capstone-sys-0.15.0/.cargo_vcs_info.json0000644000000001520000000000100135450ustar { "git": { "sha1": "8d61ed4b23890f35b46be620a7246c25a84e3d80" }, "path_in_vcs": "capstone-sys" }capstone-sys-0.15.0/CHANGELOG.md000064400000000000000000000076110072674642500142050ustar 00000000000000# Changelog All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). ## UNRELEASED - YYYY-MM-DD ### Fixed - Document that minimum supported Rust version is actually 1.50.0 - Improperly documented as 1.40.0 in 0.14.0 release ## [0.14.0] - 2021-08-09 ### Added - Compile WASM support ### Changed - Bump bindgen version to 0.59.1 ## [0.13.0] - 2021-07-13 ### Added - Support for RISC-V architecture ### Changed - Upgraded bundled capstone to from [a42f9fa9 to f278de39](https://github.com/aquynh/capstone/compare/a42f9fa9...f278de39) - Updated minimum supported Rust version to 1.40.0 ## [0.12.0] - 2021-04-09 ### Changed - Upgraded bundled capstone to from [154f91a5 to a42f9fa9](https://github.com/aquynh/capstone/compare/154f91a5...a42f9fa9) ## [0.11.0] - 2020-03-16 ### Changed - Upgraded bundled capstone to from [0cc60fb9 to 154f91a5](https://github.com/aquynh/capstone/compare/0cc60fb9...154f91a5) ## [0.10.0] - 2019-04-17 ### Changed - Upgraded bundled capstone to release 4.0 ### Removed - Capstone doc and IDE folders ## [0.9.1] - 2018-09-20 ### Changed - Upgraded bundled capstone to release [3.0.5](https://github.com/aquynh/capstone/releases/tag/3.0.5) (Git commit [a31b5328 to db19431d](https://github.com/aquynh/capstone/compare/a31b5328...db19431d)). ## [0.9.0] - 2018-07-08 ### Changed - Upgraded bundled capstone from [7e004bd4 to a31b5328](https://github.com/aquynh/capstone/compare/7e004bd4...a31b5328), which incorporates upstream Capstone PR [#1171](https://github.com/aquynh/capstone/pull/1171) - Always use `cc` crate to build Capstone ### Removed - Features affecting build: `use_system_capstone`, `build_capstone_cmake`, `build_capstone_cc` - The old build features were never used and complicated the code/documentation ## [0.8.0] - 2018-06-02 ### Added - Documented FreeBSD support ### Changed - Upgraded bundled capstone from [8308ace3 to 7e004bd4](https://github.com/aquynh/capstone/compare/8308ace3...7e004bd4), which incorporates upstream Capstone PRs [#1022](https://github.com/aquynh/capstone/pull/1022) and [#1029](https://github.com/aquynh/capstone/pull/1029) ### Removed - Unicode characters from README ## [0.7.0] - 2018-03-25 ### Added - Added support for Windows with `cc` crate - Explicitly document supported platforms ### Changed - Changed method bindgen uses to create enum types (depends on type; see API documentation) - Updated bindgen version ## [0.6.0] - 2017-10-22 ### Added - Added support for Mac OS - Added more CI tests ## [0.5.0] - 2017-08-31 ### Added - Add documentation for some types and function ### Changed - Use Rust unions instead of `bindgen` unions - Depend on necessary packages only - Use pre-generated bindings by default (instead of running `bindgen`) ### Removed - Dependency [0.14.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.13.0...capstone-sys-v0.14.0 [0.13.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.12.0...capstone-sys-v0.13.0 [0.12.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.11.0...capstone-sys-v0.12.0 [0.11.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.10.0...capstone-sys-v0.11.0 [0.10.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.9.1...capstone-sys-v0.10.0 [0.9.1]: https://github.com/capstone-rust/capstone-sys/compare/v0.9.0...v0.9.1 [0.9.0]: https://github.com/capstone-rust/capstone-sys/compare/v0.8.0...v0.9.0 [0.8.0]: https://github.com/capstone-rust/capstone-sys/compare/v0.7.0...v0.8.0 [0.7.0]: https://github.com/capstone-rust/capstone-sys/compare/v0.6.0...v0.7.0 [0.6.0]: https://github.com/capstone-rust/capstone-sys/compare/v0.5.0...v0.6.0 [0.5.0]: https://github.com/capstone-rust/capstone-sys/releases/tag/v0.5.0 capstone-sys-0.15.0/Cargo.toml0000644000000025330000000000100115500ustar # THIS FILE IS AUTOMATICALLY GENERATED BY CARGO # # When uploading crates to the registry Cargo will automatically # "normalize" Cargo.toml files for maximal compatibility # with all versions of Cargo and also rewrite `path` dependencies # to registry (e.g., crates.io) dependencies. # # If you are reading this file be aware that the original Cargo.toml # will likely look very different (and much more reasonable). # See Cargo.toml.orig for the original contents. [package] edition = "2018" name = "capstone-sys" version = "0.15.0" authors = [ "m4b ", "tmfink ", ] build = "build.rs" links = "capstone" exclude = [ "/capstone/docs/**", "/capstone/msvc/**", "/capstone/xcode/**", ] description = "System bindings to the capstone disassembly library" readme = "README.md" keywords = ["disassemble"] categories = ["external-ffi-bindings"] license = "MIT" repository = "https://github.com/capstone-rust/capstone-rs/tree/master/capstone-sys" [dependencies.libc] version = "0.2.59" default-features = false [build-dependencies.bindgen] version = "0.59.1" optional = true [build-dependencies.cc] version = "1.0" [build-dependencies.regex] version = "1.3.1" optional = true [features] default = [] use_bindgen = [ "bindgen", "regex", ] [badges.travis-ci] repository = "capstone-rust/capstone-sys" capstone-sys-0.15.0/Cargo.toml.orig0000644000000017130000000000100125060ustar [package] name = "capstone-sys" version = "0.15.0" authors = ["m4b ", "tmfink "] description = "System bindings to the capstone disassembly library" build = "build.rs" keywords = ["disassemble"] categories = ["external-ffi-bindings"] links = "capstone" license = "MIT" readme = "README.md" repository = "https://github.com/capstone-rust/capstone-rs/tree/master/capstone-sys" edition = "2018" exclude = [ "/capstone/docs/**", "/capstone/msvc/**", "/capstone/xcode/**", ] [badges] travis-ci = { repository = "capstone-rust/capstone-sys" } [dependencies] libc = { version = "0.2.59", default-features = false } [build-dependencies] bindgen = { optional = true, version = "0.59.1" } regex = { optional = true, version = "1.3.1" } cc = "1.0" [features] # use pre-generated bindings instead of dynamically with bindgen default = [] use_bindgen = ["bindgen", "regex"] # Dynamically generate bindings with bindgen capstone-sys-0.15.0/Cargo.toml.orig000064400000000000000000000017130072674642500152600ustar 00000000000000[package] name = "capstone-sys" version = "0.15.0" authors = ["m4b ", "tmfink "] description = "System bindings to the capstone disassembly library" build = "build.rs" keywords = ["disassemble"] categories = ["external-ffi-bindings"] links = "capstone" license = "MIT" readme = "README.md" repository = "https://github.com/capstone-rust/capstone-rs/tree/master/capstone-sys" edition = "2018" exclude = [ "/capstone/docs/**", "/capstone/msvc/**", "/capstone/xcode/**", ] [badges] travis-ci = { repository = "capstone-rust/capstone-sys" } [dependencies] libc = { version = "0.2.59", default-features = false } [build-dependencies] bindgen = { optional = true, version = "0.59.1" } regex = { optional = true, version = "1.3.1" } cc = "1.0" [features] # use pre-generated bindings instead of dynamically with bindgen default = [] use_bindgen = ["bindgen", "regex"] # Dynamically generate bindings with bindgen capstone-sys-0.15.0/LICENSE000064400000000000000000000020410072674642500133710ustar 00000000000000MIT License Copyright (c) 2016 Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. capstone-sys-0.15.0/README.md000064400000000000000000000035000072674642500136440ustar 00000000000000# capstone-sys Low-level, unsafe Rust bindings for the [`Capstone`][capstone] disassembly library. [capstone]: https://github.com/aquynh/capstone [![Crates.io Badge](https://img.shields.io/crates/v/capstone-sys.svg)](https://crates.io/crates/capstone-sys) [![Travis CI Badge](https://travis-ci.org/capstone-rust/capstone-sys.svg?branch=master)](https://travis-ci.org/capstone-rust/capstone-sys) [![Appveyor CI Badge](https://ci.appveyor.com/api/projects/status/github/capstone-rust/capstone-sys?svg=true&branch=master)](https://ci.appveyor.com/project/tmfink/capstone-sys) **[API Documentation](https://docs.rs/capstone-sys/)** **NOTE**: We recommend against using this crate directly. Instead, consider using [capstone-rs](https://github.com/capstone-rust/capstone-rs), which provides a high-level, "Rusty" interface. ## Requirements * Rust version >= 1.50.0 * A toolchain capable of compiling Capstone - We build the bundled Capstone with the [`cc` crate](https://github.com/alexcrichton/cc-rs) [Rust unions]: https://doc.rust-lang.org/stable/reference/items/unions.html ### Supported Platforms | Platform | Supported | | -------------------------- | -- | | `x86_64-apple-darwin` | X | | `i686-apple-darwin` | X | | `x86_64-pc-windows-msvc` | X | | `x86_64-pc-windows-gnu` | X | | `i686-pc-windows-msvc` | X | | `i686-pc-windows-gnu` | X | | `x86_64-unknown-linux-gnu` | X | | `i686-unknown-linux-gnu` | X | | `x86_64-unknown-freebsd` | X | ## Features You can specify the following [features](https://doc.rust-lang.org/cargo/reference/manifest.html#the-features-section) in `Cargo.toml`: * `use_bindgen`: instead of using the pre-generated Capstone bindings, dynamically generate bindings with [`bindgen`][bindgen]. [bindgen]: https://github.com/rust-lang-nursery/rust-bindgen capstone-sys-0.15.0/build.rs000064400000000000000000000302240072674642500140350ustar 00000000000000//! The following environment variables affect the build: //! //! * `UPDATE_CAPSTONE_BINDINGS`: setting indicates that the pre-generated `capstone.rs` should be //! updated with the output bindgen //! //! # Bindgen enum mapping //! //! Bindgen can convert C enums in several ways: //! //! 1. **"Rustified" enum**: Bindgen creates a Rust enum, which provides the most "type safety" and //! reduces the chance of confusing variants for a different type. For variants whose //! discriminant values are not distinct, bindgen defines constants. //! 2. **"Constified" enum**: Bindgen defines constants for each enum variant. //! 3. **"Constified" enum module**: Bindgen defines constants for each enum variant in a separate //! module. //! //! # Rationale for enum types //! //! Rustified enum: these have distinct variant discriminants //! //! * `cs_arch` //! * `cs_op_type` //! * `cs_opt_type` //! //! Constified enum module: //! //! * `cs_err`: avoid undefined behavior in case an error is instantiated with an invalid value; the //! compiler could make false assumptions that the value is only within a certain range. //! * `cs_group_type`/`ARCH_insn_group`: each architecture adds group types to the `cs_group_type`, //! so we constify to avoid needing to transmute. //! * `cs_mode`: used as a bitmask; when values are OR'd together, they are not a valid discriminant //! value //! * `cs_opt_value`/`ARCH_reg`: variant discriminants are not unique //! //! Bitfield enum: fields are OR'd together to form new values //! * `cs_mode` #[cfg(feature = "use_bindgen")] extern crate bindgen; extern crate cc; #[cfg(feature = "use_bindgen")] extern crate regex; #[cfg(feature = "use_bindgen")] use { regex::Regex, std::{fs::File, io::Write}, }; use std::env; use std::fs::copy; use std::path::PathBuf; include!("common.rs"); const CAPSTONE_DIR: &str = "capstone"; /// Indicates how capstone library should be linked #[allow(dead_code)] enum LinkType { Dynamic, Static, } /// Build capstone using the cc crate fn build_capstone_cc() { use std::fs::DirEntry; fn read_dir_and_filter bool>(dir: &str, filter: F) -> Vec { use std::fs::read_dir; read_dir(dir) .expect("Failed to read capstone source directory") .into_iter() .map(|e| e.expect("Failed to read capstone source directory")) .filter(|e| filter(e)) .map(|e| { format!( "{}/{}", dir, e.file_name().to_str().expect("Invalid filename") ) }) .collect() } fn find_c_source_files(dir: &str) -> Vec { read_dir_and_filter(dir, |e| { let file_type = e .file_type() .expect("Failed to read capstone source directory"); let file_name = e.file_name().into_string().expect("Invalid filename"); file_type.is_file() && (file_name.ends_with(".c") || file_name.ends_with(".C")) }) } fn find_arch_dirs() -> Vec { read_dir_and_filter(&format!("{}/{}", CAPSTONE_DIR, "arch"), |e| { let file_type = e .file_type() .expect("Failed to read capstone source directory"); file_type.is_dir() }) } let mut files = find_c_source_files(CAPSTONE_DIR); for arch_dir in find_arch_dirs().into_iter() { files.append(&mut find_c_source_files(&arch_dir)); } let use_static_crt = { let target_features = env::var("CARGO_CFG_TARGET_FEATURE").unwrap_or_default(); target_features.split(',').any(|f| f == "crt-static") }; cc::Build::new() .files(files) .include(format!("{}/{}", CAPSTONE_DIR, "include")) .define("CAPSTONE_USE_SYS_DYN_MEM", None) .define("CAPSTONE_HAS_ARM", None) .define("CAPSTONE_HAS_ARM64", None) .define("CAPSTONE_HAS_EVM", None) .define("CAPSTONE_HAS_M680X", None) .define("CAPSTONE_HAS_M68K", None) .define("CAPSTONE_HAS_MIPS", None) .define("CAPSTONE_HAS_POWERPC", None) .define("CAPSTONE_HAS_RISCV", None) .define("CAPSTONE_HAS_SPARC", None) .define("CAPSTONE_HAS_SYSZ", None) .define("CAPSTONE_HAS_TMS320C64X", None) .define("CAPSTONE_HAS_WASM", None) .define("CAPSTONE_HAS_X86", None) .define("CAPSTONE_HAS_XCORE", None) .flag_if_supported("-Wno-unused-function") .flag_if_supported("-Wno-unused-parameter") .flag_if_supported("-Wno-unknown-pragmas") .flag_if_supported("-Wno-sign-compare") .flag_if_supported("-Wno-return-type") .flag_if_supported("-Wno-implicit-fallthrough") .flag_if_supported("-Wno-missing-field-initializers") .flag_if_supported("-Wno-enum-conversion") .static_crt(use_static_crt) .compile("capstone"); } /// Search for header in search paths #[cfg(feature = "use_bindgen")] fn find_capstone_header(header_search_paths: &[PathBuf], name: &str) -> Option { for search_path in header_search_paths.iter() { let potential_file = search_path.join(name); if potential_file.is_file() { return Some(potential_file); } } None } /// Gets environment variable value. Panics if variable is not set. fn env_var(var: &str) -> String { env::var(var).unwrap_or_else(|_| panic!("Environment variable {} is not set", var)) } /// Parse generated bindings and impl from_insn_id() for all architectures /// instructions enum declaration. #[cfg(feature = "use_bindgen")] fn impl_insid_to_insenum(bindings: &str) -> String { let mut impl_arch_enum = String::new(); impl_arch_enum.push_str("use core::convert::From;\n"); for cs_arch in ARCH_INCLUDES { let arch = cs_arch.cs_name(); // find architecture instructions enum declaration let re_enum_def = Regex::new(&format!("pub enum {}_insn (?s)\\{{.*?\\}}", arch)) .expect("Unable to compile regex"); let cap_enum_def = &re_enum_def .captures(bindings) .expect("Unable to capture group")[0]; // find instructions and their id let re_ins_ids = Regex::new(&format!( "{}_INS_(?P[A-Z0-9_]+) = (?P\\d+)", &arch.to_uppercase() )) .expect("Unable to compile regex"); impl_arch_enum.push_str(&format!( "impl From for {}_insn {{\n fn from(id: u32) -> Self {{\n match id {{\n", &arch )); // fill match expression for cap_ins_id in re_ins_ids.captures_iter(cap_enum_def) { impl_arch_enum.push_str(&format!( "{} => {}_insn::{}_INS_{},\n", &cap_ins_id["id"], &arch, &arch.to_uppercase(), &cap_ins_id["ins"] )); } // if id didn't match, return [arch]_INS_INVALID. // special case for m680x which has 'INVLD' variant instead of 'INVALID' match arch { "m680x" => { impl_arch_enum.push_str(&format!( "_ => {}_insn::{}_INS_INVLD,", &arch, &arch.to_uppercase() )); } _ => { impl_arch_enum.push_str(&format!( "_ => {}_insn::{}_INS_INVALID,", &arch, &arch.to_uppercase() )); } } impl_arch_enum.push_str("}\n}\n}\n"); } impl_arch_enum } /// Create bindings using bindgen #[cfg(feature = "use_bindgen")] fn write_bindgen_bindings( header_search_paths: &[PathBuf], update_pregenerated_bindings: bool, pregenerated_bindgen_header: PathBuf, pregenerated_bindgen_impl: PathBuf, out_bindings_path: PathBuf, out_impl_path: PathBuf, ) { let mut builder = bindgen::Builder::default() .rust_target(bindgen::RustTarget::Stable_1_19) .size_t_is_usize(true) .use_core() .ctypes_prefix("libc") .header( find_capstone_header(header_search_paths, "capstone.h") .expect("Could not find header") .to_str() .unwrap(), ) .disable_name_namespacing() .prepend_enum_name(false) .generate_comments(true) .layout_tests(false) // eliminate test failures on platforms with different pointer sizes .impl_debug(true) .constified_enum_module("cs_err|cs_group_type|cs_opt_value") .bitfield_enum("cs_mode|cs_ac_type") .rustified_enum(".*") .no_copy("cs_insn"); // Whitelist cs_.* functions and types let pattern = String::from("cs_.*"); builder = builder .allowlist_function(&pattern) .allowlist_type(&pattern); // Whitelist types with architectures for arch in ARCH_INCLUDES { // .*(^|_)ARCH(_|$).* let arch_type_pattern = format!(".*(^|_){}(_|$).*", arch.cs_name); let const_mod_pattern = format!("^{}_(reg|insn_group)$", arch.cs_name); builder = builder .allowlist_type(&arch_type_pattern) .constified_enum_module(&const_mod_pattern); } let bindings = builder.generate().expect("Unable to generate bindings"); // Write bindings to $OUT_DIR/bindings.rs bindings .write_to_file(&out_bindings_path) .expect("Unable to write bindings"); // Parse bindings and impl fn to cast u32 to _insn, write output to file let bindings_impl_str = impl_insid_to_insenum(&bindings.to_string()); let mut bindings_impl = File::create(&out_impl_path).expect("Unable to open file"); bindings_impl .write_all(bindings_impl_str.as_bytes()) .expect("Unable to write file"); if update_pregenerated_bindings { copy(out_bindings_path, pregenerated_bindgen_header) .expect("Unable to update capstone bindings"); copy(out_impl_path, pregenerated_bindgen_impl).expect("Unable to update capstone bindings"); } } fn main() { #[allow(unused_assignments)] let mut link_type: Option = None; // C header search paths let mut header_search_paths: Vec = Vec::new(); build_capstone_cc(); header_search_paths.push([CAPSTONE_DIR, "include", "capstone"].iter().collect()); link_type = Some(LinkType::Static); match link_type.expect("Must specify link type") { LinkType::Dynamic => { println!("cargo:rustc-link-lib=dylib=capstone"); } LinkType::Static => { println!("cargo:rustc-link-lib=static=capstone"); } } // If UPDATE_CAPSTONE_BINDINGS is set, then updated the pre-generated capstone bindings let update_pregenerated_bindings = env::var("UPDATE_CAPSTONE_BINDINGS").is_ok(); if update_pregenerated_bindings && !cfg!(feature = "use_bindgen") { panic!( "Setting UPDATE_CAPSTONE_BINDINGS only makes sense when enabling feature \"use_bindgen\""); } let pregenerated_bindgen_header: PathBuf = [ env_var("CARGO_MANIFEST_DIR"), "pre_generated".into(), BINDINGS_FILE.into(), ] .iter() .collect(); let pregenerated_bindgen_impl: PathBuf = [ env_var("CARGO_MANIFEST_DIR"), "pre_generated".into(), BINDINGS_IMPL_FILE.into(), ] .iter() .collect(); let out_bindings_path = PathBuf::from(env_var("OUT_DIR")).join(BINDINGS_FILE); let out_impl_path = PathBuf::from(env_var("OUT_DIR")).join(BINDINGS_IMPL_FILE); // Only run bindgen if we are *not* using the bundled capstone bindings #[cfg(feature = "use_bindgen")] write_bindgen_bindings( &header_search_paths, update_pregenerated_bindings, pregenerated_bindgen_header, pregenerated_bindgen_impl, out_bindings_path, out_impl_path, ); // Otherwise, copy the pregenerated bindings #[cfg(not(feature = "use_bindgen"))] { copy(&pregenerated_bindgen_header, &out_bindings_path) .expect("Unable to update capstone bindings"); copy(&pregenerated_bindgen_impl, &out_impl_path) .expect("Unable to update capstone bindings"); } } capstone-sys-0.15.0/capstone/.appveyor.yml000064400000000000000000000004120072674642500166460ustar 00000000000000version: 4.0-{build} os: - Visual Studio 2015 before_build: - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 build_script: - mkdir build - cd build - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. - nmake capstone-sys-0.15.0/capstone/.clang-format000064400000000000000000000002060072674642500165540ustar 00000000000000BraceWrapping: AfterClass: true AfterControlStatement: false AfterFunction: true BreakBeforeBraces: Custom UseTab: Alwayscapstone-sys-0.15.0/capstone/.editorconfig000064400000000000000000000003610072674642500166600ustar 00000000000000root = true [*] end_of_line = lf insert_final_newline = true [*.{py,pyx,pxd}] indent_style = space indent_size = 4 # Follow Linux kernel coding style [*.{c,h,cpp,hpp,inc}] indent_style = tab indent_size = 8 [Makefile] indent_style = tab capstone-sys-0.15.0/capstone/.gitattributes000064400000000000000000000000430072674642500170730ustar 00000000000000/arch/**/*.inc linguist-language=C capstone-sys-0.15.0/capstone/.github/workflows/fuzz.yml000064400000000000000000000011350072674642500213210ustar 00000000000000name: CIFuzz on: [pull_request] jobs: Fuzzing: runs-on: ubuntu-latest steps: - name: Build Fuzzers uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master with: oss-fuzz-project-name: 'capstone' dry-run: false - name: Run Fuzzers uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master with: oss-fuzz-project-name: 'capstone' fuzz-seconds: 600 dry-run: false - name: Upload Crash uses: actions/upload-artifact@v1 if: failure() with: name: artifacts path: ./out/artifacts capstone-sys-0.15.0/capstone/.gitignore000064400000000000000000000034010072674642500161710ustar 00000000000000.DS_Store # Object files *.o *.ko # Gcc dependency-tracking files *.d # Libraries *.lib *.a # Shared objects (inc. Windows DLLs) *.dll *.so *.so.* *.dylib # Executables *.exe *.out *.app # python bindings/python/build/ bindings/python/capstone.egg-info/ *.pyc # java bindings/java/capstone.jar # ocaml bindings/ocaml/*.cmi bindings/ocaml/*.cmx bindings/ocaml/*.cmxa bindings/ocaml/*.mli bindings/ocaml/test bindings/ocaml/test_arm bindings/ocaml/test_arm64 bindings/ocaml/test_basic bindings/ocaml/test_mips bindings/ocaml/test_x86 bindings/ocaml/test_detail bindings/ocaml/test_ppc bindings/ocaml/test_sparc bindings/ocaml/test_systemz bindings/ocaml/test_xcore bindings/ocaml/test_m680x # test binaries tests/test_basic tests/test_detail tests/test_iter tests/test_arm tests/test_arm64 tests/test_mips tests/test_x86 tests/test_ppc tests/test_skipdata tests/test_sparc tests/test_systemz tests/test_xcore tests/*.static tests/test_customized_mnem tests/test_m68k tests/test_tms320c64x tests/test_m680x tests/test_evm tests/test_wasm tests/test_mos65xx tests/test_bpf tests/test_riscv # regress binaries suite/regress/invalid_read_in_print_operand # vim tmp file *.swp *~ capstone.pc # local files _* # freebsd ports: generated file with "make makesum" command packages/freebsd/ports/devel/capstone/distinfo # VisualStudio ProjectUpgradeLog.log Debug/ Release/ ipch/ build*/ *.sdf *.opensdf *.suo *.user *.backup *.VC.db *.VC.opendb .vscode/ # CMake build directories build*/ # Xcode xcode/Capstone.xcodeproj/xcuserdata xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata # suite/ test_arm_regression test_arm_regression.o fuzz_harness test_iter_benchmark fuzz_bindisasm fuzz_disasm fuzz_decode_platform capstone_get_setup *.s cstool/cstool # android android-ndk-* capstone-sys-0.15.0/capstone/.travis.yml000064400000000000000000000060400072674642500163140ustar 00000000000000language: cpp sudo: false before_install: - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH before_script: - wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip - unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz # TODO remove built in cmocka compile and use system cmocka (including brewfile) once xenial is default - git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka - chmod +x suite/cstest/build_cstest.sh - if [[ ${TRAVIS_OS_NAME} = linux ]]; then export PATH="/usr/lib/llvm-9/bin:${PATH}"; fi script: - ./make.sh - make check - sudo make install - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi - if [[ "$NOPYTEST" != "true" ]]; then cd bindings/python && make check; cd ../..; fi - if [[ "$NOPYTEST" != "true" ]]; then cd suite/cstest && ./build_cstest.sh; fi - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -d ../MC; fi - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -f issues.cs; fi - if [ -n "$QA_FUZZIT" ]; then suite/fuzz/fuzzit.sh; fi compiler: - clang - gcc os: - linux - osx matrix: include: - name: xenial gcc os: linux dist: xenial compiler: gcc addons: apt: packages: - libcmocka-dev - name: xenial clang os: linux dist: xenial compiler: clang addons: apt: packages: - libcmocka-dev - name: fuzza env: ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=address" NOPYTEST=true QA_FUZZIT=asan compiler: clang os: linux - name: fuzzm env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=memory" NOPYTEST=true QA_FUZZIT=msan compiler: clang os: linux - name: fuzzu env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fno-sanitize-recover=undefined,integer -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=undefined" NOPYTEST=true QA_FUZZIT=ubsan compiler: clang os: linux addons: apt: sources: - llvm-toolchain-trusty - ubuntu-toolchain-r-test packages: - clang-9 capstone-sys-0.15.0/capstone/CMakeLists.txt000064400000000000000000000560040072674642500167500ustar 00000000000000cmake_minimum_required(VERSION 2.6) project(capstone) set(VERSION_MAJOR 5) set(VERSION_MINOR 0) set(VERSION_PATCH 0) if(POLICY CMP0042) # http://www.cmake.org/cmake/help/v3.0/policy/CMP0042.html cmake_policy(SET CMP0042 NEW) endif(POLICY CMP0042) if (POLICY CMP0048) # use old policy to honor version set using VERSION_* variables to preserve backwards # compatibility. change OLD to NEW when minimum cmake version is updated to 3.* and # set VERSION using project(capstone VERSION 4.0.0). # http://www.cmake.org/cmake/help/v3.0/policy/CMP0048.html cmake_policy (SET CMP0048 OLD) endif() # to configure the options specify them in in the command line or change them in the cmake UI. # Don't edit the makefile! option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ON) option(CAPSTONE_BUILD_STATIC "Build static library" ON) option(CAPSTONE_BUILD_SHARED "Build shared library" ON) option(CAPSTONE_BUILD_DIET "Build diet library" OFF) option(CAPSTONE_BUILD_TESTS "Build tests" ON) option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON) option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON) option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF) option(CAPSTONE_INSTALL "Generate install target" OFF) set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV) set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV) list(LENGTH SUPPORTED_ARCHITECTURES count) math(EXPR count "${count}-1") # create options controlling whether support for a particular architecture is needed foreach(i RANGE ${count}) list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture) list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label) option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ${CAPSTONE_ARCHITECTURE_DEFAULT}) endforeach(i) # propagate architecture support variables to preprocessor foreach(supported_architecture ${SUPPORTED_ARCHITECTURES}) set(option_name "CAPSTONE_${supported_architecture}_SUPPORT") if(${option_name}) message("Enabling ${option_name}") add_definitions("-D${option_name}") endif() endforeach(supported_architecture) option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF) option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF) option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF) if (MSVC) set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MT") set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd") endif () enable_testing() if (CAPSTONE_BUILD_DIET) add_definitions(-DCAPSTONE_DIET) endif () if (CAPSTONE_USE_DEFAULT_ALLOC) add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM) endif () if (CAPSTONE_X86_REDUCE) add_definitions(-DCAPSTONE_X86_REDUCE) endif () if (CAPSTONE_X86_ATT_DISABLE) add_definitions(-DCAPSTONE_X86_ATT_DISABLE) endif () if (CAPSTONE_DEBUG) add_definitions(-DCAPSTONE_DEBUG) endif () ## sources set(SOURCES_ENGINE cs.c MCInst.c MCInstrDesc.c MCRegisterInfo.c SStream.c utils.c ) set(HEADERS_ENGINE cs_priv.h LEB128.h MathExtras.h MCDisassembler.h MCFixedLenDisassembler.h MCInst.h MCInstrDesc.h MCRegisterInfo.h SStream.h utils.h ) set(HEADERS_COMMON include/capstone/arm64.h include/capstone/arm.h include/capstone/capstone.h include/capstone/evm.h include/capstone/wasm.h include/capstone/mips.h include/capstone/ppc.h include/capstone/x86.h include/capstone/sparc.h include/capstone/systemz.h include/capstone/xcore.h include/capstone/m68k.h include/capstone/tms320c64x.h include/capstone/m680x.h include/capstone/mos65xx.h include/capstone/bpf.h include/capstone/riscv.h include/capstone/platform.h ) set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) ## architecture support if (CAPSTONE_ARM_SUPPORT) add_definitions(-DCAPSTONE_HAS_ARM) set(SOURCES_ARM arch/ARM/ARMDisassembler.c arch/ARM/ARMInstPrinter.c arch/ARM/ARMMapping.c arch/ARM/ARMModule.c ) set(HEADERS_ARM arch/ARM/ARMAddressingModes.h arch/ARM/ARMBaseInfo.h arch/ARM/ARMDisassembler.h arch/ARM/ARMInstPrinter.h arch/ARM/ARMMapping.h arch/ARM/ARMGenAsmWriter.inc arch/ARM/ARMGenDisassemblerTables.inc arch/ARM/ARMGenInstrInfo.inc arch/ARM/ARMGenRegisterInfo.inc arch/ARM/ARMGenSubtargetInfo.inc arch/ARM/ARMMappingInsn.inc arch/ARM/ARMMappingInsnOp.inc arch/ARM/ARMGenRegisterName.inc arch/ARM/ARMGenRegisterName_digit.inc arch/ARM/ARMGenSystemRegister.inc arch/ARM/ARMMappingInsnName.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_arm.c) endif () if (CAPSTONE_ARM64_SUPPORT) add_definitions(-DCAPSTONE_HAS_ARM64) set(SOURCES_ARM64 arch/AArch64/AArch64BaseInfo.c arch/AArch64/AArch64Disassembler.c arch/AArch64/AArch64InstPrinter.c arch/AArch64/AArch64Mapping.c arch/AArch64/AArch64Module.c ) set(HEADERS_ARM64 arch/AArch64/AArch64AddressingModes.h arch/AArch64/AArch64BaseInfo.h arch/AArch64/AArch64Disassembler.h arch/AArch64/AArch64InstPrinter.h arch/AArch64/AArch64Mapping.h arch/AArch64/AArch64GenAsmWriter.inc arch/AArch64/AArch64GenDisassemblerTables.inc arch/AArch64/AArch64GenInstrInfo.inc arch/AArch64/AArch64GenRegisterInfo.inc arch/AArch64/AArch64GenRegisterName.inc arch/AArch64/AArch64GenRegisterV.inc arch/AArch64/AArch64GenSubtargetInfo.inc arch/AArch64/AArch64GenSystemOperands.inc arch/AArch64/AArch64GenSystemOperands_enum.inc arch/AArch64/AArch64MappingInsn.inc arch/AArch64/AArch64MappingInsnName.inc arch/AArch64/AArch64MappingInsnOp.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c) endif () if (CAPSTONE_MIPS_SUPPORT) add_definitions(-DCAPSTONE_HAS_MIPS) set(SOURCES_MIPS arch/Mips/MipsDisassembler.c arch/Mips/MipsInstPrinter.c arch/Mips/MipsMapping.c arch/Mips/MipsModule.c ) set(HEADERS_MIPS arch/Mips/MipsDisassembler.h arch/Mips/MipsGenAsmWriter.inc arch/Mips/MipsGenDisassemblerTables.inc arch/Mips/MipsGenInstrInfo.inc arch/Mips/MipsGenRegisterInfo.inc arch/Mips/MipsGenSubtargetInfo.inc arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h arch/Mips/MipsMappingInsn.inc ) set(HEADERS_MIPS arch/Mips/MipsDisassembler.h arch/Mips/MipsGenAsmWriter.inc arch/Mips/MipsGenDisassemblerTables.inc arch/Mips/MipsGenInstrInfo.inc arch/Mips/MipsGenRegisterInfo.inc arch/Mips/MipsGenSubtargetInfo.inc arch/Mips/MipsInstPrinter.h arch/Mips/MipsMapping.h ) set(TEST_SOURCES ${TEST_SOURCES} test_mips.c) endif () if (CAPSTONE_PPC_SUPPORT) add_definitions(-DCAPSTONE_HAS_POWERPC) set(SOURCES_PPC arch/PowerPC/PPCDisassembler.c arch/PowerPC/PPCInstPrinter.c arch/PowerPC/PPCMapping.c arch/PowerPC/PPCModule.c ) set(HEADERS_PPC arch/PowerPC/PPCDisassembler.h arch/PowerPC/PPCGenAsmWriter.inc arch/PowerPC/PPCInstPrinter.h arch/PowerPC/PPCMapping.h arch/PowerPC/PPCPredicates.h arch/PowerPC/PPCGenAsmWriter.inc arch/PowerPC/PPCGenRegisterName.inc arch/PowerPC/PPCGenDisassemblerTables.inc arch/PowerPC/PPCMappingInsn.inc arch/PowerPC/PPCMappingInsnName.inc arch/PowerPC/PPCGenSubtargetInfo.inc arch/PowerPC/PPCGenRegisterInfo.inc arch/PowerPC/PPCGenInstrInfo.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c) endif () if (CAPSTONE_X86_SUPPORT) add_definitions(-DCAPSTONE_HAS_X86) set(SOURCES_X86 arch/X86/X86Disassembler.c arch/X86/X86DisassemblerDecoder.c arch/X86/X86IntelInstPrinter.c arch/X86/X86InstPrinterCommon.c arch/X86/X86Mapping.c arch/X86/X86Module.c ) set(HEADERS_X86 arch/X86/X86BaseInfo.h arch/X86/X86Disassembler.h arch/X86/X86DisassemblerDecoder.h arch/X86/X86DisassemblerDecoderCommon.h arch/X86/X86GenAsmWriter.inc arch/X86/X86GenAsmWriter1.inc arch/X86/X86GenAsmWriter1_reduce.inc arch/X86/X86GenAsmWriter_reduce.inc arch/X86/X86GenDisassemblerTables.inc arch/X86/X86GenDisassemblerTables_reduce.inc arch/X86/X86GenInstrInfo.inc arch/X86/X86GenInstrInfo_reduce.inc arch/X86/X86GenRegisterInfo.inc arch/X86/X86InstPrinter.h arch/X86/X86Mapping.h arch/X86/X86MappingInsn.inc arch/X86/X86MappingInsnOp.inc arch/X86/X86MappingInsnOp_reduce.inc arch/X86/X86MappingInsn_reduce.inc ) set(HEADERS_X86 arch/X86/X86BaseInfo.h arch/X86/X86Disassembler.h arch/X86/X86DisassemblerDecoder.h arch/X86/X86DisassemblerDecoderCommon.h arch/X86/X86GenAsmWriter.inc arch/X86/X86GenAsmWriter1.inc arch/X86/X86GenAsmWriter1_reduce.inc arch/X86/X86GenAsmWriter_reduce.inc arch/X86/X86GenDisassemblerTables.inc arch/X86/X86GenDisassemblerTables_reduce.inc arch/X86/X86GenInstrInfo.inc arch/X86/X86GenInstrInfo_reduce.inc arch/X86/X86GenRegisterInfo.inc arch/X86/X86InstPrinter.h arch/X86/X86Mapping.h ) if (NOT CAPSTONE_BUILD_DIET) set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c) endif () set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c) endif () if (CAPSTONE_SPARC_SUPPORT) add_definitions(-DCAPSTONE_HAS_SPARC) set(SOURCES_SPARC arch/Sparc/SparcDisassembler.c arch/Sparc/SparcInstPrinter.c arch/Sparc/SparcMapping.c arch/Sparc/SparcModule.c ) set(HEADERS_SPARC arch/Sparc/Sparc.h arch/Sparc/SparcDisassembler.h arch/Sparc/SparcGenAsmWriter.inc arch/Sparc/SparcGenDisassemblerTables.inc arch/Sparc/SparcGenInstrInfo.inc arch/Sparc/SparcGenRegisterInfo.inc arch/Sparc/SparcGenSubtargetInfo.inc arch/Sparc/SparcInstPrinter.h arch/Sparc/SparcMapping.h arch/Sparc/SparcMappingInsn.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c) endif () if (CAPSTONE_SYSZ_SUPPORT) add_definitions(-DCAPSTONE_HAS_SYSZ) set(SOURCES_SYSZ arch/SystemZ/SystemZDisassembler.c arch/SystemZ/SystemZInstPrinter.c arch/SystemZ/SystemZMapping.c arch/SystemZ/SystemZModule.c arch/SystemZ/SystemZMCTargetDesc.c ) set(HEADERS_SYSZ arch/SystemZ/SystemZDisassembler.h arch/SystemZ/SystemZGenAsmWriter.inc arch/SystemZ/SystemZGenDisassemblerTables.inc arch/SystemZ/SystemZGenInsnNameMaps.inc arch/SystemZ/SystemZGenInstrInfo.inc arch/SystemZ/SystemZGenRegisterInfo.inc arch/SystemZ/SystemZGenSubtargetInfo.inc arch/SystemZ/SystemZInstPrinter.h arch/SystemZ/SystemZMapping.h arch/SystemZ/SystemZMappingInsn.inc arch/SystemZ/SystemZMCTargetDesc.h ) set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c) endif () if (CAPSTONE_XCORE_SUPPORT) add_definitions(-DCAPSTONE_HAS_XCORE) set(SOURCES_XCORE arch/XCore/XCoreDisassembler.c arch/XCore/XCoreInstPrinter.c arch/XCore/XCoreMapping.c arch/XCore/XCoreModule.c ) set(HEADERS_XCORE arch/XCore/XCoreDisassembler.h arch/XCore/XCoreGenAsmWriter.inc arch/XCore/XCoreGenDisassemblerTables.inc arch/XCore/XCoreGenInstrInfo.inc arch/XCore/XCoreGenRegisterInfo.inc arch/XCore/XCoreInstPrinter.h arch/XCore/XCoreMapping.h arch/XCore/XCoreMappingInsn.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c) endif () if (CAPSTONE_M68K_SUPPORT) add_definitions(-DCAPSTONE_HAS_M68K) set(SOURCES_M68K arch/M68K/M68KDisassembler.c arch/M68K/M68KInstPrinter.c arch/M68K/M68KModule.c ) set(HEADERS_M68K arch/M68K/M68KDisassembler.h ) set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c) endif () if (CAPSTONE_TMS320C64X_SUPPORT) add_definitions(-DCAPSTONE_HAS_TMS320C64X) set(SOURCES_TMS320C64X arch/TMS320C64x/TMS320C64xDisassembler.c arch/TMS320C64x/TMS320C64xInstPrinter.c arch/TMS320C64x/TMS320C64xMapping.c arch/TMS320C64x/TMS320C64xModule.c ) set(HEADERS_TMS320C64X arch/TMS320C64x/TMS320C64xDisassembler.h arch/TMS320C64x/TMS320C64xGenAsmWriter.inc arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc arch/TMS320C64x/TMS320C64xGenInstrInfo.inc arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc arch/TMS320C64x/TMS320C64xInstPrinter.h arch/TMS320C64x/TMS320C64xMapping.h ) set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c) endif () if (CAPSTONE_M680X_SUPPORT) add_definitions(-DCAPSTONE_HAS_M680X) set(SOURCES_M680X arch/M680X/M680XDisassembler.c arch/M680X/M680XInstPrinter.c arch/M680X/M680XModule.c ) set(HEADERS_M680X arch/M680X/M680XInstPrinter.h arch/M680X/M680XDisassembler.h arch/M680X/M680XDisassemblerInternals.h ) set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c) endif () if (CAPSTONE_EVM_SUPPORT) add_definitions(-DCAPSTONE_HAS_EVM) set(SOURCES_EVM arch/EVM/EVMDisassembler.c arch/EVM/EVMInstPrinter.c arch/EVM/EVMMapping.c arch/EVM/EVMModule.c ) set(HEADERS_EVM arch/EVM/EVMDisassembler.h arch/EVM/EVMInstPrinter.h arch/EVM/EVMMapping.h arch/EVM/EVMMappingInsn.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_evm.c) endif () if (CAPSTONE_WASM_SUPPORT) add_definitions(-DCAPSTONE_HAS_WASM) set(SOURCES_WASM arch/WASM/WASMDisassembler.c arch/WASM/WASMInstPrinter.c arch/WASM/WASMMapping.c arch/WASM/WASMModule.c ) set(HEADERS_WASM arch/WASM/WASMDisassembler.h arch/WASM/WASMInstPrinter.h arch/WASM/WASMMapping.h ) set(TEST_SOURCES ${TEST_SOURCES} test_wasm.c) endif () if (CAPSTONE_MOS65XX_SUPPORT) add_definitions(-DCAPSTONE_HAS_MOS65XX) set(SOURCES_MOS65XX arch/MOS65XX/MOS65XXModule.c arch/MOS65XX/MOS65XXDisassembler.c) set(HEADERS_SOURCES_MOS65XX arch/MOS65XX/MOS65XXDisassembler.h ) set(TEST_SOURCES ${TEST_SOURCES} test_mos65xx.c) endif () if (CAPSTONE_BPF_SUPPORT) add_definitions(-DCAPSTONE_HAS_BPF) set(SOURCES_BPF arch/BPF/BPFDisassembler.c arch/BPF/BPFInstPrinter.c arch/BPF/BPFMapping.c arch/BPF/BPFModule.c ) set(HEADERS_BPF arch/BPF/BPFConstants.h arch/BPF/BPFDisassembler.h arch/BPF/BPFInstPrinter.h arch/BPF/BPFMapping.h arch/BPF/BPFModule.h ) set(TEST_SOURCES ${TEST_SOURCES} test_bpf.c) endif () if (CAPSTONE_RISCV_SUPPORT) add_definitions(-DCAPSTONE_HAS_RISCV) set(SOURCES_RISCV arch/RISCV/RISCVDisassembler.c arch/RISCV/RISCVInstPrinter.c arch/RISCV/RISCVMapping.c arch/RISCV/RISCVModule.c ) set(HEADERS_RISCV arch/RISCV/RISCVBaseInfo.h arch/RISCV/RISCVDisassembler.h arch/RISCV/RISCVInstPrinter.h arch/RISCV/RISCVMapping.h arch/RISCV/RISCVModule.h arch/RISCV/RISCVGenAsmWriter.inc arch/RISCV/RISCVGenDisassemblerTables.inc arch/RISCV/RISCVGenInsnNameMaps.inc arch/RISCV/RISCVGenInstrInfo.inc arch/RISCV/RISCVGenRegisterInfo.inc arch/RISCV/RISCVGenSubtargetInfo.inc arch/RISCV/RISCVMappingInsn.inc ) set(TEST_SOURCES ${TEST_SOURCES} test_riscv.c) endif () if (CAPSTONE_OSXKERNEL_SUPPORT) add_definitions(-DCAPSTONE_HAS_OSXKERNEL) endif () set(ALL_SOURCES ${SOURCES_ENGINE} ${SOURCES_ARM} ${SOURCES_ARM64} ${SOURCES_MIPS} ${SOURCES_PPC} ${SOURCES_X86} ${SOURCES_SPARC} ${SOURCES_SYSZ} ${SOURCES_XCORE} ${SOURCES_M68K} ${SOURCES_TMS320C64X} ${SOURCES_M680X} ${SOURCES_EVM} ${SOURCES_WASM} ${SOURCES_MOS65XX} ${SOURCES_BPF} ${SOURCES_RISCV} ) set(ALL_HEADERS ${HEADERS_COMMON} ${HEADERS_ENGINE} ${HEADERS_ARM} ${HEADERS_ARM64} ${HEADERS_MIPS} ${HEADERS_PPC} ${HEADERS_X86} ${HEADERS_SPARC} ${HEADERS_SYSZ} ${HEADERS_XCORE} ${HEADERS_M68K} ${HEADERS_TMS320C64X} ${HEADERS_M680X} ${HEADERS_EVM} ${HEADERS_WASM} ${HEADERS_MOS65XX} ${HEADERS_BPF} ${HEADERS_RISCV} ) include_directories("${PROJECT_SOURCE_DIR}/include") ## properties # version info set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}) ## targets if (CAPSTONE_BUILD_STATIC) add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS}) set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone) set(default-target capstone-static) endif () # Force static runtime libraries if (CAPSTONE_BUILD_STATIC_RUNTIME) FOREACH(flag CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT CMAKE_CXX_FLAGS_RELEASE CMAKE_CXX_FLAGS_RELWITHDEBINFO CMAKE_CXX_FLAGS_DEBUG CMAKE_CXX_FLAGS_DEBUG_INIT) if (MSVC) STRING(REPLACE "/MD" "/MT" "${flag}" "${${flag}}") SET("${flag}" "${${flag}} /EHsc") endif (MSVC) ENDFOREACH() endif () if (CAPSTONE_BUILD_SHARED) add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS}) set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone) set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED) if (MSVC) set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib) else() set_target_properties(capstone-shared PROPERTIES VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH} SOVERSION ${VERSION_MAJOR}) endif () if(NOT DEFINED default-target) # honor `capstone-static` for tests first. set(default-target capstone-shared) add_definitions(-DCAPSTONE_SHARED) endif () endif () if (CAPSTONE_BUILD_TESTS) foreach (TSRC ${TEST_SOURCES}) STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC}) add_executable(${TBIN} "tests/${TSRC}") target_link_libraries(${TBIN} ${default-target}) add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN}) endforeach () if (CAPSTONE_ARM_SUPPORT) set(ARM_REGRESS_TEST test_arm_regression.c) STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") target_link_libraries(${ARM_REGRESS_BIN} ${default-target}) add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN}) endif() # fuzz target built with the tests add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c suite/fuzz/platform.c) target_link_libraries(fuzz_disasm ${default-target}) endif () source_group("Source\\Engine" FILES ${SOURCES_ENGINE}) source_group("Source\\ARM" FILES ${SOURCES_ARM}) source_group("Source\\ARM64" FILES ${SOURCES_ARM64}) source_group("Source\\Mips" FILES ${SOURCES_MIPS}) source_group("Source\\PowerPC" FILES ${SOURCES_PPC}) source_group("Source\\Sparc" FILES ${SOURCES_SPARC}) source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ}) source_group("Source\\X86" FILES ${SOURCES_X86}) source_group("Source\\XCore" FILES ${SOURCES_XCORE}) source_group("Source\\M68K" FILES ${SOURCES_M68K}) source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X}) source_group("Source\\M680X" FILES ${SOURCES_M680X}) source_group("Source\\EVM" FILES ${SOURCES_EVM}) source_group("Source\\WASM" FILES ${SOURCES_WASM}) source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX}) source_group("Source\\BPF" FILES ${SOURCES_BPF}) source_group("Source\\RISCV" FILES ${SOURCES_RISCV}) source_group("Include\\Common" FILES ${HEADERS_COMMON}) source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) source_group("Include\\ARM" FILES ${HEADERS_ARM}) source_group("Include\\ARM64" FILES ${HEADERS_ARM64}) source_group("Include\\Mips" FILES ${HEADERS_MIPS}) source_group("Include\\PowerPC" FILES ${HEADERS_PPC}) source_group("Include\\Sparc" FILES ${HEADERS_SPARC}) source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ}) source_group("Include\\X86" FILES ${HEADERS_X86}) source_group("Include\\XCore" FILES ${HEADERS_XCORE}) source_group("Include\\M68K" FILES ${HEADERS_M68K}) source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X}) source_group("Include\\M680X" FILES ${HEADERS_MC680X}) source_group("Include\\EVM" FILES ${HEADERS_EVM}) source_group("Include\\WASM" FILES ${HEADERS_WASM}) source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX}) source_group("Include\\BPF" FILES ${HEADERS_BPF}) source_group("Include\\RISCV" FILES ${HEADERS_RISCV}) ### test library 64bit routine: include("GNUInstallDirs") ## installation if (CAPSTONE_INSTALL) install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone) endif () configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY) include(CMakePackageConfigHelpers) set(CAPSTONE_CMAKE_CONFIG_INSTALL_DIR "${CMAKE_INSTALL_LIBDIR}/cmake/capstone") configure_package_config_file( capstone-config.cmake.in ${CMAKE_CURRENT_BINARY_DIR}/capstone-config.cmake INSTALL_DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR} ) write_basic_package_version_file( ${CMAKE_CURRENT_BINARY_DIR}/capstone-config-version.cmake VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH} COMPATIBILITY SameMajorVersion ) if (CAPSTONE_INSTALL) install(FILES "${CMAKE_CURRENT_BINARY_DIR}/capstone-config.cmake" "${CMAKE_CURRENT_BINARY_DIR}/capstone-config-version.cmake" DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR} ) if (CAPSTONE_BUILD_STATIC) install(TARGETS capstone-static EXPORT capstone-targets RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}) endif () if (CAPSTONE_BUILD_SHARED) install(TARGETS capstone-shared EXPORT capstone-targets RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}) endif () install(EXPORT capstone-targets NAMESPACE capstone:: DESTINATION ${CAPSTONE_CMAKE_CONFIG_INSTALL_DIR}) endif () if (CAPSTONE_BUILD_SHARED AND CAPSTONE_BUILD_CSTOOL) FILE(GLOB CSTOOL_SRC cstool/*.c) add_executable(cstool ${CSTOOL_SRC}) target_link_libraries(cstool ${default-target}) if (CAPSTONE_INSTALL) install(TARGETS cstool DESTINATION ${CMAKE_INSTALL_BINDIR}) install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig) endif () endif () capstone-sys-0.15.0/capstone/COMPILE.TXT000064400000000000000000000134370072674642500157040ustar 00000000000000This documentation explains how to compile, install & run Capstone on MacOSX, Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows. To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT. To compile using CMake, see COMPILE_CMAKE.TXT. To compile using XCode on MacOSX, see xcode/README.md. To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md. *-*-*-*-*-* Capstone requires no prerequisite packages, so it is easy to compile & install. (0) Tailor Capstone to your need. Out of all archtitectures supported by Capstone, if you just need several selected archs, choose the ones you want to compile in by editing "config.mk" before going to next steps. By default, all architectures are compiled. The other way of customize Capstone without having to edit config.mk is to pass the desired options on the commandline to ./make.sh. Currently, Capstone supports 8 options, as followings. - CAPSTONE_ARCHS: specify list of architectures to compiled in. - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management. - CAPSTONE_DIET: use this to make the output binaries more compact. - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller. - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86. - CAPSTONE_STATIC: build static library. - CAPSTONE_SHARED: build dynamic (shared) library. - CAPSTONE_DEBUG: enable debug build supporting assert(). By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE modes are disable, and builds all the static & shared libraries. To avoid editing config.mk for these customization, we can pass their values to make.sh, as followings. $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh NOTE: on commandline, put these values in front of ./make.sh, not after it. For each option, refer to docs/README for more details. (1) Compile from source On *nix (such as MacOSX, Linux, *BSD, Solaris): - To compile for current platform, run: $ ./make.sh - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary: $ ./make.sh nix32 (2) Install Capstone on *nix To install Capstone, run: $ sudo ./make.sh install For FreeBSD/OpenBSD, where sudo is unavailable, run: $ su; ./make.sh install Users are then required to enter root password to copy Capstone into machine system directories. Afterwards, run ./tests/test* to see the tests disassembling sample code. NOTE: The core framework installed by "./make.sh install" consist of following files: /usr/include/capstone/arm.h /usr/include/capstone/arm64.h /usr/include/capstone/bpf.h /usr/include/capstone/capstone.h /usr/include/capstone/evm.h /usr/include/capstone/m680x.h /usr/include/capstone/m68k.h /usr/include/capstone/mips.h /usr/include/capstone/mos65xx.h /usr/include/capstone/platform.h /usr/include/capstone/ppc.h /usr/include/capstone/sparc.h /usr/include/capstone/systemz.h /usr/include/capstone/tms320c64x.h /usr/include/capstone/wasm.h /usr/include/capstone/x86.h /usr/include/capstone/xcore.h /usr/lib/libcapstone.a /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX) (3) Cross-compile for Windows from *nix To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64 for 64-bit binaries) are required. - To cross-compile Windows 32-bit binary, simply run: $ ./make.sh cross-win32 - To cross-compile Windows 64-bit binary, run: $ ./make.sh cross-win64 Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then be used on Windows machine. (4) Cross-compile for iOS from Mac OSX. To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. - To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run: $ ./make.sh ios_armv7 - To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run: $ ./make.sh ios_armv7s - To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run: $ ./make.sh ios_arm64 - To cross-compile for all iDevices (armv7 + armv7s + arm64), run: $ ./make.sh ios Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then be used on iOS devices. (5) Cross-compile for Android To cross-compile for Android (smartphone/tablet), Android NDK is required. NOTE: Only ARM and ARM64 are currently supported. $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm or $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64 Resulted files libcapstone.so, libcapstone.a & tests/test* can then be used on Android devices. (6) Compile on Windows with Cygwin To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run: - To compile Windows 32-bit binary under Cygwin, run: $ ./make.sh cygwin-mingw32 - To compile Windows 64-bit binary under Cygwin, run: $ ./make.sh cygwin-mingw64 Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then be used on Windows machine. (7) By default, "cc" (default C compiler on the system) is used as compiler. - To use "clang" compiler instead, run the command below: $ ./make.sh clang - To use "gcc" compiler instead, run: $ ./make.sh gcc (8) To uninstall Capstone, run the command below: $ sudo ./make.sh uninstall (9) Language bindings So far, Python, Ocaml & Java are supported by bindings in the main code. Look for the bindings under directory bindings/, and refer to README file of corresponding languages. Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to these can be found at address http://capstone-engine.org/download.html capstone-sys-0.15.0/capstone/COMPILE_CMAKE.TXT000064400000000000000000000123200072674642500165720ustar 00000000000000This documentation explains how to compile Capstone with CMake, focus on using Microsoft Visual C as the compiler. To compile Capstone on *nix, see COMPILE.TXT. To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT. *-*-*-*-*-* This documentation requires CMake & Windows SDK or MS Visual Studio installed on your machine. Get CMake for free from http://www.cmake.org. (0) Tailor Capstone to your need. Out of archtitectures supported by Capstone, if you just need several selected archs, run "cmake" with the unwanted archs disabled (set to 0) as followings. - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64. - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K. - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. - CAPSTONE_MOS65XX_SUPPORT: support MOS65XX. Run cmake with -DCAPSTONE_MOS65XX_SUPPORT=0 to remove MOS65XX. - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC. - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc. - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ. - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore. - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86. - CAPSTONE_X86_TMS320C64X: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X. - CAPSTONE_X86_M680X: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. - CAPSTONE_X86_EVM: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM. - CAPSTONE_X86_WASM: support Web Assembly. Run cmake with -DCAPSTONE_WASM_SUPPORT=0 to remove WASM. - CAPSTONE_BPF_SUPPORT: support BPF. Run cmake with -DCAPSTONE_BPF_SUPPORT=0 to remove BPF. - CAPSTONE_ARCHITECUTRE_DEFAULT: Whether architectures are enabled by default. Set this of OFF with -DCAPSTONE_ARCHITECUTRE_DEFAULT=OFF to dissable all architectures by default. You can then enable them again with one of the CAPSTONE__SUPPORT options. By default, all architectures are compiled in. Besides, Capstone also allows some more customization via following macros. - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management. - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact. - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller. - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86. - CAPSTONE_DEBUG: change this to ON to enable extra debug assertions. By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE modes are disabled. To use your own memory allocations, turn ON both DIET & X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1 For each option, refer to docs/README for more details. (1) CMake allows you to generate different generators to build Capstone. Below is some examples on how to build Capstone on Windows with CMake. (*) You can let CMake select a generator for you. Do: mkdir build cd build cmake .. This last command is also where you can pass additional CMake configuration flags using `-D=`. Then to build use: cmake --build . --config Release (*) To build Capstone using Nmake of Windows SDK, do: mkdir build cd build ..\nmake.bat After this, find the samples test*.exe, capstone.lib & capstone.dll in the same directory. (*) To build Capstone using Visual Studio, choose the generator accordingly to the version of Visual Studio on your machine. For example, with Visual Studio 2013, do: mkdir build cd build cmake -G "Visual Studio 12" .. After this, find capstone.sln in the same directory. Open it with Visual Studio and build the solution including libraries & all test as usual. (2) You can make sure the prior steps successfully worked by launching one of the testing binary (test*.exe). (3) You can also enable just one specific architecture by passing the architecture name to either the cmake.sh or nmake.bat scripts. e.g.: ../cmake.sh x86 Will just target the x86 architecture. The list of available architectures is: ARM, ARM64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX, WASM, BPF, RISCV. (4) You can also create an installation image with cmake, by using the 'install' target. Use: cmake --build . --config Release --target install This will normally install an image in a default location (`C:\Program Files` on Windows), so it's good to explicitly set this location when configuring CMake. Use: `-DCMAKE_INSTALL_PREFIX=image` for instance, to put the installation in the 'image' subdirectory of the build directory. capstone-sys-0.15.0/capstone/COMPILE_MSVC.TXT000064400000000000000000000123270072674642500165310ustar 00000000000000This documentation explains how to compile Capstone on Windows using Microsoft Visual Studio version 2010 or newer. To compile Capstone on *nix, see COMPILE.TXT To compile Capstone with CMake, see COMPILE_CMAKE.TXT *-*-*-*-*-* Capstone requires no prerequisite packages with default configurations, so it is easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln" and follow the instructions below. NOTE: This requires Visual Studio 2010 or newer versions. If you wish to embed Capstone in a kernel driver, Visual Studio 2013 or newer versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required. (0) Tailor Capstone to your need. Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln", then directly editing the projects "capstone_static" & "capstone_dll" for static and dynamic libraries, respectively. This must be done before going to the next steps. In VisualStudio interface, modify the preprocessor definitions via "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor" to customize Capstone library, as followings. - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support. - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support. - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support. - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support. - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support. - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support. - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support. By default, all 9 architectures are compiled in. Besides, Capstone also allows some more customization via following macros. - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management. - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact. - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller. - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable AT&T syntax on x86. By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE modes are disable. For each option, refer to docs/README for more details. (1) Compile from source on Windows with Visual Studio - Choose the configuration and the platform you want: Release/Debug & Win32/Win64. - Build only the libraries, or the libraries along with all the tests. - "capstone_static_winkernel" is for compiling Capstone for a driver and "test_winkernel" is a test for a driver, and those are excluded from build by default. To compile them, open the Configuration Manager through the [Build] menu and check "Build" check boxes for those project. (2) You can make sure the prior steps successfully worked by launching one of the testing binary (test*.exe). The testing binary for a driver "test_winkernel.sys" is made up of all tests for supported architectures configured with the step (0) along side its own tests. Below explains a procedure to run the test driver and check test results. On the x64 platform, the test signing mode has to be enabled to install the test driver. To do it, open the command prompt with the administrator privileges and type the following command, and then restart the system to activate the change: >bcdedit /set testsigning on Test results from the test driver is sent to kernel debug buffer. In order to see those results, download DebugView and run it with the administrator privileges, then check [Capture Kernel] through the [Capture] menu. DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx To install and uninstall the driver, use the 'sc' command. For installing and executing test_winkernel.sys, execute the following commands with the administrator privileges: >sc create test_winkernel type= kernel binPath= [SC] CreateService SUCCESS >sc start test_winkernel [SC] StartService FAILED 995: The I/O operation has been aborted because of either a thread exit or an application request. To uninstall the driver, execute the following commands with the administrator privileges: >sc delete test_winkernel >bcdedit /deletevalue testsigning (3) Installing and building capstone via vcpkg You can download and install capstone using the vcpkg(https://github.com/Microsoft/vcpkg) dependency manager: git clone https://github.com/Microsoft/vcpkg.git cd vcpkg ./bootstrap-vcpkg.sh ./vcpkg integrate install vcpkg install capstone The capstone port in vcpkg is kept up to date by Microsoft team members and community contributors. If the version is out of date, please create an issue or pull request on the vcpkg repository(https://github.com/Microsoft/vcpkg). capstone-sys-0.15.0/capstone/CREDITS.TXT000064400000000000000000000057150072674642500157110ustar 00000000000000This file credits all the contributors of the Capstone engine project. Key developers ============== 1. Nguyen Anh Quynh - Core engine - Bindings: Python, Ruby, OCaml, Java, C# 2. Tan Sheng Di - Bindings: Ruby 3. Ben Nagy - Bindings: Ruby, Go 4. Dang Hoang Vu - Bindings: Java Beta testers (in random order) ============================== Pancake Van Hauser FX of Phenoelit The Grugq, The Grugq <-- our hero for submitting the first ever patch! Isaac Dawson, Veracode Inc Patroklos Argyroudis, Census Inc. (http://census-labs.com) Attila Suszter Le Dinh Long Nicolas Ruff Gunther Alex Ionescu, Winsider Seminars & Solutions Inc. Snare Daniel Godas-Lopez Joshua J. Drake Edgar Barbosa Ralf-Philipp Weinmann Hugo Fortier Joxean Koret Bruce Dang Andrew Dunham Contributors (in no particular order) ===================================== (Please let us know if you want to have your name here) Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!) Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC. Daniel Pistelli: Cmake support. Peter Hlavaty: integrate Capstone for Windows kernel drivers. Guillaume Jeanne: Ocaml binding. Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features. David Martínez Moreno & Hilko Bengen: Debian package. Félix Cloutier: Xcode project. Benoit Lecocq: OpenBSD package. Christophe Avoinne (Hlide): Improve memory management for better performance. Michael Cohen & Nguyen Tan Cong: Python module installer. Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package. Felix Gröbert (Google): fuzz testing harness. Xipiter LLC: Capstone logo redesigned. Satoshi Tanda: Support Windows kernel driver. Tang Yuhang: cstool. Andrew Dutcher: better Python setup. Ruben Boonen: PowerShell binding. David Zimmer: VB6 binding. Philippe Antoine: Integration with oss-fuzz and various fixes. Bui Dinh Cuong: Explicit registers accessed for Arm64. Vincent Bénony: Explicit registers accessed for X86. Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package. Felix Gröbert (Google): fuzz testing harness. Daniel Collin & Nicolas Planel: M68K architecture. Pranith Kumar: Explicit registers accessed for Arm64. Xipiter LLC: Capstone logo redesigned. Satoshi Tanda: Support Windows kernel driver. Koutheir Attouchi: Support for Windows CE. Fotis Loukos: TMS320C64x architecture. Wolfgang Schwotzer: M680X architecture. Philippe Antoine: Integration with oss-fuzz and various fixes. Stephen Eckels (stevemk14ebr): x86 encoding features Tong Yu(Spike) & Kai Jern, Lau (xwings): WASM architecture. Sebastian Macke: MOS65XX architecture Ilya Leoshkevich: SystemZ architecture improvements. Do Minh Tuan: Regression testing tool (cstest) david942j: BPF (both classic and extended) architecture. fanfuqiang & citypw & porto703 : RISCV architecture. Josh "blacktop" Maine: Arm64 architecture improvements.capstone-sys-0.15.0/capstone/ChangeLog000064400000000000000000000454520072674642500157670ustar 00000000000000This file details the changelog of Capstone. --------------------------------- Version 4.0.1: January 10th, 2019 [ Core ] - Fix some issues for packaging (Debian, Gentoo). - Better support for building with Mingw. - cstool has new option -s to turn on skipdata mode. - cstool -v now report build settings of the core. - Add suite/capstone_get_setup.c so users can integrate with their own code to retrieve Capstone settings at build time. [ Arm ] - Fix 4.0 regression: the `tbh [r0, r1, lsl #1]` instruction sets the operand.shift.value back again (see #1317) - Remove ARM_REG_PC group for BX instruction. [ X86 ] - Fix: endbr32 and endbr64 instructions are now properly decoded in both CS_MODE_32 and CS_MODE_64 (#1129) [ M680X ] - Fix some issues reported by clang-analyzer (#1329). [ Python ] - Fix skipdata setup. - Add getter/setter for skipdata_mnem, skipdata_callback. --------------------------------- Version 4.0: December 18th, 2018 [ Core ] - New APIs: cs_regs_access() - Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM. - Various updates & bugfixes for all architectures. - Add 4 new architectures: EVM, M68K, M680X & TMS320C64x. - Add new group types: CS_GRP_PRIVILEGE & CS_GRP_BRANCH_RELATIVE. - Add new error types: CS_ERR_X86_MASM. [ X86 ] - Add XOP code condition type in x86_xop_cc. - Add some info on encoding to cs_x86 in cs_x86_encoding. - Add register flags update in cs_x86.{eflags, fpu_flags} - Change cs_x86.disp type from int32_t to int64_t. - Add new groups: X86_GRP_VM & X86_GRP_FPU. - Lots of new instructions (AVX) [ ARM64 ] - Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS. [ Mips ] - Add mode CS_MODE_MIPS2. [ PPC ] - Change cs_ppc_op.imm type from int32_t to int64_t. - Add new groups: PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR & PPC_GRP_QPX. - Lots of new instructions (QPX among them) [ Sparc ] - Change cs_sparc_op.imm type from int32_t to int64_t. [ Binding ] - New bindings: PowerShell & VB6 --------------------------------- Version 3.0.5: July 18th, 2018 [ Core ] - Fix the include path for Android builds when building cstool. - Add posibility to disable universal build for Mac OS. - cstool: Separate instruction bytes by spaces. - Fix code path of pkg-config in Cmake. - Update XCode project for XCode 9.1. - Add Cortex-M support to cstool. - Cmake forces to be build using MT with MSVC. - Better support for Mac OS kernel. [ X86 ] - Fix some issues in handling EVEX & VEX3 instructions. - Fix immediate operand for AND instruction in ATT mode. - Fix ATT syntax when imm operand is 0. - Better handle XACQUIRE/XRELEASE. - Fix imm operand of RETF. [ ARM ] - Fix an integer overlow bug. [ ARM64 ] - Bug fix for incorrect operand type in certain load/store instructions. [ Mips ] - Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32 [ PPC ] - Fix endian check. [ Sparc ] - Fix an integer overlow bug. [ SystemZ ] - Fix an integer overlow bug. [ Python binding ] - Raise error on accessing irrelevant data fields if skipdata & detail modes are enable. --------------------------------- Version 3.0.5-rc3: July 31st, 2017 [ Core ] - Fix compilation for MacOS kernel extension - cstool to support armbe and arm64be modes - Add nmake.bat for Windows build - Fix an integer overflow for Windows kernel driver - Support to embedded Capstone into MacOS kernel - cstool: fix mips64 mode - Fix a compiling error in MS Visual Studio 2015 - Install pkgconfig file with CMake build - Fix SOVERSION property of CMake build - Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc - Fix MingW build - Better handle CMake installation for Linux 64bit [ X86 ] - Support BND prefix of Intel MPX extension - Correct operand size for CALL/JMP in 64bit mode with prefix 0x66 - LOCK NOP is a valid instruction - Fix ATT syntax for instruction with zero offset segment register - LES/LDS are invalid in 64bit mode - Fix number of operands for some MOV instructions [ ARM ] - Fix POP reg to update SP register - Update flags for UADD8 instruction [ ARM64 ] - Better performance with new lookup table - Handle system registers added in ARMv8.1/2 [ Java binding ] - Better handle input with invalid code [ Visual Basic binding ] - New binding --------------------------------- Version 3.0.5-rc2: March 2nd, 2017 [ Core ] - Fix build for Visual Studio 2012 - Fix X86_REL_ADDR macro - Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA - Better support for embedding Capstone into Windows kernel drivers - Support to embedded Capstone into MacOS kernel - Support MacOS 10.11 and up - Better support for Cygwin - Support build packages for FreeBSD & DragonflyBSD - Add a command-line tool "cstool" - Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc [ X86 ] - Some random 16-bit code can be handled wrongly. - Remove abundant operand type X86_OP_FP - Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL - Add X86_REG_EFLAGS for STC and STD - Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT - Rename registers ST0-ST7 to be consistent with asm output [ ARM ] - Properly handle IT instruction - Fix LDRSB - Fix writeback for LDR - Fix Thumb BigEndian setup [ ARM64 ] - Fix arith extender - Fix writeback for LDR - Rename enum arm64_mrs_reg to arm64_sysreg [ PowerPC ] - Print 0 offset for memory operand [ Sparc ] - Fix POPC instruction [ Python binding ] - Better PyPy support - Add __version__ - Better support for Python 3 - Fix CS_SKIPDATA_CALLBACK prototype - Cast skipdata function inside binding to simplify the API [ Java binding ] - Better handle input with invalid code [ PowerShell ] - New binding --------------------------------- Version 3.0.4: July 15th, 2015 [ Library ] - Improve cross-compile for Android using Android NDK. - Support cross-compile for AArch64 Android (with Linux GCC). - Removed osxkernel_inttypes.h that is incompatible with BSD license. - Make it possible to compile with CC having a space inside (like "ccache gcc"). [ X86 ] - Fix a null pointer dereference bug on handling code with special prefixes. - Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax. - Print immediate operand in positive form in some algorithm instructions. - Properly decode some SSE instructions. [ PowerPC ] - Fixed a memory corruption bug. - Fixed a memory corruption bug for the engine built in DIET mode. [ Mips ] - Fixed instruction ID of SUBU instruction. - Fixed a memory corruption bug. [ Arm ] - Fixed a memory corruption bug on IT instruction. [ XCore ] - Fixed a memory corruption bug when instruction has a memory operand. [ Python ] - Support Virtualenv. - setup.py supports option --user if not in a virtualenv to allow for local usage. - Properly handle the destruction of Cs object in the case the shared library was already unloaded. --------------------------------- Version 3.0.3: May 08th, 2015 [ Library ] - Support to embed into Mac OS X kernel extensions. - Now it is possible to compile Capstone with older C compilers, such as GCC 4.8 on Ubuntu 12.04. - Add "test_iter" to MSVC project. [ X86 ] - All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of "rcll %edx"). - CMPXCHG16B is a valid instruction with LOCK prefix. - Fixed a segfault on the input of 0xF3. [ Arm ] - BLX instruction modifies PC & LR registers. [ Sparc ] - Improved displacement decoding for sparc banching instructions. [ Python binding ] - Fix for Cython so it can properly initialize. - X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type. - Properly support compile with Cygwin & install binding (setup.py). --------------------------------- Version 3.0.2: March 11th, 2015 [ Library ] - On *nix, only export symbols that are part of the API (instead of all the internal symbols). [ X86 ] - Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding. - Fix implicit registers read/written & instruction groups of some instructions. - More flexible on the order of prefixes, so better handle some tricky instructions. - REPNE prefix can go with STOS & MOVS instructions. - Fix a compilation bug for X86_REDUCE mode. - Fix operand size of instructions with operand PTR [] [ Arm ] - Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode). - Fix a bug on handling the If-Then block. [ Mips ] - Sanity check for the input size for MIPS64 mode. [ MSVC ] - Compile capstone.dll with static runtime MSVCR built in. [ Python binding ] - Fix a compiling issue of Cython binding with gcc 4.9. --------------------------------- Version 3.0.1: February 03rd, 2015 [ X86 ] - Properly handle LOCK, REP, REPE & REPNE prefixes. - Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions. - Print LJUMP/LCALL without * as prefix for Intel syntax. - Handle REX prefix properly for segment/MMX related instructions (x86_64). - Instruction with length > 15 is consider invalid. - Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP, FSTP, FSTPNCE, NOP. - Handle some tricky code for some X86_64 instructions with REX prefix. - Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg - MOV32ms & MOV32sm should reference word rather than dword. [ Arm64 ] - BL & BLR instructions do not read SP register. - Print absolute (rather than relative) address for instructions B, BL, CBNZ, ADR. [ Arm ] - Instructions ADC & SBC do not update flags. - BL & BLX do not read SP, but PC register. - Alias LDR instruction with operands [sp], 4 to POP. - Print immediate operand of MVN instruction in positive hexadecimal form. [ PowerPC ] - Fix some compilation bugs when DIET mode is enable. - Populate SLWI/SRWI instruction details with SH operand. [ Python binding ] - Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes. - Fixed a memory leak for Cython disasm functions when we immaturely quit the enumeration of disassembled instructions. - Fix a NULL memory access issue when SKIPDATA & Detail modes are enable at the same time. - Fix a memory leaking bug when when we stop enumeration over the disassembled instructions prematurely. - Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx). --------------------------------- Version 3.0: November 19th, 2014 [ API ] - New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials. - Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but marked obsolete to be removed in future) - Support SKIPDATA mode, so Capstone can jump over unknown data and keep going from the next legitimate instruction. See docs/README for tutorials. - More details provided in cs_detail struct for all architectures. - API version was bumped to 3.0. [ Bindings ] - Python binding supports Python3 (besides Python2). - Support Ocaml binding. - Java: add close() method to be used to deinitialize a Capstone object when no longer use it. [ Architectures ] - New architectures: Sparc, SystemZ & XCore. - Important bugfixes for Arm, Arm64, Mips, PowerPC & X86. - Support more instructions for Arm, Arm64, Mips, PowerPC & X86. - Always expose absolute addresses rather than relative addresses (Arm, Arm64, Mips, PPC, Sparc, X86). - Use common instruction operand types REG, IMM, MEM & FP across all architectures (to enable cross-architecture analysis). - Use common instruction group types across all architectures (to enable cross-architecture analysis). [ X86 ] - X86 engine is mature & handles all the malware tricks (that we are aware of). - Added a lot of new instructions (such as AVX512, 3DNow, etc). - Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE. - Print immediate in positive form & hexadecimal for AND/OR/XOR instructions. - More friendly disassembly for JMP16i (in the form segment:offset) [ Mips ] - Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) & MipsGP64 (CS_MODE_MIPSGP64). - Removed the ABI-only mode CS_MODE_N64. - New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 & CS_MODE_64). [ ARM ] - Support new mode CS_MODE_V8 for Armv8 A32 encodings. - Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions [ ARM64 ] - Print immediate in hexadecimal for AND/ORR/EOR/TST instructions. [ PowerPC ] - Do not print a dot in front of absolute address. [ Other features ] - Support for Microsoft Visual Studio (so enable Windows native compilation). - Support CMake compilation. - Cross-compile for Android. - Build libraries/tests using XCode project - Much faster, while consuming less memory for all architectures. --------------------------------- Version 2.1.2: April 3rd, 2014 This is a stable release to fix some bugs deep in the core. There is no update to any architectures or bindings, so bindings version 2.1 can be used with this version 2.1.2 just fine. [ Core changes] - Support cross-compilation for all iDevices (iPhone/iPad/iPod). - X86: do not print memory offset in negative form. - Fix a bug in X86 when Capstone cannot handle short instruction. - Print negative number above -9 without prefix 0x (arm64, mips, arm). - Correct the SONAME setup for library versioning (Linux, *BSD, Solaris). - Set library versioning for dylib of OSX. --------------------------------- Version 2.1.1: March 13th, 2014 This is a stable release to fix some bugs deep in the core. There is no update to any architectures or bindings, so bindings version 2.1 can be used with this version 2.1.1 just fine. [ Core changes] - Fix a buffer overflow bug in Thumb mode (ARM). Some special input can trigger this flaw. - Fix a crash issue when embedding Capstone into OSX kernel. This should also enable Capstone to be embedded into other systems with limited stack memory size such as Linux kernel or some firmwares. - Use a proper SONAME for library versioning (Linux). --------------------------------- Version 2.1: March 5th, 2014 [ API changes ] - API version has been bumped to 2.1. - Change prototype of cs_close() to be able to invalidate closed handle. See http://capstone-engine.org/version_2.1_API.html for more information. - Extend cs_support() to handle more query types, not only about supported architectures. This change is backward compatible, however, so existent code do not need to be modified to support this. - New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of the engine. - New error code CS_ERR_DIET to report errors about newly added diet mode. - New error code CS_ERR_VERSION to report issue of incompatible versions between bindings & core engine. [ Core changes ] - On memory usage, Capstone uses about 40% less memory, while still faster than version 2.0. - All architectures are much smaller: binaries size reduce at least 30%. Especially, X86-only binary reduces from 1.9MB to just 720KB. - Support "diet" mode, in which engine size is further reduced (by around 40%) for embedding purpose. The price to pay is that we have to sacrifice some non-critical data fields. See http://capstone-engine.org/diet.html for more details. [ Architectures ] - Update all 5 architectures to fix bugs. - PowerPC: - New instructions: FMR & MSYNC. - Mips: - New instruction: DLSA - X86: - Properly handle AVX-512 instructions. - New instructions: PSETPM, SALC, INT1, GETSEC. - Fix some memory leaking issues in case of prefixed instructions such as LOCK, REP, REPNE. [ Python binding ] - Verify the core version at initialization time. Refuse to run if its version is different from the core's version. - New API disasm_lite() added to Cs class. This light API only returns tuples of (address, size, mnemonic, op_str), rather than list of CsInsn objects. This improves performance by around 30% in some benchmarks. - New API version_bind() returns binding's version, which might differ from the core's API version if the binding is out-of-date. - New API debug() returns information on Cython support, diet status & archs compiled in. - Fixed some memory leaking bugs for Cython binding. - Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups. - Support diet mode. [ Java binding ] - Fix some memory leaking bugs. - New API version() returns combined version. - Support diet mode. - Better support for detail option. [ Miscellaneous ] - make.sh now can uninstall the core engine. This is done with: $ sudo ./make.sh uninstall ---------------------------------- Version 2.0: January 22nd, 2014 Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. [ API changes ] - API version has been bumped to 2.0 (see cs_version() API) - New API cs_strerror(errno) returns a string describing error code given in its only argument. - cs_version() now returns combined version encoding both major & minor versions. - New option CS_OPT_MODE allows to change engine’s mode at run-time with cs_option(). - New option CS_OPT_MEM allows to specify user-defined functions for dynamically memory management used internally by Capstone. This is useful to embed Capstone into special environments such as kernel or firware. - New API cs_support() can be used to check if this lib supports a particular architecture (this is necessary since we now allow to choose which architectures to compile in). - The detail option is OFF by default now. To get detail information, it should be explicitly turned ON. The details then can be accessed using cs_insn.detail pointer (to newly added structure cs_detail) [ Core changes ] - On memory usage, Capstone uses much less memory, but a lot faster now. - User now can choose which architectures to be supported by modifying config.mk before compiling/installing. [ Architectures ] - Arm - Support Big-Endian mode (besides Little-Endian mode). - Support friendly register, so instead of output sub "r12,r11,0x14", we have "sub ip,fp,0x14". - Arm64: support Big-Endian mode (besides Little-Endian mode). - PowerPC: newly added. - Mips: support friendly register, so instead of output "srl $2,$1,0x1f", we have "srl $v0,$at,0x1f". - X86: bug fixes. [ Python binding ] - Python binding is vastly improved in performance: around 3 ~ 4 times faster than in 1.0. - Cython support has been added, which can further speed up over the default pure Python binding (up to 30% in some cases) - Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) to return succesfully disassembled instructions. This improves the performance and reduces memory usage. [ Java binding ] - Better performance & bug fixes. [ Miscellaneous ] - Fixed some installation issues with Gentoo Linux. - Capstone now can easily compile/install on all *nix, including Linux, OSX, {Net, Free, Open}BSD & Solaris. ---------------------------------- [Version 1.0]: December 18th, 2013 - Initial public release. capstone-sys-0.15.0/capstone/HACK.TXT000064400000000000000000000075050072674642500153210ustar 00000000000000Code structure -------------- Capstone source is organized as followings. . <- core engine + README + COMPILE.TXT etc ├── arch <- code handling disasm engine for each arch │   ├── AArch64 <- ARM64 (aka ARMv8) engine │   ├── ARM <- ARM engine │   ├── BPF <- Berkeley Packet Filter engine │   ├── EVM <- Ethereum engine │   ├── M680X <- M680X engine │   ├── M68K <- M68K engine │   ├── Mips <- Mips engine │   ├── MOS65XX <- MOS65XX engine │   ├── PowerPC <- PowerPC engine │   ├── Sparc <- Sparc engine │   ├── SystemZ <- SystemZ engine │   ├── TMS320C64x <- TMS320C64x engine │   ├── X86 <- X86 engine │   └── XCore <- XCore engine ├── bindings <- all bindings are under this dir │   ├── java <- Java bindings + test code │   ├── ocaml <- Ocaml bindings + test code │   └── python <- Python bindings + test code ├── contrib <- Code contributed by community to help Capstone integration ├── cstool <- Cstool ├── docs <- Documentation ├── include <- API headers in C language (*.h) ├── msvc <- Microsoft Visual Studio support (for Windows compile) ├── packages <- Packages for Linux/OSX/BSD. ├── windows <- Windows support (for Windows kernel driver compile) ├── suite <- Development test tools - for Capstone developers only ├── tests <- Test code (in C language) └── xcode <- Xcode support (for MacOSX compile) Follow instructions in COMPILE.TXT for how to compile and run test code. Note: if you find some strange bugs, it is recommended to firstly clean the code and try to recompile/reinstall again. This can be done with: $ ./make.sh $ sudo ./make.sh install Then test Capstone with cstool, for example: $ cstool x32 "90 91" At the same time, for Java/Ocaml/Python bindings, be sure to always use the bindings coming with the core to avoid potential incompatibility issue with older versions. See bindings//README for detail instructions on how to compile & install the bindings. Coding style ------------ - C code follows Linux kernel coding style, using tabs for indentation. - Python code uses 4 spaces for indentation. Adding an architecture ---------------------- Obviously, you first need to write all the logic and put it in a new directory arch/newarch Then, you have to modify other files. (You can look for one architecture such as EVM in these files to get what you need to do) Integrate: - cs.c - cstool/cstool.c - cstool/cstool_newarch.c: print the architecture specific details - include/capstone/capstone.h - include/capstone/newarch.h: create this file to export all specifics about the new architecture Compile: - CMakeLists.txt - Makefile - config.mk Tests: - tests/Makefile - tests/test_basic.c - tests/test_detail.c - tests/test_iter.c - tests/test_newarch.c - suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms - suite/capstone_get_setup.c - suite/MC/newarch/mode.mc: samples - suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing Bindings: - bindings/Makefile - bindings/const_generator.py: add the header file and the architecture - bindings/python/Makefile - bindings/python/capstone/__init__.py - bindings/python/capstone/newarch.py: define the python structures - bindings/python/capstone/newarch_const.py: generate this file - bindings/python/test_newarch.py: create a basic decoding test - bindings/python/test_all.py Docs: - README.md - HACK.txt - CREDITS.txt: add your name capstone-sys-0.15.0/capstone/LEB128.h000064400000000000000000000020700072674642500152100ustar 00000000000000//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file declares some utility functions for encoding SLEB128 and // ULEB128 values. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_SUPPORT_LEB128_H #define CS_LLVM_SUPPORT_LEB128_H #include "include/capstone/capstone.h" /// Utility function to decode a ULEB128 value. static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) { const uint8_t *orig_p = p; uint64_t Value = 0; unsigned Shift = 0; do { Value += (uint64_t)(*p & 0x7f) << Shift; Shift += 7; } while (*p++ >= 128); if (n) *n = (unsigned)(p - orig_p); return Value; } #endif // LLVM_SYSTEM_LEB128_H capstone-sys-0.15.0/capstone/LICENSE.TXT000064400000000000000000000032270072674642500156720ustar 00000000000000This is the software license for Capstone disassembly framework. Capstone has been designed & implemented by Nguyen Anh Quynh See http://www.capstone-engine.org for further information. Copyright (c) 2013, COSEINC. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the developer(s) nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. capstone-sys-0.15.0/capstone/LICENSE_LLVM.TXT000064400000000000000000000064030072674642500165230ustar 00000000000000============================================================================== LLVM Release License ============================================================================== University of Illinois/NCSA Open Source License Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign. All rights reserved. Developed by: LLVM Team University of Illinois at Urbana-Champaign http://llvm.org Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal with the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimers. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimers in the documentation and/or other materials provided with the distribution. * Neither the names of the LLVM Team, University of Illinois at Urbana-Champaign, nor the names of its contributors may be used to endorse or promote products derived from this Software without specific prior written permission. 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The disclaimer of warranty in the University of Illinois Open Source License applies to all code in the LLVM Distribution, and nothing in any of the other licenses gives permission to use the names of the LLVM Team or the University of Illinois to endorse or promote products derived from this Software. The following pieces of software have additional or alternate copyrights, licenses, and/or restrictions: Program Directory ------- --------- Autoconf llvm/autoconf llvm/projects/ModuleMaker/autoconf llvm/projects/sample/autoconf Google Test llvm/utils/unittest/googletest OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} ARM contributions llvm/lib/Target/ARM/LICENSE.TXT md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h capstone-sys-0.15.0/capstone/MCDisassembler.h000064400000000000000000000004360072674642500172140ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_MCDISASSEMBLER_H #define CS_MCDISASSEMBLER_H typedef enum DecodeStatus { MCDisassembler_Fail = 0, MCDisassembler_SoftFail = 1, MCDisassembler_Success = 3, } DecodeStatus; #endif capstone-sys-0.15.0/capstone/MCFixedLenDisassembler.h000064400000000000000000000026360072674642500206370ustar 00000000000000//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // Fixed length disassembler decoder state machine driver. //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H #define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H // Disassembler state machine opcodes. enum DecoderOps { MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len) MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip) MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len, // uleb128 Val, uint16_t NumToSkip) MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip) MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx) MCD_OPC_TryDecode, // OPC_TryDecode(uleb128 Opcode, uleb128 DIdx, // uint16_t NumToSkip) MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask) MCD_OPC_Fail // OPC_Fail() }; #endif capstone-sys-0.15.0/capstone/MCInst.c000064400000000000000000000063200072674642500155050ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include #else #include #include #endif #include #include "MCInst.h" #include "utils.h" #define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1) void MCInst_Init(MCInst *inst) { unsigned int i; for (i = 0; i < 48; i++) { inst->Operands[i].Kind = kInvalid; inst->Operands[i].ImmVal = 0; } inst->Opcode = 0; inst->OpcodePub = 0; inst->size = 0; inst->has_imm = false; inst->op1_size = 0; inst->writeback = false; inst->ac_idx = 0; inst->popcode_adjust = 0; inst->assembly[0] = '\0'; inst->wasm_data.type = WASM_OP_INVALID; inst->xAcquireRelease = 0; } void MCInst_clear(MCInst *inst) { inst->size = 0; } // do not free @Op void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) { int i; for(i = inst->size; i > index; i--) //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand)); inst->Operands[i] = inst->Operands[i-1]; inst->Operands[index] = *Op; inst->size++; } void MCInst_setOpcode(MCInst *inst, unsigned Op) { inst->Opcode = Op; } void MCInst_setOpcodePub(MCInst *inst, unsigned Op) { inst->OpcodePub = Op; } unsigned MCInst_getOpcode(const MCInst *inst) { return inst->Opcode; } unsigned MCInst_getOpcodePub(const MCInst *inst) { return inst->OpcodePub; } MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) { return &inst->Operands[i]; } unsigned MCInst_getNumOperands(const MCInst *inst) { return inst->size; } // This addOperand2 function doesnt free Op void MCInst_addOperand2(MCInst *inst, MCOperand *Op) { inst->Operands[inst->size] = *Op; inst->size++; } bool MCOperand_isValid(const MCOperand *op) { return op->Kind != kInvalid; } bool MCOperand_isReg(const MCOperand *op) { return op->Kind == kRegister; } bool MCOperand_isImm(const MCOperand *op) { return op->Kind == kImmediate; } bool MCOperand_isFPImm(const MCOperand *op) { return op->Kind == kFPImmediate; } /// getReg - Returns the register number. unsigned MCOperand_getReg(const MCOperand *op) { return op->RegVal; } /// setReg - Set the register number. void MCOperand_setReg(MCOperand *op, unsigned Reg) { op->RegVal = Reg; } int64_t MCOperand_getImm(MCOperand *op) { return op->ImmVal; } void MCOperand_setImm(MCOperand *op, int64_t Val) { op->ImmVal = Val; } double MCOperand_getFPImm(const MCOperand *op) { return op->FPImmVal; } void MCOperand_setFPImm(MCOperand *op, double Val) { op->FPImmVal = Val; } MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) { MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); op->Kind = kRegister; op->RegVal = Reg; return op; } void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) { MCOperand *op = &(mcInst->Operands[mcInst->size]); mcInst->size++; op->Kind = kRegister; op->RegVal = Reg; } MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) { MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); op->Kind = kImmediate; op->ImmVal = Val; return op; } void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) { MCOperand *op = &(mcInst->Operands[mcInst->size]); mcInst->size++; op->Kind = kImmediate; op->ImmVal = Val; } capstone-sys-0.15.0/capstone/MCInst.h000064400000000000000000000110550072674642500155130ustar 00000000000000//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains the declaration of the MCInst and MCOperand classes, which // is the basic representation used to represent low-level machine code // instructions. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_MCINST_H #define CS_MCINST_H #include "include/capstone/capstone.h" #include "MCRegisterInfo.h" typedef struct MCInst MCInst; typedef struct cs_struct cs_struct; typedef struct MCOperand MCOperand; /// MCOperand - Instances of this class represent operands of the MCInst class. /// This is a simple discriminated union. struct MCOperand { enum { kInvalid = 0, ///< Uninitialized. kRegister, ///< Register operand. kImmediate, ///< Immediate operand. kFPImmediate, ///< Floating-point immediate operand. } MachineOperandType; unsigned char Kind; union { unsigned RegVal; int64_t ImmVal; double FPImmVal; }; }; bool MCOperand_isValid(const MCOperand *op); bool MCOperand_isReg(const MCOperand *op); bool MCOperand_isImm(const MCOperand *op); bool MCOperand_isFPImm(const MCOperand *op); bool MCOperand_isInst(const MCOperand *op); /// getReg - Returns the register number. unsigned MCOperand_getReg(const MCOperand *op); /// setReg - Set the register number. void MCOperand_setReg(MCOperand *op, unsigned Reg); int64_t MCOperand_getImm(MCOperand *op); void MCOperand_setImm(MCOperand *op, int64_t Val); double MCOperand_getFPImm(const MCOperand *op); void MCOperand_setFPImm(MCOperand *op, double Val); const MCInst *MCOperand_getInst(const MCOperand *op); void MCOperand_setInst(MCOperand *op, const MCInst *Val); // create Reg operand in the next slot void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); // create Reg operand use the last-unused slot MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg); // create Imm operand in the next slot void MCOperand_CreateImm0(MCInst *inst, int64_t Val); // create Imm operand in the last-unused slot MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val); /// MCInst - Instances of this class represent a single low-level machine /// instruction. struct MCInst { unsigned OpcodePub; // public opcode (_INS_yyy in header files .h) uint8_t size; // number of operands bool has_imm; // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax uint8_t op1_size; // size of 1st operand - for X86 Intel syntax unsigned Opcode; // private opcode MCOperand Operands[48]; cs_insn *flat_insn; // insn to be exposed to public uint64_t address; // address of this insn cs_struct *csh; // save the main csh uint8_t x86opsize; // opsize for [mem] operand // These flags could be used to pass some info from one target subcomponent // to another, for example, from disassembler to asm printer. The values of // the flags have any sense on target level only (e.g. prefixes on x86). unsigned flags; // (Optional) instruction prefix, which can be up to 4 bytes. // A prefix byte gets value 0 when irrelevant. // This is copied from cs_x86 struct uint8_t x86_prefix[4]; uint8_t imm_size; // immediate size for X86_OP_IMM operand bool writeback; // writeback for ARM // operand access index for list of registers sharing the same access right (for ARM) uint8_t ac_idx; uint8_t popcode_adjust; // Pseudo X86 instruction adjust char assembly[8]; // for special instruction, so that we dont need printer unsigned char evm_data[32]; // for EVM PUSH operand cs_wasm_op wasm_data; // for WASM operand MCRegisterInfo *MRI; uint8_t xAcquireRelease; // X86 xacquire/xrelease }; void MCInst_Init(MCInst *inst); void MCInst_clear(MCInst *inst); // do not free operand after inserting void MCInst_insert0(MCInst *inst, int index, MCOperand *Op); void MCInst_setOpcode(MCInst *inst, unsigned Op); unsigned MCInst_getOpcode(const MCInst*); void MCInst_setOpcodePub(MCInst *inst, unsigned Op); unsigned MCInst_getOpcodePub(const MCInst*); MCOperand *MCInst_getOperand(MCInst *inst, unsigned i); unsigned MCInst_getNumOperands(const MCInst *inst); // This addOperand2 function doesnt free Op void MCInst_addOperand2(MCInst *inst, MCOperand *Op); #endif capstone-sys-0.15.0/capstone/MCInstrDesc.c000064400000000000000000000010170072674642500164640ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #include "MCInstrDesc.h" /// isPredicate - Set if this is one of the operands that made up of /// the predicate operand that controls an isPredicable() instruction. bool MCOperandInfo_isPredicate(const MCOperandInfo *m) { return m->Flags & (1 << MCOI_Predicate); } /// isOptionalDef - Set if this operand is a optional def. /// bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m) { return m->Flags & (1 << MCOI_OptionalDef); } capstone-sys-0.15.0/capstone/MCInstrDesc.h000064400000000000000000000110300072674642500164650ustar 00000000000000//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the MCOperandInfo and MCInstrDesc classes, which // are used to describe target instructions and their operands. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_MC_MCINSTRDESC_H #define CS_LLVM_MC_MCINSTRDESC_H #include "MCRegisterInfo.h" #include "capstone/platform.h" //===----------------------------------------------------------------------===// // Machine Operand Flags and Description //===----------------------------------------------------------------------===// // Operand constraints enum MCOI_OperandConstraint { MCOI_TIED_TO = 0, // Must be allocated the same register as. MCOI_EARLY_CLOBBER // Operand is an early clobber register operand }; /// OperandFlags - These are flags set on operands, but should be considered /// private, all access should go through the MCOperandInfo accessors. /// See the accessors for a description of what these are. enum MCOI_OperandFlags { MCOI_LookupPtrRegClass = 0, MCOI_Predicate, MCOI_OptionalDef }; /// Operand Type - Operands are tagged with one of the values of this enum. enum MCOI_OperandType { MCOI_OPERAND_UNKNOWN = 0, MCOI_OPERAND_IMMEDIATE = 1, MCOI_OPERAND_REGISTER = 2, MCOI_OPERAND_MEMORY = 3, MCOI_OPERAND_PCREL = 4, MCOI_OPERAND_FIRST_GENERIC = 6, MCOI_OPERAND_GENERIC_0 = 6, MCOI_OPERAND_GENERIC_1 = 7, MCOI_OPERAND_GENERIC_2 = 8, MCOI_OPERAND_GENERIC_3 = 9, MCOI_OPERAND_GENERIC_4 = 10, MCOI_OPERAND_GENERIC_5 = 11, MCOI_OPERAND_LAST_GENERIC = 11, MCOI_OPERAND_FIRST_TARGET = 12, }; /// MCOperandInfo - This holds information about one operand of a machine /// instruction, indicating the register class for register operands, etc. /// typedef struct MCOperandInfo { /// This specifies the register class enumeration of the operand /// if the operand is a register. If isLookupPtrRegClass is set, then this is /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to /// get a dynamic register class. int16_t RegClass; /// These are flags from the MCOI::OperandFlags enum. uint8_t Flags; /// Information about the type of the operand. uint8_t OperandType; /// The lower 16 bits are used to specify which constraints are set. /// The higher 16 bits are used to specify the value of constraints (4 bits each). uint32_t Constraints; /// Currently no other information. } MCOperandInfo; //===----------------------------------------------------------------------===// // Machine Instruction Flags and Description //===----------------------------------------------------------------------===// /// MCInstrDesc flags - These should be considered private to the /// implementation of the MCInstrDesc class. Clients should use the predicate /// methods on MCInstrDesc, not use these directly. These all correspond to /// bitfields in the MCInstrDesc::Flags field. enum { MCID_Variadic = 0, MCID_HasOptionalDef, MCID_Pseudo, MCID_Return, MCID_Call, MCID_Barrier, MCID_Terminator, MCID_Branch, MCID_IndirectBranch, MCID_Compare, MCID_MoveImm, MCID_MoveReg, MCID_Bitcast, MCID_Select, MCID_DelaySlot, MCID_FoldableAsLoad, MCID_MayLoad, MCID_MayStore, MCID_Predicable, MCID_NotDuplicable, MCID_UnmodeledSideEffects, MCID_Commutable, MCID_ConvertibleTo3Addr, MCID_UsesCustomInserter, MCID_HasPostISelHook, MCID_Rematerializable, MCID_CheapAsAMove, MCID_ExtraSrcRegAllocReq, MCID_ExtraDefRegAllocReq, MCID_RegSequence, MCID_ExtractSubreg, MCID_InsertSubreg, MCID_Convergent, MCID_Add, MCID_Trap, }; /// MCInstrDesc - Describe properties that are true of each instruction in the /// target description file. This captures information about side effects, /// register use and many other things. There is one instance of this struct /// for each target instruction class, and the MachineInstr class points to /// this struct directly to describe itself. typedef struct MCInstrDesc { unsigned char NumOperands; // Num of args (may be more if variable_ops) const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands } MCInstrDesc; bool MCOperandInfo_isPredicate(const MCOperandInfo *m); bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m); #endif capstone-sys-0.15.0/capstone/MCRegisterInfo.c000064400000000000000000000067450072674642500172030ustar 00000000000000//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file implements MCRegisterInfo functions. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #include "MCRegisterInfo.h" /// DiffListIterator - Base iterator class that can traverse the /// differentially encoded register and regunit lists in DiffLists. /// Don't use this class directly, use one of the specialized sub-classes /// defined below. typedef struct DiffListIterator { uint16_t Val; const MCPhysReg *List; } DiffListIterator; void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, uint16_t (*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const char *Strings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET) { RI->Desc = D; RI->NumRegs = NR; RI->RAReg = RA; RI->PCReg = PC; RI->Classes = C; RI->DiffLists = DL; RI->RegStrings = Strings; RI->NumClasses = NC; RI->RegUnitRoots = RURoots; RI->NumRegUnits = NRU; RI->SubRegIndices = SubIndices; RI->NumSubRegIndices = NumIndices; RI->RegEncodingTable = RET; } static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList) { d->Val = InitVal; d->List = DiffList; } static uint16_t DiffListIterator_getVal(DiffListIterator *d) { return d->Val; } static bool DiffListIterator_next(DiffListIterator *d) { MCPhysReg D; if (d->List == 0) return false; D = *d->List; d->List++; d->Val += D; if (!D) d->List = 0; return (D != 0); } static bool DiffListIterator_isValid(DiffListIterator *d) { return (d->List != 0); } unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) { DiffListIterator iter; if (Reg >= RI->NumRegs) { return 0; } DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); DiffListIterator_next(&iter); while(DiffListIterator_isValid(&iter)) { uint16_t val = DiffListIterator_getVal(&iter); if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) return val; DiffListIterator_next(&iter); } return 0; } unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx) { DiffListIterator iter; const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); DiffListIterator_next(&iter); while(DiffListIterator_isValid(&iter)) { if (*SRI == Idx) return DiffListIterator_getVal(&iter); DiffListIterator_next(&iter); ++SRI; } return 0; } const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i) { //assert(i < getNumRegClasses() && "Register Class ID out of range"); if (i >= RI->NumClasses) return 0; return &(RI->Classes[i]); } bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) { unsigned InByte = Reg % 8; unsigned Byte = Reg / 8; if (Byte >= c->RegSetSize) return false; return (c->RegSet[Byte] & (1 << InByte)) != 0; } capstone-sys-0.15.0/capstone/MCRegisterInfo.h000064400000000000000000000114430072674642500171770ustar 00000000000000//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file describes an abstract interface used to get information about a // target machines register file. This information is used for a variety of // purposed, especially register allocation. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_MC_MCREGISTERINFO_H #define CS_LLVM_MC_MCREGISTERINFO_H #include "capstone/platform.h" /// An unsigned integer type large enough to represent all physical registers, /// but not necessarily virtual registers. typedef uint16_t MCPhysReg; typedef const MCPhysReg* iterator; typedef struct MCRegisterClass2 { iterator RegsBegin; const uint8_t *RegSet; uint8_t RegsSize; uint8_t RegSetSize; } MCRegisterClass2; typedef struct MCRegisterClass { iterator RegsBegin; const uint8_t *RegSet; uint16_t RegSetSize; } MCRegisterClass; /// MCRegisterDesc - This record contains information about a particular /// register. The SubRegs field is a zero terminated array of registers that /// are sub-registers of the specific register, e.g. AL, AH are sub-registers /// of AX. The SuperRegs field is a zero terminated array of registers that are /// super-registers of AX. typedef struct MCRegisterDesc { uint32_t Name; // Printable name for the reg (for debugging) uint32_t SubRegs; // Sub-register set, described above uint32_t SuperRegs; // Super-register set, described above // Offset into MCRI::SubRegIndices of a list of sub-register indices for each // sub-register in SubRegs. uint32_t SubRegIndices; // RegUnits - Points to the list of register units. The low 4 bits holds the // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. uint32_t RegUnits; /// Index into list with lane mask sequences. The sequence contains a lanemask /// for every register unit. uint16_t RegUnitLaneMasks; // ??? } MCRegisterDesc; /// MCRegisterInfo base class - We assume that the target defines a static /// array of MCRegisterDesc objects that represent all of the machine /// registers that the target has. As such, we simply have to track a pointer /// to this array so that we can turn register number into a register /// descriptor. /// /// Note this class is designed to be a base class of TargetRegisterInfo, which /// is the interface used by codegen. However, specific targets *should never* /// specialize this class. MCRegisterInfo should only contain getters to access /// TableGen generated physical register data. It must not be extended with /// virtual methods. typedef struct MCRegisterInfo { const MCRegisterDesc *Desc; // Pointer to the descriptor array unsigned NumRegs; // Number of entries in the array unsigned RAReg; // Return address register unsigned PCReg; // Program counter register const MCRegisterClass *Classes; // Pointer to the regclass array unsigned NumClasses; // Number of entries in the array unsigned NumRegUnits; // Number of regunits. uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. const MCPhysReg *DiffLists; // Pointer to the difflists array // const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences const char *RegStrings; // Pointer to the string table. // const char *RegClassStrings; // Pointer to the class strings. const uint16_t *SubRegIndices; // Pointer to the subreg lookup // array. unsigned NumSubRegIndices; // Number of subreg indices. const uint16_t *RegEncodingTable; // Pointer to array of register // encodings. } MCRegisterInfo; void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, uint16_t (*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const char *Strings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET); unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC); unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx); const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i); bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); #endif capstone-sys-0.15.0/capstone/Makefile000064400000000000000000000361120072674642500156460ustar 00000000000000# Capstone Disassembly Engine # By Nguyen Anh Quynh , 2013-2014 include config.mk include pkgconfig.mk # package version include functions.mk # Verbose output? V ?= 0 OS := $(shell uname) ifeq ($(OS),Darwin) LIBARCHS ?= x86_64 PREFIX ?= /usr/local endif ifeq ($(PKG_EXTRA),) PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR) else PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) endif ifeq ($(CROSS),) RANLIB ?= ranlib else ifeq ($(ANDROID), 1) CC = $(CROSS)/../../bin/clang AR = $(CROSS)/ar RANLIB = $(CROSS)/ranlib STRIP = $(CROSS)/strip else CC = $(CROSS)gcc AR = $(CROSS)ar RANLIB = $(CROSS)ranlib STRIP = $(CROSS)strip endif ifeq ($(OS),OS/390) RANLIB = touch endif ifneq (,$(findstring yes,$(CAPSTONE_DIET))) CFLAGS ?= -Os CFLAGS += -DCAPSTONE_DIET else CFLAGS ?= -O3 endif ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) CFLAGS += -DCAPSTONE_X86_ATT_DISABLE endif ifeq ($(CC),xlc) CFLAGS += -qcpluscmt -qkeyword=inline -qlanglvl=extc1x -Iinclude ifneq ($(OS),OS/390) CFLAGS += -fPIC endif else CFLAGS += -fPIC -Wall -Wwrite-strings -Wmissing-prototypes -Iinclude endif ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM endif ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes) CFLAGS += -DCAPSTONE_HAS_OSXKERNEL SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path) CFLAGS += -mmacosx-version-min=10.5 \ -isysroot$(SDKROOT) \ -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \ -mkernel \ -fno-builtin endif PREFIX ?= /usr DESTDIR ?= ifndef BUILDDIR BLDIR = . OBJDIR = . else BLDIR = $(abspath $(BUILDDIR)) OBJDIR = $(BLDIR)/obj endif INCDIR ?= $(PREFIX)/include UNAME_S := $(shell uname -s) LIBDIRARCH ?= lib # Uncomment the below line to installs x86_64 libs to lib64/ directory. # Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'. #LIBDIRARCH ?= lib64 LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH) BINDIR = $(DESTDIR)$(PREFIX)/bin LIBDATADIR = $(LIBDIR) # Don't redefine $LIBDATADIR when global environment variable # USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework. ifndef USE_GENERIC_LIBDATADIR ifeq ($(UNAME_S), FreeBSD) LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata endif ifeq ($(UNAME_S), DragonFly) LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata endif endif INSTALL_BIN ?= install INSTALL_DATA ?= $(INSTALL_BIN) -m0644 INSTALL_LIB ?= $(INSTALL_BIN) -m0755 LIBNAME = capstone DEP_ARM = DEP_ARM += $(wildcard arch/ARM/ARM*.inc) LIBOBJ_ARM = ifneq (,$(findstring arm,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_ARM LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c) LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o) endif DEP_ARM64 = DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc) LIBOBJ_ARM64 = ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_ARM64 LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c) LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o) endif DEP_M68K = DEP_M68K += $(wildcard arch/M68K/M68K*.inc) DEP_M68K += $(wildcard arch/M68K/M68K*.h) LIBOBJ_M68K = ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_M68K LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c) LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o) endif DEP_MIPS = DEP_MIPS += $(wildcard arch/Mips/Mips*.inc) LIBOBJ_MIPS = ifneq (,$(findstring mips,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_MIPS LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c) LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o) endif DEP_PPC = DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc) LIBOBJ_PPC = ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_POWERPC LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c) LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o) endif DEP_SPARC = DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc) LIBOBJ_SPARC = ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_SPARC LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c) LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o) endif DEP_SYSZ = DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc) LIBOBJ_SYSZ = ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_SYSZ LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c) LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o) endif # by default, we compile full X86 instruction sets X86_REDUCE = ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE))) X86_REDUCE = _reduce CFLAGS += -DCAPSTONE_X86_REDUCE -Os endif DEP_X86 = DEP_X86 += $(wildcard arch/X86/X86*.inc) LIBOBJ_X86 = ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_X86 LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86InstPrinterCommon.o LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o # assembly syntax is irrelevant in Diet mode, when this info is suppressed ifeq (,$(findstring yes,$(CAPSTONE_DIET))) ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o endif endif LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o endif DEP_XCORE = DEP_XCORE += $(wildcard arch/XCore/XCore*.inc) LIBOBJ_XCORE = ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_XCORE LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c) LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o) endif DEP_TMS320C64X = DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc) LIBOBJ_TMS320C64X = ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_TMS320C64X LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c) LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o) endif DEP_M680X = DEP_M680X += $(wildcard arch/M680X/*.inc) DEP_M680X += $(wildcard arch/M680X/M680X*.h) LIBOBJ_M680X = ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_M680X LIBSRC_M680X += $(wildcard arch/M680X/*.c) LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o) endif DEP_EVM = DEP_EVM += $(wildcard arch/EVM/EVM*.inc) LIBOBJ_EVM = ifneq (,$(findstring evm,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_EVM LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c) LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o) endif DEP_RISCV = DEP_RISCV += $(wildcard arch/RISCV/RISCV*.inc) LIBOBJ_RISCV = ifneq (,$(findstring riscv,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_RISCV LIBSRC_RISCV += $(wildcard arch/RISCV/RISCV*.c) LIBOBJ_RISCV += $(LIBSRC_RISCV:%.c=$(OBJDIR)/%.o) endif DEP_WASM = DEP_WASM += $(wildcard arch/WASM/WASM*.inc) LIBOBJ_WASM = ifneq (,$(findstring wasm,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_WASM LIBSRC_WASM += $(wildcard arch/WASM/WASM*.c) LIBOBJ_WASM += $(LIBSRC_WASM:%.c=$(OBJDIR)/%.o) endif DEP_MOS65XX = DEP_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.inc) LIBOBJ_MOS65XX = ifneq (,$(findstring mos65xx,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_MOS65XX LIBSRC_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.c) LIBOBJ_MOS65XX += $(LIBSRC_MOS65XX:%.c=$(OBJDIR)/%.o) endif DEP_BPF = DEP_BPF += $(wildcard arch/BPF/BPF*.inc) LIBOBJ_BPF = ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_BPF LIBSRC_BPF += $(wildcard arch/BPF/BPF*.c) LIBOBJ_BPF += $(LIBSRC_BPF:%.c=$(OBJDIR)/%.o) endif LIBOBJ = LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF) LIBOBJ += $(OBJDIR)/MCInst.o ifeq ($(PKG_EXTRA),) PKGCFGDIR = $(LIBDATADIR)/pkgconfig else PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig ifeq ($(PKGCFGDIR),) PKGCFGDIR = $(LIBDATADIR)/pkgconfig endif endif API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}') VERSION_EXT = IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ") ifeq ($(IS_APPLE),1) # on MacOS, do not build in Universal format by default MACOS_UNIVERSAL ?= no ifeq ($(MACOS_UNIVERSAL),yes) CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) endif EXT = dylib VERSION_EXT = $(API_MAJOR).$(EXT) $(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) AR_EXT = a # Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE # However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default ifneq ($(HOMEBREW_CAPSTONE),1) ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) # remove string check because OSX kernel complains about missing symbols CFLAGS += -D_FORTIFY_SOURCE=0 endif endif else CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) ifeq ($(OS), AIX) $(LIBNAME)_LDFLAGS += -qmkshrobj else $(LIBNAME)_LDFLAGS += -shared endif # Cygwin? IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l) ifeq ($(IS_CYGWIN),1) EXT = dll AR_EXT = lib # Cygwin doesn't like -fPIC CFLAGS := $(CFLAGS:-fPIC=) # On Windows we need the shared library to be executable else # mingw? IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) ifeq ($(IS_MINGW),1) EXT = dll AR_EXT = lib # mingw doesn't like -fPIC either CFLAGS := $(CFLAGS:-fPIC=) # On Windows we need the shared library to be executable else # Linux, *BSD EXT = so VERSION_EXT = $(EXT).$(API_MAJOR) AR_EXT = a $(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT) endif endif endif ifeq ($(CAPSTONE_SHARED),yes) ifeq ($(IS_MINGW),1) LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT) else ifeq ($(IS_CYGWIN),1) LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT) else # *nix LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT) CFLAGS += -fvisibility=hidden endif endif ifeq ($(CAPSTONE_STATIC),yes) ifeq ($(IS_MINGW),1) ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) else ifeq ($(IS_CYGWIN),1) ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) else ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT) endif endif PKGCFGF = $(BLDIR)/$(LIBNAME).pc .PHONY: all clean install uninstall dist all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF) ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) @V=$(V) CC=$(CC) $(MAKE) -C cstool ifndef BUILDDIR $(MAKE) -C tests $(MAKE) -C suite/fuzz else $(MAKE) -C tests BUILDDIR=$(BLDIR) $(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR) endif $(call install-library,$(BLDIR)/tests/) endif ifeq ($(CAPSTONE_SHARED),yes) $(LIBRARY): $(LIBOBJ) ifeq ($(V),0) $(call log,LINK,$(@:$(BLDIR)/%=%)) @$(create-library) else $(create-library) endif endif $(LIBOBJ): config.mk $(LIBOBJ_ARM): $(DEP_ARM) $(LIBOBJ_ARM64): $(DEP_ARM64) $(LIBOBJ_M68K): $(DEP_M68K) $(LIBOBJ_MIPS): $(DEP_MIPS) $(LIBOBJ_PPC): $(DEP_PPC) $(LIBOBJ_SPARC): $(DEP_SPARC) $(LIBOBJ_SYSZ): $(DEP_SYSZ) $(LIBOBJ_X86): $(DEP_X86) $(LIBOBJ_XCORE): $(DEP_XCORE) $(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X) $(LIBOBJ_M680X): $(DEP_M680X) $(LIBOBJ_EVM): $(DEP_EVM) $(LIBOBJ_RISCV): $(DEP_RISCV) $(LIBOBJ_WASM): $(DEP_WASM) $(LIBOBJ_MOS65XX): $(DEP_MOS65XX) $(LIBOBJ_BPF): $(DEP_BPF) ifeq ($(CAPSTONE_STATIC),yes) $(ARCHIVE): $(LIBOBJ) @rm -f $(ARCHIVE) ifeq ($(V),0) $(call log,AR,$(@:$(BLDIR)/%=%)) @$(create-archive) else $(create-archive) endif endif $(PKGCFGF): ifeq ($(V),0) $(call log,GEN,$(@:$(BLDIR)/%=%)) @$(generate-pkgcfg) else $(generate-pkgcfg) endif # create a list of auto dependencies AUTODEPS:= $(patsubst %.o,%.d, $(LIBOBJ)) # include by auto dependencies -include $(AUTODEPS) install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY) mkdir -p $(LIBDIR) $(call install-library,$(LIBDIR)) ifeq ($(CAPSTONE_STATIC),yes) $(INSTALL_DATA) $(ARCHIVE) $(LIBDIR) endif mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME) $(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME) mkdir -p $(PKGCFGDIR) $(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR) ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) mkdir -p $(BINDIR) $(INSTALL_LIB) cstool/cstool $(BINDIR) endif uninstall: rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME) rm -f $(LIBDIR)/lib$(LIBNAME).* rm -f $(PKGCFGDIR)/$(LIBNAME).pc ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) rm -f $(BINDIR)/cstool endif clean: rm -f $(LIBOBJ) rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc rm -f $(PKGCFGF) rm -f $(AUTODEPS) [ "${ANDROID}" = "1" ] && rm -rf android-ndk-* || true ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) $(MAKE) -C cstool clean $(MAKE) -C tests clean $(MAKE) -C suite/fuzz clean rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT) endif ifdef BUILDDIR rm -rf $(BUILDDIR) endif ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) $(MAKE) -C bindings/python clean $(MAKE) -C bindings/java clean $(MAKE) -C bindings/ocaml clean endif TAG ?= HEAD ifeq ($(TAG), HEAD) DIST_VERSION = latest else DIST_VERSION = $(TAG) endif dist: git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static TESTS += test_mos65xx.static test_wasm.static test_bpf.static check: $(TESTS) fuzztest fuzzallcorp test_%: ./tests/$@ > /dev/null && echo OK || echo FAILED FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs') fuzztest: ./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS) fuzzallcorp: ifneq ($(wildcard suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest),) ./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/ > fuzz_bindisasm.log || (tail -1 fuzz_bindisasm.log; false) else @echo "Skipping tests on whole corpus" endif $(OBJDIR)/%.o: %.c @mkdir -p $(@D) ifeq ($(V),0) $(call log,CC,$(@:$(OBJDIR)/%=%)) @$(compile) else $(compile) endif ifeq ($(CAPSTONE_SHARED),yes) define install-library $(INSTALL_LIB) $(LIBRARY) $1 $(if $(VERSION_EXT), cd $1 && \ rm -f lib$(LIBNAME).$(EXT) && \ ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT)) endef else define install-library endef endif ifeq ($(AR_FLAGS),) AR_FLAGS := q endif define create-archive $(AR) $(AR_FLAGS) $(ARCHIVE) $(LIBOBJ) $(RANLIB) $(ARCHIVE) endef define create-library $(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY) endef define generate-pkgcfg mkdir -p $(BLDIR) echo 'Name: capstone' > $(PKGCFGF) echo 'Description: Capstone disassembly engine' >> $(PKGCFGF) echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF) echo 'libdir=$(LIBDIR)' >> $(PKGCFGF) echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF) echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF) echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF) echo 'Cflags: -I$${includedir}' >> $(PKGCFGF) endef capstone-sys-0.15.0/capstone/MathExtras.h000064400000000000000000000335010072674642500164360ustar 00000000000000//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains some functions that are useful for math stuff. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H #define CS_LLVM_SUPPORT_MATHEXTRAS_H #if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) #include "windowsce/intrin.h" #elif defined(_MSC_VER) #include #endif #ifndef __cplusplus #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #define inline /* inline */ #endif #endif // NOTE: The following support functions use the _32/_64 extensions instead of // type overloading so that signed and unsigned integers can be used without // ambiguity. /// Hi_32 - This function returns the high 32 bits of a 64 bit value. static inline uint32_t Hi_32(uint64_t Value) { return (uint32_t)(Value >> 32); } /// Lo_32 - This function returns the low 32 bits of a 64 bit value. static inline uint32_t Lo_32(uint64_t Value) { return (uint32_t)(Value); } /// isUIntN - Checks if an unsigned integer fits into the given (dynamic) /// bit width. static inline bool isUIntN(unsigned N, uint64_t x) { return x == (x & (~0ULL >> (64 - N))); } /// isIntN - Checks if an signed integer fits into the given (dynamic) /// bit width. //static inline bool isIntN(unsigned N, int64_t x) { // return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1))); //} /// isMask_32 - This function returns true if the argument is a sequence of ones /// starting at the least significant bit with the remainder zero (32 bit /// version). Ex. isMask_32(0x0000FFFFU) == true. static inline bool isMask_32(uint32_t Value) { return Value && ((Value + 1) & Value) == 0; } /// isMask_64 - This function returns true if the argument is a sequence of ones /// starting at the least significant bit with the remainder zero (64 bit /// version). static inline bool isMask_64(uint64_t Value) { return Value && ((Value + 1) & Value) == 0; } /// isShiftedMask_32 - This function returns true if the argument contains a /// sequence of ones with the remainder zero (32 bit version.) /// Ex. isShiftedMask_32(0x0000FF00U) == true. static inline bool isShiftedMask_32(uint32_t Value) { return isMask_32((Value - 1) | Value); } /// isShiftedMask_64 - This function returns true if the argument contains a /// sequence of ones with the remainder zero (64 bit version.) static inline bool isShiftedMask_64(uint64_t Value) { return isMask_64((Value - 1) | Value); } /// isPowerOf2_32 - This function returns true if the argument is a power of /// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.) static inline bool isPowerOf2_32(uint32_t Value) { return Value && !(Value & (Value - 1)); } /// CountLeadingZeros_32 - this function performs the platform optimal form of /// counting the number of zeros from the most significant bit to the first one /// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8. /// Returns 32 if the word is zero. static inline unsigned CountLeadingZeros_32(uint32_t Value) { unsigned Count; // result #if __GNUC__ >= 4 // PowerPC is defined for __builtin_clz(0) #if !defined(__ppc__) && !defined(__ppc64__) if (!Value) return 32; #endif Count = __builtin_clz(Value); #else unsigned Shift; if (!Value) return 32; Count = 0; // bisection method for count leading zeros for (Shift = 32 >> 1; Shift; Shift >>= 1) { uint32_t Tmp = Value >> Shift; if (Tmp) { Value = Tmp; } else { Count |= Shift; } } #endif return Count; } /// CountLeadingOnes_32 - this function performs the operation of /// counting the number of ones from the most significant bit to the first zero /// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8. /// Returns 32 if the word is all ones. static inline unsigned CountLeadingOnes_32(uint32_t Value) { return CountLeadingZeros_32(~Value); } /// CountLeadingZeros_64 - This function performs the platform optimal form /// of counting the number of zeros from the most significant bit to the first /// one bit (64 bit edition.) /// Returns 64 if the word is zero. static inline unsigned CountLeadingZeros_64(uint64_t Value) { unsigned Count; // result #if __GNUC__ >= 4 // PowerPC is defined for __builtin_clzll(0) #if !defined(__ppc__) && !defined(__ppc64__) if (!Value) return 64; #endif Count = __builtin_clzll(Value); #else #ifndef _MSC_VER unsigned Shift; if (sizeof(long) == sizeof(int64_t)) { if (!Value) return 64; Count = 0; // bisection method for count leading zeros for (Shift = 64 >> 1; Shift; Shift >>= 1) { uint64_t Tmp = Value >> Shift; if (Tmp) { Value = Tmp; } else { Count |= Shift; } } } else #endif { // get hi portion uint32_t Hi = Hi_32(Value); // if some bits in hi portion if (Hi) { // leading zeros in hi portion plus all bits in lo portion Count = CountLeadingZeros_32(Hi); } else { // get lo portion uint32_t Lo = Lo_32(Value); // same as 32 bit value Count = CountLeadingZeros_32(Lo)+32; } } #endif return Count; } /// CountLeadingOnes_64 - This function performs the operation /// of counting the number of ones from the most significant bit to the first /// zero bit (64 bit edition.) /// Returns 64 if the word is all ones. static inline unsigned CountLeadingOnes_64(uint64_t Value) { return CountLeadingZeros_64(~Value); } /// CountTrailingZeros_32 - this function performs the platform optimal form of /// counting the number of zeros from the least significant bit to the first one /// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8. /// Returns 32 if the word is zero. static inline unsigned CountTrailingZeros_32(uint32_t Value) { #if __GNUC__ >= 4 return Value ? __builtin_ctz(Value) : 32; #else static const unsigned Mod37BitPosition[] = { 32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5, 20, 8, 19, 18 }; // Replace "-Value" by "1+~Value" in the following commented code to avoid // MSVC warning C4146 // return Mod37BitPosition[(-Value & Value) % 37]; return Mod37BitPosition[((1 + ~Value) & Value) % 37]; #endif } /// CountTrailingOnes_32 - this function performs the operation of /// counting the number of ones from the least significant bit to the first zero /// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8. /// Returns 32 if the word is all ones. static inline unsigned CountTrailingOnes_32(uint32_t Value) { return CountTrailingZeros_32(~Value); } /// CountTrailingZeros_64 - This function performs the platform optimal form /// of counting the number of zeros from the least significant bit to the first /// one bit (64 bit edition.) /// Returns 64 if the word is zero. static inline unsigned CountTrailingZeros_64(uint64_t Value) { #if __GNUC__ >= 4 return Value ? __builtin_ctzll(Value) : 64; #else static const unsigned Mod67Position[] = { 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, 4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, 47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, 29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, 7, 48, 35, 6, 34, 33, 0 }; // Replace "-Value" by "1+~Value" in the following commented code to avoid // MSVC warning C4146 // return Mod67Position[(-Value & Value) % 67]; return Mod67Position[((1 + ~Value) & Value) % 67]; #endif } /// CountTrailingOnes_64 - This function performs the operation /// of counting the number of ones from the least significant bit to the first /// zero bit (64 bit edition.) /// Returns 64 if the word is all ones. static inline unsigned CountTrailingOnes_64(uint64_t Value) { return CountTrailingZeros_64(~Value); } /// CountPopulation_32 - this function counts the number of set bits in a value. /// Ex. CountPopulation(0xF000F000) = 8 /// Returns 0 if the word is zero. static inline unsigned CountPopulation_32(uint32_t Value) { #if __GNUC__ >= 4 return __builtin_popcount(Value); #else uint32_t v = Value - ((Value >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24; #endif } /// CountPopulation_64 - this function counts the number of set bits in a value, /// (64 bit edition.) static inline unsigned CountPopulation_64(uint64_t Value) { #if __GNUC__ >= 4 return __builtin_popcountll(Value); #else uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL); v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; return (uint64_t)((v * 0x0101010101010101ULL) >> 56); #endif } /// Log2_32 - This function returns the floor log base 2 of the specified value, /// -1 if the value is zero. (32 bit edition.) /// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 static inline unsigned Log2_32(uint32_t Value) { return 31 - CountLeadingZeros_32(Value); } /// Log2_64 - This function returns the floor log base 2 of the specified value, /// -1 if the value is zero. (64 bit edition.) static inline unsigned Log2_64(uint64_t Value) { return 63 - CountLeadingZeros_64(Value); } /// Log2_32_Ceil - This function returns the ceil log base 2 of the specified /// value, 32 if the value is zero. (32 bit edition). /// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3 static inline unsigned Log2_32_Ceil(uint32_t Value) { return 32-CountLeadingZeros_32(Value-1); } /// Log2_64_Ceil - This function returns the ceil log base 2 of the specified /// value, 64 if the value is zero. (64 bit edition.) static inline unsigned Log2_64_Ceil(uint64_t Value) { return 64-CountLeadingZeros_64(Value-1); } /// GreatestCommonDivisor64 - Return the greatest common divisor of the two /// values using Euclid's algorithm. static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) { while (B) { uint64_t T = B; B = A % B; A = T; } return A; } /// BitsToDouble - This function takes a 64-bit integer and returns the bit /// equivalent double. static inline double BitsToDouble(uint64_t Bits) { union { uint64_t L; double D; } T; T.L = Bits; return T.D; } /// BitsToFloat - This function takes a 32-bit integer and returns the bit /// equivalent float. static inline float BitsToFloat(uint32_t Bits) { union { uint32_t I; float F; } T; T.I = Bits; return T.F; } /// DoubleToBits - This function takes a double and returns the bit /// equivalent 64-bit integer. Note that copying doubles around /// changes the bits of NaNs on some hosts, notably x86, so this /// routine cannot be used if these bits are needed. static inline uint64_t DoubleToBits(double Double) { union { uint64_t L; double D; } T; T.D = Double; return T.L; } /// FloatToBits - This function takes a float and returns the bit /// equivalent 32-bit integer. Note that copying floats around /// changes the bits of NaNs on some hosts, notably x86, so this /// routine cannot be used if these bits are needed. static inline uint32_t FloatToBits(float Float) { union { uint32_t I; float F; } T; T.F = Float; return T.I; } /// MinAlign - A and B are either alignments or offsets. Return the minimum /// alignment that may be assumed after adding the two together. static inline uint64_t MinAlign(uint64_t A, uint64_t B) { // The largest power of 2 that divides both A and B. // // Replace "-Value" by "1+~Value" in the following commented code to avoid // MSVC warning C4146 // return (A | B) & -(A | B); return (A | B) & (1 + ~(A | B)); } /// NextPowerOf2 - Returns the next power of two (in 64-bits) /// that is strictly greater than A. Returns zero on overflow. static inline uint64_t NextPowerOf2(uint64_t A) { A |= (A >> 1); A |= (A >> 2); A |= (A >> 4); A |= (A >> 8); A |= (A >> 16); A |= (A >> 32); return A + 1; } /// Returns the next integer (mod 2**64) that is greater than or equal to /// \p Value and is a multiple of \p Align. \p Align must be non-zero. /// /// Examples: /// \code /// RoundUpToAlignment(5, 8) = 8 /// RoundUpToAlignment(17, 8) = 24 /// RoundUpToAlignment(~0LL, 8) = 0 /// \endcode static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) { return ((Value + Align - 1) / Align) * Align; } /// Returns the offset to the next integer (mod 2**64) that is greater than /// or equal to \p Value and is a multiple of \p Align. \p Align must be /// non-zero. static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { return RoundUpToAlignment(Value, Align) - Value; } /// abs64 - absolute value of a 64-bit int. Not all environments support /// "abs" on whatever their name for the 64-bit int type is. The absolute /// value of the largest negative number is undefined, as with "abs". static inline int64_t abs64(int64_t x) { return (x < 0) ? -x : x; } /// \brief Sign extend number in the bottom B bits of X to a 32-bit int. /// Requires 0 < B <= 32. static inline int32_t SignExtend32(uint32_t X, unsigned B) { return (int32_t)(X << (32 - B)) >> (32 - B); } /// \brief Sign extend number in the bottom B bits of X to a 64-bit int. /// Requires 0 < B <= 64. static inline int64_t SignExtend64(uint64_t X, unsigned B) { return (int64_t)(X << (64 - B)) >> (64 - B); } /// \brief Count number of 0's from the most significant bit to the least /// stopping at the first 1. /// /// Only unsigned integral types are allowed. /// /// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are /// valid arguments. static inline unsigned int countLeadingZeros(int x) { int i; const unsigned bits = sizeof(x) * 8; unsigned count = bits; if (x < 0) { return 0; } for (i = bits; --i; ) { if (x == 0) break; count--; x >>= 1; } return count; } #endif capstone-sys-0.15.0/capstone/README.md000064400000000000000000000051120072674642500154610ustar 00000000000000Capstone Engine =============== [![Build Status](https://travis-ci.org/aquynh/capstone.svg?branch=next)](https://travis-ci.org/aquynh/capstone) [![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/next?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/next) [![pypi package](https://badge.fury.io/py/capstone.svg)](https://pypi.python.org/pypi/capstone) [![pypi downloads](https://pepy.tech/badge/capstone)](https://pepy.tech/project/capstone) [![Fuzzit Status](https://app.fuzzit.dev/badge?org_id=ANOh0D48gSLBxNZcDQMI&branch=master)](https://app.fuzzit.dev/admin/ANOh0D48gSLBxNZcDQMI/dashboard)
Capstone is a disassembly framework with the target of becoming the ultimate disasm engine for binary analysis and reversing in the security community. Created by Nguyen Anh Quynh, then developed and maintained by a small community, Capstone offers some unparalleled features: - Support multiple hardware architectures: ARM, ARM64 (ARMv8), BPF, Ethereum VM, Webassembly, M68K, Mips, MOS65XX, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore, RISC-V(rv32G/rv64G) and X86 (including X86_64). - Having clean/simple/lightweight/intuitive architecture-neutral API. - Provide details on disassembled instruction (called “decomposer” by others). - Provide semantics of the disassembled instruction, such as list of implicit registers read & written. - Implemented in pure C language, with lightweight bindings for Swift, D, Clojure, F#, Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala ready either in main code, or provided externally by the community). - Native support for all popular platforms: Windows, Mac OSX, iOS, Android, Linux, \*BSD, Solaris, etc. - Thread-safe by design. - Special support for embedding into firmware or OS kernel. - High performance & suitable for malware analysis (capable of handling various X86 malware tricks). - Distributed under the open source BSD license. Further information is available at http://www.capstone-engine.org Compile ------- See COMPILE.TXT file for how to compile and install Capstone. Documentation ------------- See docs/README for how to customize & program your own tools with Capstone. Hack ---- See HACK.TXT file for the structure of the source code. Fuzz ---- See suite/fuzz/README.md for more information. License ------- This project is released under the BSD license. If you redistribute the binary or source code of Capstone, please attach file LICENSE.TXT with your products. capstone-sys-0.15.0/capstone/RELEASE_NOTES000064400000000000000000000000000072674642500161440ustar 00000000000000capstone-sys-0.15.0/capstone/SPONSORS.TXT000064400000000000000000000011750072674642500160760ustar 00000000000000* Version 4.0.1 - January 10th, 2019 Release 4.0.1 was sponsored by the following companies (in no particular order). - NowSecure: https://www.nowsecure.com - Verichains: https://verichains.io - Vsec: https://vsec.com.vn ----------------------------------- * Version 4.0 - December 18th, 2018 Capstone 4.0 version marks 5 years of the project! This release was sponsored by the following companies (in no particular order). - Thinkst Canary: https://canary.tools - NowSecure: https://www.nowsecure.com - ECQ: https://e-cq.net - Senrio: https://senr.io - GracefulBits: https://gracefulbits.com - Catena Cyber: https://catenacyber.fr capstone-sys-0.15.0/capstone/SStream.c000064400000000000000000000071540072674642500157340ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include #include #else #include #include #endif #include #include #include "SStream.h" #include "cs_priv.h" #include "utils.h" #ifdef _MSC_VER #pragma warning(disable: 4996) // disable MSVC's warning on strcpy() #endif void SStream_Init(SStream *ss) { ss->index = 0; ss->buffer[0] = '\0'; } void SStream_concat0(SStream *ss, const char *s) { #ifndef CAPSTONE_DIET unsigned int len = (unsigned int) strlen(s); memcpy(ss->buffer + ss->index, s, len); ss->index += len; ss->buffer[ss->index] = '\0'; #endif } void SStream_concat1(SStream *ss, const char c) { #ifndef CAPSTONE_DIET ss->buffer[ss->index] = c; ss->index++; ss->buffer[ss->index] = '\0'; #endif } void SStream_concat(SStream *ss, const char *fmt, ...) { #ifndef CAPSTONE_DIET va_list ap; int ret; va_start(ap, fmt); ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap); va_end(ap); ss->index += ret; #endif } // print number with prefix # void printInt64Bang(SStream *O, int64_t val) { if (val >= 0) { if (val > HEX_THRESHOLD) SStream_concat(O, "#0x%"PRIx64, val); else SStream_concat(O, "#%"PRIu64, val); } else { if (val <- HEX_THRESHOLD) { if (val == LONG_MIN) SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val); else SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val); } else SStream_concat(O, "#-%"PRIu64, -val); } } void printUInt64Bang(SStream *O, uint64_t val) { if (val > HEX_THRESHOLD) SStream_concat(O, "#0x%"PRIx64, val); else SStream_concat(O, "#%"PRIu64, val); } // print number void printInt64(SStream *O, int64_t val) { if (val >= 0) { if (val > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, val); else SStream_concat(O, "%"PRIu64, val); } else { if (val <- HEX_THRESHOLD) { if (val == LONG_MIN) SStream_concat(O, "-0x%"PRIx64, (uint64_t)val); else SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val); } else SStream_concat(O, "-%"PRIu64, -val); } } void printUInt64(SStream *O, uint64_t val) { if (val > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, val); else SStream_concat(O, "%"PRIu64, val); } // print number in decimal mode void printInt32BangDec(SStream *O, int32_t val) { if (val >= 0) SStream_concat(O, "#%u", val); else { if (val == INT_MIN) SStream_concat(O, "#-%u", val); else SStream_concat(O, "#-%u", (uint32_t)-val); } } void printInt32Bang(SStream *O, int32_t val) { if (val >= 0) { if (val > HEX_THRESHOLD) SStream_concat(O, "#0x%x", val); else SStream_concat(O, "#%u", val); } else { if (val <- HEX_THRESHOLD) { if (val == INT_MIN) SStream_concat(O, "#-0x%x", (uint32_t)val); else SStream_concat(O, "#-0x%x", (uint32_t)-val); } else SStream_concat(O, "#-%u", -val); } } void printInt32(SStream *O, int32_t val) { if (val >= 0) { if (val > HEX_THRESHOLD) SStream_concat(O, "0x%x", val); else SStream_concat(O, "%u", val); } else { if (val <- HEX_THRESHOLD) { if (val == INT_MIN) SStream_concat(O, "-0x%x", (uint32_t)val); else SStream_concat(O, "-0x%x", (uint32_t)-val); } else SStream_concat(O, "-%u", -val); } } void printUInt32Bang(SStream *O, uint32_t val) { if (val > HEX_THRESHOLD) SStream_concat(O, "#0x%x", val); else SStream_concat(O, "#%u", val); } void printUInt32(SStream *O, uint32_t val) { if (val > HEX_THRESHOLD) SStream_concat(O, "0x%x", val); else SStream_concat(O, "%u", val); } capstone-sys-0.15.0/capstone/SStream.h000064400000000000000000000015730072674642500157400ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_SSTREAM_H_ #define CS_SSTREAM_H_ #include "include/capstone/platform.h" typedef struct SStream { char buffer[512]; int index; } SStream; void SStream_Init(SStream *ss); void SStream_concat(SStream *ss, const char *fmt, ...); void SStream_concat0(SStream *ss, const char *s); void SStream_concat1(SStream *ss, const char c); void printInt64Bang(SStream *O, int64_t val); void printUInt64Bang(SStream *O, uint64_t val); void printInt64(SStream *O, int64_t val); void printUInt64(SStream *O, uint64_t val); void printInt32Bang(SStream *O, int32_t val); void printInt32(SStream *O, int32_t val); void printUInt32Bang(SStream *O, uint32_t val); void printUInt32(SStream *O, uint32_t val); // print number in decimal mode void printInt32BangDec(SStream *O, int32_t val); #endif capstone-sys-0.15.0/capstone/TODO000064400000000000000000000006530072674642500146770ustar 00000000000000Issues to be solved in next versions [Core] - X86 can already handle all the malware tricks we are aware of. If you find any such instruction sequence that Capstone disassembles wrongly or fails completely, please report. Fixing this issue is always the top priority of our project. - More optimization for better performance. [Bindings] - OCaml binding is working, but still needs to support the core API better. capstone-sys-0.15.0/capstone/arch/AArch64/AArch64AddressingModes.h000064400000000000000000000601250072674642500225510ustar 00000000000000//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains the AArch64 addressing mode implementation stuff. // //===----------------------------------------------------------------------===// #ifndef CS_AARCH64_ADDRESSINGMODES_H #define CS_AARCH64_ADDRESSINGMODES_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #include "../../MathExtras.h" /// AArch64_AM - AArch64 Addressing Mode Stuff //===----------------------------------------------------------------------===// // Shifts // typedef enum AArch64_AM_ShiftExtendType { AArch64_AM_InvalidShiftExtend = -1, AArch64_AM_LSL = 0, AArch64_AM_LSR, AArch64_AM_ASR, AArch64_AM_ROR, AArch64_AM_MSL, AArch64_AM_UXTB, AArch64_AM_UXTH, AArch64_AM_UXTW, AArch64_AM_UXTX, AArch64_AM_SXTB, AArch64_AM_SXTH, AArch64_AM_SXTW, AArch64_AM_SXTX, } AArch64_AM_ShiftExtendType; /// getShiftName - Get the string encoding for the shift type. static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST) { switch (ST) { default: return NULL; // never reach case AArch64_AM_LSL: return "lsl"; case AArch64_AM_LSR: return "lsr"; case AArch64_AM_ASR: return "asr"; case AArch64_AM_ROR: return "ror"; case AArch64_AM_MSL: return "msl"; case AArch64_AM_UXTB: return "uxtb"; case AArch64_AM_UXTH: return "uxth"; case AArch64_AM_UXTW: return "uxtw"; case AArch64_AM_UXTX: return "uxtx"; case AArch64_AM_SXTB: return "sxtb"; case AArch64_AM_SXTH: return "sxth"; case AArch64_AM_SXTW: return "sxtw"; case AArch64_AM_SXTX: return "sxtx"; } } /// getShiftType - Extract the shift type. static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) { switch ((Imm >> 6) & 0x7) { default: return AArch64_AM_InvalidShiftExtend; case 0: return AArch64_AM_LSL; case 1: return AArch64_AM_LSR; case 2: return AArch64_AM_ASR; case 3: return AArch64_AM_ROR; case 4: return AArch64_AM_MSL; } } /// getShiftValue - Extract the shift value. static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) { return Imm & 0x3f; } static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, unsigned Imm) { // assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); unsigned STEnc = 0; switch (ST) { default: // llvm_unreachable("Invalid shift requested"); case AArch64_AM_LSL: STEnc = 0; break; case AArch64_AM_LSR: STEnc = 1; break; case AArch64_AM_ASR: STEnc = 2; break; case AArch64_AM_ROR: STEnc = 3; break; case AArch64_AM_MSL: STEnc = 4; break; } return (STEnc << 6) | (Imm & 0x3f); } //===----------------------------------------------------------------------===// // Extends // /// getArithShiftValue - get the arithmetic shift value. static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) { return Imm & 0x7; } /// getExtendType - Extract the extend type for operands of arithmetic ops. static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm) { // assert((Imm & 0x7) == Imm && "invalid immediate!"); switch (Imm) { default: // llvm_unreachable("Compiler bug!"); case 0: return AArch64_AM_UXTB; case 1: return AArch64_AM_UXTH; case 2: return AArch64_AM_UXTW; case 3: return AArch64_AM_UXTX; case 4: return AArch64_AM_SXTB; case 5: return AArch64_AM_SXTH; case 6: return AArch64_AM_SXTW; case 7: return AArch64_AM_SXTX; } } static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm) { return AArch64_AM_getExtendType((Imm >> 3) & 0x7); } /// Mapping from extend bits to required operation: /// shifter: 000 ==> uxtb /// 001 ==> uxth /// 010 ==> uxtw /// 011 ==> uxtx /// 100 ==> sxtb /// 101 ==> sxth /// 110 ==> sxtw /// 111 ==> sxtx static inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET) { switch (ET) { default: // llvm_unreachable("Invalid extend type requested"); case AArch64_AM_UXTB: return 0; break; case AArch64_AM_UXTH: return 1; break; case AArch64_AM_UXTW: return 2; break; case AArch64_AM_UXTX: return 3; break; case AArch64_AM_SXTB: return 4; break; case AArch64_AM_SXTH: return 5; break; case AArch64_AM_SXTW: return 6; break; case AArch64_AM_SXTX: return 7; break; } } /// getArithExtendImm - Encode the extend type and shift amount for an /// arithmetic instruction: /// imm: 3-bit extend amount /// {5-3} = shifter /// {2-0} = imm3 static inline unsigned AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm) { // assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!"); return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7); } /// getMemDoShift - Extract the "do shift" flag value for load/store /// instructions. static inline bool AArch64_AM_getMemDoShift(unsigned Imm) { return (Imm & 0x1) != 0; } /// getExtendType - Extract the extend type for the offset operand of /// loads/stores. static inline AArch64_AM_ShiftExtendType AArch64_AM_getMemExtendType(unsigned Imm) { return AArch64_AM_getExtendType((Imm >> 1) & 0x7); } static inline uint64_t ror(uint64_t elt, unsigned size) { return ((elt & 1) << (size-1)) | (elt >> 1); } /// processLogicalImmediate - Determine if an immediate value can be encoded /// as the immediate operand of a logical instruction for the given register /// size. If so, return true with "encoding" set to the encoded value in /// the form N:immr:imms. static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t *Encoding) { unsigned Size, Immr, N; uint32_t CTO, I; uint64_t Mask, NImms; if (Imm == 0ULL || Imm == ~0ULL || (RegSize != 64 && (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) { return false; } // First, determine the element size. Size = RegSize; do { uint64_t Mask; Size /= 2; Mask = (1ULL << Size) - 1; if ((Imm & Mask) != ((Imm >> Size) & Mask)) { Size *= 2; break; } } while (Size > 2); // Second, determine the rotation to make the element be: 0^m 1^n. Mask = ((uint64_t)-1LL) >> (64 - Size); Imm &= Mask; if (isShiftedMask_64(Imm)) { I = CountTrailingZeros_32(Imm); // assert(I < 64 && "undefined behavior"); CTO = CountTrailingOnes_32(Imm >> I); } else { unsigned CLO; Imm |= ~Mask; if (!isShiftedMask_64(~Imm)) return false; CLO = CountLeadingOnes_32(Imm); I = 64 - CLO; CTO = CLO + CountTrailingOnes_32(Imm) - (64 - Size); } // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n // to our target value, where I is the number of RORs to go the opposite // direction. // assert(Size > I && "I should be smaller than element size"); Immr = (Size - I) & (Size - 1); // If size has a 1 in the n'th bit, create a value that has zeroes in // bits [0, n] and ones above that. NImms = ~(Size-1) << 1; // Or the CTO value into the low bits, which must be below the Nth bit // bit mentioned above. NImms |= (CTO-1); // Extract the seventh bit and toggle it to create the N field. N = ((NImms >> 6) & 1) ^ 1; *Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); return true; } /// isLogicalImmediate - Return true if the immediate is valid for a logical /// immediate instruction of the given register size. Return false otherwise. static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) { uint64_t encoding; return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); } /// encodeLogicalImmediate - Return the encoded immediate value for a logical /// immediate instruction of the given register size. static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, unsigned regSize) { uint64_t encoding = 0; bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); // assert(res && "invalid logical immediate"); (void)res; return encoding; } /// decodeLogicalImmediate - Decode a logical immediate value in the form /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the /// integer value it represents with regSize bits. static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize) { // Extract the N, imms, and immr fields. unsigned N = (val >> 12) & 1; unsigned immr = (val >> 6) & 0x3f; unsigned imms = val & 0x3f; unsigned i, size, R, S; uint64_t pattern; // assert((regSize == 64 || N == 0) && "undefined logical immediate encoding"); int len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); // assert(len >= 0 && "undefined logical immediate encoding"); size = (1 << len); R = immr & (size - 1); S = imms & (size - 1); // assert(S != size - 1 && "undefined logical immediate encoding"); pattern = (1ULL << (S + 1)) - 1; for (i = 0; i < R; ++i) pattern = ror(pattern, size); // Replicate the pattern to fill the regSize. while (size != regSize) { pattern |= (pattern << size); size *= 2; } return pattern; } /// isValidDecodeLogicalImmediate - Check to see if the logical immediate value /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) /// is a valid encoding for an integer value with regSize bits. static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize) { unsigned size, S; int len; // Extract the N and imms fields needed for checking. unsigned N = (val >> 12) & 1; unsigned imms = val & 0x3f; if (regSize == 32 && N != 0) // undefined logical immediate encoding return false; len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); if (len < 0) // undefined logical immediate encoding return false; size = (1 << len); S = imms & (size - 1); if (S == size - 1) // undefined logical immediate encoding return false; return true; } //===----------------------------------------------------------------------===// // Floating-point Immediates // static inline float AArch64_AM_getFPImmFloat(unsigned Imm) { // We expect an 8-bit binary encoding of a floating-point number here. union { uint32_t I; float F; } FPUnion; uint8_t Sign = (Imm >> 7) & 0x1; uint8_t Exp = (Imm >> 4) & 0x7; uint8_t Mantissa = Imm & 0xf; // 8-bit FP iEEEE Float Encoding // abcd efgh aBbbbbbc defgh000 00000000 00000000 // // where B = NOT(b); FPUnion.I = 0; FPUnion.I |= ((uint32_t)Sign) << 31; FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; FPUnion.I |= (Exp & 0x3) << 23; FPUnion.I |= Mantissa << 19; return FPUnion.F; } //===--------------------------------------------------------------------===// // AdvSIMD Modified Immediates //===--------------------------------------------------------------------===// // 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm & 0xffffff00ffffff00ULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm) { return (Imm & 0xffULL); } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 32) | EncVal; } // 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm & 0xffff00ffffff00ffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm) { return (Imm & 0xff00ULL) >> 8; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 40) | (EncVal << 8); } // 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm & 0xff00ffffff00ffffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm) { return (Imm & 0xff0000ULL) >> 16; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 48) | (EncVal << 16); } // abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm & 0x00ffffff00ffffffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm) { return (Imm & 0xff000000ULL) >> 24; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 56) | (EncVal << 24); } // 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) && ((Imm & 0xff00ff00ff00ff00ULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm) { return (Imm & 0xffULL); } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal; } // abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) && ((Imm & 0x00ff00ff00ff00ffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm) { return (Imm & 0xff00ULL) >> 8; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8); } // 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm) { return (Imm & 0xff00ULL) >> 8; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL; } // 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL); } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm) { uint64_t EncVal = Imm; return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL; } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm) { return (Imm & 0x00ff0000ULL) >> 16; } // abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && ((Imm >> 48) == (Imm & 0x0000ffffULL)) && ((Imm >> 56) == (Imm & 0x000000ffULL)); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm) { return (Imm & 0xffULL); } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm) { uint64_t EncVal = Imm; EncVal |= (EncVal << 8); EncVal |= (EncVal << 16); EncVal |= (EncVal << 32); return EncVal; } // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh // cmode: 1110, op: 1 static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm) { uint64_t ByteA = Imm & 0xff00000000000000ULL; uint64_t ByteB = Imm & 0x00ff000000000000ULL; uint64_t ByteC = Imm & 0x0000ff0000000000ULL; uint64_t ByteD = Imm & 0x000000ff00000000ULL; uint64_t ByteE = Imm & 0x00000000ff000000ULL; uint64_t ByteF = Imm & 0x0000000000ff0000ULL; uint64_t ByteG = Imm & 0x000000000000ff00ULL; uint64_t ByteH = Imm & 0x00000000000000ffULL; return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) && (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) && (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) && (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) && (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) && (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) && (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) && (ByteH == 0ULL || ByteH == 0x00000000000000ffULL); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) { uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0; uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0; uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0; uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0; uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0; uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0; uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0; uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0; uint8_t EncVal = BitA; EncVal <<= 1; EncVal |= BitB; EncVal <<= 1; EncVal |= BitC; EncVal <<= 1; EncVal |= BitD; EncVal <<= 1; EncVal |= BitE; EncVal <<= 1; EncVal |= BitF; EncVal <<= 1; EncVal |= BitG; EncVal <<= 1; EncVal |= BitH; return EncVal; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) { uint64_t EncVal = 0; if (Imm & 0x80) EncVal |= 0xff00000000000000ULL; if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL; if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL; if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL; if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL; if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL; if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL; if (Imm & 0x01) EncVal |= 0x00000000000000ffULL; return EncVal; } // aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00 static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm) { uint64_t BString = (Imm & 0x7E000000ULL) >> 25; return ((Imm >> 32) == (Imm & 0xffffffffULL)) && (BString == 0x1f || BString == 0x20) && ((Imm & 0x0007ffff0007ffffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm) { uint8_t BitA = (Imm & 0x80000000ULL) != 0; uint8_t BitB = (Imm & 0x20000000ULL) != 0; uint8_t BitC = (Imm & 0x01000000ULL) != 0; uint8_t BitD = (Imm & 0x00800000ULL) != 0; uint8_t BitE = (Imm & 0x00400000ULL) != 0; uint8_t BitF = (Imm & 0x00200000ULL) != 0; uint8_t BitG = (Imm & 0x00100000ULL) != 0; uint8_t BitH = (Imm & 0x00080000ULL) != 0; uint8_t EncVal = BitA; EncVal <<= 1; EncVal |= BitB; EncVal <<= 1; EncVal |= BitC; EncVal <<= 1; EncVal |= BitD; EncVal <<= 1; EncVal |= BitE; EncVal <<= 1; EncVal |= BitF; EncVal <<= 1; EncVal |= BitG; EncVal <<= 1; EncVal |= BitH; return EncVal; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm) { uint64_t EncVal = 0; if (Imm & 0x80) EncVal |= 0x80000000ULL; if (Imm & 0x40) EncVal |= 0x3e000000ULL; else EncVal |= 0x40000000ULL; if (Imm & 0x20) EncVal |= 0x01000000ULL; if (Imm & 0x10) EncVal |= 0x00800000ULL; if (Imm & 0x08) EncVal |= 0x00400000ULL; if (Imm & 0x04) EncVal |= 0x00200000ULL; if (Imm & 0x02) EncVal |= 0x00100000ULL; if (Imm & 0x01) EncVal |= 0x00080000ULL; return (EncVal << 32) | EncVal; } // aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00 static inline bool AArch64_AM_isAdvSIMDModImmType12(uint64_t Imm) { uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54; return ((BString == 0xff || BString == 0x100) && ((Imm & 0x0000ffffffffffffULL) == 0)); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm) { uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0; uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0; uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0; uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0; uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0; uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0; uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0; uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0; uint8_t EncVal = BitA; EncVal <<= 1; EncVal |= BitB; EncVal <<= 1; EncVal |= BitC; EncVal <<= 1; EncVal |= BitD; EncVal <<= 1; EncVal |= BitE; EncVal <<= 1; EncVal |= BitF; EncVal <<= 1; EncVal |= BitG; EncVal <<= 1; EncVal |= BitH; return EncVal; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm) { uint64_t EncVal = 0; if (Imm & 0x80) EncVal |= 0x8000000000000000ULL; if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL; else EncVal |= 0x4000000000000000ULL; if (Imm & 0x20) EncVal |= 0x0020000000000000ULL; if (Imm & 0x10) EncVal |= 0x0010000000000000ULL; if (Imm & 0x08) EncVal |= 0x0008000000000000ULL; if (Imm & 0x04) EncVal |= 0x0004000000000000ULL; if (Imm & 0x02) EncVal |= 0x0002000000000000ULL; if (Imm & 0x01) EncVal |= 0x0001000000000000ULL; return (EncVal << 32) | EncVal; } /// Returns true if Imm is the concatenation of a repeating pattern of type T. static inline bool AArch64_AM_isSVEMaskOfIdenticalElements8(int64_t Imm) { #define _VECSIZE (sizeof(int64_t)/sizeof(int8_t)) unsigned int i; union { int64_t Whole; int8_t Parts[_VECSIZE]; } Vec; Vec.Whole = Imm; for(i = 1; i < _VECSIZE; i++) { if (Vec.Parts[i] != Vec.Parts[0]) return false; } #undef _VECSIZE return true; } static inline bool AArch64_AM_isSVEMaskOfIdenticalElements16(int64_t Imm) { #define _VECSIZE (sizeof(int64_t)/sizeof(int16_t)) unsigned int i; union { int64_t Whole; int16_t Parts[_VECSIZE]; } Vec; Vec.Whole = Imm; for(i = 1; i < _VECSIZE; i++) { if (Vec.Parts[i] != Vec.Parts[0]) return false; } #undef _VECSIZE return true; } static inline bool AArch64_AM_isSVEMaskOfIdenticalElements32(int64_t Imm) { #define _VECSIZE (sizeof(int64_t)/sizeof(int32_t)) unsigned int i; union { int64_t Whole; int32_t Parts[_VECSIZE]; } Vec; Vec.Whole = Imm; for(i = 1; i < _VECSIZE; i++) { if (Vec.Parts[i] != Vec.Parts[0]) return false; } #undef _VECSIZE return true; } static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm) { return true; } static inline bool isSVECpyImm8(int64_t Imm) { bool IsImm8 = (int8_t)Imm == Imm; return IsImm8 || (uint8_t)Imm == Imm; } static inline bool isSVECpyImm16(int64_t Imm) { bool IsImm8 = (int8_t)Imm == Imm; bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm; } static inline bool isSVECpyImm32(int64_t Imm) { bool IsImm8 = (int8_t)Imm == Imm; bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; return IsImm8 || IsImm16; } static inline bool isSVECpyImm64(int64_t Imm) { bool IsImm8 = (int8_t)Imm == Imm; bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; return IsImm8 || IsImm16; } /// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent. static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) { union { int64_t D; int32_t S[2]; int16_t H[4]; int8_t B[8]; } Vec = {Imm}; if (isSVECpyImm64(Vec.D)) return false; if (AArch64_AM_isSVEMaskOfIdenticalElements32(Imm) && isSVECpyImm32(Vec.S[0])) return false; if (AArch64_AM_isSVEMaskOfIdenticalElements16(Imm) && isSVECpyImm16(Vec.H[0])) return false; if (AArch64_AM_isSVEMaskOfIdenticalElements8(Imm) && isSVECpyImm8(Vec.B[0])) return false; return isLogicalImmediate(Vec.D, 64); } inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { int Shift; for (Shift = 0; Shift <= RegWidth - 16; Shift += 16) if ((Value & ~(0xffffULL << Shift)) == 0) return true; return false; } inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { if (RegWidth == 32) Value &= 0xffffffffULL; // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0". if (Value == 0 && Shift != 0) return false; return (Value & ~(0xffffULL << Shift)) == 0; } inline static bool AArch64_AM_isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { // MOVZ takes precedence over MOVN. if (isAnyMOVZMovAlias(Value, RegWidth)) return false; Value = ~Value; if (RegWidth == 32) Value &= 0xffffffffULL; return isMOVZMovAlias(Value, Shift, RegWidth); } inline static bool AArch64_AM_isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { if (isAnyMOVZMovAlias(Value, RegWidth)) return true; // It's not a MOVZ, but it might be a MOVN. Value = ~Value; if (RegWidth == 32) Value &= 0xffffffffULL; return isAnyMOVZMovAlias(Value, RegWidth); } #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64BaseInfo.c000064400000000000000000000041350072674642500211560ustar 00000000000000//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file provides basic encoding and assembly information for AArch64. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_ARM64 #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:4996) // disable MSVC's warning on strcpy() #pragma warning(disable:28719) // disable MSVC's warning on strcpy() #endif #include "../../utils.h" #include #include #include "AArch64BaseInfo.h" #include "AArch64GenSystemOperands.inc" // return a string representing the number X // NOTE: result must be big enough to contain the data static void utostr(uint64_t X, bool isNeg, char *result) { char Buffer[22]; char *BufPtr = Buffer + 21; Buffer[21] = '\0'; if (X == 0) *--BufPtr = '0'; // Handle special case... while (X) { *--BufPtr = X % 10 + '0'; X /= 10; } if (isNeg) *--BufPtr = '-'; // Add negative sign... // suppose that result is big enough strncpy(result, BufPtr, sizeof(Buffer)); } // NOTE: result must be big enough to contain the result void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result) { // assert(Bits < 0x10000); char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32]; int dummy; uint32_t Op0 = (Bits >> 14) & 0x3; uint32_t Op1 = (Bits >> 11) & 0x7; uint32_t CRn = (Bits >> 7) & 0xf; uint32_t CRm = (Bits >> 3) & 0xf; uint32_t Op2 = Bits & 0x7; utostr(Op0, false, Op0Str); utostr(Op1, false, Op1Str); utostr(Op2, false, Op2Str); utostr(CRn, false, CRnStr); utostr(CRm, false, CRmStr); dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s", Op0Str, Op1Str, CRnStr, CRmStr, Op2Str); (void)dummy; } #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64BaseInfo.h000064400000000000000000000430770072674642500211730ustar 00000000000000//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains small standalone helper functions and enum definitions for // the AArch64 target useful for the compiler back-end and the MC libraries. // As such, it deliberately does not include references to LLVM core // code gen types, passes, etc.. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_AARCH64_BASEINFO_H #define CS_LLVM_AARCH64_BASEINFO_H #include #include #include "AArch64Mapping.h" #ifndef __cplusplus #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #define inline /* inline */ #endif #endif inline static unsigned getWRegFromXReg(unsigned Reg) { switch (Reg) { default: break; case ARM64_REG_X0: return ARM64_REG_W0; case ARM64_REG_X1: return ARM64_REG_W1; case ARM64_REG_X2: return ARM64_REG_W2; case ARM64_REG_X3: return ARM64_REG_W3; case ARM64_REG_X4: return ARM64_REG_W4; case ARM64_REG_X5: return ARM64_REG_W5; case ARM64_REG_X6: return ARM64_REG_W6; case ARM64_REG_X7: return ARM64_REG_W7; case ARM64_REG_X8: return ARM64_REG_W8; case ARM64_REG_X9: return ARM64_REG_W9; case ARM64_REG_X10: return ARM64_REG_W10; case ARM64_REG_X11: return ARM64_REG_W11; case ARM64_REG_X12: return ARM64_REG_W12; case ARM64_REG_X13: return ARM64_REG_W13; case ARM64_REG_X14: return ARM64_REG_W14; case ARM64_REG_X15: return ARM64_REG_W15; case ARM64_REG_X16: return ARM64_REG_W16; case ARM64_REG_X17: return ARM64_REG_W17; case ARM64_REG_X18: return ARM64_REG_W18; case ARM64_REG_X19: return ARM64_REG_W19; case ARM64_REG_X20: return ARM64_REG_W20; case ARM64_REG_X21: return ARM64_REG_W21; case ARM64_REG_X22: return ARM64_REG_W22; case ARM64_REG_X23: return ARM64_REG_W23; case ARM64_REG_X24: return ARM64_REG_W24; case ARM64_REG_X25: return ARM64_REG_W25; case ARM64_REG_X26: return ARM64_REG_W26; case ARM64_REG_X27: return ARM64_REG_W27; case ARM64_REG_X28: return ARM64_REG_W28; case ARM64_REG_FP: return ARM64_REG_W29; case ARM64_REG_LR: return ARM64_REG_W30; case ARM64_REG_SP: return ARM64_REG_WSP; case ARM64_REG_XZR: return ARM64_REG_WZR; } // For anything else, return it unchanged. return Reg; } inline static unsigned getXRegFromWReg(unsigned Reg) { switch (Reg) { case ARM64_REG_W0: return ARM64_REG_X0; case ARM64_REG_W1: return ARM64_REG_X1; case ARM64_REG_W2: return ARM64_REG_X2; case ARM64_REG_W3: return ARM64_REG_X3; case ARM64_REG_W4: return ARM64_REG_X4; case ARM64_REG_W5: return ARM64_REG_X5; case ARM64_REG_W6: return ARM64_REG_X6; case ARM64_REG_W7: return ARM64_REG_X7; case ARM64_REG_W8: return ARM64_REG_X8; case ARM64_REG_W9: return ARM64_REG_X9; case ARM64_REG_W10: return ARM64_REG_X10; case ARM64_REG_W11: return ARM64_REG_X11; case ARM64_REG_W12: return ARM64_REG_X12; case ARM64_REG_W13: return ARM64_REG_X13; case ARM64_REG_W14: return ARM64_REG_X14; case ARM64_REG_W15: return ARM64_REG_X15; case ARM64_REG_W16: return ARM64_REG_X16; case ARM64_REG_W17: return ARM64_REG_X17; case ARM64_REG_W18: return ARM64_REG_X18; case ARM64_REG_W19: return ARM64_REG_X19; case ARM64_REG_W20: return ARM64_REG_X20; case ARM64_REG_W21: return ARM64_REG_X21; case ARM64_REG_W22: return ARM64_REG_X22; case ARM64_REG_W23: return ARM64_REG_X23; case ARM64_REG_W24: return ARM64_REG_X24; case ARM64_REG_W25: return ARM64_REG_X25; case ARM64_REG_W26: return ARM64_REG_X26; case ARM64_REG_W27: return ARM64_REG_X27; case ARM64_REG_W28: return ARM64_REG_X28; case ARM64_REG_W29: return ARM64_REG_FP; case ARM64_REG_W30: return ARM64_REG_LR; case ARM64_REG_WSP: return ARM64_REG_SP; case ARM64_REG_WZR: return ARM64_REG_XZR; } // For anything else, return it unchanged. return Reg; } inline static unsigned getBRegFromDReg(unsigned Reg) { switch (Reg) { case ARM64_REG_D0: return ARM64_REG_B0; case ARM64_REG_D1: return ARM64_REG_B1; case ARM64_REG_D2: return ARM64_REG_B2; case ARM64_REG_D3: return ARM64_REG_B3; case ARM64_REG_D4: return ARM64_REG_B4; case ARM64_REG_D5: return ARM64_REG_B5; case ARM64_REG_D6: return ARM64_REG_B6; case ARM64_REG_D7: return ARM64_REG_B7; case ARM64_REG_D8: return ARM64_REG_B8; case ARM64_REG_D9: return ARM64_REG_B9; case ARM64_REG_D10: return ARM64_REG_B10; case ARM64_REG_D11: return ARM64_REG_B11; case ARM64_REG_D12: return ARM64_REG_B12; case ARM64_REG_D13: return ARM64_REG_B13; case ARM64_REG_D14: return ARM64_REG_B14; case ARM64_REG_D15: return ARM64_REG_B15; case ARM64_REG_D16: return ARM64_REG_B16; case ARM64_REG_D17: return ARM64_REG_B17; case ARM64_REG_D18: return ARM64_REG_B18; case ARM64_REG_D19: return ARM64_REG_B19; case ARM64_REG_D20: return ARM64_REG_B20; case ARM64_REG_D21: return ARM64_REG_B21; case ARM64_REG_D22: return ARM64_REG_B22; case ARM64_REG_D23: return ARM64_REG_B23; case ARM64_REG_D24: return ARM64_REG_B24; case ARM64_REG_D25: return ARM64_REG_B25; case ARM64_REG_D26: return ARM64_REG_B26; case ARM64_REG_D27: return ARM64_REG_B27; case ARM64_REG_D28: return ARM64_REG_B28; case ARM64_REG_D29: return ARM64_REG_B29; case ARM64_REG_D30: return ARM64_REG_B30; case ARM64_REG_D31: return ARM64_REG_B31; } // For anything else, return it unchanged. return Reg; } inline static unsigned getDRegFromBReg(unsigned Reg) { switch (Reg) { case ARM64_REG_B0: return ARM64_REG_D0; case ARM64_REG_B1: return ARM64_REG_D1; case ARM64_REG_B2: return ARM64_REG_D2; case ARM64_REG_B3: return ARM64_REG_D3; case ARM64_REG_B4: return ARM64_REG_D4; case ARM64_REG_B5: return ARM64_REG_D5; case ARM64_REG_B6: return ARM64_REG_D6; case ARM64_REG_B7: return ARM64_REG_D7; case ARM64_REG_B8: return ARM64_REG_D8; case ARM64_REG_B9: return ARM64_REG_D9; case ARM64_REG_B10: return ARM64_REG_D10; case ARM64_REG_B11: return ARM64_REG_D11; case ARM64_REG_B12: return ARM64_REG_D12; case ARM64_REG_B13: return ARM64_REG_D13; case ARM64_REG_B14: return ARM64_REG_D14; case ARM64_REG_B15: return ARM64_REG_D15; case ARM64_REG_B16: return ARM64_REG_D16; case ARM64_REG_B17: return ARM64_REG_D17; case ARM64_REG_B18: return ARM64_REG_D18; case ARM64_REG_B19: return ARM64_REG_D19; case ARM64_REG_B20: return ARM64_REG_D20; case ARM64_REG_B21: return ARM64_REG_D21; case ARM64_REG_B22: return ARM64_REG_D22; case ARM64_REG_B23: return ARM64_REG_D23; case ARM64_REG_B24: return ARM64_REG_D24; case ARM64_REG_B25: return ARM64_REG_D25; case ARM64_REG_B26: return ARM64_REG_D26; case ARM64_REG_B27: return ARM64_REG_D27; case ARM64_REG_B28: return ARM64_REG_D28; case ARM64_REG_B29: return ARM64_REG_D29; case ARM64_REG_B30: return ARM64_REG_D30; case ARM64_REG_B31: return ARM64_REG_D31; } // For anything else, return it unchanged. return Reg; } // // Enums corresponding to AArch64 condition codes // The CondCodes constants map directly to the 4-bit encoding of the // condition field for predicated instructions. typedef enum AArch64CC_CondCode { // Meaning (integer) Meaning (floating-point) AArch64CC_EQ = 0x0, // Equal Equal AArch64CC_NE = 0x1, // Not equal Not equal, or unordered AArch64CC_HS = 0x2, // Unsigned higher or same >, ==, or unordered AArch64CC_LO = 0x3, // Unsigned lower Less than AArch64CC_MI = 0x4, // Minus, negative Less than AArch64CC_PL = 0x5, // Plus, positive or zero >, ==, or unordered AArch64CC_VS = 0x6, // Overflow Unordered AArch64CC_VC = 0x7, // No overflow Not unordered AArch64CC_HI = 0x8, // Unsigned higher Greater than, or unordered AArch64CC_LS = 0x9, // Unsigned lower or same Less than or equal AArch64CC_GE = 0xa, // Greater than or equal Greater than or equal AArch64CC_LT = 0xb, // Less than Less than, or unordered AArch64CC_GT = 0xc, // Greater than Greater than AArch64CC_LE = 0xd, // Less than or equal <, ==, or unordered AArch64CC_AL = 0xe, // Always (unconditional) Always (unconditional) AArch64CC_NV = 0xf, // Always (unconditional) Always (unconditional) // Note the NV exists purely to disassemble 0b1111. Execution is "always". AArch64CC_Invalid } AArch64CC_CondCode; inline static AArch64CC_CondCode getInvertedCondCode(AArch64CC_CondCode Code) { // To reverse a condition it's necessary to only invert the low bit: return (AArch64CC_CondCode)((unsigned)Code ^ 0x1); } inline static const char *getCondCodeName(AArch64CC_CondCode CC) { switch (CC) { default: return NULL; // never reach case AArch64CC_EQ: return "eq"; case AArch64CC_NE: return "ne"; case AArch64CC_HS: return "hs"; case AArch64CC_LO: return "lo"; case AArch64CC_MI: return "mi"; case AArch64CC_PL: return "pl"; case AArch64CC_VS: return "vs"; case AArch64CC_VC: return "vc"; case AArch64CC_HI: return "hi"; case AArch64CC_LS: return "ls"; case AArch64CC_GE: return "ge"; case AArch64CC_LT: return "lt"; case AArch64CC_GT: return "gt"; case AArch64CC_LE: return "le"; case AArch64CC_AL: return "al"; case AArch64CC_NV: return "nv"; } } /// Given a condition code, return NZCV flags that would satisfy that condition. /// The flag bits are in the format expected by the ccmp instructions. /// Note that many different flag settings can satisfy a given condition code, /// this function just returns one of them. inline static unsigned getNZCVToSatisfyCondCode(AArch64CC_CondCode Code) { // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. enum { N = 8, Z = 4, C = 2, V = 1 }; switch (Code) { default: // llvm_unreachable("Unknown condition code"); case AArch64CC_EQ: return Z; // Z == 1 case AArch64CC_NE: return 0; // Z == 0 case AArch64CC_HS: return C; // C == 1 case AArch64CC_LO: return 0; // C == 0 case AArch64CC_MI: return N; // N == 1 case AArch64CC_PL: return 0; // N == 0 case AArch64CC_VS: return V; // V == 1 case AArch64CC_VC: return 0; // V == 0 case AArch64CC_HI: return C; // C == 1 && Z == 0 case AArch64CC_LS: return 0; // C == 0 || Z == 1 case AArch64CC_GE: return 0; // N == V case AArch64CC_LT: return N; // N != V case AArch64CC_GT: return 0; // Z == 0 && N == V case AArch64CC_LE: return Z; // Z == 1 || N != V } } /// Instances of this class can perform bidirectional mapping from random /// identifier strings to operand encodings. For example "MSR" takes a named /// system-register which must be encoded somehow and decoded for printing. This /// central location means that the information for those transformations is not /// duplicated and remains in sync. /// /// FIXME: currently the algorithm is a completely unoptimised linear /// search. Obviously this could be improved, but we would probably want to work /// out just how often these instructions are emitted before working on it. It /// might even be optimal to just reorder the tables for the common instructions /// rather than changing the algorithm. typedef struct A64NamedImmMapper_Mapping { const char *Name; uint32_t Value; } A64NamedImmMapper_Mapping; typedef struct A64NamedImmMapper { const A64NamedImmMapper_Mapping *Pairs; size_t NumPairs; uint32_t TooBigImm; } A64NamedImmMapper; typedef struct A64SysRegMapper { const A64NamedImmMapper_Mapping *SysRegPairs; const A64NamedImmMapper_Mapping *InstPairs; size_t NumInstPairs; } A64SysRegMapper; typedef enum A64SE_ShiftExtSpecifiers { A64SE_Invalid = -1, A64SE_LSL, A64SE_MSL, A64SE_LSR, A64SE_ASR, A64SE_ROR, A64SE_UXTB, A64SE_UXTH, A64SE_UXTW, A64SE_UXTX, A64SE_SXTB, A64SE_SXTH, A64SE_SXTW, A64SE_SXTX } A64SE_ShiftExtSpecifiers; typedef enum A64Layout_VectorLayout { A64Layout_Invalid = -1, A64Layout_VL_8B, A64Layout_VL_4H, A64Layout_VL_2S, A64Layout_VL_1D, A64Layout_VL_16B, A64Layout_VL_8H, A64Layout_VL_4S, A64Layout_VL_2D, // Bare layout for the 128-bit vector // (only show ".b", ".h", ".s", ".d" without vector number) A64Layout_VL_B, A64Layout_VL_H, A64Layout_VL_S, A64Layout_VL_D } A64Layout_VectorLayout; inline static const char *AArch64VectorLayoutToString(A64Layout_VectorLayout Layout) { switch (Layout) { default: return NULL; // never reach case A64Layout_VL_8B: return ".8b"; case A64Layout_VL_4H: return ".4h"; case A64Layout_VL_2S: return ".2s"; case A64Layout_VL_1D: return ".1d"; case A64Layout_VL_16B: return ".16b"; case A64Layout_VL_8H: return ".8h"; case A64Layout_VL_4S: return ".4s"; case A64Layout_VL_2D: return ".2d"; case A64Layout_VL_B: return ".b"; case A64Layout_VL_H: return ".h"; case A64Layout_VL_S: return ".s"; case A64Layout_VL_D: return ".d"; } } inline static A64Layout_VectorLayout AArch64StringToVectorLayout(char *LayoutStr) { if (!strcmp(LayoutStr, ".8b")) return A64Layout_VL_8B; if (!strcmp(LayoutStr, ".4h")) return A64Layout_VL_4H; if (!strcmp(LayoutStr, ".2s")) return A64Layout_VL_2S; if (!strcmp(LayoutStr, ".1d")) return A64Layout_VL_1D; if (!strcmp(LayoutStr, ".16b")) return A64Layout_VL_16B; if (!strcmp(LayoutStr, ".8h")) return A64Layout_VL_8H; if (!strcmp(LayoutStr, ".4s")) return A64Layout_VL_4S; if (!strcmp(LayoutStr, ".2d")) return A64Layout_VL_2D; if (!strcmp(LayoutStr, ".b")) return A64Layout_VL_B; if (!strcmp(LayoutStr, ".s")) return A64Layout_VL_S; if (!strcmp(LayoutStr, ".d")) return A64Layout_VL_D; return A64Layout_Invalid; } /// Target Operand Flag enum. enum TOF { //===------------------------------------------------------------------===// // AArch64 Specific MachineOperand flags. MO_NO_FLAG, MO_FRAGMENT = 0xf, /// MO_PAGE - A symbol operand with this flag represents the pc-relative /// offset of the 4K page containing the symbol. This is used with the /// ADRP instruction. MO_PAGE = 1, /// MO_PAGEOFF - A symbol operand with this flag represents the offset of /// that symbol within a 4K page. This offset is added to the page address /// to produce the complete address. MO_PAGEOFF = 2, /// MO_G3 - A symbol operand with this flag (granule 3) represents the high /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction MO_G3 = 3, /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction MO_G2 = 4, /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction MO_G1 = 5, /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction MO_G0 = 6, /// MO_HI12 - This flag indicates that a symbol operand represents the bits /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- /// by-12-bits instruction. MO_HI12 = 7, /// MO_GOT - This flag indicates that a symbol operand represents the /// address of the GOT entry for the symbol, rather than the address of /// the symbol itself. MO_GOT = 0x10, /// MO_NC - Indicates whether the linker is expected to check the symbol /// reference for overflow. For example in an ADRP/ADD pair of relocations /// the ADRP usually does check, but not the ADD. MO_NC = 0x20, /// MO_TLS - Indicates that the operand being accessed is some kind of /// thread-local symbol. On Darwin, only one type of thread-local access /// exists (pre linker-relaxation), but on ELF the TLSModel used for the /// referee will affect interpretation. MO_TLS = 0x40, /// MO_DLLIMPORT - On a symbol operand, this represents that the reference /// to the symbol is for an import stub. This is used for DLL import /// storage class indication on Windows. MO_DLLIMPORT = 0x80, }; typedef struct SysAlias { const char *Name; uint16_t Encoding; } SysAlias; #define AT SysAlias #define DB SysAlias #define DC SysAlias #define SVEPRFM SysAlias #define PRFM SysAlias #define PSB SysAlias #define ISB SysAlias #define TSB SysAlias #define PState SysAlias #define SVEPREDPAT SysAlias typedef struct SysAliasReg { const char *Name; uint16_t Encoding; bool NeedsReg; } SysAliasReg; #define IC SysAliasReg #define TLBI SysAliasReg typedef struct SysAliasSysReg { const char *Name; uint16_t Encoding; bool Readable; bool Writeable; } SysAliasSysReg; #define SysReg SysAliasSysReg typedef struct ExactFPImm { const char *Name; int Enum; const char *Repr; } ExactFPImm; const AT *lookupATByEncoding(uint16_t Encoding); const DB *lookupDBByEncoding(uint16_t Encoding); const DC *lookupDCByEncoding(uint16_t Encoding); const IC *lookupICByEncoding(uint16_t Encoding); const TLBI *lookupTLBIByEncoding(uint16_t Encoding); const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding); const PRFM *lookupPRFMByEncoding(uint16_t Encoding); const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding); const ISB *lookupISBByEncoding(uint16_t Encoding); const TSB *lookupTSBByEncoding(uint16_t Encoding); const SysReg *lookupSysRegByEncoding(uint16_t Encoding); const PState *lookupPStateByEncoding(uint16_t Encoding); const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding); const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding); // NOTE: result must be 128 bytes to contain the result void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result); #include "AArch64GenSystemOperands_enum.inc" #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64Disassembler.c000064400000000000000000001632520072674642500221130ustar 00000000000000//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains the functions necessary to decode AArch64 instruction // bitpatterns into MCInsts (with the help of TableGenerated information from // the instruction definitions). // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_ARM64 #include // DEBUG #include #include "../../cs_priv.h" #include "../../utils.h" #include "AArch64Disassembler.h" #include "../../MCDisassembler.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCRegisterInfo.h" #include "AArch64AddressingModes.h" #include "AArch64BaseInfo.h" // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder, int Bits); static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder, int ElementWidth); static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); static bool Check(DecodeStatus *Out, DecodeStatus In) { switch (In) { default: // never reach return true; case MCDisassembler_Success: // Out stays the same. return true; case MCDisassembler_SoftFail: *Out = In; return true; case MCDisassembler_Fail: *Out = In; return false; } // llvm_unreachable("Invalid DecodeStatus!"); } // Hacky: enable all features for disassembler uint64_t AArch64_getFeatureBits(int feature) { // enable all features return (uint64_t)-1; } #define GET_SUBTARGETINFO_ENUM #include "AArch64GenSubtargetInfo.inc" #include "AArch64GenDisassemblerTables.inc" #define GET_INSTRINFO_ENUM #include "AArch64GenInstrInfo.inc" #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "AArch64GenRegisterInfo.inc" #define Success MCDisassembler_Success #define Fail MCDisassembler_Fail #define SoftFail MCDisassembler_SoftFail static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address, MCRegisterInfo *MRI) { uint32_t insn; DecodeStatus result; size_t i; if (code_len < 4) { // not enough data *Size = 0; return MCDisassembler_Fail; } if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm64)+sizeof(cs_arm64)); for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++) MI->flat_insn->detail->arm64.operands[i].vector_index = -1; } if (MODE_IS_BIG_ENDIAN(ud->mode)) insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); else insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | (code[1] << 8) | (code[0] << 0); // Calling the auto-generated decoder function. result = decodeInstruction_4(DecoderTable32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } // invalid code MCInst_clear(MI); *Size = 0; return MCDisassembler_Fail; } bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { DecodeStatus status = _getInstruction((cs_struct *)ud, instr, code, code_len, size, address, (MCRegisterInfo *)info); return status == MCDisassembler_Success; } static const unsigned FPR128DecoderTable[] = { AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31 }; static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = FPR128DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 15) return Fail; return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); } static const unsigned FPR64DecoderTable[] = { AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31 }; static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = FPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned FPR32DecoderTable[] = { AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31 }; static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = FPR32DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned FPR16DecoderTable[] = { AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31 }; static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = FPR16DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned FPR8DecoderTable[] = { AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31 }; static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = FPR8DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned GPR64DecoderTable[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR }; static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 30) return Fail; Register = GPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = GPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = GPR64DecoderTable[RegNo]; if (Register == AArch64_XZR) Register = AArch64_SP; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned GPR32DecoderTable[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR }; static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = GPR32DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = GPR32DecoderTable[RegNo]; if (Register == AArch64_WZR) Register = AArch64_WSP; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned ZPRDecoderTable[] = { AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31 }; static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = ZPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) return Fail; return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) return Fail; return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); } static const unsigned ZZDecoderTable[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0 }; static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = ZZDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned ZZZDecoderTable[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1 }; static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = ZZZDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned ZZZZDecoderTable[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2 }; static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = ZZZZDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned PPRDecoderTable[] = { AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15 }; static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 15) return Fail; Register = PPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { if (RegNo > 7) return Fail; // Just reuse the PPR decode table return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); } static const unsigned VectorDecoderTable[] = { AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31 }; static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = VectorDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned QQDecoderTable[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0 }; static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = QQDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned QQQDecoderTable[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1 }; static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = QQQDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned QQQQDecoderTable[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2 }; static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = QQQQDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned DDDecoderTable[] = { AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0 }; static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = DDDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned DDDDecoderTable[] = { AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1 }; static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = DDDDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static const unsigned DDDDDecoderTable[] = { AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2 }; static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; if (RegNo > 31) return Fail; Register = DDDDDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { // scale{5} is asserted as 1 in tblgen. Imm |= 0x20; MCOperand_CreateImm0(Inst, 64 - Imm); return Success; } static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { MCOperand_CreateImm0(Inst, 64 - Imm); return Success; } static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { int64_t ImmVal = Imm; // Sign-extend 19-bit immediate. if (ImmVal & (1 << (19 - 1))) ImmVal |= ~((1LL << 19) - 1); MCOperand_CreateImm0(Inst, ImmVal); return Success; } static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, (Imm >> 1) & 1); MCOperand_CreateImm0(Inst, Imm & 1); return Success; } static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, Imm); // Every system register in the encoding space is valid with the syntax // S____, so decoding system registers always succeeds. return Success; } static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, Imm); return Success; } static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { // This decoder exists to add the dummy Lane operand to the MCInst, which must // be 1 in assembly but has no other real manifestation. unsigned Rd = fieldFromInstruction_4(Insn, 0, 5); unsigned Rn = fieldFromInstruction_4(Insn, 5, 5); unsigned IsToVec = fieldFromInstruction_4(Insn, 16, 1); if (IsToVec) { DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); } else { DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); } // Add the lane MCOperand_CreateImm0(Inst, 1); return Success; } static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm, unsigned Add) { MCOperand_CreateImm0(Inst, Add - Imm); return Success; } static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm, unsigned Add) { MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1)); return Success; } static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 64); } static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); } static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 32); } static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); } static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 16); } static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); } static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm, 8); } static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 64); } static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 32); } static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 16); } static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { return DecodeVecShiftLImm(Inst, Imm, 8); } static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); unsigned Rm = fieldFromInstruction_4(insn, 16, 5); unsigned shiftHi = fieldFromInstruction_4(insn, 22, 2); unsigned shiftLo = fieldFromInstruction_4(insn, 10, 6); unsigned shift = (shiftHi << 6) | shiftLo; switch (MCInst_getOpcode(Inst)) { default: return Fail; case AArch64_ADDWrs: case AArch64_ADDSWrs: case AArch64_SUBWrs: case AArch64_SUBSWrs: // if shift == '11' then ReservedValue() if (shiftHi == 0x3) return Fail; // Deliberate fallthrough case AArch64_ANDWrs: case AArch64_ANDSWrs: case AArch64_BICWrs: case AArch64_BICSWrs: case AArch64_ORRWrs: case AArch64_ORNWrs: case AArch64_EORWrs: case AArch64_EONWrs: { // if sf == '0' and imm6<5> == '1' then ReservedValue() if (shiftLo >> 5 == 1) return Fail; DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; } case AArch64_ADDXrs: case AArch64_ADDSXrs: case AArch64_SUBXrs: case AArch64_SUBSXrs: // if shift == '11' then ReservedValue() if (shiftHi == 0x3) return Fail; // Deliberate fallthrough case AArch64_ANDXrs: case AArch64_ANDSXrs: case AArch64_BICXrs: case AArch64_BICSXrs: case AArch64_ORRXrs: case AArch64_ORNXrs: case AArch64_EORXrs: case AArch64_EONXrs: DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; } MCOperand_CreateImm0(Inst, shift); return Success; } static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); unsigned imm = fieldFromInstruction_4(insn, 5, 16); unsigned shift = fieldFromInstruction_4(insn, 21, 2); shift <<= 4; switch (MCInst_getOpcode(Inst)) { default: return Fail; case AArch64_MOVZWi: case AArch64_MOVNWi: case AArch64_MOVKWi: if (shift & (1U << 5)) return Fail; DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); break; case AArch64_MOVZXi: case AArch64_MOVNXi: case AArch64_MOVKXi: DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); break; } if (MCInst_getOpcode(Inst) == AArch64_MOVKWi || MCInst_getOpcode(Inst) == AArch64_MOVKXi) MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); MCOperand_CreateImm0(Inst, imm); MCOperand_CreateImm0(Inst, shift); return Success; } static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rt = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); unsigned offset = fieldFromInstruction_4(insn, 10, 12); switch (MCInst_getOpcode(Inst)) { default: return Fail; case AArch64_PRFMui: // Rt is an immediate in prefetch. MCOperand_CreateImm0(Inst, Rt); break; case AArch64_STRBBui: case AArch64_LDRBBui: case AArch64_LDRSBWui: case AArch64_STRHHui: case AArch64_LDRHHui: case AArch64_LDRSHWui: case AArch64_STRWui: case AArch64_LDRWui: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDRSBXui: case AArch64_LDRSHXui: case AArch64_LDRSWui: case AArch64_STRXui: case AArch64_LDRXui: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDRQui: case AArch64_STRQui: DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDRDui: case AArch64_STRDui: DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDRSui: case AArch64_STRSui: DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDRHui: case AArch64_STRHui: DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDRBui: case AArch64_STRBui: DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); break; } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) MCOperand_CreateImm0(Inst, offset); return Success; } static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { bool IsLoad, IsIndexed, IsFP; unsigned Rt = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); int64_t offset = fieldFromInstruction_4(insn, 12, 9); // offset is a 9-bit signed immediate, so sign extend it to // fill the unsigned. if (offset & (1 << (9 - 1))) offset |= ~((1LL << 9) - 1); // First operand is always the writeback to the address register, if needed. switch (MCInst_getOpcode(Inst)) { default: break; case AArch64_LDRSBWpre: case AArch64_LDRSHWpre: case AArch64_STRBBpre: case AArch64_LDRBBpre: case AArch64_STRHHpre: case AArch64_LDRHHpre: case AArch64_STRWpre: case AArch64_LDRWpre: case AArch64_LDRSBWpost: case AArch64_LDRSHWpost: case AArch64_STRBBpost: case AArch64_LDRBBpost: case AArch64_STRHHpost: case AArch64_LDRHHpost: case AArch64_STRWpost: case AArch64_LDRWpost: case AArch64_LDRSBXpre: case AArch64_LDRSHXpre: case AArch64_STRXpre: case AArch64_LDRSWpre: case AArch64_LDRXpre: case AArch64_LDRSBXpost: case AArch64_LDRSHXpost: case AArch64_STRXpost: case AArch64_LDRSWpost: case AArch64_LDRXpost: case AArch64_LDRQpre: case AArch64_STRQpre: case AArch64_LDRQpost: case AArch64_STRQpost: case AArch64_LDRDpre: case AArch64_STRDpre: case AArch64_LDRDpost: case AArch64_STRDpost: case AArch64_LDRSpre: case AArch64_STRSpre: case AArch64_LDRSpost: case AArch64_STRSpost: case AArch64_LDRHpre: case AArch64_STRHpre: case AArch64_LDRHpost: case AArch64_STRHpost: case AArch64_LDRBpre: case AArch64_STRBpre: case AArch64_LDRBpost: case AArch64_STRBpost: DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); break; } switch (MCInst_getOpcode(Inst)) { default: return Fail; case AArch64_PRFUMi: // Rt is an immediate in prefetch. MCOperand_CreateImm0(Inst, Rt); break; case AArch64_STURBBi: case AArch64_LDURBBi: case AArch64_LDURSBWi: case AArch64_STURHHi: case AArch64_LDURHHi: case AArch64_LDURSHWi: case AArch64_STURWi: case AArch64_LDURWi: case AArch64_LDTRSBWi: case AArch64_LDTRSHWi: case AArch64_STTRWi: case AArch64_LDTRWi: case AArch64_STTRHi: case AArch64_LDTRHi: case AArch64_LDTRBi: case AArch64_STTRBi: case AArch64_LDRSBWpre: case AArch64_LDRSHWpre: case AArch64_STRBBpre: case AArch64_LDRBBpre: case AArch64_STRHHpre: case AArch64_LDRHHpre: case AArch64_STRWpre: case AArch64_LDRWpre: case AArch64_LDRSBWpost: case AArch64_LDRSHWpost: case AArch64_STRBBpost: case AArch64_LDRBBpost: case AArch64_STRHHpost: case AArch64_LDRHHpost: case AArch64_STRWpost: case AArch64_LDRWpost: case AArch64_STLURBi: case AArch64_STLURHi: case AArch64_STLURWi: case AArch64_LDAPURBi: case AArch64_LDAPURSBWi: case AArch64_LDAPURHi: case AArch64_LDAPURSHWi: case AArch64_LDAPURi: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDURSBXi: case AArch64_LDURSHXi: case AArch64_LDURSWi: case AArch64_STURXi: case AArch64_LDURXi: case AArch64_LDTRSBXi: case AArch64_LDTRSHXi: case AArch64_LDTRSWi: case AArch64_STTRXi: case AArch64_LDTRXi: case AArch64_LDRSBXpre: case AArch64_LDRSHXpre: case AArch64_STRXpre: case AArch64_LDRSWpre: case AArch64_LDRXpre: case AArch64_LDRSBXpost: case AArch64_LDRSHXpost: case AArch64_STRXpost: case AArch64_LDRSWpost: case AArch64_LDRXpost: case AArch64_LDAPURSWi: case AArch64_LDAPURSHXi: case AArch64_LDAPURSBXi: case AArch64_STLURXi: case AArch64_LDAPURXi: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDURQi: case AArch64_STURQi: case AArch64_LDRQpre: case AArch64_STRQpre: case AArch64_LDRQpost: case AArch64_STRQpost: DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDURDi: case AArch64_STURDi: case AArch64_LDRDpre: case AArch64_STRDpre: case AArch64_LDRDpost: case AArch64_STRDpost: DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDURSi: case AArch64_STURSi: case AArch64_LDRSpre: case AArch64_STRSpre: case AArch64_LDRSpost: case AArch64_STRSpost: DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDURHi: case AArch64_STURHi: case AArch64_LDRHpre: case AArch64_STRHpre: case AArch64_LDRHpost: case AArch64_STRHpost: DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_LDURBi: case AArch64_STURBi: case AArch64_LDRBpre: case AArch64_STRBpre: case AArch64_LDRBpost: case AArch64_STRBpost: DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); break; } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); MCOperand_CreateImm0(Inst, offset); IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0; IsIndexed = fieldFromInstruction_4(insn, 10, 2) != 0; IsFP = fieldFromInstruction_4(insn, 26, 1) != 0; // Cannot write back to a transfer register (but xzr != sp). if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) return SoftFail; return Success; } static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rt = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); unsigned Rs = fieldFromInstruction_4(insn, 16, 5); unsigned Opcode = MCInst_getOpcode(Inst); switch (Opcode) { default: return Fail; case AArch64_STLXRW: case AArch64_STLXRB: case AArch64_STLXRH: case AArch64_STXRW: case AArch64_STXRB: case AArch64_STXRH: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); // FALLTHROUGH case AArch64_LDARW: case AArch64_LDARB: case AArch64_LDARH: case AArch64_LDAXRW: case AArch64_LDAXRB: case AArch64_LDAXRH: case AArch64_LDXRW: case AArch64_LDXRB: case AArch64_LDXRH: case AArch64_STLRW: case AArch64_STLRB: case AArch64_STLRH: case AArch64_STLLRW: case AArch64_STLLRB: case AArch64_STLLRH: case AArch64_LDLARW: case AArch64_LDLARB: case AArch64_LDLARH: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_STLXRX: case AArch64_STXRX: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); // FALLTHROUGH case AArch64_LDARX: case AArch64_LDAXRX: case AArch64_LDXRX: case AArch64_STLRX: case AArch64_LDLARX: case AArch64_STLLRX: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; case AArch64_STLXPW: case AArch64_STXPW: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); // FALLTHROUGH case AArch64_LDAXPW: case AArch64_LDXPW: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64_STLXPX: case AArch64_STXPX: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); // FALLTHROUGH case AArch64_LDAXPX: case AArch64_LDXPX: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); // You shouldn't load to the same register twice in an instruction... if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW || Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && Rt == Rt2) return SoftFail; return Success; } static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rt = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); int32_t offset = fieldFromInstruction_4(insn, 15, 7); bool IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0; unsigned Opcode = MCInst_getOpcode(Inst); bool NeedsDisjointWritebackTransfer = false; // offset is a 7-bit signed immediate, so sign extend it to // fill the unsigned. if (offset & (1 << (7 - 1))) offset |= ~((1LL << 7) - 1); // First operand is always writeback of base register. switch (Opcode) { default: break; case AArch64_LDPXpost: case AArch64_STPXpost: case AArch64_LDPSWpost: case AArch64_LDPXpre: case AArch64_STPXpre: case AArch64_LDPSWpre: case AArch64_LDPWpost: case AArch64_STPWpost: case AArch64_LDPWpre: case AArch64_STPWpre: case AArch64_LDPQpost: case AArch64_STPQpost: case AArch64_LDPQpre: case AArch64_STPQpre: case AArch64_LDPDpost: case AArch64_STPDpost: case AArch64_LDPDpre: case AArch64_STPDpre: case AArch64_LDPSpost: case AArch64_STPSpost: case AArch64_LDPSpre: case AArch64_STPSpre: DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); break; } switch (Opcode) { default: return Fail; case AArch64_LDPXpost: case AArch64_STPXpost: case AArch64_LDPSWpost: case AArch64_LDPXpre: case AArch64_STPXpre: case AArch64_LDPSWpre: NeedsDisjointWritebackTransfer = true; // Fallthrough case AArch64_LDNPXi: case AArch64_STNPXi: case AArch64_LDPXi: case AArch64_STPXi: case AArch64_LDPSWi: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64_LDPWpost: case AArch64_STPWpost: case AArch64_LDPWpre: case AArch64_STPWpre: NeedsDisjointWritebackTransfer = true; // Fallthrough case AArch64_LDNPWi: case AArch64_STNPWi: case AArch64_LDPWi: case AArch64_STPWi: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64_LDNPQi: case AArch64_STNPQi: case AArch64_LDPQpost: case AArch64_STPQpost: case AArch64_LDPQi: case AArch64_STPQi: case AArch64_LDPQpre: case AArch64_STPQpre: DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64_LDNPDi: case AArch64_STNPDi: case AArch64_LDPDpost: case AArch64_STPDpost: case AArch64_LDPDi: case AArch64_STPDi: case AArch64_LDPDpre: case AArch64_STPDpre: DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; case AArch64_LDNPSi: case AArch64_STNPSi: case AArch64_LDPSpost: case AArch64_STPSpost: case AArch64_LDPSi: case AArch64_STPSi: case AArch64_LDPSpre: case AArch64_STPSpre: DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); MCOperand_CreateImm0(Inst, offset); // You shouldn't load to the same register twice in an instruction... if (IsLoad && Rt == Rt2) return SoftFail; // ... or do any operation that writes-back to a transfer register. But note // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) return SoftFail; return Success; } static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd, Rn, Rm; unsigned extend = fieldFromInstruction_4(insn, 10, 6); unsigned shift = extend & 0x7; if (shift > 4) return Fail; Rd = fieldFromInstruction_4(insn, 0, 5); Rn = fieldFromInstruction_4(insn, 5, 5); Rm = fieldFromInstruction_4(insn, 16, 5); switch (MCInst_getOpcode(Inst)) { default: return Fail; case AArch64_ADDWrx: case AArch64_SUBWrx: DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64_ADDSWrx: case AArch64_SUBSWrx: DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64_ADDXrx: case AArch64_SUBXrx: DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64_ADDSXrx: case AArch64_SUBSXrx: DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64_ADDXrx64: case AArch64_SUBXrx64: DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; case AArch64_SUBSXrx64: case AArch64_ADDSXrx64: DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; } MCOperand_CreateImm0(Inst, extend); return Success; } static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); unsigned imm; if (Datasize) { if (MCInst_getOpcode(Inst) == AArch64_ANDSXri) DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); imm = fieldFromInstruction_4(insn, 10, 13); if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) return Fail; } else { if (MCInst_getOpcode(Inst) == AArch64_ANDSWri) DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); imm = fieldFromInstruction_4(insn, 10, 12); if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32)) return Fail; } MCOperand_CreateImm0(Inst, imm); return Success; } static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); unsigned cmode = fieldFromInstruction_4(insn, 12, 4); unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; imm |= fieldFromInstruction_4(insn, 5, 5); if (MCInst_getOpcode(Inst) == AArch64_MOVID) DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); else DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); MCOperand_CreateImm0(Inst, imm); switch (MCInst_getOpcode(Inst)) { default: break; case AArch64_MOVIv4i16: case AArch64_MOVIv8i16: case AArch64_MVNIv4i16: case AArch64_MVNIv8i16: case AArch64_MOVIv2i32: case AArch64_MOVIv4i32: case AArch64_MVNIv2i32: case AArch64_MVNIv4i32: MCOperand_CreateImm0(Inst, (cmode & 6) << 2); break; case AArch64_MOVIv2s_msl: case AArch64_MOVIv4s_msl: case AArch64_MVNIv2s_msl: case AArch64_MVNIv4s_msl: MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108); break; } return Success; } static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); unsigned cmode = fieldFromInstruction_4(insn, 12, 4); unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; imm |= fieldFromInstruction_4(insn, 5, 5); // Tied operands added twice. DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); MCOperand_CreateImm0(Inst, imm); MCOperand_CreateImm0(Inst, (cmode & 6) << 2); return Success; } static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); int64_t imm = fieldFromInstruction_4(insn, 5, 19) << 2; imm |= fieldFromInstruction_4(insn, 29, 2); // Sign-extend the 21-bit immediate. if (imm & (1 << (21 - 1))) imm |= ~((1LL << 21) - 1); DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); //if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) MCOperand_CreateImm0(Inst, imm); return Success; } static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd = fieldFromInstruction_4(insn, 0, 5); unsigned Rn = fieldFromInstruction_4(insn, 5, 5); unsigned Imm = fieldFromInstruction_4(insn, 10, 14); unsigned S = fieldFromInstruction_4(insn, 29, 1); unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); unsigned ShifterVal = (Imm >> 12) & 3; unsigned ImmVal = Imm & 0xFFF; if (ShifterVal != 0 && ShifterVal != 1) return Fail; if (Datasize) { if (Rd == 31 && !S) DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); } else { if (Rd == 31 && !S) DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); } //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) MCOperand_CreateImm0(Inst, ImmVal); MCOperand_CreateImm0(Inst, 12 * ShifterVal); return Success; } static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { int64_t imm = fieldFromInstruction_4(insn, 0, 26); // Sign-extend the 26-bit immediate. if (imm & (1 << (26 - 1))) imm |= ~((1LL << 26) - 1); // if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) MCOperand_CreateImm0(Inst, imm); return Success; } static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { uint32_t op1 = fieldFromInstruction_4(insn, 16, 3); uint32_t op2 = fieldFromInstruction_4(insn, 5, 3); uint32_t crm = fieldFromInstruction_4(insn, 8, 4); uint32_t pstate_field = (op1 << 3) | op2; if ((pstate_field == AArch64PState_PAN || pstate_field == AArch64PState_UAO) && crm > 1) return Fail; MCOperand_CreateImm0(Inst, pstate_field); MCOperand_CreateImm0(Inst, crm); if (lookupPStateByEncoding(pstate_field)) return Success; return Fail; } static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { uint32_t Rt = fieldFromInstruction_4(insn, 0, 5); uint32_t bit = fieldFromInstruction_4(insn, 31, 1) << 5; uint64_t dst = fieldFromInstruction_4(insn, 5, 14); bit |= fieldFromInstruction_4(insn, 19, 5); // Sign-extend 14-bit immediate. if (dst & (1 << (14 - 1))) dst |= ~((1LL << 14) - 1); if (fieldFromInstruction_4(insn, 31, 1) == 0) DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); else DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); MCOperand_CreateImm0(Inst, bit); //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) MCOperand_CreateImm0(Inst, dst); return Success; } static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst *Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) { unsigned Register; // Register number must be even (see CASP instruction) if (RegNo & 0x1) return Fail; Register = AArch64MCRegisterClasses[RegClassID].RegsBegin[RegNo]; MCOperand_CreateReg0(Inst, Register); return Success; } static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { return DecodeGPRSeqPairsClassRegisterClass(Inst, AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder); } static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) { return DecodeGPRSeqPairsClassRegisterClass(Inst, AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder); } static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Zdn = fieldFromInstruction_4(insn, 0, 5); unsigned imm = fieldFromInstruction_4(insn, 5, 13); if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) return Fail; // The same (tied) operand is added twice to the instruction. DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); if (MCInst_getOpcode(Inst) != AArch64_DUPM_ZI) DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); MCOperand_CreateImm0(Inst, imm); return Success; } static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder, int Bits) { if (Imm & ~((1LL << Bits) - 1)) return Fail; // Imm is a signed immediate, so sign extend it. if (Imm & (1 << (Bits - 1))) Imm |= ~((1LL << Bits) - 1); MCOperand_CreateImm0(Inst, Imm); return Success; } // Decode 8-bit signed/unsigned immediate for a given element width. static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder, int ElementWidth) { unsigned Val = (uint8_t)Imm; unsigned Shift = (Imm & 0x100) ? 8 : 0; if (ElementWidth == 8 && Shift) return Fail; MCOperand_CreateImm0(Inst, Val); MCOperand_CreateImm0(Inst, Shift); return Success; } // Decode uimm4 ranged from 1-16. static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder) { MCOperand_CreateImm0(Inst, Imm + 1); return Success; } void AArch64_init(MCRegisterInfo *MRI) { /* InitMCRegisterInfo(AArch64RegDesc, 661, RA, PC, AArch64MCRegisterClasses, 100, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100, AArch64SubRegIdxRanges, AArch64RegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 661, 0, 0, AArch64MCRegisterClasses, 100, 0, 0, AArch64RegDiffLists, 0, AArch64SubRegIdxLists, 100, 0); } #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64Disassembler.h000064400000000000000000000007460072674642500221160ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_AARCH64_DISASSEMBLER_H #define CS_AARCH64_DISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void AArch64_init(MCRegisterInfo *MRI); bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); uint64_t AArch64_getFeatureBits(int feature); #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenAsmWriter.inc000064400000000000000000032626260072674642500224040ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, /* 9 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '0', 9, 0, /* 20 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, /* 31 */ 'l', 'd', '1', 9, 0, /* 36 */ 't', 'r', 'n', '1', 9, 0, /* 42 */ 'z', 'i', 'p', '1', 9, 0, /* 48 */ 'u', 'z', 'p', '1', 9, 0, /* 54 */ 'd', 'c', 'p', 's', '1', 9, 0, /* 61 */ 's', 'm', '3', 's', 's', '1', 9, 0, /* 69 */ 's', 't', '1', 9, 0, /* 74 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, /* 83 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '1', 9, 0, /* 94 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, /* 105 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '1', 9, 0, /* 116 */ 'r', 'a', 'x', '1', 9, 0, /* 122 */ 'r', 'e', 'v', '3', '2', 9, 0, /* 129 */ 'l', 'd', '2', 9, 0, /* 134 */ 's', 'h', 'a', '5', '1', '2', 'h', '2', 9, 0, /* 144 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, /* 154 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, /* 162 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, /* 170 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, /* 180 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, /* 188 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, /* 196 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, /* 204 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, /* 212 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, /* 220 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, /* 228 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, /* 236 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, /* 244 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, /* 252 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, /* 260 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, /* 270 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, /* 278 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, /* 286 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, /* 294 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, /* 304 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, /* 312 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, /* 320 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, /* 328 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, /* 337 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, /* 346 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, /* 355 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, /* 364 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, /* 374 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, /* 384 */ 't', 'r', 'n', '2', 9, 0, /* 390 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, /* 398 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, /* 406 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, /* 414 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, /* 424 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, /* 435 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, /* 444 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, /* 453 */ 'z', 'i', 'p', '2', 9, 0, /* 459 */ 'u', 'z', 'p', '2', 9, 0, /* 465 */ 'd', 'c', 'p', 's', '2', 9, 0, /* 472 */ 's', 't', '2', 9, 0, /* 477 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, /* 485 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, /* 493 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, /* 501 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, /* 509 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '2', 9, 0, /* 520 */ 'l', 'd', '3', 9, 0, /* 525 */ 'e', 'o', 'r', '3', 9, 0, /* 531 */ 'd', 'c', 'p', 's', '3', 9, 0, /* 538 */ 's', 't', '3', 9, 0, /* 543 */ 'r', 'e', 'v', '6', '4', 9, 0, /* 550 */ 'l', 'd', '4', 9, 0, /* 555 */ 's', 't', '4', 9, 0, /* 560 */ 's', 'e', 't', 'f', '1', '6', 9, 0, /* 568 */ 'r', 'e', 'v', '1', '6', 9, 0, /* 575 */ 's', 'e', 't', 'f', '8', 9, 0, /* 582 */ 's', 'm', '3', 't', 't', '1', 'a', 9, 0, /* 591 */ 's', 'm', '3', 't', 't', '2', 'a', 9, 0, /* 600 */ 'b', 'r', 'a', 'a', 9, 0, /* 606 */ 'l', 'd', 'r', 'a', 'a', 9, 0, /* 613 */ 'b', 'l', 'r', 'a', 'a', 9, 0, /* 620 */ 's', 'a', 'b', 'a', 9, 0, /* 626 */ 'u', 'a', 'b', 'a', 9, 0, /* 632 */ 'p', 'a', 'c', 'd', 'a', 9, 0, /* 639 */ 'l', 'd', 'a', 'd', 'd', 'a', 9, 0, /* 647 */ 'f', 'a', 'd', 'd', 'a', 9, 0, /* 654 */ 'a', 'u', 't', 'd', 'a', 9, 0, /* 661 */ 'p', 'a', 'c', 'g', 'a', 9, 0, /* 668 */ 'p', 'a', 'c', 'i', 'a', 9, 0, /* 675 */ 'a', 'u', 't', 'i', 'a', 9, 0, /* 682 */ 'b', 'r', 'k', 'a', 9, 0, /* 688 */ 'f', 'c', 'm', 'l', 'a', 9, 0, /* 695 */ 'f', 'm', 'l', 'a', 9, 0, /* 701 */ 'f', 'n', 'm', 'l', 'a', 9, 0, /* 708 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 9, 0, /* 717 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 9, 0, /* 726 */ 'b', 'r', 'k', 'p', 'a', 9, 0, /* 733 */ 'c', 'a', 's', 'p', 'a', 9, 0, /* 740 */ 's', 'w', 'p', 'a', 9, 0, /* 746 */ 'f', 'e', 'x', 'p', 'a', 9, 0, /* 753 */ 'l', 'd', 'c', 'l', 'r', 'a', 9, 0, /* 761 */ 'l', 'd', 'e', 'o', 'r', 'a', 9, 0, /* 769 */ 's', 'r', 's', 'r', 'a', 9, 0, /* 776 */ 'u', 'r', 's', 'r', 'a', 9, 0, /* 783 */ 's', 's', 'r', 'a', 9, 0, /* 789 */ 'u', 's', 'r', 'a', 9, 0, /* 795 */ 'c', 'a', 's', 'a', 9, 0, /* 801 */ 'l', 'd', 's', 'e', 't', 'a', 9, 0, /* 809 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, /* 817 */ 'c', 'l', 'a', 's', 't', 'a', 9, 0, /* 825 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 9, 0, /* 834 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 9, 0, /* 843 */ 'p', 'a', 'c', 'd', 'z', 'a', 9, 0, /* 851 */ 'a', 'u', 't', 'd', 'z', 'a', 9, 0, /* 859 */ 'p', 'a', 'c', 'i', 'z', 'a', 9, 0, /* 867 */ 'a', 'u', 't', 'i', 'z', 'a', 9, 0, /* 875 */ 'l', 'd', '1', 'b', 9, 0, /* 881 */ 'l', 'd', 'f', 'f', '1', 'b', 9, 0, /* 889 */ 'l', 'd', 'n', 'f', '1', 'b', 9, 0, /* 897 */ 'l', 'd', 'n', 't', '1', 'b', 9, 0, /* 905 */ 's', 't', 'n', 't', '1', 'b', 9, 0, /* 913 */ 's', 't', '1', 'b', 9, 0, /* 919 */ 's', 'm', '3', 't', 't', '1', 'b', 9, 0, /* 928 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, /* 936 */ 'l', 'd', '2', 'b', 9, 0, /* 942 */ 's', 't', '2', 'b', 9, 0, /* 948 */ 's', 'm', '3', 't', 't', '2', 'b', 9, 0, /* 957 */ 'l', 'd', '3', 'b', 9, 0, /* 963 */ 's', 't', '3', 'b', 9, 0, /* 969 */ 'l', 'd', '4', 'b', 9, 0, /* 975 */ 's', 't', '4', 'b', 9, 0, /* 981 */ 'l', 'd', 'a', 'd', 'd', 'a', 'b', 9, 0, /* 990 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'b', 9, 0, /* 1000 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'b', 9, 0, /* 1010 */ 's', 'w', 'p', 'a', 'b', 9, 0, /* 1017 */ 'b', 'r', 'a', 'b', 9, 0, /* 1023 */ 'l', 'd', 'r', 'a', 'b', 9, 0, /* 1030 */ 'b', 'l', 'r', 'a', 'b', 9, 0, /* 1037 */ 'l', 'd', 'c', 'l', 'r', 'a', 'b', 9, 0, /* 1046 */ 'l', 'd', 'e', 'o', 'r', 'a', 'b', 9, 0, /* 1055 */ 'c', 'a', 's', 'a', 'b', 9, 0, /* 1062 */ 'l', 'd', 's', 'e', 't', 'a', 'b', 9, 0, /* 1071 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'b', 9, 0, /* 1081 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'b', 9, 0, /* 1091 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, /* 1100 */ 's', 'q', 'd', 'e', 'c', 'b', 9, 0, /* 1108 */ 'u', 'q', 'd', 'e', 'c', 'b', 9, 0, /* 1116 */ 's', 'q', 'i', 'n', 'c', 'b', 9, 0, /* 1124 */ 'u', 'q', 'i', 'n', 'c', 'b', 9, 0, /* 1132 */ 'p', 'a', 'c', 'd', 'b', 9, 0, /* 1139 */ 'l', 'd', 'a', 'd', 'd', 'b', 9, 0, /* 1147 */ 'a', 'u', 't', 'd', 'b', 9, 0, /* 1154 */ 'p', 'r', 'f', 'b', 9, 0, /* 1160 */ 'p', 'a', 'c', 'i', 'b', 9, 0, /* 1167 */ 'a', 'u', 't', 'i', 'b', 9, 0, /* 1174 */ 'b', 'r', 'k', 'b', 9, 0, /* 1180 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'b', 9, 0, /* 1190 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, /* 1201 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, /* 1212 */ 's', 'w', 'p', 'a', 'l', 'b', 9, 0, /* 1220 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'b', 9, 0, /* 1230 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'b', 9, 0, /* 1240 */ 'c', 'a', 's', 'a', 'l', 'b', 9, 0, /* 1248 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'b', 9, 0, /* 1258 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, /* 1269 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, /* 1280 */ 'l', 'd', 'a', 'd', 'd', 'l', 'b', 9, 0, /* 1289 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'b', 9, 0, /* 1299 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'b', 9, 0, /* 1309 */ 's', 'w', 'p', 'l', 'b', 9, 0, /* 1316 */ 'l', 'd', 'c', 'l', 'r', 'l', 'b', 9, 0, /* 1325 */ 'l', 'd', 'e', 'o', 'r', 'l', 'b', 9, 0, /* 1334 */ 'c', 'a', 's', 'l', 'b', 9, 0, /* 1341 */ 'l', 'd', 's', 'e', 't', 'l', 'b', 9, 0, /* 1350 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'b', 9, 0, /* 1360 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'b', 9, 0, /* 1370 */ 'd', 'm', 'b', 9, 0, /* 1375 */ 'l', 'd', 's', 'm', 'i', 'n', 'b', 9, 0, /* 1384 */ 'l', 'd', 'u', 'm', 'i', 'n', 'b', 9, 0, /* 1393 */ 'b', 'r', 'k', 'p', 'b', 9, 0, /* 1400 */ 's', 'w', 'p', 'b', 9, 0, /* 1406 */ 'l', 'd', '1', 'r', 'q', 'b', 9, 0, /* 1414 */ 'l', 'd', '1', 'r', 'b', 9, 0, /* 1421 */ 'l', 'd', 'a', 'r', 'b', 9, 0, /* 1428 */ 'l', 'd', 'l', 'a', 'r', 'b', 9, 0, /* 1436 */ 'l', 'd', 'r', 'b', 9, 0, /* 1442 */ 'l', 'd', 'c', 'l', 'r', 'b', 9, 0, /* 1450 */ 's', 't', 'l', 'l', 'r', 'b', 9, 0, /* 1458 */ 's', 't', 'l', 'r', 'b', 9, 0, /* 1465 */ 'l', 'd', 'e', 'o', 'r', 'b', 9, 0, /* 1473 */ 'l', 'd', 'a', 'p', 'r', 'b', 9, 0, /* 1481 */ 'l', 'd', 't', 'r', 'b', 9, 0, /* 1488 */ 's', 't', 'r', 'b', 9, 0, /* 1494 */ 's', 't', 't', 'r', 'b', 9, 0, /* 1501 */ 'l', 'd', 'u', 'r', 'b', 9, 0, /* 1508 */ 's', 't', 'l', 'u', 'r', 'b', 9, 0, /* 1516 */ 'l', 'd', 'a', 'p', 'u', 'r', 'b', 9, 0, /* 1525 */ 's', 't', 'u', 'r', 'b', 9, 0, /* 1532 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, /* 1540 */ 'l', 'd', 'x', 'r', 'b', 9, 0, /* 1547 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, /* 1555 */ 's', 't', 'x', 'r', 'b', 9, 0, /* 1562 */ 'l', 'd', '1', 's', 'b', 9, 0, /* 1569 */ 'l', 'd', 'f', 'f', '1', 's', 'b', 9, 0, /* 1578 */ 'l', 'd', 'n', 'f', '1', 's', 'b', 9, 0, /* 1587 */ 'c', 'a', 's', 'b', 9, 0, /* 1593 */ 'd', 's', 'b', 9, 0, /* 1598 */ 'i', 's', 'b', 9, 0, /* 1603 */ 'f', 'm', 's', 'b', 9, 0, /* 1609 */ 'f', 'n', 'm', 's', 'b', 9, 0, /* 1616 */ 'l', 'd', '1', 'r', 's', 'b', 9, 0, /* 1624 */ 'l', 'd', 'r', 's', 'b', 9, 0, /* 1631 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, /* 1639 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, /* 1647 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'b', 9, 0, /* 1657 */ 't', 's', 'b', 9, 0, /* 1662 */ 'l', 'd', 's', 'e', 't', 'b', 9, 0, /* 1670 */ 'c', 'n', 't', 'b', 9, 0, /* 1676 */ 'c', 'l', 'a', 's', 't', 'b', 9, 0, /* 1684 */ 's', 'x', 't', 'b', 9, 0, /* 1690 */ 'u', 'x', 't', 'b', 9, 0, /* 1696 */ 'f', 's', 'u', 'b', 9, 0, /* 1702 */ 's', 'h', 's', 'u', 'b', 9, 0, /* 1709 */ 'u', 'h', 's', 'u', 'b', 9, 0, /* 1716 */ 'f', 'm', 's', 'u', 'b', 9, 0, /* 1723 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, /* 1731 */ 's', 'q', 's', 'u', 'b', 9, 0, /* 1738 */ 'u', 'q', 's', 'u', 'b', 9, 0, /* 1745 */ 'r', 'e', 'v', 'b', 9, 0, /* 1751 */ 'l', 'd', 's', 'm', 'a', 'x', 'b', 9, 0, /* 1760 */ 'l', 'd', 'u', 'm', 'a', 'x', 'b', 9, 0, /* 1769 */ 'p', 'a', 'c', 'd', 'z', 'b', 9, 0, /* 1777 */ 'a', 'u', 't', 'd', 'z', 'b', 9, 0, /* 1785 */ 'p', 'a', 'c', 'i', 'z', 'b', 9, 0, /* 1793 */ 'a', 'u', 't', 'i', 'z', 'b', 9, 0, /* 1801 */ 's', 'h', 'a', '1', 'c', 9, 0, /* 1808 */ 's', 'b', 'c', 9, 0, /* 1813 */ 'a', 'd', 'c', 9, 0, /* 1818 */ 'b', 'i', 'c', 9, 0, /* 1823 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, /* 1831 */ 'a', 'e', 's', 'm', 'c', 9, 0, /* 1838 */ 'c', 's', 'i', 'n', 'c', 9, 0, /* 1845 */ 'h', 'v', 'c', 9, 0, /* 1850 */ 's', 'v', 'c', 9, 0, /* 1855 */ 'l', 'd', '1', 'd', 9, 0, /* 1861 */ 'l', 'd', 'f', 'f', '1', 'd', 9, 0, /* 1869 */ 'l', 'd', 'n', 'f', '1', 'd', 9, 0, /* 1877 */ 'l', 'd', 'n', 't', '1', 'd', 9, 0, /* 1885 */ 's', 't', 'n', 't', '1', 'd', 9, 0, /* 1893 */ 's', 't', '1', 'd', 9, 0, /* 1899 */ 'l', 'd', '2', 'd', 9, 0, /* 1905 */ 's', 't', '2', 'd', 9, 0, /* 1911 */ 'l', 'd', '3', 'd', 9, 0, /* 1917 */ 's', 't', '3', 'd', 9, 0, /* 1923 */ 'l', 'd', '4', 'd', 9, 0, /* 1929 */ 's', 't', '4', 'd', 9, 0, /* 1935 */ 'f', 'm', 'a', 'd', 9, 0, /* 1941 */ 'f', 'n', 'm', 'a', 'd', 9, 0, /* 1948 */ 'f', 't', 'm', 'a', 'd', 9, 0, /* 1955 */ 'f', 'a', 'b', 'd', 9, 0, /* 1961 */ 's', 'a', 'b', 'd', 9, 0, /* 1967 */ 'u', 'a', 'b', 'd', 9, 0, /* 1973 */ 'x', 'p', 'a', 'c', 'd', 9, 0, /* 1980 */ 's', 'q', 'd', 'e', 'c', 'd', 9, 0, /* 1988 */ 'u', 'q', 'd', 'e', 'c', 'd', 9, 0, /* 1996 */ 's', 'q', 'i', 'n', 'c', 'd', 9, 0, /* 2004 */ 'u', 'q', 'i', 'n', 'c', 'd', 9, 0, /* 2012 */ 'f', 'c', 'a', 'd', 'd', 9, 0, /* 2019 */ 'l', 'd', 'a', 'd', 'd', 9, 0, /* 2026 */ 'f', 'a', 'd', 'd', 9, 0, /* 2032 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, /* 2040 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, /* 2048 */ 's', 'h', 'a', 'd', 'd', 9, 0, /* 2055 */ 'u', 'h', 'a', 'd', 'd', 9, 0, /* 2062 */ 'f', 'm', 'a', 'd', 'd', 9, 0, /* 2069 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, /* 2077 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, /* 2085 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, /* 2093 */ 'p', 'r', 'f', 'd', 9, 0, /* 2099 */ 'n', 'a', 'n', 'd', 9, 0, /* 2105 */ 'l', 'd', '1', 'r', 'q', 'd', 9, 0, /* 2113 */ 'l', 'd', '1', 'r', 'd', 9, 0, /* 2120 */ 'a', 's', 'r', 'd', 9, 0, /* 2126 */ 'a', 'e', 's', 'd', 9, 0, /* 2132 */ 'c', 'n', 't', 'd', 9, 0, /* 2138 */ 's', 'm', '4', 'e', 9, 0, /* 2144 */ 's', 'p', 'l', 'i', 'c', 'e', 9, 0, /* 2152 */ 'f', 'a', 'c', 'g', 'e', 9, 0, /* 2159 */ 'f', 'c', 'm', 'g', 'e', 9, 0, /* 2166 */ 'c', 'm', 'p', 'g', 'e', 9, 0, /* 2173 */ 'f', 's', 'c', 'a', 'l', 'e', 9, 0, /* 2181 */ 'w', 'h', 'i', 'l', 'e', 'l', 'e', 9, 0, /* 2190 */ 'f', 'c', 'm', 'l', 'e', 9, 0, /* 2197 */ 'c', 'm', 'p', 'l', 'e', 9, 0, /* 2204 */ 'f', 'c', 'm', 'n', 'e', 9, 0, /* 2211 */ 'c', 't', 'e', 'r', 'm', 'n', 'e', 9, 0, /* 2220 */ 'c', 'm', 'p', 'n', 'e', 9, 0, /* 2227 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, /* 2235 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, /* 2243 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, /* 2251 */ 'f', 'c', 'm', 'p', 'e', 9, 0, /* 2258 */ 'a', 'e', 's', 'e', 9, 0, /* 2264 */ 'p', 'f', 'a', 'l', 's', 'e', 9, 0, /* 2272 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, /* 2281 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, /* 2290 */ 'p', 't', 'r', 'u', 'e', 9, 0, /* 2297 */ 'b', 'i', 'f', 9, 0, /* 2302 */ 'r', 'm', 'i', 'f', 9, 0, /* 2308 */ 's', 'c', 'v', 't', 'f', 9, 0, /* 2315 */ 'u', 'c', 'v', 't', 'f', 9, 0, /* 2322 */ 'f', 'n', 'e', 'g', 9, 0, /* 2328 */ 's', 'q', 'n', 'e', 'g', 9, 0, /* 2335 */ 'c', 's', 'n', 'e', 'g', 9, 0, /* 2342 */ 's', 'h', 'a', '1', 'h', 9, 0, /* 2349 */ 'l', 'd', '1', 'h', 9, 0, /* 2355 */ 'l', 'd', 'f', 'f', '1', 'h', 9, 0, /* 2363 */ 'l', 'd', 'n', 'f', '1', 'h', 9, 0, /* 2371 */ 'l', 'd', 'n', 't', '1', 'h', 9, 0, /* 2379 */ 's', 't', 'n', 't', '1', 'h', 9, 0, /* 2387 */ 's', 't', '1', 'h', 9, 0, /* 2393 */ 's', 'h', 'a', '5', '1', '2', 'h', 9, 0, /* 2402 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, /* 2410 */ 'l', 'd', '2', 'h', 9, 0, /* 2416 */ 's', 't', '2', 'h', 9, 0, /* 2422 */ 'l', 'd', '3', 'h', 9, 0, /* 2428 */ 's', 't', '3', 'h', 9, 0, /* 2434 */ 'l', 'd', '4', 'h', 9, 0, /* 2440 */ 's', 't', '4', 'h', 9, 0, /* 2446 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, /* 2455 */ 'l', 'd', 'a', 'd', 'd', 'a', 'h', 9, 0, /* 2464 */ 's', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 9, 0, /* 2474 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'h', 9, 0, /* 2484 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'h', 9, 0, /* 2494 */ 's', 'w', 'p', 'a', 'h', 9, 0, /* 2501 */ 'l', 'd', 'c', 'l', 'r', 'a', 'h', 9, 0, /* 2510 */ 'l', 'd', 'e', 'o', 'r', 'a', 'h', 9, 0, /* 2519 */ 'c', 'a', 's', 'a', 'h', 9, 0, /* 2526 */ 'l', 'd', 's', 'e', 't', 'a', 'h', 9, 0, /* 2535 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'h', 9, 0, /* 2545 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'h', 9, 0, /* 2555 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, /* 2564 */ 's', 'q', 'd', 'e', 'c', 'h', 9, 0, /* 2572 */ 'u', 'q', 'd', 'e', 'c', 'h', 9, 0, /* 2580 */ 's', 'q', 'i', 'n', 'c', 'h', 9, 0, /* 2588 */ 'u', 'q', 'i', 'n', 'c', 'h', 9, 0, /* 2596 */ 'l', 'd', 'a', 'd', 'd', 'h', 9, 0, /* 2604 */ 'p', 'r', 'f', 'h', 9, 0, /* 2610 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'h', 9, 0, /* 2620 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, /* 2631 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, /* 2642 */ 's', 'w', 'p', 'a', 'l', 'h', 9, 0, /* 2650 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'h', 9, 0, /* 2660 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'h', 9, 0, /* 2670 */ 'c', 'a', 's', 'a', 'l', 'h', 9, 0, /* 2678 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'h', 9, 0, /* 2688 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, /* 2699 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, /* 2710 */ 'l', 'd', 'a', 'd', 'd', 'l', 'h', 9, 0, /* 2719 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'h', 9, 0, /* 2729 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'h', 9, 0, /* 2739 */ 's', 'w', 'p', 'l', 'h', 9, 0, /* 2746 */ 'l', 'd', 'c', 'l', 'r', 'l', 'h', 9, 0, /* 2755 */ 'l', 'd', 'e', 'o', 'r', 'l', 'h', 9, 0, /* 2764 */ 'c', 'a', 's', 'l', 'h', 9, 0, /* 2771 */ 'l', 'd', 's', 'e', 't', 'l', 'h', 9, 0, /* 2780 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, /* 2789 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, /* 2799 */ 's', 'm', 'u', 'l', 'h', 9, 0, /* 2806 */ 'u', 'm', 'u', 'l', 'h', 9, 0, /* 2813 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'h', 9, 0, /* 2823 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'h', 9, 0, /* 2833 */ 'l', 'd', 's', 'm', 'i', 'n', 'h', 9, 0, /* 2842 */ 'l', 'd', 'u', 'm', 'i', 'n', 'h', 9, 0, /* 2851 */ 's', 'w', 'p', 'h', 9, 0, /* 2857 */ 'l', 'd', '1', 'r', 'q', 'h', 9, 0, /* 2865 */ 'l', 'd', '1', 'r', 'h', 9, 0, /* 2872 */ 'l', 'd', 'a', 'r', 'h', 9, 0, /* 2879 */ 'l', 'd', 'l', 'a', 'r', 'h', 9, 0, /* 2887 */ 'l', 'd', 'r', 'h', 9, 0, /* 2893 */ 'l', 'd', 'c', 'l', 'r', 'h', 9, 0, /* 2901 */ 's', 't', 'l', 'l', 'r', 'h', 9, 0, /* 2909 */ 's', 't', 'l', 'r', 'h', 9, 0, /* 2916 */ 'l', 'd', 'e', 'o', 'r', 'h', 9, 0, /* 2924 */ 'l', 'd', 'a', 'p', 'r', 'h', 9, 0, /* 2932 */ 'l', 'd', 't', 'r', 'h', 9, 0, /* 2939 */ 's', 't', 'r', 'h', 9, 0, /* 2945 */ 's', 't', 't', 'r', 'h', 9, 0, /* 2952 */ 'l', 'd', 'u', 'r', 'h', 9, 0, /* 2959 */ 's', 't', 'l', 'u', 'r', 'h', 9, 0, /* 2967 */ 'l', 'd', 'a', 'p', 'u', 'r', 'h', 9, 0, /* 2976 */ 's', 't', 'u', 'r', 'h', 9, 0, /* 2983 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, /* 2991 */ 'l', 'd', 'x', 'r', 'h', 9, 0, /* 2998 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, /* 3006 */ 's', 't', 'x', 'r', 'h', 9, 0, /* 3013 */ 'l', 'd', '1', 's', 'h', 9, 0, /* 3020 */ 'l', 'd', 'f', 'f', '1', 's', 'h', 9, 0, /* 3029 */ 'l', 'd', 'n', 'f', '1', 's', 'h', 9, 0, /* 3038 */ 'c', 'a', 's', 'h', 9, 0, /* 3044 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', 9, 0, /* 3054 */ 'l', 'd', '1', 'r', 's', 'h', 9, 0, /* 3062 */ 'l', 'd', 'r', 's', 'h', 9, 0, /* 3069 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, /* 3077 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, /* 3085 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'h', 9, 0, /* 3095 */ 'l', 'd', 's', 'e', 't', 'h', 9, 0, /* 3103 */ 'c', 'n', 't', 'h', 9, 0, /* 3109 */ 's', 'x', 't', 'h', 9, 0, /* 3115 */ 'u', 'x', 't', 'h', 9, 0, /* 3121 */ 'r', 'e', 'v', 'h', 9, 0, /* 3127 */ 'l', 'd', 's', 'm', 'a', 'x', 'h', 9, 0, /* 3136 */ 'l', 'd', 'u', 'm', 'a', 'x', 'h', 9, 0, /* 3145 */ 'x', 'p', 'a', 'c', 'i', 9, 0, /* 3152 */ 'p', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, /* 3161 */ 's', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, /* 3170 */ 'u', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, /* 3179 */ 'c', 'm', 'h', 'i', 9, 0, /* 3185 */ 'c', 'm', 'p', 'h', 'i', 9, 0, /* 3192 */ 's', 'l', 'i', 9, 0, /* 3197 */ 'm', 'v', 'n', 'i', 9, 0, /* 3203 */ 's', 'r', 'i', 9, 0, /* 3208 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, /* 3216 */ 'm', 'o', 'v', 'i', 9, 0, /* 3222 */ 'b', 'r', 'k', 9, 0, /* 3227 */ 'm', 'o', 'v', 'k', 9, 0, /* 3233 */ 's', 'a', 'b', 'a', 'l', 9, 0, /* 3240 */ 'u', 'a', 'b', 'a', 'l', 9, 0, /* 3247 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 9, 0, /* 3256 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, /* 3265 */ 's', 'm', 'l', 'a', 'l', 9, 0, /* 3272 */ 'u', 'm', 'l', 'a', 'l', 9, 0, /* 3279 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 9, 0, /* 3289 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 9, 0, /* 3299 */ 'c', 'a', 's', 'p', 'a', 'l', 9, 0, /* 3307 */ 's', 'w', 'p', 'a', 'l', 9, 0, /* 3314 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 9, 0, /* 3323 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 9, 0, /* 3332 */ 'c', 'a', 's', 'a', 'l', 9, 0, /* 3339 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 9, 0, /* 3348 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 9, 0, /* 3358 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 9, 0, /* 3368 */ 't', 'b', 'l', 9, 0, /* 3373 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, /* 3381 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, /* 3389 */ 's', 's', 'u', 'b', 'l', 9, 0, /* 3396 */ 'u', 's', 'u', 'b', 'l', 9, 0, /* 3403 */ 's', 'a', 'b', 'd', 'l', 9, 0, /* 3410 */ 'u', 'a', 'b', 'd', 'l', 9, 0, /* 3417 */ 'l', 'd', 'a', 'd', 'd', 'l', 9, 0, /* 3425 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, /* 3433 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, /* 3441 */ 's', 'a', 'd', 'd', 'l', 9, 0, /* 3448 */ 'u', 'a', 'd', 'd', 'l', 9, 0, /* 3455 */ 'f', 'c', 's', 'e', 'l', 9, 0, /* 3462 */ 'f', 't', 's', 's', 'e', 'l', 9, 0, /* 3470 */ 's', 'q', 's', 'h', 'l', 9, 0, /* 3477 */ 'u', 'q', 's', 'h', 'l', 9, 0, /* 3484 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, /* 3492 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, /* 3500 */ 's', 'r', 's', 'h', 'l', 9, 0, /* 3507 */ 'u', 'r', 's', 'h', 'l', 9, 0, /* 3514 */ 's', 's', 'h', 'l', 9, 0, /* 3520 */ 'u', 's', 'h', 'l', 9, 0, /* 3526 */ 's', 's', 'h', 'l', 'l', 9, 0, /* 3533 */ 'u', 's', 'h', 'l', 'l', 9, 0, /* 3540 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, /* 3549 */ 'p', 'm', 'u', 'l', 'l', 9, 0, /* 3556 */ 's', 'm', 'u', 'l', 'l', 9, 0, /* 3563 */ 'u', 'm', 'u', 'l', 'l', 9, 0, /* 3570 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 9, 0, /* 3579 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 9, 0, /* 3588 */ 'a', 'd', 'd', 'p', 'l', 9, 0, /* 3595 */ 'c', 'a', 's', 'p', 'l', 9, 0, /* 3602 */ 's', 'w', 'p', 'l', 9, 0, /* 3608 */ 'l', 'd', 'c', 'l', 'r', 'l', 9, 0, /* 3616 */ 'l', 'd', 'e', 'o', 'r', 'l', 9, 0, /* 3624 */ 'c', 'a', 's', 'l', 9, 0, /* 3630 */ 'b', 's', 'l', 9, 0, /* 3635 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, /* 3644 */ 's', 'm', 'l', 's', 'l', 9, 0, /* 3651 */ 'u', 'm', 'l', 's', 'l', 9, 0, /* 3658 */ 's', 'y', 's', 'l', 9, 0, /* 3664 */ 'l', 'd', 's', 'e', 't', 'l', 9, 0, /* 3672 */ 'f', 'c', 'v', 't', 'l', 9, 0, /* 3679 */ 'f', 'm', 'u', 'l', 9, 0, /* 3685 */ 'f', 'n', 'm', 'u', 'l', 9, 0, /* 3692 */ 'p', 'm', 'u', 'l', 9, 0, /* 3698 */ 'f', 't', 's', 'm', 'u', 'l', 9, 0, /* 3706 */ 'a', 'd', 'd', 'v', 'l', 9, 0, /* 3713 */ 'r', 'd', 'v', 'l', 9, 0, /* 3719 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 9, 0, /* 3728 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 9, 0, /* 3737 */ 's', 'h', 'a', '1', 'm', 9, 0, /* 3744 */ 's', 'b', 'f', 'm', 9, 0, /* 3750 */ 'u', 'b', 'f', 'm', 9, 0, /* 3756 */ 'p', 'r', 'f', 'm', 9, 0, /* 3762 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, /* 3770 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, /* 3778 */ 'd', 'u', 'p', 'm', 9, 0, /* 3784 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, /* 3792 */ 'p', 'r', 'f', 'u', 'm', 9, 0, /* 3799 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, /* 3807 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, /* 3815 */ 'f', 'm', 'i', 'n', 9, 0, /* 3821 */ 'l', 'd', 's', 'm', 'i', 'n', 9, 0, /* 3829 */ 'l', 'd', 'u', 'm', 'i', 'n', 9, 0, /* 3837 */ 'b', 'r', 'k', 'n', 9, 0, /* 3843 */ 'c', 'c', 'm', 'n', 9, 0, /* 3849 */ 'e', 'o', 'n', 9, 0, /* 3854 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, /* 3862 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, /* 3870 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, /* 3879 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, /* 3888 */ 'o', 'r', 'n', 9, 0, /* 3893 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, /* 3901 */ 'f', 'c', 'v', 't', 'n', 9, 0, /* 3908 */ 's', 'q', 'x', 't', 'n', 9, 0, /* 3915 */ 'u', 'q', 'x', 't', 'n', 9, 0, /* 3922 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, /* 3931 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, /* 3941 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, /* 3949 */ 'm', 'o', 'v', 'n', 9, 0, /* 3955 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, /* 3963 */ 'w', 'h', 'i', 'l', 'e', 'l', 'o', 9, 0, /* 3972 */ 'p', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, /* 3981 */ 's', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, /* 3990 */ 'u', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, /* 3999 */ 'c', 'm', 'p', 'l', 'o', 9, 0, /* 4006 */ 'f', 'c', 'm', 'u', 'o', 9, 0, /* 4013 */ 's', 'h', 'a', '1', 'p', 9, 0, /* 4020 */ 's', 'q', 'd', 'e', 'c', 'p', 9, 0, /* 4028 */ 'u', 'q', 'd', 'e', 'c', 'p', 9, 0, /* 4036 */ 's', 'q', 'i', 'n', 'c', 'p', 9, 0, /* 4044 */ 'u', 'q', 'i', 'n', 'c', 'p', 9, 0, /* 4052 */ 'f', 'a', 'd', 'd', 'p', 9, 0, /* 4059 */ 'l', 'd', 'p', 9, 0, /* 4064 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, /* 4072 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, /* 4080 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, /* 4088 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, /* 4096 */ 'f', 'c', 'c', 'm', 'p', 9, 0, /* 4103 */ 'f', 'c', 'm', 'p', 9, 0, /* 4109 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, /* 4118 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, /* 4127 */ 'l', 'd', 'n', 'p', 9, 0, /* 4133 */ 'f', 'm', 'i', 'n', 'p', 9, 0, /* 4140 */ 's', 'm', 'i', 'n', 'p', 9, 0, /* 4147 */ 'u', 'm', 'i', 'n', 'p', 9, 0, /* 4154 */ 's', 't', 'n', 'p', 9, 0, /* 4160 */ 'a', 'd', 'r', 'p', 9, 0, /* 4166 */ 'c', 'a', 's', 'p', 9, 0, /* 4172 */ 'c', 'n', 't', 'p', 9, 0, /* 4178 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, /* 4186 */ 's', 't', 'p', 9, 0, /* 4191 */ 'f', 'd', 'u', 'p', 9, 0, /* 4197 */ 's', 'w', 'p', 9, 0, /* 4202 */ 'l', 'd', 'a', 'x', 'p', 9, 0, /* 4209 */ 'f', 'm', 'a', 'x', 'p', 9, 0, /* 4216 */ 's', 'm', 'a', 'x', 'p', 9, 0, /* 4223 */ 'u', 'm', 'a', 'x', 'p', 9, 0, /* 4230 */ 'l', 'd', 'x', 'p', 9, 0, /* 4236 */ 's', 't', 'l', 'x', 'p', 9, 0, /* 4243 */ 's', 't', 'x', 'p', 9, 0, /* 4249 */ 'f', 'c', 'm', 'e', 'q', 9, 0, /* 4256 */ 'c', 't', 'e', 'r', 'm', 'e', 'q', 9, 0, /* 4265 */ 'c', 'm', 'p', 'e', 'q', 9, 0, /* 4272 */ 'l', 'd', '1', 'r', 9, 0, /* 4278 */ 'l', 'd', '2', 'r', 9, 0, /* 4284 */ 'l', 'd', '3', 'r', 9, 0, /* 4290 */ 'l', 'd', '4', 'r', 9, 0, /* 4296 */ 'l', 'd', 'a', 'r', 9, 0, /* 4302 */ 'l', 'd', 'l', 'a', 'r', 9, 0, /* 4309 */ 'x', 'a', 'r', 9, 0, /* 4314 */ 'f', 's', 'u', 'b', 'r', 9, 0, /* 4321 */ 'a', 'd', 'r', 9, 0, /* 4326 */ 'l', 'd', 'r', 9, 0, /* 4331 */ 'r', 'd', 'f', 'f', 'r', 9, 0, /* 4338 */ 'w', 'r', 'f', 'f', 'r', 9, 0, /* 4345 */ 's', 'r', 's', 'h', 'r', 9, 0, /* 4352 */ 'u', 'r', 's', 'h', 'r', 9, 0, /* 4359 */ 's', 's', 'h', 'r', 9, 0, /* 4365 */ 'u', 's', 'h', 'r', 9, 0, /* 4371 */ 'b', 'l', 'r', 9, 0, /* 4376 */ 'l', 'd', 'c', 'l', 'r', 9, 0, /* 4383 */ 's', 't', 'l', 'l', 'r', 9, 0, /* 4390 */ 'l', 's', 'l', 'r', 9, 0, /* 4396 */ 's', 't', 'l', 'r', 9, 0, /* 4402 */ 'l', 'd', 'e', 'o', 'r', 9, 0, /* 4409 */ 'n', 'o', 'r', 9, 0, /* 4414 */ 'r', 'o', 'r', 9, 0, /* 4419 */ 'l', 'd', 'a', 'p', 'r', 9, 0, /* 4426 */ 'o', 'r', 'r', 9, 0, /* 4431 */ 'a', 's', 'r', 'r', 9, 0, /* 4437 */ 'l', 's', 'r', 'r', 9, 0, /* 4443 */ 'a', 's', 'r', 9, 0, /* 4448 */ 'l', 's', 'r', 9, 0, /* 4453 */ 'm', 's', 'r', 9, 0, /* 4458 */ 'i', 'n', 's', 'r', 9, 0, /* 4464 */ 'l', 'd', 't', 'r', 9, 0, /* 4470 */ 's', 't', 'r', 9, 0, /* 4475 */ 's', 't', 't', 'r', 9, 0, /* 4481 */ 'e', 'x', 't', 'r', 9, 0, /* 4487 */ 'l', 'd', 'u', 'r', 9, 0, /* 4493 */ 's', 't', 'l', 'u', 'r', 9, 0, /* 4500 */ 'l', 'd', 'a', 'p', 'u', 'r', 9, 0, /* 4508 */ 's', 't', 'u', 'r', 9, 0, /* 4514 */ 'f', 'd', 'i', 'v', 'r', 9, 0, /* 4521 */ 's', 'd', 'i', 'v', 'r', 9, 0, /* 4528 */ 'u', 'd', 'i', 'v', 'r', 9, 0, /* 4535 */ 'l', 'd', 'a', 'x', 'r', 9, 0, /* 4542 */ 'l', 'd', 'x', 'r', 9, 0, /* 4548 */ 's', 't', 'l', 'x', 'r', 9, 0, /* 4555 */ 's', 't', 'x', 'r', 9, 0, /* 4561 */ 'c', 'a', 's', 9, 0, /* 4566 */ 'b', 'r', 'k', 'a', 's', 9, 0, /* 4573 */ 'b', 'r', 'k', 'p', 'a', 's', 9, 0, /* 4581 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, /* 4589 */ 'f', 'a', 'b', 's', 9, 0, /* 4595 */ 's', 'q', 'a', 'b', 's', 9, 0, /* 4602 */ 'b', 'r', 'k', 'b', 's', 9, 0, /* 4609 */ 'b', 'r', 'k', 'p', 'b', 's', 9, 0, /* 4617 */ 's', 'u', 'b', 's', 9, 0, /* 4623 */ 's', 'b', 'c', 's', 9, 0, /* 4629 */ 'a', 'd', 'c', 's', 9, 0, /* 4635 */ 'b', 'i', 'c', 's', 9, 0, /* 4641 */ 'a', 'd', 'd', 's', 9, 0, /* 4647 */ 'n', 'a', 'n', 'd', 's', 9, 0, /* 4654 */ 'p', 't', 'r', 'u', 'e', 's', 9, 0, /* 4662 */ 'c', 'm', 'h', 's', 9, 0, /* 4668 */ 'c', 'm', 'p', 'h', 's', 9, 0, /* 4675 */ 'c', 'l', 's', 9, 0, /* 4680 */ 'w', 'h', 'i', 'l', 'e', 'l', 's', 9, 0, /* 4689 */ 'f', 'm', 'l', 's', 9, 0, /* 4695 */ 'f', 'n', 'm', 'l', 's', 9, 0, /* 4702 */ 'c', 'm', 'p', 'l', 's', 9, 0, /* 4709 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, /* 4717 */ 'i', 'n', 's', 9, 0, /* 4722 */ 'b', 'r', 'k', 'n', 's', 9, 0, /* 4729 */ 'o', 'r', 'n', 's', 9, 0, /* 4735 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, /* 4743 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, /* 4751 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, /* 4759 */ 'r', 'd', 'f', 'f', 'r', 's', 9, 0, /* 4767 */ 'm', 'r', 's', 9, 0, /* 4772 */ 'e', 'o', 'r', 's', 9, 0, /* 4778 */ 'n', 'o', 'r', 's', 9, 0, /* 4784 */ 'o', 'r', 'r', 's', 9, 0, /* 4790 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, /* 4799 */ 's', 'y', 's', 9, 0, /* 4804 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, /* 4812 */ 'f', 'j', 'c', 'v', 't', 'z', 's', 9, 0, /* 4821 */ 'c', 'o', 'm', 'p', 'a', 'c', 't', 9, 0, /* 4830 */ 'r', 'e', 't', 9, 0, /* 4835 */ 'l', 'd', 's', 'e', 't', 9, 0, /* 4842 */ 'f', 'a', 'c', 'g', 't', 9, 0, /* 4849 */ 'f', 'c', 'm', 'g', 't', 9, 0, /* 4856 */ 'c', 'm', 'p', 'g', 't', 9, 0, /* 4863 */ 'r', 'b', 'i', 't', 9, 0, /* 4869 */ 'w', 'h', 'i', 'l', 'e', 'l', 't', 9, 0, /* 4878 */ 'h', 'l', 't', 9, 0, /* 4883 */ 'f', 'c', 'm', 'l', 't', 9, 0, /* 4890 */ 'c', 'm', 'p', 'l', 't', 9, 0, /* 4897 */ 'c', 'n', 't', 9, 0, /* 4902 */ 'h', 'i', 'n', 't', 9, 0, /* 4908 */ 's', 'd', 'o', 't', 9, 0, /* 4914 */ 'u', 'd', 'o', 't', 9, 0, /* 4920 */ 'c', 'n', 'o', 't', 9, 0, /* 4926 */ 'f', 's', 'q', 'r', 't', 9, 0, /* 4933 */ 'p', 't', 'e', 's', 't', 9, 0, /* 4940 */ 'p', 'f', 'i', 'r', 's', 't', 9, 0, /* 4948 */ 'c', 'm', 't', 's', 't', 9, 0, /* 4955 */ 'f', 'c', 'v', 't', 9, 0, /* 4961 */ 'p', 'n', 'e', 'x', 't', 9, 0, /* 4968 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, /* 4976 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, /* 4984 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, /* 4992 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, /* 5000 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, /* 5008 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, /* 5016 */ 'f', 'a', 'd', 'd', 'v', 9, 0, /* 5023 */ 's', 'a', 'd', 'd', 'v', 9, 0, /* 5030 */ 'u', 'a', 'd', 'd', 'v', 9, 0, /* 5037 */ 'a', 'n', 'd', 'v', 9, 0, /* 5043 */ 'r', 'e', 'v', 9, 0, /* 5048 */ 'f', 'd', 'i', 'v', 9, 0, /* 5054 */ 's', 'd', 'i', 'v', 9, 0, /* 5060 */ 'u', 'd', 'i', 'v', 9, 0, /* 5066 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, /* 5074 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, /* 5082 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, /* 5091 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, /* 5100 */ 'f', 'm', 'i', 'n', 'v', 9, 0, /* 5107 */ 's', 'm', 'i', 'n', 'v', 9, 0, /* 5114 */ 'u', 'm', 'i', 'n', 'v', 9, 0, /* 5121 */ 'c', 's', 'i', 'n', 'v', 9, 0, /* 5128 */ 'f', 'm', 'o', 'v', 9, 0, /* 5134 */ 's', 'm', 'o', 'v', 9, 0, /* 5140 */ 'u', 'm', 'o', 'v', 9, 0, /* 5146 */ 'e', 'o', 'r', 'v', 9, 0, /* 5152 */ 'f', 'm', 'a', 'x', 'v', 9, 0, /* 5159 */ 's', 'm', 'a', 'x', 'v', 9, 0, /* 5166 */ 'u', 'm', 'a', 'x', 'v', 9, 0, /* 5173 */ 'l', 'd', '1', 'w', 9, 0, /* 5179 */ 'l', 'd', 'f', 'f', '1', 'w', 9, 0, /* 5187 */ 'l', 'd', 'n', 'f', '1', 'w', 9, 0, /* 5195 */ 'l', 'd', 'n', 't', '1', 'w', 9, 0, /* 5203 */ 's', 't', 'n', 't', '1', 'w', 9, 0, /* 5211 */ 's', 't', '1', 'w', 9, 0, /* 5217 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, /* 5225 */ 'l', 'd', '2', 'w', 9, 0, /* 5231 */ 's', 't', '2', 'w', 9, 0, /* 5237 */ 'l', 'd', '3', 'w', 9, 0, /* 5243 */ 's', 't', '3', 'w', 9, 0, /* 5249 */ 'l', 'd', '4', 'w', 9, 0, /* 5255 */ 's', 't', '4', 'w', 9, 0, /* 5261 */ 's', 's', 'u', 'b', 'w', 9, 0, /* 5268 */ 'u', 's', 'u', 'b', 'w', 9, 0, /* 5275 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, /* 5284 */ 's', 'q', 'd', 'e', 'c', 'w', 9, 0, /* 5292 */ 'u', 'q', 'd', 'e', 'c', 'w', 9, 0, /* 5300 */ 's', 'q', 'i', 'n', 'c', 'w', 9, 0, /* 5308 */ 'u', 'q', 'i', 'n', 'c', 'w', 9, 0, /* 5316 */ 's', 'a', 'd', 'd', 'w', 9, 0, /* 5323 */ 'u', 'a', 'd', 'd', 'w', 9, 0, /* 5330 */ 'p', 'r', 'f', 'w', 9, 0, /* 5336 */ 'l', 'd', '1', 'r', 'q', 'w', 9, 0, /* 5344 */ 'l', 'd', '1', 'r', 'w', 9, 0, /* 5351 */ 'l', 'd', '1', 's', 'w', 9, 0, /* 5358 */ 'l', 'd', 'f', 'f', '1', 's', 'w', 9, 0, /* 5367 */ 'l', 'd', 'n', 'f', '1', 's', 'w', 9, 0, /* 5376 */ 'l', 'd', 'p', 's', 'w', 9, 0, /* 5383 */ 'l', 'd', '1', 'r', 's', 'w', 9, 0, /* 5391 */ 'l', 'd', 'r', 's', 'w', 9, 0, /* 5398 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, /* 5406 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, /* 5414 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'w', 9, 0, /* 5424 */ 'c', 'n', 't', 'w', 9, 0, /* 5430 */ 's', 'x', 't', 'w', 9, 0, /* 5436 */ 'u', 'x', 't', 'w', 9, 0, /* 5442 */ 'r', 'e', 'v', 'w', 9, 0, /* 5448 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, /* 5456 */ 'b', 'c', 'a', 'x', 9, 0, /* 5462 */ 'f', 'm', 'a', 'x', 9, 0, /* 5468 */ 'l', 'd', 's', 'm', 'a', 'x', 9, 0, /* 5476 */ 'l', 'd', 'u', 'm', 'a', 'x', 9, 0, /* 5484 */ 't', 'b', 'x', 9, 0, /* 5489 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, /* 5498 */ 'i', 'n', 'd', 'e', 'x', 9, 0, /* 5505 */ 'c', 'l', 'r', 'e', 'x', 9, 0, /* 5512 */ 'm', 'o', 'v', 'p', 'r', 'f', 'x', 9, 0, /* 5521 */ 'f', 'm', 'u', 'l', 'x', 9, 0, /* 5528 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, /* 5536 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, /* 5544 */ 's', 'm', '4', 'e', 'k', 'e', 'y', 9, 0, /* 5553 */ 'f', 'c', 'p', 'y', 9, 0, /* 5559 */ 'b', 'r', 'a', 'a', 'z', 9, 0, /* 5566 */ 'b', 'l', 'r', 'a', 'a', 'z', 9, 0, /* 5574 */ 'b', 'r', 'a', 'b', 'z', 9, 0, /* 5581 */ 'b', 'l', 'r', 'a', 'b', 'z', 9, 0, /* 5589 */ 'c', 'b', 'z', 9, 0, /* 5594 */ 't', 'b', 'z', 9, 0, /* 5599 */ 'c', 'l', 'z', 9, 0, /* 5604 */ 'c', 'b', 'n', 'z', 9, 0, /* 5610 */ 't', 'b', 'n', 'z', 9, 0, /* 5616 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, /* 5624 */ 'm', 'o', 'v', 'z', 9, 0, /* 5630 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, /* 5644 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, /* 5675 */ 'b', '.', 0, /* 5678 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 5702 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 5727 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, /* 5750 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, /* 5773 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, /* 5795 */ 'p', 'a', 'c', 'i', 'a', '1', '7', '1', '6', 0, /* 5805 */ 'a', 'u', 't', 'i', 'a', '1', '7', '1', '6', 0, /* 5815 */ 'p', 'a', 'c', 'i', 'b', '1', '7', '1', '6', 0, /* 5825 */ 'a', 'u', 't', 'i', 'b', '1', '7', '1', '6', 0, /* 5835 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 5848 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 5855 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 5865 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, /* 5875 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 5890 */ 'e', 'r', 'e', 't', 'a', 'a', 0, /* 5897 */ 'e', 'r', 'e', 't', 'a', 'b', 0, /* 5904 */ 'x', 'p', 'a', 'c', 'l', 'r', 'i', 0, /* 5912 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 5926 */ 'p', 'a', 'c', 'i', 'a', 's', 'p', 0, /* 5934 */ 'a', 'u', 't', 'i', 'a', 's', 'p', 0, /* 5942 */ 'p', 'a', 'c', 'i', 'b', 's', 'p', 0, /* 5950 */ 'a', 'u', 't', 'i', 'b', 's', 'p', 0, /* 5958 */ 's', 'e', 't', 'f', 'f', 'r', 0, /* 5965 */ 'd', 'r', 'p', 's', 0, /* 5970 */ 'e', 'r', 'e', 't', 0, /* 5975 */ 'c', 'f', 'i', 'n', 'v', 0, /* 5981 */ 'p', 'a', 'c', 'i', 'a', 'z', 0, /* 5988 */ 'a', 'u', 't', 'i', 'a', 'z', 0, /* 5995 */ 'p', 'a', 'c', 'i', 'b', 'z', 0, /* 6002 */ 'a', 'u', 't', 'i', 'b', 'z', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 5856U, // DBG_VALUE 5866U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 5849U, // BUNDLE 5876U, // LIFETIME_START 5836U, // LIFETIME_END 0U, // STACKMAP 5913U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 5728U, // PATCHABLE_FUNCTION_ENTER 5645U, // PATCHABLE_RET 5774U, // PATCHABLE_FUNCTION_EXIT 5751U, // PATCHABLE_TAIL_CALL 5703U, // PATCHABLE_EVENT_CALL 5679U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 12783U, // ABS_ZPmZ_B 20975U, // ABS_ZPmZ_D 2181591535U, // ABS_ZPmZ_H 37359U, // ABS_ZPmZ_S 68202991U, // ABSv16i8 2248200687U, // ABSv1i64 68727279U, // ABSv2i32 2216735215U, // ABSv2i64 69775855U, // ABSv4i16 2217783791U, // ABSv4i32 70824431U, // ABSv8i16 2218832367U, // ABSv8i8 100717078U, // ADCSWr 100717078U, // ADCSXr 100714262U, // ADCWr 100714262U, // ADCXr 2216210145U, // ADDHNv2i64_v2i32 2284904787U, // ADDHNv2i64_v4i32 69775073U, // ADDHNv4i32_v4i16 137945427U, // ADDHNv4i32_v8i16 2282807635U, // ADDHNv8i16_v16i8 2218831585U, // ADDHNv8i16_v8i8 100716037U, // ADDPL_XXI 68202454U, // ADDPv16i8 2216210390U, // ADDPv2i32 2216734678U, // ADDPv2i64 2214645718U, // ADDPv2i64p 69775318U, // ADDPv4i16 70299606U, // ADDPv4i32 2218307542U, // ADDPv8i16 2218831830U, // ADDPv8i8 100717090U, // ADDSWri 0U, // ADDSWrr 100717090U, // ADDSWrs 100717090U, // ADDSWrx 100717090U, // ADDSXri 0U, // ADDSXrr 100717090U, // ADDSXrs 100717090U, // ADDSXrx 100717090U, // ADDSXrx64 100716155U, // ADDVL_XXI 67163034U, // ADDVv16i8v 67163034U, // ADDVv4i16v 2214646682U, // ADDVv4i32v 67163034U, // ADDVv8i16v 2214646682U, // ADDVv8i8v 100714463U, // ADDWri 0U, // ADDWrr 100714463U, // ADDWrs 100714463U, // ADDWrx 100714463U, // ADDXri 0U, // ADDXrr 100714463U, // ADDXrs 100714463U, // ADDXrx 100714463U, // ADDXrx64 167782367U, // ADD_ZI_B 201344991U, // ADD_ZI_D 239626207U, // ADD_ZI_H 268470239U, // ADD_ZI_S 302000095U, // ADD_ZPmZ_B 302008287U, // ADD_ZPmZ_D 2186307551U, // ADD_ZPmZ_H 302024671U, // ADD_ZPmZ_S 167782367U, // ADD_ZZZ_B 201344991U, // ADD_ZZZ_D 2387109855U, // ADD_ZZZ_H 268470239U, // ADD_ZZZ_S 0U, // ADDlowTLS 68200415U, // ADDv16i8 100714463U, // ADDv1i64 2216208351U, // ADDv2i32 2216732639U, // ADDv2i64 69773279U, // ADDv4i16 70297567U, // ADDv4i32 2218305503U, // ADDv8i16 2218829791U, // ADDv8i8 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 2248200418U, // ADR 335597633U, // ADRP 207114466U, // ADR_LSL_ZZZ_D_0 207114466U, // ADR_LSL_ZZZ_D_1 207114466U, // ADR_LSL_ZZZ_D_2 207114466U, // ADR_LSL_ZZZ_D_3 274239714U, // ADR_LSL_ZZZ_S_0 274239714U, // ADR_LSL_ZZZ_S_1 274239714U, // ADR_LSL_ZZZ_S_2 274239714U, // ADR_LSL_ZZZ_S_3 207114466U, // ADR_SXTW_ZZZ_D_0 207114466U, // ADR_SXTW_ZZZ_D_1 207114466U, // ADR_SXTW_ZZZ_D_2 207114466U, // ADR_SXTW_ZZZ_D_3 207114466U, // ADR_UXTW_ZZZ_D_0 207114466U, // ADR_UXTW_ZZZ_D_1 207114466U, // ADR_UXTW_ZZZ_D_2 207114466U, // ADR_UXTW_ZZZ_D_3 135325775U, // AESDrr 135325907U, // AESErr 68200224U, // AESIMCrr 0U, // AESIMCrrTied 68200232U, // AESMCrr 0U, // AESMCrrTied 100717097U, // ANDSWri 0U, // ANDSWrr 100717097U, // ANDSWrs 100717097U, // ANDSXri 0U, // ANDSXrr 100717097U, // ANDSXrs 302002729U, // ANDS_PPzPP 302044078U, // ANDV_VPZ_B 302044078U, // ANDV_VPZ_D 302044078U, // ANDV_VPZ_H 302044078U, // ANDV_VPZ_S 100714549U, // ANDWri 0U, // ANDWrr 100714549U, // ANDWrs 100714549U, // ANDXri 0U, // ANDXrr 100714549U, // ANDXrs 302000181U, // AND_PPzPP 201345077U, // AND_ZI 302000181U, // AND_ZPmZ_B 302008373U, // AND_ZPmZ_D 2186307637U, // AND_ZPmZ_H 302024757U, // AND_ZPmZ_S 201345077U, // AND_ZZZ 68200501U, // ANDv16i8 2218829877U, // ANDv8i8 302000201U, // ASRD_ZPmI_B 302008393U, // ASRD_ZPmI_D 2186307657U, // ASRD_ZPmI_H 302024777U, // ASRD_ZPmI_S 302002512U, // ASRR_ZPmZ_B 302010704U, // ASRR_ZPmZ_D 2186309968U, // ASRR_ZPmZ_H 302027088U, // ASRR_ZPmZ_S 100716892U, // ASRVWr 100716892U, // ASRVXr 302002524U, // ASR_WIDE_ZPmZ_B 2186309980U, // ASR_WIDE_ZPmZ_H 302027100U, // ASR_WIDE_ZPmZ_S 167784796U, // ASR_WIDE_ZZZ_B 2387112284U, // ASR_WIDE_ZZZ_H 268472668U, // ASR_WIDE_ZZZ_S 302002524U, // ASR_ZPmI_B 302010716U, // ASR_ZPmI_D 2186309980U, // ASR_ZPmI_H 302027100U, // ASR_ZPmI_S 302002524U, // ASR_ZPmZ_B 302010716U, // ASR_ZPmZ_D 2186309980U, // ASR_ZPmZ_H 302027100U, // ASR_ZPmZ_S 167784796U, // ASR_ZZI_B 201347420U, // ASR_ZZI_D 239628636U, // ASR_ZZI_H 268472668U, // ASR_ZZI_S 2248196751U, // AUTDA 2248197244U, // AUTDB 6341460U, // AUTDZA 6342386U, // AUTDZB 2248196772U, // AUTIA 5806U, // AUTIA1716 5935U, // AUTIASP 5989U, // AUTIAZ 2248197264U, // AUTIB 5826U, // AUTIB1716 5951U, // AUTIBSP 6003U, // AUTIBZ 6341476U, // AUTIZA 6342402U, // AUTIZB 66415U, // B 68203857U, // BCAX 369151650U, // BFMWri 369151650U, // BFMXri 0U, // BICSWrr 100717084U, // BICSWrs 0U, // BICSXrr 100717084U, // BICSXrs 302002716U, // BICS_PPzPP 0U, // BICWrr 100714267U, // BICWrs 0U, // BICXrr 100714267U, // BICXrs 301999899U, // BIC_PPzPP 301999899U, // BIC_ZPmZ_B 302008091U, // BIC_ZPmZ_D 2186307355U, // BIC_ZPmZ_H 302024475U, // BIC_ZPmZ_S 201344795U, // BIC_ZZZ 68200219U, // BICv16i8 404285211U, // BICv2i32 405333787U, // BICv4i16 405858075U, // BICv4i32 406382363U, // BICv8i16 2218829595U, // BICv8i8 68200698U, // BIFv16i8 2218830074U, // BIFv8i8 135328513U, // BITv16i8 2285957889U, // BITv8i8 68906U, // BL 6344980U, // BLR 2248196710U, // BLRAA 6346175U, // BLRAAZ 2248197127U, // BLRAB 6346190U, // BLRABZ 6344926U, // BR 2248196697U, // BRAA 6346168U, // BRAAZ 2248197114U, // BRAB 6346183U, // BRABZ 76951U, // BRK 302002647U, // BRKAS_PPzP 8875U, // BRKA_PPmP 301998763U, // BRKA_PPzP 302002683U, // BRKBS_PPzP 9367U, // BRKB_PPmP 301999255U, // BRKB_PPzP 302002803U, // BRKNS_PPzP 302001918U, // BRKN_PPzP 302002654U, // BRKPAS_PPzPP 301998807U, // BRKPA_PPzPP 302002690U, // BRKPBS_PPzPP 301999474U, // BRKPB_PPzPP 135327279U, // BSLv16i8 2285956655U, // BSLv8i8 87596U, // Bcc 2516673568U, // CASAB 2516675032U, // CASAH 2516673753U, // CASALB 2516675183U, // CASALH 2516675845U, // CASALW 2516675845U, // CASALX 2516673308U, // CASAW 2516673308U, // CASAX 2516674100U, // CASB 2516675551U, // CASH 2516673847U, // CASLB 2516675277U, // CASLH 2516676137U, // CASLW 2516676137U, // CASLX 101604U, // CASPALW 109796U, // CASPALX 99038U, // CASPAW 107230U, // CASPAX 101900U, // CASPLW 110092U, // CASPLX 102471U, // CASPW 110663U, // CASPX 2516677074U, // CASW 2516677074U, // CASX 436262373U, // CBNZW 436262373U, // CBNZX 436262358U, // CBZW 436262358U, // CBZX 100716292U, // CCMNWi 100716292U, // CCMNWr 100716292U, // CCMNXi 100716292U, // CCMNXr 100716546U, // CCMPWi 100716546U, // CCMPWr 100716546U, // CCMPXi 100716546U, // CCMPXr 5976U, // CFINV 302039858U, // CLASTA_RPZ_B 302039858U, // CLASTA_RPZ_D 302039858U, // CLASTA_RPZ_H 302039858U, // CLASTA_RPZ_S 302039858U, // CLASTA_VPZ_B 302039858U, // CLASTA_VPZ_D 302039858U, // CLASTA_VPZ_H 302039858U, // CLASTA_VPZ_S 301998898U, // CLASTA_ZPZ_B 302007090U, // CLASTA_ZPZ_D 2387632946U, // CLASTA_ZPZ_H 302023474U, // CLASTA_ZPZ_S 302040717U, // CLASTB_RPZ_B 302040717U, // CLASTB_RPZ_D 302040717U, // CLASTB_RPZ_H 302040717U, // CLASTB_RPZ_S 302040717U, // CLASTB_VPZ_B 302040717U, // CLASTB_VPZ_D 302040717U, // CLASTB_VPZ_H 302040717U, // CLASTB_VPZ_S 301999757U, // CLASTB_ZPZ_B 302007949U, // CLASTB_ZPZ_D 2387633805U, // CLASTB_ZPZ_H 302024333U, // CLASTB_ZPZ_S 6346114U, // CLREX 2248200772U, // CLSWr 2248200772U, // CLSXr 12868U, // CLS_ZPmZ_B 21060U, // CLS_ZPmZ_D 2181591620U, // CLS_ZPmZ_H 37444U, // CLS_ZPmZ_S 68203076U, // CLSv16i8 68727364U, // CLSv2i32 69775940U, // CLSv4i16 2217783876U, // CLSv4i32 70824516U, // CLSv8i16 2218832452U, // CLSv8i8 2248201696U, // CLZWr 2248201696U, // CLZXr 13792U, // CLZ_ZPmZ_B 21984U, // CLZ_ZPmZ_D 2181592544U, // CLZ_ZPmZ_H 38368U, // CLZ_ZPmZ_S 68204000U, // CLZv16i8 68728288U, // CLZv2i32 69776864U, // CLZv4i16 2217784800U, // CLZv4i32 70825440U, // CLZv8i16 2218833376U, // CLZv8i8 68202651U, // CMEQv16i8 68202651U, // CMEQv16i8rz 100716699U, // CMEQv1i64 2248200347U, // CMEQv1i64rz 2216210587U, // CMEQv2i32 68726939U, // CMEQv2i32rz 2216734875U, // CMEQv2i64 2216734875U, // CMEQv2i64rz 69775515U, // CMEQv4i16 69775515U, // CMEQv4i16rz 70299803U, // CMEQv4i32 2217783451U, // CMEQv4i32rz 2218307739U, // CMEQv8i16 70824091U, // CMEQv8i16rz 2218832027U, // CMEQv8i8 2218832027U, // CMEQv8i8rz 68200561U, // CMGEv16i8 68200561U, // CMGEv16i8rz 100714609U, // CMGEv1i64 2248198257U, // CMGEv1i64rz 2216208497U, // CMGEv2i32 68724849U, // CMGEv2i32rz 2216732785U, // CMGEv2i64 2216732785U, // CMGEv2i64rz 69773425U, // CMGEv4i16 69773425U, // CMGEv4i16rz 70297713U, // CMGEv4i32 2217781361U, // CMGEv4i32rz 2218305649U, // CMGEv8i16 70822001U, // CMGEv8i16rz 2218829937U, // CMGEv8i8 2218829937U, // CMGEv8i8rz 68203251U, // CMGTv16i8 68203251U, // CMGTv16i8rz 100717299U, // CMGTv1i64 2248200947U, // CMGTv1i64rz 2216211187U, // CMGTv2i32 68727539U, // CMGTv2i32rz 2216735475U, // CMGTv2i64 2216735475U, // CMGTv2i64rz 69776115U, // CMGTv4i16 69776115U, // CMGTv4i16rz 70300403U, // CMGTv4i32 2217784051U, // CMGTv4i32rz 2218308339U, // CMGTv8i16 70824691U, // CMGTv8i16rz 2218832627U, // CMGTv8i8 2218832627U, // CMGTv8i8rz 68201580U, // CMHIv16i8 100715628U, // CMHIv1i64 2216209516U, // CMHIv2i32 2216733804U, // CMHIv2i64 69774444U, // CMHIv4i16 70298732U, // CMHIv4i32 2218306668U, // CMHIv8i16 2218830956U, // CMHIv8i8 68203063U, // CMHSv16i8 100717111U, // CMHSv1i64 2216210999U, // CMHSv2i32 2216735287U, // CMHSv2i64 69775927U, // CMHSv4i16 70300215U, // CMHSv4i32 2218308151U, // CMHSv8i16 2218832439U, // CMHSv8i8 68200592U, // CMLEv16i8rz 2248198288U, // CMLEv1i64rz 68724880U, // CMLEv2i32rz 2216732816U, // CMLEv2i64rz 69773456U, // CMLEv4i16rz 2217781392U, // CMLEv4i32rz 70822032U, // CMLEv8i16rz 2218829968U, // CMLEv8i8rz 68203285U, // CMLTv16i8rz 2248200981U, // CMLTv1i64rz 68727573U, // CMLTv2i32rz 2216735509U, // CMLTv2i64rz 69776149U, // CMLTv4i16rz 2217784085U, // CMLTv4i32rz 70824725U, // CMLTv8i16rz 2218832661U, // CMLTv8i8rz 302002346U, // CMPEQ_PPzZI_B 302010538U, // CMPEQ_PPzZI_D 2622517418U, // CMPEQ_PPzZI_H 302026922U, // CMPEQ_PPzZI_S 302002346U, // CMPEQ_PPzZZ_B 302010538U, // CMPEQ_PPzZZ_D 2622517418U, // CMPEQ_PPzZZ_H 302026922U, // CMPEQ_PPzZZ_S 302002346U, // CMPEQ_WIDE_PPzZZ_B 2622517418U, // CMPEQ_WIDE_PPzZZ_H 302026922U, // CMPEQ_WIDE_PPzZZ_S 302000247U, // CMPGE_PPzZI_B 302008439U, // CMPGE_PPzZI_D 2622515319U, // CMPGE_PPzZI_H 302024823U, // CMPGE_PPzZI_S 302000247U, // CMPGE_PPzZZ_B 302008439U, // CMPGE_PPzZZ_D 2622515319U, // CMPGE_PPzZZ_H 302024823U, // CMPGE_PPzZZ_S 302000247U, // CMPGE_WIDE_PPzZZ_B 2622515319U, // CMPGE_WIDE_PPzZZ_H 302024823U, // CMPGE_WIDE_PPzZZ_S 302002937U, // CMPGT_PPzZI_B 302011129U, // CMPGT_PPzZI_D 2622518009U, // CMPGT_PPzZI_H 302027513U, // CMPGT_PPzZI_S 302002937U, // CMPGT_PPzZZ_B 302011129U, // CMPGT_PPzZZ_D 2622518009U, // CMPGT_PPzZZ_H 302027513U, // CMPGT_PPzZZ_S 302002937U, // CMPGT_WIDE_PPzZZ_B 2622518009U, // CMPGT_WIDE_PPzZZ_H 302027513U, // CMPGT_WIDE_PPzZZ_S 302001266U, // CMPHI_PPzZI_B 302009458U, // CMPHI_PPzZI_D 2622516338U, // CMPHI_PPzZI_H 302025842U, // CMPHI_PPzZI_S 302001266U, // CMPHI_PPzZZ_B 302009458U, // CMPHI_PPzZZ_D 2622516338U, // CMPHI_PPzZZ_H 302025842U, // CMPHI_PPzZZ_S 302001266U, // CMPHI_WIDE_PPzZZ_B 2622516338U, // CMPHI_WIDE_PPzZZ_H 302025842U, // CMPHI_WIDE_PPzZZ_S 302002749U, // CMPHS_PPzZI_B 302010941U, // CMPHS_PPzZI_D 2622517821U, // CMPHS_PPzZI_H 302027325U, // CMPHS_PPzZI_S 302002749U, // CMPHS_PPzZZ_B 302010941U, // CMPHS_PPzZZ_D 2622517821U, // CMPHS_PPzZZ_H 302027325U, // CMPHS_PPzZZ_S 302002749U, // CMPHS_WIDE_PPzZZ_B 2622517821U, // CMPHS_WIDE_PPzZZ_H 302027325U, // CMPHS_WIDE_PPzZZ_S 302000278U, // CMPLE_PPzZI_B 302008470U, // CMPLE_PPzZI_D 2622515350U, // CMPLE_PPzZI_H 302024854U, // CMPLE_PPzZI_S 302000278U, // CMPLE_WIDE_PPzZZ_B 2622515350U, // CMPLE_WIDE_PPzZZ_H 302024854U, // CMPLE_WIDE_PPzZZ_S 302002080U, // CMPLO_PPzZI_B 302010272U, // CMPLO_PPzZI_D 2622517152U, // CMPLO_PPzZI_H 302026656U, // CMPLO_PPzZI_S 302002080U, // CMPLO_WIDE_PPzZZ_B 2622517152U, // CMPLO_WIDE_PPzZZ_H 302026656U, // CMPLO_WIDE_PPzZZ_S 302002783U, // CMPLS_PPzZI_B 302010975U, // CMPLS_PPzZI_D 2622517855U, // CMPLS_PPzZI_H 302027359U, // CMPLS_PPzZI_S 302002783U, // CMPLS_WIDE_PPzZZ_B 2622517855U, // CMPLS_WIDE_PPzZZ_H 302027359U, // CMPLS_WIDE_PPzZZ_S 302002971U, // CMPLT_PPzZI_B 302011163U, // CMPLT_PPzZI_D 2622518043U, // CMPLT_PPzZI_H 302027547U, // CMPLT_PPzZI_S 302002971U, // CMPLT_WIDE_PPzZZ_B 2622518043U, // CMPLT_WIDE_PPzZZ_H 302027547U, // CMPLT_WIDE_PPzZZ_S 302000301U, // CMPNE_PPzZI_B 302008493U, // CMPNE_PPzZI_D 2622515373U, // CMPNE_PPzZI_H 302024877U, // CMPNE_PPzZI_S 302000301U, // CMPNE_PPzZZ_B 302008493U, // CMPNE_PPzZZ_D 2622515373U, // CMPNE_PPzZZ_H 302024877U, // CMPNE_PPzZZ_S 302000301U, // CMPNE_WIDE_PPzZZ_B 2622515373U, // CMPNE_WIDE_PPzZZ_H 302024877U, // CMPNE_WIDE_PPzZZ_S 0U, // CMP_SWAP_128 0U, // CMP_SWAP_16 0U, // CMP_SWAP_32 0U, // CMP_SWAP_64 0U, // CMP_SWAP_8 68203349U, // CMTSTv16i8 100717397U, // CMTSTv1i64 2216211285U, // CMTSTv2i32 2216735573U, // CMTSTv2i64 69776213U, // CMTSTv4i16 70300501U, // CMTSTv4i32 2218308437U, // CMTSTv8i16 2218832725U, // CMTSTv8i8 13113U, // CNOT_ZPmZ_B 21305U, // CNOT_ZPmZ_D 2181591865U, // CNOT_ZPmZ_H 37689U, // CNOT_ZPmZ_S 503367303U, // CNTB_XPiI 503367765U, // CNTD_XPiI 503368736U, // CNTH_XPiI 302043213U, // CNTP_XPP_B 302043213U, // CNTP_XPP_D 302043213U, // CNTP_XPP_H 302043213U, // CNTP_XPP_S 503371057U, // CNTW_XPiI 13090U, // CNT_ZPmZ_B 21282U, // CNT_ZPmZ_D 2181591842U, // CNT_ZPmZ_H 37666U, // CNT_ZPmZ_S 68203298U, // CNTv16i8 2218832674U, // CNTv8i8 302011094U, // COMPACT_ZPZ_D 302027478U, // COMPACT_ZPZ_S 13747U, // CPY_ZPmI_B 21939U, // CPY_ZPmI_D 2181592499U, // CPY_ZPmI_H 38323U, // CPY_ZPmI_S 13747U, // CPY_ZPmR_B 21939U, // CPY_ZPmR_D 34108851U, // CPY_ZPmR_H 38323U, // CPY_ZPmR_S 13747U, // CPY_ZPmV_B 21939U, // CPY_ZPmV_D 34108851U, // CPY_ZPmV_H 38323U, // CPY_ZPmV_S 302003635U, // CPY_ZPzI_B 302011827U, // CPY_ZPzI_D 2622518707U, // CPY_ZPzI_H 302028211U, // CPY_ZPzI_S 67163146U, // CPYi16 2214646794U, // CPYi32 67163146U, // CPYi64 2214646794U, // CPYi8 100713377U, // CRC32Brr 100713540U, // CRC32CBrr 100715004U, // CRC32CHrr 100717724U, // CRC32CWrr 100717938U, // CRC32CXrr 100714851U, // CRC32Hrr 100717666U, // CRC32Wrr 100717897U, // CRC32Xrr 100715905U, // CSELWr 100715905U, // CSELXr 100714287U, // CSINCWr 100714287U, // CSINCXr 100717570U, // CSINVWr 100717570U, // CSINVXr 100714784U, // CSNEGWr 100714784U, // CSNEGXr 2248200353U, // CTERMEQ_WW 2248200353U, // CTERMEQ_XX 2248198308U, // CTERMNE_WW 2248198308U, // CTERMNE_XX 0U, // CompilerBarrier 73783U, // DCPS1 74194U, // DCPS2 74260U, // DCPS3 536921167U, // DECB_XPiI 536922047U, // DECD_XPiI 536889279U, // DECD_ZPiI 536922631U, // DECH_XPiI 6842887U, // DECH_ZPiI 2315308983U, // DECP_XP_B 2348863415U, // DECP_XP_D 2717962167U, // DECP_XP_H 2415972279U, // DECP_XP_S 2147504055U, // DECP_ZP_D 604532663U, // DECP_ZP_H 2147520439U, // DECP_ZP_S 536925351U, // DECW_XPiI 536908967U, // DECW_ZPiI 116059U, // DMB 5966U, // DRPS 116282U, // DSB 637554371U, // DUPM_ZI 671101025U, // DUP_ZI_B 704663649U, // DUP_ZI_D 7368801U, // DUP_ZI_H 738234465U, // DUP_ZI_S 2248159329U, // DUP_ZR_B 2248167521U, // DUP_ZR_D 611872865U, // DUP_ZR_H 2248183905U, // DUP_ZR_S 167784545U, // DUP_ZZI_B 201347169U, // DUP_ZZI_D 776499297U, // DUP_ZZI_H 127073U, // DUP_ZZI_Q 268472417U, // DUP_ZZI_S 2249240673U, // DUPv16i8gpr 2215686241U, // DUPv16i8lane 2249764961U, // DUPv2i32gpr 2216210529U, // DUPv2i32lane 2250289249U, // DUPv2i64gpr 69251169U, // DUPv2i64lane 2250813537U, // DUPv4i16gpr 69775457U, // DUPv4i16lane 2251337825U, // DUPv4i32gpr 2217783393U, // DUPv4i32lane 2251862113U, // DUPv8i16gpr 70824033U, // DUPv8i16lane 2252386401U, // DUPv8i8gpr 2218831969U, // DUPv8i8lane 0U, // EONWrr 100716298U, // EONWrs 0U, // EONXrr 100716298U, // EONXrs 68198926U, // EOR3 302002853U, // EORS_PPzPP 302044187U, // EORV_VPZ_B 302044187U, // EORV_VPZ_D 302044187U, // EORV_VPZ_H 302044187U, // EORV_VPZ_S 100716853U, // EORWri 0U, // EORWrr 100716853U, // EORWrs 100716853U, // EORXri 0U, // EORXrr 100716853U, // EORXrs 302002485U, // EOR_PPzPP 201347381U, // EOR_ZI 302002485U, // EOR_ZPmZ_B 302010677U, // EOR_ZPmZ_D 2186309941U, // EOR_ZPmZ_H 302027061U, // EOR_ZPmZ_S 201347381U, // EOR_ZZZ 68202805U, // EORv16i8 2218832181U, // EORv8i8 5971U, // ERET 5891U, // ERETAA 5898U, // ERETAB 100716930U, // EXTRWrri 100716930U, // EXTRXrri 167785316U, // EXT_ZZI 68203364U, // EXTv16i8 2218832740U, // EXTv8i8 0U, // F128CSEL 100714404U, // FABD16 100714404U, // FABD32 100714404U, // FABD64 302008228U, // FABD_ZPmZ_D 2186307492U, // FABD_ZPmZ_H 302024612U, // FABD_ZPmZ_S 2216208292U, // FABDv2f32 2216732580U, // FABDv2f64 69773220U, // FABDv4f16 70297508U, // FABDv4f32 2218305444U, // FABDv8f16 2248200686U, // FABSDr 2248200686U, // FABSHr 2248200686U, // FABSSr 20974U, // FABS_ZPmZ_D 2181591534U, // FABS_ZPmZ_H 37358U, // FABS_ZPmZ_S 68727278U, // FABSv2f32 2216735214U, // FABSv2f64 69775854U, // FABSv4f16 2217783790U, // FABSv4f32 70824430U, // FABSv8f16 100714601U, // FACGE16 100714601U, // FACGE32 100714601U, // FACGE64 302008425U, // FACGE_PPzZZ_D 2622515305U, // FACGE_PPzZZ_H 302024809U, // FACGE_PPzZZ_S 2216208489U, // FACGEv2f32 2216732777U, // FACGEv2f64 69773417U, // FACGEv4f16 70297705U, // FACGEv4f32 2218305641U, // FACGEv8f16 100717291U, // FACGT16 100717291U, // FACGT32 100717291U, // FACGT64 302011115U, // FACGT_PPzZZ_D 2622517995U, // FACGT_PPzZZ_H 302027499U, // FACGT_PPzZZ_S 2216211179U, // FACGTv2f32 2216735467U, // FACGTv2f64 69776107U, // FACGTv4f16 70300395U, // FACGTv4f32 2218308331U, // FACGTv8f16 302039688U, // FADDA_VPZ_D 302039688U, // FADDA_VPZ_H 302039688U, // FADDA_VPZ_S 100714475U, // FADDDrr 100714475U, // FADDHrr 2216210389U, // FADDPv2f32 2216734677U, // FADDPv2f64 2214645717U, // FADDPv2i16p 67162069U, // FADDPv2i32p 2214645717U, // FADDPv2i64p 69775317U, // FADDPv4f16 70299605U, // FADDPv4f32 2218307541U, // FADDPv8f16 100714475U, // FADDSrr 302044057U, // FADDV_VPZ_D 302044057U, // FADDV_VPZ_H 302044057U, // FADDV_VPZ_S 302008299U, // FADD_ZPmI_D 2186307563U, // FADD_ZPmI_H 302024683U, // FADD_ZPmI_S 302008299U, // FADD_ZPmZ_D 2186307563U, // FADD_ZPmZ_H 302024683U, // FADD_ZPmZ_S 201345003U, // FADD_ZZZ_D 2387109867U, // FADD_ZZZ_H 268470251U, // FADD_ZZZ_S 2216208363U, // FADDv2f32 2216732651U, // FADDv2f64 69773291U, // FADDv4f16 70297579U, // FADDv4f32 2218305515U, // FADDv8f16 302008285U, // FCADD_ZPmZ_D 2186307549U, // FCADD_ZPmZ_H 302024669U, // FCADD_ZPmZ_S 2216208349U, // FCADDv2f32 2216732637U, // FCADDv2f64 69773277U, // FCADDv4f16 70297565U, // FCADDv4f32 2218305501U, // FCADDv8f16 100716545U, // FCCMPDrr 100714692U, // FCCMPEDrr 100714692U, // FCCMPEHrr 100714692U, // FCCMPESrr 100716545U, // FCCMPHrr 100716545U, // FCCMPSrr 100716698U, // FCMEQ16 100716698U, // FCMEQ32 100716698U, // FCMEQ64 302010522U, // FCMEQ_PPzZ0_D 2622517402U, // FCMEQ_PPzZ0_H 302026906U, // FCMEQ_PPzZ0_S 302010522U, // FCMEQ_PPzZZ_D 2622517402U, // FCMEQ_PPzZZ_H 302026906U, // FCMEQ_PPzZZ_S 100716698U, // FCMEQv1i16rz 100716698U, // FCMEQv1i32rz 100716698U, // FCMEQv1i64rz 2216210586U, // FCMEQv2f32 2216734874U, // FCMEQv2f64 2216210586U, // FCMEQv2i32rz 69251226U, // FCMEQv2i64rz 69775514U, // FCMEQv4f16 70299802U, // FCMEQv4f32 2217259162U, // FCMEQv4i16rz 70299802U, // FCMEQv4i32rz 2218307738U, // FCMEQv8f16 2218307738U, // FCMEQv8i16rz 100714608U, // FCMGE16 100714608U, // FCMGE32 100714608U, // FCMGE64 302008432U, // FCMGE_PPzZ0_D 2622515312U, // FCMGE_PPzZ0_H 302024816U, // FCMGE_PPzZ0_S 302008432U, // FCMGE_PPzZZ_D 2622515312U, // FCMGE_PPzZZ_H 302024816U, // FCMGE_PPzZZ_S 100714608U, // FCMGEv1i16rz 100714608U, // FCMGEv1i32rz 100714608U, // FCMGEv1i64rz 2216208496U, // FCMGEv2f32 2216732784U, // FCMGEv2f64 2216208496U, // FCMGEv2i32rz 69249136U, // FCMGEv2i64rz 69773424U, // FCMGEv4f16 70297712U, // FCMGEv4f32 2217257072U, // FCMGEv4i16rz 70297712U, // FCMGEv4i32rz 2218305648U, // FCMGEv8f16 2218305648U, // FCMGEv8i16rz 100717298U, // FCMGT16 100717298U, // FCMGT32 100717298U, // FCMGT64 302011122U, // FCMGT_PPzZ0_D 2622518002U, // FCMGT_PPzZ0_H 302027506U, // FCMGT_PPzZ0_S 302011122U, // FCMGT_PPzZZ_D 2622518002U, // FCMGT_PPzZZ_H 302027506U, // FCMGT_PPzZZ_S 100717298U, // FCMGTv1i16rz 100717298U, // FCMGTv1i32rz 100717298U, // FCMGTv1i64rz 2216211186U, // FCMGTv2f32 2216735474U, // FCMGTv2f64 2216211186U, // FCMGTv2i32rz 69251826U, // FCMGTv2i64rz 69776114U, // FCMGTv4f16 70300402U, // FCMGTv4f32 2217259762U, // FCMGTv4i16rz 70300402U, // FCMGTv4i32rz 2218308338U, // FCMGTv8f16 2218308338U, // FCMGTv8i16rz 302006961U, // FCMLA_ZPmZZ_D 2186306225U, // FCMLA_ZPmZZ_H 302023345U, // FCMLA_ZPmZZ_S 243294897U, // FCMLA_ZZZI_H 2952823473U, // FCMLA_ZZZI_S 2283332273U, // FCMLAv2f32 2283856561U, // FCMLAv2f64 136897201U, // FCMLAv4f16 136897201U, // FCMLAv4f16_indexed 137421489U, // FCMLAv4f32 137421489U, // FCMLAv4f32_indexed 2285429425U, // FCMLAv8f16 2285429425U, // FCMLAv8f16_indexed 302008463U, // FCMLE_PPzZ0_D 2622515343U, // FCMLE_PPzZ0_H 302024847U, // FCMLE_PPzZ0_S 100714639U, // FCMLEv1i16rz 100714639U, // FCMLEv1i32rz 100714639U, // FCMLEv1i64rz 2216208527U, // FCMLEv2i32rz 69249167U, // FCMLEv2i64rz 2217257103U, // FCMLEv4i16rz 70297743U, // FCMLEv4i32rz 2218305679U, // FCMLEv8i16rz 302011156U, // FCMLT_PPzZ0_D 2622518036U, // FCMLT_PPzZ0_H 302027540U, // FCMLT_PPzZ0_S 100717332U, // FCMLTv1i16rz 100717332U, // FCMLTv1i32rz 100717332U, // FCMLTv1i64rz 2216211220U, // FCMLTv2i32rz 69251860U, // FCMLTv2i64rz 2217259796U, // FCMLTv4i16rz 70300436U, // FCMLTv4i32rz 2218308372U, // FCMLTv8i16rz 302008477U, // FCMNE_PPzZ0_D 2622515357U, // FCMNE_PPzZ0_H 302024861U, // FCMNE_PPzZ0_S 302008477U, // FCMNE_PPzZZ_D 2622515357U, // FCMNE_PPzZZ_H 302024861U, // FCMNE_PPzZZ_S 8966152U, // FCMPDri 2248200200U, // FCMPDrr 8964300U, // FCMPEDri 2248198348U, // FCMPEDrr 8964300U, // FCMPEHri 2248198348U, // FCMPEHrr 8964300U, // FCMPESri 2248198348U, // FCMPESrr 8966152U, // FCMPHri 2248200200U, // FCMPHrr 8966152U, // FCMPSri 2248200200U, // FCMPSrr 302010279U, // FCMUO_PPzZZ_D 2622517159U, // FCMUO_PPzZZ_H 302026663U, // FCMUO_PPzZZ_S 21938U, // FCPY_ZPmI_D 34108850U, // FCPY_ZPmI_H 38322U, // FCPY_ZPmI_S 100715904U, // FCSELDrrr 100715904U, // FCSELHrrr 100715904U, // FCSELSrrr 2248200678U, // FCVTASUWDr 2248200678U, // FCVTASUWHr 2248200678U, // FCVTASUWSr 2248200678U, // FCVTASUXDr 2248200678U, // FCVTASUXHr 2248200678U, // FCVTASUXSr 2248200678U, // FCVTASv1f16 2248200678U, // FCVTASv1i32 2248200678U, // FCVTASv1i64 68727270U, // FCVTASv2f32 2216735206U, // FCVTASv2f64 69775846U, // FCVTASv4f16 2217783782U, // FCVTASv4f32 70824422U, // FCVTASv8f16 2248201065U, // FCVTAUUWDr 2248201065U, // FCVTAUUWHr 2248201065U, // FCVTAUUWSr 2248201065U, // FCVTAUUXDr 2248201065U, // FCVTAUUXHr 2248201065U, // FCVTAUUXSr 2248201065U, // FCVTAUv1f16 2248201065U, // FCVTAUv1i32 2248201065U, // FCVTAUv1i64 68727657U, // FCVTAUv2f32 2216735593U, // FCVTAUv2f64 69776233U, // FCVTAUv4f16 2217784169U, // FCVTAUv4f32 70824809U, // FCVTAUv8f16 2248201052U, // FCVTDHr 2248201052U, // FCVTDSr 2248201052U, // FCVTHDr 2248201052U, // FCVTHSr 69250649U, // FCVTLv2i32 70299225U, // FCVTLv4i16 2216730945U, // FCVTLv4i32 70295873U, // FCVTLv8i16 2248200806U, // FCVTMSUWDr 2248200806U, // FCVTMSUWHr 2248200806U, // FCVTMSUWSr 2248200806U, // FCVTMSUXDr 2248200806U, // FCVTMSUXHr 2248200806U, // FCVTMSUXSr 2248200806U, // FCVTMSv1f16 2248200806U, // FCVTMSv1i32 2248200806U, // FCVTMSv1i64 68727398U, // FCVTMSv2f32 2216735334U, // FCVTMSv2f64 69775974U, // FCVTMSv4f16 2217783910U, // FCVTMSv4f32 70824550U, // FCVTMSv8f16 2248201081U, // FCVTMUUWDr 2248201081U, // FCVTMUUWHr 2248201081U, // FCVTMUUWSr 2248201081U, // FCVTMUUXDr 2248201081U, // FCVTMUUXHr 2248201081U, // FCVTMUUXSr 2248201081U, // FCVTMUv1f16 2248201081U, // FCVTMUv1i32 2248201081U, // FCVTMUv1i64 68727673U, // FCVTMUv2f32 2216735609U, // FCVTMUv2f64 69776249U, // FCVTMUv4f16 2217784185U, // FCVTMUv4f32 70824825U, // FCVTMUv8f16 2248200832U, // FCVTNSUWDr 2248200832U, // FCVTNSUWHr 2248200832U, // FCVTNSUWSr 2248200832U, // FCVTNSUXDr 2248200832U, // FCVTNSUXHr 2248200832U, // FCVTNSUXSr 2248200832U, // FCVTNSv1f16 2248200832U, // FCVTNSv1i32 2248200832U, // FCVTNSv1i64 68727424U, // FCVTNSv2f32 2216735360U, // FCVTNSv2f64 69776000U, // FCVTNSv4f16 2217783936U, // FCVTNSv4f32 70824576U, // FCVTNSv8f16 2248201089U, // FCVTNUUWDr 2248201089U, // FCVTNUUWHr 2248201089U, // FCVTNUUWSr 2248201089U, // FCVTNUUXDr 2248201089U, // FCVTNUUXHr 2248201089U, // FCVTNUUXSr 2248201089U, // FCVTNUv1f16 2248201089U, // FCVTNUv1i32 2248201089U, // FCVTNUv1i64 68727681U, // FCVTNUv2f32 2216735617U, // FCVTNUv2f64 69776257U, // FCVTNUv4f16 2217784193U, // FCVTNUv4f32 70824833U, // FCVTNUv8f16 2216210238U, // FCVTNv2i32 2217258814U, // FCVTNv4i16 2284904839U, // FCVTNv4i32 2285429127U, // FCVTNv8i16 2248200848U, // FCVTPSUWDr 2248200848U, // FCVTPSUWHr 2248200848U, // FCVTPSUWSr 2248200848U, // FCVTPSUXDr 2248200848U, // FCVTPSUXHr 2248200848U, // FCVTPSUXSr 2248200848U, // FCVTPSv1f16 2248200848U, // FCVTPSv1i32 2248200848U, // FCVTPSv1i64 68727440U, // FCVTPSv2f32 2216735376U, // FCVTPSv2f64 69776016U, // FCVTPSv4f16 2217783952U, // FCVTPSv4f32 70824592U, // FCVTPSv8f16 2248201097U, // FCVTPUUWDr 2248201097U, // FCVTPUUWHr 2248201097U, // FCVTPUUWSr 2248201097U, // FCVTPUUXDr 2248201097U, // FCVTPUUXHr 2248201097U, // FCVTPUUXSr 2248201097U, // FCVTPUv1f16 2248201097U, // FCVTPUv1i32 2248201097U, // FCVTPUv1i64 68727689U, // FCVTPUv2f32 2216735625U, // FCVTPUv2f64 69776265U, // FCVTPUv4f16 2217784201U, // FCVTPUv4f32 70824841U, // FCVTPUv8f16 2248201052U, // FCVTSDr 2248201052U, // FCVTSHr 2248200052U, // FCVTXNv1i64 2216210292U, // FCVTXNv2f32 2284904893U, // FCVTXNv4f32 100717253U, // FCVTZSSWDri 100717253U, // FCVTZSSWHri 100717253U, // FCVTZSSWSri 100717253U, // FCVTZSSXDri 100717253U, // FCVTZSSXHri 100717253U, // FCVTZSSXSri 2248200901U, // FCVTZSUWDr 2248200901U, // FCVTZSUWHr 2248200901U, // FCVTZSUWSr 2248200901U, // FCVTZSUXDr 2248200901U, // FCVTZSUXHr 2248200901U, // FCVTZSUXSr 21189U, // FCVTZS_ZPmZ_DtoD 37573U, // FCVTZS_ZPmZ_DtoS 21189U, // FCVTZS_ZPmZ_HtoD 2181591749U, // FCVTZS_ZPmZ_HtoH 37573U, // FCVTZS_ZPmZ_HtoS 21189U, // FCVTZS_ZPmZ_StoD 37573U, // FCVTZS_ZPmZ_StoS 100717253U, // FCVTZSd 100717253U, // FCVTZSh 100717253U, // FCVTZSs 2248200901U, // FCVTZSv1f16 2248200901U, // FCVTZSv1i32 2248200901U, // FCVTZSv1i64 68727493U, // FCVTZSv2f32 2216735429U, // FCVTZSv2f64 2216211141U, // FCVTZSv2i32_shift 2216735429U, // FCVTZSv2i64_shift 69776069U, // FCVTZSv4f16 2217784005U, // FCVTZSv4f32 69776069U, // FCVTZSv4i16_shift 70300357U, // FCVTZSv4i32_shift 70824645U, // FCVTZSv8f16 2218308293U, // FCVTZSv8i16_shift 100717457U, // FCVTZUSWDri 100717457U, // FCVTZUSWHri 100717457U, // FCVTZUSWSri 100717457U, // FCVTZUSXDri 100717457U, // FCVTZUSXHri 100717457U, // FCVTZUSXSri 2248201105U, // FCVTZUUWDr 2248201105U, // FCVTZUUWHr 2248201105U, // FCVTZUUWSr 2248201105U, // FCVTZUUXDr 2248201105U, // FCVTZUUXHr 2248201105U, // FCVTZUUXSr 21393U, // FCVTZU_ZPmZ_DtoD 37777U, // FCVTZU_ZPmZ_DtoS 21393U, // FCVTZU_ZPmZ_HtoD 2181591953U, // FCVTZU_ZPmZ_HtoH 37777U, // FCVTZU_ZPmZ_HtoS 21393U, // FCVTZU_ZPmZ_StoD 37777U, // FCVTZU_ZPmZ_StoS 100717457U, // FCVTZUd 100717457U, // FCVTZUh 100717457U, // FCVTZUs 2248201105U, // FCVTZUv1f16 2248201105U, // FCVTZUv1i32 2248201105U, // FCVTZUv1i64 68727697U, // FCVTZUv2f32 2216735633U, // FCVTZUv2f64 2216211345U, // FCVTZUv2i32_shift 2216735633U, // FCVTZUv2i64_shift 69776273U, // FCVTZUv4f16 2217784209U, // FCVTZUv4f32 69776273U, // FCVTZUv4i16_shift 70300561U, // FCVTZUv4i32_shift 70824849U, // FCVTZUv8f16 2218308497U, // FCVTZUv8i16_shift 2181591900U, // FCVT_ZPmZ_DtoH 37724U, // FCVT_ZPmZ_DtoS 21340U, // FCVT_ZPmZ_HtoD 37724U, // FCVT_ZPmZ_HtoS 21340U, // FCVT_ZPmZ_StoD 2181591900U, // FCVT_ZPmZ_StoH 100717497U, // FDIVDrr 100717497U, // FDIVHrr 302010787U, // FDIVR_ZPmZ_D 2186310051U, // FDIVR_ZPmZ_H 302027171U, // FDIVR_ZPmZ_S 100717497U, // FDIVSrr 302011321U, // FDIV_ZPmZ_D 2186310585U, // FDIV_ZPmZ_H 302027705U, // FDIV_ZPmZ_S 2216211385U, // FDIVv2f32 2216735673U, // FDIVv2f64 69776313U, // FDIVv4f16 70300601U, // FDIVv4f32 2218308537U, // FDIVv8f16 838881376U, // FDUP_ZI_D 9465952U, // FDUP_ZI_H 838897760U, // FDUP_ZI_S 2348827371U, // FEXPA_ZZ_D 608723691U, // FEXPA_ZZ_H 2415952619U, // FEXPA_ZZ_S 2248200909U, // FJCVTZS 100714511U, // FMADDDrrr 100714511U, // FMADDHrrr 100714511U, // FMADDSrrr 302008208U, // FMAD_ZPmZZ_D 2186307472U, // FMAD_ZPmZZ_H 302024592U, // FMAD_ZPmZZ_S 100717911U, // FMAXDrr 100717911U, // FMAXHrr 100716219U, // FMAXNMDrr 100716219U, // FMAXNMHrr 2216210455U, // FMAXNMPv2f32 2216734743U, // FMAXNMPv2f64 2214645783U, // FMAXNMPv2i16p 67162135U, // FMAXNMPv2i32p 2214645783U, // FMAXNMPv2i64p 69775383U, // FMAXNMPv4f16 70299671U, // FMAXNMPv4f32 2218307607U, // FMAXNMPv8f16 100716219U, // FMAXNMSrr 302044132U, // FMAXNMV_VPZ_D 302044132U, // FMAXNMV_VPZ_H 302044132U, // FMAXNMV_VPZ_S 67163108U, // FMAXNMVv4i16v 2214646756U, // FMAXNMVv4i32v 67163108U, // FMAXNMVv8i16v 302010043U, // FMAXNM_ZPmI_D 2186309307U, // FMAXNM_ZPmI_H 302026427U, // FMAXNM_ZPmI_S 302010043U, // FMAXNM_ZPmZ_D 2186309307U, // FMAXNM_ZPmZ_H 302026427U, // FMAXNM_ZPmZ_S 2216210107U, // FMAXNMv2f32 2216734395U, // FMAXNMv2f64 69775035U, // FMAXNMv4f16 70299323U, // FMAXNMv4f32 2218307259U, // FMAXNMv8f16 2216210546U, // FMAXPv2f32 2216734834U, // FMAXPv2f64 2214645874U, // FMAXPv2i16p 67162226U, // FMAXPv2i32p 2214645874U, // FMAXPv2i64p 69775474U, // FMAXPv4f16 70299762U, // FMAXPv4f32 2218307698U, // FMAXPv8f16 100717911U, // FMAXSrr 302044193U, // FMAXV_VPZ_D 302044193U, // FMAXV_VPZ_H 302044193U, // FMAXV_VPZ_S 67163169U, // FMAXVv4i16v 2214646817U, // FMAXVv4i32v 67163169U, // FMAXVv8i16v 302011735U, // FMAX_ZPmI_D 2186310999U, // FMAX_ZPmI_H 302028119U, // FMAX_ZPmI_S 302011735U, // FMAX_ZPmZ_D 2186310999U, // FMAX_ZPmZ_H 302028119U, // FMAX_ZPmZ_S 2216211799U, // FMAXv2f32 2216736087U, // FMAXv2f64 69776727U, // FMAXv4f16 70301015U, // FMAXv4f32 2218308951U, // FMAXv8f16 100716264U, // FMINDrr 100716264U, // FMINHrr 100716211U, // FMINNMDrr 100716211U, // FMINNMHrr 2216210446U, // FMINNMPv2f32 2216734734U, // FMINNMPv2f64 2214645774U, // FMINNMPv2i16p 67162126U, // FMINNMPv2i32p 2214645774U, // FMINNMPv2i64p 69775374U, // FMINNMPv4f16 70299662U, // FMINNMPv4f32 2218307598U, // FMINNMPv8f16 100716211U, // FMINNMSrr 302044123U, // FMINNMV_VPZ_D 302044123U, // FMINNMV_VPZ_H 302044123U, // FMINNMV_VPZ_S 67163099U, // FMINNMVv4i16v 2214646747U, // FMINNMVv4i32v 67163099U, // FMINNMVv8i16v 302010035U, // FMINNM_ZPmI_D 2186309299U, // FMINNM_ZPmI_H 302026419U, // FMINNM_ZPmI_S 302010035U, // FMINNM_ZPmZ_D 2186309299U, // FMINNM_ZPmZ_H 302026419U, // FMINNM_ZPmZ_S 2216210099U, // FMINNMv2f32 2216734387U, // FMINNMv2f64 69775027U, // FMINNMv4f16 70299315U, // FMINNMv4f32 2218307251U, // FMINNMv8f16 2216210470U, // FMINPv2f32 2216734758U, // FMINPv2f64 2214645798U, // FMINPv2i16p 67162150U, // FMINPv2i32p 2214645798U, // FMINPv2i64p 69775398U, // FMINPv4f16 70299686U, // FMINPv4f32 2218307622U, // FMINPv8f16 100716264U, // FMINSrr 302044141U, // FMINV_VPZ_D 302044141U, // FMINV_VPZ_H 302044141U, // FMINV_VPZ_S 67163117U, // FMINVv4i16v 2214646765U, // FMINVv4i32v 67163117U, // FMINVv8i16v 302010088U, // FMIN_ZPmI_D 2186309352U, // FMIN_ZPmI_H 302026472U, // FMIN_ZPmI_S 302010088U, // FMIN_ZPmZ_D 2186309352U, // FMIN_ZPmZ_H 302026472U, // FMIN_ZPmZ_S 2216210152U, // FMINv2f32 2216734440U, // FMINv2f64 69775080U, // FMINv4f16 70299368U, // FMINv4f32 2218307304U, // FMINv8f16 302006968U, // FMLA_ZPmZZ_D 2186306232U, // FMLA_ZPmZZ_H 302023352U, // FMLA_ZPmZZ_S 3019915960U, // FMLA_ZZZI_D 612393656U, // FMLA_ZZZI_H 2952823480U, // FMLA_ZZZI_S 369189560U, // FMLAv1i16_indexed 369189560U, // FMLAv1i32_indexed 369189560U, // FMLAv1i64_indexed 2283332280U, // FMLAv2f32 2283856568U, // FMLAv2f64 2283332280U, // FMLAv2i32_indexed 2283856568U, // FMLAv2i64_indexed 136897208U, // FMLAv4f16 137421496U, // FMLAv4f32 136897208U, // FMLAv4i16_indexed 137421496U, // FMLAv4i32_indexed 2285429432U, // FMLAv8f16 2285429432U, // FMLAv8i16_indexed 302010962U, // FMLS_ZPmZZ_D 2186310226U, // FMLS_ZPmZZ_H 302027346U, // FMLS_ZPmZZ_S 3019919954U, // FMLS_ZZZI_D 612397650U, // FMLS_ZZZI_H 2952827474U, // FMLS_ZZZI_S 369193554U, // FMLSv1i16_indexed 369193554U, // FMLSv1i32_indexed 369193554U, // FMLSv1i64_indexed 2283336274U, // FMLSv2f32 2283860562U, // FMLSv2f64 2283336274U, // FMLSv2i32_indexed 2283860562U, // FMLSv2i64_indexed 136901202U, // FMLSv4f16 137425490U, // FMLSv4f32 136901202U, // FMLSv4i16_indexed 137425490U, // FMLSv4i32_indexed 2285433426U, // FMLSv8f16 2285433426U, // FMLSv8i16_indexed 0U, // FMOVD0 67163145U, // FMOVDXHighr 2248201225U, // FMOVDXr 838915081U, // FMOVDi 2248201225U, // FMOVDr 0U, // FMOVH0 2248201225U, // FMOVHWr 2248201225U, // FMOVHXr 838915081U, // FMOVHi 2248201225U, // FMOVHr 0U, // FMOVS0 2248201225U, // FMOVSWr 838915081U, // FMOVSi 2248201225U, // FMOVSr 2248201225U, // FMOVWHr 2248201225U, // FMOVWSr 2258154505U, // FMOVXDHighr 2248201225U, // FMOVXDr 2248201225U, // FMOVXHr 840479753U, // FMOVv2f32_ns 841004041U, // FMOVv2f64_ns 841528329U, // FMOVv4f16_ns 842052617U, // FMOVv4f32_ns 842576905U, // FMOVv8f16_ns 302007876U, // FMSB_ZPmZZ_D 2186307140U, // FMSB_ZPmZZ_H 302024260U, // FMSB_ZPmZZ_S 100714165U, // FMSUBDrrr 100714165U, // FMSUBHrrr 100714165U, // FMSUBSrrr 100716128U, // FMULDrr 100716128U, // FMULHrr 100716128U, // FMULSrr 100717970U, // FMULX16 100717970U, // FMULX32 100717970U, // FMULX64 302011794U, // FMULX_ZPmZ_D 2186311058U, // FMULX_ZPmZ_H 302028178U, // FMULX_ZPmZ_S 100717970U, // FMULXv1i16_indexed 100717970U, // FMULXv1i32_indexed 100717970U, // FMULXv1i64_indexed 2216211858U, // FMULXv2f32 2216736146U, // FMULXv2f64 2216211858U, // FMULXv2i32_indexed 2216736146U, // FMULXv2i64_indexed 69776786U, // FMULXv4f16 70301074U, // FMULXv4f32 69776786U, // FMULXv4i16_indexed 70301074U, // FMULXv4i32_indexed 2218309010U, // FMULXv8f16 2218309010U, // FMULXv8i16_indexed 302009952U, // FMUL_ZPmI_D 2186309216U, // FMUL_ZPmI_H 302026336U, // FMUL_ZPmI_S 302009952U, // FMUL_ZPmZ_D 2186309216U, // FMUL_ZPmZ_H 302026336U, // FMUL_ZPmZ_S 201346656U, // FMUL_ZZZI_D 2387111520U, // FMUL_ZZZI_H 268471904U, // FMUL_ZZZI_S 201346656U, // FMUL_ZZZ_D 2387111520U, // FMUL_ZZZ_H 268471904U, // FMUL_ZZZ_S 100716128U, // FMULv1i16_indexed 100716128U, // FMULv1i32_indexed 100716128U, // FMULv1i64_indexed 2216210016U, // FMULv2f32 2216734304U, // FMULv2f64 2216210016U, // FMULv2i32_indexed 2216734304U, // FMULv2i64_indexed 69774944U, // FMULv4f16 70299232U, // FMULv4f32 69774944U, // FMULv4i16_indexed 70299232U, // FMULv4i32_indexed 2218307168U, // FMULv8f16 2218307168U, // FMULv8i16_indexed 2248198419U, // FNEGDr 2248198419U, // FNEGHr 2248198419U, // FNEGSr 18707U, // FNEG_ZPmZ_D 2181589267U, // FNEG_ZPmZ_H 35091U, // FNEG_ZPmZ_S 68725011U, // FNEGv2f32 2216732947U, // FNEGv2f64 69773587U, // FNEGv4f16 2217781523U, // FNEGv4f32 70822163U, // FNEGv8f16 100714518U, // FNMADDDrrr 100714518U, // FNMADDHrrr 100714518U, // FNMADDSrrr 302008214U, // FNMAD_ZPmZZ_D 2186307478U, // FNMAD_ZPmZZ_H 302024598U, // FNMAD_ZPmZZ_S 302006974U, // FNMLA_ZPmZZ_D 2186306238U, // FNMLA_ZPmZZ_H 302023358U, // FNMLA_ZPmZZ_S 302010968U, // FNMLS_ZPmZZ_D 2186310232U, // FNMLS_ZPmZZ_H 302027352U, // FNMLS_ZPmZZ_S 302007882U, // FNMSB_ZPmZZ_D 2186307146U, // FNMSB_ZPmZZ_H 302024266U, // FNMSB_ZPmZZ_S 100714172U, // FNMSUBDrrr 100714172U, // FNMSUBHrrr 100714172U, // FNMSUBSrrr 100716134U, // FNMULDrr 100716134U, // FNMULHrr 100716134U, // FNMULSrr 2348828852U, // FRECPE_ZZ_D 608725172U, // FRECPE_ZZ_H 2415954100U, // FRECPE_ZZ_S 2248198324U, // FRECPEv1f16 2248198324U, // FRECPEv1i32 2248198324U, // FRECPEv1i64 68724916U, // FRECPEv2f32 2216732852U, // FRECPEv2f64 69773492U, // FRECPEv4f16 2217781428U, // FRECPEv4f32 70822068U, // FRECPEv8f16 100717192U, // FRECPS16 100717192U, // FRECPS32 100717192U, // FRECPS64 201347720U, // FRECPS_ZZZ_D 2387112584U, // FRECPS_ZZZ_H 268472968U, // FRECPS_ZZZ_S 2216211080U, // FRECPSv2f32 2216735368U, // FRECPSv2f64 69776008U, // FRECPSv4f16 70300296U, // FRECPSv4f32 2218308232U, // FRECPSv8f16 21913U, // FRECPX_ZPmZ_D 2181592473U, // FRECPX_ZPmZ_H 38297U, // FRECPX_ZPmZ_S 2248201625U, // FRECPXv1f16 2248201625U, // FRECPXv1i32 2248201625U, // FRECPXv1i64 2248196906U, // FRINTADr 2248196906U, // FRINTAHr 2248196906U, // FRINTASr 17194U, // FRINTA_ZPmZ_D 2181587754U, // FRINTA_ZPmZ_H 33578U, // FRINTA_ZPmZ_S 68723498U, // FRINTAv2f32 2216731434U, // FRINTAv2f64 69772074U, // FRINTAv4f16 2217780010U, // FRINTAv4f32 70820650U, // FRINTAv8f16 2248199305U, // FRINTIDr 2248199305U, // FRINTIHr 2248199305U, // FRINTISr 19593U, // FRINTI_ZPmZ_D 2181590153U, // FRINTI_ZPmZ_H 35977U, // FRINTI_ZPmZ_S 68725897U, // FRINTIv2f32 2216733833U, // FRINTIv2f64 69774473U, // FRINTIv4f16 2217782409U, // FRINTIv4f32 70823049U, // FRINTIv8f16 2248199881U, // FRINTMDr 2248199881U, // FRINTMHr 2248199881U, // FRINTMSr 20169U, // FRINTM_ZPmZ_D 2181590729U, // FRINTM_ZPmZ_H 36553U, // FRINTM_ZPmZ_S 68726473U, // FRINTMv2f32 2216734409U, // FRINTMv2f64 69775049U, // FRINTMv4f16 2217782985U, // FRINTMv4f32 70823625U, // FRINTMv8f16 2248199990U, // FRINTNDr 2248199990U, // FRINTNHr 2248199990U, // FRINTNSr 20278U, // FRINTN_ZPmZ_D 2181590838U, // FRINTN_ZPmZ_H 36662U, // FRINTN_ZPmZ_S 68726582U, // FRINTNv2f32 2216734518U, // FRINTNv2f64 69775158U, // FRINTNv4f16 2217783094U, // FRINTNv4f32 70823734U, // FRINTNv8f16 2248200275U, // FRINTPDr 2248200275U, // FRINTPHr 2248200275U, // FRINTPSr 20563U, // FRINTP_ZPmZ_D 2181591123U, // FRINTP_ZPmZ_H 36947U, // FRINTP_ZPmZ_S 68726867U, // FRINTPv2f32 2216734803U, // FRINTPv2f64 69775443U, // FRINTPv4f16 2217783379U, // FRINTPv4f32 70824019U, // FRINTPv8f16 2248201633U, // FRINTXDr 2248201633U, // FRINTXHr 2248201633U, // FRINTXSr 21921U, // FRINTX_ZPmZ_D 2181592481U, // FRINTX_ZPmZ_H 38305U, // FRINTX_ZPmZ_S 68728225U, // FRINTXv2f32 2216736161U, // FRINTXv2f64 69776801U, // FRINTXv4f16 2217784737U, // FRINTXv4f32 70825377U, // FRINTXv8f16 2248201713U, // FRINTZDr 2248201713U, // FRINTZHr 2248201713U, // FRINTZSr 22001U, // FRINTZ_ZPmZ_D 2181592561U, // FRINTZ_ZPmZ_H 38385U, // FRINTZ_ZPmZ_S 68728305U, // FRINTZv2f32 2216736241U, // FRINTZv2f64 69776881U, // FRINTZv4f16 2217784817U, // FRINTZv4f32 70825457U, // FRINTZv8f16 2348828897U, // FRSQRTE_ZZ_D 608725217U, // FRSQRTE_ZZ_H 2415954145U, // FRSQRTE_ZZ_S 2248198369U, // FRSQRTEv1f16 2248198369U, // FRSQRTEv1i32 2248198369U, // FRSQRTEv1i64 68724961U, // FRSQRTEv2f32 2216732897U, // FRSQRTEv2f64 69773537U, // FRSQRTEv4f16 2217781473U, // FRSQRTEv4f32 70822113U, // FRSQRTEv8f16 100717239U, // FRSQRTS16 100717239U, // FRSQRTS32 100717239U, // FRSQRTS64 201347767U, // FRSQRTS_ZZZ_D 2387112631U, // FRSQRTS_ZZZ_H 268473015U, // FRSQRTS_ZZZ_S 2216211127U, // FRSQRTSv2f32 2216735415U, // FRSQRTSv2f64 69776055U, // FRSQRTSv4f16 70300343U, // FRSQRTSv4f32 2218308279U, // FRSQRTSv8f16 302008446U, // FSCALE_ZPmZ_D 2186307710U, // FSCALE_ZPmZ_H 302024830U, // FSCALE_ZPmZ_S 2248201023U, // FSQRTDr 2248201023U, // FSQRTHr 2248201023U, // FSQRTSr 21311U, // FSQRT_ZPmZ_D 2181591871U, // FSQRT_ZPmZ_H 37695U, // FSQRT_ZPmZ_S 68727615U, // FSQRTv2f32 2216735551U, // FSQRTv2f64 69776191U, // FSQRTv4f16 2217784127U, // FSQRTv4f32 70824767U, // FSQRTv8f16 100714145U, // FSUBDrr 100714145U, // FSUBHrr 302010587U, // FSUBR_ZPmI_D 2186309851U, // FSUBR_ZPmI_H 302026971U, // FSUBR_ZPmI_S 302010587U, // FSUBR_ZPmZ_D 2186309851U, // FSUBR_ZPmZ_H 302026971U, // FSUBR_ZPmZ_S 100714145U, // FSUBSrr 302007969U, // FSUB_ZPmI_D 2186307233U, // FSUB_ZPmI_H 302024353U, // FSUB_ZPmI_S 302007969U, // FSUB_ZPmZ_D 2186307233U, // FSUB_ZPmZ_H 302024353U, // FSUB_ZPmZ_S 201344673U, // FSUB_ZZZ_D 2387109537U, // FSUB_ZZZ_H 268469921U, // FSUB_ZZZ_S 2216208033U, // FSUBv2f32 2216732321U, // FSUBv2f64 69772961U, // FSUBv4f16 70297249U, // FSUBv4f32 2218305185U, // FSUBv8f16 201344925U, // FTMAD_ZZI_D 2387109789U, // FTMAD_ZZI_H 268470173U, // FTMAD_ZZI_S 201346675U, // FTSMUL_ZZZ_D 2387111539U, // FTSMUL_ZZZ_H 268471923U, // FTSMUL_ZZZ_S 201346439U, // FTSSEL_ZZZ_D 2387111303U, // FTSSEL_ZZZ_H 268471687U, // FTSSEL_ZZZ_S 883032940U, // GLD1B_D_IMM_REAL 379716460U, // GLD1B_D_REAL 379716460U, // GLD1B_D_SXTW_REAL 379716460U, // GLD1B_D_UXTW_REAL 815932268U, // GLD1B_S_IMM_REAL 379724652U, // GLD1B_S_SXTW_REAL 379724652U, // GLD1B_S_UXTW_REAL 883033920U, // GLD1D_IMM_REAL 379717440U, // GLD1D_REAL 379717440U, // GLD1D_SCALED_REAL 379717440U, // GLD1D_SXTW_REAL 379717440U, // GLD1D_SXTW_SCALED_REAL 379717440U, // GLD1D_UXTW_REAL 379717440U, // GLD1D_UXTW_SCALED_REAL 3030518062U, // GLD1H_D_IMM_REAL 379717934U, // GLD1H_D_REAL 379717934U, // GLD1H_D_SCALED_REAL 379717934U, // GLD1H_D_SXTW_REAL 379717934U, // GLD1H_D_SXTW_SCALED_REAL 379717934U, // GLD1H_D_UXTW_REAL 379717934U, // GLD1H_D_UXTW_SCALED_REAL 2963417390U, // GLD1H_S_IMM_REAL 379726126U, // GLD1H_S_SXTW_REAL 379726126U, // GLD1H_S_SXTW_SCALED_REAL 379726126U, // GLD1H_S_UXTW_REAL 379726126U, // GLD1H_S_UXTW_SCALED_REAL 883033627U, // GLD1SB_D_IMM_REAL 379717147U, // GLD1SB_D_REAL 379717147U, // GLD1SB_D_SXTW_REAL 379717147U, // GLD1SB_D_UXTW_REAL 815932955U, // GLD1SB_S_IMM_REAL 379725339U, // GLD1SB_S_SXTW_REAL 379725339U, // GLD1SB_S_UXTW_REAL 3030518726U, // GLD1SH_D_IMM_REAL 379718598U, // GLD1SH_D_REAL 379718598U, // GLD1SH_D_SCALED_REAL 379718598U, // GLD1SH_D_SXTW_REAL 379718598U, // GLD1SH_D_SXTW_SCALED_REAL 379718598U, // GLD1SH_D_UXTW_REAL 379718598U, // GLD1SH_D_UXTW_SCALED_REAL 2963418054U, // GLD1SH_S_IMM_REAL 379726790U, // GLD1SH_S_SXTW_REAL 379726790U, // GLD1SH_S_SXTW_SCALED_REAL 379726790U, // GLD1SH_S_UXTW_REAL 379726790U, // GLD1SH_S_UXTW_SCALED_REAL 883037416U, // GLD1SW_D_IMM_REAL 379720936U, // GLD1SW_D_REAL 379720936U, // GLD1SW_D_SCALED_REAL 379720936U, // GLD1SW_D_SXTW_REAL 379720936U, // GLD1SW_D_SXTW_SCALED_REAL 379720936U, // GLD1SW_D_UXTW_REAL 379720936U, // GLD1SW_D_UXTW_SCALED_REAL 883037238U, // GLD1W_D_IMM_REAL 379720758U, // GLD1W_D_REAL 379720758U, // GLD1W_D_SCALED_REAL 379720758U, // GLD1W_D_SXTW_REAL 379720758U, // GLD1W_D_SXTW_SCALED_REAL 379720758U, // GLD1W_D_UXTW_REAL 379720758U, // GLD1W_D_UXTW_SCALED_REAL 815936566U, // GLD1W_IMM_REAL 379728950U, // GLD1W_SXTW_REAL 379728950U, // GLD1W_SXTW_SCALED_REAL 379728950U, // GLD1W_UXTW_REAL 379728950U, // GLD1W_UXTW_SCALED_REAL 883032946U, // GLDFF1B_D_IMM_REAL 379716466U, // GLDFF1B_D_REAL 379716466U, // GLDFF1B_D_SXTW_REAL 379716466U, // GLDFF1B_D_UXTW_REAL 815932274U, // GLDFF1B_S_IMM_REAL 379724658U, // GLDFF1B_S_SXTW_REAL 379724658U, // GLDFF1B_S_UXTW_REAL 883033926U, // GLDFF1D_IMM_REAL 379717446U, // GLDFF1D_REAL 379717446U, // GLDFF1D_SCALED_REAL 379717446U, // GLDFF1D_SXTW_REAL 379717446U, // GLDFF1D_SXTW_SCALED_REAL 379717446U, // GLDFF1D_UXTW_REAL 379717446U, // GLDFF1D_UXTW_SCALED_REAL 3030518068U, // GLDFF1H_D_IMM_REAL 379717940U, // GLDFF1H_D_REAL 379717940U, // GLDFF1H_D_SCALED_REAL 379717940U, // GLDFF1H_D_SXTW_REAL 379717940U, // GLDFF1H_D_SXTW_SCALED_REAL 379717940U, // GLDFF1H_D_UXTW_REAL 379717940U, // GLDFF1H_D_UXTW_SCALED_REAL 2963417396U, // GLDFF1H_S_IMM_REAL 379726132U, // GLDFF1H_S_SXTW_REAL 379726132U, // GLDFF1H_S_SXTW_SCALED_REAL 379726132U, // GLDFF1H_S_UXTW_REAL 379726132U, // GLDFF1H_S_UXTW_SCALED_REAL 883033634U, // GLDFF1SB_D_IMM_REAL 379717154U, // GLDFF1SB_D_REAL 379717154U, // GLDFF1SB_D_SXTW_REAL 379717154U, // GLDFF1SB_D_UXTW_REAL 815932962U, // GLDFF1SB_S_IMM_REAL 379725346U, // GLDFF1SB_S_SXTW_REAL 379725346U, // GLDFF1SB_S_UXTW_REAL 3030518733U, // GLDFF1SH_D_IMM_REAL 379718605U, // GLDFF1SH_D_REAL 379718605U, // GLDFF1SH_D_SCALED_REAL 379718605U, // GLDFF1SH_D_SXTW_REAL 379718605U, // GLDFF1SH_D_SXTW_SCALED_REAL 379718605U, // GLDFF1SH_D_UXTW_REAL 379718605U, // GLDFF1SH_D_UXTW_SCALED_REAL 2963418061U, // GLDFF1SH_S_IMM_REAL 379726797U, // GLDFF1SH_S_SXTW_REAL 379726797U, // GLDFF1SH_S_SXTW_SCALED_REAL 379726797U, // GLDFF1SH_S_UXTW_REAL 379726797U, // GLDFF1SH_S_UXTW_SCALED_REAL 883037423U, // GLDFF1SW_D_IMM_REAL 379720943U, // GLDFF1SW_D_REAL 379720943U, // GLDFF1SW_D_SCALED_REAL 379720943U, // GLDFF1SW_D_SXTW_REAL 379720943U, // GLDFF1SW_D_SXTW_SCALED_REAL 379720943U, // GLDFF1SW_D_UXTW_REAL 379720943U, // GLDFF1SW_D_UXTW_SCALED_REAL 883037244U, // GLDFF1W_D_IMM_REAL 379720764U, // GLDFF1W_D_REAL 379720764U, // GLDFF1W_D_SCALED_REAL 379720764U, // GLDFF1W_D_SXTW_REAL 379720764U, // GLDFF1W_D_SXTW_SCALED_REAL 379720764U, // GLDFF1W_D_UXTW_REAL 379720764U, // GLDFF1W_D_UXTW_SCALED_REAL 815936572U, // GLDFF1W_IMM_REAL 379728956U, // GLDFF1W_SXTW_REAL 379728956U, // GLDFF1W_SXTW_SCALED_REAL 379728956U, // GLDFF1W_UXTW_REAL 379728956U, // GLDFF1W_UXTW_SCALED_REAL 152359U, // HINT 78607U, // HLT 75574U, // HVC 536921183U, // INCB_XPiI 536922063U, // INCD_XPiI 536889295U, // INCD_ZPiI 536922647U, // INCH_XPiI 6842903U, // INCH_ZPiI 2315308999U, // INCP_XP_B 2348863431U, // INCP_XP_D 2717962183U, // INCP_XP_H 2415972295U, // INCP_XP_S 2147504071U, // INCP_ZP_D 604532679U, // INCP_ZP_H 2147520455U, // INCP_ZP_S 536925367U, // INCW_XPiI 536908983U, // INCW_ZPiI 100676987U, // INDEX_II_B 100685179U, // INDEX_II_D 242775419U, // INDEX_II_H 100701563U, // INDEX_II_S 100676987U, // INDEX_IR_B 100685179U, // INDEX_IR_D 242775419U, // INDEX_IR_H 100701563U, // INDEX_IR_S 100676987U, // INDEX_RI_B 100685179U, // INDEX_RI_D 242775419U, // INDEX_RI_H 100701563U, // INDEX_RI_S 100676987U, // INDEX_RR_B 100685179U, // INDEX_RR_D 242775419U, // INDEX_RR_H 100701563U, // INDEX_RR_S 2516595051U, // INSR_ZR_B 2516603243U, // INSR_ZR_D 615018859U, // INSR_ZR_H 2516619627U, // INSR_ZR_S 2516595051U, // INSR_ZV_B 2516603243U, // INSR_ZV_D 615018859U, // INSR_ZV_H 2516619627U, // INSR_ZV_S 3065049710U, // INSvi16gpr 951120494U, // INSvi16lane 3065573998U, // INSvi32gpr 3099128430U, // INSvi32lane 3063476846U, // INSvi64gpr 949547630U, // INSvi64lane 3066098286U, // INSvi8gpr 3099652718U, // INSvi8lane 116287U, // ISB 302039859U, // LASTA_RPZ_B 302039859U, // LASTA_RPZ_D 302039859U, // LASTA_RPZ_H 302039859U, // LASTA_RPZ_S 302039859U, // LASTA_VPZ_B 302039859U, // LASTA_VPZ_D 302039859U, // LASTA_VPZ_H 302039859U, // LASTA_VPZ_S 302040718U, // LASTB_RPZ_B 302040718U, // LASTB_RPZ_D 302040718U, // LASTB_RPZ_H 302040718U, // LASTB_RPZ_S 302040718U, // LASTB_VPZ_B 302040718U, // LASTB_VPZ_D 302040718U, // LASTB_VPZ_H 302040718U, // LASTB_VPZ_S 379741036U, // LD1B 379716460U, // LD1B_D 379716460U, // LD1B_D_IMM_REAL 379749228U, // LD1B_H 379749228U, // LD1B_H_IMM_REAL 379741036U, // LD1B_IMM_REAL 379724652U, // LD1B_S 379724652U, // LD1B_S_IMM_REAL 379717440U, // LD1D 379717440U, // LD1D_IMM_REAL 172064U, // LD1Fourv16b 13287456U, // LD1Fourv16b_POST 188448U, // LD1Fourv1d 13828128U, // LD1Fourv1d_POST 204832U, // LD1Fourv2d 13320224U, // LD1Fourv2d_POST 221216U, // LD1Fourv2s 13860896U, // LD1Fourv2s_POST 237600U, // LD1Fourv4h 13877280U, // LD1Fourv4h_POST 253984U, // LD1Fourv4s 13369376U, // LD1Fourv4s_POST 270368U, // LD1Fourv8b 13910048U, // LD1Fourv8b_POST 286752U, // LD1Fourv8h 13402144U, // LD1Fourv8h_POST 379750702U, // LD1H 379717934U, // LD1H_D 379717934U, // LD1H_D_IMM_REAL 379750702U, // LD1H_IMM_REAL 379726126U, // LD1H_S 379726126U, // LD1H_S_IMM_REAL 172064U, // LD1Onev16b 14336032U, // LD1Onev16b_POST 188448U, // LD1Onev1d 14876704U, // LD1Onev1d_POST 204832U, // LD1Onev2d 14368800U, // LD1Onev2d_POST 221216U, // LD1Onev2s 14909472U, // LD1Onev2s_POST 237600U, // LD1Onev4h 14925856U, // LD1Onev4h_POST 253984U, // LD1Onev4s 14417952U, // LD1Onev4s_POST 270368U, // LD1Onev8b 14958624U, // LD1Onev8b_POST 286752U, // LD1Onev8h 14450720U, // LD1Onev8h_POST 379716999U, // LD1RB_D_IMM 379749767U, // LD1RB_H_IMM 379741575U, // LD1RB_IMM 379725191U, // LD1RB_S_IMM 379717698U, // LD1RD_IMM 379718450U, // LD1RH_D_IMM 379751218U, // LD1RH_IMM 379726642U, // LD1RH_S_IMM 379741567U, // LD1RQ_B 379741567U, // LD1RQ_B_IMM 379717690U, // LD1RQ_D 379717690U, // LD1RQ_D_IMM 379751210U, // LD1RQ_H 379751210U, // LD1RQ_H_IMM 379729113U, // LD1RQ_W 379729113U, // LD1RQ_W_IMM 379717201U, // LD1RSB_D_IMM 379749969U, // LD1RSB_H_IMM 379725393U, // LD1RSB_S_IMM 379718639U, // LD1RSH_D_IMM 379726831U, // LD1RSH_S_IMM 379720968U, // LD1RSW_IMM 379720929U, // LD1RW_D_IMM 379729121U, // LD1RW_IMM 176305U, // LD1Rv16b 15388849U, // LD1Rv16b_POST 192689U, // LD1Rv1d 14880945U, // LD1Rv1d_POST 209073U, // LD1Rv2d 14897329U, // LD1Rv2d_POST 225457U, // LD1Rv2s 15962289U, // LD1Rv2s_POST 241841U, // LD1Rv4h 16502961U, // LD1Rv4h_POST 258225U, // LD1Rv4s 15995057U, // LD1Rv4s_POST 274609U, // LD1Rv8b 15487153U, // LD1Rv8b_POST 290993U, // LD1Rv8h 16552113U, // LD1Rv8h_POST 379717147U, // LD1SB_D 379717147U, // LD1SB_D_IMM_REAL 379749915U, // LD1SB_H 379749915U, // LD1SB_H_IMM_REAL 379725339U, // LD1SB_S 379725339U, // LD1SB_S_IMM_REAL 379718598U, // LD1SH_D 379718598U, // LD1SH_D_IMM_REAL 379726790U, // LD1SH_S 379726790U, // LD1SH_S_IMM_REAL 379720936U, // LD1SW_D 379720936U, // LD1SW_D_IMM_REAL 172064U, // LD1Threev16b 16957472U, // LD1Threev16b_POST 188448U, // LD1Threev1d 17498144U, // LD1Threev1d_POST 204832U, // LD1Threev2d 16990240U, // LD1Threev2d_POST 221216U, // LD1Threev2s 17530912U, // LD1Threev2s_POST 237600U, // LD1Threev4h 17547296U, // LD1Threev4h_POST 253984U, // LD1Threev4s 17039392U, // LD1Threev4s_POST 270368U, // LD1Threev8b 17580064U, // LD1Threev8b_POST 286752U, // LD1Threev8h 17072160U, // LD1Threev8h_POST 172064U, // LD1Twov16b 13811744U, // LD1Twov16b_POST 188448U, // LD1Twov1d 14352416U, // LD1Twov1d_POST 204832U, // LD1Twov2d 13844512U, // LD1Twov2d_POST 221216U, // LD1Twov2s 14385184U, // LD1Twov2s_POST 237600U, // LD1Twov4h 14401568U, // LD1Twov4h_POST 253984U, // LD1Twov4s 13893664U, // LD1Twov4s_POST 270368U, // LD1Twov8b 14434336U, // LD1Twov8b_POST 286752U, // LD1Twov8h 13926432U, // LD1Twov8h_POST 379728950U, // LD1W 379720758U, // LD1W_D 379720758U, // LD1W_D_IMM_REAL 379728950U, // LD1W_IMM_REAL 18128928U, // LD1i16 18661408U, // LD1i16_POST 18145312U, // LD1i32 19202080U, // LD1i32_POST 18161696U, // LD1i64 19742752U, // LD1i64_POST 18178080U, // LD1i8 20283424U, // LD1i8_POST 379741097U, // LD2B 379741097U, // LD2B_IMM 379717484U, // LD2D 379717484U, // LD2D_IMM 379750763U, // LD2H 379750763U, // LD2H_IMM 176311U, // LD2Rv16b 16437431U, // LD2Rv16b_POST 192695U, // LD2Rv1d 14356663U, // LD2Rv1d_POST 209079U, // LD2Rv2d 14373047U, // LD2Rv2d_POST 225463U, // LD2Rv2s 14913719U, // LD2Rv2s_POST 241847U, // LD2Rv4h 15978679U, // LD2Rv4h_POST 258231U, // LD2Rv4s 14946487U, // LD2Rv4s_POST 274615U, // LD2Rv8b 16535735U, // LD2Rv8b_POST 290999U, // LD2Rv8h 16027831U, // LD2Rv8h_POST 172162U, // LD2Twov16b 13811842U, // LD2Twov16b_POST 204930U, // LD2Twov2d 13844610U, // LD2Twov2d_POST 221314U, // LD2Twov2s 14385282U, // LD2Twov2s_POST 237698U, // LD2Twov4h 14401666U, // LD2Twov4h_POST 254082U, // LD2Twov4s 13893762U, // LD2Twov4s_POST 270466U, // LD2Twov8b 14434434U, // LD2Twov8b_POST 286850U, // LD2Twov8h 13926530U, // LD2Twov8h_POST 379729002U, // LD2W 379729002U, // LD2W_IMM 18129026U, // LD2i16 19185794U, // LD2i16_POST 18145410U, // LD2i32 19726466U, // LD2i32_POST 18161794U, // LD2i64 20791426U, // LD2i64_POST 18178178U, // LD2i8 18710658U, // LD2i8_POST 379741118U, // LD3B 379741118U, // LD3B_IMM 379717496U, // LD3D 379717496U, // LD3D_IMM 379750775U, // LD3H 379750775U, // LD3H_IMM 176317U, // LD3Rv16b 21156029U, // LD3Rv16b_POST 192701U, // LD3Rv1d 17502397U, // LD3Rv1d_POST 209085U, // LD3Rv2d 17518781U, // LD3Rv2d_POST 225469U, // LD3Rv2s 21729469U, // LD3Rv2s_POST 241853U, // LD3Rv4h 22270141U, // LD3Rv4h_POST 258237U, // LD3Rv4s 21762237U, // LD3Rv4s_POST 274621U, // LD3Rv8b 21254333U, // LD3Rv8b_POST 291005U, // LD3Rv8h 22319293U, // LD3Rv8h_POST 172553U, // LD3Threev16b 16957961U, // LD3Threev16b_POST 205321U, // LD3Threev2d 16990729U, // LD3Threev2d_POST 221705U, // LD3Threev2s 17531401U, // LD3Threev2s_POST 238089U, // LD3Threev4h 17547785U, // LD3Threev4h_POST 254473U, // LD3Threev4s 17039881U, // LD3Threev4s_POST 270857U, // LD3Threev8b 17580553U, // LD3Threev8b_POST 287241U, // LD3Threev8h 17072649U, // LD3Threev8h_POST 379729014U, // LD3W 379729014U, // LD3W_IMM 18129417U, // LD3i16 22856201U, // LD3i16_POST 18145801U, // LD3i32 23396873U, // LD3i32_POST 18162185U, // LD3i64 23937545U, // LD3i64_POST 18178569U, // LD3i8 24478217U, // LD3i8_POST 379741130U, // LD4B 379741130U, // LD4B_IMM 379717508U, // LD4D 379717508U, // LD4D_IMM 172583U, // LD4Fourv16b 13287975U, // LD4Fourv16b_POST 205351U, // LD4Fourv2d 13320743U, // LD4Fourv2d_POST 221735U, // LD4Fourv2s 13861415U, // LD4Fourv2s_POST 238119U, // LD4Fourv4h 13877799U, // LD4Fourv4h_POST 254503U, // LD4Fourv4s 13369895U, // LD4Fourv4s_POST 270887U, // LD4Fourv8b 13910567U, // LD4Fourv8b_POST 287271U, // LD4Fourv8h 13402663U, // LD4Fourv8h_POST 379750787U, // LD4H 379750787U, // LD4H_IMM 176323U, // LD4Rv16b 15913155U, // LD4Rv16b_POST 192707U, // LD4Rv1d 13832387U, // LD4Rv1d_POST 209091U, // LD4Rv2d 13848771U, // LD4Rv2d_POST 225475U, // LD4Rv2s 14389443U, // LD4Rv2s_POST 241859U, // LD4Rv4h 14930115U, // LD4Rv4h_POST 258243U, // LD4Rv4s 14422211U, // LD4Rv4s_POST 274627U, // LD4Rv8b 16011459U, // LD4Rv8b_POST 291011U, // LD4Rv8h 14979267U, // LD4Rv8h_POST 379729026U, // LD4W 379729026U, // LD4W_IMM 18129447U, // LD4i16 19710503U, // LD4i16_POST 18145831U, // LD4i32 20775463U, // LD4i32_POST 18162215U, // LD4i64 24986151U, // LD4i64_POST 18178599U, // LD4i8 19235367U, // LD4i8_POST 973169622U, // LDADDAB 973171096U, // LDADDAH 973169821U, // LDADDALB 973171251U, // LDADDALH 973171888U, // LDADDALW 973171888U, // LDADDALX 973169280U, // LDADDAW 973169280U, // LDADDAX 973169780U, // LDADDB 973171237U, // LDADDH 973169921U, // LDADDLB 973171351U, // LDADDLH 973172058U, // LDADDLW 973172058U, // LDADDLX 973170660U, // LDADDW 973170660U, // LDADDX 2253964738U, // LDAPRB 2253966189U, // LDAPRH 2253967684U, // LDAPRW 2253967684U, // LDAPRX 106481133U, // LDAPURBi 106482584U, // LDAPURHi 106481264U, // LDAPURSBWi 106481264U, // LDAPURSBXi 106482702U, // LDAPURSHWi 106482702U, // LDAPURSHXi 106485031U, // LDAPURSWi 106484117U, // LDAPURXi 106484117U, // LDAPURi 2253964686U, // LDARB 2253966137U, // LDARH 2253967561U, // LDARW 2253967561U, // LDARX 2248200299U, // LDAXPW 2248200299U, // LDAXPX 2253964797U, // LDAXRB 2253966248U, // LDAXRH 2253967800U, // LDAXRW 2253967800U, // LDAXRX 973169678U, // LDCLRAB 973171142U, // LDCLRAH 973169861U, // LDCLRALB 973171291U, // LDCLRALH 973171955U, // LDCLRALW 973171955U, // LDCLRALX 973169394U, // LDCLRAW 973169394U, // LDCLRAX 973170083U, // LDCLRB 973171534U, // LDCLRH 973169957U, // LDCLRLB 973171387U, // LDCLRLH 973172249U, // LDCLRLW 973172249U, // LDCLRLX 973173017U, // LDCLRW 973173017U, // LDCLRX 973169687U, // LDEORAB 973171151U, // LDEORAH 973169871U, // LDEORALB 973171301U, // LDEORALH 973171964U, // LDEORALW 973171964U, // LDEORALX 973169402U, // LDEORAW 973169402U, // LDEORAX 973170106U, // LDEORB 973171557U, // LDEORH 973169966U, // LDEORLB 973171396U, // LDEORLH 973172257U, // LDEORLW 973172257U, // LDEORLX 973173043U, // LDEORW 973173043U, // LDEORX 379716466U, // LDFF1B_D_REAL 379749234U, // LDFF1B_H_REAL 379741042U, // LDFF1B_REAL 379724658U, // LDFF1B_S_REAL 379717446U, // LDFF1D_REAL 379717940U, // LDFF1H_D_REAL 379750708U, // LDFF1H_REAL 379726132U, // LDFF1H_S_REAL 379717154U, // LDFF1SB_D_REAL 379749922U, // LDFF1SB_H_REAL 379725346U, // LDFF1SB_S_REAL 379718605U, // LDFF1SH_D_REAL 379726797U, // LDFF1SH_S_REAL 379720943U, // LDFF1SW_D_REAL 379720764U, // LDFF1W_D_REAL 379728956U, // LDFF1W_REAL 2253964693U, // LDLARB 2253966144U, // LDLARH 2253967567U, // LDLARW 2253967567U, // LDLARX 379716474U, // LDNF1B_D_IMM_REAL 379749242U, // LDNF1B_H_IMM_REAL 379741050U, // LDNF1B_IMM_REAL 379724666U, // LDNF1B_S_IMM_REAL 379717454U, // LDNF1D_IMM_REAL 379717948U, // LDNF1H_D_IMM_REAL 379750716U, // LDNF1H_IMM_REAL 379726140U, // LDNF1H_S_IMM_REAL 379717163U, // LDNF1SB_D_IMM_REAL 379749931U, // LDNF1SB_H_IMM_REAL 379725355U, // LDNF1SB_S_IMM_REAL 379718614U, // LDNF1SH_D_IMM_REAL 379726806U, // LDNF1SH_S_IMM_REAL 379720952U, // LDNF1SW_D_IMM_REAL 379720772U, // LDNF1W_D_IMM_REAL 379728964U, // LDNF1W_IMM_REAL 2248200224U, // LDNPDi 2248200224U, // LDNPQi 2248200224U, // LDNPSi 2248200224U, // LDNPWi 2248200224U, // LDNPXi 379741058U, // LDNT1B_ZRI 379741058U, // LDNT1B_ZRR 379717462U, // LDNT1D_ZRI 379717462U, // LDNT1D_ZRR 379750724U, // LDNT1H_ZRI 379750724U, // LDNT1H_ZRR 379728972U, // LDNT1W_ZRI 379728972U, // LDNT1W_ZRR 2248200156U, // LDPDi 2516676572U, // LDPDpost 2516676572U, // LDPDpre 2248200156U, // LDPQi 2516676572U, // LDPQpost 2516676572U, // LDPQpre 2248201473U, // LDPSWi 2516677889U, // LDPSWpost 2516677889U, // LDPSWpre 2248200156U, // LDPSi 2516676572U, // LDPSpost 2516676572U, // LDPSpre 2248200156U, // LDPWi 2516676572U, // LDPWpost 2516676572U, // LDPWpre 2248200156U, // LDPXi 2516676572U, // LDPXpost 2516676572U, // LDPXpre 106480223U, // LDRAAindexed 374956639U, // LDRAAwriteback 106480640U, // LDRABindexed 374957056U, // LDRABwriteback 374957469U, // LDRBBpost 374957469U, // LDRBBpre 106481053U, // LDRBBroW 106481053U, // LDRBBroX 106481053U, // LDRBBui 374960359U, // LDRBpost 374960359U, // LDRBpre 106483943U, // LDRBroW 106483943U, // LDRBroX 106483943U, // LDRBui 436261095U, // LDRDl 374960359U, // LDRDpost 374960359U, // LDRDpre 106483943U, // LDRDroW 106483943U, // LDRDroX 106483943U, // LDRDui 374958920U, // LDRHHpost 374958920U, // LDRHHpre 106482504U, // LDRHHroW 106482504U, // LDRHHroX 106482504U, // LDRHHui 374960359U, // LDRHpost 374960359U, // LDRHpre 106483943U, // LDRHroW 106483943U, // LDRHroX 106483943U, // LDRHui 436261095U, // LDRQl 374960359U, // LDRQpost 374960359U, // LDRQpre 106483943U, // LDRQroW 106483943U, // LDRQroX 106483943U, // LDRQui 374957657U, // LDRSBWpost 374957657U, // LDRSBWpre 106481241U, // LDRSBWroW 106481241U, // LDRSBWroX 106481241U, // LDRSBWui 374957657U, // LDRSBXpost 374957657U, // LDRSBXpre 106481241U, // LDRSBXroW 106481241U, // LDRSBXroX 106481241U, // LDRSBXui 374959095U, // LDRSHWpost 374959095U, // LDRSHWpre 106482679U, // LDRSHWroW 106482679U, // LDRSHWroX 106482679U, // LDRSHWui 374959095U, // LDRSHXpost 374959095U, // LDRSHXpre 106482679U, // LDRSHXroW 106482679U, // LDRSHXroX 106482679U, // LDRSHXui 436262160U, // LDRSWl 374961424U, // LDRSWpost 374961424U, // LDRSWpre 106485008U, // LDRSWroW 106485008U, // LDRSWroX 106485008U, // LDRSWui 436261095U, // LDRSl 374960359U, // LDRSpost 374960359U, // LDRSpre 106483943U, // LDRSroW 106483943U, // LDRSroX 106483943U, // LDRSui 436261095U, // LDRWl 374960359U, // LDRWpost 374960359U, // LDRWpre 106483943U, // LDRWroW 106483943U, // LDRWroX 106483943U, // LDRWui 436261095U, // LDRXl 374960359U, // LDRXpost 374960359U, // LDRXpre 106483943U, // LDRXroW 106483943U, // LDRXroX 106483943U, // LDRXui 106803431U, // LDR_PXI 106803431U, // LDR_ZXI 973169703U, // LDSETAB 973171167U, // LDSETAH 973169889U, // LDSETALB 973171319U, // LDSETALH 973171980U, // LDSETALW 973171980U, // LDSETALX 973169442U, // LDSETAW 973169442U, // LDSETAX 973170303U, // LDSETB 973171736U, // LDSETH 973169982U, // LDSETLB 973171412U, // LDSETLH 973172305U, // LDSETLW 973172305U, // LDSETLX 973173476U, // LDSETW 973173476U, // LDSETX 973169712U, // LDSMAXAB 973171176U, // LDSMAXAH 973169899U, // LDSMAXALB 973171329U, // LDSMAXALH 973171989U, // LDSMAXALW 973171989U, // LDSMAXALX 973169466U, // LDSMAXAW 973169466U, // LDSMAXAX 973170392U, // LDSMAXB 973171768U, // LDSMAXH 973169991U, // LDSMAXLB 973171454U, // LDSMAXLH 973172360U, // LDSMAXLW 973172360U, // LDSMAXLX 973174109U, // LDSMAXW 973174109U, // LDSMAXX 973169631U, // LDSMINAB 973171115U, // LDSMINAH 973169831U, // LDSMINALB 973171261U, // LDSMINALH 973171920U, // LDSMINALW 973171920U, // LDSMINALX 973169349U, // LDSMINAW 973169349U, // LDSMINAX 973170016U, // LDSMINB 973171474U, // LDSMINH 973169930U, // LDSMINLB 973171360U, // LDSMINLH 973172211U, // LDSMINLW 973172211U, // LDSMINLX 973172462U, // LDSMINW 973172462U, // LDSMINX 106481098U, // LDTRBi 106482549U, // LDTRHi 106481248U, // LDTRSBWi 106481248U, // LDTRSBXi 106482686U, // LDTRSHWi 106482686U, // LDTRSHXi 106485015U, // LDTRSWi 106484081U, // LDTRWi 106484081U, // LDTRXi 973169722U, // LDUMAXAB 973171186U, // LDUMAXAH 973169910U, // LDUMAXALB 973171340U, // LDUMAXALH 973171999U, // LDUMAXALW 973171999U, // LDUMAXALX 973169475U, // LDUMAXAW 973169475U, // LDUMAXAX 973170401U, // LDUMAXB 973171777U, // LDUMAXH 973170001U, // LDUMAXLB 973171464U, // LDUMAXLH 973172369U, // LDUMAXLW 973172369U, // LDUMAXLX 973174117U, // LDUMAXW 973174117U, // LDUMAXX 973169641U, // LDUMINAB 973171125U, // LDUMINAH 973169842U, // LDUMINALB 973171272U, // LDUMINALH 973171930U, // LDUMINALW 973171930U, // LDUMINALX 973169358U, // LDUMINAW 973169358U, // LDUMINAX 973170025U, // LDUMINB 973171483U, // LDUMINH 973169940U, // LDUMINLB 973171370U, // LDUMINLH 973172220U, // LDUMINLW 973172220U, // LDUMINLX 973172470U, // LDUMINW 973172470U, // LDUMINX 106481118U, // LDURBBi 106484104U, // LDURBi 106484104U, // LDURDi 106482569U, // LDURHHi 106484104U, // LDURHi 106484104U, // LDURQi 106481256U, // LDURSBWi 106481256U, // LDURSBXi 106482694U, // LDURSHWi 106482694U, // LDURSHXi 106485023U, // LDURSWi 106484104U, // LDURSi 106484104U, // LDURWi 106484104U, // LDURXi 2248200327U, // LDXPW 2248200327U, // LDXPX 2253964805U, // LDXRB 2253966256U, // LDXRH 2253967807U, // LDXRW 2253967807U, // LDXRX 0U, // LOADgot 302002471U, // LSLR_ZPmZ_B 302010663U, // LSLR_ZPmZ_D 2186309927U, // LSLR_ZPmZ_H 302027047U, // LSLR_ZPmZ_S 100716088U, // LSLVWr 100716088U, // LSLVXr 302001720U, // LSL_WIDE_ZPmZ_B 2186309176U, // LSL_WIDE_ZPmZ_H 302026296U, // LSL_WIDE_ZPmZ_S 167783992U, // LSL_WIDE_ZZZ_B 2387111480U, // LSL_WIDE_ZZZ_H 268471864U, // LSL_WIDE_ZZZ_S 302001720U, // LSL_ZPmI_B 302009912U, // LSL_ZPmI_D 2186309176U, // LSL_ZPmI_H 302026296U, // LSL_ZPmI_S 302001720U, // LSL_ZPmZ_B 302009912U, // LSL_ZPmZ_D 2186309176U, // LSL_ZPmZ_H 302026296U, // LSL_ZPmZ_S 167783992U, // LSL_ZZI_B 201346616U, // LSL_ZZI_D 239627832U, // LSL_ZZI_H 268471864U, // LSL_ZZI_S 302002518U, // LSRR_ZPmZ_B 302010710U, // LSRR_ZPmZ_D 2186309974U, // LSRR_ZPmZ_H 302027094U, // LSRR_ZPmZ_S 100716897U, // LSRVWr 100716897U, // LSRVXr 302002529U, // LSR_WIDE_ZPmZ_B 2186309985U, // LSR_WIDE_ZPmZ_H 302027105U, // LSR_WIDE_ZPmZ_S 167784801U, // LSR_WIDE_ZZZ_B 2387112289U, // LSR_WIDE_ZZZ_H 268472673U, // LSR_WIDE_ZZZ_S 302002529U, // LSR_ZPmI_B 302010721U, // LSR_ZPmI_D 2186309985U, // LSR_ZPmI_H 302027105U, // LSR_ZPmI_S 302002529U, // LSR_ZPmZ_B 302010721U, // LSR_ZPmZ_D 2186309985U, // LSR_ZPmZ_H 302027105U, // LSR_ZPmZ_S 167784801U, // LSR_ZZI_B 201347425U, // LSR_ZZI_D 239628641U, // LSR_ZZI_H 268472673U, // LSR_ZZI_S 100714512U, // MADDWrrr 100714512U, // MADDXrrr 302000017U, // MAD_ZPmZZ_B 302008209U, // MAD_ZPmZZ_D 2186307473U, // MAD_ZPmZZ_H 302024593U, // MAD_ZPmZZ_S 301998771U, // MLA_ZPmZZ_B 302006963U, // MLA_ZPmZZ_D 2186306227U, // MLA_ZPmZZ_H 302023347U, // MLA_ZPmZZ_S 135324339U, // MLAv16i8 2283332275U, // MLAv2i32 2283332275U, // MLAv2i32_indexed 136897203U, // MLAv4i16 136897203U, // MLAv4i16_indexed 137421491U, // MLAv4i32 137421491U, // MLAv4i32_indexed 2285429427U, // MLAv8i16 2285429427U, // MLAv8i16_indexed 2285953715U, // MLAv8i8 302002771U, // MLS_ZPmZZ_B 302010963U, // MLS_ZPmZZ_D 2186310227U, // MLS_ZPmZZ_H 302027347U, // MLS_ZPmZZ_S 135328339U, // MLSv16i8 2283336275U, // MLSv2i32 2283336275U, // MLSv2i32_indexed 136901203U, // MLSv4i16 136901203U, // MLSv4i16_indexed 137425491U, // MLSv4i32 137425491U, // MLSv4i32_indexed 2285433427U, // MLSv8i16 2285433427U, // MLSv8i16_indexed 2285957715U, // MLSv8i8 1006685329U, // MOVID 3188763793U, // MOVIv16b_ns 1008774289U, // MOVIv2d_ns 3189288081U, // MOVIv2i32 3189288081U, // MOVIv2s_msl 3190336657U, // MOVIv4i16 3190860945U, // MOVIv4i32 3190860945U, // MOVIv4s_msl 3191909521U, // MOVIv8b_ns 3191385233U, // MOVIv8i16 402705564U, // MOVKWi 402705564U, // MOVKXi 3187724142U, // MOVNWi 3187724142U, // MOVNXi 13705U, // MOVPRFX_ZPmZ_B 21897U, // MOVPRFX_ZPmZ_D 2181592457U, // MOVPRFX_ZPmZ_H 38281U, // MOVPRFX_ZPmZ_S 302003593U, // MOVPRFX_ZPzZ_B 302011785U, // MOVPRFX_ZPzZ_D 2622518665U, // MOVPRFX_ZPzZ_H 302028169U, // MOVPRFX_ZPzZ_S 2449847689U, // MOVPRFX_ZZ 3187725817U, // MOVZWi 3187725817U, // MOVZXi 0U, // MOVaddr 0U, // MOVaddrBA 0U, // MOVaddrCP 0U, // MOVaddrEXT 0U, // MOVaddrJT 0U, // MOVaddrTLS 0U, // MOVbaseTLS 0U, // MOVi32imm 0U, // MOVi64imm 1073795744U, // MRS 301999685U, // MSB_ZPmZZ_B 302007877U, // MSB_ZPmZZ_D 2186307141U, // MSB_ZPmZZ_H 302024261U, // MSB_ZPmZZ_S 381286U, // MSR 389478U, // MSRpstateImm1 389478U, // MSRpstateImm4 100714166U, // MSUBWrrr 100714166U, // MSUBXrrr 167784033U, // MUL_ZI_B 201346657U, // MUL_ZI_D 239627873U, // MUL_ZI_H 268471905U, // MUL_ZI_S 302001761U, // MUL_ZPmZ_B 302009953U, // MUL_ZPmZ_D 2186309217U, // MUL_ZPmZ_H 302026337U, // MUL_ZPmZ_S 68202081U, // MULv16i8 2216210017U, // MULv2i32 2216210017U, // MULv2i32_indexed 69774945U, // MULv4i16 69774945U, // MULv4i16_indexed 70299233U, // MULv4i32 70299233U, // MULv4i32_indexed 2218307169U, // MULv8i16 2218307169U, // MULv8i16_indexed 2218831457U, // MULv8i8 3189288062U, // MVNIv2i32 3189288062U, // MVNIv2s_msl 3190336638U, // MVNIv4i16 3190860926U, // MVNIv4i32 3190860926U, // MVNIv4s_msl 3191385214U, // MVNIv8i16 302002728U, // NANDS_PPzPP 302000180U, // NAND_PPzPP 10516U, // NEG_ZPmZ_B 18708U, // NEG_ZPmZ_D 2181589268U, // NEG_ZPmZ_H 35092U, // NEG_ZPmZ_S 68200724U, // NEGv16i8 2248198420U, // NEGv1i64 68725012U, // NEGv2i32 2216732948U, // NEGv2i64 69773588U, // NEGv4i16 2217781524U, // NEGv4i32 70822164U, // NEGv8i16 2218830100U, // NEGv8i8 302002859U, // NORS_PPzPP 302002490U, // NOR_PPzPP 13114U, // NOT_ZPmZ_B 21306U, // NOT_ZPmZ_D 2181591866U, // NOT_ZPmZ_H 37690U, // NOT_ZPmZ_S 68203322U, // NOTv16i8 2218832698U, // NOTv8i8 302002810U, // ORNS_PPzPP 0U, // ORNWrr 100716337U, // ORNWrs 0U, // ORNXrr 100716337U, // ORNXrs 302001969U, // ORN_PPzPP 68202289U, // ORNv16i8 2218831665U, // ORNv8i8 302002865U, // ORRS_PPzPP 100716875U, // ORRWri 0U, // ORRWrr 100716875U, // ORRWrs 100716875U, // ORRXri 0U, // ORRXrr 100716875U, // ORRXrs 302002507U, // ORR_PPzPP 201347403U, // ORR_ZI 302002507U, // ORR_ZPmZ_B 302010699U, // ORR_ZPmZ_D 2186309963U, // ORR_ZPmZ_H 302027083U, // ORR_ZPmZ_S 201347403U, // ORR_ZZZ 68202827U, // ORRv16i8 404287819U, // ORRv2i32 405336395U, // ORRv4i16 405860683U, // ORRv4i32 406384971U, // ORRv8i16 2218832203U, // ORRv8i8 302044188U, // ORV_VPZ_B 302044188U, // ORV_VPZ_D 302044188U, // ORV_VPZ_H 302044188U, // ORV_VPZ_S 2248196729U, // PACDA 2248197229U, // PACDB 6341452U, // PACDZA 6342378U, // PACDZB 100713110U, // PACGA 2248196765U, // PACIA 5796U, // PACIA1716 5927U, // PACIASP 5982U, // PACIAZ 2248197257U, // PACIB 5816U, // PACIB1716 5943U, // PACIBSP 5996U, // PACIBZ 6341468U, // PACIZA 6342394U, // PACIZB 6301913U, // PFALSE 70820111U, // PMULLv16i8 1132506590U, // PMULLv1i64 1166057743U, // PMULLv2i64 2218307038U, // PMULLv8i8 68202093U, // PMULv16i8 2218831469U, // PMULv8i8 302003042U, // PNEXT_B 302011234U, // PNEXT_D 2387637090U, // PNEXT_H 302027618U, // PNEXT_S 3079537795U, // PRFB_D_PZI 246285443U, // PRFB_D_SCALED 2393769091U, // PRFB_D_SXTW_SCALED 246285443U, // PRFB_D_UXTW_SCALED 246285443U, // PRFB_PRI 2393769091U, // PRFB_PRR 3080062083U, // PRFB_S_PZI 246285443U, // PRFB_S_SXTW_SCALED 2393769091U, // PRFB_S_UXTW_SCALED 1200490542U, // PRFD_D_PZI 246286382U, // PRFD_D_SCALED 2393770030U, // PRFD_D_SXTW_SCALED 246286382U, // PRFD_D_UXTW_SCALED 246286382U, // PRFD_PRI 2393770030U, // PRFD_PRR 1201014830U, // PRFD_S_PZI 246286382U, // PRFD_S_SXTW_SCALED 2393770030U, // PRFD_S_UXTW_SCALED 1234045485U, // PRFH_D_PZI 246286893U, // PRFH_D_SCALED 2393770541U, // PRFH_D_SXTW_SCALED 246286893U, // PRFH_D_UXTW_SCALED 246286893U, // PRFH_PRI 2393770541U, // PRFH_PRR 1234569773U, // PRFH_S_PZI 246286893U, // PRFH_S_SXTW_SCALED 2393770541U, // PRFH_S_UXTW_SCALED 436612781U, // PRFMl 106835629U, // PRFMroW 106835629U, // PRFMroX 106835629U, // PRFMui 246289619U, // PRFS_PRR 106835665U, // PRFUMi 1267602643U, // PRFW_D_PZI 2393773267U, // PRFW_D_SCALED 246289619U, // PRFW_D_SXTW_SCALED 2393773267U, // PRFW_D_UXTW_SCALED 246289619U, // PRFW_PRI 1268126931U, // PRFW_S_PZI 246289619U, // PRFW_S_SXTW_SCALED 2393773267U, // PRFW_S_UXTW_SCALED 2315629382U, // PTEST_PP 2650812975U, // PTRUES_B 2650821167U, // PTRUES_D 26767919U, // PTRUES_H 2650837551U, // PTRUES_S 2650810611U, // PTRUE_B 2650818803U, // PTRUE_D 26765555U, // PTRUE_H 2650835187U, // PTRUE_S 27290705U, // PUNPKHI_PP 27291525U, // PUNPKLO_PP 2216210144U, // RADDHNv2i64_v2i32 2284904786U, // RADDHNv2i64_v4i32 69775072U, // RADDHNv4i32_v4i16 137945426U, // RADDHNv4i32_v8i16 2282807634U, // RADDHNv8i16_v16i8 2218831584U, // RADDHNv8i16_v8i8 2216730741U, // RAX1 2248200960U, // RBITWr 2248200960U, // RBITXr 13056U, // RBIT_ZPmZ_B 21248U, // RBIT_ZPmZ_D 2181591808U, // RBIT_ZPmZ_H 37632U, // RBIT_ZPmZ_S 68203264U, // RBITv16i8 2218832640U, // RBITv8i8 302002840U, // RDFFRS_PPz 6303980U, // RDFFR_P 302002412U, // RDFFR_PPz 2248199810U, // RDVLI_XI 6345439U, // RET 5892U, // RETAA 5899U, // RETAB 0U, // RET_ReallyLR 2248196665U, // REV16Wr 2248196665U, // REV16Xr 68198969U, // REV16v16i8 2218828345U, // REV16v8i8 2248196219U, // REV32Xr 68198523U, // REV32v16i8 69771387U, // REV32v4i16 70819963U, // REV32v8i16 2218827899U, // REV32v8i8 68198944U, // REV64v16i8 68723232U, // REV64v2i32 69771808U, // REV64v4i16 2217779744U, // REV64v4i32 70820384U, // REV64v8i16 2218828320U, // REV64v8i8 18130U, // REVB_ZPmZ_D 2181588690U, // REVB_ZPmZ_H 34514U, // REVB_ZPmZ_S 19506U, // REVH_ZPmZ_D 35890U, // REVH_ZPmZ_S 21827U, // REVW_ZPmZ_D 2248201140U, // REVWr 2248201140U, // REVXr 2315269044U, // REV_PP_B 2348831668U, // REV_PP_D 608727988U, // REV_PP_H 2415956916U, // REV_PP_S 2315269044U, // REV_ZZ_B 2348831668U, // REV_ZZ_D 608727988U, // REV_ZZ_H 2415956916U, // REV_ZZ_S 100714751U, // RMIF 100716863U, // RORVWr 100716863U, // RORVXr 2282807663U, // RSHRNv16i8_shift 2216210209U, // RSHRNv2i32_shift 69775137U, // RSHRNv4i16_shift 2284904815U, // RSHRNv4i32_shift 137945455U, // RSHRNv8i16_shift 2218831649U, // RSHRNv8i8_shift 2216210136U, // RSUBHNv2i64_v2i32 2284904777U, // RSUBHNv2i64_v4i32 69775064U, // RSUBHNv4i32_v4i16 137945417U, // RSUBHNv4i32_v8i16 2282807625U, // RSUBHNv8i16_v16i8 2218831576U, // RSUBHNv8i16_v8i8 137945243U, // SABALv16i8_v8i16 2283859106U, // SABALv2i32_v2i64 137424034U, // SABALv4i16_v4i32 136372379U, // SABALv4i32_v2i64 2284904603U, // SABALv8i16_v4i32 2285431970U, // SABALv8i8_v8i16 135324269U, // SABAv16i8 2283332205U, // SABAv2i32 136897133U, // SABAv4i16 137421421U, // SABAv4i32 2285429357U, // SABAv8i16 2285953645U, // SABAv8i8 70820053U, // SABDLv16i8_v8i16 2216734028U, // SABDLv2i32_v2i64 70298956U, // SABDLv4i16_v4i32 69247189U, // SABDLv4i32_v2i64 2217779413U, // SABDLv8i16_v4i32 2218306892U, // SABDLv8i8_v8i16 302000042U, // SABD_ZPmZ_B 302008234U, // SABD_ZPmZ_D 2186307498U, // SABD_ZPmZ_H 302024618U, // SABD_ZPmZ_S 68200362U, // SABDv16i8 2216208298U, // SABDv2i32 69773226U, // SABDv4i16 70297514U, // SABDv4i32 2218305450U, // SABDv8i16 2218829738U, // SABDv8i8 137949153U, // SADALPv16i8_v8i16 162066401U, // SADALPv2i32_v1i64 135852001U, // SADALPv4i16_v2i32 2283859937U, // SADALPv4i32_v2i64 137424865U, // SADALPv8i16_v4i32 2284384225U, // SADALPv8i8_v4i16 70823921U, // SADDLPv16i8_v8i16 94941169U, // SADDLPv2i32_v1i64 68726769U, // SADDLPv4i16_v2i32 2216734705U, // SADDLPv4i32_v2i64 70299633U, // SADDLPv8i16_v4i32 2217258993U, // SADDLPv8i8_v4i16 67163083U, // SADDLVv16i8v 67163083U, // SADDLVv4i16v 2214646731U, // SADDLVv4i32v 67163083U, // SADDLVv8i16v 2214646731U, // SADDLVv8i8v 70820069U, // SADDLv16i8_v8i16 2216734066U, // SADDLv2i32_v2i64 70298994U, // SADDLv4i16_v4i32 69247205U, // SADDLv4i32_v2i64 2217779429U, // SADDLv8i16_v4i32 2218306930U, // SADDLv8i8_v8i16 302044064U, // SADDV_VPZ_B 302044064U, // SADDV_VPZ_H 302044064U, // SADDV_VPZ_S 2218303982U, // SADDWv16i8_v8i16 2216735941U, // SADDWv2i32_v2i64 70300869U, // SADDWv4i16_v4i32 2216731118U, // SADDWv4i32_v2i64 70296046U, // SADDWv8i16_v4i32 2218308805U, // SADDWv8i8_v8i16 100717072U, // SBCSWr 100717072U, // SBCSXr 100714257U, // SBCWr 100714257U, // SBCXr 100716193U, // SBFMWri 100716193U, // SBFMXri 100714757U, // SCVTFSWDri 100714757U, // SCVTFSWHri 100714757U, // SCVTFSWSri 100714757U, // SCVTFSXDri 100714757U, // SCVTFSXHri 100714757U, // SCVTFSXSri 2248198405U, // SCVTFUWDri 2248198405U, // SCVTFUWHri 2248198405U, // SCVTFUWSri 2248198405U, // SCVTFUXDri 2248198405U, // SCVTFUXHri 2248198405U, // SCVTFUXSri 18693U, // SCVTF_ZPmZ_DtoD 2181589253U, // SCVTF_ZPmZ_DtoH 35077U, // SCVTF_ZPmZ_DtoS 2181589253U, // SCVTF_ZPmZ_HtoH 18693U, // SCVTF_ZPmZ_StoD 2181589253U, // SCVTF_ZPmZ_StoH 35077U, // SCVTF_ZPmZ_StoS 100714757U, // SCVTFd 100714757U, // SCVTFh 100714757U, // SCVTFs 2248198405U, // SCVTFv1i16 2248198405U, // SCVTFv1i32 2248198405U, // SCVTFv1i64 68724997U, // SCVTFv2f32 2216732933U, // SCVTFv2f64 2216208645U, // SCVTFv2i32_shift 2216732933U, // SCVTFv2i64_shift 69773573U, // SCVTFv4f16 2217781509U, // SCVTFv4f32 69773573U, // SCVTFv4i16_shift 70297861U, // SCVTFv4i32_shift 70822149U, // SCVTFv8f16 2218305797U, // SCVTFv8i16_shift 302010794U, // SDIVR_ZPmZ_D 302027178U, // SDIVR_ZPmZ_S 100717503U, // SDIVWr 100717503U, // SDIVXr 302011327U, // SDIV_ZPmZ_D 302027711U, // SDIV_ZPmZ_S 3422573357U, // SDOT_ZZZI_D 3456144173U, // SDOT_ZZZI_S 3422573357U, // SDOT_ZZZ_D 3456144173U, // SDOT_ZZZ_S 137425709U, // SDOTlanev16i8 2283336493U, // SDOTlanev8i8 137425709U, // SDOTv16i8 2283336493U, // SDOTv8i8 302001538U, // SEL_PPPP 302001538U, // SEL_ZPZZ_B 302009730U, // SEL_ZPZZ_D 2387635586U, // SEL_ZPZZ_H 302026114U, // SEL_ZPZZ_S 6341169U, // SETF16 6341184U, // SETF8 5959U, // SETFFR 369190666U, // SHA1Crrr 2248198439U, // SHA1Hrr 369192602U, // SHA1Mrrr 369192878U, // SHA1Prrr 137420801U, // SHA1SU0rrr 2284904523U, // SHA1SU1rr 369189009U, // SHA256H2rrr 369191311U, // SHA256Hrrr 2284904469U, // SHA256SU0rr 137420895U, // SHA256SU1rrr 369191258U, // SHA512H 369188999U, // SHA512H2 2216730634U, // SHA512SU0 2283855956U, // SHA512SU1 68200449U, // SHADDv16i8 2216208385U, // SHADDv2i32 69773313U, // SHADDv4i16 70297601U, // SHADDv4i32 2218305537U, // SHADDv8i16 2218829825U, // SHADDv8i8 70820086U, // SHLLv16i8 2216734152U, // SHLLv2i32 70299080U, // SHLLv4i16 2216730870U, // SHLLv4i32 70295798U, // SHLLv8i16 2218307016U, // SHLLv8i8 100715921U, // SHLd 68201873U, // SHLv16i8_shift 2216209809U, // SHLv2i32_shift 2216734097U, // SHLv2i64_shift 69774737U, // SHLv4i16_shift 70299025U, // SHLv4i32_shift 2218306961U, // SHLv8i16_shift 2218831249U, // SHLv8i8_shift 2282807645U, // SHRNv16i8_shift 2216210193U, // SHRNv2i32_shift 69775121U, // SHRNv4i16_shift 2284904797U, // SHRNv4i32_shift 137945437U, // SHRNv8i16_shift 2218831633U, // SHRNv8i8_shift 68200103U, // SHSUBv16i8 2216208039U, // SHSUBv2i32 69772967U, // SHSUBv4i16 70297255U, // SHSUBv4i32 2218305191U, // SHSUBv8i16 2218829479U, // SHSUBv8i8 369192057U, // SLId 135326841U, // SLIv16i8_shift 2283334777U, // SLIv2i32_shift 2283859065U, // SLIv2i64_shift 136899705U, // SLIv4i16_shift 137423993U, // SLIv4i32_shift 2285431929U, // SLIv8i16_shift 2285956217U, // SLIv8i8_shift 137420906U, // SM3PARTW1 137421310U, // SM3PARTW2 70295614U, // SM3SS1 137421383U, // SM3TT1A 137421720U, // SM3TT1B 137421392U, // SM3TT2A 137421749U, // SM3TT2B 2217781339U, // SM4E 70301097U, // SM4ENCKEY 100715874U, // SMADDLrrr 68202617U, // SMAXPv16i8 2216210553U, // SMAXPv2i32 69775481U, // SMAXPv4i16 70299769U, // SMAXPv4i32 2218307705U, // SMAXPv8i16 2218831993U, // SMAXPv8i8 302044200U, // SMAXV_VPZ_B 302044200U, // SMAXV_VPZ_D 302044200U, // SMAXV_VPZ_H 302044200U, // SMAXV_VPZ_S 67163176U, // SMAXVv16i8v 67163176U, // SMAXVv4i16v 2214646824U, // SMAXVv4i32v 67163176U, // SMAXVv8i16v 2214646824U, // SMAXVv8i8v 167785823U, // SMAX_ZI_B 201348447U, // SMAX_ZI_D 239629663U, // SMAX_ZI_H 268473695U, // SMAX_ZI_S 302003551U, // SMAX_ZPmZ_B 302011743U, // SMAX_ZPmZ_D 2186311007U, // SMAX_ZPmZ_H 302028127U, // SMAX_ZPmZ_S 68203871U, // SMAXv16i8 2216211807U, // SMAXv2i32 69776735U, // SMAXv4i16 70301023U, // SMAXv4i32 2218308959U, // SMAXv8i16 2218833247U, // SMAXv8i8 75562U, // SMC 68202541U, // SMINPv16i8 2216210477U, // SMINPv2i32 69775405U, // SMINPv4i16 70299693U, // SMINPv4i32 2218307629U, // SMINPv8i16 2218831917U, // SMINPv8i8 302044148U, // SMINV_VPZ_B 302044148U, // SMINV_VPZ_D 302044148U, // SMINV_VPZ_H 302044148U, // SMINV_VPZ_S 67163124U, // SMINVv16i8v 67163124U, // SMINVv4i16v 2214646772U, // SMINVv4i32v 67163124U, // SMINVv8i16v 2214646772U, // SMINVv8i8v 167784176U, // SMIN_ZI_B 201346800U, // SMIN_ZI_D 239628016U, // SMIN_ZI_H 268472048U, // SMIN_ZI_S 302001904U, // SMIN_ZPmZ_B 302010096U, // SMIN_ZPmZ_D 2186309360U, // SMIN_ZPmZ_H 302026480U, // SMIN_ZPmZ_S 68202224U, // SMINv16i8 2216210160U, // SMINv2i32 69775088U, // SMINv4i16 70299376U, // SMINv4i32 2218307312U, // SMINv8i16 2218831600U, // SMINv8i8 137945269U, // SMLALv16i8_v8i16 2283859138U, // SMLALv2i32_indexed 2283859138U, // SMLALv2i32_v2i64 137424066U, // SMLALv4i16_indexed 137424066U, // SMLALv4i16_v4i32 136372405U, // SMLALv4i32_indexed 136372405U, // SMLALv4i32_v2i64 2284904629U, // SMLALv8i16_indexed 2284904629U, // SMLALv8i16_v4i32 2285432002U, // SMLALv8i8_v8i16 137945393U, // SMLSLv16i8_v8i16 2283859517U, // SMLSLv2i32_indexed 2283859517U, // SMLSLv2i32_v2i64 137424445U, // SMLSLv4i16_indexed 137424445U, // SMLSLv4i16_v4i32 136372529U, // SMLSLv4i32_indexed 136372529U, // SMLSLv4i32_v2i64 2284904753U, // SMLSLv8i16_indexed 2284904753U, // SMLSLv8i16_v4i32 2285432381U, // SMLSLv8i8_v8i16 67163151U, // SMOVvi16to32 67163151U, // SMOVvi16to64 2214646799U, // SMOVvi32to64 2214646799U, // SMOVvi8to32 2214646799U, // SMOVvi8to64 100715822U, // SMSUBLrrr 302000880U, // SMULH_ZPmZ_B 302009072U, // SMULH_ZPmZ_D 2186308336U, // SMULH_ZPmZ_H 302025456U, // SMULH_ZPmZ_S 100715248U, // SMULHrr 70820119U, // SMULLv16i8_v8i16 2216734181U, // SMULLv2i32_indexed 2216734181U, // SMULLv2i32_v2i64 70299109U, // SMULLv4i16_indexed 70299109U, // SMULLv4i16_v4i32 69247255U, // SMULLv4i32_indexed 69247255U, // SMULLv4i32_v2i64 2217779479U, // SMULLv8i16_indexed 2217779479U, // SMULLv8i16_v4i32 2218307045U, // SMULLv8i8_v8i16 302000225U, // SPLICE_ZPZ_B 302008417U, // SPLICE_ZPZ_D 2387634273U, // SPLICE_ZPZ_H 302024801U, // SPLICE_ZPZ_S 68202996U, // SQABSv16i8 2248200692U, // SQABSv1i16 2248200692U, // SQABSv1i32 2248200692U, // SQABSv1i64 2248200692U, // SQABSv1i8 68727284U, // SQABSv2i32 2216735220U, // SQABSv2i64 69775860U, // SQABSv4i16 2217783796U, // SQABSv4i32 70824436U, // SQABSv8i16 2218832372U, // SQABSv8i8 167782431U, // SQADD_ZI_B 201345055U, // SQADD_ZI_D 239626271U, // SQADD_ZI_H 268470303U, // SQADD_ZI_S 167782431U, // SQADD_ZZZ_B 201345055U, // SQADD_ZZZ_D 2387109919U, // SQADD_ZZZ_H 268470303U, // SQADD_ZZZ_S 68200479U, // SQADDv16i8 100714527U, // SQADDv1i16 100714527U, // SQADDv1i32 100714527U, // SQADDv1i64 100714527U, // SQADDv1i8 2216208415U, // SQADDv2i32 2216732703U, // SQADDv2i64 69773343U, // SQADDv4i16 70297631U, // SQADDv4i32 2218305567U, // SQADDv8i16 2218829855U, // SQADDv8i8 536921165U, // SQDECB_XPiI 1342227533U, // SQDECB_XPiWdI 536922045U, // SQDECD_XPiI 1342228413U, // SQDECD_XPiWdI 536889277U, // SQDECD_ZPiI 536922629U, // SQDECH_XPiI 1342228997U, // SQDECH_XPiWdI 6842885U, // SQDECH_ZPiI 167825333U, // SQDECP_XPWd_B 201379765U, // SQDECP_XPWd_D 570478517U, // SQDECP_XPWd_H 268488629U, // SQDECP_XPWd_S 2315308981U, // SQDECP_XP_B 2348863413U, // SQDECP_XP_D 2717962165U, // SQDECP_XP_H 2415972277U, // SQDECP_XP_S 2147504053U, // SQDECP_ZP_D 604532661U, // SQDECP_ZP_H 2147520437U, // SQDECP_ZP_S 536925349U, // SQDECW_XPiI 1342231717U, // SQDECW_XPiWdI 536908965U, // SQDECW_ZPiI 369192121U, // SQDMLALi16 369192121U, // SQDMLALi32 369192121U, // SQDMLALv1i32_indexed 369192121U, // SQDMLALv1i64_indexed 2283859129U, // SQDMLALv2i32_indexed 2283859129U, // SQDMLALv2i32_v2i64 137424057U, // SQDMLALv4i16_indexed 137424057U, // SQDMLALv4i16_v4i32 136372395U, // SQDMLALv4i32_indexed 136372395U, // SQDMLALv4i32_v2i64 2284904619U, // SQDMLALv8i16_indexed 2284904619U, // SQDMLALv8i16_v4i32 369192500U, // SQDMLSLi16 369192500U, // SQDMLSLi32 369192500U, // SQDMLSLv1i32_indexed 369192500U, // SQDMLSLv1i64_indexed 2283859508U, // SQDMLSLv2i32_indexed 2283859508U, // SQDMLSLv2i32_v2i64 137424436U, // SQDMLSLv4i16_indexed 137424436U, // SQDMLSLv4i16_v4i32 136372519U, // SQDMLSLv4i32_indexed 136372519U, // SQDMLSLv4i32_v2i64 2284904743U, // SQDMLSLv8i16_indexed 2284904743U, // SQDMLSLv8i16_v4i32 100715229U, // SQDMULHv1i16 100715229U, // SQDMULHv1i16_indexed 100715229U, // SQDMULHv1i32 100715229U, // SQDMULHv1i32_indexed 2216209117U, // SQDMULHv2i32 2216209117U, // SQDMULHv2i32_indexed 69774045U, // SQDMULHv4i16 69774045U, // SQDMULHv4i16_indexed 70298333U, // SQDMULHv4i32 70298333U, // SQDMULHv4i32_indexed 2218306269U, // SQDMULHv8i16 2218306269U, // SQDMULHv8i16_indexed 100715989U, // SQDMULLi16 100715989U, // SQDMULLi32 100715989U, // SQDMULLv1i32_indexed 100715989U, // SQDMULLv1i64_indexed 2216734165U, // SQDMULLv2i32_indexed 2216734165U, // SQDMULLv2i32_v2i64 70299093U, // SQDMULLv4i16_indexed 70299093U, // SQDMULLv4i16_v4i32 69247237U, // SQDMULLv4i32_indexed 69247237U, // SQDMULLv4i32_v2i64 2217779461U, // SQDMULLv8i16_indexed 2217779461U, // SQDMULLv8i16_v4i32 536921181U, // SQINCB_XPiI 1342227549U, // SQINCB_XPiWdI 536922061U, // SQINCD_XPiI 1342228429U, // SQINCD_XPiWdI 536889293U, // SQINCD_ZPiI 536922645U, // SQINCH_XPiI 1342229013U, // SQINCH_XPiWdI 6842901U, // SQINCH_ZPiI 167825349U, // SQINCP_XPWd_B 201379781U, // SQINCP_XPWd_D 570478533U, // SQINCP_XPWd_H 268488645U, // SQINCP_XPWd_S 2315308997U, // SQINCP_XP_B 2348863429U, // SQINCP_XP_D 2717962181U, // SQINCP_XP_H 2415972293U, // SQINCP_XP_S 2147504069U, // SQINCP_ZP_D 604532677U, // SQINCP_ZP_H 2147520453U, // SQINCP_ZP_S 536925365U, // SQINCW_XPiI 1342231733U, // SQINCW_XPiWdI 536908981U, // SQINCW_ZPiI 68200729U, // SQNEGv16i8 2248198425U, // SQNEGv1i16 2248198425U, // SQNEGv1i32 2248198425U, // SQNEGv1i64 2248198425U, // SQNEGv1i8 68725017U, // SQNEGv2i32 2216732953U, // SQNEGv2i64 69773593U, // SQNEGv4i16 2217781529U, // SQNEGv4i32 70822169U, // SQNEGv8i16 2218830105U, // SQNEGv8i8 369191329U, // SQRDMLAHi16_indexed 369191329U, // SQRDMLAHi32_indexed 369191329U, // SQRDMLAHv1i16 369191329U, // SQRDMLAHv1i32 2283334049U, // SQRDMLAHv2i32 2283334049U, // SQRDMLAHv2i32_indexed 136898977U, // SQRDMLAHv4i16 136898977U, // SQRDMLAHv4i16_indexed 137423265U, // SQRDMLAHv4i32 137423265U, // SQRDMLAHv4i32_indexed 2285431201U, // SQRDMLAHv8i16 2285431201U, // SQRDMLAHv8i16_indexed 369191909U, // SQRDMLSHi16_indexed 369191909U, // SQRDMLSHi32_indexed 369191909U, // SQRDMLSHv1i16 369191909U, // SQRDMLSHv1i32 2283334629U, // SQRDMLSHv2i32 2283334629U, // SQRDMLSHv2i32_indexed 136899557U, // SQRDMLSHv4i16 136899557U, // SQRDMLSHv4i16_indexed 137423845U, // SQRDMLSHv4i32 137423845U, // SQRDMLSHv4i32_indexed 2285431781U, // SQRDMLSHv8i16 2285431781U, // SQRDMLSHv8i16_indexed 100715238U, // SQRDMULHv1i16 100715238U, // SQRDMULHv1i16_indexed 100715238U, // SQRDMULHv1i32 100715238U, // SQRDMULHv1i32_indexed 2216209126U, // SQRDMULHv2i32 2216209126U, // SQRDMULHv2i32_indexed 69774054U, // SQRDMULHv4i16 69774054U, // SQRDMULHv4i16_indexed 70298342U, // SQRDMULHv4i32 70298342U, // SQRDMULHv4i32_indexed 2218306278U, // SQRDMULHv8i16 2218306278U, // SQRDMULHv8i16_indexed 68201885U, // SQRSHLv16i8 100715933U, // SQRSHLv1i16 100715933U, // SQRSHLv1i32 100715933U, // SQRSHLv1i64 100715933U, // SQRSHLv1i8 2216209821U, // SQRSHLv2i32 2216734109U, // SQRSHLv2i64 69774749U, // SQRSHLv4i16 70299037U, // SQRSHLv4i32 2218306973U, // SQRSHLv8i16 2218831261U, // SQRSHLv8i8 100716319U, // SQRSHRNb 100716319U, // SQRSHRNh 100716319U, // SQRSHRNs 2282807661U, // SQRSHRNv16i8_shift 2216210207U, // SQRSHRNv2i32_shift 69775135U, // SQRSHRNv4i16_shift 2284904813U, // SQRSHRNv4i32_shift 137945453U, // SQRSHRNv8i16_shift 2218831647U, // SQRSHRNv8i8_shift 100716380U, // SQRSHRUNb 100716380U, // SQRSHRUNh 100716380U, // SQRSHRUNs 2282807721U, // SQRSHRUNv16i8_shift 2216210268U, // SQRSHRUNv2i32_shift 69775196U, // SQRSHRUNv4i16_shift 2284904873U, // SQRSHRUNv4i32_shift 137945513U, // SQRSHRUNv8i16_shift 2218831708U, // SQRSHRUNv8i8_shift 100717425U, // SQSHLUb 100717425U, // SQSHLUd 100717425U, // SQSHLUh 100717425U, // SQSHLUs 68203377U, // SQSHLUv16i8_shift 2216211313U, // SQSHLUv2i32_shift 2216735601U, // SQSHLUv2i64_shift 69776241U, // SQSHLUv4i16_shift 70300529U, // SQSHLUv4i32_shift 2218308465U, // SQSHLUv8i16_shift 2218832753U, // SQSHLUv8i8_shift 100715919U, // SQSHLb 100715919U, // SQSHLd 100715919U, // SQSHLh 100715919U, // SQSHLs 68201871U, // SQSHLv16i8 68201871U, // SQSHLv16i8_shift 100715919U, // SQSHLv1i16 100715919U, // SQSHLv1i32 100715919U, // SQSHLv1i64 100715919U, // SQSHLv1i8 2216209807U, // SQSHLv2i32 2216209807U, // SQSHLv2i32_shift 2216734095U, // SQSHLv2i64 2216734095U, // SQSHLv2i64_shift 69774735U, // SQSHLv4i16 69774735U, // SQSHLv4i16_shift 70299023U, // SQSHLv4i32 70299023U, // SQSHLv4i32_shift 2218306959U, // SQSHLv8i16 2218306959U, // SQSHLv8i16_shift 2218831247U, // SQSHLv8i8 2218831247U, // SQSHLv8i8_shift 100716303U, // SQSHRNb 100716303U, // SQSHRNh 100716303U, // SQSHRNs 2282807643U, // SQSHRNv16i8_shift 2216210191U, // SQSHRNv2i32_shift 69775119U, // SQSHRNv4i16_shift 2284904795U, // SQSHRNv4i32_shift 137945435U, // SQSHRNv8i16_shift 2218831631U, // SQSHRNv8i8_shift 100716371U, // SQSHRUNb 100716371U, // SQSHRUNh 100716371U, // SQSHRUNs 2282807711U, // SQSHRUNv16i8_shift 2216210259U, // SQSHRUNv2i32_shift 69775187U, // SQSHRUNv4i16_shift 2284904863U, // SQSHRUNv4i32_shift 137945503U, // SQSHRUNv8i16_shift 2218831699U, // SQSHRUNv8i8_shift 167782084U, // SQSUB_ZI_B 201344708U, // SQSUB_ZI_D 239625924U, // SQSUB_ZI_H 268469956U, // SQSUB_ZI_S 167782084U, // SQSUB_ZZZ_B 201344708U, // SQSUB_ZZZ_D 2387109572U, // SQSUB_ZZZ_H 268469956U, // SQSUB_ZZZ_S 68200132U, // SQSUBv16i8 100714180U, // SQSUBv1i16 100714180U, // SQSUBv1i32 100714180U, // SQSUBv1i64 100714180U, // SQSUBv1i8 2216208068U, // SQSUBv2i32 2216732356U, // SQSUBv2i64 69772996U, // SQSUBv4i16 70297284U, // SQSUBv4i32 2218305220U, // SQSUBv8i16 2218829508U, // SQSUBv8i8 135324047U, // SQXTNv16i8 2248200005U, // SQXTNv1i16 2248200005U, // SQXTNv1i32 2248200005U, // SQXTNv1i8 2216210245U, // SQXTNv2i32 2217258821U, // SQXTNv4i16 2284904847U, // SQXTNv4i32 2285429135U, // SQXTNv8i16 71348037U, // SQXTNv8i8 135324084U, // SQXTUNv16i8 2248200038U, // SQXTUNv1i16 2248200038U, // SQXTUNv1i32 2248200038U, // SQXTUNv1i8 2216210278U, // SQXTUNv2i32 2217258854U, // SQXTUNv4i16 2284904884U, // SQXTUNv4i32 2285429172U, // SQXTUNv8i16 71348070U, // SQXTUNv8i8 68200433U, // SRHADDv16i8 2216208369U, // SRHADDv2i32 69773297U, // SRHADDv4i16 70297585U, // SRHADDv4i32 2218305521U, // SRHADDv8i16 2218829809U, // SRHADDv8i8 369192068U, // SRId 135326852U, // SRIv16i8_shift 2283334788U, // SRIv2i32_shift 2283859076U, // SRIv2i64_shift 136899716U, // SRIv4i16_shift 137424004U, // SRIv4i32_shift 2285431940U, // SRIv8i16_shift 2285956228U, // SRIv8i8_shift 68201901U, // SRSHLv16i8 100715949U, // SRSHLv1i64 2216209837U, // SRSHLv2i32 2216734125U, // SRSHLv2i64 69774765U, // SRSHLv4i16 70299053U, // SRSHLv4i32 2218306989U, // SRSHLv8i16 2218831277U, // SRSHLv8i8 100716794U, // SRSHRd 68202746U, // SRSHRv16i8_shift 2216210682U, // SRSHRv2i32_shift 2216734970U, // SRSHRv2i64_shift 69775610U, // SRSHRv4i16_shift 70299898U, // SRSHRv4i32_shift 2218307834U, // SRSHRv8i16_shift 2218832122U, // SRSHRv8i8_shift 369189634U, // SRSRAd 135324418U, // SRSRAv16i8_shift 2283332354U, // SRSRAv2i32_shift 2283856642U, // SRSRAv2i64_shift 136897282U, // SRSRAv4i16_shift 137421570U, // SRSRAv4i32_shift 2285429506U, // SRSRAv8i16_shift 2285953794U, // SRSRAv8i8_shift 70820085U, // SSHLLv16i8_shift 2216734151U, // SSHLLv2i32_shift 70299079U, // SSHLLv4i16_shift 69247221U, // SSHLLv4i32_shift 2217779445U, // SSHLLv8i16_shift 2218307015U, // SSHLLv8i8_shift 68201915U, // SSHLv16i8 100715963U, // SSHLv1i64 2216209851U, // SSHLv2i32 2216734139U, // SSHLv2i64 69774779U, // SSHLv4i16 70299067U, // SSHLv4i32 2218307003U, // SSHLv8i16 2218831291U, // SSHLv8i8 100716808U, // SSHRd 68202760U, // SSHRv16i8_shift 2216210696U, // SSHRv2i32_shift 2216734984U, // SSHRv2i64_shift 69775624U, // SSHRv4i16_shift 70299912U, // SSHRv4i32_shift 2218307848U, // SSHRv8i16_shift 2218832136U, // SSHRv8i8_shift 369189648U, // SSRAd 135324432U, // SSRAv16i8_shift 2283332368U, // SSRAv2i32_shift 2283856656U, // SSRAv2i64_shift 136897296U, // SSRAv4i16_shift 137421584U, // SSRAv4i32_shift 2285429520U, // SSRAv8i16_shift 2285953808U, // SSRAv8i8_shift 374997906U, // SST1B_D 878314386U, // SST1B_D_IMM 374997906U, // SST1B_D_SXTW 374997906U, // SST1B_D_UXTW 811213714U, // SST1B_S_IMM 375006098U, // SST1B_S_SXTW 375006098U, // SST1B_S_UXTW 374998886U, // SST1D 878315366U, // SST1D_IMM 374998886U, // SST1D_SCALED 374998886U, // SST1D_SXTW 374998886U, // SST1D_SXTW_SCALED 374998886U, // SST1D_UXTW 374998886U, // SST1D_UXTW_SCALED 374999380U, // SST1H_D 3025799508U, // SST1H_D_IMM 374999380U, // SST1H_D_SCALED 374999380U, // SST1H_D_SXTW 374999380U, // SST1H_D_SXTW_SCALED 374999380U, // SST1H_D_UXTW 374999380U, // SST1H_D_UXTW_SCALED 2958698836U, // SST1H_S_IMM 375007572U, // SST1H_S_SXTW 375007572U, // SST1H_S_SXTW_SCALED 375007572U, // SST1H_S_UXTW 375007572U, // SST1H_S_UXTW_SCALED 375002204U, // SST1W_D 878318684U, // SST1W_D_IMM 375002204U, // SST1W_D_SCALED 375002204U, // SST1W_D_SXTW 375002204U, // SST1W_D_SXTW_SCALED 375002204U, // SST1W_D_UXTW 375002204U, // SST1W_D_UXTW_SCALED 811218012U, // SST1W_IMM 375010396U, // SST1W_SXTW 375010396U, // SST1W_SXTW_SCALED 375010396U, // SST1W_UXTW 375010396U, // SST1W_UXTW_SCALED 70820037U, // SSUBLv16i8_v8i16 2216734014U, // SSUBLv2i32_v2i64 70298942U, // SSUBLv4i16_v4i32 69247173U, // SSUBLv4i32_v2i64 2217779397U, // SSUBLv8i16_v4i32 2218306878U, // SSUBLv8i8_v8i16 2218303966U, // SSUBWv16i8_v8i16 2216735886U, // SSUBWv2i32_v2i64 70300814U, // SSUBWv4i16_v4i32 2216731102U, // SSUBWv4i32_v2i64 70296030U, // SSUBWv8i16_v4i32 2218308750U, // SSUBWv8i8_v8i16 375022482U, // ST1B 374997906U, // ST1B_D 374997906U, // ST1B_D_IMM 375030674U, // ST1B_H 375030674U, // ST1B_H_IMM 375022482U, // ST1B_IMM 375006098U, // ST1B_S 375006098U, // ST1B_S_IMM 374998886U, // ST1D 374998886U, // ST1D_IMM 172102U, // ST1Fourv16b 13287494U, // ST1Fourv16b_POST 188486U, // ST1Fourv1d 13828166U, // ST1Fourv1d_POST 204870U, // ST1Fourv2d 13320262U, // ST1Fourv2d_POST 221254U, // ST1Fourv2s 13860934U, // ST1Fourv2s_POST 237638U, // ST1Fourv4h 13877318U, // ST1Fourv4h_POST 254022U, // ST1Fourv4s 13369414U, // ST1Fourv4s_POST 270406U, // ST1Fourv8b 13910086U, // ST1Fourv8b_POST 286790U, // ST1Fourv8h 13402182U, // ST1Fourv8h_POST 375032148U, // ST1H 374999380U, // ST1H_D 374999380U, // ST1H_D_IMM 375032148U, // ST1H_IMM 375007572U, // ST1H_S 375007572U, // ST1H_S_IMM 172102U, // ST1Onev16b 14336070U, // ST1Onev16b_POST 188486U, // ST1Onev1d 14876742U, // ST1Onev1d_POST 204870U, // ST1Onev2d 14368838U, // ST1Onev2d_POST 221254U, // ST1Onev2s 14909510U, // ST1Onev2s_POST 237638U, // ST1Onev4h 14925894U, // ST1Onev4h_POST 254022U, // ST1Onev4s 14417990U, // ST1Onev4s_POST 270406U, // ST1Onev8b 14958662U, // ST1Onev8b_POST 286790U, // ST1Onev8h 14450758U, // ST1Onev8h_POST 172102U, // ST1Threev16b 16957510U, // ST1Threev16b_POST 188486U, // ST1Threev1d 17498182U, // ST1Threev1d_POST 204870U, // ST1Threev2d 16990278U, // ST1Threev2d_POST 221254U, // ST1Threev2s 17530950U, // ST1Threev2s_POST 237638U, // ST1Threev4h 17547334U, // ST1Threev4h_POST 254022U, // ST1Threev4s 17039430U, // ST1Threev4s_POST 270406U, // ST1Threev8b 17580102U, // ST1Threev8b_POST 286790U, // ST1Threev8h 17072198U, // ST1Threev8h_POST 172102U, // ST1Twov16b 13811782U, // ST1Twov16b_POST 188486U, // ST1Twov1d 14352454U, // ST1Twov1d_POST 204870U, // ST1Twov2d 13844550U, // ST1Twov2d_POST 221254U, // ST1Twov2s 14385222U, // ST1Twov2s_POST 237638U, // ST1Twov4h 14401606U, // ST1Twov4h_POST 254022U, // ST1Twov4s 13893702U, // ST1Twov4s_POST 270406U, // ST1Twov8b 14434374U, // ST1Twov8b_POST 286790U, // ST1Twov8h 13926470U, // ST1Twov8h_POST 375010396U, // ST1W 375002204U, // ST1W_D 375002204U, // ST1W_D_IMM 375010396U, // ST1W_IMM 409670U, // ST1i16 1404346438U, // ST1i16_POST 417862U, // ST1i32 1437917254U, // ST1i32_POST 426054U, // ST1i64 1471488070U, // ST1i64_POST 434246U, // ST1i8 1505058886U, // ST1i8_POST 375022511U, // ST2B 375022511U, // ST2B_IMM 374998898U, // ST2D 374998898U, // ST2D_IMM 375032177U, // ST2H 375032177U, // ST2H_IMM 172505U, // ST2Twov16b 13812185U, // ST2Twov16b_POST 205273U, // ST2Twov2d 13844953U, // ST2Twov2d_POST 221657U, // ST2Twov2s 14385625U, // ST2Twov2s_POST 238041U, // ST2Twov4h 14402009U, // ST2Twov4h_POST 254425U, // ST2Twov4s 13894105U, // ST2Twov4s_POST 270809U, // ST2Twov8b 14434777U, // ST2Twov8b_POST 287193U, // ST2Twov8h 13926873U, // ST2Twov8h_POST 375010416U, // ST2W 375010416U, // ST2W_IMM 410073U, // ST2i16 1437901273U, // ST2i16_POST 418265U, // ST2i32 1471472089U, // ST2i32_POST 426457U, // ST2i64 1538597337U, // ST2i64_POST 434649U, // ST2i8 1404395993U, // ST2i8_POST 375022532U, // ST3B 375022532U, // ST3B_IMM 374998910U, // ST3D 374998910U, // ST3D_IMM 375032189U, // ST3H 375032189U, // ST3H_IMM 172571U, // ST3Threev16b 16957979U, // ST3Threev16b_POST 205339U, // ST3Threev2d 16990747U, // ST3Threev2d_POST 221723U, // ST3Threev2s 17531419U, // ST3Threev2s_POST 238107U, // ST3Threev4h 17547803U, // ST3Threev4h_POST 254491U, // ST3Threev4s 17039899U, // ST3Threev4s_POST 270875U, // ST3Threev8b 17580571U, // ST3Threev8b_POST 287259U, // ST3Threev8h 17072667U, // ST3Threev8h_POST 375010428U, // ST3W 375010428U, // ST3W_IMM 410139U, // ST3i16 1572119067U, // ST3i16_POST 418331U, // ST3i32 1605689883U, // ST3i32_POST 426523U, // ST3i64 1639260699U, // ST3i64_POST 434715U, // ST3i8 1672831515U, // ST3i8_POST 375022544U, // ST4B 375022544U, // ST4B_IMM 374998922U, // ST4D 374998922U, // ST4D_IMM 172588U, // ST4Fourv16b 13287980U, // ST4Fourv16b_POST 205356U, // ST4Fourv2d 13320748U, // ST4Fourv2d_POST 221740U, // ST4Fourv2s 13861420U, // ST4Fourv2s_POST 238124U, // ST4Fourv4h 13877804U, // ST4Fourv4h_POST 254508U, // ST4Fourv4s 13369900U, // ST4Fourv4s_POST 270892U, // ST4Fourv8b 13910572U, // ST4Fourv8b_POST 287276U, // ST4Fourv8h 13402668U, // ST4Fourv8h_POST 375032201U, // ST4H 375032201U, // ST4H_IMM 375010440U, // ST4W 375010440U, // ST4W_IMM 410156U, // ST4i16 1471455788U, // ST4i16_POST 418348U, // ST4i32 1538581036U, // ST4i32_POST 426540U, // ST4i64 1706369580U, // ST4i64_POST 434732U, // ST4i8 1437950508U, // ST4i8_POST 2253964715U, // STLLRB 2253966166U, // STLLRH 2253967648U, // STLLRW 2253967648U, // STLLRX 2253964723U, // STLRB 2253966174U, // STLRH 2253967661U, // STLRW 2253967661U, // STLRX 106481125U, // STLURBi 106482576U, // STLURHi 106484110U, // STLURWi 106484110U, // STLURXi 100716685U, // STLXPW 100716685U, // STLXPX 2248197644U, // STLXRB 2248199095U, // STLXRH 2248200645U, // STLXRW 2248200645U, // STLXRX 2248200251U, // STNPDi 2248200251U, // STNPQi 2248200251U, // STNPSi 2248200251U, // STNPWi 2248200251U, // STNPXi 375022474U, // STNT1B_ZRI 375022474U, // STNT1B_ZRR 374998878U, // STNT1D_ZRI 374998878U, // STNT1D_ZRR 375032140U, // STNT1H_ZRI 375032140U, // STNT1H_ZRR 375010388U, // STNT1W_ZRI 375010388U, // STNT1W_ZRR 2248200283U, // STPDi 2516676699U, // STPDpost 2516676699U, // STPDpre 2248200283U, // STPQi 2516676699U, // STPQpost 2516676699U, // STPQpre 2248200283U, // STPSi 2516676699U, // STPSpost 2516676699U, // STPSpre 2248200283U, // STPWi 2516676699U, // STPWpost 2516676699U, // STPWpre 2248200283U, // STPXi 2516676699U, // STPXpost 2516676699U, // STPXpre 374957521U, // STRBBpost 374957521U, // STRBBpre 106481105U, // STRBBroW 106481105U, // STRBBroX 106481105U, // STRBBui 374960503U, // STRBpost 374960503U, // STRBpre 106484087U, // STRBroW 106484087U, // STRBroX 106484087U, // STRBui 374960503U, // STRDpost 374960503U, // STRDpre 106484087U, // STRDroW 106484087U, // STRDroX 106484087U, // STRDui 374958972U, // STRHHpost 374958972U, // STRHHpre 106482556U, // STRHHroW 106482556U, // STRHHroX 106482556U, // STRHHui 374960503U, // STRHpost 374960503U, // STRHpre 106484087U, // STRHroW 106484087U, // STRHroX 106484087U, // STRHui 374960503U, // STRQpost 374960503U, // STRQpre 106484087U, // STRQroW 106484087U, // STRQroX 106484087U, // STRQui 374960503U, // STRSpost 374960503U, // STRSpre 106484087U, // STRSroW 106484087U, // STRSroX 106484087U, // STRSui 374960503U, // STRWpost 374960503U, // STRWpre 106484087U, // STRWroW 106484087U, // STRWroX 106484087U, // STRWui 374960503U, // STRXpost 374960503U, // STRXpre 106484087U, // STRXroW 106484087U, // STRXroX 106484087U, // STRXui 106803575U, // STR_PXI 106803575U, // STR_ZXI 106481111U, // STTRBi 106482562U, // STTRHi 106484092U, // STTRWi 106484092U, // STTRXi 106481142U, // STURBBi 106484125U, // STURBi 106484125U, // STURDi 106482593U, // STURHHi 106484125U, // STURHi 106484125U, // STURQi 106484125U, // STURSi 106484125U, // STURWi 106484125U, // STURXi 100716692U, // STXPW 100716692U, // STXPX 2248197652U, // STXRB 2248199103U, // STXRH 2248200652U, // STXRW 2248200652U, // STXRX 2216210137U, // SUBHNv2i64_v2i32 2284904778U, // SUBHNv2i64_v4i32 69775065U, // SUBHNv4i32_v4i16 137945418U, // SUBHNv4i32_v8i16 2282807626U, // SUBHNv8i16_v16i8 2218831577U, // SUBHNv8i16_v8i8 167784668U, // SUBR_ZI_B 201347292U, // SUBR_ZI_D 239628508U, // SUBR_ZI_H 268472540U, // SUBR_ZI_S 302002396U, // SUBR_ZPmZ_B 302010588U, // SUBR_ZPmZ_D 2186309852U, // SUBR_ZPmZ_H 302026972U, // SUBR_ZPmZ_S 100717066U, // SUBSWri 0U, // SUBSWrr 100717066U, // SUBSWrs 100717066U, // SUBSWrx 100717066U, // SUBSXri 0U, // SUBSXrr 100717066U, // SUBSXrs 100717066U, // SUBSXrx 100717066U, // SUBSXrx64 100714146U, // SUBWri 0U, // SUBWrr 100714146U, // SUBWrs 100714146U, // SUBWrx 100714146U, // SUBXri 0U, // SUBXrr 100714146U, // SUBXrs 100714146U, // SUBXrx 100714146U, // SUBXrx64 167782050U, // SUB_ZI_B 201344674U, // SUB_ZI_D 239625890U, // SUB_ZI_H 268469922U, // SUB_ZI_S 301999778U, // SUB_ZPmZ_B 302007970U, // SUB_ZPmZ_D 2186307234U, // SUB_ZPmZ_H 302024354U, // SUB_ZPmZ_S 167782050U, // SUB_ZZZ_B 201344674U, // SUB_ZZZ_D 2387109538U, // SUB_ZZZ_H 268469922U, // SUB_ZZZ_S 68200098U, // SUBv16i8 100714146U, // SUBv1i64 2216208034U, // SUBv2i32 2216732322U, // SUBv2i64 69772962U, // SUBv4i16 70297250U, // SUBv4i32 2218305186U, // SUBv8i16 2218829474U, // SUBv8i8 2415938650U, // SUNPKHI_ZZ_D 27290714U, // SUNPKHI_ZZ_H 2717944922U, // SUNPKHI_ZZ_S 2415939470U, // SUNPKLO_ZZ_D 27291534U, // SUNPKLO_ZZ_H 2717945742U, // SUNPKLO_ZZ_S 135325734U, // SUQADDv16i8 2516674598U, // SUQADDv1i16 2516674598U, // SUQADDv1i32 2516674598U, // SUQADDv1i64 2516674598U, // SUQADDv1i8 135850022U, // SUQADDv2i32 2283857958U, // SUQADDv2i64 136898598U, // SUQADDv4i16 2284906534U, // SUQADDv4i32 137947174U, // SUQADDv8i16 2285955110U, // SUQADDv8i8 75579U, // SVC 973169651U, // SWPAB 973171135U, // SWPAH 973169853U, // SWPALB 973171283U, // SWPALH 973171948U, // SWPALW 973171948U, // SWPALX 973169381U, // SWPAW 973169381U, // SWPAX 973170041U, // SWPB 973171492U, // SWPH 973169950U, // SWPLB 973171380U, // SWPLH 973172243U, // SWPLW 973172243U, // SWPLX 973172838U, // SWPW 973172838U, // SWPX 18069U, // SXTB_ZPmZ_D 2181588629U, // SXTB_ZPmZ_H 34453U, // SXTB_ZPmZ_S 19494U, // SXTH_ZPmZ_D 35878U, // SXTH_ZPmZ_S 21815U, // SXTW_ZPmZ_D 100716107U, // SYSLxt 1711329984U, // SYSxt 1744842025U, // TBL_ZZZ_B 1778404649U, // TBL_ZZZ_D 28863785U, // TBL_ZZZ_H 1811975465U, // TBL_ZZZ_S 1846586665U, // TBLv16i8Four 1846586665U, // TBLv16i8One 1846586665U, // TBLv16i8Three 1846586665U, // TBLv16i8Two 3997216041U, // TBLv8i8Four 3997216041U, // TBLv8i8One 3997216041U, // TBLv8i8Three 3997216041U, // TBLv8i8Two 100718059U, // TBNZW 100718059U, // TBNZX 1880159597U, // TBXv16i8Four 1880159597U, // TBXv16i8One 1880159597U, // TBXv16i8Three 1880159597U, // TBXv16i8Two 4030788973U, // TBXv8i8Four 4030788973U, // TBXv8i8One 4030788973U, // TBXv8i8Three 4030788973U, // TBXv8i8Two 100718043U, // TBZW 100718043U, // TBZX 0U, // TCRETURNdi 0U, // TCRETURNri 6346239U, // TLSDESCCALL 0U, // TLSDESC_CALLSEQ 167780389U, // TRN1_PPP_B 201343013U, // TRN1_PPP_D 2387107877U, // TRN1_PPP_H 268468261U, // TRN1_PPP_S 167780389U, // TRN1_ZZZ_B 201343013U, // TRN1_ZZZ_D 2387107877U, // TRN1_ZZZ_H 268468261U, // TRN1_ZZZ_S 68198437U, // TRN1v16i8 2216206373U, // TRN1v2i32 2216730661U, // TRN1v2i64 69771301U, // TRN1v4i16 70295589U, // TRN1v4i32 2218303525U, // TRN1v8i16 2218827813U, // TRN1v8i8 167780737U, // TRN2_PPP_B 201343361U, // TRN2_PPP_D 2387108225U, // TRN2_PPP_H 268468609U, // TRN2_PPP_S 167780737U, // TRN2_ZZZ_B 201343361U, // TRN2_ZZZ_D 2387108225U, // TRN2_ZZZ_H 268468609U, // TRN2_ZZZ_S 68198785U, // TRN2v16i8 2216206721U, // TRN2v2i32 2216731009U, // TRN2v2i64 69771649U, // TRN2v4i16 70295937U, // TRN2v4i32 2218303873U, // TRN2v8i16 2218828161U, // TRN2v8i8 116346U, // TSB 137945251U, // UABALv16i8_v8i16 2283859113U, // UABALv2i32_v2i64 137424041U, // UABALv4i16_v4i32 136372387U, // UABALv4i32_v2i64 2284904611U, // UABALv8i16_v4i32 2285431977U, // UABALv8i8_v8i16 135324275U, // UABAv16i8 2283332211U, // UABAv2i32 136897139U, // UABAv4i16 137421427U, // UABAv4i32 2285429363U, // UABAv8i16 2285953651U, // UABAv8i8 70820061U, // UABDLv16i8_v8i16 2216734035U, // UABDLv2i32_v2i64 70298963U, // UABDLv4i16_v4i32 69247197U, // UABDLv4i32_v2i64 2217779421U, // UABDLv8i16_v4i32 2218306899U, // UABDLv8i8_v8i16 302000048U, // UABD_ZPmZ_B 302008240U, // UABD_ZPmZ_D 2186307504U, // UABD_ZPmZ_H 302024624U, // UABD_ZPmZ_S 68200368U, // UABDv16i8 2216208304U, // UABDv2i32 69773232U, // UABDv4i16 70297520U, // UABDv4i32 2218305456U, // UABDv8i16 2218829744U, // UABDv8i8 137949161U, // UADALPv16i8_v8i16 162066409U, // UADALPv2i32_v1i64 135852009U, // UADALPv4i16_v2i32 2283859945U, // UADALPv4i32_v2i64 137424873U, // UADALPv8i16_v4i32 2284384233U, // UADALPv8i8_v4i16 70823929U, // UADDLPv16i8_v8i16 94941177U, // UADDLPv2i32_v1i64 68726777U, // UADDLPv4i16_v2i32 2216734713U, // UADDLPv4i32_v2i64 70299641U, // UADDLPv8i16_v4i32 2217259001U, // UADDLPv8i8_v4i16 67163091U, // UADDLVv16i8v 67163091U, // UADDLVv4i16v 2214646739U, // UADDLVv4i32v 67163091U, // UADDLVv8i16v 2214646739U, // UADDLVv8i8v 70820077U, // UADDLv16i8_v8i16 2216734073U, // UADDLv2i32_v2i64 70299001U, // UADDLv4i16_v4i32 69247213U, // UADDLv4i32_v2i64 2217779437U, // UADDLv8i16_v4i32 2218306937U, // UADDLv8i8_v8i16 302044071U, // UADDV_VPZ_B 302044071U, // UADDV_VPZ_D 302044071U, // UADDV_VPZ_H 302044071U, // UADDV_VPZ_S 2218303990U, // UADDWv16i8_v8i16 2216735948U, // UADDWv2i32_v2i64 70300876U, // UADDWv4i16_v4i32 2216731126U, // UADDWv4i32_v2i64 70296054U, // UADDWv8i16_v4i32 2218308812U, // UADDWv8i8_v8i16 100716199U, // UBFMWri 100716199U, // UBFMXri 100714764U, // UCVTFSWDri 100714764U, // UCVTFSWHri 100714764U, // UCVTFSWSri 100714764U, // UCVTFSXDri 100714764U, // UCVTFSXHri 100714764U, // UCVTFSXSri 2248198412U, // UCVTFUWDri 2248198412U, // UCVTFUWHri 2248198412U, // UCVTFUWSri 2248198412U, // UCVTFUXDri 2248198412U, // UCVTFUXHri 2248198412U, // UCVTFUXSri 18700U, // UCVTF_ZPmZ_DtoD 2181589260U, // UCVTF_ZPmZ_DtoH 35084U, // UCVTF_ZPmZ_DtoS 2181589260U, // UCVTF_ZPmZ_HtoH 18700U, // UCVTF_ZPmZ_StoD 2181589260U, // UCVTF_ZPmZ_StoH 35084U, // UCVTF_ZPmZ_StoS 100714764U, // UCVTFd 100714764U, // UCVTFh 100714764U, // UCVTFs 2248198412U, // UCVTFv1i16 2248198412U, // UCVTFv1i32 2248198412U, // UCVTFv1i64 68725004U, // UCVTFv2f32 2216732940U, // UCVTFv2f64 2216208652U, // UCVTFv2i32_shift 2216732940U, // UCVTFv2i64_shift 69773580U, // UCVTFv4f16 2217781516U, // UCVTFv4f32 69773580U, // UCVTFv4i16_shift 70297868U, // UCVTFv4i32_shift 70822156U, // UCVTFv8f16 2218305804U, // UCVTFv8i16_shift 302010801U, // UDIVR_ZPmZ_D 302027185U, // UDIVR_ZPmZ_S 100717509U, // UDIVWr 100717509U, // UDIVXr 302011333U, // UDIV_ZPmZ_D 302027717U, // UDIV_ZPmZ_S 3422573363U, // UDOT_ZZZI_D 3456144179U, // UDOT_ZZZI_S 3422573363U, // UDOT_ZZZ_D 3456144179U, // UDOT_ZZZ_S 137425715U, // UDOTlanev16i8 2283336499U, // UDOTlanev8i8 137425715U, // UDOTv16i8 2283336499U, // UDOTv8i8 68200456U, // UHADDv16i8 2216208392U, // UHADDv2i32 69773320U, // UHADDv4i16 70297608U, // UHADDv4i32 2218305544U, // UHADDv8i16 2218829832U, // UHADDv8i8 68200110U, // UHSUBv16i8 2216208046U, // UHSUBv2i32 69772974U, // UHSUBv4i16 70297262U, // UHSUBv4i32 2218305198U, // UHSUBv8i16 2218829486U, // UHSUBv8i8 100715882U, // UMADDLrrr 68202624U, // UMAXPv16i8 2216210560U, // UMAXPv2i32 69775488U, // UMAXPv4i16 70299776U, // UMAXPv4i32 2218307712U, // UMAXPv8i16 2218832000U, // UMAXPv8i8 302044207U, // UMAXV_VPZ_B 302044207U, // UMAXV_VPZ_D 302044207U, // UMAXV_VPZ_H 302044207U, // UMAXV_VPZ_S 67163183U, // UMAXVv16i8v 67163183U, // UMAXVv4i16v 2214646831U, // UMAXVv4i32v 67163183U, // UMAXVv8i16v 2214646831U, // UMAXVv8i8v 167785831U, // UMAX_ZI_B 201348455U, // UMAX_ZI_D 239629671U, // UMAX_ZI_H 268473703U, // UMAX_ZI_S 302003559U, // UMAX_ZPmZ_B 302011751U, // UMAX_ZPmZ_D 2186311015U, // UMAX_ZPmZ_H 302028135U, // UMAX_ZPmZ_S 68203879U, // UMAXv16i8 2216211815U, // UMAXv2i32 69776743U, // UMAXv4i16 70301031U, // UMAXv4i32 2218308967U, // UMAXv8i16 2218833255U, // UMAXv8i8 68202548U, // UMINPv16i8 2216210484U, // UMINPv2i32 69775412U, // UMINPv4i16 70299700U, // UMINPv4i32 2218307636U, // UMINPv8i16 2218831924U, // UMINPv8i8 302044155U, // UMINV_VPZ_B 302044155U, // UMINV_VPZ_D 302044155U, // UMINV_VPZ_H 302044155U, // UMINV_VPZ_S 67163131U, // UMINVv16i8v 67163131U, // UMINVv4i16v 2214646779U, // UMINVv4i32v 67163131U, // UMINVv8i16v 2214646779U, // UMINVv8i8v 167784184U, // UMIN_ZI_B 201346808U, // UMIN_ZI_D 239628024U, // UMIN_ZI_H 268472056U, // UMIN_ZI_S 302001912U, // UMIN_ZPmZ_B 302010104U, // UMIN_ZPmZ_D 2186309368U, // UMIN_ZPmZ_H 302026488U, // UMIN_ZPmZ_S 68202232U, // UMINv16i8 2216210168U, // UMINv2i32 69775096U, // UMINv4i16 70299384U, // UMINv4i32 2218307320U, // UMINv8i16 2218831608U, // UMINv8i8 137945277U, // UMLALv16i8_v8i16 2283859145U, // UMLALv2i32_indexed 2283859145U, // UMLALv2i32_v2i64 137424073U, // UMLALv4i16_indexed 137424073U, // UMLALv4i16_v4i32 136372413U, // UMLALv4i32_indexed 136372413U, // UMLALv4i32_v2i64 2284904637U, // UMLALv8i16_indexed 2284904637U, // UMLALv8i16_v4i32 2285432009U, // UMLALv8i8_v8i16 137945401U, // UMLSLv16i8_v8i16 2283859524U, // UMLSLv2i32_indexed 2283859524U, // UMLSLv2i32_v2i64 137424452U, // UMLSLv4i16_indexed 137424452U, // UMLSLv4i16_v4i32 136372537U, // UMLSLv4i32_indexed 136372537U, // UMLSLv4i32_v2i64 2284904761U, // UMLSLv8i16_indexed 2284904761U, // UMLSLv8i16_v4i32 2285432388U, // UMLSLv8i8_v8i16 67163157U, // UMOVvi16 2214646805U, // UMOVvi32 67163157U, // UMOVvi64 2214646805U, // UMOVvi8 100715830U, // UMSUBLrrr 302000887U, // UMULH_ZPmZ_B 302009079U, // UMULH_ZPmZ_D 2186308343U, // UMULH_ZPmZ_H 302025463U, // UMULH_ZPmZ_S 100715255U, // UMULHrr 70820127U, // UMULLv16i8_v8i16 2216734188U, // UMULLv2i32_indexed 2216734188U, // UMULLv2i32_v2i64 70299116U, // UMULLv4i16_indexed 70299116U, // UMULLv4i16_v4i32 69247263U, // UMULLv4i32_indexed 69247263U, // UMULLv4i32_v2i64 2217779487U, // UMULLv8i16_indexed 2217779487U, // UMULLv8i16_v4i32 2218307052U, // UMULLv8i8_v8i16 167782439U, // UQADD_ZI_B 201345063U, // UQADD_ZI_D 239626279U, // UQADD_ZI_H 268470311U, // UQADD_ZI_S 167782439U, // UQADD_ZZZ_B 201345063U, // UQADD_ZZZ_D 2387109927U, // UQADD_ZZZ_H 268470311U, // UQADD_ZZZ_S 68200487U, // UQADDv16i8 100714535U, // UQADDv1i16 100714535U, // UQADDv1i32 100714535U, // UQADDv1i64 100714535U, // UQADDv1i8 2216208423U, // UQADDv2i32 2216732711U, // UQADDv2i64 69773351U, // UQADDv4i16 70297639U, // UQADDv4i32 2218305575U, // UQADDv8i16 2218829863U, // UQADDv8i8 536921173U, // UQDECB_WPiI 536921173U, // UQDECB_XPiI 536922053U, // UQDECD_WPiI 536922053U, // UQDECD_XPiI 536889285U, // UQDECD_ZPiI 536922637U, // UQDECH_WPiI 536922637U, // UQDECH_XPiI 6842893U, // UQDECH_ZPiI 2315308989U, // UQDECP_WP_B 2348863421U, // UQDECP_WP_D 2717962173U, // UQDECP_WP_H 2415972285U, // UQDECP_WP_S 2315308989U, // UQDECP_XP_B 2348863421U, // UQDECP_XP_D 2717962173U, // UQDECP_XP_H 2415972285U, // UQDECP_XP_S 2147504061U, // UQDECP_ZP_D 604532669U, // UQDECP_ZP_H 2147520445U, // UQDECP_ZP_S 536925357U, // UQDECW_WPiI 536925357U, // UQDECW_XPiI 536908973U, // UQDECW_ZPiI 536921189U, // UQINCB_WPiI 536921189U, // UQINCB_XPiI 536922069U, // UQINCD_WPiI 536922069U, // UQINCD_XPiI 536889301U, // UQINCD_ZPiI 536922653U, // UQINCH_WPiI 536922653U, // UQINCH_XPiI 6842909U, // UQINCH_ZPiI 2315309005U, // UQINCP_WP_B 2348863437U, // UQINCP_WP_D 2717962189U, // UQINCP_WP_H 2415972301U, // UQINCP_WP_S 2315309005U, // UQINCP_XP_B 2348863437U, // UQINCP_XP_D 2717962189U, // UQINCP_XP_H 2415972301U, // UQINCP_XP_S 2147504077U, // UQINCP_ZP_D 604532685U, // UQINCP_ZP_H 2147520461U, // UQINCP_ZP_S 536925373U, // UQINCW_WPiI 536925373U, // UQINCW_XPiI 536908989U, // UQINCW_ZPiI 68201893U, // UQRSHLv16i8 100715941U, // UQRSHLv1i16 100715941U, // UQRSHLv1i32 100715941U, // UQRSHLv1i64 100715941U, // UQRSHLv1i8 2216209829U, // UQRSHLv2i32 2216734117U, // UQRSHLv2i64 69774757U, // UQRSHLv4i16 70299045U, // UQRSHLv4i32 2218306981U, // UQRSHLv8i16 2218831269U, // UQRSHLv8i8 100716328U, // UQRSHRNb 100716328U, // UQRSHRNh 100716328U, // UQRSHRNs 2282807671U, // UQRSHRNv16i8_shift 2216210216U, // UQRSHRNv2i32_shift 69775144U, // UQRSHRNv4i16_shift 2284904823U, // UQRSHRNv4i32_shift 137945463U, // UQRSHRNv8i16_shift 2218831656U, // UQRSHRNv8i8_shift 100715926U, // UQSHLb 100715926U, // UQSHLd 100715926U, // UQSHLh 100715926U, // UQSHLs 68201878U, // UQSHLv16i8 68201878U, // UQSHLv16i8_shift 100715926U, // UQSHLv1i16 100715926U, // UQSHLv1i32 100715926U, // UQSHLv1i64 100715926U, // UQSHLv1i8 2216209814U, // UQSHLv2i32 2216209814U, // UQSHLv2i32_shift 2216734102U, // UQSHLv2i64 2216734102U, // UQSHLv2i64_shift 69774742U, // UQSHLv4i16 69774742U, // UQSHLv4i16_shift 70299030U, // UQSHLv4i32 70299030U, // UQSHLv4i32_shift 2218306966U, // UQSHLv8i16 2218306966U, // UQSHLv8i16_shift 2218831254U, // UQSHLv8i8 2218831254U, // UQSHLv8i8_shift 100716311U, // UQSHRNb 100716311U, // UQSHRNh 100716311U, // UQSHRNs 2282807652U, // UQSHRNv16i8_shift 2216210199U, // UQSHRNv2i32_shift 69775127U, // UQSHRNv4i16_shift 2284904804U, // UQSHRNv4i32_shift 137945444U, // UQSHRNv8i16_shift 2218831639U, // UQSHRNv8i8_shift 167782091U, // UQSUB_ZI_B 201344715U, // UQSUB_ZI_D 239625931U, // UQSUB_ZI_H 268469963U, // UQSUB_ZI_S 167782091U, // UQSUB_ZZZ_B 201344715U, // UQSUB_ZZZ_D 2387109579U, // UQSUB_ZZZ_H 268469963U, // UQSUB_ZZZ_S 68200139U, // UQSUBv16i8 100714187U, // UQSUBv1i16 100714187U, // UQSUBv1i32 100714187U, // UQSUBv1i64 100714187U, // UQSUBv1i8 2216208075U, // UQSUBv2i32 2216732363U, // UQSUBv2i64 69773003U, // UQSUBv4i16 70297291U, // UQSUBv4i32 2218305227U, // UQSUBv8i16 2218829515U, // UQSUBv8i8 135324055U, // UQXTNv16i8 2248200012U, // UQXTNv1i16 2248200012U, // UQXTNv1i32 2248200012U, // UQXTNv1i8 2216210252U, // UQXTNv2i32 2217258828U, // UQXTNv4i16 2284904855U, // UQXTNv4i32 2285429143U, // UQXTNv8i16 71348044U, // UQXTNv8i8 68724924U, // URECPEv2i32 2217781436U, // URECPEv4i32 68200441U, // URHADDv16i8 2216208377U, // URHADDv2i32 69773305U, // URHADDv4i16 70297593U, // URHADDv4i32 2218305529U, // URHADDv8i16 2218829817U, // URHADDv8i8 68201908U, // URSHLv16i8 100715956U, // URSHLv1i64 2216209844U, // URSHLv2i32 2216734132U, // URSHLv2i64 69774772U, // URSHLv4i16 70299060U, // URSHLv4i32 2218306996U, // URSHLv8i16 2218831284U, // URSHLv8i8 100716801U, // URSHRd 68202753U, // URSHRv16i8_shift 2216210689U, // URSHRv2i32_shift 2216734977U, // URSHRv2i64_shift 69775617U, // URSHRv4i16_shift 70299905U, // URSHRv4i32_shift 2218307841U, // URSHRv8i16_shift 2218832129U, // URSHRv8i8_shift 68724970U, // URSQRTEv2i32 2217781482U, // URSQRTEv4i32 369189641U, // URSRAd 135324425U, // URSRAv16i8_shift 2283332361U, // URSRAv2i32_shift 2283856649U, // URSRAv2i64_shift 136897289U, // URSRAv4i16_shift 137421577U, // URSRAv4i32_shift 2285429513U, // URSRAv8i16_shift 2285953801U, // URSRAv8i8_shift 70820093U, // USHLLv16i8_shift 2216734158U, // USHLLv2i32_shift 70299086U, // USHLLv4i16_shift 69247229U, // USHLLv4i32_shift 2217779453U, // USHLLv8i16_shift 2218307022U, // USHLLv8i8_shift 68201921U, // USHLv16i8 100715969U, // USHLv1i64 2216209857U, // USHLv2i32 2216734145U, // USHLv2i64 69774785U, // USHLv4i16 70299073U, // USHLv4i32 2218307009U, // USHLv8i16 2218831297U, // USHLv8i8 100716814U, // USHRd 68202766U, // USHRv16i8_shift 2216210702U, // USHRv2i32_shift 2216734990U, // USHRv2i64_shift 69775630U, // USHRv4i16_shift 70299918U, // USHRv4i32_shift 2218307854U, // USHRv8i16_shift 2218832142U, // USHRv8i8_shift 135325726U, // USQADDv16i8 2516674590U, // USQADDv1i16 2516674590U, // USQADDv1i32 2516674590U, // USQADDv1i64 2516674590U, // USQADDv1i8 135850014U, // USQADDv2i32 2283857950U, // USQADDv2i64 136898590U, // USQADDv4i16 2284906526U, // USQADDv4i32 137947166U, // USQADDv8i16 2285955102U, // USQADDv8i8 369189654U, // USRAd 135324438U, // USRAv16i8_shift 2283332374U, // USRAv2i32_shift 2283856662U, // USRAv2i64_shift 136897302U, // USRAv4i16_shift 137421590U, // USRAv4i32_shift 2285429526U, // USRAv8i16_shift 2285953814U, // USRAv8i8_shift 70820045U, // USUBLv16i8_v8i16 2216734021U, // USUBLv2i32_v2i64 70298949U, // USUBLv4i16_v4i32 69247181U, // USUBLv4i32_v2i64 2217779405U, // USUBLv8i16_v4i32 2218306885U, // USUBLv8i8_v8i16 2218303974U, // USUBWv16i8_v8i16 2216735893U, // USUBWv2i32_v2i64 70300821U, // USUBWv4i16_v4i32 2216731110U, // USUBWv4i32_v2i64 70296038U, // USUBWv8i16_v4i32 2218308757U, // USUBWv8i8_v8i16 2415938659U, // UUNPKHI_ZZ_D 27290723U, // UUNPKHI_ZZ_H 2717944931U, // UUNPKHI_ZZ_S 2415939479U, // UUNPKLO_ZZ_D 27291543U, // UUNPKLO_ZZ_H 2717945751U, // UUNPKLO_ZZ_S 18075U, // UXTB_ZPmZ_D 2181588635U, // UXTB_ZPmZ_H 34459U, // UXTB_ZPmZ_S 19500U, // UXTH_ZPmZ_D 35884U, // UXTH_ZPmZ_S 21821U, // UXTW_ZPmZ_D 167780401U, // UZP1_PPP_B 201343025U, // UZP1_PPP_D 2387107889U, // UZP1_PPP_H 268468273U, // UZP1_PPP_S 167780401U, // UZP1_ZZZ_B 201343025U, // UZP1_ZZZ_D 2387107889U, // UZP1_ZZZ_H 268468273U, // UZP1_ZZZ_S 68198449U, // UZP1v16i8 2216206385U, // UZP1v2i32 2216730673U, // UZP1v2i64 69771313U, // UZP1v4i16 70295601U, // UZP1v4i32 2218303537U, // UZP1v8i16 2218827825U, // UZP1v8i8 167780812U, // UZP2_PPP_B 201343436U, // UZP2_PPP_D 2387108300U, // UZP2_PPP_H 268468684U, // UZP2_PPP_S 167780812U, // UZP2_ZZZ_B 201343436U, // UZP2_ZZZ_D 2387108300U, // UZP2_ZZZ_H 268468684U, // UZP2_ZZZ_S 68198860U, // UZP2v16i8 2216206796U, // UZP2v2i32 2216731084U, // UZP2v2i64 69771724U, // UZP2v4i16 70296012U, // UZP2v4i32 2218303948U, // UZP2v8i16 2218828236U, // UZP2v8i8 100673670U, // WHILELE_PWW_B 100681862U, // WHILELE_PWW_D 242772102U, // WHILELE_PWW_H 100698246U, // WHILELE_PWW_S 100673670U, // WHILELE_PXX_B 100681862U, // WHILELE_PXX_D 242772102U, // WHILELE_PXX_H 100698246U, // WHILELE_PXX_S 100675452U, // WHILELO_PWW_B 100683644U, // WHILELO_PWW_D 242773884U, // WHILELO_PWW_H 100700028U, // WHILELO_PWW_S 100675452U, // WHILELO_PXX_B 100683644U, // WHILELO_PXX_D 242773884U, // WHILELO_PXX_H 100700028U, // WHILELO_PXX_S 100676169U, // WHILELS_PWW_B 100684361U, // WHILELS_PWW_D 242774601U, // WHILELS_PWW_H 100700745U, // WHILELS_PWW_S 100676169U, // WHILELS_PXX_B 100684361U, // WHILELS_PXX_D 242774601U, // WHILELS_PXX_H 100700745U, // WHILELS_PXX_S 100676358U, // WHILELT_PWW_B 100684550U, // WHILELT_PWW_D 242774790U, // WHILELT_PWW_H 100700934U, // WHILELT_PWW_S 100676358U, // WHILELT_PXX_B 100684550U, // WHILELT_PXX_D 242774790U, // WHILELT_PXX_H 100700934U, // WHILELT_PXX_S 6303987U, // WRFFR 2216734934U, // XAR 6342582U, // XPACD 6343754U, // XPACI 5905U, // XPACLRI 135324049U, // XTNv16i8 2216210247U, // XTNv2i32 2217258823U, // XTNv4i16 2284904849U, // XTNv4i32 2285429137U, // XTNv8i16 71348039U, // XTNv8i8 167780395U, // ZIP1_PPP_B 201343019U, // ZIP1_PPP_D 2387107883U, // ZIP1_PPP_H 268468267U, // ZIP1_PPP_S 167780395U, // ZIP1_ZZZ_B 201343019U, // ZIP1_ZZZ_D 2387107883U, // ZIP1_ZZZ_H 268468267U, // ZIP1_ZZZ_S 68198443U, // ZIP1v16i8 2216206379U, // ZIP1v2i32 2216730667U, // ZIP1v2i64 69771307U, // ZIP1v4i16 70295595U, // ZIP1v4i32 2218303531U, // ZIP1v8i16 2218827819U, // ZIP1v8i8 167780806U, // ZIP2_PPP_B 201343430U, // ZIP2_PPP_D 2387108294U, // ZIP2_PPP_H 268468678U, // ZIP2_PPP_S 167780806U, // ZIP2_ZZZ_B 201343430U, // ZIP2_ZZZ_D 2387108294U, // ZIP2_ZZZ_H 268468678U, // ZIP2_ZZZ_S 68198854U, // ZIP2v16i8 2216206790U, // ZIP2v2i32 2216731078U, // ZIP2v2i64 69771718U, // ZIP2v4i16 70296006U, // ZIP2v4i32 2218303942U, // ZIP2v8i16 2218828230U, // ZIP2v8i8 302003021U, // anonymous_1349 }; static const uint32_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // ABS_ZPmZ_B 64U, // ABS_ZPmZ_D 128U, // ABS_ZPmZ_H 192U, // ABS_ZPmZ_S 1U, // ABSv16i8 1U, // ABSv1i64 2U, // ABSv2i32 2U, // ABSv2i64 3U, // ABSv4i16 3U, // ABSv4i32 4U, // ABSv8i16 4U, // ABSv8i8 261U, // ADCSWr 261U, // ADCSXr 261U, // ADCWr 261U, // ADCXr 8517U, // ADDHNv2i64_v2i32 8581U, // ADDHNv2i64_v4i32 16710U, // ADDHNv4i32_v4i16 16774U, // ADDHNv4i32_v8i16 24966U, // ADDHNv8i16_v16i8 24902U, // ADDHNv8i16_v8i8 261U, // ADDPL_XXI 33095U, // ADDPv16i8 41287U, // ADDPv2i32 8517U, // ADDPv2i64 2U, // ADDPv2i64p 49480U, // ADDPv4i16 16710U, // ADDPv4i32 24902U, // ADDPv8i16 57672U, // ADDPv8i8 453U, // ADDSWri 0U, // ADDSWrr 517U, // ADDSWrs 581U, // ADDSWrx 453U, // ADDSXri 0U, // ADDSXrr 517U, // ADDSXrs 581U, // ADDSXrx 65797U, // ADDSXrx64 261U, // ADDVL_XXI 1U, // ADDVv16i8v 3U, // ADDVv4i16v 3U, // ADDVv4i32v 4U, // ADDVv8i16v 4U, // ADDVv8i8v 453U, // ADDWri 0U, // ADDWrr 517U, // ADDWrs 581U, // ADDWrx 453U, // ADDXri 0U, // ADDXrr 517U, // ADDXrs 581U, // ADDXrx 65797U, // ADDXrx64 645U, // ADD_ZI_B 709U, // ADD_ZI_D 9U, // ADD_ZI_H 773U, // ADD_ZI_S 74560U, // ADD_ZPmZ_B 598912U, // ADD_ZPmZ_D 1131465U, // ADD_ZPmZ_H 1647616U, // ADD_ZPmZ_S 837U, // ADD_ZZZ_B 901U, // ADD_ZZZ_D 137U, // ADD_ZZZ_H 1029U, // ADD_ZZZ_S 0U, // ADDlowTLS 33095U, // ADDv16i8 261U, // ADDv1i64 41287U, // ADDv2i32 8517U, // ADDv2i64 49480U, // ADDv4i16 16710U, // ADDv4i32 24902U, // ADDv8i16 57672U, // ADDv8i8 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 1U, // ADR 0U, // ADRP 1093U, // ADR_LSL_ZZZ_D_0 1157U, // ADR_LSL_ZZZ_D_1 1221U, // ADR_LSL_ZZZ_D_2 1285U, // ADR_LSL_ZZZ_D_3 1349U, // ADR_LSL_ZZZ_S_0 1413U, // ADR_LSL_ZZZ_S_1 1477U, // ADR_LSL_ZZZ_S_2 1541U, // ADR_LSL_ZZZ_S_3 1605U, // ADR_SXTW_ZZZ_D_0 1669U, // ADR_SXTW_ZZZ_D_1 1733U, // ADR_SXTW_ZZZ_D_2 1797U, // ADR_SXTW_ZZZ_D_3 1861U, // ADR_UXTW_ZZZ_D_0 1925U, // ADR_UXTW_ZZZ_D_1 1989U, // ADR_UXTW_ZZZ_D_2 2053U, // ADR_UXTW_ZZZ_D_3 1U, // AESDrr 1U, // AESErr 1U, // AESIMCrr 0U, // AESIMCrrTied 1U, // AESMCrr 0U, // AESMCrrTied 2117U, // ANDSWri 0U, // ANDSWrr 517U, // ANDSWrs 2181U, // ANDSXri 0U, // ANDSXrr 517U, // ANDSXrs 74570U, // ANDS_PPzPP 837U, // ANDV_VPZ_B 901U, // ANDV_VPZ_D 2245U, // ANDV_VPZ_H 1029U, // ANDV_VPZ_S 2117U, // ANDWri 0U, // ANDWrr 517U, // ANDWrs 2181U, // ANDXri 0U, // ANDXrr 517U, // ANDXrs 74570U, // AND_PPzPP 2181U, // AND_ZI 74560U, // AND_ZPmZ_B 598912U, // AND_ZPmZ_D 1131465U, // AND_ZPmZ_H 1647616U, // AND_ZPmZ_S 901U, // AND_ZZZ 33095U, // ANDv16i8 57672U, // ANDv8i8 2171712U, // ASRD_ZPmI_B 2171776U, // ASRD_ZPmI_D 91081U, // ASRD_ZPmI_H 2171904U, // ASRD_ZPmI_S 74560U, // ASRR_ZPmZ_B 598912U, // ASRR_ZPmZ_D 1131465U, // ASRR_ZPmZ_H 1647616U, // ASRR_ZPmZ_S 261U, // ASRVWr 261U, // ASRVXr 598848U, // ASR_WIDE_ZPmZ_B 99273U, // ASR_WIDE_ZPmZ_H 599040U, // ASR_WIDE_ZPmZ_S 901U, // ASR_WIDE_ZZZ_B 10U, // ASR_WIDE_ZZZ_H 901U, // ASR_WIDE_ZZZ_S 2171712U, // ASR_ZPmI_B 2171776U, // ASR_ZPmI_D 91081U, // ASR_ZPmI_H 2171904U, // ASR_ZPmI_S 74560U, // ASR_ZPmZ_B 598912U, // ASR_ZPmZ_D 1131465U, // ASR_ZPmZ_H 1647616U, // ASR_ZPmZ_S 261U, // ASR_ZZI_B 261U, // ASR_ZZI_D 11U, // ASR_ZZI_H 261U, // ASR_ZZI_S 1U, // AUTDA 1U, // AUTDB 0U, // AUTDZA 0U, // AUTDZB 1U, // AUTIA 0U, // AUTIA1716 0U, // AUTIASP 0U, // AUTIAZ 1U, // AUTIB 0U, // AUTIB1716 0U, // AUTIBSP 0U, // AUTIBZ 0U, // AUTIZA 0U, // AUTIZB 0U, // B 36282695U, // BCAX 3221765U, // BFMWri 3221765U, // BFMXri 0U, // BICSWrr 517U, // BICSWrs 0U, // BICSXrr 517U, // BICSXrs 74570U, // BICS_PPzPP 0U, // BICWrr 517U, // BICWrs 0U, // BICXrr 517U, // BICXrs 74570U, // BIC_PPzPP 74560U, // BIC_ZPmZ_B 598912U, // BIC_ZPmZ_D 1131465U, // BIC_ZPmZ_H 1647616U, // BIC_ZPmZ_S 901U, // BIC_ZZZ 33095U, // BICv16i8 0U, // BICv2i32 0U, // BICv4i16 0U, // BICv4i32 0U, // BICv8i16 57672U, // BICv8i8 33095U, // BIFv16i8 57672U, // BIFv8i8 33159U, // BITv16i8 57736U, // BITv8i8 0U, // BL 0U, // BLR 1U, // BLRAA 0U, // BLRAAZ 1U, // BLRAB 0U, // BLRABZ 0U, // BR 1U, // BRAA 0U, // BRAAZ 1U, // BRAB 0U, // BRABZ 0U, // BRK 842U, // BRKAS_PPzP 0U, // BRKA_PPmP 842U, // BRKA_PPzP 842U, // BRKBS_PPzP 0U, // BRKB_PPmP 842U, // BRKB_PPzP 74570U, // BRKNS_PPzP 74570U, // BRKN_PPzP 74570U, // BRKPAS_PPzPP 74570U, // BRKPA_PPzPP 74570U, // BRKPBS_PPzPP 74570U, // BRKPB_PPzPP 33159U, // BSLv16i8 57736U, // BSLv8i8 0U, // Bcc 117003U, // CASAB 117003U, // CASAH 117003U, // CASALB 117003U, // CASALH 117003U, // CASALW 117003U, // CASALX 117003U, // CASAW 117003U, // CASAX 117003U, // CASB 117003U, // CASH 117003U, // CASLB 117003U, // CASLH 117003U, // CASLW 117003U, // CASLX 0U, // CASPALW 0U, // CASPALX 0U, // CASPAW 0U, // CASPAX 0U, // CASPLW 0U, // CASPLX 0U, // CASPW 0U, // CASPX 117003U, // CASW 117003U, // CASX 0U, // CBNZW 0U, // CBNZX 0U, // CBZW 0U, // CBZX 3744005U, // CCMNWi 3744005U, // CCMNWr 3744005U, // CCMNXi 3744005U, // CCMNXr 3744005U, // CCMPWi 3744005U, // CCMPWr 3744005U, // CCMPXi 3744005U, // CCMPXr 0U, // CFINV 73989U, // CLASTA_RPZ_B 598277U, // CLASTA_RPZ_D 4268293U, // CLASTA_RPZ_H 1646853U, // CLASTA_RPZ_S 73989U, // CLASTA_VPZ_B 598277U, // CLASTA_VPZ_D 4268293U, // CLASTA_VPZ_H 1646853U, // CLASTA_VPZ_S 74565U, // CLASTA_ZPZ_B 598917U, // CLASTA_ZPZ_D 1131465U, // CLASTA_ZPZ_H 1647621U, // CLASTA_ZPZ_S 73989U, // CLASTB_RPZ_B 598277U, // CLASTB_RPZ_D 4268293U, // CLASTB_RPZ_H 1646853U, // CLASTB_RPZ_S 73989U, // CLASTB_VPZ_B 598277U, // CLASTB_VPZ_D 4268293U, // CLASTB_VPZ_H 1646853U, // CLASTB_VPZ_S 74565U, // CLASTB_ZPZ_B 598917U, // CLASTB_ZPZ_D 1131465U, // CLASTB_ZPZ_H 1647621U, // CLASTB_ZPZ_S 0U, // CLREX 1U, // CLSWr 1U, // CLSXr 0U, // CLS_ZPmZ_B 64U, // CLS_ZPmZ_D 128U, // CLS_ZPmZ_H 192U, // CLS_ZPmZ_S 1U, // CLSv16i8 2U, // CLSv2i32 3U, // CLSv4i16 3U, // CLSv4i32 4U, // CLSv8i16 4U, // CLSv8i8 1U, // CLZWr 1U, // CLZXr 0U, // CLZ_ZPmZ_B 64U, // CLZ_ZPmZ_D 128U, // CLZ_ZPmZ_H 192U, // CLZ_ZPmZ_S 1U, // CLZv16i8 2U, // CLZv2i32 3U, // CLZv4i16 3U, // CLZv4i32 4U, // CLZv8i16 4U, // CLZv8i8 33095U, // CMEQv16i8 12U, // CMEQv16i8rz 261U, // CMEQv1i64 12U, // CMEQv1i64rz 41287U, // CMEQv2i32 13U, // CMEQv2i32rz 8517U, // CMEQv2i64 13U, // CMEQv2i64rz 49480U, // CMEQv4i16 14U, // CMEQv4i16rz 16710U, // CMEQv4i32 14U, // CMEQv4i32rz 24902U, // CMEQv8i16 15U, // CMEQv8i16rz 57672U, // CMEQv8i8 15U, // CMEQv8i8rz 33095U, // CMGEv16i8 12U, // CMGEv16i8rz 261U, // CMGEv1i64 12U, // CMGEv1i64rz 41287U, // CMGEv2i32 13U, // CMGEv2i32rz 8517U, // CMGEv2i64 13U, // CMGEv2i64rz 49480U, // CMGEv4i16 14U, // CMGEv4i16rz 16710U, // CMGEv4i32 14U, // CMGEv4i32rz 24902U, // CMGEv8i16 15U, // CMGEv8i16rz 57672U, // CMGEv8i8 15U, // CMGEv8i8rz 33095U, // CMGTv16i8 12U, // CMGTv16i8rz 261U, // CMGTv1i64 12U, // CMGTv1i64rz 41287U, // CMGTv2i32 13U, // CMGTv2i32rz 8517U, // CMGTv2i64 13U, // CMGTv2i64rz 49480U, // CMGTv4i16 14U, // CMGTv4i16rz 16710U, // CMGTv4i32 14U, // CMGTv4i32rz 24902U, // CMGTv8i16 15U, // CMGTv8i16rz 57672U, // CMGTv8i8 15U, // CMGTv8i8rz 33095U, // CMHIv16i8 261U, // CMHIv1i64 41287U, // CMHIv2i32 8517U, // CMHIv2i64 49480U, // CMHIv4i16 16710U, // CMHIv4i32 24902U, // CMHIv8i16 57672U, // CMHIv8i8 33095U, // CMHSv16i8 261U, // CMHSv1i64 41287U, // CMHSv2i32 8517U, // CMHSv2i64 49480U, // CMHSv4i16 16710U, // CMHSv4i32 24902U, // CMHSv8i16 57672U, // CMHSv8i8 12U, // CMLEv16i8rz 12U, // CMLEv1i64rz 13U, // CMLEv2i32rz 13U, // CMLEv2i64rz 14U, // CMLEv4i16rz 14U, // CMLEv4i32rz 15U, // CMLEv8i16rz 15U, // CMLEv8i8rz 12U, // CMLTv16i8rz 12U, // CMLTv1i64rz 13U, // CMLTv2i32rz 13U, // CMLTv2i64rz 14U, // CMLTv4i16rz 14U, // CMLTv4i32rz 15U, // CMLTv8i16rz 15U, // CMLTv8i8rz 2171722U, // CMPEQ_PPzZI_B 2171786U, // CMPEQ_PPzZI_D 91081U, // CMPEQ_PPzZI_H 2171914U, // CMPEQ_PPzZI_S 74570U, // CMPEQ_PPzZZ_B 598922U, // CMPEQ_PPzZZ_D 1131465U, // CMPEQ_PPzZZ_H 1647626U, // CMPEQ_PPzZZ_S 598858U, // CMPEQ_WIDE_PPzZZ_B 99273U, // CMPEQ_WIDE_PPzZZ_H 599050U, // CMPEQ_WIDE_PPzZZ_S 2171722U, // CMPGE_PPzZI_B 2171786U, // CMPGE_PPzZI_D 91081U, // CMPGE_PPzZI_H 2171914U, // CMPGE_PPzZI_S 74570U, // CMPGE_PPzZZ_B 598922U, // CMPGE_PPzZZ_D 1131465U, // CMPGE_PPzZZ_H 1647626U, // CMPGE_PPzZZ_S 598858U, // CMPGE_WIDE_PPzZZ_B 99273U, // CMPGE_WIDE_PPzZZ_H 599050U, // CMPGE_WIDE_PPzZZ_S 2171722U, // CMPGT_PPzZI_B 2171786U, // CMPGT_PPzZI_D 91081U, // CMPGT_PPzZI_H 2171914U, // CMPGT_PPzZI_S 74570U, // CMPGT_PPzZZ_B 598922U, // CMPGT_PPzZZ_D 1131465U, // CMPGT_PPzZZ_H 1647626U, // CMPGT_PPzZZ_S 598858U, // CMPGT_WIDE_PPzZZ_B 99273U, // CMPGT_WIDE_PPzZZ_H 599050U, // CMPGT_WIDE_PPzZZ_S 4793162U, // CMPHI_PPzZI_B 4793226U, // CMPHI_PPzZI_D 123849U, // CMPHI_PPzZI_H 4793354U, // CMPHI_PPzZI_S 74570U, // CMPHI_PPzZZ_B 598922U, // CMPHI_PPzZZ_D 1131465U, // CMPHI_PPzZZ_H 1647626U, // CMPHI_PPzZZ_S 598858U, // CMPHI_WIDE_PPzZZ_B 99273U, // CMPHI_WIDE_PPzZZ_H 599050U, // CMPHI_WIDE_PPzZZ_S 4793162U, // CMPHS_PPzZI_B 4793226U, // CMPHS_PPzZI_D 123849U, // CMPHS_PPzZI_H 4793354U, // CMPHS_PPzZI_S 74570U, // CMPHS_PPzZZ_B 598922U, // CMPHS_PPzZZ_D 1131465U, // CMPHS_PPzZZ_H 1647626U, // CMPHS_PPzZZ_S 598858U, // CMPHS_WIDE_PPzZZ_B 99273U, // CMPHS_WIDE_PPzZZ_H 599050U, // CMPHS_WIDE_PPzZZ_S 2171722U, // CMPLE_PPzZI_B 2171786U, // CMPLE_PPzZI_D 91081U, // CMPLE_PPzZI_H 2171914U, // CMPLE_PPzZI_S 598858U, // CMPLE_WIDE_PPzZZ_B 99273U, // CMPLE_WIDE_PPzZZ_H 599050U, // CMPLE_WIDE_PPzZZ_S 4793162U, // CMPLO_PPzZI_B 4793226U, // CMPLO_PPzZI_D 123849U, // CMPLO_PPzZI_H 4793354U, // CMPLO_PPzZI_S 598858U, // CMPLO_WIDE_PPzZZ_B 99273U, // CMPLO_WIDE_PPzZZ_H 599050U, // CMPLO_WIDE_PPzZZ_S 4793162U, // CMPLS_PPzZI_B 4793226U, // CMPLS_PPzZI_D 123849U, // CMPLS_PPzZI_H 4793354U, // CMPLS_PPzZI_S 598858U, // CMPLS_WIDE_PPzZZ_B 99273U, // CMPLS_WIDE_PPzZZ_H 599050U, // CMPLS_WIDE_PPzZZ_S 2171722U, // CMPLT_PPzZI_B 2171786U, // CMPLT_PPzZI_D 91081U, // CMPLT_PPzZI_H 2171914U, // CMPLT_PPzZI_S 598858U, // CMPLT_WIDE_PPzZZ_B 99273U, // CMPLT_WIDE_PPzZZ_H 599050U, // CMPLT_WIDE_PPzZZ_S 2171722U, // CMPNE_PPzZI_B 2171786U, // CMPNE_PPzZI_D 91081U, // CMPNE_PPzZI_H 2171914U, // CMPNE_PPzZI_S 74570U, // CMPNE_PPzZZ_B 598922U, // CMPNE_PPzZZ_D 1131465U, // CMPNE_PPzZZ_H 1647626U, // CMPNE_PPzZZ_S 598858U, // CMPNE_WIDE_PPzZZ_B 99273U, // CMPNE_WIDE_PPzZZ_H 599050U, // CMPNE_WIDE_PPzZZ_S 0U, // CMP_SWAP_128 0U, // CMP_SWAP_16 0U, // CMP_SWAP_32 0U, // CMP_SWAP_64 0U, // CMP_SWAP_8 33095U, // CMTSTv16i8 261U, // CMTSTv1i64 41287U, // CMTSTv2i32 8517U, // CMTSTv2i64 49480U, // CMTSTv4i16 16710U, // CMTSTv4i32 24902U, // CMTSTv8i16 57672U, // CMTSTv8i8 0U, // CNOT_ZPmZ_B 64U, // CNOT_ZPmZ_D 128U, // CNOT_ZPmZ_H 192U, // CNOT_ZPmZ_S 16U, // CNTB_XPiI 16U, // CNTD_XPiI 16U, // CNTH_XPiI 837U, // CNTP_XPP_B 901U, // CNTP_XPP_D 2245U, // CNTP_XPP_H 1029U, // CNTP_XPP_S 16U, // CNTW_XPiI 0U, // CNT_ZPmZ_B 64U, // CNT_ZPmZ_D 128U, // CNT_ZPmZ_H 192U, // CNT_ZPmZ_S 1U, // CNTv16i8 4U, // CNTv8i8 901U, // COMPACT_ZPZ_D 1029U, // COMPACT_ZPZ_S 2368U, // CPY_ZPmI_B 2432U, // CPY_ZPmI_D 16U, // CPY_ZPmI_H 2496U, // CPY_ZPmI_S 2304U, // CPY_ZPmR_B 2304U, // CPY_ZPmR_D 145U, // CPY_ZPmR_H 2304U, // CPY_ZPmR_S 2304U, // CPY_ZPmV_B 2304U, // CPY_ZPmV_D 145U, // CPY_ZPmV_H 2304U, // CPY_ZPmV_S 2570U, // CPY_ZPzI_B 2634U, // CPY_ZPzI_D 17U, // CPY_ZPzI_H 2698U, // CPY_ZPzI_S 2770U, // CPYi16 2770U, // CPYi32 2771U, // CPYi64 2771U, // CPYi8 261U, // CRC32Brr 261U, // CRC32CBrr 261U, // CRC32CHrr 261U, // CRC32CWrr 261U, // CRC32CXrr 261U, // CRC32Hrr 261U, // CRC32Wrr 261U, // CRC32Xrr 3744005U, // CSELWr 3744005U, // CSELXr 3744005U, // CSINCWr 3744005U, // CSINCXr 3744005U, // CSINVWr 3744005U, // CSINVXr 3744005U, // CSNEGWr 3744005U, // CSNEGXr 1U, // CTERMEQ_WW 1U, // CTERMEQ_XX 1U, // CTERMNE_WW 1U, // CTERMNE_XX 0U, // CompilerBarrier 0U, // DCPS1 0U, // DCPS2 0U, // DCPS3 0U, // DECB_XPiI 0U, // DECD_XPiI 0U, // DECD_ZPiI 0U, // DECH_XPiI 0U, // DECH_ZPiI 1U, // DECP_XP_B 1U, // DECP_XP_D 1U, // DECP_XP_H 1U, // DECP_XP_S 1U, // DECP_ZP_D 0U, // DECP_ZP_H 1U, // DECP_ZP_S 0U, // DECW_XPiI 0U, // DECW_ZPiI 0U, // DMB 0U, // DRPS 0U, // DSB 0U, // DUPM_ZI 0U, // DUP_ZI_B 0U, // DUP_ZI_D 0U, // DUP_ZI_H 0U, // DUP_ZI_S 1U, // DUP_ZR_B 1U, // DUP_ZR_D 0U, // DUP_ZR_H 1U, // DUP_ZR_S 20U, // DUP_ZZI_B 20U, // DUP_ZZI_D 0U, // DUP_ZZI_H 0U, // DUP_ZZI_Q 20U, // DUP_ZZI_S 1U, // DUPv16i8gpr 2771U, // DUPv16i8lane 1U, // DUPv2i32gpr 2770U, // DUPv2i32lane 1U, // DUPv2i64gpr 2771U, // DUPv2i64lane 1U, // DUPv4i16gpr 2770U, // DUPv4i16lane 1U, // DUPv4i32gpr 2770U, // DUPv4i32lane 1U, // DUPv8i16gpr 2770U, // DUPv8i16lane 1U, // DUPv8i8gpr 2771U, // DUPv8i8lane 0U, // EONWrr 517U, // EONWrs 0U, // EONXrr 517U, // EONXrs 36282695U, // EOR3 74570U, // EORS_PPzPP 837U, // EORV_VPZ_B 901U, // EORV_VPZ_D 2245U, // EORV_VPZ_H 1029U, // EORV_VPZ_S 2117U, // EORWri 0U, // EORWrr 517U, // EORWrs 2181U, // EORXri 0U, // EORXrr 517U, // EORXrs 74570U, // EOR_PPzPP 2181U, // EOR_ZI 74560U, // EOR_ZPmZ_B 598912U, // EOR_ZPmZ_D 1131465U, // EOR_ZPmZ_H 1647616U, // EOR_ZPmZ_S 901U, // EOR_ZZZ 33095U, // EORv16i8 57672U, // EORv8i8 0U, // ERET 0U, // ERETAA 0U, // ERETAB 2171141U, // EXTRWrri 2171141U, // EXTRXrri 4793157U, // EXT_ZZI 2203975U, // EXTv16i8 131400U, // EXTv8i8 0U, // F128CSEL 261U, // FABD16 261U, // FABD32 261U, // FABD64 598912U, // FABD_ZPmZ_D 1131465U, // FABD_ZPmZ_H 1647616U, // FABD_ZPmZ_S 41287U, // FABDv2f32 8517U, // FABDv2f64 49480U, // FABDv4f16 16710U, // FABDv4f32 24902U, // FABDv8f16 1U, // FABSDr 1U, // FABSHr 1U, // FABSSr 64U, // FABS_ZPmZ_D 128U, // FABS_ZPmZ_H 192U, // FABS_ZPmZ_S 2U, // FABSv2f32 2U, // FABSv2f64 3U, // FABSv4f16 3U, // FABSv4f32 4U, // FABSv8f16 261U, // FACGE16 261U, // FACGE32 261U, // FACGE64 598922U, // FACGE_PPzZZ_D 1131465U, // FACGE_PPzZZ_H 1647626U, // FACGE_PPzZZ_S 41287U, // FACGEv2f32 8517U, // FACGEv2f64 49480U, // FACGEv4f16 16710U, // FACGEv4f32 24902U, // FACGEv8f16 261U, // FACGT16 261U, // FACGT32 261U, // FACGT64 598922U, // FACGT_PPzZZ_D 1131465U, // FACGT_PPzZZ_H 1647626U, // FACGT_PPzZZ_S 41287U, // FACGTv2f32 8517U, // FACGTv2f64 49480U, // FACGTv4f16 16710U, // FACGTv4f32 24902U, // FACGTv8f16 598277U, // FADDA_VPZ_D 4268293U, // FADDA_VPZ_H 1646853U, // FADDA_VPZ_S 261U, // FADDDrr 261U, // FADDHrr 41287U, // FADDPv2f32 8517U, // FADDPv2f64 20U, // FADDPv2i16p 2U, // FADDPv2i32p 2U, // FADDPv2i64p 49480U, // FADDPv4f16 16710U, // FADDPv4f32 24902U, // FADDPv8f16 261U, // FADDSrr 901U, // FADDV_VPZ_D 2245U, // FADDV_VPZ_H 1029U, // FADDV_VPZ_S 5317504U, // FADD_ZPmI_D 140233U, // FADD_ZPmI_H 5317632U, // FADD_ZPmI_S 598912U, // FADD_ZPmZ_D 1131465U, // FADD_ZPmZ_H 1647616U, // FADD_ZPmZ_S 901U, // FADD_ZZZ_D 137U, // FADD_ZZZ_H 1029U, // FADD_ZZZ_S 41287U, // FADDv2f32 8517U, // FADDv2f64 49480U, // FADDv4f16 16710U, // FADDv4f32 24902U, // FADDv8f16 67707776U, // FCADD_ZPmZ_D 106513353U, // FCADD_ZPmZ_H 68756480U, // FCADD_ZPmZ_S 6439239U, // FCADDv2f32 6447429U, // FCADDv2f64 6455624U, // FCADDv4f16 6463814U, // FCADDv4f32 6472006U, // FCADDv8f16 3744005U, // FCCMPDrr 3744005U, // FCCMPEDrr 3744005U, // FCCMPEHrr 3744005U, // FCCMPESrr 3744005U, // FCCMPHrr 3744005U, // FCCMPSrr 261U, // FCMEQ16 261U, // FCMEQ32 261U, // FCMEQ64 189322U, // FCMEQ_PPzZ0_D 2825U, // FCMEQ_PPzZ0_H 189450U, // FCMEQ_PPzZ0_S 598922U, // FCMEQ_PPzZZ_D 1131465U, // FCMEQ_PPzZZ_H 1647626U, // FCMEQ_PPzZZ_S 21U, // FCMEQv1i16rz 21U, // FCMEQv1i32rz 21U, // FCMEQv1i64rz 41287U, // FCMEQv2f32 8517U, // FCMEQv2f64 21U, // FCMEQv2i32rz 22U, // FCMEQv2i64rz 49480U, // FCMEQv4f16 16710U, // FCMEQv4f32 22U, // FCMEQv4i16rz 23U, // FCMEQv4i32rz 24902U, // FCMEQv8f16 23U, // FCMEQv8i16rz 261U, // FCMGE16 261U, // FCMGE32 261U, // FCMGE64 189322U, // FCMGE_PPzZ0_D 2825U, // FCMGE_PPzZ0_H 189450U, // FCMGE_PPzZ0_S 598922U, // FCMGE_PPzZZ_D 1131465U, // FCMGE_PPzZZ_H 1647626U, // FCMGE_PPzZZ_S 21U, // FCMGEv1i16rz 21U, // FCMGEv1i32rz 21U, // FCMGEv1i64rz 41287U, // FCMGEv2f32 8517U, // FCMGEv2f64 21U, // FCMGEv2i32rz 22U, // FCMGEv2i64rz 49480U, // FCMGEv4f16 16710U, // FCMGEv4f32 22U, // FCMGEv4i16rz 23U, // FCMGEv4i32rz 24902U, // FCMGEv8f16 23U, // FCMGEv8i16rz 261U, // FCMGT16 261U, // FCMGT32 261U, // FCMGT64 189322U, // FCMGT_PPzZ0_D 2825U, // FCMGT_PPzZ0_H 189450U, // FCMGT_PPzZ0_S 598922U, // FCMGT_PPzZZ_D 1131465U, // FCMGT_PPzZZ_H 1647626U, // FCMGT_PPzZZ_S 21U, // FCMGTv1i16rz 21U, // FCMGTv1i32rz 21U, // FCMGTv1i64rz 41287U, // FCMGTv2f32 8517U, // FCMGTv2f64 21U, // FCMGTv2i32rz 22U, // FCMGTv2i64rz 49480U, // FCMGTv4f16 16710U, // FCMGTv4f32 22U, // FCMGTv4i16rz 23U, // FCMGTv4i32rz 24902U, // FCMGTv8f16 23U, // FCMGTv8i16rz 342433856U, // FCMLA_ZPmZZ_D 140182464U, // FCMLA_ZPmZZ_H 342958272U, // FCMLA_ZPmZZ_S 24U, // FCMLA_ZZZI_H 7940952U, // FCMLA_ZZZI_S 8536455U, // FCMLAv2f32 8544645U, // FCMLAv2f64 8552840U, // FCMLAv4f16 344662408U, // FCMLAv4f16_indexed 8561030U, // FCMLAv4f32 344670598U, // FCMLAv4f32_indexed 8569222U, // FCMLAv8f16 344662406U, // FCMLAv8f16_indexed 189322U, // FCMLE_PPzZ0_D 2825U, // FCMLE_PPzZ0_H 189450U, // FCMLE_PPzZ0_S 21U, // FCMLEv1i16rz 21U, // FCMLEv1i32rz 21U, // FCMLEv1i64rz 21U, // FCMLEv2i32rz 22U, // FCMLEv2i64rz 22U, // FCMLEv4i16rz 23U, // FCMLEv4i32rz 23U, // FCMLEv8i16rz 189322U, // FCMLT_PPzZ0_D 2825U, // FCMLT_PPzZ0_H 189450U, // FCMLT_PPzZ0_S 21U, // FCMLTv1i16rz 21U, // FCMLTv1i32rz 21U, // FCMLTv1i64rz 21U, // FCMLTv2i32rz 22U, // FCMLTv2i64rz 22U, // FCMLTv4i16rz 23U, // FCMLTv4i32rz 23U, // FCMLTv8i16rz 189322U, // FCMNE_PPzZ0_D 2825U, // FCMNE_PPzZ0_H 189450U, // FCMNE_PPzZ0_S 598922U, // FCMNE_PPzZZ_D 1131465U, // FCMNE_PPzZZ_H 1647626U, // FCMNE_PPzZZ_S 0U, // FCMPDri 1U, // FCMPDrr 0U, // FCMPEDri 1U, // FCMPEDrr 0U, // FCMPEHri 1U, // FCMPEHrr 0U, // FCMPESri 1U, // FCMPESrr 0U, // FCMPHri 1U, // FCMPHrr 0U, // FCMPSri 1U, // FCMPSrr 598922U, // FCMUO_PPzZZ_D 1131465U, // FCMUO_PPzZZ_H 1647626U, // FCMUO_PPzZZ_S 2944U, // FCPY_ZPmI_D 25U, // FCPY_ZPmI_H 2944U, // FCPY_ZPmI_S 3744005U, // FCSELDrrr 3744005U, // FCSELHrrr 3744005U, // FCSELSrrr 1U, // FCVTASUWDr 1U, // FCVTASUWHr 1U, // FCVTASUWSr 1U, // FCVTASUXDr 1U, // FCVTASUXHr 1U, // FCVTASUXSr 1U, // FCVTASv1f16 1U, // FCVTASv1i32 1U, // FCVTASv1i64 2U, // FCVTASv2f32 2U, // FCVTASv2f64 3U, // FCVTASv4f16 3U, // FCVTASv4f32 4U, // FCVTASv8f16 1U, // FCVTAUUWDr 1U, // FCVTAUUWHr 1U, // FCVTAUUWSr 1U, // FCVTAUUXDr 1U, // FCVTAUUXHr 1U, // FCVTAUUXSr 1U, // FCVTAUv1f16 1U, // FCVTAUv1i32 1U, // FCVTAUv1i64 2U, // FCVTAUv2f32 2U, // FCVTAUv2f64 3U, // FCVTAUv4f16 3U, // FCVTAUv4f32 4U, // FCVTAUv8f16 1U, // FCVTDHr 1U, // FCVTDSr 1U, // FCVTHDr 1U, // FCVTHSr 2U, // FCVTLv2i32 3U, // FCVTLv4i16 3U, // FCVTLv4i32 4U, // FCVTLv8i16 1U, // FCVTMSUWDr 1U, // FCVTMSUWHr 1U, // FCVTMSUWSr 1U, // FCVTMSUXDr 1U, // FCVTMSUXHr 1U, // FCVTMSUXSr 1U, // FCVTMSv1f16 1U, // FCVTMSv1i32 1U, // FCVTMSv1i64 2U, // FCVTMSv2f32 2U, // FCVTMSv2f64 3U, // FCVTMSv4f16 3U, // FCVTMSv4f32 4U, // FCVTMSv8f16 1U, // FCVTMUUWDr 1U, // FCVTMUUWHr 1U, // FCVTMUUWSr 1U, // FCVTMUUXDr 1U, // FCVTMUUXHr 1U, // FCVTMUUXSr 1U, // FCVTMUv1f16 1U, // FCVTMUv1i32 1U, // FCVTMUv1i64 2U, // FCVTMUv2f32 2U, // FCVTMUv2f64 3U, // FCVTMUv4f16 3U, // FCVTMUv4f32 4U, // FCVTMUv8f16 1U, // FCVTNSUWDr 1U, // FCVTNSUWHr 1U, // FCVTNSUWSr 1U, // FCVTNSUXDr 1U, // FCVTNSUXHr 1U, // FCVTNSUXSr 1U, // FCVTNSv1f16 1U, // FCVTNSv1i32 1U, // FCVTNSv1i64 2U, // FCVTNSv2f32 2U, // FCVTNSv2f64 3U, // FCVTNSv4f16 3U, // FCVTNSv4f32 4U, // FCVTNSv8f16 1U, // FCVTNUUWDr 1U, // FCVTNUUWHr 1U, // FCVTNUUWSr 1U, // FCVTNUUXDr 1U, // FCVTNUUXHr 1U, // FCVTNUUXSr 1U, // FCVTNUv1f16 1U, // FCVTNUv1i32 1U, // FCVTNUv1i64 2U, // FCVTNUv2f32 2U, // FCVTNUv2f64 3U, // FCVTNUv4f16 3U, // FCVTNUv4f32 4U, // FCVTNUv8f16 2U, // FCVTNv2i32 3U, // FCVTNv4i16 2U, // FCVTNv4i32 3U, // FCVTNv8i16 1U, // FCVTPSUWDr 1U, // FCVTPSUWHr 1U, // FCVTPSUWSr 1U, // FCVTPSUXDr 1U, // FCVTPSUXHr 1U, // FCVTPSUXSr 1U, // FCVTPSv1f16 1U, // FCVTPSv1i32 1U, // FCVTPSv1i64 2U, // FCVTPSv2f32 2U, // FCVTPSv2f64 3U, // FCVTPSv4f16 3U, // FCVTPSv4f32 4U, // FCVTPSv8f16 1U, // FCVTPUUWDr 1U, // FCVTPUUWHr 1U, // FCVTPUUWSr 1U, // FCVTPUUXDr 1U, // FCVTPUUXHr 1U, // FCVTPUUXSr 1U, // FCVTPUv1f16 1U, // FCVTPUv1i32 1U, // FCVTPUv1i64 2U, // FCVTPUv2f32 2U, // FCVTPUv2f64 3U, // FCVTPUv4f16 3U, // FCVTPUv4f32 4U, // FCVTPUv8f16 1U, // FCVTSDr 1U, // FCVTSHr 1U, // FCVTXNv1i64 2U, // FCVTXNv2f32 2U, // FCVTXNv4f32 261U, // FCVTZSSWDri 261U, // FCVTZSSWHri 261U, // FCVTZSSWSri 261U, // FCVTZSSXDri 261U, // FCVTZSSXHri 261U, // FCVTZSSXSri 1U, // FCVTZSUWDr 1U, // FCVTZSUWHr 1U, // FCVTZSUWSr 1U, // FCVTZSUXDr 1U, // FCVTZSUXHr 1U, // FCVTZSUXSr 64U, // FCVTZS_ZPmZ_DtoD 64U, // FCVTZS_ZPmZ_DtoS 3008U, // FCVTZS_ZPmZ_HtoD 128U, // FCVTZS_ZPmZ_HtoH 3008U, // FCVTZS_ZPmZ_HtoS 192U, // FCVTZS_ZPmZ_StoD 192U, // FCVTZS_ZPmZ_StoS 261U, // FCVTZSd 261U, // FCVTZSh 261U, // FCVTZSs 1U, // FCVTZSv1f16 1U, // FCVTZSv1i32 1U, // FCVTZSv1i64 2U, // FCVTZSv2f32 2U, // FCVTZSv2f64 263U, // FCVTZSv2i32_shift 261U, // FCVTZSv2i64_shift 3U, // FCVTZSv4f16 3U, // FCVTZSv4f32 264U, // FCVTZSv4i16_shift 262U, // FCVTZSv4i32_shift 4U, // FCVTZSv8f16 262U, // FCVTZSv8i16_shift 261U, // FCVTZUSWDri 261U, // FCVTZUSWHri 261U, // FCVTZUSWSri 261U, // FCVTZUSXDri 261U, // FCVTZUSXHri 261U, // FCVTZUSXSri 1U, // FCVTZUUWDr 1U, // FCVTZUUWHr 1U, // FCVTZUUWSr 1U, // FCVTZUUXDr 1U, // FCVTZUUXHr 1U, // FCVTZUUXSr 64U, // FCVTZU_ZPmZ_DtoD 64U, // FCVTZU_ZPmZ_DtoS 3008U, // FCVTZU_ZPmZ_HtoD 128U, // FCVTZU_ZPmZ_HtoH 3008U, // FCVTZU_ZPmZ_HtoS 192U, // FCVTZU_ZPmZ_StoD 192U, // FCVTZU_ZPmZ_StoS 261U, // FCVTZUd 261U, // FCVTZUh 261U, // FCVTZUs 1U, // FCVTZUv1f16 1U, // FCVTZUv1i32 1U, // FCVTZUv1i64 2U, // FCVTZUv2f32 2U, // FCVTZUv2f64 263U, // FCVTZUv2i32_shift 261U, // FCVTZUv2i64_shift 3U, // FCVTZUv4f16 3U, // FCVTZUv4f32 264U, // FCVTZUv4i16_shift 262U, // FCVTZUv4i32_shift 4U, // FCVTZUv8f16 262U, // FCVTZUv8i16_shift 153U, // FCVT_ZPmZ_DtoH 64U, // FCVT_ZPmZ_DtoS 3008U, // FCVT_ZPmZ_HtoD 3008U, // FCVT_ZPmZ_HtoS 192U, // FCVT_ZPmZ_StoD 152U, // FCVT_ZPmZ_StoH 261U, // FDIVDrr 261U, // FDIVHrr 598912U, // FDIVR_ZPmZ_D 1131465U, // FDIVR_ZPmZ_H 1647616U, // FDIVR_ZPmZ_S 261U, // FDIVSrr 598912U, // FDIV_ZPmZ_D 1131465U, // FDIV_ZPmZ_H 1647616U, // FDIV_ZPmZ_S 41287U, // FDIVv2f32 8517U, // FDIVv2f64 49480U, // FDIVv4f16 16710U, // FDIVv4f32 24902U, // FDIVv8f16 0U, // FDUP_ZI_D 0U, // FDUP_ZI_H 0U, // FDUP_ZI_S 1U, // FEXPA_ZZ_D 0U, // FEXPA_ZZ_H 1U, // FEXPA_ZZ_S 1U, // FJCVTZS 2171141U, // FMADDDrrr 2171141U, // FMADDHrrr 2171141U, // FMADDSrrr 6889536U, // FMAD_ZPmZZ_D 1246144U, // FMAD_ZPmZZ_H 7413952U, // FMAD_ZPmZZ_S 261U, // FMAXDrr 261U, // FMAXHrr 261U, // FMAXNMDrr 261U, // FMAXNMHrr 41287U, // FMAXNMPv2f32 8517U, // FMAXNMPv2f64 20U, // FMAXNMPv2i16p 2U, // FMAXNMPv2i32p 2U, // FMAXNMPv2i64p 49480U, // FMAXNMPv4f16 16710U, // FMAXNMPv4f32 24902U, // FMAXNMPv8f16 261U, // FMAXNMSrr 901U, // FMAXNMV_VPZ_D 2245U, // FMAXNMV_VPZ_H 1029U, // FMAXNMV_VPZ_S 3U, // FMAXNMVv4i16v 3U, // FMAXNMVv4i32v 4U, // FMAXNMVv8i16v 9511808U, // FMAXNM_ZPmI_D 222153U, // FMAXNM_ZPmI_H 9511936U, // FMAXNM_ZPmI_S 598912U, // FMAXNM_ZPmZ_D 1131465U, // FMAXNM_ZPmZ_H 1647616U, // FMAXNM_ZPmZ_S 41287U, // FMAXNMv2f32 8517U, // FMAXNMv2f64 49480U, // FMAXNMv4f16 16710U, // FMAXNMv4f32 24902U, // FMAXNMv8f16 41287U, // FMAXPv2f32 8517U, // FMAXPv2f64 20U, // FMAXPv2i16p 2U, // FMAXPv2i32p 2U, // FMAXPv2i64p 49480U, // FMAXPv4f16 16710U, // FMAXPv4f32 24902U, // FMAXPv8f16 261U, // FMAXSrr 901U, // FMAXV_VPZ_D 2245U, // FMAXV_VPZ_H 1029U, // FMAXV_VPZ_S 3U, // FMAXVv4i16v 3U, // FMAXVv4i32v 4U, // FMAXVv8i16v 9511808U, // FMAX_ZPmI_D 222153U, // FMAX_ZPmI_H 9511936U, // FMAX_ZPmI_S 598912U, // FMAX_ZPmZ_D 1131465U, // FMAX_ZPmZ_H 1647616U, // FMAX_ZPmZ_S 41287U, // FMAXv2f32 8517U, // FMAXv2f64 49480U, // FMAXv4f16 16710U, // FMAXv4f32 24902U, // FMAXv8f16 261U, // FMINDrr 261U, // FMINHrr 261U, // FMINNMDrr 261U, // FMINNMHrr 41287U, // FMINNMPv2f32 8517U, // FMINNMPv2f64 20U, // FMINNMPv2i16p 2U, // FMINNMPv2i32p 2U, // FMINNMPv2i64p 49480U, // FMINNMPv4f16 16710U, // FMINNMPv4f32 24902U, // FMINNMPv8f16 261U, // FMINNMSrr 901U, // FMINNMV_VPZ_D 2245U, // FMINNMV_VPZ_H 1029U, // FMINNMV_VPZ_S 3U, // FMINNMVv4i16v 3U, // FMINNMVv4i32v 4U, // FMINNMVv8i16v 9511808U, // FMINNM_ZPmI_D 222153U, // FMINNM_ZPmI_H 9511936U, // FMINNM_ZPmI_S 598912U, // FMINNM_ZPmZ_D 1131465U, // FMINNM_ZPmZ_H 1647616U, // FMINNM_ZPmZ_S 41287U, // FMINNMv2f32 8517U, // FMINNMv2f64 49480U, // FMINNMv4f16 16710U, // FMINNMv4f32 24902U, // FMINNMv8f16 41287U, // FMINPv2f32 8517U, // FMINPv2f64 20U, // FMINPv2i16p 2U, // FMINPv2i32p 2U, // FMINPv2i64p 49480U, // FMINPv4f16 16710U, // FMINPv4f32 24902U, // FMINPv8f16 261U, // FMINSrr 901U, // FMINV_VPZ_D 2245U, // FMINV_VPZ_H 1029U, // FMINV_VPZ_S 3U, // FMINVv4i16v 3U, // FMINVv4i32v 4U, // FMINVv8i16v 9511808U, // FMIN_ZPmI_D 222153U, // FMIN_ZPmI_H 9511936U, // FMIN_ZPmI_S 598912U, // FMIN_ZPmZ_D 1131465U, // FMIN_ZPmZ_H 1647616U, // FMIN_ZPmZ_S 41287U, // FMINv2f32 8517U, // FMINv2f64 49480U, // FMINv4f16 16710U, // FMINv4f32 24902U, // FMINv8f16 6889536U, // FMLA_ZPmZZ_D 1246144U, // FMLA_ZPmZZ_H 7413952U, // FMLA_ZPmZZ_S 2905U, // FMLA_ZZZI_D 0U, // FMLA_ZZZI_H 2904U, // FMLA_ZZZI_S 9118085U, // FMLAv1i16_indexed 9126277U, // FMLAv1i32_indexed 9142661U, // FMLAv1i64_indexed 41351U, // FMLAv2f32 8581U, // FMLAv2f64 9126279U, // FMLAv2i32_indexed 9142661U, // FMLAv2i64_indexed 49544U, // FMLAv4f16 16774U, // FMLAv4f32 9118088U, // FMLAv4i16_indexed 9126278U, // FMLAv4i32_indexed 24966U, // FMLAv8f16 9118086U, // FMLAv8i16_indexed 6889536U, // FMLS_ZPmZZ_D 1246144U, // FMLS_ZPmZZ_H 7413952U, // FMLS_ZPmZZ_S 2905U, // FMLS_ZZZI_D 0U, // FMLS_ZZZI_H 2904U, // FMLS_ZZZI_S 9118085U, // FMLSv1i16_indexed 9126277U, // FMLSv1i32_indexed 9142661U, // FMLSv1i64_indexed 41351U, // FMLSv2f32 8581U, // FMLSv2f64 9126279U, // FMLSv2i32_indexed 9142661U, // FMLSv2i64_indexed 49544U, // FMLSv4f16 16774U, // FMLSv4f32 9118088U, // FMLSv4i16_indexed 9126278U, // FMLSv4i32_indexed 24966U, // FMLSv8f16 9118086U, // FMLSv8i16_indexed 0U, // FMOVD0 2771U, // FMOVDXHighr 1U, // FMOVDXr 0U, // FMOVDi 1U, // FMOVDr 0U, // FMOVH0 1U, // FMOVHWr 1U, // FMOVHXr 0U, // FMOVHi 1U, // FMOVHr 0U, // FMOVS0 1U, // FMOVSWr 0U, // FMOVSi 1U, // FMOVSr 1U, // FMOVWHr 1U, // FMOVWSr 1U, // FMOVXDHighr 1U, // FMOVXDr 1U, // FMOVXHr 0U, // FMOVv2f32_ns 0U, // FMOVv2f64_ns 0U, // FMOVv4f16_ns 0U, // FMOVv4f32_ns 0U, // FMOVv8f16_ns 6889536U, // FMSB_ZPmZZ_D 1246144U, // FMSB_ZPmZZ_H 7413952U, // FMSB_ZPmZZ_S 2171141U, // FMSUBDrrr 2171141U, // FMSUBHrrr 2171141U, // FMSUBSrrr 261U, // FMULDrr 261U, // FMULHrr 261U, // FMULSrr 261U, // FMULX16 261U, // FMULX32 261U, // FMULX64 598912U, // FMULX_ZPmZ_D 1131465U, // FMULX_ZPmZ_H 1647616U, // FMULX_ZPmZ_S 10166597U, // FMULXv1i16_indexed 10174789U, // FMULXv1i32_indexed 10191173U, // FMULXv1i64_indexed 41287U, // FMULXv2f32 8517U, // FMULXv2f64 10174791U, // FMULXv2i32_indexed 10191173U, // FMULXv2i64_indexed 49480U, // FMULXv4f16 16710U, // FMULXv4f32 10166600U, // FMULXv4i16_indexed 10174790U, // FMULXv4i32_indexed 24902U, // FMULXv8f16 10166598U, // FMULXv8i16_indexed 10560384U, // FMUL_ZPmI_D 238537U, // FMUL_ZPmI_H 10560512U, // FMUL_ZPmI_S 598912U, // FMUL_ZPmZ_D 1131465U, // FMUL_ZPmZ_H 1647616U, // FMUL_ZPmZ_S 246661U, // FMUL_ZZZI_D 3081U, // FMUL_ZZZI_H 246789U, // FMUL_ZZZI_S 901U, // FMUL_ZZZ_D 137U, // FMUL_ZZZ_H 1029U, // FMUL_ZZZ_S 10166597U, // FMULv1i16_indexed 10174789U, // FMULv1i32_indexed 10191173U, // FMULv1i64_indexed 41287U, // FMULv2f32 8517U, // FMULv2f64 10174791U, // FMULv2i32_indexed 10191173U, // FMULv2i64_indexed 49480U, // FMULv4f16 16710U, // FMULv4f32 10166600U, // FMULv4i16_indexed 10174790U, // FMULv4i32_indexed 24902U, // FMULv8f16 10166598U, // FMULv8i16_indexed 1U, // FNEGDr 1U, // FNEGHr 1U, // FNEGSr 64U, // FNEG_ZPmZ_D 128U, // FNEG_ZPmZ_H 192U, // FNEG_ZPmZ_S 2U, // FNEGv2f32 2U, // FNEGv2f64 3U, // FNEGv4f16 3U, // FNEGv4f32 4U, // FNEGv8f16 2171141U, // FNMADDDrrr 2171141U, // FNMADDHrrr 2171141U, // FNMADDSrrr 6889536U, // FNMAD_ZPmZZ_D 1246144U, // FNMAD_ZPmZZ_H 7413952U, // FNMAD_ZPmZZ_S 6889536U, // FNMLA_ZPmZZ_D 1246144U, // FNMLA_ZPmZZ_H 7413952U, // FNMLA_ZPmZZ_S 6889536U, // FNMLS_ZPmZZ_D 1246144U, // FNMLS_ZPmZZ_H 7413952U, // FNMLS_ZPmZZ_S 6889536U, // FNMSB_ZPmZZ_D 1246144U, // FNMSB_ZPmZZ_H 7413952U, // FNMSB_ZPmZZ_S 2171141U, // FNMSUBDrrr 2171141U, // FNMSUBHrrr 2171141U, // FNMSUBSrrr 261U, // FNMULDrr 261U, // FNMULHrr 261U, // FNMULSrr 1U, // FRECPE_ZZ_D 0U, // FRECPE_ZZ_H 1U, // FRECPE_ZZ_S 1U, // FRECPEv1f16 1U, // FRECPEv1i32 1U, // FRECPEv1i64 2U, // FRECPEv2f32 2U, // FRECPEv2f64 3U, // FRECPEv4f16 3U, // FRECPEv4f32 4U, // FRECPEv8f16 261U, // FRECPS16 261U, // FRECPS32 261U, // FRECPS64 901U, // FRECPS_ZZZ_D 137U, // FRECPS_ZZZ_H 1029U, // FRECPS_ZZZ_S 41287U, // FRECPSv2f32 8517U, // FRECPSv2f64 49480U, // FRECPSv4f16 16710U, // FRECPSv4f32 24902U, // FRECPSv8f16 64U, // FRECPX_ZPmZ_D 128U, // FRECPX_ZPmZ_H 192U, // FRECPX_ZPmZ_S 1U, // FRECPXv1f16 1U, // FRECPXv1i32 1U, // FRECPXv1i64 1U, // FRINTADr 1U, // FRINTAHr 1U, // FRINTASr 64U, // FRINTA_ZPmZ_D 128U, // FRINTA_ZPmZ_H 192U, // FRINTA_ZPmZ_S 2U, // FRINTAv2f32 2U, // FRINTAv2f64 3U, // FRINTAv4f16 3U, // FRINTAv4f32 4U, // FRINTAv8f16 1U, // FRINTIDr 1U, // FRINTIHr 1U, // FRINTISr 64U, // FRINTI_ZPmZ_D 128U, // FRINTI_ZPmZ_H 192U, // FRINTI_ZPmZ_S 2U, // FRINTIv2f32 2U, // FRINTIv2f64 3U, // FRINTIv4f16 3U, // FRINTIv4f32 4U, // FRINTIv8f16 1U, // FRINTMDr 1U, // FRINTMHr 1U, // FRINTMSr 64U, // FRINTM_ZPmZ_D 128U, // FRINTM_ZPmZ_H 192U, // FRINTM_ZPmZ_S 2U, // FRINTMv2f32 2U, // FRINTMv2f64 3U, // FRINTMv4f16 3U, // FRINTMv4f32 4U, // FRINTMv8f16 1U, // FRINTNDr 1U, // FRINTNHr 1U, // FRINTNSr 64U, // FRINTN_ZPmZ_D 128U, // FRINTN_ZPmZ_H 192U, // FRINTN_ZPmZ_S 2U, // FRINTNv2f32 2U, // FRINTNv2f64 3U, // FRINTNv4f16 3U, // FRINTNv4f32 4U, // FRINTNv8f16 1U, // FRINTPDr 1U, // FRINTPHr 1U, // FRINTPSr 64U, // FRINTP_ZPmZ_D 128U, // FRINTP_ZPmZ_H 192U, // FRINTP_ZPmZ_S 2U, // FRINTPv2f32 2U, // FRINTPv2f64 3U, // FRINTPv4f16 3U, // FRINTPv4f32 4U, // FRINTPv8f16 1U, // FRINTXDr 1U, // FRINTXHr 1U, // FRINTXSr 64U, // FRINTX_ZPmZ_D 128U, // FRINTX_ZPmZ_H 192U, // FRINTX_ZPmZ_S 2U, // FRINTXv2f32 2U, // FRINTXv2f64 3U, // FRINTXv4f16 3U, // FRINTXv4f32 4U, // FRINTXv8f16 1U, // FRINTZDr 1U, // FRINTZHr 1U, // FRINTZSr 64U, // FRINTZ_ZPmZ_D 128U, // FRINTZ_ZPmZ_H 192U, // FRINTZ_ZPmZ_S 2U, // FRINTZv2f32 2U, // FRINTZv2f64 3U, // FRINTZv4f16 3U, // FRINTZv4f32 4U, // FRINTZv8f16 1U, // FRSQRTE_ZZ_D 0U, // FRSQRTE_ZZ_H 1U, // FRSQRTE_ZZ_S 1U, // FRSQRTEv1f16 1U, // FRSQRTEv1i32 1U, // FRSQRTEv1i64 2U, // FRSQRTEv2f32 2U, // FRSQRTEv2f64 3U, // FRSQRTEv4f16 3U, // FRSQRTEv4f32 4U, // FRSQRTEv8f16 261U, // FRSQRTS16 261U, // FRSQRTS32 261U, // FRSQRTS64 901U, // FRSQRTS_ZZZ_D 137U, // FRSQRTS_ZZZ_H 1029U, // FRSQRTS_ZZZ_S 41287U, // FRSQRTSv2f32 8517U, // FRSQRTSv2f64 49480U, // FRSQRTSv4f16 16710U, // FRSQRTSv4f32 24902U, // FRSQRTSv8f16 598912U, // FSCALE_ZPmZ_D 1131465U, // FSCALE_ZPmZ_H 1647616U, // FSCALE_ZPmZ_S 1U, // FSQRTDr 1U, // FSQRTHr 1U, // FSQRTSr 64U, // FSQRT_ZPmZ_D 128U, // FSQRT_ZPmZ_H 192U, // FSQRT_ZPmZ_S 2U, // FSQRTv2f32 2U, // FSQRTv2f64 3U, // FSQRTv4f16 3U, // FSQRTv4f32 4U, // FSQRTv8f16 261U, // FSUBDrr 261U, // FSUBHrr 5317504U, // FSUBR_ZPmI_D 140233U, // FSUBR_ZPmI_H 5317632U, // FSUBR_ZPmI_S 598912U, // FSUBR_ZPmZ_D 1131465U, // FSUBR_ZPmZ_H 1647616U, // FSUBR_ZPmZ_S 261U, // FSUBSrr 5317504U, // FSUB_ZPmI_D 140233U, // FSUB_ZPmI_H 5317632U, // FSUB_ZPmI_S 598912U, // FSUB_ZPmZ_D 1131465U, // FSUB_ZPmZ_H 1647616U, // FSUB_ZPmZ_S 901U, // FSUB_ZZZ_D 137U, // FSUB_ZZZ_H 1029U, // FSUB_ZZZ_S 41287U, // FSUBv2f32 8517U, // FSUBv2f64 49480U, // FSUBv4f16 16710U, // FSUBv4f32 24902U, // FSUBv8f16 2171781U, // FTMAD_ZZI_D 91081U, // FTMAD_ZZI_H 2171909U, // FTMAD_ZZI_S 901U, // FTSMUL_ZZZ_D 137U, // FTSMUL_ZZZ_H 1029U, // FTSMUL_ZZZ_S 901U, // FTSSEL_ZZZ_D 137U, // FTSSEL_ZZZ_H 1029U, // FTSSEL_ZZZ_S 3153U, // GLD1B_D_IMM_REAL 3205U, // GLD1B_D_REAL 3269U, // GLD1B_D_SXTW_REAL 3333U, // GLD1B_D_UXTW_REAL 3153U, // GLD1B_S_IMM_REAL 3397U, // GLD1B_S_SXTW_REAL 3461U, // GLD1B_S_UXTW_REAL 26U, // GLD1D_IMM_REAL 3205U, // GLD1D_REAL 3525U, // GLD1D_SCALED_REAL 3269U, // GLD1D_SXTW_REAL 3589U, // GLD1D_SXTW_SCALED_REAL 3333U, // GLD1D_UXTW_REAL 3653U, // GLD1D_UXTW_SCALED_REAL 26U, // GLD1H_D_IMM_REAL 3205U, // GLD1H_D_REAL 3717U, // GLD1H_D_SCALED_REAL 3269U, // GLD1H_D_SXTW_REAL 3781U, // GLD1H_D_SXTW_SCALED_REAL 3333U, // GLD1H_D_UXTW_REAL 3845U, // GLD1H_D_UXTW_SCALED_REAL 26U, // GLD1H_S_IMM_REAL 3397U, // GLD1H_S_SXTW_REAL 3909U, // GLD1H_S_SXTW_SCALED_REAL 3461U, // GLD1H_S_UXTW_REAL 3973U, // GLD1H_S_UXTW_SCALED_REAL 3153U, // GLD1SB_D_IMM_REAL 3205U, // GLD1SB_D_REAL 3269U, // GLD1SB_D_SXTW_REAL 3333U, // GLD1SB_D_UXTW_REAL 3153U, // GLD1SB_S_IMM_REAL 3397U, // GLD1SB_S_SXTW_REAL 3461U, // GLD1SB_S_UXTW_REAL 26U, // GLD1SH_D_IMM_REAL 3205U, // GLD1SH_D_REAL 3717U, // GLD1SH_D_SCALED_REAL 3269U, // GLD1SH_D_SXTW_REAL 3781U, // GLD1SH_D_SXTW_SCALED_REAL 3333U, // GLD1SH_D_UXTW_REAL 3845U, // GLD1SH_D_UXTW_SCALED_REAL 26U, // GLD1SH_S_IMM_REAL 3397U, // GLD1SH_S_SXTW_REAL 3909U, // GLD1SH_S_SXTW_SCALED_REAL 3461U, // GLD1SH_S_UXTW_REAL 3973U, // GLD1SH_S_UXTW_SCALED_REAL 27U, // GLD1SW_D_IMM_REAL 3205U, // GLD1SW_D_REAL 4037U, // GLD1SW_D_SCALED_REAL 3269U, // GLD1SW_D_SXTW_REAL 4101U, // GLD1SW_D_SXTW_SCALED_REAL 3333U, // GLD1SW_D_UXTW_REAL 4165U, // GLD1SW_D_UXTW_SCALED_REAL 27U, // GLD1W_D_IMM_REAL 3205U, // GLD1W_D_REAL 4037U, // GLD1W_D_SCALED_REAL 3269U, // GLD1W_D_SXTW_REAL 4101U, // GLD1W_D_SXTW_SCALED_REAL 3333U, // GLD1W_D_UXTW_REAL 4165U, // GLD1W_D_UXTW_SCALED_REAL 27U, // GLD1W_IMM_REAL 3397U, // GLD1W_SXTW_REAL 4229U, // GLD1W_SXTW_SCALED_REAL 3461U, // GLD1W_UXTW_REAL 4293U, // GLD1W_UXTW_SCALED_REAL 3153U, // GLDFF1B_D_IMM_REAL 3205U, // GLDFF1B_D_REAL 3269U, // GLDFF1B_D_SXTW_REAL 3333U, // GLDFF1B_D_UXTW_REAL 3153U, // GLDFF1B_S_IMM_REAL 3397U, // GLDFF1B_S_SXTW_REAL 3461U, // GLDFF1B_S_UXTW_REAL 26U, // GLDFF1D_IMM_REAL 3205U, // GLDFF1D_REAL 3525U, // GLDFF1D_SCALED_REAL 3269U, // GLDFF1D_SXTW_REAL 3589U, // GLDFF1D_SXTW_SCALED_REAL 3333U, // GLDFF1D_UXTW_REAL 3653U, // GLDFF1D_UXTW_SCALED_REAL 26U, // GLDFF1H_D_IMM_REAL 3205U, // GLDFF1H_D_REAL 3717U, // GLDFF1H_D_SCALED_REAL 3269U, // GLDFF1H_D_SXTW_REAL 3781U, // GLDFF1H_D_SXTW_SCALED_REAL 3333U, // GLDFF1H_D_UXTW_REAL 3845U, // GLDFF1H_D_UXTW_SCALED_REAL 26U, // GLDFF1H_S_IMM_REAL 3397U, // GLDFF1H_S_SXTW_REAL 3909U, // GLDFF1H_S_SXTW_SCALED_REAL 3461U, // GLDFF1H_S_UXTW_REAL 3973U, // GLDFF1H_S_UXTW_SCALED_REAL 3153U, // GLDFF1SB_D_IMM_REAL 3205U, // GLDFF1SB_D_REAL 3269U, // GLDFF1SB_D_SXTW_REAL 3333U, // GLDFF1SB_D_UXTW_REAL 3153U, // GLDFF1SB_S_IMM_REAL 3397U, // GLDFF1SB_S_SXTW_REAL 3461U, // GLDFF1SB_S_UXTW_REAL 26U, // GLDFF1SH_D_IMM_REAL 3205U, // GLDFF1SH_D_REAL 3717U, // GLDFF1SH_D_SCALED_REAL 3269U, // GLDFF1SH_D_SXTW_REAL 3781U, // GLDFF1SH_D_SXTW_SCALED_REAL 3333U, // GLDFF1SH_D_UXTW_REAL 3845U, // GLDFF1SH_D_UXTW_SCALED_REAL 26U, // GLDFF1SH_S_IMM_REAL 3397U, // GLDFF1SH_S_SXTW_REAL 3909U, // GLDFF1SH_S_SXTW_SCALED_REAL 3461U, // GLDFF1SH_S_UXTW_REAL 3973U, // GLDFF1SH_S_UXTW_SCALED_REAL 27U, // GLDFF1SW_D_IMM_REAL 3205U, // GLDFF1SW_D_REAL 4037U, // GLDFF1SW_D_SCALED_REAL 3269U, // GLDFF1SW_D_SXTW_REAL 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL 3333U, // GLDFF1SW_D_UXTW_REAL 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL 27U, // GLDFF1W_D_IMM_REAL 3205U, // GLDFF1W_D_REAL 4037U, // GLDFF1W_D_SCALED_REAL 3269U, // GLDFF1W_D_SXTW_REAL 4101U, // GLDFF1W_D_SXTW_SCALED_REAL 3333U, // GLDFF1W_D_UXTW_REAL 4165U, // GLDFF1W_D_UXTW_SCALED_REAL 27U, // GLDFF1W_IMM_REAL 3397U, // GLDFF1W_SXTW_REAL 4229U, // GLDFF1W_SXTW_SCALED_REAL 3461U, // GLDFF1W_UXTW_REAL 4293U, // GLDFF1W_UXTW_SCALED_REAL 0U, // HINT 0U, // HLT 0U, // HVC 0U, // INCB_XPiI 0U, // INCD_XPiI 0U, // INCD_ZPiI 0U, // INCH_XPiI 0U, // INCH_ZPiI 1U, // INCP_XP_B 1U, // INCP_XP_D 1U, // INCP_XP_H 1U, // INCP_XP_S 1U, // INCP_ZP_D 0U, // INCP_ZP_H 1U, // INCP_ZP_S 0U, // INCW_XPiI 0U, // INCW_ZPiI 261U, // INDEX_II_B 261U, // INDEX_II_D 11U, // INDEX_II_H 261U, // INDEX_II_S 261U, // INDEX_IR_B 261U, // INDEX_IR_D 11U, // INDEX_IR_H 261U, // INDEX_IR_S 261U, // INDEX_RI_B 261U, // INDEX_RI_D 11U, // INDEX_RI_H 261U, // INDEX_RI_S 261U, // INDEX_RR_B 261U, // INDEX_RR_D 11U, // INDEX_RR_H 261U, // INDEX_RR_S 1U, // INSR_ZR_B 1U, // INSR_ZR_D 0U, // INSR_ZR_H 1U, // INSR_ZR_S 1U, // INSR_ZV_B 1U, // INSR_ZV_D 0U, // INSR_ZV_H 1U, // INSR_ZV_S 1U, // INSvi16gpr 2898U, // INSvi16lane 1U, // INSvi32gpr 2898U, // INSvi32lane 1U, // INSvi64gpr 2899U, // INSvi64lane 1U, // INSvi8gpr 2899U, // INSvi8lane 0U, // ISB 837U, // LASTA_RPZ_B 901U, // LASTA_RPZ_D 2245U, // LASTA_RPZ_H 1029U, // LASTA_RPZ_S 837U, // LASTA_VPZ_B 901U, // LASTA_VPZ_D 2245U, // LASTA_VPZ_H 1029U, // LASTA_VPZ_S 837U, // LASTB_RPZ_B 901U, // LASTB_RPZ_D 2245U, // LASTB_RPZ_H 1029U, // LASTB_RPZ_S 837U, // LASTB_VPZ_B 901U, // LASTB_VPZ_D 2245U, // LASTB_VPZ_H 1029U, // LASTB_VPZ_S 4357U, // LD1B 4357U, // LD1B_D 256261U, // LD1B_D_IMM_REAL 4357U, // LD1B_H 256261U, // LD1B_H_IMM_REAL 256261U, // LD1B_IMM_REAL 4357U, // LD1B_S 256261U, // LD1B_S_IMM_REAL 4421U, // LD1D 256261U, // LD1D_IMM_REAL 0U, // LD1Fourv16b 0U, // LD1Fourv16b_POST 0U, // LD1Fourv1d 0U, // LD1Fourv1d_POST 0U, // LD1Fourv2d 0U, // LD1Fourv2d_POST 0U, // LD1Fourv2s 0U, // LD1Fourv2s_POST 0U, // LD1Fourv4h 0U, // LD1Fourv4h_POST 0U, // LD1Fourv4s 0U, // LD1Fourv4s_POST 0U, // LD1Fourv8b 0U, // LD1Fourv8b_POST 0U, // LD1Fourv8h 0U, // LD1Fourv8h_POST 4485U, // LD1H 4485U, // LD1H_D 256261U, // LD1H_D_IMM_REAL 256261U, // LD1H_IMM_REAL 4485U, // LD1H_S 256261U, // LD1H_S_IMM_REAL 0U, // LD1Onev16b 0U, // LD1Onev16b_POST 0U, // LD1Onev1d 0U, // LD1Onev1d_POST 0U, // LD1Onev2d 0U, // LD1Onev2d_POST 0U, // LD1Onev2s 0U, // LD1Onev2s_POST 0U, // LD1Onev4h 0U, // LD1Onev4h_POST 0U, // LD1Onev4s 0U, // LD1Onev4s_POST 0U, // LD1Onev8b 0U, // LD1Onev8b_POST 0U, // LD1Onev8h 0U, // LD1Onev8h_POST 116997U, // LD1RB_D_IMM 116997U, // LD1RB_H_IMM 116997U, // LD1RB_IMM 116997U, // LD1RB_S_IMM 119237U, // LD1RD_IMM 119301U, // LD1RH_D_IMM 119301U, // LD1RH_IMM 119301U, // LD1RH_S_IMM 4357U, // LD1RQ_B 4677U, // LD1RQ_B_IMM 4421U, // LD1RQ_D 4677U, // LD1RQ_D_IMM 4485U, // LD1RQ_H 4677U, // LD1RQ_H_IMM 4741U, // LD1RQ_W 4677U, // LD1RQ_W_IMM 116997U, // LD1RSB_D_IMM 116997U, // LD1RSB_H_IMM 116997U, // LD1RSB_S_IMM 119301U, // LD1RSH_D_IMM 119301U, // LD1RSH_S_IMM 119493U, // LD1RSW_IMM 119493U, // LD1RW_D_IMM 119493U, // LD1RW_IMM 0U, // LD1Rv16b 0U, // LD1Rv16b_POST 0U, // LD1Rv1d 0U, // LD1Rv1d_POST 0U, // LD1Rv2d 0U, // LD1Rv2d_POST 0U, // LD1Rv2s 0U, // LD1Rv2s_POST 0U, // LD1Rv4h 0U, // LD1Rv4h_POST 0U, // LD1Rv4s 0U, // LD1Rv4s_POST 0U, // LD1Rv8b 0U, // LD1Rv8b_POST 0U, // LD1Rv8h 0U, // LD1Rv8h_POST 4357U, // LD1SB_D 256261U, // LD1SB_D_IMM_REAL 4357U, // LD1SB_H 256261U, // LD1SB_H_IMM_REAL 4357U, // LD1SB_S 256261U, // LD1SB_S_IMM_REAL 4485U, // LD1SH_D 256261U, // LD1SH_D_IMM_REAL 4485U, // LD1SH_S 256261U, // LD1SH_S_IMM_REAL 4741U, // LD1SW_D 256261U, // LD1SW_D_IMM_REAL 0U, // LD1Threev16b 0U, // LD1Threev16b_POST 0U, // LD1Threev1d 0U, // LD1Threev1d_POST 0U, // LD1Threev2d 0U, // LD1Threev2d_POST 0U, // LD1Threev2s 0U, // LD1Threev2s_POST 0U, // LD1Threev4h 0U, // LD1Threev4h_POST 0U, // LD1Threev4s 0U, // LD1Threev4s_POST 0U, // LD1Threev8b 0U, // LD1Threev8b_POST 0U, // LD1Threev8h 0U, // LD1Threev8h_POST 0U, // LD1Twov16b 0U, // LD1Twov16b_POST 0U, // LD1Twov1d 0U, // LD1Twov1d_POST 0U, // LD1Twov2d 0U, // LD1Twov2d_POST 0U, // LD1Twov2s 0U, // LD1Twov2s_POST 0U, // LD1Twov4h 0U, // LD1Twov4h_POST 0U, // LD1Twov4s 0U, // LD1Twov4s_POST 0U, // LD1Twov8b 0U, // LD1Twov8b_POST 0U, // LD1Twov8h 0U, // LD1Twov8h_POST 4741U, // LD1W 4741U, // LD1W_D 256261U, // LD1W_D_IMM_REAL 256261U, // LD1W_IMM_REAL 0U, // LD1i16 0U, // LD1i16_POST 0U, // LD1i32 0U, // LD1i32_POST 0U, // LD1i64 0U, // LD1i64_POST 0U, // LD1i8 0U, // LD1i8_POST 4357U, // LD2B 258565U, // LD2B_IMM 4421U, // LD2D 258565U, // LD2D_IMM 4485U, // LD2H 258565U, // LD2H_IMM 0U, // LD2Rv16b 0U, // LD2Rv16b_POST 0U, // LD2Rv1d 0U, // LD2Rv1d_POST 0U, // LD2Rv2d 0U, // LD2Rv2d_POST 0U, // LD2Rv2s 0U, // LD2Rv2s_POST 0U, // LD2Rv4h 0U, // LD2Rv4h_POST 0U, // LD2Rv4s 0U, // LD2Rv4s_POST 0U, // LD2Rv8b 0U, // LD2Rv8b_POST 0U, // LD2Rv8h 0U, // LD2Rv8h_POST 0U, // LD2Twov16b 0U, // LD2Twov16b_POST 0U, // LD2Twov2d 0U, // LD2Twov2d_POST 0U, // LD2Twov2s 0U, // LD2Twov2s_POST 0U, // LD2Twov4h 0U, // LD2Twov4h_POST 0U, // LD2Twov4s 0U, // LD2Twov4s_POST 0U, // LD2Twov8b 0U, // LD2Twov8b_POST 0U, // LD2Twov8h 0U, // LD2Twov8h_POST 4741U, // LD2W 258565U, // LD2W_IMM 0U, // LD2i16 0U, // LD2i16_POST 0U, // LD2i32 0U, // LD2i32_POST 0U, // LD2i64 0U, // LD2i64_POST 0U, // LD2i8 0U, // LD2i8_POST 4357U, // LD3B 4869U, // LD3B_IMM 4421U, // LD3D 4869U, // LD3D_IMM 4485U, // LD3H 4869U, // LD3H_IMM 0U, // LD3Rv16b 0U, // LD3Rv16b_POST 0U, // LD3Rv1d 0U, // LD3Rv1d_POST 0U, // LD3Rv2d 0U, // LD3Rv2d_POST 0U, // LD3Rv2s 0U, // LD3Rv2s_POST 0U, // LD3Rv4h 0U, // LD3Rv4h_POST 0U, // LD3Rv4s 0U, // LD3Rv4s_POST 0U, // LD3Rv8b 0U, // LD3Rv8b_POST 0U, // LD3Rv8h 0U, // LD3Rv8h_POST 0U, // LD3Threev16b 0U, // LD3Threev16b_POST 0U, // LD3Threev2d 0U, // LD3Threev2d_POST 0U, // LD3Threev2s 0U, // LD3Threev2s_POST 0U, // LD3Threev4h 0U, // LD3Threev4h_POST 0U, // LD3Threev4s 0U, // LD3Threev4s_POST 0U, // LD3Threev8b 0U, // LD3Threev8b_POST 0U, // LD3Threev8h 0U, // LD3Threev8h_POST 4741U, // LD3W 4869U, // LD3W_IMM 0U, // LD3i16 0U, // LD3i16_POST 0U, // LD3i32 0U, // LD3i32_POST 0U, // LD3i64 0U, // LD3i64_POST 0U, // LD3i8 0U, // LD3i8_POST 4357U, // LD4B 258757U, // LD4B_IMM 4421U, // LD4D 258757U, // LD4D_IMM 0U, // LD4Fourv16b 0U, // LD4Fourv16b_POST 0U, // LD4Fourv2d 0U, // LD4Fourv2d_POST 0U, // LD4Fourv2s 0U, // LD4Fourv2s_POST 0U, // LD4Fourv4h 0U, // LD4Fourv4h_POST 0U, // LD4Fourv4s 0U, // LD4Fourv4s_POST 0U, // LD4Fourv8b 0U, // LD4Fourv8b_POST 0U, // LD4Fourv8h 0U, // LD4Fourv8h_POST 4485U, // LD4H 258757U, // LD4H_IMM 0U, // LD4Rv16b 0U, // LD4Rv16b_POST 0U, // LD4Rv1d 0U, // LD4Rv1d_POST 0U, // LD4Rv2d 0U, // LD4Rv2d_POST 0U, // LD4Rv2s 0U, // LD4Rv2s_POST 0U, // LD4Rv4h 0U, // LD4Rv4h_POST 0U, // LD4Rv4s 0U, // LD4Rv4s_POST 0U, // LD4Rv8b 0U, // LD4Rv8b_POST 0U, // LD4Rv8h 0U, // LD4Rv8h_POST 4741U, // LD4W 258757U, // LD4W_IMM 0U, // LD4i16 0U, // LD4i16_POST 0U, // LD4i32 0U, // LD4i32_POST 0U, // LD4i64 0U, // LD4i64_POST 0U, // LD4i8 0U, // LD4i8_POST 0U, // LDADDAB 0U, // LDADDAH 0U, // LDADDALB 0U, // LDADDALH 0U, // LDADDALW 0U, // LDADDALX 0U, // LDADDAW 0U, // LDADDAX 0U, // LDADDB 0U, // LDADDH 0U, // LDADDLB 0U, // LDADDLH 0U, // LDADDLW 0U, // LDADDLX 0U, // LDADDW 0U, // LDADDX 27U, // LDAPRB 27U, // LDAPRH 27U, // LDAPRW 27U, // LDAPRX 114949U, // LDAPURBi 114949U, // LDAPURHi 114949U, // LDAPURSBWi 114949U, // LDAPURSBXi 114949U, // LDAPURSHWi 114949U, // LDAPURSHXi 114949U, // LDAPURSWi 114949U, // LDAPURXi 114949U, // LDAPURi 27U, // LDARB 27U, // LDARH 27U, // LDARW 27U, // LDARX 114955U, // LDAXPW 114955U, // LDAXPX 27U, // LDAXRB 27U, // LDAXRH 27U, // LDAXRW 27U, // LDAXRX 0U, // LDCLRAB 0U, // LDCLRAH 0U, // LDCLRALB 0U, // LDCLRALH 0U, // LDCLRALW 0U, // LDCLRALX 0U, // LDCLRAW 0U, // LDCLRAX 0U, // LDCLRB 0U, // LDCLRH 0U, // LDCLRLB 0U, // LDCLRLH 0U, // LDCLRLW 0U, // LDCLRLX 0U, // LDCLRW 0U, // LDCLRX 0U, // LDEORAB 0U, // LDEORAH 0U, // LDEORALB 0U, // LDEORALH 0U, // LDEORALW 0U, // LDEORALX 0U, // LDEORAW 0U, // LDEORAX 0U, // LDEORB 0U, // LDEORH 0U, // LDEORLB 0U, // LDEORLH 0U, // LDEORLW 0U, // LDEORLX 0U, // LDEORW 0U, // LDEORX 4357U, // LDFF1B_D_REAL 4357U, // LDFF1B_H_REAL 4357U, // LDFF1B_REAL 4357U, // LDFF1B_S_REAL 4421U, // LDFF1D_REAL 4485U, // LDFF1H_D_REAL 4485U, // LDFF1H_REAL 4485U, // LDFF1H_S_REAL 4357U, // LDFF1SB_D_REAL 4357U, // LDFF1SB_H_REAL 4357U, // LDFF1SB_S_REAL 4485U, // LDFF1SH_D_REAL 4485U, // LDFF1SH_S_REAL 4741U, // LDFF1SW_D_REAL 4741U, // LDFF1W_D_REAL 4741U, // LDFF1W_REAL 27U, // LDLARB 27U, // LDLARH 27U, // LDLARW 27U, // LDLARX 256261U, // LDNF1B_D_IMM_REAL 256261U, // LDNF1B_H_IMM_REAL 256261U, // LDNF1B_IMM_REAL 256261U, // LDNF1B_S_IMM_REAL 256261U, // LDNF1D_IMM_REAL 256261U, // LDNF1H_D_IMM_REAL 256261U, // LDNF1H_IMM_REAL 256261U, // LDNF1H_S_IMM_REAL 256261U, // LDNF1SB_D_IMM_REAL 256261U, // LDNF1SB_H_IMM_REAL 256261U, // LDNF1SB_S_IMM_REAL 256261U, // LDNF1SH_D_IMM_REAL 256261U, // LDNF1SH_S_IMM_REAL 256261U, // LDNF1SW_D_IMM_REAL 256261U, // LDNF1W_D_IMM_REAL 256261U, // LDNF1W_IMM_REAL 11084043U, // LDNPDi 11608331U, // LDNPQi 12132619U, // LDNPSi 12132619U, // LDNPWi 11084043U, // LDNPXi 256261U, // LDNT1B_ZRI 4357U, // LDNT1B_ZRR 256261U, // LDNT1D_ZRI 4421U, // LDNT1D_ZRR 256261U, // LDNT1H_ZRI 4485U, // LDNT1H_ZRR 256261U, // LDNT1W_ZRI 4741U, // LDNT1W_ZRR 11084043U, // LDPDi 12847371U, // LDPDpost 180431115U, // LDPDpre 11608331U, // LDPQi 13371659U, // LDPQpost 180955403U, // LDPQpre 12132619U, // LDPSWi 13895947U, // LDPSWpost 181479691U, // LDPSWpre 12132619U, // LDPSi 13895947U, // LDPSpost 181479691U, // LDPSpre 12132619U, // LDPWi 13895947U, // LDPWpost 181479691U, // LDPWpre 11084043U, // LDPXi 12847371U, // LDPXpost 180431115U, // LDPXpre 4933U, // LDRAAindexed 274885U, // LDRAAwriteback 4933U, // LDRABindexed 274885U, // LDRABwriteback 28U, // LDRBBpost 272645U, // LDRBBpre 14229765U, // LDRBBroW 14754053U, // LDRBBroX 4997U, // LDRBBui 28U, // LDRBpost 272645U, // LDRBpre 14229765U, // LDRBroW 14754053U, // LDRBroX 4997U, // LDRBui 0U, // LDRDl 28U, // LDRDpost 272645U, // LDRDpre 15278341U, // LDRDroW 15802629U, // LDRDroX 5061U, // LDRDui 28U, // LDRHHpost 272645U, // LDRHHpre 16326917U, // LDRHHroW 16851205U, // LDRHHroX 5125U, // LDRHHui 28U, // LDRHpost 272645U, // LDRHpre 16326917U, // LDRHroW 16851205U, // LDRHroX 5125U, // LDRHui 0U, // LDRQl 28U, // LDRQpost 272645U, // LDRQpre 17375493U, // LDRQroW 17899781U, // LDRQroX 5189U, // LDRQui 28U, // LDRSBWpost 272645U, // LDRSBWpre 14229765U, // LDRSBWroW 14754053U, // LDRSBWroX 4997U, // LDRSBWui 28U, // LDRSBXpost 272645U, // LDRSBXpre 14229765U, // LDRSBXroW 14754053U, // LDRSBXroX 4997U, // LDRSBXui 28U, // LDRSHWpost 272645U, // LDRSHWpre 16326917U, // LDRSHWroW 16851205U, // LDRSHWroX 5125U, // LDRSHWui 28U, // LDRSHXpost 272645U, // LDRSHXpre 16326917U, // LDRSHXroW 16851205U, // LDRSHXroX 5125U, // LDRSHXui 0U, // LDRSWl 28U, // LDRSWpost 272645U, // LDRSWpre 18424069U, // LDRSWroW 18948357U, // LDRSWroX 5253U, // LDRSWui 0U, // LDRSl 28U, // LDRSpost 272645U, // LDRSpre 18424069U, // LDRSroW 18948357U, // LDRSroX 5253U, // LDRSui 0U, // LDRWl 28U, // LDRWpost 272645U, // LDRWpre 18424069U, // LDRWroW 18948357U, // LDRWroX 5253U, // LDRWui 0U, // LDRXl 28U, // LDRXpost 272645U, // LDRXpre 15278341U, // LDRXroW 15802629U, // LDRXroX 5061U, // LDRXui 254213U, // LDR_PXI 254213U, // LDR_ZXI 0U, // LDSETAB 0U, // LDSETAH 0U, // LDSETALB 0U, // LDSETALH 0U, // LDSETALW 0U, // LDSETALX 0U, // LDSETAW 0U, // LDSETAX 0U, // LDSETB 0U, // LDSETH 0U, // LDSETLB 0U, // LDSETLH 0U, // LDSETLW 0U, // LDSETLX 0U, // LDSETW 0U, // LDSETX 0U, // LDSMAXAB 0U, // LDSMAXAH 0U, // LDSMAXALB 0U, // LDSMAXALH 0U, // LDSMAXALW 0U, // LDSMAXALX 0U, // LDSMAXAW 0U, // LDSMAXAX 0U, // LDSMAXB 0U, // LDSMAXH 0U, // LDSMAXLB 0U, // LDSMAXLH 0U, // LDSMAXLW 0U, // LDSMAXLX 0U, // LDSMAXW 0U, // LDSMAXX 0U, // LDSMINAB 0U, // LDSMINAH 0U, // LDSMINALB 0U, // LDSMINALH 0U, // LDSMINALW 0U, // LDSMINALX 0U, // LDSMINAW 0U, // LDSMINAX 0U, // LDSMINB 0U, // LDSMINH 0U, // LDSMINLB 0U, // LDSMINLH 0U, // LDSMINLW 0U, // LDSMINLX 0U, // LDSMINW 0U, // LDSMINX 114949U, // LDTRBi 114949U, // LDTRHi 114949U, // LDTRSBWi 114949U, // LDTRSBXi 114949U, // LDTRSHWi 114949U, // LDTRSHXi 114949U, // LDTRSWi 114949U, // LDTRWi 114949U, // LDTRXi 0U, // LDUMAXAB 0U, // LDUMAXAH 0U, // LDUMAXALB 0U, // LDUMAXALH 0U, // LDUMAXALW 0U, // LDUMAXALX 0U, // LDUMAXAW 0U, // LDUMAXAX 0U, // LDUMAXB 0U, // LDUMAXH 0U, // LDUMAXLB 0U, // LDUMAXLH 0U, // LDUMAXLW 0U, // LDUMAXLX 0U, // LDUMAXW 0U, // LDUMAXX 0U, // LDUMINAB 0U, // LDUMINAH 0U, // LDUMINALB 0U, // LDUMINALH 0U, // LDUMINALW 0U, // LDUMINALX 0U, // LDUMINAW 0U, // LDUMINAX 0U, // LDUMINB 0U, // LDUMINH 0U, // LDUMINLB 0U, // LDUMINLH 0U, // LDUMINLW 0U, // LDUMINLX 0U, // LDUMINW 0U, // LDUMINX 114949U, // LDURBBi 114949U, // LDURBi 114949U, // LDURDi 114949U, // LDURHHi 114949U, // LDURHi 114949U, // LDURQi 114949U, // LDURSBWi 114949U, // LDURSBXi 114949U, // LDURSHWi 114949U, // LDURSHXi 114949U, // LDURSWi 114949U, // LDURSi 114949U, // LDURWi 114949U, // LDURXi 114955U, // LDXPW 114955U, // LDXPX 27U, // LDXRB 27U, // LDXRH 27U, // LDXRW 27U, // LDXRX 0U, // LOADgot 74560U, // LSLR_ZPmZ_B 598912U, // LSLR_ZPmZ_D 1131465U, // LSLR_ZPmZ_H 1647616U, // LSLR_ZPmZ_S 261U, // LSLVWr 261U, // LSLVXr 598848U, // LSL_WIDE_ZPmZ_B 99273U, // LSL_WIDE_ZPmZ_H 599040U, // LSL_WIDE_ZPmZ_S 901U, // LSL_WIDE_ZZZ_B 10U, // LSL_WIDE_ZZZ_H 901U, // LSL_WIDE_ZZZ_S 2171712U, // LSL_ZPmI_B 2171776U, // LSL_ZPmI_D 91081U, // LSL_ZPmI_H 2171904U, // LSL_ZPmI_S 74560U, // LSL_ZPmZ_B 598912U, // LSL_ZPmZ_D 1131465U, // LSL_ZPmZ_H 1647616U, // LSL_ZPmZ_S 261U, // LSL_ZZI_B 261U, // LSL_ZZI_D 11U, // LSL_ZZI_H 261U, // LSL_ZZI_S 74560U, // LSRR_ZPmZ_B 598912U, // LSRR_ZPmZ_D 1131465U, // LSRR_ZPmZ_H 1647616U, // LSRR_ZPmZ_S 261U, // LSRVWr 261U, // LSRVXr 598848U, // LSR_WIDE_ZPmZ_B 99273U, // LSR_WIDE_ZPmZ_H 599040U, // LSR_WIDE_ZPmZ_S 901U, // LSR_WIDE_ZZZ_B 10U, // LSR_WIDE_ZZZ_H 901U, // LSR_WIDE_ZZZ_S 2171712U, // LSR_ZPmI_B 2171776U, // LSR_ZPmI_D 91081U, // LSR_ZPmI_H 2171904U, // LSR_ZPmI_S 74560U, // LSR_ZPmZ_B 598912U, // LSR_ZPmZ_D 1131465U, // LSR_ZPmZ_H 1647616U, // LSR_ZPmZ_S 261U, // LSR_ZZI_B 261U, // LSR_ZZI_D 11U, // LSR_ZZI_H 261U, // LSR_ZZI_S 2171141U, // MADDWrrr 2171141U, // MADDXrrr 19472384U, // MAD_ZPmZZ_B 6889536U, // MAD_ZPmZZ_D 1246144U, // MAD_ZPmZZ_H 7413952U, // MAD_ZPmZZ_S 19472384U, // MLA_ZPmZZ_B 6889536U, // MLA_ZPmZZ_D 1246144U, // MLA_ZPmZZ_H 7413952U, // MLA_ZPmZZ_S 33159U, // MLAv16i8 41351U, // MLAv2i32 9126279U, // MLAv2i32_indexed 49544U, // MLAv4i16 9118088U, // MLAv4i16_indexed 16774U, // MLAv4i32 9126278U, // MLAv4i32_indexed 24966U, // MLAv8i16 9118086U, // MLAv8i16_indexed 57736U, // MLAv8i8 19472384U, // MLS_ZPmZZ_B 6889536U, // MLS_ZPmZZ_D 1246144U, // MLS_ZPmZZ_H 7413952U, // MLS_ZPmZZ_S 33159U, // MLSv16i8 41351U, // MLSv2i32 9126279U, // MLSv2i32_indexed 49544U, // MLSv4i16 9118088U, // MLSv4i16_indexed 16774U, // MLSv4i32 9126278U, // MLSv4i32_indexed 24966U, // MLSv8i16 9118086U, // MLSv8i16_indexed 57736U, // MLSv8i8 0U, // MOVID 1U, // MOVIv16b_ns 0U, // MOVIv2d_ns 28U, // MOVIv2i32 28U, // MOVIv2s_msl 28U, // MOVIv4i16 28U, // MOVIv4i32 28U, // MOVIv4s_msl 1U, // MOVIv8b_ns 28U, // MOVIv8i16 0U, // MOVKWi 0U, // MOVKXi 28U, // MOVNWi 28U, // MOVNXi 0U, // MOVPRFX_ZPmZ_B 64U, // MOVPRFX_ZPmZ_D 128U, // MOVPRFX_ZPmZ_H 192U, // MOVPRFX_ZPmZ_S 842U, // MOVPRFX_ZPzZ_B 906U, // MOVPRFX_ZPzZ_D 137U, // MOVPRFX_ZPzZ_H 1034U, // MOVPRFX_ZPzZ_S 1U, // MOVPRFX_ZZ 28U, // MOVZWi 28U, // MOVZXi 0U, // MOVaddr 0U, // MOVaddrBA 0U, // MOVaddrCP 0U, // MOVaddrEXT 0U, // MOVaddrJT 0U, // MOVaddrTLS 0U, // MOVbaseTLS 0U, // MOVi32imm 0U, // MOVi64imm 0U, // MRS 19472384U, // MSB_ZPmZZ_B 6889536U, // MSB_ZPmZZ_D 1246144U, // MSB_ZPmZZ_H 7413952U, // MSB_ZPmZZ_S 0U, // MSR 0U, // MSRpstateImm1 0U, // MSRpstateImm4 2171141U, // MSUBWrrr 2171141U, // MSUBXrrr 261U, // MUL_ZI_B 261U, // MUL_ZI_D 11U, // MUL_ZI_H 261U, // MUL_ZI_S 74560U, // MUL_ZPmZ_B 598912U, // MUL_ZPmZ_D 1131465U, // MUL_ZPmZ_H 1647616U, // MUL_ZPmZ_S 33095U, // MULv16i8 41287U, // MULv2i32 10174791U, // MULv2i32_indexed 49480U, // MULv4i16 10166600U, // MULv4i16_indexed 16710U, // MULv4i32 10174790U, // MULv4i32_indexed 24902U, // MULv8i16 10166598U, // MULv8i16_indexed 57672U, // MULv8i8 28U, // MVNIv2i32 28U, // MVNIv2s_msl 28U, // MVNIv4i16 28U, // MVNIv4i32 28U, // MVNIv4s_msl 28U, // MVNIv8i16 74570U, // NANDS_PPzPP 74570U, // NAND_PPzPP 0U, // NEG_ZPmZ_B 64U, // NEG_ZPmZ_D 128U, // NEG_ZPmZ_H 192U, // NEG_ZPmZ_S 1U, // NEGv16i8 1U, // NEGv1i64 2U, // NEGv2i32 2U, // NEGv2i64 3U, // NEGv4i16 3U, // NEGv4i32 4U, // NEGv8i16 4U, // NEGv8i8 74570U, // NORS_PPzPP 74570U, // NOR_PPzPP 0U, // NOT_ZPmZ_B 64U, // NOT_ZPmZ_D 128U, // NOT_ZPmZ_H 192U, // NOT_ZPmZ_S 1U, // NOTv16i8 4U, // NOTv8i8 74570U, // ORNS_PPzPP 0U, // ORNWrr 517U, // ORNWrs 0U, // ORNXrr 517U, // ORNXrs 74570U, // ORN_PPzPP 33095U, // ORNv16i8 57672U, // ORNv8i8 74570U, // ORRS_PPzPP 2117U, // ORRWri 0U, // ORRWrr 517U, // ORRWrs 2181U, // ORRXri 0U, // ORRXrr 517U, // ORRXrs 74570U, // ORR_PPzPP 2181U, // ORR_ZI 74560U, // ORR_ZPmZ_B 598912U, // ORR_ZPmZ_D 1131465U, // ORR_ZPmZ_H 1647616U, // ORR_ZPmZ_S 901U, // ORR_ZZZ 33095U, // ORRv16i8 0U, // ORRv2i32 0U, // ORRv4i16 0U, // ORRv4i32 0U, // ORRv8i16 57672U, // ORRv8i8 837U, // ORV_VPZ_B 901U, // ORV_VPZ_D 2245U, // ORV_VPZ_H 1029U, // ORV_VPZ_S 1U, // PACDA 1U, // PACDB 0U, // PACDZA 0U, // PACDZB 261U, // PACGA 1U, // PACIA 0U, // PACIA1716 0U, // PACIASP 0U, // PACIAZ 1U, // PACIB 0U, // PACIB1716 0U, // PACIBSP 0U, // PACIBZ 0U, // PACIZA 0U, // PACIZB 0U, // PFALSE 33095U, // PMULLv16i8 0U, // PMULLv1i64 0U, // PMULLv2i64 57672U, // PMULLv8i8 33095U, // PMULv16i8 57672U, // PMULv8i8 837U, // PNEXT_B 901U, // PNEXT_D 137U, // PNEXT_H 1029U, // PNEXT_S 27U, // PRFB_D_PZI 29U, // PRFB_D_SCALED 29U, // PRFB_D_SXTW_SCALED 30U, // PRFB_D_UXTW_SCALED 5329U, // PRFB_PRI 30U, // PRFB_PRR 27U, // PRFB_S_PZI 31U, // PRFB_S_SXTW_SCALED 31U, // PRFB_S_UXTW_SCALED 0U, // PRFD_D_PZI 32U, // PRFD_D_SCALED 32U, // PRFD_D_SXTW_SCALED 33U, // PRFD_D_UXTW_SCALED 5329U, // PRFD_PRI 33U, // PRFD_PRR 0U, // PRFD_S_PZI 34U, // PRFD_S_SXTW_SCALED 34U, // PRFD_S_UXTW_SCALED 0U, // PRFH_D_PZI 35U, // PRFH_D_SCALED 35U, // PRFH_D_SXTW_SCALED 36U, // PRFH_D_UXTW_SCALED 5329U, // PRFH_PRI 36U, // PRFH_PRR 0U, // PRFH_S_PZI 37U, // PRFH_S_SXTW_SCALED 37U, // PRFH_S_UXTW_SCALED 0U, // PRFMl 15278341U, // PRFMroW 15802629U, // PRFMroX 5061U, // PRFMui 38U, // PRFS_PRR 114949U, // PRFUMi 0U, // PRFW_D_PZI 38U, // PRFW_D_SCALED 39U, // PRFW_D_SXTW_SCALED 39U, // PRFW_D_UXTW_SCALED 5329U, // PRFW_PRI 0U, // PRFW_S_PZI 40U, // PRFW_S_SXTW_SCALED 40U, // PRFW_S_UXTW_SCALED 1U, // PTEST_PP 1U, // PTRUES_B 1U, // PTRUES_D 0U, // PTRUES_H 1U, // PTRUES_S 1U, // PTRUE_B 1U, // PTRUE_D 0U, // PTRUE_H 1U, // PTRUE_S 0U, // PUNPKHI_PP 0U, // PUNPKLO_PP 8517U, // RADDHNv2i64_v2i32 8581U, // RADDHNv2i64_v4i32 16710U, // RADDHNv4i32_v4i16 16774U, // RADDHNv4i32_v8i16 24966U, // RADDHNv8i16_v16i8 24902U, // RADDHNv8i16_v8i8 8517U, // RAX1 1U, // RBITWr 1U, // RBITXr 0U, // RBIT_ZPmZ_B 64U, // RBIT_ZPmZ_D 128U, // RBIT_ZPmZ_H 192U, // RBIT_ZPmZ_S 1U, // RBITv16i8 4U, // RBITv8i8 41U, // RDFFRS_PPz 0U, // RDFFR_P 41U, // RDFFR_PPz 1U, // RDVLI_XI 0U, // RET 0U, // RETAA 0U, // RETAB 0U, // RET_ReallyLR 1U, // REV16Wr 1U, // REV16Xr 1U, // REV16v16i8 4U, // REV16v8i8 1U, // REV32Xr 1U, // REV32v16i8 3U, // REV32v4i16 4U, // REV32v8i16 4U, // REV32v8i8 1U, // REV64v16i8 2U, // REV64v2i32 3U, // REV64v4i16 3U, // REV64v4i32 4U, // REV64v8i16 4U, // REV64v8i8 64U, // REVB_ZPmZ_D 128U, // REVB_ZPmZ_H 192U, // REVB_ZPmZ_S 64U, // REVH_ZPmZ_D 192U, // REVH_ZPmZ_S 64U, // REVW_ZPmZ_D 1U, // REVWr 1U, // REVXr 1U, // REV_PP_B 1U, // REV_PP_D 0U, // REV_PP_H 1U, // REV_PP_S 1U, // REV_ZZ_B 1U, // REV_ZZ_D 0U, // REV_ZZ_H 1U, // REV_ZZ_S 261U, // RMIF 261U, // RORVWr 261U, // RORVXr 2310U, // RSHRNv16i8_shift 261U, // RSHRNv2i32_shift 262U, // RSHRNv4i16_shift 2309U, // RSHRNv4i32_shift 2310U, // RSHRNv8i16_shift 262U, // RSHRNv8i8_shift 8517U, // RSUBHNv2i64_v2i32 8581U, // RSUBHNv2i64_v4i32 16710U, // RSUBHNv4i32_v4i16 16774U, // RSUBHNv4i32_v8i16 24966U, // RSUBHNv8i16_v16i8 24902U, // RSUBHNv8i16_v8i8 33159U, // SABALv16i8_v8i16 41351U, // SABALv2i32_v2i64 49544U, // SABALv4i16_v4i32 16774U, // SABALv4i32_v2i64 24966U, // SABALv8i16_v4i32 57736U, // SABALv8i8_v8i16 33159U, // SABAv16i8 41351U, // SABAv2i32 49544U, // SABAv4i16 16774U, // SABAv4i32 24966U, // SABAv8i16 57736U, // SABAv8i8 33095U, // SABDLv16i8_v8i16 41287U, // SABDLv2i32_v2i64 49480U, // SABDLv4i16_v4i32 16710U, // SABDLv4i32_v2i64 24902U, // SABDLv8i16_v4i32 57672U, // SABDLv8i8_v8i16 74560U, // SABD_ZPmZ_B 598912U, // SABD_ZPmZ_D 1131465U, // SABD_ZPmZ_H 1647616U, // SABD_ZPmZ_S 33095U, // SABDv16i8 41287U, // SABDv2i32 49480U, // SABDv4i16 16710U, // SABDv4i32 24902U, // SABDv8i16 57672U, // SABDv8i8 1U, // SADALPv16i8_v8i16 2U, // SADALPv2i32_v1i64 3U, // SADALPv4i16_v2i32 3U, // SADALPv4i32_v2i64 4U, // SADALPv8i16_v4i32 4U, // SADALPv8i8_v4i16 1U, // SADDLPv16i8_v8i16 2U, // SADDLPv2i32_v1i64 3U, // SADDLPv4i16_v2i32 3U, // SADDLPv4i32_v2i64 4U, // SADDLPv8i16_v4i32 4U, // SADDLPv8i8_v4i16 1U, // SADDLVv16i8v 3U, // SADDLVv4i16v 3U, // SADDLVv4i32v 4U, // SADDLVv8i16v 4U, // SADDLVv8i8v 33095U, // SADDLv16i8_v8i16 41287U, // SADDLv2i32_v2i64 49480U, // SADDLv4i16_v4i32 16710U, // SADDLv4i32_v2i64 24902U, // SADDLv8i16_v4i32 57672U, // SADDLv8i8_v8i16 837U, // SADDV_VPZ_B 2245U, // SADDV_VPZ_H 1029U, // SADDV_VPZ_S 33094U, // SADDWv16i8_v8i16 41285U, // SADDWv2i32_v2i64 49478U, // SADDWv4i16_v4i32 16709U, // SADDWv4i32_v2i64 24902U, // SADDWv8i16_v4i32 57670U, // SADDWv8i8_v8i16 261U, // SBCSWr 261U, // SBCSXr 261U, // SBCWr 261U, // SBCXr 2171141U, // SBFMWri 2171141U, // SBFMXri 261U, // SCVTFSWDri 261U, // SCVTFSWHri 261U, // SCVTFSWSri 261U, // SCVTFSXDri 261U, // SCVTFSXHri 261U, // SCVTFSXSri 1U, // SCVTFUWDri 1U, // SCVTFUWHri 1U, // SCVTFUWSri 1U, // SCVTFUXDri 1U, // SCVTFUXHri 1U, // SCVTFUXSri 64U, // SCVTF_ZPmZ_DtoD 153U, // SCVTF_ZPmZ_DtoH 64U, // SCVTF_ZPmZ_DtoS 128U, // SCVTF_ZPmZ_HtoH 192U, // SCVTF_ZPmZ_StoD 152U, // SCVTF_ZPmZ_StoH 192U, // SCVTF_ZPmZ_StoS 261U, // SCVTFd 261U, // SCVTFh 261U, // SCVTFs 1U, // SCVTFv1i16 1U, // SCVTFv1i32 1U, // SCVTFv1i64 2U, // SCVTFv2f32 2U, // SCVTFv2f64 263U, // SCVTFv2i32_shift 261U, // SCVTFv2i64_shift 3U, // SCVTFv4f16 3U, // SCVTFv4f32 264U, // SCVTFv4i16_shift 262U, // SCVTFv4i32_shift 4U, // SCVTFv8f16 262U, // SCVTFv8i16_shift 598912U, // SDIVR_ZPmZ_D 1647616U, // SDIVR_ZPmZ_S 261U, // SDIVWr 261U, // SDIVXr 598912U, // SDIV_ZPmZ_D 1647616U, // SDIV_ZPmZ_S 41U, // SDOT_ZZZI_D 41U, // SDOT_ZZZI_S 1U, // SDOT_ZZZ_D 1U, // SDOT_ZZZ_S 278919U, // SDOTlanev16i8 278920U, // SDOTlanev8i8 33159U, // SDOTv16i8 57736U, // SDOTv8i8 74565U, // SEL_PPPP 74565U, // SEL_ZPZZ_B 598917U, // SEL_ZPZZ_D 1131465U, // SEL_ZPZZ_H 1647621U, // SEL_ZPZZ_S 0U, // SETF16 0U, // SETF8 0U, // SETFFR 16773U, // SHA1Crrr 1U, // SHA1Hrr 16773U, // SHA1Mrrr 16773U, // SHA1Prrr 16774U, // SHA1SU0rrr 3U, // SHA1SU1rr 16773U, // SHA256H2rrr 16773U, // SHA256Hrrr 3U, // SHA256SU0rr 16774U, // SHA256SU1rrr 8581U, // SHA512H 8581U, // SHA512H2 2U, // SHA512SU0 8581U, // SHA512SU1 33095U, // SHADDv16i8 41287U, // SHADDv2i32 49480U, // SHADDv4i16 16710U, // SHADDv4i32 24902U, // SHADDv8i16 57672U, // SHADDv8i8 42U, // SHLLv16i8 42U, // SHLLv2i32 43U, // SHLLv4i16 43U, // SHLLv4i32 44U, // SHLLv8i16 44U, // SHLLv8i8 261U, // SHLd 263U, // SHLv16i8_shift 263U, // SHLv2i32_shift 261U, // SHLv2i64_shift 264U, // SHLv4i16_shift 262U, // SHLv4i32_shift 262U, // SHLv8i16_shift 264U, // SHLv8i8_shift 2310U, // SHRNv16i8_shift 261U, // SHRNv2i32_shift 262U, // SHRNv4i16_shift 2309U, // SHRNv4i32_shift 2310U, // SHRNv8i16_shift 262U, // SHRNv8i8_shift 33095U, // SHSUBv16i8 41287U, // SHSUBv2i32 49480U, // SHSUBv4i16 16710U, // SHSUBv4i32 24902U, // SHSUBv8i16 57672U, // SHSUBv8i8 2309U, // SLId 2311U, // SLIv16i8_shift 2311U, // SLIv2i32_shift 2309U, // SLIv2i64_shift 2312U, // SLIv4i16_shift 2310U, // SLIv4i32_shift 2310U, // SLIv8i16_shift 2312U, // SLIv8i8_shift 16774U, // SM3PARTW1 16774U, // SM3PARTW2 204120390U, // SM3SS1 9126278U, // SM3TT1A 9126278U, // SM3TT1B 9126278U, // SM3TT2A 9126278U, // SM3TT2B 3U, // SM4E 16710U, // SM4ENCKEY 2171141U, // SMADDLrrr 33095U, // SMAXPv16i8 41287U, // SMAXPv2i32 49480U, // SMAXPv4i16 16710U, // SMAXPv4i32 24902U, // SMAXPv8i16 57672U, // SMAXPv8i8 837U, // SMAXV_VPZ_B 901U, // SMAXV_VPZ_D 2245U, // SMAXV_VPZ_H 1029U, // SMAXV_VPZ_S 1U, // SMAXVv16i8v 3U, // SMAXVv4i16v 3U, // SMAXVv4i32v 4U, // SMAXVv8i16v 4U, // SMAXVv8i8v 261U, // SMAX_ZI_B 261U, // SMAX_ZI_D 11U, // SMAX_ZI_H 261U, // SMAX_ZI_S 74560U, // SMAX_ZPmZ_B 598912U, // SMAX_ZPmZ_D 1131465U, // SMAX_ZPmZ_H 1647616U, // SMAX_ZPmZ_S 33095U, // SMAXv16i8 41287U, // SMAXv2i32 49480U, // SMAXv4i16 16710U, // SMAXv4i32 24902U, // SMAXv8i16 57672U, // SMAXv8i8 0U, // SMC 33095U, // SMINPv16i8 41287U, // SMINPv2i32 49480U, // SMINPv4i16 16710U, // SMINPv4i32 24902U, // SMINPv8i16 57672U, // SMINPv8i8 837U, // SMINV_VPZ_B 901U, // SMINV_VPZ_D 2245U, // SMINV_VPZ_H 1029U, // SMINV_VPZ_S 1U, // SMINVv16i8v 3U, // SMINVv4i16v 3U, // SMINVv4i32v 4U, // SMINVv8i16v 4U, // SMINVv8i8v 261U, // SMIN_ZI_B 261U, // SMIN_ZI_D 11U, // SMIN_ZI_H 261U, // SMIN_ZI_S 74560U, // SMIN_ZPmZ_B 598912U, // SMIN_ZPmZ_D 1131465U, // SMIN_ZPmZ_H 1647616U, // SMIN_ZPmZ_S 33095U, // SMINv16i8 41287U, // SMINv2i32 49480U, // SMINv4i16 16710U, // SMINv4i32 24902U, // SMINv8i16 57672U, // SMINv8i8 33159U, // SMLALv16i8_v8i16 9126279U, // SMLALv2i32_indexed 41351U, // SMLALv2i32_v2i64 9118088U, // SMLALv4i16_indexed 49544U, // SMLALv4i16_v4i32 9126278U, // SMLALv4i32_indexed 16774U, // SMLALv4i32_v2i64 9118086U, // SMLALv8i16_indexed 24966U, // SMLALv8i16_v4i32 57736U, // SMLALv8i8_v8i16 33159U, // SMLSLv16i8_v8i16 9126279U, // SMLSLv2i32_indexed 41351U, // SMLSLv2i32_v2i64 9118088U, // SMLSLv4i16_indexed 49544U, // SMLSLv4i16_v4i32 9126278U, // SMLSLv4i32_indexed 16774U, // SMLSLv4i32_v2i64 9118086U, // SMLSLv8i16_indexed 24966U, // SMLSLv8i16_v4i32 57736U, // SMLSLv8i8_v8i16 2770U, // SMOVvi16to32 2770U, // SMOVvi16to64 2770U, // SMOVvi32to64 2771U, // SMOVvi8to32 2771U, // SMOVvi8to64 2171141U, // SMSUBLrrr 74560U, // SMULH_ZPmZ_B 598912U, // SMULH_ZPmZ_D 1131465U, // SMULH_ZPmZ_H 1647616U, // SMULH_ZPmZ_S 261U, // SMULHrr 33095U, // SMULLv16i8_v8i16 10174791U, // SMULLv2i32_indexed 41287U, // SMULLv2i32_v2i64 10166600U, // SMULLv4i16_indexed 49480U, // SMULLv4i16_v4i32 10174790U, // SMULLv4i32_indexed 16710U, // SMULLv4i32_v2i64 10166598U, // SMULLv8i16_indexed 24902U, // SMULLv8i16_v4i32 57672U, // SMULLv8i8_v8i16 74565U, // SPLICE_ZPZ_B 598917U, // SPLICE_ZPZ_D 1131465U, // SPLICE_ZPZ_H 1647621U, // SPLICE_ZPZ_S 1U, // SQABSv16i8 1U, // SQABSv1i16 1U, // SQABSv1i32 1U, // SQABSv1i64 1U, // SQABSv1i8 2U, // SQABSv2i32 2U, // SQABSv2i64 3U, // SQABSv4i16 3U, // SQABSv4i32 4U, // SQABSv8i16 4U, // SQABSv8i8 645U, // SQADD_ZI_B 709U, // SQADD_ZI_D 9U, // SQADD_ZI_H 773U, // SQADD_ZI_S 837U, // SQADD_ZZZ_B 901U, // SQADD_ZZZ_D 137U, // SQADD_ZZZ_H 1029U, // SQADD_ZZZ_S 33095U, // SQADDv16i8 261U, // SQADDv1i16 261U, // SQADDv1i32 261U, // SQADDv1i64 261U, // SQADDv1i8 41287U, // SQADDv2i32 8517U, // SQADDv2i64 49480U, // SQADDv4i16 16710U, // SQADDv4i32 24902U, // SQADDv8i16 57672U, // SQADDv8i8 0U, // SQDECB_XPiI 0U, // SQDECB_XPiWdI 0U, // SQDECD_XPiI 0U, // SQDECD_XPiWdI 0U, // SQDECD_ZPiI 0U, // SQDECH_XPiI 0U, // SQDECH_XPiWdI 0U, // SQDECH_ZPiI 5381U, // SQDECP_XPWd_B 5381U, // SQDECP_XPWd_D 5381U, // SQDECP_XPWd_H 5381U, // SQDECP_XPWd_S 1U, // SQDECP_XP_B 1U, // SQDECP_XP_D 1U, // SQDECP_XP_H 1U, // SQDECP_XP_S 1U, // SQDECP_ZP_D 0U, // SQDECP_ZP_H 1U, // SQDECP_ZP_S 0U, // SQDECW_XPiI 0U, // SQDECW_XPiWdI 0U, // SQDECW_ZPiI 2309U, // SQDMLALi16 2309U, // SQDMLALi32 9118085U, // SQDMLALv1i32_indexed 9126277U, // SQDMLALv1i64_indexed 9126279U, // SQDMLALv2i32_indexed 41351U, // SQDMLALv2i32_v2i64 9118088U, // SQDMLALv4i16_indexed 49544U, // SQDMLALv4i16_v4i32 9126278U, // SQDMLALv4i32_indexed 16774U, // SQDMLALv4i32_v2i64 9118086U, // SQDMLALv8i16_indexed 24966U, // SQDMLALv8i16_v4i32 2309U, // SQDMLSLi16 2309U, // SQDMLSLi32 9118085U, // SQDMLSLv1i32_indexed 9126277U, // SQDMLSLv1i64_indexed 9126279U, // SQDMLSLv2i32_indexed 41351U, // SQDMLSLv2i32_v2i64 9118088U, // SQDMLSLv4i16_indexed 49544U, // SQDMLSLv4i16_v4i32 9126278U, // SQDMLSLv4i32_indexed 16774U, // SQDMLSLv4i32_v2i64 9118086U, // SQDMLSLv8i16_indexed 24966U, // SQDMLSLv8i16_v4i32 261U, // SQDMULHv1i16 10166597U, // SQDMULHv1i16_indexed 261U, // SQDMULHv1i32 10174789U, // SQDMULHv1i32_indexed 41287U, // SQDMULHv2i32 10174791U, // SQDMULHv2i32_indexed 49480U, // SQDMULHv4i16 10166600U, // SQDMULHv4i16_indexed 16710U, // SQDMULHv4i32 10174790U, // SQDMULHv4i32_indexed 24902U, // SQDMULHv8i16 10166598U, // SQDMULHv8i16_indexed 261U, // SQDMULLi16 261U, // SQDMULLi32 10166597U, // SQDMULLv1i32_indexed 10174789U, // SQDMULLv1i64_indexed 10174791U, // SQDMULLv2i32_indexed 41287U, // SQDMULLv2i32_v2i64 10166600U, // SQDMULLv4i16_indexed 49480U, // SQDMULLv4i16_v4i32 10174790U, // SQDMULLv4i32_indexed 16710U, // SQDMULLv4i32_v2i64 10166598U, // SQDMULLv8i16_indexed 24902U, // SQDMULLv8i16_v4i32 0U, // SQINCB_XPiI 0U, // SQINCB_XPiWdI 0U, // SQINCD_XPiI 0U, // SQINCD_XPiWdI 0U, // SQINCD_ZPiI 0U, // SQINCH_XPiI 0U, // SQINCH_XPiWdI 0U, // SQINCH_ZPiI 5381U, // SQINCP_XPWd_B 5381U, // SQINCP_XPWd_D 5381U, // SQINCP_XPWd_H 5381U, // SQINCP_XPWd_S 1U, // SQINCP_XP_B 1U, // SQINCP_XP_D 1U, // SQINCP_XP_H 1U, // SQINCP_XP_S 1U, // SQINCP_ZP_D 0U, // SQINCP_ZP_H 1U, // SQINCP_ZP_S 0U, // SQINCW_XPiI 0U, // SQINCW_XPiWdI 0U, // SQINCW_ZPiI 1U, // SQNEGv16i8 1U, // SQNEGv1i16 1U, // SQNEGv1i32 1U, // SQNEGv1i64 1U, // SQNEGv1i8 2U, // SQNEGv2i32 2U, // SQNEGv2i64 3U, // SQNEGv4i16 3U, // SQNEGv4i32 4U, // SQNEGv8i16 4U, // SQNEGv8i8 9118085U, // SQRDMLAHi16_indexed 9126277U, // SQRDMLAHi32_indexed 2309U, // SQRDMLAHv1i16 2309U, // SQRDMLAHv1i32 41351U, // SQRDMLAHv2i32 9126279U, // SQRDMLAHv2i32_indexed 49544U, // SQRDMLAHv4i16 9118088U, // SQRDMLAHv4i16_indexed 16774U, // SQRDMLAHv4i32 9126278U, // SQRDMLAHv4i32_indexed 24966U, // SQRDMLAHv8i16 9118086U, // SQRDMLAHv8i16_indexed 9118085U, // SQRDMLSHi16_indexed 9126277U, // SQRDMLSHi32_indexed 2309U, // SQRDMLSHv1i16 2309U, // SQRDMLSHv1i32 41351U, // SQRDMLSHv2i32 9126279U, // SQRDMLSHv2i32_indexed 49544U, // SQRDMLSHv4i16 9118088U, // SQRDMLSHv4i16_indexed 16774U, // SQRDMLSHv4i32 9126278U, // SQRDMLSHv4i32_indexed 24966U, // SQRDMLSHv8i16 9118086U, // SQRDMLSHv8i16_indexed 261U, // SQRDMULHv1i16 10166597U, // SQRDMULHv1i16_indexed 261U, // SQRDMULHv1i32 10174789U, // SQRDMULHv1i32_indexed 41287U, // SQRDMULHv2i32 10174791U, // SQRDMULHv2i32_indexed 49480U, // SQRDMULHv4i16 10166600U, // SQRDMULHv4i16_indexed 16710U, // SQRDMULHv4i32 10174790U, // SQRDMULHv4i32_indexed 24902U, // SQRDMULHv8i16 10166598U, // SQRDMULHv8i16_indexed 33095U, // SQRSHLv16i8 261U, // SQRSHLv1i16 261U, // SQRSHLv1i32 261U, // SQRSHLv1i64 261U, // SQRSHLv1i8 41287U, // SQRSHLv2i32 8517U, // SQRSHLv2i64 49480U, // SQRSHLv4i16 16710U, // SQRSHLv4i32 24902U, // SQRSHLv8i16 57672U, // SQRSHLv8i8 261U, // SQRSHRNb 261U, // SQRSHRNh 261U, // SQRSHRNs 2310U, // SQRSHRNv16i8_shift 261U, // SQRSHRNv2i32_shift 262U, // SQRSHRNv4i16_shift 2309U, // SQRSHRNv4i32_shift 2310U, // SQRSHRNv8i16_shift 262U, // SQRSHRNv8i8_shift 261U, // SQRSHRUNb 261U, // SQRSHRUNh 261U, // SQRSHRUNs 2310U, // SQRSHRUNv16i8_shift 261U, // SQRSHRUNv2i32_shift 262U, // SQRSHRUNv4i16_shift 2309U, // SQRSHRUNv4i32_shift 2310U, // SQRSHRUNv8i16_shift 262U, // SQRSHRUNv8i8_shift 261U, // SQSHLUb 261U, // SQSHLUd 261U, // SQSHLUh 261U, // SQSHLUs 263U, // SQSHLUv16i8_shift 263U, // SQSHLUv2i32_shift 261U, // SQSHLUv2i64_shift 264U, // SQSHLUv4i16_shift 262U, // SQSHLUv4i32_shift 262U, // SQSHLUv8i16_shift 264U, // SQSHLUv8i8_shift 261U, // SQSHLb 261U, // SQSHLd 261U, // SQSHLh 261U, // SQSHLs 33095U, // SQSHLv16i8 263U, // SQSHLv16i8_shift 261U, // SQSHLv1i16 261U, // SQSHLv1i32 261U, // SQSHLv1i64 261U, // SQSHLv1i8 41287U, // SQSHLv2i32 263U, // SQSHLv2i32_shift 8517U, // SQSHLv2i64 261U, // SQSHLv2i64_shift 49480U, // SQSHLv4i16 264U, // SQSHLv4i16_shift 16710U, // SQSHLv4i32 262U, // SQSHLv4i32_shift 24902U, // SQSHLv8i16 262U, // SQSHLv8i16_shift 57672U, // SQSHLv8i8 264U, // SQSHLv8i8_shift 261U, // SQSHRNb 261U, // SQSHRNh 261U, // SQSHRNs 2310U, // SQSHRNv16i8_shift 261U, // SQSHRNv2i32_shift 262U, // SQSHRNv4i16_shift 2309U, // SQSHRNv4i32_shift 2310U, // SQSHRNv8i16_shift 262U, // SQSHRNv8i8_shift 261U, // SQSHRUNb 261U, // SQSHRUNh 261U, // SQSHRUNs 2310U, // SQSHRUNv16i8_shift 261U, // SQSHRUNv2i32_shift 262U, // SQSHRUNv4i16_shift 2309U, // SQSHRUNv4i32_shift 2310U, // SQSHRUNv8i16_shift 262U, // SQSHRUNv8i8_shift 645U, // SQSUB_ZI_B 709U, // SQSUB_ZI_D 9U, // SQSUB_ZI_H 773U, // SQSUB_ZI_S 837U, // SQSUB_ZZZ_B 901U, // SQSUB_ZZZ_D 137U, // SQSUB_ZZZ_H 1029U, // SQSUB_ZZZ_S 33095U, // SQSUBv16i8 261U, // SQSUBv1i16 261U, // SQSUBv1i32 261U, // SQSUBv1i64 261U, // SQSUBv1i8 41287U, // SQSUBv2i32 8517U, // SQSUBv2i64 49480U, // SQSUBv4i16 16710U, // SQSUBv4i32 24902U, // SQSUBv8i16 57672U, // SQSUBv8i8 4U, // SQXTNv16i8 1U, // SQXTNv1i16 1U, // SQXTNv1i32 1U, // SQXTNv1i8 2U, // SQXTNv2i32 3U, // SQXTNv4i16 2U, // SQXTNv4i32 3U, // SQXTNv8i16 4U, // SQXTNv8i8 4U, // SQXTUNv16i8 1U, // SQXTUNv1i16 1U, // SQXTUNv1i32 1U, // SQXTUNv1i8 2U, // SQXTUNv2i32 3U, // SQXTUNv4i16 2U, // SQXTUNv4i32 3U, // SQXTUNv8i16 4U, // SQXTUNv8i8 33095U, // SRHADDv16i8 41287U, // SRHADDv2i32 49480U, // SRHADDv4i16 16710U, // SRHADDv4i32 24902U, // SRHADDv8i16 57672U, // SRHADDv8i8 2309U, // SRId 2311U, // SRIv16i8_shift 2311U, // SRIv2i32_shift 2309U, // SRIv2i64_shift 2312U, // SRIv4i16_shift 2310U, // SRIv4i32_shift 2310U, // SRIv8i16_shift 2312U, // SRIv8i8_shift 33095U, // SRSHLv16i8 261U, // SRSHLv1i64 41287U, // SRSHLv2i32 8517U, // SRSHLv2i64 49480U, // SRSHLv4i16 16710U, // SRSHLv4i32 24902U, // SRSHLv8i16 57672U, // SRSHLv8i8 261U, // SRSHRd 263U, // SRSHRv16i8_shift 263U, // SRSHRv2i32_shift 261U, // SRSHRv2i64_shift 264U, // SRSHRv4i16_shift 262U, // SRSHRv4i32_shift 262U, // SRSHRv8i16_shift 264U, // SRSHRv8i8_shift 2309U, // SRSRAd 2311U, // SRSRAv16i8_shift 2311U, // SRSRAv2i32_shift 2309U, // SRSRAv2i64_shift 2312U, // SRSRAv4i16_shift 2310U, // SRSRAv4i32_shift 2310U, // SRSRAv8i16_shift 2312U, // SRSRAv8i8_shift 263U, // SSHLLv16i8_shift 263U, // SSHLLv2i32_shift 264U, // SSHLLv4i16_shift 262U, // SSHLLv4i32_shift 262U, // SSHLLv8i16_shift 264U, // SSHLLv8i8_shift 33095U, // SSHLv16i8 261U, // SSHLv1i64 41287U, // SSHLv2i32 8517U, // SSHLv2i64 49480U, // SSHLv4i16 16710U, // SSHLv4i32 24902U, // SSHLv8i16 57672U, // SSHLv8i8 261U, // SSHRd 263U, // SSHRv16i8_shift 263U, // SSHRv2i32_shift 261U, // SSHRv2i64_shift 264U, // SSHRv4i16_shift 262U, // SSHRv4i32_shift 262U, // SSHRv8i16_shift 264U, // SSHRv8i8_shift 2309U, // SSRAd 2311U, // SSRAv16i8_shift 2311U, // SSRAv2i32_shift 2309U, // SSRAv2i64_shift 2312U, // SSRAv4i16_shift 2310U, // SSRAv4i32_shift 2310U, // SSRAv8i16_shift 2312U, // SSRAv8i8_shift 3205U, // SST1B_D 3153U, // SST1B_D_IMM 3269U, // SST1B_D_SXTW 3333U, // SST1B_D_UXTW 3153U, // SST1B_S_IMM 3397U, // SST1B_S_SXTW 3461U, // SST1B_S_UXTW 3205U, // SST1D 26U, // SST1D_IMM 3525U, // SST1D_SCALED 3269U, // SST1D_SXTW 3589U, // SST1D_SXTW_SCALED 3333U, // SST1D_UXTW 3653U, // SST1D_UXTW_SCALED 3205U, // SST1H_D 26U, // SST1H_D_IMM 3717U, // SST1H_D_SCALED 3269U, // SST1H_D_SXTW 3781U, // SST1H_D_SXTW_SCALED 3333U, // SST1H_D_UXTW 3845U, // SST1H_D_UXTW_SCALED 26U, // SST1H_S_IMM 3397U, // SST1H_S_SXTW 3909U, // SST1H_S_SXTW_SCALED 3461U, // SST1H_S_UXTW 3973U, // SST1H_S_UXTW_SCALED 3205U, // SST1W_D 27U, // SST1W_D_IMM 4037U, // SST1W_D_SCALED 3269U, // SST1W_D_SXTW 4101U, // SST1W_D_SXTW_SCALED 3333U, // SST1W_D_UXTW 4165U, // SST1W_D_UXTW_SCALED 27U, // SST1W_IMM 3397U, // SST1W_SXTW 4229U, // SST1W_SXTW_SCALED 3461U, // SST1W_UXTW 4293U, // SST1W_UXTW_SCALED 33095U, // SSUBLv16i8_v8i16 41287U, // SSUBLv2i32_v2i64 49480U, // SSUBLv4i16_v4i32 16710U, // SSUBLv4i32_v2i64 24902U, // SSUBLv8i16_v4i32 57672U, // SSUBLv8i8_v8i16 33094U, // SSUBWv16i8_v8i16 41285U, // SSUBWv2i32_v2i64 49478U, // SSUBWv4i16_v4i32 16709U, // SSUBWv4i32_v2i64 24902U, // SSUBWv8i16_v4i32 57670U, // SSUBWv8i8_v8i16 4357U, // ST1B 4357U, // ST1B_D 256261U, // ST1B_D_IMM 4357U, // ST1B_H 256261U, // ST1B_H_IMM 256261U, // ST1B_IMM 4357U, // ST1B_S 256261U, // ST1B_S_IMM 4421U, // ST1D 256261U, // ST1D_IMM 0U, // ST1Fourv16b 0U, // ST1Fourv16b_POST 0U, // ST1Fourv1d 0U, // ST1Fourv1d_POST 0U, // ST1Fourv2d 0U, // ST1Fourv2d_POST 0U, // ST1Fourv2s 0U, // ST1Fourv2s_POST 0U, // ST1Fourv4h 0U, // ST1Fourv4h_POST 0U, // ST1Fourv4s 0U, // ST1Fourv4s_POST 0U, // ST1Fourv8b 0U, // ST1Fourv8b_POST 0U, // ST1Fourv8h 0U, // ST1Fourv8h_POST 4485U, // ST1H 4485U, // ST1H_D 256261U, // ST1H_D_IMM 256261U, // ST1H_IMM 4485U, // ST1H_S 256261U, // ST1H_S_IMM 0U, // ST1Onev16b 0U, // ST1Onev16b_POST 0U, // ST1Onev1d 0U, // ST1Onev1d_POST 0U, // ST1Onev2d 0U, // ST1Onev2d_POST 0U, // ST1Onev2s 0U, // ST1Onev2s_POST 0U, // ST1Onev4h 0U, // ST1Onev4h_POST 0U, // ST1Onev4s 0U, // ST1Onev4s_POST 0U, // ST1Onev8b 0U, // ST1Onev8b_POST 0U, // ST1Onev8h 0U, // ST1Onev8h_POST 0U, // ST1Threev16b 0U, // ST1Threev16b_POST 0U, // ST1Threev1d 0U, // ST1Threev1d_POST 0U, // ST1Threev2d 0U, // ST1Threev2d_POST 0U, // ST1Threev2s 0U, // ST1Threev2s_POST 0U, // ST1Threev4h 0U, // ST1Threev4h_POST 0U, // ST1Threev4s 0U, // ST1Threev4s_POST 0U, // ST1Threev8b 0U, // ST1Threev8b_POST 0U, // ST1Threev8h 0U, // ST1Threev8h_POST 0U, // ST1Twov16b 0U, // ST1Twov16b_POST 0U, // ST1Twov1d 0U, // ST1Twov1d_POST 0U, // ST1Twov2d 0U, // ST1Twov2d_POST 0U, // ST1Twov2s 0U, // ST1Twov2s_POST 0U, // ST1Twov4h 0U, // ST1Twov4h_POST 0U, // ST1Twov4s 0U, // ST1Twov4s_POST 0U, // ST1Twov8b 0U, // ST1Twov8b_POST 0U, // ST1Twov8h 0U, // ST1Twov8h_POST 4741U, // ST1W 4741U, // ST1W_D 256261U, // ST1W_D_IMM 256261U, // ST1W_IMM 0U, // ST1i16 0U, // ST1i16_POST 0U, // ST1i32 0U, // ST1i32_POST 0U, // ST1i64 0U, // ST1i64_POST 0U, // ST1i8 0U, // ST1i8_POST 4357U, // ST2B 258565U, // ST2B_IMM 4421U, // ST2D 258565U, // ST2D_IMM 4485U, // ST2H 258565U, // ST2H_IMM 0U, // ST2Twov16b 0U, // ST2Twov16b_POST 0U, // ST2Twov2d 0U, // ST2Twov2d_POST 0U, // ST2Twov2s 0U, // ST2Twov2s_POST 0U, // ST2Twov4h 0U, // ST2Twov4h_POST 0U, // ST2Twov4s 0U, // ST2Twov4s_POST 0U, // ST2Twov8b 0U, // ST2Twov8b_POST 0U, // ST2Twov8h 0U, // ST2Twov8h_POST 4741U, // ST2W 258565U, // ST2W_IMM 0U, // ST2i16 0U, // ST2i16_POST 0U, // ST2i32 0U, // ST2i32_POST 0U, // ST2i64 0U, // ST2i64_POST 0U, // ST2i8 0U, // ST2i8_POST 4357U, // ST3B 4869U, // ST3B_IMM 4421U, // ST3D 4869U, // ST3D_IMM 4485U, // ST3H 4869U, // ST3H_IMM 0U, // ST3Threev16b 0U, // ST3Threev16b_POST 0U, // ST3Threev2d 0U, // ST3Threev2d_POST 0U, // ST3Threev2s 0U, // ST3Threev2s_POST 0U, // ST3Threev4h 0U, // ST3Threev4h_POST 0U, // ST3Threev4s 0U, // ST3Threev4s_POST 0U, // ST3Threev8b 0U, // ST3Threev8b_POST 0U, // ST3Threev8h 0U, // ST3Threev8h_POST 4741U, // ST3W 4869U, // ST3W_IMM 0U, // ST3i16 0U, // ST3i16_POST 0U, // ST3i32 0U, // ST3i32_POST 0U, // ST3i64 0U, // ST3i64_POST 0U, // ST3i8 0U, // ST3i8_POST 4357U, // ST4B 258757U, // ST4B_IMM 4421U, // ST4D 258757U, // ST4D_IMM 0U, // ST4Fourv16b 0U, // ST4Fourv16b_POST 0U, // ST4Fourv2d 0U, // ST4Fourv2d_POST 0U, // ST4Fourv2s 0U, // ST4Fourv2s_POST 0U, // ST4Fourv4h 0U, // ST4Fourv4h_POST 0U, // ST4Fourv4s 0U, // ST4Fourv4s_POST 0U, // ST4Fourv8b 0U, // ST4Fourv8b_POST 0U, // ST4Fourv8h 0U, // ST4Fourv8h_POST 4485U, // ST4H 258757U, // ST4H_IMM 4741U, // ST4W 258757U, // ST4W_IMM 0U, // ST4i16 0U, // ST4i16_POST 0U, // ST4i32 0U, // ST4i32_POST 0U, // ST4i64 0U, // ST4i64_POST 0U, // ST4i8 0U, // ST4i8_POST 27U, // STLLRB 27U, // STLLRH 27U, // STLLRW 27U, // STLLRX 27U, // STLRB 27U, // STLRH 27U, // STLRW 27U, // STLRX 114949U, // STLURBi 114949U, // STLURHi 114949U, // STLURWi 114949U, // STLURXi 286981U, // STLXPW 286981U, // STLXPX 114955U, // STLXRB 114955U, // STLXRH 114955U, // STLXRW 114955U, // STLXRX 11084043U, // STNPDi 11608331U, // STNPQi 12132619U, // STNPSi 12132619U, // STNPWi 11084043U, // STNPXi 256261U, // STNT1B_ZRI 4357U, // STNT1B_ZRR 256261U, // STNT1D_ZRI 4421U, // STNT1D_ZRR 256261U, // STNT1H_ZRI 4485U, // STNT1H_ZRR 256261U, // STNT1W_ZRI 4741U, // STNT1W_ZRR 11084043U, // STPDi 12847371U, // STPDpost 180431115U, // STPDpre 11608331U, // STPQi 13371659U, // STPQpost 180955403U, // STPQpre 12132619U, // STPSi 13895947U, // STPSpost 181479691U, // STPSpre 12132619U, // STPWi 13895947U, // STPWpost 181479691U, // STPWpre 11084043U, // STPXi 12847371U, // STPXpost 180431115U, // STPXpre 28U, // STRBBpost 272645U, // STRBBpre 14229765U, // STRBBroW 14754053U, // STRBBroX 4997U, // STRBBui 28U, // STRBpost 272645U, // STRBpre 14229765U, // STRBroW 14754053U, // STRBroX 4997U, // STRBui 28U, // STRDpost 272645U, // STRDpre 15278341U, // STRDroW 15802629U, // STRDroX 5061U, // STRDui 28U, // STRHHpost 272645U, // STRHHpre 16326917U, // STRHHroW 16851205U, // STRHHroX 5125U, // STRHHui 28U, // STRHpost 272645U, // STRHpre 16326917U, // STRHroW 16851205U, // STRHroX 5125U, // STRHui 28U, // STRQpost 272645U, // STRQpre 17375493U, // STRQroW 17899781U, // STRQroX 5189U, // STRQui 28U, // STRSpost 272645U, // STRSpre 18424069U, // STRSroW 18948357U, // STRSroX 5253U, // STRSui 28U, // STRWpost 272645U, // STRWpre 18424069U, // STRWroW 18948357U, // STRWroX 5253U, // STRWui 28U, // STRXpost 272645U, // STRXpre 15278341U, // STRXroW 15802629U, // STRXroX 5061U, // STRXui 254213U, // STR_PXI 254213U, // STR_ZXI 114949U, // STTRBi 114949U, // STTRHi 114949U, // STTRWi 114949U, // STTRXi 114949U, // STURBBi 114949U, // STURBi 114949U, // STURDi 114949U, // STURHHi 114949U, // STURHi 114949U, // STURQi 114949U, // STURSi 114949U, // STURWi 114949U, // STURXi 286981U, // STXPW 286981U, // STXPX 114955U, // STXRB 114955U, // STXRH 114955U, // STXRW 114955U, // STXRX 8517U, // SUBHNv2i64_v2i32 8581U, // SUBHNv2i64_v4i32 16710U, // SUBHNv4i32_v4i16 16774U, // SUBHNv4i32_v8i16 24966U, // SUBHNv8i16_v16i8 24902U, // SUBHNv8i16_v8i8 645U, // SUBR_ZI_B 709U, // SUBR_ZI_D 9U, // SUBR_ZI_H 773U, // SUBR_ZI_S 74560U, // SUBR_ZPmZ_B 598912U, // SUBR_ZPmZ_D 1131465U, // SUBR_ZPmZ_H 1647616U, // SUBR_ZPmZ_S 453U, // SUBSWri 0U, // SUBSWrr 517U, // SUBSWrs 581U, // SUBSWrx 453U, // SUBSXri 0U, // SUBSXrr 517U, // SUBSXrs 581U, // SUBSXrx 65797U, // SUBSXrx64 453U, // SUBWri 0U, // SUBWrr 517U, // SUBWrs 581U, // SUBWrx 453U, // SUBXri 0U, // SUBXrr 517U, // SUBXrs 581U, // SUBXrx 65797U, // SUBXrx64 645U, // SUB_ZI_B 709U, // SUB_ZI_D 9U, // SUB_ZI_H 773U, // SUB_ZI_S 74560U, // SUB_ZPmZ_B 598912U, // SUB_ZPmZ_D 1131465U, // SUB_ZPmZ_H 1647616U, // SUB_ZPmZ_S 837U, // SUB_ZZZ_B 901U, // SUB_ZZZ_D 137U, // SUB_ZZZ_H 1029U, // SUB_ZZZ_S 33095U, // SUBv16i8 261U, // SUBv1i64 41287U, // SUBv2i32 8517U, // SUBv2i64 49480U, // SUBv4i16 16710U, // SUBv4i32 24902U, // SUBv8i16 57672U, // SUBv8i8 1U, // SUNPKHI_ZZ_D 0U, // SUNPKHI_ZZ_H 1U, // SUNPKHI_ZZ_S 1U, // SUNPKLO_ZZ_D 0U, // SUNPKLO_ZZ_H 1U, // SUNPKLO_ZZ_S 1U, // SUQADDv16i8 1U, // SUQADDv1i16 1U, // SUQADDv1i32 1U, // SUQADDv1i64 1U, // SUQADDv1i8 2U, // SUQADDv2i32 2U, // SUQADDv2i64 3U, // SUQADDv4i16 3U, // SUQADDv4i32 4U, // SUQADDv8i16 4U, // SUQADDv8i8 0U, // SVC 0U, // SWPAB 0U, // SWPAH 0U, // SWPALB 0U, // SWPALH 0U, // SWPALW 0U, // SWPALX 0U, // SWPAW 0U, // SWPAX 0U, // SWPB 0U, // SWPH 0U, // SWPLB 0U, // SWPLH 0U, // SWPLW 0U, // SWPLX 0U, // SWPW 0U, // SWPX 64U, // SXTB_ZPmZ_D 128U, // SXTB_ZPmZ_H 192U, // SXTB_ZPmZ_S 64U, // SXTH_ZPmZ_D 192U, // SXTH_ZPmZ_S 64U, // SXTW_ZPmZ_D 5445U, // SYSLxt 0U, // SYSxt 0U, // TBL_ZZZ_B 0U, // TBL_ZZZ_D 0U, // TBL_ZZZ_H 0U, // TBL_ZZZ_S 1U, // TBLv16i8Four 1U, // TBLv16i8One 1U, // TBLv16i8Three 1U, // TBLv16i8Two 4U, // TBLv8i8Four 4U, // TBLv8i8One 4U, // TBLv8i8Three 4U, // TBLv8i8Two 5509U, // TBNZW 5509U, // TBNZX 1U, // TBXv16i8Four 1U, // TBXv16i8One 1U, // TBXv16i8Three 1U, // TBXv16i8Two 4U, // TBXv8i8Four 4U, // TBXv8i8One 4U, // TBXv8i8Three 4U, // TBXv8i8Two 5509U, // TBZW 5509U, // TBZX 0U, // TCRETURNdi 0U, // TCRETURNri 0U, // TLSDESCCALL 0U, // TLSDESC_CALLSEQ 837U, // TRN1_PPP_B 901U, // TRN1_PPP_D 137U, // TRN1_PPP_H 1029U, // TRN1_PPP_S 837U, // TRN1_ZZZ_B 901U, // TRN1_ZZZ_D 137U, // TRN1_ZZZ_H 1029U, // TRN1_ZZZ_S 33095U, // TRN1v16i8 41287U, // TRN1v2i32 8517U, // TRN1v2i64 49480U, // TRN1v4i16 16710U, // TRN1v4i32 24902U, // TRN1v8i16 57672U, // TRN1v8i8 837U, // TRN2_PPP_B 901U, // TRN2_PPP_D 137U, // TRN2_PPP_H 1029U, // TRN2_PPP_S 837U, // TRN2_ZZZ_B 901U, // TRN2_ZZZ_D 137U, // TRN2_ZZZ_H 1029U, // TRN2_ZZZ_S 33095U, // TRN2v16i8 41287U, // TRN2v2i32 8517U, // TRN2v2i64 49480U, // TRN2v4i16 16710U, // TRN2v4i32 24902U, // TRN2v8i16 57672U, // TRN2v8i8 0U, // TSB 33159U, // UABALv16i8_v8i16 41351U, // UABALv2i32_v2i64 49544U, // UABALv4i16_v4i32 16774U, // UABALv4i32_v2i64 24966U, // UABALv8i16_v4i32 57736U, // UABALv8i8_v8i16 33159U, // UABAv16i8 41351U, // UABAv2i32 49544U, // UABAv4i16 16774U, // UABAv4i32 24966U, // UABAv8i16 57736U, // UABAv8i8 33095U, // UABDLv16i8_v8i16 41287U, // UABDLv2i32_v2i64 49480U, // UABDLv4i16_v4i32 16710U, // UABDLv4i32_v2i64 24902U, // UABDLv8i16_v4i32 57672U, // UABDLv8i8_v8i16 74560U, // UABD_ZPmZ_B 598912U, // UABD_ZPmZ_D 1131465U, // UABD_ZPmZ_H 1647616U, // UABD_ZPmZ_S 33095U, // UABDv16i8 41287U, // UABDv2i32 49480U, // UABDv4i16 16710U, // UABDv4i32 24902U, // UABDv8i16 57672U, // UABDv8i8 1U, // UADALPv16i8_v8i16 2U, // UADALPv2i32_v1i64 3U, // UADALPv4i16_v2i32 3U, // UADALPv4i32_v2i64 4U, // UADALPv8i16_v4i32 4U, // UADALPv8i8_v4i16 1U, // UADDLPv16i8_v8i16 2U, // UADDLPv2i32_v1i64 3U, // UADDLPv4i16_v2i32 3U, // UADDLPv4i32_v2i64 4U, // UADDLPv8i16_v4i32 4U, // UADDLPv8i8_v4i16 1U, // UADDLVv16i8v 3U, // UADDLVv4i16v 3U, // UADDLVv4i32v 4U, // UADDLVv8i16v 4U, // UADDLVv8i8v 33095U, // UADDLv16i8_v8i16 41287U, // UADDLv2i32_v2i64 49480U, // UADDLv4i16_v4i32 16710U, // UADDLv4i32_v2i64 24902U, // UADDLv8i16_v4i32 57672U, // UADDLv8i8_v8i16 837U, // UADDV_VPZ_B 901U, // UADDV_VPZ_D 2245U, // UADDV_VPZ_H 1029U, // UADDV_VPZ_S 33094U, // UADDWv16i8_v8i16 41285U, // UADDWv2i32_v2i64 49478U, // UADDWv4i16_v4i32 16709U, // UADDWv4i32_v2i64 24902U, // UADDWv8i16_v4i32 57670U, // UADDWv8i8_v8i16 2171141U, // UBFMWri 2171141U, // UBFMXri 261U, // UCVTFSWDri 261U, // UCVTFSWHri 261U, // UCVTFSWSri 261U, // UCVTFSXDri 261U, // UCVTFSXHri 261U, // UCVTFSXSri 1U, // UCVTFUWDri 1U, // UCVTFUWHri 1U, // UCVTFUWSri 1U, // UCVTFUXDri 1U, // UCVTFUXHri 1U, // UCVTFUXSri 64U, // UCVTF_ZPmZ_DtoD 153U, // UCVTF_ZPmZ_DtoH 64U, // UCVTF_ZPmZ_DtoS 128U, // UCVTF_ZPmZ_HtoH 192U, // UCVTF_ZPmZ_StoD 152U, // UCVTF_ZPmZ_StoH 192U, // UCVTF_ZPmZ_StoS 261U, // UCVTFd 261U, // UCVTFh 261U, // UCVTFs 1U, // UCVTFv1i16 1U, // UCVTFv1i32 1U, // UCVTFv1i64 2U, // UCVTFv2f32 2U, // UCVTFv2f64 263U, // UCVTFv2i32_shift 261U, // UCVTFv2i64_shift 3U, // UCVTFv4f16 3U, // UCVTFv4f32 264U, // UCVTFv4i16_shift 262U, // UCVTFv4i32_shift 4U, // UCVTFv8f16 262U, // UCVTFv8i16_shift 598912U, // UDIVR_ZPmZ_D 1647616U, // UDIVR_ZPmZ_S 261U, // UDIVWr 261U, // UDIVXr 598912U, // UDIV_ZPmZ_D 1647616U, // UDIV_ZPmZ_S 41U, // UDOT_ZZZI_D 41U, // UDOT_ZZZI_S 1U, // UDOT_ZZZ_D 1U, // UDOT_ZZZ_S 278919U, // UDOTlanev16i8 278920U, // UDOTlanev8i8 33159U, // UDOTv16i8 57736U, // UDOTv8i8 33095U, // UHADDv16i8 41287U, // UHADDv2i32 49480U, // UHADDv4i16 16710U, // UHADDv4i32 24902U, // UHADDv8i16 57672U, // UHADDv8i8 33095U, // UHSUBv16i8 41287U, // UHSUBv2i32 49480U, // UHSUBv4i16 16710U, // UHSUBv4i32 24902U, // UHSUBv8i16 57672U, // UHSUBv8i8 2171141U, // UMADDLrrr 33095U, // UMAXPv16i8 41287U, // UMAXPv2i32 49480U, // UMAXPv4i16 16710U, // UMAXPv4i32 24902U, // UMAXPv8i16 57672U, // UMAXPv8i8 837U, // UMAXV_VPZ_B 901U, // UMAXV_VPZ_D 2245U, // UMAXV_VPZ_H 1029U, // UMAXV_VPZ_S 1U, // UMAXVv16i8v 3U, // UMAXVv4i16v 3U, // UMAXVv4i32v 4U, // UMAXVv8i16v 4U, // UMAXVv8i8v 5573U, // UMAX_ZI_B 5573U, // UMAX_ZI_D 45U, // UMAX_ZI_H 5573U, // UMAX_ZI_S 74560U, // UMAX_ZPmZ_B 598912U, // UMAX_ZPmZ_D 1131465U, // UMAX_ZPmZ_H 1647616U, // UMAX_ZPmZ_S 33095U, // UMAXv16i8 41287U, // UMAXv2i32 49480U, // UMAXv4i16 16710U, // UMAXv4i32 24902U, // UMAXv8i16 57672U, // UMAXv8i8 33095U, // UMINPv16i8 41287U, // UMINPv2i32 49480U, // UMINPv4i16 16710U, // UMINPv4i32 24902U, // UMINPv8i16 57672U, // UMINPv8i8 837U, // UMINV_VPZ_B 901U, // UMINV_VPZ_D 2245U, // UMINV_VPZ_H 1029U, // UMINV_VPZ_S 1U, // UMINVv16i8v 3U, // UMINVv4i16v 3U, // UMINVv4i32v 4U, // UMINVv8i16v 4U, // UMINVv8i8v 5573U, // UMIN_ZI_B 5573U, // UMIN_ZI_D 45U, // UMIN_ZI_H 5573U, // UMIN_ZI_S 74560U, // UMIN_ZPmZ_B 598912U, // UMIN_ZPmZ_D 1131465U, // UMIN_ZPmZ_H 1647616U, // UMIN_ZPmZ_S 33095U, // UMINv16i8 41287U, // UMINv2i32 49480U, // UMINv4i16 16710U, // UMINv4i32 24902U, // UMINv8i16 57672U, // UMINv8i8 33159U, // UMLALv16i8_v8i16 9126279U, // UMLALv2i32_indexed 41351U, // UMLALv2i32_v2i64 9118088U, // UMLALv4i16_indexed 49544U, // UMLALv4i16_v4i32 9126278U, // UMLALv4i32_indexed 16774U, // UMLALv4i32_v2i64 9118086U, // UMLALv8i16_indexed 24966U, // UMLALv8i16_v4i32 57736U, // UMLALv8i8_v8i16 33159U, // UMLSLv16i8_v8i16 9126279U, // UMLSLv2i32_indexed 41351U, // UMLSLv2i32_v2i64 9118088U, // UMLSLv4i16_indexed 49544U, // UMLSLv4i16_v4i32 9126278U, // UMLSLv4i32_indexed 16774U, // UMLSLv4i32_v2i64 9118086U, // UMLSLv8i16_indexed 24966U, // UMLSLv8i16_v4i32 57736U, // UMLSLv8i8_v8i16 2770U, // UMOVvi16 2770U, // UMOVvi32 2771U, // UMOVvi64 2771U, // UMOVvi8 2171141U, // UMSUBLrrr 74560U, // UMULH_ZPmZ_B 598912U, // UMULH_ZPmZ_D 1131465U, // UMULH_ZPmZ_H 1647616U, // UMULH_ZPmZ_S 261U, // UMULHrr 33095U, // UMULLv16i8_v8i16 10174791U, // UMULLv2i32_indexed 41287U, // UMULLv2i32_v2i64 10166600U, // UMULLv4i16_indexed 49480U, // UMULLv4i16_v4i32 10174790U, // UMULLv4i32_indexed 16710U, // UMULLv4i32_v2i64 10166598U, // UMULLv8i16_indexed 24902U, // UMULLv8i16_v4i32 57672U, // UMULLv8i8_v8i16 645U, // UQADD_ZI_B 709U, // UQADD_ZI_D 9U, // UQADD_ZI_H 773U, // UQADD_ZI_S 837U, // UQADD_ZZZ_B 901U, // UQADD_ZZZ_D 137U, // UQADD_ZZZ_H 1029U, // UQADD_ZZZ_S 33095U, // UQADDv16i8 261U, // UQADDv1i16 261U, // UQADDv1i32 261U, // UQADDv1i64 261U, // UQADDv1i8 41287U, // UQADDv2i32 8517U, // UQADDv2i64 49480U, // UQADDv4i16 16710U, // UQADDv4i32 24902U, // UQADDv8i16 57672U, // UQADDv8i8 0U, // UQDECB_WPiI 0U, // UQDECB_XPiI 0U, // UQDECD_WPiI 0U, // UQDECD_XPiI 0U, // UQDECD_ZPiI 0U, // UQDECH_WPiI 0U, // UQDECH_XPiI 0U, // UQDECH_ZPiI 1U, // UQDECP_WP_B 1U, // UQDECP_WP_D 1U, // UQDECP_WP_H 1U, // UQDECP_WP_S 1U, // UQDECP_XP_B 1U, // UQDECP_XP_D 1U, // UQDECP_XP_H 1U, // UQDECP_XP_S 1U, // UQDECP_ZP_D 0U, // UQDECP_ZP_H 1U, // UQDECP_ZP_S 0U, // UQDECW_WPiI 0U, // UQDECW_XPiI 0U, // UQDECW_ZPiI 0U, // UQINCB_WPiI 0U, // UQINCB_XPiI 0U, // UQINCD_WPiI 0U, // UQINCD_XPiI 0U, // UQINCD_ZPiI 0U, // UQINCH_WPiI 0U, // UQINCH_XPiI 0U, // UQINCH_ZPiI 1U, // UQINCP_WP_B 1U, // UQINCP_WP_D 1U, // UQINCP_WP_H 1U, // UQINCP_WP_S 1U, // UQINCP_XP_B 1U, // UQINCP_XP_D 1U, // UQINCP_XP_H 1U, // UQINCP_XP_S 1U, // UQINCP_ZP_D 0U, // UQINCP_ZP_H 1U, // UQINCP_ZP_S 0U, // UQINCW_WPiI 0U, // UQINCW_XPiI 0U, // UQINCW_ZPiI 33095U, // UQRSHLv16i8 261U, // UQRSHLv1i16 261U, // UQRSHLv1i32 261U, // UQRSHLv1i64 261U, // UQRSHLv1i8 41287U, // UQRSHLv2i32 8517U, // UQRSHLv2i64 49480U, // UQRSHLv4i16 16710U, // UQRSHLv4i32 24902U, // UQRSHLv8i16 57672U, // UQRSHLv8i8 261U, // UQRSHRNb 261U, // UQRSHRNh 261U, // UQRSHRNs 2310U, // UQRSHRNv16i8_shift 261U, // UQRSHRNv2i32_shift 262U, // UQRSHRNv4i16_shift 2309U, // UQRSHRNv4i32_shift 2310U, // UQRSHRNv8i16_shift 262U, // UQRSHRNv8i8_shift 261U, // UQSHLb 261U, // UQSHLd 261U, // UQSHLh 261U, // UQSHLs 33095U, // UQSHLv16i8 263U, // UQSHLv16i8_shift 261U, // UQSHLv1i16 261U, // UQSHLv1i32 261U, // UQSHLv1i64 261U, // UQSHLv1i8 41287U, // UQSHLv2i32 263U, // UQSHLv2i32_shift 8517U, // UQSHLv2i64 261U, // UQSHLv2i64_shift 49480U, // UQSHLv4i16 264U, // UQSHLv4i16_shift 16710U, // UQSHLv4i32 262U, // UQSHLv4i32_shift 24902U, // UQSHLv8i16 262U, // UQSHLv8i16_shift 57672U, // UQSHLv8i8 264U, // UQSHLv8i8_shift 261U, // UQSHRNb 261U, // UQSHRNh 261U, // UQSHRNs 2310U, // UQSHRNv16i8_shift 261U, // UQSHRNv2i32_shift 262U, // UQSHRNv4i16_shift 2309U, // UQSHRNv4i32_shift 2310U, // UQSHRNv8i16_shift 262U, // UQSHRNv8i8_shift 645U, // UQSUB_ZI_B 709U, // UQSUB_ZI_D 9U, // UQSUB_ZI_H 773U, // UQSUB_ZI_S 837U, // UQSUB_ZZZ_B 901U, // UQSUB_ZZZ_D 137U, // UQSUB_ZZZ_H 1029U, // UQSUB_ZZZ_S 33095U, // UQSUBv16i8 261U, // UQSUBv1i16 261U, // UQSUBv1i32 261U, // UQSUBv1i64 261U, // UQSUBv1i8 41287U, // UQSUBv2i32 8517U, // UQSUBv2i64 49480U, // UQSUBv4i16 16710U, // UQSUBv4i32 24902U, // UQSUBv8i16 57672U, // UQSUBv8i8 4U, // UQXTNv16i8 1U, // UQXTNv1i16 1U, // UQXTNv1i32 1U, // UQXTNv1i8 2U, // UQXTNv2i32 3U, // UQXTNv4i16 2U, // UQXTNv4i32 3U, // UQXTNv8i16 4U, // UQXTNv8i8 2U, // URECPEv2i32 3U, // URECPEv4i32 33095U, // URHADDv16i8 41287U, // URHADDv2i32 49480U, // URHADDv4i16 16710U, // URHADDv4i32 24902U, // URHADDv8i16 57672U, // URHADDv8i8 33095U, // URSHLv16i8 261U, // URSHLv1i64 41287U, // URSHLv2i32 8517U, // URSHLv2i64 49480U, // URSHLv4i16 16710U, // URSHLv4i32 24902U, // URSHLv8i16 57672U, // URSHLv8i8 261U, // URSHRd 263U, // URSHRv16i8_shift 263U, // URSHRv2i32_shift 261U, // URSHRv2i64_shift 264U, // URSHRv4i16_shift 262U, // URSHRv4i32_shift 262U, // URSHRv8i16_shift 264U, // URSHRv8i8_shift 2U, // URSQRTEv2i32 3U, // URSQRTEv4i32 2309U, // URSRAd 2311U, // URSRAv16i8_shift 2311U, // URSRAv2i32_shift 2309U, // URSRAv2i64_shift 2312U, // URSRAv4i16_shift 2310U, // URSRAv4i32_shift 2310U, // URSRAv8i16_shift 2312U, // URSRAv8i8_shift 263U, // USHLLv16i8_shift 263U, // USHLLv2i32_shift 264U, // USHLLv4i16_shift 262U, // USHLLv4i32_shift 262U, // USHLLv8i16_shift 264U, // USHLLv8i8_shift 33095U, // USHLv16i8 261U, // USHLv1i64 41287U, // USHLv2i32 8517U, // USHLv2i64 49480U, // USHLv4i16 16710U, // USHLv4i32 24902U, // USHLv8i16 57672U, // USHLv8i8 261U, // USHRd 263U, // USHRv16i8_shift 263U, // USHRv2i32_shift 261U, // USHRv2i64_shift 264U, // USHRv4i16_shift 262U, // USHRv4i32_shift 262U, // USHRv8i16_shift 264U, // USHRv8i8_shift 1U, // USQADDv16i8 1U, // USQADDv1i16 1U, // USQADDv1i32 1U, // USQADDv1i64 1U, // USQADDv1i8 2U, // USQADDv2i32 2U, // USQADDv2i64 3U, // USQADDv4i16 3U, // USQADDv4i32 4U, // USQADDv8i16 4U, // USQADDv8i8 2309U, // USRAd 2311U, // USRAv16i8_shift 2311U, // USRAv2i32_shift 2309U, // USRAv2i64_shift 2312U, // USRAv4i16_shift 2310U, // USRAv4i32_shift 2310U, // USRAv8i16_shift 2312U, // USRAv8i8_shift 33095U, // USUBLv16i8_v8i16 41287U, // USUBLv2i32_v2i64 49480U, // USUBLv4i16_v4i32 16710U, // USUBLv4i32_v2i64 24902U, // USUBLv8i16_v4i32 57672U, // USUBLv8i8_v8i16 33094U, // USUBWv16i8_v8i16 41285U, // USUBWv2i32_v2i64 49478U, // USUBWv4i16_v4i32 16709U, // USUBWv4i32_v2i64 24902U, // USUBWv8i16_v4i32 57670U, // USUBWv8i8_v8i16 1U, // UUNPKHI_ZZ_D 0U, // UUNPKHI_ZZ_H 1U, // UUNPKHI_ZZ_S 1U, // UUNPKLO_ZZ_D 0U, // UUNPKLO_ZZ_H 1U, // UUNPKLO_ZZ_S 64U, // UXTB_ZPmZ_D 128U, // UXTB_ZPmZ_H 192U, // UXTB_ZPmZ_S 64U, // UXTH_ZPmZ_D 192U, // UXTH_ZPmZ_S 64U, // UXTW_ZPmZ_D 837U, // UZP1_PPP_B 901U, // UZP1_PPP_D 137U, // UZP1_PPP_H 1029U, // UZP1_PPP_S 837U, // UZP1_ZZZ_B 901U, // UZP1_ZZZ_D 137U, // UZP1_ZZZ_H 1029U, // UZP1_ZZZ_S 33095U, // UZP1v16i8 41287U, // UZP1v2i32 8517U, // UZP1v2i64 49480U, // UZP1v4i16 16710U, // UZP1v4i32 24902U, // UZP1v8i16 57672U, // UZP1v8i8 837U, // UZP2_PPP_B 901U, // UZP2_PPP_D 137U, // UZP2_PPP_H 1029U, // UZP2_PPP_S 837U, // UZP2_ZZZ_B 901U, // UZP2_ZZZ_D 137U, // UZP2_ZZZ_H 1029U, // UZP2_ZZZ_S 33095U, // UZP2v16i8 41287U, // UZP2v2i32 8517U, // UZP2v2i64 49480U, // UZP2v4i16 16710U, // UZP2v4i32 24902U, // UZP2v8i16 57672U, // UZP2v8i8 261U, // WHILELE_PWW_B 261U, // WHILELE_PWW_D 11U, // WHILELE_PWW_H 261U, // WHILELE_PWW_S 261U, // WHILELE_PXX_B 261U, // WHILELE_PXX_D 11U, // WHILELE_PXX_H 261U, // WHILELE_PXX_S 261U, // WHILELO_PWW_B 261U, // WHILELO_PWW_D 11U, // WHILELO_PWW_H 261U, // WHILELO_PWW_S 261U, // WHILELO_PXX_B 261U, // WHILELO_PXX_D 11U, // WHILELO_PXX_H 261U, // WHILELO_PXX_S 261U, // WHILELS_PWW_B 261U, // WHILELS_PWW_D 11U, // WHILELS_PWW_H 261U, // WHILELS_PWW_S 261U, // WHILELS_PXX_B 261U, // WHILELS_PXX_D 11U, // WHILELS_PXX_H 261U, // WHILELS_PXX_S 261U, // WHILELT_PWW_B 261U, // WHILELT_PWW_D 11U, // WHILELT_PWW_H 261U, // WHILELT_PWW_S 261U, // WHILELT_PXX_B 261U, // WHILELT_PXX_D 11U, // WHILELT_PXX_H 261U, // WHILELT_PXX_S 0U, // WRFFR 2253125U, // XAR 0U, // XPACD 0U, // XPACI 0U, // XPACLRI 4U, // XTNv16i8 2U, // XTNv2i32 3U, // XTNv4i16 2U, // XTNv4i32 3U, // XTNv8i16 4U, // XTNv8i8 837U, // ZIP1_PPP_B 901U, // ZIP1_PPP_D 137U, // ZIP1_PPP_H 1029U, // ZIP1_PPP_S 837U, // ZIP1_ZZZ_B 901U, // ZIP1_ZZZ_D 137U, // ZIP1_ZZZ_H 1029U, // ZIP1_ZZZ_S 33095U, // ZIP1v16i8 41287U, // ZIP1v2i32 8517U, // ZIP1v2i64 49480U, // ZIP1v4i16 16710U, // ZIP1v4i32 24902U, // ZIP1v8i16 57672U, // ZIP1v8i8 837U, // ZIP2_PPP_B 901U, // ZIP2_PPP_D 137U, // ZIP2_PPP_H 1029U, // ZIP2_PPP_S 837U, // ZIP2_ZZZ_B 901U, // ZIP2_ZZZ_D 137U, // ZIP2_ZZZ_H 1029U, // ZIP2_ZZZ_S 33095U, // ZIP2v16i8 41287U, // ZIP2v2i32 8517U, // ZIP2v2i64 49480U, // ZIP2v4i16 16710U, // ZIP2v4i32 24902U, // ZIP2v8i16 57672U, // ZIP2v8i8 837U, // anonymous_1349 }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint64_t Bits = 0; Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 8191)-1); #endif // Fragment 0 encoded into 6 bits for 54 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 13) & 63)); switch ((Bits >> 13) & 63) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // ABS_ZPmZ_B, ADD_ZI_B, ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, AND_PPzPP, AN... printSVERegOp(MI, 0, O, 'b'); break; case 2: // ABS_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_... printSVERegOp(MI, 0, O, 'd'); break; case 3: // ABS_ZPmZ_H, ADD_ZI_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ... printSVERegOp(MI, 0, O, 'h'); SStream_concat0(O, ", "); break; case 4: // ABS_ZPmZ_S, ADD_ZI_S, ADD_ZPmZ_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_... printSVERegOp(MI, 0, O, 's'); break; case 5: // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... printVRegOperand(MI, 0, O); break; case 6: // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPv2i64p, ADDSWri... printOperand(MI, 0, O); break; case 7: // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... printVRegOperand(MI, 1, O); break; case 8: // B, BL printAlignedLabel(MI, 0, O); return; break; case 9: // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC printImmHex(MI, 0, O); return; break; case 10: // Bcc printCondCode(MI, 0, O); SStream_concat0(O, "\t"); printAlignedLabel(MI, 1, O); return; break; case 11: // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... printOperand(MI, 1, O); break; case 12: // CASPALW, CASPAW, CASPLW, CASPW printGPRSeqPairsClassOperand(MI, 1, O, 32); SStream_concat0(O, ", "); printGPRSeqPairsClassOperand(MI, 2, O, 32); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 13: // CASPALX, CASPAX, CASPLX, CASPX printGPRSeqPairsClassOperand(MI, 1, O, 64); SStream_concat0(O, ", "); printGPRSeqPairsClassOperand(MI, 2, O, 64); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 14: // DMB, DSB, ISB, TSB printBarrierOption(MI, 0, O); return; break; case 15: // DUP_ZZI_Q printSVERegOp(MI, 0, O, 'q'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 'q'); printVectorIndex(MI, 2, O); return; break; case 16: // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... printTypedVectorList(MI, 0, O, 0,'d'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; case 17: // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... printTypedVectorList(MI, 0, O, 0,'s'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; case 18: // HINT printImm(MI, 0, O); return; break; case 19: // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RQ_B, LD1RQ_B_IMM, LD2B, LD2B_IMM, ... printTypedVectorList(MI, 0, O, 0,'b'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; case 20: // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ... printTypedVectorList(MI, 0, O, 0,'h'); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); break; case 21: // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... printTypedVectorList(MI, 0, O, 16, 'b'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 22: // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... printTypedVectorList(MI, 1, O, 16, 'b'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 23: // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... printTypedVectorList(MI, 0, O, 1, 'd'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 24: // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... printTypedVectorList(MI, 1, O, 1, 'd'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 25: // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... printTypedVectorList(MI, 0, O, 2, 'd'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 26: // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... printTypedVectorList(MI, 1, O, 2, 'd'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 27: // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... printTypedVectorList(MI, 0, O, 2, 's'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 28: // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... printTypedVectorList(MI, 1, O, 2, 's'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 29: // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... printTypedVectorList(MI, 0, O, 4, 'h'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 30: // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... printTypedVectorList(MI, 1, O, 4, 'h'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 31: // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... printTypedVectorList(MI, 0, O, 4, 's'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 32: // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... printTypedVectorList(MI, 1, O, 4, 's'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 33: // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... printTypedVectorList(MI, 0, O, 8, 'b'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 34: // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... printTypedVectorList(MI, 1, O, 8, 'b'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 35: // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... printTypedVectorList(MI, 0, O, 8, 'h'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 36: // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... printTypedVectorList(MI, 1, O, 8, 'h'); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 37: // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... printTypedVectorList(MI, 1, O, 0, 'h'); printVectorIndex(MI, 2, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); break; case 38: // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST printTypedVectorList(MI, 2, O, 0, 'h'); printVectorIndex(MI, 3, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 4, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 39: // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... printTypedVectorList(MI, 1, O, 0, 's'); printVectorIndex(MI, 2, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); break; case 40: // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST printTypedVectorList(MI, 2, O, 0, 's'); printVectorIndex(MI, 3, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 4, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 41: // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... printTypedVectorList(MI, 1, O, 0, 'd'); printVectorIndex(MI, 2, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); break; case 42: // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST printTypedVectorList(MI, 2, O, 0, 'd'); printVectorIndex(MI, 3, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 4, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 43: // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... printTypedVectorList(MI, 1, O, 0, 'b'); printVectorIndex(MI, 2, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); break; case 44: // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST printTypedVectorList(MI, 2, O, 0, 'b'); printVectorIndex(MI, 3, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 4, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 45: // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI printSVERegOp(MI, 0, O, 0); break; case 46: // MSR printMSRSystemRegister(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 47: // MSRpstateImm1, MSRpstateImm4 printSystemPStateField(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 48: // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... printPrefetchOp(MI, 0, O, true); SStream_concat0(O, ", "); printSVERegOp(MI, 1, O, 0); SStream_concat0(O, ", ["); set_mem_access(MI, true); break; case 49: // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi printPrefetchOp(MI, 0, O, false); break; case 50: // ST1i16, ST2i16, ST3i16, ST4i16 printTypedVectorList(MI, 0, O, 0, 'h'); printVectorIndex(MI, 1, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 51: // ST1i32, ST2i32, ST3i32, ST4i32 printTypedVectorList(MI, 0, O, 0, 's'); printVectorIndex(MI, 1, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 52: // ST1i64, ST2i64, ST3i64, ST4i64 printTypedVectorList(MI, 0, O, 0, 'd'); printVectorIndex(MI, 1, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 53: // ST1i8, ST2i8, ST3i8, ST4i8 printTypedVectorList(MI, 0, O, 0, 'b'); printVectorIndex(MI, 1, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; } // Fragment 1 encoded into 6 bits for 56 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 63)); switch ((Bits >> 19) & 63) { default: // unreachable case 0: // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCSWr, ADCSXr, ADCWr, A... SStream_concat0(O, ", "); break; case 1: // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, CPY_ZPmI_... printSVERegOp(MI, 2, O, 0); break; case 2: // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... SStream_concat0(O, ".16b, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); break; case 3: // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... SStream_concat0(O, ".2s, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); break; case 4: // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... SStream_concat0(O, ".2d, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); break; case 5: // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... SStream_concat0(O, ".4h, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); break; case 6: // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... SStream_concat0(O, ".4s, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); break; case 7: // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... SStream_concat0(O, ".8h, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); break; case 8: // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... SStream_concat0(O, ".8b, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); break; case 9: // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, DUP_ZZI_H, FADD_ZZZ_H,... printSVERegOp(MI, 1, O, 'h'); break; case 10: // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... printSVERegOp(MI, 1, O, 0); break; case 11: // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... SStream_concat0(O, ", ["); set_mem_access(MI, true); break; case 12: // AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, BRAAZ, BRABZ,... return; break; case 13: // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... printSVEPattern(MI, 2, O); SStream_concat0(O, ", mul "); printOperand(MI, 3, O); return; break; case 14: // DUP_ZI_H printImm8OptLsl32(MI, 1, O); return; break; case 15: // DUP_ZR_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, WHILELE_PWW_... printOperand(MI, 1, O); break; case 16: // FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H printSVERegOp(MI, 2, O, 'h'); SStream_concat0(O, ", "); printSVERegOp(MI, 3, O, 'h'); printVectorIndex(MI, 4, O); break; case 17: // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri SStream_concat0(O, ", #0.0"); arm64_op_addFP(MI, 0); return; break; case 18: // FDUP_ZI_H printFPImmOperand(MI, 1, O); return; break; case 19: // FMOVXDHighr, INSvi64gpr, INSvi64lane SStream_concat0(O, ".d"); printVectorIndex(MI, 2, O); SStream_concat0(O, ", "); break; case 20: // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... SStream_concat0(O, "/z, ["); set_mem_access(MI, true); break; case 21: // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S... printOperand(MI, 2, O); break; case 22: // INSvi16gpr, INSvi16lane SStream_concat0(O, ".h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H); printVectorIndex(MI, 2, O); SStream_concat0(O, ", "); break; case 23: // INSvi32gpr, INSvi32lane SStream_concat0(O, ".s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); printVectorIndex(MI, 2, O); SStream_concat0(O, ", "); break; case 24: // INSvi8gpr, INSvi8lane SStream_concat0(O, ".b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B); printVectorIndex(MI, 2, O); SStream_concat0(O, ", "); break; case 25: // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... printPostIncOperand(MI, 3, O, 64); return; break; case 26: // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... printPostIncOperand(MI, 3, O, 32); return; break; case 27: // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... printPostIncOperand(MI, 3, O, 16); return; break; case 28: // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... printPostIncOperand(MI, 3, O, 8); return; break; case 29: // LD1Rv16b_POST, LD1Rv8b_POST printPostIncOperand(MI, 3, O, 1); return; break; case 30: // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... printPostIncOperand(MI, 3, O, 4); return; break; case 31: // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST printPostIncOperand(MI, 3, O, 2); return; break; case 32: // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... printPostIncOperand(MI, 3, O, 48); return; break; case 33: // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... printPostIncOperand(MI, 3, O, 24); return; break; case 34: // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 35: // LD1i16_POST, LD2i8_POST printPostIncOperand(MI, 5, O, 2); return; break; case 36: // LD1i32_POST, LD2i16_POST, LD4i8_POST printPostIncOperand(MI, 5, O, 4); return; break; case 37: // LD1i64_POST, LD2i32_POST, LD4i16_POST printPostIncOperand(MI, 5, O, 8); return; break; case 38: // LD1i8_POST printPostIncOperand(MI, 5, O, 1); return; break; case 39: // LD2i64_POST, LD4i32_POST printPostIncOperand(MI, 5, O, 16); return; break; case 40: // LD3Rv16b_POST, LD3Rv8b_POST printPostIncOperand(MI, 3, O, 3); return; break; case 41: // LD3Rv2s_POST, LD3Rv4s_POST printPostIncOperand(MI, 3, O, 12); return; break; case 42: // LD3Rv4h_POST, LD3Rv8h_POST printPostIncOperand(MI, 3, O, 6); return; break; case 43: // LD3i16_POST printPostIncOperand(MI, 5, O, 6); return; break; case 44: // LD3i32_POST printPostIncOperand(MI, 5, O, 12); return; break; case 45: // LD3i64_POST printPostIncOperand(MI, 5, O, 24); return; break; case 46: // LD3i8_POST printPostIncOperand(MI, 5, O, 3); return; break; case 47: // LD4i64_POST printPostIncOperand(MI, 5, O, 32); return; break; case 48: // PMULLv1i64, PMULLv2i64 SStream_concat0(O, ".1q, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); printVRegOperand(MI, 1, O); break; case 49: // PRFB_D_PZI, PRFD_D_PZI, PRFH_D_PZI, PRFW_D_PZI printSVERegOp(MI, 2, O, 'd'); SStream_concat0(O, ", "); break; case 50: // PRFB_S_PZI, PRFD_S_PZI, PRFH_S_PZI, PRFW_S_PZI printSVERegOp(MI, 2, O, 's'); SStream_concat0(O, ", "); break; case 51: // PTRUES_H, PTRUE_H printSVEPattern(MI, 1, O); return; break; case 52: // PUNPKHI_PP, PUNPKLO_PP, SUNPKHI_ZZ_H, SUNPKLO_ZZ_H, UUNPKHI_ZZ_H, UUNP... printSVERegOp(MI, 1, O, 'b'); return; break; case 53: // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... SStream_concat0(O, ".1d, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); break; case 54: // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 55: // TBL_ZZZ_H printTypedVectorList(MI, 1, O, 0,'h'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 'h'); return; break; } // Fragment 2 encoded into 6 bits for 57 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 25) & 63)); switch ((Bits >> 25) & 63) { default: // unreachable case 0: // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... printSVERegOp(MI, 2, O, 0); break; case 1: // ABS_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE... SStream_concat0(O, "/m, "); break; case 2: // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... printVRegOperand(MI, 1, O); break; case 3: // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, A... printOperand(MI, 1, O); break; case 4: // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... printVRegOperand(MI, 2, O); break; case 5: // ADD_ZI_B, ADD_ZZZ_B, ASR_WIDE_ZZZ_B, ASR_ZZI_B, DECP_XP_B, DUP_ZZI_B, ... printSVERegOp(MI, 1, O, 'b'); break; case 6: // ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2... printSVERegOp(MI, 1, O, 'd'); break; case 7: // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, CLASTA_ZPZ_H, CLASTB_Z... SStream_concat0(O, ", "); break; case 8: // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... printSVERegOp(MI, 1, O, 's'); break; case 9: // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, ANDV_VPZ_B, ANDV_VPZ_D... printSVERegOp(MI, 1, O, 0); break; case 10: // ADRP printAdrpLabel(MI, 1, O); return; break; case 11: // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... printOperand(MI, 2, O); break; case 12: // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... printImm(MI, 2, O); printShifter(MI, 3, O); return; break; case 13: // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... printAlignedLabel(MI, 1, O); return; break; case 14: // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... SStream_concat0(O, "/z, "); break; case 15: // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... printSVEPattern(MI, 1, O); break; case 16: // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... printSVEPattern(MI, 2, O); SStream_concat0(O, ", mul "); printOperand(MI, 3, O); return; break; case 17: // DECP_XP_H, INCP_XP_H, SQDECP_XPWd_H, SQDECP_XP_H, SQINCP_XPWd_H, SQINC... printSVERegOp(MI, 1, O, 'h'); break; case 18: // DECP_ZP_H, DUP_ZR_H, FEXPA_ZZ_H, FMLA_ZZZI_H, FMLS_ZZZI_H, FRECPE_ZZ_H... return; break; case 19: // DUPM_ZI printLogicalImm64(MI, 1, O); return; break; case 20: // DUP_ZI_B printImm8OptLsl32(MI, 1, O); return; break; case 21: // DUP_ZI_D printImm8OptLsl64(MI, 1, O); return; break; case 22: // DUP_ZI_S printImm8OptLsl32(MI, 1, O); return; break; case 23: // DUP_ZZI_H printVectorIndex(MI, 2, O); return; break; case 24: // FCMLA_ZZZI_S, FMLA_ZZZI_S, FMLS_ZZZI_S, GLD1B_S_IMM_REAL, GLD1H_S_IMM_... printSVERegOp(MI, 2, O, 's'); SStream_concat0(O, ", "); break; case 25: // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... printFPImmOperand(MI, 1, O); return; break; case 26: // FMLA_ZZZI_D, FMLS_ZZZI_D, GLD1B_D_IMM_REAL, GLD1D_IMM_REAL, GLD1H_D_IM... printSVERegOp(MI, 2, O, 'd'); SStream_concat0(O, ", "); break; case 27: // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr, PRFB_D_PZI, PRFB_S_PZI printOperand(MI, 3, O); break; case 28: // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane printVRegOperand(MI, 3, O); break; case 29: // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... printOperand(MI, 0, O); SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 30: // MOVID, MOVIv2d_ns printSIMDType10Operand(MI, 1, O); return; break; case 31: // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... printImm(MI, 1, O); break; case 32: // MRS printMRSSystemRegister(MI, 1, O); return; break; case 33: // PMULLv1i64 SStream_concat0(O, ".1d, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); printVRegOperand(MI, 2, O); SStream_concat0(O, ".1d"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); return; break; case 34: // PMULLv2i64 SStream_concat0(O, ".2d, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); printVRegOperand(MI, 2, O); SStream_concat0(O, ".2d"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); return; break; case 35: // PRFD_D_PZI, PRFD_S_PZI printImmScale(MI, 3, O, 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 36: // PRFH_D_PZI, PRFH_S_PZI printImmScale(MI, 3, O, 2); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 37: // PRFW_D_PZI, PRFW_S_PZI printImmScale(MI, 3, O, 4); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 38: // SDOT_ZZZI_D, SDOT_ZZZ_D, UDOT_ZZZI_D, UDOT_ZZZ_D printSVERegOp(MI, 2, O, 'h'); SStream_concat0(O, ", "); printSVERegOp(MI, 3, O, 'h'); break; case 39: // SDOT_ZZZI_S, SDOT_ZZZ_S, UDOT_ZZZI_S, UDOT_ZZZ_S printSVERegOp(MI, 2, O, 'b'); SStream_concat0(O, ", "); printSVERegOp(MI, 3, O, 'b'); break; case 40: // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... printGPR64as32(MI, 1, O); SStream_concat0(O, ", "); printSVEPattern(MI, 2, O); SStream_concat0(O, ", mul "); printOperand(MI, 3, O); return; break; case 41: // ST1i16_POST, ST2i8_POST printPostIncOperand(MI, 4, O, 2); return; break; case 42: // ST1i32_POST, ST2i16_POST, ST4i8_POST printPostIncOperand(MI, 4, O, 4); return; break; case 43: // ST1i64_POST, ST2i32_POST, ST4i16_POST printPostIncOperand(MI, 4, O, 8); return; break; case 44: // ST1i8_POST printPostIncOperand(MI, 4, O, 1); return; break; case 45: // ST2i64_POST, ST4i32_POST printPostIncOperand(MI, 4, O, 16); return; break; case 46: // ST3i16_POST printPostIncOperand(MI, 4, O, 6); return; break; case 47: // ST3i32_POST printPostIncOperand(MI, 4, O, 12); return; break; case 48: // ST3i64_POST printPostIncOperand(MI, 4, O, 24); return; break; case 49: // ST3i8_POST printPostIncOperand(MI, 4, O, 3); return; break; case 50: // ST4i64_POST printPostIncOperand(MI, 4, O, 32); return; break; case 51: // SYSxt printSysCROperand(MI, 1, O); SStream_concat0(O, ", "); printSysCROperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 4, O); return; break; case 52: // TBL_ZZZ_B printTypedVectorList(MI, 1, O, 0,'b'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 'b'); return; break; case 53: // TBL_ZZZ_D printTypedVectorList(MI, 1, O, 0,'d'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 'd'); return; break; case 54: // TBL_ZZZ_S printTypedVectorList(MI, 1, O, 0,'s'); SStream_concat0(O, ", "); printSVERegOp(MI, 2, O, 's'); return; break; case 55: // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... printTypedVectorList(MI, 1, O, 16, 'b'); SStream_concat0(O, ", "); printVRegOperand(MI, 2, O); break; case 56: // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... printTypedVectorList(MI, 2, O, 16, 'b'); SStream_concat0(O, ", "); printVRegOperand(MI, 3, O); break; } // Fragment 3 encoded into 7 bits for 91 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 31) & 127)); switch ((Bits >> 31) & 127) { default: // unreachable case 0: // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S... SStream_concat0(O, "/m, "); break; case 1: // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... printSVERegOp(MI, 3, O, 'h'); break; case 2: // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... SStream_concat0(O, ".16b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); return; break; case 3: // ABSv1i64, ADR, AUTDA, AUTDB, AUTIA, AUTIB, BLRAA, BLRAB, BRAA, BRAB, C... return; break; case 4: // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... SStream_concat0(O, ".2s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); return; break; case 5: // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... SStream_concat0(O, ".2d"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); return; break; case 6: // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... SStream_concat0(O, ".4h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); return; break; case 7: // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... SStream_concat0(O, ".4s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); return; break; case 8: // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... SStream_concat0(O, ".8h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); return; break; case 9: // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... SStream_concat0(O, ".8b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); return; break; case 10: // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, ADDSWrx, AD... SStream_concat0(O, ", "); break; case 11: // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... SStream_concat0(O, ".2d, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); break; case 12: // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... SStream_concat0(O, ".4s, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); break; case 13: // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... SStream_concat0(O, ".8h, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); break; case 14: // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... SStream_concat0(O, ".16b, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); break; case 15: // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... SStream_concat0(O, ".2s, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); break; case 16: // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... SStream_concat0(O, ".4h, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); break; case 17: // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... SStream_concat0(O, ".8b, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); break; case 18: // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... printImm8OptLsl32(MI, 2, O); return; break; case 19: // ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_... printSVERegOp(MI, 2, O, 'h'); break; case 20: // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... SStream_concat0(O, "/z, "); break; case 21: // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H printSVERegOp(MI, 2, O, 'd'); return; break; case 22: // ASR_ZZI_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, LSL_ZZI_H, ... printOperand(MI, 2, O); return; break; case 23: // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... SStream_concat0(O, ", ["); set_mem_access(MI, true); break; case 24: // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz SStream_concat0(O, ".16b, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); arm64_op_addImm(MI, 0); return; break; case 25: // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz SStream_concat0(O, ", #0"); op_addImm(MI, 0); arm64_op_addImm(MI, 0); return; break; case 26: // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz SStream_concat0(O, ".2s, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); arm64_op_addImm(MI, 0); return; break; case 27: // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz SStream_concat0(O, ".2d, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); arm64_op_addImm(MI, 0); return; break; case 28: // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz SStream_concat0(O, ".4h, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); arm64_op_addImm(MI, 0); return; break; case 29: // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz SStream_concat0(O, ".4s, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); arm64_op_addImm(MI, 0); return; break; case 30: // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz SStream_concat0(O, ".8h, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); arm64_op_addImm(MI, 0); return; break; case 31: // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz SStream_concat0(O, ".8b, #0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); arm64_op_addImm(MI, 0); return; break; case 32: // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI SStream_concat0(O, ", mul "); printOperand(MI, 2, O); return; break; case 33: // CPY_ZPmI_H printImm8OptLsl32(MI, 3, O); return; break; case 34: // CPY_ZPmR_H, CPY_ZPmV_H, GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_I... printOperand(MI, 3, O); break; case 35: // CPY_ZPzI_H printImm8OptLsl32(MI, 2, O); return; break; case 36: // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... SStream_concat0(O, ".h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H); break; case 37: // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... SStream_concat0(O, ".s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); break; case 38: // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 SStream_concat0(O, ".d"); break; case 39: // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... SStream_concat0(O, ".b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B); break; case 40: // DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S printVectorIndex(MI, 2, O); return; break; case 41: // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p SStream_concat0(O, ".2h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H); return; break; case 42: // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... SStream_concat0(O, ", #0.0"); arm64_op_addFP(MI, 0); return; break; case 43: // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz SStream_concat0(O, ".2s, #0.0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); arm64_op_addFP(MI, 0); return; break; case 44: // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz SStream_concat0(O, ".2d, #0.0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); arm64_op_addFP(MI, 0); return; break; case 45: // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz SStream_concat0(O, ".4h, #0.0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); arm64_op_addFP(MI, 0); return; break; case 46: // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz SStream_concat0(O, ".4s, #0.0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); arm64_op_addFP(MI, 0); return; break; case 47: // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz SStream_concat0(O, ".8h, #0.0"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); arm64_op_addFP(MI, 0); return; break; case 48: // FCMLA_ZZZI_H printComplexRotationOp(MI, 5, O, 90, 0); return; break; case 49: // FCMLA_ZZZI_S, FCVT_ZPmZ_StoH, FMLA_ZZZI_S, FMLS_ZZZI_S, SCVTF_ZPmZ_Sto... printSVERegOp(MI, 3, O, 's'); break; case 50: // FCPY_ZPmI_H printFPImmOperand(MI, 3, O); return; break; case 51: // FCVT_ZPmZ_DtoH, FMLA_ZZZI_D, FMLS_ZZZI_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_... printSVERegOp(MI, 3, O, 'd'); break; case 52: // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, SST1D_IMM printImmScale(MI, 3, O, 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 53: // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... printImmScale(MI, 3, O, 2); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 54: // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... printImmScale(MI, 3, O, 4); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 55: // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD... SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 56: // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 3, O); return; break; case 57: // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... printShifter(MI, 2, O); return; break; case 58: // PRFB_D_SCALED printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 59: // PRFB_D_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 60: // PRFB_D_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 61: // PRFB_PRR printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 62: // PRFB_S_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 63: // PRFB_S_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 64: // PRFD_D_SCALED printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 65: // PRFD_D_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 66: // PRFD_D_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 67: // PRFD_PRR printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 68: // PRFD_S_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 69: // PRFD_S_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 70: // PRFH_D_SCALED printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 71: // PRFH_D_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 72: // PRFH_D_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 73: // PRFH_PRR printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 74: // PRFH_S_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 75: // PRFH_S_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 76: // PRFS_PRR printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 77: // PRFW_D_SCALED printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 78: // PRFW_D_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 79: // PRFW_D_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 80: // PRFW_S_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 81: // PRFW_S_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 82: // RDFFRS_PPz, RDFFR_PPz SStream_concat0(O, "/z"); return; break; case 83: // SDOT_ZZZI_D, SDOT_ZZZI_S, UDOT_ZZZI_D, UDOT_ZZZI_S printVectorIndex(MI, 4, O); return; break; case 84: // SHLLv16i8 SStream_concat0(O, ".16b, #8"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); arm64_op_addImm(MI, 8); return; break; case 85: // SHLLv2i32 SStream_concat0(O, ".2s, #32"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); arm64_op_addImm(MI, 32); return; break; case 86: // SHLLv4i16 SStream_concat0(O, ".4h, #16"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); arm64_op_addImm(MI, 16); return; break; case 87: // SHLLv4i32 SStream_concat0(O, ".4s, #32"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); arm64_op_addImm(MI, 32); return; break; case 88: // SHLLv8i16 SStream_concat0(O, ".8h, #16"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); arm64_op_addImm(MI, 16); return; break; case 89: // SHLLv8i8 SStream_concat0(O, ".8b, #8"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); arm64_op_addImm(MI, 8); return; break; case 90: // UMAX_ZI_H, UMIN_ZI_H printImm(MI, 2, O); return; break; } // Fragment 4 encoded into 7 bits for 88 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 38) & 127)); switch ((Bits >> 38) & 127) { default: // unreachable case 0: // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, CLZ_ZPmZ_B, CNOT_ZPmZ_B,... printSVERegOp(MI, 3, O, 'b'); break; case 1: // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... printSVERegOp(MI, 3, O, 'd'); break; case 2: // ABS_ZPmZ_H, ADD_ZZZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H... return; break; case 3: // ABS_ZPmZ_S, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPmZ_S, FABS_ZPmZ... printSVERegOp(MI, 3, O, 's'); break; case 4: // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6... printOperand(MI, 2, O); break; case 5: // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... printVRegOperand(MI, 2, O); break; case 6: // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... printVRegOperand(MI, 3, O); break; case 7: // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri printAddSubImm(MI, 2, O); return; break; case 8: // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... printShiftedRegister(MI, 2, O); return; break; case 9: // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx printExtendedRegister(MI, 2, O); return; break; case 10: // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... printImm8OptLsl32(MI, 2, O); return; break; case 11: // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... printImm8OptLsl64(MI, 2, O); return; break; case 12: // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... printImm8OptLsl32(MI, 2, O); return; break; case 13: // ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, ANDV_VPZ_B, AND_PPzPP, AND_ZPmZ_B, ... printSVERegOp(MI, 2, O, 'b'); break; case 14: // ADD_ZPmZ_D, ADD_ZZZ_D, ANDV_VPZ_D, AND_ZPmZ_D, AND_ZZZ, ASRD_ZPmI_D, A... printSVERegOp(MI, 2, O, 'd'); break; case 15: // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... SStream_concat0(O, ", "); break; case 16: // ADD_ZPmZ_S, ADD_ZZZ_S, ANDV_VPZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ_... printSVERegOp(MI, 2, O, 's'); break; case 17: // ADR_LSL_ZZZ_D_0 printRegWithShiftExtend(MI, 2, O, false, 8, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 18: // ADR_LSL_ZZZ_D_1 printRegWithShiftExtend(MI, 2, O, false, 16, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 19: // ADR_LSL_ZZZ_D_2 printRegWithShiftExtend(MI, 2, O, false, 32, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 20: // ADR_LSL_ZZZ_D_3 printRegWithShiftExtend(MI, 2, O, false, 64, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 21: // ADR_LSL_ZZZ_S_0 printRegWithShiftExtend(MI, 2, O, false, 8, 'x', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 22: // ADR_LSL_ZZZ_S_1 printRegWithShiftExtend(MI, 2, O, false, 16, 'x', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 23: // ADR_LSL_ZZZ_S_2 printRegWithShiftExtend(MI, 2, O, false, 32, 'x', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 24: // ADR_LSL_ZZZ_S_3 printRegWithShiftExtend(MI, 2, O, false, 64, 'x', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 25: // ADR_SXTW_ZZZ_D_0 printRegWithShiftExtend(MI, 2, O, true, 8, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 26: // ADR_SXTW_ZZZ_D_1 printRegWithShiftExtend(MI, 2, O, true, 16, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 27: // ADR_SXTW_ZZZ_D_2 printRegWithShiftExtend(MI, 2, O, true, 32, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 28: // ADR_SXTW_ZZZ_D_3 printRegWithShiftExtend(MI, 2, O, true, 64, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 29: // ADR_UXTW_ZZZ_D_0 printRegWithShiftExtend(MI, 2, O, false, 8, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 30: // ADR_UXTW_ZZZ_D_1 printRegWithShiftExtend(MI, 2, O, false, 16, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 31: // ADR_UXTW_ZZZ_D_2 printRegWithShiftExtend(MI, 2, O, false, 32, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 32: // ADR_UXTW_ZZZ_D_3 printRegWithShiftExtend(MI, 2, O, false, 64, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 33: // ANDSWri, ANDWri, EORWri, ORRWri printLogicalImm32(MI, 2, O); return; break; case 34: // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI printLogicalImm64(MI, 2, O); return; break; case 35: // ANDV_VPZ_H, CNTP_XPP_H, EORV_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV_... printSVERegOp(MI, 2, O, 'h'); return; break; case 36: // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... printOperand(MI, 3, O); break; case 37: // CPY_ZPmI_B printImm8OptLsl32(MI, 3, O); return; break; case 38: // CPY_ZPmI_D printImm8OptLsl64(MI, 3, O); return; break; case 39: // CPY_ZPmI_S printImm8OptLsl32(MI, 3, O); return; break; case 40: // CPY_ZPzI_B printImm8OptLsl32(MI, 2, O); return; break; case 41: // CPY_ZPzI_D printImm8OptLsl64(MI, 2, O); return; break; case 42: // CPY_ZPzI_S printImm8OptLsl32(MI, 2, O); return; break; case 43: // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... printVectorIndex(MI, 2, O); return; break; case 44: // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... SStream_concat0(O, ", #0.0"); arm64_op_addFP(MI, 0); return; break; case 45: // FCMLA_ZZZI_S, FMLA_ZZZI_D, FMLA_ZZZI_S, FMLS_ZZZI_D, FMLS_ZZZI_S, INSv... printVectorIndex(MI, 4, O); break; case 46: // FCPY_ZPmI_D, FCPY_ZPmI_S printFPImmOperand(MI, 3, O); return; break; case 47: // FCVTZS_ZPmZ_HtoD, FCVTZS_ZPmZ_HtoS, FCVTZU_ZPmZ_HtoD, FCVTZU_ZPmZ_HtoS... printSVERegOp(MI, 3, O, 'h'); return; break; case 48: // FMUL_ZZZI_H printVectorIndex(MI, 3, O); return; break; case 49: // GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_IMM_REAL, GLD1SB_S_IMM_RE... SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 50: // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 51: // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 52: // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 53: // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 54: // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 55: // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 56: // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 57: // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 58: // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 59: // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 60: // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 61: // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 62: // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 63: // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 64: // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 65: // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 'd'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 66: // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 67: // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 's'); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 68: // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RQ_B, LD1SB_D, LD1SB_H, LD1SB_S, LD2B... printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 69: // LD1D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1D, ST2D, ... printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 70: // LD1H, LD1H_D, LD1H_S, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, LD4H, LDF... printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 71: // LD1RD_IMM, LDRAAwriteback, LDRABwriteback printImmScale(MI, 3, O, 8); break; case 72: // LD1RH_D_IMM, LD1RH_IMM, LD1RH_S_IMM, LD1RSH_D_IMM, LD1RSH_S_IMM, LD2B_... printImmScale(MI, 3, O, 2); break; case 73: // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM printImmScale(MI, 3, O, 16); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 74: // LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_REAL, LDFF... printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 0); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 75: // LD1RSW_IMM, LD1RW_D_IMM, LD1RW_IMM, LD4B_IMM, LD4D_IMM, LD4H_IMM, LD4W... printImmScale(MI, 3, O, 4); break; case 76: // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ... printImmScale(MI, 3, O, 3); SStream_concat0(O, ", mul vl]"); set_mem_access(MI, false); return; break; case 77: // LDRAAindexed, LDRABindexed printImmScale(MI, 2, O, 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 78: // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui printUImm12Offset(MI, 2, O, 1); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 79: // LDRDui, LDRXui, PRFMui, STRDui, STRXui printUImm12Offset(MI, 2, O, 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 80: // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui printUImm12Offset(MI, 2, O, 2); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 81: // LDRQui, STRQui printUImm12Offset(MI, 2, O, 16); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 82: // LDRSWui, LDRSui, LDRWui, STRSui, STRWui printUImm12Offset(MI, 2, O, 4); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 83: // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI SStream_concat0(O, ", mul vl]"); set_mem_access(MI, false); return; break; case 84: // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... printGPR64as32(MI, 2, O); return; break; case 85: // SYSLxt printSysCROperand(MI, 2, O); SStream_concat0(O, ", "); printSysCROperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 4, O); return; break; case 86: // TBNZW, TBNZX, TBZW, TBZX printAlignedLabel(MI, 2, O); return; break; case 87: // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S printImm(MI, 2, O); return; break; } // Fragment 5 encoded into 6 bits for 36 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 45) & 63)); switch ((Bits >> 45) & 63) { default: // unreachable case 0: // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDP... return; break; case 1: // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... SStream_concat0(O, ".2d"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); return; break; case 2: // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... SStream_concat0(O, ".4s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); return; break; case 3: // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... SStream_concat0(O, ".8h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); return; break; case 4: // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... SStream_concat0(O, ".16b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); return; break; case 5: // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... SStream_concat0(O, ".2s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); return; break; case 6: // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... SStream_concat0(O, ".4h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); return; break; case 7: // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... SStream_concat0(O, ".8b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); return; break; case 8: // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 printArithExtend(MI, 3, O); return; break; case 9: // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B,... SStream_concat0(O, ", "); break; case 10: // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... printSVERegOp(MI, 3, O, 'h'); break; case 11: // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... printOperand(MI, 3, O); return; break; case 12: // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... printSVERegOp(MI, 3, O, 'd'); return; break; case 13: // BCAX, EOR3, EXTv16i8 SStream_concat0(O, ".16b, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); break; case 14: // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 15: // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H printImm(MI, 3, O); return; break; case 16: // EXTv8i8 SStream_concat0(O, ".8b, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); printOperand(MI, 3, O); return; break; case 17: // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one); return; break; case 18: // FCADDv2f32, FCMLAv2f32 SStream_concat0(O, ".2s, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); break; case 19: // FCADDv2f64, FCMLAv2f64, XAR SStream_concat0(O, ".2d, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); break; case 20: // FCADDv4f16, FCMLAv4f16 SStream_concat0(O, ".4h, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); break; case 21: // FCADDv4f32, FCMLAv4f32, SM3SS1 SStream_concat0(O, ".4s, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); break; case 22: // FCADDv8f16, FCMLAv8f16 SStream_concat0(O, ".8h, "); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); break; case 23: // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... SStream_concat0(O, ", #0.0"); arm64_op_addFP(MI, 0); return; break; case 24: // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,... printSVERegOp(MI, 4, O, 'h'); break; case 25: // FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAv1i16_indexed, FMLAv4i16_i... SStream_concat0(O, ".h"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H); break; case 26: // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... SStream_concat0(O, ".s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); break; case 27: // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H printExactFPImm(MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one); return; break; case 28: // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... SStream_concat0(O, ".d"); break; case 29: // FMUL_ZPmI_H printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two); return; break; case 30: // FMUL_ZZZI_D, FMUL_ZZZI_S printVectorIndex(MI, 3, O); return; break; case 31: // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D... SStream_concat0(O, ", mul vl]"); set_mem_access(MI, false); return; break; case 32: // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 33: // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ... SStream_concat0(O, "]!"); set_mem_access(MI, false); return; break; case 34: // SDOTlanev16i8, SDOTlanev8i8, UDOTlanev16i8, UDOTlanev8i8 SStream_concat0(O, ".4b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4B); printVectorIndex(MI, 4, O); return; break; case 35: // STLXPW, STLXPX, STXPW, STXPX SStream_concat0(O, ", ["); set_mem_access(MI, true); printOperand(MI, 3, O); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; } // Fragment 6 encoded into 6 bits for 38 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 51) & 63)); switch ((Bits >> 51) & 63) { default: // unreachable case 0: // ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_B, ASR_ZPmZ_B... printSVERegOp(MI, 3, O, 'b'); return; break; case 1: // ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR_WIDE_ZPmZ_S,... printSVERegOp(MI, 3, O, 'd'); break; case 2: // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... return; break; case 3: // ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ_S, CLASTA_RP... printSVERegOp(MI, 3, O, 's'); break; case 4: // ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, ASR_ZPm... printOperand(MI, 3, O); return; break; case 5: // BCAX, EOR3, SM3SS1 printVRegOperand(MI, 3, O); break; case 6: // BFMWri, BFMXri printOperand(MI, 4, O); return; break; case 7: // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... printCondCode(MI, 3, O); return; break; case 8: // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H, FADDA_VPZ_H printSVERegOp(MI, 3, O, 'h'); return; break; case 9: // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... printImm(MI, 3, O); return; break; case 10: // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one); return; break; case 11: // FCADD_ZPmZ_H, FCMLA_ZPmZZ_H SStream_concat0(O, ", "); break; case 12: // FCADDv2f32, FCADDv2f64, FCADDv4f16, FCADDv4f32, FCADDv8f16 printComplexRotationOp(MI, 3, O, 180, 90); return; break; case 13: // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... printSVERegOp(MI, 4, O, 'd'); break; case 14: // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... printSVERegOp(MI, 4, O, 's'); break; case 15: // FCMLA_ZZZI_S printComplexRotationOp(MI, 5, O, 90, 0); return; break; case 16: // FCMLAv2f32, FCMLAv2f64, FCMLAv4f16, FCMLAv4f32, FCMLAv8f16 printComplexRotationOp(MI, 4, O, 90, 0); return; break; case 17: // FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv8f16_indexed, FMLAv1i16_... printVectorIndex(MI, 4, O); break; case 18: // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... printExactFPImm(MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one); return; break; case 19: // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... printVectorIndex(MI, 3, O); return; break; case 20: // FMUL_ZPmI_D, FMUL_ZPmI_S printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two); return; break; case 21: // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi printImmScale(MI, 3, O, 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 22: // LDNPQi, LDPQi, STNPQi, STPQi printImmScale(MI, 3, O, 16); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 23: // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi printImmScale(MI, 3, O, 4); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 24: // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... printImmScale(MI, 4, O, 8); break; case 25: // LDPQpost, LDPQpre, STPQpost, STPQpre printImmScale(MI, 4, O, 16); break; case 26: // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... printImmScale(MI, 4, O, 4); break; case 27: // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW printMemExtend(MI, 3, O, 'w', 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 28: // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX printMemExtend(MI, 3, O, 'x', 8); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 29: // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW printMemExtend(MI, 3, O, 'w', 64); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 30: // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX printMemExtend(MI, 3, O, 'x', 64); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 31: // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW printMemExtend(MI, 3, O, 'w', 16); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 32: // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX printMemExtend(MI, 3, O, 'x', 16); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 33: // LDRQroW, STRQroW printMemExtend(MI, 3, O, 'w', 128); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 34: // LDRQroX, STRQroX printMemExtend(MI, 3, O, 'x', 128); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 35: // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW printMemExtend(MI, 3, O, 'w', 32); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 36: // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX printMemExtend(MI, 3, O, 'x', 32); SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 37: // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B printSVERegOp(MI, 4, O, 'b'); return; break; } // Fragment 7 encoded into 3 bits for 7 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 57) & 7)); switch ((Bits >> 57) & 7) { default: // unreachable case 0: // ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ_S, ASRR_ZPmZ_D, ASRR_ZPmZ... return; break; case 1: // BCAX, EOR3 SStream_concat0(O, ".16b"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); return; break; case 2: // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i... SStream_concat0(O, ", "); break; case 3: // FCADD_ZPmZ_H printComplexRotationOp(MI, 4, O, 180, 90); return; break; case 4: // FCMLA_ZPmZZ_H printComplexRotationOp(MI, 5, O, 90, 0); return; break; case 5: // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... SStream_concat0(O, "]!"); set_mem_access(MI, false); return; break; case 6: // SM3SS1 SStream_concat0(O, ".4s"); arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); return; break; } // Fragment 8 encoded into 1 bits for 2 unique commands. // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 60) & 1)); if ((Bits >> 60) & 1) { // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_indexed, FCMLAv4f32_indexed, ... printComplexRotationOp(MI, 5, O, 90, 0); return; } else { // FCADD_ZPmZ_D, FCADD_ZPmZ_S printComplexRotationOp(MI, 4, O, 180, 90); return; } } #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, unsigned PredicateIndex); static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) { #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) unsigned int I = 0, OpIdx, PrintMethodIdx; char *tmpString; const char *AsmString; switch (MCInst_getOpcode(MI)) { default: return false; case AArch64_ADDSWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) AsmString = "cmn $\x02, $\xFF\x03\x01"; break; } return NULL; case AArch64_ADDSWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDSWrx: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDSXri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) AsmString = "cmn $\x02, $\xFF\x03\x01"; break; } return NULL; case AArch64_ADDSXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDSXrx: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; break; } return NULL; case AArch64_ADDSXrx64: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) AsmString = "mov $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) AsmString = "mov $\x01, $\x02"; break; } return NULL; case AArch64_ADDWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDWrx: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) AsmString = "add $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDXri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) AsmString = "mov $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) AsmString = "mov $\x01, $\x02"; break; } return NULL; case AArch64_ADDXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ADDXrx64: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) AsmString = "add $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ANDSWri: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1)) { // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) AsmString = "tst $\x02, $\xFF\x03\x04"; break; } return NULL; case AArch64_ANDSWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) AsmString = "tst $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "ands $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ANDSXri: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1)) { // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) AsmString = "tst $\x02, $\xFF\x03\x05"; break; } return NULL; case AArch64_ANDSXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) AsmString = "tst $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "ands $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ANDS_PPzPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 2)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; break; } return NULL; case AArch64_ANDWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "and $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ANDXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "and $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_AND_PPzPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 2)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; break; } return NULL; case AArch64_AND_ZI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) AsmString = "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) AsmString = "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) AsmString = "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; break; } return NULL; case AArch64_BICSWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "bics $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_BICSXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "bics $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_BICWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "bic $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_BICXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "bic $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_CLREX: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { // (CLREX 15) AsmString = "clrex"; break; } return NULL; case AArch64_CNTB_XPiI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) AsmString = "cntb $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) AsmString = "cntb $\x01, $\xFF\x02\x0E"; break; } return NULL; case AArch64_CNTD_XPiI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) AsmString = "cntd $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) AsmString = "cntd $\x01, $\xFF\x02\x0E"; break; } return NULL; case AArch64_CNTH_XPiI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) AsmString = "cnth $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) AsmString = "cnth $\x01, $\xFF\x02\x0E"; break; } return NULL; case AArch64_CNTW_XPiI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) AsmString = "cntw $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) AsmString = "cntw $\x01, $\xFF\x02\x0E"; break; } return NULL; case AArch64_CPY_ZPmI_B: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F"; break; } return NULL; case AArch64_CPY_ZPmI_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11"; break; } return NULL; case AArch64_CPY_ZPmI_H: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12"; break; } return NULL; case AArch64_CPY_ZPmI_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13"; break; } return NULL; case AArch64_CPY_ZPmR_B: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmR_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmR_H: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmR_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmV_B: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmV_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmV_H: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPmV_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; break; } return NULL; case AArch64_CPY_ZPzI_B: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F"; break; } return NULL; case AArch64_CPY_ZPzI_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11"; break; } return NULL; case AArch64_CPY_ZPzI_H: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12"; break; } return NULL; case AArch64_CPY_ZPzI_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13"; break; } return NULL; case AArch64_CSINCWr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) AsmString = "cset $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; case AArch64_CSINCXr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) AsmString = "cset $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; case AArch64_CSINVWr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) AsmString = "csetm $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; case AArch64_CSINVXr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) AsmString = "csetm $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; case AArch64_CSNEGWr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; case AArch64_CSNEGXr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; case AArch64_DCPS1: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (DCPS1 0) AsmString = "dcps1"; break; } return NULL; case AArch64_DCPS2: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (DCPS2 0) AsmString = "dcps2"; break; } return NULL; case AArch64_DCPS3: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (DCPS3 0) AsmString = "dcps3"; break; } return NULL; case AArch64_DECB_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "decb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "decb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DECD_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "decd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "decd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DECD_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "decd $\xFF\x01\x10"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "decd $\xFF\x01\x10, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DECH_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "dech $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "dech $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DECH_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "dech $\xFF\x01\x09"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "dech $\xFF\x01\x09, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DECW_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "decw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "decw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DECW_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "decw $\xFF\x01\x0B"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "decw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; case AArch64_DUPM_ZI: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 5) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x15"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 6) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x16"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 7) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x17"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) AsmString = "dupm $\xFF\x01\x06, $\xFF\x02\x08"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) AsmString = "dupm $\xFF\x01\x09, $\xFF\x02\x0A"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) AsmString = "dupm $\xFF\x01\x0B, $\xFF\x02\x04"; break; } return NULL; case AArch64_DUP_ZI_B: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x0F"; break; } return NULL; case AArch64_DUP_ZI_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x11"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_D ZPR64:$Zd, 0, 0) AsmString = "fmov $\xFF\x01\x10, #0.0"; break; } return NULL; case AArch64_DUP_ZI_H: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x12"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_H ZPR16:$Zd, 0, 0) AsmString = "fmov $\xFF\x01\x09, #0.0"; break; } return NULL; case AArch64_DUP_ZI_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x13"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZI_S ZPR32:$Zd, 0, 0) AsmString = "fmov $\xFF\x01\x0B, #0.0"; break; } return NULL; case AArch64_DUP_ZR_B: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) AsmString = "mov $\xFF\x01\x06, $\x02"; break; } return NULL; case AArch64_DUP_ZR_D: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) AsmString = "mov $\xFF\x01\x10, $\x02"; break; } return NULL; case AArch64_DUP_ZR_H: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) AsmString = "mov $\xFF\x01\x09, $\x02"; break; } return NULL; case AArch64_DUP_ZR_S: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) AsmString = "mov $\xFF\x01\x0B, $\x02"; break; } return NULL; case AArch64_DUP_ZZI_B: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x18"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19"; break; } return NULL; case AArch64_DUP_ZZI_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x1A"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19"; break; } return NULL; case AArch64_DUP_ZZI_H: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x1B"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19"; break; } return NULL; case AArch64_DUP_ZZI_Q: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1D"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19"; break; } return NULL; case AArch64_DUP_ZZI_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x1E"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19"; break; } return NULL; case AArch64_EONWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "eon $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_EONXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "eon $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_EORS_PPzPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) AsmString = "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; break; } return NULL; case AArch64_EORWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "eor $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_EORXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "eor $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_EOR_PPzPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) AsmString = "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; break; } return NULL; case AArch64_EOR_ZI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) AsmString = "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) AsmString = "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) AsmString = "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; break; } return NULL; case AArch64_EXTRWrri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) AsmString = "ror $\x01, $\x02, $\x04"; break; } return NULL; case AArch64_EXTRXrri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) AsmString = "ror $\x01, $\x02, $\x04"; break; } return NULL; case AArch64_FCPY_ZPmI_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) AsmString = "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F"; break; } return NULL; case AArch64_FCPY_ZPmI_H: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) AsmString = "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F"; break; } return NULL; case AArch64_FCPY_ZPmI_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) AsmString = "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F"; break; } return NULL; case AArch64_FDUP_ZI_D: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) AsmString = "fmov $\xFF\x01\x10, $\xFF\x02\x1F"; break; } return NULL; case AArch64_FDUP_ZI_H: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) AsmString = "fmov $\xFF\x01\x09, $\xFF\x02\x1F"; break; } return NULL; case AArch64_FDUP_ZI_S: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) AsmString = "fmov $\xFF\x01\x0B, $\xFF\x02\x1F"; break; } return NULL; case AArch64_GLD1B_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1B_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLD1D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1H_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1H_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLD1SB_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1SB_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLD1SH_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1SH_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLD1SW_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1W_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLD1W_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLDFF1B_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1B_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLDFF1D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1H_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1H_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLDFF1SB_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1SB_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLDFF1SH_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1SH_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_GLDFF1SW_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1W_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_GLDFF1W_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_HINT: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (HINT { 0, 0, 0 }) AsmString = "nop"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { // (HINT { 0, 0, 1 }) AsmString = "yield"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { // (HINT { 0, 1, 0 }) AsmString = "wfe"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { // (HINT { 0, 1, 1 }) AsmString = "wfi"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { // (HINT { 1, 0, 0 }) AsmString = "sev"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { // (HINT { 1, 0, 1 }) AsmString = "sevl"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && AArch64_getFeatureBits(AArch64_FeatureRAS)) { // (HINT { 1, 0, 0, 0, 0 }) AsmString = "esb"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20) { // (HINT 20) AsmString = "csdb"; break; } if (MCInst_getNumOperands(MI) == 1 && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 0), 8) && AArch64_getFeatureBits(AArch64_FeatureSPE)) { // (HINT psbhint_op:$op) AsmString = "psb $\xFF\x01\x22"; break; } return NULL; case AArch64_INCB_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "incb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "incb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INCD_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "incd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "incd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INCD_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "incd $\xFF\x01\x10"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "incd $\xFF\x01\x10, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INCH_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "inch $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "inch $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INCH_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "inch $\xFF\x01\x09"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "inch $\xFF\x01\x09, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INCW_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "incw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "incw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INCW_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "incw $\xFF\x01\x0B"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "incw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; case AArch64_INSvi16gpr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi16lane: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19"; break; } return NULL; case AArch64_INSvi32gpr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi32lane: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19"; break; } return NULL; case AArch64_INSvi64gpr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi64lane: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19"; break; } return NULL; case AArch64_INSvi8gpr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi8lane: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19"; break; } return NULL; case AArch64_ISB: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { // (ISB 15) AsmString = "isb"; break; } return NULL; case AArch64_LD1B_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1B_H_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1B_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1B_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Fourv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_LD1Fourv1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x26, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_LD1Fourv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_LD1Fourv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #64"; break; } return NULL; case AArch64_LD1H_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1H_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1H_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Onev16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x25, [$\x01], #16"; break; } return NULL; case AArch64_LD1Onev1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x26, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x27, [$\x01], #16"; break; } return NULL; case AArch64_LD1Onev2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x28, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x29, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #16"; break; } return NULL; case AArch64_LD1Onev8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #16"; break; } return NULL; case AArch64_LD1RB_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RB_H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RB_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RB_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RD_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RH_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RH_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RH_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RQ_B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rqb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RQ_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RQ_H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rqh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RQ_W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RSB_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RSB_H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RSB_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RSH_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RSH_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RSW_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RW_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1RW_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Rv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x25, [$\x01], #1"; break; } return NULL; case AArch64_LD1Rv1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x26, [$\x01], #8"; break; } return NULL; case AArch64_LD1Rv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x27, [$\x01], #8"; break; } return NULL; case AArch64_LD1Rv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x28, [$\x01], #4"; break; } return NULL; case AArch64_LD1Rv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x29, [$\x01], #2"; break; } return NULL; case AArch64_LD1Rv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x2A, [$\x01], #4"; break; } return NULL; case AArch64_LD1Rv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x2B, [$\x01], #1"; break; } return NULL; case AArch64_LD1Rv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) AsmString = "ld1r $\xFF\x02\x2C, [$\x01], #2"; break; } return NULL; case AArch64_LD1SB_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1SB_H_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1SB_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1SH_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1SH_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1SW_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Threev16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_LD1Threev1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x26, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_LD1Threev2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_LD1Threev8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #48"; break; } return NULL; case AArch64_LD1Twov16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_LD1Twov1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x26, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_LD1Twov2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_LD1Twov8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #32"; break; } return NULL; case AArch64_LD1W_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1W_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1i16_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) AsmString = "ld1 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #2"; break; } return NULL; case AArch64_LD1i32_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) AsmString = "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4"; break; } return NULL; case AArch64_LD1i64_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) AsmString = "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8"; break; } return NULL; case AArch64_LD1i8_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) AsmString = "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #1"; break; } return NULL; case AArch64_LD2B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld2b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD2D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD2H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld2h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD2Rv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x25, [$\x01], #2"; break; } return NULL; case AArch64_LD2Rv1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x26, [$\x01], #16"; break; } return NULL; case AArch64_LD2Rv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x27, [$\x01], #16"; break; } return NULL; case AArch64_LD2Rv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x28, [$\x01], #8"; break; } return NULL; case AArch64_LD2Rv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x29, [$\x01], #4"; break; } return NULL; case AArch64_LD2Rv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x2A, [$\x01], #8"; break; } return NULL; case AArch64_LD2Rv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x2B, [$\x01], #2"; break; } return NULL; case AArch64_LD2Rv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) AsmString = "ld2r $\xFF\x02\x2C, [$\x01], #4"; break; } return NULL; case AArch64_LD2Twov16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_LD2Twov2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_LD2Twov2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_LD2Twov4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_LD2Twov4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_LD2Twov8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_LD2Twov8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) AsmString = "ld2 $\xFF\x02\x2C, [$\x01], #32"; break; } return NULL; case AArch64_LD2W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD2i16_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) AsmString = "ld2 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #4"; break; } return NULL; case AArch64_LD2i32_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) AsmString = "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8"; break; } return NULL; case AArch64_LD2i64_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) AsmString = "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16"; break; } return NULL; case AArch64_LD2i8_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) AsmString = "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #2"; break; } return NULL; case AArch64_LD3B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld3b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD3D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD3H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld3h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD3Rv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x25, [$\x01], #3"; break; } return NULL; case AArch64_LD3Rv1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x26, [$\x01], #24"; break; } return NULL; case AArch64_LD3Rv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x27, [$\x01], #24"; break; } return NULL; case AArch64_LD3Rv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x28, [$\x01], #12"; break; } return NULL; case AArch64_LD3Rv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x29, [$\x01], #6"; break; } return NULL; case AArch64_LD3Rv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x2A, [$\x01], #12"; break; } return NULL; case AArch64_LD3Rv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x2B, [$\x01], #3"; break; } return NULL; case AArch64_LD3Rv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) AsmString = "ld3r $\xFF\x02\x2C, [$\x01], #6"; break; } return NULL; case AArch64_LD3Threev16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_LD3Threev2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_LD3Threev2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_LD3Threev4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_LD3Threev4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_LD3Threev8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_LD3Threev8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) AsmString = "ld3 $\xFF\x02\x2C, [$\x01], #48"; break; } return NULL; case AArch64_LD3W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD3i16_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) AsmString = "ld3 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #6"; break; } return NULL; case AArch64_LD3i32_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) AsmString = "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #12"; break; } return NULL; case AArch64_LD3i64_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) AsmString = "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #24"; break; } return NULL; case AArch64_LD3i8_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) AsmString = "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #3"; break; } return NULL; case AArch64_LD4B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld4b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4Fourv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_LD4Fourv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_LD4Fourv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_LD4Fourv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_LD4Fourv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_LD4Fourv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_LD4Fourv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) AsmString = "ld4 $\xFF\x02\x2C, [$\x01], #64"; break; } return NULL; case AArch64_LD4H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld4h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4Rv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x25, [$\x01], #4"; break; } return NULL; case AArch64_LD4Rv1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x26, [$\x01], #32"; break; } return NULL; case AArch64_LD4Rv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_LD4Rv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_LD4Rv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x29, [$\x01], #8"; break; } return NULL; case AArch64_LD4Rv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x2A, [$\x01], #16"; break; } return NULL; case AArch64_LD4Rv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x2B, [$\x01], #4"; break; } return NULL; case AArch64_LD4Rv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) AsmString = "ld4r $\xFF\x02\x2C, [$\x01], #8"; break; } return NULL; case AArch64_LD4W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4i16_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) AsmString = "ld4 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #8"; break; } return NULL; case AArch64_LD4i32_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) AsmString = "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #16"; break; } return NULL; case AArch64_LD4i64_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) AsmString = "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #32"; break; } return NULL; case AArch64_LD4i8_POST: if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) AsmString = "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #4"; break; } return NULL; case AArch64_LDADDB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "staddb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "staddh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "staddlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "staddlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "staddl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "staddl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stadd $\x02, [$\x03]"; break; } return NULL; case AArch64_LDADDX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stadd $\x02, [$\x03]"; break; } return NULL; case AArch64_LDAPURBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapurb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapurh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURSBWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapursb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURSBXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapursb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURSHWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapursh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURSHXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapursh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURSWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapursw $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDAPURi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldapur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDCLRB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stclrb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stclrh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stclrlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stclrlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stclrl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stclrl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stclr $\x02, [$\x03]"; break; } return NULL; case AArch64_LDCLRX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stclr $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "steorb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "steorh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "steorlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "steorlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "steorl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "steorl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "steor $\x02, [$\x03]"; break; } return NULL; case AArch64_LDEORX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "steor $\x02, [$\x03]"; break; } return NULL; case AArch64_LDFF1B_D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1B_H_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1B_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1B_S_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1H_D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1H_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1H_S_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1SB_D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1SB_H_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1SB_S_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1SH_D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1SH_S_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1SW_D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1W_D_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDFF1W_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1B_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1B_H_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1B_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1B_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1H_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1H_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1H_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1SB_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1SB_H_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1SB_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1SH_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1SH_S_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1SW_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1W_D_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNF1W_IMM_REAL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNPDi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDNPQi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDNPSi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDNPWi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDNPXi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDNT1B_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNT1D_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNT1H_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDNT1W_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LDPDi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDPQi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDPSWi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldpsw $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDPSi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDPWi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDPXi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_LDRAAindexed: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_3aOps)) { // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldraa $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRABindexed: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_3aOps)) { // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrab $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRBBroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrb $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRBBui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRBroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRBui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRDroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRDui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRHHroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrh $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRHHui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRHroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRHui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRQroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRQui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRSBWroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrsb $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRSBWui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrsb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRSBXroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrsb $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRSBXui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrsb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRSHWroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrsh $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRSHWui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrsh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRSHXroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrsh $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRSHXui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrsh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRSWroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldrsw $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRSWui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldrsw $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRSroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRSui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRWroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRWui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDRXroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_LDRXui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDR_PXI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) AsmString = "ldr $\xFF\x01\x07, [$\x02]"; break; } return NULL; case AArch64_LDR_ZXI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) AsmString = "ldr $\xFF\x01\x07, [$\x02]"; break; } return NULL; case AArch64_LDSETB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsetb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stseth $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsetlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsetlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsetl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stsetl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stset $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSETX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stset $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmaxb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmaxh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmaxlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmaxlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmaxl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stsmaxl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmax $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMAXX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stsmax $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsminb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsminh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsminlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsminlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsminl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stsminl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stsmin $\x02, [$\x03]"; break; } return NULL; case AArch64_LDSMINX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stsmin $\x02, [$\x03]"; break; } return NULL; case AArch64_LDTRBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRSBWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrsb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRSBXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrsb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRSHWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrsh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRSHXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrsh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRSWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtrsw $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDTRXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldtr $\x01, [$\x02]"; break; } return NULL; case AArch64_LDUMAXB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumaxb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumaxh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumaxlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumaxlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumaxl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stumaxl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumax $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMAXX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stumax $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stuminb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stuminh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINLB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stuminlb $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINLH: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stuminlh $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stuminl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINLX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stuminl $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) AsmString = "stumin $\x02, [$\x03]"; break; } return NULL; case AArch64_LDUMINX: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && AArch64_getFeatureBits(AArch64_FeatureLSE)) { // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) AsmString = "stumin $\x02, [$\x03]"; break; } return NULL; case AArch64_LDURBBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldurb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURDi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURHHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldurh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURQi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURSBWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldursb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURSBXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldursb $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURSHWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "ldursh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURSHXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldursh $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURSWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "ldursw $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURSi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_LDURXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; case AArch64_MADDWrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) AsmString = "mul $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_MADDXrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) AsmString = "mul $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_MSUBWrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) AsmString = "mneg $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_MSUBXrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) AsmString = "mneg $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_NOTv16i8: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { // (NOTv16i8 V128:$Vd, V128:$Vn) AsmString = "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; break; } return NULL; case AArch64_NOTv8i8: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1)) { // (NOTv8i8 V64:$Vd, V64:$Vn) AsmString = "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; break; } return NULL; case AArch64_ORNWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) AsmString = "mvn $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "orn $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ORNXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) AsmString = "mvn $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "orn $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ORRS_PPzPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x06"; break; } return NULL; case AArch64_ORRWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) AsmString = "mov $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "orr $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ORRXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) AsmString = "mov $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "orr $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_ORR_PPzPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06"; break; } return NULL; case AArch64_ORR_ZI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) AsmString = "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 2) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) AsmString = "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 3) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) AsmString = "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; break; } return NULL; case AArch64_ORR_ZZZ: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10"; break; } return NULL; case AArch64_ORRv16i8: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (ORRv16i8 V128:$dst, V128:$src, V128:$src) AsmString = "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; break; } return NULL; case AArch64_ORRv8i8: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (ORRv8i8 V64:$dst, V64:$src, V64:$src) AsmString = "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; break; } return NULL; case AArch64_PRFB_D_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_PRFB_PRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_PRFB_S_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_PRFD_D_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_PRFD_PRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_PRFD_S_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_PRFH_D_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_PRFH_PRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_PRFH_S_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_PRFMroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "prfm $\xFF\x01\x33, [$\x02, $\x03]"; break; } return NULL; case AArch64_PRFMui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) AsmString = "prfm $\xFF\x01\x33, [$\x02]"; break; } return NULL; case AArch64_PRFUMi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) AsmString = "prfum $\xFF\x01\x33, [$\x02]"; break; } return NULL; case AArch64_PRFW_D_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_PRFW_PRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_PRFW_S_PZI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_PTRUES_B: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrues $\xFF\x01\x06"; break; } return NULL; case AArch64_PTRUES_D: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrues $\xFF\x01\x10"; break; } return NULL; case AArch64_PTRUES_H: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrues $\xFF\x01\x09"; break; } return NULL; case AArch64_PTRUES_S: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrues $\xFF\x01\x0B"; break; } return NULL; case AArch64_PTRUE_B: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrue $\xFF\x01\x06"; break; } return NULL; case AArch64_PTRUE_D: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrue $\xFF\x01\x10"; break; } return NULL; case AArch64_PTRUE_H: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrue $\xFF\x01\x09"; break; } return NULL; case AArch64_PTRUE_S: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) AsmString = "ptrue $\xFF\x01\x0B"; break; } return NULL; case AArch64_RET: if (MCInst_getNumOperands(MI) == 1 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) { // (RET LR) AsmString = "ret"; break; } return NULL; case AArch64_SBCSWr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SBCSWr GPR32:$dst, WZR, GPR32:$src) AsmString = "ngcs $\x01, $\x03"; break; } return NULL; case AArch64_SBCSXr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SBCSXr GPR64:$dst, XZR, GPR64:$src) AsmString = "ngcs $\x01, $\x03"; break; } return NULL; case AArch64_SBCWr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SBCWr GPR32:$dst, WZR, GPR32:$src) AsmString = "ngc $\x01, $\x03"; break; } return NULL; case AArch64_SBCXr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SBCXr GPR64:$dst, XZR, GPR64:$src) AsmString = "ngc $\x01, $\x03"; break; } return NULL; case AArch64_SBFMWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) AsmString = "asr $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) AsmString = "sxtb $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) AsmString = "sxth $\x01, $\x02"; break; } return NULL; case AArch64_SBFMXri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) AsmString = "asr $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) AsmString = "sxtb $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) AsmString = "sxth $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) AsmString = "sxtw $\x01, $\x02"; break; } return NULL; case AArch64_SEL_PPPP: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; break; } return NULL; case AArch64_SEL_ZPZZ_B: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; break; } return NULL; case AArch64_SEL_ZPZZ_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10"; break; } return NULL; case AArch64_SEL_ZPZZ_H: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09"; break; } return NULL; case AArch64_SEL_ZPZZ_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B"; break; } return NULL; case AArch64_SMADDLrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) AsmString = "smull $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SMSUBLrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) AsmString = "smnegl $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SQDECB_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqdecb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECB_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecb $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqdecb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECD_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqdecd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECD_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecd $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqdecd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECD_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecd $\xFF\x01\x10"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECH_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdech $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqdech $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECH_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdech $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqdech $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECH_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdech $\xFF\x01\x09"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "sqdech $\xFF\x01\x09, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECW_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqdecw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECW_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecw $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqdecw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQDECW_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqdecw $\xFF\x01\x0B"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCB_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqincb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCB_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincb $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqincb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCD_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqincd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCD_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincd $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqincd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCD_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincd $\xFF\x01\x10"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "sqincd $\xFF\x01\x10, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCH_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqinch $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqinch $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCH_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqinch $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqinch $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCH_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqinch $\xFF\x01\x09"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "sqinch $\xFF\x01\x09, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCW_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "sqincw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCW_XPiWdI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincw $\x01, $\xFF\x02\x34"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) AsmString = "sqincw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SQINCW_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "sqincw $\xFF\x01\x0B"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; case AArch64_SST1B_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_SST1B_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_SST1D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_SST1H_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_SST1H_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_SST1W_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; break; } return NULL; case AArch64_SST1W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; case AArch64_ST1B_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1B_H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1B_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1Fourv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_ST1Fourv1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x26, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_ST1Fourv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_ST1Fourv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2C, [$\x01], #64"; break; } return NULL; case AArch64_ST1H_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1H_S_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1Onev16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x25, [$\x01], #16"; break; } return NULL; case AArch64_ST1Onev1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x26, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x27, [$\x01], #16"; break; } return NULL; case AArch64_ST1Onev2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x28, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x29, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2A, [$\x01], #16"; break; } return NULL; case AArch64_ST1Onev8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2B, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2C, [$\x01], #16"; break; } return NULL; case AArch64_ST1Threev16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_ST1Threev1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x26, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_ST1Threev2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_ST1Threev8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2C, [$\x01], #48"; break; } return NULL; case AArch64_ST1Twov16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_ST1Twov1d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x26, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) AsmString = "st1 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_ST1Twov2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_ST1Twov8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) AsmString = "st1 $\xFF\x02\x2C, [$\x01], #32"; break; } return NULL; case AArch64_ST1W_D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1i16_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) AsmString = "st1 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #2"; break; } return NULL; case AArch64_ST1i32_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) AsmString = "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4"; break; } return NULL; case AArch64_ST1i64_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) AsmString = "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8"; break; } return NULL; case AArch64_ST1i8_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) AsmString = "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #1"; break; } return NULL; case AArch64_ST2B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st2b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST2D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST2H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st2h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST2Twov16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) AsmString = "st2 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_ST2Twov2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) AsmString = "st2 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_ST2Twov2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) AsmString = "st2 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_ST2Twov4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) AsmString = "st2 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_ST2Twov4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) AsmString = "st2 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_ST2Twov8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) AsmString = "st2 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_ST2Twov8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) AsmString = "st2 $\xFF\x02\x2C, [$\x01], #32"; break; } return NULL; case AArch64_ST2W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST2i16_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) AsmString = "st2 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #4"; break; } return NULL; case AArch64_ST2i32_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) AsmString = "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8"; break; } return NULL; case AArch64_ST2i64_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) AsmString = "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16"; break; } return NULL; case AArch64_ST2i8_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) AsmString = "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #2"; break; } return NULL; case AArch64_ST3B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st3b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST3D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST3H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st3h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST3Threev16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) AsmString = "st3 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_ST3Threev2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) AsmString = "st3 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_ST3Threev2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) AsmString = "st3 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_ST3Threev4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) AsmString = "st3 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_ST3Threev4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) AsmString = "st3 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_ST3Threev8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) AsmString = "st3 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_ST3Threev8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) AsmString = "st3 $\xFF\x02\x2C, [$\x01], #48"; break; } return NULL; case AArch64_ST3W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST3i16_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) AsmString = "st3 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #6"; break; } return NULL; case AArch64_ST3i32_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) AsmString = "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #12"; break; } return NULL; case AArch64_ST3i64_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) AsmString = "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #24"; break; } return NULL; case AArch64_ST3i8_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) AsmString = "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #3"; break; } return NULL; case AArch64_ST4B_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st4b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST4D_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST4Fourv16b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) AsmString = "st4 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_ST4Fourv2d_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) AsmString = "st4 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_ST4Fourv2s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) AsmString = "st4 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_ST4Fourv4h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) AsmString = "st4 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_ST4Fourv4s_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) AsmString = "st4 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_ST4Fourv8b_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) AsmString = "st4 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_ST4Fourv8h_POST: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) AsmString = "st4 $\xFF\x02\x2C, [$\x01], #64"; break; } return NULL; case AArch64_ST4H_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st4h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST4W_IMM: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST4i16_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) AsmString = "st4 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #8"; break; } return NULL; case AArch64_ST4i32_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) AsmString = "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #16"; break; } return NULL; case AArch64_ST4i64_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) AsmString = "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #32"; break; } return NULL; case AArch64_ST4i8_POST: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) AsmString = "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #4"; break; } return NULL; case AArch64_STLURBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "stlurb $\x01, [$\x02]"; break; } return NULL; case AArch64_STLURHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "stlurh $\x01, [$\x02]"; break; } return NULL; case AArch64_STLURWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "stlur $\x01, [$\x02]"; break; } return NULL; case AArch64_STLURXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "stlur $\x01, [$\x02]"; break; } return NULL; case AArch64_STNPDi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STNPQi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STNPSi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STNPWi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STNPXi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STNT1B_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_STNT1D_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_STNT1H_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_STNT1W_ZRI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) AsmString = "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_STPDi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STPQi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STPSi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STPWi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STPXi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; case AArch64_STRBBroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "strb $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRBBui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "strb $\x01, [$\x02]"; break; } return NULL; case AArch64_STRBroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRBui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STRDroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRDui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STRHHroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "strh $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRHHui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "strh $\x01, [$\x02]"; break; } return NULL; case AArch64_STRHroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRHui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STRQroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRQui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STRSroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRSui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STRWroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRWui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STRXroX: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; case AArch64_STRXui: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) AsmString = "str $\x01, [$\x02]"; break; } return NULL; case AArch64_STR_PXI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) AsmString = "str $\xFF\x01\x07, [$\x02]"; break; } return NULL; case AArch64_STR_ZXI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) AsmString = "str $\xFF\x01\x07, [$\x02]"; break; } return NULL; case AArch64_STTRBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "sttrb $\x01, [$\x02]"; break; } return NULL; case AArch64_STTRHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "sttrh $\x01, [$\x02]"; break; } return NULL; case AArch64_STTRWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) AsmString = "sttr $\x01, [$\x02]"; break; } return NULL; case AArch64_STTRXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) AsmString = "sttr $\x01, [$\x02]"; break; } return NULL; case AArch64_STURBBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "sturb $\x01, [$\x02]"; break; } return NULL; case AArch64_STURBi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_STURDi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_STURHHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "sturh $\x01, [$\x02]"; break; } return NULL; case AArch64_STURHi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_STURQi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_STURSi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_STURWi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_STURXi: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) AsmString = "stur $\x01, [$\x02]"; break; } return NULL; case AArch64_SUBSWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) AsmString = "cmp $\x02, $\xFF\x03\x01"; break; } return NULL; case AArch64_SUBSWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) AsmString = "negs $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBSWrx: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBSXri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) AsmString = "cmp $\x02, $\xFF\x03\x01"; break; } return NULL; case AArch64_SUBSXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) AsmString = "negs $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBSXrx: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; break; } return NULL; case AArch64_SUBSXrx64: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) AsmString = "neg $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBWrx: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) AsmString = "sub $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBXrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) AsmString = "neg $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SUBXrx64: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) AsmString = "sub $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_SYSxt: if (MCInst_getNumOperands(MI) == 5 && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) { // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) AsmString = "sys $\x01, $\xFF\x02\x35, $\xFF\x03\x35, $\x04"; break; } return NULL; case AArch64_UBFMWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) AsmString = "lsr $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) AsmString = "uxtb $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) AsmString = "uxth $\x01, $\x02"; break; } return NULL; case AArch64_UBFMXri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) AsmString = "lsr $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) AsmString = "uxtb $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) AsmString = "uxth $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) AsmString = "uxtw $\x01, $\x02"; break; } return NULL; case AArch64_UMADDLrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) AsmString = "umull $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_UMOVvi32: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) AsmString = "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19"; break; } return NULL; case AArch64_UMOVvi64: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) AsmString = "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19"; break; } return NULL; case AArch64_UMSUBLrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) AsmString = "umnegl $\x01, $\x02, $\x03"; break; } return NULL; case AArch64_UQDECB_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECB_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECD_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECD_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECD_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecd $\xFF\x01\x10"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECH_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdech $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdech $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECH_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdech $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdech $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECH_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdech $\xFF\x01\x09"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "uqdech $\xFF\x01\x09, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECW_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECW_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQDECW_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqdecw $\xFF\x01\x0B"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCB_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqincb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCB_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincb $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqincb $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCD_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqincd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCD_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincd $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqincd $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCD_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincd $\xFF\x01\x10"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "uqincd $\xFF\x01\x10, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCH_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqinch $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqinch $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCH_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqinch $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqinch $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCH_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqinch $\xFF\x01\x09"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "uqinch $\xFF\x01\x09, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCW_WPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqincw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCW_XPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincw $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) AsmString = "uqincw $\x01, $\xFF\x03\x0E"; break; } return NULL; case AArch64_UQINCW_ZPiI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) AsmString = "uqincw $\xFF\x01\x0B"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && AArch64_getFeatureBits(AArch64_FeatureSVE)) { // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) AsmString = "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; } tmpString = cs_strdup(AsmString); while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && AsmString[I] != '\0') ++I; tmpString[I] = 0; SStream_concat0(OS, tmpString); if (AsmString[I] != '\0') { if (AsmString[I] == ' ' || AsmString[I] == '\t') { SStream_concat0(OS, " "); ++I; } do { if (AsmString[I] == '$') { ++I; if (AsmString[I] == (char)0xff) { ++I; OpIdx = AsmString[I++] - 1; PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else { printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } } else { if (AsmString[I] == '[') { set_mem_access(MI, true); } else if (AsmString[I] == ']') { set_mem_access(MI, false); } SStream_concat1(OS, AsmString[I++]); } } while (AsmString[I] != '\0'); } return tmpString; } static void printCustomAliasOperand( MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: break; case 0: printAddSubImm(MI, OpIdx, OS); break; case 1: printShifter(MI, OpIdx, OS); break; case 2: printArithExtend(MI, OpIdx, OS); break; case 3: printLogicalImm32(MI, OpIdx, OS); break; case 4: printLogicalImm64(MI, OpIdx, OS); break; case 5: printSVERegOp(MI, OpIdx, OS, 'b'); break; case 6: printSVERegOp(MI, OpIdx, OS, 0); break; case 7: printLogicalImm32(MI, OpIdx, OS); break; case 8: printSVERegOp(MI, OpIdx, OS, 'h'); break; case 9: printLogicalImm32(MI, OpIdx, OS); break; case 10: printSVERegOp(MI, OpIdx, OS, 's'); break; case 11: printVRegOperand(MI, OpIdx, OS); break; case 12: printImm(MI, OpIdx, OS); break; case 13: printSVEPattern(MI, OpIdx, OS); break; case 14: printImm8OptLsl32(MI, OpIdx, OS); break; case 15: printSVERegOp(MI, OpIdx, OS, 'd'); break; case 16: printImm8OptLsl64(MI, OpIdx, OS); break; case 17: printImm8OptLsl32(MI, OpIdx, OS); break; case 18: printImm8OptLsl32(MI, OpIdx, OS); break; case 19: printInverseCondCode(MI, OpIdx, OS); break; case 20: printSVELogicalImm16(MI, OpIdx, OS); break; case 21: printSVELogicalImm32(MI, OpIdx, OS); break; case 22: printSVELogicalImm64(MI, OpIdx, OS); break; case 23: printZPRasFPR(MI, OpIdx, OS, 8); break; case 24: printVectorIndex(MI, OpIdx, OS); break; case 25: printZPRasFPR(MI, OpIdx, OS, 64); break; case 26: printZPRasFPR(MI, OpIdx, OS, 16); break; case 27: printSVERegOp(MI, OpIdx, OS, 'q'); break; case 28: printZPRasFPR(MI, OpIdx, OS, 128); break; case 29: printZPRasFPR(MI, OpIdx, OS, 32); break; case 30: printFPImmOperand(MI, OpIdx, OS); break; case 31: printTypedVectorList(MI, OpIdx, OS, 0,'d'); break; case 32: printTypedVectorList(MI, OpIdx, OS, 0,'s'); break; case 33: printPSBHintOp(MI, OpIdx, OS); break; case 34: printTypedVectorList(MI, OpIdx, OS, 0,'h'); break; case 35: printTypedVectorList(MI, OpIdx, OS, 0,'b'); break; case 36: printTypedVectorList(MI, OpIdx, OS, 16, 'b'); break; case 37: printTypedVectorList(MI, OpIdx, OS, 1, 'd'); break; case 38: printTypedVectorList(MI, OpIdx, OS, 2, 'd'); break; case 39: printTypedVectorList(MI, OpIdx, OS, 2, 's'); break; case 40: printTypedVectorList(MI, OpIdx, OS, 4, 'h'); break; case 41: printTypedVectorList(MI, OpIdx, OS, 4, 's'); break; case 42: printTypedVectorList(MI, OpIdx, OS, 8, 'b'); break; case 43: printTypedVectorList(MI, OpIdx, OS, 8, 'h'); break; case 44: printTypedVectorList(MI, OpIdx, OS, 0, 'h'); break; case 45: printTypedVectorList(MI, OpIdx, OS, 0, 's'); break; case 46: printTypedVectorList(MI, OpIdx, OS, 0, 'd'); break; case 47: printTypedVectorList(MI, OpIdx, OS, 0, 'b'); break; case 48: printImmHex(MI, OpIdx, OS); break; case 49: printPrefetchOp(MI, OpIdx, OS, true); break; case 50: printPrefetchOp(MI, OpIdx, OS, false); break; case 51: printGPR64as32(MI, OpIdx, OS); break; case 52: printSysCROperand(MI, OpIdx, OS); break; } } static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, unsigned PredicateIndex) { int64_t Val; switch (PredicateIndex) { default: return false; // never reach break; case 1: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements8(Val); } case 2: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements16(Val); } case 3: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements32(Val); } case 4: { return MCOperand_isImm(MCOp) && MCOperand_getImm(MCOp) != AArch64CC_AL && MCOperand_getImm(MCOp) != AArch64CC_NV; } case 5: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements16(Val) && AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); } case 6: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements32(Val) && AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); } case 7: { if (!MCOperand_isImm(MCOp)) return false; Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); return AArch64_AM_isSVEMaskOfIdenticalElements64(Val) && AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); } case 8: { // Check, if operand is valid, to fix exhaustive aliasing in disassembly. // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. if (!MCOperand_isImm(MCOp)) return false; return AArch64PSBHint_lookupPSBByEncoding(MCOperand_getImm(MCOp)) != NULL; } } } #endif // PRINT_ALIAS_INSTR capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenDisassemblerTables.inc000064400000000000000000054545450072674642500242440ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /* Automatically generated file, do not edit! */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. //#if defined(_MSC_VER) && !defined(__clang__) //__declspec(noinline) //#endif #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ... /* 3 */ MCD_OPC_FilterValue, 1, 215, 111, 0, // Skip to: 28639 /* 8 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 11 */ MCD_OPC_FilterValue, 0, 120, 43, 0, // Skip to: 11144 /* 16 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 19 */ MCD_OPC_FilterValue, 0, 209, 17, 0, // Skip to: 4585 /* 24 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 27 */ MCD_OPC_FilterValue, 0, 22, 8, 0, // Skip to: 2102 /* 32 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 35 */ MCD_OPC_FilterValue, 0, 67, 2, 0, // Skip to: 619 /* 40 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 43 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 79 /* 48 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 51 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 65 /* 56 */ MCD_OPC_CheckPredicate, 0, 103, 83, 1, // Skip to: 86948 /* 61 */ MCD_OPC_Decode, 185, 1, 0, // Opcode: ADD_ZPmZ_B /* 65 */ MCD_OPC_FilterValue, 1, 94, 83, 1, // Skip to: 86948 /* 70 */ MCD_OPC_CheckPredicate, 0, 89, 83, 1, // Skip to: 86948 /* 75 */ MCD_OPC_Decode, 187, 1, 0, // Opcode: ADD_ZPmZ_H /* 79 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 115 /* 84 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 87 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 101 /* 92 */ MCD_OPC_CheckPredicate, 0, 67, 83, 1, // Skip to: 86948 /* 97 */ MCD_OPC_Decode, 247, 29, 0, // Opcode: SUB_ZPmZ_B /* 101 */ MCD_OPC_FilterValue, 1, 58, 83, 1, // Skip to: 86948 /* 106 */ MCD_OPC_CheckPredicate, 0, 53, 83, 1, // Skip to: 86948 /* 111 */ MCD_OPC_Decode, 249, 29, 0, // Opcode: SUB_ZPmZ_H /* 115 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 151 /* 120 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 123 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 137 /* 128 */ MCD_OPC_CheckPredicate, 0, 31, 83, 1, // Skip to: 86948 /* 133 */ MCD_OPC_Decode, 221, 29, 0, // Opcode: SUBR_ZPmZ_B /* 137 */ MCD_OPC_FilterValue, 1, 22, 83, 1, // Skip to: 86948 /* 142 */ MCD_OPC_CheckPredicate, 0, 17, 83, 1, // Skip to: 86948 /* 147 */ MCD_OPC_Decode, 223, 29, 0, // Opcode: SUBR_ZPmZ_H /* 151 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 187 /* 156 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 159 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 173 /* 164 */ MCD_OPC_CheckPredicate, 0, 251, 82, 1, // Skip to: 86948 /* 169 */ MCD_OPC_Decode, 196, 23, 0, // Opcode: SMAX_ZPmZ_B /* 173 */ MCD_OPC_FilterValue, 1, 242, 82, 1, // Skip to: 86948 /* 178 */ MCD_OPC_CheckPredicate, 0, 237, 82, 1, // Skip to: 86948 /* 183 */ MCD_OPC_Decode, 198, 23, 0, // Opcode: SMAX_ZPmZ_H /* 187 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 223 /* 192 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 195 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 209 /* 200 */ MCD_OPC_CheckPredicate, 0, 215, 82, 1, // Skip to: 86948 /* 205 */ MCD_OPC_Decode, 252, 31, 0, // Opcode: UMAX_ZPmZ_B /* 209 */ MCD_OPC_FilterValue, 1, 206, 82, 1, // Skip to: 86948 /* 214 */ MCD_OPC_CheckPredicate, 0, 201, 82, 1, // Skip to: 86948 /* 219 */ MCD_OPC_Decode, 254, 31, 0, // Opcode: UMAX_ZPmZ_H /* 223 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 259 /* 228 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 231 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 245 /* 236 */ MCD_OPC_CheckPredicate, 0, 179, 82, 1, // Skip to: 86948 /* 241 */ MCD_OPC_Decode, 226, 23, 0, // Opcode: SMIN_ZPmZ_B /* 245 */ MCD_OPC_FilterValue, 1, 170, 82, 1, // Skip to: 86948 /* 250 */ MCD_OPC_CheckPredicate, 0, 165, 82, 1, // Skip to: 86948 /* 255 */ MCD_OPC_Decode, 228, 23, 0, // Opcode: SMIN_ZPmZ_H /* 259 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 295 /* 264 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 /* 272 */ MCD_OPC_CheckPredicate, 0, 143, 82, 1, // Skip to: 86948 /* 277 */ MCD_OPC_Decode, 153, 32, 0, // Opcode: UMIN_ZPmZ_B /* 281 */ MCD_OPC_FilterValue, 1, 134, 82, 1, // Skip to: 86948 /* 286 */ MCD_OPC_CheckPredicate, 0, 129, 82, 1, // Skip to: 86948 /* 291 */ MCD_OPC_Decode, 155, 32, 0, // Opcode: UMIN_ZPmZ_H /* 295 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 331 /* 300 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 303 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 317 /* 308 */ MCD_OPC_CheckPredicate, 0, 107, 82, 1, // Skip to: 86948 /* 313 */ MCD_OPC_Decode, 136, 22, 0, // Opcode: SABD_ZPmZ_B /* 317 */ MCD_OPC_FilterValue, 1, 98, 82, 1, // Skip to: 86948 /* 322 */ MCD_OPC_CheckPredicate, 0, 93, 82, 1, // Skip to: 86948 /* 327 */ MCD_OPC_Decode, 138, 22, 0, // Opcode: SABD_ZPmZ_H /* 331 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 367 /* 336 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 339 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 353 /* 344 */ MCD_OPC_CheckPredicate, 0, 71, 82, 1, // Skip to: 86948 /* 349 */ MCD_OPC_Decode, 254, 30, 0, // Opcode: UABD_ZPmZ_B /* 353 */ MCD_OPC_FilterValue, 1, 62, 82, 1, // Skip to: 86948 /* 358 */ MCD_OPC_CheckPredicate, 0, 57, 82, 1, // Skip to: 86948 /* 363 */ MCD_OPC_Decode, 128, 31, 0, // Opcode: UABD_ZPmZ_H /* 367 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 403 /* 372 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 375 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 389 /* 380 */ MCD_OPC_CheckPredicate, 0, 35, 82, 1, // Skip to: 86948 /* 385 */ MCD_OPC_Decode, 153, 20, 0, // Opcode: MUL_ZPmZ_B /* 389 */ MCD_OPC_FilterValue, 1, 26, 82, 1, // Skip to: 86948 /* 394 */ MCD_OPC_CheckPredicate, 0, 21, 82, 1, // Skip to: 86948 /* 399 */ MCD_OPC_Decode, 155, 20, 0, // Opcode: MUL_ZPmZ_H /* 403 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 439 /* 408 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 411 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 425 /* 416 */ MCD_OPC_CheckPredicate, 0, 255, 81, 1, // Skip to: 86948 /* 421 */ MCD_OPC_Decode, 134, 24, 0, // Opcode: SMULH_ZPmZ_B /* 425 */ MCD_OPC_FilterValue, 1, 246, 81, 1, // Skip to: 86948 /* 430 */ MCD_OPC_CheckPredicate, 0, 241, 81, 1, // Skip to: 86948 /* 435 */ MCD_OPC_Decode, 136, 24, 0, // Opcode: SMULH_ZPmZ_H /* 439 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 475 /* 444 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 447 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 461 /* 452 */ MCD_OPC_CheckPredicate, 0, 219, 81, 1, // Skip to: 86948 /* 457 */ MCD_OPC_Decode, 188, 32, 0, // Opcode: UMULH_ZPmZ_B /* 461 */ MCD_OPC_FilterValue, 1, 210, 81, 1, // Skip to: 86948 /* 466 */ MCD_OPC_CheckPredicate, 0, 205, 81, 1, // Skip to: 86948 /* 471 */ MCD_OPC_Decode, 190, 32, 0, // Opcode: UMULH_ZPmZ_H /* 475 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 511 /* 480 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 483 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 497 /* 488 */ MCD_OPC_CheckPredicate, 0, 183, 81, 1, // Skip to: 86948 /* 493 */ MCD_OPC_Decode, 212, 20, 0, // Opcode: ORR_ZPmZ_B /* 497 */ MCD_OPC_FilterValue, 1, 174, 81, 1, // Skip to: 86948 /* 502 */ MCD_OPC_CheckPredicate, 0, 169, 81, 1, // Skip to: 86948 /* 507 */ MCD_OPC_Decode, 214, 20, 0, // Opcode: ORR_ZPmZ_H /* 511 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 547 /* 516 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 519 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 533 /* 524 */ MCD_OPC_CheckPredicate, 0, 147, 81, 1, // Skip to: 86948 /* 529 */ MCD_OPC_Decode, 240, 5, 0, // Opcode: EOR_ZPmZ_B /* 533 */ MCD_OPC_FilterValue, 1, 138, 81, 1, // Skip to: 86948 /* 538 */ MCD_OPC_CheckPredicate, 0, 133, 81, 1, // Skip to: 86948 /* 543 */ MCD_OPC_Decode, 242, 5, 0, // Opcode: EOR_ZPmZ_H /* 547 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 583 /* 552 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 555 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 569 /* 560 */ MCD_OPC_CheckPredicate, 0, 111, 81, 1, // Skip to: 86948 /* 565 */ MCD_OPC_Decode, 247, 1, 0, // Opcode: AND_ZPmZ_B /* 569 */ MCD_OPC_FilterValue, 1, 102, 81, 1, // Skip to: 86948 /* 574 */ MCD_OPC_CheckPredicate, 0, 97, 81, 1, // Skip to: 86948 /* 579 */ MCD_OPC_Decode, 249, 1, 0, // Opcode: AND_ZPmZ_H /* 583 */ MCD_OPC_FilterValue, 27, 88, 81, 1, // Skip to: 86948 /* 588 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 591 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 605 /* 596 */ MCD_OPC_CheckPredicate, 0, 75, 81, 1, // Skip to: 86948 /* 601 */ MCD_OPC_Decode, 182, 2, 0, // Opcode: BIC_ZPmZ_B /* 605 */ MCD_OPC_FilterValue, 1, 66, 81, 1, // Skip to: 86948 /* 610 */ MCD_OPC_CheckPredicate, 0, 61, 81, 1, // Skip to: 86948 /* 615 */ MCD_OPC_Decode, 184, 2, 0, // Opcode: BIC_ZPmZ_H /* 619 */ MCD_OPC_FilterValue, 1, 143, 1, 0, // Skip to: 1023 /* 624 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 627 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 663 /* 632 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 635 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 649 /* 640 */ MCD_OPC_CheckPredicate, 0, 31, 81, 1, // Skip to: 86948 /* 645 */ MCD_OPC_Decode, 169, 22, 1, // Opcode: SADDV_VPZ_B /* 649 */ MCD_OPC_FilterValue, 1, 22, 81, 1, // Skip to: 86948 /* 654 */ MCD_OPC_CheckPredicate, 0, 17, 81, 1, // Skip to: 86948 /* 659 */ MCD_OPC_Decode, 170, 22, 1, // Opcode: SADDV_VPZ_H /* 663 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 699 /* 668 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 671 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 685 /* 676 */ MCD_OPC_CheckPredicate, 0, 251, 80, 1, // Skip to: 86948 /* 681 */ MCD_OPC_Decode, 159, 31, 1, // Opcode: UADDV_VPZ_B /* 685 */ MCD_OPC_FilterValue, 1, 242, 80, 1, // Skip to: 86948 /* 690 */ MCD_OPC_CheckPredicate, 0, 237, 80, 1, // Skip to: 86948 /* 695 */ MCD_OPC_Decode, 161, 31, 1, // Opcode: UADDV_VPZ_H /* 699 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 735 /* 704 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 707 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 721 /* 712 */ MCD_OPC_CheckPredicate, 0, 215, 80, 1, // Skip to: 86948 /* 717 */ MCD_OPC_Decode, 183, 23, 2, // Opcode: SMAXV_VPZ_B /* 721 */ MCD_OPC_FilterValue, 1, 206, 80, 1, // Skip to: 86948 /* 726 */ MCD_OPC_CheckPredicate, 0, 201, 80, 1, // Skip to: 86948 /* 731 */ MCD_OPC_Decode, 185, 23, 3, // Opcode: SMAXV_VPZ_H /* 735 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 771 /* 740 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 743 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 757 /* 748 */ MCD_OPC_CheckPredicate, 0, 179, 80, 1, // Skip to: 86948 /* 753 */ MCD_OPC_Decode, 239, 31, 2, // Opcode: UMAXV_VPZ_B /* 757 */ MCD_OPC_FilterValue, 1, 170, 80, 1, // Skip to: 86948 /* 762 */ MCD_OPC_CheckPredicate, 0, 165, 80, 1, // Skip to: 86948 /* 767 */ MCD_OPC_Decode, 241, 31, 3, // Opcode: UMAXV_VPZ_H /* 771 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 807 /* 776 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 779 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 793 /* 784 */ MCD_OPC_CheckPredicate, 0, 143, 80, 1, // Skip to: 86948 /* 789 */ MCD_OPC_Decode, 213, 23, 2, // Opcode: SMINV_VPZ_B /* 793 */ MCD_OPC_FilterValue, 1, 134, 80, 1, // Skip to: 86948 /* 798 */ MCD_OPC_CheckPredicate, 0, 129, 80, 1, // Skip to: 86948 /* 803 */ MCD_OPC_Decode, 215, 23, 3, // Opcode: SMINV_VPZ_H /* 807 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 843 /* 812 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 815 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 829 /* 820 */ MCD_OPC_CheckPredicate, 0, 107, 80, 1, // Skip to: 86948 /* 825 */ MCD_OPC_Decode, 140, 32, 2, // Opcode: UMINV_VPZ_B /* 829 */ MCD_OPC_FilterValue, 1, 98, 80, 1, // Skip to: 86948 /* 834 */ MCD_OPC_CheckPredicate, 0, 93, 80, 1, // Skip to: 86948 /* 839 */ MCD_OPC_Decode, 142, 32, 3, // Opcode: UMINV_VPZ_H /* 843 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 879 /* 848 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 851 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865 /* 856 */ MCD_OPC_CheckPredicate, 0, 71, 80, 1, // Skip to: 86948 /* 861 */ MCD_OPC_Decode, 251, 19, 4, // Opcode: MOVPRFX_ZPzZ_B /* 865 */ MCD_OPC_FilterValue, 1, 62, 80, 1, // Skip to: 86948 /* 870 */ MCD_OPC_CheckPredicate, 0, 57, 80, 1, // Skip to: 86948 /* 875 */ MCD_OPC_Decode, 253, 19, 4, // Opcode: MOVPRFX_ZPzZ_H /* 879 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 915 /* 884 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 887 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 901 /* 892 */ MCD_OPC_CheckPredicate, 0, 35, 80, 1, // Skip to: 86948 /* 897 */ MCD_OPC_Decode, 247, 19, 5, // Opcode: MOVPRFX_ZPmZ_B /* 901 */ MCD_OPC_FilterValue, 1, 26, 80, 1, // Skip to: 86948 /* 906 */ MCD_OPC_CheckPredicate, 0, 21, 80, 1, // Skip to: 86948 /* 911 */ MCD_OPC_Decode, 249, 19, 5, // Opcode: MOVPRFX_ZPmZ_H /* 915 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 951 /* 920 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 923 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 937 /* 928 */ MCD_OPC_CheckPredicate, 0, 255, 79, 1, // Skip to: 86948 /* 933 */ MCD_OPC_Decode, 223, 20, 2, // Opcode: ORV_VPZ_B /* 937 */ MCD_OPC_FilterValue, 1, 246, 79, 1, // Skip to: 86948 /* 942 */ MCD_OPC_CheckPredicate, 0, 241, 79, 1, // Skip to: 86948 /* 947 */ MCD_OPC_Decode, 225, 20, 3, // Opcode: ORV_VPZ_H /* 951 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 987 /* 956 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 959 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 973 /* 964 */ MCD_OPC_CheckPredicate, 0, 219, 79, 1, // Skip to: 86948 /* 969 */ MCD_OPC_Decode, 228, 5, 2, // Opcode: EORV_VPZ_B /* 973 */ MCD_OPC_FilterValue, 1, 210, 79, 1, // Skip to: 86948 /* 978 */ MCD_OPC_CheckPredicate, 0, 205, 79, 1, // Skip to: 86948 /* 983 */ MCD_OPC_Decode, 230, 5, 3, // Opcode: EORV_VPZ_H /* 987 */ MCD_OPC_FilterValue, 26, 196, 79, 1, // Skip to: 86948 /* 992 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 995 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1009 /* 1000 */ MCD_OPC_CheckPredicate, 0, 183, 79, 1, // Skip to: 86948 /* 1005 */ MCD_OPC_Decode, 235, 1, 2, // Opcode: ANDV_VPZ_B /* 1009 */ MCD_OPC_FilterValue, 1, 174, 79, 1, // Skip to: 86948 /* 1014 */ MCD_OPC_CheckPredicate, 0, 169, 79, 1, // Skip to: 86948 /* 1019 */ MCD_OPC_Decode, 237, 1, 3, // Opcode: ANDV_VPZ_H /* 1023 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1059 /* 1028 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1031 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1045 /* 1036 */ MCD_OPC_CheckPredicate, 0, 147, 79, 1, // Skip to: 86948 /* 1041 */ MCD_OPC_Decode, 205, 19, 6, // Opcode: MLA_ZPmZZ_B /* 1045 */ MCD_OPC_FilterValue, 1, 138, 79, 1, // Skip to: 86948 /* 1050 */ MCD_OPC_CheckPredicate, 0, 133, 79, 1, // Skip to: 86948 /* 1055 */ MCD_OPC_Decode, 207, 19, 6, // Opcode: MLA_ZPmZZ_H /* 1059 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 1095 /* 1064 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1067 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1081 /* 1072 */ MCD_OPC_CheckPredicate, 0, 111, 79, 1, // Skip to: 86948 /* 1077 */ MCD_OPC_Decode, 219, 19, 6, // Opcode: MLS_ZPmZZ_B /* 1081 */ MCD_OPC_FilterValue, 1, 102, 79, 1, // Skip to: 86948 /* 1086 */ MCD_OPC_CheckPredicate, 0, 97, 79, 1, // Skip to: 86948 /* 1091 */ MCD_OPC_Decode, 221, 19, 6, // Opcode: MLS_ZPmZZ_H /* 1095 */ MCD_OPC_FilterValue, 4, 75, 2, 0, // Skip to: 1687 /* 1100 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 1103 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 1168 /* 1108 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1111 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1154 /* 1116 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 1119 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1140 /* 1124 */ MCD_OPC_CheckPredicate, 0, 59, 79, 1, // Skip to: 86948 /* 1129 */ MCD_OPC_CheckField, 8, 1, 1, 52, 79, 1, // Skip to: 86948 /* 1136 */ MCD_OPC_Decode, 142, 2, 7, // Opcode: ASR_ZPmI_B /* 1140 */ MCD_OPC_FilterValue, 1, 43, 79, 1, // Skip to: 86948 /* 1145 */ MCD_OPC_CheckPredicate, 0, 38, 79, 1, // Skip to: 86948 /* 1150 */ MCD_OPC_Decode, 144, 2, 8, // Opcode: ASR_ZPmI_H /* 1154 */ MCD_OPC_FilterValue, 1, 29, 79, 1, // Skip to: 86948 /* 1159 */ MCD_OPC_CheckPredicate, 0, 24, 79, 1, // Skip to: 86948 /* 1164 */ MCD_OPC_Decode, 145, 2, 9, // Opcode: ASR_ZPmI_S /* 1168 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 1233 /* 1173 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1176 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1219 /* 1181 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 1184 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1205 /* 1189 */ MCD_OPC_CheckPredicate, 0, 250, 78, 1, // Skip to: 86948 /* 1194 */ MCD_OPC_CheckField, 8, 1, 1, 243, 78, 1, // Skip to: 86948 /* 1201 */ MCD_OPC_Decode, 187, 19, 7, // Opcode: LSR_ZPmI_B /* 1205 */ MCD_OPC_FilterValue, 1, 234, 78, 1, // Skip to: 86948 /* 1210 */ MCD_OPC_CheckPredicate, 0, 229, 78, 1, // Skip to: 86948 /* 1215 */ MCD_OPC_Decode, 189, 19, 8, // Opcode: LSR_ZPmI_H /* 1219 */ MCD_OPC_FilterValue, 1, 220, 78, 1, // Skip to: 86948 /* 1224 */ MCD_OPC_CheckPredicate, 0, 215, 78, 1, // Skip to: 86948 /* 1229 */ MCD_OPC_Decode, 190, 19, 9, // Opcode: LSR_ZPmI_S /* 1233 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 1298 /* 1238 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1241 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1284 /* 1246 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 1249 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1270 /* 1254 */ MCD_OPC_CheckPredicate, 0, 185, 78, 1, // Skip to: 86948 /* 1259 */ MCD_OPC_CheckField, 8, 1, 1, 178, 78, 1, // Skip to: 86948 /* 1266 */ MCD_OPC_Decode, 163, 19, 10, // Opcode: LSL_ZPmI_B /* 1270 */ MCD_OPC_FilterValue, 1, 169, 78, 1, // Skip to: 86948 /* 1275 */ MCD_OPC_CheckPredicate, 0, 164, 78, 1, // Skip to: 86948 /* 1280 */ MCD_OPC_Decode, 165, 19, 11, // Opcode: LSL_ZPmI_H /* 1284 */ MCD_OPC_FilterValue, 1, 155, 78, 1, // Skip to: 86948 /* 1289 */ MCD_OPC_CheckPredicate, 0, 150, 78, 1, // Skip to: 86948 /* 1294 */ MCD_OPC_Decode, 166, 19, 12, // Opcode: LSL_ZPmI_S /* 1298 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 1363 /* 1303 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1306 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1349 /* 1311 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 1314 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1335 /* 1319 */ MCD_OPC_CheckPredicate, 0, 120, 78, 1, // Skip to: 86948 /* 1324 */ MCD_OPC_CheckField, 8, 1, 1, 113, 78, 1, // Skip to: 86948 /* 1331 */ MCD_OPC_Decode, 254, 1, 7, // Opcode: ASRD_ZPmI_B /* 1335 */ MCD_OPC_FilterValue, 1, 104, 78, 1, // Skip to: 86948 /* 1340 */ MCD_OPC_CheckPredicate, 0, 99, 78, 1, // Skip to: 86948 /* 1345 */ MCD_OPC_Decode, 128, 2, 8, // Opcode: ASRD_ZPmI_H /* 1349 */ MCD_OPC_FilterValue, 1, 90, 78, 1, // Skip to: 86948 /* 1354 */ MCD_OPC_CheckPredicate, 0, 85, 78, 1, // Skip to: 86948 /* 1359 */ MCD_OPC_Decode, 129, 2, 9, // Opcode: ASRD_ZPmI_S /* 1363 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1399 /* 1368 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1385 /* 1376 */ MCD_OPC_CheckPredicate, 0, 63, 78, 1, // Skip to: 86948 /* 1381 */ MCD_OPC_Decode, 146, 2, 0, // Opcode: ASR_ZPmZ_B /* 1385 */ MCD_OPC_FilterValue, 1, 54, 78, 1, // Skip to: 86948 /* 1390 */ MCD_OPC_CheckPredicate, 0, 49, 78, 1, // Skip to: 86948 /* 1395 */ MCD_OPC_Decode, 148, 2, 0, // Opcode: ASR_ZPmZ_H /* 1399 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1435 /* 1404 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1421 /* 1412 */ MCD_OPC_CheckPredicate, 0, 27, 78, 1, // Skip to: 86948 /* 1417 */ MCD_OPC_Decode, 191, 19, 0, // Opcode: LSR_ZPmZ_B /* 1421 */ MCD_OPC_FilterValue, 1, 18, 78, 1, // Skip to: 86948 /* 1426 */ MCD_OPC_CheckPredicate, 0, 13, 78, 1, // Skip to: 86948 /* 1431 */ MCD_OPC_Decode, 193, 19, 0, // Opcode: LSR_ZPmZ_H /* 1435 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1471 /* 1440 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1443 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1457 /* 1448 */ MCD_OPC_CheckPredicate, 0, 247, 77, 1, // Skip to: 86948 /* 1453 */ MCD_OPC_Decode, 167, 19, 0, // Opcode: LSL_ZPmZ_B /* 1457 */ MCD_OPC_FilterValue, 1, 238, 77, 1, // Skip to: 86948 /* 1462 */ MCD_OPC_CheckPredicate, 0, 233, 77, 1, // Skip to: 86948 /* 1467 */ MCD_OPC_Decode, 169, 19, 0, // Opcode: LSL_ZPmZ_H /* 1471 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 1507 /* 1476 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1479 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1493 /* 1484 */ MCD_OPC_CheckPredicate, 0, 211, 77, 1, // Skip to: 86948 /* 1489 */ MCD_OPC_Decode, 130, 2, 0, // Opcode: ASRR_ZPmZ_B /* 1493 */ MCD_OPC_FilterValue, 1, 202, 77, 1, // Skip to: 86948 /* 1498 */ MCD_OPC_CheckPredicate, 0, 197, 77, 1, // Skip to: 86948 /* 1503 */ MCD_OPC_Decode, 132, 2, 0, // Opcode: ASRR_ZPmZ_H /* 1507 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 1543 /* 1512 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1515 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1529 /* 1520 */ MCD_OPC_CheckPredicate, 0, 175, 77, 1, // Skip to: 86948 /* 1525 */ MCD_OPC_Decode, 175, 19, 0, // Opcode: LSRR_ZPmZ_B /* 1529 */ MCD_OPC_FilterValue, 1, 166, 77, 1, // Skip to: 86948 /* 1534 */ MCD_OPC_CheckPredicate, 0, 161, 77, 1, // Skip to: 86948 /* 1539 */ MCD_OPC_Decode, 177, 19, 0, // Opcode: LSRR_ZPmZ_H /* 1543 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 1579 /* 1548 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1551 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1565 /* 1556 */ MCD_OPC_CheckPredicate, 0, 139, 77, 1, // Skip to: 86948 /* 1561 */ MCD_OPC_Decode, 151, 19, 0, // Opcode: LSLR_ZPmZ_B /* 1565 */ MCD_OPC_FilterValue, 1, 130, 77, 1, // Skip to: 86948 /* 1570 */ MCD_OPC_CheckPredicate, 0, 125, 77, 1, // Skip to: 86948 /* 1575 */ MCD_OPC_Decode, 153, 19, 0, // Opcode: LSLR_ZPmZ_H /* 1579 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1615 /* 1584 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1587 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1601 /* 1592 */ MCD_OPC_CheckPredicate, 0, 103, 77, 1, // Skip to: 86948 /* 1597 */ MCD_OPC_Decode, 136, 2, 0, // Opcode: ASR_WIDE_ZPmZ_B /* 1601 */ MCD_OPC_FilterValue, 1, 94, 77, 1, // Skip to: 86948 /* 1606 */ MCD_OPC_CheckPredicate, 0, 89, 77, 1, // Skip to: 86948 /* 1611 */ MCD_OPC_Decode, 137, 2, 0, // Opcode: ASR_WIDE_ZPmZ_H /* 1615 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 1651 /* 1620 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1623 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1637 /* 1628 */ MCD_OPC_CheckPredicate, 0, 67, 77, 1, // Skip to: 86948 /* 1633 */ MCD_OPC_Decode, 181, 19, 0, // Opcode: LSR_WIDE_ZPmZ_B /* 1637 */ MCD_OPC_FilterValue, 1, 58, 77, 1, // Skip to: 86948 /* 1642 */ MCD_OPC_CheckPredicate, 0, 53, 77, 1, // Skip to: 86948 /* 1647 */ MCD_OPC_Decode, 182, 19, 0, // Opcode: LSR_WIDE_ZPmZ_H /* 1651 */ MCD_OPC_FilterValue, 27, 44, 77, 1, // Skip to: 86948 /* 1656 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1659 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1673 /* 1664 */ MCD_OPC_CheckPredicate, 0, 31, 77, 1, // Skip to: 86948 /* 1669 */ MCD_OPC_Decode, 157, 19, 0, // Opcode: LSL_WIDE_ZPmZ_B /* 1673 */ MCD_OPC_FilterValue, 1, 22, 77, 1, // Skip to: 86948 /* 1678 */ MCD_OPC_CheckPredicate, 0, 17, 77, 1, // Skip to: 86948 /* 1683 */ MCD_OPC_Decode, 158, 19, 0, // Opcode: LSL_WIDE_ZPmZ_H /* 1687 */ MCD_OPC_FilterValue, 5, 82, 1, 0, // Skip to: 2030 /* 1692 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 1695 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 1716 /* 1700 */ MCD_OPC_CheckPredicate, 0, 251, 76, 1, // Skip to: 86948 /* 1705 */ MCD_OPC_CheckField, 22, 1, 1, 244, 76, 1, // Skip to: 86948 /* 1712 */ MCD_OPC_Decode, 170, 30, 5, // Opcode: SXTB_ZPmZ_H /* 1716 */ MCD_OPC_FilterValue, 17, 16, 0, 0, // Skip to: 1737 /* 1721 */ MCD_OPC_CheckPredicate, 0, 230, 76, 1, // Skip to: 86948 /* 1726 */ MCD_OPC_CheckField, 22, 1, 1, 223, 76, 1, // Skip to: 86948 /* 1733 */ MCD_OPC_Decode, 183, 34, 5, // Opcode: UXTB_ZPmZ_H /* 1737 */ MCD_OPC_FilterValue, 22, 30, 0, 0, // Skip to: 1772 /* 1742 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1745 */ MCD_OPC_FilterValue, 0, 8, 0, 0, // Skip to: 1758 /* 1750 */ MCD_OPC_CheckPredicate, 0, 201, 76, 1, // Skip to: 86948 /* 1755 */ MCD_OPC_Decode, 126, 5, // Opcode: ABS_ZPmZ_B /* 1758 */ MCD_OPC_FilterValue, 1, 193, 76, 1, // Skip to: 86948 /* 1763 */ MCD_OPC_CheckPredicate, 0, 188, 76, 1, // Skip to: 86948 /* 1768 */ MCD_OPC_Decode, 128, 1, 5, // Opcode: ABS_ZPmZ_H /* 1772 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 1808 /* 1777 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1780 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1794 /* 1785 */ MCD_OPC_CheckPredicate, 0, 166, 76, 1, // Skip to: 86948 /* 1790 */ MCD_OPC_Decode, 175, 20, 5, // Opcode: NEG_ZPmZ_B /* 1794 */ MCD_OPC_FilterValue, 1, 157, 76, 1, // Skip to: 86948 /* 1799 */ MCD_OPC_CheckPredicate, 0, 152, 76, 1, // Skip to: 86948 /* 1804 */ MCD_OPC_Decode, 177, 20, 5, // Opcode: NEG_ZPmZ_H /* 1808 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1844 /* 1813 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1816 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1830 /* 1821 */ MCD_OPC_CheckPredicate, 0, 130, 76, 1, // Skip to: 86948 /* 1826 */ MCD_OPC_Decode, 160, 3, 5, // Opcode: CLS_ZPmZ_B /* 1830 */ MCD_OPC_FilterValue, 1, 121, 76, 1, // Skip to: 86948 /* 1835 */ MCD_OPC_CheckPredicate, 0, 116, 76, 1, // Skip to: 86948 /* 1840 */ MCD_OPC_Decode, 162, 3, 5, // Opcode: CLS_ZPmZ_H /* 1844 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 1880 /* 1849 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1852 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1866 /* 1857 */ MCD_OPC_CheckPredicate, 0, 94, 76, 1, // Skip to: 86948 /* 1862 */ MCD_OPC_Decode, 172, 3, 5, // Opcode: CLZ_ZPmZ_B /* 1866 */ MCD_OPC_FilterValue, 1, 85, 76, 1, // Skip to: 86948 /* 1871 */ MCD_OPC_CheckPredicate, 0, 80, 76, 1, // Skip to: 86948 /* 1876 */ MCD_OPC_Decode, 174, 3, 5, // Opcode: CLZ_ZPmZ_H /* 1880 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 1916 /* 1885 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1888 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1902 /* 1893 */ MCD_OPC_CheckPredicate, 0, 58, 76, 1, // Skip to: 86948 /* 1898 */ MCD_OPC_Decode, 253, 4, 5, // Opcode: CNT_ZPmZ_B /* 1902 */ MCD_OPC_FilterValue, 1, 49, 76, 1, // Skip to: 86948 /* 1907 */ MCD_OPC_CheckPredicate, 0, 44, 76, 1, // Skip to: 86948 /* 1912 */ MCD_OPC_Decode, 255, 4, 5, // Opcode: CNT_ZPmZ_H /* 1916 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 1952 /* 1921 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1924 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1938 /* 1929 */ MCD_OPC_CheckPredicate, 0, 22, 76, 1, // Skip to: 86948 /* 1934 */ MCD_OPC_Decode, 241, 4, 5, // Opcode: CNOT_ZPmZ_B /* 1938 */ MCD_OPC_FilterValue, 1, 13, 76, 1, // Skip to: 86948 /* 1943 */ MCD_OPC_CheckPredicate, 0, 8, 76, 1, // Skip to: 86948 /* 1948 */ MCD_OPC_Decode, 243, 4, 5, // Opcode: CNOT_ZPmZ_H /* 1952 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 1973 /* 1957 */ MCD_OPC_CheckPredicate, 0, 250, 75, 1, // Skip to: 86948 /* 1962 */ MCD_OPC_CheckField, 22, 1, 1, 243, 75, 1, // Skip to: 86948 /* 1969 */ MCD_OPC_Decode, 143, 6, 5, // Opcode: FABS_ZPmZ_H /* 1973 */ MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 1994 /* 1978 */ MCD_OPC_CheckPredicate, 0, 229, 75, 1, // Skip to: 86948 /* 1983 */ MCD_OPC_CheckField, 22, 1, 1, 222, 75, 1, // Skip to: 86948 /* 1990 */ MCD_OPC_Decode, 168, 11, 5, // Opcode: FNEG_ZPmZ_H /* 1994 */ MCD_OPC_FilterValue, 30, 213, 75, 1, // Skip to: 86948 /* 1999 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2002 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2016 /* 2007 */ MCD_OPC_CheckPredicate, 0, 200, 75, 1, // Skip to: 86948 /* 2012 */ MCD_OPC_Decode, 189, 20, 5, // Opcode: NOT_ZPmZ_B /* 2016 */ MCD_OPC_FilterValue, 1, 191, 75, 1, // Skip to: 86948 /* 2021 */ MCD_OPC_CheckPredicate, 0, 186, 75, 1, // Skip to: 86948 /* 2026 */ MCD_OPC_Decode, 191, 20, 5, // Opcode: NOT_ZPmZ_H /* 2030 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2066 /* 2035 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2038 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2052 /* 2043 */ MCD_OPC_CheckPredicate, 0, 164, 75, 1, // Skip to: 86948 /* 2048 */ MCD_OPC_Decode, 201, 19, 13, // Opcode: MAD_ZPmZZ_B /* 2052 */ MCD_OPC_FilterValue, 1, 155, 75, 1, // Skip to: 86948 /* 2057 */ MCD_OPC_CheckPredicate, 0, 150, 75, 1, // Skip to: 86948 /* 2062 */ MCD_OPC_Decode, 203, 19, 13, // Opcode: MAD_ZPmZZ_H /* 2066 */ MCD_OPC_FilterValue, 7, 141, 75, 1, // Skip to: 86948 /* 2071 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2088 /* 2079 */ MCD_OPC_CheckPredicate, 0, 128, 75, 1, // Skip to: 86948 /* 2084 */ MCD_OPC_Decode, 140, 20, 13, // Opcode: MSB_ZPmZZ_B /* 2088 */ MCD_OPC_FilterValue, 1, 119, 75, 1, // Skip to: 86948 /* 2093 */ MCD_OPC_CheckPredicate, 0, 114, 75, 1, // Skip to: 86948 /* 2098 */ MCD_OPC_Decode, 142, 20, 13, // Opcode: MSB_ZPmZZ_H /* 2102 */ MCD_OPC_FilterValue, 1, 76, 8, 0, // Skip to: 4231 /* 2107 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 2110 */ MCD_OPC_FilterValue, 0, 211, 2, 0, // Skip to: 2838 /* 2115 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 2118 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 2154 /* 2123 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2126 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2140 /* 2131 */ MCD_OPC_CheckPredicate, 0, 76, 75, 1, // Skip to: 86948 /* 2136 */ MCD_OPC_Decode, 188, 1, 0, // Opcode: ADD_ZPmZ_S /* 2140 */ MCD_OPC_FilterValue, 1, 67, 75, 1, // Skip to: 86948 /* 2145 */ MCD_OPC_CheckPredicate, 0, 62, 75, 1, // Skip to: 86948 /* 2150 */ MCD_OPC_Decode, 186, 1, 0, // Opcode: ADD_ZPmZ_D /* 2154 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 2190 /* 2159 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2176 /* 2167 */ MCD_OPC_CheckPredicate, 0, 40, 75, 1, // Skip to: 86948 /* 2172 */ MCD_OPC_Decode, 250, 29, 0, // Opcode: SUB_ZPmZ_S /* 2176 */ MCD_OPC_FilterValue, 1, 31, 75, 1, // Skip to: 86948 /* 2181 */ MCD_OPC_CheckPredicate, 0, 26, 75, 1, // Skip to: 86948 /* 2186 */ MCD_OPC_Decode, 248, 29, 0, // Opcode: SUB_ZPmZ_D /* 2190 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 2226 /* 2195 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2198 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2212 /* 2203 */ MCD_OPC_CheckPredicate, 0, 4, 75, 1, // Skip to: 86948 /* 2208 */ MCD_OPC_Decode, 224, 29, 0, // Opcode: SUBR_ZPmZ_S /* 2212 */ MCD_OPC_FilterValue, 1, 251, 74, 1, // Skip to: 86948 /* 2217 */ MCD_OPC_CheckPredicate, 0, 246, 74, 1, // Skip to: 86948 /* 2222 */ MCD_OPC_Decode, 222, 29, 0, // Opcode: SUBR_ZPmZ_D /* 2226 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2262 /* 2231 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2234 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2248 /* 2239 */ MCD_OPC_CheckPredicate, 0, 224, 74, 1, // Skip to: 86948 /* 2244 */ MCD_OPC_Decode, 199, 23, 0, // Opcode: SMAX_ZPmZ_S /* 2248 */ MCD_OPC_FilterValue, 1, 215, 74, 1, // Skip to: 86948 /* 2253 */ MCD_OPC_CheckPredicate, 0, 210, 74, 1, // Skip to: 86948 /* 2258 */ MCD_OPC_Decode, 197, 23, 0, // Opcode: SMAX_ZPmZ_D /* 2262 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2298 /* 2267 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2270 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2284 /* 2275 */ MCD_OPC_CheckPredicate, 0, 188, 74, 1, // Skip to: 86948 /* 2280 */ MCD_OPC_Decode, 255, 31, 0, // Opcode: UMAX_ZPmZ_S /* 2284 */ MCD_OPC_FilterValue, 1, 179, 74, 1, // Skip to: 86948 /* 2289 */ MCD_OPC_CheckPredicate, 0, 174, 74, 1, // Skip to: 86948 /* 2294 */ MCD_OPC_Decode, 253, 31, 0, // Opcode: UMAX_ZPmZ_D /* 2298 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2334 /* 2303 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2306 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2320 /* 2311 */ MCD_OPC_CheckPredicate, 0, 152, 74, 1, // Skip to: 86948 /* 2316 */ MCD_OPC_Decode, 229, 23, 0, // Opcode: SMIN_ZPmZ_S /* 2320 */ MCD_OPC_FilterValue, 1, 143, 74, 1, // Skip to: 86948 /* 2325 */ MCD_OPC_CheckPredicate, 0, 138, 74, 1, // Skip to: 86948 /* 2330 */ MCD_OPC_Decode, 227, 23, 0, // Opcode: SMIN_ZPmZ_D /* 2334 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2370 /* 2339 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2342 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2356 /* 2347 */ MCD_OPC_CheckPredicate, 0, 116, 74, 1, // Skip to: 86948 /* 2352 */ MCD_OPC_Decode, 156, 32, 0, // Opcode: UMIN_ZPmZ_S /* 2356 */ MCD_OPC_FilterValue, 1, 107, 74, 1, // Skip to: 86948 /* 2361 */ MCD_OPC_CheckPredicate, 0, 102, 74, 1, // Skip to: 86948 /* 2366 */ MCD_OPC_Decode, 154, 32, 0, // Opcode: UMIN_ZPmZ_D /* 2370 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 2406 /* 2375 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2378 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2392 /* 2383 */ MCD_OPC_CheckPredicate, 0, 80, 74, 1, // Skip to: 86948 /* 2388 */ MCD_OPC_Decode, 139, 22, 0, // Opcode: SABD_ZPmZ_S /* 2392 */ MCD_OPC_FilterValue, 1, 71, 74, 1, // Skip to: 86948 /* 2397 */ MCD_OPC_CheckPredicate, 0, 66, 74, 1, // Skip to: 86948 /* 2402 */ MCD_OPC_Decode, 137, 22, 0, // Opcode: SABD_ZPmZ_D /* 2406 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 2442 /* 2411 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2428 /* 2419 */ MCD_OPC_CheckPredicate, 0, 44, 74, 1, // Skip to: 86948 /* 2424 */ MCD_OPC_Decode, 129, 31, 0, // Opcode: UABD_ZPmZ_S /* 2428 */ MCD_OPC_FilterValue, 1, 35, 74, 1, // Skip to: 86948 /* 2433 */ MCD_OPC_CheckPredicate, 0, 30, 74, 1, // Skip to: 86948 /* 2438 */ MCD_OPC_Decode, 255, 30, 0, // Opcode: UABD_ZPmZ_D /* 2442 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 2478 /* 2447 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2450 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2464 /* 2455 */ MCD_OPC_CheckPredicate, 0, 8, 74, 1, // Skip to: 86948 /* 2460 */ MCD_OPC_Decode, 156, 20, 0, // Opcode: MUL_ZPmZ_S /* 2464 */ MCD_OPC_FilterValue, 1, 255, 73, 1, // Skip to: 86948 /* 2469 */ MCD_OPC_CheckPredicate, 0, 250, 73, 1, // Skip to: 86948 /* 2474 */ MCD_OPC_Decode, 154, 20, 0, // Opcode: MUL_ZPmZ_D /* 2478 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 2514 /* 2483 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2486 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2500 /* 2491 */ MCD_OPC_CheckPredicate, 0, 228, 73, 1, // Skip to: 86948 /* 2496 */ MCD_OPC_Decode, 137, 24, 0, // Opcode: SMULH_ZPmZ_S /* 2500 */ MCD_OPC_FilterValue, 1, 219, 73, 1, // Skip to: 86948 /* 2505 */ MCD_OPC_CheckPredicate, 0, 214, 73, 1, // Skip to: 86948 /* 2510 */ MCD_OPC_Decode, 135, 24, 0, // Opcode: SMULH_ZPmZ_D /* 2514 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 2550 /* 2519 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2522 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2536 /* 2527 */ MCD_OPC_CheckPredicate, 0, 192, 73, 1, // Skip to: 86948 /* 2532 */ MCD_OPC_Decode, 191, 32, 0, // Opcode: UMULH_ZPmZ_S /* 2536 */ MCD_OPC_FilterValue, 1, 183, 73, 1, // Skip to: 86948 /* 2541 */ MCD_OPC_CheckPredicate, 0, 178, 73, 1, // Skip to: 86948 /* 2546 */ MCD_OPC_Decode, 189, 32, 0, // Opcode: UMULH_ZPmZ_D /* 2550 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2586 /* 2555 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2558 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2572 /* 2563 */ MCD_OPC_CheckPredicate, 0, 156, 73, 1, // Skip to: 86948 /* 2568 */ MCD_OPC_Decode, 224, 22, 0, // Opcode: SDIV_ZPmZ_S /* 2572 */ MCD_OPC_FilterValue, 1, 147, 73, 1, // Skip to: 86948 /* 2577 */ MCD_OPC_CheckPredicate, 0, 142, 73, 1, // Skip to: 86948 /* 2582 */ MCD_OPC_Decode, 223, 22, 0, // Opcode: SDIV_ZPmZ_D /* 2586 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 2622 /* 2591 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2594 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2608 /* 2599 */ MCD_OPC_CheckPredicate, 0, 120, 73, 1, // Skip to: 86948 /* 2604 */ MCD_OPC_Decode, 211, 31, 0, // Opcode: UDIV_ZPmZ_S /* 2608 */ MCD_OPC_FilterValue, 1, 111, 73, 1, // Skip to: 86948 /* 2613 */ MCD_OPC_CheckPredicate, 0, 106, 73, 1, // Skip to: 86948 /* 2618 */ MCD_OPC_Decode, 210, 31, 0, // Opcode: UDIV_ZPmZ_D /* 2622 */ MCD_OPC_FilterValue, 22, 31, 0, 0, // Skip to: 2658 /* 2627 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2630 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2644 /* 2635 */ MCD_OPC_CheckPredicate, 0, 84, 73, 1, // Skip to: 86948 /* 2640 */ MCD_OPC_Decode, 220, 22, 0, // Opcode: SDIVR_ZPmZ_S /* 2644 */ MCD_OPC_FilterValue, 1, 75, 73, 1, // Skip to: 86948 /* 2649 */ MCD_OPC_CheckPredicate, 0, 70, 73, 1, // Skip to: 86948 /* 2654 */ MCD_OPC_Decode, 219, 22, 0, // Opcode: SDIVR_ZPmZ_D /* 2658 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 2694 /* 2663 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2666 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2680 /* 2671 */ MCD_OPC_CheckPredicate, 0, 48, 73, 1, // Skip to: 86948 /* 2676 */ MCD_OPC_Decode, 207, 31, 0, // Opcode: UDIVR_ZPmZ_S /* 2680 */ MCD_OPC_FilterValue, 1, 39, 73, 1, // Skip to: 86948 /* 2685 */ MCD_OPC_CheckPredicate, 0, 34, 73, 1, // Skip to: 86948 /* 2690 */ MCD_OPC_Decode, 206, 31, 0, // Opcode: UDIVR_ZPmZ_D /* 2694 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 2730 /* 2699 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2702 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2716 /* 2707 */ MCD_OPC_CheckPredicate, 0, 12, 73, 1, // Skip to: 86948 /* 2712 */ MCD_OPC_Decode, 215, 20, 0, // Opcode: ORR_ZPmZ_S /* 2716 */ MCD_OPC_FilterValue, 1, 3, 73, 1, // Skip to: 86948 /* 2721 */ MCD_OPC_CheckPredicate, 0, 254, 72, 1, // Skip to: 86948 /* 2726 */ MCD_OPC_Decode, 213, 20, 0, // Opcode: ORR_ZPmZ_D /* 2730 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 2766 /* 2735 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2738 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2752 /* 2743 */ MCD_OPC_CheckPredicate, 0, 232, 72, 1, // Skip to: 86948 /* 2748 */ MCD_OPC_Decode, 243, 5, 0, // Opcode: EOR_ZPmZ_S /* 2752 */ MCD_OPC_FilterValue, 1, 223, 72, 1, // Skip to: 86948 /* 2757 */ MCD_OPC_CheckPredicate, 0, 218, 72, 1, // Skip to: 86948 /* 2762 */ MCD_OPC_Decode, 241, 5, 0, // Opcode: EOR_ZPmZ_D /* 2766 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 2802 /* 2771 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2774 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2788 /* 2779 */ MCD_OPC_CheckPredicate, 0, 196, 72, 1, // Skip to: 86948 /* 2784 */ MCD_OPC_Decode, 250, 1, 0, // Opcode: AND_ZPmZ_S /* 2788 */ MCD_OPC_FilterValue, 1, 187, 72, 1, // Skip to: 86948 /* 2793 */ MCD_OPC_CheckPredicate, 0, 182, 72, 1, // Skip to: 86948 /* 2798 */ MCD_OPC_Decode, 248, 1, 0, // Opcode: AND_ZPmZ_D /* 2802 */ MCD_OPC_FilterValue, 27, 173, 72, 1, // Skip to: 86948 /* 2807 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2810 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2824 /* 2815 */ MCD_OPC_CheckPredicate, 0, 160, 72, 1, // Skip to: 86948 /* 2820 */ MCD_OPC_Decode, 185, 2, 0, // Opcode: BIC_ZPmZ_S /* 2824 */ MCD_OPC_FilterValue, 1, 151, 72, 1, // Skip to: 86948 /* 2829 */ MCD_OPC_CheckPredicate, 0, 146, 72, 1, // Skip to: 86948 /* 2834 */ MCD_OPC_Decode, 183, 2, 0, // Opcode: BIC_ZPmZ_D /* 2838 */ MCD_OPC_FilterValue, 1, 128, 1, 0, // Skip to: 3227 /* 2843 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 2846 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2867 /* 2851 */ MCD_OPC_CheckPredicate, 0, 124, 72, 1, // Skip to: 86948 /* 2856 */ MCD_OPC_CheckField, 22, 1, 0, 117, 72, 1, // Skip to: 86948 /* 2863 */ MCD_OPC_Decode, 171, 22, 1, // Opcode: SADDV_VPZ_S /* 2867 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 2903 /* 2872 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2875 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2889 /* 2880 */ MCD_OPC_CheckPredicate, 0, 95, 72, 1, // Skip to: 86948 /* 2885 */ MCD_OPC_Decode, 162, 31, 1, // Opcode: UADDV_VPZ_S /* 2889 */ MCD_OPC_FilterValue, 1, 86, 72, 1, // Skip to: 86948 /* 2894 */ MCD_OPC_CheckPredicate, 0, 81, 72, 1, // Skip to: 86948 /* 2899 */ MCD_OPC_Decode, 160, 31, 1, // Opcode: UADDV_VPZ_D /* 2903 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2939 /* 2908 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2911 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2925 /* 2916 */ MCD_OPC_CheckPredicate, 0, 59, 72, 1, // Skip to: 86948 /* 2921 */ MCD_OPC_Decode, 186, 23, 14, // Opcode: SMAXV_VPZ_S /* 2925 */ MCD_OPC_FilterValue, 1, 50, 72, 1, // Skip to: 86948 /* 2930 */ MCD_OPC_CheckPredicate, 0, 45, 72, 1, // Skip to: 86948 /* 2935 */ MCD_OPC_Decode, 184, 23, 1, // Opcode: SMAXV_VPZ_D /* 2939 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2975 /* 2944 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2947 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2961 /* 2952 */ MCD_OPC_CheckPredicate, 0, 23, 72, 1, // Skip to: 86948 /* 2957 */ MCD_OPC_Decode, 242, 31, 14, // Opcode: UMAXV_VPZ_S /* 2961 */ MCD_OPC_FilterValue, 1, 14, 72, 1, // Skip to: 86948 /* 2966 */ MCD_OPC_CheckPredicate, 0, 9, 72, 1, // Skip to: 86948 /* 2971 */ MCD_OPC_Decode, 240, 31, 1, // Opcode: UMAXV_VPZ_D /* 2975 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 3011 /* 2980 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2983 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2997 /* 2988 */ MCD_OPC_CheckPredicate, 0, 243, 71, 1, // Skip to: 86948 /* 2993 */ MCD_OPC_Decode, 216, 23, 14, // Opcode: SMINV_VPZ_S /* 2997 */ MCD_OPC_FilterValue, 1, 234, 71, 1, // Skip to: 86948 /* 3002 */ MCD_OPC_CheckPredicate, 0, 229, 71, 1, // Skip to: 86948 /* 3007 */ MCD_OPC_Decode, 214, 23, 1, // Opcode: SMINV_VPZ_D /* 3011 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 3047 /* 3016 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3019 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3033 /* 3024 */ MCD_OPC_CheckPredicate, 0, 207, 71, 1, // Skip to: 86948 /* 3029 */ MCD_OPC_Decode, 143, 32, 14, // Opcode: UMINV_VPZ_S /* 3033 */ MCD_OPC_FilterValue, 1, 198, 71, 1, // Skip to: 86948 /* 3038 */ MCD_OPC_CheckPredicate, 0, 193, 71, 1, // Skip to: 86948 /* 3043 */ MCD_OPC_Decode, 141, 32, 1, // Opcode: UMINV_VPZ_D /* 3047 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3083 /* 3052 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3055 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3069 /* 3060 */ MCD_OPC_CheckPredicate, 0, 171, 71, 1, // Skip to: 86948 /* 3065 */ MCD_OPC_Decode, 254, 19, 4, // Opcode: MOVPRFX_ZPzZ_S /* 3069 */ MCD_OPC_FilterValue, 1, 162, 71, 1, // Skip to: 86948 /* 3074 */ MCD_OPC_CheckPredicate, 0, 157, 71, 1, // Skip to: 86948 /* 3079 */ MCD_OPC_Decode, 252, 19, 4, // Opcode: MOVPRFX_ZPzZ_D /* 3083 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3119 /* 3088 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3091 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3105 /* 3096 */ MCD_OPC_CheckPredicate, 0, 135, 71, 1, // Skip to: 86948 /* 3101 */ MCD_OPC_Decode, 250, 19, 5, // Opcode: MOVPRFX_ZPmZ_S /* 3105 */ MCD_OPC_FilterValue, 1, 126, 71, 1, // Skip to: 86948 /* 3110 */ MCD_OPC_CheckPredicate, 0, 121, 71, 1, // Skip to: 86948 /* 3115 */ MCD_OPC_Decode, 248, 19, 5, // Opcode: MOVPRFX_ZPmZ_D /* 3119 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 3155 /* 3124 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3127 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3141 /* 3132 */ MCD_OPC_CheckPredicate, 0, 99, 71, 1, // Skip to: 86948 /* 3137 */ MCD_OPC_Decode, 226, 20, 14, // Opcode: ORV_VPZ_S /* 3141 */ MCD_OPC_FilterValue, 1, 90, 71, 1, // Skip to: 86948 /* 3146 */ MCD_OPC_CheckPredicate, 0, 85, 71, 1, // Skip to: 86948 /* 3151 */ MCD_OPC_Decode, 224, 20, 1, // Opcode: ORV_VPZ_D /* 3155 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 3191 /* 3160 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3163 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3177 /* 3168 */ MCD_OPC_CheckPredicate, 0, 63, 71, 1, // Skip to: 86948 /* 3173 */ MCD_OPC_Decode, 231, 5, 14, // Opcode: EORV_VPZ_S /* 3177 */ MCD_OPC_FilterValue, 1, 54, 71, 1, // Skip to: 86948 /* 3182 */ MCD_OPC_CheckPredicate, 0, 49, 71, 1, // Skip to: 86948 /* 3187 */ MCD_OPC_Decode, 229, 5, 1, // Opcode: EORV_VPZ_D /* 3191 */ MCD_OPC_FilterValue, 26, 40, 71, 1, // Skip to: 86948 /* 3196 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3199 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3213 /* 3204 */ MCD_OPC_CheckPredicate, 0, 27, 71, 1, // Skip to: 86948 /* 3209 */ MCD_OPC_Decode, 238, 1, 14, // Opcode: ANDV_VPZ_S /* 3213 */ MCD_OPC_FilterValue, 1, 18, 71, 1, // Skip to: 86948 /* 3218 */ MCD_OPC_CheckPredicate, 0, 13, 71, 1, // Skip to: 86948 /* 3223 */ MCD_OPC_Decode, 236, 1, 1, // Opcode: ANDV_VPZ_D /* 3227 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 3263 /* 3232 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3235 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3249 /* 3240 */ MCD_OPC_CheckPredicate, 0, 247, 70, 1, // Skip to: 86948 /* 3245 */ MCD_OPC_Decode, 208, 19, 6, // Opcode: MLA_ZPmZZ_S /* 3249 */ MCD_OPC_FilterValue, 1, 238, 70, 1, // Skip to: 86948 /* 3254 */ MCD_OPC_CheckPredicate, 0, 233, 70, 1, // Skip to: 86948 /* 3259 */ MCD_OPC_Decode, 206, 19, 6, // Opcode: MLA_ZPmZZ_D /* 3263 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 3299 /* 3268 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3271 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3285 /* 3276 */ MCD_OPC_CheckPredicate, 0, 211, 70, 1, // Skip to: 86948 /* 3281 */ MCD_OPC_Decode, 222, 19, 6, // Opcode: MLS_ZPmZZ_S /* 3285 */ MCD_OPC_FilterValue, 1, 202, 70, 1, // Skip to: 86948 /* 3290 */ MCD_OPC_CheckPredicate, 0, 197, 70, 1, // Skip to: 86948 /* 3295 */ MCD_OPC_Decode, 220, 19, 6, // Opcode: MLS_ZPmZZ_D /* 3299 */ MCD_OPC_FilterValue, 4, 82, 1, 0, // Skip to: 3642 /* 3304 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 3307 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3321 /* 3312 */ MCD_OPC_CheckPredicate, 0, 175, 70, 1, // Skip to: 86948 /* 3317 */ MCD_OPC_Decode, 143, 2, 15, // Opcode: ASR_ZPmI_D /* 3321 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3335 /* 3326 */ MCD_OPC_CheckPredicate, 0, 161, 70, 1, // Skip to: 86948 /* 3331 */ MCD_OPC_Decode, 188, 19, 15, // Opcode: LSR_ZPmI_D /* 3335 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3349 /* 3340 */ MCD_OPC_CheckPredicate, 0, 147, 70, 1, // Skip to: 86948 /* 3345 */ MCD_OPC_Decode, 164, 19, 16, // Opcode: LSL_ZPmI_D /* 3349 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3363 /* 3354 */ MCD_OPC_CheckPredicate, 0, 133, 70, 1, // Skip to: 86948 /* 3359 */ MCD_OPC_Decode, 255, 1, 15, // Opcode: ASRD_ZPmI_D /* 3363 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3399 /* 3368 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3385 /* 3376 */ MCD_OPC_CheckPredicate, 0, 111, 70, 1, // Skip to: 86948 /* 3381 */ MCD_OPC_Decode, 149, 2, 0, // Opcode: ASR_ZPmZ_S /* 3385 */ MCD_OPC_FilterValue, 1, 102, 70, 1, // Skip to: 86948 /* 3390 */ MCD_OPC_CheckPredicate, 0, 97, 70, 1, // Skip to: 86948 /* 3395 */ MCD_OPC_Decode, 147, 2, 0, // Opcode: ASR_ZPmZ_D /* 3399 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3435 /* 3404 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3421 /* 3412 */ MCD_OPC_CheckPredicate, 0, 75, 70, 1, // Skip to: 86948 /* 3417 */ MCD_OPC_Decode, 194, 19, 0, // Opcode: LSR_ZPmZ_S /* 3421 */ MCD_OPC_FilterValue, 1, 66, 70, 1, // Skip to: 86948 /* 3426 */ MCD_OPC_CheckPredicate, 0, 61, 70, 1, // Skip to: 86948 /* 3431 */ MCD_OPC_Decode, 192, 19, 0, // Opcode: LSR_ZPmZ_D /* 3435 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 3471 /* 3440 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3443 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3457 /* 3448 */ MCD_OPC_CheckPredicate, 0, 39, 70, 1, // Skip to: 86948 /* 3453 */ MCD_OPC_Decode, 170, 19, 0, // Opcode: LSL_ZPmZ_S /* 3457 */ MCD_OPC_FilterValue, 1, 30, 70, 1, // Skip to: 86948 /* 3462 */ MCD_OPC_CheckPredicate, 0, 25, 70, 1, // Skip to: 86948 /* 3467 */ MCD_OPC_Decode, 168, 19, 0, // Opcode: LSL_ZPmZ_D /* 3471 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 3507 /* 3476 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3479 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3493 /* 3484 */ MCD_OPC_CheckPredicate, 0, 3, 70, 1, // Skip to: 86948 /* 3489 */ MCD_OPC_Decode, 133, 2, 0, // Opcode: ASRR_ZPmZ_S /* 3493 */ MCD_OPC_FilterValue, 1, 250, 69, 1, // Skip to: 86948 /* 3498 */ MCD_OPC_CheckPredicate, 0, 245, 69, 1, // Skip to: 86948 /* 3503 */ MCD_OPC_Decode, 131, 2, 0, // Opcode: ASRR_ZPmZ_D /* 3507 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3543 /* 3512 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3515 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3529 /* 3520 */ MCD_OPC_CheckPredicate, 0, 223, 69, 1, // Skip to: 86948 /* 3525 */ MCD_OPC_Decode, 178, 19, 0, // Opcode: LSRR_ZPmZ_S /* 3529 */ MCD_OPC_FilterValue, 1, 214, 69, 1, // Skip to: 86948 /* 3534 */ MCD_OPC_CheckPredicate, 0, 209, 69, 1, // Skip to: 86948 /* 3539 */ MCD_OPC_Decode, 176, 19, 0, // Opcode: LSRR_ZPmZ_D /* 3543 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 3579 /* 3548 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3551 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3565 /* 3556 */ MCD_OPC_CheckPredicate, 0, 187, 69, 1, // Skip to: 86948 /* 3561 */ MCD_OPC_Decode, 154, 19, 0, // Opcode: LSLR_ZPmZ_S /* 3565 */ MCD_OPC_FilterValue, 1, 178, 69, 1, // Skip to: 86948 /* 3570 */ MCD_OPC_CheckPredicate, 0, 173, 69, 1, // Skip to: 86948 /* 3575 */ MCD_OPC_Decode, 152, 19, 0, // Opcode: LSLR_ZPmZ_D /* 3579 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 3600 /* 3584 */ MCD_OPC_CheckPredicate, 0, 159, 69, 1, // Skip to: 86948 /* 3589 */ MCD_OPC_CheckField, 22, 1, 0, 152, 69, 1, // Skip to: 86948 /* 3596 */ MCD_OPC_Decode, 138, 2, 0, // Opcode: ASR_WIDE_ZPmZ_S /* 3600 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 3621 /* 3605 */ MCD_OPC_CheckPredicate, 0, 138, 69, 1, // Skip to: 86948 /* 3610 */ MCD_OPC_CheckField, 22, 1, 0, 131, 69, 1, // Skip to: 86948 /* 3617 */ MCD_OPC_Decode, 183, 19, 0, // Opcode: LSR_WIDE_ZPmZ_S /* 3621 */ MCD_OPC_FilterValue, 27, 122, 69, 1, // Skip to: 86948 /* 3626 */ MCD_OPC_CheckPredicate, 0, 117, 69, 1, // Skip to: 86948 /* 3631 */ MCD_OPC_CheckField, 22, 1, 0, 110, 69, 1, // Skip to: 86948 /* 3638 */ MCD_OPC_Decode, 159, 19, 0, // Opcode: LSL_WIDE_ZPmZ_S /* 3642 */ MCD_OPC_FilterValue, 5, 0, 2, 0, // Skip to: 4159 /* 3647 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 3650 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3686 /* 3655 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3658 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3672 /* 3663 */ MCD_OPC_CheckPredicate, 0, 80, 69, 1, // Skip to: 86948 /* 3668 */ MCD_OPC_Decode, 171, 30, 5, // Opcode: SXTB_ZPmZ_S /* 3672 */ MCD_OPC_FilterValue, 1, 71, 69, 1, // Skip to: 86948 /* 3677 */ MCD_OPC_CheckPredicate, 0, 66, 69, 1, // Skip to: 86948 /* 3682 */ MCD_OPC_Decode, 169, 30, 5, // Opcode: SXTB_ZPmZ_D /* 3686 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3722 /* 3691 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3694 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3708 /* 3699 */ MCD_OPC_CheckPredicate, 0, 44, 69, 1, // Skip to: 86948 /* 3704 */ MCD_OPC_Decode, 184, 34, 5, // Opcode: UXTB_ZPmZ_S /* 3708 */ MCD_OPC_FilterValue, 1, 35, 69, 1, // Skip to: 86948 /* 3713 */ MCD_OPC_CheckPredicate, 0, 30, 69, 1, // Skip to: 86948 /* 3718 */ MCD_OPC_Decode, 182, 34, 5, // Opcode: UXTB_ZPmZ_D /* 3722 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 3758 /* 3727 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3730 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3744 /* 3735 */ MCD_OPC_CheckPredicate, 0, 8, 69, 1, // Skip to: 86948 /* 3740 */ MCD_OPC_Decode, 173, 30, 5, // Opcode: SXTH_ZPmZ_S /* 3744 */ MCD_OPC_FilterValue, 1, 255, 68, 1, // Skip to: 86948 /* 3749 */ MCD_OPC_CheckPredicate, 0, 250, 68, 1, // Skip to: 86948 /* 3754 */ MCD_OPC_Decode, 172, 30, 5, // Opcode: SXTH_ZPmZ_D /* 3758 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 3794 /* 3763 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3766 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3780 /* 3771 */ MCD_OPC_CheckPredicate, 0, 228, 68, 1, // Skip to: 86948 /* 3776 */ MCD_OPC_Decode, 186, 34, 5, // Opcode: UXTH_ZPmZ_S /* 3780 */ MCD_OPC_FilterValue, 1, 219, 68, 1, // Skip to: 86948 /* 3785 */ MCD_OPC_CheckPredicate, 0, 214, 68, 1, // Skip to: 86948 /* 3790 */ MCD_OPC_Decode, 185, 34, 5, // Opcode: UXTH_ZPmZ_D /* 3794 */ MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 3815 /* 3799 */ MCD_OPC_CheckPredicate, 0, 200, 68, 1, // Skip to: 86948 /* 3804 */ MCD_OPC_CheckField, 22, 1, 1, 193, 68, 1, // Skip to: 86948 /* 3811 */ MCD_OPC_Decode, 174, 30, 5, // Opcode: SXTW_ZPmZ_D /* 3815 */ MCD_OPC_FilterValue, 21, 16, 0, 0, // Skip to: 3836 /* 3820 */ MCD_OPC_CheckPredicate, 0, 179, 68, 1, // Skip to: 86948 /* 3825 */ MCD_OPC_CheckField, 22, 1, 1, 172, 68, 1, // Skip to: 86948 /* 3832 */ MCD_OPC_Decode, 187, 34, 5, // Opcode: UXTW_ZPmZ_D /* 3836 */ MCD_OPC_FilterValue, 22, 30, 0, 0, // Skip to: 3871 /* 3841 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3844 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3858 /* 3849 */ MCD_OPC_CheckPredicate, 0, 150, 68, 1, // Skip to: 86948 /* 3854 */ MCD_OPC_Decode, 129, 1, 5, // Opcode: ABS_ZPmZ_S /* 3858 */ MCD_OPC_FilterValue, 1, 141, 68, 1, // Skip to: 86948 /* 3863 */ MCD_OPC_CheckPredicate, 0, 136, 68, 1, // Skip to: 86948 /* 3868 */ MCD_OPC_Decode, 127, 5, // Opcode: ABS_ZPmZ_D /* 3871 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 3907 /* 3876 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3879 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3893 /* 3884 */ MCD_OPC_CheckPredicate, 0, 115, 68, 1, // Skip to: 86948 /* 3889 */ MCD_OPC_Decode, 178, 20, 5, // Opcode: NEG_ZPmZ_S /* 3893 */ MCD_OPC_FilterValue, 1, 106, 68, 1, // Skip to: 86948 /* 3898 */ MCD_OPC_CheckPredicate, 0, 101, 68, 1, // Skip to: 86948 /* 3903 */ MCD_OPC_Decode, 176, 20, 5, // Opcode: NEG_ZPmZ_D /* 3907 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 3943 /* 3912 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3915 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3929 /* 3920 */ MCD_OPC_CheckPredicate, 0, 79, 68, 1, // Skip to: 86948 /* 3925 */ MCD_OPC_Decode, 163, 3, 5, // Opcode: CLS_ZPmZ_S /* 3929 */ MCD_OPC_FilterValue, 1, 70, 68, 1, // Skip to: 86948 /* 3934 */ MCD_OPC_CheckPredicate, 0, 65, 68, 1, // Skip to: 86948 /* 3939 */ MCD_OPC_Decode, 161, 3, 5, // Opcode: CLS_ZPmZ_D /* 3943 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 3979 /* 3948 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3951 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3965 /* 3956 */ MCD_OPC_CheckPredicate, 0, 43, 68, 1, // Skip to: 86948 /* 3961 */ MCD_OPC_Decode, 175, 3, 5, // Opcode: CLZ_ZPmZ_S /* 3965 */ MCD_OPC_FilterValue, 1, 34, 68, 1, // Skip to: 86948 /* 3970 */ MCD_OPC_CheckPredicate, 0, 29, 68, 1, // Skip to: 86948 /* 3975 */ MCD_OPC_Decode, 173, 3, 5, // Opcode: CLZ_ZPmZ_D /* 3979 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 4015 /* 3984 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3987 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4001 /* 3992 */ MCD_OPC_CheckPredicate, 0, 7, 68, 1, // Skip to: 86948 /* 3997 */ MCD_OPC_Decode, 128, 5, 5, // Opcode: CNT_ZPmZ_S /* 4001 */ MCD_OPC_FilterValue, 1, 254, 67, 1, // Skip to: 86948 /* 4006 */ MCD_OPC_CheckPredicate, 0, 249, 67, 1, // Skip to: 86948 /* 4011 */ MCD_OPC_Decode, 254, 4, 5, // Opcode: CNT_ZPmZ_D /* 4015 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 4051 /* 4020 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4023 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4037 /* 4028 */ MCD_OPC_CheckPredicate, 0, 227, 67, 1, // Skip to: 86948 /* 4033 */ MCD_OPC_Decode, 244, 4, 5, // Opcode: CNOT_ZPmZ_S /* 4037 */ MCD_OPC_FilterValue, 1, 218, 67, 1, // Skip to: 86948 /* 4042 */ MCD_OPC_CheckPredicate, 0, 213, 67, 1, // Skip to: 86948 /* 4047 */ MCD_OPC_Decode, 242, 4, 5, // Opcode: CNOT_ZPmZ_D /* 4051 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 4087 /* 4056 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4059 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4073 /* 4064 */ MCD_OPC_CheckPredicate, 0, 191, 67, 1, // Skip to: 86948 /* 4069 */ MCD_OPC_Decode, 144, 6, 5, // Opcode: FABS_ZPmZ_S /* 4073 */ MCD_OPC_FilterValue, 1, 182, 67, 1, // Skip to: 86948 /* 4078 */ MCD_OPC_CheckPredicate, 0, 177, 67, 1, // Skip to: 86948 /* 4083 */ MCD_OPC_Decode, 142, 6, 5, // Opcode: FABS_ZPmZ_D /* 4087 */ MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 4123 /* 4092 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4095 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109 /* 4100 */ MCD_OPC_CheckPredicate, 0, 155, 67, 1, // Skip to: 86948 /* 4105 */ MCD_OPC_Decode, 169, 11, 5, // Opcode: FNEG_ZPmZ_S /* 4109 */ MCD_OPC_FilterValue, 1, 146, 67, 1, // Skip to: 86948 /* 4114 */ MCD_OPC_CheckPredicate, 0, 141, 67, 1, // Skip to: 86948 /* 4119 */ MCD_OPC_Decode, 167, 11, 5, // Opcode: FNEG_ZPmZ_D /* 4123 */ MCD_OPC_FilterValue, 30, 132, 67, 1, // Skip to: 86948 /* 4128 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4131 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4145 /* 4136 */ MCD_OPC_CheckPredicate, 0, 119, 67, 1, // Skip to: 86948 /* 4141 */ MCD_OPC_Decode, 192, 20, 5, // Opcode: NOT_ZPmZ_S /* 4145 */ MCD_OPC_FilterValue, 1, 110, 67, 1, // Skip to: 86948 /* 4150 */ MCD_OPC_CheckPredicate, 0, 105, 67, 1, // Skip to: 86948 /* 4155 */ MCD_OPC_Decode, 190, 20, 5, // Opcode: NOT_ZPmZ_D /* 4159 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4195 /* 4164 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4167 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4181 /* 4172 */ MCD_OPC_CheckPredicate, 0, 83, 67, 1, // Skip to: 86948 /* 4177 */ MCD_OPC_Decode, 204, 19, 13, // Opcode: MAD_ZPmZZ_S /* 4181 */ MCD_OPC_FilterValue, 1, 74, 67, 1, // Skip to: 86948 /* 4186 */ MCD_OPC_CheckPredicate, 0, 69, 67, 1, // Skip to: 86948 /* 4191 */ MCD_OPC_Decode, 202, 19, 13, // Opcode: MAD_ZPmZZ_D /* 4195 */ MCD_OPC_FilterValue, 7, 60, 67, 1, // Skip to: 86948 /* 4200 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4203 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4217 /* 4208 */ MCD_OPC_CheckPredicate, 0, 47, 67, 1, // Skip to: 86948 /* 4213 */ MCD_OPC_Decode, 143, 20, 13, // Opcode: MSB_ZPmZZ_S /* 4217 */ MCD_OPC_FilterValue, 1, 38, 67, 1, // Skip to: 86948 /* 4222 */ MCD_OPC_CheckPredicate, 0, 33, 67, 1, // Skip to: 86948 /* 4227 */ MCD_OPC_Decode, 141, 20, 13, // Opcode: MSB_ZPmZZ_D /* 4231 */ MCD_OPC_FilterValue, 2, 161, 0, 0, // Skip to: 4397 /* 4236 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4239 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 4289 /* 4244 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4247 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4268 /* 4252 */ MCD_OPC_CheckPredicate, 0, 3, 67, 1, // Skip to: 86948 /* 4257 */ MCD_OPC_CheckField, 18, 2, 0, 252, 66, 1, // Skip to: 86948 /* 4264 */ MCD_OPC_Decode, 211, 20, 17, // Opcode: ORR_ZI /* 4268 */ MCD_OPC_FilterValue, 1, 243, 66, 1, // Skip to: 86948 /* 4273 */ MCD_OPC_CheckPredicate, 0, 238, 66, 1, // Skip to: 86948 /* 4278 */ MCD_OPC_CheckField, 18, 2, 0, 231, 66, 1, // Skip to: 86948 /* 4285 */ MCD_OPC_Decode, 239, 5, 17, // Opcode: EOR_ZI /* 4289 */ MCD_OPC_FilterValue, 1, 222, 66, 1, // Skip to: 86948 /* 4294 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 4297 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4333 /* 4302 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4305 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4319 /* 4310 */ MCD_OPC_CheckPredicate, 0, 201, 66, 1, // Skip to: 86948 /* 4315 */ MCD_OPC_Decode, 145, 5, 18, // Opcode: CPY_ZPzI_B /* 4319 */ MCD_OPC_FilterValue, 1, 192, 66, 1, // Skip to: 86948 /* 4324 */ MCD_OPC_CheckPredicate, 0, 187, 66, 1, // Skip to: 86948 /* 4329 */ MCD_OPC_Decode, 147, 5, 19, // Opcode: CPY_ZPzI_H /* 4333 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 4369 /* 4338 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4341 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4355 /* 4346 */ MCD_OPC_CheckPredicate, 0, 165, 66, 1, // Skip to: 86948 /* 4351 */ MCD_OPC_Decode, 133, 5, 20, // Opcode: CPY_ZPmI_B /* 4355 */ MCD_OPC_FilterValue, 1, 156, 66, 1, // Skip to: 86948 /* 4360 */ MCD_OPC_CheckPredicate, 0, 151, 66, 1, // Skip to: 86948 /* 4365 */ MCD_OPC_Decode, 135, 5, 21, // Opcode: CPY_ZPmI_H /* 4369 */ MCD_OPC_FilterValue, 3, 142, 66, 1, // Skip to: 86948 /* 4374 */ MCD_OPC_CheckPredicate, 0, 137, 66, 1, // Skip to: 86948 /* 4379 */ MCD_OPC_CheckField, 22, 1, 1, 130, 66, 1, // Skip to: 86948 /* 4386 */ MCD_OPC_CheckField, 13, 1, 0, 123, 66, 1, // Skip to: 86948 /* 4393 */ MCD_OPC_Decode, 212, 7, 22, // Opcode: FCPY_ZPmI_H /* 4397 */ MCD_OPC_FilterValue, 3, 114, 66, 1, // Skip to: 86948 /* 4402 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4405 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 4455 /* 4410 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4413 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4434 /* 4418 */ MCD_OPC_CheckPredicate, 0, 93, 66, 1, // Skip to: 86948 /* 4423 */ MCD_OPC_CheckField, 18, 2, 0, 86, 66, 1, // Skip to: 86948 /* 4430 */ MCD_OPC_Decode, 246, 1, 17, // Opcode: AND_ZI /* 4434 */ MCD_OPC_FilterValue, 1, 77, 66, 1, // Skip to: 86948 /* 4439 */ MCD_OPC_CheckPredicate, 0, 72, 66, 1, // Skip to: 86948 /* 4444 */ MCD_OPC_CheckField, 18, 2, 0, 65, 66, 1, // Skip to: 86948 /* 4451 */ MCD_OPC_Decode, 194, 5, 17, // Opcode: DUPM_ZI /* 4455 */ MCD_OPC_FilterValue, 1, 56, 66, 1, // Skip to: 86948 /* 4460 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 4463 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4499 /* 4468 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4471 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4485 /* 4476 */ MCD_OPC_CheckPredicate, 0, 35, 66, 1, // Skip to: 86948 /* 4481 */ MCD_OPC_Decode, 148, 5, 23, // Opcode: CPY_ZPzI_S /* 4485 */ MCD_OPC_FilterValue, 1, 26, 66, 1, // Skip to: 86948 /* 4490 */ MCD_OPC_CheckPredicate, 0, 21, 66, 1, // Skip to: 86948 /* 4495 */ MCD_OPC_Decode, 146, 5, 24, // Opcode: CPY_ZPzI_D /* 4499 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 4535 /* 4504 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4507 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4521 /* 4512 */ MCD_OPC_CheckPredicate, 0, 255, 65, 1, // Skip to: 86948 /* 4517 */ MCD_OPC_Decode, 136, 5, 25, // Opcode: CPY_ZPmI_S /* 4521 */ MCD_OPC_FilterValue, 1, 246, 65, 1, // Skip to: 86948 /* 4526 */ MCD_OPC_CheckPredicate, 0, 241, 65, 1, // Skip to: 86948 /* 4531 */ MCD_OPC_Decode, 134, 5, 26, // Opcode: CPY_ZPmI_D /* 4535 */ MCD_OPC_FilterValue, 3, 232, 65, 1, // Skip to: 86948 /* 4540 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4543 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4564 /* 4548 */ MCD_OPC_CheckPredicate, 0, 219, 65, 1, // Skip to: 86948 /* 4553 */ MCD_OPC_CheckField, 13, 1, 0, 212, 65, 1, // Skip to: 86948 /* 4560 */ MCD_OPC_Decode, 213, 7, 22, // Opcode: FCPY_ZPmI_S /* 4564 */ MCD_OPC_FilterValue, 1, 203, 65, 1, // Skip to: 86948 /* 4569 */ MCD_OPC_CheckPredicate, 0, 198, 65, 1, // Skip to: 86948 /* 4574 */ MCD_OPC_CheckField, 13, 1, 0, 191, 65, 1, // Skip to: 86948 /* 4581 */ MCD_OPC_Decode, 211, 7, 22, // Opcode: FCPY_ZPmI_D /* 4585 */ MCD_OPC_FilterValue, 1, 182, 65, 1, // Skip to: 86948 /* 4590 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 4593 */ MCD_OPC_FilterValue, 0, 105, 4, 0, // Skip to: 5727 /* 4598 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 4601 */ MCD_OPC_FilterValue, 0, 129, 1, 0, // Skip to: 4991 /* 4606 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 4609 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 4701 /* 4614 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 4617 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4631 /* 4622 */ MCD_OPC_CheckPredicate, 0, 145, 65, 1, // Skip to: 86948 /* 4627 */ MCD_OPC_Decode, 189, 1, 27, // Opcode: ADD_ZZZ_B /* 4631 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4645 /* 4636 */ MCD_OPC_CheckPredicate, 0, 131, 65, 1, // Skip to: 86948 /* 4641 */ MCD_OPC_Decode, 251, 29, 27, // Opcode: SUB_ZZZ_B /* 4645 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4659 /* 4650 */ MCD_OPC_CheckPredicate, 0, 117, 65, 1, // Skip to: 86948 /* 4655 */ MCD_OPC_Decode, 168, 24, 27, // Opcode: SQADD_ZZZ_B /* 4659 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4673 /* 4664 */ MCD_OPC_CheckPredicate, 0, 103, 65, 1, // Skip to: 86948 /* 4669 */ MCD_OPC_Decode, 207, 32, 27, // Opcode: UQADD_ZZZ_B /* 4673 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4687 /* 4678 */ MCD_OPC_CheckPredicate, 0, 89, 65, 1, // Skip to: 86948 /* 4683 */ MCD_OPC_Decode, 150, 26, 27, // Opcode: SQSUB_ZZZ_B /* 4687 */ MCD_OPC_FilterValue, 7, 80, 65, 1, // Skip to: 86948 /* 4692 */ MCD_OPC_CheckPredicate, 0, 75, 65, 1, // Skip to: 86948 /* 4697 */ MCD_OPC_Decode, 193, 33, 27, // Opcode: UQSUB_ZZZ_B /* 4701 */ MCD_OPC_FilterValue, 1, 87, 0, 0, // Skip to: 4793 /* 4706 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 4709 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4723 /* 4714 */ MCD_OPC_CheckPredicate, 0, 53, 65, 1, // Skip to: 86948 /* 4719 */ MCD_OPC_Decode, 191, 1, 27, // Opcode: ADD_ZZZ_H /* 4723 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4737 /* 4728 */ MCD_OPC_CheckPredicate, 0, 39, 65, 1, // Skip to: 86948 /* 4733 */ MCD_OPC_Decode, 253, 29, 27, // Opcode: SUB_ZZZ_H /* 4737 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4751 /* 4742 */ MCD_OPC_CheckPredicate, 0, 25, 65, 1, // Skip to: 86948 /* 4747 */ MCD_OPC_Decode, 170, 24, 27, // Opcode: SQADD_ZZZ_H /* 4751 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4765 /* 4756 */ MCD_OPC_CheckPredicate, 0, 11, 65, 1, // Skip to: 86948 /* 4761 */ MCD_OPC_Decode, 209, 32, 27, // Opcode: UQADD_ZZZ_H /* 4765 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4779 /* 4770 */ MCD_OPC_CheckPredicate, 0, 253, 64, 1, // Skip to: 86948 /* 4775 */ MCD_OPC_Decode, 152, 26, 27, // Opcode: SQSUB_ZZZ_H /* 4779 */ MCD_OPC_FilterValue, 7, 244, 64, 1, // Skip to: 86948 /* 4784 */ MCD_OPC_CheckPredicate, 0, 239, 64, 1, // Skip to: 86948 /* 4789 */ MCD_OPC_Decode, 195, 33, 27, // Opcode: UQSUB_ZZZ_H /* 4793 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 4885 /* 4798 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 4801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4815 /* 4806 */ MCD_OPC_CheckPredicate, 0, 217, 64, 1, // Skip to: 86948 /* 4811 */ MCD_OPC_Decode, 192, 1, 27, // Opcode: ADD_ZZZ_S /* 4815 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4829 /* 4820 */ MCD_OPC_CheckPredicate, 0, 203, 64, 1, // Skip to: 86948 /* 4825 */ MCD_OPC_Decode, 254, 29, 27, // Opcode: SUB_ZZZ_S /* 4829 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4843 /* 4834 */ MCD_OPC_CheckPredicate, 0, 189, 64, 1, // Skip to: 86948 /* 4839 */ MCD_OPC_Decode, 171, 24, 27, // Opcode: SQADD_ZZZ_S /* 4843 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4857 /* 4848 */ MCD_OPC_CheckPredicate, 0, 175, 64, 1, // Skip to: 86948 /* 4853 */ MCD_OPC_Decode, 210, 32, 27, // Opcode: UQADD_ZZZ_S /* 4857 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4871 /* 4862 */ MCD_OPC_CheckPredicate, 0, 161, 64, 1, // Skip to: 86948 /* 4867 */ MCD_OPC_Decode, 153, 26, 27, // Opcode: SQSUB_ZZZ_S /* 4871 */ MCD_OPC_FilterValue, 7, 152, 64, 1, // Skip to: 86948 /* 4876 */ MCD_OPC_CheckPredicate, 0, 147, 64, 1, // Skip to: 86948 /* 4881 */ MCD_OPC_Decode, 196, 33, 27, // Opcode: UQSUB_ZZZ_S /* 4885 */ MCD_OPC_FilterValue, 3, 87, 0, 0, // Skip to: 4977 /* 4890 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 4893 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4907 /* 4898 */ MCD_OPC_CheckPredicate, 0, 125, 64, 1, // Skip to: 86948 /* 4903 */ MCD_OPC_Decode, 190, 1, 27, // Opcode: ADD_ZZZ_D /* 4907 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4921 /* 4912 */ MCD_OPC_CheckPredicate, 0, 111, 64, 1, // Skip to: 86948 /* 4917 */ MCD_OPC_Decode, 252, 29, 27, // Opcode: SUB_ZZZ_D /* 4921 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4935 /* 4926 */ MCD_OPC_CheckPredicate, 0, 97, 64, 1, // Skip to: 86948 /* 4931 */ MCD_OPC_Decode, 169, 24, 27, // Opcode: SQADD_ZZZ_D /* 4935 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4949 /* 4940 */ MCD_OPC_CheckPredicate, 0, 83, 64, 1, // Skip to: 86948 /* 4945 */ MCD_OPC_Decode, 208, 32, 27, // Opcode: UQADD_ZZZ_D /* 4949 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4963 /* 4954 */ MCD_OPC_CheckPredicate, 0, 69, 64, 1, // Skip to: 86948 /* 4959 */ MCD_OPC_Decode, 151, 26, 27, // Opcode: SQSUB_ZZZ_D /* 4963 */ MCD_OPC_FilterValue, 7, 60, 64, 1, // Skip to: 86948 /* 4968 */ MCD_OPC_CheckPredicate, 0, 55, 64, 1, // Skip to: 86948 /* 4973 */ MCD_OPC_Decode, 194, 33, 27, // Opcode: UQSUB_ZZZ_D /* 4977 */ MCD_OPC_FilterValue, 4, 46, 64, 1, // Skip to: 86948 /* 4982 */ MCD_OPC_CheckPredicate, 0, 41, 64, 1, // Skip to: 86948 /* 4987 */ MCD_OPC_Decode, 252, 5, 28, // Opcode: EXT_ZZI /* 4991 */ MCD_OPC_FilterValue, 1, 32, 64, 1, // Skip to: 86948 /* 4996 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 4999 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 5143 /* 5004 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 5007 */ MCD_OPC_FilterValue, 0, 110, 0, 0, // Skip to: 5122 /* 5012 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 5015 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 5101 /* 5020 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 5023 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5080 /* 5028 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 5031 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 5059 /* 5036 */ MCD_OPC_CheckPredicate, 0, 243, 63, 1, // Skip to: 86948 /* 5041 */ MCD_OPC_CheckField, 24, 2, 1, 236, 63, 1, // Skip to: 86948 /* 5048 */ MCD_OPC_CheckField, 20, 1, 1, 229, 63, 1, // Skip to: 86948 /* 5055 */ MCD_OPC_Decode, 206, 5, 29, // Opcode: DUP_ZZI_Q /* 5059 */ MCD_OPC_FilterValue, 1, 220, 63, 1, // Skip to: 86948 /* 5064 */ MCD_OPC_CheckPredicate, 0, 215, 63, 1, // Skip to: 86948 /* 5069 */ MCD_OPC_CheckField, 24, 2, 1, 208, 63, 1, // Skip to: 86948 /* 5076 */ MCD_OPC_Decode, 204, 5, 30, // Opcode: DUP_ZZI_D /* 5080 */ MCD_OPC_FilterValue, 1, 199, 63, 1, // Skip to: 86948 /* 5085 */ MCD_OPC_CheckPredicate, 0, 194, 63, 1, // Skip to: 86948 /* 5090 */ MCD_OPC_CheckField, 24, 2, 1, 187, 63, 1, // Skip to: 86948 /* 5097 */ MCD_OPC_Decode, 207, 5, 31, // Opcode: DUP_ZZI_S /* 5101 */ MCD_OPC_FilterValue, 1, 178, 63, 1, // Skip to: 86948 /* 5106 */ MCD_OPC_CheckPredicate, 0, 173, 63, 1, // Skip to: 86948 /* 5111 */ MCD_OPC_CheckField, 24, 2, 1, 166, 63, 1, // Skip to: 86948 /* 5118 */ MCD_OPC_Decode, 205, 5, 32, // Opcode: DUP_ZZI_H /* 5122 */ MCD_OPC_FilterValue, 1, 157, 63, 1, // Skip to: 86948 /* 5127 */ MCD_OPC_CheckPredicate, 0, 152, 63, 1, // Skip to: 86948 /* 5132 */ MCD_OPC_CheckField, 24, 2, 1, 145, 63, 1, // Skip to: 86948 /* 5139 */ MCD_OPC_Decode, 203, 5, 33, // Opcode: DUP_ZZI_B /* 5143 */ MCD_OPC_FilterValue, 4, 115, 0, 0, // Skip to: 5263 /* 5148 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5165 /* 5156 */ MCD_OPC_CheckPredicate, 0, 123, 63, 1, // Skip to: 86948 /* 5161 */ MCD_OPC_Decode, 251, 1, 27, // Opcode: AND_ZZZ /* 5165 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5179 /* 5170 */ MCD_OPC_CheckPredicate, 0, 109, 63, 1, // Skip to: 86948 /* 5175 */ MCD_OPC_Decode, 216, 20, 27, // Opcode: ORR_ZZZ /* 5179 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5193 /* 5184 */ MCD_OPC_CheckPredicate, 0, 95, 63, 1, // Skip to: 86948 /* 5189 */ MCD_OPC_Decode, 244, 5, 27, // Opcode: EOR_ZZZ /* 5193 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 5207 /* 5198 */ MCD_OPC_CheckPredicate, 0, 81, 63, 1, // Skip to: 86948 /* 5203 */ MCD_OPC_Decode, 186, 2, 27, // Opcode: BIC_ZZZ /* 5207 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5221 /* 5212 */ MCD_OPC_CheckPredicate, 0, 67, 63, 1, // Skip to: 86948 /* 5217 */ MCD_OPC_Decode, 177, 30, 27, // Opcode: TBL_ZZZ_B /* 5221 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5235 /* 5226 */ MCD_OPC_CheckPredicate, 0, 53, 63, 1, // Skip to: 86948 /* 5231 */ MCD_OPC_Decode, 179, 30, 27, // Opcode: TBL_ZZZ_H /* 5235 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5249 /* 5240 */ MCD_OPC_CheckPredicate, 0, 39, 63, 1, // Skip to: 86948 /* 5245 */ MCD_OPC_Decode, 180, 30, 27, // Opcode: TBL_ZZZ_S /* 5249 */ MCD_OPC_FilterValue, 7, 30, 63, 1, // Skip to: 86948 /* 5254 */ MCD_OPC_CheckPredicate, 0, 25, 63, 1, // Skip to: 86948 /* 5259 */ MCD_OPC_Decode, 178, 30, 27, // Opcode: TBL_ZZZ_D /* 5263 */ MCD_OPC_FilterValue, 6, 16, 63, 1, // Skip to: 86948 /* 5268 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 5271 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 5335 /* 5276 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5279 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5293 /* 5284 */ MCD_OPC_CheckPredicate, 0, 251, 62, 1, // Skip to: 86948 /* 5289 */ MCD_OPC_Decode, 199, 5, 34, // Opcode: DUP_ZR_B /* 5293 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5307 /* 5298 */ MCD_OPC_CheckPredicate, 0, 237, 62, 1, // Skip to: 86948 /* 5303 */ MCD_OPC_Decode, 201, 5, 34, // Opcode: DUP_ZR_H /* 5307 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5321 /* 5312 */ MCD_OPC_CheckPredicate, 0, 223, 62, 1, // Skip to: 86948 /* 5317 */ MCD_OPC_Decode, 202, 5, 34, // Opcode: DUP_ZR_S /* 5321 */ MCD_OPC_FilterValue, 7, 214, 62, 1, // Skip to: 86948 /* 5326 */ MCD_OPC_CheckPredicate, 0, 209, 62, 1, // Skip to: 86948 /* 5331 */ MCD_OPC_Decode, 200, 5, 35, // Opcode: DUP_ZR_D /* 5335 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 5399 /* 5340 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5343 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5357 /* 5348 */ MCD_OPC_CheckPredicate, 0, 187, 62, 1, // Skip to: 86948 /* 5353 */ MCD_OPC_Decode, 146, 14, 36, // Opcode: INSR_ZR_B /* 5357 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5371 /* 5362 */ MCD_OPC_CheckPredicate, 0, 173, 62, 1, // Skip to: 86948 /* 5367 */ MCD_OPC_Decode, 148, 14, 36, // Opcode: INSR_ZR_H /* 5371 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5385 /* 5376 */ MCD_OPC_CheckPredicate, 0, 159, 62, 1, // Skip to: 86948 /* 5381 */ MCD_OPC_Decode, 149, 14, 36, // Opcode: INSR_ZR_S /* 5385 */ MCD_OPC_FilterValue, 7, 150, 62, 1, // Skip to: 86948 /* 5390 */ MCD_OPC_CheckPredicate, 0, 145, 62, 1, // Skip to: 86948 /* 5395 */ MCD_OPC_Decode, 147, 14, 37, // Opcode: INSR_ZR_D /* 5399 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 5449 /* 5404 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5407 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5421 /* 5412 */ MCD_OPC_CheckPredicate, 0, 123, 62, 1, // Skip to: 86948 /* 5417 */ MCD_OPC_Decode, 139, 30, 38, // Opcode: SUNPKLO_ZZ_H /* 5421 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5435 /* 5426 */ MCD_OPC_CheckPredicate, 0, 109, 62, 1, // Skip to: 86948 /* 5431 */ MCD_OPC_Decode, 140, 30, 38, // Opcode: SUNPKLO_ZZ_S /* 5435 */ MCD_OPC_FilterValue, 7, 100, 62, 1, // Skip to: 86948 /* 5440 */ MCD_OPC_CheckPredicate, 0, 95, 62, 1, // Skip to: 86948 /* 5445 */ MCD_OPC_Decode, 138, 30, 38, // Opcode: SUNPKLO_ZZ_D /* 5449 */ MCD_OPC_FilterValue, 17, 45, 0, 0, // Skip to: 5499 /* 5454 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5457 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5471 /* 5462 */ MCD_OPC_CheckPredicate, 0, 73, 62, 1, // Skip to: 86948 /* 5467 */ MCD_OPC_Decode, 136, 30, 38, // Opcode: SUNPKHI_ZZ_H /* 5471 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5485 /* 5476 */ MCD_OPC_CheckPredicate, 0, 59, 62, 1, // Skip to: 86948 /* 5481 */ MCD_OPC_Decode, 137, 30, 38, // Opcode: SUNPKHI_ZZ_S /* 5485 */ MCD_OPC_FilterValue, 7, 50, 62, 1, // Skip to: 86948 /* 5490 */ MCD_OPC_CheckPredicate, 0, 45, 62, 1, // Skip to: 86948 /* 5495 */ MCD_OPC_Decode, 135, 30, 38, // Opcode: SUNPKHI_ZZ_D /* 5499 */ MCD_OPC_FilterValue, 18, 45, 0, 0, // Skip to: 5549 /* 5504 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5507 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5521 /* 5512 */ MCD_OPC_CheckPredicate, 0, 23, 62, 1, // Skip to: 86948 /* 5517 */ MCD_OPC_Decode, 180, 34, 38, // Opcode: UUNPKLO_ZZ_H /* 5521 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5535 /* 5526 */ MCD_OPC_CheckPredicate, 0, 9, 62, 1, // Skip to: 86948 /* 5531 */ MCD_OPC_Decode, 181, 34, 38, // Opcode: UUNPKLO_ZZ_S /* 5535 */ MCD_OPC_FilterValue, 7, 0, 62, 1, // Skip to: 86948 /* 5540 */ MCD_OPC_CheckPredicate, 0, 251, 61, 1, // Skip to: 86948 /* 5545 */ MCD_OPC_Decode, 179, 34, 38, // Opcode: UUNPKLO_ZZ_D /* 5549 */ MCD_OPC_FilterValue, 19, 45, 0, 0, // Skip to: 5599 /* 5554 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5557 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5571 /* 5562 */ MCD_OPC_CheckPredicate, 0, 229, 61, 1, // Skip to: 86948 /* 5567 */ MCD_OPC_Decode, 177, 34, 38, // Opcode: UUNPKHI_ZZ_H /* 5571 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5585 /* 5576 */ MCD_OPC_CheckPredicate, 0, 215, 61, 1, // Skip to: 86948 /* 5581 */ MCD_OPC_Decode, 178, 34, 38, // Opcode: UUNPKHI_ZZ_S /* 5585 */ MCD_OPC_FilterValue, 7, 206, 61, 1, // Skip to: 86948 /* 5590 */ MCD_OPC_CheckPredicate, 0, 201, 61, 1, // Skip to: 86948 /* 5595 */ MCD_OPC_Decode, 176, 34, 38, // Opcode: UUNPKHI_ZZ_D /* 5599 */ MCD_OPC_FilterValue, 20, 59, 0, 0, // Skip to: 5663 /* 5604 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5607 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5621 /* 5612 */ MCD_OPC_CheckPredicate, 0, 179, 61, 1, // Skip to: 86948 /* 5617 */ MCD_OPC_Decode, 150, 14, 39, // Opcode: INSR_ZV_B /* 5621 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5635 /* 5626 */ MCD_OPC_CheckPredicate, 0, 165, 61, 1, // Skip to: 86948 /* 5631 */ MCD_OPC_Decode, 152, 14, 40, // Opcode: INSR_ZV_H /* 5635 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5649 /* 5640 */ MCD_OPC_CheckPredicate, 0, 151, 61, 1, // Skip to: 86948 /* 5645 */ MCD_OPC_Decode, 153, 14, 41, // Opcode: INSR_ZV_S /* 5649 */ MCD_OPC_FilterValue, 7, 142, 61, 1, // Skip to: 86948 /* 5654 */ MCD_OPC_CheckPredicate, 0, 137, 61, 1, // Skip to: 86948 /* 5659 */ MCD_OPC_Decode, 151, 14, 42, // Opcode: INSR_ZV_D /* 5663 */ MCD_OPC_FilterValue, 24, 128, 61, 1, // Skip to: 86948 /* 5668 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5671 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5685 /* 5676 */ MCD_OPC_CheckPredicate, 0, 115, 61, 1, // Skip to: 86948 /* 5681 */ MCD_OPC_Decode, 227, 21, 38, // Opcode: REV_ZZ_B /* 5685 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5699 /* 5690 */ MCD_OPC_CheckPredicate, 0, 101, 61, 1, // Skip to: 86948 /* 5695 */ MCD_OPC_Decode, 229, 21, 38, // Opcode: REV_ZZ_H /* 5699 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5713 /* 5704 */ MCD_OPC_CheckPredicate, 0, 87, 61, 1, // Skip to: 86948 /* 5709 */ MCD_OPC_Decode, 230, 21, 38, // Opcode: REV_ZZ_S /* 5713 */ MCD_OPC_FilterValue, 7, 78, 61, 1, // Skip to: 86948 /* 5718 */ MCD_OPC_CheckPredicate, 0, 73, 61, 1, // Skip to: 86948 /* 5723 */ MCD_OPC_Decode, 228, 21, 38, // Opcode: REV_ZZ_D /* 5727 */ MCD_OPC_FilterValue, 1, 229, 6, 0, // Skip to: 7497 /* 5732 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5735 */ MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 5829 /* 5740 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 5743 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5779 /* 5748 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 5751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5765 /* 5756 */ MCD_OPC_CheckPredicate, 0, 35, 61, 1, // Skip to: 86948 /* 5761 */ MCD_OPC_Decode, 130, 14, 43, // Opcode: INDEX_II_B /* 5765 */ MCD_OPC_FilterValue, 1, 26, 61, 1, // Skip to: 86948 /* 5770 */ MCD_OPC_CheckPredicate, 0, 21, 61, 1, // Skip to: 86948 /* 5775 */ MCD_OPC_Decode, 138, 14, 44, // Opcode: INDEX_RI_B /* 5779 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5815 /* 5784 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 5787 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5801 /* 5792 */ MCD_OPC_CheckPredicate, 0, 255, 60, 1, // Skip to: 86948 /* 5797 */ MCD_OPC_Decode, 134, 14, 45, // Opcode: INDEX_IR_B /* 5801 */ MCD_OPC_FilterValue, 1, 246, 60, 1, // Skip to: 86948 /* 5806 */ MCD_OPC_CheckPredicate, 0, 241, 60, 1, // Skip to: 86948 /* 5811 */ MCD_OPC_Decode, 142, 14, 46, // Opcode: INDEX_RR_B /* 5815 */ MCD_OPC_FilterValue, 2, 232, 60, 1, // Skip to: 86948 /* 5820 */ MCD_OPC_CheckPredicate, 0, 227, 60, 1, // Skip to: 86948 /* 5825 */ MCD_OPC_Decode, 166, 1, 47, // Opcode: ADDVL_XXI /* 5829 */ MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 5923 /* 5834 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 5837 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5873 /* 5842 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 5845 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5859 /* 5850 */ MCD_OPC_CheckPredicate, 0, 197, 60, 1, // Skip to: 86948 /* 5855 */ MCD_OPC_Decode, 132, 14, 43, // Opcode: INDEX_II_H /* 5859 */ MCD_OPC_FilterValue, 1, 188, 60, 1, // Skip to: 86948 /* 5864 */ MCD_OPC_CheckPredicate, 0, 183, 60, 1, // Skip to: 86948 /* 5869 */ MCD_OPC_Decode, 140, 14, 44, // Opcode: INDEX_RI_H /* 5873 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5909 /* 5878 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 5881 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5895 /* 5886 */ MCD_OPC_CheckPredicate, 0, 161, 60, 1, // Skip to: 86948 /* 5891 */ MCD_OPC_Decode, 136, 14, 45, // Opcode: INDEX_IR_H /* 5895 */ MCD_OPC_FilterValue, 1, 152, 60, 1, // Skip to: 86948 /* 5900 */ MCD_OPC_CheckPredicate, 0, 147, 60, 1, // Skip to: 86948 /* 5905 */ MCD_OPC_Decode, 144, 14, 46, // Opcode: INDEX_RR_H /* 5909 */ MCD_OPC_FilterValue, 2, 138, 60, 1, // Skip to: 86948 /* 5914 */ MCD_OPC_CheckPredicate, 0, 133, 60, 1, // Skip to: 86948 /* 5919 */ MCD_OPC_Decode, 148, 1, 47, // Opcode: ADDPL_XXI /* 5923 */ MCD_OPC_FilterValue, 2, 96, 0, 0, // Skip to: 6024 /* 5928 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 5931 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5967 /* 5936 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 5939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5953 /* 5944 */ MCD_OPC_CheckPredicate, 0, 103, 60, 1, // Skip to: 86948 /* 5949 */ MCD_OPC_Decode, 133, 14, 43, // Opcode: INDEX_II_S /* 5953 */ MCD_OPC_FilterValue, 1, 94, 60, 1, // Skip to: 86948 /* 5958 */ MCD_OPC_CheckPredicate, 0, 89, 60, 1, // Skip to: 86948 /* 5963 */ MCD_OPC_Decode, 141, 14, 44, // Opcode: INDEX_RI_S /* 5967 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 6003 /* 5972 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5989 /* 5980 */ MCD_OPC_CheckPredicate, 0, 67, 60, 1, // Skip to: 86948 /* 5985 */ MCD_OPC_Decode, 137, 14, 45, // Opcode: INDEX_IR_S /* 5989 */ MCD_OPC_FilterValue, 1, 58, 60, 1, // Skip to: 86948 /* 5994 */ MCD_OPC_CheckPredicate, 0, 53, 60, 1, // Skip to: 86948 /* 5999 */ MCD_OPC_Decode, 145, 14, 46, // Opcode: INDEX_RR_S /* 6003 */ MCD_OPC_FilterValue, 2, 44, 60, 1, // Skip to: 86948 /* 6008 */ MCD_OPC_CheckPredicate, 0, 39, 60, 1, // Skip to: 86948 /* 6013 */ MCD_OPC_CheckField, 16, 5, 31, 32, 60, 1, // Skip to: 86948 /* 6020 */ MCD_OPC_Decode, 195, 21, 48, // Opcode: RDVLI_XI /* 6024 */ MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 6088 /* 6029 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 6032 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6046 /* 6037 */ MCD_OPC_CheckPredicate, 0, 10, 60, 1, // Skip to: 86948 /* 6042 */ MCD_OPC_Decode, 131, 14, 43, // Opcode: INDEX_II_D /* 6046 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6060 /* 6051 */ MCD_OPC_CheckPredicate, 0, 252, 59, 1, // Skip to: 86948 /* 6056 */ MCD_OPC_Decode, 139, 14, 49, // Opcode: INDEX_RI_D /* 6060 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6074 /* 6065 */ MCD_OPC_CheckPredicate, 0, 238, 59, 1, // Skip to: 86948 /* 6070 */ MCD_OPC_Decode, 135, 14, 50, // Opcode: INDEX_IR_D /* 6074 */ MCD_OPC_FilterValue, 3, 229, 59, 1, // Skip to: 86948 /* 6079 */ MCD_OPC_CheckPredicate, 0, 224, 59, 1, // Skip to: 86948 /* 6084 */ MCD_OPC_Decode, 143, 14, 51, // Opcode: INDEX_RR_D /* 6088 */ MCD_OPC_FilterValue, 4, 134, 1, 0, // Skip to: 6483 /* 6093 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 6096 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 6224 /* 6101 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6104 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6132 /* 6109 */ MCD_OPC_CheckPredicate, 0, 194, 59, 1, // Skip to: 86948 /* 6114 */ MCD_OPC_CheckField, 9, 1, 0, 187, 59, 1, // Skip to: 86948 /* 6121 */ MCD_OPC_CheckField, 4, 1, 0, 180, 59, 1, // Skip to: 86948 /* 6128 */ MCD_OPC_Decode, 133, 35, 52, // Opcode: ZIP1_PPP_B /* 6132 */ MCD_OPC_FilterValue, 1, 171, 59, 1, // Skip to: 86948 /* 6137 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 6140 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6168 /* 6145 */ MCD_OPC_CheckPredicate, 0, 158, 59, 1, // Skip to: 86948 /* 6150 */ MCD_OPC_CheckField, 9, 1, 0, 151, 59, 1, // Skip to: 86948 /* 6157 */ MCD_OPC_CheckField, 4, 1, 0, 144, 59, 1, // Skip to: 86948 /* 6164 */ MCD_OPC_Decode, 176, 21, 53, // Opcode: PUNPKLO_PP /* 6168 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 6196 /* 6173 */ MCD_OPC_CheckPredicate, 0, 130, 59, 1, // Skip to: 86948 /* 6178 */ MCD_OPC_CheckField, 9, 1, 0, 123, 59, 1, // Skip to: 86948 /* 6185 */ MCD_OPC_CheckField, 4, 1, 0, 116, 59, 1, // Skip to: 86948 /* 6192 */ MCD_OPC_Decode, 175, 21, 53, // Opcode: PUNPKHI_PP /* 6196 */ MCD_OPC_FilterValue, 4, 107, 59, 1, // Skip to: 86948 /* 6201 */ MCD_OPC_CheckPredicate, 0, 102, 59, 1, // Skip to: 86948 /* 6206 */ MCD_OPC_CheckField, 9, 1, 0, 95, 59, 1, // Skip to: 86948 /* 6213 */ MCD_OPC_CheckField, 4, 1, 0, 88, 59, 1, // Skip to: 86948 /* 6220 */ MCD_OPC_Decode, 223, 21, 53, // Opcode: REV_PP_B /* 6224 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6259 /* 6229 */ MCD_OPC_CheckPredicate, 0, 74, 59, 1, // Skip to: 86948 /* 6234 */ MCD_OPC_CheckField, 20, 1, 0, 67, 59, 1, // Skip to: 86948 /* 6241 */ MCD_OPC_CheckField, 9, 1, 0, 60, 59, 1, // Skip to: 86948 /* 6248 */ MCD_OPC_CheckField, 4, 1, 0, 53, 59, 1, // Skip to: 86948 /* 6255 */ MCD_OPC_Decode, 148, 35, 52, // Opcode: ZIP2_PPP_B /* 6259 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6294 /* 6264 */ MCD_OPC_CheckPredicate, 0, 39, 59, 1, // Skip to: 86948 /* 6269 */ MCD_OPC_CheckField, 20, 1, 0, 32, 59, 1, // Skip to: 86948 /* 6276 */ MCD_OPC_CheckField, 9, 1, 0, 25, 59, 1, // Skip to: 86948 /* 6283 */ MCD_OPC_CheckField, 4, 1, 0, 18, 59, 1, // Skip to: 86948 /* 6290 */ MCD_OPC_Decode, 188, 34, 52, // Opcode: UZP1_PPP_B /* 6294 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 6329 /* 6299 */ MCD_OPC_CheckPredicate, 0, 4, 59, 1, // Skip to: 86948 /* 6304 */ MCD_OPC_CheckField, 20, 1, 0, 253, 58, 1, // Skip to: 86948 /* 6311 */ MCD_OPC_CheckField, 9, 1, 0, 246, 58, 1, // Skip to: 86948 /* 6318 */ MCD_OPC_CheckField, 4, 1, 0, 239, 58, 1, // Skip to: 86948 /* 6325 */ MCD_OPC_Decode, 203, 34, 52, // Opcode: UZP2_PPP_B /* 6329 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 6364 /* 6334 */ MCD_OPC_CheckPredicate, 0, 225, 58, 1, // Skip to: 86948 /* 6339 */ MCD_OPC_CheckField, 20, 1, 0, 218, 58, 1, // Skip to: 86948 /* 6346 */ MCD_OPC_CheckField, 9, 1, 0, 211, 58, 1, // Skip to: 86948 /* 6353 */ MCD_OPC_CheckField, 4, 1, 0, 204, 58, 1, // Skip to: 86948 /* 6360 */ MCD_OPC_Decode, 205, 30, 52, // Opcode: TRN1_PPP_B /* 6364 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 6399 /* 6369 */ MCD_OPC_CheckPredicate, 0, 190, 58, 1, // Skip to: 86948 /* 6374 */ MCD_OPC_CheckField, 20, 1, 0, 183, 58, 1, // Skip to: 86948 /* 6381 */ MCD_OPC_CheckField, 9, 1, 0, 176, 58, 1, // Skip to: 86948 /* 6388 */ MCD_OPC_CheckField, 4, 1, 0, 169, 58, 1, // Skip to: 86948 /* 6395 */ MCD_OPC_Decode, 220, 30, 52, // Opcode: TRN2_PPP_B /* 6399 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6413 /* 6404 */ MCD_OPC_CheckPredicate, 0, 155, 58, 1, // Skip to: 86948 /* 6409 */ MCD_OPC_Decode, 137, 35, 27, // Opcode: ZIP1_ZZZ_B /* 6413 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6427 /* 6418 */ MCD_OPC_CheckPredicate, 0, 141, 58, 1, // Skip to: 86948 /* 6423 */ MCD_OPC_Decode, 152, 35, 27, // Opcode: ZIP2_ZZZ_B /* 6427 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 6441 /* 6432 */ MCD_OPC_CheckPredicate, 0, 127, 58, 1, // Skip to: 86948 /* 6437 */ MCD_OPC_Decode, 192, 34, 27, // Opcode: UZP1_ZZZ_B /* 6441 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6455 /* 6446 */ MCD_OPC_CheckPredicate, 0, 113, 58, 1, // Skip to: 86948 /* 6451 */ MCD_OPC_Decode, 207, 34, 27, // Opcode: UZP2_ZZZ_B /* 6455 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 6469 /* 6460 */ MCD_OPC_CheckPredicate, 0, 99, 58, 1, // Skip to: 86948 /* 6465 */ MCD_OPC_Decode, 209, 30, 27, // Opcode: TRN1_ZZZ_B /* 6469 */ MCD_OPC_FilterValue, 13, 90, 58, 1, // Skip to: 86948 /* 6474 */ MCD_OPC_CheckPredicate, 0, 85, 58, 1, // Skip to: 86948 /* 6479 */ MCD_OPC_Decode, 224, 30, 27, // Opcode: TRN2_ZZZ_B /* 6483 */ MCD_OPC_FilterValue, 5, 77, 1, 0, // Skip to: 6821 /* 6488 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 6491 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 6562 /* 6496 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6499 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6527 /* 6504 */ MCD_OPC_CheckPredicate, 0, 55, 58, 1, // Skip to: 86948 /* 6509 */ MCD_OPC_CheckField, 9, 1, 0, 48, 58, 1, // Skip to: 86948 /* 6516 */ MCD_OPC_CheckField, 4, 1, 0, 41, 58, 1, // Skip to: 86948 /* 6523 */ MCD_OPC_Decode, 135, 35, 52, // Opcode: ZIP1_PPP_H /* 6527 */ MCD_OPC_FilterValue, 1, 32, 58, 1, // Skip to: 86948 /* 6532 */ MCD_OPC_CheckPredicate, 0, 27, 58, 1, // Skip to: 86948 /* 6537 */ MCD_OPC_CheckField, 16, 4, 4, 20, 58, 1, // Skip to: 86948 /* 6544 */ MCD_OPC_CheckField, 9, 1, 0, 13, 58, 1, // Skip to: 86948 /* 6551 */ MCD_OPC_CheckField, 4, 1, 0, 6, 58, 1, // Skip to: 86948 /* 6558 */ MCD_OPC_Decode, 225, 21, 53, // Opcode: REV_PP_H /* 6562 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6597 /* 6567 */ MCD_OPC_CheckPredicate, 0, 248, 57, 1, // Skip to: 86948 /* 6572 */ MCD_OPC_CheckField, 20, 1, 0, 241, 57, 1, // Skip to: 86948 /* 6579 */ MCD_OPC_CheckField, 9, 1, 0, 234, 57, 1, // Skip to: 86948 /* 6586 */ MCD_OPC_CheckField, 4, 1, 0, 227, 57, 1, // Skip to: 86948 /* 6593 */ MCD_OPC_Decode, 150, 35, 52, // Opcode: ZIP2_PPP_H /* 6597 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6632 /* 6602 */ MCD_OPC_CheckPredicate, 0, 213, 57, 1, // Skip to: 86948 /* 6607 */ MCD_OPC_CheckField, 20, 1, 0, 206, 57, 1, // Skip to: 86948 /* 6614 */ MCD_OPC_CheckField, 9, 1, 0, 199, 57, 1, // Skip to: 86948 /* 6621 */ MCD_OPC_CheckField, 4, 1, 0, 192, 57, 1, // Skip to: 86948 /* 6628 */ MCD_OPC_Decode, 190, 34, 52, // Opcode: UZP1_PPP_H /* 6632 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 6667 /* 6637 */ MCD_OPC_CheckPredicate, 0, 178, 57, 1, // Skip to: 86948 /* 6642 */ MCD_OPC_CheckField, 20, 1, 0, 171, 57, 1, // Skip to: 86948 /* 6649 */ MCD_OPC_CheckField, 9, 1, 0, 164, 57, 1, // Skip to: 86948 /* 6656 */ MCD_OPC_CheckField, 4, 1, 0, 157, 57, 1, // Skip to: 86948 /* 6663 */ MCD_OPC_Decode, 205, 34, 52, // Opcode: UZP2_PPP_H /* 6667 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 6702 /* 6672 */ MCD_OPC_CheckPredicate, 0, 143, 57, 1, // Skip to: 86948 /* 6677 */ MCD_OPC_CheckField, 20, 1, 0, 136, 57, 1, // Skip to: 86948 /* 6684 */ MCD_OPC_CheckField, 9, 1, 0, 129, 57, 1, // Skip to: 86948 /* 6691 */ MCD_OPC_CheckField, 4, 1, 0, 122, 57, 1, // Skip to: 86948 /* 6698 */ MCD_OPC_Decode, 207, 30, 52, // Opcode: TRN1_PPP_H /* 6702 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 6737 /* 6707 */ MCD_OPC_CheckPredicate, 0, 108, 57, 1, // Skip to: 86948 /* 6712 */ MCD_OPC_CheckField, 20, 1, 0, 101, 57, 1, // Skip to: 86948 /* 6719 */ MCD_OPC_CheckField, 9, 1, 0, 94, 57, 1, // Skip to: 86948 /* 6726 */ MCD_OPC_CheckField, 4, 1, 0, 87, 57, 1, // Skip to: 86948 /* 6733 */ MCD_OPC_Decode, 222, 30, 52, // Opcode: TRN2_PPP_H /* 6737 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6751 /* 6742 */ MCD_OPC_CheckPredicate, 0, 73, 57, 1, // Skip to: 86948 /* 6747 */ MCD_OPC_Decode, 139, 35, 27, // Opcode: ZIP1_ZZZ_H /* 6751 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6765 /* 6756 */ MCD_OPC_CheckPredicate, 0, 59, 57, 1, // Skip to: 86948 /* 6761 */ MCD_OPC_Decode, 154, 35, 27, // Opcode: ZIP2_ZZZ_H /* 6765 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 6779 /* 6770 */ MCD_OPC_CheckPredicate, 0, 45, 57, 1, // Skip to: 86948 /* 6775 */ MCD_OPC_Decode, 194, 34, 27, // Opcode: UZP1_ZZZ_H /* 6779 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6793 /* 6784 */ MCD_OPC_CheckPredicate, 0, 31, 57, 1, // Skip to: 86948 /* 6789 */ MCD_OPC_Decode, 209, 34, 27, // Opcode: UZP2_ZZZ_H /* 6793 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 6807 /* 6798 */ MCD_OPC_CheckPredicate, 0, 17, 57, 1, // Skip to: 86948 /* 6803 */ MCD_OPC_Decode, 211, 30, 27, // Opcode: TRN1_ZZZ_H /* 6807 */ MCD_OPC_FilterValue, 13, 8, 57, 1, // Skip to: 86948 /* 6812 */ MCD_OPC_CheckPredicate, 0, 3, 57, 1, // Skip to: 86948 /* 6817 */ MCD_OPC_Decode, 226, 30, 27, // Opcode: TRN2_ZZZ_H /* 6821 */ MCD_OPC_FilterValue, 6, 77, 1, 0, // Skip to: 7159 /* 6826 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 6829 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 6900 /* 6834 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6837 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6865 /* 6842 */ MCD_OPC_CheckPredicate, 0, 229, 56, 1, // Skip to: 86948 /* 6847 */ MCD_OPC_CheckField, 9, 1, 0, 222, 56, 1, // Skip to: 86948 /* 6854 */ MCD_OPC_CheckField, 4, 1, 0, 215, 56, 1, // Skip to: 86948 /* 6861 */ MCD_OPC_Decode, 136, 35, 52, // Opcode: ZIP1_PPP_S /* 6865 */ MCD_OPC_FilterValue, 1, 206, 56, 1, // Skip to: 86948 /* 6870 */ MCD_OPC_CheckPredicate, 0, 201, 56, 1, // Skip to: 86948 /* 6875 */ MCD_OPC_CheckField, 16, 4, 4, 194, 56, 1, // Skip to: 86948 /* 6882 */ MCD_OPC_CheckField, 9, 1, 0, 187, 56, 1, // Skip to: 86948 /* 6889 */ MCD_OPC_CheckField, 4, 1, 0, 180, 56, 1, // Skip to: 86948 /* 6896 */ MCD_OPC_Decode, 226, 21, 53, // Opcode: REV_PP_S /* 6900 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6935 /* 6905 */ MCD_OPC_CheckPredicate, 0, 166, 56, 1, // Skip to: 86948 /* 6910 */ MCD_OPC_CheckField, 20, 1, 0, 159, 56, 1, // Skip to: 86948 /* 6917 */ MCD_OPC_CheckField, 9, 1, 0, 152, 56, 1, // Skip to: 86948 /* 6924 */ MCD_OPC_CheckField, 4, 1, 0, 145, 56, 1, // Skip to: 86948 /* 6931 */ MCD_OPC_Decode, 151, 35, 52, // Opcode: ZIP2_PPP_S /* 6935 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6970 /* 6940 */ MCD_OPC_CheckPredicate, 0, 131, 56, 1, // Skip to: 86948 /* 6945 */ MCD_OPC_CheckField, 20, 1, 0, 124, 56, 1, // Skip to: 86948 /* 6952 */ MCD_OPC_CheckField, 9, 1, 0, 117, 56, 1, // Skip to: 86948 /* 6959 */ MCD_OPC_CheckField, 4, 1, 0, 110, 56, 1, // Skip to: 86948 /* 6966 */ MCD_OPC_Decode, 191, 34, 52, // Opcode: UZP1_PPP_S /* 6970 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 7005 /* 6975 */ MCD_OPC_CheckPredicate, 0, 96, 56, 1, // Skip to: 86948 /* 6980 */ MCD_OPC_CheckField, 20, 1, 0, 89, 56, 1, // Skip to: 86948 /* 6987 */ MCD_OPC_CheckField, 9, 1, 0, 82, 56, 1, // Skip to: 86948 /* 6994 */ MCD_OPC_CheckField, 4, 1, 0, 75, 56, 1, // Skip to: 86948 /* 7001 */ MCD_OPC_Decode, 206, 34, 52, // Opcode: UZP2_PPP_S /* 7005 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 7040 /* 7010 */ MCD_OPC_CheckPredicate, 0, 61, 56, 1, // Skip to: 86948 /* 7015 */ MCD_OPC_CheckField, 20, 1, 0, 54, 56, 1, // Skip to: 86948 /* 7022 */ MCD_OPC_CheckField, 9, 1, 0, 47, 56, 1, // Skip to: 86948 /* 7029 */ MCD_OPC_CheckField, 4, 1, 0, 40, 56, 1, // Skip to: 86948 /* 7036 */ MCD_OPC_Decode, 208, 30, 52, // Opcode: TRN1_PPP_S /* 7040 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 7075 /* 7045 */ MCD_OPC_CheckPredicate, 0, 26, 56, 1, // Skip to: 86948 /* 7050 */ MCD_OPC_CheckField, 20, 1, 0, 19, 56, 1, // Skip to: 86948 /* 7057 */ MCD_OPC_CheckField, 9, 1, 0, 12, 56, 1, // Skip to: 86948 /* 7064 */ MCD_OPC_CheckField, 4, 1, 0, 5, 56, 1, // Skip to: 86948 /* 7071 */ MCD_OPC_Decode, 223, 30, 52, // Opcode: TRN2_PPP_S /* 7075 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7089 /* 7080 */ MCD_OPC_CheckPredicate, 0, 247, 55, 1, // Skip to: 86948 /* 7085 */ MCD_OPC_Decode, 140, 35, 27, // Opcode: ZIP1_ZZZ_S /* 7089 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 7103 /* 7094 */ MCD_OPC_CheckPredicate, 0, 233, 55, 1, // Skip to: 86948 /* 7099 */ MCD_OPC_Decode, 155, 35, 27, // Opcode: ZIP2_ZZZ_S /* 7103 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7117 /* 7108 */ MCD_OPC_CheckPredicate, 0, 219, 55, 1, // Skip to: 86948 /* 7113 */ MCD_OPC_Decode, 195, 34, 27, // Opcode: UZP1_ZZZ_S /* 7117 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 7131 /* 7122 */ MCD_OPC_CheckPredicate, 0, 205, 55, 1, // Skip to: 86948 /* 7127 */ MCD_OPC_Decode, 210, 34, 27, // Opcode: UZP2_ZZZ_S /* 7131 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 7145 /* 7136 */ MCD_OPC_CheckPredicate, 0, 191, 55, 1, // Skip to: 86948 /* 7141 */ MCD_OPC_Decode, 212, 30, 27, // Opcode: TRN1_ZZZ_S /* 7145 */ MCD_OPC_FilterValue, 13, 182, 55, 1, // Skip to: 86948 /* 7150 */ MCD_OPC_CheckPredicate, 0, 177, 55, 1, // Skip to: 86948 /* 7155 */ MCD_OPC_Decode, 227, 30, 27, // Opcode: TRN2_ZZZ_S /* 7159 */ MCD_OPC_FilterValue, 7, 168, 55, 1, // Skip to: 86948 /* 7164 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 7167 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 7238 /* 7172 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7175 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 7203 /* 7180 */ MCD_OPC_CheckPredicate, 0, 147, 55, 1, // Skip to: 86948 /* 7185 */ MCD_OPC_CheckField, 9, 1, 0, 140, 55, 1, // Skip to: 86948 /* 7192 */ MCD_OPC_CheckField, 4, 1, 0, 133, 55, 1, // Skip to: 86948 /* 7199 */ MCD_OPC_Decode, 134, 35, 52, // Opcode: ZIP1_PPP_D /* 7203 */ MCD_OPC_FilterValue, 1, 124, 55, 1, // Skip to: 86948 /* 7208 */ MCD_OPC_CheckPredicate, 0, 119, 55, 1, // Skip to: 86948 /* 7213 */ MCD_OPC_CheckField, 16, 4, 4, 112, 55, 1, // Skip to: 86948 /* 7220 */ MCD_OPC_CheckField, 9, 1, 0, 105, 55, 1, // Skip to: 86948 /* 7227 */ MCD_OPC_CheckField, 4, 1, 0, 98, 55, 1, // Skip to: 86948 /* 7234 */ MCD_OPC_Decode, 224, 21, 53, // Opcode: REV_PP_D /* 7238 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 7273 /* 7243 */ MCD_OPC_CheckPredicate, 0, 84, 55, 1, // Skip to: 86948 /* 7248 */ MCD_OPC_CheckField, 20, 1, 0, 77, 55, 1, // Skip to: 86948 /* 7255 */ MCD_OPC_CheckField, 9, 1, 0, 70, 55, 1, // Skip to: 86948 /* 7262 */ MCD_OPC_CheckField, 4, 1, 0, 63, 55, 1, // Skip to: 86948 /* 7269 */ MCD_OPC_Decode, 149, 35, 52, // Opcode: ZIP2_PPP_D /* 7273 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 7308 /* 7278 */ MCD_OPC_CheckPredicate, 0, 49, 55, 1, // Skip to: 86948 /* 7283 */ MCD_OPC_CheckField, 20, 1, 0, 42, 55, 1, // Skip to: 86948 /* 7290 */ MCD_OPC_CheckField, 9, 1, 0, 35, 55, 1, // Skip to: 86948 /* 7297 */ MCD_OPC_CheckField, 4, 1, 0, 28, 55, 1, // Skip to: 86948 /* 7304 */ MCD_OPC_Decode, 189, 34, 52, // Opcode: UZP1_PPP_D /* 7308 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 7343 /* 7313 */ MCD_OPC_CheckPredicate, 0, 14, 55, 1, // Skip to: 86948 /* 7318 */ MCD_OPC_CheckField, 20, 1, 0, 7, 55, 1, // Skip to: 86948 /* 7325 */ MCD_OPC_CheckField, 9, 1, 0, 0, 55, 1, // Skip to: 86948 /* 7332 */ MCD_OPC_CheckField, 4, 1, 0, 249, 54, 1, // Skip to: 86948 /* 7339 */ MCD_OPC_Decode, 204, 34, 52, // Opcode: UZP2_PPP_D /* 7343 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 7378 /* 7348 */ MCD_OPC_CheckPredicate, 0, 235, 54, 1, // Skip to: 86948 /* 7353 */ MCD_OPC_CheckField, 20, 1, 0, 228, 54, 1, // Skip to: 86948 /* 7360 */ MCD_OPC_CheckField, 9, 1, 0, 221, 54, 1, // Skip to: 86948 /* 7367 */ MCD_OPC_CheckField, 4, 1, 0, 214, 54, 1, // Skip to: 86948 /* 7374 */ MCD_OPC_Decode, 206, 30, 52, // Opcode: TRN1_PPP_D /* 7378 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 7413 /* 7383 */ MCD_OPC_CheckPredicate, 0, 200, 54, 1, // Skip to: 86948 /* 7388 */ MCD_OPC_CheckField, 20, 1, 0, 193, 54, 1, // Skip to: 86948 /* 7395 */ MCD_OPC_CheckField, 9, 1, 0, 186, 54, 1, // Skip to: 86948 /* 7402 */ MCD_OPC_CheckField, 4, 1, 0, 179, 54, 1, // Skip to: 86948 /* 7409 */ MCD_OPC_Decode, 221, 30, 52, // Opcode: TRN2_PPP_D /* 7413 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7427 /* 7418 */ MCD_OPC_CheckPredicate, 0, 165, 54, 1, // Skip to: 86948 /* 7423 */ MCD_OPC_Decode, 138, 35, 27, // Opcode: ZIP1_ZZZ_D /* 7427 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 7441 /* 7432 */ MCD_OPC_CheckPredicate, 0, 151, 54, 1, // Skip to: 86948 /* 7437 */ MCD_OPC_Decode, 153, 35, 27, // Opcode: ZIP2_ZZZ_D /* 7441 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7455 /* 7446 */ MCD_OPC_CheckPredicate, 0, 137, 54, 1, // Skip to: 86948 /* 7451 */ MCD_OPC_Decode, 193, 34, 27, // Opcode: UZP1_ZZZ_D /* 7455 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 7469 /* 7460 */ MCD_OPC_CheckPredicate, 0, 123, 54, 1, // Skip to: 86948 /* 7465 */ MCD_OPC_Decode, 208, 34, 27, // Opcode: UZP2_ZZZ_D /* 7469 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 7483 /* 7474 */ MCD_OPC_CheckPredicate, 0, 109, 54, 1, // Skip to: 86948 /* 7479 */ MCD_OPC_Decode, 210, 30, 27, // Opcode: TRN1_ZZZ_D /* 7483 */ MCD_OPC_FilterValue, 13, 100, 54, 1, // Skip to: 86948 /* 7488 */ MCD_OPC_CheckPredicate, 0, 95, 54, 1, // Skip to: 86948 /* 7493 */ MCD_OPC_Decode, 225, 30, 27, // Opcode: TRN2_ZZZ_D /* 7497 */ MCD_OPC_FilterValue, 2, 96, 9, 0, // Skip to: 9902 /* 7502 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 7505 */ MCD_OPC_FilterValue, 0, 15, 2, 0, // Skip to: 8037 /* 7510 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 7513 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7549 /* 7518 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7521 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7535 /* 7526 */ MCD_OPC_CheckPredicate, 0, 57, 54, 1, // Skip to: 86948 /* 7531 */ MCD_OPC_Decode, 139, 2, 27, // Opcode: ASR_WIDE_ZZZ_B /* 7535 */ MCD_OPC_FilterValue, 1, 48, 54, 1, // Skip to: 86948 /* 7540 */ MCD_OPC_CheckPredicate, 0, 43, 54, 1, // Skip to: 86948 /* 7545 */ MCD_OPC_Decode, 140, 2, 27, // Opcode: ASR_WIDE_ZZZ_H /* 7549 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7585 /* 7554 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7557 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7571 /* 7562 */ MCD_OPC_CheckPredicate, 0, 21, 54, 1, // Skip to: 86948 /* 7567 */ MCD_OPC_Decode, 184, 19, 27, // Opcode: LSR_WIDE_ZZZ_B /* 7571 */ MCD_OPC_FilterValue, 1, 12, 54, 1, // Skip to: 86948 /* 7576 */ MCD_OPC_CheckPredicate, 0, 7, 54, 1, // Skip to: 86948 /* 7581 */ MCD_OPC_Decode, 185, 19, 27, // Opcode: LSR_WIDE_ZZZ_H /* 7585 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 7621 /* 7590 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7593 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7607 /* 7598 */ MCD_OPC_CheckPredicate, 0, 241, 53, 1, // Skip to: 86948 /* 7603 */ MCD_OPC_Decode, 160, 19, 27, // Opcode: LSL_WIDE_ZZZ_B /* 7607 */ MCD_OPC_FilterValue, 1, 232, 53, 1, // Skip to: 86948 /* 7612 */ MCD_OPC_CheckPredicate, 0, 227, 53, 1, // Skip to: 86948 /* 7617 */ MCD_OPC_Decode, 161, 19, 27, // Opcode: LSL_WIDE_ZZZ_H /* 7621 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 7686 /* 7626 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7629 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7672 /* 7634 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7637 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7658 /* 7642 */ MCD_OPC_CheckPredicate, 0, 197, 53, 1, // Skip to: 86948 /* 7647 */ MCD_OPC_CheckField, 19, 1, 1, 190, 53, 1, // Skip to: 86948 /* 7654 */ MCD_OPC_Decode, 150, 2, 54, // Opcode: ASR_ZZI_B /* 7658 */ MCD_OPC_FilterValue, 1, 181, 53, 1, // Skip to: 86948 /* 7663 */ MCD_OPC_CheckPredicate, 0, 176, 53, 1, // Skip to: 86948 /* 7668 */ MCD_OPC_Decode, 152, 2, 55, // Opcode: ASR_ZZI_H /* 7672 */ MCD_OPC_FilterValue, 1, 167, 53, 1, // Skip to: 86948 /* 7677 */ MCD_OPC_CheckPredicate, 0, 162, 53, 1, // Skip to: 86948 /* 7682 */ MCD_OPC_Decode, 153, 2, 56, // Opcode: ASR_ZZI_S /* 7686 */ MCD_OPC_FilterValue, 5, 60, 0, 0, // Skip to: 7751 /* 7691 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7694 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7737 /* 7699 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7702 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7723 /* 7707 */ MCD_OPC_CheckPredicate, 0, 132, 53, 1, // Skip to: 86948 /* 7712 */ MCD_OPC_CheckField, 19, 1, 1, 125, 53, 1, // Skip to: 86948 /* 7719 */ MCD_OPC_Decode, 195, 19, 54, // Opcode: LSR_ZZI_B /* 7723 */ MCD_OPC_FilterValue, 1, 116, 53, 1, // Skip to: 86948 /* 7728 */ MCD_OPC_CheckPredicate, 0, 111, 53, 1, // Skip to: 86948 /* 7733 */ MCD_OPC_Decode, 197, 19, 55, // Opcode: LSR_ZZI_H /* 7737 */ MCD_OPC_FilterValue, 1, 102, 53, 1, // Skip to: 86948 /* 7742 */ MCD_OPC_CheckPredicate, 0, 97, 53, 1, // Skip to: 86948 /* 7747 */ MCD_OPC_Decode, 198, 19, 56, // Opcode: LSR_ZZI_S /* 7751 */ MCD_OPC_FilterValue, 7, 60, 0, 0, // Skip to: 7816 /* 7756 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7759 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7802 /* 7764 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7767 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7788 /* 7772 */ MCD_OPC_CheckPredicate, 0, 67, 53, 1, // Skip to: 86948 /* 7777 */ MCD_OPC_CheckField, 19, 1, 1, 60, 53, 1, // Skip to: 86948 /* 7784 */ MCD_OPC_Decode, 171, 19, 57, // Opcode: LSL_ZZI_B /* 7788 */ MCD_OPC_FilterValue, 1, 51, 53, 1, // Skip to: 86948 /* 7793 */ MCD_OPC_CheckPredicate, 0, 46, 53, 1, // Skip to: 86948 /* 7798 */ MCD_OPC_Decode, 173, 19, 58, // Opcode: LSL_ZZI_H /* 7802 */ MCD_OPC_FilterValue, 1, 37, 53, 1, // Skip to: 86948 /* 7807 */ MCD_OPC_CheckPredicate, 0, 32, 53, 1, // Skip to: 86948 /* 7812 */ MCD_OPC_Decode, 174, 19, 59, // Opcode: LSL_ZZI_S /* 7816 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 7852 /* 7821 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7824 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7838 /* 7829 */ MCD_OPC_CheckPredicate, 0, 10, 53, 1, // Skip to: 86948 /* 7834 */ MCD_OPC_Decode, 214, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_0 /* 7838 */ MCD_OPC_FilterValue, 1, 1, 53, 1, // Skip to: 86948 /* 7843 */ MCD_OPC_CheckPredicate, 0, 252, 52, 1, // Skip to: 86948 /* 7848 */ MCD_OPC_Decode, 218, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_0 /* 7852 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7888 /* 7857 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7860 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7874 /* 7865 */ MCD_OPC_CheckPredicate, 0, 230, 52, 1, // Skip to: 86948 /* 7870 */ MCD_OPC_Decode, 215, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_1 /* 7874 */ MCD_OPC_FilterValue, 1, 221, 52, 1, // Skip to: 86948 /* 7879 */ MCD_OPC_CheckPredicate, 0, 216, 52, 1, // Skip to: 86948 /* 7884 */ MCD_OPC_Decode, 219, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_1 /* 7888 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 7924 /* 7893 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7896 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7910 /* 7901 */ MCD_OPC_CheckPredicate, 0, 194, 52, 1, // Skip to: 86948 /* 7906 */ MCD_OPC_Decode, 216, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_2 /* 7910 */ MCD_OPC_FilterValue, 1, 185, 52, 1, // Skip to: 86948 /* 7915 */ MCD_OPC_CheckPredicate, 0, 180, 52, 1, // Skip to: 86948 /* 7920 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_2 /* 7924 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 7960 /* 7929 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 7932 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7946 /* 7937 */ MCD_OPC_CheckPredicate, 0, 158, 52, 1, // Skip to: 86948 /* 7942 */ MCD_OPC_Decode, 217, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_3 /* 7946 */ MCD_OPC_FilterValue, 1, 149, 52, 1, // Skip to: 86948 /* 7951 */ MCD_OPC_CheckPredicate, 0, 144, 52, 1, // Skip to: 86948 /* 7956 */ MCD_OPC_Decode, 221, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_3 /* 7960 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 7981 /* 7965 */ MCD_OPC_CheckPredicate, 0, 130, 52, 1, // Skip to: 86948 /* 7970 */ MCD_OPC_CheckField, 22, 1, 1, 123, 52, 1, // Skip to: 86948 /* 7977 */ MCD_OPC_Decode, 239, 12, 27, // Opcode: FTSSEL_ZZZ_H /* 7981 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 8009 /* 7986 */ MCD_OPC_CheckPredicate, 0, 109, 52, 1, // Skip to: 86948 /* 7991 */ MCD_OPC_CheckField, 22, 1, 1, 102, 52, 1, // Skip to: 86948 /* 7998 */ MCD_OPC_CheckField, 16, 5, 0, 95, 52, 1, // Skip to: 86948 /* 8005 */ MCD_OPC_Decode, 184, 9, 38, // Opcode: FEXPA_ZZ_H /* 8009 */ MCD_OPC_FilterValue, 15, 86, 52, 1, // Skip to: 86948 /* 8014 */ MCD_OPC_CheckPredicate, 0, 81, 52, 1, // Skip to: 86948 /* 8019 */ MCD_OPC_CheckField, 22, 1, 0, 74, 52, 1, // Skip to: 86948 /* 8026 */ MCD_OPC_CheckField, 16, 5, 0, 67, 52, 1, // Skip to: 86948 /* 8033 */ MCD_OPC_Decode, 255, 19, 38, // Opcode: MOVPRFX_ZZ /* 8037 */ MCD_OPC_FilterValue, 1, 82, 1, 0, // Skip to: 8380 /* 8042 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 8045 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8066 /* 8050 */ MCD_OPC_CheckPredicate, 0, 45, 52, 1, // Skip to: 86948 /* 8055 */ MCD_OPC_CheckField, 22, 1, 0, 38, 52, 1, // Skip to: 86948 /* 8062 */ MCD_OPC_Decode, 141, 2, 27, // Opcode: ASR_WIDE_ZZZ_S /* 8066 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 8087 /* 8071 */ MCD_OPC_CheckPredicate, 0, 24, 52, 1, // Skip to: 86948 /* 8076 */ MCD_OPC_CheckField, 22, 1, 0, 17, 52, 1, // Skip to: 86948 /* 8083 */ MCD_OPC_Decode, 186, 19, 27, // Opcode: LSR_WIDE_ZZZ_S /* 8087 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 8108 /* 8092 */ MCD_OPC_CheckPredicate, 0, 3, 52, 1, // Skip to: 86948 /* 8097 */ MCD_OPC_CheckField, 22, 1, 0, 252, 51, 1, // Skip to: 86948 /* 8104 */ MCD_OPC_Decode, 162, 19, 27, // Opcode: LSL_WIDE_ZZZ_S /* 8108 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 8122 /* 8113 */ MCD_OPC_CheckPredicate, 0, 238, 51, 1, // Skip to: 86948 /* 8118 */ MCD_OPC_Decode, 151, 2, 60, // Opcode: ASR_ZZI_D /* 8122 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 8136 /* 8127 */ MCD_OPC_CheckPredicate, 0, 224, 51, 1, // Skip to: 86948 /* 8132 */ MCD_OPC_Decode, 196, 19, 60, // Opcode: LSR_ZZI_D /* 8136 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 8150 /* 8141 */ MCD_OPC_CheckPredicate, 0, 210, 51, 1, // Skip to: 86948 /* 8146 */ MCD_OPC_Decode, 172, 19, 61, // Opcode: LSL_ZZI_D /* 8150 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 8186 /* 8155 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8158 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8172 /* 8163 */ MCD_OPC_CheckPredicate, 0, 188, 51, 1, // Skip to: 86948 /* 8168 */ MCD_OPC_Decode, 210, 1, 27, // Opcode: ADR_LSL_ZZZ_S_0 /* 8172 */ MCD_OPC_FilterValue, 1, 179, 51, 1, // Skip to: 86948 /* 8177 */ MCD_OPC_CheckPredicate, 0, 174, 51, 1, // Skip to: 86948 /* 8182 */ MCD_OPC_Decode, 206, 1, 27, // Opcode: ADR_LSL_ZZZ_D_0 /* 8186 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 8222 /* 8191 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8194 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8208 /* 8199 */ MCD_OPC_CheckPredicate, 0, 152, 51, 1, // Skip to: 86948 /* 8204 */ MCD_OPC_Decode, 211, 1, 27, // Opcode: ADR_LSL_ZZZ_S_1 /* 8208 */ MCD_OPC_FilterValue, 1, 143, 51, 1, // Skip to: 86948 /* 8213 */ MCD_OPC_CheckPredicate, 0, 138, 51, 1, // Skip to: 86948 /* 8218 */ MCD_OPC_Decode, 207, 1, 27, // Opcode: ADR_LSL_ZZZ_D_1 /* 8222 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 8258 /* 8227 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8230 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8244 /* 8235 */ MCD_OPC_CheckPredicate, 0, 116, 51, 1, // Skip to: 86948 /* 8240 */ MCD_OPC_Decode, 212, 1, 27, // Opcode: ADR_LSL_ZZZ_S_2 /* 8244 */ MCD_OPC_FilterValue, 1, 107, 51, 1, // Skip to: 86948 /* 8249 */ MCD_OPC_CheckPredicate, 0, 102, 51, 1, // Skip to: 86948 /* 8254 */ MCD_OPC_Decode, 208, 1, 27, // Opcode: ADR_LSL_ZZZ_D_2 /* 8258 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 8294 /* 8263 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8266 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8280 /* 8271 */ MCD_OPC_CheckPredicate, 0, 80, 51, 1, // Skip to: 86948 /* 8276 */ MCD_OPC_Decode, 213, 1, 27, // Opcode: ADR_LSL_ZZZ_S_3 /* 8280 */ MCD_OPC_FilterValue, 1, 71, 51, 1, // Skip to: 86948 /* 8285 */ MCD_OPC_CheckPredicate, 0, 66, 51, 1, // Skip to: 86948 /* 8290 */ MCD_OPC_Decode, 209, 1, 27, // Opcode: ADR_LSL_ZZZ_D_3 /* 8294 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 8330 /* 8299 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8302 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8316 /* 8307 */ MCD_OPC_CheckPredicate, 0, 44, 51, 1, // Skip to: 86948 /* 8312 */ MCD_OPC_Decode, 240, 12, 27, // Opcode: FTSSEL_ZZZ_S /* 8316 */ MCD_OPC_FilterValue, 1, 35, 51, 1, // Skip to: 86948 /* 8321 */ MCD_OPC_CheckPredicate, 0, 30, 51, 1, // Skip to: 86948 /* 8326 */ MCD_OPC_Decode, 238, 12, 27, // Opcode: FTSSEL_ZZZ_D /* 8330 */ MCD_OPC_FilterValue, 14, 21, 51, 1, // Skip to: 86948 /* 8335 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8338 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8359 /* 8343 */ MCD_OPC_CheckPredicate, 0, 8, 51, 1, // Skip to: 86948 /* 8348 */ MCD_OPC_CheckField, 16, 5, 0, 1, 51, 1, // Skip to: 86948 /* 8355 */ MCD_OPC_Decode, 185, 9, 38, // Opcode: FEXPA_ZZ_S /* 8359 */ MCD_OPC_FilterValue, 1, 248, 50, 1, // Skip to: 86948 /* 8364 */ MCD_OPC_CheckPredicate, 0, 243, 50, 1, // Skip to: 86948 /* 8369 */ MCD_OPC_CheckField, 16, 5, 0, 236, 50, 1, // Skip to: 86948 /* 8376 */ MCD_OPC_Decode, 183, 9, 38, // Opcode: FEXPA_ZZ_D /* 8380 */ MCD_OPC_FilterValue, 2, 179, 2, 0, // Skip to: 9076 /* 8385 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 8388 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 8468 /* 8393 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 8396 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8432 /* 8401 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8404 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8418 /* 8409 */ MCD_OPC_CheckPredicate, 0, 198, 50, 1, // Skip to: 86948 /* 8414 */ MCD_OPC_Decode, 141, 5, 62, // Opcode: CPY_ZPmV_B /* 8418 */ MCD_OPC_FilterValue, 1, 189, 50, 1, // Skip to: 86948 /* 8423 */ MCD_OPC_CheckPredicate, 0, 184, 50, 1, // Skip to: 86948 /* 8428 */ MCD_OPC_Decode, 143, 5, 63, // Opcode: CPY_ZPmV_H /* 8432 */ MCD_OPC_FilterValue, 1, 175, 50, 1, // Skip to: 86948 /* 8437 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8440 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8454 /* 8445 */ MCD_OPC_CheckPredicate, 0, 162, 50, 1, // Skip to: 86948 /* 8450 */ MCD_OPC_Decode, 163, 14, 64, // Opcode: LASTA_RPZ_B /* 8454 */ MCD_OPC_FilterValue, 1, 153, 50, 1, // Skip to: 86948 /* 8459 */ MCD_OPC_CheckPredicate, 0, 148, 50, 1, // Skip to: 86948 /* 8464 */ MCD_OPC_Decode, 165, 14, 64, // Opcode: LASTA_RPZ_H /* 8468 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 8518 /* 8473 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8476 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8497 /* 8481 */ MCD_OPC_CheckPredicate, 0, 126, 50, 1, // Skip to: 86948 /* 8486 */ MCD_OPC_CheckField, 13, 1, 1, 119, 50, 1, // Skip to: 86948 /* 8493 */ MCD_OPC_Decode, 171, 14, 64, // Opcode: LASTB_RPZ_B /* 8497 */ MCD_OPC_FilterValue, 1, 110, 50, 1, // Skip to: 86948 /* 8502 */ MCD_OPC_CheckPredicate, 0, 105, 50, 1, // Skip to: 86948 /* 8507 */ MCD_OPC_CheckField, 13, 1, 1, 98, 50, 1, // Skip to: 86948 /* 8514 */ MCD_OPC_Decode, 173, 14, 64, // Opcode: LASTB_RPZ_H /* 8518 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 8568 /* 8523 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8526 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8547 /* 8531 */ MCD_OPC_CheckPredicate, 0, 76, 50, 1, // Skip to: 86948 /* 8536 */ MCD_OPC_CheckField, 13, 1, 0, 69, 50, 1, // Skip to: 86948 /* 8543 */ MCD_OPC_Decode, 167, 14, 2, // Opcode: LASTA_VPZ_B /* 8547 */ MCD_OPC_FilterValue, 1, 60, 50, 1, // Skip to: 86948 /* 8552 */ MCD_OPC_CheckPredicate, 0, 55, 50, 1, // Skip to: 86948 /* 8557 */ MCD_OPC_CheckField, 13, 1, 0, 48, 50, 1, // Skip to: 86948 /* 8564 */ MCD_OPC_Decode, 169, 14, 3, // Opcode: LASTA_VPZ_H /* 8568 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 8618 /* 8573 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8576 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8597 /* 8581 */ MCD_OPC_CheckPredicate, 0, 26, 50, 1, // Skip to: 86948 /* 8586 */ MCD_OPC_CheckField, 13, 1, 0, 19, 50, 1, // Skip to: 86948 /* 8593 */ MCD_OPC_Decode, 175, 14, 2, // Opcode: LASTB_VPZ_B /* 8597 */ MCD_OPC_FilterValue, 1, 10, 50, 1, // Skip to: 86948 /* 8602 */ MCD_OPC_CheckPredicate, 0, 5, 50, 1, // Skip to: 86948 /* 8607 */ MCD_OPC_CheckField, 13, 1, 0, 254, 49, 1, // Skip to: 86948 /* 8614 */ MCD_OPC_Decode, 177, 14, 3, // Opcode: LASTB_VPZ_H /* 8618 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 8646 /* 8623 */ MCD_OPC_CheckPredicate, 0, 240, 49, 1, // Skip to: 86948 /* 8628 */ MCD_OPC_CheckField, 22, 1, 1, 233, 49, 1, // Skip to: 86948 /* 8635 */ MCD_OPC_CheckField, 13, 1, 0, 226, 49, 1, // Skip to: 86948 /* 8642 */ MCD_OPC_Decode, 216, 21, 5, // Opcode: REVB_ZPmZ_H /* 8646 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 8696 /* 8651 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8654 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8675 /* 8659 */ MCD_OPC_CheckPredicate, 0, 204, 49, 1, // Skip to: 86948 /* 8664 */ MCD_OPC_CheckField, 13, 1, 0, 197, 49, 1, // Skip to: 86948 /* 8671 */ MCD_OPC_Decode, 186, 21, 5, // Opcode: RBIT_ZPmZ_B /* 8675 */ MCD_OPC_FilterValue, 1, 188, 49, 1, // Skip to: 86948 /* 8680 */ MCD_OPC_CheckPredicate, 0, 183, 49, 1, // Skip to: 86948 /* 8685 */ MCD_OPC_CheckField, 13, 1, 0, 176, 49, 1, // Skip to: 86948 /* 8692 */ MCD_OPC_Decode, 188, 21, 5, // Opcode: RBIT_ZPmZ_H /* 8696 */ MCD_OPC_FilterValue, 8, 75, 0, 0, // Skip to: 8776 /* 8701 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 8704 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8740 /* 8709 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8712 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8726 /* 8717 */ MCD_OPC_CheckPredicate, 0, 146, 49, 1, // Skip to: 86948 /* 8722 */ MCD_OPC_Decode, 141, 3, 0, // Opcode: CLASTA_ZPZ_B /* 8726 */ MCD_OPC_FilterValue, 1, 137, 49, 1, // Skip to: 86948 /* 8731 */ MCD_OPC_CheckPredicate, 0, 132, 49, 1, // Skip to: 86948 /* 8736 */ MCD_OPC_Decode, 143, 3, 0, // Opcode: CLASTA_ZPZ_H /* 8740 */ MCD_OPC_FilterValue, 1, 123, 49, 1, // Skip to: 86948 /* 8745 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8748 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8762 /* 8753 */ MCD_OPC_CheckPredicate, 0, 110, 49, 1, // Skip to: 86948 /* 8758 */ MCD_OPC_Decode, 137, 5, 65, // Opcode: CPY_ZPmR_B /* 8762 */ MCD_OPC_FilterValue, 1, 101, 49, 1, // Skip to: 86948 /* 8767 */ MCD_OPC_CheckPredicate, 0, 96, 49, 1, // Skip to: 86948 /* 8772 */ MCD_OPC_Decode, 139, 5, 65, // Opcode: CPY_ZPmR_H /* 8776 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 8826 /* 8781 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8784 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8805 /* 8789 */ MCD_OPC_CheckPredicate, 0, 74, 49, 1, // Skip to: 86948 /* 8794 */ MCD_OPC_CheckField, 13, 1, 0, 67, 49, 1, // Skip to: 86948 /* 8801 */ MCD_OPC_Decode, 153, 3, 0, // Opcode: CLASTB_ZPZ_B /* 8805 */ MCD_OPC_FilterValue, 1, 58, 49, 1, // Skip to: 86948 /* 8810 */ MCD_OPC_CheckPredicate, 0, 53, 49, 1, // Skip to: 86948 /* 8815 */ MCD_OPC_CheckField, 13, 1, 0, 46, 49, 1, // Skip to: 86948 /* 8822 */ MCD_OPC_Decode, 155, 3, 0, // Opcode: CLASTB_ZPZ_H /* 8826 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 8876 /* 8831 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8834 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8855 /* 8839 */ MCD_OPC_CheckPredicate, 0, 24, 49, 1, // Skip to: 86948 /* 8844 */ MCD_OPC_CheckField, 13, 1, 0, 17, 49, 1, // Skip to: 86948 /* 8851 */ MCD_OPC_Decode, 137, 3, 66, // Opcode: CLASTA_VPZ_B /* 8855 */ MCD_OPC_FilterValue, 1, 8, 49, 1, // Skip to: 86948 /* 8860 */ MCD_OPC_CheckPredicate, 0, 3, 49, 1, // Skip to: 86948 /* 8865 */ MCD_OPC_CheckField, 13, 1, 0, 252, 48, 1, // Skip to: 86948 /* 8872 */ MCD_OPC_Decode, 139, 3, 67, // Opcode: CLASTA_VPZ_H /* 8876 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 8926 /* 8881 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8884 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8905 /* 8889 */ MCD_OPC_CheckPredicate, 0, 230, 48, 1, // Skip to: 86948 /* 8894 */ MCD_OPC_CheckField, 13, 1, 0, 223, 48, 1, // Skip to: 86948 /* 8901 */ MCD_OPC_Decode, 149, 3, 66, // Opcode: CLASTB_VPZ_B /* 8905 */ MCD_OPC_FilterValue, 1, 214, 48, 1, // Skip to: 86948 /* 8910 */ MCD_OPC_CheckPredicate, 0, 209, 48, 1, // Skip to: 86948 /* 8915 */ MCD_OPC_CheckField, 13, 1, 0, 202, 48, 1, // Skip to: 86948 /* 8922 */ MCD_OPC_Decode, 151, 3, 67, // Opcode: CLASTB_VPZ_H /* 8926 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 8976 /* 8931 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8934 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8955 /* 8939 */ MCD_OPC_CheckPredicate, 0, 180, 48, 1, // Skip to: 86948 /* 8944 */ MCD_OPC_CheckField, 13, 1, 0, 173, 48, 1, // Skip to: 86948 /* 8951 */ MCD_OPC_Decode, 149, 24, 0, // Opcode: SPLICE_ZPZ_B /* 8955 */ MCD_OPC_FilterValue, 1, 164, 48, 1, // Skip to: 86948 /* 8960 */ MCD_OPC_CheckPredicate, 0, 159, 48, 1, // Skip to: 86948 /* 8965 */ MCD_OPC_CheckField, 13, 1, 0, 152, 48, 1, // Skip to: 86948 /* 8972 */ MCD_OPC_Decode, 151, 24, 0, // Opcode: SPLICE_ZPZ_H /* 8976 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 9026 /* 8981 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 8984 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9005 /* 8989 */ MCD_OPC_CheckPredicate, 0, 130, 48, 1, // Skip to: 86948 /* 8994 */ MCD_OPC_CheckField, 13, 1, 1, 123, 48, 1, // Skip to: 86948 /* 9001 */ MCD_OPC_Decode, 133, 3, 68, // Opcode: CLASTA_RPZ_B /* 9005 */ MCD_OPC_FilterValue, 1, 114, 48, 1, // Skip to: 86948 /* 9010 */ MCD_OPC_CheckPredicate, 0, 109, 48, 1, // Skip to: 86948 /* 9015 */ MCD_OPC_CheckField, 13, 1, 1, 102, 48, 1, // Skip to: 86948 /* 9022 */ MCD_OPC_Decode, 135, 3, 68, // Opcode: CLASTA_RPZ_H /* 9026 */ MCD_OPC_FilterValue, 17, 93, 48, 1, // Skip to: 86948 /* 9031 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9034 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9055 /* 9039 */ MCD_OPC_CheckPredicate, 0, 80, 48, 1, // Skip to: 86948 /* 9044 */ MCD_OPC_CheckField, 13, 1, 1, 73, 48, 1, // Skip to: 86948 /* 9051 */ MCD_OPC_Decode, 145, 3, 68, // Opcode: CLASTB_RPZ_B /* 9055 */ MCD_OPC_FilterValue, 1, 64, 48, 1, // Skip to: 86948 /* 9060 */ MCD_OPC_CheckPredicate, 0, 59, 48, 1, // Skip to: 86948 /* 9065 */ MCD_OPC_CheckField, 13, 1, 1, 52, 48, 1, // Skip to: 86948 /* 9072 */ MCD_OPC_Decode, 147, 3, 68, // Opcode: CLASTB_RPZ_H /* 9076 */ MCD_OPC_FilterValue, 3, 43, 48, 1, // Skip to: 86948 /* 9081 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 9084 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 9164 /* 9089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 9092 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9128 /* 9097 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9114 /* 9105 */ MCD_OPC_CheckPredicate, 0, 14, 48, 1, // Skip to: 86948 /* 9110 */ MCD_OPC_Decode, 144, 5, 69, // Opcode: CPY_ZPmV_S /* 9114 */ MCD_OPC_FilterValue, 1, 5, 48, 1, // Skip to: 86948 /* 9119 */ MCD_OPC_CheckPredicate, 0, 0, 48, 1, // Skip to: 86948 /* 9124 */ MCD_OPC_Decode, 142, 5, 70, // Opcode: CPY_ZPmV_D /* 9128 */ MCD_OPC_FilterValue, 1, 247, 47, 1, // Skip to: 86948 /* 9133 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9136 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9150 /* 9141 */ MCD_OPC_CheckPredicate, 0, 234, 47, 1, // Skip to: 86948 /* 9146 */ MCD_OPC_Decode, 166, 14, 64, // Opcode: LASTA_RPZ_S /* 9150 */ MCD_OPC_FilterValue, 1, 225, 47, 1, // Skip to: 86948 /* 9155 */ MCD_OPC_CheckPredicate, 0, 220, 47, 1, // Skip to: 86948 /* 9160 */ MCD_OPC_Decode, 164, 14, 71, // Opcode: LASTA_RPZ_D /* 9164 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 9244 /* 9169 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 9172 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9208 /* 9177 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9180 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9194 /* 9185 */ MCD_OPC_CheckPredicate, 0, 190, 47, 1, // Skip to: 86948 /* 9190 */ MCD_OPC_Decode, 132, 5, 4, // Opcode: COMPACT_ZPZ_S /* 9194 */ MCD_OPC_FilterValue, 1, 181, 47, 1, // Skip to: 86948 /* 9199 */ MCD_OPC_CheckPredicate, 0, 176, 47, 1, // Skip to: 86948 /* 9204 */ MCD_OPC_Decode, 131, 5, 4, // Opcode: COMPACT_ZPZ_D /* 9208 */ MCD_OPC_FilterValue, 1, 167, 47, 1, // Skip to: 86948 /* 9213 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9216 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9230 /* 9221 */ MCD_OPC_CheckPredicate, 0, 154, 47, 1, // Skip to: 86948 /* 9226 */ MCD_OPC_Decode, 174, 14, 64, // Opcode: LASTB_RPZ_S /* 9230 */ MCD_OPC_FilterValue, 1, 145, 47, 1, // Skip to: 86948 /* 9235 */ MCD_OPC_CheckPredicate, 0, 140, 47, 1, // Skip to: 86948 /* 9240 */ MCD_OPC_Decode, 172, 14, 71, // Opcode: LASTB_RPZ_D /* 9244 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 9294 /* 9249 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9252 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9273 /* 9257 */ MCD_OPC_CheckPredicate, 0, 118, 47, 1, // Skip to: 86948 /* 9262 */ MCD_OPC_CheckField, 13, 1, 0, 111, 47, 1, // Skip to: 86948 /* 9269 */ MCD_OPC_Decode, 170, 14, 14, // Opcode: LASTA_VPZ_S /* 9273 */ MCD_OPC_FilterValue, 1, 102, 47, 1, // Skip to: 86948 /* 9278 */ MCD_OPC_CheckPredicate, 0, 97, 47, 1, // Skip to: 86948 /* 9283 */ MCD_OPC_CheckField, 13, 1, 0, 90, 47, 1, // Skip to: 86948 /* 9290 */ MCD_OPC_Decode, 168, 14, 1, // Opcode: LASTA_VPZ_D /* 9294 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 9344 /* 9299 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9302 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9323 /* 9307 */ MCD_OPC_CheckPredicate, 0, 68, 47, 1, // Skip to: 86948 /* 9312 */ MCD_OPC_CheckField, 13, 1, 0, 61, 47, 1, // Skip to: 86948 /* 9319 */ MCD_OPC_Decode, 178, 14, 14, // Opcode: LASTB_VPZ_S /* 9323 */ MCD_OPC_FilterValue, 1, 52, 47, 1, // Skip to: 86948 /* 9328 */ MCD_OPC_CheckPredicate, 0, 47, 47, 1, // Skip to: 86948 /* 9333 */ MCD_OPC_CheckField, 13, 1, 0, 40, 47, 1, // Skip to: 86948 /* 9340 */ MCD_OPC_Decode, 176, 14, 1, // Opcode: LASTB_VPZ_D /* 9344 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 9394 /* 9349 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9352 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9373 /* 9357 */ MCD_OPC_CheckPredicate, 0, 18, 47, 1, // Skip to: 86948 /* 9362 */ MCD_OPC_CheckField, 13, 1, 0, 11, 47, 1, // Skip to: 86948 /* 9369 */ MCD_OPC_Decode, 217, 21, 5, // Opcode: REVB_ZPmZ_S /* 9373 */ MCD_OPC_FilterValue, 1, 2, 47, 1, // Skip to: 86948 /* 9378 */ MCD_OPC_CheckPredicate, 0, 253, 46, 1, // Skip to: 86948 /* 9383 */ MCD_OPC_CheckField, 13, 1, 0, 246, 46, 1, // Skip to: 86948 /* 9390 */ MCD_OPC_Decode, 215, 21, 5, // Opcode: REVB_ZPmZ_D /* 9394 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 9444 /* 9399 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9402 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9423 /* 9407 */ MCD_OPC_CheckPredicate, 0, 224, 46, 1, // Skip to: 86948 /* 9412 */ MCD_OPC_CheckField, 13, 1, 0, 217, 46, 1, // Skip to: 86948 /* 9419 */ MCD_OPC_Decode, 219, 21, 5, // Opcode: REVH_ZPmZ_S /* 9423 */ MCD_OPC_FilterValue, 1, 208, 46, 1, // Skip to: 86948 /* 9428 */ MCD_OPC_CheckPredicate, 0, 203, 46, 1, // Skip to: 86948 /* 9433 */ MCD_OPC_CheckField, 13, 1, 0, 196, 46, 1, // Skip to: 86948 /* 9440 */ MCD_OPC_Decode, 218, 21, 5, // Opcode: REVH_ZPmZ_D /* 9444 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 9472 /* 9449 */ MCD_OPC_CheckPredicate, 0, 182, 46, 1, // Skip to: 86948 /* 9454 */ MCD_OPC_CheckField, 22, 1, 1, 175, 46, 1, // Skip to: 86948 /* 9461 */ MCD_OPC_CheckField, 13, 1, 0, 168, 46, 1, // Skip to: 86948 /* 9468 */ MCD_OPC_Decode, 220, 21, 5, // Opcode: REVW_ZPmZ_D /* 9472 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 9522 /* 9477 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9480 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9501 /* 9485 */ MCD_OPC_CheckPredicate, 0, 146, 46, 1, // Skip to: 86948 /* 9490 */ MCD_OPC_CheckField, 13, 1, 0, 139, 46, 1, // Skip to: 86948 /* 9497 */ MCD_OPC_Decode, 189, 21, 5, // Opcode: RBIT_ZPmZ_S /* 9501 */ MCD_OPC_FilterValue, 1, 130, 46, 1, // Skip to: 86948 /* 9506 */ MCD_OPC_CheckPredicate, 0, 125, 46, 1, // Skip to: 86948 /* 9511 */ MCD_OPC_CheckField, 13, 1, 0, 118, 46, 1, // Skip to: 86948 /* 9518 */ MCD_OPC_Decode, 187, 21, 5, // Opcode: RBIT_ZPmZ_D /* 9522 */ MCD_OPC_FilterValue, 8, 75, 0, 0, // Skip to: 9602 /* 9527 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 9530 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9566 /* 9535 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9538 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9552 /* 9543 */ MCD_OPC_CheckPredicate, 0, 88, 46, 1, // Skip to: 86948 /* 9548 */ MCD_OPC_Decode, 144, 3, 0, // Opcode: CLASTA_ZPZ_S /* 9552 */ MCD_OPC_FilterValue, 1, 79, 46, 1, // Skip to: 86948 /* 9557 */ MCD_OPC_CheckPredicate, 0, 74, 46, 1, // Skip to: 86948 /* 9562 */ MCD_OPC_Decode, 142, 3, 0, // Opcode: CLASTA_ZPZ_D /* 9566 */ MCD_OPC_FilterValue, 1, 65, 46, 1, // Skip to: 86948 /* 9571 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9574 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9588 /* 9579 */ MCD_OPC_CheckPredicate, 0, 52, 46, 1, // Skip to: 86948 /* 9584 */ MCD_OPC_Decode, 140, 5, 65, // Opcode: CPY_ZPmR_S /* 9588 */ MCD_OPC_FilterValue, 1, 43, 46, 1, // Skip to: 86948 /* 9593 */ MCD_OPC_CheckPredicate, 0, 38, 46, 1, // Skip to: 86948 /* 9598 */ MCD_OPC_Decode, 138, 5, 72, // Opcode: CPY_ZPmR_D /* 9602 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 9652 /* 9607 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9610 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9631 /* 9615 */ MCD_OPC_CheckPredicate, 0, 16, 46, 1, // Skip to: 86948 /* 9620 */ MCD_OPC_CheckField, 13, 1, 0, 9, 46, 1, // Skip to: 86948 /* 9627 */ MCD_OPC_Decode, 156, 3, 0, // Opcode: CLASTB_ZPZ_S /* 9631 */ MCD_OPC_FilterValue, 1, 0, 46, 1, // Skip to: 86948 /* 9636 */ MCD_OPC_CheckPredicate, 0, 251, 45, 1, // Skip to: 86948 /* 9641 */ MCD_OPC_CheckField, 13, 1, 0, 244, 45, 1, // Skip to: 86948 /* 9648 */ MCD_OPC_Decode, 154, 3, 0, // Opcode: CLASTB_ZPZ_D /* 9652 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 9702 /* 9657 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9660 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9681 /* 9665 */ MCD_OPC_CheckPredicate, 0, 222, 45, 1, // Skip to: 86948 /* 9670 */ MCD_OPC_CheckField, 13, 1, 0, 215, 45, 1, // Skip to: 86948 /* 9677 */ MCD_OPC_Decode, 140, 3, 73, // Opcode: CLASTA_VPZ_S /* 9681 */ MCD_OPC_FilterValue, 1, 206, 45, 1, // Skip to: 86948 /* 9686 */ MCD_OPC_CheckPredicate, 0, 201, 45, 1, // Skip to: 86948 /* 9691 */ MCD_OPC_CheckField, 13, 1, 0, 194, 45, 1, // Skip to: 86948 /* 9698 */ MCD_OPC_Decode, 138, 3, 74, // Opcode: CLASTA_VPZ_D /* 9702 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 9752 /* 9707 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9710 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9731 /* 9715 */ MCD_OPC_CheckPredicate, 0, 172, 45, 1, // Skip to: 86948 /* 9720 */ MCD_OPC_CheckField, 13, 1, 0, 165, 45, 1, // Skip to: 86948 /* 9727 */ MCD_OPC_Decode, 152, 3, 73, // Opcode: CLASTB_VPZ_S /* 9731 */ MCD_OPC_FilterValue, 1, 156, 45, 1, // Skip to: 86948 /* 9736 */ MCD_OPC_CheckPredicate, 0, 151, 45, 1, // Skip to: 86948 /* 9741 */ MCD_OPC_CheckField, 13, 1, 0, 144, 45, 1, // Skip to: 86948 /* 9748 */ MCD_OPC_Decode, 150, 3, 74, // Opcode: CLASTB_VPZ_D /* 9752 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 9802 /* 9757 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9760 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9781 /* 9765 */ MCD_OPC_CheckPredicate, 0, 122, 45, 1, // Skip to: 86948 /* 9770 */ MCD_OPC_CheckField, 13, 1, 0, 115, 45, 1, // Skip to: 86948 /* 9777 */ MCD_OPC_Decode, 152, 24, 0, // Opcode: SPLICE_ZPZ_S /* 9781 */ MCD_OPC_FilterValue, 1, 106, 45, 1, // Skip to: 86948 /* 9786 */ MCD_OPC_CheckPredicate, 0, 101, 45, 1, // Skip to: 86948 /* 9791 */ MCD_OPC_CheckField, 13, 1, 0, 94, 45, 1, // Skip to: 86948 /* 9798 */ MCD_OPC_Decode, 150, 24, 0, // Opcode: SPLICE_ZPZ_D /* 9802 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 9852 /* 9807 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9810 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9831 /* 9815 */ MCD_OPC_CheckPredicate, 0, 72, 45, 1, // Skip to: 86948 /* 9820 */ MCD_OPC_CheckField, 13, 1, 1, 65, 45, 1, // Skip to: 86948 /* 9827 */ MCD_OPC_Decode, 136, 3, 68, // Opcode: CLASTA_RPZ_S /* 9831 */ MCD_OPC_FilterValue, 1, 56, 45, 1, // Skip to: 86948 /* 9836 */ MCD_OPC_CheckPredicate, 0, 51, 45, 1, // Skip to: 86948 /* 9841 */ MCD_OPC_CheckField, 13, 1, 1, 44, 45, 1, // Skip to: 86948 /* 9848 */ MCD_OPC_Decode, 134, 3, 75, // Opcode: CLASTA_RPZ_D /* 9852 */ MCD_OPC_FilterValue, 17, 35, 45, 1, // Skip to: 86948 /* 9857 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 9860 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9881 /* 9865 */ MCD_OPC_CheckPredicate, 0, 22, 45, 1, // Skip to: 86948 /* 9870 */ MCD_OPC_CheckField, 13, 1, 1, 15, 45, 1, // Skip to: 86948 /* 9877 */ MCD_OPC_Decode, 148, 3, 68, // Opcode: CLASTB_RPZ_S /* 9881 */ MCD_OPC_FilterValue, 1, 6, 45, 1, // Skip to: 86948 /* 9886 */ MCD_OPC_CheckPredicate, 0, 1, 45, 1, // Skip to: 86948 /* 9891 */ MCD_OPC_CheckField, 13, 1, 1, 250, 44, 1, // Skip to: 86948 /* 9898 */ MCD_OPC_Decode, 146, 3, 75, // Opcode: CLASTB_RPZ_D /* 9902 */ MCD_OPC_FilterValue, 3, 241, 44, 1, // Skip to: 86948 /* 9907 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 9910 */ MCD_OPC_FilterValue, 0, 204, 0, 0, // Skip to: 10119 /* 9915 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 9918 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 9954 /* 9923 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 9926 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9940 /* 9931 */ MCD_OPC_CheckPredicate, 0, 212, 44, 1, // Skip to: 86948 /* 9936 */ MCD_OPC_Decode, 245, 4, 76, // Opcode: CNTB_XPiI /* 9940 */ MCD_OPC_FilterValue, 1, 203, 44, 1, // Skip to: 86948 /* 9945 */ MCD_OPC_CheckPredicate, 0, 198, 44, 1, // Skip to: 86948 /* 9950 */ MCD_OPC_Decode, 244, 13, 77, // Opcode: INCB_XPiI /* 9954 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 9975 /* 9959 */ MCD_OPC_CheckPredicate, 0, 184, 44, 1, // Skip to: 86948 /* 9964 */ MCD_OPC_CheckField, 20, 1, 1, 177, 44, 1, // Skip to: 86948 /* 9971 */ MCD_OPC_Decode, 177, 5, 77, // Opcode: DECB_XPiI /* 9975 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10011 /* 9980 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 9983 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9997 /* 9988 */ MCD_OPC_CheckPredicate, 0, 155, 44, 1, // Skip to: 86948 /* 9993 */ MCD_OPC_Decode, 254, 24, 77, // Opcode: SQINCB_XPiWdI /* 9997 */ MCD_OPC_FilterValue, 1, 146, 44, 1, // Skip to: 86948 /* 10002 */ MCD_OPC_CheckPredicate, 0, 141, 44, 1, // Skip to: 86948 /* 10007 */ MCD_OPC_Decode, 253, 24, 77, // Opcode: SQINCB_XPiI /* 10011 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10047 /* 10016 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10019 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10033 /* 10024 */ MCD_OPC_CheckPredicate, 0, 119, 44, 1, // Skip to: 86948 /* 10029 */ MCD_OPC_Decode, 244, 32, 78, // Opcode: UQINCB_WPiI /* 10033 */ MCD_OPC_FilterValue, 1, 110, 44, 1, // Skip to: 86948 /* 10038 */ MCD_OPC_CheckPredicate, 0, 105, 44, 1, // Skip to: 86948 /* 10043 */ MCD_OPC_Decode, 245, 32, 77, // Opcode: UQINCB_XPiI /* 10047 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10083 /* 10052 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10055 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10069 /* 10060 */ MCD_OPC_CheckPredicate, 0, 83, 44, 1, // Skip to: 86948 /* 10065 */ MCD_OPC_Decode, 184, 24, 77, // Opcode: SQDECB_XPiWdI /* 10069 */ MCD_OPC_FilterValue, 1, 74, 44, 1, // Skip to: 86948 /* 10074 */ MCD_OPC_CheckPredicate, 0, 69, 44, 1, // Skip to: 86948 /* 10079 */ MCD_OPC_Decode, 183, 24, 77, // Opcode: SQDECB_XPiI /* 10083 */ MCD_OPC_FilterValue, 15, 60, 44, 1, // Skip to: 86948 /* 10088 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10091 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10105 /* 10096 */ MCD_OPC_CheckPredicate, 0, 47, 44, 1, // Skip to: 86948 /* 10101 */ MCD_OPC_Decode, 222, 32, 78, // Opcode: UQDECB_WPiI /* 10105 */ MCD_OPC_FilterValue, 1, 38, 44, 1, // Skip to: 86948 /* 10110 */ MCD_OPC_CheckPredicate, 0, 33, 44, 1, // Skip to: 86948 /* 10115 */ MCD_OPC_Decode, 223, 32, 77, // Opcode: UQDECB_XPiI /* 10119 */ MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 10442 /* 10124 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 10127 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10163 /* 10132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10135 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10149 /* 10140 */ MCD_OPC_CheckPredicate, 0, 3, 44, 1, // Skip to: 86948 /* 10145 */ MCD_OPC_Decode, 132, 25, 79, // Opcode: SQINCH_ZPiI /* 10149 */ MCD_OPC_FilterValue, 1, 250, 43, 1, // Skip to: 86948 /* 10154 */ MCD_OPC_CheckPredicate, 0, 245, 43, 1, // Skip to: 86948 /* 10159 */ MCD_OPC_Decode, 248, 13, 79, // Opcode: INCH_ZPiI /* 10163 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10199 /* 10168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10185 /* 10176 */ MCD_OPC_CheckPredicate, 0, 223, 43, 1, // Skip to: 86948 /* 10181 */ MCD_OPC_Decode, 251, 32, 79, // Opcode: UQINCH_ZPiI /* 10185 */ MCD_OPC_FilterValue, 1, 214, 43, 1, // Skip to: 86948 /* 10190 */ MCD_OPC_CheckPredicate, 0, 209, 43, 1, // Skip to: 86948 /* 10195 */ MCD_OPC_Decode, 181, 5, 79, // Opcode: DECH_ZPiI /* 10199 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10220 /* 10204 */ MCD_OPC_CheckPredicate, 0, 195, 43, 1, // Skip to: 86948 /* 10209 */ MCD_OPC_CheckField, 20, 1, 0, 188, 43, 1, // Skip to: 86948 /* 10216 */ MCD_OPC_Decode, 190, 24, 79, // Opcode: SQDECH_ZPiI /* 10220 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10241 /* 10225 */ MCD_OPC_CheckPredicate, 0, 174, 43, 1, // Skip to: 86948 /* 10230 */ MCD_OPC_CheckField, 20, 1, 0, 167, 43, 1, // Skip to: 86948 /* 10237 */ MCD_OPC_Decode, 229, 32, 79, // Opcode: UQDECH_ZPiI /* 10241 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10277 /* 10246 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10249 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10263 /* 10254 */ MCD_OPC_CheckPredicate, 0, 145, 43, 1, // Skip to: 86948 /* 10259 */ MCD_OPC_Decode, 247, 4, 76, // Opcode: CNTH_XPiI /* 10263 */ MCD_OPC_FilterValue, 1, 136, 43, 1, // Skip to: 86948 /* 10268 */ MCD_OPC_CheckPredicate, 0, 131, 43, 1, // Skip to: 86948 /* 10273 */ MCD_OPC_Decode, 247, 13, 77, // Opcode: INCH_XPiI /* 10277 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10298 /* 10282 */ MCD_OPC_CheckPredicate, 0, 117, 43, 1, // Skip to: 86948 /* 10287 */ MCD_OPC_CheckField, 20, 1, 1, 110, 43, 1, // Skip to: 86948 /* 10294 */ MCD_OPC_Decode, 180, 5, 77, // Opcode: DECH_XPiI /* 10298 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10334 /* 10303 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10306 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10320 /* 10311 */ MCD_OPC_CheckPredicate, 0, 88, 43, 1, // Skip to: 86948 /* 10316 */ MCD_OPC_Decode, 131, 25, 77, // Opcode: SQINCH_XPiWdI /* 10320 */ MCD_OPC_FilterValue, 1, 79, 43, 1, // Skip to: 86948 /* 10325 */ MCD_OPC_CheckPredicate, 0, 74, 43, 1, // Skip to: 86948 /* 10330 */ MCD_OPC_Decode, 130, 25, 77, // Opcode: SQINCH_XPiI /* 10334 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10370 /* 10339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10342 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10356 /* 10347 */ MCD_OPC_CheckPredicate, 0, 52, 43, 1, // Skip to: 86948 /* 10352 */ MCD_OPC_Decode, 249, 32, 78, // Opcode: UQINCH_WPiI /* 10356 */ MCD_OPC_FilterValue, 1, 43, 43, 1, // Skip to: 86948 /* 10361 */ MCD_OPC_CheckPredicate, 0, 38, 43, 1, // Skip to: 86948 /* 10366 */ MCD_OPC_Decode, 250, 32, 77, // Opcode: UQINCH_XPiI /* 10370 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10406 /* 10375 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10378 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10392 /* 10383 */ MCD_OPC_CheckPredicate, 0, 16, 43, 1, // Skip to: 86948 /* 10388 */ MCD_OPC_Decode, 189, 24, 77, // Opcode: SQDECH_XPiWdI /* 10392 */ MCD_OPC_FilterValue, 1, 7, 43, 1, // Skip to: 86948 /* 10397 */ MCD_OPC_CheckPredicate, 0, 2, 43, 1, // Skip to: 86948 /* 10402 */ MCD_OPC_Decode, 188, 24, 77, // Opcode: SQDECH_XPiI /* 10406 */ MCD_OPC_FilterValue, 15, 249, 42, 1, // Skip to: 86948 /* 10411 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10428 /* 10419 */ MCD_OPC_CheckPredicate, 0, 236, 42, 1, // Skip to: 86948 /* 10424 */ MCD_OPC_Decode, 227, 32, 78, // Opcode: UQDECH_WPiI /* 10428 */ MCD_OPC_FilterValue, 1, 227, 42, 1, // Skip to: 86948 /* 10433 */ MCD_OPC_CheckPredicate, 0, 222, 42, 1, // Skip to: 86948 /* 10438 */ MCD_OPC_Decode, 228, 32, 77, // Opcode: UQDECH_XPiI /* 10442 */ MCD_OPC_FilterValue, 2, 62, 1, 0, // Skip to: 10765 /* 10447 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 10450 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10486 /* 10455 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10458 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10472 /* 10463 */ MCD_OPC_CheckPredicate, 0, 192, 42, 1, // Skip to: 86948 /* 10468 */ MCD_OPC_Decode, 146, 25, 79, // Opcode: SQINCW_ZPiI /* 10472 */ MCD_OPC_FilterValue, 1, 183, 42, 1, // Skip to: 86948 /* 10477 */ MCD_OPC_CheckPredicate, 0, 178, 42, 1, // Skip to: 86948 /* 10482 */ MCD_OPC_Decode, 129, 14, 79, // Opcode: INCW_ZPiI /* 10486 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10522 /* 10491 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10494 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10508 /* 10499 */ MCD_OPC_CheckPredicate, 0, 156, 42, 1, // Skip to: 86948 /* 10504 */ MCD_OPC_Decode, 137, 33, 79, // Opcode: UQINCW_ZPiI /* 10508 */ MCD_OPC_FilterValue, 1, 147, 42, 1, // Skip to: 86948 /* 10513 */ MCD_OPC_CheckPredicate, 0, 142, 42, 1, // Skip to: 86948 /* 10518 */ MCD_OPC_Decode, 190, 5, 79, // Opcode: DECW_ZPiI /* 10522 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10543 /* 10527 */ MCD_OPC_CheckPredicate, 0, 128, 42, 1, // Skip to: 86948 /* 10532 */ MCD_OPC_CheckField, 20, 1, 0, 121, 42, 1, // Skip to: 86948 /* 10539 */ MCD_OPC_Decode, 204, 24, 79, // Opcode: SQDECW_ZPiI /* 10543 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10564 /* 10548 */ MCD_OPC_CheckPredicate, 0, 107, 42, 1, // Skip to: 86948 /* 10553 */ MCD_OPC_CheckField, 20, 1, 0, 100, 42, 1, // Skip to: 86948 /* 10560 */ MCD_OPC_Decode, 243, 32, 79, // Opcode: UQDECW_ZPiI /* 10564 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10600 /* 10569 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10572 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10586 /* 10577 */ MCD_OPC_CheckPredicate, 0, 78, 42, 1, // Skip to: 86948 /* 10582 */ MCD_OPC_Decode, 252, 4, 76, // Opcode: CNTW_XPiI /* 10586 */ MCD_OPC_FilterValue, 1, 69, 42, 1, // Skip to: 86948 /* 10591 */ MCD_OPC_CheckPredicate, 0, 64, 42, 1, // Skip to: 86948 /* 10596 */ MCD_OPC_Decode, 128, 14, 77, // Opcode: INCW_XPiI /* 10600 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10621 /* 10605 */ MCD_OPC_CheckPredicate, 0, 50, 42, 1, // Skip to: 86948 /* 10610 */ MCD_OPC_CheckField, 20, 1, 1, 43, 42, 1, // Skip to: 86948 /* 10617 */ MCD_OPC_Decode, 189, 5, 77, // Opcode: DECW_XPiI /* 10621 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10657 /* 10626 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10629 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10643 /* 10634 */ MCD_OPC_CheckPredicate, 0, 21, 42, 1, // Skip to: 86948 /* 10639 */ MCD_OPC_Decode, 145, 25, 77, // Opcode: SQINCW_XPiWdI /* 10643 */ MCD_OPC_FilterValue, 1, 12, 42, 1, // Skip to: 86948 /* 10648 */ MCD_OPC_CheckPredicate, 0, 7, 42, 1, // Skip to: 86948 /* 10653 */ MCD_OPC_Decode, 144, 25, 77, // Opcode: SQINCW_XPiI /* 10657 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10693 /* 10662 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10665 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10679 /* 10670 */ MCD_OPC_CheckPredicate, 0, 241, 41, 1, // Skip to: 86948 /* 10675 */ MCD_OPC_Decode, 135, 33, 78, // Opcode: UQINCW_WPiI /* 10679 */ MCD_OPC_FilterValue, 1, 232, 41, 1, // Skip to: 86948 /* 10684 */ MCD_OPC_CheckPredicate, 0, 227, 41, 1, // Skip to: 86948 /* 10689 */ MCD_OPC_Decode, 136, 33, 77, // Opcode: UQINCW_XPiI /* 10693 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10729 /* 10698 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10701 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10715 /* 10706 */ MCD_OPC_CheckPredicate, 0, 205, 41, 1, // Skip to: 86948 /* 10711 */ MCD_OPC_Decode, 203, 24, 77, // Opcode: SQDECW_XPiWdI /* 10715 */ MCD_OPC_FilterValue, 1, 196, 41, 1, // Skip to: 86948 /* 10720 */ MCD_OPC_CheckPredicate, 0, 191, 41, 1, // Skip to: 86948 /* 10725 */ MCD_OPC_Decode, 202, 24, 77, // Opcode: SQDECW_XPiI /* 10729 */ MCD_OPC_FilterValue, 15, 182, 41, 1, // Skip to: 86948 /* 10734 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10737 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10751 /* 10742 */ MCD_OPC_CheckPredicate, 0, 169, 41, 1, // Skip to: 86948 /* 10747 */ MCD_OPC_Decode, 241, 32, 78, // Opcode: UQDECW_WPiI /* 10751 */ MCD_OPC_FilterValue, 1, 160, 41, 1, // Skip to: 86948 /* 10756 */ MCD_OPC_CheckPredicate, 0, 155, 41, 1, // Skip to: 86948 /* 10761 */ MCD_OPC_Decode, 242, 32, 77, // Opcode: UQDECW_XPiI /* 10765 */ MCD_OPC_FilterValue, 3, 62, 1, 0, // Skip to: 11088 /* 10770 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 10773 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10809 /* 10778 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10781 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10795 /* 10786 */ MCD_OPC_CheckPredicate, 0, 125, 41, 1, // Skip to: 86948 /* 10791 */ MCD_OPC_Decode, 129, 25, 79, // Opcode: SQINCD_ZPiI /* 10795 */ MCD_OPC_FilterValue, 1, 116, 41, 1, // Skip to: 86948 /* 10800 */ MCD_OPC_CheckPredicate, 0, 111, 41, 1, // Skip to: 86948 /* 10805 */ MCD_OPC_Decode, 246, 13, 79, // Opcode: INCD_ZPiI /* 10809 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10845 /* 10814 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10817 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10831 /* 10822 */ MCD_OPC_CheckPredicate, 0, 89, 41, 1, // Skip to: 86948 /* 10827 */ MCD_OPC_Decode, 248, 32, 79, // Opcode: UQINCD_ZPiI /* 10831 */ MCD_OPC_FilterValue, 1, 80, 41, 1, // Skip to: 86948 /* 10836 */ MCD_OPC_CheckPredicate, 0, 75, 41, 1, // Skip to: 86948 /* 10841 */ MCD_OPC_Decode, 179, 5, 79, // Opcode: DECD_ZPiI /* 10845 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10866 /* 10850 */ MCD_OPC_CheckPredicate, 0, 61, 41, 1, // Skip to: 86948 /* 10855 */ MCD_OPC_CheckField, 20, 1, 0, 54, 41, 1, // Skip to: 86948 /* 10862 */ MCD_OPC_Decode, 187, 24, 79, // Opcode: SQDECD_ZPiI /* 10866 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10887 /* 10871 */ MCD_OPC_CheckPredicate, 0, 40, 41, 1, // Skip to: 86948 /* 10876 */ MCD_OPC_CheckField, 20, 1, 0, 33, 41, 1, // Skip to: 86948 /* 10883 */ MCD_OPC_Decode, 226, 32, 79, // Opcode: UQDECD_ZPiI /* 10887 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10923 /* 10892 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10895 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10909 /* 10900 */ MCD_OPC_CheckPredicate, 0, 11, 41, 1, // Skip to: 86948 /* 10905 */ MCD_OPC_Decode, 246, 4, 76, // Opcode: CNTD_XPiI /* 10909 */ MCD_OPC_FilterValue, 1, 2, 41, 1, // Skip to: 86948 /* 10914 */ MCD_OPC_CheckPredicate, 0, 253, 40, 1, // Skip to: 86948 /* 10919 */ MCD_OPC_Decode, 245, 13, 77, // Opcode: INCD_XPiI /* 10923 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10944 /* 10928 */ MCD_OPC_CheckPredicate, 0, 239, 40, 1, // Skip to: 86948 /* 10933 */ MCD_OPC_CheckField, 20, 1, 1, 232, 40, 1, // Skip to: 86948 /* 10940 */ MCD_OPC_Decode, 178, 5, 77, // Opcode: DECD_XPiI /* 10944 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10980 /* 10949 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10952 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10966 /* 10957 */ MCD_OPC_CheckPredicate, 0, 210, 40, 1, // Skip to: 86948 /* 10962 */ MCD_OPC_Decode, 128, 25, 77, // Opcode: SQINCD_XPiWdI /* 10966 */ MCD_OPC_FilterValue, 1, 201, 40, 1, // Skip to: 86948 /* 10971 */ MCD_OPC_CheckPredicate, 0, 196, 40, 1, // Skip to: 86948 /* 10976 */ MCD_OPC_Decode, 255, 24, 77, // Opcode: SQINCD_XPiI /* 10980 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 11016 /* 10985 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 10988 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11002 /* 10993 */ MCD_OPC_CheckPredicate, 0, 174, 40, 1, // Skip to: 86948 /* 10998 */ MCD_OPC_Decode, 246, 32, 78, // Opcode: UQINCD_WPiI /* 11002 */ MCD_OPC_FilterValue, 1, 165, 40, 1, // Skip to: 86948 /* 11007 */ MCD_OPC_CheckPredicate, 0, 160, 40, 1, // Skip to: 86948 /* 11012 */ MCD_OPC_Decode, 247, 32, 77, // Opcode: UQINCD_XPiI /* 11016 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11052 /* 11021 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 11024 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11038 /* 11029 */ MCD_OPC_CheckPredicate, 0, 138, 40, 1, // Skip to: 86948 /* 11034 */ MCD_OPC_Decode, 186, 24, 77, // Opcode: SQDECD_XPiWdI /* 11038 */ MCD_OPC_FilterValue, 1, 129, 40, 1, // Skip to: 86948 /* 11043 */ MCD_OPC_CheckPredicate, 0, 124, 40, 1, // Skip to: 86948 /* 11048 */ MCD_OPC_Decode, 185, 24, 77, // Opcode: SQDECD_XPiI /* 11052 */ MCD_OPC_FilterValue, 15, 115, 40, 1, // Skip to: 86948 /* 11057 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 11060 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11074 /* 11065 */ MCD_OPC_CheckPredicate, 0, 102, 40, 1, // Skip to: 86948 /* 11070 */ MCD_OPC_Decode, 224, 32, 78, // Opcode: UQDECD_WPiI /* 11074 */ MCD_OPC_FilterValue, 1, 93, 40, 1, // Skip to: 86948 /* 11079 */ MCD_OPC_CheckPredicate, 0, 88, 40, 1, // Skip to: 86948 /* 11084 */ MCD_OPC_Decode, 225, 32, 77, // Opcode: UQDECD_XPiI /* 11088 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 11102 /* 11093 */ MCD_OPC_CheckPredicate, 0, 74, 40, 1, // Skip to: 86948 /* 11098 */ MCD_OPC_Decode, 234, 22, 80, // Opcode: SEL_ZPZZ_B /* 11102 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 11116 /* 11107 */ MCD_OPC_CheckPredicate, 0, 60, 40, 1, // Skip to: 86948 /* 11112 */ MCD_OPC_Decode, 236, 22, 80, // Opcode: SEL_ZPZZ_H /* 11116 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 11130 /* 11121 */ MCD_OPC_CheckPredicate, 0, 46, 40, 1, // Skip to: 86948 /* 11126 */ MCD_OPC_Decode, 237, 22, 80, // Opcode: SEL_ZPZZ_S /* 11130 */ MCD_OPC_FilterValue, 7, 37, 40, 1, // Skip to: 86948 /* 11135 */ MCD_OPC_CheckPredicate, 0, 32, 40, 1, // Skip to: 86948 /* 11140 */ MCD_OPC_Decode, 235, 22, 80, // Opcode: SEL_ZPZZ_D /* 11144 */ MCD_OPC_FilterValue, 1, 8, 23, 0, // Skip to: 17045 /* 11149 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 11152 */ MCD_OPC_FilterValue, 0, 35, 1, 0, // Skip to: 11448 /* 11157 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 11160 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11196 /* 11165 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11182 /* 11173 */ MCD_OPC_CheckPredicate, 0, 250, 39, 1, // Skip to: 86948 /* 11178 */ MCD_OPC_Decode, 182, 4, 81, // Opcode: CMPHS_PPzZZ_B /* 11182 */ MCD_OPC_FilterValue, 1, 241, 39, 1, // Skip to: 86948 /* 11187 */ MCD_OPC_CheckPredicate, 0, 236, 39, 1, // Skip to: 86948 /* 11192 */ MCD_OPC_Decode, 171, 4, 81, // Opcode: CMPHI_PPzZZ_B /* 11196 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11232 /* 11201 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11204 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11218 /* 11209 */ MCD_OPC_CheckPredicate, 0, 214, 39, 1, // Skip to: 86948 /* 11214 */ MCD_OPC_Decode, 142, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_B /* 11218 */ MCD_OPC_FilterValue, 1, 205, 39, 1, // Skip to: 86948 /* 11223 */ MCD_OPC_CheckPredicate, 0, 200, 39, 1, // Skip to: 86948 /* 11228 */ MCD_OPC_Decode, 225, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_B /* 11232 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 11268 /* 11237 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11240 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11254 /* 11245 */ MCD_OPC_CheckPredicate, 0, 178, 39, 1, // Skip to: 86948 /* 11250 */ MCD_OPC_Decode, 153, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_B /* 11254 */ MCD_OPC_FilterValue, 1, 169, 39, 1, // Skip to: 86948 /* 11259 */ MCD_OPC_CheckPredicate, 0, 164, 39, 1, // Skip to: 86948 /* 11264 */ MCD_OPC_Decode, 164, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_B /* 11268 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 11304 /* 11273 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11290 /* 11281 */ MCD_OPC_CheckPredicate, 0, 142, 39, 1, // Skip to: 86948 /* 11286 */ MCD_OPC_Decode, 214, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_B /* 11290 */ MCD_OPC_FilterValue, 1, 133, 39, 1, // Skip to: 86948 /* 11295 */ MCD_OPC_CheckPredicate, 0, 128, 39, 1, // Skip to: 86948 /* 11300 */ MCD_OPC_Decode, 193, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_B /* 11304 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 11340 /* 11309 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11312 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11326 /* 11317 */ MCD_OPC_CheckPredicate, 0, 106, 39, 1, // Skip to: 86948 /* 11322 */ MCD_OPC_Decode, 149, 4, 81, // Opcode: CMPGE_PPzZZ_B /* 11326 */ MCD_OPC_FilterValue, 1, 97, 39, 1, // Skip to: 86948 /* 11331 */ MCD_OPC_CheckPredicate, 0, 92, 39, 1, // Skip to: 86948 /* 11336 */ MCD_OPC_Decode, 160, 4, 81, // Opcode: CMPGT_PPzZZ_B /* 11340 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 11376 /* 11345 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11348 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11362 /* 11353 */ MCD_OPC_CheckPredicate, 0, 70, 39, 1, // Skip to: 86948 /* 11358 */ MCD_OPC_Decode, 138, 4, 81, // Opcode: CMPEQ_PPzZZ_B /* 11362 */ MCD_OPC_FilterValue, 1, 61, 39, 1, // Skip to: 86948 /* 11367 */ MCD_OPC_CheckPredicate, 0, 56, 39, 1, // Skip to: 86948 /* 11372 */ MCD_OPC_Decode, 221, 4, 81, // Opcode: CMPNE_PPzZZ_B /* 11376 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 11412 /* 11381 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11384 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11398 /* 11389 */ MCD_OPC_CheckPredicate, 0, 34, 39, 1, // Skip to: 86948 /* 11394 */ MCD_OPC_Decode, 186, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_B /* 11398 */ MCD_OPC_FilterValue, 1, 25, 39, 1, // Skip to: 86948 /* 11403 */ MCD_OPC_CheckPredicate, 0, 20, 39, 1, // Skip to: 86948 /* 11408 */ MCD_OPC_Decode, 175, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_B /* 11412 */ MCD_OPC_FilterValue, 7, 11, 39, 1, // Skip to: 86948 /* 11417 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11420 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11434 /* 11425 */ MCD_OPC_CheckPredicate, 0, 254, 38, 1, // Skip to: 86948 /* 11430 */ MCD_OPC_Decode, 200, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_B /* 11434 */ MCD_OPC_FilterValue, 1, 245, 38, 1, // Skip to: 86948 /* 11439 */ MCD_OPC_CheckPredicate, 0, 240, 38, 1, // Skip to: 86948 /* 11444 */ MCD_OPC_Decode, 207, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_B /* 11448 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 11528 /* 11453 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11456 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11492 /* 11461 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 11464 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11478 /* 11469 */ MCD_OPC_CheckPredicate, 0, 210, 38, 1, // Skip to: 86948 /* 11474 */ MCD_OPC_Decode, 178, 4, 82, // Opcode: CMPHS_PPzZI_B /* 11478 */ MCD_OPC_FilterValue, 1, 201, 38, 1, // Skip to: 86948 /* 11483 */ MCD_OPC_CheckPredicate, 0, 196, 38, 1, // Skip to: 86948 /* 11488 */ MCD_OPC_Decode, 196, 4, 82, // Opcode: CMPLO_PPzZI_B /* 11492 */ MCD_OPC_FilterValue, 1, 187, 38, 1, // Skip to: 86948 /* 11497 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 11500 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11514 /* 11505 */ MCD_OPC_CheckPredicate, 0, 174, 38, 1, // Skip to: 86948 /* 11510 */ MCD_OPC_Decode, 167, 4, 82, // Opcode: CMPHI_PPzZI_B /* 11514 */ MCD_OPC_FilterValue, 1, 165, 38, 1, // Skip to: 86948 /* 11519 */ MCD_OPC_CheckPredicate, 0, 160, 38, 1, // Skip to: 86948 /* 11524 */ MCD_OPC_Decode, 203, 4, 82, // Opcode: CMPLS_PPzZI_B /* 11528 */ MCD_OPC_FilterValue, 2, 35, 1, 0, // Skip to: 11824 /* 11533 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 11536 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11572 /* 11541 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11544 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11558 /* 11549 */ MCD_OPC_CheckPredicate, 0, 130, 38, 1, // Skip to: 86948 /* 11554 */ MCD_OPC_Decode, 184, 4, 81, // Opcode: CMPHS_PPzZZ_H /* 11558 */ MCD_OPC_FilterValue, 1, 121, 38, 1, // Skip to: 86948 /* 11563 */ MCD_OPC_CheckPredicate, 0, 116, 38, 1, // Skip to: 86948 /* 11568 */ MCD_OPC_Decode, 173, 4, 81, // Opcode: CMPHI_PPzZZ_H /* 11572 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11608 /* 11577 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11580 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11594 /* 11585 */ MCD_OPC_CheckPredicate, 0, 94, 38, 1, // Skip to: 86948 /* 11590 */ MCD_OPC_Decode, 143, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_H /* 11594 */ MCD_OPC_FilterValue, 1, 85, 38, 1, // Skip to: 86948 /* 11599 */ MCD_OPC_CheckPredicate, 0, 80, 38, 1, // Skip to: 86948 /* 11604 */ MCD_OPC_Decode, 226, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_H /* 11608 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 11644 /* 11613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11616 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11630 /* 11621 */ MCD_OPC_CheckPredicate, 0, 58, 38, 1, // Skip to: 86948 /* 11626 */ MCD_OPC_Decode, 154, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_H /* 11630 */ MCD_OPC_FilterValue, 1, 49, 38, 1, // Skip to: 86948 /* 11635 */ MCD_OPC_CheckPredicate, 0, 44, 38, 1, // Skip to: 86948 /* 11640 */ MCD_OPC_Decode, 165, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_H /* 11644 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 11680 /* 11649 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11652 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11666 /* 11657 */ MCD_OPC_CheckPredicate, 0, 22, 38, 1, // Skip to: 86948 /* 11662 */ MCD_OPC_Decode, 215, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_H /* 11666 */ MCD_OPC_FilterValue, 1, 13, 38, 1, // Skip to: 86948 /* 11671 */ MCD_OPC_CheckPredicate, 0, 8, 38, 1, // Skip to: 86948 /* 11676 */ MCD_OPC_Decode, 194, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_H /* 11680 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 11716 /* 11685 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11688 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11702 /* 11693 */ MCD_OPC_CheckPredicate, 0, 242, 37, 1, // Skip to: 86948 /* 11698 */ MCD_OPC_Decode, 151, 4, 81, // Opcode: CMPGE_PPzZZ_H /* 11702 */ MCD_OPC_FilterValue, 1, 233, 37, 1, // Skip to: 86948 /* 11707 */ MCD_OPC_CheckPredicate, 0, 228, 37, 1, // Skip to: 86948 /* 11712 */ MCD_OPC_Decode, 162, 4, 81, // Opcode: CMPGT_PPzZZ_H /* 11716 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 11752 /* 11721 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11738 /* 11729 */ MCD_OPC_CheckPredicate, 0, 206, 37, 1, // Skip to: 86948 /* 11734 */ MCD_OPC_Decode, 140, 4, 81, // Opcode: CMPEQ_PPzZZ_H /* 11738 */ MCD_OPC_FilterValue, 1, 197, 37, 1, // Skip to: 86948 /* 11743 */ MCD_OPC_CheckPredicate, 0, 192, 37, 1, // Skip to: 86948 /* 11748 */ MCD_OPC_Decode, 223, 4, 81, // Opcode: CMPNE_PPzZZ_H /* 11752 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 11788 /* 11757 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11760 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11774 /* 11765 */ MCD_OPC_CheckPredicate, 0, 170, 37, 1, // Skip to: 86948 /* 11770 */ MCD_OPC_Decode, 187, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_H /* 11774 */ MCD_OPC_FilterValue, 1, 161, 37, 1, // Skip to: 86948 /* 11779 */ MCD_OPC_CheckPredicate, 0, 156, 37, 1, // Skip to: 86948 /* 11784 */ MCD_OPC_Decode, 176, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_H /* 11788 */ MCD_OPC_FilterValue, 7, 147, 37, 1, // Skip to: 86948 /* 11793 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11796 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11810 /* 11801 */ MCD_OPC_CheckPredicate, 0, 134, 37, 1, // Skip to: 86948 /* 11806 */ MCD_OPC_Decode, 201, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_H /* 11810 */ MCD_OPC_FilterValue, 1, 125, 37, 1, // Skip to: 86948 /* 11815 */ MCD_OPC_CheckPredicate, 0, 120, 37, 1, // Skip to: 86948 /* 11820 */ MCD_OPC_Decode, 208, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_H /* 11824 */ MCD_OPC_FilterValue, 3, 75, 0, 0, // Skip to: 11904 /* 11829 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11832 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11868 /* 11837 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 11840 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11854 /* 11845 */ MCD_OPC_CheckPredicate, 0, 90, 37, 1, // Skip to: 86948 /* 11850 */ MCD_OPC_Decode, 180, 4, 82, // Opcode: CMPHS_PPzZI_H /* 11854 */ MCD_OPC_FilterValue, 1, 81, 37, 1, // Skip to: 86948 /* 11859 */ MCD_OPC_CheckPredicate, 0, 76, 37, 1, // Skip to: 86948 /* 11864 */ MCD_OPC_Decode, 198, 4, 82, // Opcode: CMPLO_PPzZI_H /* 11868 */ MCD_OPC_FilterValue, 1, 67, 37, 1, // Skip to: 86948 /* 11873 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 11876 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11890 /* 11881 */ MCD_OPC_CheckPredicate, 0, 54, 37, 1, // Skip to: 86948 /* 11886 */ MCD_OPC_Decode, 169, 4, 82, // Opcode: CMPHI_PPzZI_H /* 11890 */ MCD_OPC_FilterValue, 1, 45, 37, 1, // Skip to: 86948 /* 11895 */ MCD_OPC_CheckPredicate, 0, 40, 37, 1, // Skip to: 86948 /* 11900 */ MCD_OPC_Decode, 205, 4, 82, // Opcode: CMPLS_PPzZI_H /* 11904 */ MCD_OPC_FilterValue, 4, 35, 1, 0, // Skip to: 12200 /* 11909 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 11912 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11948 /* 11917 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11920 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11934 /* 11925 */ MCD_OPC_CheckPredicate, 0, 10, 37, 1, // Skip to: 86948 /* 11930 */ MCD_OPC_Decode, 185, 4, 81, // Opcode: CMPHS_PPzZZ_S /* 11934 */ MCD_OPC_FilterValue, 1, 1, 37, 1, // Skip to: 86948 /* 11939 */ MCD_OPC_CheckPredicate, 0, 252, 36, 1, // Skip to: 86948 /* 11944 */ MCD_OPC_Decode, 174, 4, 81, // Opcode: CMPHI_PPzZZ_S /* 11948 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11984 /* 11953 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11956 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11970 /* 11961 */ MCD_OPC_CheckPredicate, 0, 230, 36, 1, // Skip to: 86948 /* 11966 */ MCD_OPC_Decode, 144, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_S /* 11970 */ MCD_OPC_FilterValue, 1, 221, 36, 1, // Skip to: 86948 /* 11975 */ MCD_OPC_CheckPredicate, 0, 216, 36, 1, // Skip to: 86948 /* 11980 */ MCD_OPC_Decode, 227, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_S /* 11984 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 12020 /* 11989 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 11992 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12006 /* 11997 */ MCD_OPC_CheckPredicate, 0, 194, 36, 1, // Skip to: 86948 /* 12002 */ MCD_OPC_Decode, 155, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_S /* 12006 */ MCD_OPC_FilterValue, 1, 185, 36, 1, // Skip to: 86948 /* 12011 */ MCD_OPC_CheckPredicate, 0, 180, 36, 1, // Skip to: 86948 /* 12016 */ MCD_OPC_Decode, 166, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_S /* 12020 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 12056 /* 12025 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12028 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12042 /* 12033 */ MCD_OPC_CheckPredicate, 0, 158, 36, 1, // Skip to: 86948 /* 12038 */ MCD_OPC_Decode, 216, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_S /* 12042 */ MCD_OPC_FilterValue, 1, 149, 36, 1, // Skip to: 86948 /* 12047 */ MCD_OPC_CheckPredicate, 0, 144, 36, 1, // Skip to: 86948 /* 12052 */ MCD_OPC_Decode, 195, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_S /* 12056 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 12092 /* 12061 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12064 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12078 /* 12069 */ MCD_OPC_CheckPredicate, 0, 122, 36, 1, // Skip to: 86948 /* 12074 */ MCD_OPC_Decode, 152, 4, 81, // Opcode: CMPGE_PPzZZ_S /* 12078 */ MCD_OPC_FilterValue, 1, 113, 36, 1, // Skip to: 86948 /* 12083 */ MCD_OPC_CheckPredicate, 0, 108, 36, 1, // Skip to: 86948 /* 12088 */ MCD_OPC_Decode, 163, 4, 81, // Opcode: CMPGT_PPzZZ_S /* 12092 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 12128 /* 12097 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12114 /* 12105 */ MCD_OPC_CheckPredicate, 0, 86, 36, 1, // Skip to: 86948 /* 12110 */ MCD_OPC_Decode, 141, 4, 81, // Opcode: CMPEQ_PPzZZ_S /* 12114 */ MCD_OPC_FilterValue, 1, 77, 36, 1, // Skip to: 86948 /* 12119 */ MCD_OPC_CheckPredicate, 0, 72, 36, 1, // Skip to: 86948 /* 12124 */ MCD_OPC_Decode, 224, 4, 81, // Opcode: CMPNE_PPzZZ_S /* 12128 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 12164 /* 12133 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12136 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12150 /* 12141 */ MCD_OPC_CheckPredicate, 0, 50, 36, 1, // Skip to: 86948 /* 12146 */ MCD_OPC_Decode, 188, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_S /* 12150 */ MCD_OPC_FilterValue, 1, 41, 36, 1, // Skip to: 86948 /* 12155 */ MCD_OPC_CheckPredicate, 0, 36, 36, 1, // Skip to: 86948 /* 12160 */ MCD_OPC_Decode, 177, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_S /* 12164 */ MCD_OPC_FilterValue, 7, 27, 36, 1, // Skip to: 86948 /* 12169 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12172 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12186 /* 12177 */ MCD_OPC_CheckPredicate, 0, 14, 36, 1, // Skip to: 86948 /* 12182 */ MCD_OPC_Decode, 202, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_S /* 12186 */ MCD_OPC_FilterValue, 1, 5, 36, 1, // Skip to: 86948 /* 12191 */ MCD_OPC_CheckPredicate, 0, 0, 36, 1, // Skip to: 86948 /* 12196 */ MCD_OPC_Decode, 209, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_S /* 12200 */ MCD_OPC_FilterValue, 5, 75, 0, 0, // Skip to: 12280 /* 12205 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12208 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12244 /* 12213 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 12216 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12230 /* 12221 */ MCD_OPC_CheckPredicate, 0, 226, 35, 1, // Skip to: 86948 /* 12226 */ MCD_OPC_Decode, 181, 4, 82, // Opcode: CMPHS_PPzZI_S /* 12230 */ MCD_OPC_FilterValue, 1, 217, 35, 1, // Skip to: 86948 /* 12235 */ MCD_OPC_CheckPredicate, 0, 212, 35, 1, // Skip to: 86948 /* 12240 */ MCD_OPC_Decode, 199, 4, 82, // Opcode: CMPLO_PPzZI_S /* 12244 */ MCD_OPC_FilterValue, 1, 203, 35, 1, // Skip to: 86948 /* 12249 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 12252 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12266 /* 12257 */ MCD_OPC_CheckPredicate, 0, 190, 35, 1, // Skip to: 86948 /* 12262 */ MCD_OPC_Decode, 170, 4, 82, // Opcode: CMPHI_PPzZI_S /* 12266 */ MCD_OPC_FilterValue, 1, 181, 35, 1, // Skip to: 86948 /* 12271 */ MCD_OPC_CheckPredicate, 0, 176, 35, 1, // Skip to: 86948 /* 12276 */ MCD_OPC_Decode, 206, 4, 82, // Opcode: CMPLS_PPzZI_S /* 12280 */ MCD_OPC_FilterValue, 6, 111, 0, 0, // Skip to: 12396 /* 12285 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 12288 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12324 /* 12293 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12296 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12310 /* 12301 */ MCD_OPC_CheckPredicate, 0, 146, 35, 1, // Skip to: 86948 /* 12306 */ MCD_OPC_Decode, 183, 4, 81, // Opcode: CMPHS_PPzZZ_D /* 12310 */ MCD_OPC_FilterValue, 1, 137, 35, 1, // Skip to: 86948 /* 12315 */ MCD_OPC_CheckPredicate, 0, 132, 35, 1, // Skip to: 86948 /* 12320 */ MCD_OPC_Decode, 172, 4, 81, // Opcode: CMPHI_PPzZZ_D /* 12324 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 12360 /* 12329 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12332 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12346 /* 12337 */ MCD_OPC_CheckPredicate, 0, 110, 35, 1, // Skip to: 86948 /* 12342 */ MCD_OPC_Decode, 150, 4, 81, // Opcode: CMPGE_PPzZZ_D /* 12346 */ MCD_OPC_FilterValue, 1, 101, 35, 1, // Skip to: 86948 /* 12351 */ MCD_OPC_CheckPredicate, 0, 96, 35, 1, // Skip to: 86948 /* 12356 */ MCD_OPC_Decode, 161, 4, 81, // Opcode: CMPGT_PPzZZ_D /* 12360 */ MCD_OPC_FilterValue, 5, 87, 35, 1, // Skip to: 86948 /* 12365 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12368 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12382 /* 12373 */ MCD_OPC_CheckPredicate, 0, 74, 35, 1, // Skip to: 86948 /* 12378 */ MCD_OPC_Decode, 139, 4, 81, // Opcode: CMPEQ_PPzZZ_D /* 12382 */ MCD_OPC_FilterValue, 1, 65, 35, 1, // Skip to: 86948 /* 12387 */ MCD_OPC_CheckPredicate, 0, 60, 35, 1, // Skip to: 86948 /* 12392 */ MCD_OPC_Decode, 222, 4, 81, // Opcode: CMPNE_PPzZZ_D /* 12396 */ MCD_OPC_FilterValue, 7, 75, 0, 0, // Skip to: 12476 /* 12401 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12404 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12440 /* 12409 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 12412 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12426 /* 12417 */ MCD_OPC_CheckPredicate, 0, 30, 35, 1, // Skip to: 86948 /* 12422 */ MCD_OPC_Decode, 179, 4, 82, // Opcode: CMPHS_PPzZI_D /* 12426 */ MCD_OPC_FilterValue, 1, 21, 35, 1, // Skip to: 86948 /* 12431 */ MCD_OPC_CheckPredicate, 0, 16, 35, 1, // Skip to: 86948 /* 12436 */ MCD_OPC_Decode, 197, 4, 82, // Opcode: CMPLO_PPzZI_D /* 12440 */ MCD_OPC_FilterValue, 1, 7, 35, 1, // Skip to: 86948 /* 12445 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 12448 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12462 /* 12453 */ MCD_OPC_CheckPredicate, 0, 250, 34, 1, // Skip to: 86948 /* 12458 */ MCD_OPC_Decode, 168, 4, 82, // Opcode: CMPHI_PPzZI_D /* 12462 */ MCD_OPC_FilterValue, 1, 241, 34, 1, // Skip to: 86948 /* 12467 */ MCD_OPC_CheckPredicate, 0, 236, 34, 1, // Skip to: 86948 /* 12472 */ MCD_OPC_Decode, 204, 4, 82, // Opcode: CMPLS_PPzZI_D /* 12476 */ MCD_OPC_FilterValue, 8, 3, 2, 0, // Skip to: 12996 /* 12481 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 12484 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 12564 /* 12489 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12492 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12528 /* 12497 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 12500 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12514 /* 12505 */ MCD_OPC_CheckPredicate, 0, 198, 34, 1, // Skip to: 86948 /* 12510 */ MCD_OPC_Decode, 145, 4, 83, // Opcode: CMPGE_PPzZI_B /* 12514 */ MCD_OPC_FilterValue, 1, 189, 34, 1, // Skip to: 86948 /* 12519 */ MCD_OPC_CheckPredicate, 0, 184, 34, 1, // Skip to: 86948 /* 12524 */ MCD_OPC_Decode, 210, 4, 83, // Opcode: CMPLT_PPzZI_B /* 12528 */ MCD_OPC_FilterValue, 1, 175, 34, 1, // Skip to: 86948 /* 12533 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 12536 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12550 /* 12541 */ MCD_OPC_CheckPredicate, 0, 162, 34, 1, // Skip to: 86948 /* 12546 */ MCD_OPC_Decode, 156, 4, 83, // Opcode: CMPGT_PPzZI_B /* 12550 */ MCD_OPC_FilterValue, 1, 153, 34, 1, // Skip to: 86948 /* 12555 */ MCD_OPC_CheckPredicate, 0, 148, 34, 1, // Skip to: 86948 /* 12560 */ MCD_OPC_Decode, 189, 4, 83, // Opcode: CMPLE_PPzZI_B /* 12564 */ MCD_OPC_FilterValue, 1, 162, 0, 0, // Skip to: 12731 /* 12569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12572 */ MCD_OPC_FilterValue, 0, 82, 0, 0, // Skip to: 12659 /* 12577 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 12580 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 12638 /* 12585 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12588 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12602 /* 12593 */ MCD_OPC_CheckPredicate, 0, 110, 34, 1, // Skip to: 86948 /* 12598 */ MCD_OPC_Decode, 245, 1, 84, // Opcode: AND_PPzPP /* 12602 */ MCD_OPC_FilterValue, 1, 101, 34, 1, // Skip to: 86948 /* 12607 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 12610 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12624 /* 12615 */ MCD_OPC_CheckPredicate, 0, 88, 34, 1, // Skip to: 86948 /* 12620 */ MCD_OPC_Decode, 211, 2, 85, // Opcode: BRKA_PPzP /* 12624 */ MCD_OPC_FilterValue, 8, 79, 34, 1, // Skip to: 86948 /* 12629 */ MCD_OPC_CheckPredicate, 0, 74, 34, 1, // Skip to: 86948 /* 12634 */ MCD_OPC_Decode, 216, 2, 86, // Opcode: BRKN_PPzP /* 12638 */ MCD_OPC_FilterValue, 1, 65, 34, 1, // Skip to: 86948 /* 12643 */ MCD_OPC_CheckPredicate, 0, 60, 34, 1, // Skip to: 86948 /* 12648 */ MCD_OPC_CheckField, 20, 1, 0, 53, 34, 1, // Skip to: 86948 /* 12655 */ MCD_OPC_Decode, 238, 5, 84, // Opcode: EOR_PPzPP /* 12659 */ MCD_OPC_FilterValue, 1, 44, 34, 1, // Skip to: 86948 /* 12664 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 12667 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 12710 /* 12672 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12675 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12689 /* 12680 */ MCD_OPC_CheckPredicate, 0, 23, 34, 1, // Skip to: 86948 /* 12685 */ MCD_OPC_Decode, 181, 2, 84, // Opcode: BIC_PPzPP /* 12689 */ MCD_OPC_FilterValue, 1, 14, 34, 1, // Skip to: 86948 /* 12694 */ MCD_OPC_CheckPredicate, 0, 9, 34, 1, // Skip to: 86948 /* 12699 */ MCD_OPC_CheckField, 16, 4, 0, 2, 34, 1, // Skip to: 86948 /* 12706 */ MCD_OPC_Decode, 210, 2, 87, // Opcode: BRKA_PPmP /* 12710 */ MCD_OPC_FilterValue, 1, 249, 33, 1, // Skip to: 86948 /* 12715 */ MCD_OPC_CheckPredicate, 0, 244, 33, 1, // Skip to: 86948 /* 12720 */ MCD_OPC_CheckField, 20, 1, 0, 237, 33, 1, // Skip to: 86948 /* 12727 */ MCD_OPC_Decode, 233, 22, 84, // Opcode: SEL_PPPP /* 12731 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 12781 /* 12736 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12739 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12760 /* 12744 */ MCD_OPC_CheckPredicate, 0, 215, 33, 1, // Skip to: 86948 /* 12749 */ MCD_OPC_CheckField, 13, 1, 0, 208, 33, 1, // Skip to: 86948 /* 12756 */ MCD_OPC_Decode, 134, 4, 83, // Opcode: CMPEQ_PPzZI_B /* 12760 */ MCD_OPC_FilterValue, 1, 199, 33, 1, // Skip to: 86948 /* 12765 */ MCD_OPC_CheckPredicate, 0, 194, 33, 1, // Skip to: 86948 /* 12770 */ MCD_OPC_CheckField, 13, 1, 0, 187, 33, 1, // Skip to: 86948 /* 12777 */ MCD_OPC_Decode, 217, 4, 83, // Opcode: CMPNE_PPzZI_B /* 12781 */ MCD_OPC_FilterValue, 3, 178, 33, 1, // Skip to: 86948 /* 12786 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 12789 */ MCD_OPC_FilterValue, 0, 174, 0, 0, // Skip to: 12968 /* 12794 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12797 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12818 /* 12802 */ MCD_OPC_CheckPredicate, 0, 157, 33, 1, // Skip to: 86948 /* 12807 */ MCD_OPC_CheckField, 9, 1, 0, 150, 33, 1, // Skip to: 86948 /* 12814 */ MCD_OPC_Decode, 218, 2, 84, // Opcode: BRKPA_PPzPP /* 12818 */ MCD_OPC_FilterValue, 1, 141, 33, 1, // Skip to: 86948 /* 12823 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 12826 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 12854 /* 12831 */ MCD_OPC_CheckPredicate, 0, 128, 33, 1, // Skip to: 86948 /* 12836 */ MCD_OPC_CheckField, 16, 4, 9, 121, 33, 1, // Skip to: 86948 /* 12843 */ MCD_OPC_CheckField, 9, 1, 0, 114, 33, 1, // Skip to: 86948 /* 12850 */ MCD_OPC_Decode, 249, 20, 88, // Opcode: PNEXT_B /* 12854 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 12890 /* 12859 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 12862 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 12876 /* 12867 */ MCD_OPC_CheckPredicate, 0, 92, 33, 1, // Skip to: 86948 /* 12872 */ MCD_OPC_Decode, 171, 21, 89, // Opcode: PTRUE_B /* 12876 */ MCD_OPC_FilterValue, 9, 83, 33, 1, // Skip to: 86948 /* 12881 */ MCD_OPC_CheckPredicate, 0, 78, 33, 1, // Skip to: 86948 /* 12886 */ MCD_OPC_Decode, 167, 21, 89, // Opcode: PTRUES_B /* 12890 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 12918 /* 12895 */ MCD_OPC_CheckPredicate, 0, 64, 33, 1, // Skip to: 86948 /* 12900 */ MCD_OPC_CheckField, 16, 4, 8, 57, 33, 1, // Skip to: 86948 /* 12907 */ MCD_OPC_CheckField, 5, 5, 0, 50, 33, 1, // Skip to: 86948 /* 12914 */ MCD_OPC_Decode, 242, 20, 90, // Opcode: PFALSE /* 12918 */ MCD_OPC_FilterValue, 12, 41, 33, 1, // Skip to: 86948 /* 12923 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 12926 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 12947 /* 12931 */ MCD_OPC_CheckPredicate, 0, 28, 33, 1, // Skip to: 86948 /* 12936 */ MCD_OPC_CheckField, 9, 1, 0, 21, 33, 1, // Skip to: 86948 /* 12943 */ MCD_OPC_Decode, 194, 21, 53, // Opcode: RDFFR_PPz /* 12947 */ MCD_OPC_FilterValue, 9, 12, 33, 1, // Skip to: 86948 /* 12952 */ MCD_OPC_CheckPredicate, 0, 7, 33, 1, // Skip to: 86948 /* 12957 */ MCD_OPC_CheckField, 5, 5, 0, 0, 33, 1, // Skip to: 86948 /* 12964 */ MCD_OPC_Decode, 193, 21, 90, // Opcode: RDFFR_P /* 12968 */ MCD_OPC_FilterValue, 1, 247, 32, 1, // Skip to: 86948 /* 12973 */ MCD_OPC_CheckPredicate, 0, 242, 32, 1, // Skip to: 86948 /* 12978 */ MCD_OPC_CheckField, 20, 1, 0, 235, 32, 1, // Skip to: 86948 /* 12985 */ MCD_OPC_CheckField, 9, 1, 0, 228, 32, 1, // Skip to: 86948 /* 12992 */ MCD_OPC_Decode, 220, 2, 84, // Opcode: BRKPB_PPzPP /* 12996 */ MCD_OPC_FilterValue, 9, 126, 2, 0, // Skip to: 13639 /* 13001 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 13004 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 13156 /* 13009 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 13012 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 13048 /* 13017 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13020 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13034 /* 13025 */ MCD_OPC_CheckPredicate, 0, 190, 32, 1, // Skip to: 86948 /* 13030 */ MCD_OPC_Decode, 242, 34, 91, // Opcode: WHILELT_PWW_B /* 13034 */ MCD_OPC_FilterValue, 1, 181, 32, 1, // Skip to: 86948 /* 13039 */ MCD_OPC_CheckPredicate, 0, 176, 32, 1, // Skip to: 86948 /* 13044 */ MCD_OPC_Decode, 218, 34, 91, // Opcode: WHILELE_PWW_B /* 13048 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 13084 /* 13053 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13056 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13070 /* 13061 */ MCD_OPC_CheckPredicate, 0, 154, 32, 1, // Skip to: 86948 /* 13066 */ MCD_OPC_Decode, 226, 34, 91, // Opcode: WHILELO_PWW_B /* 13070 */ MCD_OPC_FilterValue, 1, 145, 32, 1, // Skip to: 86948 /* 13075 */ MCD_OPC_CheckPredicate, 0, 140, 32, 1, // Skip to: 86948 /* 13080 */ MCD_OPC_Decode, 234, 34, 91, // Opcode: WHILELS_PWW_B /* 13084 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 13120 /* 13089 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13092 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13106 /* 13097 */ MCD_OPC_CheckPredicate, 0, 118, 32, 1, // Skip to: 86948 /* 13102 */ MCD_OPC_Decode, 246, 34, 92, // Opcode: WHILELT_PXX_B /* 13106 */ MCD_OPC_FilterValue, 1, 109, 32, 1, // Skip to: 86948 /* 13111 */ MCD_OPC_CheckPredicate, 0, 104, 32, 1, // Skip to: 86948 /* 13116 */ MCD_OPC_Decode, 222, 34, 92, // Opcode: WHILELE_PXX_B /* 13120 */ MCD_OPC_FilterValue, 7, 95, 32, 1, // Skip to: 86948 /* 13125 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13128 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13142 /* 13133 */ MCD_OPC_CheckPredicate, 0, 82, 32, 1, // Skip to: 86948 /* 13138 */ MCD_OPC_Decode, 230, 34, 92, // Opcode: WHILELO_PXX_B /* 13142 */ MCD_OPC_FilterValue, 1, 73, 32, 1, // Skip to: 86948 /* 13147 */ MCD_OPC_CheckPredicate, 0, 68, 32, 1, // Skip to: 86948 /* 13152 */ MCD_OPC_Decode, 238, 34, 92, // Opcode: WHILELS_PXX_B /* 13156 */ MCD_OPC_FilterValue, 2, 253, 0, 0, // Skip to: 13414 /* 13161 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 13164 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13185 /* 13169 */ MCD_OPC_CheckPredicate, 0, 46, 32, 1, // Skip to: 86948 /* 13174 */ MCD_OPC_CheckField, 9, 1, 0, 39, 32, 1, // Skip to: 86948 /* 13181 */ MCD_OPC_Decode, 248, 4, 93, // Opcode: CNTP_XPP_B /* 13185 */ MCD_OPC_FilterValue, 8, 52, 0, 0, // Skip to: 13242 /* 13190 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 13193 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13207 /* 13198 */ MCD_OPC_CheckPredicate, 0, 17, 32, 1, // Skip to: 86948 /* 13203 */ MCD_OPC_Decode, 133, 25, 94, // Opcode: SQINCP_XPWd_B /* 13207 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 13221 /* 13212 */ MCD_OPC_CheckPredicate, 0, 3, 32, 1, // Skip to: 86948 /* 13217 */ MCD_OPC_Decode, 137, 25, 94, // Opcode: SQINCP_XP_B /* 13221 */ MCD_OPC_FilterValue, 8, 250, 31, 1, // Skip to: 86948 /* 13226 */ MCD_OPC_CheckPredicate, 0, 245, 31, 1, // Skip to: 86948 /* 13231 */ MCD_OPC_CheckField, 0, 5, 0, 238, 31, 1, // Skip to: 86948 /* 13238 */ MCD_OPC_Decode, 250, 34, 95, // Opcode: WRFFR /* 13242 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 13278 /* 13247 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 13250 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13264 /* 13255 */ MCD_OPC_CheckPredicate, 0, 216, 31, 1, // Skip to: 86948 /* 13260 */ MCD_OPC_Decode, 252, 32, 96, // Opcode: UQINCP_WP_B /* 13264 */ MCD_OPC_FilterValue, 6, 207, 31, 1, // Skip to: 86948 /* 13269 */ MCD_OPC_CheckPredicate, 0, 202, 31, 1, // Skip to: 86948 /* 13274 */ MCD_OPC_Decode, 128, 33, 94, // Opcode: UQINCP_XP_B /* 13278 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 13314 /* 13283 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 13286 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13300 /* 13291 */ MCD_OPC_CheckPredicate, 0, 180, 31, 1, // Skip to: 86948 /* 13296 */ MCD_OPC_Decode, 191, 24, 94, // Opcode: SQDECP_XPWd_B /* 13300 */ MCD_OPC_FilterValue, 6, 171, 31, 1, // Skip to: 86948 /* 13305 */ MCD_OPC_CheckPredicate, 0, 166, 31, 1, // Skip to: 86948 /* 13310 */ MCD_OPC_Decode, 195, 24, 94, // Opcode: SQDECP_XP_B /* 13314 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 13350 /* 13319 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 13322 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13336 /* 13327 */ MCD_OPC_CheckPredicate, 0, 144, 31, 1, // Skip to: 86948 /* 13332 */ MCD_OPC_Decode, 230, 32, 96, // Opcode: UQDECP_WP_B /* 13336 */ MCD_OPC_FilterValue, 6, 135, 31, 1, // Skip to: 86948 /* 13341 */ MCD_OPC_CheckPredicate, 0, 130, 31, 1, // Skip to: 86948 /* 13346 */ MCD_OPC_Decode, 234, 32, 94, // Opcode: UQDECP_XP_B /* 13350 */ MCD_OPC_FilterValue, 12, 38, 0, 0, // Skip to: 13393 /* 13355 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 13358 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13372 /* 13363 */ MCD_OPC_CheckPredicate, 0, 108, 31, 1, // Skip to: 86948 /* 13368 */ MCD_OPC_Decode, 249, 13, 94, // Opcode: INCP_XP_B /* 13372 */ MCD_OPC_FilterValue, 8, 99, 31, 1, // Skip to: 86948 /* 13377 */ MCD_OPC_CheckPredicate, 0, 94, 31, 1, // Skip to: 86948 /* 13382 */ MCD_OPC_CheckField, 0, 9, 0, 87, 31, 1, // Skip to: 86948 /* 13389 */ MCD_OPC_Decode, 240, 22, 97, // Opcode: SETFFR /* 13393 */ MCD_OPC_FilterValue, 13, 78, 31, 1, // Skip to: 86948 /* 13398 */ MCD_OPC_CheckPredicate, 0, 73, 31, 1, // Skip to: 86948 /* 13403 */ MCD_OPC_CheckField, 9, 5, 4, 66, 31, 1, // Skip to: 86948 /* 13410 */ MCD_OPC_Decode, 182, 5, 94, // Opcode: DECP_XP_B /* 13414 */ MCD_OPC_FilterValue, 3, 57, 31, 1, // Skip to: 86948 /* 13419 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 13422 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13436 /* 13427 */ MCD_OPC_CheckPredicate, 0, 44, 31, 1, // Skip to: 86948 /* 13432 */ MCD_OPC_Decode, 181, 1, 98, // Opcode: ADD_ZI_B /* 13436 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 13450 /* 13441 */ MCD_OPC_CheckPredicate, 0, 30, 31, 1, // Skip to: 86948 /* 13446 */ MCD_OPC_Decode, 243, 29, 98, // Opcode: SUB_ZI_B /* 13450 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 13464 /* 13455 */ MCD_OPC_CheckPredicate, 0, 16, 31, 1, // Skip to: 86948 /* 13460 */ MCD_OPC_Decode, 217, 29, 98, // Opcode: SUBR_ZI_B /* 13464 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13478 /* 13469 */ MCD_OPC_CheckPredicate, 0, 2, 31, 1, // Skip to: 86948 /* 13474 */ MCD_OPC_Decode, 164, 24, 98, // Opcode: SQADD_ZI_B /* 13478 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 13492 /* 13483 */ MCD_OPC_CheckPredicate, 0, 244, 30, 1, // Skip to: 86948 /* 13488 */ MCD_OPC_Decode, 203, 32, 98, // Opcode: UQADD_ZI_B /* 13492 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 13506 /* 13497 */ MCD_OPC_CheckPredicate, 0, 230, 30, 1, // Skip to: 86948 /* 13502 */ MCD_OPC_Decode, 146, 26, 98, // Opcode: SQSUB_ZI_B /* 13506 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 13520 /* 13511 */ MCD_OPC_CheckPredicate, 0, 216, 30, 1, // Skip to: 86948 /* 13516 */ MCD_OPC_Decode, 189, 33, 98, // Opcode: UQSUB_ZI_B /* 13520 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 13541 /* 13525 */ MCD_OPC_CheckPredicate, 0, 202, 30, 1, // Skip to: 86948 /* 13530 */ MCD_OPC_CheckField, 13, 1, 0, 195, 30, 1, // Skip to: 86948 /* 13537 */ MCD_OPC_Decode, 192, 23, 99, // Opcode: SMAX_ZI_B /* 13541 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 13562 /* 13546 */ MCD_OPC_CheckPredicate, 0, 181, 30, 1, // Skip to: 86948 /* 13551 */ MCD_OPC_CheckField, 13, 1, 0, 174, 30, 1, // Skip to: 86948 /* 13558 */ MCD_OPC_Decode, 248, 31, 100, // Opcode: UMAX_ZI_B /* 13562 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 13583 /* 13567 */ MCD_OPC_CheckPredicate, 0, 160, 30, 1, // Skip to: 86948 /* 13572 */ MCD_OPC_CheckField, 13, 1, 0, 153, 30, 1, // Skip to: 86948 /* 13579 */ MCD_OPC_Decode, 222, 23, 99, // Opcode: SMIN_ZI_B /* 13583 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 13604 /* 13588 */ MCD_OPC_CheckPredicate, 0, 139, 30, 1, // Skip to: 86948 /* 13593 */ MCD_OPC_CheckField, 13, 1, 0, 132, 30, 1, // Skip to: 86948 /* 13600 */ MCD_OPC_Decode, 149, 32, 100, // Opcode: UMIN_ZI_B /* 13604 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 13625 /* 13609 */ MCD_OPC_CheckPredicate, 0, 118, 30, 1, // Skip to: 86948 /* 13614 */ MCD_OPC_CheckField, 13, 1, 0, 111, 30, 1, // Skip to: 86948 /* 13621 */ MCD_OPC_Decode, 149, 20, 99, // Opcode: MUL_ZI_B /* 13625 */ MCD_OPC_FilterValue, 24, 102, 30, 1, // Skip to: 86948 /* 13630 */ MCD_OPC_CheckPredicate, 0, 97, 30, 1, // Skip to: 86948 /* 13635 */ MCD_OPC_Decode, 195, 5, 101, // Opcode: DUP_ZI_B /* 13639 */ MCD_OPC_FilterValue, 10, 208, 1, 0, // Skip to: 14108 /* 13644 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 13647 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 13727 /* 13652 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13655 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 13691 /* 13660 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 13663 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13677 /* 13668 */ MCD_OPC_CheckPredicate, 0, 59, 30, 1, // Skip to: 86948 /* 13673 */ MCD_OPC_Decode, 147, 4, 83, // Opcode: CMPGE_PPzZI_H /* 13677 */ MCD_OPC_FilterValue, 1, 50, 30, 1, // Skip to: 86948 /* 13682 */ MCD_OPC_CheckPredicate, 0, 45, 30, 1, // Skip to: 86948 /* 13687 */ MCD_OPC_Decode, 212, 4, 83, // Opcode: CMPLT_PPzZI_H /* 13691 */ MCD_OPC_FilterValue, 1, 36, 30, 1, // Skip to: 86948 /* 13696 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 13699 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13713 /* 13704 */ MCD_OPC_CheckPredicate, 0, 23, 30, 1, // Skip to: 86948 /* 13709 */ MCD_OPC_Decode, 158, 4, 83, // Opcode: CMPGT_PPzZI_H /* 13713 */ MCD_OPC_FilterValue, 1, 14, 30, 1, // Skip to: 86948 /* 13718 */ MCD_OPC_CheckPredicate, 0, 9, 30, 1, // Skip to: 86948 /* 13723 */ MCD_OPC_Decode, 191, 4, 83, // Opcode: CMPLE_PPzZI_H /* 13727 */ MCD_OPC_FilterValue, 1, 118, 0, 0, // Skip to: 13850 /* 13732 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13735 */ MCD_OPC_FilterValue, 0, 82, 0, 0, // Skip to: 13822 /* 13740 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 13743 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 13801 /* 13748 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13765 /* 13756 */ MCD_OPC_CheckPredicate, 0, 227, 29, 1, // Skip to: 86948 /* 13761 */ MCD_OPC_Decode, 234, 1, 84, // Opcode: ANDS_PPzPP /* 13765 */ MCD_OPC_FilterValue, 1, 218, 29, 1, // Skip to: 86948 /* 13770 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 13773 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13787 /* 13778 */ MCD_OPC_CheckPredicate, 0, 205, 29, 1, // Skip to: 86948 /* 13783 */ MCD_OPC_Decode, 209, 2, 85, // Opcode: BRKAS_PPzP /* 13787 */ MCD_OPC_FilterValue, 8, 196, 29, 1, // Skip to: 86948 /* 13792 */ MCD_OPC_CheckPredicate, 0, 191, 29, 1, // Skip to: 86948 /* 13797 */ MCD_OPC_Decode, 215, 2, 86, // Opcode: BRKNS_PPzP /* 13801 */ MCD_OPC_FilterValue, 1, 182, 29, 1, // Skip to: 86948 /* 13806 */ MCD_OPC_CheckPredicate, 0, 177, 29, 1, // Skip to: 86948 /* 13811 */ MCD_OPC_CheckField, 20, 1, 0, 170, 29, 1, // Skip to: 86948 /* 13818 */ MCD_OPC_Decode, 227, 5, 84, // Opcode: EORS_PPzPP /* 13822 */ MCD_OPC_FilterValue, 1, 161, 29, 1, // Skip to: 86948 /* 13827 */ MCD_OPC_CheckPredicate, 0, 156, 29, 1, // Skip to: 86948 /* 13832 */ MCD_OPC_CheckField, 20, 1, 0, 149, 29, 1, // Skip to: 86948 /* 13839 */ MCD_OPC_CheckField, 9, 1, 0, 142, 29, 1, // Skip to: 86948 /* 13846 */ MCD_OPC_Decode, 176, 2, 84, // Opcode: BICS_PPzPP /* 13850 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 13900 /* 13855 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13858 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13879 /* 13863 */ MCD_OPC_CheckPredicate, 0, 120, 29, 1, // Skip to: 86948 /* 13868 */ MCD_OPC_CheckField, 13, 1, 0, 113, 29, 1, // Skip to: 86948 /* 13875 */ MCD_OPC_Decode, 136, 4, 83, // Opcode: CMPEQ_PPzZI_H /* 13879 */ MCD_OPC_FilterValue, 1, 104, 29, 1, // Skip to: 86948 /* 13884 */ MCD_OPC_CheckPredicate, 0, 99, 29, 1, // Skip to: 86948 /* 13889 */ MCD_OPC_CheckField, 13, 1, 0, 92, 29, 1, // Skip to: 86948 /* 13896 */ MCD_OPC_Decode, 219, 4, 83, // Opcode: CMPNE_PPzZI_H /* 13900 */ MCD_OPC_FilterValue, 3, 83, 29, 1, // Skip to: 86948 /* 13905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 13908 */ MCD_OPC_FilterValue, 0, 167, 0, 0, // Skip to: 14080 /* 13913 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13916 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13937 /* 13921 */ MCD_OPC_CheckPredicate, 0, 62, 29, 1, // Skip to: 86948 /* 13926 */ MCD_OPC_CheckField, 9, 1, 0, 55, 29, 1, // Skip to: 86948 /* 13933 */ MCD_OPC_Decode, 217, 2, 84, // Opcode: BRKPAS_PPzPP /* 13937 */ MCD_OPC_FilterValue, 1, 46, 29, 1, // Skip to: 86948 /* 13942 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 13945 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13973 /* 13950 */ MCD_OPC_CheckPredicate, 0, 33, 29, 1, // Skip to: 86948 /* 13955 */ MCD_OPC_CheckField, 9, 1, 0, 26, 29, 1, // Skip to: 86948 /* 13962 */ MCD_OPC_CheckField, 0, 4, 0, 19, 29, 1, // Skip to: 86948 /* 13969 */ MCD_OPC_Decode, 166, 21, 102, // Opcode: PTEST_PP /* 13973 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 14037 /* 13978 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 13981 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14002 /* 13986 */ MCD_OPC_CheckPredicate, 0, 253, 28, 1, // Skip to: 86948 /* 13991 */ MCD_OPC_CheckField, 9, 1, 0, 246, 28, 1, // Skip to: 86948 /* 13998 */ MCD_OPC_Decode, 163, 35, 88, // Opcode: anonymous_1349 /* 14002 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 14016 /* 14007 */ MCD_OPC_CheckPredicate, 0, 232, 28, 1, // Skip to: 86948 /* 14012 */ MCD_OPC_Decode, 173, 21, 89, // Opcode: PTRUE_H /* 14016 */ MCD_OPC_FilterValue, 12, 223, 28, 1, // Skip to: 86948 /* 14021 */ MCD_OPC_CheckPredicate, 0, 218, 28, 1, // Skip to: 86948 /* 14026 */ MCD_OPC_CheckField, 9, 1, 0, 211, 28, 1, // Skip to: 86948 /* 14033 */ MCD_OPC_Decode, 192, 21, 53, // Opcode: RDFFRS_PPz /* 14037 */ MCD_OPC_FilterValue, 9, 202, 28, 1, // Skip to: 86948 /* 14042 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 14045 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 14066 /* 14050 */ MCD_OPC_CheckPredicate, 0, 189, 28, 1, // Skip to: 86948 /* 14055 */ MCD_OPC_CheckField, 9, 1, 0, 182, 28, 1, // Skip to: 86948 /* 14062 */ MCD_OPC_Decode, 251, 20, 88, // Opcode: PNEXT_H /* 14066 */ MCD_OPC_FilterValue, 8, 173, 28, 1, // Skip to: 86948 /* 14071 */ MCD_OPC_CheckPredicate, 0, 168, 28, 1, // Skip to: 86948 /* 14076 */ MCD_OPC_Decode, 169, 21, 89, // Opcode: PTRUES_H /* 14080 */ MCD_OPC_FilterValue, 1, 159, 28, 1, // Skip to: 86948 /* 14085 */ MCD_OPC_CheckPredicate, 0, 154, 28, 1, // Skip to: 86948 /* 14090 */ MCD_OPC_CheckField, 20, 1, 0, 147, 28, 1, // Skip to: 86948 /* 14097 */ MCD_OPC_CheckField, 9, 1, 0, 140, 28, 1, // Skip to: 86948 /* 14104 */ MCD_OPC_Decode, 219, 2, 84, // Opcode: BRKPBS_PPzPP /* 14108 */ MCD_OPC_FilterValue, 11, 190, 2, 0, // Skip to: 14815 /* 14113 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 14116 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 14268 /* 14121 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 14124 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 14160 /* 14129 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 14132 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14146 /* 14137 */ MCD_OPC_CheckPredicate, 0, 102, 28, 1, // Skip to: 86948 /* 14142 */ MCD_OPC_Decode, 244, 34, 91, // Opcode: WHILELT_PWW_H /* 14146 */ MCD_OPC_FilterValue, 1, 93, 28, 1, // Skip to: 86948 /* 14151 */ MCD_OPC_CheckPredicate, 0, 88, 28, 1, // Skip to: 86948 /* 14156 */ MCD_OPC_Decode, 220, 34, 91, // Opcode: WHILELE_PWW_H /* 14160 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 14196 /* 14165 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 14168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14182 /* 14173 */ MCD_OPC_CheckPredicate, 0, 66, 28, 1, // Skip to: 86948 /* 14178 */ MCD_OPC_Decode, 228, 34, 91, // Opcode: WHILELO_PWW_H /* 14182 */ MCD_OPC_FilterValue, 1, 57, 28, 1, // Skip to: 86948 /* 14187 */ MCD_OPC_CheckPredicate, 0, 52, 28, 1, // Skip to: 86948 /* 14192 */ MCD_OPC_Decode, 236, 34, 91, // Opcode: WHILELS_PWW_H /* 14196 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 14232 /* 14201 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 14204 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14218 /* 14209 */ MCD_OPC_CheckPredicate, 0, 30, 28, 1, // Skip to: 86948 /* 14214 */ MCD_OPC_Decode, 248, 34, 92, // Opcode: WHILELT_PXX_H /* 14218 */ MCD_OPC_FilterValue, 1, 21, 28, 1, // Skip to: 86948 /* 14223 */ MCD_OPC_CheckPredicate, 0, 16, 28, 1, // Skip to: 86948 /* 14228 */ MCD_OPC_Decode, 224, 34, 92, // Opcode: WHILELE_PXX_H /* 14232 */ MCD_OPC_FilterValue, 7, 7, 28, 1, // Skip to: 86948 /* 14237 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 14240 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14254 /* 14245 */ MCD_OPC_CheckPredicate, 0, 250, 27, 1, // Skip to: 86948 /* 14250 */ MCD_OPC_Decode, 232, 34, 92, // Opcode: WHILELO_PXX_H /* 14254 */ MCD_OPC_FilterValue, 1, 241, 27, 1, // Skip to: 86948 /* 14259 */ MCD_OPC_CheckPredicate, 0, 236, 27, 1, // Skip to: 86948 /* 14264 */ MCD_OPC_Decode, 240, 34, 92, // Opcode: WHILELS_PXX_H /* 14268 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 14569 /* 14273 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 14276 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14297 /* 14281 */ MCD_OPC_CheckPredicate, 0, 214, 27, 1, // Skip to: 86948 /* 14286 */ MCD_OPC_CheckField, 9, 1, 0, 207, 27, 1, // Skip to: 86948 /* 14293 */ MCD_OPC_Decode, 250, 4, 93, // Opcode: CNTP_XPP_H /* 14297 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 14347 /* 14302 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 14305 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14319 /* 14310 */ MCD_OPC_CheckPredicate, 0, 185, 27, 1, // Skip to: 86948 /* 14315 */ MCD_OPC_Decode, 142, 25, 103, // Opcode: SQINCP_ZP_H /* 14319 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14333 /* 14324 */ MCD_OPC_CheckPredicate, 0, 171, 27, 1, // Skip to: 86948 /* 14329 */ MCD_OPC_Decode, 135, 25, 94, // Opcode: SQINCP_XPWd_H /* 14333 */ MCD_OPC_FilterValue, 6, 162, 27, 1, // Skip to: 86948 /* 14338 */ MCD_OPC_CheckPredicate, 0, 157, 27, 1, // Skip to: 86948 /* 14343 */ MCD_OPC_Decode, 139, 25, 94, // Opcode: SQINCP_XP_H /* 14347 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 14397 /* 14352 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 14355 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14369 /* 14360 */ MCD_OPC_CheckPredicate, 0, 135, 27, 1, // Skip to: 86948 /* 14365 */ MCD_OPC_Decode, 133, 33, 103, // Opcode: UQINCP_ZP_H /* 14369 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14383 /* 14374 */ MCD_OPC_CheckPredicate, 0, 121, 27, 1, // Skip to: 86948 /* 14379 */ MCD_OPC_Decode, 254, 32, 96, // Opcode: UQINCP_WP_H /* 14383 */ MCD_OPC_FilterValue, 6, 112, 27, 1, // Skip to: 86948 /* 14388 */ MCD_OPC_CheckPredicate, 0, 107, 27, 1, // Skip to: 86948 /* 14393 */ MCD_OPC_Decode, 130, 33, 94, // Opcode: UQINCP_XP_H /* 14397 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 14447 /* 14402 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 14405 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14419 /* 14410 */ MCD_OPC_CheckPredicate, 0, 85, 27, 1, // Skip to: 86948 /* 14415 */ MCD_OPC_Decode, 200, 24, 103, // Opcode: SQDECP_ZP_H /* 14419 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14433 /* 14424 */ MCD_OPC_CheckPredicate, 0, 71, 27, 1, // Skip to: 86948 /* 14429 */ MCD_OPC_Decode, 193, 24, 94, // Opcode: SQDECP_XPWd_H /* 14433 */ MCD_OPC_FilterValue, 6, 62, 27, 1, // Skip to: 86948 /* 14438 */ MCD_OPC_CheckPredicate, 0, 57, 27, 1, // Skip to: 86948 /* 14443 */ MCD_OPC_Decode, 197, 24, 94, // Opcode: SQDECP_XP_H /* 14447 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 14497 /* 14452 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 14455 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14469 /* 14460 */ MCD_OPC_CheckPredicate, 0, 35, 27, 1, // Skip to: 86948 /* 14465 */ MCD_OPC_Decode, 239, 32, 103, // Opcode: UQDECP_ZP_H /* 14469 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14483 /* 14474 */ MCD_OPC_CheckPredicate, 0, 21, 27, 1, // Skip to: 86948 /* 14479 */ MCD_OPC_Decode, 232, 32, 96, // Opcode: UQDECP_WP_H /* 14483 */ MCD_OPC_FilterValue, 6, 12, 27, 1, // Skip to: 86948 /* 14488 */ MCD_OPC_CheckPredicate, 0, 7, 27, 1, // Skip to: 86948 /* 14493 */ MCD_OPC_Decode, 236, 32, 94, // Opcode: UQDECP_XP_H /* 14497 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 14533 /* 14502 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 14505 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14519 /* 14510 */ MCD_OPC_CheckPredicate, 0, 241, 26, 1, // Skip to: 86948 /* 14515 */ MCD_OPC_Decode, 254, 13, 103, // Opcode: INCP_ZP_H /* 14519 */ MCD_OPC_FilterValue, 4, 232, 26, 1, // Skip to: 86948 /* 14524 */ MCD_OPC_CheckPredicate, 0, 227, 26, 1, // Skip to: 86948 /* 14529 */ MCD_OPC_Decode, 251, 13, 94, // Opcode: INCP_XP_H /* 14533 */ MCD_OPC_FilterValue, 13, 218, 26, 1, // Skip to: 86948 /* 14538 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 14541 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14555 /* 14546 */ MCD_OPC_CheckPredicate, 0, 205, 26, 1, // Skip to: 86948 /* 14551 */ MCD_OPC_Decode, 187, 5, 103, // Opcode: DECP_ZP_H /* 14555 */ MCD_OPC_FilterValue, 4, 196, 26, 1, // Skip to: 86948 /* 14560 */ MCD_OPC_CheckPredicate, 0, 191, 26, 1, // Skip to: 86948 /* 14565 */ MCD_OPC_Decode, 184, 5, 94, // Opcode: DECP_XP_H /* 14569 */ MCD_OPC_FilterValue, 3, 182, 26, 1, // Skip to: 86948 /* 14574 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 14577 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14591 /* 14582 */ MCD_OPC_CheckPredicate, 0, 169, 26, 1, // Skip to: 86948 /* 14587 */ MCD_OPC_Decode, 183, 1, 104, // Opcode: ADD_ZI_H /* 14591 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 14605 /* 14596 */ MCD_OPC_CheckPredicate, 0, 155, 26, 1, // Skip to: 86948 /* 14601 */ MCD_OPC_Decode, 245, 29, 104, // Opcode: SUB_ZI_H /* 14605 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 14619 /* 14610 */ MCD_OPC_CheckPredicate, 0, 141, 26, 1, // Skip to: 86948 /* 14615 */ MCD_OPC_Decode, 219, 29, 104, // Opcode: SUBR_ZI_H /* 14619 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14633 /* 14624 */ MCD_OPC_CheckPredicate, 0, 127, 26, 1, // Skip to: 86948 /* 14629 */ MCD_OPC_Decode, 166, 24, 104, // Opcode: SQADD_ZI_H /* 14633 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 14647 /* 14638 */ MCD_OPC_CheckPredicate, 0, 113, 26, 1, // Skip to: 86948 /* 14643 */ MCD_OPC_Decode, 205, 32, 104, // Opcode: UQADD_ZI_H /* 14647 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 14661 /* 14652 */ MCD_OPC_CheckPredicate, 0, 99, 26, 1, // Skip to: 86948 /* 14657 */ MCD_OPC_Decode, 148, 26, 104, // Opcode: SQSUB_ZI_H /* 14661 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 14675 /* 14666 */ MCD_OPC_CheckPredicate, 0, 85, 26, 1, // Skip to: 86948 /* 14671 */ MCD_OPC_Decode, 191, 33, 104, // Opcode: UQSUB_ZI_H /* 14675 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 14696 /* 14680 */ MCD_OPC_CheckPredicate, 0, 71, 26, 1, // Skip to: 86948 /* 14685 */ MCD_OPC_CheckField, 13, 1, 0, 64, 26, 1, // Skip to: 86948 /* 14692 */ MCD_OPC_Decode, 194, 23, 99, // Opcode: SMAX_ZI_H /* 14696 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 14717 /* 14701 */ MCD_OPC_CheckPredicate, 0, 50, 26, 1, // Skip to: 86948 /* 14706 */ MCD_OPC_CheckField, 13, 1, 0, 43, 26, 1, // Skip to: 86948 /* 14713 */ MCD_OPC_Decode, 250, 31, 100, // Opcode: UMAX_ZI_H /* 14717 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 14738 /* 14722 */ MCD_OPC_CheckPredicate, 0, 29, 26, 1, // Skip to: 86948 /* 14727 */ MCD_OPC_CheckField, 13, 1, 0, 22, 26, 1, // Skip to: 86948 /* 14734 */ MCD_OPC_Decode, 224, 23, 99, // Opcode: SMIN_ZI_H /* 14738 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 14759 /* 14743 */ MCD_OPC_CheckPredicate, 0, 8, 26, 1, // Skip to: 86948 /* 14748 */ MCD_OPC_CheckField, 13, 1, 0, 1, 26, 1, // Skip to: 86948 /* 14755 */ MCD_OPC_Decode, 151, 32, 100, // Opcode: UMIN_ZI_H /* 14759 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 14780 /* 14764 */ MCD_OPC_CheckPredicate, 0, 243, 25, 1, // Skip to: 86948 /* 14769 */ MCD_OPC_CheckField, 13, 1, 0, 236, 25, 1, // Skip to: 86948 /* 14776 */ MCD_OPC_Decode, 151, 20, 99, // Opcode: MUL_ZI_H /* 14780 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 14794 /* 14785 */ MCD_OPC_CheckPredicate, 0, 222, 25, 1, // Skip to: 86948 /* 14790 */ MCD_OPC_Decode, 197, 5, 105, // Opcode: DUP_ZI_H /* 14794 */ MCD_OPC_FilterValue, 25, 213, 25, 1, // Skip to: 86948 /* 14799 */ MCD_OPC_CheckPredicate, 0, 208, 25, 1, // Skip to: 86948 /* 14804 */ MCD_OPC_CheckField, 13, 1, 0, 201, 25, 1, // Skip to: 86948 /* 14811 */ MCD_OPC_Decode, 181, 9, 106, // Opcode: FDUP_ZI_H /* 14815 */ MCD_OPC_FilterValue, 12, 122, 1, 0, // Skip to: 15198 /* 14820 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 14823 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 14903 /* 14828 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 14831 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 14867 /* 14836 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 14839 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14853 /* 14844 */ MCD_OPC_CheckPredicate, 0, 163, 25, 1, // Skip to: 86948 /* 14849 */ MCD_OPC_Decode, 148, 4, 83, // Opcode: CMPGE_PPzZI_S /* 14853 */ MCD_OPC_FilterValue, 1, 154, 25, 1, // Skip to: 86948 /* 14858 */ MCD_OPC_CheckPredicate, 0, 149, 25, 1, // Skip to: 86948 /* 14863 */ MCD_OPC_Decode, 213, 4, 83, // Opcode: CMPLT_PPzZI_S /* 14867 */ MCD_OPC_FilterValue, 1, 140, 25, 1, // Skip to: 86948 /* 14872 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 14875 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14889 /* 14880 */ MCD_OPC_CheckPredicate, 0, 127, 25, 1, // Skip to: 86948 /* 14885 */ MCD_OPC_Decode, 159, 4, 83, // Opcode: CMPGT_PPzZI_S /* 14889 */ MCD_OPC_FilterValue, 1, 118, 25, 1, // Skip to: 86948 /* 14894 */ MCD_OPC_CheckPredicate, 0, 113, 25, 1, // Skip to: 86948 /* 14899 */ MCD_OPC_Decode, 192, 4, 83, // Opcode: CMPLE_PPzZI_S /* 14903 */ MCD_OPC_FilterValue, 1, 147, 0, 0, // Skip to: 15055 /* 14908 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 14911 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 14983 /* 14916 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 14919 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 14962 /* 14924 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 14927 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14941 /* 14932 */ MCD_OPC_CheckPredicate, 0, 75, 25, 1, // Skip to: 86948 /* 14937 */ MCD_OPC_Decode, 210, 20, 84, // Opcode: ORR_PPzPP /* 14941 */ MCD_OPC_FilterValue, 1, 66, 25, 1, // Skip to: 86948 /* 14946 */ MCD_OPC_CheckPredicate, 0, 61, 25, 1, // Skip to: 86948 /* 14951 */ MCD_OPC_CheckField, 16, 4, 0, 54, 25, 1, // Skip to: 86948 /* 14958 */ MCD_OPC_Decode, 214, 2, 85, // Opcode: BRKB_PPzP /* 14962 */ MCD_OPC_FilterValue, 1, 45, 25, 1, // Skip to: 86948 /* 14967 */ MCD_OPC_CheckPredicate, 0, 40, 25, 1, // Skip to: 86948 /* 14972 */ MCD_OPC_CheckField, 20, 1, 0, 33, 25, 1, // Skip to: 86948 /* 14979 */ MCD_OPC_Decode, 188, 20, 84, // Opcode: NOR_PPzPP /* 14983 */ MCD_OPC_FilterValue, 1, 24, 25, 1, // Skip to: 86948 /* 14988 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 14991 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 15034 /* 14996 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 14999 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15013 /* 15004 */ MCD_OPC_CheckPredicate, 0, 3, 25, 1, // Skip to: 86948 /* 15009 */ MCD_OPC_Decode, 200, 20, 84, // Opcode: ORN_PPzPP /* 15013 */ MCD_OPC_FilterValue, 1, 250, 24, 1, // Skip to: 86948 /* 15018 */ MCD_OPC_CheckPredicate, 0, 245, 24, 1, // Skip to: 86948 /* 15023 */ MCD_OPC_CheckField, 16, 4, 0, 238, 24, 1, // Skip to: 86948 /* 15030 */ MCD_OPC_Decode, 213, 2, 87, // Opcode: BRKB_PPmP /* 15034 */ MCD_OPC_FilterValue, 1, 229, 24, 1, // Skip to: 86948 /* 15039 */ MCD_OPC_CheckPredicate, 0, 224, 24, 1, // Skip to: 86948 /* 15044 */ MCD_OPC_CheckField, 20, 1, 0, 217, 24, 1, // Skip to: 86948 /* 15051 */ MCD_OPC_Decode, 174, 20, 84, // Opcode: NAND_PPzPP /* 15055 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 15105 /* 15060 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 15063 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 15084 /* 15068 */ MCD_OPC_CheckPredicate, 0, 195, 24, 1, // Skip to: 86948 /* 15073 */ MCD_OPC_CheckField, 13, 1, 0, 188, 24, 1, // Skip to: 86948 /* 15080 */ MCD_OPC_Decode, 137, 4, 83, // Opcode: CMPEQ_PPzZI_S /* 15084 */ MCD_OPC_FilterValue, 1, 179, 24, 1, // Skip to: 86948 /* 15089 */ MCD_OPC_CheckPredicate, 0, 174, 24, 1, // Skip to: 86948 /* 15094 */ MCD_OPC_CheckField, 13, 1, 0, 167, 24, 1, // Skip to: 86948 /* 15101 */ MCD_OPC_Decode, 220, 4, 83, // Opcode: CMPNE_PPzZI_S /* 15105 */ MCD_OPC_FilterValue, 3, 158, 24, 1, // Skip to: 86948 /* 15110 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 15113 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 15148 /* 15118 */ MCD_OPC_CheckPredicate, 0, 145, 24, 1, // Skip to: 86948 /* 15123 */ MCD_OPC_CheckField, 16, 5, 25, 138, 24, 1, // Skip to: 86948 /* 15130 */ MCD_OPC_CheckField, 9, 1, 0, 131, 24, 1, // Skip to: 86948 /* 15137 */ MCD_OPC_CheckField, 4, 1, 0, 124, 24, 1, // Skip to: 86948 /* 15144 */ MCD_OPC_Decode, 252, 20, 88, // Opcode: PNEXT_S /* 15148 */ MCD_OPC_FilterValue, 8, 115, 24, 1, // Skip to: 86948 /* 15153 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 15156 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 15177 /* 15161 */ MCD_OPC_CheckPredicate, 0, 102, 24, 1, // Skip to: 86948 /* 15166 */ MCD_OPC_CheckField, 4, 1, 0, 95, 24, 1, // Skip to: 86948 /* 15173 */ MCD_OPC_Decode, 174, 21, 89, // Opcode: PTRUE_S /* 15177 */ MCD_OPC_FilterValue, 25, 86, 24, 1, // Skip to: 86948 /* 15182 */ MCD_OPC_CheckPredicate, 0, 81, 24, 1, // Skip to: 86948 /* 15187 */ MCD_OPC_CheckField, 4, 1, 0, 74, 24, 1, // Skip to: 86948 /* 15194 */ MCD_OPC_Decode, 170, 21, 89, // Opcode: PTRUES_S /* 15198 */ MCD_OPC_FilterValue, 13, 226, 2, 0, // Skip to: 15941 /* 15203 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 15206 */ MCD_OPC_FilterValue, 0, 183, 0, 0, // Skip to: 15394 /* 15211 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 15214 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 15250 /* 15219 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 15222 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15236 /* 15227 */ MCD_OPC_CheckPredicate, 0, 36, 24, 1, // Skip to: 86948 /* 15232 */ MCD_OPC_Decode, 245, 34, 91, // Opcode: WHILELT_PWW_S /* 15236 */ MCD_OPC_FilterValue, 1, 27, 24, 1, // Skip to: 86948 /* 15241 */ MCD_OPC_CheckPredicate, 0, 22, 24, 1, // Skip to: 86948 /* 15246 */ MCD_OPC_Decode, 221, 34, 91, // Opcode: WHILELE_PWW_S /* 15250 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 15286 /* 15255 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 15258 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15272 /* 15263 */ MCD_OPC_CheckPredicate, 0, 0, 24, 1, // Skip to: 86948 /* 15268 */ MCD_OPC_Decode, 229, 34, 91, // Opcode: WHILELO_PWW_S /* 15272 */ MCD_OPC_FilterValue, 1, 247, 23, 1, // Skip to: 86948 /* 15277 */ MCD_OPC_CheckPredicate, 0, 242, 23, 1, // Skip to: 86948 /* 15282 */ MCD_OPC_Decode, 237, 34, 91, // Opcode: WHILELS_PWW_S /* 15286 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 15322 /* 15291 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 15294 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15308 /* 15299 */ MCD_OPC_CheckPredicate, 0, 220, 23, 1, // Skip to: 86948 /* 15304 */ MCD_OPC_Decode, 249, 34, 92, // Opcode: WHILELT_PXX_S /* 15308 */ MCD_OPC_FilterValue, 1, 211, 23, 1, // Skip to: 86948 /* 15313 */ MCD_OPC_CheckPredicate, 0, 206, 23, 1, // Skip to: 86948 /* 15318 */ MCD_OPC_Decode, 225, 34, 92, // Opcode: WHILELE_PXX_S /* 15322 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 15358 /* 15327 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 15330 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15344 /* 15335 */ MCD_OPC_CheckPredicate, 0, 184, 23, 1, // Skip to: 86948 /* 15340 */ MCD_OPC_Decode, 233, 34, 92, // Opcode: WHILELO_PXX_S /* 15344 */ MCD_OPC_FilterValue, 1, 175, 23, 1, // Skip to: 86948 /* 15349 */ MCD_OPC_CheckPredicate, 0, 170, 23, 1, // Skip to: 86948 /* 15354 */ MCD_OPC_Decode, 241, 34, 92, // Opcode: WHILELS_PXX_S /* 15358 */ MCD_OPC_FilterValue, 8, 161, 23, 1, // Skip to: 86948 /* 15363 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 15366 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15380 /* 15371 */ MCD_OPC_CheckPredicate, 0, 148, 23, 1, // Skip to: 86948 /* 15376 */ MCD_OPC_Decode, 169, 5, 107, // Opcode: CTERMEQ_WW /* 15380 */ MCD_OPC_FilterValue, 16, 139, 23, 1, // Skip to: 86948 /* 15385 */ MCD_OPC_CheckPredicate, 0, 134, 23, 1, // Skip to: 86948 /* 15390 */ MCD_OPC_Decode, 171, 5, 107, // Opcode: CTERMNE_WW /* 15394 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 15695 /* 15399 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 15402 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 15423 /* 15407 */ MCD_OPC_CheckPredicate, 0, 112, 23, 1, // Skip to: 86948 /* 15412 */ MCD_OPC_CheckField, 9, 1, 0, 105, 23, 1, // Skip to: 86948 /* 15419 */ MCD_OPC_Decode, 251, 4, 93, // Opcode: CNTP_XPP_S /* 15423 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 15473 /* 15428 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 15431 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15445 /* 15436 */ MCD_OPC_CheckPredicate, 0, 83, 23, 1, // Skip to: 86948 /* 15441 */ MCD_OPC_Decode, 143, 25, 103, // Opcode: SQINCP_ZP_S /* 15445 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15459 /* 15450 */ MCD_OPC_CheckPredicate, 0, 69, 23, 1, // Skip to: 86948 /* 15455 */ MCD_OPC_Decode, 136, 25, 94, // Opcode: SQINCP_XPWd_S /* 15459 */ MCD_OPC_FilterValue, 6, 60, 23, 1, // Skip to: 86948 /* 15464 */ MCD_OPC_CheckPredicate, 0, 55, 23, 1, // Skip to: 86948 /* 15469 */ MCD_OPC_Decode, 140, 25, 94, // Opcode: SQINCP_XP_S /* 15473 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 15523 /* 15478 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 15481 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15495 /* 15486 */ MCD_OPC_CheckPredicate, 0, 33, 23, 1, // Skip to: 86948 /* 15491 */ MCD_OPC_Decode, 134, 33, 103, // Opcode: UQINCP_ZP_S /* 15495 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15509 /* 15500 */ MCD_OPC_CheckPredicate, 0, 19, 23, 1, // Skip to: 86948 /* 15505 */ MCD_OPC_Decode, 255, 32, 96, // Opcode: UQINCP_WP_S /* 15509 */ MCD_OPC_FilterValue, 6, 10, 23, 1, // Skip to: 86948 /* 15514 */ MCD_OPC_CheckPredicate, 0, 5, 23, 1, // Skip to: 86948 /* 15519 */ MCD_OPC_Decode, 131, 33, 94, // Opcode: UQINCP_XP_S /* 15523 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 15573 /* 15528 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 15531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15545 /* 15536 */ MCD_OPC_CheckPredicate, 0, 239, 22, 1, // Skip to: 86948 /* 15541 */ MCD_OPC_Decode, 201, 24, 103, // Opcode: SQDECP_ZP_S /* 15545 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15559 /* 15550 */ MCD_OPC_CheckPredicate, 0, 225, 22, 1, // Skip to: 86948 /* 15555 */ MCD_OPC_Decode, 194, 24, 94, // Opcode: SQDECP_XPWd_S /* 15559 */ MCD_OPC_FilterValue, 6, 216, 22, 1, // Skip to: 86948 /* 15564 */ MCD_OPC_CheckPredicate, 0, 211, 22, 1, // Skip to: 86948 /* 15569 */ MCD_OPC_Decode, 198, 24, 94, // Opcode: SQDECP_XP_S /* 15573 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 15623 /* 15578 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 15581 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15595 /* 15586 */ MCD_OPC_CheckPredicate, 0, 189, 22, 1, // Skip to: 86948 /* 15591 */ MCD_OPC_Decode, 240, 32, 103, // Opcode: UQDECP_ZP_S /* 15595 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15609 /* 15600 */ MCD_OPC_CheckPredicate, 0, 175, 22, 1, // Skip to: 86948 /* 15605 */ MCD_OPC_Decode, 233, 32, 96, // Opcode: UQDECP_WP_S /* 15609 */ MCD_OPC_FilterValue, 6, 166, 22, 1, // Skip to: 86948 /* 15614 */ MCD_OPC_CheckPredicate, 0, 161, 22, 1, // Skip to: 86948 /* 15619 */ MCD_OPC_Decode, 237, 32, 94, // Opcode: UQDECP_XP_S /* 15623 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 15659 /* 15628 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 15631 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15645 /* 15636 */ MCD_OPC_CheckPredicate, 0, 139, 22, 1, // Skip to: 86948 /* 15641 */ MCD_OPC_Decode, 255, 13, 103, // Opcode: INCP_ZP_S /* 15645 */ MCD_OPC_FilterValue, 4, 130, 22, 1, // Skip to: 86948 /* 15650 */ MCD_OPC_CheckPredicate, 0, 125, 22, 1, // Skip to: 86948 /* 15655 */ MCD_OPC_Decode, 252, 13, 94, // Opcode: INCP_XP_S /* 15659 */ MCD_OPC_FilterValue, 13, 116, 22, 1, // Skip to: 86948 /* 15664 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 15667 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15681 /* 15672 */ MCD_OPC_CheckPredicate, 0, 103, 22, 1, // Skip to: 86948 /* 15677 */ MCD_OPC_Decode, 188, 5, 103, // Opcode: DECP_ZP_S /* 15681 */ MCD_OPC_FilterValue, 4, 94, 22, 1, // Skip to: 86948 /* 15686 */ MCD_OPC_CheckPredicate, 0, 89, 22, 1, // Skip to: 86948 /* 15691 */ MCD_OPC_Decode, 185, 5, 94, // Opcode: DECP_XP_S /* 15695 */ MCD_OPC_FilterValue, 3, 80, 22, 1, // Skip to: 86948 /* 15700 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 15703 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15717 /* 15708 */ MCD_OPC_CheckPredicate, 0, 67, 22, 1, // Skip to: 86948 /* 15713 */ MCD_OPC_Decode, 184, 1, 108, // Opcode: ADD_ZI_S /* 15717 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 15731 /* 15722 */ MCD_OPC_CheckPredicate, 0, 53, 22, 1, // Skip to: 86948 /* 15727 */ MCD_OPC_Decode, 246, 29, 108, // Opcode: SUB_ZI_S /* 15731 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 15745 /* 15736 */ MCD_OPC_CheckPredicate, 0, 39, 22, 1, // Skip to: 86948 /* 15741 */ MCD_OPC_Decode, 220, 29, 108, // Opcode: SUBR_ZI_S /* 15745 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15759 /* 15750 */ MCD_OPC_CheckPredicate, 0, 25, 22, 1, // Skip to: 86948 /* 15755 */ MCD_OPC_Decode, 167, 24, 108, // Opcode: SQADD_ZI_S /* 15759 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 15773 /* 15764 */ MCD_OPC_CheckPredicate, 0, 11, 22, 1, // Skip to: 86948 /* 15769 */ MCD_OPC_Decode, 206, 32, 108, // Opcode: UQADD_ZI_S /* 15773 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 15787 /* 15778 */ MCD_OPC_CheckPredicate, 0, 253, 21, 1, // Skip to: 86948 /* 15783 */ MCD_OPC_Decode, 149, 26, 108, // Opcode: SQSUB_ZI_S /* 15787 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 15801 /* 15792 */ MCD_OPC_CheckPredicate, 0, 239, 21, 1, // Skip to: 86948 /* 15797 */ MCD_OPC_Decode, 192, 33, 108, // Opcode: UQSUB_ZI_S /* 15801 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 15822 /* 15806 */ MCD_OPC_CheckPredicate, 0, 225, 21, 1, // Skip to: 86948 /* 15811 */ MCD_OPC_CheckField, 13, 1, 0, 218, 21, 1, // Skip to: 86948 /* 15818 */ MCD_OPC_Decode, 195, 23, 99, // Opcode: SMAX_ZI_S /* 15822 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 15843 /* 15827 */ MCD_OPC_CheckPredicate, 0, 204, 21, 1, // Skip to: 86948 /* 15832 */ MCD_OPC_CheckField, 13, 1, 0, 197, 21, 1, // Skip to: 86948 /* 15839 */ MCD_OPC_Decode, 251, 31, 100, // Opcode: UMAX_ZI_S /* 15843 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 15864 /* 15848 */ MCD_OPC_CheckPredicate, 0, 183, 21, 1, // Skip to: 86948 /* 15853 */ MCD_OPC_CheckField, 13, 1, 0, 176, 21, 1, // Skip to: 86948 /* 15860 */ MCD_OPC_Decode, 225, 23, 99, // Opcode: SMIN_ZI_S /* 15864 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 15885 /* 15869 */ MCD_OPC_CheckPredicate, 0, 162, 21, 1, // Skip to: 86948 /* 15874 */ MCD_OPC_CheckField, 13, 1, 0, 155, 21, 1, // Skip to: 86948 /* 15881 */ MCD_OPC_Decode, 152, 32, 100, // Opcode: UMIN_ZI_S /* 15885 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 15906 /* 15890 */ MCD_OPC_CheckPredicate, 0, 141, 21, 1, // Skip to: 86948 /* 15895 */ MCD_OPC_CheckField, 13, 1, 0, 134, 21, 1, // Skip to: 86948 /* 15902 */ MCD_OPC_Decode, 152, 20, 99, // Opcode: MUL_ZI_S /* 15906 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 15920 /* 15911 */ MCD_OPC_CheckPredicate, 0, 120, 21, 1, // Skip to: 86948 /* 15916 */ MCD_OPC_Decode, 198, 5, 109, // Opcode: DUP_ZI_S /* 15920 */ MCD_OPC_FilterValue, 25, 111, 21, 1, // Skip to: 86948 /* 15925 */ MCD_OPC_CheckPredicate, 0, 106, 21, 1, // Skip to: 86948 /* 15930 */ MCD_OPC_CheckField, 13, 1, 0, 99, 21, 1, // Skip to: 86948 /* 15937 */ MCD_OPC_Decode, 182, 9, 106, // Opcode: FDUP_ZI_S /* 15941 */ MCD_OPC_FilterValue, 14, 100, 1, 0, // Skip to: 16302 /* 15946 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 15949 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 16029 /* 15954 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 15957 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 15993 /* 15962 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 15965 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15979 /* 15970 */ MCD_OPC_CheckPredicate, 0, 61, 21, 1, // Skip to: 86948 /* 15975 */ MCD_OPC_Decode, 146, 4, 83, // Opcode: CMPGE_PPzZI_D /* 15979 */ MCD_OPC_FilterValue, 1, 52, 21, 1, // Skip to: 86948 /* 15984 */ MCD_OPC_CheckPredicate, 0, 47, 21, 1, // Skip to: 86948 /* 15989 */ MCD_OPC_Decode, 211, 4, 83, // Opcode: CMPLT_PPzZI_D /* 15993 */ MCD_OPC_FilterValue, 1, 38, 21, 1, // Skip to: 86948 /* 15998 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 16001 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16015 /* 16006 */ MCD_OPC_CheckPredicate, 0, 25, 21, 1, // Skip to: 86948 /* 16011 */ MCD_OPC_Decode, 157, 4, 83, // Opcode: CMPGT_PPzZI_D /* 16015 */ MCD_OPC_FilterValue, 1, 16, 21, 1, // Skip to: 86948 /* 16020 */ MCD_OPC_CheckPredicate, 0, 11, 21, 1, // Skip to: 86948 /* 16025 */ MCD_OPC_Decode, 190, 4, 83, // Opcode: CMPLE_PPzZI_D /* 16029 */ MCD_OPC_FilterValue, 1, 125, 0, 0, // Skip to: 16159 /* 16034 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 16037 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 16109 /* 16042 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 16045 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 16088 /* 16050 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 16053 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16067 /* 16058 */ MCD_OPC_CheckPredicate, 0, 229, 20, 1, // Skip to: 86948 /* 16063 */ MCD_OPC_Decode, 203, 20, 84, // Opcode: ORRS_PPzPP /* 16067 */ MCD_OPC_FilterValue, 1, 220, 20, 1, // Skip to: 86948 /* 16072 */ MCD_OPC_CheckPredicate, 0, 215, 20, 1, // Skip to: 86948 /* 16077 */ MCD_OPC_CheckField, 16, 4, 0, 208, 20, 1, // Skip to: 86948 /* 16084 */ MCD_OPC_Decode, 212, 2, 85, // Opcode: BRKBS_PPzP /* 16088 */ MCD_OPC_FilterValue, 1, 199, 20, 1, // Skip to: 86948 /* 16093 */ MCD_OPC_CheckPredicate, 0, 194, 20, 1, // Skip to: 86948 /* 16098 */ MCD_OPC_CheckField, 20, 1, 0, 187, 20, 1, // Skip to: 86948 /* 16105 */ MCD_OPC_Decode, 187, 20, 84, // Opcode: NORS_PPzPP /* 16109 */ MCD_OPC_FilterValue, 1, 178, 20, 1, // Skip to: 86948 /* 16114 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 16117 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16138 /* 16122 */ MCD_OPC_CheckPredicate, 0, 165, 20, 1, // Skip to: 86948 /* 16127 */ MCD_OPC_CheckField, 20, 1, 0, 158, 20, 1, // Skip to: 86948 /* 16134 */ MCD_OPC_Decode, 195, 20, 84, // Opcode: ORNS_PPzPP /* 16138 */ MCD_OPC_FilterValue, 1, 149, 20, 1, // Skip to: 86948 /* 16143 */ MCD_OPC_CheckPredicate, 0, 144, 20, 1, // Skip to: 86948 /* 16148 */ MCD_OPC_CheckField, 20, 1, 0, 137, 20, 1, // Skip to: 86948 /* 16155 */ MCD_OPC_Decode, 173, 20, 84, // Opcode: NANDS_PPzPP /* 16159 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 16209 /* 16164 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 16167 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16188 /* 16172 */ MCD_OPC_CheckPredicate, 0, 115, 20, 1, // Skip to: 86948 /* 16177 */ MCD_OPC_CheckField, 13, 1, 0, 108, 20, 1, // Skip to: 86948 /* 16184 */ MCD_OPC_Decode, 135, 4, 83, // Opcode: CMPEQ_PPzZI_D /* 16188 */ MCD_OPC_FilterValue, 1, 99, 20, 1, // Skip to: 86948 /* 16193 */ MCD_OPC_CheckPredicate, 0, 94, 20, 1, // Skip to: 86948 /* 16198 */ MCD_OPC_CheckField, 13, 1, 0, 87, 20, 1, // Skip to: 86948 /* 16205 */ MCD_OPC_Decode, 218, 4, 83, // Opcode: CMPNE_PPzZI_D /* 16209 */ MCD_OPC_FilterValue, 3, 78, 20, 1, // Skip to: 86948 /* 16214 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 16217 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 16252 /* 16222 */ MCD_OPC_CheckPredicate, 0, 65, 20, 1, // Skip to: 86948 /* 16227 */ MCD_OPC_CheckField, 16, 5, 25, 58, 20, 1, // Skip to: 86948 /* 16234 */ MCD_OPC_CheckField, 9, 1, 0, 51, 20, 1, // Skip to: 86948 /* 16241 */ MCD_OPC_CheckField, 4, 1, 0, 44, 20, 1, // Skip to: 86948 /* 16248 */ MCD_OPC_Decode, 250, 20, 88, // Opcode: PNEXT_D /* 16252 */ MCD_OPC_FilterValue, 8, 35, 20, 1, // Skip to: 86948 /* 16257 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 16260 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 16281 /* 16265 */ MCD_OPC_CheckPredicate, 0, 22, 20, 1, // Skip to: 86948 /* 16270 */ MCD_OPC_CheckField, 4, 1, 0, 15, 20, 1, // Skip to: 86948 /* 16277 */ MCD_OPC_Decode, 172, 21, 89, // Opcode: PTRUE_D /* 16281 */ MCD_OPC_FilterValue, 25, 6, 20, 1, // Skip to: 86948 /* 16286 */ MCD_OPC_CheckPredicate, 0, 1, 20, 1, // Skip to: 86948 /* 16291 */ MCD_OPC_CheckField, 4, 1, 0, 250, 19, 1, // Skip to: 86948 /* 16298 */ MCD_OPC_Decode, 168, 21, 89, // Opcode: PTRUES_D /* 16302 */ MCD_OPC_FilterValue, 15, 241, 19, 1, // Skip to: 86948 /* 16307 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 16310 */ MCD_OPC_FilterValue, 0, 183, 0, 0, // Skip to: 16498 /* 16315 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 16318 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 16354 /* 16323 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 16326 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16340 /* 16331 */ MCD_OPC_CheckPredicate, 0, 212, 19, 1, // Skip to: 86948 /* 16336 */ MCD_OPC_Decode, 243, 34, 91, // Opcode: WHILELT_PWW_D /* 16340 */ MCD_OPC_FilterValue, 1, 203, 19, 1, // Skip to: 86948 /* 16345 */ MCD_OPC_CheckPredicate, 0, 198, 19, 1, // Skip to: 86948 /* 16350 */ MCD_OPC_Decode, 219, 34, 91, // Opcode: WHILELE_PWW_D /* 16354 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 16390 /* 16359 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 16362 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16376 /* 16367 */ MCD_OPC_CheckPredicate, 0, 176, 19, 1, // Skip to: 86948 /* 16372 */ MCD_OPC_Decode, 227, 34, 91, // Opcode: WHILELO_PWW_D /* 16376 */ MCD_OPC_FilterValue, 1, 167, 19, 1, // Skip to: 86948 /* 16381 */ MCD_OPC_CheckPredicate, 0, 162, 19, 1, // Skip to: 86948 /* 16386 */ MCD_OPC_Decode, 235, 34, 91, // Opcode: WHILELS_PWW_D /* 16390 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 16426 /* 16395 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 16398 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16412 /* 16403 */ MCD_OPC_CheckPredicate, 0, 140, 19, 1, // Skip to: 86948 /* 16408 */ MCD_OPC_Decode, 247, 34, 92, // Opcode: WHILELT_PXX_D /* 16412 */ MCD_OPC_FilterValue, 1, 131, 19, 1, // Skip to: 86948 /* 16417 */ MCD_OPC_CheckPredicate, 0, 126, 19, 1, // Skip to: 86948 /* 16422 */ MCD_OPC_Decode, 223, 34, 92, // Opcode: WHILELE_PXX_D /* 16426 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 16462 /* 16431 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 16434 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16448 /* 16439 */ MCD_OPC_CheckPredicate, 0, 104, 19, 1, // Skip to: 86948 /* 16444 */ MCD_OPC_Decode, 231, 34, 92, // Opcode: WHILELO_PXX_D /* 16448 */ MCD_OPC_FilterValue, 1, 95, 19, 1, // Skip to: 86948 /* 16453 */ MCD_OPC_CheckPredicate, 0, 90, 19, 1, // Skip to: 86948 /* 16458 */ MCD_OPC_Decode, 239, 34, 92, // Opcode: WHILELS_PXX_D /* 16462 */ MCD_OPC_FilterValue, 8, 81, 19, 1, // Skip to: 86948 /* 16467 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 16470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16484 /* 16475 */ MCD_OPC_CheckPredicate, 0, 68, 19, 1, // Skip to: 86948 /* 16480 */ MCD_OPC_Decode, 170, 5, 110, // Opcode: CTERMEQ_XX /* 16484 */ MCD_OPC_FilterValue, 16, 59, 19, 1, // Skip to: 86948 /* 16489 */ MCD_OPC_CheckPredicate, 0, 54, 19, 1, // Skip to: 86948 /* 16494 */ MCD_OPC_Decode, 172, 5, 110, // Opcode: CTERMNE_XX /* 16498 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 16799 /* 16503 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 16506 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16527 /* 16511 */ MCD_OPC_CheckPredicate, 0, 32, 19, 1, // Skip to: 86948 /* 16516 */ MCD_OPC_CheckField, 9, 1, 0, 25, 19, 1, // Skip to: 86948 /* 16523 */ MCD_OPC_Decode, 249, 4, 93, // Opcode: CNTP_XPP_D /* 16527 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 16577 /* 16532 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 16535 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16549 /* 16540 */ MCD_OPC_CheckPredicate, 0, 3, 19, 1, // Skip to: 86948 /* 16545 */ MCD_OPC_Decode, 141, 25, 103, // Opcode: SQINCP_ZP_D /* 16549 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16563 /* 16554 */ MCD_OPC_CheckPredicate, 0, 245, 18, 1, // Skip to: 86948 /* 16559 */ MCD_OPC_Decode, 134, 25, 94, // Opcode: SQINCP_XPWd_D /* 16563 */ MCD_OPC_FilterValue, 6, 236, 18, 1, // Skip to: 86948 /* 16568 */ MCD_OPC_CheckPredicate, 0, 231, 18, 1, // Skip to: 86948 /* 16573 */ MCD_OPC_Decode, 138, 25, 94, // Opcode: SQINCP_XP_D /* 16577 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 16627 /* 16582 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 16585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16599 /* 16590 */ MCD_OPC_CheckPredicate, 0, 209, 18, 1, // Skip to: 86948 /* 16595 */ MCD_OPC_Decode, 132, 33, 103, // Opcode: UQINCP_ZP_D /* 16599 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16613 /* 16604 */ MCD_OPC_CheckPredicate, 0, 195, 18, 1, // Skip to: 86948 /* 16609 */ MCD_OPC_Decode, 253, 32, 96, // Opcode: UQINCP_WP_D /* 16613 */ MCD_OPC_FilterValue, 6, 186, 18, 1, // Skip to: 86948 /* 16618 */ MCD_OPC_CheckPredicate, 0, 181, 18, 1, // Skip to: 86948 /* 16623 */ MCD_OPC_Decode, 129, 33, 94, // Opcode: UQINCP_XP_D /* 16627 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 16677 /* 16632 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 16635 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16649 /* 16640 */ MCD_OPC_CheckPredicate, 0, 159, 18, 1, // Skip to: 86948 /* 16645 */ MCD_OPC_Decode, 199, 24, 103, // Opcode: SQDECP_ZP_D /* 16649 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16663 /* 16654 */ MCD_OPC_CheckPredicate, 0, 145, 18, 1, // Skip to: 86948 /* 16659 */ MCD_OPC_Decode, 192, 24, 94, // Opcode: SQDECP_XPWd_D /* 16663 */ MCD_OPC_FilterValue, 6, 136, 18, 1, // Skip to: 86948 /* 16668 */ MCD_OPC_CheckPredicate, 0, 131, 18, 1, // Skip to: 86948 /* 16673 */ MCD_OPC_Decode, 196, 24, 94, // Opcode: SQDECP_XP_D /* 16677 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 16727 /* 16682 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 16685 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16699 /* 16690 */ MCD_OPC_CheckPredicate, 0, 109, 18, 1, // Skip to: 86948 /* 16695 */ MCD_OPC_Decode, 238, 32, 103, // Opcode: UQDECP_ZP_D /* 16699 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16713 /* 16704 */ MCD_OPC_CheckPredicate, 0, 95, 18, 1, // Skip to: 86948 /* 16709 */ MCD_OPC_Decode, 231, 32, 96, // Opcode: UQDECP_WP_D /* 16713 */ MCD_OPC_FilterValue, 6, 86, 18, 1, // Skip to: 86948 /* 16718 */ MCD_OPC_CheckPredicate, 0, 81, 18, 1, // Skip to: 86948 /* 16723 */ MCD_OPC_Decode, 235, 32, 94, // Opcode: UQDECP_XP_D /* 16727 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 16763 /* 16732 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 16735 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16749 /* 16740 */ MCD_OPC_CheckPredicate, 0, 59, 18, 1, // Skip to: 86948 /* 16745 */ MCD_OPC_Decode, 253, 13, 103, // Opcode: INCP_ZP_D /* 16749 */ MCD_OPC_FilterValue, 4, 50, 18, 1, // Skip to: 86948 /* 16754 */ MCD_OPC_CheckPredicate, 0, 45, 18, 1, // Skip to: 86948 /* 16759 */ MCD_OPC_Decode, 250, 13, 94, // Opcode: INCP_XP_D /* 16763 */ MCD_OPC_FilterValue, 13, 36, 18, 1, // Skip to: 86948 /* 16768 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... /* 16771 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16785 /* 16776 */ MCD_OPC_CheckPredicate, 0, 23, 18, 1, // Skip to: 86948 /* 16781 */ MCD_OPC_Decode, 186, 5, 103, // Opcode: DECP_ZP_D /* 16785 */ MCD_OPC_FilterValue, 4, 14, 18, 1, // Skip to: 86948 /* 16790 */ MCD_OPC_CheckPredicate, 0, 9, 18, 1, // Skip to: 86948 /* 16795 */ MCD_OPC_Decode, 183, 5, 94, // Opcode: DECP_XP_D /* 16799 */ MCD_OPC_FilterValue, 3, 0, 18, 1, // Skip to: 86948 /* 16804 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 16807 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16821 /* 16812 */ MCD_OPC_CheckPredicate, 0, 243, 17, 1, // Skip to: 86948 /* 16817 */ MCD_OPC_Decode, 182, 1, 111, // Opcode: ADD_ZI_D /* 16821 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 16835 /* 16826 */ MCD_OPC_CheckPredicate, 0, 229, 17, 1, // Skip to: 86948 /* 16831 */ MCD_OPC_Decode, 244, 29, 111, // Opcode: SUB_ZI_D /* 16835 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 16849 /* 16840 */ MCD_OPC_CheckPredicate, 0, 215, 17, 1, // Skip to: 86948 /* 16845 */ MCD_OPC_Decode, 218, 29, 111, // Opcode: SUBR_ZI_D /* 16849 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16863 /* 16854 */ MCD_OPC_CheckPredicate, 0, 201, 17, 1, // Skip to: 86948 /* 16859 */ MCD_OPC_Decode, 165, 24, 111, // Opcode: SQADD_ZI_D /* 16863 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 16877 /* 16868 */ MCD_OPC_CheckPredicate, 0, 187, 17, 1, // Skip to: 86948 /* 16873 */ MCD_OPC_Decode, 204, 32, 111, // Opcode: UQADD_ZI_D /* 16877 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 16891 /* 16882 */ MCD_OPC_CheckPredicate, 0, 173, 17, 1, // Skip to: 86948 /* 16887 */ MCD_OPC_Decode, 147, 26, 111, // Opcode: SQSUB_ZI_D /* 16891 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 16905 /* 16896 */ MCD_OPC_CheckPredicate, 0, 159, 17, 1, // Skip to: 86948 /* 16901 */ MCD_OPC_Decode, 190, 33, 111, // Opcode: UQSUB_ZI_D /* 16905 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 16926 /* 16910 */ MCD_OPC_CheckPredicate, 0, 145, 17, 1, // Skip to: 86948 /* 16915 */ MCD_OPC_CheckField, 13, 1, 0, 138, 17, 1, // Skip to: 86948 /* 16922 */ MCD_OPC_Decode, 193, 23, 99, // Opcode: SMAX_ZI_D /* 16926 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 16947 /* 16931 */ MCD_OPC_CheckPredicate, 0, 124, 17, 1, // Skip to: 86948 /* 16936 */ MCD_OPC_CheckField, 13, 1, 0, 117, 17, 1, // Skip to: 86948 /* 16943 */ MCD_OPC_Decode, 249, 31, 100, // Opcode: UMAX_ZI_D /* 16947 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 16968 /* 16952 */ MCD_OPC_CheckPredicate, 0, 103, 17, 1, // Skip to: 86948 /* 16957 */ MCD_OPC_CheckField, 13, 1, 0, 96, 17, 1, // Skip to: 86948 /* 16964 */ MCD_OPC_Decode, 223, 23, 99, // Opcode: SMIN_ZI_D /* 16968 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 16989 /* 16973 */ MCD_OPC_CheckPredicate, 0, 82, 17, 1, // Skip to: 86948 /* 16978 */ MCD_OPC_CheckField, 13, 1, 0, 75, 17, 1, // Skip to: 86948 /* 16985 */ MCD_OPC_Decode, 150, 32, 100, // Opcode: UMIN_ZI_D /* 16989 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 17010 /* 16994 */ MCD_OPC_CheckPredicate, 0, 61, 17, 1, // Skip to: 86948 /* 16999 */ MCD_OPC_CheckField, 13, 1, 0, 54, 17, 1, // Skip to: 86948 /* 17006 */ MCD_OPC_Decode, 150, 20, 99, // Opcode: MUL_ZI_D /* 17010 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 17024 /* 17015 */ MCD_OPC_CheckPredicate, 0, 40, 17, 1, // Skip to: 86948 /* 17020 */ MCD_OPC_Decode, 196, 5, 112, // Opcode: DUP_ZI_D /* 17024 */ MCD_OPC_FilterValue, 25, 31, 17, 1, // Skip to: 86948 /* 17029 */ MCD_OPC_CheckPredicate, 0, 26, 17, 1, // Skip to: 86948 /* 17034 */ MCD_OPC_CheckField, 13, 1, 0, 19, 17, 1, // Skip to: 86948 /* 17041 */ MCD_OPC_Decode, 180, 9, 106, // Opcode: FDUP_ZI_D /* 17045 */ MCD_OPC_FilterValue, 2, 147, 0, 0, // Skip to: 17197 /* 17050 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 17053 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 17089 /* 17058 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 17061 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17075 /* 17066 */ MCD_OPC_CheckPredicate, 0, 245, 16, 1, // Skip to: 86948 /* 17071 */ MCD_OPC_Decode, 228, 22, 113, // Opcode: SDOT_ZZZ_S /* 17075 */ MCD_OPC_FilterValue, 1, 236, 16, 1, // Skip to: 86948 /* 17080 */ MCD_OPC_CheckPredicate, 0, 231, 16, 1, // Skip to: 86948 /* 17085 */ MCD_OPC_Decode, 215, 31, 113, // Opcode: UDOT_ZZZ_S /* 17089 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 17125 /* 17094 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 17097 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17111 /* 17102 */ MCD_OPC_CheckPredicate, 0, 209, 16, 1, // Skip to: 86948 /* 17107 */ MCD_OPC_Decode, 226, 22, 114, // Opcode: SDOT_ZZZI_S /* 17111 */ MCD_OPC_FilterValue, 1, 200, 16, 1, // Skip to: 86948 /* 17116 */ MCD_OPC_CheckPredicate, 0, 195, 16, 1, // Skip to: 86948 /* 17121 */ MCD_OPC_Decode, 213, 31, 114, // Opcode: UDOT_ZZZI_S /* 17125 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 17161 /* 17130 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 17133 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17147 /* 17138 */ MCD_OPC_CheckPredicate, 0, 173, 16, 1, // Skip to: 86948 /* 17143 */ MCD_OPC_Decode, 227, 22, 113, // Opcode: SDOT_ZZZ_D /* 17147 */ MCD_OPC_FilterValue, 1, 164, 16, 1, // Skip to: 86948 /* 17152 */ MCD_OPC_CheckPredicate, 0, 159, 16, 1, // Skip to: 86948 /* 17157 */ MCD_OPC_Decode, 214, 31, 113, // Opcode: UDOT_ZZZ_D /* 17161 */ MCD_OPC_FilterValue, 7, 150, 16, 1, // Skip to: 86948 /* 17166 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 17169 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17183 /* 17174 */ MCD_OPC_CheckPredicate, 0, 137, 16, 1, // Skip to: 86948 /* 17179 */ MCD_OPC_Decode, 225, 22, 115, // Opcode: SDOT_ZZZI_D /* 17183 */ MCD_OPC_FilterValue, 1, 128, 16, 1, // Skip to: 86948 /* 17188 */ MCD_OPC_CheckPredicate, 0, 123, 16, 1, // Skip to: 86948 /* 17193 */ MCD_OPC_Decode, 212, 31, 115, // Opcode: UDOT_ZZZI_D /* 17197 */ MCD_OPC_FilterValue, 3, 6, 17, 0, // Skip to: 21560 /* 17202 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 17205 */ MCD_OPC_FilterValue, 0, 110, 0, 0, // Skip to: 17320 /* 17210 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 17213 */ MCD_OPC_FilterValue, 0, 74, 0, 0, // Skip to: 17292 /* 17218 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17221 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 17242 /* 17226 */ MCD_OPC_CheckPredicate, 0, 85, 16, 1, // Skip to: 86948 /* 17231 */ MCD_OPC_CheckField, 22, 1, 1, 78, 16, 1, // Skip to: 86948 /* 17238 */ MCD_OPC_Decode, 156, 7, 116, // Opcode: FCMLA_ZPmZZ_H /* 17242 */ MCD_OPC_FilterValue, 1, 69, 16, 1, // Skip to: 86948 /* 17247 */ MCD_OPC_ExtractField, 10, 5, // Inst{14-10} ... /* 17250 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17264 /* 17255 */ MCD_OPC_CheckPredicate, 0, 56, 16, 1, // Skip to: 86948 /* 17260 */ MCD_OPC_Decode, 181, 10, 117, // Opcode: FMLA_ZZZI_H /* 17264 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17278 /* 17269 */ MCD_OPC_CheckPredicate, 0, 42, 16, 1, // Skip to: 86948 /* 17274 */ MCD_OPC_Decode, 200, 10, 117, // Opcode: FMLS_ZZZI_H /* 17278 */ MCD_OPC_FilterValue, 8, 33, 16, 1, // Skip to: 86948 /* 17283 */ MCD_OPC_CheckPredicate, 0, 28, 16, 1, // Skip to: 86948 /* 17288 */ MCD_OPC_Decode, 146, 11, 118, // Opcode: FMUL_ZZZI_H /* 17292 */ MCD_OPC_FilterValue, 1, 19, 16, 1, // Skip to: 86948 /* 17297 */ MCD_OPC_CheckPredicate, 0, 14, 16, 1, // Skip to: 86948 /* 17302 */ MCD_OPC_CheckField, 17, 6, 32, 7, 16, 1, // Skip to: 86948 /* 17309 */ MCD_OPC_CheckField, 13, 2, 0, 0, 16, 1, // Skip to: 86948 /* 17316 */ MCD_OPC_Decode, 204, 6, 119, // Opcode: FCADD_ZPmZ_H /* 17320 */ MCD_OPC_FilterValue, 1, 5, 1, 0, // Skip to: 17586 /* 17325 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 17328 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 17378 /* 17333 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 17336 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17350 /* 17341 */ MCD_OPC_CheckPredicate, 0, 226, 15, 1, // Skip to: 86948 /* 17346 */ MCD_OPC_Decode, 157, 7, 116, // Opcode: FCMLA_ZPmZZ_S /* 17350 */ MCD_OPC_FilterValue, 1, 217, 15, 1, // Skip to: 86948 /* 17355 */ MCD_OPC_CheckPredicate, 0, 212, 15, 1, // Skip to: 86948 /* 17360 */ MCD_OPC_CheckField, 17, 4, 0, 205, 15, 1, // Skip to: 86948 /* 17367 */ MCD_OPC_CheckField, 13, 2, 0, 198, 15, 1, // Skip to: 86948 /* 17374 */ MCD_OPC_Decode, 205, 6, 119, // Opcode: FCADD_ZPmZ_S /* 17378 */ MCD_OPC_FilterValue, 1, 74, 0, 0, // Skip to: 17457 /* 17383 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17386 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 17422 /* 17391 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 17394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17408 /* 17399 */ MCD_OPC_CheckPredicate, 0, 168, 15, 1, // Skip to: 86948 /* 17404 */ MCD_OPC_Decode, 182, 10, 114, // Opcode: FMLA_ZZZI_S /* 17408 */ MCD_OPC_FilterValue, 1, 159, 15, 1, // Skip to: 86948 /* 17413 */ MCD_OPC_CheckPredicate, 0, 154, 15, 1, // Skip to: 86948 /* 17418 */ MCD_OPC_Decode, 201, 10, 114, // Opcode: FMLS_ZZZI_S /* 17422 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17436 /* 17427 */ MCD_OPC_CheckPredicate, 0, 140, 15, 1, // Skip to: 86948 /* 17432 */ MCD_OPC_Decode, 158, 7, 120, // Opcode: FCMLA_ZZZI_H /* 17436 */ MCD_OPC_FilterValue, 2, 131, 15, 1, // Skip to: 86948 /* 17441 */ MCD_OPC_CheckPredicate, 0, 126, 15, 1, // Skip to: 86948 /* 17446 */ MCD_OPC_CheckField, 10, 2, 0, 119, 15, 1, // Skip to: 86948 /* 17453 */ MCD_OPC_Decode, 147, 11, 121, // Opcode: FMUL_ZZZI_S /* 17457 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 17507 /* 17462 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 17465 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17479 /* 17470 */ MCD_OPC_CheckPredicate, 0, 97, 15, 1, // Skip to: 86948 /* 17475 */ MCD_OPC_Decode, 155, 7, 116, // Opcode: FCMLA_ZPmZZ_D /* 17479 */ MCD_OPC_FilterValue, 1, 88, 15, 1, // Skip to: 86948 /* 17484 */ MCD_OPC_CheckPredicate, 0, 83, 15, 1, // Skip to: 86948 /* 17489 */ MCD_OPC_CheckField, 17, 4, 0, 76, 15, 1, // Skip to: 86948 /* 17496 */ MCD_OPC_CheckField, 13, 2, 0, 69, 15, 1, // Skip to: 86948 /* 17503 */ MCD_OPC_Decode, 203, 6, 119, // Opcode: FCADD_ZPmZ_D /* 17507 */ MCD_OPC_FilterValue, 3, 60, 15, 1, // Skip to: 86948 /* 17512 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17515 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 17551 /* 17520 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 17523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17537 /* 17528 */ MCD_OPC_CheckPredicate, 0, 39, 15, 1, // Skip to: 86948 /* 17533 */ MCD_OPC_Decode, 180, 10, 115, // Opcode: FMLA_ZZZI_D /* 17537 */ MCD_OPC_FilterValue, 1, 30, 15, 1, // Skip to: 86948 /* 17542 */ MCD_OPC_CheckPredicate, 0, 25, 15, 1, // Skip to: 86948 /* 17547 */ MCD_OPC_Decode, 199, 10, 115, // Opcode: FMLS_ZZZI_D /* 17551 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17565 /* 17556 */ MCD_OPC_CheckPredicate, 0, 11, 15, 1, // Skip to: 86948 /* 17561 */ MCD_OPC_Decode, 159, 7, 122, // Opcode: FCMLA_ZZZI_S /* 17565 */ MCD_OPC_FilterValue, 2, 2, 15, 1, // Skip to: 86948 /* 17570 */ MCD_OPC_CheckPredicate, 0, 253, 14, 1, // Skip to: 86948 /* 17575 */ MCD_OPC_CheckField, 10, 2, 0, 246, 14, 1, // Skip to: 86948 /* 17582 */ MCD_OPC_Decode, 145, 11, 123, // Opcode: FMUL_ZZZI_D /* 17586 */ MCD_OPC_FilterValue, 2, 73, 5, 0, // Skip to: 18944 /* 17591 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 17594 */ MCD_OPC_FilterValue, 0, 109, 0, 0, // Skip to: 17708 /* 17599 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 17602 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 17694 /* 17607 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 17610 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17624 /* 17615 */ MCD_OPC_CheckPredicate, 0, 208, 14, 1, // Skip to: 86948 /* 17620 */ MCD_OPC_Decode, 196, 6, 27, // Opcode: FADD_ZZZ_H /* 17624 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17638 /* 17629 */ MCD_OPC_CheckPredicate, 0, 194, 14, 1, // Skip to: 86948 /* 17634 */ MCD_OPC_Decode, 225, 12, 27, // Opcode: FSUB_ZZZ_H /* 17638 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 17652 /* 17643 */ MCD_OPC_CheckPredicate, 0, 180, 14, 1, // Skip to: 86948 /* 17648 */ MCD_OPC_Decode, 149, 11, 27, // Opcode: FMUL_ZZZ_H /* 17652 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 17666 /* 17657 */ MCD_OPC_CheckPredicate, 0, 166, 14, 1, // Skip to: 86948 /* 17662 */ MCD_OPC_Decode, 236, 12, 27, // Opcode: FTSMUL_ZZZ_H /* 17666 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 17680 /* 17671 */ MCD_OPC_CheckPredicate, 0, 152, 14, 1, // Skip to: 86948 /* 17676 */ MCD_OPC_Decode, 211, 11, 27, // Opcode: FRECPS_ZZZ_H /* 17680 */ MCD_OPC_FilterValue, 7, 143, 14, 1, // Skip to: 86948 /* 17685 */ MCD_OPC_CheckPredicate, 0, 138, 14, 1, // Skip to: 86948 /* 17690 */ MCD_OPC_Decode, 188, 12, 27, // Opcode: FRSQRTS_ZZZ_H /* 17694 */ MCD_OPC_FilterValue, 3, 129, 14, 1, // Skip to: 86948 /* 17699 */ MCD_OPC_CheckPredicate, 0, 124, 14, 1, // Skip to: 86948 /* 17704 */ MCD_OPC_Decode, 178, 10, 6, // Opcode: FMLA_ZPmZZ_H /* 17708 */ MCD_OPC_FilterValue, 1, 9, 1, 0, // Skip to: 17978 /* 17713 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 17716 */ MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 17964 /* 17721 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 17724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17738 /* 17729 */ MCD_OPC_CheckPredicate, 0, 94, 14, 1, // Skip to: 86948 /* 17734 */ MCD_OPC_Decode, 187, 6, 3, // Opcode: FADDV_VPZ_H /* 17738 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 17752 /* 17743 */ MCD_OPC_CheckPredicate, 0, 80, 14, 1, // Skip to: 86948 /* 17748 */ MCD_OPC_Decode, 207, 9, 3, // Opcode: FMAXNMV_VPZ_H /* 17752 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 17766 /* 17757 */ MCD_OPC_CheckPredicate, 0, 66, 14, 1, // Skip to: 86948 /* 17762 */ MCD_OPC_Decode, 135, 10, 3, // Opcode: FMINNMV_VPZ_H /* 17766 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 17780 /* 17771 */ MCD_OPC_CheckPredicate, 0, 52, 14, 1, // Skip to: 86948 /* 17776 */ MCD_OPC_Decode, 233, 9, 3, // Opcode: FMAXV_VPZ_H /* 17780 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 17794 /* 17785 */ MCD_OPC_CheckPredicate, 0, 38, 14, 1, // Skip to: 86948 /* 17790 */ MCD_OPC_Decode, 161, 10, 3, // Opcode: FMINV_VPZ_H /* 17794 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 17815 /* 17799 */ MCD_OPC_CheckPredicate, 0, 24, 14, 1, // Skip to: 86948 /* 17804 */ MCD_OPC_CheckField, 10, 3, 4, 17, 14, 1, // Skip to: 86948 /* 17811 */ MCD_OPC_Decode, 197, 11, 38, // Opcode: FRECPE_ZZ_H /* 17815 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 17836 /* 17820 */ MCD_OPC_CheckPredicate, 0, 3, 14, 1, // Skip to: 86948 /* 17825 */ MCD_OPC_CheckField, 10, 3, 4, 252, 13, 1, // Skip to: 86948 /* 17832 */ MCD_OPC_Decode, 174, 12, 38, // Opcode: FRSQRTE_ZZ_H /* 17836 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 17872 /* 17841 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 17844 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17858 /* 17849 */ MCD_OPC_CheckPredicate, 0, 230, 13, 1, // Skip to: 86948 /* 17854 */ MCD_OPC_Decode, 243, 6, 124, // Opcode: FCMGE_PPzZ0_H /* 17858 */ MCD_OPC_FilterValue, 1, 221, 13, 1, // Skip to: 86948 /* 17863 */ MCD_OPC_CheckPredicate, 0, 216, 13, 1, // Skip to: 86948 /* 17868 */ MCD_OPC_Decode, 137, 7, 124, // Opcode: FCMGT_PPzZ0_H /* 17872 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 17908 /* 17877 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 17880 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17894 /* 17885 */ MCD_OPC_CheckPredicate, 0, 194, 13, 1, // Skip to: 86948 /* 17890 */ MCD_OPC_Decode, 180, 7, 124, // Opcode: FCMLT_PPzZ0_H /* 17894 */ MCD_OPC_FilterValue, 1, 185, 13, 1, // Skip to: 86948 /* 17899 */ MCD_OPC_CheckPredicate, 0, 180, 13, 1, // Skip to: 86948 /* 17904 */ MCD_OPC_Decode, 169, 7, 124, // Opcode: FCMLE_PPzZ0_H /* 17908 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 17929 /* 17913 */ MCD_OPC_CheckPredicate, 0, 166, 13, 1, // Skip to: 86948 /* 17918 */ MCD_OPC_CheckField, 4, 1, 0, 159, 13, 1, // Skip to: 86948 /* 17925 */ MCD_OPC_Decode, 221, 6, 124, // Opcode: FCMEQ_PPzZ0_H /* 17929 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 17950 /* 17934 */ MCD_OPC_CheckPredicate, 0, 145, 13, 1, // Skip to: 86948 /* 17939 */ MCD_OPC_CheckField, 4, 1, 0, 138, 13, 1, // Skip to: 86948 /* 17946 */ MCD_OPC_Decode, 191, 7, 124, // Opcode: FCMNE_PPzZ0_H /* 17950 */ MCD_OPC_FilterValue, 24, 129, 13, 1, // Skip to: 86948 /* 17955 */ MCD_OPC_CheckPredicate, 0, 124, 13, 1, // Skip to: 86948 /* 17960 */ MCD_OPC_Decode, 173, 6, 67, // Opcode: FADDA_VPZ_H /* 17964 */ MCD_OPC_FilterValue, 3, 115, 13, 1, // Skip to: 86948 /* 17969 */ MCD_OPC_CheckPredicate, 0, 110, 13, 1, // Skip to: 86948 /* 17974 */ MCD_OPC_Decode, 197, 10, 6, // Opcode: FMLS_ZPmZZ_H /* 17978 */ MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 18036 /* 17983 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 17986 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18022 /* 17991 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 17994 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18008 /* 17999 */ MCD_OPC_CheckPredicate, 0, 80, 13, 1, // Skip to: 86948 /* 18004 */ MCD_OPC_Decode, 246, 6, 81, // Opcode: FCMGE_PPzZZ_H /* 18008 */ MCD_OPC_FilterValue, 1, 71, 13, 1, // Skip to: 86948 /* 18013 */ MCD_OPC_CheckPredicate, 0, 66, 13, 1, // Skip to: 86948 /* 18018 */ MCD_OPC_Decode, 140, 7, 81, // Opcode: FCMGT_PPzZZ_H /* 18022 */ MCD_OPC_FilterValue, 3, 57, 13, 1, // Skip to: 86948 /* 18027 */ MCD_OPC_CheckPredicate, 0, 52, 13, 1, // Skip to: 86948 /* 18032 */ MCD_OPC_Decode, 182, 11, 6, // Opcode: FNMLA_ZPmZZ_H /* 18036 */ MCD_OPC_FilterValue, 3, 53, 0, 0, // Skip to: 18094 /* 18041 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 18044 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18080 /* 18049 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 18052 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18066 /* 18057 */ MCD_OPC_CheckPredicate, 0, 22, 13, 1, // Skip to: 86948 /* 18062 */ MCD_OPC_Decode, 224, 6, 81, // Opcode: FCMEQ_PPzZZ_H /* 18066 */ MCD_OPC_FilterValue, 1, 13, 13, 1, // Skip to: 86948 /* 18071 */ MCD_OPC_CheckPredicate, 0, 8, 13, 1, // Skip to: 86948 /* 18076 */ MCD_OPC_Decode, 194, 7, 81, // Opcode: FCMNE_PPzZZ_H /* 18080 */ MCD_OPC_FilterValue, 3, 255, 12, 1, // Skip to: 86948 /* 18085 */ MCD_OPC_CheckPredicate, 0, 250, 12, 1, // Skip to: 86948 /* 18090 */ MCD_OPC_Decode, 185, 11, 6, // Opcode: FNMLS_ZPmZZ_H /* 18094 */ MCD_OPC_FilterValue, 4, 164, 1, 0, // Skip to: 18519 /* 18099 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 18102 */ MCD_OPC_FilterValue, 2, 142, 1, 0, // Skip to: 18505 /* 18107 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... /* 18110 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 18230 /* 18115 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 18118 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18132 /* 18123 */ MCD_OPC_CheckPredicate, 0, 212, 12, 1, // Skip to: 86948 /* 18128 */ MCD_OPC_Decode, 193, 6, 0, // Opcode: FADD_ZPmZ_H /* 18132 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18146 /* 18137 */ MCD_OPC_CheckPredicate, 0, 198, 12, 1, // Skip to: 86948 /* 18142 */ MCD_OPC_Decode, 222, 12, 0, // Opcode: FSUB_ZPmZ_H /* 18146 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18160 /* 18151 */ MCD_OPC_CheckPredicate, 0, 184, 12, 1, // Skip to: 86948 /* 18156 */ MCD_OPC_Decode, 143, 11, 0, // Opcode: FMUL_ZPmZ_H /* 18160 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 18174 /* 18165 */ MCD_OPC_CheckPredicate, 0, 170, 12, 1, // Skip to: 86948 /* 18170 */ MCD_OPC_Decode, 215, 12, 0, // Opcode: FSUBR_ZPmZ_H /* 18174 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18188 /* 18179 */ MCD_OPC_CheckPredicate, 0, 156, 12, 1, // Skip to: 86948 /* 18184 */ MCD_OPC_Decode, 216, 9, 0, // Opcode: FMAXNM_ZPmZ_H /* 18188 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 18202 /* 18193 */ MCD_OPC_CheckPredicate, 0, 142, 12, 1, // Skip to: 86948 /* 18198 */ MCD_OPC_Decode, 144, 10, 0, // Opcode: FMINNM_ZPmZ_H /* 18202 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 18216 /* 18207 */ MCD_OPC_CheckPredicate, 0, 128, 12, 1, // Skip to: 86948 /* 18212 */ MCD_OPC_Decode, 242, 9, 0, // Opcode: FMAX_ZPmZ_H /* 18216 */ MCD_OPC_FilterValue, 7, 119, 12, 1, // Skip to: 86948 /* 18221 */ MCD_OPC_CheckPredicate, 0, 114, 12, 1, // Skip to: 86948 /* 18226 */ MCD_OPC_Decode, 170, 10, 0, // Opcode: FMIN_ZPmZ_H /* 18230 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 18308 /* 18235 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 18238 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18252 /* 18243 */ MCD_OPC_CheckPredicate, 0, 92, 12, 1, // Skip to: 86948 /* 18248 */ MCD_OPC_Decode, 132, 6, 0, // Opcode: FABD_ZPmZ_H /* 18252 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18266 /* 18257 */ MCD_OPC_CheckPredicate, 0, 78, 12, 1, // Skip to: 86948 /* 18262 */ MCD_OPC_Decode, 196, 12, 0, // Opcode: FSCALE_ZPmZ_H /* 18266 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18280 /* 18271 */ MCD_OPC_CheckPredicate, 0, 64, 12, 1, // Skip to: 86948 /* 18276 */ MCD_OPC_Decode, 252, 10, 0, // Opcode: FMULX_ZPmZ_H /* 18280 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18294 /* 18285 */ MCD_OPC_CheckPredicate, 0, 50, 12, 1, // Skip to: 86948 /* 18290 */ MCD_OPC_Decode, 169, 9, 0, // Opcode: FDIVR_ZPmZ_H /* 18294 */ MCD_OPC_FilterValue, 5, 41, 12, 1, // Skip to: 86948 /* 18299 */ MCD_OPC_CheckPredicate, 0, 36, 12, 1, // Skip to: 86948 /* 18304 */ MCD_OPC_Decode, 173, 9, 0, // Opcode: FDIV_ZPmZ_H /* 18308 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18329 /* 18313 */ MCD_OPC_CheckPredicate, 0, 22, 12, 1, // Skip to: 86948 /* 18318 */ MCD_OPC_CheckField, 10, 3, 0, 15, 12, 1, // Skip to: 86948 /* 18325 */ MCD_OPC_Decode, 233, 12, 125, // Opcode: FTMAD_ZZI_H /* 18329 */ MCD_OPC_FilterValue, 3, 6, 12, 1, // Skip to: 86948 /* 18334 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 18337 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 18358 /* 18342 */ MCD_OPC_CheckPredicate, 0, 249, 11, 1, // Skip to: 86948 /* 18347 */ MCD_OPC_CheckField, 6, 4, 0, 242, 11, 1, // Skip to: 86948 /* 18354 */ MCD_OPC_Decode, 190, 6, 126, // Opcode: FADD_ZPmI_H /* 18358 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 18379 /* 18363 */ MCD_OPC_CheckPredicate, 0, 228, 11, 1, // Skip to: 86948 /* 18368 */ MCD_OPC_CheckField, 6, 4, 0, 221, 11, 1, // Skip to: 86948 /* 18375 */ MCD_OPC_Decode, 219, 12, 126, // Opcode: FSUB_ZPmI_H /* 18379 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18400 /* 18384 */ MCD_OPC_CheckPredicate, 0, 207, 11, 1, // Skip to: 86948 /* 18389 */ MCD_OPC_CheckField, 6, 4, 0, 200, 11, 1, // Skip to: 86948 /* 18396 */ MCD_OPC_Decode, 140, 11, 126, // Opcode: FMUL_ZPmI_H /* 18400 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 18421 /* 18405 */ MCD_OPC_CheckPredicate, 0, 186, 11, 1, // Skip to: 86948 /* 18410 */ MCD_OPC_CheckField, 6, 4, 0, 179, 11, 1, // Skip to: 86948 /* 18417 */ MCD_OPC_Decode, 212, 12, 126, // Opcode: FSUBR_ZPmI_H /* 18421 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 18442 /* 18426 */ MCD_OPC_CheckPredicate, 0, 165, 11, 1, // Skip to: 86948 /* 18431 */ MCD_OPC_CheckField, 6, 4, 0, 158, 11, 1, // Skip to: 86948 /* 18438 */ MCD_OPC_Decode, 213, 9, 126, // Opcode: FMAXNM_ZPmI_H /* 18442 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 18463 /* 18447 */ MCD_OPC_CheckPredicate, 0, 144, 11, 1, // Skip to: 86948 /* 18452 */ MCD_OPC_CheckField, 6, 4, 0, 137, 11, 1, // Skip to: 86948 /* 18459 */ MCD_OPC_Decode, 141, 10, 126, // Opcode: FMINNM_ZPmI_H /* 18463 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 18484 /* 18468 */ MCD_OPC_CheckPredicate, 0, 123, 11, 1, // Skip to: 86948 /* 18473 */ MCD_OPC_CheckField, 6, 4, 0, 116, 11, 1, // Skip to: 86948 /* 18480 */ MCD_OPC_Decode, 239, 9, 126, // Opcode: FMAX_ZPmI_H /* 18484 */ MCD_OPC_FilterValue, 7, 107, 11, 1, // Skip to: 86948 /* 18489 */ MCD_OPC_CheckPredicate, 0, 102, 11, 1, // Skip to: 86948 /* 18494 */ MCD_OPC_CheckField, 6, 4, 0, 95, 11, 1, // Skip to: 86948 /* 18501 */ MCD_OPC_Decode, 167, 10, 126, // Opcode: FMIN_ZPmI_H /* 18505 */ MCD_OPC_FilterValue, 3, 86, 11, 1, // Skip to: 86948 /* 18510 */ MCD_OPC_CheckPredicate, 0, 81, 11, 1, // Skip to: 86948 /* 18515 */ MCD_OPC_Decode, 191, 9, 6, // Opcode: FMAD_ZPmZZ_H /* 18519 */ MCD_OPC_FilterValue, 5, 63, 1, 0, // Skip to: 18843 /* 18524 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 18527 */ MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 18829 /* 18532 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 18535 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18549 /* 18540 */ MCD_OPC_CheckPredicate, 0, 51, 11, 1, // Skip to: 86948 /* 18545 */ MCD_OPC_Decode, 133, 12, 5, // Opcode: FRINTN_ZPmZ_H /* 18549 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18563 /* 18554 */ MCD_OPC_CheckPredicate, 0, 37, 11, 1, // Skip to: 86948 /* 18559 */ MCD_OPC_Decode, 144, 12, 5, // Opcode: FRINTP_ZPmZ_H /* 18563 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18577 /* 18568 */ MCD_OPC_CheckPredicate, 0, 23, 11, 1, // Skip to: 86948 /* 18573 */ MCD_OPC_Decode, 250, 11, 5, // Opcode: FRINTM_ZPmZ_H /* 18577 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 18591 /* 18582 */ MCD_OPC_CheckPredicate, 0, 9, 11, 1, // Skip to: 86948 /* 18587 */ MCD_OPC_Decode, 166, 12, 5, // Opcode: FRINTZ_ZPmZ_H /* 18591 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18605 /* 18596 */ MCD_OPC_CheckPredicate, 0, 251, 10, 1, // Skip to: 86948 /* 18601 */ MCD_OPC_Decode, 228, 11, 5, // Opcode: FRINTA_ZPmZ_H /* 18605 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 18619 /* 18610 */ MCD_OPC_CheckPredicate, 0, 237, 10, 1, // Skip to: 86948 /* 18615 */ MCD_OPC_Decode, 155, 12, 5, // Opcode: FRINTX_ZPmZ_H /* 18619 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 18633 /* 18624 */ MCD_OPC_CheckPredicate, 0, 223, 10, 1, // Skip to: 86948 /* 18629 */ MCD_OPC_Decode, 239, 11, 5, // Opcode: FRINTI_ZPmZ_H /* 18633 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 18647 /* 18638 */ MCD_OPC_CheckPredicate, 0, 209, 10, 1, // Skip to: 86948 /* 18643 */ MCD_OPC_Decode, 219, 11, 5, // Opcode: FRECPX_ZPmZ_H /* 18647 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 18661 /* 18652 */ MCD_OPC_CheckPredicate, 0, 195, 10, 1, // Skip to: 86948 /* 18657 */ MCD_OPC_Decode, 202, 12, 5, // Opcode: FSQRT_ZPmZ_H /* 18661 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 18675 /* 18666 */ MCD_OPC_CheckPredicate, 0, 181, 10, 1, // Skip to: 86948 /* 18671 */ MCD_OPC_Decode, 199, 22, 5, // Opcode: SCVTF_ZPmZ_HtoH /* 18675 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 18689 /* 18680 */ MCD_OPC_CheckPredicate, 0, 167, 10, 1, // Skip to: 86948 /* 18685 */ MCD_OPC_Decode, 186, 31, 5, // Opcode: UCVTF_ZPmZ_HtoH /* 18689 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 18703 /* 18694 */ MCD_OPC_CheckPredicate, 0, 153, 10, 1, // Skip to: 86948 /* 18699 */ MCD_OPC_Decode, 201, 22, 5, // Opcode: SCVTF_ZPmZ_StoH /* 18703 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 18717 /* 18708 */ MCD_OPC_CheckPredicate, 0, 139, 10, 1, // Skip to: 86948 /* 18713 */ MCD_OPC_Decode, 188, 31, 5, // Opcode: UCVTF_ZPmZ_StoH /* 18717 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 18731 /* 18722 */ MCD_OPC_CheckPredicate, 0, 125, 10, 1, // Skip to: 86948 /* 18727 */ MCD_OPC_Decode, 197, 22, 5, // Opcode: SCVTF_ZPmZ_DtoH /* 18731 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 18745 /* 18736 */ MCD_OPC_CheckPredicate, 0, 111, 10, 1, // Skip to: 86948 /* 18741 */ MCD_OPC_Decode, 184, 31, 5, // Opcode: UCVTF_ZPmZ_DtoH /* 18745 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 18759 /* 18750 */ MCD_OPC_CheckPredicate, 0, 97, 10, 1, // Skip to: 86948 /* 18755 */ MCD_OPC_Decode, 233, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoH /* 18759 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 18773 /* 18764 */ MCD_OPC_CheckPredicate, 0, 83, 10, 1, // Skip to: 86948 /* 18769 */ MCD_OPC_Decode, 140, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoH /* 18773 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 18787 /* 18778 */ MCD_OPC_CheckPredicate, 0, 69, 10, 1, // Skip to: 86948 /* 18783 */ MCD_OPC_Decode, 234, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoS /* 18787 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 18801 /* 18792 */ MCD_OPC_CheckPredicate, 0, 55, 10, 1, // Skip to: 86948 /* 18797 */ MCD_OPC_Decode, 141, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoS /* 18801 */ MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 18815 /* 18806 */ MCD_OPC_CheckPredicate, 0, 41, 10, 1, // Skip to: 86948 /* 18811 */ MCD_OPC_Decode, 232, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoD /* 18815 */ MCD_OPC_FilterValue, 31, 32, 10, 1, // Skip to: 86948 /* 18820 */ MCD_OPC_CheckPredicate, 0, 27, 10, 1, // Skip to: 86948 /* 18825 */ MCD_OPC_Decode, 139, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoD /* 18829 */ MCD_OPC_FilterValue, 3, 18, 10, 1, // Skip to: 86948 /* 18834 */ MCD_OPC_CheckPredicate, 0, 13, 10, 1, // Skip to: 86948 /* 18839 */ MCD_OPC_Decode, 240, 10, 6, // Opcode: FMSB_ZPmZZ_H /* 18843 */ MCD_OPC_FilterValue, 6, 53, 0, 0, // Skip to: 18901 /* 18848 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 18851 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18887 /* 18856 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 18859 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18873 /* 18864 */ MCD_OPC_CheckPredicate, 0, 239, 9, 1, // Skip to: 86948 /* 18869 */ MCD_OPC_Decode, 209, 7, 81, // Opcode: FCMUO_PPzZZ_H /* 18873 */ MCD_OPC_FilterValue, 1, 230, 9, 1, // Skip to: 86948 /* 18878 */ MCD_OPC_CheckPredicate, 0, 225, 9, 1, // Skip to: 86948 /* 18883 */ MCD_OPC_Decode, 154, 6, 81, // Opcode: FACGE_PPzZZ_H /* 18887 */ MCD_OPC_FilterValue, 3, 216, 9, 1, // Skip to: 86948 /* 18892 */ MCD_OPC_CheckPredicate, 0, 211, 9, 1, // Skip to: 86948 /* 18897 */ MCD_OPC_Decode, 179, 11, 6, // Opcode: FNMAD_ZPmZZ_H /* 18901 */ MCD_OPC_FilterValue, 7, 202, 9, 1, // Skip to: 86948 /* 18906 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 18909 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18930 /* 18914 */ MCD_OPC_CheckPredicate, 0, 189, 9, 1, // Skip to: 86948 /* 18919 */ MCD_OPC_CheckField, 4, 1, 1, 182, 9, 1, // Skip to: 86948 /* 18926 */ MCD_OPC_Decode, 165, 6, 81, // Opcode: FACGT_PPzZZ_H /* 18930 */ MCD_OPC_FilterValue, 3, 173, 9, 1, // Skip to: 86948 /* 18935 */ MCD_OPC_CheckPredicate, 0, 168, 9, 1, // Skip to: 86948 /* 18940 */ MCD_OPC_Decode, 188, 11, 6, // Opcode: FNMSB_ZPmZZ_H /* 18944 */ MCD_OPC_FilterValue, 3, 159, 9, 1, // Skip to: 86948 /* 18949 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 18952 */ MCD_OPC_FilterValue, 0, 215, 0, 0, // Skip to: 19172 /* 18957 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 18960 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 19052 /* 18965 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 18968 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18982 /* 18973 */ MCD_OPC_CheckPredicate, 0, 130, 9, 1, // Skip to: 86948 /* 18978 */ MCD_OPC_Decode, 197, 6, 27, // Opcode: FADD_ZZZ_S /* 18982 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18996 /* 18987 */ MCD_OPC_CheckPredicate, 0, 116, 9, 1, // Skip to: 86948 /* 18992 */ MCD_OPC_Decode, 226, 12, 27, // Opcode: FSUB_ZZZ_S /* 18996 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19010 /* 19001 */ MCD_OPC_CheckPredicate, 0, 102, 9, 1, // Skip to: 86948 /* 19006 */ MCD_OPC_Decode, 150, 11, 27, // Opcode: FMUL_ZZZ_S /* 19010 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 19024 /* 19015 */ MCD_OPC_CheckPredicate, 0, 88, 9, 1, // Skip to: 86948 /* 19020 */ MCD_OPC_Decode, 237, 12, 27, // Opcode: FTSMUL_ZZZ_S /* 19024 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19038 /* 19029 */ MCD_OPC_CheckPredicate, 0, 74, 9, 1, // Skip to: 86948 /* 19034 */ MCD_OPC_Decode, 212, 11, 27, // Opcode: FRECPS_ZZZ_S /* 19038 */ MCD_OPC_FilterValue, 7, 65, 9, 1, // Skip to: 86948 /* 19043 */ MCD_OPC_CheckPredicate, 0, 60, 9, 1, // Skip to: 86948 /* 19048 */ MCD_OPC_Decode, 189, 12, 27, // Opcode: FRSQRTS_ZZZ_S /* 19052 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19066 /* 19057 */ MCD_OPC_CheckPredicate, 0, 46, 9, 1, // Skip to: 86948 /* 19062 */ MCD_OPC_Decode, 179, 10, 6, // Opcode: FMLA_ZPmZZ_S /* 19066 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 19158 /* 19071 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 19074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19088 /* 19079 */ MCD_OPC_CheckPredicate, 0, 24, 9, 1, // Skip to: 86948 /* 19084 */ MCD_OPC_Decode, 195, 6, 27, // Opcode: FADD_ZZZ_D /* 19088 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19102 /* 19093 */ MCD_OPC_CheckPredicate, 0, 10, 9, 1, // Skip to: 86948 /* 19098 */ MCD_OPC_Decode, 224, 12, 27, // Opcode: FSUB_ZZZ_D /* 19102 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19116 /* 19107 */ MCD_OPC_CheckPredicate, 0, 252, 8, 1, // Skip to: 86948 /* 19112 */ MCD_OPC_Decode, 148, 11, 27, // Opcode: FMUL_ZZZ_D /* 19116 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 19130 /* 19121 */ MCD_OPC_CheckPredicate, 0, 238, 8, 1, // Skip to: 86948 /* 19126 */ MCD_OPC_Decode, 235, 12, 27, // Opcode: FTSMUL_ZZZ_D /* 19130 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19144 /* 19135 */ MCD_OPC_CheckPredicate, 0, 224, 8, 1, // Skip to: 86948 /* 19140 */ MCD_OPC_Decode, 210, 11, 27, // Opcode: FRECPS_ZZZ_D /* 19144 */ MCD_OPC_FilterValue, 7, 215, 8, 1, // Skip to: 86948 /* 19149 */ MCD_OPC_CheckPredicate, 0, 210, 8, 1, // Skip to: 86948 /* 19154 */ MCD_OPC_Decode, 187, 12, 27, // Opcode: FRSQRTS_ZZZ_D /* 19158 */ MCD_OPC_FilterValue, 3, 201, 8, 1, // Skip to: 86948 /* 19163 */ MCD_OPC_CheckPredicate, 0, 196, 8, 1, // Skip to: 86948 /* 19168 */ MCD_OPC_Decode, 177, 10, 6, // Opcode: FMLA_ZPmZZ_D /* 19172 */ MCD_OPC_FilterValue, 1, 15, 2, 0, // Skip to: 19704 /* 19177 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 19180 */ MCD_OPC_FilterValue, 0, 243, 0, 0, // Skip to: 19428 /* 19185 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 19188 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19202 /* 19193 */ MCD_OPC_CheckPredicate, 0, 166, 8, 1, // Skip to: 86948 /* 19198 */ MCD_OPC_Decode, 188, 6, 14, // Opcode: FADDV_VPZ_S /* 19202 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 19216 /* 19207 */ MCD_OPC_CheckPredicate, 0, 152, 8, 1, // Skip to: 86948 /* 19212 */ MCD_OPC_Decode, 208, 9, 14, // Opcode: FMAXNMV_VPZ_S /* 19216 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 19230 /* 19221 */ MCD_OPC_CheckPredicate, 0, 138, 8, 1, // Skip to: 86948 /* 19226 */ MCD_OPC_Decode, 136, 10, 14, // Opcode: FMINNMV_VPZ_S /* 19230 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19244 /* 19235 */ MCD_OPC_CheckPredicate, 0, 124, 8, 1, // Skip to: 86948 /* 19240 */ MCD_OPC_Decode, 234, 9, 14, // Opcode: FMAXV_VPZ_S /* 19244 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 19258 /* 19249 */ MCD_OPC_CheckPredicate, 0, 110, 8, 1, // Skip to: 86948 /* 19254 */ MCD_OPC_Decode, 162, 10, 14, // Opcode: FMINV_VPZ_S /* 19258 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 19279 /* 19263 */ MCD_OPC_CheckPredicate, 0, 96, 8, 1, // Skip to: 86948 /* 19268 */ MCD_OPC_CheckField, 10, 3, 4, 89, 8, 1, // Skip to: 86948 /* 19275 */ MCD_OPC_Decode, 198, 11, 38, // Opcode: FRECPE_ZZ_S /* 19279 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 19300 /* 19284 */ MCD_OPC_CheckPredicate, 0, 75, 8, 1, // Skip to: 86948 /* 19289 */ MCD_OPC_CheckField, 10, 3, 4, 68, 8, 1, // Skip to: 86948 /* 19296 */ MCD_OPC_Decode, 175, 12, 38, // Opcode: FRSQRTE_ZZ_S /* 19300 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 19336 /* 19305 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19308 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19322 /* 19313 */ MCD_OPC_CheckPredicate, 0, 46, 8, 1, // Skip to: 86948 /* 19318 */ MCD_OPC_Decode, 244, 6, 124, // Opcode: FCMGE_PPzZ0_S /* 19322 */ MCD_OPC_FilterValue, 1, 37, 8, 1, // Skip to: 86948 /* 19327 */ MCD_OPC_CheckPredicate, 0, 32, 8, 1, // Skip to: 86948 /* 19332 */ MCD_OPC_Decode, 138, 7, 124, // Opcode: FCMGT_PPzZ0_S /* 19336 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 19372 /* 19341 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19344 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19358 /* 19349 */ MCD_OPC_CheckPredicate, 0, 10, 8, 1, // Skip to: 86948 /* 19354 */ MCD_OPC_Decode, 181, 7, 124, // Opcode: FCMLT_PPzZ0_S /* 19358 */ MCD_OPC_FilterValue, 1, 1, 8, 1, // Skip to: 86948 /* 19363 */ MCD_OPC_CheckPredicate, 0, 252, 7, 1, // Skip to: 86948 /* 19368 */ MCD_OPC_Decode, 170, 7, 124, // Opcode: FCMLE_PPzZ0_S /* 19372 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 19393 /* 19377 */ MCD_OPC_CheckPredicate, 0, 238, 7, 1, // Skip to: 86948 /* 19382 */ MCD_OPC_CheckField, 4, 1, 0, 231, 7, 1, // Skip to: 86948 /* 19389 */ MCD_OPC_Decode, 222, 6, 124, // Opcode: FCMEQ_PPzZ0_S /* 19393 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 19414 /* 19398 */ MCD_OPC_CheckPredicate, 0, 217, 7, 1, // Skip to: 86948 /* 19403 */ MCD_OPC_CheckField, 4, 1, 0, 210, 7, 1, // Skip to: 86948 /* 19410 */ MCD_OPC_Decode, 192, 7, 124, // Opcode: FCMNE_PPzZ0_S /* 19414 */ MCD_OPC_FilterValue, 24, 201, 7, 1, // Skip to: 86948 /* 19419 */ MCD_OPC_CheckPredicate, 0, 196, 7, 1, // Skip to: 86948 /* 19424 */ MCD_OPC_Decode, 174, 6, 73, // Opcode: FADDA_VPZ_S /* 19428 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19442 /* 19433 */ MCD_OPC_CheckPredicate, 0, 182, 7, 1, // Skip to: 86948 /* 19438 */ MCD_OPC_Decode, 198, 10, 6, // Opcode: FMLS_ZPmZZ_S /* 19442 */ MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 19690 /* 19447 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 19450 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19464 /* 19455 */ MCD_OPC_CheckPredicate, 0, 160, 7, 1, // Skip to: 86948 /* 19460 */ MCD_OPC_Decode, 186, 6, 1, // Opcode: FADDV_VPZ_D /* 19464 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 19478 /* 19469 */ MCD_OPC_CheckPredicate, 0, 146, 7, 1, // Skip to: 86948 /* 19474 */ MCD_OPC_Decode, 206, 9, 1, // Opcode: FMAXNMV_VPZ_D /* 19478 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 19492 /* 19483 */ MCD_OPC_CheckPredicate, 0, 132, 7, 1, // Skip to: 86948 /* 19488 */ MCD_OPC_Decode, 134, 10, 1, // Opcode: FMINNMV_VPZ_D /* 19492 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19506 /* 19497 */ MCD_OPC_CheckPredicate, 0, 118, 7, 1, // Skip to: 86948 /* 19502 */ MCD_OPC_Decode, 232, 9, 1, // Opcode: FMAXV_VPZ_D /* 19506 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 19520 /* 19511 */ MCD_OPC_CheckPredicate, 0, 104, 7, 1, // Skip to: 86948 /* 19516 */ MCD_OPC_Decode, 160, 10, 1, // Opcode: FMINV_VPZ_D /* 19520 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 19541 /* 19525 */ MCD_OPC_CheckPredicate, 0, 90, 7, 1, // Skip to: 86948 /* 19530 */ MCD_OPC_CheckField, 10, 3, 4, 83, 7, 1, // Skip to: 86948 /* 19537 */ MCD_OPC_Decode, 196, 11, 38, // Opcode: FRECPE_ZZ_D /* 19541 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 19562 /* 19546 */ MCD_OPC_CheckPredicate, 0, 69, 7, 1, // Skip to: 86948 /* 19551 */ MCD_OPC_CheckField, 10, 3, 4, 62, 7, 1, // Skip to: 86948 /* 19558 */ MCD_OPC_Decode, 173, 12, 38, // Opcode: FRSQRTE_ZZ_D /* 19562 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 19598 /* 19567 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19570 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19584 /* 19575 */ MCD_OPC_CheckPredicate, 0, 40, 7, 1, // Skip to: 86948 /* 19580 */ MCD_OPC_Decode, 242, 6, 124, // Opcode: FCMGE_PPzZ0_D /* 19584 */ MCD_OPC_FilterValue, 1, 31, 7, 1, // Skip to: 86948 /* 19589 */ MCD_OPC_CheckPredicate, 0, 26, 7, 1, // Skip to: 86948 /* 19594 */ MCD_OPC_Decode, 136, 7, 124, // Opcode: FCMGT_PPzZ0_D /* 19598 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 19634 /* 19603 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19606 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19620 /* 19611 */ MCD_OPC_CheckPredicate, 0, 4, 7, 1, // Skip to: 86948 /* 19616 */ MCD_OPC_Decode, 179, 7, 124, // Opcode: FCMLT_PPzZ0_D /* 19620 */ MCD_OPC_FilterValue, 1, 251, 6, 1, // Skip to: 86948 /* 19625 */ MCD_OPC_CheckPredicate, 0, 246, 6, 1, // Skip to: 86948 /* 19630 */ MCD_OPC_Decode, 168, 7, 124, // Opcode: FCMLE_PPzZ0_D /* 19634 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 19655 /* 19639 */ MCD_OPC_CheckPredicate, 0, 232, 6, 1, // Skip to: 86948 /* 19644 */ MCD_OPC_CheckField, 4, 1, 0, 225, 6, 1, // Skip to: 86948 /* 19651 */ MCD_OPC_Decode, 220, 6, 124, // Opcode: FCMEQ_PPzZ0_D /* 19655 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 19676 /* 19660 */ MCD_OPC_CheckPredicate, 0, 211, 6, 1, // Skip to: 86948 /* 19665 */ MCD_OPC_CheckField, 4, 1, 0, 204, 6, 1, // Skip to: 86948 /* 19672 */ MCD_OPC_Decode, 190, 7, 124, // Opcode: FCMNE_PPzZ0_D /* 19676 */ MCD_OPC_FilterValue, 24, 195, 6, 1, // Skip to: 86948 /* 19681 */ MCD_OPC_CheckPredicate, 0, 190, 6, 1, // Skip to: 86948 /* 19686 */ MCD_OPC_Decode, 172, 6, 74, // Opcode: FADDA_VPZ_D /* 19690 */ MCD_OPC_FilterValue, 3, 181, 6, 1, // Skip to: 86948 /* 19695 */ MCD_OPC_CheckPredicate, 0, 176, 6, 1, // Skip to: 86948 /* 19700 */ MCD_OPC_Decode, 196, 10, 6, // Opcode: FMLS_ZPmZZ_D /* 19704 */ MCD_OPC_FilterValue, 2, 103, 0, 0, // Skip to: 19812 /* 19709 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 19712 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 19748 /* 19717 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19720 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19734 /* 19725 */ MCD_OPC_CheckPredicate, 0, 146, 6, 1, // Skip to: 86948 /* 19730 */ MCD_OPC_Decode, 247, 6, 81, // Opcode: FCMGE_PPzZZ_S /* 19734 */ MCD_OPC_FilterValue, 1, 137, 6, 1, // Skip to: 86948 /* 19739 */ MCD_OPC_CheckPredicate, 0, 132, 6, 1, // Skip to: 86948 /* 19744 */ MCD_OPC_Decode, 141, 7, 81, // Opcode: FCMGT_PPzZZ_S /* 19748 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19762 /* 19753 */ MCD_OPC_CheckPredicate, 0, 118, 6, 1, // Skip to: 86948 /* 19758 */ MCD_OPC_Decode, 183, 11, 6, // Opcode: FNMLA_ZPmZZ_S /* 19762 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 19798 /* 19767 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19770 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19784 /* 19775 */ MCD_OPC_CheckPredicate, 0, 96, 6, 1, // Skip to: 86948 /* 19780 */ MCD_OPC_Decode, 245, 6, 81, // Opcode: FCMGE_PPzZZ_D /* 19784 */ MCD_OPC_FilterValue, 1, 87, 6, 1, // Skip to: 86948 /* 19789 */ MCD_OPC_CheckPredicate, 0, 82, 6, 1, // Skip to: 86948 /* 19794 */ MCD_OPC_Decode, 139, 7, 81, // Opcode: FCMGT_PPzZZ_D /* 19798 */ MCD_OPC_FilterValue, 3, 73, 6, 1, // Skip to: 86948 /* 19803 */ MCD_OPC_CheckPredicate, 0, 68, 6, 1, // Skip to: 86948 /* 19808 */ MCD_OPC_Decode, 181, 11, 6, // Opcode: FNMLA_ZPmZZ_D /* 19812 */ MCD_OPC_FilterValue, 3, 103, 0, 0, // Skip to: 19920 /* 19817 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 19820 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 19856 /* 19825 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19828 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19842 /* 19833 */ MCD_OPC_CheckPredicate, 0, 38, 6, 1, // Skip to: 86948 /* 19838 */ MCD_OPC_Decode, 225, 6, 81, // Opcode: FCMEQ_PPzZZ_S /* 19842 */ MCD_OPC_FilterValue, 1, 29, 6, 1, // Skip to: 86948 /* 19847 */ MCD_OPC_CheckPredicate, 0, 24, 6, 1, // Skip to: 86948 /* 19852 */ MCD_OPC_Decode, 195, 7, 81, // Opcode: FCMNE_PPzZZ_S /* 19856 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19870 /* 19861 */ MCD_OPC_CheckPredicate, 0, 10, 6, 1, // Skip to: 86948 /* 19866 */ MCD_OPC_Decode, 186, 11, 6, // Opcode: FNMLS_ZPmZZ_S /* 19870 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 19906 /* 19875 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 19878 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19892 /* 19883 */ MCD_OPC_CheckPredicate, 0, 244, 5, 1, // Skip to: 86948 /* 19888 */ MCD_OPC_Decode, 223, 6, 81, // Opcode: FCMEQ_PPzZZ_D /* 19892 */ MCD_OPC_FilterValue, 1, 235, 5, 1, // Skip to: 86948 /* 19897 */ MCD_OPC_CheckPredicate, 0, 230, 5, 1, // Skip to: 86948 /* 19902 */ MCD_OPC_Decode, 193, 7, 81, // Opcode: FCMNE_PPzZZ_D /* 19906 */ MCD_OPC_FilterValue, 3, 221, 5, 1, // Skip to: 86948 /* 19911 */ MCD_OPC_CheckPredicate, 0, 216, 5, 1, // Skip to: 86948 /* 19916 */ MCD_OPC_Decode, 184, 11, 6, // Opcode: FNMLS_ZPmZZ_D /* 19920 */ MCD_OPC_FilterValue, 4, 69, 3, 0, // Skip to: 20762 /* 19925 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 19928 */ MCD_OPC_FilterValue, 0, 142, 1, 0, // Skip to: 20331 /* 19933 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... /* 19936 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 20056 /* 19941 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 19944 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19958 /* 19949 */ MCD_OPC_CheckPredicate, 0, 178, 5, 1, // Skip to: 86948 /* 19954 */ MCD_OPC_Decode, 194, 6, 0, // Opcode: FADD_ZPmZ_S /* 19958 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19972 /* 19963 */ MCD_OPC_CheckPredicate, 0, 164, 5, 1, // Skip to: 86948 /* 19968 */ MCD_OPC_Decode, 223, 12, 0, // Opcode: FSUB_ZPmZ_S /* 19972 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19986 /* 19977 */ MCD_OPC_CheckPredicate, 0, 150, 5, 1, // Skip to: 86948 /* 19982 */ MCD_OPC_Decode, 144, 11, 0, // Opcode: FMUL_ZPmZ_S /* 19986 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20000 /* 19991 */ MCD_OPC_CheckPredicate, 0, 136, 5, 1, // Skip to: 86948 /* 19996 */ MCD_OPC_Decode, 216, 12, 0, // Opcode: FSUBR_ZPmZ_S /* 20000 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20014 /* 20005 */ MCD_OPC_CheckPredicate, 0, 122, 5, 1, // Skip to: 86948 /* 20010 */ MCD_OPC_Decode, 217, 9, 0, // Opcode: FMAXNM_ZPmZ_S /* 20014 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 20028 /* 20019 */ MCD_OPC_CheckPredicate, 0, 108, 5, 1, // Skip to: 86948 /* 20024 */ MCD_OPC_Decode, 145, 10, 0, // Opcode: FMINNM_ZPmZ_S /* 20028 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20042 /* 20033 */ MCD_OPC_CheckPredicate, 0, 94, 5, 1, // Skip to: 86948 /* 20038 */ MCD_OPC_Decode, 243, 9, 0, // Opcode: FMAX_ZPmZ_S /* 20042 */ MCD_OPC_FilterValue, 7, 85, 5, 1, // Skip to: 86948 /* 20047 */ MCD_OPC_CheckPredicate, 0, 80, 5, 1, // Skip to: 86948 /* 20052 */ MCD_OPC_Decode, 171, 10, 0, // Opcode: FMIN_ZPmZ_S /* 20056 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 20134 /* 20061 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 20064 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20078 /* 20069 */ MCD_OPC_CheckPredicate, 0, 58, 5, 1, // Skip to: 86948 /* 20074 */ MCD_OPC_Decode, 133, 6, 0, // Opcode: FABD_ZPmZ_S /* 20078 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20092 /* 20083 */ MCD_OPC_CheckPredicate, 0, 44, 5, 1, // Skip to: 86948 /* 20088 */ MCD_OPC_Decode, 197, 12, 0, // Opcode: FSCALE_ZPmZ_S /* 20092 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20106 /* 20097 */ MCD_OPC_CheckPredicate, 0, 30, 5, 1, // Skip to: 86948 /* 20102 */ MCD_OPC_Decode, 253, 10, 0, // Opcode: FMULX_ZPmZ_S /* 20106 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20120 /* 20111 */ MCD_OPC_CheckPredicate, 0, 16, 5, 1, // Skip to: 86948 /* 20116 */ MCD_OPC_Decode, 170, 9, 0, // Opcode: FDIVR_ZPmZ_S /* 20120 */ MCD_OPC_FilterValue, 5, 7, 5, 1, // Skip to: 86948 /* 20125 */ MCD_OPC_CheckPredicate, 0, 2, 5, 1, // Skip to: 86948 /* 20130 */ MCD_OPC_Decode, 174, 9, 0, // Opcode: FDIV_ZPmZ_S /* 20134 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20155 /* 20139 */ MCD_OPC_CheckPredicate, 0, 244, 4, 1, // Skip to: 86948 /* 20144 */ MCD_OPC_CheckField, 10, 3, 0, 237, 4, 1, // Skip to: 86948 /* 20151 */ MCD_OPC_Decode, 234, 12, 125, // Opcode: FTMAD_ZZI_S /* 20155 */ MCD_OPC_FilterValue, 3, 228, 4, 1, // Skip to: 86948 /* 20160 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 20163 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 20184 /* 20168 */ MCD_OPC_CheckPredicate, 0, 215, 4, 1, // Skip to: 86948 /* 20173 */ MCD_OPC_CheckField, 6, 4, 0, 208, 4, 1, // Skip to: 86948 /* 20180 */ MCD_OPC_Decode, 191, 6, 126, // Opcode: FADD_ZPmI_S /* 20184 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 20205 /* 20189 */ MCD_OPC_CheckPredicate, 0, 194, 4, 1, // Skip to: 86948 /* 20194 */ MCD_OPC_CheckField, 6, 4, 0, 187, 4, 1, // Skip to: 86948 /* 20201 */ MCD_OPC_Decode, 220, 12, 126, // Opcode: FSUB_ZPmI_S /* 20205 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20226 /* 20210 */ MCD_OPC_CheckPredicate, 0, 173, 4, 1, // Skip to: 86948 /* 20215 */ MCD_OPC_CheckField, 6, 4, 0, 166, 4, 1, // Skip to: 86948 /* 20222 */ MCD_OPC_Decode, 141, 11, 126, // Opcode: FMUL_ZPmI_S /* 20226 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 20247 /* 20231 */ MCD_OPC_CheckPredicate, 0, 152, 4, 1, // Skip to: 86948 /* 20236 */ MCD_OPC_CheckField, 6, 4, 0, 145, 4, 1, // Skip to: 86948 /* 20243 */ MCD_OPC_Decode, 213, 12, 126, // Opcode: FSUBR_ZPmI_S /* 20247 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 20268 /* 20252 */ MCD_OPC_CheckPredicate, 0, 131, 4, 1, // Skip to: 86948 /* 20257 */ MCD_OPC_CheckField, 6, 4, 0, 124, 4, 1, // Skip to: 86948 /* 20264 */ MCD_OPC_Decode, 214, 9, 126, // Opcode: FMAXNM_ZPmI_S /* 20268 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 20289 /* 20273 */ MCD_OPC_CheckPredicate, 0, 110, 4, 1, // Skip to: 86948 /* 20278 */ MCD_OPC_CheckField, 6, 4, 0, 103, 4, 1, // Skip to: 86948 /* 20285 */ MCD_OPC_Decode, 142, 10, 126, // Opcode: FMINNM_ZPmI_S /* 20289 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 20310 /* 20294 */ MCD_OPC_CheckPredicate, 0, 89, 4, 1, // Skip to: 86948 /* 20299 */ MCD_OPC_CheckField, 6, 4, 0, 82, 4, 1, // Skip to: 86948 /* 20306 */ MCD_OPC_Decode, 240, 9, 126, // Opcode: FMAX_ZPmI_S /* 20310 */ MCD_OPC_FilterValue, 7, 73, 4, 1, // Skip to: 86948 /* 20315 */ MCD_OPC_CheckPredicate, 0, 68, 4, 1, // Skip to: 86948 /* 20320 */ MCD_OPC_CheckField, 6, 4, 0, 61, 4, 1, // Skip to: 86948 /* 20327 */ MCD_OPC_Decode, 168, 10, 126, // Opcode: FMIN_ZPmI_S /* 20331 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20345 /* 20336 */ MCD_OPC_CheckPredicate, 0, 47, 4, 1, // Skip to: 86948 /* 20341 */ MCD_OPC_Decode, 192, 9, 6, // Opcode: FMAD_ZPmZZ_S /* 20345 */ MCD_OPC_FilterValue, 2, 142, 1, 0, // Skip to: 20748 /* 20350 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... /* 20353 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 20473 /* 20358 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 20361 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20375 /* 20366 */ MCD_OPC_CheckPredicate, 0, 17, 4, 1, // Skip to: 86948 /* 20371 */ MCD_OPC_Decode, 192, 6, 0, // Opcode: FADD_ZPmZ_D /* 20375 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20389 /* 20380 */ MCD_OPC_CheckPredicate, 0, 3, 4, 1, // Skip to: 86948 /* 20385 */ MCD_OPC_Decode, 221, 12, 0, // Opcode: FSUB_ZPmZ_D /* 20389 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20403 /* 20394 */ MCD_OPC_CheckPredicate, 0, 245, 3, 1, // Skip to: 86948 /* 20399 */ MCD_OPC_Decode, 142, 11, 0, // Opcode: FMUL_ZPmZ_D /* 20403 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20417 /* 20408 */ MCD_OPC_CheckPredicate, 0, 231, 3, 1, // Skip to: 86948 /* 20413 */ MCD_OPC_Decode, 214, 12, 0, // Opcode: FSUBR_ZPmZ_D /* 20417 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20431 /* 20422 */ MCD_OPC_CheckPredicate, 0, 217, 3, 1, // Skip to: 86948 /* 20427 */ MCD_OPC_Decode, 215, 9, 0, // Opcode: FMAXNM_ZPmZ_D /* 20431 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 20445 /* 20436 */ MCD_OPC_CheckPredicate, 0, 203, 3, 1, // Skip to: 86948 /* 20441 */ MCD_OPC_Decode, 143, 10, 0, // Opcode: FMINNM_ZPmZ_D /* 20445 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20459 /* 20450 */ MCD_OPC_CheckPredicate, 0, 189, 3, 1, // Skip to: 86948 /* 20455 */ MCD_OPC_Decode, 241, 9, 0, // Opcode: FMAX_ZPmZ_D /* 20459 */ MCD_OPC_FilterValue, 7, 180, 3, 1, // Skip to: 86948 /* 20464 */ MCD_OPC_CheckPredicate, 0, 175, 3, 1, // Skip to: 86948 /* 20469 */ MCD_OPC_Decode, 169, 10, 0, // Opcode: FMIN_ZPmZ_D /* 20473 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 20551 /* 20478 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 20481 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20495 /* 20486 */ MCD_OPC_CheckPredicate, 0, 153, 3, 1, // Skip to: 86948 /* 20491 */ MCD_OPC_Decode, 131, 6, 0, // Opcode: FABD_ZPmZ_D /* 20495 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20509 /* 20500 */ MCD_OPC_CheckPredicate, 0, 139, 3, 1, // Skip to: 86948 /* 20505 */ MCD_OPC_Decode, 195, 12, 0, // Opcode: FSCALE_ZPmZ_D /* 20509 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20523 /* 20514 */ MCD_OPC_CheckPredicate, 0, 125, 3, 1, // Skip to: 86948 /* 20519 */ MCD_OPC_Decode, 251, 10, 0, // Opcode: FMULX_ZPmZ_D /* 20523 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20537 /* 20528 */ MCD_OPC_CheckPredicate, 0, 111, 3, 1, // Skip to: 86948 /* 20533 */ MCD_OPC_Decode, 168, 9, 0, // Opcode: FDIVR_ZPmZ_D /* 20537 */ MCD_OPC_FilterValue, 5, 102, 3, 1, // Skip to: 86948 /* 20542 */ MCD_OPC_CheckPredicate, 0, 97, 3, 1, // Skip to: 86948 /* 20547 */ MCD_OPC_Decode, 172, 9, 0, // Opcode: FDIV_ZPmZ_D /* 20551 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20572 /* 20556 */ MCD_OPC_CheckPredicate, 0, 83, 3, 1, // Skip to: 86948 /* 20561 */ MCD_OPC_CheckField, 10, 3, 0, 76, 3, 1, // Skip to: 86948 /* 20568 */ MCD_OPC_Decode, 232, 12, 125, // Opcode: FTMAD_ZZI_D /* 20572 */ MCD_OPC_FilterValue, 3, 67, 3, 1, // Skip to: 86948 /* 20577 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... /* 20580 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 20601 /* 20585 */ MCD_OPC_CheckPredicate, 0, 54, 3, 1, // Skip to: 86948 /* 20590 */ MCD_OPC_CheckField, 6, 4, 0, 47, 3, 1, // Skip to: 86948 /* 20597 */ MCD_OPC_Decode, 189, 6, 126, // Opcode: FADD_ZPmI_D /* 20601 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 20622 /* 20606 */ MCD_OPC_CheckPredicate, 0, 33, 3, 1, // Skip to: 86948 /* 20611 */ MCD_OPC_CheckField, 6, 4, 0, 26, 3, 1, // Skip to: 86948 /* 20618 */ MCD_OPC_Decode, 218, 12, 126, // Opcode: FSUB_ZPmI_D /* 20622 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20643 /* 20627 */ MCD_OPC_CheckPredicate, 0, 12, 3, 1, // Skip to: 86948 /* 20632 */ MCD_OPC_CheckField, 6, 4, 0, 5, 3, 1, // Skip to: 86948 /* 20639 */ MCD_OPC_Decode, 139, 11, 126, // Opcode: FMUL_ZPmI_D /* 20643 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 20664 /* 20648 */ MCD_OPC_CheckPredicate, 0, 247, 2, 1, // Skip to: 86948 /* 20653 */ MCD_OPC_CheckField, 6, 4, 0, 240, 2, 1, // Skip to: 86948 /* 20660 */ MCD_OPC_Decode, 211, 12, 126, // Opcode: FSUBR_ZPmI_D /* 20664 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 20685 /* 20669 */ MCD_OPC_CheckPredicate, 0, 226, 2, 1, // Skip to: 86948 /* 20674 */ MCD_OPC_CheckField, 6, 4, 0, 219, 2, 1, // Skip to: 86948 /* 20681 */ MCD_OPC_Decode, 212, 9, 126, // Opcode: FMAXNM_ZPmI_D /* 20685 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 20706 /* 20690 */ MCD_OPC_CheckPredicate, 0, 205, 2, 1, // Skip to: 86948 /* 20695 */ MCD_OPC_CheckField, 6, 4, 0, 198, 2, 1, // Skip to: 86948 /* 20702 */ MCD_OPC_Decode, 140, 10, 126, // Opcode: FMINNM_ZPmI_D /* 20706 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 20727 /* 20711 */ MCD_OPC_CheckPredicate, 0, 184, 2, 1, // Skip to: 86948 /* 20716 */ MCD_OPC_CheckField, 6, 4, 0, 177, 2, 1, // Skip to: 86948 /* 20723 */ MCD_OPC_Decode, 238, 9, 126, // Opcode: FMAX_ZPmI_D /* 20727 */ MCD_OPC_FilterValue, 7, 168, 2, 1, // Skip to: 86948 /* 20732 */ MCD_OPC_CheckPredicate, 0, 163, 2, 1, // Skip to: 86948 /* 20737 */ MCD_OPC_CheckField, 6, 4, 0, 156, 2, 1, // Skip to: 86948 /* 20744 */ MCD_OPC_Decode, 166, 10, 126, // Opcode: FMIN_ZPmI_D /* 20748 */ MCD_OPC_FilterValue, 3, 147, 2, 1, // Skip to: 86948 /* 20753 */ MCD_OPC_CheckPredicate, 0, 142, 2, 1, // Skip to: 86948 /* 20758 */ MCD_OPC_Decode, 190, 9, 6, // Opcode: FMAD_ZPmZZ_D /* 20762 */ MCD_OPC_FilterValue, 5, 95, 2, 0, // Skip to: 21374 /* 20767 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 20770 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 20988 /* 20775 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 20778 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20792 /* 20783 */ MCD_OPC_CheckPredicate, 0, 112, 2, 1, // Skip to: 86948 /* 20788 */ MCD_OPC_Decode, 134, 12, 5, // Opcode: FRINTN_ZPmZ_S /* 20792 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20806 /* 20797 */ MCD_OPC_CheckPredicate, 0, 98, 2, 1, // Skip to: 86948 /* 20802 */ MCD_OPC_Decode, 145, 12, 5, // Opcode: FRINTP_ZPmZ_S /* 20806 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20820 /* 20811 */ MCD_OPC_CheckPredicate, 0, 84, 2, 1, // Skip to: 86948 /* 20816 */ MCD_OPC_Decode, 251, 11, 5, // Opcode: FRINTM_ZPmZ_S /* 20820 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20834 /* 20825 */ MCD_OPC_CheckPredicate, 0, 70, 2, 1, // Skip to: 86948 /* 20830 */ MCD_OPC_Decode, 167, 12, 5, // Opcode: FRINTZ_ZPmZ_S /* 20834 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20848 /* 20839 */ MCD_OPC_CheckPredicate, 0, 56, 2, 1, // Skip to: 86948 /* 20844 */ MCD_OPC_Decode, 229, 11, 5, // Opcode: FRINTA_ZPmZ_S /* 20848 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20862 /* 20853 */ MCD_OPC_CheckPredicate, 0, 42, 2, 1, // Skip to: 86948 /* 20858 */ MCD_OPC_Decode, 156, 12, 5, // Opcode: FRINTX_ZPmZ_S /* 20862 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 20876 /* 20867 */ MCD_OPC_CheckPredicate, 0, 28, 2, 1, // Skip to: 86948 /* 20872 */ MCD_OPC_Decode, 240, 11, 5, // Opcode: FRINTI_ZPmZ_S /* 20876 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 20890 /* 20881 */ MCD_OPC_CheckPredicate, 0, 14, 2, 1, // Skip to: 86948 /* 20886 */ MCD_OPC_Decode, 165, 9, 5, // Opcode: FCVT_ZPmZ_StoH /* 20890 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 20904 /* 20895 */ MCD_OPC_CheckPredicate, 0, 0, 2, 1, // Skip to: 86948 /* 20900 */ MCD_OPC_Decode, 163, 9, 5, // Opcode: FCVT_ZPmZ_HtoS /* 20904 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 20918 /* 20909 */ MCD_OPC_CheckPredicate, 0, 242, 1, 1, // Skip to: 86948 /* 20914 */ MCD_OPC_Decode, 220, 11, 5, // Opcode: FRECPX_ZPmZ_S /* 20918 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 20932 /* 20923 */ MCD_OPC_CheckPredicate, 0, 228, 1, 1, // Skip to: 86948 /* 20928 */ MCD_OPC_Decode, 203, 12, 5, // Opcode: FSQRT_ZPmZ_S /* 20932 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 20946 /* 20937 */ MCD_OPC_CheckPredicate, 0, 214, 1, 1, // Skip to: 86948 /* 20942 */ MCD_OPC_Decode, 202, 22, 5, // Opcode: SCVTF_ZPmZ_StoS /* 20946 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 20960 /* 20951 */ MCD_OPC_CheckPredicate, 0, 200, 1, 1, // Skip to: 86948 /* 20956 */ MCD_OPC_Decode, 189, 31, 5, // Opcode: UCVTF_ZPmZ_StoS /* 20960 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 20974 /* 20965 */ MCD_OPC_CheckPredicate, 0, 186, 1, 1, // Skip to: 86948 /* 20970 */ MCD_OPC_Decode, 236, 8, 5, // Opcode: FCVTZS_ZPmZ_StoS /* 20974 */ MCD_OPC_FilterValue, 29, 177, 1, 1, // Skip to: 86948 /* 20979 */ MCD_OPC_CheckPredicate, 0, 172, 1, 1, // Skip to: 86948 /* 20984 */ MCD_OPC_Decode, 143, 9, 5, // Opcode: FCVTZU_ZPmZ_StoS /* 20988 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21002 /* 20993 */ MCD_OPC_CheckPredicate, 0, 158, 1, 1, // Skip to: 86948 /* 20998 */ MCD_OPC_Decode, 241, 10, 6, // Opcode: FMSB_ZPmZZ_S /* 21002 */ MCD_OPC_FilterValue, 2, 97, 1, 0, // Skip to: 21360 /* 21007 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 21010 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21024 /* 21015 */ MCD_OPC_CheckPredicate, 0, 136, 1, 1, // Skip to: 86948 /* 21020 */ MCD_OPC_Decode, 132, 12, 5, // Opcode: FRINTN_ZPmZ_D /* 21024 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21038 /* 21029 */ MCD_OPC_CheckPredicate, 0, 122, 1, 1, // Skip to: 86948 /* 21034 */ MCD_OPC_Decode, 143, 12, 5, // Opcode: FRINTP_ZPmZ_D /* 21038 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 21052 /* 21043 */ MCD_OPC_CheckPredicate, 0, 108, 1, 1, // Skip to: 86948 /* 21048 */ MCD_OPC_Decode, 249, 11, 5, // Opcode: FRINTM_ZPmZ_D /* 21052 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 21066 /* 21057 */ MCD_OPC_CheckPredicate, 0, 94, 1, 1, // Skip to: 86948 /* 21062 */ MCD_OPC_Decode, 165, 12, 5, // Opcode: FRINTZ_ZPmZ_D /* 21066 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 21080 /* 21071 */ MCD_OPC_CheckPredicate, 0, 80, 1, 1, // Skip to: 86948 /* 21076 */ MCD_OPC_Decode, 227, 11, 5, // Opcode: FRINTA_ZPmZ_D /* 21080 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 21094 /* 21085 */ MCD_OPC_CheckPredicate, 0, 66, 1, 1, // Skip to: 86948 /* 21090 */ MCD_OPC_Decode, 154, 12, 5, // Opcode: FRINTX_ZPmZ_D /* 21094 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 21108 /* 21099 */ MCD_OPC_CheckPredicate, 0, 52, 1, 1, // Skip to: 86948 /* 21104 */ MCD_OPC_Decode, 238, 11, 5, // Opcode: FRINTI_ZPmZ_D /* 21108 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 21122 /* 21113 */ MCD_OPC_CheckPredicate, 0, 38, 1, 1, // Skip to: 86948 /* 21118 */ MCD_OPC_Decode, 160, 9, 5, // Opcode: FCVT_ZPmZ_DtoH /* 21122 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 21136 /* 21127 */ MCD_OPC_CheckPredicate, 0, 24, 1, 1, // Skip to: 86948 /* 21132 */ MCD_OPC_Decode, 162, 9, 5, // Opcode: FCVT_ZPmZ_HtoD /* 21136 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 21150 /* 21141 */ MCD_OPC_CheckPredicate, 0, 10, 1, 1, // Skip to: 86948 /* 21146 */ MCD_OPC_Decode, 161, 9, 5, // Opcode: FCVT_ZPmZ_DtoS /* 21150 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 21164 /* 21155 */ MCD_OPC_CheckPredicate, 0, 252, 0, 1, // Skip to: 86948 /* 21160 */ MCD_OPC_Decode, 164, 9, 5, // Opcode: FCVT_ZPmZ_StoD /* 21164 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 21178 /* 21169 */ MCD_OPC_CheckPredicate, 0, 238, 0, 1, // Skip to: 86948 /* 21174 */ MCD_OPC_Decode, 218, 11, 5, // Opcode: FRECPX_ZPmZ_D /* 21178 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 21192 /* 21183 */ MCD_OPC_CheckPredicate, 0, 224, 0, 1, // Skip to: 86948 /* 21188 */ MCD_OPC_Decode, 201, 12, 5, // Opcode: FSQRT_ZPmZ_D /* 21192 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 21206 /* 21197 */ MCD_OPC_CheckPredicate, 0, 210, 0, 1, // Skip to: 86948 /* 21202 */ MCD_OPC_Decode, 200, 22, 5, // Opcode: SCVTF_ZPmZ_StoD /* 21206 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 21220 /* 21211 */ MCD_OPC_CheckPredicate, 0, 196, 0, 1, // Skip to: 86948 /* 21216 */ MCD_OPC_Decode, 187, 31, 5, // Opcode: UCVTF_ZPmZ_StoD /* 21220 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 21234 /* 21225 */ MCD_OPC_CheckPredicate, 0, 182, 0, 1, // Skip to: 86948 /* 21230 */ MCD_OPC_Decode, 198, 22, 5, // Opcode: SCVTF_ZPmZ_DtoS /* 21234 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 21248 /* 21239 */ MCD_OPC_CheckPredicate, 0, 168, 0, 1, // Skip to: 86948 /* 21244 */ MCD_OPC_Decode, 185, 31, 5, // Opcode: UCVTF_ZPmZ_DtoS /* 21248 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 21262 /* 21253 */ MCD_OPC_CheckPredicate, 0, 154, 0, 1, // Skip to: 86948 /* 21258 */ MCD_OPC_Decode, 196, 22, 5, // Opcode: SCVTF_ZPmZ_DtoD /* 21262 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 21276 /* 21267 */ MCD_OPC_CheckPredicate, 0, 140, 0, 1, // Skip to: 86948 /* 21272 */ MCD_OPC_Decode, 183, 31, 5, // Opcode: UCVTF_ZPmZ_DtoD /* 21276 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 21290 /* 21281 */ MCD_OPC_CheckPredicate, 0, 126, 0, 1, // Skip to: 86948 /* 21286 */ MCD_OPC_Decode, 231, 8, 5, // Opcode: FCVTZS_ZPmZ_DtoS /* 21290 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 21304 /* 21295 */ MCD_OPC_CheckPredicate, 0, 112, 0, 1, // Skip to: 86948 /* 21300 */ MCD_OPC_Decode, 138, 9, 5, // Opcode: FCVTZU_ZPmZ_DtoS /* 21304 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 21318 /* 21309 */ MCD_OPC_CheckPredicate, 0, 98, 0, 1, // Skip to: 86948 /* 21314 */ MCD_OPC_Decode, 235, 8, 5, // Opcode: FCVTZS_ZPmZ_StoD /* 21318 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 21332 /* 21323 */ MCD_OPC_CheckPredicate, 0, 84, 0, 1, // Skip to: 86948 /* 21328 */ MCD_OPC_Decode, 142, 9, 5, // Opcode: FCVTZU_ZPmZ_StoD /* 21332 */ MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 21346 /* 21337 */ MCD_OPC_CheckPredicate, 0, 70, 0, 1, // Skip to: 86948 /* 21342 */ MCD_OPC_Decode, 230, 8, 5, // Opcode: FCVTZS_ZPmZ_DtoD /* 21346 */ MCD_OPC_FilterValue, 31, 61, 0, 1, // Skip to: 86948 /* 21351 */ MCD_OPC_CheckPredicate, 0, 56, 0, 1, // Skip to: 86948 /* 21356 */ MCD_OPC_Decode, 137, 9, 5, // Opcode: FCVTZU_ZPmZ_DtoD /* 21360 */ MCD_OPC_FilterValue, 3, 47, 0, 1, // Skip to: 86948 /* 21365 */ MCD_OPC_CheckPredicate, 0, 42, 0, 1, // Skip to: 86948 /* 21370 */ MCD_OPC_Decode, 239, 10, 6, // Opcode: FMSB_ZPmZZ_D /* 21374 */ MCD_OPC_FilterValue, 6, 103, 0, 0, // Skip to: 21482 /* 21379 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 21382 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 21418 /* 21387 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 21390 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21404 /* 21395 */ MCD_OPC_CheckPredicate, 0, 12, 0, 1, // Skip to: 86948 /* 21400 */ MCD_OPC_Decode, 210, 7, 81, // Opcode: FCMUO_PPzZZ_S /* 21404 */ MCD_OPC_FilterValue, 1, 3, 0, 1, // Skip to: 86948 /* 21409 */ MCD_OPC_CheckPredicate, 0, 254, 255, 0, // Skip to: 86948 /* 21414 */ MCD_OPC_Decode, 155, 6, 81, // Opcode: FACGE_PPzZZ_S /* 21418 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21432 /* 21423 */ MCD_OPC_CheckPredicate, 0, 240, 255, 0, // Skip to: 86948 /* 21428 */ MCD_OPC_Decode, 180, 11, 6, // Opcode: FNMAD_ZPmZZ_S /* 21432 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21468 /* 21437 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 21440 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21454 /* 21445 */ MCD_OPC_CheckPredicate, 0, 218, 255, 0, // Skip to: 86948 /* 21450 */ MCD_OPC_Decode, 208, 7, 81, // Opcode: FCMUO_PPzZZ_D /* 21454 */ MCD_OPC_FilterValue, 1, 209, 255, 0, // Skip to: 86948 /* 21459 */ MCD_OPC_CheckPredicate, 0, 204, 255, 0, // Skip to: 86948 /* 21464 */ MCD_OPC_Decode, 153, 6, 81, // Opcode: FACGE_PPzZZ_D /* 21468 */ MCD_OPC_FilterValue, 3, 195, 255, 0, // Skip to: 86948 /* 21473 */ MCD_OPC_CheckPredicate, 0, 190, 255, 0, // Skip to: 86948 /* 21478 */ MCD_OPC_Decode, 178, 11, 6, // Opcode: FNMAD_ZPmZZ_D /* 21482 */ MCD_OPC_FilterValue, 7, 181, 255, 0, // Skip to: 86948 /* 21487 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 21490 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 21511 /* 21495 */ MCD_OPC_CheckPredicate, 0, 168, 255, 0, // Skip to: 86948 /* 21500 */ MCD_OPC_CheckField, 4, 1, 1, 161, 255, 0, // Skip to: 86948 /* 21507 */ MCD_OPC_Decode, 166, 6, 81, // Opcode: FACGT_PPzZZ_S /* 21511 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21525 /* 21516 */ MCD_OPC_CheckPredicate, 0, 147, 255, 0, // Skip to: 86948 /* 21521 */ MCD_OPC_Decode, 189, 11, 6, // Opcode: FNMSB_ZPmZZ_S /* 21525 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 21546 /* 21530 */ MCD_OPC_CheckPredicate, 0, 133, 255, 0, // Skip to: 86948 /* 21535 */ MCD_OPC_CheckField, 4, 1, 1, 126, 255, 0, // Skip to: 86948 /* 21542 */ MCD_OPC_Decode, 164, 6, 81, // Opcode: FACGT_PPzZZ_D /* 21546 */ MCD_OPC_FilterValue, 3, 117, 255, 0, // Skip to: 86948 /* 21551 */ MCD_OPC_CheckPredicate, 0, 112, 255, 0, // Skip to: 86948 /* 21556 */ MCD_OPC_Decode, 187, 11, 6, // Opcode: FNMSB_ZPmZZ_D /* 21560 */ MCD_OPC_FilterValue, 4, 96, 6, 0, // Skip to: 23197 /* 21565 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 21568 */ MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 21780 /* 21573 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 21576 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 21620 /* 21581 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21584 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21598 /* 21589 */ MCD_OPC_CheckPredicate, 0, 74, 255, 0, // Skip to: 86948 /* 21594 */ MCD_OPC_Decode, 145, 13, 127, // Opcode: GLD1SB_S_UXTW_REAL /* 21598 */ MCD_OPC_FilterValue, 1, 65, 255, 0, // Skip to: 86948 /* 21603 */ MCD_OPC_CheckPredicate, 0, 60, 255, 0, // Skip to: 86948 /* 21608 */ MCD_OPC_CheckField, 4, 1, 0, 53, 255, 0, // Skip to: 86948 /* 21615 */ MCD_OPC_Decode, 133, 21, 128, 1, // Opcode: PRFB_S_UXTW_SCALED /* 21620 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 21664 /* 21625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21628 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21642 /* 21633 */ MCD_OPC_CheckPredicate, 0, 30, 255, 0, // Skip to: 86948 /* 21638 */ MCD_OPC_Decode, 144, 13, 127, // Opcode: GLD1SB_S_SXTW_REAL /* 21642 */ MCD_OPC_FilterValue, 1, 21, 255, 0, // Skip to: 86948 /* 21647 */ MCD_OPC_CheckPredicate, 0, 16, 255, 0, // Skip to: 86948 /* 21652 */ MCD_OPC_CheckField, 4, 1, 0, 9, 255, 0, // Skip to: 86948 /* 21659 */ MCD_OPC_Decode, 132, 21, 128, 1, // Opcode: PRFB_S_SXTW_SCALED /* 21664 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21700 /* 21669 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21672 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21686 /* 21677 */ MCD_OPC_CheckPredicate, 0, 242, 254, 0, // Skip to: 86948 /* 21682 */ MCD_OPC_Decode, 156, 13, 127, // Opcode: GLD1SH_S_UXTW_REAL /* 21686 */ MCD_OPC_FilterValue, 1, 233, 254, 0, // Skip to: 86948 /* 21691 */ MCD_OPC_CheckPredicate, 0, 228, 254, 0, // Skip to: 86948 /* 21696 */ MCD_OPC_Decode, 157, 13, 127, // Opcode: GLD1SH_S_UXTW_SCALED_REAL /* 21700 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 21736 /* 21705 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21708 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21722 /* 21713 */ MCD_OPC_CheckPredicate, 0, 206, 254, 0, // Skip to: 86948 /* 21718 */ MCD_OPC_Decode, 154, 13, 127, // Opcode: GLD1SH_S_SXTW_REAL /* 21722 */ MCD_OPC_FilterValue, 1, 197, 254, 0, // Skip to: 86948 /* 21727 */ MCD_OPC_CheckPredicate, 0, 192, 254, 0, // Skip to: 86948 /* 21732 */ MCD_OPC_Decode, 155, 13, 127, // Opcode: GLD1SH_S_SXTW_SCALED_REAL /* 21736 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 21758 /* 21741 */ MCD_OPC_CheckPredicate, 0, 178, 254, 0, // Skip to: 86948 /* 21746 */ MCD_OPC_CheckField, 4, 1, 0, 171, 254, 0, // Skip to: 86948 /* 21753 */ MCD_OPC_Decode, 167, 18, 129, 1, // Opcode: LDR_PXI /* 21758 */ MCD_OPC_FilterValue, 7, 161, 254, 0, // Skip to: 86948 /* 21763 */ MCD_OPC_CheckPredicate, 0, 156, 254, 0, // Skip to: 86948 /* 21768 */ MCD_OPC_CheckField, 4, 1, 0, 149, 254, 0, // Skip to: 86948 /* 21775 */ MCD_OPC_Decode, 129, 21, 130, 1, // Opcode: PRFB_PRI /* 21780 */ MCD_OPC_FilterValue, 1, 185, 0, 0, // Skip to: 21970 /* 21785 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 21788 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 21832 /* 21793 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21796 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21810 /* 21801 */ MCD_OPC_CheckPredicate, 0, 118, 254, 0, // Skip to: 86948 /* 21806 */ MCD_OPC_Decode, 209, 13, 127, // Opcode: GLDFF1SB_S_UXTW_REAL /* 21810 */ MCD_OPC_FilterValue, 1, 109, 254, 0, // Skip to: 86948 /* 21815 */ MCD_OPC_CheckPredicate, 0, 104, 254, 0, // Skip to: 86948 /* 21820 */ MCD_OPC_CheckField, 4, 1, 0, 97, 254, 0, // Skip to: 86948 /* 21827 */ MCD_OPC_Decode, 151, 21, 128, 1, // Opcode: PRFH_S_UXTW_SCALED /* 21832 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 21876 /* 21837 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21840 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21854 /* 21845 */ MCD_OPC_CheckPredicate, 0, 74, 254, 0, // Skip to: 86948 /* 21850 */ MCD_OPC_Decode, 208, 13, 127, // Opcode: GLDFF1SB_S_SXTW_REAL /* 21854 */ MCD_OPC_FilterValue, 1, 65, 254, 0, // Skip to: 86948 /* 21859 */ MCD_OPC_CheckPredicate, 0, 60, 254, 0, // Skip to: 86948 /* 21864 */ MCD_OPC_CheckField, 4, 1, 0, 53, 254, 0, // Skip to: 86948 /* 21871 */ MCD_OPC_Decode, 150, 21, 128, 1, // Opcode: PRFH_S_SXTW_SCALED /* 21876 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21912 /* 21881 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21884 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21898 /* 21889 */ MCD_OPC_CheckPredicate, 0, 30, 254, 0, // Skip to: 86948 /* 21894 */ MCD_OPC_Decode, 220, 13, 127, // Opcode: GLDFF1SH_S_UXTW_REAL /* 21898 */ MCD_OPC_FilterValue, 1, 21, 254, 0, // Skip to: 86948 /* 21903 */ MCD_OPC_CheckPredicate, 0, 16, 254, 0, // Skip to: 86948 /* 21908 */ MCD_OPC_Decode, 221, 13, 127, // Opcode: GLDFF1SH_S_UXTW_SCALED_REAL /* 21912 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 21948 /* 21917 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21920 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21934 /* 21925 */ MCD_OPC_CheckPredicate, 0, 250, 253, 0, // Skip to: 86948 /* 21930 */ MCD_OPC_Decode, 218, 13, 127, // Opcode: GLDFF1SH_S_SXTW_REAL /* 21934 */ MCD_OPC_FilterValue, 1, 241, 253, 0, // Skip to: 86948 /* 21939 */ MCD_OPC_CheckPredicate, 0, 236, 253, 0, // Skip to: 86948 /* 21944 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: GLDFF1SH_S_SXTW_SCALED_REAL /* 21948 */ MCD_OPC_FilterValue, 7, 227, 253, 0, // Skip to: 86948 /* 21953 */ MCD_OPC_CheckPredicate, 0, 222, 253, 0, // Skip to: 86948 /* 21958 */ MCD_OPC_CheckField, 4, 1, 0, 215, 253, 0, // Skip to: 86948 /* 21965 */ MCD_OPC_Decode, 147, 21, 130, 1, // Opcode: PRFH_PRI /* 21970 */ MCD_OPC_FilterValue, 2, 16, 1, 0, // Skip to: 22247 /* 21975 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 21978 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 22022 /* 21983 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 21986 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22000 /* 21991 */ MCD_OPC_CheckPredicate, 0, 184, 253, 0, // Skip to: 86948 /* 21996 */ MCD_OPC_Decode, 247, 12, 127, // Opcode: GLD1B_S_UXTW_REAL /* 22000 */ MCD_OPC_FilterValue, 1, 175, 253, 0, // Skip to: 86948 /* 22005 */ MCD_OPC_CheckPredicate, 0, 170, 253, 0, // Skip to: 86948 /* 22010 */ MCD_OPC_CheckField, 4, 1, 0, 163, 253, 0, // Skip to: 86948 /* 22017 */ MCD_OPC_Decode, 165, 21, 128, 1, // Opcode: PRFW_S_UXTW_SCALED /* 22022 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 22066 /* 22027 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22030 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22044 /* 22035 */ MCD_OPC_CheckPredicate, 0, 140, 253, 0, // Skip to: 86948 /* 22040 */ MCD_OPC_Decode, 246, 12, 127, // Opcode: GLD1B_S_SXTW_REAL /* 22044 */ MCD_OPC_FilterValue, 1, 131, 253, 0, // Skip to: 86948 /* 22049 */ MCD_OPC_CheckPredicate, 0, 126, 253, 0, // Skip to: 86948 /* 22054 */ MCD_OPC_CheckField, 4, 1, 0, 119, 253, 0, // Skip to: 86948 /* 22061 */ MCD_OPC_Decode, 164, 21, 128, 1, // Opcode: PRFW_S_SXTW_SCALED /* 22066 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 22102 /* 22071 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22088 /* 22079 */ MCD_OPC_CheckPredicate, 0, 96, 253, 0, // Skip to: 86948 /* 22084 */ MCD_OPC_Decode, 137, 13, 127, // Opcode: GLD1H_S_UXTW_REAL /* 22088 */ MCD_OPC_FilterValue, 1, 87, 253, 0, // Skip to: 86948 /* 22093 */ MCD_OPC_CheckPredicate, 0, 82, 253, 0, // Skip to: 86948 /* 22098 */ MCD_OPC_Decode, 138, 13, 127, // Opcode: GLD1H_S_UXTW_SCALED_REAL /* 22102 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 22138 /* 22107 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22110 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22124 /* 22115 */ MCD_OPC_CheckPredicate, 0, 60, 253, 0, // Skip to: 86948 /* 22120 */ MCD_OPC_Decode, 135, 13, 127, // Opcode: GLD1H_S_SXTW_REAL /* 22124 */ MCD_OPC_FilterValue, 1, 51, 253, 0, // Skip to: 86948 /* 22129 */ MCD_OPC_CheckPredicate, 0, 46, 253, 0, // Skip to: 86948 /* 22134 */ MCD_OPC_Decode, 136, 13, 127, // Opcode: GLD1H_S_SXTW_SCALED_REAL /* 22138 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 22174 /* 22143 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22146 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22160 /* 22151 */ MCD_OPC_CheckPredicate, 0, 24, 253, 0, // Skip to: 86948 /* 22156 */ MCD_OPC_Decode, 175, 13, 127, // Opcode: GLD1W_UXTW_REAL /* 22160 */ MCD_OPC_FilterValue, 1, 15, 253, 0, // Skip to: 86948 /* 22165 */ MCD_OPC_CheckPredicate, 0, 10, 253, 0, // Skip to: 86948 /* 22170 */ MCD_OPC_Decode, 176, 13, 127, // Opcode: GLD1W_UXTW_SCALED_REAL /* 22174 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 22210 /* 22179 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22182 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22196 /* 22187 */ MCD_OPC_CheckPredicate, 0, 244, 252, 0, // Skip to: 86948 /* 22192 */ MCD_OPC_Decode, 173, 13, 127, // Opcode: GLD1W_SXTW_REAL /* 22196 */ MCD_OPC_FilterValue, 1, 235, 252, 0, // Skip to: 86948 /* 22201 */ MCD_OPC_CheckPredicate, 0, 230, 252, 0, // Skip to: 86948 /* 22206 */ MCD_OPC_Decode, 174, 13, 127, // Opcode: GLD1W_SXTW_SCALED_REAL /* 22210 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 22225 /* 22215 */ MCD_OPC_CheckPredicate, 0, 216, 252, 0, // Skip to: 86948 /* 22220 */ MCD_OPC_Decode, 168, 18, 131, 1, // Opcode: LDR_ZXI /* 22225 */ MCD_OPC_FilterValue, 7, 206, 252, 0, // Skip to: 86948 /* 22230 */ MCD_OPC_CheckPredicate, 0, 201, 252, 0, // Skip to: 86948 /* 22235 */ MCD_OPC_CheckField, 4, 1, 0, 194, 252, 0, // Skip to: 86948 /* 22242 */ MCD_OPC_Decode, 162, 21, 130, 1, // Opcode: PRFW_PRI /* 22247 */ MCD_OPC_FilterValue, 3, 1, 1, 0, // Skip to: 22509 /* 22252 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 22255 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 22299 /* 22260 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22263 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22277 /* 22268 */ MCD_OPC_CheckPredicate, 0, 163, 252, 0, // Skip to: 86948 /* 22273 */ MCD_OPC_Decode, 183, 13, 127, // Opcode: GLDFF1B_S_UXTW_REAL /* 22277 */ MCD_OPC_FilterValue, 1, 154, 252, 0, // Skip to: 86948 /* 22282 */ MCD_OPC_CheckPredicate, 0, 149, 252, 0, // Skip to: 86948 /* 22287 */ MCD_OPC_CheckField, 4, 1, 0, 142, 252, 0, // Skip to: 86948 /* 22294 */ MCD_OPC_Decode, 142, 21, 128, 1, // Opcode: PRFD_S_UXTW_SCALED /* 22299 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 22343 /* 22304 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22307 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22321 /* 22312 */ MCD_OPC_CheckPredicate, 0, 119, 252, 0, // Skip to: 86948 /* 22317 */ MCD_OPC_Decode, 182, 13, 127, // Opcode: GLDFF1B_S_SXTW_REAL /* 22321 */ MCD_OPC_FilterValue, 1, 110, 252, 0, // Skip to: 86948 /* 22326 */ MCD_OPC_CheckPredicate, 0, 105, 252, 0, // Skip to: 86948 /* 22331 */ MCD_OPC_CheckField, 4, 1, 0, 98, 252, 0, // Skip to: 86948 /* 22338 */ MCD_OPC_Decode, 141, 21, 128, 1, // Opcode: PRFD_S_SXTW_SCALED /* 22343 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 22379 /* 22348 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22351 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22365 /* 22356 */ MCD_OPC_CheckPredicate, 0, 75, 252, 0, // Skip to: 86948 /* 22361 */ MCD_OPC_Decode, 201, 13, 127, // Opcode: GLDFF1H_S_UXTW_REAL /* 22365 */ MCD_OPC_FilterValue, 1, 66, 252, 0, // Skip to: 86948 /* 22370 */ MCD_OPC_CheckPredicate, 0, 61, 252, 0, // Skip to: 86948 /* 22375 */ MCD_OPC_Decode, 202, 13, 127, // Opcode: GLDFF1H_S_UXTW_SCALED_REAL /* 22379 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 22415 /* 22384 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22387 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22401 /* 22392 */ MCD_OPC_CheckPredicate, 0, 39, 252, 0, // Skip to: 86948 /* 22397 */ MCD_OPC_Decode, 199, 13, 127, // Opcode: GLDFF1H_S_SXTW_REAL /* 22401 */ MCD_OPC_FilterValue, 1, 30, 252, 0, // Skip to: 86948 /* 22406 */ MCD_OPC_CheckPredicate, 0, 25, 252, 0, // Skip to: 86948 /* 22411 */ MCD_OPC_Decode, 200, 13, 127, // Opcode: GLDFF1H_S_SXTW_SCALED_REAL /* 22415 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 22451 /* 22420 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22423 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22437 /* 22428 */ MCD_OPC_CheckPredicate, 0, 3, 252, 0, // Skip to: 86948 /* 22433 */ MCD_OPC_Decode, 239, 13, 127, // Opcode: GLDFF1W_UXTW_REAL /* 22437 */ MCD_OPC_FilterValue, 1, 250, 251, 0, // Skip to: 86948 /* 22442 */ MCD_OPC_CheckPredicate, 0, 245, 251, 0, // Skip to: 86948 /* 22447 */ MCD_OPC_Decode, 240, 13, 127, // Opcode: GLDFF1W_UXTW_SCALED_REAL /* 22451 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 22487 /* 22456 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22459 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22473 /* 22464 */ MCD_OPC_CheckPredicate, 0, 223, 251, 0, // Skip to: 86948 /* 22469 */ MCD_OPC_Decode, 237, 13, 127, // Opcode: GLDFF1W_SXTW_REAL /* 22473 */ MCD_OPC_FilterValue, 1, 214, 251, 0, // Skip to: 86948 /* 22478 */ MCD_OPC_CheckPredicate, 0, 209, 251, 0, // Skip to: 86948 /* 22483 */ MCD_OPC_Decode, 238, 13, 127, // Opcode: GLDFF1W_SXTW_SCALED_REAL /* 22487 */ MCD_OPC_FilterValue, 7, 200, 251, 0, // Skip to: 86948 /* 22492 */ MCD_OPC_CheckPredicate, 0, 195, 251, 0, // Skip to: 86948 /* 22497 */ MCD_OPC_CheckField, 4, 1, 0, 188, 251, 0, // Skip to: 86948 /* 22504 */ MCD_OPC_Decode, 138, 21, 130, 1, // Opcode: PRFD_PRI /* 22509 */ MCD_OPC_FilterValue, 4, 107, 0, 0, // Skip to: 22621 /* 22514 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 22517 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22539 /* 22522 */ MCD_OPC_CheckPredicate, 0, 165, 251, 0, // Skip to: 86948 /* 22527 */ MCD_OPC_CheckField, 21, 1, 1, 158, 251, 0, // Skip to: 86948 /* 22534 */ MCD_OPC_Decode, 143, 13, 132, 1, // Opcode: GLD1SB_S_IMM_REAL /* 22539 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22554 /* 22544 */ MCD_OPC_CheckPredicate, 0, 143, 251, 0, // Skip to: 86948 /* 22549 */ MCD_OPC_Decode, 229, 14, 133, 1, // Opcode: LD1RB_IMM /* 22554 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 22576 /* 22559 */ MCD_OPC_CheckPredicate, 0, 128, 251, 0, // Skip to: 86948 /* 22564 */ MCD_OPC_CheckField, 21, 1, 1, 121, 251, 0, // Skip to: 86948 /* 22571 */ MCD_OPC_Decode, 153, 13, 132, 1, // Opcode: GLD1SH_S_IMM_REAL /* 22576 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22591 /* 22581 */ MCD_OPC_CheckPredicate, 0, 106, 251, 0, // Skip to: 86948 /* 22586 */ MCD_OPC_Decode, 248, 14, 133, 1, // Opcode: LD1RSW_IMM /* 22591 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22606 /* 22596 */ MCD_OPC_CheckPredicate, 0, 91, 251, 0, // Skip to: 86948 /* 22601 */ MCD_OPC_Decode, 246, 14, 133, 1, // Opcode: LD1RSH_D_IMM /* 22606 */ MCD_OPC_FilterValue, 7, 81, 251, 0, // Skip to: 86948 /* 22611 */ MCD_OPC_CheckPredicate, 0, 76, 251, 0, // Skip to: 86948 /* 22616 */ MCD_OPC_Decode, 243, 14, 133, 1, // Opcode: LD1RSB_D_IMM /* 22621 */ MCD_OPC_FilterValue, 5, 107, 0, 0, // Skip to: 22733 /* 22626 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 22629 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22651 /* 22634 */ MCD_OPC_CheckPredicate, 0, 53, 251, 0, // Skip to: 86948 /* 22639 */ MCD_OPC_CheckField, 21, 1, 1, 46, 251, 0, // Skip to: 86948 /* 22646 */ MCD_OPC_Decode, 207, 13, 132, 1, // Opcode: GLDFF1SB_S_IMM_REAL /* 22651 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22666 /* 22656 */ MCD_OPC_CheckPredicate, 0, 31, 251, 0, // Skip to: 86948 /* 22661 */ MCD_OPC_Decode, 228, 14, 133, 1, // Opcode: LD1RB_H_IMM /* 22666 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 22688 /* 22671 */ MCD_OPC_CheckPredicate, 0, 16, 251, 0, // Skip to: 86948 /* 22676 */ MCD_OPC_CheckField, 21, 1, 1, 9, 251, 0, // Skip to: 86948 /* 22683 */ MCD_OPC_Decode, 217, 13, 132, 1, // Opcode: GLDFF1SH_S_IMM_REAL /* 22688 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22703 /* 22693 */ MCD_OPC_CheckPredicate, 0, 250, 250, 0, // Skip to: 86948 /* 22698 */ MCD_OPC_Decode, 233, 14, 133, 1, // Opcode: LD1RH_IMM /* 22703 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22718 /* 22708 */ MCD_OPC_CheckPredicate, 0, 235, 250, 0, // Skip to: 86948 /* 22713 */ MCD_OPC_Decode, 247, 14, 133, 1, // Opcode: LD1RSH_S_IMM /* 22718 */ MCD_OPC_FilterValue, 7, 225, 250, 0, // Skip to: 86948 /* 22723 */ MCD_OPC_CheckPredicate, 0, 220, 250, 0, // Skip to: 86948 /* 22728 */ MCD_OPC_Decode, 245, 14, 133, 1, // Opcode: LD1RSB_S_IMM /* 22733 */ MCD_OPC_FilterValue, 6, 227, 0, 0, // Skip to: 22965 /* 22738 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 22741 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 22786 /* 22746 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22749 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22771 /* 22754 */ MCD_OPC_CheckPredicate, 0, 189, 250, 0, // Skip to: 86948 /* 22759 */ MCD_OPC_CheckField, 4, 1, 0, 182, 250, 0, // Skip to: 86948 /* 22766 */ MCD_OPC_Decode, 130, 21, 134, 1, // Opcode: PRFB_PRR /* 22771 */ MCD_OPC_FilterValue, 1, 172, 250, 0, // Skip to: 86948 /* 22776 */ MCD_OPC_CheckPredicate, 0, 167, 250, 0, // Skip to: 86948 /* 22781 */ MCD_OPC_Decode, 245, 12, 132, 1, // Opcode: GLD1B_S_IMM_REAL /* 22786 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22801 /* 22791 */ MCD_OPC_CheckPredicate, 0, 152, 250, 0, // Skip to: 86948 /* 22796 */ MCD_OPC_Decode, 230, 14, 133, 1, // Opcode: LD1RB_S_IMM /* 22801 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 22846 /* 22806 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22809 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22831 /* 22814 */ MCD_OPC_CheckPredicate, 0, 129, 250, 0, // Skip to: 86948 /* 22819 */ MCD_OPC_CheckField, 4, 1, 0, 122, 250, 0, // Skip to: 86948 /* 22826 */ MCD_OPC_Decode, 148, 21, 134, 1, // Opcode: PRFH_PRR /* 22831 */ MCD_OPC_FilterValue, 1, 112, 250, 0, // Skip to: 86948 /* 22836 */ MCD_OPC_CheckPredicate, 0, 107, 250, 0, // Skip to: 86948 /* 22841 */ MCD_OPC_Decode, 134, 13, 132, 1, // Opcode: GLD1H_S_IMM_REAL /* 22846 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22861 /* 22851 */ MCD_OPC_CheckPredicate, 0, 92, 250, 0, // Skip to: 86948 /* 22856 */ MCD_OPC_Decode, 234, 14, 133, 1, // Opcode: LD1RH_S_IMM /* 22861 */ MCD_OPC_FilterValue, 4, 40, 0, 0, // Skip to: 22906 /* 22866 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22869 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22891 /* 22874 */ MCD_OPC_CheckPredicate, 0, 69, 250, 0, // Skip to: 86948 /* 22879 */ MCD_OPC_CheckField, 4, 1, 0, 62, 250, 0, // Skip to: 86948 /* 22886 */ MCD_OPC_Decode, 156, 21, 134, 1, // Opcode: PRFS_PRR /* 22891 */ MCD_OPC_FilterValue, 1, 52, 250, 0, // Skip to: 86948 /* 22896 */ MCD_OPC_CheckPredicate, 0, 47, 250, 0, // Skip to: 86948 /* 22901 */ MCD_OPC_Decode, 172, 13, 132, 1, // Opcode: GLD1W_IMM_REAL /* 22906 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22921 /* 22911 */ MCD_OPC_CheckPredicate, 0, 32, 250, 0, // Skip to: 86948 /* 22916 */ MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: LD1RW_IMM /* 22921 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 22950 /* 22926 */ MCD_OPC_CheckPredicate, 0, 17, 250, 0, // Skip to: 86948 /* 22931 */ MCD_OPC_CheckField, 21, 1, 0, 10, 250, 0, // Skip to: 86948 /* 22938 */ MCD_OPC_CheckField, 4, 1, 0, 3, 250, 0, // Skip to: 86948 /* 22945 */ MCD_OPC_Decode, 139, 21, 134, 1, // Opcode: PRFD_PRR /* 22950 */ MCD_OPC_FilterValue, 7, 249, 249, 0, // Skip to: 86948 /* 22955 */ MCD_OPC_CheckPredicate, 0, 244, 249, 0, // Skip to: 86948 /* 22960 */ MCD_OPC_Decode, 244, 14, 133, 1, // Opcode: LD1RSB_H_IMM /* 22965 */ MCD_OPC_FilterValue, 7, 234, 249, 0, // Skip to: 86948 /* 22970 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 22973 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 23018 /* 22978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 22981 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23003 /* 22986 */ MCD_OPC_CheckPredicate, 0, 213, 249, 0, // Skip to: 86948 /* 22991 */ MCD_OPC_CheckField, 4, 1, 0, 206, 249, 0, // Skip to: 86948 /* 22998 */ MCD_OPC_Decode, 131, 21, 135, 1, // Opcode: PRFB_S_PZI /* 23003 */ MCD_OPC_FilterValue, 1, 196, 249, 0, // Skip to: 86948 /* 23008 */ MCD_OPC_CheckPredicate, 0, 191, 249, 0, // Skip to: 86948 /* 23013 */ MCD_OPC_Decode, 181, 13, 132, 1, // Opcode: GLDFF1B_S_IMM_REAL /* 23018 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 23033 /* 23023 */ MCD_OPC_CheckPredicate, 0, 176, 249, 0, // Skip to: 86948 /* 23028 */ MCD_OPC_Decode, 227, 14, 133, 1, // Opcode: LD1RB_D_IMM /* 23033 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 23078 /* 23038 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 23041 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23063 /* 23046 */ MCD_OPC_CheckPredicate, 0, 153, 249, 0, // Skip to: 86948 /* 23051 */ MCD_OPC_CheckField, 4, 1, 0, 146, 249, 0, // Skip to: 86948 /* 23058 */ MCD_OPC_Decode, 149, 21, 135, 1, // Opcode: PRFH_S_PZI /* 23063 */ MCD_OPC_FilterValue, 1, 136, 249, 0, // Skip to: 86948 /* 23068 */ MCD_OPC_CheckPredicate, 0, 131, 249, 0, // Skip to: 86948 /* 23073 */ MCD_OPC_Decode, 198, 13, 132, 1, // Opcode: GLDFF1H_S_IMM_REAL /* 23078 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23093 /* 23083 */ MCD_OPC_CheckPredicate, 0, 116, 249, 0, // Skip to: 86948 /* 23088 */ MCD_OPC_Decode, 232, 14, 133, 1, // Opcode: LD1RH_D_IMM /* 23093 */ MCD_OPC_FilterValue, 4, 40, 0, 0, // Skip to: 23138 /* 23098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 23101 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23123 /* 23106 */ MCD_OPC_CheckPredicate, 0, 93, 249, 0, // Skip to: 86948 /* 23111 */ MCD_OPC_CheckField, 4, 1, 0, 86, 249, 0, // Skip to: 86948 /* 23118 */ MCD_OPC_Decode, 163, 21, 135, 1, // Opcode: PRFW_S_PZI /* 23123 */ MCD_OPC_FilterValue, 1, 76, 249, 0, // Skip to: 86948 /* 23128 */ MCD_OPC_CheckPredicate, 0, 71, 249, 0, // Skip to: 86948 /* 23133 */ MCD_OPC_Decode, 236, 13, 132, 1, // Opcode: GLDFF1W_IMM_REAL /* 23138 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 23153 /* 23143 */ MCD_OPC_CheckPredicate, 0, 56, 249, 0, // Skip to: 86948 /* 23148 */ MCD_OPC_Decode, 249, 14, 133, 1, // Opcode: LD1RW_D_IMM /* 23153 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 23182 /* 23158 */ MCD_OPC_CheckPredicate, 0, 41, 249, 0, // Skip to: 86948 /* 23163 */ MCD_OPC_CheckField, 21, 1, 0, 34, 249, 0, // Skip to: 86948 /* 23170 */ MCD_OPC_CheckField, 4, 1, 0, 27, 249, 0, // Skip to: 86948 /* 23177 */ MCD_OPC_Decode, 140, 21, 135, 1, // Opcode: PRFD_S_PZI /* 23182 */ MCD_OPC_FilterValue, 7, 17, 249, 0, // Skip to: 86948 /* 23187 */ MCD_OPC_CheckPredicate, 0, 12, 249, 0, // Skip to: 86948 /* 23192 */ MCD_OPC_Decode, 231, 14, 133, 1, // Opcode: LD1RD_IMM /* 23197 */ MCD_OPC_FilterValue, 5, 167, 7, 0, // Skip to: 25161 /* 23202 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 23205 */ MCD_OPC_FilterValue, 0, 145, 0, 0, // Skip to: 23355 /* 23210 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23228 /* 23218 */ MCD_OPC_CheckPredicate, 0, 237, 248, 0, // Skip to: 86948 /* 23223 */ MCD_OPC_Decode, 235, 14, 136, 1, // Opcode: LD1RQ_B /* 23228 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 23250 /* 23233 */ MCD_OPC_CheckPredicate, 0, 222, 248, 0, // Skip to: 86948 /* 23238 */ MCD_OPC_CheckField, 20, 1, 0, 215, 248, 0, // Skip to: 86948 /* 23245 */ MCD_OPC_Decode, 236, 14, 137, 1, // Opcode: LD1RQ_B_IMM /* 23250 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23265 /* 23255 */ MCD_OPC_CheckPredicate, 0, 200, 248, 0, // Skip to: 86948 /* 23260 */ MCD_OPC_Decode, 179, 14, 136, 1, // Opcode: LD1B /* 23265 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23280 /* 23270 */ MCD_OPC_CheckPredicate, 0, 185, 248, 0, // Skip to: 86948 /* 23275 */ MCD_OPC_Decode, 150, 17, 138, 1, // Opcode: LDFF1B_REAL /* 23280 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23318 /* 23285 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 23288 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23303 /* 23293 */ MCD_OPC_CheckPredicate, 0, 162, 248, 0, // Skip to: 86948 /* 23298 */ MCD_OPC_Decode, 184, 14, 137, 1, // Opcode: LD1B_IMM_REAL /* 23303 */ MCD_OPC_FilterValue, 1, 152, 248, 0, // Skip to: 86948 /* 23308 */ MCD_OPC_CheckPredicate, 0, 147, 248, 0, // Skip to: 86948 /* 23313 */ MCD_OPC_Decode, 170, 17, 137, 1, // Opcode: LDNF1B_IMM_REAL /* 23318 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23333 /* 23323 */ MCD_OPC_CheckPredicate, 0, 132, 248, 0, // Skip to: 86948 /* 23328 */ MCD_OPC_Decode, 190, 17, 136, 1, // Opcode: LDNT1B_ZRR /* 23333 */ MCD_OPC_FilterValue, 7, 122, 248, 0, // Skip to: 86948 /* 23338 */ MCD_OPC_CheckPredicate, 0, 117, 248, 0, // Skip to: 86948 /* 23343 */ MCD_OPC_CheckField, 20, 1, 0, 110, 248, 0, // Skip to: 86948 /* 23350 */ MCD_OPC_Decode, 189, 17, 137, 1, // Opcode: LDNT1B_ZRI /* 23355 */ MCD_OPC_FilterValue, 1, 108, 0, 0, // Skip to: 23468 /* 23360 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23363 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23378 /* 23368 */ MCD_OPC_CheckPredicate, 0, 87, 248, 0, // Skip to: 86948 /* 23373 */ MCD_OPC_Decode, 182, 14, 136, 1, // Opcode: LD1B_H /* 23378 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23393 /* 23383 */ MCD_OPC_CheckPredicate, 0, 72, 248, 0, // Skip to: 86948 /* 23388 */ MCD_OPC_Decode, 149, 17, 138, 1, // Opcode: LDFF1B_H_REAL /* 23393 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23431 /* 23398 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 23401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23416 /* 23406 */ MCD_OPC_CheckPredicate, 0, 49, 248, 0, // Skip to: 86948 /* 23411 */ MCD_OPC_Decode, 183, 14, 137, 1, // Opcode: LD1B_H_IMM_REAL /* 23416 */ MCD_OPC_FilterValue, 1, 39, 248, 0, // Skip to: 86948 /* 23421 */ MCD_OPC_CheckPredicate, 0, 34, 248, 0, // Skip to: 86948 /* 23426 */ MCD_OPC_Decode, 169, 17, 137, 1, // Opcode: LDNF1B_H_IMM_REAL /* 23431 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23446 /* 23436 */ MCD_OPC_CheckPredicate, 0, 19, 248, 0, // Skip to: 86948 /* 23441 */ MCD_OPC_Decode, 195, 15, 139, 1, // Opcode: LD2B /* 23446 */ MCD_OPC_FilterValue, 7, 9, 248, 0, // Skip to: 86948 /* 23451 */ MCD_OPC_CheckPredicate, 0, 4, 248, 0, // Skip to: 86948 /* 23456 */ MCD_OPC_CheckField, 20, 1, 0, 253, 247, 0, // Skip to: 86948 /* 23463 */ MCD_OPC_Decode, 196, 15, 140, 1, // Opcode: LD2B_IMM /* 23468 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 23581 /* 23473 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23476 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23491 /* 23481 */ MCD_OPC_CheckPredicate, 0, 230, 247, 0, // Skip to: 86948 /* 23486 */ MCD_OPC_Decode, 185, 14, 136, 1, // Opcode: LD1B_S /* 23491 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23506 /* 23496 */ MCD_OPC_CheckPredicate, 0, 215, 247, 0, // Skip to: 86948 /* 23501 */ MCD_OPC_Decode, 151, 17, 138, 1, // Opcode: LDFF1B_S_REAL /* 23506 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23544 /* 23511 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 23514 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23529 /* 23519 */ MCD_OPC_CheckPredicate, 0, 192, 247, 0, // Skip to: 86948 /* 23524 */ MCD_OPC_Decode, 186, 14, 137, 1, // Opcode: LD1B_S_IMM_REAL /* 23529 */ MCD_OPC_FilterValue, 1, 182, 247, 0, // Skip to: 86948 /* 23534 */ MCD_OPC_CheckPredicate, 0, 177, 247, 0, // Skip to: 86948 /* 23539 */ MCD_OPC_Decode, 171, 17, 137, 1, // Opcode: LDNF1B_S_IMM_REAL /* 23544 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23559 /* 23549 */ MCD_OPC_CheckPredicate, 0, 162, 247, 0, // Skip to: 86948 /* 23554 */ MCD_OPC_Decode, 241, 15, 141, 1, // Opcode: LD3B /* 23559 */ MCD_OPC_FilterValue, 7, 152, 247, 0, // Skip to: 86948 /* 23564 */ MCD_OPC_CheckPredicate, 0, 147, 247, 0, // Skip to: 86948 /* 23569 */ MCD_OPC_CheckField, 20, 1, 0, 140, 247, 0, // Skip to: 86948 /* 23576 */ MCD_OPC_Decode, 242, 15, 142, 1, // Opcode: LD3B_IMM /* 23581 */ MCD_OPC_FilterValue, 3, 108, 0, 0, // Skip to: 23694 /* 23586 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23589 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23604 /* 23594 */ MCD_OPC_CheckPredicate, 0, 117, 247, 0, // Skip to: 86948 /* 23599 */ MCD_OPC_Decode, 180, 14, 136, 1, // Opcode: LD1B_D /* 23604 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23619 /* 23609 */ MCD_OPC_CheckPredicate, 0, 102, 247, 0, // Skip to: 86948 /* 23614 */ MCD_OPC_Decode, 148, 17, 138, 1, // Opcode: LDFF1B_D_REAL /* 23619 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23657 /* 23624 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 23627 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23642 /* 23632 */ MCD_OPC_CheckPredicate, 0, 79, 247, 0, // Skip to: 86948 /* 23637 */ MCD_OPC_Decode, 181, 14, 137, 1, // Opcode: LD1B_D_IMM_REAL /* 23642 */ MCD_OPC_FilterValue, 1, 69, 247, 0, // Skip to: 86948 /* 23647 */ MCD_OPC_CheckPredicate, 0, 64, 247, 0, // Skip to: 86948 /* 23652 */ MCD_OPC_Decode, 168, 17, 137, 1, // Opcode: LDNF1B_D_IMM_REAL /* 23657 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23672 /* 23662 */ MCD_OPC_CheckPredicate, 0, 49, 247, 0, // Skip to: 86948 /* 23667 */ MCD_OPC_Decode, 159, 16, 143, 1, // Opcode: LD4B /* 23672 */ MCD_OPC_FilterValue, 7, 39, 247, 0, // Skip to: 86948 /* 23677 */ MCD_OPC_CheckPredicate, 0, 34, 247, 0, // Skip to: 86948 /* 23682 */ MCD_OPC_CheckField, 20, 1, 0, 27, 247, 0, // Skip to: 86948 /* 23689 */ MCD_OPC_Decode, 160, 16, 144, 1, // Opcode: LD4B_IMM /* 23694 */ MCD_OPC_FilterValue, 4, 145, 0, 0, // Skip to: 23844 /* 23699 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23702 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23717 /* 23707 */ MCD_OPC_CheckPredicate, 0, 4, 247, 0, // Skip to: 86948 /* 23712 */ MCD_OPC_Decode, 239, 14, 136, 1, // Opcode: LD1RQ_H /* 23717 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 23739 /* 23722 */ MCD_OPC_CheckPredicate, 0, 245, 246, 0, // Skip to: 86948 /* 23727 */ MCD_OPC_CheckField, 20, 1, 0, 238, 246, 0, // Skip to: 86948 /* 23734 */ MCD_OPC_Decode, 240, 14, 137, 1, // Opcode: LD1RQ_H_IMM /* 23739 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23754 /* 23744 */ MCD_OPC_CheckPredicate, 0, 223, 246, 0, // Skip to: 86948 /* 23749 */ MCD_OPC_Decode, 149, 15, 136, 1, // Opcode: LD1SW_D /* 23754 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23769 /* 23759 */ MCD_OPC_CheckPredicate, 0, 208, 246, 0, // Skip to: 86948 /* 23764 */ MCD_OPC_Decode, 161, 17, 138, 1, // Opcode: LDFF1SW_D_REAL /* 23769 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23807 /* 23774 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 23777 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23792 /* 23782 */ MCD_OPC_CheckPredicate, 0, 185, 246, 0, // Skip to: 86948 /* 23787 */ MCD_OPC_Decode, 150, 15, 137, 1, // Opcode: LD1SW_D_IMM_REAL /* 23792 */ MCD_OPC_FilterValue, 1, 175, 246, 0, // Skip to: 86948 /* 23797 */ MCD_OPC_CheckPredicate, 0, 170, 246, 0, // Skip to: 86948 /* 23802 */ MCD_OPC_Decode, 181, 17, 137, 1, // Opcode: LDNF1SW_D_IMM_REAL /* 23807 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23822 /* 23812 */ MCD_OPC_CheckPredicate, 0, 155, 246, 0, // Skip to: 86948 /* 23817 */ MCD_OPC_Decode, 194, 17, 136, 1, // Opcode: LDNT1H_ZRR /* 23822 */ MCD_OPC_FilterValue, 7, 145, 246, 0, // Skip to: 86948 /* 23827 */ MCD_OPC_CheckPredicate, 0, 140, 246, 0, // Skip to: 86948 /* 23832 */ MCD_OPC_CheckField, 20, 1, 0, 133, 246, 0, // Skip to: 86948 /* 23839 */ MCD_OPC_Decode, 193, 17, 137, 1, // Opcode: LDNT1H_ZRI /* 23844 */ MCD_OPC_FilterValue, 5, 108, 0, 0, // Skip to: 23957 /* 23849 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23852 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23867 /* 23857 */ MCD_OPC_CheckPredicate, 0, 110, 246, 0, // Skip to: 86948 /* 23862 */ MCD_OPC_Decode, 205, 14, 136, 1, // Opcode: LD1H /* 23867 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23882 /* 23872 */ MCD_OPC_CheckPredicate, 0, 95, 246, 0, // Skip to: 86948 /* 23877 */ MCD_OPC_Decode, 154, 17, 138, 1, // Opcode: LDFF1H_REAL /* 23882 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23920 /* 23887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 23890 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23905 /* 23895 */ MCD_OPC_CheckPredicate, 0, 72, 246, 0, // Skip to: 86948 /* 23900 */ MCD_OPC_Decode, 208, 14, 137, 1, // Opcode: LD1H_IMM_REAL /* 23905 */ MCD_OPC_FilterValue, 1, 62, 246, 0, // Skip to: 86948 /* 23910 */ MCD_OPC_CheckPredicate, 0, 57, 246, 0, // Skip to: 86948 /* 23915 */ MCD_OPC_Decode, 174, 17, 137, 1, // Opcode: LDNF1H_IMM_REAL /* 23920 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23935 /* 23925 */ MCD_OPC_CheckPredicate, 0, 42, 246, 0, // Skip to: 86948 /* 23930 */ MCD_OPC_Decode, 199, 15, 139, 1, // Opcode: LD2H /* 23935 */ MCD_OPC_FilterValue, 7, 32, 246, 0, // Skip to: 86948 /* 23940 */ MCD_OPC_CheckPredicate, 0, 27, 246, 0, // Skip to: 86948 /* 23945 */ MCD_OPC_CheckField, 20, 1, 0, 20, 246, 0, // Skip to: 86948 /* 23952 */ MCD_OPC_Decode, 200, 15, 140, 1, // Opcode: LD2H_IMM /* 23957 */ MCD_OPC_FilterValue, 6, 108, 0, 0, // Skip to: 24070 /* 23962 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 23965 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23980 /* 23970 */ MCD_OPC_CheckPredicate, 0, 253, 245, 0, // Skip to: 86948 /* 23975 */ MCD_OPC_Decode, 209, 14, 136, 1, // Opcode: LD1H_S /* 23980 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23995 /* 23985 */ MCD_OPC_CheckPredicate, 0, 238, 245, 0, // Skip to: 86948 /* 23990 */ MCD_OPC_Decode, 155, 17, 138, 1, // Opcode: LDFF1H_S_REAL /* 23995 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24033 /* 24000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24003 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24018 /* 24008 */ MCD_OPC_CheckPredicate, 0, 215, 245, 0, // Skip to: 86948 /* 24013 */ MCD_OPC_Decode, 210, 14, 137, 1, // Opcode: LD1H_S_IMM_REAL /* 24018 */ MCD_OPC_FilterValue, 1, 205, 245, 0, // Skip to: 86948 /* 24023 */ MCD_OPC_CheckPredicate, 0, 200, 245, 0, // Skip to: 86948 /* 24028 */ MCD_OPC_Decode, 175, 17, 137, 1, // Opcode: LDNF1H_S_IMM_REAL /* 24033 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24048 /* 24038 */ MCD_OPC_CheckPredicate, 0, 185, 245, 0, // Skip to: 86948 /* 24043 */ MCD_OPC_Decode, 245, 15, 141, 1, // Opcode: LD3H /* 24048 */ MCD_OPC_FilterValue, 7, 175, 245, 0, // Skip to: 86948 /* 24053 */ MCD_OPC_CheckPredicate, 0, 170, 245, 0, // Skip to: 86948 /* 24058 */ MCD_OPC_CheckField, 20, 1, 0, 163, 245, 0, // Skip to: 86948 /* 24065 */ MCD_OPC_Decode, 246, 15, 142, 1, // Opcode: LD3H_IMM /* 24070 */ MCD_OPC_FilterValue, 7, 108, 0, 0, // Skip to: 24183 /* 24075 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24078 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24093 /* 24083 */ MCD_OPC_CheckPredicate, 0, 140, 245, 0, // Skip to: 86948 /* 24088 */ MCD_OPC_Decode, 206, 14, 136, 1, // Opcode: LD1H_D /* 24093 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24108 /* 24098 */ MCD_OPC_CheckPredicate, 0, 125, 245, 0, // Skip to: 86948 /* 24103 */ MCD_OPC_Decode, 153, 17, 138, 1, // Opcode: LDFF1H_D_REAL /* 24108 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24146 /* 24113 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24116 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24131 /* 24121 */ MCD_OPC_CheckPredicate, 0, 102, 245, 0, // Skip to: 86948 /* 24126 */ MCD_OPC_Decode, 207, 14, 137, 1, // Opcode: LD1H_D_IMM_REAL /* 24131 */ MCD_OPC_FilterValue, 1, 92, 245, 0, // Skip to: 86948 /* 24136 */ MCD_OPC_CheckPredicate, 0, 87, 245, 0, // Skip to: 86948 /* 24141 */ MCD_OPC_Decode, 173, 17, 137, 1, // Opcode: LDNF1H_D_IMM_REAL /* 24146 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24161 /* 24151 */ MCD_OPC_CheckPredicate, 0, 72, 245, 0, // Skip to: 86948 /* 24156 */ MCD_OPC_Decode, 177, 16, 143, 1, // Opcode: LD4H /* 24161 */ MCD_OPC_FilterValue, 7, 62, 245, 0, // Skip to: 86948 /* 24166 */ MCD_OPC_CheckPredicate, 0, 57, 245, 0, // Skip to: 86948 /* 24171 */ MCD_OPC_CheckField, 20, 1, 0, 50, 245, 0, // Skip to: 86948 /* 24178 */ MCD_OPC_Decode, 178, 16, 144, 1, // Opcode: LD4H_IMM /* 24183 */ MCD_OPC_FilterValue, 8, 145, 0, 0, // Skip to: 24333 /* 24188 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24191 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24206 /* 24196 */ MCD_OPC_CheckPredicate, 0, 27, 245, 0, // Skip to: 86948 /* 24201 */ MCD_OPC_Decode, 241, 14, 136, 1, // Opcode: LD1RQ_W /* 24206 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24228 /* 24211 */ MCD_OPC_CheckPredicate, 0, 12, 245, 0, // Skip to: 86948 /* 24216 */ MCD_OPC_CheckField, 20, 1, 0, 5, 245, 0, // Skip to: 86948 /* 24223 */ MCD_OPC_Decode, 242, 14, 137, 1, // Opcode: LD1RQ_W_IMM /* 24228 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24243 /* 24233 */ MCD_OPC_CheckPredicate, 0, 246, 244, 0, // Skip to: 86948 /* 24238 */ MCD_OPC_Decode, 145, 15, 136, 1, // Opcode: LD1SH_D /* 24243 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24258 /* 24248 */ MCD_OPC_CheckPredicate, 0, 231, 244, 0, // Skip to: 86948 /* 24253 */ MCD_OPC_Decode, 159, 17, 138, 1, // Opcode: LDFF1SH_D_REAL /* 24258 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24296 /* 24263 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24266 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24281 /* 24271 */ MCD_OPC_CheckPredicate, 0, 208, 244, 0, // Skip to: 86948 /* 24276 */ MCD_OPC_Decode, 146, 15, 137, 1, // Opcode: LD1SH_D_IMM_REAL /* 24281 */ MCD_OPC_FilterValue, 1, 198, 244, 0, // Skip to: 86948 /* 24286 */ MCD_OPC_CheckPredicate, 0, 193, 244, 0, // Skip to: 86948 /* 24291 */ MCD_OPC_Decode, 179, 17, 137, 1, // Opcode: LDNF1SH_D_IMM_REAL /* 24296 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24311 /* 24301 */ MCD_OPC_CheckPredicate, 0, 178, 244, 0, // Skip to: 86948 /* 24306 */ MCD_OPC_Decode, 196, 17, 136, 1, // Opcode: LDNT1W_ZRR /* 24311 */ MCD_OPC_FilterValue, 7, 168, 244, 0, // Skip to: 86948 /* 24316 */ MCD_OPC_CheckPredicate, 0, 163, 244, 0, // Skip to: 86948 /* 24321 */ MCD_OPC_CheckField, 20, 1, 0, 156, 244, 0, // Skip to: 86948 /* 24328 */ MCD_OPC_Decode, 195, 17, 137, 1, // Opcode: LDNT1W_ZRI /* 24333 */ MCD_OPC_FilterValue, 9, 108, 0, 0, // Skip to: 24446 /* 24338 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24341 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24356 /* 24346 */ MCD_OPC_CheckPredicate, 0, 133, 244, 0, // Skip to: 86948 /* 24351 */ MCD_OPC_Decode, 147, 15, 136, 1, // Opcode: LD1SH_S /* 24356 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24371 /* 24361 */ MCD_OPC_CheckPredicate, 0, 118, 244, 0, // Skip to: 86948 /* 24366 */ MCD_OPC_Decode, 160, 17, 138, 1, // Opcode: LDFF1SH_S_REAL /* 24371 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24409 /* 24376 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24379 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24394 /* 24384 */ MCD_OPC_CheckPredicate, 0, 95, 244, 0, // Skip to: 86948 /* 24389 */ MCD_OPC_Decode, 148, 15, 137, 1, // Opcode: LD1SH_S_IMM_REAL /* 24394 */ MCD_OPC_FilterValue, 1, 85, 244, 0, // Skip to: 86948 /* 24399 */ MCD_OPC_CheckPredicate, 0, 80, 244, 0, // Skip to: 86948 /* 24404 */ MCD_OPC_Decode, 180, 17, 137, 1, // Opcode: LDNF1SH_S_IMM_REAL /* 24409 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24424 /* 24414 */ MCD_OPC_CheckPredicate, 0, 65, 244, 0, // Skip to: 86948 /* 24419 */ MCD_OPC_Decode, 231, 15, 139, 1, // Opcode: LD2W /* 24424 */ MCD_OPC_FilterValue, 7, 55, 244, 0, // Skip to: 86948 /* 24429 */ MCD_OPC_CheckPredicate, 0, 50, 244, 0, // Skip to: 86948 /* 24434 */ MCD_OPC_CheckField, 20, 1, 0, 43, 244, 0, // Skip to: 86948 /* 24441 */ MCD_OPC_Decode, 232, 15, 140, 1, // Opcode: LD2W_IMM /* 24446 */ MCD_OPC_FilterValue, 10, 108, 0, 0, // Skip to: 24559 /* 24451 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24454 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24469 /* 24459 */ MCD_OPC_CheckPredicate, 0, 20, 244, 0, // Skip to: 86948 /* 24464 */ MCD_OPC_Decode, 183, 15, 136, 1, // Opcode: LD1W /* 24469 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24484 /* 24474 */ MCD_OPC_CheckPredicate, 0, 5, 244, 0, // Skip to: 86948 /* 24479 */ MCD_OPC_Decode, 163, 17, 138, 1, // Opcode: LDFF1W_REAL /* 24484 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24522 /* 24489 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24492 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24507 /* 24497 */ MCD_OPC_CheckPredicate, 0, 238, 243, 0, // Skip to: 86948 /* 24502 */ MCD_OPC_Decode, 186, 15, 137, 1, // Opcode: LD1W_IMM_REAL /* 24507 */ MCD_OPC_FilterValue, 1, 228, 243, 0, // Skip to: 86948 /* 24512 */ MCD_OPC_CheckPredicate, 0, 223, 243, 0, // Skip to: 86948 /* 24517 */ MCD_OPC_Decode, 183, 17, 137, 1, // Opcode: LDNF1W_IMM_REAL /* 24522 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24537 /* 24527 */ MCD_OPC_CheckPredicate, 0, 208, 243, 0, // Skip to: 86948 /* 24532 */ MCD_OPC_Decode, 149, 16, 141, 1, // Opcode: LD3W /* 24537 */ MCD_OPC_FilterValue, 7, 198, 243, 0, // Skip to: 86948 /* 24542 */ MCD_OPC_CheckPredicate, 0, 193, 243, 0, // Skip to: 86948 /* 24547 */ MCD_OPC_CheckField, 20, 1, 0, 186, 243, 0, // Skip to: 86948 /* 24554 */ MCD_OPC_Decode, 150, 16, 142, 1, // Opcode: LD3W_IMM /* 24559 */ MCD_OPC_FilterValue, 11, 108, 0, 0, // Skip to: 24672 /* 24564 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24567 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24582 /* 24572 */ MCD_OPC_CheckPredicate, 0, 163, 243, 0, // Skip to: 86948 /* 24577 */ MCD_OPC_Decode, 184, 15, 136, 1, // Opcode: LD1W_D /* 24582 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24597 /* 24587 */ MCD_OPC_CheckPredicate, 0, 148, 243, 0, // Skip to: 86948 /* 24592 */ MCD_OPC_Decode, 162, 17, 138, 1, // Opcode: LDFF1W_D_REAL /* 24597 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24635 /* 24602 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24605 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24620 /* 24610 */ MCD_OPC_CheckPredicate, 0, 125, 243, 0, // Skip to: 86948 /* 24615 */ MCD_OPC_Decode, 185, 15, 137, 1, // Opcode: LD1W_D_IMM_REAL /* 24620 */ MCD_OPC_FilterValue, 1, 115, 243, 0, // Skip to: 86948 /* 24625 */ MCD_OPC_CheckPredicate, 0, 110, 243, 0, // Skip to: 86948 /* 24630 */ MCD_OPC_Decode, 182, 17, 137, 1, // Opcode: LDNF1W_D_IMM_REAL /* 24635 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24650 /* 24640 */ MCD_OPC_CheckPredicate, 0, 95, 243, 0, // Skip to: 86948 /* 24645 */ MCD_OPC_Decode, 195, 16, 143, 1, // Opcode: LD4W /* 24650 */ MCD_OPC_FilterValue, 7, 85, 243, 0, // Skip to: 86948 /* 24655 */ MCD_OPC_CheckPredicate, 0, 80, 243, 0, // Skip to: 86948 /* 24660 */ MCD_OPC_CheckField, 20, 1, 0, 73, 243, 0, // Skip to: 86948 /* 24667 */ MCD_OPC_Decode, 196, 16, 144, 1, // Opcode: LD4W_IMM /* 24672 */ MCD_OPC_FilterValue, 12, 145, 0, 0, // Skip to: 24822 /* 24677 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24680 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24695 /* 24685 */ MCD_OPC_CheckPredicate, 0, 50, 243, 0, // Skip to: 86948 /* 24690 */ MCD_OPC_Decode, 237, 14, 136, 1, // Opcode: LD1RQ_D /* 24695 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24717 /* 24700 */ MCD_OPC_CheckPredicate, 0, 35, 243, 0, // Skip to: 86948 /* 24705 */ MCD_OPC_CheckField, 20, 1, 0, 28, 243, 0, // Skip to: 86948 /* 24712 */ MCD_OPC_Decode, 238, 14, 137, 1, // Opcode: LD1RQ_D_IMM /* 24717 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24732 /* 24722 */ MCD_OPC_CheckPredicate, 0, 13, 243, 0, // Skip to: 86948 /* 24727 */ MCD_OPC_Decode, 139, 15, 136, 1, // Opcode: LD1SB_D /* 24732 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24747 /* 24737 */ MCD_OPC_CheckPredicate, 0, 254, 242, 0, // Skip to: 86948 /* 24742 */ MCD_OPC_Decode, 156, 17, 138, 1, // Opcode: LDFF1SB_D_REAL /* 24747 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24785 /* 24752 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24755 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24770 /* 24760 */ MCD_OPC_CheckPredicate, 0, 231, 242, 0, // Skip to: 86948 /* 24765 */ MCD_OPC_Decode, 140, 15, 137, 1, // Opcode: LD1SB_D_IMM_REAL /* 24770 */ MCD_OPC_FilterValue, 1, 221, 242, 0, // Skip to: 86948 /* 24775 */ MCD_OPC_CheckPredicate, 0, 216, 242, 0, // Skip to: 86948 /* 24780 */ MCD_OPC_Decode, 176, 17, 137, 1, // Opcode: LDNF1SB_D_IMM_REAL /* 24785 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24800 /* 24790 */ MCD_OPC_CheckPredicate, 0, 201, 242, 0, // Skip to: 86948 /* 24795 */ MCD_OPC_Decode, 192, 17, 136, 1, // Opcode: LDNT1D_ZRR /* 24800 */ MCD_OPC_FilterValue, 7, 191, 242, 0, // Skip to: 86948 /* 24805 */ MCD_OPC_CheckPredicate, 0, 186, 242, 0, // Skip to: 86948 /* 24810 */ MCD_OPC_CheckField, 20, 1, 0, 179, 242, 0, // Skip to: 86948 /* 24817 */ MCD_OPC_Decode, 191, 17, 137, 1, // Opcode: LDNT1D_ZRI /* 24822 */ MCD_OPC_FilterValue, 13, 108, 0, 0, // Skip to: 24935 /* 24827 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24830 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24845 /* 24835 */ MCD_OPC_CheckPredicate, 0, 156, 242, 0, // Skip to: 86948 /* 24840 */ MCD_OPC_Decode, 143, 15, 136, 1, // Opcode: LD1SB_S /* 24845 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24860 /* 24850 */ MCD_OPC_CheckPredicate, 0, 141, 242, 0, // Skip to: 86948 /* 24855 */ MCD_OPC_Decode, 158, 17, 138, 1, // Opcode: LDFF1SB_S_REAL /* 24860 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24898 /* 24865 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24868 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24883 /* 24873 */ MCD_OPC_CheckPredicate, 0, 118, 242, 0, // Skip to: 86948 /* 24878 */ MCD_OPC_Decode, 144, 15, 137, 1, // Opcode: LD1SB_S_IMM_REAL /* 24883 */ MCD_OPC_FilterValue, 1, 108, 242, 0, // Skip to: 86948 /* 24888 */ MCD_OPC_CheckPredicate, 0, 103, 242, 0, // Skip to: 86948 /* 24893 */ MCD_OPC_Decode, 178, 17, 137, 1, // Opcode: LDNF1SB_S_IMM_REAL /* 24898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24913 /* 24903 */ MCD_OPC_CheckPredicate, 0, 88, 242, 0, // Skip to: 86948 /* 24908 */ MCD_OPC_Decode, 197, 15, 139, 1, // Opcode: LD2D /* 24913 */ MCD_OPC_FilterValue, 7, 78, 242, 0, // Skip to: 86948 /* 24918 */ MCD_OPC_CheckPredicate, 0, 73, 242, 0, // Skip to: 86948 /* 24923 */ MCD_OPC_CheckField, 20, 1, 0, 66, 242, 0, // Skip to: 86948 /* 24930 */ MCD_OPC_Decode, 198, 15, 140, 1, // Opcode: LD2D_IMM /* 24935 */ MCD_OPC_FilterValue, 14, 108, 0, 0, // Skip to: 25048 /* 24940 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 24943 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24958 /* 24948 */ MCD_OPC_CheckPredicate, 0, 43, 242, 0, // Skip to: 86948 /* 24953 */ MCD_OPC_Decode, 141, 15, 136, 1, // Opcode: LD1SB_H /* 24958 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24973 /* 24963 */ MCD_OPC_CheckPredicate, 0, 28, 242, 0, // Skip to: 86948 /* 24968 */ MCD_OPC_Decode, 157, 17, 138, 1, // Opcode: LDFF1SB_H_REAL /* 24973 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 25011 /* 24978 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 24981 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24996 /* 24986 */ MCD_OPC_CheckPredicate, 0, 5, 242, 0, // Skip to: 86948 /* 24991 */ MCD_OPC_Decode, 142, 15, 137, 1, // Opcode: LD1SB_H_IMM_REAL /* 24996 */ MCD_OPC_FilterValue, 1, 251, 241, 0, // Skip to: 86948 /* 25001 */ MCD_OPC_CheckPredicate, 0, 246, 241, 0, // Skip to: 86948 /* 25006 */ MCD_OPC_Decode, 177, 17, 137, 1, // Opcode: LDNF1SB_H_IMM_REAL /* 25011 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25026 /* 25016 */ MCD_OPC_CheckPredicate, 0, 231, 241, 0, // Skip to: 86948 /* 25021 */ MCD_OPC_Decode, 243, 15, 141, 1, // Opcode: LD3D /* 25026 */ MCD_OPC_FilterValue, 7, 221, 241, 0, // Skip to: 86948 /* 25031 */ MCD_OPC_CheckPredicate, 0, 216, 241, 0, // Skip to: 86948 /* 25036 */ MCD_OPC_CheckField, 20, 1, 0, 209, 241, 0, // Skip to: 86948 /* 25043 */ MCD_OPC_Decode, 244, 15, 142, 1, // Opcode: LD3D_IMM /* 25048 */ MCD_OPC_FilterValue, 15, 199, 241, 0, // Skip to: 86948 /* 25053 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25056 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 25071 /* 25061 */ MCD_OPC_CheckPredicate, 0, 186, 241, 0, // Skip to: 86948 /* 25066 */ MCD_OPC_Decode, 187, 14, 136, 1, // Opcode: LD1D /* 25071 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 25086 /* 25076 */ MCD_OPC_CheckPredicate, 0, 171, 241, 0, // Skip to: 86948 /* 25081 */ MCD_OPC_Decode, 152, 17, 138, 1, // Opcode: LDFF1D_REAL /* 25086 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 25124 /* 25091 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 25094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 25109 /* 25099 */ MCD_OPC_CheckPredicate, 0, 148, 241, 0, // Skip to: 86948 /* 25104 */ MCD_OPC_Decode, 188, 14, 137, 1, // Opcode: LD1D_IMM_REAL /* 25109 */ MCD_OPC_FilterValue, 1, 138, 241, 0, // Skip to: 86948 /* 25114 */ MCD_OPC_CheckPredicate, 0, 133, 241, 0, // Skip to: 86948 /* 25119 */ MCD_OPC_Decode, 172, 17, 137, 1, // Opcode: LDNF1D_IMM_REAL /* 25124 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25139 /* 25129 */ MCD_OPC_CheckPredicate, 0, 118, 241, 0, // Skip to: 86948 /* 25134 */ MCD_OPC_Decode, 161, 16, 143, 1, // Opcode: LD4D /* 25139 */ MCD_OPC_FilterValue, 7, 108, 241, 0, // Skip to: 86948 /* 25144 */ MCD_OPC_CheckPredicate, 0, 103, 241, 0, // Skip to: 86948 /* 25149 */ MCD_OPC_CheckField, 20, 1, 0, 96, 241, 0, // Skip to: 86948 /* 25156 */ MCD_OPC_Decode, 162, 16, 144, 1, // Opcode: LD4D_IMM /* 25161 */ MCD_OPC_FilterValue, 6, 165, 6, 0, // Skip to: 26867 /* 25166 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 25169 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 25255 /* 25174 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25177 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25191 /* 25182 */ MCD_OPC_CheckPredicate, 0, 65, 241, 0, // Skip to: 86948 /* 25187 */ MCD_OPC_Decode, 142, 13, 127, // Opcode: GLD1SB_D_UXTW_REAL /* 25191 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25205 /* 25196 */ MCD_OPC_CheckPredicate, 0, 51, 241, 0, // Skip to: 86948 /* 25201 */ MCD_OPC_Decode, 206, 13, 127, // Opcode: GLDFF1SB_D_UXTW_REAL /* 25205 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25219 /* 25210 */ MCD_OPC_CheckPredicate, 0, 37, 241, 0, // Skip to: 86948 /* 25215 */ MCD_OPC_Decode, 244, 12, 127, // Opcode: GLD1B_D_UXTW_REAL /* 25219 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25233 /* 25224 */ MCD_OPC_CheckPredicate, 0, 23, 241, 0, // Skip to: 86948 /* 25229 */ MCD_OPC_Decode, 180, 13, 127, // Opcode: GLDFF1B_D_UXTW_REAL /* 25233 */ MCD_OPC_FilterValue, 7, 14, 241, 0, // Skip to: 86948 /* 25238 */ MCD_OPC_CheckPredicate, 0, 9, 241, 0, // Skip to: 86948 /* 25243 */ MCD_OPC_CheckField, 4, 1, 0, 2, 241, 0, // Skip to: 86948 /* 25250 */ MCD_OPC_Decode, 253, 20, 135, 1, // Opcode: PRFB_D_PZI /* 25255 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 25411 /* 25260 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25263 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25285 /* 25268 */ MCD_OPC_CheckPredicate, 0, 235, 240, 0, // Skip to: 86948 /* 25273 */ MCD_OPC_CheckField, 4, 1, 0, 228, 240, 0, // Skip to: 86948 /* 25280 */ MCD_OPC_Decode, 128, 21, 128, 1, // Opcode: PRFB_D_UXTW_SCALED /* 25285 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 25307 /* 25290 */ MCD_OPC_CheckPredicate, 0, 213, 240, 0, // Skip to: 86948 /* 25295 */ MCD_OPC_CheckField, 4, 1, 0, 206, 240, 0, // Skip to: 86948 /* 25302 */ MCD_OPC_Decode, 146, 21, 128, 1, // Opcode: PRFH_D_UXTW_SCALED /* 25307 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 25329 /* 25312 */ MCD_OPC_CheckPredicate, 0, 191, 240, 0, // Skip to: 86948 /* 25317 */ MCD_OPC_CheckField, 4, 1, 0, 184, 240, 0, // Skip to: 86948 /* 25324 */ MCD_OPC_Decode, 161, 21, 128, 1, // Opcode: PRFW_D_UXTW_SCALED /* 25329 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 25351 /* 25334 */ MCD_OPC_CheckPredicate, 0, 169, 240, 0, // Skip to: 86948 /* 25339 */ MCD_OPC_CheckField, 4, 1, 0, 162, 240, 0, // Skip to: 86948 /* 25346 */ MCD_OPC_Decode, 137, 21, 128, 1, // Opcode: PRFD_D_UXTW_SCALED /* 25351 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 25366 /* 25356 */ MCD_OPC_CheckPredicate, 0, 147, 240, 0, // Skip to: 86948 /* 25361 */ MCD_OPC_Decode, 139, 13, 132, 1, // Opcode: GLD1SB_D_IMM_REAL /* 25366 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 25381 /* 25371 */ MCD_OPC_CheckPredicate, 0, 132, 240, 0, // Skip to: 86948 /* 25376 */ MCD_OPC_Decode, 203, 13, 132, 1, // Opcode: GLDFF1SB_D_IMM_REAL /* 25381 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25396 /* 25386 */ MCD_OPC_CheckPredicate, 0, 117, 240, 0, // Skip to: 86948 /* 25391 */ MCD_OPC_Decode, 241, 12, 132, 1, // Opcode: GLD1B_D_IMM_REAL /* 25396 */ MCD_OPC_FilterValue, 7, 107, 240, 0, // Skip to: 86948 /* 25401 */ MCD_OPC_CheckPredicate, 0, 102, 240, 0, // Skip to: 86948 /* 25406 */ MCD_OPC_Decode, 177, 13, 132, 1, // Opcode: GLDFF1B_D_IMM_REAL /* 25411 */ MCD_OPC_FilterValue, 2, 115, 0, 0, // Skip to: 25531 /* 25416 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25419 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25433 /* 25424 */ MCD_OPC_CheckPredicate, 0, 79, 240, 0, // Skip to: 86948 /* 25429 */ MCD_OPC_Decode, 141, 13, 127, // Opcode: GLD1SB_D_SXTW_REAL /* 25433 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25447 /* 25438 */ MCD_OPC_CheckPredicate, 0, 65, 240, 0, // Skip to: 86948 /* 25443 */ MCD_OPC_Decode, 205, 13, 127, // Opcode: GLDFF1SB_D_SXTW_REAL /* 25447 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25461 /* 25452 */ MCD_OPC_CheckPredicate, 0, 51, 240, 0, // Skip to: 86948 /* 25457 */ MCD_OPC_Decode, 243, 12, 127, // Opcode: GLD1B_D_SXTW_REAL /* 25461 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25475 /* 25466 */ MCD_OPC_CheckPredicate, 0, 37, 240, 0, // Skip to: 86948 /* 25471 */ MCD_OPC_Decode, 179, 13, 127, // Opcode: GLDFF1B_D_SXTW_REAL /* 25475 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 25489 /* 25480 */ MCD_OPC_CheckPredicate, 0, 23, 240, 0, // Skip to: 86948 /* 25485 */ MCD_OPC_Decode, 140, 13, 127, // Opcode: GLD1SB_D_REAL /* 25489 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 25503 /* 25494 */ MCD_OPC_CheckPredicate, 0, 9, 240, 0, // Skip to: 86948 /* 25499 */ MCD_OPC_Decode, 204, 13, 127, // Opcode: GLDFF1SB_D_REAL /* 25503 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 25517 /* 25508 */ MCD_OPC_CheckPredicate, 0, 251, 239, 0, // Skip to: 86948 /* 25513 */ MCD_OPC_Decode, 242, 12, 127, // Opcode: GLD1B_D_REAL /* 25517 */ MCD_OPC_FilterValue, 7, 242, 239, 0, // Skip to: 86948 /* 25522 */ MCD_OPC_CheckPredicate, 0, 237, 239, 0, // Skip to: 86948 /* 25527 */ MCD_OPC_Decode, 178, 13, 127, // Opcode: GLDFF1B_D_REAL /* 25531 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 25715 /* 25536 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25539 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25561 /* 25544 */ MCD_OPC_CheckPredicate, 0, 215, 239, 0, // Skip to: 86948 /* 25549 */ MCD_OPC_CheckField, 4, 1, 0, 208, 239, 0, // Skip to: 86948 /* 25556 */ MCD_OPC_Decode, 255, 20, 128, 1, // Opcode: PRFB_D_SXTW_SCALED /* 25561 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 25583 /* 25566 */ MCD_OPC_CheckPredicate, 0, 193, 239, 0, // Skip to: 86948 /* 25571 */ MCD_OPC_CheckField, 4, 1, 0, 186, 239, 0, // Skip to: 86948 /* 25578 */ MCD_OPC_Decode, 145, 21, 128, 1, // Opcode: PRFH_D_SXTW_SCALED /* 25583 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 25605 /* 25588 */ MCD_OPC_CheckPredicate, 0, 171, 239, 0, // Skip to: 86948 /* 25593 */ MCD_OPC_CheckField, 4, 1, 0, 164, 239, 0, // Skip to: 86948 /* 25600 */ MCD_OPC_Decode, 160, 21, 128, 1, // Opcode: PRFW_D_SXTW_SCALED /* 25605 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 25627 /* 25610 */ MCD_OPC_CheckPredicate, 0, 149, 239, 0, // Skip to: 86948 /* 25615 */ MCD_OPC_CheckField, 4, 1, 0, 142, 239, 0, // Skip to: 86948 /* 25622 */ MCD_OPC_Decode, 136, 21, 128, 1, // Opcode: PRFD_D_SXTW_SCALED /* 25627 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 25649 /* 25632 */ MCD_OPC_CheckPredicate, 0, 127, 239, 0, // Skip to: 86948 /* 25637 */ MCD_OPC_CheckField, 4, 1, 0, 120, 239, 0, // Skip to: 86948 /* 25644 */ MCD_OPC_Decode, 254, 20, 128, 1, // Opcode: PRFB_D_SCALED /* 25649 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 25671 /* 25654 */ MCD_OPC_CheckPredicate, 0, 105, 239, 0, // Skip to: 86948 /* 25659 */ MCD_OPC_CheckField, 4, 1, 0, 98, 239, 0, // Skip to: 86948 /* 25666 */ MCD_OPC_Decode, 144, 21, 128, 1, // Opcode: PRFH_D_SCALED /* 25671 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 25693 /* 25676 */ MCD_OPC_CheckPredicate, 0, 83, 239, 0, // Skip to: 86948 /* 25681 */ MCD_OPC_CheckField, 4, 1, 0, 76, 239, 0, // Skip to: 86948 /* 25688 */ MCD_OPC_Decode, 159, 21, 128, 1, // Opcode: PRFW_D_SCALED /* 25693 */ MCD_OPC_FilterValue, 7, 66, 239, 0, // Skip to: 86948 /* 25698 */ MCD_OPC_CheckPredicate, 0, 61, 239, 0, // Skip to: 86948 /* 25703 */ MCD_OPC_CheckField, 4, 1, 0, 54, 239, 0, // Skip to: 86948 /* 25710 */ MCD_OPC_Decode, 135, 21, 128, 1, // Opcode: PRFD_D_SCALED /* 25715 */ MCD_OPC_FilterValue, 4, 81, 0, 0, // Skip to: 25801 /* 25720 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25723 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25737 /* 25728 */ MCD_OPC_CheckPredicate, 0, 31, 239, 0, // Skip to: 86948 /* 25733 */ MCD_OPC_Decode, 151, 13, 127, // Opcode: GLD1SH_D_UXTW_REAL /* 25737 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25751 /* 25742 */ MCD_OPC_CheckPredicate, 0, 17, 239, 0, // Skip to: 86948 /* 25747 */ MCD_OPC_Decode, 215, 13, 127, // Opcode: GLDFF1SH_D_UXTW_REAL /* 25751 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25765 /* 25756 */ MCD_OPC_CheckPredicate, 0, 3, 239, 0, // Skip to: 86948 /* 25761 */ MCD_OPC_Decode, 132, 13, 127, // Opcode: GLD1H_D_UXTW_REAL /* 25765 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25779 /* 25770 */ MCD_OPC_CheckPredicate, 0, 245, 238, 0, // Skip to: 86948 /* 25775 */ MCD_OPC_Decode, 196, 13, 127, // Opcode: GLDFF1H_D_UXTW_REAL /* 25779 */ MCD_OPC_FilterValue, 7, 236, 238, 0, // Skip to: 86948 /* 25784 */ MCD_OPC_CheckPredicate, 0, 231, 238, 0, // Skip to: 86948 /* 25789 */ MCD_OPC_CheckField, 4, 1, 0, 224, 238, 0, // Skip to: 86948 /* 25796 */ MCD_OPC_Decode, 143, 21, 135, 1, // Opcode: PRFH_D_PZI /* 25801 */ MCD_OPC_FilterValue, 5, 119, 0, 0, // Skip to: 25925 /* 25806 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25809 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25823 /* 25814 */ MCD_OPC_CheckPredicate, 0, 201, 238, 0, // Skip to: 86948 /* 25819 */ MCD_OPC_Decode, 152, 13, 127, // Opcode: GLD1SH_D_UXTW_SCALED_REAL /* 25823 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25837 /* 25828 */ MCD_OPC_CheckPredicate, 0, 187, 238, 0, // Skip to: 86948 /* 25833 */ MCD_OPC_Decode, 216, 13, 127, // Opcode: GLDFF1SH_D_UXTW_SCALED_REAL /* 25837 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25851 /* 25842 */ MCD_OPC_CheckPredicate, 0, 173, 238, 0, // Skip to: 86948 /* 25847 */ MCD_OPC_Decode, 133, 13, 127, // Opcode: GLD1H_D_UXTW_SCALED_REAL /* 25851 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25865 /* 25856 */ MCD_OPC_CheckPredicate, 0, 159, 238, 0, // Skip to: 86948 /* 25861 */ MCD_OPC_Decode, 197, 13, 127, // Opcode: GLDFF1H_D_UXTW_SCALED_REAL /* 25865 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 25880 /* 25870 */ MCD_OPC_CheckPredicate, 0, 145, 238, 0, // Skip to: 86948 /* 25875 */ MCD_OPC_Decode, 146, 13, 132, 1, // Opcode: GLD1SH_D_IMM_REAL /* 25880 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 25895 /* 25885 */ MCD_OPC_CheckPredicate, 0, 130, 238, 0, // Skip to: 86948 /* 25890 */ MCD_OPC_Decode, 210, 13, 132, 1, // Opcode: GLDFF1SH_D_IMM_REAL /* 25895 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25910 /* 25900 */ MCD_OPC_CheckPredicate, 0, 115, 238, 0, // Skip to: 86948 /* 25905 */ MCD_OPC_Decode, 255, 12, 132, 1, // Opcode: GLD1H_D_IMM_REAL /* 25910 */ MCD_OPC_FilterValue, 7, 105, 238, 0, // Skip to: 86948 /* 25915 */ MCD_OPC_CheckPredicate, 0, 100, 238, 0, // Skip to: 86948 /* 25920 */ MCD_OPC_Decode, 191, 13, 132, 1, // Opcode: GLDFF1H_D_IMM_REAL /* 25925 */ MCD_OPC_FilterValue, 6, 115, 0, 0, // Skip to: 26045 /* 25930 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 25933 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25947 /* 25938 */ MCD_OPC_CheckPredicate, 0, 77, 238, 0, // Skip to: 86948 /* 25943 */ MCD_OPC_Decode, 149, 13, 127, // Opcode: GLD1SH_D_SXTW_REAL /* 25947 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25961 /* 25952 */ MCD_OPC_CheckPredicate, 0, 63, 238, 0, // Skip to: 86948 /* 25957 */ MCD_OPC_Decode, 213, 13, 127, // Opcode: GLDFF1SH_D_SXTW_REAL /* 25961 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25975 /* 25966 */ MCD_OPC_CheckPredicate, 0, 49, 238, 0, // Skip to: 86948 /* 25971 */ MCD_OPC_Decode, 130, 13, 127, // Opcode: GLD1H_D_SXTW_REAL /* 25975 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25989 /* 25980 */ MCD_OPC_CheckPredicate, 0, 35, 238, 0, // Skip to: 86948 /* 25985 */ MCD_OPC_Decode, 194, 13, 127, // Opcode: GLDFF1H_D_SXTW_REAL /* 25989 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26003 /* 25994 */ MCD_OPC_CheckPredicate, 0, 21, 238, 0, // Skip to: 86948 /* 25999 */ MCD_OPC_Decode, 147, 13, 127, // Opcode: GLD1SH_D_REAL /* 26003 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26017 /* 26008 */ MCD_OPC_CheckPredicate, 0, 7, 238, 0, // Skip to: 86948 /* 26013 */ MCD_OPC_Decode, 211, 13, 127, // Opcode: GLDFF1SH_D_REAL /* 26017 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26031 /* 26022 */ MCD_OPC_CheckPredicate, 0, 249, 237, 0, // Skip to: 86948 /* 26027 */ MCD_OPC_Decode, 128, 13, 127, // Opcode: GLD1H_D_REAL /* 26031 */ MCD_OPC_FilterValue, 7, 240, 237, 0, // Skip to: 86948 /* 26036 */ MCD_OPC_CheckPredicate, 0, 235, 237, 0, // Skip to: 86948 /* 26041 */ MCD_OPC_Decode, 192, 13, 127, // Opcode: GLDFF1H_D_REAL /* 26045 */ MCD_OPC_FilterValue, 7, 115, 0, 0, // Skip to: 26165 /* 26050 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26053 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26067 /* 26058 */ MCD_OPC_CheckPredicate, 0, 213, 237, 0, // Skip to: 86948 /* 26063 */ MCD_OPC_Decode, 150, 13, 127, // Opcode: GLD1SH_D_SXTW_SCALED_REAL /* 26067 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26081 /* 26072 */ MCD_OPC_CheckPredicate, 0, 199, 237, 0, // Skip to: 86948 /* 26077 */ MCD_OPC_Decode, 214, 13, 127, // Opcode: GLDFF1SH_D_SXTW_SCALED_REAL /* 26081 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26095 /* 26086 */ MCD_OPC_CheckPredicate, 0, 185, 237, 0, // Skip to: 86948 /* 26091 */ MCD_OPC_Decode, 131, 13, 127, // Opcode: GLD1H_D_SXTW_SCALED_REAL /* 26095 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26109 /* 26100 */ MCD_OPC_CheckPredicate, 0, 171, 237, 0, // Skip to: 86948 /* 26105 */ MCD_OPC_Decode, 195, 13, 127, // Opcode: GLDFF1H_D_SXTW_SCALED_REAL /* 26109 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26123 /* 26114 */ MCD_OPC_CheckPredicate, 0, 157, 237, 0, // Skip to: 86948 /* 26119 */ MCD_OPC_Decode, 148, 13, 127, // Opcode: GLD1SH_D_SCALED_REAL /* 26123 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26137 /* 26128 */ MCD_OPC_CheckPredicate, 0, 143, 237, 0, // Skip to: 86948 /* 26133 */ MCD_OPC_Decode, 212, 13, 127, // Opcode: GLDFF1SH_D_SCALED_REAL /* 26137 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26151 /* 26142 */ MCD_OPC_CheckPredicate, 0, 129, 237, 0, // Skip to: 86948 /* 26147 */ MCD_OPC_Decode, 129, 13, 127, // Opcode: GLD1H_D_SCALED_REAL /* 26151 */ MCD_OPC_FilterValue, 7, 120, 237, 0, // Skip to: 86948 /* 26156 */ MCD_OPC_CheckPredicate, 0, 115, 237, 0, // Skip to: 86948 /* 26161 */ MCD_OPC_Decode, 193, 13, 127, // Opcode: GLDFF1H_D_SCALED_REAL /* 26165 */ MCD_OPC_FilterValue, 8, 81, 0, 0, // Skip to: 26251 /* 26170 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26173 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26187 /* 26178 */ MCD_OPC_CheckPredicate, 0, 93, 237, 0, // Skip to: 86948 /* 26183 */ MCD_OPC_Decode, 163, 13, 127, // Opcode: GLD1SW_D_UXTW_REAL /* 26187 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26201 /* 26192 */ MCD_OPC_CheckPredicate, 0, 79, 237, 0, // Skip to: 86948 /* 26197 */ MCD_OPC_Decode, 227, 13, 127, // Opcode: GLDFF1SW_D_UXTW_REAL /* 26201 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26215 /* 26206 */ MCD_OPC_CheckPredicate, 0, 65, 237, 0, // Skip to: 86948 /* 26211 */ MCD_OPC_Decode, 170, 13, 127, // Opcode: GLD1W_D_UXTW_REAL /* 26215 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26229 /* 26220 */ MCD_OPC_CheckPredicate, 0, 51, 237, 0, // Skip to: 86948 /* 26225 */ MCD_OPC_Decode, 234, 13, 127, // Opcode: GLDFF1W_D_UXTW_REAL /* 26229 */ MCD_OPC_FilterValue, 7, 42, 237, 0, // Skip to: 86948 /* 26234 */ MCD_OPC_CheckPredicate, 0, 37, 237, 0, // Skip to: 86948 /* 26239 */ MCD_OPC_CheckField, 4, 1, 0, 30, 237, 0, // Skip to: 86948 /* 26246 */ MCD_OPC_Decode, 158, 21, 135, 1, // Opcode: PRFW_D_PZI /* 26251 */ MCD_OPC_FilterValue, 9, 119, 0, 0, // Skip to: 26375 /* 26256 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26273 /* 26264 */ MCD_OPC_CheckPredicate, 0, 7, 237, 0, // Skip to: 86948 /* 26269 */ MCD_OPC_Decode, 164, 13, 127, // Opcode: GLD1SW_D_UXTW_SCALED_REAL /* 26273 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26287 /* 26278 */ MCD_OPC_CheckPredicate, 0, 249, 236, 0, // Skip to: 86948 /* 26283 */ MCD_OPC_Decode, 228, 13, 127, // Opcode: GLDFF1SW_D_UXTW_SCALED_REAL /* 26287 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26301 /* 26292 */ MCD_OPC_CheckPredicate, 0, 235, 236, 0, // Skip to: 86948 /* 26297 */ MCD_OPC_Decode, 171, 13, 127, // Opcode: GLD1W_D_UXTW_SCALED_REAL /* 26301 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26315 /* 26306 */ MCD_OPC_CheckPredicate, 0, 221, 236, 0, // Skip to: 86948 /* 26311 */ MCD_OPC_Decode, 235, 13, 127, // Opcode: GLDFF1W_D_UXTW_SCALED_REAL /* 26315 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 26330 /* 26320 */ MCD_OPC_CheckPredicate, 0, 207, 236, 0, // Skip to: 86948 /* 26325 */ MCD_OPC_Decode, 158, 13, 132, 1, // Opcode: GLD1SW_D_IMM_REAL /* 26330 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 26345 /* 26335 */ MCD_OPC_CheckPredicate, 0, 192, 236, 0, // Skip to: 86948 /* 26340 */ MCD_OPC_Decode, 222, 13, 132, 1, // Opcode: GLDFF1SW_D_IMM_REAL /* 26345 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 26360 /* 26350 */ MCD_OPC_CheckPredicate, 0, 177, 236, 0, // Skip to: 86948 /* 26355 */ MCD_OPC_Decode, 165, 13, 132, 1, // Opcode: GLD1W_D_IMM_REAL /* 26360 */ MCD_OPC_FilterValue, 7, 167, 236, 0, // Skip to: 86948 /* 26365 */ MCD_OPC_CheckPredicate, 0, 162, 236, 0, // Skip to: 86948 /* 26370 */ MCD_OPC_Decode, 229, 13, 132, 1, // Opcode: GLDFF1W_D_IMM_REAL /* 26375 */ MCD_OPC_FilterValue, 10, 115, 0, 0, // Skip to: 26495 /* 26380 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26383 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26397 /* 26388 */ MCD_OPC_CheckPredicate, 0, 139, 236, 0, // Skip to: 86948 /* 26393 */ MCD_OPC_Decode, 161, 13, 127, // Opcode: GLD1SW_D_SXTW_REAL /* 26397 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26411 /* 26402 */ MCD_OPC_CheckPredicate, 0, 125, 236, 0, // Skip to: 86948 /* 26407 */ MCD_OPC_Decode, 225, 13, 127, // Opcode: GLDFF1SW_D_SXTW_REAL /* 26411 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26425 /* 26416 */ MCD_OPC_CheckPredicate, 0, 111, 236, 0, // Skip to: 86948 /* 26421 */ MCD_OPC_Decode, 168, 13, 127, // Opcode: GLD1W_D_SXTW_REAL /* 26425 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26439 /* 26430 */ MCD_OPC_CheckPredicate, 0, 97, 236, 0, // Skip to: 86948 /* 26435 */ MCD_OPC_Decode, 232, 13, 127, // Opcode: GLDFF1W_D_SXTW_REAL /* 26439 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26453 /* 26444 */ MCD_OPC_CheckPredicate, 0, 83, 236, 0, // Skip to: 86948 /* 26449 */ MCD_OPC_Decode, 159, 13, 127, // Opcode: GLD1SW_D_REAL /* 26453 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26467 /* 26458 */ MCD_OPC_CheckPredicate, 0, 69, 236, 0, // Skip to: 86948 /* 26463 */ MCD_OPC_Decode, 223, 13, 127, // Opcode: GLDFF1SW_D_REAL /* 26467 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26481 /* 26472 */ MCD_OPC_CheckPredicate, 0, 55, 236, 0, // Skip to: 86948 /* 26477 */ MCD_OPC_Decode, 166, 13, 127, // Opcode: GLD1W_D_REAL /* 26481 */ MCD_OPC_FilterValue, 7, 46, 236, 0, // Skip to: 86948 /* 26486 */ MCD_OPC_CheckPredicate, 0, 41, 236, 0, // Skip to: 86948 /* 26491 */ MCD_OPC_Decode, 230, 13, 127, // Opcode: GLDFF1W_D_REAL /* 26495 */ MCD_OPC_FilterValue, 11, 115, 0, 0, // Skip to: 26615 /* 26500 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26503 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26517 /* 26508 */ MCD_OPC_CheckPredicate, 0, 19, 236, 0, // Skip to: 86948 /* 26513 */ MCD_OPC_Decode, 162, 13, 127, // Opcode: GLD1SW_D_SXTW_SCALED_REAL /* 26517 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26531 /* 26522 */ MCD_OPC_CheckPredicate, 0, 5, 236, 0, // Skip to: 86948 /* 26527 */ MCD_OPC_Decode, 226, 13, 127, // Opcode: GLDFF1SW_D_SXTW_SCALED_REAL /* 26531 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26545 /* 26536 */ MCD_OPC_CheckPredicate, 0, 247, 235, 0, // Skip to: 86948 /* 26541 */ MCD_OPC_Decode, 169, 13, 127, // Opcode: GLD1W_D_SXTW_SCALED_REAL /* 26545 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26559 /* 26550 */ MCD_OPC_CheckPredicate, 0, 233, 235, 0, // Skip to: 86948 /* 26555 */ MCD_OPC_Decode, 233, 13, 127, // Opcode: GLDFF1W_D_SXTW_SCALED_REAL /* 26559 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26573 /* 26564 */ MCD_OPC_CheckPredicate, 0, 219, 235, 0, // Skip to: 86948 /* 26569 */ MCD_OPC_Decode, 160, 13, 127, // Opcode: GLD1SW_D_SCALED_REAL /* 26573 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26587 /* 26578 */ MCD_OPC_CheckPredicate, 0, 205, 235, 0, // Skip to: 86948 /* 26583 */ MCD_OPC_Decode, 224, 13, 127, // Opcode: GLDFF1SW_D_SCALED_REAL /* 26587 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26601 /* 26592 */ MCD_OPC_CheckPredicate, 0, 191, 235, 0, // Skip to: 86948 /* 26597 */ MCD_OPC_Decode, 167, 13, 127, // Opcode: GLD1W_D_SCALED_REAL /* 26601 */ MCD_OPC_FilterValue, 7, 182, 235, 0, // Skip to: 86948 /* 26606 */ MCD_OPC_CheckPredicate, 0, 177, 235, 0, // Skip to: 86948 /* 26611 */ MCD_OPC_Decode, 231, 13, 127, // Opcode: GLDFF1W_D_SCALED_REAL /* 26615 */ MCD_OPC_FilterValue, 12, 53, 0, 0, // Skip to: 26673 /* 26620 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26623 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26637 /* 26628 */ MCD_OPC_CheckPredicate, 0, 155, 235, 0, // Skip to: 86948 /* 26633 */ MCD_OPC_Decode, 253, 12, 127, // Opcode: GLD1D_UXTW_REAL /* 26637 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26651 /* 26642 */ MCD_OPC_CheckPredicate, 0, 141, 235, 0, // Skip to: 86948 /* 26647 */ MCD_OPC_Decode, 189, 13, 127, // Opcode: GLDFF1D_UXTW_REAL /* 26651 */ MCD_OPC_FilterValue, 7, 132, 235, 0, // Skip to: 86948 /* 26656 */ MCD_OPC_CheckPredicate, 0, 127, 235, 0, // Skip to: 86948 /* 26661 */ MCD_OPC_CheckField, 4, 1, 0, 120, 235, 0, // Skip to: 86948 /* 26668 */ MCD_OPC_Decode, 134, 21, 135, 1, // Opcode: PRFD_D_PZI /* 26673 */ MCD_OPC_FilterValue, 13, 61, 0, 0, // Skip to: 26739 /* 26678 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26681 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26695 /* 26686 */ MCD_OPC_CheckPredicate, 0, 97, 235, 0, // Skip to: 86948 /* 26691 */ MCD_OPC_Decode, 254, 12, 127, // Opcode: GLD1D_UXTW_SCALED_REAL /* 26695 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26709 /* 26700 */ MCD_OPC_CheckPredicate, 0, 83, 235, 0, // Skip to: 86948 /* 26705 */ MCD_OPC_Decode, 190, 13, 127, // Opcode: GLDFF1D_UXTW_SCALED_REAL /* 26709 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 26724 /* 26714 */ MCD_OPC_CheckPredicate, 0, 69, 235, 0, // Skip to: 86948 /* 26719 */ MCD_OPC_Decode, 248, 12, 132, 1, // Opcode: GLD1D_IMM_REAL /* 26724 */ MCD_OPC_FilterValue, 7, 59, 235, 0, // Skip to: 86948 /* 26729 */ MCD_OPC_CheckPredicate, 0, 54, 235, 0, // Skip to: 86948 /* 26734 */ MCD_OPC_Decode, 184, 13, 132, 1, // Opcode: GLDFF1D_IMM_REAL /* 26739 */ MCD_OPC_FilterValue, 14, 59, 0, 0, // Skip to: 26803 /* 26744 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26747 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26761 /* 26752 */ MCD_OPC_CheckPredicate, 0, 31, 235, 0, // Skip to: 86948 /* 26757 */ MCD_OPC_Decode, 251, 12, 127, // Opcode: GLD1D_SXTW_REAL /* 26761 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26775 /* 26766 */ MCD_OPC_CheckPredicate, 0, 17, 235, 0, // Skip to: 86948 /* 26771 */ MCD_OPC_Decode, 187, 13, 127, // Opcode: GLDFF1D_SXTW_REAL /* 26775 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26789 /* 26780 */ MCD_OPC_CheckPredicate, 0, 3, 235, 0, // Skip to: 86948 /* 26785 */ MCD_OPC_Decode, 249, 12, 127, // Opcode: GLD1D_REAL /* 26789 */ MCD_OPC_FilterValue, 7, 250, 234, 0, // Skip to: 86948 /* 26794 */ MCD_OPC_CheckPredicate, 0, 245, 234, 0, // Skip to: 86948 /* 26799 */ MCD_OPC_Decode, 185, 13, 127, // Opcode: GLDFF1D_REAL /* 26803 */ MCD_OPC_FilterValue, 15, 236, 234, 0, // Skip to: 86948 /* 26808 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26811 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26825 /* 26816 */ MCD_OPC_CheckPredicate, 0, 223, 234, 0, // Skip to: 86948 /* 26821 */ MCD_OPC_Decode, 252, 12, 127, // Opcode: GLD1D_SXTW_SCALED_REAL /* 26825 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26839 /* 26830 */ MCD_OPC_CheckPredicate, 0, 209, 234, 0, // Skip to: 86948 /* 26835 */ MCD_OPC_Decode, 188, 13, 127, // Opcode: GLDFF1D_SXTW_SCALED_REAL /* 26839 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26853 /* 26844 */ MCD_OPC_CheckPredicate, 0, 195, 234, 0, // Skip to: 86948 /* 26849 */ MCD_OPC_Decode, 250, 12, 127, // Opcode: GLD1D_SCALED_REAL /* 26853 */ MCD_OPC_FilterValue, 7, 186, 234, 0, // Skip to: 86948 /* 26858 */ MCD_OPC_CheckPredicate, 0, 181, 234, 0, // Skip to: 86948 /* 26863 */ MCD_OPC_Decode, 186, 13, 127, // Opcode: GLDFF1D_SCALED_REAL /* 26867 */ MCD_OPC_FilterValue, 7, 172, 234, 0, // Skip to: 86948 /* 26872 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 26875 */ MCD_OPC_FilterValue, 0, 210, 0, 0, // Skip to: 27090 /* 26880 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 26883 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 26921 /* 26888 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 26891 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26906 /* 26896 */ MCD_OPC_CheckPredicate, 0, 143, 234, 0, // Skip to: 86948 /* 26901 */ MCD_OPC_Decode, 173, 27, 136, 1, // Opcode: ST1B /* 26906 */ MCD_OPC_FilterValue, 1, 133, 234, 0, // Skip to: 86948 /* 26911 */ MCD_OPC_CheckPredicate, 0, 128, 234, 0, // Skip to: 86948 /* 26916 */ MCD_OPC_Decode, 176, 27, 136, 1, // Opcode: ST1B_H /* 26921 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 26959 /* 26926 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 26929 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26944 /* 26934 */ MCD_OPC_CheckPredicate, 0, 105, 234, 0, // Skip to: 86948 /* 26939 */ MCD_OPC_Decode, 251, 28, 136, 1, // Opcode: STNT1B_ZRR /* 26944 */ MCD_OPC_FilterValue, 1, 95, 234, 0, // Skip to: 86948 /* 26949 */ MCD_OPC_CheckPredicate, 0, 90, 234, 0, // Skip to: 86948 /* 26954 */ MCD_OPC_Decode, 137, 28, 139, 1, // Opcode: ST2B /* 26959 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 26980 /* 26964 */ MCD_OPC_CheckPredicate, 0, 75, 234, 0, // Skip to: 86948 /* 26969 */ MCD_OPC_CheckField, 21, 1, 0, 68, 234, 0, // Skip to: 86948 /* 26976 */ MCD_OPC_Decode, 254, 26, 127, // Opcode: SST1B_D_UXTW /* 26980 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 27001 /* 26985 */ MCD_OPC_CheckPredicate, 0, 54, 234, 0, // Skip to: 86948 /* 26990 */ MCD_OPC_CheckField, 21, 1, 0, 47, 234, 0, // Skip to: 86948 /* 26997 */ MCD_OPC_Decode, 251, 26, 127, // Opcode: SST1B_D /* 27001 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 27022 /* 27006 */ MCD_OPC_CheckPredicate, 0, 33, 234, 0, // Skip to: 86948 /* 27011 */ MCD_OPC_CheckField, 21, 1, 0, 26, 234, 0, // Skip to: 86948 /* 27018 */ MCD_OPC_Decode, 253, 26, 127, // Opcode: SST1B_D_SXTW /* 27022 */ MCD_OPC_FilterValue, 7, 17, 234, 0, // Skip to: 86948 /* 27027 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 27030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27045 /* 27035 */ MCD_OPC_CheckPredicate, 0, 4, 234, 0, // Skip to: 86948 /* 27040 */ MCD_OPC_Decode, 178, 27, 137, 1, // Opcode: ST1B_IMM /* 27045 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27060 /* 27050 */ MCD_OPC_CheckPredicate, 0, 245, 233, 0, // Skip to: 86948 /* 27055 */ MCD_OPC_Decode, 250, 28, 137, 1, // Opcode: STNT1B_ZRI /* 27060 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27075 /* 27065 */ MCD_OPC_CheckPredicate, 0, 230, 233, 0, // Skip to: 86948 /* 27070 */ MCD_OPC_Decode, 177, 27, 137, 1, // Opcode: ST1B_H_IMM /* 27075 */ MCD_OPC_FilterValue, 3, 220, 233, 0, // Skip to: 86948 /* 27080 */ MCD_OPC_CheckPredicate, 0, 215, 233, 0, // Skip to: 86948 /* 27085 */ MCD_OPC_Decode, 138, 28, 140, 1, // Opcode: ST2B_IMM /* 27090 */ MCD_OPC_FilterValue, 1, 227, 0, 0, // Skip to: 27322 /* 27095 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 27098 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 27136 /* 27103 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27121 /* 27111 */ MCD_OPC_CheckPredicate, 0, 184, 233, 0, // Skip to: 86948 /* 27116 */ MCD_OPC_Decode, 179, 27, 136, 1, // Opcode: ST1B_S /* 27121 */ MCD_OPC_FilterValue, 1, 174, 233, 0, // Skip to: 86948 /* 27126 */ MCD_OPC_CheckPredicate, 0, 169, 233, 0, // Skip to: 86948 /* 27131 */ MCD_OPC_Decode, 174, 27, 136, 1, // Opcode: ST1B_D /* 27136 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27174 /* 27141 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27144 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27159 /* 27149 */ MCD_OPC_CheckPredicate, 0, 146, 233, 0, // Skip to: 86948 /* 27154 */ MCD_OPC_Decode, 167, 28, 141, 1, // Opcode: ST3B /* 27159 */ MCD_OPC_FilterValue, 1, 136, 233, 0, // Skip to: 86948 /* 27164 */ MCD_OPC_CheckPredicate, 0, 131, 233, 0, // Skip to: 86948 /* 27169 */ MCD_OPC_Decode, 197, 28, 143, 1, // Opcode: ST4B /* 27174 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 27195 /* 27179 */ MCD_OPC_CheckPredicate, 0, 116, 233, 0, // Skip to: 86948 /* 27184 */ MCD_OPC_CheckField, 21, 1, 0, 109, 233, 0, // Skip to: 86948 /* 27191 */ MCD_OPC_Decode, 129, 27, 127, // Opcode: SST1B_S_UXTW /* 27195 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 27233 /* 27200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27203 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27218 /* 27208 */ MCD_OPC_CheckPredicate, 0, 87, 233, 0, // Skip to: 86948 /* 27213 */ MCD_OPC_Decode, 252, 26, 132, 1, // Opcode: SST1B_D_IMM /* 27218 */ MCD_OPC_FilterValue, 1, 77, 233, 0, // Skip to: 86948 /* 27223 */ MCD_OPC_CheckPredicate, 0, 72, 233, 0, // Skip to: 86948 /* 27228 */ MCD_OPC_Decode, 255, 26, 132, 1, // Opcode: SST1B_S_IMM /* 27233 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 27254 /* 27238 */ MCD_OPC_CheckPredicate, 0, 57, 233, 0, // Skip to: 86948 /* 27243 */ MCD_OPC_CheckField, 21, 1, 0, 50, 233, 0, // Skip to: 86948 /* 27250 */ MCD_OPC_Decode, 128, 27, 127, // Opcode: SST1B_S_SXTW /* 27254 */ MCD_OPC_FilterValue, 7, 41, 233, 0, // Skip to: 86948 /* 27259 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 27262 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27277 /* 27267 */ MCD_OPC_CheckPredicate, 0, 28, 233, 0, // Skip to: 86948 /* 27272 */ MCD_OPC_Decode, 180, 27, 137, 1, // Opcode: ST1B_S_IMM /* 27277 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27292 /* 27282 */ MCD_OPC_CheckPredicate, 0, 13, 233, 0, // Skip to: 86948 /* 27287 */ MCD_OPC_Decode, 168, 28, 142, 1, // Opcode: ST3B_IMM /* 27292 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27307 /* 27297 */ MCD_OPC_CheckPredicate, 0, 254, 232, 0, // Skip to: 86948 /* 27302 */ MCD_OPC_Decode, 175, 27, 137, 1, // Opcode: ST1B_D_IMM /* 27307 */ MCD_OPC_FilterValue, 3, 244, 232, 0, // Skip to: 86948 /* 27312 */ MCD_OPC_CheckPredicate, 0, 239, 232, 0, // Skip to: 86948 /* 27317 */ MCD_OPC_Decode, 198, 28, 144, 1, // Opcode: ST4B_IMM /* 27322 */ MCD_OPC_FilterValue, 2, 224, 0, 0, // Skip to: 27551 /* 27327 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 27330 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 27352 /* 27335 */ MCD_OPC_CheckPredicate, 0, 216, 232, 0, // Skip to: 86948 /* 27340 */ MCD_OPC_CheckField, 21, 1, 1, 209, 232, 0, // Skip to: 86948 /* 27347 */ MCD_OPC_Decode, 199, 27, 136, 1, // Opcode: ST1H /* 27352 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27390 /* 27357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27375 /* 27365 */ MCD_OPC_CheckPredicate, 0, 186, 232, 0, // Skip to: 86948 /* 27370 */ MCD_OPC_Decode, 255, 28, 136, 1, // Opcode: STNT1H_ZRR /* 27375 */ MCD_OPC_FilterValue, 1, 176, 232, 0, // Skip to: 86948 /* 27380 */ MCD_OPC_CheckPredicate, 0, 171, 232, 0, // Skip to: 86948 /* 27385 */ MCD_OPC_Decode, 141, 28, 139, 1, // Opcode: ST2H /* 27390 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27426 /* 27395 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27398 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27412 /* 27403 */ MCD_OPC_CheckPredicate, 0, 148, 232, 0, // Skip to: 86948 /* 27408 */ MCD_OPC_Decode, 142, 27, 127, // Opcode: SST1H_D_UXTW /* 27412 */ MCD_OPC_FilterValue, 1, 139, 232, 0, // Skip to: 86948 /* 27417 */ MCD_OPC_CheckPredicate, 0, 134, 232, 0, // Skip to: 86948 /* 27422 */ MCD_OPC_Decode, 143, 27, 127, // Opcode: SST1H_D_UXTW_SCALED /* 27426 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 27462 /* 27431 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27434 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27448 /* 27439 */ MCD_OPC_CheckPredicate, 0, 112, 232, 0, // Skip to: 86948 /* 27444 */ MCD_OPC_Decode, 137, 27, 127, // Opcode: SST1H_D /* 27448 */ MCD_OPC_FilterValue, 1, 103, 232, 0, // Skip to: 86948 /* 27453 */ MCD_OPC_CheckPredicate, 0, 98, 232, 0, // Skip to: 86948 /* 27458 */ MCD_OPC_Decode, 139, 27, 127, // Opcode: SST1H_D_SCALED /* 27462 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27498 /* 27467 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27484 /* 27475 */ MCD_OPC_CheckPredicate, 0, 76, 232, 0, // Skip to: 86948 /* 27480 */ MCD_OPC_Decode, 140, 27, 127, // Opcode: SST1H_D_SXTW /* 27484 */ MCD_OPC_FilterValue, 1, 67, 232, 0, // Skip to: 86948 /* 27489 */ MCD_OPC_CheckPredicate, 0, 62, 232, 0, // Skip to: 86948 /* 27494 */ MCD_OPC_Decode, 141, 27, 127, // Opcode: SST1H_D_SXTW_SCALED /* 27498 */ MCD_OPC_FilterValue, 7, 53, 232, 0, // Skip to: 86948 /* 27503 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 27506 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27521 /* 27511 */ MCD_OPC_CheckPredicate, 0, 40, 232, 0, // Skip to: 86948 /* 27516 */ MCD_OPC_Decode, 254, 28, 137, 1, // Opcode: STNT1H_ZRI /* 27521 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27536 /* 27526 */ MCD_OPC_CheckPredicate, 0, 25, 232, 0, // Skip to: 86948 /* 27531 */ MCD_OPC_Decode, 202, 27, 137, 1, // Opcode: ST1H_IMM /* 27536 */ MCD_OPC_FilterValue, 3, 15, 232, 0, // Skip to: 86948 /* 27541 */ MCD_OPC_CheckPredicate, 0, 10, 232, 0, // Skip to: 86948 /* 27546 */ MCD_OPC_Decode, 142, 28, 140, 1, // Opcode: ST2H_IMM /* 27551 */ MCD_OPC_FilterValue, 3, 1, 1, 0, // Skip to: 27813 /* 27556 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 27559 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 27597 /* 27564 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27567 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27582 /* 27572 */ MCD_OPC_CheckPredicate, 0, 235, 231, 0, // Skip to: 86948 /* 27577 */ MCD_OPC_Decode, 203, 27, 136, 1, // Opcode: ST1H_S /* 27582 */ MCD_OPC_FilterValue, 1, 225, 231, 0, // Skip to: 86948 /* 27587 */ MCD_OPC_CheckPredicate, 0, 220, 231, 0, // Skip to: 86948 /* 27592 */ MCD_OPC_Decode, 200, 27, 136, 1, // Opcode: ST1H_D /* 27597 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27635 /* 27602 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27605 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27620 /* 27610 */ MCD_OPC_CheckPredicate, 0, 197, 231, 0, // Skip to: 86948 /* 27615 */ MCD_OPC_Decode, 171, 28, 141, 1, // Opcode: ST3H /* 27620 */ MCD_OPC_FilterValue, 1, 187, 231, 0, // Skip to: 86948 /* 27625 */ MCD_OPC_CheckPredicate, 0, 182, 231, 0, // Skip to: 86948 /* 27630 */ MCD_OPC_Decode, 215, 28, 143, 1, // Opcode: ST4H /* 27635 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27671 /* 27640 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27643 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27657 /* 27648 */ MCD_OPC_CheckPredicate, 0, 159, 231, 0, // Skip to: 86948 /* 27653 */ MCD_OPC_Decode, 147, 27, 127, // Opcode: SST1H_S_UXTW /* 27657 */ MCD_OPC_FilterValue, 1, 150, 231, 0, // Skip to: 86948 /* 27662 */ MCD_OPC_CheckPredicate, 0, 145, 231, 0, // Skip to: 86948 /* 27667 */ MCD_OPC_Decode, 148, 27, 127, // Opcode: SST1H_S_UXTW_SCALED /* 27671 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 27709 /* 27676 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27679 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27694 /* 27684 */ MCD_OPC_CheckPredicate, 0, 123, 231, 0, // Skip to: 86948 /* 27689 */ MCD_OPC_Decode, 138, 27, 132, 1, // Opcode: SST1H_D_IMM /* 27694 */ MCD_OPC_FilterValue, 1, 113, 231, 0, // Skip to: 86948 /* 27699 */ MCD_OPC_CheckPredicate, 0, 108, 231, 0, // Skip to: 86948 /* 27704 */ MCD_OPC_Decode, 144, 27, 132, 1, // Opcode: SST1H_S_IMM /* 27709 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27745 /* 27714 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27717 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27731 /* 27722 */ MCD_OPC_CheckPredicate, 0, 85, 231, 0, // Skip to: 86948 /* 27727 */ MCD_OPC_Decode, 145, 27, 127, // Opcode: SST1H_S_SXTW /* 27731 */ MCD_OPC_FilterValue, 1, 76, 231, 0, // Skip to: 86948 /* 27736 */ MCD_OPC_CheckPredicate, 0, 71, 231, 0, // Skip to: 86948 /* 27741 */ MCD_OPC_Decode, 146, 27, 127, // Opcode: SST1H_S_SXTW_SCALED /* 27745 */ MCD_OPC_FilterValue, 7, 62, 231, 0, // Skip to: 86948 /* 27750 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 27753 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27768 /* 27758 */ MCD_OPC_CheckPredicate, 0, 49, 231, 0, // Skip to: 86948 /* 27763 */ MCD_OPC_Decode, 204, 27, 137, 1, // Opcode: ST1H_S_IMM /* 27768 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27783 /* 27773 */ MCD_OPC_CheckPredicate, 0, 34, 231, 0, // Skip to: 86948 /* 27778 */ MCD_OPC_Decode, 172, 28, 142, 1, // Opcode: ST3H_IMM /* 27783 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27798 /* 27788 */ MCD_OPC_CheckPredicate, 0, 19, 231, 0, // Skip to: 86948 /* 27793 */ MCD_OPC_Decode, 201, 27, 137, 1, // Opcode: ST1H_D_IMM /* 27798 */ MCD_OPC_FilterValue, 3, 9, 231, 0, // Skip to: 86948 /* 27803 */ MCD_OPC_CheckPredicate, 0, 4, 231, 0, // Skip to: 86948 /* 27808 */ MCD_OPC_Decode, 216, 28, 144, 1, // Opcode: ST4H_IMM /* 27813 */ MCD_OPC_FilterValue, 4, 187, 0, 0, // Skip to: 28005 /* 27818 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 27821 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27859 /* 27826 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27829 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27844 /* 27834 */ MCD_OPC_CheckPredicate, 0, 229, 230, 0, // Skip to: 86948 /* 27839 */ MCD_OPC_Decode, 129, 29, 136, 1, // Opcode: STNT1W_ZRR /* 27844 */ MCD_OPC_FilterValue, 1, 219, 230, 0, // Skip to: 86948 /* 27849 */ MCD_OPC_CheckPredicate, 0, 214, 230, 0, // Skip to: 86948 /* 27854 */ MCD_OPC_Decode, 157, 28, 139, 1, // Opcode: ST2W /* 27859 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27895 /* 27864 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27867 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27881 /* 27872 */ MCD_OPC_CheckPredicate, 0, 191, 230, 0, // Skip to: 86948 /* 27877 */ MCD_OPC_Decode, 154, 27, 127, // Opcode: SST1W_D_UXTW /* 27881 */ MCD_OPC_FilterValue, 1, 182, 230, 0, // Skip to: 86948 /* 27886 */ MCD_OPC_CheckPredicate, 0, 177, 230, 0, // Skip to: 86948 /* 27891 */ MCD_OPC_Decode, 155, 27, 127, // Opcode: SST1W_D_UXTW_SCALED /* 27895 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 27931 /* 27900 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27903 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27917 /* 27908 */ MCD_OPC_CheckPredicate, 0, 155, 230, 0, // Skip to: 86948 /* 27913 */ MCD_OPC_Decode, 149, 27, 127, // Opcode: SST1W_D /* 27917 */ MCD_OPC_FilterValue, 1, 146, 230, 0, // Skip to: 86948 /* 27922 */ MCD_OPC_CheckPredicate, 0, 141, 230, 0, // Skip to: 86948 /* 27927 */ MCD_OPC_Decode, 151, 27, 127, // Opcode: SST1W_D_SCALED /* 27931 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27967 /* 27936 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 27939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27953 /* 27944 */ MCD_OPC_CheckPredicate, 0, 119, 230, 0, // Skip to: 86948 /* 27949 */ MCD_OPC_Decode, 152, 27, 127, // Opcode: SST1W_D_SXTW /* 27953 */ MCD_OPC_FilterValue, 1, 110, 230, 0, // Skip to: 86948 /* 27958 */ MCD_OPC_CheckPredicate, 0, 105, 230, 0, // Skip to: 86948 /* 27963 */ MCD_OPC_Decode, 153, 27, 127, // Opcode: SST1W_D_SXTW_SCALED /* 27967 */ MCD_OPC_FilterValue, 7, 96, 230, 0, // Skip to: 86948 /* 27972 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 27975 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27990 /* 27980 */ MCD_OPC_CheckPredicate, 0, 83, 230, 0, // Skip to: 86948 /* 27985 */ MCD_OPC_Decode, 128, 29, 137, 1, // Opcode: STNT1W_ZRI /* 27990 */ MCD_OPC_FilterValue, 3, 73, 230, 0, // Skip to: 86948 /* 27995 */ MCD_OPC_CheckPredicate, 0, 68, 230, 0, // Skip to: 86948 /* 28000 */ MCD_OPC_Decode, 158, 28, 140, 1, // Opcode: ST2W_IMM /* 28005 */ MCD_OPC_FilterValue, 5, 1, 1, 0, // Skip to: 28267 /* 28010 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 28013 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 28051 /* 28018 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28021 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28036 /* 28026 */ MCD_OPC_CheckPredicate, 0, 37, 230, 0, // Skip to: 86948 /* 28031 */ MCD_OPC_Decode, 253, 27, 136, 1, // Opcode: ST1W /* 28036 */ MCD_OPC_FilterValue, 1, 27, 230, 0, // Skip to: 86948 /* 28041 */ MCD_OPC_CheckPredicate, 0, 22, 230, 0, // Skip to: 86948 /* 28046 */ MCD_OPC_Decode, 254, 27, 136, 1, // Opcode: ST1W_D /* 28051 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28089 /* 28056 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28059 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28074 /* 28064 */ MCD_OPC_CheckPredicate, 0, 255, 229, 0, // Skip to: 86948 /* 28069 */ MCD_OPC_Decode, 187, 28, 141, 1, // Opcode: ST3W /* 28074 */ MCD_OPC_FilterValue, 1, 245, 229, 0, // Skip to: 86948 /* 28079 */ MCD_OPC_CheckPredicate, 0, 240, 229, 0, // Skip to: 86948 /* 28084 */ MCD_OPC_Decode, 217, 28, 143, 1, // Opcode: ST4W /* 28089 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 28125 /* 28094 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28097 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28111 /* 28102 */ MCD_OPC_CheckPredicate, 0, 217, 229, 0, // Skip to: 86948 /* 28107 */ MCD_OPC_Decode, 159, 27, 127, // Opcode: SST1W_UXTW /* 28111 */ MCD_OPC_FilterValue, 1, 208, 229, 0, // Skip to: 86948 /* 28116 */ MCD_OPC_CheckPredicate, 0, 203, 229, 0, // Skip to: 86948 /* 28121 */ MCD_OPC_Decode, 160, 27, 127, // Opcode: SST1W_UXTW_SCALED /* 28125 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 28163 /* 28130 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28133 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28148 /* 28138 */ MCD_OPC_CheckPredicate, 0, 181, 229, 0, // Skip to: 86948 /* 28143 */ MCD_OPC_Decode, 150, 27, 132, 1, // Opcode: SST1W_D_IMM /* 28148 */ MCD_OPC_FilterValue, 1, 171, 229, 0, // Skip to: 86948 /* 28153 */ MCD_OPC_CheckPredicate, 0, 166, 229, 0, // Skip to: 86948 /* 28158 */ MCD_OPC_Decode, 156, 27, 132, 1, // Opcode: SST1W_IMM /* 28163 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 28199 /* 28168 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28185 /* 28176 */ MCD_OPC_CheckPredicate, 0, 143, 229, 0, // Skip to: 86948 /* 28181 */ MCD_OPC_Decode, 157, 27, 127, // Opcode: SST1W_SXTW /* 28185 */ MCD_OPC_FilterValue, 1, 134, 229, 0, // Skip to: 86948 /* 28190 */ MCD_OPC_CheckPredicate, 0, 129, 229, 0, // Skip to: 86948 /* 28195 */ MCD_OPC_Decode, 158, 27, 127, // Opcode: SST1W_SXTW_SCALED /* 28199 */ MCD_OPC_FilterValue, 7, 120, 229, 0, // Skip to: 86948 /* 28204 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 28207 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28222 /* 28212 */ MCD_OPC_CheckPredicate, 0, 107, 229, 0, // Skip to: 86948 /* 28217 */ MCD_OPC_Decode, 128, 28, 137, 1, // Opcode: ST1W_IMM /* 28222 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28237 /* 28227 */ MCD_OPC_CheckPredicate, 0, 92, 229, 0, // Skip to: 86948 /* 28232 */ MCD_OPC_Decode, 188, 28, 142, 1, // Opcode: ST3W_IMM /* 28237 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28252 /* 28242 */ MCD_OPC_CheckPredicate, 0, 77, 229, 0, // Skip to: 86948 /* 28247 */ MCD_OPC_Decode, 255, 27, 137, 1, // Opcode: ST1W_D_IMM /* 28252 */ MCD_OPC_FilterValue, 3, 67, 229, 0, // Skip to: 86948 /* 28257 */ MCD_OPC_CheckPredicate, 0, 62, 229, 0, // Skip to: 86948 /* 28262 */ MCD_OPC_Decode, 218, 28, 144, 1, // Opcode: ST4W_IMM /* 28267 */ MCD_OPC_FilterValue, 6, 224, 0, 0, // Skip to: 28496 /* 28272 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 28275 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 28297 /* 28280 */ MCD_OPC_CheckPredicate, 0, 39, 229, 0, // Skip to: 86948 /* 28285 */ MCD_OPC_CheckField, 4, 1, 0, 32, 229, 0, // Skip to: 86948 /* 28292 */ MCD_OPC_Decode, 190, 29, 129, 1, // Opcode: STR_PXI /* 28297 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28312 /* 28302 */ MCD_OPC_CheckPredicate, 0, 17, 229, 0, // Skip to: 86948 /* 28307 */ MCD_OPC_Decode, 191, 29, 131, 1, // Opcode: STR_ZXI /* 28312 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28350 /* 28317 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28320 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28335 /* 28325 */ MCD_OPC_CheckPredicate, 0, 250, 228, 0, // Skip to: 86948 /* 28330 */ MCD_OPC_Decode, 253, 28, 136, 1, // Opcode: STNT1D_ZRR /* 28335 */ MCD_OPC_FilterValue, 1, 240, 228, 0, // Skip to: 86948 /* 28340 */ MCD_OPC_CheckPredicate, 0, 235, 228, 0, // Skip to: 86948 /* 28345 */ MCD_OPC_Decode, 139, 28, 139, 1, // Opcode: ST2D /* 28350 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 28386 /* 28355 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28358 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28372 /* 28363 */ MCD_OPC_CheckPredicate, 0, 212, 228, 0, // Skip to: 86948 /* 28368 */ MCD_OPC_Decode, 135, 27, 127, // Opcode: SST1D_UXTW /* 28372 */ MCD_OPC_FilterValue, 1, 203, 228, 0, // Skip to: 86948 /* 28377 */ MCD_OPC_CheckPredicate, 0, 198, 228, 0, // Skip to: 86948 /* 28382 */ MCD_OPC_Decode, 136, 27, 127, // Opcode: SST1D_UXTW_SCALED /* 28386 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 28422 /* 28391 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28408 /* 28399 */ MCD_OPC_CheckPredicate, 0, 176, 228, 0, // Skip to: 86948 /* 28404 */ MCD_OPC_Decode, 130, 27, 127, // Opcode: SST1D /* 28408 */ MCD_OPC_FilterValue, 1, 167, 228, 0, // Skip to: 86948 /* 28413 */ MCD_OPC_CheckPredicate, 0, 162, 228, 0, // Skip to: 86948 /* 28418 */ MCD_OPC_Decode, 132, 27, 127, // Opcode: SST1D_SCALED /* 28422 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 28458 /* 28427 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28430 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28444 /* 28435 */ MCD_OPC_CheckPredicate, 0, 140, 228, 0, // Skip to: 86948 /* 28440 */ MCD_OPC_Decode, 133, 27, 127, // Opcode: SST1D_SXTW /* 28444 */ MCD_OPC_FilterValue, 1, 131, 228, 0, // Skip to: 86948 /* 28449 */ MCD_OPC_CheckPredicate, 0, 126, 228, 0, // Skip to: 86948 /* 28454 */ MCD_OPC_Decode, 134, 27, 127, // Opcode: SST1D_SXTW_SCALED /* 28458 */ MCD_OPC_FilterValue, 7, 117, 228, 0, // Skip to: 86948 /* 28463 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 28466 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28481 /* 28471 */ MCD_OPC_CheckPredicate, 0, 104, 228, 0, // Skip to: 86948 /* 28476 */ MCD_OPC_Decode, 252, 28, 137, 1, // Opcode: STNT1D_ZRI /* 28481 */ MCD_OPC_FilterValue, 3, 94, 228, 0, // Skip to: 86948 /* 28486 */ MCD_OPC_CheckPredicate, 0, 89, 228, 0, // Skip to: 86948 /* 28491 */ MCD_OPC_Decode, 140, 28, 140, 1, // Opcode: ST2D_IMM /* 28496 */ MCD_OPC_FilterValue, 7, 79, 228, 0, // Skip to: 86948 /* 28501 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 28504 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 28526 /* 28509 */ MCD_OPC_CheckPredicate, 0, 66, 228, 0, // Skip to: 86948 /* 28514 */ MCD_OPC_CheckField, 21, 1, 1, 59, 228, 0, // Skip to: 86948 /* 28521 */ MCD_OPC_Decode, 181, 27, 136, 1, // Opcode: ST1D /* 28526 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28564 /* 28531 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28534 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28549 /* 28539 */ MCD_OPC_CheckPredicate, 0, 36, 228, 0, // Skip to: 86948 /* 28544 */ MCD_OPC_Decode, 169, 28, 141, 1, // Opcode: ST3D /* 28549 */ MCD_OPC_FilterValue, 1, 26, 228, 0, // Skip to: 86948 /* 28554 */ MCD_OPC_CheckPredicate, 0, 21, 228, 0, // Skip to: 86948 /* 28559 */ MCD_OPC_Decode, 199, 28, 143, 1, // Opcode: ST4D /* 28564 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 28586 /* 28569 */ MCD_OPC_CheckPredicate, 0, 6, 228, 0, // Skip to: 86948 /* 28574 */ MCD_OPC_CheckField, 21, 1, 0, 255, 227, 0, // Skip to: 86948 /* 28581 */ MCD_OPC_Decode, 131, 27, 132, 1, // Opcode: SST1D_IMM /* 28586 */ MCD_OPC_FilterValue, 7, 245, 227, 0, // Skip to: 86948 /* 28591 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 28594 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28609 /* 28599 */ MCD_OPC_CheckPredicate, 0, 232, 227, 0, // Skip to: 86948 /* 28604 */ MCD_OPC_Decode, 170, 28, 142, 1, // Opcode: ST3D_IMM /* 28609 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28624 /* 28614 */ MCD_OPC_CheckPredicate, 0, 217, 227, 0, // Skip to: 86948 /* 28619 */ MCD_OPC_Decode, 182, 27, 137, 1, // Opcode: ST1D_IMM /* 28624 */ MCD_OPC_FilterValue, 3, 207, 227, 0, // Skip to: 86948 /* 28629 */ MCD_OPC_CheckPredicate, 0, 202, 227, 0, // Skip to: 86948 /* 28634 */ MCD_OPC_Decode, 200, 28, 144, 1, // Opcode: ST4D_IMM /* 28639 */ MCD_OPC_FilterValue, 2, 20, 8, 0, // Skip to: 30712 /* 28644 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 28647 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 29030 /* 28652 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 28655 */ MCD_OPC_FilterValue, 0, 51, 1, 0, // Skip to: 28967 /* 28660 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 28663 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 28691 /* 28668 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 28671 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 28681 /* 28676 */ MCD_OPC_Decode, 207, 29, 145, 1, // Opcode: STXRB /* 28681 */ MCD_OPC_FilterValue, 1, 150, 227, 0, // Skip to: 86948 /* 28686 */ MCD_OPC_Decode, 241, 28, 145, 1, // Opcode: STLXRB /* 28691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 28729 /* 28696 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 28699 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28714 /* 28704 */ MCD_OPC_CheckPredicate, 1, 127, 227, 0, // Skip to: 86948 /* 28709 */ MCD_OPC_Decode, 244, 2, 146, 1, // Opcode: CASPW /* 28714 */ MCD_OPC_FilterValue, 63, 117, 227, 0, // Skip to: 86948 /* 28719 */ MCD_OPC_CheckPredicate, 1, 112, 227, 0, // Skip to: 86948 /* 28724 */ MCD_OPC_Decode, 242, 2, 146, 1, // Opcode: CASPLW /* 28729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 28767 /* 28734 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 28737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28752 /* 28742 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 28747 */ MCD_OPC_Decode, 146, 19, 145, 1, // Opcode: LDXRB /* 28752 */ MCD_OPC_FilterValue, 1, 79, 227, 0, // Skip to: 86948 /* 28757 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 28762 */ MCD_OPC_Decode, 240, 16, 145, 1, // Opcode: LDAXRB /* 28767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28805 /* 28772 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 28775 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28790 /* 28780 */ MCD_OPC_CheckPredicate, 1, 51, 227, 0, // Skip to: 86948 /* 28785 */ MCD_OPC_Decode, 240, 2, 146, 1, // Opcode: CASPAW /* 28790 */ MCD_OPC_FilterValue, 63, 41, 227, 0, // Skip to: 86948 /* 28795 */ MCD_OPC_CheckPredicate, 1, 36, 227, 0, // Skip to: 86948 /* 28800 */ MCD_OPC_Decode, 238, 2, 146, 1, // Opcode: CASPALW /* 28805 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 28848 /* 28810 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 28813 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 28833 /* 28818 */ MCD_OPC_CheckPredicate, 2, 13, 227, 0, // Skip to: 86948 /* 28823 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 28828 */ MCD_OPC_Decode, 227, 28, 145, 1, // Opcode: STLLRB /* 28833 */ MCD_OPC_FilterValue, 1, 254, 226, 0, // Skip to: 86948 /* 28838 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 28843 */ MCD_OPC_Decode, 231, 28, 145, 1, // Opcode: STLRB /* 28848 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 28886 /* 28853 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 28856 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28871 /* 28861 */ MCD_OPC_CheckPredicate, 1, 226, 226, 0, // Skip to: 86948 /* 28866 */ MCD_OPC_Decode, 232, 2, 147, 1, // Opcode: CASB /* 28871 */ MCD_OPC_FilterValue, 63, 216, 226, 0, // Skip to: 86948 /* 28876 */ MCD_OPC_CheckPredicate, 1, 211, 226, 0, // Skip to: 86948 /* 28881 */ MCD_OPC_Decode, 234, 2, 147, 1, // Opcode: CASLB /* 28886 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 28929 /* 28891 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 28894 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 28914 /* 28899 */ MCD_OPC_CheckPredicate, 2, 188, 226, 0, // Skip to: 86948 /* 28904 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 28909 */ MCD_OPC_Decode, 164, 17, 145, 1, // Opcode: LDLARB /* 28914 */ MCD_OPC_FilterValue, 1, 173, 226, 0, // Skip to: 86948 /* 28919 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 28924 */ MCD_OPC_Decode, 234, 16, 145, 1, // Opcode: LDARB /* 28929 */ MCD_OPC_FilterValue, 7, 158, 226, 0, // Skip to: 86948 /* 28934 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 28937 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28952 /* 28942 */ MCD_OPC_CheckPredicate, 1, 145, 226, 0, // Skip to: 86948 /* 28947 */ MCD_OPC_Decode, 224, 2, 147, 1, // Opcode: CASAB /* 28952 */ MCD_OPC_FilterValue, 63, 135, 226, 0, // Skip to: 86948 /* 28957 */ MCD_OPC_CheckPredicate, 1, 130, 226, 0, // Skip to: 86948 /* 28962 */ MCD_OPC_Decode, 226, 2, 147, 1, // Opcode: CASALB /* 28967 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 28995 /* 28972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 28975 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 28985 /* 28980 */ MCD_OPC_Decode, 241, 1, 148, 1, // Opcode: ANDWrs /* 28985 */ MCD_OPC_FilterValue, 1, 102, 226, 0, // Skip to: 86948 /* 28990 */ MCD_OPC_Decode, 178, 2, 148, 1, // Opcode: BICWrs /* 28995 */ MCD_OPC_FilterValue, 3, 92, 226, 0, // Skip to: 86948 /* 29000 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29003 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29013 /* 29008 */ MCD_OPC_Decode, 174, 1, 148, 1, // Opcode: ADDWrs /* 29013 */ MCD_OPC_FilterValue, 1, 74, 226, 0, // Skip to: 86948 /* 29018 */ MCD_OPC_CheckField, 22, 2, 0, 67, 226, 0, // Skip to: 86948 /* 29025 */ MCD_OPC_Decode, 175, 1, 149, 1, // Opcode: ADDWrx /* 29030 */ MCD_OPC_FilterValue, 1, 162, 0, 0, // Skip to: 29197 /* 29035 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 29038 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 29086 /* 29043 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 29046 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29056 /* 29051 */ MCD_OPC_Decode, 248, 28, 150, 1, // Opcode: STNPWi /* 29056 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29066 /* 29061 */ MCD_OPC_Decode, 187, 17, 150, 1, // Opcode: LDNPWi /* 29066 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 29076 /* 29071 */ MCD_OPC_Decode, 140, 29, 150, 1, // Opcode: STPWpost /* 29076 */ MCD_OPC_FilterValue, 3, 11, 226, 0, // Skip to: 86948 /* 29081 */ MCD_OPC_Decode, 210, 17, 150, 1, // Opcode: LDPWpost /* 29086 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 29134 /* 29091 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 29094 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29104 /* 29099 */ MCD_OPC_Decode, 139, 29, 150, 1, // Opcode: STPWi /* 29104 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29114 /* 29109 */ MCD_OPC_Decode, 209, 17, 150, 1, // Opcode: LDPWi /* 29114 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 29124 /* 29119 */ MCD_OPC_Decode, 141, 29, 150, 1, // Opcode: STPWpre /* 29124 */ MCD_OPC_FilterValue, 3, 219, 225, 0, // Skip to: 86948 /* 29129 */ MCD_OPC_Decode, 211, 17, 150, 1, // Opcode: LDPWpre /* 29134 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29162 /* 29139 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29142 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29152 /* 29147 */ MCD_OPC_Decode, 206, 20, 148, 1, // Opcode: ORRWrs /* 29152 */ MCD_OPC_FilterValue, 1, 191, 225, 0, // Skip to: 86948 /* 29157 */ MCD_OPC_Decode, 197, 20, 148, 1, // Opcode: ORNWrs /* 29162 */ MCD_OPC_FilterValue, 3, 181, 225, 0, // Skip to: 86948 /* 29167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29170 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29180 /* 29175 */ MCD_OPC_Decode, 159, 1, 148, 1, // Opcode: ADDSWrs /* 29180 */ MCD_OPC_FilterValue, 1, 163, 225, 0, // Skip to: 86948 /* 29185 */ MCD_OPC_CheckField, 22, 2, 0, 156, 225, 0, // Skip to: 86948 /* 29192 */ MCD_OPC_Decode, 160, 1, 149, 1, // Opcode: ADDSWrx /* 29197 */ MCD_OPC_FilterValue, 2, 122, 1, 0, // Skip to: 29580 /* 29202 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 29205 */ MCD_OPC_FilterValue, 0, 51, 1, 0, // Skip to: 29517 /* 29210 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 29213 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 29241 /* 29218 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29221 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29231 /* 29226 */ MCD_OPC_Decode, 208, 29, 145, 1, // Opcode: STXRH /* 29231 */ MCD_OPC_FilterValue, 1, 112, 225, 0, // Skip to: 86948 /* 29236 */ MCD_OPC_Decode, 242, 28, 145, 1, // Opcode: STLXRH /* 29241 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 29279 /* 29246 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 29249 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29264 /* 29254 */ MCD_OPC_CheckPredicate, 1, 89, 225, 0, // Skip to: 86948 /* 29259 */ MCD_OPC_Decode, 245, 2, 151, 1, // Opcode: CASPX /* 29264 */ MCD_OPC_FilterValue, 63, 79, 225, 0, // Skip to: 86948 /* 29269 */ MCD_OPC_CheckPredicate, 1, 74, 225, 0, // Skip to: 86948 /* 29274 */ MCD_OPC_Decode, 243, 2, 151, 1, // Opcode: CASPLX /* 29279 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 29317 /* 29284 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29287 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 29302 /* 29292 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29297 */ MCD_OPC_Decode, 147, 19, 145, 1, // Opcode: LDXRH /* 29302 */ MCD_OPC_FilterValue, 1, 41, 225, 0, // Skip to: 86948 /* 29307 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29312 */ MCD_OPC_Decode, 241, 16, 145, 1, // Opcode: LDAXRH /* 29317 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 29355 /* 29322 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 29325 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29340 /* 29330 */ MCD_OPC_CheckPredicate, 1, 13, 225, 0, // Skip to: 86948 /* 29335 */ MCD_OPC_Decode, 241, 2, 151, 1, // Opcode: CASPAX /* 29340 */ MCD_OPC_FilterValue, 63, 3, 225, 0, // Skip to: 86948 /* 29345 */ MCD_OPC_CheckPredicate, 1, 254, 224, 0, // Skip to: 86948 /* 29350 */ MCD_OPC_Decode, 239, 2, 151, 1, // Opcode: CASPALX /* 29355 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 29398 /* 29360 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29363 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29383 /* 29368 */ MCD_OPC_CheckPredicate, 2, 231, 224, 0, // Skip to: 86948 /* 29373 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29378 */ MCD_OPC_Decode, 228, 28, 145, 1, // Opcode: STLLRH /* 29383 */ MCD_OPC_FilterValue, 1, 216, 224, 0, // Skip to: 86948 /* 29388 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29393 */ MCD_OPC_Decode, 232, 28, 145, 1, // Opcode: STLRH /* 29398 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 29436 /* 29403 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 29406 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29421 /* 29411 */ MCD_OPC_CheckPredicate, 1, 188, 224, 0, // Skip to: 86948 /* 29416 */ MCD_OPC_Decode, 233, 2, 147, 1, // Opcode: CASH /* 29421 */ MCD_OPC_FilterValue, 63, 178, 224, 0, // Skip to: 86948 /* 29426 */ MCD_OPC_CheckPredicate, 1, 173, 224, 0, // Skip to: 86948 /* 29431 */ MCD_OPC_Decode, 235, 2, 147, 1, // Opcode: CASLH /* 29436 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 29479 /* 29441 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29444 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29464 /* 29449 */ MCD_OPC_CheckPredicate, 2, 150, 224, 0, // Skip to: 86948 /* 29454 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29459 */ MCD_OPC_Decode, 165, 17, 145, 1, // Opcode: LDLARH /* 29464 */ MCD_OPC_FilterValue, 1, 135, 224, 0, // Skip to: 86948 /* 29469 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29474 */ MCD_OPC_Decode, 235, 16, 145, 1, // Opcode: LDARH /* 29479 */ MCD_OPC_FilterValue, 7, 120, 224, 0, // Skip to: 86948 /* 29484 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 29487 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29502 /* 29492 */ MCD_OPC_CheckPredicate, 1, 107, 224, 0, // Skip to: 86948 /* 29497 */ MCD_OPC_Decode, 225, 2, 147, 1, // Opcode: CASAH /* 29502 */ MCD_OPC_FilterValue, 63, 97, 224, 0, // Skip to: 86948 /* 29507 */ MCD_OPC_CheckPredicate, 1, 92, 224, 0, // Skip to: 86948 /* 29512 */ MCD_OPC_Decode, 227, 2, 147, 1, // Opcode: CASALH /* 29517 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29545 /* 29522 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29525 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29535 /* 29530 */ MCD_OPC_Decode, 234, 5, 148, 1, // Opcode: EORWrs /* 29535 */ MCD_OPC_FilterValue, 1, 64, 224, 0, // Skip to: 86948 /* 29540 */ MCD_OPC_Decode, 223, 5, 148, 1, // Opcode: EONWrs /* 29545 */ MCD_OPC_FilterValue, 3, 54, 224, 0, // Skip to: 86948 /* 29550 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29553 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29563 /* 29558 */ MCD_OPC_Decode, 236, 29, 148, 1, // Opcode: SUBWrs /* 29563 */ MCD_OPC_FilterValue, 1, 36, 224, 0, // Skip to: 86948 /* 29568 */ MCD_OPC_CheckField, 22, 2, 0, 29, 224, 0, // Skip to: 86948 /* 29575 */ MCD_OPC_Decode, 237, 29, 149, 1, // Opcode: SUBWrx /* 29580 */ MCD_OPC_FilterValue, 3, 111, 0, 0, // Skip to: 29696 /* 29585 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 29588 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 29605 /* 29593 */ MCD_OPC_CheckField, 22, 2, 3, 4, 224, 0, // Skip to: 86948 /* 29600 */ MCD_OPC_Decode, 204, 17, 150, 1, // Opcode: LDPSWpost /* 29605 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 29633 /* 29610 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 29613 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29623 /* 29618 */ MCD_OPC_Decode, 203, 17, 150, 1, // Opcode: LDPSWi /* 29623 */ MCD_OPC_FilterValue, 3, 232, 223, 0, // Skip to: 86948 /* 29628 */ MCD_OPC_Decode, 205, 17, 150, 1, // Opcode: LDPSWpre /* 29633 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29661 /* 29638 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29641 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29651 /* 29646 */ MCD_OPC_Decode, 230, 1, 148, 1, // Opcode: ANDSWrs /* 29651 */ MCD_OPC_FilterValue, 1, 204, 223, 0, // Skip to: 86948 /* 29656 */ MCD_OPC_Decode, 173, 2, 148, 1, // Opcode: BICSWrs /* 29661 */ MCD_OPC_FilterValue, 3, 194, 223, 0, // Skip to: 86948 /* 29666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 29669 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29679 /* 29674 */ MCD_OPC_Decode, 227, 29, 148, 1, // Opcode: SUBSWrs /* 29679 */ MCD_OPC_FilterValue, 1, 176, 223, 0, // Skip to: 86948 /* 29684 */ MCD_OPC_CheckField, 22, 2, 0, 169, 223, 0, // Skip to: 86948 /* 29691 */ MCD_OPC_Decode, 228, 29, 149, 1, // Opcode: SUBSWrx /* 29696 */ MCD_OPC_FilterValue, 4, 115, 1, 0, // Skip to: 30072 /* 29701 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 29704 */ MCD_OPC_FilterValue, 0, 31, 1, 0, // Skip to: 29996 /* 29709 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 29712 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 29740 /* 29717 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29720 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29730 /* 29725 */ MCD_OPC_Decode, 209, 29, 145, 1, // Opcode: STXRW /* 29730 */ MCD_OPC_FilterValue, 1, 125, 223, 0, // Skip to: 86948 /* 29735 */ MCD_OPC_Decode, 243, 28, 145, 1, // Opcode: STLXRW /* 29740 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 29768 /* 29745 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29748 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29758 /* 29753 */ MCD_OPC_Decode, 205, 29, 145, 1, // Opcode: STXPW /* 29758 */ MCD_OPC_FilterValue, 1, 97, 223, 0, // Skip to: 86948 /* 29763 */ MCD_OPC_Decode, 239, 28, 145, 1, // Opcode: STLXPW /* 29768 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 29806 /* 29773 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 29791 /* 29781 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29786 */ MCD_OPC_Decode, 148, 19, 145, 1, // Opcode: LDXRW /* 29791 */ MCD_OPC_FilterValue, 1, 64, 223, 0, // Skip to: 86948 /* 29796 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29801 */ MCD_OPC_Decode, 242, 16, 145, 1, // Opcode: LDAXRW /* 29806 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 29834 /* 29811 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29814 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29824 /* 29819 */ MCD_OPC_Decode, 144, 19, 145, 1, // Opcode: LDXPW /* 29824 */ MCD_OPC_FilterValue, 1, 31, 223, 0, // Skip to: 86948 /* 29829 */ MCD_OPC_Decode, 238, 16, 145, 1, // Opcode: LDAXPW /* 29834 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 29877 /* 29839 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29842 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29862 /* 29847 */ MCD_OPC_CheckPredicate, 2, 8, 223, 0, // Skip to: 86948 /* 29852 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29857 */ MCD_OPC_Decode, 229, 28, 145, 1, // Opcode: STLLRW /* 29862 */ MCD_OPC_FilterValue, 1, 249, 222, 0, // Skip to: 86948 /* 29867 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29872 */ MCD_OPC_Decode, 233, 28, 145, 1, // Opcode: STLRW /* 29877 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 29915 /* 29882 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 29885 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29900 /* 29890 */ MCD_OPC_CheckPredicate, 1, 221, 222, 0, // Skip to: 86948 /* 29895 */ MCD_OPC_Decode, 246, 2, 147, 1, // Opcode: CASW /* 29900 */ MCD_OPC_FilterValue, 63, 211, 222, 0, // Skip to: 86948 /* 29905 */ MCD_OPC_CheckPredicate, 1, 206, 222, 0, // Skip to: 86948 /* 29910 */ MCD_OPC_Decode, 236, 2, 147, 1, // Opcode: CASLW /* 29915 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 29958 /* 29920 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 29923 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29943 /* 29928 */ MCD_OPC_CheckPredicate, 2, 183, 222, 0, // Skip to: 86948 /* 29933 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29938 */ MCD_OPC_Decode, 166, 17, 145, 1, // Opcode: LDLARW /* 29943 */ MCD_OPC_FilterValue, 1, 168, 222, 0, // Skip to: 86948 /* 29948 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 29953 */ MCD_OPC_Decode, 236, 16, 145, 1, // Opcode: LDARW /* 29958 */ MCD_OPC_FilterValue, 7, 153, 222, 0, // Skip to: 86948 /* 29963 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 29966 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29981 /* 29971 */ MCD_OPC_CheckPredicate, 1, 140, 222, 0, // Skip to: 86948 /* 29976 */ MCD_OPC_Decode, 230, 2, 147, 1, // Opcode: CASAW /* 29981 */ MCD_OPC_FilterValue, 63, 130, 222, 0, // Skip to: 86948 /* 29986 */ MCD_OPC_CheckPredicate, 1, 125, 222, 0, // Skip to: 86948 /* 29991 */ MCD_OPC_Decode, 228, 2, 147, 1, // Opcode: CASALW /* 29996 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30024 /* 30001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30004 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30014 /* 30009 */ MCD_OPC_Decode, 244, 1, 148, 1, // Opcode: ANDXrs /* 30014 */ MCD_OPC_FilterValue, 1, 97, 222, 0, // Skip to: 86948 /* 30019 */ MCD_OPC_Decode, 180, 2, 148, 1, // Opcode: BICXrs /* 30024 */ MCD_OPC_FilterValue, 3, 87, 222, 0, // Skip to: 86948 /* 30029 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30032 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30042 /* 30037 */ MCD_OPC_Decode, 178, 1, 148, 1, // Opcode: ADDXrs /* 30042 */ MCD_OPC_FilterValue, 1, 69, 222, 0, // Skip to: 86948 /* 30047 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 30050 */ MCD_OPC_FilterValue, 0, 61, 222, 0, // Skip to: 86948 /* 30055 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30067 /* 30062 */ MCD_OPC_Decode, 180, 1, 149, 1, // Opcode: ADDXrx64 /* 30067 */ MCD_OPC_Decode, 179, 1, 149, 1, // Opcode: ADDXrx /* 30072 */ MCD_OPC_FilterValue, 5, 175, 0, 0, // Skip to: 30252 /* 30077 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 30080 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 30128 /* 30085 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 30088 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30098 /* 30093 */ MCD_OPC_Decode, 249, 28, 150, 1, // Opcode: STNPXi /* 30098 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 30108 /* 30103 */ MCD_OPC_Decode, 188, 17, 150, 1, // Opcode: LDNPXi /* 30108 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30118 /* 30113 */ MCD_OPC_Decode, 143, 29, 150, 1, // Opcode: STPXpost /* 30118 */ MCD_OPC_FilterValue, 3, 249, 221, 0, // Skip to: 86948 /* 30123 */ MCD_OPC_Decode, 213, 17, 150, 1, // Opcode: LDPXpost /* 30128 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 30176 /* 30133 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 30136 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30146 /* 30141 */ MCD_OPC_Decode, 142, 29, 150, 1, // Opcode: STPXi /* 30146 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 30156 /* 30151 */ MCD_OPC_Decode, 212, 17, 150, 1, // Opcode: LDPXi /* 30156 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30166 /* 30161 */ MCD_OPC_Decode, 144, 29, 150, 1, // Opcode: STPXpre /* 30166 */ MCD_OPC_FilterValue, 3, 201, 221, 0, // Skip to: 86948 /* 30171 */ MCD_OPC_Decode, 214, 17, 150, 1, // Opcode: LDPXpre /* 30176 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30204 /* 30181 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30184 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30194 /* 30189 */ MCD_OPC_Decode, 209, 20, 148, 1, // Opcode: ORRXrs /* 30194 */ MCD_OPC_FilterValue, 1, 173, 221, 0, // Skip to: 86948 /* 30199 */ MCD_OPC_Decode, 199, 20, 148, 1, // Opcode: ORNXrs /* 30204 */ MCD_OPC_FilterValue, 3, 163, 221, 0, // Skip to: 86948 /* 30209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30212 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30222 /* 30217 */ MCD_OPC_Decode, 163, 1, 148, 1, // Opcode: ADDSXrs /* 30222 */ MCD_OPC_FilterValue, 1, 145, 221, 0, // Skip to: 86948 /* 30227 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 30230 */ MCD_OPC_FilterValue, 0, 137, 221, 0, // Skip to: 86948 /* 30235 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30247 /* 30242 */ MCD_OPC_Decode, 165, 1, 149, 1, // Opcode: ADDSXrx64 /* 30247 */ MCD_OPC_Decode, 164, 1, 149, 1, // Opcode: ADDSXrx /* 30252 */ MCD_OPC_FilterValue, 6, 115, 1, 0, // Skip to: 30628 /* 30257 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 30260 */ MCD_OPC_FilterValue, 0, 31, 1, 0, // Skip to: 30552 /* 30265 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 30268 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 30296 /* 30273 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 30276 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30286 /* 30281 */ MCD_OPC_Decode, 210, 29, 145, 1, // Opcode: STXRX /* 30286 */ MCD_OPC_FilterValue, 1, 81, 221, 0, // Skip to: 86948 /* 30291 */ MCD_OPC_Decode, 244, 28, 145, 1, // Opcode: STLXRX /* 30296 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 30324 /* 30301 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 30304 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30314 /* 30309 */ MCD_OPC_Decode, 206, 29, 145, 1, // Opcode: STXPX /* 30314 */ MCD_OPC_FilterValue, 1, 53, 221, 0, // Skip to: 86948 /* 30319 */ MCD_OPC_Decode, 240, 28, 145, 1, // Opcode: STLXPX /* 30324 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 30362 /* 30329 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 30332 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 30347 /* 30337 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 30342 */ MCD_OPC_Decode, 149, 19, 145, 1, // Opcode: LDXRX /* 30347 */ MCD_OPC_FilterValue, 1, 20, 221, 0, // Skip to: 86948 /* 30352 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 30357 */ MCD_OPC_Decode, 243, 16, 145, 1, // Opcode: LDAXRX /* 30362 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 30390 /* 30367 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 30370 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30380 /* 30375 */ MCD_OPC_Decode, 145, 19, 145, 1, // Opcode: LDXPX /* 30380 */ MCD_OPC_FilterValue, 1, 243, 220, 0, // Skip to: 86948 /* 30385 */ MCD_OPC_Decode, 239, 16, 145, 1, // Opcode: LDAXPX /* 30390 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 30433 /* 30395 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 30398 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 30418 /* 30403 */ MCD_OPC_CheckPredicate, 2, 220, 220, 0, // Skip to: 86948 /* 30408 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 30413 */ MCD_OPC_Decode, 230, 28, 145, 1, // Opcode: STLLRX /* 30418 */ MCD_OPC_FilterValue, 1, 205, 220, 0, // Skip to: 86948 /* 30423 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 30428 */ MCD_OPC_Decode, 234, 28, 145, 1, // Opcode: STLRX /* 30433 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 30471 /* 30438 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 30441 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 30456 /* 30446 */ MCD_OPC_CheckPredicate, 1, 177, 220, 0, // Skip to: 86948 /* 30451 */ MCD_OPC_Decode, 247, 2, 152, 1, // Opcode: CASX /* 30456 */ MCD_OPC_FilterValue, 63, 167, 220, 0, // Skip to: 86948 /* 30461 */ MCD_OPC_CheckPredicate, 1, 162, 220, 0, // Skip to: 86948 /* 30466 */ MCD_OPC_Decode, 237, 2, 152, 1, // Opcode: CASLX /* 30471 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 30514 /* 30476 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 30479 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 30499 /* 30484 */ MCD_OPC_CheckPredicate, 2, 139, 220, 0, // Skip to: 86948 /* 30489 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 30494 */ MCD_OPC_Decode, 167, 17, 145, 1, // Opcode: LDLARX /* 30499 */ MCD_OPC_FilterValue, 1, 124, 220, 0, // Skip to: 86948 /* 30504 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, /* 30509 */ MCD_OPC_Decode, 237, 16, 145, 1, // Opcode: LDARX /* 30514 */ MCD_OPC_FilterValue, 7, 109, 220, 0, // Skip to: 86948 /* 30519 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 30522 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 30537 /* 30527 */ MCD_OPC_CheckPredicate, 1, 96, 220, 0, // Skip to: 86948 /* 30532 */ MCD_OPC_Decode, 231, 2, 152, 1, // Opcode: CASAX /* 30537 */ MCD_OPC_FilterValue, 63, 86, 220, 0, // Skip to: 86948 /* 30542 */ MCD_OPC_CheckPredicate, 1, 81, 220, 0, // Skip to: 86948 /* 30547 */ MCD_OPC_Decode, 229, 2, 152, 1, // Opcode: CASALX /* 30552 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30580 /* 30557 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30560 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30570 /* 30565 */ MCD_OPC_Decode, 237, 5, 148, 1, // Opcode: EORXrs /* 30570 */ MCD_OPC_FilterValue, 1, 53, 220, 0, // Skip to: 86948 /* 30575 */ MCD_OPC_Decode, 225, 5, 148, 1, // Opcode: EONXrs /* 30580 */ MCD_OPC_FilterValue, 3, 43, 220, 0, // Skip to: 86948 /* 30585 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30588 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30598 /* 30593 */ MCD_OPC_Decode, 240, 29, 148, 1, // Opcode: SUBXrs /* 30598 */ MCD_OPC_FilterValue, 1, 25, 220, 0, // Skip to: 86948 /* 30603 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 30606 */ MCD_OPC_FilterValue, 0, 17, 220, 0, // Skip to: 86948 /* 30611 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30623 /* 30618 */ MCD_OPC_Decode, 242, 29, 149, 1, // Opcode: SUBXrx64 /* 30623 */ MCD_OPC_Decode, 241, 29, 149, 1, // Opcode: SUBXrx /* 30628 */ MCD_OPC_FilterValue, 7, 251, 219, 0, // Skip to: 86948 /* 30633 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 30636 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 30664 /* 30641 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 30644 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30654 /* 30649 */ MCD_OPC_Decode, 233, 1, 148, 1, // Opcode: ANDSXrs /* 30654 */ MCD_OPC_FilterValue, 3, 225, 219, 0, // Skip to: 86948 /* 30659 */ MCD_OPC_Decode, 231, 29, 148, 1, // Opcode: SUBSXrs /* 30664 */ MCD_OPC_FilterValue, 1, 215, 219, 0, // Skip to: 86948 /* 30669 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 30672 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30682 /* 30677 */ MCD_OPC_Decode, 175, 2, 148, 1, // Opcode: BICSXrs /* 30682 */ MCD_OPC_FilterValue, 3, 197, 219, 0, // Skip to: 86948 /* 30687 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 30690 */ MCD_OPC_FilterValue, 0, 189, 219, 0, // Skip to: 86948 /* 30695 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30707 /* 30702 */ MCD_OPC_Decode, 233, 29, 149, 1, // Opcode: SUBSXrx64 /* 30707 */ MCD_OPC_Decode, 232, 29, 149, 1, // Opcode: SUBSXrx /* 30712 */ MCD_OPC_FilterValue, 3, 166, 145, 0, // Skip to: 68003 /* 30717 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 30720 */ MCD_OPC_FilterValue, 0, 76, 3, 0, // Skip to: 31569 /* 30725 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 30728 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 31111 /* 30733 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... /* 30736 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 30751 /* 30741 */ MCD_OPC_CheckPredicate, 3, 138, 219, 0, // Skip to: 86948 /* 30746 */ MCD_OPC_Decode, 211, 28, 153, 1, // Opcode: ST4Fourv8b /* 30751 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 30766 /* 30756 */ MCD_OPC_CheckPredicate, 3, 123, 219, 0, // Skip to: 86948 /* 30761 */ MCD_OPC_Decode, 207, 28, 153, 1, // Opcode: ST4Fourv4h /* 30766 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 30781 /* 30771 */ MCD_OPC_CheckPredicate, 3, 108, 219, 0, // Skip to: 86948 /* 30776 */ MCD_OPC_Decode, 205, 28, 153, 1, // Opcode: ST4Fourv2s /* 30781 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 30796 /* 30786 */ MCD_OPC_CheckPredicate, 3, 93, 219, 0, // Skip to: 86948 /* 30791 */ MCD_OPC_Decode, 195, 27, 153, 1, // Opcode: ST1Fourv8b /* 30796 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 30811 /* 30801 */ MCD_OPC_CheckPredicate, 3, 78, 219, 0, // Skip to: 86948 /* 30806 */ MCD_OPC_Decode, 191, 27, 153, 1, // Opcode: ST1Fourv4h /* 30811 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 30826 /* 30816 */ MCD_OPC_CheckPredicate, 3, 63, 219, 0, // Skip to: 86948 /* 30821 */ MCD_OPC_Decode, 189, 27, 153, 1, // Opcode: ST1Fourv2s /* 30826 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 30841 /* 30831 */ MCD_OPC_CheckPredicate, 3, 48, 219, 0, // Skip to: 86948 /* 30836 */ MCD_OPC_Decode, 185, 27, 153, 1, // Opcode: ST1Fourv1d /* 30841 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 30856 /* 30846 */ MCD_OPC_CheckPredicate, 3, 33, 219, 0, // Skip to: 86948 /* 30851 */ MCD_OPC_Decode, 183, 28, 154, 1, // Opcode: ST3Threev8b /* 30856 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 30871 /* 30861 */ MCD_OPC_CheckPredicate, 3, 18, 219, 0, // Skip to: 86948 /* 30866 */ MCD_OPC_Decode, 179, 28, 154, 1, // Opcode: ST3Threev4h /* 30871 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 30886 /* 30876 */ MCD_OPC_CheckPredicate, 3, 3, 219, 0, // Skip to: 86948 /* 30881 */ MCD_OPC_Decode, 177, 28, 154, 1, // Opcode: ST3Threev2s /* 30886 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 30901 /* 30891 */ MCD_OPC_CheckPredicate, 3, 244, 218, 0, // Skip to: 86948 /* 30896 */ MCD_OPC_Decode, 233, 27, 154, 1, // Opcode: ST1Threev8b /* 30901 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 30916 /* 30906 */ MCD_OPC_CheckPredicate, 3, 229, 218, 0, // Skip to: 86948 /* 30911 */ MCD_OPC_Decode, 229, 27, 154, 1, // Opcode: ST1Threev4h /* 30916 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 30931 /* 30921 */ MCD_OPC_CheckPredicate, 3, 214, 218, 0, // Skip to: 86948 /* 30926 */ MCD_OPC_Decode, 227, 27, 154, 1, // Opcode: ST1Threev2s /* 30931 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 30946 /* 30936 */ MCD_OPC_CheckPredicate, 3, 199, 218, 0, // Skip to: 86948 /* 30941 */ MCD_OPC_Decode, 223, 27, 154, 1, // Opcode: ST1Threev1d /* 30946 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 30961 /* 30951 */ MCD_OPC_CheckPredicate, 3, 184, 218, 0, // Skip to: 86948 /* 30956 */ MCD_OPC_Decode, 217, 27, 155, 1, // Opcode: ST1Onev8b /* 30961 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 30976 /* 30966 */ MCD_OPC_CheckPredicate, 3, 169, 218, 0, // Skip to: 86948 /* 30971 */ MCD_OPC_Decode, 213, 27, 155, 1, // Opcode: ST1Onev4h /* 30976 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 30991 /* 30981 */ MCD_OPC_CheckPredicate, 3, 154, 218, 0, // Skip to: 86948 /* 30986 */ MCD_OPC_Decode, 211, 27, 155, 1, // Opcode: ST1Onev2s /* 30991 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31006 /* 30996 */ MCD_OPC_CheckPredicate, 3, 139, 218, 0, // Skip to: 86948 /* 31001 */ MCD_OPC_Decode, 207, 27, 155, 1, // Opcode: ST1Onev1d /* 31006 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31021 /* 31011 */ MCD_OPC_CheckPredicate, 3, 124, 218, 0, // Skip to: 86948 /* 31016 */ MCD_OPC_Decode, 153, 28, 156, 1, // Opcode: ST2Twov8b /* 31021 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31036 /* 31026 */ MCD_OPC_CheckPredicate, 3, 109, 218, 0, // Skip to: 86948 /* 31031 */ MCD_OPC_Decode, 149, 28, 156, 1, // Opcode: ST2Twov4h /* 31036 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31051 /* 31041 */ MCD_OPC_CheckPredicate, 3, 94, 218, 0, // Skip to: 86948 /* 31046 */ MCD_OPC_Decode, 147, 28, 156, 1, // Opcode: ST2Twov2s /* 31051 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31066 /* 31056 */ MCD_OPC_CheckPredicate, 3, 79, 218, 0, // Skip to: 86948 /* 31061 */ MCD_OPC_Decode, 249, 27, 156, 1, // Opcode: ST1Twov8b /* 31066 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31081 /* 31071 */ MCD_OPC_CheckPredicate, 3, 64, 218, 0, // Skip to: 86948 /* 31076 */ MCD_OPC_Decode, 245, 27, 156, 1, // Opcode: ST1Twov4h /* 31081 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31096 /* 31086 */ MCD_OPC_CheckPredicate, 3, 49, 218, 0, // Skip to: 86948 /* 31091 */ MCD_OPC_Decode, 243, 27, 156, 1, // Opcode: ST1Twov2s /* 31096 */ MCD_OPC_FilterValue, 43, 39, 218, 0, // Skip to: 86948 /* 31101 */ MCD_OPC_CheckPredicate, 3, 34, 218, 0, // Skip to: 86948 /* 31106 */ MCD_OPC_Decode, 239, 27, 156, 1, // Opcode: ST1Twov1d /* 31111 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 31121 /* 31116 */ MCD_OPC_Decode, 247, 28, 150, 1, // Opcode: STNPSi /* 31121 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 31549 /* 31126 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... /* 31129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31144 /* 31134 */ MCD_OPC_CheckPredicate, 3, 1, 218, 0, // Skip to: 86948 /* 31139 */ MCD_OPC_Decode, 201, 28, 157, 1, // Opcode: ST4Fourv16b /* 31144 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 31159 /* 31149 */ MCD_OPC_CheckPredicate, 3, 242, 217, 0, // Skip to: 86948 /* 31154 */ MCD_OPC_Decode, 213, 28, 157, 1, // Opcode: ST4Fourv8h /* 31159 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 31174 /* 31164 */ MCD_OPC_CheckPredicate, 3, 227, 217, 0, // Skip to: 86948 /* 31169 */ MCD_OPC_Decode, 209, 28, 157, 1, // Opcode: ST4Fourv4s /* 31174 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 31189 /* 31179 */ MCD_OPC_CheckPredicate, 3, 212, 217, 0, // Skip to: 86948 /* 31184 */ MCD_OPC_Decode, 203, 28, 157, 1, // Opcode: ST4Fourv2d /* 31189 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 31204 /* 31194 */ MCD_OPC_CheckPredicate, 3, 197, 217, 0, // Skip to: 86948 /* 31199 */ MCD_OPC_Decode, 183, 27, 157, 1, // Opcode: ST1Fourv16b /* 31204 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 31219 /* 31209 */ MCD_OPC_CheckPredicate, 3, 182, 217, 0, // Skip to: 86948 /* 31214 */ MCD_OPC_Decode, 197, 27, 157, 1, // Opcode: ST1Fourv8h /* 31219 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 31234 /* 31224 */ MCD_OPC_CheckPredicate, 3, 167, 217, 0, // Skip to: 86948 /* 31229 */ MCD_OPC_Decode, 193, 27, 157, 1, // Opcode: ST1Fourv4s /* 31234 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 31249 /* 31239 */ MCD_OPC_CheckPredicate, 3, 152, 217, 0, // Skip to: 86948 /* 31244 */ MCD_OPC_Decode, 187, 27, 157, 1, // Opcode: ST1Fourv2d /* 31249 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 31264 /* 31254 */ MCD_OPC_CheckPredicate, 3, 137, 217, 0, // Skip to: 86948 /* 31259 */ MCD_OPC_Decode, 173, 28, 158, 1, // Opcode: ST3Threev16b /* 31264 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 31279 /* 31269 */ MCD_OPC_CheckPredicate, 3, 122, 217, 0, // Skip to: 86948 /* 31274 */ MCD_OPC_Decode, 185, 28, 158, 1, // Opcode: ST3Threev8h /* 31279 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 31294 /* 31284 */ MCD_OPC_CheckPredicate, 3, 107, 217, 0, // Skip to: 86948 /* 31289 */ MCD_OPC_Decode, 181, 28, 158, 1, // Opcode: ST3Threev4s /* 31294 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 31309 /* 31299 */ MCD_OPC_CheckPredicate, 3, 92, 217, 0, // Skip to: 86948 /* 31304 */ MCD_OPC_Decode, 175, 28, 158, 1, // Opcode: ST3Threev2d /* 31309 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 31324 /* 31314 */ MCD_OPC_CheckPredicate, 3, 77, 217, 0, // Skip to: 86948 /* 31319 */ MCD_OPC_Decode, 221, 27, 158, 1, // Opcode: ST1Threev16b /* 31324 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 31339 /* 31329 */ MCD_OPC_CheckPredicate, 3, 62, 217, 0, // Skip to: 86948 /* 31334 */ MCD_OPC_Decode, 235, 27, 158, 1, // Opcode: ST1Threev8h /* 31339 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 31354 /* 31344 */ MCD_OPC_CheckPredicate, 3, 47, 217, 0, // Skip to: 86948 /* 31349 */ MCD_OPC_Decode, 231, 27, 158, 1, // Opcode: ST1Threev4s /* 31354 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 31369 /* 31359 */ MCD_OPC_CheckPredicate, 3, 32, 217, 0, // Skip to: 86948 /* 31364 */ MCD_OPC_Decode, 225, 27, 158, 1, // Opcode: ST1Threev2d /* 31369 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 31384 /* 31374 */ MCD_OPC_CheckPredicate, 3, 17, 217, 0, // Skip to: 86948 /* 31379 */ MCD_OPC_Decode, 205, 27, 159, 1, // Opcode: ST1Onev16b /* 31384 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 31399 /* 31389 */ MCD_OPC_CheckPredicate, 3, 2, 217, 0, // Skip to: 86948 /* 31394 */ MCD_OPC_Decode, 219, 27, 159, 1, // Opcode: ST1Onev8h /* 31399 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 31414 /* 31404 */ MCD_OPC_CheckPredicate, 3, 243, 216, 0, // Skip to: 86948 /* 31409 */ MCD_OPC_Decode, 215, 27, 159, 1, // Opcode: ST1Onev4s /* 31414 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31429 /* 31419 */ MCD_OPC_CheckPredicate, 3, 228, 216, 0, // Skip to: 86948 /* 31424 */ MCD_OPC_Decode, 209, 27, 159, 1, // Opcode: ST1Onev2d /* 31429 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31444 /* 31434 */ MCD_OPC_CheckPredicate, 3, 213, 216, 0, // Skip to: 86948 /* 31439 */ MCD_OPC_Decode, 143, 28, 160, 1, // Opcode: ST2Twov16b /* 31444 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31459 /* 31449 */ MCD_OPC_CheckPredicate, 3, 198, 216, 0, // Skip to: 86948 /* 31454 */ MCD_OPC_Decode, 155, 28, 160, 1, // Opcode: ST2Twov8h /* 31459 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31474 /* 31464 */ MCD_OPC_CheckPredicate, 3, 183, 216, 0, // Skip to: 86948 /* 31469 */ MCD_OPC_Decode, 151, 28, 160, 1, // Opcode: ST2Twov4s /* 31474 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 31489 /* 31479 */ MCD_OPC_CheckPredicate, 3, 168, 216, 0, // Skip to: 86948 /* 31484 */ MCD_OPC_Decode, 145, 28, 160, 1, // Opcode: ST2Twov2d /* 31489 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31504 /* 31494 */ MCD_OPC_CheckPredicate, 3, 153, 216, 0, // Skip to: 86948 /* 31499 */ MCD_OPC_Decode, 237, 27, 160, 1, // Opcode: ST1Twov16b /* 31504 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31519 /* 31509 */ MCD_OPC_CheckPredicate, 3, 138, 216, 0, // Skip to: 86948 /* 31514 */ MCD_OPC_Decode, 251, 27, 160, 1, // Opcode: ST1Twov8h /* 31519 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31534 /* 31524 */ MCD_OPC_CheckPredicate, 3, 123, 216, 0, // Skip to: 86948 /* 31529 */ MCD_OPC_Decode, 247, 27, 160, 1, // Opcode: ST1Twov4s /* 31534 */ MCD_OPC_FilterValue, 43, 113, 216, 0, // Skip to: 86948 /* 31539 */ MCD_OPC_CheckPredicate, 3, 108, 216, 0, // Skip to: 86948 /* 31544 */ MCD_OPC_Decode, 241, 27, 160, 1, // Opcode: ST1Twov2d /* 31549 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 31559 /* 31554 */ MCD_OPC_Decode, 245, 28, 150, 1, // Opcode: STNPDi /* 31559 */ MCD_OPC_FilterValue, 5, 88, 216, 0, // Skip to: 86948 /* 31564 */ MCD_OPC_Decode, 246, 28, 150, 1, // Opcode: STNPQi /* 31569 */ MCD_OPC_FilterValue, 1, 76, 3, 0, // Skip to: 32418 /* 31574 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 31577 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 31960 /* 31582 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... /* 31585 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31600 /* 31590 */ MCD_OPC_CheckPredicate, 3, 57, 216, 0, // Skip to: 86948 /* 31595 */ MCD_OPC_Decode, 173, 16, 153, 1, // Opcode: LD4Fourv8b /* 31600 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 31615 /* 31605 */ MCD_OPC_CheckPredicate, 3, 42, 216, 0, // Skip to: 86948 /* 31610 */ MCD_OPC_Decode, 169, 16, 153, 1, // Opcode: LD4Fourv4h /* 31615 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 31630 /* 31620 */ MCD_OPC_CheckPredicate, 3, 27, 216, 0, // Skip to: 86948 /* 31625 */ MCD_OPC_Decode, 167, 16, 153, 1, // Opcode: LD4Fourv2s /* 31630 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 31645 /* 31635 */ MCD_OPC_CheckPredicate, 3, 12, 216, 0, // Skip to: 86948 /* 31640 */ MCD_OPC_Decode, 201, 14, 153, 1, // Opcode: LD1Fourv8b /* 31645 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 31660 /* 31650 */ MCD_OPC_CheckPredicate, 3, 253, 215, 0, // Skip to: 86948 /* 31655 */ MCD_OPC_Decode, 197, 14, 153, 1, // Opcode: LD1Fourv4h /* 31660 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 31675 /* 31665 */ MCD_OPC_CheckPredicate, 3, 238, 215, 0, // Skip to: 86948 /* 31670 */ MCD_OPC_Decode, 195, 14, 153, 1, // Opcode: LD1Fourv2s /* 31675 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 31690 /* 31680 */ MCD_OPC_CheckPredicate, 3, 223, 215, 0, // Skip to: 86948 /* 31685 */ MCD_OPC_Decode, 191, 14, 153, 1, // Opcode: LD1Fourv1d /* 31690 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 31705 /* 31695 */ MCD_OPC_CheckPredicate, 3, 208, 215, 0, // Skip to: 86948 /* 31700 */ MCD_OPC_Decode, 145, 16, 154, 1, // Opcode: LD3Threev8b /* 31705 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 31720 /* 31710 */ MCD_OPC_CheckPredicate, 3, 193, 215, 0, // Skip to: 86948 /* 31715 */ MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: LD3Threev4h /* 31720 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 31735 /* 31725 */ MCD_OPC_CheckPredicate, 3, 178, 215, 0, // Skip to: 86948 /* 31730 */ MCD_OPC_Decode, 139, 16, 154, 1, // Opcode: LD3Threev2s /* 31735 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 31750 /* 31740 */ MCD_OPC_CheckPredicate, 3, 163, 215, 0, // Skip to: 86948 /* 31745 */ MCD_OPC_Decode, 163, 15, 154, 1, // Opcode: LD1Threev8b /* 31750 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 31765 /* 31755 */ MCD_OPC_CheckPredicate, 3, 148, 215, 0, // Skip to: 86948 /* 31760 */ MCD_OPC_Decode, 159, 15, 154, 1, // Opcode: LD1Threev4h /* 31765 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 31780 /* 31770 */ MCD_OPC_CheckPredicate, 3, 133, 215, 0, // Skip to: 86948 /* 31775 */ MCD_OPC_Decode, 157, 15, 154, 1, // Opcode: LD1Threev2s /* 31780 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 31795 /* 31785 */ MCD_OPC_CheckPredicate, 3, 118, 215, 0, // Skip to: 86948 /* 31790 */ MCD_OPC_Decode, 153, 15, 154, 1, // Opcode: LD1Threev1d /* 31795 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 31810 /* 31800 */ MCD_OPC_CheckPredicate, 3, 103, 215, 0, // Skip to: 86948 /* 31805 */ MCD_OPC_Decode, 223, 14, 155, 1, // Opcode: LD1Onev8b /* 31810 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 31825 /* 31815 */ MCD_OPC_CheckPredicate, 3, 88, 215, 0, // Skip to: 86948 /* 31820 */ MCD_OPC_Decode, 219, 14, 155, 1, // Opcode: LD1Onev4h /* 31825 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 31840 /* 31830 */ MCD_OPC_CheckPredicate, 3, 73, 215, 0, // Skip to: 86948 /* 31835 */ MCD_OPC_Decode, 217, 14, 155, 1, // Opcode: LD1Onev2s /* 31840 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31855 /* 31845 */ MCD_OPC_CheckPredicate, 3, 58, 215, 0, // Skip to: 86948 /* 31850 */ MCD_OPC_Decode, 213, 14, 155, 1, // Opcode: LD1Onev1d /* 31855 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31870 /* 31860 */ MCD_OPC_CheckPredicate, 3, 43, 215, 0, // Skip to: 86948 /* 31865 */ MCD_OPC_Decode, 227, 15, 156, 1, // Opcode: LD2Twov8b /* 31870 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31885 /* 31875 */ MCD_OPC_CheckPredicate, 3, 28, 215, 0, // Skip to: 86948 /* 31880 */ MCD_OPC_Decode, 223, 15, 156, 1, // Opcode: LD2Twov4h /* 31885 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31900 /* 31890 */ MCD_OPC_CheckPredicate, 3, 13, 215, 0, // Skip to: 86948 /* 31895 */ MCD_OPC_Decode, 221, 15, 156, 1, // Opcode: LD2Twov2s /* 31900 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31915 /* 31905 */ MCD_OPC_CheckPredicate, 3, 254, 214, 0, // Skip to: 86948 /* 31910 */ MCD_OPC_Decode, 179, 15, 156, 1, // Opcode: LD1Twov8b /* 31915 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31930 /* 31920 */ MCD_OPC_CheckPredicate, 3, 239, 214, 0, // Skip to: 86948 /* 31925 */ MCD_OPC_Decode, 175, 15, 156, 1, // Opcode: LD1Twov4h /* 31930 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31945 /* 31935 */ MCD_OPC_CheckPredicate, 3, 224, 214, 0, // Skip to: 86948 /* 31940 */ MCD_OPC_Decode, 173, 15, 156, 1, // Opcode: LD1Twov2s /* 31945 */ MCD_OPC_FilterValue, 43, 214, 214, 0, // Skip to: 86948 /* 31950 */ MCD_OPC_CheckPredicate, 3, 209, 214, 0, // Skip to: 86948 /* 31955 */ MCD_OPC_Decode, 169, 15, 156, 1, // Opcode: LD1Twov1d /* 31960 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 31970 /* 31965 */ MCD_OPC_Decode, 186, 17, 150, 1, // Opcode: LDNPSi /* 31970 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 32398 /* 31975 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... /* 31978 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31993 /* 31983 */ MCD_OPC_CheckPredicate, 3, 176, 214, 0, // Skip to: 86948 /* 31988 */ MCD_OPC_Decode, 163, 16, 157, 1, // Opcode: LD4Fourv16b /* 31993 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 32008 /* 31998 */ MCD_OPC_CheckPredicate, 3, 161, 214, 0, // Skip to: 86948 /* 32003 */ MCD_OPC_Decode, 175, 16, 157, 1, // Opcode: LD4Fourv8h /* 32008 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 32023 /* 32013 */ MCD_OPC_CheckPredicate, 3, 146, 214, 0, // Skip to: 86948 /* 32018 */ MCD_OPC_Decode, 171, 16, 157, 1, // Opcode: LD4Fourv4s /* 32023 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 32038 /* 32028 */ MCD_OPC_CheckPredicate, 3, 131, 214, 0, // Skip to: 86948 /* 32033 */ MCD_OPC_Decode, 165, 16, 157, 1, // Opcode: LD4Fourv2d /* 32038 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 32053 /* 32043 */ MCD_OPC_CheckPredicate, 3, 116, 214, 0, // Skip to: 86948 /* 32048 */ MCD_OPC_Decode, 189, 14, 157, 1, // Opcode: LD1Fourv16b /* 32053 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 32068 /* 32058 */ MCD_OPC_CheckPredicate, 3, 101, 214, 0, // Skip to: 86948 /* 32063 */ MCD_OPC_Decode, 203, 14, 157, 1, // Opcode: LD1Fourv8h /* 32068 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 32083 /* 32073 */ MCD_OPC_CheckPredicate, 3, 86, 214, 0, // Skip to: 86948 /* 32078 */ MCD_OPC_Decode, 199, 14, 157, 1, // Opcode: LD1Fourv4s /* 32083 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 32098 /* 32088 */ MCD_OPC_CheckPredicate, 3, 71, 214, 0, // Skip to: 86948 /* 32093 */ MCD_OPC_Decode, 193, 14, 157, 1, // Opcode: LD1Fourv2d /* 32098 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 32113 /* 32103 */ MCD_OPC_CheckPredicate, 3, 56, 214, 0, // Skip to: 86948 /* 32108 */ MCD_OPC_Decode, 135, 16, 158, 1, // Opcode: LD3Threev16b /* 32113 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 32128 /* 32118 */ MCD_OPC_CheckPredicate, 3, 41, 214, 0, // Skip to: 86948 /* 32123 */ MCD_OPC_Decode, 147, 16, 158, 1, // Opcode: LD3Threev8h /* 32128 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 32143 /* 32133 */ MCD_OPC_CheckPredicate, 3, 26, 214, 0, // Skip to: 86948 /* 32138 */ MCD_OPC_Decode, 143, 16, 158, 1, // Opcode: LD3Threev4s /* 32143 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 32158 /* 32148 */ MCD_OPC_CheckPredicate, 3, 11, 214, 0, // Skip to: 86948 /* 32153 */ MCD_OPC_Decode, 137, 16, 158, 1, // Opcode: LD3Threev2d /* 32158 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 32173 /* 32163 */ MCD_OPC_CheckPredicate, 3, 252, 213, 0, // Skip to: 86948 /* 32168 */ MCD_OPC_Decode, 151, 15, 158, 1, // Opcode: LD1Threev16b /* 32173 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 32188 /* 32178 */ MCD_OPC_CheckPredicate, 3, 237, 213, 0, // Skip to: 86948 /* 32183 */ MCD_OPC_Decode, 165, 15, 158, 1, // Opcode: LD1Threev8h /* 32188 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 32203 /* 32193 */ MCD_OPC_CheckPredicate, 3, 222, 213, 0, // Skip to: 86948 /* 32198 */ MCD_OPC_Decode, 161, 15, 158, 1, // Opcode: LD1Threev4s /* 32203 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 32218 /* 32208 */ MCD_OPC_CheckPredicate, 3, 207, 213, 0, // Skip to: 86948 /* 32213 */ MCD_OPC_Decode, 155, 15, 158, 1, // Opcode: LD1Threev2d /* 32218 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 32233 /* 32223 */ MCD_OPC_CheckPredicate, 3, 192, 213, 0, // Skip to: 86948 /* 32228 */ MCD_OPC_Decode, 211, 14, 159, 1, // Opcode: LD1Onev16b /* 32233 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 32248 /* 32238 */ MCD_OPC_CheckPredicate, 3, 177, 213, 0, // Skip to: 86948 /* 32243 */ MCD_OPC_Decode, 225, 14, 159, 1, // Opcode: LD1Onev8h /* 32248 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 32263 /* 32253 */ MCD_OPC_CheckPredicate, 3, 162, 213, 0, // Skip to: 86948 /* 32258 */ MCD_OPC_Decode, 221, 14, 159, 1, // Opcode: LD1Onev4s /* 32263 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 32278 /* 32268 */ MCD_OPC_CheckPredicate, 3, 147, 213, 0, // Skip to: 86948 /* 32273 */ MCD_OPC_Decode, 215, 14, 159, 1, // Opcode: LD1Onev2d /* 32278 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 32293 /* 32283 */ MCD_OPC_CheckPredicate, 3, 132, 213, 0, // Skip to: 86948 /* 32288 */ MCD_OPC_Decode, 217, 15, 160, 1, // Opcode: LD2Twov16b /* 32293 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 32308 /* 32298 */ MCD_OPC_CheckPredicate, 3, 117, 213, 0, // Skip to: 86948 /* 32303 */ MCD_OPC_Decode, 229, 15, 160, 1, // Opcode: LD2Twov8h /* 32308 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 32323 /* 32313 */ MCD_OPC_CheckPredicate, 3, 102, 213, 0, // Skip to: 86948 /* 32318 */ MCD_OPC_Decode, 225, 15, 160, 1, // Opcode: LD2Twov4s /* 32323 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 32338 /* 32328 */ MCD_OPC_CheckPredicate, 3, 87, 213, 0, // Skip to: 86948 /* 32333 */ MCD_OPC_Decode, 219, 15, 160, 1, // Opcode: LD2Twov2d /* 32338 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 32353 /* 32343 */ MCD_OPC_CheckPredicate, 3, 72, 213, 0, // Skip to: 86948 /* 32348 */ MCD_OPC_Decode, 167, 15, 160, 1, // Opcode: LD1Twov16b /* 32353 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 32368 /* 32358 */ MCD_OPC_CheckPredicate, 3, 57, 213, 0, // Skip to: 86948 /* 32363 */ MCD_OPC_Decode, 181, 15, 160, 1, // Opcode: LD1Twov8h /* 32368 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 32383 /* 32373 */ MCD_OPC_CheckPredicate, 3, 42, 213, 0, // Skip to: 86948 /* 32378 */ MCD_OPC_Decode, 177, 15, 160, 1, // Opcode: LD1Twov4s /* 32383 */ MCD_OPC_FilterValue, 43, 32, 213, 0, // Skip to: 86948 /* 32388 */ MCD_OPC_CheckPredicate, 3, 27, 213, 0, // Skip to: 86948 /* 32393 */ MCD_OPC_Decode, 171, 15, 160, 1, // Opcode: LD1Twov2d /* 32398 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 32408 /* 32403 */ MCD_OPC_Decode, 184, 17, 150, 1, // Opcode: LDNPDi /* 32408 */ MCD_OPC_FilterValue, 5, 7, 213, 0, // Skip to: 86948 /* 32413 */ MCD_OPC_Decode, 185, 17, 150, 1, // Opcode: LDNPQi /* 32418 */ MCD_OPC_FilterValue, 2, 191, 4, 0, // Skip to: 33638 /* 32423 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 32426 */ MCD_OPC_FilterValue, 0, 41, 2, 0, // Skip to: 32984 /* 32431 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 32434 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 32456 /* 32439 */ MCD_OPC_CheckPredicate, 3, 232, 212, 0, // Skip to: 86948 /* 32444 */ MCD_OPC_CheckField, 21, 1, 0, 225, 212, 0, // Skip to: 86948 /* 32451 */ MCD_OPC_Decode, 212, 28, 161, 1, // Opcode: ST4Fourv8b_POST /* 32456 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 32478 /* 32461 */ MCD_OPC_CheckPredicate, 3, 210, 212, 0, // Skip to: 86948 /* 32466 */ MCD_OPC_CheckField, 21, 1, 0, 203, 212, 0, // Skip to: 86948 /* 32473 */ MCD_OPC_Decode, 208, 28, 161, 1, // Opcode: ST4Fourv4h_POST /* 32478 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 32500 /* 32483 */ MCD_OPC_CheckPredicate, 3, 188, 212, 0, // Skip to: 86948 /* 32488 */ MCD_OPC_CheckField, 21, 1, 0, 181, 212, 0, // Skip to: 86948 /* 32495 */ MCD_OPC_Decode, 206, 28, 161, 1, // Opcode: ST4Fourv2s_POST /* 32500 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 32522 /* 32505 */ MCD_OPC_CheckPredicate, 3, 166, 212, 0, // Skip to: 86948 /* 32510 */ MCD_OPC_CheckField, 21, 1, 0, 159, 212, 0, // Skip to: 86948 /* 32517 */ MCD_OPC_Decode, 196, 27, 161, 1, // Opcode: ST1Fourv8b_POST /* 32522 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 32544 /* 32527 */ MCD_OPC_CheckPredicate, 3, 144, 212, 0, // Skip to: 86948 /* 32532 */ MCD_OPC_CheckField, 21, 1, 0, 137, 212, 0, // Skip to: 86948 /* 32539 */ MCD_OPC_Decode, 192, 27, 161, 1, // Opcode: ST1Fourv4h_POST /* 32544 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 32566 /* 32549 */ MCD_OPC_CheckPredicate, 3, 122, 212, 0, // Skip to: 86948 /* 32554 */ MCD_OPC_CheckField, 21, 1, 0, 115, 212, 0, // Skip to: 86948 /* 32561 */ MCD_OPC_Decode, 190, 27, 161, 1, // Opcode: ST1Fourv2s_POST /* 32566 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 32588 /* 32571 */ MCD_OPC_CheckPredicate, 3, 100, 212, 0, // Skip to: 86948 /* 32576 */ MCD_OPC_CheckField, 21, 1, 0, 93, 212, 0, // Skip to: 86948 /* 32583 */ MCD_OPC_Decode, 186, 27, 161, 1, // Opcode: ST1Fourv1d_POST /* 32588 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 32610 /* 32593 */ MCD_OPC_CheckPredicate, 3, 78, 212, 0, // Skip to: 86948 /* 32598 */ MCD_OPC_CheckField, 21, 1, 0, 71, 212, 0, // Skip to: 86948 /* 32605 */ MCD_OPC_Decode, 184, 28, 162, 1, // Opcode: ST3Threev8b_POST /* 32610 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 32632 /* 32615 */ MCD_OPC_CheckPredicate, 3, 56, 212, 0, // Skip to: 86948 /* 32620 */ MCD_OPC_CheckField, 21, 1, 0, 49, 212, 0, // Skip to: 86948 /* 32627 */ MCD_OPC_Decode, 180, 28, 162, 1, // Opcode: ST3Threev4h_POST /* 32632 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 32654 /* 32637 */ MCD_OPC_CheckPredicate, 3, 34, 212, 0, // Skip to: 86948 /* 32642 */ MCD_OPC_CheckField, 21, 1, 0, 27, 212, 0, // Skip to: 86948 /* 32649 */ MCD_OPC_Decode, 178, 28, 162, 1, // Opcode: ST3Threev2s_POST /* 32654 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 32676 /* 32659 */ MCD_OPC_CheckPredicate, 3, 12, 212, 0, // Skip to: 86948 /* 32664 */ MCD_OPC_CheckField, 21, 1, 0, 5, 212, 0, // Skip to: 86948 /* 32671 */ MCD_OPC_Decode, 234, 27, 162, 1, // Opcode: ST1Threev8b_POST /* 32676 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 32698 /* 32681 */ MCD_OPC_CheckPredicate, 3, 246, 211, 0, // Skip to: 86948 /* 32686 */ MCD_OPC_CheckField, 21, 1, 0, 239, 211, 0, // Skip to: 86948 /* 32693 */ MCD_OPC_Decode, 230, 27, 162, 1, // Opcode: ST1Threev4h_POST /* 32698 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 32720 /* 32703 */ MCD_OPC_CheckPredicate, 3, 224, 211, 0, // Skip to: 86948 /* 32708 */ MCD_OPC_CheckField, 21, 1, 0, 217, 211, 0, // Skip to: 86948 /* 32715 */ MCD_OPC_Decode, 228, 27, 162, 1, // Opcode: ST1Threev2s_POST /* 32720 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 32742 /* 32725 */ MCD_OPC_CheckPredicate, 3, 202, 211, 0, // Skip to: 86948 /* 32730 */ MCD_OPC_CheckField, 21, 1, 0, 195, 211, 0, // Skip to: 86948 /* 32737 */ MCD_OPC_Decode, 224, 27, 162, 1, // Opcode: ST1Threev1d_POST /* 32742 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 32764 /* 32747 */ MCD_OPC_CheckPredicate, 3, 180, 211, 0, // Skip to: 86948 /* 32752 */ MCD_OPC_CheckField, 21, 1, 0, 173, 211, 0, // Skip to: 86948 /* 32759 */ MCD_OPC_Decode, 218, 27, 163, 1, // Opcode: ST1Onev8b_POST /* 32764 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 32786 /* 32769 */ MCD_OPC_CheckPredicate, 3, 158, 211, 0, // Skip to: 86948 /* 32774 */ MCD_OPC_CheckField, 21, 1, 0, 151, 211, 0, // Skip to: 86948 /* 32781 */ MCD_OPC_Decode, 214, 27, 163, 1, // Opcode: ST1Onev4h_POST /* 32786 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 32808 /* 32791 */ MCD_OPC_CheckPredicate, 3, 136, 211, 0, // Skip to: 86948 /* 32796 */ MCD_OPC_CheckField, 21, 1, 0, 129, 211, 0, // Skip to: 86948 /* 32803 */ MCD_OPC_Decode, 212, 27, 163, 1, // Opcode: ST1Onev2s_POST /* 32808 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 32830 /* 32813 */ MCD_OPC_CheckPredicate, 3, 114, 211, 0, // Skip to: 86948 /* 32818 */ MCD_OPC_CheckField, 21, 1, 0, 107, 211, 0, // Skip to: 86948 /* 32825 */ MCD_OPC_Decode, 208, 27, 163, 1, // Opcode: ST1Onev1d_POST /* 32830 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 32852 /* 32835 */ MCD_OPC_CheckPredicate, 3, 92, 211, 0, // Skip to: 86948 /* 32840 */ MCD_OPC_CheckField, 21, 1, 0, 85, 211, 0, // Skip to: 86948 /* 32847 */ MCD_OPC_Decode, 154, 28, 164, 1, // Opcode: ST2Twov8b_POST /* 32852 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 32874 /* 32857 */ MCD_OPC_CheckPredicate, 3, 70, 211, 0, // Skip to: 86948 /* 32862 */ MCD_OPC_CheckField, 21, 1, 0, 63, 211, 0, // Skip to: 86948 /* 32869 */ MCD_OPC_Decode, 150, 28, 164, 1, // Opcode: ST2Twov4h_POST /* 32874 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 32896 /* 32879 */ MCD_OPC_CheckPredicate, 3, 48, 211, 0, // Skip to: 86948 /* 32884 */ MCD_OPC_CheckField, 21, 1, 0, 41, 211, 0, // Skip to: 86948 /* 32891 */ MCD_OPC_Decode, 148, 28, 164, 1, // Opcode: ST2Twov2s_POST /* 32896 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 32918 /* 32901 */ MCD_OPC_CheckPredicate, 3, 26, 211, 0, // Skip to: 86948 /* 32906 */ MCD_OPC_CheckField, 21, 1, 0, 19, 211, 0, // Skip to: 86948 /* 32913 */ MCD_OPC_Decode, 250, 27, 164, 1, // Opcode: ST1Twov8b_POST /* 32918 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 32940 /* 32923 */ MCD_OPC_CheckPredicate, 3, 4, 211, 0, // Skip to: 86948 /* 32928 */ MCD_OPC_CheckField, 21, 1, 0, 253, 210, 0, // Skip to: 86948 /* 32935 */ MCD_OPC_Decode, 246, 27, 164, 1, // Opcode: ST1Twov4h_POST /* 32940 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 32962 /* 32945 */ MCD_OPC_CheckPredicate, 3, 238, 210, 0, // Skip to: 86948 /* 32950 */ MCD_OPC_CheckField, 21, 1, 0, 231, 210, 0, // Skip to: 86948 /* 32957 */ MCD_OPC_Decode, 244, 27, 164, 1, // Opcode: ST1Twov2s_POST /* 32962 */ MCD_OPC_FilterValue, 43, 221, 210, 0, // Skip to: 86948 /* 32967 */ MCD_OPC_CheckPredicate, 3, 216, 210, 0, // Skip to: 86948 /* 32972 */ MCD_OPC_CheckField, 21, 1, 0, 209, 210, 0, // Skip to: 86948 /* 32979 */ MCD_OPC_Decode, 240, 27, 164, 1, // Opcode: ST1Twov1d_POST /* 32984 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 32994 /* 32989 */ MCD_OPC_Decode, 137, 29, 150, 1, // Opcode: STPSpost /* 32994 */ MCD_OPC_FilterValue, 2, 107, 2, 0, // Skip to: 33618 /* 32999 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 33002 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33024 /* 33007 */ MCD_OPC_CheckPredicate, 3, 176, 210, 0, // Skip to: 86948 /* 33012 */ MCD_OPC_CheckField, 21, 1, 0, 169, 210, 0, // Skip to: 86948 /* 33019 */ MCD_OPC_Decode, 202, 28, 165, 1, // Opcode: ST4Fourv16b_POST /* 33024 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 33046 /* 33029 */ MCD_OPC_CheckPredicate, 3, 154, 210, 0, // Skip to: 86948 /* 33034 */ MCD_OPC_CheckField, 21, 1, 0, 147, 210, 0, // Skip to: 86948 /* 33041 */ MCD_OPC_Decode, 214, 28, 165, 1, // Opcode: ST4Fourv8h_POST /* 33046 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 33068 /* 33051 */ MCD_OPC_CheckPredicate, 3, 132, 210, 0, // Skip to: 86948 /* 33056 */ MCD_OPC_CheckField, 21, 1, 0, 125, 210, 0, // Skip to: 86948 /* 33063 */ MCD_OPC_Decode, 210, 28, 165, 1, // Opcode: ST4Fourv4s_POST /* 33068 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 33090 /* 33073 */ MCD_OPC_CheckPredicate, 3, 110, 210, 0, // Skip to: 86948 /* 33078 */ MCD_OPC_CheckField, 21, 1, 0, 103, 210, 0, // Skip to: 86948 /* 33085 */ MCD_OPC_Decode, 204, 28, 165, 1, // Opcode: ST4Fourv2d_POST /* 33090 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 33112 /* 33095 */ MCD_OPC_CheckPredicate, 3, 88, 210, 0, // Skip to: 86948 /* 33100 */ MCD_OPC_CheckField, 21, 1, 0, 81, 210, 0, // Skip to: 86948 /* 33107 */ MCD_OPC_Decode, 184, 27, 165, 1, // Opcode: ST1Fourv16b_POST /* 33112 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 33134 /* 33117 */ MCD_OPC_CheckPredicate, 3, 66, 210, 0, // Skip to: 86948 /* 33122 */ MCD_OPC_CheckField, 21, 1, 0, 59, 210, 0, // Skip to: 86948 /* 33129 */ MCD_OPC_Decode, 198, 27, 165, 1, // Opcode: ST1Fourv8h_POST /* 33134 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 33156 /* 33139 */ MCD_OPC_CheckPredicate, 3, 44, 210, 0, // Skip to: 86948 /* 33144 */ MCD_OPC_CheckField, 21, 1, 0, 37, 210, 0, // Skip to: 86948 /* 33151 */ MCD_OPC_Decode, 194, 27, 165, 1, // Opcode: ST1Fourv4s_POST /* 33156 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 33178 /* 33161 */ MCD_OPC_CheckPredicate, 3, 22, 210, 0, // Skip to: 86948 /* 33166 */ MCD_OPC_CheckField, 21, 1, 0, 15, 210, 0, // Skip to: 86948 /* 33173 */ MCD_OPC_Decode, 188, 27, 165, 1, // Opcode: ST1Fourv2d_POST /* 33178 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 33200 /* 33183 */ MCD_OPC_CheckPredicate, 3, 0, 210, 0, // Skip to: 86948 /* 33188 */ MCD_OPC_CheckField, 21, 1, 0, 249, 209, 0, // Skip to: 86948 /* 33195 */ MCD_OPC_Decode, 174, 28, 166, 1, // Opcode: ST3Threev16b_POST /* 33200 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 33222 /* 33205 */ MCD_OPC_CheckPredicate, 3, 234, 209, 0, // Skip to: 86948 /* 33210 */ MCD_OPC_CheckField, 21, 1, 0, 227, 209, 0, // Skip to: 86948 /* 33217 */ MCD_OPC_Decode, 186, 28, 166, 1, // Opcode: ST3Threev8h_POST /* 33222 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 33244 /* 33227 */ MCD_OPC_CheckPredicate, 3, 212, 209, 0, // Skip to: 86948 /* 33232 */ MCD_OPC_CheckField, 21, 1, 0, 205, 209, 0, // Skip to: 86948 /* 33239 */ MCD_OPC_Decode, 182, 28, 166, 1, // Opcode: ST3Threev4s_POST /* 33244 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 33266 /* 33249 */ MCD_OPC_CheckPredicate, 3, 190, 209, 0, // Skip to: 86948 /* 33254 */ MCD_OPC_CheckField, 21, 1, 0, 183, 209, 0, // Skip to: 86948 /* 33261 */ MCD_OPC_Decode, 176, 28, 166, 1, // Opcode: ST3Threev2d_POST /* 33266 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 33288 /* 33271 */ MCD_OPC_CheckPredicate, 3, 168, 209, 0, // Skip to: 86948 /* 33276 */ MCD_OPC_CheckField, 21, 1, 0, 161, 209, 0, // Skip to: 86948 /* 33283 */ MCD_OPC_Decode, 222, 27, 166, 1, // Opcode: ST1Threev16b_POST /* 33288 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 33310 /* 33293 */ MCD_OPC_CheckPredicate, 3, 146, 209, 0, // Skip to: 86948 /* 33298 */ MCD_OPC_CheckField, 21, 1, 0, 139, 209, 0, // Skip to: 86948 /* 33305 */ MCD_OPC_Decode, 236, 27, 166, 1, // Opcode: ST1Threev8h_POST /* 33310 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 33332 /* 33315 */ MCD_OPC_CheckPredicate, 3, 124, 209, 0, // Skip to: 86948 /* 33320 */ MCD_OPC_CheckField, 21, 1, 0, 117, 209, 0, // Skip to: 86948 /* 33327 */ MCD_OPC_Decode, 232, 27, 166, 1, // Opcode: ST1Threev4s_POST /* 33332 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 33354 /* 33337 */ MCD_OPC_CheckPredicate, 3, 102, 209, 0, // Skip to: 86948 /* 33342 */ MCD_OPC_CheckField, 21, 1, 0, 95, 209, 0, // Skip to: 86948 /* 33349 */ MCD_OPC_Decode, 226, 27, 166, 1, // Opcode: ST1Threev2d_POST /* 33354 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 33376 /* 33359 */ MCD_OPC_CheckPredicate, 3, 80, 209, 0, // Skip to: 86948 /* 33364 */ MCD_OPC_CheckField, 21, 1, 0, 73, 209, 0, // Skip to: 86948 /* 33371 */ MCD_OPC_Decode, 206, 27, 167, 1, // Opcode: ST1Onev16b_POST /* 33376 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 33398 /* 33381 */ MCD_OPC_CheckPredicate, 3, 58, 209, 0, // Skip to: 86948 /* 33386 */ MCD_OPC_CheckField, 21, 1, 0, 51, 209, 0, // Skip to: 86948 /* 33393 */ MCD_OPC_Decode, 220, 27, 167, 1, // Opcode: ST1Onev8h_POST /* 33398 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 33420 /* 33403 */ MCD_OPC_CheckPredicate, 3, 36, 209, 0, // Skip to: 86948 /* 33408 */ MCD_OPC_CheckField, 21, 1, 0, 29, 209, 0, // Skip to: 86948 /* 33415 */ MCD_OPC_Decode, 216, 27, 167, 1, // Opcode: ST1Onev4s_POST /* 33420 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 33442 /* 33425 */ MCD_OPC_CheckPredicate, 3, 14, 209, 0, // Skip to: 86948 /* 33430 */ MCD_OPC_CheckField, 21, 1, 0, 7, 209, 0, // Skip to: 86948 /* 33437 */ MCD_OPC_Decode, 210, 27, 167, 1, // Opcode: ST1Onev2d_POST /* 33442 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 33464 /* 33447 */ MCD_OPC_CheckPredicate, 3, 248, 208, 0, // Skip to: 86948 /* 33452 */ MCD_OPC_CheckField, 21, 1, 0, 241, 208, 0, // Skip to: 86948 /* 33459 */ MCD_OPC_Decode, 144, 28, 168, 1, // Opcode: ST2Twov16b_POST /* 33464 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 33486 /* 33469 */ MCD_OPC_CheckPredicate, 3, 226, 208, 0, // Skip to: 86948 /* 33474 */ MCD_OPC_CheckField, 21, 1, 0, 219, 208, 0, // Skip to: 86948 /* 33481 */ MCD_OPC_Decode, 156, 28, 168, 1, // Opcode: ST2Twov8h_POST /* 33486 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 33508 /* 33491 */ MCD_OPC_CheckPredicate, 3, 204, 208, 0, // Skip to: 86948 /* 33496 */ MCD_OPC_CheckField, 21, 1, 0, 197, 208, 0, // Skip to: 86948 /* 33503 */ MCD_OPC_Decode, 152, 28, 168, 1, // Opcode: ST2Twov4s_POST /* 33508 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 33530 /* 33513 */ MCD_OPC_CheckPredicate, 3, 182, 208, 0, // Skip to: 86948 /* 33518 */ MCD_OPC_CheckField, 21, 1, 0, 175, 208, 0, // Skip to: 86948 /* 33525 */ MCD_OPC_Decode, 146, 28, 168, 1, // Opcode: ST2Twov2d_POST /* 33530 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 33552 /* 33535 */ MCD_OPC_CheckPredicate, 3, 160, 208, 0, // Skip to: 86948 /* 33540 */ MCD_OPC_CheckField, 21, 1, 0, 153, 208, 0, // Skip to: 86948 /* 33547 */ MCD_OPC_Decode, 238, 27, 168, 1, // Opcode: ST1Twov16b_POST /* 33552 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 33574 /* 33557 */ MCD_OPC_CheckPredicate, 3, 138, 208, 0, // Skip to: 86948 /* 33562 */ MCD_OPC_CheckField, 21, 1, 0, 131, 208, 0, // Skip to: 86948 /* 33569 */ MCD_OPC_Decode, 252, 27, 168, 1, // Opcode: ST1Twov8h_POST /* 33574 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 33596 /* 33579 */ MCD_OPC_CheckPredicate, 3, 116, 208, 0, // Skip to: 86948 /* 33584 */ MCD_OPC_CheckField, 21, 1, 0, 109, 208, 0, // Skip to: 86948 /* 33591 */ MCD_OPC_Decode, 248, 27, 168, 1, // Opcode: ST1Twov4s_POST /* 33596 */ MCD_OPC_FilterValue, 43, 99, 208, 0, // Skip to: 86948 /* 33601 */ MCD_OPC_CheckPredicate, 3, 94, 208, 0, // Skip to: 86948 /* 33606 */ MCD_OPC_CheckField, 21, 1, 0, 87, 208, 0, // Skip to: 86948 /* 33613 */ MCD_OPC_Decode, 242, 27, 168, 1, // Opcode: ST1Twov2d_POST /* 33618 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 33628 /* 33623 */ MCD_OPC_Decode, 131, 29, 150, 1, // Opcode: STPDpost /* 33628 */ MCD_OPC_FilterValue, 5, 67, 208, 0, // Skip to: 86948 /* 33633 */ MCD_OPC_Decode, 134, 29, 150, 1, // Opcode: STPQpost /* 33638 */ MCD_OPC_FilterValue, 3, 191, 4, 0, // Skip to: 34858 /* 33643 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 33646 */ MCD_OPC_FilterValue, 0, 41, 2, 0, // Skip to: 34204 /* 33651 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 33654 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33676 /* 33659 */ MCD_OPC_CheckPredicate, 3, 36, 208, 0, // Skip to: 86948 /* 33664 */ MCD_OPC_CheckField, 21, 1, 0, 29, 208, 0, // Skip to: 86948 /* 33671 */ MCD_OPC_Decode, 174, 16, 161, 1, // Opcode: LD4Fourv8b_POST /* 33676 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 33698 /* 33681 */ MCD_OPC_CheckPredicate, 3, 14, 208, 0, // Skip to: 86948 /* 33686 */ MCD_OPC_CheckField, 21, 1, 0, 7, 208, 0, // Skip to: 86948 /* 33693 */ MCD_OPC_Decode, 170, 16, 161, 1, // Opcode: LD4Fourv4h_POST /* 33698 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 33720 /* 33703 */ MCD_OPC_CheckPredicate, 3, 248, 207, 0, // Skip to: 86948 /* 33708 */ MCD_OPC_CheckField, 21, 1, 0, 241, 207, 0, // Skip to: 86948 /* 33715 */ MCD_OPC_Decode, 168, 16, 161, 1, // Opcode: LD4Fourv2s_POST /* 33720 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 33742 /* 33725 */ MCD_OPC_CheckPredicate, 3, 226, 207, 0, // Skip to: 86948 /* 33730 */ MCD_OPC_CheckField, 21, 1, 0, 219, 207, 0, // Skip to: 86948 /* 33737 */ MCD_OPC_Decode, 202, 14, 161, 1, // Opcode: LD1Fourv8b_POST /* 33742 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 33764 /* 33747 */ MCD_OPC_CheckPredicate, 3, 204, 207, 0, // Skip to: 86948 /* 33752 */ MCD_OPC_CheckField, 21, 1, 0, 197, 207, 0, // Skip to: 86948 /* 33759 */ MCD_OPC_Decode, 198, 14, 161, 1, // Opcode: LD1Fourv4h_POST /* 33764 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 33786 /* 33769 */ MCD_OPC_CheckPredicate, 3, 182, 207, 0, // Skip to: 86948 /* 33774 */ MCD_OPC_CheckField, 21, 1, 0, 175, 207, 0, // Skip to: 86948 /* 33781 */ MCD_OPC_Decode, 196, 14, 161, 1, // Opcode: LD1Fourv2s_POST /* 33786 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 33808 /* 33791 */ MCD_OPC_CheckPredicate, 3, 160, 207, 0, // Skip to: 86948 /* 33796 */ MCD_OPC_CheckField, 21, 1, 0, 153, 207, 0, // Skip to: 86948 /* 33803 */ MCD_OPC_Decode, 192, 14, 161, 1, // Opcode: LD1Fourv1d_POST /* 33808 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 33830 /* 33813 */ MCD_OPC_CheckPredicate, 3, 138, 207, 0, // Skip to: 86948 /* 33818 */ MCD_OPC_CheckField, 21, 1, 0, 131, 207, 0, // Skip to: 86948 /* 33825 */ MCD_OPC_Decode, 146, 16, 162, 1, // Opcode: LD3Threev8b_POST /* 33830 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 33852 /* 33835 */ MCD_OPC_CheckPredicate, 3, 116, 207, 0, // Skip to: 86948 /* 33840 */ MCD_OPC_CheckField, 21, 1, 0, 109, 207, 0, // Skip to: 86948 /* 33847 */ MCD_OPC_Decode, 142, 16, 162, 1, // Opcode: LD3Threev4h_POST /* 33852 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 33874 /* 33857 */ MCD_OPC_CheckPredicate, 3, 94, 207, 0, // Skip to: 86948 /* 33862 */ MCD_OPC_CheckField, 21, 1, 0, 87, 207, 0, // Skip to: 86948 /* 33869 */ MCD_OPC_Decode, 140, 16, 162, 1, // Opcode: LD3Threev2s_POST /* 33874 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 33896 /* 33879 */ MCD_OPC_CheckPredicate, 3, 72, 207, 0, // Skip to: 86948 /* 33884 */ MCD_OPC_CheckField, 21, 1, 0, 65, 207, 0, // Skip to: 86948 /* 33891 */ MCD_OPC_Decode, 164, 15, 162, 1, // Opcode: LD1Threev8b_POST /* 33896 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 33918 /* 33901 */ MCD_OPC_CheckPredicate, 3, 50, 207, 0, // Skip to: 86948 /* 33906 */ MCD_OPC_CheckField, 21, 1, 0, 43, 207, 0, // Skip to: 86948 /* 33913 */ MCD_OPC_Decode, 160, 15, 162, 1, // Opcode: LD1Threev4h_POST /* 33918 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 33940 /* 33923 */ MCD_OPC_CheckPredicate, 3, 28, 207, 0, // Skip to: 86948 /* 33928 */ MCD_OPC_CheckField, 21, 1, 0, 21, 207, 0, // Skip to: 86948 /* 33935 */ MCD_OPC_Decode, 158, 15, 162, 1, // Opcode: LD1Threev2s_POST /* 33940 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 33962 /* 33945 */ MCD_OPC_CheckPredicate, 3, 6, 207, 0, // Skip to: 86948 /* 33950 */ MCD_OPC_CheckField, 21, 1, 0, 255, 206, 0, // Skip to: 86948 /* 33957 */ MCD_OPC_Decode, 154, 15, 162, 1, // Opcode: LD1Threev1d_POST /* 33962 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 33984 /* 33967 */ MCD_OPC_CheckPredicate, 3, 240, 206, 0, // Skip to: 86948 /* 33972 */ MCD_OPC_CheckField, 21, 1, 0, 233, 206, 0, // Skip to: 86948 /* 33979 */ MCD_OPC_Decode, 224, 14, 163, 1, // Opcode: LD1Onev8b_POST /* 33984 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 34006 /* 33989 */ MCD_OPC_CheckPredicate, 3, 218, 206, 0, // Skip to: 86948 /* 33994 */ MCD_OPC_CheckField, 21, 1, 0, 211, 206, 0, // Skip to: 86948 /* 34001 */ MCD_OPC_Decode, 220, 14, 163, 1, // Opcode: LD1Onev4h_POST /* 34006 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 34028 /* 34011 */ MCD_OPC_CheckPredicate, 3, 196, 206, 0, // Skip to: 86948 /* 34016 */ MCD_OPC_CheckField, 21, 1, 0, 189, 206, 0, // Skip to: 86948 /* 34023 */ MCD_OPC_Decode, 218, 14, 163, 1, // Opcode: LD1Onev2s_POST /* 34028 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 34050 /* 34033 */ MCD_OPC_CheckPredicate, 3, 174, 206, 0, // Skip to: 86948 /* 34038 */ MCD_OPC_CheckField, 21, 1, 0, 167, 206, 0, // Skip to: 86948 /* 34045 */ MCD_OPC_Decode, 214, 14, 163, 1, // Opcode: LD1Onev1d_POST /* 34050 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 34072 /* 34055 */ MCD_OPC_CheckPredicate, 3, 152, 206, 0, // Skip to: 86948 /* 34060 */ MCD_OPC_CheckField, 21, 1, 0, 145, 206, 0, // Skip to: 86948 /* 34067 */ MCD_OPC_Decode, 228, 15, 164, 1, // Opcode: LD2Twov8b_POST /* 34072 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 34094 /* 34077 */ MCD_OPC_CheckPredicate, 3, 130, 206, 0, // Skip to: 86948 /* 34082 */ MCD_OPC_CheckField, 21, 1, 0, 123, 206, 0, // Skip to: 86948 /* 34089 */ MCD_OPC_Decode, 224, 15, 164, 1, // Opcode: LD2Twov4h_POST /* 34094 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 34116 /* 34099 */ MCD_OPC_CheckPredicate, 3, 108, 206, 0, // Skip to: 86948 /* 34104 */ MCD_OPC_CheckField, 21, 1, 0, 101, 206, 0, // Skip to: 86948 /* 34111 */ MCD_OPC_Decode, 222, 15, 164, 1, // Opcode: LD2Twov2s_POST /* 34116 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 34138 /* 34121 */ MCD_OPC_CheckPredicate, 3, 86, 206, 0, // Skip to: 86948 /* 34126 */ MCD_OPC_CheckField, 21, 1, 0, 79, 206, 0, // Skip to: 86948 /* 34133 */ MCD_OPC_Decode, 180, 15, 164, 1, // Opcode: LD1Twov8b_POST /* 34138 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 34160 /* 34143 */ MCD_OPC_CheckPredicate, 3, 64, 206, 0, // Skip to: 86948 /* 34148 */ MCD_OPC_CheckField, 21, 1, 0, 57, 206, 0, // Skip to: 86948 /* 34155 */ MCD_OPC_Decode, 176, 15, 164, 1, // Opcode: LD1Twov4h_POST /* 34160 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 34182 /* 34165 */ MCD_OPC_CheckPredicate, 3, 42, 206, 0, // Skip to: 86948 /* 34170 */ MCD_OPC_CheckField, 21, 1, 0, 35, 206, 0, // Skip to: 86948 /* 34177 */ MCD_OPC_Decode, 174, 15, 164, 1, // Opcode: LD1Twov2s_POST /* 34182 */ MCD_OPC_FilterValue, 43, 25, 206, 0, // Skip to: 86948 /* 34187 */ MCD_OPC_CheckPredicate, 3, 20, 206, 0, // Skip to: 86948 /* 34192 */ MCD_OPC_CheckField, 21, 1, 0, 13, 206, 0, // Skip to: 86948 /* 34199 */ MCD_OPC_Decode, 170, 15, 164, 1, // Opcode: LD1Twov1d_POST /* 34204 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 34214 /* 34209 */ MCD_OPC_Decode, 207, 17, 150, 1, // Opcode: LDPSpost /* 34214 */ MCD_OPC_FilterValue, 2, 107, 2, 0, // Skip to: 34838 /* 34219 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 34222 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 34244 /* 34227 */ MCD_OPC_CheckPredicate, 3, 236, 205, 0, // Skip to: 86948 /* 34232 */ MCD_OPC_CheckField, 21, 1, 0, 229, 205, 0, // Skip to: 86948 /* 34239 */ MCD_OPC_Decode, 164, 16, 165, 1, // Opcode: LD4Fourv16b_POST /* 34244 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 34266 /* 34249 */ MCD_OPC_CheckPredicate, 3, 214, 205, 0, // Skip to: 86948 /* 34254 */ MCD_OPC_CheckField, 21, 1, 0, 207, 205, 0, // Skip to: 86948 /* 34261 */ MCD_OPC_Decode, 176, 16, 165, 1, // Opcode: LD4Fourv8h_POST /* 34266 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 34288 /* 34271 */ MCD_OPC_CheckPredicate, 3, 192, 205, 0, // Skip to: 86948 /* 34276 */ MCD_OPC_CheckField, 21, 1, 0, 185, 205, 0, // Skip to: 86948 /* 34283 */ MCD_OPC_Decode, 172, 16, 165, 1, // Opcode: LD4Fourv4s_POST /* 34288 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 34310 /* 34293 */ MCD_OPC_CheckPredicate, 3, 170, 205, 0, // Skip to: 86948 /* 34298 */ MCD_OPC_CheckField, 21, 1, 0, 163, 205, 0, // Skip to: 86948 /* 34305 */ MCD_OPC_Decode, 166, 16, 165, 1, // Opcode: LD4Fourv2d_POST /* 34310 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 34332 /* 34315 */ MCD_OPC_CheckPredicate, 3, 148, 205, 0, // Skip to: 86948 /* 34320 */ MCD_OPC_CheckField, 21, 1, 0, 141, 205, 0, // Skip to: 86948 /* 34327 */ MCD_OPC_Decode, 190, 14, 165, 1, // Opcode: LD1Fourv16b_POST /* 34332 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 34354 /* 34337 */ MCD_OPC_CheckPredicate, 3, 126, 205, 0, // Skip to: 86948 /* 34342 */ MCD_OPC_CheckField, 21, 1, 0, 119, 205, 0, // Skip to: 86948 /* 34349 */ MCD_OPC_Decode, 204, 14, 165, 1, // Opcode: LD1Fourv8h_POST /* 34354 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 34376 /* 34359 */ MCD_OPC_CheckPredicate, 3, 104, 205, 0, // Skip to: 86948 /* 34364 */ MCD_OPC_CheckField, 21, 1, 0, 97, 205, 0, // Skip to: 86948 /* 34371 */ MCD_OPC_Decode, 200, 14, 165, 1, // Opcode: LD1Fourv4s_POST /* 34376 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 34398 /* 34381 */ MCD_OPC_CheckPredicate, 3, 82, 205, 0, // Skip to: 86948 /* 34386 */ MCD_OPC_CheckField, 21, 1, 0, 75, 205, 0, // Skip to: 86948 /* 34393 */ MCD_OPC_Decode, 194, 14, 165, 1, // Opcode: LD1Fourv2d_POST /* 34398 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 34420 /* 34403 */ MCD_OPC_CheckPredicate, 3, 60, 205, 0, // Skip to: 86948 /* 34408 */ MCD_OPC_CheckField, 21, 1, 0, 53, 205, 0, // Skip to: 86948 /* 34415 */ MCD_OPC_Decode, 136, 16, 166, 1, // Opcode: LD3Threev16b_POST /* 34420 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 34442 /* 34425 */ MCD_OPC_CheckPredicate, 3, 38, 205, 0, // Skip to: 86948 /* 34430 */ MCD_OPC_CheckField, 21, 1, 0, 31, 205, 0, // Skip to: 86948 /* 34437 */ MCD_OPC_Decode, 148, 16, 166, 1, // Opcode: LD3Threev8h_POST /* 34442 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 34464 /* 34447 */ MCD_OPC_CheckPredicate, 3, 16, 205, 0, // Skip to: 86948 /* 34452 */ MCD_OPC_CheckField, 21, 1, 0, 9, 205, 0, // Skip to: 86948 /* 34459 */ MCD_OPC_Decode, 144, 16, 166, 1, // Opcode: LD3Threev4s_POST /* 34464 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 34486 /* 34469 */ MCD_OPC_CheckPredicate, 3, 250, 204, 0, // Skip to: 86948 /* 34474 */ MCD_OPC_CheckField, 21, 1, 0, 243, 204, 0, // Skip to: 86948 /* 34481 */ MCD_OPC_Decode, 138, 16, 166, 1, // Opcode: LD3Threev2d_POST /* 34486 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 34508 /* 34491 */ MCD_OPC_CheckPredicate, 3, 228, 204, 0, // Skip to: 86948 /* 34496 */ MCD_OPC_CheckField, 21, 1, 0, 221, 204, 0, // Skip to: 86948 /* 34503 */ MCD_OPC_Decode, 152, 15, 166, 1, // Opcode: LD1Threev16b_POST /* 34508 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 34530 /* 34513 */ MCD_OPC_CheckPredicate, 3, 206, 204, 0, // Skip to: 86948 /* 34518 */ MCD_OPC_CheckField, 21, 1, 0, 199, 204, 0, // Skip to: 86948 /* 34525 */ MCD_OPC_Decode, 166, 15, 166, 1, // Opcode: LD1Threev8h_POST /* 34530 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 34552 /* 34535 */ MCD_OPC_CheckPredicate, 3, 184, 204, 0, // Skip to: 86948 /* 34540 */ MCD_OPC_CheckField, 21, 1, 0, 177, 204, 0, // Skip to: 86948 /* 34547 */ MCD_OPC_Decode, 162, 15, 166, 1, // Opcode: LD1Threev4s_POST /* 34552 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 34574 /* 34557 */ MCD_OPC_CheckPredicate, 3, 162, 204, 0, // Skip to: 86948 /* 34562 */ MCD_OPC_CheckField, 21, 1, 0, 155, 204, 0, // Skip to: 86948 /* 34569 */ MCD_OPC_Decode, 156, 15, 166, 1, // Opcode: LD1Threev2d_POST /* 34574 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 34596 /* 34579 */ MCD_OPC_CheckPredicate, 3, 140, 204, 0, // Skip to: 86948 /* 34584 */ MCD_OPC_CheckField, 21, 1, 0, 133, 204, 0, // Skip to: 86948 /* 34591 */ MCD_OPC_Decode, 212, 14, 167, 1, // Opcode: LD1Onev16b_POST /* 34596 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 34618 /* 34601 */ MCD_OPC_CheckPredicate, 3, 118, 204, 0, // Skip to: 86948 /* 34606 */ MCD_OPC_CheckField, 21, 1, 0, 111, 204, 0, // Skip to: 86948 /* 34613 */ MCD_OPC_Decode, 226, 14, 167, 1, // Opcode: LD1Onev8h_POST /* 34618 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 34640 /* 34623 */ MCD_OPC_CheckPredicate, 3, 96, 204, 0, // Skip to: 86948 /* 34628 */ MCD_OPC_CheckField, 21, 1, 0, 89, 204, 0, // Skip to: 86948 /* 34635 */ MCD_OPC_Decode, 222, 14, 167, 1, // Opcode: LD1Onev4s_POST /* 34640 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 34662 /* 34645 */ MCD_OPC_CheckPredicate, 3, 74, 204, 0, // Skip to: 86948 /* 34650 */ MCD_OPC_CheckField, 21, 1, 0, 67, 204, 0, // Skip to: 86948 /* 34657 */ MCD_OPC_Decode, 216, 14, 167, 1, // Opcode: LD1Onev2d_POST /* 34662 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 34684 /* 34667 */ MCD_OPC_CheckPredicate, 3, 52, 204, 0, // Skip to: 86948 /* 34672 */ MCD_OPC_CheckField, 21, 1, 0, 45, 204, 0, // Skip to: 86948 /* 34679 */ MCD_OPC_Decode, 218, 15, 168, 1, // Opcode: LD2Twov16b_POST /* 34684 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 34706 /* 34689 */ MCD_OPC_CheckPredicate, 3, 30, 204, 0, // Skip to: 86948 /* 34694 */ MCD_OPC_CheckField, 21, 1, 0, 23, 204, 0, // Skip to: 86948 /* 34701 */ MCD_OPC_Decode, 230, 15, 168, 1, // Opcode: LD2Twov8h_POST /* 34706 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 34728 /* 34711 */ MCD_OPC_CheckPredicate, 3, 8, 204, 0, // Skip to: 86948 /* 34716 */ MCD_OPC_CheckField, 21, 1, 0, 1, 204, 0, // Skip to: 86948 /* 34723 */ MCD_OPC_Decode, 226, 15, 168, 1, // Opcode: LD2Twov4s_POST /* 34728 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 34750 /* 34733 */ MCD_OPC_CheckPredicate, 3, 242, 203, 0, // Skip to: 86948 /* 34738 */ MCD_OPC_CheckField, 21, 1, 0, 235, 203, 0, // Skip to: 86948 /* 34745 */ MCD_OPC_Decode, 220, 15, 168, 1, // Opcode: LD2Twov2d_POST /* 34750 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 34772 /* 34755 */ MCD_OPC_CheckPredicate, 3, 220, 203, 0, // Skip to: 86948 /* 34760 */ MCD_OPC_CheckField, 21, 1, 0, 213, 203, 0, // Skip to: 86948 /* 34767 */ MCD_OPC_Decode, 168, 15, 168, 1, // Opcode: LD1Twov16b_POST /* 34772 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 34794 /* 34777 */ MCD_OPC_CheckPredicate, 3, 198, 203, 0, // Skip to: 86948 /* 34782 */ MCD_OPC_CheckField, 21, 1, 0, 191, 203, 0, // Skip to: 86948 /* 34789 */ MCD_OPC_Decode, 182, 15, 168, 1, // Opcode: LD1Twov8h_POST /* 34794 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 34816 /* 34799 */ MCD_OPC_CheckPredicate, 3, 176, 203, 0, // Skip to: 86948 /* 34804 */ MCD_OPC_CheckField, 21, 1, 0, 169, 203, 0, // Skip to: 86948 /* 34811 */ MCD_OPC_Decode, 178, 15, 168, 1, // Opcode: LD1Twov4s_POST /* 34816 */ MCD_OPC_FilterValue, 43, 159, 203, 0, // Skip to: 86948 /* 34821 */ MCD_OPC_CheckPredicate, 3, 154, 203, 0, // Skip to: 86948 /* 34826 */ MCD_OPC_CheckField, 21, 1, 0, 147, 203, 0, // Skip to: 86948 /* 34833 */ MCD_OPC_Decode, 172, 15, 168, 1, // Opcode: LD1Twov2d_POST /* 34838 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 34848 /* 34843 */ MCD_OPC_Decode, 198, 17, 150, 1, // Opcode: LDPDpost /* 34848 */ MCD_OPC_FilterValue, 5, 127, 203, 0, // Skip to: 86948 /* 34853 */ MCD_OPC_Decode, 201, 17, 150, 1, // Opcode: LDPQpost /* 34858 */ MCD_OPC_FilterValue, 4, 239, 1, 0, // Skip to: 35358 /* 34863 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 34866 */ MCD_OPC_FilterValue, 0, 193, 1, 0, // Skip to: 35320 /* 34871 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... /* 34874 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 34896 /* 34879 */ MCD_OPC_CheckPredicate, 3, 96, 203, 0, // Skip to: 86948 /* 34884 */ MCD_OPC_CheckField, 31, 1, 0, 89, 203, 0, // Skip to: 86948 /* 34891 */ MCD_OPC_Decode, 135, 28, 169, 1, // Opcode: ST1i8 /* 34896 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 34918 /* 34901 */ MCD_OPC_CheckPredicate, 3, 74, 203, 0, // Skip to: 86948 /* 34906 */ MCD_OPC_CheckField, 31, 1, 0, 67, 203, 0, // Skip to: 86948 /* 34913 */ MCD_OPC_Decode, 195, 28, 170, 1, // Opcode: ST3i8 /* 34918 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 34947 /* 34923 */ MCD_OPC_CheckPredicate, 3, 52, 203, 0, // Skip to: 86948 /* 34928 */ MCD_OPC_CheckField, 31, 1, 0, 45, 203, 0, // Skip to: 86948 /* 34935 */ MCD_OPC_CheckField, 10, 1, 0, 38, 203, 0, // Skip to: 86948 /* 34942 */ MCD_OPC_Decode, 129, 28, 171, 1, // Opcode: ST1i16 /* 34947 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 34976 /* 34952 */ MCD_OPC_CheckPredicate, 3, 23, 203, 0, // Skip to: 86948 /* 34957 */ MCD_OPC_CheckField, 31, 1, 0, 16, 203, 0, // Skip to: 86948 /* 34964 */ MCD_OPC_CheckField, 10, 1, 0, 9, 203, 0, // Skip to: 86948 /* 34971 */ MCD_OPC_Decode, 189, 28, 172, 1, // Opcode: ST3i16 /* 34976 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 35035 /* 34981 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 34984 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35006 /* 34989 */ MCD_OPC_CheckPredicate, 3, 242, 202, 0, // Skip to: 86948 /* 34994 */ MCD_OPC_CheckField, 31, 1, 0, 235, 202, 0, // Skip to: 86948 /* 35001 */ MCD_OPC_Decode, 131, 28, 173, 1, // Opcode: ST1i32 /* 35006 */ MCD_OPC_FilterValue, 1, 225, 202, 0, // Skip to: 86948 /* 35011 */ MCD_OPC_CheckPredicate, 3, 220, 202, 0, // Skip to: 86948 /* 35016 */ MCD_OPC_CheckField, 31, 1, 0, 213, 202, 0, // Skip to: 86948 /* 35023 */ MCD_OPC_CheckField, 12, 1, 0, 206, 202, 0, // Skip to: 86948 /* 35030 */ MCD_OPC_Decode, 133, 28, 174, 1, // Opcode: ST1i64 /* 35035 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 35094 /* 35040 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 35043 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35065 /* 35048 */ MCD_OPC_CheckPredicate, 3, 183, 202, 0, // Skip to: 86948 /* 35053 */ MCD_OPC_CheckField, 31, 1, 0, 176, 202, 0, // Skip to: 86948 /* 35060 */ MCD_OPC_Decode, 191, 28, 175, 1, // Opcode: ST3i32 /* 35065 */ MCD_OPC_FilterValue, 1, 166, 202, 0, // Skip to: 86948 /* 35070 */ MCD_OPC_CheckPredicate, 3, 161, 202, 0, // Skip to: 86948 /* 35075 */ MCD_OPC_CheckField, 31, 1, 0, 154, 202, 0, // Skip to: 86948 /* 35082 */ MCD_OPC_CheckField, 12, 1, 0, 147, 202, 0, // Skip to: 86948 /* 35089 */ MCD_OPC_Decode, 193, 28, 176, 1, // Opcode: ST3i64 /* 35094 */ MCD_OPC_FilterValue, 128, 2, 17, 0, 0, // Skip to: 35117 /* 35100 */ MCD_OPC_CheckPredicate, 3, 131, 202, 0, // Skip to: 86948 /* 35105 */ MCD_OPC_CheckField, 31, 1, 0, 124, 202, 0, // Skip to: 86948 /* 35112 */ MCD_OPC_Decode, 165, 28, 177, 1, // Opcode: ST2i8 /* 35117 */ MCD_OPC_FilterValue, 129, 2, 17, 0, 0, // Skip to: 35140 /* 35123 */ MCD_OPC_CheckPredicate, 3, 108, 202, 0, // Skip to: 86948 /* 35128 */ MCD_OPC_CheckField, 31, 1, 0, 101, 202, 0, // Skip to: 86948 /* 35135 */ MCD_OPC_Decode, 225, 28, 178, 1, // Opcode: ST4i8 /* 35140 */ MCD_OPC_FilterValue, 130, 2, 24, 0, 0, // Skip to: 35170 /* 35146 */ MCD_OPC_CheckPredicate, 3, 85, 202, 0, // Skip to: 86948 /* 35151 */ MCD_OPC_CheckField, 31, 1, 0, 78, 202, 0, // Skip to: 86948 /* 35158 */ MCD_OPC_CheckField, 10, 1, 0, 71, 202, 0, // Skip to: 86948 /* 35165 */ MCD_OPC_Decode, 159, 28, 179, 1, // Opcode: ST2i16 /* 35170 */ MCD_OPC_FilterValue, 131, 2, 24, 0, 0, // Skip to: 35200 /* 35176 */ MCD_OPC_CheckPredicate, 3, 55, 202, 0, // Skip to: 86948 /* 35181 */ MCD_OPC_CheckField, 31, 1, 0, 48, 202, 0, // Skip to: 86948 /* 35188 */ MCD_OPC_CheckField, 10, 1, 0, 41, 202, 0, // Skip to: 86948 /* 35195 */ MCD_OPC_Decode, 219, 28, 180, 1, // Opcode: ST4i16 /* 35200 */ MCD_OPC_FilterValue, 132, 2, 54, 0, 0, // Skip to: 35260 /* 35206 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 35209 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35231 /* 35214 */ MCD_OPC_CheckPredicate, 3, 17, 202, 0, // Skip to: 86948 /* 35219 */ MCD_OPC_CheckField, 31, 1, 0, 10, 202, 0, // Skip to: 86948 /* 35226 */ MCD_OPC_Decode, 161, 28, 181, 1, // Opcode: ST2i32 /* 35231 */ MCD_OPC_FilterValue, 1, 0, 202, 0, // Skip to: 86948 /* 35236 */ MCD_OPC_CheckPredicate, 3, 251, 201, 0, // Skip to: 86948 /* 35241 */ MCD_OPC_CheckField, 31, 1, 0, 244, 201, 0, // Skip to: 86948 /* 35248 */ MCD_OPC_CheckField, 12, 1, 0, 237, 201, 0, // Skip to: 86948 /* 35255 */ MCD_OPC_Decode, 163, 28, 182, 1, // Opcode: ST2i64 /* 35260 */ MCD_OPC_FilterValue, 133, 2, 226, 201, 0, // Skip to: 86948 /* 35266 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 35269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35291 /* 35274 */ MCD_OPC_CheckPredicate, 3, 213, 201, 0, // Skip to: 86948 /* 35279 */ MCD_OPC_CheckField, 31, 1, 0, 206, 201, 0, // Skip to: 86948 /* 35286 */ MCD_OPC_Decode, 221, 28, 183, 1, // Opcode: ST4i32 /* 35291 */ MCD_OPC_FilterValue, 1, 196, 201, 0, // Skip to: 86948 /* 35296 */ MCD_OPC_CheckPredicate, 3, 191, 201, 0, // Skip to: 86948 /* 35301 */ MCD_OPC_CheckField, 31, 1, 0, 184, 201, 0, // Skip to: 86948 /* 35308 */ MCD_OPC_CheckField, 12, 1, 0, 177, 201, 0, // Skip to: 86948 /* 35315 */ MCD_OPC_Decode, 223, 28, 184, 1, // Opcode: ST4i64 /* 35320 */ MCD_OPC_FilterValue, 1, 167, 201, 0, // Skip to: 86948 /* 35325 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35328 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 35338 /* 35333 */ MCD_OPC_Decode, 136, 29, 150, 1, // Opcode: STPSi /* 35338 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 35348 /* 35343 */ MCD_OPC_Decode, 130, 29, 150, 1, // Opcode: STPDi /* 35348 */ MCD_OPC_FilterValue, 2, 139, 201, 0, // Skip to: 86948 /* 35353 */ MCD_OPC_Decode, 133, 29, 150, 1, // Opcode: STPQi /* 35358 */ MCD_OPC_FilterValue, 5, 113, 4, 0, // Skip to: 36500 /* 35363 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 35366 */ MCD_OPC_FilterValue, 0, 67, 4, 0, // Skip to: 36462 /* 35371 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... /* 35374 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35396 /* 35379 */ MCD_OPC_CheckPredicate, 3, 108, 201, 0, // Skip to: 86948 /* 35384 */ MCD_OPC_CheckField, 31, 1, 0, 101, 201, 0, // Skip to: 86948 /* 35391 */ MCD_OPC_Decode, 193, 15, 185, 1, // Opcode: LD1i8 /* 35396 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 35418 /* 35401 */ MCD_OPC_CheckPredicate, 3, 86, 201, 0, // Skip to: 86948 /* 35406 */ MCD_OPC_CheckField, 31, 1, 0, 79, 201, 0, // Skip to: 86948 /* 35413 */ MCD_OPC_Decode, 157, 16, 186, 1, // Opcode: LD3i8 /* 35418 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 35447 /* 35423 */ MCD_OPC_CheckPredicate, 3, 64, 201, 0, // Skip to: 86948 /* 35428 */ MCD_OPC_CheckField, 31, 1, 0, 57, 201, 0, // Skip to: 86948 /* 35435 */ MCD_OPC_CheckField, 10, 1, 0, 50, 201, 0, // Skip to: 86948 /* 35442 */ MCD_OPC_Decode, 187, 15, 187, 1, // Opcode: LD1i16 /* 35447 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 35476 /* 35452 */ MCD_OPC_CheckPredicate, 3, 35, 201, 0, // Skip to: 86948 /* 35457 */ MCD_OPC_CheckField, 31, 1, 0, 28, 201, 0, // Skip to: 86948 /* 35464 */ MCD_OPC_CheckField, 10, 1, 0, 21, 201, 0, // Skip to: 86948 /* 35471 */ MCD_OPC_Decode, 151, 16, 188, 1, // Opcode: LD3i16 /* 35476 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 35535 /* 35481 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 35484 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35506 /* 35489 */ MCD_OPC_CheckPredicate, 3, 254, 200, 0, // Skip to: 86948 /* 35494 */ MCD_OPC_CheckField, 31, 1, 0, 247, 200, 0, // Skip to: 86948 /* 35501 */ MCD_OPC_Decode, 189, 15, 189, 1, // Opcode: LD1i32 /* 35506 */ MCD_OPC_FilterValue, 1, 237, 200, 0, // Skip to: 86948 /* 35511 */ MCD_OPC_CheckPredicate, 3, 232, 200, 0, // Skip to: 86948 /* 35516 */ MCD_OPC_CheckField, 31, 1, 0, 225, 200, 0, // Skip to: 86948 /* 35523 */ MCD_OPC_CheckField, 12, 1, 0, 218, 200, 0, // Skip to: 86948 /* 35530 */ MCD_OPC_Decode, 191, 15, 190, 1, // Opcode: LD1i64 /* 35535 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 35594 /* 35540 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 35543 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35565 /* 35548 */ MCD_OPC_CheckPredicate, 3, 195, 200, 0, // Skip to: 86948 /* 35553 */ MCD_OPC_CheckField, 31, 1, 0, 188, 200, 0, // Skip to: 86948 /* 35560 */ MCD_OPC_Decode, 153, 16, 191, 1, // Opcode: LD3i32 /* 35565 */ MCD_OPC_FilterValue, 1, 178, 200, 0, // Skip to: 86948 /* 35570 */ MCD_OPC_CheckPredicate, 3, 173, 200, 0, // Skip to: 86948 /* 35575 */ MCD_OPC_CheckField, 31, 1, 0, 166, 200, 0, // Skip to: 86948 /* 35582 */ MCD_OPC_CheckField, 12, 1, 0, 159, 200, 0, // Skip to: 86948 /* 35589 */ MCD_OPC_Decode, 155, 16, 192, 1, // Opcode: LD3i64 /* 35594 */ MCD_OPC_FilterValue, 6, 155, 0, 0, // Skip to: 35754 /* 35599 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 35602 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 35640 /* 35607 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35610 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35625 /* 35615 */ MCD_OPC_CheckPredicate, 3, 128, 200, 0, // Skip to: 86948 /* 35620 */ MCD_OPC_Decode, 135, 15, 155, 1, // Opcode: LD1Rv8b /* 35625 */ MCD_OPC_FilterValue, 1, 118, 200, 0, // Skip to: 86948 /* 35630 */ MCD_OPC_CheckPredicate, 3, 113, 200, 0, // Skip to: 86948 /* 35635 */ MCD_OPC_Decode, 251, 14, 159, 1, // Opcode: LD1Rv16b /* 35640 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 35678 /* 35645 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35648 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35663 /* 35653 */ MCD_OPC_CheckPredicate, 3, 90, 200, 0, // Skip to: 86948 /* 35658 */ MCD_OPC_Decode, 131, 15, 155, 1, // Opcode: LD1Rv4h /* 35663 */ MCD_OPC_FilterValue, 1, 80, 200, 0, // Skip to: 86948 /* 35668 */ MCD_OPC_CheckPredicate, 3, 75, 200, 0, // Skip to: 86948 /* 35673 */ MCD_OPC_Decode, 137, 15, 159, 1, // Opcode: LD1Rv8h /* 35678 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 35716 /* 35683 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35686 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35701 /* 35691 */ MCD_OPC_CheckPredicate, 3, 52, 200, 0, // Skip to: 86948 /* 35696 */ MCD_OPC_Decode, 129, 15, 155, 1, // Opcode: LD1Rv2s /* 35701 */ MCD_OPC_FilterValue, 1, 42, 200, 0, // Skip to: 86948 /* 35706 */ MCD_OPC_CheckPredicate, 3, 37, 200, 0, // Skip to: 86948 /* 35711 */ MCD_OPC_Decode, 133, 15, 159, 1, // Opcode: LD1Rv4s /* 35716 */ MCD_OPC_FilterValue, 3, 27, 200, 0, // Skip to: 86948 /* 35721 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35724 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35739 /* 35729 */ MCD_OPC_CheckPredicate, 3, 14, 200, 0, // Skip to: 86948 /* 35734 */ MCD_OPC_Decode, 253, 14, 155, 1, // Opcode: LD1Rv1d /* 35739 */ MCD_OPC_FilterValue, 1, 4, 200, 0, // Skip to: 86948 /* 35744 */ MCD_OPC_CheckPredicate, 3, 255, 199, 0, // Skip to: 86948 /* 35749 */ MCD_OPC_Decode, 255, 14, 159, 1, // Opcode: LD1Rv2d /* 35754 */ MCD_OPC_FilterValue, 7, 155, 0, 0, // Skip to: 35914 /* 35759 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 35762 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 35800 /* 35767 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35770 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35785 /* 35775 */ MCD_OPC_CheckPredicate, 3, 224, 199, 0, // Skip to: 86948 /* 35780 */ MCD_OPC_Decode, 131, 16, 154, 1, // Opcode: LD3Rv8b /* 35785 */ MCD_OPC_FilterValue, 1, 214, 199, 0, // Skip to: 86948 /* 35790 */ MCD_OPC_CheckPredicate, 3, 209, 199, 0, // Skip to: 86948 /* 35795 */ MCD_OPC_Decode, 247, 15, 158, 1, // Opcode: LD3Rv16b /* 35800 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 35838 /* 35805 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35823 /* 35813 */ MCD_OPC_CheckPredicate, 3, 186, 199, 0, // Skip to: 86948 /* 35818 */ MCD_OPC_Decode, 255, 15, 154, 1, // Opcode: LD3Rv4h /* 35823 */ MCD_OPC_FilterValue, 1, 176, 199, 0, // Skip to: 86948 /* 35828 */ MCD_OPC_CheckPredicate, 3, 171, 199, 0, // Skip to: 86948 /* 35833 */ MCD_OPC_Decode, 133, 16, 158, 1, // Opcode: LD3Rv8h /* 35838 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 35876 /* 35843 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35846 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35861 /* 35851 */ MCD_OPC_CheckPredicate, 3, 148, 199, 0, // Skip to: 86948 /* 35856 */ MCD_OPC_Decode, 253, 15, 154, 1, // Opcode: LD3Rv2s /* 35861 */ MCD_OPC_FilterValue, 1, 138, 199, 0, // Skip to: 86948 /* 35866 */ MCD_OPC_CheckPredicate, 3, 133, 199, 0, // Skip to: 86948 /* 35871 */ MCD_OPC_Decode, 129, 16, 158, 1, // Opcode: LD3Rv4s /* 35876 */ MCD_OPC_FilterValue, 3, 123, 199, 0, // Skip to: 86948 /* 35881 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 35884 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35899 /* 35889 */ MCD_OPC_CheckPredicate, 3, 110, 199, 0, // Skip to: 86948 /* 35894 */ MCD_OPC_Decode, 249, 15, 154, 1, // Opcode: LD3Rv1d /* 35899 */ MCD_OPC_FilterValue, 1, 100, 199, 0, // Skip to: 86948 /* 35904 */ MCD_OPC_CheckPredicate, 3, 95, 199, 0, // Skip to: 86948 /* 35909 */ MCD_OPC_Decode, 251, 15, 158, 1, // Opcode: LD3Rv2d /* 35914 */ MCD_OPC_FilterValue, 128, 2, 17, 0, 0, // Skip to: 35937 /* 35920 */ MCD_OPC_CheckPredicate, 3, 79, 199, 0, // Skip to: 86948 /* 35925 */ MCD_OPC_CheckField, 31, 1, 0, 72, 199, 0, // Skip to: 86948 /* 35932 */ MCD_OPC_Decode, 239, 15, 193, 1, // Opcode: LD2i8 /* 35937 */ MCD_OPC_FilterValue, 129, 2, 17, 0, 0, // Skip to: 35960 /* 35943 */ MCD_OPC_CheckPredicate, 3, 56, 199, 0, // Skip to: 86948 /* 35948 */ MCD_OPC_CheckField, 31, 1, 0, 49, 199, 0, // Skip to: 86948 /* 35955 */ MCD_OPC_Decode, 203, 16, 194, 1, // Opcode: LD4i8 /* 35960 */ MCD_OPC_FilterValue, 130, 2, 24, 0, 0, // Skip to: 35990 /* 35966 */ MCD_OPC_CheckPredicate, 3, 33, 199, 0, // Skip to: 86948 /* 35971 */ MCD_OPC_CheckField, 31, 1, 0, 26, 199, 0, // Skip to: 86948 /* 35978 */ MCD_OPC_CheckField, 10, 1, 0, 19, 199, 0, // Skip to: 86948 /* 35985 */ MCD_OPC_Decode, 233, 15, 195, 1, // Opcode: LD2i16 /* 35990 */ MCD_OPC_FilterValue, 131, 2, 24, 0, 0, // Skip to: 36020 /* 35996 */ MCD_OPC_CheckPredicate, 3, 3, 199, 0, // Skip to: 86948 /* 36001 */ MCD_OPC_CheckField, 31, 1, 0, 252, 198, 0, // Skip to: 86948 /* 36008 */ MCD_OPC_CheckField, 10, 1, 0, 245, 198, 0, // Skip to: 86948 /* 36015 */ MCD_OPC_Decode, 197, 16, 196, 1, // Opcode: LD4i16 /* 36020 */ MCD_OPC_FilterValue, 132, 2, 54, 0, 0, // Skip to: 36080 /* 36026 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 36029 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36051 /* 36034 */ MCD_OPC_CheckPredicate, 3, 221, 198, 0, // Skip to: 86948 /* 36039 */ MCD_OPC_CheckField, 31, 1, 0, 214, 198, 0, // Skip to: 86948 /* 36046 */ MCD_OPC_Decode, 235, 15, 197, 1, // Opcode: LD2i32 /* 36051 */ MCD_OPC_FilterValue, 1, 204, 198, 0, // Skip to: 86948 /* 36056 */ MCD_OPC_CheckPredicate, 3, 199, 198, 0, // Skip to: 86948 /* 36061 */ MCD_OPC_CheckField, 31, 1, 0, 192, 198, 0, // Skip to: 86948 /* 36068 */ MCD_OPC_CheckField, 12, 1, 0, 185, 198, 0, // Skip to: 86948 /* 36075 */ MCD_OPC_Decode, 237, 15, 198, 1, // Opcode: LD2i64 /* 36080 */ MCD_OPC_FilterValue, 133, 2, 54, 0, 0, // Skip to: 36140 /* 36086 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 36089 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36111 /* 36094 */ MCD_OPC_CheckPredicate, 3, 161, 198, 0, // Skip to: 86948 /* 36099 */ MCD_OPC_CheckField, 31, 1, 0, 154, 198, 0, // Skip to: 86948 /* 36106 */ MCD_OPC_Decode, 199, 16, 199, 1, // Opcode: LD4i32 /* 36111 */ MCD_OPC_FilterValue, 1, 144, 198, 0, // Skip to: 86948 /* 36116 */ MCD_OPC_CheckPredicate, 3, 139, 198, 0, // Skip to: 86948 /* 36121 */ MCD_OPC_CheckField, 31, 1, 0, 132, 198, 0, // Skip to: 86948 /* 36128 */ MCD_OPC_CheckField, 12, 1, 0, 125, 198, 0, // Skip to: 86948 /* 36135 */ MCD_OPC_Decode, 201, 16, 200, 1, // Opcode: LD4i64 /* 36140 */ MCD_OPC_FilterValue, 134, 2, 155, 0, 0, // Skip to: 36301 /* 36146 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 36149 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 36187 /* 36154 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36157 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36172 /* 36162 */ MCD_OPC_CheckPredicate, 3, 93, 198, 0, // Skip to: 86948 /* 36167 */ MCD_OPC_Decode, 213, 15, 156, 1, // Opcode: LD2Rv8b /* 36172 */ MCD_OPC_FilterValue, 1, 83, 198, 0, // Skip to: 86948 /* 36177 */ MCD_OPC_CheckPredicate, 3, 78, 198, 0, // Skip to: 86948 /* 36182 */ MCD_OPC_Decode, 201, 15, 160, 1, // Opcode: LD2Rv16b /* 36187 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 36225 /* 36192 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36195 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36210 /* 36200 */ MCD_OPC_CheckPredicate, 3, 55, 198, 0, // Skip to: 86948 /* 36205 */ MCD_OPC_Decode, 209, 15, 156, 1, // Opcode: LD2Rv4h /* 36210 */ MCD_OPC_FilterValue, 1, 45, 198, 0, // Skip to: 86948 /* 36215 */ MCD_OPC_CheckPredicate, 3, 40, 198, 0, // Skip to: 86948 /* 36220 */ MCD_OPC_Decode, 215, 15, 160, 1, // Opcode: LD2Rv8h /* 36225 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 36263 /* 36230 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36233 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36248 /* 36238 */ MCD_OPC_CheckPredicate, 3, 17, 198, 0, // Skip to: 86948 /* 36243 */ MCD_OPC_Decode, 207, 15, 156, 1, // Opcode: LD2Rv2s /* 36248 */ MCD_OPC_FilterValue, 1, 7, 198, 0, // Skip to: 86948 /* 36253 */ MCD_OPC_CheckPredicate, 3, 2, 198, 0, // Skip to: 86948 /* 36258 */ MCD_OPC_Decode, 211, 15, 160, 1, // Opcode: LD2Rv4s /* 36263 */ MCD_OPC_FilterValue, 3, 248, 197, 0, // Skip to: 86948 /* 36268 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36286 /* 36276 */ MCD_OPC_CheckPredicate, 3, 235, 197, 0, // Skip to: 86948 /* 36281 */ MCD_OPC_Decode, 203, 15, 156, 1, // Opcode: LD2Rv1d /* 36286 */ MCD_OPC_FilterValue, 1, 225, 197, 0, // Skip to: 86948 /* 36291 */ MCD_OPC_CheckPredicate, 3, 220, 197, 0, // Skip to: 86948 /* 36296 */ MCD_OPC_Decode, 205, 15, 160, 1, // Opcode: LD2Rv2d /* 36301 */ MCD_OPC_FilterValue, 135, 2, 209, 197, 0, // Skip to: 86948 /* 36307 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 36310 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 36348 /* 36315 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36318 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36333 /* 36323 */ MCD_OPC_CheckPredicate, 3, 188, 197, 0, // Skip to: 86948 /* 36328 */ MCD_OPC_Decode, 191, 16, 153, 1, // Opcode: LD4Rv8b /* 36333 */ MCD_OPC_FilterValue, 1, 178, 197, 0, // Skip to: 86948 /* 36338 */ MCD_OPC_CheckPredicate, 3, 173, 197, 0, // Skip to: 86948 /* 36343 */ MCD_OPC_Decode, 179, 16, 157, 1, // Opcode: LD4Rv16b /* 36348 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 36386 /* 36353 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36356 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36371 /* 36361 */ MCD_OPC_CheckPredicate, 3, 150, 197, 0, // Skip to: 86948 /* 36366 */ MCD_OPC_Decode, 187, 16, 153, 1, // Opcode: LD4Rv4h /* 36371 */ MCD_OPC_FilterValue, 1, 140, 197, 0, // Skip to: 86948 /* 36376 */ MCD_OPC_CheckPredicate, 3, 135, 197, 0, // Skip to: 86948 /* 36381 */ MCD_OPC_Decode, 193, 16, 157, 1, // Opcode: LD4Rv8h /* 36386 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 36424 /* 36391 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36394 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36409 /* 36399 */ MCD_OPC_CheckPredicate, 3, 112, 197, 0, // Skip to: 86948 /* 36404 */ MCD_OPC_Decode, 185, 16, 153, 1, // Opcode: LD4Rv2s /* 36409 */ MCD_OPC_FilterValue, 1, 102, 197, 0, // Skip to: 86948 /* 36414 */ MCD_OPC_CheckPredicate, 3, 97, 197, 0, // Skip to: 86948 /* 36419 */ MCD_OPC_Decode, 189, 16, 157, 1, // Opcode: LD4Rv4s /* 36424 */ MCD_OPC_FilterValue, 3, 87, 197, 0, // Skip to: 86948 /* 36429 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36432 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36447 /* 36437 */ MCD_OPC_CheckPredicate, 3, 74, 197, 0, // Skip to: 86948 /* 36442 */ MCD_OPC_Decode, 181, 16, 153, 1, // Opcode: LD4Rv1d /* 36447 */ MCD_OPC_FilterValue, 1, 64, 197, 0, // Skip to: 86948 /* 36452 */ MCD_OPC_CheckPredicate, 3, 59, 197, 0, // Skip to: 86948 /* 36457 */ MCD_OPC_Decode, 183, 16, 157, 1, // Opcode: LD4Rv2d /* 36462 */ MCD_OPC_FilterValue, 1, 49, 197, 0, // Skip to: 86948 /* 36467 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 36470 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 36480 /* 36475 */ MCD_OPC_Decode, 206, 17, 150, 1, // Opcode: LDPSi /* 36480 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 36490 /* 36485 */ MCD_OPC_Decode, 197, 17, 150, 1, // Opcode: LDPDi /* 36490 */ MCD_OPC_FilterValue, 2, 21, 197, 0, // Skip to: 86948 /* 36495 */ MCD_OPC_Decode, 200, 17, 150, 1, // Opcode: LDPQi /* 36500 */ MCD_OPC_FilterValue, 6, 25, 2, 0, // Skip to: 37042 /* 36505 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 36508 */ MCD_OPC_FilterValue, 0, 235, 1, 0, // Skip to: 37004 /* 36513 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 36516 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36568 /* 36521 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36524 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36546 /* 36529 */ MCD_OPC_CheckPredicate, 3, 238, 196, 0, // Skip to: 86948 /* 36534 */ MCD_OPC_CheckField, 31, 1, 0, 231, 196, 0, // Skip to: 86948 /* 36541 */ MCD_OPC_Decode, 136, 28, 201, 1, // Opcode: ST1i8_POST /* 36546 */ MCD_OPC_FilterValue, 1, 221, 196, 0, // Skip to: 86948 /* 36551 */ MCD_OPC_CheckPredicate, 3, 216, 196, 0, // Skip to: 86948 /* 36556 */ MCD_OPC_CheckField, 31, 1, 0, 209, 196, 0, // Skip to: 86948 /* 36563 */ MCD_OPC_Decode, 166, 28, 202, 1, // Opcode: ST2i8_POST /* 36568 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 36620 /* 36573 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36576 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36598 /* 36581 */ MCD_OPC_CheckPredicate, 3, 186, 196, 0, // Skip to: 86948 /* 36586 */ MCD_OPC_CheckField, 31, 1, 0, 179, 196, 0, // Skip to: 86948 /* 36593 */ MCD_OPC_Decode, 196, 28, 203, 1, // Opcode: ST3i8_POST /* 36598 */ MCD_OPC_FilterValue, 1, 169, 196, 0, // Skip to: 86948 /* 36603 */ MCD_OPC_CheckPredicate, 3, 164, 196, 0, // Skip to: 86948 /* 36608 */ MCD_OPC_CheckField, 31, 1, 0, 157, 196, 0, // Skip to: 86948 /* 36615 */ MCD_OPC_Decode, 226, 28, 204, 1, // Opcode: ST4i8_POST /* 36620 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 36686 /* 36625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36628 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36657 /* 36633 */ MCD_OPC_CheckPredicate, 3, 134, 196, 0, // Skip to: 86948 /* 36638 */ MCD_OPC_CheckField, 31, 1, 0, 127, 196, 0, // Skip to: 86948 /* 36645 */ MCD_OPC_CheckField, 10, 1, 0, 120, 196, 0, // Skip to: 86948 /* 36652 */ MCD_OPC_Decode, 130, 28, 205, 1, // Opcode: ST1i16_POST /* 36657 */ MCD_OPC_FilterValue, 1, 110, 196, 0, // Skip to: 86948 /* 36662 */ MCD_OPC_CheckPredicate, 3, 105, 196, 0, // Skip to: 86948 /* 36667 */ MCD_OPC_CheckField, 31, 1, 0, 98, 196, 0, // Skip to: 86948 /* 36674 */ MCD_OPC_CheckField, 10, 1, 0, 91, 196, 0, // Skip to: 86948 /* 36681 */ MCD_OPC_Decode, 160, 28, 206, 1, // Opcode: ST2i16_POST /* 36686 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 36752 /* 36691 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36694 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36723 /* 36699 */ MCD_OPC_CheckPredicate, 3, 68, 196, 0, // Skip to: 86948 /* 36704 */ MCD_OPC_CheckField, 31, 1, 0, 61, 196, 0, // Skip to: 86948 /* 36711 */ MCD_OPC_CheckField, 10, 1, 0, 54, 196, 0, // Skip to: 86948 /* 36718 */ MCD_OPC_Decode, 190, 28, 207, 1, // Opcode: ST3i16_POST /* 36723 */ MCD_OPC_FilterValue, 1, 44, 196, 0, // Skip to: 86948 /* 36728 */ MCD_OPC_CheckPredicate, 3, 39, 196, 0, // Skip to: 86948 /* 36733 */ MCD_OPC_CheckField, 31, 1, 0, 32, 196, 0, // Skip to: 86948 /* 36740 */ MCD_OPC_CheckField, 10, 1, 0, 25, 196, 0, // Skip to: 86948 /* 36747 */ MCD_OPC_Decode, 220, 28, 208, 1, // Opcode: ST4i16_POST /* 36752 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 36878 /* 36757 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 36760 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36812 /* 36765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36768 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36790 /* 36773 */ MCD_OPC_CheckPredicate, 3, 250, 195, 0, // Skip to: 86948 /* 36778 */ MCD_OPC_CheckField, 31, 1, 0, 243, 195, 0, // Skip to: 86948 /* 36785 */ MCD_OPC_Decode, 132, 28, 209, 1, // Opcode: ST1i32_POST /* 36790 */ MCD_OPC_FilterValue, 1, 233, 195, 0, // Skip to: 86948 /* 36795 */ MCD_OPC_CheckPredicate, 3, 228, 195, 0, // Skip to: 86948 /* 36800 */ MCD_OPC_CheckField, 31, 1, 0, 221, 195, 0, // Skip to: 86948 /* 36807 */ MCD_OPC_Decode, 162, 28, 210, 1, // Opcode: ST2i32_POST /* 36812 */ MCD_OPC_FilterValue, 1, 211, 195, 0, // Skip to: 86948 /* 36817 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36820 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36849 /* 36825 */ MCD_OPC_CheckPredicate, 3, 198, 195, 0, // Skip to: 86948 /* 36830 */ MCD_OPC_CheckField, 31, 1, 0, 191, 195, 0, // Skip to: 86948 /* 36837 */ MCD_OPC_CheckField, 12, 1, 0, 184, 195, 0, // Skip to: 86948 /* 36844 */ MCD_OPC_Decode, 134, 28, 211, 1, // Opcode: ST1i64_POST /* 36849 */ MCD_OPC_FilterValue, 1, 174, 195, 0, // Skip to: 86948 /* 36854 */ MCD_OPC_CheckPredicate, 3, 169, 195, 0, // Skip to: 86948 /* 36859 */ MCD_OPC_CheckField, 31, 1, 0, 162, 195, 0, // Skip to: 86948 /* 36866 */ MCD_OPC_CheckField, 12, 1, 0, 155, 195, 0, // Skip to: 86948 /* 36873 */ MCD_OPC_Decode, 164, 28, 212, 1, // Opcode: ST2i64_POST /* 36878 */ MCD_OPC_FilterValue, 5, 145, 195, 0, // Skip to: 86948 /* 36883 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 36886 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36938 /* 36891 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36894 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36916 /* 36899 */ MCD_OPC_CheckPredicate, 3, 124, 195, 0, // Skip to: 86948 /* 36904 */ MCD_OPC_CheckField, 31, 1, 0, 117, 195, 0, // Skip to: 86948 /* 36911 */ MCD_OPC_Decode, 192, 28, 213, 1, // Opcode: ST3i32_POST /* 36916 */ MCD_OPC_FilterValue, 1, 107, 195, 0, // Skip to: 86948 /* 36921 */ MCD_OPC_CheckPredicate, 3, 102, 195, 0, // Skip to: 86948 /* 36926 */ MCD_OPC_CheckField, 31, 1, 0, 95, 195, 0, // Skip to: 86948 /* 36933 */ MCD_OPC_Decode, 222, 28, 214, 1, // Opcode: ST4i32_POST /* 36938 */ MCD_OPC_FilterValue, 1, 85, 195, 0, // Skip to: 86948 /* 36943 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 36946 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36975 /* 36951 */ MCD_OPC_CheckPredicate, 3, 72, 195, 0, // Skip to: 86948 /* 36956 */ MCD_OPC_CheckField, 31, 1, 0, 65, 195, 0, // Skip to: 86948 /* 36963 */ MCD_OPC_CheckField, 12, 1, 0, 58, 195, 0, // Skip to: 86948 /* 36970 */ MCD_OPC_Decode, 194, 28, 215, 1, // Opcode: ST3i64_POST /* 36975 */ MCD_OPC_FilterValue, 1, 48, 195, 0, // Skip to: 86948 /* 36980 */ MCD_OPC_CheckPredicate, 3, 43, 195, 0, // Skip to: 86948 /* 36985 */ MCD_OPC_CheckField, 31, 1, 0, 36, 195, 0, // Skip to: 86948 /* 36992 */ MCD_OPC_CheckField, 12, 1, 0, 29, 195, 0, // Skip to: 86948 /* 36999 */ MCD_OPC_Decode, 224, 28, 216, 1, // Opcode: ST4i64_POST /* 37004 */ MCD_OPC_FilterValue, 1, 19, 195, 0, // Skip to: 86948 /* 37009 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37012 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 37022 /* 37017 */ MCD_OPC_Decode, 138, 29, 150, 1, // Opcode: STPSpre /* 37022 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 37032 /* 37027 */ MCD_OPC_Decode, 132, 29, 150, 1, // Opcode: STPDpre /* 37032 */ MCD_OPC_FilterValue, 2, 247, 194, 0, // Skip to: 86948 /* 37037 */ MCD_OPC_Decode, 135, 29, 150, 1, // Opcode: STPQpre /* 37042 */ MCD_OPC_FilterValue, 7, 201, 4, 0, // Skip to: 38272 /* 37047 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 37050 */ MCD_OPC_FilterValue, 0, 155, 4, 0, // Skip to: 38234 /* 37055 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 37058 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37110 /* 37063 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37066 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37088 /* 37071 */ MCD_OPC_CheckPredicate, 3, 208, 194, 0, // Skip to: 86948 /* 37076 */ MCD_OPC_CheckField, 31, 1, 0, 201, 194, 0, // Skip to: 86948 /* 37083 */ MCD_OPC_Decode, 194, 15, 217, 1, // Opcode: LD1i8_POST /* 37088 */ MCD_OPC_FilterValue, 1, 191, 194, 0, // Skip to: 86948 /* 37093 */ MCD_OPC_CheckPredicate, 3, 186, 194, 0, // Skip to: 86948 /* 37098 */ MCD_OPC_CheckField, 31, 1, 0, 179, 194, 0, // Skip to: 86948 /* 37105 */ MCD_OPC_Decode, 240, 15, 218, 1, // Opcode: LD2i8_POST /* 37110 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 37162 /* 37115 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37118 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37140 /* 37123 */ MCD_OPC_CheckPredicate, 3, 156, 194, 0, // Skip to: 86948 /* 37128 */ MCD_OPC_CheckField, 31, 1, 0, 149, 194, 0, // Skip to: 86948 /* 37135 */ MCD_OPC_Decode, 158, 16, 219, 1, // Opcode: LD3i8_POST /* 37140 */ MCD_OPC_FilterValue, 1, 139, 194, 0, // Skip to: 86948 /* 37145 */ MCD_OPC_CheckPredicate, 3, 134, 194, 0, // Skip to: 86948 /* 37150 */ MCD_OPC_CheckField, 31, 1, 0, 127, 194, 0, // Skip to: 86948 /* 37157 */ MCD_OPC_Decode, 204, 16, 220, 1, // Opcode: LD4i8_POST /* 37162 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 37228 /* 37167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37170 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37199 /* 37175 */ MCD_OPC_CheckPredicate, 3, 104, 194, 0, // Skip to: 86948 /* 37180 */ MCD_OPC_CheckField, 31, 1, 0, 97, 194, 0, // Skip to: 86948 /* 37187 */ MCD_OPC_CheckField, 10, 1, 0, 90, 194, 0, // Skip to: 86948 /* 37194 */ MCD_OPC_Decode, 188, 15, 221, 1, // Opcode: LD1i16_POST /* 37199 */ MCD_OPC_FilterValue, 1, 80, 194, 0, // Skip to: 86948 /* 37204 */ MCD_OPC_CheckPredicate, 3, 75, 194, 0, // Skip to: 86948 /* 37209 */ MCD_OPC_CheckField, 31, 1, 0, 68, 194, 0, // Skip to: 86948 /* 37216 */ MCD_OPC_CheckField, 10, 1, 0, 61, 194, 0, // Skip to: 86948 /* 37223 */ MCD_OPC_Decode, 234, 15, 222, 1, // Opcode: LD2i16_POST /* 37228 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 37294 /* 37233 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37236 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37265 /* 37241 */ MCD_OPC_CheckPredicate, 3, 38, 194, 0, // Skip to: 86948 /* 37246 */ MCD_OPC_CheckField, 31, 1, 0, 31, 194, 0, // Skip to: 86948 /* 37253 */ MCD_OPC_CheckField, 10, 1, 0, 24, 194, 0, // Skip to: 86948 /* 37260 */ MCD_OPC_Decode, 152, 16, 223, 1, // Opcode: LD3i16_POST /* 37265 */ MCD_OPC_FilterValue, 1, 14, 194, 0, // Skip to: 86948 /* 37270 */ MCD_OPC_CheckPredicate, 3, 9, 194, 0, // Skip to: 86948 /* 37275 */ MCD_OPC_CheckField, 31, 1, 0, 2, 194, 0, // Skip to: 86948 /* 37282 */ MCD_OPC_CheckField, 10, 1, 0, 251, 193, 0, // Skip to: 86948 /* 37289 */ MCD_OPC_Decode, 198, 16, 224, 1, // Opcode: LD4i16_POST /* 37294 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 37420 /* 37299 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 37302 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37354 /* 37307 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37310 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37332 /* 37315 */ MCD_OPC_CheckPredicate, 3, 220, 193, 0, // Skip to: 86948 /* 37320 */ MCD_OPC_CheckField, 31, 1, 0, 213, 193, 0, // Skip to: 86948 /* 37327 */ MCD_OPC_Decode, 190, 15, 225, 1, // Opcode: LD1i32_POST /* 37332 */ MCD_OPC_FilterValue, 1, 203, 193, 0, // Skip to: 86948 /* 37337 */ MCD_OPC_CheckPredicate, 3, 198, 193, 0, // Skip to: 86948 /* 37342 */ MCD_OPC_CheckField, 31, 1, 0, 191, 193, 0, // Skip to: 86948 /* 37349 */ MCD_OPC_Decode, 236, 15, 226, 1, // Opcode: LD2i32_POST /* 37354 */ MCD_OPC_FilterValue, 1, 181, 193, 0, // Skip to: 86948 /* 37359 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37362 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37391 /* 37367 */ MCD_OPC_CheckPredicate, 3, 168, 193, 0, // Skip to: 86948 /* 37372 */ MCD_OPC_CheckField, 31, 1, 0, 161, 193, 0, // Skip to: 86948 /* 37379 */ MCD_OPC_CheckField, 12, 1, 0, 154, 193, 0, // Skip to: 86948 /* 37386 */ MCD_OPC_Decode, 192, 15, 227, 1, // Opcode: LD1i64_POST /* 37391 */ MCD_OPC_FilterValue, 1, 144, 193, 0, // Skip to: 86948 /* 37396 */ MCD_OPC_CheckPredicate, 3, 139, 193, 0, // Skip to: 86948 /* 37401 */ MCD_OPC_CheckField, 31, 1, 0, 132, 193, 0, // Skip to: 86948 /* 37408 */ MCD_OPC_CheckField, 12, 1, 0, 125, 193, 0, // Skip to: 86948 /* 37415 */ MCD_OPC_Decode, 238, 15, 228, 1, // Opcode: LD2i64_POST /* 37420 */ MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 37546 /* 37425 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 37428 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37480 /* 37433 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37436 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37458 /* 37441 */ MCD_OPC_CheckPredicate, 3, 94, 193, 0, // Skip to: 86948 /* 37446 */ MCD_OPC_CheckField, 31, 1, 0, 87, 193, 0, // Skip to: 86948 /* 37453 */ MCD_OPC_Decode, 154, 16, 229, 1, // Opcode: LD3i32_POST /* 37458 */ MCD_OPC_FilterValue, 1, 77, 193, 0, // Skip to: 86948 /* 37463 */ MCD_OPC_CheckPredicate, 3, 72, 193, 0, // Skip to: 86948 /* 37468 */ MCD_OPC_CheckField, 31, 1, 0, 65, 193, 0, // Skip to: 86948 /* 37475 */ MCD_OPC_Decode, 200, 16, 230, 1, // Opcode: LD4i32_POST /* 37480 */ MCD_OPC_FilterValue, 1, 55, 193, 0, // Skip to: 86948 /* 37485 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37488 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37517 /* 37493 */ MCD_OPC_CheckPredicate, 3, 42, 193, 0, // Skip to: 86948 /* 37498 */ MCD_OPC_CheckField, 31, 1, 0, 35, 193, 0, // Skip to: 86948 /* 37505 */ MCD_OPC_CheckField, 12, 1, 0, 28, 193, 0, // Skip to: 86948 /* 37512 */ MCD_OPC_Decode, 156, 16, 231, 1, // Opcode: LD3i64_POST /* 37517 */ MCD_OPC_FilterValue, 1, 18, 193, 0, // Skip to: 86948 /* 37522 */ MCD_OPC_CheckPredicate, 3, 13, 193, 0, // Skip to: 86948 /* 37527 */ MCD_OPC_CheckField, 31, 1, 0, 6, 193, 0, // Skip to: 86948 /* 37534 */ MCD_OPC_CheckField, 12, 1, 0, 255, 192, 0, // Skip to: 86948 /* 37541 */ MCD_OPC_Decode, 202, 16, 232, 1, // Opcode: LD4i64_POST /* 37546 */ MCD_OPC_FilterValue, 6, 83, 1, 0, // Skip to: 37890 /* 37551 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 37554 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 37638 /* 37559 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37562 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37600 /* 37567 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37570 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37585 /* 37575 */ MCD_OPC_CheckPredicate, 3, 216, 192, 0, // Skip to: 86948 /* 37580 */ MCD_OPC_Decode, 136, 15, 163, 1, // Opcode: LD1Rv8b_POST /* 37585 */ MCD_OPC_FilterValue, 1, 206, 192, 0, // Skip to: 86948 /* 37590 */ MCD_OPC_CheckPredicate, 3, 201, 192, 0, // Skip to: 86948 /* 37595 */ MCD_OPC_Decode, 252, 14, 167, 1, // Opcode: LD1Rv16b_POST /* 37600 */ MCD_OPC_FilterValue, 1, 191, 192, 0, // Skip to: 86948 /* 37605 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37608 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37623 /* 37613 */ MCD_OPC_CheckPredicate, 3, 178, 192, 0, // Skip to: 86948 /* 37618 */ MCD_OPC_Decode, 214, 15, 164, 1, // Opcode: LD2Rv8b_POST /* 37623 */ MCD_OPC_FilterValue, 1, 168, 192, 0, // Skip to: 86948 /* 37628 */ MCD_OPC_CheckPredicate, 3, 163, 192, 0, // Skip to: 86948 /* 37633 */ MCD_OPC_Decode, 202, 15, 168, 1, // Opcode: LD2Rv16b_POST /* 37638 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 37722 /* 37643 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37646 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37684 /* 37651 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37654 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37669 /* 37659 */ MCD_OPC_CheckPredicate, 3, 132, 192, 0, // Skip to: 86948 /* 37664 */ MCD_OPC_Decode, 132, 15, 163, 1, // Opcode: LD1Rv4h_POST /* 37669 */ MCD_OPC_FilterValue, 1, 122, 192, 0, // Skip to: 86948 /* 37674 */ MCD_OPC_CheckPredicate, 3, 117, 192, 0, // Skip to: 86948 /* 37679 */ MCD_OPC_Decode, 138, 15, 167, 1, // Opcode: LD1Rv8h_POST /* 37684 */ MCD_OPC_FilterValue, 1, 107, 192, 0, // Skip to: 86948 /* 37689 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37692 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37707 /* 37697 */ MCD_OPC_CheckPredicate, 3, 94, 192, 0, // Skip to: 86948 /* 37702 */ MCD_OPC_Decode, 210, 15, 164, 1, // Opcode: LD2Rv4h_POST /* 37707 */ MCD_OPC_FilterValue, 1, 84, 192, 0, // Skip to: 86948 /* 37712 */ MCD_OPC_CheckPredicate, 3, 79, 192, 0, // Skip to: 86948 /* 37717 */ MCD_OPC_Decode, 216, 15, 168, 1, // Opcode: LD2Rv8h_POST /* 37722 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 37806 /* 37727 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37730 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37768 /* 37735 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37738 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37753 /* 37743 */ MCD_OPC_CheckPredicate, 3, 48, 192, 0, // Skip to: 86948 /* 37748 */ MCD_OPC_Decode, 130, 15, 163, 1, // Opcode: LD1Rv2s_POST /* 37753 */ MCD_OPC_FilterValue, 1, 38, 192, 0, // Skip to: 86948 /* 37758 */ MCD_OPC_CheckPredicate, 3, 33, 192, 0, // Skip to: 86948 /* 37763 */ MCD_OPC_Decode, 134, 15, 167, 1, // Opcode: LD1Rv4s_POST /* 37768 */ MCD_OPC_FilterValue, 1, 23, 192, 0, // Skip to: 86948 /* 37773 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37791 /* 37781 */ MCD_OPC_CheckPredicate, 3, 10, 192, 0, // Skip to: 86948 /* 37786 */ MCD_OPC_Decode, 208, 15, 164, 1, // Opcode: LD2Rv2s_POST /* 37791 */ MCD_OPC_FilterValue, 1, 0, 192, 0, // Skip to: 86948 /* 37796 */ MCD_OPC_CheckPredicate, 3, 251, 191, 0, // Skip to: 86948 /* 37801 */ MCD_OPC_Decode, 212, 15, 168, 1, // Opcode: LD2Rv4s_POST /* 37806 */ MCD_OPC_FilterValue, 3, 241, 191, 0, // Skip to: 86948 /* 37811 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37814 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37852 /* 37819 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37822 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37837 /* 37827 */ MCD_OPC_CheckPredicate, 3, 220, 191, 0, // Skip to: 86948 /* 37832 */ MCD_OPC_Decode, 254, 14, 163, 1, // Opcode: LD1Rv1d_POST /* 37837 */ MCD_OPC_FilterValue, 1, 210, 191, 0, // Skip to: 86948 /* 37842 */ MCD_OPC_CheckPredicate, 3, 205, 191, 0, // Skip to: 86948 /* 37847 */ MCD_OPC_Decode, 128, 15, 167, 1, // Opcode: LD1Rv2d_POST /* 37852 */ MCD_OPC_FilterValue, 1, 195, 191, 0, // Skip to: 86948 /* 37857 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37860 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37875 /* 37865 */ MCD_OPC_CheckPredicate, 3, 182, 191, 0, // Skip to: 86948 /* 37870 */ MCD_OPC_Decode, 204, 15, 164, 1, // Opcode: LD2Rv1d_POST /* 37875 */ MCD_OPC_FilterValue, 1, 172, 191, 0, // Skip to: 86948 /* 37880 */ MCD_OPC_CheckPredicate, 3, 167, 191, 0, // Skip to: 86948 /* 37885 */ MCD_OPC_Decode, 206, 15, 168, 1, // Opcode: LD2Rv2d_POST /* 37890 */ MCD_OPC_FilterValue, 7, 157, 191, 0, // Skip to: 86948 /* 37895 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 37898 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 37982 /* 37903 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37906 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37944 /* 37911 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37929 /* 37919 */ MCD_OPC_CheckPredicate, 3, 128, 191, 0, // Skip to: 86948 /* 37924 */ MCD_OPC_Decode, 132, 16, 162, 1, // Opcode: LD3Rv8b_POST /* 37929 */ MCD_OPC_FilterValue, 1, 118, 191, 0, // Skip to: 86948 /* 37934 */ MCD_OPC_CheckPredicate, 3, 113, 191, 0, // Skip to: 86948 /* 37939 */ MCD_OPC_Decode, 248, 15, 166, 1, // Opcode: LD3Rv16b_POST /* 37944 */ MCD_OPC_FilterValue, 1, 103, 191, 0, // Skip to: 86948 /* 37949 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37952 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37967 /* 37957 */ MCD_OPC_CheckPredicate, 3, 90, 191, 0, // Skip to: 86948 /* 37962 */ MCD_OPC_Decode, 192, 16, 161, 1, // Opcode: LD4Rv8b_POST /* 37967 */ MCD_OPC_FilterValue, 1, 80, 191, 0, // Skip to: 86948 /* 37972 */ MCD_OPC_CheckPredicate, 3, 75, 191, 0, // Skip to: 86948 /* 37977 */ MCD_OPC_Decode, 180, 16, 165, 1, // Opcode: LD4Rv16b_POST /* 37982 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 38066 /* 37987 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 37990 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38028 /* 37995 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 37998 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38013 /* 38003 */ MCD_OPC_CheckPredicate, 3, 44, 191, 0, // Skip to: 86948 /* 38008 */ MCD_OPC_Decode, 128, 16, 162, 1, // Opcode: LD3Rv4h_POST /* 38013 */ MCD_OPC_FilterValue, 1, 34, 191, 0, // Skip to: 86948 /* 38018 */ MCD_OPC_CheckPredicate, 3, 29, 191, 0, // Skip to: 86948 /* 38023 */ MCD_OPC_Decode, 134, 16, 166, 1, // Opcode: LD3Rv8h_POST /* 38028 */ MCD_OPC_FilterValue, 1, 19, 191, 0, // Skip to: 86948 /* 38033 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 38036 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38051 /* 38041 */ MCD_OPC_CheckPredicate, 3, 6, 191, 0, // Skip to: 86948 /* 38046 */ MCD_OPC_Decode, 188, 16, 161, 1, // Opcode: LD4Rv4h_POST /* 38051 */ MCD_OPC_FilterValue, 1, 252, 190, 0, // Skip to: 86948 /* 38056 */ MCD_OPC_CheckPredicate, 3, 247, 190, 0, // Skip to: 86948 /* 38061 */ MCD_OPC_Decode, 194, 16, 165, 1, // Opcode: LD4Rv8h_POST /* 38066 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 38150 /* 38071 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38074 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38112 /* 38079 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 38082 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38097 /* 38087 */ MCD_OPC_CheckPredicate, 3, 216, 190, 0, // Skip to: 86948 /* 38092 */ MCD_OPC_Decode, 254, 15, 162, 1, // Opcode: LD3Rv2s_POST /* 38097 */ MCD_OPC_FilterValue, 1, 206, 190, 0, // Skip to: 86948 /* 38102 */ MCD_OPC_CheckPredicate, 3, 201, 190, 0, // Skip to: 86948 /* 38107 */ MCD_OPC_Decode, 130, 16, 166, 1, // Opcode: LD3Rv4s_POST /* 38112 */ MCD_OPC_FilterValue, 1, 191, 190, 0, // Skip to: 86948 /* 38117 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 38120 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38135 /* 38125 */ MCD_OPC_CheckPredicate, 3, 178, 190, 0, // Skip to: 86948 /* 38130 */ MCD_OPC_Decode, 186, 16, 161, 1, // Opcode: LD4Rv2s_POST /* 38135 */ MCD_OPC_FilterValue, 1, 168, 190, 0, // Skip to: 86948 /* 38140 */ MCD_OPC_CheckPredicate, 3, 163, 190, 0, // Skip to: 86948 /* 38145 */ MCD_OPC_Decode, 190, 16, 165, 1, // Opcode: LD4Rv4s_POST /* 38150 */ MCD_OPC_FilterValue, 3, 153, 190, 0, // Skip to: 86948 /* 38155 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38158 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38196 /* 38163 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 38166 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38181 /* 38171 */ MCD_OPC_CheckPredicate, 3, 132, 190, 0, // Skip to: 86948 /* 38176 */ MCD_OPC_Decode, 250, 15, 162, 1, // Opcode: LD3Rv1d_POST /* 38181 */ MCD_OPC_FilterValue, 1, 122, 190, 0, // Skip to: 86948 /* 38186 */ MCD_OPC_CheckPredicate, 3, 117, 190, 0, // Skip to: 86948 /* 38191 */ MCD_OPC_Decode, 252, 15, 166, 1, // Opcode: LD3Rv2d_POST /* 38196 */ MCD_OPC_FilterValue, 1, 107, 190, 0, // Skip to: 86948 /* 38201 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 38204 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38219 /* 38209 */ MCD_OPC_CheckPredicate, 3, 94, 190, 0, // Skip to: 86948 /* 38214 */ MCD_OPC_Decode, 182, 16, 161, 1, // Opcode: LD4Rv1d_POST /* 38219 */ MCD_OPC_FilterValue, 1, 84, 190, 0, // Skip to: 86948 /* 38224 */ MCD_OPC_CheckPredicate, 3, 79, 190, 0, // Skip to: 86948 /* 38229 */ MCD_OPC_Decode, 184, 16, 165, 1, // Opcode: LD4Rv2d_POST /* 38234 */ MCD_OPC_FilterValue, 1, 69, 190, 0, // Skip to: 86948 /* 38239 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 38242 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 38252 /* 38247 */ MCD_OPC_Decode, 208, 17, 150, 1, // Opcode: LDPSpre /* 38252 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 38262 /* 38257 */ MCD_OPC_Decode, 199, 17, 150, 1, // Opcode: LDPDpre /* 38262 */ MCD_OPC_FilterValue, 2, 41, 190, 0, // Skip to: 86948 /* 38267 */ MCD_OPC_Decode, 202, 17, 150, 1, // Opcode: LDPQpre /* 38272 */ MCD_OPC_FilterValue, 8, 6, 27, 0, // Skip to: 45195 /* 38277 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 38280 */ MCD_OPC_FilterValue, 0, 189, 7, 0, // Skip to: 40266 /* 38285 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 38288 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38326 /* 38293 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38311 /* 38301 */ MCD_OPC_CheckPredicate, 3, 2, 190, 0, // Skip to: 86948 /* 38306 */ MCD_OPC_Decode, 186, 30, 233, 1, // Opcode: TBLv8i8One /* 38311 */ MCD_OPC_FilterValue, 1, 248, 189, 0, // Skip to: 86948 /* 38316 */ MCD_OPC_CheckPredicate, 3, 243, 189, 0, // Skip to: 86948 /* 38321 */ MCD_OPC_Decode, 168, 22, 234, 1, // Opcode: SADDLv8i8_v8i16 /* 38326 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 38417 /* 38331 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38334 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 38402 /* 38339 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 38342 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38387 /* 38347 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 38350 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38372 /* 38355 */ MCD_OPC_CheckPredicate, 3, 204, 189, 0, // Skip to: 86948 /* 38360 */ MCD_OPC_CheckField, 18, 1, 1, 197, 189, 0, // Skip to: 86948 /* 38367 */ MCD_OPC_Decode, 211, 5, 235, 1, // Opcode: DUPv2i32lane /* 38372 */ MCD_OPC_FilterValue, 1, 187, 189, 0, // Skip to: 86948 /* 38377 */ MCD_OPC_CheckPredicate, 3, 182, 189, 0, // Skip to: 86948 /* 38382 */ MCD_OPC_Decode, 215, 5, 236, 1, // Opcode: DUPv4i16lane /* 38387 */ MCD_OPC_FilterValue, 1, 172, 189, 0, // Skip to: 86948 /* 38392 */ MCD_OPC_CheckPredicate, 3, 167, 189, 0, // Skip to: 86948 /* 38397 */ MCD_OPC_Decode, 221, 5, 237, 1, // Opcode: DUPv8i8lane /* 38402 */ MCD_OPC_FilterValue, 1, 157, 189, 0, // Skip to: 86948 /* 38407 */ MCD_OPC_CheckPredicate, 3, 152, 189, 0, // Skip to: 86948 /* 38412 */ MCD_OPC_Decode, 132, 23, 238, 1, // Opcode: SHADDv8i8 /* 38417 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 38439 /* 38422 */ MCD_OPC_CheckPredicate, 3, 137, 189, 0, // Skip to: 86948 /* 38427 */ MCD_OPC_CheckField, 16, 6, 32, 130, 189, 0, // Skip to: 86948 /* 38434 */ MCD_OPC_Decode, 214, 21, 239, 1, // Opcode: REV64v8i8 /* 38439 */ MCD_OPC_FilterValue, 3, 86, 0, 0, // Skip to: 38530 /* 38444 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38447 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 38515 /* 38452 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 38455 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38500 /* 38460 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 38463 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38485 /* 38468 */ MCD_OPC_CheckPredicate, 3, 91, 189, 0, // Skip to: 86948 /* 38473 */ MCD_OPC_CheckField, 18, 1, 1, 84, 189, 0, // Skip to: 86948 /* 38480 */ MCD_OPC_Decode, 210, 5, 240, 1, // Opcode: DUPv2i32gpr /* 38485 */ MCD_OPC_FilterValue, 1, 74, 189, 0, // Skip to: 86948 /* 38490 */ MCD_OPC_CheckPredicate, 3, 69, 189, 0, // Skip to: 86948 /* 38495 */ MCD_OPC_Decode, 214, 5, 240, 1, // Opcode: DUPv4i16gpr /* 38500 */ MCD_OPC_FilterValue, 1, 59, 189, 0, // Skip to: 86948 /* 38505 */ MCD_OPC_CheckPredicate, 3, 54, 189, 0, // Skip to: 86948 /* 38510 */ MCD_OPC_Decode, 220, 5, 240, 1, // Opcode: DUPv8i8gpr /* 38515 */ MCD_OPC_FilterValue, 1, 44, 189, 0, // Skip to: 86948 /* 38520 */ MCD_OPC_CheckPredicate, 3, 39, 189, 0, // Skip to: 86948 /* 38525 */ MCD_OPC_Decode, 182, 24, 238, 1, // Opcode: SQADDv8i8 /* 38530 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 38568 /* 38535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38538 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38553 /* 38543 */ MCD_OPC_CheckPredicate, 3, 16, 189, 0, // Skip to: 86948 /* 38548 */ MCD_OPC_Decode, 196, 30, 241, 1, // Opcode: TBXv8i8One /* 38553 */ MCD_OPC_FilterValue, 1, 6, 189, 0, // Skip to: 86948 /* 38558 */ MCD_OPC_CheckPredicate, 3, 1, 189, 0, // Skip to: 86948 /* 38563 */ MCD_OPC_Decode, 177, 22, 242, 1, // Opcode: SADDWv8i8_v8i16 /* 38568 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 38590 /* 38573 */ MCD_OPC_CheckPredicate, 3, 242, 188, 0, // Skip to: 86948 /* 38578 */ MCD_OPC_CheckField, 21, 1, 1, 235, 188, 0, // Skip to: 86948 /* 38585 */ MCD_OPC_Decode, 188, 26, 238, 1, // Opcode: SRHADDv8i8 /* 38590 */ MCD_OPC_FilterValue, 6, 40, 0, 0, // Skip to: 38635 /* 38595 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38598 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38613 /* 38603 */ MCD_OPC_CheckPredicate, 3, 212, 188, 0, // Skip to: 86948 /* 38608 */ MCD_OPC_Decode, 202, 34, 238, 1, // Opcode: UZP1v8i8 /* 38613 */ MCD_OPC_FilterValue, 1, 202, 188, 0, // Skip to: 86948 /* 38618 */ MCD_OPC_CheckPredicate, 3, 197, 188, 0, // Skip to: 86948 /* 38623 */ MCD_OPC_CheckField, 16, 5, 0, 190, 188, 0, // Skip to: 86948 /* 38630 */ MCD_OPC_Decode, 203, 21, 239, 1, // Opcode: REV16v8i8 /* 38635 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 38657 /* 38640 */ MCD_OPC_CheckPredicate, 3, 175, 188, 0, // Skip to: 86948 /* 38645 */ MCD_OPC_CheckField, 21, 1, 1, 168, 188, 0, // Skip to: 86948 /* 38652 */ MCD_OPC_Decode, 253, 1, 238, 1, // Opcode: ANDv8i8 /* 38657 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 38695 /* 38662 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38665 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38680 /* 38670 */ MCD_OPC_CheckPredicate, 3, 145, 188, 0, // Skip to: 86948 /* 38675 */ MCD_OPC_Decode, 188, 30, 243, 1, // Opcode: TBLv8i8Two /* 38680 */ MCD_OPC_FilterValue, 1, 135, 188, 0, // Skip to: 86948 /* 38685 */ MCD_OPC_CheckPredicate, 3, 130, 188, 0, // Skip to: 86948 /* 38690 */ MCD_OPC_Decode, 166, 27, 234, 1, // Opcode: SSUBLv8i8_v8i16 /* 38695 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 38717 /* 38700 */ MCD_OPC_CheckPredicate, 3, 115, 188, 0, // Skip to: 86948 /* 38705 */ MCD_OPC_CheckField, 21, 1, 1, 108, 188, 0, // Skip to: 86948 /* 38712 */ MCD_OPC_Decode, 158, 23, 238, 1, // Opcode: SHSUBv8i8 /* 38717 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 38778 /* 38722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38725 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38740 /* 38730 */ MCD_OPC_CheckPredicate, 3, 85, 188, 0, // Skip to: 86948 /* 38735 */ MCD_OPC_Decode, 219, 30, 238, 1, // Opcode: TRN1v8i8 /* 38740 */ MCD_OPC_FilterValue, 1, 75, 188, 0, // Skip to: 86948 /* 38745 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 38748 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38763 /* 38753 */ MCD_OPC_CheckPredicate, 3, 62, 188, 0, // Skip to: 86948 /* 38758 */ MCD_OPC_Decode, 157, 22, 239, 1, // Opcode: SADDLPv8i8_v4i16 /* 38763 */ MCD_OPC_FilterValue, 1, 52, 188, 0, // Skip to: 86948 /* 38768 */ MCD_OPC_CheckPredicate, 3, 47, 188, 0, // Skip to: 86948 /* 38773 */ MCD_OPC_Decode, 132, 35, 244, 1, // Opcode: XTNv8i8 /* 38778 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 38846 /* 38783 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38786 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38831 /* 38791 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 38794 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38816 /* 38799 */ MCD_OPC_CheckPredicate, 3, 16, 188, 0, // Skip to: 86948 /* 38804 */ MCD_OPC_CheckField, 17, 1, 1, 9, 188, 0, // Skip to: 86948 /* 38811 */ MCD_OPC_Decode, 128, 24, 245, 1, // Opcode: SMOVvi16to32 /* 38816 */ MCD_OPC_FilterValue, 1, 255, 187, 0, // Skip to: 86948 /* 38821 */ MCD_OPC_CheckPredicate, 3, 250, 187, 0, // Skip to: 86948 /* 38826 */ MCD_OPC_Decode, 131, 24, 246, 1, // Opcode: SMOVvi8to32 /* 38831 */ MCD_OPC_FilterValue, 1, 240, 187, 0, // Skip to: 86948 /* 38836 */ MCD_OPC_CheckPredicate, 3, 235, 187, 0, // Skip to: 86948 /* 38841 */ MCD_OPC_Decode, 164, 26, 238, 1, // Opcode: SQSUBv8i8 /* 38846 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 38884 /* 38851 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38854 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38869 /* 38859 */ MCD_OPC_CheckPredicate, 3, 212, 187, 0, // Skip to: 86948 /* 38864 */ MCD_OPC_Decode, 198, 30, 247, 1, // Opcode: TBXv8i8Two /* 38869 */ MCD_OPC_FilterValue, 1, 202, 187, 0, // Skip to: 86948 /* 38874 */ MCD_OPC_CheckPredicate, 3, 197, 187, 0, // Skip to: 86948 /* 38879 */ MCD_OPC_Decode, 172, 27, 242, 1, // Opcode: SSUBWv8i8_v8i16 /* 38884 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 38906 /* 38889 */ MCD_OPC_CheckPredicate, 3, 182, 187, 0, // Skip to: 86948 /* 38894 */ MCD_OPC_CheckField, 21, 1, 1, 175, 187, 0, // Skip to: 86948 /* 38901 */ MCD_OPC_Decode, 228, 3, 238, 1, // Opcode: CMGTv8i8 /* 38906 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 38967 /* 38911 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38929 /* 38919 */ MCD_OPC_CheckPredicate, 3, 152, 187, 0, // Skip to: 86948 /* 38924 */ MCD_OPC_Decode, 147, 35, 238, 1, // Opcode: ZIP1v8i8 /* 38929 */ MCD_OPC_FilterValue, 1, 142, 187, 0, // Skip to: 86948 /* 38934 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 38937 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38952 /* 38942 */ MCD_OPC_CheckPredicate, 3, 129, 187, 0, // Skip to: 86948 /* 38947 */ MCD_OPC_Decode, 151, 30, 248, 1, // Opcode: SUQADDv8i8 /* 38952 */ MCD_OPC_FilterValue, 16, 119, 187, 0, // Skip to: 86948 /* 38957 */ MCD_OPC_CheckPredicate, 3, 114, 187, 0, // Skip to: 86948 /* 38962 */ MCD_OPC_Decode, 162, 22, 249, 1, // Opcode: SADDLVv8i8v /* 38967 */ MCD_OPC_FilterValue, 15, 86, 0, 0, // Skip to: 39058 /* 38972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 38975 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 39043 /* 38980 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 38983 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 39028 /* 38988 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 38991 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 39013 /* 38996 */ MCD_OPC_CheckPredicate, 3, 75, 187, 0, // Skip to: 86948 /* 39001 */ MCD_OPC_CheckField, 18, 1, 1, 68, 187, 0, // Skip to: 86948 /* 39008 */ MCD_OPC_Decode, 184, 32, 250, 1, // Opcode: UMOVvi32 /* 39013 */ MCD_OPC_FilterValue, 1, 58, 187, 0, // Skip to: 86948 /* 39018 */ MCD_OPC_CheckPredicate, 3, 53, 187, 0, // Skip to: 86948 /* 39023 */ MCD_OPC_Decode, 183, 32, 245, 1, // Opcode: UMOVvi16 /* 39028 */ MCD_OPC_FilterValue, 1, 43, 187, 0, // Skip to: 86948 /* 39033 */ MCD_OPC_CheckPredicate, 3, 38, 187, 0, // Skip to: 86948 /* 39038 */ MCD_OPC_Decode, 186, 32, 246, 1, // Opcode: UMOVvi8 /* 39043 */ MCD_OPC_FilterValue, 1, 28, 187, 0, // Skip to: 86948 /* 39048 */ MCD_OPC_CheckPredicate, 3, 23, 187, 0, // Skip to: 86948 /* 39053 */ MCD_OPC_Decode, 212, 3, 238, 1, // Opcode: CMGEv8i8 /* 39058 */ MCD_OPC_FilterValue, 16, 33, 0, 0, // Skip to: 39096 /* 39063 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39066 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39081 /* 39071 */ MCD_OPC_CheckPredicate, 3, 0, 187, 0, // Skip to: 86948 /* 39076 */ MCD_OPC_Decode, 187, 30, 251, 1, // Opcode: TBLv8i8Three /* 39081 */ MCD_OPC_FilterValue, 1, 246, 186, 0, // Skip to: 86948 /* 39086 */ MCD_OPC_CheckPredicate, 3, 241, 186, 0, // Skip to: 86948 /* 39091 */ MCD_OPC_Decode, 147, 1, 252, 1, // Opcode: ADDHNv8i16_v8i8 /* 39096 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 39118 /* 39101 */ MCD_OPC_CheckPredicate, 3, 226, 186, 0, // Skip to: 86948 /* 39106 */ MCD_OPC_CheckField, 21, 1, 1, 219, 186, 0, // Skip to: 86948 /* 39113 */ MCD_OPC_Decode, 234, 26, 238, 1, // Opcode: SSHLv8i8 /* 39118 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 39156 /* 39123 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 39126 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39141 /* 39131 */ MCD_OPC_CheckPredicate, 3, 196, 186, 0, // Skip to: 86948 /* 39136 */ MCD_OPC_Decode, 169, 3, 239, 1, // Opcode: CLSv8i8 /* 39141 */ MCD_OPC_FilterValue, 33, 186, 186, 0, // Skip to: 86948 /* 39146 */ MCD_OPC_CheckPredicate, 3, 181, 186, 0, // Skip to: 86948 /* 39151 */ MCD_OPC_Decode, 173, 26, 244, 1, // Opcode: SQXTNv8i8 /* 39156 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 39178 /* 39161 */ MCD_OPC_CheckPredicate, 3, 166, 186, 0, // Skip to: 86948 /* 39166 */ MCD_OPC_CheckField, 21, 1, 1, 159, 186, 0, // Skip to: 86948 /* 39173 */ MCD_OPC_Decode, 254, 25, 238, 1, // Opcode: SQSHLv8i8 /* 39178 */ MCD_OPC_FilterValue, 20, 33, 0, 0, // Skip to: 39216 /* 39183 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39186 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39201 /* 39191 */ MCD_OPC_CheckPredicate, 3, 136, 186, 0, // Skip to: 86948 /* 39196 */ MCD_OPC_Decode, 197, 30, 253, 1, // Opcode: TBXv8i8Three /* 39201 */ MCD_OPC_FilterValue, 1, 126, 186, 0, // Skip to: 86948 /* 39206 */ MCD_OPC_CheckPredicate, 3, 121, 186, 0, // Skip to: 86948 /* 39211 */ MCD_OPC_Decode, 251, 21, 254, 1, // Opcode: SABALv8i8_v8i16 /* 39216 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 39238 /* 39221 */ MCD_OPC_CheckPredicate, 3, 106, 186, 0, // Skip to: 86948 /* 39226 */ MCD_OPC_CheckField, 21, 1, 1, 99, 186, 0, // Skip to: 86948 /* 39233 */ MCD_OPC_Decode, 204, 26, 238, 1, // Opcode: SRSHLv8i8 /* 39238 */ MCD_OPC_FilterValue, 22, 40, 0, 0, // Skip to: 39283 /* 39243 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39246 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39261 /* 39251 */ MCD_OPC_CheckPredicate, 3, 76, 186, 0, // Skip to: 86948 /* 39256 */ MCD_OPC_Decode, 217, 34, 238, 1, // Opcode: UZP2v8i8 /* 39261 */ MCD_OPC_FilterValue, 1, 66, 186, 0, // Skip to: 86948 /* 39266 */ MCD_OPC_CheckPredicate, 3, 61, 186, 0, // Skip to: 86948 /* 39271 */ MCD_OPC_CheckField, 16, 5, 0, 54, 186, 0, // Skip to: 86948 /* 39278 */ MCD_OPC_Decode, 130, 5, 239, 1, // Opcode: CNTv8i8 /* 39283 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 39305 /* 39288 */ MCD_OPC_CheckPredicate, 3, 39, 186, 0, // Skip to: 86948 /* 39293 */ MCD_OPC_CheckField, 21, 1, 1, 32, 186, 0, // Skip to: 86948 /* 39300 */ MCD_OPC_Decode, 204, 25, 238, 1, // Opcode: SQRSHLv8i8 /* 39305 */ MCD_OPC_FilterValue, 24, 33, 0, 0, // Skip to: 39343 /* 39310 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39328 /* 39318 */ MCD_OPC_CheckPredicate, 3, 9, 186, 0, // Skip to: 86948 /* 39323 */ MCD_OPC_Decode, 185, 30, 255, 1, // Opcode: TBLv8i8Four /* 39328 */ MCD_OPC_FilterValue, 1, 255, 185, 0, // Skip to: 86948 /* 39333 */ MCD_OPC_CheckPredicate, 3, 250, 185, 0, // Skip to: 86948 /* 39338 */ MCD_OPC_Decode, 216, 29, 252, 1, // Opcode: SUBHNv8i16_v8i8 /* 39343 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 39365 /* 39348 */ MCD_OPC_CheckPredicate, 3, 235, 185, 0, // Skip to: 86948 /* 39353 */ MCD_OPC_CheckField, 21, 1, 1, 228, 185, 0, // Skip to: 86948 /* 39360 */ MCD_OPC_Decode, 205, 23, 238, 1, // Opcode: SMAXv8i8 /* 39365 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 39426 /* 39370 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39373 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39388 /* 39378 */ MCD_OPC_CheckPredicate, 3, 205, 185, 0, // Skip to: 86948 /* 39383 */ MCD_OPC_Decode, 234, 30, 238, 1, // Opcode: TRN2v8i8 /* 39388 */ MCD_OPC_FilterValue, 1, 195, 185, 0, // Skip to: 86948 /* 39393 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 39396 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39411 /* 39401 */ MCD_OPC_CheckPredicate, 3, 182, 185, 0, // Skip to: 86948 /* 39406 */ MCD_OPC_Decode, 151, 22, 248, 1, // Opcode: SADALPv8i8_v4i16 /* 39411 */ MCD_OPC_FilterValue, 1, 172, 185, 0, // Skip to: 86948 /* 39416 */ MCD_OPC_CheckPredicate, 3, 167, 185, 0, // Skip to: 86948 /* 39421 */ MCD_OPC_Decode, 182, 8, 244, 1, // Opcode: FCVTNv4i16 /* 39426 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 39448 /* 39431 */ MCD_OPC_CheckPredicate, 3, 152, 185, 0, // Skip to: 86948 /* 39436 */ MCD_OPC_CheckField, 21, 1, 1, 145, 185, 0, // Skip to: 86948 /* 39443 */ MCD_OPC_Decode, 235, 23, 238, 1, // Opcode: SMINv8i8 /* 39448 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 39486 /* 39453 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39456 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39471 /* 39461 */ MCD_OPC_CheckPredicate, 3, 122, 185, 0, // Skip to: 86948 /* 39466 */ MCD_OPC_Decode, 195, 30, 128, 2, // Opcode: TBXv8i8Four /* 39471 */ MCD_OPC_FilterValue, 1, 112, 185, 0, // Skip to: 86948 /* 39476 */ MCD_OPC_CheckPredicate, 3, 107, 185, 0, // Skip to: 86948 /* 39481 */ MCD_OPC_Decode, 135, 22, 234, 1, // Opcode: SABDLv8i8_v8i16 /* 39486 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 39508 /* 39491 */ MCD_OPC_CheckPredicate, 3, 92, 185, 0, // Skip to: 86948 /* 39496 */ MCD_OPC_CheckField, 21, 1, 1, 85, 185, 0, // Skip to: 86948 /* 39503 */ MCD_OPC_Decode, 145, 22, 238, 1, // Opcode: SABDv8i8 /* 39508 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 39569 /* 39513 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 39516 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39531 /* 39521 */ MCD_OPC_CheckPredicate, 3, 62, 185, 0, // Skip to: 86948 /* 39526 */ MCD_OPC_Decode, 162, 35, 238, 1, // Opcode: ZIP2v8i8 /* 39531 */ MCD_OPC_FilterValue, 1, 52, 185, 0, // Skip to: 86948 /* 39536 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 39539 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39554 /* 39544 */ MCD_OPC_CheckPredicate, 3, 39, 185, 0, // Skip to: 86948 /* 39549 */ MCD_OPC_Decode, 163, 24, 239, 1, // Opcode: SQABSv8i8 /* 39554 */ MCD_OPC_FilterValue, 1, 29, 185, 0, // Skip to: 86948 /* 39559 */ MCD_OPC_CheckPredicate, 3, 24, 185, 0, // Skip to: 86948 /* 39564 */ MCD_OPC_Decode, 250, 7, 129, 2, // Opcode: FCVTLv4i16 /* 39569 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 39591 /* 39574 */ MCD_OPC_CheckPredicate, 3, 9, 185, 0, // Skip to: 86948 /* 39579 */ MCD_OPC_CheckField, 21, 1, 1, 2, 185, 0, // Skip to: 86948 /* 39586 */ MCD_OPC_Decode, 129, 22, 130, 2, // Opcode: SABAv8i8 /* 39591 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 39613 /* 39596 */ MCD_OPC_CheckPredicate, 3, 243, 184, 0, // Skip to: 86948 /* 39601 */ MCD_OPC_CheckField, 21, 1, 1, 236, 184, 0, // Skip to: 86948 /* 39608 */ MCD_OPC_Decode, 245, 23, 254, 1, // Opcode: SMLALv8i8_v8i16 /* 39613 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 39635 /* 39618 */ MCD_OPC_CheckPredicate, 3, 221, 184, 0, // Skip to: 86948 /* 39623 */ MCD_OPC_CheckField, 21, 1, 1, 214, 184, 0, // Skip to: 86948 /* 39630 */ MCD_OPC_Decode, 201, 1, 238, 1, // Opcode: ADDv8i8 /* 39635 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 39673 /* 39640 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 39643 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39658 /* 39648 */ MCD_OPC_CheckPredicate, 3, 191, 184, 0, // Skip to: 86948 /* 39653 */ MCD_OPC_Decode, 229, 3, 239, 1, // Opcode: CMGTv8i8rz /* 39658 */ MCD_OPC_FilterValue, 33, 181, 184, 0, // Skip to: 86948 /* 39663 */ MCD_OPC_CheckPredicate, 3, 176, 184, 0, // Skip to: 86948 /* 39668 */ MCD_OPC_Decode, 135, 12, 239, 1, // Opcode: FRINTNv2f32 /* 39673 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 39695 /* 39678 */ MCD_OPC_CheckPredicate, 3, 161, 184, 0, // Skip to: 86948 /* 39683 */ MCD_OPC_CheckField, 21, 1, 1, 154, 184, 0, // Skip to: 86948 /* 39690 */ MCD_OPC_Decode, 240, 4, 238, 1, // Opcode: CMTSTv8i8 /* 39695 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 39717 /* 39700 */ MCD_OPC_CheckPredicate, 3, 139, 184, 0, // Skip to: 86948 /* 39705 */ MCD_OPC_CheckField, 21, 1, 1, 132, 184, 0, // Skip to: 86948 /* 39712 */ MCD_OPC_Decode, 218, 19, 130, 2, // Opcode: MLAv8i8 /* 39717 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 39755 /* 39722 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 39725 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39740 /* 39730 */ MCD_OPC_CheckPredicate, 3, 109, 184, 0, // Skip to: 86948 /* 39735 */ MCD_OPC_Decode, 197, 3, 239, 1, // Opcode: CMEQv8i8rz /* 39740 */ MCD_OPC_FilterValue, 33, 99, 184, 0, // Skip to: 86948 /* 39745 */ MCD_OPC_CheckPredicate, 3, 94, 184, 0, // Skip to: 86948 /* 39750 */ MCD_OPC_Decode, 252, 11, 239, 1, // Opcode: FRINTMv2f32 /* 39755 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 39777 /* 39760 */ MCD_OPC_CheckPredicate, 3, 79, 184, 0, // Skip to: 86948 /* 39765 */ MCD_OPC_CheckField, 21, 1, 1, 72, 184, 0, // Skip to: 86948 /* 39772 */ MCD_OPC_Decode, 166, 20, 238, 1, // Opcode: MULv8i8 /* 39777 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 39799 /* 39782 */ MCD_OPC_CheckPredicate, 3, 57, 184, 0, // Skip to: 86948 /* 39787 */ MCD_OPC_CheckField, 21, 1, 1, 50, 184, 0, // Skip to: 86948 /* 39794 */ MCD_OPC_Decode, 255, 23, 254, 1, // Opcode: SMLSLv8i8_v8i16 /* 39799 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 39821 /* 39804 */ MCD_OPC_CheckPredicate, 3, 35, 184, 0, // Skip to: 86948 /* 39809 */ MCD_OPC_CheckField, 21, 1, 1, 28, 184, 0, // Skip to: 86948 /* 39816 */ MCD_OPC_Decode, 182, 23, 238, 1, // Opcode: SMAXPv8i8 /* 39821 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 39889 /* 39826 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 39829 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39844 /* 39834 */ MCD_OPC_CheckPredicate, 3, 5, 184, 0, // Skip to: 86948 /* 39839 */ MCD_OPC_Decode, 133, 4, 239, 1, // Opcode: CMLTv8i8rz /* 39844 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 39859 /* 39849 */ MCD_OPC_CheckPredicate, 3, 246, 183, 0, // Skip to: 86948 /* 39854 */ MCD_OPC_Decode, 162, 8, 239, 1, // Opcode: FCVTNSv2f32 /* 39859 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 39874 /* 39864 */ MCD_OPC_CheckPredicate, 3, 231, 183, 0, // Skip to: 86948 /* 39869 */ MCD_OPC_Decode, 191, 23, 131, 2, // Opcode: SMAXVv8i8v /* 39874 */ MCD_OPC_FilterValue, 49, 221, 183, 0, // Skip to: 86948 /* 39879 */ MCD_OPC_CheckPredicate, 3, 216, 183, 0, // Skip to: 86948 /* 39884 */ MCD_OPC_Decode, 221, 23, 131, 2, // Opcode: SMINVv8i8v /* 39889 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 39911 /* 39894 */ MCD_OPC_CheckPredicate, 3, 201, 183, 0, // Skip to: 86948 /* 39899 */ MCD_OPC_CheckField, 21, 1, 1, 194, 183, 0, // Skip to: 86948 /* 39906 */ MCD_OPC_Decode, 212, 23, 238, 1, // Opcode: SMINPv8i8 /* 39911 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 39964 /* 39916 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 39919 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39934 /* 39924 */ MCD_OPC_CheckPredicate, 3, 171, 183, 0, // Skip to: 86948 /* 39929 */ MCD_OPC_Decode, 137, 1, 239, 1, // Opcode: ABSv8i8 /* 39934 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 39949 /* 39939 */ MCD_OPC_CheckPredicate, 3, 156, 183, 0, // Skip to: 86948 /* 39944 */ MCD_OPC_Decode, 134, 8, 239, 1, // Opcode: FCVTMSv2f32 /* 39949 */ MCD_OPC_FilterValue, 49, 146, 183, 0, // Skip to: 86948 /* 39954 */ MCD_OPC_CheckPredicate, 3, 141, 183, 0, // Skip to: 86948 /* 39959 */ MCD_OPC_Decode, 171, 1, 131, 2, // Opcode: ADDVv8i8v /* 39964 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 39986 /* 39969 */ MCD_OPC_CheckPredicate, 3, 126, 183, 0, // Skip to: 86948 /* 39974 */ MCD_OPC_CheckField, 21, 1, 1, 119, 183, 0, // Skip to: 86948 /* 39981 */ MCD_OPC_Decode, 156, 1, 238, 1, // Opcode: ADDPv8i8 /* 39986 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 40008 /* 39991 */ MCD_OPC_CheckPredicate, 3, 104, 183, 0, // Skip to: 86948 /* 39996 */ MCD_OPC_CheckField, 21, 1, 1, 97, 183, 0, // Skip to: 86948 /* 40003 */ MCD_OPC_Decode, 148, 24, 234, 1, // Opcode: SMULLv8i8_v8i16 /* 40008 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 40030 /* 40013 */ MCD_OPC_CheckPredicate, 3, 82, 183, 0, // Skip to: 86948 /* 40018 */ MCD_OPC_CheckField, 21, 1, 1, 75, 183, 0, // Skip to: 86948 /* 40025 */ MCD_OPC_Decode, 218, 9, 238, 1, // Opcode: FMAXNMv2f32 /* 40030 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 40068 /* 40035 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 40038 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 40053 /* 40043 */ MCD_OPC_CheckPredicate, 3, 52, 183, 0, // Skip to: 86948 /* 40048 */ MCD_OPC_Decode, 226, 7, 239, 1, // Opcode: FCVTASv2f32 /* 40053 */ MCD_OPC_FilterValue, 48, 42, 183, 0, // Skip to: 86948 /* 40058 */ MCD_OPC_CheckPredicate, 4, 37, 183, 0, // Skip to: 86948 /* 40063 */ MCD_OPC_Decode, 209, 9, 249, 1, // Opcode: FMAXNMVv4i16v /* 40068 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 40090 /* 40073 */ MCD_OPC_CheckPredicate, 3, 22, 183, 0, // Skip to: 86948 /* 40078 */ MCD_OPC_CheckField, 21, 1, 1, 15, 183, 0, // Skip to: 86948 /* 40085 */ MCD_OPC_Decode, 186, 10, 130, 2, // Opcode: FMLAv2f32 /* 40090 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 40112 /* 40095 */ MCD_OPC_CheckPredicate, 3, 0, 183, 0, // Skip to: 86948 /* 40100 */ MCD_OPC_CheckField, 21, 1, 1, 249, 182, 0, // Skip to: 86948 /* 40107 */ MCD_OPC_Decode, 198, 6, 238, 1, // Opcode: FADDv2f32 /* 40112 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 40134 /* 40117 */ MCD_OPC_CheckPredicate, 3, 234, 182, 0, // Skip to: 86948 /* 40122 */ MCD_OPC_CheckField, 16, 6, 33, 227, 182, 0, // Skip to: 86948 /* 40129 */ MCD_OPC_Decode, 209, 22, 239, 1, // Opcode: SCVTFv2f32 /* 40134 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 40156 /* 40139 */ MCD_OPC_CheckPredicate, 3, 212, 182, 0, // Skip to: 86948 /* 40144 */ MCD_OPC_CheckField, 21, 1, 1, 205, 182, 0, // Skip to: 86948 /* 40151 */ MCD_OPC_Decode, 129, 11, 238, 1, // Opcode: FMULXv2f32 /* 40156 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 40178 /* 40161 */ MCD_OPC_CheckPredicate, 3, 190, 182, 0, // Skip to: 86948 /* 40166 */ MCD_OPC_CheckField, 21, 1, 1, 183, 182, 0, // Skip to: 86948 /* 40173 */ MCD_OPC_Decode, 246, 20, 234, 1, // Opcode: PMULLv8i8 /* 40178 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 40200 /* 40183 */ MCD_OPC_CheckPredicate, 3, 168, 182, 0, // Skip to: 86948 /* 40188 */ MCD_OPC_CheckField, 21, 1, 1, 161, 182, 0, // Skip to: 86948 /* 40195 */ MCD_OPC_Decode, 229, 6, 238, 1, // Opcode: FCMEQv2f32 /* 40200 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 40222 /* 40205 */ MCD_OPC_CheckPredicate, 3, 146, 182, 0, // Skip to: 86948 /* 40210 */ MCD_OPC_CheckField, 21, 1, 1, 139, 182, 0, // Skip to: 86948 /* 40217 */ MCD_OPC_Decode, 244, 9, 238, 1, // Opcode: FMAXv2f32 /* 40222 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 40244 /* 40227 */ MCD_OPC_CheckPredicate, 4, 124, 182, 0, // Skip to: 86948 /* 40232 */ MCD_OPC_CheckField, 16, 6, 48, 117, 182, 0, // Skip to: 86948 /* 40239 */ MCD_OPC_Decode, 235, 9, 249, 1, // Opcode: FMAXVv4i16v /* 40244 */ MCD_OPC_FilterValue, 63, 107, 182, 0, // Skip to: 86948 /* 40249 */ MCD_OPC_CheckPredicate, 3, 102, 182, 0, // Skip to: 86948 /* 40254 */ MCD_OPC_CheckField, 21, 1, 1, 95, 182, 0, // Skip to: 86948 /* 40261 */ MCD_OPC_Decode, 213, 11, 238, 1, // Opcode: FRECPSv2f32 /* 40266 */ MCD_OPC_FilterValue, 1, 74, 5, 0, // Skip to: 41625 /* 40271 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... /* 40274 */ MCD_OPC_FilterValue, 0, 135, 1, 0, // Skip to: 40670 /* 40279 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 40282 */ MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 40486 /* 40287 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 40290 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40305 /* 40295 */ MCD_OPC_CheckPredicate, 3, 56, 182, 0, // Skip to: 86948 /* 40300 */ MCD_OPC_Decode, 254, 5, 132, 2, // Opcode: EXTv8i8 /* 40305 */ MCD_OPC_FilterValue, 1, 46, 182, 0, // Skip to: 86948 /* 40310 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 40313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40328 /* 40318 */ MCD_OPC_CheckPredicate, 3, 33, 182, 0, // Skip to: 86948 /* 40323 */ MCD_OPC_Decode, 158, 31, 234, 1, // Opcode: UADDLv8i8_v8i16 /* 40328 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40350 /* 40333 */ MCD_OPC_CheckPredicate, 3, 18, 182, 0, // Skip to: 86948 /* 40338 */ MCD_OPC_CheckField, 16, 5, 0, 11, 182, 0, // Skip to: 86948 /* 40345 */ MCD_OPC_Decode, 208, 21, 239, 1, // Opcode: REV32v8i8 /* 40350 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 40365 /* 40355 */ MCD_OPC_CheckPredicate, 3, 252, 181, 0, // Skip to: 86948 /* 40360 */ MCD_OPC_Decode, 168, 31, 242, 1, // Opcode: UADDWv8i8_v8i16 /* 40365 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 40380 /* 40370 */ MCD_OPC_CheckPredicate, 3, 237, 181, 0, // Skip to: 86948 /* 40375 */ MCD_OPC_Decode, 169, 34, 234, 1, // Opcode: USUBLv8i8_v8i16 /* 40380 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 40418 /* 40385 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 40388 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40403 /* 40393 */ MCD_OPC_CheckPredicate, 3, 214, 181, 0, // Skip to: 86948 /* 40398 */ MCD_OPC_Decode, 147, 31, 239, 1, // Opcode: UADDLPv8i8_v4i16 /* 40403 */ MCD_OPC_FilterValue, 1, 204, 181, 0, // Skip to: 86948 /* 40408 */ MCD_OPC_CheckPredicate, 3, 199, 181, 0, // Skip to: 86948 /* 40413 */ MCD_OPC_Decode, 182, 26, 244, 1, // Opcode: SQXTUNv8i8 /* 40418 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 40433 /* 40423 */ MCD_OPC_CheckPredicate, 3, 184, 181, 0, // Skip to: 86948 /* 40428 */ MCD_OPC_Decode, 175, 34, 242, 1, // Opcode: USUBWv8i8_v8i16 /* 40433 */ MCD_OPC_FilterValue, 7, 174, 181, 0, // Skip to: 86948 /* 40438 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 40441 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40456 /* 40446 */ MCD_OPC_CheckPredicate, 3, 161, 181, 0, // Skip to: 86948 /* 40451 */ MCD_OPC_Decode, 155, 34, 248, 1, // Opcode: USQADDv8i8 /* 40456 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 40471 /* 40461 */ MCD_OPC_CheckPredicate, 3, 146, 181, 0, // Skip to: 86948 /* 40466 */ MCD_OPC_Decode, 138, 23, 129, 2, // Opcode: SHLLv8i8 /* 40471 */ MCD_OPC_FilterValue, 16, 136, 181, 0, // Skip to: 86948 /* 40476 */ MCD_OPC_CheckPredicate, 3, 131, 181, 0, // Skip to: 86948 /* 40481 */ MCD_OPC_Decode, 152, 31, 249, 1, // Opcode: UADDLVv8i8v /* 40486 */ MCD_OPC_FilterValue, 1, 121, 181, 0, // Skip to: 86948 /* 40491 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 40494 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 40516 /* 40499 */ MCD_OPC_CheckPredicate, 3, 108, 181, 0, // Skip to: 86948 /* 40504 */ MCD_OPC_CheckField, 21, 1, 1, 101, 181, 0, // Skip to: 86948 /* 40511 */ MCD_OPC_Decode, 225, 31, 238, 1, // Opcode: UHADDv8i8 /* 40516 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40538 /* 40521 */ MCD_OPC_CheckPredicate, 3, 86, 181, 0, // Skip to: 86948 /* 40526 */ MCD_OPC_CheckField, 21, 1, 1, 79, 181, 0, // Skip to: 86948 /* 40533 */ MCD_OPC_Decode, 221, 32, 238, 1, // Opcode: UQADDv8i8 /* 40538 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 40560 /* 40543 */ MCD_OPC_CheckPredicate, 3, 64, 181, 0, // Skip to: 86948 /* 40548 */ MCD_OPC_CheckField, 21, 1, 1, 57, 181, 0, // Skip to: 86948 /* 40555 */ MCD_OPC_Decode, 224, 33, 238, 1, // Opcode: URHADDv8i8 /* 40560 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 40582 /* 40565 */ MCD_OPC_CheckPredicate, 3, 42, 181, 0, // Skip to: 86948 /* 40570 */ MCD_OPC_CheckField, 21, 1, 1, 35, 181, 0, // Skip to: 86948 /* 40577 */ MCD_OPC_Decode, 246, 5, 238, 1, // Opcode: EORv8i8 /* 40582 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 40604 /* 40587 */ MCD_OPC_CheckPredicate, 3, 20, 181, 0, // Skip to: 86948 /* 40592 */ MCD_OPC_CheckField, 21, 1, 1, 13, 181, 0, // Skip to: 86948 /* 40599 */ MCD_OPC_Decode, 231, 31, 238, 1, // Opcode: UHSUBv8i8 /* 40604 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 40626 /* 40609 */ MCD_OPC_CheckPredicate, 3, 254, 180, 0, // Skip to: 86948 /* 40614 */ MCD_OPC_CheckField, 21, 1, 1, 247, 180, 0, // Skip to: 86948 /* 40621 */ MCD_OPC_Decode, 207, 33, 238, 1, // Opcode: UQSUBv8i8 /* 40626 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 40648 /* 40631 */ MCD_OPC_CheckPredicate, 3, 232, 180, 0, // Skip to: 86948 /* 40636 */ MCD_OPC_CheckField, 21, 1, 1, 225, 180, 0, // Skip to: 86948 /* 40643 */ MCD_OPC_Decode, 237, 3, 238, 1, // Opcode: CMHIv8i8 /* 40648 */ MCD_OPC_FilterValue, 7, 215, 180, 0, // Skip to: 86948 /* 40653 */ MCD_OPC_CheckPredicate, 3, 210, 180, 0, // Skip to: 86948 /* 40658 */ MCD_OPC_CheckField, 21, 1, 1, 203, 180, 0, // Skip to: 86948 /* 40665 */ MCD_OPC_Decode, 245, 3, 238, 1, // Opcode: CMHSv8i8 /* 40670 */ MCD_OPC_FilterValue, 1, 115, 1, 0, // Skip to: 41046 /* 40675 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 40678 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 40700 /* 40683 */ MCD_OPC_CheckPredicate, 3, 180, 180, 0, // Skip to: 86948 /* 40688 */ MCD_OPC_CheckField, 21, 1, 1, 173, 180, 0, // Skip to: 86948 /* 40695 */ MCD_OPC_Decode, 182, 21, 252, 1, // Opcode: RADDHNv8i16_v8i8 /* 40700 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40722 /* 40705 */ MCD_OPC_CheckPredicate, 3, 158, 180, 0, // Skip to: 86948 /* 40710 */ MCD_OPC_CheckField, 21, 1, 1, 151, 180, 0, // Skip to: 86948 /* 40717 */ MCD_OPC_Decode, 136, 34, 238, 1, // Opcode: USHLv8i8 /* 40722 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 40760 /* 40727 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 40730 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 40745 /* 40735 */ MCD_OPC_CheckPredicate, 3, 128, 180, 0, // Skip to: 86948 /* 40740 */ MCD_OPC_Decode, 181, 3, 239, 1, // Opcode: CLZv8i8 /* 40745 */ MCD_OPC_FilterValue, 33, 118, 180, 0, // Skip to: 86948 /* 40750 */ MCD_OPC_CheckPredicate, 3, 113, 180, 0, // Skip to: 86948 /* 40755 */ MCD_OPC_Decode, 216, 33, 244, 1, // Opcode: UQXTNv8i8 /* 40760 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 40782 /* 40765 */ MCD_OPC_CheckPredicate, 3, 98, 180, 0, // Skip to: 86948 /* 40770 */ MCD_OPC_CheckField, 21, 1, 1, 91, 180, 0, // Skip to: 86948 /* 40777 */ MCD_OPC_Decode, 178, 33, 238, 1, // Opcode: UQSHLv8i8 /* 40782 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 40804 /* 40787 */ MCD_OPC_CheckPredicate, 3, 76, 180, 0, // Skip to: 86948 /* 40792 */ MCD_OPC_CheckField, 21, 1, 1, 69, 180, 0, // Skip to: 86948 /* 40799 */ MCD_OPC_Decode, 241, 30, 254, 1, // Opcode: UABALv8i8_v8i16 /* 40804 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 40826 /* 40809 */ MCD_OPC_CheckPredicate, 3, 54, 180, 0, // Skip to: 86948 /* 40814 */ MCD_OPC_CheckField, 21, 1, 1, 47, 180, 0, // Skip to: 86948 /* 40821 */ MCD_OPC_Decode, 232, 33, 238, 1, // Opcode: URSHLv8i8 /* 40826 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 40848 /* 40831 */ MCD_OPC_CheckPredicate, 3, 32, 180, 0, // Skip to: 86948 /* 40836 */ MCD_OPC_CheckField, 16, 6, 32, 25, 180, 0, // Skip to: 86948 /* 40843 */ MCD_OPC_Decode, 194, 20, 239, 1, // Opcode: NOTv8i8 /* 40848 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 40870 /* 40853 */ MCD_OPC_CheckPredicate, 3, 10, 180, 0, // Skip to: 86948 /* 40858 */ MCD_OPC_CheckField, 21, 1, 1, 3, 180, 0, // Skip to: 86948 /* 40865 */ MCD_OPC_Decode, 148, 33, 238, 1, // Opcode: UQRSHLv8i8 /* 40870 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 40892 /* 40875 */ MCD_OPC_CheckPredicate, 3, 244, 179, 0, // Skip to: 86948 /* 40880 */ MCD_OPC_CheckField, 21, 1, 1, 237, 179, 0, // Skip to: 86948 /* 40887 */ MCD_OPC_Decode, 245, 21, 252, 1, // Opcode: RSUBHNv8i16_v8i8 /* 40892 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 40914 /* 40897 */ MCD_OPC_CheckPredicate, 3, 222, 179, 0, // Skip to: 86948 /* 40902 */ MCD_OPC_CheckField, 21, 1, 1, 215, 179, 0, // Skip to: 86948 /* 40909 */ MCD_OPC_Decode, 133, 32, 238, 1, // Opcode: UMAXv8i8 /* 40914 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 40936 /* 40919 */ MCD_OPC_CheckPredicate, 3, 200, 179, 0, // Skip to: 86948 /* 40924 */ MCD_OPC_CheckField, 16, 6, 32, 193, 179, 0, // Skip to: 86948 /* 40931 */ MCD_OPC_Decode, 141, 31, 248, 1, // Opcode: UADALPv8i8_v4i16 /* 40936 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 40958 /* 40941 */ MCD_OPC_CheckPredicate, 3, 178, 179, 0, // Skip to: 86948 /* 40946 */ MCD_OPC_CheckField, 21, 1, 1, 171, 179, 0, // Skip to: 86948 /* 40953 */ MCD_OPC_Decode, 162, 32, 238, 1, // Opcode: UMINv8i8 /* 40958 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 40980 /* 40963 */ MCD_OPC_CheckPredicate, 3, 156, 179, 0, // Skip to: 86948 /* 40968 */ MCD_OPC_CheckField, 21, 1, 1, 149, 179, 0, // Skip to: 86948 /* 40975 */ MCD_OPC_Decode, 253, 30, 234, 1, // Opcode: UABDLv8i8_v8i16 /* 40980 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 41002 /* 40985 */ MCD_OPC_CheckPredicate, 3, 134, 179, 0, // Skip to: 86948 /* 40990 */ MCD_OPC_CheckField, 21, 1, 1, 127, 179, 0, // Skip to: 86948 /* 40997 */ MCD_OPC_Decode, 135, 31, 238, 1, // Opcode: UABDv8i8 /* 41002 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 41024 /* 41007 */ MCD_OPC_CheckPredicate, 3, 112, 179, 0, // Skip to: 86948 /* 41012 */ MCD_OPC_CheckField, 16, 6, 32, 105, 179, 0, // Skip to: 86948 /* 41019 */ MCD_OPC_Decode, 157, 25, 239, 1, // Opcode: SQNEGv8i8 /* 41024 */ MCD_OPC_FilterValue, 15, 95, 179, 0, // Skip to: 86948 /* 41029 */ MCD_OPC_CheckPredicate, 3, 90, 179, 0, // Skip to: 86948 /* 41034 */ MCD_OPC_CheckField, 21, 1, 1, 83, 179, 0, // Skip to: 86948 /* 41041 */ MCD_OPC_Decode, 247, 30, 130, 2, // Opcode: UABAv8i8 /* 41046 */ MCD_OPC_FilterValue, 2, 90, 1, 0, // Skip to: 41397 /* 41051 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 41054 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41076 /* 41059 */ MCD_OPC_CheckPredicate, 3, 60, 179, 0, // Skip to: 86948 /* 41064 */ MCD_OPC_CheckField, 21, 1, 1, 53, 179, 0, // Skip to: 86948 /* 41071 */ MCD_OPC_Decode, 172, 32, 254, 1, // Opcode: UMLALv8i8_v8i16 /* 41076 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 41098 /* 41081 */ MCD_OPC_CheckPredicate, 3, 38, 179, 0, // Skip to: 86948 /* 41086 */ MCD_OPC_CheckField, 21, 1, 1, 31, 179, 0, // Skip to: 86948 /* 41093 */ MCD_OPC_Decode, 134, 30, 238, 1, // Opcode: SUBv8i8 /* 41098 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 41136 /* 41103 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 41106 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41121 /* 41111 */ MCD_OPC_CheckPredicate, 3, 8, 179, 0, // Skip to: 86948 /* 41116 */ MCD_OPC_Decode, 213, 3, 239, 1, // Opcode: CMGEv8i8rz /* 41121 */ MCD_OPC_FilterValue, 33, 254, 178, 0, // Skip to: 86948 /* 41126 */ MCD_OPC_CheckPredicate, 3, 249, 178, 0, // Skip to: 86948 /* 41131 */ MCD_OPC_Decode, 230, 11, 239, 1, // Opcode: FRINTAv2f32 /* 41136 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 41158 /* 41141 */ MCD_OPC_CheckPredicate, 3, 234, 178, 0, // Skip to: 86948 /* 41146 */ MCD_OPC_CheckField, 21, 1, 1, 227, 178, 0, // Skip to: 86948 /* 41153 */ MCD_OPC_Decode, 196, 3, 238, 1, // Opcode: CMEQv8i8 /* 41158 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41180 /* 41163 */ MCD_OPC_CheckPredicate, 3, 212, 178, 0, // Skip to: 86948 /* 41168 */ MCD_OPC_CheckField, 21, 1, 1, 205, 178, 0, // Skip to: 86948 /* 41175 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: MLSv8i8 /* 41180 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 41218 /* 41185 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 41188 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41203 /* 41193 */ MCD_OPC_CheckPredicate, 3, 182, 178, 0, // Skip to: 86948 /* 41198 */ MCD_OPC_Decode, 253, 3, 239, 1, // Opcode: CMLEv8i8rz /* 41203 */ MCD_OPC_FilterValue, 33, 172, 178, 0, // Skip to: 86948 /* 41208 */ MCD_OPC_CheckPredicate, 3, 167, 178, 0, // Skip to: 86948 /* 41213 */ MCD_OPC_Decode, 157, 12, 239, 1, // Opcode: FRINTXv2f32 /* 41218 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 41240 /* 41223 */ MCD_OPC_CheckPredicate, 3, 152, 178, 0, // Skip to: 86948 /* 41228 */ MCD_OPC_CheckField, 21, 1, 1, 145, 178, 0, // Skip to: 86948 /* 41235 */ MCD_OPC_Decode, 248, 20, 238, 1, // Opcode: PMULv8i8 /* 41240 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 41262 /* 41245 */ MCD_OPC_CheckPredicate, 3, 130, 178, 0, // Skip to: 86948 /* 41250 */ MCD_OPC_CheckField, 21, 1, 1, 123, 178, 0, // Skip to: 86948 /* 41257 */ MCD_OPC_Decode, 182, 32, 254, 1, // Opcode: UMLSLv8i8_v8i16 /* 41262 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 41284 /* 41267 */ MCD_OPC_CheckPredicate, 3, 108, 178, 0, // Skip to: 86948 /* 41272 */ MCD_OPC_CheckField, 21, 1, 1, 101, 178, 0, // Skip to: 86948 /* 41279 */ MCD_OPC_Decode, 238, 31, 238, 1, // Opcode: UMAXPv8i8 /* 41284 */ MCD_OPC_FilterValue, 10, 48, 0, 0, // Skip to: 41337 /* 41289 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 41292 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 41307 /* 41297 */ MCD_OPC_CheckPredicate, 3, 78, 178, 0, // Skip to: 86948 /* 41302 */ MCD_OPC_Decode, 176, 8, 239, 1, // Opcode: FCVTNUv2f32 /* 41307 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 41322 /* 41312 */ MCD_OPC_CheckPredicate, 3, 63, 178, 0, // Skip to: 86948 /* 41317 */ MCD_OPC_Decode, 247, 31, 131, 2, // Opcode: UMAXVv8i8v /* 41322 */ MCD_OPC_FilterValue, 49, 53, 178, 0, // Skip to: 86948 /* 41327 */ MCD_OPC_CheckPredicate, 3, 48, 178, 0, // Skip to: 86948 /* 41332 */ MCD_OPC_Decode, 148, 32, 131, 2, // Opcode: UMINVv8i8v /* 41337 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 41359 /* 41342 */ MCD_OPC_CheckPredicate, 3, 33, 178, 0, // Skip to: 86948 /* 41347 */ MCD_OPC_CheckField, 21, 1, 1, 26, 178, 0, // Skip to: 86948 /* 41354 */ MCD_OPC_Decode, 139, 32, 238, 1, // Opcode: UMINPv8i8 /* 41359 */ MCD_OPC_FilterValue, 14, 16, 178, 0, // Skip to: 86948 /* 41364 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 41367 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41382 /* 41372 */ MCD_OPC_CheckPredicate, 3, 3, 178, 0, // Skip to: 86948 /* 41377 */ MCD_OPC_Decode, 186, 20, 239, 1, // Opcode: NEGv8i8 /* 41382 */ MCD_OPC_FilterValue, 33, 249, 177, 0, // Skip to: 86948 /* 41387 */ MCD_OPC_CheckPredicate, 3, 244, 177, 0, // Skip to: 86948 /* 41392 */ MCD_OPC_Decode, 148, 8, 239, 1, // Opcode: FCVTMUv2f32 /* 41397 */ MCD_OPC_FilterValue, 3, 234, 177, 0, // Skip to: 86948 /* 41402 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 41405 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41427 /* 41410 */ MCD_OPC_CheckPredicate, 3, 221, 177, 0, // Skip to: 86948 /* 41415 */ MCD_OPC_CheckField, 21, 1, 1, 214, 177, 0, // Skip to: 86948 /* 41422 */ MCD_OPC_Decode, 202, 32, 234, 1, // Opcode: UMULLv8i8_v8i16 /* 41427 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 41449 /* 41432 */ MCD_OPC_CheckPredicate, 3, 199, 177, 0, // Skip to: 86948 /* 41437 */ MCD_OPC_CheckField, 21, 1, 1, 192, 177, 0, // Skip to: 86948 /* 41444 */ MCD_OPC_Decode, 197, 9, 238, 1, // Opcode: FMAXNMPv2f32 /* 41449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 41471 /* 41454 */ MCD_OPC_CheckPredicate, 3, 177, 177, 0, // Skip to: 86948 /* 41459 */ MCD_OPC_CheckField, 16, 6, 33, 170, 177, 0, // Skip to: 86948 /* 41466 */ MCD_OPC_Decode, 240, 7, 239, 1, // Opcode: FCVTAUv2f32 /* 41471 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41493 /* 41476 */ MCD_OPC_CheckPredicate, 3, 155, 177, 0, // Skip to: 86948 /* 41481 */ MCD_OPC_CheckField, 21, 1, 1, 148, 177, 0, // Skip to: 86948 /* 41488 */ MCD_OPC_Decode, 177, 6, 238, 1, // Opcode: FADDPv2f32 /* 41493 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 41515 /* 41498 */ MCD_OPC_CheckPredicate, 3, 133, 177, 0, // Skip to: 86948 /* 41503 */ MCD_OPC_CheckField, 16, 6, 33, 126, 177, 0, // Skip to: 86948 /* 41510 */ MCD_OPC_Decode, 196, 31, 239, 1, // Opcode: UCVTFv2f32 /* 41515 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 41537 /* 41520 */ MCD_OPC_CheckPredicate, 3, 111, 177, 0, // Skip to: 86948 /* 41525 */ MCD_OPC_CheckField, 21, 1, 1, 104, 177, 0, // Skip to: 86948 /* 41532 */ MCD_OPC_Decode, 154, 11, 238, 1, // Opcode: FMULv2f32 /* 41537 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 41559 /* 41542 */ MCD_OPC_CheckPredicate, 3, 89, 177, 0, // Skip to: 86948 /* 41547 */ MCD_OPC_CheckField, 21, 1, 1, 82, 177, 0, // Skip to: 86948 /* 41554 */ MCD_OPC_Decode, 251, 6, 238, 1, // Opcode: FCMGEv2f32 /* 41559 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 41581 /* 41564 */ MCD_OPC_CheckPredicate, 3, 67, 177, 0, // Skip to: 86948 /* 41569 */ MCD_OPC_CheckField, 21, 1, 1, 60, 177, 0, // Skip to: 86948 /* 41576 */ MCD_OPC_Decode, 156, 6, 238, 1, // Opcode: FACGEv2f32 /* 41581 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 41603 /* 41586 */ MCD_OPC_CheckPredicate, 3, 45, 177, 0, // Skip to: 86948 /* 41591 */ MCD_OPC_CheckField, 21, 1, 1, 38, 177, 0, // Skip to: 86948 /* 41598 */ MCD_OPC_Decode, 223, 9, 238, 1, // Opcode: FMAXPv2f32 /* 41603 */ MCD_OPC_FilterValue, 15, 28, 177, 0, // Skip to: 86948 /* 41608 */ MCD_OPC_CheckPredicate, 3, 23, 177, 0, // Skip to: 86948 /* 41613 */ MCD_OPC_CheckField, 21, 1, 1, 16, 177, 0, // Skip to: 86948 /* 41620 */ MCD_OPC_Decode, 175, 9, 238, 1, // Opcode: FDIVv2f32 /* 41625 */ MCD_OPC_FilterValue, 2, 109, 8, 0, // Skip to: 43787 /* 41630 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 41633 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 41671 /* 41638 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 41641 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 41656 /* 41646 */ MCD_OPC_CheckPredicate, 3, 241, 176, 0, // Skip to: 86948 /* 41651 */ MCD_OPC_Decode, 182, 30, 133, 2, // Opcode: TBLv16i8One /* 41656 */ MCD_OPC_FilterValue, 1, 231, 176, 0, // Skip to: 86948 /* 41661 */ MCD_OPC_CheckPredicate, 3, 226, 176, 0, // Skip to: 86948 /* 41666 */ MCD_OPC_Decode, 163, 22, 133, 2, // Opcode: SADDLv16i8_v8i16 /* 41671 */ MCD_OPC_FilterValue, 1, 109, 0, 0, // Skip to: 41785 /* 41676 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 41679 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 41770 /* 41684 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 41687 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 41755 /* 41692 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 41695 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 41740 /* 41700 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 41703 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41725 /* 41708 */ MCD_OPC_CheckPredicate, 3, 179, 176, 0, // Skip to: 86948 /* 41713 */ MCD_OPC_CheckField, 19, 1, 1, 172, 176, 0, // Skip to: 86948 /* 41720 */ MCD_OPC_Decode, 213, 5, 134, 2, // Opcode: DUPv2i64lane /* 41725 */ MCD_OPC_FilterValue, 1, 162, 176, 0, // Skip to: 86948 /* 41730 */ MCD_OPC_CheckPredicate, 3, 157, 176, 0, // Skip to: 86948 /* 41735 */ MCD_OPC_Decode, 217, 5, 135, 2, // Opcode: DUPv4i32lane /* 41740 */ MCD_OPC_FilterValue, 1, 147, 176, 0, // Skip to: 86948 /* 41745 */ MCD_OPC_CheckPredicate, 3, 142, 176, 0, // Skip to: 86948 /* 41750 */ MCD_OPC_Decode, 219, 5, 136, 2, // Opcode: DUPv8i16lane /* 41755 */ MCD_OPC_FilterValue, 1, 132, 176, 0, // Skip to: 86948 /* 41760 */ MCD_OPC_CheckPredicate, 3, 127, 176, 0, // Skip to: 86948 /* 41765 */ MCD_OPC_Decode, 209, 5, 137, 2, // Opcode: DUPv16i8lane /* 41770 */ MCD_OPC_FilterValue, 1, 117, 176, 0, // Skip to: 86948 /* 41775 */ MCD_OPC_CheckPredicate, 3, 112, 176, 0, // Skip to: 86948 /* 41780 */ MCD_OPC_Decode, 255, 22, 133, 2, // Opcode: SHADDv16i8 /* 41785 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 41807 /* 41790 */ MCD_OPC_CheckPredicate, 3, 97, 176, 0, // Skip to: 86948 /* 41795 */ MCD_OPC_CheckField, 16, 6, 32, 90, 176, 0, // Skip to: 86948 /* 41802 */ MCD_OPC_Decode, 209, 21, 138, 2, // Opcode: REV64v16i8 /* 41807 */ MCD_OPC_FilterValue, 3, 109, 0, 0, // Skip to: 41921 /* 41812 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 41815 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 41906 /* 41820 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 41823 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 41891 /* 41828 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 41831 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 41876 /* 41836 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 41839 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41861 /* 41844 */ MCD_OPC_CheckPredicate, 3, 43, 176, 0, // Skip to: 86948 /* 41849 */ MCD_OPC_CheckField, 19, 1, 1, 36, 176, 0, // Skip to: 86948 /* 41856 */ MCD_OPC_Decode, 212, 5, 139, 2, // Opcode: DUPv2i64gpr /* 41861 */ MCD_OPC_FilterValue, 1, 26, 176, 0, // Skip to: 86948 /* 41866 */ MCD_OPC_CheckPredicate, 3, 21, 176, 0, // Skip to: 86948 /* 41871 */ MCD_OPC_Decode, 216, 5, 140, 2, // Opcode: DUPv4i32gpr /* 41876 */ MCD_OPC_FilterValue, 1, 11, 176, 0, // Skip to: 86948 /* 41881 */ MCD_OPC_CheckPredicate, 3, 6, 176, 0, // Skip to: 86948 /* 41886 */ MCD_OPC_Decode, 218, 5, 140, 2, // Opcode: DUPv8i16gpr /* 41891 */ MCD_OPC_FilterValue, 1, 252, 175, 0, // Skip to: 86948 /* 41896 */ MCD_OPC_CheckPredicate, 3, 247, 175, 0, // Skip to: 86948 /* 41901 */ MCD_OPC_Decode, 208, 5, 140, 2, // Opcode: DUPv16i8gpr /* 41906 */ MCD_OPC_FilterValue, 1, 237, 175, 0, // Skip to: 86948 /* 41911 */ MCD_OPC_CheckPredicate, 3, 232, 175, 0, // Skip to: 86948 /* 41916 */ MCD_OPC_Decode, 172, 24, 133, 2, // Opcode: SQADDv16i8 /* 41921 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 41959 /* 41926 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 41929 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 41944 /* 41934 */ MCD_OPC_CheckPredicate, 3, 209, 175, 0, // Skip to: 86948 /* 41939 */ MCD_OPC_Decode, 192, 30, 141, 2, // Opcode: TBXv16i8One /* 41944 */ MCD_OPC_FilterValue, 1, 199, 175, 0, // Skip to: 86948 /* 41949 */ MCD_OPC_CheckPredicate, 3, 194, 175, 0, // Skip to: 86948 /* 41954 */ MCD_OPC_Decode, 172, 22, 133, 2, // Opcode: SADDWv16i8_v8i16 /* 41959 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41981 /* 41964 */ MCD_OPC_CheckPredicate, 3, 179, 175, 0, // Skip to: 86948 /* 41969 */ MCD_OPC_CheckField, 21, 1, 1, 172, 175, 0, // Skip to: 86948 /* 41976 */ MCD_OPC_Decode, 183, 26, 133, 2, // Opcode: SRHADDv16i8 /* 41981 */ MCD_OPC_FilterValue, 6, 40, 0, 0, // Skip to: 42026 /* 41986 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 41989 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42004 /* 41994 */ MCD_OPC_CheckPredicate, 3, 149, 175, 0, // Skip to: 86948 /* 41999 */ MCD_OPC_Decode, 196, 34, 133, 2, // Opcode: UZP1v16i8 /* 42004 */ MCD_OPC_FilterValue, 1, 139, 175, 0, // Skip to: 86948 /* 42009 */ MCD_OPC_CheckPredicate, 3, 134, 175, 0, // Skip to: 86948 /* 42014 */ MCD_OPC_CheckField, 16, 5, 0, 127, 175, 0, // Skip to: 86948 /* 42021 */ MCD_OPC_Decode, 202, 21, 138, 2, // Opcode: REV16v16i8 /* 42026 */ MCD_OPC_FilterValue, 7, 109, 0, 0, // Skip to: 42140 /* 42031 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42034 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 42125 /* 42039 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 42042 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 42110 /* 42047 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 42050 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 42095 /* 42055 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 42058 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42080 /* 42063 */ MCD_OPC_CheckPredicate, 3, 80, 175, 0, // Skip to: 86948 /* 42068 */ MCD_OPC_CheckField, 19, 1, 1, 73, 175, 0, // Skip to: 86948 /* 42075 */ MCD_OPC_Decode, 158, 14, 142, 2, // Opcode: INSvi64gpr /* 42080 */ MCD_OPC_FilterValue, 1, 63, 175, 0, // Skip to: 86948 /* 42085 */ MCD_OPC_CheckPredicate, 3, 58, 175, 0, // Skip to: 86948 /* 42090 */ MCD_OPC_Decode, 156, 14, 143, 2, // Opcode: INSvi32gpr /* 42095 */ MCD_OPC_FilterValue, 1, 48, 175, 0, // Skip to: 86948 /* 42100 */ MCD_OPC_CheckPredicate, 3, 43, 175, 0, // Skip to: 86948 /* 42105 */ MCD_OPC_Decode, 154, 14, 144, 2, // Opcode: INSvi16gpr /* 42110 */ MCD_OPC_FilterValue, 1, 33, 175, 0, // Skip to: 86948 /* 42115 */ MCD_OPC_CheckPredicate, 3, 28, 175, 0, // Skip to: 86948 /* 42120 */ MCD_OPC_Decode, 160, 14, 145, 2, // Opcode: INSvi8gpr /* 42125 */ MCD_OPC_FilterValue, 1, 18, 175, 0, // Skip to: 86948 /* 42130 */ MCD_OPC_CheckPredicate, 3, 13, 175, 0, // Skip to: 86948 /* 42135 */ MCD_OPC_Decode, 252, 1, 133, 2, // Opcode: ANDv16i8 /* 42140 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 42178 /* 42145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42148 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42163 /* 42153 */ MCD_OPC_CheckPredicate, 3, 246, 174, 0, // Skip to: 86948 /* 42158 */ MCD_OPC_Decode, 184, 30, 146, 2, // Opcode: TBLv16i8Two /* 42163 */ MCD_OPC_FilterValue, 1, 236, 174, 0, // Skip to: 86948 /* 42168 */ MCD_OPC_CheckPredicate, 3, 231, 174, 0, // Skip to: 86948 /* 42173 */ MCD_OPC_Decode, 161, 27, 133, 2, // Opcode: SSUBLv16i8_v8i16 /* 42178 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 42200 /* 42183 */ MCD_OPC_CheckPredicate, 3, 216, 174, 0, // Skip to: 86948 /* 42188 */ MCD_OPC_CheckField, 21, 1, 1, 209, 174, 0, // Skip to: 86948 /* 42195 */ MCD_OPC_Decode, 153, 23, 133, 2, // Opcode: SHSUBv16i8 /* 42200 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 42261 /* 42205 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42208 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42223 /* 42213 */ MCD_OPC_CheckPredicate, 3, 186, 174, 0, // Skip to: 86948 /* 42218 */ MCD_OPC_Decode, 213, 30, 133, 2, // Opcode: TRN1v16i8 /* 42223 */ MCD_OPC_FilterValue, 1, 176, 174, 0, // Skip to: 86948 /* 42228 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 42231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42246 /* 42236 */ MCD_OPC_CheckPredicate, 3, 163, 174, 0, // Skip to: 86948 /* 42241 */ MCD_OPC_Decode, 152, 22, 138, 2, // Opcode: SADDLPv16i8_v8i16 /* 42246 */ MCD_OPC_FilterValue, 1, 153, 174, 0, // Skip to: 86948 /* 42251 */ MCD_OPC_CheckPredicate, 3, 148, 174, 0, // Skip to: 86948 /* 42256 */ MCD_OPC_Decode, 255, 34, 147, 2, // Opcode: XTNv16i8 /* 42261 */ MCD_OPC_FilterValue, 11, 86, 0, 0, // Skip to: 42352 /* 42266 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42269 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 42337 /* 42274 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 42277 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 42322 /* 42282 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 42285 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42307 /* 42290 */ MCD_OPC_CheckPredicate, 3, 109, 174, 0, // Skip to: 86948 /* 42295 */ MCD_OPC_CheckField, 18, 1, 1, 102, 174, 0, // Skip to: 86948 /* 42302 */ MCD_OPC_Decode, 130, 24, 148, 2, // Opcode: SMOVvi32to64 /* 42307 */ MCD_OPC_FilterValue, 1, 92, 174, 0, // Skip to: 86948 /* 42312 */ MCD_OPC_CheckPredicate, 3, 87, 174, 0, // Skip to: 86948 /* 42317 */ MCD_OPC_Decode, 129, 24, 149, 2, // Opcode: SMOVvi16to64 /* 42322 */ MCD_OPC_FilterValue, 1, 77, 174, 0, // Skip to: 86948 /* 42327 */ MCD_OPC_CheckPredicate, 3, 72, 174, 0, // Skip to: 86948 /* 42332 */ MCD_OPC_Decode, 132, 24, 150, 2, // Opcode: SMOVvi8to64 /* 42337 */ MCD_OPC_FilterValue, 1, 62, 174, 0, // Skip to: 86948 /* 42342 */ MCD_OPC_CheckPredicate, 3, 57, 174, 0, // Skip to: 86948 /* 42347 */ MCD_OPC_Decode, 154, 26, 133, 2, // Opcode: SQSUBv16i8 /* 42352 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 42390 /* 42357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42375 /* 42365 */ MCD_OPC_CheckPredicate, 3, 34, 174, 0, // Skip to: 86948 /* 42370 */ MCD_OPC_Decode, 194, 30, 151, 2, // Opcode: TBXv16i8Two /* 42375 */ MCD_OPC_FilterValue, 1, 24, 174, 0, // Skip to: 86948 /* 42380 */ MCD_OPC_CheckPredicate, 3, 19, 174, 0, // Skip to: 86948 /* 42385 */ MCD_OPC_Decode, 167, 27, 133, 2, // Opcode: SSUBWv16i8_v8i16 /* 42390 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 42412 /* 42395 */ MCD_OPC_CheckPredicate, 3, 4, 174, 0, // Skip to: 86948 /* 42400 */ MCD_OPC_CheckField, 21, 1, 1, 253, 173, 0, // Skip to: 86948 /* 42407 */ MCD_OPC_Decode, 214, 3, 133, 2, // Opcode: CMGTv16i8 /* 42412 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 42473 /* 42417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42420 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42435 /* 42425 */ MCD_OPC_CheckPredicate, 3, 230, 173, 0, // Skip to: 86948 /* 42430 */ MCD_OPC_Decode, 141, 35, 133, 2, // Opcode: ZIP1v16i8 /* 42435 */ MCD_OPC_FilterValue, 1, 220, 173, 0, // Skip to: 86948 /* 42440 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 42443 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42458 /* 42448 */ MCD_OPC_CheckPredicate, 3, 207, 173, 0, // Skip to: 86948 /* 42453 */ MCD_OPC_Decode, 141, 30, 147, 2, // Opcode: SUQADDv16i8 /* 42458 */ MCD_OPC_FilterValue, 16, 197, 173, 0, // Skip to: 86948 /* 42463 */ MCD_OPC_CheckPredicate, 3, 192, 173, 0, // Skip to: 86948 /* 42468 */ MCD_OPC_Decode, 158, 22, 152, 2, // Opcode: SADDLVv16i8v /* 42473 */ MCD_OPC_FilterValue, 15, 40, 0, 0, // Skip to: 42518 /* 42478 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42481 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42503 /* 42486 */ MCD_OPC_CheckPredicate, 3, 169, 173, 0, // Skip to: 86948 /* 42491 */ MCD_OPC_CheckField, 16, 4, 8, 162, 173, 0, // Skip to: 86948 /* 42498 */ MCD_OPC_Decode, 185, 32, 153, 2, // Opcode: UMOVvi64 /* 42503 */ MCD_OPC_FilterValue, 1, 152, 173, 0, // Skip to: 86948 /* 42508 */ MCD_OPC_CheckPredicate, 3, 147, 173, 0, // Skip to: 86948 /* 42513 */ MCD_OPC_Decode, 198, 3, 133, 2, // Opcode: CMGEv16i8 /* 42518 */ MCD_OPC_FilterValue, 16, 33, 0, 0, // Skip to: 42556 /* 42523 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42526 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42541 /* 42531 */ MCD_OPC_CheckPredicate, 3, 124, 173, 0, // Skip to: 86948 /* 42536 */ MCD_OPC_Decode, 183, 30, 154, 2, // Opcode: TBLv16i8Three /* 42541 */ MCD_OPC_FilterValue, 1, 114, 173, 0, // Skip to: 86948 /* 42546 */ MCD_OPC_CheckPredicate, 3, 109, 173, 0, // Skip to: 86948 /* 42551 */ MCD_OPC_Decode, 146, 1, 141, 2, // Opcode: ADDHNv8i16_v16i8 /* 42556 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 42578 /* 42561 */ MCD_OPC_CheckPredicate, 3, 94, 173, 0, // Skip to: 86948 /* 42566 */ MCD_OPC_CheckField, 21, 1, 1, 87, 173, 0, // Skip to: 86948 /* 42573 */ MCD_OPC_Decode, 227, 26, 133, 2, // Opcode: SSHLv16i8 /* 42578 */ MCD_OPC_FilterValue, 18, 48, 0, 0, // Skip to: 42631 /* 42583 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 42586 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 42601 /* 42591 */ MCD_OPC_CheckPredicate, 3, 64, 173, 0, // Skip to: 86948 /* 42596 */ MCD_OPC_Decode, 164, 3, 138, 2, // Opcode: CLSv16i8 /* 42601 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 42616 /* 42606 */ MCD_OPC_CheckPredicate, 3, 49, 173, 0, // Skip to: 86948 /* 42611 */ MCD_OPC_Decode, 165, 26, 147, 2, // Opcode: SQXTNv16i8 /* 42616 */ MCD_OPC_FilterValue, 40, 39, 173, 0, // Skip to: 86948 /* 42621 */ MCD_OPC_CheckPredicate, 5, 34, 173, 0, // Skip to: 86948 /* 42626 */ MCD_OPC_Decode, 223, 1, 147, 2, // Opcode: AESErr /* 42631 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 42653 /* 42636 */ MCD_OPC_CheckPredicate, 3, 19, 173, 0, // Skip to: 86948 /* 42641 */ MCD_OPC_CheckField, 21, 1, 1, 12, 173, 0, // Skip to: 86948 /* 42648 */ MCD_OPC_Decode, 238, 25, 133, 2, // Opcode: SQSHLv16i8 /* 42653 */ MCD_OPC_FilterValue, 20, 33, 0, 0, // Skip to: 42691 /* 42658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42676 /* 42666 */ MCD_OPC_CheckPredicate, 3, 245, 172, 0, // Skip to: 86948 /* 42671 */ MCD_OPC_Decode, 193, 30, 155, 2, // Opcode: TBXv16i8Three /* 42676 */ MCD_OPC_FilterValue, 1, 235, 172, 0, // Skip to: 86948 /* 42681 */ MCD_OPC_CheckPredicate, 3, 230, 172, 0, // Skip to: 86948 /* 42686 */ MCD_OPC_Decode, 246, 21, 141, 2, // Opcode: SABALv16i8_v8i16 /* 42691 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 42713 /* 42696 */ MCD_OPC_CheckPredicate, 3, 215, 172, 0, // Skip to: 86948 /* 42701 */ MCD_OPC_CheckField, 21, 1, 1, 208, 172, 0, // Skip to: 86948 /* 42708 */ MCD_OPC_Decode, 197, 26, 133, 2, // Opcode: SRSHLv16i8 /* 42713 */ MCD_OPC_FilterValue, 22, 56, 0, 0, // Skip to: 42774 /* 42718 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42721 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42736 /* 42726 */ MCD_OPC_CheckPredicate, 3, 185, 172, 0, // Skip to: 86948 /* 42731 */ MCD_OPC_Decode, 211, 34, 133, 2, // Opcode: UZP2v16i8 /* 42736 */ MCD_OPC_FilterValue, 1, 175, 172, 0, // Skip to: 86948 /* 42741 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 42744 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42759 /* 42749 */ MCD_OPC_CheckPredicate, 3, 162, 172, 0, // Skip to: 86948 /* 42754 */ MCD_OPC_Decode, 129, 5, 138, 2, // Opcode: CNTv16i8 /* 42759 */ MCD_OPC_FilterValue, 8, 152, 172, 0, // Skip to: 86948 /* 42764 */ MCD_OPC_CheckPredicate, 5, 147, 172, 0, // Skip to: 86948 /* 42769 */ MCD_OPC_Decode, 222, 1, 147, 2, // Opcode: AESDrr /* 42774 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 42796 /* 42779 */ MCD_OPC_CheckPredicate, 3, 132, 172, 0, // Skip to: 86948 /* 42784 */ MCD_OPC_CheckField, 21, 1, 1, 125, 172, 0, // Skip to: 86948 /* 42791 */ MCD_OPC_Decode, 194, 25, 133, 2, // Opcode: SQRSHLv16i8 /* 42796 */ MCD_OPC_FilterValue, 24, 33, 0, 0, // Skip to: 42834 /* 42801 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42804 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42819 /* 42809 */ MCD_OPC_CheckPredicate, 3, 102, 172, 0, // Skip to: 86948 /* 42814 */ MCD_OPC_Decode, 181, 30, 156, 2, // Opcode: TBLv16i8Four /* 42819 */ MCD_OPC_FilterValue, 1, 92, 172, 0, // Skip to: 86948 /* 42824 */ MCD_OPC_CheckPredicate, 3, 87, 172, 0, // Skip to: 86948 /* 42829 */ MCD_OPC_Decode, 215, 29, 141, 2, // Opcode: SUBHNv8i16_v16i8 /* 42834 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 42856 /* 42839 */ MCD_OPC_CheckPredicate, 3, 72, 172, 0, // Skip to: 86948 /* 42844 */ MCD_OPC_CheckField, 21, 1, 1, 65, 172, 0, // Skip to: 86948 /* 42851 */ MCD_OPC_Decode, 200, 23, 133, 2, // Opcode: SMAXv16i8 /* 42856 */ MCD_OPC_FilterValue, 26, 71, 0, 0, // Skip to: 42932 /* 42861 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42864 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42879 /* 42869 */ MCD_OPC_CheckPredicate, 3, 42, 172, 0, // Skip to: 86948 /* 42874 */ MCD_OPC_Decode, 228, 30, 133, 2, // Opcode: TRN2v16i8 /* 42879 */ MCD_OPC_FilterValue, 1, 32, 172, 0, // Skip to: 86948 /* 42884 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 42887 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42902 /* 42892 */ MCD_OPC_CheckPredicate, 3, 19, 172, 0, // Skip to: 86948 /* 42897 */ MCD_OPC_Decode, 146, 22, 147, 2, // Opcode: SADALPv16i8_v8i16 /* 42902 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 42917 /* 42907 */ MCD_OPC_CheckPredicate, 3, 4, 172, 0, // Skip to: 86948 /* 42912 */ MCD_OPC_Decode, 184, 8, 147, 2, // Opcode: FCVTNv8i16 /* 42917 */ MCD_OPC_FilterValue, 8, 250, 171, 0, // Skip to: 86948 /* 42922 */ MCD_OPC_CheckPredicate, 5, 245, 171, 0, // Skip to: 86948 /* 42927 */ MCD_OPC_Decode, 226, 1, 138, 2, // Opcode: AESMCrr /* 42932 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 42954 /* 42937 */ MCD_OPC_CheckPredicate, 3, 230, 171, 0, // Skip to: 86948 /* 42942 */ MCD_OPC_CheckField, 21, 1, 1, 223, 171, 0, // Skip to: 86948 /* 42949 */ MCD_OPC_Decode, 230, 23, 133, 2, // Opcode: SMINv16i8 /* 42954 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 42992 /* 42959 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 42962 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42977 /* 42967 */ MCD_OPC_CheckPredicate, 3, 200, 171, 0, // Skip to: 86948 /* 42972 */ MCD_OPC_Decode, 191, 30, 157, 2, // Opcode: TBXv16i8Four /* 42977 */ MCD_OPC_FilterValue, 1, 190, 171, 0, // Skip to: 86948 /* 42982 */ MCD_OPC_CheckPredicate, 3, 185, 171, 0, // Skip to: 86948 /* 42987 */ MCD_OPC_Decode, 130, 22, 133, 2, // Opcode: SABDLv16i8_v8i16 /* 42992 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 43014 /* 42997 */ MCD_OPC_CheckPredicate, 3, 170, 171, 0, // Skip to: 86948 /* 43002 */ MCD_OPC_CheckField, 21, 1, 1, 163, 171, 0, // Skip to: 86948 /* 43009 */ MCD_OPC_Decode, 140, 22, 133, 2, // Opcode: SABDv16i8 /* 43014 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 43090 /* 43019 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 43022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43037 /* 43027 */ MCD_OPC_CheckPredicate, 3, 140, 171, 0, // Skip to: 86948 /* 43032 */ MCD_OPC_Decode, 156, 35, 133, 2, // Opcode: ZIP2v16i8 /* 43037 */ MCD_OPC_FilterValue, 1, 130, 171, 0, // Skip to: 86948 /* 43042 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 43045 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43060 /* 43050 */ MCD_OPC_CheckPredicate, 3, 117, 171, 0, // Skip to: 86948 /* 43055 */ MCD_OPC_Decode, 153, 24, 138, 2, // Opcode: SQABSv16i8 /* 43060 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 43075 /* 43065 */ MCD_OPC_CheckPredicate, 3, 102, 171, 0, // Skip to: 86948 /* 43070 */ MCD_OPC_Decode, 252, 7, 138, 2, // Opcode: FCVTLv8i16 /* 43075 */ MCD_OPC_FilterValue, 8, 92, 171, 0, // Skip to: 86948 /* 43080 */ MCD_OPC_CheckPredicate, 5, 87, 171, 0, // Skip to: 86948 /* 43085 */ MCD_OPC_Decode, 224, 1, 138, 2, // Opcode: AESIMCrr /* 43090 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 43112 /* 43095 */ MCD_OPC_CheckPredicate, 3, 72, 171, 0, // Skip to: 86948 /* 43100 */ MCD_OPC_CheckField, 21, 1, 1, 65, 171, 0, // Skip to: 86948 /* 43107 */ MCD_OPC_Decode, 252, 21, 141, 2, // Opcode: SABAv16i8 /* 43112 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 43134 /* 43117 */ MCD_OPC_CheckPredicate, 3, 50, 171, 0, // Skip to: 86948 /* 43122 */ MCD_OPC_CheckField, 21, 1, 1, 43, 171, 0, // Skip to: 86948 /* 43129 */ MCD_OPC_Decode, 236, 23, 141, 2, // Opcode: SMLALv16i8_v8i16 /* 43134 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 43156 /* 43139 */ MCD_OPC_CheckPredicate, 3, 28, 171, 0, // Skip to: 86948 /* 43144 */ MCD_OPC_CheckField, 21, 1, 1, 21, 171, 0, // Skip to: 86948 /* 43151 */ MCD_OPC_Decode, 194, 1, 133, 2, // Opcode: ADDv16i8 /* 43156 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 43194 /* 43161 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 43164 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43179 /* 43169 */ MCD_OPC_CheckPredicate, 3, 254, 170, 0, // Skip to: 86948 /* 43174 */ MCD_OPC_Decode, 215, 3, 138, 2, // Opcode: CMGTv16i8rz /* 43179 */ MCD_OPC_FilterValue, 33, 244, 170, 0, // Skip to: 86948 /* 43184 */ MCD_OPC_CheckPredicate, 3, 239, 170, 0, // Skip to: 86948 /* 43189 */ MCD_OPC_Decode, 138, 12, 138, 2, // Opcode: FRINTNv4f32 /* 43194 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 43216 /* 43199 */ MCD_OPC_CheckPredicate, 3, 224, 170, 0, // Skip to: 86948 /* 43204 */ MCD_OPC_CheckField, 21, 1, 1, 217, 170, 0, // Skip to: 86948 /* 43211 */ MCD_OPC_Decode, 233, 4, 133, 2, // Opcode: CMTSTv16i8 /* 43216 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 43238 /* 43221 */ MCD_OPC_CheckPredicate, 3, 202, 170, 0, // Skip to: 86948 /* 43226 */ MCD_OPC_CheckField, 21, 1, 1, 195, 170, 0, // Skip to: 86948 /* 43233 */ MCD_OPC_Decode, 209, 19, 141, 2, // Opcode: MLAv16i8 /* 43238 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 43276 /* 43243 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 43246 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43261 /* 43251 */ MCD_OPC_CheckPredicate, 3, 172, 170, 0, // Skip to: 86948 /* 43256 */ MCD_OPC_Decode, 183, 3, 138, 2, // Opcode: CMEQv16i8rz /* 43261 */ MCD_OPC_FilterValue, 33, 162, 170, 0, // Skip to: 86948 /* 43266 */ MCD_OPC_CheckPredicate, 3, 157, 170, 0, // Skip to: 86948 /* 43271 */ MCD_OPC_Decode, 255, 11, 138, 2, // Opcode: FRINTMv4f32 /* 43276 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 43298 /* 43281 */ MCD_OPC_CheckPredicate, 3, 142, 170, 0, // Skip to: 86948 /* 43286 */ MCD_OPC_CheckField, 21, 1, 1, 135, 170, 0, // Skip to: 86948 /* 43293 */ MCD_OPC_Decode, 157, 20, 133, 2, // Opcode: MULv16i8 /* 43298 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 43320 /* 43303 */ MCD_OPC_CheckPredicate, 3, 120, 170, 0, // Skip to: 86948 /* 43308 */ MCD_OPC_CheckField, 21, 1, 1, 113, 170, 0, // Skip to: 86948 /* 43315 */ MCD_OPC_Decode, 246, 23, 141, 2, // Opcode: SMLSLv16i8_v8i16 /* 43320 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 43342 /* 43325 */ MCD_OPC_CheckPredicate, 3, 98, 170, 0, // Skip to: 86948 /* 43330 */ MCD_OPC_CheckField, 21, 1, 1, 91, 170, 0, // Skip to: 86948 /* 43337 */ MCD_OPC_Decode, 177, 23, 133, 2, // Opcode: SMAXPv16i8 /* 43342 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 43410 /* 43347 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 43350 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43365 /* 43355 */ MCD_OPC_CheckPredicate, 3, 68, 170, 0, // Skip to: 86948 /* 43360 */ MCD_OPC_Decode, 254, 3, 138, 2, // Opcode: CMLTv16i8rz /* 43365 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43380 /* 43370 */ MCD_OPC_CheckPredicate, 3, 53, 170, 0, // Skip to: 86948 /* 43375 */ MCD_OPC_Decode, 165, 8, 138, 2, // Opcode: FCVTNSv4f32 /* 43380 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 43395 /* 43385 */ MCD_OPC_CheckPredicate, 3, 38, 170, 0, // Skip to: 86948 /* 43390 */ MCD_OPC_Decode, 187, 23, 158, 2, // Opcode: SMAXVv16i8v /* 43395 */ MCD_OPC_FilterValue, 49, 28, 170, 0, // Skip to: 86948 /* 43400 */ MCD_OPC_CheckPredicate, 3, 23, 170, 0, // Skip to: 86948 /* 43405 */ MCD_OPC_Decode, 217, 23, 158, 2, // Opcode: SMINVv16i8v /* 43410 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 43432 /* 43415 */ MCD_OPC_CheckPredicate, 3, 8, 170, 0, // Skip to: 86948 /* 43420 */ MCD_OPC_CheckField, 21, 1, 1, 1, 170, 0, // Skip to: 86948 /* 43427 */ MCD_OPC_Decode, 207, 23, 133, 2, // Opcode: SMINPv16i8 /* 43432 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 43485 /* 43437 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 43440 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43455 /* 43445 */ MCD_OPC_CheckPredicate, 3, 234, 169, 0, // Skip to: 86948 /* 43450 */ MCD_OPC_Decode, 130, 1, 138, 2, // Opcode: ABSv16i8 /* 43455 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43470 /* 43460 */ MCD_OPC_CheckPredicate, 3, 219, 169, 0, // Skip to: 86948 /* 43465 */ MCD_OPC_Decode, 137, 8, 138, 2, // Opcode: FCVTMSv4f32 /* 43470 */ MCD_OPC_FilterValue, 49, 209, 169, 0, // Skip to: 86948 /* 43475 */ MCD_OPC_CheckPredicate, 3, 204, 169, 0, // Skip to: 86948 /* 43480 */ MCD_OPC_Decode, 167, 1, 158, 2, // Opcode: ADDVv16i8v /* 43485 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 43507 /* 43490 */ MCD_OPC_CheckPredicate, 3, 189, 169, 0, // Skip to: 86948 /* 43495 */ MCD_OPC_CheckField, 21, 1, 1, 182, 169, 0, // Skip to: 86948 /* 43502 */ MCD_OPC_Decode, 149, 1, 133, 2, // Opcode: ADDPv16i8 /* 43507 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 43529 /* 43512 */ MCD_OPC_CheckPredicate, 3, 167, 169, 0, // Skip to: 86948 /* 43517 */ MCD_OPC_CheckField, 21, 1, 1, 160, 169, 0, // Skip to: 86948 /* 43524 */ MCD_OPC_Decode, 139, 24, 133, 2, // Opcode: SMULLv16i8_v8i16 /* 43529 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 43551 /* 43534 */ MCD_OPC_CheckPredicate, 3, 145, 169, 0, // Skip to: 86948 /* 43539 */ MCD_OPC_CheckField, 21, 1, 1, 138, 169, 0, // Skip to: 86948 /* 43546 */ MCD_OPC_Decode, 221, 9, 133, 2, // Opcode: FMAXNMv4f32 /* 43551 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 43589 /* 43556 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 43559 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43574 /* 43564 */ MCD_OPC_CheckPredicate, 3, 115, 169, 0, // Skip to: 86948 /* 43569 */ MCD_OPC_Decode, 229, 7, 138, 2, // Opcode: FCVTASv4f32 /* 43574 */ MCD_OPC_FilterValue, 48, 105, 169, 0, // Skip to: 86948 /* 43579 */ MCD_OPC_CheckPredicate, 4, 100, 169, 0, // Skip to: 86948 /* 43584 */ MCD_OPC_Decode, 211, 9, 152, 2, // Opcode: FMAXNMVv8i16v /* 43589 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 43611 /* 43594 */ MCD_OPC_CheckPredicate, 3, 85, 169, 0, // Skip to: 86948 /* 43599 */ MCD_OPC_CheckField, 21, 1, 1, 78, 169, 0, // Skip to: 86948 /* 43606 */ MCD_OPC_Decode, 191, 10, 141, 2, // Opcode: FMLAv4f32 /* 43611 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 43633 /* 43616 */ MCD_OPC_CheckPredicate, 3, 63, 169, 0, // Skip to: 86948 /* 43621 */ MCD_OPC_CheckField, 21, 1, 1, 56, 169, 0, // Skip to: 86948 /* 43628 */ MCD_OPC_Decode, 201, 6, 133, 2, // Opcode: FADDv4f32 /* 43633 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 43655 /* 43638 */ MCD_OPC_CheckPredicate, 3, 41, 169, 0, // Skip to: 86948 /* 43643 */ MCD_OPC_CheckField, 16, 6, 33, 34, 169, 0, // Skip to: 86948 /* 43650 */ MCD_OPC_Decode, 214, 22, 138, 2, // Opcode: SCVTFv4f32 /* 43655 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 43677 /* 43660 */ MCD_OPC_CheckPredicate, 3, 19, 169, 0, // Skip to: 86948 /* 43665 */ MCD_OPC_CheckField, 21, 1, 1, 12, 169, 0, // Skip to: 86948 /* 43672 */ MCD_OPC_Decode, 134, 11, 133, 2, // Opcode: FMULXv4f32 /* 43677 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 43699 /* 43682 */ MCD_OPC_CheckPredicate, 3, 253, 168, 0, // Skip to: 86948 /* 43687 */ MCD_OPC_CheckField, 21, 1, 1, 246, 168, 0, // Skip to: 86948 /* 43694 */ MCD_OPC_Decode, 243, 20, 133, 2, // Opcode: PMULLv16i8 /* 43699 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 43721 /* 43704 */ MCD_OPC_CheckPredicate, 3, 231, 168, 0, // Skip to: 86948 /* 43709 */ MCD_OPC_CheckField, 21, 1, 1, 224, 168, 0, // Skip to: 86948 /* 43716 */ MCD_OPC_Decode, 234, 6, 133, 2, // Opcode: FCMEQv4f32 /* 43721 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 43743 /* 43726 */ MCD_OPC_CheckPredicate, 3, 209, 168, 0, // Skip to: 86948 /* 43731 */ MCD_OPC_CheckField, 21, 1, 1, 202, 168, 0, // Skip to: 86948 /* 43738 */ MCD_OPC_Decode, 247, 9, 133, 2, // Opcode: FMAXv4f32 /* 43743 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 43765 /* 43748 */ MCD_OPC_CheckPredicate, 4, 187, 168, 0, // Skip to: 86948 /* 43753 */ MCD_OPC_CheckField, 16, 6, 48, 180, 168, 0, // Skip to: 86948 /* 43760 */ MCD_OPC_Decode, 237, 9, 152, 2, // Opcode: FMAXVv8i16v /* 43765 */ MCD_OPC_FilterValue, 63, 170, 168, 0, // Skip to: 86948 /* 43770 */ MCD_OPC_CheckPredicate, 3, 165, 168, 0, // Skip to: 86948 /* 43775 */ MCD_OPC_CheckField, 21, 1, 1, 158, 168, 0, // Skip to: 86948 /* 43782 */ MCD_OPC_Decode, 216, 11, 133, 2, // Opcode: FRECPSv4f32 /* 43787 */ MCD_OPC_FilterValue, 3, 71, 5, 0, // Skip to: 45143 /* 43792 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 43795 */ MCD_OPC_FilterValue, 0, 182, 2, 0, // Skip to: 44494 /* 43800 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 43803 */ MCD_OPC_FilterValue, 0, 107, 1, 0, // Skip to: 44171 /* 43808 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 43811 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43826 /* 43816 */ MCD_OPC_CheckPredicate, 3, 119, 168, 0, // Skip to: 86948 /* 43821 */ MCD_OPC_Decode, 253, 5, 159, 2, // Opcode: EXTv16i8 /* 43826 */ MCD_OPC_FilterValue, 1, 109, 168, 0, // Skip to: 86948 /* 43831 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... /* 43834 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43849 /* 43839 */ MCD_OPC_CheckPredicate, 3, 96, 168, 0, // Skip to: 86948 /* 43844 */ MCD_OPC_Decode, 153, 31, 133, 2, // Opcode: UADDLv16i8_v8i16 /* 43849 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 43871 /* 43854 */ MCD_OPC_CheckPredicate, 3, 81, 168, 0, // Skip to: 86948 /* 43859 */ MCD_OPC_CheckField, 16, 5, 0, 74, 168, 0, // Skip to: 86948 /* 43866 */ MCD_OPC_Decode, 205, 21, 138, 2, // Opcode: REV32v16i8 /* 43871 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 43886 /* 43876 */ MCD_OPC_CheckPredicate, 3, 59, 168, 0, // Skip to: 86948 /* 43881 */ MCD_OPC_Decode, 163, 31, 133, 2, // Opcode: UADDWv16i8_v8i16 /* 43886 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 43901 /* 43891 */ MCD_OPC_CheckPredicate, 3, 44, 168, 0, // Skip to: 86948 /* 43896 */ MCD_OPC_Decode, 164, 34, 133, 2, // Opcode: USUBLv16i8_v8i16 /* 43901 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 43939 /* 43906 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 43909 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43924 /* 43914 */ MCD_OPC_CheckPredicate, 3, 21, 168, 0, // Skip to: 86948 /* 43919 */ MCD_OPC_Decode, 142, 31, 138, 2, // Opcode: UADDLPv16i8_v8i16 /* 43924 */ MCD_OPC_FilterValue, 1, 11, 168, 0, // Skip to: 86948 /* 43929 */ MCD_OPC_CheckPredicate, 3, 6, 168, 0, // Skip to: 86948 /* 43934 */ MCD_OPC_Decode, 174, 26, 147, 2, // Opcode: SQXTUNv16i8 /* 43939 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 43954 /* 43944 */ MCD_OPC_CheckPredicate, 3, 247, 167, 0, // Skip to: 86948 /* 43949 */ MCD_OPC_Decode, 170, 34, 133, 2, // Opcode: USUBWv16i8_v8i16 /* 43954 */ MCD_OPC_FilterValue, 7, 48, 0, 0, // Skip to: 44007 /* 43959 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 43962 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43977 /* 43967 */ MCD_OPC_CheckPredicate, 3, 224, 167, 0, // Skip to: 86948 /* 43972 */ MCD_OPC_Decode, 145, 34, 147, 2, // Opcode: USQADDv16i8 /* 43977 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 43992 /* 43982 */ MCD_OPC_CheckPredicate, 3, 209, 167, 0, // Skip to: 86948 /* 43987 */ MCD_OPC_Decode, 133, 23, 138, 2, // Opcode: SHLLv16i8 /* 43992 */ MCD_OPC_FilterValue, 16, 199, 167, 0, // Skip to: 86948 /* 43997 */ MCD_OPC_CheckPredicate, 3, 194, 167, 0, // Skip to: 86948 /* 44002 */ MCD_OPC_Decode, 148, 31, 152, 2, // Opcode: UADDLVv16i8v /* 44007 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 44022 /* 44012 */ MCD_OPC_CheckPredicate, 3, 179, 167, 0, // Skip to: 86948 /* 44017 */ MCD_OPC_Decode, 181, 21, 141, 2, // Opcode: RADDHNv8i16_v16i8 /* 44022 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 44060 /* 44027 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 44030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 44045 /* 44035 */ MCD_OPC_CheckPredicate, 3, 156, 167, 0, // Skip to: 86948 /* 44040 */ MCD_OPC_Decode, 176, 3, 138, 2, // Opcode: CLZv16i8 /* 44045 */ MCD_OPC_FilterValue, 1, 146, 167, 0, // Skip to: 86948 /* 44050 */ MCD_OPC_CheckPredicate, 3, 141, 167, 0, // Skip to: 86948 /* 44055 */ MCD_OPC_Decode, 208, 33, 147, 2, // Opcode: UQXTNv16i8 /* 44060 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 44075 /* 44065 */ MCD_OPC_CheckPredicate, 3, 126, 167, 0, // Skip to: 86948 /* 44070 */ MCD_OPC_Decode, 236, 30, 141, 2, // Opcode: UABALv16i8_v8i16 /* 44075 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 44097 /* 44080 */ MCD_OPC_CheckPredicate, 3, 111, 167, 0, // Skip to: 86948 /* 44085 */ MCD_OPC_CheckField, 16, 5, 0, 104, 167, 0, // Skip to: 86948 /* 44092 */ MCD_OPC_Decode, 193, 20, 138, 2, // Opcode: NOTv16i8 /* 44097 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 44112 /* 44102 */ MCD_OPC_CheckPredicate, 3, 89, 167, 0, // Skip to: 86948 /* 44107 */ MCD_OPC_Decode, 244, 21, 141, 2, // Opcode: RSUBHNv8i16_v16i8 /* 44112 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 44134 /* 44117 */ MCD_OPC_CheckPredicate, 3, 74, 167, 0, // Skip to: 86948 /* 44122 */ MCD_OPC_CheckField, 16, 5, 0, 67, 167, 0, // Skip to: 86948 /* 44129 */ MCD_OPC_Decode, 136, 31, 147, 2, // Opcode: UADALPv16i8_v8i16 /* 44134 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 44149 /* 44139 */ MCD_OPC_CheckPredicate, 3, 52, 167, 0, // Skip to: 86948 /* 44144 */ MCD_OPC_Decode, 248, 30, 133, 2, // Opcode: UABDLv16i8_v8i16 /* 44149 */ MCD_OPC_FilterValue, 15, 42, 167, 0, // Skip to: 86948 /* 44154 */ MCD_OPC_CheckPredicate, 3, 37, 167, 0, // Skip to: 86948 /* 44159 */ MCD_OPC_CheckField, 16, 5, 0, 30, 167, 0, // Skip to: 86948 /* 44166 */ MCD_OPC_Decode, 147, 25, 138, 2, // Opcode: SQNEGv16i8 /* 44171 */ MCD_OPC_FilterValue, 1, 20, 167, 0, // Skip to: 86948 /* 44176 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... /* 44179 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44201 /* 44184 */ MCD_OPC_CheckPredicate, 3, 7, 167, 0, // Skip to: 86948 /* 44189 */ MCD_OPC_CheckField, 21, 1, 1, 0, 167, 0, // Skip to: 86948 /* 44196 */ MCD_OPC_Decode, 163, 32, 141, 2, // Opcode: UMLALv16i8_v8i16 /* 44201 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 44239 /* 44206 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 44209 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44224 /* 44214 */ MCD_OPC_CheckPredicate, 3, 233, 166, 0, // Skip to: 86948 /* 44219 */ MCD_OPC_Decode, 199, 3, 138, 2, // Opcode: CMGEv16i8rz /* 44224 */ MCD_OPC_FilterValue, 33, 223, 166, 0, // Skip to: 86948 /* 44229 */ MCD_OPC_CheckPredicate, 3, 218, 166, 0, // Skip to: 86948 /* 44234 */ MCD_OPC_Decode, 233, 11, 138, 2, // Opcode: FRINTAv4f32 /* 44239 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 44277 /* 44244 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 44247 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44262 /* 44252 */ MCD_OPC_CheckPredicate, 3, 195, 166, 0, // Skip to: 86948 /* 44257 */ MCD_OPC_Decode, 246, 3, 138, 2, // Opcode: CMLEv16i8rz /* 44262 */ MCD_OPC_FilterValue, 33, 185, 166, 0, // Skip to: 86948 /* 44267 */ MCD_OPC_CheckPredicate, 3, 180, 166, 0, // Skip to: 86948 /* 44272 */ MCD_OPC_Decode, 160, 12, 138, 2, // Opcode: FRINTXv4f32 /* 44277 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 44299 /* 44282 */ MCD_OPC_CheckPredicate, 3, 165, 166, 0, // Skip to: 86948 /* 44287 */ MCD_OPC_CheckField, 21, 1, 1, 158, 166, 0, // Skip to: 86948 /* 44294 */ MCD_OPC_Decode, 173, 32, 141, 2, // Opcode: UMLSLv16i8_v8i16 /* 44299 */ MCD_OPC_FilterValue, 5, 48, 0, 0, // Skip to: 44352 /* 44304 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 44307 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 44322 /* 44312 */ MCD_OPC_CheckPredicate, 3, 135, 166, 0, // Skip to: 86948 /* 44317 */ MCD_OPC_Decode, 179, 8, 138, 2, // Opcode: FCVTNUv4f32 /* 44322 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 44337 /* 44327 */ MCD_OPC_CheckPredicate, 3, 120, 166, 0, // Skip to: 86948 /* 44332 */ MCD_OPC_Decode, 243, 31, 158, 2, // Opcode: UMAXVv16i8v /* 44337 */ MCD_OPC_FilterValue, 49, 110, 166, 0, // Skip to: 86948 /* 44342 */ MCD_OPC_CheckPredicate, 3, 105, 166, 0, // Skip to: 86948 /* 44347 */ MCD_OPC_Decode, 144, 32, 158, 2, // Opcode: UMINVv16i8v /* 44352 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 44390 /* 44357 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 44360 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44375 /* 44365 */ MCD_OPC_CheckPredicate, 3, 82, 166, 0, // Skip to: 86948 /* 44370 */ MCD_OPC_Decode, 179, 20, 138, 2, // Opcode: NEGv16i8 /* 44375 */ MCD_OPC_FilterValue, 33, 72, 166, 0, // Skip to: 86948 /* 44380 */ MCD_OPC_CheckPredicate, 3, 67, 166, 0, // Skip to: 86948 /* 44385 */ MCD_OPC_Decode, 151, 8, 138, 2, // Opcode: FCVTMUv4f32 /* 44390 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 44412 /* 44395 */ MCD_OPC_CheckPredicate, 3, 52, 166, 0, // Skip to: 86948 /* 44400 */ MCD_OPC_CheckField, 21, 1, 1, 45, 166, 0, // Skip to: 86948 /* 44407 */ MCD_OPC_Decode, 193, 32, 133, 2, // Opcode: UMULLv16i8_v8i16 /* 44412 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 44450 /* 44417 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 44420 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 44435 /* 44425 */ MCD_OPC_CheckPredicate, 3, 22, 166, 0, // Skip to: 86948 /* 44430 */ MCD_OPC_Decode, 243, 7, 138, 2, // Opcode: FCVTAUv4f32 /* 44435 */ MCD_OPC_FilterValue, 48, 12, 166, 0, // Skip to: 86948 /* 44440 */ MCD_OPC_CheckPredicate, 3, 7, 166, 0, // Skip to: 86948 /* 44445 */ MCD_OPC_Decode, 210, 9, 160, 2, // Opcode: FMAXNMVv4i32v /* 44450 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 44472 /* 44455 */ MCD_OPC_CheckPredicate, 3, 248, 165, 0, // Skip to: 86948 /* 44460 */ MCD_OPC_CheckField, 16, 6, 33, 241, 165, 0, // Skip to: 86948 /* 44467 */ MCD_OPC_Decode, 201, 31, 138, 2, // Opcode: UCVTFv4f32 /* 44472 */ MCD_OPC_FilterValue, 15, 231, 165, 0, // Skip to: 86948 /* 44477 */ MCD_OPC_CheckPredicate, 3, 226, 165, 0, // Skip to: 86948 /* 44482 */ MCD_OPC_CheckField, 16, 6, 48, 219, 165, 0, // Skip to: 86948 /* 44489 */ MCD_OPC_Decode, 236, 9, 160, 2, // Opcode: FMAXVv4i32v /* 44494 */ MCD_OPC_FilterValue, 1, 209, 165, 0, // Skip to: 86948 /* 44499 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 44502 */ MCD_OPC_FilterValue, 0, 86, 1, 0, // Skip to: 44849 /* 44507 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 44510 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 44601 /* 44515 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 44518 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 44586 /* 44523 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 44526 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 44571 /* 44531 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 44534 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44556 /* 44539 */ MCD_OPC_CheckPredicate, 3, 164, 165, 0, // Skip to: 86948 /* 44544 */ MCD_OPC_CheckField, 19, 1, 1, 157, 165, 0, // Skip to: 86948 /* 44551 */ MCD_OPC_Decode, 159, 14, 161, 2, // Opcode: INSvi64lane /* 44556 */ MCD_OPC_FilterValue, 1, 147, 165, 0, // Skip to: 86948 /* 44561 */ MCD_OPC_CheckPredicate, 3, 142, 165, 0, // Skip to: 86948 /* 44566 */ MCD_OPC_Decode, 157, 14, 162, 2, // Opcode: INSvi32lane /* 44571 */ MCD_OPC_FilterValue, 1, 132, 165, 0, // Skip to: 86948 /* 44576 */ MCD_OPC_CheckPredicate, 3, 127, 165, 0, // Skip to: 86948 /* 44581 */ MCD_OPC_Decode, 155, 14, 163, 2, // Opcode: INSvi16lane /* 44586 */ MCD_OPC_FilterValue, 1, 117, 165, 0, // Skip to: 86948 /* 44591 */ MCD_OPC_CheckPredicate, 3, 112, 165, 0, // Skip to: 86948 /* 44596 */ MCD_OPC_Decode, 161, 14, 164, 2, // Opcode: INSvi8lane /* 44601 */ MCD_OPC_FilterValue, 1, 102, 165, 0, // Skip to: 86948 /* 44606 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... /* 44609 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 44624 /* 44614 */ MCD_OPC_CheckPredicate, 3, 89, 165, 0, // Skip to: 86948 /* 44619 */ MCD_OPC_Decode, 220, 31, 133, 2, // Opcode: UHADDv16i8 /* 44624 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 44639 /* 44629 */ MCD_OPC_CheckPredicate, 3, 74, 165, 0, // Skip to: 86948 /* 44634 */ MCD_OPC_Decode, 211, 32, 133, 2, // Opcode: UQADDv16i8 /* 44639 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 44654 /* 44644 */ MCD_OPC_CheckPredicate, 3, 59, 165, 0, // Skip to: 86948 /* 44649 */ MCD_OPC_Decode, 219, 33, 133, 2, // Opcode: URHADDv16i8 /* 44654 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 44669 /* 44659 */ MCD_OPC_CheckPredicate, 3, 44, 165, 0, // Skip to: 86948 /* 44664 */ MCD_OPC_Decode, 245, 5, 133, 2, // Opcode: EORv16i8 /* 44669 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 44684 /* 44674 */ MCD_OPC_CheckPredicate, 3, 29, 165, 0, // Skip to: 86948 /* 44679 */ MCD_OPC_Decode, 226, 31, 133, 2, // Opcode: UHSUBv16i8 /* 44684 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 44699 /* 44689 */ MCD_OPC_CheckPredicate, 3, 14, 165, 0, // Skip to: 86948 /* 44694 */ MCD_OPC_Decode, 197, 33, 133, 2, // Opcode: UQSUBv16i8 /* 44699 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 44714 /* 44704 */ MCD_OPC_CheckPredicate, 3, 255, 164, 0, // Skip to: 86948 /* 44709 */ MCD_OPC_Decode, 230, 3, 133, 2, // Opcode: CMHIv16i8 /* 44714 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 44729 /* 44719 */ MCD_OPC_CheckPredicate, 3, 240, 164, 0, // Skip to: 86948 /* 44724 */ MCD_OPC_Decode, 238, 3, 133, 2, // Opcode: CMHSv16i8 /* 44729 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 44744 /* 44734 */ MCD_OPC_CheckPredicate, 3, 225, 164, 0, // Skip to: 86948 /* 44739 */ MCD_OPC_Decode, 129, 34, 133, 2, // Opcode: USHLv16i8 /* 44744 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 44759 /* 44749 */ MCD_OPC_CheckPredicate, 3, 210, 164, 0, // Skip to: 86948 /* 44754 */ MCD_OPC_Decode, 162, 33, 133, 2, // Opcode: UQSHLv16i8 /* 44759 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 44774 /* 44764 */ MCD_OPC_CheckPredicate, 3, 195, 164, 0, // Skip to: 86948 /* 44769 */ MCD_OPC_Decode, 225, 33, 133, 2, // Opcode: URSHLv16i8 /* 44774 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 44789 /* 44779 */ MCD_OPC_CheckPredicate, 3, 180, 164, 0, // Skip to: 86948 /* 44784 */ MCD_OPC_Decode, 138, 33, 133, 2, // Opcode: UQRSHLv16i8 /* 44789 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 44804 /* 44794 */ MCD_OPC_CheckPredicate, 3, 165, 164, 0, // Skip to: 86948 /* 44799 */ MCD_OPC_Decode, 128, 32, 133, 2, // Opcode: UMAXv16i8 /* 44804 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 44819 /* 44809 */ MCD_OPC_CheckPredicate, 3, 150, 164, 0, // Skip to: 86948 /* 44814 */ MCD_OPC_Decode, 157, 32, 133, 2, // Opcode: UMINv16i8 /* 44819 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 44834 /* 44824 */ MCD_OPC_CheckPredicate, 3, 135, 164, 0, // Skip to: 86948 /* 44829 */ MCD_OPC_Decode, 130, 31, 133, 2, // Opcode: UABDv16i8 /* 44834 */ MCD_OPC_FilterValue, 15, 125, 164, 0, // Skip to: 86948 /* 44839 */ MCD_OPC_CheckPredicate, 3, 120, 164, 0, // Skip to: 86948 /* 44844 */ MCD_OPC_Decode, 242, 30, 141, 2, // Opcode: UABAv16i8 /* 44849 */ MCD_OPC_FilterValue, 1, 110, 164, 0, // Skip to: 86948 /* 44854 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... /* 44857 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44879 /* 44862 */ MCD_OPC_CheckPredicate, 3, 97, 164, 0, // Skip to: 86948 /* 44867 */ MCD_OPC_CheckField, 21, 1, 1, 90, 164, 0, // Skip to: 86948 /* 44874 */ MCD_OPC_Decode, 255, 29, 133, 2, // Opcode: SUBv16i8 /* 44879 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 44901 /* 44884 */ MCD_OPC_CheckPredicate, 3, 75, 164, 0, // Skip to: 86948 /* 44889 */ MCD_OPC_CheckField, 21, 1, 1, 68, 164, 0, // Skip to: 86948 /* 44896 */ MCD_OPC_Decode, 182, 3, 133, 2, // Opcode: CMEQv16i8 /* 44901 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 44923 /* 44906 */ MCD_OPC_CheckPredicate, 3, 53, 164, 0, // Skip to: 86948 /* 44911 */ MCD_OPC_CheckField, 21, 1, 1, 46, 164, 0, // Skip to: 86948 /* 44918 */ MCD_OPC_Decode, 223, 19, 141, 2, // Opcode: MLSv16i8 /* 44923 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 44945 /* 44928 */ MCD_OPC_CheckPredicate, 3, 31, 164, 0, // Skip to: 86948 /* 44933 */ MCD_OPC_CheckField, 21, 1, 1, 24, 164, 0, // Skip to: 86948 /* 44940 */ MCD_OPC_Decode, 247, 20, 133, 2, // Opcode: PMULv16i8 /* 44945 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 44967 /* 44950 */ MCD_OPC_CheckPredicate, 3, 9, 164, 0, // Skip to: 86948 /* 44955 */ MCD_OPC_CheckField, 21, 1, 1, 2, 164, 0, // Skip to: 86948 /* 44962 */ MCD_OPC_Decode, 233, 31, 133, 2, // Opcode: UMAXPv16i8 /* 44967 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 44989 /* 44972 */ MCD_OPC_CheckPredicate, 3, 243, 163, 0, // Skip to: 86948 /* 44977 */ MCD_OPC_CheckField, 21, 1, 1, 236, 163, 0, // Skip to: 86948 /* 44984 */ MCD_OPC_Decode, 134, 32, 133, 2, // Opcode: UMINPv16i8 /* 44989 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 45011 /* 44994 */ MCD_OPC_CheckPredicate, 3, 221, 163, 0, // Skip to: 86948 /* 44999 */ MCD_OPC_CheckField, 21, 1, 1, 214, 163, 0, // Skip to: 86948 /* 45006 */ MCD_OPC_Decode, 203, 9, 133, 2, // Opcode: FMAXNMPv4f32 /* 45011 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 45033 /* 45016 */ MCD_OPC_CheckPredicate, 3, 199, 163, 0, // Skip to: 86948 /* 45021 */ MCD_OPC_CheckField, 21, 1, 1, 192, 163, 0, // Skip to: 86948 /* 45028 */ MCD_OPC_Decode, 183, 6, 133, 2, // Opcode: FADDPv4f32 /* 45033 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 45055 /* 45038 */ MCD_OPC_CheckPredicate, 3, 177, 163, 0, // Skip to: 86948 /* 45043 */ MCD_OPC_CheckField, 21, 1, 1, 170, 163, 0, // Skip to: 86948 /* 45050 */ MCD_OPC_Decode, 159, 11, 133, 2, // Opcode: FMULv4f32 /* 45055 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 45077 /* 45060 */ MCD_OPC_CheckPredicate, 3, 155, 163, 0, // Skip to: 86948 /* 45065 */ MCD_OPC_CheckField, 21, 1, 1, 148, 163, 0, // Skip to: 86948 /* 45072 */ MCD_OPC_Decode, 128, 7, 133, 2, // Opcode: FCMGEv4f32 /* 45077 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 45099 /* 45082 */ MCD_OPC_CheckPredicate, 3, 133, 163, 0, // Skip to: 86948 /* 45087 */ MCD_OPC_CheckField, 21, 1, 1, 126, 163, 0, // Skip to: 86948 /* 45094 */ MCD_OPC_Decode, 159, 6, 133, 2, // Opcode: FACGEv4f32 /* 45099 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 45121 /* 45104 */ MCD_OPC_CheckPredicate, 3, 111, 163, 0, // Skip to: 86948 /* 45109 */ MCD_OPC_CheckField, 21, 1, 1, 104, 163, 0, // Skip to: 86948 /* 45116 */ MCD_OPC_Decode, 229, 9, 133, 2, // Opcode: FMAXPv4f32 /* 45121 */ MCD_OPC_FilterValue, 15, 94, 163, 0, // Skip to: 86948 /* 45126 */ MCD_OPC_CheckPredicate, 3, 89, 163, 0, // Skip to: 86948 /* 45131 */ MCD_OPC_CheckField, 21, 1, 1, 82, 163, 0, // Skip to: 86948 /* 45138 */ MCD_OPC_Decode, 178, 9, 133, 2, // Opcode: FDIVv4f32 /* 45143 */ MCD_OPC_FilterValue, 6, 72, 163, 0, // Skip to: 86948 /* 45148 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45151 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 45173 /* 45156 */ MCD_OPC_CheckPredicate, 6, 59, 163, 0, // Skip to: 86948 /* 45161 */ MCD_OPC_CheckField, 15, 1, 0, 52, 163, 0, // Skip to: 86948 /* 45168 */ MCD_OPC_Decode, 226, 5, 165, 2, // Opcode: EOR3 /* 45173 */ MCD_OPC_FilterValue, 1, 42, 163, 0, // Skip to: 86948 /* 45178 */ MCD_OPC_CheckPredicate, 6, 37, 163, 0, // Skip to: 86948 /* 45183 */ MCD_OPC_CheckField, 15, 1, 0, 30, 163, 0, // Skip to: 86948 /* 45190 */ MCD_OPC_Decode, 169, 2, 165, 2, // Opcode: BCAX /* 45195 */ MCD_OPC_FilterValue, 9, 131, 26, 0, // Skip to: 51987 /* 45200 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 45203 */ MCD_OPC_FilterValue, 0, 4, 6, 0, // Skip to: 46748 /* 45208 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 45211 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 45233 /* 45216 */ MCD_OPC_CheckPredicate, 3, 255, 162, 0, // Skip to: 86948 /* 45221 */ MCD_OPC_CheckField, 21, 1, 1, 248, 162, 0, // Skip to: 86948 /* 45228 */ MCD_OPC_Decode, 165, 22, 234, 1, // Opcode: SADDLv4i16_v4i32 /* 45233 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 45271 /* 45238 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45256 /* 45246 */ MCD_OPC_CheckPredicate, 4, 225, 162, 0, // Skip to: 86948 /* 45251 */ MCD_OPC_Decode, 220, 9, 238, 1, // Opcode: FMAXNMv4f16 /* 45256 */ MCD_OPC_FilterValue, 1, 215, 162, 0, // Skip to: 86948 /* 45261 */ MCD_OPC_CheckPredicate, 3, 210, 162, 0, // Skip to: 86948 /* 45266 */ MCD_OPC_Decode, 129, 23, 238, 1, // Opcode: SHADDv4i16 /* 45271 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 45293 /* 45276 */ MCD_OPC_CheckPredicate, 3, 195, 162, 0, // Skip to: 86948 /* 45281 */ MCD_OPC_CheckField, 16, 6, 32, 188, 162, 0, // Skip to: 86948 /* 45288 */ MCD_OPC_Decode, 211, 21, 239, 1, // Opcode: REV64v4i16 /* 45293 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 45331 /* 45298 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45301 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45316 /* 45306 */ MCD_OPC_CheckPredicate, 4, 165, 162, 0, // Skip to: 86948 /* 45311 */ MCD_OPC_Decode, 190, 10, 130, 2, // Opcode: FMLAv4f16 /* 45316 */ MCD_OPC_FilterValue, 1, 155, 162, 0, // Skip to: 86948 /* 45321 */ MCD_OPC_CheckPredicate, 3, 150, 162, 0, // Skip to: 86948 /* 45326 */ MCD_OPC_Decode, 179, 24, 238, 1, // Opcode: SQADDv4i16 /* 45331 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 45353 /* 45336 */ MCD_OPC_CheckPredicate, 3, 135, 162, 0, // Skip to: 86948 /* 45341 */ MCD_OPC_CheckField, 21, 1, 1, 128, 162, 0, // Skip to: 86948 /* 45348 */ MCD_OPC_Decode, 174, 22, 242, 1, // Opcode: SADDWv4i16_v4i32 /* 45353 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 45391 /* 45358 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45361 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45376 /* 45366 */ MCD_OPC_CheckPredicate, 4, 105, 162, 0, // Skip to: 86948 /* 45371 */ MCD_OPC_Decode, 200, 6, 238, 1, // Opcode: FADDv4f16 /* 45376 */ MCD_OPC_FilterValue, 1, 95, 162, 0, // Skip to: 86948 /* 45381 */ MCD_OPC_CheckPredicate, 3, 90, 162, 0, // Skip to: 86948 /* 45386 */ MCD_OPC_Decode, 185, 26, 238, 1, // Opcode: SRHADDv4i16 /* 45391 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 45413 /* 45396 */ MCD_OPC_CheckPredicate, 3, 75, 162, 0, // Skip to: 86948 /* 45401 */ MCD_OPC_CheckField, 21, 1, 0, 68, 162, 0, // Skip to: 86948 /* 45408 */ MCD_OPC_Decode, 199, 34, 238, 1, // Opcode: UZP1v4i16 /* 45413 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 45451 /* 45418 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45421 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45436 /* 45426 */ MCD_OPC_CheckPredicate, 4, 45, 162, 0, // Skip to: 86948 /* 45431 */ MCD_OPC_Decode, 133, 11, 238, 1, // Opcode: FMULXv4f16 /* 45436 */ MCD_OPC_FilterValue, 1, 35, 162, 0, // Skip to: 86948 /* 45441 */ MCD_OPC_CheckPredicate, 3, 30, 162, 0, // Skip to: 86948 /* 45446 */ MCD_OPC_Decode, 192, 2, 238, 1, // Opcode: BICv8i8 /* 45451 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 45473 /* 45456 */ MCD_OPC_CheckPredicate, 3, 15, 162, 0, // Skip to: 86948 /* 45461 */ MCD_OPC_CheckField, 21, 1, 1, 8, 162, 0, // Skip to: 86948 /* 45468 */ MCD_OPC_Decode, 163, 27, 234, 1, // Opcode: SSUBLv4i16_v4i32 /* 45473 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 45511 /* 45478 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45481 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45496 /* 45486 */ MCD_OPC_CheckPredicate, 4, 241, 161, 0, // Skip to: 86948 /* 45491 */ MCD_OPC_Decode, 233, 6, 238, 1, // Opcode: FCMEQv4f16 /* 45496 */ MCD_OPC_FilterValue, 1, 231, 161, 0, // Skip to: 86948 /* 45501 */ MCD_OPC_CheckPredicate, 3, 226, 161, 0, // Skip to: 86948 /* 45506 */ MCD_OPC_Decode, 155, 23, 238, 1, // Opcode: SHSUBv4i16 /* 45511 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 45572 /* 45516 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45519 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45534 /* 45524 */ MCD_OPC_CheckPredicate, 3, 203, 161, 0, // Skip to: 86948 /* 45529 */ MCD_OPC_Decode, 216, 30, 238, 1, // Opcode: TRN1v4i16 /* 45534 */ MCD_OPC_FilterValue, 1, 193, 161, 0, // Skip to: 86948 /* 45539 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 45542 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45557 /* 45547 */ MCD_OPC_CheckPredicate, 3, 180, 161, 0, // Skip to: 86948 /* 45552 */ MCD_OPC_Decode, 154, 22, 239, 1, // Opcode: SADDLPv4i16_v2i32 /* 45557 */ MCD_OPC_FilterValue, 1, 170, 161, 0, // Skip to: 86948 /* 45562 */ MCD_OPC_CheckPredicate, 3, 165, 161, 0, // Skip to: 86948 /* 45567 */ MCD_OPC_Decode, 129, 35, 244, 1, // Opcode: XTNv4i16 /* 45572 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 45594 /* 45577 */ MCD_OPC_CheckPredicate, 3, 150, 161, 0, // Skip to: 86948 /* 45582 */ MCD_OPC_CheckField, 21, 1, 1, 143, 161, 0, // Skip to: 86948 /* 45589 */ MCD_OPC_Decode, 161, 26, 238, 1, // Opcode: SQSUBv4i16 /* 45594 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 45616 /* 45599 */ MCD_OPC_CheckPredicate, 3, 128, 161, 0, // Skip to: 86948 /* 45604 */ MCD_OPC_CheckField, 21, 1, 1, 121, 161, 0, // Skip to: 86948 /* 45611 */ MCD_OPC_Decode, 169, 27, 242, 1, // Opcode: SSUBWv4i16_v4i32 /* 45616 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 45654 /* 45621 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45624 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45639 /* 45629 */ MCD_OPC_CheckPredicate, 4, 98, 161, 0, // Skip to: 86948 /* 45634 */ MCD_OPC_Decode, 246, 9, 238, 1, // Opcode: FMAXv4f16 /* 45639 */ MCD_OPC_FilterValue, 1, 88, 161, 0, // Skip to: 86948 /* 45644 */ MCD_OPC_CheckPredicate, 3, 83, 161, 0, // Skip to: 86948 /* 45649 */ MCD_OPC_Decode, 222, 3, 238, 1, // Opcode: CMGTv4i16 /* 45654 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 45715 /* 45659 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45662 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45677 /* 45667 */ MCD_OPC_CheckPredicate, 3, 60, 161, 0, // Skip to: 86948 /* 45672 */ MCD_OPC_Decode, 144, 35, 238, 1, // Opcode: ZIP1v4i16 /* 45677 */ MCD_OPC_FilterValue, 1, 50, 161, 0, // Skip to: 86948 /* 45682 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 45685 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45700 /* 45690 */ MCD_OPC_CheckPredicate, 3, 37, 161, 0, // Skip to: 86948 /* 45695 */ MCD_OPC_Decode, 148, 30, 248, 1, // Opcode: SUQADDv4i16 /* 45700 */ MCD_OPC_FilterValue, 16, 27, 161, 0, // Skip to: 86948 /* 45705 */ MCD_OPC_CheckPredicate, 3, 22, 161, 0, // Skip to: 86948 /* 45710 */ MCD_OPC_Decode, 159, 22, 166, 2, // Opcode: SADDLVv4i16v /* 45715 */ MCD_OPC_FilterValue, 15, 33, 0, 0, // Skip to: 45753 /* 45720 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45723 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45738 /* 45728 */ MCD_OPC_CheckPredicate, 4, 255, 160, 0, // Skip to: 86948 /* 45733 */ MCD_OPC_Decode, 215, 11, 238, 1, // Opcode: FRECPSv4f16 /* 45738 */ MCD_OPC_FilterValue, 1, 245, 160, 0, // Skip to: 86948 /* 45743 */ MCD_OPC_CheckPredicate, 3, 240, 160, 0, // Skip to: 86948 /* 45748 */ MCD_OPC_Decode, 206, 3, 238, 1, // Opcode: CMGEv4i16 /* 45753 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 45775 /* 45758 */ MCD_OPC_CheckPredicate, 3, 225, 160, 0, // Skip to: 86948 /* 45763 */ MCD_OPC_CheckField, 21, 1, 1, 218, 160, 0, // Skip to: 86948 /* 45770 */ MCD_OPC_Decode, 144, 1, 252, 1, // Opcode: ADDHNv4i32_v4i16 /* 45775 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 45797 /* 45780 */ MCD_OPC_CheckPredicate, 3, 203, 160, 0, // Skip to: 86948 /* 45785 */ MCD_OPC_CheckField, 21, 1, 1, 196, 160, 0, // Skip to: 86948 /* 45792 */ MCD_OPC_Decode, 231, 26, 238, 1, // Opcode: SSHLv4i16 /* 45797 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 45835 /* 45802 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 45805 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 45820 /* 45810 */ MCD_OPC_CheckPredicate, 3, 173, 160, 0, // Skip to: 86948 /* 45815 */ MCD_OPC_Decode, 166, 3, 239, 1, // Opcode: CLSv4i16 /* 45820 */ MCD_OPC_FilterValue, 33, 163, 160, 0, // Skip to: 86948 /* 45825 */ MCD_OPC_CheckPredicate, 3, 158, 160, 0, // Skip to: 86948 /* 45830 */ MCD_OPC_Decode, 170, 26, 244, 1, // Opcode: SQXTNv4i16 /* 45835 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 45857 /* 45840 */ MCD_OPC_CheckPredicate, 3, 143, 160, 0, // Skip to: 86948 /* 45845 */ MCD_OPC_CheckField, 21, 1, 1, 136, 160, 0, // Skip to: 86948 /* 45852 */ MCD_OPC_Decode, 248, 25, 238, 1, // Opcode: SQSHLv4i16 /* 45857 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 45879 /* 45862 */ MCD_OPC_CheckPredicate, 3, 121, 160, 0, // Skip to: 86948 /* 45867 */ MCD_OPC_CheckField, 21, 1, 1, 114, 160, 0, // Skip to: 86948 /* 45874 */ MCD_OPC_Decode, 248, 21, 254, 1, // Opcode: SABALv4i16_v4i32 /* 45879 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 45901 /* 45884 */ MCD_OPC_CheckPredicate, 3, 99, 160, 0, // Skip to: 86948 /* 45889 */ MCD_OPC_CheckField, 21, 1, 1, 92, 160, 0, // Skip to: 86948 /* 45896 */ MCD_OPC_Decode, 201, 26, 238, 1, // Opcode: SRSHLv4i16 /* 45901 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 45923 /* 45906 */ MCD_OPC_CheckPredicate, 3, 77, 160, 0, // Skip to: 86948 /* 45911 */ MCD_OPC_CheckField, 21, 1, 0, 70, 160, 0, // Skip to: 86948 /* 45918 */ MCD_OPC_Decode, 214, 34, 238, 1, // Opcode: UZP2v4i16 /* 45923 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 45945 /* 45928 */ MCD_OPC_CheckPredicate, 3, 55, 160, 0, // Skip to: 86948 /* 45933 */ MCD_OPC_CheckField, 21, 1, 1, 48, 160, 0, // Skip to: 86948 /* 45940 */ MCD_OPC_Decode, 201, 25, 238, 1, // Opcode: SQRSHLv4i16 /* 45945 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 45967 /* 45950 */ MCD_OPC_CheckPredicate, 3, 33, 160, 0, // Skip to: 86948 /* 45955 */ MCD_OPC_CheckField, 21, 1, 1, 26, 160, 0, // Skip to: 86948 /* 45962 */ MCD_OPC_Decode, 213, 29, 252, 1, // Opcode: SUBHNv4i32_v4i16 /* 45967 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 45989 /* 45972 */ MCD_OPC_CheckPredicate, 3, 11, 160, 0, // Skip to: 86948 /* 45977 */ MCD_OPC_CheckField, 21, 1, 1, 4, 160, 0, // Skip to: 86948 /* 45984 */ MCD_OPC_Decode, 202, 23, 238, 1, // Opcode: SMAXv4i16 /* 45989 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 46050 /* 45994 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 45997 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46012 /* 46002 */ MCD_OPC_CheckPredicate, 3, 237, 159, 0, // Skip to: 86948 /* 46007 */ MCD_OPC_Decode, 231, 30, 238, 1, // Opcode: TRN2v4i16 /* 46012 */ MCD_OPC_FilterValue, 1, 227, 159, 0, // Skip to: 86948 /* 46017 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 46020 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46035 /* 46025 */ MCD_OPC_CheckPredicate, 3, 214, 159, 0, // Skip to: 86948 /* 46030 */ MCD_OPC_Decode, 148, 22, 248, 1, // Opcode: SADALPv4i16_v2i32 /* 46035 */ MCD_OPC_FilterValue, 1, 204, 159, 0, // Skip to: 86948 /* 46040 */ MCD_OPC_CheckPredicate, 3, 199, 159, 0, // Skip to: 86948 /* 46045 */ MCD_OPC_Decode, 181, 8, 244, 1, // Opcode: FCVTNv2i32 /* 46050 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 46072 /* 46055 */ MCD_OPC_CheckPredicate, 3, 184, 159, 0, // Skip to: 86948 /* 46060 */ MCD_OPC_CheckField, 21, 1, 1, 177, 159, 0, // Skip to: 86948 /* 46067 */ MCD_OPC_Decode, 232, 23, 238, 1, // Opcode: SMINv4i16 /* 46072 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 46094 /* 46077 */ MCD_OPC_CheckPredicate, 3, 162, 159, 0, // Skip to: 86948 /* 46082 */ MCD_OPC_CheckField, 21, 1, 1, 155, 159, 0, // Skip to: 86948 /* 46089 */ MCD_OPC_Decode, 132, 22, 234, 1, // Opcode: SABDLv4i16_v4i32 /* 46094 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 46116 /* 46099 */ MCD_OPC_CheckPredicate, 3, 140, 159, 0, // Skip to: 86948 /* 46104 */ MCD_OPC_CheckField, 21, 1, 1, 133, 159, 0, // Skip to: 86948 /* 46111 */ MCD_OPC_Decode, 142, 22, 238, 1, // Opcode: SABDv4i16 /* 46116 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 46177 /* 46121 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 46124 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46139 /* 46129 */ MCD_OPC_CheckPredicate, 3, 110, 159, 0, // Skip to: 86948 /* 46134 */ MCD_OPC_Decode, 159, 35, 238, 1, // Opcode: ZIP2v4i16 /* 46139 */ MCD_OPC_FilterValue, 1, 100, 159, 0, // Skip to: 86948 /* 46144 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 46147 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46162 /* 46152 */ MCD_OPC_CheckPredicate, 3, 87, 159, 0, // Skip to: 86948 /* 46157 */ MCD_OPC_Decode, 160, 24, 239, 1, // Opcode: SQABSv4i16 /* 46162 */ MCD_OPC_FilterValue, 1, 77, 159, 0, // Skip to: 86948 /* 46167 */ MCD_OPC_CheckPredicate, 3, 72, 159, 0, // Skip to: 86948 /* 46172 */ MCD_OPC_Decode, 249, 7, 129, 2, // Opcode: FCVTLv2i32 /* 46177 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 46199 /* 46182 */ MCD_OPC_CheckPredicate, 3, 57, 159, 0, // Skip to: 86948 /* 46187 */ MCD_OPC_CheckField, 21, 1, 1, 50, 159, 0, // Skip to: 86948 /* 46194 */ MCD_OPC_Decode, 254, 21, 130, 2, // Opcode: SABAv4i16 /* 46199 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 46221 /* 46204 */ MCD_OPC_CheckPredicate, 3, 35, 159, 0, // Skip to: 86948 /* 46209 */ MCD_OPC_CheckField, 21, 1, 1, 28, 159, 0, // Skip to: 86948 /* 46216 */ MCD_OPC_Decode, 240, 23, 254, 1, // Opcode: SMLALv4i16_v4i32 /* 46221 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 46243 /* 46226 */ MCD_OPC_CheckPredicate, 3, 13, 159, 0, // Skip to: 86948 /* 46231 */ MCD_OPC_CheckField, 21, 1, 1, 6, 159, 0, // Skip to: 86948 /* 46238 */ MCD_OPC_Decode, 198, 1, 238, 1, // Opcode: ADDv4i16 /* 46243 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 46281 /* 46248 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 46251 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46266 /* 46256 */ MCD_OPC_CheckPredicate, 3, 239, 158, 0, // Skip to: 86948 /* 46261 */ MCD_OPC_Decode, 223, 3, 239, 1, // Opcode: CMGTv4i16rz /* 46266 */ MCD_OPC_FilterValue, 57, 229, 158, 0, // Skip to: 86948 /* 46271 */ MCD_OPC_CheckPredicate, 4, 224, 158, 0, // Skip to: 86948 /* 46276 */ MCD_OPC_Decode, 137, 12, 239, 1, // Opcode: FRINTNv4f16 /* 46281 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 46303 /* 46286 */ MCD_OPC_CheckPredicate, 3, 209, 158, 0, // Skip to: 86948 /* 46291 */ MCD_OPC_CheckField, 21, 1, 1, 202, 158, 0, // Skip to: 86948 /* 46298 */ MCD_OPC_Decode, 237, 4, 238, 1, // Opcode: CMTSTv4i16 /* 46303 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 46325 /* 46308 */ MCD_OPC_CheckPredicate, 3, 187, 158, 0, // Skip to: 86948 /* 46313 */ MCD_OPC_CheckField, 21, 1, 1, 180, 158, 0, // Skip to: 86948 /* 46320 */ MCD_OPC_Decode, 212, 24, 254, 1, // Opcode: SQDMLALv4i16_v4i32 /* 46325 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 46347 /* 46330 */ MCD_OPC_CheckPredicate, 3, 165, 158, 0, // Skip to: 86948 /* 46335 */ MCD_OPC_CheckField, 21, 1, 1, 158, 158, 0, // Skip to: 86948 /* 46342 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: MLAv4i16 /* 46347 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 46385 /* 46352 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 46355 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46370 /* 46360 */ MCD_OPC_CheckPredicate, 3, 135, 158, 0, // Skip to: 86948 /* 46365 */ MCD_OPC_Decode, 191, 3, 239, 1, // Opcode: CMEQv4i16rz /* 46370 */ MCD_OPC_FilterValue, 57, 125, 158, 0, // Skip to: 86948 /* 46375 */ MCD_OPC_CheckPredicate, 4, 120, 158, 0, // Skip to: 86948 /* 46380 */ MCD_OPC_Decode, 254, 11, 239, 1, // Opcode: FRINTMv4f16 /* 46385 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 46407 /* 46390 */ MCD_OPC_CheckPredicate, 3, 105, 158, 0, // Skip to: 86948 /* 46395 */ MCD_OPC_CheckField, 21, 1, 1, 98, 158, 0, // Skip to: 86948 /* 46402 */ MCD_OPC_Decode, 160, 20, 238, 1, // Opcode: MULv4i16 /* 46407 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 46429 /* 46412 */ MCD_OPC_CheckPredicate, 3, 83, 158, 0, // Skip to: 86948 /* 46417 */ MCD_OPC_CheckField, 21, 1, 1, 76, 158, 0, // Skip to: 86948 /* 46424 */ MCD_OPC_Decode, 250, 23, 254, 1, // Opcode: SMLSLv4i16_v4i32 /* 46429 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 46451 /* 46434 */ MCD_OPC_CheckPredicate, 3, 61, 158, 0, // Skip to: 86948 /* 46439 */ MCD_OPC_CheckField, 21, 1, 1, 54, 158, 0, // Skip to: 86948 /* 46446 */ MCD_OPC_Decode, 179, 23, 238, 1, // Opcode: SMAXPv4i16 /* 46451 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 46519 /* 46456 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 46459 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46474 /* 46464 */ MCD_OPC_CheckPredicate, 3, 31, 158, 0, // Skip to: 86948 /* 46469 */ MCD_OPC_Decode, 130, 4, 239, 1, // Opcode: CMLTv4i16rz /* 46474 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 46489 /* 46479 */ MCD_OPC_CheckPredicate, 3, 16, 158, 0, // Skip to: 86948 /* 46484 */ MCD_OPC_Decode, 188, 23, 249, 1, // Opcode: SMAXVv4i16v /* 46489 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 46504 /* 46494 */ MCD_OPC_CheckPredicate, 3, 1, 158, 0, // Skip to: 86948 /* 46499 */ MCD_OPC_Decode, 218, 23, 249, 1, // Opcode: SMINVv4i16v /* 46504 */ MCD_OPC_FilterValue, 57, 247, 157, 0, // Skip to: 86948 /* 46509 */ MCD_OPC_CheckPredicate, 4, 242, 157, 0, // Skip to: 86948 /* 46514 */ MCD_OPC_Decode, 164, 8, 239, 1, // Opcode: FCVTNSv4f16 /* 46519 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 46541 /* 46524 */ MCD_OPC_CheckPredicate, 3, 227, 157, 0, // Skip to: 86948 /* 46529 */ MCD_OPC_CheckField, 21, 1, 1, 220, 157, 0, // Skip to: 86948 /* 46536 */ MCD_OPC_Decode, 209, 23, 238, 1, // Opcode: SMINPv4i16 /* 46541 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 46563 /* 46546 */ MCD_OPC_CheckPredicate, 3, 205, 157, 0, // Skip to: 86948 /* 46551 */ MCD_OPC_CheckField, 21, 1, 1, 198, 157, 0, // Skip to: 86948 /* 46558 */ MCD_OPC_Decode, 224, 24, 254, 1, // Opcode: SQDMLSLv4i16_v4i32 /* 46563 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 46585 /* 46568 */ MCD_OPC_CheckPredicate, 3, 183, 157, 0, // Skip to: 86948 /* 46573 */ MCD_OPC_CheckField, 21, 1, 1, 176, 157, 0, // Skip to: 86948 /* 46580 */ MCD_OPC_Decode, 235, 24, 238, 1, // Opcode: SQDMULHv4i16 /* 46585 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 46638 /* 46590 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 46593 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46608 /* 46598 */ MCD_OPC_CheckPredicate, 3, 153, 157, 0, // Skip to: 86948 /* 46603 */ MCD_OPC_Decode, 134, 1, 239, 1, // Opcode: ABSv4i16 /* 46608 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 46623 /* 46613 */ MCD_OPC_CheckPredicate, 3, 138, 157, 0, // Skip to: 86948 /* 46618 */ MCD_OPC_Decode, 168, 1, 249, 1, // Opcode: ADDVv4i16v /* 46623 */ MCD_OPC_FilterValue, 57, 128, 157, 0, // Skip to: 86948 /* 46628 */ MCD_OPC_CheckPredicate, 4, 123, 157, 0, // Skip to: 86948 /* 46633 */ MCD_OPC_Decode, 136, 8, 239, 1, // Opcode: FCVTMSv4f16 /* 46638 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 46660 /* 46643 */ MCD_OPC_CheckPredicate, 3, 108, 157, 0, // Skip to: 86948 /* 46648 */ MCD_OPC_CheckField, 21, 1, 1, 101, 157, 0, // Skip to: 86948 /* 46655 */ MCD_OPC_Decode, 153, 1, 238, 1, // Opcode: ADDPv4i16 /* 46660 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 46682 /* 46665 */ MCD_OPC_CheckPredicate, 3, 86, 157, 0, // Skip to: 86948 /* 46670 */ MCD_OPC_CheckField, 21, 1, 1, 79, 157, 0, // Skip to: 86948 /* 46677 */ MCD_OPC_Decode, 143, 24, 234, 1, // Opcode: SMULLv4i16_v4i32 /* 46682 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 46704 /* 46687 */ MCD_OPC_CheckPredicate, 4, 64, 157, 0, // Skip to: 86948 /* 46692 */ MCD_OPC_CheckField, 16, 6, 57, 57, 157, 0, // Skip to: 86948 /* 46699 */ MCD_OPC_Decode, 228, 7, 239, 1, // Opcode: FCVTASv4f16 /* 46704 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 46726 /* 46709 */ MCD_OPC_CheckPredicate, 3, 42, 157, 0, // Skip to: 86948 /* 46714 */ MCD_OPC_CheckField, 21, 1, 1, 35, 157, 0, // Skip to: 86948 /* 46721 */ MCD_OPC_Decode, 248, 24, 234, 1, // Opcode: SQDMULLv4i16_v4i32 /* 46726 */ MCD_OPC_FilterValue, 54, 25, 157, 0, // Skip to: 86948 /* 46731 */ MCD_OPC_CheckPredicate, 4, 20, 157, 0, // Skip to: 86948 /* 46736 */ MCD_OPC_CheckField, 16, 6, 57, 13, 157, 0, // Skip to: 86948 /* 46743 */ MCD_OPC_Decode, 213, 22, 239, 1, // Opcode: SCVTFv4f16 /* 46748 */ MCD_OPC_FilterValue, 1, 152, 5, 0, // Skip to: 48185 /* 46753 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 46756 */ MCD_OPC_FilterValue, 0, 205, 0, 0, // Skip to: 46966 /* 46761 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 46764 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 46786 /* 46769 */ MCD_OPC_CheckPredicate, 3, 238, 156, 0, // Skip to: 86948 /* 46774 */ MCD_OPC_CheckField, 21, 1, 1, 231, 156, 0, // Skip to: 86948 /* 46781 */ MCD_OPC_Decode, 155, 31, 234, 1, // Opcode: UADDLv4i16_v4i32 /* 46786 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 46824 /* 46791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 46794 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46809 /* 46799 */ MCD_OPC_CheckPredicate, 4, 208, 156, 0, // Skip to: 86948 /* 46804 */ MCD_OPC_Decode, 202, 9, 238, 1, // Opcode: FMAXNMPv4f16 /* 46809 */ MCD_OPC_FilterValue, 1, 198, 156, 0, // Skip to: 86948 /* 46814 */ MCD_OPC_CheckPredicate, 3, 193, 156, 0, // Skip to: 86948 /* 46819 */ MCD_OPC_Decode, 222, 31, 238, 1, // Opcode: UHADDv4i16 /* 46824 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 46846 /* 46829 */ MCD_OPC_CheckPredicate, 3, 178, 156, 0, // Skip to: 86948 /* 46834 */ MCD_OPC_CheckField, 16, 6, 32, 171, 156, 0, // Skip to: 86948 /* 46841 */ MCD_OPC_Decode, 206, 21, 239, 1, // Opcode: REV32v4i16 /* 46846 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 46868 /* 46851 */ MCD_OPC_CheckPredicate, 3, 156, 156, 0, // Skip to: 86948 /* 46856 */ MCD_OPC_CheckField, 21, 1, 1, 149, 156, 0, // Skip to: 86948 /* 46863 */ MCD_OPC_Decode, 218, 32, 238, 1, // Opcode: UQADDv4i16 /* 46868 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 46890 /* 46873 */ MCD_OPC_CheckPredicate, 3, 134, 156, 0, // Skip to: 86948 /* 46878 */ MCD_OPC_CheckField, 21, 1, 1, 127, 156, 0, // Skip to: 86948 /* 46885 */ MCD_OPC_Decode, 165, 31, 242, 1, // Opcode: UADDWv4i16_v4i32 /* 46890 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 46928 /* 46895 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 46898 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46913 /* 46903 */ MCD_OPC_CheckPredicate, 4, 104, 156, 0, // Skip to: 86948 /* 46908 */ MCD_OPC_Decode, 182, 6, 238, 1, // Opcode: FADDPv4f16 /* 46913 */ MCD_OPC_FilterValue, 1, 94, 156, 0, // Skip to: 86948 /* 46918 */ MCD_OPC_CheckPredicate, 3, 89, 156, 0, // Skip to: 86948 /* 46923 */ MCD_OPC_Decode, 221, 33, 238, 1, // Opcode: URHADDv4i16 /* 46928 */ MCD_OPC_FilterValue, 7, 79, 156, 0, // Skip to: 86948 /* 46933 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 46936 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46951 /* 46941 */ MCD_OPC_CheckPredicate, 4, 66, 156, 0, // Skip to: 86948 /* 46946 */ MCD_OPC_Decode, 158, 11, 238, 1, // Opcode: FMULv4f16 /* 46951 */ MCD_OPC_FilterValue, 1, 56, 156, 0, // Skip to: 86948 /* 46956 */ MCD_OPC_CheckPredicate, 3, 51, 156, 0, // Skip to: 86948 /* 46961 */ MCD_OPC_Decode, 222, 2, 130, 2, // Opcode: BSLv8i8 /* 46966 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 47261 /* 46971 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 46974 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 46996 /* 46979 */ MCD_OPC_CheckPredicate, 3, 28, 156, 0, // Skip to: 86948 /* 46984 */ MCD_OPC_CheckField, 21, 1, 1, 21, 156, 0, // Skip to: 86948 /* 46991 */ MCD_OPC_Decode, 166, 34, 234, 1, // Opcode: USUBLv4i16_v4i32 /* 46996 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 47034 /* 47001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 47004 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47019 /* 47009 */ MCD_OPC_CheckPredicate, 4, 254, 155, 0, // Skip to: 86948 /* 47014 */ MCD_OPC_Decode, 255, 6, 238, 1, // Opcode: FCMGEv4f16 /* 47019 */ MCD_OPC_FilterValue, 1, 244, 155, 0, // Skip to: 86948 /* 47024 */ MCD_OPC_CheckPredicate, 3, 239, 155, 0, // Skip to: 86948 /* 47029 */ MCD_OPC_Decode, 228, 31, 238, 1, // Opcode: UHSUBv4i16 /* 47034 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47072 /* 47039 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47042 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47057 /* 47047 */ MCD_OPC_CheckPredicate, 3, 216, 155, 0, // Skip to: 86948 /* 47052 */ MCD_OPC_Decode, 144, 31, 239, 1, // Opcode: UADDLPv4i16_v2i32 /* 47057 */ MCD_OPC_FilterValue, 33, 206, 155, 0, // Skip to: 86948 /* 47062 */ MCD_OPC_CheckPredicate, 3, 201, 155, 0, // Skip to: 86948 /* 47067 */ MCD_OPC_Decode, 179, 26, 244, 1, // Opcode: SQXTUNv4i16 /* 47072 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 47110 /* 47077 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 47080 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47095 /* 47085 */ MCD_OPC_CheckPredicate, 4, 178, 155, 0, // Skip to: 86948 /* 47090 */ MCD_OPC_Decode, 158, 6, 238, 1, // Opcode: FACGEv4f16 /* 47095 */ MCD_OPC_FilterValue, 1, 168, 155, 0, // Skip to: 86948 /* 47100 */ MCD_OPC_CheckPredicate, 3, 163, 155, 0, // Skip to: 86948 /* 47105 */ MCD_OPC_Decode, 204, 33, 238, 1, // Opcode: UQSUBv4i16 /* 47110 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47132 /* 47115 */ MCD_OPC_CheckPredicate, 3, 148, 155, 0, // Skip to: 86948 /* 47120 */ MCD_OPC_CheckField, 21, 1, 1, 141, 155, 0, // Skip to: 86948 /* 47127 */ MCD_OPC_Decode, 172, 34, 242, 1, // Opcode: USUBWv4i16_v4i32 /* 47132 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 47170 /* 47137 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 47140 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47155 /* 47145 */ MCD_OPC_CheckPredicate, 4, 118, 155, 0, // Skip to: 86948 /* 47150 */ MCD_OPC_Decode, 228, 9, 238, 1, // Opcode: FMAXPv4f16 /* 47155 */ MCD_OPC_FilterValue, 1, 108, 155, 0, // Skip to: 86948 /* 47160 */ MCD_OPC_CheckPredicate, 3, 103, 155, 0, // Skip to: 86948 /* 47165 */ MCD_OPC_Decode, 234, 3, 238, 1, // Opcode: CMHIv4i16 /* 47170 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 47223 /* 47175 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47178 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47193 /* 47183 */ MCD_OPC_CheckPredicate, 3, 80, 155, 0, // Skip to: 86948 /* 47188 */ MCD_OPC_Decode, 152, 34, 248, 1, // Opcode: USQADDv4i16 /* 47193 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 47208 /* 47198 */ MCD_OPC_CheckPredicate, 3, 65, 155, 0, // Skip to: 86948 /* 47203 */ MCD_OPC_Decode, 135, 23, 129, 2, // Opcode: SHLLv4i16 /* 47208 */ MCD_OPC_FilterValue, 48, 55, 155, 0, // Skip to: 86948 /* 47213 */ MCD_OPC_CheckPredicate, 3, 50, 155, 0, // Skip to: 86948 /* 47218 */ MCD_OPC_Decode, 149, 31, 166, 2, // Opcode: UADDLVv4i16v /* 47223 */ MCD_OPC_FilterValue, 7, 40, 155, 0, // Skip to: 86948 /* 47228 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 47231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47246 /* 47236 */ MCD_OPC_CheckPredicate, 4, 27, 155, 0, // Skip to: 86948 /* 47241 */ MCD_OPC_Decode, 177, 9, 238, 1, // Opcode: FDIVv4f16 /* 47246 */ MCD_OPC_FilterValue, 1, 17, 155, 0, // Skip to: 86948 /* 47251 */ MCD_OPC_CheckPredicate, 3, 12, 155, 0, // Skip to: 86948 /* 47256 */ MCD_OPC_Decode, 242, 3, 238, 1, // Opcode: CMHSv4i16 /* 47261 */ MCD_OPC_FilterValue, 2, 195, 0, 0, // Skip to: 47461 /* 47266 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 47269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47291 /* 47274 */ MCD_OPC_CheckPredicate, 3, 245, 154, 0, // Skip to: 86948 /* 47279 */ MCD_OPC_CheckField, 21, 1, 1, 238, 154, 0, // Skip to: 86948 /* 47286 */ MCD_OPC_Decode, 179, 21, 252, 1, // Opcode: RADDHNv4i32_v4i16 /* 47291 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47313 /* 47296 */ MCD_OPC_CheckPredicate, 3, 223, 154, 0, // Skip to: 86948 /* 47301 */ MCD_OPC_CheckField, 21, 1, 1, 216, 154, 0, // Skip to: 86948 /* 47308 */ MCD_OPC_Decode, 133, 34, 238, 1, // Opcode: USHLv4i16 /* 47313 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47351 /* 47318 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47321 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47336 /* 47326 */ MCD_OPC_CheckPredicate, 3, 193, 154, 0, // Skip to: 86948 /* 47331 */ MCD_OPC_Decode, 178, 3, 239, 1, // Opcode: CLZv4i16 /* 47336 */ MCD_OPC_FilterValue, 33, 183, 154, 0, // Skip to: 86948 /* 47341 */ MCD_OPC_CheckPredicate, 3, 178, 154, 0, // Skip to: 86948 /* 47346 */ MCD_OPC_Decode, 213, 33, 244, 1, // Opcode: UQXTNv4i16 /* 47351 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47373 /* 47356 */ MCD_OPC_CheckPredicate, 3, 163, 154, 0, // Skip to: 86948 /* 47361 */ MCD_OPC_CheckField, 21, 1, 1, 156, 154, 0, // Skip to: 86948 /* 47368 */ MCD_OPC_Decode, 172, 33, 238, 1, // Opcode: UQSHLv4i16 /* 47373 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47395 /* 47378 */ MCD_OPC_CheckPredicate, 3, 141, 154, 0, // Skip to: 86948 /* 47383 */ MCD_OPC_CheckField, 21, 1, 1, 134, 154, 0, // Skip to: 86948 /* 47390 */ MCD_OPC_Decode, 238, 30, 254, 1, // Opcode: UABALv4i16_v4i32 /* 47395 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47417 /* 47400 */ MCD_OPC_CheckPredicate, 3, 119, 154, 0, // Skip to: 86948 /* 47405 */ MCD_OPC_CheckField, 21, 1, 1, 112, 154, 0, // Skip to: 86948 /* 47412 */ MCD_OPC_Decode, 229, 33, 238, 1, // Opcode: URSHLv4i16 /* 47417 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 47439 /* 47422 */ MCD_OPC_CheckPredicate, 3, 97, 154, 0, // Skip to: 86948 /* 47427 */ MCD_OPC_CheckField, 16, 6, 32, 90, 154, 0, // Skip to: 86948 /* 47434 */ MCD_OPC_Decode, 191, 21, 239, 1, // Opcode: RBITv8i8 /* 47439 */ MCD_OPC_FilterValue, 7, 80, 154, 0, // Skip to: 86948 /* 47444 */ MCD_OPC_CheckPredicate, 3, 75, 154, 0, // Skip to: 86948 /* 47449 */ MCD_OPC_CheckField, 21, 1, 1, 68, 154, 0, // Skip to: 86948 /* 47456 */ MCD_OPC_Decode, 145, 33, 238, 1, // Opcode: UQRSHLv4i16 /* 47461 */ MCD_OPC_FilterValue, 3, 195, 0, 0, // Skip to: 47661 /* 47466 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 47469 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47491 /* 47474 */ MCD_OPC_CheckPredicate, 3, 45, 154, 0, // Skip to: 86948 /* 47479 */ MCD_OPC_CheckField, 21, 1, 1, 38, 154, 0, // Skip to: 86948 /* 47486 */ MCD_OPC_Decode, 242, 21, 252, 1, // Opcode: RSUBHNv4i32_v4i16 /* 47491 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47513 /* 47496 */ MCD_OPC_CheckPredicate, 3, 23, 154, 0, // Skip to: 86948 /* 47501 */ MCD_OPC_CheckField, 21, 1, 1, 16, 154, 0, // Skip to: 86948 /* 47508 */ MCD_OPC_Decode, 130, 32, 238, 1, // Opcode: UMAXv4i16 /* 47513 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47551 /* 47518 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47521 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47536 /* 47526 */ MCD_OPC_CheckPredicate, 3, 249, 153, 0, // Skip to: 86948 /* 47531 */ MCD_OPC_Decode, 138, 31, 248, 1, // Opcode: UADALPv4i16_v2i32 /* 47536 */ MCD_OPC_FilterValue, 33, 239, 153, 0, // Skip to: 86948 /* 47541 */ MCD_OPC_CheckPredicate, 3, 234, 153, 0, // Skip to: 86948 /* 47546 */ MCD_OPC_Decode, 216, 8, 244, 1, // Opcode: FCVTXNv2f32 /* 47551 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47573 /* 47556 */ MCD_OPC_CheckPredicate, 3, 219, 153, 0, // Skip to: 86948 /* 47561 */ MCD_OPC_CheckField, 21, 1, 1, 212, 153, 0, // Skip to: 86948 /* 47568 */ MCD_OPC_Decode, 159, 32, 238, 1, // Opcode: UMINv4i16 /* 47573 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47595 /* 47578 */ MCD_OPC_CheckPredicate, 3, 197, 153, 0, // Skip to: 86948 /* 47583 */ MCD_OPC_CheckField, 21, 1, 1, 190, 153, 0, // Skip to: 86948 /* 47590 */ MCD_OPC_Decode, 250, 30, 234, 1, // Opcode: UABDLv4i16_v4i32 /* 47595 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47617 /* 47600 */ MCD_OPC_CheckPredicate, 3, 175, 153, 0, // Skip to: 86948 /* 47605 */ MCD_OPC_CheckField, 21, 1, 1, 168, 153, 0, // Skip to: 86948 /* 47612 */ MCD_OPC_Decode, 132, 31, 238, 1, // Opcode: UABDv4i16 /* 47617 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 47639 /* 47622 */ MCD_OPC_CheckPredicate, 3, 153, 153, 0, // Skip to: 86948 /* 47627 */ MCD_OPC_CheckField, 16, 6, 32, 146, 153, 0, // Skip to: 86948 /* 47634 */ MCD_OPC_Decode, 154, 25, 239, 1, // Opcode: SQNEGv4i16 /* 47639 */ MCD_OPC_FilterValue, 7, 136, 153, 0, // Skip to: 86948 /* 47644 */ MCD_OPC_CheckPredicate, 3, 131, 153, 0, // Skip to: 86948 /* 47649 */ MCD_OPC_CheckField, 21, 1, 1, 124, 153, 0, // Skip to: 86948 /* 47656 */ MCD_OPC_Decode, 244, 30, 130, 2, // Opcode: UABAv4i16 /* 47661 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 47865 /* 47666 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 47669 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47691 /* 47674 */ MCD_OPC_CheckPredicate, 3, 101, 153, 0, // Skip to: 86948 /* 47679 */ MCD_OPC_CheckField, 21, 1, 1, 94, 153, 0, // Skip to: 86948 /* 47686 */ MCD_OPC_Decode, 167, 32, 254, 1, // Opcode: UMLALv4i16_v4i32 /* 47691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 47729 /* 47696 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 47699 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47714 /* 47704 */ MCD_OPC_CheckPredicate, 7, 71, 153, 0, // Skip to: 86948 /* 47709 */ MCD_OPC_Decode, 164, 25, 130, 2, // Opcode: SQRDMLAHv4i16 /* 47714 */ MCD_OPC_FilterValue, 1, 61, 153, 0, // Skip to: 86948 /* 47719 */ MCD_OPC_CheckPredicate, 3, 56, 153, 0, // Skip to: 86948 /* 47724 */ MCD_OPC_Decode, 131, 30, 238, 1, // Opcode: SUBv4i16 /* 47729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47767 /* 47734 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47737 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47752 /* 47742 */ MCD_OPC_CheckPredicate, 3, 33, 153, 0, // Skip to: 86948 /* 47747 */ MCD_OPC_Decode, 207, 3, 239, 1, // Opcode: CMGEv4i16rz /* 47752 */ MCD_OPC_FilterValue, 57, 23, 153, 0, // Skip to: 86948 /* 47757 */ MCD_OPC_CheckPredicate, 4, 18, 153, 0, // Skip to: 86948 /* 47762 */ MCD_OPC_Decode, 232, 11, 239, 1, // Opcode: FRINTAv4f16 /* 47767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 47805 /* 47772 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 47775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47790 /* 47780 */ MCD_OPC_CheckPredicate, 7, 251, 152, 0, // Skip to: 86948 /* 47785 */ MCD_OPC_Decode, 176, 25, 130, 2, // Opcode: SQRDMLSHv4i16 /* 47790 */ MCD_OPC_FilterValue, 1, 241, 152, 0, // Skip to: 86948 /* 47795 */ MCD_OPC_CheckPredicate, 3, 236, 152, 0, // Skip to: 86948 /* 47800 */ MCD_OPC_Decode, 190, 3, 238, 1, // Opcode: CMEQv4i16 /* 47805 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47827 /* 47810 */ MCD_OPC_CheckPredicate, 3, 221, 152, 0, // Skip to: 86948 /* 47815 */ MCD_OPC_CheckField, 21, 1, 1, 214, 152, 0, // Skip to: 86948 /* 47822 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: MLSv4i16 /* 47827 */ MCD_OPC_FilterValue, 6, 204, 152, 0, // Skip to: 86948 /* 47832 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47835 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47850 /* 47840 */ MCD_OPC_CheckPredicate, 3, 191, 152, 0, // Skip to: 86948 /* 47845 */ MCD_OPC_Decode, 250, 3, 239, 1, // Opcode: CMLEv4i16rz /* 47850 */ MCD_OPC_FilterValue, 57, 181, 152, 0, // Skip to: 86948 /* 47855 */ MCD_OPC_CheckPredicate, 4, 176, 152, 0, // Skip to: 86948 /* 47860 */ MCD_OPC_Decode, 159, 12, 239, 1, // Opcode: FRINTXv4f16 /* 47865 */ MCD_OPC_FilterValue, 5, 182, 0, 0, // Skip to: 48052 /* 47870 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 47873 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47895 /* 47878 */ MCD_OPC_CheckPredicate, 3, 153, 152, 0, // Skip to: 86948 /* 47883 */ MCD_OPC_CheckField, 21, 1, 1, 146, 152, 0, // Skip to: 86948 /* 47890 */ MCD_OPC_Decode, 177, 32, 254, 1, // Opcode: UMLSLv4i16_v4i32 /* 47895 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47917 /* 47900 */ MCD_OPC_CheckPredicate, 3, 131, 152, 0, // Skip to: 86948 /* 47905 */ MCD_OPC_CheckField, 21, 1, 1, 124, 152, 0, // Skip to: 86948 /* 47912 */ MCD_OPC_Decode, 235, 31, 238, 1, // Opcode: UMAXPv4i16 /* 47917 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 47970 /* 47922 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 47925 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 47940 /* 47930 */ MCD_OPC_CheckPredicate, 3, 101, 152, 0, // Skip to: 86948 /* 47935 */ MCD_OPC_Decode, 244, 31, 249, 1, // Opcode: UMAXVv4i16v /* 47940 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 47955 /* 47945 */ MCD_OPC_CheckPredicate, 3, 86, 152, 0, // Skip to: 86948 /* 47950 */ MCD_OPC_Decode, 145, 32, 249, 1, // Opcode: UMINVv4i16v /* 47955 */ MCD_OPC_FilterValue, 57, 76, 152, 0, // Skip to: 86948 /* 47960 */ MCD_OPC_CheckPredicate, 4, 71, 152, 0, // Skip to: 86948 /* 47965 */ MCD_OPC_Decode, 178, 8, 239, 1, // Opcode: FCVTNUv4f16 /* 47970 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47992 /* 47975 */ MCD_OPC_CheckPredicate, 3, 56, 152, 0, // Skip to: 86948 /* 47980 */ MCD_OPC_CheckField, 21, 1, 1, 49, 152, 0, // Skip to: 86948 /* 47987 */ MCD_OPC_Decode, 136, 32, 238, 1, // Opcode: UMINPv4i16 /* 47992 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 48014 /* 47997 */ MCD_OPC_CheckPredicate, 3, 34, 152, 0, // Skip to: 86948 /* 48002 */ MCD_OPC_CheckField, 21, 1, 1, 27, 152, 0, // Skip to: 86948 /* 48009 */ MCD_OPC_Decode, 188, 25, 238, 1, // Opcode: SQRDMULHv4i16 /* 48014 */ MCD_OPC_FilterValue, 6, 17, 152, 0, // Skip to: 86948 /* 48019 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 48022 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 48037 /* 48027 */ MCD_OPC_CheckPredicate, 3, 4, 152, 0, // Skip to: 86948 /* 48032 */ MCD_OPC_Decode, 183, 20, 239, 1, // Opcode: NEGv4i16 /* 48037 */ MCD_OPC_FilterValue, 57, 250, 151, 0, // Skip to: 86948 /* 48042 */ MCD_OPC_CheckPredicate, 4, 245, 151, 0, // Skip to: 86948 /* 48047 */ MCD_OPC_Decode, 150, 8, 239, 1, // Opcode: FCVTMUv4f16 /* 48052 */ MCD_OPC_FilterValue, 6, 99, 0, 0, // Skip to: 48156 /* 48057 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 48060 */ MCD_OPC_FilterValue, 0, 69, 0, 0, // Skip to: 48134 /* 48065 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 48068 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 48090 /* 48073 */ MCD_OPC_CheckPredicate, 3, 214, 151, 0, // Skip to: 86948 /* 48078 */ MCD_OPC_CheckField, 21, 1, 1, 207, 151, 0, // Skip to: 86948 /* 48085 */ MCD_OPC_Decode, 197, 32, 234, 1, // Opcode: UMULLv4i16_v4i32 /* 48090 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 48112 /* 48095 */ MCD_OPC_CheckPredicate, 4, 192, 151, 0, // Skip to: 86948 /* 48100 */ MCD_OPC_CheckField, 16, 6, 57, 185, 151, 0, // Skip to: 86948 /* 48107 */ MCD_OPC_Decode, 242, 7, 239, 1, // Opcode: FCVTAUv4f16 /* 48112 */ MCD_OPC_FilterValue, 3, 175, 151, 0, // Skip to: 86948 /* 48117 */ MCD_OPC_CheckPredicate, 4, 170, 151, 0, // Skip to: 86948 /* 48122 */ MCD_OPC_CheckField, 16, 6, 57, 163, 151, 0, // Skip to: 86948 /* 48129 */ MCD_OPC_Decode, 200, 31, 239, 1, // Opcode: UCVTFv4f16 /* 48134 */ MCD_OPC_FilterValue, 1, 153, 151, 0, // Skip to: 86948 /* 48139 */ MCD_OPC_CheckPredicate, 8, 148, 151, 0, // Skip to: 86948 /* 48144 */ MCD_OPC_CheckField, 21, 1, 0, 141, 151, 0, // Skip to: 86948 /* 48151 */ MCD_OPC_Decode, 162, 7, 167, 2, // Opcode: FCMLAv4f16 /* 48156 */ MCD_OPC_FilterValue, 7, 131, 151, 0, // Skip to: 86948 /* 48161 */ MCD_OPC_CheckPredicate, 8, 126, 151, 0, // Skip to: 86948 /* 48166 */ MCD_OPC_CheckField, 21, 1, 0, 119, 151, 0, // Skip to: 86948 /* 48173 */ MCD_OPC_CheckField, 10, 2, 1, 112, 151, 0, // Skip to: 86948 /* 48180 */ MCD_OPC_Decode, 208, 6, 168, 2, // Opcode: FCADDv4f16 /* 48185 */ MCD_OPC_FilterValue, 2, 250, 6, 0, // Skip to: 49976 /* 48190 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 48193 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 48215 /* 48198 */ MCD_OPC_CheckPredicate, 3, 89, 151, 0, // Skip to: 86948 /* 48203 */ MCD_OPC_CheckField, 21, 1, 1, 82, 151, 0, // Skip to: 86948 /* 48210 */ MCD_OPC_Decode, 167, 22, 133, 2, // Opcode: SADDLv8i16_v4i32 /* 48215 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 48253 /* 48220 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48223 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48238 /* 48228 */ MCD_OPC_CheckPredicate, 4, 59, 151, 0, // Skip to: 86948 /* 48233 */ MCD_OPC_Decode, 222, 9, 133, 2, // Opcode: FMAXNMv8f16 /* 48238 */ MCD_OPC_FilterValue, 1, 49, 151, 0, // Skip to: 86948 /* 48243 */ MCD_OPC_CheckPredicate, 3, 44, 151, 0, // Skip to: 86948 /* 48248 */ MCD_OPC_Decode, 131, 23, 133, 2, // Opcode: SHADDv8i16 /* 48253 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 48275 /* 48258 */ MCD_OPC_CheckPredicate, 3, 29, 151, 0, // Skip to: 86948 /* 48263 */ MCD_OPC_CheckField, 16, 6, 32, 22, 151, 0, // Skip to: 86948 /* 48270 */ MCD_OPC_Decode, 213, 21, 138, 2, // Opcode: REV64v8i16 /* 48275 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 48313 /* 48280 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48283 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48298 /* 48288 */ MCD_OPC_CheckPredicate, 4, 255, 150, 0, // Skip to: 86948 /* 48293 */ MCD_OPC_Decode, 194, 10, 141, 2, // Opcode: FMLAv8f16 /* 48298 */ MCD_OPC_FilterValue, 1, 245, 150, 0, // Skip to: 86948 /* 48303 */ MCD_OPC_CheckPredicate, 3, 240, 150, 0, // Skip to: 86948 /* 48308 */ MCD_OPC_Decode, 181, 24, 133, 2, // Opcode: SQADDv8i16 /* 48313 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 48335 /* 48318 */ MCD_OPC_CheckPredicate, 3, 225, 150, 0, // Skip to: 86948 /* 48323 */ MCD_OPC_CheckField, 21, 1, 1, 218, 150, 0, // Skip to: 86948 /* 48330 */ MCD_OPC_Decode, 176, 22, 133, 2, // Opcode: SADDWv8i16_v4i32 /* 48335 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 48373 /* 48340 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48343 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48358 /* 48348 */ MCD_OPC_CheckPredicate, 4, 195, 150, 0, // Skip to: 86948 /* 48353 */ MCD_OPC_Decode, 202, 6, 133, 2, // Opcode: FADDv8f16 /* 48358 */ MCD_OPC_FilterValue, 1, 185, 150, 0, // Skip to: 86948 /* 48363 */ MCD_OPC_CheckPredicate, 3, 180, 150, 0, // Skip to: 86948 /* 48368 */ MCD_OPC_Decode, 187, 26, 133, 2, // Opcode: SRHADDv8i16 /* 48373 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 48395 /* 48378 */ MCD_OPC_CheckPredicate, 3, 165, 150, 0, // Skip to: 86948 /* 48383 */ MCD_OPC_CheckField, 21, 1, 0, 158, 150, 0, // Skip to: 86948 /* 48390 */ MCD_OPC_Decode, 201, 34, 133, 2, // Opcode: UZP1v8i16 /* 48395 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 48433 /* 48400 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48403 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48418 /* 48408 */ MCD_OPC_CheckPredicate, 4, 135, 150, 0, // Skip to: 86948 /* 48413 */ MCD_OPC_Decode, 137, 11, 133, 2, // Opcode: FMULXv8f16 /* 48418 */ MCD_OPC_FilterValue, 1, 125, 150, 0, // Skip to: 86948 /* 48423 */ MCD_OPC_CheckPredicate, 3, 120, 150, 0, // Skip to: 86948 /* 48428 */ MCD_OPC_Decode, 187, 2, 133, 2, // Opcode: BICv16i8 /* 48433 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 48455 /* 48438 */ MCD_OPC_CheckPredicate, 3, 105, 150, 0, // Skip to: 86948 /* 48443 */ MCD_OPC_CheckField, 21, 1, 1, 98, 150, 0, // Skip to: 86948 /* 48450 */ MCD_OPC_Decode, 165, 27, 133, 2, // Opcode: SSUBLv8i16_v4i32 /* 48455 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 48493 /* 48460 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48463 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48478 /* 48468 */ MCD_OPC_CheckPredicate, 4, 75, 150, 0, // Skip to: 86948 /* 48473 */ MCD_OPC_Decode, 237, 6, 133, 2, // Opcode: FCMEQv8f16 /* 48478 */ MCD_OPC_FilterValue, 1, 65, 150, 0, // Skip to: 86948 /* 48483 */ MCD_OPC_CheckPredicate, 3, 60, 150, 0, // Skip to: 86948 /* 48488 */ MCD_OPC_Decode, 157, 23, 133, 2, // Opcode: SHSUBv8i16 /* 48493 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 48554 /* 48498 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48501 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48516 /* 48506 */ MCD_OPC_CheckPredicate, 3, 37, 150, 0, // Skip to: 86948 /* 48511 */ MCD_OPC_Decode, 218, 30, 133, 2, // Opcode: TRN1v8i16 /* 48516 */ MCD_OPC_FilterValue, 1, 27, 150, 0, // Skip to: 86948 /* 48521 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 48524 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48539 /* 48529 */ MCD_OPC_CheckPredicate, 3, 14, 150, 0, // Skip to: 86948 /* 48534 */ MCD_OPC_Decode, 156, 22, 138, 2, // Opcode: SADDLPv8i16_v4i32 /* 48539 */ MCD_OPC_FilterValue, 1, 4, 150, 0, // Skip to: 86948 /* 48544 */ MCD_OPC_CheckPredicate, 3, 255, 149, 0, // Skip to: 86948 /* 48549 */ MCD_OPC_Decode, 131, 35, 147, 2, // Opcode: XTNv8i16 /* 48554 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 48576 /* 48559 */ MCD_OPC_CheckPredicate, 3, 240, 149, 0, // Skip to: 86948 /* 48564 */ MCD_OPC_CheckField, 21, 1, 1, 233, 149, 0, // Skip to: 86948 /* 48571 */ MCD_OPC_Decode, 163, 26, 133, 2, // Opcode: SQSUBv8i16 /* 48576 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 48598 /* 48581 */ MCD_OPC_CheckPredicate, 3, 218, 149, 0, // Skip to: 86948 /* 48586 */ MCD_OPC_CheckField, 21, 1, 1, 211, 149, 0, // Skip to: 86948 /* 48593 */ MCD_OPC_Decode, 171, 27, 133, 2, // Opcode: SSUBWv8i16_v4i32 /* 48598 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 48636 /* 48603 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48606 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48621 /* 48611 */ MCD_OPC_CheckPredicate, 4, 188, 149, 0, // Skip to: 86948 /* 48616 */ MCD_OPC_Decode, 248, 9, 133, 2, // Opcode: FMAXv8f16 /* 48621 */ MCD_OPC_FilterValue, 1, 178, 149, 0, // Skip to: 86948 /* 48626 */ MCD_OPC_CheckPredicate, 3, 173, 149, 0, // Skip to: 86948 /* 48631 */ MCD_OPC_Decode, 226, 3, 133, 2, // Opcode: CMGTv8i16 /* 48636 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 48697 /* 48641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48659 /* 48649 */ MCD_OPC_CheckPredicate, 3, 150, 149, 0, // Skip to: 86948 /* 48654 */ MCD_OPC_Decode, 146, 35, 133, 2, // Opcode: ZIP1v8i16 /* 48659 */ MCD_OPC_FilterValue, 1, 140, 149, 0, // Skip to: 86948 /* 48664 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 48667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48682 /* 48672 */ MCD_OPC_CheckPredicate, 3, 127, 149, 0, // Skip to: 86948 /* 48677 */ MCD_OPC_Decode, 150, 30, 147, 2, // Opcode: SUQADDv8i16 /* 48682 */ MCD_OPC_FilterValue, 16, 117, 149, 0, // Skip to: 86948 /* 48687 */ MCD_OPC_CheckPredicate, 3, 112, 149, 0, // Skip to: 86948 /* 48692 */ MCD_OPC_Decode, 161, 22, 160, 2, // Opcode: SADDLVv8i16v /* 48697 */ MCD_OPC_FilterValue, 15, 33, 0, 0, // Skip to: 48735 /* 48702 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48720 /* 48710 */ MCD_OPC_CheckPredicate, 4, 89, 149, 0, // Skip to: 86948 /* 48715 */ MCD_OPC_Decode, 217, 11, 133, 2, // Opcode: FRECPSv8f16 /* 48720 */ MCD_OPC_FilterValue, 1, 79, 149, 0, // Skip to: 86948 /* 48725 */ MCD_OPC_CheckPredicate, 3, 74, 149, 0, // Skip to: 86948 /* 48730 */ MCD_OPC_Decode, 210, 3, 133, 2, // Opcode: CMGEv8i16 /* 48735 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 48757 /* 48740 */ MCD_OPC_CheckPredicate, 3, 59, 149, 0, // Skip to: 86948 /* 48745 */ MCD_OPC_CheckField, 21, 1, 1, 52, 149, 0, // Skip to: 86948 /* 48752 */ MCD_OPC_Decode, 145, 1, 141, 2, // Opcode: ADDHNv4i32_v8i16 /* 48757 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 48779 /* 48762 */ MCD_OPC_CheckPredicate, 3, 37, 149, 0, // Skip to: 86948 /* 48767 */ MCD_OPC_CheckField, 21, 1, 1, 30, 149, 0, // Skip to: 86948 /* 48774 */ MCD_OPC_Decode, 233, 26, 133, 2, // Opcode: SSHLv8i16 /* 48779 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 48817 /* 48784 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 48787 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 48802 /* 48792 */ MCD_OPC_CheckPredicate, 3, 7, 149, 0, // Skip to: 86948 /* 48797 */ MCD_OPC_Decode, 168, 3, 138, 2, // Opcode: CLSv8i16 /* 48802 */ MCD_OPC_FilterValue, 33, 253, 148, 0, // Skip to: 86948 /* 48807 */ MCD_OPC_CheckPredicate, 3, 248, 148, 0, // Skip to: 86948 /* 48812 */ MCD_OPC_Decode, 172, 26, 147, 2, // Opcode: SQXTNv8i16 /* 48817 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 48839 /* 48822 */ MCD_OPC_CheckPredicate, 3, 233, 148, 0, // Skip to: 86948 /* 48827 */ MCD_OPC_CheckField, 21, 1, 1, 226, 148, 0, // Skip to: 86948 /* 48834 */ MCD_OPC_Decode, 252, 25, 133, 2, // Opcode: SQSHLv8i16 /* 48839 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 48861 /* 48844 */ MCD_OPC_CheckPredicate, 3, 211, 148, 0, // Skip to: 86948 /* 48849 */ MCD_OPC_CheckField, 21, 1, 1, 204, 148, 0, // Skip to: 86948 /* 48856 */ MCD_OPC_Decode, 250, 21, 141, 2, // Opcode: SABALv8i16_v4i32 /* 48861 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 48883 /* 48866 */ MCD_OPC_CheckPredicate, 3, 189, 148, 0, // Skip to: 86948 /* 48871 */ MCD_OPC_CheckField, 21, 1, 1, 182, 148, 0, // Skip to: 86948 /* 48878 */ MCD_OPC_Decode, 203, 26, 133, 2, // Opcode: SRSHLv8i16 /* 48883 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 48905 /* 48888 */ MCD_OPC_CheckPredicate, 3, 167, 148, 0, // Skip to: 86948 /* 48893 */ MCD_OPC_CheckField, 21, 1, 0, 160, 148, 0, // Skip to: 86948 /* 48900 */ MCD_OPC_Decode, 216, 34, 133, 2, // Opcode: UZP2v8i16 /* 48905 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 48927 /* 48910 */ MCD_OPC_CheckPredicate, 3, 145, 148, 0, // Skip to: 86948 /* 48915 */ MCD_OPC_CheckField, 21, 1, 1, 138, 148, 0, // Skip to: 86948 /* 48922 */ MCD_OPC_Decode, 203, 25, 133, 2, // Opcode: SQRSHLv8i16 /* 48927 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 48949 /* 48932 */ MCD_OPC_CheckPredicate, 3, 123, 148, 0, // Skip to: 86948 /* 48937 */ MCD_OPC_CheckField, 21, 1, 1, 116, 148, 0, // Skip to: 86948 /* 48944 */ MCD_OPC_Decode, 214, 29, 141, 2, // Opcode: SUBHNv4i32_v8i16 /* 48949 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 48971 /* 48954 */ MCD_OPC_CheckPredicate, 3, 101, 148, 0, // Skip to: 86948 /* 48959 */ MCD_OPC_CheckField, 21, 1, 1, 94, 148, 0, // Skip to: 86948 /* 48966 */ MCD_OPC_Decode, 204, 23, 133, 2, // Opcode: SMAXv8i16 /* 48971 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 49032 /* 48976 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 48979 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48994 /* 48984 */ MCD_OPC_CheckPredicate, 3, 71, 148, 0, // Skip to: 86948 /* 48989 */ MCD_OPC_Decode, 233, 30, 133, 2, // Opcode: TRN2v8i16 /* 48994 */ MCD_OPC_FilterValue, 1, 61, 148, 0, // Skip to: 86948 /* 48999 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 49002 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49017 /* 49007 */ MCD_OPC_CheckPredicate, 3, 48, 148, 0, // Skip to: 86948 /* 49012 */ MCD_OPC_Decode, 150, 22, 147, 2, // Opcode: SADALPv8i16_v4i32 /* 49017 */ MCD_OPC_FilterValue, 1, 38, 148, 0, // Skip to: 86948 /* 49022 */ MCD_OPC_CheckPredicate, 3, 33, 148, 0, // Skip to: 86948 /* 49027 */ MCD_OPC_Decode, 183, 8, 147, 2, // Opcode: FCVTNv4i32 /* 49032 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 49054 /* 49037 */ MCD_OPC_CheckPredicate, 3, 18, 148, 0, // Skip to: 86948 /* 49042 */ MCD_OPC_CheckField, 21, 1, 1, 11, 148, 0, // Skip to: 86948 /* 49049 */ MCD_OPC_Decode, 234, 23, 133, 2, // Opcode: SMINv8i16 /* 49054 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 49076 /* 49059 */ MCD_OPC_CheckPredicate, 3, 252, 147, 0, // Skip to: 86948 /* 49064 */ MCD_OPC_CheckField, 21, 1, 1, 245, 147, 0, // Skip to: 86948 /* 49071 */ MCD_OPC_Decode, 134, 22, 133, 2, // Opcode: SABDLv8i16_v4i32 /* 49076 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 49098 /* 49081 */ MCD_OPC_CheckPredicate, 3, 230, 147, 0, // Skip to: 86948 /* 49086 */ MCD_OPC_CheckField, 21, 1, 1, 223, 147, 0, // Skip to: 86948 /* 49093 */ MCD_OPC_Decode, 144, 22, 133, 2, // Opcode: SABDv8i16 /* 49098 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 49159 /* 49103 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 49106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49121 /* 49111 */ MCD_OPC_CheckPredicate, 3, 200, 147, 0, // Skip to: 86948 /* 49116 */ MCD_OPC_Decode, 161, 35, 133, 2, // Opcode: ZIP2v8i16 /* 49121 */ MCD_OPC_FilterValue, 1, 190, 147, 0, // Skip to: 86948 /* 49126 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 49129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49144 /* 49134 */ MCD_OPC_CheckPredicate, 3, 177, 147, 0, // Skip to: 86948 /* 49139 */ MCD_OPC_Decode, 162, 24, 138, 2, // Opcode: SQABSv8i16 /* 49144 */ MCD_OPC_FilterValue, 1, 167, 147, 0, // Skip to: 86948 /* 49149 */ MCD_OPC_CheckPredicate, 3, 162, 147, 0, // Skip to: 86948 /* 49154 */ MCD_OPC_Decode, 251, 7, 138, 2, // Opcode: FCVTLv4i32 /* 49159 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 49181 /* 49164 */ MCD_OPC_CheckPredicate, 3, 147, 147, 0, // Skip to: 86948 /* 49169 */ MCD_OPC_CheckField, 21, 1, 1, 140, 147, 0, // Skip to: 86948 /* 49176 */ MCD_OPC_Decode, 128, 22, 141, 2, // Opcode: SABAv8i16 /* 49181 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 49203 /* 49186 */ MCD_OPC_CheckPredicate, 3, 125, 147, 0, // Skip to: 86948 /* 49191 */ MCD_OPC_CheckField, 21, 1, 1, 118, 147, 0, // Skip to: 86948 /* 49198 */ MCD_OPC_Decode, 244, 23, 141, 2, // Opcode: SMLALv8i16_v4i32 /* 49203 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 49225 /* 49208 */ MCD_OPC_CheckPredicate, 3, 103, 147, 0, // Skip to: 86948 /* 49213 */ MCD_OPC_CheckField, 21, 1, 1, 96, 147, 0, // Skip to: 86948 /* 49220 */ MCD_OPC_Decode, 200, 1, 133, 2, // Opcode: ADDv8i16 /* 49225 */ MCD_OPC_FilterValue, 34, 48, 0, 0, // Skip to: 49278 /* 49230 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 49233 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49248 /* 49238 */ MCD_OPC_CheckPredicate, 3, 73, 147, 0, // Skip to: 86948 /* 49243 */ MCD_OPC_Decode, 227, 3, 138, 2, // Opcode: CMGTv8i16rz /* 49248 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49263 /* 49253 */ MCD_OPC_CheckPredicate, 3, 58, 147, 0, // Skip to: 86948 /* 49258 */ MCD_OPC_Decode, 136, 12, 138, 2, // Opcode: FRINTNv2f64 /* 49263 */ MCD_OPC_FilterValue, 57, 48, 147, 0, // Skip to: 86948 /* 49268 */ MCD_OPC_CheckPredicate, 4, 43, 147, 0, // Skip to: 86948 /* 49273 */ MCD_OPC_Decode, 139, 12, 138, 2, // Opcode: FRINTNv8f16 /* 49278 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 49300 /* 49283 */ MCD_OPC_CheckPredicate, 3, 28, 147, 0, // Skip to: 86948 /* 49288 */ MCD_OPC_CheckField, 21, 1, 1, 21, 147, 0, // Skip to: 86948 /* 49295 */ MCD_OPC_Decode, 239, 4, 133, 2, // Opcode: CMTSTv8i16 /* 49300 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 49322 /* 49305 */ MCD_OPC_CheckPredicate, 3, 6, 147, 0, // Skip to: 86948 /* 49310 */ MCD_OPC_CheckField, 21, 1, 1, 255, 146, 0, // Skip to: 86948 /* 49317 */ MCD_OPC_Decode, 216, 24, 141, 2, // Opcode: SQDMLALv8i16_v4i32 /* 49322 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 49344 /* 49327 */ MCD_OPC_CheckPredicate, 3, 240, 146, 0, // Skip to: 86948 /* 49332 */ MCD_OPC_CheckField, 21, 1, 1, 233, 146, 0, // Skip to: 86948 /* 49339 */ MCD_OPC_Decode, 216, 19, 141, 2, // Opcode: MLAv8i16 /* 49344 */ MCD_OPC_FilterValue, 38, 48, 0, 0, // Skip to: 49397 /* 49349 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 49352 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49367 /* 49357 */ MCD_OPC_CheckPredicate, 3, 210, 146, 0, // Skip to: 86948 /* 49362 */ MCD_OPC_Decode, 195, 3, 138, 2, // Opcode: CMEQv8i16rz /* 49367 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49382 /* 49372 */ MCD_OPC_CheckPredicate, 3, 195, 146, 0, // Skip to: 86948 /* 49377 */ MCD_OPC_Decode, 253, 11, 138, 2, // Opcode: FRINTMv2f64 /* 49382 */ MCD_OPC_FilterValue, 57, 185, 146, 0, // Skip to: 86948 /* 49387 */ MCD_OPC_CheckPredicate, 4, 180, 146, 0, // Skip to: 86948 /* 49392 */ MCD_OPC_Decode, 128, 12, 138, 2, // Opcode: FRINTMv8f16 /* 49397 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 49419 /* 49402 */ MCD_OPC_CheckPredicate, 3, 165, 146, 0, // Skip to: 86948 /* 49407 */ MCD_OPC_CheckField, 21, 1, 1, 158, 146, 0, // Skip to: 86948 /* 49414 */ MCD_OPC_Decode, 164, 20, 133, 2, // Opcode: MULv8i16 /* 49419 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 49441 /* 49424 */ MCD_OPC_CheckPredicate, 3, 143, 146, 0, // Skip to: 86948 /* 49429 */ MCD_OPC_CheckField, 21, 1, 1, 136, 146, 0, // Skip to: 86948 /* 49436 */ MCD_OPC_Decode, 254, 23, 141, 2, // Opcode: SMLSLv8i16_v4i32 /* 49441 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 49463 /* 49446 */ MCD_OPC_CheckPredicate, 3, 121, 146, 0, // Skip to: 86948 /* 49451 */ MCD_OPC_CheckField, 21, 1, 1, 114, 146, 0, // Skip to: 86948 /* 49458 */ MCD_OPC_Decode, 181, 23, 133, 2, // Opcode: SMAXPv8i16 /* 49463 */ MCD_OPC_FilterValue, 42, 78, 0, 0, // Skip to: 49546 /* 49468 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 49471 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49486 /* 49476 */ MCD_OPC_CheckPredicate, 3, 91, 146, 0, // Skip to: 86948 /* 49481 */ MCD_OPC_Decode, 132, 4, 138, 2, // Opcode: CMLTv8i16rz /* 49486 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49501 /* 49491 */ MCD_OPC_CheckPredicate, 3, 76, 146, 0, // Skip to: 86948 /* 49496 */ MCD_OPC_Decode, 163, 8, 138, 2, // Opcode: FCVTNSv2f64 /* 49501 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 49516 /* 49506 */ MCD_OPC_CheckPredicate, 3, 61, 146, 0, // Skip to: 86948 /* 49511 */ MCD_OPC_Decode, 190, 23, 152, 2, // Opcode: SMAXVv8i16v /* 49516 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 49531 /* 49521 */ MCD_OPC_CheckPredicate, 3, 46, 146, 0, // Skip to: 86948 /* 49526 */ MCD_OPC_Decode, 220, 23, 152, 2, // Opcode: SMINVv8i16v /* 49531 */ MCD_OPC_FilterValue, 57, 36, 146, 0, // Skip to: 86948 /* 49536 */ MCD_OPC_CheckPredicate, 4, 31, 146, 0, // Skip to: 86948 /* 49541 */ MCD_OPC_Decode, 166, 8, 138, 2, // Opcode: FCVTNSv8f16 /* 49546 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 49568 /* 49551 */ MCD_OPC_CheckPredicate, 3, 16, 146, 0, // Skip to: 86948 /* 49556 */ MCD_OPC_CheckField, 21, 1, 1, 9, 146, 0, // Skip to: 86948 /* 49563 */ MCD_OPC_Decode, 211, 23, 133, 2, // Opcode: SMINPv8i16 /* 49568 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 49590 /* 49573 */ MCD_OPC_CheckPredicate, 3, 250, 145, 0, // Skip to: 86948 /* 49578 */ MCD_OPC_CheckField, 21, 1, 1, 243, 145, 0, // Skip to: 86948 /* 49585 */ MCD_OPC_Decode, 228, 24, 141, 2, // Opcode: SQDMLSLv8i16_v4i32 /* 49590 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 49612 /* 49595 */ MCD_OPC_CheckPredicate, 3, 228, 145, 0, // Skip to: 86948 /* 49600 */ MCD_OPC_CheckField, 21, 1, 1, 221, 145, 0, // Skip to: 86948 /* 49607 */ MCD_OPC_Decode, 239, 24, 133, 2, // Opcode: SQDMULHv8i16 /* 49612 */ MCD_OPC_FilterValue, 46, 63, 0, 0, // Skip to: 49680 /* 49617 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 49620 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49635 /* 49625 */ MCD_OPC_CheckPredicate, 3, 198, 145, 0, // Skip to: 86948 /* 49630 */ MCD_OPC_Decode, 136, 1, 138, 2, // Opcode: ABSv8i16 /* 49635 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49650 /* 49640 */ MCD_OPC_CheckPredicate, 3, 183, 145, 0, // Skip to: 86948 /* 49645 */ MCD_OPC_Decode, 135, 8, 138, 2, // Opcode: FCVTMSv2f64 /* 49650 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 49665 /* 49655 */ MCD_OPC_CheckPredicate, 3, 168, 145, 0, // Skip to: 86948 /* 49660 */ MCD_OPC_Decode, 170, 1, 152, 2, // Opcode: ADDVv8i16v /* 49665 */ MCD_OPC_FilterValue, 57, 158, 145, 0, // Skip to: 86948 /* 49670 */ MCD_OPC_CheckPredicate, 4, 153, 145, 0, // Skip to: 86948 /* 49675 */ MCD_OPC_Decode, 138, 8, 138, 2, // Opcode: FCVTMSv8f16 /* 49680 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 49702 /* 49685 */ MCD_OPC_CheckPredicate, 3, 138, 145, 0, // Skip to: 86948 /* 49690 */ MCD_OPC_CheckField, 21, 1, 1, 131, 145, 0, // Skip to: 86948 /* 49697 */ MCD_OPC_Decode, 155, 1, 133, 2, // Opcode: ADDPv8i16 /* 49702 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 49724 /* 49707 */ MCD_OPC_CheckPredicate, 3, 116, 145, 0, // Skip to: 86948 /* 49712 */ MCD_OPC_CheckField, 21, 1, 1, 109, 145, 0, // Skip to: 86948 /* 49719 */ MCD_OPC_Decode, 147, 24, 133, 2, // Opcode: SMULLv8i16_v4i32 /* 49724 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 49746 /* 49729 */ MCD_OPC_CheckPredicate, 3, 94, 145, 0, // Skip to: 86948 /* 49734 */ MCD_OPC_CheckField, 21, 1, 1, 87, 145, 0, // Skip to: 86948 /* 49741 */ MCD_OPC_Decode, 219, 9, 133, 2, // Opcode: FMAXNMv2f64 /* 49746 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 49784 /* 49751 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 49754 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49769 /* 49759 */ MCD_OPC_CheckPredicate, 3, 64, 145, 0, // Skip to: 86948 /* 49764 */ MCD_OPC_Decode, 227, 7, 138, 2, // Opcode: FCVTASv2f64 /* 49769 */ MCD_OPC_FilterValue, 57, 54, 145, 0, // Skip to: 86948 /* 49774 */ MCD_OPC_CheckPredicate, 4, 49, 145, 0, // Skip to: 86948 /* 49779 */ MCD_OPC_Decode, 230, 7, 138, 2, // Opcode: FCVTASv8f16 /* 49784 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 49806 /* 49789 */ MCD_OPC_CheckPredicate, 3, 34, 145, 0, // Skip to: 86948 /* 49794 */ MCD_OPC_CheckField, 21, 1, 1, 27, 145, 0, // Skip to: 86948 /* 49801 */ MCD_OPC_Decode, 187, 10, 141, 2, // Opcode: FMLAv2f64 /* 49806 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 49828 /* 49811 */ MCD_OPC_CheckPredicate, 3, 12, 145, 0, // Skip to: 86948 /* 49816 */ MCD_OPC_CheckField, 21, 1, 1, 5, 145, 0, // Skip to: 86948 /* 49823 */ MCD_OPC_Decode, 252, 24, 133, 2, // Opcode: SQDMULLv8i16_v4i32 /* 49828 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 49850 /* 49833 */ MCD_OPC_CheckPredicate, 3, 246, 144, 0, // Skip to: 86948 /* 49838 */ MCD_OPC_CheckField, 21, 1, 1, 239, 144, 0, // Skip to: 86948 /* 49845 */ MCD_OPC_Decode, 199, 6, 133, 2, // Opcode: FADDv2f64 /* 49850 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 49888 /* 49855 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 49858 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49873 /* 49863 */ MCD_OPC_CheckPredicate, 3, 216, 144, 0, // Skip to: 86948 /* 49868 */ MCD_OPC_Decode, 210, 22, 138, 2, // Opcode: SCVTFv2f64 /* 49873 */ MCD_OPC_FilterValue, 57, 206, 144, 0, // Skip to: 86948 /* 49878 */ MCD_OPC_CheckPredicate, 4, 201, 144, 0, // Skip to: 86948 /* 49883 */ MCD_OPC_Decode, 217, 22, 138, 2, // Opcode: SCVTFv8f16 /* 49888 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 49910 /* 49893 */ MCD_OPC_CheckPredicate, 3, 186, 144, 0, // Skip to: 86948 /* 49898 */ MCD_OPC_CheckField, 21, 1, 1, 179, 144, 0, // Skip to: 86948 /* 49905 */ MCD_OPC_Decode, 130, 11, 133, 2, // Opcode: FMULXv2f64 /* 49910 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 49932 /* 49915 */ MCD_OPC_CheckPredicate, 3, 164, 144, 0, // Skip to: 86948 /* 49920 */ MCD_OPC_CheckField, 21, 1, 1, 157, 144, 0, // Skip to: 86948 /* 49927 */ MCD_OPC_Decode, 230, 6, 133, 2, // Opcode: FCMEQv2f64 /* 49932 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 49954 /* 49937 */ MCD_OPC_CheckPredicate, 3, 142, 144, 0, // Skip to: 86948 /* 49942 */ MCD_OPC_CheckField, 21, 1, 1, 135, 144, 0, // Skip to: 86948 /* 49949 */ MCD_OPC_Decode, 245, 9, 133, 2, // Opcode: FMAXv2f64 /* 49954 */ MCD_OPC_FilterValue, 63, 125, 144, 0, // Skip to: 86948 /* 49959 */ MCD_OPC_CheckPredicate, 3, 120, 144, 0, // Skip to: 86948 /* 49964 */ MCD_OPC_CheckField, 21, 1, 1, 113, 144, 0, // Skip to: 86948 /* 49971 */ MCD_OPC_Decode, 214, 11, 133, 2, // Opcode: FRECPSv2f64 /* 49976 */ MCD_OPC_FilterValue, 3, 134, 6, 0, // Skip to: 51651 /* 49981 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 49984 */ MCD_OPC_FilterValue, 0, 205, 0, 0, // Skip to: 50194 /* 49989 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 49992 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50014 /* 49997 */ MCD_OPC_CheckPredicate, 3, 82, 144, 0, // Skip to: 86948 /* 50002 */ MCD_OPC_CheckField, 21, 1, 1, 75, 144, 0, // Skip to: 86948 /* 50009 */ MCD_OPC_Decode, 157, 31, 133, 2, // Opcode: UADDLv8i16_v4i32 /* 50014 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50052 /* 50019 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50037 /* 50027 */ MCD_OPC_CheckPredicate, 4, 52, 144, 0, // Skip to: 86948 /* 50032 */ MCD_OPC_Decode, 204, 9, 133, 2, // Opcode: FMAXNMPv8f16 /* 50037 */ MCD_OPC_FilterValue, 1, 42, 144, 0, // Skip to: 86948 /* 50042 */ MCD_OPC_CheckPredicate, 3, 37, 144, 0, // Skip to: 86948 /* 50047 */ MCD_OPC_Decode, 224, 31, 133, 2, // Opcode: UHADDv8i16 /* 50052 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 50074 /* 50057 */ MCD_OPC_CheckPredicate, 3, 22, 144, 0, // Skip to: 86948 /* 50062 */ MCD_OPC_CheckField, 16, 6, 32, 15, 144, 0, // Skip to: 86948 /* 50069 */ MCD_OPC_Decode, 207, 21, 138, 2, // Opcode: REV32v8i16 /* 50074 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50096 /* 50079 */ MCD_OPC_CheckPredicate, 3, 0, 144, 0, // Skip to: 86948 /* 50084 */ MCD_OPC_CheckField, 21, 1, 1, 249, 143, 0, // Skip to: 86948 /* 50091 */ MCD_OPC_Decode, 220, 32, 133, 2, // Opcode: UQADDv8i16 /* 50096 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50118 /* 50101 */ MCD_OPC_CheckPredicate, 3, 234, 143, 0, // Skip to: 86948 /* 50106 */ MCD_OPC_CheckField, 21, 1, 1, 227, 143, 0, // Skip to: 86948 /* 50113 */ MCD_OPC_Decode, 167, 31, 133, 2, // Opcode: UADDWv8i16_v4i32 /* 50118 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 50156 /* 50123 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50126 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50141 /* 50131 */ MCD_OPC_CheckPredicate, 4, 204, 143, 0, // Skip to: 86948 /* 50136 */ MCD_OPC_Decode, 184, 6, 133, 2, // Opcode: FADDPv8f16 /* 50141 */ MCD_OPC_FilterValue, 1, 194, 143, 0, // Skip to: 86948 /* 50146 */ MCD_OPC_CheckPredicate, 3, 189, 143, 0, // Skip to: 86948 /* 50151 */ MCD_OPC_Decode, 223, 33, 133, 2, // Opcode: URHADDv8i16 /* 50156 */ MCD_OPC_FilterValue, 7, 179, 143, 0, // Skip to: 86948 /* 50161 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50164 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50179 /* 50169 */ MCD_OPC_CheckPredicate, 4, 166, 143, 0, // Skip to: 86948 /* 50174 */ MCD_OPC_Decode, 162, 11, 133, 2, // Opcode: FMULv8f16 /* 50179 */ MCD_OPC_FilterValue, 1, 156, 143, 0, // Skip to: 86948 /* 50184 */ MCD_OPC_CheckPredicate, 3, 151, 143, 0, // Skip to: 86948 /* 50189 */ MCD_OPC_Decode, 221, 2, 141, 2, // Opcode: BSLv16i8 /* 50194 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 50489 /* 50199 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 50202 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50224 /* 50207 */ MCD_OPC_CheckPredicate, 3, 128, 143, 0, // Skip to: 86948 /* 50212 */ MCD_OPC_CheckField, 21, 1, 1, 121, 143, 0, // Skip to: 86948 /* 50219 */ MCD_OPC_Decode, 168, 34, 133, 2, // Opcode: USUBLv8i16_v4i32 /* 50224 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50262 /* 50229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50232 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50247 /* 50237 */ MCD_OPC_CheckPredicate, 4, 98, 143, 0, // Skip to: 86948 /* 50242 */ MCD_OPC_Decode, 131, 7, 133, 2, // Opcode: FCMGEv8f16 /* 50247 */ MCD_OPC_FilterValue, 1, 88, 143, 0, // Skip to: 86948 /* 50252 */ MCD_OPC_CheckPredicate, 3, 83, 143, 0, // Skip to: 86948 /* 50257 */ MCD_OPC_Decode, 230, 31, 133, 2, // Opcode: UHSUBv8i16 /* 50262 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50300 /* 50267 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 50270 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50285 /* 50275 */ MCD_OPC_CheckPredicate, 3, 60, 143, 0, // Skip to: 86948 /* 50280 */ MCD_OPC_Decode, 146, 31, 138, 2, // Opcode: UADDLPv8i16_v4i32 /* 50285 */ MCD_OPC_FilterValue, 33, 50, 143, 0, // Skip to: 86948 /* 50290 */ MCD_OPC_CheckPredicate, 3, 45, 143, 0, // Skip to: 86948 /* 50295 */ MCD_OPC_Decode, 181, 26, 147, 2, // Opcode: SQXTUNv8i16 /* 50300 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 50338 /* 50305 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50308 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50323 /* 50313 */ MCD_OPC_CheckPredicate, 4, 22, 143, 0, // Skip to: 86948 /* 50318 */ MCD_OPC_Decode, 160, 6, 133, 2, // Opcode: FACGEv8f16 /* 50323 */ MCD_OPC_FilterValue, 1, 12, 143, 0, // Skip to: 86948 /* 50328 */ MCD_OPC_CheckPredicate, 3, 7, 143, 0, // Skip to: 86948 /* 50333 */ MCD_OPC_Decode, 206, 33, 133, 2, // Opcode: UQSUBv8i16 /* 50338 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50360 /* 50343 */ MCD_OPC_CheckPredicate, 3, 248, 142, 0, // Skip to: 86948 /* 50348 */ MCD_OPC_CheckField, 21, 1, 1, 241, 142, 0, // Skip to: 86948 /* 50355 */ MCD_OPC_Decode, 174, 34, 133, 2, // Opcode: USUBWv8i16_v4i32 /* 50360 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 50398 /* 50365 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50368 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50383 /* 50373 */ MCD_OPC_CheckPredicate, 4, 218, 142, 0, // Skip to: 86948 /* 50378 */ MCD_OPC_Decode, 230, 9, 133, 2, // Opcode: FMAXPv8f16 /* 50383 */ MCD_OPC_FilterValue, 1, 208, 142, 0, // Skip to: 86948 /* 50388 */ MCD_OPC_CheckPredicate, 3, 203, 142, 0, // Skip to: 86948 /* 50393 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: CMHIv8i16 /* 50398 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 50451 /* 50403 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 50406 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50421 /* 50411 */ MCD_OPC_CheckPredicate, 3, 180, 142, 0, // Skip to: 86948 /* 50416 */ MCD_OPC_Decode, 154, 34, 147, 2, // Opcode: USQADDv8i16 /* 50421 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 50436 /* 50426 */ MCD_OPC_CheckPredicate, 3, 165, 142, 0, // Skip to: 86948 /* 50431 */ MCD_OPC_Decode, 137, 23, 138, 2, // Opcode: SHLLv8i16 /* 50436 */ MCD_OPC_FilterValue, 48, 155, 142, 0, // Skip to: 86948 /* 50441 */ MCD_OPC_CheckPredicate, 3, 150, 142, 0, // Skip to: 86948 /* 50446 */ MCD_OPC_Decode, 151, 31, 160, 2, // Opcode: UADDLVv8i16v /* 50451 */ MCD_OPC_FilterValue, 7, 140, 142, 0, // Skip to: 86948 /* 50456 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50459 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50474 /* 50464 */ MCD_OPC_CheckPredicate, 4, 127, 142, 0, // Skip to: 86948 /* 50469 */ MCD_OPC_Decode, 179, 9, 133, 2, // Opcode: FDIVv8f16 /* 50474 */ MCD_OPC_FilterValue, 1, 117, 142, 0, // Skip to: 86948 /* 50479 */ MCD_OPC_CheckPredicate, 3, 112, 142, 0, // Skip to: 86948 /* 50484 */ MCD_OPC_Decode, 244, 3, 133, 2, // Opcode: CMHSv8i16 /* 50489 */ MCD_OPC_FilterValue, 2, 195, 0, 0, // Skip to: 50689 /* 50494 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 50497 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50519 /* 50502 */ MCD_OPC_CheckPredicate, 3, 89, 142, 0, // Skip to: 86948 /* 50507 */ MCD_OPC_CheckField, 21, 1, 1, 82, 142, 0, // Skip to: 86948 /* 50514 */ MCD_OPC_Decode, 180, 21, 141, 2, // Opcode: RADDHNv4i32_v8i16 /* 50519 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 50541 /* 50524 */ MCD_OPC_CheckPredicate, 3, 67, 142, 0, // Skip to: 86948 /* 50529 */ MCD_OPC_CheckField, 21, 1, 1, 60, 142, 0, // Skip to: 86948 /* 50536 */ MCD_OPC_Decode, 135, 34, 133, 2, // Opcode: USHLv8i16 /* 50541 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50579 /* 50546 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 50549 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50564 /* 50554 */ MCD_OPC_CheckPredicate, 3, 37, 142, 0, // Skip to: 86948 /* 50559 */ MCD_OPC_Decode, 180, 3, 138, 2, // Opcode: CLZv8i16 /* 50564 */ MCD_OPC_FilterValue, 33, 27, 142, 0, // Skip to: 86948 /* 50569 */ MCD_OPC_CheckPredicate, 3, 22, 142, 0, // Skip to: 86948 /* 50574 */ MCD_OPC_Decode, 215, 33, 147, 2, // Opcode: UQXTNv8i16 /* 50579 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50601 /* 50584 */ MCD_OPC_CheckPredicate, 3, 7, 142, 0, // Skip to: 86948 /* 50589 */ MCD_OPC_CheckField, 21, 1, 1, 0, 142, 0, // Skip to: 86948 /* 50596 */ MCD_OPC_Decode, 176, 33, 133, 2, // Opcode: UQSHLv8i16 /* 50601 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50623 /* 50606 */ MCD_OPC_CheckPredicate, 3, 241, 141, 0, // Skip to: 86948 /* 50611 */ MCD_OPC_CheckField, 21, 1, 1, 234, 141, 0, // Skip to: 86948 /* 50618 */ MCD_OPC_Decode, 240, 30, 141, 2, // Opcode: UABALv8i16_v4i32 /* 50623 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 50645 /* 50628 */ MCD_OPC_CheckPredicate, 3, 219, 141, 0, // Skip to: 86948 /* 50633 */ MCD_OPC_CheckField, 21, 1, 1, 212, 141, 0, // Skip to: 86948 /* 50640 */ MCD_OPC_Decode, 231, 33, 133, 2, // Opcode: URSHLv8i16 /* 50645 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 50667 /* 50650 */ MCD_OPC_CheckPredicate, 3, 197, 141, 0, // Skip to: 86948 /* 50655 */ MCD_OPC_CheckField, 16, 6, 32, 190, 141, 0, // Skip to: 86948 /* 50662 */ MCD_OPC_Decode, 190, 21, 138, 2, // Opcode: RBITv16i8 /* 50667 */ MCD_OPC_FilterValue, 7, 180, 141, 0, // Skip to: 86948 /* 50672 */ MCD_OPC_CheckPredicate, 3, 175, 141, 0, // Skip to: 86948 /* 50677 */ MCD_OPC_CheckField, 21, 1, 1, 168, 141, 0, // Skip to: 86948 /* 50684 */ MCD_OPC_Decode, 147, 33, 133, 2, // Opcode: UQRSHLv8i16 /* 50689 */ MCD_OPC_FilterValue, 3, 195, 0, 0, // Skip to: 50889 /* 50694 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 50697 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50719 /* 50702 */ MCD_OPC_CheckPredicate, 3, 145, 141, 0, // Skip to: 86948 /* 50707 */ MCD_OPC_CheckField, 21, 1, 1, 138, 141, 0, // Skip to: 86948 /* 50714 */ MCD_OPC_Decode, 243, 21, 141, 2, // Opcode: RSUBHNv4i32_v8i16 /* 50719 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 50741 /* 50724 */ MCD_OPC_CheckPredicate, 3, 123, 141, 0, // Skip to: 86948 /* 50729 */ MCD_OPC_CheckField, 21, 1, 1, 116, 141, 0, // Skip to: 86948 /* 50736 */ MCD_OPC_Decode, 132, 32, 133, 2, // Opcode: UMAXv8i16 /* 50741 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50779 /* 50746 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 50749 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50764 /* 50754 */ MCD_OPC_CheckPredicate, 3, 93, 141, 0, // Skip to: 86948 /* 50759 */ MCD_OPC_Decode, 140, 31, 147, 2, // Opcode: UADALPv8i16_v4i32 /* 50764 */ MCD_OPC_FilterValue, 33, 83, 141, 0, // Skip to: 86948 /* 50769 */ MCD_OPC_CheckPredicate, 3, 78, 141, 0, // Skip to: 86948 /* 50774 */ MCD_OPC_Decode, 217, 8, 147, 2, // Opcode: FCVTXNv4f32 /* 50779 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50801 /* 50784 */ MCD_OPC_CheckPredicate, 3, 63, 141, 0, // Skip to: 86948 /* 50789 */ MCD_OPC_CheckField, 21, 1, 1, 56, 141, 0, // Skip to: 86948 /* 50796 */ MCD_OPC_Decode, 161, 32, 133, 2, // Opcode: UMINv8i16 /* 50801 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50823 /* 50806 */ MCD_OPC_CheckPredicate, 3, 41, 141, 0, // Skip to: 86948 /* 50811 */ MCD_OPC_CheckField, 21, 1, 1, 34, 141, 0, // Skip to: 86948 /* 50818 */ MCD_OPC_Decode, 252, 30, 133, 2, // Opcode: UABDLv8i16_v4i32 /* 50823 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 50845 /* 50828 */ MCD_OPC_CheckPredicate, 3, 19, 141, 0, // Skip to: 86948 /* 50833 */ MCD_OPC_CheckField, 21, 1, 1, 12, 141, 0, // Skip to: 86948 /* 50840 */ MCD_OPC_Decode, 134, 31, 133, 2, // Opcode: UABDv8i16 /* 50845 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 50867 /* 50850 */ MCD_OPC_CheckPredicate, 3, 253, 140, 0, // Skip to: 86948 /* 50855 */ MCD_OPC_CheckField, 16, 6, 32, 246, 140, 0, // Skip to: 86948 /* 50862 */ MCD_OPC_Decode, 156, 25, 138, 2, // Opcode: SQNEGv8i16 /* 50867 */ MCD_OPC_FilterValue, 7, 236, 140, 0, // Skip to: 86948 /* 50872 */ MCD_OPC_CheckPredicate, 3, 231, 140, 0, // Skip to: 86948 /* 50877 */ MCD_OPC_CheckField, 21, 1, 1, 224, 140, 0, // Skip to: 86948 /* 50884 */ MCD_OPC_Decode, 246, 30, 141, 2, // Opcode: UABAv8i16 /* 50889 */ MCD_OPC_FilterValue, 4, 229, 0, 0, // Skip to: 51123 /* 50894 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 50897 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50919 /* 50902 */ MCD_OPC_CheckPredicate, 3, 201, 140, 0, // Skip to: 86948 /* 50907 */ MCD_OPC_CheckField, 21, 1, 1, 194, 140, 0, // Skip to: 86948 /* 50914 */ MCD_OPC_Decode, 171, 32, 141, 2, // Opcode: UMLALv8i16_v4i32 /* 50919 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50957 /* 50924 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 50927 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50942 /* 50932 */ MCD_OPC_CheckPredicate, 7, 171, 140, 0, // Skip to: 86948 /* 50937 */ MCD_OPC_Decode, 168, 25, 141, 2, // Opcode: SQRDMLAHv8i16 /* 50942 */ MCD_OPC_FilterValue, 1, 161, 140, 0, // Skip to: 86948 /* 50947 */ MCD_OPC_CheckPredicate, 3, 156, 140, 0, // Skip to: 86948 /* 50952 */ MCD_OPC_Decode, 133, 30, 133, 2, // Opcode: SUBv8i16 /* 50957 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 51010 /* 50962 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 50965 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50980 /* 50970 */ MCD_OPC_CheckPredicate, 3, 133, 140, 0, // Skip to: 86948 /* 50975 */ MCD_OPC_Decode, 211, 3, 138, 2, // Opcode: CMGEv8i16rz /* 50980 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 50995 /* 50985 */ MCD_OPC_CheckPredicate, 3, 118, 140, 0, // Skip to: 86948 /* 50990 */ MCD_OPC_Decode, 231, 11, 138, 2, // Opcode: FRINTAv2f64 /* 50995 */ MCD_OPC_FilterValue, 57, 108, 140, 0, // Skip to: 86948 /* 51000 */ MCD_OPC_CheckPredicate, 4, 103, 140, 0, // Skip to: 86948 /* 51005 */ MCD_OPC_Decode, 234, 11, 138, 2, // Opcode: FRINTAv8f16 /* 51010 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 51048 /* 51015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51018 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51033 /* 51023 */ MCD_OPC_CheckPredicate, 7, 80, 140, 0, // Skip to: 86948 /* 51028 */ MCD_OPC_Decode, 180, 25, 141, 2, // Opcode: SQRDMLSHv8i16 /* 51033 */ MCD_OPC_FilterValue, 1, 70, 140, 0, // Skip to: 86948 /* 51038 */ MCD_OPC_CheckPredicate, 3, 65, 140, 0, // Skip to: 86948 /* 51043 */ MCD_OPC_Decode, 194, 3, 133, 2, // Opcode: CMEQv8i16 /* 51048 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 51070 /* 51053 */ MCD_OPC_CheckPredicate, 3, 50, 140, 0, // Skip to: 86948 /* 51058 */ MCD_OPC_CheckField, 21, 1, 1, 43, 140, 0, // Skip to: 86948 /* 51065 */ MCD_OPC_Decode, 230, 19, 141, 2, // Opcode: MLSv8i16 /* 51070 */ MCD_OPC_FilterValue, 6, 33, 140, 0, // Skip to: 86948 /* 51075 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 51078 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 51093 /* 51083 */ MCD_OPC_CheckPredicate, 3, 20, 140, 0, // Skip to: 86948 /* 51088 */ MCD_OPC_Decode, 252, 3, 138, 2, // Opcode: CMLEv8i16rz /* 51093 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51108 /* 51098 */ MCD_OPC_CheckPredicate, 3, 5, 140, 0, // Skip to: 86948 /* 51103 */ MCD_OPC_Decode, 158, 12, 138, 2, // Opcode: FRINTXv2f64 /* 51108 */ MCD_OPC_FilterValue, 57, 251, 139, 0, // Skip to: 86948 /* 51113 */ MCD_OPC_CheckPredicate, 4, 246, 139, 0, // Skip to: 86948 /* 51118 */ MCD_OPC_Decode, 161, 12, 138, 2, // Opcode: FRINTXv8f16 /* 51123 */ MCD_OPC_FilterValue, 5, 212, 0, 0, // Skip to: 51340 /* 51128 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 51131 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51153 /* 51136 */ MCD_OPC_CheckPredicate, 3, 223, 139, 0, // Skip to: 86948 /* 51141 */ MCD_OPC_CheckField, 21, 1, 1, 216, 139, 0, // Skip to: 86948 /* 51148 */ MCD_OPC_Decode, 181, 32, 141, 2, // Opcode: UMLSLv8i16_v4i32 /* 51153 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 51175 /* 51158 */ MCD_OPC_CheckPredicate, 3, 201, 139, 0, // Skip to: 86948 /* 51163 */ MCD_OPC_CheckField, 21, 1, 1, 194, 139, 0, // Skip to: 86948 /* 51170 */ MCD_OPC_Decode, 237, 31, 133, 2, // Opcode: UMAXPv8i16 /* 51175 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 51243 /* 51180 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 51183 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51198 /* 51188 */ MCD_OPC_CheckPredicate, 3, 171, 139, 0, // Skip to: 86948 /* 51193 */ MCD_OPC_Decode, 177, 8, 138, 2, // Opcode: FCVTNUv2f64 /* 51198 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 51213 /* 51203 */ MCD_OPC_CheckPredicate, 3, 156, 139, 0, // Skip to: 86948 /* 51208 */ MCD_OPC_Decode, 246, 31, 152, 2, // Opcode: UMAXVv8i16v /* 51213 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 51228 /* 51218 */ MCD_OPC_CheckPredicate, 3, 141, 139, 0, // Skip to: 86948 /* 51223 */ MCD_OPC_Decode, 147, 32, 152, 2, // Opcode: UMINVv8i16v /* 51228 */ MCD_OPC_FilterValue, 57, 131, 139, 0, // Skip to: 86948 /* 51233 */ MCD_OPC_CheckPredicate, 4, 126, 139, 0, // Skip to: 86948 /* 51238 */ MCD_OPC_Decode, 180, 8, 138, 2, // Opcode: FCVTNUv8f16 /* 51243 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 51265 /* 51248 */ MCD_OPC_CheckPredicate, 3, 111, 139, 0, // Skip to: 86948 /* 51253 */ MCD_OPC_CheckField, 21, 1, 1, 104, 139, 0, // Skip to: 86948 /* 51260 */ MCD_OPC_Decode, 138, 32, 133, 2, // Opcode: UMINPv8i16 /* 51265 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 51287 /* 51270 */ MCD_OPC_CheckPredicate, 3, 89, 139, 0, // Skip to: 86948 /* 51275 */ MCD_OPC_CheckField, 21, 1, 1, 82, 139, 0, // Skip to: 86948 /* 51282 */ MCD_OPC_Decode, 192, 25, 133, 2, // Opcode: SQRDMULHv8i16 /* 51287 */ MCD_OPC_FilterValue, 6, 72, 139, 0, // Skip to: 86948 /* 51292 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 51295 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 51310 /* 51300 */ MCD_OPC_CheckPredicate, 3, 59, 139, 0, // Skip to: 86948 /* 51305 */ MCD_OPC_Decode, 185, 20, 138, 2, // Opcode: NEGv8i16 /* 51310 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51325 /* 51315 */ MCD_OPC_CheckPredicate, 3, 44, 139, 0, // Skip to: 86948 /* 51320 */ MCD_OPC_Decode, 149, 8, 138, 2, // Opcode: FCVTMUv2f64 /* 51325 */ MCD_OPC_FilterValue, 57, 34, 139, 0, // Skip to: 86948 /* 51330 */ MCD_OPC_CheckPredicate, 4, 29, 139, 0, // Skip to: 86948 /* 51335 */ MCD_OPC_Decode, 152, 8, 138, 2, // Opcode: FCVTMUv8f16 /* 51340 */ MCD_OPC_FilterValue, 6, 185, 0, 0, // Skip to: 51530 /* 51345 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 51348 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 51454 /* 51353 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 51356 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51378 /* 51361 */ MCD_OPC_CheckPredicate, 3, 254, 138, 0, // Skip to: 86948 /* 51366 */ MCD_OPC_CheckField, 21, 1, 1, 247, 138, 0, // Skip to: 86948 /* 51373 */ MCD_OPC_Decode, 201, 32, 133, 2, // Opcode: UMULLv8i16_v4i32 /* 51378 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 51416 /* 51383 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 51386 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51401 /* 51391 */ MCD_OPC_CheckPredicate, 3, 224, 138, 0, // Skip to: 86948 /* 51396 */ MCD_OPC_Decode, 241, 7, 138, 2, // Opcode: FCVTAUv2f64 /* 51401 */ MCD_OPC_FilterValue, 57, 214, 138, 0, // Skip to: 86948 /* 51406 */ MCD_OPC_CheckPredicate, 4, 209, 138, 0, // Skip to: 86948 /* 51411 */ MCD_OPC_Decode, 244, 7, 138, 2, // Opcode: FCVTAUv8f16 /* 51416 */ MCD_OPC_FilterValue, 3, 199, 138, 0, // Skip to: 86948 /* 51421 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 51424 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51439 /* 51429 */ MCD_OPC_CheckPredicate, 3, 186, 138, 0, // Skip to: 86948 /* 51434 */ MCD_OPC_Decode, 197, 31, 138, 2, // Opcode: UCVTFv2f64 /* 51439 */ MCD_OPC_FilterValue, 57, 176, 138, 0, // Skip to: 86948 /* 51444 */ MCD_OPC_CheckPredicate, 4, 171, 138, 0, // Skip to: 86948 /* 51449 */ MCD_OPC_Decode, 204, 31, 138, 2, // Opcode: UCVTFv8f16 /* 51454 */ MCD_OPC_FilterValue, 1, 161, 138, 0, // Skip to: 86948 /* 51459 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51477 /* 51467 */ MCD_OPC_CheckPredicate, 8, 148, 138, 0, // Skip to: 86948 /* 51472 */ MCD_OPC_Decode, 166, 7, 169, 2, // Opcode: FCMLAv8f16 /* 51477 */ MCD_OPC_FilterValue, 1, 138, 138, 0, // Skip to: 86948 /* 51482 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 51485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51500 /* 51490 */ MCD_OPC_CheckPredicate, 3, 125, 138, 0, // Skip to: 86948 /* 51495 */ MCD_OPC_Decode, 198, 9, 133, 2, // Opcode: FMAXNMPv2f64 /* 51500 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 51515 /* 51505 */ MCD_OPC_CheckPredicate, 3, 110, 138, 0, // Skip to: 86948 /* 51510 */ MCD_OPC_Decode, 178, 6, 133, 2, // Opcode: FADDPv2f64 /* 51515 */ MCD_OPC_FilterValue, 3, 100, 138, 0, // Skip to: 86948 /* 51520 */ MCD_OPC_CheckPredicate, 3, 95, 138, 0, // Skip to: 86948 /* 51525 */ MCD_OPC_Decode, 155, 11, 133, 2, // Opcode: FMULv2f64 /* 51530 */ MCD_OPC_FilterValue, 7, 85, 138, 0, // Skip to: 86948 /* 51535 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 51538 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 51599 /* 51543 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51546 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51561 /* 51551 */ MCD_OPC_CheckPredicate, 8, 64, 138, 0, // Skip to: 86948 /* 51556 */ MCD_OPC_Decode, 210, 6, 170, 2, // Opcode: FCADDv8f16 /* 51561 */ MCD_OPC_FilterValue, 1, 54, 138, 0, // Skip to: 86948 /* 51566 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 51569 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51584 /* 51574 */ MCD_OPC_CheckPredicate, 3, 41, 138, 0, // Skip to: 86948 /* 51579 */ MCD_OPC_Decode, 252, 6, 133, 2, // Opcode: FCMGEv2f64 /* 51584 */ MCD_OPC_FilterValue, 1, 31, 138, 0, // Skip to: 86948 /* 51589 */ MCD_OPC_CheckPredicate, 3, 26, 138, 0, // Skip to: 86948 /* 51594 */ MCD_OPC_Decode, 224, 9, 133, 2, // Opcode: FMAXPv2f64 /* 51599 */ MCD_OPC_FilterValue, 3, 16, 138, 0, // Skip to: 86948 /* 51604 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 51607 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51629 /* 51612 */ MCD_OPC_CheckPredicate, 3, 3, 138, 0, // Skip to: 86948 /* 51617 */ MCD_OPC_CheckField, 21, 1, 1, 252, 137, 0, // Skip to: 86948 /* 51624 */ MCD_OPC_Decode, 157, 6, 133, 2, // Opcode: FACGEv2f64 /* 51629 */ MCD_OPC_FilterValue, 1, 242, 137, 0, // Skip to: 86948 /* 51634 */ MCD_OPC_CheckPredicate, 3, 237, 137, 0, // Skip to: 86948 /* 51639 */ MCD_OPC_CheckField, 21, 1, 1, 230, 137, 0, // Skip to: 86948 /* 51646 */ MCD_OPC_Decode, 176, 9, 133, 2, // Opcode: FDIVv2f64 /* 51651 */ MCD_OPC_FilterValue, 6, 220, 137, 0, // Skip to: 86948 /* 51656 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 51659 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51681 /* 51664 */ MCD_OPC_CheckPredicate, 9, 207, 137, 0, // Skip to: 86948 /* 51669 */ MCD_OPC_CheckField, 21, 1, 0, 200, 137, 0, // Skip to: 86948 /* 51676 */ MCD_OPC_Decode, 169, 23, 165, 2, // Opcode: SM3SS1 /* 51681 */ MCD_OPC_FilterValue, 1, 190, 137, 0, // Skip to: 86948 /* 51686 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 51689 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 51771 /* 51694 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 51697 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51742 /* 51702 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51720 /* 51710 */ MCD_OPC_CheckPredicate, 9, 161, 137, 0, // Skip to: 86948 /* 51715 */ MCD_OPC_Decode, 170, 23, 171, 2, // Opcode: SM3TT1A /* 51720 */ MCD_OPC_FilterValue, 1, 151, 137, 0, // Skip to: 86948 /* 51725 */ MCD_OPC_CheckPredicate, 6, 146, 137, 0, // Skip to: 86948 /* 51730 */ MCD_OPC_CheckField, 12, 2, 0, 139, 137, 0, // Skip to: 86948 /* 51737 */ MCD_OPC_Decode, 251, 22, 141, 2, // Opcode: SHA512H /* 51742 */ MCD_OPC_FilterValue, 1, 129, 137, 0, // Skip to: 86948 /* 51747 */ MCD_OPC_CheckPredicate, 9, 124, 137, 0, // Skip to: 86948 /* 51752 */ MCD_OPC_CheckField, 21, 1, 1, 117, 137, 0, // Skip to: 86948 /* 51759 */ MCD_OPC_CheckField, 12, 2, 0, 110, 137, 0, // Skip to: 86948 /* 51766 */ MCD_OPC_Decode, 167, 23, 141, 2, // Opcode: SM3PARTW1 /* 51771 */ MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 51853 /* 51776 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 51779 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51824 /* 51784 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51787 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51802 /* 51792 */ MCD_OPC_CheckPredicate, 9, 79, 137, 0, // Skip to: 86948 /* 51797 */ MCD_OPC_Decode, 171, 23, 171, 2, // Opcode: SM3TT1B /* 51802 */ MCD_OPC_FilterValue, 1, 69, 137, 0, // Skip to: 86948 /* 51807 */ MCD_OPC_CheckPredicate, 6, 64, 137, 0, // Skip to: 86948 /* 51812 */ MCD_OPC_CheckField, 12, 2, 0, 57, 137, 0, // Skip to: 86948 /* 51819 */ MCD_OPC_Decode, 252, 22, 141, 2, // Opcode: SHA512H2 /* 51824 */ MCD_OPC_FilterValue, 1, 47, 137, 0, // Skip to: 86948 /* 51829 */ MCD_OPC_CheckPredicate, 9, 42, 137, 0, // Skip to: 86948 /* 51834 */ MCD_OPC_CheckField, 21, 1, 1, 35, 137, 0, // Skip to: 86948 /* 51841 */ MCD_OPC_CheckField, 12, 2, 0, 28, 137, 0, // Skip to: 86948 /* 51848 */ MCD_OPC_Decode, 168, 23, 141, 2, // Opcode: SM3PARTW2 /* 51853 */ MCD_OPC_FilterValue, 2, 77, 0, 0, // Skip to: 51935 /* 51858 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 51861 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51906 /* 51866 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51869 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51884 /* 51874 */ MCD_OPC_CheckPredicate, 9, 253, 136, 0, // Skip to: 86948 /* 51879 */ MCD_OPC_Decode, 172, 23, 171, 2, // Opcode: SM3TT2A /* 51884 */ MCD_OPC_FilterValue, 1, 243, 136, 0, // Skip to: 86948 /* 51889 */ MCD_OPC_CheckPredicate, 6, 238, 136, 0, // Skip to: 86948 /* 51894 */ MCD_OPC_CheckField, 12, 2, 0, 231, 136, 0, // Skip to: 86948 /* 51901 */ MCD_OPC_Decode, 254, 22, 141, 2, // Opcode: SHA512SU1 /* 51906 */ MCD_OPC_FilterValue, 1, 221, 136, 0, // Skip to: 86948 /* 51911 */ MCD_OPC_CheckPredicate, 9, 216, 136, 0, // Skip to: 86948 /* 51916 */ MCD_OPC_CheckField, 21, 1, 1, 209, 136, 0, // Skip to: 86948 /* 51923 */ MCD_OPC_CheckField, 12, 2, 0, 202, 136, 0, // Skip to: 86948 /* 51930 */ MCD_OPC_Decode, 175, 23, 133, 2, // Opcode: SM4ENCKEY /* 51935 */ MCD_OPC_FilterValue, 3, 192, 136, 0, // Skip to: 86948 /* 51940 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 51943 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51965 /* 51948 */ MCD_OPC_CheckPredicate, 9, 179, 136, 0, // Skip to: 86948 /* 51953 */ MCD_OPC_CheckField, 14, 1, 0, 172, 136, 0, // Skip to: 86948 /* 51960 */ MCD_OPC_Decode, 173, 23, 171, 2, // Opcode: SM3TT2B /* 51965 */ MCD_OPC_FilterValue, 1, 162, 136, 0, // Skip to: 86948 /* 51970 */ MCD_OPC_CheckPredicate, 6, 157, 136, 0, // Skip to: 86948 /* 51975 */ MCD_OPC_CheckField, 12, 3, 0, 150, 136, 0, // Skip to: 86948 /* 51982 */ MCD_OPC_Decode, 183, 21, 133, 2, // Opcode: RAX1 /* 51987 */ MCD_OPC_FilterValue, 10, 249, 23, 0, // Skip to: 58129 /* 51992 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 51995 */ MCD_OPC_FilterValue, 0, 32, 6, 0, // Skip to: 53568 /* 52000 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 52003 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 52025 /* 52008 */ MCD_OPC_CheckPredicate, 3, 119, 136, 0, // Skip to: 86948 /* 52013 */ MCD_OPC_CheckField, 21, 1, 1, 112, 136, 0, // Skip to: 86948 /* 52020 */ MCD_OPC_Decode, 164, 22, 234, 1, // Opcode: SADDLv2i32_v2i64 /* 52025 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 52047 /* 52030 */ MCD_OPC_CheckPredicate, 3, 97, 136, 0, // Skip to: 86948 /* 52035 */ MCD_OPC_CheckField, 21, 1, 1, 90, 136, 0, // Skip to: 86948 /* 52042 */ MCD_OPC_Decode, 128, 23, 238, 1, // Opcode: SHADDv2i32 /* 52047 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 52069 /* 52052 */ MCD_OPC_CheckPredicate, 3, 75, 136, 0, // Skip to: 86948 /* 52057 */ MCD_OPC_CheckField, 16, 6, 32, 68, 136, 0, // Skip to: 86948 /* 52064 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: REV64v2i32 /* 52069 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 52091 /* 52074 */ MCD_OPC_CheckPredicate, 3, 53, 136, 0, // Skip to: 86948 /* 52079 */ MCD_OPC_CheckField, 21, 1, 1, 46, 136, 0, // Skip to: 86948 /* 52086 */ MCD_OPC_Decode, 177, 24, 238, 1, // Opcode: SQADDv2i32 /* 52091 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 52113 /* 52096 */ MCD_OPC_CheckPredicate, 3, 31, 136, 0, // Skip to: 86948 /* 52101 */ MCD_OPC_CheckField, 21, 1, 1, 24, 136, 0, // Skip to: 86948 /* 52108 */ MCD_OPC_Decode, 173, 22, 242, 1, // Opcode: SADDWv2i32_v2i64 /* 52113 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 52135 /* 52118 */ MCD_OPC_CheckPredicate, 3, 9, 136, 0, // Skip to: 86948 /* 52123 */ MCD_OPC_CheckField, 21, 1, 1, 2, 136, 0, // Skip to: 86948 /* 52130 */ MCD_OPC_Decode, 184, 26, 238, 1, // Opcode: SRHADDv2i32 /* 52135 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 52157 /* 52140 */ MCD_OPC_CheckPredicate, 3, 243, 135, 0, // Skip to: 86948 /* 52145 */ MCD_OPC_CheckField, 21, 1, 0, 236, 135, 0, // Skip to: 86948 /* 52152 */ MCD_OPC_Decode, 197, 34, 238, 1, // Opcode: UZP1v2i32 /* 52157 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 52179 /* 52162 */ MCD_OPC_CheckPredicate, 3, 221, 135, 0, // Skip to: 86948 /* 52167 */ MCD_OPC_CheckField, 21, 1, 1, 214, 135, 0, // Skip to: 86948 /* 52174 */ MCD_OPC_Decode, 222, 20, 238, 1, // Opcode: ORRv8i8 /* 52179 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 52201 /* 52184 */ MCD_OPC_CheckPredicate, 3, 199, 135, 0, // Skip to: 86948 /* 52189 */ MCD_OPC_CheckField, 21, 1, 1, 192, 135, 0, // Skip to: 86948 /* 52196 */ MCD_OPC_Decode, 162, 27, 234, 1, // Opcode: SSUBLv2i32_v2i64 /* 52201 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 52223 /* 52206 */ MCD_OPC_CheckPredicate, 3, 177, 135, 0, // Skip to: 86948 /* 52211 */ MCD_OPC_CheckField, 21, 1, 1, 170, 135, 0, // Skip to: 86948 /* 52218 */ MCD_OPC_Decode, 154, 23, 238, 1, // Opcode: SHSUBv2i32 /* 52223 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 52284 /* 52228 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 52231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52246 /* 52236 */ MCD_OPC_CheckPredicate, 3, 147, 135, 0, // Skip to: 86948 /* 52241 */ MCD_OPC_Decode, 214, 30, 238, 1, // Opcode: TRN1v2i32 /* 52246 */ MCD_OPC_FilterValue, 1, 137, 135, 0, // Skip to: 86948 /* 52251 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 52254 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52269 /* 52259 */ MCD_OPC_CheckPredicate, 3, 124, 135, 0, // Skip to: 86948 /* 52264 */ MCD_OPC_Decode, 153, 22, 239, 1, // Opcode: SADDLPv2i32_v1i64 /* 52269 */ MCD_OPC_FilterValue, 1, 114, 135, 0, // Skip to: 86948 /* 52274 */ MCD_OPC_CheckPredicate, 3, 109, 135, 0, // Skip to: 86948 /* 52279 */ MCD_OPC_Decode, 128, 35, 244, 1, // Opcode: XTNv2i32 /* 52284 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 52306 /* 52289 */ MCD_OPC_CheckPredicate, 3, 94, 135, 0, // Skip to: 86948 /* 52294 */ MCD_OPC_CheckField, 21, 1, 1, 87, 135, 0, // Skip to: 86948 /* 52301 */ MCD_OPC_Decode, 159, 26, 238, 1, // Opcode: SQSUBv2i32 /* 52306 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 52328 /* 52311 */ MCD_OPC_CheckPredicate, 3, 72, 135, 0, // Skip to: 86948 /* 52316 */ MCD_OPC_CheckField, 21, 1, 1, 65, 135, 0, // Skip to: 86948 /* 52323 */ MCD_OPC_Decode, 168, 27, 242, 1, // Opcode: SSUBWv2i32_v2i64 /* 52328 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 52350 /* 52333 */ MCD_OPC_CheckPredicate, 3, 50, 135, 0, // Skip to: 86948 /* 52338 */ MCD_OPC_CheckField, 21, 1, 1, 43, 135, 0, // Skip to: 86948 /* 52345 */ MCD_OPC_Decode, 218, 3, 238, 1, // Opcode: CMGTv2i32 /* 52350 */ MCD_OPC_FilterValue, 14, 40, 0, 0, // Skip to: 52395 /* 52355 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 52358 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52373 /* 52363 */ MCD_OPC_CheckPredicate, 3, 20, 135, 0, // Skip to: 86948 /* 52368 */ MCD_OPC_Decode, 142, 35, 238, 1, // Opcode: ZIP1v2i32 /* 52373 */ MCD_OPC_FilterValue, 1, 10, 135, 0, // Skip to: 86948 /* 52378 */ MCD_OPC_CheckPredicate, 3, 5, 135, 0, // Skip to: 86948 /* 52383 */ MCD_OPC_CheckField, 16, 5, 0, 254, 134, 0, // Skip to: 86948 /* 52390 */ MCD_OPC_Decode, 146, 30, 248, 1, // Opcode: SUQADDv2i32 /* 52395 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 52417 /* 52400 */ MCD_OPC_CheckPredicate, 3, 239, 134, 0, // Skip to: 86948 /* 52405 */ MCD_OPC_CheckField, 21, 1, 1, 232, 134, 0, // Skip to: 86948 /* 52412 */ MCD_OPC_Decode, 202, 3, 238, 1, // Opcode: CMGEv2i32 /* 52417 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 52439 /* 52422 */ MCD_OPC_CheckPredicate, 3, 217, 134, 0, // Skip to: 86948 /* 52427 */ MCD_OPC_CheckField, 21, 1, 1, 210, 134, 0, // Skip to: 86948 /* 52434 */ MCD_OPC_Decode, 142, 1, 252, 1, // Opcode: ADDHNv2i64_v2i32 /* 52439 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 52461 /* 52444 */ MCD_OPC_CheckPredicate, 3, 195, 134, 0, // Skip to: 86948 /* 52449 */ MCD_OPC_CheckField, 21, 1, 1, 188, 134, 0, // Skip to: 86948 /* 52456 */ MCD_OPC_Decode, 229, 26, 238, 1, // Opcode: SSHLv2i32 /* 52461 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 52499 /* 52466 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 52469 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 52484 /* 52474 */ MCD_OPC_CheckPredicate, 3, 165, 134, 0, // Skip to: 86948 /* 52479 */ MCD_OPC_Decode, 165, 3, 239, 1, // Opcode: CLSv2i32 /* 52484 */ MCD_OPC_FilterValue, 33, 155, 134, 0, // Skip to: 86948 /* 52489 */ MCD_OPC_CheckPredicate, 3, 150, 134, 0, // Skip to: 86948 /* 52494 */ MCD_OPC_Decode, 169, 26, 244, 1, // Opcode: SQXTNv2i32 /* 52499 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 52521 /* 52504 */ MCD_OPC_CheckPredicate, 3, 135, 134, 0, // Skip to: 86948 /* 52509 */ MCD_OPC_CheckField, 21, 1, 1, 128, 134, 0, // Skip to: 86948 /* 52516 */ MCD_OPC_Decode, 244, 25, 238, 1, // Opcode: SQSHLv2i32 /* 52521 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 52543 /* 52526 */ MCD_OPC_CheckPredicate, 3, 113, 134, 0, // Skip to: 86948 /* 52531 */ MCD_OPC_CheckField, 21, 1, 1, 106, 134, 0, // Skip to: 86948 /* 52538 */ MCD_OPC_Decode, 247, 21, 254, 1, // Opcode: SABALv2i32_v2i64 /* 52543 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 52565 /* 52548 */ MCD_OPC_CheckPredicate, 3, 91, 134, 0, // Skip to: 86948 /* 52553 */ MCD_OPC_CheckField, 21, 1, 1, 84, 134, 0, // Skip to: 86948 /* 52560 */ MCD_OPC_Decode, 199, 26, 238, 1, // Opcode: SRSHLv2i32 /* 52565 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 52587 /* 52570 */ MCD_OPC_CheckPredicate, 3, 69, 134, 0, // Skip to: 86948 /* 52575 */ MCD_OPC_CheckField, 21, 1, 0, 62, 134, 0, // Skip to: 86948 /* 52582 */ MCD_OPC_Decode, 212, 34, 238, 1, // Opcode: UZP2v2i32 /* 52587 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 52609 /* 52592 */ MCD_OPC_CheckPredicate, 3, 47, 134, 0, // Skip to: 86948 /* 52597 */ MCD_OPC_CheckField, 21, 1, 1, 40, 134, 0, // Skip to: 86948 /* 52604 */ MCD_OPC_Decode, 199, 25, 238, 1, // Opcode: SQRSHLv2i32 /* 52609 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 52631 /* 52614 */ MCD_OPC_CheckPredicate, 3, 25, 134, 0, // Skip to: 86948 /* 52619 */ MCD_OPC_CheckField, 21, 1, 1, 18, 134, 0, // Skip to: 86948 /* 52626 */ MCD_OPC_Decode, 211, 29, 252, 1, // Opcode: SUBHNv2i64_v2i32 /* 52631 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 52653 /* 52636 */ MCD_OPC_CheckPredicate, 3, 3, 134, 0, // Skip to: 86948 /* 52641 */ MCD_OPC_CheckField, 21, 1, 1, 252, 133, 0, // Skip to: 86948 /* 52648 */ MCD_OPC_Decode, 201, 23, 238, 1, // Opcode: SMAXv2i32 /* 52653 */ MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 52698 /* 52658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 52661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52676 /* 52666 */ MCD_OPC_CheckPredicate, 3, 229, 133, 0, // Skip to: 86948 /* 52671 */ MCD_OPC_Decode, 229, 30, 238, 1, // Opcode: TRN2v2i32 /* 52676 */ MCD_OPC_FilterValue, 1, 219, 133, 0, // Skip to: 86948 /* 52681 */ MCD_OPC_CheckPredicate, 3, 214, 133, 0, // Skip to: 86948 /* 52686 */ MCD_OPC_CheckField, 16, 5, 0, 207, 133, 0, // Skip to: 86948 /* 52693 */ MCD_OPC_Decode, 147, 22, 248, 1, // Opcode: SADALPv2i32_v1i64 /* 52698 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 52720 /* 52703 */ MCD_OPC_CheckPredicate, 3, 192, 133, 0, // Skip to: 86948 /* 52708 */ MCD_OPC_CheckField, 21, 1, 1, 185, 133, 0, // Skip to: 86948 /* 52715 */ MCD_OPC_Decode, 231, 23, 238, 1, // Opcode: SMINv2i32 /* 52720 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 52742 /* 52725 */ MCD_OPC_CheckPredicate, 3, 170, 133, 0, // Skip to: 86948 /* 52730 */ MCD_OPC_CheckField, 21, 1, 1, 163, 133, 0, // Skip to: 86948 /* 52737 */ MCD_OPC_Decode, 131, 22, 234, 1, // Opcode: SABDLv2i32_v2i64 /* 52742 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 52764 /* 52747 */ MCD_OPC_CheckPredicate, 3, 148, 133, 0, // Skip to: 86948 /* 52752 */ MCD_OPC_CheckField, 21, 1, 1, 141, 133, 0, // Skip to: 86948 /* 52759 */ MCD_OPC_Decode, 141, 22, 238, 1, // Opcode: SABDv2i32 /* 52764 */ MCD_OPC_FilterValue, 30, 40, 0, 0, // Skip to: 52809 /* 52769 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 52772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52787 /* 52777 */ MCD_OPC_CheckPredicate, 3, 118, 133, 0, // Skip to: 86948 /* 52782 */ MCD_OPC_Decode, 157, 35, 238, 1, // Opcode: ZIP2v2i32 /* 52787 */ MCD_OPC_FilterValue, 1, 108, 133, 0, // Skip to: 86948 /* 52792 */ MCD_OPC_CheckPredicate, 3, 103, 133, 0, // Skip to: 86948 /* 52797 */ MCD_OPC_CheckField, 16, 5, 0, 96, 133, 0, // Skip to: 86948 /* 52804 */ MCD_OPC_Decode, 158, 24, 239, 1, // Opcode: SQABSv2i32 /* 52809 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 52831 /* 52814 */ MCD_OPC_CheckPredicate, 3, 81, 133, 0, // Skip to: 86948 /* 52819 */ MCD_OPC_CheckField, 21, 1, 1, 74, 133, 0, // Skip to: 86948 /* 52826 */ MCD_OPC_Decode, 253, 21, 130, 2, // Opcode: SABAv2i32 /* 52831 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 52853 /* 52836 */ MCD_OPC_CheckPredicate, 3, 59, 133, 0, // Skip to: 86948 /* 52841 */ MCD_OPC_CheckField, 21, 1, 1, 52, 133, 0, // Skip to: 86948 /* 52848 */ MCD_OPC_Decode, 238, 23, 254, 1, // Opcode: SMLALv2i32_v2i64 /* 52853 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 52875 /* 52858 */ MCD_OPC_CheckPredicate, 3, 37, 133, 0, // Skip to: 86948 /* 52863 */ MCD_OPC_CheckField, 21, 1, 1, 30, 133, 0, // Skip to: 86948 /* 52870 */ MCD_OPC_Decode, 196, 1, 238, 1, // Opcode: ADDv2i32 /* 52875 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 52913 /* 52880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 52883 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 52898 /* 52888 */ MCD_OPC_CheckPredicate, 3, 7, 133, 0, // Skip to: 86948 /* 52893 */ MCD_OPC_Decode, 219, 3, 239, 1, // Opcode: CMGTv2i32rz /* 52898 */ MCD_OPC_FilterValue, 33, 253, 132, 0, // Skip to: 86948 /* 52903 */ MCD_OPC_CheckPredicate, 3, 248, 132, 0, // Skip to: 86948 /* 52908 */ MCD_OPC_Decode, 146, 12, 239, 1, // Opcode: FRINTPv2f32 /* 52913 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 52935 /* 52918 */ MCD_OPC_CheckPredicate, 3, 233, 132, 0, // Skip to: 86948 /* 52923 */ MCD_OPC_CheckField, 21, 1, 1, 226, 132, 0, // Skip to: 86948 /* 52930 */ MCD_OPC_Decode, 235, 4, 238, 1, // Opcode: CMTSTv2i32 /* 52935 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 52957 /* 52940 */ MCD_OPC_CheckPredicate, 3, 211, 132, 0, // Skip to: 86948 /* 52945 */ MCD_OPC_CheckField, 21, 1, 1, 204, 132, 0, // Skip to: 86948 /* 52952 */ MCD_OPC_Decode, 210, 24, 254, 1, // Opcode: SQDMLALv2i32_v2i64 /* 52957 */ MCD_OPC_FilterValue, 37, 33, 0, 0, // Skip to: 52995 /* 52962 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 52965 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52980 /* 52970 */ MCD_OPC_CheckPredicate, 10, 181, 132, 0, // Skip to: 86948 /* 52975 */ MCD_OPC_Decode, 232, 22, 130, 2, // Opcode: SDOTv8i8 /* 52980 */ MCD_OPC_FilterValue, 1, 171, 132, 0, // Skip to: 86948 /* 52985 */ MCD_OPC_CheckPredicate, 3, 166, 132, 0, // Skip to: 86948 /* 52990 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: MLAv2i32 /* 52995 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 53033 /* 53000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53018 /* 53008 */ MCD_OPC_CheckPredicate, 3, 143, 132, 0, // Skip to: 86948 /* 53013 */ MCD_OPC_Decode, 187, 3, 239, 1, // Opcode: CMEQv2i32rz /* 53018 */ MCD_OPC_FilterValue, 33, 133, 132, 0, // Skip to: 86948 /* 53023 */ MCD_OPC_CheckPredicate, 3, 128, 132, 0, // Skip to: 86948 /* 53028 */ MCD_OPC_Decode, 168, 12, 239, 1, // Opcode: FRINTZv2f32 /* 53033 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 53055 /* 53038 */ MCD_OPC_CheckPredicate, 3, 113, 132, 0, // Skip to: 86948 /* 53043 */ MCD_OPC_CheckField, 21, 1, 1, 106, 132, 0, // Skip to: 86948 /* 53050 */ MCD_OPC_Decode, 158, 20, 238, 1, // Opcode: MULv2i32 /* 53055 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 53077 /* 53060 */ MCD_OPC_CheckPredicate, 3, 91, 132, 0, // Skip to: 86948 /* 53065 */ MCD_OPC_CheckField, 21, 1, 1, 84, 132, 0, // Skip to: 86948 /* 53072 */ MCD_OPC_Decode, 248, 23, 254, 1, // Opcode: SMLSLv2i32_v2i64 /* 53077 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 53099 /* 53082 */ MCD_OPC_CheckPredicate, 3, 69, 132, 0, // Skip to: 86948 /* 53087 */ MCD_OPC_CheckField, 21, 1, 1, 62, 132, 0, // Skip to: 86948 /* 53094 */ MCD_OPC_Decode, 178, 23, 238, 1, // Opcode: SMAXPv2i32 /* 53099 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 53137 /* 53104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53107 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53122 /* 53112 */ MCD_OPC_CheckPredicate, 3, 39, 132, 0, // Skip to: 86948 /* 53117 */ MCD_OPC_Decode, 128, 4, 239, 1, // Opcode: CMLTv2i32rz /* 53122 */ MCD_OPC_FilterValue, 33, 29, 132, 0, // Skip to: 86948 /* 53127 */ MCD_OPC_CheckPredicate, 3, 24, 132, 0, // Skip to: 86948 /* 53132 */ MCD_OPC_Decode, 194, 8, 239, 1, // Opcode: FCVTPSv2f32 /* 53137 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 53159 /* 53142 */ MCD_OPC_CheckPredicate, 3, 9, 132, 0, // Skip to: 86948 /* 53147 */ MCD_OPC_CheckField, 21, 1, 1, 2, 132, 0, // Skip to: 86948 /* 53154 */ MCD_OPC_Decode, 208, 23, 238, 1, // Opcode: SMINPv2i32 /* 53159 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 53181 /* 53164 */ MCD_OPC_CheckPredicate, 3, 243, 131, 0, // Skip to: 86948 /* 53169 */ MCD_OPC_CheckField, 21, 1, 1, 236, 131, 0, // Skip to: 86948 /* 53176 */ MCD_OPC_Decode, 222, 24, 254, 1, // Opcode: SQDMLSLv2i32_v2i64 /* 53181 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 53203 /* 53186 */ MCD_OPC_CheckPredicate, 3, 221, 131, 0, // Skip to: 86948 /* 53191 */ MCD_OPC_CheckField, 21, 1, 1, 214, 131, 0, // Skip to: 86948 /* 53198 */ MCD_OPC_Decode, 233, 24, 238, 1, // Opcode: SQDMULHv2i32 /* 53203 */ MCD_OPC_FilterValue, 46, 33, 0, 0, // Skip to: 53241 /* 53208 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53211 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53226 /* 53216 */ MCD_OPC_CheckPredicate, 3, 191, 131, 0, // Skip to: 86948 /* 53221 */ MCD_OPC_Decode, 132, 1, 239, 1, // Opcode: ABSv2i32 /* 53226 */ MCD_OPC_FilterValue, 33, 181, 131, 0, // Skip to: 86948 /* 53231 */ MCD_OPC_CheckPredicate, 3, 176, 131, 0, // Skip to: 86948 /* 53236 */ MCD_OPC_Decode, 243, 8, 239, 1, // Opcode: FCVTZSv2f32 /* 53241 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 53263 /* 53246 */ MCD_OPC_CheckPredicate, 3, 161, 131, 0, // Skip to: 86948 /* 53251 */ MCD_OPC_CheckField, 21, 1, 1, 154, 131, 0, // Skip to: 86948 /* 53258 */ MCD_OPC_Decode, 150, 1, 238, 1, // Opcode: ADDPv2i32 /* 53263 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 53285 /* 53268 */ MCD_OPC_CheckPredicate, 3, 139, 131, 0, // Skip to: 86948 /* 53273 */ MCD_OPC_CheckField, 21, 1, 1, 132, 131, 0, // Skip to: 86948 /* 53280 */ MCD_OPC_Decode, 141, 24, 234, 1, // Opcode: SMULLv2i32_v2i64 /* 53285 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 53307 /* 53290 */ MCD_OPC_CheckPredicate, 3, 117, 131, 0, // Skip to: 86948 /* 53295 */ MCD_OPC_CheckField, 21, 1, 1, 110, 131, 0, // Skip to: 86948 /* 53302 */ MCD_OPC_Decode, 146, 10, 238, 1, // Opcode: FMINNMv2f32 /* 53307 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 53360 /* 53312 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53315 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53330 /* 53320 */ MCD_OPC_CheckPredicate, 3, 87, 131, 0, // Skip to: 86948 /* 53325 */ MCD_OPC_Decode, 147, 7, 239, 1, // Opcode: FCMGTv2i32rz /* 53330 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 53345 /* 53335 */ MCD_OPC_CheckPredicate, 3, 72, 131, 0, // Skip to: 86948 /* 53340 */ MCD_OPC_Decode, 217, 33, 239, 1, // Opcode: URECPEv2i32 /* 53345 */ MCD_OPC_FilterValue, 48, 62, 131, 0, // Skip to: 86948 /* 53350 */ MCD_OPC_CheckPredicate, 4, 57, 131, 0, // Skip to: 86948 /* 53355 */ MCD_OPC_Decode, 137, 10, 249, 1, // Opcode: FMINNMVv4i16v /* 53360 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 53382 /* 53365 */ MCD_OPC_CheckPredicate, 3, 42, 131, 0, // Skip to: 86948 /* 53370 */ MCD_OPC_CheckField, 21, 1, 1, 35, 131, 0, // Skip to: 86948 /* 53377 */ MCD_OPC_Decode, 205, 10, 130, 2, // Opcode: FMLSv2f32 /* 53382 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 53404 /* 53387 */ MCD_OPC_CheckPredicate, 3, 20, 131, 0, // Skip to: 86948 /* 53392 */ MCD_OPC_CheckField, 21, 1, 1, 13, 131, 0, // Skip to: 86948 /* 53399 */ MCD_OPC_Decode, 246, 24, 234, 1, // Opcode: SQDMULLv2i32_v2i64 /* 53404 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 53426 /* 53409 */ MCD_OPC_CheckPredicate, 3, 254, 130, 0, // Skip to: 86948 /* 53414 */ MCD_OPC_CheckField, 21, 1, 1, 247, 130, 0, // Skip to: 86948 /* 53421 */ MCD_OPC_Decode, 227, 12, 238, 1, // Opcode: FSUBv2f32 /* 53426 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 53464 /* 53431 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53434 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53449 /* 53439 */ MCD_OPC_CheckPredicate, 3, 224, 130, 0, // Skip to: 86948 /* 53444 */ MCD_OPC_Decode, 231, 6, 239, 1, // Opcode: FCMEQv2i32rz /* 53449 */ MCD_OPC_FilterValue, 33, 214, 130, 0, // Skip to: 86948 /* 53454 */ MCD_OPC_CheckPredicate, 3, 209, 130, 0, // Skip to: 86948 /* 53459 */ MCD_OPC_Decode, 202, 11, 239, 1, // Opcode: FRECPEv2f32 /* 53464 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 53486 /* 53469 */ MCD_OPC_CheckPredicate, 3, 194, 130, 0, // Skip to: 86948 /* 53474 */ MCD_OPC_CheckField, 16, 6, 32, 187, 130, 0, // Skip to: 86948 /* 53481 */ MCD_OPC_Decode, 185, 7, 239, 1, // Opcode: FCMLTv2i32rz /* 53486 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 53508 /* 53491 */ MCD_OPC_CheckPredicate, 3, 172, 130, 0, // Skip to: 86948 /* 53496 */ MCD_OPC_CheckField, 21, 1, 1, 165, 130, 0, // Skip to: 86948 /* 53503 */ MCD_OPC_Decode, 172, 10, 238, 1, // Opcode: FMINv2f32 /* 53508 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 53546 /* 53513 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53516 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53531 /* 53521 */ MCD_OPC_CheckPredicate, 3, 142, 130, 0, // Skip to: 86948 /* 53526 */ MCD_OPC_Decode, 145, 6, 239, 1, // Opcode: FABSv2f32 /* 53531 */ MCD_OPC_FilterValue, 48, 132, 130, 0, // Skip to: 86948 /* 53536 */ MCD_OPC_CheckPredicate, 4, 127, 130, 0, // Skip to: 86948 /* 53541 */ MCD_OPC_Decode, 163, 10, 249, 1, // Opcode: FMINVv4i16v /* 53546 */ MCD_OPC_FilterValue, 63, 117, 130, 0, // Skip to: 86948 /* 53551 */ MCD_OPC_CheckPredicate, 3, 112, 130, 0, // Skip to: 86948 /* 53556 */ MCD_OPC_CheckField, 21, 1, 1, 105, 130, 0, // Skip to: 86948 /* 53563 */ MCD_OPC_Decode, 190, 12, 238, 1, // Opcode: FRSQRTSv2f32 /* 53568 */ MCD_OPC_FilterValue, 1, 126, 5, 0, // Skip to: 54979 /* 53573 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 53576 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 53716 /* 53581 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 53584 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53606 /* 53589 */ MCD_OPC_CheckPredicate, 3, 74, 130, 0, // Skip to: 86948 /* 53594 */ MCD_OPC_CheckField, 21, 1, 1, 67, 130, 0, // Skip to: 86948 /* 53601 */ MCD_OPC_Decode, 154, 31, 234, 1, // Opcode: UADDLv2i32_v2i64 /* 53606 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53628 /* 53611 */ MCD_OPC_CheckPredicate, 3, 52, 130, 0, // Skip to: 86948 /* 53616 */ MCD_OPC_CheckField, 21, 1, 1, 45, 130, 0, // Skip to: 86948 /* 53623 */ MCD_OPC_Decode, 221, 31, 238, 1, // Opcode: UHADDv2i32 /* 53628 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 53650 /* 53633 */ MCD_OPC_CheckPredicate, 3, 30, 130, 0, // Skip to: 86948 /* 53638 */ MCD_OPC_CheckField, 21, 1, 1, 23, 130, 0, // Skip to: 86948 /* 53645 */ MCD_OPC_Decode, 216, 32, 238, 1, // Opcode: UQADDv2i32 /* 53650 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 53672 /* 53655 */ MCD_OPC_CheckPredicate, 3, 8, 130, 0, // Skip to: 86948 /* 53660 */ MCD_OPC_CheckField, 21, 1, 1, 1, 130, 0, // Skip to: 86948 /* 53667 */ MCD_OPC_Decode, 164, 31, 242, 1, // Opcode: UADDWv2i32_v2i64 /* 53672 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 53694 /* 53677 */ MCD_OPC_CheckPredicate, 3, 242, 129, 0, // Skip to: 86948 /* 53682 */ MCD_OPC_CheckField, 21, 1, 1, 235, 129, 0, // Skip to: 86948 /* 53689 */ MCD_OPC_Decode, 220, 33, 238, 1, // Opcode: URHADDv2i32 /* 53694 */ MCD_OPC_FilterValue, 7, 225, 129, 0, // Skip to: 86948 /* 53699 */ MCD_OPC_CheckPredicate, 3, 220, 129, 0, // Skip to: 86948 /* 53704 */ MCD_OPC_CheckField, 21, 1, 1, 213, 129, 0, // Skip to: 86948 /* 53711 */ MCD_OPC_Decode, 196, 2, 130, 2, // Opcode: BITv8i8 /* 53716 */ MCD_OPC_FilterValue, 1, 211, 0, 0, // Skip to: 53932 /* 53721 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 53724 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53746 /* 53729 */ MCD_OPC_CheckPredicate, 3, 190, 129, 0, // Skip to: 86948 /* 53734 */ MCD_OPC_CheckField, 21, 1, 1, 183, 129, 0, // Skip to: 86948 /* 53741 */ MCD_OPC_Decode, 165, 34, 234, 1, // Opcode: USUBLv2i32_v2i64 /* 53746 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53768 /* 53751 */ MCD_OPC_CheckPredicate, 3, 168, 129, 0, // Skip to: 86948 /* 53756 */ MCD_OPC_CheckField, 21, 1, 1, 161, 129, 0, // Skip to: 86948 /* 53763 */ MCD_OPC_Decode, 227, 31, 238, 1, // Opcode: UHSUBv2i32 /* 53768 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 53806 /* 53773 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53776 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53791 /* 53781 */ MCD_OPC_CheckPredicate, 3, 138, 129, 0, // Skip to: 86948 /* 53786 */ MCD_OPC_Decode, 143, 31, 239, 1, // Opcode: UADDLPv2i32_v1i64 /* 53791 */ MCD_OPC_FilterValue, 33, 128, 129, 0, // Skip to: 86948 /* 53796 */ MCD_OPC_CheckPredicate, 3, 123, 129, 0, // Skip to: 86948 /* 53801 */ MCD_OPC_Decode, 178, 26, 244, 1, // Opcode: SQXTUNv2i32 /* 53806 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 53828 /* 53811 */ MCD_OPC_CheckPredicate, 3, 108, 129, 0, // Skip to: 86948 /* 53816 */ MCD_OPC_CheckField, 21, 1, 1, 101, 129, 0, // Skip to: 86948 /* 53823 */ MCD_OPC_Decode, 202, 33, 238, 1, // Opcode: UQSUBv2i32 /* 53828 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 53850 /* 53833 */ MCD_OPC_CheckPredicate, 3, 86, 129, 0, // Skip to: 86948 /* 53838 */ MCD_OPC_CheckField, 21, 1, 1, 79, 129, 0, // Skip to: 86948 /* 53845 */ MCD_OPC_Decode, 171, 34, 242, 1, // Opcode: USUBWv2i32_v2i64 /* 53850 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 53872 /* 53855 */ MCD_OPC_CheckPredicate, 3, 64, 129, 0, // Skip to: 86948 /* 53860 */ MCD_OPC_CheckField, 21, 1, 1, 57, 129, 0, // Skip to: 86948 /* 53867 */ MCD_OPC_Decode, 232, 3, 238, 1, // Opcode: CMHIv2i32 /* 53872 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 53910 /* 53877 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53880 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53895 /* 53885 */ MCD_OPC_CheckPredicate, 3, 34, 129, 0, // Skip to: 86948 /* 53890 */ MCD_OPC_Decode, 150, 34, 248, 1, // Opcode: USQADDv2i32 /* 53895 */ MCD_OPC_FilterValue, 33, 24, 129, 0, // Skip to: 86948 /* 53900 */ MCD_OPC_CheckPredicate, 3, 19, 129, 0, // Skip to: 86948 /* 53905 */ MCD_OPC_Decode, 134, 23, 129, 2, // Opcode: SHLLv2i32 /* 53910 */ MCD_OPC_FilterValue, 7, 9, 129, 0, // Skip to: 86948 /* 53915 */ MCD_OPC_CheckPredicate, 3, 4, 129, 0, // Skip to: 86948 /* 53920 */ MCD_OPC_CheckField, 21, 1, 1, 253, 128, 0, // Skip to: 86948 /* 53927 */ MCD_OPC_Decode, 240, 3, 238, 1, // Opcode: CMHSv2i32 /* 53932 */ MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 54110 /* 53937 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 53940 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53962 /* 53945 */ MCD_OPC_CheckPredicate, 3, 230, 128, 0, // Skip to: 86948 /* 53950 */ MCD_OPC_CheckField, 21, 1, 1, 223, 128, 0, // Skip to: 86948 /* 53957 */ MCD_OPC_Decode, 177, 21, 252, 1, // Opcode: RADDHNv2i64_v2i32 /* 53962 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53984 /* 53967 */ MCD_OPC_CheckPredicate, 3, 208, 128, 0, // Skip to: 86948 /* 53972 */ MCD_OPC_CheckField, 21, 1, 1, 201, 128, 0, // Skip to: 86948 /* 53979 */ MCD_OPC_Decode, 131, 34, 238, 1, // Opcode: USHLv2i32 /* 53984 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 54022 /* 53989 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 53992 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54007 /* 53997 */ MCD_OPC_CheckPredicate, 3, 178, 128, 0, // Skip to: 86948 /* 54002 */ MCD_OPC_Decode, 177, 3, 239, 1, // Opcode: CLZv2i32 /* 54007 */ MCD_OPC_FilterValue, 33, 168, 128, 0, // Skip to: 86948 /* 54012 */ MCD_OPC_CheckPredicate, 3, 163, 128, 0, // Skip to: 86948 /* 54017 */ MCD_OPC_Decode, 212, 33, 244, 1, // Opcode: UQXTNv2i32 /* 54022 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54044 /* 54027 */ MCD_OPC_CheckPredicate, 3, 148, 128, 0, // Skip to: 86948 /* 54032 */ MCD_OPC_CheckField, 21, 1, 1, 141, 128, 0, // Skip to: 86948 /* 54039 */ MCD_OPC_Decode, 168, 33, 238, 1, // Opcode: UQSHLv2i32 /* 54044 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 54066 /* 54049 */ MCD_OPC_CheckPredicate, 3, 126, 128, 0, // Skip to: 86948 /* 54054 */ MCD_OPC_CheckField, 21, 1, 1, 119, 128, 0, // Skip to: 86948 /* 54061 */ MCD_OPC_Decode, 237, 30, 254, 1, // Opcode: UABALv2i32_v2i64 /* 54066 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54088 /* 54071 */ MCD_OPC_CheckPredicate, 3, 104, 128, 0, // Skip to: 86948 /* 54076 */ MCD_OPC_CheckField, 21, 1, 1, 97, 128, 0, // Skip to: 86948 /* 54083 */ MCD_OPC_Decode, 227, 33, 238, 1, // Opcode: URSHLv2i32 /* 54088 */ MCD_OPC_FilterValue, 7, 87, 128, 0, // Skip to: 86948 /* 54093 */ MCD_OPC_CheckPredicate, 3, 82, 128, 0, // Skip to: 86948 /* 54098 */ MCD_OPC_CheckField, 21, 1, 1, 75, 128, 0, // Skip to: 86948 /* 54105 */ MCD_OPC_Decode, 143, 33, 238, 1, // Opcode: UQRSHLv2i32 /* 54110 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 54294 /* 54115 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 54118 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54140 /* 54123 */ MCD_OPC_CheckPredicate, 3, 52, 128, 0, // Skip to: 86948 /* 54128 */ MCD_OPC_CheckField, 21, 1, 1, 45, 128, 0, // Skip to: 86948 /* 54135 */ MCD_OPC_Decode, 240, 21, 252, 1, // Opcode: RSUBHNv2i64_v2i32 /* 54140 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 54162 /* 54145 */ MCD_OPC_CheckPredicate, 3, 30, 128, 0, // Skip to: 86948 /* 54150 */ MCD_OPC_CheckField, 21, 1, 1, 23, 128, 0, // Skip to: 86948 /* 54157 */ MCD_OPC_Decode, 129, 32, 238, 1, // Opcode: UMAXv2i32 /* 54162 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54184 /* 54167 */ MCD_OPC_CheckPredicate, 3, 8, 128, 0, // Skip to: 86948 /* 54172 */ MCD_OPC_CheckField, 16, 6, 32, 1, 128, 0, // Skip to: 86948 /* 54179 */ MCD_OPC_Decode, 137, 31, 248, 1, // Opcode: UADALPv2i32_v1i64 /* 54184 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54206 /* 54189 */ MCD_OPC_CheckPredicate, 3, 242, 127, 0, // Skip to: 86948 /* 54194 */ MCD_OPC_CheckField, 21, 1, 1, 235, 127, 0, // Skip to: 86948 /* 54201 */ MCD_OPC_Decode, 158, 32, 238, 1, // Opcode: UMINv2i32 /* 54206 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 54228 /* 54211 */ MCD_OPC_CheckPredicate, 3, 220, 127, 0, // Skip to: 86948 /* 54216 */ MCD_OPC_CheckField, 21, 1, 1, 213, 127, 0, // Skip to: 86948 /* 54223 */ MCD_OPC_Decode, 249, 30, 234, 1, // Opcode: UABDLv2i32_v2i64 /* 54228 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54250 /* 54233 */ MCD_OPC_CheckPredicate, 3, 198, 127, 0, // Skip to: 86948 /* 54238 */ MCD_OPC_CheckField, 21, 1, 1, 191, 127, 0, // Skip to: 86948 /* 54245 */ MCD_OPC_Decode, 131, 31, 238, 1, // Opcode: UABDv2i32 /* 54250 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 54272 /* 54255 */ MCD_OPC_CheckPredicate, 3, 176, 127, 0, // Skip to: 86948 /* 54260 */ MCD_OPC_CheckField, 16, 6, 32, 169, 127, 0, // Skip to: 86948 /* 54267 */ MCD_OPC_Decode, 152, 25, 239, 1, // Opcode: SQNEGv2i32 /* 54272 */ MCD_OPC_FilterValue, 7, 159, 127, 0, // Skip to: 86948 /* 54277 */ MCD_OPC_CheckPredicate, 3, 154, 127, 0, // Skip to: 86948 /* 54282 */ MCD_OPC_CheckField, 21, 1, 1, 147, 127, 0, // Skip to: 86948 /* 54289 */ MCD_OPC_Decode, 243, 30, 130, 2, // Opcode: UABAv2i32 /* 54294 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 54498 /* 54299 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 54302 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54324 /* 54307 */ MCD_OPC_CheckPredicate, 3, 124, 127, 0, // Skip to: 86948 /* 54312 */ MCD_OPC_CheckField, 21, 1, 1, 117, 127, 0, // Skip to: 86948 /* 54319 */ MCD_OPC_Decode, 165, 32, 254, 1, // Opcode: UMLALv2i32_v2i64 /* 54324 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 54362 /* 54329 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 54332 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54347 /* 54337 */ MCD_OPC_CheckPredicate, 7, 94, 127, 0, // Skip to: 86948 /* 54342 */ MCD_OPC_Decode, 162, 25, 130, 2, // Opcode: SQRDMLAHv2i32 /* 54347 */ MCD_OPC_FilterValue, 1, 84, 127, 0, // Skip to: 86948 /* 54352 */ MCD_OPC_CheckPredicate, 3, 79, 127, 0, // Skip to: 86948 /* 54357 */ MCD_OPC_Decode, 129, 30, 238, 1, // Opcode: SUBv2i32 /* 54362 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54384 /* 54367 */ MCD_OPC_CheckPredicate, 3, 64, 127, 0, // Skip to: 86948 /* 54372 */ MCD_OPC_CheckField, 16, 6, 32, 57, 127, 0, // Skip to: 86948 /* 54379 */ MCD_OPC_Decode, 203, 3, 239, 1, // Opcode: CMGEv2i32rz /* 54384 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 54422 /* 54389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 54392 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54407 /* 54397 */ MCD_OPC_CheckPredicate, 7, 34, 127, 0, // Skip to: 86948 /* 54402 */ MCD_OPC_Decode, 174, 25, 130, 2, // Opcode: SQRDMLSHv2i32 /* 54407 */ MCD_OPC_FilterValue, 1, 24, 127, 0, // Skip to: 86948 /* 54412 */ MCD_OPC_CheckPredicate, 3, 19, 127, 0, // Skip to: 86948 /* 54417 */ MCD_OPC_Decode, 186, 3, 238, 1, // Opcode: CMEQv2i32 /* 54422 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 54460 /* 54427 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 54430 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54445 /* 54435 */ MCD_OPC_CheckPredicate, 10, 252, 126, 0, // Skip to: 86948 /* 54440 */ MCD_OPC_Decode, 219, 31, 130, 2, // Opcode: UDOTv8i8 /* 54445 */ MCD_OPC_FilterValue, 1, 242, 126, 0, // Skip to: 86948 /* 54450 */ MCD_OPC_CheckPredicate, 3, 237, 126, 0, // Skip to: 86948 /* 54455 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: MLSv2i32 /* 54460 */ MCD_OPC_FilterValue, 6, 227, 126, 0, // Skip to: 86948 /* 54465 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 54468 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54483 /* 54473 */ MCD_OPC_CheckPredicate, 3, 214, 126, 0, // Skip to: 86948 /* 54478 */ MCD_OPC_Decode, 248, 3, 239, 1, // Opcode: CMLEv2i32rz /* 54483 */ MCD_OPC_FilterValue, 33, 204, 126, 0, // Skip to: 86948 /* 54488 */ MCD_OPC_CheckPredicate, 3, 199, 126, 0, // Skip to: 86948 /* 54493 */ MCD_OPC_Decode, 241, 11, 239, 1, // Opcode: FRINTIv2f32 /* 54498 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 54654 /* 54503 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 54506 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54528 /* 54511 */ MCD_OPC_CheckPredicate, 3, 176, 126, 0, // Skip to: 86948 /* 54516 */ MCD_OPC_CheckField, 21, 1, 1, 169, 126, 0, // Skip to: 86948 /* 54523 */ MCD_OPC_Decode, 175, 32, 254, 1, // Opcode: UMLSLv2i32_v2i64 /* 54528 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 54550 /* 54533 */ MCD_OPC_CheckPredicate, 3, 154, 126, 0, // Skip to: 86948 /* 54538 */ MCD_OPC_CheckField, 21, 1, 1, 147, 126, 0, // Skip to: 86948 /* 54545 */ MCD_OPC_Decode, 234, 31, 238, 1, // Opcode: UMAXPv2i32 /* 54550 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54572 /* 54555 */ MCD_OPC_CheckPredicate, 3, 132, 126, 0, // Skip to: 86948 /* 54560 */ MCD_OPC_CheckField, 16, 6, 33, 125, 126, 0, // Skip to: 86948 /* 54567 */ MCD_OPC_Decode, 208, 8, 239, 1, // Opcode: FCVTPUv2f32 /* 54572 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54594 /* 54577 */ MCD_OPC_CheckPredicate, 3, 110, 126, 0, // Skip to: 86948 /* 54582 */ MCD_OPC_CheckField, 21, 1, 1, 103, 126, 0, // Skip to: 86948 /* 54589 */ MCD_OPC_Decode, 135, 32, 238, 1, // Opcode: UMINPv2i32 /* 54594 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54616 /* 54599 */ MCD_OPC_CheckPredicate, 3, 88, 126, 0, // Skip to: 86948 /* 54604 */ MCD_OPC_CheckField, 21, 1, 1, 81, 126, 0, // Skip to: 86948 /* 54611 */ MCD_OPC_Decode, 186, 25, 238, 1, // Opcode: SQRDMULHv2i32 /* 54616 */ MCD_OPC_FilterValue, 6, 71, 126, 0, // Skip to: 86948 /* 54621 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 54624 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54639 /* 54629 */ MCD_OPC_CheckPredicate, 3, 58, 126, 0, // Skip to: 86948 /* 54634 */ MCD_OPC_Decode, 181, 20, 239, 1, // Opcode: NEGv2i32 /* 54639 */ MCD_OPC_FilterValue, 33, 48, 126, 0, // Skip to: 86948 /* 54644 */ MCD_OPC_CheckPredicate, 3, 43, 126, 0, // Skip to: 86948 /* 54649 */ MCD_OPC_Decode, 150, 9, 239, 1, // Opcode: FCVTZUv2f32 /* 54654 */ MCD_OPC_FilterValue, 6, 170, 0, 0, // Skip to: 54829 /* 54659 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 54662 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 54768 /* 54667 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 54670 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54692 /* 54675 */ MCD_OPC_CheckPredicate, 3, 12, 126, 0, // Skip to: 86948 /* 54680 */ MCD_OPC_CheckField, 21, 1, 1, 5, 126, 0, // Skip to: 86948 /* 54687 */ MCD_OPC_Decode, 195, 32, 234, 1, // Opcode: UMULLv2i32_v2i64 /* 54692 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 54730 /* 54697 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 54700 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54715 /* 54705 */ MCD_OPC_CheckPredicate, 3, 238, 125, 0, // Skip to: 86948 /* 54710 */ MCD_OPC_Decode, 253, 6, 239, 1, // Opcode: FCMGEv2i32rz /* 54715 */ MCD_OPC_FilterValue, 33, 228, 125, 0, // Skip to: 86948 /* 54720 */ MCD_OPC_CheckPredicate, 3, 223, 125, 0, // Skip to: 86948 /* 54725 */ MCD_OPC_Decode, 241, 33, 239, 1, // Opcode: URSQRTEv2i32 /* 54730 */ MCD_OPC_FilterValue, 3, 213, 125, 0, // Skip to: 86948 /* 54735 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 54738 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54753 /* 54743 */ MCD_OPC_CheckPredicate, 3, 200, 125, 0, // Skip to: 86948 /* 54748 */ MCD_OPC_Decode, 174, 7, 239, 1, // Opcode: FCMLEv2i32rz /* 54753 */ MCD_OPC_FilterValue, 33, 190, 125, 0, // Skip to: 86948 /* 54758 */ MCD_OPC_CheckPredicate, 3, 185, 125, 0, // Skip to: 86948 /* 54763 */ MCD_OPC_Decode, 179, 12, 239, 1, // Opcode: FRSQRTEv2f32 /* 54768 */ MCD_OPC_FilterValue, 1, 175, 125, 0, // Skip to: 86948 /* 54773 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 54776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54791 /* 54781 */ MCD_OPC_CheckPredicate, 11, 162, 125, 0, // Skip to: 86948 /* 54786 */ MCD_OPC_Decode, 160, 7, 167, 2, // Opcode: FCMLAv2f32 /* 54791 */ MCD_OPC_FilterValue, 1, 152, 125, 0, // Skip to: 86948 /* 54796 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 54799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54814 /* 54804 */ MCD_OPC_CheckPredicate, 3, 139, 125, 0, // Skip to: 86948 /* 54809 */ MCD_OPC_Decode, 253, 9, 238, 1, // Opcode: FMINNMPv2f32 /* 54814 */ MCD_OPC_FilterValue, 2, 129, 125, 0, // Skip to: 86948 /* 54819 */ MCD_OPC_CheckPredicate, 3, 124, 125, 0, // Skip to: 86948 /* 54824 */ MCD_OPC_Decode, 134, 6, 238, 1, // Opcode: FABDv2f32 /* 54829 */ MCD_OPC_FilterValue, 7, 114, 125, 0, // Skip to: 86948 /* 54834 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 54837 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 54898 /* 54842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 54845 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54860 /* 54850 */ MCD_OPC_CheckPredicate, 11, 93, 125, 0, // Skip to: 86948 /* 54855 */ MCD_OPC_Decode, 206, 6, 168, 2, // Opcode: FCADDv2f32 /* 54860 */ MCD_OPC_FilterValue, 1, 83, 125, 0, // Skip to: 86948 /* 54865 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 54868 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54883 /* 54873 */ MCD_OPC_CheckPredicate, 3, 70, 125, 0, // Skip to: 86948 /* 54878 */ MCD_OPC_Decode, 145, 7, 238, 1, // Opcode: FCMGTv2f32 /* 54883 */ MCD_OPC_FilterValue, 1, 60, 125, 0, // Skip to: 86948 /* 54888 */ MCD_OPC_CheckPredicate, 3, 55, 125, 0, // Skip to: 86948 /* 54893 */ MCD_OPC_Decode, 151, 10, 238, 1, // Opcode: FMINPv2f32 /* 54898 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 54950 /* 54903 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 54906 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 54928 /* 54911 */ MCD_OPC_CheckPredicate, 3, 32, 125, 0, // Skip to: 86948 /* 54916 */ MCD_OPC_CheckField, 12, 1, 1, 25, 125, 0, // Skip to: 86948 /* 54923 */ MCD_OPC_Decode, 170, 11, 239, 1, // Opcode: FNEGv2f32 /* 54928 */ MCD_OPC_FilterValue, 33, 15, 125, 0, // Skip to: 86948 /* 54933 */ MCD_OPC_CheckPredicate, 3, 10, 125, 0, // Skip to: 86948 /* 54938 */ MCD_OPC_CheckField, 12, 1, 1, 3, 125, 0, // Skip to: 86948 /* 54945 */ MCD_OPC_Decode, 204, 12, 239, 1, // Opcode: FSQRTv2f32 /* 54950 */ MCD_OPC_FilterValue, 3, 249, 124, 0, // Skip to: 86948 /* 54955 */ MCD_OPC_CheckPredicate, 3, 244, 124, 0, // Skip to: 86948 /* 54960 */ MCD_OPC_CheckField, 21, 1, 1, 237, 124, 0, // Skip to: 86948 /* 54967 */ MCD_OPC_CheckField, 12, 1, 0, 230, 124, 0, // Skip to: 86948 /* 54974 */ MCD_OPC_Decode, 167, 6, 238, 1, // Opcode: FACGTv2f32 /* 54979 */ MCD_OPC_FilterValue, 2, 93, 6, 0, // Skip to: 56613 /* 54984 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 54987 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 55009 /* 54992 */ MCD_OPC_CheckPredicate, 3, 207, 124, 0, // Skip to: 86948 /* 54997 */ MCD_OPC_CheckField, 21, 1, 1, 200, 124, 0, // Skip to: 86948 /* 55004 */ MCD_OPC_Decode, 166, 22, 133, 2, // Opcode: SADDLv4i32_v2i64 /* 55009 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 55031 /* 55014 */ MCD_OPC_CheckPredicate, 3, 185, 124, 0, // Skip to: 86948 /* 55019 */ MCD_OPC_CheckField, 21, 1, 1, 178, 124, 0, // Skip to: 86948 /* 55026 */ MCD_OPC_Decode, 130, 23, 133, 2, // Opcode: SHADDv4i32 /* 55031 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 55053 /* 55036 */ MCD_OPC_CheckPredicate, 3, 163, 124, 0, // Skip to: 86948 /* 55041 */ MCD_OPC_CheckField, 16, 6, 32, 156, 124, 0, // Skip to: 86948 /* 55048 */ MCD_OPC_Decode, 212, 21, 138, 2, // Opcode: REV64v4i32 /* 55053 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 55075 /* 55058 */ MCD_OPC_CheckPredicate, 3, 141, 124, 0, // Skip to: 86948 /* 55063 */ MCD_OPC_CheckField, 21, 1, 1, 134, 124, 0, // Skip to: 86948 /* 55070 */ MCD_OPC_Decode, 180, 24, 133, 2, // Opcode: SQADDv4i32 /* 55075 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 55097 /* 55080 */ MCD_OPC_CheckPredicate, 3, 119, 124, 0, // Skip to: 86948 /* 55085 */ MCD_OPC_CheckField, 21, 1, 1, 112, 124, 0, // Skip to: 86948 /* 55092 */ MCD_OPC_Decode, 175, 22, 133, 2, // Opcode: SADDWv4i32_v2i64 /* 55097 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 55119 /* 55102 */ MCD_OPC_CheckPredicate, 3, 97, 124, 0, // Skip to: 86948 /* 55107 */ MCD_OPC_CheckField, 21, 1, 1, 90, 124, 0, // Skip to: 86948 /* 55114 */ MCD_OPC_Decode, 186, 26, 133, 2, // Opcode: SRHADDv4i32 /* 55119 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 55141 /* 55124 */ MCD_OPC_CheckPredicate, 3, 75, 124, 0, // Skip to: 86948 /* 55129 */ MCD_OPC_CheckField, 21, 1, 0, 68, 124, 0, // Skip to: 86948 /* 55136 */ MCD_OPC_Decode, 200, 34, 133, 2, // Opcode: UZP1v4i32 /* 55141 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 55163 /* 55146 */ MCD_OPC_CheckPredicate, 3, 53, 124, 0, // Skip to: 86948 /* 55151 */ MCD_OPC_CheckField, 21, 1, 1, 46, 124, 0, // Skip to: 86948 /* 55158 */ MCD_OPC_Decode, 217, 20, 133, 2, // Opcode: ORRv16i8 /* 55163 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 55185 /* 55168 */ MCD_OPC_CheckPredicate, 3, 31, 124, 0, // Skip to: 86948 /* 55173 */ MCD_OPC_CheckField, 21, 1, 1, 24, 124, 0, // Skip to: 86948 /* 55180 */ MCD_OPC_Decode, 164, 27, 133, 2, // Opcode: SSUBLv4i32_v2i64 /* 55185 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 55207 /* 55190 */ MCD_OPC_CheckPredicate, 3, 9, 124, 0, // Skip to: 86948 /* 55195 */ MCD_OPC_CheckField, 21, 1, 1, 2, 124, 0, // Skip to: 86948 /* 55202 */ MCD_OPC_Decode, 156, 23, 133, 2, // Opcode: SHSUBv4i32 /* 55207 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 55268 /* 55212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 55215 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55230 /* 55220 */ MCD_OPC_CheckPredicate, 3, 235, 123, 0, // Skip to: 86948 /* 55225 */ MCD_OPC_Decode, 217, 30, 133, 2, // Opcode: TRN1v4i32 /* 55230 */ MCD_OPC_FilterValue, 1, 225, 123, 0, // Skip to: 86948 /* 55235 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 55238 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55253 /* 55243 */ MCD_OPC_CheckPredicate, 3, 212, 123, 0, // Skip to: 86948 /* 55248 */ MCD_OPC_Decode, 155, 22, 138, 2, // Opcode: SADDLPv4i32_v2i64 /* 55253 */ MCD_OPC_FilterValue, 1, 202, 123, 0, // Skip to: 86948 /* 55258 */ MCD_OPC_CheckPredicate, 3, 197, 123, 0, // Skip to: 86948 /* 55263 */ MCD_OPC_Decode, 130, 35, 147, 2, // Opcode: XTNv4i32 /* 55268 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 55290 /* 55273 */ MCD_OPC_CheckPredicate, 3, 182, 123, 0, // Skip to: 86948 /* 55278 */ MCD_OPC_CheckField, 21, 1, 1, 175, 123, 0, // Skip to: 86948 /* 55285 */ MCD_OPC_Decode, 162, 26, 133, 2, // Opcode: SQSUBv4i32 /* 55290 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 55312 /* 55295 */ MCD_OPC_CheckPredicate, 3, 160, 123, 0, // Skip to: 86948 /* 55300 */ MCD_OPC_CheckField, 21, 1, 1, 153, 123, 0, // Skip to: 86948 /* 55307 */ MCD_OPC_Decode, 170, 27, 133, 2, // Opcode: SSUBWv4i32_v2i64 /* 55312 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 55334 /* 55317 */ MCD_OPC_CheckPredicate, 3, 138, 123, 0, // Skip to: 86948 /* 55322 */ MCD_OPC_CheckField, 21, 1, 1, 131, 123, 0, // Skip to: 86948 /* 55329 */ MCD_OPC_Decode, 224, 3, 133, 2, // Opcode: CMGTv4i32 /* 55334 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 55395 /* 55339 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 55342 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55357 /* 55347 */ MCD_OPC_CheckPredicate, 3, 108, 123, 0, // Skip to: 86948 /* 55352 */ MCD_OPC_Decode, 145, 35, 133, 2, // Opcode: ZIP1v4i32 /* 55357 */ MCD_OPC_FilterValue, 1, 98, 123, 0, // Skip to: 86948 /* 55362 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 55365 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55380 /* 55370 */ MCD_OPC_CheckPredicate, 3, 85, 123, 0, // Skip to: 86948 /* 55375 */ MCD_OPC_Decode, 149, 30, 147, 2, // Opcode: SUQADDv4i32 /* 55380 */ MCD_OPC_FilterValue, 16, 75, 123, 0, // Skip to: 86948 /* 55385 */ MCD_OPC_CheckPredicate, 3, 70, 123, 0, // Skip to: 86948 /* 55390 */ MCD_OPC_Decode, 160, 22, 244, 1, // Opcode: SADDLVv4i32v /* 55395 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 55417 /* 55400 */ MCD_OPC_CheckPredicate, 3, 55, 123, 0, // Skip to: 86948 /* 55405 */ MCD_OPC_CheckField, 21, 1, 1, 48, 123, 0, // Skip to: 86948 /* 55412 */ MCD_OPC_Decode, 208, 3, 133, 2, // Opcode: CMGEv4i32 /* 55417 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 55439 /* 55422 */ MCD_OPC_CheckPredicate, 3, 33, 123, 0, // Skip to: 86948 /* 55427 */ MCD_OPC_CheckField, 21, 1, 1, 26, 123, 0, // Skip to: 86948 /* 55434 */ MCD_OPC_Decode, 143, 1, 141, 2, // Opcode: ADDHNv2i64_v4i32 /* 55439 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 55461 /* 55444 */ MCD_OPC_CheckPredicate, 3, 11, 123, 0, // Skip to: 86948 /* 55449 */ MCD_OPC_CheckField, 21, 1, 1, 4, 123, 0, // Skip to: 86948 /* 55456 */ MCD_OPC_Decode, 232, 26, 133, 2, // Opcode: SSHLv4i32 /* 55461 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 55499 /* 55466 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 55469 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 55484 /* 55474 */ MCD_OPC_CheckPredicate, 3, 237, 122, 0, // Skip to: 86948 /* 55479 */ MCD_OPC_Decode, 167, 3, 138, 2, // Opcode: CLSv4i32 /* 55484 */ MCD_OPC_FilterValue, 33, 227, 122, 0, // Skip to: 86948 /* 55489 */ MCD_OPC_CheckPredicate, 3, 222, 122, 0, // Skip to: 86948 /* 55494 */ MCD_OPC_Decode, 171, 26, 147, 2, // Opcode: SQXTNv4i32 /* 55499 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 55521 /* 55504 */ MCD_OPC_CheckPredicate, 3, 207, 122, 0, // Skip to: 86948 /* 55509 */ MCD_OPC_CheckField, 21, 1, 1, 200, 122, 0, // Skip to: 86948 /* 55516 */ MCD_OPC_Decode, 250, 25, 133, 2, // Opcode: SQSHLv4i32 /* 55521 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 55543 /* 55526 */ MCD_OPC_CheckPredicate, 3, 185, 122, 0, // Skip to: 86948 /* 55531 */ MCD_OPC_CheckField, 21, 1, 1, 178, 122, 0, // Skip to: 86948 /* 55538 */ MCD_OPC_Decode, 249, 21, 141, 2, // Opcode: SABALv4i32_v2i64 /* 55543 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 55565 /* 55548 */ MCD_OPC_CheckPredicate, 3, 163, 122, 0, // Skip to: 86948 /* 55553 */ MCD_OPC_CheckField, 21, 1, 1, 156, 122, 0, // Skip to: 86948 /* 55560 */ MCD_OPC_Decode, 202, 26, 133, 2, // Opcode: SRSHLv4i32 /* 55565 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 55587 /* 55570 */ MCD_OPC_CheckPredicate, 3, 141, 122, 0, // Skip to: 86948 /* 55575 */ MCD_OPC_CheckField, 21, 1, 0, 134, 122, 0, // Skip to: 86948 /* 55582 */ MCD_OPC_Decode, 215, 34, 133, 2, // Opcode: UZP2v4i32 /* 55587 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 55609 /* 55592 */ MCD_OPC_CheckPredicate, 3, 119, 122, 0, // Skip to: 86948 /* 55597 */ MCD_OPC_CheckField, 21, 1, 1, 112, 122, 0, // Skip to: 86948 /* 55604 */ MCD_OPC_Decode, 202, 25, 133, 2, // Opcode: SQRSHLv4i32 /* 55609 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 55631 /* 55614 */ MCD_OPC_CheckPredicate, 3, 97, 122, 0, // Skip to: 86948 /* 55619 */ MCD_OPC_CheckField, 21, 1, 1, 90, 122, 0, // Skip to: 86948 /* 55626 */ MCD_OPC_Decode, 212, 29, 141, 2, // Opcode: SUBHNv2i64_v4i32 /* 55631 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 55653 /* 55636 */ MCD_OPC_CheckPredicate, 3, 75, 122, 0, // Skip to: 86948 /* 55641 */ MCD_OPC_CheckField, 21, 1, 1, 68, 122, 0, // Skip to: 86948 /* 55648 */ MCD_OPC_Decode, 203, 23, 133, 2, // Opcode: SMAXv4i32 /* 55653 */ MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 55698 /* 55658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 55661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55676 /* 55666 */ MCD_OPC_CheckPredicate, 3, 45, 122, 0, // Skip to: 86948 /* 55671 */ MCD_OPC_Decode, 232, 30, 133, 2, // Opcode: TRN2v4i32 /* 55676 */ MCD_OPC_FilterValue, 1, 35, 122, 0, // Skip to: 86948 /* 55681 */ MCD_OPC_CheckPredicate, 3, 30, 122, 0, // Skip to: 86948 /* 55686 */ MCD_OPC_CheckField, 16, 5, 0, 23, 122, 0, // Skip to: 86948 /* 55693 */ MCD_OPC_Decode, 149, 22, 147, 2, // Opcode: SADALPv4i32_v2i64 /* 55698 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 55720 /* 55703 */ MCD_OPC_CheckPredicate, 3, 8, 122, 0, // Skip to: 86948 /* 55708 */ MCD_OPC_CheckField, 21, 1, 1, 1, 122, 0, // Skip to: 86948 /* 55715 */ MCD_OPC_Decode, 233, 23, 133, 2, // Opcode: SMINv4i32 /* 55720 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 55742 /* 55725 */ MCD_OPC_CheckPredicate, 3, 242, 121, 0, // Skip to: 86948 /* 55730 */ MCD_OPC_CheckField, 21, 1, 1, 235, 121, 0, // Skip to: 86948 /* 55737 */ MCD_OPC_Decode, 133, 22, 133, 2, // Opcode: SABDLv4i32_v2i64 /* 55742 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 55764 /* 55747 */ MCD_OPC_CheckPredicate, 3, 220, 121, 0, // Skip to: 86948 /* 55752 */ MCD_OPC_CheckField, 21, 1, 1, 213, 121, 0, // Skip to: 86948 /* 55759 */ MCD_OPC_Decode, 143, 22, 133, 2, // Opcode: SABDv4i32 /* 55764 */ MCD_OPC_FilterValue, 30, 40, 0, 0, // Skip to: 55809 /* 55769 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 55772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55787 /* 55777 */ MCD_OPC_CheckPredicate, 3, 190, 121, 0, // Skip to: 86948 /* 55782 */ MCD_OPC_Decode, 160, 35, 133, 2, // Opcode: ZIP2v4i32 /* 55787 */ MCD_OPC_FilterValue, 1, 180, 121, 0, // Skip to: 86948 /* 55792 */ MCD_OPC_CheckPredicate, 3, 175, 121, 0, // Skip to: 86948 /* 55797 */ MCD_OPC_CheckField, 16, 5, 0, 168, 121, 0, // Skip to: 86948 /* 55804 */ MCD_OPC_Decode, 161, 24, 138, 2, // Opcode: SQABSv4i32 /* 55809 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 55831 /* 55814 */ MCD_OPC_CheckPredicate, 3, 153, 121, 0, // Skip to: 86948 /* 55819 */ MCD_OPC_CheckField, 21, 1, 1, 146, 121, 0, // Skip to: 86948 /* 55826 */ MCD_OPC_Decode, 255, 21, 141, 2, // Opcode: SABAv4i32 /* 55831 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 55853 /* 55836 */ MCD_OPC_CheckPredicate, 3, 131, 121, 0, // Skip to: 86948 /* 55841 */ MCD_OPC_CheckField, 21, 1, 1, 124, 121, 0, // Skip to: 86948 /* 55848 */ MCD_OPC_Decode, 242, 23, 141, 2, // Opcode: SMLALv4i32_v2i64 /* 55853 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 55875 /* 55858 */ MCD_OPC_CheckPredicate, 3, 109, 121, 0, // Skip to: 86948 /* 55863 */ MCD_OPC_CheckField, 21, 1, 1, 102, 121, 0, // Skip to: 86948 /* 55870 */ MCD_OPC_Decode, 199, 1, 133, 2, // Opcode: ADDv4i32 /* 55875 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 55913 /* 55880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 55883 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 55898 /* 55888 */ MCD_OPC_CheckPredicate, 3, 79, 121, 0, // Skip to: 86948 /* 55893 */ MCD_OPC_Decode, 225, 3, 138, 2, // Opcode: CMGTv4i32rz /* 55898 */ MCD_OPC_FilterValue, 33, 69, 121, 0, // Skip to: 86948 /* 55903 */ MCD_OPC_CheckPredicate, 3, 64, 121, 0, // Skip to: 86948 /* 55908 */ MCD_OPC_Decode, 149, 12, 138, 2, // Opcode: FRINTPv4f32 /* 55913 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 55935 /* 55918 */ MCD_OPC_CheckPredicate, 3, 49, 121, 0, // Skip to: 86948 /* 55923 */ MCD_OPC_CheckField, 21, 1, 1, 42, 121, 0, // Skip to: 86948 /* 55930 */ MCD_OPC_Decode, 238, 4, 133, 2, // Opcode: CMTSTv4i32 /* 55935 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 55957 /* 55940 */ MCD_OPC_CheckPredicate, 3, 27, 121, 0, // Skip to: 86948 /* 55945 */ MCD_OPC_CheckField, 21, 1, 1, 20, 121, 0, // Skip to: 86948 /* 55952 */ MCD_OPC_Decode, 214, 24, 141, 2, // Opcode: SQDMLALv4i32_v2i64 /* 55957 */ MCD_OPC_FilterValue, 37, 33, 0, 0, // Skip to: 55995 /* 55962 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 55965 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55980 /* 55970 */ MCD_OPC_CheckPredicate, 10, 253, 120, 0, // Skip to: 86948 /* 55975 */ MCD_OPC_Decode, 231, 22, 141, 2, // Opcode: SDOTv16i8 /* 55980 */ MCD_OPC_FilterValue, 1, 243, 120, 0, // Skip to: 86948 /* 55985 */ MCD_OPC_CheckPredicate, 3, 238, 120, 0, // Skip to: 86948 /* 55990 */ MCD_OPC_Decode, 214, 19, 141, 2, // Opcode: MLAv4i32 /* 55995 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 56033 /* 56000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56018 /* 56008 */ MCD_OPC_CheckPredicate, 3, 215, 120, 0, // Skip to: 86948 /* 56013 */ MCD_OPC_Decode, 193, 3, 138, 2, // Opcode: CMEQv4i32rz /* 56018 */ MCD_OPC_FilterValue, 33, 205, 120, 0, // Skip to: 86948 /* 56023 */ MCD_OPC_CheckPredicate, 3, 200, 120, 0, // Skip to: 86948 /* 56028 */ MCD_OPC_Decode, 171, 12, 138, 2, // Opcode: FRINTZv4f32 /* 56033 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 56055 /* 56038 */ MCD_OPC_CheckPredicate, 3, 185, 120, 0, // Skip to: 86948 /* 56043 */ MCD_OPC_CheckField, 21, 1, 1, 178, 120, 0, // Skip to: 86948 /* 56050 */ MCD_OPC_Decode, 162, 20, 133, 2, // Opcode: MULv4i32 /* 56055 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 56077 /* 56060 */ MCD_OPC_CheckPredicate, 3, 163, 120, 0, // Skip to: 86948 /* 56065 */ MCD_OPC_CheckField, 21, 1, 1, 156, 120, 0, // Skip to: 86948 /* 56072 */ MCD_OPC_Decode, 252, 23, 141, 2, // Opcode: SMLSLv4i32_v2i64 /* 56077 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 56099 /* 56082 */ MCD_OPC_CheckPredicate, 3, 141, 120, 0, // Skip to: 86948 /* 56087 */ MCD_OPC_CheckField, 21, 1, 1, 134, 120, 0, // Skip to: 86948 /* 56094 */ MCD_OPC_Decode, 180, 23, 133, 2, // Opcode: SMAXPv4i32 /* 56099 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 56167 /* 56104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56107 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56122 /* 56112 */ MCD_OPC_CheckPredicate, 3, 111, 120, 0, // Skip to: 86948 /* 56117 */ MCD_OPC_Decode, 131, 4, 138, 2, // Opcode: CMLTv4i32rz /* 56122 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56137 /* 56127 */ MCD_OPC_CheckPredicate, 3, 96, 120, 0, // Skip to: 86948 /* 56132 */ MCD_OPC_Decode, 197, 8, 138, 2, // Opcode: FCVTPSv4f32 /* 56137 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 56152 /* 56142 */ MCD_OPC_CheckPredicate, 3, 81, 120, 0, // Skip to: 86948 /* 56147 */ MCD_OPC_Decode, 189, 23, 160, 2, // Opcode: SMAXVv4i32v /* 56152 */ MCD_OPC_FilterValue, 49, 71, 120, 0, // Skip to: 86948 /* 56157 */ MCD_OPC_CheckPredicate, 3, 66, 120, 0, // Skip to: 86948 /* 56162 */ MCD_OPC_Decode, 219, 23, 160, 2, // Opcode: SMINVv4i32v /* 56167 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 56189 /* 56172 */ MCD_OPC_CheckPredicate, 3, 51, 120, 0, // Skip to: 86948 /* 56177 */ MCD_OPC_CheckField, 21, 1, 1, 44, 120, 0, // Skip to: 86948 /* 56184 */ MCD_OPC_Decode, 210, 23, 133, 2, // Opcode: SMINPv4i32 /* 56189 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 56211 /* 56194 */ MCD_OPC_CheckPredicate, 3, 29, 120, 0, // Skip to: 86948 /* 56199 */ MCD_OPC_CheckField, 21, 1, 1, 22, 120, 0, // Skip to: 86948 /* 56206 */ MCD_OPC_Decode, 226, 24, 141, 2, // Opcode: SQDMLSLv4i32_v2i64 /* 56211 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 56233 /* 56216 */ MCD_OPC_CheckPredicate, 3, 7, 120, 0, // Skip to: 86948 /* 56221 */ MCD_OPC_CheckField, 21, 1, 1, 0, 120, 0, // Skip to: 86948 /* 56228 */ MCD_OPC_Decode, 237, 24, 133, 2, // Opcode: SQDMULHv4i32 /* 56233 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 56286 /* 56238 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56241 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56256 /* 56246 */ MCD_OPC_CheckPredicate, 3, 233, 119, 0, // Skip to: 86948 /* 56251 */ MCD_OPC_Decode, 135, 1, 138, 2, // Opcode: ABSv4i32 /* 56256 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56271 /* 56261 */ MCD_OPC_CheckPredicate, 3, 218, 119, 0, // Skip to: 86948 /* 56266 */ MCD_OPC_Decode, 248, 8, 138, 2, // Opcode: FCVTZSv4f32 /* 56271 */ MCD_OPC_FilterValue, 49, 208, 119, 0, // Skip to: 86948 /* 56276 */ MCD_OPC_CheckPredicate, 3, 203, 119, 0, // Skip to: 86948 /* 56281 */ MCD_OPC_Decode, 169, 1, 160, 2, // Opcode: ADDVv4i32v /* 56286 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 56308 /* 56291 */ MCD_OPC_CheckPredicate, 3, 188, 119, 0, // Skip to: 86948 /* 56296 */ MCD_OPC_CheckField, 21, 1, 1, 181, 119, 0, // Skip to: 86948 /* 56303 */ MCD_OPC_Decode, 154, 1, 133, 2, // Opcode: ADDPv4i32 /* 56308 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 56330 /* 56313 */ MCD_OPC_CheckPredicate, 3, 166, 119, 0, // Skip to: 86948 /* 56318 */ MCD_OPC_CheckField, 21, 1, 1, 159, 119, 0, // Skip to: 86948 /* 56325 */ MCD_OPC_Decode, 145, 24, 133, 2, // Opcode: SMULLv4i32_v2i64 /* 56330 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 56352 /* 56335 */ MCD_OPC_CheckPredicate, 3, 144, 119, 0, // Skip to: 86948 /* 56340 */ MCD_OPC_CheckField, 21, 1, 1, 137, 119, 0, // Skip to: 86948 /* 56347 */ MCD_OPC_Decode, 149, 10, 133, 2, // Opcode: FMINNMv4f32 /* 56352 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 56405 /* 56357 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56360 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56375 /* 56365 */ MCD_OPC_CheckPredicate, 3, 114, 119, 0, // Skip to: 86948 /* 56370 */ MCD_OPC_Decode, 152, 7, 138, 2, // Opcode: FCMGTv4i32rz /* 56375 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56390 /* 56380 */ MCD_OPC_CheckPredicate, 3, 99, 119, 0, // Skip to: 86948 /* 56385 */ MCD_OPC_Decode, 218, 33, 138, 2, // Opcode: URECPEv4i32 /* 56390 */ MCD_OPC_FilterValue, 48, 89, 119, 0, // Skip to: 86948 /* 56395 */ MCD_OPC_CheckPredicate, 4, 84, 119, 0, // Skip to: 86948 /* 56400 */ MCD_OPC_Decode, 139, 10, 152, 2, // Opcode: FMINNMVv8i16v /* 56405 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 56427 /* 56410 */ MCD_OPC_CheckPredicate, 3, 69, 119, 0, // Skip to: 86948 /* 56415 */ MCD_OPC_CheckField, 21, 1, 1, 62, 119, 0, // Skip to: 86948 /* 56422 */ MCD_OPC_Decode, 210, 10, 141, 2, // Opcode: FMLSv4f32 /* 56427 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 56449 /* 56432 */ MCD_OPC_CheckPredicate, 3, 47, 119, 0, // Skip to: 86948 /* 56437 */ MCD_OPC_CheckField, 21, 1, 1, 40, 119, 0, // Skip to: 86948 /* 56444 */ MCD_OPC_Decode, 250, 24, 133, 2, // Opcode: SQDMULLv4i32_v2i64 /* 56449 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 56471 /* 56454 */ MCD_OPC_CheckPredicate, 3, 25, 119, 0, // Skip to: 86948 /* 56459 */ MCD_OPC_CheckField, 21, 1, 1, 18, 119, 0, // Skip to: 86948 /* 56466 */ MCD_OPC_Decode, 230, 12, 133, 2, // Opcode: FSUBv4f32 /* 56471 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 56509 /* 56476 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56479 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56494 /* 56484 */ MCD_OPC_CheckPredicate, 3, 251, 118, 0, // Skip to: 86948 /* 56489 */ MCD_OPC_Decode, 236, 6, 138, 2, // Opcode: FCMEQv4i32rz /* 56494 */ MCD_OPC_FilterValue, 33, 241, 118, 0, // Skip to: 86948 /* 56499 */ MCD_OPC_CheckPredicate, 3, 236, 118, 0, // Skip to: 86948 /* 56504 */ MCD_OPC_Decode, 205, 11, 138, 2, // Opcode: FRECPEv4f32 /* 56509 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 56531 /* 56514 */ MCD_OPC_CheckPredicate, 3, 221, 118, 0, // Skip to: 86948 /* 56519 */ MCD_OPC_CheckField, 16, 6, 32, 214, 118, 0, // Skip to: 86948 /* 56526 */ MCD_OPC_Decode, 188, 7, 138, 2, // Opcode: FCMLTv4i32rz /* 56531 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 56553 /* 56536 */ MCD_OPC_CheckPredicate, 3, 199, 118, 0, // Skip to: 86948 /* 56541 */ MCD_OPC_CheckField, 21, 1, 1, 192, 118, 0, // Skip to: 86948 /* 56548 */ MCD_OPC_Decode, 175, 10, 133, 2, // Opcode: FMINv4f32 /* 56553 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 56591 /* 56558 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56561 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56576 /* 56566 */ MCD_OPC_CheckPredicate, 3, 169, 118, 0, // Skip to: 86948 /* 56571 */ MCD_OPC_Decode, 148, 6, 138, 2, // Opcode: FABSv4f32 /* 56576 */ MCD_OPC_FilterValue, 48, 159, 118, 0, // Skip to: 86948 /* 56581 */ MCD_OPC_CheckPredicate, 4, 154, 118, 0, // Skip to: 86948 /* 56586 */ MCD_OPC_Decode, 165, 10, 152, 2, // Opcode: FMINVv8i16v /* 56591 */ MCD_OPC_FilterValue, 63, 144, 118, 0, // Skip to: 86948 /* 56596 */ MCD_OPC_CheckPredicate, 3, 139, 118, 0, // Skip to: 86948 /* 56601 */ MCD_OPC_CheckField, 21, 1, 1, 132, 118, 0, // Skip to: 86948 /* 56608 */ MCD_OPC_Decode, 193, 12, 133, 2, // Opcode: FRSQRTSv4f32 /* 56613 */ MCD_OPC_FilterValue, 3, 209, 5, 0, // Skip to: 58107 /* 56618 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 56621 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 56761 /* 56626 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 56629 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 56651 /* 56634 */ MCD_OPC_CheckPredicate, 3, 101, 118, 0, // Skip to: 86948 /* 56639 */ MCD_OPC_CheckField, 21, 1, 1, 94, 118, 0, // Skip to: 86948 /* 56646 */ MCD_OPC_Decode, 156, 31, 133, 2, // Opcode: UADDLv4i32_v2i64 /* 56651 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 56673 /* 56656 */ MCD_OPC_CheckPredicate, 3, 79, 118, 0, // Skip to: 86948 /* 56661 */ MCD_OPC_CheckField, 21, 1, 1, 72, 118, 0, // Skip to: 86948 /* 56668 */ MCD_OPC_Decode, 223, 31, 133, 2, // Opcode: UHADDv4i32 /* 56673 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 56695 /* 56678 */ MCD_OPC_CheckPredicate, 3, 57, 118, 0, // Skip to: 86948 /* 56683 */ MCD_OPC_CheckField, 21, 1, 1, 50, 118, 0, // Skip to: 86948 /* 56690 */ MCD_OPC_Decode, 219, 32, 133, 2, // Opcode: UQADDv4i32 /* 56695 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 56717 /* 56700 */ MCD_OPC_CheckPredicate, 3, 35, 118, 0, // Skip to: 86948 /* 56705 */ MCD_OPC_CheckField, 21, 1, 1, 28, 118, 0, // Skip to: 86948 /* 56712 */ MCD_OPC_Decode, 166, 31, 133, 2, // Opcode: UADDWv4i32_v2i64 /* 56717 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 56739 /* 56722 */ MCD_OPC_CheckPredicate, 3, 13, 118, 0, // Skip to: 86948 /* 56727 */ MCD_OPC_CheckField, 21, 1, 1, 6, 118, 0, // Skip to: 86948 /* 56734 */ MCD_OPC_Decode, 222, 33, 133, 2, // Opcode: URHADDv4i32 /* 56739 */ MCD_OPC_FilterValue, 7, 252, 117, 0, // Skip to: 86948 /* 56744 */ MCD_OPC_CheckPredicate, 3, 247, 117, 0, // Skip to: 86948 /* 56749 */ MCD_OPC_CheckField, 21, 1, 1, 240, 117, 0, // Skip to: 86948 /* 56756 */ MCD_OPC_Decode, 195, 2, 141, 2, // Opcode: BITv16i8 /* 56761 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 56992 /* 56766 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 56769 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 56791 /* 56774 */ MCD_OPC_CheckPredicate, 3, 217, 117, 0, // Skip to: 86948 /* 56779 */ MCD_OPC_CheckField, 21, 1, 1, 210, 117, 0, // Skip to: 86948 /* 56786 */ MCD_OPC_Decode, 167, 34, 133, 2, // Opcode: USUBLv4i32_v2i64 /* 56791 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 56813 /* 56796 */ MCD_OPC_CheckPredicate, 3, 195, 117, 0, // Skip to: 86948 /* 56801 */ MCD_OPC_CheckField, 21, 1, 1, 188, 117, 0, // Skip to: 86948 /* 56808 */ MCD_OPC_Decode, 229, 31, 133, 2, // Opcode: UHSUBv4i32 /* 56813 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 56851 /* 56818 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56821 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56836 /* 56826 */ MCD_OPC_CheckPredicate, 3, 165, 117, 0, // Skip to: 86948 /* 56831 */ MCD_OPC_Decode, 145, 31, 138, 2, // Opcode: UADDLPv4i32_v2i64 /* 56836 */ MCD_OPC_FilterValue, 33, 155, 117, 0, // Skip to: 86948 /* 56841 */ MCD_OPC_CheckPredicate, 3, 150, 117, 0, // Skip to: 86948 /* 56846 */ MCD_OPC_Decode, 180, 26, 147, 2, // Opcode: SQXTUNv4i32 /* 56851 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 56873 /* 56856 */ MCD_OPC_CheckPredicate, 3, 135, 117, 0, // Skip to: 86948 /* 56861 */ MCD_OPC_CheckField, 21, 1, 1, 128, 117, 0, // Skip to: 86948 /* 56868 */ MCD_OPC_Decode, 205, 33, 133, 2, // Opcode: UQSUBv4i32 /* 56873 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 56895 /* 56878 */ MCD_OPC_CheckPredicate, 3, 113, 117, 0, // Skip to: 86948 /* 56883 */ MCD_OPC_CheckField, 21, 1, 1, 106, 117, 0, // Skip to: 86948 /* 56890 */ MCD_OPC_Decode, 173, 34, 133, 2, // Opcode: USUBWv4i32_v2i64 /* 56895 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 56917 /* 56900 */ MCD_OPC_CheckPredicate, 3, 91, 117, 0, // Skip to: 86948 /* 56905 */ MCD_OPC_CheckField, 21, 1, 1, 84, 117, 0, // Skip to: 86948 /* 56912 */ MCD_OPC_Decode, 235, 3, 133, 2, // Opcode: CMHIv4i32 /* 56917 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 56970 /* 56922 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 56925 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56940 /* 56930 */ MCD_OPC_CheckPredicate, 3, 61, 117, 0, // Skip to: 86948 /* 56935 */ MCD_OPC_Decode, 153, 34, 147, 2, // Opcode: USQADDv4i32 /* 56940 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56955 /* 56945 */ MCD_OPC_CheckPredicate, 3, 46, 117, 0, // Skip to: 86948 /* 56950 */ MCD_OPC_Decode, 136, 23, 138, 2, // Opcode: SHLLv4i32 /* 56955 */ MCD_OPC_FilterValue, 48, 36, 117, 0, // Skip to: 86948 /* 56960 */ MCD_OPC_CheckPredicate, 3, 31, 117, 0, // Skip to: 86948 /* 56965 */ MCD_OPC_Decode, 150, 31, 244, 1, // Opcode: UADDLVv4i32v /* 56970 */ MCD_OPC_FilterValue, 7, 21, 117, 0, // Skip to: 86948 /* 56975 */ MCD_OPC_CheckPredicate, 3, 16, 117, 0, // Skip to: 86948 /* 56980 */ MCD_OPC_CheckField, 21, 1, 1, 9, 117, 0, // Skip to: 86948 /* 56987 */ MCD_OPC_Decode, 243, 3, 133, 2, // Opcode: CMHSv4i32 /* 56992 */ MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 57170 /* 56997 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 57000 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57022 /* 57005 */ MCD_OPC_CheckPredicate, 3, 242, 116, 0, // Skip to: 86948 /* 57010 */ MCD_OPC_CheckField, 21, 1, 1, 235, 116, 0, // Skip to: 86948 /* 57017 */ MCD_OPC_Decode, 178, 21, 141, 2, // Opcode: RADDHNv2i64_v4i32 /* 57022 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57044 /* 57027 */ MCD_OPC_CheckPredicate, 3, 220, 116, 0, // Skip to: 86948 /* 57032 */ MCD_OPC_CheckField, 21, 1, 1, 213, 116, 0, // Skip to: 86948 /* 57039 */ MCD_OPC_Decode, 134, 34, 133, 2, // Opcode: USHLv4i32 /* 57044 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 57082 /* 57049 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 57052 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57067 /* 57057 */ MCD_OPC_CheckPredicate, 3, 190, 116, 0, // Skip to: 86948 /* 57062 */ MCD_OPC_Decode, 179, 3, 138, 2, // Opcode: CLZv4i32 /* 57067 */ MCD_OPC_FilterValue, 33, 180, 116, 0, // Skip to: 86948 /* 57072 */ MCD_OPC_CheckPredicate, 3, 175, 116, 0, // Skip to: 86948 /* 57077 */ MCD_OPC_Decode, 214, 33, 147, 2, // Opcode: UQXTNv4i32 /* 57082 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57104 /* 57087 */ MCD_OPC_CheckPredicate, 3, 160, 116, 0, // Skip to: 86948 /* 57092 */ MCD_OPC_CheckField, 21, 1, 1, 153, 116, 0, // Skip to: 86948 /* 57099 */ MCD_OPC_Decode, 174, 33, 133, 2, // Opcode: UQSHLv4i32 /* 57104 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 57126 /* 57109 */ MCD_OPC_CheckPredicate, 3, 138, 116, 0, // Skip to: 86948 /* 57114 */ MCD_OPC_CheckField, 21, 1, 1, 131, 116, 0, // Skip to: 86948 /* 57121 */ MCD_OPC_Decode, 239, 30, 141, 2, // Opcode: UABALv4i32_v2i64 /* 57126 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57148 /* 57131 */ MCD_OPC_CheckPredicate, 3, 116, 116, 0, // Skip to: 86948 /* 57136 */ MCD_OPC_CheckField, 21, 1, 1, 109, 116, 0, // Skip to: 86948 /* 57143 */ MCD_OPC_Decode, 230, 33, 133, 2, // Opcode: URSHLv4i32 /* 57148 */ MCD_OPC_FilterValue, 7, 99, 116, 0, // Skip to: 86948 /* 57153 */ MCD_OPC_CheckPredicate, 3, 94, 116, 0, // Skip to: 86948 /* 57158 */ MCD_OPC_CheckField, 21, 1, 1, 87, 116, 0, // Skip to: 86948 /* 57165 */ MCD_OPC_Decode, 146, 33, 133, 2, // Opcode: UQRSHLv4i32 /* 57170 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 57354 /* 57175 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 57178 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57200 /* 57183 */ MCD_OPC_CheckPredicate, 3, 64, 116, 0, // Skip to: 86948 /* 57188 */ MCD_OPC_CheckField, 21, 1, 1, 57, 116, 0, // Skip to: 86948 /* 57195 */ MCD_OPC_Decode, 241, 21, 141, 2, // Opcode: RSUBHNv2i64_v4i32 /* 57200 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57222 /* 57205 */ MCD_OPC_CheckPredicate, 3, 42, 116, 0, // Skip to: 86948 /* 57210 */ MCD_OPC_CheckField, 21, 1, 1, 35, 116, 0, // Skip to: 86948 /* 57217 */ MCD_OPC_Decode, 131, 32, 133, 2, // Opcode: UMAXv4i32 /* 57222 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 57244 /* 57227 */ MCD_OPC_CheckPredicate, 3, 20, 116, 0, // Skip to: 86948 /* 57232 */ MCD_OPC_CheckField, 16, 6, 32, 13, 116, 0, // Skip to: 86948 /* 57239 */ MCD_OPC_Decode, 139, 31, 147, 2, // Opcode: UADALPv4i32_v2i64 /* 57244 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57266 /* 57249 */ MCD_OPC_CheckPredicate, 3, 254, 115, 0, // Skip to: 86948 /* 57254 */ MCD_OPC_CheckField, 21, 1, 1, 247, 115, 0, // Skip to: 86948 /* 57261 */ MCD_OPC_Decode, 160, 32, 133, 2, // Opcode: UMINv4i32 /* 57266 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 57288 /* 57271 */ MCD_OPC_CheckPredicate, 3, 232, 115, 0, // Skip to: 86948 /* 57276 */ MCD_OPC_CheckField, 21, 1, 1, 225, 115, 0, // Skip to: 86948 /* 57283 */ MCD_OPC_Decode, 251, 30, 133, 2, // Opcode: UABDLv4i32_v2i64 /* 57288 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57310 /* 57293 */ MCD_OPC_CheckPredicate, 3, 210, 115, 0, // Skip to: 86948 /* 57298 */ MCD_OPC_CheckField, 21, 1, 1, 203, 115, 0, // Skip to: 86948 /* 57305 */ MCD_OPC_Decode, 133, 31, 133, 2, // Opcode: UABDv4i32 /* 57310 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 57332 /* 57315 */ MCD_OPC_CheckPredicate, 3, 188, 115, 0, // Skip to: 86948 /* 57320 */ MCD_OPC_CheckField, 16, 6, 32, 181, 115, 0, // Skip to: 86948 /* 57327 */ MCD_OPC_Decode, 155, 25, 138, 2, // Opcode: SQNEGv4i32 /* 57332 */ MCD_OPC_FilterValue, 7, 171, 115, 0, // Skip to: 86948 /* 57337 */ MCD_OPC_CheckPredicate, 3, 166, 115, 0, // Skip to: 86948 /* 57342 */ MCD_OPC_CheckField, 21, 1, 1, 159, 115, 0, // Skip to: 86948 /* 57349 */ MCD_OPC_Decode, 245, 30, 141, 2, // Opcode: UABAv4i32 /* 57354 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 57558 /* 57359 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 57362 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57384 /* 57367 */ MCD_OPC_CheckPredicate, 3, 136, 115, 0, // Skip to: 86948 /* 57372 */ MCD_OPC_CheckField, 21, 1, 1, 129, 115, 0, // Skip to: 86948 /* 57379 */ MCD_OPC_Decode, 169, 32, 141, 2, // Opcode: UMLALv4i32_v2i64 /* 57384 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 57422 /* 57389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 57392 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57407 /* 57397 */ MCD_OPC_CheckPredicate, 7, 106, 115, 0, // Skip to: 86948 /* 57402 */ MCD_OPC_Decode, 166, 25, 141, 2, // Opcode: SQRDMLAHv4i32 /* 57407 */ MCD_OPC_FilterValue, 1, 96, 115, 0, // Skip to: 86948 /* 57412 */ MCD_OPC_CheckPredicate, 3, 91, 115, 0, // Skip to: 86948 /* 57417 */ MCD_OPC_Decode, 132, 30, 133, 2, // Opcode: SUBv4i32 /* 57422 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 57444 /* 57427 */ MCD_OPC_CheckPredicate, 3, 76, 115, 0, // Skip to: 86948 /* 57432 */ MCD_OPC_CheckField, 16, 6, 32, 69, 115, 0, // Skip to: 86948 /* 57439 */ MCD_OPC_Decode, 209, 3, 138, 2, // Opcode: CMGEv4i32rz /* 57444 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 57482 /* 57449 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 57452 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57467 /* 57457 */ MCD_OPC_CheckPredicate, 7, 46, 115, 0, // Skip to: 86948 /* 57462 */ MCD_OPC_Decode, 178, 25, 141, 2, // Opcode: SQRDMLSHv4i32 /* 57467 */ MCD_OPC_FilterValue, 1, 36, 115, 0, // Skip to: 86948 /* 57472 */ MCD_OPC_CheckPredicate, 3, 31, 115, 0, // Skip to: 86948 /* 57477 */ MCD_OPC_Decode, 192, 3, 133, 2, // Opcode: CMEQv4i32 /* 57482 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 57520 /* 57487 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 57490 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57505 /* 57495 */ MCD_OPC_CheckPredicate, 10, 8, 115, 0, // Skip to: 86948 /* 57500 */ MCD_OPC_Decode, 218, 31, 141, 2, // Opcode: UDOTv16i8 /* 57505 */ MCD_OPC_FilterValue, 1, 254, 114, 0, // Skip to: 86948 /* 57510 */ MCD_OPC_CheckPredicate, 3, 249, 114, 0, // Skip to: 86948 /* 57515 */ MCD_OPC_Decode, 228, 19, 141, 2, // Opcode: MLSv4i32 /* 57520 */ MCD_OPC_FilterValue, 6, 239, 114, 0, // Skip to: 86948 /* 57525 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 57528 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57543 /* 57533 */ MCD_OPC_CheckPredicate, 3, 226, 114, 0, // Skip to: 86948 /* 57538 */ MCD_OPC_Decode, 251, 3, 138, 2, // Opcode: CMLEv4i32rz /* 57543 */ MCD_OPC_FilterValue, 33, 216, 114, 0, // Skip to: 86948 /* 57548 */ MCD_OPC_CheckPredicate, 3, 211, 114, 0, // Skip to: 86948 /* 57553 */ MCD_OPC_Decode, 244, 11, 138, 2, // Opcode: FRINTIv4f32 /* 57558 */ MCD_OPC_FilterValue, 5, 182, 0, 0, // Skip to: 57745 /* 57563 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 57566 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57588 /* 57571 */ MCD_OPC_CheckPredicate, 3, 188, 114, 0, // Skip to: 86948 /* 57576 */ MCD_OPC_CheckField, 21, 1, 1, 181, 114, 0, // Skip to: 86948 /* 57583 */ MCD_OPC_Decode, 179, 32, 141, 2, // Opcode: UMLSLv4i32_v2i64 /* 57588 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57610 /* 57593 */ MCD_OPC_CheckPredicate, 3, 166, 114, 0, // Skip to: 86948 /* 57598 */ MCD_OPC_CheckField, 21, 1, 1, 159, 114, 0, // Skip to: 86948 /* 57605 */ MCD_OPC_Decode, 236, 31, 133, 2, // Opcode: UMAXPv4i32 /* 57610 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 57663 /* 57615 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 57618 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 57633 /* 57623 */ MCD_OPC_CheckPredicate, 3, 136, 114, 0, // Skip to: 86948 /* 57628 */ MCD_OPC_Decode, 211, 8, 138, 2, // Opcode: FCVTPUv4f32 /* 57633 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 57648 /* 57638 */ MCD_OPC_CheckPredicate, 3, 121, 114, 0, // Skip to: 86948 /* 57643 */ MCD_OPC_Decode, 245, 31, 160, 2, // Opcode: UMAXVv4i32v /* 57648 */ MCD_OPC_FilterValue, 49, 111, 114, 0, // Skip to: 86948 /* 57653 */ MCD_OPC_CheckPredicate, 3, 106, 114, 0, // Skip to: 86948 /* 57658 */ MCD_OPC_Decode, 146, 32, 160, 2, // Opcode: UMINVv4i32v /* 57663 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57685 /* 57668 */ MCD_OPC_CheckPredicate, 3, 91, 114, 0, // Skip to: 86948 /* 57673 */ MCD_OPC_CheckField, 21, 1, 1, 84, 114, 0, // Skip to: 86948 /* 57680 */ MCD_OPC_Decode, 137, 32, 133, 2, // Opcode: UMINPv4i32 /* 57685 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57707 /* 57690 */ MCD_OPC_CheckPredicate, 3, 69, 114, 0, // Skip to: 86948 /* 57695 */ MCD_OPC_CheckField, 21, 1, 1, 62, 114, 0, // Skip to: 86948 /* 57702 */ MCD_OPC_Decode, 190, 25, 133, 2, // Opcode: SQRDMULHv4i32 /* 57707 */ MCD_OPC_FilterValue, 6, 52, 114, 0, // Skip to: 86948 /* 57712 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 57715 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57730 /* 57720 */ MCD_OPC_CheckPredicate, 3, 39, 114, 0, // Skip to: 86948 /* 57725 */ MCD_OPC_Decode, 184, 20, 138, 2, // Opcode: NEGv4i32 /* 57730 */ MCD_OPC_FilterValue, 33, 29, 114, 0, // Skip to: 86948 /* 57735 */ MCD_OPC_CheckPredicate, 3, 24, 114, 0, // Skip to: 86948 /* 57740 */ MCD_OPC_Decode, 155, 9, 138, 2, // Opcode: FCVTZUv4f32 /* 57745 */ MCD_OPC_FilterValue, 6, 185, 0, 0, // Skip to: 57935 /* 57750 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 57753 */ MCD_OPC_FilterValue, 0, 116, 0, 0, // Skip to: 57874 /* 57758 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 57761 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57783 /* 57766 */ MCD_OPC_CheckPredicate, 3, 249, 113, 0, // Skip to: 86948 /* 57771 */ MCD_OPC_CheckField, 21, 1, 1, 242, 113, 0, // Skip to: 86948 /* 57778 */ MCD_OPC_Decode, 199, 32, 133, 2, // Opcode: UMULLv4i32_v2i64 /* 57783 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 57836 /* 57788 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 57791 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57806 /* 57796 */ MCD_OPC_CheckPredicate, 3, 219, 113, 0, // Skip to: 86948 /* 57801 */ MCD_OPC_Decode, 130, 7, 138, 2, // Opcode: FCMGEv4i32rz /* 57806 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 57821 /* 57811 */ MCD_OPC_CheckPredicate, 3, 204, 113, 0, // Skip to: 86948 /* 57816 */ MCD_OPC_Decode, 242, 33, 138, 2, // Opcode: URSQRTEv4i32 /* 57821 */ MCD_OPC_FilterValue, 48, 194, 113, 0, // Skip to: 86948 /* 57826 */ MCD_OPC_CheckPredicate, 3, 189, 113, 0, // Skip to: 86948 /* 57831 */ MCD_OPC_Decode, 138, 10, 160, 2, // Opcode: FMINNMVv4i32v /* 57836 */ MCD_OPC_FilterValue, 3, 179, 113, 0, // Skip to: 86948 /* 57841 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 57844 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57859 /* 57849 */ MCD_OPC_CheckPredicate, 3, 166, 113, 0, // Skip to: 86948 /* 57854 */ MCD_OPC_Decode, 177, 7, 138, 2, // Opcode: FCMLEv4i32rz /* 57859 */ MCD_OPC_FilterValue, 33, 156, 113, 0, // Skip to: 86948 /* 57864 */ MCD_OPC_CheckPredicate, 3, 151, 113, 0, // Skip to: 86948 /* 57869 */ MCD_OPC_Decode, 182, 12, 138, 2, // Opcode: FRSQRTEv4f32 /* 57874 */ MCD_OPC_FilterValue, 1, 141, 113, 0, // Skip to: 86948 /* 57879 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 57882 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57897 /* 57887 */ MCD_OPC_CheckPredicate, 11, 128, 113, 0, // Skip to: 86948 /* 57892 */ MCD_OPC_Decode, 164, 7, 169, 2, // Opcode: FCMLAv4f32 /* 57897 */ MCD_OPC_FilterValue, 1, 118, 113, 0, // Skip to: 86948 /* 57902 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 57905 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57920 /* 57910 */ MCD_OPC_CheckPredicate, 3, 105, 113, 0, // Skip to: 86948 /* 57915 */ MCD_OPC_Decode, 131, 10, 133, 2, // Opcode: FMINNMPv4f32 /* 57920 */ MCD_OPC_FilterValue, 2, 95, 113, 0, // Skip to: 86948 /* 57925 */ MCD_OPC_CheckPredicate, 3, 90, 113, 0, // Skip to: 86948 /* 57930 */ MCD_OPC_Decode, 137, 6, 133, 2, // Opcode: FABDv4f32 /* 57935 */ MCD_OPC_FilterValue, 7, 80, 113, 0, // Skip to: 86948 /* 57940 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 57943 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 58004 /* 57948 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 57951 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57966 /* 57956 */ MCD_OPC_CheckPredicate, 11, 59, 113, 0, // Skip to: 86948 /* 57961 */ MCD_OPC_Decode, 209, 6, 170, 2, // Opcode: FCADDv4f32 /* 57966 */ MCD_OPC_FilterValue, 1, 49, 113, 0, // Skip to: 86948 /* 57971 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 57974 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57989 /* 57979 */ MCD_OPC_CheckPredicate, 3, 36, 113, 0, // Skip to: 86948 /* 57984 */ MCD_OPC_Decode, 150, 7, 133, 2, // Opcode: FCMGTv4f32 /* 57989 */ MCD_OPC_FilterValue, 1, 26, 113, 0, // Skip to: 86948 /* 57994 */ MCD_OPC_CheckPredicate, 3, 21, 113, 0, // Skip to: 86948 /* 57999 */ MCD_OPC_Decode, 157, 10, 133, 2, // Opcode: FMINPv4f32 /* 58004 */ MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 58078 /* 58009 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 58012 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 58034 /* 58017 */ MCD_OPC_CheckPredicate, 3, 254, 112, 0, // Skip to: 86948 /* 58022 */ MCD_OPC_CheckField, 12, 1, 1, 247, 112, 0, // Skip to: 86948 /* 58029 */ MCD_OPC_Decode, 173, 11, 138, 2, // Opcode: FNEGv4f32 /* 58034 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 58056 /* 58039 */ MCD_OPC_CheckPredicate, 3, 232, 112, 0, // Skip to: 86948 /* 58044 */ MCD_OPC_CheckField, 12, 1, 1, 225, 112, 0, // Skip to: 86948 /* 58051 */ MCD_OPC_Decode, 207, 12, 138, 2, // Opcode: FSQRTv4f32 /* 58056 */ MCD_OPC_FilterValue, 48, 215, 112, 0, // Skip to: 86948 /* 58061 */ MCD_OPC_CheckPredicate, 3, 210, 112, 0, // Skip to: 86948 /* 58066 */ MCD_OPC_CheckField, 12, 1, 1, 203, 112, 0, // Skip to: 86948 /* 58073 */ MCD_OPC_Decode, 164, 10, 160, 2, // Opcode: FMINVv4i32v /* 58078 */ MCD_OPC_FilterValue, 3, 193, 112, 0, // Skip to: 86948 /* 58083 */ MCD_OPC_CheckPredicate, 3, 188, 112, 0, // Skip to: 86948 /* 58088 */ MCD_OPC_CheckField, 21, 1, 1, 181, 112, 0, // Skip to: 86948 /* 58095 */ MCD_OPC_CheckField, 12, 1, 0, 174, 112, 0, // Skip to: 86948 /* 58102 */ MCD_OPC_Decode, 170, 6, 133, 2, // Opcode: FACGTv4f32 /* 58107 */ MCD_OPC_FilterValue, 6, 164, 112, 0, // Skip to: 86948 /* 58112 */ MCD_OPC_CheckPredicate, 6, 159, 112, 0, // Skip to: 86948 /* 58117 */ MCD_OPC_CheckField, 21, 1, 0, 152, 112, 0, // Skip to: 86948 /* 58124 */ MCD_OPC_Decode, 251, 34, 172, 2, // Opcode: XAR /* 58129 */ MCD_OPC_FilterValue, 11, 14, 12, 0, // Skip to: 61220 /* 58134 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 58137 */ MCD_OPC_FilterValue, 0, 154, 1, 0, // Skip to: 58552 /* 58142 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 58145 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 58241 /* 58150 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58153 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58175 /* 58158 */ MCD_OPC_CheckPredicate, 4, 113, 112, 0, // Skip to: 86948 /* 58163 */ MCD_OPC_CheckField, 21, 1, 0, 106, 112, 0, // Skip to: 86948 /* 58170 */ MCD_OPC_Decode, 148, 10, 238, 1, // Opcode: FMINNMv4f16 /* 58175 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58197 /* 58180 */ MCD_OPC_CheckPredicate, 4, 91, 112, 0, // Skip to: 86948 /* 58185 */ MCD_OPC_CheckField, 21, 1, 0, 84, 112, 0, // Skip to: 86948 /* 58192 */ MCD_OPC_Decode, 130, 10, 238, 1, // Opcode: FMINNMPv4f16 /* 58197 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58219 /* 58202 */ MCD_OPC_CheckPredicate, 4, 69, 112, 0, // Skip to: 86948 /* 58207 */ MCD_OPC_CheckField, 21, 1, 0, 62, 112, 0, // Skip to: 86948 /* 58214 */ MCD_OPC_Decode, 150, 10, 133, 2, // Opcode: FMINNMv8f16 /* 58219 */ MCD_OPC_FilterValue, 3, 52, 112, 0, // Skip to: 86948 /* 58224 */ MCD_OPC_CheckPredicate, 4, 47, 112, 0, // Skip to: 86948 /* 58229 */ MCD_OPC_CheckField, 21, 1, 0, 40, 112, 0, // Skip to: 86948 /* 58236 */ MCD_OPC_Decode, 132, 10, 133, 2, // Opcode: FMINNMPv8f16 /* 58241 */ MCD_OPC_FilterValue, 3, 85, 0, 0, // Skip to: 58331 /* 58246 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58249 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58271 /* 58254 */ MCD_OPC_CheckPredicate, 4, 17, 112, 0, // Skip to: 86948 /* 58259 */ MCD_OPC_CheckField, 21, 1, 0, 10, 112, 0, // Skip to: 86948 /* 58266 */ MCD_OPC_Decode, 209, 10, 130, 2, // Opcode: FMLSv4f16 /* 58271 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 58309 /* 58276 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 58279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58294 /* 58284 */ MCD_OPC_CheckPredicate, 4, 243, 111, 0, // Skip to: 86948 /* 58289 */ MCD_OPC_Decode, 213, 10, 141, 2, // Opcode: FMLSv8f16 /* 58294 */ MCD_OPC_FilterValue, 1, 233, 111, 0, // Skip to: 86948 /* 58299 */ MCD_OPC_CheckPredicate, 3, 228, 111, 0, // Skip to: 86948 /* 58304 */ MCD_OPC_Decode, 178, 24, 133, 2, // Opcode: SQADDv2i64 /* 58309 */ MCD_OPC_FilterValue, 3, 218, 111, 0, // Skip to: 86948 /* 58314 */ MCD_OPC_CheckPredicate, 3, 213, 111, 0, // Skip to: 86948 /* 58319 */ MCD_OPC_CheckField, 21, 1, 1, 206, 111, 0, // Skip to: 86948 /* 58326 */ MCD_OPC_Decode, 217, 32, 133, 2, // Opcode: UQADDv2i64 /* 58331 */ MCD_OPC_FilterValue, 5, 91, 0, 0, // Skip to: 58427 /* 58336 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58339 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58361 /* 58344 */ MCD_OPC_CheckPredicate, 4, 183, 111, 0, // Skip to: 86948 /* 58349 */ MCD_OPC_CheckField, 21, 1, 0, 176, 111, 0, // Skip to: 86948 /* 58356 */ MCD_OPC_Decode, 229, 12, 238, 1, // Opcode: FSUBv4f16 /* 58361 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58383 /* 58366 */ MCD_OPC_CheckPredicate, 4, 161, 111, 0, // Skip to: 86948 /* 58371 */ MCD_OPC_CheckField, 21, 1, 0, 154, 111, 0, // Skip to: 86948 /* 58378 */ MCD_OPC_Decode, 136, 6, 238, 1, // Opcode: FABDv4f16 /* 58383 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58405 /* 58388 */ MCD_OPC_CheckPredicate, 4, 139, 111, 0, // Skip to: 86948 /* 58393 */ MCD_OPC_CheckField, 21, 1, 0, 132, 111, 0, // Skip to: 86948 /* 58400 */ MCD_OPC_Decode, 231, 12, 133, 2, // Opcode: FSUBv8f16 /* 58405 */ MCD_OPC_FilterValue, 3, 122, 111, 0, // Skip to: 86948 /* 58410 */ MCD_OPC_CheckPredicate, 4, 117, 111, 0, // Skip to: 86948 /* 58415 */ MCD_OPC_CheckField, 21, 1, 0, 110, 111, 0, // Skip to: 86948 /* 58422 */ MCD_OPC_Decode, 138, 6, 133, 2, // Opcode: FABDv8f16 /* 58427 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 58456 /* 58432 */ MCD_OPC_CheckPredicate, 3, 95, 111, 0, // Skip to: 86948 /* 58437 */ MCD_OPC_CheckField, 29, 3, 2, 88, 111, 0, // Skip to: 86948 /* 58444 */ MCD_OPC_CheckField, 21, 1, 0, 81, 111, 0, // Skip to: 86948 /* 58451 */ MCD_OPC_Decode, 198, 34, 133, 2, // Opcode: UZP1v2i64 /* 58456 */ MCD_OPC_FilterValue, 7, 71, 111, 0, // Skip to: 86948 /* 58461 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58464 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58486 /* 58469 */ MCD_OPC_CheckPredicate, 3, 58, 111, 0, // Skip to: 86948 /* 58474 */ MCD_OPC_CheckField, 21, 1, 1, 51, 111, 0, // Skip to: 86948 /* 58481 */ MCD_OPC_Decode, 202, 20, 238, 1, // Opcode: ORNv8i8 /* 58486 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58508 /* 58491 */ MCD_OPC_CheckPredicate, 3, 36, 111, 0, // Skip to: 86948 /* 58496 */ MCD_OPC_CheckField, 21, 1, 1, 29, 111, 0, // Skip to: 86948 /* 58503 */ MCD_OPC_Decode, 194, 2, 238, 1, // Opcode: BIFv8i8 /* 58508 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58530 /* 58513 */ MCD_OPC_CheckPredicate, 3, 14, 111, 0, // Skip to: 86948 /* 58518 */ MCD_OPC_CheckField, 21, 1, 1, 7, 111, 0, // Skip to: 86948 /* 58525 */ MCD_OPC_Decode, 201, 20, 133, 2, // Opcode: ORNv16i8 /* 58530 */ MCD_OPC_FilterValue, 3, 253, 110, 0, // Skip to: 86948 /* 58535 */ MCD_OPC_CheckPredicate, 3, 248, 110, 0, // Skip to: 86948 /* 58540 */ MCD_OPC_CheckField, 21, 1, 1, 241, 110, 0, // Skip to: 86948 /* 58547 */ MCD_OPC_Decode, 193, 2, 133, 2, // Opcode: BIFv16i8 /* 58552 */ MCD_OPC_FilterValue, 1, 218, 1, 0, // Skip to: 59031 /* 58557 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 58560 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 58612 /* 58565 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58568 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58590 /* 58573 */ MCD_OPC_CheckPredicate, 4, 210, 110, 0, // Skip to: 86948 /* 58578 */ MCD_OPC_CheckField, 21, 1, 0, 203, 110, 0, // Skip to: 86948 /* 58585 */ MCD_OPC_Decode, 149, 7, 238, 1, // Opcode: FCMGTv4f16 /* 58590 */ MCD_OPC_FilterValue, 3, 193, 110, 0, // Skip to: 86948 /* 58595 */ MCD_OPC_CheckPredicate, 4, 188, 110, 0, // Skip to: 86948 /* 58600 */ MCD_OPC_CheckField, 21, 1, 0, 181, 110, 0, // Skip to: 86948 /* 58607 */ MCD_OPC_Decode, 153, 7, 133, 2, // Opcode: FCMGTv8f16 /* 58612 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 58641 /* 58617 */ MCD_OPC_CheckPredicate, 3, 166, 110, 0, // Skip to: 86948 /* 58622 */ MCD_OPC_CheckField, 29, 3, 2, 159, 110, 0, // Skip to: 86948 /* 58629 */ MCD_OPC_CheckField, 21, 1, 0, 152, 110, 0, // Skip to: 86948 /* 58636 */ MCD_OPC_Decode, 215, 30, 133, 2, // Opcode: TRN1v2i64 /* 58641 */ MCD_OPC_FilterValue, 3, 85, 0, 0, // Skip to: 58731 /* 58646 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58649 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58671 /* 58654 */ MCD_OPC_CheckPredicate, 4, 129, 110, 0, // Skip to: 86948 /* 58659 */ MCD_OPC_CheckField, 21, 1, 0, 122, 110, 0, // Skip to: 86948 /* 58666 */ MCD_OPC_Decode, 169, 6, 238, 1, // Opcode: FACGTv4f16 /* 58671 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58693 /* 58676 */ MCD_OPC_CheckPredicate, 3, 107, 110, 0, // Skip to: 86948 /* 58681 */ MCD_OPC_CheckField, 21, 1, 1, 100, 110, 0, // Skip to: 86948 /* 58688 */ MCD_OPC_Decode, 160, 26, 133, 2, // Opcode: SQSUBv2i64 /* 58693 */ MCD_OPC_FilterValue, 3, 90, 110, 0, // Skip to: 86948 /* 58698 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 58701 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58716 /* 58706 */ MCD_OPC_CheckPredicate, 4, 77, 110, 0, // Skip to: 86948 /* 58711 */ MCD_OPC_Decode, 171, 6, 133, 2, // Opcode: FACGTv8f16 /* 58716 */ MCD_OPC_FilterValue, 1, 67, 110, 0, // Skip to: 86948 /* 58721 */ MCD_OPC_CheckPredicate, 3, 62, 110, 0, // Skip to: 86948 /* 58726 */ MCD_OPC_Decode, 203, 33, 133, 2, // Opcode: UQSUBv2i64 /* 58731 */ MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 58859 /* 58736 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58739 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58761 /* 58744 */ MCD_OPC_CheckPredicate, 4, 39, 110, 0, // Skip to: 86948 /* 58749 */ MCD_OPC_CheckField, 21, 1, 0, 32, 110, 0, // Skip to: 86948 /* 58756 */ MCD_OPC_Decode, 174, 10, 238, 1, // Opcode: FMINv4f16 /* 58761 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58783 /* 58766 */ MCD_OPC_CheckPredicate, 4, 17, 110, 0, // Skip to: 86948 /* 58771 */ MCD_OPC_CheckField, 21, 1, 0, 10, 110, 0, // Skip to: 86948 /* 58778 */ MCD_OPC_Decode, 156, 10, 238, 1, // Opcode: FMINPv4f16 /* 58783 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 58821 /* 58788 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 58791 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58806 /* 58796 */ MCD_OPC_CheckPredicate, 4, 243, 109, 0, // Skip to: 86948 /* 58801 */ MCD_OPC_Decode, 176, 10, 133, 2, // Opcode: FMINv8f16 /* 58806 */ MCD_OPC_FilterValue, 1, 233, 109, 0, // Skip to: 86948 /* 58811 */ MCD_OPC_CheckPredicate, 3, 228, 109, 0, // Skip to: 86948 /* 58816 */ MCD_OPC_Decode, 220, 3, 133, 2, // Opcode: CMGTv2i64 /* 58821 */ MCD_OPC_FilterValue, 3, 218, 109, 0, // Skip to: 86948 /* 58826 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 58829 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58844 /* 58834 */ MCD_OPC_CheckPredicate, 4, 205, 109, 0, // Skip to: 86948 /* 58839 */ MCD_OPC_Decode, 158, 10, 133, 2, // Opcode: FMINPv8f16 /* 58844 */ MCD_OPC_FilterValue, 1, 195, 109, 0, // Skip to: 86948 /* 58849 */ MCD_OPC_CheckPredicate, 3, 190, 109, 0, // Skip to: 86948 /* 58854 */ MCD_OPC_Decode, 233, 3, 133, 2, // Opcode: CMHIv2i64 /* 58859 */ MCD_OPC_FilterValue, 6, 77, 0, 0, // Skip to: 58941 /* 58864 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 58867 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58889 /* 58872 */ MCD_OPC_CheckPredicate, 3, 167, 109, 0, // Skip to: 86948 /* 58877 */ MCD_OPC_CheckField, 29, 3, 2, 160, 109, 0, // Skip to: 86948 /* 58884 */ MCD_OPC_Decode, 143, 35, 133, 2, // Opcode: ZIP1v2i64 /* 58889 */ MCD_OPC_FilterValue, 1, 150, 109, 0, // Skip to: 86948 /* 58894 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58897 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58919 /* 58902 */ MCD_OPC_CheckPredicate, 3, 137, 109, 0, // Skip to: 86948 /* 58907 */ MCD_OPC_CheckField, 16, 5, 0, 130, 109, 0, // Skip to: 86948 /* 58914 */ MCD_OPC_Decode, 147, 30, 147, 2, // Opcode: SUQADDv2i64 /* 58919 */ MCD_OPC_FilterValue, 3, 120, 109, 0, // Skip to: 86948 /* 58924 */ MCD_OPC_CheckPredicate, 3, 115, 109, 0, // Skip to: 86948 /* 58929 */ MCD_OPC_CheckField, 16, 5, 0, 108, 109, 0, // Skip to: 86948 /* 58936 */ MCD_OPC_Decode, 151, 34, 147, 2, // Opcode: USQADDv2i64 /* 58941 */ MCD_OPC_FilterValue, 7, 98, 109, 0, // Skip to: 86948 /* 58946 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 58949 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58971 /* 58954 */ MCD_OPC_CheckPredicate, 4, 85, 109, 0, // Skip to: 86948 /* 58959 */ MCD_OPC_CheckField, 21, 1, 0, 78, 109, 0, // Skip to: 86948 /* 58966 */ MCD_OPC_Decode, 192, 12, 238, 1, // Opcode: FRSQRTSv4f16 /* 58971 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 59009 /* 58976 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 58979 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58994 /* 58984 */ MCD_OPC_CheckPredicate, 4, 55, 109, 0, // Skip to: 86948 /* 58989 */ MCD_OPC_Decode, 194, 12, 133, 2, // Opcode: FRSQRTSv8f16 /* 58994 */ MCD_OPC_FilterValue, 1, 45, 109, 0, // Skip to: 86948 /* 58999 */ MCD_OPC_CheckPredicate, 3, 40, 109, 0, // Skip to: 86948 /* 59004 */ MCD_OPC_Decode, 204, 3, 133, 2, // Opcode: CMGEv2i64 /* 59009 */ MCD_OPC_FilterValue, 3, 30, 109, 0, // Skip to: 86948 /* 59014 */ MCD_OPC_CheckPredicate, 3, 25, 109, 0, // Skip to: 86948 /* 59019 */ MCD_OPC_CheckField, 21, 1, 1, 18, 109, 0, // Skip to: 86948 /* 59026 */ MCD_OPC_Decode, 241, 3, 133, 2, // Opcode: CMHSv2i64 /* 59031 */ MCD_OPC_FilterValue, 2, 240, 0, 0, // Skip to: 59276 /* 59036 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 59039 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 59091 /* 59044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59047 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59069 /* 59052 */ MCD_OPC_CheckPredicate, 3, 243, 108, 0, // Skip to: 86948 /* 59057 */ MCD_OPC_CheckField, 21, 1, 1, 236, 108, 0, // Skip to: 86948 /* 59064 */ MCD_OPC_Decode, 230, 26, 133, 2, // Opcode: SSHLv2i64 /* 59069 */ MCD_OPC_FilterValue, 3, 226, 108, 0, // Skip to: 86948 /* 59074 */ MCD_OPC_CheckPredicate, 3, 221, 108, 0, // Skip to: 86948 /* 59079 */ MCD_OPC_CheckField, 21, 1, 1, 214, 108, 0, // Skip to: 86948 /* 59086 */ MCD_OPC_Decode, 132, 34, 133, 2, // Opcode: USHLv2i64 /* 59091 */ MCD_OPC_FilterValue, 3, 47, 0, 0, // Skip to: 59143 /* 59096 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59099 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59121 /* 59104 */ MCD_OPC_CheckPredicate, 3, 191, 108, 0, // Skip to: 86948 /* 59109 */ MCD_OPC_CheckField, 21, 1, 1, 184, 108, 0, // Skip to: 86948 /* 59116 */ MCD_OPC_Decode, 246, 25, 133, 2, // Opcode: SQSHLv2i64 /* 59121 */ MCD_OPC_FilterValue, 3, 174, 108, 0, // Skip to: 86948 /* 59126 */ MCD_OPC_CheckPredicate, 3, 169, 108, 0, // Skip to: 86948 /* 59131 */ MCD_OPC_CheckField, 21, 1, 1, 162, 108, 0, // Skip to: 86948 /* 59138 */ MCD_OPC_Decode, 170, 33, 133, 2, // Opcode: UQSHLv2i64 /* 59143 */ MCD_OPC_FilterValue, 5, 47, 0, 0, // Skip to: 59195 /* 59148 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59151 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59173 /* 59156 */ MCD_OPC_CheckPredicate, 3, 139, 108, 0, // Skip to: 86948 /* 59161 */ MCD_OPC_CheckField, 21, 1, 1, 132, 108, 0, // Skip to: 86948 /* 59168 */ MCD_OPC_Decode, 200, 26, 133, 2, // Opcode: SRSHLv2i64 /* 59173 */ MCD_OPC_FilterValue, 3, 122, 108, 0, // Skip to: 86948 /* 59178 */ MCD_OPC_CheckPredicate, 3, 117, 108, 0, // Skip to: 86948 /* 59183 */ MCD_OPC_CheckField, 21, 1, 1, 110, 108, 0, // Skip to: 86948 /* 59190 */ MCD_OPC_Decode, 228, 33, 133, 2, // Opcode: URSHLv2i64 /* 59195 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 59224 /* 59200 */ MCD_OPC_CheckPredicate, 3, 95, 108, 0, // Skip to: 86948 /* 59205 */ MCD_OPC_CheckField, 29, 3, 2, 88, 108, 0, // Skip to: 86948 /* 59212 */ MCD_OPC_CheckField, 21, 1, 0, 81, 108, 0, // Skip to: 86948 /* 59219 */ MCD_OPC_Decode, 213, 34, 133, 2, // Opcode: UZP2v2i64 /* 59224 */ MCD_OPC_FilterValue, 7, 71, 108, 0, // Skip to: 86948 /* 59229 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59232 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59254 /* 59237 */ MCD_OPC_CheckPredicate, 3, 58, 108, 0, // Skip to: 86948 /* 59242 */ MCD_OPC_CheckField, 21, 1, 1, 51, 108, 0, // Skip to: 86948 /* 59249 */ MCD_OPC_Decode, 200, 25, 133, 2, // Opcode: SQRSHLv2i64 /* 59254 */ MCD_OPC_FilterValue, 3, 41, 108, 0, // Skip to: 86948 /* 59259 */ MCD_OPC_CheckPredicate, 3, 36, 108, 0, // Skip to: 86948 /* 59264 */ MCD_OPC_CheckField, 21, 1, 1, 29, 108, 0, // Skip to: 86948 /* 59271 */ MCD_OPC_Decode, 144, 33, 133, 2, // Opcode: UQRSHLv2i64 /* 59276 */ MCD_OPC_FilterValue, 3, 114, 0, 0, // Skip to: 59395 /* 59281 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 59284 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 59313 /* 59289 */ MCD_OPC_CheckPredicate, 3, 6, 108, 0, // Skip to: 86948 /* 59294 */ MCD_OPC_CheckField, 29, 3, 2, 255, 107, 0, // Skip to: 86948 /* 59301 */ MCD_OPC_CheckField, 21, 1, 0, 248, 107, 0, // Skip to: 86948 /* 59308 */ MCD_OPC_Decode, 230, 30, 133, 2, // Opcode: TRN2v2i64 /* 59313 */ MCD_OPC_FilterValue, 6, 238, 107, 0, // Skip to: 86948 /* 59318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 59321 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 59343 /* 59326 */ MCD_OPC_CheckPredicate, 3, 225, 107, 0, // Skip to: 86948 /* 59331 */ MCD_OPC_CheckField, 29, 3, 2, 218, 107, 0, // Skip to: 86948 /* 59338 */ MCD_OPC_Decode, 158, 35, 133, 2, // Opcode: ZIP2v2i64 /* 59343 */ MCD_OPC_FilterValue, 1, 208, 107, 0, // Skip to: 86948 /* 59348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59351 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59373 /* 59356 */ MCD_OPC_CheckPredicate, 3, 195, 107, 0, // Skip to: 86948 /* 59361 */ MCD_OPC_CheckField, 16, 5, 0, 188, 107, 0, // Skip to: 86948 /* 59368 */ MCD_OPC_Decode, 159, 24, 138, 2, // Opcode: SQABSv2i64 /* 59373 */ MCD_OPC_FilterValue, 3, 178, 107, 0, // Skip to: 86948 /* 59378 */ MCD_OPC_CheckPredicate, 3, 173, 107, 0, // Skip to: 86948 /* 59383 */ MCD_OPC_CheckField, 16, 5, 0, 166, 107, 0, // Skip to: 86948 /* 59390 */ MCD_OPC_Decode, 153, 25, 138, 2, // Opcode: SQNEGv2i64 /* 59395 */ MCD_OPC_FilterValue, 4, 166, 1, 0, // Skip to: 59822 /* 59400 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 59403 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 59432 /* 59408 */ MCD_OPC_CheckPredicate, 6, 143, 107, 0, // Skip to: 86948 /* 59413 */ MCD_OPC_CheckField, 29, 3, 6, 136, 107, 0, // Skip to: 86948 /* 59420 */ MCD_OPC_CheckField, 16, 6, 0, 129, 107, 0, // Skip to: 86948 /* 59427 */ MCD_OPC_Decode, 253, 22, 173, 2, // Opcode: SHA512SU0 /* 59432 */ MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 59506 /* 59437 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59440 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59462 /* 59445 */ MCD_OPC_CheckPredicate, 3, 106, 107, 0, // Skip to: 86948 /* 59450 */ MCD_OPC_CheckField, 21, 1, 1, 99, 107, 0, // Skip to: 86948 /* 59457 */ MCD_OPC_Decode, 197, 1, 133, 2, // Opcode: ADDv2i64 /* 59462 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 59484 /* 59467 */ MCD_OPC_CheckPredicate, 3, 84, 107, 0, // Skip to: 86948 /* 59472 */ MCD_OPC_CheckField, 21, 1, 1, 77, 107, 0, // Skip to: 86948 /* 59479 */ MCD_OPC_Decode, 130, 30, 133, 2, // Opcode: SUBv2i64 /* 59484 */ MCD_OPC_FilterValue, 6, 67, 107, 0, // Skip to: 86948 /* 59489 */ MCD_OPC_CheckPredicate, 9, 62, 107, 0, // Skip to: 86948 /* 59494 */ MCD_OPC_CheckField, 16, 6, 0, 55, 107, 0, // Skip to: 86948 /* 59501 */ MCD_OPC_Decode, 174, 23, 173, 2, // Opcode: SM4E /* 59506 */ MCD_OPC_FilterValue, 2, 101, 0, 0, // Skip to: 59612 /* 59511 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 59514 */ MCD_OPC_FilterValue, 32, 33, 0, 0, // Skip to: 59552 /* 59519 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59522 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 59537 /* 59527 */ MCD_OPC_CheckPredicate, 3, 24, 107, 0, // Skip to: 86948 /* 59532 */ MCD_OPC_Decode, 221, 3, 138, 2, // Opcode: CMGTv2i64rz /* 59537 */ MCD_OPC_FilterValue, 3, 14, 107, 0, // Skip to: 86948 /* 59542 */ MCD_OPC_CheckPredicate, 3, 9, 107, 0, // Skip to: 86948 /* 59547 */ MCD_OPC_Decode, 205, 3, 138, 2, // Opcode: CMGEv2i64rz /* 59552 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 59574 /* 59557 */ MCD_OPC_CheckPredicate, 3, 250, 106, 0, // Skip to: 86948 /* 59562 */ MCD_OPC_CheckField, 29, 3, 2, 243, 106, 0, // Skip to: 86948 /* 59569 */ MCD_OPC_Decode, 147, 12, 138, 2, // Opcode: FRINTPv2f64 /* 59574 */ MCD_OPC_FilterValue, 57, 233, 106, 0, // Skip to: 86948 /* 59579 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59582 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 59597 /* 59587 */ MCD_OPC_CheckPredicate, 4, 220, 106, 0, // Skip to: 86948 /* 59592 */ MCD_OPC_Decode, 148, 12, 239, 1, // Opcode: FRINTPv4f16 /* 59597 */ MCD_OPC_FilterValue, 2, 210, 106, 0, // Skip to: 86948 /* 59602 */ MCD_OPC_CheckPredicate, 4, 205, 106, 0, // Skip to: 86948 /* 59607 */ MCD_OPC_Decode, 150, 12, 138, 2, // Opcode: FRINTPv8f16 /* 59612 */ MCD_OPC_FilterValue, 3, 47, 0, 0, // Skip to: 59664 /* 59617 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59620 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59642 /* 59625 */ MCD_OPC_CheckPredicate, 3, 182, 106, 0, // Skip to: 86948 /* 59630 */ MCD_OPC_CheckField, 21, 1, 1, 175, 106, 0, // Skip to: 86948 /* 59637 */ MCD_OPC_Decode, 236, 4, 133, 2, // Opcode: CMTSTv2i64 /* 59642 */ MCD_OPC_FilterValue, 3, 165, 106, 0, // Skip to: 86948 /* 59647 */ MCD_OPC_CheckPredicate, 3, 160, 106, 0, // Skip to: 86948 /* 59652 */ MCD_OPC_CheckField, 21, 1, 1, 153, 106, 0, // Skip to: 86948 /* 59659 */ MCD_OPC_Decode, 188, 3, 133, 2, // Opcode: CMEQv2i64 /* 59664 */ MCD_OPC_FilterValue, 6, 143, 106, 0, // Skip to: 86948 /* 59669 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59672 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 59694 /* 59677 */ MCD_OPC_CheckPredicate, 4, 130, 106, 0, // Skip to: 86948 /* 59682 */ MCD_OPC_CheckField, 16, 6, 57, 123, 106, 0, // Skip to: 86948 /* 59689 */ MCD_OPC_Decode, 170, 12, 239, 1, // Opcode: FRINTZv4f16 /* 59694 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 59716 /* 59699 */ MCD_OPC_CheckPredicate, 4, 108, 106, 0, // Skip to: 86948 /* 59704 */ MCD_OPC_CheckField, 16, 6, 57, 101, 106, 0, // Skip to: 86948 /* 59711 */ MCD_OPC_Decode, 243, 11, 239, 1, // Opcode: FRINTIv4f16 /* 59716 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 59769 /* 59721 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 59724 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59739 /* 59729 */ MCD_OPC_CheckPredicate, 3, 78, 106, 0, // Skip to: 86948 /* 59734 */ MCD_OPC_Decode, 189, 3, 138, 2, // Opcode: CMEQv2i64rz /* 59739 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59754 /* 59744 */ MCD_OPC_CheckPredicate, 3, 63, 106, 0, // Skip to: 86948 /* 59749 */ MCD_OPC_Decode, 169, 12, 138, 2, // Opcode: FRINTZv2f64 /* 59754 */ MCD_OPC_FilterValue, 57, 53, 106, 0, // Skip to: 86948 /* 59759 */ MCD_OPC_CheckPredicate, 4, 48, 106, 0, // Skip to: 86948 /* 59764 */ MCD_OPC_Decode, 172, 12, 138, 2, // Opcode: FRINTZv8f16 /* 59769 */ MCD_OPC_FilterValue, 3, 38, 106, 0, // Skip to: 86948 /* 59774 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 59777 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59792 /* 59782 */ MCD_OPC_CheckPredicate, 3, 25, 106, 0, // Skip to: 86948 /* 59787 */ MCD_OPC_Decode, 249, 3, 138, 2, // Opcode: CMLEv2i64rz /* 59792 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59807 /* 59797 */ MCD_OPC_CheckPredicate, 3, 10, 106, 0, // Skip to: 86948 /* 59802 */ MCD_OPC_Decode, 242, 11, 138, 2, // Opcode: FRINTIv2f64 /* 59807 */ MCD_OPC_FilterValue, 57, 0, 106, 0, // Skip to: 86948 /* 59812 */ MCD_OPC_CheckPredicate, 4, 251, 105, 0, // Skip to: 86948 /* 59817 */ MCD_OPC_Decode, 245, 11, 138, 2, // Opcode: FRINTIv8f16 /* 59822 */ MCD_OPC_FilterValue, 5, 93, 1, 0, // Skip to: 60176 /* 59827 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 59830 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 59882 /* 59835 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 59838 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59860 /* 59843 */ MCD_OPC_CheckPredicate, 4, 220, 105, 0, // Skip to: 86948 /* 59848 */ MCD_OPC_CheckField, 16, 6, 57, 213, 105, 0, // Skip to: 86948 /* 59855 */ MCD_OPC_Decode, 196, 8, 239, 1, // Opcode: FCVTPSv4f16 /* 59860 */ MCD_OPC_FilterValue, 6, 203, 105, 0, // Skip to: 86948 /* 59865 */ MCD_OPC_CheckPredicate, 4, 198, 105, 0, // Skip to: 86948 /* 59870 */ MCD_OPC_CheckField, 16, 6, 57, 191, 105, 0, // Skip to: 86948 /* 59877 */ MCD_OPC_Decode, 247, 8, 239, 1, // Opcode: FCVTZSv4f16 /* 59882 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 59934 /* 59887 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 59890 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59912 /* 59895 */ MCD_OPC_CheckPredicate, 4, 168, 105, 0, // Skip to: 86948 /* 59900 */ MCD_OPC_CheckField, 16, 6, 57, 161, 105, 0, // Skip to: 86948 /* 59907 */ MCD_OPC_Decode, 210, 8, 239, 1, // Opcode: FCVTPUv4f16 /* 59912 */ MCD_OPC_FilterValue, 6, 151, 105, 0, // Skip to: 86948 /* 59917 */ MCD_OPC_CheckPredicate, 4, 146, 105, 0, // Skip to: 86948 /* 59922 */ MCD_OPC_CheckField, 16, 6, 57, 139, 105, 0, // Skip to: 86948 /* 59929 */ MCD_OPC_Decode, 154, 9, 239, 1, // Opcode: FCVTZUv4f16 /* 59934 */ MCD_OPC_FilterValue, 2, 131, 0, 0, // Skip to: 60070 /* 59939 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 59942 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 59995 /* 59947 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 59950 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59965 /* 59955 */ MCD_OPC_CheckPredicate, 3, 108, 105, 0, // Skip to: 86948 /* 59960 */ MCD_OPC_Decode, 129, 4, 138, 2, // Opcode: CMLTv2i64rz /* 59965 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59980 /* 59970 */ MCD_OPC_CheckPredicate, 3, 93, 105, 0, // Skip to: 86948 /* 59975 */ MCD_OPC_Decode, 195, 8, 138, 2, // Opcode: FCVTPSv2f64 /* 59980 */ MCD_OPC_FilterValue, 57, 83, 105, 0, // Skip to: 86948 /* 59985 */ MCD_OPC_CheckPredicate, 4, 78, 105, 0, // Skip to: 86948 /* 59990 */ MCD_OPC_Decode, 198, 8, 138, 2, // Opcode: FCVTPSv8f16 /* 59995 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 60048 /* 60000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60018 /* 60008 */ MCD_OPC_CheckPredicate, 3, 55, 105, 0, // Skip to: 86948 /* 60013 */ MCD_OPC_Decode, 133, 1, 138, 2, // Opcode: ABSv2i64 /* 60018 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 60033 /* 60023 */ MCD_OPC_CheckPredicate, 3, 40, 105, 0, // Skip to: 86948 /* 60028 */ MCD_OPC_Decode, 244, 8, 138, 2, // Opcode: FCVTZSv2f64 /* 60033 */ MCD_OPC_FilterValue, 57, 30, 105, 0, // Skip to: 86948 /* 60038 */ MCD_OPC_CheckPredicate, 4, 25, 105, 0, // Skip to: 86948 /* 60043 */ MCD_OPC_Decode, 251, 8, 138, 2, // Opcode: FCVTZSv8f16 /* 60048 */ MCD_OPC_FilterValue, 7, 15, 105, 0, // Skip to: 86948 /* 60053 */ MCD_OPC_CheckPredicate, 3, 10, 105, 0, // Skip to: 86948 /* 60058 */ MCD_OPC_CheckField, 21, 1, 1, 3, 105, 0, // Skip to: 86948 /* 60065 */ MCD_OPC_Decode, 151, 1, 133, 2, // Opcode: ADDPv2i64 /* 60070 */ MCD_OPC_FilterValue, 3, 249, 104, 0, // Skip to: 86948 /* 60075 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60078 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 60100 /* 60083 */ MCD_OPC_CheckPredicate, 3, 236, 104, 0, // Skip to: 86948 /* 60088 */ MCD_OPC_CheckField, 10, 3, 6, 229, 104, 0, // Skip to: 86948 /* 60095 */ MCD_OPC_Decode, 182, 20, 138, 2, // Opcode: NEGv2i64 /* 60100 */ MCD_OPC_FilterValue, 33, 33, 0, 0, // Skip to: 60138 /* 60105 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 60108 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60123 /* 60113 */ MCD_OPC_CheckPredicate, 3, 206, 104, 0, // Skip to: 86948 /* 60118 */ MCD_OPC_Decode, 209, 8, 138, 2, // Opcode: FCVTPUv2f64 /* 60123 */ MCD_OPC_FilterValue, 6, 196, 104, 0, // Skip to: 86948 /* 60128 */ MCD_OPC_CheckPredicate, 3, 191, 104, 0, // Skip to: 86948 /* 60133 */ MCD_OPC_Decode, 151, 9, 138, 2, // Opcode: FCVTZUv2f64 /* 60138 */ MCD_OPC_FilterValue, 57, 181, 104, 0, // Skip to: 86948 /* 60143 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 60146 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60161 /* 60151 */ MCD_OPC_CheckPredicate, 4, 168, 104, 0, // Skip to: 86948 /* 60156 */ MCD_OPC_Decode, 212, 8, 138, 2, // Opcode: FCVTPUv8f16 /* 60161 */ MCD_OPC_FilterValue, 6, 158, 104, 0, // Skip to: 86948 /* 60166 */ MCD_OPC_CheckPredicate, 4, 153, 104, 0, // Skip to: 86948 /* 60171 */ MCD_OPC_Decode, 158, 9, 138, 2, // Opcode: FCVTZUv8f16 /* 60176 */ MCD_OPC_FilterValue, 6, 4, 2, 0, // Skip to: 60697 /* 60181 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 60184 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 60252 /* 60189 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 60192 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 60214 /* 60197 */ MCD_OPC_CheckPredicate, 4, 122, 104, 0, // Skip to: 86948 /* 60202 */ MCD_OPC_CheckField, 16, 6, 56, 115, 104, 0, // Skip to: 86948 /* 60209 */ MCD_OPC_Decode, 151, 7, 239, 1, // Opcode: FCMGTv4i16rz /* 60214 */ MCD_OPC_FilterValue, 6, 105, 104, 0, // Skip to: 86948 /* 60219 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60222 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60237 /* 60227 */ MCD_OPC_CheckPredicate, 4, 92, 104, 0, // Skip to: 86948 /* 60232 */ MCD_OPC_Decode, 235, 6, 239, 1, // Opcode: FCMEQv4i16rz /* 60237 */ MCD_OPC_FilterValue, 57, 82, 104, 0, // Skip to: 86948 /* 60242 */ MCD_OPC_CheckPredicate, 4, 77, 104, 0, // Skip to: 86948 /* 60247 */ MCD_OPC_Decode, 204, 11, 239, 1, // Opcode: FRECPEv4f16 /* 60252 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 60320 /* 60257 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 60260 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 60282 /* 60265 */ MCD_OPC_CheckPredicate, 4, 54, 104, 0, // Skip to: 86948 /* 60270 */ MCD_OPC_CheckField, 16, 6, 56, 47, 104, 0, // Skip to: 86948 /* 60277 */ MCD_OPC_Decode, 129, 7, 239, 1, // Opcode: FCMGEv4i16rz /* 60282 */ MCD_OPC_FilterValue, 6, 37, 104, 0, // Skip to: 86948 /* 60287 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60290 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60305 /* 60295 */ MCD_OPC_CheckPredicate, 4, 24, 104, 0, // Skip to: 86948 /* 60300 */ MCD_OPC_Decode, 176, 7, 239, 1, // Opcode: FCMLEv4i16rz /* 60305 */ MCD_OPC_FilterValue, 57, 14, 104, 0, // Skip to: 86948 /* 60310 */ MCD_OPC_CheckPredicate, 4, 9, 104, 0, // Skip to: 86948 /* 60315 */ MCD_OPC_Decode, 181, 12, 239, 1, // Opcode: FRSQRTEv4f16 /* 60320 */ MCD_OPC_FilterValue, 2, 175, 0, 0, // Skip to: 60500 /* 60325 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... /* 60328 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 60350 /* 60333 */ MCD_OPC_CheckPredicate, 3, 242, 103, 0, // Skip to: 86948 /* 60338 */ MCD_OPC_CheckField, 21, 1, 1, 235, 103, 0, // Skip to: 86948 /* 60345 */ MCD_OPC_Decode, 147, 10, 133, 2, // Opcode: FMINNMv2f64 /* 60350 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 60388 /* 60355 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60358 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60373 /* 60363 */ MCD_OPC_CheckPredicate, 3, 212, 103, 0, // Skip to: 86948 /* 60368 */ MCD_OPC_Decode, 148, 7, 138, 2, // Opcode: FCMGTv2i64rz /* 60373 */ MCD_OPC_FilterValue, 56, 202, 103, 0, // Skip to: 86948 /* 60378 */ MCD_OPC_CheckPredicate, 4, 197, 103, 0, // Skip to: 86948 /* 60383 */ MCD_OPC_Decode, 154, 7, 138, 2, // Opcode: FCMGTv8i16rz /* 60388 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 60410 /* 60393 */ MCD_OPC_CheckPredicate, 3, 182, 103, 0, // Skip to: 86948 /* 60398 */ MCD_OPC_CheckField, 21, 1, 1, 175, 103, 0, // Skip to: 86948 /* 60405 */ MCD_OPC_Decode, 206, 10, 141, 2, // Opcode: FMLSv2f64 /* 60410 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 60432 /* 60415 */ MCD_OPC_CheckPredicate, 3, 160, 103, 0, // Skip to: 86948 /* 60420 */ MCD_OPC_CheckField, 21, 1, 1, 153, 103, 0, // Skip to: 86948 /* 60427 */ MCD_OPC_Decode, 228, 12, 133, 2, // Opcode: FSUBv2f64 /* 60432 */ MCD_OPC_FilterValue, 6, 143, 103, 0, // Skip to: 86948 /* 60437 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60440 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60455 /* 60445 */ MCD_OPC_CheckPredicate, 3, 130, 103, 0, // Skip to: 86948 /* 60450 */ MCD_OPC_Decode, 232, 6, 138, 2, // Opcode: FCMEQv2i64rz /* 60455 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 60470 /* 60460 */ MCD_OPC_CheckPredicate, 3, 115, 103, 0, // Skip to: 86948 /* 60465 */ MCD_OPC_Decode, 203, 11, 138, 2, // Opcode: FRECPEv2f64 /* 60470 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60485 /* 60475 */ MCD_OPC_CheckPredicate, 4, 100, 103, 0, // Skip to: 86948 /* 60480 */ MCD_OPC_Decode, 238, 6, 138, 2, // Opcode: FCMEQv8i16rz /* 60485 */ MCD_OPC_FilterValue, 57, 90, 103, 0, // Skip to: 86948 /* 60490 */ MCD_OPC_CheckPredicate, 4, 85, 103, 0, // Skip to: 86948 /* 60495 */ MCD_OPC_Decode, 206, 11, 138, 2, // Opcode: FRECPEv8f16 /* 60500 */ MCD_OPC_FilterValue, 3, 75, 103, 0, // Skip to: 86948 /* 60505 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 60508 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 60636 /* 60513 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60516 */ MCD_OPC_FilterValue, 32, 33, 0, 0, // Skip to: 60554 /* 60521 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 60524 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 60539 /* 60529 */ MCD_OPC_CheckPredicate, 3, 46, 103, 0, // Skip to: 86948 /* 60534 */ MCD_OPC_Decode, 254, 6, 138, 2, // Opcode: FCMGEv2i64rz /* 60539 */ MCD_OPC_FilterValue, 3, 36, 103, 0, // Skip to: 86948 /* 60544 */ MCD_OPC_CheckPredicate, 3, 31, 103, 0, // Skip to: 86948 /* 60549 */ MCD_OPC_Decode, 175, 7, 138, 2, // Opcode: FCMLEv2i64rz /* 60554 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 60576 /* 60559 */ MCD_OPC_CheckPredicate, 3, 16, 103, 0, // Skip to: 86948 /* 60564 */ MCD_OPC_CheckField, 11, 2, 3, 9, 103, 0, // Skip to: 86948 /* 60571 */ MCD_OPC_Decode, 180, 12, 138, 2, // Opcode: FRSQRTEv2f64 /* 60576 */ MCD_OPC_FilterValue, 56, 33, 0, 0, // Skip to: 60614 /* 60581 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 60584 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 60599 /* 60589 */ MCD_OPC_CheckPredicate, 4, 242, 102, 0, // Skip to: 86948 /* 60594 */ MCD_OPC_Decode, 132, 7, 138, 2, // Opcode: FCMGEv8i16rz /* 60599 */ MCD_OPC_FilterValue, 3, 232, 102, 0, // Skip to: 86948 /* 60604 */ MCD_OPC_CheckPredicate, 4, 227, 102, 0, // Skip to: 86948 /* 60609 */ MCD_OPC_Decode, 178, 7, 138, 2, // Opcode: FCMLEv8i16rz /* 60614 */ MCD_OPC_FilterValue, 57, 217, 102, 0, // Skip to: 86948 /* 60619 */ MCD_OPC_CheckPredicate, 4, 212, 102, 0, // Skip to: 86948 /* 60624 */ MCD_OPC_CheckField, 11, 2, 3, 205, 102, 0, // Skip to: 86948 /* 60631 */ MCD_OPC_Decode, 183, 12, 138, 2, // Opcode: FRSQRTEv8f16 /* 60636 */ MCD_OPC_FilterValue, 1, 195, 102, 0, // Skip to: 86948 /* 60641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 60644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 60659 /* 60649 */ MCD_OPC_CheckPredicate, 11, 182, 102, 0, // Skip to: 86948 /* 60654 */ MCD_OPC_Decode, 161, 7, 169, 2, // Opcode: FCMLAv2f64 /* 60659 */ MCD_OPC_FilterValue, 1, 172, 102, 0, // Skip to: 86948 /* 60664 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 60667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 60682 /* 60672 */ MCD_OPC_CheckPredicate, 3, 159, 102, 0, // Skip to: 86948 /* 60677 */ MCD_OPC_Decode, 254, 9, 133, 2, // Opcode: FMINNMPv2f64 /* 60682 */ MCD_OPC_FilterValue, 2, 149, 102, 0, // Skip to: 86948 /* 60687 */ MCD_OPC_CheckPredicate, 3, 144, 102, 0, // Skip to: 86948 /* 60692 */ MCD_OPC_Decode, 135, 6, 133, 2, // Opcode: FABDv2f64 /* 60697 */ MCD_OPC_FilterValue, 7, 134, 102, 0, // Skip to: 86948 /* 60702 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 60705 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 60771 /* 60710 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 60713 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 60742 /* 60718 */ MCD_OPC_CheckPredicate, 5, 113, 102, 0, // Skip to: 86948 /* 60723 */ MCD_OPC_CheckField, 21, 1, 1, 106, 102, 0, // Skip to: 86948 /* 60730 */ MCD_OPC_CheckField, 12, 1, 0, 99, 102, 0, // Skip to: 86948 /* 60737 */ MCD_OPC_Decode, 244, 20, 234, 1, // Opcode: PMULLv1i64 /* 60742 */ MCD_OPC_FilterValue, 2, 89, 102, 0, // Skip to: 86948 /* 60747 */ MCD_OPC_CheckPredicate, 5, 84, 102, 0, // Skip to: 86948 /* 60752 */ MCD_OPC_CheckField, 21, 1, 1, 77, 102, 0, // Skip to: 86948 /* 60759 */ MCD_OPC_CheckField, 12, 1, 0, 70, 102, 0, // Skip to: 86948 /* 60766 */ MCD_OPC_Decode, 245, 20, 133, 2, // Opcode: PMULLv2i64 /* 60771 */ MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 60869 /* 60776 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 60779 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60801 /* 60784 */ MCD_OPC_CheckPredicate, 11, 47, 102, 0, // Skip to: 86948 /* 60789 */ MCD_OPC_CheckField, 29, 3, 3, 40, 102, 0, // Skip to: 86948 /* 60796 */ MCD_OPC_Decode, 207, 6, 170, 2, // Opcode: FCADDv2f64 /* 60801 */ MCD_OPC_FilterValue, 1, 30, 102, 0, // Skip to: 86948 /* 60806 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 60809 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60831 /* 60814 */ MCD_OPC_CheckPredicate, 3, 17, 102, 0, // Skip to: 86948 /* 60819 */ MCD_OPC_CheckField, 29, 3, 3, 10, 102, 0, // Skip to: 86948 /* 60826 */ MCD_OPC_Decode, 146, 7, 133, 2, // Opcode: FCMGTv2f64 /* 60831 */ MCD_OPC_FilterValue, 1, 0, 102, 0, // Skip to: 86948 /* 60836 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 60839 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60854 /* 60844 */ MCD_OPC_CheckPredicate, 3, 243, 101, 0, // Skip to: 86948 /* 60849 */ MCD_OPC_Decode, 173, 10, 133, 2, // Opcode: FMINv2f64 /* 60854 */ MCD_OPC_FilterValue, 3, 233, 101, 0, // Skip to: 86948 /* 60859 */ MCD_OPC_CheckPredicate, 3, 228, 101, 0, // Skip to: 86948 /* 60864 */ MCD_OPC_Decode, 152, 10, 133, 2, // Opcode: FMINPv2f64 /* 60869 */ MCD_OPC_FilterValue, 2, 24, 1, 0, // Skip to: 61154 /* 60874 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 60877 */ MCD_OPC_FilterValue, 32, 63, 0, 0, // Skip to: 60945 /* 60882 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 60885 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60907 /* 60890 */ MCD_OPC_CheckPredicate, 3, 197, 101, 0, // Skip to: 86948 /* 60895 */ MCD_OPC_CheckField, 29, 3, 2, 190, 101, 0, // Skip to: 86948 /* 60902 */ MCD_OPC_Decode, 186, 7, 138, 2, // Opcode: FCMLTv2i64rz /* 60907 */ MCD_OPC_FilterValue, 1, 180, 101, 0, // Skip to: 86948 /* 60912 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 60915 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60930 /* 60920 */ MCD_OPC_CheckPredicate, 3, 167, 101, 0, // Skip to: 86948 /* 60925 */ MCD_OPC_Decode, 146, 6, 138, 2, // Opcode: FABSv2f64 /* 60930 */ MCD_OPC_FilterValue, 3, 157, 101, 0, // Skip to: 86948 /* 60935 */ MCD_OPC_CheckPredicate, 3, 152, 101, 0, // Skip to: 86948 /* 60940 */ MCD_OPC_Decode, 171, 11, 138, 2, // Opcode: FNEGv2f64 /* 60945 */ MCD_OPC_FilterValue, 33, 24, 0, 0, // Skip to: 60974 /* 60950 */ MCD_OPC_CheckPredicate, 3, 137, 101, 0, // Skip to: 86948 /* 60955 */ MCD_OPC_CheckField, 29, 3, 3, 130, 101, 0, // Skip to: 86948 /* 60962 */ MCD_OPC_CheckField, 12, 1, 1, 123, 101, 0, // Skip to: 86948 /* 60969 */ MCD_OPC_Decode, 205, 12, 138, 2, // Opcode: FSQRTv2f64 /* 60974 */ MCD_OPC_FilterValue, 56, 123, 0, 0, // Skip to: 61102 /* 60979 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 60982 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 61020 /* 60987 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 60990 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61005 /* 60995 */ MCD_OPC_CheckPredicate, 4, 92, 101, 0, // Skip to: 86948 /* 61000 */ MCD_OPC_Decode, 187, 7, 239, 1, // Opcode: FCMLTv4i16rz /* 61005 */ MCD_OPC_FilterValue, 1, 82, 101, 0, // Skip to: 86948 /* 61010 */ MCD_OPC_CheckPredicate, 4, 77, 101, 0, // Skip to: 86948 /* 61015 */ MCD_OPC_Decode, 147, 6, 239, 1, // Opcode: FABSv4f16 /* 61020 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 61042 /* 61025 */ MCD_OPC_CheckPredicate, 4, 62, 101, 0, // Skip to: 86948 /* 61030 */ MCD_OPC_CheckField, 12, 1, 1, 55, 101, 0, // Skip to: 86948 /* 61037 */ MCD_OPC_Decode, 172, 11, 239, 1, // Opcode: FNEGv4f16 /* 61042 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 61080 /* 61047 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 61050 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61065 /* 61055 */ MCD_OPC_CheckPredicate, 4, 32, 101, 0, // Skip to: 86948 /* 61060 */ MCD_OPC_Decode, 189, 7, 138, 2, // Opcode: FCMLTv8i16rz /* 61065 */ MCD_OPC_FilterValue, 1, 22, 101, 0, // Skip to: 86948 /* 61070 */ MCD_OPC_CheckPredicate, 4, 17, 101, 0, // Skip to: 86948 /* 61075 */ MCD_OPC_Decode, 149, 6, 138, 2, // Opcode: FABSv8f16 /* 61080 */ MCD_OPC_FilterValue, 3, 7, 101, 0, // Skip to: 86948 /* 61085 */ MCD_OPC_CheckPredicate, 4, 2, 101, 0, // Skip to: 86948 /* 61090 */ MCD_OPC_CheckField, 12, 1, 1, 251, 100, 0, // Skip to: 86948 /* 61097 */ MCD_OPC_Decode, 174, 11, 138, 2, // Opcode: FNEGv8f16 /* 61102 */ MCD_OPC_FilterValue, 57, 241, 100, 0, // Skip to: 86948 /* 61107 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 61110 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 61132 /* 61115 */ MCD_OPC_CheckPredicate, 4, 228, 100, 0, // Skip to: 86948 /* 61120 */ MCD_OPC_CheckField, 12, 1, 1, 221, 100, 0, // Skip to: 86948 /* 61127 */ MCD_OPC_Decode, 206, 12, 239, 1, // Opcode: FSQRTv4f16 /* 61132 */ MCD_OPC_FilterValue, 3, 211, 100, 0, // Skip to: 86948 /* 61137 */ MCD_OPC_CheckPredicate, 4, 206, 100, 0, // Skip to: 86948 /* 61142 */ MCD_OPC_CheckField, 12, 1, 1, 199, 100, 0, // Skip to: 86948 /* 61149 */ MCD_OPC_Decode, 208, 12, 138, 2, // Opcode: FSQRTv8f16 /* 61154 */ MCD_OPC_FilterValue, 3, 189, 100, 0, // Skip to: 86948 /* 61159 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 61162 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 61191 /* 61167 */ MCD_OPC_CheckPredicate, 3, 176, 100, 0, // Skip to: 86948 /* 61172 */ MCD_OPC_CheckField, 29, 3, 3, 169, 100, 0, // Skip to: 86948 /* 61179 */ MCD_OPC_CheckField, 21, 1, 1, 162, 100, 0, // Skip to: 86948 /* 61186 */ MCD_OPC_Decode, 168, 6, 133, 2, // Opcode: FACGTv2f64 /* 61191 */ MCD_OPC_FilterValue, 1, 152, 100, 0, // Skip to: 86948 /* 61196 */ MCD_OPC_CheckPredicate, 3, 147, 100, 0, // Skip to: 86948 /* 61201 */ MCD_OPC_CheckField, 29, 3, 2, 140, 100, 0, // Skip to: 86948 /* 61208 */ MCD_OPC_CheckField, 21, 1, 1, 133, 100, 0, // Skip to: 86948 /* 61215 */ MCD_OPC_Decode, 191, 12, 133, 2, // Opcode: FRSQRTSv2f64 /* 61220 */ MCD_OPC_FilterValue, 12, 94, 17, 0, // Skip to: 65671 /* 61225 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 61228 */ MCD_OPC_FilterValue, 0, 66, 4, 0, // Skip to: 62323 /* 61233 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 61236 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 61289 /* 61241 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 61244 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61259 /* 61249 */ MCD_OPC_CheckPredicate, 4, 94, 100, 0, // Skip to: 86948 /* 61254 */ MCD_OPC_Decode, 192, 10, 174, 2, // Opcode: FMLAv4i16_indexed /* 61259 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 61274 /* 61264 */ MCD_OPC_CheckPredicate, 4, 79, 100, 0, // Skip to: 86948 /* 61269 */ MCD_OPC_Decode, 211, 10, 174, 2, // Opcode: FMLSv4i16_indexed /* 61274 */ MCD_OPC_FilterValue, 9, 69, 100, 0, // Skip to: 86948 /* 61279 */ MCD_OPC_CheckPredicate, 4, 64, 100, 0, // Skip to: 86948 /* 61284 */ MCD_OPC_Decode, 160, 11, 175, 2, // Opcode: FMULv4i16_indexed /* 61289 */ MCD_OPC_FilterValue, 1, 54, 100, 0, // Skip to: 86948 /* 61294 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 61297 */ MCD_OPC_FilterValue, 0, 41, 3, 0, // Skip to: 62111 /* 61302 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 61305 */ MCD_OPC_FilterValue, 0, 143, 1, 0, // Skip to: 61709 /* 61310 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 61313 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 61466 /* 61318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 61321 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 61428 /* 61326 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 61329 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 61390 /* 61334 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 61337 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61352 /* 61342 */ MCD_OPC_CheckPredicate, 3, 1, 100, 0, // Skip to: 86948 /* 61347 */ MCD_OPC_Decode, 236, 19, 176, 2, // Opcode: MOVIv2i32 /* 61352 */ MCD_OPC_FilterValue, 1, 247, 99, 0, // Skip to: 86948 /* 61357 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 61360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61375 /* 61365 */ MCD_OPC_CheckPredicate, 3, 234, 99, 0, // Skip to: 86948 /* 61370 */ MCD_OPC_Decode, 242, 26, 177, 2, // Opcode: SSHRv8i8_shift /* 61375 */ MCD_OPC_FilterValue, 1, 224, 99, 0, // Skip to: 86948 /* 61380 */ MCD_OPC_CheckPredicate, 3, 219, 99, 0, // Skip to: 86948 /* 61385 */ MCD_OPC_Decode, 212, 26, 177, 2, // Opcode: SRSHRv8i8_shift /* 61390 */ MCD_OPC_FilterValue, 1, 209, 99, 0, // Skip to: 86948 /* 61395 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 61398 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61413 /* 61403 */ MCD_OPC_CheckPredicate, 3, 196, 99, 0, // Skip to: 86948 /* 61408 */ MCD_OPC_Decode, 239, 26, 178, 2, // Opcode: SSHRv4i16_shift /* 61413 */ MCD_OPC_FilterValue, 1, 186, 99, 0, // Skip to: 86948 /* 61418 */ MCD_OPC_CheckPredicate, 3, 181, 99, 0, // Skip to: 86948 /* 61423 */ MCD_OPC_Decode, 209, 26, 178, 2, // Opcode: SRSHRv4i16_shift /* 61428 */ MCD_OPC_FilterValue, 1, 171, 99, 0, // Skip to: 86948 /* 61433 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 61436 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61451 /* 61441 */ MCD_OPC_CheckPredicate, 3, 158, 99, 0, // Skip to: 86948 /* 61446 */ MCD_OPC_Decode, 237, 26, 179, 2, // Opcode: SSHRv2i32_shift /* 61451 */ MCD_OPC_FilterValue, 1, 148, 99, 0, // Skip to: 86948 /* 61456 */ MCD_OPC_CheckPredicate, 3, 143, 99, 0, // Skip to: 86948 /* 61461 */ MCD_OPC_Decode, 207, 26, 179, 2, // Opcode: SRSHRv2i32_shift /* 61466 */ MCD_OPC_FilterValue, 1, 133, 99, 0, // Skip to: 86948 /* 61471 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 61474 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 61641 /* 61479 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 61482 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 61573 /* 61487 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 61490 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61505 /* 61495 */ MCD_OPC_CheckPredicate, 3, 104, 99, 0, // Skip to: 86948 /* 61500 */ MCD_OPC_Decode, 218, 20, 180, 2, // Opcode: ORRv2i32 /* 61505 */ MCD_OPC_FilterValue, 1, 94, 99, 0, // Skip to: 86948 /* 61510 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 61513 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61528 /* 61518 */ MCD_OPC_CheckPredicate, 3, 81, 99, 0, // Skip to: 86948 /* 61523 */ MCD_OPC_Decode, 250, 26, 181, 2, // Opcode: SSRAv8i8_shift /* 61528 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61543 /* 61533 */ MCD_OPC_CheckPredicate, 3, 66, 99, 0, // Skip to: 86948 /* 61538 */ MCD_OPC_Decode, 220, 26, 181, 2, // Opcode: SRSRAv8i8_shift /* 61543 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61558 /* 61548 */ MCD_OPC_CheckPredicate, 3, 51, 99, 0, // Skip to: 86948 /* 61553 */ MCD_OPC_Decode, 146, 23, 182, 2, // Opcode: SHLv8i8_shift /* 61558 */ MCD_OPC_FilterValue, 3, 41, 99, 0, // Skip to: 86948 /* 61563 */ MCD_OPC_CheckPredicate, 3, 36, 99, 0, // Skip to: 86948 /* 61568 */ MCD_OPC_Decode, 255, 25, 182, 2, // Opcode: SQSHLv8i8_shift /* 61573 */ MCD_OPC_FilterValue, 1, 26, 99, 0, // Skip to: 86948 /* 61578 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 61581 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61596 /* 61586 */ MCD_OPC_CheckPredicate, 3, 13, 99, 0, // Skip to: 86948 /* 61591 */ MCD_OPC_Decode, 247, 26, 183, 2, // Opcode: SSRAv4i16_shift /* 61596 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61611 /* 61601 */ MCD_OPC_CheckPredicate, 3, 254, 98, 0, // Skip to: 86948 /* 61606 */ MCD_OPC_Decode, 217, 26, 183, 2, // Opcode: SRSRAv4i16_shift /* 61611 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61626 /* 61616 */ MCD_OPC_CheckPredicate, 3, 239, 98, 0, // Skip to: 86948 /* 61621 */ MCD_OPC_Decode, 143, 23, 184, 2, // Opcode: SHLv4i16_shift /* 61626 */ MCD_OPC_FilterValue, 3, 229, 98, 0, // Skip to: 86948 /* 61631 */ MCD_OPC_CheckPredicate, 3, 224, 98, 0, // Skip to: 86948 /* 61636 */ MCD_OPC_Decode, 249, 25, 184, 2, // Opcode: SQSHLv4i16_shift /* 61641 */ MCD_OPC_FilterValue, 1, 214, 98, 0, // Skip to: 86948 /* 61646 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 61649 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61664 /* 61654 */ MCD_OPC_CheckPredicate, 3, 201, 98, 0, // Skip to: 86948 /* 61659 */ MCD_OPC_Decode, 245, 26, 185, 2, // Opcode: SSRAv2i32_shift /* 61664 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61679 /* 61669 */ MCD_OPC_CheckPredicate, 3, 186, 98, 0, // Skip to: 86948 /* 61674 */ MCD_OPC_Decode, 215, 26, 185, 2, // Opcode: SRSRAv2i32_shift /* 61679 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61694 /* 61684 */ MCD_OPC_CheckPredicate, 3, 171, 98, 0, // Skip to: 86948 /* 61689 */ MCD_OPC_Decode, 141, 23, 186, 2, // Opcode: SHLv2i32_shift /* 61694 */ MCD_OPC_FilterValue, 3, 161, 98, 0, // Skip to: 86948 /* 61699 */ MCD_OPC_CheckPredicate, 3, 156, 98, 0, // Skip to: 86948 /* 61704 */ MCD_OPC_Decode, 245, 25, 186, 2, // Opcode: SQSHLv2i32_shift /* 61709 */ MCD_OPC_FilterValue, 1, 146, 98, 0, // Skip to: 86948 /* 61714 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 61717 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 61983 /* 61722 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 61725 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 61878 /* 61730 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 61733 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 61840 /* 61738 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 61741 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 61802 /* 61746 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 61749 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61764 /* 61754 */ MCD_OPC_CheckPredicate, 3, 101, 98, 0, // Skip to: 86948 /* 61759 */ MCD_OPC_Decode, 238, 19, 176, 2, // Opcode: MOVIv4i16 /* 61764 */ MCD_OPC_FilterValue, 1, 91, 98, 0, // Skip to: 86948 /* 61769 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 61772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61787 /* 61777 */ MCD_OPC_CheckPredicate, 3, 78, 98, 0, // Skip to: 86948 /* 61782 */ MCD_OPC_Decode, 152, 23, 187, 2, // Opcode: SHRNv8i8_shift /* 61787 */ MCD_OPC_FilterValue, 1, 68, 98, 0, // Skip to: 86948 /* 61792 */ MCD_OPC_CheckPredicate, 3, 63, 98, 0, // Skip to: 86948 /* 61797 */ MCD_OPC_Decode, 226, 26, 188, 2, // Opcode: SSHLLv8i8_shift /* 61802 */ MCD_OPC_FilterValue, 1, 53, 98, 0, // Skip to: 86948 /* 61807 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 61810 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61825 /* 61815 */ MCD_OPC_CheckPredicate, 3, 40, 98, 0, // Skip to: 86948 /* 61820 */ MCD_OPC_Decode, 149, 23, 189, 2, // Opcode: SHRNv4i16_shift /* 61825 */ MCD_OPC_FilterValue, 1, 30, 98, 0, // Skip to: 86948 /* 61830 */ MCD_OPC_CheckPredicate, 3, 25, 98, 0, // Skip to: 86948 /* 61835 */ MCD_OPC_Decode, 223, 26, 190, 2, // Opcode: SSHLLv4i16_shift /* 61840 */ MCD_OPC_FilterValue, 1, 15, 98, 0, // Skip to: 86948 /* 61845 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 61848 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61863 /* 61853 */ MCD_OPC_CheckPredicate, 3, 2, 98, 0, // Skip to: 86948 /* 61858 */ MCD_OPC_Decode, 148, 23, 191, 2, // Opcode: SHRNv2i32_shift /* 61863 */ MCD_OPC_FilterValue, 1, 248, 97, 0, // Skip to: 86948 /* 61868 */ MCD_OPC_CheckPredicate, 3, 243, 97, 0, // Skip to: 86948 /* 61873 */ MCD_OPC_Decode, 222, 26, 192, 2, // Opcode: SSHLLv2i32_shift /* 61878 */ MCD_OPC_FilterValue, 1, 233, 97, 0, // Skip to: 86948 /* 61883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 61886 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 61961 /* 61891 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 61894 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 61939 /* 61899 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 61902 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61917 /* 61907 */ MCD_OPC_CheckPredicate, 3, 204, 97, 0, // Skip to: 86948 /* 61912 */ MCD_OPC_Decode, 219, 20, 180, 2, // Opcode: ORRv4i16 /* 61917 */ MCD_OPC_FilterValue, 1, 194, 97, 0, // Skip to: 86948 /* 61922 */ MCD_OPC_CheckPredicate, 3, 189, 97, 0, // Skip to: 86948 /* 61927 */ MCD_OPC_CheckField, 13, 1, 0, 182, 97, 0, // Skip to: 86948 /* 61934 */ MCD_OPC_Decode, 136, 26, 187, 2, // Opcode: SQSHRNv8i8_shift /* 61939 */ MCD_OPC_FilterValue, 1, 172, 97, 0, // Skip to: 86948 /* 61944 */ MCD_OPC_CheckPredicate, 3, 167, 97, 0, // Skip to: 86948 /* 61949 */ MCD_OPC_CheckField, 13, 1, 0, 160, 97, 0, // Skip to: 86948 /* 61956 */ MCD_OPC_Decode, 133, 26, 189, 2, // Opcode: SQSHRNv4i16_shift /* 61961 */ MCD_OPC_FilterValue, 1, 150, 97, 0, // Skip to: 86948 /* 61966 */ MCD_OPC_CheckPredicate, 3, 145, 97, 0, // Skip to: 86948 /* 61971 */ MCD_OPC_CheckField, 13, 1, 0, 138, 97, 0, // Skip to: 86948 /* 61978 */ MCD_OPC_Decode, 132, 26, 191, 2, // Opcode: SQSHRNv2i32_shift /* 61983 */ MCD_OPC_FilterValue, 1, 128, 97, 0, // Skip to: 86948 /* 61988 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 61991 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62013 /* 61996 */ MCD_OPC_CheckPredicate, 3, 115, 97, 0, // Skip to: 86948 /* 62001 */ MCD_OPC_CheckField, 19, 3, 0, 108, 97, 0, // Skip to: 86948 /* 62008 */ MCD_OPC_Decode, 237, 19, 176, 2, // Opcode: MOVIv2s_msl /* 62013 */ MCD_OPC_FilterValue, 1, 98, 97, 0, // Skip to: 86948 /* 62018 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 62021 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 62089 /* 62026 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62029 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62074 /* 62034 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62037 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62059 /* 62042 */ MCD_OPC_CheckPredicate, 3, 69, 97, 0, // Skip to: 86948 /* 62047 */ MCD_OPC_CheckField, 19, 1, 0, 62, 97, 0, // Skip to: 86948 /* 62054 */ MCD_OPC_Decode, 241, 19, 176, 2, // Opcode: MOVIv8b_ns /* 62059 */ MCD_OPC_FilterValue, 1, 52, 97, 0, // Skip to: 86948 /* 62064 */ MCD_OPC_CheckPredicate, 4, 47, 97, 0, // Skip to: 86948 /* 62069 */ MCD_OPC_Decode, 215, 22, 178, 2, // Opcode: SCVTFv4i16_shift /* 62074 */ MCD_OPC_FilterValue, 1, 37, 97, 0, // Skip to: 86948 /* 62079 */ MCD_OPC_CheckPredicate, 3, 32, 97, 0, // Skip to: 86948 /* 62084 */ MCD_OPC_Decode, 211, 22, 179, 2, // Opcode: SCVTFv2i32_shift /* 62089 */ MCD_OPC_FilterValue, 1, 22, 97, 0, // Skip to: 86948 /* 62094 */ MCD_OPC_CheckPredicate, 3, 17, 97, 0, // Skip to: 86948 /* 62099 */ MCD_OPC_CheckField, 19, 3, 0, 10, 97, 0, // Skip to: 86948 /* 62106 */ MCD_OPC_Decode, 234, 10, 176, 2, // Opcode: FMOVv2f32_ns /* 62111 */ MCD_OPC_FilterValue, 1, 0, 97, 0, // Skip to: 86948 /* 62116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 62119 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 62187 /* 62124 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62127 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62172 /* 62132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62135 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62157 /* 62140 */ MCD_OPC_CheckPredicate, 3, 227, 96, 0, // Skip to: 86948 /* 62145 */ MCD_OPC_CheckField, 19, 1, 1, 220, 96, 0, // Skip to: 86948 /* 62152 */ MCD_OPC_Decode, 239, 21, 187, 2, // Opcode: RSHRNv8i8_shift /* 62157 */ MCD_OPC_FilterValue, 1, 210, 96, 0, // Skip to: 86948 /* 62162 */ MCD_OPC_CheckPredicate, 3, 205, 96, 0, // Skip to: 86948 /* 62167 */ MCD_OPC_Decode, 236, 21, 189, 2, // Opcode: RSHRNv4i16_shift /* 62172 */ MCD_OPC_FilterValue, 1, 195, 96, 0, // Skip to: 86948 /* 62177 */ MCD_OPC_CheckPredicate, 3, 190, 96, 0, // Skip to: 86948 /* 62182 */ MCD_OPC_Decode, 235, 21, 191, 2, // Opcode: RSHRNv2i32_shift /* 62187 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 62255 /* 62192 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62195 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62240 /* 62200 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62203 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62225 /* 62208 */ MCD_OPC_CheckPredicate, 3, 159, 96, 0, // Skip to: 86948 /* 62213 */ MCD_OPC_CheckField, 19, 1, 1, 152, 96, 0, // Skip to: 86948 /* 62220 */ MCD_OPC_Decode, 213, 25, 187, 2, // Opcode: SQRSHRNv8i8_shift /* 62225 */ MCD_OPC_FilterValue, 1, 142, 96, 0, // Skip to: 86948 /* 62230 */ MCD_OPC_CheckPredicate, 3, 137, 96, 0, // Skip to: 86948 /* 62235 */ MCD_OPC_Decode, 210, 25, 189, 2, // Opcode: SQRSHRNv4i16_shift /* 62240 */ MCD_OPC_FilterValue, 1, 127, 96, 0, // Skip to: 86948 /* 62245 */ MCD_OPC_CheckPredicate, 3, 122, 96, 0, // Skip to: 86948 /* 62250 */ MCD_OPC_Decode, 209, 25, 191, 2, // Opcode: SQRSHRNv2i32_shift /* 62255 */ MCD_OPC_FilterValue, 15, 112, 96, 0, // Skip to: 86948 /* 62260 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62263 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62308 /* 62268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62271 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62293 /* 62276 */ MCD_OPC_CheckPredicate, 4, 91, 96, 0, // Skip to: 86948 /* 62281 */ MCD_OPC_CheckField, 19, 1, 0, 84, 96, 0, // Skip to: 86948 /* 62288 */ MCD_OPC_Decode, 236, 10, 176, 2, // Opcode: FMOVv4f16_ns /* 62293 */ MCD_OPC_FilterValue, 1, 74, 96, 0, // Skip to: 86948 /* 62298 */ MCD_OPC_CheckPredicate, 4, 69, 96, 0, // Skip to: 86948 /* 62303 */ MCD_OPC_Decode, 249, 8, 178, 2, // Opcode: FCVTZSv4i16_shift /* 62308 */ MCD_OPC_FilterValue, 1, 59, 96, 0, // Skip to: 86948 /* 62313 */ MCD_OPC_CheckPredicate, 3, 54, 96, 0, // Skip to: 86948 /* 62318 */ MCD_OPC_Decode, 245, 8, 179, 2, // Opcode: FCVTZSv2i32_shift /* 62323 */ MCD_OPC_FilterValue, 1, 93, 4, 0, // Skip to: 63445 /* 62328 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 62331 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62353 /* 62336 */ MCD_OPC_CheckPredicate, 4, 31, 96, 0, // Skip to: 86948 /* 62341 */ MCD_OPC_CheckField, 12, 4, 9, 24, 96, 0, // Skip to: 86948 /* 62348 */ MCD_OPC_Decode, 135, 11, 175, 2, // Opcode: FMULXv4i16_indexed /* 62353 */ MCD_OPC_FilterValue, 1, 14, 96, 0, // Skip to: 86948 /* 62358 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 62361 */ MCD_OPC_FilterValue, 0, 122, 3, 0, // Skip to: 63256 /* 62366 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 62369 */ MCD_OPC_FilterValue, 0, 233, 1, 0, // Skip to: 62863 /* 62374 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 62377 */ MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 62620 /* 62382 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62385 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 62552 /* 62390 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62393 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 62484 /* 62398 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 62401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62416 /* 62406 */ MCD_OPC_CheckPredicate, 3, 217, 95, 0, // Skip to: 86948 /* 62411 */ MCD_OPC_Decode, 167, 20, 176, 2, // Opcode: MVNIv2i32 /* 62416 */ MCD_OPC_FilterValue, 1, 207, 95, 0, // Skip to: 86948 /* 62421 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 62424 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62439 /* 62429 */ MCD_OPC_CheckPredicate, 3, 194, 95, 0, // Skip to: 86948 /* 62434 */ MCD_OPC_Decode, 144, 34, 177, 2, // Opcode: USHRv8i8_shift /* 62439 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62454 /* 62444 */ MCD_OPC_CheckPredicate, 3, 179, 95, 0, // Skip to: 86948 /* 62449 */ MCD_OPC_Decode, 240, 33, 177, 2, // Opcode: URSHRv8i8_shift /* 62454 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62469 /* 62459 */ MCD_OPC_CheckPredicate, 3, 164, 95, 0, // Skip to: 86948 /* 62464 */ MCD_OPC_Decode, 196, 26, 181, 2, // Opcode: SRIv8i8_shift /* 62469 */ MCD_OPC_FilterValue, 3, 154, 95, 0, // Skip to: 86948 /* 62474 */ MCD_OPC_CheckPredicate, 3, 149, 95, 0, // Skip to: 86948 /* 62479 */ MCD_OPC_Decode, 233, 25, 182, 2, // Opcode: SQSHLUv8i8_shift /* 62484 */ MCD_OPC_FilterValue, 1, 139, 95, 0, // Skip to: 86948 /* 62489 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 62492 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62507 /* 62497 */ MCD_OPC_CheckPredicate, 3, 126, 95, 0, // Skip to: 86948 /* 62502 */ MCD_OPC_Decode, 141, 34, 178, 2, // Opcode: USHRv4i16_shift /* 62507 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62522 /* 62512 */ MCD_OPC_CheckPredicate, 3, 111, 95, 0, // Skip to: 86948 /* 62517 */ MCD_OPC_Decode, 237, 33, 178, 2, // Opcode: URSHRv4i16_shift /* 62522 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62537 /* 62527 */ MCD_OPC_CheckPredicate, 3, 96, 95, 0, // Skip to: 86948 /* 62532 */ MCD_OPC_Decode, 193, 26, 183, 2, // Opcode: SRIv4i16_shift /* 62537 */ MCD_OPC_FilterValue, 3, 86, 95, 0, // Skip to: 86948 /* 62542 */ MCD_OPC_CheckPredicate, 3, 81, 95, 0, // Skip to: 86948 /* 62547 */ MCD_OPC_Decode, 230, 25, 184, 2, // Opcode: SQSHLUv4i16_shift /* 62552 */ MCD_OPC_FilterValue, 1, 71, 95, 0, // Skip to: 86948 /* 62557 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 62560 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62575 /* 62565 */ MCD_OPC_CheckPredicate, 3, 58, 95, 0, // Skip to: 86948 /* 62570 */ MCD_OPC_Decode, 139, 34, 179, 2, // Opcode: USHRv2i32_shift /* 62575 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62590 /* 62580 */ MCD_OPC_CheckPredicate, 3, 43, 95, 0, // Skip to: 86948 /* 62585 */ MCD_OPC_Decode, 235, 33, 179, 2, // Opcode: URSHRv2i32_shift /* 62590 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62605 /* 62595 */ MCD_OPC_CheckPredicate, 3, 28, 95, 0, // Skip to: 86948 /* 62600 */ MCD_OPC_Decode, 191, 26, 185, 2, // Opcode: SRIv2i32_shift /* 62605 */ MCD_OPC_FilterValue, 3, 18, 95, 0, // Skip to: 86948 /* 62610 */ MCD_OPC_CheckPredicate, 3, 13, 95, 0, // Skip to: 86948 /* 62615 */ MCD_OPC_Decode, 228, 25, 186, 2, // Opcode: SQSHLUv2i32_shift /* 62620 */ MCD_OPC_FilterValue, 1, 3, 95, 0, // Skip to: 86948 /* 62625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62628 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 62795 /* 62633 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62636 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 62727 /* 62641 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 62644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62659 /* 62649 */ MCD_OPC_CheckPredicate, 3, 230, 94, 0, // Skip to: 86948 /* 62654 */ MCD_OPC_Decode, 188, 2, 180, 2, // Opcode: BICv2i32 /* 62659 */ MCD_OPC_FilterValue, 1, 220, 94, 0, // Skip to: 86948 /* 62664 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 62667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62682 /* 62672 */ MCD_OPC_CheckPredicate, 3, 207, 94, 0, // Skip to: 86948 /* 62677 */ MCD_OPC_Decode, 163, 34, 181, 2, // Opcode: USRAv8i8_shift /* 62682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62697 /* 62687 */ MCD_OPC_CheckPredicate, 3, 192, 94, 0, // Skip to: 86948 /* 62692 */ MCD_OPC_Decode, 250, 33, 181, 2, // Opcode: URSRAv8i8_shift /* 62697 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62712 /* 62702 */ MCD_OPC_CheckPredicate, 3, 177, 94, 0, // Skip to: 86948 /* 62707 */ MCD_OPC_Decode, 166, 23, 193, 2, // Opcode: SLIv8i8_shift /* 62712 */ MCD_OPC_FilterValue, 3, 167, 94, 0, // Skip to: 86948 /* 62717 */ MCD_OPC_CheckPredicate, 3, 162, 94, 0, // Skip to: 86948 /* 62722 */ MCD_OPC_Decode, 179, 33, 182, 2, // Opcode: UQSHLv8i8_shift /* 62727 */ MCD_OPC_FilterValue, 1, 152, 94, 0, // Skip to: 86948 /* 62732 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 62735 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62750 /* 62740 */ MCD_OPC_CheckPredicate, 3, 139, 94, 0, // Skip to: 86948 /* 62745 */ MCD_OPC_Decode, 160, 34, 183, 2, // Opcode: USRAv4i16_shift /* 62750 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62765 /* 62755 */ MCD_OPC_CheckPredicate, 3, 124, 94, 0, // Skip to: 86948 /* 62760 */ MCD_OPC_Decode, 247, 33, 183, 2, // Opcode: URSRAv4i16_shift /* 62765 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62780 /* 62770 */ MCD_OPC_CheckPredicate, 3, 109, 94, 0, // Skip to: 86948 /* 62775 */ MCD_OPC_Decode, 163, 23, 194, 2, // Opcode: SLIv4i16_shift /* 62780 */ MCD_OPC_FilterValue, 3, 99, 94, 0, // Skip to: 86948 /* 62785 */ MCD_OPC_CheckPredicate, 3, 94, 94, 0, // Skip to: 86948 /* 62790 */ MCD_OPC_Decode, 173, 33, 184, 2, // Opcode: UQSHLv4i16_shift /* 62795 */ MCD_OPC_FilterValue, 1, 84, 94, 0, // Skip to: 86948 /* 62800 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 62803 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62818 /* 62808 */ MCD_OPC_CheckPredicate, 3, 71, 94, 0, // Skip to: 86948 /* 62813 */ MCD_OPC_Decode, 158, 34, 185, 2, // Opcode: USRAv2i32_shift /* 62818 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62833 /* 62823 */ MCD_OPC_CheckPredicate, 3, 56, 94, 0, // Skip to: 86948 /* 62828 */ MCD_OPC_Decode, 245, 33, 185, 2, // Opcode: URSRAv2i32_shift /* 62833 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62848 /* 62838 */ MCD_OPC_CheckPredicate, 3, 41, 94, 0, // Skip to: 86948 /* 62843 */ MCD_OPC_Decode, 161, 23, 195, 2, // Opcode: SLIv2i32_shift /* 62848 */ MCD_OPC_FilterValue, 3, 31, 94, 0, // Skip to: 86948 /* 62853 */ MCD_OPC_CheckPredicate, 3, 26, 94, 0, // Skip to: 86948 /* 62858 */ MCD_OPC_Decode, 169, 33, 186, 2, // Opcode: UQSHLv2i32_shift /* 62863 */ MCD_OPC_FilterValue, 1, 16, 94, 0, // Skip to: 86948 /* 62868 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 62871 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 63137 /* 62876 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 62879 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 63032 /* 62884 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 62887 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 62994 /* 62892 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 62895 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 62956 /* 62900 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 62903 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62918 /* 62908 */ MCD_OPC_CheckPredicate, 3, 227, 93, 0, // Skip to: 86948 /* 62913 */ MCD_OPC_Decode, 169, 20, 176, 2, // Opcode: MVNIv4i16 /* 62918 */ MCD_OPC_FilterValue, 1, 217, 93, 0, // Skip to: 86948 /* 62923 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 62926 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62941 /* 62931 */ MCD_OPC_CheckPredicate, 3, 204, 93, 0, // Skip to: 86948 /* 62936 */ MCD_OPC_Decode, 145, 26, 187, 2, // Opcode: SQSHRUNv8i8_shift /* 62941 */ MCD_OPC_FilterValue, 1, 194, 93, 0, // Skip to: 86948 /* 62946 */ MCD_OPC_CheckPredicate, 3, 189, 93, 0, // Skip to: 86948 /* 62951 */ MCD_OPC_Decode, 128, 34, 188, 2, // Opcode: USHLLv8i8_shift /* 62956 */ MCD_OPC_FilterValue, 1, 179, 93, 0, // Skip to: 86948 /* 62961 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 62964 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62979 /* 62969 */ MCD_OPC_CheckPredicate, 3, 166, 93, 0, // Skip to: 86948 /* 62974 */ MCD_OPC_Decode, 142, 26, 189, 2, // Opcode: SQSHRUNv4i16_shift /* 62979 */ MCD_OPC_FilterValue, 1, 156, 93, 0, // Skip to: 86948 /* 62984 */ MCD_OPC_CheckPredicate, 3, 151, 93, 0, // Skip to: 86948 /* 62989 */ MCD_OPC_Decode, 253, 33, 190, 2, // Opcode: USHLLv4i16_shift /* 62994 */ MCD_OPC_FilterValue, 1, 141, 93, 0, // Skip to: 86948 /* 62999 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 63002 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63017 /* 63007 */ MCD_OPC_CheckPredicate, 3, 128, 93, 0, // Skip to: 86948 /* 63012 */ MCD_OPC_Decode, 141, 26, 191, 2, // Opcode: SQSHRUNv2i32_shift /* 63017 */ MCD_OPC_FilterValue, 1, 118, 93, 0, // Skip to: 86948 /* 63022 */ MCD_OPC_CheckPredicate, 3, 113, 93, 0, // Skip to: 86948 /* 63027 */ MCD_OPC_Decode, 252, 33, 192, 2, // Opcode: USHLLv2i32_shift /* 63032 */ MCD_OPC_FilterValue, 1, 103, 93, 0, // Skip to: 86948 /* 63037 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63040 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 63115 /* 63045 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63048 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63093 /* 63053 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 63056 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63071 /* 63061 */ MCD_OPC_CheckPredicate, 3, 74, 93, 0, // Skip to: 86948 /* 63066 */ MCD_OPC_Decode, 189, 2, 180, 2, // Opcode: BICv4i16 /* 63071 */ MCD_OPC_FilterValue, 1, 64, 93, 0, // Skip to: 86948 /* 63076 */ MCD_OPC_CheckPredicate, 3, 59, 93, 0, // Skip to: 86948 /* 63081 */ MCD_OPC_CheckField, 13, 1, 0, 52, 93, 0, // Skip to: 86948 /* 63088 */ MCD_OPC_Decode, 188, 33, 187, 2, // Opcode: UQSHRNv8i8_shift /* 63093 */ MCD_OPC_FilterValue, 1, 42, 93, 0, // Skip to: 86948 /* 63098 */ MCD_OPC_CheckPredicate, 3, 37, 93, 0, // Skip to: 86948 /* 63103 */ MCD_OPC_CheckField, 13, 1, 0, 30, 93, 0, // Skip to: 86948 /* 63110 */ MCD_OPC_Decode, 185, 33, 189, 2, // Opcode: UQSHRNv4i16_shift /* 63115 */ MCD_OPC_FilterValue, 1, 20, 93, 0, // Skip to: 86948 /* 63120 */ MCD_OPC_CheckPredicate, 3, 15, 93, 0, // Skip to: 86948 /* 63125 */ MCD_OPC_CheckField, 13, 1, 0, 8, 93, 0, // Skip to: 86948 /* 63132 */ MCD_OPC_Decode, 184, 33, 191, 2, // Opcode: UQSHRNv2i32_shift /* 63137 */ MCD_OPC_FilterValue, 1, 254, 92, 0, // Skip to: 86948 /* 63142 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 63145 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63167 /* 63150 */ MCD_OPC_CheckPredicate, 3, 241, 92, 0, // Skip to: 86948 /* 63155 */ MCD_OPC_CheckField, 19, 3, 0, 234, 92, 0, // Skip to: 86948 /* 63162 */ MCD_OPC_Decode, 168, 20, 176, 2, // Opcode: MVNIv2s_msl /* 63167 */ MCD_OPC_FilterValue, 1, 224, 92, 0, // Skip to: 86948 /* 63172 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63175 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 63234 /* 63180 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63183 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 63212 /* 63188 */ MCD_OPC_CheckPredicate, 3, 203, 92, 0, // Skip to: 86948 /* 63193 */ MCD_OPC_CheckField, 19, 1, 0, 196, 92, 0, // Skip to: 86948 /* 63200 */ MCD_OPC_CheckField, 12, 1, 0, 189, 92, 0, // Skip to: 86948 /* 63207 */ MCD_OPC_Decode, 233, 19, 176, 2, // Opcode: MOVID /* 63212 */ MCD_OPC_FilterValue, 1, 179, 92, 0, // Skip to: 86948 /* 63217 */ MCD_OPC_CheckPredicate, 4, 174, 92, 0, // Skip to: 86948 /* 63222 */ MCD_OPC_CheckField, 12, 1, 0, 167, 92, 0, // Skip to: 86948 /* 63229 */ MCD_OPC_Decode, 202, 31, 178, 2, // Opcode: UCVTFv4i16_shift /* 63234 */ MCD_OPC_FilterValue, 1, 157, 92, 0, // Skip to: 86948 /* 63239 */ MCD_OPC_CheckPredicate, 3, 152, 92, 0, // Skip to: 86948 /* 63244 */ MCD_OPC_CheckField, 12, 1, 0, 145, 92, 0, // Skip to: 86948 /* 63251 */ MCD_OPC_Decode, 198, 31, 179, 2, // Opcode: UCVTFv2i32_shift /* 63256 */ MCD_OPC_FilterValue, 1, 135, 92, 0, // Skip to: 86948 /* 63261 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 63264 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 63332 /* 63269 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63272 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63317 /* 63277 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63280 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63302 /* 63285 */ MCD_OPC_CheckPredicate, 3, 106, 92, 0, // Skip to: 86948 /* 63290 */ MCD_OPC_CheckField, 19, 1, 1, 99, 92, 0, // Skip to: 86948 /* 63297 */ MCD_OPC_Decode, 222, 25, 187, 2, // Opcode: SQRSHRUNv8i8_shift /* 63302 */ MCD_OPC_FilterValue, 1, 89, 92, 0, // Skip to: 86948 /* 63307 */ MCD_OPC_CheckPredicate, 3, 84, 92, 0, // Skip to: 86948 /* 63312 */ MCD_OPC_Decode, 219, 25, 189, 2, // Opcode: SQRSHRUNv4i16_shift /* 63317 */ MCD_OPC_FilterValue, 1, 74, 92, 0, // Skip to: 86948 /* 63322 */ MCD_OPC_CheckPredicate, 3, 69, 92, 0, // Skip to: 86948 /* 63327 */ MCD_OPC_Decode, 218, 25, 191, 2, // Opcode: SQRSHRUNv2i32_shift /* 63332 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 63400 /* 63337 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63340 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63385 /* 63345 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63348 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63370 /* 63353 */ MCD_OPC_CheckPredicate, 3, 38, 92, 0, // Skip to: 86948 /* 63358 */ MCD_OPC_CheckField, 19, 1, 1, 31, 92, 0, // Skip to: 86948 /* 63365 */ MCD_OPC_Decode, 157, 33, 187, 2, // Opcode: UQRSHRNv8i8_shift /* 63370 */ MCD_OPC_FilterValue, 1, 21, 92, 0, // Skip to: 86948 /* 63375 */ MCD_OPC_CheckPredicate, 3, 16, 92, 0, // Skip to: 86948 /* 63380 */ MCD_OPC_Decode, 154, 33, 189, 2, // Opcode: UQRSHRNv4i16_shift /* 63385 */ MCD_OPC_FilterValue, 1, 6, 92, 0, // Skip to: 86948 /* 63390 */ MCD_OPC_CheckPredicate, 3, 1, 92, 0, // Skip to: 86948 /* 63395 */ MCD_OPC_Decode, 153, 33, 191, 2, // Opcode: UQRSHRNv2i32_shift /* 63400 */ MCD_OPC_FilterValue, 15, 247, 91, 0, // Skip to: 86948 /* 63405 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63430 /* 63413 */ MCD_OPC_CheckPredicate, 4, 234, 91, 0, // Skip to: 86948 /* 63418 */ MCD_OPC_CheckField, 20, 1, 1, 227, 91, 0, // Skip to: 86948 /* 63425 */ MCD_OPC_Decode, 156, 9, 178, 2, // Opcode: FCVTZUv4i16_shift /* 63430 */ MCD_OPC_FilterValue, 1, 217, 91, 0, // Skip to: 86948 /* 63435 */ MCD_OPC_CheckPredicate, 3, 212, 91, 0, // Skip to: 86948 /* 63440 */ MCD_OPC_Decode, 152, 9, 179, 2, // Opcode: FCVTZUv2i32_shift /* 63445 */ MCD_OPC_FilterValue, 2, 66, 4, 0, // Skip to: 64540 /* 63450 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 63453 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 63506 /* 63458 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 63461 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63476 /* 63466 */ MCD_OPC_CheckPredicate, 4, 181, 91, 0, // Skip to: 86948 /* 63471 */ MCD_OPC_Decode, 195, 10, 196, 2, // Opcode: FMLAv8i16_indexed /* 63476 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 63491 /* 63481 */ MCD_OPC_CheckPredicate, 4, 166, 91, 0, // Skip to: 86948 /* 63486 */ MCD_OPC_Decode, 214, 10, 196, 2, // Opcode: FMLSv8i16_indexed /* 63491 */ MCD_OPC_FilterValue, 9, 156, 91, 0, // Skip to: 86948 /* 63496 */ MCD_OPC_CheckPredicate, 4, 151, 91, 0, // Skip to: 86948 /* 63501 */ MCD_OPC_Decode, 163, 11, 197, 2, // Opcode: FMULv8i16_indexed /* 63506 */ MCD_OPC_FilterValue, 1, 141, 91, 0, // Skip to: 86948 /* 63511 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 63514 */ MCD_OPC_FilterValue, 0, 41, 3, 0, // Skip to: 64328 /* 63519 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 63522 */ MCD_OPC_FilterValue, 0, 143, 1, 0, // Skip to: 63926 /* 63527 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 63530 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 63683 /* 63535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63538 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 63645 /* 63543 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63546 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 63607 /* 63551 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 63554 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63569 /* 63559 */ MCD_OPC_CheckPredicate, 3, 88, 91, 0, // Skip to: 86948 /* 63564 */ MCD_OPC_Decode, 239, 19, 176, 2, // Opcode: MOVIv4i32 /* 63569 */ MCD_OPC_FilterValue, 1, 78, 91, 0, // Skip to: 86948 /* 63574 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 63577 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63592 /* 63582 */ MCD_OPC_CheckPredicate, 3, 65, 91, 0, // Skip to: 86948 /* 63587 */ MCD_OPC_Decode, 236, 26, 198, 2, // Opcode: SSHRv16i8_shift /* 63592 */ MCD_OPC_FilterValue, 1, 55, 91, 0, // Skip to: 86948 /* 63597 */ MCD_OPC_CheckPredicate, 3, 50, 91, 0, // Skip to: 86948 /* 63602 */ MCD_OPC_Decode, 206, 26, 198, 2, // Opcode: SRSHRv16i8_shift /* 63607 */ MCD_OPC_FilterValue, 1, 40, 91, 0, // Skip to: 86948 /* 63612 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 63615 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63630 /* 63620 */ MCD_OPC_CheckPredicate, 3, 27, 91, 0, // Skip to: 86948 /* 63625 */ MCD_OPC_Decode, 241, 26, 199, 2, // Opcode: SSHRv8i16_shift /* 63630 */ MCD_OPC_FilterValue, 1, 17, 91, 0, // Skip to: 86948 /* 63635 */ MCD_OPC_CheckPredicate, 3, 12, 91, 0, // Skip to: 86948 /* 63640 */ MCD_OPC_Decode, 211, 26, 199, 2, // Opcode: SRSHRv8i16_shift /* 63645 */ MCD_OPC_FilterValue, 1, 2, 91, 0, // Skip to: 86948 /* 63650 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 63653 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63668 /* 63658 */ MCD_OPC_CheckPredicate, 3, 245, 90, 0, // Skip to: 86948 /* 63663 */ MCD_OPC_Decode, 240, 26, 200, 2, // Opcode: SSHRv4i32_shift /* 63668 */ MCD_OPC_FilterValue, 1, 235, 90, 0, // Skip to: 86948 /* 63673 */ MCD_OPC_CheckPredicate, 3, 230, 90, 0, // Skip to: 86948 /* 63678 */ MCD_OPC_Decode, 210, 26, 200, 2, // Opcode: SRSHRv4i32_shift /* 63683 */ MCD_OPC_FilterValue, 1, 220, 90, 0, // Skip to: 86948 /* 63688 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63691 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 63858 /* 63696 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63699 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 63790 /* 63704 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 63707 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63722 /* 63712 */ MCD_OPC_CheckPredicate, 3, 191, 90, 0, // Skip to: 86948 /* 63717 */ MCD_OPC_Decode, 220, 20, 180, 2, // Opcode: ORRv4i32 /* 63722 */ MCD_OPC_FilterValue, 1, 181, 90, 0, // Skip to: 86948 /* 63727 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 63730 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63745 /* 63735 */ MCD_OPC_CheckPredicate, 3, 168, 90, 0, // Skip to: 86948 /* 63740 */ MCD_OPC_Decode, 244, 26, 201, 2, // Opcode: SSRAv16i8_shift /* 63745 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63760 /* 63750 */ MCD_OPC_CheckPredicate, 3, 153, 90, 0, // Skip to: 86948 /* 63755 */ MCD_OPC_Decode, 214, 26, 201, 2, // Opcode: SRSRAv16i8_shift /* 63760 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63775 /* 63765 */ MCD_OPC_CheckPredicate, 3, 138, 90, 0, // Skip to: 86948 /* 63770 */ MCD_OPC_Decode, 140, 23, 202, 2, // Opcode: SHLv16i8_shift /* 63775 */ MCD_OPC_FilterValue, 3, 128, 90, 0, // Skip to: 86948 /* 63780 */ MCD_OPC_CheckPredicate, 3, 123, 90, 0, // Skip to: 86948 /* 63785 */ MCD_OPC_Decode, 239, 25, 202, 2, // Opcode: SQSHLv16i8_shift /* 63790 */ MCD_OPC_FilterValue, 1, 113, 90, 0, // Skip to: 86948 /* 63795 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 63798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63813 /* 63803 */ MCD_OPC_CheckPredicate, 3, 100, 90, 0, // Skip to: 86948 /* 63808 */ MCD_OPC_Decode, 249, 26, 203, 2, // Opcode: SSRAv8i16_shift /* 63813 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63828 /* 63818 */ MCD_OPC_CheckPredicate, 3, 85, 90, 0, // Skip to: 86948 /* 63823 */ MCD_OPC_Decode, 219, 26, 203, 2, // Opcode: SRSRAv8i16_shift /* 63828 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63843 /* 63833 */ MCD_OPC_CheckPredicate, 3, 70, 90, 0, // Skip to: 86948 /* 63838 */ MCD_OPC_Decode, 145, 23, 204, 2, // Opcode: SHLv8i16_shift /* 63843 */ MCD_OPC_FilterValue, 3, 60, 90, 0, // Skip to: 86948 /* 63848 */ MCD_OPC_CheckPredicate, 3, 55, 90, 0, // Skip to: 86948 /* 63853 */ MCD_OPC_Decode, 253, 25, 204, 2, // Opcode: SQSHLv8i16_shift /* 63858 */ MCD_OPC_FilterValue, 1, 45, 90, 0, // Skip to: 86948 /* 63863 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 63866 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63881 /* 63871 */ MCD_OPC_CheckPredicate, 3, 32, 90, 0, // Skip to: 86948 /* 63876 */ MCD_OPC_Decode, 248, 26, 205, 2, // Opcode: SSRAv4i32_shift /* 63881 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63896 /* 63886 */ MCD_OPC_CheckPredicate, 3, 17, 90, 0, // Skip to: 86948 /* 63891 */ MCD_OPC_Decode, 218, 26, 205, 2, // Opcode: SRSRAv4i32_shift /* 63896 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63911 /* 63901 */ MCD_OPC_CheckPredicate, 3, 2, 90, 0, // Skip to: 86948 /* 63906 */ MCD_OPC_Decode, 144, 23, 206, 2, // Opcode: SHLv4i32_shift /* 63911 */ MCD_OPC_FilterValue, 3, 248, 89, 0, // Skip to: 86948 /* 63916 */ MCD_OPC_CheckPredicate, 3, 243, 89, 0, // Skip to: 86948 /* 63921 */ MCD_OPC_Decode, 251, 25, 206, 2, // Opcode: SQSHLv4i32_shift /* 63926 */ MCD_OPC_FilterValue, 1, 233, 89, 0, // Skip to: 86948 /* 63931 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 63934 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 64200 /* 63939 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 63942 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 64095 /* 63947 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 63950 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 64057 /* 63955 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 63958 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 64019 /* 63963 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 63966 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63981 /* 63971 */ MCD_OPC_CheckPredicate, 3, 188, 89, 0, // Skip to: 86948 /* 63976 */ MCD_OPC_Decode, 242, 19, 176, 2, // Opcode: MOVIv8i16 /* 63981 */ MCD_OPC_FilterValue, 1, 178, 89, 0, // Skip to: 86948 /* 63986 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 63989 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64004 /* 63994 */ MCD_OPC_CheckPredicate, 3, 165, 89, 0, // Skip to: 86948 /* 63999 */ MCD_OPC_Decode, 147, 23, 207, 2, // Opcode: SHRNv16i8_shift /* 64004 */ MCD_OPC_FilterValue, 1, 155, 89, 0, // Skip to: 86948 /* 64009 */ MCD_OPC_CheckPredicate, 3, 150, 89, 0, // Skip to: 86948 /* 64014 */ MCD_OPC_Decode, 221, 26, 202, 2, // Opcode: SSHLLv16i8_shift /* 64019 */ MCD_OPC_FilterValue, 1, 140, 89, 0, // Skip to: 86948 /* 64024 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 64027 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64042 /* 64032 */ MCD_OPC_CheckPredicate, 3, 127, 89, 0, // Skip to: 86948 /* 64037 */ MCD_OPC_Decode, 151, 23, 208, 2, // Opcode: SHRNv8i16_shift /* 64042 */ MCD_OPC_FilterValue, 1, 117, 89, 0, // Skip to: 86948 /* 64047 */ MCD_OPC_CheckPredicate, 3, 112, 89, 0, // Skip to: 86948 /* 64052 */ MCD_OPC_Decode, 225, 26, 204, 2, // Opcode: SSHLLv8i16_shift /* 64057 */ MCD_OPC_FilterValue, 1, 102, 89, 0, // Skip to: 86948 /* 64062 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 64065 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64080 /* 64070 */ MCD_OPC_CheckPredicate, 3, 89, 89, 0, // Skip to: 86948 /* 64075 */ MCD_OPC_Decode, 150, 23, 209, 2, // Opcode: SHRNv4i32_shift /* 64080 */ MCD_OPC_FilterValue, 1, 79, 89, 0, // Skip to: 86948 /* 64085 */ MCD_OPC_CheckPredicate, 3, 74, 89, 0, // Skip to: 86948 /* 64090 */ MCD_OPC_Decode, 224, 26, 206, 2, // Opcode: SSHLLv4i32_shift /* 64095 */ MCD_OPC_FilterValue, 1, 64, 89, 0, // Skip to: 86948 /* 64100 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64103 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 64178 /* 64108 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64111 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64156 /* 64116 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 64119 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64134 /* 64124 */ MCD_OPC_CheckPredicate, 3, 35, 89, 0, // Skip to: 86948 /* 64129 */ MCD_OPC_Decode, 221, 20, 180, 2, // Opcode: ORRv8i16 /* 64134 */ MCD_OPC_FilterValue, 1, 25, 89, 0, // Skip to: 86948 /* 64139 */ MCD_OPC_CheckPredicate, 3, 20, 89, 0, // Skip to: 86948 /* 64144 */ MCD_OPC_CheckField, 13, 1, 0, 13, 89, 0, // Skip to: 86948 /* 64151 */ MCD_OPC_Decode, 131, 26, 207, 2, // Opcode: SQSHRNv16i8_shift /* 64156 */ MCD_OPC_FilterValue, 1, 3, 89, 0, // Skip to: 86948 /* 64161 */ MCD_OPC_CheckPredicate, 3, 254, 88, 0, // Skip to: 86948 /* 64166 */ MCD_OPC_CheckField, 13, 1, 0, 247, 88, 0, // Skip to: 86948 /* 64173 */ MCD_OPC_Decode, 135, 26, 208, 2, // Opcode: SQSHRNv8i16_shift /* 64178 */ MCD_OPC_FilterValue, 1, 237, 88, 0, // Skip to: 86948 /* 64183 */ MCD_OPC_CheckPredicate, 3, 232, 88, 0, // Skip to: 86948 /* 64188 */ MCD_OPC_CheckField, 13, 1, 0, 225, 88, 0, // Skip to: 86948 /* 64195 */ MCD_OPC_Decode, 134, 26, 209, 2, // Opcode: SQSHRNv4i32_shift /* 64200 */ MCD_OPC_FilterValue, 1, 215, 88, 0, // Skip to: 86948 /* 64205 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 64208 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64230 /* 64213 */ MCD_OPC_CheckPredicate, 3, 202, 88, 0, // Skip to: 86948 /* 64218 */ MCD_OPC_CheckField, 19, 3, 0, 195, 88, 0, // Skip to: 86948 /* 64225 */ MCD_OPC_Decode, 240, 19, 176, 2, // Opcode: MOVIv4s_msl /* 64230 */ MCD_OPC_FilterValue, 1, 185, 88, 0, // Skip to: 86948 /* 64235 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 64238 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 64306 /* 64243 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64246 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64291 /* 64251 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64254 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64276 /* 64259 */ MCD_OPC_CheckPredicate, 3, 156, 88, 0, // Skip to: 86948 /* 64264 */ MCD_OPC_CheckField, 19, 1, 0, 149, 88, 0, // Skip to: 86948 /* 64271 */ MCD_OPC_Decode, 234, 19, 176, 2, // Opcode: MOVIv16b_ns /* 64276 */ MCD_OPC_FilterValue, 1, 139, 88, 0, // Skip to: 86948 /* 64281 */ MCD_OPC_CheckPredicate, 4, 134, 88, 0, // Skip to: 86948 /* 64286 */ MCD_OPC_Decode, 218, 22, 199, 2, // Opcode: SCVTFv8i16_shift /* 64291 */ MCD_OPC_FilterValue, 1, 124, 88, 0, // Skip to: 86948 /* 64296 */ MCD_OPC_CheckPredicate, 3, 119, 88, 0, // Skip to: 86948 /* 64301 */ MCD_OPC_Decode, 216, 22, 200, 2, // Opcode: SCVTFv4i32_shift /* 64306 */ MCD_OPC_FilterValue, 1, 109, 88, 0, // Skip to: 86948 /* 64311 */ MCD_OPC_CheckPredicate, 3, 104, 88, 0, // Skip to: 86948 /* 64316 */ MCD_OPC_CheckField, 19, 3, 0, 97, 88, 0, // Skip to: 86948 /* 64323 */ MCD_OPC_Decode, 237, 10, 176, 2, // Opcode: FMOVv4f32_ns /* 64328 */ MCD_OPC_FilterValue, 1, 87, 88, 0, // Skip to: 86948 /* 64333 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 64336 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 64404 /* 64341 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64344 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64389 /* 64349 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64352 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64374 /* 64357 */ MCD_OPC_CheckPredicate, 3, 58, 88, 0, // Skip to: 86948 /* 64362 */ MCD_OPC_CheckField, 19, 1, 1, 51, 88, 0, // Skip to: 86948 /* 64369 */ MCD_OPC_Decode, 234, 21, 207, 2, // Opcode: RSHRNv16i8_shift /* 64374 */ MCD_OPC_FilterValue, 1, 41, 88, 0, // Skip to: 86948 /* 64379 */ MCD_OPC_CheckPredicate, 3, 36, 88, 0, // Skip to: 86948 /* 64384 */ MCD_OPC_Decode, 238, 21, 208, 2, // Opcode: RSHRNv8i16_shift /* 64389 */ MCD_OPC_FilterValue, 1, 26, 88, 0, // Skip to: 86948 /* 64394 */ MCD_OPC_CheckPredicate, 3, 21, 88, 0, // Skip to: 86948 /* 64399 */ MCD_OPC_Decode, 237, 21, 209, 2, // Opcode: RSHRNv4i32_shift /* 64404 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 64472 /* 64409 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64412 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64457 /* 64417 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64420 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64442 /* 64425 */ MCD_OPC_CheckPredicate, 3, 246, 87, 0, // Skip to: 86948 /* 64430 */ MCD_OPC_CheckField, 19, 1, 1, 239, 87, 0, // Skip to: 86948 /* 64437 */ MCD_OPC_Decode, 208, 25, 207, 2, // Opcode: SQRSHRNv16i8_shift /* 64442 */ MCD_OPC_FilterValue, 1, 229, 87, 0, // Skip to: 86948 /* 64447 */ MCD_OPC_CheckPredicate, 3, 224, 87, 0, // Skip to: 86948 /* 64452 */ MCD_OPC_Decode, 212, 25, 208, 2, // Opcode: SQRSHRNv8i16_shift /* 64457 */ MCD_OPC_FilterValue, 1, 214, 87, 0, // Skip to: 86948 /* 64462 */ MCD_OPC_CheckPredicate, 3, 209, 87, 0, // Skip to: 86948 /* 64467 */ MCD_OPC_Decode, 211, 25, 209, 2, // Opcode: SQRSHRNv4i32_shift /* 64472 */ MCD_OPC_FilterValue, 15, 199, 87, 0, // Skip to: 86948 /* 64477 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64480 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64525 /* 64485 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64488 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64510 /* 64493 */ MCD_OPC_CheckPredicate, 4, 178, 87, 0, // Skip to: 86948 /* 64498 */ MCD_OPC_CheckField, 19, 1, 0, 171, 87, 0, // Skip to: 86948 /* 64505 */ MCD_OPC_Decode, 238, 10, 176, 2, // Opcode: FMOVv8f16_ns /* 64510 */ MCD_OPC_FilterValue, 1, 161, 87, 0, // Skip to: 86948 /* 64515 */ MCD_OPC_CheckPredicate, 4, 156, 87, 0, // Skip to: 86948 /* 64520 */ MCD_OPC_Decode, 252, 8, 199, 2, // Opcode: FCVTZSv8i16_shift /* 64525 */ MCD_OPC_FilterValue, 1, 146, 87, 0, // Skip to: 86948 /* 64530 */ MCD_OPC_CheckPredicate, 3, 141, 87, 0, // Skip to: 86948 /* 64535 */ MCD_OPC_Decode, 250, 8, 200, 2, // Opcode: FCVTZSv4i32_shift /* 64540 */ MCD_OPC_FilterValue, 3, 131, 87, 0, // Skip to: 86948 /* 64545 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 64548 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64570 /* 64553 */ MCD_OPC_CheckPredicate, 4, 118, 87, 0, // Skip to: 86948 /* 64558 */ MCD_OPC_CheckField, 12, 4, 9, 111, 87, 0, // Skip to: 86948 /* 64565 */ MCD_OPC_Decode, 138, 11, 197, 2, // Opcode: FMULXv8i16_indexed /* 64570 */ MCD_OPC_FilterValue, 1, 101, 87, 0, // Skip to: 86948 /* 64575 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 64578 */ MCD_OPC_FilterValue, 0, 131, 3, 0, // Skip to: 65482 /* 64583 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 64586 */ MCD_OPC_FilterValue, 0, 233, 1, 0, // Skip to: 65080 /* 64591 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 64594 */ MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 64837 /* 64599 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64602 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 64769 /* 64607 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64610 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 64701 /* 64615 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 64618 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64633 /* 64623 */ MCD_OPC_CheckPredicate, 3, 48, 87, 0, // Skip to: 86948 /* 64628 */ MCD_OPC_Decode, 170, 20, 176, 2, // Opcode: MVNIv4i32 /* 64633 */ MCD_OPC_FilterValue, 1, 38, 87, 0, // Skip to: 86948 /* 64638 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 64641 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64656 /* 64646 */ MCD_OPC_CheckPredicate, 3, 25, 87, 0, // Skip to: 86948 /* 64651 */ MCD_OPC_Decode, 138, 34, 198, 2, // Opcode: USHRv16i8_shift /* 64656 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64671 /* 64661 */ MCD_OPC_CheckPredicate, 3, 10, 87, 0, // Skip to: 86948 /* 64666 */ MCD_OPC_Decode, 234, 33, 198, 2, // Opcode: URSHRv16i8_shift /* 64671 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64686 /* 64676 */ MCD_OPC_CheckPredicate, 3, 251, 86, 0, // Skip to: 86948 /* 64681 */ MCD_OPC_Decode, 190, 26, 201, 2, // Opcode: SRIv16i8_shift /* 64686 */ MCD_OPC_FilterValue, 3, 241, 86, 0, // Skip to: 86948 /* 64691 */ MCD_OPC_CheckPredicate, 3, 236, 86, 0, // Skip to: 86948 /* 64696 */ MCD_OPC_Decode, 227, 25, 202, 2, // Opcode: SQSHLUv16i8_shift /* 64701 */ MCD_OPC_FilterValue, 1, 226, 86, 0, // Skip to: 86948 /* 64706 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 64709 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64724 /* 64714 */ MCD_OPC_CheckPredicate, 3, 213, 86, 0, // Skip to: 86948 /* 64719 */ MCD_OPC_Decode, 143, 34, 199, 2, // Opcode: USHRv8i16_shift /* 64724 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64739 /* 64729 */ MCD_OPC_CheckPredicate, 3, 198, 86, 0, // Skip to: 86948 /* 64734 */ MCD_OPC_Decode, 239, 33, 199, 2, // Opcode: URSHRv8i16_shift /* 64739 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64754 /* 64744 */ MCD_OPC_CheckPredicate, 3, 183, 86, 0, // Skip to: 86948 /* 64749 */ MCD_OPC_Decode, 195, 26, 203, 2, // Opcode: SRIv8i16_shift /* 64754 */ MCD_OPC_FilterValue, 3, 173, 86, 0, // Skip to: 86948 /* 64759 */ MCD_OPC_CheckPredicate, 3, 168, 86, 0, // Skip to: 86948 /* 64764 */ MCD_OPC_Decode, 232, 25, 204, 2, // Opcode: SQSHLUv8i16_shift /* 64769 */ MCD_OPC_FilterValue, 1, 158, 86, 0, // Skip to: 86948 /* 64774 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 64777 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64792 /* 64782 */ MCD_OPC_CheckPredicate, 3, 145, 86, 0, // Skip to: 86948 /* 64787 */ MCD_OPC_Decode, 142, 34, 200, 2, // Opcode: USHRv4i32_shift /* 64792 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64807 /* 64797 */ MCD_OPC_CheckPredicate, 3, 130, 86, 0, // Skip to: 86948 /* 64802 */ MCD_OPC_Decode, 238, 33, 200, 2, // Opcode: URSHRv4i32_shift /* 64807 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64822 /* 64812 */ MCD_OPC_CheckPredicate, 3, 115, 86, 0, // Skip to: 86948 /* 64817 */ MCD_OPC_Decode, 194, 26, 205, 2, // Opcode: SRIv4i32_shift /* 64822 */ MCD_OPC_FilterValue, 3, 105, 86, 0, // Skip to: 86948 /* 64827 */ MCD_OPC_CheckPredicate, 3, 100, 86, 0, // Skip to: 86948 /* 64832 */ MCD_OPC_Decode, 231, 25, 206, 2, // Opcode: SQSHLUv4i32_shift /* 64837 */ MCD_OPC_FilterValue, 1, 90, 86, 0, // Skip to: 86948 /* 64842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 64845 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 65012 /* 64850 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 64853 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 64944 /* 64858 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 64861 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64876 /* 64866 */ MCD_OPC_CheckPredicate, 3, 61, 86, 0, // Skip to: 86948 /* 64871 */ MCD_OPC_Decode, 190, 2, 180, 2, // Opcode: BICv4i32 /* 64876 */ MCD_OPC_FilterValue, 1, 51, 86, 0, // Skip to: 86948 /* 64881 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 64884 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64899 /* 64889 */ MCD_OPC_CheckPredicate, 3, 38, 86, 0, // Skip to: 86948 /* 64894 */ MCD_OPC_Decode, 157, 34, 201, 2, // Opcode: USRAv16i8_shift /* 64899 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64914 /* 64904 */ MCD_OPC_CheckPredicate, 3, 23, 86, 0, // Skip to: 86948 /* 64909 */ MCD_OPC_Decode, 244, 33, 201, 2, // Opcode: URSRAv16i8_shift /* 64914 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64929 /* 64919 */ MCD_OPC_CheckPredicate, 3, 8, 86, 0, // Skip to: 86948 /* 64924 */ MCD_OPC_Decode, 160, 23, 210, 2, // Opcode: SLIv16i8_shift /* 64929 */ MCD_OPC_FilterValue, 3, 254, 85, 0, // Skip to: 86948 /* 64934 */ MCD_OPC_CheckPredicate, 3, 249, 85, 0, // Skip to: 86948 /* 64939 */ MCD_OPC_Decode, 163, 33, 202, 2, // Opcode: UQSHLv16i8_shift /* 64944 */ MCD_OPC_FilterValue, 1, 239, 85, 0, // Skip to: 86948 /* 64949 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 64952 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64967 /* 64957 */ MCD_OPC_CheckPredicate, 3, 226, 85, 0, // Skip to: 86948 /* 64962 */ MCD_OPC_Decode, 162, 34, 203, 2, // Opcode: USRAv8i16_shift /* 64967 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64982 /* 64972 */ MCD_OPC_CheckPredicate, 3, 211, 85, 0, // Skip to: 86948 /* 64977 */ MCD_OPC_Decode, 249, 33, 203, 2, // Opcode: URSRAv8i16_shift /* 64982 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64997 /* 64987 */ MCD_OPC_CheckPredicate, 3, 196, 85, 0, // Skip to: 86948 /* 64992 */ MCD_OPC_Decode, 165, 23, 211, 2, // Opcode: SLIv8i16_shift /* 64997 */ MCD_OPC_FilterValue, 3, 186, 85, 0, // Skip to: 86948 /* 65002 */ MCD_OPC_CheckPredicate, 3, 181, 85, 0, // Skip to: 86948 /* 65007 */ MCD_OPC_Decode, 177, 33, 204, 2, // Opcode: UQSHLv8i16_shift /* 65012 */ MCD_OPC_FilterValue, 1, 171, 85, 0, // Skip to: 86948 /* 65017 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 65020 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65035 /* 65025 */ MCD_OPC_CheckPredicate, 3, 158, 85, 0, // Skip to: 86948 /* 65030 */ MCD_OPC_Decode, 161, 34, 205, 2, // Opcode: USRAv4i32_shift /* 65035 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 65050 /* 65040 */ MCD_OPC_CheckPredicate, 3, 143, 85, 0, // Skip to: 86948 /* 65045 */ MCD_OPC_Decode, 248, 33, 205, 2, // Opcode: URSRAv4i32_shift /* 65050 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 65065 /* 65055 */ MCD_OPC_CheckPredicate, 3, 128, 85, 0, // Skip to: 86948 /* 65060 */ MCD_OPC_Decode, 164, 23, 212, 2, // Opcode: SLIv4i32_shift /* 65065 */ MCD_OPC_FilterValue, 3, 118, 85, 0, // Skip to: 86948 /* 65070 */ MCD_OPC_CheckPredicate, 3, 113, 85, 0, // Skip to: 86948 /* 65075 */ MCD_OPC_Decode, 175, 33, 206, 2, // Opcode: UQSHLv4i32_shift /* 65080 */ MCD_OPC_FilterValue, 1, 103, 85, 0, // Skip to: 86948 /* 65085 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 65088 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 65354 /* 65093 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 65096 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 65249 /* 65101 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 65104 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 65211 /* 65109 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 65112 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 65173 /* 65117 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 65120 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65135 /* 65125 */ MCD_OPC_CheckPredicate, 3, 58, 85, 0, // Skip to: 86948 /* 65130 */ MCD_OPC_Decode, 172, 20, 176, 2, // Opcode: MVNIv8i16 /* 65135 */ MCD_OPC_FilterValue, 1, 48, 85, 0, // Skip to: 86948 /* 65140 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 65143 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65158 /* 65148 */ MCD_OPC_CheckPredicate, 3, 35, 85, 0, // Skip to: 86948 /* 65153 */ MCD_OPC_Decode, 140, 26, 207, 2, // Opcode: SQSHRUNv16i8_shift /* 65158 */ MCD_OPC_FilterValue, 1, 25, 85, 0, // Skip to: 86948 /* 65163 */ MCD_OPC_CheckPredicate, 3, 20, 85, 0, // Skip to: 86948 /* 65168 */ MCD_OPC_Decode, 251, 33, 202, 2, // Opcode: USHLLv16i8_shift /* 65173 */ MCD_OPC_FilterValue, 1, 10, 85, 0, // Skip to: 86948 /* 65178 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 65181 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65196 /* 65186 */ MCD_OPC_CheckPredicate, 3, 253, 84, 0, // Skip to: 86948 /* 65191 */ MCD_OPC_Decode, 144, 26, 208, 2, // Opcode: SQSHRUNv8i16_shift /* 65196 */ MCD_OPC_FilterValue, 1, 243, 84, 0, // Skip to: 86948 /* 65201 */ MCD_OPC_CheckPredicate, 3, 238, 84, 0, // Skip to: 86948 /* 65206 */ MCD_OPC_Decode, 255, 33, 204, 2, // Opcode: USHLLv8i16_shift /* 65211 */ MCD_OPC_FilterValue, 1, 228, 84, 0, // Skip to: 86948 /* 65216 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 65219 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65234 /* 65224 */ MCD_OPC_CheckPredicate, 3, 215, 84, 0, // Skip to: 86948 /* 65229 */ MCD_OPC_Decode, 143, 26, 209, 2, // Opcode: SQSHRUNv4i32_shift /* 65234 */ MCD_OPC_FilterValue, 1, 205, 84, 0, // Skip to: 86948 /* 65239 */ MCD_OPC_CheckPredicate, 3, 200, 84, 0, // Skip to: 86948 /* 65244 */ MCD_OPC_Decode, 254, 33, 206, 2, // Opcode: USHLLv4i32_shift /* 65249 */ MCD_OPC_FilterValue, 1, 190, 84, 0, // Skip to: 86948 /* 65254 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 65257 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 65332 /* 65262 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 65265 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65310 /* 65270 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 65273 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65288 /* 65278 */ MCD_OPC_CheckPredicate, 3, 161, 84, 0, // Skip to: 86948 /* 65283 */ MCD_OPC_Decode, 191, 2, 180, 2, // Opcode: BICv8i16 /* 65288 */ MCD_OPC_FilterValue, 1, 151, 84, 0, // Skip to: 86948 /* 65293 */ MCD_OPC_CheckPredicate, 3, 146, 84, 0, // Skip to: 86948 /* 65298 */ MCD_OPC_CheckField, 13, 1, 0, 139, 84, 0, // Skip to: 86948 /* 65305 */ MCD_OPC_Decode, 183, 33, 207, 2, // Opcode: UQSHRNv16i8_shift /* 65310 */ MCD_OPC_FilterValue, 1, 129, 84, 0, // Skip to: 86948 /* 65315 */ MCD_OPC_CheckPredicate, 3, 124, 84, 0, // Skip to: 86948 /* 65320 */ MCD_OPC_CheckField, 13, 1, 0, 117, 84, 0, // Skip to: 86948 /* 65327 */ MCD_OPC_Decode, 187, 33, 208, 2, // Opcode: UQSHRNv8i16_shift /* 65332 */ MCD_OPC_FilterValue, 1, 107, 84, 0, // Skip to: 86948 /* 65337 */ MCD_OPC_CheckPredicate, 3, 102, 84, 0, // Skip to: 86948 /* 65342 */ MCD_OPC_CheckField, 13, 1, 0, 95, 84, 0, // Skip to: 86948 /* 65349 */ MCD_OPC_Decode, 186, 33, 209, 2, // Opcode: UQSHRNv4i32_shift /* 65354 */ MCD_OPC_FilterValue, 1, 85, 84, 0, // Skip to: 86948 /* 65359 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 65362 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65384 /* 65367 */ MCD_OPC_CheckPredicate, 3, 72, 84, 0, // Skip to: 86948 /* 65372 */ MCD_OPC_CheckField, 19, 3, 0, 65, 84, 0, // Skip to: 86948 /* 65379 */ MCD_OPC_Decode, 171, 20, 176, 2, // Opcode: MVNIv4s_msl /* 65384 */ MCD_OPC_FilterValue, 1, 55, 84, 0, // Skip to: 86948 /* 65389 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 65392 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 65460 /* 65397 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 65400 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65445 /* 65405 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 65408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65430 /* 65413 */ MCD_OPC_CheckPredicate, 3, 26, 84, 0, // Skip to: 86948 /* 65418 */ MCD_OPC_CheckField, 19, 1, 0, 19, 84, 0, // Skip to: 86948 /* 65425 */ MCD_OPC_Decode, 235, 19, 176, 2, // Opcode: MOVIv2d_ns /* 65430 */ MCD_OPC_FilterValue, 1, 9, 84, 0, // Skip to: 86948 /* 65435 */ MCD_OPC_CheckPredicate, 4, 4, 84, 0, // Skip to: 86948 /* 65440 */ MCD_OPC_Decode, 205, 31, 199, 2, // Opcode: UCVTFv8i16_shift /* 65445 */ MCD_OPC_FilterValue, 1, 250, 83, 0, // Skip to: 86948 /* 65450 */ MCD_OPC_CheckPredicate, 3, 245, 83, 0, // Skip to: 86948 /* 65455 */ MCD_OPC_Decode, 203, 31, 200, 2, // Opcode: UCVTFv4i32_shift /* 65460 */ MCD_OPC_FilterValue, 1, 235, 83, 0, // Skip to: 86948 /* 65465 */ MCD_OPC_CheckPredicate, 3, 230, 83, 0, // Skip to: 86948 /* 65470 */ MCD_OPC_CheckField, 19, 3, 0, 223, 83, 0, // Skip to: 86948 /* 65477 */ MCD_OPC_Decode, 235, 10, 176, 2, // Opcode: FMOVv2f64_ns /* 65482 */ MCD_OPC_FilterValue, 1, 213, 83, 0, // Skip to: 86948 /* 65487 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 65490 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 65558 /* 65495 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 65498 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65543 /* 65503 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 65506 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65528 /* 65511 */ MCD_OPC_CheckPredicate, 3, 184, 83, 0, // Skip to: 86948 /* 65516 */ MCD_OPC_CheckField, 19, 1, 1, 177, 83, 0, // Skip to: 86948 /* 65523 */ MCD_OPC_Decode, 217, 25, 207, 2, // Opcode: SQRSHRUNv16i8_shift /* 65528 */ MCD_OPC_FilterValue, 1, 167, 83, 0, // Skip to: 86948 /* 65533 */ MCD_OPC_CheckPredicate, 3, 162, 83, 0, // Skip to: 86948 /* 65538 */ MCD_OPC_Decode, 221, 25, 208, 2, // Opcode: SQRSHRUNv8i16_shift /* 65543 */ MCD_OPC_FilterValue, 1, 152, 83, 0, // Skip to: 86948 /* 65548 */ MCD_OPC_CheckPredicate, 3, 147, 83, 0, // Skip to: 86948 /* 65553 */ MCD_OPC_Decode, 220, 25, 209, 2, // Opcode: SQRSHRUNv4i32_shift /* 65558 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 65626 /* 65563 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 65566 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65611 /* 65571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 65574 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65596 /* 65579 */ MCD_OPC_CheckPredicate, 3, 116, 83, 0, // Skip to: 86948 /* 65584 */ MCD_OPC_CheckField, 19, 1, 1, 109, 83, 0, // Skip to: 86948 /* 65591 */ MCD_OPC_Decode, 152, 33, 207, 2, // Opcode: UQRSHRNv16i8_shift /* 65596 */ MCD_OPC_FilterValue, 1, 99, 83, 0, // Skip to: 86948 /* 65601 */ MCD_OPC_CheckPredicate, 3, 94, 83, 0, // Skip to: 86948 /* 65606 */ MCD_OPC_Decode, 156, 33, 208, 2, // Opcode: UQRSHRNv8i16_shift /* 65611 */ MCD_OPC_FilterValue, 1, 84, 83, 0, // Skip to: 86948 /* 65616 */ MCD_OPC_CheckPredicate, 3, 79, 83, 0, // Skip to: 86948 /* 65621 */ MCD_OPC_Decode, 155, 33, 209, 2, // Opcode: UQRSHRNv4i32_shift /* 65626 */ MCD_OPC_FilterValue, 15, 69, 83, 0, // Skip to: 86948 /* 65631 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 65634 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65656 /* 65639 */ MCD_OPC_CheckPredicate, 4, 56, 83, 0, // Skip to: 86948 /* 65644 */ MCD_OPC_CheckField, 20, 1, 1, 49, 83, 0, // Skip to: 86948 /* 65651 */ MCD_OPC_Decode, 159, 9, 199, 2, // Opcode: FCVTZUv8i16_shift /* 65656 */ MCD_OPC_FilterValue, 1, 39, 83, 0, // Skip to: 86948 /* 65661 */ MCD_OPC_CheckPredicate, 3, 34, 83, 0, // Skip to: 86948 /* 65666 */ MCD_OPC_Decode, 157, 9, 200, 2, // Opcode: FCVTZUv4i32_shift /* 65671 */ MCD_OPC_FilterValue, 13, 96, 4, 0, // Skip to: 66796 /* 65676 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 65679 */ MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 65885 /* 65684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 65687 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 65709 /* 65692 */ MCD_OPC_CheckPredicate, 3, 3, 83, 0, // Skip to: 86948 /* 65697 */ MCD_OPC_CheckField, 10, 1, 0, 252, 82, 0, // Skip to: 86948 /* 65704 */ MCD_OPC_Decode, 239, 23, 213, 2, // Opcode: SMLALv4i16_indexed /* 65709 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 65731 /* 65714 */ MCD_OPC_CheckPredicate, 3, 237, 82, 0, // Skip to: 86948 /* 65719 */ MCD_OPC_CheckField, 10, 1, 0, 230, 82, 0, // Skip to: 86948 /* 65726 */ MCD_OPC_Decode, 211, 24, 213, 2, // Opcode: SQDMLALv4i16_indexed /* 65731 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 65753 /* 65736 */ MCD_OPC_CheckPredicate, 3, 215, 82, 0, // Skip to: 86948 /* 65741 */ MCD_OPC_CheckField, 10, 1, 0, 208, 82, 0, // Skip to: 86948 /* 65748 */ MCD_OPC_Decode, 249, 23, 213, 2, // Opcode: SMLSLv4i16_indexed /* 65753 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 65775 /* 65758 */ MCD_OPC_CheckPredicate, 3, 193, 82, 0, // Skip to: 86948 /* 65763 */ MCD_OPC_CheckField, 10, 1, 0, 186, 82, 0, // Skip to: 86948 /* 65770 */ MCD_OPC_Decode, 223, 24, 213, 2, // Opcode: SQDMLSLv4i16_indexed /* 65775 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 65797 /* 65780 */ MCD_OPC_CheckPredicate, 3, 171, 82, 0, // Skip to: 86948 /* 65785 */ MCD_OPC_CheckField, 10, 1, 0, 164, 82, 0, // Skip to: 86948 /* 65792 */ MCD_OPC_Decode, 161, 20, 175, 2, // Opcode: MULv4i16_indexed /* 65797 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 65819 /* 65802 */ MCD_OPC_CheckPredicate, 3, 149, 82, 0, // Skip to: 86948 /* 65807 */ MCD_OPC_CheckField, 10, 1, 0, 142, 82, 0, // Skip to: 86948 /* 65814 */ MCD_OPC_Decode, 142, 24, 214, 2, // Opcode: SMULLv4i16_indexed /* 65819 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 65841 /* 65824 */ MCD_OPC_CheckPredicate, 3, 127, 82, 0, // Skip to: 86948 /* 65829 */ MCD_OPC_CheckField, 10, 1, 0, 120, 82, 0, // Skip to: 86948 /* 65836 */ MCD_OPC_Decode, 247, 24, 214, 2, // Opcode: SQDMULLv4i16_indexed /* 65841 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 65863 /* 65846 */ MCD_OPC_CheckPredicate, 3, 105, 82, 0, // Skip to: 86948 /* 65851 */ MCD_OPC_CheckField, 10, 1, 0, 98, 82, 0, // Skip to: 86948 /* 65858 */ MCD_OPC_Decode, 236, 24, 175, 2, // Opcode: SQDMULHv4i16_indexed /* 65863 */ MCD_OPC_FilterValue, 13, 88, 82, 0, // Skip to: 86948 /* 65868 */ MCD_OPC_CheckPredicate, 3, 83, 82, 0, // Skip to: 86948 /* 65873 */ MCD_OPC_CheckField, 10, 1, 0, 76, 82, 0, // Skip to: 86948 /* 65880 */ MCD_OPC_Decode, 189, 25, 175, 2, // Opcode: SQRDMULHv4i16_indexed /* 65885 */ MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 66093 /* 65890 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 65893 */ MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 66011 /* 65898 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 65901 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65923 /* 65906 */ MCD_OPC_CheckPredicate, 3, 45, 82, 0, // Skip to: 86948 /* 65911 */ MCD_OPC_CheckField, 10, 1, 0, 38, 82, 0, // Skip to: 86948 /* 65918 */ MCD_OPC_Decode, 213, 19, 174, 2, // Opcode: MLAv4i16_indexed /* 65923 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 65945 /* 65928 */ MCD_OPC_CheckPredicate, 3, 23, 82, 0, // Skip to: 86948 /* 65933 */ MCD_OPC_CheckField, 10, 1, 0, 16, 82, 0, // Skip to: 86948 /* 65940 */ MCD_OPC_Decode, 166, 32, 213, 2, // Opcode: UMLALv4i16_indexed /* 65945 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 65967 /* 65950 */ MCD_OPC_CheckPredicate, 3, 1, 82, 0, // Skip to: 86948 /* 65955 */ MCD_OPC_CheckField, 10, 1, 0, 250, 81, 0, // Skip to: 86948 /* 65962 */ MCD_OPC_Decode, 227, 19, 174, 2, // Opcode: MLSv4i16_indexed /* 65967 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 65989 /* 65972 */ MCD_OPC_CheckPredicate, 3, 235, 81, 0, // Skip to: 86948 /* 65977 */ MCD_OPC_CheckField, 10, 1, 0, 228, 81, 0, // Skip to: 86948 /* 65984 */ MCD_OPC_Decode, 176, 32, 213, 2, // Opcode: UMLSLv4i16_indexed /* 65989 */ MCD_OPC_FilterValue, 5, 218, 81, 0, // Skip to: 86948 /* 65994 */ MCD_OPC_CheckPredicate, 3, 213, 81, 0, // Skip to: 86948 /* 65999 */ MCD_OPC_CheckField, 10, 1, 0, 206, 81, 0, // Skip to: 86948 /* 66006 */ MCD_OPC_Decode, 196, 32, 214, 2, // Opcode: UMULLv4i16_indexed /* 66011 */ MCD_OPC_FilterValue, 1, 196, 81, 0, // Skip to: 86948 /* 66016 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 66019 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 66041 /* 66024 */ MCD_OPC_CheckPredicate, 8, 183, 81, 0, // Skip to: 86948 /* 66029 */ MCD_OPC_CheckField, 10, 2, 0, 176, 81, 0, // Skip to: 86948 /* 66036 */ MCD_OPC_Decode, 163, 7, 215, 2, // Opcode: FCMLAv4f16_indexed /* 66041 */ MCD_OPC_FilterValue, 1, 166, 81, 0, // Skip to: 86948 /* 66046 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 66049 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 66071 /* 66054 */ MCD_OPC_CheckPredicate, 7, 153, 81, 0, // Skip to: 86948 /* 66059 */ MCD_OPC_CheckField, 10, 1, 0, 146, 81, 0, // Skip to: 86948 /* 66066 */ MCD_OPC_Decode, 165, 25, 174, 2, // Opcode: SQRDMLAHv4i16_indexed /* 66071 */ MCD_OPC_FilterValue, 3, 136, 81, 0, // Skip to: 86948 /* 66076 */ MCD_OPC_CheckPredicate, 7, 131, 81, 0, // Skip to: 86948 /* 66081 */ MCD_OPC_CheckField, 10, 1, 0, 124, 81, 0, // Skip to: 86948 /* 66088 */ MCD_OPC_Decode, 177, 25, 174, 2, // Opcode: SQRDMLSHv4i16_indexed /* 66093 */ MCD_OPC_FilterValue, 2, 124, 1, 0, // Skip to: 66478 /* 66098 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 66101 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 66123 /* 66106 */ MCD_OPC_CheckPredicate, 3, 101, 81, 0, // Skip to: 86948 /* 66111 */ MCD_OPC_CheckField, 10, 2, 1, 94, 81, 0, // Skip to: 86948 /* 66118 */ MCD_OPC_Decode, 238, 26, 216, 2, // Opcode: SSHRv2i64_shift /* 66123 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 66145 /* 66128 */ MCD_OPC_CheckPredicate, 3, 79, 81, 0, // Skip to: 86948 /* 66133 */ MCD_OPC_CheckField, 10, 2, 1, 72, 81, 0, // Skip to: 86948 /* 66140 */ MCD_OPC_Decode, 246, 26, 217, 2, // Opcode: SSRAv2i64_shift /* 66145 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 66190 /* 66150 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 66153 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66168 /* 66158 */ MCD_OPC_CheckPredicate, 3, 49, 81, 0, // Skip to: 86948 /* 66163 */ MCD_OPC_Decode, 243, 23, 196, 2, // Opcode: SMLALv8i16_indexed /* 66168 */ MCD_OPC_FilterValue, 1, 39, 81, 0, // Skip to: 86948 /* 66173 */ MCD_OPC_CheckPredicate, 3, 34, 81, 0, // Skip to: 86948 /* 66178 */ MCD_OPC_CheckField, 11, 1, 0, 27, 81, 0, // Skip to: 86948 /* 66185 */ MCD_OPC_Decode, 208, 26, 216, 2, // Opcode: SRSHRv2i64_shift /* 66190 */ MCD_OPC_FilterValue, 3, 40, 0, 0, // Skip to: 66235 /* 66195 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 66198 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66213 /* 66203 */ MCD_OPC_CheckPredicate, 3, 4, 81, 0, // Skip to: 86948 /* 66208 */ MCD_OPC_Decode, 215, 24, 196, 2, // Opcode: SQDMLALv8i16_indexed /* 66213 */ MCD_OPC_FilterValue, 1, 250, 80, 0, // Skip to: 86948 /* 66218 */ MCD_OPC_CheckPredicate, 3, 245, 80, 0, // Skip to: 86948 /* 66223 */ MCD_OPC_CheckField, 11, 1, 0, 238, 80, 0, // Skip to: 86948 /* 66230 */ MCD_OPC_Decode, 216, 26, 217, 2, // Opcode: SRSRAv2i64_shift /* 66235 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 66257 /* 66240 */ MCD_OPC_CheckPredicate, 3, 223, 80, 0, // Skip to: 86948 /* 66245 */ MCD_OPC_CheckField, 10, 2, 1, 216, 80, 0, // Skip to: 86948 /* 66252 */ MCD_OPC_Decode, 142, 23, 218, 2, // Opcode: SHLv2i64_shift /* 66257 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 66279 /* 66262 */ MCD_OPC_CheckPredicate, 3, 201, 80, 0, // Skip to: 86948 /* 66267 */ MCD_OPC_CheckField, 10, 1, 0, 194, 80, 0, // Skip to: 86948 /* 66274 */ MCD_OPC_Decode, 253, 23, 196, 2, // Opcode: SMLSLv8i16_indexed /* 66279 */ MCD_OPC_FilterValue, 7, 40, 0, 0, // Skip to: 66324 /* 66284 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 66287 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66302 /* 66292 */ MCD_OPC_CheckPredicate, 3, 171, 80, 0, // Skip to: 86948 /* 66297 */ MCD_OPC_Decode, 227, 24, 196, 2, // Opcode: SQDMLSLv8i16_indexed /* 66302 */ MCD_OPC_FilterValue, 1, 161, 80, 0, // Skip to: 86948 /* 66307 */ MCD_OPC_CheckPredicate, 3, 156, 80, 0, // Skip to: 86948 /* 66312 */ MCD_OPC_CheckField, 11, 1, 0, 149, 80, 0, // Skip to: 86948 /* 66319 */ MCD_OPC_Decode, 247, 25, 218, 2, // Opcode: SQSHLv2i64_shift /* 66324 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 66346 /* 66329 */ MCD_OPC_CheckPredicate, 3, 134, 80, 0, // Skip to: 86948 /* 66334 */ MCD_OPC_CheckField, 10, 1, 0, 127, 80, 0, // Skip to: 86948 /* 66341 */ MCD_OPC_Decode, 165, 20, 197, 2, // Opcode: MULv8i16_indexed /* 66346 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 66368 /* 66351 */ MCD_OPC_CheckPredicate, 3, 112, 80, 0, // Skip to: 86948 /* 66356 */ MCD_OPC_CheckField, 10, 1, 0, 105, 80, 0, // Skip to: 86948 /* 66363 */ MCD_OPC_Decode, 146, 24, 197, 2, // Opcode: SMULLv8i16_indexed /* 66368 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 66390 /* 66373 */ MCD_OPC_CheckPredicate, 3, 90, 80, 0, // Skip to: 86948 /* 66378 */ MCD_OPC_CheckField, 10, 1, 0, 83, 80, 0, // Skip to: 86948 /* 66385 */ MCD_OPC_Decode, 251, 24, 197, 2, // Opcode: SQDMULLv8i16_indexed /* 66390 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 66412 /* 66395 */ MCD_OPC_CheckPredicate, 3, 68, 80, 0, // Skip to: 86948 /* 66400 */ MCD_OPC_CheckField, 10, 1, 0, 61, 80, 0, // Skip to: 86948 /* 66407 */ MCD_OPC_Decode, 240, 24, 197, 2, // Opcode: SQDMULHv8i16_indexed /* 66412 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 66434 /* 66417 */ MCD_OPC_CheckPredicate, 3, 46, 80, 0, // Skip to: 86948 /* 66422 */ MCD_OPC_CheckField, 10, 1, 0, 39, 80, 0, // Skip to: 86948 /* 66429 */ MCD_OPC_Decode, 193, 25, 197, 2, // Opcode: SQRDMULHv8i16_indexed /* 66434 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 66456 /* 66439 */ MCD_OPC_CheckPredicate, 3, 24, 80, 0, // Skip to: 86948 /* 66444 */ MCD_OPC_CheckField, 10, 2, 1, 17, 80, 0, // Skip to: 86948 /* 66451 */ MCD_OPC_Decode, 212, 22, 216, 2, // Opcode: SCVTFv2i64_shift /* 66456 */ MCD_OPC_FilterValue, 15, 7, 80, 0, // Skip to: 86948 /* 66461 */ MCD_OPC_CheckPredicate, 3, 2, 80, 0, // Skip to: 86948 /* 66466 */ MCD_OPC_CheckField, 10, 2, 3, 251, 79, 0, // Skip to: 86948 /* 66473 */ MCD_OPC_Decode, 246, 8, 216, 2, // Opcode: FCVTZSv2i64_shift /* 66478 */ MCD_OPC_FilterValue, 3, 241, 79, 0, // Skip to: 86948 /* 66483 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 66486 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 66638 /* 66491 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 66494 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 66577 /* 66499 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 66502 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66517 /* 66507 */ MCD_OPC_CheckPredicate, 3, 212, 79, 0, // Skip to: 86948 /* 66512 */ MCD_OPC_Decode, 217, 19, 196, 2, // Opcode: MLAv8i16_indexed /* 66517 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 66532 /* 66522 */ MCD_OPC_CheckPredicate, 3, 197, 79, 0, // Skip to: 86948 /* 66527 */ MCD_OPC_Decode, 170, 32, 196, 2, // Opcode: UMLALv8i16_indexed /* 66532 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66547 /* 66537 */ MCD_OPC_CheckPredicate, 3, 182, 79, 0, // Skip to: 86948 /* 66542 */ MCD_OPC_Decode, 231, 19, 196, 2, // Opcode: MLSv8i16_indexed /* 66547 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 66562 /* 66552 */ MCD_OPC_CheckPredicate, 3, 167, 79, 0, // Skip to: 86948 /* 66557 */ MCD_OPC_Decode, 180, 32, 196, 2, // Opcode: UMLSLv8i16_indexed /* 66562 */ MCD_OPC_FilterValue, 5, 157, 79, 0, // Skip to: 86948 /* 66567 */ MCD_OPC_CheckPredicate, 3, 152, 79, 0, // Skip to: 86948 /* 66572 */ MCD_OPC_Decode, 200, 32, 197, 2, // Opcode: UMULLv8i16_indexed /* 66577 */ MCD_OPC_FilterValue, 1, 142, 79, 0, // Skip to: 86948 /* 66582 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 66585 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66600 /* 66590 */ MCD_OPC_CheckPredicate, 8, 129, 79, 0, // Skip to: 86948 /* 66595 */ MCD_OPC_Decode, 167, 7, 219, 2, // Opcode: FCMLAv8f16_indexed /* 66600 */ MCD_OPC_FilterValue, 1, 119, 79, 0, // Skip to: 86948 /* 66605 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 66608 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66623 /* 66613 */ MCD_OPC_CheckPredicate, 7, 106, 79, 0, // Skip to: 86948 /* 66618 */ MCD_OPC_Decode, 169, 25, 196, 2, // Opcode: SQRDMLAHv8i16_indexed /* 66623 */ MCD_OPC_FilterValue, 3, 96, 79, 0, // Skip to: 86948 /* 66628 */ MCD_OPC_CheckPredicate, 7, 91, 79, 0, // Skip to: 86948 /* 66633 */ MCD_OPC_Decode, 181, 25, 196, 2, // Opcode: SQRDMLSHv8i16_indexed /* 66638 */ MCD_OPC_FilterValue, 1, 81, 79, 0, // Skip to: 86948 /* 66643 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... /* 66646 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66661 /* 66651 */ MCD_OPC_CheckPredicate, 3, 68, 79, 0, // Skip to: 86948 /* 66656 */ MCD_OPC_Decode, 140, 34, 216, 2, // Opcode: USHRv2i64_shift /* 66661 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66676 /* 66666 */ MCD_OPC_CheckPredicate, 3, 53, 79, 0, // Skip to: 86948 /* 66671 */ MCD_OPC_Decode, 159, 34, 217, 2, // Opcode: USRAv2i64_shift /* 66676 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 66691 /* 66681 */ MCD_OPC_CheckPredicate, 3, 38, 79, 0, // Skip to: 86948 /* 66686 */ MCD_OPC_Decode, 236, 33, 216, 2, // Opcode: URSHRv2i64_shift /* 66691 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 66706 /* 66696 */ MCD_OPC_CheckPredicate, 3, 23, 79, 0, // Skip to: 86948 /* 66701 */ MCD_OPC_Decode, 246, 33, 217, 2, // Opcode: URSRAv2i64_shift /* 66706 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 66721 /* 66711 */ MCD_OPC_CheckPredicate, 3, 8, 79, 0, // Skip to: 86948 /* 66716 */ MCD_OPC_Decode, 192, 26, 217, 2, // Opcode: SRIv2i64_shift /* 66721 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 66736 /* 66726 */ MCD_OPC_CheckPredicate, 3, 249, 78, 0, // Skip to: 86948 /* 66731 */ MCD_OPC_Decode, 162, 23, 220, 2, // Opcode: SLIv2i64_shift /* 66736 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 66751 /* 66741 */ MCD_OPC_CheckPredicate, 3, 234, 78, 0, // Skip to: 86948 /* 66746 */ MCD_OPC_Decode, 229, 25, 218, 2, // Opcode: SQSHLUv2i64_shift /* 66751 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 66766 /* 66756 */ MCD_OPC_CheckPredicate, 3, 219, 78, 0, // Skip to: 86948 /* 66761 */ MCD_OPC_Decode, 171, 33, 218, 2, // Opcode: UQSHLv2i64_shift /* 66766 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 66781 /* 66771 */ MCD_OPC_CheckPredicate, 3, 204, 78, 0, // Skip to: 86948 /* 66776 */ MCD_OPC_Decode, 199, 31, 216, 2, // Opcode: UCVTFv2i64_shift /* 66781 */ MCD_OPC_FilterValue, 31, 194, 78, 0, // Skip to: 86948 /* 66786 */ MCD_OPC_CheckPredicate, 3, 189, 78, 0, // Skip to: 86948 /* 66791 */ MCD_OPC_Decode, 153, 9, 216, 2, // Opcode: FCVTZUv2i64_shift /* 66796 */ MCD_OPC_FilterValue, 14, 32, 4, 0, // Skip to: 67857 /* 66801 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 66804 */ MCD_OPC_FilterValue, 0, 33, 1, 0, // Skip to: 67098 /* 66809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 66812 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 66834 /* 66817 */ MCD_OPC_CheckPredicate, 3, 158, 78, 0, // Skip to: 86948 /* 66822 */ MCD_OPC_CheckField, 10, 1, 0, 151, 78, 0, // Skip to: 86948 /* 66829 */ MCD_OPC_Decode, 188, 10, 221, 2, // Opcode: FMLAv2i32_indexed /* 66834 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 66856 /* 66839 */ MCD_OPC_CheckPredicate, 3, 136, 78, 0, // Skip to: 86948 /* 66844 */ MCD_OPC_CheckField, 10, 1, 0, 129, 78, 0, // Skip to: 86948 /* 66851 */ MCD_OPC_Decode, 237, 23, 222, 2, // Opcode: SMLALv2i32_indexed /* 66856 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 66878 /* 66861 */ MCD_OPC_CheckPredicate, 3, 114, 78, 0, // Skip to: 86948 /* 66866 */ MCD_OPC_CheckField, 10, 1, 0, 107, 78, 0, // Skip to: 86948 /* 66873 */ MCD_OPC_Decode, 209, 24, 222, 2, // Opcode: SQDMLALv2i32_indexed /* 66878 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 66900 /* 66883 */ MCD_OPC_CheckPredicate, 3, 92, 78, 0, // Skip to: 86948 /* 66888 */ MCD_OPC_CheckField, 10, 1, 0, 85, 78, 0, // Skip to: 86948 /* 66895 */ MCD_OPC_Decode, 207, 10, 221, 2, // Opcode: FMLSv2i32_indexed /* 66900 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 66922 /* 66905 */ MCD_OPC_CheckPredicate, 3, 70, 78, 0, // Skip to: 86948 /* 66910 */ MCD_OPC_CheckField, 10, 1, 0, 63, 78, 0, // Skip to: 86948 /* 66917 */ MCD_OPC_Decode, 247, 23, 222, 2, // Opcode: SMLSLv2i32_indexed /* 66922 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 66944 /* 66927 */ MCD_OPC_CheckPredicate, 3, 48, 78, 0, // Skip to: 86948 /* 66932 */ MCD_OPC_CheckField, 10, 1, 0, 41, 78, 0, // Skip to: 86948 /* 66939 */ MCD_OPC_Decode, 221, 24, 222, 2, // Opcode: SQDMLSLv2i32_indexed /* 66944 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 66966 /* 66949 */ MCD_OPC_CheckPredicate, 3, 26, 78, 0, // Skip to: 86948 /* 66954 */ MCD_OPC_CheckField, 10, 1, 0, 19, 78, 0, // Skip to: 86948 /* 66961 */ MCD_OPC_Decode, 159, 20, 223, 2, // Opcode: MULv2i32_indexed /* 66966 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 66988 /* 66971 */ MCD_OPC_CheckPredicate, 3, 4, 78, 0, // Skip to: 86948 /* 66976 */ MCD_OPC_CheckField, 10, 1, 0, 253, 77, 0, // Skip to: 86948 /* 66983 */ MCD_OPC_Decode, 156, 11, 223, 2, // Opcode: FMULv2i32_indexed /* 66988 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67010 /* 66993 */ MCD_OPC_CheckPredicate, 3, 238, 77, 0, // Skip to: 86948 /* 66998 */ MCD_OPC_CheckField, 10, 1, 0, 231, 77, 0, // Skip to: 86948 /* 67005 */ MCD_OPC_Decode, 140, 24, 224, 2, // Opcode: SMULLv2i32_indexed /* 67010 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 67032 /* 67015 */ MCD_OPC_CheckPredicate, 3, 216, 77, 0, // Skip to: 86948 /* 67020 */ MCD_OPC_CheckField, 10, 1, 0, 209, 77, 0, // Skip to: 86948 /* 67027 */ MCD_OPC_Decode, 245, 24, 224, 2, // Opcode: SQDMULLv2i32_indexed /* 67032 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 67054 /* 67037 */ MCD_OPC_CheckPredicate, 3, 194, 77, 0, // Skip to: 86948 /* 67042 */ MCD_OPC_CheckField, 10, 1, 0, 187, 77, 0, // Skip to: 86948 /* 67049 */ MCD_OPC_Decode, 234, 24, 223, 2, // Opcode: SQDMULHv2i32_indexed /* 67054 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67076 /* 67059 */ MCD_OPC_CheckPredicate, 3, 172, 77, 0, // Skip to: 86948 /* 67064 */ MCD_OPC_CheckField, 10, 1, 0, 165, 77, 0, // Skip to: 86948 /* 67071 */ MCD_OPC_Decode, 187, 25, 223, 2, // Opcode: SQRDMULHv2i32_indexed /* 67076 */ MCD_OPC_FilterValue, 14, 155, 77, 0, // Skip to: 86948 /* 67081 */ MCD_OPC_CheckPredicate, 10, 150, 77, 0, // Skip to: 86948 /* 67086 */ MCD_OPC_CheckField, 10, 1, 0, 143, 77, 0, // Skip to: 86948 /* 67093 */ MCD_OPC_Decode, 230, 22, 221, 2, // Opcode: SDOTlanev8i8 /* 67098 */ MCD_OPC_FilterValue, 1, 201, 0, 0, // Skip to: 67304 /* 67103 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 67106 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67128 /* 67111 */ MCD_OPC_CheckPredicate, 3, 120, 77, 0, // Skip to: 86948 /* 67116 */ MCD_OPC_CheckField, 10, 1, 0, 113, 77, 0, // Skip to: 86948 /* 67123 */ MCD_OPC_Decode, 211, 19, 221, 2, // Opcode: MLAv2i32_indexed /* 67128 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67150 /* 67133 */ MCD_OPC_CheckPredicate, 3, 98, 77, 0, // Skip to: 86948 /* 67138 */ MCD_OPC_CheckField, 10, 1, 0, 91, 77, 0, // Skip to: 86948 /* 67145 */ MCD_OPC_Decode, 164, 32, 222, 2, // Opcode: UMLALv2i32_indexed /* 67150 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 67172 /* 67155 */ MCD_OPC_CheckPredicate, 3, 76, 77, 0, // Skip to: 86948 /* 67160 */ MCD_OPC_CheckField, 10, 1, 0, 69, 77, 0, // Skip to: 86948 /* 67167 */ MCD_OPC_Decode, 225, 19, 221, 2, // Opcode: MLSv2i32_indexed /* 67172 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 67194 /* 67177 */ MCD_OPC_CheckPredicate, 3, 54, 77, 0, // Skip to: 86948 /* 67182 */ MCD_OPC_CheckField, 10, 1, 0, 47, 77, 0, // Skip to: 86948 /* 67189 */ MCD_OPC_Decode, 174, 32, 222, 2, // Opcode: UMLSLv2i32_indexed /* 67194 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 67216 /* 67199 */ MCD_OPC_CheckPredicate, 3, 32, 77, 0, // Skip to: 86948 /* 67204 */ MCD_OPC_CheckField, 10, 1, 0, 25, 77, 0, // Skip to: 86948 /* 67211 */ MCD_OPC_Decode, 131, 11, 223, 2, // Opcode: FMULXv2i32_indexed /* 67216 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67238 /* 67221 */ MCD_OPC_CheckPredicate, 3, 10, 77, 0, // Skip to: 86948 /* 67226 */ MCD_OPC_CheckField, 10, 1, 0, 3, 77, 0, // Skip to: 86948 /* 67233 */ MCD_OPC_Decode, 194, 32, 224, 2, // Opcode: UMULLv2i32_indexed /* 67238 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67260 /* 67243 */ MCD_OPC_CheckPredicate, 7, 244, 76, 0, // Skip to: 86948 /* 67248 */ MCD_OPC_CheckField, 10, 1, 0, 237, 76, 0, // Skip to: 86948 /* 67255 */ MCD_OPC_Decode, 163, 25, 221, 2, // Opcode: SQRDMLAHv2i32_indexed /* 67260 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 67282 /* 67265 */ MCD_OPC_CheckPredicate, 10, 222, 76, 0, // Skip to: 86948 /* 67270 */ MCD_OPC_CheckField, 10, 1, 0, 215, 76, 0, // Skip to: 86948 /* 67277 */ MCD_OPC_Decode, 217, 31, 221, 2, // Opcode: UDOTlanev8i8 /* 67282 */ MCD_OPC_FilterValue, 15, 205, 76, 0, // Skip to: 86948 /* 67287 */ MCD_OPC_CheckPredicate, 7, 200, 76, 0, // Skip to: 86948 /* 67292 */ MCD_OPC_CheckField, 10, 1, 0, 193, 76, 0, // Skip to: 86948 /* 67299 */ MCD_OPC_Decode, 175, 25, 221, 2, // Opcode: SQRDMLSHv2i32_indexed /* 67304 */ MCD_OPC_FilterValue, 2, 33, 1, 0, // Skip to: 67598 /* 67309 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 67312 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 67334 /* 67317 */ MCD_OPC_CheckPredicate, 3, 170, 76, 0, // Skip to: 86948 /* 67322 */ MCD_OPC_CheckField, 10, 1, 0, 163, 76, 0, // Skip to: 86948 /* 67329 */ MCD_OPC_Decode, 193, 10, 225, 2, // Opcode: FMLAv4i32_indexed /* 67334 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67356 /* 67339 */ MCD_OPC_CheckPredicate, 3, 148, 76, 0, // Skip to: 86948 /* 67344 */ MCD_OPC_CheckField, 10, 1, 0, 141, 76, 0, // Skip to: 86948 /* 67351 */ MCD_OPC_Decode, 241, 23, 225, 2, // Opcode: SMLALv4i32_indexed /* 67356 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 67378 /* 67361 */ MCD_OPC_CheckPredicate, 3, 126, 76, 0, // Skip to: 86948 /* 67366 */ MCD_OPC_CheckField, 10, 1, 0, 119, 76, 0, // Skip to: 86948 /* 67373 */ MCD_OPC_Decode, 213, 24, 225, 2, // Opcode: SQDMLALv4i32_indexed /* 67378 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 67400 /* 67383 */ MCD_OPC_CheckPredicate, 3, 104, 76, 0, // Skip to: 86948 /* 67388 */ MCD_OPC_CheckField, 10, 1, 0, 97, 76, 0, // Skip to: 86948 /* 67395 */ MCD_OPC_Decode, 212, 10, 225, 2, // Opcode: FMLSv4i32_indexed /* 67400 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 67422 /* 67405 */ MCD_OPC_CheckPredicate, 3, 82, 76, 0, // Skip to: 86948 /* 67410 */ MCD_OPC_CheckField, 10, 1, 0, 75, 76, 0, // Skip to: 86948 /* 67417 */ MCD_OPC_Decode, 251, 23, 225, 2, // Opcode: SMLSLv4i32_indexed /* 67422 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 67444 /* 67427 */ MCD_OPC_CheckPredicate, 3, 60, 76, 0, // Skip to: 86948 /* 67432 */ MCD_OPC_CheckField, 10, 1, 0, 53, 76, 0, // Skip to: 86948 /* 67439 */ MCD_OPC_Decode, 225, 24, 225, 2, // Opcode: SQDMLSLv4i32_indexed /* 67444 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 67466 /* 67449 */ MCD_OPC_CheckPredicate, 3, 38, 76, 0, // Skip to: 86948 /* 67454 */ MCD_OPC_CheckField, 10, 1, 0, 31, 76, 0, // Skip to: 86948 /* 67461 */ MCD_OPC_Decode, 163, 20, 226, 2, // Opcode: MULv4i32_indexed /* 67466 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 67488 /* 67471 */ MCD_OPC_CheckPredicate, 3, 16, 76, 0, // Skip to: 86948 /* 67476 */ MCD_OPC_CheckField, 10, 1, 0, 9, 76, 0, // Skip to: 86948 /* 67483 */ MCD_OPC_Decode, 161, 11, 226, 2, // Opcode: FMULv4i32_indexed /* 67488 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67510 /* 67493 */ MCD_OPC_CheckPredicate, 3, 250, 75, 0, // Skip to: 86948 /* 67498 */ MCD_OPC_CheckField, 10, 1, 0, 243, 75, 0, // Skip to: 86948 /* 67505 */ MCD_OPC_Decode, 144, 24, 226, 2, // Opcode: SMULLv4i32_indexed /* 67510 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 67532 /* 67515 */ MCD_OPC_CheckPredicate, 3, 228, 75, 0, // Skip to: 86948 /* 67520 */ MCD_OPC_CheckField, 10, 1, 0, 221, 75, 0, // Skip to: 86948 /* 67527 */ MCD_OPC_Decode, 249, 24, 226, 2, // Opcode: SQDMULLv4i32_indexed /* 67532 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 67554 /* 67537 */ MCD_OPC_CheckPredicate, 3, 206, 75, 0, // Skip to: 86948 /* 67542 */ MCD_OPC_CheckField, 10, 1, 0, 199, 75, 0, // Skip to: 86948 /* 67549 */ MCD_OPC_Decode, 238, 24, 226, 2, // Opcode: SQDMULHv4i32_indexed /* 67554 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67576 /* 67559 */ MCD_OPC_CheckPredicate, 3, 184, 75, 0, // Skip to: 86948 /* 67564 */ MCD_OPC_CheckField, 10, 1, 0, 177, 75, 0, // Skip to: 86948 /* 67571 */ MCD_OPC_Decode, 191, 25, 226, 2, // Opcode: SQRDMULHv4i32_indexed /* 67576 */ MCD_OPC_FilterValue, 14, 167, 75, 0, // Skip to: 86948 /* 67581 */ MCD_OPC_CheckPredicate, 10, 162, 75, 0, // Skip to: 86948 /* 67586 */ MCD_OPC_CheckField, 10, 1, 0, 155, 75, 0, // Skip to: 86948 /* 67593 */ MCD_OPC_Decode, 229, 22, 225, 2, // Opcode: SDOTlanev16i8 /* 67598 */ MCD_OPC_FilterValue, 3, 145, 75, 0, // Skip to: 86948 /* 67603 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 67606 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 67746 /* 67611 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 67614 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67636 /* 67619 */ MCD_OPC_CheckPredicate, 3, 124, 75, 0, // Skip to: 86948 /* 67624 */ MCD_OPC_CheckField, 10, 1, 0, 117, 75, 0, // Skip to: 86948 /* 67631 */ MCD_OPC_Decode, 215, 19, 225, 2, // Opcode: MLAv4i32_indexed /* 67636 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 67658 /* 67641 */ MCD_OPC_CheckPredicate, 3, 102, 75, 0, // Skip to: 86948 /* 67646 */ MCD_OPC_CheckField, 10, 1, 0, 95, 75, 0, // Skip to: 86948 /* 67653 */ MCD_OPC_Decode, 168, 32, 225, 2, // Opcode: UMLALv4i32_indexed /* 67658 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67680 /* 67663 */ MCD_OPC_CheckPredicate, 3, 80, 75, 0, // Skip to: 86948 /* 67668 */ MCD_OPC_CheckField, 10, 1, 0, 73, 75, 0, // Skip to: 86948 /* 67675 */ MCD_OPC_Decode, 229, 19, 225, 2, // Opcode: MLSv4i32_indexed /* 67680 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 67702 /* 67685 */ MCD_OPC_CheckPredicate, 3, 58, 75, 0, // Skip to: 86948 /* 67690 */ MCD_OPC_CheckField, 10, 1, 0, 51, 75, 0, // Skip to: 86948 /* 67697 */ MCD_OPC_Decode, 178, 32, 225, 2, // Opcode: UMLSLv4i32_indexed /* 67702 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 67724 /* 67707 */ MCD_OPC_CheckPredicate, 3, 36, 75, 0, // Skip to: 86948 /* 67712 */ MCD_OPC_CheckField, 10, 1, 0, 29, 75, 0, // Skip to: 86948 /* 67719 */ MCD_OPC_Decode, 198, 32, 226, 2, // Opcode: UMULLv4i32_indexed /* 67724 */ MCD_OPC_FilterValue, 7, 19, 75, 0, // Skip to: 86948 /* 67729 */ MCD_OPC_CheckPredicate, 10, 14, 75, 0, // Skip to: 86948 /* 67734 */ MCD_OPC_CheckField, 10, 1, 0, 7, 75, 0, // Skip to: 86948 /* 67741 */ MCD_OPC_Decode, 216, 31, 225, 2, // Opcode: UDOTlanev16i8 /* 67746 */ MCD_OPC_FilterValue, 1, 253, 74, 0, // Skip to: 86948 /* 67751 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 67754 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 67783 /* 67759 */ MCD_OPC_CheckPredicate, 11, 240, 74, 0, // Skip to: 86948 /* 67764 */ MCD_OPC_CheckField, 21, 1, 0, 233, 74, 0, // Skip to: 86948 /* 67771 */ MCD_OPC_CheckField, 10, 1, 0, 226, 74, 0, // Skip to: 86948 /* 67778 */ MCD_OPC_Decode, 165, 7, 227, 2, // Opcode: FCMLAv4f32_indexed /* 67783 */ MCD_OPC_FilterValue, 1, 216, 74, 0, // Skip to: 86948 /* 67788 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 67791 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67813 /* 67796 */ MCD_OPC_CheckPredicate, 3, 203, 74, 0, // Skip to: 86948 /* 67801 */ MCD_OPC_CheckField, 10, 1, 0, 196, 74, 0, // Skip to: 86948 /* 67808 */ MCD_OPC_Decode, 136, 11, 226, 2, // Opcode: FMULXv4i32_indexed /* 67813 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67835 /* 67818 */ MCD_OPC_CheckPredicate, 7, 181, 74, 0, // Skip to: 86948 /* 67823 */ MCD_OPC_CheckField, 10, 1, 0, 174, 74, 0, // Skip to: 86948 /* 67830 */ MCD_OPC_Decode, 167, 25, 225, 2, // Opcode: SQRDMLAHv4i32_indexed /* 67835 */ MCD_OPC_FilterValue, 3, 164, 74, 0, // Skip to: 86948 /* 67840 */ MCD_OPC_CheckPredicate, 7, 159, 74, 0, // Skip to: 86948 /* 67845 */ MCD_OPC_CheckField, 10, 1, 0, 152, 74, 0, // Skip to: 86948 /* 67852 */ MCD_OPC_Decode, 179, 25, 225, 2, // Opcode: SQRDMLSHv4i32_indexed /* 67857 */ MCD_OPC_FilterValue, 15, 142, 74, 0, // Skip to: 86948 /* 67862 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 67865 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 67901 /* 67870 */ MCD_OPC_CheckPredicate, 3, 129, 74, 0, // Skip to: 86948 /* 67875 */ MCD_OPC_CheckField, 29, 3, 2, 122, 74, 0, // Skip to: 86948 /* 67882 */ MCD_OPC_CheckField, 21, 1, 0, 115, 74, 0, // Skip to: 86948 /* 67889 */ MCD_OPC_CheckField, 10, 1, 0, 108, 74, 0, // Skip to: 86948 /* 67896 */ MCD_OPC_Decode, 189, 10, 228, 2, // Opcode: FMLAv2i64_indexed /* 67901 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 67937 /* 67906 */ MCD_OPC_CheckPredicate, 3, 93, 74, 0, // Skip to: 86948 /* 67911 */ MCD_OPC_CheckField, 29, 3, 2, 86, 74, 0, // Skip to: 86948 /* 67918 */ MCD_OPC_CheckField, 21, 1, 0, 79, 74, 0, // Skip to: 86948 /* 67925 */ MCD_OPC_CheckField, 10, 1, 0, 72, 74, 0, // Skip to: 86948 /* 67932 */ MCD_OPC_Decode, 208, 10, 228, 2, // Opcode: FMLSv2i64_indexed /* 67937 */ MCD_OPC_FilterValue, 9, 62, 74, 0, // Skip to: 86948 /* 67942 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 67945 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 67974 /* 67950 */ MCD_OPC_CheckPredicate, 3, 49, 74, 0, // Skip to: 86948 /* 67955 */ MCD_OPC_CheckField, 21, 1, 0, 42, 74, 0, // Skip to: 86948 /* 67962 */ MCD_OPC_CheckField, 10, 1, 0, 35, 74, 0, // Skip to: 86948 /* 67969 */ MCD_OPC_Decode, 157, 11, 229, 2, // Opcode: FMULv2i64_indexed /* 67974 */ MCD_OPC_FilterValue, 3, 25, 74, 0, // Skip to: 86948 /* 67979 */ MCD_OPC_CheckPredicate, 3, 20, 74, 0, // Skip to: 86948 /* 67984 */ MCD_OPC_CheckField, 21, 1, 0, 13, 74, 0, // Skip to: 86948 /* 67991 */ MCD_OPC_CheckField, 10, 1, 0, 6, 74, 0, // Skip to: 86948 /* 67998 */ MCD_OPC_Decode, 132, 11, 229, 2, // Opcode: FMULXv2i64_indexed /* 68003 */ MCD_OPC_FilterValue, 4, 5, 2, 0, // Skip to: 68525 /* 68008 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 68011 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 68039 /* 68016 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ... /* 68019 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68029 /* 68024 */ MCD_OPC_Decode, 204, 1, 230, 2, // Opcode: ADR /* 68029 */ MCD_OPC_FilterValue, 1, 226, 73, 0, // Skip to: 86948 /* 68034 */ MCD_OPC_Decode, 205, 1, 230, 2, // Opcode: ADRP /* 68039 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 68127 /* 68044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 68047 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68057 /* 68052 */ MCD_OPC_Decode, 172, 1, 231, 2, // Opcode: ADDWri /* 68057 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68067 /* 68062 */ MCD_OPC_Decode, 157, 1, 231, 2, // Opcode: ADDSWri /* 68067 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68077 /* 68072 */ MCD_OPC_Decode, 234, 29, 231, 2, // Opcode: SUBWri /* 68077 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 68087 /* 68082 */ MCD_OPC_Decode, 225, 29, 231, 2, // Opcode: SUBSWri /* 68087 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 68097 /* 68092 */ MCD_OPC_Decode, 176, 1, 231, 2, // Opcode: ADDXri /* 68097 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 68107 /* 68102 */ MCD_OPC_Decode, 161, 1, 231, 2, // Opcode: ADDSXri /* 68107 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 68117 /* 68112 */ MCD_OPC_Decode, 238, 29, 231, 2, // Opcode: SUBXri /* 68117 */ MCD_OPC_FilterValue, 7, 138, 73, 0, // Skip to: 86948 /* 68122 */ MCD_OPC_Decode, 229, 29, 231, 2, // Opcode: SUBSXri /* 68127 */ MCD_OPC_FilterValue, 2, 226, 0, 0, // Skip to: 68358 /* 68132 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 68135 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 68170 /* 68140 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 68143 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68160 /* 68148 */ MCD_OPC_CheckField, 22, 1, 0, 105, 73, 0, // Skip to: 86948 /* 68155 */ MCD_OPC_Decode, 239, 1, 232, 2, // Opcode: ANDWri /* 68160 */ MCD_OPC_FilterValue, 1, 95, 73, 0, // Skip to: 86948 /* 68165 */ MCD_OPC_Decode, 245, 19, 233, 2, // Opcode: MOVNWi /* 68170 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 68187 /* 68175 */ MCD_OPC_CheckField, 22, 2, 0, 78, 73, 0, // Skip to: 86948 /* 68182 */ MCD_OPC_Decode, 204, 20, 232, 2, // Opcode: ORRWri /* 68187 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 68222 /* 68192 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 68195 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68212 /* 68200 */ MCD_OPC_CheckField, 22, 1, 0, 53, 73, 0, // Skip to: 86948 /* 68207 */ MCD_OPC_Decode, 232, 5, 232, 2, // Opcode: EORWri /* 68212 */ MCD_OPC_FilterValue, 1, 43, 73, 0, // Skip to: 86948 /* 68217 */ MCD_OPC_Decode, 128, 20, 233, 2, // Opcode: MOVZWi /* 68222 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 68257 /* 68227 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 68230 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68247 /* 68235 */ MCD_OPC_CheckField, 22, 1, 0, 18, 73, 0, // Skip to: 86948 /* 68242 */ MCD_OPC_Decode, 228, 1, 232, 2, // Opcode: ANDSWri /* 68247 */ MCD_OPC_FilterValue, 1, 8, 73, 0, // Skip to: 86948 /* 68252 */ MCD_OPC_Decode, 243, 19, 233, 2, // Opcode: MOVKWi /* 68257 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 68285 /* 68262 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 68265 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68275 /* 68270 */ MCD_OPC_Decode, 242, 1, 232, 2, // Opcode: ANDXri /* 68275 */ MCD_OPC_FilterValue, 1, 236, 72, 0, // Skip to: 86948 /* 68280 */ MCD_OPC_Decode, 246, 19, 233, 2, // Opcode: MOVNXi /* 68285 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 68302 /* 68290 */ MCD_OPC_CheckField, 23, 1, 0, 219, 72, 0, // Skip to: 86948 /* 68297 */ MCD_OPC_Decode, 207, 20, 232, 2, // Opcode: ORRXri /* 68302 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 68330 /* 68307 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 68310 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68320 /* 68315 */ MCD_OPC_Decode, 235, 5, 232, 2, // Opcode: EORXri /* 68320 */ MCD_OPC_FilterValue, 1, 191, 72, 0, // Skip to: 86948 /* 68325 */ MCD_OPC_Decode, 129, 20, 233, 2, // Opcode: MOVZXi /* 68330 */ MCD_OPC_FilterValue, 7, 181, 72, 0, // Skip to: 86948 /* 68335 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 68338 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68348 /* 68343 */ MCD_OPC_Decode, 231, 1, 232, 2, // Opcode: ANDSXri /* 68348 */ MCD_OPC_FilterValue, 1, 163, 72, 0, // Skip to: 86948 /* 68353 */ MCD_OPC_Decode, 244, 19, 233, 2, // Opcode: MOVKXi /* 68358 */ MCD_OPC_FilterValue, 3, 153, 72, 0, // Skip to: 86948 /* 68363 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 68366 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 68408 /* 68371 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 68374 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68391 /* 68379 */ MCD_OPC_CheckField, 15, 1, 0, 130, 72, 0, // Skip to: 86948 /* 68386 */ MCD_OPC_Decode, 182, 22, 234, 2, // Opcode: SBFMWri /* 68391 */ MCD_OPC_FilterValue, 4, 120, 72, 0, // Skip to: 86948 /* 68396 */ MCD_OPC_CheckField, 15, 1, 0, 113, 72, 0, // Skip to: 86948 /* 68403 */ MCD_OPC_Decode, 250, 5, 235, 2, // Opcode: EXTRWrri /* 68408 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 68432 /* 68413 */ MCD_OPC_CheckField, 21, 3, 0, 96, 72, 0, // Skip to: 86948 /* 68420 */ MCD_OPC_CheckField, 15, 1, 0, 89, 72, 0, // Skip to: 86948 /* 68427 */ MCD_OPC_Decode, 170, 2, 236, 2, // Opcode: BFMWri /* 68432 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 68456 /* 68437 */ MCD_OPC_CheckField, 21, 3, 0, 72, 72, 0, // Skip to: 86948 /* 68444 */ MCD_OPC_CheckField, 15, 1, 0, 65, 72, 0, // Skip to: 86948 /* 68451 */ MCD_OPC_Decode, 169, 31, 234, 2, // Opcode: UBFMWri /* 68456 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 68491 /* 68461 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 68464 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68474 /* 68469 */ MCD_OPC_Decode, 183, 22, 237, 2, // Opcode: SBFMXri /* 68474 */ MCD_OPC_FilterValue, 3, 37, 72, 0, // Skip to: 86948 /* 68479 */ MCD_OPC_CheckField, 21, 1, 0, 30, 72, 0, // Skip to: 86948 /* 68486 */ MCD_OPC_Decode, 251, 5, 238, 2, // Opcode: EXTRXrri /* 68491 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 68508 /* 68496 */ MCD_OPC_CheckField, 22, 2, 1, 13, 72, 0, // Skip to: 86948 /* 68503 */ MCD_OPC_Decode, 171, 2, 239, 2, // Opcode: BFMXri /* 68508 */ MCD_OPC_FilterValue, 6, 3, 72, 0, // Skip to: 86948 /* 68513 */ MCD_OPC_CheckField, 22, 2, 1, 252, 71, 0, // Skip to: 86948 /* 68520 */ MCD_OPC_Decode, 170, 31, 237, 2, // Opcode: UBFMXri /* 68525 */ MCD_OPC_FilterValue, 5, 218, 3, 0, // Skip to: 69516 /* 68530 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 68533 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68543 /* 68538 */ MCD_OPC_Decode, 168, 2, 240, 2, // Opcode: B /* 68543 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 68591 /* 68548 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 68551 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68561 /* 68556 */ MCD_OPC_Decode, 250, 2, 241, 2, // Opcode: CBZW /* 68561 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68571 /* 68566 */ MCD_OPC_Decode, 248, 2, 241, 2, // Opcode: CBNZW /* 68571 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68581 /* 68576 */ MCD_OPC_Decode, 199, 30, 242, 2, // Opcode: TBZW /* 68581 */ MCD_OPC_FilterValue, 3, 186, 71, 0, // Skip to: 86948 /* 68586 */ MCD_OPC_Decode, 189, 30, 242, 2, // Opcode: TBNZW /* 68591 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 68615 /* 68596 */ MCD_OPC_CheckField, 24, 2, 0, 169, 71, 0, // Skip to: 86948 /* 68603 */ MCD_OPC_CheckField, 4, 1, 0, 162, 71, 0, // Skip to: 86948 /* 68610 */ MCD_OPC_Decode, 223, 2, 243, 2, // Opcode: Bcc /* 68615 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 68625 /* 68620 */ MCD_OPC_Decode, 197, 2, 240, 2, // Opcode: BL /* 68625 */ MCD_OPC_FilterValue, 5, 43, 0, 0, // Skip to: 68673 /* 68630 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 68633 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68643 /* 68638 */ MCD_OPC_Decode, 251, 2, 244, 2, // Opcode: CBZX /* 68643 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68653 /* 68648 */ MCD_OPC_Decode, 249, 2, 244, 2, // Opcode: CBNZX /* 68653 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68663 /* 68658 */ MCD_OPC_Decode, 200, 30, 242, 2, // Opcode: TBZX /* 68663 */ MCD_OPC_FilterValue, 3, 104, 71, 0, // Skip to: 86948 /* 68668 */ MCD_OPC_Decode, 190, 30, 242, 2, // Opcode: TBNZX /* 68673 */ MCD_OPC_FilterValue, 6, 94, 71, 0, // Skip to: 86948 /* 68678 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 68681 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 68719 /* 68686 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 68689 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68699 /* 68694 */ MCD_OPC_Decode, 152, 30, 245, 2, // Opcode: SVC /* 68699 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68709 /* 68704 */ MCD_OPC_Decode, 243, 13, 245, 2, // Opcode: HVC /* 68709 */ MCD_OPC_FilterValue, 3, 58, 71, 0, // Skip to: 86948 /* 68714 */ MCD_OPC_Decode, 206, 23, 245, 2, // Opcode: SMC /* 68719 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 68736 /* 68724 */ MCD_OPC_CheckField, 0, 5, 0, 41, 71, 0, // Skip to: 86948 /* 68731 */ MCD_OPC_Decode, 208, 2, 245, 2, // Opcode: BRK /* 68736 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 68753 /* 68741 */ MCD_OPC_CheckField, 0, 5, 0, 24, 71, 0, // Skip to: 86948 /* 68748 */ MCD_OPC_Decode, 242, 13, 245, 2, // Opcode: HLT /* 68753 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 68791 /* 68758 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 68761 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68771 /* 68766 */ MCD_OPC_Decode, 174, 5, 245, 2, // Opcode: DCPS1 /* 68771 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68781 /* 68776 */ MCD_OPC_Decode, 175, 5, 245, 2, // Opcode: DCPS2 /* 68781 */ MCD_OPC_FilterValue, 3, 242, 70, 0, // Skip to: 86948 /* 68786 */ MCD_OPC_Decode, 176, 5, 245, 2, // Opcode: DCPS3 /* 68791 */ MCD_OPC_FilterValue, 8, 77, 1, 0, // Skip to: 69129 /* 68796 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... /* 68799 */ MCD_OPC_FilterValue, 159, 128, 1, 9, 0, 0, // Skip to: 68815 /* 68806 */ MCD_OPC_CheckPredicate, 12, 163, 0, 0, // Skip to: 68974 /* 68811 */ MCD_OPC_Decode, 132, 3, 97, // Opcode: CFINV /* 68815 */ MCD_OPC_FilterValue, 255, 193, 12, 4, 0, 0, // Skip to: 68826 /* 68822 */ MCD_OPC_Decode, 254, 34, 97, // Opcode: XPACLRI /* 68826 */ MCD_OPC_FilterValue, 159, 194, 12, 4, 0, 0, // Skip to: 68837 /* 68833 */ MCD_OPC_Decode, 233, 20, 97, // Opcode: PACIA1716 /* 68837 */ MCD_OPC_FilterValue, 223, 194, 12, 4, 0, 0, // Skip to: 68848 /* 68844 */ MCD_OPC_Decode, 237, 20, 97, // Opcode: PACIB1716 /* 68848 */ MCD_OPC_FilterValue, 159, 195, 12, 4, 0, 0, // Skip to: 68859 /* 68855 */ MCD_OPC_Decode, 159, 2, 97, // Opcode: AUTIA1716 /* 68859 */ MCD_OPC_FilterValue, 223, 195, 12, 4, 0, 0, // Skip to: 68870 /* 68866 */ MCD_OPC_Decode, 163, 2, 97, // Opcode: AUTIB1716 /* 68870 */ MCD_OPC_FilterValue, 223, 196, 12, 9, 0, 0, // Skip to: 68886 /* 68877 */ MCD_OPC_CheckPredicate, 12, 92, 0, 0, // Skip to: 68974 /* 68882 */ MCD_OPC_Decode, 235, 30, 97, // Opcode: TSB /* 68886 */ MCD_OPC_FilterValue, 159, 198, 12, 4, 0, 0, // Skip to: 68897 /* 68893 */ MCD_OPC_Decode, 235, 20, 97, // Opcode: PACIAZ /* 68897 */ MCD_OPC_FilterValue, 191, 198, 12, 4, 0, 0, // Skip to: 68908 /* 68904 */ MCD_OPC_Decode, 234, 20, 97, // Opcode: PACIASP /* 68908 */ MCD_OPC_FilterValue, 223, 198, 12, 4, 0, 0, // Skip to: 68919 /* 68915 */ MCD_OPC_Decode, 239, 20, 97, // Opcode: PACIBZ /* 68919 */ MCD_OPC_FilterValue, 255, 198, 12, 4, 0, 0, // Skip to: 68930 /* 68926 */ MCD_OPC_Decode, 238, 20, 97, // Opcode: PACIBSP /* 68930 */ MCD_OPC_FilterValue, 159, 199, 12, 4, 0, 0, // Skip to: 68941 /* 68937 */ MCD_OPC_Decode, 161, 2, 97, // Opcode: AUTIAZ /* 68941 */ MCD_OPC_FilterValue, 191, 199, 12, 4, 0, 0, // Skip to: 68952 /* 68948 */ MCD_OPC_Decode, 160, 2, 97, // Opcode: AUTIASP /* 68952 */ MCD_OPC_FilterValue, 223, 199, 12, 4, 0, 0, // Skip to: 68963 /* 68959 */ MCD_OPC_Decode, 165, 2, 97, // Opcode: AUTIBZ /* 68963 */ MCD_OPC_FilterValue, 255, 199, 12, 4, 0, 0, // Skip to: 68974 /* 68970 */ MCD_OPC_Decode, 164, 2, 97, // Opcode: AUTIBSP /* 68974 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 68977 */ MCD_OPC_FilterValue, 95, 12, 0, 0, // Skip to: 68994 /* 68982 */ MCD_OPC_CheckField, 12, 9, 51, 59, 0, 0, // Skip to: 69048 /* 68989 */ MCD_OPC_Decode, 157, 3, 246, 2, // Opcode: CLREX /* 68994 */ MCD_OPC_FilterValue, 159, 1, 12, 0, 0, // Skip to: 69012 /* 69000 */ MCD_OPC_CheckField, 12, 9, 51, 41, 0, 0, // Skip to: 69048 /* 69007 */ MCD_OPC_Decode, 193, 5, 246, 2, // Opcode: DSB /* 69012 */ MCD_OPC_FilterValue, 191, 1, 12, 0, 0, // Skip to: 69030 /* 69018 */ MCD_OPC_CheckField, 12, 9, 51, 23, 0, 0, // Skip to: 69048 /* 69025 */ MCD_OPC_Decode, 191, 5, 246, 2, // Opcode: DMB /* 69030 */ MCD_OPC_FilterValue, 223, 1, 12, 0, 0, // Skip to: 69048 /* 69036 */ MCD_OPC_CheckField, 12, 9, 51, 5, 0, 0, // Skip to: 69048 /* 69043 */ MCD_OPC_Decode, 162, 14, 246, 2, // Opcode: ISB /* 69048 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 69051 */ MCD_OPC_FilterValue, 31, 56, 0, 0, // Skip to: 69112 /* 69056 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 69059 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 69076 /* 69064 */ MCD_OPC_CheckField, 16, 5, 3, 41, 0, 0, // Skip to: 69112 /* 69071 */ MCD_OPC_Decode, 241, 13, 247, 2, // Opcode: HINT /* 69076 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 69112 /* 69081 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... /* 69084 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 69112 /* 69089 */ MCD_OPC_CheckField, 9, 3, 0, 8, 0, 0, // Skip to: 69104 /* 69096 */ MCD_OPC_TryDecode, 145, 20, 248, 2, 0, 0, 0, // Opcode: MSRpstateImm1, skip to: 69104 /* 69104 */ MCD_OPC_TryDecode, 146, 20, 248, 2, 0, 0, 0, // Opcode: MSRpstateImm4, skip to: 69112 /* 69112 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, 0, // Skip to: 69124 /* 69119 */ MCD_OPC_Decode, 176, 30, 249, 2, // Opcode: SYSxt /* 69124 */ MCD_OPC_Decode, 144, 20, 250, 2, // Opcode: MSR /* 69129 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 69151 /* 69134 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, 0, // Skip to: 69146 /* 69141 */ MCD_OPC_Decode, 175, 30, 251, 2, // Opcode: SYSLxt /* 69146 */ MCD_OPC_Decode, 139, 20, 252, 2, // Opcode: MRS /* 69151 */ MCD_OPC_FilterValue, 16, 67, 0, 0, // Skip to: 69223 /* 69156 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... /* 69159 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69177 /* 69165 */ MCD_OPC_CheckField, 0, 5, 0, 112, 69, 0, // Skip to: 86948 /* 69172 */ MCD_OPC_Decode, 203, 2, 253, 2, // Opcode: BR /* 69177 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69200 /* 69183 */ MCD_OPC_CheckPredicate, 13, 96, 69, 0, // Skip to: 86948 /* 69188 */ MCD_OPC_CheckField, 0, 5, 31, 89, 69, 0, // Skip to: 86948 /* 69195 */ MCD_OPC_Decode, 205, 2, 253, 2, // Opcode: BRAAZ /* 69200 */ MCD_OPC_FilterValue, 195, 15, 78, 69, 0, // Skip to: 86948 /* 69206 */ MCD_OPC_CheckPredicate, 13, 73, 69, 0, // Skip to: 86948 /* 69211 */ MCD_OPC_CheckField, 0, 5, 31, 66, 69, 0, // Skip to: 86948 /* 69218 */ MCD_OPC_Decode, 207, 2, 253, 2, // Opcode: BRABZ /* 69223 */ MCD_OPC_FilterValue, 17, 67, 0, 0, // Skip to: 69295 /* 69228 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... /* 69231 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69249 /* 69237 */ MCD_OPC_CheckField, 0, 5, 0, 40, 69, 0, // Skip to: 86948 /* 69244 */ MCD_OPC_Decode, 198, 2, 253, 2, // Opcode: BLR /* 69249 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69272 /* 69255 */ MCD_OPC_CheckPredicate, 13, 24, 69, 0, // Skip to: 86948 /* 69260 */ MCD_OPC_CheckField, 0, 5, 31, 17, 69, 0, // Skip to: 86948 /* 69267 */ MCD_OPC_Decode, 200, 2, 253, 2, // Opcode: BLRAAZ /* 69272 */ MCD_OPC_FilterValue, 195, 15, 6, 69, 0, // Skip to: 86948 /* 69278 */ MCD_OPC_CheckPredicate, 13, 1, 69, 0, // Skip to: 86948 /* 69283 */ MCD_OPC_CheckField, 0, 5, 31, 250, 68, 0, // Skip to: 86948 /* 69290 */ MCD_OPC_Decode, 202, 2, 253, 2, // Opcode: BLRABZ /* 69295 */ MCD_OPC_FilterValue, 18, 67, 0, 0, // Skip to: 69367 /* 69300 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... /* 69303 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69321 /* 69309 */ MCD_OPC_CheckField, 0, 5, 0, 224, 68, 0, // Skip to: 86948 /* 69316 */ MCD_OPC_Decode, 196, 21, 253, 2, // Opcode: RET /* 69321 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69344 /* 69327 */ MCD_OPC_CheckPredicate, 13, 208, 68, 0, // Skip to: 86948 /* 69332 */ MCD_OPC_CheckField, 0, 10, 255, 7, 200, 68, 0, // Skip to: 86948 /* 69340 */ MCD_OPC_Decode, 197, 21, 97, // Opcode: RETAA /* 69344 */ MCD_OPC_FilterValue, 195, 15, 190, 68, 0, // Skip to: 86948 /* 69350 */ MCD_OPC_CheckPredicate, 13, 185, 68, 0, // Skip to: 86948 /* 69355 */ MCD_OPC_CheckField, 0, 10, 255, 7, 177, 68, 0, // Skip to: 86948 /* 69363 */ MCD_OPC_Decode, 198, 21, 97, // Opcode: RETAB /* 69367 */ MCD_OPC_FilterValue, 20, 46, 0, 0, // Skip to: 69418 /* 69372 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... /* 69375 */ MCD_OPC_FilterValue, 224, 135, 124, 4, 0, 0, // Skip to: 69386 /* 69382 */ MCD_OPC_Decode, 247, 5, 97, // Opcode: ERET /* 69386 */ MCD_OPC_FilterValue, 255, 151, 124, 9, 0, 0, // Skip to: 69402 /* 69393 */ MCD_OPC_CheckPredicate, 13, 142, 68, 0, // Skip to: 86948 /* 69398 */ MCD_OPC_Decode, 248, 5, 97, // Opcode: ERETAA /* 69402 */ MCD_OPC_FilterValue, 255, 159, 124, 131, 68, 0, // Skip to: 86948 /* 69409 */ MCD_OPC_CheckPredicate, 13, 126, 68, 0, // Skip to: 86948 /* 69414 */ MCD_OPC_Decode, 249, 5, 97, // Opcode: ERETAB /* 69418 */ MCD_OPC_FilterValue, 21, 13, 0, 0, // Skip to: 69436 /* 69423 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 108, 68, 0, // Skip to: 86948 /* 69432 */ MCD_OPC_Decode, 192, 5, 97, // Opcode: DRPS /* 69436 */ MCD_OPC_FilterValue, 24, 35, 0, 0, // Skip to: 69476 /* 69441 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... /* 69444 */ MCD_OPC_FilterValue, 194, 15, 10, 0, 0, // Skip to: 69460 /* 69450 */ MCD_OPC_CheckPredicate, 13, 85, 68, 0, // Skip to: 86948 /* 69455 */ MCD_OPC_Decode, 204, 2, 254, 2, // Opcode: BRAA /* 69460 */ MCD_OPC_FilterValue, 195, 15, 74, 68, 0, // Skip to: 86948 /* 69466 */ MCD_OPC_CheckPredicate, 13, 69, 68, 0, // Skip to: 86948 /* 69471 */ MCD_OPC_Decode, 206, 2, 254, 2, // Opcode: BRAB /* 69476 */ MCD_OPC_FilterValue, 25, 59, 68, 0, // Skip to: 86948 /* 69481 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... /* 69484 */ MCD_OPC_FilterValue, 194, 15, 10, 0, 0, // Skip to: 69500 /* 69490 */ MCD_OPC_CheckPredicate, 13, 45, 68, 0, // Skip to: 86948 /* 69495 */ MCD_OPC_Decode, 199, 2, 254, 2, // Opcode: BLRAA /* 69500 */ MCD_OPC_FilterValue, 195, 15, 34, 68, 0, // Skip to: 86948 /* 69506 */ MCD_OPC_CheckPredicate, 13, 29, 68, 0, // Skip to: 86948 /* 69511 */ MCD_OPC_Decode, 201, 2, 254, 2, // Opcode: BLRAB /* 69516 */ MCD_OPC_FilterValue, 6, 115, 24, 0, // Skip to: 75780 /* 69521 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 69524 */ MCD_OPC_FilterValue, 0, 180, 1, 0, // Skip to: 69965 /* 69529 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 69532 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 69542 /* 69537 */ MCD_OPC_Decode, 155, 18, 241, 2, // Opcode: LDRWl /* 69542 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 69638 /* 69547 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 69550 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 69572 /* 69555 */ MCD_OPC_CheckPredicate, 12, 236, 67, 0, // Skip to: 86948 /* 69560 */ MCD_OPC_CheckField, 10, 2, 0, 229, 67, 0, // Skip to: 86948 /* 69567 */ MCD_OPC_Decode, 235, 28, 255, 2, // Opcode: STLURBi /* 69572 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 69594 /* 69577 */ MCD_OPC_CheckPredicate, 12, 214, 67, 0, // Skip to: 86948 /* 69582 */ MCD_OPC_CheckField, 10, 2, 0, 207, 67, 0, // Skip to: 86948 /* 69589 */ MCD_OPC_Decode, 225, 16, 255, 2, // Opcode: LDAPURBi /* 69594 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 69616 /* 69599 */ MCD_OPC_CheckPredicate, 12, 192, 67, 0, // Skip to: 86948 /* 69604 */ MCD_OPC_CheckField, 10, 2, 0, 185, 67, 0, // Skip to: 86948 /* 69611 */ MCD_OPC_Decode, 228, 16, 255, 2, // Opcode: LDAPURSBXi /* 69616 */ MCD_OPC_FilterValue, 6, 175, 67, 0, // Skip to: 86948 /* 69621 */ MCD_OPC_CheckPredicate, 12, 170, 67, 0, // Skip to: 86948 /* 69626 */ MCD_OPC_CheckField, 10, 2, 0, 163, 67, 0, // Skip to: 86948 /* 69633 */ MCD_OPC_Decode, 227, 16, 255, 2, // Opcode: LDAPURSBWi /* 69638 */ MCD_OPC_FilterValue, 2, 24, 1, 0, // Skip to: 69923 /* 69643 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 69646 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 69729 /* 69651 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 69654 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69671 /* 69659 */ MCD_OPC_CheckField, 12, 4, 0, 130, 67, 0, // Skip to: 86948 /* 69666 */ MCD_OPC_Decode, 140, 1, 128, 3, // Opcode: ADCWr /* 69671 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 69681 /* 69676 */ MCD_OPC_Decode, 161, 5, 129, 3, // Opcode: CSELWr /* 69681 */ MCD_OPC_FilterValue, 6, 110, 67, 0, // Skip to: 86948 /* 69686 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 69689 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 69699 /* 69694 */ MCD_OPC_Decode, 155, 19, 128, 3, // Opcode: LSLVWr /* 69699 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 69714 /* 69704 */ MCD_OPC_CheckPredicate, 14, 87, 67, 0, // Skip to: 86948 /* 69709 */ MCD_OPC_Decode, 153, 5, 128, 3, // Opcode: CRC32Brr /* 69714 */ MCD_OPC_FilterValue, 5, 77, 67, 0, // Skip to: 86948 /* 69719 */ MCD_OPC_CheckPredicate, 14, 72, 67, 0, // Skip to: 86948 /* 69724 */ MCD_OPC_Decode, 154, 5, 128, 3, // Opcode: CRC32CBrr /* 69729 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 69795 /* 69734 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 69737 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 69747 /* 69742 */ MCD_OPC_Decode, 163, 5, 129, 3, // Opcode: CSINCWr /* 69747 */ MCD_OPC_FilterValue, 6, 44, 67, 0, // Skip to: 86948 /* 69752 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 69755 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 69765 /* 69760 */ MCD_OPC_Decode, 179, 19, 128, 3, // Opcode: LSRVWr /* 69765 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 69780 /* 69770 */ MCD_OPC_CheckPredicate, 14, 21, 67, 0, // Skip to: 86948 /* 69775 */ MCD_OPC_Decode, 158, 5, 128, 3, // Opcode: CRC32Hrr /* 69780 */ MCD_OPC_FilterValue, 5, 11, 67, 0, // Skip to: 86948 /* 69785 */ MCD_OPC_CheckPredicate, 14, 6, 67, 0, // Skip to: 86948 /* 69790 */ MCD_OPC_Decode, 155, 5, 128, 3, // Opcode: CRC32CHrr /* 69795 */ MCD_OPC_FilterValue, 2, 81, 0, 0, // Skip to: 69881 /* 69800 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 69803 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69820 /* 69808 */ MCD_OPC_CheckField, 21, 3, 6, 237, 66, 0, // Skip to: 86948 /* 69815 */ MCD_OPC_Decode, 208, 31, 128, 3, // Opcode: UDIVWr /* 69820 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 69837 /* 69825 */ MCD_OPC_CheckField, 21, 3, 6, 220, 66, 0, // Skip to: 86948 /* 69832 */ MCD_OPC_Decode, 134, 2, 128, 3, // Opcode: ASRVWr /* 69837 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 69859 /* 69842 */ MCD_OPC_CheckPredicate, 14, 205, 66, 0, // Skip to: 86948 /* 69847 */ MCD_OPC_CheckField, 21, 3, 6, 198, 66, 0, // Skip to: 86948 /* 69854 */ MCD_OPC_Decode, 159, 5, 128, 3, // Opcode: CRC32Wrr /* 69859 */ MCD_OPC_FilterValue, 5, 188, 66, 0, // Skip to: 86948 /* 69864 */ MCD_OPC_CheckPredicate, 14, 183, 66, 0, // Skip to: 86948 /* 69869 */ MCD_OPC_CheckField, 21, 3, 6, 176, 66, 0, // Skip to: 86948 /* 69876 */ MCD_OPC_Decode, 156, 5, 128, 3, // Opcode: CRC32CWrr /* 69881 */ MCD_OPC_FilterValue, 3, 166, 66, 0, // Skip to: 86948 /* 69886 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 69889 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69906 /* 69894 */ MCD_OPC_CheckField, 21, 3, 6, 151, 66, 0, // Skip to: 86948 /* 69901 */ MCD_OPC_Decode, 221, 22, 128, 3, // Opcode: SDIVWr /* 69906 */ MCD_OPC_FilterValue, 2, 141, 66, 0, // Skip to: 86948 /* 69911 */ MCD_OPC_CheckField, 21, 3, 6, 134, 66, 0, // Skip to: 86948 /* 69918 */ MCD_OPC_Decode, 232, 21, 128, 3, // Opcode: RORVWr /* 69923 */ MCD_OPC_FilterValue, 3, 124, 66, 0, // Skip to: 86948 /* 69928 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 69931 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69948 /* 69936 */ MCD_OPC_CheckField, 21, 3, 0, 109, 66, 0, // Skip to: 86948 /* 69943 */ MCD_OPC_Decode, 199, 19, 130, 3, // Opcode: MADDWrrr /* 69948 */ MCD_OPC_FilterValue, 1, 99, 66, 0, // Skip to: 86948 /* 69953 */ MCD_OPC_CheckField, 21, 3, 0, 92, 66, 0, // Skip to: 86948 /* 69960 */ MCD_OPC_Decode, 147, 20, 130, 3, // Opcode: MSUBWrrr /* 69965 */ MCD_OPC_FilterValue, 1, 176, 4, 0, // Skip to: 71170 /* 69970 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 69973 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 70222 /* 69978 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 69981 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70142 /* 69986 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 69989 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 69999 /* 69994 */ MCD_OPC_Decode, 196, 29, 255, 2, // Opcode: STURBBi /* 69999 */ MCD_OPC_FilterValue, 1, 48, 66, 0, // Skip to: 86948 /* 70004 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 70007 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70022 /* 70012 */ MCD_OPC_CheckPredicate, 1, 35, 66, 0, // Skip to: 86948 /* 70017 */ MCD_OPC_Decode, 213, 16, 131, 3, // Opcode: LDADDB /* 70022 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70037 /* 70027 */ MCD_OPC_CheckPredicate, 1, 20, 66, 0, // Skip to: 86948 /* 70032 */ MCD_OPC_Decode, 252, 16, 131, 3, // Opcode: LDCLRB /* 70037 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70052 /* 70042 */ MCD_OPC_CheckPredicate, 1, 5, 66, 0, // Skip to: 86948 /* 70047 */ MCD_OPC_Decode, 140, 17, 131, 3, // Opcode: LDEORB /* 70052 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70067 /* 70057 */ MCD_OPC_CheckPredicate, 1, 246, 65, 0, // Skip to: 86948 /* 70062 */ MCD_OPC_Decode, 177, 18, 131, 3, // Opcode: LDSETB /* 70067 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70082 /* 70072 */ MCD_OPC_CheckPredicate, 1, 231, 65, 0, // Skip to: 86948 /* 70077 */ MCD_OPC_Decode, 193, 18, 131, 3, // Opcode: LDSMAXB /* 70082 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70097 /* 70087 */ MCD_OPC_CheckPredicate, 1, 216, 65, 0, // Skip to: 86948 /* 70092 */ MCD_OPC_Decode, 209, 18, 131, 3, // Opcode: LDSMINB /* 70097 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70112 /* 70102 */ MCD_OPC_CheckPredicate, 1, 201, 65, 0, // Skip to: 86948 /* 70107 */ MCD_OPC_Decode, 234, 18, 131, 3, // Opcode: LDUMAXB /* 70112 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70127 /* 70117 */ MCD_OPC_CheckPredicate, 1, 186, 65, 0, // Skip to: 86948 /* 70122 */ MCD_OPC_Decode, 250, 18, 131, 3, // Opcode: LDUMINB /* 70127 */ MCD_OPC_FilterValue, 8, 176, 65, 0, // Skip to: 86948 /* 70132 */ MCD_OPC_CheckPredicate, 1, 171, 65, 0, // Skip to: 86948 /* 70137 */ MCD_OPC_Decode, 161, 30, 131, 3, // Opcode: SWPB /* 70142 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70159 /* 70147 */ MCD_OPC_CheckField, 21, 1, 0, 154, 65, 0, // Skip to: 86948 /* 70154 */ MCD_OPC_Decode, 145, 29, 255, 2, // Opcode: STRBBpost /* 70159 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70205 /* 70164 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70167 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70177 /* 70172 */ MCD_OPC_Decode, 192, 29, 255, 2, // Opcode: STTRBi /* 70177 */ MCD_OPC_FilterValue, 1, 126, 65, 0, // Skip to: 86948 /* 70182 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 70185 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70195 /* 70190 */ MCD_OPC_Decode, 147, 29, 132, 3, // Opcode: STRBBroW /* 70195 */ MCD_OPC_FilterValue, 3, 108, 65, 0, // Skip to: 86948 /* 70200 */ MCD_OPC_Decode, 148, 29, 133, 3, // Opcode: STRBBroX /* 70205 */ MCD_OPC_FilterValue, 3, 98, 65, 0, // Skip to: 86948 /* 70210 */ MCD_OPC_CheckField, 21, 1, 0, 91, 65, 0, // Skip to: 86948 /* 70217 */ MCD_OPC_Decode, 146, 29, 255, 2, // Opcode: STRBBpre /* 70222 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 70471 /* 70227 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 70230 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70391 /* 70235 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70238 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70248 /* 70243 */ MCD_OPC_Decode, 130, 19, 255, 2, // Opcode: LDURBBi /* 70248 */ MCD_OPC_FilterValue, 1, 55, 65, 0, // Skip to: 86948 /* 70253 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 70256 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70271 /* 70261 */ MCD_OPC_CheckPredicate, 1, 42, 65, 0, // Skip to: 86948 /* 70266 */ MCD_OPC_Decode, 215, 16, 131, 3, // Opcode: LDADDLB /* 70271 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70286 /* 70276 */ MCD_OPC_CheckPredicate, 1, 27, 65, 0, // Skip to: 86948 /* 70281 */ MCD_OPC_Decode, 254, 16, 131, 3, // Opcode: LDCLRLB /* 70286 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70301 /* 70291 */ MCD_OPC_CheckPredicate, 1, 12, 65, 0, // Skip to: 86948 /* 70296 */ MCD_OPC_Decode, 142, 17, 131, 3, // Opcode: LDEORLB /* 70301 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70316 /* 70306 */ MCD_OPC_CheckPredicate, 1, 253, 64, 0, // Skip to: 86948 /* 70311 */ MCD_OPC_Decode, 179, 18, 131, 3, // Opcode: LDSETLB /* 70316 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70331 /* 70321 */ MCD_OPC_CheckPredicate, 1, 238, 64, 0, // Skip to: 86948 /* 70326 */ MCD_OPC_Decode, 195, 18, 131, 3, // Opcode: LDSMAXLB /* 70331 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70346 /* 70336 */ MCD_OPC_CheckPredicate, 1, 223, 64, 0, // Skip to: 86948 /* 70341 */ MCD_OPC_Decode, 211, 18, 131, 3, // Opcode: LDSMINLB /* 70346 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70361 /* 70351 */ MCD_OPC_CheckPredicate, 1, 208, 64, 0, // Skip to: 86948 /* 70356 */ MCD_OPC_Decode, 236, 18, 131, 3, // Opcode: LDUMAXLB /* 70361 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70376 /* 70366 */ MCD_OPC_CheckPredicate, 1, 193, 64, 0, // Skip to: 86948 /* 70371 */ MCD_OPC_Decode, 252, 18, 131, 3, // Opcode: LDUMINLB /* 70376 */ MCD_OPC_FilterValue, 8, 183, 64, 0, // Skip to: 86948 /* 70381 */ MCD_OPC_CheckPredicate, 1, 178, 64, 0, // Skip to: 86948 /* 70386 */ MCD_OPC_Decode, 163, 30, 131, 3, // Opcode: SWPLB /* 70391 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70408 /* 70396 */ MCD_OPC_CheckField, 21, 1, 0, 161, 64, 0, // Skip to: 86948 /* 70403 */ MCD_OPC_Decode, 219, 17, 255, 2, // Opcode: LDRBBpost /* 70408 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70454 /* 70413 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70416 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70426 /* 70421 */ MCD_OPC_Decode, 217, 18, 255, 2, // Opcode: LDTRBi /* 70426 */ MCD_OPC_FilterValue, 1, 133, 64, 0, // Skip to: 86948 /* 70431 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 70434 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70444 /* 70439 */ MCD_OPC_Decode, 221, 17, 132, 3, // Opcode: LDRBBroW /* 70444 */ MCD_OPC_FilterValue, 3, 115, 64, 0, // Skip to: 86948 /* 70449 */ MCD_OPC_Decode, 222, 17, 133, 3, // Opcode: LDRBBroX /* 70454 */ MCD_OPC_FilterValue, 3, 105, 64, 0, // Skip to: 86948 /* 70459 */ MCD_OPC_CheckField, 21, 1, 0, 98, 64, 0, // Skip to: 86948 /* 70466 */ MCD_OPC_Decode, 220, 17, 255, 2, // Opcode: LDRBBpre /* 70471 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 70742 /* 70476 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 70479 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 70662 /* 70484 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70487 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70497 /* 70492 */ MCD_OPC_Decode, 137, 19, 255, 2, // Opcode: LDURSBXi /* 70497 */ MCD_OPC_FilterValue, 1, 62, 64, 0, // Skip to: 86948 /* 70502 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 70505 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70520 /* 70510 */ MCD_OPC_CheckPredicate, 1, 49, 64, 0, // Skip to: 86948 /* 70515 */ MCD_OPC_Decode, 205, 16, 131, 3, // Opcode: LDADDAB /* 70520 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70535 /* 70525 */ MCD_OPC_CheckPredicate, 1, 34, 64, 0, // Skip to: 86948 /* 70530 */ MCD_OPC_Decode, 244, 16, 131, 3, // Opcode: LDCLRAB /* 70535 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70550 /* 70540 */ MCD_OPC_CheckPredicate, 1, 19, 64, 0, // Skip to: 86948 /* 70545 */ MCD_OPC_Decode, 132, 17, 131, 3, // Opcode: LDEORAB /* 70550 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70565 /* 70555 */ MCD_OPC_CheckPredicate, 1, 4, 64, 0, // Skip to: 86948 /* 70560 */ MCD_OPC_Decode, 169, 18, 131, 3, // Opcode: LDSETAB /* 70565 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70580 /* 70570 */ MCD_OPC_CheckPredicate, 1, 245, 63, 0, // Skip to: 86948 /* 70575 */ MCD_OPC_Decode, 185, 18, 131, 3, // Opcode: LDSMAXAB /* 70580 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70595 /* 70585 */ MCD_OPC_CheckPredicate, 1, 230, 63, 0, // Skip to: 86948 /* 70590 */ MCD_OPC_Decode, 201, 18, 131, 3, // Opcode: LDSMINAB /* 70595 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70610 /* 70600 */ MCD_OPC_CheckPredicate, 1, 215, 63, 0, // Skip to: 86948 /* 70605 */ MCD_OPC_Decode, 226, 18, 131, 3, // Opcode: LDUMAXAB /* 70610 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70625 /* 70615 */ MCD_OPC_CheckPredicate, 1, 200, 63, 0, // Skip to: 86948 /* 70620 */ MCD_OPC_Decode, 242, 18, 131, 3, // Opcode: LDUMINAB /* 70625 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 70640 /* 70630 */ MCD_OPC_CheckPredicate, 1, 185, 63, 0, // Skip to: 86948 /* 70635 */ MCD_OPC_Decode, 153, 30, 131, 3, // Opcode: SWPAB /* 70640 */ MCD_OPC_FilterValue, 12, 175, 63, 0, // Skip to: 86948 /* 70645 */ MCD_OPC_CheckPredicate, 15, 170, 63, 0, // Skip to: 86948 /* 70650 */ MCD_OPC_CheckField, 16, 5, 31, 163, 63, 0, // Skip to: 86948 /* 70657 */ MCD_OPC_Decode, 221, 16, 134, 3, // Opcode: LDAPRB /* 70662 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70679 /* 70667 */ MCD_OPC_CheckField, 21, 1, 0, 146, 63, 0, // Skip to: 86948 /* 70674 */ MCD_OPC_Decode, 128, 18, 255, 2, // Opcode: LDRSBXpost /* 70679 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70725 /* 70684 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70687 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70697 /* 70692 */ MCD_OPC_Decode, 220, 18, 255, 2, // Opcode: LDTRSBXi /* 70697 */ MCD_OPC_FilterValue, 1, 118, 63, 0, // Skip to: 86948 /* 70702 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 70705 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70715 /* 70710 */ MCD_OPC_Decode, 130, 18, 135, 3, // Opcode: LDRSBXroW /* 70715 */ MCD_OPC_FilterValue, 3, 100, 63, 0, // Skip to: 86948 /* 70720 */ MCD_OPC_Decode, 131, 18, 136, 3, // Opcode: LDRSBXroX /* 70725 */ MCD_OPC_FilterValue, 3, 90, 63, 0, // Skip to: 86948 /* 70730 */ MCD_OPC_CheckField, 21, 1, 0, 83, 63, 0, // Skip to: 86948 /* 70737 */ MCD_OPC_Decode, 129, 18, 255, 2, // Opcode: LDRSBXpre /* 70742 */ MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 70991 /* 70747 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 70750 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70911 /* 70755 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70758 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70768 /* 70763 */ MCD_OPC_Decode, 136, 19, 255, 2, // Opcode: LDURSBWi /* 70768 */ MCD_OPC_FilterValue, 1, 47, 63, 0, // Skip to: 86948 /* 70773 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 70776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70791 /* 70781 */ MCD_OPC_CheckPredicate, 1, 34, 63, 0, // Skip to: 86948 /* 70786 */ MCD_OPC_Decode, 207, 16, 131, 3, // Opcode: LDADDALB /* 70791 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70806 /* 70796 */ MCD_OPC_CheckPredicate, 1, 19, 63, 0, // Skip to: 86948 /* 70801 */ MCD_OPC_Decode, 246, 16, 131, 3, // Opcode: LDCLRALB /* 70806 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70821 /* 70811 */ MCD_OPC_CheckPredicate, 1, 4, 63, 0, // Skip to: 86948 /* 70816 */ MCD_OPC_Decode, 134, 17, 131, 3, // Opcode: LDEORALB /* 70821 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70836 /* 70826 */ MCD_OPC_CheckPredicate, 1, 245, 62, 0, // Skip to: 86948 /* 70831 */ MCD_OPC_Decode, 171, 18, 131, 3, // Opcode: LDSETALB /* 70836 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70851 /* 70841 */ MCD_OPC_CheckPredicate, 1, 230, 62, 0, // Skip to: 86948 /* 70846 */ MCD_OPC_Decode, 187, 18, 131, 3, // Opcode: LDSMAXALB /* 70851 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70866 /* 70856 */ MCD_OPC_CheckPredicate, 1, 215, 62, 0, // Skip to: 86948 /* 70861 */ MCD_OPC_Decode, 203, 18, 131, 3, // Opcode: LDSMINALB /* 70866 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70881 /* 70871 */ MCD_OPC_CheckPredicate, 1, 200, 62, 0, // Skip to: 86948 /* 70876 */ MCD_OPC_Decode, 228, 18, 131, 3, // Opcode: LDUMAXALB /* 70881 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70896 /* 70886 */ MCD_OPC_CheckPredicate, 1, 185, 62, 0, // Skip to: 86948 /* 70891 */ MCD_OPC_Decode, 244, 18, 131, 3, // Opcode: LDUMINALB /* 70896 */ MCD_OPC_FilterValue, 8, 175, 62, 0, // Skip to: 86948 /* 70901 */ MCD_OPC_CheckPredicate, 1, 170, 62, 0, // Skip to: 86948 /* 70906 */ MCD_OPC_Decode, 155, 30, 131, 3, // Opcode: SWPALB /* 70911 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70928 /* 70916 */ MCD_OPC_CheckField, 21, 1, 0, 153, 62, 0, // Skip to: 86948 /* 70923 */ MCD_OPC_Decode, 251, 17, 255, 2, // Opcode: LDRSBWpost /* 70928 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70974 /* 70933 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 70936 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70946 /* 70941 */ MCD_OPC_Decode, 219, 18, 255, 2, // Opcode: LDTRSBWi /* 70946 */ MCD_OPC_FilterValue, 1, 125, 62, 0, // Skip to: 86948 /* 70951 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 70954 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70964 /* 70959 */ MCD_OPC_Decode, 253, 17, 132, 3, // Opcode: LDRSBWroW /* 70964 */ MCD_OPC_FilterValue, 3, 107, 62, 0, // Skip to: 86948 /* 70969 */ MCD_OPC_Decode, 254, 17, 133, 3, // Opcode: LDRSBWroX /* 70974 */ MCD_OPC_FilterValue, 3, 97, 62, 0, // Skip to: 86948 /* 70979 */ MCD_OPC_CheckField, 21, 1, 0, 90, 62, 0, // Skip to: 86948 /* 70986 */ MCD_OPC_Decode, 252, 17, 255, 2, // Opcode: LDRSBWpre /* 70991 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71001 /* 70996 */ MCD_OPC_Decode, 149, 29, 137, 3, // Opcode: STRBBui /* 71001 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 71011 /* 71006 */ MCD_OPC_Decode, 223, 17, 137, 3, // Opcode: LDRBBui /* 71011 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 71021 /* 71016 */ MCD_OPC_Decode, 132, 18, 137, 3, // Opcode: LDRSBXui /* 71021 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 71031 /* 71026 */ MCD_OPC_Decode, 255, 17, 137, 3, // Opcode: LDRSBWui /* 71031 */ MCD_OPC_FilterValue, 8, 78, 0, 0, // Skip to: 71114 /* 71036 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 71039 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 71056 /* 71044 */ MCD_OPC_CheckField, 21, 1, 0, 25, 62, 0, // Skip to: 86948 /* 71051 */ MCD_OPC_Decode, 138, 1, 128, 3, // Opcode: ADCSWr /* 71056 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 71085 /* 71061 */ MCD_OPC_CheckPredicate, 12, 10, 62, 0, // Skip to: 86948 /* 71066 */ MCD_OPC_CheckField, 16, 6, 0, 3, 62, 0, // Skip to: 86948 /* 71073 */ MCD_OPC_CheckField, 0, 5, 13, 252, 61, 0, // Skip to: 86948 /* 71080 */ MCD_OPC_Decode, 239, 22, 138, 3, // Opcode: SETF8 /* 71085 */ MCD_OPC_FilterValue, 18, 242, 61, 0, // Skip to: 86948 /* 71090 */ MCD_OPC_CheckPredicate, 12, 237, 61, 0, // Skip to: 86948 /* 71095 */ MCD_OPC_CheckField, 16, 6, 0, 230, 61, 0, // Skip to: 86948 /* 71102 */ MCD_OPC_CheckField, 0, 5, 13, 223, 61, 0, // Skip to: 86948 /* 71109 */ MCD_OPC_Decode, 238, 22, 138, 3, // Opcode: SETF16 /* 71114 */ MCD_OPC_FilterValue, 9, 213, 61, 0, // Skip to: 86948 /* 71119 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 71122 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 71146 /* 71127 */ MCD_OPC_CheckField, 21, 1, 0, 198, 61, 0, // Skip to: 86948 /* 71134 */ MCD_OPC_CheckField, 4, 1, 0, 191, 61, 0, // Skip to: 86948 /* 71141 */ MCD_OPC_Decode, 253, 2, 139, 3, // Opcode: CCMNWr /* 71146 */ MCD_OPC_FilterValue, 2, 181, 61, 0, // Skip to: 86948 /* 71151 */ MCD_OPC_CheckField, 21, 1, 0, 174, 61, 0, // Skip to: 86948 /* 71158 */ MCD_OPC_CheckField, 4, 1, 0, 167, 61, 0, // Skip to: 86948 /* 71165 */ MCD_OPC_Decode, 252, 2, 140, 3, // Opcode: CCMNWi /* 71170 */ MCD_OPC_FilterValue, 2, 244, 0, 0, // Skip to: 71419 /* 71175 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 71178 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71188 /* 71183 */ MCD_OPC_Decode, 161, 18, 244, 2, // Opcode: LDRXl /* 71188 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 71284 /* 71193 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 71196 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 71218 /* 71201 */ MCD_OPC_CheckPredicate, 12, 126, 61, 0, // Skip to: 86948 /* 71206 */ MCD_OPC_CheckField, 10, 2, 0, 119, 61, 0, // Skip to: 86948 /* 71213 */ MCD_OPC_Decode, 236, 28, 255, 2, // Opcode: STLURHi /* 71218 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 71240 /* 71223 */ MCD_OPC_CheckPredicate, 12, 104, 61, 0, // Skip to: 86948 /* 71228 */ MCD_OPC_CheckField, 10, 2, 0, 97, 61, 0, // Skip to: 86948 /* 71235 */ MCD_OPC_Decode, 226, 16, 255, 2, // Opcode: LDAPURHi /* 71240 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 71262 /* 71245 */ MCD_OPC_CheckPredicate, 12, 82, 61, 0, // Skip to: 86948 /* 71250 */ MCD_OPC_CheckField, 10, 2, 0, 75, 61, 0, // Skip to: 86948 /* 71257 */ MCD_OPC_Decode, 230, 16, 255, 2, // Opcode: LDAPURSHXi /* 71262 */ MCD_OPC_FilterValue, 6, 65, 61, 0, // Skip to: 86948 /* 71267 */ MCD_OPC_CheckPredicate, 12, 60, 61, 0, // Skip to: 86948 /* 71272 */ MCD_OPC_CheckField, 10, 2, 0, 53, 61, 0, // Skip to: 86948 /* 71279 */ MCD_OPC_Decode, 229, 16, 255, 2, // Opcode: LDAPURSHWi /* 71284 */ MCD_OPC_FilterValue, 2, 43, 61, 0, // Skip to: 86948 /* 71289 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 71292 */ MCD_OPC_FilterValue, 0, 58, 0, 0, // Skip to: 71355 /* 71297 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 71300 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 71317 /* 71305 */ MCD_OPC_CheckField, 12, 4, 0, 20, 61, 0, // Skip to: 86948 /* 71312 */ MCD_OPC_Decode, 180, 22, 128, 3, // Opcode: SBCWr /* 71317 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71327 /* 71322 */ MCD_OPC_Decode, 165, 5, 129, 3, // Opcode: CSINVWr /* 71327 */ MCD_OPC_FilterValue, 6, 0, 61, 0, // Skip to: 86948 /* 71332 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... /* 71335 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71345 /* 71340 */ MCD_OPC_Decode, 184, 21, 141, 3, // Opcode: RBITWr /* 71345 */ MCD_OPC_FilterValue, 1, 238, 60, 0, // Skip to: 86948 /* 71350 */ MCD_OPC_Decode, 170, 3, 141, 3, // Opcode: CLZWr /* 71355 */ MCD_OPC_FilterValue, 1, 41, 0, 0, // Skip to: 71401 /* 71360 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 71363 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71373 /* 71368 */ MCD_OPC_Decode, 167, 5, 129, 3, // Opcode: CSNEGWr /* 71373 */ MCD_OPC_FilterValue, 6, 210, 60, 0, // Skip to: 86948 /* 71378 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... /* 71381 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71391 /* 71386 */ MCD_OPC_Decode, 200, 21, 141, 3, // Opcode: REV16Wr /* 71391 */ MCD_OPC_FilterValue, 1, 192, 60, 0, // Skip to: 86948 /* 71396 */ MCD_OPC_Decode, 158, 3, 141, 3, // Opcode: CLSWr /* 71401 */ MCD_OPC_FilterValue, 2, 182, 60, 0, // Skip to: 86948 /* 71406 */ MCD_OPC_CheckField, 12, 12, 128, 24, 174, 60, 0, // Skip to: 86948 /* 71414 */ MCD_OPC_Decode, 221, 21, 141, 3, // Opcode: REVWr /* 71419 */ MCD_OPC_FilterValue, 3, 117, 4, 0, // Skip to: 72565 /* 71424 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 71427 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 71676 /* 71432 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 71435 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 71596 /* 71440 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 71443 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71453 /* 71448 */ MCD_OPC_Decode, 199, 29, 255, 2, // Opcode: STURHHi /* 71453 */ MCD_OPC_FilterValue, 1, 130, 60, 0, // Skip to: 86948 /* 71458 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 71461 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71476 /* 71466 */ MCD_OPC_CheckPredicate, 1, 117, 60, 0, // Skip to: 86948 /* 71471 */ MCD_OPC_Decode, 214, 16, 131, 3, // Opcode: LDADDH /* 71476 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71491 /* 71481 */ MCD_OPC_CheckPredicate, 1, 102, 60, 0, // Skip to: 86948 /* 71486 */ MCD_OPC_Decode, 253, 16, 131, 3, // Opcode: LDCLRH /* 71491 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 71506 /* 71496 */ MCD_OPC_CheckPredicate, 1, 87, 60, 0, // Skip to: 86948 /* 71501 */ MCD_OPC_Decode, 141, 17, 131, 3, // Opcode: LDEORH /* 71506 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 71521 /* 71511 */ MCD_OPC_CheckPredicate, 1, 72, 60, 0, // Skip to: 86948 /* 71516 */ MCD_OPC_Decode, 178, 18, 131, 3, // Opcode: LDSETH /* 71521 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 71536 /* 71526 */ MCD_OPC_CheckPredicate, 1, 57, 60, 0, // Skip to: 86948 /* 71531 */ MCD_OPC_Decode, 194, 18, 131, 3, // Opcode: LDSMAXH /* 71536 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 71551 /* 71541 */ MCD_OPC_CheckPredicate, 1, 42, 60, 0, // Skip to: 86948 /* 71546 */ MCD_OPC_Decode, 210, 18, 131, 3, // Opcode: LDSMINH /* 71551 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 71566 /* 71556 */ MCD_OPC_CheckPredicate, 1, 27, 60, 0, // Skip to: 86948 /* 71561 */ MCD_OPC_Decode, 235, 18, 131, 3, // Opcode: LDUMAXH /* 71566 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 71581 /* 71571 */ MCD_OPC_CheckPredicate, 1, 12, 60, 0, // Skip to: 86948 /* 71576 */ MCD_OPC_Decode, 251, 18, 131, 3, // Opcode: LDUMINH /* 71581 */ MCD_OPC_FilterValue, 8, 2, 60, 0, // Skip to: 86948 /* 71586 */ MCD_OPC_CheckPredicate, 1, 253, 59, 0, // Skip to: 86948 /* 71591 */ MCD_OPC_Decode, 162, 30, 131, 3, // Opcode: SWPH /* 71596 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 71613 /* 71601 */ MCD_OPC_CheckField, 21, 1, 0, 236, 59, 0, // Skip to: 86948 /* 71608 */ MCD_OPC_Decode, 160, 29, 255, 2, // Opcode: STRHHpost /* 71613 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 71659 /* 71618 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 71621 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71631 /* 71626 */ MCD_OPC_Decode, 193, 29, 255, 2, // Opcode: STTRHi /* 71631 */ MCD_OPC_FilterValue, 1, 208, 59, 0, // Skip to: 86948 /* 71636 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 71639 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 71649 /* 71644 */ MCD_OPC_Decode, 162, 29, 132, 3, // Opcode: STRHHroW /* 71649 */ MCD_OPC_FilterValue, 3, 190, 59, 0, // Skip to: 86948 /* 71654 */ MCD_OPC_Decode, 163, 29, 133, 3, // Opcode: STRHHroX /* 71659 */ MCD_OPC_FilterValue, 3, 180, 59, 0, // Skip to: 86948 /* 71664 */ MCD_OPC_CheckField, 21, 1, 0, 173, 59, 0, // Skip to: 86948 /* 71671 */ MCD_OPC_Decode, 161, 29, 255, 2, // Opcode: STRHHpre /* 71676 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 71925 /* 71681 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 71684 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 71845 /* 71689 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 71692 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71702 /* 71697 */ MCD_OPC_Decode, 133, 19, 255, 2, // Opcode: LDURHHi /* 71702 */ MCD_OPC_FilterValue, 1, 137, 59, 0, // Skip to: 86948 /* 71707 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 71710 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71725 /* 71715 */ MCD_OPC_CheckPredicate, 1, 124, 59, 0, // Skip to: 86948 /* 71720 */ MCD_OPC_Decode, 216, 16, 131, 3, // Opcode: LDADDLH /* 71725 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71740 /* 71730 */ MCD_OPC_CheckPredicate, 1, 109, 59, 0, // Skip to: 86948 /* 71735 */ MCD_OPC_Decode, 255, 16, 131, 3, // Opcode: LDCLRLH /* 71740 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 71755 /* 71745 */ MCD_OPC_CheckPredicate, 1, 94, 59, 0, // Skip to: 86948 /* 71750 */ MCD_OPC_Decode, 143, 17, 131, 3, // Opcode: LDEORLH /* 71755 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 71770 /* 71760 */ MCD_OPC_CheckPredicate, 1, 79, 59, 0, // Skip to: 86948 /* 71765 */ MCD_OPC_Decode, 180, 18, 131, 3, // Opcode: LDSETLH /* 71770 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 71785 /* 71775 */ MCD_OPC_CheckPredicate, 1, 64, 59, 0, // Skip to: 86948 /* 71780 */ MCD_OPC_Decode, 196, 18, 131, 3, // Opcode: LDSMAXLH /* 71785 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 71800 /* 71790 */ MCD_OPC_CheckPredicate, 1, 49, 59, 0, // Skip to: 86948 /* 71795 */ MCD_OPC_Decode, 212, 18, 131, 3, // Opcode: LDSMINLH /* 71800 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 71815 /* 71805 */ MCD_OPC_CheckPredicate, 1, 34, 59, 0, // Skip to: 86948 /* 71810 */ MCD_OPC_Decode, 237, 18, 131, 3, // Opcode: LDUMAXLH /* 71815 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 71830 /* 71820 */ MCD_OPC_CheckPredicate, 1, 19, 59, 0, // Skip to: 86948 /* 71825 */ MCD_OPC_Decode, 253, 18, 131, 3, // Opcode: LDUMINLH /* 71830 */ MCD_OPC_FilterValue, 8, 9, 59, 0, // Skip to: 86948 /* 71835 */ MCD_OPC_CheckPredicate, 1, 4, 59, 0, // Skip to: 86948 /* 71840 */ MCD_OPC_Decode, 164, 30, 131, 3, // Opcode: SWPLH /* 71845 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 71862 /* 71850 */ MCD_OPC_CheckField, 21, 1, 0, 243, 58, 0, // Skip to: 86948 /* 71857 */ MCD_OPC_Decode, 235, 17, 255, 2, // Opcode: LDRHHpost /* 71862 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 71908 /* 71867 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 71870 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71880 /* 71875 */ MCD_OPC_Decode, 218, 18, 255, 2, // Opcode: LDTRHi /* 71880 */ MCD_OPC_FilterValue, 1, 215, 58, 0, // Skip to: 86948 /* 71885 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 71888 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 71898 /* 71893 */ MCD_OPC_Decode, 237, 17, 132, 3, // Opcode: LDRHHroW /* 71898 */ MCD_OPC_FilterValue, 3, 197, 58, 0, // Skip to: 86948 /* 71903 */ MCD_OPC_Decode, 238, 17, 133, 3, // Opcode: LDRHHroX /* 71908 */ MCD_OPC_FilterValue, 3, 187, 58, 0, // Skip to: 86948 /* 71913 */ MCD_OPC_CheckField, 21, 1, 0, 180, 58, 0, // Skip to: 86948 /* 71920 */ MCD_OPC_Decode, 236, 17, 255, 2, // Opcode: LDRHHpre /* 71925 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 72196 /* 71930 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 71933 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 72116 /* 71938 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 71941 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71951 /* 71946 */ MCD_OPC_Decode, 139, 19, 255, 2, // Opcode: LDURSHXi /* 71951 */ MCD_OPC_FilterValue, 1, 144, 58, 0, // Skip to: 86948 /* 71956 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 71959 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71974 /* 71964 */ MCD_OPC_CheckPredicate, 1, 131, 58, 0, // Skip to: 86948 /* 71969 */ MCD_OPC_Decode, 206, 16, 131, 3, // Opcode: LDADDAH /* 71974 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71989 /* 71979 */ MCD_OPC_CheckPredicate, 1, 116, 58, 0, // Skip to: 86948 /* 71984 */ MCD_OPC_Decode, 245, 16, 131, 3, // Opcode: LDCLRAH /* 71989 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 72004 /* 71994 */ MCD_OPC_CheckPredicate, 1, 101, 58, 0, // Skip to: 86948 /* 71999 */ MCD_OPC_Decode, 133, 17, 131, 3, // Opcode: LDEORAH /* 72004 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 72019 /* 72009 */ MCD_OPC_CheckPredicate, 1, 86, 58, 0, // Skip to: 86948 /* 72014 */ MCD_OPC_Decode, 170, 18, 131, 3, // Opcode: LDSETAH /* 72019 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 72034 /* 72024 */ MCD_OPC_CheckPredicate, 1, 71, 58, 0, // Skip to: 86948 /* 72029 */ MCD_OPC_Decode, 186, 18, 131, 3, // Opcode: LDSMAXAH /* 72034 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 72049 /* 72039 */ MCD_OPC_CheckPredicate, 1, 56, 58, 0, // Skip to: 86948 /* 72044 */ MCD_OPC_Decode, 202, 18, 131, 3, // Opcode: LDSMINAH /* 72049 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 72064 /* 72054 */ MCD_OPC_CheckPredicate, 1, 41, 58, 0, // Skip to: 86948 /* 72059 */ MCD_OPC_Decode, 227, 18, 131, 3, // Opcode: LDUMAXAH /* 72064 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 72079 /* 72069 */ MCD_OPC_CheckPredicate, 1, 26, 58, 0, // Skip to: 86948 /* 72074 */ MCD_OPC_Decode, 243, 18, 131, 3, // Opcode: LDUMINAH /* 72079 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 72094 /* 72084 */ MCD_OPC_CheckPredicate, 1, 11, 58, 0, // Skip to: 86948 /* 72089 */ MCD_OPC_Decode, 154, 30, 131, 3, // Opcode: SWPAH /* 72094 */ MCD_OPC_FilterValue, 12, 1, 58, 0, // Skip to: 86948 /* 72099 */ MCD_OPC_CheckPredicate, 15, 252, 57, 0, // Skip to: 86948 /* 72104 */ MCD_OPC_CheckField, 16, 5, 31, 245, 57, 0, // Skip to: 86948 /* 72111 */ MCD_OPC_Decode, 222, 16, 134, 3, // Opcode: LDAPRH /* 72116 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 72133 /* 72121 */ MCD_OPC_CheckField, 21, 1, 0, 228, 57, 0, // Skip to: 86948 /* 72128 */ MCD_OPC_Decode, 138, 18, 255, 2, // Opcode: LDRSHXpost /* 72133 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 72179 /* 72138 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 72141 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72151 /* 72146 */ MCD_OPC_Decode, 222, 18, 255, 2, // Opcode: LDTRSHXi /* 72151 */ MCD_OPC_FilterValue, 1, 200, 57, 0, // Skip to: 86948 /* 72156 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 72159 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72169 /* 72164 */ MCD_OPC_Decode, 140, 18, 135, 3, // Opcode: LDRSHXroW /* 72169 */ MCD_OPC_FilterValue, 3, 182, 57, 0, // Skip to: 86948 /* 72174 */ MCD_OPC_Decode, 141, 18, 136, 3, // Opcode: LDRSHXroX /* 72179 */ MCD_OPC_FilterValue, 3, 172, 57, 0, // Skip to: 86948 /* 72184 */ MCD_OPC_CheckField, 21, 1, 0, 165, 57, 0, // Skip to: 86948 /* 72191 */ MCD_OPC_Decode, 139, 18, 255, 2, // Opcode: LDRSHXpre /* 72196 */ MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 72445 /* 72201 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 72204 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 72365 /* 72209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 72212 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72222 /* 72217 */ MCD_OPC_Decode, 138, 19, 255, 2, // Opcode: LDURSHWi /* 72222 */ MCD_OPC_FilterValue, 1, 129, 57, 0, // Skip to: 86948 /* 72227 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 72230 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 72245 /* 72235 */ MCD_OPC_CheckPredicate, 1, 116, 57, 0, // Skip to: 86948 /* 72240 */ MCD_OPC_Decode, 208, 16, 131, 3, // Opcode: LDADDALH /* 72245 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 72260 /* 72250 */ MCD_OPC_CheckPredicate, 1, 101, 57, 0, // Skip to: 86948 /* 72255 */ MCD_OPC_Decode, 247, 16, 131, 3, // Opcode: LDCLRALH /* 72260 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 72275 /* 72265 */ MCD_OPC_CheckPredicate, 1, 86, 57, 0, // Skip to: 86948 /* 72270 */ MCD_OPC_Decode, 135, 17, 131, 3, // Opcode: LDEORALH /* 72275 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 72290 /* 72280 */ MCD_OPC_CheckPredicate, 1, 71, 57, 0, // Skip to: 86948 /* 72285 */ MCD_OPC_Decode, 172, 18, 131, 3, // Opcode: LDSETALH /* 72290 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 72305 /* 72295 */ MCD_OPC_CheckPredicate, 1, 56, 57, 0, // Skip to: 86948 /* 72300 */ MCD_OPC_Decode, 188, 18, 131, 3, // Opcode: LDSMAXALH /* 72305 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 72320 /* 72310 */ MCD_OPC_CheckPredicate, 1, 41, 57, 0, // Skip to: 86948 /* 72315 */ MCD_OPC_Decode, 204, 18, 131, 3, // Opcode: LDSMINALH /* 72320 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 72335 /* 72325 */ MCD_OPC_CheckPredicate, 1, 26, 57, 0, // Skip to: 86948 /* 72330 */ MCD_OPC_Decode, 229, 18, 131, 3, // Opcode: LDUMAXALH /* 72335 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 72350 /* 72340 */ MCD_OPC_CheckPredicate, 1, 11, 57, 0, // Skip to: 86948 /* 72345 */ MCD_OPC_Decode, 245, 18, 131, 3, // Opcode: LDUMINALH /* 72350 */ MCD_OPC_FilterValue, 8, 1, 57, 0, // Skip to: 86948 /* 72355 */ MCD_OPC_CheckPredicate, 1, 252, 56, 0, // Skip to: 86948 /* 72360 */ MCD_OPC_Decode, 156, 30, 131, 3, // Opcode: SWPALH /* 72365 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 72382 /* 72370 */ MCD_OPC_CheckField, 21, 1, 0, 235, 56, 0, // Skip to: 86948 /* 72377 */ MCD_OPC_Decode, 133, 18, 255, 2, // Opcode: LDRSHWpost /* 72382 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 72428 /* 72387 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 72390 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72400 /* 72395 */ MCD_OPC_Decode, 221, 18, 255, 2, // Opcode: LDTRSHWi /* 72400 */ MCD_OPC_FilterValue, 1, 207, 56, 0, // Skip to: 86948 /* 72405 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 72408 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72418 /* 72413 */ MCD_OPC_Decode, 135, 18, 132, 3, // Opcode: LDRSHWroW /* 72418 */ MCD_OPC_FilterValue, 3, 189, 56, 0, // Skip to: 86948 /* 72423 */ MCD_OPC_Decode, 136, 18, 133, 3, // Opcode: LDRSHWroX /* 72428 */ MCD_OPC_FilterValue, 3, 179, 56, 0, // Skip to: 86948 /* 72433 */ MCD_OPC_CheckField, 21, 1, 0, 172, 56, 0, // Skip to: 86948 /* 72440 */ MCD_OPC_Decode, 134, 18, 255, 2, // Opcode: LDRSHWpre /* 72445 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72455 /* 72450 */ MCD_OPC_Decode, 164, 29, 137, 3, // Opcode: STRHHui /* 72455 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 72465 /* 72460 */ MCD_OPC_Decode, 239, 17, 137, 3, // Opcode: LDRHHui /* 72465 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 72475 /* 72470 */ MCD_OPC_Decode, 142, 18, 137, 3, // Opcode: LDRSHXui /* 72475 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 72485 /* 72480 */ MCD_OPC_Decode, 137, 18, 137, 3, // Opcode: LDRSHWui /* 72485 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 72509 /* 72490 */ MCD_OPC_CheckField, 21, 1, 0, 115, 56, 0, // Skip to: 86948 /* 72497 */ MCD_OPC_CheckField, 10, 6, 0, 108, 56, 0, // Skip to: 86948 /* 72504 */ MCD_OPC_Decode, 178, 22, 128, 3, // Opcode: SBCSWr /* 72509 */ MCD_OPC_FilterValue, 9, 98, 56, 0, // Skip to: 86948 /* 72514 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 72517 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 72541 /* 72522 */ MCD_OPC_CheckField, 21, 1, 0, 83, 56, 0, // Skip to: 86948 /* 72529 */ MCD_OPC_CheckField, 4, 1, 0, 76, 56, 0, // Skip to: 86948 /* 72536 */ MCD_OPC_Decode, 129, 3, 139, 3, // Opcode: CCMPWr /* 72541 */ MCD_OPC_FilterValue, 2, 66, 56, 0, // Skip to: 86948 /* 72546 */ MCD_OPC_CheckField, 21, 1, 0, 59, 56, 0, // Skip to: 86948 /* 72553 */ MCD_OPC_CheckField, 4, 1, 0, 52, 56, 0, // Skip to: 86948 /* 72560 */ MCD_OPC_Decode, 128, 3, 140, 3, // Opcode: CCMPWi /* 72565 */ MCD_OPC_FilterValue, 4, 196, 1, 0, // Skip to: 73022 /* 72570 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 72573 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72583 /* 72578 */ MCD_OPC_Decode, 143, 18, 244, 2, // Opcode: LDRSWl /* 72583 */ MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 72657 /* 72588 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 72591 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 72613 /* 72596 */ MCD_OPC_CheckPredicate, 12, 11, 56, 0, // Skip to: 86948 /* 72601 */ MCD_OPC_CheckField, 10, 2, 0, 4, 56, 0, // Skip to: 86948 /* 72608 */ MCD_OPC_Decode, 237, 28, 255, 2, // Opcode: STLURWi /* 72613 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 72635 /* 72618 */ MCD_OPC_CheckPredicate, 12, 245, 55, 0, // Skip to: 86948 /* 72623 */ MCD_OPC_CheckField, 10, 2, 0, 238, 55, 0, // Skip to: 86948 /* 72630 */ MCD_OPC_Decode, 233, 16, 255, 2, // Opcode: LDAPURi /* 72635 */ MCD_OPC_FilterValue, 4, 228, 55, 0, // Skip to: 86948 /* 72640 */ MCD_OPC_CheckPredicate, 12, 223, 55, 0, // Skip to: 86948 /* 72645 */ MCD_OPC_CheckField, 10, 2, 0, 216, 55, 0, // Skip to: 86948 /* 72652 */ MCD_OPC_Decode, 231, 16, 255, 2, // Opcode: LDAPURSWi /* 72657 */ MCD_OPC_FilterValue, 2, 234, 0, 0, // Skip to: 72896 /* 72662 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 72665 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 72733 /* 72670 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 72673 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72690 /* 72678 */ MCD_OPC_CheckField, 12, 4, 0, 183, 55, 0, // Skip to: 86948 /* 72685 */ MCD_OPC_Decode, 141, 1, 142, 3, // Opcode: ADCXr /* 72690 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72700 /* 72695 */ MCD_OPC_Decode, 162, 5, 143, 3, // Opcode: CSELXr /* 72700 */ MCD_OPC_FilterValue, 6, 163, 55, 0, // Skip to: 86948 /* 72705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 72708 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72718 /* 72713 */ MCD_OPC_Decode, 156, 19, 142, 3, // Opcode: LSLVXr /* 72718 */ MCD_OPC_FilterValue, 3, 145, 55, 0, // Skip to: 86948 /* 72723 */ MCD_OPC_CheckPredicate, 13, 140, 55, 0, // Skip to: 86948 /* 72728 */ MCD_OPC_Decode, 231, 20, 144, 3, // Opcode: PACGA /* 72733 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 72768 /* 72738 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 72741 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72751 /* 72746 */ MCD_OPC_Decode, 164, 5, 143, 3, // Opcode: CSINCXr /* 72751 */ MCD_OPC_FilterValue, 6, 112, 55, 0, // Skip to: 86948 /* 72756 */ MCD_OPC_CheckField, 12, 4, 2, 105, 55, 0, // Skip to: 86948 /* 72763 */ MCD_OPC_Decode, 180, 19, 142, 3, // Opcode: LSRVXr /* 72768 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 72810 /* 72773 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 72776 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72793 /* 72781 */ MCD_OPC_CheckField, 21, 3, 6, 80, 55, 0, // Skip to: 86948 /* 72788 */ MCD_OPC_Decode, 209, 31, 142, 3, // Opcode: UDIVXr /* 72793 */ MCD_OPC_FilterValue, 2, 70, 55, 0, // Skip to: 86948 /* 72798 */ MCD_OPC_CheckField, 21, 3, 6, 63, 55, 0, // Skip to: 86948 /* 72805 */ MCD_OPC_Decode, 135, 2, 142, 3, // Opcode: ASRVXr /* 72810 */ MCD_OPC_FilterValue, 3, 53, 55, 0, // Skip to: 86948 /* 72815 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 72818 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72835 /* 72823 */ MCD_OPC_CheckField, 21, 3, 6, 38, 55, 0, // Skip to: 86948 /* 72830 */ MCD_OPC_Decode, 222, 22, 142, 3, // Opcode: SDIVXr /* 72835 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 72852 /* 72840 */ MCD_OPC_CheckField, 21, 3, 6, 21, 55, 0, // Skip to: 86948 /* 72847 */ MCD_OPC_Decode, 233, 21, 142, 3, // Opcode: RORVXr /* 72852 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 72874 /* 72857 */ MCD_OPC_CheckPredicate, 14, 6, 55, 0, // Skip to: 86948 /* 72862 */ MCD_OPC_CheckField, 21, 3, 6, 255, 54, 0, // Skip to: 86948 /* 72869 */ MCD_OPC_Decode, 160, 5, 145, 3, // Opcode: CRC32Xrr /* 72874 */ MCD_OPC_FilterValue, 5, 245, 54, 0, // Skip to: 86948 /* 72879 */ MCD_OPC_CheckPredicate, 14, 240, 54, 0, // Skip to: 86948 /* 72884 */ MCD_OPC_CheckField, 21, 3, 6, 233, 54, 0, // Skip to: 86948 /* 72891 */ MCD_OPC_Decode, 157, 5, 145, 3, // Opcode: CRC32CXrr /* 72896 */ MCD_OPC_FilterValue, 3, 223, 54, 0, // Skip to: 86948 /* 72901 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 72904 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 72932 /* 72909 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 72912 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72922 /* 72917 */ MCD_OPC_Decode, 200, 19, 146, 3, // Opcode: MADDXrrr /* 72922 */ MCD_OPC_FilterValue, 1, 197, 54, 0, // Skip to: 86948 /* 72927 */ MCD_OPC_Decode, 148, 20, 146, 3, // Opcode: MSUBXrrr /* 72932 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 72960 /* 72937 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 72940 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72950 /* 72945 */ MCD_OPC_Decode, 176, 23, 147, 3, // Opcode: SMADDLrrr /* 72950 */ MCD_OPC_FilterValue, 1, 169, 54, 0, // Skip to: 86948 /* 72955 */ MCD_OPC_Decode, 133, 24, 147, 3, // Opcode: SMSUBLrrr /* 72960 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 72977 /* 72965 */ MCD_OPC_CheckField, 15, 1, 0, 152, 54, 0, // Skip to: 86948 /* 72972 */ MCD_OPC_Decode, 138, 24, 142, 3, // Opcode: SMULHrr /* 72977 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 73005 /* 72982 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 72985 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72995 /* 72990 */ MCD_OPC_Decode, 232, 31, 147, 3, // Opcode: UMADDLrrr /* 72995 */ MCD_OPC_FilterValue, 1, 124, 54, 0, // Skip to: 86948 /* 73000 */ MCD_OPC_Decode, 187, 32, 147, 3, // Opcode: UMSUBLrrr /* 73005 */ MCD_OPC_FilterValue, 6, 114, 54, 0, // Skip to: 86948 /* 73010 */ MCD_OPC_CheckField, 15, 1, 0, 107, 54, 0, // Skip to: 86948 /* 73017 */ MCD_OPC_Decode, 192, 32, 142, 3, // Opcode: UMULHrr /* 73022 */ MCD_OPC_FilterValue, 5, 101, 4, 0, // Skip to: 74152 /* 73027 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 73030 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 73279 /* 73035 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 73038 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 73199 /* 73043 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 73046 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73056 /* 73051 */ MCD_OPC_Decode, 203, 29, 255, 2, // Opcode: STURWi /* 73056 */ MCD_OPC_FilterValue, 1, 63, 54, 0, // Skip to: 86948 /* 73061 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 73064 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73079 /* 73069 */ MCD_OPC_CheckPredicate, 1, 50, 54, 0, // Skip to: 86948 /* 73074 */ MCD_OPC_Decode, 219, 16, 131, 3, // Opcode: LDADDW /* 73079 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73094 /* 73084 */ MCD_OPC_CheckPredicate, 1, 35, 54, 0, // Skip to: 86948 /* 73089 */ MCD_OPC_Decode, 130, 17, 131, 3, // Opcode: LDCLRW /* 73094 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73109 /* 73099 */ MCD_OPC_CheckPredicate, 1, 20, 54, 0, // Skip to: 86948 /* 73104 */ MCD_OPC_Decode, 146, 17, 131, 3, // Opcode: LDEORW /* 73109 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73124 /* 73114 */ MCD_OPC_CheckPredicate, 1, 5, 54, 0, // Skip to: 86948 /* 73119 */ MCD_OPC_Decode, 183, 18, 131, 3, // Opcode: LDSETW /* 73124 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73139 /* 73129 */ MCD_OPC_CheckPredicate, 1, 246, 53, 0, // Skip to: 86948 /* 73134 */ MCD_OPC_Decode, 199, 18, 131, 3, // Opcode: LDSMAXW /* 73139 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73154 /* 73144 */ MCD_OPC_CheckPredicate, 1, 231, 53, 0, // Skip to: 86948 /* 73149 */ MCD_OPC_Decode, 215, 18, 131, 3, // Opcode: LDSMINW /* 73154 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73169 /* 73159 */ MCD_OPC_CheckPredicate, 1, 216, 53, 0, // Skip to: 86948 /* 73164 */ MCD_OPC_Decode, 240, 18, 131, 3, // Opcode: LDUMAXW /* 73169 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73184 /* 73174 */ MCD_OPC_CheckPredicate, 1, 201, 53, 0, // Skip to: 86948 /* 73179 */ MCD_OPC_Decode, 128, 19, 131, 3, // Opcode: LDUMINW /* 73184 */ MCD_OPC_FilterValue, 8, 191, 53, 0, // Skip to: 86948 /* 73189 */ MCD_OPC_CheckPredicate, 1, 186, 53, 0, // Skip to: 86948 /* 73194 */ MCD_OPC_Decode, 167, 30, 131, 3, // Opcode: SWPW /* 73199 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73216 /* 73204 */ MCD_OPC_CheckField, 21, 1, 0, 169, 53, 0, // Skip to: 86948 /* 73211 */ MCD_OPC_Decode, 180, 29, 255, 2, // Opcode: STRWpost /* 73216 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73262 /* 73221 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 73224 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73234 /* 73229 */ MCD_OPC_Decode, 194, 29, 255, 2, // Opcode: STTRWi /* 73234 */ MCD_OPC_FilterValue, 1, 141, 53, 0, // Skip to: 86948 /* 73239 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 73242 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73252 /* 73247 */ MCD_OPC_Decode, 182, 29, 132, 3, // Opcode: STRWroW /* 73252 */ MCD_OPC_FilterValue, 3, 123, 53, 0, // Skip to: 86948 /* 73257 */ MCD_OPC_Decode, 183, 29, 133, 3, // Opcode: STRWroX /* 73262 */ MCD_OPC_FilterValue, 3, 113, 53, 0, // Skip to: 86948 /* 73267 */ MCD_OPC_CheckField, 21, 1, 0, 106, 53, 0, // Skip to: 86948 /* 73274 */ MCD_OPC_Decode, 181, 29, 255, 2, // Opcode: STRWpre /* 73279 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 73528 /* 73284 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 73287 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 73448 /* 73292 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 73295 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73305 /* 73300 */ MCD_OPC_Decode, 142, 19, 255, 2, // Opcode: LDURWi /* 73305 */ MCD_OPC_FilterValue, 1, 70, 53, 0, // Skip to: 86948 /* 73310 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 73313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73328 /* 73318 */ MCD_OPC_CheckPredicate, 1, 57, 53, 0, // Skip to: 86948 /* 73323 */ MCD_OPC_Decode, 217, 16, 131, 3, // Opcode: LDADDLW /* 73328 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73343 /* 73333 */ MCD_OPC_CheckPredicate, 1, 42, 53, 0, // Skip to: 86948 /* 73338 */ MCD_OPC_Decode, 128, 17, 131, 3, // Opcode: LDCLRLW /* 73343 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73358 /* 73348 */ MCD_OPC_CheckPredicate, 1, 27, 53, 0, // Skip to: 86948 /* 73353 */ MCD_OPC_Decode, 144, 17, 131, 3, // Opcode: LDEORLW /* 73358 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73373 /* 73363 */ MCD_OPC_CheckPredicate, 1, 12, 53, 0, // Skip to: 86948 /* 73368 */ MCD_OPC_Decode, 181, 18, 131, 3, // Opcode: LDSETLW /* 73373 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73388 /* 73378 */ MCD_OPC_CheckPredicate, 1, 253, 52, 0, // Skip to: 86948 /* 73383 */ MCD_OPC_Decode, 197, 18, 131, 3, // Opcode: LDSMAXLW /* 73388 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73403 /* 73393 */ MCD_OPC_CheckPredicate, 1, 238, 52, 0, // Skip to: 86948 /* 73398 */ MCD_OPC_Decode, 213, 18, 131, 3, // Opcode: LDSMINLW /* 73403 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73418 /* 73408 */ MCD_OPC_CheckPredicate, 1, 223, 52, 0, // Skip to: 86948 /* 73413 */ MCD_OPC_Decode, 238, 18, 131, 3, // Opcode: LDUMAXLW /* 73418 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73433 /* 73423 */ MCD_OPC_CheckPredicate, 1, 208, 52, 0, // Skip to: 86948 /* 73428 */ MCD_OPC_Decode, 254, 18, 131, 3, // Opcode: LDUMINLW /* 73433 */ MCD_OPC_FilterValue, 8, 198, 52, 0, // Skip to: 86948 /* 73438 */ MCD_OPC_CheckPredicate, 1, 193, 52, 0, // Skip to: 86948 /* 73443 */ MCD_OPC_Decode, 165, 30, 131, 3, // Opcode: SWPLW /* 73448 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73465 /* 73453 */ MCD_OPC_CheckField, 21, 1, 0, 176, 52, 0, // Skip to: 86948 /* 73460 */ MCD_OPC_Decode, 156, 18, 255, 2, // Opcode: LDRWpost /* 73465 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73511 /* 73470 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 73473 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73483 /* 73478 */ MCD_OPC_Decode, 224, 18, 255, 2, // Opcode: LDTRWi /* 73483 */ MCD_OPC_FilterValue, 1, 148, 52, 0, // Skip to: 86948 /* 73488 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 73491 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73501 /* 73496 */ MCD_OPC_Decode, 158, 18, 132, 3, // Opcode: LDRWroW /* 73501 */ MCD_OPC_FilterValue, 3, 130, 52, 0, // Skip to: 86948 /* 73506 */ MCD_OPC_Decode, 159, 18, 133, 3, // Opcode: LDRWroX /* 73511 */ MCD_OPC_FilterValue, 3, 120, 52, 0, // Skip to: 86948 /* 73516 */ MCD_OPC_CheckField, 21, 1, 0, 113, 52, 0, // Skip to: 86948 /* 73523 */ MCD_OPC_Decode, 157, 18, 255, 2, // Opcode: LDRWpre /* 73528 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 73799 /* 73533 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 73536 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 73719 /* 73541 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 73544 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73554 /* 73549 */ MCD_OPC_Decode, 140, 19, 255, 2, // Opcode: LDURSWi /* 73554 */ MCD_OPC_FilterValue, 1, 77, 52, 0, // Skip to: 86948 /* 73559 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 73562 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73577 /* 73567 */ MCD_OPC_CheckPredicate, 1, 64, 52, 0, // Skip to: 86948 /* 73572 */ MCD_OPC_Decode, 211, 16, 131, 3, // Opcode: LDADDAW /* 73577 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73592 /* 73582 */ MCD_OPC_CheckPredicate, 1, 49, 52, 0, // Skip to: 86948 /* 73587 */ MCD_OPC_Decode, 250, 16, 131, 3, // Opcode: LDCLRAW /* 73592 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73607 /* 73597 */ MCD_OPC_CheckPredicate, 1, 34, 52, 0, // Skip to: 86948 /* 73602 */ MCD_OPC_Decode, 138, 17, 131, 3, // Opcode: LDEORAW /* 73607 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73622 /* 73612 */ MCD_OPC_CheckPredicate, 1, 19, 52, 0, // Skip to: 86948 /* 73617 */ MCD_OPC_Decode, 175, 18, 131, 3, // Opcode: LDSETAW /* 73622 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73637 /* 73627 */ MCD_OPC_CheckPredicate, 1, 4, 52, 0, // Skip to: 86948 /* 73632 */ MCD_OPC_Decode, 191, 18, 131, 3, // Opcode: LDSMAXAW /* 73637 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73652 /* 73642 */ MCD_OPC_CheckPredicate, 1, 245, 51, 0, // Skip to: 86948 /* 73647 */ MCD_OPC_Decode, 207, 18, 131, 3, // Opcode: LDSMINAW /* 73652 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73667 /* 73657 */ MCD_OPC_CheckPredicate, 1, 230, 51, 0, // Skip to: 86948 /* 73662 */ MCD_OPC_Decode, 232, 18, 131, 3, // Opcode: LDUMAXAW /* 73667 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73682 /* 73672 */ MCD_OPC_CheckPredicate, 1, 215, 51, 0, // Skip to: 86948 /* 73677 */ MCD_OPC_Decode, 248, 18, 131, 3, // Opcode: LDUMINAW /* 73682 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 73697 /* 73687 */ MCD_OPC_CheckPredicate, 1, 200, 51, 0, // Skip to: 86948 /* 73692 */ MCD_OPC_Decode, 159, 30, 131, 3, // Opcode: SWPAW /* 73697 */ MCD_OPC_FilterValue, 12, 190, 51, 0, // Skip to: 86948 /* 73702 */ MCD_OPC_CheckPredicate, 15, 185, 51, 0, // Skip to: 86948 /* 73707 */ MCD_OPC_CheckField, 16, 5, 31, 178, 51, 0, // Skip to: 86948 /* 73714 */ MCD_OPC_Decode, 223, 16, 134, 3, // Opcode: LDAPRW /* 73719 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73736 /* 73724 */ MCD_OPC_CheckField, 21, 1, 0, 161, 51, 0, // Skip to: 86948 /* 73731 */ MCD_OPC_Decode, 144, 18, 255, 2, // Opcode: LDRSWpost /* 73736 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73782 /* 73741 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 73744 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73754 /* 73749 */ MCD_OPC_Decode, 223, 18, 255, 2, // Opcode: LDTRSWi /* 73754 */ MCD_OPC_FilterValue, 1, 133, 51, 0, // Skip to: 86948 /* 73759 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 73762 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73772 /* 73767 */ MCD_OPC_Decode, 146, 18, 135, 3, // Opcode: LDRSWroW /* 73772 */ MCD_OPC_FilterValue, 3, 115, 51, 0, // Skip to: 86948 /* 73777 */ MCD_OPC_Decode, 147, 18, 136, 3, // Opcode: LDRSWroX /* 73782 */ MCD_OPC_FilterValue, 3, 105, 51, 0, // Skip to: 86948 /* 73787 */ MCD_OPC_CheckField, 21, 1, 0, 98, 51, 0, // Skip to: 86948 /* 73794 */ MCD_OPC_Decode, 145, 18, 255, 2, // Opcode: LDRSWpre /* 73799 */ MCD_OPC_FilterValue, 3, 201, 0, 0, // Skip to: 74005 /* 73804 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 73807 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 73829 /* 73812 */ MCD_OPC_CheckPredicate, 1, 75, 51, 0, // Skip to: 86948 /* 73817 */ MCD_OPC_CheckField, 21, 1, 1, 68, 51, 0, // Skip to: 86948 /* 73824 */ MCD_OPC_Decode, 209, 16, 131, 3, // Opcode: LDADDALW /* 73829 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 73851 /* 73834 */ MCD_OPC_CheckPredicate, 1, 53, 51, 0, // Skip to: 86948 /* 73839 */ MCD_OPC_CheckField, 21, 1, 1, 46, 51, 0, // Skip to: 86948 /* 73846 */ MCD_OPC_Decode, 248, 16, 131, 3, // Opcode: LDCLRALW /* 73851 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 73873 /* 73856 */ MCD_OPC_CheckPredicate, 1, 31, 51, 0, // Skip to: 86948 /* 73861 */ MCD_OPC_CheckField, 21, 1, 1, 24, 51, 0, // Skip to: 86948 /* 73868 */ MCD_OPC_Decode, 136, 17, 131, 3, // Opcode: LDEORALW /* 73873 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 73895 /* 73878 */ MCD_OPC_CheckPredicate, 1, 9, 51, 0, // Skip to: 86948 /* 73883 */ MCD_OPC_CheckField, 21, 1, 1, 2, 51, 0, // Skip to: 86948 /* 73890 */ MCD_OPC_Decode, 173, 18, 131, 3, // Opcode: LDSETALW /* 73895 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 73917 /* 73900 */ MCD_OPC_CheckPredicate, 1, 243, 50, 0, // Skip to: 86948 /* 73905 */ MCD_OPC_CheckField, 21, 1, 1, 236, 50, 0, // Skip to: 86948 /* 73912 */ MCD_OPC_Decode, 189, 18, 131, 3, // Opcode: LDSMAXALW /* 73917 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 73939 /* 73922 */ MCD_OPC_CheckPredicate, 1, 221, 50, 0, // Skip to: 86948 /* 73927 */ MCD_OPC_CheckField, 21, 1, 1, 214, 50, 0, // Skip to: 86948 /* 73934 */ MCD_OPC_Decode, 205, 18, 131, 3, // Opcode: LDSMINALW /* 73939 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 73961 /* 73944 */ MCD_OPC_CheckPredicate, 1, 199, 50, 0, // Skip to: 86948 /* 73949 */ MCD_OPC_CheckField, 21, 1, 1, 192, 50, 0, // Skip to: 86948 /* 73956 */ MCD_OPC_Decode, 230, 18, 131, 3, // Opcode: LDUMAXALW /* 73961 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 73983 /* 73966 */ MCD_OPC_CheckPredicate, 1, 177, 50, 0, // Skip to: 86948 /* 73971 */ MCD_OPC_CheckField, 21, 1, 1, 170, 50, 0, // Skip to: 86948 /* 73978 */ MCD_OPC_Decode, 246, 18, 131, 3, // Opcode: LDUMINALW /* 73983 */ MCD_OPC_FilterValue, 32, 160, 50, 0, // Skip to: 86948 /* 73988 */ MCD_OPC_CheckPredicate, 1, 155, 50, 0, // Skip to: 86948 /* 73993 */ MCD_OPC_CheckField, 21, 1, 1, 148, 50, 0, // Skip to: 86948 /* 74000 */ MCD_OPC_Decode, 157, 30, 131, 3, // Opcode: SWPALW /* 74005 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74015 /* 74010 */ MCD_OPC_Decode, 184, 29, 137, 3, // Opcode: STRWui /* 74015 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 74025 /* 74020 */ MCD_OPC_Decode, 160, 18, 137, 3, // Opcode: LDRWui /* 74025 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 74035 /* 74030 */ MCD_OPC_Decode, 148, 18, 137, 3, // Opcode: LDRSWui /* 74035 */ MCD_OPC_FilterValue, 8, 56, 0, 0, // Skip to: 74096 /* 74040 */ MCD_OPC_ExtractField, 10, 5, // Inst{14-10} ... /* 74043 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 74067 /* 74048 */ MCD_OPC_CheckField, 21, 1, 0, 93, 50, 0, // Skip to: 86948 /* 74055 */ MCD_OPC_CheckField, 15, 1, 0, 86, 50, 0, // Skip to: 86948 /* 74062 */ MCD_OPC_Decode, 139, 1, 142, 3, // Opcode: ADCSXr /* 74067 */ MCD_OPC_FilterValue, 1, 76, 50, 0, // Skip to: 86948 /* 74072 */ MCD_OPC_CheckPredicate, 12, 71, 50, 0, // Skip to: 86948 /* 74077 */ MCD_OPC_CheckField, 21, 1, 0, 64, 50, 0, // Skip to: 86948 /* 74084 */ MCD_OPC_CheckField, 4, 1, 0, 57, 50, 0, // Skip to: 86948 /* 74091 */ MCD_OPC_Decode, 231, 21, 148, 3, // Opcode: RMIF /* 74096 */ MCD_OPC_FilterValue, 9, 47, 50, 0, // Skip to: 86948 /* 74101 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 74104 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 74128 /* 74109 */ MCD_OPC_CheckField, 21, 1, 0, 32, 50, 0, // Skip to: 86948 /* 74116 */ MCD_OPC_CheckField, 4, 1, 0, 25, 50, 0, // Skip to: 86948 /* 74123 */ MCD_OPC_Decode, 255, 2, 149, 3, // Opcode: CCMNXr /* 74128 */ MCD_OPC_FilterValue, 2, 15, 50, 0, // Skip to: 86948 /* 74133 */ MCD_OPC_CheckField, 21, 1, 0, 8, 50, 0, // Skip to: 86948 /* 74140 */ MCD_OPC_CheckField, 4, 1, 0, 1, 50, 0, // Skip to: 86948 /* 74147 */ MCD_OPC_Decode, 254, 2, 150, 3, // Opcode: CCMNXi /* 74152 */ MCD_OPC_FilterValue, 6, 56, 2, 0, // Skip to: 74725 /* 74157 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 74160 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74170 /* 74165 */ MCD_OPC_Decode, 152, 21, 151, 3, // Opcode: PRFMl /* 74170 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 74222 /* 74175 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 74178 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 74200 /* 74183 */ MCD_OPC_CheckPredicate, 12, 216, 49, 0, // Skip to: 86948 /* 74188 */ MCD_OPC_CheckField, 10, 2, 0, 209, 49, 0, // Skip to: 86948 /* 74195 */ MCD_OPC_Decode, 238, 28, 255, 2, // Opcode: STLURXi /* 74200 */ MCD_OPC_FilterValue, 2, 199, 49, 0, // Skip to: 86948 /* 74205 */ MCD_OPC_CheckPredicate, 12, 194, 49, 0, // Skip to: 86948 /* 74210 */ MCD_OPC_CheckField, 10, 2, 0, 187, 49, 0, // Skip to: 86948 /* 74217 */ MCD_OPC_Decode, 232, 16, 255, 2, // Opcode: LDAPURXi /* 74222 */ MCD_OPC_FilterValue, 2, 177, 49, 0, // Skip to: 86948 /* 74227 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 74230 */ MCD_OPC_FilterValue, 0, 154, 0, 0, // Skip to: 74389 /* 74235 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 74238 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 74255 /* 74243 */ MCD_OPC_CheckField, 12, 4, 0, 154, 49, 0, // Skip to: 86948 /* 74250 */ MCD_OPC_Decode, 181, 22, 142, 3, // Opcode: SBCXr /* 74255 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74265 /* 74260 */ MCD_OPC_Decode, 166, 5, 143, 3, // Opcode: CSINVXr /* 74265 */ MCD_OPC_FilterValue, 6, 134, 49, 0, // Skip to: 86948 /* 74270 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... /* 74273 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74283 /* 74278 */ MCD_OPC_Decode, 185, 21, 152, 3, // Opcode: RBITXr /* 74283 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 74293 /* 74288 */ MCD_OPC_Decode, 171, 3, 152, 3, // Opcode: CLZXr /* 74293 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 74308 /* 74298 */ MCD_OPC_CheckPredicate, 13, 101, 49, 0, // Skip to: 86948 /* 74303 */ MCD_OPC_Decode, 232, 20, 153, 3, // Opcode: PACIA /* 74308 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 74323 /* 74313 */ MCD_OPC_CheckPredicate, 13, 86, 49, 0, // Skip to: 86948 /* 74318 */ MCD_OPC_Decode, 158, 2, 153, 3, // Opcode: AUTIA /* 74323 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 74345 /* 74328 */ MCD_OPC_CheckPredicate, 13, 71, 49, 0, // Skip to: 86948 /* 74333 */ MCD_OPC_CheckField, 5, 5, 31, 64, 49, 0, // Skip to: 86948 /* 74340 */ MCD_OPC_Decode, 240, 20, 154, 3, // Opcode: PACIZA /* 74345 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 74367 /* 74350 */ MCD_OPC_CheckPredicate, 13, 49, 49, 0, // Skip to: 86948 /* 74355 */ MCD_OPC_CheckField, 5, 5, 31, 42, 49, 0, // Skip to: 86948 /* 74362 */ MCD_OPC_Decode, 166, 2, 154, 3, // Opcode: AUTIZA /* 74367 */ MCD_OPC_FilterValue, 20, 32, 49, 0, // Skip to: 86948 /* 74372 */ MCD_OPC_CheckPredicate, 13, 27, 49, 0, // Skip to: 86948 /* 74377 */ MCD_OPC_CheckField, 5, 5, 31, 20, 49, 0, // Skip to: 86948 /* 74384 */ MCD_OPC_Decode, 253, 34, 154, 3, // Opcode: XPACI /* 74389 */ MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 74531 /* 74394 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 74397 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74407 /* 74402 */ MCD_OPC_Decode, 168, 5, 143, 3, // Opcode: CSNEGXr /* 74407 */ MCD_OPC_FilterValue, 6, 248, 48, 0, // Skip to: 86948 /* 74412 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... /* 74415 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74425 /* 74420 */ MCD_OPC_Decode, 201, 21, 152, 3, // Opcode: REV16Xr /* 74425 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 74435 /* 74430 */ MCD_OPC_Decode, 159, 3, 152, 3, // Opcode: CLSXr /* 74435 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 74450 /* 74440 */ MCD_OPC_CheckPredicate, 13, 215, 48, 0, // Skip to: 86948 /* 74445 */ MCD_OPC_Decode, 236, 20, 153, 3, // Opcode: PACIB /* 74450 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 74465 /* 74455 */ MCD_OPC_CheckPredicate, 13, 200, 48, 0, // Skip to: 86948 /* 74460 */ MCD_OPC_Decode, 162, 2, 153, 3, // Opcode: AUTIB /* 74465 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 74487 /* 74470 */ MCD_OPC_CheckPredicate, 13, 185, 48, 0, // Skip to: 86948 /* 74475 */ MCD_OPC_CheckField, 5, 5, 31, 178, 48, 0, // Skip to: 86948 /* 74482 */ MCD_OPC_Decode, 241, 20, 154, 3, // Opcode: PACIZB /* 74487 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 74509 /* 74492 */ MCD_OPC_CheckPredicate, 13, 163, 48, 0, // Skip to: 86948 /* 74497 */ MCD_OPC_CheckField, 5, 5, 31, 156, 48, 0, // Skip to: 86948 /* 74504 */ MCD_OPC_Decode, 167, 2, 154, 3, // Opcode: AUTIZB /* 74509 */ MCD_OPC_FilterValue, 20, 146, 48, 0, // Skip to: 86948 /* 74514 */ MCD_OPC_CheckPredicate, 13, 141, 48, 0, // Skip to: 86948 /* 74519 */ MCD_OPC_CheckField, 5, 5, 31, 134, 48, 0, // Skip to: 86948 /* 74526 */ MCD_OPC_Decode, 252, 34, 154, 3, // Opcode: XPACD /* 74531 */ MCD_OPC_FilterValue, 2, 92, 0, 0, // Skip to: 74628 /* 74536 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... /* 74539 */ MCD_OPC_FilterValue, 128, 24, 5, 0, 0, // Skip to: 74550 /* 74545 */ MCD_OPC_Decode, 204, 21, 152, 3, // Opcode: REV32Xr /* 74550 */ MCD_OPC_FilterValue, 144, 24, 10, 0, 0, // Skip to: 74566 /* 74556 */ MCD_OPC_CheckPredicate, 13, 99, 48, 0, // Skip to: 86948 /* 74561 */ MCD_OPC_Decode, 227, 20, 153, 3, // Opcode: PACDA /* 74566 */ MCD_OPC_FilterValue, 145, 24, 10, 0, 0, // Skip to: 74582 /* 74572 */ MCD_OPC_CheckPredicate, 13, 83, 48, 0, // Skip to: 86948 /* 74577 */ MCD_OPC_Decode, 154, 2, 153, 3, // Opcode: AUTDA /* 74582 */ MCD_OPC_FilterValue, 146, 24, 17, 0, 0, // Skip to: 74605 /* 74588 */ MCD_OPC_CheckPredicate, 13, 67, 48, 0, // Skip to: 86948 /* 74593 */ MCD_OPC_CheckField, 5, 5, 31, 60, 48, 0, // Skip to: 86948 /* 74600 */ MCD_OPC_Decode, 229, 20, 154, 3, // Opcode: PACDZA /* 74605 */ MCD_OPC_FilterValue, 147, 24, 49, 48, 0, // Skip to: 86948 /* 74611 */ MCD_OPC_CheckPredicate, 13, 44, 48, 0, // Skip to: 86948 /* 74616 */ MCD_OPC_CheckField, 5, 5, 31, 37, 48, 0, // Skip to: 86948 /* 74623 */ MCD_OPC_Decode, 156, 2, 154, 3, // Opcode: AUTDZA /* 74628 */ MCD_OPC_FilterValue, 3, 27, 48, 0, // Skip to: 86948 /* 74633 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... /* 74636 */ MCD_OPC_FilterValue, 128, 24, 5, 0, 0, // Skip to: 74647 /* 74642 */ MCD_OPC_Decode, 222, 21, 152, 3, // Opcode: REVXr /* 74647 */ MCD_OPC_FilterValue, 144, 24, 10, 0, 0, // Skip to: 74663 /* 74653 */ MCD_OPC_CheckPredicate, 13, 2, 48, 0, // Skip to: 86948 /* 74658 */ MCD_OPC_Decode, 228, 20, 153, 3, // Opcode: PACDB /* 74663 */ MCD_OPC_FilterValue, 145, 24, 10, 0, 0, // Skip to: 74679 /* 74669 */ MCD_OPC_CheckPredicate, 13, 242, 47, 0, // Skip to: 86948 /* 74674 */ MCD_OPC_Decode, 155, 2, 153, 3, // Opcode: AUTDB /* 74679 */ MCD_OPC_FilterValue, 146, 24, 17, 0, 0, // Skip to: 74702 /* 74685 */ MCD_OPC_CheckPredicate, 13, 226, 47, 0, // Skip to: 86948 /* 74690 */ MCD_OPC_CheckField, 5, 5, 31, 219, 47, 0, // Skip to: 86948 /* 74697 */ MCD_OPC_Decode, 230, 20, 154, 3, // Opcode: PACDZB /* 74702 */ MCD_OPC_FilterValue, 147, 24, 208, 47, 0, // Skip to: 86948 /* 74708 */ MCD_OPC_CheckPredicate, 13, 203, 47, 0, // Skip to: 86948 /* 74713 */ MCD_OPC_CheckField, 5, 5, 31, 196, 47, 0, // Skip to: 86948 /* 74720 */ MCD_OPC_Decode, 157, 2, 154, 3, // Opcode: AUTDZB /* 74725 */ MCD_OPC_FilterValue, 7, 186, 47, 0, // Skip to: 86948 /* 74730 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 74733 */ MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 75241 /* 74738 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 74741 */ MCD_OPC_FilterValue, 0, 53, 1, 0, // Skip to: 75055 /* 74746 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 74749 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74759 /* 74754 */ MCD_OPC_Decode, 204, 29, 255, 2, // Opcode: STURXi /* 74759 */ MCD_OPC_FilterValue, 1, 138, 0, 0, // Skip to: 74902 /* 74764 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 74767 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 74782 /* 74772 */ MCD_OPC_CheckPredicate, 1, 139, 47, 0, // Skip to: 86948 /* 74777 */ MCD_OPC_Decode, 220, 16, 155, 3, // Opcode: LDADDX /* 74782 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 74797 /* 74787 */ MCD_OPC_CheckPredicate, 1, 124, 47, 0, // Skip to: 86948 /* 74792 */ MCD_OPC_Decode, 131, 17, 155, 3, // Opcode: LDCLRX /* 74797 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 74812 /* 74802 */ MCD_OPC_CheckPredicate, 1, 109, 47, 0, // Skip to: 86948 /* 74807 */ MCD_OPC_Decode, 147, 17, 155, 3, // Opcode: LDEORX /* 74812 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 74827 /* 74817 */ MCD_OPC_CheckPredicate, 1, 94, 47, 0, // Skip to: 86948 /* 74822 */ MCD_OPC_Decode, 184, 18, 155, 3, // Opcode: LDSETX /* 74827 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 74842 /* 74832 */ MCD_OPC_CheckPredicate, 1, 79, 47, 0, // Skip to: 86948 /* 74837 */ MCD_OPC_Decode, 200, 18, 155, 3, // Opcode: LDSMAXX /* 74842 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 74857 /* 74847 */ MCD_OPC_CheckPredicate, 1, 64, 47, 0, // Skip to: 86948 /* 74852 */ MCD_OPC_Decode, 216, 18, 155, 3, // Opcode: LDSMINX /* 74857 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 74872 /* 74862 */ MCD_OPC_CheckPredicate, 1, 49, 47, 0, // Skip to: 86948 /* 74867 */ MCD_OPC_Decode, 241, 18, 155, 3, // Opcode: LDUMAXX /* 74872 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 74887 /* 74877 */ MCD_OPC_CheckPredicate, 1, 34, 47, 0, // Skip to: 86948 /* 74882 */ MCD_OPC_Decode, 129, 19, 155, 3, // Opcode: LDUMINX /* 74887 */ MCD_OPC_FilterValue, 8, 24, 47, 0, // Skip to: 86948 /* 74892 */ MCD_OPC_CheckPredicate, 1, 19, 47, 0, // Skip to: 86948 /* 74897 */ MCD_OPC_Decode, 168, 30, 155, 3, // Opcode: SWPX /* 74902 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 74912 /* 74907 */ MCD_OPC_Decode, 143, 19, 255, 2, // Opcode: LDURXi /* 74912 */ MCD_OPC_FilterValue, 3, 255, 46, 0, // Skip to: 86948 /* 74917 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 74920 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 74935 /* 74925 */ MCD_OPC_CheckPredicate, 1, 242, 46, 0, // Skip to: 86948 /* 74930 */ MCD_OPC_Decode, 218, 16, 155, 3, // Opcode: LDADDLX /* 74935 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 74950 /* 74940 */ MCD_OPC_CheckPredicate, 1, 227, 46, 0, // Skip to: 86948 /* 74945 */ MCD_OPC_Decode, 129, 17, 155, 3, // Opcode: LDCLRLX /* 74950 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 74965 /* 74955 */ MCD_OPC_CheckPredicate, 1, 212, 46, 0, // Skip to: 86948 /* 74960 */ MCD_OPC_Decode, 145, 17, 155, 3, // Opcode: LDEORLX /* 74965 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 74980 /* 74970 */ MCD_OPC_CheckPredicate, 1, 197, 46, 0, // Skip to: 86948 /* 74975 */ MCD_OPC_Decode, 182, 18, 155, 3, // Opcode: LDSETLX /* 74980 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 74995 /* 74985 */ MCD_OPC_CheckPredicate, 1, 182, 46, 0, // Skip to: 86948 /* 74990 */ MCD_OPC_Decode, 198, 18, 155, 3, // Opcode: LDSMAXLX /* 74995 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75010 /* 75000 */ MCD_OPC_CheckPredicate, 1, 167, 46, 0, // Skip to: 86948 /* 75005 */ MCD_OPC_Decode, 214, 18, 155, 3, // Opcode: LDSMINLX /* 75010 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75025 /* 75015 */ MCD_OPC_CheckPredicate, 1, 152, 46, 0, // Skip to: 86948 /* 75020 */ MCD_OPC_Decode, 239, 18, 155, 3, // Opcode: LDUMAXLX /* 75025 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75040 /* 75030 */ MCD_OPC_CheckPredicate, 1, 137, 46, 0, // Skip to: 86948 /* 75035 */ MCD_OPC_Decode, 255, 18, 155, 3, // Opcode: LDUMINLX /* 75040 */ MCD_OPC_FilterValue, 8, 127, 46, 0, // Skip to: 86948 /* 75045 */ MCD_OPC_CheckPredicate, 1, 122, 46, 0, // Skip to: 86948 /* 75050 */ MCD_OPC_Decode, 166, 30, 155, 3, // Opcode: SWPLX /* 75055 */ MCD_OPC_FilterValue, 1, 46, 0, 0, // Skip to: 75106 /* 75060 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 75063 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 75091 /* 75068 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 75071 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75081 /* 75076 */ MCD_OPC_Decode, 185, 29, 255, 2, // Opcode: STRXpost /* 75081 */ MCD_OPC_FilterValue, 1, 86, 46, 0, // Skip to: 86948 /* 75086 */ MCD_OPC_Decode, 162, 18, 255, 2, // Opcode: LDRXpost /* 75091 */ MCD_OPC_FilterValue, 1, 76, 46, 0, // Skip to: 86948 /* 75096 */ MCD_OPC_CheckPredicate, 13, 71, 46, 0, // Skip to: 86948 /* 75101 */ MCD_OPC_Decode, 215, 17, 156, 3, // Opcode: LDRAAindexed /* 75106 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 75190 /* 75111 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 75114 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75124 /* 75119 */ MCD_OPC_Decode, 195, 29, 255, 2, // Opcode: STTRXi /* 75124 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 75152 /* 75129 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 75132 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75142 /* 75137 */ MCD_OPC_Decode, 187, 29, 135, 3, // Opcode: STRXroW /* 75142 */ MCD_OPC_FilterValue, 3, 25, 46, 0, // Skip to: 86948 /* 75147 */ MCD_OPC_Decode, 188, 29, 136, 3, // Opcode: STRXroX /* 75152 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75162 /* 75157 */ MCD_OPC_Decode, 225, 18, 255, 2, // Opcode: LDTRXi /* 75162 */ MCD_OPC_FilterValue, 3, 5, 46, 0, // Skip to: 86948 /* 75167 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 75170 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75180 /* 75175 */ MCD_OPC_Decode, 164, 18, 135, 3, // Opcode: LDRXroW /* 75180 */ MCD_OPC_FilterValue, 3, 243, 45, 0, // Skip to: 86948 /* 75185 */ MCD_OPC_Decode, 165, 18, 136, 3, // Opcode: LDRXroX /* 75190 */ MCD_OPC_FilterValue, 3, 233, 45, 0, // Skip to: 86948 /* 75195 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 75198 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 75226 /* 75203 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 75206 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75216 /* 75211 */ MCD_OPC_Decode, 186, 29, 255, 2, // Opcode: STRXpre /* 75216 */ MCD_OPC_FilterValue, 1, 207, 45, 0, // Skip to: 86948 /* 75221 */ MCD_OPC_Decode, 163, 18, 255, 2, // Opcode: LDRXpre /* 75226 */ MCD_OPC_FilterValue, 1, 197, 45, 0, // Skip to: 86948 /* 75231 */ MCD_OPC_CheckPredicate, 13, 192, 45, 0, // Skip to: 86948 /* 75236 */ MCD_OPC_Decode, 216, 17, 157, 3, // Opcode: LDRAAwriteback /* 75241 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 75661 /* 75246 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 75249 */ MCD_OPC_FilterValue, 0, 65, 1, 0, // Skip to: 75575 /* 75254 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 75257 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75267 /* 75262 */ MCD_OPC_Decode, 157, 21, 255, 2, // Opcode: PRFUMi /* 75267 */ MCD_OPC_FilterValue, 1, 160, 0, 0, // Skip to: 75432 /* 75272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 75275 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75290 /* 75280 */ MCD_OPC_CheckPredicate, 1, 143, 45, 0, // Skip to: 86948 /* 75285 */ MCD_OPC_Decode, 212, 16, 155, 3, // Opcode: LDADDAX /* 75290 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75305 /* 75295 */ MCD_OPC_CheckPredicate, 1, 128, 45, 0, // Skip to: 86948 /* 75300 */ MCD_OPC_Decode, 251, 16, 155, 3, // Opcode: LDCLRAX /* 75305 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75320 /* 75310 */ MCD_OPC_CheckPredicate, 1, 113, 45, 0, // Skip to: 86948 /* 75315 */ MCD_OPC_Decode, 139, 17, 155, 3, // Opcode: LDEORAX /* 75320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75335 /* 75325 */ MCD_OPC_CheckPredicate, 1, 98, 45, 0, // Skip to: 86948 /* 75330 */ MCD_OPC_Decode, 176, 18, 155, 3, // Opcode: LDSETAX /* 75335 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75350 /* 75340 */ MCD_OPC_CheckPredicate, 1, 83, 45, 0, // Skip to: 86948 /* 75345 */ MCD_OPC_Decode, 192, 18, 155, 3, // Opcode: LDSMAXAX /* 75350 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75365 /* 75355 */ MCD_OPC_CheckPredicate, 1, 68, 45, 0, // Skip to: 86948 /* 75360 */ MCD_OPC_Decode, 208, 18, 155, 3, // Opcode: LDSMINAX /* 75365 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75380 /* 75370 */ MCD_OPC_CheckPredicate, 1, 53, 45, 0, // Skip to: 86948 /* 75375 */ MCD_OPC_Decode, 233, 18, 155, 3, // Opcode: LDUMAXAX /* 75380 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75395 /* 75385 */ MCD_OPC_CheckPredicate, 1, 38, 45, 0, // Skip to: 86948 /* 75390 */ MCD_OPC_Decode, 249, 18, 155, 3, // Opcode: LDUMINAX /* 75395 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 75410 /* 75400 */ MCD_OPC_CheckPredicate, 1, 23, 45, 0, // Skip to: 86948 /* 75405 */ MCD_OPC_Decode, 160, 30, 155, 3, // Opcode: SWPAX /* 75410 */ MCD_OPC_FilterValue, 12, 13, 45, 0, // Skip to: 86948 /* 75415 */ MCD_OPC_CheckPredicate, 15, 8, 45, 0, // Skip to: 86948 /* 75420 */ MCD_OPC_CheckField, 16, 5, 31, 1, 45, 0, // Skip to: 86948 /* 75427 */ MCD_OPC_Decode, 224, 16, 153, 3, // Opcode: LDAPRX /* 75432 */ MCD_OPC_FilterValue, 3, 247, 44, 0, // Skip to: 86948 /* 75437 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 75440 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75455 /* 75445 */ MCD_OPC_CheckPredicate, 1, 234, 44, 0, // Skip to: 86948 /* 75450 */ MCD_OPC_Decode, 210, 16, 155, 3, // Opcode: LDADDALX /* 75455 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75470 /* 75460 */ MCD_OPC_CheckPredicate, 1, 219, 44, 0, // Skip to: 86948 /* 75465 */ MCD_OPC_Decode, 249, 16, 155, 3, // Opcode: LDCLRALX /* 75470 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75485 /* 75475 */ MCD_OPC_CheckPredicate, 1, 204, 44, 0, // Skip to: 86948 /* 75480 */ MCD_OPC_Decode, 137, 17, 155, 3, // Opcode: LDEORALX /* 75485 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75500 /* 75490 */ MCD_OPC_CheckPredicate, 1, 189, 44, 0, // Skip to: 86948 /* 75495 */ MCD_OPC_Decode, 174, 18, 155, 3, // Opcode: LDSETALX /* 75500 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75515 /* 75505 */ MCD_OPC_CheckPredicate, 1, 174, 44, 0, // Skip to: 86948 /* 75510 */ MCD_OPC_Decode, 190, 18, 155, 3, // Opcode: LDSMAXALX /* 75515 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75530 /* 75520 */ MCD_OPC_CheckPredicate, 1, 159, 44, 0, // Skip to: 86948 /* 75525 */ MCD_OPC_Decode, 206, 18, 155, 3, // Opcode: LDSMINALX /* 75530 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75545 /* 75535 */ MCD_OPC_CheckPredicate, 1, 144, 44, 0, // Skip to: 86948 /* 75540 */ MCD_OPC_Decode, 231, 18, 155, 3, // Opcode: LDUMAXALX /* 75545 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75560 /* 75550 */ MCD_OPC_CheckPredicate, 1, 129, 44, 0, // Skip to: 86948 /* 75555 */ MCD_OPC_Decode, 247, 18, 155, 3, // Opcode: LDUMINALX /* 75560 */ MCD_OPC_FilterValue, 8, 119, 44, 0, // Skip to: 86948 /* 75565 */ MCD_OPC_CheckPredicate, 1, 114, 44, 0, // Skip to: 86948 /* 75570 */ MCD_OPC_Decode, 158, 30, 155, 3, // Opcode: SWPALX /* 75575 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 75597 /* 75580 */ MCD_OPC_CheckPredicate, 13, 99, 44, 0, // Skip to: 86948 /* 75585 */ MCD_OPC_CheckField, 21, 1, 1, 92, 44, 0, // Skip to: 86948 /* 75592 */ MCD_OPC_Decode, 217, 17, 156, 3, // Opcode: LDRABindexed /* 75597 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 75639 /* 75602 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 75605 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 75622 /* 75610 */ MCD_OPC_CheckField, 21, 2, 1, 67, 44, 0, // Skip to: 86948 /* 75617 */ MCD_OPC_Decode, 153, 21, 158, 3, // Opcode: PRFMroW /* 75622 */ MCD_OPC_FilterValue, 3, 57, 44, 0, // Skip to: 86948 /* 75627 */ MCD_OPC_CheckField, 21, 2, 1, 50, 44, 0, // Skip to: 86948 /* 75634 */ MCD_OPC_Decode, 154, 21, 159, 3, // Opcode: PRFMroX /* 75639 */ MCD_OPC_FilterValue, 3, 40, 44, 0, // Skip to: 86948 /* 75644 */ MCD_OPC_CheckPredicate, 13, 35, 44, 0, // Skip to: 86948 /* 75649 */ MCD_OPC_CheckField, 21, 1, 1, 28, 44, 0, // Skip to: 86948 /* 75656 */ MCD_OPC_Decode, 218, 17, 157, 3, // Opcode: LDRABwriteback /* 75661 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 75689 /* 75666 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 75669 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75679 /* 75674 */ MCD_OPC_Decode, 189, 29, 137, 3, // Opcode: STRXui /* 75679 */ MCD_OPC_FilterValue, 1, 0, 44, 0, // Skip to: 86948 /* 75684 */ MCD_OPC_Decode, 166, 18, 137, 3, // Opcode: LDRXui /* 75689 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 75706 /* 75694 */ MCD_OPC_CheckField, 22, 1, 0, 239, 43, 0, // Skip to: 86948 /* 75701 */ MCD_OPC_Decode, 155, 21, 137, 3, // Opcode: PRFMui /* 75706 */ MCD_OPC_FilterValue, 4, 229, 43, 0, // Skip to: 86948 /* 75711 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 75714 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 75756 /* 75719 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 75722 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 75739 /* 75727 */ MCD_OPC_CheckField, 12, 4, 0, 206, 43, 0, // Skip to: 86948 /* 75734 */ MCD_OPC_Decode, 179, 22, 142, 3, // Opcode: SBCSXr /* 75739 */ MCD_OPC_FilterValue, 2, 196, 43, 0, // Skip to: 86948 /* 75744 */ MCD_OPC_CheckField, 4, 1, 0, 189, 43, 0, // Skip to: 86948 /* 75751 */ MCD_OPC_Decode, 131, 3, 149, 3, // Opcode: CCMPXr /* 75756 */ MCD_OPC_FilterValue, 2, 179, 43, 0, // Skip to: 86948 /* 75761 */ MCD_OPC_CheckField, 21, 2, 2, 172, 43, 0, // Skip to: 86948 /* 75768 */ MCD_OPC_CheckField, 4, 1, 0, 165, 43, 0, // Skip to: 86948 /* 75775 */ MCD_OPC_Decode, 130, 3, 150, 3, // Opcode: CCMPXi /* 75780 */ MCD_OPC_FilterValue, 7, 155, 43, 0, // Skip to: 86948 /* 75785 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... /* 75788 */ MCD_OPC_FilterValue, 0, 103, 10, 0, // Skip to: 78456 /* 75793 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 75796 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75806 /* 75801 */ MCD_OPC_Decode, 149, 18, 160, 3, // Opcode: LDRSl /* 75806 */ MCD_OPC_FilterValue, 2, 105, 9, 0, // Skip to: 78220 /* 75811 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 75814 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 75882 /* 75819 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... /* 75822 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75837 /* 75827 */ MCD_OPC_CheckPredicate, 16, 108, 43, 0, // Skip to: 86948 /* 75832 */ MCD_OPC_Decode, 186, 22, 161, 3, // Opcode: SCVTFSWSri /* 75837 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75852 /* 75842 */ MCD_OPC_CheckPredicate, 16, 93, 43, 0, // Skip to: 86948 /* 75847 */ MCD_OPC_Decode, 173, 31, 161, 3, // Opcode: UCVTFSWSri /* 75852 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 75867 /* 75857 */ MCD_OPC_CheckPredicate, 16, 78, 43, 0, // Skip to: 86948 /* 75862 */ MCD_OPC_Decode, 220, 8, 162, 3, // Opcode: FCVTZSSWSri /* 75867 */ MCD_OPC_FilterValue, 51, 68, 43, 0, // Skip to: 86948 /* 75872 */ MCD_OPC_CheckPredicate, 16, 63, 43, 0, // Skip to: 86948 /* 75877 */ MCD_OPC_Decode, 255, 8, 162, 3, // Opcode: FCVTZUSWSri /* 75882 */ MCD_OPC_FilterValue, 1, 222, 2, 0, // Skip to: 76621 /* 75887 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 75890 */ MCD_OPC_FilterValue, 0, 18, 2, 0, // Skip to: 76425 /* 75895 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 75898 */ MCD_OPC_FilterValue, 0, 244, 1, 0, // Skip to: 76403 /* 75903 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 75906 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 76124 /* 75911 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 75914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75929 /* 75919 */ MCD_OPC_CheckPredicate, 16, 16, 43, 0, // Skip to: 86948 /* 75924 */ MCD_OPC_Decode, 155, 8, 163, 3, // Opcode: FCVTNSUWSr /* 75929 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75944 /* 75934 */ MCD_OPC_CheckPredicate, 16, 1, 43, 0, // Skip to: 86948 /* 75939 */ MCD_OPC_Decode, 169, 8, 163, 3, // Opcode: FCVTNUUWSr /* 75944 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75959 /* 75949 */ MCD_OPC_CheckPredicate, 16, 242, 42, 0, // Skip to: 86948 /* 75954 */ MCD_OPC_Decode, 192, 22, 164, 3, // Opcode: SCVTFUWSri /* 75959 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75974 /* 75964 */ MCD_OPC_CheckPredicate, 16, 227, 42, 0, // Skip to: 86948 /* 75969 */ MCD_OPC_Decode, 179, 31, 164, 3, // Opcode: UCVTFUWSri /* 75974 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75989 /* 75979 */ MCD_OPC_CheckPredicate, 16, 212, 42, 0, // Skip to: 86948 /* 75984 */ MCD_OPC_Decode, 219, 7, 163, 3, // Opcode: FCVTASUWSr /* 75989 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76004 /* 75994 */ MCD_OPC_CheckPredicate, 16, 197, 42, 0, // Skip to: 86948 /* 75999 */ MCD_OPC_Decode, 233, 7, 163, 3, // Opcode: FCVTAUUWSr /* 76004 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76019 /* 76009 */ MCD_OPC_CheckPredicate, 16, 182, 42, 0, // Skip to: 86948 /* 76014 */ MCD_OPC_Decode, 226, 10, 163, 3, // Opcode: FMOVSWr /* 76019 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76034 /* 76024 */ MCD_OPC_CheckPredicate, 16, 167, 42, 0, // Skip to: 86948 /* 76029 */ MCD_OPC_Decode, 230, 10, 164, 3, // Opcode: FMOVWSr /* 76034 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76049 /* 76039 */ MCD_OPC_CheckPredicate, 16, 152, 42, 0, // Skip to: 86948 /* 76044 */ MCD_OPC_Decode, 187, 8, 163, 3, // Opcode: FCVTPSUWSr /* 76049 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 76064 /* 76054 */ MCD_OPC_CheckPredicate, 16, 137, 42, 0, // Skip to: 86948 /* 76059 */ MCD_OPC_Decode, 201, 8, 163, 3, // Opcode: FCVTPUUWSr /* 76064 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76079 /* 76069 */ MCD_OPC_CheckPredicate, 16, 122, 42, 0, // Skip to: 86948 /* 76074 */ MCD_OPC_Decode, 255, 7, 163, 3, // Opcode: FCVTMSUWSr /* 76079 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 76094 /* 76084 */ MCD_OPC_CheckPredicate, 16, 107, 42, 0, // Skip to: 86948 /* 76089 */ MCD_OPC_Decode, 141, 8, 163, 3, // Opcode: FCVTMUUWSr /* 76094 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 76109 /* 76099 */ MCD_OPC_CheckPredicate, 16, 92, 42, 0, // Skip to: 86948 /* 76104 */ MCD_OPC_Decode, 226, 8, 163, 3, // Opcode: FCVTZSUWSr /* 76109 */ MCD_OPC_FilterValue, 25, 82, 42, 0, // Skip to: 86948 /* 76114 */ MCD_OPC_CheckPredicate, 16, 77, 42, 0, // Skip to: 86948 /* 76119 */ MCD_OPC_Decode, 133, 9, 163, 3, // Opcode: FCVTZUUWSr /* 76124 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 76192 /* 76129 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 76132 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76147 /* 76137 */ MCD_OPC_CheckPredicate, 16, 54, 42, 0, // Skip to: 86948 /* 76142 */ MCD_OPC_Decode, 207, 7, 165, 3, // Opcode: FCMPSrr /* 76147 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76162 /* 76152 */ MCD_OPC_CheckPredicate, 16, 39, 42, 0, // Skip to: 86948 /* 76157 */ MCD_OPC_Decode, 206, 7, 166, 3, // Opcode: FCMPSri /* 76162 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76177 /* 76167 */ MCD_OPC_CheckPredicate, 16, 24, 42, 0, // Skip to: 86948 /* 76172 */ MCD_OPC_Decode, 203, 7, 165, 3, // Opcode: FCMPESrr /* 76177 */ MCD_OPC_FilterValue, 24, 14, 42, 0, // Skip to: 86948 /* 76182 */ MCD_OPC_CheckPredicate, 16, 9, 42, 0, // Skip to: 86948 /* 76187 */ MCD_OPC_Decode, 202, 7, 166, 3, // Opcode: FCMPESri /* 76192 */ MCD_OPC_FilterValue, 2, 93, 0, 0, // Skip to: 76290 /* 76197 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 76200 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76215 /* 76205 */ MCD_OPC_CheckPredicate, 16, 242, 41, 0, // Skip to: 86948 /* 76210 */ MCD_OPC_Decode, 228, 10, 167, 3, // Opcode: FMOVSr /* 76215 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76230 /* 76220 */ MCD_OPC_CheckPredicate, 16, 227, 41, 0, // Skip to: 86948 /* 76225 */ MCD_OPC_Decode, 166, 11, 167, 3, // Opcode: FNEGSr /* 76230 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76245 /* 76235 */ MCD_OPC_CheckPredicate, 16, 212, 41, 0, // Skip to: 86948 /* 76240 */ MCD_OPC_Decode, 131, 12, 167, 3, // Opcode: FRINTNSr /* 76245 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76260 /* 76250 */ MCD_OPC_CheckPredicate, 16, 197, 41, 0, // Skip to: 86948 /* 76255 */ MCD_OPC_Decode, 248, 11, 167, 3, // Opcode: FRINTMSr /* 76260 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76275 /* 76265 */ MCD_OPC_CheckPredicate, 16, 182, 41, 0, // Skip to: 86948 /* 76270 */ MCD_OPC_Decode, 226, 11, 167, 3, // Opcode: FRINTASr /* 76275 */ MCD_OPC_FilterValue, 7, 172, 41, 0, // Skip to: 86948 /* 76280 */ MCD_OPC_CheckPredicate, 16, 167, 41, 0, // Skip to: 86948 /* 76285 */ MCD_OPC_Decode, 153, 12, 167, 3, // Opcode: FRINTXSr /* 76290 */ MCD_OPC_FilterValue, 6, 157, 41, 0, // Skip to: 86948 /* 76295 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 76298 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76313 /* 76303 */ MCD_OPC_CheckPredicate, 16, 144, 41, 0, // Skip to: 86948 /* 76308 */ MCD_OPC_Decode, 141, 6, 167, 3, // Opcode: FABSSr /* 76313 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76328 /* 76318 */ MCD_OPC_CheckPredicate, 16, 129, 41, 0, // Skip to: 86948 /* 76323 */ MCD_OPC_Decode, 200, 12, 167, 3, // Opcode: FSQRTSr /* 76328 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76343 /* 76333 */ MCD_OPC_CheckPredicate, 16, 114, 41, 0, // Skip to: 86948 /* 76338 */ MCD_OPC_Decode, 246, 7, 168, 3, // Opcode: FCVTDSr /* 76343 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76358 /* 76348 */ MCD_OPC_CheckPredicate, 16, 99, 41, 0, // Skip to: 86948 /* 76353 */ MCD_OPC_Decode, 248, 7, 169, 3, // Opcode: FCVTHSr /* 76358 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76373 /* 76363 */ MCD_OPC_CheckPredicate, 16, 84, 41, 0, // Skip to: 86948 /* 76368 */ MCD_OPC_Decode, 142, 12, 167, 3, // Opcode: FRINTPSr /* 76373 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76388 /* 76378 */ MCD_OPC_CheckPredicate, 16, 69, 41, 0, // Skip to: 86948 /* 76383 */ MCD_OPC_Decode, 164, 12, 167, 3, // Opcode: FRINTZSr /* 76388 */ MCD_OPC_FilterValue, 7, 59, 41, 0, // Skip to: 86948 /* 76393 */ MCD_OPC_CheckPredicate, 16, 54, 41, 0, // Skip to: 86948 /* 76398 */ MCD_OPC_Decode, 237, 11, 167, 3, // Opcode: FRINTISr /* 76403 */ MCD_OPC_FilterValue, 1, 44, 41, 0, // Skip to: 86948 /* 76408 */ MCD_OPC_CheckPredicate, 16, 39, 41, 0, // Skip to: 86948 /* 76413 */ MCD_OPC_CheckField, 5, 5, 0, 32, 41, 0, // Skip to: 86948 /* 76420 */ MCD_OPC_Decode, 227, 10, 170, 3, // Opcode: FMOVSi /* 76425 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 76463 /* 76430 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 76433 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76448 /* 76438 */ MCD_OPC_CheckPredicate, 16, 9, 41, 0, // Skip to: 86948 /* 76443 */ MCD_OPC_Decode, 216, 6, 171, 3, // Opcode: FCCMPSrr /* 76448 */ MCD_OPC_FilterValue, 1, 255, 40, 0, // Skip to: 86948 /* 76453 */ MCD_OPC_CheckPredicate, 16, 250, 40, 0, // Skip to: 86948 /* 76458 */ MCD_OPC_Decode, 214, 6, 171, 3, // Opcode: FCCMPESrr /* 76463 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 76606 /* 76468 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 76471 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76486 /* 76476 */ MCD_OPC_CheckPredicate, 16, 227, 40, 0, // Skip to: 86948 /* 76481 */ MCD_OPC_Decode, 247, 10, 172, 3, // Opcode: FMULSrr /* 76486 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76501 /* 76491 */ MCD_OPC_CheckPredicate, 16, 212, 40, 0, // Skip to: 86948 /* 76496 */ MCD_OPC_Decode, 171, 9, 172, 3, // Opcode: FDIVSrr /* 76501 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76516 /* 76506 */ MCD_OPC_CheckPredicate, 16, 197, 40, 0, // Skip to: 86948 /* 76511 */ MCD_OPC_Decode, 185, 6, 172, 3, // Opcode: FADDSrr /* 76516 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76531 /* 76521 */ MCD_OPC_CheckPredicate, 16, 182, 40, 0, // Skip to: 86948 /* 76526 */ MCD_OPC_Decode, 217, 12, 172, 3, // Opcode: FSUBSrr /* 76531 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76546 /* 76536 */ MCD_OPC_CheckPredicate, 16, 167, 40, 0, // Skip to: 86948 /* 76541 */ MCD_OPC_Decode, 231, 9, 172, 3, // Opcode: FMAXSrr /* 76546 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76561 /* 76551 */ MCD_OPC_CheckPredicate, 16, 152, 40, 0, // Skip to: 86948 /* 76556 */ MCD_OPC_Decode, 159, 10, 172, 3, // Opcode: FMINSrr /* 76561 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76576 /* 76566 */ MCD_OPC_CheckPredicate, 16, 137, 40, 0, // Skip to: 86948 /* 76571 */ MCD_OPC_Decode, 205, 9, 172, 3, // Opcode: FMAXNMSrr /* 76576 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76591 /* 76581 */ MCD_OPC_CheckPredicate, 16, 122, 40, 0, // Skip to: 86948 /* 76586 */ MCD_OPC_Decode, 133, 10, 172, 3, // Opcode: FMINNMSrr /* 76591 */ MCD_OPC_FilterValue, 8, 112, 40, 0, // Skip to: 86948 /* 76596 */ MCD_OPC_CheckPredicate, 16, 107, 40, 0, // Skip to: 86948 /* 76601 */ MCD_OPC_Decode, 195, 11, 172, 3, // Opcode: FNMULSrr /* 76606 */ MCD_OPC_FilterValue, 3, 97, 40, 0, // Skip to: 86948 /* 76611 */ MCD_OPC_CheckPredicate, 16, 92, 40, 0, // Skip to: 86948 /* 76616 */ MCD_OPC_Decode, 216, 7, 173, 3, // Opcode: FCSELSrrr /* 76621 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 76689 /* 76626 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... /* 76629 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76644 /* 76634 */ MCD_OPC_CheckPredicate, 16, 69, 40, 0, // Skip to: 86948 /* 76639 */ MCD_OPC_Decode, 184, 22, 174, 3, // Opcode: SCVTFSWDri /* 76644 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76659 /* 76649 */ MCD_OPC_CheckPredicate, 16, 54, 40, 0, // Skip to: 86948 /* 76654 */ MCD_OPC_Decode, 171, 31, 174, 3, // Opcode: UCVTFSWDri /* 76659 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 76674 /* 76664 */ MCD_OPC_CheckPredicate, 16, 39, 40, 0, // Skip to: 86948 /* 76669 */ MCD_OPC_Decode, 218, 8, 175, 3, // Opcode: FCVTZSSWDri /* 76674 */ MCD_OPC_FilterValue, 51, 29, 40, 0, // Skip to: 86948 /* 76679 */ MCD_OPC_CheckPredicate, 16, 24, 40, 0, // Skip to: 86948 /* 76684 */ MCD_OPC_Decode, 253, 8, 175, 3, // Opcode: FCVTZUSWDri /* 76689 */ MCD_OPC_FilterValue, 3, 207, 2, 0, // Skip to: 77413 /* 76694 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 76697 */ MCD_OPC_FilterValue, 0, 3, 2, 0, // Skip to: 77217 /* 76702 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 76705 */ MCD_OPC_FilterValue, 0, 229, 1, 0, // Skip to: 77195 /* 76710 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 76713 */ MCD_OPC_FilterValue, 0, 198, 0, 0, // Skip to: 76916 /* 76718 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 76721 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76736 /* 76726 */ MCD_OPC_CheckPredicate, 16, 233, 39, 0, // Skip to: 86948 /* 76731 */ MCD_OPC_Decode, 153, 8, 176, 3, // Opcode: FCVTNSUWDr /* 76736 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76751 /* 76741 */ MCD_OPC_CheckPredicate, 16, 218, 39, 0, // Skip to: 86948 /* 76746 */ MCD_OPC_Decode, 167, 8, 176, 3, // Opcode: FCVTNUUWDr /* 76751 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76766 /* 76756 */ MCD_OPC_CheckPredicate, 16, 203, 39, 0, // Skip to: 86948 /* 76761 */ MCD_OPC_Decode, 190, 22, 240, 1, // Opcode: SCVTFUWDri /* 76766 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76781 /* 76771 */ MCD_OPC_CheckPredicate, 16, 188, 39, 0, // Skip to: 86948 /* 76776 */ MCD_OPC_Decode, 177, 31, 240, 1, // Opcode: UCVTFUWDri /* 76781 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76796 /* 76786 */ MCD_OPC_CheckPredicate, 16, 173, 39, 0, // Skip to: 86948 /* 76791 */ MCD_OPC_Decode, 217, 7, 176, 3, // Opcode: FCVTASUWDr /* 76796 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76811 /* 76801 */ MCD_OPC_CheckPredicate, 16, 158, 39, 0, // Skip to: 86948 /* 76806 */ MCD_OPC_Decode, 231, 7, 176, 3, // Opcode: FCVTAUUWDr /* 76811 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76826 /* 76816 */ MCD_OPC_CheckPredicate, 16, 143, 39, 0, // Skip to: 86948 /* 76821 */ MCD_OPC_Decode, 185, 8, 176, 3, // Opcode: FCVTPSUWDr /* 76826 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 76841 /* 76831 */ MCD_OPC_CheckPredicate, 16, 128, 39, 0, // Skip to: 86948 /* 76836 */ MCD_OPC_Decode, 199, 8, 176, 3, // Opcode: FCVTPUUWDr /* 76841 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76856 /* 76846 */ MCD_OPC_CheckPredicate, 16, 113, 39, 0, // Skip to: 86948 /* 76851 */ MCD_OPC_Decode, 253, 7, 176, 3, // Opcode: FCVTMSUWDr /* 76856 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 76871 /* 76861 */ MCD_OPC_CheckPredicate, 16, 98, 39, 0, // Skip to: 86948 /* 76866 */ MCD_OPC_Decode, 139, 8, 176, 3, // Opcode: FCVTMUUWDr /* 76871 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 76886 /* 76876 */ MCD_OPC_CheckPredicate, 16, 83, 39, 0, // Skip to: 86948 /* 76881 */ MCD_OPC_Decode, 224, 8, 176, 3, // Opcode: FCVTZSUWDr /* 76886 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 76901 /* 76891 */ MCD_OPC_CheckPredicate, 16, 68, 39, 0, // Skip to: 86948 /* 76896 */ MCD_OPC_Decode, 131, 9, 176, 3, // Opcode: FCVTZUUWDr /* 76901 */ MCD_OPC_FilterValue, 30, 58, 39, 0, // Skip to: 86948 /* 76906 */ MCD_OPC_CheckPredicate, 17, 53, 39, 0, // Skip to: 86948 /* 76911 */ MCD_OPC_Decode, 186, 9, 176, 3, // Opcode: FJCVTZS /* 76916 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 76984 /* 76921 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 76924 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76939 /* 76929 */ MCD_OPC_CheckPredicate, 16, 30, 39, 0, // Skip to: 86948 /* 76934 */ MCD_OPC_Decode, 197, 7, 177, 3, // Opcode: FCMPDrr /* 76939 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76954 /* 76944 */ MCD_OPC_CheckPredicate, 16, 15, 39, 0, // Skip to: 86948 /* 76949 */ MCD_OPC_Decode, 196, 7, 178, 3, // Opcode: FCMPDri /* 76954 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76969 /* 76959 */ MCD_OPC_CheckPredicate, 16, 0, 39, 0, // Skip to: 86948 /* 76964 */ MCD_OPC_Decode, 199, 7, 177, 3, // Opcode: FCMPEDrr /* 76969 */ MCD_OPC_FilterValue, 24, 246, 38, 0, // Skip to: 86948 /* 76974 */ MCD_OPC_CheckPredicate, 16, 241, 38, 0, // Skip to: 86948 /* 76979 */ MCD_OPC_Decode, 198, 7, 178, 3, // Opcode: FCMPEDri /* 76984 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 77097 /* 76989 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 76992 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77007 /* 76997 */ MCD_OPC_CheckPredicate, 16, 218, 38, 0, // Skip to: 86948 /* 77002 */ MCD_OPC_Decode, 219, 10, 239, 1, // Opcode: FMOVDr /* 77007 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77022 /* 77012 */ MCD_OPC_CheckPredicate, 16, 203, 38, 0, // Skip to: 86948 /* 77017 */ MCD_OPC_Decode, 164, 11, 239, 1, // Opcode: FNEGDr /* 77022 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77037 /* 77027 */ MCD_OPC_CheckPredicate, 16, 188, 38, 0, // Skip to: 86948 /* 77032 */ MCD_OPC_Decode, 213, 8, 166, 2, // Opcode: FCVTSDr /* 77037 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77052 /* 77042 */ MCD_OPC_CheckPredicate, 16, 173, 38, 0, // Skip to: 86948 /* 77047 */ MCD_OPC_Decode, 129, 12, 239, 1, // Opcode: FRINTNDr /* 77052 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77067 /* 77057 */ MCD_OPC_CheckPredicate, 16, 158, 38, 0, // Skip to: 86948 /* 77062 */ MCD_OPC_Decode, 246, 11, 239, 1, // Opcode: FRINTMDr /* 77067 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77082 /* 77072 */ MCD_OPC_CheckPredicate, 16, 143, 38, 0, // Skip to: 86948 /* 77077 */ MCD_OPC_Decode, 224, 11, 239, 1, // Opcode: FRINTADr /* 77082 */ MCD_OPC_FilterValue, 7, 133, 38, 0, // Skip to: 86948 /* 77087 */ MCD_OPC_CheckPredicate, 16, 128, 38, 0, // Skip to: 86948 /* 77092 */ MCD_OPC_Decode, 151, 12, 239, 1, // Opcode: FRINTXDr /* 77097 */ MCD_OPC_FilterValue, 6, 118, 38, 0, // Skip to: 86948 /* 77102 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 77105 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77120 /* 77110 */ MCD_OPC_CheckPredicate, 16, 105, 38, 0, // Skip to: 86948 /* 77115 */ MCD_OPC_Decode, 139, 6, 239, 1, // Opcode: FABSDr /* 77120 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77135 /* 77125 */ MCD_OPC_CheckPredicate, 16, 90, 38, 0, // Skip to: 86948 /* 77130 */ MCD_OPC_Decode, 198, 12, 239, 1, // Opcode: FSQRTDr /* 77135 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77150 /* 77140 */ MCD_OPC_CheckPredicate, 16, 75, 38, 0, // Skip to: 86948 /* 77145 */ MCD_OPC_Decode, 247, 7, 249, 1, // Opcode: FCVTHDr /* 77150 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77165 /* 77155 */ MCD_OPC_CheckPredicate, 16, 60, 38, 0, // Skip to: 86948 /* 77160 */ MCD_OPC_Decode, 140, 12, 239, 1, // Opcode: FRINTPDr /* 77165 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77180 /* 77170 */ MCD_OPC_CheckPredicate, 16, 45, 38, 0, // Skip to: 86948 /* 77175 */ MCD_OPC_Decode, 162, 12, 239, 1, // Opcode: FRINTZDr /* 77180 */ MCD_OPC_FilterValue, 7, 35, 38, 0, // Skip to: 86948 /* 77185 */ MCD_OPC_CheckPredicate, 16, 30, 38, 0, // Skip to: 86948 /* 77190 */ MCD_OPC_Decode, 235, 11, 239, 1, // Opcode: FRINTIDr /* 77195 */ MCD_OPC_FilterValue, 1, 20, 38, 0, // Skip to: 86948 /* 77200 */ MCD_OPC_CheckPredicate, 16, 15, 38, 0, // Skip to: 86948 /* 77205 */ MCD_OPC_CheckField, 5, 5, 0, 8, 38, 0, // Skip to: 86948 /* 77212 */ MCD_OPC_Decode, 218, 10, 179, 3, // Opcode: FMOVDi /* 77217 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 77255 /* 77222 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 77225 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77240 /* 77230 */ MCD_OPC_CheckPredicate, 16, 241, 37, 0, // Skip to: 86948 /* 77235 */ MCD_OPC_Decode, 211, 6, 180, 3, // Opcode: FCCMPDrr /* 77240 */ MCD_OPC_FilterValue, 1, 231, 37, 0, // Skip to: 86948 /* 77245 */ MCD_OPC_CheckPredicate, 16, 226, 37, 0, // Skip to: 86948 /* 77250 */ MCD_OPC_Decode, 212, 6, 180, 3, // Opcode: FCCMPEDrr /* 77255 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 77398 /* 77260 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 77263 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77278 /* 77268 */ MCD_OPC_CheckPredicate, 16, 203, 37, 0, // Skip to: 86948 /* 77273 */ MCD_OPC_Decode, 245, 10, 238, 1, // Opcode: FMULDrr /* 77278 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77293 /* 77283 */ MCD_OPC_CheckPredicate, 16, 188, 37, 0, // Skip to: 86948 /* 77288 */ MCD_OPC_Decode, 166, 9, 238, 1, // Opcode: FDIVDrr /* 77293 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77308 /* 77298 */ MCD_OPC_CheckPredicate, 16, 173, 37, 0, // Skip to: 86948 /* 77303 */ MCD_OPC_Decode, 175, 6, 238, 1, // Opcode: FADDDrr /* 77308 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77323 /* 77313 */ MCD_OPC_CheckPredicate, 16, 158, 37, 0, // Skip to: 86948 /* 77318 */ MCD_OPC_Decode, 209, 12, 238, 1, // Opcode: FSUBDrr /* 77323 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77338 /* 77328 */ MCD_OPC_CheckPredicate, 16, 143, 37, 0, // Skip to: 86948 /* 77333 */ MCD_OPC_Decode, 193, 9, 238, 1, // Opcode: FMAXDrr /* 77338 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77353 /* 77343 */ MCD_OPC_CheckPredicate, 16, 128, 37, 0, // Skip to: 86948 /* 77348 */ MCD_OPC_Decode, 249, 9, 238, 1, // Opcode: FMINDrr /* 77353 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77368 /* 77358 */ MCD_OPC_CheckPredicate, 16, 113, 37, 0, // Skip to: 86948 /* 77363 */ MCD_OPC_Decode, 195, 9, 238, 1, // Opcode: FMAXNMDrr /* 77368 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77383 /* 77373 */ MCD_OPC_CheckPredicate, 16, 98, 37, 0, // Skip to: 86948 /* 77378 */ MCD_OPC_Decode, 251, 9, 238, 1, // Opcode: FMINNMDrr /* 77383 */ MCD_OPC_FilterValue, 8, 88, 37, 0, // Skip to: 86948 /* 77388 */ MCD_OPC_CheckPredicate, 16, 83, 37, 0, // Skip to: 86948 /* 77393 */ MCD_OPC_Decode, 193, 11, 238, 1, // Opcode: FNMULDrr /* 77398 */ MCD_OPC_FilterValue, 3, 73, 37, 0, // Skip to: 86948 /* 77403 */ MCD_OPC_CheckPredicate, 16, 68, 37, 0, // Skip to: 86948 /* 77408 */ MCD_OPC_Decode, 214, 7, 181, 3, // Opcode: FCSELDrrr /* 77413 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 77481 /* 77418 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... /* 77421 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77436 /* 77426 */ MCD_OPC_CheckPredicate, 18, 45, 37, 0, // Skip to: 86948 /* 77431 */ MCD_OPC_Decode, 185, 22, 182, 3, // Opcode: SCVTFSWHri /* 77436 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77451 /* 77441 */ MCD_OPC_CheckPredicate, 18, 30, 37, 0, // Skip to: 86948 /* 77446 */ MCD_OPC_Decode, 172, 31, 182, 3, // Opcode: UCVTFSWHri /* 77451 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 77466 /* 77456 */ MCD_OPC_CheckPredicate, 18, 15, 37, 0, // Skip to: 86948 /* 77461 */ MCD_OPC_Decode, 219, 8, 183, 3, // Opcode: FCVTZSSWHri /* 77466 */ MCD_OPC_FilterValue, 51, 5, 37, 0, // Skip to: 86948 /* 77471 */ MCD_OPC_CheckPredicate, 18, 0, 37, 0, // Skip to: 86948 /* 77476 */ MCD_OPC_Decode, 254, 8, 183, 3, // Opcode: FCVTZUSWHri /* 77481 */ MCD_OPC_FilterValue, 7, 246, 36, 0, // Skip to: 86948 /* 77486 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 77489 */ MCD_OPC_FilterValue, 0, 18, 2, 0, // Skip to: 78024 /* 77494 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 77497 */ MCD_OPC_FilterValue, 0, 244, 1, 0, // Skip to: 78002 /* 77502 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 77505 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 77723 /* 77510 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 77513 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77528 /* 77518 */ MCD_OPC_CheckPredicate, 18, 209, 36, 0, // Skip to: 86948 /* 77523 */ MCD_OPC_Decode, 154, 8, 184, 3, // Opcode: FCVTNSUWHr /* 77528 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77543 /* 77533 */ MCD_OPC_CheckPredicate, 18, 194, 36, 0, // Skip to: 86948 /* 77538 */ MCD_OPC_Decode, 168, 8, 184, 3, // Opcode: FCVTNUUWHr /* 77543 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77558 /* 77548 */ MCD_OPC_CheckPredicate, 18, 179, 36, 0, // Skip to: 86948 /* 77553 */ MCD_OPC_Decode, 191, 22, 185, 3, // Opcode: SCVTFUWHri /* 77558 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77573 /* 77563 */ MCD_OPC_CheckPredicate, 18, 164, 36, 0, // Skip to: 86948 /* 77568 */ MCD_OPC_Decode, 178, 31, 185, 3, // Opcode: UCVTFUWHri /* 77573 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77588 /* 77578 */ MCD_OPC_CheckPredicate, 18, 149, 36, 0, // Skip to: 86948 /* 77583 */ MCD_OPC_Decode, 218, 7, 184, 3, // Opcode: FCVTASUWHr /* 77588 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77603 /* 77593 */ MCD_OPC_CheckPredicate, 18, 134, 36, 0, // Skip to: 86948 /* 77598 */ MCD_OPC_Decode, 232, 7, 184, 3, // Opcode: FCVTAUUWHr /* 77603 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77618 /* 77608 */ MCD_OPC_CheckPredicate, 18, 119, 36, 0, // Skip to: 86948 /* 77613 */ MCD_OPC_Decode, 221, 10, 184, 3, // Opcode: FMOVHWr /* 77618 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77633 /* 77623 */ MCD_OPC_CheckPredicate, 18, 104, 36, 0, // Skip to: 86948 /* 77628 */ MCD_OPC_Decode, 229, 10, 185, 3, // Opcode: FMOVWHr /* 77633 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 77648 /* 77638 */ MCD_OPC_CheckPredicate, 18, 89, 36, 0, // Skip to: 86948 /* 77643 */ MCD_OPC_Decode, 186, 8, 184, 3, // Opcode: FCVTPSUWHr /* 77648 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 77663 /* 77653 */ MCD_OPC_CheckPredicate, 18, 74, 36, 0, // Skip to: 86948 /* 77658 */ MCD_OPC_Decode, 200, 8, 184, 3, // Opcode: FCVTPUUWHr /* 77663 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 77678 /* 77668 */ MCD_OPC_CheckPredicate, 18, 59, 36, 0, // Skip to: 86948 /* 77673 */ MCD_OPC_Decode, 254, 7, 184, 3, // Opcode: FCVTMSUWHr /* 77678 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 77693 /* 77683 */ MCD_OPC_CheckPredicate, 18, 44, 36, 0, // Skip to: 86948 /* 77688 */ MCD_OPC_Decode, 140, 8, 184, 3, // Opcode: FCVTMUUWHr /* 77693 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 77708 /* 77698 */ MCD_OPC_CheckPredicate, 18, 29, 36, 0, // Skip to: 86948 /* 77703 */ MCD_OPC_Decode, 225, 8, 184, 3, // Opcode: FCVTZSUWHr /* 77708 */ MCD_OPC_FilterValue, 25, 19, 36, 0, // Skip to: 86948 /* 77713 */ MCD_OPC_CheckPredicate, 18, 14, 36, 0, // Skip to: 86948 /* 77718 */ MCD_OPC_Decode, 132, 9, 184, 3, // Opcode: FCVTZUUWHr /* 77723 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 77791 /* 77728 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... /* 77731 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77746 /* 77736 */ MCD_OPC_CheckPredicate, 18, 247, 35, 0, // Skip to: 86948 /* 77741 */ MCD_OPC_Decode, 205, 7, 186, 3, // Opcode: FCMPHrr /* 77746 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 77761 /* 77751 */ MCD_OPC_CheckPredicate, 18, 232, 35, 0, // Skip to: 86948 /* 77756 */ MCD_OPC_Decode, 204, 7, 187, 3, // Opcode: FCMPHri /* 77761 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 77776 /* 77766 */ MCD_OPC_CheckPredicate, 18, 217, 35, 0, // Skip to: 86948 /* 77771 */ MCD_OPC_Decode, 201, 7, 186, 3, // Opcode: FCMPEHrr /* 77776 */ MCD_OPC_FilterValue, 24, 207, 35, 0, // Skip to: 86948 /* 77781 */ MCD_OPC_CheckPredicate, 18, 202, 35, 0, // Skip to: 86948 /* 77786 */ MCD_OPC_Decode, 200, 7, 187, 3, // Opcode: FCMPEHri /* 77791 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 77904 /* 77796 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 77799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77814 /* 77804 */ MCD_OPC_CheckPredicate, 18, 179, 35, 0, // Skip to: 86948 /* 77809 */ MCD_OPC_Decode, 224, 10, 188, 3, // Opcode: FMOVHr /* 77814 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77829 /* 77819 */ MCD_OPC_CheckPredicate, 18, 164, 35, 0, // Skip to: 86948 /* 77824 */ MCD_OPC_Decode, 165, 11, 188, 3, // Opcode: FNEGHr /* 77829 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77844 /* 77834 */ MCD_OPC_CheckPredicate, 16, 149, 35, 0, // Skip to: 86948 /* 77839 */ MCD_OPC_Decode, 214, 8, 189, 3, // Opcode: FCVTSHr /* 77844 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77859 /* 77849 */ MCD_OPC_CheckPredicate, 18, 134, 35, 0, // Skip to: 86948 /* 77854 */ MCD_OPC_Decode, 130, 12, 188, 3, // Opcode: FRINTNHr /* 77859 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77874 /* 77864 */ MCD_OPC_CheckPredicate, 18, 119, 35, 0, // Skip to: 86948 /* 77869 */ MCD_OPC_Decode, 247, 11, 188, 3, // Opcode: FRINTMHr /* 77874 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77889 /* 77879 */ MCD_OPC_CheckPredicate, 18, 104, 35, 0, // Skip to: 86948 /* 77884 */ MCD_OPC_Decode, 225, 11, 188, 3, // Opcode: FRINTAHr /* 77889 */ MCD_OPC_FilterValue, 7, 94, 35, 0, // Skip to: 86948 /* 77894 */ MCD_OPC_CheckPredicate, 18, 89, 35, 0, // Skip to: 86948 /* 77899 */ MCD_OPC_Decode, 152, 12, 188, 3, // Opcode: FRINTXHr /* 77904 */ MCD_OPC_FilterValue, 6, 79, 35, 0, // Skip to: 86948 /* 77909 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 77912 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77927 /* 77917 */ MCD_OPC_CheckPredicate, 18, 66, 35, 0, // Skip to: 86948 /* 77922 */ MCD_OPC_Decode, 140, 6, 188, 3, // Opcode: FABSHr /* 77927 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77942 /* 77932 */ MCD_OPC_CheckPredicate, 18, 51, 35, 0, // Skip to: 86948 /* 77937 */ MCD_OPC_Decode, 199, 12, 188, 3, // Opcode: FSQRTHr /* 77942 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77957 /* 77947 */ MCD_OPC_CheckPredicate, 16, 36, 35, 0, // Skip to: 86948 /* 77952 */ MCD_OPC_Decode, 245, 7, 190, 3, // Opcode: FCVTDHr /* 77957 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77972 /* 77962 */ MCD_OPC_CheckPredicate, 18, 21, 35, 0, // Skip to: 86948 /* 77967 */ MCD_OPC_Decode, 141, 12, 188, 3, // Opcode: FRINTPHr /* 77972 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77987 /* 77977 */ MCD_OPC_CheckPredicate, 18, 6, 35, 0, // Skip to: 86948 /* 77982 */ MCD_OPC_Decode, 163, 12, 188, 3, // Opcode: FRINTZHr /* 77987 */ MCD_OPC_FilterValue, 7, 252, 34, 0, // Skip to: 86948 /* 77992 */ MCD_OPC_CheckPredicate, 18, 247, 34, 0, // Skip to: 86948 /* 77997 */ MCD_OPC_Decode, 236, 11, 188, 3, // Opcode: FRINTIHr /* 78002 */ MCD_OPC_FilterValue, 1, 237, 34, 0, // Skip to: 86948 /* 78007 */ MCD_OPC_CheckPredicate, 18, 232, 34, 0, // Skip to: 86948 /* 78012 */ MCD_OPC_CheckField, 5, 5, 0, 225, 34, 0, // Skip to: 86948 /* 78019 */ MCD_OPC_Decode, 223, 10, 191, 3, // Opcode: FMOVHi /* 78024 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 78062 /* 78029 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 78032 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78047 /* 78037 */ MCD_OPC_CheckPredicate, 18, 202, 34, 0, // Skip to: 86948 /* 78042 */ MCD_OPC_Decode, 215, 6, 192, 3, // Opcode: FCCMPHrr /* 78047 */ MCD_OPC_FilterValue, 1, 192, 34, 0, // Skip to: 86948 /* 78052 */ MCD_OPC_CheckPredicate, 18, 187, 34, 0, // Skip to: 86948 /* 78057 */ MCD_OPC_Decode, 213, 6, 192, 3, // Opcode: FCCMPEHrr /* 78062 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 78205 /* 78067 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 78070 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78085 /* 78075 */ MCD_OPC_CheckPredicate, 18, 164, 34, 0, // Skip to: 86948 /* 78080 */ MCD_OPC_Decode, 246, 10, 193, 3, // Opcode: FMULHrr /* 78085 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 78100 /* 78090 */ MCD_OPC_CheckPredicate, 18, 149, 34, 0, // Skip to: 86948 /* 78095 */ MCD_OPC_Decode, 167, 9, 193, 3, // Opcode: FDIVHrr /* 78100 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 78115 /* 78105 */ MCD_OPC_CheckPredicate, 18, 134, 34, 0, // Skip to: 86948 /* 78110 */ MCD_OPC_Decode, 176, 6, 193, 3, // Opcode: FADDHrr /* 78115 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 78130 /* 78120 */ MCD_OPC_CheckPredicate, 18, 119, 34, 0, // Skip to: 86948 /* 78125 */ MCD_OPC_Decode, 210, 12, 193, 3, // Opcode: FSUBHrr /* 78130 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 78145 /* 78135 */ MCD_OPC_CheckPredicate, 18, 104, 34, 0, // Skip to: 86948 /* 78140 */ MCD_OPC_Decode, 194, 9, 193, 3, // Opcode: FMAXHrr /* 78145 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 78160 /* 78150 */ MCD_OPC_CheckPredicate, 18, 89, 34, 0, // Skip to: 86948 /* 78155 */ MCD_OPC_Decode, 250, 9, 193, 3, // Opcode: FMINHrr /* 78160 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 78175 /* 78165 */ MCD_OPC_CheckPredicate, 18, 74, 34, 0, // Skip to: 86948 /* 78170 */ MCD_OPC_Decode, 196, 9, 193, 3, // Opcode: FMAXNMHrr /* 78175 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 78190 /* 78180 */ MCD_OPC_CheckPredicate, 18, 59, 34, 0, // Skip to: 86948 /* 78185 */ MCD_OPC_Decode, 252, 9, 193, 3, // Opcode: FMINNMHrr /* 78190 */ MCD_OPC_FilterValue, 8, 49, 34, 0, // Skip to: 86948 /* 78195 */ MCD_OPC_CheckPredicate, 18, 44, 34, 0, // Skip to: 86948 /* 78200 */ MCD_OPC_Decode, 194, 11, 193, 3, // Opcode: FNMULHrr /* 78205 */ MCD_OPC_FilterValue, 3, 34, 34, 0, // Skip to: 86948 /* 78210 */ MCD_OPC_CheckPredicate, 18, 29, 34, 0, // Skip to: 86948 /* 78215 */ MCD_OPC_Decode, 215, 7, 194, 3, // Opcode: FCSELHrrr /* 78220 */ MCD_OPC_FilterValue, 3, 19, 34, 0, // Skip to: 86948 /* 78225 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 78228 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 78266 /* 78233 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 78236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78251 /* 78241 */ MCD_OPC_CheckPredicate, 16, 254, 33, 0, // Skip to: 86948 /* 78246 */ MCD_OPC_Decode, 189, 9, 195, 3, // Opcode: FMADDSrrr /* 78251 */ MCD_OPC_FilterValue, 1, 244, 33, 0, // Skip to: 86948 /* 78256 */ MCD_OPC_CheckPredicate, 16, 239, 33, 0, // Skip to: 86948 /* 78261 */ MCD_OPC_Decode, 244, 10, 195, 3, // Opcode: FMSUBSrrr /* 78266 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 78304 /* 78271 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 78274 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78289 /* 78279 */ MCD_OPC_CheckPredicate, 16, 216, 33, 0, // Skip to: 86948 /* 78284 */ MCD_OPC_Decode, 177, 11, 195, 3, // Opcode: FNMADDSrrr /* 78289 */ MCD_OPC_FilterValue, 1, 206, 33, 0, // Skip to: 86948 /* 78294 */ MCD_OPC_CheckPredicate, 16, 201, 33, 0, // Skip to: 86948 /* 78299 */ MCD_OPC_Decode, 192, 11, 195, 3, // Opcode: FNMSUBSrrr /* 78304 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 78342 /* 78309 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 78312 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78327 /* 78317 */ MCD_OPC_CheckPredicate, 16, 178, 33, 0, // Skip to: 86948 /* 78322 */ MCD_OPC_Decode, 187, 9, 196, 3, // Opcode: FMADDDrrr /* 78327 */ MCD_OPC_FilterValue, 1, 168, 33, 0, // Skip to: 86948 /* 78332 */ MCD_OPC_CheckPredicate, 16, 163, 33, 0, // Skip to: 86948 /* 78337 */ MCD_OPC_Decode, 242, 10, 196, 3, // Opcode: FMSUBDrrr /* 78342 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 78380 /* 78347 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 78350 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78365 /* 78355 */ MCD_OPC_CheckPredicate, 16, 140, 33, 0, // Skip to: 86948 /* 78360 */ MCD_OPC_Decode, 175, 11, 196, 3, // Opcode: FNMADDDrrr /* 78365 */ MCD_OPC_FilterValue, 1, 130, 33, 0, // Skip to: 86948 /* 78370 */ MCD_OPC_CheckPredicate, 16, 125, 33, 0, // Skip to: 86948 /* 78375 */ MCD_OPC_Decode, 190, 11, 196, 3, // Opcode: FNMSUBDrrr /* 78380 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 78418 /* 78385 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 78388 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78403 /* 78393 */ MCD_OPC_CheckPredicate, 18, 102, 33, 0, // Skip to: 86948 /* 78398 */ MCD_OPC_Decode, 188, 9, 197, 3, // Opcode: FMADDHrrr /* 78403 */ MCD_OPC_FilterValue, 1, 92, 33, 0, // Skip to: 86948 /* 78408 */ MCD_OPC_CheckPredicate, 18, 87, 33, 0, // Skip to: 86948 /* 78413 */ MCD_OPC_Decode, 243, 10, 197, 3, // Opcode: FMSUBHrrr /* 78418 */ MCD_OPC_FilterValue, 7, 77, 33, 0, // Skip to: 86948 /* 78423 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 78426 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78441 /* 78431 */ MCD_OPC_CheckPredicate, 18, 64, 33, 0, // Skip to: 86948 /* 78436 */ MCD_OPC_Decode, 176, 11, 197, 3, // Opcode: FNMADDHrrr /* 78441 */ MCD_OPC_FilterValue, 1, 54, 33, 0, // Skip to: 86948 /* 78446 */ MCD_OPC_CheckPredicate, 18, 49, 33, 0, // Skip to: 86948 /* 78451 */ MCD_OPC_Decode, 191, 11, 197, 3, // Opcode: FNMSUBHrrr /* 78456 */ MCD_OPC_FilterValue, 1, 191, 1, 0, // Skip to: 78908 /* 78461 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 78464 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 78565 /* 78469 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 78472 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78489 /* 78477 */ MCD_OPC_CheckField, 21, 1, 0, 16, 33, 0, // Skip to: 86948 /* 78484 */ MCD_OPC_Decode, 197, 29, 255, 2, // Opcode: STURBi /* 78489 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78506 /* 78494 */ MCD_OPC_CheckField, 21, 1, 0, 255, 32, 0, // Skip to: 86948 /* 78501 */ MCD_OPC_Decode, 150, 29, 255, 2, // Opcode: STRBpost /* 78506 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78548 /* 78511 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 78514 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78531 /* 78519 */ MCD_OPC_CheckField, 21, 1, 1, 230, 32, 0, // Skip to: 86948 /* 78526 */ MCD_OPC_Decode, 152, 29, 198, 3, // Opcode: STRBroW /* 78531 */ MCD_OPC_FilterValue, 3, 220, 32, 0, // Skip to: 86948 /* 78536 */ MCD_OPC_CheckField, 21, 1, 1, 213, 32, 0, // Skip to: 86948 /* 78543 */ MCD_OPC_Decode, 153, 29, 199, 3, // Opcode: STRBroX /* 78548 */ MCD_OPC_FilterValue, 3, 203, 32, 0, // Skip to: 86948 /* 78553 */ MCD_OPC_CheckField, 21, 1, 0, 196, 32, 0, // Skip to: 86948 /* 78560 */ MCD_OPC_Decode, 151, 29, 255, 2, // Opcode: STRBpre /* 78565 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 78666 /* 78570 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 78573 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78590 /* 78578 */ MCD_OPC_CheckField, 21, 1, 0, 171, 32, 0, // Skip to: 86948 /* 78585 */ MCD_OPC_Decode, 131, 19, 255, 2, // Opcode: LDURBi /* 78590 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78607 /* 78595 */ MCD_OPC_CheckField, 21, 1, 0, 154, 32, 0, // Skip to: 86948 /* 78602 */ MCD_OPC_Decode, 224, 17, 255, 2, // Opcode: LDRBpost /* 78607 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78649 /* 78612 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 78615 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78632 /* 78620 */ MCD_OPC_CheckField, 21, 1, 1, 129, 32, 0, // Skip to: 86948 /* 78627 */ MCD_OPC_Decode, 226, 17, 198, 3, // Opcode: LDRBroW /* 78632 */ MCD_OPC_FilterValue, 3, 119, 32, 0, // Skip to: 86948 /* 78637 */ MCD_OPC_CheckField, 21, 1, 1, 112, 32, 0, // Skip to: 86948 /* 78644 */ MCD_OPC_Decode, 227, 17, 199, 3, // Opcode: LDRBroX /* 78649 */ MCD_OPC_FilterValue, 3, 102, 32, 0, // Skip to: 86948 /* 78654 */ MCD_OPC_CheckField, 21, 1, 0, 95, 32, 0, // Skip to: 86948 /* 78661 */ MCD_OPC_Decode, 225, 17, 255, 2, // Opcode: LDRBpre /* 78666 */ MCD_OPC_FilterValue, 2, 96, 0, 0, // Skip to: 78767 /* 78671 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 78674 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78691 /* 78679 */ MCD_OPC_CheckField, 21, 1, 0, 70, 32, 0, // Skip to: 86948 /* 78686 */ MCD_OPC_Decode, 201, 29, 255, 2, // Opcode: STURQi /* 78691 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78708 /* 78696 */ MCD_OPC_CheckField, 21, 1, 0, 53, 32, 0, // Skip to: 86948 /* 78703 */ MCD_OPC_Decode, 170, 29, 255, 2, // Opcode: STRQpost /* 78708 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78750 /* 78713 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 78716 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78733 /* 78721 */ MCD_OPC_CheckField, 21, 1, 1, 28, 32, 0, // Skip to: 86948 /* 78728 */ MCD_OPC_Decode, 172, 29, 200, 3, // Opcode: STRQroW /* 78733 */ MCD_OPC_FilterValue, 3, 18, 32, 0, // Skip to: 86948 /* 78738 */ MCD_OPC_CheckField, 21, 1, 1, 11, 32, 0, // Skip to: 86948 /* 78745 */ MCD_OPC_Decode, 173, 29, 201, 3, // Opcode: STRQroX /* 78750 */ MCD_OPC_FilterValue, 3, 1, 32, 0, // Skip to: 86948 /* 78755 */ MCD_OPC_CheckField, 21, 1, 0, 250, 31, 0, // Skip to: 86948 /* 78762 */ MCD_OPC_Decode, 171, 29, 255, 2, // Opcode: STRQpre /* 78767 */ MCD_OPC_FilterValue, 3, 96, 0, 0, // Skip to: 78868 /* 78772 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 78775 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78792 /* 78780 */ MCD_OPC_CheckField, 21, 1, 0, 225, 31, 0, // Skip to: 86948 /* 78787 */ MCD_OPC_Decode, 135, 19, 255, 2, // Opcode: LDURQi /* 78792 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78809 /* 78797 */ MCD_OPC_CheckField, 21, 1, 0, 208, 31, 0, // Skip to: 86948 /* 78804 */ MCD_OPC_Decode, 246, 17, 255, 2, // Opcode: LDRQpost /* 78809 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78851 /* 78814 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 78817 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78834 /* 78822 */ MCD_OPC_CheckField, 21, 1, 1, 183, 31, 0, // Skip to: 86948 /* 78829 */ MCD_OPC_Decode, 248, 17, 200, 3, // Opcode: LDRQroW /* 78834 */ MCD_OPC_FilterValue, 3, 173, 31, 0, // Skip to: 86948 /* 78839 */ MCD_OPC_CheckField, 21, 1, 1, 166, 31, 0, // Skip to: 86948 /* 78846 */ MCD_OPC_Decode, 249, 17, 201, 3, // Opcode: LDRQroX /* 78851 */ MCD_OPC_FilterValue, 3, 156, 31, 0, // Skip to: 86948 /* 78856 */ MCD_OPC_CheckField, 21, 1, 0, 149, 31, 0, // Skip to: 86948 /* 78863 */ MCD_OPC_Decode, 247, 17, 255, 2, // Opcode: LDRQpre /* 78868 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 78878 /* 78873 */ MCD_OPC_Decode, 154, 29, 137, 3, // Opcode: STRBui /* 78878 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 78888 /* 78883 */ MCD_OPC_Decode, 228, 17, 137, 3, // Opcode: LDRBui /* 78888 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 78898 /* 78893 */ MCD_OPC_Decode, 174, 29, 137, 3, // Opcode: STRQui /* 78898 */ MCD_OPC_FilterValue, 7, 109, 31, 0, // Skip to: 86948 /* 78903 */ MCD_OPC_Decode, 250, 17, 137, 3, // Opcode: LDRQui /* 78908 */ MCD_OPC_FilterValue, 2, 63, 12, 0, // Skip to: 82048 /* 78913 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 78916 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 78926 /* 78921 */ MCD_OPC_Decode, 229, 17, 202, 3, // Opcode: LDRDl /* 78926 */ MCD_OPC_FilterValue, 2, 254, 7, 0, // Skip to: 80977 /* 78931 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 78934 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 78956 /* 78939 */ MCD_OPC_CheckPredicate, 19, 68, 31, 0, // Skip to: 86948 /* 78944 */ MCD_OPC_CheckField, 21, 3, 0, 61, 31, 0, // Skip to: 86948 /* 78951 */ MCD_OPC_Decode, 241, 22, 203, 3, // Opcode: SHA1Crrr /* 78956 */ MCD_OPC_FilterValue, 1, 114, 0, 0, // Skip to: 79075 /* 78961 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 78964 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 79053 /* 78969 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 78972 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 79031 /* 78977 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 78980 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 79009 /* 78985 */ MCD_OPC_CheckPredicate, 3, 22, 31, 0, // Skip to: 86948 /* 78990 */ MCD_OPC_CheckField, 21, 3, 0, 15, 31, 0, // Skip to: 86948 /* 78997 */ MCD_OPC_CheckField, 19, 1, 1, 8, 31, 0, // Skip to: 86948 /* 79004 */ MCD_OPC_Decode, 151, 5, 204, 3, // Opcode: CPYi64 /* 79009 */ MCD_OPC_FilterValue, 1, 254, 30, 0, // Skip to: 86948 /* 79014 */ MCD_OPC_CheckPredicate, 3, 249, 30, 0, // Skip to: 86948 /* 79019 */ MCD_OPC_CheckField, 21, 3, 0, 242, 30, 0, // Skip to: 86948 /* 79026 */ MCD_OPC_Decode, 150, 5, 205, 3, // Opcode: CPYi32 /* 79031 */ MCD_OPC_FilterValue, 1, 232, 30, 0, // Skip to: 86948 /* 79036 */ MCD_OPC_CheckPredicate, 3, 227, 30, 0, // Skip to: 86948 /* 79041 */ MCD_OPC_CheckField, 21, 3, 0, 220, 30, 0, // Skip to: 86948 /* 79048 */ MCD_OPC_Decode, 149, 5, 206, 3, // Opcode: CPYi16 /* 79053 */ MCD_OPC_FilterValue, 1, 210, 30, 0, // Skip to: 86948 /* 79058 */ MCD_OPC_CheckPredicate, 3, 205, 30, 0, // Skip to: 86948 /* 79063 */ MCD_OPC_CheckField, 21, 3, 0, 198, 30, 0, // Skip to: 86948 /* 79070 */ MCD_OPC_Decode, 152, 5, 207, 3, // Opcode: CPYi8 /* 79075 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 79097 /* 79080 */ MCD_OPC_CheckPredicate, 19, 183, 30, 0, // Skip to: 86948 /* 79085 */ MCD_OPC_CheckField, 16, 8, 40, 176, 30, 0, // Skip to: 86948 /* 79092 */ MCD_OPC_Decode, 242, 22, 167, 3, // Opcode: SHA1Hrr /* 79097 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 79165 /* 79102 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 79105 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79120 /* 79110 */ MCD_OPC_CheckPredicate, 3, 153, 30, 0, // Skip to: 86948 /* 79115 */ MCD_OPC_Decode, 176, 24, 208, 3, // Opcode: SQADDv1i8 /* 79120 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79135 /* 79125 */ MCD_OPC_CheckPredicate, 3, 138, 30, 0, // Skip to: 86948 /* 79130 */ MCD_OPC_Decode, 173, 24, 193, 3, // Opcode: SQADDv1i16 /* 79135 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79150 /* 79140 */ MCD_OPC_CheckPredicate, 3, 123, 30, 0, // Skip to: 86948 /* 79145 */ MCD_OPC_Decode, 174, 24, 172, 3, // Opcode: SQADDv1i32 /* 79150 */ MCD_OPC_FilterValue, 7, 113, 30, 0, // Skip to: 86948 /* 79155 */ MCD_OPC_CheckPredicate, 3, 108, 30, 0, // Skip to: 86948 /* 79160 */ MCD_OPC_Decode, 175, 24, 238, 1, // Opcode: SQADDv1i64 /* 79165 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 79187 /* 79170 */ MCD_OPC_CheckPredicate, 19, 93, 30, 0, // Skip to: 86948 /* 79175 */ MCD_OPC_CheckField, 21, 3, 0, 86, 30, 0, // Skip to: 86948 /* 79182 */ MCD_OPC_Decode, 244, 22, 203, 3, // Opcode: SHA1Prrr /* 79187 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 79209 /* 79192 */ MCD_OPC_CheckPredicate, 19, 71, 30, 0, // Skip to: 86948 /* 79197 */ MCD_OPC_CheckField, 16, 8, 40, 64, 30, 0, // Skip to: 86948 /* 79204 */ MCD_OPC_Decode, 246, 22, 147, 2, // Opcode: SHA1SU1rr /* 79209 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 79231 /* 79214 */ MCD_OPC_CheckPredicate, 4, 49, 30, 0, // Skip to: 86948 /* 79219 */ MCD_OPC_CheckField, 21, 3, 2, 42, 30, 0, // Skip to: 86948 /* 79226 */ MCD_OPC_Decode, 248, 10, 193, 3, // Opcode: FMULX16 /* 79231 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 79253 /* 79236 */ MCD_OPC_CheckPredicate, 19, 27, 30, 0, // Skip to: 86948 /* 79241 */ MCD_OPC_CheckField, 21, 3, 0, 20, 30, 0, // Skip to: 86948 /* 79248 */ MCD_OPC_Decode, 243, 22, 203, 3, // Opcode: SHA1Mrrr /* 79253 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 79275 /* 79258 */ MCD_OPC_CheckPredicate, 4, 5, 30, 0, // Skip to: 86948 /* 79263 */ MCD_OPC_CheckField, 21, 3, 2, 254, 29, 0, // Skip to: 86948 /* 79270 */ MCD_OPC_Decode, 217, 6, 193, 3, // Opcode: FCMEQ16 /* 79275 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 79297 /* 79280 */ MCD_OPC_CheckPredicate, 19, 239, 29, 0, // Skip to: 86948 /* 79285 */ MCD_OPC_CheckField, 16, 8, 40, 232, 29, 0, // Skip to: 86948 /* 79292 */ MCD_OPC_Decode, 249, 22, 147, 2, // Opcode: SHA256SU0rr /* 79297 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 79365 /* 79302 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 79305 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79320 /* 79310 */ MCD_OPC_CheckPredicate, 3, 209, 29, 0, // Skip to: 86948 /* 79315 */ MCD_OPC_Decode, 158, 26, 208, 3, // Opcode: SQSUBv1i8 /* 79320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79335 /* 79325 */ MCD_OPC_CheckPredicate, 3, 194, 29, 0, // Skip to: 86948 /* 79330 */ MCD_OPC_Decode, 155, 26, 193, 3, // Opcode: SQSUBv1i16 /* 79335 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79350 /* 79340 */ MCD_OPC_CheckPredicate, 3, 179, 29, 0, // Skip to: 86948 /* 79345 */ MCD_OPC_Decode, 156, 26, 172, 3, // Opcode: SQSUBv1i32 /* 79350 */ MCD_OPC_FilterValue, 7, 169, 29, 0, // Skip to: 86948 /* 79355 */ MCD_OPC_CheckPredicate, 3, 164, 29, 0, // Skip to: 86948 /* 79360 */ MCD_OPC_Decode, 157, 26, 238, 1, // Opcode: SQSUBv1i64 /* 79365 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 79387 /* 79370 */ MCD_OPC_CheckPredicate, 19, 149, 29, 0, // Skip to: 86948 /* 79375 */ MCD_OPC_CheckField, 21, 3, 0, 142, 29, 0, // Skip to: 86948 /* 79382 */ MCD_OPC_Decode, 245, 22, 141, 2, // Opcode: SHA1SU0rrr /* 79387 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 79409 /* 79392 */ MCD_OPC_CheckPredicate, 3, 127, 29, 0, // Skip to: 86948 /* 79397 */ MCD_OPC_CheckField, 21, 3, 7, 120, 29, 0, // Skip to: 86948 /* 79404 */ MCD_OPC_Decode, 216, 3, 238, 1, // Opcode: CMGTv1i64 /* 79409 */ MCD_OPC_FilterValue, 14, 65, 0, 0, // Skip to: 79479 /* 79414 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 79417 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 79432 /* 79422 */ MCD_OPC_CheckPredicate, 3, 97, 29, 0, // Skip to: 86948 /* 79427 */ MCD_OPC_Decode, 145, 30, 209, 3, // Opcode: SUQADDv1i8 /* 79432 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 79447 /* 79437 */ MCD_OPC_CheckPredicate, 3, 82, 29, 0, // Skip to: 86948 /* 79442 */ MCD_OPC_Decode, 142, 30, 210, 3, // Opcode: SUQADDv1i16 /* 79447 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 79463 /* 79453 */ MCD_OPC_CheckPredicate, 3, 66, 29, 0, // Skip to: 86948 /* 79458 */ MCD_OPC_Decode, 143, 30, 211, 3, // Opcode: SUQADDv1i32 /* 79463 */ MCD_OPC_FilterValue, 224, 1, 55, 29, 0, // Skip to: 86948 /* 79469 */ MCD_OPC_CheckPredicate, 3, 50, 29, 0, // Skip to: 86948 /* 79474 */ MCD_OPC_Decode, 144, 30, 248, 1, // Opcode: SUQADDv1i64 /* 79479 */ MCD_OPC_FilterValue, 15, 48, 0, 0, // Skip to: 79532 /* 79484 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 79487 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 79502 /* 79492 */ MCD_OPC_CheckPredicate, 4, 27, 29, 0, // Skip to: 86948 /* 79497 */ MCD_OPC_Decode, 207, 11, 193, 3, // Opcode: FRECPS16 /* 79502 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 79517 /* 79507 */ MCD_OPC_CheckPredicate, 4, 12, 29, 0, // Skip to: 86948 /* 79512 */ MCD_OPC_Decode, 184, 12, 193, 3, // Opcode: FRSQRTS16 /* 79517 */ MCD_OPC_FilterValue, 7, 2, 29, 0, // Skip to: 86948 /* 79522 */ MCD_OPC_CheckPredicate, 3, 253, 28, 0, // Skip to: 86948 /* 79527 */ MCD_OPC_Decode, 200, 3, 238, 1, // Opcode: CMGEv1i64 /* 79532 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 79554 /* 79537 */ MCD_OPC_CheckPredicate, 19, 238, 28, 0, // Skip to: 86948 /* 79542 */ MCD_OPC_CheckField, 21, 3, 0, 231, 28, 0, // Skip to: 86948 /* 79549 */ MCD_OPC_Decode, 248, 22, 141, 2, // Opcode: SHA256Hrrr /* 79554 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 79576 /* 79559 */ MCD_OPC_CheckPredicate, 3, 216, 28, 0, // Skip to: 86948 /* 79564 */ MCD_OPC_CheckField, 21, 3, 7, 209, 28, 0, // Skip to: 86948 /* 79571 */ MCD_OPC_Decode, 228, 26, 238, 1, // Opcode: SSHLv1i64 /* 79576 */ MCD_OPC_FilterValue, 18, 49, 0, 0, // Skip to: 79630 /* 79581 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 79584 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 79599 /* 79589 */ MCD_OPC_CheckPredicate, 3, 186, 28, 0, // Skip to: 86948 /* 79594 */ MCD_OPC_Decode, 168, 26, 212, 3, // Opcode: SQXTNv1i8 /* 79599 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 79614 /* 79604 */ MCD_OPC_CheckPredicate, 3, 171, 28, 0, // Skip to: 86948 /* 79609 */ MCD_OPC_Decode, 166, 26, 169, 3, // Opcode: SQXTNv1i16 /* 79614 */ MCD_OPC_FilterValue, 161, 1, 160, 28, 0, // Skip to: 86948 /* 79620 */ MCD_OPC_CheckPredicate, 3, 155, 28, 0, // Skip to: 86948 /* 79625 */ MCD_OPC_Decode, 167, 26, 166, 2, // Opcode: SQXTNv1i32 /* 79630 */ MCD_OPC_FilterValue, 19, 63, 0, 0, // Skip to: 79698 /* 79635 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 79638 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79653 /* 79643 */ MCD_OPC_CheckPredicate, 3, 132, 28, 0, // Skip to: 86948 /* 79648 */ MCD_OPC_Decode, 243, 25, 208, 3, // Opcode: SQSHLv1i8 /* 79653 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79668 /* 79658 */ MCD_OPC_CheckPredicate, 3, 117, 28, 0, // Skip to: 86948 /* 79663 */ MCD_OPC_Decode, 240, 25, 193, 3, // Opcode: SQSHLv1i16 /* 79668 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79683 /* 79673 */ MCD_OPC_CheckPredicate, 3, 102, 28, 0, // Skip to: 86948 /* 79678 */ MCD_OPC_Decode, 241, 25, 172, 3, // Opcode: SQSHLv1i32 /* 79683 */ MCD_OPC_FilterValue, 7, 92, 28, 0, // Skip to: 86948 /* 79688 */ MCD_OPC_CheckPredicate, 3, 87, 28, 0, // Skip to: 86948 /* 79693 */ MCD_OPC_Decode, 242, 25, 238, 1, // Opcode: SQSHLv1i64 /* 79698 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 79720 /* 79703 */ MCD_OPC_CheckPredicate, 19, 72, 28, 0, // Skip to: 86948 /* 79708 */ MCD_OPC_CheckField, 21, 3, 0, 65, 28, 0, // Skip to: 86948 /* 79715 */ MCD_OPC_Decode, 247, 22, 141, 2, // Opcode: SHA256H2rrr /* 79720 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 79742 /* 79725 */ MCD_OPC_CheckPredicate, 3, 50, 28, 0, // Skip to: 86948 /* 79730 */ MCD_OPC_CheckField, 21, 3, 7, 43, 28, 0, // Skip to: 86948 /* 79737 */ MCD_OPC_Decode, 198, 26, 238, 1, // Opcode: SRSHLv1i64 /* 79742 */ MCD_OPC_FilterValue, 23, 63, 0, 0, // Skip to: 79810 /* 79747 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 79750 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79765 /* 79755 */ MCD_OPC_CheckPredicate, 3, 20, 28, 0, // Skip to: 86948 /* 79760 */ MCD_OPC_Decode, 198, 25, 208, 3, // Opcode: SQRSHLv1i8 /* 79765 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79780 /* 79770 */ MCD_OPC_CheckPredicate, 3, 5, 28, 0, // Skip to: 86948 /* 79775 */ MCD_OPC_Decode, 195, 25, 193, 3, // Opcode: SQRSHLv1i16 /* 79780 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79795 /* 79785 */ MCD_OPC_CheckPredicate, 3, 246, 27, 0, // Skip to: 86948 /* 79790 */ MCD_OPC_Decode, 196, 25, 172, 3, // Opcode: SQRSHLv1i32 /* 79795 */ MCD_OPC_FilterValue, 7, 236, 27, 0, // Skip to: 86948 /* 79800 */ MCD_OPC_CheckPredicate, 3, 231, 27, 0, // Skip to: 86948 /* 79805 */ MCD_OPC_Decode, 197, 25, 238, 1, // Opcode: SQRSHLv1i64 /* 79810 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 79832 /* 79815 */ MCD_OPC_CheckPredicate, 19, 216, 27, 0, // Skip to: 86948 /* 79820 */ MCD_OPC_CheckField, 21, 3, 0, 209, 27, 0, // Skip to: 86948 /* 79827 */ MCD_OPC_Decode, 250, 22, 141, 2, // Opcode: SHA256SU1rrr /* 79832 */ MCD_OPC_FilterValue, 30, 65, 0, 0, // Skip to: 79902 /* 79837 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 79840 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 79855 /* 79845 */ MCD_OPC_CheckPredicate, 3, 186, 27, 0, // Skip to: 86948 /* 79850 */ MCD_OPC_Decode, 157, 24, 213, 3, // Opcode: SQABSv1i8 /* 79855 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 79870 /* 79860 */ MCD_OPC_CheckPredicate, 3, 171, 27, 0, // Skip to: 86948 /* 79865 */ MCD_OPC_Decode, 154, 24, 188, 3, // Opcode: SQABSv1i16 /* 79870 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 79886 /* 79876 */ MCD_OPC_CheckPredicate, 3, 155, 27, 0, // Skip to: 86948 /* 79881 */ MCD_OPC_Decode, 155, 24, 167, 3, // Opcode: SQABSv1i32 /* 79886 */ MCD_OPC_FilterValue, 224, 1, 144, 27, 0, // Skip to: 86948 /* 79892 */ MCD_OPC_CheckPredicate, 3, 139, 27, 0, // Skip to: 86948 /* 79897 */ MCD_OPC_Decode, 156, 24, 239, 1, // Opcode: SQABSv1i64 /* 79902 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 79924 /* 79907 */ MCD_OPC_CheckPredicate, 3, 124, 27, 0, // Skip to: 86948 /* 79912 */ MCD_OPC_CheckField, 21, 3, 7, 117, 27, 0, // Skip to: 86948 /* 79919 */ MCD_OPC_Decode, 195, 1, 238, 1, // Opcode: ADDv1i64 /* 79924 */ MCD_OPC_FilterValue, 34, 18, 0, 0, // Skip to: 79947 /* 79929 */ MCD_OPC_CheckPredicate, 3, 102, 27, 0, // Skip to: 86948 /* 79934 */ MCD_OPC_CheckField, 16, 8, 224, 1, 94, 27, 0, // Skip to: 86948 /* 79942 */ MCD_OPC_Decode, 217, 3, 239, 1, // Opcode: CMGTv1i64rz /* 79947 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 79969 /* 79952 */ MCD_OPC_CheckPredicate, 3, 79, 27, 0, // Skip to: 86948 /* 79957 */ MCD_OPC_CheckField, 21, 3, 7, 72, 27, 0, // Skip to: 86948 /* 79964 */ MCD_OPC_Decode, 234, 4, 238, 1, // Opcode: CMTSTv1i64 /* 79969 */ MCD_OPC_FilterValue, 36, 33, 0, 0, // Skip to: 80007 /* 79974 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 79977 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79992 /* 79982 */ MCD_OPC_CheckPredicate, 3, 49, 27, 0, // Skip to: 86948 /* 79987 */ MCD_OPC_Decode, 205, 24, 214, 3, // Opcode: SQDMLALi16 /* 79992 */ MCD_OPC_FilterValue, 5, 39, 27, 0, // Skip to: 86948 /* 79997 */ MCD_OPC_CheckPredicate, 3, 34, 27, 0, // Skip to: 86948 /* 80002 */ MCD_OPC_Decode, 206, 24, 215, 3, // Opcode: SQDMLALi32 /* 80007 */ MCD_OPC_FilterValue, 38, 18, 0, 0, // Skip to: 80030 /* 80012 */ MCD_OPC_CheckPredicate, 3, 19, 27, 0, // Skip to: 86948 /* 80017 */ MCD_OPC_CheckField, 16, 8, 224, 1, 11, 27, 0, // Skip to: 86948 /* 80025 */ MCD_OPC_Decode, 185, 3, 239, 1, // Opcode: CMEQv1i64rz /* 80030 */ MCD_OPC_FilterValue, 42, 112, 0, 0, // Skip to: 80147 /* 80035 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 80038 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80053 /* 80043 */ MCD_OPC_CheckPredicate, 3, 244, 26, 0, // Skip to: 86948 /* 80048 */ MCD_OPC_Decode, 160, 8, 167, 3, // Opcode: FCVTNSv1i32 /* 80053 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80068 /* 80058 */ MCD_OPC_CheckPredicate, 3, 229, 26, 0, // Skip to: 86948 /* 80063 */ MCD_OPC_Decode, 161, 8, 239, 1, // Opcode: FCVTNSv1i64 /* 80068 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80083 /* 80073 */ MCD_OPC_CheckPredicate, 4, 214, 26, 0, // Skip to: 86948 /* 80078 */ MCD_OPC_Decode, 159, 8, 188, 3, // Opcode: FCVTNSv1f16 /* 80083 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80099 /* 80089 */ MCD_OPC_CheckPredicate, 3, 198, 26, 0, // Skip to: 86948 /* 80094 */ MCD_OPC_Decode, 192, 8, 167, 3, // Opcode: FCVTPSv1i32 /* 80099 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80115 /* 80105 */ MCD_OPC_CheckPredicate, 3, 182, 26, 0, // Skip to: 86948 /* 80110 */ MCD_OPC_Decode, 255, 3, 239, 1, // Opcode: CMLTv1i64rz /* 80115 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80131 /* 80121 */ MCD_OPC_CheckPredicate, 3, 166, 26, 0, // Skip to: 86948 /* 80126 */ MCD_OPC_Decode, 193, 8, 239, 1, // Opcode: FCVTPSv1i64 /* 80131 */ MCD_OPC_FilterValue, 249, 1, 155, 26, 0, // Skip to: 86948 /* 80137 */ MCD_OPC_CheckPredicate, 4, 150, 26, 0, // Skip to: 86948 /* 80142 */ MCD_OPC_Decode, 191, 8, 188, 3, // Opcode: FCVTPSv1f16 /* 80147 */ MCD_OPC_FilterValue, 44, 33, 0, 0, // Skip to: 80185 /* 80152 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 80155 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80170 /* 80160 */ MCD_OPC_CheckPredicate, 3, 127, 26, 0, // Skip to: 86948 /* 80165 */ MCD_OPC_Decode, 217, 24, 214, 3, // Opcode: SQDMLSLi16 /* 80170 */ MCD_OPC_FilterValue, 5, 117, 26, 0, // Skip to: 86948 /* 80175 */ MCD_OPC_CheckPredicate, 3, 112, 26, 0, // Skip to: 86948 /* 80180 */ MCD_OPC_Decode, 218, 24, 215, 3, // Opcode: SQDMLSLi32 /* 80185 */ MCD_OPC_FilterValue, 45, 33, 0, 0, // Skip to: 80223 /* 80190 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 80193 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80208 /* 80198 */ MCD_OPC_CheckPredicate, 3, 89, 26, 0, // Skip to: 86948 /* 80203 */ MCD_OPC_Decode, 229, 24, 193, 3, // Opcode: SQDMULHv1i16 /* 80208 */ MCD_OPC_FilterValue, 5, 79, 26, 0, // Skip to: 86948 /* 80213 */ MCD_OPC_CheckPredicate, 3, 74, 26, 0, // Skip to: 86948 /* 80218 */ MCD_OPC_Decode, 231, 24, 172, 3, // Opcode: SQDMULHv1i32 /* 80223 */ MCD_OPC_FilterValue, 46, 128, 0, 0, // Skip to: 80356 /* 80228 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 80231 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80246 /* 80236 */ MCD_OPC_CheckPredicate, 3, 51, 26, 0, // Skip to: 86948 /* 80241 */ MCD_OPC_Decode, 132, 8, 167, 3, // Opcode: FCVTMSv1i32 /* 80246 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80261 /* 80251 */ MCD_OPC_CheckPredicate, 3, 36, 26, 0, // Skip to: 86948 /* 80256 */ MCD_OPC_Decode, 133, 8, 239, 1, // Opcode: FCVTMSv1i64 /* 80261 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80276 /* 80266 */ MCD_OPC_CheckPredicate, 4, 21, 26, 0, // Skip to: 86948 /* 80271 */ MCD_OPC_Decode, 131, 8, 188, 3, // Opcode: FCVTMSv1f16 /* 80276 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80292 /* 80282 */ MCD_OPC_CheckPredicate, 3, 5, 26, 0, // Skip to: 86948 /* 80287 */ MCD_OPC_Decode, 241, 8, 167, 3, // Opcode: FCVTZSv1i32 /* 80292 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80308 /* 80298 */ MCD_OPC_CheckPredicate, 3, 245, 25, 0, // Skip to: 86948 /* 80303 */ MCD_OPC_Decode, 131, 1, 239, 1, // Opcode: ABSv1i64 /* 80308 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80324 /* 80314 */ MCD_OPC_CheckPredicate, 3, 229, 25, 0, // Skip to: 86948 /* 80319 */ MCD_OPC_Decode, 242, 8, 239, 1, // Opcode: FCVTZSv1i64 /* 80324 */ MCD_OPC_FilterValue, 241, 1, 10, 0, 0, // Skip to: 80340 /* 80330 */ MCD_OPC_CheckPredicate, 3, 213, 25, 0, // Skip to: 86948 /* 80335 */ MCD_OPC_Decode, 152, 1, 244, 1, // Opcode: ADDPv2i64p /* 80340 */ MCD_OPC_FilterValue, 249, 1, 202, 25, 0, // Skip to: 86948 /* 80346 */ MCD_OPC_CheckPredicate, 4, 197, 25, 0, // Skip to: 86948 /* 80351 */ MCD_OPC_Decode, 240, 8, 188, 3, // Opcode: FCVTZSv1f16 /* 80356 */ MCD_OPC_FilterValue, 50, 127, 0, 0, // Skip to: 80488 /* 80361 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 80364 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80379 /* 80369 */ MCD_OPC_CheckPredicate, 3, 174, 25, 0, // Skip to: 86948 /* 80374 */ MCD_OPC_Decode, 224, 7, 167, 3, // Opcode: FCVTASv1i32 /* 80379 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80394 /* 80384 */ MCD_OPC_CheckPredicate, 4, 159, 25, 0, // Skip to: 86948 /* 80389 */ MCD_OPC_Decode, 199, 9, 249, 1, // Opcode: FMAXNMPv2i16p /* 80394 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80409 /* 80399 */ MCD_OPC_CheckPredicate, 3, 144, 25, 0, // Skip to: 86948 /* 80404 */ MCD_OPC_Decode, 225, 7, 239, 1, // Opcode: FCVTASv1i64 /* 80409 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80424 /* 80414 */ MCD_OPC_CheckPredicate, 4, 129, 25, 0, // Skip to: 86948 /* 80419 */ MCD_OPC_Decode, 223, 7, 188, 3, // Opcode: FCVTASv1f16 /* 80424 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80440 /* 80430 */ MCD_OPC_CheckPredicate, 3, 113, 25, 0, // Skip to: 86948 /* 80435 */ MCD_OPC_Decode, 143, 7, 167, 3, // Opcode: FCMGTv1i32rz /* 80440 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 80456 /* 80446 */ MCD_OPC_CheckPredicate, 4, 97, 25, 0, // Skip to: 86948 /* 80451 */ MCD_OPC_Decode, 255, 9, 249, 1, // Opcode: FMINNMPv2i16p /* 80456 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80472 /* 80462 */ MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 86948 /* 80467 */ MCD_OPC_Decode, 144, 7, 239, 1, // Opcode: FCMGTv1i64rz /* 80472 */ MCD_OPC_FilterValue, 248, 1, 70, 25, 0, // Skip to: 86948 /* 80478 */ MCD_OPC_CheckPredicate, 4, 65, 25, 0, // Skip to: 86948 /* 80483 */ MCD_OPC_Decode, 142, 7, 188, 3, // Opcode: FCMGTv1i16rz /* 80488 */ MCD_OPC_FilterValue, 52, 33, 0, 0, // Skip to: 80526 /* 80493 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 80496 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80511 /* 80501 */ MCD_OPC_CheckPredicate, 3, 42, 25, 0, // Skip to: 86948 /* 80506 */ MCD_OPC_Decode, 241, 24, 216, 3, // Opcode: SQDMULLi16 /* 80511 */ MCD_OPC_FilterValue, 5, 32, 25, 0, // Skip to: 86948 /* 80516 */ MCD_OPC_CheckPredicate, 3, 27, 25, 0, // Skip to: 86948 /* 80521 */ MCD_OPC_Decode, 242, 24, 217, 3, // Opcode: SQDMULLi32 /* 80526 */ MCD_OPC_FilterValue, 54, 159, 0, 0, // Skip to: 80690 /* 80531 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 80534 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80549 /* 80539 */ MCD_OPC_CheckPredicate, 3, 4, 25, 0, // Skip to: 86948 /* 80544 */ MCD_OPC_Decode, 207, 22, 167, 3, // Opcode: SCVTFv1i32 /* 80549 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80564 /* 80554 */ MCD_OPC_CheckPredicate, 4, 245, 24, 0, // Skip to: 86948 /* 80559 */ MCD_OPC_Decode, 179, 6, 249, 1, // Opcode: FADDPv2i16p /* 80564 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80579 /* 80569 */ MCD_OPC_CheckPredicate, 3, 230, 24, 0, // Skip to: 86948 /* 80574 */ MCD_OPC_Decode, 208, 22, 239, 1, // Opcode: SCVTFv1i64 /* 80579 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80594 /* 80584 */ MCD_OPC_CheckPredicate, 4, 215, 24, 0, // Skip to: 86948 /* 80589 */ MCD_OPC_Decode, 206, 22, 188, 3, // Opcode: SCVTFv1i16 /* 80594 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80610 /* 80600 */ MCD_OPC_CheckPredicate, 3, 199, 24, 0, // Skip to: 86948 /* 80605 */ MCD_OPC_Decode, 227, 6, 167, 3, // Opcode: FCMEQv1i32rz /* 80610 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80626 /* 80616 */ MCD_OPC_CheckPredicate, 3, 183, 24, 0, // Skip to: 86948 /* 80621 */ MCD_OPC_Decode, 200, 11, 167, 3, // Opcode: FRECPEv1i32 /* 80626 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80642 /* 80632 */ MCD_OPC_CheckPredicate, 3, 167, 24, 0, // Skip to: 86948 /* 80637 */ MCD_OPC_Decode, 228, 6, 239, 1, // Opcode: FCMEQv1i64rz /* 80642 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80658 /* 80648 */ MCD_OPC_CheckPredicate, 3, 151, 24, 0, // Skip to: 86948 /* 80653 */ MCD_OPC_Decode, 201, 11, 239, 1, // Opcode: FRECPEv1i64 /* 80658 */ MCD_OPC_FilterValue, 248, 1, 10, 0, 0, // Skip to: 80674 /* 80664 */ MCD_OPC_CheckPredicate, 4, 135, 24, 0, // Skip to: 86948 /* 80669 */ MCD_OPC_Decode, 226, 6, 188, 3, // Opcode: FCMEQv1i16rz /* 80674 */ MCD_OPC_FilterValue, 249, 1, 124, 24, 0, // Skip to: 86948 /* 80680 */ MCD_OPC_CheckPredicate, 4, 119, 24, 0, // Skip to: 86948 /* 80685 */ MCD_OPC_Decode, 199, 11, 188, 3, // Opcode: FRECPEv1f16 /* 80690 */ MCD_OPC_FilterValue, 55, 33, 0, 0, // Skip to: 80728 /* 80695 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 80698 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80713 /* 80703 */ MCD_OPC_CheckPredicate, 3, 96, 24, 0, // Skip to: 86948 /* 80708 */ MCD_OPC_Decode, 249, 10, 172, 3, // Opcode: FMULX32 /* 80713 */ MCD_OPC_FilterValue, 3, 86, 24, 0, // Skip to: 86948 /* 80718 */ MCD_OPC_CheckPredicate, 3, 81, 24, 0, // Skip to: 86948 /* 80723 */ MCD_OPC_Decode, 250, 10, 238, 1, // Opcode: FMULX64 /* 80728 */ MCD_OPC_FilterValue, 57, 33, 0, 0, // Skip to: 80766 /* 80733 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 80736 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80751 /* 80741 */ MCD_OPC_CheckPredicate, 3, 58, 24, 0, // Skip to: 86948 /* 80746 */ MCD_OPC_Decode, 218, 6, 172, 3, // Opcode: FCMEQ32 /* 80751 */ MCD_OPC_FilterValue, 3, 48, 24, 0, // Skip to: 86948 /* 80756 */ MCD_OPC_CheckPredicate, 3, 43, 24, 0, // Skip to: 86948 /* 80761 */ MCD_OPC_Decode, 219, 6, 238, 1, // Opcode: FCMEQ64 /* 80766 */ MCD_OPC_FilterValue, 58, 51, 0, 0, // Skip to: 80822 /* 80771 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 80774 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80790 /* 80780 */ MCD_OPC_CheckPredicate, 3, 19, 24, 0, // Skip to: 86948 /* 80785 */ MCD_OPC_Decode, 183, 7, 167, 3, // Opcode: FCMLTv1i32rz /* 80790 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80806 /* 80796 */ MCD_OPC_CheckPredicate, 3, 3, 24, 0, // Skip to: 86948 /* 80801 */ MCD_OPC_Decode, 184, 7, 239, 1, // Opcode: FCMLTv1i64rz /* 80806 */ MCD_OPC_FilterValue, 248, 1, 248, 23, 0, // Skip to: 86948 /* 80812 */ MCD_OPC_CheckPredicate, 4, 243, 23, 0, // Skip to: 86948 /* 80817 */ MCD_OPC_Decode, 182, 7, 188, 3, // Opcode: FCMLTv1i16rz /* 80822 */ MCD_OPC_FilterValue, 62, 82, 0, 0, // Skip to: 80909 /* 80827 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 80830 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80845 /* 80835 */ MCD_OPC_CheckPredicate, 4, 220, 23, 0, // Skip to: 86948 /* 80840 */ MCD_OPC_Decode, 225, 9, 249, 1, // Opcode: FMAXPv2i16p /* 80845 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80861 /* 80851 */ MCD_OPC_CheckPredicate, 3, 204, 23, 0, // Skip to: 86948 /* 80856 */ MCD_OPC_Decode, 222, 11, 167, 3, // Opcode: FRECPXv1i32 /* 80861 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 80877 /* 80867 */ MCD_OPC_CheckPredicate, 4, 188, 23, 0, // Skip to: 86948 /* 80872 */ MCD_OPC_Decode, 153, 10, 249, 1, // Opcode: FMINPv2i16p /* 80877 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80893 /* 80883 */ MCD_OPC_CheckPredicate, 3, 172, 23, 0, // Skip to: 86948 /* 80888 */ MCD_OPC_Decode, 223, 11, 239, 1, // Opcode: FRECPXv1i64 /* 80893 */ MCD_OPC_FilterValue, 249, 1, 161, 23, 0, // Skip to: 86948 /* 80899 */ MCD_OPC_CheckPredicate, 4, 156, 23, 0, // Skip to: 86948 /* 80904 */ MCD_OPC_Decode, 221, 11, 188, 3, // Opcode: FRECPXv1f16 /* 80909 */ MCD_OPC_FilterValue, 63, 146, 23, 0, // Skip to: 86948 /* 80914 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 80917 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80932 /* 80922 */ MCD_OPC_CheckPredicate, 3, 133, 23, 0, // Skip to: 86948 /* 80927 */ MCD_OPC_Decode, 208, 11, 172, 3, // Opcode: FRECPS32 /* 80932 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80947 /* 80937 */ MCD_OPC_CheckPredicate, 3, 118, 23, 0, // Skip to: 86948 /* 80942 */ MCD_OPC_Decode, 209, 11, 238, 1, // Opcode: FRECPS64 /* 80947 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 80962 /* 80952 */ MCD_OPC_CheckPredicate, 3, 103, 23, 0, // Skip to: 86948 /* 80957 */ MCD_OPC_Decode, 185, 12, 172, 3, // Opcode: FRSQRTS32 /* 80962 */ MCD_OPC_FilterValue, 7, 93, 23, 0, // Skip to: 86948 /* 80967 */ MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 86948 /* 80972 */ MCD_OPC_Decode, 186, 12, 238, 1, // Opcode: FRSQRTS64 /* 80977 */ MCD_OPC_FilterValue, 3, 78, 23, 0, // Skip to: 86948 /* 80982 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 80985 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81014 /* 80990 */ MCD_OPC_CheckPredicate, 3, 65, 23, 0, // Skip to: 86948 /* 80995 */ MCD_OPC_CheckField, 22, 2, 1, 58, 23, 0, // Skip to: 86948 /* 81002 */ MCD_OPC_CheckField, 10, 2, 1, 51, 23, 0, // Skip to: 86948 /* 81009 */ MCD_OPC_Decode, 235, 26, 218, 3, // Opcode: SSHRd /* 81014 */ MCD_OPC_FilterValue, 1, 98, 0, 0, // Skip to: 81117 /* 81019 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81022 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81044 /* 81027 */ MCD_OPC_CheckPredicate, 4, 28, 23, 0, // Skip to: 86948 /* 81032 */ MCD_OPC_CheckField, 10, 1, 0, 21, 23, 0, // Skip to: 86948 /* 81039 */ MCD_OPC_Decode, 183, 10, 219, 3, // Opcode: FMLAv1i16_indexed /* 81044 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81066 /* 81049 */ MCD_OPC_CheckPredicate, 3, 6, 23, 0, // Skip to: 86948 /* 81054 */ MCD_OPC_CheckField, 10, 2, 1, 255, 22, 0, // Skip to: 86948 /* 81061 */ MCD_OPC_Decode, 243, 26, 220, 3, // Opcode: SSRAd /* 81066 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81088 /* 81071 */ MCD_OPC_CheckPredicate, 3, 240, 22, 0, // Skip to: 86948 /* 81076 */ MCD_OPC_CheckField, 10, 1, 0, 233, 22, 0, // Skip to: 86948 /* 81083 */ MCD_OPC_Decode, 184, 10, 221, 3, // Opcode: FMLAv1i32_indexed /* 81088 */ MCD_OPC_FilterValue, 3, 223, 22, 0, // Skip to: 86948 /* 81093 */ MCD_OPC_CheckPredicate, 3, 218, 22, 0, // Skip to: 86948 /* 81098 */ MCD_OPC_CheckField, 21, 1, 0, 211, 22, 0, // Skip to: 86948 /* 81105 */ MCD_OPC_CheckField, 10, 1, 0, 204, 22, 0, // Skip to: 86948 /* 81112 */ MCD_OPC_Decode, 185, 10, 222, 3, // Opcode: FMLAv1i64_indexed /* 81117 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 81146 /* 81122 */ MCD_OPC_CheckPredicate, 3, 189, 22, 0, // Skip to: 86948 /* 81127 */ MCD_OPC_CheckField, 22, 2, 1, 182, 22, 0, // Skip to: 86948 /* 81134 */ MCD_OPC_CheckField, 10, 2, 1, 175, 22, 0, // Skip to: 86948 /* 81141 */ MCD_OPC_Decode, 205, 26, 218, 3, // Opcode: SRSHRd /* 81146 */ MCD_OPC_FilterValue, 3, 70, 0, 0, // Skip to: 81221 /* 81151 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 81154 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 81192 /* 81159 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81162 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 81177 /* 81167 */ MCD_OPC_CheckPredicate, 3, 144, 22, 0, // Skip to: 86948 /* 81172 */ MCD_OPC_Decode, 207, 24, 223, 3, // Opcode: SQDMLALv1i32_indexed /* 81177 */ MCD_OPC_FilterValue, 2, 134, 22, 0, // Skip to: 86948 /* 81182 */ MCD_OPC_CheckPredicate, 3, 129, 22, 0, // Skip to: 86948 /* 81187 */ MCD_OPC_Decode, 208, 24, 224, 3, // Opcode: SQDMLALv1i64_indexed /* 81192 */ MCD_OPC_FilterValue, 1, 119, 22, 0, // Skip to: 86948 /* 81197 */ MCD_OPC_CheckPredicate, 3, 114, 22, 0, // Skip to: 86948 /* 81202 */ MCD_OPC_CheckField, 22, 2, 1, 107, 22, 0, // Skip to: 86948 /* 81209 */ MCD_OPC_CheckField, 11, 1, 0, 100, 22, 0, // Skip to: 86948 /* 81216 */ MCD_OPC_Decode, 213, 26, 220, 3, // Opcode: SRSRAd /* 81221 */ MCD_OPC_FilterValue, 5, 98, 0, 0, // Skip to: 81324 /* 81226 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81229 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81251 /* 81234 */ MCD_OPC_CheckPredicate, 4, 77, 22, 0, // Skip to: 86948 /* 81239 */ MCD_OPC_CheckField, 10, 1, 0, 70, 22, 0, // Skip to: 86948 /* 81246 */ MCD_OPC_Decode, 202, 10, 219, 3, // Opcode: FMLSv1i16_indexed /* 81251 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81273 /* 81256 */ MCD_OPC_CheckPredicate, 3, 55, 22, 0, // Skip to: 86948 /* 81261 */ MCD_OPC_CheckField, 10, 2, 1, 48, 22, 0, // Skip to: 86948 /* 81268 */ MCD_OPC_Decode, 139, 23, 225, 3, // Opcode: SHLd /* 81273 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81295 /* 81278 */ MCD_OPC_CheckPredicate, 3, 33, 22, 0, // Skip to: 86948 /* 81283 */ MCD_OPC_CheckField, 10, 1, 0, 26, 22, 0, // Skip to: 86948 /* 81290 */ MCD_OPC_Decode, 203, 10, 221, 3, // Opcode: FMLSv1i32_indexed /* 81295 */ MCD_OPC_FilterValue, 3, 16, 22, 0, // Skip to: 86948 /* 81300 */ MCD_OPC_CheckPredicate, 3, 11, 22, 0, // Skip to: 86948 /* 81305 */ MCD_OPC_CheckField, 21, 1, 0, 4, 22, 0, // Skip to: 86948 /* 81312 */ MCD_OPC_CheckField, 10, 1, 0, 253, 21, 0, // Skip to: 86948 /* 81319 */ MCD_OPC_Decode, 204, 10, 222, 3, // Opcode: FMLSv1i64_indexed /* 81324 */ MCD_OPC_FilterValue, 7, 159, 0, 0, // Skip to: 81488 /* 81329 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81332 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 81421 /* 81337 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 81340 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 81399 /* 81345 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 81348 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81377 /* 81353 */ MCD_OPC_CheckPredicate, 3, 214, 21, 0, // Skip to: 86948 /* 81358 */ MCD_OPC_CheckField, 19, 1, 1, 207, 21, 0, // Skip to: 86948 /* 81365 */ MCD_OPC_CheckField, 10, 2, 1, 200, 21, 0, // Skip to: 86948 /* 81372 */ MCD_OPC_Decode, 234, 25, 226, 3, // Opcode: SQSHLb /* 81377 */ MCD_OPC_FilterValue, 1, 190, 21, 0, // Skip to: 86948 /* 81382 */ MCD_OPC_CheckPredicate, 3, 185, 21, 0, // Skip to: 86948 /* 81387 */ MCD_OPC_CheckField, 10, 2, 1, 178, 21, 0, // Skip to: 86948 /* 81394 */ MCD_OPC_Decode, 236, 25, 227, 3, // Opcode: SQSHLh /* 81399 */ MCD_OPC_FilterValue, 1, 168, 21, 0, // Skip to: 86948 /* 81404 */ MCD_OPC_CheckPredicate, 3, 163, 21, 0, // Skip to: 86948 /* 81409 */ MCD_OPC_CheckField, 10, 2, 1, 156, 21, 0, // Skip to: 86948 /* 81416 */ MCD_OPC_Decode, 237, 25, 228, 3, // Opcode: SQSHLs /* 81421 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 81466 /* 81426 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 81429 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 81444 /* 81434 */ MCD_OPC_CheckPredicate, 3, 133, 21, 0, // Skip to: 86948 /* 81439 */ MCD_OPC_Decode, 219, 24, 223, 3, // Opcode: SQDMLSLv1i32_indexed /* 81444 */ MCD_OPC_FilterValue, 1, 123, 21, 0, // Skip to: 86948 /* 81449 */ MCD_OPC_CheckPredicate, 3, 118, 21, 0, // Skip to: 86948 /* 81454 */ MCD_OPC_CheckField, 11, 1, 0, 111, 21, 0, // Skip to: 86948 /* 81461 */ MCD_OPC_Decode, 235, 25, 225, 3, // Opcode: SQSHLd /* 81466 */ MCD_OPC_FilterValue, 2, 101, 21, 0, // Skip to: 86948 /* 81471 */ MCD_OPC_CheckPredicate, 3, 96, 21, 0, // Skip to: 86948 /* 81476 */ MCD_OPC_CheckField, 10, 1, 0, 89, 21, 0, // Skip to: 86948 /* 81483 */ MCD_OPC_Decode, 220, 24, 224, 3, // Opcode: SQDMLSLv1i64_indexed /* 81488 */ MCD_OPC_FilterValue, 9, 221, 0, 0, // Skip to: 81714 /* 81493 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81496 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 81663 /* 81501 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 81504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 81519 /* 81509 */ MCD_OPC_CheckPredicate, 4, 58, 21, 0, // Skip to: 86948 /* 81514 */ MCD_OPC_Decode, 151, 11, 229, 3, // Opcode: FMULv1i16_indexed /* 81519 */ MCD_OPC_FilterValue, 1, 48, 21, 0, // Skip to: 86948 /* 81524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 81527 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 81595 /* 81532 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 81535 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 81580 /* 81540 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 81543 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81565 /* 81548 */ MCD_OPC_CheckPredicate, 3, 19, 21, 0, // Skip to: 86948 /* 81553 */ MCD_OPC_CheckField, 19, 1, 1, 12, 21, 0, // Skip to: 86948 /* 81560 */ MCD_OPC_Decode, 128, 26, 230, 3, // Opcode: SQSHRNb /* 81565 */ MCD_OPC_FilterValue, 1, 2, 21, 0, // Skip to: 86948 /* 81570 */ MCD_OPC_CheckPredicate, 3, 253, 20, 0, // Skip to: 86948 /* 81575 */ MCD_OPC_Decode, 129, 26, 231, 3, // Opcode: SQSHRNh /* 81580 */ MCD_OPC_FilterValue, 1, 243, 20, 0, // Skip to: 86948 /* 81585 */ MCD_OPC_CheckPredicate, 3, 238, 20, 0, // Skip to: 86948 /* 81590 */ MCD_OPC_Decode, 130, 26, 232, 3, // Opcode: SQSHRNs /* 81595 */ MCD_OPC_FilterValue, 1, 228, 20, 0, // Skip to: 86948 /* 81600 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 81603 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 81648 /* 81608 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 81611 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81633 /* 81616 */ MCD_OPC_CheckPredicate, 3, 207, 20, 0, // Skip to: 86948 /* 81621 */ MCD_OPC_CheckField, 19, 1, 1, 200, 20, 0, // Skip to: 86948 /* 81628 */ MCD_OPC_Decode, 205, 25, 230, 3, // Opcode: SQRSHRNb /* 81633 */ MCD_OPC_FilterValue, 1, 190, 20, 0, // Skip to: 86948 /* 81638 */ MCD_OPC_CheckPredicate, 3, 185, 20, 0, // Skip to: 86948 /* 81643 */ MCD_OPC_Decode, 206, 25, 231, 3, // Opcode: SQRSHRNh /* 81648 */ MCD_OPC_FilterValue, 1, 175, 20, 0, // Skip to: 86948 /* 81653 */ MCD_OPC_CheckPredicate, 3, 170, 20, 0, // Skip to: 86948 /* 81658 */ MCD_OPC_Decode, 207, 25, 232, 3, // Opcode: SQRSHRNs /* 81663 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81685 /* 81668 */ MCD_OPC_CheckPredicate, 3, 155, 20, 0, // Skip to: 86948 /* 81673 */ MCD_OPC_CheckField, 10, 1, 0, 148, 20, 0, // Skip to: 86948 /* 81680 */ MCD_OPC_Decode, 152, 11, 233, 3, // Opcode: FMULv1i32_indexed /* 81685 */ MCD_OPC_FilterValue, 3, 138, 20, 0, // Skip to: 86948 /* 81690 */ MCD_OPC_CheckPredicate, 3, 133, 20, 0, // Skip to: 86948 /* 81695 */ MCD_OPC_CheckField, 21, 1, 0, 126, 20, 0, // Skip to: 86948 /* 81702 */ MCD_OPC_CheckField, 10, 1, 0, 119, 20, 0, // Skip to: 86948 /* 81709 */ MCD_OPC_Decode, 153, 11, 234, 3, // Opcode: FMULv1i64_indexed /* 81714 */ MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 81766 /* 81719 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81722 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81744 /* 81727 */ MCD_OPC_CheckPredicate, 3, 96, 20, 0, // Skip to: 86948 /* 81732 */ MCD_OPC_CheckField, 10, 1, 0, 89, 20, 0, // Skip to: 86948 /* 81739 */ MCD_OPC_Decode, 243, 24, 235, 3, // Opcode: SQDMULLv1i32_indexed /* 81744 */ MCD_OPC_FilterValue, 2, 79, 20, 0, // Skip to: 86948 /* 81749 */ MCD_OPC_CheckPredicate, 3, 74, 20, 0, // Skip to: 86948 /* 81754 */ MCD_OPC_CheckField, 10, 1, 0, 67, 20, 0, // Skip to: 86948 /* 81761 */ MCD_OPC_Decode, 244, 24, 236, 3, // Opcode: SQDMULLv1i64_indexed /* 81766 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 81818 /* 81771 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81774 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81796 /* 81779 */ MCD_OPC_CheckPredicate, 3, 44, 20, 0, // Skip to: 86948 /* 81784 */ MCD_OPC_CheckField, 10, 1, 0, 37, 20, 0, // Skip to: 86948 /* 81791 */ MCD_OPC_Decode, 230, 24, 229, 3, // Opcode: SQDMULHv1i16_indexed /* 81796 */ MCD_OPC_FilterValue, 2, 27, 20, 0, // Skip to: 86948 /* 81801 */ MCD_OPC_CheckPredicate, 3, 22, 20, 0, // Skip to: 86948 /* 81806 */ MCD_OPC_CheckField, 10, 1, 0, 15, 20, 0, // Skip to: 86948 /* 81813 */ MCD_OPC_Decode, 232, 24, 233, 3, // Opcode: SQDMULHv1i32_indexed /* 81818 */ MCD_OPC_FilterValue, 13, 47, 0, 0, // Skip to: 81870 /* 81823 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81826 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81848 /* 81831 */ MCD_OPC_CheckPredicate, 3, 248, 19, 0, // Skip to: 86948 /* 81836 */ MCD_OPC_CheckField, 10, 1, 0, 241, 19, 0, // Skip to: 86948 /* 81843 */ MCD_OPC_Decode, 183, 25, 229, 3, // Opcode: SQRDMULHv1i16_indexed /* 81848 */ MCD_OPC_FilterValue, 2, 231, 19, 0, // Skip to: 86948 /* 81853 */ MCD_OPC_CheckPredicate, 3, 226, 19, 0, // Skip to: 86948 /* 81858 */ MCD_OPC_CheckField, 10, 1, 0, 219, 19, 0, // Skip to: 86948 /* 81865 */ MCD_OPC_Decode, 185, 25, 233, 3, // Opcode: SQRDMULHv1i32_indexed /* 81870 */ MCD_OPC_FilterValue, 14, 84, 0, 0, // Skip to: 81959 /* 81875 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81878 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 81937 /* 81883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 81886 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81915 /* 81891 */ MCD_OPC_CheckPredicate, 4, 188, 19, 0, // Skip to: 86948 /* 81896 */ MCD_OPC_CheckField, 20, 1, 1, 181, 19, 0, // Skip to: 86948 /* 81903 */ MCD_OPC_CheckField, 10, 2, 1, 174, 19, 0, // Skip to: 86948 /* 81910 */ MCD_OPC_Decode, 204, 22, 237, 3, // Opcode: SCVTFh /* 81915 */ MCD_OPC_FilterValue, 1, 164, 19, 0, // Skip to: 86948 /* 81920 */ MCD_OPC_CheckPredicate, 3, 159, 19, 0, // Skip to: 86948 /* 81925 */ MCD_OPC_CheckField, 10, 2, 1, 152, 19, 0, // Skip to: 86948 /* 81932 */ MCD_OPC_Decode, 205, 22, 238, 3, // Opcode: SCVTFs /* 81937 */ MCD_OPC_FilterValue, 1, 142, 19, 0, // Skip to: 86948 /* 81942 */ MCD_OPC_CheckPredicate, 3, 137, 19, 0, // Skip to: 86948 /* 81947 */ MCD_OPC_CheckField, 10, 2, 1, 130, 19, 0, // Skip to: 86948 /* 81954 */ MCD_OPC_Decode, 203, 22, 218, 3, // Opcode: SCVTFd /* 81959 */ MCD_OPC_FilterValue, 15, 120, 19, 0, // Skip to: 86948 /* 81964 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 81967 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 82026 /* 81972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 81975 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 82004 /* 81980 */ MCD_OPC_CheckPredicate, 4, 99, 19, 0, // Skip to: 86948 /* 81985 */ MCD_OPC_CheckField, 20, 1, 1, 92, 19, 0, // Skip to: 86948 /* 81992 */ MCD_OPC_CheckField, 10, 2, 3, 85, 19, 0, // Skip to: 86948 /* 81999 */ MCD_OPC_Decode, 238, 8, 237, 3, // Opcode: FCVTZSh /* 82004 */ MCD_OPC_FilterValue, 1, 75, 19, 0, // Skip to: 86948 /* 82009 */ MCD_OPC_CheckPredicate, 3, 70, 19, 0, // Skip to: 86948 /* 82014 */ MCD_OPC_CheckField, 10, 2, 3, 63, 19, 0, // Skip to: 86948 /* 82021 */ MCD_OPC_Decode, 239, 8, 238, 3, // Opcode: FCVTZSs /* 82026 */ MCD_OPC_FilterValue, 1, 53, 19, 0, // Skip to: 86948 /* 82031 */ MCD_OPC_CheckPredicate, 3, 48, 19, 0, // Skip to: 86948 /* 82036 */ MCD_OPC_CheckField, 10, 2, 3, 41, 19, 0, // Skip to: 86948 /* 82043 */ MCD_OPC_Decode, 237, 8, 218, 3, // Opcode: FCVTZSd /* 82048 */ MCD_OPC_FilterValue, 3, 213, 12, 0, // Skip to: 85338 /* 82053 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 82056 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 82157 /* 82061 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 82064 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 82081 /* 82069 */ MCD_OPC_CheckField, 21, 1, 0, 8, 19, 0, // Skip to: 86948 /* 82076 */ MCD_OPC_Decode, 200, 29, 255, 2, // Opcode: STURHi /* 82081 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 82098 /* 82086 */ MCD_OPC_CheckField, 21, 1, 0, 247, 18, 0, // Skip to: 86948 /* 82093 */ MCD_OPC_Decode, 165, 29, 255, 2, // Opcode: STRHpost /* 82098 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 82140 /* 82103 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 82106 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 82123 /* 82111 */ MCD_OPC_CheckField, 21, 1, 1, 222, 18, 0, // Skip to: 86948 /* 82118 */ MCD_OPC_Decode, 167, 29, 239, 3, // Opcode: STRHroW /* 82123 */ MCD_OPC_FilterValue, 3, 212, 18, 0, // Skip to: 86948 /* 82128 */ MCD_OPC_CheckField, 21, 1, 1, 205, 18, 0, // Skip to: 86948 /* 82135 */ MCD_OPC_Decode, 168, 29, 240, 3, // Opcode: STRHroX /* 82140 */ MCD_OPC_FilterValue, 3, 195, 18, 0, // Skip to: 86948 /* 82145 */ MCD_OPC_CheckField, 21, 1, 0, 188, 18, 0, // Skip to: 86948 /* 82152 */ MCD_OPC_Decode, 166, 29, 255, 2, // Opcode: STRHpre /* 82157 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 82258 /* 82162 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 82165 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 82182 /* 82170 */ MCD_OPC_CheckField, 21, 1, 0, 163, 18, 0, // Skip to: 86948 /* 82177 */ MCD_OPC_Decode, 134, 19, 255, 2, // Opcode: LDURHi /* 82182 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 82199 /* 82187 */ MCD_OPC_CheckField, 21, 1, 0, 146, 18, 0, // Skip to: 86948 /* 82194 */ MCD_OPC_Decode, 240, 17, 255, 2, // Opcode: LDRHpost /* 82199 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 82241 /* 82204 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 82207 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 82224 /* 82212 */ MCD_OPC_CheckField, 21, 1, 1, 121, 18, 0, // Skip to: 86948 /* 82219 */ MCD_OPC_Decode, 242, 17, 239, 3, // Opcode: LDRHroW /* 82224 */ MCD_OPC_FilterValue, 3, 111, 18, 0, // Skip to: 86948 /* 82229 */ MCD_OPC_CheckField, 21, 1, 1, 104, 18, 0, // Skip to: 86948 /* 82236 */ MCD_OPC_Decode, 243, 17, 240, 3, // Opcode: LDRHroX /* 82241 */ MCD_OPC_FilterValue, 3, 94, 18, 0, // Skip to: 86948 /* 82246 */ MCD_OPC_CheckField, 21, 1, 0, 87, 18, 0, // Skip to: 86948 /* 82253 */ MCD_OPC_Decode, 241, 17, 255, 2, // Opcode: LDRHpre /* 82258 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 82268 /* 82263 */ MCD_OPC_Decode, 169, 29, 137, 3, // Opcode: STRHui /* 82268 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 82278 /* 82273 */ MCD_OPC_Decode, 244, 17, 137, 3, // Opcode: LDRHui /* 82278 */ MCD_OPC_FilterValue, 8, 109, 1, 0, // Skip to: 82648 /* 82283 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 82286 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 82308 /* 82291 */ MCD_OPC_CheckPredicate, 3, 44, 18, 0, // Skip to: 86948 /* 82296 */ MCD_OPC_CheckField, 21, 1, 1, 37, 18, 0, // Skip to: 86948 /* 82303 */ MCD_OPC_Decode, 215, 32, 208, 3, // Opcode: UQADDv1i8 /* 82308 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 82330 /* 82313 */ MCD_OPC_CheckPredicate, 3, 22, 18, 0, // Skip to: 86948 /* 82318 */ MCD_OPC_CheckField, 16, 6, 33, 15, 18, 0, // Skip to: 86948 /* 82325 */ MCD_OPC_Decode, 177, 26, 212, 3, // Opcode: SQXTUNv1i8 /* 82330 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 82352 /* 82335 */ MCD_OPC_CheckPredicate, 3, 0, 18, 0, // Skip to: 86948 /* 82340 */ MCD_OPC_CheckField, 21, 1, 1, 249, 17, 0, // Skip to: 86948 /* 82347 */ MCD_OPC_Decode, 201, 33, 208, 3, // Opcode: UQSUBv1i8 /* 82352 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 82374 /* 82357 */ MCD_OPC_CheckPredicate, 3, 234, 17, 0, // Skip to: 86948 /* 82362 */ MCD_OPC_CheckField, 16, 6, 32, 227, 17, 0, // Skip to: 86948 /* 82369 */ MCD_OPC_Decode, 149, 34, 209, 3, // Opcode: USQADDv1i8 /* 82374 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 82396 /* 82379 */ MCD_OPC_CheckPredicate, 3, 212, 17, 0, // Skip to: 86948 /* 82384 */ MCD_OPC_CheckField, 16, 6, 33, 205, 17, 0, // Skip to: 86948 /* 82391 */ MCD_OPC_Decode, 211, 33, 212, 3, // Opcode: UQXTNv1i8 /* 82396 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 82418 /* 82401 */ MCD_OPC_CheckPredicate, 3, 190, 17, 0, // Skip to: 86948 /* 82406 */ MCD_OPC_CheckField, 21, 1, 1, 183, 17, 0, // Skip to: 86948 /* 82413 */ MCD_OPC_Decode, 167, 33, 208, 3, // Opcode: UQSHLv1i8 /* 82418 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 82440 /* 82423 */ MCD_OPC_CheckPredicate, 3, 168, 17, 0, // Skip to: 86948 /* 82428 */ MCD_OPC_CheckField, 21, 1, 1, 161, 17, 0, // Skip to: 86948 /* 82435 */ MCD_OPC_Decode, 142, 33, 208, 3, // Opcode: UQRSHLv1i8 /* 82440 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 82462 /* 82445 */ MCD_OPC_CheckPredicate, 3, 146, 17, 0, // Skip to: 86948 /* 82450 */ MCD_OPC_CheckField, 16, 6, 32, 139, 17, 0, // Skip to: 86948 /* 82457 */ MCD_OPC_Decode, 151, 25, 213, 3, // Opcode: SQNEGv1i8 /* 82462 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 82484 /* 82467 */ MCD_OPC_CheckPredicate, 3, 124, 17, 0, // Skip to: 86948 /* 82472 */ MCD_OPC_CheckField, 16, 6, 33, 117, 17, 0, // Skip to: 86948 /* 82479 */ MCD_OPC_Decode, 174, 8, 167, 3, // Opcode: FCVTNUv1i32 /* 82484 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 82506 /* 82489 */ MCD_OPC_CheckPredicate, 3, 102, 17, 0, // Skip to: 86948 /* 82494 */ MCD_OPC_CheckField, 16, 6, 33, 95, 17, 0, // Skip to: 86948 /* 82501 */ MCD_OPC_Decode, 146, 8, 167, 3, // Opcode: FCVTMUv1i32 /* 82506 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 82544 /* 82511 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 82514 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82529 /* 82519 */ MCD_OPC_CheckPredicate, 3, 72, 17, 0, // Skip to: 86948 /* 82524 */ MCD_OPC_Decode, 238, 7, 167, 3, // Opcode: FCVTAUv1i32 /* 82529 */ MCD_OPC_FilterValue, 48, 62, 17, 0, // Skip to: 86948 /* 82534 */ MCD_OPC_CheckPredicate, 3, 57, 17, 0, // Skip to: 86948 /* 82539 */ MCD_OPC_Decode, 200, 9, 166, 2, // Opcode: FMAXNMPv2i32p /* 82544 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 82582 /* 82549 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 82552 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82567 /* 82557 */ MCD_OPC_CheckPredicate, 3, 34, 17, 0, // Skip to: 86948 /* 82562 */ MCD_OPC_Decode, 194, 31, 167, 3, // Opcode: UCVTFv1i32 /* 82567 */ MCD_OPC_FilterValue, 48, 24, 17, 0, // Skip to: 86948 /* 82572 */ MCD_OPC_CheckPredicate, 3, 19, 17, 0, // Skip to: 86948 /* 82577 */ MCD_OPC_Decode, 180, 6, 166, 2, // Opcode: FADDPv2i32p /* 82582 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 82604 /* 82587 */ MCD_OPC_CheckPredicate, 3, 4, 17, 0, // Skip to: 86948 /* 82592 */ MCD_OPC_CheckField, 21, 1, 1, 253, 16, 0, // Skip to: 86948 /* 82599 */ MCD_OPC_Decode, 240, 6, 172, 3, // Opcode: FCMGE32 /* 82604 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 82626 /* 82609 */ MCD_OPC_CheckPredicate, 3, 238, 16, 0, // Skip to: 86948 /* 82614 */ MCD_OPC_CheckField, 21, 1, 1, 231, 16, 0, // Skip to: 86948 /* 82621 */ MCD_OPC_Decode, 151, 6, 172, 3, // Opcode: FACGE32 /* 82626 */ MCD_OPC_FilterValue, 62, 221, 16, 0, // Skip to: 86948 /* 82631 */ MCD_OPC_CheckPredicate, 3, 216, 16, 0, // Skip to: 86948 /* 82636 */ MCD_OPC_CheckField, 16, 6, 48, 209, 16, 0, // Skip to: 86948 /* 82643 */ MCD_OPC_Decode, 226, 9, 166, 2, // Opcode: FMAXPv2i32p /* 82648 */ MCD_OPC_FilterValue, 9, 41, 2, 0, // Skip to: 83206 /* 82653 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 82656 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 82678 /* 82661 */ MCD_OPC_CheckPredicate, 3, 186, 16, 0, // Skip to: 86948 /* 82666 */ MCD_OPC_CheckField, 21, 1, 1, 179, 16, 0, // Skip to: 86948 /* 82673 */ MCD_OPC_Decode, 212, 32, 193, 3, // Opcode: UQADDv1i16 /* 82678 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 82700 /* 82683 */ MCD_OPC_CheckPredicate, 4, 164, 16, 0, // Skip to: 86948 /* 82688 */ MCD_OPC_CheckField, 21, 1, 0, 157, 16, 0, // Skip to: 86948 /* 82695 */ MCD_OPC_Decode, 239, 6, 193, 3, // Opcode: FCMGE16 /* 82700 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 82722 /* 82705 */ MCD_OPC_CheckPredicate, 3, 142, 16, 0, // Skip to: 86948 /* 82710 */ MCD_OPC_CheckField, 16, 6, 33, 135, 16, 0, // Skip to: 86948 /* 82717 */ MCD_OPC_Decode, 175, 26, 169, 3, // Opcode: SQXTUNv1i16 /* 82722 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 82760 /* 82727 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 82730 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 82745 /* 82735 */ MCD_OPC_CheckPredicate, 4, 112, 16, 0, // Skip to: 86948 /* 82740 */ MCD_OPC_Decode, 150, 6, 193, 3, // Opcode: FACGE16 /* 82745 */ MCD_OPC_FilterValue, 1, 102, 16, 0, // Skip to: 86948 /* 82750 */ MCD_OPC_CheckPredicate, 3, 97, 16, 0, // Skip to: 86948 /* 82755 */ MCD_OPC_Decode, 198, 33, 193, 3, // Opcode: UQSUBv1i16 /* 82760 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 82782 /* 82765 */ MCD_OPC_CheckPredicate, 3, 82, 16, 0, // Skip to: 86948 /* 82770 */ MCD_OPC_CheckField, 16, 6, 32, 75, 16, 0, // Skip to: 86948 /* 82777 */ MCD_OPC_Decode, 146, 34, 210, 3, // Opcode: USQADDv1i16 /* 82782 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 82804 /* 82787 */ MCD_OPC_CheckPredicate, 3, 60, 16, 0, // Skip to: 86948 /* 82792 */ MCD_OPC_CheckField, 16, 6, 33, 53, 16, 0, // Skip to: 86948 /* 82799 */ MCD_OPC_Decode, 209, 33, 169, 3, // Opcode: UQXTNv1i16 /* 82804 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 82826 /* 82809 */ MCD_OPC_CheckPredicate, 3, 38, 16, 0, // Skip to: 86948 /* 82814 */ MCD_OPC_CheckField, 21, 1, 1, 31, 16, 0, // Skip to: 86948 /* 82821 */ MCD_OPC_Decode, 164, 33, 193, 3, // Opcode: UQSHLv1i16 /* 82826 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 82848 /* 82831 */ MCD_OPC_CheckPredicate, 3, 16, 16, 0, // Skip to: 86948 /* 82836 */ MCD_OPC_CheckField, 21, 1, 1, 9, 16, 0, // Skip to: 86948 /* 82843 */ MCD_OPC_Decode, 139, 33, 193, 3, // Opcode: UQRSHLv1i16 /* 82848 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 82870 /* 82853 */ MCD_OPC_CheckPredicate, 3, 250, 15, 0, // Skip to: 86948 /* 82858 */ MCD_OPC_CheckField, 16, 6, 33, 243, 15, 0, // Skip to: 86948 /* 82865 */ MCD_OPC_Decode, 215, 8, 166, 2, // Opcode: FCVTXNv1i64 /* 82870 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 82892 /* 82875 */ MCD_OPC_CheckPredicate, 3, 228, 15, 0, // Skip to: 86948 /* 82880 */ MCD_OPC_CheckField, 16, 6, 32, 221, 15, 0, // Skip to: 86948 /* 82887 */ MCD_OPC_Decode, 148, 25, 188, 3, // Opcode: SQNEGv1i16 /* 82892 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 82914 /* 82897 */ MCD_OPC_CheckPredicate, 20, 206, 15, 0, // Skip to: 86948 /* 82902 */ MCD_OPC_CheckField, 21, 1, 0, 199, 15, 0, // Skip to: 86948 /* 82909 */ MCD_OPC_Decode, 160, 25, 241, 3, // Opcode: SQRDMLAHv1i16 /* 82914 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 82936 /* 82919 */ MCD_OPC_CheckPredicate, 20, 184, 15, 0, // Skip to: 86948 /* 82924 */ MCD_OPC_CheckField, 21, 1, 0, 177, 15, 0, // Skip to: 86948 /* 82931 */ MCD_OPC_Decode, 172, 25, 241, 3, // Opcode: SQRDMLSHv1i16 /* 82936 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 82974 /* 82941 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 82944 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82959 /* 82949 */ MCD_OPC_CheckPredicate, 3, 154, 15, 0, // Skip to: 86948 /* 82954 */ MCD_OPC_Decode, 175, 8, 239, 1, // Opcode: FCVTNUv1i64 /* 82959 */ MCD_OPC_FilterValue, 57, 144, 15, 0, // Skip to: 86948 /* 82964 */ MCD_OPC_CheckPredicate, 4, 139, 15, 0, // Skip to: 86948 /* 82969 */ MCD_OPC_Decode, 173, 8, 188, 3, // Opcode: FCVTNUv1f16 /* 82974 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 82996 /* 82979 */ MCD_OPC_CheckPredicate, 3, 124, 15, 0, // Skip to: 86948 /* 82984 */ MCD_OPC_CheckField, 21, 1, 1, 117, 15, 0, // Skip to: 86948 /* 82991 */ MCD_OPC_Decode, 182, 25, 193, 3, // Opcode: SQRDMULHv1i16 /* 82996 */ MCD_OPC_FilterValue, 46, 33, 0, 0, // Skip to: 83034 /* 83001 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 83004 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83019 /* 83009 */ MCD_OPC_CheckPredicate, 3, 94, 15, 0, // Skip to: 86948 /* 83014 */ MCD_OPC_Decode, 147, 8, 239, 1, // Opcode: FCVTMUv1i64 /* 83019 */ MCD_OPC_FilterValue, 57, 84, 15, 0, // Skip to: 86948 /* 83024 */ MCD_OPC_CheckPredicate, 4, 79, 15, 0, // Skip to: 86948 /* 83029 */ MCD_OPC_Decode, 145, 8, 188, 3, // Opcode: FCVTMUv1f16 /* 83034 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 83087 /* 83039 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 83042 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83057 /* 83047 */ MCD_OPC_CheckPredicate, 3, 56, 15, 0, // Skip to: 86948 /* 83052 */ MCD_OPC_Decode, 239, 7, 239, 1, // Opcode: FCVTAUv1i64 /* 83057 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 83072 /* 83062 */ MCD_OPC_CheckPredicate, 3, 41, 15, 0, // Skip to: 86948 /* 83067 */ MCD_OPC_Decode, 201, 9, 244, 1, // Opcode: FMAXNMPv2i64p /* 83072 */ MCD_OPC_FilterValue, 57, 31, 15, 0, // Skip to: 86948 /* 83077 */ MCD_OPC_CheckPredicate, 4, 26, 15, 0, // Skip to: 86948 /* 83082 */ MCD_OPC_Decode, 237, 7, 188, 3, // Opcode: FCVTAUv1f16 /* 83087 */ MCD_OPC_FilterValue, 54, 48, 0, 0, // Skip to: 83140 /* 83092 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 83095 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83110 /* 83100 */ MCD_OPC_CheckPredicate, 3, 3, 15, 0, // Skip to: 86948 /* 83105 */ MCD_OPC_Decode, 195, 31, 239, 1, // Opcode: UCVTFv1i64 /* 83110 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 83125 /* 83115 */ MCD_OPC_CheckPredicate, 3, 244, 14, 0, // Skip to: 86948 /* 83120 */ MCD_OPC_Decode, 181, 6, 244, 1, // Opcode: FADDPv2i64p /* 83125 */ MCD_OPC_FilterValue, 57, 234, 14, 0, // Skip to: 86948 /* 83130 */ MCD_OPC_CheckPredicate, 4, 229, 14, 0, // Skip to: 86948 /* 83135 */ MCD_OPC_Decode, 193, 31, 188, 3, // Opcode: UCVTFv1i16 /* 83140 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 83162 /* 83145 */ MCD_OPC_CheckPredicate, 3, 214, 14, 0, // Skip to: 86948 /* 83150 */ MCD_OPC_CheckField, 21, 1, 1, 207, 14, 0, // Skip to: 86948 /* 83157 */ MCD_OPC_Decode, 241, 6, 238, 1, // Opcode: FCMGE64 /* 83162 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 83184 /* 83167 */ MCD_OPC_CheckPredicate, 3, 192, 14, 0, // Skip to: 86948 /* 83172 */ MCD_OPC_CheckField, 21, 1, 1, 185, 14, 0, // Skip to: 86948 /* 83179 */ MCD_OPC_Decode, 152, 6, 238, 1, // Opcode: FACGE64 /* 83184 */ MCD_OPC_FilterValue, 62, 175, 14, 0, // Skip to: 86948 /* 83189 */ MCD_OPC_CheckPredicate, 3, 170, 14, 0, // Skip to: 86948 /* 83194 */ MCD_OPC_CheckField, 16, 6, 48, 163, 14, 0, // Skip to: 86948 /* 83201 */ MCD_OPC_Decode, 227, 9, 244, 1, // Opcode: FMAXPv2i64p /* 83206 */ MCD_OPC_FilterValue, 10, 197, 1, 0, // Skip to: 83664 /* 83211 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 83214 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 83236 /* 83219 */ MCD_OPC_CheckPredicate, 3, 140, 14, 0, // Skip to: 86948 /* 83224 */ MCD_OPC_CheckField, 21, 1, 1, 133, 14, 0, // Skip to: 86948 /* 83231 */ MCD_OPC_Decode, 213, 32, 172, 3, // Opcode: UQADDv1i32 /* 83236 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 83258 /* 83241 */ MCD_OPC_CheckPredicate, 3, 118, 14, 0, // Skip to: 86948 /* 83246 */ MCD_OPC_CheckField, 16, 6, 33, 111, 14, 0, // Skip to: 86948 /* 83253 */ MCD_OPC_Decode, 176, 26, 166, 2, // Opcode: SQXTUNv1i32 /* 83258 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 83280 /* 83263 */ MCD_OPC_CheckPredicate, 3, 96, 14, 0, // Skip to: 86948 /* 83268 */ MCD_OPC_CheckField, 21, 1, 1, 89, 14, 0, // Skip to: 86948 /* 83275 */ MCD_OPC_Decode, 199, 33, 172, 3, // Opcode: UQSUBv1i32 /* 83280 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 83302 /* 83285 */ MCD_OPC_CheckPredicate, 3, 74, 14, 0, // Skip to: 86948 /* 83290 */ MCD_OPC_CheckField, 16, 6, 32, 67, 14, 0, // Skip to: 86948 /* 83297 */ MCD_OPC_Decode, 147, 34, 211, 3, // Opcode: USQADDv1i32 /* 83302 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 83324 /* 83307 */ MCD_OPC_CheckPredicate, 3, 52, 14, 0, // Skip to: 86948 /* 83312 */ MCD_OPC_CheckField, 16, 6, 33, 45, 14, 0, // Skip to: 86948 /* 83319 */ MCD_OPC_Decode, 210, 33, 166, 2, // Opcode: UQXTNv1i32 /* 83324 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 83346 /* 83329 */ MCD_OPC_CheckPredicate, 3, 30, 14, 0, // Skip to: 86948 /* 83334 */ MCD_OPC_CheckField, 21, 1, 1, 23, 14, 0, // Skip to: 86948 /* 83341 */ MCD_OPC_Decode, 165, 33, 172, 3, // Opcode: UQSHLv1i32 /* 83346 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 83368 /* 83351 */ MCD_OPC_CheckPredicate, 3, 8, 14, 0, // Skip to: 86948 /* 83356 */ MCD_OPC_CheckField, 21, 1, 1, 1, 14, 0, // Skip to: 86948 /* 83363 */ MCD_OPC_Decode, 140, 33, 172, 3, // Opcode: UQRSHLv1i32 /* 83368 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 83390 /* 83373 */ MCD_OPC_CheckPredicate, 3, 242, 13, 0, // Skip to: 86948 /* 83378 */ MCD_OPC_CheckField, 16, 6, 32, 235, 13, 0, // Skip to: 86948 /* 83385 */ MCD_OPC_Decode, 149, 25, 167, 3, // Opcode: SQNEGv1i32 /* 83390 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 83412 /* 83395 */ MCD_OPC_CheckPredicate, 20, 220, 13, 0, // Skip to: 86948 /* 83400 */ MCD_OPC_CheckField, 21, 1, 0, 213, 13, 0, // Skip to: 86948 /* 83407 */ MCD_OPC_Decode, 161, 25, 242, 3, // Opcode: SQRDMLAHv1i32 /* 83412 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 83434 /* 83417 */ MCD_OPC_CheckPredicate, 20, 198, 13, 0, // Skip to: 86948 /* 83422 */ MCD_OPC_CheckField, 21, 1, 0, 191, 13, 0, // Skip to: 86948 /* 83429 */ MCD_OPC_Decode, 173, 25, 242, 3, // Opcode: SQRDMLSHv1i32 /* 83434 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 83456 /* 83439 */ MCD_OPC_CheckPredicate, 3, 176, 13, 0, // Skip to: 86948 /* 83444 */ MCD_OPC_CheckField, 16, 6, 33, 169, 13, 0, // Skip to: 86948 /* 83451 */ MCD_OPC_Decode, 206, 8, 167, 3, // Opcode: FCVTPUv1i32 /* 83456 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 83478 /* 83461 */ MCD_OPC_CheckPredicate, 3, 154, 13, 0, // Skip to: 86948 /* 83466 */ MCD_OPC_CheckField, 21, 1, 1, 147, 13, 0, // Skip to: 86948 /* 83473 */ MCD_OPC_Decode, 184, 25, 172, 3, // Opcode: SQRDMULHv1i32 /* 83478 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 83500 /* 83483 */ MCD_OPC_CheckPredicate, 3, 132, 13, 0, // Skip to: 86948 /* 83488 */ MCD_OPC_CheckField, 16, 6, 33, 125, 13, 0, // Skip to: 86948 /* 83495 */ MCD_OPC_Decode, 148, 9, 167, 3, // Opcode: FCVTZUv1i32 /* 83500 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 83538 /* 83505 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 83508 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 83523 /* 83513 */ MCD_OPC_CheckPredicate, 3, 102, 13, 0, // Skip to: 86948 /* 83518 */ MCD_OPC_Decode, 249, 6, 167, 3, // Opcode: FCMGEv1i32rz /* 83523 */ MCD_OPC_FilterValue, 48, 92, 13, 0, // Skip to: 86948 /* 83528 */ MCD_OPC_CheckPredicate, 3, 87, 13, 0, // Skip to: 86948 /* 83533 */ MCD_OPC_Decode, 128, 10, 166, 2, // Opcode: FMINNMPv2i32p /* 83538 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 83560 /* 83543 */ MCD_OPC_CheckPredicate, 3, 72, 13, 0, // Skip to: 86948 /* 83548 */ MCD_OPC_CheckField, 21, 1, 1, 65, 13, 0, // Skip to: 86948 /* 83555 */ MCD_OPC_Decode, 129, 6, 172, 3, // Opcode: FABD32 /* 83560 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 83598 /* 83565 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 83568 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 83583 /* 83573 */ MCD_OPC_CheckPredicate, 3, 42, 13, 0, // Skip to: 86948 /* 83578 */ MCD_OPC_Decode, 172, 7, 167, 3, // Opcode: FCMLEv1i32rz /* 83583 */ MCD_OPC_FilterValue, 33, 32, 13, 0, // Skip to: 86948 /* 83588 */ MCD_OPC_CheckPredicate, 3, 27, 13, 0, // Skip to: 86948 /* 83593 */ MCD_OPC_Decode, 177, 12, 167, 3, // Opcode: FRSQRTEv1i32 /* 83598 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 83620 /* 83603 */ MCD_OPC_CheckPredicate, 3, 12, 13, 0, // Skip to: 86948 /* 83608 */ MCD_OPC_CheckField, 21, 1, 1, 5, 13, 0, // Skip to: 86948 /* 83615 */ MCD_OPC_Decode, 134, 7, 172, 3, // Opcode: FCMGT32 /* 83620 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 83642 /* 83625 */ MCD_OPC_CheckPredicate, 3, 246, 12, 0, // Skip to: 86948 /* 83630 */ MCD_OPC_CheckField, 21, 1, 1, 239, 12, 0, // Skip to: 86948 /* 83637 */ MCD_OPC_Decode, 162, 6, 172, 3, // Opcode: FACGT32 /* 83642 */ MCD_OPC_FilterValue, 62, 229, 12, 0, // Skip to: 86948 /* 83647 */ MCD_OPC_CheckPredicate, 3, 224, 12, 0, // Skip to: 86948 /* 83652 */ MCD_OPC_CheckField, 16, 6, 48, 217, 12, 0, // Skip to: 86948 /* 83659 */ MCD_OPC_Decode, 154, 10, 166, 2, // Opcode: FMINPv2i32p /* 83664 */ MCD_OPC_FilterValue, 11, 159, 2, 0, // Skip to: 84340 /* 83669 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 83672 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 83694 /* 83677 */ MCD_OPC_CheckPredicate, 3, 194, 12, 0, // Skip to: 86948 /* 83682 */ MCD_OPC_CheckField, 21, 1, 1, 187, 12, 0, // Skip to: 86948 /* 83689 */ MCD_OPC_Decode, 214, 32, 238, 1, // Opcode: UQADDv1i64 /* 83694 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 83716 /* 83699 */ MCD_OPC_CheckPredicate, 4, 172, 12, 0, // Skip to: 86948 /* 83704 */ MCD_OPC_CheckField, 21, 1, 0, 165, 12, 0, // Skip to: 86948 /* 83711 */ MCD_OPC_Decode, 128, 6, 193, 3, // Opcode: FABD16 /* 83716 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 83738 /* 83721 */ MCD_OPC_CheckPredicate, 4, 150, 12, 0, // Skip to: 86948 /* 83726 */ MCD_OPC_CheckField, 21, 1, 0, 143, 12, 0, // Skip to: 86948 /* 83733 */ MCD_OPC_Decode, 133, 7, 193, 3, // Opcode: FCMGT16 /* 83738 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 83776 /* 83743 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 83746 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 83761 /* 83751 */ MCD_OPC_CheckPredicate, 4, 120, 12, 0, // Skip to: 86948 /* 83756 */ MCD_OPC_Decode, 161, 6, 193, 3, // Opcode: FACGT16 /* 83761 */ MCD_OPC_FilterValue, 1, 110, 12, 0, // Skip to: 86948 /* 83766 */ MCD_OPC_CheckPredicate, 3, 105, 12, 0, // Skip to: 86948 /* 83771 */ MCD_OPC_Decode, 200, 33, 238, 1, // Opcode: UQSUBv1i64 /* 83776 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 83798 /* 83781 */ MCD_OPC_CheckPredicate, 3, 90, 12, 0, // Skip to: 86948 /* 83786 */ MCD_OPC_CheckField, 21, 1, 1, 83, 12, 0, // Skip to: 86948 /* 83793 */ MCD_OPC_Decode, 231, 3, 238, 1, // Opcode: CMHIv1i64 /* 83798 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 83820 /* 83803 */ MCD_OPC_CheckPredicate, 3, 68, 12, 0, // Skip to: 86948 /* 83808 */ MCD_OPC_CheckField, 16, 6, 32, 61, 12, 0, // Skip to: 86948 /* 83815 */ MCD_OPC_Decode, 148, 34, 248, 1, // Opcode: USQADDv1i64 /* 83820 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 83842 /* 83825 */ MCD_OPC_CheckPredicate, 3, 46, 12, 0, // Skip to: 86948 /* 83830 */ MCD_OPC_CheckField, 21, 1, 1, 39, 12, 0, // Skip to: 86948 /* 83837 */ MCD_OPC_Decode, 239, 3, 238, 1, // Opcode: CMHSv1i64 /* 83842 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 83864 /* 83847 */ MCD_OPC_CheckPredicate, 3, 24, 12, 0, // Skip to: 86948 /* 83852 */ MCD_OPC_CheckField, 21, 1, 1, 17, 12, 0, // Skip to: 86948 /* 83859 */ MCD_OPC_Decode, 130, 34, 238, 1, // Opcode: USHLv1i64 /* 83864 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 83886 /* 83869 */ MCD_OPC_CheckPredicate, 3, 2, 12, 0, // Skip to: 86948 /* 83874 */ MCD_OPC_CheckField, 21, 1, 1, 251, 11, 0, // Skip to: 86948 /* 83881 */ MCD_OPC_Decode, 166, 33, 238, 1, // Opcode: UQSHLv1i64 /* 83886 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 83908 /* 83891 */ MCD_OPC_CheckPredicate, 3, 236, 11, 0, // Skip to: 86948 /* 83896 */ MCD_OPC_CheckField, 21, 1, 1, 229, 11, 0, // Skip to: 86948 /* 83903 */ MCD_OPC_Decode, 226, 33, 238, 1, // Opcode: URSHLv1i64 /* 83908 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 83930 /* 83913 */ MCD_OPC_CheckPredicate, 3, 214, 11, 0, // Skip to: 86948 /* 83918 */ MCD_OPC_CheckField, 21, 1, 1, 207, 11, 0, // Skip to: 86948 /* 83925 */ MCD_OPC_Decode, 141, 33, 238, 1, // Opcode: UQRSHLv1i64 /* 83930 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 83952 /* 83935 */ MCD_OPC_CheckPredicate, 3, 192, 11, 0, // Skip to: 86948 /* 83940 */ MCD_OPC_CheckField, 16, 6, 32, 185, 11, 0, // Skip to: 86948 /* 83947 */ MCD_OPC_Decode, 150, 25, 239, 1, // Opcode: SQNEGv1i64 /* 83952 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 83974 /* 83957 */ MCD_OPC_CheckPredicate, 3, 170, 11, 0, // Skip to: 86948 /* 83962 */ MCD_OPC_CheckField, 21, 1, 1, 163, 11, 0, // Skip to: 86948 /* 83969 */ MCD_OPC_Decode, 128, 30, 238, 1, // Opcode: SUBv1i64 /* 83974 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 83996 /* 83979 */ MCD_OPC_CheckPredicate, 3, 148, 11, 0, // Skip to: 86948 /* 83984 */ MCD_OPC_CheckField, 16, 6, 32, 141, 11, 0, // Skip to: 86948 /* 83991 */ MCD_OPC_Decode, 201, 3, 239, 1, // Opcode: CMGEv1i64rz /* 83996 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 84018 /* 84001 */ MCD_OPC_CheckPredicate, 3, 126, 11, 0, // Skip to: 86948 /* 84006 */ MCD_OPC_CheckField, 21, 1, 1, 119, 11, 0, // Skip to: 86948 /* 84013 */ MCD_OPC_Decode, 184, 3, 238, 1, // Opcode: CMEQv1i64 /* 84018 */ MCD_OPC_FilterValue, 38, 17, 0, 0, // Skip to: 84040 /* 84023 */ MCD_OPC_CheckPredicate, 3, 104, 11, 0, // Skip to: 86948 /* 84028 */ MCD_OPC_CheckField, 16, 6, 32, 97, 11, 0, // Skip to: 86948 /* 84035 */ MCD_OPC_Decode, 247, 3, 239, 1, // Opcode: CMLEv1i64rz /* 84040 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 84078 /* 84045 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 84048 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84063 /* 84053 */ MCD_OPC_CheckPredicate, 3, 74, 11, 0, // Skip to: 86948 /* 84058 */ MCD_OPC_Decode, 207, 8, 239, 1, // Opcode: FCVTPUv1i64 /* 84063 */ MCD_OPC_FilterValue, 57, 64, 11, 0, // Skip to: 86948 /* 84068 */ MCD_OPC_CheckPredicate, 4, 59, 11, 0, // Skip to: 86948 /* 84073 */ MCD_OPC_Decode, 205, 8, 188, 3, // Opcode: FCVTPUv1f16 /* 84078 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 84131 /* 84083 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 84086 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84101 /* 84091 */ MCD_OPC_CheckPredicate, 3, 36, 11, 0, // Skip to: 86948 /* 84096 */ MCD_OPC_Decode, 180, 20, 239, 1, // Opcode: NEGv1i64 /* 84101 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84116 /* 84106 */ MCD_OPC_CheckPredicate, 3, 21, 11, 0, // Skip to: 86948 /* 84111 */ MCD_OPC_Decode, 149, 9, 239, 1, // Opcode: FCVTZUv1i64 /* 84116 */ MCD_OPC_FilterValue, 57, 11, 11, 0, // Skip to: 86948 /* 84121 */ MCD_OPC_CheckPredicate, 4, 6, 11, 0, // Skip to: 86948 /* 84126 */ MCD_OPC_Decode, 147, 9, 188, 3, // Opcode: FCVTZUv1f16 /* 84131 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 84184 /* 84136 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 84139 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84154 /* 84144 */ MCD_OPC_CheckPredicate, 3, 239, 10, 0, // Skip to: 86948 /* 84149 */ MCD_OPC_Decode, 250, 6, 239, 1, // Opcode: FCMGEv1i64rz /* 84154 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 84169 /* 84159 */ MCD_OPC_CheckPredicate, 3, 224, 10, 0, // Skip to: 86948 /* 84164 */ MCD_OPC_Decode, 129, 10, 244, 1, // Opcode: FMINNMPv2i64p /* 84169 */ MCD_OPC_FilterValue, 56, 214, 10, 0, // Skip to: 86948 /* 84174 */ MCD_OPC_CheckPredicate, 4, 209, 10, 0, // Skip to: 86948 /* 84179 */ MCD_OPC_Decode, 248, 6, 188, 3, // Opcode: FCMGEv1i16rz /* 84184 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 84206 /* 84189 */ MCD_OPC_CheckPredicate, 3, 194, 10, 0, // Skip to: 86948 /* 84194 */ MCD_OPC_CheckField, 21, 1, 1, 187, 10, 0, // Skip to: 86948 /* 84201 */ MCD_OPC_Decode, 130, 6, 238, 1, // Opcode: FABD64 /* 84206 */ MCD_OPC_FilterValue, 54, 63, 0, 0, // Skip to: 84274 /* 84211 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 84214 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84229 /* 84219 */ MCD_OPC_CheckPredicate, 3, 164, 10, 0, // Skip to: 86948 /* 84224 */ MCD_OPC_Decode, 173, 7, 239, 1, // Opcode: FCMLEv1i64rz /* 84229 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84244 /* 84234 */ MCD_OPC_CheckPredicate, 3, 149, 10, 0, // Skip to: 86948 /* 84239 */ MCD_OPC_Decode, 178, 12, 239, 1, // Opcode: FRSQRTEv1i64 /* 84244 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 84259 /* 84249 */ MCD_OPC_CheckPredicate, 4, 134, 10, 0, // Skip to: 86948 /* 84254 */ MCD_OPC_Decode, 171, 7, 188, 3, // Opcode: FCMLEv1i16rz /* 84259 */ MCD_OPC_FilterValue, 57, 124, 10, 0, // Skip to: 86948 /* 84264 */ MCD_OPC_CheckPredicate, 4, 119, 10, 0, // Skip to: 86948 /* 84269 */ MCD_OPC_Decode, 176, 12, 188, 3, // Opcode: FRSQRTEv1f16 /* 84274 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 84296 /* 84279 */ MCD_OPC_CheckPredicate, 3, 104, 10, 0, // Skip to: 86948 /* 84284 */ MCD_OPC_CheckField, 21, 1, 1, 97, 10, 0, // Skip to: 86948 /* 84291 */ MCD_OPC_Decode, 135, 7, 238, 1, // Opcode: FCMGT64 /* 84296 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 84318 /* 84301 */ MCD_OPC_CheckPredicate, 3, 82, 10, 0, // Skip to: 86948 /* 84306 */ MCD_OPC_CheckField, 21, 1, 1, 75, 10, 0, // Skip to: 86948 /* 84313 */ MCD_OPC_Decode, 163, 6, 238, 1, // Opcode: FACGT64 /* 84318 */ MCD_OPC_FilterValue, 62, 65, 10, 0, // Skip to: 86948 /* 84323 */ MCD_OPC_CheckPredicate, 3, 60, 10, 0, // Skip to: 86948 /* 84328 */ MCD_OPC_CheckField, 16, 6, 48, 53, 10, 0, // Skip to: 86948 /* 84335 */ MCD_OPC_Decode, 155, 10, 244, 1, // Opcode: FMINPv2i64p /* 84340 */ MCD_OPC_FilterValue, 12, 98, 2, 0, // Skip to: 84955 /* 84345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 84348 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 84437 /* 84353 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84356 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 84415 /* 84361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 84364 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84393 /* 84369 */ MCD_OPC_CheckPredicate, 3, 14, 10, 0, // Skip to: 86948 /* 84374 */ MCD_OPC_CheckField, 19, 1, 1, 7, 10, 0, // Skip to: 86948 /* 84381 */ MCD_OPC_CheckField, 10, 2, 1, 0, 10, 0, // Skip to: 86948 /* 84388 */ MCD_OPC_Decode, 223, 25, 226, 3, // Opcode: SQSHLUb /* 84393 */ MCD_OPC_FilterValue, 1, 246, 9, 0, // Skip to: 86948 /* 84398 */ MCD_OPC_CheckPredicate, 3, 241, 9, 0, // Skip to: 86948 /* 84403 */ MCD_OPC_CheckField, 10, 2, 1, 234, 9, 0, // Skip to: 86948 /* 84410 */ MCD_OPC_Decode, 225, 25, 227, 3, // Opcode: SQSHLUh /* 84415 */ MCD_OPC_FilterValue, 1, 224, 9, 0, // Skip to: 86948 /* 84420 */ MCD_OPC_CheckPredicate, 3, 219, 9, 0, // Skip to: 86948 /* 84425 */ MCD_OPC_CheckField, 10, 2, 1, 212, 9, 0, // Skip to: 86948 /* 84432 */ MCD_OPC_Decode, 226, 25, 228, 3, // Opcode: SQSHLUs /* 84437 */ MCD_OPC_FilterValue, 7, 84, 0, 0, // Skip to: 84526 /* 84442 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84445 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 84504 /* 84450 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 84453 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84482 /* 84458 */ MCD_OPC_CheckPredicate, 3, 181, 9, 0, // Skip to: 86948 /* 84463 */ MCD_OPC_CheckField, 19, 1, 1, 174, 9, 0, // Skip to: 86948 /* 84470 */ MCD_OPC_CheckField, 10, 2, 1, 167, 9, 0, // Skip to: 86948 /* 84477 */ MCD_OPC_Decode, 158, 33, 226, 3, // Opcode: UQSHLb /* 84482 */ MCD_OPC_FilterValue, 1, 157, 9, 0, // Skip to: 86948 /* 84487 */ MCD_OPC_CheckPredicate, 3, 152, 9, 0, // Skip to: 86948 /* 84492 */ MCD_OPC_CheckField, 10, 2, 1, 145, 9, 0, // Skip to: 86948 /* 84499 */ MCD_OPC_Decode, 160, 33, 227, 3, // Opcode: UQSHLh /* 84504 */ MCD_OPC_FilterValue, 1, 135, 9, 0, // Skip to: 86948 /* 84509 */ MCD_OPC_CheckPredicate, 3, 130, 9, 0, // Skip to: 86948 /* 84514 */ MCD_OPC_CheckField, 10, 2, 1, 123, 9, 0, // Skip to: 86948 /* 84521 */ MCD_OPC_Decode, 161, 33, 228, 3, // Opcode: UQSHLs /* 84526 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 84670 /* 84531 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 84534 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 84602 /* 84539 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84542 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84587 /* 84547 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 84550 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84572 /* 84555 */ MCD_OPC_CheckPredicate, 3, 84, 9, 0, // Skip to: 86948 /* 84560 */ MCD_OPC_CheckField, 19, 1, 1, 77, 9, 0, // Skip to: 86948 /* 84567 */ MCD_OPC_Decode, 137, 26, 230, 3, // Opcode: SQSHRUNb /* 84572 */ MCD_OPC_FilterValue, 1, 67, 9, 0, // Skip to: 86948 /* 84577 */ MCD_OPC_CheckPredicate, 3, 62, 9, 0, // Skip to: 86948 /* 84582 */ MCD_OPC_Decode, 138, 26, 231, 3, // Opcode: SQSHRUNh /* 84587 */ MCD_OPC_FilterValue, 1, 52, 9, 0, // Skip to: 86948 /* 84592 */ MCD_OPC_CheckPredicate, 3, 47, 9, 0, // Skip to: 86948 /* 84597 */ MCD_OPC_Decode, 139, 26, 232, 3, // Opcode: SQSHRUNs /* 84602 */ MCD_OPC_FilterValue, 3, 37, 9, 0, // Skip to: 86948 /* 84607 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84610 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84655 /* 84615 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 84618 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84640 /* 84623 */ MCD_OPC_CheckPredicate, 3, 16, 9, 0, // Skip to: 86948 /* 84628 */ MCD_OPC_CheckField, 19, 1, 1, 9, 9, 0, // Skip to: 86948 /* 84635 */ MCD_OPC_Decode, 214, 25, 230, 3, // Opcode: SQRSHRUNb /* 84640 */ MCD_OPC_FilterValue, 1, 255, 8, 0, // Skip to: 86948 /* 84645 */ MCD_OPC_CheckPredicate, 3, 250, 8, 0, // Skip to: 86948 /* 84650 */ MCD_OPC_Decode, 215, 25, 231, 3, // Opcode: SQRSHRUNh /* 84655 */ MCD_OPC_FilterValue, 1, 240, 8, 0, // Skip to: 86948 /* 84660 */ MCD_OPC_CheckPredicate, 3, 235, 8, 0, // Skip to: 86948 /* 84665 */ MCD_OPC_Decode, 216, 25, 232, 3, // Opcode: SQRSHRUNs /* 84670 */ MCD_OPC_FilterValue, 9, 162, 0, 0, // Skip to: 84837 /* 84675 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 84678 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 84693 /* 84683 */ MCD_OPC_CheckPredicate, 4, 212, 8, 0, // Skip to: 86948 /* 84688 */ MCD_OPC_Decode, 254, 10, 229, 3, // Opcode: FMULXv1i16_indexed /* 84693 */ MCD_OPC_FilterValue, 1, 202, 8, 0, // Skip to: 86948 /* 84698 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 84701 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 84769 /* 84706 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84709 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84754 /* 84714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 84717 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84739 /* 84722 */ MCD_OPC_CheckPredicate, 3, 173, 8, 0, // Skip to: 86948 /* 84727 */ MCD_OPC_CheckField, 19, 1, 1, 166, 8, 0, // Skip to: 86948 /* 84734 */ MCD_OPC_Decode, 180, 33, 230, 3, // Opcode: UQSHRNb /* 84739 */ MCD_OPC_FilterValue, 1, 156, 8, 0, // Skip to: 86948 /* 84744 */ MCD_OPC_CheckPredicate, 3, 151, 8, 0, // Skip to: 86948 /* 84749 */ MCD_OPC_Decode, 181, 33, 231, 3, // Opcode: UQSHRNh /* 84754 */ MCD_OPC_FilterValue, 1, 141, 8, 0, // Skip to: 86948 /* 84759 */ MCD_OPC_CheckPredicate, 3, 136, 8, 0, // Skip to: 86948 /* 84764 */ MCD_OPC_Decode, 182, 33, 232, 3, // Opcode: UQSHRNs /* 84769 */ MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 86948 /* 84774 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84777 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84822 /* 84782 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 84785 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84807 /* 84790 */ MCD_OPC_CheckPredicate, 3, 105, 8, 0, // Skip to: 86948 /* 84795 */ MCD_OPC_CheckField, 19, 1, 1, 98, 8, 0, // Skip to: 86948 /* 84802 */ MCD_OPC_Decode, 149, 33, 230, 3, // Opcode: UQRSHRNb /* 84807 */ MCD_OPC_FilterValue, 1, 88, 8, 0, // Skip to: 86948 /* 84812 */ MCD_OPC_CheckPredicate, 3, 83, 8, 0, // Skip to: 86948 /* 84817 */ MCD_OPC_Decode, 150, 33, 231, 3, // Opcode: UQRSHRNh /* 84822 */ MCD_OPC_FilterValue, 1, 73, 8, 0, // Skip to: 86948 /* 84827 */ MCD_OPC_CheckPredicate, 3, 68, 8, 0, // Skip to: 86948 /* 84832 */ MCD_OPC_Decode, 151, 33, 232, 3, // Opcode: UQRSHRNs /* 84837 */ MCD_OPC_FilterValue, 14, 54, 0, 0, // Skip to: 84896 /* 84842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84845 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84874 /* 84850 */ MCD_OPC_CheckPredicate, 4, 45, 8, 0, // Skip to: 86948 /* 84855 */ MCD_OPC_CheckField, 20, 1, 1, 38, 8, 0, // Skip to: 86948 /* 84862 */ MCD_OPC_CheckField, 10, 2, 1, 31, 8, 0, // Skip to: 86948 /* 84869 */ MCD_OPC_Decode, 191, 31, 237, 3, // Opcode: UCVTFh /* 84874 */ MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 86948 /* 84879 */ MCD_OPC_CheckPredicate, 3, 16, 8, 0, // Skip to: 86948 /* 84884 */ MCD_OPC_CheckField, 10, 2, 1, 9, 8, 0, // Skip to: 86948 /* 84891 */ MCD_OPC_Decode, 192, 31, 238, 3, // Opcode: UCVTFs /* 84896 */ MCD_OPC_FilterValue, 15, 255, 7, 0, // Skip to: 86948 /* 84901 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 84904 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84933 /* 84909 */ MCD_OPC_CheckPredicate, 4, 242, 7, 0, // Skip to: 86948 /* 84914 */ MCD_OPC_CheckField, 20, 1, 1, 235, 7, 0, // Skip to: 86948 /* 84921 */ MCD_OPC_CheckField, 10, 2, 3, 228, 7, 0, // Skip to: 86948 /* 84928 */ MCD_OPC_Decode, 145, 9, 237, 3, // Opcode: FCVTZUh /* 84933 */ MCD_OPC_FilterValue, 1, 218, 7, 0, // Skip to: 86948 /* 84938 */ MCD_OPC_CheckPredicate, 3, 213, 7, 0, // Skip to: 86948 /* 84943 */ MCD_OPC_CheckField, 10, 2, 3, 206, 7, 0, // Skip to: 86948 /* 84950 */ MCD_OPC_Decode, 146, 9, 238, 3, // Opcode: FCVTZUs /* 84955 */ MCD_OPC_FilterValue, 13, 12, 1, 0, // Skip to: 85228 /* 84960 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 84963 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84985 /* 84968 */ MCD_OPC_CheckPredicate, 3, 183, 7, 0, // Skip to: 86948 /* 84973 */ MCD_OPC_CheckField, 10, 2, 1, 176, 7, 0, // Skip to: 86948 /* 84980 */ MCD_OPC_Decode, 137, 34, 218, 3, // Opcode: USHRd /* 84985 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 85007 /* 84990 */ MCD_OPC_CheckPredicate, 3, 161, 7, 0, // Skip to: 86948 /* 84995 */ MCD_OPC_CheckField, 10, 2, 1, 154, 7, 0, // Skip to: 86948 /* 85002 */ MCD_OPC_Decode, 156, 34, 220, 3, // Opcode: USRAd /* 85007 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 85029 /* 85012 */ MCD_OPC_CheckPredicate, 3, 139, 7, 0, // Skip to: 86948 /* 85017 */ MCD_OPC_CheckField, 10, 2, 1, 132, 7, 0, // Skip to: 86948 /* 85024 */ MCD_OPC_Decode, 233, 33, 218, 3, // Opcode: URSHRd /* 85029 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 85051 /* 85034 */ MCD_OPC_CheckPredicate, 3, 117, 7, 0, // Skip to: 86948 /* 85039 */ MCD_OPC_CheckField, 10, 2, 1, 110, 7, 0, // Skip to: 86948 /* 85046 */ MCD_OPC_Decode, 243, 33, 220, 3, // Opcode: URSRAd /* 85051 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 85073 /* 85056 */ MCD_OPC_CheckPredicate, 3, 95, 7, 0, // Skip to: 86948 /* 85061 */ MCD_OPC_CheckField, 10, 2, 1, 88, 7, 0, // Skip to: 86948 /* 85068 */ MCD_OPC_Decode, 189, 26, 220, 3, // Opcode: SRId /* 85073 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 85095 /* 85078 */ MCD_OPC_CheckPredicate, 3, 73, 7, 0, // Skip to: 86948 /* 85083 */ MCD_OPC_CheckField, 10, 2, 1, 66, 7, 0, // Skip to: 86948 /* 85090 */ MCD_OPC_Decode, 159, 23, 243, 3, // Opcode: SLId /* 85095 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 85117 /* 85100 */ MCD_OPC_CheckPredicate, 3, 51, 7, 0, // Skip to: 86948 /* 85105 */ MCD_OPC_CheckField, 10, 2, 1, 44, 7, 0, // Skip to: 86948 /* 85112 */ MCD_OPC_Decode, 224, 25, 225, 3, // Opcode: SQSHLUd /* 85117 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 85139 /* 85122 */ MCD_OPC_CheckPredicate, 3, 29, 7, 0, // Skip to: 86948 /* 85127 */ MCD_OPC_CheckField, 10, 2, 1, 22, 7, 0, // Skip to: 86948 /* 85134 */ MCD_OPC_Decode, 159, 33, 225, 3, // Opcode: UQSHLd /* 85139 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 85161 /* 85144 */ MCD_OPC_CheckPredicate, 7, 7, 7, 0, // Skip to: 86948 /* 85149 */ MCD_OPC_CheckField, 10, 1, 0, 0, 7, 0, // Skip to: 86948 /* 85156 */ MCD_OPC_Decode, 158, 25, 219, 3, // Opcode: SQRDMLAHi16_indexed /* 85161 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 85183 /* 85166 */ MCD_OPC_CheckPredicate, 3, 241, 6, 0, // Skip to: 86948 /* 85171 */ MCD_OPC_CheckField, 10, 2, 1, 234, 6, 0, // Skip to: 86948 /* 85178 */ MCD_OPC_Decode, 190, 31, 218, 3, // Opcode: UCVTFd /* 85183 */ MCD_OPC_FilterValue, 15, 224, 6, 0, // Skip to: 86948 /* 85188 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 85191 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 85206 /* 85196 */ MCD_OPC_CheckPredicate, 7, 211, 6, 0, // Skip to: 86948 /* 85201 */ MCD_OPC_Decode, 170, 25, 219, 3, // Opcode: SQRDMLSHi16_indexed /* 85206 */ MCD_OPC_FilterValue, 1, 201, 6, 0, // Skip to: 86948 /* 85211 */ MCD_OPC_CheckPredicate, 3, 196, 6, 0, // Skip to: 86948 /* 85216 */ MCD_OPC_CheckField, 11, 1, 1, 189, 6, 0, // Skip to: 86948 /* 85223 */ MCD_OPC_Decode, 144, 9, 218, 3, // Opcode: FCVTZUd /* 85228 */ MCD_OPC_FilterValue, 14, 69, 0, 0, // Skip to: 85302 /* 85233 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 85236 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 85258 /* 85241 */ MCD_OPC_CheckPredicate, 3, 166, 6, 0, // Skip to: 86948 /* 85246 */ MCD_OPC_CheckField, 10, 1, 0, 159, 6, 0, // Skip to: 86948 /* 85253 */ MCD_OPC_Decode, 255, 10, 233, 3, // Opcode: FMULXv1i32_indexed /* 85258 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 85280 /* 85263 */ MCD_OPC_CheckPredicate, 7, 144, 6, 0, // Skip to: 86948 /* 85268 */ MCD_OPC_CheckField, 10, 1, 0, 137, 6, 0, // Skip to: 86948 /* 85275 */ MCD_OPC_Decode, 159, 25, 221, 3, // Opcode: SQRDMLAHi32_indexed /* 85280 */ MCD_OPC_FilterValue, 15, 127, 6, 0, // Skip to: 86948 /* 85285 */ MCD_OPC_CheckPredicate, 7, 122, 6, 0, // Skip to: 86948 /* 85290 */ MCD_OPC_CheckField, 10, 1, 0, 115, 6, 0, // Skip to: 86948 /* 85297 */ MCD_OPC_Decode, 171, 25, 221, 3, // Opcode: SQRDMLSHi32_indexed /* 85302 */ MCD_OPC_FilterValue, 15, 105, 6, 0, // Skip to: 86948 /* 85307 */ MCD_OPC_CheckPredicate, 3, 100, 6, 0, // Skip to: 86948 /* 85312 */ MCD_OPC_CheckField, 21, 1, 0, 93, 6, 0, // Skip to: 86948 /* 85319 */ MCD_OPC_CheckField, 12, 4, 9, 86, 6, 0, // Skip to: 86948 /* 85326 */ MCD_OPC_CheckField, 10, 1, 0, 79, 6, 0, // Skip to: 86948 /* 85333 */ MCD_OPC_Decode, 128, 11, 234, 3, // Opcode: FMULXv1i64_indexed /* 85338 */ MCD_OPC_FilterValue, 4, 121, 4, 0, // Skip to: 86488 /* 85343 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 85346 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 85356 /* 85351 */ MCD_OPC_Decode, 245, 17, 244, 3, // Opcode: LDRQl /* 85356 */ MCD_OPC_FilterValue, 2, 51, 6, 0, // Skip to: 86948 /* 85361 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 85364 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 85379 /* 85369 */ MCD_OPC_CheckPredicate, 16, 38, 6, 0, // Skip to: 86948 /* 85374 */ MCD_OPC_Decode, 189, 22, 245, 3, // Opcode: SCVTFSXSri /* 85379 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 85394 /* 85384 */ MCD_OPC_CheckPredicate, 16, 23, 6, 0, // Skip to: 86948 /* 85389 */ MCD_OPC_Decode, 176, 31, 245, 3, // Opcode: UCVTFSXSri /* 85394 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 85409 /* 85399 */ MCD_OPC_CheckPredicate, 16, 8, 6, 0, // Skip to: 86948 /* 85404 */ MCD_OPC_Decode, 223, 8, 246, 3, // Opcode: FCVTZSSXSri /* 85409 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 85424 /* 85414 */ MCD_OPC_CheckPredicate, 16, 249, 5, 0, // Skip to: 86948 /* 85419 */ MCD_OPC_Decode, 130, 9, 246, 3, // Opcode: FCVTZUSXSri /* 85424 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 85446 /* 85429 */ MCD_OPC_CheckPredicate, 16, 234, 5, 0, // Skip to: 86948 /* 85434 */ MCD_OPC_CheckField, 10, 6, 0, 227, 5, 0, // Skip to: 86948 /* 85441 */ MCD_OPC_Decode, 158, 8, 247, 3, // Opcode: FCVTNSUXSr /* 85446 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 85468 /* 85451 */ MCD_OPC_CheckPredicate, 16, 212, 5, 0, // Skip to: 86948 /* 85456 */ MCD_OPC_CheckField, 10, 6, 0, 205, 5, 0, // Skip to: 86948 /* 85463 */ MCD_OPC_Decode, 172, 8, 247, 3, // Opcode: FCVTNUUXSr /* 85468 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 85490 /* 85473 */ MCD_OPC_CheckPredicate, 16, 190, 5, 0, // Skip to: 86948 /* 85478 */ MCD_OPC_CheckField, 10, 6, 0, 183, 5, 0, // Skip to: 86948 /* 85485 */ MCD_OPC_Decode, 195, 22, 248, 3, // Opcode: SCVTFUXSri /* 85490 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 85512 /* 85495 */ MCD_OPC_CheckPredicate, 16, 168, 5, 0, // Skip to: 86948 /* 85500 */ MCD_OPC_CheckField, 10, 6, 0, 161, 5, 0, // Skip to: 86948 /* 85507 */ MCD_OPC_Decode, 182, 31, 248, 3, // Opcode: UCVTFUXSri /* 85512 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 85534 /* 85517 */ MCD_OPC_CheckPredicate, 16, 146, 5, 0, // Skip to: 86948 /* 85522 */ MCD_OPC_CheckField, 10, 6, 0, 139, 5, 0, // Skip to: 86948 /* 85529 */ MCD_OPC_Decode, 222, 7, 247, 3, // Opcode: FCVTASUXSr /* 85534 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 85556 /* 85539 */ MCD_OPC_CheckPredicate, 16, 124, 5, 0, // Skip to: 86948 /* 85544 */ MCD_OPC_CheckField, 10, 6, 0, 117, 5, 0, // Skip to: 86948 /* 85551 */ MCD_OPC_Decode, 236, 7, 247, 3, // Opcode: FCVTAUUXSr /* 85556 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 85578 /* 85561 */ MCD_OPC_CheckPredicate, 16, 102, 5, 0, // Skip to: 86948 /* 85566 */ MCD_OPC_CheckField, 10, 6, 0, 95, 5, 0, // Skip to: 86948 /* 85573 */ MCD_OPC_Decode, 190, 8, 247, 3, // Opcode: FCVTPSUXSr /* 85578 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 85600 /* 85583 */ MCD_OPC_CheckPredicate, 16, 80, 5, 0, // Skip to: 86948 /* 85588 */ MCD_OPC_CheckField, 10, 6, 0, 73, 5, 0, // Skip to: 86948 /* 85595 */ MCD_OPC_Decode, 204, 8, 247, 3, // Opcode: FCVTPUUXSr /* 85600 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 85622 /* 85605 */ MCD_OPC_CheckPredicate, 16, 58, 5, 0, // Skip to: 86948 /* 85610 */ MCD_OPC_CheckField, 10, 6, 0, 51, 5, 0, // Skip to: 86948 /* 85617 */ MCD_OPC_Decode, 130, 8, 247, 3, // Opcode: FCVTMSUXSr /* 85622 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 85644 /* 85627 */ MCD_OPC_CheckPredicate, 16, 36, 5, 0, // Skip to: 86948 /* 85632 */ MCD_OPC_CheckField, 10, 6, 0, 29, 5, 0, // Skip to: 86948 /* 85639 */ MCD_OPC_Decode, 144, 8, 247, 3, // Opcode: FCVTMUUXSr /* 85644 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 85666 /* 85649 */ MCD_OPC_CheckPredicate, 16, 14, 5, 0, // Skip to: 86948 /* 85654 */ MCD_OPC_CheckField, 10, 6, 0, 7, 5, 0, // Skip to: 86948 /* 85661 */ MCD_OPC_Decode, 229, 8, 247, 3, // Opcode: FCVTZSUXSr /* 85666 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 85688 /* 85671 */ MCD_OPC_CheckPredicate, 16, 248, 4, 0, // Skip to: 86948 /* 85676 */ MCD_OPC_CheckField, 10, 6, 0, 241, 4, 0, // Skip to: 86948 /* 85683 */ MCD_OPC_Decode, 136, 9, 247, 3, // Opcode: FCVTZUUXSr /* 85688 */ MCD_OPC_FilterValue, 66, 10, 0, 0, // Skip to: 85703 /* 85693 */ MCD_OPC_CheckPredicate, 16, 226, 4, 0, // Skip to: 86948 /* 85698 */ MCD_OPC_Decode, 187, 22, 249, 3, // Opcode: SCVTFSXDri /* 85703 */ MCD_OPC_FilterValue, 67, 10, 0, 0, // Skip to: 85718 /* 85708 */ MCD_OPC_CheckPredicate, 16, 211, 4, 0, // Skip to: 86948 /* 85713 */ MCD_OPC_Decode, 174, 31, 249, 3, // Opcode: UCVTFSXDri /* 85718 */ MCD_OPC_FilterValue, 88, 10, 0, 0, // Skip to: 85733 /* 85723 */ MCD_OPC_CheckPredicate, 16, 196, 4, 0, // Skip to: 86948 /* 85728 */ MCD_OPC_Decode, 221, 8, 250, 3, // Opcode: FCVTZSSXDri /* 85733 */ MCD_OPC_FilterValue, 89, 10, 0, 0, // Skip to: 85748 /* 85738 */ MCD_OPC_CheckPredicate, 16, 181, 4, 0, // Skip to: 86948 /* 85743 */ MCD_OPC_Decode, 128, 9, 250, 3, // Opcode: FCVTZUSXDri /* 85748 */ MCD_OPC_FilterValue, 96, 17, 0, 0, // Skip to: 85770 /* 85753 */ MCD_OPC_CheckPredicate, 16, 166, 4, 0, // Skip to: 86948 /* 85758 */ MCD_OPC_CheckField, 10, 6, 0, 159, 4, 0, // Skip to: 86948 /* 85765 */ MCD_OPC_Decode, 156, 8, 251, 3, // Opcode: FCVTNSUXDr /* 85770 */ MCD_OPC_FilterValue, 97, 17, 0, 0, // Skip to: 85792 /* 85775 */ MCD_OPC_CheckPredicate, 16, 144, 4, 0, // Skip to: 86948 /* 85780 */ MCD_OPC_CheckField, 10, 6, 0, 137, 4, 0, // Skip to: 86948 /* 85787 */ MCD_OPC_Decode, 170, 8, 251, 3, // Opcode: FCVTNUUXDr /* 85792 */ MCD_OPC_FilterValue, 98, 17, 0, 0, // Skip to: 85814 /* 85797 */ MCD_OPC_CheckPredicate, 16, 122, 4, 0, // Skip to: 86948 /* 85802 */ MCD_OPC_CheckField, 10, 6, 0, 115, 4, 0, // Skip to: 86948 /* 85809 */ MCD_OPC_Decode, 193, 22, 252, 3, // Opcode: SCVTFUXDri /* 85814 */ MCD_OPC_FilterValue, 99, 17, 0, 0, // Skip to: 85836 /* 85819 */ MCD_OPC_CheckPredicate, 16, 100, 4, 0, // Skip to: 86948 /* 85824 */ MCD_OPC_CheckField, 10, 6, 0, 93, 4, 0, // Skip to: 86948 /* 85831 */ MCD_OPC_Decode, 180, 31, 252, 3, // Opcode: UCVTFUXDri /* 85836 */ MCD_OPC_FilterValue, 100, 17, 0, 0, // Skip to: 85858 /* 85841 */ MCD_OPC_CheckPredicate, 16, 78, 4, 0, // Skip to: 86948 /* 85846 */ MCD_OPC_CheckField, 10, 6, 0, 71, 4, 0, // Skip to: 86948 /* 85853 */ MCD_OPC_Decode, 220, 7, 251, 3, // Opcode: FCVTASUXDr /* 85858 */ MCD_OPC_FilterValue, 101, 17, 0, 0, // Skip to: 85880 /* 85863 */ MCD_OPC_CheckPredicate, 16, 56, 4, 0, // Skip to: 86948 /* 85868 */ MCD_OPC_CheckField, 10, 6, 0, 49, 4, 0, // Skip to: 86948 /* 85875 */ MCD_OPC_Decode, 234, 7, 251, 3, // Opcode: FCVTAUUXDr /* 85880 */ MCD_OPC_FilterValue, 102, 17, 0, 0, // Skip to: 85902 /* 85885 */ MCD_OPC_CheckPredicate, 16, 34, 4, 0, // Skip to: 86948 /* 85890 */ MCD_OPC_CheckField, 10, 6, 0, 27, 4, 0, // Skip to: 86948 /* 85897 */ MCD_OPC_Decode, 217, 10, 251, 3, // Opcode: FMOVDXr /* 85902 */ MCD_OPC_FilterValue, 103, 17, 0, 0, // Skip to: 85924 /* 85907 */ MCD_OPC_CheckPredicate, 16, 12, 4, 0, // Skip to: 86948 /* 85912 */ MCD_OPC_CheckField, 10, 6, 0, 5, 4, 0, // Skip to: 86948 /* 85919 */ MCD_OPC_Decode, 232, 10, 252, 3, // Opcode: FMOVXDr /* 85924 */ MCD_OPC_FilterValue, 104, 17, 0, 0, // Skip to: 85946 /* 85929 */ MCD_OPC_CheckPredicate, 16, 246, 3, 0, // Skip to: 86948 /* 85934 */ MCD_OPC_CheckField, 10, 6, 0, 239, 3, 0, // Skip to: 86948 /* 85941 */ MCD_OPC_Decode, 188, 8, 251, 3, // Opcode: FCVTPSUXDr /* 85946 */ MCD_OPC_FilterValue, 105, 17, 0, 0, // Skip to: 85968 /* 85951 */ MCD_OPC_CheckPredicate, 16, 224, 3, 0, // Skip to: 86948 /* 85956 */ MCD_OPC_CheckField, 10, 6, 0, 217, 3, 0, // Skip to: 86948 /* 85963 */ MCD_OPC_Decode, 202, 8, 251, 3, // Opcode: FCVTPUUXDr /* 85968 */ MCD_OPC_FilterValue, 112, 17, 0, 0, // Skip to: 85990 /* 85973 */ MCD_OPC_CheckPredicate, 16, 202, 3, 0, // Skip to: 86948 /* 85978 */ MCD_OPC_CheckField, 10, 6, 0, 195, 3, 0, // Skip to: 86948 /* 85985 */ MCD_OPC_Decode, 128, 8, 251, 3, // Opcode: FCVTMSUXDr /* 85990 */ MCD_OPC_FilterValue, 113, 17, 0, 0, // Skip to: 86012 /* 85995 */ MCD_OPC_CheckPredicate, 16, 180, 3, 0, // Skip to: 86948 /* 86000 */ MCD_OPC_CheckField, 10, 6, 0, 173, 3, 0, // Skip to: 86948 /* 86007 */ MCD_OPC_Decode, 142, 8, 251, 3, // Opcode: FCVTMUUXDr /* 86012 */ MCD_OPC_FilterValue, 120, 17, 0, 0, // Skip to: 86034 /* 86017 */ MCD_OPC_CheckPredicate, 16, 158, 3, 0, // Skip to: 86948 /* 86022 */ MCD_OPC_CheckField, 10, 6, 0, 151, 3, 0, // Skip to: 86948 /* 86029 */ MCD_OPC_Decode, 227, 8, 251, 3, // Opcode: FCVTZSUXDr /* 86034 */ MCD_OPC_FilterValue, 121, 17, 0, 0, // Skip to: 86056 /* 86039 */ MCD_OPC_CheckPredicate, 16, 136, 3, 0, // Skip to: 86948 /* 86044 */ MCD_OPC_CheckField, 10, 6, 0, 129, 3, 0, // Skip to: 86948 /* 86051 */ MCD_OPC_Decode, 134, 9, 251, 3, // Opcode: FCVTZUUXDr /* 86056 */ MCD_OPC_FilterValue, 174, 1, 17, 0, 0, // Skip to: 86079 /* 86062 */ MCD_OPC_CheckPredicate, 16, 113, 3, 0, // Skip to: 86948 /* 86067 */ MCD_OPC_CheckField, 10, 6, 0, 106, 3, 0, // Skip to: 86948 /* 86074 */ MCD_OPC_Decode, 216, 10, 253, 3, // Opcode: FMOVDXHighr /* 86079 */ MCD_OPC_FilterValue, 175, 1, 17, 0, 0, // Skip to: 86102 /* 86085 */ MCD_OPC_CheckPredicate, 16, 90, 3, 0, // Skip to: 86948 /* 86090 */ MCD_OPC_CheckField, 10, 6, 0, 83, 3, 0, // Skip to: 86948 /* 86097 */ MCD_OPC_Decode, 231, 10, 253, 3, // Opcode: FMOVXDHighr /* 86102 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 86118 /* 86108 */ MCD_OPC_CheckPredicate, 18, 67, 3, 0, // Skip to: 86948 /* 86113 */ MCD_OPC_Decode, 188, 22, 254, 3, // Opcode: SCVTFSXHri /* 86118 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 86134 /* 86124 */ MCD_OPC_CheckPredicate, 18, 51, 3, 0, // Skip to: 86948 /* 86129 */ MCD_OPC_Decode, 175, 31, 254, 3, // Opcode: UCVTFSXHri /* 86134 */ MCD_OPC_FilterValue, 216, 1, 10, 0, 0, // Skip to: 86150 /* 86140 */ MCD_OPC_CheckPredicate, 18, 35, 3, 0, // Skip to: 86948 /* 86145 */ MCD_OPC_Decode, 222, 8, 255, 3, // Opcode: FCVTZSSXHri /* 86150 */ MCD_OPC_FilterValue, 217, 1, 10, 0, 0, // Skip to: 86166 /* 86156 */ MCD_OPC_CheckPredicate, 18, 19, 3, 0, // Skip to: 86948 /* 86161 */ MCD_OPC_Decode, 129, 9, 255, 3, // Opcode: FCVTZUSXHri /* 86166 */ MCD_OPC_FilterValue, 224, 1, 17, 0, 0, // Skip to: 86189 /* 86172 */ MCD_OPC_CheckPredicate, 18, 3, 3, 0, // Skip to: 86948 /* 86177 */ MCD_OPC_CheckField, 10, 6, 0, 252, 2, 0, // Skip to: 86948 /* 86184 */ MCD_OPC_Decode, 157, 8, 128, 4, // Opcode: FCVTNSUXHr /* 86189 */ MCD_OPC_FilterValue, 225, 1, 17, 0, 0, // Skip to: 86212 /* 86195 */ MCD_OPC_CheckPredicate, 18, 236, 2, 0, // Skip to: 86948 /* 86200 */ MCD_OPC_CheckField, 10, 6, 0, 229, 2, 0, // Skip to: 86948 /* 86207 */ MCD_OPC_Decode, 171, 8, 128, 4, // Opcode: FCVTNUUXHr /* 86212 */ MCD_OPC_FilterValue, 226, 1, 17, 0, 0, // Skip to: 86235 /* 86218 */ MCD_OPC_CheckPredicate, 18, 213, 2, 0, // Skip to: 86948 /* 86223 */ MCD_OPC_CheckField, 10, 6, 0, 206, 2, 0, // Skip to: 86948 /* 86230 */ MCD_OPC_Decode, 194, 22, 129, 4, // Opcode: SCVTFUXHri /* 86235 */ MCD_OPC_FilterValue, 227, 1, 17, 0, 0, // Skip to: 86258 /* 86241 */ MCD_OPC_CheckPredicate, 18, 190, 2, 0, // Skip to: 86948 /* 86246 */ MCD_OPC_CheckField, 10, 6, 0, 183, 2, 0, // Skip to: 86948 /* 86253 */ MCD_OPC_Decode, 181, 31, 129, 4, // Opcode: UCVTFUXHri /* 86258 */ MCD_OPC_FilterValue, 228, 1, 17, 0, 0, // Skip to: 86281 /* 86264 */ MCD_OPC_CheckPredicate, 18, 167, 2, 0, // Skip to: 86948 /* 86269 */ MCD_OPC_CheckField, 10, 6, 0, 160, 2, 0, // Skip to: 86948 /* 86276 */ MCD_OPC_Decode, 221, 7, 128, 4, // Opcode: FCVTASUXHr /* 86281 */ MCD_OPC_FilterValue, 229, 1, 17, 0, 0, // Skip to: 86304 /* 86287 */ MCD_OPC_CheckPredicate, 18, 144, 2, 0, // Skip to: 86948 /* 86292 */ MCD_OPC_CheckField, 10, 6, 0, 137, 2, 0, // Skip to: 86948 /* 86299 */ MCD_OPC_Decode, 235, 7, 128, 4, // Opcode: FCVTAUUXHr /* 86304 */ MCD_OPC_FilterValue, 230, 1, 17, 0, 0, // Skip to: 86327 /* 86310 */ MCD_OPC_CheckPredicate, 18, 121, 2, 0, // Skip to: 86948 /* 86315 */ MCD_OPC_CheckField, 10, 6, 0, 114, 2, 0, // Skip to: 86948 /* 86322 */ MCD_OPC_Decode, 222, 10, 128, 4, // Opcode: FMOVHXr /* 86327 */ MCD_OPC_FilterValue, 231, 1, 17, 0, 0, // Skip to: 86350 /* 86333 */ MCD_OPC_CheckPredicate, 18, 98, 2, 0, // Skip to: 86948 /* 86338 */ MCD_OPC_CheckField, 10, 6, 0, 91, 2, 0, // Skip to: 86948 /* 86345 */ MCD_OPC_Decode, 233, 10, 129, 4, // Opcode: FMOVXHr /* 86350 */ MCD_OPC_FilterValue, 232, 1, 17, 0, 0, // Skip to: 86373 /* 86356 */ MCD_OPC_CheckPredicate, 18, 75, 2, 0, // Skip to: 86948 /* 86361 */ MCD_OPC_CheckField, 10, 6, 0, 68, 2, 0, // Skip to: 86948 /* 86368 */ MCD_OPC_Decode, 189, 8, 128, 4, // Opcode: FCVTPSUXHr /* 86373 */ MCD_OPC_FilterValue, 233, 1, 17, 0, 0, // Skip to: 86396 /* 86379 */ MCD_OPC_CheckPredicate, 18, 52, 2, 0, // Skip to: 86948 /* 86384 */ MCD_OPC_CheckField, 10, 6, 0, 45, 2, 0, // Skip to: 86948 /* 86391 */ MCD_OPC_Decode, 203, 8, 128, 4, // Opcode: FCVTPUUXHr /* 86396 */ MCD_OPC_FilterValue, 240, 1, 17, 0, 0, // Skip to: 86419 /* 86402 */ MCD_OPC_CheckPredicate, 18, 29, 2, 0, // Skip to: 86948 /* 86407 */ MCD_OPC_CheckField, 10, 6, 0, 22, 2, 0, // Skip to: 86948 /* 86414 */ MCD_OPC_Decode, 129, 8, 128, 4, // Opcode: FCVTMSUXHr /* 86419 */ MCD_OPC_FilterValue, 241, 1, 17, 0, 0, // Skip to: 86442 /* 86425 */ MCD_OPC_CheckPredicate, 18, 6, 2, 0, // Skip to: 86948 /* 86430 */ MCD_OPC_CheckField, 10, 6, 0, 255, 1, 0, // Skip to: 86948 /* 86437 */ MCD_OPC_Decode, 143, 8, 128, 4, // Opcode: FCVTMUUXHr /* 86442 */ MCD_OPC_FilterValue, 248, 1, 17, 0, 0, // Skip to: 86465 /* 86448 */ MCD_OPC_CheckPredicate, 18, 239, 1, 0, // Skip to: 86948 /* 86453 */ MCD_OPC_CheckField, 10, 6, 0, 232, 1, 0, // Skip to: 86948 /* 86460 */ MCD_OPC_Decode, 228, 8, 128, 4, // Opcode: FCVTZSUXHr /* 86465 */ MCD_OPC_FilterValue, 249, 1, 221, 1, 0, // Skip to: 86948 /* 86471 */ MCD_OPC_CheckPredicate, 18, 216, 1, 0, // Skip to: 86948 /* 86476 */ MCD_OPC_CheckField, 10, 6, 0, 209, 1, 0, // Skip to: 86948 /* 86483 */ MCD_OPC_Decode, 135, 9, 128, 4, // Opcode: FCVTZUUXHr /* 86488 */ MCD_OPC_FilterValue, 5, 225, 0, 0, // Skip to: 86718 /* 86493 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 86496 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 86597 /* 86501 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 86504 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86521 /* 86509 */ MCD_OPC_CheckField, 21, 1, 0, 176, 1, 0, // Skip to: 86948 /* 86516 */ MCD_OPC_Decode, 202, 29, 255, 2, // Opcode: STURSi /* 86521 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86538 /* 86526 */ MCD_OPC_CheckField, 21, 1, 0, 159, 1, 0, // Skip to: 86948 /* 86533 */ MCD_OPC_Decode, 175, 29, 255, 2, // Opcode: STRSpost /* 86538 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86580 /* 86543 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 86546 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86563 /* 86551 */ MCD_OPC_CheckField, 21, 1, 1, 134, 1, 0, // Skip to: 86948 /* 86558 */ MCD_OPC_Decode, 177, 29, 130, 4, // Opcode: STRSroW /* 86563 */ MCD_OPC_FilterValue, 3, 124, 1, 0, // Skip to: 86948 /* 86568 */ MCD_OPC_CheckField, 21, 1, 1, 117, 1, 0, // Skip to: 86948 /* 86575 */ MCD_OPC_Decode, 178, 29, 131, 4, // Opcode: STRSroX /* 86580 */ MCD_OPC_FilterValue, 3, 107, 1, 0, // Skip to: 86948 /* 86585 */ MCD_OPC_CheckField, 21, 1, 0, 100, 1, 0, // Skip to: 86948 /* 86592 */ MCD_OPC_Decode, 176, 29, 255, 2, // Opcode: STRSpre /* 86597 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 86698 /* 86602 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 86605 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86622 /* 86610 */ MCD_OPC_CheckField, 21, 1, 0, 75, 1, 0, // Skip to: 86948 /* 86617 */ MCD_OPC_Decode, 141, 19, 255, 2, // Opcode: LDURSi /* 86622 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86639 /* 86627 */ MCD_OPC_CheckField, 21, 1, 0, 58, 1, 0, // Skip to: 86948 /* 86634 */ MCD_OPC_Decode, 150, 18, 255, 2, // Opcode: LDRSpost /* 86639 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86681 /* 86644 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 86647 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86664 /* 86652 */ MCD_OPC_CheckField, 21, 1, 1, 33, 1, 0, // Skip to: 86948 /* 86659 */ MCD_OPC_Decode, 152, 18, 130, 4, // Opcode: LDRSroW /* 86664 */ MCD_OPC_FilterValue, 3, 23, 1, 0, // Skip to: 86948 /* 86669 */ MCD_OPC_CheckField, 21, 1, 1, 16, 1, 0, // Skip to: 86948 /* 86676 */ MCD_OPC_Decode, 153, 18, 131, 4, // Opcode: LDRSroX /* 86681 */ MCD_OPC_FilterValue, 3, 6, 1, 0, // Skip to: 86948 /* 86686 */ MCD_OPC_CheckField, 21, 1, 0, 255, 0, 0, // Skip to: 86948 /* 86693 */ MCD_OPC_Decode, 151, 18, 255, 2, // Opcode: LDRSpre /* 86698 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 86708 /* 86703 */ MCD_OPC_Decode, 179, 29, 137, 3, // Opcode: STRSui /* 86708 */ MCD_OPC_FilterValue, 5, 235, 0, 0, // Skip to: 86948 /* 86713 */ MCD_OPC_Decode, 154, 18, 137, 3, // Opcode: LDRSui /* 86718 */ MCD_OPC_FilterValue, 7, 225, 0, 0, // Skip to: 86948 /* 86723 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 86726 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 86827 /* 86731 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 86734 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86751 /* 86739 */ MCD_OPC_CheckField, 21, 1, 0, 202, 0, 0, // Skip to: 86948 /* 86746 */ MCD_OPC_Decode, 198, 29, 255, 2, // Opcode: STURDi /* 86751 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86768 /* 86756 */ MCD_OPC_CheckField, 21, 1, 0, 185, 0, 0, // Skip to: 86948 /* 86763 */ MCD_OPC_Decode, 155, 29, 255, 2, // Opcode: STRDpost /* 86768 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86810 /* 86773 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 86776 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86793 /* 86781 */ MCD_OPC_CheckField, 21, 1, 1, 160, 0, 0, // Skip to: 86948 /* 86788 */ MCD_OPC_Decode, 157, 29, 132, 4, // Opcode: STRDroW /* 86793 */ MCD_OPC_FilterValue, 3, 150, 0, 0, // Skip to: 86948 /* 86798 */ MCD_OPC_CheckField, 21, 1, 1, 143, 0, 0, // Skip to: 86948 /* 86805 */ MCD_OPC_Decode, 158, 29, 133, 4, // Opcode: STRDroX /* 86810 */ MCD_OPC_FilterValue, 3, 133, 0, 0, // Skip to: 86948 /* 86815 */ MCD_OPC_CheckField, 21, 1, 0, 126, 0, 0, // Skip to: 86948 /* 86822 */ MCD_OPC_Decode, 156, 29, 255, 2, // Opcode: STRDpre /* 86827 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 86928 /* 86832 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 86835 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86852 /* 86840 */ MCD_OPC_CheckField, 21, 1, 0, 101, 0, 0, // Skip to: 86948 /* 86847 */ MCD_OPC_Decode, 132, 19, 255, 2, // Opcode: LDURDi /* 86852 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86869 /* 86857 */ MCD_OPC_CheckField, 21, 1, 0, 84, 0, 0, // Skip to: 86948 /* 86864 */ MCD_OPC_Decode, 230, 17, 255, 2, // Opcode: LDRDpost /* 86869 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86911 /* 86874 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... /* 86877 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86894 /* 86882 */ MCD_OPC_CheckField, 21, 1, 1, 59, 0, 0, // Skip to: 86948 /* 86889 */ MCD_OPC_Decode, 232, 17, 132, 4, // Opcode: LDRDroW /* 86894 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 86948 /* 86899 */ MCD_OPC_CheckField, 21, 1, 1, 42, 0, 0, // Skip to: 86948 /* 86906 */ MCD_OPC_Decode, 233, 17, 133, 4, // Opcode: LDRDroX /* 86911 */ MCD_OPC_FilterValue, 3, 32, 0, 0, // Skip to: 86948 /* 86916 */ MCD_OPC_CheckField, 21, 1, 0, 25, 0, 0, // Skip to: 86948 /* 86923 */ MCD_OPC_Decode, 231, 17, 255, 2, // Opcode: LDRDpre /* 86928 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 86938 /* 86933 */ MCD_OPC_Decode, 159, 29, 137, 3, // Opcode: STRDui /* 86938 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 86948 /* 86943 */ MCD_OPC_Decode, 234, 17, 137, 3, // Opcode: LDRDui /* 86948 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) { switch (Idx) { default: /* llvm_unreachable("Invalid index!");*/ case 0: return (AArch64_getFeatureBits(AArch64_FeatureSVE)); case 1: return (AArch64_getFeatureBits(AArch64_FeatureLSE)); case 2: return (AArch64_getFeatureBits(AArch64_HasV8_1aOps)); case 3: return (AArch64_getFeatureBits(AArch64_FeatureNEON)); case 4: return (AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureFullFP16)); case 5: return (AArch64_getFeatureBits(AArch64_FeatureAES)); case 6: return (AArch64_getFeatureBits(AArch64_FeatureSHA3)); case 7: return (AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureRDM)); case 8: return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureFullFP16)); case 9: return (AArch64_getFeatureBits(AArch64_FeatureSM4)); case 10: return (AArch64_getFeatureBits(AArch64_FeatureDotProd)); case 11: return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureNEON)); case 12: return (AArch64_getFeatureBits(AArch64_HasV8_4aOps)); case 13: return (AArch64_getFeatureBits(AArch64_HasV8_3aOps)); case 14: return (AArch64_getFeatureBits(AArch64_FeatureCRC)); case 15: return (AArch64_getFeatureBits(AArch64_FeatureRCPC)); case 16: return (AArch64_getFeatureBits(AArch64_FeatureFPARMv8)); case 17: return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureFPARMv8)); case 18: return (AArch64_getFeatureBits(AArch64_FeatureFullFP16)); case 19: return (AArch64_getFeatureBits(AArch64_FeatureSHA2)); case 20: return (AArch64_getFeatureBits(AArch64_FeatureRDM)); } } #define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, bool *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ default: /* llvm_unreachable("Invalid index!");*/ \ case 0: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 1: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 2: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 3: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 4: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 5: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 6: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 7: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 8: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 9: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 10: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 11: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 12: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 13: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 14: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 15: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 5) << 0; \ tmp |= fieldname(insn, 22, 1) << 5; \ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 16: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 5) << 0; \ tmp |= fieldname(insn, 22, 1) << 5; \ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 17: \ if (!Check(&S, DecodeSVELogicalImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 18: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 19: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 20: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 21: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 22: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 23: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 24: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 25: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 26: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 27: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 28: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 16, 5) << 3; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 29: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 22, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 30: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 20, 1) << 0; \ tmp |= fieldname(insn, 22, 2) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 31: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 19, 2) << 0; \ tmp |= fieldname(insn, 22, 2) << 2; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 32: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 18, 3) << 0; \ tmp |= fieldname(insn, 22, 2) << 3; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 33: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 17, 4) << 0; \ tmp |= fieldname(insn, 22, 2) << 4; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 34: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 35: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 36: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 37: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 38: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 39: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 40: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 41: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 42: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 43: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 44: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 45: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 46: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 47: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 6); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ return S; \ case 48: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 6); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ return S; \ case 49: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 50: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 51: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 52: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 53: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 54: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 55: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 56: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 57: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 58: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 59: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 60: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 16, 5) << 0; \ tmp |= fieldname(insn, 22, 1) << 5; \ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 61: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 16, 5) << 0; \ tmp |= fieldname(insn, 22, 1) << 5; \ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 62: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 63: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 64: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 65: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 66: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 67: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 68: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 69: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 70: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 71: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 72: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 73: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 74: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 75: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 76: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 77: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 78: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 79: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 80: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 81: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 82: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 14, 7); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 83: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 84: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 85: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 86: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 87: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 88: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 89: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 90: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 91: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 92: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 93: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 94: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 95: \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 96: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 97: \ return S; \ case 98: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 99: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 8); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 100: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 101: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 102: \ tmp = fieldname(insn, 10, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 103: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 104: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 105: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 106: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 107: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 108: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 109: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 110: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 111: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 112: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 9); \ if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 113: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 114: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 115: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 116: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 13, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 117: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 19, 2) << 0; \ tmp |= fieldname(insn, 22, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 118: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 19, 2) << 0; \ tmp |= fieldname(insn, 22, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 119: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 120: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 121: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 122: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 123: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 124: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 125: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 126: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 127: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 128: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 129: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 16, 6) << 3; \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 9))) { return MCDisassembler_Fail; } \ return S; \ case 130: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ return S; \ case 131: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 16, 6) << 3; \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 9))) { return MCDisassembler_Fail; } \ return S; \ case 132: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 133: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 134: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 135: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 136: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 137: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 138: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 139: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 140: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 141: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPR3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 142: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPR3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 143: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 144: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeZPR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 3); \ if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 145: \ if (!Check(&S, DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 146: \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 147: \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 148: \ if (!Check(&S, DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 149: \ if (!Check(&S, DecodeAddSubERegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 150: \ if (!Check(&S, DecodePairLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 151: \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 152: \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 153: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 154: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 155: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 156: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 157: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 158: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 159: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 160: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 161: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 162: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 163: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 164: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 165: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 166: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 167: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 168: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 169: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 170: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 171: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 172: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 173: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 174: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 175: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 176: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 177: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 178: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 179: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 180: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 181: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 182: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 183: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 184: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 185: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 186: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 187: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 188: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 189: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 190: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 191: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 192: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 193: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 194: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 195: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 196: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 197: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 198: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 199: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 200: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 201: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 202: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 203: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 204: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 205: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 206: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 207: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 208: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 209: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 210: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 211: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 212: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 213: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 214: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 215: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 216: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 217: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 218: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 219: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 220: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 221: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 222: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 223: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 224: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 2) << 0; \ tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 225: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 226: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 227: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 228: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 229: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 230: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 231: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 232: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 233: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 234: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 235: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 236: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 237: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 238: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 239: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 240: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 241: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 242: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 243: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 244: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 245: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 246: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 247: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 248: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 249: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 250: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 251: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 252: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 253: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 254: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 255: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 256: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 257: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 258: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 259: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 260: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 261: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 262: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 263: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 264: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 265: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 266: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 267: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 268: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 269: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 270: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 271: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 272: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 273: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 274: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 275: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 276: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 277: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 278: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 279: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 280: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 281: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 282: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 283: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 284: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 285: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 286: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 287: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 288: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 289: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 14, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 290: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 13, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 291: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 292: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 293: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 294: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 295: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 296: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 297: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 298: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 299: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 300: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 301: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 302: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 303: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 304: \ if (!Check(&S, DecodeModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 305: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 306: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 307: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 308: \ if (!Check(&S, DecodeModImmTiedInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 309: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 310: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 311: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 312: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 313: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 314: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 315: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 316: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 317: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 318: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 319: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 320: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 321: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 322: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 323: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 324: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 325: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 326: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 327: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 328: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 329: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 330: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 331: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 332: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 333: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 334: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 335: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 336: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 337: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 338: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 339: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 340: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 341: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 342: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 343: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 13, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 344: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 345: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 346: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 347: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 13, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 348: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 349: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 350: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 351: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 352: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 353: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 354: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 355: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 13, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 356: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 357: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 358: \ if (!Check(&S, DecodeAdrInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 359: \ if (!Check(&S, DecodeBaseAddSubImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 360: \ if (!Check(&S, DecodeLogicalImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 361: \ if (!Check(&S, DecodeMoveImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 362: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 363: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 364: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 365: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 366: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 367: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 10, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 368: \ if (!Check(&S, DecodeUnconditionalBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 369: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 370: \ if (!Check(&S, DecodeTestAndBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 371: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 372: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 373: \ tmp = fieldname(insn, 5, 16); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 374: \ tmp = fieldname(insn, 8, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 375: \ tmp = fieldname(insn, 5, 7); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 376: \ if (!Check(&S, DecodeSystemPStateInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 377: \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 8, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 378: \ tmp = fieldname(insn, 5, 16); \ if (!Check(&S, DecodeMSRSystemRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 379: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 8, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 380: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 16); \ if (!Check(&S, DecodeMRSSystemRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 381: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 382: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 383: \ if (!Check(&S, DecodeSignedLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 384: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 385: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 386: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 387: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 388: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 389: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 390: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 391: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 392: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 393: \ if (!Check(&S, DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 394: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 395: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 396: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 397: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 398: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 399: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 400: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 401: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 402: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 403: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 404: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 15, 6); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 405: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 406: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 407: \ tmp = fieldname(insn, 0, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 408: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 409: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 410: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 411: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 412: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 9) << 0; \ tmp |= fieldname(insn, 22, 1) << 9; \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 10))) { return MCDisassembler_Fail; } \ return S; \ case 413: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 9) << 0; \ tmp |= fieldname(insn, 22, 1) << 9; \ if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 10))) { return MCDisassembler_Fail; } \ return S; \ case 414: \ tmp = fieldname(insn, 0, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 415: \ tmp = fieldname(insn, 0, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 416: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 417: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 418: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 419: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 420: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 421: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 422: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 423: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 424: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 425: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 426: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 13, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 427: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 428: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 429: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 430: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 431: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 432: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 433: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 434: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 435: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 13, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 436: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 437: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 438: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 439: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 440: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 441: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 442: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 443: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 444: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 445: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 446: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 447: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 13, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 448: \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 449: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 450: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 451: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 452: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 453: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 454: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 455: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 456: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 457: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 458: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 459: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 460: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 461: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 462: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 463: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 464: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 465: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 466: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 467: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 468: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 469: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 470: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 471: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 472: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 473: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 474: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 475: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 476: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 477: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 478: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 479: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 480: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 481: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 482: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 483: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 484: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 485: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 486: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 487: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 488: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 489: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 490: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 491: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 492: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 493: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 494: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 495: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 496: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 497: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 498: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 499: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 500: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 19); \ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 501: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 502: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 503: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 504: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 505: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 506: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 507: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 508: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 509: \ if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 510: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 511: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 512: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 513: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 514: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 515: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 516: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 517: \ tmp = fieldname(insn, 0, 5); \ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address) \ { \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail, DecodeComplete = true; \ uint32_t ExpectedValue; \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ /* Decode the field value. */ \ Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ /* Decode the field value. */ \ ExpectedValue = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ /* Decode the Predicate Index value. */ \ PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Check the predicate. */ \ if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ /* Decode the Opcode value. */ \ Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_clear(MI); \ MCInst_setOpcode(MI, Opc); \ S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ /* assert(DecodeComplete); */ \ return S; \ } \ case MCD_OPC_TryDecode: { \ /* Decode the Opcode value. */ \ Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Perform the decode operation. */ \ MCInst_setOpcode(MI, Opc); \ S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ if (DecodeComplete) { \ /* Decoding complete. */ \ return S; \ } else { \ /* assert(S == MCDisassembler_Fail); */ \ /* If the decoding was incomplete, skip. */ \ Ptr += NumToSkip; \ /* Reset decode status. This also drops a SoftFail status that could be */ \ /* set before the decode attempt. */ \ S = MCDisassembler_Success; \ } \ break; \ } \ case MCD_OPC_SoftFail: { \ /* Decode the mask values. */ \ PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ } FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenInstrInfo.inc000064400000000000000000012336330072674642500223740ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { AArch64_PHI = 0, AArch64_INLINEASM = 1, AArch64_CFI_INSTRUCTION = 2, AArch64_EH_LABEL = 3, AArch64_GC_LABEL = 4, AArch64_ANNOTATION_LABEL = 5, AArch64_KILL = 6, AArch64_EXTRACT_SUBREG = 7, AArch64_INSERT_SUBREG = 8, AArch64_IMPLICIT_DEF = 9, AArch64_SUBREG_TO_REG = 10, AArch64_COPY_TO_REGCLASS = 11, AArch64_DBG_VALUE = 12, AArch64_DBG_LABEL = 13, AArch64_REG_SEQUENCE = 14, AArch64_COPY = 15, AArch64_BUNDLE = 16, AArch64_LIFETIME_START = 17, AArch64_LIFETIME_END = 18, AArch64_STACKMAP = 19, AArch64_FENTRY_CALL = 20, AArch64_PATCHPOINT = 21, AArch64_LOAD_STACK_GUARD = 22, AArch64_STATEPOINT = 23, AArch64_LOCAL_ESCAPE = 24, AArch64_FAULTING_OP = 25, AArch64_PATCHABLE_OP = 26, AArch64_PATCHABLE_FUNCTION_ENTER = 27, AArch64_PATCHABLE_RET = 28, AArch64_PATCHABLE_FUNCTION_EXIT = 29, AArch64_PATCHABLE_TAIL_CALL = 30, AArch64_PATCHABLE_EVENT_CALL = 31, AArch64_PATCHABLE_TYPED_EVENT_CALL = 32, AArch64_ICALL_BRANCH_FUNNEL = 33, AArch64_G_ADD = 34, AArch64_G_SUB = 35, AArch64_G_MUL = 36, AArch64_G_SDIV = 37, AArch64_G_UDIV = 38, AArch64_G_SREM = 39, AArch64_G_UREM = 40, AArch64_G_AND = 41, AArch64_G_OR = 42, AArch64_G_XOR = 43, AArch64_G_IMPLICIT_DEF = 44, AArch64_G_PHI = 45, AArch64_G_FRAME_INDEX = 46, AArch64_G_GLOBAL_VALUE = 47, AArch64_G_EXTRACT = 48, AArch64_G_UNMERGE_VALUES = 49, AArch64_G_INSERT = 50, AArch64_G_MERGE_VALUES = 51, AArch64_G_PTRTOINT = 52, AArch64_G_INTTOPTR = 53, AArch64_G_BITCAST = 54, AArch64_G_LOAD = 55, AArch64_G_SEXTLOAD = 56, AArch64_G_ZEXTLOAD = 57, AArch64_G_STORE = 58, AArch64_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, AArch64_G_ATOMIC_CMPXCHG = 60, AArch64_G_ATOMICRMW_XCHG = 61, AArch64_G_ATOMICRMW_ADD = 62, AArch64_G_ATOMICRMW_SUB = 63, AArch64_G_ATOMICRMW_AND = 64, AArch64_G_ATOMICRMW_NAND = 65, AArch64_G_ATOMICRMW_OR = 66, AArch64_G_ATOMICRMW_XOR = 67, AArch64_G_ATOMICRMW_MAX = 68, AArch64_G_ATOMICRMW_MIN = 69, AArch64_G_ATOMICRMW_UMAX = 70, AArch64_G_ATOMICRMW_UMIN = 71, AArch64_G_BRCOND = 72, AArch64_G_BRINDIRECT = 73, AArch64_G_INTRINSIC = 74, AArch64_G_INTRINSIC_W_SIDE_EFFECTS = 75, AArch64_G_ANYEXT = 76, AArch64_G_TRUNC = 77, AArch64_G_CONSTANT = 78, AArch64_G_FCONSTANT = 79, AArch64_G_VASTART = 80, AArch64_G_VAARG = 81, AArch64_G_SEXT = 82, AArch64_G_ZEXT = 83, AArch64_G_SHL = 84, AArch64_G_LSHR = 85, AArch64_G_ASHR = 86, AArch64_G_ICMP = 87, AArch64_G_FCMP = 88, AArch64_G_SELECT = 89, AArch64_G_UADDE = 90, AArch64_G_USUBE = 91, AArch64_G_SADDO = 92, AArch64_G_SSUBO = 93, AArch64_G_UMULO = 94, AArch64_G_SMULO = 95, AArch64_G_UMULH = 96, AArch64_G_SMULH = 97, AArch64_G_FADD = 98, AArch64_G_FSUB = 99, AArch64_G_FMUL = 100, AArch64_G_FMA = 101, AArch64_G_FDIV = 102, AArch64_G_FREM = 103, AArch64_G_FPOW = 104, AArch64_G_FEXP = 105, AArch64_G_FEXP2 = 106, AArch64_G_FLOG = 107, AArch64_G_FLOG2 = 108, AArch64_G_FNEG = 109, AArch64_G_FPEXT = 110, AArch64_G_FPTRUNC = 111, AArch64_G_FPTOSI = 112, AArch64_G_FPTOUI = 113, AArch64_G_SITOFP = 114, AArch64_G_UITOFP = 115, AArch64_G_FABS = 116, AArch64_G_GEP = 117, AArch64_G_PTR_MASK = 118, AArch64_G_BR = 119, AArch64_G_INSERT_VECTOR_ELT = 120, AArch64_G_EXTRACT_VECTOR_ELT = 121, AArch64_G_SHUFFLE_VECTOR = 122, AArch64_G_BSWAP = 123, AArch64_G_ADDRSPACE_CAST = 124, AArch64_G_BLOCK_ADDR = 125, AArch64_ABS_ZPmZ_B = 126, AArch64_ABS_ZPmZ_D = 127, AArch64_ABS_ZPmZ_H = 128, AArch64_ABS_ZPmZ_S = 129, AArch64_ABSv16i8 = 130, AArch64_ABSv1i64 = 131, AArch64_ABSv2i32 = 132, AArch64_ABSv2i64 = 133, AArch64_ABSv4i16 = 134, AArch64_ABSv4i32 = 135, AArch64_ABSv8i16 = 136, AArch64_ABSv8i8 = 137, AArch64_ADCSWr = 138, AArch64_ADCSXr = 139, AArch64_ADCWr = 140, AArch64_ADCXr = 141, AArch64_ADDHNv2i64_v2i32 = 142, AArch64_ADDHNv2i64_v4i32 = 143, AArch64_ADDHNv4i32_v4i16 = 144, AArch64_ADDHNv4i32_v8i16 = 145, AArch64_ADDHNv8i16_v16i8 = 146, AArch64_ADDHNv8i16_v8i8 = 147, AArch64_ADDPL_XXI = 148, AArch64_ADDPv16i8 = 149, AArch64_ADDPv2i32 = 150, AArch64_ADDPv2i64 = 151, AArch64_ADDPv2i64p = 152, AArch64_ADDPv4i16 = 153, AArch64_ADDPv4i32 = 154, AArch64_ADDPv8i16 = 155, AArch64_ADDPv8i8 = 156, AArch64_ADDSWri = 157, AArch64_ADDSWrr = 158, AArch64_ADDSWrs = 159, AArch64_ADDSWrx = 160, AArch64_ADDSXri = 161, AArch64_ADDSXrr = 162, AArch64_ADDSXrs = 163, AArch64_ADDSXrx = 164, AArch64_ADDSXrx64 = 165, AArch64_ADDVL_XXI = 166, AArch64_ADDVv16i8v = 167, AArch64_ADDVv4i16v = 168, AArch64_ADDVv4i32v = 169, AArch64_ADDVv8i16v = 170, AArch64_ADDVv8i8v = 171, AArch64_ADDWri = 172, AArch64_ADDWrr = 173, AArch64_ADDWrs = 174, AArch64_ADDWrx = 175, AArch64_ADDXri = 176, AArch64_ADDXrr = 177, AArch64_ADDXrs = 178, AArch64_ADDXrx = 179, AArch64_ADDXrx64 = 180, AArch64_ADD_ZI_B = 181, AArch64_ADD_ZI_D = 182, AArch64_ADD_ZI_H = 183, AArch64_ADD_ZI_S = 184, AArch64_ADD_ZPmZ_B = 185, AArch64_ADD_ZPmZ_D = 186, AArch64_ADD_ZPmZ_H = 187, AArch64_ADD_ZPmZ_S = 188, AArch64_ADD_ZZZ_B = 189, AArch64_ADD_ZZZ_D = 190, AArch64_ADD_ZZZ_H = 191, AArch64_ADD_ZZZ_S = 192, AArch64_ADDlowTLS = 193, AArch64_ADDv16i8 = 194, AArch64_ADDv1i64 = 195, AArch64_ADDv2i32 = 196, AArch64_ADDv2i64 = 197, AArch64_ADDv4i16 = 198, AArch64_ADDv4i32 = 199, AArch64_ADDv8i16 = 200, AArch64_ADDv8i8 = 201, AArch64_ADJCALLSTACKDOWN = 202, AArch64_ADJCALLSTACKUP = 203, AArch64_ADR = 204, AArch64_ADRP = 205, AArch64_ADR_LSL_ZZZ_D_0 = 206, AArch64_ADR_LSL_ZZZ_D_1 = 207, AArch64_ADR_LSL_ZZZ_D_2 = 208, AArch64_ADR_LSL_ZZZ_D_3 = 209, AArch64_ADR_LSL_ZZZ_S_0 = 210, AArch64_ADR_LSL_ZZZ_S_1 = 211, AArch64_ADR_LSL_ZZZ_S_2 = 212, AArch64_ADR_LSL_ZZZ_S_3 = 213, AArch64_ADR_SXTW_ZZZ_D_0 = 214, AArch64_ADR_SXTW_ZZZ_D_1 = 215, AArch64_ADR_SXTW_ZZZ_D_2 = 216, AArch64_ADR_SXTW_ZZZ_D_3 = 217, AArch64_ADR_UXTW_ZZZ_D_0 = 218, AArch64_ADR_UXTW_ZZZ_D_1 = 219, AArch64_ADR_UXTW_ZZZ_D_2 = 220, AArch64_ADR_UXTW_ZZZ_D_3 = 221, AArch64_AESDrr = 222, AArch64_AESErr = 223, AArch64_AESIMCrr = 224, AArch64_AESIMCrrTied = 225, AArch64_AESMCrr = 226, AArch64_AESMCrrTied = 227, AArch64_ANDSWri = 228, AArch64_ANDSWrr = 229, AArch64_ANDSWrs = 230, AArch64_ANDSXri = 231, AArch64_ANDSXrr = 232, AArch64_ANDSXrs = 233, AArch64_ANDS_PPzPP = 234, AArch64_ANDV_VPZ_B = 235, AArch64_ANDV_VPZ_D = 236, AArch64_ANDV_VPZ_H = 237, AArch64_ANDV_VPZ_S = 238, AArch64_ANDWri = 239, AArch64_ANDWrr = 240, AArch64_ANDWrs = 241, AArch64_ANDXri = 242, AArch64_ANDXrr = 243, AArch64_ANDXrs = 244, AArch64_AND_PPzPP = 245, AArch64_AND_ZI = 246, AArch64_AND_ZPmZ_B = 247, AArch64_AND_ZPmZ_D = 248, AArch64_AND_ZPmZ_H = 249, AArch64_AND_ZPmZ_S = 250, AArch64_AND_ZZZ = 251, AArch64_ANDv16i8 = 252, AArch64_ANDv8i8 = 253, AArch64_ASRD_ZPmI_B = 254, AArch64_ASRD_ZPmI_D = 255, AArch64_ASRD_ZPmI_H = 256, AArch64_ASRD_ZPmI_S = 257, AArch64_ASRR_ZPmZ_B = 258, AArch64_ASRR_ZPmZ_D = 259, AArch64_ASRR_ZPmZ_H = 260, AArch64_ASRR_ZPmZ_S = 261, AArch64_ASRVWr = 262, AArch64_ASRVXr = 263, AArch64_ASR_WIDE_ZPmZ_B = 264, AArch64_ASR_WIDE_ZPmZ_H = 265, AArch64_ASR_WIDE_ZPmZ_S = 266, AArch64_ASR_WIDE_ZZZ_B = 267, AArch64_ASR_WIDE_ZZZ_H = 268, AArch64_ASR_WIDE_ZZZ_S = 269, AArch64_ASR_ZPmI_B = 270, AArch64_ASR_ZPmI_D = 271, AArch64_ASR_ZPmI_H = 272, AArch64_ASR_ZPmI_S = 273, AArch64_ASR_ZPmZ_B = 274, AArch64_ASR_ZPmZ_D = 275, AArch64_ASR_ZPmZ_H = 276, AArch64_ASR_ZPmZ_S = 277, AArch64_ASR_ZZI_B = 278, AArch64_ASR_ZZI_D = 279, AArch64_ASR_ZZI_H = 280, AArch64_ASR_ZZI_S = 281, AArch64_AUTDA = 282, AArch64_AUTDB = 283, AArch64_AUTDZA = 284, AArch64_AUTDZB = 285, AArch64_AUTIA = 286, AArch64_AUTIA1716 = 287, AArch64_AUTIASP = 288, AArch64_AUTIAZ = 289, AArch64_AUTIB = 290, AArch64_AUTIB1716 = 291, AArch64_AUTIBSP = 292, AArch64_AUTIBZ = 293, AArch64_AUTIZA = 294, AArch64_AUTIZB = 295, AArch64_B = 296, AArch64_BCAX = 297, AArch64_BFMWri = 298, AArch64_BFMXri = 299, AArch64_BICSWrr = 300, AArch64_BICSWrs = 301, AArch64_BICSXrr = 302, AArch64_BICSXrs = 303, AArch64_BICS_PPzPP = 304, AArch64_BICWrr = 305, AArch64_BICWrs = 306, AArch64_BICXrr = 307, AArch64_BICXrs = 308, AArch64_BIC_PPzPP = 309, AArch64_BIC_ZPmZ_B = 310, AArch64_BIC_ZPmZ_D = 311, AArch64_BIC_ZPmZ_H = 312, AArch64_BIC_ZPmZ_S = 313, AArch64_BIC_ZZZ = 314, AArch64_BICv16i8 = 315, AArch64_BICv2i32 = 316, AArch64_BICv4i16 = 317, AArch64_BICv4i32 = 318, AArch64_BICv8i16 = 319, AArch64_BICv8i8 = 320, AArch64_BIFv16i8 = 321, AArch64_BIFv8i8 = 322, AArch64_BITv16i8 = 323, AArch64_BITv8i8 = 324, AArch64_BL = 325, AArch64_BLR = 326, AArch64_BLRAA = 327, AArch64_BLRAAZ = 328, AArch64_BLRAB = 329, AArch64_BLRABZ = 330, AArch64_BR = 331, AArch64_BRAA = 332, AArch64_BRAAZ = 333, AArch64_BRAB = 334, AArch64_BRABZ = 335, AArch64_BRK = 336, AArch64_BRKAS_PPzP = 337, AArch64_BRKA_PPmP = 338, AArch64_BRKA_PPzP = 339, AArch64_BRKBS_PPzP = 340, AArch64_BRKB_PPmP = 341, AArch64_BRKB_PPzP = 342, AArch64_BRKNS_PPzP = 343, AArch64_BRKN_PPzP = 344, AArch64_BRKPAS_PPzPP = 345, AArch64_BRKPA_PPzPP = 346, AArch64_BRKPBS_PPzPP = 347, AArch64_BRKPB_PPzPP = 348, AArch64_BSLv16i8 = 349, AArch64_BSLv8i8 = 350, AArch64_Bcc = 351, AArch64_CASAB = 352, AArch64_CASAH = 353, AArch64_CASALB = 354, AArch64_CASALH = 355, AArch64_CASALW = 356, AArch64_CASALX = 357, AArch64_CASAW = 358, AArch64_CASAX = 359, AArch64_CASB = 360, AArch64_CASH = 361, AArch64_CASLB = 362, AArch64_CASLH = 363, AArch64_CASLW = 364, AArch64_CASLX = 365, AArch64_CASPALW = 366, AArch64_CASPALX = 367, AArch64_CASPAW = 368, AArch64_CASPAX = 369, AArch64_CASPLW = 370, AArch64_CASPLX = 371, AArch64_CASPW = 372, AArch64_CASPX = 373, AArch64_CASW = 374, AArch64_CASX = 375, AArch64_CBNZW = 376, AArch64_CBNZX = 377, AArch64_CBZW = 378, AArch64_CBZX = 379, AArch64_CCMNWi = 380, AArch64_CCMNWr = 381, AArch64_CCMNXi = 382, AArch64_CCMNXr = 383, AArch64_CCMPWi = 384, AArch64_CCMPWr = 385, AArch64_CCMPXi = 386, AArch64_CCMPXr = 387, AArch64_CFINV = 388, AArch64_CLASTA_RPZ_B = 389, AArch64_CLASTA_RPZ_D = 390, AArch64_CLASTA_RPZ_H = 391, AArch64_CLASTA_RPZ_S = 392, AArch64_CLASTA_VPZ_B = 393, AArch64_CLASTA_VPZ_D = 394, AArch64_CLASTA_VPZ_H = 395, AArch64_CLASTA_VPZ_S = 396, AArch64_CLASTA_ZPZ_B = 397, AArch64_CLASTA_ZPZ_D = 398, AArch64_CLASTA_ZPZ_H = 399, AArch64_CLASTA_ZPZ_S = 400, AArch64_CLASTB_RPZ_B = 401, AArch64_CLASTB_RPZ_D = 402, AArch64_CLASTB_RPZ_H = 403, AArch64_CLASTB_RPZ_S = 404, AArch64_CLASTB_VPZ_B = 405, AArch64_CLASTB_VPZ_D = 406, AArch64_CLASTB_VPZ_H = 407, AArch64_CLASTB_VPZ_S = 408, AArch64_CLASTB_ZPZ_B = 409, AArch64_CLASTB_ZPZ_D = 410, AArch64_CLASTB_ZPZ_H = 411, AArch64_CLASTB_ZPZ_S = 412, AArch64_CLREX = 413, AArch64_CLSWr = 414, AArch64_CLSXr = 415, AArch64_CLS_ZPmZ_B = 416, AArch64_CLS_ZPmZ_D = 417, AArch64_CLS_ZPmZ_H = 418, AArch64_CLS_ZPmZ_S = 419, AArch64_CLSv16i8 = 420, AArch64_CLSv2i32 = 421, AArch64_CLSv4i16 = 422, AArch64_CLSv4i32 = 423, AArch64_CLSv8i16 = 424, AArch64_CLSv8i8 = 425, AArch64_CLZWr = 426, AArch64_CLZXr = 427, AArch64_CLZ_ZPmZ_B = 428, AArch64_CLZ_ZPmZ_D = 429, AArch64_CLZ_ZPmZ_H = 430, AArch64_CLZ_ZPmZ_S = 431, AArch64_CLZv16i8 = 432, AArch64_CLZv2i32 = 433, AArch64_CLZv4i16 = 434, AArch64_CLZv4i32 = 435, AArch64_CLZv8i16 = 436, AArch64_CLZv8i8 = 437, AArch64_CMEQv16i8 = 438, AArch64_CMEQv16i8rz = 439, AArch64_CMEQv1i64 = 440, AArch64_CMEQv1i64rz = 441, AArch64_CMEQv2i32 = 442, AArch64_CMEQv2i32rz = 443, AArch64_CMEQv2i64 = 444, AArch64_CMEQv2i64rz = 445, AArch64_CMEQv4i16 = 446, AArch64_CMEQv4i16rz = 447, AArch64_CMEQv4i32 = 448, AArch64_CMEQv4i32rz = 449, AArch64_CMEQv8i16 = 450, AArch64_CMEQv8i16rz = 451, AArch64_CMEQv8i8 = 452, AArch64_CMEQv8i8rz = 453, AArch64_CMGEv16i8 = 454, AArch64_CMGEv16i8rz = 455, AArch64_CMGEv1i64 = 456, AArch64_CMGEv1i64rz = 457, AArch64_CMGEv2i32 = 458, AArch64_CMGEv2i32rz = 459, AArch64_CMGEv2i64 = 460, AArch64_CMGEv2i64rz = 461, AArch64_CMGEv4i16 = 462, AArch64_CMGEv4i16rz = 463, AArch64_CMGEv4i32 = 464, AArch64_CMGEv4i32rz = 465, AArch64_CMGEv8i16 = 466, AArch64_CMGEv8i16rz = 467, AArch64_CMGEv8i8 = 468, AArch64_CMGEv8i8rz = 469, AArch64_CMGTv16i8 = 470, AArch64_CMGTv16i8rz = 471, AArch64_CMGTv1i64 = 472, AArch64_CMGTv1i64rz = 473, AArch64_CMGTv2i32 = 474, AArch64_CMGTv2i32rz = 475, AArch64_CMGTv2i64 = 476, AArch64_CMGTv2i64rz = 477, AArch64_CMGTv4i16 = 478, AArch64_CMGTv4i16rz = 479, AArch64_CMGTv4i32 = 480, AArch64_CMGTv4i32rz = 481, AArch64_CMGTv8i16 = 482, AArch64_CMGTv8i16rz = 483, AArch64_CMGTv8i8 = 484, AArch64_CMGTv8i8rz = 485, AArch64_CMHIv16i8 = 486, AArch64_CMHIv1i64 = 487, AArch64_CMHIv2i32 = 488, AArch64_CMHIv2i64 = 489, AArch64_CMHIv4i16 = 490, AArch64_CMHIv4i32 = 491, AArch64_CMHIv8i16 = 492, AArch64_CMHIv8i8 = 493, AArch64_CMHSv16i8 = 494, AArch64_CMHSv1i64 = 495, AArch64_CMHSv2i32 = 496, AArch64_CMHSv2i64 = 497, AArch64_CMHSv4i16 = 498, AArch64_CMHSv4i32 = 499, AArch64_CMHSv8i16 = 500, AArch64_CMHSv8i8 = 501, AArch64_CMLEv16i8rz = 502, AArch64_CMLEv1i64rz = 503, AArch64_CMLEv2i32rz = 504, AArch64_CMLEv2i64rz = 505, AArch64_CMLEv4i16rz = 506, AArch64_CMLEv4i32rz = 507, AArch64_CMLEv8i16rz = 508, AArch64_CMLEv8i8rz = 509, AArch64_CMLTv16i8rz = 510, AArch64_CMLTv1i64rz = 511, AArch64_CMLTv2i32rz = 512, AArch64_CMLTv2i64rz = 513, AArch64_CMLTv4i16rz = 514, AArch64_CMLTv4i32rz = 515, AArch64_CMLTv8i16rz = 516, AArch64_CMLTv8i8rz = 517, AArch64_CMPEQ_PPzZI_B = 518, AArch64_CMPEQ_PPzZI_D = 519, AArch64_CMPEQ_PPzZI_H = 520, AArch64_CMPEQ_PPzZI_S = 521, AArch64_CMPEQ_PPzZZ_B = 522, AArch64_CMPEQ_PPzZZ_D = 523, AArch64_CMPEQ_PPzZZ_H = 524, AArch64_CMPEQ_PPzZZ_S = 525, AArch64_CMPEQ_WIDE_PPzZZ_B = 526, AArch64_CMPEQ_WIDE_PPzZZ_H = 527, AArch64_CMPEQ_WIDE_PPzZZ_S = 528, AArch64_CMPGE_PPzZI_B = 529, AArch64_CMPGE_PPzZI_D = 530, AArch64_CMPGE_PPzZI_H = 531, AArch64_CMPGE_PPzZI_S = 532, AArch64_CMPGE_PPzZZ_B = 533, AArch64_CMPGE_PPzZZ_D = 534, AArch64_CMPGE_PPzZZ_H = 535, AArch64_CMPGE_PPzZZ_S = 536, AArch64_CMPGE_WIDE_PPzZZ_B = 537, AArch64_CMPGE_WIDE_PPzZZ_H = 538, AArch64_CMPGE_WIDE_PPzZZ_S = 539, AArch64_CMPGT_PPzZI_B = 540, AArch64_CMPGT_PPzZI_D = 541, AArch64_CMPGT_PPzZI_H = 542, AArch64_CMPGT_PPzZI_S = 543, AArch64_CMPGT_PPzZZ_B = 544, AArch64_CMPGT_PPzZZ_D = 545, AArch64_CMPGT_PPzZZ_H = 546, AArch64_CMPGT_PPzZZ_S = 547, AArch64_CMPGT_WIDE_PPzZZ_B = 548, AArch64_CMPGT_WIDE_PPzZZ_H = 549, AArch64_CMPGT_WIDE_PPzZZ_S = 550, AArch64_CMPHI_PPzZI_B = 551, AArch64_CMPHI_PPzZI_D = 552, AArch64_CMPHI_PPzZI_H = 553, AArch64_CMPHI_PPzZI_S = 554, AArch64_CMPHI_PPzZZ_B = 555, AArch64_CMPHI_PPzZZ_D = 556, AArch64_CMPHI_PPzZZ_H = 557, AArch64_CMPHI_PPzZZ_S = 558, AArch64_CMPHI_WIDE_PPzZZ_B = 559, AArch64_CMPHI_WIDE_PPzZZ_H = 560, AArch64_CMPHI_WIDE_PPzZZ_S = 561, AArch64_CMPHS_PPzZI_B = 562, AArch64_CMPHS_PPzZI_D = 563, AArch64_CMPHS_PPzZI_H = 564, AArch64_CMPHS_PPzZI_S = 565, AArch64_CMPHS_PPzZZ_B = 566, AArch64_CMPHS_PPzZZ_D = 567, AArch64_CMPHS_PPzZZ_H = 568, AArch64_CMPHS_PPzZZ_S = 569, AArch64_CMPHS_WIDE_PPzZZ_B = 570, AArch64_CMPHS_WIDE_PPzZZ_H = 571, AArch64_CMPHS_WIDE_PPzZZ_S = 572, AArch64_CMPLE_PPzZI_B = 573, AArch64_CMPLE_PPzZI_D = 574, AArch64_CMPLE_PPzZI_H = 575, AArch64_CMPLE_PPzZI_S = 576, AArch64_CMPLE_WIDE_PPzZZ_B = 577, AArch64_CMPLE_WIDE_PPzZZ_H = 578, AArch64_CMPLE_WIDE_PPzZZ_S = 579, AArch64_CMPLO_PPzZI_B = 580, AArch64_CMPLO_PPzZI_D = 581, AArch64_CMPLO_PPzZI_H = 582, AArch64_CMPLO_PPzZI_S = 583, AArch64_CMPLO_WIDE_PPzZZ_B = 584, AArch64_CMPLO_WIDE_PPzZZ_H = 585, AArch64_CMPLO_WIDE_PPzZZ_S = 586, AArch64_CMPLS_PPzZI_B = 587, AArch64_CMPLS_PPzZI_D = 588, AArch64_CMPLS_PPzZI_H = 589, AArch64_CMPLS_PPzZI_S = 590, AArch64_CMPLS_WIDE_PPzZZ_B = 591, AArch64_CMPLS_WIDE_PPzZZ_H = 592, AArch64_CMPLS_WIDE_PPzZZ_S = 593, AArch64_CMPLT_PPzZI_B = 594, AArch64_CMPLT_PPzZI_D = 595, AArch64_CMPLT_PPzZI_H = 596, AArch64_CMPLT_PPzZI_S = 597, AArch64_CMPLT_WIDE_PPzZZ_B = 598, AArch64_CMPLT_WIDE_PPzZZ_H = 599, AArch64_CMPLT_WIDE_PPzZZ_S = 600, AArch64_CMPNE_PPzZI_B = 601, AArch64_CMPNE_PPzZI_D = 602, AArch64_CMPNE_PPzZI_H = 603, AArch64_CMPNE_PPzZI_S = 604, AArch64_CMPNE_PPzZZ_B = 605, AArch64_CMPNE_PPzZZ_D = 606, AArch64_CMPNE_PPzZZ_H = 607, AArch64_CMPNE_PPzZZ_S = 608, AArch64_CMPNE_WIDE_PPzZZ_B = 609, AArch64_CMPNE_WIDE_PPzZZ_H = 610, AArch64_CMPNE_WIDE_PPzZZ_S = 611, AArch64_CMP_SWAP_128 = 612, AArch64_CMP_SWAP_16 = 613, AArch64_CMP_SWAP_32 = 614, AArch64_CMP_SWAP_64 = 615, AArch64_CMP_SWAP_8 = 616, AArch64_CMTSTv16i8 = 617, AArch64_CMTSTv1i64 = 618, AArch64_CMTSTv2i32 = 619, AArch64_CMTSTv2i64 = 620, AArch64_CMTSTv4i16 = 621, AArch64_CMTSTv4i32 = 622, AArch64_CMTSTv8i16 = 623, AArch64_CMTSTv8i8 = 624, AArch64_CNOT_ZPmZ_B = 625, AArch64_CNOT_ZPmZ_D = 626, AArch64_CNOT_ZPmZ_H = 627, AArch64_CNOT_ZPmZ_S = 628, AArch64_CNTB_XPiI = 629, AArch64_CNTD_XPiI = 630, AArch64_CNTH_XPiI = 631, AArch64_CNTP_XPP_B = 632, AArch64_CNTP_XPP_D = 633, AArch64_CNTP_XPP_H = 634, AArch64_CNTP_XPP_S = 635, AArch64_CNTW_XPiI = 636, AArch64_CNT_ZPmZ_B = 637, AArch64_CNT_ZPmZ_D = 638, AArch64_CNT_ZPmZ_H = 639, AArch64_CNT_ZPmZ_S = 640, AArch64_CNTv16i8 = 641, AArch64_CNTv8i8 = 642, AArch64_COMPACT_ZPZ_D = 643, AArch64_COMPACT_ZPZ_S = 644, AArch64_CPY_ZPmI_B = 645, AArch64_CPY_ZPmI_D = 646, AArch64_CPY_ZPmI_H = 647, AArch64_CPY_ZPmI_S = 648, AArch64_CPY_ZPmR_B = 649, AArch64_CPY_ZPmR_D = 650, AArch64_CPY_ZPmR_H = 651, AArch64_CPY_ZPmR_S = 652, AArch64_CPY_ZPmV_B = 653, AArch64_CPY_ZPmV_D = 654, AArch64_CPY_ZPmV_H = 655, AArch64_CPY_ZPmV_S = 656, AArch64_CPY_ZPzI_B = 657, AArch64_CPY_ZPzI_D = 658, AArch64_CPY_ZPzI_H = 659, AArch64_CPY_ZPzI_S = 660, AArch64_CPYi16 = 661, AArch64_CPYi32 = 662, AArch64_CPYi64 = 663, AArch64_CPYi8 = 664, AArch64_CRC32Brr = 665, AArch64_CRC32CBrr = 666, AArch64_CRC32CHrr = 667, AArch64_CRC32CWrr = 668, AArch64_CRC32CXrr = 669, AArch64_CRC32Hrr = 670, AArch64_CRC32Wrr = 671, AArch64_CRC32Xrr = 672, AArch64_CSELWr = 673, AArch64_CSELXr = 674, AArch64_CSINCWr = 675, AArch64_CSINCXr = 676, AArch64_CSINVWr = 677, AArch64_CSINVXr = 678, AArch64_CSNEGWr = 679, AArch64_CSNEGXr = 680, AArch64_CTERMEQ_WW = 681, AArch64_CTERMEQ_XX = 682, AArch64_CTERMNE_WW = 683, AArch64_CTERMNE_XX = 684, AArch64_CompilerBarrier = 685, AArch64_DCPS1 = 686, AArch64_DCPS2 = 687, AArch64_DCPS3 = 688, AArch64_DECB_XPiI = 689, AArch64_DECD_XPiI = 690, AArch64_DECD_ZPiI = 691, AArch64_DECH_XPiI = 692, AArch64_DECH_ZPiI = 693, AArch64_DECP_XP_B = 694, AArch64_DECP_XP_D = 695, AArch64_DECP_XP_H = 696, AArch64_DECP_XP_S = 697, AArch64_DECP_ZP_D = 698, AArch64_DECP_ZP_H = 699, AArch64_DECP_ZP_S = 700, AArch64_DECW_XPiI = 701, AArch64_DECW_ZPiI = 702, AArch64_DMB = 703, AArch64_DRPS = 704, AArch64_DSB = 705, AArch64_DUPM_ZI = 706, AArch64_DUP_ZI_B = 707, AArch64_DUP_ZI_D = 708, AArch64_DUP_ZI_H = 709, AArch64_DUP_ZI_S = 710, AArch64_DUP_ZR_B = 711, AArch64_DUP_ZR_D = 712, AArch64_DUP_ZR_H = 713, AArch64_DUP_ZR_S = 714, AArch64_DUP_ZZI_B = 715, AArch64_DUP_ZZI_D = 716, AArch64_DUP_ZZI_H = 717, AArch64_DUP_ZZI_Q = 718, AArch64_DUP_ZZI_S = 719, AArch64_DUPv16i8gpr = 720, AArch64_DUPv16i8lane = 721, AArch64_DUPv2i32gpr = 722, AArch64_DUPv2i32lane = 723, AArch64_DUPv2i64gpr = 724, AArch64_DUPv2i64lane = 725, AArch64_DUPv4i16gpr = 726, AArch64_DUPv4i16lane = 727, AArch64_DUPv4i32gpr = 728, AArch64_DUPv4i32lane = 729, AArch64_DUPv8i16gpr = 730, AArch64_DUPv8i16lane = 731, AArch64_DUPv8i8gpr = 732, AArch64_DUPv8i8lane = 733, AArch64_EONWrr = 734, AArch64_EONWrs = 735, AArch64_EONXrr = 736, AArch64_EONXrs = 737, AArch64_EOR3 = 738, AArch64_EORS_PPzPP = 739, AArch64_EORV_VPZ_B = 740, AArch64_EORV_VPZ_D = 741, AArch64_EORV_VPZ_H = 742, AArch64_EORV_VPZ_S = 743, AArch64_EORWri = 744, AArch64_EORWrr = 745, AArch64_EORWrs = 746, AArch64_EORXri = 747, AArch64_EORXrr = 748, AArch64_EORXrs = 749, AArch64_EOR_PPzPP = 750, AArch64_EOR_ZI = 751, AArch64_EOR_ZPmZ_B = 752, AArch64_EOR_ZPmZ_D = 753, AArch64_EOR_ZPmZ_H = 754, AArch64_EOR_ZPmZ_S = 755, AArch64_EOR_ZZZ = 756, AArch64_EORv16i8 = 757, AArch64_EORv8i8 = 758, AArch64_ERET = 759, AArch64_ERETAA = 760, AArch64_ERETAB = 761, AArch64_EXTRWrri = 762, AArch64_EXTRXrri = 763, AArch64_EXT_ZZI = 764, AArch64_EXTv16i8 = 765, AArch64_EXTv8i8 = 766, AArch64_F128CSEL = 767, AArch64_FABD16 = 768, AArch64_FABD32 = 769, AArch64_FABD64 = 770, AArch64_FABD_ZPmZ_D = 771, AArch64_FABD_ZPmZ_H = 772, AArch64_FABD_ZPmZ_S = 773, AArch64_FABDv2f32 = 774, AArch64_FABDv2f64 = 775, AArch64_FABDv4f16 = 776, AArch64_FABDv4f32 = 777, AArch64_FABDv8f16 = 778, AArch64_FABSDr = 779, AArch64_FABSHr = 780, AArch64_FABSSr = 781, AArch64_FABS_ZPmZ_D = 782, AArch64_FABS_ZPmZ_H = 783, AArch64_FABS_ZPmZ_S = 784, AArch64_FABSv2f32 = 785, AArch64_FABSv2f64 = 786, AArch64_FABSv4f16 = 787, AArch64_FABSv4f32 = 788, AArch64_FABSv8f16 = 789, AArch64_FACGE16 = 790, AArch64_FACGE32 = 791, AArch64_FACGE64 = 792, AArch64_FACGE_PPzZZ_D = 793, AArch64_FACGE_PPzZZ_H = 794, AArch64_FACGE_PPzZZ_S = 795, AArch64_FACGEv2f32 = 796, AArch64_FACGEv2f64 = 797, AArch64_FACGEv4f16 = 798, AArch64_FACGEv4f32 = 799, AArch64_FACGEv8f16 = 800, AArch64_FACGT16 = 801, AArch64_FACGT32 = 802, AArch64_FACGT64 = 803, AArch64_FACGT_PPzZZ_D = 804, AArch64_FACGT_PPzZZ_H = 805, AArch64_FACGT_PPzZZ_S = 806, AArch64_FACGTv2f32 = 807, AArch64_FACGTv2f64 = 808, AArch64_FACGTv4f16 = 809, AArch64_FACGTv4f32 = 810, AArch64_FACGTv8f16 = 811, AArch64_FADDA_VPZ_D = 812, AArch64_FADDA_VPZ_H = 813, AArch64_FADDA_VPZ_S = 814, AArch64_FADDDrr = 815, AArch64_FADDHrr = 816, AArch64_FADDPv2f32 = 817, AArch64_FADDPv2f64 = 818, AArch64_FADDPv2i16p = 819, AArch64_FADDPv2i32p = 820, AArch64_FADDPv2i64p = 821, AArch64_FADDPv4f16 = 822, AArch64_FADDPv4f32 = 823, AArch64_FADDPv8f16 = 824, AArch64_FADDSrr = 825, AArch64_FADDV_VPZ_D = 826, AArch64_FADDV_VPZ_H = 827, AArch64_FADDV_VPZ_S = 828, AArch64_FADD_ZPmI_D = 829, AArch64_FADD_ZPmI_H = 830, AArch64_FADD_ZPmI_S = 831, AArch64_FADD_ZPmZ_D = 832, AArch64_FADD_ZPmZ_H = 833, AArch64_FADD_ZPmZ_S = 834, AArch64_FADD_ZZZ_D = 835, AArch64_FADD_ZZZ_H = 836, AArch64_FADD_ZZZ_S = 837, AArch64_FADDv2f32 = 838, AArch64_FADDv2f64 = 839, AArch64_FADDv4f16 = 840, AArch64_FADDv4f32 = 841, AArch64_FADDv8f16 = 842, AArch64_FCADD_ZPmZ_D = 843, AArch64_FCADD_ZPmZ_H = 844, AArch64_FCADD_ZPmZ_S = 845, AArch64_FCADDv2f32 = 846, AArch64_FCADDv2f64 = 847, AArch64_FCADDv4f16 = 848, AArch64_FCADDv4f32 = 849, AArch64_FCADDv8f16 = 850, AArch64_FCCMPDrr = 851, AArch64_FCCMPEDrr = 852, AArch64_FCCMPEHrr = 853, AArch64_FCCMPESrr = 854, AArch64_FCCMPHrr = 855, AArch64_FCCMPSrr = 856, AArch64_FCMEQ16 = 857, AArch64_FCMEQ32 = 858, AArch64_FCMEQ64 = 859, AArch64_FCMEQ_PPzZ0_D = 860, AArch64_FCMEQ_PPzZ0_H = 861, AArch64_FCMEQ_PPzZ0_S = 862, AArch64_FCMEQ_PPzZZ_D = 863, AArch64_FCMEQ_PPzZZ_H = 864, AArch64_FCMEQ_PPzZZ_S = 865, AArch64_FCMEQv1i16rz = 866, AArch64_FCMEQv1i32rz = 867, AArch64_FCMEQv1i64rz = 868, AArch64_FCMEQv2f32 = 869, AArch64_FCMEQv2f64 = 870, AArch64_FCMEQv2i32rz = 871, AArch64_FCMEQv2i64rz = 872, AArch64_FCMEQv4f16 = 873, AArch64_FCMEQv4f32 = 874, AArch64_FCMEQv4i16rz = 875, AArch64_FCMEQv4i32rz = 876, AArch64_FCMEQv8f16 = 877, AArch64_FCMEQv8i16rz = 878, AArch64_FCMGE16 = 879, AArch64_FCMGE32 = 880, AArch64_FCMGE64 = 881, AArch64_FCMGE_PPzZ0_D = 882, AArch64_FCMGE_PPzZ0_H = 883, AArch64_FCMGE_PPzZ0_S = 884, AArch64_FCMGE_PPzZZ_D = 885, AArch64_FCMGE_PPzZZ_H = 886, AArch64_FCMGE_PPzZZ_S = 887, AArch64_FCMGEv1i16rz = 888, AArch64_FCMGEv1i32rz = 889, AArch64_FCMGEv1i64rz = 890, AArch64_FCMGEv2f32 = 891, AArch64_FCMGEv2f64 = 892, AArch64_FCMGEv2i32rz = 893, AArch64_FCMGEv2i64rz = 894, AArch64_FCMGEv4f16 = 895, AArch64_FCMGEv4f32 = 896, AArch64_FCMGEv4i16rz = 897, AArch64_FCMGEv4i32rz = 898, AArch64_FCMGEv8f16 = 899, AArch64_FCMGEv8i16rz = 900, AArch64_FCMGT16 = 901, AArch64_FCMGT32 = 902, AArch64_FCMGT64 = 903, AArch64_FCMGT_PPzZ0_D = 904, AArch64_FCMGT_PPzZ0_H = 905, AArch64_FCMGT_PPzZ0_S = 906, AArch64_FCMGT_PPzZZ_D = 907, AArch64_FCMGT_PPzZZ_H = 908, AArch64_FCMGT_PPzZZ_S = 909, AArch64_FCMGTv1i16rz = 910, AArch64_FCMGTv1i32rz = 911, AArch64_FCMGTv1i64rz = 912, AArch64_FCMGTv2f32 = 913, AArch64_FCMGTv2f64 = 914, AArch64_FCMGTv2i32rz = 915, AArch64_FCMGTv2i64rz = 916, AArch64_FCMGTv4f16 = 917, AArch64_FCMGTv4f32 = 918, AArch64_FCMGTv4i16rz = 919, AArch64_FCMGTv4i32rz = 920, AArch64_FCMGTv8f16 = 921, AArch64_FCMGTv8i16rz = 922, AArch64_FCMLA_ZPmZZ_D = 923, AArch64_FCMLA_ZPmZZ_H = 924, AArch64_FCMLA_ZPmZZ_S = 925, AArch64_FCMLA_ZZZI_H = 926, AArch64_FCMLA_ZZZI_S = 927, AArch64_FCMLAv2f32 = 928, AArch64_FCMLAv2f64 = 929, AArch64_FCMLAv4f16 = 930, AArch64_FCMLAv4f16_indexed = 931, AArch64_FCMLAv4f32 = 932, AArch64_FCMLAv4f32_indexed = 933, AArch64_FCMLAv8f16 = 934, AArch64_FCMLAv8f16_indexed = 935, AArch64_FCMLE_PPzZ0_D = 936, AArch64_FCMLE_PPzZ0_H = 937, AArch64_FCMLE_PPzZ0_S = 938, AArch64_FCMLEv1i16rz = 939, AArch64_FCMLEv1i32rz = 940, AArch64_FCMLEv1i64rz = 941, AArch64_FCMLEv2i32rz = 942, AArch64_FCMLEv2i64rz = 943, AArch64_FCMLEv4i16rz = 944, AArch64_FCMLEv4i32rz = 945, AArch64_FCMLEv8i16rz = 946, AArch64_FCMLT_PPzZ0_D = 947, AArch64_FCMLT_PPzZ0_H = 948, AArch64_FCMLT_PPzZ0_S = 949, AArch64_FCMLTv1i16rz = 950, AArch64_FCMLTv1i32rz = 951, AArch64_FCMLTv1i64rz = 952, AArch64_FCMLTv2i32rz = 953, AArch64_FCMLTv2i64rz = 954, AArch64_FCMLTv4i16rz = 955, AArch64_FCMLTv4i32rz = 956, AArch64_FCMLTv8i16rz = 957, AArch64_FCMNE_PPzZ0_D = 958, AArch64_FCMNE_PPzZ0_H = 959, AArch64_FCMNE_PPzZ0_S = 960, AArch64_FCMNE_PPzZZ_D = 961, AArch64_FCMNE_PPzZZ_H = 962, AArch64_FCMNE_PPzZZ_S = 963, AArch64_FCMPDri = 964, AArch64_FCMPDrr = 965, AArch64_FCMPEDri = 966, AArch64_FCMPEDrr = 967, AArch64_FCMPEHri = 968, AArch64_FCMPEHrr = 969, AArch64_FCMPESri = 970, AArch64_FCMPESrr = 971, AArch64_FCMPHri = 972, AArch64_FCMPHrr = 973, AArch64_FCMPSri = 974, AArch64_FCMPSrr = 975, AArch64_FCMUO_PPzZZ_D = 976, AArch64_FCMUO_PPzZZ_H = 977, AArch64_FCMUO_PPzZZ_S = 978, AArch64_FCPY_ZPmI_D = 979, AArch64_FCPY_ZPmI_H = 980, AArch64_FCPY_ZPmI_S = 981, AArch64_FCSELDrrr = 982, AArch64_FCSELHrrr = 983, AArch64_FCSELSrrr = 984, AArch64_FCVTASUWDr = 985, AArch64_FCVTASUWHr = 986, AArch64_FCVTASUWSr = 987, AArch64_FCVTASUXDr = 988, AArch64_FCVTASUXHr = 989, AArch64_FCVTASUXSr = 990, AArch64_FCVTASv1f16 = 991, AArch64_FCVTASv1i32 = 992, AArch64_FCVTASv1i64 = 993, AArch64_FCVTASv2f32 = 994, AArch64_FCVTASv2f64 = 995, AArch64_FCVTASv4f16 = 996, AArch64_FCVTASv4f32 = 997, AArch64_FCVTASv8f16 = 998, AArch64_FCVTAUUWDr = 999, AArch64_FCVTAUUWHr = 1000, AArch64_FCVTAUUWSr = 1001, AArch64_FCVTAUUXDr = 1002, AArch64_FCVTAUUXHr = 1003, AArch64_FCVTAUUXSr = 1004, AArch64_FCVTAUv1f16 = 1005, AArch64_FCVTAUv1i32 = 1006, AArch64_FCVTAUv1i64 = 1007, AArch64_FCVTAUv2f32 = 1008, AArch64_FCVTAUv2f64 = 1009, AArch64_FCVTAUv4f16 = 1010, AArch64_FCVTAUv4f32 = 1011, AArch64_FCVTAUv8f16 = 1012, AArch64_FCVTDHr = 1013, AArch64_FCVTDSr = 1014, AArch64_FCVTHDr = 1015, AArch64_FCVTHSr = 1016, AArch64_FCVTLv2i32 = 1017, AArch64_FCVTLv4i16 = 1018, AArch64_FCVTLv4i32 = 1019, AArch64_FCVTLv8i16 = 1020, AArch64_FCVTMSUWDr = 1021, AArch64_FCVTMSUWHr = 1022, AArch64_FCVTMSUWSr = 1023, AArch64_FCVTMSUXDr = 1024, AArch64_FCVTMSUXHr = 1025, AArch64_FCVTMSUXSr = 1026, AArch64_FCVTMSv1f16 = 1027, AArch64_FCVTMSv1i32 = 1028, AArch64_FCVTMSv1i64 = 1029, AArch64_FCVTMSv2f32 = 1030, AArch64_FCVTMSv2f64 = 1031, AArch64_FCVTMSv4f16 = 1032, AArch64_FCVTMSv4f32 = 1033, AArch64_FCVTMSv8f16 = 1034, AArch64_FCVTMUUWDr = 1035, AArch64_FCVTMUUWHr = 1036, AArch64_FCVTMUUWSr = 1037, AArch64_FCVTMUUXDr = 1038, AArch64_FCVTMUUXHr = 1039, AArch64_FCVTMUUXSr = 1040, AArch64_FCVTMUv1f16 = 1041, AArch64_FCVTMUv1i32 = 1042, AArch64_FCVTMUv1i64 = 1043, AArch64_FCVTMUv2f32 = 1044, AArch64_FCVTMUv2f64 = 1045, AArch64_FCVTMUv4f16 = 1046, AArch64_FCVTMUv4f32 = 1047, AArch64_FCVTMUv8f16 = 1048, AArch64_FCVTNSUWDr = 1049, AArch64_FCVTNSUWHr = 1050, AArch64_FCVTNSUWSr = 1051, AArch64_FCVTNSUXDr = 1052, AArch64_FCVTNSUXHr = 1053, AArch64_FCVTNSUXSr = 1054, AArch64_FCVTNSv1f16 = 1055, AArch64_FCVTNSv1i32 = 1056, AArch64_FCVTNSv1i64 = 1057, AArch64_FCVTNSv2f32 = 1058, AArch64_FCVTNSv2f64 = 1059, AArch64_FCVTNSv4f16 = 1060, AArch64_FCVTNSv4f32 = 1061, AArch64_FCVTNSv8f16 = 1062, AArch64_FCVTNUUWDr = 1063, AArch64_FCVTNUUWHr = 1064, AArch64_FCVTNUUWSr = 1065, AArch64_FCVTNUUXDr = 1066, AArch64_FCVTNUUXHr = 1067, AArch64_FCVTNUUXSr = 1068, AArch64_FCVTNUv1f16 = 1069, AArch64_FCVTNUv1i32 = 1070, AArch64_FCVTNUv1i64 = 1071, AArch64_FCVTNUv2f32 = 1072, AArch64_FCVTNUv2f64 = 1073, AArch64_FCVTNUv4f16 = 1074, AArch64_FCVTNUv4f32 = 1075, AArch64_FCVTNUv8f16 = 1076, AArch64_FCVTNv2i32 = 1077, AArch64_FCVTNv4i16 = 1078, AArch64_FCVTNv4i32 = 1079, AArch64_FCVTNv8i16 = 1080, AArch64_FCVTPSUWDr = 1081, AArch64_FCVTPSUWHr = 1082, AArch64_FCVTPSUWSr = 1083, AArch64_FCVTPSUXDr = 1084, AArch64_FCVTPSUXHr = 1085, AArch64_FCVTPSUXSr = 1086, AArch64_FCVTPSv1f16 = 1087, AArch64_FCVTPSv1i32 = 1088, AArch64_FCVTPSv1i64 = 1089, AArch64_FCVTPSv2f32 = 1090, AArch64_FCVTPSv2f64 = 1091, AArch64_FCVTPSv4f16 = 1092, AArch64_FCVTPSv4f32 = 1093, AArch64_FCVTPSv8f16 = 1094, AArch64_FCVTPUUWDr = 1095, AArch64_FCVTPUUWHr = 1096, AArch64_FCVTPUUWSr = 1097, AArch64_FCVTPUUXDr = 1098, AArch64_FCVTPUUXHr = 1099, AArch64_FCVTPUUXSr = 1100, AArch64_FCVTPUv1f16 = 1101, AArch64_FCVTPUv1i32 = 1102, AArch64_FCVTPUv1i64 = 1103, AArch64_FCVTPUv2f32 = 1104, AArch64_FCVTPUv2f64 = 1105, AArch64_FCVTPUv4f16 = 1106, AArch64_FCVTPUv4f32 = 1107, AArch64_FCVTPUv8f16 = 1108, AArch64_FCVTSDr = 1109, AArch64_FCVTSHr = 1110, AArch64_FCVTXNv1i64 = 1111, AArch64_FCVTXNv2f32 = 1112, AArch64_FCVTXNv4f32 = 1113, AArch64_FCVTZSSWDri = 1114, AArch64_FCVTZSSWHri = 1115, AArch64_FCVTZSSWSri = 1116, AArch64_FCVTZSSXDri = 1117, AArch64_FCVTZSSXHri = 1118, AArch64_FCVTZSSXSri = 1119, AArch64_FCVTZSUWDr = 1120, AArch64_FCVTZSUWHr = 1121, AArch64_FCVTZSUWSr = 1122, AArch64_FCVTZSUXDr = 1123, AArch64_FCVTZSUXHr = 1124, AArch64_FCVTZSUXSr = 1125, AArch64_FCVTZS_ZPmZ_DtoD = 1126, AArch64_FCVTZS_ZPmZ_DtoS = 1127, AArch64_FCVTZS_ZPmZ_HtoD = 1128, AArch64_FCVTZS_ZPmZ_HtoH = 1129, AArch64_FCVTZS_ZPmZ_HtoS = 1130, AArch64_FCVTZS_ZPmZ_StoD = 1131, AArch64_FCVTZS_ZPmZ_StoS = 1132, AArch64_FCVTZSd = 1133, AArch64_FCVTZSh = 1134, AArch64_FCVTZSs = 1135, AArch64_FCVTZSv1f16 = 1136, AArch64_FCVTZSv1i32 = 1137, AArch64_FCVTZSv1i64 = 1138, AArch64_FCVTZSv2f32 = 1139, AArch64_FCVTZSv2f64 = 1140, AArch64_FCVTZSv2i32_shift = 1141, AArch64_FCVTZSv2i64_shift = 1142, AArch64_FCVTZSv4f16 = 1143, AArch64_FCVTZSv4f32 = 1144, AArch64_FCVTZSv4i16_shift = 1145, AArch64_FCVTZSv4i32_shift = 1146, AArch64_FCVTZSv8f16 = 1147, AArch64_FCVTZSv8i16_shift = 1148, AArch64_FCVTZUSWDri = 1149, AArch64_FCVTZUSWHri = 1150, AArch64_FCVTZUSWSri = 1151, AArch64_FCVTZUSXDri = 1152, AArch64_FCVTZUSXHri = 1153, AArch64_FCVTZUSXSri = 1154, AArch64_FCVTZUUWDr = 1155, AArch64_FCVTZUUWHr = 1156, AArch64_FCVTZUUWSr = 1157, AArch64_FCVTZUUXDr = 1158, AArch64_FCVTZUUXHr = 1159, AArch64_FCVTZUUXSr = 1160, AArch64_FCVTZU_ZPmZ_DtoD = 1161, AArch64_FCVTZU_ZPmZ_DtoS = 1162, AArch64_FCVTZU_ZPmZ_HtoD = 1163, AArch64_FCVTZU_ZPmZ_HtoH = 1164, AArch64_FCVTZU_ZPmZ_HtoS = 1165, AArch64_FCVTZU_ZPmZ_StoD = 1166, AArch64_FCVTZU_ZPmZ_StoS = 1167, AArch64_FCVTZUd = 1168, AArch64_FCVTZUh = 1169, AArch64_FCVTZUs = 1170, AArch64_FCVTZUv1f16 = 1171, AArch64_FCVTZUv1i32 = 1172, AArch64_FCVTZUv1i64 = 1173, AArch64_FCVTZUv2f32 = 1174, AArch64_FCVTZUv2f64 = 1175, AArch64_FCVTZUv2i32_shift = 1176, AArch64_FCVTZUv2i64_shift = 1177, AArch64_FCVTZUv4f16 = 1178, AArch64_FCVTZUv4f32 = 1179, AArch64_FCVTZUv4i16_shift = 1180, AArch64_FCVTZUv4i32_shift = 1181, AArch64_FCVTZUv8f16 = 1182, AArch64_FCVTZUv8i16_shift = 1183, AArch64_FCVT_ZPmZ_DtoH = 1184, AArch64_FCVT_ZPmZ_DtoS = 1185, AArch64_FCVT_ZPmZ_HtoD = 1186, AArch64_FCVT_ZPmZ_HtoS = 1187, AArch64_FCVT_ZPmZ_StoD = 1188, AArch64_FCVT_ZPmZ_StoH = 1189, AArch64_FDIVDrr = 1190, AArch64_FDIVHrr = 1191, AArch64_FDIVR_ZPmZ_D = 1192, AArch64_FDIVR_ZPmZ_H = 1193, AArch64_FDIVR_ZPmZ_S = 1194, AArch64_FDIVSrr = 1195, AArch64_FDIV_ZPmZ_D = 1196, AArch64_FDIV_ZPmZ_H = 1197, AArch64_FDIV_ZPmZ_S = 1198, AArch64_FDIVv2f32 = 1199, AArch64_FDIVv2f64 = 1200, AArch64_FDIVv4f16 = 1201, AArch64_FDIVv4f32 = 1202, AArch64_FDIVv8f16 = 1203, AArch64_FDUP_ZI_D = 1204, AArch64_FDUP_ZI_H = 1205, AArch64_FDUP_ZI_S = 1206, AArch64_FEXPA_ZZ_D = 1207, AArch64_FEXPA_ZZ_H = 1208, AArch64_FEXPA_ZZ_S = 1209, AArch64_FJCVTZS = 1210, AArch64_FMADDDrrr = 1211, AArch64_FMADDHrrr = 1212, AArch64_FMADDSrrr = 1213, AArch64_FMAD_ZPmZZ_D = 1214, AArch64_FMAD_ZPmZZ_H = 1215, AArch64_FMAD_ZPmZZ_S = 1216, AArch64_FMAXDrr = 1217, AArch64_FMAXHrr = 1218, AArch64_FMAXNMDrr = 1219, AArch64_FMAXNMHrr = 1220, AArch64_FMAXNMPv2f32 = 1221, AArch64_FMAXNMPv2f64 = 1222, AArch64_FMAXNMPv2i16p = 1223, AArch64_FMAXNMPv2i32p = 1224, AArch64_FMAXNMPv2i64p = 1225, AArch64_FMAXNMPv4f16 = 1226, AArch64_FMAXNMPv4f32 = 1227, AArch64_FMAXNMPv8f16 = 1228, AArch64_FMAXNMSrr = 1229, AArch64_FMAXNMV_VPZ_D = 1230, AArch64_FMAXNMV_VPZ_H = 1231, AArch64_FMAXNMV_VPZ_S = 1232, AArch64_FMAXNMVv4i16v = 1233, AArch64_FMAXNMVv4i32v = 1234, AArch64_FMAXNMVv8i16v = 1235, AArch64_FMAXNM_ZPmI_D = 1236, AArch64_FMAXNM_ZPmI_H = 1237, AArch64_FMAXNM_ZPmI_S = 1238, AArch64_FMAXNM_ZPmZ_D = 1239, AArch64_FMAXNM_ZPmZ_H = 1240, AArch64_FMAXNM_ZPmZ_S = 1241, AArch64_FMAXNMv2f32 = 1242, AArch64_FMAXNMv2f64 = 1243, AArch64_FMAXNMv4f16 = 1244, AArch64_FMAXNMv4f32 = 1245, AArch64_FMAXNMv8f16 = 1246, AArch64_FMAXPv2f32 = 1247, AArch64_FMAXPv2f64 = 1248, AArch64_FMAXPv2i16p = 1249, AArch64_FMAXPv2i32p = 1250, AArch64_FMAXPv2i64p = 1251, AArch64_FMAXPv4f16 = 1252, AArch64_FMAXPv4f32 = 1253, AArch64_FMAXPv8f16 = 1254, AArch64_FMAXSrr = 1255, AArch64_FMAXV_VPZ_D = 1256, AArch64_FMAXV_VPZ_H = 1257, AArch64_FMAXV_VPZ_S = 1258, AArch64_FMAXVv4i16v = 1259, AArch64_FMAXVv4i32v = 1260, AArch64_FMAXVv8i16v = 1261, AArch64_FMAX_ZPmI_D = 1262, AArch64_FMAX_ZPmI_H = 1263, AArch64_FMAX_ZPmI_S = 1264, AArch64_FMAX_ZPmZ_D = 1265, AArch64_FMAX_ZPmZ_H = 1266, AArch64_FMAX_ZPmZ_S = 1267, AArch64_FMAXv2f32 = 1268, AArch64_FMAXv2f64 = 1269, AArch64_FMAXv4f16 = 1270, AArch64_FMAXv4f32 = 1271, AArch64_FMAXv8f16 = 1272, AArch64_FMINDrr = 1273, AArch64_FMINHrr = 1274, AArch64_FMINNMDrr = 1275, AArch64_FMINNMHrr = 1276, AArch64_FMINNMPv2f32 = 1277, AArch64_FMINNMPv2f64 = 1278, AArch64_FMINNMPv2i16p = 1279, AArch64_FMINNMPv2i32p = 1280, AArch64_FMINNMPv2i64p = 1281, AArch64_FMINNMPv4f16 = 1282, AArch64_FMINNMPv4f32 = 1283, AArch64_FMINNMPv8f16 = 1284, AArch64_FMINNMSrr = 1285, AArch64_FMINNMV_VPZ_D = 1286, AArch64_FMINNMV_VPZ_H = 1287, AArch64_FMINNMV_VPZ_S = 1288, AArch64_FMINNMVv4i16v = 1289, AArch64_FMINNMVv4i32v = 1290, AArch64_FMINNMVv8i16v = 1291, AArch64_FMINNM_ZPmI_D = 1292, AArch64_FMINNM_ZPmI_H = 1293, AArch64_FMINNM_ZPmI_S = 1294, AArch64_FMINNM_ZPmZ_D = 1295, AArch64_FMINNM_ZPmZ_H = 1296, AArch64_FMINNM_ZPmZ_S = 1297, AArch64_FMINNMv2f32 = 1298, AArch64_FMINNMv2f64 = 1299, AArch64_FMINNMv4f16 = 1300, AArch64_FMINNMv4f32 = 1301, AArch64_FMINNMv8f16 = 1302, AArch64_FMINPv2f32 = 1303, AArch64_FMINPv2f64 = 1304, AArch64_FMINPv2i16p = 1305, AArch64_FMINPv2i32p = 1306, AArch64_FMINPv2i64p = 1307, AArch64_FMINPv4f16 = 1308, AArch64_FMINPv4f32 = 1309, AArch64_FMINPv8f16 = 1310, AArch64_FMINSrr = 1311, AArch64_FMINV_VPZ_D = 1312, AArch64_FMINV_VPZ_H = 1313, AArch64_FMINV_VPZ_S = 1314, AArch64_FMINVv4i16v = 1315, AArch64_FMINVv4i32v = 1316, AArch64_FMINVv8i16v = 1317, AArch64_FMIN_ZPmI_D = 1318, AArch64_FMIN_ZPmI_H = 1319, AArch64_FMIN_ZPmI_S = 1320, AArch64_FMIN_ZPmZ_D = 1321, AArch64_FMIN_ZPmZ_H = 1322, AArch64_FMIN_ZPmZ_S = 1323, AArch64_FMINv2f32 = 1324, AArch64_FMINv2f64 = 1325, AArch64_FMINv4f16 = 1326, AArch64_FMINv4f32 = 1327, AArch64_FMINv8f16 = 1328, AArch64_FMLA_ZPmZZ_D = 1329, AArch64_FMLA_ZPmZZ_H = 1330, AArch64_FMLA_ZPmZZ_S = 1331, AArch64_FMLA_ZZZI_D = 1332, AArch64_FMLA_ZZZI_H = 1333, AArch64_FMLA_ZZZI_S = 1334, AArch64_FMLAv1i16_indexed = 1335, AArch64_FMLAv1i32_indexed = 1336, AArch64_FMLAv1i64_indexed = 1337, AArch64_FMLAv2f32 = 1338, AArch64_FMLAv2f64 = 1339, AArch64_FMLAv2i32_indexed = 1340, AArch64_FMLAv2i64_indexed = 1341, AArch64_FMLAv4f16 = 1342, AArch64_FMLAv4f32 = 1343, AArch64_FMLAv4i16_indexed = 1344, AArch64_FMLAv4i32_indexed = 1345, AArch64_FMLAv8f16 = 1346, AArch64_FMLAv8i16_indexed = 1347, AArch64_FMLS_ZPmZZ_D = 1348, AArch64_FMLS_ZPmZZ_H = 1349, AArch64_FMLS_ZPmZZ_S = 1350, AArch64_FMLS_ZZZI_D = 1351, AArch64_FMLS_ZZZI_H = 1352, AArch64_FMLS_ZZZI_S = 1353, AArch64_FMLSv1i16_indexed = 1354, AArch64_FMLSv1i32_indexed = 1355, AArch64_FMLSv1i64_indexed = 1356, AArch64_FMLSv2f32 = 1357, AArch64_FMLSv2f64 = 1358, AArch64_FMLSv2i32_indexed = 1359, AArch64_FMLSv2i64_indexed = 1360, AArch64_FMLSv4f16 = 1361, AArch64_FMLSv4f32 = 1362, AArch64_FMLSv4i16_indexed = 1363, AArch64_FMLSv4i32_indexed = 1364, AArch64_FMLSv8f16 = 1365, AArch64_FMLSv8i16_indexed = 1366, AArch64_FMOVD0 = 1367, AArch64_FMOVDXHighr = 1368, AArch64_FMOVDXr = 1369, AArch64_FMOVDi = 1370, AArch64_FMOVDr = 1371, AArch64_FMOVH0 = 1372, AArch64_FMOVHWr = 1373, AArch64_FMOVHXr = 1374, AArch64_FMOVHi = 1375, AArch64_FMOVHr = 1376, AArch64_FMOVS0 = 1377, AArch64_FMOVSWr = 1378, AArch64_FMOVSi = 1379, AArch64_FMOVSr = 1380, AArch64_FMOVWHr = 1381, AArch64_FMOVWSr = 1382, AArch64_FMOVXDHighr = 1383, AArch64_FMOVXDr = 1384, AArch64_FMOVXHr = 1385, AArch64_FMOVv2f32_ns = 1386, AArch64_FMOVv2f64_ns = 1387, AArch64_FMOVv4f16_ns = 1388, AArch64_FMOVv4f32_ns = 1389, AArch64_FMOVv8f16_ns = 1390, AArch64_FMSB_ZPmZZ_D = 1391, AArch64_FMSB_ZPmZZ_H = 1392, AArch64_FMSB_ZPmZZ_S = 1393, AArch64_FMSUBDrrr = 1394, AArch64_FMSUBHrrr = 1395, AArch64_FMSUBSrrr = 1396, AArch64_FMULDrr = 1397, AArch64_FMULHrr = 1398, AArch64_FMULSrr = 1399, AArch64_FMULX16 = 1400, AArch64_FMULX32 = 1401, AArch64_FMULX64 = 1402, AArch64_FMULX_ZPmZ_D = 1403, AArch64_FMULX_ZPmZ_H = 1404, AArch64_FMULX_ZPmZ_S = 1405, AArch64_FMULXv1i16_indexed = 1406, AArch64_FMULXv1i32_indexed = 1407, AArch64_FMULXv1i64_indexed = 1408, AArch64_FMULXv2f32 = 1409, AArch64_FMULXv2f64 = 1410, AArch64_FMULXv2i32_indexed = 1411, AArch64_FMULXv2i64_indexed = 1412, AArch64_FMULXv4f16 = 1413, AArch64_FMULXv4f32 = 1414, AArch64_FMULXv4i16_indexed = 1415, AArch64_FMULXv4i32_indexed = 1416, AArch64_FMULXv8f16 = 1417, AArch64_FMULXv8i16_indexed = 1418, AArch64_FMUL_ZPmI_D = 1419, AArch64_FMUL_ZPmI_H = 1420, AArch64_FMUL_ZPmI_S = 1421, AArch64_FMUL_ZPmZ_D = 1422, AArch64_FMUL_ZPmZ_H = 1423, AArch64_FMUL_ZPmZ_S = 1424, AArch64_FMUL_ZZZI_D = 1425, AArch64_FMUL_ZZZI_H = 1426, AArch64_FMUL_ZZZI_S = 1427, AArch64_FMUL_ZZZ_D = 1428, AArch64_FMUL_ZZZ_H = 1429, AArch64_FMUL_ZZZ_S = 1430, AArch64_FMULv1i16_indexed = 1431, AArch64_FMULv1i32_indexed = 1432, AArch64_FMULv1i64_indexed = 1433, AArch64_FMULv2f32 = 1434, AArch64_FMULv2f64 = 1435, AArch64_FMULv2i32_indexed = 1436, AArch64_FMULv2i64_indexed = 1437, AArch64_FMULv4f16 = 1438, AArch64_FMULv4f32 = 1439, AArch64_FMULv4i16_indexed = 1440, AArch64_FMULv4i32_indexed = 1441, AArch64_FMULv8f16 = 1442, AArch64_FMULv8i16_indexed = 1443, AArch64_FNEGDr = 1444, AArch64_FNEGHr = 1445, AArch64_FNEGSr = 1446, AArch64_FNEG_ZPmZ_D = 1447, AArch64_FNEG_ZPmZ_H = 1448, AArch64_FNEG_ZPmZ_S = 1449, AArch64_FNEGv2f32 = 1450, AArch64_FNEGv2f64 = 1451, AArch64_FNEGv4f16 = 1452, AArch64_FNEGv4f32 = 1453, AArch64_FNEGv8f16 = 1454, AArch64_FNMADDDrrr = 1455, AArch64_FNMADDHrrr = 1456, AArch64_FNMADDSrrr = 1457, AArch64_FNMAD_ZPmZZ_D = 1458, AArch64_FNMAD_ZPmZZ_H = 1459, AArch64_FNMAD_ZPmZZ_S = 1460, AArch64_FNMLA_ZPmZZ_D = 1461, AArch64_FNMLA_ZPmZZ_H = 1462, AArch64_FNMLA_ZPmZZ_S = 1463, AArch64_FNMLS_ZPmZZ_D = 1464, AArch64_FNMLS_ZPmZZ_H = 1465, AArch64_FNMLS_ZPmZZ_S = 1466, AArch64_FNMSB_ZPmZZ_D = 1467, AArch64_FNMSB_ZPmZZ_H = 1468, AArch64_FNMSB_ZPmZZ_S = 1469, AArch64_FNMSUBDrrr = 1470, AArch64_FNMSUBHrrr = 1471, AArch64_FNMSUBSrrr = 1472, AArch64_FNMULDrr = 1473, AArch64_FNMULHrr = 1474, AArch64_FNMULSrr = 1475, AArch64_FRECPE_ZZ_D = 1476, AArch64_FRECPE_ZZ_H = 1477, AArch64_FRECPE_ZZ_S = 1478, AArch64_FRECPEv1f16 = 1479, AArch64_FRECPEv1i32 = 1480, AArch64_FRECPEv1i64 = 1481, AArch64_FRECPEv2f32 = 1482, AArch64_FRECPEv2f64 = 1483, AArch64_FRECPEv4f16 = 1484, AArch64_FRECPEv4f32 = 1485, AArch64_FRECPEv8f16 = 1486, AArch64_FRECPS16 = 1487, AArch64_FRECPS32 = 1488, AArch64_FRECPS64 = 1489, AArch64_FRECPS_ZZZ_D = 1490, AArch64_FRECPS_ZZZ_H = 1491, AArch64_FRECPS_ZZZ_S = 1492, AArch64_FRECPSv2f32 = 1493, AArch64_FRECPSv2f64 = 1494, AArch64_FRECPSv4f16 = 1495, AArch64_FRECPSv4f32 = 1496, AArch64_FRECPSv8f16 = 1497, AArch64_FRECPX_ZPmZ_D = 1498, AArch64_FRECPX_ZPmZ_H = 1499, AArch64_FRECPX_ZPmZ_S = 1500, AArch64_FRECPXv1f16 = 1501, AArch64_FRECPXv1i32 = 1502, AArch64_FRECPXv1i64 = 1503, AArch64_FRINTADr = 1504, AArch64_FRINTAHr = 1505, AArch64_FRINTASr = 1506, AArch64_FRINTA_ZPmZ_D = 1507, AArch64_FRINTA_ZPmZ_H = 1508, AArch64_FRINTA_ZPmZ_S = 1509, AArch64_FRINTAv2f32 = 1510, AArch64_FRINTAv2f64 = 1511, AArch64_FRINTAv4f16 = 1512, AArch64_FRINTAv4f32 = 1513, AArch64_FRINTAv8f16 = 1514, AArch64_FRINTIDr = 1515, AArch64_FRINTIHr = 1516, AArch64_FRINTISr = 1517, AArch64_FRINTI_ZPmZ_D = 1518, AArch64_FRINTI_ZPmZ_H = 1519, AArch64_FRINTI_ZPmZ_S = 1520, AArch64_FRINTIv2f32 = 1521, AArch64_FRINTIv2f64 = 1522, AArch64_FRINTIv4f16 = 1523, AArch64_FRINTIv4f32 = 1524, AArch64_FRINTIv8f16 = 1525, AArch64_FRINTMDr = 1526, AArch64_FRINTMHr = 1527, AArch64_FRINTMSr = 1528, AArch64_FRINTM_ZPmZ_D = 1529, AArch64_FRINTM_ZPmZ_H = 1530, AArch64_FRINTM_ZPmZ_S = 1531, AArch64_FRINTMv2f32 = 1532, AArch64_FRINTMv2f64 = 1533, AArch64_FRINTMv4f16 = 1534, AArch64_FRINTMv4f32 = 1535, AArch64_FRINTMv8f16 = 1536, AArch64_FRINTNDr = 1537, AArch64_FRINTNHr = 1538, AArch64_FRINTNSr = 1539, AArch64_FRINTN_ZPmZ_D = 1540, AArch64_FRINTN_ZPmZ_H = 1541, AArch64_FRINTN_ZPmZ_S = 1542, AArch64_FRINTNv2f32 = 1543, AArch64_FRINTNv2f64 = 1544, AArch64_FRINTNv4f16 = 1545, AArch64_FRINTNv4f32 = 1546, AArch64_FRINTNv8f16 = 1547, AArch64_FRINTPDr = 1548, AArch64_FRINTPHr = 1549, AArch64_FRINTPSr = 1550, AArch64_FRINTP_ZPmZ_D = 1551, AArch64_FRINTP_ZPmZ_H = 1552, AArch64_FRINTP_ZPmZ_S = 1553, AArch64_FRINTPv2f32 = 1554, AArch64_FRINTPv2f64 = 1555, AArch64_FRINTPv4f16 = 1556, AArch64_FRINTPv4f32 = 1557, AArch64_FRINTPv8f16 = 1558, AArch64_FRINTXDr = 1559, AArch64_FRINTXHr = 1560, AArch64_FRINTXSr = 1561, AArch64_FRINTX_ZPmZ_D = 1562, AArch64_FRINTX_ZPmZ_H = 1563, AArch64_FRINTX_ZPmZ_S = 1564, AArch64_FRINTXv2f32 = 1565, AArch64_FRINTXv2f64 = 1566, AArch64_FRINTXv4f16 = 1567, AArch64_FRINTXv4f32 = 1568, AArch64_FRINTXv8f16 = 1569, AArch64_FRINTZDr = 1570, AArch64_FRINTZHr = 1571, AArch64_FRINTZSr = 1572, AArch64_FRINTZ_ZPmZ_D = 1573, AArch64_FRINTZ_ZPmZ_H = 1574, AArch64_FRINTZ_ZPmZ_S = 1575, AArch64_FRINTZv2f32 = 1576, AArch64_FRINTZv2f64 = 1577, AArch64_FRINTZv4f16 = 1578, AArch64_FRINTZv4f32 = 1579, AArch64_FRINTZv8f16 = 1580, AArch64_FRSQRTE_ZZ_D = 1581, AArch64_FRSQRTE_ZZ_H = 1582, AArch64_FRSQRTE_ZZ_S = 1583, AArch64_FRSQRTEv1f16 = 1584, AArch64_FRSQRTEv1i32 = 1585, AArch64_FRSQRTEv1i64 = 1586, AArch64_FRSQRTEv2f32 = 1587, AArch64_FRSQRTEv2f64 = 1588, AArch64_FRSQRTEv4f16 = 1589, AArch64_FRSQRTEv4f32 = 1590, AArch64_FRSQRTEv8f16 = 1591, AArch64_FRSQRTS16 = 1592, AArch64_FRSQRTS32 = 1593, AArch64_FRSQRTS64 = 1594, AArch64_FRSQRTS_ZZZ_D = 1595, AArch64_FRSQRTS_ZZZ_H = 1596, AArch64_FRSQRTS_ZZZ_S = 1597, AArch64_FRSQRTSv2f32 = 1598, AArch64_FRSQRTSv2f64 = 1599, AArch64_FRSQRTSv4f16 = 1600, AArch64_FRSQRTSv4f32 = 1601, AArch64_FRSQRTSv8f16 = 1602, AArch64_FSCALE_ZPmZ_D = 1603, AArch64_FSCALE_ZPmZ_H = 1604, AArch64_FSCALE_ZPmZ_S = 1605, AArch64_FSQRTDr = 1606, AArch64_FSQRTHr = 1607, AArch64_FSQRTSr = 1608, AArch64_FSQRT_ZPmZ_D = 1609, AArch64_FSQRT_ZPmZ_H = 1610, AArch64_FSQRT_ZPmZ_S = 1611, AArch64_FSQRTv2f32 = 1612, AArch64_FSQRTv2f64 = 1613, AArch64_FSQRTv4f16 = 1614, AArch64_FSQRTv4f32 = 1615, AArch64_FSQRTv8f16 = 1616, AArch64_FSUBDrr = 1617, AArch64_FSUBHrr = 1618, AArch64_FSUBR_ZPmI_D = 1619, AArch64_FSUBR_ZPmI_H = 1620, AArch64_FSUBR_ZPmI_S = 1621, AArch64_FSUBR_ZPmZ_D = 1622, AArch64_FSUBR_ZPmZ_H = 1623, AArch64_FSUBR_ZPmZ_S = 1624, AArch64_FSUBSrr = 1625, AArch64_FSUB_ZPmI_D = 1626, AArch64_FSUB_ZPmI_H = 1627, AArch64_FSUB_ZPmI_S = 1628, AArch64_FSUB_ZPmZ_D = 1629, AArch64_FSUB_ZPmZ_H = 1630, AArch64_FSUB_ZPmZ_S = 1631, AArch64_FSUB_ZZZ_D = 1632, AArch64_FSUB_ZZZ_H = 1633, AArch64_FSUB_ZZZ_S = 1634, AArch64_FSUBv2f32 = 1635, AArch64_FSUBv2f64 = 1636, AArch64_FSUBv4f16 = 1637, AArch64_FSUBv4f32 = 1638, AArch64_FSUBv8f16 = 1639, AArch64_FTMAD_ZZI_D = 1640, AArch64_FTMAD_ZZI_H = 1641, AArch64_FTMAD_ZZI_S = 1642, AArch64_FTSMUL_ZZZ_D = 1643, AArch64_FTSMUL_ZZZ_H = 1644, AArch64_FTSMUL_ZZZ_S = 1645, AArch64_FTSSEL_ZZZ_D = 1646, AArch64_FTSSEL_ZZZ_H = 1647, AArch64_FTSSEL_ZZZ_S = 1648, AArch64_GLD1B_D_IMM_REAL = 1649, AArch64_GLD1B_D_REAL = 1650, AArch64_GLD1B_D_SXTW_REAL = 1651, AArch64_GLD1B_D_UXTW_REAL = 1652, AArch64_GLD1B_S_IMM_REAL = 1653, AArch64_GLD1B_S_SXTW_REAL = 1654, AArch64_GLD1B_S_UXTW_REAL = 1655, AArch64_GLD1D_IMM_REAL = 1656, AArch64_GLD1D_REAL = 1657, AArch64_GLD1D_SCALED_REAL = 1658, AArch64_GLD1D_SXTW_REAL = 1659, AArch64_GLD1D_SXTW_SCALED_REAL = 1660, AArch64_GLD1D_UXTW_REAL = 1661, AArch64_GLD1D_UXTW_SCALED_REAL = 1662, AArch64_GLD1H_D_IMM_REAL = 1663, AArch64_GLD1H_D_REAL = 1664, AArch64_GLD1H_D_SCALED_REAL = 1665, AArch64_GLD1H_D_SXTW_REAL = 1666, AArch64_GLD1H_D_SXTW_SCALED_REAL = 1667, AArch64_GLD1H_D_UXTW_REAL = 1668, AArch64_GLD1H_D_UXTW_SCALED_REAL = 1669, AArch64_GLD1H_S_IMM_REAL = 1670, AArch64_GLD1H_S_SXTW_REAL = 1671, AArch64_GLD1H_S_SXTW_SCALED_REAL = 1672, AArch64_GLD1H_S_UXTW_REAL = 1673, AArch64_GLD1H_S_UXTW_SCALED_REAL = 1674, AArch64_GLD1SB_D_IMM_REAL = 1675, AArch64_GLD1SB_D_REAL = 1676, AArch64_GLD1SB_D_SXTW_REAL = 1677, AArch64_GLD1SB_D_UXTW_REAL = 1678, AArch64_GLD1SB_S_IMM_REAL = 1679, AArch64_GLD1SB_S_SXTW_REAL = 1680, AArch64_GLD1SB_S_UXTW_REAL = 1681, AArch64_GLD1SH_D_IMM_REAL = 1682, AArch64_GLD1SH_D_REAL = 1683, AArch64_GLD1SH_D_SCALED_REAL = 1684, AArch64_GLD1SH_D_SXTW_REAL = 1685, AArch64_GLD1SH_D_SXTW_SCALED_REAL = 1686, AArch64_GLD1SH_D_UXTW_REAL = 1687, AArch64_GLD1SH_D_UXTW_SCALED_REAL = 1688, AArch64_GLD1SH_S_IMM_REAL = 1689, AArch64_GLD1SH_S_SXTW_REAL = 1690, AArch64_GLD1SH_S_SXTW_SCALED_REAL = 1691, AArch64_GLD1SH_S_UXTW_REAL = 1692, AArch64_GLD1SH_S_UXTW_SCALED_REAL = 1693, AArch64_GLD1SW_D_IMM_REAL = 1694, AArch64_GLD1SW_D_REAL = 1695, AArch64_GLD1SW_D_SCALED_REAL = 1696, AArch64_GLD1SW_D_SXTW_REAL = 1697, AArch64_GLD1SW_D_SXTW_SCALED_REAL = 1698, AArch64_GLD1SW_D_UXTW_REAL = 1699, AArch64_GLD1SW_D_UXTW_SCALED_REAL = 1700, AArch64_GLD1W_D_IMM_REAL = 1701, AArch64_GLD1W_D_REAL = 1702, AArch64_GLD1W_D_SCALED_REAL = 1703, AArch64_GLD1W_D_SXTW_REAL = 1704, AArch64_GLD1W_D_SXTW_SCALED_REAL = 1705, AArch64_GLD1W_D_UXTW_REAL = 1706, AArch64_GLD1W_D_UXTW_SCALED_REAL = 1707, AArch64_GLD1W_IMM_REAL = 1708, AArch64_GLD1W_SXTW_REAL = 1709, AArch64_GLD1W_SXTW_SCALED_REAL = 1710, AArch64_GLD1W_UXTW_REAL = 1711, AArch64_GLD1W_UXTW_SCALED_REAL = 1712, AArch64_GLDFF1B_D_IMM_REAL = 1713, AArch64_GLDFF1B_D_REAL = 1714, AArch64_GLDFF1B_D_SXTW_REAL = 1715, AArch64_GLDFF1B_D_UXTW_REAL = 1716, AArch64_GLDFF1B_S_IMM_REAL = 1717, AArch64_GLDFF1B_S_SXTW_REAL = 1718, AArch64_GLDFF1B_S_UXTW_REAL = 1719, AArch64_GLDFF1D_IMM_REAL = 1720, AArch64_GLDFF1D_REAL = 1721, AArch64_GLDFF1D_SCALED_REAL = 1722, AArch64_GLDFF1D_SXTW_REAL = 1723, AArch64_GLDFF1D_SXTW_SCALED_REAL = 1724, AArch64_GLDFF1D_UXTW_REAL = 1725, AArch64_GLDFF1D_UXTW_SCALED_REAL = 1726, AArch64_GLDFF1H_D_IMM_REAL = 1727, AArch64_GLDFF1H_D_REAL = 1728, AArch64_GLDFF1H_D_SCALED_REAL = 1729, AArch64_GLDFF1H_D_SXTW_REAL = 1730, AArch64_GLDFF1H_D_SXTW_SCALED_REAL = 1731, AArch64_GLDFF1H_D_UXTW_REAL = 1732, AArch64_GLDFF1H_D_UXTW_SCALED_REAL = 1733, AArch64_GLDFF1H_S_IMM_REAL = 1734, AArch64_GLDFF1H_S_SXTW_REAL = 1735, AArch64_GLDFF1H_S_SXTW_SCALED_REAL = 1736, AArch64_GLDFF1H_S_UXTW_REAL = 1737, AArch64_GLDFF1H_S_UXTW_SCALED_REAL = 1738, AArch64_GLDFF1SB_D_IMM_REAL = 1739, AArch64_GLDFF1SB_D_REAL = 1740, AArch64_GLDFF1SB_D_SXTW_REAL = 1741, AArch64_GLDFF1SB_D_UXTW_REAL = 1742, AArch64_GLDFF1SB_S_IMM_REAL = 1743, AArch64_GLDFF1SB_S_SXTW_REAL = 1744, AArch64_GLDFF1SB_S_UXTW_REAL = 1745, AArch64_GLDFF1SH_D_IMM_REAL = 1746, AArch64_GLDFF1SH_D_REAL = 1747, AArch64_GLDFF1SH_D_SCALED_REAL = 1748, AArch64_GLDFF1SH_D_SXTW_REAL = 1749, AArch64_GLDFF1SH_D_SXTW_SCALED_REAL = 1750, AArch64_GLDFF1SH_D_UXTW_REAL = 1751, AArch64_GLDFF1SH_D_UXTW_SCALED_REAL = 1752, AArch64_GLDFF1SH_S_IMM_REAL = 1753, AArch64_GLDFF1SH_S_SXTW_REAL = 1754, AArch64_GLDFF1SH_S_SXTW_SCALED_REAL = 1755, AArch64_GLDFF1SH_S_UXTW_REAL = 1756, AArch64_GLDFF1SH_S_UXTW_SCALED_REAL = 1757, AArch64_GLDFF1SW_D_IMM_REAL = 1758, AArch64_GLDFF1SW_D_REAL = 1759, AArch64_GLDFF1SW_D_SCALED_REAL = 1760, AArch64_GLDFF1SW_D_SXTW_REAL = 1761, AArch64_GLDFF1SW_D_SXTW_SCALED_REAL = 1762, AArch64_GLDFF1SW_D_UXTW_REAL = 1763, AArch64_GLDFF1SW_D_UXTW_SCALED_REAL = 1764, AArch64_GLDFF1W_D_IMM_REAL = 1765, AArch64_GLDFF1W_D_REAL = 1766, AArch64_GLDFF1W_D_SCALED_REAL = 1767, AArch64_GLDFF1W_D_SXTW_REAL = 1768, AArch64_GLDFF1W_D_SXTW_SCALED_REAL = 1769, AArch64_GLDFF1W_D_UXTW_REAL = 1770, AArch64_GLDFF1W_D_UXTW_SCALED_REAL = 1771, AArch64_GLDFF1W_IMM_REAL = 1772, AArch64_GLDFF1W_SXTW_REAL = 1773, AArch64_GLDFF1W_SXTW_SCALED_REAL = 1774, AArch64_GLDFF1W_UXTW_REAL = 1775, AArch64_GLDFF1W_UXTW_SCALED_REAL = 1776, AArch64_HINT = 1777, AArch64_HLT = 1778, AArch64_HVC = 1779, AArch64_INCB_XPiI = 1780, AArch64_INCD_XPiI = 1781, AArch64_INCD_ZPiI = 1782, AArch64_INCH_XPiI = 1783, AArch64_INCH_ZPiI = 1784, AArch64_INCP_XP_B = 1785, AArch64_INCP_XP_D = 1786, AArch64_INCP_XP_H = 1787, AArch64_INCP_XP_S = 1788, AArch64_INCP_ZP_D = 1789, AArch64_INCP_ZP_H = 1790, AArch64_INCP_ZP_S = 1791, AArch64_INCW_XPiI = 1792, AArch64_INCW_ZPiI = 1793, AArch64_INDEX_II_B = 1794, AArch64_INDEX_II_D = 1795, AArch64_INDEX_II_H = 1796, AArch64_INDEX_II_S = 1797, AArch64_INDEX_IR_B = 1798, AArch64_INDEX_IR_D = 1799, AArch64_INDEX_IR_H = 1800, AArch64_INDEX_IR_S = 1801, AArch64_INDEX_RI_B = 1802, AArch64_INDEX_RI_D = 1803, AArch64_INDEX_RI_H = 1804, AArch64_INDEX_RI_S = 1805, AArch64_INDEX_RR_B = 1806, AArch64_INDEX_RR_D = 1807, AArch64_INDEX_RR_H = 1808, AArch64_INDEX_RR_S = 1809, AArch64_INSR_ZR_B = 1810, AArch64_INSR_ZR_D = 1811, AArch64_INSR_ZR_H = 1812, AArch64_INSR_ZR_S = 1813, AArch64_INSR_ZV_B = 1814, AArch64_INSR_ZV_D = 1815, AArch64_INSR_ZV_H = 1816, AArch64_INSR_ZV_S = 1817, AArch64_INSvi16gpr = 1818, AArch64_INSvi16lane = 1819, AArch64_INSvi32gpr = 1820, AArch64_INSvi32lane = 1821, AArch64_INSvi64gpr = 1822, AArch64_INSvi64lane = 1823, AArch64_INSvi8gpr = 1824, AArch64_INSvi8lane = 1825, AArch64_ISB = 1826, AArch64_LASTA_RPZ_B = 1827, AArch64_LASTA_RPZ_D = 1828, AArch64_LASTA_RPZ_H = 1829, AArch64_LASTA_RPZ_S = 1830, AArch64_LASTA_VPZ_B = 1831, AArch64_LASTA_VPZ_D = 1832, AArch64_LASTA_VPZ_H = 1833, AArch64_LASTA_VPZ_S = 1834, AArch64_LASTB_RPZ_B = 1835, AArch64_LASTB_RPZ_D = 1836, AArch64_LASTB_RPZ_H = 1837, AArch64_LASTB_RPZ_S = 1838, AArch64_LASTB_VPZ_B = 1839, AArch64_LASTB_VPZ_D = 1840, AArch64_LASTB_VPZ_H = 1841, AArch64_LASTB_VPZ_S = 1842, AArch64_LD1B = 1843, AArch64_LD1B_D = 1844, AArch64_LD1B_D_IMM_REAL = 1845, AArch64_LD1B_H = 1846, AArch64_LD1B_H_IMM_REAL = 1847, AArch64_LD1B_IMM_REAL = 1848, AArch64_LD1B_S = 1849, AArch64_LD1B_S_IMM_REAL = 1850, AArch64_LD1D = 1851, AArch64_LD1D_IMM_REAL = 1852, AArch64_LD1Fourv16b = 1853, AArch64_LD1Fourv16b_POST = 1854, AArch64_LD1Fourv1d = 1855, AArch64_LD1Fourv1d_POST = 1856, AArch64_LD1Fourv2d = 1857, AArch64_LD1Fourv2d_POST = 1858, AArch64_LD1Fourv2s = 1859, AArch64_LD1Fourv2s_POST = 1860, AArch64_LD1Fourv4h = 1861, AArch64_LD1Fourv4h_POST = 1862, AArch64_LD1Fourv4s = 1863, AArch64_LD1Fourv4s_POST = 1864, AArch64_LD1Fourv8b = 1865, AArch64_LD1Fourv8b_POST = 1866, AArch64_LD1Fourv8h = 1867, AArch64_LD1Fourv8h_POST = 1868, AArch64_LD1H = 1869, AArch64_LD1H_D = 1870, AArch64_LD1H_D_IMM_REAL = 1871, AArch64_LD1H_IMM_REAL = 1872, AArch64_LD1H_S = 1873, AArch64_LD1H_S_IMM_REAL = 1874, AArch64_LD1Onev16b = 1875, AArch64_LD1Onev16b_POST = 1876, AArch64_LD1Onev1d = 1877, AArch64_LD1Onev1d_POST = 1878, AArch64_LD1Onev2d = 1879, AArch64_LD1Onev2d_POST = 1880, AArch64_LD1Onev2s = 1881, AArch64_LD1Onev2s_POST = 1882, AArch64_LD1Onev4h = 1883, AArch64_LD1Onev4h_POST = 1884, AArch64_LD1Onev4s = 1885, AArch64_LD1Onev4s_POST = 1886, AArch64_LD1Onev8b = 1887, AArch64_LD1Onev8b_POST = 1888, AArch64_LD1Onev8h = 1889, AArch64_LD1Onev8h_POST = 1890, AArch64_LD1RB_D_IMM = 1891, AArch64_LD1RB_H_IMM = 1892, AArch64_LD1RB_IMM = 1893, AArch64_LD1RB_S_IMM = 1894, AArch64_LD1RD_IMM = 1895, AArch64_LD1RH_D_IMM = 1896, AArch64_LD1RH_IMM = 1897, AArch64_LD1RH_S_IMM = 1898, AArch64_LD1RQ_B = 1899, AArch64_LD1RQ_B_IMM = 1900, AArch64_LD1RQ_D = 1901, AArch64_LD1RQ_D_IMM = 1902, AArch64_LD1RQ_H = 1903, AArch64_LD1RQ_H_IMM = 1904, AArch64_LD1RQ_W = 1905, AArch64_LD1RQ_W_IMM = 1906, AArch64_LD1RSB_D_IMM = 1907, AArch64_LD1RSB_H_IMM = 1908, AArch64_LD1RSB_S_IMM = 1909, AArch64_LD1RSH_D_IMM = 1910, AArch64_LD1RSH_S_IMM = 1911, AArch64_LD1RSW_IMM = 1912, AArch64_LD1RW_D_IMM = 1913, AArch64_LD1RW_IMM = 1914, AArch64_LD1Rv16b = 1915, AArch64_LD1Rv16b_POST = 1916, AArch64_LD1Rv1d = 1917, AArch64_LD1Rv1d_POST = 1918, AArch64_LD1Rv2d = 1919, AArch64_LD1Rv2d_POST = 1920, AArch64_LD1Rv2s = 1921, AArch64_LD1Rv2s_POST = 1922, AArch64_LD1Rv4h = 1923, AArch64_LD1Rv4h_POST = 1924, AArch64_LD1Rv4s = 1925, AArch64_LD1Rv4s_POST = 1926, AArch64_LD1Rv8b = 1927, AArch64_LD1Rv8b_POST = 1928, AArch64_LD1Rv8h = 1929, AArch64_LD1Rv8h_POST = 1930, AArch64_LD1SB_D = 1931, AArch64_LD1SB_D_IMM_REAL = 1932, AArch64_LD1SB_H = 1933, AArch64_LD1SB_H_IMM_REAL = 1934, AArch64_LD1SB_S = 1935, AArch64_LD1SB_S_IMM_REAL = 1936, AArch64_LD1SH_D = 1937, AArch64_LD1SH_D_IMM_REAL = 1938, AArch64_LD1SH_S = 1939, AArch64_LD1SH_S_IMM_REAL = 1940, AArch64_LD1SW_D = 1941, AArch64_LD1SW_D_IMM_REAL = 1942, AArch64_LD1Threev16b = 1943, AArch64_LD1Threev16b_POST = 1944, AArch64_LD1Threev1d = 1945, AArch64_LD1Threev1d_POST = 1946, AArch64_LD1Threev2d = 1947, AArch64_LD1Threev2d_POST = 1948, AArch64_LD1Threev2s = 1949, AArch64_LD1Threev2s_POST = 1950, AArch64_LD1Threev4h = 1951, AArch64_LD1Threev4h_POST = 1952, AArch64_LD1Threev4s = 1953, AArch64_LD1Threev4s_POST = 1954, AArch64_LD1Threev8b = 1955, AArch64_LD1Threev8b_POST = 1956, AArch64_LD1Threev8h = 1957, AArch64_LD1Threev8h_POST = 1958, AArch64_LD1Twov16b = 1959, AArch64_LD1Twov16b_POST = 1960, AArch64_LD1Twov1d = 1961, AArch64_LD1Twov1d_POST = 1962, AArch64_LD1Twov2d = 1963, AArch64_LD1Twov2d_POST = 1964, AArch64_LD1Twov2s = 1965, AArch64_LD1Twov2s_POST = 1966, AArch64_LD1Twov4h = 1967, AArch64_LD1Twov4h_POST = 1968, AArch64_LD1Twov4s = 1969, AArch64_LD1Twov4s_POST = 1970, AArch64_LD1Twov8b = 1971, AArch64_LD1Twov8b_POST = 1972, AArch64_LD1Twov8h = 1973, AArch64_LD1Twov8h_POST = 1974, AArch64_LD1W = 1975, AArch64_LD1W_D = 1976, AArch64_LD1W_D_IMM_REAL = 1977, AArch64_LD1W_IMM_REAL = 1978, AArch64_LD1i16 = 1979, AArch64_LD1i16_POST = 1980, AArch64_LD1i32 = 1981, AArch64_LD1i32_POST = 1982, AArch64_LD1i64 = 1983, AArch64_LD1i64_POST = 1984, AArch64_LD1i8 = 1985, AArch64_LD1i8_POST = 1986, AArch64_LD2B = 1987, AArch64_LD2B_IMM = 1988, AArch64_LD2D = 1989, AArch64_LD2D_IMM = 1990, AArch64_LD2H = 1991, AArch64_LD2H_IMM = 1992, AArch64_LD2Rv16b = 1993, AArch64_LD2Rv16b_POST = 1994, AArch64_LD2Rv1d = 1995, AArch64_LD2Rv1d_POST = 1996, AArch64_LD2Rv2d = 1997, AArch64_LD2Rv2d_POST = 1998, AArch64_LD2Rv2s = 1999, AArch64_LD2Rv2s_POST = 2000, AArch64_LD2Rv4h = 2001, AArch64_LD2Rv4h_POST = 2002, AArch64_LD2Rv4s = 2003, AArch64_LD2Rv4s_POST = 2004, AArch64_LD2Rv8b = 2005, AArch64_LD2Rv8b_POST = 2006, AArch64_LD2Rv8h = 2007, AArch64_LD2Rv8h_POST = 2008, AArch64_LD2Twov16b = 2009, AArch64_LD2Twov16b_POST = 2010, AArch64_LD2Twov2d = 2011, AArch64_LD2Twov2d_POST = 2012, AArch64_LD2Twov2s = 2013, AArch64_LD2Twov2s_POST = 2014, AArch64_LD2Twov4h = 2015, AArch64_LD2Twov4h_POST = 2016, AArch64_LD2Twov4s = 2017, AArch64_LD2Twov4s_POST = 2018, AArch64_LD2Twov8b = 2019, AArch64_LD2Twov8b_POST = 2020, AArch64_LD2Twov8h = 2021, AArch64_LD2Twov8h_POST = 2022, AArch64_LD2W = 2023, AArch64_LD2W_IMM = 2024, AArch64_LD2i16 = 2025, AArch64_LD2i16_POST = 2026, AArch64_LD2i32 = 2027, AArch64_LD2i32_POST = 2028, AArch64_LD2i64 = 2029, AArch64_LD2i64_POST = 2030, AArch64_LD2i8 = 2031, AArch64_LD2i8_POST = 2032, AArch64_LD3B = 2033, AArch64_LD3B_IMM = 2034, AArch64_LD3D = 2035, AArch64_LD3D_IMM = 2036, AArch64_LD3H = 2037, AArch64_LD3H_IMM = 2038, AArch64_LD3Rv16b = 2039, AArch64_LD3Rv16b_POST = 2040, AArch64_LD3Rv1d = 2041, AArch64_LD3Rv1d_POST = 2042, AArch64_LD3Rv2d = 2043, AArch64_LD3Rv2d_POST = 2044, AArch64_LD3Rv2s = 2045, AArch64_LD3Rv2s_POST = 2046, AArch64_LD3Rv4h = 2047, AArch64_LD3Rv4h_POST = 2048, AArch64_LD3Rv4s = 2049, AArch64_LD3Rv4s_POST = 2050, AArch64_LD3Rv8b = 2051, AArch64_LD3Rv8b_POST = 2052, AArch64_LD3Rv8h = 2053, AArch64_LD3Rv8h_POST = 2054, AArch64_LD3Threev16b = 2055, AArch64_LD3Threev16b_POST = 2056, AArch64_LD3Threev2d = 2057, AArch64_LD3Threev2d_POST = 2058, AArch64_LD3Threev2s = 2059, AArch64_LD3Threev2s_POST = 2060, AArch64_LD3Threev4h = 2061, AArch64_LD3Threev4h_POST = 2062, AArch64_LD3Threev4s = 2063, AArch64_LD3Threev4s_POST = 2064, AArch64_LD3Threev8b = 2065, AArch64_LD3Threev8b_POST = 2066, AArch64_LD3Threev8h = 2067, AArch64_LD3Threev8h_POST = 2068, AArch64_LD3W = 2069, AArch64_LD3W_IMM = 2070, AArch64_LD3i16 = 2071, AArch64_LD3i16_POST = 2072, AArch64_LD3i32 = 2073, AArch64_LD3i32_POST = 2074, AArch64_LD3i64 = 2075, AArch64_LD3i64_POST = 2076, AArch64_LD3i8 = 2077, AArch64_LD3i8_POST = 2078, AArch64_LD4B = 2079, AArch64_LD4B_IMM = 2080, AArch64_LD4D = 2081, AArch64_LD4D_IMM = 2082, AArch64_LD4Fourv16b = 2083, AArch64_LD4Fourv16b_POST = 2084, AArch64_LD4Fourv2d = 2085, AArch64_LD4Fourv2d_POST = 2086, AArch64_LD4Fourv2s = 2087, AArch64_LD4Fourv2s_POST = 2088, AArch64_LD4Fourv4h = 2089, AArch64_LD4Fourv4h_POST = 2090, AArch64_LD4Fourv4s = 2091, AArch64_LD4Fourv4s_POST = 2092, AArch64_LD4Fourv8b = 2093, AArch64_LD4Fourv8b_POST = 2094, AArch64_LD4Fourv8h = 2095, AArch64_LD4Fourv8h_POST = 2096, AArch64_LD4H = 2097, AArch64_LD4H_IMM = 2098, AArch64_LD4Rv16b = 2099, AArch64_LD4Rv16b_POST = 2100, AArch64_LD4Rv1d = 2101, AArch64_LD4Rv1d_POST = 2102, AArch64_LD4Rv2d = 2103, AArch64_LD4Rv2d_POST = 2104, AArch64_LD4Rv2s = 2105, AArch64_LD4Rv2s_POST = 2106, AArch64_LD4Rv4h = 2107, AArch64_LD4Rv4h_POST = 2108, AArch64_LD4Rv4s = 2109, AArch64_LD4Rv4s_POST = 2110, AArch64_LD4Rv8b = 2111, AArch64_LD4Rv8b_POST = 2112, AArch64_LD4Rv8h = 2113, AArch64_LD4Rv8h_POST = 2114, AArch64_LD4W = 2115, AArch64_LD4W_IMM = 2116, AArch64_LD4i16 = 2117, AArch64_LD4i16_POST = 2118, AArch64_LD4i32 = 2119, AArch64_LD4i32_POST = 2120, AArch64_LD4i64 = 2121, AArch64_LD4i64_POST = 2122, AArch64_LD4i8 = 2123, AArch64_LD4i8_POST = 2124, AArch64_LDADDAB = 2125, AArch64_LDADDAH = 2126, AArch64_LDADDALB = 2127, AArch64_LDADDALH = 2128, AArch64_LDADDALW = 2129, AArch64_LDADDALX = 2130, AArch64_LDADDAW = 2131, AArch64_LDADDAX = 2132, AArch64_LDADDB = 2133, AArch64_LDADDH = 2134, AArch64_LDADDLB = 2135, AArch64_LDADDLH = 2136, AArch64_LDADDLW = 2137, AArch64_LDADDLX = 2138, AArch64_LDADDW = 2139, AArch64_LDADDX = 2140, AArch64_LDAPRB = 2141, AArch64_LDAPRH = 2142, AArch64_LDAPRW = 2143, AArch64_LDAPRX = 2144, AArch64_LDAPURBi = 2145, AArch64_LDAPURHi = 2146, AArch64_LDAPURSBWi = 2147, AArch64_LDAPURSBXi = 2148, AArch64_LDAPURSHWi = 2149, AArch64_LDAPURSHXi = 2150, AArch64_LDAPURSWi = 2151, AArch64_LDAPURXi = 2152, AArch64_LDAPURi = 2153, AArch64_LDARB = 2154, AArch64_LDARH = 2155, AArch64_LDARW = 2156, AArch64_LDARX = 2157, AArch64_LDAXPW = 2158, AArch64_LDAXPX = 2159, AArch64_LDAXRB = 2160, AArch64_LDAXRH = 2161, AArch64_LDAXRW = 2162, AArch64_LDAXRX = 2163, AArch64_LDCLRAB = 2164, AArch64_LDCLRAH = 2165, AArch64_LDCLRALB = 2166, AArch64_LDCLRALH = 2167, AArch64_LDCLRALW = 2168, AArch64_LDCLRALX = 2169, AArch64_LDCLRAW = 2170, AArch64_LDCLRAX = 2171, AArch64_LDCLRB = 2172, AArch64_LDCLRH = 2173, AArch64_LDCLRLB = 2174, AArch64_LDCLRLH = 2175, AArch64_LDCLRLW = 2176, AArch64_LDCLRLX = 2177, AArch64_LDCLRW = 2178, AArch64_LDCLRX = 2179, AArch64_LDEORAB = 2180, AArch64_LDEORAH = 2181, AArch64_LDEORALB = 2182, AArch64_LDEORALH = 2183, AArch64_LDEORALW = 2184, AArch64_LDEORALX = 2185, AArch64_LDEORAW = 2186, AArch64_LDEORAX = 2187, AArch64_LDEORB = 2188, AArch64_LDEORH = 2189, AArch64_LDEORLB = 2190, AArch64_LDEORLH = 2191, AArch64_LDEORLW = 2192, AArch64_LDEORLX = 2193, AArch64_LDEORW = 2194, AArch64_LDEORX = 2195, AArch64_LDFF1B_D_REAL = 2196, AArch64_LDFF1B_H_REAL = 2197, AArch64_LDFF1B_REAL = 2198, AArch64_LDFF1B_S_REAL = 2199, AArch64_LDFF1D_REAL = 2200, AArch64_LDFF1H_D_REAL = 2201, AArch64_LDFF1H_REAL = 2202, AArch64_LDFF1H_S_REAL = 2203, AArch64_LDFF1SB_D_REAL = 2204, AArch64_LDFF1SB_H_REAL = 2205, AArch64_LDFF1SB_S_REAL = 2206, AArch64_LDFF1SH_D_REAL = 2207, AArch64_LDFF1SH_S_REAL = 2208, AArch64_LDFF1SW_D_REAL = 2209, AArch64_LDFF1W_D_REAL = 2210, AArch64_LDFF1W_REAL = 2211, AArch64_LDLARB = 2212, AArch64_LDLARH = 2213, AArch64_LDLARW = 2214, AArch64_LDLARX = 2215, AArch64_LDNF1B_D_IMM_REAL = 2216, AArch64_LDNF1B_H_IMM_REAL = 2217, AArch64_LDNF1B_IMM_REAL = 2218, AArch64_LDNF1B_S_IMM_REAL = 2219, AArch64_LDNF1D_IMM_REAL = 2220, AArch64_LDNF1H_D_IMM_REAL = 2221, AArch64_LDNF1H_IMM_REAL = 2222, AArch64_LDNF1H_S_IMM_REAL = 2223, AArch64_LDNF1SB_D_IMM_REAL = 2224, AArch64_LDNF1SB_H_IMM_REAL = 2225, AArch64_LDNF1SB_S_IMM_REAL = 2226, AArch64_LDNF1SH_D_IMM_REAL = 2227, AArch64_LDNF1SH_S_IMM_REAL = 2228, AArch64_LDNF1SW_D_IMM_REAL = 2229, AArch64_LDNF1W_D_IMM_REAL = 2230, AArch64_LDNF1W_IMM_REAL = 2231, AArch64_LDNPDi = 2232, AArch64_LDNPQi = 2233, AArch64_LDNPSi = 2234, AArch64_LDNPWi = 2235, AArch64_LDNPXi = 2236, AArch64_LDNT1B_ZRI = 2237, AArch64_LDNT1B_ZRR = 2238, AArch64_LDNT1D_ZRI = 2239, AArch64_LDNT1D_ZRR = 2240, AArch64_LDNT1H_ZRI = 2241, AArch64_LDNT1H_ZRR = 2242, AArch64_LDNT1W_ZRI = 2243, AArch64_LDNT1W_ZRR = 2244, AArch64_LDPDi = 2245, AArch64_LDPDpost = 2246, AArch64_LDPDpre = 2247, AArch64_LDPQi = 2248, AArch64_LDPQpost = 2249, AArch64_LDPQpre = 2250, AArch64_LDPSWi = 2251, AArch64_LDPSWpost = 2252, AArch64_LDPSWpre = 2253, AArch64_LDPSi = 2254, AArch64_LDPSpost = 2255, AArch64_LDPSpre = 2256, AArch64_LDPWi = 2257, AArch64_LDPWpost = 2258, AArch64_LDPWpre = 2259, AArch64_LDPXi = 2260, AArch64_LDPXpost = 2261, AArch64_LDPXpre = 2262, AArch64_LDRAAindexed = 2263, AArch64_LDRAAwriteback = 2264, AArch64_LDRABindexed = 2265, AArch64_LDRABwriteback = 2266, AArch64_LDRBBpost = 2267, AArch64_LDRBBpre = 2268, AArch64_LDRBBroW = 2269, AArch64_LDRBBroX = 2270, AArch64_LDRBBui = 2271, AArch64_LDRBpost = 2272, AArch64_LDRBpre = 2273, AArch64_LDRBroW = 2274, AArch64_LDRBroX = 2275, AArch64_LDRBui = 2276, AArch64_LDRDl = 2277, AArch64_LDRDpost = 2278, AArch64_LDRDpre = 2279, AArch64_LDRDroW = 2280, AArch64_LDRDroX = 2281, AArch64_LDRDui = 2282, AArch64_LDRHHpost = 2283, AArch64_LDRHHpre = 2284, AArch64_LDRHHroW = 2285, AArch64_LDRHHroX = 2286, AArch64_LDRHHui = 2287, AArch64_LDRHpost = 2288, AArch64_LDRHpre = 2289, AArch64_LDRHroW = 2290, AArch64_LDRHroX = 2291, AArch64_LDRHui = 2292, AArch64_LDRQl = 2293, AArch64_LDRQpost = 2294, AArch64_LDRQpre = 2295, AArch64_LDRQroW = 2296, AArch64_LDRQroX = 2297, AArch64_LDRQui = 2298, AArch64_LDRSBWpost = 2299, AArch64_LDRSBWpre = 2300, AArch64_LDRSBWroW = 2301, AArch64_LDRSBWroX = 2302, AArch64_LDRSBWui = 2303, AArch64_LDRSBXpost = 2304, AArch64_LDRSBXpre = 2305, AArch64_LDRSBXroW = 2306, AArch64_LDRSBXroX = 2307, AArch64_LDRSBXui = 2308, AArch64_LDRSHWpost = 2309, AArch64_LDRSHWpre = 2310, AArch64_LDRSHWroW = 2311, AArch64_LDRSHWroX = 2312, AArch64_LDRSHWui = 2313, AArch64_LDRSHXpost = 2314, AArch64_LDRSHXpre = 2315, AArch64_LDRSHXroW = 2316, AArch64_LDRSHXroX = 2317, AArch64_LDRSHXui = 2318, AArch64_LDRSWl = 2319, AArch64_LDRSWpost = 2320, AArch64_LDRSWpre = 2321, AArch64_LDRSWroW = 2322, AArch64_LDRSWroX = 2323, AArch64_LDRSWui = 2324, AArch64_LDRSl = 2325, AArch64_LDRSpost = 2326, AArch64_LDRSpre = 2327, AArch64_LDRSroW = 2328, AArch64_LDRSroX = 2329, AArch64_LDRSui = 2330, AArch64_LDRWl = 2331, AArch64_LDRWpost = 2332, AArch64_LDRWpre = 2333, AArch64_LDRWroW = 2334, AArch64_LDRWroX = 2335, AArch64_LDRWui = 2336, AArch64_LDRXl = 2337, AArch64_LDRXpost = 2338, AArch64_LDRXpre = 2339, AArch64_LDRXroW = 2340, AArch64_LDRXroX = 2341, AArch64_LDRXui = 2342, AArch64_LDR_PXI = 2343, AArch64_LDR_ZXI = 2344, AArch64_LDSETAB = 2345, AArch64_LDSETAH = 2346, AArch64_LDSETALB = 2347, AArch64_LDSETALH = 2348, AArch64_LDSETALW = 2349, AArch64_LDSETALX = 2350, AArch64_LDSETAW = 2351, AArch64_LDSETAX = 2352, AArch64_LDSETB = 2353, AArch64_LDSETH = 2354, AArch64_LDSETLB = 2355, AArch64_LDSETLH = 2356, AArch64_LDSETLW = 2357, AArch64_LDSETLX = 2358, AArch64_LDSETW = 2359, AArch64_LDSETX = 2360, AArch64_LDSMAXAB = 2361, AArch64_LDSMAXAH = 2362, AArch64_LDSMAXALB = 2363, AArch64_LDSMAXALH = 2364, AArch64_LDSMAXALW = 2365, AArch64_LDSMAXALX = 2366, AArch64_LDSMAXAW = 2367, AArch64_LDSMAXAX = 2368, AArch64_LDSMAXB = 2369, AArch64_LDSMAXH = 2370, AArch64_LDSMAXLB = 2371, AArch64_LDSMAXLH = 2372, AArch64_LDSMAXLW = 2373, AArch64_LDSMAXLX = 2374, AArch64_LDSMAXW = 2375, AArch64_LDSMAXX = 2376, AArch64_LDSMINAB = 2377, AArch64_LDSMINAH = 2378, AArch64_LDSMINALB = 2379, AArch64_LDSMINALH = 2380, AArch64_LDSMINALW = 2381, AArch64_LDSMINALX = 2382, AArch64_LDSMINAW = 2383, AArch64_LDSMINAX = 2384, AArch64_LDSMINB = 2385, AArch64_LDSMINH = 2386, AArch64_LDSMINLB = 2387, AArch64_LDSMINLH = 2388, AArch64_LDSMINLW = 2389, AArch64_LDSMINLX = 2390, AArch64_LDSMINW = 2391, AArch64_LDSMINX = 2392, AArch64_LDTRBi = 2393, AArch64_LDTRHi = 2394, AArch64_LDTRSBWi = 2395, AArch64_LDTRSBXi = 2396, AArch64_LDTRSHWi = 2397, AArch64_LDTRSHXi = 2398, AArch64_LDTRSWi = 2399, AArch64_LDTRWi = 2400, AArch64_LDTRXi = 2401, AArch64_LDUMAXAB = 2402, AArch64_LDUMAXAH = 2403, AArch64_LDUMAXALB = 2404, AArch64_LDUMAXALH = 2405, AArch64_LDUMAXALW = 2406, AArch64_LDUMAXALX = 2407, AArch64_LDUMAXAW = 2408, AArch64_LDUMAXAX = 2409, AArch64_LDUMAXB = 2410, AArch64_LDUMAXH = 2411, AArch64_LDUMAXLB = 2412, AArch64_LDUMAXLH = 2413, AArch64_LDUMAXLW = 2414, AArch64_LDUMAXLX = 2415, AArch64_LDUMAXW = 2416, AArch64_LDUMAXX = 2417, AArch64_LDUMINAB = 2418, AArch64_LDUMINAH = 2419, AArch64_LDUMINALB = 2420, AArch64_LDUMINALH = 2421, AArch64_LDUMINALW = 2422, AArch64_LDUMINALX = 2423, AArch64_LDUMINAW = 2424, AArch64_LDUMINAX = 2425, AArch64_LDUMINB = 2426, AArch64_LDUMINH = 2427, AArch64_LDUMINLB = 2428, AArch64_LDUMINLH = 2429, AArch64_LDUMINLW = 2430, AArch64_LDUMINLX = 2431, AArch64_LDUMINW = 2432, AArch64_LDUMINX = 2433, AArch64_LDURBBi = 2434, AArch64_LDURBi = 2435, AArch64_LDURDi = 2436, AArch64_LDURHHi = 2437, AArch64_LDURHi = 2438, AArch64_LDURQi = 2439, AArch64_LDURSBWi = 2440, AArch64_LDURSBXi = 2441, AArch64_LDURSHWi = 2442, AArch64_LDURSHXi = 2443, AArch64_LDURSWi = 2444, AArch64_LDURSi = 2445, AArch64_LDURWi = 2446, AArch64_LDURXi = 2447, AArch64_LDXPW = 2448, AArch64_LDXPX = 2449, AArch64_LDXRB = 2450, AArch64_LDXRH = 2451, AArch64_LDXRW = 2452, AArch64_LDXRX = 2453, AArch64_LOADgot = 2454, AArch64_LSLR_ZPmZ_B = 2455, AArch64_LSLR_ZPmZ_D = 2456, AArch64_LSLR_ZPmZ_H = 2457, AArch64_LSLR_ZPmZ_S = 2458, AArch64_LSLVWr = 2459, AArch64_LSLVXr = 2460, AArch64_LSL_WIDE_ZPmZ_B = 2461, AArch64_LSL_WIDE_ZPmZ_H = 2462, AArch64_LSL_WIDE_ZPmZ_S = 2463, AArch64_LSL_WIDE_ZZZ_B = 2464, AArch64_LSL_WIDE_ZZZ_H = 2465, AArch64_LSL_WIDE_ZZZ_S = 2466, AArch64_LSL_ZPmI_B = 2467, AArch64_LSL_ZPmI_D = 2468, AArch64_LSL_ZPmI_H = 2469, AArch64_LSL_ZPmI_S = 2470, AArch64_LSL_ZPmZ_B = 2471, AArch64_LSL_ZPmZ_D = 2472, AArch64_LSL_ZPmZ_H = 2473, AArch64_LSL_ZPmZ_S = 2474, AArch64_LSL_ZZI_B = 2475, AArch64_LSL_ZZI_D = 2476, AArch64_LSL_ZZI_H = 2477, AArch64_LSL_ZZI_S = 2478, AArch64_LSRR_ZPmZ_B = 2479, AArch64_LSRR_ZPmZ_D = 2480, AArch64_LSRR_ZPmZ_H = 2481, AArch64_LSRR_ZPmZ_S = 2482, AArch64_LSRVWr = 2483, AArch64_LSRVXr = 2484, AArch64_LSR_WIDE_ZPmZ_B = 2485, AArch64_LSR_WIDE_ZPmZ_H = 2486, AArch64_LSR_WIDE_ZPmZ_S = 2487, AArch64_LSR_WIDE_ZZZ_B = 2488, AArch64_LSR_WIDE_ZZZ_H = 2489, AArch64_LSR_WIDE_ZZZ_S = 2490, AArch64_LSR_ZPmI_B = 2491, AArch64_LSR_ZPmI_D = 2492, AArch64_LSR_ZPmI_H = 2493, AArch64_LSR_ZPmI_S = 2494, AArch64_LSR_ZPmZ_B = 2495, AArch64_LSR_ZPmZ_D = 2496, AArch64_LSR_ZPmZ_H = 2497, AArch64_LSR_ZPmZ_S = 2498, AArch64_LSR_ZZI_B = 2499, AArch64_LSR_ZZI_D = 2500, AArch64_LSR_ZZI_H = 2501, AArch64_LSR_ZZI_S = 2502, AArch64_MADDWrrr = 2503, AArch64_MADDXrrr = 2504, AArch64_MAD_ZPmZZ_B = 2505, AArch64_MAD_ZPmZZ_D = 2506, AArch64_MAD_ZPmZZ_H = 2507, AArch64_MAD_ZPmZZ_S = 2508, AArch64_MLA_ZPmZZ_B = 2509, AArch64_MLA_ZPmZZ_D = 2510, AArch64_MLA_ZPmZZ_H = 2511, AArch64_MLA_ZPmZZ_S = 2512, AArch64_MLAv16i8 = 2513, AArch64_MLAv2i32 = 2514, AArch64_MLAv2i32_indexed = 2515, AArch64_MLAv4i16 = 2516, AArch64_MLAv4i16_indexed = 2517, AArch64_MLAv4i32 = 2518, AArch64_MLAv4i32_indexed = 2519, AArch64_MLAv8i16 = 2520, AArch64_MLAv8i16_indexed = 2521, AArch64_MLAv8i8 = 2522, AArch64_MLS_ZPmZZ_B = 2523, AArch64_MLS_ZPmZZ_D = 2524, AArch64_MLS_ZPmZZ_H = 2525, AArch64_MLS_ZPmZZ_S = 2526, AArch64_MLSv16i8 = 2527, AArch64_MLSv2i32 = 2528, AArch64_MLSv2i32_indexed = 2529, AArch64_MLSv4i16 = 2530, AArch64_MLSv4i16_indexed = 2531, AArch64_MLSv4i32 = 2532, AArch64_MLSv4i32_indexed = 2533, AArch64_MLSv8i16 = 2534, AArch64_MLSv8i16_indexed = 2535, AArch64_MLSv8i8 = 2536, AArch64_MOVID = 2537, AArch64_MOVIv16b_ns = 2538, AArch64_MOVIv2d_ns = 2539, AArch64_MOVIv2i32 = 2540, AArch64_MOVIv2s_msl = 2541, AArch64_MOVIv4i16 = 2542, AArch64_MOVIv4i32 = 2543, AArch64_MOVIv4s_msl = 2544, AArch64_MOVIv8b_ns = 2545, AArch64_MOVIv8i16 = 2546, AArch64_MOVKWi = 2547, AArch64_MOVKXi = 2548, AArch64_MOVNWi = 2549, AArch64_MOVNXi = 2550, AArch64_MOVPRFX_ZPmZ_B = 2551, AArch64_MOVPRFX_ZPmZ_D = 2552, AArch64_MOVPRFX_ZPmZ_H = 2553, AArch64_MOVPRFX_ZPmZ_S = 2554, AArch64_MOVPRFX_ZPzZ_B = 2555, AArch64_MOVPRFX_ZPzZ_D = 2556, AArch64_MOVPRFX_ZPzZ_H = 2557, AArch64_MOVPRFX_ZPzZ_S = 2558, AArch64_MOVPRFX_ZZ = 2559, AArch64_MOVZWi = 2560, AArch64_MOVZXi = 2561, AArch64_MOVaddr = 2562, AArch64_MOVaddrBA = 2563, AArch64_MOVaddrCP = 2564, AArch64_MOVaddrEXT = 2565, AArch64_MOVaddrJT = 2566, AArch64_MOVaddrTLS = 2567, AArch64_MOVbaseTLS = 2568, AArch64_MOVi32imm = 2569, AArch64_MOVi64imm = 2570, AArch64_MRS = 2571, AArch64_MSB_ZPmZZ_B = 2572, AArch64_MSB_ZPmZZ_D = 2573, AArch64_MSB_ZPmZZ_H = 2574, AArch64_MSB_ZPmZZ_S = 2575, AArch64_MSR = 2576, AArch64_MSRpstateImm1 = 2577, AArch64_MSRpstateImm4 = 2578, AArch64_MSUBWrrr = 2579, AArch64_MSUBXrrr = 2580, AArch64_MUL_ZI_B = 2581, AArch64_MUL_ZI_D = 2582, AArch64_MUL_ZI_H = 2583, AArch64_MUL_ZI_S = 2584, AArch64_MUL_ZPmZ_B = 2585, AArch64_MUL_ZPmZ_D = 2586, AArch64_MUL_ZPmZ_H = 2587, AArch64_MUL_ZPmZ_S = 2588, AArch64_MULv16i8 = 2589, AArch64_MULv2i32 = 2590, AArch64_MULv2i32_indexed = 2591, AArch64_MULv4i16 = 2592, AArch64_MULv4i16_indexed = 2593, AArch64_MULv4i32 = 2594, AArch64_MULv4i32_indexed = 2595, AArch64_MULv8i16 = 2596, AArch64_MULv8i16_indexed = 2597, AArch64_MULv8i8 = 2598, AArch64_MVNIv2i32 = 2599, AArch64_MVNIv2s_msl = 2600, AArch64_MVNIv4i16 = 2601, AArch64_MVNIv4i32 = 2602, AArch64_MVNIv4s_msl = 2603, AArch64_MVNIv8i16 = 2604, AArch64_NANDS_PPzPP = 2605, AArch64_NAND_PPzPP = 2606, AArch64_NEG_ZPmZ_B = 2607, AArch64_NEG_ZPmZ_D = 2608, AArch64_NEG_ZPmZ_H = 2609, AArch64_NEG_ZPmZ_S = 2610, AArch64_NEGv16i8 = 2611, AArch64_NEGv1i64 = 2612, AArch64_NEGv2i32 = 2613, AArch64_NEGv2i64 = 2614, AArch64_NEGv4i16 = 2615, AArch64_NEGv4i32 = 2616, AArch64_NEGv8i16 = 2617, AArch64_NEGv8i8 = 2618, AArch64_NORS_PPzPP = 2619, AArch64_NOR_PPzPP = 2620, AArch64_NOT_ZPmZ_B = 2621, AArch64_NOT_ZPmZ_D = 2622, AArch64_NOT_ZPmZ_H = 2623, AArch64_NOT_ZPmZ_S = 2624, AArch64_NOTv16i8 = 2625, AArch64_NOTv8i8 = 2626, AArch64_ORNS_PPzPP = 2627, AArch64_ORNWrr = 2628, AArch64_ORNWrs = 2629, AArch64_ORNXrr = 2630, AArch64_ORNXrs = 2631, AArch64_ORN_PPzPP = 2632, AArch64_ORNv16i8 = 2633, AArch64_ORNv8i8 = 2634, AArch64_ORRS_PPzPP = 2635, AArch64_ORRWri = 2636, AArch64_ORRWrr = 2637, AArch64_ORRWrs = 2638, AArch64_ORRXri = 2639, AArch64_ORRXrr = 2640, AArch64_ORRXrs = 2641, AArch64_ORR_PPzPP = 2642, AArch64_ORR_ZI = 2643, AArch64_ORR_ZPmZ_B = 2644, AArch64_ORR_ZPmZ_D = 2645, AArch64_ORR_ZPmZ_H = 2646, AArch64_ORR_ZPmZ_S = 2647, AArch64_ORR_ZZZ = 2648, AArch64_ORRv16i8 = 2649, AArch64_ORRv2i32 = 2650, AArch64_ORRv4i16 = 2651, AArch64_ORRv4i32 = 2652, AArch64_ORRv8i16 = 2653, AArch64_ORRv8i8 = 2654, AArch64_ORV_VPZ_B = 2655, AArch64_ORV_VPZ_D = 2656, AArch64_ORV_VPZ_H = 2657, AArch64_ORV_VPZ_S = 2658, AArch64_PACDA = 2659, AArch64_PACDB = 2660, AArch64_PACDZA = 2661, AArch64_PACDZB = 2662, AArch64_PACGA = 2663, AArch64_PACIA = 2664, AArch64_PACIA1716 = 2665, AArch64_PACIASP = 2666, AArch64_PACIAZ = 2667, AArch64_PACIB = 2668, AArch64_PACIB1716 = 2669, AArch64_PACIBSP = 2670, AArch64_PACIBZ = 2671, AArch64_PACIZA = 2672, AArch64_PACIZB = 2673, AArch64_PFALSE = 2674, AArch64_PMULLv16i8 = 2675, AArch64_PMULLv1i64 = 2676, AArch64_PMULLv2i64 = 2677, AArch64_PMULLv8i8 = 2678, AArch64_PMULv16i8 = 2679, AArch64_PMULv8i8 = 2680, AArch64_PNEXT_B = 2681, AArch64_PNEXT_D = 2682, AArch64_PNEXT_H = 2683, AArch64_PNEXT_S = 2684, AArch64_PRFB_D_PZI = 2685, AArch64_PRFB_D_SCALED = 2686, AArch64_PRFB_D_SXTW_SCALED = 2687, AArch64_PRFB_D_UXTW_SCALED = 2688, AArch64_PRFB_PRI = 2689, AArch64_PRFB_PRR = 2690, AArch64_PRFB_S_PZI = 2691, AArch64_PRFB_S_SXTW_SCALED = 2692, AArch64_PRFB_S_UXTW_SCALED = 2693, AArch64_PRFD_D_PZI = 2694, AArch64_PRFD_D_SCALED = 2695, AArch64_PRFD_D_SXTW_SCALED = 2696, AArch64_PRFD_D_UXTW_SCALED = 2697, AArch64_PRFD_PRI = 2698, AArch64_PRFD_PRR = 2699, AArch64_PRFD_S_PZI = 2700, AArch64_PRFD_S_SXTW_SCALED = 2701, AArch64_PRFD_S_UXTW_SCALED = 2702, AArch64_PRFH_D_PZI = 2703, AArch64_PRFH_D_SCALED = 2704, AArch64_PRFH_D_SXTW_SCALED = 2705, AArch64_PRFH_D_UXTW_SCALED = 2706, AArch64_PRFH_PRI = 2707, AArch64_PRFH_PRR = 2708, AArch64_PRFH_S_PZI = 2709, AArch64_PRFH_S_SXTW_SCALED = 2710, AArch64_PRFH_S_UXTW_SCALED = 2711, AArch64_PRFMl = 2712, AArch64_PRFMroW = 2713, AArch64_PRFMroX = 2714, AArch64_PRFMui = 2715, AArch64_PRFS_PRR = 2716, AArch64_PRFUMi = 2717, AArch64_PRFW_D_PZI = 2718, AArch64_PRFW_D_SCALED = 2719, AArch64_PRFW_D_SXTW_SCALED = 2720, AArch64_PRFW_D_UXTW_SCALED = 2721, AArch64_PRFW_PRI = 2722, AArch64_PRFW_S_PZI = 2723, AArch64_PRFW_S_SXTW_SCALED = 2724, AArch64_PRFW_S_UXTW_SCALED = 2725, AArch64_PTEST_PP = 2726, AArch64_PTRUES_B = 2727, AArch64_PTRUES_D = 2728, AArch64_PTRUES_H = 2729, AArch64_PTRUES_S = 2730, AArch64_PTRUE_B = 2731, AArch64_PTRUE_D = 2732, AArch64_PTRUE_H = 2733, AArch64_PTRUE_S = 2734, AArch64_PUNPKHI_PP = 2735, AArch64_PUNPKLO_PP = 2736, AArch64_RADDHNv2i64_v2i32 = 2737, AArch64_RADDHNv2i64_v4i32 = 2738, AArch64_RADDHNv4i32_v4i16 = 2739, AArch64_RADDHNv4i32_v8i16 = 2740, AArch64_RADDHNv8i16_v16i8 = 2741, AArch64_RADDHNv8i16_v8i8 = 2742, AArch64_RAX1 = 2743, AArch64_RBITWr = 2744, AArch64_RBITXr = 2745, AArch64_RBIT_ZPmZ_B = 2746, AArch64_RBIT_ZPmZ_D = 2747, AArch64_RBIT_ZPmZ_H = 2748, AArch64_RBIT_ZPmZ_S = 2749, AArch64_RBITv16i8 = 2750, AArch64_RBITv8i8 = 2751, AArch64_RDFFRS_PPz = 2752, AArch64_RDFFR_P = 2753, AArch64_RDFFR_PPz = 2754, AArch64_RDVLI_XI = 2755, AArch64_RET = 2756, AArch64_RETAA = 2757, AArch64_RETAB = 2758, AArch64_RET_ReallyLR = 2759, AArch64_REV16Wr = 2760, AArch64_REV16Xr = 2761, AArch64_REV16v16i8 = 2762, AArch64_REV16v8i8 = 2763, AArch64_REV32Xr = 2764, AArch64_REV32v16i8 = 2765, AArch64_REV32v4i16 = 2766, AArch64_REV32v8i16 = 2767, AArch64_REV32v8i8 = 2768, AArch64_REV64v16i8 = 2769, AArch64_REV64v2i32 = 2770, AArch64_REV64v4i16 = 2771, AArch64_REV64v4i32 = 2772, AArch64_REV64v8i16 = 2773, AArch64_REV64v8i8 = 2774, AArch64_REVB_ZPmZ_D = 2775, AArch64_REVB_ZPmZ_H = 2776, AArch64_REVB_ZPmZ_S = 2777, AArch64_REVH_ZPmZ_D = 2778, AArch64_REVH_ZPmZ_S = 2779, AArch64_REVW_ZPmZ_D = 2780, AArch64_REVWr = 2781, AArch64_REVXr = 2782, AArch64_REV_PP_B = 2783, AArch64_REV_PP_D = 2784, AArch64_REV_PP_H = 2785, AArch64_REV_PP_S = 2786, AArch64_REV_ZZ_B = 2787, AArch64_REV_ZZ_D = 2788, AArch64_REV_ZZ_H = 2789, AArch64_REV_ZZ_S = 2790, AArch64_RMIF = 2791, AArch64_RORVWr = 2792, AArch64_RORVXr = 2793, AArch64_RSHRNv16i8_shift = 2794, AArch64_RSHRNv2i32_shift = 2795, AArch64_RSHRNv4i16_shift = 2796, AArch64_RSHRNv4i32_shift = 2797, AArch64_RSHRNv8i16_shift = 2798, AArch64_RSHRNv8i8_shift = 2799, AArch64_RSUBHNv2i64_v2i32 = 2800, AArch64_RSUBHNv2i64_v4i32 = 2801, AArch64_RSUBHNv4i32_v4i16 = 2802, AArch64_RSUBHNv4i32_v8i16 = 2803, AArch64_RSUBHNv8i16_v16i8 = 2804, AArch64_RSUBHNv8i16_v8i8 = 2805, AArch64_SABALv16i8_v8i16 = 2806, AArch64_SABALv2i32_v2i64 = 2807, AArch64_SABALv4i16_v4i32 = 2808, AArch64_SABALv4i32_v2i64 = 2809, AArch64_SABALv8i16_v4i32 = 2810, AArch64_SABALv8i8_v8i16 = 2811, AArch64_SABAv16i8 = 2812, AArch64_SABAv2i32 = 2813, AArch64_SABAv4i16 = 2814, AArch64_SABAv4i32 = 2815, AArch64_SABAv8i16 = 2816, AArch64_SABAv8i8 = 2817, AArch64_SABDLv16i8_v8i16 = 2818, AArch64_SABDLv2i32_v2i64 = 2819, AArch64_SABDLv4i16_v4i32 = 2820, AArch64_SABDLv4i32_v2i64 = 2821, AArch64_SABDLv8i16_v4i32 = 2822, AArch64_SABDLv8i8_v8i16 = 2823, AArch64_SABD_ZPmZ_B = 2824, AArch64_SABD_ZPmZ_D = 2825, AArch64_SABD_ZPmZ_H = 2826, AArch64_SABD_ZPmZ_S = 2827, AArch64_SABDv16i8 = 2828, AArch64_SABDv2i32 = 2829, AArch64_SABDv4i16 = 2830, AArch64_SABDv4i32 = 2831, AArch64_SABDv8i16 = 2832, AArch64_SABDv8i8 = 2833, AArch64_SADALPv16i8_v8i16 = 2834, AArch64_SADALPv2i32_v1i64 = 2835, AArch64_SADALPv4i16_v2i32 = 2836, AArch64_SADALPv4i32_v2i64 = 2837, AArch64_SADALPv8i16_v4i32 = 2838, AArch64_SADALPv8i8_v4i16 = 2839, AArch64_SADDLPv16i8_v8i16 = 2840, AArch64_SADDLPv2i32_v1i64 = 2841, AArch64_SADDLPv4i16_v2i32 = 2842, AArch64_SADDLPv4i32_v2i64 = 2843, AArch64_SADDLPv8i16_v4i32 = 2844, AArch64_SADDLPv8i8_v4i16 = 2845, AArch64_SADDLVv16i8v = 2846, AArch64_SADDLVv4i16v = 2847, AArch64_SADDLVv4i32v = 2848, AArch64_SADDLVv8i16v = 2849, AArch64_SADDLVv8i8v = 2850, AArch64_SADDLv16i8_v8i16 = 2851, AArch64_SADDLv2i32_v2i64 = 2852, AArch64_SADDLv4i16_v4i32 = 2853, AArch64_SADDLv4i32_v2i64 = 2854, AArch64_SADDLv8i16_v4i32 = 2855, AArch64_SADDLv8i8_v8i16 = 2856, AArch64_SADDV_VPZ_B = 2857, AArch64_SADDV_VPZ_H = 2858, AArch64_SADDV_VPZ_S = 2859, AArch64_SADDWv16i8_v8i16 = 2860, AArch64_SADDWv2i32_v2i64 = 2861, AArch64_SADDWv4i16_v4i32 = 2862, AArch64_SADDWv4i32_v2i64 = 2863, AArch64_SADDWv8i16_v4i32 = 2864, AArch64_SADDWv8i8_v8i16 = 2865, AArch64_SBCSWr = 2866, AArch64_SBCSXr = 2867, AArch64_SBCWr = 2868, AArch64_SBCXr = 2869, AArch64_SBFMWri = 2870, AArch64_SBFMXri = 2871, AArch64_SCVTFSWDri = 2872, AArch64_SCVTFSWHri = 2873, AArch64_SCVTFSWSri = 2874, AArch64_SCVTFSXDri = 2875, AArch64_SCVTFSXHri = 2876, AArch64_SCVTFSXSri = 2877, AArch64_SCVTFUWDri = 2878, AArch64_SCVTFUWHri = 2879, AArch64_SCVTFUWSri = 2880, AArch64_SCVTFUXDri = 2881, AArch64_SCVTFUXHri = 2882, AArch64_SCVTFUXSri = 2883, AArch64_SCVTF_ZPmZ_DtoD = 2884, AArch64_SCVTF_ZPmZ_DtoH = 2885, AArch64_SCVTF_ZPmZ_DtoS = 2886, AArch64_SCVTF_ZPmZ_HtoH = 2887, AArch64_SCVTF_ZPmZ_StoD = 2888, AArch64_SCVTF_ZPmZ_StoH = 2889, AArch64_SCVTF_ZPmZ_StoS = 2890, AArch64_SCVTFd = 2891, AArch64_SCVTFh = 2892, AArch64_SCVTFs = 2893, AArch64_SCVTFv1i16 = 2894, AArch64_SCVTFv1i32 = 2895, AArch64_SCVTFv1i64 = 2896, AArch64_SCVTFv2f32 = 2897, AArch64_SCVTFv2f64 = 2898, AArch64_SCVTFv2i32_shift = 2899, AArch64_SCVTFv2i64_shift = 2900, AArch64_SCVTFv4f16 = 2901, AArch64_SCVTFv4f32 = 2902, AArch64_SCVTFv4i16_shift = 2903, AArch64_SCVTFv4i32_shift = 2904, AArch64_SCVTFv8f16 = 2905, AArch64_SCVTFv8i16_shift = 2906, AArch64_SDIVR_ZPmZ_D = 2907, AArch64_SDIVR_ZPmZ_S = 2908, AArch64_SDIVWr = 2909, AArch64_SDIVXr = 2910, AArch64_SDIV_ZPmZ_D = 2911, AArch64_SDIV_ZPmZ_S = 2912, AArch64_SDOT_ZZZI_D = 2913, AArch64_SDOT_ZZZI_S = 2914, AArch64_SDOT_ZZZ_D = 2915, AArch64_SDOT_ZZZ_S = 2916, AArch64_SDOTlanev16i8 = 2917, AArch64_SDOTlanev8i8 = 2918, AArch64_SDOTv16i8 = 2919, AArch64_SDOTv8i8 = 2920, AArch64_SEL_PPPP = 2921, AArch64_SEL_ZPZZ_B = 2922, AArch64_SEL_ZPZZ_D = 2923, AArch64_SEL_ZPZZ_H = 2924, AArch64_SEL_ZPZZ_S = 2925, AArch64_SETF16 = 2926, AArch64_SETF8 = 2927, AArch64_SETFFR = 2928, AArch64_SHA1Crrr = 2929, AArch64_SHA1Hrr = 2930, AArch64_SHA1Mrrr = 2931, AArch64_SHA1Prrr = 2932, AArch64_SHA1SU0rrr = 2933, AArch64_SHA1SU1rr = 2934, AArch64_SHA256H2rrr = 2935, AArch64_SHA256Hrrr = 2936, AArch64_SHA256SU0rr = 2937, AArch64_SHA256SU1rrr = 2938, AArch64_SHA512H = 2939, AArch64_SHA512H2 = 2940, AArch64_SHA512SU0 = 2941, AArch64_SHA512SU1 = 2942, AArch64_SHADDv16i8 = 2943, AArch64_SHADDv2i32 = 2944, AArch64_SHADDv4i16 = 2945, AArch64_SHADDv4i32 = 2946, AArch64_SHADDv8i16 = 2947, AArch64_SHADDv8i8 = 2948, AArch64_SHLLv16i8 = 2949, AArch64_SHLLv2i32 = 2950, AArch64_SHLLv4i16 = 2951, AArch64_SHLLv4i32 = 2952, AArch64_SHLLv8i16 = 2953, AArch64_SHLLv8i8 = 2954, AArch64_SHLd = 2955, AArch64_SHLv16i8_shift = 2956, AArch64_SHLv2i32_shift = 2957, AArch64_SHLv2i64_shift = 2958, AArch64_SHLv4i16_shift = 2959, AArch64_SHLv4i32_shift = 2960, AArch64_SHLv8i16_shift = 2961, AArch64_SHLv8i8_shift = 2962, AArch64_SHRNv16i8_shift = 2963, AArch64_SHRNv2i32_shift = 2964, AArch64_SHRNv4i16_shift = 2965, AArch64_SHRNv4i32_shift = 2966, AArch64_SHRNv8i16_shift = 2967, AArch64_SHRNv8i8_shift = 2968, AArch64_SHSUBv16i8 = 2969, AArch64_SHSUBv2i32 = 2970, AArch64_SHSUBv4i16 = 2971, AArch64_SHSUBv4i32 = 2972, AArch64_SHSUBv8i16 = 2973, AArch64_SHSUBv8i8 = 2974, AArch64_SLId = 2975, AArch64_SLIv16i8_shift = 2976, AArch64_SLIv2i32_shift = 2977, AArch64_SLIv2i64_shift = 2978, AArch64_SLIv4i16_shift = 2979, AArch64_SLIv4i32_shift = 2980, AArch64_SLIv8i16_shift = 2981, AArch64_SLIv8i8_shift = 2982, AArch64_SM3PARTW1 = 2983, AArch64_SM3PARTW2 = 2984, AArch64_SM3SS1 = 2985, AArch64_SM3TT1A = 2986, AArch64_SM3TT1B = 2987, AArch64_SM3TT2A = 2988, AArch64_SM3TT2B = 2989, AArch64_SM4E = 2990, AArch64_SM4ENCKEY = 2991, AArch64_SMADDLrrr = 2992, AArch64_SMAXPv16i8 = 2993, AArch64_SMAXPv2i32 = 2994, AArch64_SMAXPv4i16 = 2995, AArch64_SMAXPv4i32 = 2996, AArch64_SMAXPv8i16 = 2997, AArch64_SMAXPv8i8 = 2998, AArch64_SMAXV_VPZ_B = 2999, AArch64_SMAXV_VPZ_D = 3000, AArch64_SMAXV_VPZ_H = 3001, AArch64_SMAXV_VPZ_S = 3002, AArch64_SMAXVv16i8v = 3003, AArch64_SMAXVv4i16v = 3004, AArch64_SMAXVv4i32v = 3005, AArch64_SMAXVv8i16v = 3006, AArch64_SMAXVv8i8v = 3007, AArch64_SMAX_ZI_B = 3008, AArch64_SMAX_ZI_D = 3009, AArch64_SMAX_ZI_H = 3010, AArch64_SMAX_ZI_S = 3011, AArch64_SMAX_ZPmZ_B = 3012, AArch64_SMAX_ZPmZ_D = 3013, AArch64_SMAX_ZPmZ_H = 3014, AArch64_SMAX_ZPmZ_S = 3015, AArch64_SMAXv16i8 = 3016, AArch64_SMAXv2i32 = 3017, AArch64_SMAXv4i16 = 3018, AArch64_SMAXv4i32 = 3019, AArch64_SMAXv8i16 = 3020, AArch64_SMAXv8i8 = 3021, AArch64_SMC = 3022, AArch64_SMINPv16i8 = 3023, AArch64_SMINPv2i32 = 3024, AArch64_SMINPv4i16 = 3025, AArch64_SMINPv4i32 = 3026, AArch64_SMINPv8i16 = 3027, AArch64_SMINPv8i8 = 3028, AArch64_SMINV_VPZ_B = 3029, AArch64_SMINV_VPZ_D = 3030, AArch64_SMINV_VPZ_H = 3031, AArch64_SMINV_VPZ_S = 3032, AArch64_SMINVv16i8v = 3033, AArch64_SMINVv4i16v = 3034, AArch64_SMINVv4i32v = 3035, AArch64_SMINVv8i16v = 3036, AArch64_SMINVv8i8v = 3037, AArch64_SMIN_ZI_B = 3038, AArch64_SMIN_ZI_D = 3039, AArch64_SMIN_ZI_H = 3040, AArch64_SMIN_ZI_S = 3041, AArch64_SMIN_ZPmZ_B = 3042, AArch64_SMIN_ZPmZ_D = 3043, AArch64_SMIN_ZPmZ_H = 3044, AArch64_SMIN_ZPmZ_S = 3045, AArch64_SMINv16i8 = 3046, AArch64_SMINv2i32 = 3047, AArch64_SMINv4i16 = 3048, AArch64_SMINv4i32 = 3049, AArch64_SMINv8i16 = 3050, AArch64_SMINv8i8 = 3051, AArch64_SMLALv16i8_v8i16 = 3052, AArch64_SMLALv2i32_indexed = 3053, AArch64_SMLALv2i32_v2i64 = 3054, AArch64_SMLALv4i16_indexed = 3055, AArch64_SMLALv4i16_v4i32 = 3056, AArch64_SMLALv4i32_indexed = 3057, AArch64_SMLALv4i32_v2i64 = 3058, AArch64_SMLALv8i16_indexed = 3059, AArch64_SMLALv8i16_v4i32 = 3060, AArch64_SMLALv8i8_v8i16 = 3061, AArch64_SMLSLv16i8_v8i16 = 3062, AArch64_SMLSLv2i32_indexed = 3063, AArch64_SMLSLv2i32_v2i64 = 3064, AArch64_SMLSLv4i16_indexed = 3065, AArch64_SMLSLv4i16_v4i32 = 3066, AArch64_SMLSLv4i32_indexed = 3067, AArch64_SMLSLv4i32_v2i64 = 3068, AArch64_SMLSLv8i16_indexed = 3069, AArch64_SMLSLv8i16_v4i32 = 3070, AArch64_SMLSLv8i8_v8i16 = 3071, AArch64_SMOVvi16to32 = 3072, AArch64_SMOVvi16to64 = 3073, AArch64_SMOVvi32to64 = 3074, AArch64_SMOVvi8to32 = 3075, AArch64_SMOVvi8to64 = 3076, AArch64_SMSUBLrrr = 3077, AArch64_SMULH_ZPmZ_B = 3078, AArch64_SMULH_ZPmZ_D = 3079, AArch64_SMULH_ZPmZ_H = 3080, AArch64_SMULH_ZPmZ_S = 3081, AArch64_SMULHrr = 3082, AArch64_SMULLv16i8_v8i16 = 3083, AArch64_SMULLv2i32_indexed = 3084, AArch64_SMULLv2i32_v2i64 = 3085, AArch64_SMULLv4i16_indexed = 3086, AArch64_SMULLv4i16_v4i32 = 3087, AArch64_SMULLv4i32_indexed = 3088, AArch64_SMULLv4i32_v2i64 = 3089, AArch64_SMULLv8i16_indexed = 3090, AArch64_SMULLv8i16_v4i32 = 3091, AArch64_SMULLv8i8_v8i16 = 3092, AArch64_SPLICE_ZPZ_B = 3093, AArch64_SPLICE_ZPZ_D = 3094, AArch64_SPLICE_ZPZ_H = 3095, AArch64_SPLICE_ZPZ_S = 3096, AArch64_SQABSv16i8 = 3097, AArch64_SQABSv1i16 = 3098, AArch64_SQABSv1i32 = 3099, AArch64_SQABSv1i64 = 3100, AArch64_SQABSv1i8 = 3101, AArch64_SQABSv2i32 = 3102, AArch64_SQABSv2i64 = 3103, AArch64_SQABSv4i16 = 3104, AArch64_SQABSv4i32 = 3105, AArch64_SQABSv8i16 = 3106, AArch64_SQABSv8i8 = 3107, AArch64_SQADD_ZI_B = 3108, AArch64_SQADD_ZI_D = 3109, AArch64_SQADD_ZI_H = 3110, AArch64_SQADD_ZI_S = 3111, AArch64_SQADD_ZZZ_B = 3112, AArch64_SQADD_ZZZ_D = 3113, AArch64_SQADD_ZZZ_H = 3114, AArch64_SQADD_ZZZ_S = 3115, AArch64_SQADDv16i8 = 3116, AArch64_SQADDv1i16 = 3117, AArch64_SQADDv1i32 = 3118, AArch64_SQADDv1i64 = 3119, AArch64_SQADDv1i8 = 3120, AArch64_SQADDv2i32 = 3121, AArch64_SQADDv2i64 = 3122, AArch64_SQADDv4i16 = 3123, AArch64_SQADDv4i32 = 3124, AArch64_SQADDv8i16 = 3125, AArch64_SQADDv8i8 = 3126, AArch64_SQDECB_XPiI = 3127, AArch64_SQDECB_XPiWdI = 3128, AArch64_SQDECD_XPiI = 3129, AArch64_SQDECD_XPiWdI = 3130, AArch64_SQDECD_ZPiI = 3131, AArch64_SQDECH_XPiI = 3132, AArch64_SQDECH_XPiWdI = 3133, AArch64_SQDECH_ZPiI = 3134, AArch64_SQDECP_XPWd_B = 3135, AArch64_SQDECP_XPWd_D = 3136, AArch64_SQDECP_XPWd_H = 3137, AArch64_SQDECP_XPWd_S = 3138, AArch64_SQDECP_XP_B = 3139, AArch64_SQDECP_XP_D = 3140, AArch64_SQDECP_XP_H = 3141, AArch64_SQDECP_XP_S = 3142, AArch64_SQDECP_ZP_D = 3143, AArch64_SQDECP_ZP_H = 3144, AArch64_SQDECP_ZP_S = 3145, AArch64_SQDECW_XPiI = 3146, AArch64_SQDECW_XPiWdI = 3147, AArch64_SQDECW_ZPiI = 3148, AArch64_SQDMLALi16 = 3149, AArch64_SQDMLALi32 = 3150, AArch64_SQDMLALv1i32_indexed = 3151, AArch64_SQDMLALv1i64_indexed = 3152, AArch64_SQDMLALv2i32_indexed = 3153, AArch64_SQDMLALv2i32_v2i64 = 3154, AArch64_SQDMLALv4i16_indexed = 3155, AArch64_SQDMLALv4i16_v4i32 = 3156, AArch64_SQDMLALv4i32_indexed = 3157, AArch64_SQDMLALv4i32_v2i64 = 3158, AArch64_SQDMLALv8i16_indexed = 3159, AArch64_SQDMLALv8i16_v4i32 = 3160, AArch64_SQDMLSLi16 = 3161, AArch64_SQDMLSLi32 = 3162, AArch64_SQDMLSLv1i32_indexed = 3163, AArch64_SQDMLSLv1i64_indexed = 3164, AArch64_SQDMLSLv2i32_indexed = 3165, AArch64_SQDMLSLv2i32_v2i64 = 3166, AArch64_SQDMLSLv4i16_indexed = 3167, AArch64_SQDMLSLv4i16_v4i32 = 3168, AArch64_SQDMLSLv4i32_indexed = 3169, AArch64_SQDMLSLv4i32_v2i64 = 3170, AArch64_SQDMLSLv8i16_indexed = 3171, AArch64_SQDMLSLv8i16_v4i32 = 3172, AArch64_SQDMULHv1i16 = 3173, AArch64_SQDMULHv1i16_indexed = 3174, AArch64_SQDMULHv1i32 = 3175, AArch64_SQDMULHv1i32_indexed = 3176, AArch64_SQDMULHv2i32 = 3177, AArch64_SQDMULHv2i32_indexed = 3178, AArch64_SQDMULHv4i16 = 3179, AArch64_SQDMULHv4i16_indexed = 3180, AArch64_SQDMULHv4i32 = 3181, AArch64_SQDMULHv4i32_indexed = 3182, AArch64_SQDMULHv8i16 = 3183, AArch64_SQDMULHv8i16_indexed = 3184, AArch64_SQDMULLi16 = 3185, AArch64_SQDMULLi32 = 3186, AArch64_SQDMULLv1i32_indexed = 3187, AArch64_SQDMULLv1i64_indexed = 3188, AArch64_SQDMULLv2i32_indexed = 3189, AArch64_SQDMULLv2i32_v2i64 = 3190, AArch64_SQDMULLv4i16_indexed = 3191, AArch64_SQDMULLv4i16_v4i32 = 3192, AArch64_SQDMULLv4i32_indexed = 3193, AArch64_SQDMULLv4i32_v2i64 = 3194, AArch64_SQDMULLv8i16_indexed = 3195, AArch64_SQDMULLv8i16_v4i32 = 3196, AArch64_SQINCB_XPiI = 3197, AArch64_SQINCB_XPiWdI = 3198, AArch64_SQINCD_XPiI = 3199, AArch64_SQINCD_XPiWdI = 3200, AArch64_SQINCD_ZPiI = 3201, AArch64_SQINCH_XPiI = 3202, AArch64_SQINCH_XPiWdI = 3203, AArch64_SQINCH_ZPiI = 3204, AArch64_SQINCP_XPWd_B = 3205, AArch64_SQINCP_XPWd_D = 3206, AArch64_SQINCP_XPWd_H = 3207, AArch64_SQINCP_XPWd_S = 3208, AArch64_SQINCP_XP_B = 3209, AArch64_SQINCP_XP_D = 3210, AArch64_SQINCP_XP_H = 3211, AArch64_SQINCP_XP_S = 3212, AArch64_SQINCP_ZP_D = 3213, AArch64_SQINCP_ZP_H = 3214, AArch64_SQINCP_ZP_S = 3215, AArch64_SQINCW_XPiI = 3216, AArch64_SQINCW_XPiWdI = 3217, AArch64_SQINCW_ZPiI = 3218, AArch64_SQNEGv16i8 = 3219, AArch64_SQNEGv1i16 = 3220, AArch64_SQNEGv1i32 = 3221, AArch64_SQNEGv1i64 = 3222, AArch64_SQNEGv1i8 = 3223, AArch64_SQNEGv2i32 = 3224, AArch64_SQNEGv2i64 = 3225, AArch64_SQNEGv4i16 = 3226, AArch64_SQNEGv4i32 = 3227, AArch64_SQNEGv8i16 = 3228, AArch64_SQNEGv8i8 = 3229, AArch64_SQRDMLAHi16_indexed = 3230, AArch64_SQRDMLAHi32_indexed = 3231, AArch64_SQRDMLAHv1i16 = 3232, AArch64_SQRDMLAHv1i32 = 3233, AArch64_SQRDMLAHv2i32 = 3234, AArch64_SQRDMLAHv2i32_indexed = 3235, AArch64_SQRDMLAHv4i16 = 3236, AArch64_SQRDMLAHv4i16_indexed = 3237, AArch64_SQRDMLAHv4i32 = 3238, AArch64_SQRDMLAHv4i32_indexed = 3239, AArch64_SQRDMLAHv8i16 = 3240, AArch64_SQRDMLAHv8i16_indexed = 3241, AArch64_SQRDMLSHi16_indexed = 3242, AArch64_SQRDMLSHi32_indexed = 3243, AArch64_SQRDMLSHv1i16 = 3244, AArch64_SQRDMLSHv1i32 = 3245, AArch64_SQRDMLSHv2i32 = 3246, AArch64_SQRDMLSHv2i32_indexed = 3247, AArch64_SQRDMLSHv4i16 = 3248, AArch64_SQRDMLSHv4i16_indexed = 3249, AArch64_SQRDMLSHv4i32 = 3250, AArch64_SQRDMLSHv4i32_indexed = 3251, AArch64_SQRDMLSHv8i16 = 3252, AArch64_SQRDMLSHv8i16_indexed = 3253, AArch64_SQRDMULHv1i16 = 3254, AArch64_SQRDMULHv1i16_indexed = 3255, AArch64_SQRDMULHv1i32 = 3256, AArch64_SQRDMULHv1i32_indexed = 3257, AArch64_SQRDMULHv2i32 = 3258, AArch64_SQRDMULHv2i32_indexed = 3259, AArch64_SQRDMULHv4i16 = 3260, AArch64_SQRDMULHv4i16_indexed = 3261, AArch64_SQRDMULHv4i32 = 3262, AArch64_SQRDMULHv4i32_indexed = 3263, AArch64_SQRDMULHv8i16 = 3264, AArch64_SQRDMULHv8i16_indexed = 3265, AArch64_SQRSHLv16i8 = 3266, AArch64_SQRSHLv1i16 = 3267, AArch64_SQRSHLv1i32 = 3268, AArch64_SQRSHLv1i64 = 3269, AArch64_SQRSHLv1i8 = 3270, AArch64_SQRSHLv2i32 = 3271, AArch64_SQRSHLv2i64 = 3272, AArch64_SQRSHLv4i16 = 3273, AArch64_SQRSHLv4i32 = 3274, AArch64_SQRSHLv8i16 = 3275, AArch64_SQRSHLv8i8 = 3276, AArch64_SQRSHRNb = 3277, AArch64_SQRSHRNh = 3278, AArch64_SQRSHRNs = 3279, AArch64_SQRSHRNv16i8_shift = 3280, AArch64_SQRSHRNv2i32_shift = 3281, AArch64_SQRSHRNv4i16_shift = 3282, AArch64_SQRSHRNv4i32_shift = 3283, AArch64_SQRSHRNv8i16_shift = 3284, AArch64_SQRSHRNv8i8_shift = 3285, AArch64_SQRSHRUNb = 3286, AArch64_SQRSHRUNh = 3287, AArch64_SQRSHRUNs = 3288, AArch64_SQRSHRUNv16i8_shift = 3289, AArch64_SQRSHRUNv2i32_shift = 3290, AArch64_SQRSHRUNv4i16_shift = 3291, AArch64_SQRSHRUNv4i32_shift = 3292, AArch64_SQRSHRUNv8i16_shift = 3293, AArch64_SQRSHRUNv8i8_shift = 3294, AArch64_SQSHLUb = 3295, AArch64_SQSHLUd = 3296, AArch64_SQSHLUh = 3297, AArch64_SQSHLUs = 3298, AArch64_SQSHLUv16i8_shift = 3299, AArch64_SQSHLUv2i32_shift = 3300, AArch64_SQSHLUv2i64_shift = 3301, AArch64_SQSHLUv4i16_shift = 3302, AArch64_SQSHLUv4i32_shift = 3303, AArch64_SQSHLUv8i16_shift = 3304, AArch64_SQSHLUv8i8_shift = 3305, AArch64_SQSHLb = 3306, AArch64_SQSHLd = 3307, AArch64_SQSHLh = 3308, AArch64_SQSHLs = 3309, AArch64_SQSHLv16i8 = 3310, AArch64_SQSHLv16i8_shift = 3311, AArch64_SQSHLv1i16 = 3312, AArch64_SQSHLv1i32 = 3313, AArch64_SQSHLv1i64 = 3314, AArch64_SQSHLv1i8 = 3315, AArch64_SQSHLv2i32 = 3316, AArch64_SQSHLv2i32_shift = 3317, AArch64_SQSHLv2i64 = 3318, AArch64_SQSHLv2i64_shift = 3319, AArch64_SQSHLv4i16 = 3320, AArch64_SQSHLv4i16_shift = 3321, AArch64_SQSHLv4i32 = 3322, AArch64_SQSHLv4i32_shift = 3323, AArch64_SQSHLv8i16 = 3324, AArch64_SQSHLv8i16_shift = 3325, AArch64_SQSHLv8i8 = 3326, AArch64_SQSHLv8i8_shift = 3327, AArch64_SQSHRNb = 3328, AArch64_SQSHRNh = 3329, AArch64_SQSHRNs = 3330, AArch64_SQSHRNv16i8_shift = 3331, AArch64_SQSHRNv2i32_shift = 3332, AArch64_SQSHRNv4i16_shift = 3333, AArch64_SQSHRNv4i32_shift = 3334, AArch64_SQSHRNv8i16_shift = 3335, AArch64_SQSHRNv8i8_shift = 3336, AArch64_SQSHRUNb = 3337, AArch64_SQSHRUNh = 3338, AArch64_SQSHRUNs = 3339, AArch64_SQSHRUNv16i8_shift = 3340, AArch64_SQSHRUNv2i32_shift = 3341, AArch64_SQSHRUNv4i16_shift = 3342, AArch64_SQSHRUNv4i32_shift = 3343, AArch64_SQSHRUNv8i16_shift = 3344, AArch64_SQSHRUNv8i8_shift = 3345, AArch64_SQSUB_ZI_B = 3346, AArch64_SQSUB_ZI_D = 3347, AArch64_SQSUB_ZI_H = 3348, AArch64_SQSUB_ZI_S = 3349, AArch64_SQSUB_ZZZ_B = 3350, AArch64_SQSUB_ZZZ_D = 3351, AArch64_SQSUB_ZZZ_H = 3352, AArch64_SQSUB_ZZZ_S = 3353, AArch64_SQSUBv16i8 = 3354, AArch64_SQSUBv1i16 = 3355, AArch64_SQSUBv1i32 = 3356, AArch64_SQSUBv1i64 = 3357, AArch64_SQSUBv1i8 = 3358, AArch64_SQSUBv2i32 = 3359, AArch64_SQSUBv2i64 = 3360, AArch64_SQSUBv4i16 = 3361, AArch64_SQSUBv4i32 = 3362, AArch64_SQSUBv8i16 = 3363, AArch64_SQSUBv8i8 = 3364, AArch64_SQXTNv16i8 = 3365, AArch64_SQXTNv1i16 = 3366, AArch64_SQXTNv1i32 = 3367, AArch64_SQXTNv1i8 = 3368, AArch64_SQXTNv2i32 = 3369, AArch64_SQXTNv4i16 = 3370, AArch64_SQXTNv4i32 = 3371, AArch64_SQXTNv8i16 = 3372, AArch64_SQXTNv8i8 = 3373, AArch64_SQXTUNv16i8 = 3374, AArch64_SQXTUNv1i16 = 3375, AArch64_SQXTUNv1i32 = 3376, AArch64_SQXTUNv1i8 = 3377, AArch64_SQXTUNv2i32 = 3378, AArch64_SQXTUNv4i16 = 3379, AArch64_SQXTUNv4i32 = 3380, AArch64_SQXTUNv8i16 = 3381, AArch64_SQXTUNv8i8 = 3382, AArch64_SRHADDv16i8 = 3383, AArch64_SRHADDv2i32 = 3384, AArch64_SRHADDv4i16 = 3385, AArch64_SRHADDv4i32 = 3386, AArch64_SRHADDv8i16 = 3387, AArch64_SRHADDv8i8 = 3388, AArch64_SRId = 3389, AArch64_SRIv16i8_shift = 3390, AArch64_SRIv2i32_shift = 3391, AArch64_SRIv2i64_shift = 3392, AArch64_SRIv4i16_shift = 3393, AArch64_SRIv4i32_shift = 3394, AArch64_SRIv8i16_shift = 3395, AArch64_SRIv8i8_shift = 3396, AArch64_SRSHLv16i8 = 3397, AArch64_SRSHLv1i64 = 3398, AArch64_SRSHLv2i32 = 3399, AArch64_SRSHLv2i64 = 3400, AArch64_SRSHLv4i16 = 3401, AArch64_SRSHLv4i32 = 3402, AArch64_SRSHLv8i16 = 3403, AArch64_SRSHLv8i8 = 3404, AArch64_SRSHRd = 3405, AArch64_SRSHRv16i8_shift = 3406, AArch64_SRSHRv2i32_shift = 3407, AArch64_SRSHRv2i64_shift = 3408, AArch64_SRSHRv4i16_shift = 3409, AArch64_SRSHRv4i32_shift = 3410, AArch64_SRSHRv8i16_shift = 3411, AArch64_SRSHRv8i8_shift = 3412, AArch64_SRSRAd = 3413, AArch64_SRSRAv16i8_shift = 3414, AArch64_SRSRAv2i32_shift = 3415, AArch64_SRSRAv2i64_shift = 3416, AArch64_SRSRAv4i16_shift = 3417, AArch64_SRSRAv4i32_shift = 3418, AArch64_SRSRAv8i16_shift = 3419, AArch64_SRSRAv8i8_shift = 3420, AArch64_SSHLLv16i8_shift = 3421, AArch64_SSHLLv2i32_shift = 3422, AArch64_SSHLLv4i16_shift = 3423, AArch64_SSHLLv4i32_shift = 3424, AArch64_SSHLLv8i16_shift = 3425, AArch64_SSHLLv8i8_shift = 3426, AArch64_SSHLv16i8 = 3427, AArch64_SSHLv1i64 = 3428, AArch64_SSHLv2i32 = 3429, AArch64_SSHLv2i64 = 3430, AArch64_SSHLv4i16 = 3431, AArch64_SSHLv4i32 = 3432, AArch64_SSHLv8i16 = 3433, AArch64_SSHLv8i8 = 3434, AArch64_SSHRd = 3435, AArch64_SSHRv16i8_shift = 3436, AArch64_SSHRv2i32_shift = 3437, AArch64_SSHRv2i64_shift = 3438, AArch64_SSHRv4i16_shift = 3439, AArch64_SSHRv4i32_shift = 3440, AArch64_SSHRv8i16_shift = 3441, AArch64_SSHRv8i8_shift = 3442, AArch64_SSRAd = 3443, AArch64_SSRAv16i8_shift = 3444, AArch64_SSRAv2i32_shift = 3445, AArch64_SSRAv2i64_shift = 3446, AArch64_SSRAv4i16_shift = 3447, AArch64_SSRAv4i32_shift = 3448, AArch64_SSRAv8i16_shift = 3449, AArch64_SSRAv8i8_shift = 3450, AArch64_SST1B_D = 3451, AArch64_SST1B_D_IMM = 3452, AArch64_SST1B_D_SXTW = 3453, AArch64_SST1B_D_UXTW = 3454, AArch64_SST1B_S_IMM = 3455, AArch64_SST1B_S_SXTW = 3456, AArch64_SST1B_S_UXTW = 3457, AArch64_SST1D = 3458, AArch64_SST1D_IMM = 3459, AArch64_SST1D_SCALED = 3460, AArch64_SST1D_SXTW = 3461, AArch64_SST1D_SXTW_SCALED = 3462, AArch64_SST1D_UXTW = 3463, AArch64_SST1D_UXTW_SCALED = 3464, AArch64_SST1H_D = 3465, AArch64_SST1H_D_IMM = 3466, AArch64_SST1H_D_SCALED = 3467, AArch64_SST1H_D_SXTW = 3468, AArch64_SST1H_D_SXTW_SCALED = 3469, AArch64_SST1H_D_UXTW = 3470, AArch64_SST1H_D_UXTW_SCALED = 3471, AArch64_SST1H_S_IMM = 3472, AArch64_SST1H_S_SXTW = 3473, AArch64_SST1H_S_SXTW_SCALED = 3474, AArch64_SST1H_S_UXTW = 3475, AArch64_SST1H_S_UXTW_SCALED = 3476, AArch64_SST1W_D = 3477, AArch64_SST1W_D_IMM = 3478, AArch64_SST1W_D_SCALED = 3479, AArch64_SST1W_D_SXTW = 3480, AArch64_SST1W_D_SXTW_SCALED = 3481, AArch64_SST1W_D_UXTW = 3482, AArch64_SST1W_D_UXTW_SCALED = 3483, AArch64_SST1W_IMM = 3484, AArch64_SST1W_SXTW = 3485, AArch64_SST1W_SXTW_SCALED = 3486, AArch64_SST1W_UXTW = 3487, AArch64_SST1W_UXTW_SCALED = 3488, AArch64_SSUBLv16i8_v8i16 = 3489, AArch64_SSUBLv2i32_v2i64 = 3490, AArch64_SSUBLv4i16_v4i32 = 3491, AArch64_SSUBLv4i32_v2i64 = 3492, AArch64_SSUBLv8i16_v4i32 = 3493, AArch64_SSUBLv8i8_v8i16 = 3494, AArch64_SSUBWv16i8_v8i16 = 3495, AArch64_SSUBWv2i32_v2i64 = 3496, AArch64_SSUBWv4i16_v4i32 = 3497, AArch64_SSUBWv4i32_v2i64 = 3498, AArch64_SSUBWv8i16_v4i32 = 3499, AArch64_SSUBWv8i8_v8i16 = 3500, AArch64_ST1B = 3501, AArch64_ST1B_D = 3502, AArch64_ST1B_D_IMM = 3503, AArch64_ST1B_H = 3504, AArch64_ST1B_H_IMM = 3505, AArch64_ST1B_IMM = 3506, AArch64_ST1B_S = 3507, AArch64_ST1B_S_IMM = 3508, AArch64_ST1D = 3509, AArch64_ST1D_IMM = 3510, AArch64_ST1Fourv16b = 3511, AArch64_ST1Fourv16b_POST = 3512, AArch64_ST1Fourv1d = 3513, AArch64_ST1Fourv1d_POST = 3514, AArch64_ST1Fourv2d = 3515, AArch64_ST1Fourv2d_POST = 3516, AArch64_ST1Fourv2s = 3517, AArch64_ST1Fourv2s_POST = 3518, AArch64_ST1Fourv4h = 3519, AArch64_ST1Fourv4h_POST = 3520, AArch64_ST1Fourv4s = 3521, AArch64_ST1Fourv4s_POST = 3522, AArch64_ST1Fourv8b = 3523, AArch64_ST1Fourv8b_POST = 3524, AArch64_ST1Fourv8h = 3525, AArch64_ST1Fourv8h_POST = 3526, AArch64_ST1H = 3527, AArch64_ST1H_D = 3528, AArch64_ST1H_D_IMM = 3529, AArch64_ST1H_IMM = 3530, AArch64_ST1H_S = 3531, AArch64_ST1H_S_IMM = 3532, AArch64_ST1Onev16b = 3533, AArch64_ST1Onev16b_POST = 3534, AArch64_ST1Onev1d = 3535, AArch64_ST1Onev1d_POST = 3536, AArch64_ST1Onev2d = 3537, AArch64_ST1Onev2d_POST = 3538, AArch64_ST1Onev2s = 3539, AArch64_ST1Onev2s_POST = 3540, AArch64_ST1Onev4h = 3541, AArch64_ST1Onev4h_POST = 3542, AArch64_ST1Onev4s = 3543, AArch64_ST1Onev4s_POST = 3544, AArch64_ST1Onev8b = 3545, AArch64_ST1Onev8b_POST = 3546, AArch64_ST1Onev8h = 3547, AArch64_ST1Onev8h_POST = 3548, AArch64_ST1Threev16b = 3549, AArch64_ST1Threev16b_POST = 3550, AArch64_ST1Threev1d = 3551, AArch64_ST1Threev1d_POST = 3552, AArch64_ST1Threev2d = 3553, AArch64_ST1Threev2d_POST = 3554, AArch64_ST1Threev2s = 3555, AArch64_ST1Threev2s_POST = 3556, AArch64_ST1Threev4h = 3557, AArch64_ST1Threev4h_POST = 3558, AArch64_ST1Threev4s = 3559, AArch64_ST1Threev4s_POST = 3560, AArch64_ST1Threev8b = 3561, AArch64_ST1Threev8b_POST = 3562, AArch64_ST1Threev8h = 3563, AArch64_ST1Threev8h_POST = 3564, AArch64_ST1Twov16b = 3565, AArch64_ST1Twov16b_POST = 3566, AArch64_ST1Twov1d = 3567, AArch64_ST1Twov1d_POST = 3568, AArch64_ST1Twov2d = 3569, AArch64_ST1Twov2d_POST = 3570, AArch64_ST1Twov2s = 3571, AArch64_ST1Twov2s_POST = 3572, AArch64_ST1Twov4h = 3573, AArch64_ST1Twov4h_POST = 3574, AArch64_ST1Twov4s = 3575, AArch64_ST1Twov4s_POST = 3576, AArch64_ST1Twov8b = 3577, AArch64_ST1Twov8b_POST = 3578, AArch64_ST1Twov8h = 3579, AArch64_ST1Twov8h_POST = 3580, AArch64_ST1W = 3581, AArch64_ST1W_D = 3582, AArch64_ST1W_D_IMM = 3583, AArch64_ST1W_IMM = 3584, AArch64_ST1i16 = 3585, AArch64_ST1i16_POST = 3586, AArch64_ST1i32 = 3587, AArch64_ST1i32_POST = 3588, AArch64_ST1i64 = 3589, AArch64_ST1i64_POST = 3590, AArch64_ST1i8 = 3591, AArch64_ST1i8_POST = 3592, AArch64_ST2B = 3593, AArch64_ST2B_IMM = 3594, AArch64_ST2D = 3595, AArch64_ST2D_IMM = 3596, AArch64_ST2H = 3597, AArch64_ST2H_IMM = 3598, AArch64_ST2Twov16b = 3599, AArch64_ST2Twov16b_POST = 3600, AArch64_ST2Twov2d = 3601, AArch64_ST2Twov2d_POST = 3602, AArch64_ST2Twov2s = 3603, AArch64_ST2Twov2s_POST = 3604, AArch64_ST2Twov4h = 3605, AArch64_ST2Twov4h_POST = 3606, AArch64_ST2Twov4s = 3607, AArch64_ST2Twov4s_POST = 3608, AArch64_ST2Twov8b = 3609, AArch64_ST2Twov8b_POST = 3610, AArch64_ST2Twov8h = 3611, AArch64_ST2Twov8h_POST = 3612, AArch64_ST2W = 3613, AArch64_ST2W_IMM = 3614, AArch64_ST2i16 = 3615, AArch64_ST2i16_POST = 3616, AArch64_ST2i32 = 3617, AArch64_ST2i32_POST = 3618, AArch64_ST2i64 = 3619, AArch64_ST2i64_POST = 3620, AArch64_ST2i8 = 3621, AArch64_ST2i8_POST = 3622, AArch64_ST3B = 3623, AArch64_ST3B_IMM = 3624, AArch64_ST3D = 3625, AArch64_ST3D_IMM = 3626, AArch64_ST3H = 3627, AArch64_ST3H_IMM = 3628, AArch64_ST3Threev16b = 3629, AArch64_ST3Threev16b_POST = 3630, AArch64_ST3Threev2d = 3631, AArch64_ST3Threev2d_POST = 3632, AArch64_ST3Threev2s = 3633, AArch64_ST3Threev2s_POST = 3634, AArch64_ST3Threev4h = 3635, AArch64_ST3Threev4h_POST = 3636, AArch64_ST3Threev4s = 3637, AArch64_ST3Threev4s_POST = 3638, AArch64_ST3Threev8b = 3639, AArch64_ST3Threev8b_POST = 3640, AArch64_ST3Threev8h = 3641, AArch64_ST3Threev8h_POST = 3642, AArch64_ST3W = 3643, AArch64_ST3W_IMM = 3644, AArch64_ST3i16 = 3645, AArch64_ST3i16_POST = 3646, AArch64_ST3i32 = 3647, AArch64_ST3i32_POST = 3648, AArch64_ST3i64 = 3649, AArch64_ST3i64_POST = 3650, AArch64_ST3i8 = 3651, AArch64_ST3i8_POST = 3652, AArch64_ST4B = 3653, AArch64_ST4B_IMM = 3654, AArch64_ST4D = 3655, AArch64_ST4D_IMM = 3656, AArch64_ST4Fourv16b = 3657, AArch64_ST4Fourv16b_POST = 3658, AArch64_ST4Fourv2d = 3659, AArch64_ST4Fourv2d_POST = 3660, AArch64_ST4Fourv2s = 3661, AArch64_ST4Fourv2s_POST = 3662, AArch64_ST4Fourv4h = 3663, AArch64_ST4Fourv4h_POST = 3664, AArch64_ST4Fourv4s = 3665, AArch64_ST4Fourv4s_POST = 3666, AArch64_ST4Fourv8b = 3667, AArch64_ST4Fourv8b_POST = 3668, AArch64_ST4Fourv8h = 3669, AArch64_ST4Fourv8h_POST = 3670, AArch64_ST4H = 3671, AArch64_ST4H_IMM = 3672, AArch64_ST4W = 3673, AArch64_ST4W_IMM = 3674, AArch64_ST4i16 = 3675, AArch64_ST4i16_POST = 3676, AArch64_ST4i32 = 3677, AArch64_ST4i32_POST = 3678, AArch64_ST4i64 = 3679, AArch64_ST4i64_POST = 3680, AArch64_ST4i8 = 3681, AArch64_ST4i8_POST = 3682, AArch64_STLLRB = 3683, AArch64_STLLRH = 3684, AArch64_STLLRW = 3685, AArch64_STLLRX = 3686, AArch64_STLRB = 3687, AArch64_STLRH = 3688, AArch64_STLRW = 3689, AArch64_STLRX = 3690, AArch64_STLURBi = 3691, AArch64_STLURHi = 3692, AArch64_STLURWi = 3693, AArch64_STLURXi = 3694, AArch64_STLXPW = 3695, AArch64_STLXPX = 3696, AArch64_STLXRB = 3697, AArch64_STLXRH = 3698, AArch64_STLXRW = 3699, AArch64_STLXRX = 3700, AArch64_STNPDi = 3701, AArch64_STNPQi = 3702, AArch64_STNPSi = 3703, AArch64_STNPWi = 3704, AArch64_STNPXi = 3705, AArch64_STNT1B_ZRI = 3706, AArch64_STNT1B_ZRR = 3707, AArch64_STNT1D_ZRI = 3708, AArch64_STNT1D_ZRR = 3709, AArch64_STNT1H_ZRI = 3710, AArch64_STNT1H_ZRR = 3711, AArch64_STNT1W_ZRI = 3712, AArch64_STNT1W_ZRR = 3713, AArch64_STPDi = 3714, AArch64_STPDpost = 3715, AArch64_STPDpre = 3716, AArch64_STPQi = 3717, AArch64_STPQpost = 3718, AArch64_STPQpre = 3719, AArch64_STPSi = 3720, AArch64_STPSpost = 3721, AArch64_STPSpre = 3722, AArch64_STPWi = 3723, AArch64_STPWpost = 3724, AArch64_STPWpre = 3725, AArch64_STPXi = 3726, AArch64_STPXpost = 3727, AArch64_STPXpre = 3728, AArch64_STRBBpost = 3729, AArch64_STRBBpre = 3730, AArch64_STRBBroW = 3731, AArch64_STRBBroX = 3732, AArch64_STRBBui = 3733, AArch64_STRBpost = 3734, AArch64_STRBpre = 3735, AArch64_STRBroW = 3736, AArch64_STRBroX = 3737, AArch64_STRBui = 3738, AArch64_STRDpost = 3739, AArch64_STRDpre = 3740, AArch64_STRDroW = 3741, AArch64_STRDroX = 3742, AArch64_STRDui = 3743, AArch64_STRHHpost = 3744, AArch64_STRHHpre = 3745, AArch64_STRHHroW = 3746, AArch64_STRHHroX = 3747, AArch64_STRHHui = 3748, AArch64_STRHpost = 3749, AArch64_STRHpre = 3750, AArch64_STRHroW = 3751, AArch64_STRHroX = 3752, AArch64_STRHui = 3753, AArch64_STRQpost = 3754, AArch64_STRQpre = 3755, AArch64_STRQroW = 3756, AArch64_STRQroX = 3757, AArch64_STRQui = 3758, AArch64_STRSpost = 3759, AArch64_STRSpre = 3760, AArch64_STRSroW = 3761, AArch64_STRSroX = 3762, AArch64_STRSui = 3763, AArch64_STRWpost = 3764, AArch64_STRWpre = 3765, AArch64_STRWroW = 3766, AArch64_STRWroX = 3767, AArch64_STRWui = 3768, AArch64_STRXpost = 3769, AArch64_STRXpre = 3770, AArch64_STRXroW = 3771, AArch64_STRXroX = 3772, AArch64_STRXui = 3773, AArch64_STR_PXI = 3774, AArch64_STR_ZXI = 3775, AArch64_STTRBi = 3776, AArch64_STTRHi = 3777, AArch64_STTRWi = 3778, AArch64_STTRXi = 3779, AArch64_STURBBi = 3780, AArch64_STURBi = 3781, AArch64_STURDi = 3782, AArch64_STURHHi = 3783, AArch64_STURHi = 3784, AArch64_STURQi = 3785, AArch64_STURSi = 3786, AArch64_STURWi = 3787, AArch64_STURXi = 3788, AArch64_STXPW = 3789, AArch64_STXPX = 3790, AArch64_STXRB = 3791, AArch64_STXRH = 3792, AArch64_STXRW = 3793, AArch64_STXRX = 3794, AArch64_SUBHNv2i64_v2i32 = 3795, AArch64_SUBHNv2i64_v4i32 = 3796, AArch64_SUBHNv4i32_v4i16 = 3797, AArch64_SUBHNv4i32_v8i16 = 3798, AArch64_SUBHNv8i16_v16i8 = 3799, AArch64_SUBHNv8i16_v8i8 = 3800, AArch64_SUBR_ZI_B = 3801, AArch64_SUBR_ZI_D = 3802, AArch64_SUBR_ZI_H = 3803, AArch64_SUBR_ZI_S = 3804, AArch64_SUBR_ZPmZ_B = 3805, AArch64_SUBR_ZPmZ_D = 3806, AArch64_SUBR_ZPmZ_H = 3807, AArch64_SUBR_ZPmZ_S = 3808, AArch64_SUBSWri = 3809, AArch64_SUBSWrr = 3810, AArch64_SUBSWrs = 3811, AArch64_SUBSWrx = 3812, AArch64_SUBSXri = 3813, AArch64_SUBSXrr = 3814, AArch64_SUBSXrs = 3815, AArch64_SUBSXrx = 3816, AArch64_SUBSXrx64 = 3817, AArch64_SUBWri = 3818, AArch64_SUBWrr = 3819, AArch64_SUBWrs = 3820, AArch64_SUBWrx = 3821, AArch64_SUBXri = 3822, AArch64_SUBXrr = 3823, AArch64_SUBXrs = 3824, AArch64_SUBXrx = 3825, AArch64_SUBXrx64 = 3826, AArch64_SUB_ZI_B = 3827, AArch64_SUB_ZI_D = 3828, AArch64_SUB_ZI_H = 3829, AArch64_SUB_ZI_S = 3830, AArch64_SUB_ZPmZ_B = 3831, AArch64_SUB_ZPmZ_D = 3832, AArch64_SUB_ZPmZ_H = 3833, AArch64_SUB_ZPmZ_S = 3834, AArch64_SUB_ZZZ_B = 3835, AArch64_SUB_ZZZ_D = 3836, AArch64_SUB_ZZZ_H = 3837, AArch64_SUB_ZZZ_S = 3838, AArch64_SUBv16i8 = 3839, AArch64_SUBv1i64 = 3840, AArch64_SUBv2i32 = 3841, AArch64_SUBv2i64 = 3842, AArch64_SUBv4i16 = 3843, AArch64_SUBv4i32 = 3844, AArch64_SUBv8i16 = 3845, AArch64_SUBv8i8 = 3846, AArch64_SUNPKHI_ZZ_D = 3847, AArch64_SUNPKHI_ZZ_H = 3848, AArch64_SUNPKHI_ZZ_S = 3849, AArch64_SUNPKLO_ZZ_D = 3850, AArch64_SUNPKLO_ZZ_H = 3851, AArch64_SUNPKLO_ZZ_S = 3852, AArch64_SUQADDv16i8 = 3853, AArch64_SUQADDv1i16 = 3854, AArch64_SUQADDv1i32 = 3855, AArch64_SUQADDv1i64 = 3856, AArch64_SUQADDv1i8 = 3857, AArch64_SUQADDv2i32 = 3858, AArch64_SUQADDv2i64 = 3859, AArch64_SUQADDv4i16 = 3860, AArch64_SUQADDv4i32 = 3861, AArch64_SUQADDv8i16 = 3862, AArch64_SUQADDv8i8 = 3863, AArch64_SVC = 3864, AArch64_SWPAB = 3865, AArch64_SWPAH = 3866, AArch64_SWPALB = 3867, AArch64_SWPALH = 3868, AArch64_SWPALW = 3869, AArch64_SWPALX = 3870, AArch64_SWPAW = 3871, AArch64_SWPAX = 3872, AArch64_SWPB = 3873, AArch64_SWPH = 3874, AArch64_SWPLB = 3875, AArch64_SWPLH = 3876, AArch64_SWPLW = 3877, AArch64_SWPLX = 3878, AArch64_SWPW = 3879, AArch64_SWPX = 3880, AArch64_SXTB_ZPmZ_D = 3881, AArch64_SXTB_ZPmZ_H = 3882, AArch64_SXTB_ZPmZ_S = 3883, AArch64_SXTH_ZPmZ_D = 3884, AArch64_SXTH_ZPmZ_S = 3885, AArch64_SXTW_ZPmZ_D = 3886, AArch64_SYSLxt = 3887, AArch64_SYSxt = 3888, AArch64_TBL_ZZZ_B = 3889, AArch64_TBL_ZZZ_D = 3890, AArch64_TBL_ZZZ_H = 3891, AArch64_TBL_ZZZ_S = 3892, AArch64_TBLv16i8Four = 3893, AArch64_TBLv16i8One = 3894, AArch64_TBLv16i8Three = 3895, AArch64_TBLv16i8Two = 3896, AArch64_TBLv8i8Four = 3897, AArch64_TBLv8i8One = 3898, AArch64_TBLv8i8Three = 3899, AArch64_TBLv8i8Two = 3900, AArch64_TBNZW = 3901, AArch64_TBNZX = 3902, AArch64_TBXv16i8Four = 3903, AArch64_TBXv16i8One = 3904, AArch64_TBXv16i8Three = 3905, AArch64_TBXv16i8Two = 3906, AArch64_TBXv8i8Four = 3907, AArch64_TBXv8i8One = 3908, AArch64_TBXv8i8Three = 3909, AArch64_TBXv8i8Two = 3910, AArch64_TBZW = 3911, AArch64_TBZX = 3912, AArch64_TCRETURNdi = 3913, AArch64_TCRETURNri = 3914, AArch64_TLSDESCCALL = 3915, AArch64_TLSDESC_CALLSEQ = 3916, AArch64_TRN1_PPP_B = 3917, AArch64_TRN1_PPP_D = 3918, AArch64_TRN1_PPP_H = 3919, AArch64_TRN1_PPP_S = 3920, AArch64_TRN1_ZZZ_B = 3921, AArch64_TRN1_ZZZ_D = 3922, AArch64_TRN1_ZZZ_H = 3923, AArch64_TRN1_ZZZ_S = 3924, AArch64_TRN1v16i8 = 3925, AArch64_TRN1v2i32 = 3926, AArch64_TRN1v2i64 = 3927, AArch64_TRN1v4i16 = 3928, AArch64_TRN1v4i32 = 3929, AArch64_TRN1v8i16 = 3930, AArch64_TRN1v8i8 = 3931, AArch64_TRN2_PPP_B = 3932, AArch64_TRN2_PPP_D = 3933, AArch64_TRN2_PPP_H = 3934, AArch64_TRN2_PPP_S = 3935, AArch64_TRN2_ZZZ_B = 3936, AArch64_TRN2_ZZZ_D = 3937, AArch64_TRN2_ZZZ_H = 3938, AArch64_TRN2_ZZZ_S = 3939, AArch64_TRN2v16i8 = 3940, AArch64_TRN2v2i32 = 3941, AArch64_TRN2v2i64 = 3942, AArch64_TRN2v4i16 = 3943, AArch64_TRN2v4i32 = 3944, AArch64_TRN2v8i16 = 3945, AArch64_TRN2v8i8 = 3946, AArch64_TSB = 3947, AArch64_UABALv16i8_v8i16 = 3948, AArch64_UABALv2i32_v2i64 = 3949, AArch64_UABALv4i16_v4i32 = 3950, AArch64_UABALv4i32_v2i64 = 3951, AArch64_UABALv8i16_v4i32 = 3952, AArch64_UABALv8i8_v8i16 = 3953, AArch64_UABAv16i8 = 3954, AArch64_UABAv2i32 = 3955, AArch64_UABAv4i16 = 3956, AArch64_UABAv4i32 = 3957, AArch64_UABAv8i16 = 3958, AArch64_UABAv8i8 = 3959, AArch64_UABDLv16i8_v8i16 = 3960, AArch64_UABDLv2i32_v2i64 = 3961, AArch64_UABDLv4i16_v4i32 = 3962, AArch64_UABDLv4i32_v2i64 = 3963, AArch64_UABDLv8i16_v4i32 = 3964, AArch64_UABDLv8i8_v8i16 = 3965, AArch64_UABD_ZPmZ_B = 3966, AArch64_UABD_ZPmZ_D = 3967, AArch64_UABD_ZPmZ_H = 3968, AArch64_UABD_ZPmZ_S = 3969, AArch64_UABDv16i8 = 3970, AArch64_UABDv2i32 = 3971, AArch64_UABDv4i16 = 3972, AArch64_UABDv4i32 = 3973, AArch64_UABDv8i16 = 3974, AArch64_UABDv8i8 = 3975, AArch64_UADALPv16i8_v8i16 = 3976, AArch64_UADALPv2i32_v1i64 = 3977, AArch64_UADALPv4i16_v2i32 = 3978, AArch64_UADALPv4i32_v2i64 = 3979, AArch64_UADALPv8i16_v4i32 = 3980, AArch64_UADALPv8i8_v4i16 = 3981, AArch64_UADDLPv16i8_v8i16 = 3982, AArch64_UADDLPv2i32_v1i64 = 3983, AArch64_UADDLPv4i16_v2i32 = 3984, AArch64_UADDLPv4i32_v2i64 = 3985, AArch64_UADDLPv8i16_v4i32 = 3986, AArch64_UADDLPv8i8_v4i16 = 3987, AArch64_UADDLVv16i8v = 3988, AArch64_UADDLVv4i16v = 3989, AArch64_UADDLVv4i32v = 3990, AArch64_UADDLVv8i16v = 3991, AArch64_UADDLVv8i8v = 3992, AArch64_UADDLv16i8_v8i16 = 3993, AArch64_UADDLv2i32_v2i64 = 3994, AArch64_UADDLv4i16_v4i32 = 3995, AArch64_UADDLv4i32_v2i64 = 3996, AArch64_UADDLv8i16_v4i32 = 3997, AArch64_UADDLv8i8_v8i16 = 3998, AArch64_UADDV_VPZ_B = 3999, AArch64_UADDV_VPZ_D = 4000, AArch64_UADDV_VPZ_H = 4001, AArch64_UADDV_VPZ_S = 4002, AArch64_UADDWv16i8_v8i16 = 4003, AArch64_UADDWv2i32_v2i64 = 4004, AArch64_UADDWv4i16_v4i32 = 4005, AArch64_UADDWv4i32_v2i64 = 4006, AArch64_UADDWv8i16_v4i32 = 4007, AArch64_UADDWv8i8_v8i16 = 4008, AArch64_UBFMWri = 4009, AArch64_UBFMXri = 4010, AArch64_UCVTFSWDri = 4011, AArch64_UCVTFSWHri = 4012, AArch64_UCVTFSWSri = 4013, AArch64_UCVTFSXDri = 4014, AArch64_UCVTFSXHri = 4015, AArch64_UCVTFSXSri = 4016, AArch64_UCVTFUWDri = 4017, AArch64_UCVTFUWHri = 4018, AArch64_UCVTFUWSri = 4019, AArch64_UCVTFUXDri = 4020, AArch64_UCVTFUXHri = 4021, AArch64_UCVTFUXSri = 4022, AArch64_UCVTF_ZPmZ_DtoD = 4023, AArch64_UCVTF_ZPmZ_DtoH = 4024, AArch64_UCVTF_ZPmZ_DtoS = 4025, AArch64_UCVTF_ZPmZ_HtoH = 4026, AArch64_UCVTF_ZPmZ_StoD = 4027, AArch64_UCVTF_ZPmZ_StoH = 4028, AArch64_UCVTF_ZPmZ_StoS = 4029, AArch64_UCVTFd = 4030, AArch64_UCVTFh = 4031, AArch64_UCVTFs = 4032, AArch64_UCVTFv1i16 = 4033, AArch64_UCVTFv1i32 = 4034, AArch64_UCVTFv1i64 = 4035, AArch64_UCVTFv2f32 = 4036, AArch64_UCVTFv2f64 = 4037, AArch64_UCVTFv2i32_shift = 4038, AArch64_UCVTFv2i64_shift = 4039, AArch64_UCVTFv4f16 = 4040, AArch64_UCVTFv4f32 = 4041, AArch64_UCVTFv4i16_shift = 4042, AArch64_UCVTFv4i32_shift = 4043, AArch64_UCVTFv8f16 = 4044, AArch64_UCVTFv8i16_shift = 4045, AArch64_UDIVR_ZPmZ_D = 4046, AArch64_UDIVR_ZPmZ_S = 4047, AArch64_UDIVWr = 4048, AArch64_UDIVXr = 4049, AArch64_UDIV_ZPmZ_D = 4050, AArch64_UDIV_ZPmZ_S = 4051, AArch64_UDOT_ZZZI_D = 4052, AArch64_UDOT_ZZZI_S = 4053, AArch64_UDOT_ZZZ_D = 4054, AArch64_UDOT_ZZZ_S = 4055, AArch64_UDOTlanev16i8 = 4056, AArch64_UDOTlanev8i8 = 4057, AArch64_UDOTv16i8 = 4058, AArch64_UDOTv8i8 = 4059, AArch64_UHADDv16i8 = 4060, AArch64_UHADDv2i32 = 4061, AArch64_UHADDv4i16 = 4062, AArch64_UHADDv4i32 = 4063, AArch64_UHADDv8i16 = 4064, AArch64_UHADDv8i8 = 4065, AArch64_UHSUBv16i8 = 4066, AArch64_UHSUBv2i32 = 4067, AArch64_UHSUBv4i16 = 4068, AArch64_UHSUBv4i32 = 4069, AArch64_UHSUBv8i16 = 4070, AArch64_UHSUBv8i8 = 4071, AArch64_UMADDLrrr = 4072, AArch64_UMAXPv16i8 = 4073, AArch64_UMAXPv2i32 = 4074, AArch64_UMAXPv4i16 = 4075, AArch64_UMAXPv4i32 = 4076, AArch64_UMAXPv8i16 = 4077, AArch64_UMAXPv8i8 = 4078, AArch64_UMAXV_VPZ_B = 4079, AArch64_UMAXV_VPZ_D = 4080, AArch64_UMAXV_VPZ_H = 4081, AArch64_UMAXV_VPZ_S = 4082, AArch64_UMAXVv16i8v = 4083, AArch64_UMAXVv4i16v = 4084, AArch64_UMAXVv4i32v = 4085, AArch64_UMAXVv8i16v = 4086, AArch64_UMAXVv8i8v = 4087, AArch64_UMAX_ZI_B = 4088, AArch64_UMAX_ZI_D = 4089, AArch64_UMAX_ZI_H = 4090, AArch64_UMAX_ZI_S = 4091, AArch64_UMAX_ZPmZ_B = 4092, AArch64_UMAX_ZPmZ_D = 4093, AArch64_UMAX_ZPmZ_H = 4094, AArch64_UMAX_ZPmZ_S = 4095, AArch64_UMAXv16i8 = 4096, AArch64_UMAXv2i32 = 4097, AArch64_UMAXv4i16 = 4098, AArch64_UMAXv4i32 = 4099, AArch64_UMAXv8i16 = 4100, AArch64_UMAXv8i8 = 4101, AArch64_UMINPv16i8 = 4102, AArch64_UMINPv2i32 = 4103, AArch64_UMINPv4i16 = 4104, AArch64_UMINPv4i32 = 4105, AArch64_UMINPv8i16 = 4106, AArch64_UMINPv8i8 = 4107, AArch64_UMINV_VPZ_B = 4108, AArch64_UMINV_VPZ_D = 4109, AArch64_UMINV_VPZ_H = 4110, AArch64_UMINV_VPZ_S = 4111, AArch64_UMINVv16i8v = 4112, AArch64_UMINVv4i16v = 4113, AArch64_UMINVv4i32v = 4114, AArch64_UMINVv8i16v = 4115, AArch64_UMINVv8i8v = 4116, AArch64_UMIN_ZI_B = 4117, AArch64_UMIN_ZI_D = 4118, AArch64_UMIN_ZI_H = 4119, AArch64_UMIN_ZI_S = 4120, AArch64_UMIN_ZPmZ_B = 4121, AArch64_UMIN_ZPmZ_D = 4122, AArch64_UMIN_ZPmZ_H = 4123, AArch64_UMIN_ZPmZ_S = 4124, AArch64_UMINv16i8 = 4125, AArch64_UMINv2i32 = 4126, AArch64_UMINv4i16 = 4127, AArch64_UMINv4i32 = 4128, AArch64_UMINv8i16 = 4129, AArch64_UMINv8i8 = 4130, AArch64_UMLALv16i8_v8i16 = 4131, AArch64_UMLALv2i32_indexed = 4132, AArch64_UMLALv2i32_v2i64 = 4133, AArch64_UMLALv4i16_indexed = 4134, AArch64_UMLALv4i16_v4i32 = 4135, AArch64_UMLALv4i32_indexed = 4136, AArch64_UMLALv4i32_v2i64 = 4137, AArch64_UMLALv8i16_indexed = 4138, AArch64_UMLALv8i16_v4i32 = 4139, AArch64_UMLALv8i8_v8i16 = 4140, AArch64_UMLSLv16i8_v8i16 = 4141, AArch64_UMLSLv2i32_indexed = 4142, AArch64_UMLSLv2i32_v2i64 = 4143, AArch64_UMLSLv4i16_indexed = 4144, AArch64_UMLSLv4i16_v4i32 = 4145, AArch64_UMLSLv4i32_indexed = 4146, AArch64_UMLSLv4i32_v2i64 = 4147, AArch64_UMLSLv8i16_indexed = 4148, AArch64_UMLSLv8i16_v4i32 = 4149, AArch64_UMLSLv8i8_v8i16 = 4150, AArch64_UMOVvi16 = 4151, AArch64_UMOVvi32 = 4152, AArch64_UMOVvi64 = 4153, AArch64_UMOVvi8 = 4154, AArch64_UMSUBLrrr = 4155, AArch64_UMULH_ZPmZ_B = 4156, AArch64_UMULH_ZPmZ_D = 4157, AArch64_UMULH_ZPmZ_H = 4158, AArch64_UMULH_ZPmZ_S = 4159, AArch64_UMULHrr = 4160, AArch64_UMULLv16i8_v8i16 = 4161, AArch64_UMULLv2i32_indexed = 4162, AArch64_UMULLv2i32_v2i64 = 4163, AArch64_UMULLv4i16_indexed = 4164, AArch64_UMULLv4i16_v4i32 = 4165, AArch64_UMULLv4i32_indexed = 4166, AArch64_UMULLv4i32_v2i64 = 4167, AArch64_UMULLv8i16_indexed = 4168, AArch64_UMULLv8i16_v4i32 = 4169, AArch64_UMULLv8i8_v8i16 = 4170, AArch64_UQADD_ZI_B = 4171, AArch64_UQADD_ZI_D = 4172, AArch64_UQADD_ZI_H = 4173, AArch64_UQADD_ZI_S = 4174, AArch64_UQADD_ZZZ_B = 4175, AArch64_UQADD_ZZZ_D = 4176, AArch64_UQADD_ZZZ_H = 4177, AArch64_UQADD_ZZZ_S = 4178, AArch64_UQADDv16i8 = 4179, AArch64_UQADDv1i16 = 4180, AArch64_UQADDv1i32 = 4181, AArch64_UQADDv1i64 = 4182, AArch64_UQADDv1i8 = 4183, AArch64_UQADDv2i32 = 4184, AArch64_UQADDv2i64 = 4185, AArch64_UQADDv4i16 = 4186, AArch64_UQADDv4i32 = 4187, AArch64_UQADDv8i16 = 4188, AArch64_UQADDv8i8 = 4189, AArch64_UQDECB_WPiI = 4190, AArch64_UQDECB_XPiI = 4191, AArch64_UQDECD_WPiI = 4192, AArch64_UQDECD_XPiI = 4193, AArch64_UQDECD_ZPiI = 4194, AArch64_UQDECH_WPiI = 4195, AArch64_UQDECH_XPiI = 4196, AArch64_UQDECH_ZPiI = 4197, AArch64_UQDECP_WP_B = 4198, AArch64_UQDECP_WP_D = 4199, AArch64_UQDECP_WP_H = 4200, AArch64_UQDECP_WP_S = 4201, AArch64_UQDECP_XP_B = 4202, AArch64_UQDECP_XP_D = 4203, AArch64_UQDECP_XP_H = 4204, AArch64_UQDECP_XP_S = 4205, AArch64_UQDECP_ZP_D = 4206, AArch64_UQDECP_ZP_H = 4207, AArch64_UQDECP_ZP_S = 4208, AArch64_UQDECW_WPiI = 4209, AArch64_UQDECW_XPiI = 4210, AArch64_UQDECW_ZPiI = 4211, AArch64_UQINCB_WPiI = 4212, AArch64_UQINCB_XPiI = 4213, AArch64_UQINCD_WPiI = 4214, AArch64_UQINCD_XPiI = 4215, AArch64_UQINCD_ZPiI = 4216, AArch64_UQINCH_WPiI = 4217, AArch64_UQINCH_XPiI = 4218, AArch64_UQINCH_ZPiI = 4219, AArch64_UQINCP_WP_B = 4220, AArch64_UQINCP_WP_D = 4221, AArch64_UQINCP_WP_H = 4222, AArch64_UQINCP_WP_S = 4223, AArch64_UQINCP_XP_B = 4224, AArch64_UQINCP_XP_D = 4225, AArch64_UQINCP_XP_H = 4226, AArch64_UQINCP_XP_S = 4227, AArch64_UQINCP_ZP_D = 4228, AArch64_UQINCP_ZP_H = 4229, AArch64_UQINCP_ZP_S = 4230, AArch64_UQINCW_WPiI = 4231, AArch64_UQINCW_XPiI = 4232, AArch64_UQINCW_ZPiI = 4233, AArch64_UQRSHLv16i8 = 4234, AArch64_UQRSHLv1i16 = 4235, AArch64_UQRSHLv1i32 = 4236, AArch64_UQRSHLv1i64 = 4237, AArch64_UQRSHLv1i8 = 4238, AArch64_UQRSHLv2i32 = 4239, AArch64_UQRSHLv2i64 = 4240, AArch64_UQRSHLv4i16 = 4241, AArch64_UQRSHLv4i32 = 4242, AArch64_UQRSHLv8i16 = 4243, AArch64_UQRSHLv8i8 = 4244, AArch64_UQRSHRNb = 4245, AArch64_UQRSHRNh = 4246, AArch64_UQRSHRNs = 4247, AArch64_UQRSHRNv16i8_shift = 4248, AArch64_UQRSHRNv2i32_shift = 4249, AArch64_UQRSHRNv4i16_shift = 4250, AArch64_UQRSHRNv4i32_shift = 4251, AArch64_UQRSHRNv8i16_shift = 4252, AArch64_UQRSHRNv8i8_shift = 4253, AArch64_UQSHLb = 4254, AArch64_UQSHLd = 4255, AArch64_UQSHLh = 4256, AArch64_UQSHLs = 4257, AArch64_UQSHLv16i8 = 4258, AArch64_UQSHLv16i8_shift = 4259, AArch64_UQSHLv1i16 = 4260, AArch64_UQSHLv1i32 = 4261, AArch64_UQSHLv1i64 = 4262, AArch64_UQSHLv1i8 = 4263, AArch64_UQSHLv2i32 = 4264, AArch64_UQSHLv2i32_shift = 4265, AArch64_UQSHLv2i64 = 4266, AArch64_UQSHLv2i64_shift = 4267, AArch64_UQSHLv4i16 = 4268, AArch64_UQSHLv4i16_shift = 4269, AArch64_UQSHLv4i32 = 4270, AArch64_UQSHLv4i32_shift = 4271, AArch64_UQSHLv8i16 = 4272, AArch64_UQSHLv8i16_shift = 4273, AArch64_UQSHLv8i8 = 4274, AArch64_UQSHLv8i8_shift = 4275, AArch64_UQSHRNb = 4276, AArch64_UQSHRNh = 4277, AArch64_UQSHRNs = 4278, AArch64_UQSHRNv16i8_shift = 4279, AArch64_UQSHRNv2i32_shift = 4280, AArch64_UQSHRNv4i16_shift = 4281, AArch64_UQSHRNv4i32_shift = 4282, AArch64_UQSHRNv8i16_shift = 4283, AArch64_UQSHRNv8i8_shift = 4284, AArch64_UQSUB_ZI_B = 4285, AArch64_UQSUB_ZI_D = 4286, AArch64_UQSUB_ZI_H = 4287, AArch64_UQSUB_ZI_S = 4288, AArch64_UQSUB_ZZZ_B = 4289, AArch64_UQSUB_ZZZ_D = 4290, AArch64_UQSUB_ZZZ_H = 4291, AArch64_UQSUB_ZZZ_S = 4292, AArch64_UQSUBv16i8 = 4293, AArch64_UQSUBv1i16 = 4294, AArch64_UQSUBv1i32 = 4295, AArch64_UQSUBv1i64 = 4296, AArch64_UQSUBv1i8 = 4297, AArch64_UQSUBv2i32 = 4298, AArch64_UQSUBv2i64 = 4299, AArch64_UQSUBv4i16 = 4300, AArch64_UQSUBv4i32 = 4301, AArch64_UQSUBv8i16 = 4302, AArch64_UQSUBv8i8 = 4303, AArch64_UQXTNv16i8 = 4304, AArch64_UQXTNv1i16 = 4305, AArch64_UQXTNv1i32 = 4306, AArch64_UQXTNv1i8 = 4307, AArch64_UQXTNv2i32 = 4308, AArch64_UQXTNv4i16 = 4309, AArch64_UQXTNv4i32 = 4310, AArch64_UQXTNv8i16 = 4311, AArch64_UQXTNv8i8 = 4312, AArch64_URECPEv2i32 = 4313, AArch64_URECPEv4i32 = 4314, AArch64_URHADDv16i8 = 4315, AArch64_URHADDv2i32 = 4316, AArch64_URHADDv4i16 = 4317, AArch64_URHADDv4i32 = 4318, AArch64_URHADDv8i16 = 4319, AArch64_URHADDv8i8 = 4320, AArch64_URSHLv16i8 = 4321, AArch64_URSHLv1i64 = 4322, AArch64_URSHLv2i32 = 4323, AArch64_URSHLv2i64 = 4324, AArch64_URSHLv4i16 = 4325, AArch64_URSHLv4i32 = 4326, AArch64_URSHLv8i16 = 4327, AArch64_URSHLv8i8 = 4328, AArch64_URSHRd = 4329, AArch64_URSHRv16i8_shift = 4330, AArch64_URSHRv2i32_shift = 4331, AArch64_URSHRv2i64_shift = 4332, AArch64_URSHRv4i16_shift = 4333, AArch64_URSHRv4i32_shift = 4334, AArch64_URSHRv8i16_shift = 4335, AArch64_URSHRv8i8_shift = 4336, AArch64_URSQRTEv2i32 = 4337, AArch64_URSQRTEv4i32 = 4338, AArch64_URSRAd = 4339, AArch64_URSRAv16i8_shift = 4340, AArch64_URSRAv2i32_shift = 4341, AArch64_URSRAv2i64_shift = 4342, AArch64_URSRAv4i16_shift = 4343, AArch64_URSRAv4i32_shift = 4344, AArch64_URSRAv8i16_shift = 4345, AArch64_URSRAv8i8_shift = 4346, AArch64_USHLLv16i8_shift = 4347, AArch64_USHLLv2i32_shift = 4348, AArch64_USHLLv4i16_shift = 4349, AArch64_USHLLv4i32_shift = 4350, AArch64_USHLLv8i16_shift = 4351, AArch64_USHLLv8i8_shift = 4352, AArch64_USHLv16i8 = 4353, AArch64_USHLv1i64 = 4354, AArch64_USHLv2i32 = 4355, AArch64_USHLv2i64 = 4356, AArch64_USHLv4i16 = 4357, AArch64_USHLv4i32 = 4358, AArch64_USHLv8i16 = 4359, AArch64_USHLv8i8 = 4360, AArch64_USHRd = 4361, AArch64_USHRv16i8_shift = 4362, AArch64_USHRv2i32_shift = 4363, AArch64_USHRv2i64_shift = 4364, AArch64_USHRv4i16_shift = 4365, AArch64_USHRv4i32_shift = 4366, AArch64_USHRv8i16_shift = 4367, AArch64_USHRv8i8_shift = 4368, AArch64_USQADDv16i8 = 4369, AArch64_USQADDv1i16 = 4370, AArch64_USQADDv1i32 = 4371, AArch64_USQADDv1i64 = 4372, AArch64_USQADDv1i8 = 4373, AArch64_USQADDv2i32 = 4374, AArch64_USQADDv2i64 = 4375, AArch64_USQADDv4i16 = 4376, AArch64_USQADDv4i32 = 4377, AArch64_USQADDv8i16 = 4378, AArch64_USQADDv8i8 = 4379, AArch64_USRAd = 4380, AArch64_USRAv16i8_shift = 4381, AArch64_USRAv2i32_shift = 4382, AArch64_USRAv2i64_shift = 4383, AArch64_USRAv4i16_shift = 4384, AArch64_USRAv4i32_shift = 4385, AArch64_USRAv8i16_shift = 4386, AArch64_USRAv8i8_shift = 4387, AArch64_USUBLv16i8_v8i16 = 4388, AArch64_USUBLv2i32_v2i64 = 4389, AArch64_USUBLv4i16_v4i32 = 4390, AArch64_USUBLv4i32_v2i64 = 4391, AArch64_USUBLv8i16_v4i32 = 4392, AArch64_USUBLv8i8_v8i16 = 4393, AArch64_USUBWv16i8_v8i16 = 4394, AArch64_USUBWv2i32_v2i64 = 4395, AArch64_USUBWv4i16_v4i32 = 4396, AArch64_USUBWv4i32_v2i64 = 4397, AArch64_USUBWv8i16_v4i32 = 4398, AArch64_USUBWv8i8_v8i16 = 4399, AArch64_UUNPKHI_ZZ_D = 4400, AArch64_UUNPKHI_ZZ_H = 4401, AArch64_UUNPKHI_ZZ_S = 4402, AArch64_UUNPKLO_ZZ_D = 4403, AArch64_UUNPKLO_ZZ_H = 4404, AArch64_UUNPKLO_ZZ_S = 4405, AArch64_UXTB_ZPmZ_D = 4406, AArch64_UXTB_ZPmZ_H = 4407, AArch64_UXTB_ZPmZ_S = 4408, AArch64_UXTH_ZPmZ_D = 4409, AArch64_UXTH_ZPmZ_S = 4410, AArch64_UXTW_ZPmZ_D = 4411, AArch64_UZP1_PPP_B = 4412, AArch64_UZP1_PPP_D = 4413, AArch64_UZP1_PPP_H = 4414, AArch64_UZP1_PPP_S = 4415, AArch64_UZP1_ZZZ_B = 4416, AArch64_UZP1_ZZZ_D = 4417, AArch64_UZP1_ZZZ_H = 4418, AArch64_UZP1_ZZZ_S = 4419, AArch64_UZP1v16i8 = 4420, AArch64_UZP1v2i32 = 4421, AArch64_UZP1v2i64 = 4422, AArch64_UZP1v4i16 = 4423, AArch64_UZP1v4i32 = 4424, AArch64_UZP1v8i16 = 4425, AArch64_UZP1v8i8 = 4426, AArch64_UZP2_PPP_B = 4427, AArch64_UZP2_PPP_D = 4428, AArch64_UZP2_PPP_H = 4429, AArch64_UZP2_PPP_S = 4430, AArch64_UZP2_ZZZ_B = 4431, AArch64_UZP2_ZZZ_D = 4432, AArch64_UZP2_ZZZ_H = 4433, AArch64_UZP2_ZZZ_S = 4434, AArch64_UZP2v16i8 = 4435, AArch64_UZP2v2i32 = 4436, AArch64_UZP2v2i64 = 4437, AArch64_UZP2v4i16 = 4438, AArch64_UZP2v4i32 = 4439, AArch64_UZP2v8i16 = 4440, AArch64_UZP2v8i8 = 4441, AArch64_WHILELE_PWW_B = 4442, AArch64_WHILELE_PWW_D = 4443, AArch64_WHILELE_PWW_H = 4444, AArch64_WHILELE_PWW_S = 4445, AArch64_WHILELE_PXX_B = 4446, AArch64_WHILELE_PXX_D = 4447, AArch64_WHILELE_PXX_H = 4448, AArch64_WHILELE_PXX_S = 4449, AArch64_WHILELO_PWW_B = 4450, AArch64_WHILELO_PWW_D = 4451, AArch64_WHILELO_PWW_H = 4452, AArch64_WHILELO_PWW_S = 4453, AArch64_WHILELO_PXX_B = 4454, AArch64_WHILELO_PXX_D = 4455, AArch64_WHILELO_PXX_H = 4456, AArch64_WHILELO_PXX_S = 4457, AArch64_WHILELS_PWW_B = 4458, AArch64_WHILELS_PWW_D = 4459, AArch64_WHILELS_PWW_H = 4460, AArch64_WHILELS_PWW_S = 4461, AArch64_WHILELS_PXX_B = 4462, AArch64_WHILELS_PXX_D = 4463, AArch64_WHILELS_PXX_H = 4464, AArch64_WHILELS_PXX_S = 4465, AArch64_WHILELT_PWW_B = 4466, AArch64_WHILELT_PWW_D = 4467, AArch64_WHILELT_PWW_H = 4468, AArch64_WHILELT_PWW_S = 4469, AArch64_WHILELT_PXX_B = 4470, AArch64_WHILELT_PXX_D = 4471, AArch64_WHILELT_PXX_H = 4472, AArch64_WHILELT_PXX_S = 4473, AArch64_WRFFR = 4474, AArch64_XAR = 4475, AArch64_XPACD = 4476, AArch64_XPACI = 4477, AArch64_XPACLRI = 4478, AArch64_XTNv16i8 = 4479, AArch64_XTNv2i32 = 4480, AArch64_XTNv4i16 = 4481, AArch64_XTNv4i32 = 4482, AArch64_XTNv8i16 = 4483, AArch64_XTNv8i8 = 4484, AArch64_ZIP1_PPP_B = 4485, AArch64_ZIP1_PPP_D = 4486, AArch64_ZIP1_PPP_H = 4487, AArch64_ZIP1_PPP_S = 4488, AArch64_ZIP1_ZZZ_B = 4489, AArch64_ZIP1_ZZZ_D = 4490, AArch64_ZIP1_ZZZ_H = 4491, AArch64_ZIP1_ZZZ_S = 4492, AArch64_ZIP1v16i8 = 4493, AArch64_ZIP1v2i32 = 4494, AArch64_ZIP1v2i64 = 4495, AArch64_ZIP1v4i16 = 4496, AArch64_ZIP1v4i32 = 4497, AArch64_ZIP1v8i16 = 4498, AArch64_ZIP1v8i8 = 4499, AArch64_ZIP2_PPP_B = 4500, AArch64_ZIP2_PPP_D = 4501, AArch64_ZIP2_PPP_H = 4502, AArch64_ZIP2_PPP_S = 4503, AArch64_ZIP2_ZZZ_B = 4504, AArch64_ZIP2_ZZZ_D = 4505, AArch64_ZIP2_ZZZ_H = 4506, AArch64_ZIP2_ZZZ_S = 4507, AArch64_ZIP2v16i8 = 4508, AArch64_ZIP2v2i32 = 4509, AArch64_ZIP2v2i64 = 4510, AArch64_ZIP2v4i16 = 4511, AArch64_ZIP2v4i32 = 4512, AArch64_ZIP2v8i16 = 4513, AArch64_ZIP2v8i8 = 4514, AArch64_anonymous_1349 = 4515, AArch64_INSTRUCTION_LIST_END = 4516 }; #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC #define nullptr 0 static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { AArch64_NoRegister, AArch64_FFR = 1, AArch64_FP = 2, AArch64_LR = 3, AArch64_NZCV = 4, AArch64_SP = 5, AArch64_WSP = 6, AArch64_WZR = 7, AArch64_XZR = 8, AArch64_B0 = 9, AArch64_B1 = 10, AArch64_B2 = 11, AArch64_B3 = 12, AArch64_B4 = 13, AArch64_B5 = 14, AArch64_B6 = 15, AArch64_B7 = 16, AArch64_B8 = 17, AArch64_B9 = 18, AArch64_B10 = 19, AArch64_B11 = 20, AArch64_B12 = 21, AArch64_B13 = 22, AArch64_B14 = 23, AArch64_B15 = 24, AArch64_B16 = 25, AArch64_B17 = 26, AArch64_B18 = 27, AArch64_B19 = 28, AArch64_B20 = 29, AArch64_B21 = 30, AArch64_B22 = 31, AArch64_B23 = 32, AArch64_B24 = 33, AArch64_B25 = 34, AArch64_B26 = 35, AArch64_B27 = 36, AArch64_B28 = 37, AArch64_B29 = 38, AArch64_B30 = 39, AArch64_B31 = 40, AArch64_D0 = 41, AArch64_D1 = 42, AArch64_D2 = 43, AArch64_D3 = 44, AArch64_D4 = 45, AArch64_D5 = 46, AArch64_D6 = 47, AArch64_D7 = 48, AArch64_D8 = 49, AArch64_D9 = 50, AArch64_D10 = 51, AArch64_D11 = 52, AArch64_D12 = 53, AArch64_D13 = 54, AArch64_D14 = 55, AArch64_D15 = 56, AArch64_D16 = 57, AArch64_D17 = 58, AArch64_D18 = 59, AArch64_D19 = 60, AArch64_D20 = 61, AArch64_D21 = 62, AArch64_D22 = 63, AArch64_D23 = 64, AArch64_D24 = 65, AArch64_D25 = 66, AArch64_D26 = 67, AArch64_D27 = 68, AArch64_D28 = 69, AArch64_D29 = 70, AArch64_D30 = 71, AArch64_D31 = 72, AArch64_H0 = 73, AArch64_H1 = 74, AArch64_H2 = 75, AArch64_H3 = 76, AArch64_H4 = 77, AArch64_H5 = 78, AArch64_H6 = 79, AArch64_H7 = 80, AArch64_H8 = 81, AArch64_H9 = 82, AArch64_H10 = 83, AArch64_H11 = 84, AArch64_H12 = 85, AArch64_H13 = 86, AArch64_H14 = 87, AArch64_H15 = 88, AArch64_H16 = 89, AArch64_H17 = 90, AArch64_H18 = 91, AArch64_H19 = 92, AArch64_H20 = 93, AArch64_H21 = 94, AArch64_H22 = 95, AArch64_H23 = 96, AArch64_H24 = 97, AArch64_H25 = 98, AArch64_H26 = 99, AArch64_H27 = 100, AArch64_H28 = 101, AArch64_H29 = 102, AArch64_H30 = 103, AArch64_H31 = 104, AArch64_P0 = 105, AArch64_P1 = 106, AArch64_P2 = 107, AArch64_P3 = 108, AArch64_P4 = 109, AArch64_P5 = 110, AArch64_P6 = 111, AArch64_P7 = 112, AArch64_P8 = 113, AArch64_P9 = 114, AArch64_P10 = 115, AArch64_P11 = 116, AArch64_P12 = 117, AArch64_P13 = 118, AArch64_P14 = 119, AArch64_P15 = 120, AArch64_Q0 = 121, AArch64_Q1 = 122, AArch64_Q2 = 123, AArch64_Q3 = 124, AArch64_Q4 = 125, AArch64_Q5 = 126, AArch64_Q6 = 127, AArch64_Q7 = 128, AArch64_Q8 = 129, AArch64_Q9 = 130, AArch64_Q10 = 131, AArch64_Q11 = 132, AArch64_Q12 = 133, AArch64_Q13 = 134, AArch64_Q14 = 135, AArch64_Q15 = 136, AArch64_Q16 = 137, AArch64_Q17 = 138, AArch64_Q18 = 139, AArch64_Q19 = 140, AArch64_Q20 = 141, AArch64_Q21 = 142, AArch64_Q22 = 143, AArch64_Q23 = 144, AArch64_Q24 = 145, AArch64_Q25 = 146, AArch64_Q26 = 147, AArch64_Q27 = 148, AArch64_Q28 = 149, AArch64_Q29 = 150, AArch64_Q30 = 151, AArch64_Q31 = 152, AArch64_S0 = 153, AArch64_S1 = 154, AArch64_S2 = 155, AArch64_S3 = 156, AArch64_S4 = 157, AArch64_S5 = 158, AArch64_S6 = 159, AArch64_S7 = 160, AArch64_S8 = 161, AArch64_S9 = 162, AArch64_S10 = 163, AArch64_S11 = 164, AArch64_S12 = 165, AArch64_S13 = 166, AArch64_S14 = 167, AArch64_S15 = 168, AArch64_S16 = 169, AArch64_S17 = 170, AArch64_S18 = 171, AArch64_S19 = 172, AArch64_S20 = 173, AArch64_S21 = 174, AArch64_S22 = 175, AArch64_S23 = 176, AArch64_S24 = 177, AArch64_S25 = 178, AArch64_S26 = 179, AArch64_S27 = 180, AArch64_S28 = 181, AArch64_S29 = 182, AArch64_S30 = 183, AArch64_S31 = 184, AArch64_W0 = 185, AArch64_W1 = 186, AArch64_W2 = 187, AArch64_W3 = 188, AArch64_W4 = 189, AArch64_W5 = 190, AArch64_W6 = 191, AArch64_W7 = 192, AArch64_W8 = 193, AArch64_W9 = 194, AArch64_W10 = 195, AArch64_W11 = 196, AArch64_W12 = 197, AArch64_W13 = 198, AArch64_W14 = 199, AArch64_W15 = 200, AArch64_W16 = 201, AArch64_W17 = 202, AArch64_W18 = 203, AArch64_W19 = 204, AArch64_W20 = 205, AArch64_W21 = 206, AArch64_W22 = 207, AArch64_W23 = 208, AArch64_W24 = 209, AArch64_W25 = 210, AArch64_W26 = 211, AArch64_W27 = 212, AArch64_W28 = 213, AArch64_W29 = 214, AArch64_W30 = 215, AArch64_X0 = 216, AArch64_X1 = 217, AArch64_X2 = 218, AArch64_X3 = 219, AArch64_X4 = 220, AArch64_X5 = 221, AArch64_X6 = 222, AArch64_X7 = 223, AArch64_X8 = 224, AArch64_X9 = 225, AArch64_X10 = 226, AArch64_X11 = 227, AArch64_X12 = 228, AArch64_X13 = 229, AArch64_X14 = 230, AArch64_X15 = 231, AArch64_X16 = 232, AArch64_X17 = 233, AArch64_X18 = 234, AArch64_X19 = 235, AArch64_X20 = 236, AArch64_X21 = 237, AArch64_X22 = 238, AArch64_X23 = 239, AArch64_X24 = 240, AArch64_X25 = 241, AArch64_X26 = 242, AArch64_X27 = 243, AArch64_X28 = 244, AArch64_Z0 = 245, AArch64_Z1 = 246, AArch64_Z2 = 247, AArch64_Z3 = 248, AArch64_Z4 = 249, AArch64_Z5 = 250, AArch64_Z6 = 251, AArch64_Z7 = 252, AArch64_Z8 = 253, AArch64_Z9 = 254, AArch64_Z10 = 255, AArch64_Z11 = 256, AArch64_Z12 = 257, AArch64_Z13 = 258, AArch64_Z14 = 259, AArch64_Z15 = 260, AArch64_Z16 = 261, AArch64_Z17 = 262, AArch64_Z18 = 263, AArch64_Z19 = 264, AArch64_Z20 = 265, AArch64_Z21 = 266, AArch64_Z22 = 267, AArch64_Z23 = 268, AArch64_Z24 = 269, AArch64_Z25 = 270, AArch64_Z26 = 271, AArch64_Z27 = 272, AArch64_Z28 = 273, AArch64_Z29 = 274, AArch64_Z30 = 275, AArch64_Z31 = 276, AArch64_Z0_HI = 277, AArch64_Z1_HI = 278, AArch64_Z2_HI = 279, AArch64_Z3_HI = 280, AArch64_Z4_HI = 281, AArch64_Z5_HI = 282, AArch64_Z6_HI = 283, AArch64_Z7_HI = 284, AArch64_Z8_HI = 285, AArch64_Z9_HI = 286, AArch64_Z10_HI = 287, AArch64_Z11_HI = 288, AArch64_Z12_HI = 289, AArch64_Z13_HI = 290, AArch64_Z14_HI = 291, AArch64_Z15_HI = 292, AArch64_Z16_HI = 293, AArch64_Z17_HI = 294, AArch64_Z18_HI = 295, AArch64_Z19_HI = 296, AArch64_Z20_HI = 297, AArch64_Z21_HI = 298, AArch64_Z22_HI = 299, AArch64_Z23_HI = 300, AArch64_Z24_HI = 301, AArch64_Z25_HI = 302, AArch64_Z26_HI = 303, AArch64_Z27_HI = 304, AArch64_Z28_HI = 305, AArch64_Z29_HI = 306, AArch64_Z30_HI = 307, AArch64_Z31_HI = 308, AArch64_D0_D1 = 309, AArch64_D1_D2 = 310, AArch64_D2_D3 = 311, AArch64_D3_D4 = 312, AArch64_D4_D5 = 313, AArch64_D5_D6 = 314, AArch64_D6_D7 = 315, AArch64_D7_D8 = 316, AArch64_D8_D9 = 317, AArch64_D9_D10 = 318, AArch64_D10_D11 = 319, AArch64_D11_D12 = 320, AArch64_D12_D13 = 321, AArch64_D13_D14 = 322, AArch64_D14_D15 = 323, AArch64_D15_D16 = 324, AArch64_D16_D17 = 325, AArch64_D17_D18 = 326, AArch64_D18_D19 = 327, AArch64_D19_D20 = 328, AArch64_D20_D21 = 329, AArch64_D21_D22 = 330, AArch64_D22_D23 = 331, AArch64_D23_D24 = 332, AArch64_D24_D25 = 333, AArch64_D25_D26 = 334, AArch64_D26_D27 = 335, AArch64_D27_D28 = 336, AArch64_D28_D29 = 337, AArch64_D29_D30 = 338, AArch64_D30_D31 = 339, AArch64_D31_D0 = 340, AArch64_D0_D1_D2_D3 = 341, AArch64_D1_D2_D3_D4 = 342, AArch64_D2_D3_D4_D5 = 343, AArch64_D3_D4_D5_D6 = 344, AArch64_D4_D5_D6_D7 = 345, AArch64_D5_D6_D7_D8 = 346, AArch64_D6_D7_D8_D9 = 347, AArch64_D7_D8_D9_D10 = 348, AArch64_D8_D9_D10_D11 = 349, AArch64_D9_D10_D11_D12 = 350, AArch64_D10_D11_D12_D13 = 351, AArch64_D11_D12_D13_D14 = 352, AArch64_D12_D13_D14_D15 = 353, AArch64_D13_D14_D15_D16 = 354, AArch64_D14_D15_D16_D17 = 355, AArch64_D15_D16_D17_D18 = 356, AArch64_D16_D17_D18_D19 = 357, AArch64_D17_D18_D19_D20 = 358, AArch64_D18_D19_D20_D21 = 359, AArch64_D19_D20_D21_D22 = 360, AArch64_D20_D21_D22_D23 = 361, AArch64_D21_D22_D23_D24 = 362, AArch64_D22_D23_D24_D25 = 363, AArch64_D23_D24_D25_D26 = 364, AArch64_D24_D25_D26_D27 = 365, AArch64_D25_D26_D27_D28 = 366, AArch64_D26_D27_D28_D29 = 367, AArch64_D27_D28_D29_D30 = 368, AArch64_D28_D29_D30_D31 = 369, AArch64_D29_D30_D31_D0 = 370, AArch64_D30_D31_D0_D1 = 371, AArch64_D31_D0_D1_D2 = 372, AArch64_D0_D1_D2 = 373, AArch64_D1_D2_D3 = 374, AArch64_D2_D3_D4 = 375, AArch64_D3_D4_D5 = 376, AArch64_D4_D5_D6 = 377, AArch64_D5_D6_D7 = 378, AArch64_D6_D7_D8 = 379, AArch64_D7_D8_D9 = 380, AArch64_D8_D9_D10 = 381, AArch64_D9_D10_D11 = 382, AArch64_D10_D11_D12 = 383, AArch64_D11_D12_D13 = 384, AArch64_D12_D13_D14 = 385, AArch64_D13_D14_D15 = 386, AArch64_D14_D15_D16 = 387, AArch64_D15_D16_D17 = 388, AArch64_D16_D17_D18 = 389, AArch64_D17_D18_D19 = 390, AArch64_D18_D19_D20 = 391, AArch64_D19_D20_D21 = 392, AArch64_D20_D21_D22 = 393, AArch64_D21_D22_D23 = 394, AArch64_D22_D23_D24 = 395, AArch64_D23_D24_D25 = 396, AArch64_D24_D25_D26 = 397, AArch64_D25_D26_D27 = 398, AArch64_D26_D27_D28 = 399, AArch64_D27_D28_D29 = 400, AArch64_D28_D29_D30 = 401, AArch64_D29_D30_D31 = 402, AArch64_D30_D31_D0 = 403, AArch64_D31_D0_D1 = 404, AArch64_Q0_Q1 = 405, AArch64_Q1_Q2 = 406, AArch64_Q2_Q3 = 407, AArch64_Q3_Q4 = 408, AArch64_Q4_Q5 = 409, AArch64_Q5_Q6 = 410, AArch64_Q6_Q7 = 411, AArch64_Q7_Q8 = 412, AArch64_Q8_Q9 = 413, AArch64_Q9_Q10 = 414, AArch64_Q10_Q11 = 415, AArch64_Q11_Q12 = 416, AArch64_Q12_Q13 = 417, AArch64_Q13_Q14 = 418, AArch64_Q14_Q15 = 419, AArch64_Q15_Q16 = 420, AArch64_Q16_Q17 = 421, AArch64_Q17_Q18 = 422, AArch64_Q18_Q19 = 423, AArch64_Q19_Q20 = 424, AArch64_Q20_Q21 = 425, AArch64_Q21_Q22 = 426, AArch64_Q22_Q23 = 427, AArch64_Q23_Q24 = 428, AArch64_Q24_Q25 = 429, AArch64_Q25_Q26 = 430, AArch64_Q26_Q27 = 431, AArch64_Q27_Q28 = 432, AArch64_Q28_Q29 = 433, AArch64_Q29_Q30 = 434, AArch64_Q30_Q31 = 435, AArch64_Q31_Q0 = 436, AArch64_Q0_Q1_Q2_Q3 = 437, AArch64_Q1_Q2_Q3_Q4 = 438, AArch64_Q2_Q3_Q4_Q5 = 439, AArch64_Q3_Q4_Q5_Q6 = 440, AArch64_Q4_Q5_Q6_Q7 = 441, AArch64_Q5_Q6_Q7_Q8 = 442, AArch64_Q6_Q7_Q8_Q9 = 443, AArch64_Q7_Q8_Q9_Q10 = 444, AArch64_Q8_Q9_Q10_Q11 = 445, AArch64_Q9_Q10_Q11_Q12 = 446, AArch64_Q10_Q11_Q12_Q13 = 447, AArch64_Q11_Q12_Q13_Q14 = 448, AArch64_Q12_Q13_Q14_Q15 = 449, AArch64_Q13_Q14_Q15_Q16 = 450, AArch64_Q14_Q15_Q16_Q17 = 451, AArch64_Q15_Q16_Q17_Q18 = 452, AArch64_Q16_Q17_Q18_Q19 = 453, AArch64_Q17_Q18_Q19_Q20 = 454, AArch64_Q18_Q19_Q20_Q21 = 455, AArch64_Q19_Q20_Q21_Q22 = 456, AArch64_Q20_Q21_Q22_Q23 = 457, AArch64_Q21_Q22_Q23_Q24 = 458, AArch64_Q22_Q23_Q24_Q25 = 459, AArch64_Q23_Q24_Q25_Q26 = 460, AArch64_Q24_Q25_Q26_Q27 = 461, AArch64_Q25_Q26_Q27_Q28 = 462, AArch64_Q26_Q27_Q28_Q29 = 463, AArch64_Q27_Q28_Q29_Q30 = 464, AArch64_Q28_Q29_Q30_Q31 = 465, AArch64_Q29_Q30_Q31_Q0 = 466, AArch64_Q30_Q31_Q0_Q1 = 467, AArch64_Q31_Q0_Q1_Q2 = 468, AArch64_Q0_Q1_Q2 = 469, AArch64_Q1_Q2_Q3 = 470, AArch64_Q2_Q3_Q4 = 471, AArch64_Q3_Q4_Q5 = 472, AArch64_Q4_Q5_Q6 = 473, AArch64_Q5_Q6_Q7 = 474, AArch64_Q6_Q7_Q8 = 475, AArch64_Q7_Q8_Q9 = 476, AArch64_Q8_Q9_Q10 = 477, AArch64_Q9_Q10_Q11 = 478, AArch64_Q10_Q11_Q12 = 479, AArch64_Q11_Q12_Q13 = 480, AArch64_Q12_Q13_Q14 = 481, AArch64_Q13_Q14_Q15 = 482, AArch64_Q14_Q15_Q16 = 483, AArch64_Q15_Q16_Q17 = 484, AArch64_Q16_Q17_Q18 = 485, AArch64_Q17_Q18_Q19 = 486, AArch64_Q18_Q19_Q20 = 487, AArch64_Q19_Q20_Q21 = 488, AArch64_Q20_Q21_Q22 = 489, AArch64_Q21_Q22_Q23 = 490, AArch64_Q22_Q23_Q24 = 491, AArch64_Q23_Q24_Q25 = 492, AArch64_Q24_Q25_Q26 = 493, AArch64_Q25_Q26_Q27 = 494, AArch64_Q26_Q27_Q28 = 495, AArch64_Q27_Q28_Q29 = 496, AArch64_Q28_Q29_Q30 = 497, AArch64_Q29_Q30_Q31 = 498, AArch64_Q30_Q31_Q0 = 499, AArch64_Q31_Q0_Q1 = 500, AArch64_WZR_W0 = 501, AArch64_W30_WZR = 502, AArch64_W0_W1 = 503, AArch64_W1_W2 = 504, AArch64_W2_W3 = 505, AArch64_W3_W4 = 506, AArch64_W4_W5 = 507, AArch64_W5_W6 = 508, AArch64_W6_W7 = 509, AArch64_W7_W8 = 510, AArch64_W8_W9 = 511, AArch64_W9_W10 = 512, AArch64_W10_W11 = 513, AArch64_W11_W12 = 514, AArch64_W12_W13 = 515, AArch64_W13_W14 = 516, AArch64_W14_W15 = 517, AArch64_W15_W16 = 518, AArch64_W16_W17 = 519, AArch64_W17_W18 = 520, AArch64_W18_W19 = 521, AArch64_W19_W20 = 522, AArch64_W20_W21 = 523, AArch64_W21_W22 = 524, AArch64_W22_W23 = 525, AArch64_W23_W24 = 526, AArch64_W24_W25 = 527, AArch64_W25_W26 = 528, AArch64_W26_W27 = 529, AArch64_W27_W28 = 530, AArch64_W28_W29 = 531, AArch64_W29_W30 = 532, AArch64_FP_LR = 533, AArch64_LR_XZR = 534, AArch64_XZR_X0 = 535, AArch64_X28_FP = 536, AArch64_X0_X1 = 537, AArch64_X1_X2 = 538, AArch64_X2_X3 = 539, AArch64_X3_X4 = 540, AArch64_X4_X5 = 541, AArch64_X5_X6 = 542, AArch64_X6_X7 = 543, AArch64_X7_X8 = 544, AArch64_X8_X9 = 545, AArch64_X9_X10 = 546, AArch64_X10_X11 = 547, AArch64_X11_X12 = 548, AArch64_X12_X13 = 549, AArch64_X13_X14 = 550, AArch64_X14_X15 = 551, AArch64_X15_X16 = 552, AArch64_X16_X17 = 553, AArch64_X17_X18 = 554, AArch64_X18_X19 = 555, AArch64_X19_X20 = 556, AArch64_X20_X21 = 557, AArch64_X21_X22 = 558, AArch64_X22_X23 = 559, AArch64_X23_X24 = 560, AArch64_X24_X25 = 561, AArch64_X25_X26 = 562, AArch64_X26_X27 = 563, AArch64_X27_X28 = 564, AArch64_Z0_Z1 = 565, AArch64_Z1_Z2 = 566, AArch64_Z2_Z3 = 567, AArch64_Z3_Z4 = 568, AArch64_Z4_Z5 = 569, AArch64_Z5_Z6 = 570, AArch64_Z6_Z7 = 571, AArch64_Z7_Z8 = 572, AArch64_Z8_Z9 = 573, AArch64_Z9_Z10 = 574, AArch64_Z10_Z11 = 575, AArch64_Z11_Z12 = 576, AArch64_Z12_Z13 = 577, AArch64_Z13_Z14 = 578, AArch64_Z14_Z15 = 579, AArch64_Z15_Z16 = 580, AArch64_Z16_Z17 = 581, AArch64_Z17_Z18 = 582, AArch64_Z18_Z19 = 583, AArch64_Z19_Z20 = 584, AArch64_Z20_Z21 = 585, AArch64_Z21_Z22 = 586, AArch64_Z22_Z23 = 587, AArch64_Z23_Z24 = 588, AArch64_Z24_Z25 = 589, AArch64_Z25_Z26 = 590, AArch64_Z26_Z27 = 591, AArch64_Z27_Z28 = 592, AArch64_Z28_Z29 = 593, AArch64_Z29_Z30 = 594, AArch64_Z30_Z31 = 595, AArch64_Z31_Z0 = 596, AArch64_Z0_Z1_Z2_Z3 = 597, AArch64_Z1_Z2_Z3_Z4 = 598, AArch64_Z2_Z3_Z4_Z5 = 599, AArch64_Z3_Z4_Z5_Z6 = 600, AArch64_Z4_Z5_Z6_Z7 = 601, AArch64_Z5_Z6_Z7_Z8 = 602, AArch64_Z6_Z7_Z8_Z9 = 603, AArch64_Z7_Z8_Z9_Z10 = 604, AArch64_Z8_Z9_Z10_Z11 = 605, AArch64_Z9_Z10_Z11_Z12 = 606, AArch64_Z10_Z11_Z12_Z13 = 607, AArch64_Z11_Z12_Z13_Z14 = 608, AArch64_Z12_Z13_Z14_Z15 = 609, AArch64_Z13_Z14_Z15_Z16 = 610, AArch64_Z14_Z15_Z16_Z17 = 611, AArch64_Z15_Z16_Z17_Z18 = 612, AArch64_Z16_Z17_Z18_Z19 = 613, AArch64_Z17_Z18_Z19_Z20 = 614, AArch64_Z18_Z19_Z20_Z21 = 615, AArch64_Z19_Z20_Z21_Z22 = 616, AArch64_Z20_Z21_Z22_Z23 = 617, AArch64_Z21_Z22_Z23_Z24 = 618, AArch64_Z22_Z23_Z24_Z25 = 619, AArch64_Z23_Z24_Z25_Z26 = 620, AArch64_Z24_Z25_Z26_Z27 = 621, AArch64_Z25_Z26_Z27_Z28 = 622, AArch64_Z26_Z27_Z28_Z29 = 623, AArch64_Z27_Z28_Z29_Z30 = 624, AArch64_Z28_Z29_Z30_Z31 = 625, AArch64_Z29_Z30_Z31_Z0 = 626, AArch64_Z30_Z31_Z0_Z1 = 627, AArch64_Z31_Z0_Z1_Z2 = 628, AArch64_Z0_Z1_Z2 = 629, AArch64_Z1_Z2_Z3 = 630, AArch64_Z2_Z3_Z4 = 631, AArch64_Z3_Z4_Z5 = 632, AArch64_Z4_Z5_Z6 = 633, AArch64_Z5_Z6_Z7 = 634, AArch64_Z6_Z7_Z8 = 635, AArch64_Z7_Z8_Z9 = 636, AArch64_Z8_Z9_Z10 = 637, AArch64_Z9_Z10_Z11 = 638, AArch64_Z10_Z11_Z12 = 639, AArch64_Z11_Z12_Z13 = 640, AArch64_Z12_Z13_Z14 = 641, AArch64_Z13_Z14_Z15 = 642, AArch64_Z14_Z15_Z16 = 643, AArch64_Z15_Z16_Z17 = 644, AArch64_Z16_Z17_Z18 = 645, AArch64_Z17_Z18_Z19 = 646, AArch64_Z18_Z19_Z20 = 647, AArch64_Z19_Z20_Z21 = 648, AArch64_Z20_Z21_Z22 = 649, AArch64_Z21_Z22_Z23 = 650, AArch64_Z22_Z23_Z24 = 651, AArch64_Z23_Z24_Z25 = 652, AArch64_Z24_Z25_Z26 = 653, AArch64_Z25_Z26_Z27 = 654, AArch64_Z26_Z27_Z28 = 655, AArch64_Z27_Z28_Z29 = 656, AArch64_Z28_Z29_Z30 = 657, AArch64_Z29_Z30_Z31 = 658, AArch64_Z30_Z31_Z0 = 659, AArch64_Z31_Z0_Z1 = 660, AArch64_NUM_TARGET_REGS // 661 }; // Register classes enum { AArch64_FPR8RegClassID = 0, AArch64_FPR16RegClassID = 1, AArch64_PPRRegClassID = 2, AArch64_PPR_3bRegClassID = 3, AArch64_GPR32allRegClassID = 4, AArch64_FPR32RegClassID = 5, AArch64_GPR32RegClassID = 6, AArch64_GPR32spRegClassID = 7, AArch64_GPR32commonRegClassID = 8, AArch64_CCRRegClassID = 9, AArch64_GPR32sponlyRegClassID = 10, AArch64_WSeqPairsClassRegClassID = 11, AArch64_WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12, AArch64_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13, AArch64_WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14, AArch64_GPR64allRegClassID = 15, AArch64_FPR64RegClassID = 16, AArch64_GPR64RegClassID = 17, AArch64_GPR64spRegClassID = 18, AArch64_GPR64commonRegClassID = 19, AArch64_tcGPR64RegClassID = 20, AArch64_GPR64sponlyRegClassID = 21, AArch64_DDRegClassID = 22, AArch64_XSeqPairsClassRegClassID = 23, AArch64_XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24, AArch64_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25, AArch64_XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26, AArch64_XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27, AArch64_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28, AArch64_XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29, AArch64_FPR128RegClassID = 30, AArch64_ZPRRegClassID = 31, AArch64_FPR128_loRegClassID = 32, AArch64_ZPR_4bRegClassID = 33, AArch64_ZPR_3bRegClassID = 34, AArch64_DDDRegClassID = 35, AArch64_DDDDRegClassID = 36, AArch64_QQRegClassID = 37, AArch64_ZPR2RegClassID = 38, AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 39, AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 40, AArch64_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 41, AArch64_ZPR2_with_zsub_in_FPR128_loRegClassID = 42, AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 43, AArch64_ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 44, AArch64_ZPR2_with_zsub0_in_ZPR_3bRegClassID = 45, AArch64_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 46, AArch64_ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 47, AArch64_QQQRegClassID = 48, AArch64_ZPR3RegClassID = 49, AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 50, AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 51, AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 52, AArch64_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 53, AArch64_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 54, AArch64_ZPR3_with_zsub_in_FPR128_loRegClassID = 55, AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 56, AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 57, AArch64_ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58, AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 59, AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 60, AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 61, AArch64_ZPR3_with_zsub0_in_ZPR_3bRegClassID = 62, AArch64_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 63, AArch64_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 64, AArch64_ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 65, AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 66, AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 67, AArch64_QQQQRegClassID = 68, AArch64_ZPR4RegClassID = 69, AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 70, AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 71, AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 72, AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 73, AArch64_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 74, AArch64_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 75, AArch64_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 76, AArch64_ZPR4_with_zsub_in_FPR128_loRegClassID = 77, AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 78, AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 79, AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 80, AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 81, AArch64_ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 82, AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 83, AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 84, AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 85, AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86, AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 87, AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88, AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 89, AArch64_ZPR4_with_zsub0_in_ZPR_3bRegClassID = 90, AArch64_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 91, AArch64_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 92, AArch64_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 93, AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 94, AArch64_ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 95, AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 96, AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97, AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98, AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99, }; // Register alternate name indices enum { AArch64_NoRegAltName, // 0 AArch64_vlist1, // 1 AArch64_vreg, // 2 AArch64_NUM_TARGET_REG_ALT_NAMES = 3 }; // Subregister indices enum { AArch64_NoSubRegister, AArch64_bsub, // 1 AArch64_dsub, // 2 AArch64_dsub0, // 3 AArch64_dsub1, // 4 AArch64_dsub2, // 5 AArch64_dsub3, // 6 AArch64_hsub, // 7 AArch64_qhisub, // 8 AArch64_qsub, // 9 AArch64_qsub0, // 10 AArch64_qsub1, // 11 AArch64_qsub2, // 12 AArch64_qsub3, // 13 AArch64_ssub, // 14 AArch64_sub_32, // 15 AArch64_sube32, // 16 AArch64_sube64, // 17 AArch64_subo32, // 18 AArch64_subo64, // 19 AArch64_zsub, // 20 AArch64_zsub0, // 21 AArch64_zsub1, // 22 AArch64_zsub2, // 23 AArch64_zsub3, // 24 AArch64_zsub_hi, // 25 AArch64_dsub1_then_bsub, // 26 AArch64_dsub1_then_hsub, // 27 AArch64_dsub1_then_ssub, // 28 AArch64_dsub3_then_bsub, // 29 AArch64_dsub3_then_hsub, // 30 AArch64_dsub3_then_ssub, // 31 AArch64_dsub2_then_bsub, // 32 AArch64_dsub2_then_hsub, // 33 AArch64_dsub2_then_ssub, // 34 AArch64_qsub1_then_bsub, // 35 AArch64_qsub1_then_dsub, // 36 AArch64_qsub1_then_hsub, // 37 AArch64_qsub1_then_ssub, // 38 AArch64_qsub3_then_bsub, // 39 AArch64_qsub3_then_dsub, // 40 AArch64_qsub3_then_hsub, // 41 AArch64_qsub3_then_ssub, // 42 AArch64_qsub2_then_bsub, // 43 AArch64_qsub2_then_dsub, // 44 AArch64_qsub2_then_hsub, // 45 AArch64_qsub2_then_ssub, // 46 AArch64_subo64_then_sub_32, // 47 AArch64_zsub1_then_bsub, // 48 AArch64_zsub1_then_dsub, // 49 AArch64_zsub1_then_hsub, // 50 AArch64_zsub1_then_ssub, // 51 AArch64_zsub1_then_zsub, // 52 AArch64_zsub1_then_zsub_hi, // 53 AArch64_zsub3_then_bsub, // 54 AArch64_zsub3_then_dsub, // 55 AArch64_zsub3_then_hsub, // 56 AArch64_zsub3_then_ssub, // 57 AArch64_zsub3_then_zsub, // 58 AArch64_zsub3_then_zsub_hi, // 59 AArch64_zsub2_then_bsub, // 60 AArch64_zsub2_then_dsub, // 61 AArch64_zsub2_then_hsub, // 62 AArch64_zsub2_then_ssub, // 63 AArch64_zsub2_then_zsub, // 64 AArch64_zsub2_then_zsub_hi, // 65 AArch64_dsub0_dsub1, // 66 AArch64_dsub0_dsub1_dsub2, // 67 AArch64_dsub1_dsub2, // 68 AArch64_dsub1_dsub2_dsub3, // 69 AArch64_dsub2_dsub3, // 70 AArch64_dsub_qsub1_then_dsub, // 71 AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72 AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 73 AArch64_qsub0_qsub1, // 74 AArch64_qsub0_qsub1_qsub2, // 75 AArch64_qsub1_qsub2, // 76 AArch64_qsub1_qsub2_qsub3, // 77 AArch64_qsub2_qsub3, // 78 AArch64_qsub1_then_dsub_qsub2_then_dsub, // 79 AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 80 AArch64_qsub2_then_dsub_qsub3_then_dsub, // 81 AArch64_sub_32_subo64_then_sub_32, // 82 AArch64_dsub_zsub1_then_dsub, // 83 AArch64_zsub_zsub1_then_zsub, // 84 AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85 AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub, // 86 AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87 AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub, // 88 AArch64_zsub0_zsub1, // 89 AArch64_zsub0_zsub1_zsub2, // 90 AArch64_zsub1_zsub2, // 91 AArch64_zsub1_zsub2_zsub3, // 92 AArch64_zsub2_zsub3, // 93 AArch64_zsub1_then_dsub_zsub2_then_dsub, // 94 AArch64_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 95 AArch64_zsub1_then_zsub_zsub2_then_zsub, // 96 AArch64_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 97 AArch64_zsub2_then_dsub_zsub3_then_dsub, // 98 AArch64_zsub2_then_zsub_zsub3_then_zsub, // 99 AArch64_NUM_TARGET_SUBREGS }; #endif // GET_REGINFO_ENUM #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg AArch64RegDiffLists[] = { /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0, /* 9 */ 65105, 1, 1, 1, 0, /* 14 */ 65201, 1, 1, 1, 0, /* 19 */ 6, 29, 1, 1, 0, /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0, /* 33 */ 65324, 499, 30, 1, 1, 0, /* 39 */ 64913, 1, 1, 75, 1, 1, 0, /* 46 */ 65073, 1, 1, 0, /* 50 */ 65169, 1, 1, 0, /* 54 */ 6, 1, 29, 1, 0, /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0, /* 68 */ 6, 30, 1, 0, /* 72 */ 6, 30, 1, 46, 30, 1, 0, /* 79 */ 1, 493, 1, 32, 1, 0, /* 85 */ 31, 286, 1, 33, 1, 0, /* 91 */ 64977, 1, 76, 1, 0, /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0, /* 111 */ 320, 1, 0, /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0, /* 129 */ 526, 1, 0, /* 132 */ 530, 1, 0, /* 135 */ 65053, 1, 0, /* 138 */ 65087, 1, 0, /* 141 */ 65137, 1, 0, /* 144 */ 65218, 1, 0, /* 147 */ 65233, 1, 0, /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0, /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0, /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0, /* 387 */ 31, 285, 2, 32, 2, 0, /* 393 */ 319, 2, 0, /* 396 */ 65324, 529, 1, 1, 3, 0, /* 402 */ 2, 3, 0, /* 405 */ 531, 3, 0, /* 408 */ 65004, 3, 0, /* 411 */ 4, 0, /* 413 */ 5, 0, /* 415 */ 31, 286, 1, 5, 28, 0, /* 421 */ 292, 28, 0, /* 424 */ 6, 1, 1, 29, 0, /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0, /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, /* 502 */ 6, 1, 30, 0, /* 506 */ 6, 1, 30, 46, 1, 30, 0, /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0, /* 531 */ 6, 31, 0, /* 534 */ 6, 31, 46, 31, 0, /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0, /* 548 */ 32, 0, /* 550 */ 34, 0, /* 552 */ 5, 49, 0, /* 555 */ 63936, 49, 0, /* 558 */ 65297, 77, 0, /* 561 */ 1, 81, 0, /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0, /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0, /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0, /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0, /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0, /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0, /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0, /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0, /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0, /* 872 */ 96, 160, 0, /* 875 */ 65042, 178, 0, /* 878 */ 212, 0, /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0, /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0, /* 899 */ 65009, 65535, 209, 65505, 316, 0, /* 905 */ 65005, 212, 65325, 212, 317, 0, /* 911 */ 65244, 65505, 65325, 212, 317, 0, /* 917 */ 65215, 65505, 32, 65505, 317, 0, /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0, /* 935 */ 65005, 212, 65329, 65535, 495, 0, /* 941 */ 65323, 0, /* 943 */ 65249, 65328, 0, /* 946 */ 65342, 0, /* 948 */ 65374, 0, /* 950 */ 65389, 0, /* 952 */ 65405, 0, /* 954 */ 65421, 0, /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0, /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0, /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0, /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0, /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0, /* 1073 */ 65469, 0, /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0, /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0, /* 1093 */ 65456, 112, 65456, 65472, 0, /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0, /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0, /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0, /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0, /* 1260 */ 65501, 0, /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0, /* 1277 */ 65533, 0, /* 1279 */ 65535, 0, }; static const uint16_t AArch64SubRegIdxLists[] = { /* 0 */ 2, 14, 7, 1, 0, /* 5 */ 15, 0, /* 7 */ 16, 18, 0, /* 10 */ 20, 2, 14, 7, 1, 25, 0, /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0, /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0, /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0, /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0, /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0, /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0, /* 128 */ 17, 15, 19, 47, 82, 0, /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0, /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0, /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0, }; static const MCRegisterDesc AArch64RegDesc[] = { { 3, 0, 0, 0, 0, 0 }, { 2489, 8, 8, 4, 20465, 0 }, { 2482, 878, 405, 5, 20465, 27 }, { 2496, 878, 132, 5, 20465, 27 }, { 2514, 8, 8, 4, 20465, 0 }, { 2486, 7, 8, 5, 6576, 27 }, { 2485, 8, 1279, 4, 6576, 0 }, { 2503, 8, 79, 4, 6608, 0 }, { 2510, 1279, 129, 5, 6608, 27 }, { 213, 8, 214, 4, 20433, 0 }, { 494, 8, 296, 4, 20433, 0 }, { 713, 8, 438, 4, 20433, 0 }, { 932, 8, 150, 4, 20433, 0 }, { 1148, 8, 150, 4, 20433, 0 }, { 1364, 8, 150, 4, 20433, 0 }, { 1576, 8, 150, 4, 20433, 0 }, { 1788, 8, 150, 4, 20433, 0 }, { 2000, 8, 150, 4, 20433, 0 }, { 2204, 8, 150, 4, 20433, 0 }, { 0, 8, 150, 4, 20433, 0 }, { 284, 8, 150, 4, 20433, 0 }, { 560, 8, 150, 4, 20433, 0 }, { 776, 8, 150, 4, 20433, 0 }, { 992, 8, 150, 4, 20433, 0 }, { 1208, 8, 150, 4, 20433, 0 }, { 1424, 8, 150, 4, 20433, 0 }, { 1636, 8, 150, 4, 20433, 0 }, { 1848, 8, 150, 4, 20433, 0 }, { 2060, 8, 150, 4, 20433, 0 }, { 69, 8, 150, 4, 20433, 0 }, { 358, 8, 150, 4, 20433, 0 }, { 637, 8, 150, 4, 20433, 0 }, { 856, 8, 150, 4, 20433, 0 }, { 1072, 8, 150, 4, 20433, 0 }, { 1288, 8, 150, 4, 20433, 0 }, { 1500, 8, 150, 4, 20433, 0 }, { 1712, 8, 150, 4, 20433, 0 }, { 1924, 8, 150, 4, 20433, 0 }, { 2136, 8, 150, 4, 20433, 0 }, { 145, 8, 150, 4, 20433, 0 }, { 434, 8, 150, 4, 20433, 0 }, { 228, 1080, 217, 1, 20161, 3 }, { 508, 1080, 299, 1, 20161, 3 }, { 726, 1080, 441, 1, 20161, 3 }, { 944, 1080, 153, 1, 20161, 3 }, { 1160, 1080, 153, 1, 20161, 3 }, { 1376, 1080, 153, 1, 20161, 3 }, { 1588, 1080, 153, 1, 20161, 3 }, { 1800, 1080, 153, 1, 20161, 3 }, { 2012, 1080, 153, 1, 20161, 3 }, { 2216, 1080, 153, 1, 20161, 3 }, { 13, 1080, 153, 1, 20161, 3 }, { 298, 1080, 153, 1, 20161, 3 }, { 575, 1080, 153, 1, 20161, 3 }, { 792, 1080, 153, 1, 20161, 3 }, { 1008, 1080, 153, 1, 20161, 3 }, { 1224, 1080, 153, 1, 20161, 3 }, { 1440, 1080, 153, 1, 20161, 3 }, { 1652, 1080, 153, 1, 20161, 3 }, { 1864, 1080, 153, 1, 20161, 3 }, { 2076, 1080, 153, 1, 20161, 3 }, { 85, 1080, 153, 1, 20161, 3 }, { 374, 1080, 153, 1, 20161, 3 }, { 653, 1080, 153, 1, 20161, 3 }, { 872, 1080, 153, 1, 20161, 3 }, { 1088, 1080, 153, 1, 20161, 3 }, { 1304, 1080, 153, 1, 20161, 3 }, { 1516, 1080, 153, 1, 20161, 3 }, { 1728, 1080, 153, 1, 20161, 3 }, { 1940, 1080, 153, 1, 20161, 3 }, { 2152, 1080, 153, 1, 20161, 3 }, { 161, 1080, 153, 1, 20161, 3 }, { 450, 1080, 153, 1, 20161, 3 }, { 231, 1082, 215, 3, 17169, 3 }, { 511, 1082, 297, 3, 17169, 3 }, { 729, 1082, 439, 3, 17169, 3 }, { 947, 1082, 151, 3, 17169, 3 }, { 1163, 1082, 151, 3, 17169, 3 }, { 1379, 1082, 151, 3, 17169, 3 }, { 1591, 1082, 151, 3, 17169, 3 }, { 1803, 1082, 151, 3, 17169, 3 }, { 2015, 1082, 151, 3, 17169, 3 }, { 2219, 1082, 151, 3, 17169, 3 }, { 17, 1082, 151, 3, 17169, 3 }, { 302, 1082, 151, 3, 17169, 3 }, { 579, 1082, 151, 3, 17169, 3 }, { 796, 1082, 151, 3, 17169, 3 }, { 1012, 1082, 151, 3, 17169, 3 }, { 1228, 1082, 151, 3, 17169, 3 }, { 1444, 1082, 151, 3, 17169, 3 }, { 1656, 1082, 151, 3, 17169, 3 }, { 1868, 1082, 151, 3, 17169, 3 }, { 2080, 1082, 151, 3, 17169, 3 }, { 89, 1082, 151, 3, 17169, 3 }, { 378, 1082, 151, 3, 17169, 3 }, { 657, 1082, 151, 3, 17169, 3 }, { 876, 1082, 151, 3, 17169, 3 }, { 1092, 1082, 151, 3, 17169, 3 }, { 1308, 1082, 151, 3, 17169, 3 }, { 1520, 1082, 151, 3, 17169, 3 }, { 1732, 1082, 151, 3, 17169, 3 }, { 1944, 1082, 151, 3, 17169, 3 }, { 2156, 1082, 151, 3, 17169, 3 }, { 165, 1082, 151, 3, 17169, 3 }, { 454, 1082, 151, 3, 17169, 3 }, { 234, 8, 8, 4, 17169, 0 }, { 514, 8, 8, 4, 17169, 0 }, { 732, 8, 8, 4, 17169, 0 }, { 950, 8, 8, 4, 17169, 0 }, { 1166, 8, 8, 4, 17169, 0 }, { 1382, 8, 8, 4, 17169, 0 }, { 1594, 8, 8, 4, 17169, 0 }, { 1806, 8, 8, 4, 17169, 0 }, { 2018, 8, 8, 4, 17169, 0 }, { 2222, 8, 8, 4, 17169, 0 }, { 21, 8, 8, 4, 17169, 0 }, { 306, 8, 8, 4, 17169, 0 }, { 583, 8, 8, 4, 17169, 0 }, { 800, 8, 8, 4, 17169, 0 }, { 1016, 8, 8, 4, 17169, 0 }, { 1232, 8, 8, 4, 17169, 0 }, { 249, 1093, 247, 0, 15265, 3 }, { 528, 1093, 329, 0, 15265, 3 }, { 745, 1093, 471, 0, 15265, 3 }, { 962, 1093, 183, 0, 15265, 3 }, { 1178, 1093, 183, 0, 15265, 3 }, { 1394, 1093, 183, 0, 15265, 3 }, { 1606, 1093, 183, 0, 15265, 3 }, { 1818, 1093, 183, 0, 15265, 3 }, { 2030, 1093, 183, 0, 15265, 3 }, { 2234, 1093, 183, 0, 15265, 3 }, { 34, 1093, 183, 0, 15265, 3 }, { 320, 1093, 183, 0, 15265, 3 }, { 598, 1093, 183, 0, 15265, 3 }, { 816, 1093, 183, 0, 15265, 3 }, { 1032, 1093, 183, 0, 15265, 3 }, { 1248, 1093, 183, 0, 15265, 3 }, { 1460, 1093, 183, 0, 15265, 3 }, { 1672, 1093, 183, 0, 15265, 3 }, { 1884, 1093, 183, 0, 15265, 3 }, { 2096, 1093, 183, 0, 15265, 3 }, { 105, 1093, 183, 0, 15265, 3 }, { 394, 1093, 183, 0, 15265, 3 }, { 673, 1093, 183, 0, 15265, 3 }, { 892, 1093, 183, 0, 15265, 3 }, { 1108, 1093, 183, 0, 15265, 3 }, { 1324, 1093, 183, 0, 15265, 3 }, { 1536, 1093, 183, 0, 15265, 3 }, { 1748, 1093, 183, 0, 15265, 3 }, { 1960, 1093, 183, 0, 15265, 3 }, { 2172, 1093, 183, 0, 15265, 3 }, { 181, 1093, 183, 0, 15265, 3 }, { 470, 1093, 183, 0, 15265, 3 }, { 252, 1081, 216, 2, 15201, 3 }, { 531, 1081, 298, 2, 15201, 3 }, { 748, 1081, 440, 2, 15201, 3 }, { 965, 1081, 152, 2, 15201, 3 }, { 1181, 1081, 152, 2, 15201, 3 }, { 1397, 1081, 152, 2, 15201, 3 }, { 1609, 1081, 152, 2, 15201, 3 }, { 1821, 1081, 152, 2, 15201, 3 }, { 2033, 1081, 152, 2, 15201, 3 }, { 2237, 1081, 152, 2, 15201, 3 }, { 38, 1081, 152, 2, 15201, 3 }, { 324, 1081, 152, 2, 15201, 3 }, { 602, 1081, 152, 2, 15201, 3 }, { 820, 1081, 152, 2, 15201, 3 }, { 1036, 1081, 152, 2, 15201, 3 }, { 1252, 1081, 152, 2, 15201, 3 }, { 1464, 1081, 152, 2, 15201, 3 }, { 1676, 1081, 152, 2, 15201, 3 }, { 1888, 1081, 152, 2, 15201, 3 }, { 2100, 1081, 152, 2, 15201, 3 }, { 109, 1081, 152, 2, 15201, 3 }, { 398, 1081, 152, 2, 15201, 3 }, { 677, 1081, 152, 2, 15201, 3 }, { 896, 1081, 152, 2, 15201, 3 }, { 1112, 1081, 152, 2, 15201, 3 }, { 1328, 1081, 152, 2, 15201, 3 }, { 1540, 1081, 152, 2, 15201, 3 }, { 1752, 1081, 152, 2, 15201, 3 }, { 1964, 1081, 152, 2, 15201, 3 }, { 2176, 1081, 152, 2, 15201, 3 }, { 185, 1081, 152, 2, 15201, 3 }, { 474, 1081, 152, 2, 15201, 3 }, { 259, 8, 387, 4, 15233, 0 }, { 537, 8, 85, 4, 15233, 0 }, { 754, 8, 85, 4, 15233, 0 }, { 971, 8, 85, 4, 15233, 0 }, { 1187, 8, 85, 4, 15233, 0 }, { 1403, 8, 85, 4, 15233, 0 }, { 1615, 8, 85, 4, 15233, 0 }, { 1827, 8, 85, 4, 15233, 0 }, { 2039, 8, 85, 4, 15233, 0 }, { 2243, 8, 85, 4, 15233, 0 }, { 45, 8, 85, 4, 15233, 0 }, { 332, 8, 85, 4, 15233, 0 }, { 610, 8, 85, 4, 15233, 0 }, { 828, 8, 85, 4, 15233, 0 }, { 1044, 8, 85, 4, 15233, 0 }, { 1260, 8, 85, 4, 15233, 0 }, { 1472, 8, 85, 4, 15233, 0 }, { 1684, 8, 85, 4, 15233, 0 }, { 1896, 8, 85, 4, 15233, 0 }, { 2108, 8, 85, 4, 15233, 0 }, { 117, 8, 85, 4, 15233, 0 }, { 406, 8, 85, 4, 15233, 0 }, { 685, 8, 85, 4, 15233, 0 }, { 904, 8, 85, 4, 15233, 0 }, { 1120, 8, 85, 4, 15233, 0 }, { 1336, 8, 85, 4, 15233, 0 }, { 1548, 8, 85, 4, 15233, 0 }, { 1760, 8, 85, 4, 15233, 0 }, { 1972, 8, 415, 4, 15233, 0 }, { 2184, 8, 396, 4, 15057, 0 }, { 193, 8, 33, 4, 15057, 0 }, { 266, 1275, 393, 5, 15169, 27 }, { 543, 1275, 111, 5, 15169, 27 }, { 760, 1275, 111, 5, 15169, 27 }, { 977, 1275, 111, 5, 15169, 27 }, { 1193, 1275, 111, 5, 15169, 27 }, { 1409, 1275, 111, 5, 15169, 27 }, { 1621, 1275, 111, 5, 15169, 27 }, { 1833, 1275, 111, 5, 15169, 27 }, { 2045, 1275, 111, 5, 15169, 27 }, { 2249, 1275, 111, 5, 15169, 27 }, { 52, 1275, 111, 5, 15169, 27 }, { 340, 1275, 111, 5, 15169, 27 }, { 618, 1275, 111, 5, 15169, 27 }, { 836, 1275, 111, 5, 15169, 27 }, { 1052, 1275, 111, 5, 15169, 27 }, { 1268, 1275, 111, 5, 15169, 27 }, { 1480, 1275, 111, 5, 15169, 27 }, { 1692, 1275, 111, 5, 15169, 27 }, { 1904, 1275, 111, 5, 15169, 27 }, { 2116, 1275, 111, 5, 15169, 27 }, { 125, 1275, 111, 5, 15169, 27 }, { 414, 1275, 111, 5, 15169, 27 }, { 693, 1275, 111, 5, 15169, 27 }, { 912, 1275, 111, 5, 15169, 27 }, { 1128, 1275, 111, 5, 15169, 27 }, { 1344, 1275, 111, 5, 15169, 27 }, { 1556, 1275, 111, 5, 15169, 27 }, { 1768, 1275, 111, 5, 15169, 27 }, { 1980, 1275, 421, 5, 15169, 27 }, { 281, 880, 268, 10, 8929, 35 }, { 557, 880, 350, 10, 8929, 35 }, { 773, 880, 492, 10, 8929, 35 }, { 989, 880, 204, 10, 8929, 35 }, { 1205, 880, 204, 10, 8929, 35 }, { 1421, 880, 204, 10, 8929, 35 }, { 1633, 880, 204, 10, 8929, 35 }, { 1845, 880, 204, 10, 8929, 35 }, { 2057, 880, 204, 10, 8929, 35 }, { 2261, 880, 204, 10, 8929, 35 }, { 65, 880, 204, 10, 8929, 35 }, { 354, 880, 204, 10, 8929, 35 }, { 633, 880, 204, 10, 8929, 35 }, { 852, 880, 204, 10, 8929, 35 }, { 1068, 880, 204, 10, 8929, 35 }, { 1284, 880, 204, 10, 8929, 35 }, { 1496, 880, 204, 10, 8929, 35 }, { 1708, 880, 204, 10, 8929, 35 }, { 1920, 880, 204, 10, 8929, 35 }, { 2132, 880, 204, 10, 8929, 35 }, { 141, 880, 204, 10, 8929, 35 }, { 430, 880, 204, 10, 8929, 35 }, { 709, 880, 204, 10, 8929, 35 }, { 928, 880, 204, 10, 8929, 35 }, { 1144, 880, 204, 10, 8929, 35 }, { 1360, 880, 204, 10, 8929, 35 }, { 1572, 880, 204, 10, 8929, 35 }, { 1784, 880, 204, 10, 8929, 35 }, { 1996, 880, 204, 10, 8929, 35 }, { 2200, 880, 204, 10, 8929, 35 }, { 209, 880, 204, 10, 8929, 35 }, { 490, 880, 204, 10, 8929, 35 }, { 2285, 8, 267, 4, 15137, 0 }, { 2312, 8, 349, 4, 15137, 0 }, { 2332, 8, 491, 4, 15137, 0 }, { 2352, 8, 203, 4, 15137, 0 }, { 2372, 8, 203, 4, 15137, 0 }, { 2392, 8, 203, 4, 15137, 0 }, { 2412, 8, 203, 4, 15137, 0 }, { 2432, 8, 203, 4, 15137, 0 }, { 2452, 8, 203, 4, 15137, 0 }, { 2472, 8, 203, 4, 15137, 0 }, { 2264, 8, 203, 4, 15137, 0 }, { 2291, 8, 203, 4, 15137, 0 }, { 2318, 8, 203, 4, 15137, 0 }, { 2338, 8, 203, 4, 15137, 0 }, { 2358, 8, 203, 4, 15137, 0 }, { 2378, 8, 203, 4, 15137, 0 }, { 2398, 8, 203, 4, 15137, 0 }, { 2418, 8, 203, 4, 15137, 0 }, { 2438, 8, 203, 4, 15137, 0 }, { 2458, 8, 203, 4, 15137, 0 }, { 2271, 8, 203, 4, 15137, 0 }, { 2298, 8, 203, 4, 15137, 0 }, { 2325, 8, 203, 4, 15137, 0 }, { 2345, 8, 203, 4, 15137, 0 }, { 2365, 8, 203, 4, 15137, 0 }, { 2385, 8, 203, 4, 15137, 0 }, { 2405, 8, 203, 4, 15137, 0 }, { 2425, 8, 203, 4, 15137, 0 }, { 2445, 8, 203, 4, 15137, 0 }, { 2465, 8, 203, 4, 15137, 0 }, { 2278, 8, 203, 4, 15137, 0 }, { 2305, 8, 203, 4, 15137, 0 }, { 505, 1084, 360, 17, 2353, 61 }, { 723, 1084, 513, 17, 2353, 61 }, { 941, 1084, 278, 17, 2353, 61 }, { 1157, 1084, 278, 17, 2353, 61 }, { 1373, 1084, 278, 17, 2353, 61 }, { 1585, 1084, 278, 17, 2353, 61 }, { 1797, 1084, 278, 17, 2353, 61 }, { 2009, 1084, 278, 17, 2353, 61 }, { 2213, 1084, 278, 17, 2353, 61 }, { 10, 1084, 278, 17, 2353, 61 }, { 294, 1084, 278, 17, 2353, 61 }, { 571, 1084, 278, 17, 2353, 61 }, { 788, 1084, 278, 17, 2353, 61 }, { 1004, 1084, 278, 17, 2353, 61 }, { 1220, 1084, 278, 17, 2353, 61 }, { 1436, 1084, 278, 17, 2353, 61 }, { 1648, 1084, 278, 17, 2353, 61 }, { 1860, 1084, 278, 17, 2353, 61 }, { 2072, 1084, 278, 17, 2353, 61 }, { 81, 1084, 278, 17, 2353, 61 }, { 370, 1084, 278, 17, 2353, 61 }, { 649, 1084, 278, 17, 2353, 61 }, { 868, 1084, 278, 17, 2353, 61 }, { 1084, 1084, 278, 17, 2353, 61 }, { 1300, 1084, 278, 17, 2353, 61 }, { 1512, 1084, 278, 17, 2353, 61 }, { 1724, 1084, 278, 17, 2353, 61 }, { 1936, 1084, 278, 17, 2353, 61 }, { 2148, 1084, 278, 17, 2353, 61 }, { 157, 1084, 278, 17, 2353, 61 }, { 446, 1084, 278, 17, 2353, 61 }, { 224, 1075, 278, 17, 8496, 2 }, { 935, 1216, 872, 41, 225, 68 }, { 1151, 1216, 872, 41, 225, 68 }, { 1367, 1216, 872, 41, 225, 68 }, { 1579, 1216, 872, 41, 225, 68 }, { 1791, 1216, 872, 41, 225, 68 }, { 2003, 1216, 872, 41, 225, 68 }, { 2207, 1216, 872, 41, 225, 68 }, { 4, 1216, 872, 41, 225, 68 }, { 288, 1216, 872, 41, 225, 68 }, { 564, 1216, 872, 41, 225, 68 }, { 780, 1216, 872, 41, 225, 68 }, { 996, 1216, 872, 41, 225, 68 }, { 1212, 1216, 872, 41, 225, 68 }, { 1428, 1216, 872, 41, 225, 68 }, { 1640, 1216, 872, 41, 225, 68 }, { 1852, 1216, 872, 41, 225, 68 }, { 2064, 1216, 872, 41, 225, 68 }, { 73, 1216, 872, 41, 225, 68 }, { 362, 1216, 872, 41, 225, 68 }, { 641, 1216, 872, 41, 225, 68 }, { 860, 1216, 872, 41, 225, 68 }, { 1076, 1216, 872, 41, 225, 68 }, { 1292, 1216, 872, 41, 225, 68 }, { 1504, 1216, 872, 41, 225, 68 }, { 1716, 1216, 872, 41, 225, 68 }, { 1928, 1216, 872, 41, 225, 68 }, { 2140, 1216, 872, 41, 225, 68 }, { 149, 1216, 872, 41, 225, 68 }, { 438, 1216, 872, 41, 225, 68 }, { 216, 1238, 872, 41, 304, 73 }, { 497, 1051, 872, 41, 864, 59 }, { 716, 1194, 872, 41, 6784, 5 }, { 720, 96, 539, 26, 801, 74 }, { 938, 96, 378, 26, 801, 74 }, { 1154, 96, 378, 26, 801, 74 }, { 1370, 96, 378, 26, 801, 74 }, { 1582, 96, 378, 26, 801, 74 }, { 1794, 96, 378, 26, 801, 74 }, { 2006, 96, 378, 26, 801, 74 }, { 2210, 96, 378, 26, 801, 74 }, { 7, 96, 378, 26, 801, 74 }, { 291, 96, 378, 26, 801, 74 }, { 567, 96, 378, 26, 801, 74 }, { 784, 96, 378, 26, 801, 74 }, { 1000, 96, 378, 26, 801, 74 }, { 1216, 96, 378, 26, 801, 74 }, { 1432, 96, 378, 26, 801, 74 }, { 1644, 96, 378, 26, 801, 74 }, { 1856, 96, 378, 26, 801, 74 }, { 2068, 96, 378, 26, 801, 74 }, { 77, 96, 378, 26, 801, 74 }, { 366, 96, 378, 26, 801, 74 }, { 645, 96, 378, 26, 801, 74 }, { 864, 96, 378, 26, 801, 74 }, { 1080, 96, 378, 26, 801, 74 }, { 1296, 96, 378, 26, 801, 74 }, { 1508, 96, 378, 26, 801, 74 }, { 1720, 96, 378, 26, 801, 74 }, { 1932, 96, 378, 26, 801, 74 }, { 2144, 96, 378, 26, 801, 74 }, { 153, 96, 378, 26, 801, 74 }, { 442, 96, 378, 26, 801, 74 }, { 220, 114, 378, 26, 1088, 64 }, { 501, 1262, 378, 26, 8032, 10 }, { 525, 887, 366, 63, 2257, 80 }, { 742, 887, 519, 63, 2257, 80 }, { 959, 887, 284, 63, 2257, 80 }, { 1175, 887, 284, 63, 2257, 80 }, { 1391, 887, 284, 63, 2257, 80 }, { 1603, 887, 284, 63, 2257, 80 }, { 1815, 887, 284, 63, 2257, 80 }, { 2027, 887, 284, 63, 2257, 80 }, { 2231, 887, 284, 63, 2257, 80 }, { 31, 887, 284, 63, 2257, 80 }, { 316, 887, 284, 63, 2257, 80 }, { 594, 887, 284, 63, 2257, 80 }, { 812, 887, 284, 63, 2257, 80 }, { 1028, 887, 284, 63, 2257, 80 }, { 1244, 887, 284, 63, 2257, 80 }, { 1456, 887, 284, 63, 2257, 80 }, { 1668, 887, 284, 63, 2257, 80 }, { 1880, 887, 284, 63, 2257, 80 }, { 2092, 887, 284, 63, 2257, 80 }, { 101, 887, 284, 63, 2257, 80 }, { 390, 887, 284, 63, 2257, 80 }, { 669, 887, 284, 63, 2257, 80 }, { 888, 887, 284, 63, 2257, 80 }, { 1104, 887, 284, 63, 2257, 80 }, { 1320, 887, 284, 63, 2257, 80 }, { 1532, 887, 284, 63, 2257, 80 }, { 1744, 887, 284, 63, 2257, 80 }, { 1956, 887, 284, 63, 2257, 80 }, { 2168, 887, 284, 63, 2257, 80 }, { 177, 887, 284, 63, 2257, 80 }, { 466, 887, 284, 63, 2257, 80 }, { 245, 923, 284, 63, 8496, 14 }, { 953, 1130, 873, 96, 145, 87 }, { 1169, 1130, 873, 96, 145, 87 }, { 1385, 1130, 873, 96, 145, 87 }, { 1597, 1130, 873, 96, 145, 87 }, { 1809, 1130, 873, 96, 145, 87 }, { 2021, 1130, 873, 96, 145, 87 }, { 2225, 1130, 873, 96, 145, 87 }, { 25, 1130, 873, 96, 145, 87 }, { 310, 1130, 873, 96, 145, 87 }, { 587, 1130, 873, 96, 145, 87 }, { 804, 1130, 873, 96, 145, 87 }, { 1020, 1130, 873, 96, 145, 87 }, { 1236, 1130, 873, 96, 145, 87 }, { 1448, 1130, 873, 96, 145, 87 }, { 1660, 1130, 873, 96, 145, 87 }, { 1872, 1130, 873, 96, 145, 87 }, { 2084, 1130, 873, 96, 145, 87 }, { 93, 1130, 873, 96, 145, 87 }, { 382, 1130, 873, 96, 145, 87 }, { 661, 1130, 873, 96, 145, 87 }, { 880, 1130, 873, 96, 145, 87 }, { 1096, 1130, 873, 96, 145, 87 }, { 1312, 1130, 873, 96, 145, 87 }, { 1524, 1130, 873, 96, 145, 87 }, { 1736, 1130, 873, 96, 145, 87 }, { 1948, 1130, 873, 96, 145, 87 }, { 2160, 1130, 873, 96, 145, 87 }, { 169, 1130, 873, 96, 145, 87 }, { 458, 1130, 873, 96, 145, 87 }, { 237, 1162, 873, 96, 304, 92 }, { 517, 1019, 873, 96, 864, 78 }, { 735, 1098, 873, 96, 6784, 17 }, { 739, 956, 542, 75, 737, 93 }, { 956, 956, 381, 75, 737, 93 }, { 1172, 956, 381, 75, 737, 93 }, { 1388, 956, 381, 75, 737, 93 }, { 1600, 956, 381, 75, 737, 93 }, { 1812, 956, 381, 75, 737, 93 }, { 2024, 956, 381, 75, 737, 93 }, { 2228, 956, 381, 75, 737, 93 }, { 28, 956, 381, 75, 737, 93 }, { 313, 956, 381, 75, 737, 93 }, { 590, 956, 381, 75, 737, 93 }, { 808, 956, 381, 75, 737, 93 }, { 1024, 956, 381, 75, 737, 93 }, { 1240, 956, 381, 75, 737, 93 }, { 1452, 956, 381, 75, 737, 93 }, { 1664, 956, 381, 75, 737, 93 }, { 1876, 956, 381, 75, 737, 93 }, { 2088, 956, 381, 75, 737, 93 }, { 97, 956, 381, 75, 737, 93 }, { 386, 956, 381, 75, 737, 93 }, { 665, 956, 381, 75, 737, 93 }, { 884, 956, 381, 75, 737, 93 }, { 1100, 956, 381, 75, 737, 93 }, { 1316, 956, 381, 75, 737, 93 }, { 1528, 956, 381, 75, 737, 93 }, { 1740, 956, 381, 75, 737, 93 }, { 1952, 956, 381, 75, 737, 93 }, { 2164, 956, 381, 75, 737, 93 }, { 173, 956, 381, 75, 737, 93 }, { 462, 956, 381, 75, 737, 93 }, { 241, 977, 381, 75, 1088, 83 }, { 521, 998, 381, 75, 8032, 22 }, { 255, 875, 550, 7, 8832, 32 }, { 2499, 943, 548, 7, 6432, 32 }, { 534, 144, 550, 7, 2209, 32 }, { 751, 144, 550, 7, 2209, 32 }, { 968, 144, 550, 7, 2209, 32 }, { 1184, 144, 550, 7, 2209, 32 }, { 1400, 144, 550, 7, 2209, 32 }, { 1612, 144, 550, 7, 2209, 32 }, { 1824, 144, 550, 7, 2209, 32 }, { 2036, 144, 550, 7, 2209, 32 }, { 2240, 144, 550, 7, 2209, 32 }, { 42, 144, 550, 7, 2209, 32 }, { 328, 144, 550, 7, 2209, 32 }, { 606, 144, 550, 7, 2209, 32 }, { 824, 144, 550, 7, 2209, 32 }, { 1040, 144, 550, 7, 2209, 32 }, { 1256, 144, 550, 7, 2209, 32 }, { 1468, 144, 550, 7, 2209, 32 }, { 1680, 144, 550, 7, 2209, 32 }, { 1892, 144, 550, 7, 2209, 32 }, { 2104, 144, 550, 7, 2209, 32 }, { 113, 144, 550, 7, 2209, 32 }, { 402, 144, 550, 7, 2209, 32 }, { 681, 144, 550, 7, 2209, 32 }, { 900, 144, 550, 7, 2209, 32 }, { 1116, 144, 550, 7, 2209, 32 }, { 1332, 144, 550, 7, 2209, 32 }, { 1544, 144, 550, 7, 2209, 32 }, { 1756, 144, 550, 7, 2209, 32 }, { 1968, 144, 550, 7, 2209, 32 }, { 2180, 144, 413, 7, 8976, 29 }, { 189, 144, 7, 7, 96, 32 }, { 2493, 905, 8, 128, 96, 97 }, { 2507, 935, 8, 128, 6529, 97 }, { 262, 899, 8, 128, 8883, 97 }, { 2478, 911, 8, 128, 8976, 26 }, { 540, 917, 8, 128, 2161, 97 }, { 757, 917, 8, 128, 2161, 97 }, { 974, 917, 8, 128, 2161, 97 }, { 1190, 917, 8, 128, 2161, 97 }, { 1406, 917, 8, 128, 2161, 97 }, { 1618, 917, 8, 128, 2161, 97 }, { 1830, 917, 8, 128, 2161, 97 }, { 2042, 917, 8, 128, 2161, 97 }, { 2246, 917, 8, 128, 2161, 97 }, { 49, 917, 8, 128, 2161, 97 }, { 336, 917, 8, 128, 2161, 97 }, { 614, 917, 8, 128, 2161, 97 }, { 832, 917, 8, 128, 2161, 97 }, { 1048, 917, 8, 128, 2161, 97 }, { 1264, 917, 8, 128, 2161, 97 }, { 1476, 917, 8, 128, 2161, 97 }, { 1688, 917, 8, 128, 2161, 97 }, { 1900, 917, 8, 128, 2161, 97 }, { 2112, 917, 8, 128, 2161, 97 }, { 121, 917, 8, 128, 2161, 97 }, { 410, 917, 8, 128, 2161, 97 }, { 689, 917, 8, 128, 2161, 97 }, { 908, 917, 8, 128, 2161, 97 }, { 1124, 917, 8, 128, 2161, 97 }, { 1340, 917, 8, 128, 2161, 97 }, { 1552, 917, 8, 128, 2161, 97 }, { 1764, 917, 8, 128, 2161, 97 }, { 1976, 917, 8, 128, 2161, 97 }, { 554, 564, 372, 134, 1457, 100 }, { 770, 564, 525, 134, 1457, 100 }, { 986, 564, 290, 134, 1457, 100 }, { 1202, 564, 290, 134, 1457, 100 }, { 1418, 564, 290, 134, 1457, 100 }, { 1630, 564, 290, 134, 1457, 100 }, { 1842, 564, 290, 134, 1457, 100 }, { 2054, 564, 290, 134, 1457, 100 }, { 2258, 564, 290, 134, 1457, 100 }, { 62, 564, 290, 134, 1457, 100 }, { 350, 564, 290, 134, 1457, 100 }, { 629, 564, 290, 134, 1457, 100 }, { 848, 564, 290, 134, 1457, 100 }, { 1064, 564, 290, 134, 1457, 100 }, { 1280, 564, 290, 134, 1457, 100 }, { 1492, 564, 290, 134, 1457, 100 }, { 1704, 564, 290, 134, 1457, 100 }, { 1916, 564, 290, 134, 1457, 100 }, { 2128, 564, 290, 134, 1457, 100 }, { 137, 564, 290, 134, 1457, 100 }, { 426, 564, 290, 134, 1457, 100 }, { 705, 564, 290, 134, 1457, 100 }, { 924, 564, 290, 134, 1457, 100 }, { 1140, 564, 290, 134, 1457, 100 }, { 1356, 564, 290, 134, 1457, 100 }, { 1568, 564, 290, 134, 1457, 100 }, { 1780, 564, 290, 134, 1457, 100 }, { 1992, 564, 290, 134, 1457, 100 }, { 2196, 564, 290, 134, 1457, 100 }, { 205, 564, 290, 134, 1457, 100 }, { 486, 564, 290, 134, 1457, 100 }, { 277, 581, 290, 134, 8544, 38 }, { 980, 780, 8, 181, 1, 121 }, { 1196, 780, 8, 181, 1, 121 }, { 1412, 780, 8, 181, 1, 121 }, { 1624, 780, 8, 181, 1, 121 }, { 1836, 780, 8, 181, 1, 121 }, { 2048, 780, 8, 181, 1, 121 }, { 2252, 780, 8, 181, 1, 121 }, { 56, 780, 8, 181, 1, 121 }, { 344, 780, 8, 181, 1, 121 }, { 622, 780, 8, 181, 1, 121 }, { 840, 780, 8, 181, 1, 121 }, { 1056, 780, 8, 181, 1, 121 }, { 1272, 780, 8, 181, 1, 121 }, { 1484, 780, 8, 181, 1, 121 }, { 1696, 780, 8, 181, 1, 121 }, { 1908, 780, 8, 181, 1, 121 }, { 2120, 780, 8, 181, 1, 121 }, { 129, 780, 8, 181, 1, 121 }, { 418, 780, 8, 181, 1, 121 }, { 697, 780, 8, 181, 1, 121 }, { 916, 780, 8, 181, 1, 121 }, { 1132, 780, 8, 181, 1, 121 }, { 1348, 780, 8, 181, 1, 121 }, { 1560, 780, 8, 181, 1, 121 }, { 1772, 780, 8, 181, 1, 121 }, { 1984, 780, 8, 181, 1, 121 }, { 2188, 780, 8, 181, 1, 121 }, { 197, 780, 8, 181, 1, 121 }, { 478, 780, 8, 181, 1, 121 }, { 269, 826, 8, 181, 384, 130 }, { 546, 688, 8, 181, 944, 105 }, { 763, 734, 8, 181, 6864, 43 }, { 767, 598, 545, 151, 625, 139 }, { 983, 598, 180, 151, 625, 139 }, { 1199, 598, 180, 151, 625, 139 }, { 1415, 598, 180, 151, 625, 139 }, { 1627, 598, 180, 151, 625, 139 }, { 1839, 598, 180, 151, 625, 139 }, { 2051, 598, 180, 151, 625, 139 }, { 2255, 598, 180, 151, 625, 139 }, { 59, 598, 180, 151, 625, 139 }, { 347, 598, 180, 151, 625, 139 }, { 625, 598, 180, 151, 625, 139 }, { 844, 598, 180, 151, 625, 139 }, { 1060, 598, 180, 151, 625, 139 }, { 1276, 598, 180, 151, 625, 139 }, { 1488, 598, 180, 151, 625, 139 }, { 1700, 598, 180, 151, 625, 139 }, { 1912, 598, 180, 151, 625, 139 }, { 2124, 598, 180, 151, 625, 139 }, { 133, 598, 180, 151, 625, 139 }, { 422, 598, 180, 151, 625, 139 }, { 701, 598, 180, 151, 625, 139 }, { 920, 598, 180, 151, 625, 139 }, { 1136, 598, 180, 151, 625, 139 }, { 1352, 598, 180, 151, 625, 139 }, { 1564, 598, 180, 151, 625, 139 }, { 1776, 598, 180, 151, 625, 139 }, { 1988, 598, 180, 151, 625, 139 }, { 2192, 598, 180, 151, 625, 139 }, { 201, 598, 180, 151, 625, 139 }, { 482, 598, 180, 151, 625, 139 }, { 273, 628, 180, 151, 1152, 114 }, { 550, 658, 180, 151, 8096, 52 }, }; // FPR8 Register Class... static const MCPhysReg FPR8[] = { AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31, }; // FPR8 Bit set. static const uint8_t FPR8Bits[] = { 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // FPR16 Register Class... static const MCPhysReg FPR16[] = { AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31, }; // FPR16 Bit set. static const uint8_t FPR16Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // PPR Register Class... static const MCPhysReg PPR[] = { AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15, }; // PPR Bit set. static const uint8_t PPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, }; // PPR_3b Register Class... static const MCPhysReg PPR_3b[] = { AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, }; // PPR_3b Bit set. static const uint8_t PPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, }; // GPR32all Register Class... static const MCPhysReg GPR32all[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP, }; // GPR32all Bit set. static const uint8_t GPR32allBits[] = { 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; // FPR32 Register Class... static const MCPhysReg FPR32[] = { AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31, }; // FPR32 Bit set. static const uint8_t FPR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR32 Register Class... static const MCPhysReg GPR32[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, }; // GPR32 Bit set. static const uint8_t GPR32Bits[] = { 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; // GPR32sp Register Class... static const MCPhysReg GPR32sp[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP, }; // GPR32sp Bit set. static const uint8_t GPR32spBits[] = { 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; // GPR32common Register Class... static const MCPhysReg GPR32common[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, }; // GPR32common Bit set. static const uint8_t GPR32commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; // CCR Register Class... static const MCPhysReg CCR[] = { AArch64_NZCV, }; // CCR Bit set. static const uint8_t CCRBits[] = { 0x10, }; // GPR32sponly Register Class... static const MCPhysReg GPR32sponly[] = { AArch64_WSP, }; // GPR32sponly Bit set. static const uint8_t GPR32sponlyBits[] = { 0x40, }; // WSeqPairsClass Register Class... static const MCPhysReg WSeqPairsClass[] = { AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_W30_WZR, AArch64_WZR_W0, }; // WSeqPairsClass Bit set. static const uint8_t WSeqPairsClassBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // WSeqPairsClass_with_sube32_in_GPR32common Register Class... static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = { AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_W30_WZR, }; // WSeqPairsClass_with_sube32_in_GPR32common Bit set. static const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, }; // WSeqPairsClass_with_subo32_in_GPR32common Register Class... static const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = { AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_WZR_W0, }; // WSeqPairsClass_with_subo32_in_GPR32common Bit set. static const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, }; // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class... static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = { AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, }; // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set. static const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, }; // GPR64all Register Class... static const MCPhysReg GPR64all[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP, }; // GPR64all Bit set. static const uint8_t GPR64allBits[] = { 0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; // FPR64 Register Class... static const MCPhysReg FPR64[] = { AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31, }; // FPR64 Bit set. static const uint8_t FPR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR64 Register Class... static const MCPhysReg GPR64[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, }; // GPR64 Bit set. static const uint8_t GPR64Bits[] = { 0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; // GPR64sp Register Class... static const MCPhysReg GPR64sp[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP, }; // GPR64sp Bit set. static const uint8_t GPR64spBits[] = { 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; // GPR64common Register Class... static const MCPhysReg GPR64common[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, }; // GPR64common Bit set. static const uint8_t GPR64commonBits[] = { 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; // tcGPR64 Register Class... static const MCPhysReg tcGPR64[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, }; // tcGPR64 Bit set. static const uint8_t tcGPR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, }; // GPR64sponly Register Class... static const MCPhysReg GPR64sponly[] = { AArch64_SP, }; // GPR64sponly Bit set. static const uint8_t GPR64sponlyBits[] = { 0x20, }; // DD Register Class... static const MCPhysReg DD[] = { AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0, }; // DD Bit set. static const uint8_t DDBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // XSeqPairsClass Register Class... static const MCPhysReg XSeqPairsClass[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_LR_XZR, AArch64_XZR_X0, }; // XSeqPairsClass Bit set. static const uint8_t XSeqPairsClassBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // XSeqPairsClass_with_sub_32_in_GPR32common Register Class... static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_LR_XZR, }; // XSeqPairsClass_with_sub_32_in_GPR32common Bit set. static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, }; // XSeqPairsClass_with_subo64_in_GPR64common Register Class... static const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_XZR_X0, }; // XSeqPairsClass_with_subo64_in_GPR64common Bit set. static const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, }; // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class... static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, }; // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set. static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f, }; // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class... static const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, }; // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set. static const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, }; // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class... static const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_XZR_X0, }; // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set. static const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07, }; // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class... static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = { AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, }; // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set. static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, }; // FPR128 Register Class... static const MCPhysReg FPR128[] = { AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31, }; // FPR128 Bit set. static const uint8_t FPR128Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // ZPR Register Class... static const MCPhysReg ZPR[] = { AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31, }; // ZPR Bit set. static const uint8_t ZPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // FPR128_lo Register Class... static const MCPhysReg FPR128_lo[] = { AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, }; // FPR128_lo Bit set. static const uint8_t FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, }; // ZPR_4b Register Class... static const MCPhysReg ZPR_4b[] = { AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, }; // ZPR_4b Bit set. static const uint8_t ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // ZPR_3b Register Class... static const MCPhysReg ZPR_3b[] = { AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, }; // ZPR_3b Bit set. static const uint8_t ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // DDD Register Class... static const MCPhysReg DDD[] = { AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1, }; // DDD Bit set. static const uint8_t DDDBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // DDDD Register Class... static const MCPhysReg DDDD[] = { AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2, }; // DDDD Bit set. static const uint8_t DDDDBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // QQ Register Class... static const MCPhysReg QQ[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0, }; // QQ Bit set. static const uint8_t QQBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // ZPR2 Register Class... static const MCPhysReg ZPR2[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0, }; // ZPR2 Bit set. static const uint8_t ZPR2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // QQ_with_qsub0_in_FPR128_lo Register Class... static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, }; // QQ_with_qsub0_in_FPR128_lo Bit set. static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // QQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0, }; // QQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; // ZPR2_with_zsub1_in_ZPR_4b Register Class... static const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z31_Z0, }; // ZPR2_with_zsub1_in_ZPR_4b Bit set. static const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; // ZPR2_with_zsub_in_FPR128_lo Register Class... static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, }; // ZPR2_with_zsub_in_FPR128_lo Bit set. static const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, }; // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class... static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, }; // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set. static const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // ZPR2_with_zsub0_in_ZPR_3b Register Class... static const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, }; // ZPR2_with_zsub0_in_ZPR_3b Bit set. static const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // ZPR2_with_zsub1_in_ZPR_3b Register Class... static const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z31_Z0, }; // ZPR2_with_zsub1_in_ZPR_3b Bit set. static const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, }; // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class... static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = { AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, }; // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set. static const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // QQQ Register Class... static const MCPhysReg QQQ[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, }; // QQQ Bit set. static const uint8_t QQQBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // ZPR3 Register Class... static const MCPhysReg ZPR3[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, }; // ZPR3 Bit set. static const uint8_t ZPR3Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // QQQ_with_qsub0_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, }; // QQQ_with_qsub0_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // QQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1, }; // QQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; // QQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, }; // QQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, }; // ZPR3_with_zsub1_in_ZPR_4b Register Class... static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z31_Z0_Z1, }; // ZPR3_with_zsub1_in_ZPR_4b Bit set. static const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; // ZPR3_with_zsub2_in_ZPR_4b Register Class... static const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, }; // ZPR3_with_zsub2_in_ZPR_4b Bit set. static const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, }; // ZPR3_with_zsub_in_FPR128_lo Register Class... static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17, }; // ZPR3_with_zsub_in_FPR128_lo Bit set. static const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, }; // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1, }; // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, }; // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z31_Z0_Z1, }; // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. static const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class... static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set. static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, }; // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, }; // ZPR3_with_zsub0_in_ZPR_3b Register Class... static const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, }; // ZPR3_with_zsub0_in_ZPR_3b Bit set. static const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // ZPR3_with_zsub1_in_ZPR_3b Register Class... static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z31_Z0_Z1, }; // ZPR3_with_zsub1_in_ZPR_3b Bit set. static const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, }; // ZPR3_with_zsub2_in_ZPR_3b Register Class... static const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, }; // ZPR3_with_zsub2_in_ZPR_3b Bit set. static const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, }; // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z31_Z0_Z1, }; // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. static const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class... static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set. static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, }; // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, }; // QQQQ Register Class... static const MCPhysReg QQQQ[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ Bit set. static const uint8_t QQQQBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // ZPR4 Register Class... static const MCPhysReg ZPR4[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4 Bit set. static const uint8_t ZPR4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // QQQQ_with_qsub0_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, }; // QQQQ_with_qsub0_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // QQQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; // QQQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, }; // QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, }; // ZPR4_with_zsub1_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub1_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; // ZPR4_with_zsub2_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub2_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, }; // ZPR4_with_zsub3_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub3_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, }; // ZPR4_with_zsub_in_FPR128_lo Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18, }; // ZPR4_with_zsub_in_FPR128_lo Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, }; // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, }; // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, }; // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, }; // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, }; // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, }; // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2, }; // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, }; // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, }; // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, }; // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, }; // ZPR4_with_zsub0_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, }; // ZPR4_with_zsub0_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // ZPR4_with_zsub1_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub1_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, }; // ZPR4_with_zsub2_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub2_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, }; // ZPR4_with_zsub3_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub3_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c, }; // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, }; // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z31_Z0_Z1_Z2, }; // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = { AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, }; // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, }; static const MCRegisterClass AArch64MCRegisterClasses[] = { { FPR8, FPR8Bits, sizeof(FPR8Bits) }, { FPR16, FPR16Bits, sizeof(FPR16Bits) }, { PPR, PPRBits, sizeof(PPRBits) }, { PPR_3b, PPR_3bBits, sizeof(PPR_3bBits) }, { GPR32all, GPR32allBits, sizeof(GPR32allBits) }, { FPR32, FPR32Bits, sizeof(FPR32Bits) }, { GPR32, GPR32Bits, sizeof(GPR32Bits) }, { GPR32sp, GPR32spBits, sizeof(GPR32spBits) }, { GPR32common, GPR32commonBits, sizeof(GPR32commonBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { GPR32sponly, GPR32sponlyBits, sizeof(GPR32sponlyBits) }, { WSeqPairsClass, WSeqPairsClassBits, sizeof(WSeqPairsClassBits) }, { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits) }, { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits) }, { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits) }, { GPR64all, GPR64allBits, sizeof(GPR64allBits) }, { FPR64, FPR64Bits, sizeof(FPR64Bits) }, { GPR64, GPR64Bits, sizeof(GPR64Bits) }, { GPR64sp, GPR64spBits, sizeof(GPR64spBits) }, { GPR64common, GPR64commonBits, sizeof(GPR64commonBits) }, { tcGPR64, tcGPR64Bits, sizeof(tcGPR64Bits) }, { GPR64sponly, GPR64sponlyBits, sizeof(GPR64sponlyBits) }, { DD, DDBits, sizeof(DDBits) }, { XSeqPairsClass, XSeqPairsClassBits, sizeof(XSeqPairsClassBits) }, { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits) }, { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits) }, { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits) }, { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits) }, { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits) }, { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits) }, { FPR128, FPR128Bits, sizeof(FPR128Bits) }, { ZPR, ZPRBits, sizeof(ZPRBits) }, { FPR128_lo, FPR128_loBits, sizeof(FPR128_loBits) }, { ZPR_4b, ZPR_4bBits, sizeof(ZPR_4bBits) }, { ZPR_3b, ZPR_3bBits, sizeof(ZPR_3bBits) }, { DDD, DDDBits, sizeof(DDDBits) }, { DDDD, DDDDBits, sizeof(DDDDBits) }, { QQ, QQBits, sizeof(QQBits) }, { ZPR2, ZPR2Bits, sizeof(ZPR2Bits) }, { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, sizeof(QQ_with_qsub0_in_FPR128_loBits) }, { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, sizeof(QQ_with_qsub1_in_FPR128_loBits) }, { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits) }, { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, sizeof(ZPR2_with_zsub_in_FPR128_loBits) }, { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits) }, { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits) }, { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits) }, { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits) }, { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits) }, { QQQ, QQQBits, sizeof(QQQBits) }, { ZPR3, ZPR3Bits, sizeof(ZPR3Bits) }, { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_loBits) }, { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQ_with_qsub1_in_FPR128_loBits) }, { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub2_in_FPR128_loBits) }, { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits) }, { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits) }, { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, sizeof(ZPR3_with_zsub_in_FPR128_loBits) }, { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits) }, { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits) }, { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits) }, { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits) }, { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits) }, { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits) }, { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits) }, { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits) }, { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits) }, { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits) }, { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits) }, { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits) }, { QQQQ, QQQQBits, sizeof(QQQQBits) }, { ZPR4, ZPR4Bits, sizeof(ZPR4Bits) }, { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_loBits) }, { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_loBits) }, { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub2_in_FPR128_loBits) }, { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub3_in_FPR128_loBits) }, { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits) }, { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits) }, { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits) }, { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, sizeof(ZPR4_with_zsub_in_FPR128_loBits) }, { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits) }, { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits) }, { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) }, { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits) }, { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits) }, { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits) }, { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits) }, { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) }, { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits) }, { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits) }, { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) }, { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits) }, { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits) }, { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits) }, { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits) }, { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits) }, { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits) }, { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits) }, { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits) }, { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits) }, { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits) }, { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenRegisterName.inc000064400000000000000000000744630072674642500230510ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo, unsigned AltIdx) { #ifndef CAPSTONE_DIET static const char AsmStrsNoRegAltName[] = { /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, /* 26 */ 'W', '9', '_', 'W', '1', '0', 0, /* 33 */ 'X', '9', '_', 'X', '1', '0', 0, /* 40 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0, /* 53 */ 'b', '1', '0', 0, /* 57 */ 'd', '1', '0', 0, /* 61 */ 'h', '1', '0', 0, /* 65 */ 'p', '1', '0', 0, /* 69 */ 'q', '1', '0', 0, /* 73 */ 's', '1', '0', 0, /* 77 */ 'w', '1', '0', 0, /* 81 */ 'x', '1', '0', 0, /* 85 */ 'z', '1', '0', 0, /* 89 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, /* 105 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, /* 121 */ 'W', '1', '9', '_', 'W', '2', '0', 0, /* 129 */ 'X', '1', '9', '_', 'X', '2', '0', 0, /* 137 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0, /* 153 */ 'b', '2', '0', 0, /* 157 */ 'd', '2', '0', 0, /* 161 */ 'h', '2', '0', 0, /* 165 */ 'q', '2', '0', 0, /* 169 */ 's', '2', '0', 0, /* 173 */ 'w', '2', '0', 0, /* 177 */ 'x', '2', '0', 0, /* 181 */ 'z', '2', '0', 0, /* 185 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, /* 201 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, /* 217 */ 'W', '2', '9', '_', 'W', '3', '0', 0, /* 225 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0, /* 241 */ 'b', '3', '0', 0, /* 245 */ 'd', '3', '0', 0, /* 249 */ 'h', '3', '0', 0, /* 253 */ 'q', '3', '0', 0, /* 257 */ 's', '3', '0', 0, /* 261 */ 'w', '3', '0', 0, /* 265 */ 'x', '3', '0', 0, /* 269 */ 'z', '3', '0', 0, /* 273 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, /* 288 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, /* 303 */ 'W', 'Z', 'R', '_', 'W', '0', 0, /* 310 */ 'X', 'Z', 'R', '_', 'X', '0', 0, /* 317 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0, /* 332 */ 'b', '0', 0, /* 335 */ 'd', '0', 0, /* 338 */ 'h', '0', 0, /* 341 */ 'p', '0', 0, /* 344 */ 'q', '0', 0, /* 347 */ 's', '0', 0, /* 350 */ 'w', '0', 0, /* 353 */ 'x', '0', 0, /* 356 */ 'z', '0', 0, /* 359 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, /* 373 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, /* 387 */ 'W', '1', '0', '_', 'W', '1', '1', 0, /* 395 */ 'X', '1', '0', '_', 'X', '1', '1', 0, /* 403 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0, /* 417 */ 'b', '1', '1', 0, /* 421 */ 'd', '1', '1', 0, /* 425 */ 'h', '1', '1', 0, /* 429 */ 'p', '1', '1', 0, /* 433 */ 'q', '1', '1', 0, /* 437 */ 's', '1', '1', 0, /* 441 */ 'w', '1', '1', 0, /* 445 */ 'x', '1', '1', 0, /* 449 */ 'z', '1', '1', 0, /* 453 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, /* 469 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, /* 485 */ 'W', '2', '0', '_', 'W', '2', '1', 0, /* 493 */ 'X', '2', '0', '_', 'X', '2', '1', 0, /* 501 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0, /* 517 */ 'b', '2', '1', 0, /* 521 */ 'd', '2', '1', 0, /* 525 */ 'h', '2', '1', 0, /* 529 */ 'q', '2', '1', 0, /* 533 */ 's', '2', '1', 0, /* 537 */ 'w', '2', '1', 0, /* 541 */ 'x', '2', '1', 0, /* 545 */ 'z', '2', '1', 0, /* 549 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, /* 565 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, /* 581 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0, /* 597 */ 'b', '3', '1', 0, /* 601 */ 'd', '3', '1', 0, /* 605 */ 'h', '3', '1', 0, /* 609 */ 'q', '3', '1', 0, /* 613 */ 's', '3', '1', 0, /* 617 */ 'z', '3', '1', 0, /* 621 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, /* 635 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, /* 649 */ 'W', '0', '_', 'W', '1', 0, /* 655 */ 'X', '0', '_', 'X', '1', 0, /* 661 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0, /* 675 */ 'b', '1', 0, /* 678 */ 'd', '1', 0, /* 681 */ 'h', '1', 0, /* 684 */ 'p', '1', 0, /* 687 */ 'q', '1', 0, /* 690 */ 's', '1', 0, /* 693 */ 'w', '1', 0, /* 696 */ 'x', '1', 0, /* 699 */ 'z', '1', 0, /* 702 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, /* 717 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, /* 732 */ 'W', '1', '1', '_', 'W', '1', '2', 0, /* 740 */ 'X', '1', '1', '_', 'X', '1', '2', 0, /* 748 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0, /* 763 */ 'b', '1', '2', 0, /* 767 */ 'd', '1', '2', 0, /* 771 */ 'h', '1', '2', 0, /* 775 */ 'p', '1', '2', 0, /* 779 */ 'q', '1', '2', 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'D', '7', '_', 'D', '8', 0, /* 2524 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, /* 2536 */ 'W', '7', '_', 'W', '8', 0, /* 2542 */ 'X', '7', '_', 'X', '8', 0, /* 2548 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0, /* 2560 */ 'b', '8', 0, /* 2563 */ 'd', '8', 0, /* 2566 */ 'h', '8', 0, /* 2569 */ 'p', '8', 0, /* 2572 */ 'q', '8', 0, /* 2575 */ 's', '8', 0, /* 2578 */ 'w', '8', 0, /* 2581 */ 'x', '8', 0, /* 2584 */ 'z', '8', 0, /* 2587 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, /* 2603 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, /* 2619 */ 'W', '1', '8', '_', 'W', '1', '9', 0, /* 2627 */ 'X', '1', '8', '_', 'X', '1', '9', 0, /* 2635 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0, /* 2651 */ 'b', '1', '9', 0, /* 2655 */ 'd', '1', '9', 0, /* 2659 */ 'h', '1', '9', 0, /* 2663 */ 'q', '1', '9', 0, /* 2667 */ 's', '1', '9', 0, /* 2671 */ 'w', '1', '9', 0, /* 2675 */ 'x', '1', '9', 0, /* 2679 */ 'z', '1', '9', 0, /* 2683 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, /* 2699 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, /* 2715 */ 'W', '2', '8', '_', 'W', '2', '9', 0, /* 2723 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0, /* 2739 */ 'b', '2', '9', 0, /* 2743 */ 'd', '2', '9', 0, /* 2747 */ 'h', '2', '9', 0, /* 2751 */ 'q', '2', '9', 0, /* 2755 */ 's', '2', '9', 0, /* 2759 */ 'w', '2', '9', 0, /* 2763 */ 'x', '2', '9', 0, /* 2767 */ 'z', '2', '9', 0, /* 2771 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, /* 2783 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, /* 2795 */ 'W', '8', '_', 'W', '9', 0, /* 2801 */ 'X', '8', '_', 'X', '9', 0, /* 2807 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0, /* 2819 */ 'b', '9', 0, /* 2822 */ 'd', '9', 0, /* 2825 */ 'h', '9', 0, /* 2828 */ 'p', '9', 0, /* 2831 */ 'q', '9', 0, /* 2834 */ 's', '9', 0, /* 2837 */ 'w', '9', 0, /* 2840 */ 'x', '9', 0, /* 2843 */ 'z', '9', 0, /* 2846 */ 'X', '2', '8', '_', 'F', 'P', 0, /* 2853 */ 'F', 'P', '_', 'L', 'R', 0, /* 2859 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0, /* 2867 */ 'L', 'R', '_', 'X', 'Z', 'R', 0, /* 2874 */ 'z', '1', '0', '_', 'h', 'i', 0, /* 2881 */ 'z', '2', '0', '_', 'h', 'i', 0, /* 2888 */ 'z', '3', '0', '_', 'h', 'i', 0, /* 2895 */ 'z', '0', '_', 'h', 'i', 0, /* 2901 */ 'z', '1', '1', '_', 'h', 'i', 0, /* 2908 */ 'z', '2', '1', '_', 'h', 'i', 0, /* 2915 */ 'z', '3', '1', '_', 'h', 'i', 0, /* 2922 */ 'z', '1', '_', 'h', 'i', 0, /* 2928 */ 'z', '1', '2', '_', 'h', 'i', 0, /* 2935 */ 'z', '2', '2', '_', 'h', 'i', 0, /* 2942 */ 'z', '2', '_', 'h', 'i', 0, /* 2948 */ 'z', '1', '3', '_', 'h', 'i', 0, /* 2955 */ 'z', '2', '3', '_', 'h', 'i', 0, /* 2962 */ 'z', '3', '_', 'h', 'i', 0, /* 2968 */ 'z', '1', '4', '_', 'h', 'i', 0, /* 2975 */ 'z', '2', '4', '_', 'h', 'i', 0, /* 2982 */ 'z', '4', '_', 'h', 'i', 0, /* 2988 */ 'z', '1', '5', '_', 'h', 'i', 0, /* 2995 */ 'z', '2', '5', '_', 'h', 'i', 0, /* 3002 */ 'z', '5', '_', 'h', 'i', 0, /* 3008 */ 'z', '1', '6', '_', 'h', 'i', 0, /* 3015 */ 'z', '2', '6', '_', 'h', 'i', 0, /* 3022 */ 'z', '6', '_', 'h', 'i', 0, /* 3028 */ 'z', '1', '7', '_', 'h', 'i', 0, /* 3035 */ 'z', '2', '7', '_', 'h', 'i', 0, /* 3042 */ 'z', '7', '_', 'h', 'i', 0, /* 3048 */ 'z', '1', '8', '_', 'h', 'i', 0, /* 3055 */ 'z', '2', '8', '_', 'h', 'i', 0, /* 3062 */ 'z', '8', '_', 'h', 'i', 0, /* 3068 */ 'z', '1', '9', '_', 'h', 'i', 0, /* 3075 */ 'z', '2', '9', '_', 'h', 'i', 0, /* 3082 */ 'z', '9', '_', 'h', 'i', 0, /* 3088 */ 'w', 's', 'p', 0, /* 3092 */ 'f', 'f', 'r', 0, /* 3096 */ 'w', 'z', 'r', 0, /* 3100 */ 'x', 'z', 'r', 0, /* 3104 */ 'n', 'z', 'c', 'v', 0, }; static const uint16_t RegAsmOffsetNoRegAltName[] = { 3092, 2763, 265, 3104, 3089, 3088, 3096, 3100, 332, 675, 946, 1217, 1488, 1759, 2026, 2293, 2560, 2819, 53, 417, 763, 1037, 1308, 1579, 1850, 2117, 2384, 2651, 153, 517, 863, 1137, 1408, 1679, 1946, 2213, 2480, 2739, 241, 597, 335, 678, 949, 1220, 1491, 1762, 2029, 2296, 2563, 2822, 57, 421, 767, 1041, 1312, 1583, 1854, 2121, 2388, 2655, 157, 521, 867, 1141, 1412, 1683, 1950, 2217, 2484, 2743, 245, 601, 338, 681, 952, 1223, 1494, 1765, 2032, 2299, 2566, 2825, 61, 425, 771, 1045, 1316, 1587, 1858, 2125, 2392, 2659, 161, 525, 871, 1145, 1416, 1687, 1954, 2221, 2488, 2747, 249, 605, 341, 684, 955, 1226, 1497, 1768, 2035, 2302, 2569, 2828, 65, 429, 775, 1049, 1320, 1591, 344, 687, 958, 1229, 1500, 1771, 2038, 2305, 2572, 2831, 69, 433, 779, 1053, 1324, 1595, 1862, 2129, 2396, 2663, 165, 529, 875, 1149, 1420, 1691, 1958, 2225, 2492, 2751, 253, 609, 347, 690, 961, 1232, 1503, 1774, 2041, 2308, 2575, 2834, 73, 437, 783, 1057, 1328, 1599, 1866, 2133, 2400, 2667, 169, 533, 879, 1153, 1424, 1695, 1962, 2229, 2496, 2755, 257, 613, 350, 693, 964, 1235, 1506, 1777, 2044, 2311, 2578, 2837, 77, 441, 787, 1061, 1332, 1603, 1870, 2137, 2404, 2671, 173, 537, 883, 1157, 1428, 1699, 1966, 2233, 2500, 2759, 261, 353, 696, 967, 1238, 1509, 1780, 2047, 2314, 2581, 2840, 81, 445, 791, 1065, 1336, 1607, 1874, 2141, 2408, 2675, 177, 541, 887, 1161, 1432, 1703, 1970, 2237, 2504, 356, 699, 970, 1241, 1512, 1783, 2050, 2317, 2584, 2843, 85, 449, 795, 1069, 1340, 1611, 1878, 2145, 2412, 2679, 181, 545, 891, 1165, 1436, 1707, 1974, 2241, 2508, 2767, 269, 617, 2895, 2922, 2942, 2962, 2982, 3002, 3022, 3042, 3062, 3082, 2874, 2901, 2928, 2948, 2968, 2988, 3008, 3028, 3048, 3068, 2881, 2908, 2935, 2955, 2975, 2995, 3015, 3035, 3055, 3075, 2888, 2915, 629, 902, 1175, 1446, 1717, 1984, 2251, 2518, 2777, 6, 365, 709, 981, 1252, 1523, 1794, 2061, 2328, 2595, 97, 461, 807, 1081, 1352, 1623, 1890, 2157, 2424, 2691, 193, 557, 281, 1169, 1440, 1711, 1978, 2245, 2512, 2771, 0, 359, 702, 973, 1244, 1515, 1786, 2053, 2320, 2587, 89, 453, 799, 1073, 1344, 1615, 1882, 2149, 2416, 2683, 185, 549, 273, 621, 895, 899, 1172, 1443, 1714, 1981, 2248, 2515, 2774, 3, 362, 705, 977, 1248, 1519, 1790, 2057, 2324, 2591, 93, 457, 803, 1077, 1348, 1619, 1886, 2153, 2420, 2687, 189, 553, 277, 625, 643, 915, 1187, 1458, 1729, 1996, 2263, 2530, 2789, 19, 379, 724, 997, 1268, 1539, 1810, 2077, 2344, 2611, 113, 477, 823, 1097, 1368, 1639, 1906, 2173, 2440, 2707, 209, 573, 296, 1181, 1452, 1723, 1990, 2257, 2524, 2783, 13, 373, 717, 989, 1260, 1531, 1802, 2069, 2336, 2603, 105, 469, 815, 1089, 1360, 1631, 1898, 2165, 2432, 2699, 201, 565, 288, 635, 908, 912, 1184, 1455, 1726, 1993, 2260, 2527, 2786, 16, 376, 720, 993, 1264, 1535, 1806, 2073, 2340, 2607, 109, 473, 819, 1093, 1364, 1635, 1902, 2169, 2436, 2703, 205, 569, 292, 639, 303, 2859, 649, 921, 1193, 1464, 1735, 2002, 2269, 2536, 2795, 26, 387, 732, 1005, 1276, 1547, 1818, 2085, 2352, 2619, 121, 485, 831, 1105, 1376, 1647, 1914, 2181, 2448, 2715, 217, 2853, 2867, 310, 2846, 655, 927, 1199, 1470, 1741, 2008, 2275, 2542, 2801, 33, 395, 740, 1013, 1284, 1555, 1826, 2093, 2360, 2627, 129, 493, 839, 1113, 1384, 1655, 1922, 2189, 2456, 669, 940, 1211, 1482, 1753, 2020, 2287, 2554, 2813, 46, 409, 755, 1029, 1300, 1571, 1842, 2109, 2376, 2643, 145, 509, 855, 1129, 1400, 1671, 1938, 2205, 2472, 2731, 233, 589, 325, 1205, 1476, 1747, 2014, 2281, 2548, 2807, 40, 403, 748, 1021, 1292, 1563, 1834, 2101, 2368, 2635, 137, 501, 847, 1121, 1392, 1663, 1930, 2197, 2464, 2723, 225, 581, 317, 661, 933, 937, 1208, 1479, 1750, 2017, 2284, 2551, 2810, 43, 406, 751, 1025, 1296, 1567, 1838, 2105, 2372, 2639, 141, 505, 851, 1125, 1396, 1667, 1934, 2201, 2468, 2727, 229, 585, 321, 665, }; static const char AsmStrsvlist1[] = { /* 0 */ 0, }; static const uint8_t RegAsmOffsetvlist1[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const char AsmStrsvreg[] = { /* 0 */ 'v', '1', '0', 0, /* 4 */ 'v', '2', '0', 0, /* 8 */ 'v', '3', '0', 0, /* 12 */ 'v', '0', 0, /* 15 */ 'v', '1', '1', 0, /* 19 */ 'v', '2', '1', 0, /* 23 */ 'v', '3', '1', 0, /* 27 */ 'v', '1', 0, /* 30 */ 'v', '1', '2', 0, /* 34 */ 'v', '2', '2', 0, /* 38 */ 'v', '2', 0, /* 41 */ 'v', '1', '3', 0, /* 45 */ 'v', '2', '3', 0, /* 49 */ 'v', '3', 0, /* 52 */ 'v', '1', '4', 0, /* 56 */ 'v', '2', '4', 0, /* 60 */ 'v', '4', 0, /* 63 */ 'v', '1', '5', 0, /* 67 */ 'v', '2', '5', 0, /* 71 */ 'v', '5', 0, /* 74 */ 'v', '1', '6', 0, /* 78 */ 'v', '2', '6', 0, /* 82 */ 'v', '6', 0, /* 85 */ 'v', '1', '7', 0, /* 89 */ 'v', '2', '7', 0, /* 93 */ 'v', '7', 0, /* 96 */ 'v', '1', '8', 0, /* 100 */ 'v', '2', '8', 0, /* 104 */ 'v', '8', 0, /* 107 */ 'v', '1', '9', 0, /* 111 */ 'v', '2', '9', 0, /* 115 */ 'v', '9', 0, }; static const uint8_t RegAsmOffsetvreg[] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, }; switch(AltIdx) { default: return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0])); case AArch64_NoRegAltName: return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; case AArch64_vlist1: return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; case AArch64_vreg: return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; } #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenRegisterV.inc000064400000000000000000000115670072674642500223720ustar 00000000000000// size = 660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc000064400000000000000000000054630072674642500232320ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ enum { AArch64_FeatureAES = 0, AArch64_FeatureAggressiveFMA = 1, AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 2, AArch64_FeatureArithmeticBccFusion = 3, AArch64_FeatureArithmeticCbzFusion = 4, AArch64_FeatureBalanceFPOps = 5, AArch64_FeatureCRC = 6, AArch64_FeatureCrypto = 7, AArch64_FeatureCustomCheapAsMoveHandling = 8, AArch64_FeatureDisableLatencySchedHeuristic = 9, AArch64_FeatureDotProd = 10, AArch64_FeatureExynosCheapAsMoveHandling = 11, AArch64_FeatureFPARMv8 = 12, AArch64_FeatureFullFP16 = 13, AArch64_FeatureFuseAES = 14, AArch64_FeatureFuseAddress = 15, AArch64_FeatureFuseCCSelect = 16, AArch64_FeatureFuseLiterals = 17, AArch64_FeatureLSE = 18, AArch64_FeatureLSLFast = 19, AArch64_FeatureNEON = 20, AArch64_FeatureNoNegativeImmediates = 21, AArch64_FeaturePerfMon = 22, AArch64_FeaturePostRAScheduler = 23, AArch64_FeaturePredictableSelectIsExpensive = 24, AArch64_FeatureRAS = 25, AArch64_FeatureRCPC = 26, AArch64_FeatureRDM = 27, AArch64_FeatureReserveX18 = 28, AArch64_FeatureReserveX20 = 29, AArch64_FeatureSHA2 = 30, AArch64_FeatureSHA3 = 31, AArch64_FeatureSM4 = 32, AArch64_FeatureSPE = 33, AArch64_FeatureSVE = 34, AArch64_FeatureSlowMisaligned128Store = 35, AArch64_FeatureSlowPaired128 = 36, AArch64_FeatureSlowSTRQro = 37, AArch64_FeatureStrictAlign = 38, AArch64_FeatureUseAA = 39, AArch64_FeatureUseRSqrt = 40, AArch64_FeatureZCRegMove = 41, AArch64_FeatureZCZeroing = 42, AArch64_FeatureZCZeroingFPWorkaround = 43, AArch64_HasV8_1aOps = 44, AArch64_HasV8_2aOps = 45, AArch64_HasV8_3aOps = 46, AArch64_HasV8_4aOps = 47, AArch64_ProcA35 = 48, AArch64_ProcA53 = 49, AArch64_ProcA55 = 50, AArch64_ProcA57 = 51, AArch64_ProcA72 = 52, AArch64_ProcA73 = 53, AArch64_ProcA75 = 54, AArch64_ProcCyclone = 55, AArch64_ProcExynosM1 = 56, AArch64_ProcExynosM2 = 57, AArch64_ProcExynosM3 = 58, AArch64_ProcFalkor = 59, AArch64_ProcKryo = 60, AArch64_ProcSaphira = 61, AArch64_ProcThunderX = 62, AArch64_ProcThunderX2T99 = 63, AArch64_ProcThunderXT81 = 64, AArch64_ProcThunderXT83 = 65, AArch64_ProcThunderXT88 = 66, }; capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenSystemOperands.inc000064400000000000000000002013700072674642500234310ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ static const AT ATsList[] = { { "s1e1r", 0x3C0 }, // 0 { "s1e2r", 0x23C0 }, // 1 { "s1e3r", 0x33C0 }, // 2 { "s1e1w", 0x3C1 }, // 3 { "s1e2w", 0x23C1 }, // 4 { "s1e3w", 0x33C1 }, // 5 { "s1e0r", 0x3C2 }, // 6 { "s1e0w", 0x3C3 }, // 7 { "s12e1r", 0x23C4 }, // 8 { "s12e1w", 0x23C5 }, // 9 { "s12e0r", 0x23C6 }, // 10 { "s12e0w", 0x23C7 }, // 11 { "s1e1rp", 0x3C8 }, // 12 { "s1e1wp", 0x3C9 }, // 13 }; const AT *lookupATByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x3C0, 0 }, { 0x3C1, 3 }, { 0x3C2, 6 }, { 0x3C3, 7 }, { 0x3C8, 12 }, { 0x3C9, 13 }, { 0x23C0, 1 }, { 0x23C1, 4 }, { 0x23C4, 8 }, { 0x23C5, 9 }, { 0x23C6, 10 }, { 0x23C7, 11 }, { 0x33C0, 2 }, { 0x33C1, 5 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &ATsList[Index[i].index]; } static const DB DBsList[] = { { "oshld", 0x1 }, // 0 { "oshst", 0x2 }, // 1 { "osh", 0x3 }, // 2 { "nshld", 0x5 }, // 3 { "nshst", 0x6 }, // 4 { "nsh", 0x7 }, // 5 { "ishld", 0x9 }, // 6 { "ishst", 0xA }, // 7 { "ish", 0xB }, // 8 { "ld", 0xD }, // 9 { "st", 0xE }, // 10 { "sy", 0xF }, // 11 }; const DB *lookupDBByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x1, 0 }, { 0x2, 1 }, { 0x3, 2 }, { 0x5, 3 }, { 0x6, 4 }, { 0x7, 5 }, { 0x9, 6 }, { 0xA, 7 }, { 0xB, 8 }, { 0xD, 9 }, { 0xE, 10 }, { 0xF, 11 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &DBsList[Index[i].index]; } static const DC DCsList[] = { { "zva", 0x1BA1 }, // 0 { "ivac", 0x3B1 }, // 1 { "isw", 0x3B2 }, // 2 { "cvac", 0x1BD1 }, // 3 { "csw", 0x3D2 }, // 4 { "cvau", 0x1BD9 }, // 5 { "civac", 0x1BF1 }, // 6 { "cisw", 0x3F2 }, // 7 { "cvap", 0x1BE1 }, // 8 }; const DC *lookupDCByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x3B1, 1 }, { 0x3B2, 2 }, { 0x3D2, 4 }, { 0x3F2, 7 }, { 0x1BA1, 0 }, { 0x1BD1, 3 }, { 0x1BD9, 5 }, { 0x1BE1, 8 }, { 0x1BF1, 6 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &DCsList[Index[i].index]; } static const IC ICsList[] = { { "ialluis", 0x388, false }, // 0 { "iallu", 0x3a8, false }, // 1 { "ivau", 0x1ba9, true }, // 2 }; const IC *lookupICByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x388, 0 }, { 0x3A8, 1 }, { 0x1BA9, 2 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &ICsList[Index[i].index]; } static const TLBI TLBIsList[] = { { "ipas2e1is", 0x2401, true }, // 0 { "ipas2le1is", 0x2405, true }, // 1 { "vmalle1is", 0x418, false }, // 2 { "alle2is", 0x2418, false }, // 3 { "alle3is", 0x3418, false }, // 4 { "vae1is", 0x419, true }, // 5 { "vae2is", 0x2419, true }, // 6 { "vae3is", 0x3419, true }, // 7 { "aside1is", 0x41A, true }, // 8 { "vaae1is", 0x41B, true }, // 9 { "alle1is", 0x241C, false }, // 10 { "vale1is", 0x41D, true }, // 11 { "vale2is", 0x241D, true }, // 12 { "vale3is", 0x341D, true }, // 13 { "vmalls12e1is", 0x241E, false }, // 14 { "vaale1is", 0x41F, true }, // 15 { "ipas2e1", 0x2421, true }, // 16 { "ipas2le1", 0x2425, true }, // 17 { "vmalle1", 0x438, false }, // 18 { "alle2", 0x2438, false }, // 19 { "alle3", 0x3438, false }, // 20 { "vae1", 0x439, true }, // 21 { "vae2", 0x2439, true }, // 22 { "vae3", 0x3439, true }, // 23 { "aside1", 0x43A, true }, // 24 { "vaae1", 0x43B, true }, // 25 { "alle1", 0x243C, false }, // 26 { "vale1", 0x43D, true }, // 27 { "vale2", 0x243D, true }, // 28 { "vale3", 0x343D, true }, // 29 { "vmalls12e1", 0x243E, false }, // 30 { "vaale1", 0x43F, true }, // 31 { "vmalle1os", 0x408, false }, // 32 { "vae1os", 0x409, true }, // 33 { "aside1os", 0x40A, true }, // 34 { "vaae1os", 0x40B, true }, // 35 { "vale1os", 0x40D, true }, // 36 { "vaale1os", 0x40F, true }, // 37 { "ipas2e1os", 0x2420, true }, // 38 { "ipas2le1os", 0x2424, true }, // 39 { "vae2os", 0x2409, true }, // 40 { "vale2os", 0x240D, true }, // 41 { "vmalls12e1os", 0x240E, false }, // 42 { "vae3os", 0x3409, true }, // 43 { "vale3os", 0x340D, true }, // 44 { "alle2os", 0x2408, false }, // 45 { "alle1os", 0x240C, false }, // 46 { "alle3os", 0x3408, false }, // 47 { "rvae1", 0x431, true }, // 48 { "rvaae1", 0x433, true }, // 49 { "rvale1", 0x435, true }, // 50 { "rvaale1", 0x437, true }, // 51 { "rvae1is", 0x411, true }, // 52 { "rvaae1is", 0x413, true }, // 53 { "rvale1is", 0x415, true }, // 54 { "rvaale1is", 0x417, true }, // 55 { "rvae1os", 0x429, true }, // 56 { "rvaae1os", 0x42B, true }, // 57 { "rvale1os", 0x42D, true }, // 58 { "rvaale1os", 0x42F, true }, // 59 { "ripas2e1is", 0x2402, true }, // 60 { "ripas2le1is", 0x2406, true }, // 61 { "ripas2e1", 0x2422, true }, // 62 { "ripas2le1", 0x2426, true }, // 63 { "ripas2e1os", 0x2423, true }, // 64 { "ripas2le1os", 0x2427, true }, // 65 { "rvae2", 0x2431, true }, // 66 { "rvale2", 0x2435, true }, // 67 { "rvae2is", 0x2411, true }, // 68 { "rvale2is", 0x2415, true }, // 69 { "rvae2os", 0x2429, true }, // 70 { "rvale2os", 0x242D, true }, // 71 { "rvae3", 0x3431, true }, // 72 { "rvale3", 0x3435, true }, // 73 { "rvae3is", 0x3411, true }, // 74 { "rvale3is", 0x3415, true }, // 75 { "rvae3os", 0x3429, true }, // 76 { "rvale3os", 0x342D, true }, // 77 }; const TLBI *lookupTLBIByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x408, 32 }, { 0x409, 33 }, { 0x40A, 34 }, { 0x40B, 35 }, { 0x40D, 36 }, { 0x40F, 37 }, { 0x411, 52 }, { 0x413, 53 }, { 0x415, 54 }, { 0x417, 55 }, { 0x418, 2 }, { 0x419, 5 }, { 0x41A, 8 }, { 0x41B, 9 }, { 0x41D, 11 }, { 0x41F, 15 }, { 0x429, 56 }, { 0x42B, 57 }, { 0x42D, 58 }, { 0x42F, 59 }, { 0x431, 48 }, { 0x433, 49 }, { 0x435, 50 }, { 0x437, 51 }, { 0x438, 18 }, { 0x439, 21 }, { 0x43A, 24 }, { 0x43B, 25 }, { 0x43D, 27 }, { 0x43F, 31 }, { 0x2401, 0 }, { 0x2402, 60 }, { 0x2405, 1 }, { 0x2406, 61 }, { 0x2408, 45 }, { 0x2409, 40 }, { 0x240C, 46 }, { 0x240D, 41 }, { 0x240E, 42 }, { 0x2411, 68 }, { 0x2415, 69 }, { 0x2418, 3 }, { 0x2419, 6 }, { 0x241C, 10 }, { 0x241D, 12 }, { 0x241E, 14 }, { 0x2420, 38 }, { 0x2421, 16 }, { 0x2422, 62 }, { 0x2423, 64 }, { 0x2424, 39 }, { 0x2425, 17 }, { 0x2426, 63 }, { 0x2427, 65 }, { 0x2429, 70 }, { 0x242D, 71 }, { 0x2431, 66 }, { 0x2435, 67 }, { 0x2438, 19 }, { 0x2439, 22 }, { 0x243C, 26 }, { 0x243D, 28 }, { 0x243E, 30 }, { 0x3408, 47 }, { 0x3409, 43 }, { 0x340D, 44 }, { 0x3411, 74 }, { 0x3415, 75 }, { 0x3418, 4 }, { 0x3419, 7 }, { 0x341D, 13 }, { 0x3429, 76 }, { 0x342D, 77 }, { 0x3431, 72 }, { 0x3435, 73 }, { 0x3438, 20 }, { 0x3439, 23 }, { 0x343D, 29 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &TLBIsList[Index[i].index]; } static const SVEPRFM SVEPRFMsList[] = { { "pldl1keep", 0x0 }, // 0 { "pldl1strm", 0x1 }, // 1 { "pldl2keep", 0x2 }, // 2 { "pldl2strm", 0x3 }, // 3 { "pldl3keep", 0x4 }, // 4 { "pldl3strm", 0x5 }, // 5 { "pstl1keep", 0x8 }, // 6 { "pstl1strm", 0x9 }, // 7 { "pstl2keep", 0xA }, // 8 { "pstl2strm", 0xB }, // 9 { "pstl3keep", 0xC }, // 10 { "pstl3strm", 0xD }, // 11 }; const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x0, 0 }, { 0x1, 1 }, { 0x2, 2 }, { 0x3, 3 }, { 0x4, 4 }, { 0x5, 5 }, { 0x8, 6 }, { 0x9, 7 }, { 0xA, 8 }, { 0xB, 9 }, { 0xC, 10 }, { 0xD, 11 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &SVEPRFMsList[Index[i].index]; } static const PRFM PRFMsList[] = { { "pldl1keep", 0x0 }, // 0 { "pldl1strm", 0x1 }, // 1 { "pldl2keep", 0x2 }, // 2 { "pldl2strm", 0x3 }, // 3 { "pldl3keep", 0x4 }, // 4 { "pldl3strm", 0x5 }, // 5 { "plil1keep", 0x8 }, // 6 { "plil1strm", 0x9 }, // 7 { "plil2keep", 0xa }, // 8 { "plil2strm", 0xb }, // 9 { "plil3keep", 0xc }, // 10 { "plil3strm", 0xd }, // 11 { "pstl1keep", 0x10 }, // 12 { "pstl1strm", 0x11 }, // 13 { "pstl2keep", 0x12 }, // 14 { "pstl2strm", 0x13 }, // 15 { "pstl3keep", 0x14 }, // 16 { "pstl3strm", 0x15 }, // 17 }; const PRFM *lookupPRFMByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x0, 0 }, { 0x1, 1 }, { 0x2, 2 }, { 0x3, 3 }, { 0x4, 4 }, { 0x5, 5 }, { 0x8, 6 }, { 0x9, 7 }, { 0xA, 8 }, { 0xB, 9 }, { 0xC, 10 }, { 0xD, 11 }, { 0x10, 12 }, { 0x11, 13 }, { 0x12, 14 }, { 0x13, 15 }, { 0x14, 16 }, { 0x15, 17 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &PRFMsList[Index[i].index]; } static const PSB PSBsList[] = { { "csync", 0x11 }, // 0 }; const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x11, 0 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &PSBsList[Index[i].index]; } static const ISB ISBsList[] = { { "sy", 0xf }, // 0 }; const ISB *lookupISBByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0xF, 0 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &ISBsList[Index[i].index]; } static const TSB TSBsList[] = { { "csync", 0x0 }, // 0 }; const TSB *lookupTSBByEncoding(uint16_t Encoding) { static const struct IndexType Index[] = { { 0x0, 0 }, }; if (Encoding >= ARR_SIZE(TSBsList)) return NULL; else return &TSBsList[Index[Encoding].index]; } static const SysReg SysRegsList[] = { { "mdccsr_el0", 0x9808, true, false }, // 0 { "dbgdtrrx_el0", 0x9828, true, false }, // 1 { "mdrar_el1", 0x8080, true, false }, // 2 { "oslsr_el1", 0x808C, true, false }, // 3 { "dbgauthstatus_el1", 0x83F6, true, false }, // 4 { "pmceid0_el0", 0xDCE6, true, false }, // 5 { "pmceid1_el0", 0xDCE7, true, false }, // 6 { "midr_el1", 0xC000, true, false }, // 7 { "ccsidr_el1", 0xC800, true, false }, // 8 { "ccsidr2_el1", 0xC802, true, false }, // 9 { "clidr_el1", 0xC801, true, false }, // 10 { "ctr_el0", 0xD801, true, false }, // 11 { "mpidr_el1", 0xC005, true, false }, // 12 { "revidr_el1", 0xC006, true, false }, // 13 { "aidr_el1", 0xC807, true, false }, // 14 { "dczid_el0", 0xD807, true, false }, // 15 { "id_pfr0_el1", 0xC008, true, false }, // 16 { "id_pfr1_el1", 0xC009, true, false }, // 17 { "id_dfr0_el1", 0xC00A, true, false }, // 18 { "id_afr0_el1", 0xC00B, true, false }, // 19 { "id_mmfr0_el1", 0xC00C, true, false }, // 20 { "id_mmfr1_el1", 0xC00D, true, false }, // 21 { "id_mmfr2_el1", 0xC00E, true, false }, // 22 { "id_mmfr3_el1", 0xC00F, true, false }, // 23 { "id_isar0_el1", 0xC010, true, false }, // 24 { "id_isar1_el1", 0xC011, true, false }, // 25 { "id_isar2_el1", 0xC012, true, false }, // 26 { "id_isar3_el1", 0xC013, true, false }, // 27 { "id_isar4_el1", 0xC014, true, false }, // 28 { "id_isar5_el1", 0xC015, true, false }, // 29 { "id_isar6_el1", 0xC017, true, false }, // 30 { "id_aa64pfr0_el1", 0xC020, true, false }, // 31 { "id_aa64pfr1_el1", 0xC021, true, false }, // 32 { "id_aa64dfr0_el1", 0xC028, true, false }, // 33 { "id_aa64dfr1_el1", 0xC029, true, false }, // 34 { "id_aa64afr0_el1", 0xC02C, true, false }, // 35 { "id_aa64afr1_el1", 0xC02D, true, false }, // 36 { "id_aa64isar0_el1", 0xC030, true, false }, // 37 { "id_aa64isar1_el1", 0xC031, true, false }, // 38 { "id_aa64mmfr0_el1", 0xC038, true, false }, // 39 { "id_aa64mmfr1_el1", 0xC039, true, false }, // 40 { "id_aa64mmfr2_el1", 0xC03A, true, false }, // 41 { "mvfr0_el1", 0xC018, true, false }, // 42 { "mvfr1_el1", 0xC019, true, false }, // 43 { "mvfr2_el1", 0xC01A, true, false }, // 44 { "rvbar_el1", 0xC601, true, false }, // 45 { "rvbar_el2", 0xE601, true, false }, // 46 { "rvbar_el3", 0xF601, true, false }, // 47 { "isr_el1", 0xC608, true, false }, // 48 { "cntpct_el0", 0xDF01, true, false }, // 49 { "cntvct_el0", 0xDF02, true, false }, // 50 { "id_mmfr4_el1", 0xC016, true, false }, // 51 { "trcstatr", 0x8818, true, false }, // 52 { "trcidr8", 0x8806, true, false }, // 53 { "trcidr9", 0x880E, true, false }, // 54 { "trcidr10", 0x8816, true, false }, // 55 { "trcidr11", 0x881E, true, false }, // 56 { "trcidr12", 0x8826, true, false }, // 57 { "trcidr13", 0x882E, true, false }, // 58 { "trcidr0", 0x8847, true, false }, // 59 { "trcidr1", 0x884F, true, false }, // 60 { "trcidr2", 0x8857, true, false }, // 61 { "trcidr3", 0x885F, true, false }, // 62 { "trcidr4", 0x8867, true, false }, // 63 { "trcidr5", 0x886F, true, false }, // 64 { "trcidr6", 0x8877, true, false }, // 65 { "trcidr7", 0x887F, true, false }, // 66 { "trcoslsr", 0x888C, true, false }, // 67 { "trcpdsr", 0x88AC, true, false }, // 68 { "trcdevaff0", 0x8BD6, true, false }, // 69 { "trcdevaff1", 0x8BDE, true, false }, // 70 { "trclsr", 0x8BEE, true, false }, // 71 { "trcauthstatus", 0x8BF6, true, false }, // 72 { "trcdevarch", 0x8BFE, true, false }, // 73 { "trcdevid", 0x8B97, true, false }, // 74 { "trcdevtype", 0x8B9F, true, false }, // 75 { "trcpidr4", 0x8BA7, true, false }, // 76 { "trcpidr5", 0x8BAF, true, false }, // 77 { "trcpidr6", 0x8BB7, true, false }, // 78 { "trcpidr7", 0x8BBF, true, false }, // 79 { "trcpidr0", 0x8BC7, true, false }, // 80 { "trcpidr1", 0x8BCF, true, false }, // 81 { "trcpidr2", 0x8BD7, true, false }, // 82 { "trcpidr3", 0x8BDF, true, false }, // 83 { "trccidr0", 0x8BE7, true, false }, // 84 { "trccidr1", 0x8BEF, true, false }, // 85 { "trccidr2", 0x8BF7, true, false }, // 86 { "trccidr3", 0x8BFF, true, false }, // 87 { "icc_iar1_el1", 0xC660, true, false }, // 88 { "icc_iar0_el1", 0xC640, true, false }, // 89 { "icc_hppir1_el1", 0xC662, true, false }, // 90 { "icc_hppir0_el1", 0xC642, true, false }, // 91 { "icc_rpr_el1", 0xC65B, true, false }, // 92 { "ich_vtr_el2", 0xE659, true, false }, // 93 { "ich_eisr_el2", 0xE65B, true, false }, // 94 { "ich_elrsr_el2", 0xE65D, true, false }, // 95 { "id_aa64zfr0_el1", 0xC024, true, false }, // 96 { "lorid_el1", 0xC527, true, false }, // 97 { "erridr_el1", 0xC298, true, false }, // 98 { "erxfr_el1", 0xC2A0, true, false }, // 99 { "dbgdtrtx_el0", 0x9828, false, true }, // 100 { "oslar_el1", 0x8084, false, true }, // 101 { "pmswinc_el0", 0xDCE4, false, true }, // 102 { "trcoslar", 0x8884, false, true }, // 103 { "trclar", 0x8BE6, false, true }, // 104 { "icc_eoir1_el1", 0xC661, false, true }, // 105 { "icc_eoir0_el1", 0xC641, false, true }, // 106 { "icc_dir_el1", 0xC659, false, true }, // 107 { "icc_sgi1r_el1", 0xC65D, false, true }, // 108 { "icc_asgi1r_el1", 0xC65E, false, true }, // 109 { "icc_sgi0r_el1", 0xC65F, false, true }, // 110 { "osdtrrx_el1", 0x8002, true, true }, // 111 { "osdtrtx_el1", 0x801A, true, true }, // 112 { "teecr32_el1", 0x9000, true, true }, // 113 { "mdccint_el1", 0x8010, true, true }, // 114 { "mdscr_el1", 0x8012, true, true }, // 115 { "dbgdtr_el0", 0x9820, true, true }, // 116 { "oseccr_el1", 0x8032, true, true }, // 117 { "dbgvcr32_el2", 0xA038, true, true }, // 118 { "dbgbvr0_el1", 0x8004, true, true }, // 119 { "dbgbvr1_el1", 0x800C, true, true }, // 120 { "dbgbvr2_el1", 0x8014, true, true }, // 121 { "dbgbvr3_el1", 0x801C, true, true }, // 122 { "dbgbvr4_el1", 0x8024, true, true }, // 123 { "dbgbvr5_el1", 0x802C, true, true }, // 124 { "dbgbvr6_el1", 0x8034, true, true }, // 125 { "dbgbvr7_el1", 0x803C, true, true }, // 126 { "dbgbvr8_el1", 0x8044, true, true }, // 127 { "dbgbvr9_el1", 0x804C, true, true }, // 128 { "dbgbvr10_el1", 0x8054, true, true }, // 129 { "dbgbvr11_el1", 0x805C, true, true }, // 130 { "dbgbvr12_el1", 0x8064, true, true }, // 131 { "dbgbvr13_el1", 0x806C, true, true }, // 132 { "dbgbvr14_el1", 0x8074, true, true }, // 133 { "dbgbvr15_el1", 0x807C, true, true }, // 134 { "dbgbcr0_el1", 0x8005, true, true }, // 135 { "dbgbcr1_el1", 0x800D, true, true }, // 136 { "dbgbcr2_el1", 0x8015, true, true }, // 137 { "dbgbcr3_el1", 0x801D, true, true }, // 138 { "dbgbcr4_el1", 0x8025, true, true }, // 139 { "dbgbcr5_el1", 0x802D, true, true }, // 140 { "dbgbcr6_el1", 0x8035, true, true }, // 141 { "dbgbcr7_el1", 0x803D, true, true }, // 142 { "dbgbcr8_el1", 0x8045, true, true }, // 143 { "dbgbcr9_el1", 0x804D, true, true }, // 144 { "dbgbcr10_el1", 0x8055, true, true }, // 145 { "dbgbcr11_el1", 0x805D, true, true }, // 146 { "dbgbcr12_el1", 0x8065, true, true }, // 147 { "dbgbcr13_el1", 0x806D, true, true }, // 148 { "dbgbcr14_el1", 0x8075, true, true }, // 149 { "dbgbcr15_el1", 0x807D, true, true }, // 150 { "dbgwvr0_el1", 0x8006, true, true }, // 151 { "dbgwvr1_el1", 0x800E, true, true }, // 152 { "dbgwvr2_el1", 0x8016, true, true }, // 153 { "dbgwvr3_el1", 0x801E, true, true }, // 154 { "dbgwvr4_el1", 0x8026, true, true }, // 155 { "dbgwvr5_el1", 0x802E, true, true }, // 156 { "dbgwvr6_el1", 0x8036, true, true }, // 157 { "dbgwvr7_el1", 0x803E, true, true }, // 158 { "dbgwvr8_el1", 0x8046, true, true }, // 159 { "dbgwvr9_el1", 0x804E, true, true }, // 160 { "dbgwvr10_el1", 0x8056, true, true }, // 161 { "dbgwvr11_el1", 0x805E, true, true }, // 162 { "dbgwvr12_el1", 0x8066, true, true }, // 163 { "dbgwvr13_el1", 0x806E, true, true }, // 164 { "dbgwvr14_el1", 0x8076, true, true }, // 165 { "dbgwvr15_el1", 0x807E, true, true }, // 166 { "dbgwcr0_el1", 0x8007, true, true }, // 167 { "dbgwcr1_el1", 0x800F, true, true }, // 168 { "dbgwcr2_el1", 0x8017, true, true }, // 169 { "dbgwcr3_el1", 0x801F, true, true }, // 170 { "dbgwcr4_el1", 0x8027, true, true }, // 171 { "dbgwcr5_el1", 0x802F, true, true }, // 172 { "dbgwcr6_el1", 0x8037, true, true }, // 173 { "dbgwcr7_el1", 0x803F, true, true }, // 174 { "dbgwcr8_el1", 0x8047, true, true }, // 175 { "dbgwcr9_el1", 0x804F, true, true }, // 176 { "dbgwcr10_el1", 0x8057, true, true }, // 177 { "dbgwcr11_el1", 0x805F, true, true }, // 178 { "dbgwcr12_el1", 0x8067, true, true }, // 179 { "dbgwcr13_el1", 0x806F, true, true }, // 180 { "dbgwcr14_el1", 0x8077, true, true }, // 181 { "dbgwcr15_el1", 0x807F, true, true }, // 182 { "teehbr32_el1", 0x9080, true, true }, // 183 { "osdlr_el1", 0x809C, true, true }, // 184 { "dbgprcr_el1", 0x80A4, true, true }, // 185 { "dbgclaimset_el1", 0x83C6, true, true }, // 186 { "dbgclaimclr_el1", 0x83CE, true, true }, // 187 { "csselr_el1", 0xD000, true, true }, // 188 { "vpidr_el2", 0xE000, true, true }, // 189 { "vmpidr_el2", 0xE005, true, true }, // 190 { "cpacr_el1", 0xC082, true, true }, // 191 { "sctlr_el1", 0xC080, true, true }, // 192 { "sctlr_el2", 0xE080, true, true }, // 193 { "sctlr_el3", 0xF080, true, true }, // 194 { "actlr_el1", 0xC081, true, true }, // 195 { "actlr_el2", 0xE081, true, true }, // 196 { "actlr_el3", 0xF081, true, true }, // 197 { "hcr_el2", 0xE088, true, true }, // 198 { "scr_el3", 0xF088, true, true }, // 199 { "mdcr_el2", 0xE089, true, true }, // 200 { "sder32_el3", 0xF089, true, true }, // 201 { "cptr_el2", 0xE08A, true, true }, // 202 { "cptr_el3", 0xF08A, true, true }, // 203 { "hstr_el2", 0xE08B, true, true }, // 204 { "hacr_el2", 0xE08F, true, true }, // 205 { "mdcr_el3", 0xF099, true, true }, // 206 { "ttbr0_el1", 0xC100, true, true }, // 207 { "ttbr0_el2", 0xE100, true, true }, // 208 { "ttbr0_el3", 0xF100, true, true }, // 209 { "ttbr1_el1", 0xC101, true, true }, // 210 { "tcr_el1", 0xC102, true, true }, // 211 { "tcr_el2", 0xE102, true, true }, // 212 { "tcr_el3", 0xF102, true, true }, // 213 { "vttbr_el2", 0xE108, true, true }, // 214 { "vtcr_el2", 0xE10A, true, true }, // 215 { "dacr32_el2", 0xE180, true, true }, // 216 { "spsr_el1", 0xC200, true, true }, // 217 { "spsr_el2", 0xE200, true, true }, // 218 { "spsr_el3", 0xF200, true, true }, // 219 { "elr_el1", 0xC201, true, true }, // 220 { "elr_el2", 0xE201, true, true }, // 221 { "elr_el3", 0xF201, true, true }, // 222 { "sp_el0", 0xC208, true, true }, // 223 { "sp_el1", 0xE208, true, true }, // 224 { "sp_el2", 0xF208, true, true }, // 225 { "spsel", 0xC210, true, true }, // 226 { "nzcv", 0xDA10, true, true }, // 227 { "daif", 0xDA11, true, true }, // 228 { "currentel", 0xC212, true, true }, // 229 { "spsr_irq", 0xE218, true, true }, // 230 { "spsr_abt", 0xE219, true, true }, // 231 { "spsr_und", 0xE21A, true, true }, // 232 { "spsr_fiq", 0xE21B, true, true }, // 233 { "fpcr", 0xDA20, true, true }, // 234 { "fpsr", 0xDA21, true, true }, // 235 { "dspsr_el0", 0xDA28, true, true }, // 236 { "dlr_el0", 0xDA29, true, true }, // 237 { "ifsr32_el2", 0xE281, true, true }, // 238 { "afsr0_el1", 0xC288, true, true }, // 239 { "afsr0_el2", 0xE288, true, true }, // 240 { "afsr0_el3", 0xF288, true, true }, // 241 { "afsr1_el1", 0xC289, true, true }, // 242 { "afsr1_el2", 0xE289, true, true }, // 243 { "afsr1_el3", 0xF289, true, true }, // 244 { "esr_el1", 0xC290, true, true }, // 245 { "esr_el2", 0xE290, true, true }, // 246 { "esr_el3", 0xF290, true, true }, // 247 { "fpexc32_el2", 0xE298, true, true }, // 248 { "far_el1", 0xC300, true, true }, // 249 { "far_el2", 0xE300, true, true }, // 250 { "far_el3", 0xF300, true, true }, // 251 { "hpfar_el2", 0xE304, true, true }, // 252 { "par_el1", 0xC3A0, true, true }, // 253 { "pmcr_el0", 0xDCE0, true, true }, // 254 { "pmcntenset_el0", 0xDCE1, true, true }, // 255 { "pmcntenclr_el0", 0xDCE2, true, true }, // 256 { "pmovsclr_el0", 0xDCE3, true, true }, // 257 { "pmselr_el0", 0xDCE5, true, true }, // 258 { "pmccntr_el0", 0xDCE8, true, true }, // 259 { "pmxevtyper_el0", 0xDCE9, true, true }, // 260 { "pmxevcntr_el0", 0xDCEA, true, true }, // 261 { "pmuserenr_el0", 0xDCF0, true, true }, // 262 { "pmintenset_el1", 0xC4F1, true, true }, // 263 { "pmintenclr_el1", 0xC4F2, true, true }, // 264 { "pmovsset_el0", 0xDCF3, true, true }, // 265 { "mair_el1", 0xC510, true, true }, // 266 { "mair_el2", 0xE510, true, true }, // 267 { "mair_el3", 0xF510, true, true }, // 268 { "amair_el1", 0xC518, true, true }, // 269 { "amair_el2", 0xE518, true, true }, // 270 { "amair_el3", 0xF518, true, true }, // 271 { "vbar_el1", 0xC600, true, true }, // 272 { "vbar_el2", 0xE600, true, true }, // 273 { "vbar_el3", 0xF600, true, true }, // 274 { "rmr_el1", 0xC602, true, true }, // 275 { "rmr_el2", 0xE602, true, true }, // 276 { "rmr_el3", 0xF602, true, true }, // 277 { "contextidr_el1", 0xC681, true, true }, // 278 { "tpidr_el0", 0xDE82, true, true }, // 279 { "tpidr_el2", 0xE682, true, true }, // 280 { "tpidr_el3", 0xF682, true, true }, // 281 { "tpidrro_el0", 0xDE83, true, true }, // 282 { "tpidr_el1", 0xC684, true, true }, // 283 { "cntfrq_el0", 0xDF00, true, true }, // 284 { "cntvoff_el2", 0xE703, true, true }, // 285 { "cntkctl_el1", 0xC708, true, true }, // 286 { "cnthctl_el2", 0xE708, true, true }, // 287 { "cntp_tval_el0", 0xDF10, true, true }, // 288 { "cnthp_tval_el2", 0xE710, true, true }, // 289 { "cntps_tval_el1", 0xFF10, true, true }, // 290 { "cntp_ctl_el0", 0xDF11, true, true }, // 291 { "cnthp_ctl_el2", 0xE711, true, true }, // 292 { "cntps_ctl_el1", 0xFF11, true, true }, // 293 { "cntp_cval_el0", 0xDF12, true, true }, // 294 { "cnthp_cval_el2", 0xE712, true, true }, // 295 { "cntps_cval_el1", 0xFF12, true, true }, // 296 { "cntv_tval_el0", 0xDF18, true, true }, // 297 { "cntv_ctl_el0", 0xDF19, true, true }, // 298 { "cntv_cval_el0", 0xDF1A, true, true }, // 299 { "pmevcntr0_el0", 0xDF40, true, true }, // 300 { "pmevcntr1_el0", 0xDF41, true, true }, // 301 { "pmevcntr2_el0", 0xDF42, true, true }, // 302 { "pmevcntr3_el0", 0xDF43, true, true }, // 303 { "pmevcntr4_el0", 0xDF44, true, true }, // 304 { "pmevcntr5_el0", 0xDF45, true, true }, // 305 { "pmevcntr6_el0", 0xDF46, true, true }, // 306 { "pmevcntr7_el0", 0xDF47, true, true }, // 307 { "pmevcntr8_el0", 0xDF48, true, true }, // 308 { "pmevcntr9_el0", 0xDF49, true, true }, // 309 { "pmevcntr10_el0", 0xDF4A, true, true }, // 310 { "pmevcntr11_el0", 0xDF4B, true, true }, // 311 { "pmevcntr12_el0", 0xDF4C, true, true }, // 312 { "pmevcntr13_el0", 0xDF4D, true, true }, // 313 { "pmevcntr14_el0", 0xDF4E, true, true }, // 314 { "pmevcntr15_el0", 0xDF4F, true, true }, // 315 { "pmevcntr16_el0", 0xDF50, true, true }, // 316 { "pmevcntr17_el0", 0xDF51, true, true }, // 317 { "pmevcntr18_el0", 0xDF52, true, true }, // 318 { "pmevcntr19_el0", 0xDF53, true, true }, // 319 { "pmevcntr20_el0", 0xDF54, true, true }, // 320 { "pmevcntr21_el0", 0xDF55, true, true }, // 321 { "pmevcntr22_el0", 0xDF56, true, true }, // 322 { "pmevcntr23_el0", 0xDF57, true, true }, // 323 { "pmevcntr24_el0", 0xDF58, true, true }, // 324 { "pmevcntr25_el0", 0xDF59, true, true }, // 325 { "pmevcntr26_el0", 0xDF5A, true, true }, // 326 { "pmevcntr27_el0", 0xDF5B, true, true }, // 327 { "pmevcntr28_el0", 0xDF5C, true, true }, // 328 { "pmevcntr29_el0", 0xDF5D, true, true }, // 329 { "pmevcntr30_el0", 0xDF5E, true, true }, // 330 { "pmccfiltr_el0", 0xDF7F, true, true }, // 331 { "pmevtyper0_el0", 0xDF60, true, true }, // 332 { "pmevtyper1_el0", 0xDF61, true, true }, // 333 { "pmevtyper2_el0", 0xDF62, true, true }, // 334 { "pmevtyper3_el0", 0xDF63, true, true }, // 335 { "pmevtyper4_el0", 0xDF64, true, true }, // 336 { "pmevtyper5_el0", 0xDF65, true, true }, // 337 { "pmevtyper6_el0", 0xDF66, true, true }, // 338 { "pmevtyper7_el0", 0xDF67, true, true }, // 339 { "pmevtyper8_el0", 0xDF68, true, true }, // 340 { "pmevtyper9_el0", 0xDF69, true, true }, // 341 { "pmevtyper10_el0", 0xDF6A, true, true }, // 342 { "pmevtyper11_el0", 0xDF6B, true, true }, // 343 { "pmevtyper12_el0", 0xDF6C, true, true }, // 344 { "pmevtyper13_el0", 0xDF6D, true, true }, // 345 { "pmevtyper14_el0", 0xDF6E, true, true }, // 346 { "pmevtyper15_el0", 0xDF6F, true, true }, // 347 { "pmevtyper16_el0", 0xDF70, true, true }, // 348 { "pmevtyper17_el0", 0xDF71, true, true }, // 349 { "pmevtyper18_el0", 0xDF72, true, true }, // 350 { "pmevtyper19_el0", 0xDF73, true, true }, // 351 { "pmevtyper20_el0", 0xDF74, true, true }, // 352 { "pmevtyper21_el0", 0xDF75, true, true }, // 353 { "pmevtyper22_el0", 0xDF76, true, true }, // 354 { "pmevtyper23_el0", 0xDF77, true, true }, // 355 { "pmevtyper24_el0", 0xDF78, true, true }, // 356 { "pmevtyper25_el0", 0xDF79, true, true }, // 357 { "pmevtyper26_el0", 0xDF7A, true, true }, // 358 { "pmevtyper27_el0", 0xDF7B, true, true }, // 359 { "pmevtyper28_el0", 0xDF7C, true, true }, // 360 { "pmevtyper29_el0", 0xDF7D, true, true }, // 361 { "pmevtyper30_el0", 0xDF7E, true, true }, // 362 { "trcprgctlr", 0x8808, true, true }, // 363 { "trcprocselr", 0x8810, true, true }, // 364 { "trcconfigr", 0x8820, true, true }, // 365 { "trcauxctlr", 0x8830, true, true }, // 366 { "trceventctl0r", 0x8840, true, true }, // 367 { "trceventctl1r", 0x8848, true, true }, // 368 { "trcstallctlr", 0x8858, true, true }, // 369 { "trctsctlr", 0x8860, true, true }, // 370 { "trcsyncpr", 0x8868, true, true }, // 371 { "trcccctlr", 0x8870, true, true }, // 372 { "trcbbctlr", 0x8878, true, true }, // 373 { "trctraceidr", 0x8801, true, true }, // 374 { "trcqctlr", 0x8809, true, true }, // 375 { "trcvictlr", 0x8802, true, true }, // 376 { "trcviiectlr", 0x880A, true, true }, // 377 { "trcvissctlr", 0x8812, true, true }, // 378 { "trcvipcssctlr", 0x881A, true, true }, // 379 { "trcvdctlr", 0x8842, true, true }, // 380 { "trcvdsacctlr", 0x884A, true, true }, // 381 { "trcvdarcctlr", 0x8852, true, true }, // 382 { "trcseqevr0", 0x8804, true, true }, // 383 { "trcseqevr1", 0x880C, true, true }, // 384 { "trcseqevr2", 0x8814, true, true }, // 385 { "trcseqrstevr", 0x8834, true, true }, // 386 { "trcseqstr", 0x883C, true, true }, // 387 { "trcextinselr", 0x8844, true, true }, // 388 { "trccntrldvr0", 0x8805, true, true }, // 389 { "trccntrldvr1", 0x880D, true, true }, // 390 { "trccntrldvr2", 0x8815, true, true }, // 391 { "trccntrldvr3", 0x881D, true, true }, // 392 { "trccntctlr0", 0x8825, true, true }, // 393 { "trccntctlr1", 0x882D, true, true }, // 394 { "trccntctlr2", 0x8835, true, true }, // 395 { "trccntctlr3", 0x883D, true, true }, // 396 { "trccntvr0", 0x8845, true, true }, // 397 { "trccntvr1", 0x884D, true, true }, // 398 { "trccntvr2", 0x8855, true, true }, // 399 { "trccntvr3", 0x885D, true, true }, // 400 { "trcimspec0", 0x8807, true, true }, // 401 { "trcimspec1", 0x880F, true, true }, // 402 { "trcimspec2", 0x8817, true, true }, // 403 { "trcimspec3", 0x881F, true, true }, // 404 { "trcimspec4", 0x8827, true, true }, // 405 { "trcimspec5", 0x882F, true, true }, // 406 { "trcimspec6", 0x8837, true, true }, // 407 { "trcimspec7", 0x883F, true, true }, // 408 { "trcrsctlr2", 0x8890, true, true }, // 409 { "trcrsctlr3", 0x8898, true, true }, // 410 { "trcrsctlr4", 0x88A0, true, true }, // 411 { "trcrsctlr5", 0x88A8, true, true }, // 412 { "trcrsctlr6", 0x88B0, true, true }, // 413 { "trcrsctlr7", 0x88B8, true, true }, // 414 { "trcrsctlr8", 0x88C0, true, true }, // 415 { "trcrsctlr9", 0x88C8, true, true }, // 416 { "trcrsctlr10", 0x88D0, true, true }, // 417 { "trcrsctlr11", 0x88D8, true, true }, // 418 { "trcrsctlr12", 0x88E0, true, true }, // 419 { "trcrsctlr13", 0x88E8, true, true }, // 420 { "trcrsctlr14", 0x88F0, true, true }, // 421 { "trcrsctlr15", 0x88F8, true, true }, // 422 { "trcrsctlr16", 0x8881, true, true }, // 423 { "trcrsctlr17", 0x8889, true, true }, // 424 { "trcrsctlr18", 0x8891, true, true }, // 425 { "trcrsctlr19", 0x8899, true, true }, // 426 { "trcrsctlr20", 0x88A1, true, true }, // 427 { "trcrsctlr21", 0x88A9, true, true }, // 428 { "trcrsctlr22", 0x88B1, true, true }, // 429 { "trcrsctlr23", 0x88B9, true, true }, // 430 { "trcrsctlr24", 0x88C1, true, true }, // 431 { "trcrsctlr25", 0x88C9, true, true }, // 432 { "trcrsctlr26", 0x88D1, true, true }, // 433 { "trcrsctlr27", 0x88D9, true, true }, // 434 { "trcrsctlr28", 0x88E1, true, true }, // 435 { "trcrsctlr29", 0x88E9, true, true }, // 436 { "trcrsctlr30", 0x88F1, true, true }, // 437 { "trcrsctlr31", 0x88F9, true, true }, // 438 { "trcssccr0", 0x8882, true, true }, // 439 { "trcssccr1", 0x888A, true, true }, // 440 { "trcssccr2", 0x8892, true, true }, // 441 { "trcssccr3", 0x889A, true, true }, // 442 { "trcssccr4", 0x88A2, true, true }, // 443 { "trcssccr5", 0x88AA, true, true }, // 444 { "trcssccr6", 0x88B2, true, true }, // 445 { "trcssccr7", 0x88BA, true, true }, // 446 { "trcsscsr0", 0x88C2, true, true }, // 447 { "trcsscsr1", 0x88CA, true, true }, // 448 { "trcsscsr2", 0x88D2, true, true }, // 449 { "trcsscsr3", 0x88DA, true, true }, // 450 { "trcsscsr4", 0x88E2, true, true }, // 451 { "trcsscsr5", 0x88EA, true, true }, // 452 { "trcsscsr6", 0x88F2, true, true }, // 453 { "trcsscsr7", 0x88FA, true, true }, // 454 { "trcsspcicr0", 0x8883, true, true }, // 455 { "trcsspcicr1", 0x888B, true, true }, // 456 { "trcsspcicr2", 0x8893, true, true }, // 457 { "trcsspcicr3", 0x889B, true, true }, // 458 { "trcsspcicr4", 0x88A3, true, true }, // 459 { "trcsspcicr5", 0x88AB, true, true }, // 460 { "trcsspcicr6", 0x88B3, true, true }, // 461 { "trcsspcicr7", 0x88BB, true, true }, // 462 { "trcpdcr", 0x88A4, true, true }, // 463 { "trcacvr0", 0x8900, true, true }, // 464 { "trcacvr1", 0x8910, true, true }, // 465 { "trcacvr2", 0x8920, true, true }, // 466 { "trcacvr3", 0x8930, true, true }, // 467 { "trcacvr4", 0x8940, true, true }, // 468 { "trcacvr5", 0x8950, true, true }, // 469 { "trcacvr6", 0x8960, true, true }, // 470 { "trcacvr7", 0x8970, true, true }, // 471 { "trcacvr8", 0x8901, true, true }, // 472 { "trcacvr9", 0x8911, true, true }, // 473 { "trcacvr10", 0x8921, true, true }, // 474 { "trcacvr11", 0x8931, true, true }, // 475 { "trcacvr12", 0x8941, true, true }, // 476 { "trcacvr13", 0x8951, true, true }, // 477 { "trcacvr14", 0x8961, true, true }, // 478 { "trcacvr15", 0x8971, true, true }, // 479 { "trcacatr0", 0x8902, true, true }, // 480 { "trcacatr1", 0x8912, true, true }, // 481 { "trcacatr2", 0x8922, true, true }, // 482 { "trcacatr3", 0x8932, true, true }, // 483 { "trcacatr4", 0x8942, true, true }, // 484 { "trcacatr5", 0x8952, true, true }, // 485 { "trcacatr6", 0x8962, true, true }, // 486 { "trcacatr7", 0x8972, true, true }, // 487 { "trcacatr8", 0x8903, true, true }, // 488 { "trcacatr9", 0x8913, true, true }, // 489 { "trcacatr10", 0x8923, true, true }, // 490 { "trcacatr11", 0x8933, true, true }, // 491 { "trcacatr12", 0x8943, true, true }, // 492 { "trcacatr13", 0x8953, true, true }, // 493 { "trcacatr14", 0x8963, true, true }, // 494 { "trcacatr15", 0x8973, true, true }, // 495 { "trcdvcvr0", 0x8904, true, true }, // 496 { "trcdvcvr1", 0x8924, true, true }, // 497 { "trcdvcvr2", 0x8944, true, true }, // 498 { "trcdvcvr3", 0x8964, true, true }, // 499 { "trcdvcvr4", 0x8905, true, true }, // 500 { "trcdvcvr5", 0x8925, true, true }, // 501 { "trcdvcvr6", 0x8945, true, true }, // 502 { "trcdvcvr7", 0x8965, true, true }, // 503 { "trcdvcmr0", 0x8906, true, true }, // 504 { "trcdvcmr1", 0x8926, true, true }, // 505 { "trcdvcmr2", 0x8946, true, true }, // 506 { "trcdvcmr3", 0x8966, true, true }, // 507 { "trcdvcmr4", 0x8907, true, true }, // 508 { "trcdvcmr5", 0x8927, true, true }, // 509 { "trcdvcmr6", 0x8947, true, true }, // 510 { "trcdvcmr7", 0x8967, true, true }, // 511 { "trccidcvr0", 0x8980, true, true }, // 512 { "trccidcvr1", 0x8990, true, true }, // 513 { "trccidcvr2", 0x89A0, true, true }, // 514 { "trccidcvr3", 0x89B0, true, true }, // 515 { "trccidcvr4", 0x89C0, true, true }, // 516 { "trccidcvr5", 0x89D0, true, true }, // 517 { "trccidcvr6", 0x89E0, true, true }, // 518 { "trccidcvr7", 0x89F0, true, true }, // 519 { "trcvmidcvr0", 0x8981, true, true }, // 520 { "trcvmidcvr1", 0x8991, true, true }, // 521 { "trcvmidcvr2", 0x89A1, true, true }, // 522 { "trcvmidcvr3", 0x89B1, true, true }, // 523 { "trcvmidcvr4", 0x89C1, true, true }, // 524 { "trcvmidcvr5", 0x89D1, true, true }, // 525 { "trcvmidcvr6", 0x89E1, true, true }, // 526 { "trcvmidcvr7", 0x89F1, true, true }, // 527 { "trccidcctlr0", 0x8982, true, true }, // 528 { "trccidcctlr1", 0x898A, true, true }, // 529 { "trcvmidcctlr0", 0x8992, true, true }, // 530 { "trcvmidcctlr1", 0x899A, true, true }, // 531 { "trcitctrl", 0x8B84, true, true }, // 532 { "trcclaimset", 0x8BC6, true, true }, // 533 { "trcclaimclr", 0x8BCE, true, true }, // 534 { "icc_bpr1_el1", 0xC663, true, true }, // 535 { "icc_bpr0_el1", 0xC643, true, true }, // 536 { "icc_pmr_el1", 0xC230, true, true }, // 537 { "icc_ctlr_el1", 0xC664, true, true }, // 538 { "icc_ctlr_el3", 0xF664, true, true }, // 539 { "icc_sre_el1", 0xC665, true, true }, // 540 { "icc_sre_el2", 0xE64D, true, true }, // 541 { "icc_sre_el3", 0xF665, true, true }, // 542 { "icc_igrpen0_el1", 0xC666, true, true }, // 543 { "icc_igrpen1_el1", 0xC667, true, true }, // 544 { "icc_igrpen1_el3", 0xF667, true, true }, // 545 { "icc_seien_el1", 0xC668, true, true }, // 546 { "icc_ap0r0_el1", 0xC644, true, true }, // 547 { "icc_ap0r1_el1", 0xC645, true, true }, // 548 { "icc_ap0r2_el1", 0xC646, true, true }, // 549 { "icc_ap0r3_el1", 0xC647, true, true }, // 550 { "icc_ap1r0_el1", 0xC648, true, true }, // 551 { "icc_ap1r1_el1", 0xC649, true, true }, // 552 { "icc_ap1r2_el1", 0xC64A, true, true }, // 553 { "icc_ap1r3_el1", 0xC64B, true, true }, // 554 { "ich_ap0r0_el2", 0xE640, true, true }, // 555 { "ich_ap0r1_el2", 0xE641, true, true }, // 556 { "ich_ap0r2_el2", 0xE642, true, true }, // 557 { "ich_ap0r3_el2", 0xE643, true, true }, // 558 { "ich_ap1r0_el2", 0xE648, true, true }, // 559 { "ich_ap1r1_el2", 0xE649, true, true }, // 560 { "ich_ap1r2_el2", 0xE64A, true, true }, // 561 { "ich_ap1r3_el2", 0xE64B, true, true }, // 562 { "ich_hcr_el2", 0xE658, true, true }, // 563 { "ich_misr_el2", 0xE65A, true, true }, // 564 { "ich_vmcr_el2", 0xE65F, true, true }, // 565 { "ich_vseir_el2", 0xE64C, true, true }, // 566 { "ich_lr0_el2", 0xE660, true, true }, // 567 { "ich_lr1_el2", 0xE661, true, true }, // 568 { "ich_lr2_el2", 0xE662, true, true }, // 569 { "ich_lr3_el2", 0xE663, true, true }, // 570 { "ich_lr4_el2", 0xE664, true, true }, // 571 { "ich_lr5_el2", 0xE665, true, true }, // 572 { "ich_lr6_el2", 0xE666, true, true }, // 573 { "ich_lr7_el2", 0xE667, true, true }, // 574 { "ich_lr8_el2", 0xE668, true, true }, // 575 { "ich_lr9_el2", 0xE669, true, true }, // 576 { "ich_lr10_el2", 0xE66A, true, true }, // 577 { "ich_lr11_el2", 0xE66B, true, true }, // 578 { "ich_lr12_el2", 0xE66C, true, true }, // 579 { "ich_lr13_el2", 0xE66D, true, true }, // 580 { "ich_lr14_el2", 0xE66E, true, true }, // 581 { "ich_lr15_el2", 0xE66F, true, true }, // 582 { "pan", 0xC213, true, true }, // 583 { "lorsa_el1", 0xC520, true, true }, // 584 { "lorea_el1", 0xC521, true, true }, // 585 { "lorn_el1", 0xC522, true, true }, // 586 { "lorc_el1", 0xC523, true, true }, // 587 { "ttbr1_el2", 0xE101, true, true }, // 588 { "contextidr_el2", 0xE681, true, true }, // 589 { "cnthv_tval_el2", 0xE718, true, true }, // 590 { "cnthv_cval_el2", 0xE71A, true, true }, // 591 { "cnthv_ctl_el2", 0xE719, true, true }, // 592 { "sctlr_el12", 0xE880, true, true }, // 593 { "cpacr_el12", 0xE882, true, true }, // 594 { "ttbr0_el12", 0xE900, true, true }, // 595 { "ttbr1_el12", 0xE901, true, true }, // 596 { "tcr_el12", 0xE902, true, true }, // 597 { "afsr0_el12", 0xEA88, true, true }, // 598 { "afsr1_el12", 0xEA89, true, true }, // 599 { "esr_el12", 0xEA90, true, true }, // 600 { "far_el12", 0xEB00, true, true }, // 601 { "mair_el12", 0xED10, true, true }, // 602 { "amair_el12", 0xED18, true, true }, // 603 { "vbar_el12", 0xEE00, true, true }, // 604 { "contextidr_el12", 0xEE81, true, true }, // 605 { "cntkctl_el12", 0xEF08, true, true }, // 606 { "cntp_tval_el02", 0xEF10, true, true }, // 607 { "cntp_ctl_el02", 0xEF11, true, true }, // 608 { "cntp_cval_el02", 0xEF12, true, true }, // 609 { "cntv_tval_el02", 0xEF18, true, true }, // 610 { "cntv_ctl_el02", 0xEF19, true, true }, // 611 { "cntv_cval_el02", 0xEF1A, true, true }, // 612 { "spsr_el12", 0xEA00, true, true }, // 613 { "elr_el12", 0xEA01, true, true }, // 614 { "uao", 0xC214, true, true }, // 615 { "pmblimitr_el1", 0xC4D0, true, true }, // 616 { "pmbptr_el1", 0xC4D1, true, true }, // 617 { "pmbsr_el1", 0xC4D3, true, true }, // 618 { "pmbidr_el1", 0xC4D7, true, true }, // 619 { "pmscr_el2", 0xE4C8, true, true }, // 620 { "pmscr_el12", 0xECC8, true, true }, // 621 { "pmscr_el1", 0xC4C8, true, true }, // 622 { "pmsicr_el1", 0xC4CA, true, true }, // 623 { "pmsirr_el1", 0xC4CB, true, true }, // 624 { "pmsfcr_el1", 0xC4CC, true, true }, // 625 { "pmsevfr_el1", 0xC4CD, true, true }, // 626 { "pmslatfr_el1", 0xC4CE, true, true }, // 627 { "pmsidr_el1", 0xC4CF, true, true }, // 628 { "errselr_el1", 0xC299, true, true }, // 629 { "erxctlr_el1", 0xC2A1, true, true }, // 630 { "erxstatus_el1", 0xC2A2, true, true }, // 631 { "erxaddr_el1", 0xC2A3, true, true }, // 632 { "erxmisc0_el1", 0xC2A8, true, true }, // 633 { "erxmisc1_el1", 0xC2A9, true, true }, // 634 { "disr_el1", 0xC609, true, true }, // 635 { "vdisr_el2", 0xE609, true, true }, // 636 { "vsesr_el2", 0xE293, true, true }, // 637 { "apiakeylo_el1", 0xC108, true, true }, // 638 { "apiakeyhi_el1", 0xC109, true, true }, // 639 { "apibkeylo_el1", 0xC10A, true, true }, // 640 { "apibkeyhi_el1", 0xC10B, true, true }, // 641 { "apdakeylo_el1", 0xC110, true, true }, // 642 { "apdakeyhi_el1", 0xC111, true, true }, // 643 { "apdbkeylo_el1", 0xC112, true, true }, // 644 { "apdbkeyhi_el1", 0xC113, true, true }, // 645 { "apgakeylo_el1", 0xC118, true, true }, // 646 { "apgakeyhi_el1", 0xC119, true, true }, // 647 { "vstcr_el2", 0xE132, true, true }, // 648 { "vsttbr_el2", 0xE130, true, true }, // 649 { "cnthvs_tval_el2", 0xE720, true, true }, // 650 { "cnthvs_cval_el2", 0xE722, true, true }, // 651 { "cnthvs_ctl_el2", 0xE721, true, true }, // 652 { "cnthps_tval_el2", 0xE728, true, true }, // 653 { "cnthps_cval_el2", 0xE72A, true, true }, // 654 { "cnthps_ctl_el2", 0xE729, true, true }, // 655 { "sder32_el2", 0xE099, true, true }, // 656 { "erxpfgctl_el1", 0xC2A5, true, true }, // 657 { "erxpfgcdn_el1", 0xC2A6, true, true }, // 658 { "erxts_el1", 0xC2AF, true, true }, // 659 { "erxmisc2_el1", 0xC2AA, true, true }, // 660 { "erxmisc3_el1", 0xC2AB, true, true }, // 661 { "erxpfgf_el1", 0xC2A4, true, false }, // 662 { "mpam0_el1", 0xC529, true, true }, // 663 { "mpam1_el1", 0xC528, true, true }, // 664 { "mpam2_el2", 0xE528, true, true }, // 665 { "mpam3_el3", 0xF528, true, true }, // 666 { "mpam1_el12", 0xED28, true, true }, // 667 { "mpamhcr_el2", 0xE520, true, true }, // 668 { "mpamvpmv_el2", 0xE521, true, true }, // 669 { "mpamvpm0_el2", 0xE530, true, true }, // 670 { "mpamvpm1_el2", 0xE531, true, true }, // 671 { "mpamvpm2_el2", 0xE532, true, true }, // 672 { "mpamvpm3_el2", 0xE533, true, true }, // 673 { "mpamvpm4_el2", 0xE534, true, true }, // 674 { "mpamvpm5_el2", 0xE535, true, true }, // 675 { "mpamvpm6_el2", 0xE536, true, true }, // 676 { "mpamvpm7_el2", 0xE537, true, true }, // 677 { "mpamidr_el1", 0xC524, true, false }, // 678 { "amcr_el0", 0xDE90, true, true }, // 679 { "amcfgr_el0", 0xDE91, true, false }, // 680 { "amcgcr_el0", 0xDE92, true, false }, // 681 { "amuserenr_el0", 0xDE93, true, true }, // 682 { "amcntenclr0_el0", 0xDE94, true, true }, // 683 { "amcntenset0_el0", 0xDE95, true, true }, // 684 { "amevcntr00_el0", 0xDEA0, true, true }, // 685 { "amevcntr01_el0", 0xDEA1, true, true }, // 686 { "amevcntr02_el0", 0xDEA2, true, true }, // 687 { "amevcntr03_el0", 0xDEA3, true, true }, // 688 { "amevtyper00_el0", 0xDEB0, true, false }, // 689 { "amevtyper01_el0", 0xDEB1, true, false }, // 690 { "amevtyper02_el0", 0xDEB2, true, false }, // 691 { "amevtyper03_el0", 0xDEB3, true, false }, // 692 { "amcntenclr1_el0", 0xDE98, true, true }, // 693 { "amcntenset1_el0", 0xDE99, true, true }, // 694 { "amevcntr10_el0", 0xDEE0, true, true }, // 695 { "amevcntr11_el0", 0xDEE1, true, true }, // 696 { "amevcntr12_el0", 0xDEE2, true, true }, // 697 { "amevcntr13_el0", 0xDEE3, true, true }, // 698 { "amevcntr14_el0", 0xDEE4, true, true }, // 699 { "amevcntr15_el0", 0xDEE5, true, true }, // 700 { "amevcntr16_el0", 0xDEE6, true, true }, // 701 { "amevcntr17_el0", 0xDEE7, true, true }, // 702 { "amevcntr18_el0", 0xDEE8, true, true }, // 703 { "amevcntr19_el0", 0xDEE9, true, true }, // 704 { "amevcntr110_el0", 0xDEEA, true, true }, // 705 { "amevcntr111_el0", 0xDEEB, true, true }, // 706 { "amevcntr112_el0", 0xDEEC, true, true }, // 707 { "amevcntr113_el0", 0xDEED, true, true }, // 708 { "amevcntr114_el0", 0xDEEE, true, true }, // 709 { "amevcntr115_el0", 0xDEEF, true, true }, // 710 { "amevtyper10_el0", 0xDEF0, true, true }, // 711 { "amevtyper11_el0", 0xDEF1, true, true }, // 712 { "amevtyper12_el0", 0xDEF2, true, true }, // 713 { "amevtyper13_el0", 0xDEF3, true, true }, // 714 { "amevtyper14_el0", 0xDEF4, true, true }, // 715 { "amevtyper15_el0", 0xDEF5, true, true }, // 716 { "amevtyper16_el0", 0xDEF6, true, true }, // 717 { "amevtyper17_el0", 0xDEF7, true, true }, // 718 { "amevtyper18_el0", 0xDEF8, true, true }, // 719 { "amevtyper19_el0", 0xDEF9, true, true }, // 720 { "amevtyper110_el0", 0xDEFA, true, true }, // 721 { "amevtyper111_el0", 0xDEFB, true, true }, // 722 { "amevtyper112_el0", 0xDEFC, true, true }, // 723 { "amevtyper113_el0", 0xDEFD, true, true }, // 724 { "amevtyper114_el0", 0xDEFE, true, true }, // 725 { "amevtyper115_el0", 0xDEFF, true, true }, // 726 { "trfcr_el1", 0xC091, true, true }, // 727 { "trfcr_el2", 0xE091, true, true }, // 728 { "trfcr_el12", 0xE891, true, true }, // 729 { "dit", 0xDA15, true, true }, // 730 { "vncr_el2", 0xE110, true, true }, // 731 { "zcr_el1", 0xC090, true, true }, // 732 { "zcr_el2", 0xE090, true, true }, // 733 { "zcr_el3", 0xF090, true, true }, // 734 { "zcr_el12", 0xE890, true, true }, // 735 { "cpm_ioacc_ctl_el3", 0xFF90, true, true }, // 736 }; const SysReg *lookupSysRegByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x8002, 111 }, { 0x8004, 119 }, { 0x8005, 135 }, { 0x8006, 151 }, { 0x8007, 167 }, { 0x800C, 120 }, { 0x800D, 136 }, { 0x800E, 152 }, { 0x800F, 168 }, { 0x8010, 114 }, { 0x8012, 115 }, { 0x8014, 121 }, { 0x8015, 137 }, { 0x8016, 153 }, { 0x8017, 169 }, { 0x801A, 112 }, { 0x801C, 122 }, { 0x801D, 138 }, { 0x801E, 154 }, { 0x801F, 170 }, { 0x8024, 123 }, { 0x8025, 139 }, { 0x8026, 155 }, { 0x8027, 171 }, { 0x802C, 124 }, { 0x802D, 140 }, { 0x802E, 156 }, { 0x802F, 172 }, { 0x8032, 117 }, { 0x8034, 125 }, { 0x8035, 141 }, { 0x8036, 157 }, { 0x8037, 173 }, { 0x803C, 126 }, { 0x803D, 142 }, { 0x803E, 158 }, { 0x803F, 174 }, { 0x8044, 127 }, { 0x8045, 143 }, { 0x8046, 159 }, { 0x8047, 175 }, { 0x804C, 128 }, { 0x804D, 144 }, { 0x804E, 160 }, { 0x804F, 176 }, { 0x8054, 129 }, { 0x8055, 145 }, { 0x8056, 161 }, { 0x8057, 177 }, { 0x805C, 130 }, { 0x805D, 146 }, { 0x805E, 162 }, { 0x805F, 178 }, { 0x8064, 131 }, { 0x8065, 147 }, { 0x8066, 163 }, { 0x8067, 179 }, { 0x806C, 132 }, { 0x806D, 148 }, { 0x806E, 164 }, { 0x806F, 180 }, { 0x8074, 133 }, { 0x8075, 149 }, { 0x8076, 165 }, { 0x8077, 181 }, { 0x807C, 134 }, { 0x807D, 150 }, { 0x807E, 166 }, { 0x807F, 182 }, { 0x8080, 2 }, { 0x8084, 101 }, { 0x808C, 3 }, { 0x809C, 184 }, { 0x80A4, 185 }, { 0x83C6, 186 }, { 0x83CE, 187 }, { 0x83F6, 4 }, { 0x8801, 374 }, { 0x8802, 376 }, { 0x8804, 383 }, { 0x8805, 389 }, { 0x8806, 53 }, { 0x8807, 401 }, { 0x8808, 363 }, { 0x8809, 375 }, { 0x880A, 377 }, { 0x880C, 384 }, { 0x880D, 390 }, { 0x880E, 54 }, { 0x880F, 402 }, { 0x8810, 364 }, { 0x8812, 378 }, { 0x8814, 385 }, { 0x8815, 391 }, { 0x8816, 55 }, { 0x8817, 403 }, { 0x8818, 52 }, { 0x881A, 379 }, { 0x881D, 392 }, { 0x881E, 56 }, { 0x881F, 404 }, { 0x8820, 365 }, { 0x8825, 393 }, { 0x8826, 57 }, { 0x8827, 405 }, { 0x882D, 394 }, { 0x882E, 58 }, { 0x882F, 406 }, { 0x8830, 366 }, { 0x8834, 386 }, { 0x8835, 395 }, { 0x8837, 407 }, { 0x883C, 387 }, { 0x883D, 396 }, { 0x883F, 408 }, { 0x8840, 367 }, { 0x8842, 380 }, { 0x8844, 388 }, { 0x8845, 397 }, { 0x8847, 59 }, { 0x8848, 368 }, { 0x884A, 381 }, { 0x884D, 398 }, { 0x884F, 60 }, { 0x8852, 382 }, { 0x8855, 399 }, { 0x8857, 61 }, { 0x8858, 369 }, { 0x885D, 400 }, { 0x885F, 62 }, { 0x8860, 370 }, { 0x8867, 63 }, { 0x8868, 371 }, { 0x886F, 64 }, { 0x8870, 372 }, { 0x8877, 65 }, { 0x8878, 373 }, { 0x887F, 66 }, { 0x8881, 423 }, { 0x8882, 439 }, { 0x8883, 455 }, { 0x8884, 103 }, { 0x8889, 424 }, { 0x888A, 440 }, { 0x888B, 456 }, { 0x888C, 67 }, { 0x8890, 409 }, { 0x8891, 425 }, { 0x8892, 441 }, { 0x8893, 457 }, { 0x8898, 410 }, { 0x8899, 426 }, { 0x889A, 442 }, { 0x889B, 458 }, { 0x88A0, 411 }, { 0x88A1, 427 }, { 0x88A2, 443 }, { 0x88A3, 459 }, { 0x88A4, 463 }, { 0x88A8, 412 }, { 0x88A9, 428 }, { 0x88AA, 444 }, { 0x88AB, 460 }, { 0x88AC, 68 }, { 0x88B0, 413 }, { 0x88B1, 429 }, { 0x88B2, 445 }, { 0x88B3, 461 }, { 0x88B8, 414 }, { 0x88B9, 430 }, { 0x88BA, 446 }, { 0x88BB, 462 }, { 0x88C0, 415 }, { 0x88C1, 431 }, { 0x88C2, 447 }, { 0x88C8, 416 }, { 0x88C9, 432 }, { 0x88CA, 448 }, { 0x88D0, 417 }, { 0x88D1, 433 }, { 0x88D2, 449 }, { 0x88D8, 418 }, { 0x88D9, 434 }, { 0x88DA, 450 }, { 0x88E0, 419 }, { 0x88E1, 435 }, { 0x88E2, 451 }, { 0x88E8, 420 }, { 0x88E9, 436 }, { 0x88EA, 452 }, { 0x88F0, 421 }, { 0x88F1, 437 }, { 0x88F2, 453 }, { 0x88F8, 422 }, { 0x88F9, 438 }, { 0x88FA, 454 }, { 0x8900, 464 }, { 0x8901, 472 }, { 0x8902, 480 }, { 0x8903, 488 }, { 0x8904, 496 }, { 0x8905, 500 }, { 0x8906, 504 }, { 0x8907, 508 }, { 0x8910, 465 }, { 0x8911, 473 }, { 0x8912, 481 }, { 0x8913, 489 }, { 0x8920, 466 }, { 0x8921, 474 }, { 0x8922, 482 }, { 0x8923, 490 }, { 0x8924, 497 }, { 0x8925, 501 }, { 0x8926, 505 }, { 0x8927, 509 }, { 0x8930, 467 }, { 0x8931, 475 }, { 0x8932, 483 }, { 0x8933, 491 }, { 0x8940, 468 }, { 0x8941, 476 }, { 0x8942, 484 }, { 0x8943, 492 }, { 0x8944, 498 }, { 0x8945, 502 }, { 0x8946, 506 }, { 0x8947, 510 }, { 0x8950, 469 }, { 0x8951, 477 }, { 0x8952, 485 }, { 0x8953, 493 }, { 0x8960, 470 }, { 0x8961, 478 }, { 0x8962, 486 }, { 0x8963, 494 }, { 0x8964, 499 }, { 0x8965, 503 }, { 0x8966, 507 }, { 0x8967, 511 }, { 0x8970, 471 }, { 0x8971, 479 }, { 0x8972, 487 }, { 0x8973, 495 }, { 0x8980, 512 }, { 0x8981, 520 }, { 0x8982, 528 }, { 0x898A, 529 }, { 0x8990, 513 }, { 0x8991, 521 }, { 0x8992, 530 }, { 0x899A, 531 }, { 0x89A0, 514 }, { 0x89A1, 522 }, { 0x89B0, 515 }, { 0x89B1, 523 }, { 0x89C0, 516 }, { 0x89C1, 524 }, { 0x89D0, 517 }, { 0x89D1, 525 }, { 0x89E0, 518 }, { 0x89E1, 526 }, { 0x89F0, 519 }, { 0x89F1, 527 }, { 0x8B84, 532 }, { 0x8B97, 74 }, { 0x8B9F, 75 }, { 0x8BA7, 76 }, { 0x8BAF, 77 }, { 0x8BB7, 78 }, { 0x8BBF, 79 }, { 0x8BC6, 533 }, { 0x8BC7, 80 }, { 0x8BCE, 534 }, { 0x8BCF, 81 }, { 0x8BD6, 69 }, { 0x8BD7, 82 }, { 0x8BDE, 70 }, { 0x8BDF, 83 }, { 0x8BE6, 104 }, { 0x8BE7, 84 }, { 0x8BEE, 71 }, { 0x8BEF, 85 }, { 0x8BF6, 72 }, { 0x8BF7, 86 }, { 0x8BFE, 73 }, { 0x8BFF, 87 }, { 0x9000, 113 }, { 0x9080, 183 }, { 0x9808, 0 }, { 0x9820, 116 }, { 0x9828, 1 }, { 0x9828, 100 }, { 0xA038, 118 }, { 0xC000, 7 }, { 0xC005, 12 }, { 0xC006, 13 }, { 0xC008, 16 }, { 0xC009, 17 }, { 0xC00A, 18 }, { 0xC00B, 19 }, { 0xC00C, 20 }, { 0xC00D, 21 }, { 0xC00E, 22 }, { 0xC00F, 23 }, { 0xC010, 24 }, { 0xC011, 25 }, { 0xC012, 26 }, { 0xC013, 27 }, { 0xC014, 28 }, { 0xC015, 29 }, { 0xC016, 51 }, { 0xC017, 30 }, { 0xC018, 42 }, { 0xC019, 43 }, { 0xC01A, 44 }, { 0xC020, 31 }, { 0xC021, 32 }, { 0xC024, 96 }, { 0xC028, 33 }, { 0xC029, 34 }, { 0xC02C, 35 }, { 0xC02D, 36 }, { 0xC030, 37 }, { 0xC031, 38 }, { 0xC038, 39 }, { 0xC039, 40 }, { 0xC03A, 41 }, { 0xC080, 192 }, { 0xC081, 195 }, { 0xC082, 191 }, { 0xC090, 732 }, { 0xC091, 727 }, { 0xC100, 207 }, { 0xC101, 210 }, { 0xC102, 211 }, { 0xC108, 638 }, { 0xC109, 639 }, { 0xC10A, 640 }, { 0xC10B, 641 }, { 0xC110, 642 }, { 0xC111, 643 }, { 0xC112, 644 }, { 0xC113, 645 }, { 0xC118, 646 }, { 0xC119, 647 }, { 0xC200, 217 }, { 0xC201, 220 }, { 0xC208, 223 }, { 0xC210, 226 }, { 0xC212, 229 }, { 0xC213, 583 }, { 0xC214, 615 }, { 0xC230, 537 }, { 0xC288, 239 }, { 0xC289, 242 }, { 0xC290, 245 }, { 0xC298, 98 }, { 0xC299, 629 }, { 0xC2A0, 99 }, { 0xC2A1, 630 }, { 0xC2A2, 631 }, { 0xC2A3, 632 }, { 0xC2A4, 662 }, { 0xC2A5, 657 }, { 0xC2A6, 658 }, { 0xC2A8, 633 }, { 0xC2A9, 634 }, { 0xC2AA, 660 }, { 0xC2AB, 661 }, { 0xC2AF, 659 }, { 0xC300, 249 }, { 0xC3A0, 253 }, { 0xC4C8, 622 }, { 0xC4CA, 623 }, { 0xC4CB, 624 }, { 0xC4CC, 625 }, { 0xC4CD, 626 }, { 0xC4CE, 627 }, { 0xC4CF, 628 }, { 0xC4D0, 616 }, { 0xC4D1, 617 }, { 0xC4D3, 618 }, { 0xC4D7, 619 }, { 0xC4F1, 263 }, { 0xC4F2, 264 }, { 0xC510, 266 }, { 0xC518, 269 }, { 0xC520, 584 }, { 0xC521, 585 }, { 0xC522, 586 }, { 0xC523, 587 }, { 0xC524, 678 }, { 0xC527, 97 }, { 0xC528, 664 }, { 0xC529, 663 }, { 0xC600, 272 }, { 0xC601, 45 }, { 0xC602, 275 }, { 0xC608, 48 }, { 0xC609, 635 }, { 0xC640, 89 }, { 0xC641, 106 }, { 0xC642, 91 }, { 0xC643, 536 }, { 0xC644, 547 }, { 0xC645, 548 }, { 0xC646, 549 }, { 0xC647, 550 }, { 0xC648, 551 }, { 0xC649, 552 }, { 0xC64A, 553 }, { 0xC64B, 554 }, { 0xC659, 107 }, { 0xC65B, 92 }, { 0xC65D, 108 }, { 0xC65E, 109 }, { 0xC65F, 110 }, { 0xC660, 88 }, { 0xC661, 105 }, { 0xC662, 90 }, { 0xC663, 535 }, { 0xC664, 538 }, { 0xC665, 540 }, { 0xC666, 543 }, { 0xC667, 544 }, { 0xC668, 546 }, { 0xC681, 278 }, { 0xC684, 283 }, { 0xC708, 286 }, { 0xC800, 8 }, { 0xC801, 10 }, { 0xC802, 9 }, { 0xC807, 14 }, { 0xD000, 188 }, { 0xD801, 11 }, { 0xD807, 15 }, { 0xDA10, 227 }, { 0xDA11, 228 }, { 0xDA15, 730 }, { 0xDA20, 234 }, { 0xDA21, 235 }, { 0xDA28, 236 }, { 0xDA29, 237 }, { 0xDCE0, 254 }, { 0xDCE1, 255 }, { 0xDCE2, 256 }, { 0xDCE3, 257 }, { 0xDCE4, 102 }, { 0xDCE5, 258 }, { 0xDCE6, 5 }, { 0xDCE7, 6 }, { 0xDCE8, 259 }, { 0xDCE9, 260 }, { 0xDCEA, 261 }, { 0xDCF0, 262 }, { 0xDCF3, 265 }, { 0xDE82, 279 }, { 0xDE83, 282 }, { 0xDE90, 679 }, { 0xDE91, 680 }, { 0xDE92, 681 }, { 0xDE93, 682 }, { 0xDE94, 683 }, { 0xDE95, 684 }, { 0xDE98, 693 }, { 0xDE99, 694 }, { 0xDEA0, 685 }, { 0xDEA1, 686 }, { 0xDEA2, 687 }, { 0xDEA3, 688 }, { 0xDEB0, 689 }, { 0xDEB1, 690 }, { 0xDEB2, 691 }, { 0xDEB3, 692 }, { 0xDEE0, 695 }, { 0xDEE1, 696 }, { 0xDEE2, 697 }, { 0xDEE3, 698 }, { 0xDEE4, 699 }, { 0xDEE5, 700 }, { 0xDEE6, 701 }, { 0xDEE7, 702 }, { 0xDEE8, 703 }, { 0xDEE9, 704 }, { 0xDEEA, 705 }, { 0xDEEB, 706 }, { 0xDEEC, 707 }, { 0xDEED, 708 }, { 0xDEEE, 709 }, { 0xDEEF, 710 }, { 0xDEF0, 711 }, { 0xDEF1, 712 }, { 0xDEF2, 713 }, { 0xDEF3, 714 }, { 0xDEF4, 715 }, { 0xDEF5, 716 }, { 0xDEF6, 717 }, { 0xDEF7, 718 }, { 0xDEF8, 719 }, { 0xDEF9, 720 }, { 0xDEFA, 721 }, { 0xDEFB, 722 }, { 0xDEFC, 723 }, { 0xDEFD, 724 }, { 0xDEFE, 725 }, { 0xDEFF, 726 }, { 0xDF00, 284 }, { 0xDF01, 49 }, { 0xDF02, 50 }, { 0xDF10, 288 }, { 0xDF11, 291 }, { 0xDF12, 294 }, { 0xDF18, 297 }, { 0xDF19, 298 }, { 0xDF1A, 299 }, { 0xDF40, 300 }, { 0xDF41, 301 }, { 0xDF42, 302 }, { 0xDF43, 303 }, { 0xDF44, 304 }, { 0xDF45, 305 }, { 0xDF46, 306 }, { 0xDF47, 307 }, { 0xDF48, 308 }, { 0xDF49, 309 }, { 0xDF4A, 310 }, { 0xDF4B, 311 }, { 0xDF4C, 312 }, { 0xDF4D, 313 }, { 0xDF4E, 314 }, { 0xDF4F, 315 }, { 0xDF50, 316 }, { 0xDF51, 317 }, { 0xDF52, 318 }, { 0xDF53, 319 }, { 0xDF54, 320 }, { 0xDF55, 321 }, { 0xDF56, 322 }, { 0xDF57, 323 }, { 0xDF58, 324 }, { 0xDF59, 325 }, { 0xDF5A, 326 }, { 0xDF5B, 327 }, { 0xDF5C, 328 }, { 0xDF5D, 329 }, { 0xDF5E, 330 }, { 0xDF60, 332 }, { 0xDF61, 333 }, { 0xDF62, 334 }, { 0xDF63, 335 }, { 0xDF64, 336 }, { 0xDF65, 337 }, { 0xDF66, 338 }, { 0xDF67, 339 }, { 0xDF68, 340 }, { 0xDF69, 341 }, { 0xDF6A, 342 }, { 0xDF6B, 343 }, { 0xDF6C, 344 }, { 0xDF6D, 345 }, { 0xDF6E, 346 }, { 0xDF6F, 347 }, { 0xDF70, 348 }, { 0xDF71, 349 }, { 0xDF72, 350 }, { 0xDF73, 351 }, { 0xDF74, 352 }, { 0xDF75, 353 }, { 0xDF76, 354 }, { 0xDF77, 355 }, { 0xDF78, 356 }, { 0xDF79, 357 }, { 0xDF7A, 358 }, { 0xDF7B, 359 }, { 0xDF7C, 360 }, { 0xDF7D, 361 }, { 0xDF7E, 362 }, { 0xDF7F, 331 }, { 0xE000, 189 }, { 0xE005, 190 }, { 0xE080, 193 }, { 0xE081, 196 }, { 0xE088, 198 }, { 0xE089, 200 }, { 0xE08A, 202 }, { 0xE08B, 204 }, { 0xE08F, 205 }, { 0xE090, 733 }, { 0xE091, 728 }, { 0xE099, 656 }, { 0xE100, 208 }, { 0xE101, 588 }, { 0xE102, 212 }, { 0xE108, 214 }, { 0xE10A, 215 }, { 0xE110, 731 }, { 0xE130, 649 }, { 0xE132, 648 }, { 0xE180, 216 }, { 0xE200, 218 }, { 0xE201, 221 }, { 0xE208, 224 }, { 0xE218, 230 }, { 0xE219, 231 }, { 0xE21A, 232 }, { 0xE21B, 233 }, { 0xE281, 238 }, { 0xE288, 240 }, { 0xE289, 243 }, { 0xE290, 246 }, { 0xE293, 637 }, { 0xE298, 248 }, { 0xE300, 250 }, { 0xE304, 252 }, { 0xE4C8, 620 }, { 0xE510, 267 }, { 0xE518, 270 }, { 0xE520, 668 }, { 0xE521, 669 }, { 0xE528, 665 }, { 0xE530, 670 }, { 0xE531, 671 }, { 0xE532, 672 }, { 0xE533, 673 }, { 0xE534, 674 }, { 0xE535, 675 }, { 0xE536, 676 }, { 0xE537, 677 }, { 0xE600, 273 }, { 0xE601, 46 }, { 0xE602, 276 }, { 0xE609, 636 }, { 0xE640, 555 }, { 0xE641, 556 }, { 0xE642, 557 }, { 0xE643, 558 }, { 0xE648, 559 }, { 0xE649, 560 }, { 0xE64A, 561 }, { 0xE64B, 562 }, { 0xE64C, 566 }, { 0xE64D, 541 }, { 0xE658, 563 }, { 0xE659, 93 }, { 0xE65A, 564 }, { 0xE65B, 94 }, { 0xE65D, 95 }, { 0xE65F, 565 }, { 0xE660, 567 }, { 0xE661, 568 }, { 0xE662, 569 }, { 0xE663, 570 }, { 0xE664, 571 }, { 0xE665, 572 }, { 0xE666, 573 }, { 0xE667, 574 }, { 0xE668, 575 }, { 0xE669, 576 }, { 0xE66A, 577 }, { 0xE66B, 578 }, { 0xE66C, 579 }, { 0xE66D, 580 }, { 0xE66E, 581 }, { 0xE66F, 582 }, { 0xE681, 589 }, { 0xE682, 280 }, { 0xE703, 285 }, { 0xE708, 287 }, { 0xE710, 289 }, { 0xE711, 292 }, { 0xE712, 295 }, { 0xE718, 590 }, { 0xE719, 592 }, { 0xE71A, 591 }, { 0xE720, 650 }, { 0xE721, 652 }, { 0xE722, 651 }, { 0xE728, 653 }, { 0xE729, 655 }, { 0xE72A, 654 }, { 0xE880, 593 }, { 0xE882, 594 }, { 0xE890, 735 }, { 0xE891, 729 }, { 0xE900, 595 }, { 0xE901, 596 }, { 0xE902, 597 }, { 0xEA00, 613 }, { 0xEA01, 614 }, { 0xEA88, 598 }, { 0xEA89, 599 }, { 0xEA90, 600 }, { 0xEB00, 601 }, { 0xECC8, 621 }, { 0xED10, 602 }, { 0xED18, 603 }, { 0xED28, 667 }, { 0xEE00, 604 }, { 0xEE81, 605 }, { 0xEF08, 606 }, { 0xEF10, 607 }, { 0xEF11, 608 }, { 0xEF12, 609 }, { 0xEF18, 610 }, { 0xEF19, 611 }, { 0xEF1A, 612 }, { 0xF080, 194 }, { 0xF081, 197 }, { 0xF088, 199 }, { 0xF089, 201 }, { 0xF08A, 203 }, { 0xF090, 734 }, { 0xF099, 206 }, { 0xF100, 209 }, { 0xF102, 213 }, { 0xF200, 219 }, { 0xF201, 222 }, { 0xF208, 225 }, { 0xF288, 241 }, { 0xF289, 244 }, { 0xF290, 247 }, { 0xF300, 251 }, { 0xF510, 268 }, { 0xF518, 271 }, { 0xF528, 666 }, { 0xF600, 274 }, { 0xF601, 47 }, { 0xF602, 277 }, { 0xF664, 539 }, { 0xF665, 542 }, { 0xF667, 545 }, { 0xF682, 281 }, { 0xFF10, 290 }, { 0xFF11, 293 }, { 0xFF12, 296 }, { 0xFF90, 736 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &SysRegsList[Index[i].index]; } static const PState PStatesList[] = { { "spsel", 0x5 }, // 0 { "daifset", 0x1E }, // 1 { "daifclr", 0x1F }, // 2 { "pan", 0x4 }, // 3 { "uao", 0x3 }, // 4 { "dit", 0x1A }, // 5 }; const PState *lookupPStateByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x3, 4 }, { 0x4, 3 }, { 0x5, 0 }, { 0x1A, 5 }, { 0x1E, 1 }, { 0x1F, 2 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &PStatesList[Index[i].index]; } static const SVEPREDPAT SVEPREDPATsList[] = { { "pow2", 0x0 }, // 0 { "vl1", 0x1 }, // 1 { "vl2", 0x2 }, // 2 { "vl3", 0x3 }, // 3 { "vl4", 0x4 }, // 4 { "vl5", 0x5 }, // 5 { "vl6", 0x6 }, // 6 { "vl7", 0x7 }, // 7 { "vl8", 0x8 }, // 8 { "vl16", 0x9 }, // 9 { "vl32", 0xa }, // 10 { "vl64", 0xb }, // 11 { "vl128", 0xc }, // 12 { "vl256", 0xd }, // 13 { "mul4", 0x1d }, // 14 { "mul3", 0x1e }, // 15 { "all", 0x1f }, // 16 }; const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x0, 0 }, { 0x1, 1 }, { 0x2, 2 }, { 0x3, 3 }, { 0x4, 4 }, { 0x5, 5 }, { 0x6, 6 }, { 0x7, 7 }, { 0x8, 8 }, { 0x9, 9 }, { 0xA, 10 }, { 0xB, 11 }, { 0xC, 12 }, { 0xD, 13 }, { 0x1D, 14 }, { 0x1E, 15 }, { 0x1F, 16 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &SVEPREDPATsList[Index[i].index]; } static const ExactFPImm ExactFPImmsList[] = { { "zero", 0x0, "0.0" }, // 0 { "half", 0x1, "0.5" }, // 1 { "one", 0x2, "1.0" }, // 2 { "two", 0x3, "2.0" }, // 3 }; const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding) { static const struct IndexType Index[] = { { 0x0, 0 }, { 0x1, 1 }, { 0x2, 2 }, { 0x3, 3 }, }; if (Encoding >= ARR_SIZE(ExactFPImmsList)) return NULL; else return &ExactFPImmsList[Index[Encoding].index]; } capstone-sys-0.15.0/capstone/arch/AArch64/AArch64GenSystemOperands_enum.inc000064400000000000000000000007100072674642500244500ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ enum PStateValues { AArch64PState_SPSel = 5, AArch64PState_DAIFSet = 30, AArch64PState_DAIFClr = 31, AArch64PState_PAN = 4, AArch64PState_UAO = 3, AArch64PState_DIT = 26, }; enum ExactFPImmValues { AArch64ExactFPImm_zero = 0, AArch64ExactFPImm_half = 1, AArch64ExactFPImm_one = 2, AArch64ExactFPImm_two = 3, }; capstone-sys-0.15.0/capstone/arch/AArch64/AArch64InstPrinter.c000064400000000000000000002377440072674642500217670ustar 00000000000000//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an AArch64 MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2016 */ #ifdef CAPSTONE_HAS_ARM64 #include #include #include #include "AArch64InstPrinter.h" #include "AArch64Disassembler.h" #include "AArch64BaseInfo.h" #include "../../utils.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" #include "AArch64Mapping.h" #include "AArch64AddressingModes.h" #define GET_REGINFO_ENUM #include "AArch64GenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "AArch64GenInstrInfo.inc" #include "AArch64GenSubtargetInfo.inc" static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); static void printOperand(MCInst *MI, unsigned OpNum, SStream *O); static bool printSysAlias(MCInst *MI, SStream *O); static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI); static void printInstruction(MCInst *MI, SStream *O); static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS); static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index) { #ifndef CAPSTONE_DIET const uint8_t *arr = AArch64_get_op_access(h, id); if (arr[index] == CS_AC_IGNORE) return 0; return arr[index]; #else return 0; #endif } static void op_addImm(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v; MI->flat_insn->detail->arm64.op_count++; } } static void set_mem_access(MCInst *MI, bool status) { MI->csh->doing_mem = status; if (MI->csh->detail != CS_OPT_ON) return; if (status) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0; } else { // done, create the next operand slot MI->flat_insn->detail->arm64.op_count++; } } void AArch64_printInst(MCInst *MI, SStream *O, void *Info) { // Check for special encodings and print the canonical alias instead. unsigned Opcode = MCInst_getOpcode(MI); int LSB, Width; char *mnem; // printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) return; // SBFM/UBFM should print to a nicer aliased form if possible. if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); MCOperand *Op0 = MCInst_getOperand(MI, 0); MCOperand *Op1 = MCInst_getOperand(MI, 1); MCOperand *Op2 = MCInst_getOperand(MI, 2); MCOperand *Op3 = MCInst_getOperand(MI, 3); if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { const char *AsmMnemonic = NULL; switch (MCOperand_getImm(Op3)) { default: break; case 7: if (IsSigned) AsmMnemonic = "sxtb"; else if (!Is64Bit) AsmMnemonic = "uxtb"; break; case 15: if (IsSigned) AsmMnemonic = "sxth"; else if (!Is64Bit) AsmMnemonic = "uxth"; break; case 31: // *xtw is only valid for signed 64-bit operations. if (Is64Bit && IsSigned) AsmMnemonic = "sxtw"; break; } if (AsmMnemonic) { SStream_concat(O, "%s\t%s, %s", AsmMnemonic, getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1)); MI->flat_insn->detail->arm64.op_count++; } MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); return; } } // All immediate shifts are aliases, implemented using the Bitfield // instruction. In all cases the immediate shift amount shift must be in // the range 0 to (reg.size -1). if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { const char *AsmMnemonic = NULL; int shift = 0; int immr = (int)MCOperand_getImm(Op2); int imms = (int)MCOperand_getImm(Op3); if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { AsmMnemonic = "lsl"; shift = 31 - imms; } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && ((imms + 1 == immr))) { AsmMnemonic = "lsl"; shift = 63 - imms; } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { AsmMnemonic = "lsr"; shift = immr; } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { AsmMnemonic = "lsr"; shift = immr; } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { AsmMnemonic = "asr"; shift = immr; } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { AsmMnemonic = "asr"; shift = immr; } if (AsmMnemonic) { SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic, getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); printInt32Bang(O, shift); MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift; MI->flat_insn->detail->arm64.op_count++; } return; } } // SBFIZ/UBFIZ aliases if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); SStream_concat0(O, ", "); printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1; MI->flat_insn->detail->arm64.op_count++; } return; } // Otherwise SBFX/UBFX is the preferred form SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); printInt32Bang(O, (int)MCOperand_getImm(Op2)); SStream_concat0(O, ", "); printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx")); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1; MI->flat_insn->detail->arm64.op_count++; } return; } if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0 MCOperand *Op2 = MCInst_getOperand(MI, 2); int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) && (ImmR == 0 || ImmS < ImmR)) { // BFC takes precedence over its entire range, sligtly differently to BFI. int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; int LSB = (BitWidth - ImmR) % BitWidth; int Width = ImmS + 1; SStream_concat(O, "bfc\t%s, ", getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName)); printInt32Bang(O, LSB); SStream_concat0(O, ", "); printInt32Bang(O, Width); MCInst_setOpcodePub(MI, AArch64_map_insn("bfc")); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; MI->flat_insn->detail->arm64.op_count++; } return; } else if (ImmS < ImmR) { // BFI alias int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; LSB = (BitWidth - ImmR) % BitWidth; Width = ImmS + 1; SStream_concat(O, "bfi\t%s, %s, ", getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); printInt32Bang(O, LSB); SStream_concat0(O, ", "); printInt32Bang(O, Width); MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; MI->flat_insn->detail->arm64.op_count++; } return; } LSB = ImmR; Width = ImmS - ImmR + 1; // Otherwise BFXIL the preferred form SStream_concat(O, "bfxil\t%s, %s, ", getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); printInt32Bang(O, LSB); SStream_concat0(O, ", "); printInt32Bang(O, Width); MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; MI->flat_insn->detail->arm64.op_count++; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; MI->flat_insn->detail->arm64.op_count++; } return; } // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction // that can represent the move is the MOV alias, and the rest get printed // normally. if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32; int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift; if (isMOVZMovAlias(Value, Shift, Opcode == AArch64_MOVZXi ? 64 : 32)) { SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); printInt64Bang(O, SignExtend64(Value, RegWidth)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); MI->flat_insn->detail->arm64.op_count++; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); MI->flat_insn->detail->arm64.op_count++; } MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); return; } } if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32; int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift); if (RegWidth == 32) Value = Value & 0xffffffff; if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) { SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); printInt64Bang(O, SignExtend64(Value, RegWidth)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); MI->flat_insn->detail->arm64.op_count++; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); MI->flat_insn->detail->arm64.op_count++; } MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); return; } } if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) && (MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR || MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32; uint64_t Value = AArch64_AM_decodeLogicalImmediate( MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth); if (!AArch64_AM_isAnyMOVWMovAlias(Value, RegWidth)) { SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); printInt64Bang(O, SignExtend64(Value, RegWidth)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); MI->flat_insn->detail->arm64.op_count++; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = SignExtend64(Value, RegWidth); MI->flat_insn->detail->arm64.op_count++; } MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); return; } } // Instruction TSB is specified as a one operand instruction, but 'csync' is // not encoded, so for printing it is treated as a special case here: if (Opcode == AArch64_TSB) { SStream_concat0(O, "tsb\tcsync"); MCInst_setOpcodePub(MI, AArch64_map_insn("tsb")); return; } MI->MRI = Info; mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info); if (mnem) { MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); cs_mem_free(mnem); switch(MCInst_getOpcode(MI)) { default: break; case AArch64_LD1i8_POST: arm64_op_addImm(MI, 1); break; case AArch64_LD1i16_POST: arm64_op_addImm(MI, 2); break; case AArch64_LD1i32_POST: arm64_op_addImm(MI, 4); break; case AArch64_LD1Onev1d_POST: case AArch64_LD1Onev2s_POST: case AArch64_LD1Onev4h_POST: case AArch64_LD1Onev8b_POST: case AArch64_LD1i64_POST: arm64_op_addImm(MI, 8); break; case AArch64_LD1Onev16b_POST: case AArch64_LD1Onev2d_POST: case AArch64_LD1Onev4s_POST: case AArch64_LD1Onev8h_POST: case AArch64_LD1Twov1d_POST: case AArch64_LD1Twov2s_POST: case AArch64_LD1Twov4h_POST: case AArch64_LD1Twov8b_POST: arm64_op_addImm(MI, 16); break; case AArch64_LD1Threev1d_POST: case AArch64_LD1Threev2s_POST: case AArch64_LD1Threev4h_POST: case AArch64_LD1Threev8b_POST: arm64_op_addImm(MI, 24); break; case AArch64_LD1Fourv1d_POST: case AArch64_LD1Fourv2s_POST: case AArch64_LD1Fourv4h_POST: case AArch64_LD1Fourv8b_POST: case AArch64_LD1Twov16b_POST: case AArch64_LD1Twov2d_POST: case AArch64_LD1Twov4s_POST: case AArch64_LD1Twov8h_POST: arm64_op_addImm(MI, 32); break; case AArch64_LD1Threev16b_POST: case AArch64_LD1Threev2d_POST: case AArch64_LD1Threev4s_POST: case AArch64_LD1Threev8h_POST: arm64_op_addImm(MI, 48); break; case AArch64_LD1Fourv16b_POST: case AArch64_LD1Fourv2d_POST: case AArch64_LD1Fourv4s_POST: case AArch64_LD1Fourv8h_POST: arm64_op_addImm(MI, 64); break; case AArch64_UMOVvi64: arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); break; case AArch64_UMOVvi32: arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); break; } } else { printInstruction(MI, O); } } static bool printSysAlias(MCInst *MI, SStream *O) { // unsigned Opcode = MCInst_getOpcode(MI); //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); const char *Ins; uint16_t Encoding; bool NeedsReg; char Name[64]; MCOperand *Op1 = MCInst_getOperand(MI, 0); MCOperand *Cn = MCInst_getOperand(MI, 1); MCOperand *Cm = MCInst_getOperand(MI, 2); MCOperand *Op2 = MCInst_getOperand(MI, 3); unsigned Op1Val = (unsigned)MCOperand_getImm(Op1); unsigned CnVal = (unsigned)MCOperand_getImm(Cn); unsigned CmVal = (unsigned)MCOperand_getImm(Cm); unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); Encoding = Op2Val; Encoding |= CmVal << 3; Encoding |= CnVal << 7; Encoding |= Op1Val << 11; if (CnVal == 7) { switch (CmVal) { default: return false; // IC aliases case 1: case 5: { const IC *IC = lookupICByEncoding(Encoding); // if (!IC || !IC->haveFeatures(STI.getFeatureBits())) if (!IC) return false; NeedsReg = IC->NeedsReg; Ins = "ic"; strncpy(Name, IC->Name, sizeof(Name) - 1); } break; // DC aliases case 4: case 6: case 10: case 11: case 12: case 14: { const DC *DC = lookupDCByEncoding(Encoding); // if (!DC || !DC->haveFeatures(STI.getFeatureBits())) if (!DC) return false; NeedsReg = true; Ins = "dc"; strncpy(Name, DC->Name, sizeof(Name) - 1); } break; // AT aliases case 8: case 9: { const AT *AT = lookupATByEncoding(Encoding); // if (!AT || !AT->haveFeatures(STI.getFeatureBits())) if (!AT) return false; NeedsReg = true; Ins = "at"; strncpy(Name, AT->Name, sizeof(Name) - 1); } break; } } else if (CnVal == 8) { // TLBI aliases const TLBI *TLBI = lookupTLBIByEncoding(Encoding); // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) if (!TLBI) return false; NeedsReg = TLBI->NeedsReg; Ins = "tlbi"; strncpy(Name, TLBI->Name, sizeof(Name) - 1); } else return false; SStream_concat(O, "%s\t%s", Ins, Name); if (NeedsReg) { SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName)); } MCInst_setOpcodePub(MI, AArch64_map_insn(Ins)); if (MI->csh->detail) { #if 0 #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif #endif if (NeedsReg) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); MI->flat_insn->detail->arm64.op_count++; } } return true; } static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); if (MCOperand_isReg(Op)) { unsigned Reg = MCOperand_getReg(Op); SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); if (MI->csh->detail) { if (MI->csh->doing_mem) { if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg; } else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg; } } else { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; MI->flat_insn->detail->arm64.op_count++; } } } else if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op); if (MI->Opcode == AArch64_ADR) { imm += MI->address; printUInt64Bang(O, imm); } else { if (MI->csh->doing_mem) { if (MI->csh->imm_unsigned) { printUInt64Bang(O, imm); } else { printInt64Bang(O, imm); } } else printUInt64Bang(O, imm); } if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm; } else { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; MI->flat_insn->detail->arm64.op_count++; } } } } static void printImm(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); printUInt64Bang(O, MCOperand_getImm(Op)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); MI->flat_insn->detail->arm64.op_count++; } } static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); printUInt64Bang(O, MCOperand_getImm(Op)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); MI->flat_insn->detail->arm64.op_count++; } } static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Imm) { MCOperand *Op = MCInst_getOperand(MI, OpNum); if (MCOperand_isReg(Op)) { unsigned Reg = MCOperand_getReg(Op); if (Reg == AArch64_XZR) { printInt32Bang(O, Imm); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm; MI->flat_insn->detail->arm64.op_count++; } } else { SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; MI->flat_insn->detail->arm64.op_count++; } } } //llvm_unreachable("unknown operand kind in printPostIncOperand64"); } static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); //assert(Op.isReg() && "Non-register vreg operand!"); unsigned Reg = MCOperand_getReg(Op); SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); MI->flat_insn->detail->arm64.op_count++; } } static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); SStream_concat(O, "c%u", MCOperand_getImm(Op)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); MI->flat_insn->detail->arm64.op_count++; } } static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { unsigned Val = (MCOperand_getImm(MO) & 0xfff); //assert(Val == MO.getImm() && "Add/sub immediate out of range!"); unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); printInt32Bang(O, Val); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; MI->flat_insn->detail->arm64.op_count++; } if (Shift != 0) printShifter(MI, OpNum + 1, O); } } static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) { int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); Val = AArch64_AM_decodeLogicalImmediate(Val, 32); printUInt32Bang(O, (int)Val); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; MI->flat_insn->detail->arm64.op_count++; } } static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) { int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); Val = AArch64_AM_decodeLogicalImmediate(Val, 64); switch(MI->flat_insn->id) { default: printInt64Bang(O, Val); break; case ARM64_INS_ORR: case ARM64_INS_AND: case ARM64_INS_EOR: case ARM64_INS_TST: // do not print number in negative form if (Val >= 0 && Val <= HEX_THRESHOLD) SStream_concat(O, "#%u", (int)Val); else SStream_concat(O, "#0x%"PRIx64, Val); break; } if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val; MI->flat_insn->detail->arm64.op_count++; } } static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // LSL #0 should not be printed. if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && AArch64_AM_getShiftValue(Val) == 0) return; SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); if (MI->csh->detail) { arm64_shifter shifter = ARM64_SFT_INVALID; switch(AArch64_AM_getShiftType(Val)) { default: // never reach case AArch64_AM_LSL: shifter = ARM64_SFT_LSL; break; case AArch64_AM_LSR: shifter = ARM64_SFT_LSR; break; case AArch64_AM_ASR: shifter = ARM64_SFT_ASR; break; case AArch64_AM_ROR: shifter = ARM64_SFT_ROR; break; case AArch64_AM_MSL: shifter = ARM64_SFT_MSL; break; } MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val); } } static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) { SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); MI->flat_insn->detail->arm64.op_count++; } printShifter(MI, OpNum + 1, O); } static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); // If the destination or first source register operand is [W]SP, print // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at // all. if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); if (((Dest == AArch64_SP || Src1 == AArch64_SP) && ExtType == AArch64_AM_UXTX) || ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && ExtType == AArch64_AM_UXTW)) { if (ShiftVal != 0) { SStream_concat0(O, ", lsl "); printInt32Bang(O, ShiftVal); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; } } return; } } SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); if (MI->csh->detail) { arm64_extender ext = ARM64_EXT_INVALID; switch(ExtType) { default: // never reach case AArch64_AM_UXTB: ext = ARM64_EXT_UXTB; break; case AArch64_AM_UXTH: ext = ARM64_EXT_UXTH; break; case AArch64_AM_UXTW: ext = ARM64_EXT_UXTW; break; case AArch64_AM_UXTX: ext = ARM64_EXT_UXTX; break; case AArch64_AM_SXTB: ext = ARM64_EXT_SXTB; break; case AArch64_AM_SXTH: ext = ARM64_EXT_SXTH; break; case AArch64_AM_SXTW: ext = ARM64_EXT_SXTW; break; case AArch64_AM_SXTX: ext = ARM64_EXT_SXTX; break; } MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext; } if (ShiftVal != 0) { SStream_concat0(O, " "); printInt32Bang(O, ShiftVal); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; } } } static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; MI->flat_insn->detail->arm64.op_count++; } printArithExtend(MI, OpNum + 1, O); } static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, SStream *O) { // sxtw, sxtx, uxtw or lsl (== uxtx) bool IsLSL = !SignExtend && SrcRegKind == 'x'; if (IsLSL) { SStream_concat0(O, "lsl"); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; } } else { SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); if (MI->csh->detail) { if (!SignExtend) { switch(SrcRegKind) { default: break; case 'b': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB; break; case 'h': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH; break; case 'w': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW; break; } } else { switch(SrcRegKind) { default: break; case 'b': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB; break; case 'h': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH; break; case 'w': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW; break; case 'x': MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX; break; } } } } if (DoShift || IsLSL) { SStream_concat(O, " #%u", Log2_32(Width / 8)); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8); } } } static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width) { unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O); } static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O, bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix) { bool DoShift; printOperand(MI, OpNum, O); if (Suffix == 's' || Suffix == 'd') SStream_concat(O, ".%c", Suffix); DoShift = ExtWidth != 8; if (SignExtend || DoShift || SrcRegKind == 'w') { SStream_concat0(O, ", "); printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O); } } static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) { AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getCondCodeName(CC)); if (MI->csh->detail) MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); } static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) { AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); if (MI->csh->detail) { MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); } } static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) { int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printInt64Bang(O, val); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; } else { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; MI->flat_insn->detail->arm64.op_count++; } } } static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { int64_t val = Scale * MCOperand_getImm(MO); printInt64Bang(O, val); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; } else { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val; MI->flat_insn->detail->arm64.op_count++; } } } } #if 0 static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale) { MCOperand *MO = MCInst_getOperand(MI, OpNum + 1); SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); if (MCOperand_isImm(MO)) { int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printInt64Bang(O, val); // } else { // // assert(MO1.isExpr() && "Unexpected operand type!"); // SStream_concat0(O, ", "); // MO1.getExpr()->print(O, &MAI); } SStream_concat0(O, "]"); } #endif // IsSVEPrefetch = false static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch) { unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (IsSVEPrefetch) { const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop); if (PRFM) SStream_concat0(O, PRFM->Name); return; } else { const PRFM *PRFM = lookupPRFMByEncoding(prfop); if (PRFM) SStream_concat0(O, PRFM->Name); return; } // FIXME: set OpcodePub? printInt32Bang(O, prfop); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; MI->flat_insn->detail->arm64.op_count++; } } static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); unsigned int psbhintop = MCOperand_getImm(Op); const PSB *PSB = AArch64PSBHint_lookupPSBByEncoding(psbhintop); if (PSB) SStream_concat0(O, PSB->Name); else printUInt32Bang(O, psbhintop); } static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); // 8 decimal places are enough to perfectly represent permitted floats. #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point SStream_concat(O, "#"); #else SStream_concat(O, "#%.8f", FPImm); #endif if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm; MI->flat_insn->detail->arm64.op_count++; } } //static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) { while (Stride--) { if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30 Reg += 1; else if (Reg == AArch64_Q31) // Vector lists can wrap around. Reg = AArch64_Q0; else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30 Reg += 1; else if (Reg == AArch64_Z31) // Vector lists can wrap around. Reg = AArch64_Z0; } return Reg; } static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned int size) { // static_assert(size == 64 || size == 32, // "Template parameter must be either 32 or 64"); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64; unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64; unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName), getRegisterName(Odd, AArch64_NoRegAltName)); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Even); MI->flat_insn->detail->arm64.op_count++; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Odd); MI->flat_insn->detail->arm64.op_count++; } } static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas) { #define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned NumRegs = 1, FirstReg, i; SStream_concat0(O, "{"); // Work out how many registers there are in the list (if there is an actual // list). if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) || GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) NumRegs = 2; else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) NumRegs = 3; else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) NumRegs = 4; // Now forget about the list and find out what the first register is. if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) Reg = FirstReg; else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) Reg = FirstReg; else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0))) Reg = FirstReg; // If it's a D-reg, we need to promote it to the equivalent Q-reg before // printing (otherwise getRegisterName fails). if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) { const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID); Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC); } for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { if (GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg)) SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix); else SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; MI->flat_insn->detail->arm64.op_count++; } if (i + 1 != NumRegs) SStream_concat0(O, ", "); } SStream_concat0(O, "}"); } static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind) { char Suffix[32]; arm64_vas vas = 0; if (NumLanes) { cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); switch(LaneKind) { default: break; case 'b': switch(NumLanes) { default: break; case 1: vas = ARM64_VAS_1B; break; case 4: vas = ARM64_VAS_4B; break; case 8: vas = ARM64_VAS_8B; break; case 16: vas = ARM64_VAS_16B; break; } break; case 'h': switch(NumLanes) { default: break; case 1: vas = ARM64_VAS_1H; break; case 2: vas = ARM64_VAS_2H; break; case 4: vas = ARM64_VAS_4H; break; case 8: vas = ARM64_VAS_8H; break; } break; case 's': switch(NumLanes) { default: break; case 1: vas = ARM64_VAS_1S; break; case 2: vas = ARM64_VAS_2S; break; case 4: vas = ARM64_VAS_4S; break; } break; case 'd': switch(NumLanes) { default: break; case 1: vas = ARM64_VAS_1D; break; case 2: vas = ARM64_VAS_2D; break; } break; case 'q': switch(NumLanes) { default: break; case 1: vas = ARM64_VAS_1Q; break; } break; } } else { cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); switch(LaneKind) { default: break; case 'b': vas = ARM64_VAS_1B; break; case 'h': vas = ARM64_VAS_1H; break; case 's': vas = ARM64_VAS_1S; break; case 'd': vas = ARM64_VAS_1D; break; case 'q': vas = ARM64_VAS_1Q; break; } } printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas); } static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) { SStream_concat0(O, "["); printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); SStream_concat0(O, "]"); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); } } static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); // If the label has already been resolved to an immediate offset (say, when // we're running the disassembler), just print the immediate. if (MCOperand_isImm(Op)) { uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address; printUInt64Bang(O, imm); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; MI->flat_insn->detail->arm64.op_count++; } } } static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(Op)) { // ADRP sign extends a 21-bit offset, shifts it left by 12 // and adds it to the value of the PC with its bottom 12 bits cleared uint64_t imm = (MCOperand_getImm(Op) * 0x1000) + (MI->address & ~0xfff); printUInt64Bang(O, imm); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; MI->flat_insn->detail->arm64.op_count++; } } } static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Opcode = MCInst_getOpcode(MI); const char *Name = NULL; if (Opcode == AArch64_ISB) { const ISB *ISB = lookupISBByEncoding(Val); Name = ISB ? ISB->Name : NULL; } else if (Opcode == AArch64_TSB) { const TSB *TSB = lookupTSBByEncoding(Val); Name = TSB ? TSB->Name : NULL; } else { const DB *DB = lookupDBByEncoding(Val); Name = DB ? DB->Name : NULL; } if (Name) { SStream_concat0(O, Name); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; MI->flat_insn->detail->arm64.op_count++; } } else { printUInt32Bang(O, Val); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; MI->flat_insn->detail->arm64.op_count++; } } } static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); const SysReg *Reg = lookupSysRegByEncoding(Val); // Horrible hack for the one register that has identical encodings but // different names in MSR and MRS. Because of this, one of MRS and MSR is // going to get the wrong entry if (Val == ARM64_SYSREG_DBGDTRRX_EL0) { SStream_concat0(O, "dbgdtrrx_el0"); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; MI->flat_insn->detail->arm64.op_count++; } return; } // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) if (Reg && Reg->Readable) { SStream_concat0(O, Reg->Name); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; MI->flat_insn->detail->arm64.op_count++; } } else { char result[128]; AArch64SysReg_genericRegisterString(Val, result); SStream_concat0(O, result); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; MI->flat_insn->detail->arm64.op_count++; } } } static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); const SysReg *Reg = lookupSysRegByEncoding(Val); // Horrible hack for the one register that has identical encodings but // different names in MSR and MRS. Because of this, one of MRS and MSR is // going to get the wrong entry if (Val == ARM64_SYSREG_DBGDTRTX_EL0) { SStream_concat0(O, "dbgdtrtx_el0"); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; MI->flat_insn->detail->arm64.op_count++; } return; } // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) if (Reg && Reg->Writeable) { SStream_concat0(O, Reg->Name); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; MI->flat_insn->detail->arm64.op_count++; } } else { char result[128]; AArch64SysReg_genericRegisterString(Val, result); SStream_concat0(O, result); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; MI->flat_insn->detail->arm64.op_count++; } } } static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); const PState *PState = lookupPStateByEncoding(Val); if (PState) { SStream_concat0(O, PState->Name); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val; MI->flat_insn->detail->arm64.op_count++; } } else { printUInt32Bang(O, Val); if (MI->csh->detail) { #ifndef CAPSTONE_DIET unsigned char access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; MI->flat_insn->detail->arm64.op_count++; } } } static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O) { uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); SStream_concat(O, "#%#016llx", Val); if (MI->csh->detail) { #ifndef CAPSTONE_DIET unsigned char access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; MI->flat_insn->detail->arm64.op_count++; } } static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder) { unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printInt64Bang(O, (Val * Angle) + Remainder); op_addImm(MI, (Val * Angle) + Remainder); } static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val); if (Pat) SStream_concat0(O, Pat->Name); else printUInt32Bang(O, Val); } // default suffix = 0 static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix) { unsigned int Reg; #if 0 switch (suffix) { case 0: case 'b': case 'h': case 's': case 'd': case 'q': break; default: // llvm_unreachable("Invalid kind specifier."); } #endif Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; MI->flat_insn->detail->arm64.op_count++; } SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); if (suffix != '\0') SStream_concat(O, ".%c", suffix); } static void printImmSVE16(int16_t Val, SStream *O) { printUInt32Bang(O, Val); } static void printImmSVE32(int32_t Val, SStream *O) { printUInt32Bang(O, Val); } static void printImmSVE64(int64_t Val, SStream *O) { printUInt64Bang(O, Val); } static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O) { unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); uint32_t Val; // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && // "Unexepected shift type!"); // #0 lsl #8 is never pretty printed if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { printUInt32Bang(O, UnscaledVal); printShifter(MI, OpNum + 1, O); return; } Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); printImmSVE32(Val, O); } static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O) { unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); uint64_t Val; // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && // "Unexepected shift type!"); // #0 lsl #8 is never pretty printed if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { printUInt32Bang(O, UnscaledVal); printShifter(MI, OpNum + 1, O); return; } Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); printImmSVE64(Val, O); } static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O) { uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); // Prefer the default format for 16bit values, hex otherwise. printImmSVE16(PrintVal, O); } static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) { uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); // Prefer the default format for 16bit values, hex otherwise. if ((uint16_t)PrintVal == (uint32_t)PrintVal) printImmSVE16(PrintVal, O); else printUInt64Bang(O, PrintVal); } static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) { uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); printImmSVE64(PrintVal, O); } static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width) { unsigned int Base, Reg; switch (Width) { default: // llvm_unreachable("Unsupported width"); case 8: Base = AArch64_B0; break; case 16: Base = AArch64_H0; break; case 32: Base = AArch64_S0; break; case 64: Base = AArch64_D0; break; case 128: Base = AArch64_Q0; break; } Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getRegisterName(Reg - AArch64_Z0 + Base, AArch64_NoRegAltName)); } static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1) { const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0); const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1); unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr); } static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O) { unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName)); } #define PRINT_ALIAS_INSTR #include "AArch64GenAsmWriter.inc" #include "AArch64GenRegisterName.inc" void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci) { if (((cs_struct *)handle)->detail != CS_OPT_ON) return; if (mci->csh->detail) { unsigned opcode = MCInst_getOpcode(mci); switch (opcode) { default: break; case AArch64_LD1Fourv16b_POST: case AArch64_LD1Fourv1d_POST: case AArch64_LD1Fourv2d_POST: case AArch64_LD1Fourv2s_POST: case AArch64_LD1Fourv4h_POST: case AArch64_LD1Fourv4s_POST: case AArch64_LD1Fourv8b_POST: case AArch64_LD1Fourv8h_POST: case AArch64_LD1Onev16b_POST: case AArch64_LD1Onev1d_POST: case AArch64_LD1Onev2d_POST: case AArch64_LD1Onev2s_POST: case AArch64_LD1Onev4h_POST: case AArch64_LD1Onev4s_POST: case AArch64_LD1Onev8b_POST: case AArch64_LD1Onev8h_POST: case AArch64_LD1Rv16b_POST: case AArch64_LD1Rv1d_POST: case AArch64_LD1Rv2d_POST: case AArch64_LD1Rv2s_POST: case AArch64_LD1Rv4h_POST: case AArch64_LD1Rv4s_POST: case AArch64_LD1Rv8b_POST: case AArch64_LD1Rv8h_POST: case AArch64_LD1Threev16b_POST: case AArch64_LD1Threev1d_POST: case AArch64_LD1Threev2d_POST: case AArch64_LD1Threev2s_POST: case AArch64_LD1Threev4h_POST: case AArch64_LD1Threev4s_POST: case AArch64_LD1Threev8b_POST: case AArch64_LD1Threev8h_POST: case AArch64_LD1Twov16b_POST: case AArch64_LD1Twov1d_POST: case AArch64_LD1Twov2d_POST: case AArch64_LD1Twov2s_POST: case AArch64_LD1Twov4h_POST: case AArch64_LD1Twov4s_POST: case AArch64_LD1Twov8b_POST: case AArch64_LD1Twov8h_POST: case AArch64_LD1i16_POST: case AArch64_LD1i32_POST: case AArch64_LD1i64_POST: case AArch64_LD1i8_POST: case AArch64_LD2Rv16b_POST: case AArch64_LD2Rv1d_POST: case AArch64_LD2Rv2d_POST: case AArch64_LD2Rv2s_POST: case AArch64_LD2Rv4h_POST: case AArch64_LD2Rv4s_POST: case AArch64_LD2Rv8b_POST: case AArch64_LD2Rv8h_POST: case AArch64_LD2Twov16b_POST: case AArch64_LD2Twov2d_POST: case AArch64_LD2Twov2s_POST: case AArch64_LD2Twov4h_POST: case AArch64_LD2Twov4s_POST: case AArch64_LD2Twov8b_POST: case AArch64_LD2Twov8h_POST: case AArch64_LD2i16_POST: case AArch64_LD2i32_POST: case AArch64_LD2i64_POST: case AArch64_LD2i8_POST: case AArch64_LD3Rv16b_POST: case AArch64_LD3Rv1d_POST: case AArch64_LD3Rv2d_POST: case AArch64_LD3Rv2s_POST: case AArch64_LD3Rv4h_POST: case AArch64_LD3Rv4s_POST: case AArch64_LD3Rv8b_POST: case AArch64_LD3Rv8h_POST: case AArch64_LD3Threev16b_POST: case AArch64_LD3Threev2d_POST: case AArch64_LD3Threev2s_POST: case AArch64_LD3Threev4h_POST: case AArch64_LD3Threev4s_POST: case AArch64_LD3Threev8b_POST: case AArch64_LD3Threev8h_POST: case AArch64_LD3i16_POST: case AArch64_LD3i32_POST: case AArch64_LD3i64_POST: case AArch64_LD3i8_POST: case AArch64_LD4Fourv16b_POST: case AArch64_LD4Fourv2d_POST: case AArch64_LD4Fourv2s_POST: case AArch64_LD4Fourv4h_POST: case AArch64_LD4Fourv4s_POST: case AArch64_LD4Fourv8b_POST: case AArch64_LD4Fourv8h_POST: case AArch64_LD4Rv16b_POST: case AArch64_LD4Rv1d_POST: case AArch64_LD4Rv2d_POST: case AArch64_LD4Rv2s_POST: case AArch64_LD4Rv4h_POST: case AArch64_LD4Rv4s_POST: case AArch64_LD4Rv8b_POST: case AArch64_LD4Rv8h_POST: case AArch64_LD4i16_POST: case AArch64_LD4i32_POST: case AArch64_LD4i64_POST: case AArch64_LD4i8_POST: case AArch64_LDPDpost: case AArch64_LDPDpre: case AArch64_LDPQpost: case AArch64_LDPQpre: case AArch64_LDPSWpost: case AArch64_LDPSWpre: case AArch64_LDPSpost: case AArch64_LDPSpre: case AArch64_LDPWpost: case AArch64_LDPWpre: case AArch64_LDPXpost: case AArch64_LDPXpre: case AArch64_LDRBBpost: case AArch64_LDRBBpre: case AArch64_LDRBpost: case AArch64_LDRBpre: case AArch64_LDRDpost: case AArch64_LDRDpre: case AArch64_LDRHHpost: case AArch64_LDRHHpre: case AArch64_LDRHpost: case AArch64_LDRHpre: case AArch64_LDRQpost: case AArch64_LDRQpre: case AArch64_LDRSBWpost: case AArch64_LDRSBWpre: case AArch64_LDRSBXpost: case AArch64_LDRSBXpre: case AArch64_LDRSHWpost: case AArch64_LDRSHWpre: case AArch64_LDRSHXpost: case AArch64_LDRSHXpre: case AArch64_LDRSWpost: case AArch64_LDRSWpre: case AArch64_LDRSpost: case AArch64_LDRSpre: case AArch64_LDRWpost: case AArch64_LDRWpre: case AArch64_LDRXpost: case AArch64_LDRXpre: case AArch64_ST1Fourv16b_POST: case AArch64_ST1Fourv1d_POST: case AArch64_ST1Fourv2d_POST: case AArch64_ST1Fourv2s_POST: case AArch64_ST1Fourv4h_POST: case AArch64_ST1Fourv4s_POST: case AArch64_ST1Fourv8b_POST: case AArch64_ST1Fourv8h_POST: case AArch64_ST1Onev16b_POST: case AArch64_ST1Onev1d_POST: case AArch64_ST1Onev2d_POST: case AArch64_ST1Onev2s_POST: case AArch64_ST1Onev4h_POST: case AArch64_ST1Onev4s_POST: case AArch64_ST1Onev8b_POST: case AArch64_ST1Onev8h_POST: case AArch64_ST1Threev16b_POST: case AArch64_ST1Threev1d_POST: case AArch64_ST1Threev2d_POST: case AArch64_ST1Threev2s_POST: case AArch64_ST1Threev4h_POST: case AArch64_ST1Threev4s_POST: case AArch64_ST1Threev8b_POST: case AArch64_ST1Threev8h_POST: case AArch64_ST1Twov16b_POST: case AArch64_ST1Twov1d_POST: case AArch64_ST1Twov2d_POST: case AArch64_ST1Twov2s_POST: case AArch64_ST1Twov4h_POST: case AArch64_ST1Twov4s_POST: case AArch64_ST1Twov8b_POST: case AArch64_ST1Twov8h_POST: case AArch64_ST1i16_POST: case AArch64_ST1i32_POST: case AArch64_ST1i64_POST: case AArch64_ST1i8_POST: case AArch64_ST2Twov16b_POST: case AArch64_ST2Twov2d_POST: case AArch64_ST2Twov2s_POST: case AArch64_ST2Twov4h_POST: case AArch64_ST2Twov4s_POST: case AArch64_ST2Twov8b_POST: case AArch64_ST2Twov8h_POST: case AArch64_ST2i16_POST: case AArch64_ST2i32_POST: case AArch64_ST2i64_POST: case AArch64_ST2i8_POST: case AArch64_ST3Threev16b_POST: case AArch64_ST3Threev2d_POST: case AArch64_ST3Threev2s_POST: case AArch64_ST3Threev4h_POST: case AArch64_ST3Threev4s_POST: case AArch64_ST3Threev8b_POST: case AArch64_ST3Threev8h_POST: case AArch64_ST3i16_POST: case AArch64_ST3i32_POST: case AArch64_ST3i64_POST: case AArch64_ST3i8_POST: case AArch64_ST4Fourv16b_POST: case AArch64_ST4Fourv2d_POST: case AArch64_ST4Fourv2s_POST: case AArch64_ST4Fourv4h_POST: case AArch64_ST4Fourv4s_POST: case AArch64_ST4Fourv8b_POST: case AArch64_ST4Fourv8h_POST: case AArch64_ST4i16_POST: case AArch64_ST4i32_POST: case AArch64_ST4i64_POST: case AArch64_ST4i8_POST: case AArch64_STPDpost: case AArch64_STPDpre: case AArch64_STPQpost: case AArch64_STPQpre: case AArch64_STPSpost: case AArch64_STPSpre: case AArch64_STPWpost: case AArch64_STPWpre: case AArch64_STPXpost: case AArch64_STPXpre: case AArch64_STRBBpost: case AArch64_STRBBpre: case AArch64_STRBpost: case AArch64_STRBpre: case AArch64_STRDpost: case AArch64_STRDpre: case AArch64_STRHHpost: case AArch64_STRHHpre: case AArch64_STRHpost: case AArch64_STRHpre: case AArch64_STRQpost: case AArch64_STRQpre: case AArch64_STRSpost: case AArch64_STRSpre: case AArch64_STRWpost: case AArch64_STRWpre: case AArch64_STRXpost: case AArch64_STRXpre: flat_insn->detail->arm64.writeback = true; break; } } } #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64InstPrinter.h000064400000000000000000000015700072674642500217560ustar 00000000000000//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an AArch64 MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_AARCH64INSTPRINTER_H #define CS_LLVM_AARCH64INSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void AArch64_printInst(MCInst *MI, SStream *O, void *); void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64Mapping.c000064400000000000000000000222770072674642500210720ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_ARM64 #include // debug #include #include "../../utils.h" #include "AArch64Mapping.h" #define GET_INSTRINFO_ENUM #include "AArch64GenInstrInfo.inc" #ifndef CAPSTONE_DIET // NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg static const char * const reg_name_maps[] = { NULL, /* ARM64_REG_INVALID */ "ffr", "fp", "lr", "nzcv", "sp", "wsp", "wzr", "xzr", "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", }; #endif const char *AArch64_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg]; #else return NULL; #endif } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "AArch64MappingInsn.inc" }; // given internal insn id, return public instruction info void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET cs_struct handle; handle.detail = h->detail; memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); #endif } } } static const char * const insn_name_maps[] = { NULL, // ARM64_INS_INVALID #include "AArch64MappingInsnName.inc" "sbfiz", "ubfiz", "sbfx", "ubfx", "bfi", "bfxil", "ic", "dc", "at", "tlbi", }; const char *AArch64_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= ARM64_INS_ENDING) return NULL; if (id < ARR_SIZE(insn_name_maps)) return insn_name_maps[id]; // not found return NULL; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { ARM64_GRP_INVALID, NULL }, { ARM64_GRP_JUMP, "jump" }, { ARM64_GRP_CALL, "call" }, { ARM64_GRP_RET, "return" }, { ARM64_GRP_PRIVILEGE, "privilege" }, { ARM64_GRP_INT, "int" }, { ARM64_GRP_BRANCH_RELATIVE, "branch_relative" }, { ARM64_GRP_PAC, "pointer authentication" }, // architecture-specific groups { ARM64_GRP_CRYPTO, "crypto" }, { ARM64_GRP_FPARMV8, "fparmv8" }, { ARM64_GRP_NEON, "neon" }, { ARM64_GRP_CRC, "crc" }, { ARM64_GRP_AES, "aes" }, { ARM64_GRP_DOTPROD, "dotprod" }, { ARM64_GRP_FULLFP16, "fullfp16" }, { ARM64_GRP_LSE, "lse" }, { ARM64_GRP_RCPC, "rcpc" }, { ARM64_GRP_RDM, "rdm" }, { ARM64_GRP_SHA2, "sha2" }, { ARM64_GRP_SHA3, "sha3" }, { ARM64_GRP_SM4, "sm4" }, { ARM64_GRP_SVE, "sve" }, { ARM64_GRP_V8_1A, "v8_1a" }, { ARM64_GRP_V8_3A, "v8_3a" }, { ARM64_GRP_V8_4A, "v8_4a" }, }; #endif const char *AArch64_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // map instruction name to public instruction ID arm64_insn AArch64_map_insn(const char *name) { unsigned int i; for(i = 1; i < ARR_SIZE(insn_name_maps); i++) { if (!strcmp(name, insn_name_maps[i])) return i; } // not found return ARM64_INS_INVALID; } // map internal raw vregister to 'public' register arm64_reg AArch64_map_vregister(unsigned int r) { static const unsigned short RegAsmOffsetvreg[] = { #include "AArch64GenRegisterV.inc" }; if (r < ARR_SIZE(RegAsmOffsetvreg)) return RegAsmOffsetvreg[r - 1]; // cannot find this register return 0; } void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) { if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp; } } void arm64_op_addFP(MCInst *MI, float fp) { if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp; MI->flat_insn->detail->arm64.op_count++; } } void arm64_op_addImm(MCInst *MI, int64_t imm) { if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm; MI->flat_insn->detail->arm64.op_count++; } } #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { unsigned int eflags_update; // how this instruction update status flags uint8_t access[5]; } insn_op; static const insn_op insn_ops[] = { { /* NULL item */ 0, { 0 } }, #include "AArch64MappingInsnOp.inc" }; // given internal insn id, return operand access info const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id) { int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { return insn_ops[i].access; } return NULL; } void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count) { uint8_t i; uint8_t read_count, write_count; cs_arm64 *arm64 = &(insn->detail->arm64); read_count = insn->detail->regs_read_count; write_count = insn->detail->regs_write_count; // implicit registers memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); // explicit registers for (i = 0; i < arm64->op_count; i++) { cs_arm64_op *op = &(arm64->operands[i]); switch((int)op->type) { case ARM64_OP_REG: if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { regs_read[read_count] = (uint16_t)op->reg; read_count++; } if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { regs_write[write_count] = (uint16_t)op->reg; write_count++; } break; case ARM_OP_MEM: // registers appeared in memory references always being read if ((op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { regs_read[read_count] = (uint16_t)op->mem.base; read_count++; } if ((op->mem.index != ARM64_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { regs_read[read_count] = (uint16_t)op->mem.index; read_count++; } if ((arm64->writeback) && (op->mem.base != ARM64_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { regs_write[write_count] = (uint16_t)op->mem.base; write_count++; } default: break; } } *regs_read_count = read_count; *regs_write_count = write_count; } #endif #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64Mapping.h000064400000000000000000000022370072674642500210710ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_ARM64_MAP_H #define CS_ARM64_MAP_H #include "capstone/capstone.h" #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) // return name of regiser in friendly string const char *AArch64_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *AArch64_insn_name(csh handle, unsigned int id); const char *AArch64_group_name(csh handle, unsigned int id); // map instruction name to public instruction ID arm64_insn AArch64_map_insn(const char *name); // map internal vregister to public register arm64_reg AArch64_map_vregister(unsigned int r); void arm64_op_addReg(MCInst *MI, int reg); void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); void arm64_op_addFP(MCInst *MI, float fp); void arm64_op_addImm(MCInst *MI, int64_t imm); const uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id); void AArch64_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64MappingInsn.inc000064400000000000000000016275420072674642500222600ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { AArch64_ABS_ZPmZ_B, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ABS_ZPmZ_D, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ABS_ZPmZ_H, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ABS_ZPmZ_S, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ABSv16i8, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv1i64, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv2i32, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv2i64, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv4i16, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv4i32, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv8i16, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ABSv8i8, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADCSWr, ARM64_INS_ADCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADCSXr, ARM64_INS_ADCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADCWr, ARM64_INS_ADC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADCXr, ARM64_INS_ADC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPL_XXI, ARM64_INS_ADDPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDPv16i8, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv2i32, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv2i64, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv2i64p, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv4i16, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv4i32, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv8i16, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDPv8i8, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDSWri, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDSWrs, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDSWrx, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDSXri, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDSXrs, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDSXrx, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDSXrx64, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDVL_XXI, ARM64_INS_ADDVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDVv16i8v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDVv4i16v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDVv4i32v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDVv8i16v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDVv8i8v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDWri, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDWrs, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDWrx, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDXri, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDXrs, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDXrx, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDXrx64, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZI_B, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZI_D, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZI_H, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZI_S, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZPmZ_B, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZPmZ_D, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZPmZ_H, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZPmZ_S, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZZZ_B, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZZZ_D, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZZZ_H, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADD_ZZZ_S, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADDv16i8, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv1i64, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv2i32, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv2i64, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv4i16, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv4i32, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv8i16, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADDv8i8, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ADR, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADRP, ARM64_INS_ADRP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_D_0, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_D_1, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_D_2, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_D_3, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_S_0, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_S_1, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_S_2, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_LSL_ZZZ_S_3, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_SXTW_ZZZ_D_0, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_SXTW_ZZZ_D_1, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_SXTW_ZZZ_D_2, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_SXTW_ZZZ_D_3, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_UXTW_ZZZ_D_0, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_UXTW_ZZZ_D_1, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_UXTW_ZZZ_D_2, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ADR_UXTW_ZZZ_D_3, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AESDrr, ARM64_INS_AESD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_AESErr, ARM64_INS_AESE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_AESIMCrr, ARM64_INS_AESIMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_AESMCrr, ARM64_INS_AESMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_ANDSWri, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDSWrs, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDSXri, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDSXrs, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDS_PPzPP, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDV_VPZ_B, ARM64_INS_ANDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDV_VPZ_D, ARM64_INS_ANDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDV_VPZ_H, ARM64_INS_ANDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDV_VPZ_S, ARM64_INS_ANDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDWri, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDWrs, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDXri, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDXrs, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_PPzPP, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_ZI, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_ZPmZ_B, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_ZPmZ_D, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_ZPmZ_H, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_ZPmZ_S, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AND_ZZZ, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ANDv16i8, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ANDv8i8, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ASRD_ZPmI_B, ARM64_INS_ASRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRD_ZPmI_D, ARM64_INS_ASRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRD_ZPmI_H, ARM64_INS_ASRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRD_ZPmI_S, ARM64_INS_ASRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRR_ZPmZ_B, ARM64_INS_ASRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRR_ZPmZ_D, ARM64_INS_ASRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRR_ZPmZ_H, ARM64_INS_ASRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRR_ZPmZ_S, ARM64_INS_ASRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRVWr, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASRVXr, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_WIDE_ZPmZ_B, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_WIDE_ZPmZ_H, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_WIDE_ZPmZ_S, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_WIDE_ZZZ_B, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_WIDE_ZZZ_H, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_WIDE_ZZZ_S, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmI_B, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmI_D, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmI_H, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmI_S, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmZ_B, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmZ_D, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmZ_H, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZPmZ_S, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZZI_B, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZZI_D, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZZI_H, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ASR_ZZI_S, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_AUTDA, ARM64_INS_AUTDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTDB, ARM64_INS_AUTDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTDZA, ARM64_INS_AUTDZA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTDZB, ARM64_INS_AUTDZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIA, ARM64_INS_AUTIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIA1716, ARM64_INS_AUTIA1716, #ifndef CAPSTONE_DIET { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIASP, ARM64_INS_AUTIASP, #ifndef CAPSTONE_DIET { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIAZ, ARM64_INS_AUTIAZ, #ifndef CAPSTONE_DIET { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIB, ARM64_INS_AUTIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIB1716, ARM64_INS_AUTIB1716, #ifndef CAPSTONE_DIET { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIBSP, ARM64_INS_AUTIBSP, #ifndef CAPSTONE_DIET { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIBZ, ARM64_INS_AUTIBZ, #ifndef CAPSTONE_DIET { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIZA, ARM64_INS_AUTIZA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_AUTIZB, ARM64_INS_AUTIZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_B, ARM64_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_BCAX, ARM64_INS_BCAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BFMWri, ARM64_INS_BFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BFMXri, ARM64_INS_BFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BICSWrs, ARM64_INS_BICS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_BICSXrs, ARM64_INS_BICS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_BICS_PPzPP, ARM64_INS_BICS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BICWrs, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BICXrs, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BIC_PPzPP, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BIC_ZPmZ_B, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BIC_ZPmZ_D, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BIC_ZPmZ_H, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BIC_ZPmZ_S, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BIC_ZZZ, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BICv16i8, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BICv2i32, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BICv4i16, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BICv4i32, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BICv8i16, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BICv8i8, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BIFv16i8, ARM64_INS_BIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BIFv8i8, ARM64_INS_BIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BITv16i8, ARM64_INS_BIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BITv8i8, ARM64_INS_BIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BL, ARM64_INS_BL, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_BLR, ARM64_INS_BLR, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1 #endif }, { AArch64_BLRAA, ARM64_INS_BLRAA, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BLRAAZ, ARM64_INS_BLRAAZ, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BLRAB, ARM64_INS_BLRAB, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BLRABZ, ARM64_INS_BLRABZ, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_CALL, ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BR, ARM64_INS_BR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 1 #endif }, { AArch64_BRAA, ARM64_INS_BRAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BRAAZ, ARM64_INS_BRAAZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BRAB, ARM64_INS_BRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BRABZ, ARM64_INS_BRABZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_BRK, ARM64_INS_BRK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKAS_PPzP, ARM64_INS_BRKAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKA_PPmP, ARM64_INS_BRKA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKA_PPzP, ARM64_INS_BRKA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKBS_PPzP, ARM64_INS_BRKBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKB_PPmP, ARM64_INS_BRKB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKB_PPzP, ARM64_INS_BRKB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKNS_PPzP, ARM64_INS_BRKNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKN_PPzP, ARM64_INS_BRKN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKPAS_PPzPP, ARM64_INS_BRKPAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKPA_PPzPP, ARM64_INS_BRKPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKPBS_PPzPP, ARM64_INS_BRKPBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BRKPB_PPzPP, ARM64_INS_BRKPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_BSLv16i8, ARM64_INS_BSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_BSLv8i8, ARM64_INS_BSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_Bcc, ARM64_INS_B, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_CASAB, ARM64_INS_CASAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASAH, ARM64_INS_CASAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASALB, ARM64_INS_CASALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASALH, ARM64_INS_CASALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASALW, ARM64_INS_CASAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASALX, ARM64_INS_CASAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASAW, ARM64_INS_CASA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASAX, ARM64_INS_CASA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASB, ARM64_INS_CASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASH, ARM64_INS_CASH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASLB, ARM64_INS_CASLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASLH, ARM64_INS_CASLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASLW, ARM64_INS_CASL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASLX, ARM64_INS_CASL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPALW, ARM64_INS_CASPAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPALX, ARM64_INS_CASPAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPAW, ARM64_INS_CASPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPAX, ARM64_INS_CASPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPLW, ARM64_INS_CASPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPLX, ARM64_INS_CASPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPW, ARM64_INS_CASP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASPX, ARM64_INS_CASP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASW, ARM64_INS_CAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CASX, ARM64_INS_CAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CBNZW, ARM64_INS_CBNZ, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_CBNZX, ARM64_INS_CBNZ, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_CBZW, ARM64_INS_CBZ, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_CBZX, ARM64_INS_CBZ, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_CCMNWi, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMNWr, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMNXi, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMNXr, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMPWi, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMPWr, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMPXi, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CCMPXr, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_CFINV, ARM64_INS_CFINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_RPZ_B, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_RPZ_D, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_RPZ_H, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_RPZ_S, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_VPZ_B, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_VPZ_D, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_VPZ_H, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_VPZ_S, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_ZPZ_B, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_ZPZ_D, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_ZPZ_H, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTA_ZPZ_S, ARM64_INS_CLASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_RPZ_B, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_RPZ_D, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_RPZ_H, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_RPZ_S, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_VPZ_B, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_VPZ_D, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_VPZ_H, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_VPZ_S, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_ZPZ_B, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_ZPZ_D, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_ZPZ_H, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLASTB_ZPZ_S, ARM64_INS_CLASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLREX, ARM64_INS_CLREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLSWr, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLSXr, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLS_ZPmZ_B, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLS_ZPmZ_D, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLS_ZPmZ_H, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLS_ZPmZ_S, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLSv16i8, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLSv2i32, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLSv4i16, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLSv4i32, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLSv8i16, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLSv8i8, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLZWr, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLZXr, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLZ_ZPmZ_B, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLZ_ZPmZ_D, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLZ_ZPmZ_H, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLZ_ZPmZ_S, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CLZv16i8, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLZv2i32, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLZv4i16, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLZv4i32, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLZv8i16, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CLZv8i8, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv16i8, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv16i8rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv1i64, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv1i64rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv2i32, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv2i32rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv2i64, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv2i64rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv4i16, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv4i16rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv4i32, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv4i32rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv8i16, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv8i16rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv8i8, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMEQv8i8rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv16i8, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv16i8rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv1i64, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv1i64rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv2i32, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv2i32rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv2i64, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv2i64rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv4i16, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv4i16rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv4i32, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv4i32rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv8i16, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv8i16rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv8i8, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGEv8i8rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv16i8, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv16i8rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv1i64, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv1i64rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv2i32, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv2i32rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv2i64, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv2i64rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv4i16, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv4i16rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv4i32, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv4i32rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv8i16, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv8i16rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv8i8, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMGTv8i8rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv16i8, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv1i64, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv2i32, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv2i64, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv4i16, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv4i32, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv8i16, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHIv8i8, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv16i8, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv1i64, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv2i32, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv2i64, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv4i16, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv4i32, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv8i16, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMHSv8i8, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv16i8rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv1i64rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv2i32rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv2i64rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv4i16rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv4i32rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv8i16rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLEv8i8rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv16i8rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv1i64rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv2i32rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv2i64rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv4i16rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv4i32rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv8i16rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMLTv8i8rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZI_B, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZI_D, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZI_H, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZI_S, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZZ_B, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZZ_D, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZZ_H, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_PPzZZ_S, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_WIDE_PPzZZ_B, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_WIDE_PPzZZ_H, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPEQ_WIDE_PPzZZ_S, ARM64_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZI_B, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZI_D, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZI_H, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZI_S, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZZ_B, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZZ_D, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZZ_H, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_PPzZZ_S, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_WIDE_PPzZZ_B, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_WIDE_PPzZZ_H, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGE_WIDE_PPzZZ_S, ARM64_INS_CMPGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZI_B, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZI_D, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZI_H, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZI_S, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZZ_B, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZZ_D, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZZ_H, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_PPzZZ_S, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_WIDE_PPzZZ_B, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_WIDE_PPzZZ_H, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPGT_WIDE_PPzZZ_S, ARM64_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZI_B, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZI_D, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZI_H, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZI_S, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZZ_B, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZZ_D, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZZ_H, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_PPzZZ_S, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_WIDE_PPzZZ_B, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_WIDE_PPzZZ_H, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHI_WIDE_PPzZZ_S, ARM64_INS_CMPHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZI_B, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZI_D, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZI_H, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZI_S, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZZ_B, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZZ_D, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZZ_H, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_PPzZZ_S, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_WIDE_PPzZZ_B, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_WIDE_PPzZZ_H, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPHS_WIDE_PPzZZ_S, ARM64_INS_CMPHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_PPzZI_B, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_PPzZI_D, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_PPzZI_H, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_PPzZI_S, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_WIDE_PPzZZ_B, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_WIDE_PPzZZ_H, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLE_WIDE_PPzZZ_S, ARM64_INS_CMPLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_PPzZI_B, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_PPzZI_D, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_PPzZI_H, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_PPzZI_S, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_WIDE_PPzZZ_B, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_WIDE_PPzZZ_H, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLO_WIDE_PPzZZ_S, ARM64_INS_CMPLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_PPzZI_B, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_PPzZI_D, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_PPzZI_H, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_PPzZI_S, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_WIDE_PPzZZ_B, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_WIDE_PPzZZ_H, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLS_WIDE_PPzZZ_S, ARM64_INS_CMPLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_PPzZI_B, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_PPzZI_D, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_PPzZI_H, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_PPzZI_S, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_WIDE_PPzZZ_B, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_WIDE_PPzZZ_H, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPLT_WIDE_PPzZZ_S, ARM64_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZI_B, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZI_D, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZI_H, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZI_S, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZZ_B, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZZ_D, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZZ_H, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_PPzZZ_S, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_WIDE_PPzZZ_B, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_WIDE_PPzZZ_H, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMPNE_WIDE_PPzZZ_S, ARM64_INS_CMPNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CMTSTv16i8, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv1i64, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv2i32, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv2i64, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv4i16, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv4i32, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv8i16, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CMTSTv8i8, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CNOT_ZPmZ_B, ARM64_INS_CNOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNOT_ZPmZ_D, ARM64_INS_CNOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNOT_ZPmZ_H, ARM64_INS_CNOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNOT_ZPmZ_S, ARM64_INS_CNOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTB_XPiI, ARM64_INS_CNTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTD_XPiI, ARM64_INS_CNTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTH_XPiI, ARM64_INS_CNTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTP_XPP_B, ARM64_INS_CNTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTP_XPP_D, ARM64_INS_CNTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTP_XPP_H, ARM64_INS_CNTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTP_XPP_S, ARM64_INS_CNTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTW_XPiI, ARM64_INS_CNTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNT_ZPmZ_B, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNT_ZPmZ_D, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNT_ZPmZ_H, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNT_ZPmZ_S, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CNTv16i8, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CNTv8i8, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_COMPACT_ZPZ_D, ARM64_INS_COMPACT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_COMPACT_ZPZ_S, ARM64_INS_COMPACT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmI_B, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmI_D, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmI_H, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmI_S, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmR_B, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmR_D, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmR_H, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmR_S, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmV_B, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmV_D, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmV_H, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPmV_S, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPzI_B, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPzI_D, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPzI_H, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPY_ZPzI_S, ARM64_INS_CPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CPYi16, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CPYi32, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CPYi64, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CPYi8, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_CRC32Brr, ARM64_INS_CRC32B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32CBrr, ARM64_INS_CRC32CB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32CHrr, ARM64_INS_CRC32CH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32CWrr, ARM64_INS_CRC32CW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32CXrr, ARM64_INS_CRC32CX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32Hrr, ARM64_INS_CRC32H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32Wrr, ARM64_INS_CRC32W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CRC32Xrr, ARM64_INS_CRC32X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, { AArch64_CSELWr, ARM64_INS_CSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSELXr, ARM64_INS_CSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSINCWr, ARM64_INS_CSINC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSINCXr, ARM64_INS_CSINC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSINVWr, ARM64_INS_CSINV, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSINVXr, ARM64_INS_CSINV, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSNEGWr, ARM64_INS_CSNEG, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CSNEGXr, ARM64_INS_CSNEG, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CTERMEQ_WW, ARM64_INS_CTERMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CTERMEQ_XX, ARM64_INS_CTERMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CTERMNE_WW, ARM64_INS_CTERMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_CTERMNE_XX, ARM64_INS_CTERMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DCPS1, ARM64_INS_DCPS1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DCPS2, ARM64_INS_DCPS2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DCPS3, ARM64_INS_DCPS3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECB_XPiI, ARM64_INS_DECB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECD_XPiI, ARM64_INS_DECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECD_ZPiI, ARM64_INS_DECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECH_XPiI, ARM64_INS_DECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECH_ZPiI, ARM64_INS_DECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_XP_B, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_XP_D, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_XP_H, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_XP_S, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_ZP_D, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_ZP_H, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECP_ZP_S, ARM64_INS_DECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECW_XPiI, ARM64_INS_DECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DECW_ZPiI, ARM64_INS_DECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DMB, ARM64_INS_DMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DRPS, ARM64_INS_DRPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DSB, ARM64_INS_DSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUPM_ZI, ARM64_INS_DUPM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZI_B, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZI_D, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZI_H, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZI_S, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZR_B, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZR_D, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZR_H, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZR_S, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZZI_B, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZZI_D, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZZI_H, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZZI_Q, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUP_ZZI_S, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_DUPv16i8gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv16i8lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv2i32gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv2i32lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv2i64gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv2i64lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv4i16gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv4i16lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv4i32gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv4i32lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv8i16gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv8i16lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv8i8gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_DUPv8i8lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_EONWrs, ARM64_INS_EON, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EONXrs, ARM64_INS_EON, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR3, ARM64_INS_EOR3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORS_PPzPP, ARM64_INS_EORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORV_VPZ_B, ARM64_INS_EORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORV_VPZ_D, ARM64_INS_EORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORV_VPZ_H, ARM64_INS_EORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORV_VPZ_S, ARM64_INS_EORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORWri, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORWrs, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORXri, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORXrs, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_PPzPP, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_ZI, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_ZPmZ_B, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_ZPmZ_D, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_ZPmZ_H, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_ZPmZ_S, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EOR_ZZZ, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EORv16i8, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_EORv8i8, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ERET, ARM64_INS_ERET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ERETAA, ARM64_INS_ERETAA, #ifndef CAPSTONE_DIET { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_ERETAB, ARM64_INS_ERETAB, #ifndef CAPSTONE_DIET { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_EXTRWrri, ARM64_INS_EXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EXTRXrri, ARM64_INS_EXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EXT_ZZI, ARM64_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_EXTv16i8, ARM64_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_EXTv8i8, ARM64_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABD16, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABD32, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABD64, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABD_ZPmZ_D, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABD_ZPmZ_H, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABD_ZPmZ_S, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABDv2f32, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABDv2f64, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABDv4f16, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABDv4f32, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABDv8f16, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABSDr, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FABSHr, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABSSr, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FABS_ZPmZ_D, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABS_ZPmZ_H, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABS_ZPmZ_S, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABSv2f32, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABSv2f64, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABSv4f16, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FABSv4f32, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FABSv8f16, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGE16, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGE32, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGE64, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGE_PPzZZ_D, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGE_PPzZZ_H, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGE_PPzZZ_S, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGEv2f32, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGEv2f64, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGEv4f16, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGEv4f32, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGEv8f16, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGT16, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGT32, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGT64, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGT_PPzZZ_D, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGT_PPzZZ_H, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGT_PPzZZ_S, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGTv2f32, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGTv2f64, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGTv4f16, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FACGTv4f32, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FACGTv8f16, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDA_VPZ_D, ARM64_INS_FADDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDA_VPZ_H, ARM64_INS_FADDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDA_VPZ_S, ARM64_INS_FADDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDDrr, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FADDHrr, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDPv2f32, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDPv2f64, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDPv2i16p, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDPv2i32p, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDPv2i64p, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDPv4f16, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDPv4f32, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDPv8f16, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDSrr, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FADDV_VPZ_D, ARM64_INS_FADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDV_VPZ_H, ARM64_INS_FADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDV_VPZ_S, ARM64_INS_FADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZPmI_D, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZPmI_H, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZPmI_S, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZPmZ_D, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZPmZ_H, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZPmZ_S, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZZZ_D, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZZZ_H, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADD_ZZZ_S, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDv2f32, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDv2f64, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDv4f16, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FADDv4f32, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FADDv8f16, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADD_ZPmZ_D, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADD_ZPmZ_H, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADD_ZPmZ_S, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADDv2f32, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADDv2f64, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADDv4f16, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADDv4f32, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCADDv8f16, ARM64_INS_FCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCCMPDrr, ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCCMPEDrr, ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCCMPEHrr, ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCCMPESrr, ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCCMPHrr, ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCCMPSrr, ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMEQ16, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQ32, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQ64, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQ_PPzZ0_D, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQ_PPzZ0_H, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQ_PPzZ0_S, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQ_PPzZZ_D, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQ_PPzZZ_H, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQ_PPzZZ_S, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQv1i16rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv2f32, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv2f64, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv4f16, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQv4f32, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv4i16rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMEQv8f16, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMEQv8i16rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE16, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE32, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGE64, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGE_PPzZ0_D, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE_PPzZ0_H, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE_PPzZ0_S, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE_PPzZZ_D, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE_PPzZZ_H, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGE_PPzZZ_S, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGEv1i16rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv2f32, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv2f64, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv4f16, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGEv4f32, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv4i16rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGEv8f16, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGEv8i16rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT16, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT32, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGT64, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGT_PPzZ0_D, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT_PPzZ0_H, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT_PPzZ0_S, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT_PPzZZ_D, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT_PPzZZ_H, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGT_PPzZZ_S, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGTv1i16rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv2f32, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv2f64, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv4f16, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGTv4f32, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv4i16rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMGTv8f16, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMGTv8i16rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLA_ZPmZZ_D, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLA_ZPmZZ_H, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLA_ZPmZZ_S, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLA_ZZZI_H, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLA_ZZZI_S, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv2f32, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv2f64, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv4f16, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv4f16_indexed, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv4f32, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv4f32_indexed, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv8f16, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLAv8f16_indexed, ARM64_INS_FCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLE_PPzZ0_D, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLE_PPzZ0_H, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLE_PPzZ0_S, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLEv1i16rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLEv4i16rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLEv8i16rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLT_PPzZ0_D, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLT_PPzZ0_H, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLT_PPzZ0_S, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLTv1i16rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLTv4i16rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCMLTv8i16rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMNE_PPzZ0_D, ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMNE_PPzZ0_H, ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMNE_PPzZ0_S, ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMNE_PPzZZ_D, ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMNE_PPzZZ_H, ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMNE_PPzZZ_S, ARM64_INS_FCMNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMPDri, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPDrr, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPEDri, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPEDrr, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPEHri, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMPEHrr, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMPESri, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPESrr, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPHri, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMPHrr, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMPSri, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMPSrr, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCMUO_PPzZZ_D, ARM64_INS_FCMUO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMUO_PPzZZ_H, ARM64_INS_FCMUO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCMUO_PPzZZ_S, ARM64_INS_FCMUO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCPY_ZPmI_D, ARM64_INS_FCPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCPY_ZPmI_H, ARM64_INS_FCPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCPY_ZPmI_S, ARM64_INS_FCPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCSELDrrr, ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCSELHrrr, ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCSELSrrr, ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTASUWDr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTASUWHr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTASUWSr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTASUXDr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTASUXHr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTASUXSr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTASv1f16, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTASv1i32, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTASv1i64, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTASv2f32, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTASv2f64, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTASv4f16, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTASv4f32, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTASv8f16, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTAUUWHr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTAUUXHr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTAUv1f16, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTAUv4f16, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTAUv8f16, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTDHr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTDSr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTHDr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTHSr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTLv2i32, ARM64_INS_FCVTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTLv4i16, ARM64_INS_FCVTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTLv4i32, ARM64_INS_FCVTL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTLv8i16, ARM64_INS_FCVTL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMSUWHr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMSUXHr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMSv1f16, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMSv4f16, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMSv8f16, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMUUWHr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMUUXHr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTMUv1f16, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMUv4f16, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTMUv8f16, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNSUWHr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNSUXHr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNSv1f16, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNSv4f16, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNSv8f16, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNUUWHr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNUUXHr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTNUv1f16, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNUv4f16, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNUv8f16, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTNv2i32, ARM64_INS_FCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNv4i16, ARM64_INS_FCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNv4i32, ARM64_INS_FCVTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTNv8i16, ARM64_INS_FCVTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPSUWHr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPSUXHr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPSv1f16, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPSv4f16, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPSv8f16, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPUUWHr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPUUXHr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTPUv1f16, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPUv4f16, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTPUv8f16, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTSDr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTSHr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSSWHri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSSXHri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSUWHr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZSUXHr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_DtoD, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_DtoS, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_HtoD, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_HtoH, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_HtoS, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_StoD, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZS_ZPmZ_StoS, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSd, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSh, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSs, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv1f16, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv4f16, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv4i16_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZSv8f16, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZSv8i16_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUSWHri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUSXHri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUUWHr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZUUXHr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_DtoD, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_DtoS, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_HtoD, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_HtoH, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_HtoS, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_StoD, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZU_ZPmZ_StoS, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUd, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUh, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUs, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv1f16, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv4f16, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv4i16_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FCVTZUv8f16, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVTZUv8i16_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVT_ZPmZ_DtoH, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVT_ZPmZ_DtoS, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVT_ZPmZ_HtoD, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVT_ZPmZ_HtoS, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVT_ZPmZ_StoD, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FCVT_ZPmZ_StoH, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVDrr, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FDIVHrr, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVR_ZPmZ_D, ARM64_INS_FDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVR_ZPmZ_H, ARM64_INS_FDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVR_ZPmZ_S, ARM64_INS_FDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVSrr, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FDIV_ZPmZ_D, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIV_ZPmZ_H, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIV_ZPmZ_S, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVv2f32, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FDIVv2f64, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FDIVv4f16, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDIVv4f32, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FDIVv8f16, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDUP_ZI_D, ARM64_INS_FDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDUP_ZI_H, ARM64_INS_FDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FDUP_ZI_S, ARM64_INS_FDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FEXPA_ZZ_D, ARM64_INS_FEXPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FEXPA_ZZ_H, ARM64_INS_FEXPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FEXPA_ZZ_S, ARM64_INS_FEXPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FJCVTZS, ARM64_INS_FJCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMADDDrrr, ARM64_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMADDHrrr, ARM64_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMADDSrrr, ARM64_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMAD_ZPmZZ_D, ARM64_INS_FMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAD_ZPmZZ_H, ARM64_INS_FMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAD_ZPmZZ_S, ARM64_INS_FMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXDrr, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMAXHrr, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMDrr, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMAXNMHrr, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv2i16p, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv4f16, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMPv8f16, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMSrr, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMAXNMV_VPZ_D, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMV_VPZ_H, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMV_VPZ_S, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMVv4i16v, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMVv8i16v, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNM_ZPmI_D, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNM_ZPmI_H, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNM_ZPmI_S, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNM_ZPmZ_D, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNM_ZPmZ_H, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNM_ZPmZ_S, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMv4f16, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXNMv8f16, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXPv2f32, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXPv2f64, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXPv2i16p, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXPv2i32p, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXPv2i64p, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXPv4f16, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXPv4f32, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXPv8f16, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXSrr, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMAXV_VPZ_D, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXV_VPZ_H, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXV_VPZ_S, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXVv4i16v, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXVv4i32v, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXVv8i16v, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAX_ZPmI_D, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAX_ZPmI_H, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAX_ZPmI_S, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAX_ZPmZ_D, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAX_ZPmZ_H, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAX_ZPmZ_S, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXv2f32, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXv2f64, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXv4f16, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMAXv4f32, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMAXv8f16, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINDrr, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMINHrr, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMDrr, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMINNMHrr, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMPv2i16p, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMPv4f16, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMPv8f16, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMSrr, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMINNMV_VPZ_D, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMV_VPZ_H, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMV_VPZ_S, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMVv4i16v, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMVv8i16v, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNM_ZPmI_D, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNM_ZPmI_H, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNM_ZPmI_S, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNM_ZPmZ_D, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNM_ZPmZ_H, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNM_ZPmZ_S, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMv2f32, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMv2f64, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMv4f16, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINNMv4f32, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINNMv8f16, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINPv2f32, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINPv2f64, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINPv2i16p, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINPv2i32p, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINPv2i64p, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINPv4f16, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINPv4f32, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINPv8f16, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINSrr, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMINV_VPZ_D, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINV_VPZ_H, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINV_VPZ_S, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINVv4i16v, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINVv4i32v, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINVv8i16v, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMIN_ZPmI_D, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMIN_ZPmI_H, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMIN_ZPmI_S, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMIN_ZPmZ_D, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMIN_ZPmZ_H, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMIN_ZPmZ_S, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINv2f32, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINv2f64, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINv4f16, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMINv4f32, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMINv8f16, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLA_ZPmZZ_D, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLA_ZPmZZ_H, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLA_ZPmZZ_S, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLA_ZZZI_D, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLA_ZZZI_H, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLA_ZZZI_S, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLAv1i16_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv2f32, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv2f64, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv4f16, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLAv4f32, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv4i16_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLAv8f16, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLAv8i16_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLS_ZPmZZ_D, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLS_ZPmZZ_H, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLS_ZPmZZ_S, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLS_ZZZI_D, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLS_ZZZI_H, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLS_ZZZI_S, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLSv1i16_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv2f32, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv2f64, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv4f16, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLSv4f32, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv4i16_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMLSv8f16, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMLSv8i16_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVDXHighr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVDXr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVDi, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVDr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVHWr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVHXr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVHi, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVHr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVSWr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVSi, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVSr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVWHr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVWSr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVXDHighr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVXDr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMOVXHr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVv2f32_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMOVv2f64_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMOVv4f16_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMOVv4f32_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMOVv8f16_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMSB_ZPmZZ_D, ARM64_INS_FMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMSB_ZPmZZ_H, ARM64_INS_FMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMSB_ZPmZZ_S, ARM64_INS_FMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMSUBDrrr, ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMSUBHrrr, ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMSUBSrrr, ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMULDrr, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMULHrr, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULSrr, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FMULX16, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULX32, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULX64, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULX_ZPmZ_D, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULX_ZPmZ_H, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULX_ZPmZ_S, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULXv1i16_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv2f32, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv2f64, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv4f16, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULXv4f32, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv4i16_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULXv8f16, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULXv8i16_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZPmI_D, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZPmI_H, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZPmI_S, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZPmZ_D, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZPmZ_H, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZPmZ_S, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZZZI_D, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZZZI_H, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZZZI_S, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZZZ_D, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZZZ_H, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMUL_ZZZ_S, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULv1i16_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULv1i32_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv1i64_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv2f32, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv2f64, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv2i32_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv2i64_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv4f16, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULv4f32, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv4i16_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULv4i32_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FMULv8f16, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FMULv8i16_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNEGDr, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNEGHr, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNEGSr, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNEG_ZPmZ_D, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNEG_ZPmZ_H, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNEG_ZPmZ_S, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNEGv2f32, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FNEGv2f64, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FNEGv4f16, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNEGv4f32, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FNEGv8f16, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMADDDrrr, ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNMADDHrrr, ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMADDSrrr, ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNMAD_ZPmZZ_D, ARM64_INS_FNMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMAD_ZPmZZ_H, ARM64_INS_FNMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMAD_ZPmZZ_S, ARM64_INS_FNMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMLA_ZPmZZ_D, ARM64_INS_FNMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMLA_ZPmZZ_H, ARM64_INS_FNMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMLA_ZPmZZ_S, ARM64_INS_FNMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMLS_ZPmZZ_D, ARM64_INS_FNMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMLS_ZPmZZ_H, ARM64_INS_FNMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMLS_ZPmZZ_S, ARM64_INS_FNMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMSB_ZPmZZ_D, ARM64_INS_FNMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMSB_ZPmZZ_H, ARM64_INS_FNMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMSB_ZPmZZ_S, ARM64_INS_FNMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNMSUBHrrr, ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNMULDrr, ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FNMULHrr, ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FNMULSrr, ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRECPE_ZZ_D, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPE_ZZ_H, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPE_ZZ_S, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPEv1f16, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPEv1i32, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPEv1i64, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPEv2f32, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPEv2f64, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPEv4f16, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPEv4f32, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPEv8f16, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPS16, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPS32, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPS64, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPS_ZZZ_D, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPS_ZZZ_H, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPS_ZZZ_S, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPSv2f32, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPSv2f64, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPSv4f16, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPSv4f32, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPSv8f16, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPX_ZPmZ_D, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPX_ZPmZ_H, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPX_ZPmZ_S, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPXv1f16, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRECPXv1i32, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRECPXv1i64, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTADr, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTAHr, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTASr, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTA_ZPmZ_D, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTA_ZPmZ_H, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTA_ZPmZ_S, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTAv2f32, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTAv2f64, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTAv4f16, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTAv4f32, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTAv8f16, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTIDr, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTIHr, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTISr, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTI_ZPmZ_D, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTI_ZPmZ_H, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTI_ZPmZ_S, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTIv2f32, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTIv2f64, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTIv4f16, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTIv4f32, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTIv8f16, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTMDr, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTMHr, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTMSr, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTM_ZPmZ_D, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTM_ZPmZ_H, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTM_ZPmZ_S, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTMv2f32, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTMv2f64, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTMv4f16, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTMv4f32, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTMv8f16, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTNDr, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTNHr, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTNSr, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTN_ZPmZ_D, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTN_ZPmZ_H, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTN_ZPmZ_S, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTNv2f32, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTNv2f64, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTNv4f16, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTNv4f32, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTNv8f16, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTPDr, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTPHr, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTPSr, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTP_ZPmZ_D, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTP_ZPmZ_H, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTP_ZPmZ_S, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTPv2f32, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTPv2f64, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTPv4f16, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTPv4f32, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTPv8f16, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTXDr, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTXHr, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTXSr, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTX_ZPmZ_D, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTX_ZPmZ_H, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTX_ZPmZ_S, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTXv2f32, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTXv2f64, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTXv4f16, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTXv4f32, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTXv8f16, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTZDr, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTZHr, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTZSr, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FRINTZ_ZPmZ_D, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTZ_ZPmZ_H, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTZ_ZPmZ_S, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTZv2f32, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTZv2f64, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTZv4f16, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRINTZv4f32, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRINTZv8f16, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTE_ZZ_D, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTE_ZZ_H, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTE_ZZ_S, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv1f16, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv4f16, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTEv8f16, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTS16, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTS32, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTS64, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTS_ZZZ_D, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTS_ZZZ_H, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTS_ZZZ_S, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTSv4f16, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FRSQRTSv8f16, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSCALE_ZPmZ_D, ARM64_INS_FSCALE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSCALE_ZPmZ_H, ARM64_INS_FSCALE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSCALE_ZPmZ_S, ARM64_INS_FSCALE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSQRTDr, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FSQRTHr, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSQRTSr, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FSQRT_ZPmZ_D, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSQRT_ZPmZ_H, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSQRT_ZPmZ_S, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSQRTv2f32, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FSQRTv2f64, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FSQRTv4f16, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSQRTv4f32, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FSQRTv8f16, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBDrr, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FSUBHrr, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBR_ZPmI_D, ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBR_ZPmI_H, ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBR_ZPmI_S, ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBR_ZPmZ_D, ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBR_ZPmZ_H, ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBR_ZPmZ_S, ARM64_INS_FSUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBSrr, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_FSUB_ZPmI_D, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZPmI_H, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZPmI_S, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZPmZ_D, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZPmZ_H, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZPmZ_S, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZZZ_D, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZZZ_H, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUB_ZZZ_S, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBv2f32, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FSUBv2f64, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FSUBv4f16, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FSUBv4f32, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_FSUBv8f16, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTMAD_ZZI_D, ARM64_INS_FTMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTMAD_ZZI_H, ARM64_INS_FTMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTMAD_ZZI_S, ARM64_INS_FTMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTSMUL_ZZZ_D, ARM64_INS_FTSMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTSMUL_ZZZ_H, ARM64_INS_FTSMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTSMUL_ZZZ_S, ARM64_INS_FTSMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTSSEL_ZZZ_D, ARM64_INS_FTSSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTSSEL_ZZZ_H, ARM64_INS_FTSSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_FTSSEL_ZZZ_S, ARM64_INS_FTSSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_D_IMM_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_D_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_D_SXTW_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_D_UXTW_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_S_IMM_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_S_SXTW_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1B_S_UXTW_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_IMM_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_SCALED_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_SXTW_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_SXTW_SCALED_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_UXTW_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1D_UXTW_SCALED_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_IMM_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_SCALED_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_SXTW_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_SXTW_SCALED_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_UXTW_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_D_UXTW_SCALED_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_S_IMM_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_S_SXTW_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_S_SXTW_SCALED_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_S_UXTW_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1H_S_UXTW_SCALED_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_D_IMM_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_D_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_D_SXTW_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_D_UXTW_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_S_IMM_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_S_SXTW_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SB_S_UXTW_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_IMM_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_SCALED_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_SXTW_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_SXTW_SCALED_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_UXTW_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_D_UXTW_SCALED_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_S_IMM_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_S_SXTW_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_S_SXTW_SCALED_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_S_UXTW_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SH_S_UXTW_SCALED_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_IMM_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_SCALED_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_SXTW_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_SXTW_SCALED_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_UXTW_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1SW_D_UXTW_SCALED_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_IMM_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_SCALED_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_SXTW_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_SXTW_SCALED_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_UXTW_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_D_UXTW_SCALED_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_IMM_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_SXTW_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_SXTW_SCALED_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_UXTW_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLD1W_UXTW_SCALED_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_D_IMM_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_D_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_D_SXTW_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_D_UXTW_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_S_IMM_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_S_SXTW_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1B_S_UXTW_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_IMM_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_SCALED_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_SXTW_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_SXTW_SCALED_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_UXTW_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1D_UXTW_SCALED_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_IMM_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_SCALED_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_SXTW_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_UXTW_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_S_IMM_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_S_SXTW_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_S_SXTW_SCALED_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_S_UXTW_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1H_S_UXTW_SCALED_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_D_IMM_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_D_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_D_SXTW_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_D_UXTW_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_S_IMM_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_S_SXTW_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SB_S_UXTW_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_IMM_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_SCALED_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_SXTW_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_UXTW_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_S_IMM_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_S_SXTW_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_S_UXTW_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_IMM_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_SCALED_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_SXTW_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_UXTW_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_IMM_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_SCALED_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_SXTW_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_UXTW_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_IMM_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_SXTW_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_SXTW_SCALED_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_UXTW_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_GLDFF1W_UXTW_SCALED_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_HINT, ARM64_INS_HINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_HLT, ARM64_INS_HLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_HVC, ARM64_INS_HVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCB_XPiI, ARM64_INS_INCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCD_XPiI, ARM64_INS_INCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCD_ZPiI, ARM64_INS_INCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCH_XPiI, ARM64_INS_INCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCH_ZPiI, ARM64_INS_INCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_XP_B, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_XP_D, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_XP_H, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_XP_S, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_ZP_D, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_ZP_H, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCP_ZP_S, ARM64_INS_INCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCW_XPiI, ARM64_INS_INCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INCW_ZPiI, ARM64_INS_INCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_II_B, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_II_D, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_II_H, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_II_S, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_IR_B, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_IR_D, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_IR_H, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_IR_S, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RI_B, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RI_D, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RI_H, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RI_S, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RR_B, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RR_D, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RR_H, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INDEX_RR_S, ARM64_INS_INDEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZR_B, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZR_D, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZR_H, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZR_S, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZV_B, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZV_D, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZV_H, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSR_ZV_S, ARM64_INS_INSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_INSvi16gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi16lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi32gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi32lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi64gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi64lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi8gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_INSvi8lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ISB, ARM64_INS_ISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_RPZ_B, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_RPZ_D, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_RPZ_H, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_RPZ_S, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_VPZ_B, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_VPZ_D, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_VPZ_H, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTA_VPZ_S, ARM64_INS_LASTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_RPZ_B, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_RPZ_D, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_RPZ_H, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_RPZ_S, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_VPZ_B, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_VPZ_D, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_VPZ_H, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LASTB_VPZ_S, ARM64_INS_LASTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_D, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_D_IMM_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_H, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_H_IMM_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_IMM_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_S, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1B_S_IMM_REAL, ARM64_INS_LD1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1D, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1D_IMM_REAL, ARM64_INS_LD1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1Fourv16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Fourv8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1H, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1H_D, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1H_D_IMM_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1H_IMM_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1H_S, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1H_S_IMM_REAL, ARM64_INS_LD1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1Onev16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Onev8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1RB_D_IMM, ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RB_H_IMM, ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RB_IMM, ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RB_S_IMM, ARM64_INS_LD1RB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RD_IMM, ARM64_INS_LD1RD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RH_D_IMM, ARM64_INS_LD1RH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RH_IMM, ARM64_INS_LD1RH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RH_S_IMM, ARM64_INS_LD1RH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_B, ARM64_INS_LD1RQB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_B_IMM, ARM64_INS_LD1RQB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_D, ARM64_INS_LD1RQD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_D_IMM, ARM64_INS_LD1RQD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_H, ARM64_INS_LD1RQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_H_IMM, ARM64_INS_LD1RQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_W, ARM64_INS_LD1RQW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RQ_W_IMM, ARM64_INS_LD1RQW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RSB_D_IMM, ARM64_INS_LD1RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RSB_H_IMM, ARM64_INS_LD1RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RSB_S_IMM, ARM64_INS_LD1RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RSH_D_IMM, ARM64_INS_LD1RSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RSH_S_IMM, ARM64_INS_LD1RSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RSW_IMM, ARM64_INS_LD1RSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RW_D_IMM, ARM64_INS_LD1RW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1RW_IMM, ARM64_INS_LD1RW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1Rv16b, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv16b_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv1d, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv1d_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv2d, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv2d_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv2s, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv2s_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv4h, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv4h_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv4s, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv4s_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv8b, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv8b_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv8h, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Rv8h_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1SB_D, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SB_D_IMM_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SB_H, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SB_H_IMM_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SB_S, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SB_S_IMM_REAL, ARM64_INS_LD1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SH_D, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SH_D_IMM_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SH_S, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SH_S_IMM_REAL, ARM64_INS_LD1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SW_D, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1SW_D_IMM_REAL, ARM64_INS_LD1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1Threev16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Threev8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1Twov8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1W, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1W_D, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1W_D_IMM_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1W_IMM_REAL, ARM64_INS_LD1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD1i16, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i16_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i32, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i32_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i64, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i64_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i8, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD1i8_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2B, ARM64_INS_LD2B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2B_IMM, ARM64_INS_LD2B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2D, ARM64_INS_LD2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2D_IMM, ARM64_INS_LD2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2H, ARM64_INS_LD2H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2H_IMM, ARM64_INS_LD2H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2Rv16b, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv16b_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv1d, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv1d_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv2d, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv2d_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv2s, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv2s_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv4h, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv4h_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv4s, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv4s_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv8b, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv8b_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv8h, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Rv8h_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov16b, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov16b_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov2d, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov2d_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov2s, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov2s_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov4h, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov4h_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov4s, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov4s_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov8b, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov8b_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov8h, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2Twov8h_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2W, ARM64_INS_LD2W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2W_IMM, ARM64_INS_LD2W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD2i16, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i16_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i32, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i32_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i64, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i64_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i8, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD2i8_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3B, ARM64_INS_LD3B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3B_IMM, ARM64_INS_LD3B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3D, ARM64_INS_LD3D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3D_IMM, ARM64_INS_LD3D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3H, ARM64_INS_LD3H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3H_IMM, ARM64_INS_LD3H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3Rv16b, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv16b_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv1d, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv1d_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv2d, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv2d_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv2s, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv2s_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv4h, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv4h_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv4s, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv4s_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv8b, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv8b_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv8h, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Rv8h_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev16b, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev16b_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev2d, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev2d_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev2s, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev2s_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev4h, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev4h_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev4s, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev4s_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev8b, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev8b_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev8h, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3Threev8h_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3W, ARM64_INS_LD3W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3W_IMM, ARM64_INS_LD3W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD3i16, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i16_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i32, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i32_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i64, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i64_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i8, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD3i8_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4B, ARM64_INS_LD4B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4B_IMM, ARM64_INS_LD4B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4D, ARM64_INS_LD4D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4D_IMM, ARM64_INS_LD4D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4Fourv16b, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv16b_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv2d, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv2d_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv2s, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv2s_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv4h, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv4h_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv4s, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv4s_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv8b, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv8b_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv8h, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Fourv8h_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4H, ARM64_INS_LD4H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4H_IMM, ARM64_INS_LD4H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4Rv16b, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv16b_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv1d, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv1d_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv2d, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv2d_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv2s, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv2s_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv4h, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv4h_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv4s, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv4s_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv8b, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv8b_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv8h, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4Rv8h_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4W, ARM64_INS_LD4W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4W_IMM, ARM64_INS_LD4W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LD4i16, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i16_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i32, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i32_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i64, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i64_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i8, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LD4i8_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_LDADDAB, ARM64_INS_LDADDAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDAH, ARM64_INS_LDADDAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDALB, ARM64_INS_LDADDALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDALH, ARM64_INS_LDADDALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDALW, ARM64_INS_LDADDAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDALX, ARM64_INS_LDADDAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDAW, ARM64_INS_LDADDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDAX, ARM64_INS_LDADDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDB, ARM64_INS_LDADDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDH, ARM64_INS_LDADDH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDLB, ARM64_INS_LDADDLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDLH, ARM64_INS_LDADDLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDLW, ARM64_INS_LDADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDLX, ARM64_INS_LDADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDW, ARM64_INS_LDADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDADDX, ARM64_INS_LDADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPRB, ARM64_INS_LDAPRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPRH, ARM64_INS_LDAPRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPRW, ARM64_INS_LDAPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPRX, ARM64_INS_LDAPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURBi, ARM64_INS_LDAPURB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURHi, ARM64_INS_LDAPURH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURSBWi, ARM64_INS_LDAPURSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURSBXi, ARM64_INS_LDAPURSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURSHWi, ARM64_INS_LDAPURSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURSHXi, ARM64_INS_LDAPURSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURSWi, ARM64_INS_LDAPURSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURXi, ARM64_INS_LDAPUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAPURi, ARM64_INS_LDAPUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDARB, ARM64_INS_LDARB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDARH, ARM64_INS_LDARH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDARW, ARM64_INS_LDAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDARX, ARM64_INS_LDAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAXPW, ARM64_INS_LDAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAXPX, ARM64_INS_LDAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAXRB, ARM64_INS_LDAXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAXRH, ARM64_INS_LDAXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAXRW, ARM64_INS_LDAXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDAXRX, ARM64_INS_LDAXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRAB, ARM64_INS_LDCLRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRAH, ARM64_INS_LDCLRAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRALB, ARM64_INS_LDCLRALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRALH, ARM64_INS_LDCLRALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRALW, ARM64_INS_LDCLRAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRALX, ARM64_INS_LDCLRAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRAW, ARM64_INS_LDCLRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRAX, ARM64_INS_LDCLRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRB, ARM64_INS_LDCLRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRH, ARM64_INS_LDCLRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRLB, ARM64_INS_LDCLRLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRLH, ARM64_INS_LDCLRLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRLW, ARM64_INS_LDCLRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRLX, ARM64_INS_LDCLRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRW, ARM64_INS_LDCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDCLRX, ARM64_INS_LDCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORAB, ARM64_INS_LDEORAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORAH, ARM64_INS_LDEORAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORALB, ARM64_INS_LDEORALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORALH, ARM64_INS_LDEORALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORALW, ARM64_INS_LDEORAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORALX, ARM64_INS_LDEORAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORAW, ARM64_INS_LDEORA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORAX, ARM64_INS_LDEORA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORB, ARM64_INS_LDEORB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORH, ARM64_INS_LDEORH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORLB, ARM64_INS_LDEORLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORLH, ARM64_INS_LDEORLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORLW, ARM64_INS_LDEORL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORLX, ARM64_INS_LDEORL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORW, ARM64_INS_LDEOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDEORX, ARM64_INS_LDEOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1B_D_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1B_H_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1B_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1B_S_REAL, ARM64_INS_LDFF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1D_REAL, ARM64_INS_LDFF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1H_D_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1H_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1H_S_REAL, ARM64_INS_LDFF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1SB_D_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1SB_H_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1SB_S_REAL, ARM64_INS_LDFF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1SH_D_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1SH_S_REAL, ARM64_INS_LDFF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1SW_D_REAL, ARM64_INS_LDFF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1W_D_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDFF1W_REAL, ARM64_INS_LDFF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDLARB, ARM64_INS_LDLARB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDLARH, ARM64_INS_LDLARH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDLARW, ARM64_INS_LDLAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDLARX, ARM64_INS_LDLAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1B_D_IMM_REAL, ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1B_H_IMM_REAL, ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1B_IMM_REAL, ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1B_S_IMM_REAL, ARM64_INS_LDNF1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1D_IMM_REAL, ARM64_INS_LDNF1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1H_D_IMM_REAL, ARM64_INS_LDNF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1H_IMM_REAL, ARM64_INS_LDNF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1H_S_IMM_REAL, ARM64_INS_LDNF1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1SB_D_IMM_REAL, ARM64_INS_LDNF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1SB_H_IMM_REAL, ARM64_INS_LDNF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1SB_S_IMM_REAL, ARM64_INS_LDNF1SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1SH_D_IMM_REAL, ARM64_INS_LDNF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1SH_S_IMM_REAL, ARM64_INS_LDNF1SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1SW_D_IMM_REAL, ARM64_INS_LDNF1SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1W_D_IMM_REAL, ARM64_INS_LDNF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNF1W_IMM_REAL, ARM64_INS_LDNF1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNPDi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNPQi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNPSi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNPWi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNPXi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1B_ZRI, ARM64_INS_LDNT1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1B_ZRR, ARM64_INS_LDNT1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1D_ZRI, ARM64_INS_LDNT1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1D_ZRR, ARM64_INS_LDNT1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1H_ZRI, ARM64_INS_LDNT1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1H_ZRR, ARM64_INS_LDNT1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1W_ZRI, ARM64_INS_LDNT1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDNT1W_ZRR, ARM64_INS_LDNT1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPDi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPDpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPDpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPQi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPQpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPQpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPSWi, ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPSWpost, ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPSWpre, ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPSi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPSpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPSpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPWi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPWpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPWpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPXi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPXpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDPXpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRAAindexed, ARM64_INS_LDRAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRAAwriteback, ARM64_INS_LDRAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRABindexed, ARM64_INS_LDRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRABwriteback, ARM64_INS_LDRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBBpost, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBBpre, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBBroW, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBBroX, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBBui, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRBui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRDl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRDpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRDpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRDroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRDroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRDui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHHpost, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHHpre, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHHroW, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHHroX, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHHui, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRHui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRQl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRQpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRQpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRQroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRQroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRQui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBWpost, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBWpre, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBWroW, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBWroX, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBWui, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBXpost, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBXpre, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBXroW, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBXroX, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSBXui, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHWpost, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHWpre, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHWroW, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHWroX, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHWui, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHXpost, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHXpre, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHXroW, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHXroX, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSHXui, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSWl, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSWpost, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSWpre, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSWroW, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSWroX, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSWui, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRSui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRWl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRWpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRWpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRWroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRWroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRWui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRXl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRXpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRXpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRXroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRXroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDRXui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDR_PXI, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDR_ZXI, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETAB, ARM64_INS_LDSETAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETAH, ARM64_INS_LDSETAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETALB, ARM64_INS_LDSETALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETALH, ARM64_INS_LDSETALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETALW, ARM64_INS_LDSETAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETALX, ARM64_INS_LDSETAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETAW, ARM64_INS_LDSETA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETAX, ARM64_INS_LDSETA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETB, ARM64_INS_LDSETB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETH, ARM64_INS_LDSETH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETLB, ARM64_INS_LDSETLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETLH, ARM64_INS_LDSETLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETLW, ARM64_INS_LDSETL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETLX, ARM64_INS_LDSETL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETW, ARM64_INS_LDSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSETX, ARM64_INS_LDSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXAB, ARM64_INS_LDSMAXAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXAH, ARM64_INS_LDSMAXAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXALB, ARM64_INS_LDSMAXALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXALH, ARM64_INS_LDSMAXALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXALW, ARM64_INS_LDSMAXAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXALX, ARM64_INS_LDSMAXAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXAW, ARM64_INS_LDSMAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXAX, ARM64_INS_LDSMAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXB, ARM64_INS_LDSMAXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXH, ARM64_INS_LDSMAXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXLB, ARM64_INS_LDSMAXLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXLH, ARM64_INS_LDSMAXLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXLW, ARM64_INS_LDSMAXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXLX, ARM64_INS_LDSMAXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXW, ARM64_INS_LDSMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMAXX, ARM64_INS_LDSMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINAB, ARM64_INS_LDSMINAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINAH, ARM64_INS_LDSMINAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINALB, ARM64_INS_LDSMINALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINALH, ARM64_INS_LDSMINALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINALW, ARM64_INS_LDSMINAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINALX, ARM64_INS_LDSMINAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINAW, ARM64_INS_LDSMINA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINAX, ARM64_INS_LDSMINA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINB, ARM64_INS_LDSMINB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINH, ARM64_INS_LDSMINH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINLB, ARM64_INS_LDSMINLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINLH, ARM64_INS_LDSMINLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINLW, ARM64_INS_LDSMINL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINLX, ARM64_INS_LDSMINL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINW, ARM64_INS_LDSMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDSMINX, ARM64_INS_LDSMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRBi, ARM64_INS_LDTRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRHi, ARM64_INS_LDTRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRSBWi, ARM64_INS_LDTRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRSBXi, ARM64_INS_LDTRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRSHWi, ARM64_INS_LDTRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRSHXi, ARM64_INS_LDTRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRSWi, ARM64_INS_LDTRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRWi, ARM64_INS_LDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDTRXi, ARM64_INS_LDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXAB, ARM64_INS_LDUMAXAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXAH, ARM64_INS_LDUMAXAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXALB, ARM64_INS_LDUMAXALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXALH, ARM64_INS_LDUMAXALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXALW, ARM64_INS_LDUMAXAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXALX, ARM64_INS_LDUMAXAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXAW, ARM64_INS_LDUMAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXAX, ARM64_INS_LDUMAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXB, ARM64_INS_LDUMAXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXH, ARM64_INS_LDUMAXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXLB, ARM64_INS_LDUMAXLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXLH, ARM64_INS_LDUMAXLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXLW, ARM64_INS_LDUMAXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXLX, ARM64_INS_LDUMAXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXW, ARM64_INS_LDUMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMAXX, ARM64_INS_LDUMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINAB, ARM64_INS_LDUMINAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINAH, ARM64_INS_LDUMINAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINALB, ARM64_INS_LDUMINALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINALH, ARM64_INS_LDUMINALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINALW, ARM64_INS_LDUMINAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINALX, ARM64_INS_LDUMINAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINAW, ARM64_INS_LDUMINA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINAX, ARM64_INS_LDUMINA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINB, ARM64_INS_LDUMINB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINH, ARM64_INS_LDUMINH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINLB, ARM64_INS_LDUMINLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINLH, ARM64_INS_LDUMINLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINLW, ARM64_INS_LDUMINL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINLX, ARM64_INS_LDUMINL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINW, ARM64_INS_LDUMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDUMINX, ARM64_INS_LDUMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURBBi, ARM64_INS_LDURB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURBi, ARM64_INS_LDURB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURDi, ARM64_INS_LDUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURHHi, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURHi, ARM64_INS_LDUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURQi, ARM64_INS_LDUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURSBWi, ARM64_INS_LDURSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURSBXi, ARM64_INS_LDURSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURSHWi, ARM64_INS_LDURSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURSHXi, ARM64_INS_LDURSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURSWi, ARM64_INS_LDURSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURSi, ARM64_INS_LDUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURWi, ARM64_INS_LDUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDURXi, ARM64_INS_LDUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDXPW, ARM64_INS_LDXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDXPX, ARM64_INS_LDXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDXRB, ARM64_INS_LDXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDXRH, ARM64_INS_LDXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDXRW, ARM64_INS_LDXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LDXRX, ARM64_INS_LDXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSLR_ZPmZ_B, ARM64_INS_LSLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSLR_ZPmZ_D, ARM64_INS_LSLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSLR_ZPmZ_H, ARM64_INS_LSLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSLR_ZPmZ_S, ARM64_INS_LSLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSLVWr, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSLVXr, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_WIDE_ZPmZ_B, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_WIDE_ZPmZ_H, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_WIDE_ZPmZ_S, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_WIDE_ZZZ_B, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_WIDE_ZZZ_H, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_WIDE_ZZZ_S, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmI_B, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmI_D, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmI_H, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmI_S, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmZ_B, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmZ_D, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmZ_H, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZPmZ_S, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZZI_B, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZZI_D, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZZI_H, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSL_ZZI_S, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSRR_ZPmZ_B, ARM64_INS_LSRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSRR_ZPmZ_D, ARM64_INS_LSRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSRR_ZPmZ_H, ARM64_INS_LSRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSRR_ZPmZ_S, ARM64_INS_LSRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSRVWr, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSRVXr, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_WIDE_ZPmZ_B, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_WIDE_ZPmZ_H, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_WIDE_ZPmZ_S, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_WIDE_ZZZ_B, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_WIDE_ZZZ_H, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_WIDE_ZZZ_S, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmI_B, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmI_D, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmI_H, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmI_S, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmZ_B, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmZ_D, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmZ_H, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZPmZ_S, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZZI_B, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZZI_D, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZZI_H, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_LSR_ZZI_S, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MADDWrrr, ARM64_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MADDXrrr, ARM64_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MAD_ZPmZZ_B, ARM64_INS_MAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MAD_ZPmZZ_D, ARM64_INS_MAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MAD_ZPmZZ_H, ARM64_INS_MAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MAD_ZPmZZ_S, ARM64_INS_MAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLA_ZPmZZ_B, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLA_ZPmZZ_D, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLA_ZPmZZ_H, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLA_ZPmZZ_S, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLAv16i8, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv2i32, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv2i32_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv4i16, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv4i16_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv4i32, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv4i32_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv8i16, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv8i16_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLAv8i8, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLS_ZPmZZ_B, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLS_ZPmZZ_D, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLS_ZPmZZ_H, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLS_ZPmZZ_S, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MLSv16i8, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv2i32, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv2i32_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv4i16, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv4i16_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv4i32, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv4i32_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv8i16, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv8i16_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MLSv8i8, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVID, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv16b_ns, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv2d_ns, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv2i32, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv2s_msl, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv4i16, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv4i32, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv4s_msl, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv8b_ns, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVIv8i16, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MOVKWi, ARM64_INS_MOVK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVKXi, ARM64_INS_MOVK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVNWi, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVNXi, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPmZ_B, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPmZ_D, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPmZ_H, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPmZ_S, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPzZ_B, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPzZ_D, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPzZ_H, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZPzZ_S, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVPRFX_ZZ, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVZWi, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MOVZXi, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MRS, ARM64_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { AArch64_MSB_ZPmZZ_B, ARM64_INS_MSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MSB_ZPmZZ_D, ARM64_INS_MSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MSB_ZPmZZ_H, ARM64_INS_MSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MSB_ZPmZZ_S, ARM64_INS_MSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MSR, ARM64_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { AArch64_MSRpstateImm1, ARM64_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { AArch64_MSRpstateImm4, ARM64_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { AArch64_MSUBWrrr, ARM64_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MSUBXrrr, ARM64_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZI_B, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZI_D, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZI_H, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZI_S, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZPmZ_B, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZPmZ_D, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZPmZ_H, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MUL_ZPmZ_S, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_MULv16i8, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv2i32, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv2i32_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv4i16, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv4i16_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv4i32, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv4i32_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv8i16, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv8i16_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MULv8i8, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MVNIv2i32, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MVNIv2s_msl, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MVNIv4i16, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MVNIv4i32, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MVNIv4s_msl, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_MVNIv8i16, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NANDS_PPzPP, ARM64_INS_NANDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NAND_PPzPP, ARM64_INS_NAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NEG_ZPmZ_B, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NEG_ZPmZ_D, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NEG_ZPmZ_H, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NEG_ZPmZ_S, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NEGv16i8, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv1i64, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv2i32, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv2i64, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv4i16, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv4i32, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv8i16, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NEGv8i8, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NORS_PPzPP, ARM64_INS_NORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NOR_PPzPP, ARM64_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NOT_ZPmZ_B, ARM64_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NOT_ZPmZ_D, ARM64_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NOT_ZPmZ_H, ARM64_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NOT_ZPmZ_S, ARM64_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_NOTv16i8, ARM64_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_NOTv8i8, ARM64_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORNS_PPzPP, ARM64_INS_ORNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORNWrs, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORNXrs, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORN_PPzPP, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORNv16i8, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORNv8i8, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORRS_PPzPP, ARM64_INS_ORRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORRWri, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORRWrs, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORRXri, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORRXrs, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_PPzPP, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_ZI, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_ZPmZ_B, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_ZPmZ_D, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_ZPmZ_H, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_ZPmZ_S, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORR_ZZZ, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORRv16i8, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORRv2i32, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORRv4i16, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORRv4i32, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORRv8i16, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORRv8i8, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ORV_VPZ_B, ARM64_INS_ORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORV_VPZ_D, ARM64_INS_ORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORV_VPZ_H, ARM64_INS_ORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ORV_VPZ_S, ARM64_INS_ORV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PACDA, ARM64_INS_PACDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACDB, ARM64_INS_PACDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACDZA, ARM64_INS_PACDZA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACDZB, ARM64_INS_PACDZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACGA, ARM64_INS_PACGA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIA, ARM64_INS_PACIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIA1716, ARM64_INS_PACIA1716, #ifndef CAPSTONE_DIET { ARM64_REG_X17, 0 }, { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIASP, ARM64_INS_PACIASP, #ifndef CAPSTONE_DIET { ARM64_REG_LR, 0 }, { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIAZ, ARM64_INS_PACIAZ, #ifndef CAPSTONE_DIET { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIB, ARM64_INS_PACIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIB1716, ARM64_INS_PACIB1716, #ifndef CAPSTONE_DIET { ARM64_REG_X17, 0 }, { ARM64_REG_X16, ARM64_REG_X17, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIBSP, ARM64_INS_PACIBSP, #ifndef CAPSTONE_DIET { ARM64_REG_LR, 0 }, { ARM64_REG_LR, ARM64_REG_SP, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIBZ, ARM64_INS_PACIBZ, #ifndef CAPSTONE_DIET { ARM64_REG_LR, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIZA, ARM64_INS_PACIZA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PACIZB, ARM64_INS_PACIZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_PFALSE, ARM64_INS_PFALSE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PMULLv16i8, ARM64_INS_PMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_PMULLv1i64, ARM64_INS_PMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_PMULLv2i64, ARM64_INS_PMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_PMULLv8i8, ARM64_INS_PMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_PMULv16i8, ARM64_INS_PMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_PMULv8i8, ARM64_INS_PMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_PNEXT_B, ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PNEXT_D, ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PNEXT_H, ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PNEXT_S, ARM64_INS_PNEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_D_PZI, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_D_SCALED, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_D_SXTW_SCALED, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_D_UXTW_SCALED, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_PRI, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_PRR, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_S_PZI, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_S_SXTW_SCALED, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFB_S_UXTW_SCALED, ARM64_INS_PRFB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_D_PZI, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_D_SCALED, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_D_SXTW_SCALED, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_D_UXTW_SCALED, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_PRI, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_PRR, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_S_PZI, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_S_SXTW_SCALED, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFD_S_UXTW_SCALED, ARM64_INS_PRFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_D_PZI, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_D_SCALED, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_D_SXTW_SCALED, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_D_UXTW_SCALED, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_PRI, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_PRR, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_S_PZI, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_S_SXTW_SCALED, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFH_S_UXTW_SCALED, ARM64_INS_PRFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFMl, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFMroW, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFMroX, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFMui, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFS_PRR, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFUMi, ARM64_INS_PRFUM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_D_PZI, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_D_SCALED, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_D_SXTW_SCALED, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_D_UXTW_SCALED, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_PRI, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_S_PZI, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_S_SXTW_SCALED, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PRFW_S_UXTW_SCALED, ARM64_INS_PRFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTEST_PP, ARM64_INS_PTEST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUES_B, ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUES_D, ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUES_H, ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUES_S, ARM64_INS_PTRUES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUE_B, ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUE_D, ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUE_H, ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PTRUE_S, ARM64_INS_PTRUE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PUNPKHI_PP, ARM64_INS_PUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_PUNPKLO_PP, ARM64_INS_PUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RAX1, ARM64_INS_RAX1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBITWr, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBITXr, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBIT_ZPmZ_B, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBIT_ZPmZ_D, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBIT_ZPmZ_H, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBIT_ZPmZ_S, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RBITv16i8, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RBITv8i8, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RDFFRS_PPz, ARM64_INS_RDFFRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RDFFR_P, ARM64_INS_RDFFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RDFFR_PPz, ARM64_INS_RDFFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RDVLI_XI, ARM64_INS_RDVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RET, ARM64_INS_RET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_RET, 0 }, 0, 0 #endif }, { AArch64_RETAA, ARM64_INS_RETAA, #ifndef CAPSTONE_DIET { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0 #endif }, { AArch64_RETAB, ARM64_INS_RETAB, #ifndef CAPSTONE_DIET { ARM64_REG_LR, ARM64_REG_SP, 0 }, { 0 }, { ARM64_GRP_PAC, ARM64_GRP_RET, 0 }, 0, 0 #endif }, { AArch64_REV16Wr, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV16Xr, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV16v16i8, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV16v8i8, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV32Xr, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV32v16i8, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV32v4i16, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV32v8i16, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV32v8i8, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV64v16i8, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV64v2i32, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV64v4i16, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV64v4i32, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV64v8i16, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REV64v8i8, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_REVB_ZPmZ_D, ARM64_INS_REVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVB_ZPmZ_H, ARM64_INS_REVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVB_ZPmZ_S, ARM64_INS_REVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVH_ZPmZ_D, ARM64_INS_REVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVH_ZPmZ_S, ARM64_INS_REVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVW_ZPmZ_D, ARM64_INS_REVW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVWr, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REVXr, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_PP_B, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_PP_D, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_PP_H, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_PP_S, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_ZZ_B, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_ZZ_D, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_ZZ_H, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_REV_ZZ_S, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RMIF, ARM64_INS_RMIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RORVWr, ARM64_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RORVXr, ARM64_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABAv16i8, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABAv2i32, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABAv4i16, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABAv4i32, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABAv8i16, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABAv8i8, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABD_ZPmZ_B, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SABD_ZPmZ_D, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SABD_ZPmZ_H, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SABD_ZPmZ_S, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SABDv16i8, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDv2i32, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDv4i16, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDv4i32, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDv8i16, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SABDv8i8, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLVv16i8v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLVv4i16v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLVv4i32v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLVv8i16v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLVv8i8v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDV_VPZ_B, ARM64_INS_SADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SADDV_VPZ_H, ARM64_INS_SADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SADDV_VPZ_S, ARM64_INS_SADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SBCSWr, ARM64_INS_SBCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SBCSXr, ARM64_INS_SBCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SBCWr, ARM64_INS_SBC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SBCXr, ARM64_INS_SBC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SBFMWri, ARM64_INS_SBFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SBFMXri, ARM64_INS_SBFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFSWDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFSWHri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFSWSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFSXDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFSXHri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFSXSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFUWDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFUWHri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFUWSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFUXDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTFUXHri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFUXSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_DtoD, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_DtoH, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_DtoS, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_HtoH, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_StoD, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_StoH, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTF_ZPmZ_StoS, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFd, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFh, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFs, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv1i16, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFv1i32, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv1i64, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv2f32, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv2f64, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv4f16, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFv4f32, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv4i16_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SCVTFv8f16, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SCVTFv8i16_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDIVR_ZPmZ_D, ARM64_INS_SDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDIVR_ZPmZ_S, ARM64_INS_SDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDIVWr, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDIVXr, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDIV_ZPmZ_D, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDIV_ZPmZ_S, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOT_ZZZI_D, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOT_ZZZI_S, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOT_ZZZ_D, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOT_ZZZ_S, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOTlanev16i8, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOTlanev8i8, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOTv16i8, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SDOTv8i8, ARM64_INS_SDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SEL_PPPP, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SEL_ZPZZ_B, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SEL_ZPZZ_D, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SEL_ZPZZ_H, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SEL_ZPZZ_S, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SETF16, ARM64_INS_SETF16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SETF8, ARM64_INS_SETF8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SETFFR, ARM64_INS_SETFFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SHA1Crrr, ARM64_INS_SHA1C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA1Hrr, ARM64_INS_SHA1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA1Mrrr, ARM64_INS_SHA1M, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA1Prrr, ARM64_INS_SHA1P, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA256H2rrr, ARM64_INS_SHA256H2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA256Hrrr, ARM64_INS_SHA256H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, { AArch64_SHA512H, ARM64_INS_SHA512H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SHA512H2, ARM64_INS_SHA512H2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SHA512SU0, ARM64_INS_SHA512SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SHA512SU1, ARM64_INS_SHA512SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SHADDv16i8, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHADDv2i32, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHADDv4i16, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHADDv4i32, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHADDv8i16, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHADDv8i8, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLLv16i8, ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLLv2i32, ARM64_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLLv4i16, ARM64_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLLv4i32, ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLLv8i16, ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLLv8i8, ARM64_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLd, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv16i8_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv2i32_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv2i64_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv4i16_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv4i32_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv8i16_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHLv8i8_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHRNv2i32_shift, ARM64_INS_SHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHRNv4i16_shift, ARM64_INS_SHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHRNv8i8_shift, ARM64_INS_SHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHSUBv16i8, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHSUBv2i32, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHSUBv4i16, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHSUBv4i32, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHSUBv8i16, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SHSUBv8i8, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLId, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv16i8_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv2i32_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv2i64_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv4i16_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv4i32_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv8i16_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SLIv8i8_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SM3PARTW1, ARM64_INS_SM3PARTW1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM3PARTW2, ARM64_INS_SM3PARTW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM3SS1, ARM64_INS_SM3SS1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM3TT1A, ARM64_INS_SM3TT1A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM3TT1B, ARM64_INS_SM3TT1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM3TT2A, ARM64_INS_SM3TT2A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM3TT2B, ARM64_INS_SM3TT2B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM4E, ARM64_INS_SM4E, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SM4ENCKEY, ARM64_INS_SM4EKEY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMADDLrrr, ARM64_INS_SMADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAXPv16i8, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXPv2i32, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXPv4i16, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXPv4i32, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXPv8i16, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXPv8i8, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXV_VPZ_B, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAXV_VPZ_D, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAXV_VPZ_H, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAXV_VPZ_S, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAXVv16i8v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXVv4i16v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXVv4i32v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXVv8i16v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXVv8i8v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAX_ZI_B, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZI_D, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZI_H, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZI_S, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZPmZ_B, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZPmZ_D, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZPmZ_H, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAX_ZPmZ_S, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMAXv16i8, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXv2i32, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXv4i16, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXv4i32, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXv8i16, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMAXv8i8, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMC, ARM64_INS_SMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMINPv16i8, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINPv2i32, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINPv4i16, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINPv4i32, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINPv8i16, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINPv8i8, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINV_VPZ_B, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMINV_VPZ_D, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMINV_VPZ_H, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMINV_VPZ_S, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMINVv16i8v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINVv4i16v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINVv4i32v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINVv8i16v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINVv8i8v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMIN_ZI_B, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZI_D, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZI_H, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZI_S, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZPmZ_B, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZPmZ_D, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZPmZ_H, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMIN_ZPmZ_S, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMINv16i8, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINv2i32, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINv4i16, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINv4i32, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINv8i16, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMINv8i8, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMOVvi16to32, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMOVvi16to64, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMOVvi32to64, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMOVvi8to32, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMOVvi8to64, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMSUBLrrr, ARM64_INS_SMSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMULH_ZPmZ_B, ARM64_INS_SMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMULH_ZPmZ_D, ARM64_INS_SMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMULH_ZPmZ_H, ARM64_INS_SMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMULH_ZPmZ_S, ARM64_INS_SMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMULHrr, ARM64_INS_SMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SPLICE_ZPZ_B, ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SPLICE_ZPZ_D, ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SPLICE_ZPZ_H, ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SPLICE_ZPZ_S, ARM64_INS_SPLICE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQABSv16i8, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv1i16, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv1i32, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv1i64, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv1i8, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv2i32, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv2i64, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv4i16, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv4i32, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv8i16, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQABSv8i8, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADD_ZI_B, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZI_D, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZI_H, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZI_S, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZZZ_B, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZZZ_D, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZZZ_H, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADD_ZZZ_S, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQADDv16i8, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv1i16, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv1i32, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv1i64, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv1i8, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv2i32, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv2i64, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv4i16, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv4i32, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv8i16, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQADDv8i8, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDECB_XPiI, ARM64_INS_SQDECB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECB_XPiWdI, ARM64_INS_SQDECB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECD_XPiI, ARM64_INS_SQDECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECD_XPiWdI, ARM64_INS_SQDECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECD_ZPiI, ARM64_INS_SQDECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECH_XPiI, ARM64_INS_SQDECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECH_XPiWdI, ARM64_INS_SQDECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECH_ZPiI, ARM64_INS_SQDECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XPWd_B, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XPWd_D, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XPWd_H, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XPWd_S, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XP_B, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XP_D, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XP_H, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_XP_S, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_ZP_D, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_ZP_H, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECP_ZP_S, ARM64_INS_SQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECW_XPiI, ARM64_INS_SQDECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECW_XPiWdI, ARM64_INS_SQDECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDECW_ZPiI, ARM64_INS_SQDECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQDMLALi16, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALi32, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLi16, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLi32, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQINCB_XPiI, ARM64_INS_SQINCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCB_XPiWdI, ARM64_INS_SQINCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCD_XPiI, ARM64_INS_SQINCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCD_XPiWdI, ARM64_INS_SQINCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCD_ZPiI, ARM64_INS_SQINCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCH_XPiI, ARM64_INS_SQINCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCH_XPiWdI, ARM64_INS_SQINCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCH_ZPiI, ARM64_INS_SQINCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XPWd_B, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XPWd_D, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XPWd_H, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XPWd_S, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XP_B, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XP_D, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XP_H, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_XP_S, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_ZP_D, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_ZP_H, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCP_ZP_S, ARM64_INS_SQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCW_XPiI, ARM64_INS_SQINCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCW_XPiWdI, ARM64_INS_SQINCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQINCW_ZPiI, ARM64_INS_SQINCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQNEGv16i8, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv1i16, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv1i32, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv1i64, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv1i8, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv2i32, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv2i64, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv4i16, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv4i32, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv8i16, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQNEGv8i8, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHi16_indexed, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHi32_indexed, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv1i16, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv1i32, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv2i32, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv2i32_indexed, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv4i16, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv4i16_indexed, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv4i32, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv4i32_indexed, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv8i16, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLAHv8i16_indexed, ARM64_INS_SQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHi16_indexed, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHi32_indexed, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv1i16, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv1i32, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv2i32, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv2i32_indexed, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv4i16, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv4i16_indexed, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv4i32, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv4i32_indexed, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv8i16, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMLSHv8i16_indexed, ARM64_INS_SQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNb, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNh, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNs, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUb, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUd, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUh, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUs, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLb, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLd, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLh, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLs, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv16i8, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv1i16, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv1i32, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv1i64, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv1i8, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv2i32, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv2i64, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv4i16, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv4i32, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv8i16, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv8i8, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNb, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNh, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNs, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNb, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNh, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNs, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZI_B, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZI_D, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZI_H, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZI_S, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZZZ_B, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZZZ_D, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZZZ_H, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUB_ZZZ_S, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SQSUBv16i8, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv1i16, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv1i32, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv1i64, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv1i8, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv2i32, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv2i64, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv4i16, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv4i32, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv8i16, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQSUBv8i8, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv16i8, ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv1i16, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv1i32, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv1i8, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv2i32, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv4i16, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv4i32, ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv8i16, ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTNv8i8, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRHADDv16i8, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRHADDv2i32, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRHADDv4i16, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRHADDv4i32, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRHADDv8i16, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRHADDv8i8, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRId, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv16i8_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv2i32_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv2i64_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv4i16_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv4i32_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv8i16_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRIv8i8_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv16i8, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv1i64, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv2i32, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv2i64, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv4i16, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv4i32, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv8i16, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHLv8i8, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRd, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAd, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv16i8, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv1i64, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv2i32, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv2i64, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv4i16, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv4i32, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv8i16, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHLv8i8, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRd, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv16i8_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv2i32_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv2i64_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv4i16_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv4i32_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv8i16_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSHRv8i8_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAd, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv16i8_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv2i32_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv2i64_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv4i16_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv4i32_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv8i16_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSRAv8i8_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SST1B_D, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1B_D_IMM, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1B_D_SXTW, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1B_D_UXTW, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1B_S_IMM, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1B_S_SXTW, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1B_S_UXTW, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D_IMM, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D_SCALED, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D_SXTW, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D_SXTW_SCALED, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D_UXTW, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1D_UXTW_SCALED, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D_IMM, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D_SCALED, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D_SXTW, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D_SXTW_SCALED, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D_UXTW, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_D_UXTW_SCALED, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_S_IMM, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_S_SXTW, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_S_SXTW_SCALED, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_S_UXTW, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1H_S_UXTW_SCALED, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D_IMM, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D_SCALED, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D_SXTW, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D_SXTW_SCALED, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D_UXTW, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_D_UXTW_SCALED, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_IMM, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_SXTW, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_SXTW_SCALED, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_UXTW, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SST1W_UXTW_SCALED, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1B, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_D, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_D_IMM, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_H, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_H_IMM, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_IMM, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_S, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1B_S_IMM, ARM64_INS_ST1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1D, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1D_IMM, ARM64_INS_ST1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1Fourv16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Fourv8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1H, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1H_D, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1H_D_IMM, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1H_IMM, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1H_S, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1H_S_IMM, ARM64_INS_ST1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1Onev16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Onev8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Threev8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1Twov8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1W, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1W_D, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1W_D_IMM, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1W_IMM, ARM64_INS_ST1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST1i16, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i16_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i32, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i32_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i64, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i64_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i8, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST1i8_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2B, ARM64_INS_ST2B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2B_IMM, ARM64_INS_ST2B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2D, ARM64_INS_ST2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2D_IMM, ARM64_INS_ST2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2H, ARM64_INS_ST2H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2H_IMM, ARM64_INS_ST2H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2Twov16b, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov16b_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov2d, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov2d_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov2s, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov2s_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov4h, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov4h_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov4s, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov4s_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov8b, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov8b_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov8h, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2Twov8h_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2W, ARM64_INS_ST2W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2W_IMM, ARM64_INS_ST2W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST2i16, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i16_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i32, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i32_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i64, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i64_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i8, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST2i8_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3B, ARM64_INS_ST3B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3B_IMM, ARM64_INS_ST3B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3D, ARM64_INS_ST3D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3D_IMM, ARM64_INS_ST3D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3H, ARM64_INS_ST3H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3H_IMM, ARM64_INS_ST3H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3Threev16b, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev16b_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev2d, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev2d_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev2s, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev2s_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev4h, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev4h_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev4s, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev4s_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev8b, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev8b_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev8h, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3Threev8h_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3W, ARM64_INS_ST3W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3W_IMM, ARM64_INS_ST3W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST3i16, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i16_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i32, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i32_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i64, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i64_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i8, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST3i8_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4B, ARM64_INS_ST4B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4B_IMM, ARM64_INS_ST4B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4D, ARM64_INS_ST4D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4D_IMM, ARM64_INS_ST4D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4Fourv16b, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv16b_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv2d, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv2d_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv2s, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv2s_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv4h, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv4h_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv4s, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv4s_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv8b, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv8b_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv8h, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4Fourv8h_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4H, ARM64_INS_ST4H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4H_IMM, ARM64_INS_ST4H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4W, ARM64_INS_ST4W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4W_IMM, ARM64_INS_ST4W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ST4i16, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i16_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i32, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i32_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i64, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i64_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i8, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ST4i8_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_STLLRB, ARM64_INS_STLLRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLLRH, ARM64_INS_STLLRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLLRW, ARM64_INS_STLLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLLRX, ARM64_INS_STLLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLRB, ARM64_INS_STLRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLRH, ARM64_INS_STLRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLRW, ARM64_INS_STLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLRX, ARM64_INS_STLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLURBi, ARM64_INS_STLURB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLURHi, ARM64_INS_STLURH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLURWi, ARM64_INS_STLUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLURXi, ARM64_INS_STLUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLXPW, ARM64_INS_STLXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLXPX, ARM64_INS_STLXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLXRB, ARM64_INS_STLXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLXRH, ARM64_INS_STLXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLXRW, ARM64_INS_STLXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STLXRX, ARM64_INS_STLXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNPDi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNPQi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNPSi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNPWi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNPXi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1B_ZRI, ARM64_INS_STNT1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1B_ZRR, ARM64_INS_STNT1B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1D_ZRI, ARM64_INS_STNT1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1D_ZRR, ARM64_INS_STNT1D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1H_ZRI, ARM64_INS_STNT1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1H_ZRR, ARM64_INS_STNT1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1W_ZRI, ARM64_INS_STNT1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STNT1W_ZRR, ARM64_INS_STNT1W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPDi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPDpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPDpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPQi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPQpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPQpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPSi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPSpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPSpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPWi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPWpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPWpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPXi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPXpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STPXpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBBpost, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBBpre, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBBroW, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBBroX, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBBui, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRBui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRDpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRDpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRDroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRDroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRDui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHHpost, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHHpre, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHHroW, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHHroX, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHHui, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRHui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRQpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRQpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRQroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRQroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRQui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRSpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRSpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRSroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRSroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRSui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRWpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRWpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRWroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRWroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRWui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRXpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRXpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRXroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRXroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STRXui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STR_PXI, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STR_ZXI, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STTRBi, ARM64_INS_STTRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STTRHi, ARM64_INS_STTRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STTRWi, ARM64_INS_STTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STTRXi, ARM64_INS_STTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURBBi, ARM64_INS_STURB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURBi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURDi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURHHi, ARM64_INS_STURH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURHi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURQi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURSi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURWi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STURXi, ARM64_INS_STUR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STXPW, ARM64_INS_STXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STXPX, ARM64_INS_STXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STXRB, ARM64_INS_STXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STXRH, ARM64_INS_STXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STXRW, ARM64_INS_STXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_STXRX, ARM64_INS_STXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBR_ZI_B, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZI_D, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZI_H, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZI_S, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZPmZ_B, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZPmZ_D, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZPmZ_H, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBR_ZPmZ_S, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSWri, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSWrs, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSWrx, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSXri, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSXrs, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSXrx, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBSXrx64, ARM64_INS_SUBS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBWri, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBWrs, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBWrx, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBXri, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBXrs, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBXrx, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBXrx64, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZI_B, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZI_D, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZI_H, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZI_S, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZPmZ_B, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZPmZ_D, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZPmZ_H, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZPmZ_S, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZZZ_B, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZZZ_D, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZZZ_H, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUB_ZZZ_S, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUBv16i8, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv1i64, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv2i32, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv2i64, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv4i16, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv4i32, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv8i16, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUBv8i8, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUNPKHI_ZZ_D, ARM64_INS_SUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUNPKHI_ZZ_H, ARM64_INS_SUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUNPKHI_ZZ_S, ARM64_INS_SUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUNPKLO_ZZ_D, ARM64_INS_SUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUNPKLO_ZZ_H, ARM64_INS_SUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUNPKLO_ZZ_S, ARM64_INS_SUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SUQADDv16i8, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv1i16, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv1i32, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv1i64, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv1i8, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv2i32, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv2i64, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv4i16, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv4i32, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv8i16, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SUQADDv8i8, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_SVC, ARM64_INS_SVC, #ifndef CAPSTONE_DIET { 0, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_INT, 0 }, 0, 0 #endif }, { AArch64_SWPAB, ARM64_INS_SWPAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPAH, ARM64_INS_SWPAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPALB, ARM64_INS_SWPALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPALH, ARM64_INS_SWPALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPALW, ARM64_INS_SWPAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPALX, ARM64_INS_SWPAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPAW, ARM64_INS_SWPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPAX, ARM64_INS_SWPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPB, ARM64_INS_SWPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPH, ARM64_INS_SWPH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPLB, ARM64_INS_SWPLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPLH, ARM64_INS_SWPLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPLW, ARM64_INS_SWPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPLX, ARM64_INS_SWPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPW, ARM64_INS_SWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SWPX, ARM64_INS_SWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SXTB_ZPmZ_D, ARM64_INS_SXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SXTB_ZPmZ_H, ARM64_INS_SXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SXTB_ZPmZ_S, ARM64_INS_SXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SXTH_ZPmZ_D, ARM64_INS_SXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SXTH_ZPmZ_S, ARM64_INS_SXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SXTW_ZPmZ_D, ARM64_INS_SXTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SYSLxt, ARM64_INS_SYSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_SYSxt, ARM64_INS_SYS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TBL_ZZZ_B, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TBL_ZZZ_D, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TBL_ZZZ_H, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TBL_ZZZ_S, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TBLv16i8Four, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv16i8One, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv16i8Three, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv16i8Two, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv8i8Four, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv8i8One, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv8i8Three, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBLv8i8Two, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBNZW, ARM64_INS_TBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_TBNZX, ARM64_INS_TBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_TBXv16i8Four, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv16i8One, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv16i8Three, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv16i8Two, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv8i8Four, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv8i8One, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv8i8Three, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBXv8i8Two, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TBZW, ARM64_INS_TBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_TBZX, ARM64_INS_TBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { AArch64_TRN1_PPP_B, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_PPP_D, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_PPP_H, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_PPP_S, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_ZZZ_B, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_ZZZ_D, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_ZZZ_H, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1_ZZZ_S, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN1v16i8, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN1v2i32, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN1v2i64, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN1v4i16, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN1v4i32, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN1v8i16, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN1v8i8, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2_PPP_B, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_PPP_D, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_PPP_H, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_PPP_S, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_ZZZ_B, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_ZZZ_D, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_ZZZ_H, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2_ZZZ_S, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_TRN2v16i8, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2v2i32, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2v2i64, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2v4i16, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2v4i32, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2v8i16, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TRN2v8i8, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_TSB, ARM64_INS_TSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABAv16i8, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABAv2i32, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABAv4i16, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABAv4i32, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABAv8i16, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABAv8i8, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABD_ZPmZ_B, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UABD_ZPmZ_D, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UABD_ZPmZ_H, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UABD_ZPmZ_S, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UABDv16i8, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDv2i32, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDv4i16, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDv4i32, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDv8i16, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UABDv8i8, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLVv16i8v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLVv4i16v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLVv4i32v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLVv8i16v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLVv8i8v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDV_VPZ_B, ARM64_INS_UADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UADDV_VPZ_D, ARM64_INS_UADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UADDV_VPZ_H, ARM64_INS_UADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UADDV_VPZ_S, ARM64_INS_UADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UBFMWri, ARM64_INS_UBFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UBFMXri, ARM64_INS_UBFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFSWDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFSWHri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFSWSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFSXDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFSXHri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFSXSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFUWDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFUWHri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFUWSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFUXDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTFUXHri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFUXSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_DtoD, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_DtoH, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_DtoS, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_HtoH, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_StoD, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_StoH, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTF_ZPmZ_StoS, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFd, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFh, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFs, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv1i16, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFv1i32, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv1i64, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv2f32, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv2f64, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv4f16, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFv4f32, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv4i16_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UCVTFv8f16, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UCVTFv8i16_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDIVR_ZPmZ_D, ARM64_INS_UDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDIVR_ZPmZ_S, ARM64_INS_UDIVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDIVWr, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDIVXr, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDIV_ZPmZ_D, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDIV_ZPmZ_S, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOT_ZZZI_D, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOT_ZZZI_S, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOT_ZZZ_D, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOT_ZZZ_S, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOTlanev16i8, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOTlanev8i8, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOTv16i8, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UDOTv8i8, ARM64_INS_UDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UHADDv16i8, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHADDv2i32, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHADDv4i16, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHADDv4i32, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHADDv8i16, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHADDv8i8, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHSUBv16i8, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHSUBv2i32, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHSUBv4i16, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHSUBv4i32, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHSUBv8i16, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UHSUBv8i8, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMADDLrrr, ARM64_INS_UMADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAXPv16i8, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXPv2i32, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXPv4i16, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXPv4i32, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXPv8i16, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXPv8i8, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXV_VPZ_B, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAXV_VPZ_D, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAXV_VPZ_H, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAXV_VPZ_S, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAXVv16i8v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXVv4i16v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXVv4i32v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXVv8i16v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXVv8i8v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAX_ZI_B, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZI_D, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZI_H, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZI_S, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZPmZ_B, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZPmZ_D, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZPmZ_H, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAX_ZPmZ_S, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMAXv16i8, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXv2i32, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXv4i16, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXv4i32, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXv8i16, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMAXv8i8, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINPv16i8, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINPv2i32, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINPv4i16, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINPv4i32, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINPv8i16, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINPv8i8, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINV_VPZ_B, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMINV_VPZ_D, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMINV_VPZ_H, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMINV_VPZ_S, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMINVv16i8v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINVv4i16v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINVv4i32v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINVv8i16v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINVv8i8v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMIN_ZI_B, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZI_D, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZI_H, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZI_S, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZPmZ_B, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZPmZ_D, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZPmZ_H, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMIN_ZPmZ_S, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMINv16i8, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINv2i32, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINv4i16, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINv4i32, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINv8i16, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMINv8i8, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMOVvi16, ARM64_INS_UMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMOVvi32, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMOVvi64, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMOVvi8, ARM64_INS_UMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMSUBLrrr, ARM64_INS_UMSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMULH_ZPmZ_B, ARM64_INS_UMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMULH_ZPmZ_D, ARM64_INS_UMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMULH_ZPmZ_H, ARM64_INS_UMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMULH_ZPmZ_S, ARM64_INS_UMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMULHrr, ARM64_INS_UMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADD_ZI_B, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZI_D, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZI_H, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZI_S, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZZZ_B, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZZZ_D, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZZZ_H, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADD_ZZZ_S, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQADDv16i8, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv1i16, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv1i32, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv1i64, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv1i8, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv2i32, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv2i64, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv4i16, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv4i32, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv8i16, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQADDv8i8, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQDECB_WPiI, ARM64_INS_UQDECB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECB_XPiI, ARM64_INS_UQDECB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECD_WPiI, ARM64_INS_UQDECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECD_XPiI, ARM64_INS_UQDECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECD_ZPiI, ARM64_INS_UQDECD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECH_WPiI, ARM64_INS_UQDECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECH_XPiI, ARM64_INS_UQDECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECH_ZPiI, ARM64_INS_UQDECH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_WP_B, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_WP_D, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_WP_H, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_WP_S, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_XP_B, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_XP_D, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_XP_H, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_XP_S, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_ZP_D, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_ZP_H, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECP_ZP_S, ARM64_INS_UQDECP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECW_WPiI, ARM64_INS_UQDECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECW_XPiI, ARM64_INS_UQDECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQDECW_ZPiI, ARM64_INS_UQDECW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCB_WPiI, ARM64_INS_UQINCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCB_XPiI, ARM64_INS_UQINCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCD_WPiI, ARM64_INS_UQINCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCD_XPiI, ARM64_INS_UQINCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCD_ZPiI, ARM64_INS_UQINCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCH_WPiI, ARM64_INS_UQINCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCH_XPiI, ARM64_INS_UQINCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCH_ZPiI, ARM64_INS_UQINCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_WP_B, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_WP_D, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_WP_H, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_WP_S, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_XP_B, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_XP_D, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_XP_H, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_XP_S, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_ZP_D, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_ZP_H, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCP_ZP_S, ARM64_INS_UQINCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCW_WPiI, ARM64_INS_UQINCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCW_XPiI, ARM64_INS_UQINCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQINCW_ZPiI, ARM64_INS_UQINCW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNb, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNh, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNs, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLb, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLd, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLh, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLs, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv16i8, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv1i16, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv1i32, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv1i64, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv1i8, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv2i32, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv2i64, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv4i16, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv4i32, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv8i16, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv8i8, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNb, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNh, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNs, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZI_B, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZI_D, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZI_H, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZI_S, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZZZ_B, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZZZ_D, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZZZ_H, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUB_ZZZ_S, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UQSUBv16i8, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv1i16, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv1i32, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv1i64, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv1i8, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv2i32, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv2i64, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv4i16, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv4i32, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv8i16, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQSUBv8i8, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv16i8, ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv1i16, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv1i32, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv1i8, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv2i32, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv4i16, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv4i32, ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv8i16, ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UQXTNv8i8, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URECPEv2i32, ARM64_INS_URECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URECPEv4i32, ARM64_INS_URECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URHADDv16i8, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URHADDv2i32, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URHADDv4i16, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URHADDv4i32, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URHADDv8i16, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URHADDv8i8, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv16i8, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv1i64, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv2i32, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv2i64, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv4i16, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv4i32, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv8i16, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHLv8i8, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRd, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv16i8_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv2i32_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv2i64_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv4i16_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv4i32_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv8i16_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSHRv8i8_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAd, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv16i8_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv2i32_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv2i64_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv4i16_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv4i32_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv8i16_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_URSRAv8i8_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLLv2i32_shift, ARM64_INS_USHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLLv4i16_shift, ARM64_INS_USHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLLv8i8_shift, ARM64_INS_USHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv16i8, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv1i64, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv2i32, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv2i64, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv4i16, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv4i32, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv8i16, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHLv8i8, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRd, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv16i8_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv2i32_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv2i64_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv4i16_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv4i32_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv8i16_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USHRv8i8_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv16i8, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv1i16, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv1i32, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv1i64, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv1i8, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv2i32, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv2i64, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv4i16, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv4i32, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv8i16, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USQADDv8i8, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAd, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv16i8_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv2i32_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv2i64_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv4i16_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv4i32_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv8i16_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USRAv8i8_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UUNPKHI_ZZ_D, ARM64_INS_UUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UUNPKHI_ZZ_H, ARM64_INS_UUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UUNPKHI_ZZ_S, ARM64_INS_UUNPKHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UUNPKLO_ZZ_D, ARM64_INS_UUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UUNPKLO_ZZ_H, ARM64_INS_UUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UUNPKLO_ZZ_S, ARM64_INS_UUNPKLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UXTB_ZPmZ_D, ARM64_INS_UXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UXTB_ZPmZ_H, ARM64_INS_UXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UXTB_ZPmZ_S, ARM64_INS_UXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UXTH_ZPmZ_D, ARM64_INS_UXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UXTH_ZPmZ_S, ARM64_INS_UXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UXTW_ZPmZ_D, ARM64_INS_UXTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_PPP_B, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_PPP_D, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_PPP_H, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_PPP_S, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_ZZZ_B, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_ZZZ_D, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_ZZZ_H, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1_ZZZ_S, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP1v16i8, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP1v2i32, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP1v2i64, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP1v4i16, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP1v4i32, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP1v8i16, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP1v8i8, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2_PPP_B, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_PPP_D, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_PPP_H, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_PPP_S, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_ZZZ_B, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_ZZZ_D, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_ZZZ_H, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2_ZZZ_S, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_UZP2v16i8, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2v2i32, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2v2i64, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2v4i16, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2v4i32, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2v8i16, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_UZP2v8i8, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_WHILELE_PWW_B, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PWW_D, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PWW_H, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PWW_S, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PXX_B, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PXX_D, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PXX_H, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELE_PXX_S, ARM64_INS_WHILELE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PWW_B, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PWW_D, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PWW_H, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PWW_S, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PXX_B, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PXX_D, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PXX_H, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELO_PXX_S, ARM64_INS_WHILELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PWW_B, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PWW_D, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PWW_H, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PWW_S, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PXX_B, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PXX_D, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PXX_H, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELS_PXX_S, ARM64_INS_WHILELS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PWW_B, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PWW_D, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PWW_H, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PWW_S, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PXX_B, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PXX_D, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PXX_H, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WHILELT_PXX_S, ARM64_INS_WHILELT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_WRFFR, ARM64_INS_WRFFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_XAR, ARM64_INS_XAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_XPACD, ARM64_INS_XPACD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_XPACI, ARM64_INS_XPACI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_XPACLRI, ARM64_INS_XPACLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PAC, 0 }, 0, 0 #endif }, { AArch64_XTNv16i8, ARM64_INS_XTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_XTNv2i32, ARM64_INS_XTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_XTNv4i16, ARM64_INS_XTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_XTNv4i32, ARM64_INS_XTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_XTNv8i16, ARM64_INS_XTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_XTNv8i8, ARM64_INS_XTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1_PPP_B, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_PPP_D, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_PPP_H, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_PPP_S, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_ZZZ_B, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_ZZZ_D, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_ZZZ_H, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1_ZZZ_S, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP1v16i8, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1v2i32, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1v2i64, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1v4i16, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1v4i32, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1v8i16, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP1v8i8, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2_PPP_B, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_PPP_D, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_PPP_H, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_PPP_S, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_ZZZ_B, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_ZZZ_D, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_ZZZ_H, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2_ZZZ_S, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { AArch64_ZIP2v16i8, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2v2i32, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2v2i64, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2v4i16, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2v4i32, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2v8i16, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_ZIP2v8i8, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, { AArch64_anonymous_1349, ARM64_INS_PFIRST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/AArch64/AArch64MappingInsnName.inc000064400000000000000000000704030072674642500230440ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ "abs", // ARM64_INS_ABS, "adc", // ARM64_INS_ADC, "adcs", // ARM64_INS_ADCS, "add", // ARM64_INS_ADD, "addhn", // ARM64_INS_ADDHN, "addhn2", // ARM64_INS_ADDHN2, "addp", // ARM64_INS_ADDP, "addpl", // ARM64_INS_ADDPL, "adds", // ARM64_INS_ADDS, "addv", // ARM64_INS_ADDV, "addvl", // ARM64_INS_ADDVL, "adr", // ARM64_INS_ADR, "adrp", // ARM64_INS_ADRP, "aesd", // ARM64_INS_AESD, "aese", // ARM64_INS_AESE, "aesimc", // ARM64_INS_AESIMC, "aesmc", // ARM64_INS_AESMC, "and", // ARM64_INS_AND, "ands", // ARM64_INS_ANDS, "andv", // ARM64_INS_ANDV, "asr", // ARM64_INS_ASR, "asrd", // ARM64_INS_ASRD, "asrr", // ARM64_INS_ASRR, "asrv", // ARM64_INS_ASRV, "autda", // ARM64_INS_AUTDA, "autdb", // ARM64_INS_AUTDB, "autdza", // ARM64_INS_AUTDZA, "autdzb", // ARM64_INS_AUTDZB, "autia", // ARM64_INS_AUTIA, "autia1716", // ARM64_INS_AUTIA1716, "autiasp", // ARM64_INS_AUTIASP, "autiaz", // ARM64_INS_AUTIAZ, "autib", // ARM64_INS_AUTIB, "autib1716", // ARM64_INS_AUTIB1716, "autibsp", // ARM64_INS_AUTIBSP, "autibz", // ARM64_INS_AUTIBZ, "autiza", // ARM64_INS_AUTIZA, "autizb", // ARM64_INS_AUTIZB, "b", // ARM64_INS_B, "bcax", // ARM64_INS_BCAX, "bfm", // ARM64_INS_BFM, "bic", // ARM64_INS_BIC, "bics", // ARM64_INS_BICS, "bif", // ARM64_INS_BIF, "bit", // ARM64_INS_BIT, "bl", // ARM64_INS_BL, "blr", // ARM64_INS_BLR, "blraa", // ARM64_INS_BLRAA, "blraaz", // ARM64_INS_BLRAAZ, "blrab", // ARM64_INS_BLRAB, "blrabz", // ARM64_INS_BLRABZ, "br", // ARM64_INS_BR, "braa", // ARM64_INS_BRAA, "braaz", // ARM64_INS_BRAAZ, "brab", // ARM64_INS_BRAB, "brabz", // ARM64_INS_BRABZ, "brk", // ARM64_INS_BRK, "brka", // ARM64_INS_BRKA, "brkas", // ARM64_INS_BRKAS, "brkb", // ARM64_INS_BRKB, "brkbs", // ARM64_INS_BRKBS, "brkn", // ARM64_INS_BRKN, "brkns", // ARM64_INS_BRKNS, "brkpa", // ARM64_INS_BRKPA, "brkpas", // ARM64_INS_BRKPAS, "brkpb", // ARM64_INS_BRKPB, "brkpbs", // ARM64_INS_BRKPBS, "bsl", // ARM64_INS_BSL, "cas", // ARM64_INS_CAS, "casa", // ARM64_INS_CASA, "casab", // ARM64_INS_CASAB, "casah", // ARM64_INS_CASAH, "casal", // ARM64_INS_CASAL, "casalb", // ARM64_INS_CASALB, "casalh", // ARM64_INS_CASALH, "casb", // ARM64_INS_CASB, "cash", // ARM64_INS_CASH, "casl", // ARM64_INS_CASL, "caslb", // ARM64_INS_CASLB, "caslh", // ARM64_INS_CASLH, "casp", // ARM64_INS_CASP, "caspa", // ARM64_INS_CASPA, "caspal", // ARM64_INS_CASPAL, "caspl", // ARM64_INS_CASPL, "cbnz", // ARM64_INS_CBNZ, "cbz", // ARM64_INS_CBZ, "ccmn", // ARM64_INS_CCMN, "ccmp", // ARM64_INS_CCMP, "cfinv", // ARM64_INS_CFINV, "cinc", // ARM64_INS_CINC, "cinv", // ARM64_INS_CINV, "clasta", // ARM64_INS_CLASTA, "clastb", // ARM64_INS_CLASTB, "clrex", // ARM64_INS_CLREX, "cls", // ARM64_INS_CLS, "clz", // ARM64_INS_CLZ, "cmeq", // ARM64_INS_CMEQ, "cmge", // ARM64_INS_CMGE, "cmgt", // ARM64_INS_CMGT, "cmhi", // ARM64_INS_CMHI, "cmhs", // ARM64_INS_CMHS, "cmle", // ARM64_INS_CMLE, "cmlo", // ARM64_INS_CMLO, "cmls", // ARM64_INS_CMLS, "cmlt", // ARM64_INS_CMLT, "cmn", // ARM64_INS_CMN, "cmp", // ARM64_INS_CMP, "cmpeq", // ARM64_INS_CMPEQ, "cmpge", // ARM64_INS_CMPGE, "cmpgt", // ARM64_INS_CMPGT, "cmphi", // ARM64_INS_CMPHI, "cmphs", // ARM64_INS_CMPHS, "cmple", // ARM64_INS_CMPLE, "cmplo", // ARM64_INS_CMPLO, "cmpls", // ARM64_INS_CMPLS, "cmplt", // ARM64_INS_CMPLT, "cmpne", // ARM64_INS_CMPNE, "cmtst", // ARM64_INS_CMTST, "cneg", // ARM64_INS_CNEG, "cnot", // ARM64_INS_CNOT, "cnt", // ARM64_INS_CNT, "cntb", // ARM64_INS_CNTB, "cntd", // ARM64_INS_CNTD, "cnth", // ARM64_INS_CNTH, "cntp", // ARM64_INS_CNTP, "cntw", // ARM64_INS_CNTW, "compact", // ARM64_INS_COMPACT, "cpy", // ARM64_INS_CPY, "crc32b", // ARM64_INS_CRC32B, "crc32cb", // ARM64_INS_CRC32CB, "crc32ch", // ARM64_INS_CRC32CH, "crc32cw", // ARM64_INS_CRC32CW, "crc32cx", // ARM64_INS_CRC32CX, "crc32h", // ARM64_INS_CRC32H, "crc32w", // ARM64_INS_CRC32W, "crc32x", // ARM64_INS_CRC32X, "csdb", // ARM64_INS_CSDB, "csel", // ARM64_INS_CSEL, "cset", // ARM64_INS_CSET, "csetm", // ARM64_INS_CSETM, "csinc", // ARM64_INS_CSINC, "csinv", // ARM64_INS_CSINV, "csneg", // ARM64_INS_CSNEG, "ctermeq", // ARM64_INS_CTERMEQ, "ctermne", // ARM64_INS_CTERMNE, "dcps1", // ARM64_INS_DCPS1, "dcps2", // ARM64_INS_DCPS2, "dcps3", // ARM64_INS_DCPS3, "decb", // ARM64_INS_DECB, "decd", // ARM64_INS_DECD, "dech", // ARM64_INS_DECH, "decp", // ARM64_INS_DECP, "decw", // ARM64_INS_DECW, "dmb", // ARM64_INS_DMB, "drps", // ARM64_INS_DRPS, "dsb", // ARM64_INS_DSB, "dup", // ARM64_INS_DUP, "dupm", // ARM64_INS_DUPM, "eon", // ARM64_INS_EON, "eor", // ARM64_INS_EOR, "eor3", // ARM64_INS_EOR3, "eors", // ARM64_INS_EORS, "eorv", // ARM64_INS_EORV, "eret", // ARM64_INS_ERET, "eretaa", // ARM64_INS_ERETAA, "eretab", // ARM64_INS_ERETAB, "esb", // ARM64_INS_ESB, "ext", // ARM64_INS_EXT, "extr", // ARM64_INS_EXTR, "fabd", // ARM64_INS_FABD, "fabs", // ARM64_INS_FABS, "facge", // ARM64_INS_FACGE, "facgt", // ARM64_INS_FACGT, "facle", // ARM64_INS_FACLE, "faclt", // ARM64_INS_FACLT, "fadd", // ARM64_INS_FADD, "fadda", // ARM64_INS_FADDA, "faddp", // ARM64_INS_FADDP, "faddv", // ARM64_INS_FADDV, "fcadd", // ARM64_INS_FCADD, "fccmp", // ARM64_INS_FCCMP, "fccmpe", // ARM64_INS_FCCMPE, "fcmeq", // ARM64_INS_FCMEQ, "fcmge", // ARM64_INS_FCMGE, "fcmgt", // ARM64_INS_FCMGT, "fcmla", // ARM64_INS_FCMLA, "fcmle", // ARM64_INS_FCMLE, "fcmlt", // ARM64_INS_FCMLT, "fcmne", // ARM64_INS_FCMNE, "fcmp", // ARM64_INS_FCMP, "fcmpe", // ARM64_INS_FCMPE, "fcmuo", // ARM64_INS_FCMUO, "fcpy", // ARM64_INS_FCPY, "fcsel", // ARM64_INS_FCSEL, "fcvt", // ARM64_INS_FCVT, "fcvtas", // ARM64_INS_FCVTAS, "fcvtau", // ARM64_INS_FCVTAU, "fcvtl", // ARM64_INS_FCVTL, "fcvtl2", // ARM64_INS_FCVTL2, "fcvtms", // ARM64_INS_FCVTMS, "fcvtmu", // ARM64_INS_FCVTMU, "fcvtn", // ARM64_INS_FCVTN, "fcvtn2", // ARM64_INS_FCVTN2, "fcvtns", // ARM64_INS_FCVTNS, "fcvtnu", // ARM64_INS_FCVTNU, "fcvtps", // ARM64_INS_FCVTPS, "fcvtpu", // ARM64_INS_FCVTPU, "fcvtxn", // ARM64_INS_FCVTXN, "fcvtxn2", // ARM64_INS_FCVTXN2, "fcvtzs", // ARM64_INS_FCVTZS, "fcvtzu", // ARM64_INS_FCVTZU, "fdiv", // ARM64_INS_FDIV, "fdivr", // ARM64_INS_FDIVR, "fdup", // ARM64_INS_FDUP, "fexpa", // ARM64_INS_FEXPA, "fjcvtzs", // ARM64_INS_FJCVTZS, "fmad", // ARM64_INS_FMAD, "fmadd", // ARM64_INS_FMADD, "fmax", // ARM64_INS_FMAX, "fmaxnm", // ARM64_INS_FMAXNM, "fmaxnmp", // ARM64_INS_FMAXNMP, "fmaxnmv", // ARM64_INS_FMAXNMV, "fmaxp", // ARM64_INS_FMAXP, "fmaxv", // ARM64_INS_FMAXV, "fmin", // ARM64_INS_FMIN, "fminnm", // ARM64_INS_FMINNM, "fminnmp", // ARM64_INS_FMINNMP, "fminnmv", // ARM64_INS_FMINNMV, "fminp", // ARM64_INS_FMINP, "fminv", // ARM64_INS_FMINV, "fmla", // ARM64_INS_FMLA, "fmls", // ARM64_INS_FMLS, "fmov", // ARM64_INS_FMOV, "fmsb", // ARM64_INS_FMSB, "fmsub", // ARM64_INS_FMSUB, "fmul", // ARM64_INS_FMUL, "fmulx", // ARM64_INS_FMULX, "fneg", // ARM64_INS_FNEG, "fnmad", // ARM64_INS_FNMAD, "fnmadd", // ARM64_INS_FNMADD, "fnmla", // ARM64_INS_FNMLA, "fnmls", // ARM64_INS_FNMLS, "fnmsb", // ARM64_INS_FNMSB, "fnmsub", // ARM64_INS_FNMSUB, "fnmul", // ARM64_INS_FNMUL, "frecpe", // ARM64_INS_FRECPE, "frecps", // ARM64_INS_FRECPS, "frecpx", // ARM64_INS_FRECPX, "frinta", // ARM64_INS_FRINTA, "frinti", // ARM64_INS_FRINTI, "frintm", // ARM64_INS_FRINTM, "frintn", // ARM64_INS_FRINTN, "frintp", // ARM64_INS_FRINTP, "frintx", // ARM64_INS_FRINTX, "frintz", // ARM64_INS_FRINTZ, "frsqrte", // ARM64_INS_FRSQRTE, "frsqrts", // ARM64_INS_FRSQRTS, "fscale", // ARM64_INS_FSCALE, "fsqrt", // ARM64_INS_FSQRT, "fsub", // ARM64_INS_FSUB, "fsubr", // ARM64_INS_FSUBR, "ftmad", // ARM64_INS_FTMAD, "ftsmul", // ARM64_INS_FTSMUL, "ftssel", // ARM64_INS_FTSSEL, "hint", // ARM64_INS_HINT, "hlt", // ARM64_INS_HLT, "hvc", // ARM64_INS_HVC, "incb", // ARM64_INS_INCB, "incd", // ARM64_INS_INCD, "inch", // ARM64_INS_INCH, "incp", // ARM64_INS_INCP, "incw", // ARM64_INS_INCW, "index", // ARM64_INS_INDEX, "ins", // ARM64_INS_INS, "insr", // ARM64_INS_INSR, "isb", // ARM64_INS_ISB, "lasta", // ARM64_INS_LASTA, "lastb", // ARM64_INS_LASTB, "ld1", // ARM64_INS_LD1, "ld1b", // ARM64_INS_LD1B, "ld1d", // ARM64_INS_LD1D, "ld1h", // ARM64_INS_LD1H, "ld1r", // ARM64_INS_LD1R, "ld1rb", // ARM64_INS_LD1RB, "ld1rd", // ARM64_INS_LD1RD, "ld1rh", // ARM64_INS_LD1RH, "ld1rqb", // ARM64_INS_LD1RQB, "ld1rqd", // ARM64_INS_LD1RQD, "ld1rqh", // ARM64_INS_LD1RQH, "ld1rqw", // ARM64_INS_LD1RQW, "ld1rsb", // ARM64_INS_LD1RSB, "ld1rsh", // ARM64_INS_LD1RSH, "ld1rsw", // ARM64_INS_LD1RSW, "ld1rw", // ARM64_INS_LD1RW, "ld1sb", // ARM64_INS_LD1SB, "ld1sh", // ARM64_INS_LD1SH, "ld1sw", // ARM64_INS_LD1SW, "ld1w", // ARM64_INS_LD1W, "ld2", // ARM64_INS_LD2, "ld2b", // ARM64_INS_LD2B, "ld2d", // ARM64_INS_LD2D, "ld2h", // ARM64_INS_LD2H, "ld2r", // ARM64_INS_LD2R, "ld2w", // ARM64_INS_LD2W, "ld3", // ARM64_INS_LD3, "ld3b", // ARM64_INS_LD3B, "ld3d", // ARM64_INS_LD3D, "ld3h", // ARM64_INS_LD3H, "ld3r", // ARM64_INS_LD3R, "ld3w", // ARM64_INS_LD3W, "ld4", // ARM64_INS_LD4, "ld4b", // ARM64_INS_LD4B, "ld4d", // ARM64_INS_LD4D, "ld4h", // ARM64_INS_LD4H, "ld4r", // ARM64_INS_LD4R, "ld4w", // ARM64_INS_LD4W, "ldadd", // ARM64_INS_LDADD, "ldadda", // ARM64_INS_LDADDA, "ldaddab", // ARM64_INS_LDADDAB, "ldaddah", // ARM64_INS_LDADDAH, "ldaddal", // ARM64_INS_LDADDAL, "ldaddalb", // ARM64_INS_LDADDALB, "ldaddalh", // ARM64_INS_LDADDALH, "ldaddb", // ARM64_INS_LDADDB, "ldaddh", // ARM64_INS_LDADDH, "ldaddl", // ARM64_INS_LDADDL, "ldaddlb", // ARM64_INS_LDADDLB, "ldaddlh", // ARM64_INS_LDADDLH, "ldapr", // ARM64_INS_LDAPR, "ldaprb", // ARM64_INS_LDAPRB, "ldaprh", // ARM64_INS_LDAPRH, "ldapur", // ARM64_INS_LDAPUR, "ldapurb", // ARM64_INS_LDAPURB, "ldapurh", // ARM64_INS_LDAPURH, "ldapursb", // ARM64_INS_LDAPURSB, "ldapursh", // ARM64_INS_LDAPURSH, "ldapursw", // ARM64_INS_LDAPURSW, "ldar", // ARM64_INS_LDAR, "ldarb", // ARM64_INS_LDARB, "ldarh", // ARM64_INS_LDARH, "ldaxp", // ARM64_INS_LDAXP, "ldaxr", // ARM64_INS_LDAXR, "ldaxrb", // ARM64_INS_LDAXRB, "ldaxrh", // ARM64_INS_LDAXRH, "ldclr", // ARM64_INS_LDCLR, "ldclra", // ARM64_INS_LDCLRA, "ldclrab", // ARM64_INS_LDCLRAB, "ldclrah", // ARM64_INS_LDCLRAH, "ldclral", // ARM64_INS_LDCLRAL, "ldclralb", // ARM64_INS_LDCLRALB, "ldclralh", // ARM64_INS_LDCLRALH, "ldclrb", // ARM64_INS_LDCLRB, "ldclrh", // ARM64_INS_LDCLRH, "ldclrl", // ARM64_INS_LDCLRL, "ldclrlb", // ARM64_INS_LDCLRLB, "ldclrlh", // ARM64_INS_LDCLRLH, "ldeor", // ARM64_INS_LDEOR, "ldeora", // ARM64_INS_LDEORA, "ldeorab", // ARM64_INS_LDEORAB, "ldeorah", // ARM64_INS_LDEORAH, "ldeoral", // ARM64_INS_LDEORAL, "ldeoralb", // ARM64_INS_LDEORALB, "ldeoralh", // ARM64_INS_LDEORALH, "ldeorb", // ARM64_INS_LDEORB, "ldeorh", // ARM64_INS_LDEORH, "ldeorl", // ARM64_INS_LDEORL, "ldeorlb", // ARM64_INS_LDEORLB, "ldeorlh", // ARM64_INS_LDEORLH, "ldff1b", // ARM64_INS_LDFF1B, "ldff1d", // ARM64_INS_LDFF1D, "ldff1h", // ARM64_INS_LDFF1H, "ldff1sb", // ARM64_INS_LDFF1SB, "ldff1sh", // ARM64_INS_LDFF1SH, "ldff1sw", // ARM64_INS_LDFF1SW, "ldff1w", // ARM64_INS_LDFF1W, "ldlar", // ARM64_INS_LDLAR, "ldlarb", // ARM64_INS_LDLARB, "ldlarh", // ARM64_INS_LDLARH, "ldnf1b", // ARM64_INS_LDNF1B, "ldnf1d", // ARM64_INS_LDNF1D, "ldnf1h", // ARM64_INS_LDNF1H, "ldnf1sb", // ARM64_INS_LDNF1SB, "ldnf1sh", // ARM64_INS_LDNF1SH, "ldnf1sw", // ARM64_INS_LDNF1SW, "ldnf1w", // ARM64_INS_LDNF1W, "ldnp", // ARM64_INS_LDNP, "ldnt1b", // ARM64_INS_LDNT1B, "ldnt1d", // ARM64_INS_LDNT1D, "ldnt1h", // ARM64_INS_LDNT1H, "ldnt1w", // ARM64_INS_LDNT1W, "ldp", // ARM64_INS_LDP, "ldpsw", // ARM64_INS_LDPSW, "ldr", // ARM64_INS_LDR, "ldraa", // ARM64_INS_LDRAA, "ldrab", // ARM64_INS_LDRAB, "ldrb", // ARM64_INS_LDRB, "ldrh", // ARM64_INS_LDRH, "ldrsb", // ARM64_INS_LDRSB, "ldrsh", // ARM64_INS_LDRSH, "ldrsw", // ARM64_INS_LDRSW, "ldset", // ARM64_INS_LDSET, "ldseta", // ARM64_INS_LDSETA, "ldsetab", // ARM64_INS_LDSETAB, "ldsetah", // ARM64_INS_LDSETAH, "ldsetal", // ARM64_INS_LDSETAL, "ldsetalb", // ARM64_INS_LDSETALB, "ldsetalh", // ARM64_INS_LDSETALH, "ldsetb", // ARM64_INS_LDSETB, "ldseth", // ARM64_INS_LDSETH, "ldsetl", // ARM64_INS_LDSETL, "ldsetlb", // ARM64_INS_LDSETLB, "ldsetlh", // ARM64_INS_LDSETLH, "ldsmax", // ARM64_INS_LDSMAX, "ldsmaxa", // ARM64_INS_LDSMAXA, "ldsmaxab", // ARM64_INS_LDSMAXAB, "ldsmaxah", // ARM64_INS_LDSMAXAH, "ldsmaxal", // ARM64_INS_LDSMAXAL, "ldsmaxalb", // ARM64_INS_LDSMAXALB, "ldsmaxalh", // ARM64_INS_LDSMAXALH, "ldsmaxb", // ARM64_INS_LDSMAXB, "ldsmaxh", // ARM64_INS_LDSMAXH, "ldsmaxl", // ARM64_INS_LDSMAXL, "ldsmaxlb", // ARM64_INS_LDSMAXLB, "ldsmaxlh", // ARM64_INS_LDSMAXLH, "ldsmin", // ARM64_INS_LDSMIN, "ldsmina", // ARM64_INS_LDSMINA, "ldsminab", // ARM64_INS_LDSMINAB, "ldsminah", // ARM64_INS_LDSMINAH, "ldsminal", // ARM64_INS_LDSMINAL, "ldsminalb", // ARM64_INS_LDSMINALB, "ldsminalh", // ARM64_INS_LDSMINALH, "ldsminb", // ARM64_INS_LDSMINB, "ldsminh", // ARM64_INS_LDSMINH, "ldsminl", // ARM64_INS_LDSMINL, "ldsminlb", // ARM64_INS_LDSMINLB, "ldsminlh", // ARM64_INS_LDSMINLH, "ldtr", // ARM64_INS_LDTR, "ldtrb", // ARM64_INS_LDTRB, "ldtrh", // ARM64_INS_LDTRH, "ldtrsb", // ARM64_INS_LDTRSB, "ldtrsh", // ARM64_INS_LDTRSH, "ldtrsw", // ARM64_INS_LDTRSW, "ldumax", // ARM64_INS_LDUMAX, "ldumaxa", // ARM64_INS_LDUMAXA, "ldumaxab", // ARM64_INS_LDUMAXAB, "ldumaxah", // ARM64_INS_LDUMAXAH, "ldumaxal", // ARM64_INS_LDUMAXAL, "ldumaxalb", // ARM64_INS_LDUMAXALB, "ldumaxalh", // ARM64_INS_LDUMAXALH, "ldumaxb", // ARM64_INS_LDUMAXB, "ldumaxh", // ARM64_INS_LDUMAXH, "ldumaxl", // ARM64_INS_LDUMAXL, "ldumaxlb", // ARM64_INS_LDUMAXLB, "ldumaxlh", // ARM64_INS_LDUMAXLH, "ldumin", // ARM64_INS_LDUMIN, "ldumina", // ARM64_INS_LDUMINA, "lduminab", // ARM64_INS_LDUMINAB, "lduminah", // ARM64_INS_LDUMINAH, "lduminal", // ARM64_INS_LDUMINAL, "lduminalb", // ARM64_INS_LDUMINALB, "lduminalh", // ARM64_INS_LDUMINALH, "lduminb", // ARM64_INS_LDUMINB, "lduminh", // ARM64_INS_LDUMINH, "lduminl", // ARM64_INS_LDUMINL, "lduminlb", // ARM64_INS_LDUMINLB, "lduminlh", // ARM64_INS_LDUMINLH, "ldur", // ARM64_INS_LDUR, "ldurb", // ARM64_INS_LDURB, "ldurh", // ARM64_INS_LDURH, "ldursb", // ARM64_INS_LDURSB, "ldursh", // ARM64_INS_LDURSH, "ldursw", // ARM64_INS_LDURSW, "ldxp", // ARM64_INS_LDXP, "ldxr", // ARM64_INS_LDXR, "ldxrb", // ARM64_INS_LDXRB, "ldxrh", // ARM64_INS_LDXRH, "lsl", // ARM64_INS_LSL, "lslr", // ARM64_INS_LSLR, "lslv", // ARM64_INS_LSLV, "lsr", // ARM64_INS_LSR, "lsrr", // ARM64_INS_LSRR, "lsrv", // ARM64_INS_LSRV, "mad", // ARM64_INS_MAD, "madd", // ARM64_INS_MADD, "mla", // ARM64_INS_MLA, "mls", // ARM64_INS_MLS, "mneg", // ARM64_INS_MNEG, "mov", // ARM64_INS_MOV, "movi", // ARM64_INS_MOVI, "movk", // ARM64_INS_MOVK, "movn", // ARM64_INS_MOVN, "movprfx", // ARM64_INS_MOVPRFX, "movs", // ARM64_INS_MOVS, "movz", // ARM64_INS_MOVZ, "mrs", // ARM64_INS_MRS, "msb", // ARM64_INS_MSB, "msr", // ARM64_INS_MSR, "msub", // ARM64_INS_MSUB, "mul", // ARM64_INS_MUL, "mvn", // ARM64_INS_MVN, "mvni", // ARM64_INS_MVNI, "nand", // ARM64_INS_NAND, "nands", // ARM64_INS_NANDS, "neg", // ARM64_INS_NEG, "negs", // ARM64_INS_NEGS, "ngc", // ARM64_INS_NGC, "ngcs", // ARM64_INS_NGCS, "nop", // ARM64_INS_NOP, "nor", // ARM64_INS_NOR, "nors", // ARM64_INS_NORS, "not", // ARM64_INS_NOT, "nots", // ARM64_INS_NOTS, "orn", // ARM64_INS_ORN, "orns", // ARM64_INS_ORNS, "orr", // ARM64_INS_ORR, "orrs", // ARM64_INS_ORRS, "orv", // ARM64_INS_ORV, "pacda", // ARM64_INS_PACDA, "pacdb", // ARM64_INS_PACDB, "pacdza", // ARM64_INS_PACDZA, "pacdzb", // ARM64_INS_PACDZB, "pacga", // ARM64_INS_PACGA, "pacia", // ARM64_INS_PACIA, "pacia1716", // ARM64_INS_PACIA1716, "paciasp", // ARM64_INS_PACIASP, "paciaz", // ARM64_INS_PACIAZ, "pacib", // ARM64_INS_PACIB, "pacib1716", // ARM64_INS_PACIB1716, "pacibsp", // ARM64_INS_PACIBSP, "pacibz", // ARM64_INS_PACIBZ, "paciza", // ARM64_INS_PACIZA, "pacizb", // ARM64_INS_PACIZB, "pfalse", // ARM64_INS_PFALSE, "pfirst", // ARM64_INS_PFIRST, "pmul", // ARM64_INS_PMUL, "pmull", // ARM64_INS_PMULL, "pmull2", // ARM64_INS_PMULL2, "pnext", // ARM64_INS_PNEXT, "prfb", // ARM64_INS_PRFB, "prfd", // ARM64_INS_PRFD, "prfh", // ARM64_INS_PRFH, "prfm", // ARM64_INS_PRFM, "prfum", // ARM64_INS_PRFUM, "prfw", // ARM64_INS_PRFW, "psb", // ARM64_INS_PSB, "ptest", // ARM64_INS_PTEST, "ptrue", // ARM64_INS_PTRUE, "ptrues", // ARM64_INS_PTRUES, "punpkhi", // ARM64_INS_PUNPKHI, "punpklo", // ARM64_INS_PUNPKLO, "raddhn", // ARM64_INS_RADDHN, "raddhn2", // ARM64_INS_RADDHN2, "rax1", // ARM64_INS_RAX1, "rbit", // ARM64_INS_RBIT, "rdffr", // ARM64_INS_RDFFR, "rdffrs", // ARM64_INS_RDFFRS, "rdvl", // ARM64_INS_RDVL, "ret", // ARM64_INS_RET, "retaa", // ARM64_INS_RETAA, "retab", // ARM64_INS_RETAB, "rev", // ARM64_INS_REV, "rev16", // ARM64_INS_REV16, "rev32", // ARM64_INS_REV32, "rev64", // ARM64_INS_REV64, "revb", // ARM64_INS_REVB, "revh", // ARM64_INS_REVH, "revw", // ARM64_INS_REVW, "rmif", // ARM64_INS_RMIF, "ror", // ARM64_INS_ROR, "rorv", // ARM64_INS_RORV, "rshrn", // ARM64_INS_RSHRN, "rshrn2", // ARM64_INS_RSHRN2, "rsubhn", // ARM64_INS_RSUBHN, "rsubhn2", // ARM64_INS_RSUBHN2, "saba", // ARM64_INS_SABA, "sabal", // ARM64_INS_SABAL, "sabal2", // ARM64_INS_SABAL2, "sabd", // ARM64_INS_SABD, "sabdl", // ARM64_INS_SABDL, "sabdl2", // ARM64_INS_SABDL2, "sadalp", // ARM64_INS_SADALP, "saddl", // ARM64_INS_SADDL, "saddl2", // ARM64_INS_SADDL2, "saddlp", // ARM64_INS_SADDLP, "saddlv", // ARM64_INS_SADDLV, "saddv", // ARM64_INS_SADDV, "saddw", // ARM64_INS_SADDW, "saddw2", // ARM64_INS_SADDW2, "sbc", // ARM64_INS_SBC, "sbcs", // ARM64_INS_SBCS, "sbfm", // ARM64_INS_SBFM, "scvtf", // ARM64_INS_SCVTF, "sdiv", // ARM64_INS_SDIV, "sdivr", // ARM64_INS_SDIVR, "sdot", // ARM64_INS_SDOT, "sel", // ARM64_INS_SEL, "setf16", // ARM64_INS_SETF16, "setf8", // ARM64_INS_SETF8, "setffr", // ARM64_INS_SETFFR, "sev", // ARM64_INS_SEV, "sevl", // ARM64_INS_SEVL, "sha1c", // ARM64_INS_SHA1C, "sha1h", // ARM64_INS_SHA1H, "sha1m", // ARM64_INS_SHA1M, "sha1p", // ARM64_INS_SHA1P, "sha1su0", // ARM64_INS_SHA1SU0, "sha1su1", // ARM64_INS_SHA1SU1, "sha256h", // ARM64_INS_SHA256H, "sha256h2", // ARM64_INS_SHA256H2, "sha256su0", // ARM64_INS_SHA256SU0, "sha256su1", // ARM64_INS_SHA256SU1, "sha512h", // ARM64_INS_SHA512H, "sha512h2", // ARM64_INS_SHA512H2, "sha512su0", // ARM64_INS_SHA512SU0, "sha512su1", // ARM64_INS_SHA512SU1, "shadd", // ARM64_INS_SHADD, "shl", // ARM64_INS_SHL, "shll", // ARM64_INS_SHLL, "shll2", // ARM64_INS_SHLL2, "shrn", // ARM64_INS_SHRN, "shrn2", // ARM64_INS_SHRN2, "shsub", // ARM64_INS_SHSUB, "sli", // ARM64_INS_SLI, "sm3partw1", // ARM64_INS_SM3PARTW1, "sm3partw2", // ARM64_INS_SM3PARTW2, "sm3ss1", // ARM64_INS_SM3SS1, "sm3tt1a", // ARM64_INS_SM3TT1A, "sm3tt1b", // ARM64_INS_SM3TT1B, "sm3tt2a", // ARM64_INS_SM3TT2A, "sm3tt2b", // ARM64_INS_SM3TT2B, "sm4e", // ARM64_INS_SM4E, "sm4ekey", // ARM64_INS_SM4EKEY, "smaddl", // ARM64_INS_SMADDL, "smax", // ARM64_INS_SMAX, "smaxp", // ARM64_INS_SMAXP, "smaxv", // ARM64_INS_SMAXV, "smc", // ARM64_INS_SMC, "smin", // ARM64_INS_SMIN, "sminp", // ARM64_INS_SMINP, "sminv", // ARM64_INS_SMINV, "smlal", // ARM64_INS_SMLAL, "smlal2", // ARM64_INS_SMLAL2, "smlsl", // ARM64_INS_SMLSL, "smlsl2", // ARM64_INS_SMLSL2, "smnegl", // ARM64_INS_SMNEGL, "smov", // ARM64_INS_SMOV, "smsubl", // ARM64_INS_SMSUBL, "smulh", // ARM64_INS_SMULH, "smull", // ARM64_INS_SMULL, "smull2", // ARM64_INS_SMULL2, "splice", // ARM64_INS_SPLICE, "sqabs", // ARM64_INS_SQABS, "sqadd", // ARM64_INS_SQADD, "sqdecb", // ARM64_INS_SQDECB, "sqdecd", // ARM64_INS_SQDECD, "sqdech", // ARM64_INS_SQDECH, "sqdecp", // ARM64_INS_SQDECP, "sqdecw", // ARM64_INS_SQDECW, "sqdmlal", // ARM64_INS_SQDMLAL, "sqdmlal2", // ARM64_INS_SQDMLAL2, "sqdmlsl", // ARM64_INS_SQDMLSL, "sqdmlsl2", // ARM64_INS_SQDMLSL2, "sqdmulh", // ARM64_INS_SQDMULH, "sqdmull", // ARM64_INS_SQDMULL, "sqdmull2", // ARM64_INS_SQDMULL2, "sqincb", // ARM64_INS_SQINCB, "sqincd", // ARM64_INS_SQINCD, "sqinch", // ARM64_INS_SQINCH, "sqincp", // ARM64_INS_SQINCP, "sqincw", // ARM64_INS_SQINCW, "sqneg", // ARM64_INS_SQNEG, "sqrdmlah", // ARM64_INS_SQRDMLAH, "sqrdmlsh", // ARM64_INS_SQRDMLSH, "sqrdmulh", // ARM64_INS_SQRDMULH, "sqrshl", // ARM64_INS_SQRSHL, "sqrshrn", // ARM64_INS_SQRSHRN, "sqrshrn2", // ARM64_INS_SQRSHRN2, "sqrshrun", // ARM64_INS_SQRSHRUN, "sqrshrun2", // ARM64_INS_SQRSHRUN2, "sqshl", // ARM64_INS_SQSHL, "sqshlu", // ARM64_INS_SQSHLU, "sqshrn", // ARM64_INS_SQSHRN, "sqshrn2", // ARM64_INS_SQSHRN2, "sqshrun", // ARM64_INS_SQSHRUN, "sqshrun2", // ARM64_INS_SQSHRUN2, "sqsub", // ARM64_INS_SQSUB, "sqxtn", // ARM64_INS_SQXTN, "sqxtn2", // ARM64_INS_SQXTN2, "sqxtun", // ARM64_INS_SQXTUN, "sqxtun2", // ARM64_INS_SQXTUN2, "srhadd", // ARM64_INS_SRHADD, "sri", // ARM64_INS_SRI, "srshl", // ARM64_INS_SRSHL, "srshr", // ARM64_INS_SRSHR, "srsra", // ARM64_INS_SRSRA, "sshl", // ARM64_INS_SSHL, "sshll", // ARM64_INS_SSHLL, "sshll2", // ARM64_INS_SSHLL2, "sshr", // ARM64_INS_SSHR, "ssra", // ARM64_INS_SSRA, "ssubl", // ARM64_INS_SSUBL, "ssubl2", // ARM64_INS_SSUBL2, "ssubw", // ARM64_INS_SSUBW, "ssubw2", // ARM64_INS_SSUBW2, "st1", // ARM64_INS_ST1, "st1b", // ARM64_INS_ST1B, "st1d", // ARM64_INS_ST1D, "st1h", // ARM64_INS_ST1H, "st1w", // ARM64_INS_ST1W, "st2", // ARM64_INS_ST2, "st2b", // ARM64_INS_ST2B, "st2d", // ARM64_INS_ST2D, "st2h", // ARM64_INS_ST2H, "st2w", // ARM64_INS_ST2W, "st3", // ARM64_INS_ST3, "st3b", // ARM64_INS_ST3B, "st3d", // ARM64_INS_ST3D, "st3h", // ARM64_INS_ST3H, "st3w", // ARM64_INS_ST3W, "st4", // ARM64_INS_ST4, "st4b", // ARM64_INS_ST4B, "st4d", // ARM64_INS_ST4D, "st4h", // ARM64_INS_ST4H, "st4w", // ARM64_INS_ST4W, "stadd", // ARM64_INS_STADD, "staddb", // ARM64_INS_STADDB, "staddh", // ARM64_INS_STADDH, "staddl", // ARM64_INS_STADDL, "staddlb", // ARM64_INS_STADDLB, "staddlh", // ARM64_INS_STADDLH, "stclr", // ARM64_INS_STCLR, "stclrb", // ARM64_INS_STCLRB, "stclrh", // ARM64_INS_STCLRH, "stclrl", // ARM64_INS_STCLRL, "stclrlb", // ARM64_INS_STCLRLB, "stclrlh", // ARM64_INS_STCLRLH, "steor", // ARM64_INS_STEOR, "steorb", // ARM64_INS_STEORB, "steorh", // ARM64_INS_STEORH, "steorl", // ARM64_INS_STEORL, "steorlb", // ARM64_INS_STEORLB, "steorlh", // ARM64_INS_STEORLH, "stllr", // ARM64_INS_STLLR, "stllrb", // ARM64_INS_STLLRB, "stllrh", // ARM64_INS_STLLRH, "stlr", // ARM64_INS_STLR, "stlrb", // ARM64_INS_STLRB, "stlrh", // ARM64_INS_STLRH, "stlur", // ARM64_INS_STLUR, "stlurb", // ARM64_INS_STLURB, "stlurh", // ARM64_INS_STLURH, "stlxp", // ARM64_INS_STLXP, "stlxr", // ARM64_INS_STLXR, "stlxrb", // ARM64_INS_STLXRB, "stlxrh", // ARM64_INS_STLXRH, "stnp", // ARM64_INS_STNP, "stnt1b", // ARM64_INS_STNT1B, "stnt1d", // ARM64_INS_STNT1D, "stnt1h", // ARM64_INS_STNT1H, "stnt1w", // ARM64_INS_STNT1W, "stp", // ARM64_INS_STP, "str", // ARM64_INS_STR, "strb", // ARM64_INS_STRB, "strh", // ARM64_INS_STRH, "stset", // ARM64_INS_STSET, "stsetb", // ARM64_INS_STSETB, "stseth", // ARM64_INS_STSETH, "stsetl", // ARM64_INS_STSETL, "stsetlb", // ARM64_INS_STSETLB, "stsetlh", // ARM64_INS_STSETLH, "stsmax", // ARM64_INS_STSMAX, "stsmaxb", // ARM64_INS_STSMAXB, "stsmaxh", // ARM64_INS_STSMAXH, "stsmaxl", // ARM64_INS_STSMAXL, "stsmaxlb", // ARM64_INS_STSMAXLB, "stsmaxlh", // ARM64_INS_STSMAXLH, "stsmin", // ARM64_INS_STSMIN, "stsminb", // ARM64_INS_STSMINB, "stsminh", // ARM64_INS_STSMINH, "stsminl", // ARM64_INS_STSMINL, "stsminlb", // ARM64_INS_STSMINLB, "stsminlh", // ARM64_INS_STSMINLH, "sttr", // ARM64_INS_STTR, "sttrb", // ARM64_INS_STTRB, "sttrh", // ARM64_INS_STTRH, "stumax", // ARM64_INS_STUMAX, "stumaxb", // ARM64_INS_STUMAXB, "stumaxh", // ARM64_INS_STUMAXH, "stumaxl", // ARM64_INS_STUMAXL, "stumaxlb", // ARM64_INS_STUMAXLB, "stumaxlh", // ARM64_INS_STUMAXLH, "stumin", // ARM64_INS_STUMIN, "stuminb", // ARM64_INS_STUMINB, "stuminh", // ARM64_INS_STUMINH, "stuminl", // ARM64_INS_STUMINL, "stuminlb", // ARM64_INS_STUMINLB, "stuminlh", // ARM64_INS_STUMINLH, "stur", // ARM64_INS_STUR, "sturb", // ARM64_INS_STURB, "sturh", // ARM64_INS_STURH, "stxp", // ARM64_INS_STXP, "stxr", // ARM64_INS_STXR, "stxrb", // ARM64_INS_STXRB, "stxrh", // ARM64_INS_STXRH, "sub", // ARM64_INS_SUB, "subhn", // ARM64_INS_SUBHN, "subhn2", // ARM64_INS_SUBHN2, "subr", // ARM64_INS_SUBR, "subs", // ARM64_INS_SUBS, "sunpkhi", // ARM64_INS_SUNPKHI, "sunpklo", // ARM64_INS_SUNPKLO, "suqadd", // ARM64_INS_SUQADD, "svc", // ARM64_INS_SVC, "swp", // ARM64_INS_SWP, "swpa", // ARM64_INS_SWPA, "swpab", // ARM64_INS_SWPAB, "swpah", // ARM64_INS_SWPAH, "swpal", // ARM64_INS_SWPAL, "swpalb", // ARM64_INS_SWPALB, "swpalh", // ARM64_INS_SWPALH, "swpb", // ARM64_INS_SWPB, "swph", // ARM64_INS_SWPH, "swpl", // ARM64_INS_SWPL, "swplb", // ARM64_INS_SWPLB, "swplh", // ARM64_INS_SWPLH, "sxtb", // ARM64_INS_SXTB, "sxth", // ARM64_INS_SXTH, "sxtl", // ARM64_INS_SXTL, "sxtl2", // ARM64_INS_SXTL2, "sxtw", // ARM64_INS_SXTW, "sys", // ARM64_INS_SYS, "sysl", // ARM64_INS_SYSL, "tbl", // ARM64_INS_TBL, "tbnz", // ARM64_INS_TBNZ, "tbx", // ARM64_INS_TBX, "tbz", // ARM64_INS_TBZ, "trn1", // ARM64_INS_TRN1, "trn2", // ARM64_INS_TRN2, "tsb", // ARM64_INS_TSB, "tst", // ARM64_INS_TST, "uaba", // ARM64_INS_UABA, "uabal", // ARM64_INS_UABAL, "uabal2", // ARM64_INS_UABAL2, "uabd", // ARM64_INS_UABD, "uabdl", // ARM64_INS_UABDL, "uabdl2", // ARM64_INS_UABDL2, "uadalp", // ARM64_INS_UADALP, "uaddl", // ARM64_INS_UADDL, "uaddl2", // ARM64_INS_UADDL2, "uaddlp", // ARM64_INS_UADDLP, "uaddlv", // ARM64_INS_UADDLV, "uaddv", // ARM64_INS_UADDV, "uaddw", // ARM64_INS_UADDW, "uaddw2", // ARM64_INS_UADDW2, "ubfm", // ARM64_INS_UBFM, "ucvtf", // ARM64_INS_UCVTF, "udiv", // ARM64_INS_UDIV, "udivr", // ARM64_INS_UDIVR, "udot", // ARM64_INS_UDOT, "uhadd", // ARM64_INS_UHADD, "uhsub", // ARM64_INS_UHSUB, "umaddl", // ARM64_INS_UMADDL, "umax", // ARM64_INS_UMAX, "umaxp", // ARM64_INS_UMAXP, "umaxv", // ARM64_INS_UMAXV, "umin", // ARM64_INS_UMIN, "uminp", // ARM64_INS_UMINP, "uminv", // ARM64_INS_UMINV, "umlal", // ARM64_INS_UMLAL, "umlal2", // ARM64_INS_UMLAL2, "umlsl", // ARM64_INS_UMLSL, "umlsl2", // ARM64_INS_UMLSL2, "umnegl", // ARM64_INS_UMNEGL, "umov", // ARM64_INS_UMOV, "umsubl", // ARM64_INS_UMSUBL, "umulh", // ARM64_INS_UMULH, "umull", // ARM64_INS_UMULL, "umull2", // ARM64_INS_UMULL2, "uqadd", // ARM64_INS_UQADD, "uqdecb", // ARM64_INS_UQDECB, "uqdecd", // ARM64_INS_UQDECD, "uqdech", // ARM64_INS_UQDECH, "uqdecp", // ARM64_INS_UQDECP, "uqdecw", // ARM64_INS_UQDECW, "uqincb", // ARM64_INS_UQINCB, "uqincd", // ARM64_INS_UQINCD, "uqinch", // ARM64_INS_UQINCH, "uqincp", // ARM64_INS_UQINCP, "uqincw", // ARM64_INS_UQINCW, "uqrshl", // ARM64_INS_UQRSHL, "uqrshrn", // ARM64_INS_UQRSHRN, "uqrshrn2", // ARM64_INS_UQRSHRN2, "uqshl", // ARM64_INS_UQSHL, "uqshrn", // ARM64_INS_UQSHRN, "uqshrn2", // ARM64_INS_UQSHRN2, "uqsub", // ARM64_INS_UQSUB, "uqxtn", // ARM64_INS_UQXTN, "uqxtn2", // ARM64_INS_UQXTN2, "urecpe", // ARM64_INS_URECPE, "urhadd", // ARM64_INS_URHADD, "urshl", // ARM64_INS_URSHL, "urshr", // ARM64_INS_URSHR, "ursqrte", // ARM64_INS_URSQRTE, "ursra", // ARM64_INS_URSRA, "ushl", // ARM64_INS_USHL, "ushll", // ARM64_INS_USHLL, "ushll2", // ARM64_INS_USHLL2, "ushr", // ARM64_INS_USHR, "usqadd", // ARM64_INS_USQADD, "usra", // ARM64_INS_USRA, "usubl", // ARM64_INS_USUBL, "usubl2", // ARM64_INS_USUBL2, "usubw", // ARM64_INS_USUBW, "usubw2", // ARM64_INS_USUBW2, "uunpkhi", // ARM64_INS_UUNPKHI, "uunpklo", // ARM64_INS_UUNPKLO, "uxtb", // ARM64_INS_UXTB, "uxth", // ARM64_INS_UXTH, "uxtl", // ARM64_INS_UXTL, "uxtl2", // ARM64_INS_UXTL2, "uxtw", // ARM64_INS_UXTW, "uzp1", // ARM64_INS_UZP1, "uzp2", // ARM64_INS_UZP2, "wfe", // ARM64_INS_WFE, "wfi", // ARM64_INS_WFI, "whilele", // ARM64_INS_WHILELE, "whilelo", // ARM64_INS_WHILELO, "whilels", // ARM64_INS_WHILELS, "whilelt", // ARM64_INS_WHILELT, "wrffr", // ARM64_INS_WRFFR, "xar", // ARM64_INS_XAR, "xpacd", // ARM64_INS_XPACD, "xpaci", // ARM64_INS_XPACI, "xpaclri", // ARM64_INS_XPACLRI, "xtn", // ARM64_INS_XTN, "xtn2", // ARM64_INS_XTN2, "yield", // ARM64_INS_YIELD, "zip1", // ARM64_INS_ZIP1, "zip2", // ARM64_INS_ZIP2, capstone-sys-0.15.0/capstone/arch/AArch64/AArch64MappingInsnOp.inc000064400000000000000000013705160072674642500225530ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { /* AArch64_ABS_ZPmZ_B, AArch64_INS_ABS: abs */ 0, { 0 } }, { /* AArch64_ABS_ZPmZ_D, AArch64_INS_ABS: abs */ 0, { 0 } }, { /* AArch64_ABS_ZPmZ_H, AArch64_INS_ABS: abs */ 0, { 0 } }, { /* AArch64_ABS_ZPmZ_S, AArch64_INS_ABS: abs */ 0, { 0 } }, { /* AArch64_ABSv16i8, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv1i64, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv2i32, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv2i64, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv4i16, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv4i32, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv8i16, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ABSv8i8, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADCSWr, AArch64_INS_ADCS: adcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADCSXr, AArch64_INS_ADCS: adcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADCWr, AArch64_INS_ADC: adc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADCXr, AArch64_INS_ADC: adc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDHNv2i64_v2i32, AArch64_INS_ADDHN: addhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDHNv2i64_v4i32, AArch64_INS_ADDHN2: addhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDHNv4i32_v4i16, AArch64_INS_ADDHN: addhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDHNv4i32_v8i16, AArch64_INS_ADDHN2: addhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDHNv8i16_v16i8, AArch64_INS_ADDHN2: addhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDHNv8i16_v8i8, AArch64_INS_ADDHN: addhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPL_XXI, AArch64_INS_ADDPL: addpl */ 0, { 0 } }, { /* AArch64_ADDPv16i8, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPv2i32, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPv2i64, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPv2i64p, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADDPv4i16, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPv4i32, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPv8i16, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDPv8i8, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDSWri, AArch64_INS_ADDS: adds */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ,0 } }, { /* AArch64_ADDSWrs, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDSWrx, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDSXri, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDSXrs, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDSXrx, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDSXrx64, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDVL_XXI, AArch64_INS_ADDVL: addvl */ 0, { 0 } }, { /* AArch64_ADDVv16i8v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADDVv4i16v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADDVv4i32v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADDVv8i16v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADDVv8i8v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADDWri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDWrs, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDWrx, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDXri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDXrs, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDXrx, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDXrx64, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADD_ZI_B, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZI_D, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZI_H, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZI_S, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZPmZ_B, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZPmZ_D, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZPmZ_H, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZPmZ_S, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZZZ_B, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZZZ_D, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZZZ_H, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADD_ZZZ_S, AArch64_INS_ADD: add */ 0, { 0 } }, { /* AArch64_ADDv16i8, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv1i64, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv2i32, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv2i64, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv4i16, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv4i32, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv8i16, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADDv8i8, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ADR, AArch64_INS_ADR: adr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADRP, AArch64_INS_ADRP: adrp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ADR_LSL_ZZZ_D_0, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_D_1, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_D_2, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_D_3, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_S_0, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_S_1, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_S_2, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_LSL_ZZZ_S_3, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_SXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_SXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_SXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_SXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_UXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_UXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_UXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_ADR_UXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ 0, { 0 } }, { /* AArch64_AESDrr, AArch64_INS_AESD: aesd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_AESErr, AArch64_INS_AESE: aese */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_AESIMCrr, AArch64_INS_AESIMC: aesimc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_AESMCrr, AArch64_INS_AESMC: aesmc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ANDSWri, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDSWrs, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDSXri, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDSXrs, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDS_PPzPP, AArch64_INS_ANDS: ands */ 0, { 0 } }, { /* AArch64_ANDV_VPZ_B, AArch64_INS_ANDV: andv */ 0, { 0 } }, { /* AArch64_ANDV_VPZ_D, AArch64_INS_ANDV: andv */ 0, { 0 } }, { /* AArch64_ANDV_VPZ_H, AArch64_INS_ANDV: andv */ 0, { 0 } }, { /* AArch64_ANDV_VPZ_S, AArch64_INS_ANDV: andv */ 0, { 0 } }, { /* AArch64_ANDWri, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDWrs, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDXri, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDXrs, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_AND_PPzPP, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_AND_ZI, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_AND_ZPmZ_B, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_AND_ZPmZ_D, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_AND_ZPmZ_H, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_AND_ZPmZ_S, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_AND_ZZZ, AArch64_INS_AND: and */ 0, { 0 } }, { /* AArch64_ANDv16i8, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ANDv8i8, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ASRD_ZPmI_B, AArch64_INS_ASRD: asrd */ 0, { 0 } }, { /* AArch64_ASRD_ZPmI_D, AArch64_INS_ASRD: asrd */ 0, { 0 } }, { /* AArch64_ASRD_ZPmI_H, AArch64_INS_ASRD: asrd */ 0, { 0 } }, { /* AArch64_ASRD_ZPmI_S, AArch64_INS_ASRD: asrd */ 0, { 0 } }, { /* AArch64_ASRR_ZPmZ_B, AArch64_INS_ASRR: asrr */ 0, { 0 } }, { /* AArch64_ASRR_ZPmZ_D, AArch64_INS_ASRR: asrr */ 0, { 0 } }, { /* AArch64_ASRR_ZPmZ_H, AArch64_INS_ASRR: asrr */ 0, { 0 } }, { /* AArch64_ASRR_ZPmZ_S, AArch64_INS_ASRR: asrr */ 0, { 0 } }, { /* AArch64_ASRVWr, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ASRVXr, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ASR_WIDE_ZPmZ_B, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_WIDE_ZPmZ_H, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_WIDE_ZPmZ_S, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_WIDE_ZZZ_B, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_WIDE_ZZZ_H, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_WIDE_ZZZ_S, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmI_B, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmI_D, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmI_H, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmI_S, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmZ_B, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmZ_D, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmZ_H, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZPmZ_S, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZZI_B, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZZI_D, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZZI_H, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_ASR_ZZI_S, AArch64_INS_ASR: asr */ 0, { 0 } }, { /* AArch64_AUTDA, AArch64_INS_AUTDA: autda */ 0, { 0 } }, { /* AArch64_AUTDB, AArch64_INS_AUTDB: autdb */ 0, { 0 } }, { /* AArch64_AUTDZA, AArch64_INS_AUTDZA: autdza */ 0, { 0 } }, { /* AArch64_AUTDZB, AArch64_INS_AUTDZB: autdzb */ 0, { 0 } }, { /* AArch64_AUTIA, AArch64_INS_AUTIA: autia */ 0, { 0 } }, { /* AArch64_AUTIA1716, AArch64_INS_AUTIA1716: autia1716 */ 0, { 0 } }, { /* AArch64_AUTIASP, AArch64_INS_AUTIASP: autiasp */ 0, { 0 } }, { /* AArch64_AUTIAZ, AArch64_INS_AUTIAZ: autiaz */ 0, { 0 } }, { /* AArch64_AUTIB, AArch64_INS_AUTIB: autib */ 0, { 0 } }, { /* AArch64_AUTIB1716, AArch64_INS_AUTIB1716: autib1716 */ 0, { 0 } }, { /* AArch64_AUTIBSP, AArch64_INS_AUTIBSP: autibsp */ 0, { 0 } }, { /* AArch64_AUTIBZ, AArch64_INS_AUTIBZ: autibz */ 0, { 0 } }, { /* AArch64_AUTIZA, AArch64_INS_AUTIZA: autiza */ 0, { 0 } }, { /* AArch64_AUTIZB, AArch64_INS_AUTIZB: autizb */ 0, { 0 } }, { /* AArch64_B, AArch64_INS_B: b */ 0, { CS_AC_READ, 0 } }, { /* AArch64_BCAX, AArch64_INS_BCAX: bcax */ 0, { 0 } }, { /* AArch64_BFMWri, AArch64_INS_BFM: bfm */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_BFMXri, AArch64_INS_BFM: bfm */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_BICSWrs, AArch64_INS_BICS: bics */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BICSXrs, AArch64_INS_BICS: bics */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BICS_PPzPP, AArch64_INS_BICS: bics */ 0, { 0 } }, { /* AArch64_BICWrs, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BICXrs, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BIC_PPzPP, AArch64_INS_BIC: bic */ 0, { 0 } }, { /* AArch64_BIC_ZPmZ_B, AArch64_INS_BIC: bic */ 0, { 0 } }, { /* AArch64_BIC_ZPmZ_D, AArch64_INS_BIC: bic */ 0, { 0 } }, { /* AArch64_BIC_ZPmZ_H, AArch64_INS_BIC: bic */ 0, { 0 } }, { /* AArch64_BIC_ZPmZ_S, AArch64_INS_BIC: bic */ 0, { 0 } }, { /* AArch64_BIC_ZZZ, AArch64_INS_BIC: bic */ 0, { 0 } }, { /* AArch64_BICv16i8, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BICv2i32, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_BICv4i16, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_BICv4i32, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_BICv8i16, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_BICv8i8, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_BIFv16i8, AArch64_INS_BIF: bif */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BIFv8i8, AArch64_INS_BIF: bif */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BITv16i8, AArch64_INS_BIT: bit */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BITv8i8, AArch64_INS_BIT: bit */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BL, AArch64_INS_BL: bl */ 0, { CS_AC_READ, 0 } }, { /* AArch64_BLR, AArch64_INS_BLR: blr */ 0, { CS_AC_READ, 0 } }, { /* AArch64_BLRAA, AArch64_INS_BLRAA: blraa */ 0, { 0 } }, { /* AArch64_BLRAAZ, AArch64_INS_BLRAAZ: blraaz */ 0, { 0 } }, { /* AArch64_BLRAB, AArch64_INS_BLRAB: blrab */ 0, { 0 } }, { /* AArch64_BLRABZ, AArch64_INS_BLRABZ: blrabz */ 0, { 0 } }, { /* AArch64_BR, AArch64_INS_BR: br */ 0, { CS_AC_READ, 0 } }, { /* AArch64_BRAA, AArch64_INS_BRAA: braa */ 0, { 0 } }, { /* AArch64_BRAAZ, AArch64_INS_BRAAZ: braaz */ 0, { 0 } }, { /* AArch64_BRAB, AArch64_INS_BRAB: brab */ 0, { 0 } }, { /* AArch64_BRABZ, AArch64_INS_BRABZ: brabz */ 0, { 0 } }, { /* AArch64_BRK, AArch64_INS_BRK: brk */ 0, { CS_AC_READ, 0 } }, { /* AArch64_BRKAS_PPzP, AArch64_INS_BRKAS: brkas */ 0, { 0 } }, { /* AArch64_BRKA_PPmP, AArch64_INS_BRKA: brka */ 0, { 0 } }, { /* AArch64_BRKA_PPzP, AArch64_INS_BRKA: brka */ 0, { 0 } }, { /* AArch64_BRKBS_PPzP, AArch64_INS_BRKBS: brkbs */ 0, { 0 } }, { /* AArch64_BRKB_PPmP, AArch64_INS_BRKB: brkb */ 0, { 0 } }, { /* AArch64_BRKB_PPzP, AArch64_INS_BRKB: brkb */ 0, { 0 } }, { /* AArch64_BRKNS_PPzP, AArch64_INS_BRKNS: brkns */ 0, { 0 } }, { /* AArch64_BRKN_PPzP, AArch64_INS_BRKN: brkn */ 0, { 0 } }, { /* AArch64_BRKPAS_PPzPP, AArch64_INS_BRKPAS: brkpas */ 0, { 0 } }, { /* AArch64_BRKPA_PPzPP, AArch64_INS_BRKPA: brkpa */ 0, { 0 } }, { /* AArch64_BRKPBS_PPzPP, AArch64_INS_BRKPBS: brkpbs */ 0, { 0 } }, { /* AArch64_BRKPB_PPzPP, AArch64_INS_BRKPB: brkpb */ 0, { 0 } }, { /* AArch64_BSLv16i8, AArch64_INS_BSL: bsl */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_BSLv8i8, AArch64_INS_BSL: bsl */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_Bcc, AArch64_INS_B: b */ 0, { CS_AC_READ, 0 } }, { /* AArch64_CASAB, AArch64_INS_CASAB: casab */ 0, { 0 } }, { /* AArch64_CASAH, AArch64_INS_CASAH: casah */ 0, { 0 } }, { /* AArch64_CASALB, AArch64_INS_CASALB: casalb */ 0, { 0 } }, { /* AArch64_CASALH, AArch64_INS_CASALH: casalh */ 0, { 0 } }, { /* AArch64_CASALW, AArch64_INS_CASAL: casal */ 0, { 0 } }, { /* AArch64_CASALX, AArch64_INS_CASAL: casal */ 0, { 0 } }, { /* AArch64_CASAW, AArch64_INS_CASA: casa */ 0, { 0 } }, { /* AArch64_CASAX, AArch64_INS_CASA: casa */ 0, { 0 } }, { /* AArch64_CASB, AArch64_INS_CASB: casb */ 0, { 0 } }, { /* AArch64_CASH, AArch64_INS_CASH: cash */ 0, { 0 } }, { /* AArch64_CASLB, AArch64_INS_CASLB: caslb */ 0, { 0 } }, { /* AArch64_CASLH, AArch64_INS_CASLH: caslh */ 0, { 0 } }, { /* AArch64_CASLW, AArch64_INS_CASL: casl */ 0, { 0 } }, { /* AArch64_CASLX, AArch64_INS_CASL: casl */ 0, { 0 } }, { /* AArch64_CASPALW, AArch64_INS_CASPAL: caspal */ 0, { 0 } }, { /* AArch64_CASPALX, AArch64_INS_CASPAL: caspal */ 0, { 0 } }, { /* AArch64_CASPAW, AArch64_INS_CASPA: caspa */ 0, { 0 } }, { /* AArch64_CASPAX, AArch64_INS_CASPA: caspa */ 0, { 0 } }, { /* AArch64_CASPLW, AArch64_INS_CASPL: caspl */ 0, { 0 } }, { /* AArch64_CASPLX, AArch64_INS_CASPL: caspl */ 0, { 0 } }, { /* AArch64_CASPW, AArch64_INS_CASP: casp */ 0, { 0 } }, { /* AArch64_CASPX, AArch64_INS_CASP: casp */ 0, { 0 } }, { /* AArch64_CASW, AArch64_INS_CAS: cas */ 0, { 0 } }, { /* AArch64_CASX, AArch64_INS_CAS: cas */ 0, { 0 } }, { /* AArch64_CBNZW, AArch64_INS_CBNZ: cbnz */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CBNZX, AArch64_INS_CBNZ: cbnz */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CBZW, AArch64_INS_CBZ: cbz */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CBZX, AArch64_INS_CBZ: cbz */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CCMNWi, AArch64_INS_CCMN: ccmn */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMNWr, AArch64_INS_CCMN: ccmn */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMNXi, AArch64_INS_CCMN: ccmn */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMNXr, AArch64_INS_CCMN: ccmn */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMPWi, AArch64_INS_CCMP: ccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMPWr, AArch64_INS_CCMP: ccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMPXi, AArch64_INS_CCMP: ccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CCMPXr, AArch64_INS_CCMP: ccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CFINV, AArch64_INS_CFINV: cfinv */ 0, { 0 } }, { /* AArch64_CLASTA_RPZ_B, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_RPZ_D, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_RPZ_H, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_RPZ_S, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_VPZ_B, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_VPZ_D, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_VPZ_H, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_VPZ_S, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_ZPZ_B, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_ZPZ_D, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_ZPZ_H, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTA_ZPZ_S, AArch64_INS_CLASTA: clasta */ 0, { 0 } }, { /* AArch64_CLASTB_RPZ_B, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_RPZ_D, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_RPZ_H, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_RPZ_S, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_VPZ_B, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_VPZ_D, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_VPZ_H, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_VPZ_S, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_ZPZ_B, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_ZPZ_D, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_ZPZ_H, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLASTB_ZPZ_S, AArch64_INS_CLASTB: clastb */ 0, { 0 } }, { /* AArch64_CLREX, AArch64_INS_CLREX: clrex */ 0, { CS_AC_READ, 0 } }, { /* AArch64_CLSWr, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLSXr, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLS_ZPmZ_B, AArch64_INS_CLS: cls */ 0, { 0 } }, { /* AArch64_CLS_ZPmZ_D, AArch64_INS_CLS: cls */ 0, { 0 } }, { /* AArch64_CLS_ZPmZ_H, AArch64_INS_CLS: cls */ 0, { 0 } }, { /* AArch64_CLS_ZPmZ_S, AArch64_INS_CLS: cls */ 0, { 0 } }, { /* AArch64_CLSv16i8, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLSv2i32, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLSv4i16, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLSv4i32, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLSv8i16, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLSv8i8, AArch64_INS_CLS: cls */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZWr, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZXr, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZ_ZPmZ_B, AArch64_INS_CLZ: clz */ 0, { 0 } }, { /* AArch64_CLZ_ZPmZ_D, AArch64_INS_CLZ: clz */ 0, { 0 } }, { /* AArch64_CLZ_ZPmZ_H, AArch64_INS_CLZ: clz */ 0, { 0 } }, { /* AArch64_CLZ_ZPmZ_S, AArch64_INS_CLZ: clz */ 0, { 0 } }, { /* AArch64_CLZv16i8, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZv2i32, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZv4i16, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZv4i32, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZv8i16, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CLZv8i8, AArch64_INS_CLZ: clz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CMEQv16i8, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv16i8rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv1i64, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv1i64rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv2i32, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv2i32rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv2i64, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv2i64rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv4i16, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv4i16rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv4i32, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv4i32rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv8i16, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv8i16rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv8i8, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMEQv8i8rz, AArch64_INS_CMEQ: cmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv16i8, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv16i8rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv1i64, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv1i64rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv2i32, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv2i32rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv2i64, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv2i64rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv4i16, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv4i16rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv4i32, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv4i32rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv8i16, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv8i16rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv8i8, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGEv8i8rz, AArch64_INS_CMGE: cmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv16i8, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv16i8rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv1i64, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv1i64rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv2i32, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv2i32rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv2i64, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv2i64rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv4i16, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv4i16rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv4i32, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv4i32rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv8i16, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv8i16rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv8i8, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMGTv8i8rz, AArch64_INS_CMGT: cmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv16i8, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv1i64, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv2i32, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv2i64, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv4i16, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv4i32, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv8i16, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHIv8i8, AArch64_INS_CMHI: cmhi */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv16i8, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv1i64, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv2i32, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv2i64, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv4i16, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv4i32, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv8i16, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMHSv8i8, AArch64_INS_CMHS: cmhs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv16i8rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv1i64rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv2i32rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv2i64rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv4i16rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv4i32rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv8i16rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLEv8i8rz, AArch64_INS_CMLE: cmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv16i8rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv1i64rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv2i32rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv2i64rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv4i16rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv4i32rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv8i16rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMLTv8i8rz, AArch64_INS_CMLT: cmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMPEQ_PPzZI_B, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZI_D, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZI_H, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZI_S, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZZ_D, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_WIDE_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_WIDE_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPEQ_WIDE_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZI_B, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZI_D, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZI_H, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZI_S, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZZ_D, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_WIDE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_WIDE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGE_WIDE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZI_B, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZI_D, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZI_H, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZI_S, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZZ_D, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_WIDE_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_WIDE_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPGT_WIDE_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZI_B, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZI_D, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZI_H, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZI_S, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZZ_D, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_WIDE_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_WIDE_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHI_WIDE_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZI_B, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZI_D, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZI_H, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZI_S, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZZ_D, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_WIDE_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_WIDE_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPHS_WIDE_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ 0, { 0 } }, { /* AArch64_CMPLE_PPzZI_B, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLE_PPzZI_D, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLE_PPzZI_H, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLE_PPzZI_S, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLE_WIDE_PPzZZ_B, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLE_WIDE_PPzZZ_H, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLE_WIDE_PPzZZ_S, AArch64_INS_CMPLE: cmple */ 0, { 0 } }, { /* AArch64_CMPLO_PPzZI_B, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLO_PPzZI_D, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLO_PPzZI_H, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLO_PPzZI_S, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLO_WIDE_PPzZZ_B, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLO_WIDE_PPzZZ_H, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLO_WIDE_PPzZZ_S, AArch64_INS_CMPLO: cmplo */ 0, { 0 } }, { /* AArch64_CMPLS_PPzZI_B, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLS_PPzZI_D, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLS_PPzZI_H, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLS_PPzZI_S, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLS_WIDE_PPzZZ_B, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLS_WIDE_PPzZZ_H, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLS_WIDE_PPzZZ_S, AArch64_INS_CMPLS: cmpls */ 0, { 0 } }, { /* AArch64_CMPLT_PPzZI_B, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPLT_PPzZI_D, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPLT_PPzZI_H, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPLT_PPzZI_S, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPLT_WIDE_PPzZZ_B, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPLT_WIDE_PPzZZ_H, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPLT_WIDE_PPzZZ_S, AArch64_INS_CMPLT: cmplt */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZI_B, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZI_D, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZI_H, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZI_S, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZZ_D, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_WIDE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_WIDE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMPNE_WIDE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ 0, { 0 } }, { /* AArch64_CMTSTv16i8, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv1i64, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv2i32, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv2i64, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv4i16, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv4i32, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv8i16, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CMTSTv8i8, AArch64_INS_CMTST: cmtst */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CNOT_ZPmZ_B, AArch64_INS_CNOT: cnot */ 0, { 0 } }, { /* AArch64_CNOT_ZPmZ_D, AArch64_INS_CNOT: cnot */ 0, { 0 } }, { /* AArch64_CNOT_ZPmZ_H, AArch64_INS_CNOT: cnot */ 0, { 0 } }, { /* AArch64_CNOT_ZPmZ_S, AArch64_INS_CNOT: cnot */ 0, { 0 } }, { /* AArch64_CNTB_XPiI, AArch64_INS_CNTB: cntb */ 0, { 0 } }, { /* AArch64_CNTD_XPiI, AArch64_INS_CNTD: cntd */ 0, { 0 } }, { /* AArch64_CNTH_XPiI, AArch64_INS_CNTH: cnth */ 0, { 0 } }, { /* AArch64_CNTP_XPP_B, AArch64_INS_CNTP: cntp */ 0, { 0 } }, { /* AArch64_CNTP_XPP_D, AArch64_INS_CNTP: cntp */ 0, { 0 } }, { /* AArch64_CNTP_XPP_H, AArch64_INS_CNTP: cntp */ 0, { 0 } }, { /* AArch64_CNTP_XPP_S, AArch64_INS_CNTP: cntp */ 0, { 0 } }, { /* AArch64_CNTW_XPiI, AArch64_INS_CNTW: cntw */ 0, { 0 } }, { /* AArch64_CNT_ZPmZ_B, AArch64_INS_CNT: cnt */ 0, { 0 } }, { /* AArch64_CNT_ZPmZ_D, AArch64_INS_CNT: cnt */ 0, { 0 } }, { /* AArch64_CNT_ZPmZ_H, AArch64_INS_CNT: cnt */ 0, { 0 } }, { /* AArch64_CNT_ZPmZ_S, AArch64_INS_CNT: cnt */ 0, { 0 } }, { /* AArch64_CNTv16i8, AArch64_INS_CNT: cnt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_CNTv8i8, AArch64_INS_CNT: cnt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_COMPACT_ZPZ_D, AArch64_INS_COMPACT: compact */ 0, { 0 } }, { /* AArch64_COMPACT_ZPZ_S, AArch64_INS_COMPACT: compact */ 0, { 0 } }, { /* AArch64_CPY_ZPmI_B, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmI_D, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmI_H, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmI_S, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmR_B, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmR_D, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmR_H, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmR_S, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmV_B, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmV_D, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmV_H, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPmV_S, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPzI_B, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPzI_D, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPzI_H, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPY_ZPzI_S, AArch64_INS_CPY: cpy */ 0, { 0 } }, { /* AArch64_CPYi16, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CPYi32, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CPYi64, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CPYi8, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32Brr, AArch64_INS_CRC32B: crc32b */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32CBrr, AArch64_INS_CRC32CB: crc32cb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32CHrr, AArch64_INS_CRC32CH: crc32ch */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32CWrr, AArch64_INS_CRC32CW: crc32cw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32CXrr, AArch64_INS_CRC32CX: crc32cx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32Hrr, AArch64_INS_CRC32H: crc32h */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32Wrr, AArch64_INS_CRC32W: crc32w */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CRC32Xrr, AArch64_INS_CRC32X: crc32x */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_CSELWr, AArch64_INS_CSEL: csel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSELXr, AArch64_INS_CSEL: csel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSINCWr, AArch64_INS_CINC: cinc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSINCXr, AArch64_INS_CINC: cinc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSINVWr, AArch64_INS_CINV: cinv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSINVXr, AArch64_INS_CINV: cinv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSNEGWr, AArch64_INS_CNEG: cneg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CSNEGXr, AArch64_INS_CNEG: cneg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_CTERMEQ_WW, AArch64_INS_CTERMEQ: ctermeq */ 0, { 0 } }, { /* AArch64_CTERMEQ_XX, AArch64_INS_CTERMEQ: ctermeq */ 0, { 0 } }, { /* AArch64_CTERMNE_WW, AArch64_INS_CTERMNE: ctermne */ 0, { 0 } }, { /* AArch64_CTERMNE_XX, AArch64_INS_CTERMNE: ctermne */ 0, { 0 } }, { /* AArch64_DCPS1, AArch64_INS_DCPS1: dcps1 */ 0, { CS_AC_READ, 0 } }, { /* AArch64_DCPS2, AArch64_INS_DCPS2: dcps2 */ 0, { CS_AC_READ, 0 } }, { /* AArch64_DCPS3, AArch64_INS_DCPS3: dcps3 */ 0, { CS_AC_READ, 0 } }, { /* AArch64_DECB_XPiI, AArch64_INS_DECB: decb */ 0, { 0 } }, { /* AArch64_DECD_XPiI, AArch64_INS_DECD: decd */ 0, { 0 } }, { /* AArch64_DECD_ZPiI, AArch64_INS_DECD: decd */ 0, { 0 } }, { /* AArch64_DECH_XPiI, AArch64_INS_DECH: dech */ 0, { 0 } }, { /* AArch64_DECH_ZPiI, AArch64_INS_DECH: dech */ 0, { 0 } }, { /* AArch64_DECP_XP_B, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECP_XP_D, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECP_XP_H, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECP_XP_S, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECP_ZP_D, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECP_ZP_H, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECP_ZP_S, AArch64_INS_DECP: decp */ 0, { 0 } }, { /* AArch64_DECW_XPiI, AArch64_INS_DECW: decw */ 0, { 0 } }, { /* AArch64_DECW_ZPiI, AArch64_INS_DECW: decw */ 0, { 0 } }, { /* AArch64_DMB, AArch64_INS_DMB: dmb */ 0, { CS_AC_READ, 0 } }, { /* AArch64_DRPS, AArch64_INS_DRPS: drps */ 0, { 0 } }, { /* AArch64_DSB, AArch64_INS_DSB: dsb */ 0, { CS_AC_READ, 0 } }, { /* AArch64_DUPM_ZI, AArch64_INS_DUPM: dupm */ 0, { 0 } }, { /* AArch64_DUP_ZI_B, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZI_D, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZI_H, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZI_S, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZR_B, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZR_D, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZR_H, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZR_S, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZZI_B, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZZI_D, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZZI_H, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZZI_Q, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUP_ZZI_S, AArch64_INS_DUP: dup */ 0, { 0 } }, { /* AArch64_DUPv16i8gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv16i8lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_DUPv2i32gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv2i32lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_DUPv2i64gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv2i64lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_DUPv4i16gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv4i16lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_DUPv4i32gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv4i32lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_DUPv8i16gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv8i16lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_DUPv8i8gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_DUPv8i8lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EONWrs, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EONXrs, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EOR3, AArch64_INS_EOR3: eor3 */ 0, { 0 } }, { /* AArch64_EORS_PPzPP, AArch64_INS_EORS: eors */ 0, { 0 } }, { /* AArch64_EORV_VPZ_B, AArch64_INS_EORV: eorv */ 0, { 0 } }, { /* AArch64_EORV_VPZ_D, AArch64_INS_EORV: eorv */ 0, { 0 } }, { /* AArch64_EORV_VPZ_H, AArch64_INS_EORV: eorv */ 0, { 0 } }, { /* AArch64_EORV_VPZ_S, AArch64_INS_EORV: eorv */ 0, { 0 } }, { /* AArch64_EORWri, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EORWrs, AArch64_INS_EOR: eor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EORXri, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EORXrs, AArch64_INS_EOR: eor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EOR_PPzPP, AArch64_INS_EOR: eor */ 0, { 0 } }, { /* AArch64_EOR_ZI, AArch64_INS_EON: eon */ 0, { 0 } }, { /* AArch64_EOR_ZPmZ_B, AArch64_INS_EOR: eor */ 0, { 0 } }, { /* AArch64_EOR_ZPmZ_D, AArch64_INS_EOR: eor */ 0, { 0 } }, { /* AArch64_EOR_ZPmZ_H, AArch64_INS_EOR: eor */ 0, { 0 } }, { /* AArch64_EOR_ZPmZ_S, AArch64_INS_EOR: eor */ 0, { 0 } }, { /* AArch64_EOR_ZZZ, AArch64_INS_EOR: eor */ 0, { 0 } }, { /* AArch64_EORv16i8, AArch64_INS_EOR: eor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_EORv8i8, AArch64_INS_EOR: eor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ERET, AArch64_INS_ERET: eret */ 0, { 0 } }, { /* AArch64_ERETAA, AArch64_INS_ERETAA: eretaa */ 0, { 0 } }, { /* AArch64_ERETAB, AArch64_INS_ERETAB: eretab */ 0, { 0 } }, { /* AArch64_EXTRWrri, AArch64_INS_EXTR: extr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_EXTRXrri, AArch64_INS_EXTR: extr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_EXT_ZZI, AArch64_INS_EXT: ext */ 0, { 0 } }, { /* AArch64_EXTv16i8, AArch64_INS_EXT: ext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_EXTv8i8, AArch64_INS_EXT: ext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FABD16, AArch64_INS_FABD: fabd */ 0, { 0 } }, { /* AArch64_FABD32, AArch64_INS_FABD: fabd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FABD64, AArch64_INS_FABD: fabd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FABD_ZPmZ_D, AArch64_INS_FABD: fabd */ 0, { 0 } }, { /* AArch64_FABD_ZPmZ_H, AArch64_INS_FABD: fabd */ 0, { 0 } }, { /* AArch64_FABD_ZPmZ_S, AArch64_INS_FABD: fabd */ 0, { 0 } }, { /* AArch64_FABDv2f32, AArch64_INS_FABD: fabd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FABDv2f64, AArch64_INS_FABD: fabd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FABDv4f16, AArch64_INS_FABD: fabd */ 0, { 0 } }, { /* AArch64_FABDv4f32, AArch64_INS_FABD: fabd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FABDv8f16, AArch64_INS_FABD: fabd */ 0, { 0 } }, { /* AArch64_FABSDr, AArch64_INS_FABS: fabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FABSHr, AArch64_INS_FABS: fabs */ 0, { 0 } }, { /* AArch64_FABSSr, AArch64_INS_FABS: fabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FABS_ZPmZ_D, AArch64_INS_FABS: fabs */ 0, { 0 } }, { /* AArch64_FABS_ZPmZ_H, AArch64_INS_FABS: fabs */ 0, { 0 } }, { /* AArch64_FABS_ZPmZ_S, AArch64_INS_FABS: fabs */ 0, { 0 } }, { /* AArch64_FABSv2f32, AArch64_INS_FABS: fabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FABSv2f64, AArch64_INS_FABS: fabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FABSv4f16, AArch64_INS_FABS: fabs */ 0, { 0 } }, { /* AArch64_FABSv4f32, AArch64_INS_FABS: fabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FABSv8f16, AArch64_INS_FABS: fabs */ 0, { 0 } }, { /* AArch64_FACGE16, AArch64_INS_FACGE: facge */ 0, { 0 } }, { /* AArch64_FACGE32, AArch64_INS_FACGE: facge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGE64, AArch64_INS_FACGE: facge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGE_PPzZZ_D, AArch64_INS_FACGE: facge */ 0, { 0 } }, { /* AArch64_FACGE_PPzZZ_H, AArch64_INS_FACGE: facge */ 0, { 0 } }, { /* AArch64_FACGE_PPzZZ_S, AArch64_INS_FACGE: facge */ 0, { 0 } }, { /* AArch64_FACGEv2f32, AArch64_INS_FACGE: facge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGEv2f64, AArch64_INS_FACGE: facge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGEv4f16, AArch64_INS_FACGE: facge */ 0, { 0 } }, { /* AArch64_FACGEv4f32, AArch64_INS_FACGE: facge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGEv8f16, AArch64_INS_FACGE: facge */ 0, { 0 } }, { /* AArch64_FACGT16, AArch64_INS_FACGT: facgt */ 0, { 0 } }, { /* AArch64_FACGT32, AArch64_INS_FACGT: facgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGT64, AArch64_INS_FACGT: facgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGT_PPzZZ_D, AArch64_INS_FACGT: facgt */ 0, { 0 } }, { /* AArch64_FACGT_PPzZZ_H, AArch64_INS_FACGT: facgt */ 0, { 0 } }, { /* AArch64_FACGT_PPzZZ_S, AArch64_INS_FACGT: facgt */ 0, { 0 } }, { /* AArch64_FACGTv2f32, AArch64_INS_FACGT: facgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGTv2f64, AArch64_INS_FACGT: facgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGTv4f16, AArch64_INS_FACGT: facgt */ 0, { 0 } }, { /* AArch64_FACGTv4f32, AArch64_INS_FACGT: facgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FACGTv8f16, AArch64_INS_FACGT: facgt */ 0, { 0 } }, { /* AArch64_FADDA_VPZ_D, AArch64_INS_FADDA: fadda */ 0, { 0 } }, { /* AArch64_FADDA_VPZ_H, AArch64_INS_FADDA: fadda */ 0, { 0 } }, { /* AArch64_FADDA_VPZ_S, AArch64_INS_FADDA: fadda */ 0, { 0 } }, { /* AArch64_FADDDrr, AArch64_INS_FADD: fadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDHrr, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADDPv2f32, AArch64_INS_FADDP: faddp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDPv2f64, AArch64_INS_FADDP: faddp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDPv2i16p, AArch64_INS_FADDP: faddp */ 0, { 0 } }, { /* AArch64_FADDPv2i32p, AArch64_INS_FADDP: faddp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FADDPv2i64p, AArch64_INS_FADDP: faddp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FADDPv4f16, AArch64_INS_FADDP: faddp */ 0, { 0 } }, { /* AArch64_FADDPv4f32, AArch64_INS_FADDP: faddp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDPv8f16, AArch64_INS_FADDP: faddp */ 0, { 0 } }, { /* AArch64_FADDSrr, AArch64_INS_FADD: fadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDV_VPZ_D, AArch64_INS_FADDV: faddv */ 0, { 0 } }, { /* AArch64_FADDV_VPZ_H, AArch64_INS_FADDV: faddv */ 0, { 0 } }, { /* AArch64_FADDV_VPZ_S, AArch64_INS_FADDV: faddv */ 0, { 0 } }, { /* AArch64_FADD_ZPmI_D, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZPmI_H, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZPmI_S, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZPmZ_D, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZPmZ_H, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZPmZ_S, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZZZ_D, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZZZ_H, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADD_ZZZ_S, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADDv2f32, AArch64_INS_FADD: fadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDv2f64, AArch64_INS_FADD: fadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDv4f16, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FADDv4f32, AArch64_INS_FADD: fadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FADDv8f16, AArch64_INS_FADD: fadd */ 0, { 0 } }, { /* AArch64_FCADD_ZPmZ_D, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADD_ZPmZ_H, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADD_ZPmZ_S, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADDv2f32, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADDv2f64, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADDv4f16, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADDv4f32, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCADDv8f16, AArch64_INS_FCADD: fcadd */ 0, { 0 } }, { /* AArch64_FCCMPDrr, AArch64_INS_FCCMP: fccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, { /* AArch64_FCCMPEDrr, AArch64_INS_FCCMPE: fccmpe */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, { /* AArch64_FCCMPEHrr, AArch64_INS_FCCMPE: fccmpe */ 0, { 0 } }, { /* AArch64_FCCMPESrr, AArch64_INS_FCCMPE: fccmpe */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, { /* AArch64_FCCMPHrr, AArch64_INS_FCCMP: fccmp */ 0, { 0 } }, { /* AArch64_FCCMPSrr, AArch64_INS_FCCMP: fccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, { /* AArch64_FCMEQ16, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQ32, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQ64, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQ_PPzZ0_D, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQ_PPzZ0_H, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQ_PPzZ0_S, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQ_PPzZZ_D, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQ_PPzZZ_H, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQ_PPzZZ_S, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQv1i16rz, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQv1i32rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv1i64rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv2f32, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv2f64, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv2i32rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv2i64rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv4f16, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQv4f32, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv4i16rz, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQv4i32rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMEQv8f16, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMEQv8i16rz, AArch64_INS_FCMEQ: fcmeq */ 0, { 0 } }, { /* AArch64_FCMGE16, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGE32, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGE64, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGE_PPzZ0_D, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGE_PPzZ0_H, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGE_PPzZ0_S, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGE_PPzZZ_D, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGE_PPzZZ_H, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGE_PPzZZ_S, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGEv1i16rz, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGEv1i32rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv1i64rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv2f32, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv2f64, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv2i32rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv2i64rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv4f16, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGEv4f32, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv4i16rz, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGEv4i32rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGEv8f16, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGEv8i16rz, AArch64_INS_FCMGE: fcmge */ 0, { 0 } }, { /* AArch64_FCMGT16, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGT32, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGT64, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGT_PPzZ0_D, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGT_PPzZ0_H, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGT_PPzZ0_S, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGT_PPzZZ_D, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGT_PPzZZ_H, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGT_PPzZZ_S, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGTv1i16rz, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGTv1i32rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv1i64rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv2f32, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv2f64, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv2i32rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv2i64rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv4f16, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGTv4f32, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv4i16rz, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGTv4i32rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMGTv8f16, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMGTv8i16rz, AArch64_INS_FCMGT: fcmgt */ 0, { 0 } }, { /* AArch64_FCMLA_ZPmZZ_D, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLA_ZPmZZ_H, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLA_ZPmZZ_S, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLA_ZZZI_H, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLA_ZZZI_S, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv2f32, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv2f64, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv4f16, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv4f16_indexed, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv4f32, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv4f32_indexed, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv8f16, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLAv8f16_indexed, AArch64_INS_FCMLA: fcmla */ 0, { 0 } }, { /* AArch64_FCMLE_PPzZ0_D, AArch64_INS_FCMLE: fcmle */ 0, { 0 } }, { /* AArch64_FCMLE_PPzZ0_H, AArch64_INS_FCMLE: fcmle */ 0, { 0 } }, { /* AArch64_FCMLE_PPzZ0_S, AArch64_INS_FCMLE: fcmle */ 0, { 0 } }, { /* AArch64_FCMLEv1i16rz, AArch64_INS_FCMLE: fcmle */ 0, { 0 } }, { /* AArch64_FCMLEv1i32rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLEv1i64rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLEv2i32rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLEv2i64rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLEv4i16rz, AArch64_INS_FCMLE: fcmle */ 0, { 0 } }, { /* AArch64_FCMLEv4i32rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLEv8i16rz, AArch64_INS_FCMLE: fcmle */ 0, { 0 } }, { /* AArch64_FCMLT_PPzZ0_D, AArch64_INS_FCMLT: fcmlt */ 0, { 0 } }, { /* AArch64_FCMLT_PPzZ0_H, AArch64_INS_FCMLT: fcmlt */ 0, { 0 } }, { /* AArch64_FCMLT_PPzZ0_S, AArch64_INS_FCMLT: fcmlt */ 0, { 0 } }, { /* AArch64_FCMLTv1i16rz, AArch64_INS_FCMLT: fcmlt */ 0, { 0 } }, { /* AArch64_FCMLTv1i32rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLTv1i64rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLTv2i32rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLTv2i64rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLTv4i16rz, AArch64_INS_FCMLT: fcmlt */ 0, { 0 } }, { /* AArch64_FCMLTv4i32rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMLTv8i16rz, AArch64_INS_FCMLT: fcmlt */ 0, { 0 } }, { /* AArch64_FCMNE_PPzZ0_D, AArch64_INS_FCMNE: fcmne */ 0, { 0 } }, { /* AArch64_FCMNE_PPzZ0_H, AArch64_INS_FCMNE: fcmne */ 0, { 0 } }, { /* AArch64_FCMNE_PPzZ0_S, AArch64_INS_FCMNE: fcmne */ 0, { 0 } }, { /* AArch64_FCMNE_PPzZZ_D, AArch64_INS_FCMNE: fcmne */ 0, { 0 } }, { /* AArch64_FCMNE_PPzZZ_H, AArch64_INS_FCMNE: fcmne */ 0, { 0 } }, { /* AArch64_FCMNE_PPzZZ_S, AArch64_INS_FCMNE: fcmne */ 0, { 0 } }, { /* AArch64_FCMPDri, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPDrr, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPEDri, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPEDrr, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPEHri, AArch64_INS_FCMPE: fcmpe */ 0, { 0 } }, { /* AArch64_FCMPEHrr, AArch64_INS_FCMPE: fcmpe */ 0, { 0 } }, { /* AArch64_FCMPESri, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPESrr, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPHri, AArch64_INS_FCMP: fcmp */ 0, { 0 } }, { /* AArch64_FCMPHrr, AArch64_INS_FCMP: fcmp */ 0, { 0 } }, { /* AArch64_FCMPSri, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMPSrr, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCMUO_PPzZZ_D, AArch64_INS_FCMUO: fcmuo */ 0, { 0 } }, { /* AArch64_FCMUO_PPzZZ_H, AArch64_INS_FCMUO: fcmuo */ 0, { 0 } }, { /* AArch64_FCMUO_PPzZZ_S, AArch64_INS_FCMUO: fcmuo */ 0, { 0 } }, { /* AArch64_FCPY_ZPmI_D, AArch64_INS_FCPY: fcpy */ 0, { 0 } }, { /* AArch64_FCPY_ZPmI_H, AArch64_INS_FCPY: fcpy */ 0, { 0 } }, { /* AArch64_FCPY_ZPmI_S, AArch64_INS_FCPY: fcpy */ 0, { 0 } }, { /* AArch64_FCSELDrrr, AArch64_INS_FCSEL: fcsel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FCSELHrrr, AArch64_INS_FCSEL: fcsel */ 0, { 0 } }, { /* AArch64_FCSELSrrr, AArch64_INS_FCSEL: fcsel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FCVTASUWDr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASUWHr, AArch64_INS_FCVTAS: fcvtas */ 0, { 0 } }, { /* AArch64_FCVTASUWSr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASUXDr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASUXHr, AArch64_INS_FCVTAS: fcvtas */ 0, { 0 } }, { /* AArch64_FCVTASUXSr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASv1f16, AArch64_INS_FCVTAS: fcvtas */ 0, { 0 } }, { /* AArch64_FCVTASv1i32, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASv1i64, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASv2f32, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASv2f64, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASv4f16, AArch64_INS_FCVTAS: fcvtas */ 0, { 0 } }, { /* AArch64_FCVTASv4f32, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTASv8f16, AArch64_INS_FCVTAS: fcvtas */ 0, { 0 } }, { /* AArch64_FCVTAUUWDr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUUWHr, AArch64_INS_FCVTAU: fcvtau */ 0, { 0 } }, { /* AArch64_FCVTAUUWSr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUUXDr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUUXHr, AArch64_INS_FCVTAU: fcvtau */ 0, { 0 } }, { /* AArch64_FCVTAUUXSr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUv1f16, AArch64_INS_FCVTAU: fcvtau */ 0, { 0 } }, { /* AArch64_FCVTAUv1i32, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUv1i64, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUv2f32, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUv2f64, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUv4f16, AArch64_INS_FCVTAU: fcvtau */ 0, { 0 } }, { /* AArch64_FCVTAUv4f32, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTAUv8f16, AArch64_INS_FCVTAU: fcvtau */ 0, { 0 } }, { /* AArch64_FCVTDHr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTDSr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTHDr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTHSr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTLv2i32, AArch64_INS_FCVTL: fcvtl */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTLv4i16, AArch64_INS_FCVTL: fcvtl */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTLv4i32, AArch64_INS_FCVTL2: fcvtl2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTLv8i16, AArch64_INS_FCVTL2: fcvtl2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSUWDr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSUWHr, AArch64_INS_FCVTMS: fcvtms */ 0, { 0 } }, { /* AArch64_FCVTMSUWSr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSUXDr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSUXHr, AArch64_INS_FCVTMS: fcvtms */ 0, { 0 } }, { /* AArch64_FCVTMSUXSr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSv1f16, AArch64_INS_FCVTMS: fcvtms */ 0, { 0 } }, { /* AArch64_FCVTMSv1i32, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSv1i64, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSv2f32, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSv2f64, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSv4f16, AArch64_INS_FCVTMS: fcvtms */ 0, { 0 } }, { /* AArch64_FCVTMSv4f32, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMSv8f16, AArch64_INS_FCVTMS: fcvtms */ 0, { 0 } }, { /* AArch64_FCVTMUUWDr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUUWHr, AArch64_INS_FCVTMU: fcvtmu */ 0, { 0 } }, { /* AArch64_FCVTMUUWSr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUUXDr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUUXHr, AArch64_INS_FCVTMU: fcvtmu */ 0, { 0 } }, { /* AArch64_FCVTMUUXSr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUv1f16, AArch64_INS_FCVTMU: fcvtmu */ 0, { 0 } }, { /* AArch64_FCVTMUv1i32, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUv1i64, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUv2f32, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUv2f64, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUv4f16, AArch64_INS_FCVTMU: fcvtmu */ 0, { 0 } }, { /* AArch64_FCVTMUv4f32, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTMUv8f16, AArch64_INS_FCVTMU: fcvtmu */ 0, { 0 } }, { /* AArch64_FCVTNSUWDr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSUWHr, AArch64_INS_FCVTNS: fcvtns */ 0, { 0 } }, { /* AArch64_FCVTNSUWSr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSUXDr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSUXHr, AArch64_INS_FCVTNS: fcvtns */ 0, { 0 } }, { /* AArch64_FCVTNSUXSr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSv1f16, AArch64_INS_FCVTNS: fcvtns */ 0, { 0 } }, { /* AArch64_FCVTNSv1i32, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSv1i64, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSv2f32, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSv2f64, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSv4f16, AArch64_INS_FCVTNS: fcvtns */ 0, { 0 } }, { /* AArch64_FCVTNSv4f32, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNSv8f16, AArch64_INS_FCVTNS: fcvtns */ 0, { 0 } }, { /* AArch64_FCVTNUUWDr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUUWHr, AArch64_INS_FCVTNU: fcvtnu */ 0, { 0 } }, { /* AArch64_FCVTNUUWSr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUUXDr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUUXHr, AArch64_INS_FCVTNU: fcvtnu */ 0, { 0 } }, { /* AArch64_FCVTNUUXSr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUv1f16, AArch64_INS_FCVTNU: fcvtnu */ 0, { 0 } }, { /* AArch64_FCVTNUv1i32, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUv1i64, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUv2f32, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUv2f64, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUv4f16, AArch64_INS_FCVTNU: fcvtnu */ 0, { 0 } }, { /* AArch64_FCVTNUv4f32, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNUv8f16, AArch64_INS_FCVTNU: fcvtnu */ 0, { 0 } }, { /* AArch64_FCVTNv2i32, AArch64_INS_FCVTN: fcvtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNv4i16, AArch64_INS_FCVTN: fcvtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNv4i32, AArch64_INS_FCVTN2: fcvtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTNv8i16, AArch64_INS_FCVTN2: fcvtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSUWDr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSUWHr, AArch64_INS_FCVTPS: fcvtps */ 0, { 0 } }, { /* AArch64_FCVTPSUWSr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSUXDr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSUXHr, AArch64_INS_FCVTPS: fcvtps */ 0, { 0 } }, { /* AArch64_FCVTPSUXSr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSv1f16, AArch64_INS_FCVTPS: fcvtps */ 0, { 0 } }, { /* AArch64_FCVTPSv1i32, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSv1i64, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSv2f32, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSv2f64, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSv4f16, AArch64_INS_FCVTPS: fcvtps */ 0, { 0 } }, { /* AArch64_FCVTPSv4f32, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPSv8f16, AArch64_INS_FCVTPS: fcvtps */ 0, { 0 } }, { /* AArch64_FCVTPUUWDr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUUWHr, AArch64_INS_FCVTPU: fcvtpu */ 0, { 0 } }, { /* AArch64_FCVTPUUWSr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUUXDr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUUXHr, AArch64_INS_FCVTPU: fcvtpu */ 0, { 0 } }, { /* AArch64_FCVTPUUXSr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUv1f16, AArch64_INS_FCVTPU: fcvtpu */ 0, { 0 } }, { /* AArch64_FCVTPUv1i32, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUv1i64, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUv2f32, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUv2f64, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUv4f16, AArch64_INS_FCVTPU: fcvtpu */ 0, { 0 } }, { /* AArch64_FCVTPUv4f32, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTPUv8f16, AArch64_INS_FCVTPU: fcvtpu */ 0, { 0 } }, { /* AArch64_FCVTSDr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTSHr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTXNv1i64, AArch64_INS_FCVTXN: fcvtxn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTXNv2f32, AArch64_INS_FCVTXN: fcvtxn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTXNv4f32, AArch64_INS_FCVTXN2: fcvtxn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSSWDri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSSWHri, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSSWSri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSSXDri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSSXHri, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSSXSri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSUWDr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSUWHr, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSUWSr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSUXDr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSUXHr, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSUXSr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZS_ZPmZ_DtoD, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZS_ZPmZ_DtoS, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZS_ZPmZ_HtoD, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZS_ZPmZ_HtoH, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZS_ZPmZ_HtoS, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZS_ZPmZ_StoD, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZS_ZPmZ_StoS, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSd, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSh, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSs, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv1f16, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSv1i32, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv1i64, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv2f32, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv2f64, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv2i32_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv2i64_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv4f16, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSv4f32, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv4i16_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSv4i32_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZSv8f16, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZSv8i16_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { 0 } }, { /* AArch64_FCVTZUSWDri, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUSWHri, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUSWSri, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUSXDri, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUSXHri, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUSXSri, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUUWDr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUUWHr, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUUWSr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUUXDr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUUXHr, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUUXSr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZU_ZPmZ_DtoD, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZU_ZPmZ_DtoS, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZU_ZPmZ_HtoD, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZU_ZPmZ_HtoH, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZU_ZPmZ_HtoS, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZU_ZPmZ_StoD, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZU_ZPmZ_StoS, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUd, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUh, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUs, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv1f16, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUv1i32, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv1i64, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv2f32, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv2f64, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv2i32_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv2i64_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv4f16, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUv4f32, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv4i16_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUv4i32_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FCVTZUv8f16, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVTZUv8i16_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { 0 } }, { /* AArch64_FCVT_ZPmZ_DtoH, AArch64_INS_FCVT: fcvt */ 0, { 0 } }, { /* AArch64_FCVT_ZPmZ_DtoS, AArch64_INS_FCVT: fcvt */ 0, { 0 } }, { /* AArch64_FCVT_ZPmZ_HtoD, AArch64_INS_FCVT: fcvt */ 0, { 0 } }, { /* AArch64_FCVT_ZPmZ_HtoS, AArch64_INS_FCVT: fcvt */ 0, { 0 } }, { /* AArch64_FCVT_ZPmZ_StoD, AArch64_INS_FCVT: fcvt */ 0, { 0 } }, { /* AArch64_FCVT_ZPmZ_StoH, AArch64_INS_FCVT: fcvt */ 0, { 0 } }, { /* AArch64_FDIVDrr, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FDIVHrr, AArch64_INS_FDIV: fdiv */ 0, { 0 } }, { /* AArch64_FDIVR_ZPmZ_D, AArch64_INS_FDIVR: fdivr */ 0, { 0 } }, { /* AArch64_FDIVR_ZPmZ_H, AArch64_INS_FDIVR: fdivr */ 0, { 0 } }, { /* AArch64_FDIVR_ZPmZ_S, AArch64_INS_FDIVR: fdivr */ 0, { 0 } }, { /* AArch64_FDIVSrr, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FDIV_ZPmZ_D, AArch64_INS_FDIV: fdiv */ 0, { 0 } }, { /* AArch64_FDIV_ZPmZ_H, AArch64_INS_FDIV: fdiv */ 0, { 0 } }, { /* AArch64_FDIV_ZPmZ_S, AArch64_INS_FDIV: fdiv */ 0, { 0 } }, { /* AArch64_FDIVv2f32, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FDIVv2f64, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FDIVv4f16, AArch64_INS_FDIV: fdiv */ 0, { 0 } }, { /* AArch64_FDIVv4f32, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FDIVv8f16, AArch64_INS_FDIV: fdiv */ 0, { 0 } }, { /* AArch64_FDUP_ZI_D, AArch64_INS_FDUP: fdup */ 0, { 0 } }, { /* AArch64_FDUP_ZI_H, AArch64_INS_FDUP: fdup */ 0, { 0 } }, { /* AArch64_FDUP_ZI_S, AArch64_INS_FDUP: fdup */ 0, { 0 } }, { /* AArch64_FEXPA_ZZ_D, AArch64_INS_FEXPA: fexpa */ 0, { 0 } }, { /* AArch64_FEXPA_ZZ_H, AArch64_INS_FEXPA: fexpa */ 0, { 0 } }, { /* AArch64_FEXPA_ZZ_S, AArch64_INS_FEXPA: fexpa */ 0, { 0 } }, { /* AArch64_FJCVTZS, AArch64_INS_FJCVTZS: fjcvtzs */ 0, { 0 } }, { /* AArch64_FMADDDrrr, AArch64_INS_FMADD: fmadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMADDHrrr, AArch64_INS_FMADD: fmadd */ 0, { 0 } }, { /* AArch64_FMADDSrrr, AArch64_INS_FMADD: fmadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMAD_ZPmZZ_D, AArch64_INS_FMAD: fmad */ 0, { 0 } }, { /* AArch64_FMAD_ZPmZZ_H, AArch64_INS_FMAD: fmad */ 0, { 0 } }, { /* AArch64_FMAD_ZPmZZ_S, AArch64_INS_FMAD: fmad */ 0, { 0 } }, { /* AArch64_FMAXDrr, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXHrr, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAXNMDrr, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMHrr, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNMPv2f32, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMPv2f64, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMPv2i16p, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { 0 } }, { /* AArch64_FMAXNMPv2i32p, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMPv2i64p, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMPv4f16, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { 0 } }, { /* AArch64_FMAXNMPv4f32, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMPv8f16, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { 0 } }, { /* AArch64_FMAXNMSrr, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMV_VPZ_D, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { 0 } }, { /* AArch64_FMAXNMV_VPZ_H, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { 0 } }, { /* AArch64_FMAXNMV_VPZ_S, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { 0 } }, { /* AArch64_FMAXNMVv4i16v, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { 0 } }, { /* AArch64_FMAXNMVv4i32v, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMVv8i16v, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { 0 } }, { /* AArch64_FMAXNM_ZPmI_D, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNM_ZPmI_H, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNM_ZPmI_S, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNM_ZPmZ_D, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNM_ZPmZ_H, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNM_ZPmZ_S, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNMv2f32, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMv2f64, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMv4f16, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXNMv4f32, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXNMv8f16, AArch64_INS_FMAXNM: fmaxnm */ 0, { 0 } }, { /* AArch64_FMAXPv2f32, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXPv2f64, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXPv2i16p, AArch64_INS_FMAXP: fmaxp */ 0, { 0 } }, { /* AArch64_FMAXPv2i32p, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMAXPv2i64p, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMAXPv4f16, AArch64_INS_FMAXP: fmaxp */ 0, { 0 } }, { /* AArch64_FMAXPv4f32, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXPv8f16, AArch64_INS_FMAXP: fmaxp */ 0, { 0 } }, { /* AArch64_FMAXSrr, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXV_VPZ_D, AArch64_INS_FMAXV: fmaxv */ 0, { 0 } }, { /* AArch64_FMAXV_VPZ_H, AArch64_INS_FMAXV: fmaxv */ 0, { 0 } }, { /* AArch64_FMAXV_VPZ_S, AArch64_INS_FMAXV: fmaxv */ 0, { 0 } }, { /* AArch64_FMAXVv4i16v, AArch64_INS_FMAXV: fmaxv */ 0, { 0 } }, { /* AArch64_FMAXVv4i32v, AArch64_INS_FMAXV: fmaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMAXVv8i16v, AArch64_INS_FMAXV: fmaxv */ 0, { 0 } }, { /* AArch64_FMAX_ZPmI_D, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAX_ZPmI_H, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAX_ZPmI_S, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAX_ZPmZ_D, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAX_ZPmZ_H, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAX_ZPmZ_S, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAXv2f32, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXv2f64, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXv4f16, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMAXv4f32, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMAXv8f16, AArch64_INS_FMAX: fmax */ 0, { 0 } }, { /* AArch64_FMINDrr, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINHrr, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMINNMDrr, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMHrr, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNMPv2f32, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMPv2f64, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMPv2i16p, AArch64_INS_FMINNMP: fminnmp */ 0, { 0 } }, { /* AArch64_FMINNMPv2i32p, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMINNMPv2i64p, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMINNMPv4f16, AArch64_INS_FMINNMP: fminnmp */ 0, { 0 } }, { /* AArch64_FMINNMPv4f32, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMPv8f16, AArch64_INS_FMINNMP: fminnmp */ 0, { 0 } }, { /* AArch64_FMINNMSrr, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMV_VPZ_D, AArch64_INS_FMINNMV: fminnmv */ 0, { 0 } }, { /* AArch64_FMINNMV_VPZ_H, AArch64_INS_FMINNMV: fminnmv */ 0, { 0 } }, { /* AArch64_FMINNMV_VPZ_S, AArch64_INS_FMINNMV: fminnmv */ 0, { 0 } }, { /* AArch64_FMINNMVv4i16v, AArch64_INS_FMINNMV: fminnmv */ 0, { 0 } }, { /* AArch64_FMINNMVv4i32v, AArch64_INS_FMINNMV: fminnmv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMINNMVv8i16v, AArch64_INS_FMINNMV: fminnmv */ 0, { 0 } }, { /* AArch64_FMINNM_ZPmI_D, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNM_ZPmI_H, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNM_ZPmI_S, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNM_ZPmZ_D, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNM_ZPmZ_H, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNM_ZPmZ_S, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNMv2f32, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMv2f64, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMv4f16, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINNMv4f32, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINNMv8f16, AArch64_INS_FMINNM: fminnm */ 0, { 0 } }, { /* AArch64_FMINPv2f32, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINPv2f64, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINPv2i16p, AArch64_INS_FMINP: fminp */ 0, { 0 } }, { /* AArch64_FMINPv2i32p, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMINPv2i64p, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMINPv4f16, AArch64_INS_FMINP: fminp */ 0, { 0 } }, { /* AArch64_FMINPv4f32, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINPv8f16, AArch64_INS_FMINP: fminp */ 0, { 0 } }, { /* AArch64_FMINSrr, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINV_VPZ_D, AArch64_INS_FMINV: fminv */ 0, { 0 } }, { /* AArch64_FMINV_VPZ_H, AArch64_INS_FMINV: fminv */ 0, { 0 } }, { /* AArch64_FMINV_VPZ_S, AArch64_INS_FMINV: fminv */ 0, { 0 } }, { /* AArch64_FMINVv4i16v, AArch64_INS_FMINV: fminv */ 0, { 0 } }, { /* AArch64_FMINVv4i32v, AArch64_INS_FMINV: fminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMINVv8i16v, AArch64_INS_FMINV: fminv */ 0, { 0 } }, { /* AArch64_FMIN_ZPmI_D, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMIN_ZPmI_H, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMIN_ZPmI_S, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMIN_ZPmZ_D, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMIN_ZPmZ_H, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMIN_ZPmZ_S, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMINv2f32, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINv2f64, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINv4f16, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMINv4f32, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMINv8f16, AArch64_INS_FMIN: fmin */ 0, { 0 } }, { /* AArch64_FMLA_ZPmZZ_D, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLA_ZPmZZ_H, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLA_ZPmZZ_S, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLA_ZZZI_D, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLA_ZZZI_H, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLA_ZZZI_S, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLAv1i16_indexed, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLAv1i32_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLAv1i64_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLAv2f32, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMLAv2f64, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMLAv2i32_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLAv2i64_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLAv4f16, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLAv4f32, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMLAv4i16_indexed, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLAv4i32_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLAv8f16, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLAv8i16_indexed, AArch64_INS_FMLA: fmla */ 0, { 0 } }, { /* AArch64_FMLS_ZPmZZ_D, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLS_ZPmZZ_H, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLS_ZPmZZ_S, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLS_ZZZI_D, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLS_ZZZI_H, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLS_ZZZI_S, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLSv1i16_indexed, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLSv1i32_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLSv1i64_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLSv2f32, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMLSv2f64, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMLSv2i32_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLSv2i64_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLSv4f16, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLSv4f32, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMLSv4i16_indexed, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLSv4i32_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMLSv8f16, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMLSv8i16_indexed, AArch64_INS_FMLS: fmls */ 0, { 0 } }, { /* AArch64_FMOVDXHighr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVDXr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVDi, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMOVDr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVHWr, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVHXr, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVHi, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVHr, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVSWr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVSi, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMOVSr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVWHr, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVWSr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVXDHighr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVXDr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FMOVXHr, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVv2f32_ns, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } }, { /* AArch64_FMOVv2f64_ns, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } }, { /* AArch64_FMOVv4f16_ns, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMOVv4f32_ns, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } }, { /* AArch64_FMOVv8f16_ns, AArch64_INS_FMOV: fmov */ 0, { 0 } }, { /* AArch64_FMSB_ZPmZZ_D, AArch64_INS_FMSB: fmsb */ 0, { 0 } }, { /* AArch64_FMSB_ZPmZZ_H, AArch64_INS_FMSB: fmsb */ 0, { 0 } }, { /* AArch64_FMSB_ZPmZZ_S, AArch64_INS_FMSB: fmsb */ 0, { 0 } }, { /* AArch64_FMSUBDrrr, AArch64_INS_FMSUB: fmsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMSUBHrrr, AArch64_INS_FMSUB: fmsub */ 0, { 0 } }, { /* AArch64_FMSUBSrrr, AArch64_INS_FMSUB: fmsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULDrr, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULHrr, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMULSrr, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULX16, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULX32, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULX64, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULX_ZPmZ_D, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULX_ZPmZ_H, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULX_ZPmZ_S, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULXv1i16_indexed, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULXv1i32_indexed, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULXv1i64_indexed, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULXv2f32, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULXv2f64, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULXv2i32_indexed, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULXv2i64_indexed, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULXv4f16, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULXv4f32, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULXv4i16_indexed, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULXv4i32_indexed, AArch64_INS_FMULX: fmulx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULXv8f16, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMULXv8i16_indexed, AArch64_INS_FMULX: fmulx */ 0, { 0 } }, { /* AArch64_FMUL_ZPmI_D, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZPmI_H, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZPmI_S, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZPmZ_D, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZPmZ_H, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZPmZ_S, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZZZI_D, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZZZI_H, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZZZI_S, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZZZ_D, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZZZ_H, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMUL_ZZZ_S, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMULv1i16_indexed, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMULv1i32_indexed, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULv1i64_indexed, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULv2f32, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULv2f64, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULv2i32_indexed, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULv2i64_indexed, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULv4f16, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMULv4f32, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FMULv4i16_indexed, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMULv4i32_indexed, AArch64_INS_FMUL: fmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FMULv8f16, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FMULv8i16_indexed, AArch64_INS_FMUL: fmul */ 0, { 0 } }, { /* AArch64_FNEGDr, AArch64_INS_FNEG: fneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FNEGHr, AArch64_INS_FNEG: fneg */ 0, { 0 } }, { /* AArch64_FNEGSr, AArch64_INS_FNEG: fneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FNEG_ZPmZ_D, AArch64_INS_FNEG: fneg */ 0, { 0 } }, { /* AArch64_FNEG_ZPmZ_H, AArch64_INS_FNEG: fneg */ 0, { 0 } }, { /* AArch64_FNEG_ZPmZ_S, AArch64_INS_FNEG: fneg */ 0, { 0 } }, { /* AArch64_FNEGv2f32, AArch64_INS_FNEG: fneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FNEGv2f64, AArch64_INS_FNEG: fneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FNEGv4f16, AArch64_INS_FNEG: fneg */ 0, { 0 } }, { /* AArch64_FNEGv4f32, AArch64_INS_FNEG: fneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FNEGv8f16, AArch64_INS_FNEG: fneg */ 0, { 0 } }, { /* AArch64_FNMADDDrrr, AArch64_INS_FNMADD: fnmadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FNMADDHrrr, AArch64_INS_FNMADD: fnmadd */ 0, { 0 } }, { /* AArch64_FNMADDSrrr, AArch64_INS_FNMADD: fnmadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FNMAD_ZPmZZ_D, AArch64_INS_FNMAD: fnmad */ 0, { 0 } }, { /* AArch64_FNMAD_ZPmZZ_H, AArch64_INS_FNMAD: fnmad */ 0, { 0 } }, { /* AArch64_FNMAD_ZPmZZ_S, AArch64_INS_FNMAD: fnmad */ 0, { 0 } }, { /* AArch64_FNMLA_ZPmZZ_D, AArch64_INS_FNMLA: fnmla */ 0, { 0 } }, { /* AArch64_FNMLA_ZPmZZ_H, AArch64_INS_FNMLA: fnmla */ 0, { 0 } }, { /* AArch64_FNMLA_ZPmZZ_S, AArch64_INS_FNMLA: fnmla */ 0, { 0 } }, { /* AArch64_FNMLS_ZPmZZ_D, AArch64_INS_FNMLS: fnmls */ 0, { 0 } }, { /* AArch64_FNMLS_ZPmZZ_H, AArch64_INS_FNMLS: fnmls */ 0, { 0 } }, { /* AArch64_FNMLS_ZPmZZ_S, AArch64_INS_FNMLS: fnmls */ 0, { 0 } }, { /* AArch64_FNMSB_ZPmZZ_D, AArch64_INS_FNMSB: fnmsb */ 0, { 0 } }, { /* AArch64_FNMSB_ZPmZZ_H, AArch64_INS_FNMSB: fnmsb */ 0, { 0 } }, { /* AArch64_FNMSB_ZPmZZ_S, AArch64_INS_FNMSB: fnmsb */ 0, { 0 } }, { /* AArch64_FNMSUBDrrr, AArch64_INS_FNMSUB: fnmsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FNMSUBHrrr, AArch64_INS_FNMSUB: fnmsub */ 0, { 0 } }, { /* AArch64_FNMSUBSrrr, AArch64_INS_FNMSUB: fnmsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_FNMULDrr, AArch64_INS_FNMUL: fnmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FNMULHrr, AArch64_INS_FNMUL: fnmul */ 0, { 0 } }, { /* AArch64_FNMULSrr, AArch64_INS_FNMUL: fnmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRECPE_ZZ_D, AArch64_INS_FRECPE: frecpe */ 0, { 0 } }, { /* AArch64_FRECPE_ZZ_H, AArch64_INS_FRECPE: frecpe */ 0, { 0 } }, { /* AArch64_FRECPE_ZZ_S, AArch64_INS_FRECPE: frecpe */ 0, { 0 } }, { /* AArch64_FRECPEv1f16, AArch64_INS_FRECPE: frecpe */ 0, { 0 } }, { /* AArch64_FRECPEv1i32, AArch64_INS_FRECPE: frecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRECPEv1i64, AArch64_INS_FRECPE: frecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRECPEv2f32, AArch64_INS_FRECPE: frecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRECPEv2f64, AArch64_INS_FRECPE: frecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRECPEv4f16, AArch64_INS_FRECPE: frecpe */ 0, { 0 } }, { /* AArch64_FRECPEv4f32, AArch64_INS_FRECPE: frecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRECPEv8f16, AArch64_INS_FRECPE: frecpe */ 0, { 0 } }, { /* AArch64_FRECPS16, AArch64_INS_FRECPS: frecps */ 0, { 0 } }, { /* AArch64_FRECPS32, AArch64_INS_FRECPS: frecps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRECPS64, AArch64_INS_FRECPS: frecps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRECPS_ZZZ_D, AArch64_INS_FRECPS: frecps */ 0, { 0 } }, { /* AArch64_FRECPS_ZZZ_H, AArch64_INS_FRECPS: frecps */ 0, { 0 } }, { /* AArch64_FRECPS_ZZZ_S, AArch64_INS_FRECPS: frecps */ 0, { 0 } }, { /* AArch64_FRECPSv2f32, AArch64_INS_FRECPS: frecps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRECPSv2f64, AArch64_INS_FRECPS: frecps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRECPSv4f16, AArch64_INS_FRECPS: frecps */ 0, { 0 } }, { /* AArch64_FRECPSv4f32, AArch64_INS_FRECPS: frecps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRECPSv8f16, AArch64_INS_FRECPS: frecps */ 0, { 0 } }, { /* AArch64_FRECPX_ZPmZ_D, AArch64_INS_FRECPX: frecpx */ 0, { 0 } }, { /* AArch64_FRECPX_ZPmZ_H, AArch64_INS_FRECPX: frecpx */ 0, { 0 } }, { /* AArch64_FRECPX_ZPmZ_S, AArch64_INS_FRECPX: frecpx */ 0, { 0 } }, { /* AArch64_FRECPXv1f16, AArch64_INS_FRECPX: frecpx */ 0, { 0 } }, { /* AArch64_FRECPXv1i32, AArch64_INS_FRECPX: frecpx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRECPXv1i64, AArch64_INS_FRECPX: frecpx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTADr, AArch64_INS_FRINTA: frinta */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTAHr, AArch64_INS_FRINTA: frinta */ 0, { 0 } }, { /* AArch64_FRINTASr, AArch64_INS_FRINTA: frinta */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTA_ZPmZ_D, AArch64_INS_FRINTA: frinta */ 0, { 0 } }, { /* AArch64_FRINTA_ZPmZ_H, AArch64_INS_FRINTA: frinta */ 0, { 0 } }, { /* AArch64_FRINTA_ZPmZ_S, AArch64_INS_FRINTA: frinta */ 0, { 0 } }, { /* AArch64_FRINTAv2f32, AArch64_INS_FRINTA: frinta */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTAv2f64, AArch64_INS_FRINTA: frinta */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTAv4f16, AArch64_INS_FRINTA: frinta */ 0, { 0 } }, { /* AArch64_FRINTAv4f32, AArch64_INS_FRINTA: frinta */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTAv8f16, AArch64_INS_FRINTA: frinta */ 0, { 0 } }, { /* AArch64_FRINTIDr, AArch64_INS_FRINTI: frinti */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTIHr, AArch64_INS_FRINTI: frinti */ 0, { 0 } }, { /* AArch64_FRINTISr, AArch64_INS_FRINTI: frinti */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTI_ZPmZ_D, AArch64_INS_FRINTI: frinti */ 0, { 0 } }, { /* AArch64_FRINTI_ZPmZ_H, AArch64_INS_FRINTI: frinti */ 0, { 0 } }, { /* AArch64_FRINTI_ZPmZ_S, AArch64_INS_FRINTI: frinti */ 0, { 0 } }, { /* AArch64_FRINTIv2f32, AArch64_INS_FRINTI: frinti */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTIv2f64, AArch64_INS_FRINTI: frinti */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTIv4f16, AArch64_INS_FRINTI: frinti */ 0, { 0 } }, { /* AArch64_FRINTIv4f32, AArch64_INS_FRINTI: frinti */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTIv8f16, AArch64_INS_FRINTI: frinti */ 0, { 0 } }, { /* AArch64_FRINTMDr, AArch64_INS_FRINTM: frintm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTMHr, AArch64_INS_FRINTM: frintm */ 0, { 0 } }, { /* AArch64_FRINTMSr, AArch64_INS_FRINTM: frintm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTM_ZPmZ_D, AArch64_INS_FRINTM: frintm */ 0, { 0 } }, { /* AArch64_FRINTM_ZPmZ_H, AArch64_INS_FRINTM: frintm */ 0, { 0 } }, { /* AArch64_FRINTM_ZPmZ_S, AArch64_INS_FRINTM: frintm */ 0, { 0 } }, { /* AArch64_FRINTMv2f32, AArch64_INS_FRINTM: frintm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTMv2f64, AArch64_INS_FRINTM: frintm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTMv4f16, AArch64_INS_FRINTM: frintm */ 0, { 0 } }, { /* AArch64_FRINTMv4f32, AArch64_INS_FRINTM: frintm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTMv8f16, AArch64_INS_FRINTM: frintm */ 0, { 0 } }, { /* AArch64_FRINTNDr, AArch64_INS_FRINTN: frintn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTNHr, AArch64_INS_FRINTN: frintn */ 0, { 0 } }, { /* AArch64_FRINTNSr, AArch64_INS_FRINTN: frintn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTN_ZPmZ_D, AArch64_INS_FRINTN: frintn */ 0, { 0 } }, { /* AArch64_FRINTN_ZPmZ_H, AArch64_INS_FRINTN: frintn */ 0, { 0 } }, { /* AArch64_FRINTN_ZPmZ_S, AArch64_INS_FRINTN: frintn */ 0, { 0 } }, { /* AArch64_FRINTNv2f32, AArch64_INS_FRINTN: frintn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTNv2f64, AArch64_INS_FRINTN: frintn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTNv4f16, AArch64_INS_FRINTN: frintn */ 0, { 0 } }, { /* AArch64_FRINTNv4f32, AArch64_INS_FRINTN: frintn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTNv8f16, AArch64_INS_FRINTN: frintn */ 0, { 0 } }, { /* AArch64_FRINTPDr, AArch64_INS_FRINTP: frintp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTPHr, AArch64_INS_FRINTP: frintp */ 0, { 0 } }, { /* AArch64_FRINTPSr, AArch64_INS_FRINTP: frintp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTP_ZPmZ_D, AArch64_INS_FRINTP: frintp */ 0, { 0 } }, { /* AArch64_FRINTP_ZPmZ_H, AArch64_INS_FRINTP: frintp */ 0, { 0 } }, { /* AArch64_FRINTP_ZPmZ_S, AArch64_INS_FRINTP: frintp */ 0, { 0 } }, { /* AArch64_FRINTPv2f32, AArch64_INS_FRINTP: frintp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTPv2f64, AArch64_INS_FRINTP: frintp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTPv4f16, AArch64_INS_FRINTP: frintp */ 0, { 0 } }, { /* AArch64_FRINTPv4f32, AArch64_INS_FRINTP: frintp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTPv8f16, AArch64_INS_FRINTP: frintp */ 0, { 0 } }, { /* AArch64_FRINTXDr, AArch64_INS_FRINTX: frintx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTXHr, AArch64_INS_FRINTX: frintx */ 0, { 0 } }, { /* AArch64_FRINTXSr, AArch64_INS_FRINTX: frintx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTX_ZPmZ_D, AArch64_INS_FRINTX: frintx */ 0, { 0 } }, { /* AArch64_FRINTX_ZPmZ_H, AArch64_INS_FRINTX: frintx */ 0, { 0 } }, { /* AArch64_FRINTX_ZPmZ_S, AArch64_INS_FRINTX: frintx */ 0, { 0 } }, { /* AArch64_FRINTXv2f32, AArch64_INS_FRINTX: frintx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTXv2f64, AArch64_INS_FRINTX: frintx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTXv4f16, AArch64_INS_FRINTX: frintx */ 0, { 0 } }, { /* AArch64_FRINTXv4f32, AArch64_INS_FRINTX: frintx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTXv8f16, AArch64_INS_FRINTX: frintx */ 0, { 0 } }, { /* AArch64_FRINTZDr, AArch64_INS_FRINTZ: frintz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTZHr, AArch64_INS_FRINTZ: frintz */ 0, { 0 } }, { /* AArch64_FRINTZSr, AArch64_INS_FRINTZ: frintz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTZ_ZPmZ_D, AArch64_INS_FRINTZ: frintz */ 0, { 0 } }, { /* AArch64_FRINTZ_ZPmZ_H, AArch64_INS_FRINTZ: frintz */ 0, { 0 } }, { /* AArch64_FRINTZ_ZPmZ_S, AArch64_INS_FRINTZ: frintz */ 0, { 0 } }, { /* AArch64_FRINTZv2f32, AArch64_INS_FRINTZ: frintz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTZv2f64, AArch64_INS_FRINTZ: frintz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTZv4f16, AArch64_INS_FRINTZ: frintz */ 0, { 0 } }, { /* AArch64_FRINTZv4f32, AArch64_INS_FRINTZ: frintz */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRINTZv8f16, AArch64_INS_FRINTZ: frintz */ 0, { 0 } }, { /* AArch64_FRSQRTE_ZZ_D, AArch64_INS_FRSQRTE: frsqrte */ 0, { 0 } }, { /* AArch64_FRSQRTE_ZZ_H, AArch64_INS_FRSQRTE: frsqrte */ 0, { 0 } }, { /* AArch64_FRSQRTE_ZZ_S, AArch64_INS_FRSQRTE: frsqrte */ 0, { 0 } }, { /* AArch64_FRSQRTEv1f16, AArch64_INS_FRSQRTE: frsqrte */ 0, { 0 } }, { /* AArch64_FRSQRTEv1i32, AArch64_INS_FRSQRTE: frsqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTEv1i64, AArch64_INS_FRSQRTE: frsqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTEv2f32, AArch64_INS_FRSQRTE: frsqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTEv2f64, AArch64_INS_FRSQRTE: frsqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTEv4f16, AArch64_INS_FRSQRTE: frsqrte */ 0, { 0 } }, { /* AArch64_FRSQRTEv4f32, AArch64_INS_FRSQRTE: frsqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTEv8f16, AArch64_INS_FRSQRTE: frsqrte */ 0, { 0 } }, { /* AArch64_FRSQRTS16, AArch64_INS_FRSQRTS: frsqrts */ 0, { 0 } }, { /* AArch64_FRSQRTS32, AArch64_INS_FRSQRTS: frsqrts */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTS64, AArch64_INS_FRSQRTS: frsqrts */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTS_ZZZ_D, AArch64_INS_FRSQRTS: frsqrts */ 0, { 0 } }, { /* AArch64_FRSQRTS_ZZZ_H, AArch64_INS_FRSQRTS: frsqrts */ 0, { 0 } }, { /* AArch64_FRSQRTS_ZZZ_S, AArch64_INS_FRSQRTS: frsqrts */ 0, { 0 } }, { /* AArch64_FRSQRTSv2f32, AArch64_INS_FRSQRTS: frsqrts */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTSv2f64, AArch64_INS_FRSQRTS: frsqrts */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTSv4f16, AArch64_INS_FRSQRTS: frsqrts */ 0, { 0 } }, { /* AArch64_FRSQRTSv4f32, AArch64_INS_FRSQRTS: frsqrts */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FRSQRTSv8f16, AArch64_INS_FRSQRTS: frsqrts */ 0, { 0 } }, { /* AArch64_FSCALE_ZPmZ_D, AArch64_INS_FSCALE: fscale */ 0, { 0 } }, { /* AArch64_FSCALE_ZPmZ_H, AArch64_INS_FSCALE: fscale */ 0, { 0 } }, { /* AArch64_FSCALE_ZPmZ_S, AArch64_INS_FSCALE: fscale */ 0, { 0 } }, { /* AArch64_FSQRTDr, AArch64_INS_FSQRT: fsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FSQRTHr, AArch64_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* AArch64_FSQRTSr, AArch64_INS_FSQRT: fsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FSQRT_ZPmZ_D, AArch64_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* AArch64_FSQRT_ZPmZ_H, AArch64_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* AArch64_FSQRT_ZPmZ_S, AArch64_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* AArch64_FSQRTv2f32, AArch64_INS_FSQRT: fsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FSQRTv2f64, AArch64_INS_FSQRT: fsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FSQRTv4f16, AArch64_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* AArch64_FSQRTv4f32, AArch64_INS_FSQRT: fsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_FSQRTv8f16, AArch64_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* AArch64_FSUBDrr, AArch64_INS_FSUB: fsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FSUBHrr, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUBR_ZPmI_D, AArch64_INS_FSUBR: fsubr */ 0, { 0 } }, { /* AArch64_FSUBR_ZPmI_H, AArch64_INS_FSUBR: fsubr */ 0, { 0 } }, { /* AArch64_FSUBR_ZPmI_S, AArch64_INS_FSUBR: fsubr */ 0, { 0 } }, { /* AArch64_FSUBR_ZPmZ_D, AArch64_INS_FSUBR: fsubr */ 0, { 0 } }, { /* AArch64_FSUBR_ZPmZ_H, AArch64_INS_FSUBR: fsubr */ 0, { 0 } }, { /* AArch64_FSUBR_ZPmZ_S, AArch64_INS_FSUBR: fsubr */ 0, { 0 } }, { /* AArch64_FSUBSrr, AArch64_INS_FSUB: fsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FSUB_ZPmI_D, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZPmI_H, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZPmI_S, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZPmZ_D, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZPmZ_H, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZPmZ_S, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZZZ_D, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZZZ_H, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUB_ZZZ_S, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUBv2f32, AArch64_INS_FSUB: fsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FSUBv2f64, AArch64_INS_FSUB: fsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FSUBv4f16, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FSUBv4f32, AArch64_INS_FSUB: fsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_FSUBv8f16, AArch64_INS_FSUB: fsub */ 0, { 0 } }, { /* AArch64_FTMAD_ZZI_D, AArch64_INS_FTMAD: ftmad */ 0, { 0 } }, { /* AArch64_FTMAD_ZZI_H, AArch64_INS_FTMAD: ftmad */ 0, { 0 } }, { /* AArch64_FTMAD_ZZI_S, AArch64_INS_FTMAD: ftmad */ 0, { 0 } }, { /* AArch64_FTSMUL_ZZZ_D, AArch64_INS_FTSMUL: ftsmul */ 0, { 0 } }, { /* AArch64_FTSMUL_ZZZ_H, AArch64_INS_FTSMUL: ftsmul */ 0, { 0 } }, { /* AArch64_FTSMUL_ZZZ_S, AArch64_INS_FTSMUL: ftsmul */ 0, { 0 } }, { /* AArch64_FTSSEL_ZZZ_D, AArch64_INS_FTSSEL: ftssel */ 0, { 0 } }, { /* AArch64_FTSSEL_ZZZ_H, AArch64_INS_FTSSEL: ftssel */ 0, { 0 } }, { /* AArch64_FTSSEL_ZZZ_S, AArch64_INS_FTSSEL: ftssel */ 0, { 0 } }, { /* AArch64_GLD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1B_D_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1B_D_SXTW_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1B_D_UXTW_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1B_S_SXTW_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1B_S_UXTW_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_GLD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1D_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1D_SCALED_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1D_SXTW_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1D_SXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1D_UXTW_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1D_UXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_GLD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_D_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_D_SCALED_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_D_SXTW_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_D_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_D_UXTW_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_D_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_S_SXTW_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_S_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_S_UXTW_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1H_S_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_GLD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SB_D_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SB_D_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SB_D_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SB_S_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SB_S_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_GLD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_D_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_D_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_D_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_D_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_D_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_D_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_S_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_S_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_S_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SH_S_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_GLD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1SW_D_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1SW_D_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1SW_D_SXTW_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1SW_D_SXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1SW_D_UXTW_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1SW_D_UXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_GLD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_D_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_D_SCALED_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_D_SXTW_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_D_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_D_UXTW_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_D_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_SXTW_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_UXTW_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLD1W_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_GLDFF1B_D_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1B_D_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1B_D_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1B_S_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1B_S_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1B_S_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_GLDFF1D_IMM_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1D_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1D_SXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1D_SXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1D_UXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1D_UXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_S_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_S_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_S_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1H_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_GLDFF1SB_D_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SB_D_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SB_D_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SB_S_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SB_S_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SB_S_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_S_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_S_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_S_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_IMM_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_SXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_UXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_GLDFF1W_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_HINT, AArch64_INS_CSDB: csdb */ 0, { CS_AC_READ, 0 } }, { /* AArch64_HLT, AArch64_INS_HLT: hlt */ 0, { CS_AC_READ, 0 } }, { /* AArch64_HVC, AArch64_INS_HVC: hvc */ 0, { CS_AC_READ, 0 } }, { /* AArch64_INCB_XPiI, AArch64_INS_INCB: incb */ 0, { 0 } }, { /* AArch64_INCD_XPiI, AArch64_INS_INCD: incd */ 0, { 0 } }, { /* AArch64_INCD_ZPiI, AArch64_INS_INCD: incd */ 0, { 0 } }, { /* AArch64_INCH_XPiI, AArch64_INS_INCH: inch */ 0, { 0 } }, { /* AArch64_INCH_ZPiI, AArch64_INS_INCH: inch */ 0, { 0 } }, { /* AArch64_INCP_XP_B, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCP_XP_D, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCP_XP_H, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCP_XP_S, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCP_ZP_D, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCP_ZP_H, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCP_ZP_S, AArch64_INS_INCP: incp */ 0, { 0 } }, { /* AArch64_INCW_XPiI, AArch64_INS_INCW: incw */ 0, { 0 } }, { /* AArch64_INCW_ZPiI, AArch64_INS_INCW: incw */ 0, { 0 } }, { /* AArch64_INDEX_II_B, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_II_D, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_II_H, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_II_S, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_IR_B, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_IR_D, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_IR_H, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_IR_S, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RI_B, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RI_D, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RI_H, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RI_S, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RR_B, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RR_D, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RR_H, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INDEX_RR_S, AArch64_INS_INDEX: index */ 0, { 0 } }, { /* AArch64_INSR_ZR_B, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZR_D, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZR_H, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZR_S, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZV_B, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZV_D, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZV_H, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSR_ZV_S, AArch64_INS_INSR: insr */ 0, { 0 } }, { /* AArch64_INSvi16gpr, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_INSvi16lane, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_INSvi32gpr, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_INSvi32lane, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_INSvi64gpr, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_INSvi64lane, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_INSvi8gpr, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_INSvi8lane, AArch64_INS_INS: ins */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_ISB, AArch64_INS_ISB: isb */ 0, { 0 } }, { /* AArch64_LASTA_RPZ_B, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_RPZ_D, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_RPZ_H, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_RPZ_S, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_VPZ_B, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_VPZ_D, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_VPZ_H, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTA_VPZ_S, AArch64_INS_LASTA: lasta */ 0, { 0 } }, { /* AArch64_LASTB_RPZ_B, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_RPZ_D, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_RPZ_H, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_RPZ_S, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_VPZ_B, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_VPZ_D, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_VPZ_H, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LASTB_VPZ_S, AArch64_INS_LASTB: lastb */ 0, { 0 } }, { /* AArch64_LD1B, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_D, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_H, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_H_IMM_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_IMM_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_S, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ 0, { 0 } }, { /* AArch64_LD1D, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_LD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ 0, { 0 } }, { /* AArch64_LD1Fourv16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Fourv8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1H, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_LD1H_D, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_LD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_LD1H_IMM_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_LD1H_S, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_LD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ 0, { 0 } }, { /* AArch64_LD1Onev16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Onev1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Onev2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD1Onev2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Onev4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Onev4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Onev8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Onev8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Onev8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1RB_D_IMM, AArch64_INS_LD1RB: ld1rb */ 0, { 0 } }, { /* AArch64_LD1RB_H_IMM, AArch64_INS_LD1RB: ld1rb */ 0, { 0 } }, { /* AArch64_LD1RB_IMM, AArch64_INS_LD1RB: ld1rb */ 0, { 0 } }, { /* AArch64_LD1RB_S_IMM, AArch64_INS_LD1RB: ld1rb */ 0, { 0 } }, { /* AArch64_LD1RD_IMM, AArch64_INS_LD1RD: ld1rd */ 0, { 0 } }, { /* AArch64_LD1RH_D_IMM, AArch64_INS_LD1RH: ld1rh */ 0, { 0 } }, { /* AArch64_LD1RH_IMM, AArch64_INS_LD1RH: ld1rh */ 0, { 0 } }, { /* AArch64_LD1RH_S_IMM, AArch64_INS_LD1RH: ld1rh */ 0, { 0 } }, { /* AArch64_LD1RQ_B, AArch64_INS_LD1RQB: ld1rqb */ 0, { 0 } }, { /* AArch64_LD1RQ_B_IMM, AArch64_INS_LD1RQB: ld1rqb */ 0, { 0 } }, { /* AArch64_LD1RQ_D, AArch64_INS_LD1RQD: ld1rqd */ 0, { 0 } }, { /* AArch64_LD1RQ_D_IMM, AArch64_INS_LD1RQD: ld1rqd */ 0, { 0 } }, { /* AArch64_LD1RQ_H, AArch64_INS_LD1RQH: ld1rqh */ 0, { 0 } }, { /* AArch64_LD1RQ_H_IMM, AArch64_INS_LD1RQH: ld1rqh */ 0, { 0 } }, { /* AArch64_LD1RQ_W, AArch64_INS_LD1RQW: ld1rqw */ 0, { 0 } }, { /* AArch64_LD1RQ_W_IMM, AArch64_INS_LD1RQW: ld1rqw */ 0, { 0 } }, { /* AArch64_LD1RSB_D_IMM, AArch64_INS_LD1RSB: ld1rsb */ 0, { 0 } }, { /* AArch64_LD1RSB_H_IMM, AArch64_INS_LD1RSB: ld1rsb */ 0, { 0 } }, { /* AArch64_LD1RSB_S_IMM, AArch64_INS_LD1RSB: ld1rsb */ 0, { 0 } }, { /* AArch64_LD1RSH_D_IMM, AArch64_INS_LD1RSH: ld1rsh */ 0, { 0 } }, { /* AArch64_LD1RSH_S_IMM, AArch64_INS_LD1RSH: ld1rsh */ 0, { 0 } }, { /* AArch64_LD1RSW_IMM, AArch64_INS_LD1RSW: ld1rsw */ 0, { 0 } }, { /* AArch64_LD1RW_D_IMM, AArch64_INS_LD1RW: ld1rw */ 0, { 0 } }, { /* AArch64_LD1RW_IMM, AArch64_INS_LD1RW: ld1rw */ 0, { 0 } }, { /* AArch64_LD1Rv16b, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv16b_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv1d, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv1d_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv2d, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv2d_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv2s, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv2s_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv4h, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv4h_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv4s, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv4s_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv8b, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv8b_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Rv8h, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Rv8h_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1SB_D, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_LD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_LD1SB_H, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_LD1SB_H_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_LD1SB_S, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_LD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ 0, { 0 } }, { /* AArch64_LD1SH_D, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_LD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_LD1SH_S, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_LD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ 0, { 0 } }, { /* AArch64_LD1SW_D, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_LD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ 0, { 0 } }, { /* AArch64_LD1Threev16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Threev8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Threev8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1Twov8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1Twov8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1W, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_LD1W_D, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_LD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_LD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ 0, { 0 } }, { /* AArch64_LD1i16, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1i16_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1i32, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1i32_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1i64, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1i64_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD1i8, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD1i8_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2B, AArch64_INS_LD2B: ld2b */ 0, { 0 } }, { /* AArch64_LD2B_IMM, AArch64_INS_LD2B: ld2b */ 0, { 0 } }, { /* AArch64_LD2D, AArch64_INS_LD2D: ld2d */ 0, { 0 } }, { /* AArch64_LD2D_IMM, AArch64_INS_LD2D: ld2d */ 0, { 0 } }, { /* AArch64_LD2H, AArch64_INS_LD2H: ld2h */ 0, { 0 } }, { /* AArch64_LD2H_IMM, AArch64_INS_LD2H: ld2h */ 0, { 0 } }, { /* AArch64_LD2Rv16b, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv16b_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv1d, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv1d_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv2d, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv2d_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv2s, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv2s_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv4h, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv4h_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv4s, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv4s_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv8b, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv8b_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Rv8h, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD2Rv8h_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD2Twov16b, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov16b_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2Twov2d, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov2d_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2Twov2s, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov2s_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2Twov4h, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov4h_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2Twov4s, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov4s_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2Twov8b, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov8b_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2Twov8h, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2Twov8h_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2W, AArch64_INS_LD2W: ld2w */ 0, { 0 } }, { /* AArch64_LD2W_IMM, AArch64_INS_LD2W: ld2w */ 0, { 0 } }, { /* AArch64_LD2i16, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2i16_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2i32, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2i32_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2i64, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2i64_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD2i8, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, { /* AArch64_LD2i8_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LD3B, AArch64_INS_LD3B: ld3b */ 0, { 0 } }, { /* AArch64_LD3B_IMM, AArch64_INS_LD3B: ld3b */ 0, { 0 } }, { /* AArch64_LD3D, AArch64_INS_LD3D: ld3d */ 0, { 0 } }, { /* AArch64_LD3D_IMM, AArch64_INS_LD3D: ld3d */ 0, { 0 } }, { /* AArch64_LD3H, AArch64_INS_LD3H: ld3h */ 0, { 0 } }, { /* AArch64_LD3H_IMM, AArch64_INS_LD3H: ld3h */ 0, { 0 } }, { /* AArch64_LD3Rv16b, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv16b_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv1d, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv1d_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv2d, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv2d_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv2s, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv2s_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv4h, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv4h_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv4s, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv4s_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv8b, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv8b_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Rv8h, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Rv8h_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev16b, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev16b_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev2d, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev2d_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev2s, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev2s_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev4h, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev4h_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev4s, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev4s_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev8b, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev8b_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3Threev8h, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3Threev8h_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD3W, AArch64_INS_LD3W: ld3w */ 0, { 0 } }, { /* AArch64_LD3W_IMM, AArch64_INS_LD3W: ld3w */ 0, { 0 } }, { /* AArch64_LD3i16, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3i16_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD3i32, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3i32_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD3i64, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3i64_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD3i8, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD3i8_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD4B, AArch64_INS_LD4B: ld4b */ 0, { 0 } }, { /* AArch64_LD4B_IMM, AArch64_INS_LD4B: ld4b */ 0, { 0 } }, { /* AArch64_LD4D, AArch64_INS_LD4D: ld4d */ 0, { 0 } }, { /* AArch64_LD4D_IMM, AArch64_INS_LD4D: ld4d */ 0, { 0 } }, { /* AArch64_LD4Fourv16b, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv16b_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv2d, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv2d_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv2s, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv2s_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv4h, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv4h_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv4s, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv4s_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv8b, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv8b_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv8h, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Fourv8h_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4H, AArch64_INS_LD4H: ld4h */ 0, { 0 } }, { /* AArch64_LD4H_IMM, AArch64_INS_LD4H: ld4h */ 0, { 0 } }, { /* AArch64_LD4Rv16b, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv16b_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv1d, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv1d_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv2d, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv2d_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv2s, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv2s_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv4h, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv4h_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv4s, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv4s_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv8b, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv8b_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4Rv8h, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4Rv8h_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LD4W, AArch64_INS_LD4W: ld4w */ 0, { 0 } }, { /* AArch64_LD4W_IMM, AArch64_INS_LD4W: ld4w */ 0, { 0 } }, { /* AArch64_LD4i16, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4i16_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD4i32, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4i32_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD4i64, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4i64_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LD4i8, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_LD4i8_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDADDAB, AArch64_INS_LDADDAB: ldaddab */ 0, { 0 } }, { /* AArch64_LDADDAH, AArch64_INS_LDADDAH: ldaddah */ 0, { 0 } }, { /* AArch64_LDADDALB, AArch64_INS_LDADDALB: ldaddalb */ 0, { 0 } }, { /* AArch64_LDADDALH, AArch64_INS_LDADDALH: ldaddalh */ 0, { 0 } }, { /* AArch64_LDADDALW, AArch64_INS_LDADDAL: ldaddal */ 0, { 0 } }, { /* AArch64_LDADDALX, AArch64_INS_LDADDAL: ldaddal */ 0, { 0 } }, { /* AArch64_LDADDAW, AArch64_INS_LDADDA: ldadda */ 0, { 0 } }, { /* AArch64_LDADDAX, AArch64_INS_LDADDA: ldadda */ 0, { 0 } }, { /* AArch64_LDADDB, AArch64_INS_LDADDB: ldaddb */ 0, { 0 } }, { /* AArch64_LDADDH, AArch64_INS_LDADDH: ldaddh */ 0, { 0 } }, { /* AArch64_LDADDLB, AArch64_INS_LDADDLB: ldaddlb */ 0, { 0 } }, { /* AArch64_LDADDLH, AArch64_INS_LDADDLH: ldaddlh */ 0, { 0 } }, { /* AArch64_LDADDLW, AArch64_INS_LDADDL: ldaddl */ 0, { 0 } }, { /* AArch64_LDADDLX, AArch64_INS_LDADDL: ldaddl */ 0, { 0 } }, { /* AArch64_LDADDW, AArch64_INS_LDADD: ldadd */ 0, { 0 } }, { /* AArch64_LDADDX, AArch64_INS_LDADD: ldadd */ 0, { 0 } }, { /* AArch64_LDAPRB, AArch64_INS_LDAPRB: ldaprb */ 0, { 0 } }, { /* AArch64_LDAPRH, AArch64_INS_LDAPRH: ldaprh */ 0, { 0 } }, { /* AArch64_LDAPRW, AArch64_INS_LDAPR: ldapr */ 0, { 0 } }, { /* AArch64_LDAPRX, AArch64_INS_LDAPR: ldapr */ 0, { 0 } }, { /* AArch64_LDAPURBi, AArch64_INS_LDAPURB: ldapurb */ 0, { 0 } }, { /* AArch64_LDAPURHi, AArch64_INS_LDAPURH: ldapurh */ 0, { 0 } }, { /* AArch64_LDAPURSBWi, AArch64_INS_LDAPURSB: ldapursb */ 0, { 0 } }, { /* AArch64_LDAPURSBXi, AArch64_INS_LDAPURSB: ldapursb */ 0, { 0 } }, { /* AArch64_LDAPURSHWi, AArch64_INS_LDAPURSH: ldapursh */ 0, { 0 } }, { /* AArch64_LDAPURSHXi, AArch64_INS_LDAPURSH: ldapursh */ 0, { 0 } }, { /* AArch64_LDAPURSWi, AArch64_INS_LDAPURSW: ldapursw */ 0, { 0 } }, { /* AArch64_LDAPURXi, AArch64_INS_LDAPUR: ldapur */ 0, { 0 } }, { /* AArch64_LDAPURi, AArch64_INS_LDAPUR: ldapur */ 0, { 0 } }, { /* AArch64_LDARB, AArch64_INS_LDARB: ldarb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDARH, AArch64_INS_LDARH: ldarh */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDARW, AArch64_INS_LDAR: ldar */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDARX, AArch64_INS_LDAR: ldar */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAXPW, AArch64_INS_LDAXP: ldaxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAXPX, AArch64_INS_LDAXP: ldaxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAXRB, AArch64_INS_LDAXRB: ldaxrb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAXRH, AArch64_INS_LDAXRH: ldaxrh */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAXRW, AArch64_INS_LDAXR: ldaxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDAXRX, AArch64_INS_LDAXR: ldaxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDCLRAB, AArch64_INS_LDCLRAB: ldclrab */ 0, { 0 } }, { /* AArch64_LDCLRAH, AArch64_INS_LDCLRAH: ldclrah */ 0, { 0 } }, { /* AArch64_LDCLRALB, AArch64_INS_LDCLRALB: ldclralb */ 0, { 0 } }, { /* AArch64_LDCLRALH, AArch64_INS_LDCLRALH: ldclralh */ 0, { 0 } }, { /* AArch64_LDCLRALW, AArch64_INS_LDCLRAL: ldclral */ 0, { 0 } }, { /* AArch64_LDCLRALX, AArch64_INS_LDCLRAL: ldclral */ 0, { 0 } }, { /* AArch64_LDCLRAW, AArch64_INS_LDCLRA: ldclra */ 0, { 0 } }, { /* AArch64_LDCLRAX, AArch64_INS_LDCLRA: ldclra */ 0, { 0 } }, { /* AArch64_LDCLRB, AArch64_INS_LDCLRB: ldclrb */ 0, { 0 } }, { /* AArch64_LDCLRH, AArch64_INS_LDCLRH: ldclrh */ 0, { 0 } }, { /* AArch64_LDCLRLB, AArch64_INS_LDCLRLB: ldclrlb */ 0, { 0 } }, { /* AArch64_LDCLRLH, AArch64_INS_LDCLRLH: ldclrlh */ 0, { 0 } }, { /* AArch64_LDCLRLW, AArch64_INS_LDCLRL: ldclrl */ 0, { 0 } }, { /* AArch64_LDCLRLX, AArch64_INS_LDCLRL: ldclrl */ 0, { 0 } }, { /* AArch64_LDCLRW, AArch64_INS_LDCLR: ldclr */ 0, { 0 } }, { /* AArch64_LDCLRX, AArch64_INS_LDCLR: ldclr */ 0, { 0 } }, { /* AArch64_LDEORAB, AArch64_INS_LDEORAB: ldeorab */ 0, { 0 } }, { /* AArch64_LDEORAH, AArch64_INS_LDEORAH: ldeorah */ 0, { 0 } }, { /* AArch64_LDEORALB, AArch64_INS_LDEORALB: ldeoralb */ 0, { 0 } }, { /* AArch64_LDEORALH, AArch64_INS_LDEORALH: ldeoralh */ 0, { 0 } }, { /* AArch64_LDEORALW, AArch64_INS_LDEORAL: ldeoral */ 0, { 0 } }, { /* AArch64_LDEORALX, AArch64_INS_LDEORAL: ldeoral */ 0, { 0 } }, { /* AArch64_LDEORAW, AArch64_INS_LDEORA: ldeora */ 0, { 0 } }, { /* AArch64_LDEORAX, AArch64_INS_LDEORA: ldeora */ 0, { 0 } }, { /* AArch64_LDEORB, AArch64_INS_LDEORB: ldeorb */ 0, { 0 } }, { /* AArch64_LDEORH, AArch64_INS_LDEORH: ldeorh */ 0, { 0 } }, { /* AArch64_LDEORLB, AArch64_INS_LDEORLB: ldeorlb */ 0, { 0 } }, { /* AArch64_LDEORLH, AArch64_INS_LDEORLH: ldeorlh */ 0, { 0 } }, { /* AArch64_LDEORLW, AArch64_INS_LDEORL: ldeorl */ 0, { 0 } }, { /* AArch64_LDEORLX, AArch64_INS_LDEORL: ldeorl */ 0, { 0 } }, { /* AArch64_LDEORW, AArch64_INS_LDEOR: ldeor */ 0, { 0 } }, { /* AArch64_LDEORX, AArch64_INS_LDEOR: ldeor */ 0, { 0 } }, { /* AArch64_LDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_LDFF1B_H_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_LDFF1B_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_LDFF1B_S_REAL, AArch64_INS_LDFF1B: ldff1b */ 0, { 0 } }, { /* AArch64_LDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ 0, { 0 } }, { /* AArch64_LDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_LDFF1H_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_LDFF1H_S_REAL, AArch64_INS_LDFF1H: ldff1h */ 0, { 0 } }, { /* AArch64_LDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_LDFF1SB_H_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_LDFF1SB_S_REAL, AArch64_INS_LDFF1SB: ldff1sb */ 0, { 0 } }, { /* AArch64_LDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_LDFF1SH_S_REAL, AArch64_INS_LDFF1SH: ldff1sh */ 0, { 0 } }, { /* AArch64_LDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ 0, { 0 } }, { /* AArch64_LDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_LDFF1W_REAL, AArch64_INS_LDFF1W: ldff1w */ 0, { 0 } }, { /* AArch64_LDLARB, AArch64_INS_LDLARB: ldlarb */ 0, { 0 } }, { /* AArch64_LDLARH, AArch64_INS_LDLARH: ldlarh */ 0, { 0 } }, { /* AArch64_LDLARW, AArch64_INS_LDLAR: ldlar */ 0, { 0 } }, { /* AArch64_LDLARX, AArch64_INS_LDLAR: ldlar */ 0, { 0 } }, { /* AArch64_LDNF1B_D_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ 0, { 0 } }, { /* AArch64_LDNF1B_H_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ 0, { 0 } }, { /* AArch64_LDNF1B_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ 0, { 0 } }, { /* AArch64_LDNF1B_S_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ 0, { 0 } }, { /* AArch64_LDNF1D_IMM_REAL, AArch64_INS_LDNF1D: ldnf1d */ 0, { 0 } }, { /* AArch64_LDNF1H_D_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ 0, { 0 } }, { /* AArch64_LDNF1H_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ 0, { 0 } }, { /* AArch64_LDNF1H_S_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ 0, { 0 } }, { /* AArch64_LDNF1SB_D_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ 0, { 0 } }, { /* AArch64_LDNF1SB_H_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ 0, { 0 } }, { /* AArch64_LDNF1SB_S_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ 0, { 0 } }, { /* AArch64_LDNF1SH_D_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ 0, { 0 } }, { /* AArch64_LDNF1SH_S_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ 0, { 0 } }, { /* AArch64_LDNF1SW_D_IMM_REAL, AArch64_INS_LDNF1SW: ldnf1sw */ 0, { 0 } }, { /* AArch64_LDNF1W_D_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ 0, { 0 } }, { /* AArch64_LDNF1W_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ 0, { 0 } }, { /* AArch64_LDNPDi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDNPQi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDNPSi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDNPWi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDNPXi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDNT1B_ZRI, AArch64_INS_LDNT1B: ldnt1b */ 0, { 0 } }, { /* AArch64_LDNT1B_ZRR, AArch64_INS_LDNT1B: ldnt1b */ 0, { 0 } }, { /* AArch64_LDNT1D_ZRI, AArch64_INS_LDNT1D: ldnt1d */ 0, { 0 } }, { /* AArch64_LDNT1D_ZRR, AArch64_INS_LDNT1D: ldnt1d */ 0, { 0 } }, { /* AArch64_LDNT1H_ZRI, AArch64_INS_LDNT1H: ldnt1h */ 0, { 0 } }, { /* AArch64_LDNT1H_ZRR, AArch64_INS_LDNT1H: ldnt1h */ 0, { 0 } }, { /* AArch64_LDNT1W_ZRI, AArch64_INS_LDNT1W: ldnt1w */ 0, { 0 } }, { /* AArch64_LDNT1W_ZRR, AArch64_INS_LDNT1W: ldnt1w */ 0, { 0 } }, { /* AArch64_LDPDi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPDpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPDpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPQi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPQpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPQpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPSWi, AArch64_INS_LDPSW: ldpsw */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPSWpost, AArch64_INS_LDPSW: ldpsw */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPSWpre, AArch64_INS_LDPSW: ldpsw */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPSi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPSpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPSpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPWi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPWpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPWpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPXi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPXpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDPXpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRAAindexed, AArch64_INS_LDRAA: ldraa */ 0, { 0 } }, { /* AArch64_LDRAAwriteback, AArch64_INS_LDRAA: ldraa */ 0, { 0 } }, { /* AArch64_LDRABindexed, AArch64_INS_LDRAB: ldrab */ 0, { 0 } }, { /* AArch64_LDRABwriteback, AArch64_INS_LDRAB: ldrab */ 0, { 0 } }, { /* AArch64_LDRBBpost, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRBBpre, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRBBroW, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRBBroX, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRBBui, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRBpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRBpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRBroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRBroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRBui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRDl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDRDpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRDpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRDroW, AArch64_INS_LDR: ldr */ 00, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRDroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRDui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHHpost, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHHpre, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHHroW, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHHroX, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHHui, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRHroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRHroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRHui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRQl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDRQpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRQpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRQroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRQroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRQui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSBWpost, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSBWpre, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSBWroW, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSBWroX, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSBWui, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSBXpost, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSBXpre, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSBXroW, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSBXroX, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSBXui, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSHWpost, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSHWpre, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSHWroW, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSHWroX, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSHWui, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSHXpost, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSHXpre, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSHXroW, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSHXroX, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSHXui, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSWl, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDRSWpost, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSWpre, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSWroW, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSWroX, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSWui, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDRSpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRSroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRSui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRWl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDRWpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRWpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRWroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRWroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRWui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRXl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDRXpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRXpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDRXroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRXroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_LDRXui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LDR_PXI, AArch64_INS_LDR: ldr */ 0, { 0 } }, { /* AArch64_LDR_ZXI, AArch64_INS_LDR: ldr */ 0, { 0 } }, { /* AArch64_LDSETAB, AArch64_INS_LDSETAB: ldsetab */ 0, { 0 } }, { /* AArch64_LDSETAH, AArch64_INS_LDSETAH: ldsetah */ 0, { 0 } }, { /* AArch64_LDSETALB, AArch64_INS_LDSETALB: ldsetalb */ 0, { 0 } }, { /* AArch64_LDSETALH, AArch64_INS_LDSETALH: ldsetalh */ 0, { 0 } }, { /* AArch64_LDSETALW, AArch64_INS_LDSETAL: ldsetal */ 0, { 0 } }, { /* AArch64_LDSETALX, AArch64_INS_LDSETAL: ldsetal */ 0, { 0 } }, { /* AArch64_LDSETAW, AArch64_INS_LDSETA: ldseta */ 0, { 0 } }, { /* AArch64_LDSETAX, AArch64_INS_LDSETA: ldseta */ 0, { 0 } }, { /* AArch64_LDSETB, AArch64_INS_LDSETB: ldsetb */ 0, { 0 } }, { /* AArch64_LDSETH, AArch64_INS_LDSETH: ldseth */ 0, { 0 } }, { /* AArch64_LDSETLB, AArch64_INS_LDSETLB: ldsetlb */ 0, { 0 } }, { /* AArch64_LDSETLH, AArch64_INS_LDSETLH: ldsetlh */ 0, { 0 } }, { /* AArch64_LDSETLW, AArch64_INS_LDSETL: ldsetl */ 0, { 0 } }, { /* AArch64_LDSETLX, AArch64_INS_LDSETL: ldsetl */ 0, { 0 } }, { /* AArch64_LDSETW, AArch64_INS_LDSET: ldset */ 0, { 0 } }, { /* AArch64_LDSETX, AArch64_INS_LDSET: ldset */ 0, { 0 } }, { /* AArch64_LDSMAXAB, AArch64_INS_LDSMAXAB: ldsmaxab */ 0, { 0 } }, { /* AArch64_LDSMAXAH, AArch64_INS_LDSMAXAH: ldsmaxah */ 0, { 0 } }, { /* AArch64_LDSMAXALB, AArch64_INS_LDSMAXALB: ldsmaxalb */ 0, { 0 } }, { /* AArch64_LDSMAXALH, AArch64_INS_LDSMAXALH: ldsmaxalh */ 0, { 0 } }, { /* AArch64_LDSMAXALW, AArch64_INS_LDSMAXAL: ldsmaxal */ 0, { 0 } }, { /* AArch64_LDSMAXALX, AArch64_INS_LDSMAXAL: ldsmaxal */ 0, { 0 } }, { /* AArch64_LDSMAXAW, AArch64_INS_LDSMAXA: ldsmaxa */ 0, { 0 } }, { /* AArch64_LDSMAXAX, AArch64_INS_LDSMAXA: ldsmaxa */ 0, { 0 } }, { /* AArch64_LDSMAXB, AArch64_INS_LDSMAXB: ldsmaxb */ 0, { 0 } }, { /* AArch64_LDSMAXH, AArch64_INS_LDSMAXH: ldsmaxh */ 0, { 0 } }, { /* AArch64_LDSMAXLB, AArch64_INS_LDSMAXLB: ldsmaxlb */ 0, { 0 } }, { /* AArch64_LDSMAXLH, AArch64_INS_LDSMAXLH: ldsmaxlh */ 0, { 0 } }, { /* AArch64_LDSMAXLW, AArch64_INS_LDSMAXL: ldsmaxl */ 0, { 0 } }, { /* AArch64_LDSMAXLX, AArch64_INS_LDSMAXL: ldsmaxl */ 0, { 0 } }, { /* AArch64_LDSMAXW, AArch64_INS_LDSMAX: ldsmax */ 0, { 0 } }, { /* AArch64_LDSMAXX, AArch64_INS_LDSMAX: ldsmax */ 0, { 0 } }, { /* AArch64_LDSMINAB, AArch64_INS_LDSMINAB: ldsminab */ 0, { 0 } }, { /* AArch64_LDSMINAH, AArch64_INS_LDSMINAH: ldsminah */ 0, { 0 } }, { /* AArch64_LDSMINALB, AArch64_INS_LDSMINALB: ldsminalb */ 0, { 0 } }, { /* AArch64_LDSMINALH, AArch64_INS_LDSMINALH: ldsminalh */ 0, { 0 } }, { /* AArch64_LDSMINALW, AArch64_INS_LDSMINAL: ldsminal */ 0, { 0 } }, { /* AArch64_LDSMINALX, AArch64_INS_LDSMINAL: ldsminal */ 0, { 0 } }, { /* AArch64_LDSMINAW, AArch64_INS_LDSMINA: ldsmina */ 0, { 0 } }, { /* AArch64_LDSMINAX, AArch64_INS_LDSMINA: ldsmina */ 0, { 0 } }, { /* AArch64_LDSMINB, AArch64_INS_LDSMINB: ldsminb */ 0, { 0 } }, { /* AArch64_LDSMINH, AArch64_INS_LDSMINH: ldsminh */ 0, { 0 } }, { /* AArch64_LDSMINLB, AArch64_INS_LDSMINLB: ldsminlb */ 0, { 0 } }, { /* AArch64_LDSMINLH, AArch64_INS_LDSMINLH: ldsminlh */ 0, { 0 } }, { /* AArch64_LDSMINLW, AArch64_INS_LDSMINL: ldsminl */ 0, { 0 } }, { /* AArch64_LDSMINLX, AArch64_INS_LDSMINL: ldsminl */ 0, { 0 } }, { /* AArch64_LDSMINW, AArch64_INS_LDSMIN: ldsmin */ 0, { 0 } }, { /* AArch64_LDSMINX, AArch64_INS_LDSMIN: ldsmin */ 0, { 0 } }, { /* AArch64_LDTRBi, AArch64_INS_LDTRB: ldtrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRHi, AArch64_INS_LDTRH: ldtrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRSBWi, AArch64_INS_LDTRSB: ldtrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRSBXi, AArch64_INS_LDTRSB: ldtrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRSHWi, AArch64_INS_LDTRSH: ldtrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRSHXi, AArch64_INS_LDTRSH: ldtrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRSWi, AArch64_INS_LDTRSW: ldtrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRWi, AArch64_INS_LDTR: ldtr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDTRXi, AArch64_INS_LDTR: ldtr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDUMAXAB, AArch64_INS_LDUMAXAB: ldumaxab */ 0, { 0 } }, { /* AArch64_LDUMAXAH, AArch64_INS_LDUMAXAH: ldumaxah */ 0, { 0 } }, { /* AArch64_LDUMAXALB, AArch64_INS_LDUMAXALB: ldumaxalb */ 0, { 0 } }, { /* AArch64_LDUMAXALH, AArch64_INS_LDUMAXALH: ldumaxalh */ 0, { 0 } }, { /* AArch64_LDUMAXALW, AArch64_INS_LDUMAXAL: ldumaxal */ 0, { 0 } }, { /* AArch64_LDUMAXALX, AArch64_INS_LDUMAXAL: ldumaxal */ 0, { 0 } }, { /* AArch64_LDUMAXAW, AArch64_INS_LDUMAXA: ldumaxa */ 0, { 0 } }, { /* AArch64_LDUMAXAX, AArch64_INS_LDUMAXA: ldumaxa */ 0, { 0 } }, { /* AArch64_LDUMAXB, AArch64_INS_LDUMAXB: ldumaxb */ 0, { 0 } }, { /* AArch64_LDUMAXH, AArch64_INS_LDUMAXH: ldumaxh */ 0, { 0 } }, { /* AArch64_LDUMAXLB, AArch64_INS_LDUMAXLB: ldumaxlb */ 0, { 0 } }, { /* AArch64_LDUMAXLH, AArch64_INS_LDUMAXLH: ldumaxlh */ 0, { 0 } }, { /* AArch64_LDUMAXLW, AArch64_INS_LDUMAXL: ldumaxl */ 0, { 0 } }, { /* AArch64_LDUMAXLX, AArch64_INS_LDUMAXL: ldumaxl */ 0, { 0 } }, { /* AArch64_LDUMAXW, AArch64_INS_LDUMAX: ldumax */ 0, { 0 } }, { /* AArch64_LDUMAXX, AArch64_INS_LDUMAX: ldumax */ 0, { 0 } }, { /* AArch64_LDUMINAB, AArch64_INS_LDUMINAB: lduminab */ 0, { 0 } }, { /* AArch64_LDUMINAH, AArch64_INS_LDUMINAH: lduminah */ 0, { 0 } }, { /* AArch64_LDUMINALB, AArch64_INS_LDUMINALB: lduminalb */ 0, { 0 } }, { /* AArch64_LDUMINALH, AArch64_INS_LDUMINALH: lduminalh */ 0, { 0 } }, { /* AArch64_LDUMINALW, AArch64_INS_LDUMINAL: lduminal */ 0, { 0 } }, { /* AArch64_LDUMINALX, AArch64_INS_LDUMINAL: lduminal */ 0, { 0 } }, { /* AArch64_LDUMINAW, AArch64_INS_LDUMINA: ldumina */ 0, { 0 } }, { /* AArch64_LDUMINAX, AArch64_INS_LDUMINA: ldumina */ 0, { 0 } }, { /* AArch64_LDUMINB, AArch64_INS_LDUMINB: lduminb */ 0, { 0 } }, { /* AArch64_LDUMINH, AArch64_INS_LDUMINH: lduminh */ 0, { 0 } }, { /* AArch64_LDUMINLB, AArch64_INS_LDUMINLB: lduminlb */ 0, { 0 } }, { /* AArch64_LDUMINLH, AArch64_INS_LDUMINLH: lduminlh */ 0, { 0 } }, { /* AArch64_LDUMINLW, AArch64_INS_LDUMINL: lduminl */ 0, { 0 } }, { /* AArch64_LDUMINLX, AArch64_INS_LDUMINL: lduminl */ 0, { 0 } }, { /* AArch64_LDUMINW, AArch64_INS_LDUMIN: ldumin */ 0, { 0 } }, { /* AArch64_LDUMINX, AArch64_INS_LDUMIN: ldumin */ 0, { 0 } }, { /* AArch64_LDURBBi, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURBi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURDi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURHHi, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURHi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURQi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURSBWi, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURSBXi, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURSHWi, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURSHXi, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURSWi, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURSi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURWi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDURXi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_LDXPW, AArch64_INS_LDXP: ldxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDXPX, AArch64_INS_LDXP: ldxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDXRB, AArch64_INS_LDXRB: ldxrb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDXRH, AArch64_INS_LDXRH: ldxrh */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDXRW, AArch64_INS_LDXR: ldxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LDXRX, AArch64_INS_LDXR: ldxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_LSLR_ZPmZ_B, AArch64_INS_LSLR: lslr */ 0, { 0 } }, { /* AArch64_LSLR_ZPmZ_D, AArch64_INS_LSLR: lslr */ 0, { 0 } }, { /* AArch64_LSLR_ZPmZ_H, AArch64_INS_LSLR: lslr */ 0, { 0 } }, { /* AArch64_LSLR_ZPmZ_S, AArch64_INS_LSLR: lslr */ 0, { 0 } }, { /* AArch64_LSLVWr, AArch64_INS_LSL: lsl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LSLVXr, AArch64_INS_LSL: lsl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LSL_WIDE_ZPmZ_B, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_WIDE_ZPmZ_H, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_WIDE_ZPmZ_S, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_WIDE_ZZZ_B, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_WIDE_ZZZ_H, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_WIDE_ZZZ_S, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmI_B, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmI_D, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmI_H, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmI_S, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmZ_B, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmZ_D, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmZ_H, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZPmZ_S, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZZI_B, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZZI_D, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZZI_H, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSL_ZZI_S, AArch64_INS_LSL: lsl */ 0, { 0 } }, { /* AArch64_LSRR_ZPmZ_B, AArch64_INS_LSRR: lsrr */ 0, { 0 } }, { /* AArch64_LSRR_ZPmZ_D, AArch64_INS_LSRR: lsrr */ 0, { 0 } }, { /* AArch64_LSRR_ZPmZ_H, AArch64_INS_LSRR: lsrr */ 0, { 0 } }, { /* AArch64_LSRR_ZPmZ_S, AArch64_INS_LSRR: lsrr */ 0, { 0 } }, { /* AArch64_LSRVWr, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LSRVXr, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_LSR_WIDE_ZPmZ_B, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_WIDE_ZPmZ_H, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_WIDE_ZPmZ_S, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_WIDE_ZZZ_B, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_WIDE_ZZZ_H, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_WIDE_ZZZ_S, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmI_B, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmI_D, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmI_H, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmI_S, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmZ_B, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmZ_D, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmZ_H, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZPmZ_S, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZZI_B, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZZI_D, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZZI_H, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_LSR_ZZI_S, AArch64_INS_LSR: lsr */ 0, { 0 } }, { /* AArch64_MADDWrrr, AArch64_INS_MADD: madd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MADDXrrr, AArch64_INS_MADD: madd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MAD_ZPmZZ_B, AArch64_INS_MAD: mad */ 0, { 0 } }, { /* AArch64_MAD_ZPmZZ_D, AArch64_INS_MAD: mad */ 0, { 0 } }, { /* AArch64_MAD_ZPmZZ_H, AArch64_INS_MAD: mad */ 0, { 0 } }, { /* AArch64_MAD_ZPmZZ_S, AArch64_INS_MAD: mad */ 0, { 0 } }, { /* AArch64_MLA_ZPmZZ_B, AArch64_INS_MLA: mla */ 0, { 0 } }, { /* AArch64_MLA_ZPmZZ_D, AArch64_INS_MLA: mla */ 0, { 0 } }, { /* AArch64_MLA_ZPmZZ_H, AArch64_INS_MLA: mla */ 0, { 0 } }, { /* AArch64_MLA_ZPmZZ_S, AArch64_INS_MLA: mla */ 0, { 0 } }, { /* AArch64_MLAv16i8, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLAv2i32, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLAv2i32_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLAv4i16, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLAv4i16_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLAv4i32, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLAv4i32_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLAv8i16, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLAv8i16_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLAv8i8, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLS_ZPmZZ_B, AArch64_INS_MLS: mls */ 0, { 0 } }, { /* AArch64_MLS_ZPmZZ_D, AArch64_INS_MLS: mls */ 0, { 0 } }, { /* AArch64_MLS_ZPmZZ_H, AArch64_INS_MLS: mls */ 0, { 0 } }, { /* AArch64_MLS_ZPmZZ_S, AArch64_INS_MLS: mls */ 0, { 0 } }, { /* AArch64_MLSv16i8, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLSv2i32, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLSv2i32_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLSv4i16, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLSv4i16_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLSv4i32, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLSv4i32_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLSv8i16, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MLSv8i16_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MLSv8i8, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVID, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv16b_ns, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv2d_ns, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv2i32, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv2s_msl, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv4i16, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv4i32, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv4s_msl, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv8b_ns, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVIv8i16, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVKWi, AArch64_INS_MOVK: movk */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVKXi, AArch64_INS_MOVK: movk */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVNWi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVNXi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVPRFX_ZPmZ_B, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPmZ_D, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPmZ_H, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPmZ_S, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPzZ_B, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPzZ_D, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPzZ_H, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZPzZ_S, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVPRFX_ZZ, AArch64_INS_MOVPRFX: movprfx */ 0, { 0 } }, { /* AArch64_MOVZWi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MOVZXi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MRS, AArch64_INS_MRS: mrs */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_MSB_ZPmZZ_B, AArch64_INS_MSB: msb */ 0, { 0 } }, { /* AArch64_MSB_ZPmZZ_D, AArch64_INS_MSB: msb */ 0, { 0 } }, { /* AArch64_MSB_ZPmZZ_H, AArch64_INS_MSB: msb */ 0, { 0 } }, { /* AArch64_MSB_ZPmZZ_S, AArch64_INS_MSB: msb */ 0, { 0 } }, { /* AArch64_MSR, AArch64_INS_MSR: msr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_MSRpstateImm1, AArch64_INS_MSR: msr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MSRpstateImm4, AArch64_INS_MSR: msr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MSUBWrrr, AArch64_INS_MNEG: mneg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MSUBXrrr, AArch64_INS_MNEG: mneg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MUL_ZI_B, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZI_D, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZI_H, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZI_S, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZPmZ_B, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZPmZ_D, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZPmZ_H, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MUL_ZPmZ_S, AArch64_INS_MUL: mul */ 0, { 0 } }, { /* AArch64_MULv16i8, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv2i32, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv2i32_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MULv4i16, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv4i16_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_MULv4i32, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv4i32_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv8i16, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv8i16_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MULv8i8, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MVNIv2i32, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MVNIv2s_msl, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MVNIv4i16, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MVNIv4i32, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MVNIv4s_msl, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_MVNIv8i16, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_NANDS_PPzPP, AArch64_INS_NANDS: nands */ 0, { 0 } }, { /* AArch64_NAND_PPzPP, AArch64_INS_NAND: nand */ 0, { 0 } }, { /* AArch64_NEG_ZPmZ_B, AArch64_INS_NEG: neg */ 0, { 0 } }, { /* AArch64_NEG_ZPmZ_D, AArch64_INS_NEG: neg */ 0, { 0 } }, { /* AArch64_NEG_ZPmZ_H, AArch64_INS_NEG: neg */ 0, { 0 } }, { /* AArch64_NEG_ZPmZ_S, AArch64_INS_NEG: neg */ 0, { 0 } }, { /* AArch64_NEGv16i8, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv1i64, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv2i32, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv2i64, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv4i16, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv4i32, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv8i16, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NEGv8i8, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NORS_PPzPP, AArch64_INS_NORS: nors */ 0, { 0 } }, { /* AArch64_NOR_PPzPP, AArch64_INS_NOR: nor */ 0, { 0 } }, { /* AArch64_NOT_ZPmZ_B, AArch64_INS_NOT: not */ 0, { 0 } }, { /* AArch64_NOT_ZPmZ_D, AArch64_INS_NOT: not */ 0, { 0 } }, { /* AArch64_NOT_ZPmZ_H, AArch64_INS_NOT: not */ 0, { 0 } }, { /* AArch64_NOT_ZPmZ_S, AArch64_INS_NOT: not */ 0, { 0 } }, { /* AArch64_NOTv16i8, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_NOTv8i8, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ORNS_PPzPP, AArch64_INS_ORNS: orns */ 0, { 0 } }, { /* AArch64_ORNWrs, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORNXrs, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORN_PPzPP, AArch64_INS_ORN: orn */ 0, { 0 } }, { /* AArch64_ORNv16i8, AArch64_INS_ORN: orn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORNv8i8, AArch64_INS_ORN: orn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRS_PPzPP, AArch64_INS_MOVS: movs */ 0, { 0 } }, { /* AArch64_ORRWri, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRWrs, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRXri, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRXrs, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORR_PPzPP, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_ORR_ZI, AArch64_INS_ORN: orn */ 0, { 0 } }, { /* AArch64_ORR_ZPmZ_B, AArch64_INS_ORR: orr */ 0, { 0 } }, { /* AArch64_ORR_ZPmZ_D, AArch64_INS_ORR: orr */ 0, { 0 } }, { /* AArch64_ORR_ZPmZ_H, AArch64_INS_ORR: orr */ 0, { 0 } }, { /* AArch64_ORR_ZPmZ_S, AArch64_INS_ORR: orr */ 0, { 0 } }, { /* AArch64_ORR_ZZZ, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_ORRv16i8, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRv2i32, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRv4i16, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRv4i32, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRv8i16, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORRv8i8, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ORV_VPZ_B, AArch64_INS_ORV: orv */ 0, { 0 } }, { /* AArch64_ORV_VPZ_D, AArch64_INS_ORV: orv */ 0, { 0 } }, { /* AArch64_ORV_VPZ_H, AArch64_INS_ORV: orv */ 0, { 0 } }, { /* AArch64_ORV_VPZ_S, AArch64_INS_ORV: orv */ 0, { 0 } }, { /* AArch64_PACDA, AArch64_INS_PACDA: pacda */ 0, { 0 } }, { /* AArch64_PACDB, AArch64_INS_PACDB: pacdb */ 0, { 0 } }, { /* AArch64_PACDZA, AArch64_INS_PACDZA: pacdza */ 0, { 0 } }, { /* AArch64_PACDZB, AArch64_INS_PACDZB: pacdzb */ 0, { 0 } }, { /* AArch64_PACGA, AArch64_INS_PACGA: pacga */ 0, { 0 } }, { /* AArch64_PACIA, AArch64_INS_PACIA: pacia */ 0, { 0 } }, { /* AArch64_PACIA1716, AArch64_INS_PACIA1716: pacia1716 */ 0, { 0 } }, { /* AArch64_PACIASP, AArch64_INS_PACIASP: paciasp */ 0, { 0 } }, { /* AArch64_PACIAZ, AArch64_INS_PACIAZ: paciaz */ 0, { 0 } }, { /* AArch64_PACIB, AArch64_INS_PACIB: pacib */ 0, { 0 } }, { /* AArch64_PACIB1716, AArch64_INS_PACIB1716: pacib1716 */ 0, { 0 } }, { /* AArch64_PACIBSP, AArch64_INS_PACIBSP: pacibsp */ 0, { 0 } }, { /* AArch64_PACIBZ, AArch64_INS_PACIBZ: pacibz */ 0, { 0 } }, { /* AArch64_PACIZA, AArch64_INS_PACIZA: paciza */ 0, { 0 } }, { /* AArch64_PACIZB, AArch64_INS_PACIZB: pacizb */ 0, { 0 } }, { /* AArch64_PFALSE, AArch64_INS_PFALSE: pfalse */ 0, { 0 } }, { /* AArch64_PMULLv16i8, AArch64_INS_PMULL2: pmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_PMULLv1i64, AArch64_INS_PMULL: pmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_PMULLv2i64, AArch64_INS_PMULL2: pmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_PMULLv8i8, AArch64_INS_PMULL: pmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_PMULv16i8, AArch64_INS_PMUL: pmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_PMULv8i8, AArch64_INS_PMUL: pmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_PNEXT_B, AArch64_INS_PNEXT: pnext */ 0, { 0 } }, { /* AArch64_PNEXT_D, AArch64_INS_PNEXT: pnext */ 0, { 0 } }, { /* AArch64_PNEXT_H, AArch64_INS_PNEXT: pnext */ 0, { 0 } }, { /* AArch64_PNEXT_S, AArch64_INS_PNEXT: pnext */ 0, { 0 } }, { /* AArch64_PRFB_D_PZI, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_D_SCALED, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_D_SXTW_SCALED, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_D_UXTW_SCALED, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_PRI, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_PRR, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_S_PZI, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_S_SXTW_SCALED, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFB_S_UXTW_SCALED, AArch64_INS_PRFB: prfb */ 0, { 0 } }, { /* AArch64_PRFD_D_PZI, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_D_SCALED, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_D_SXTW_SCALED, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_D_UXTW_SCALED, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_PRI, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_PRR, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_S_PZI, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_S_SXTW_SCALED, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFD_S_UXTW_SCALED, AArch64_INS_PRFD: prfd */ 0, { 0 } }, { /* AArch64_PRFH_D_PZI, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_D_SCALED, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_D_SXTW_SCALED, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_D_UXTW_SCALED, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_PRI, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_PRR, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_S_PZI, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_S_SXTW_SCALED, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFH_S_UXTW_SCALED, AArch64_INS_PRFH: prfh */ 0, { 0 } }, { /* AArch64_PRFMl, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_PRFMroW, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_PRFMroX, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_PRFMui, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_PRFS_PRR, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFUMi, AArch64_INS_PRFUM: prfum */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_PRFW_D_PZI, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_D_SCALED, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_D_SXTW_SCALED, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_D_UXTW_SCALED, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_PRI, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_S_PZI, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_S_SXTW_SCALED, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PRFW_S_UXTW_SCALED, AArch64_INS_PRFW: prfw */ 0, { 0 } }, { /* AArch64_PTEST_PP, AArch64_INS_PTEST: ptest */ 0, { 0 } }, { /* AArch64_PTRUES_B, AArch64_INS_PTRUES: ptrues */ 0, { 0 } }, { /* AArch64_PTRUES_D, AArch64_INS_PTRUES: ptrues */ 0, { 0 } }, { /* AArch64_PTRUES_H, AArch64_INS_PTRUES: ptrues */ 0, { 0 } }, { /* AArch64_PTRUES_S, AArch64_INS_PTRUES: ptrues */ 0, { 0 } }, { /* AArch64_PTRUE_B, AArch64_INS_PTRUE: ptrue */ 0, { 0 } }, { /* AArch64_PTRUE_D, AArch64_INS_PTRUE: ptrue */ 0, { 0 } }, { /* AArch64_PTRUE_H, AArch64_INS_PTRUE: ptrue */ 0, { 0 } }, { /* AArch64_PTRUE_S, AArch64_INS_PTRUE: ptrue */ 0, { 0 } }, { /* AArch64_PUNPKHI_PP, AArch64_INS_PUNPKHI: punpkhi */ 0, { 0 } }, { /* AArch64_PUNPKLO_PP, AArch64_INS_PUNPKLO: punpklo */ 0, { 0 } }, { /* AArch64_RADDHNv2i64_v2i32, AArch64_INS_RADDHN: raddhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RADDHNv2i64_v4i32, AArch64_INS_RADDHN2: raddhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RADDHNv4i32_v4i16, AArch64_INS_RADDHN: raddhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RADDHNv4i32_v8i16, AArch64_INS_RADDHN2: raddhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RADDHNv8i16_v16i8, AArch64_INS_RADDHN2: raddhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RADDHNv8i16_v8i8, AArch64_INS_RADDHN: raddhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RAX1, AArch64_INS_RAX1: rax1 */ 0, { 0 } }, { /* AArch64_RBITWr, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_RBITXr, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_RBIT_ZPmZ_B, AArch64_INS_RBIT: rbit */ 0, { 0 } }, { /* AArch64_RBIT_ZPmZ_D, AArch64_INS_RBIT: rbit */ 0, { 0 } }, { /* AArch64_RBIT_ZPmZ_H, AArch64_INS_RBIT: rbit */ 0, { 0 } }, { /* AArch64_RBIT_ZPmZ_S, AArch64_INS_RBIT: rbit */ 0, { 0 } }, { /* AArch64_RBITv16i8, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_RBITv8i8, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_RDFFRS_PPz, AArch64_INS_RDFFRS: rdffrs */ 0, { 0 } }, { /* AArch64_RDFFR_P, AArch64_INS_RDFFR: rdffr */ 0, { 0 } }, { /* AArch64_RDFFR_PPz, AArch64_INS_RDFFR: rdffr */ 0, { 0 } }, { /* AArch64_RDVLI_XI, AArch64_INS_RDVL: rdvl */ 0, { 0 } }, { /* AArch64_RET, AArch64_INS_RET: ret */ 0, { CS_AC_READ, 0 } }, { /* AArch64_RETAA, AArch64_INS_RETAA: retaa */ 0, { 0 } }, { /* AArch64_RETAB, AArch64_INS_RETAB: retab */ 0, { 0 } }, { /* AArch64_REV16Wr, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV16Xr, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV16v16i8, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV16v8i8, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV32Xr, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV32v16i8, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV32v4i16, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV32v8i16, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV32v8i8, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV64v16i8, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV64v2i32, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV64v4i16, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV64v4i32, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV64v8i16, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV64v8i8, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REVB_ZPmZ_D, AArch64_INS_REVB: revb */ 0, { 0 } }, { /* AArch64_REVB_ZPmZ_H, AArch64_INS_REVB: revb */ 0, { 0 } }, { /* AArch64_REVB_ZPmZ_S, AArch64_INS_REVB: revb */ 0, { 0 } }, { /* AArch64_REVH_ZPmZ_D, AArch64_INS_REVH: revh */ 0, { 0 } }, { /* AArch64_REVH_ZPmZ_S, AArch64_INS_REVH: revh */ 0, { 0 } }, { /* AArch64_REVW_ZPmZ_D, AArch64_INS_REVW: revw */ 0, { 0 } }, { /* AArch64_REVWr, AArch64_INS_REV: rev */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REVXr, AArch64_INS_REV: rev */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_REV_PP_B, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_PP_D, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_PP_H, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_PP_S, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_ZZ_B, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_ZZ_D, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_ZZ_H, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_REV_ZZ_S, AArch64_INS_REV: rev */ 0, { 0 } }, { /* AArch64_RMIF, AArch64_INS_RMIF: rmif */ 0, { 0 } }, { /* AArch64_RORVWr, AArch64_INS_ROR: ror */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RORVXr, AArch64_INS_ROR: ror */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSHRNv16i8_shift, AArch64_INS_RSHRN2: rshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSHRNv2i32_shift, AArch64_INS_RSHRN: rshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSHRNv4i16_shift, AArch64_INS_RSHRN: rshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSHRNv4i32_shift, AArch64_INS_RSHRN2: rshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSHRNv8i16_shift, AArch64_INS_RSHRN2: rshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSHRNv8i8_shift, AArch64_INS_RSHRN: rshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSUBHNv2i64_v2i32, AArch64_INS_RSUBHN: rsubhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSUBHNv2i64_v4i32, AArch64_INS_RSUBHN2: rsubhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSUBHNv4i32_v4i16, AArch64_INS_RSUBHN: rsubhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSUBHNv4i32_v8i16, AArch64_INS_RSUBHN2: rsubhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSUBHNv8i16_v16i8, AArch64_INS_RSUBHN2: rsubhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_RSUBHNv8i16_v8i8, AArch64_INS_RSUBHN: rsubhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABALv16i8_v8i16, AArch64_INS_SABAL2: sabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABALv2i32_v2i64, AArch64_INS_SABAL: sabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABALv4i16_v4i32, AArch64_INS_SABAL: sabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABALv4i32_v2i64, AArch64_INS_SABAL2: sabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABALv8i16_v4i32, AArch64_INS_SABAL2: sabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABALv8i8_v8i16, AArch64_INS_SABAL: sabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABAv16i8, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABAv2i32, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABAv4i16, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABAv4i32, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABAv8i16, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABAv8i8, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDLv16i8_v8i16, AArch64_INS_SABDL2: sabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDLv2i32_v2i64, AArch64_INS_SABDL: sabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDLv4i16_v4i32, AArch64_INS_SABDL: sabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDLv4i32_v2i64, AArch64_INS_SABDL2: sabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDLv8i16_v4i32, AArch64_INS_SABDL2: sabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDLv8i8_v8i16, AArch64_INS_SABDL: sabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABD_ZPmZ_B, AArch64_INS_SABD: sabd */ 0, { 0 } }, { /* AArch64_SABD_ZPmZ_D, AArch64_INS_SABD: sabd */ 0, { 0 } }, { /* AArch64_SABD_ZPmZ_H, AArch64_INS_SABD: sabd */ 0, { 0 } }, { /* AArch64_SABD_ZPmZ_S, AArch64_INS_SABD: sabd */ 0, { 0 } }, { /* AArch64_SABDv16i8, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDv2i32, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDv4i16, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDv4i32, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDv8i16, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SABDv8i8, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADALPv16i8_v8i16, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADALPv2i32_v1i64, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADALPv4i16_v2i32, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADALPv4i32_v2i64, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADALPv8i16_v4i32, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADALPv8i8_v4i16, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLPv16i8_v8i16, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLPv2i32_v1i64, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLPv4i16_v2i32, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLPv4i32_v2i64, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLPv8i16_v4i32, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLPv8i8_v4i16, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLVv16i8v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SADDLVv4i16v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SADDLVv4i32v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SADDLVv8i16v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SADDLVv8i8v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SADDLv16i8_v8i16, AArch64_INS_SADDL2: saddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLv2i32_v2i64, AArch64_INS_SADDL: saddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLv4i16_v4i32, AArch64_INS_SADDL: saddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLv4i32_v2i64, AArch64_INS_SADDL2: saddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLv8i16_v4i32, AArch64_INS_SADDL2: saddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDLv8i8_v8i16, AArch64_INS_SADDL: saddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDV_VPZ_B, AArch64_INS_SADDV: saddv */ 0, { 0 } }, { /* AArch64_SADDV_VPZ_H, AArch64_INS_SADDV: saddv */ 0, { 0 } }, { /* AArch64_SADDV_VPZ_S, AArch64_INS_SADDV: saddv */ 0, { 0 } }, { /* AArch64_SADDWv16i8_v8i16, AArch64_INS_SADDW2: saddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDWv2i32_v2i64, AArch64_INS_SADDW: saddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDWv4i16_v4i32, AArch64_INS_SADDW: saddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDWv4i32_v2i64, AArch64_INS_SADDW2: saddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDWv8i16_v4i32, AArch64_INS_SADDW2: saddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SADDWv8i8_v8i16, AArch64_INS_SADDW: saddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SBCSWr, AArch64_INS_NGCS: ngcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SBCSXr, AArch64_INS_NGCS: ngcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SBCWr, AArch64_INS_NGC: ngc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SBCXr, AArch64_INS_NGC: ngc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SBFMWri, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SBFMXri, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SCVTFSWDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFSWHri, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFSWSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFSXDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFSXHri, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFSXSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFUWDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFUWHri, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFUWSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFUXDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFUXHri, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFUXSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTF_ZPmZ_DtoD, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTF_ZPmZ_DtoH, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTF_ZPmZ_DtoS, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTF_ZPmZ_HtoH, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTF_ZPmZ_StoD, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTF_ZPmZ_StoH, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTF_ZPmZ_StoS, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFd, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFh, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFs, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFv1i16, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFv1i32, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFv1i64, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFv2f32, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFv2f64, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFv2i32_shift, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFv2i64_shift, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFv4f16, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFv4f32, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, { /* AArch64_SCVTFv4i16_shift, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFv4i32_shift, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SCVTFv8f16, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SCVTFv8i16_shift, AArch64_INS_SCVTF: scvtf */ 0, { 0 } }, { /* AArch64_SDIVR_ZPmZ_D, AArch64_INS_SDIVR: sdivr */ 0, { 0 } }, { /* AArch64_SDIVR_ZPmZ_S, AArch64_INS_SDIVR: sdivr */ 0, { 0 } }, { /* AArch64_SDIVWr, AArch64_INS_SDIV: sdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SDIVXr, AArch64_INS_SDIV: sdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SDIV_ZPmZ_D, AArch64_INS_SDIV: sdiv */ 0, { 0 } }, { /* AArch64_SDIV_ZPmZ_S, AArch64_INS_SDIV: sdiv */ 0, { 0 } }, { /* AArch64_SDOT_ZZZI_D, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOT_ZZZI_S, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOT_ZZZ_D, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOT_ZZZ_S, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOTlanev16i8, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOTlanev8i8, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOTv16i8, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SDOTv8i8, AArch64_INS_SDOT: sdot */ 0, { 0 } }, { /* AArch64_SEL_PPPP, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_SEL_ZPZZ_B, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_SEL_ZPZZ_D, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_SEL_ZPZZ_H, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_SEL_ZPZZ_S, AArch64_INS_MOV: mov */ 0, { 0 } }, { /* AArch64_SETF16, AArch64_INS_SETF16: setf16 */ 0, { 0 } }, { /* AArch64_SETF8, AArch64_INS_SETF8: setf8 */ 0, { 0 } }, { /* AArch64_SETFFR, AArch64_INS_SETFFR: setffr */ 0, { 0 } }, { /* AArch64_SHA1Crrr, AArch64_INS_SHA1C: sha1c */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA1Hrr, AArch64_INS_SHA1H: sha1h */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SHA1Mrrr, AArch64_INS_SHA1M: sha1m */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA1Prrr, AArch64_INS_SHA1P: sha1p */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA1SU0rrr, AArch64_INS_SHA1SU0: sha1su0 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA1SU1rr, AArch64_INS_SHA1SU1: sha1su1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA256H2rrr, AArch64_INS_SHA256H2: sha256h2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA256Hrrr, AArch64_INS_SHA256H: sha256h */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA256SU0rr, AArch64_INS_SHA256SU0: sha256su0 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA256SU1rrr, AArch64_INS_SHA256SU1: sha256su1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SHA512H, AArch64_INS_SHA512H: sha512h */ 0, { 0 } }, { /* AArch64_SHA512H2, AArch64_INS_SHA512H2: sha512h2 */ 0, { 0 } }, { /* AArch64_SHA512SU0, AArch64_INS_SHA512SU0: sha512su0 */ 0, { 0 } }, { /* AArch64_SHA512SU1, AArch64_INS_SHA512SU1: sha512su1 */ 0, { 0 } }, { /* AArch64_SHADDv16i8, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHADDv2i32, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHADDv4i16, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHADDv4i32, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHADDv8i16, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHADDv8i8, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLLv16i8, AArch64_INS_SHLL2: shll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLLv2i32, AArch64_INS_SHLL: shll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLLv4i16, AArch64_INS_SHLL: shll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLLv4i32, AArch64_INS_SHLL2: shll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLLv8i16, AArch64_INS_SHLL2: shll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLLv8i8, AArch64_INS_SHLL: shll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLd, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv16i8_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv2i32_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv2i64_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv4i16_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv4i32_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv8i16_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHLv8i8_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHRNv16i8_shift, AArch64_INS_SHRN2: shrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHRNv2i32_shift, AArch64_INS_SHRN: shrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHRNv4i16_shift, AArch64_INS_SHRN: shrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHRNv4i32_shift, AArch64_INS_SHRN2: shrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHRNv8i16_shift, AArch64_INS_SHRN2: shrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHRNv8i8_shift, AArch64_INS_SHRN: shrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHSUBv16i8, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHSUBv2i32, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHSUBv4i16, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHSUBv4i32, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHSUBv8i16, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SHSUBv8i8, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLId, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv16i8_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv2i32_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv2i64_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv4i16_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv4i32_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv8i16_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SLIv8i8_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, { /* AArch64_SM3PARTW1, AArch64_INS_SM3PARTW1: sm3partw1 */ 0, { 0 } }, { /* AArch64_SM3PARTW2, AArch64_INS_SM3PARTW2: sm3partw2 */ 0, { 0 } }, { /* AArch64_SM3SS1, AArch64_INS_SM3SS1: sm3ss1 */ 0, { 0 } }, { /* AArch64_SM3TT1A, AArch64_INS_SM3TT1A: sm3tt1a */ 0, { 0 } }, { /* AArch64_SM3TT1B, AArch64_INS_SM3TT1B: sm3tt1b */ 0, { 0 } }, { /* AArch64_SM3TT2A, AArch64_INS_SM3TT2A: sm3tt2a */ 0, { 0 } }, { /* AArch64_SM3TT2B, AArch64_INS_SM3TT2B: sm3tt2b */ 0, { 0 } }, { /* AArch64_SM4E, AArch64_INS_SM4E: sm4e */ 0, { 0 } }, { /* AArch64_SM4ENCKEY, AArch64_INS_SM4EKEY: sm4ekey */ 0, { 0 } }, { /* AArch64_SMADDLrrr, AArch64_INS_SMADDL: smaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXPv16i8, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXPv2i32, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXPv4i16, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXPv4i32, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXPv8i16, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXPv8i8, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXV_VPZ_B, AArch64_INS_SMAXV: smaxv */ 0, { 0 } }, { /* AArch64_SMAXV_VPZ_D, AArch64_INS_SMAXV: smaxv */ 0, { 0 } }, { /* AArch64_SMAXV_VPZ_H, AArch64_INS_SMAXV: smaxv */ 0, { 0 } }, { /* AArch64_SMAXV_VPZ_S, AArch64_INS_SMAXV: smaxv */ 0, { 0 } }, { /* AArch64_SMAXVv16i8v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMAXVv4i16v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMAXVv4i32v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMAXVv8i16v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMAXVv8i8v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMAX_ZI_B, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZI_D, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZI_H, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZI_S, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZPmZ_B, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZPmZ_D, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZPmZ_H, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAX_ZPmZ_S, AArch64_INS_SMAX: smax */ 0, { 0 } }, { /* AArch64_SMAXv16i8, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXv2i32, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXv4i16, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXv4i32, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXv8i16, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMAXv8i8, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMC, AArch64_INS_SMC: smc */ 0, { CS_AC_READ, 0 } }, { /* AArch64_SMINPv16i8, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINPv2i32, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINPv4i16, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINPv4i32, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINPv8i16, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINPv8i8, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINV_VPZ_B, AArch64_INS_SMINV: sminv */ 0, { 0 } }, { /* AArch64_SMINV_VPZ_D, AArch64_INS_SMINV: sminv */ 0, { 0 } }, { /* AArch64_SMINV_VPZ_H, AArch64_INS_SMINV: sminv */ 0, { 0 } }, { /* AArch64_SMINV_VPZ_S, AArch64_INS_SMINV: sminv */ 0, { 0 } }, { /* AArch64_SMINVv16i8v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMINVv4i16v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMINVv4i32v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMINVv8i16v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMINVv8i8v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SMIN_ZI_B, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZI_D, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZI_H, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZI_S, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZPmZ_B, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZPmZ_D, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZPmZ_H, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMIN_ZPmZ_S, AArch64_INS_SMIN: smin */ 0, { 0 } }, { /* AArch64_SMINv16i8, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINv2i32, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINv4i16, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINv4i32, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINv8i16, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMINv8i8, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLALv16i8_v8i16, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLALv2i32_indexed, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLALv2i32_v2i64, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLALv4i16_indexed, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLALv4i16_v4i32, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLALv4i32_indexed, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLALv4i32_v2i64, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLALv8i16_indexed, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLALv8i16_v4i32, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLALv8i8_v8i16, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLSLv16i8_v8i16, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLSLv2i32_indexed, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLSLv2i32_v2i64, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLSLv4i16_indexed, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLSLv4i16_v4i32, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLSLv4i32_indexed, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLSLv4i32_v2i64, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLSLv8i16_indexed, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SMLSLv8i16_v4i32, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMLSLv8i8_v8i16, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMOVvi16to32, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMOVvi16to64, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMOVvi32to64, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMOVvi8to32, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMOVvi8to64, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMSUBLrrr, AArch64_INS_SMNEGL: smnegl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULH_ZPmZ_B, AArch64_INS_SMULH: smulh */ 0, { 0 } }, { /* AArch64_SMULH_ZPmZ_D, AArch64_INS_SMULH: smulh */ 0, { 0 } }, { /* AArch64_SMULH_ZPmZ_H, AArch64_INS_SMULH: smulh */ 0, { 0 } }, { /* AArch64_SMULH_ZPmZ_S, AArch64_INS_SMULH: smulh */ 0, { 0 } }, { /* AArch64_SMULHrr, AArch64_INS_SMULH: smulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv16i8_v8i16, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv2i32_indexed, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv2i32_v2i64, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv4i16_indexed, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv4i16_v4i32, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv4i32_indexed, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv4i32_v2i64, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv8i16_indexed, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv8i16_v4i32, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SMULLv8i8_v8i16, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SPLICE_ZPZ_B, AArch64_INS_SPLICE: splice */ 0, { 0 } }, { /* AArch64_SPLICE_ZPZ_D, AArch64_INS_SPLICE: splice */ 0, { 0 } }, { /* AArch64_SPLICE_ZPZ_H, AArch64_INS_SPLICE: splice */ 0, { 0 } }, { /* AArch64_SPLICE_ZPZ_S, AArch64_INS_SPLICE: splice */ 0, { 0 } }, { /* AArch64_SQABSv16i8, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv1i16, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv1i32, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv1i64, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv1i8, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv2i32, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv2i64, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv4i16, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv4i32, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv8i16, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQABSv8i8, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQADD_ZI_B, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZI_D, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZI_H, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZI_S, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZZZ_B, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZZZ_D, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZZZ_H, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADD_ZZZ_S, AArch64_INS_SQADD: sqadd */ 0, { 0 } }, { /* AArch64_SQADDv16i8, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv1i16, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv1i32, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv1i64, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv1i8, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv2i32, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv2i64, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv4i16, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv4i32, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv8i16, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQADDv8i8, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDECB_XPiI, AArch64_INS_SQDECB: sqdecb */ 0, { 0 } }, { /* AArch64_SQDECB_XPiWdI, AArch64_INS_SQDECB: sqdecb */ 0, { 0 } }, { /* AArch64_SQDECD_XPiI, AArch64_INS_SQDECD: sqdecd */ 0, { 0 } }, { /* AArch64_SQDECD_XPiWdI, AArch64_INS_SQDECD: sqdecd */ 0, { 0 } }, { /* AArch64_SQDECD_ZPiI, AArch64_INS_SQDECD: sqdecd */ 0, { 0 } }, { /* AArch64_SQDECH_XPiI, AArch64_INS_SQDECH: sqdech */ 0, { 0 } }, { /* AArch64_SQDECH_XPiWdI, AArch64_INS_SQDECH: sqdech */ 0, { 0 } }, { /* AArch64_SQDECH_ZPiI, AArch64_INS_SQDECH: sqdech */ 0, { 0 } }, { /* AArch64_SQDECP_XPWd_B, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XPWd_D, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XPWd_H, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XPWd_S, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XP_B, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XP_D, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XP_H, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_XP_S, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_ZP_D, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_ZP_H, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECP_ZP_S, AArch64_INS_SQDECP: sqdecp */ 0, { 0 } }, { /* AArch64_SQDECW_XPiI, AArch64_INS_SQDECW: sqdecw */ 0, { 0 } }, { /* AArch64_SQDECW_XPiWdI, AArch64_INS_SQDECW: sqdecw */ 0, { 0 } }, { /* AArch64_SQDECW_ZPiI, AArch64_INS_SQDECW: sqdecw */ 0, { 0 } }, { /* AArch64_SQDMLALi16, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLALi32, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLALv1i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLALv1i64_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLALv2i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLALv2i32_v2i64, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLALv4i16_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLALv4i16_v4i32, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLALv4i32_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLALv4i32_v2i64, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLALv8i16_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLALv8i16_v4i32, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLSLi16, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLSLi32, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLSLv1i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLSLv1i64_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLSLv2i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLSLv2i32_v2i64, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLSLv4i16_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLSLv4i16_v4i32, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLSLv4i32_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLSLv4i32_v2i64, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMLSLv8i16_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQDMLSLv8i16_v4i32, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv1i16, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv1i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv1i32, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv1i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv2i32, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv2i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv4i16, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv4i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv4i32, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv4i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv8i16, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULHv8i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLi16, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLi32, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv1i32_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv1i64_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv2i32_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv2i32_v2i64, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv4i16_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv4i16_v4i32, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv4i32_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv4i32_v2i64, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv8i16_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQDMULLv8i16_v4i32, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQINCB_XPiI, AArch64_INS_SQINCB: sqincb */ 0, { 0 } }, { /* AArch64_SQINCB_XPiWdI, AArch64_INS_SQINCB: sqincb */ 0, { 0 } }, { /* AArch64_SQINCD_XPiI, AArch64_INS_SQINCD: sqincd */ 0, { 0 } }, { /* AArch64_SQINCD_XPiWdI, AArch64_INS_SQINCD: sqincd */ 0, { 0 } }, { /* AArch64_SQINCD_ZPiI, AArch64_INS_SQINCD: sqincd */ 0, { 0 } }, { /* AArch64_SQINCH_XPiI, AArch64_INS_SQINCH: sqinch */ 0, { 0 } }, { /* AArch64_SQINCH_XPiWdI, AArch64_INS_SQINCH: sqinch */ 0, { 0 } }, { /* AArch64_SQINCH_ZPiI, AArch64_INS_SQINCH: sqinch */ 0, { 0 } }, { /* AArch64_SQINCP_XPWd_B, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XPWd_D, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XPWd_H, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XPWd_S, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XP_B, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XP_D, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XP_H, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_XP_S, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_ZP_D, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_ZP_H, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCP_ZP_S, AArch64_INS_SQINCP: sqincp */ 0, { 0 } }, { /* AArch64_SQINCW_XPiI, AArch64_INS_SQINCW: sqincw */ 0, { 0 } }, { /* AArch64_SQINCW_XPiWdI, AArch64_INS_SQINCW: sqincw */ 0, { 0 } }, { /* AArch64_SQINCW_ZPiI, AArch64_INS_SQINCW: sqincw */ 0, { 0 } }, { /* AArch64_SQNEGv16i8, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv1i16, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv1i32, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv1i64, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv1i8, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv2i32, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv2i64, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv4i16, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv4i32, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv8i16, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQNEGv8i8, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQRDMLAHi16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHi32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv1i16, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv1i32, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv2i32, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv2i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv4i16, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv4i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv4i32, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv4i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv8i16, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLAHv8i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ 0, { 0 } }, { /* AArch64_SQRDMLSHi16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHi32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv1i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv1i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv2i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv2i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv4i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv4i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv4i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv4i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv8i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMLSHv8i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ 0, { 0 } }, { /* AArch64_SQRDMULHv1i16, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRDMULHv1i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQRDMULHv1i32, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRDMULHv1i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQRDMULHv2i32, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRDMULHv2i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQRDMULHv4i16, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRDMULHv4i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQRDMULHv4i32, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRDMULHv4i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQRDMULHv8i16, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRDMULHv8i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SQRSHLv16i8, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv1i16, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv1i32, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv1i64, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv1i8, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv2i32, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv2i64, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv4i16, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv4i32, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv8i16, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHLv8i8, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNb, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNh, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNs, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNv16i8_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNv2i32_shift, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNv4i16_shift, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNv4i32_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNv8i16_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRNv8i8_shift, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNb, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNh, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNs, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNv16i8_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNv2i32_shift, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNv4i16_shift, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNv4i32_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNv8i16_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQRSHRUNv8i8_shift, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUb, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUd, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUh, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUs, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv16i8_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv2i32_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv2i64_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv4i16_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv4i32_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv8i16_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLUv8i8_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLb, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLd, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLh, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLs, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv16i8, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv16i8_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv1i16, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv1i32, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv1i64, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv1i8, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv2i32, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv2i32_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv2i64, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv2i64_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv4i16, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv4i16_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv4i32, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv4i32_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv8i16, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv8i16_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv8i8, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHLv8i8_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNb, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNh, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNs, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNv16i8_shift, AArch64_INS_SQSHRN2: sqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNv2i32_shift, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNv4i16_shift, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNv4i32_shift, AArch64_INS_SQSHRN2: sqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNv8i16_shift, AArch64_INS_SQSHRN2: sqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRNv8i8_shift, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNb, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNh, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNs, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNv16i8_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNv2i32_shift, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNv4i16_shift, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNv4i32_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNv8i16_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSHRUNv8i8_shift, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUB_ZI_B, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZI_D, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZI_H, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZI_S, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZZZ_B, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZZZ_D, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZZZ_H, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUB_ZZZ_S, AArch64_INS_SQSUB: sqsub */ 0, { 0 } }, { /* AArch64_SQSUBv16i8, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv1i16, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv1i32, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv1i64, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv1i8, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv2i32, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv2i64, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv4i16, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv4i32, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv8i16, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQSUBv8i8, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv16i8, AArch64_INS_SQXTN2: sqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv1i16, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv1i32, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv1i8, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv2i32, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv4i16, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv4i32, AArch64_INS_SQXTN2: sqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv8i16, AArch64_INS_SQXTN2: sqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTNv8i8, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv16i8, AArch64_INS_SQXTUN2: sqxtun2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv1i16, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv1i32, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv1i8, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv2i32, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv4i16, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv4i32, AArch64_INS_SQXTUN2: sqxtun2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv8i16, AArch64_INS_SQXTUN2: sqxtun2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SQXTUNv8i8, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_SRHADDv16i8, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRHADDv2i32, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRHADDv4i16, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRHADDv4i32, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRHADDv8i16, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRHADDv8i8, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRId, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv16i8_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv2i32_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv2i64_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv4i16_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv4i32_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv8i16_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRIv8i8_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv16i8, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv1i64, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv2i32, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv2i64, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv4i16, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv4i32, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv8i16, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHLv8i8, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRd, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv16i8_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv2i32_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv2i64_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv4i16_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv4i32_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv8i16_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSHRv8i8_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAd, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv16i8_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv2i32_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv2i64_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv4i16_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv4i32_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv8i16_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SRSRAv8i8_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLLv16i8_shift, AArch64_INS_SSHLL2: sshll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLLv2i32_shift, AArch64_INS_SSHLL: sshll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLLv4i16_shift, AArch64_INS_SSHLL: sshll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLLv4i32_shift, AArch64_INS_SSHLL2: sshll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLLv8i16_shift, AArch64_INS_SSHLL2: sshll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLLv8i8_shift, AArch64_INS_SSHLL: sshll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv16i8, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv1i64, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv2i32, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv2i64, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv4i16, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv4i32, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv8i16, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHLv8i8, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRd, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv16i8_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv2i32_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv2i64_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv4i16_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv4i32_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv8i16_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSHRv8i8_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAd, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv16i8_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv2i32_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv2i64_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv4i16_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv4i32_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv8i16_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSRAv8i8_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SST1B_D, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1B_D_IMM, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1B_D_SXTW, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1B_D_UXTW, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1B_S_IMM, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1B_S_SXTW, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1B_S_UXTW, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_SST1D, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1D_IMM, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1D_SCALED, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1D_SXTW, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1D_SXTW_SCALED, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1D_UXTW, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1D_UXTW_SCALED, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_SST1H_D, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_D_IMM, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_D_SCALED, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_D_SXTW, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_D_SXTW_SCALED, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_D_UXTW, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_D_UXTW_SCALED, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_S_IMM, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_S_SXTW, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_S_SXTW_SCALED, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_S_UXTW, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1H_S_UXTW_SCALED, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_SST1W_D, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_D_IMM, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_D_SCALED, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_D_SXTW, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_D_SXTW_SCALED, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_D_UXTW, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_D_UXTW_SCALED, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_IMM, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_SXTW, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_SXTW_SCALED, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_UXTW, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SST1W_UXTW_SCALED, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_SSUBLv16i8_v8i16, AArch64_INS_SSUBL2: ssubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBLv2i32_v2i64, AArch64_INS_SSUBL: ssubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBLv4i16_v4i32, AArch64_INS_SSUBL: ssubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBLv4i32_v2i64, AArch64_INS_SSUBL2: ssubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBLv8i16_v4i32, AArch64_INS_SSUBL2: ssubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBLv8i8_v8i16, AArch64_INS_SSUBL: ssubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBWv16i8_v8i16, AArch64_INS_SSUBW2: ssubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBWv2i32_v2i64, AArch64_INS_SSUBW: ssubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBWv4i16_v4i32, AArch64_INS_SSUBW: ssubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBWv4i32_v2i64, AArch64_INS_SSUBW2: ssubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBWv8i16_v4i32, AArch64_INS_SSUBW2: ssubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SSUBWv8i8_v8i16, AArch64_INS_SSUBW: ssubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1B, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_D, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_D_IMM, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_H, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_H_IMM, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_IMM, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_S, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1B_S_IMM, AArch64_INS_ST1B: st1b */ 0, { 0 } }, { /* AArch64_ST1D, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_ST1D_IMM, AArch64_INS_ST1D: st1d */ 0, { 0 } }, { /* AArch64_ST1Fourv16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Fourv8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1H, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_ST1H_D, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_ST1H_D_IMM, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_ST1H_IMM, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_ST1H_S, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_ST1H_S_IMM, AArch64_INS_ST1H: st1h */ 0, { 0 } }, { /* AArch64_ST1Onev16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Onev8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Onev8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Threev8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Threev8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1Twov8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1Twov8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1W, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_ST1W_D, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_ST1W_D_IMM, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_ST1W_IMM, AArch64_INS_ST1W: st1w */ 0, { 0 } }, { /* AArch64_ST1i16, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1i16_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1i32, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1i32_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1i64, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1i64_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST1i8, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST1i8_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2B, AArch64_INS_ST2B: st2b */ 0, { 0 } }, { /* AArch64_ST2B_IMM, AArch64_INS_ST2B: st2b */ 0, { 0 } }, { /* AArch64_ST2D, AArch64_INS_ST2D: st2d */ 0, { 0 } }, { /* AArch64_ST2D_IMM, AArch64_INS_ST2D: st2d */ 0, { 0 } }, { /* AArch64_ST2H, AArch64_INS_ST2H: st2h */ 0, { 0 } }, { /* AArch64_ST2H_IMM, AArch64_INS_ST2H: st2h */ 0, { 0 } }, { /* AArch64_ST2Twov16b, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov16b_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2Twov2d, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov2d_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2Twov2s, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov2s_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2Twov4h, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov4h_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2Twov4s, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov4s_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2Twov8b, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov8b_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2Twov8h, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2Twov8h_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2W, AArch64_INS_ST2W: st2w */ 0, { 0 } }, { /* AArch64_ST2W_IMM, AArch64_INS_ST2W: st2w */ 0, { 0 } }, { /* AArch64_ST2i16, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2i16_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2i32, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2i32_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2i64, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2i64_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST2i8, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST2i8_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3B, AArch64_INS_ST3B: st3b */ 0, { 0 } }, { /* AArch64_ST3B_IMM, AArch64_INS_ST3B: st3b */ 0, { 0 } }, { /* AArch64_ST3D, AArch64_INS_ST3D: st3d */ 0, { 0 } }, { /* AArch64_ST3D_IMM, AArch64_INS_ST3D: st3d */ 0, { 0 } }, { /* AArch64_ST3H, AArch64_INS_ST3H: st3h */ 0, { 0 } }, { /* AArch64_ST3H_IMM, AArch64_INS_ST3H: st3h */ 0, { 0 } }, { /* AArch64_ST3Threev16b, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev16b_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3Threev2d, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev2d_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3Threev2s, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev2s_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3Threev4h, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev4h_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3Threev4s, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev4s_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3Threev8b, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev8b_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3Threev8h, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3Threev8h_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3W, AArch64_INS_ST3W: st3w */ 0, { 0 } }, { /* AArch64_ST3W_IMM, AArch64_INS_ST3W: st3w */ 0, { 0 } }, { /* AArch64_ST3i16, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3i16_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3i32, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3i32_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3i64, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3i64_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST3i8, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST3i8_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4B, AArch64_INS_ST4B: st4b */ 0, { 0 } }, { /* AArch64_ST4B_IMM, AArch64_INS_ST4B: st4b */ 0, { 0 } }, { /* AArch64_ST4D, AArch64_INS_ST4D: st4d */ 0, { 0 } }, { /* AArch64_ST4D_IMM, AArch64_INS_ST4D: st4d */ 0, { 0 } }, { /* AArch64_ST4Fourv16b, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv16b_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv2d, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv2d_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv2s, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv2s_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv4h, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv4h_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv4s, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv4s_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv8b, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv8b_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv8h, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4Fourv8h_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4H, AArch64_INS_ST4H: st4h */ 0, { 0 } }, { /* AArch64_ST4H_IMM, AArch64_INS_ST4H: st4h */ 0, { 0 } }, { /* AArch64_ST4W, AArch64_INS_ST4W: st4w */ 0, { 0 } }, { /* AArch64_ST4W_IMM, AArch64_INS_ST4W: st4w */ 0, { 0 } }, { /* AArch64_ST4i16, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4i16_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4i32, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4i32_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4i64, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4i64_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ST4i8, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, { /* AArch64_ST4i8_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLLRB, AArch64_INS_STLLRB: stllrb */ 0, { 0 } }, { /* AArch64_STLLRH, AArch64_INS_STLLRH: stllrh */ 0, { 0 } }, { /* AArch64_STLLRW, AArch64_INS_STLLR: stllr */ 0, { 0 } }, { /* AArch64_STLLRX, AArch64_INS_STLLR: stllr */ 0, { 0 } }, { /* AArch64_STLRB, AArch64_INS_STLRB: stlrb */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLRH, AArch64_INS_STLRH: stlrh */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLRW, AArch64_INS_STLR: stlr */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLRX, AArch64_INS_STLR: stlr */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLURBi, AArch64_INS_STLURB: stlurb */ 0, { 0 } }, { /* AArch64_STLURHi, AArch64_INS_STLURH: stlurh */ 0, { 0 } }, { /* AArch64_STLURWi, AArch64_INS_STLUR: stlur */ 0, { 0 } }, { /* AArch64_STLURXi, AArch64_INS_STLUR: stlur */ 0, { 0 } }, { /* AArch64_STLXPW, AArch64_INS_STLXP: stlxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLXPX, AArch64_INS_STLXP: stlxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLXRB, AArch64_INS_STLXRB: stlxrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLXRH, AArch64_INS_STLXRH: stlxrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLXRW, AArch64_INS_STLXR: stlxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STLXRX, AArch64_INS_STLXR: stlxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STNPDi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STNPQi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STNPSi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STNPWi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STNPXi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STNT1B_ZRI, AArch64_INS_STNT1B: stnt1b */ 0, { 0 } }, { /* AArch64_STNT1B_ZRR, AArch64_INS_STNT1B: stnt1b */ 0, { 0 } }, { /* AArch64_STNT1D_ZRI, AArch64_INS_STNT1D: stnt1d */ 0, { 0 } }, { /* AArch64_STNT1D_ZRR, AArch64_INS_STNT1D: stnt1d */ 0, { 0 } }, { /* AArch64_STNT1H_ZRI, AArch64_INS_STNT1H: stnt1h */ 0, { 0 } }, { /* AArch64_STNT1H_ZRR, AArch64_INS_STNT1H: stnt1h */ 0, { 0 } }, { /* AArch64_STNT1W_ZRI, AArch64_INS_STNT1W: stnt1w */ 0, { 0 } }, { /* AArch64_STNT1W_ZRR, AArch64_INS_STNT1W: stnt1w */ 0, { 0 } }, { /* AArch64_STPDi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPDpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPDpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPQi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPQpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPQpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPSi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPSpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPSpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPWi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPWpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPWpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPXi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPXpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STPXpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRBBpost, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRBBpre, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRBBroW, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRBBroX, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRBBui, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRBpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRBpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRBroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRBroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRBui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRDpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRDpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRDroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRDroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRDui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRHHpost, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRHHpre, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRHHroW, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRHHroX, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRHHui, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRHpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRHpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRHroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRHroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRHui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRQpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRQpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRQroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRQroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRQui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRSpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRSpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRSroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRSroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRSui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRWpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRWpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRWroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRWroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRWui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRXpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRXpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STRXroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRXroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STRXui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STR_PXI, AArch64_INS_STR: str */ 0, { 0 } }, { /* AArch64_STR_ZXI, AArch64_INS_STR: str */ 0, { 0 } }, { /* AArch64_STTRBi, AArch64_INS_STTRB: sttrb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STTRHi, AArch64_INS_STTRH: sttrh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STTRWi, AArch64_INS_STTR: sttr */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STTRXi, AArch64_INS_STTR: sttr */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURBBi, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURBi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURDi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURHHi, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURHi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURQi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURSi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURWi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STURXi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STXPW, AArch64_INS_STXP: stxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STXPX, AArch64_INS_STXP: stxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_STXRB, AArch64_INS_STXRB: stxrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STXRH, AArch64_INS_STXRH: stxrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STXRW, AArch64_INS_STXR: stxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_STXRX, AArch64_INS_STXR: stxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBHNv2i64_v2i32, AArch64_INS_SUBHN: subhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBHNv2i64_v4i32, AArch64_INS_SUBHN2: subhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBHNv4i32_v4i16, AArch64_INS_SUBHN: subhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBHNv4i32_v8i16, AArch64_INS_SUBHN2: subhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBHNv8i16_v16i8, AArch64_INS_SUBHN2: subhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBHNv8i16_v8i8, AArch64_INS_SUBHN: subhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBR_ZI_B, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZI_D, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZI_H, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZI_S, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZPmZ_B, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZPmZ_D, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZPmZ_H, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBR_ZPmZ_S, AArch64_INS_SUBR: subr */ 0, { 0 } }, { /* AArch64_SUBSWri, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBSWrs, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBSWrx, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBSXri, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBSXrs, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBSXrx, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBSXrx64, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SUBWri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBWrs, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBWrx, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBXri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBXrs, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBXrx, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBXrx64, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SUB_ZI_B, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZI_D, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZI_H, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZI_S, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZPmZ_B, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZPmZ_D, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZPmZ_H, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZPmZ_S, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZZZ_B, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZZZ_D, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZZZ_H, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUB_ZZZ_S, AArch64_INS_SUB: sub */ 0, { 0 } }, { /* AArch64_SUBv16i8, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv1i64, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv2i32, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv2i64, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv4i16, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv4i32, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv8i16, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUBv8i8, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUNPKHI_ZZ_D, AArch64_INS_SUNPKHI: sunpkhi */ 0, { 0 } }, { /* AArch64_SUNPKHI_ZZ_H, AArch64_INS_SUNPKHI: sunpkhi */ 0, { 0 } }, { /* AArch64_SUNPKHI_ZZ_S, AArch64_INS_SUNPKHI: sunpkhi */ 0, { 0 } }, { /* AArch64_SUNPKLO_ZZ_D, AArch64_INS_SUNPKLO: sunpklo */ 0, { 0 } }, { /* AArch64_SUNPKLO_ZZ_H, AArch64_INS_SUNPKLO: sunpklo */ 0, { 0 } }, { /* AArch64_SUNPKLO_ZZ_S, AArch64_INS_SUNPKLO: sunpklo */ 0, { 0 } }, { /* AArch64_SUQADDv16i8, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv1i16, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv1i32, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv1i64, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv1i8, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv2i32, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv2i64, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv4i16, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv4i32, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv8i16, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SUQADDv8i8, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_SVC, AArch64_INS_SVC: svc */ 0, { CS_AC_READ, 0 } }, { /* AArch64_SWPAB, AArch64_INS_SWPAB: swpab */ 0, { 0 } }, { /* AArch64_SWPAH, AArch64_INS_SWPAH: swpah */ 0, { 0 } }, { /* AArch64_SWPALB, AArch64_INS_SWPALB: swpalb */ 0, { 0 } }, { /* AArch64_SWPALH, AArch64_INS_SWPALH: swpalh */ 0, { 0 } }, { /* AArch64_SWPALW, AArch64_INS_SWPAL: swpal */ 0, { 0 } }, { /* AArch64_SWPALX, AArch64_INS_SWPAL: swpal */ 0, { 0 } }, { /* AArch64_SWPAW, AArch64_INS_SWPA: swpa */ 0, { 0 } }, { /* AArch64_SWPAX, AArch64_INS_SWPA: swpa */ 0, { 0 } }, { /* AArch64_SWPB, AArch64_INS_SWPB: swpb */ 0, { 0 } }, { /* AArch64_SWPH, AArch64_INS_SWPH: swph */ 0, { 0 } }, { /* AArch64_SWPLB, AArch64_INS_SWPLB: swplb */ 0, { 0 } }, { /* AArch64_SWPLH, AArch64_INS_SWPLH: swplh */ 0, { 0 } }, { /* AArch64_SWPLW, AArch64_INS_SWPL: swpl */ 0, { 0 } }, { /* AArch64_SWPLX, AArch64_INS_SWPL: swpl */ 0, { 0 } }, { /* AArch64_SWPW, AArch64_INS_SWP: swp */ 0, { 0 } }, { /* AArch64_SWPX, AArch64_INS_SWP: swp */ 0, { 0 } }, { /* AArch64_SXTB_ZPmZ_D, AArch64_INS_SXTB: sxtb */ 0, { 0 } }, { /* AArch64_SXTB_ZPmZ_H, AArch64_INS_SXTB: sxtb */ 0, { 0 } }, { /* AArch64_SXTB_ZPmZ_S, AArch64_INS_SXTB: sxtb */ 0, { 0 } }, { /* AArch64_SXTH_ZPmZ_D, AArch64_INS_SXTH: sxth */ 0, { 0 } }, { /* AArch64_SXTH_ZPmZ_S, AArch64_INS_SXTH: sxth */ 0, { 0 } }, { /* AArch64_SXTW_ZPmZ_D, AArch64_INS_SXTW: sxtw */ 0, { 0 } }, { /* AArch64_SYSLxt, AArch64_INS_SYSL: sysl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, { /* AArch64_SYSxt, AArch64_INS_SYS: sys */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ } }, { /* AArch64_TBL_ZZZ_B, AArch64_INS_TBL: tbl */ 0, { 0 } }, { /* AArch64_TBL_ZZZ_D, AArch64_INS_TBL: tbl */ 0, { 0 } }, { /* AArch64_TBL_ZZZ_H, AArch64_INS_TBL: tbl */ 0, { 0 } }, { /* AArch64_TBL_ZZZ_S, AArch64_INS_TBL: tbl */ 0, { 0 } }, { /* AArch64_TBLv16i8Four, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv16i8One, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv16i8Three, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv16i8Two, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv8i8Four, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv8i8One, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv8i8Three, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBLv8i8Two, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBNZW, AArch64_INS_TBNZ: tbnz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBNZX, AArch64_INS_TBNZ: tbnz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv16i8Four, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv16i8One, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv16i8Three, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv16i8Two, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv8i8Four, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv8i8One, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv8i8Three, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBXv8i8Two, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBZW, AArch64_INS_TBZ: tbz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TBZX, AArch64_INS_TBZ: tbz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1_PPP_B, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_PPP_D, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_PPP_H, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_PPP_S, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_ZZZ_B, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_ZZZ_D, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_ZZZ_H, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1_ZZZ_S, AArch64_INS_TRN1: trn1 */ 0, { 0 } }, { /* AArch64_TRN1v16i8, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1v2i32, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1v2i64, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1v4i16, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1v4i32, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1v8i16, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN1v8i8, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2_PPP_B, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_PPP_D, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_PPP_H, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_PPP_S, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_ZZZ_B, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_ZZZ_D, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_ZZZ_H, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2_ZZZ_S, AArch64_INS_TRN2: trn2 */ 0, { 0 } }, { /* AArch64_TRN2v16i8, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2v2i32, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2v2i64, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2v4i16, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2v4i32, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2v8i16, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TRN2v8i8, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_TSB, AArch64_INS_TSB: tsb */ 0, { 0 } }, { /* AArch64_UABALv16i8_v8i16, AArch64_INS_UABAL2: uabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABALv2i32_v2i64, AArch64_INS_UABAL: uabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABALv4i16_v4i32, AArch64_INS_UABAL: uabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABALv4i32_v2i64, AArch64_INS_UABAL2: uabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABALv8i16_v4i32, AArch64_INS_UABAL2: uabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABALv8i8_v8i16, AArch64_INS_UABAL: uabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABAv16i8, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABAv2i32, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABAv4i16, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABAv4i32, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABAv8i16, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABAv8i8, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDLv16i8_v8i16, AArch64_INS_UABDL2: uabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDLv2i32_v2i64, AArch64_INS_UABDL: uabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDLv4i16_v4i32, AArch64_INS_UABDL: uabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDLv4i32_v2i64, AArch64_INS_UABDL2: uabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDLv8i16_v4i32, AArch64_INS_UABDL2: uabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDLv8i8_v8i16, AArch64_INS_UABDL: uabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABD_ZPmZ_B, AArch64_INS_UABD: uabd */ 0, { 0 } }, { /* AArch64_UABD_ZPmZ_D, AArch64_INS_UABD: uabd */ 0, { 0 } }, { /* AArch64_UABD_ZPmZ_H, AArch64_INS_UABD: uabd */ 0, { 0 } }, { /* AArch64_UABD_ZPmZ_S, AArch64_INS_UABD: uabd */ 0, { 0 } }, { /* AArch64_UABDv16i8, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDv2i32, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDv4i16, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDv4i32, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDv8i16, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UABDv8i8, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADALPv16i8_v8i16, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADALPv2i32_v1i64, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADALPv4i16_v2i32, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADALPv4i32_v2i64, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADALPv8i16_v4i32, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADALPv8i8_v4i16, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLPv16i8_v8i16, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLPv2i32_v1i64, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLPv4i16_v2i32, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLPv4i32_v2i64, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLPv8i16_v4i32, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLPv8i8_v4i16, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLVv16i8v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UADDLVv4i16v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UADDLVv4i32v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UADDLVv8i16v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UADDLVv8i8v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UADDLv16i8_v8i16, AArch64_INS_UADDL2: uaddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLv2i32_v2i64, AArch64_INS_UADDL: uaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLv4i16_v4i32, AArch64_INS_UADDL: uaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLv4i32_v2i64, AArch64_INS_UADDL2: uaddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLv8i16_v4i32, AArch64_INS_UADDL2: uaddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDLv8i8_v8i16, AArch64_INS_UADDL: uaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDV_VPZ_B, AArch64_INS_UADDV: uaddv */ 0, { 0 } }, { /* AArch64_UADDV_VPZ_D, AArch64_INS_UADDV: uaddv */ 0, { 0 } }, { /* AArch64_UADDV_VPZ_H, AArch64_INS_UADDV: uaddv */ 0, { 0 } }, { /* AArch64_UADDV_VPZ_S, AArch64_INS_UADDV: uaddv */ 0, { 0 } }, { /* AArch64_UADDWv16i8_v8i16, AArch64_INS_UADDW2: uaddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDWv2i32_v2i64, AArch64_INS_UADDW: uaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDWv4i16_v4i32, AArch64_INS_UADDW: uaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDWv4i32_v2i64, AArch64_INS_UADDW2: uaddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDWv8i16_v4i32, AArch64_INS_UADDW2: uaddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UADDWv8i8_v8i16, AArch64_INS_UADDW: uaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UBFMWri, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UBFMXri, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFSWDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFSWHri, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFSWSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFSXDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFSXHri, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFSXSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFUWDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFUWHri, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFUWSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFUXDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFUXHri, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFUXSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTF_ZPmZ_DtoD, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTF_ZPmZ_DtoH, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTF_ZPmZ_DtoS, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTF_ZPmZ_HtoH, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTF_ZPmZ_StoD, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTF_ZPmZ_StoH, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTF_ZPmZ_StoS, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFd, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFh, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFs, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv1i16, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFv1i32, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv1i64, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv2f32, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv2f64, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv2i32_shift, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv2i64_shift, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv4f16, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFv4f32, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv4i16_shift, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFv4i32_shift, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UCVTFv8f16, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UCVTFv8i16_shift, AArch64_INS_UCVTF: ucvtf */ 0, { 0 } }, { /* AArch64_UDIVR_ZPmZ_D, AArch64_INS_UDIVR: udivr */ 0, { 0 } }, { /* AArch64_UDIVR_ZPmZ_S, AArch64_INS_UDIVR: udivr */ 0, { 0 } }, { /* AArch64_UDIVWr, AArch64_INS_UDIV: udiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UDIVXr, AArch64_INS_UDIV: udiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UDIV_ZPmZ_D, AArch64_INS_UDIV: udiv */ 0, { 0 } }, { /* AArch64_UDIV_ZPmZ_S, AArch64_INS_UDIV: udiv */ 0, { 0 } }, { /* AArch64_UDOT_ZZZI_D, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOT_ZZZI_S, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOT_ZZZ_D, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOT_ZZZ_S, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOTlanev16i8, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOTlanev8i8, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOTv16i8, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UDOTv8i8, AArch64_INS_UDOT: udot */ 0, { 0 } }, { /* AArch64_UHADDv16i8, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHADDv2i32, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHADDv4i16, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHADDv4i32, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHADDv8i16, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHADDv8i8, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHSUBv16i8, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHSUBv2i32, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHSUBv4i16, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHSUBv4i32, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHSUBv8i16, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UHSUBv8i8, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMADDLrrr, AArch64_INS_UMADDL: umaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXPv16i8, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXPv2i32, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXPv4i16, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXPv4i32, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXPv8i16, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXPv8i8, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXV_VPZ_B, AArch64_INS_UMAXV: umaxv */ 0, { 0 } }, { /* AArch64_UMAXV_VPZ_D, AArch64_INS_UMAXV: umaxv */ 0, { 0 } }, { /* AArch64_UMAXV_VPZ_H, AArch64_INS_UMAXV: umaxv */ 0, { 0 } }, { /* AArch64_UMAXV_VPZ_S, AArch64_INS_UMAXV: umaxv */ 0, { 0 } }, { /* AArch64_UMAXVv16i8v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMAXVv4i16v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMAXVv4i32v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMAXVv8i16v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMAXVv8i8v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMAX_ZI_B, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZI_D, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZI_H, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZI_S, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZPmZ_B, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZPmZ_D, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZPmZ_H, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAX_ZPmZ_S, AArch64_INS_UMAX: umax */ 0, { 0 } }, { /* AArch64_UMAXv16i8, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXv2i32, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXv4i16, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXv4i32, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXv8i16, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMAXv8i8, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINPv16i8, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINPv2i32, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINPv4i16, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINPv4i32, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINPv8i16, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINPv8i8, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINV_VPZ_B, AArch64_INS_UMINV: uminv */ 0, { 0 } }, { /* AArch64_UMINV_VPZ_D, AArch64_INS_UMINV: uminv */ 0, { 0 } }, { /* AArch64_UMINV_VPZ_H, AArch64_INS_UMINV: uminv */ 0, { 0 } }, { /* AArch64_UMINV_VPZ_S, AArch64_INS_UMINV: uminv */ 0, { 0 } }, { /* AArch64_UMINVv16i8v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMINVv4i16v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMINVv4i32v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMINVv8i16v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMINVv8i8v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UMIN_ZI_B, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZI_D, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZI_H, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZI_S, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZPmZ_B, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZPmZ_D, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZPmZ_H, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMIN_ZPmZ_S, AArch64_INS_UMIN: umin */ 0, { 0 } }, { /* AArch64_UMINv16i8, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINv2i32, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINv4i16, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINv4i32, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINv8i16, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMINv8i8, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv16i8_v8i16, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv2i32_indexed, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv2i32_v2i64, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv4i16_indexed, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv4i16_v4i32, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv4i32_indexed, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv4i32_v2i64, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv8i16_indexed, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv8i16_v4i32, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLALv8i8_v8i16, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv16i8_v8i16, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv2i32_indexed, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv2i32_v2i64, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv4i16_indexed, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv4i16_v4i32, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv4i32_indexed, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv4i32_v2i64, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv8i16_indexed, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv8i16_v4i32, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMLSLv8i8_v8i16, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMOVvi16, AArch64_INS_UMOV: umov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMOVvi32, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMOVvi64, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMOVvi8, AArch64_INS_UMOV: umov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMSUBLrrr, AArch64_INS_UMNEGL: umnegl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULH_ZPmZ_B, AArch64_INS_UMULH: umulh */ 0, { 0 } }, { /* AArch64_UMULH_ZPmZ_D, AArch64_INS_UMULH: umulh */ 0, { 0 } }, { /* AArch64_UMULH_ZPmZ_H, AArch64_INS_UMULH: umulh */ 0, { 0 } }, { /* AArch64_UMULH_ZPmZ_S, AArch64_INS_UMULH: umulh */ 0, { 0 } }, { /* AArch64_UMULHrr, AArch64_INS_UMULH: umulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv16i8_v8i16, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv2i32_indexed, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv2i32_v2i64, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv4i16_indexed, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv4i16_v4i32, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv4i32_indexed, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv4i32_v2i64, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv8i16_indexed, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv8i16_v4i32, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UMULLv8i8_v8i16, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADD_ZI_B, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZI_D, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZI_H, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZI_S, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZZZ_B, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZZZ_D, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZZZ_H, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADD_ZZZ_S, AArch64_INS_UQADD: uqadd */ 0, { 0 } }, { /* AArch64_UQADDv16i8, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv1i16, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv1i32, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv1i64, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv1i8, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv2i32, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv2i64, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv4i16, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv4i32, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv8i16, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQADDv8i8, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQDECB_WPiI, AArch64_INS_UQDECB: uqdecb */ 0, { 0 } }, { /* AArch64_UQDECB_XPiI, AArch64_INS_UQDECB: uqdecb */ 0, { 0 } }, { /* AArch64_UQDECD_WPiI, AArch64_INS_UQDECD: uqdecd */ 0, { 0 } }, { /* AArch64_UQDECD_XPiI, AArch64_INS_UQDECD: uqdecd */ 0, { 0 } }, { /* AArch64_UQDECD_ZPiI, AArch64_INS_UQDECD: uqdecd */ 0, { 0 } }, { /* AArch64_UQDECH_WPiI, AArch64_INS_UQDECH: uqdech */ 0, { 0 } }, { /* AArch64_UQDECH_XPiI, AArch64_INS_UQDECH: uqdech */ 0, { 0 } }, { /* AArch64_UQDECH_ZPiI, AArch64_INS_UQDECH: uqdech */ 0, { 0 } }, { /* AArch64_UQDECP_WP_B, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_WP_D, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_WP_H, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_WP_S, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_XP_B, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_XP_D, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_XP_H, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_XP_S, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_ZP_D, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_ZP_H, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECP_ZP_S, AArch64_INS_UQDECP: uqdecp */ 0, { 0 } }, { /* AArch64_UQDECW_WPiI, AArch64_INS_UQDECW: uqdecw */ 0, { 0 } }, { /* AArch64_UQDECW_XPiI, AArch64_INS_UQDECW: uqdecw */ 0, { 0 } }, { /* AArch64_UQDECW_ZPiI, AArch64_INS_UQDECW: uqdecw */ 0, { 0 } }, { /* AArch64_UQINCB_WPiI, AArch64_INS_UQINCB: uqincb */ 0, { 0 } }, { /* AArch64_UQINCB_XPiI, AArch64_INS_UQINCB: uqincb */ 0, { 0 } }, { /* AArch64_UQINCD_WPiI, AArch64_INS_UQINCD: uqincd */ 0, { 0 } }, { /* AArch64_UQINCD_XPiI, AArch64_INS_UQINCD: uqincd */ 0, { 0 } }, { /* AArch64_UQINCD_ZPiI, AArch64_INS_UQINCD: uqincd */ 0, { 0 } }, { /* AArch64_UQINCH_WPiI, AArch64_INS_UQINCH: uqinch */ 0, { 0 } }, { /* AArch64_UQINCH_XPiI, AArch64_INS_UQINCH: uqinch */ 0, { 0 } }, { /* AArch64_UQINCH_ZPiI, AArch64_INS_UQINCH: uqinch */ 0, { 0 } }, { /* AArch64_UQINCP_WP_B, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_WP_D, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_WP_H, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_WP_S, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_XP_B, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_XP_D, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_XP_H, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_XP_S, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_ZP_D, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_ZP_H, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCP_ZP_S, AArch64_INS_UQINCP: uqincp */ 0, { 0 } }, { /* AArch64_UQINCW_WPiI, AArch64_INS_UQINCW: uqincw */ 0, { 0 } }, { /* AArch64_UQINCW_XPiI, AArch64_INS_UQINCW: uqincw */ 0, { 0 } }, { /* AArch64_UQINCW_ZPiI, AArch64_INS_UQINCW: uqincw */ 0, { 0 } }, { /* AArch64_UQRSHLv16i8, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv1i16, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv1i32, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv1i64, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv1i8, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv2i32, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv2i64, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv4i16, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv4i32, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv8i16, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHLv8i8, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNb, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNh, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNs, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNv16i8_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNv2i32_shift, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNv4i16_shift, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNv4i32_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNv8i16_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQRSHRNv8i8_shift, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLb, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLd, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLh, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLs, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv16i8, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv16i8_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv1i16, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv1i32, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv1i64, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv1i8, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv2i32, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv2i32_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv2i64, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv2i64_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv4i16, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv4i16_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv4i32, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv4i32_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv8i16, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv8i16_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv8i8, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHLv8i8_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNb, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNh, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNs, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNv16i8_shift, AArch64_INS_UQSHRN2: uqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNv2i32_shift, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNv4i16_shift, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNv4i32_shift, AArch64_INS_UQSHRN2: uqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNv8i16_shift, AArch64_INS_UQSHRN2: uqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSHRNv8i8_shift, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUB_ZI_B, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZI_D, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZI_H, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZI_S, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZZZ_B, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZZZ_D, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZZZ_H, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUB_ZZZ_S, AArch64_INS_UQSUB: uqsub */ 0, { 0 } }, { /* AArch64_UQSUBv16i8, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv1i16, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv1i32, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv1i64, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv1i8, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv2i32, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv2i64, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv4i16, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv4i32, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv8i16, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQSUBv8i8, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv16i8, AArch64_INS_UQXTN2: uqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv1i16, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv1i32, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv1i8, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv2i32, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv4i16, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv4i32, AArch64_INS_UQXTN2: uqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv8i16, AArch64_INS_UQXTN2: uqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_UQXTNv8i8, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_URECPEv2i32, AArch64_INS_URECPE: urecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_URECPEv4i32, AArch64_INS_URECPE: urecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_URHADDv16i8, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URHADDv2i32, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URHADDv4i16, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URHADDv4i32, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URHADDv8i16, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URHADDv8i8, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv16i8, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv1i64, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv2i32, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv2i64, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv4i16, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv4i32, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv8i16, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHLv8i8, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRd, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv16i8_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv2i32_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv2i64_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv4i16_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv4i32_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv8i16_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSHRv8i8_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSQRTEv2i32, AArch64_INS_URSQRTE: ursqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_URSQRTEv4i32, AArch64_INS_URSQRTE: ursqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_URSRAd, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv16i8_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv2i32_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv2i64_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv4i16_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv4i32_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv8i16_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_URSRAv8i8_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLLv16i8_shift, AArch64_INS_USHLL2: ushll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLLv2i32_shift, AArch64_INS_USHLL: ushll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLLv4i16_shift, AArch64_INS_USHLL: ushll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLLv4i32_shift, AArch64_INS_USHLL2: ushll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLLv8i16_shift, AArch64_INS_USHLL2: ushll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLLv8i8_shift, AArch64_INS_USHLL: ushll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv16i8, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv1i64, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv2i32, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv2i64, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv4i16, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv4i32, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv8i16, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHLv8i8, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRd, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv16i8_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv2i32_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv2i64_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv4i16_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv4i32_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv8i16_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USHRv8i8_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv16i8, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv1i16, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv1i32, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv1i64, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv1i8, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv2i32, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv2i64, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv4i16, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv4i32, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv8i16, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USQADDv8i8, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAd, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv16i8_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv2i32_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv2i64_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv4i16_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv4i32_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv8i16_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USRAv8i8_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBLv16i8_v8i16, AArch64_INS_USUBL2: usubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBLv2i32_v2i64, AArch64_INS_USUBL: usubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBLv4i16_v4i32, AArch64_INS_USUBL: usubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBLv4i32_v2i64, AArch64_INS_USUBL2: usubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBLv8i16_v4i32, AArch64_INS_USUBL2: usubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBLv8i8_v8i16, AArch64_INS_USUBL: usubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBWv16i8_v8i16, AArch64_INS_USUBW2: usubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBWv2i32_v2i64, AArch64_INS_USUBW: usubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBWv4i16_v4i32, AArch64_INS_USUBW: usubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBWv4i32_v2i64, AArch64_INS_USUBW2: usubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBWv8i16_v4i32, AArch64_INS_USUBW2: usubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_USUBWv8i8_v8i16, AArch64_INS_USUBW: usubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UUNPKHI_ZZ_D, AArch64_INS_UUNPKHI: uunpkhi */ 0, { 0 } }, { /* AArch64_UUNPKHI_ZZ_H, AArch64_INS_UUNPKHI: uunpkhi */ 0, { 0 } }, { /* AArch64_UUNPKHI_ZZ_S, AArch64_INS_UUNPKHI: uunpkhi */ 0, { 0 } }, { /* AArch64_UUNPKLO_ZZ_D, AArch64_INS_UUNPKLO: uunpklo */ 0, { 0 } }, { /* AArch64_UUNPKLO_ZZ_H, AArch64_INS_UUNPKLO: uunpklo */ 0, { 0 } }, { /* AArch64_UUNPKLO_ZZ_S, AArch64_INS_UUNPKLO: uunpklo */ 0, { 0 } }, { /* AArch64_UXTB_ZPmZ_D, AArch64_INS_UXTB: uxtb */ 0, { 0 } }, { /* AArch64_UXTB_ZPmZ_H, AArch64_INS_UXTB: uxtb */ 0, { 0 } }, { /* AArch64_UXTB_ZPmZ_S, AArch64_INS_UXTB: uxtb */ 0, { 0 } }, { /* AArch64_UXTH_ZPmZ_D, AArch64_INS_UXTH: uxth */ 0, { 0 } }, { /* AArch64_UXTH_ZPmZ_S, AArch64_INS_UXTH: uxth */ 0, { 0 } }, { /* AArch64_UXTW_ZPmZ_D, AArch64_INS_UXTW: uxtw */ 0, { 0 } }, { /* AArch64_UZP1_PPP_B, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_PPP_D, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_PPP_H, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_PPP_S, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_ZZZ_B, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_ZZZ_D, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_ZZZ_H, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1_ZZZ_S, AArch64_INS_UZP1: uzp1 */ 0, { 0 } }, { /* AArch64_UZP1v16i8, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP1v2i32, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP1v2i64, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP1v4i16, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP1v4i32, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP1v8i16, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP1v8i8, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2_PPP_B, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_PPP_D, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_PPP_H, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_PPP_S, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_ZZZ_B, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_ZZZ_D, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_ZZZ_H, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2_ZZZ_S, AArch64_INS_UZP2: uzp2 */ 0, { 0 } }, { /* AArch64_UZP2v16i8, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2v2i32, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2v2i64, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2v4i16, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2v4i32, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2v8i16, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_UZP2v8i8, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_WHILELE_PWW_B, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PWW_D, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PWW_H, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PWW_S, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PXX_B, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PXX_D, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PXX_H, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELE_PXX_S, AArch64_INS_WHILELE: whilele */ 0, { 0 } }, { /* AArch64_WHILELO_PWW_B, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PWW_D, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PWW_H, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PWW_S, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PXX_B, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PXX_D, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PXX_H, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELO_PXX_S, AArch64_INS_WHILELO: whilelo */ 0, { 0 } }, { /* AArch64_WHILELS_PWW_B, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PWW_D, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PWW_H, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PWW_S, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PXX_B, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PXX_D, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PXX_H, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELS_PXX_S, AArch64_INS_WHILELS: whilels */ 0, { 0 } }, { /* AArch64_WHILELT_PWW_B, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PWW_D, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PWW_H, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PWW_S, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PXX_B, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PXX_D, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PXX_H, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WHILELT_PXX_S, AArch64_INS_WHILELT: whilelt */ 0, { 0 } }, { /* AArch64_WRFFR, AArch64_INS_WRFFR: wrffr */ 0, { 0 } }, { /* AArch64_XAR, AArch64_INS_XAR: xar */ 0, { 0 } }, { /* AArch64_XPACD, AArch64_INS_XPACD: xpacd */ 0, { 0 } }, { /* AArch64_XPACI, AArch64_INS_XPACI: xpaci */ 0, { 0 } }, { /* AArch64_XPACLRI, AArch64_INS_XPACLRI: xpaclri */ 0, { 0 } }, { /* AArch64_XTNv16i8, AArch64_INS_XTN2: xtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_XTNv2i32, AArch64_INS_XTN: xtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_XTNv4i16, AArch64_INS_XTN: xtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_XTNv4i32, AArch64_INS_XTN2: xtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_XTNv8i16, AArch64_INS_XTN2: xtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_XTNv8i8, AArch64_INS_XTN: xtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* AArch64_ZIP1_PPP_B, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_PPP_D, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_PPP_H, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_PPP_S, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_ZZZ_B, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_ZZZ_D, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_ZZZ_H, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1_ZZZ_S, AArch64_INS_ZIP1: zip1 */ 0, { 0 } }, { /* AArch64_ZIP1v16i8, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP1v2i32, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP1v2i64, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP1v4i16, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP1v4i32, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP1v8i16, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP1v8i8, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2_PPP_B, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_PPP_D, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_PPP_H, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_PPP_S, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_ZZZ_B, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_ZZZ_D, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_ZZZ_H, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2_ZZZ_S, AArch64_INS_ZIP2: zip2 */ 0, { 0 } }, { /* AArch64_ZIP2v16i8, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2v2i32, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2v2i64, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2v4i16, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2v4i32, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2v8i16, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_ZIP2v8i8, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* AArch64_anonymous_1349, AArch64_INS_PFIRST: pfirst */ 0, { 0 } }, capstone-sys-0.15.0/capstone/arch/AArch64/AArch64Module.c000064400000000000000000000017240072674642500207160ustar 00000000000000/* Capstone Disassembly Engine */ /* By Dang Hoang Vu 2013 */ #ifdef CAPSTONE_HAS_ARM64 #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "AArch64Disassembler.h" #include "AArch64InstPrinter.h" #include "AArch64Mapping.h" #include "AArch64Module.h" cs_err AArch64_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); AArch64_init(mri); ud->printer = AArch64_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = AArch64_getInstruction; ud->reg_name = AArch64_reg_name; ud->insn_id = AArch64_get_insn_id; ud->insn_name = AArch64_insn_name; ud->group_name = AArch64_group_name; ud->post_printer = AArch64_post_printer; #ifndef CAPSTONE_DIET ud->reg_access = AArch64_reg_access; #endif return CS_ERR_OK; } cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_MODE) { handle->mode = (cs_mode)value; } return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/AArch64/AArch64Module.h000064400000000000000000000004510072674642500207170ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_AARCH64_MODULE_H #define CS_AARCH64_MODULE_H #include "../../utils.h" cs_err AArch64_global_init(cs_struct *ud); cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMAddressingModes.h000064400000000000000000000512300072674642500213240ustar 00000000000000//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains the ARM addressing mode implementation stuff. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H #define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H #include "capstone/platform.h" #include "../../MathExtras.h" /// ARM_AM - ARM Addressing Mode Stuff typedef enum ARM_AM_ShiftOpc { ARM_AM_no_shift = 0, ARM_AM_asr, ARM_AM_lsl, ARM_AM_lsr, ARM_AM_ror, ARM_AM_rrx } ARM_AM_ShiftOpc; typedef enum ARM_AM_AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc; static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) { return Op == ARM_AM_sub ? "-" : ""; } static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) { switch (Op) { default: return ""; //llvm_unreachable("Unknown shift opc!"); case ARM_AM_asr: return "asr"; case ARM_AM_lsl: return "lsl"; case ARM_AM_lsr: return "lsr"; case ARM_AM_ror: return "ror"; case ARM_AM_rrx: return "rrx"; } } static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) { switch (Op) { default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!"); case ARM_AM_asr: return 2; case ARM_AM_lsl: return 0; case ARM_AM_lsr: return 1; case ARM_AM_ror: return 3; } } typedef enum ARM_AM_AMSubMode { ARM_AM_bad_am_submode = 0, ARM_AM_ia, ARM_AM_ib, ARM_AM_da, ARM_AM_db } ARM_AM_AMSubMode; static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode) { switch (Mode) { default: return ""; case ARM_AM_ia: return "ia"; case ARM_AM_ib: return "ib"; case ARM_AM_da: return "da"; case ARM_AM_db: return "db"; } } /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. /// static inline unsigned rotr32(unsigned Val, unsigned Amt) { //assert(Amt < 32 && "Invalid rotate amount"); return (Val >> Amt) | (Val << ((32-Amt)&31)); } /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. /// static inline unsigned rotl32(unsigned Val, unsigned Amt) { //assert(Amt < 32 && "Invalid rotate amount"); return (Val << Amt) | (Val >> ((32-Amt)&31)); } //===--------------------------------------------------------------------===// // Addressing Mode #1: shift_operand with registers //===--------------------------------------------------------------------===// // // This 'addressing mode' is used for arithmetic instructions. It can // represent things like: // reg // reg [asr|lsl|lsr|ror|rrx] reg // reg [asr|lsl|lsr|ror|rrx] imm // // This is stored three operands [rega, regb, opc]. The first is the base // reg, the second is the shift amount (or reg0 if not present or imm). The // third operand encodes the shift opcode and the imm if a reg isn't present. // static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) { return ShOp | (Imm << 3); } static inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; } static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) { return (ARM_AM_ShiftOpc)(Op & 7); } /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return /// the 8-bit imm value. static inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return /// the rotate amount. static inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, /// computing the rotate amount to use. If this immediate value cannot be /// handled with a single shifter-op, determine a good rotate amount that will /// take a maximal chunk of bits out of the immediate. static inline unsigned getSOImmValRotate(unsigned Imm) { unsigned TZ, RotAmt; // 8-bit (or less) immediates are trivially shifter_operands with a rotate // of zero. if ((Imm & ~255U) == 0) return 0; // Use CTZ to compute the rotate amount. TZ = CountTrailingZeros_32(Imm); // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, // not 9. RotAmt = TZ & ~1; // If we can handle this spread, return it. if ((rotr32(Imm, RotAmt) & ~255U) == 0) return (32-RotAmt)&31; // HW rotates right, not left. // For values like 0xF000000F, we should ignore the low 6 bits, then // retry the hunt. if (Imm & 63U) { unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); unsigned RotAmt2 = TZ2 & ~1; if ((rotr32(Imm, RotAmt2) & ~255U) == 0) return (32-RotAmt2)&31; // HW rotates right, not left. } // Otherwise, we have no way to cover this span of bits with a single // shifter_op immediate. Return a chunk of bits that will be useful to // handle. return (32-RotAmt)&31; // HW rotates right, not left. } /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit /// into an shifter_operand immediate operand, return the 12-bit encoding for /// it. If not, return -1. static inline int getSOImmVal(unsigned Arg) { unsigned RotAmt; // 8-bit (or less) immediates are trivially shifter_operands with a rotate // of zero. if ((Arg & ~255U) == 0) return Arg; RotAmt = getSOImmValRotate(Arg); // If this cannot be handled with a single shifter_op, bail out. if (rotr32(~255U, RotAmt) & Arg) return -1; // Encode this correctly. return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); } /// isSOImmTwoPartVal - Return true if the specified value can be obtained by /// or'ing together two SOImmVal's. static inline bool isSOImmTwoPartVal(unsigned V) { // If this can be handled with a single shifter_op, bail out. V = rotr32(~255U, getSOImmValRotate(V)) & V; if (V == 0) return false; // If this can be handled with two shifter_op's, accept. V = rotr32(~255U, getSOImmValRotate(V)) & V; return V == 0; } /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, /// return the first chunk of it. static inline unsigned getSOImmTwoPartFirst(unsigned V) { return rotr32(255U, getSOImmValRotate(V)) & V; } /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, /// return the second chunk of it. static inline unsigned getSOImmTwoPartSecond(unsigned V) { // Mask out the first hunk. V = rotr32(~255U, getSOImmValRotate(V)) & V; // Take what's left. //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); return V; } /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed /// by a left shift. Returns the shift amount to use. static inline unsigned getThumbImmValShift(unsigned Imm) { // 8-bit (or less) immediates are trivially immediate operand with a shift // of zero. if ((Imm & ~255U) == 0) return 0; // Use CTZ to compute the shift amount. return CountTrailingZeros_32(Imm); } /// isThumbImmShiftedVal - Return true if the specified value can be obtained /// by left shifting a 8-bit immediate. static inline bool isThumbImmShiftedVal(unsigned V) { // If this can be handled with V = (~255U << getThumbImmValShift(V)) & V; return V == 0; } /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed /// by a left shift. Returns the shift amount to use. static inline unsigned getThumbImm16ValShift(unsigned Imm) { // 16-bit (or less) immediates are trivially immediate operand with a shift // of zero. if ((Imm & ~65535U) == 0) return 0; // Use CTZ to compute the shift amount. return CountTrailingZeros_32(Imm); } /// isThumbImm16ShiftedVal - Return true if the specified value can be /// obtained by left shifting a 16-bit immediate. static inline bool isThumbImm16ShiftedVal(unsigned V) { // If this can be handled with V = (~65535U << getThumbImm16ValShift(V)) & V; return V == 0; } /// getThumbImmNonShiftedVal - If V is a value that satisfies /// isThumbImmShiftedVal, return the non-shiftd value. static inline unsigned getThumbImmNonShiftedVal(unsigned V) { return V >> getThumbImmValShift(V); } /// getT2SOImmValSplat - Return the 12-bit encoded representation /// if the specified value can be obtained by splatting the low 8 bits /// into every other byte or every byte of a 32-bit value. i.e., /// 00000000 00000000 00000000 abcdefgh control = 0 /// 00000000 abcdefgh 00000000 abcdefgh control = 1 /// abcdefgh 00000000 abcdefgh 00000000 control = 2 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 /// Return -1 if none of the above apply. /// See ARM Reference Manual A6.3.2. static inline int getT2SOImmValSplatVal(unsigned V) { unsigned u, Vs, Imm; // control = 0 if ((V & 0xffffff00) == 0) return V; // If the value is zeroes in the first byte, just shift those off Vs = ((V & 0xff) == 0) ? V >> 8 : V; // Any passing value only has 8 bits of payload, splatted across the word Imm = Vs & 0xff; // Likewise, any passing values have the payload splatted into the 3rd byte u = Imm | (Imm << 16); // control = 1 or 2 if (Vs == u) return (((Vs == V) ? 1 : 2) << 8) | Imm; // control = 3 if (Vs == (u | (u << 8))) return (3 << 8) | Imm; return -1; } /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the /// specified value is a rotated 8-bit value. Return -1 if no rotation /// encoding is possible. /// See ARM Reference Manual A6.3.2. static inline int getT2SOImmValRotateVal(unsigned V) { unsigned RotAmt = CountLeadingZeros_32(V); if (RotAmt >= 24) return -1; // If 'Arg' can be handled with a single shifter_op return the value. if ((rotr32(0xff000000U, RotAmt) & V) == V) return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); return -1; } /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit /// encoding for it. If not, return -1. /// See ARM Reference Manual A6.3.2. static inline int getT2SOImmVal(unsigned Arg) { int Rot; // If 'Arg' is an 8-bit splat, then get the encoded value. int Splat = getT2SOImmValSplatVal(Arg); if (Splat != -1) return Splat; // If 'Arg' can be handled with a single shifter_op return the value. Rot = getT2SOImmValRotateVal(Arg); if (Rot != -1) return Rot; return -1; } static inline unsigned getT2SOImmValRotate(unsigned V) { unsigned RotAmt; if ((V & ~255U) == 0) return 0; // Use CTZ to compute the rotate amount. RotAmt = CountTrailingZeros_32(V); return (32 - RotAmt) & 31; } static inline bool isT2SOImmTwoPartVal (unsigned Imm) { unsigned V = Imm; // Passing values can be any combination of splat values and shifter // values. If this can be handled with a single shifter or splat, bail // out. Those should be handled directly, not with a two-part val. if (getT2SOImmValSplatVal(V) != -1) return false; V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; if (V == 0) return false; // If this can be handled as an immediate, accept. if (getT2SOImmVal(V) != -1) return true; // Likewise, try masking out a splat value first. V = Imm; if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) V &= ~0xff00ff00U; else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) V &= ~0x00ff00ffU; // If what's left can be handled as an immediate, accept. if (getT2SOImmVal(V) != -1) return true; // Otherwise, do not accept. return false; } static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { //assert (isT2SOImmTwoPartVal(Imm) && // "Immedate cannot be encoded as two part immediate!"); // Try a shifter operand as one part unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm; // If the rest is encodable as an immediate, then return it. if (getT2SOImmVal(V) != -1) return V; // Try masking out a splat value first. if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) return Imm & 0xff00ff00U; // The other splat is all that's left as an option. //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); return Imm & 0x00ff00ffU; } static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { // Mask out the first hunk Imm ^= getT2SOImmTwoPartFirst(Imm); // Return what's left //assert (getT2SOImmVal(Imm) != -1 && // "Unable to encode second part of T2 two part SO immediate"); return Imm; } //===--------------------------------------------------------------------===// // Addressing Mode #2 //===--------------------------------------------------------------------===// // // This is used for most simple load/store instructions. // // addrmode2 := reg +/- reg shop imm // addrmode2 := reg +/- imm12 // // The first operand is always a Reg. The second operand is a reg if in // reg/reg form, otherwise it's reg#0. The third field encodes the operation // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The // fourth operand 16-17 encodes the index mode. // // If this addressing mode is a frame index (before prolog/epilog insertion // and code rewriting), this operand will have the form: FI#, reg0, // with no shift amount for the frame offset. // static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO, unsigned IdxMode) { //assert(Imm12 < (1 << 12) && "Imm too large!"); bool isSub = Opc == ARM_AM_sub; return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; } static inline unsigned getAM2Offset(unsigned AM2Opc) { return AM2Opc & ((1 << 12)-1); } static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc) { return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; } static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); } static inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); } //===--------------------------------------------------------------------===// // Addressing Mode #3 //===--------------------------------------------------------------------===// // // This is used for sign-extending loads, and load/store-pair instructions. // // addrmode3 := reg +/- reg // addrmode3 := reg +/- imm8 // // The first operand is always a Reg. The second operand is a reg if in // reg/reg form, otherwise it's reg#0. The third field encodes the operation // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the // index mode. /// getAM3Opc - This function encodes the addrmode3 opc field. static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset, unsigned IdxMode) { bool isSub = Opc == ARM_AM_sub; return ((int)isSub << 8) | Offset | (IdxMode << 9); } static inline unsigned char getAM3Offset(unsigned AM3Opc) { return AM3Opc & 0xFF; } static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc) { return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; } static inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); } //===--------------------------------------------------------------------===// // Addressing Mode #4 //===--------------------------------------------------------------------===// // // This is used for load / store multiple instructions. // // addrmode4 := reg, // // The four modes are: // IA - Increment after // IB - Increment before // DA - Decrement after // DB - Decrement before // For VFP instructions, only the IA and DB modes are valid. static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode) { return (ARM_AM_AMSubMode)(Mode & 0x7); } static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) { return (int)SubMode; } //===--------------------------------------------------------------------===// // Addressing Mode #5 //===--------------------------------------------------------------------===// // // This is used for coprocessor instructions, such as FP load/stores. // // addrmode5 := reg +/- imm8*4 // // The first operand is always a Reg. The second operand encodes the // operation in bit 8 and the immediate in bits 0-7. /// getAM5Opc - This function encodes the addrmode5 opc field. static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) { bool isSub = Opc == ARM_AM_sub; return ((int)isSub << 8) | Offset; } static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; } static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) { return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; } //===--------------------------------------------------------------------===// // Addressing Mode #5 FP16 //===--------------------------------------------------------------------===// // // This is used for coprocessor instructions, such as 16-bit FP load/stores. // // addrmode5fp16 := reg +/- imm8*2 // // The first operand is always a Reg. The second operand encodes the // operation (add or subtract) in bit 8 and the immediate in bits 0-7. /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field. static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) { bool isSub = Opc == ARM_AM_sub; return ((int)isSub << 8) | Offset; } static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; } static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc) { return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; } //===--------------------------------------------------------------------===// // Addressing Mode #6 //===--------------------------------------------------------------------===// // // This is used for NEON load / store instructions. // // addrmode6 := reg with optional alignment // // This is stored in two operands [regaddr, align]. The first is the // address register. The second operand is the value of the alignment // specifier in bytes or zero if no explicit alignment. // Valid alignments depend on the specific instruction. //===--------------------------------------------------------------------===// // NEON Modified Immediates //===--------------------------------------------------------------------===// // // Several NEON instructions (e.g., VMOV) take a "modified immediate" // vector operand, where a small immediate encoded in the instruction // specifies a full NEON vector value. These modified immediates are // represented here as encoded integers. The low 8 bits hold the immediate // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold // the "Cmode" field of the instruction. The interfaces below treat the // Op and Cmode values as a single 5-bit value. static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { return (OpCmode << 8) | Val; } static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { return (ModImm >> 8) & 0x1f; } static inline unsigned getNEONModImmVal(unsigned ModImm) { return ModImm & 0xff; } /// decodeNEONModImm - Decode a NEON modified immediate value into the /// element value and the element size in bits. (If the element size is /// smaller than the vector, it is splatted into all the elements.) static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits) { unsigned OpCmode = getNEONModImmOpCmode(ModImm); unsigned Imm8 = getNEONModImmVal(ModImm); uint64_t Val = 0; unsigned ByteNum; if (OpCmode == 0xe) { // 8-bit vector elements Val = Imm8; *EltBits = 8; } else if ((OpCmode & 0xc) == 0x8) { // 16-bit vector elements ByteNum = (OpCmode & 0x6) >> 1; Val = (uint64_t)Imm8 << (8 * ByteNum); *EltBits = 16; } else if ((OpCmode & 0x8) == 0) { // 32-bit vector elements, zero with one byte set ByteNum = (OpCmode & 0x6) >> 1; Val = (uint64_t)Imm8 << (8 * ByteNum); *EltBits = 32; } else if ((OpCmode & 0xe) == 0xc) { // 32-bit vector elements, one byte with low bits set ByteNum = 1 + (OpCmode & 0x1); Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); *EltBits = 32; } else if (OpCmode == 0x1e) { // 64-bit vector elements for (ByteNum = 0; ByteNum < 8; ++ByteNum) { if ((ModImm >> ByteNum) & 1) Val |= (uint64_t)0xff << (8 * ByteNum); } *EltBits = 64; } else { //llvm_unreachable("Unsupported NEON immediate"); } return Val; } ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode); //===--------------------------------------------------------------------===// // Floating-point Immediates // static inline float getFPImmFloat(unsigned Imm) { // We expect an 8-bit binary encoding of a floating-point number here. union { uint32_t I; float F; } FPUnion; uint8_t Sign = (Imm >> 7) & 0x1; uint8_t Exp = (Imm >> 4) & 0x7; uint8_t Mantissa = Imm & 0xf; // 8-bit FP iEEEE Float Encoding // abcd efgh aBbbbbbc defgh000 00000000 00000000 // // where B = NOT(b); FPUnion.I = 0; FPUnion.I |= ((uint32_t) Sign) << 31; FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; FPUnion.I |= (Exp & 0x3) << 23; FPUnion.I |= Mantissa << 19; return FPUnion.F; } #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMBaseInfo.h000064400000000000000000000400320072674642500177350ustar 00000000000000//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains small standalone helper functions and enum definitions for // the ARM target useful for the compiler back-end and the MC libraries. // As such, it deliberately does not include references to LLVM core // code gen types, passes, etc.. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_ARMBASEINFO_H #define CS_ARMBASEINFO_H #include "capstone/arm.h" // Defines symbolic names for ARM registers. This defines a mapping from // register name to register number. // #define GET_REGINFO_ENUM #include "ARMGenRegisterInfo.inc" // Enums corresponding to ARM condition codes // The CondCodes constants map directly to the 4-bit encoding of the // condition field for predicated instructions. typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point) ARMCC_EQ, // Equal Equal ARMCC_NE, // Not equal Not equal, or unordered ARMCC_HS, // Carry set >, ==, or unordered ARMCC_LO, // Carry clear Less than ARMCC_MI, // Minus, negative Less than ARMCC_PL, // Plus, positive or zero >, ==, or unordered ARMCC_VS, // Overflow Unordered ARMCC_VC, // No overflow Not unordered ARMCC_HI, // Unsigned higher Greater than, or unordered ARMCC_LS, // Unsigned lower or same Less than or equal ARMCC_GE, // Greater than or equal Greater than or equal ARMCC_LT, // Less than Less than, or unordered ARMCC_GT, // Greater than Greater than ARMCC_LE, // Less than or equal <, ==, or unordered ARMCC_AL // Always (unconditional) Always (unconditional) } ARMCC_CondCodes; inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) { switch (CC) { case ARMCC_EQ: return ARMCC_NE; case ARMCC_NE: return ARMCC_EQ; case ARMCC_HS: return ARMCC_LO; case ARMCC_LO: return ARMCC_HS; case ARMCC_MI: return ARMCC_PL; case ARMCC_PL: return ARMCC_MI; case ARMCC_VS: return ARMCC_VC; case ARMCC_VC: return ARMCC_VS; case ARMCC_HI: return ARMCC_LS; case ARMCC_LS: return ARMCC_HI; case ARMCC_GE: return ARMCC_LT; case ARMCC_LT: return ARMCC_GE; case ARMCC_GT: return ARMCC_LE; case ARMCC_LE: return ARMCC_GT; default: return ARMCC_AL; } } inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) { switch (CC) { case ARMCC_EQ: return "eq"; case ARMCC_NE: return "ne"; case ARMCC_HS: return "hs"; case ARMCC_LO: return "lo"; case ARMCC_MI: return "mi"; case ARMCC_PL: return "pl"; case ARMCC_VS: return "vs"; case ARMCC_VC: return "vc"; case ARMCC_HI: return "hi"; case ARMCC_LS: return "ls"; case ARMCC_GE: return "ge"; case ARMCC_LT: return "lt"; case ARMCC_GT: return "gt"; case ARMCC_LE: return "le"; case ARMCC_AL: return "al"; default: return ""; } } inline static const char *ARM_PROC_IFlagsToString(unsigned val) { switch (val) { case ARM_CPSFLAG_F: return "f"; case ARM_CPSFLAG_I: return "i"; case ARM_CPSFLAG_A: return "a"; default: return ""; } } inline static const char *ARM_PROC_IModToString(unsigned val) { switch (val) { case ARM_CPSMODE_IE: return "ie"; case ARM_CPSMODE_ID: return "id"; default: return ""; } } inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) { // TODO: add details switch (val + 1) { default: return "BUGBUG"; case ARM_MB_SY: return "sy"; case ARM_MB_ST: return "st"; case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; case ARM_MB_RESERVED_12: return "#0xc"; case ARM_MB_ISH: return "ish"; case ARM_MB_ISHST: return "ishst"; case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#9"; case ARM_MB_RESERVED_8: return "#8"; case ARM_MB_NSH: return "nsh"; case ARM_MB_NSHST: return "nshst"; case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5"; case ARM_MB_RESERVED_4: return "#4"; case ARM_MB_OSH: return "osh"; case ARM_MB_OSHST: return "oshst"; case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1"; case ARM_MB_RESERVED_0: return "#0"; } } enum ARM_ISB_InstSyncBOpt { ARM_ISB_RESERVED_0 = 0, ARM_ISB_RESERVED_1 = 1, ARM_ISB_RESERVED_2 = 2, ARM_ISB_RESERVED_3 = 3, ARM_ISB_RESERVED_4 = 4, ARM_ISB_RESERVED_5 = 5, ARM_ISB_RESERVED_6 = 6, ARM_ISB_RESERVED_7 = 7, ARM_ISB_RESERVED_8 = 8, ARM_ISB_RESERVED_9 = 9, ARM_ISB_RESERVED_10 = 10, ARM_ISB_RESERVED_11 = 11, ARM_ISB_RESERVED_12 = 12, ARM_ISB_RESERVED_13 = 13, ARM_ISB_RESERVED_14 = 14, ARM_ISB_SY = 15 }; inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) { switch (val) { default: // never reach case ARM_ISB_RESERVED_0: return "#0x0"; case ARM_ISB_RESERVED_1: return "#0x1"; case ARM_ISB_RESERVED_2: return "#0x2"; case ARM_ISB_RESERVED_3: return "#0x3"; case ARM_ISB_RESERVED_4: return "#0x4"; case ARM_ISB_RESERVED_5: return "#0x5"; case ARM_ISB_RESERVED_6: return "#0x6"; case ARM_ISB_RESERVED_7: return "#0x7"; case ARM_ISB_RESERVED_8: return "#0x8"; case ARM_ISB_RESERVED_9: return "#0x9"; case ARM_ISB_RESERVED_10: return "#0xa"; case ARM_ISB_RESERVED_11: return "#0xb"; case ARM_ISB_RESERVED_12: return "#0xc"; case ARM_ISB_RESERVED_13: return "#0xd"; case ARM_ISB_RESERVED_14: return "#0xe"; case ARM_ISB_SY: return "sy"; } } /// isARMLowRegister - Returns true if the register is a low register (r0-r7). /// static inline bool isARMLowRegister(unsigned Reg) { //using namespace ARM; switch (Reg) { case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3: case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7: return true; default: return false; } } /// ARMII - This namespace holds all of the target specific flags that /// instruction info tracks. /// /// ARM Index Modes enum ARMII_IndexMode { ARMII_IndexModeNone = 0, ARMII_IndexModePre = 1, ARMII_IndexModePost = 2, ARMII_IndexModeUpd = 3 }; /// ARM Addressing Modes typedef enum ARMII_AddrMode { ARMII_AddrModeNone = 0, ARMII_AddrMode1 = 1, ARMII_AddrMode2 = 2, ARMII_AddrMode3 = 3, ARMII_AddrMode4 = 4, ARMII_AddrMode5 = 5, ARMII_AddrMode6 = 6, ARMII_AddrModeT1_1 = 7, ARMII_AddrModeT1_2 = 8, ARMII_AddrModeT1_4 = 9, ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data ARMII_AddrModeT2_i12 = 11, ARMII_AddrModeT2_i8 = 12, ARMII_AddrModeT2_so = 13, ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 ARMII_AddrMode_i12 = 16 } ARMII_AddrMode; inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) { switch (addrmode) { case ARMII_AddrModeNone: return "AddrModeNone"; case ARMII_AddrMode1: return "AddrMode1"; case ARMII_AddrMode2: return "AddrMode2"; case ARMII_AddrMode3: return "AddrMode3"; case ARMII_AddrMode4: return "AddrMode4"; case ARMII_AddrMode5: return "AddrMode5"; case ARMII_AddrMode6: return "AddrMode6"; case ARMII_AddrModeT1_1: return "AddrModeT1_1"; case ARMII_AddrModeT1_2: return "AddrModeT1_2"; case ARMII_AddrModeT1_4: return "AddrModeT1_4"; case ARMII_AddrModeT1_s: return "AddrModeT1_s"; case ARMII_AddrModeT2_i12: return "AddrModeT2_i12"; case ARMII_AddrModeT2_i8: return "AddrModeT2_i8"; case ARMII_AddrModeT2_so: return "AddrModeT2_so"; case ARMII_AddrModeT2_pc: return "AddrModeT2_pc"; case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4"; case ARMII_AddrMode_i12: return "AddrMode_i12"; } } /// Target Operand Flag enum. enum ARMII_TOF { //===------------------------------------------------------------------===// // ARM Specific MachineOperand flags. ARMII_MO_NO_FLAG, /// MO_LO16 - On a symbol operand, this represents a relocation containing /// lower 16 bit of the address. Used only via movw instruction. ARMII_MO_LO16, /// MO_HI16 - On a symbol operand, this represents a relocation containing /// higher 16 bit of the address. Used only via movt instruction. ARMII_MO_HI16, /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, /// i.e. "FOO$non_lazy_ptr". /// Used only via movw instruction. ARMII_MO_LO16_NONLAZY, /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. ARMII_MO_HI16_NONLAZY, /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a /// relocation containing lower 16 bit of the PC relative address of the /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". /// Used only via movw instruction. ARMII_MO_LO16_NONLAZY_PIC, /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a /// relocation containing lower 16 bit of the PC relative address of the /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". /// Used only via movt instruction. ARMII_MO_HI16_NONLAZY_PIC, /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a /// call operand. ARMII_MO_PLT }; enum { //===------------------------------------------------------------------===// // Instruction Flags. //===------------------------------------------------------------------===// // This four-bit field describes the addressing mode used. ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load // and store ops only. Generic "updating" flag is used for ld/st multiple. // The index mode enums are declared in ARMBaseInfo.h ARMII_IndexModeShift = 5, ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, //===------------------------------------------------------------------===// // Instruction encoding formats. // ARMII_FormShift = 7, ARMII_FormMask = 0x3f << ARMII_FormShift, // Pseudo instructions ARMII_Pseudo = 0 << ARMII_FormShift, // Multiply instructions ARMII_MulFrm = 1 << ARMII_FormShift, // Branch instructions ARMII_BrFrm = 2 << ARMII_FormShift, ARMII_BrMiscFrm = 3 << ARMII_FormShift, // Data Processing instructions ARMII_DPFrm = 4 << ARMII_FormShift, ARMII_DPSoRegFrm = 5 << ARMII_FormShift, // Load and Store ARMII_LdFrm = 6 << ARMII_FormShift, ARMII_StFrm = 7 << ARMII_FormShift, ARMII_LdMiscFrm = 8 << ARMII_FormShift, ARMII_StMiscFrm = 9 << ARMII_FormShift, ARMII_LdStMulFrm = 10 << ARMII_FormShift, ARMII_LdStExFrm = 11 << ARMII_FormShift, // Miscellaneous arithmetic instructions ARMII_ArithMiscFrm = 12 << ARMII_FormShift, ARMII_SatFrm = 13 << ARMII_FormShift, // Extend instructions ARMII_ExtFrm = 14 << ARMII_FormShift, // VFP formats ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, ARMII_VFPConv1Frm = 17 << ARMII_FormShift, ARMII_VFPConv2Frm = 18 << ARMII_FormShift, ARMII_VFPConv3Frm = 19 << ARMII_FormShift, ARMII_VFPConv4Frm = 20 << ARMII_FormShift, ARMII_VFPConv5Frm = 21 << ARMII_FormShift, ARMII_VFPLdStFrm = 22 << ARMII_FormShift, ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, ARMII_VFPMiscFrm = 24 << ARMII_FormShift, // Thumb format ARMII_ThumbFrm = 25 << ARMII_FormShift, // Miscelleaneous format ARMII_MiscFrm = 26 << ARMII_FormShift, // NEON formats ARMII_NGetLnFrm = 27 << ARMII_FormShift, ARMII_NSetLnFrm = 28 << ARMII_FormShift, ARMII_NDupFrm = 29 << ARMII_FormShift, ARMII_NLdStFrm = 30 << ARMII_FormShift, ARMII_N1RegModImmFrm= 31 << ARMII_FormShift, ARMII_N2RegFrm = 32 << ARMII_FormShift, ARMII_NVCVTFrm = 33 << ARMII_FormShift, ARMII_NVDupLnFrm = 34 << ARMII_FormShift, ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, ARMII_N3RegFrm = 37 << ARMII_FormShift, ARMII_N3RegVShFrm = 38 << ARMII_FormShift, ARMII_NVExtFrm = 39 << ARMII_FormShift, ARMII_NVMulSLFrm = 40 << ARMII_FormShift, ARMII_NVTBLFrm = 41 << ARMII_FormShift, //===------------------------------------------------------------------===// // Misc flags. // UnaryDP - Indicates this is a unary data processing instruction, i.e. // it doesn't have a Rn operand. ARMII_UnaryDP = 1 << 13, // Xform16Bit - Indicates this Thumb2 instruction may be transformed into // a 16-bit Thumb instruction if certain conditions are met. ARMII_Xform16Bit = 1 << 14, // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb // instruction. Used by the parser to determine whether to require the 'S' // suffix on the mnemonic (when not in an IT block) or preclude it (when // in an IT block). ARMII_ThumbArithFlagSetting = 1 << 18, //===------------------------------------------------------------------===// // Code domain. ARMII_DomainShift = 15, ARMII_DomainMask = 7 << ARMII_DomainShift, ARMII_DomainGeneral = 0 << ARMII_DomainShift, ARMII_DomainVFP = 1 << ARMII_DomainShift, ARMII_DomainNEON = 2 << ARMII_DomainShift, ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating // machine instructions. // // FIXME: This list will need adjusting/fixing as the MC code emitter // takes shape and the ARMCodeEmitter.cpp bits go away. ARMII_ShiftTypeShift = 4, ARMII_M_BitShift = 5, ARMII_ShiftImmShift = 5, ARMII_ShiftShift = 7, ARMII_N_BitShift = 7, ARMII_ImmHiShift = 8, ARMII_SoRotImmShift = 8, ARMII_RegRsShift = 8, ARMII_ExtRotImmShift = 10, ARMII_RegRdLoShift = 12, ARMII_RegRdShift = 12, ARMII_RegRdHiShift = 16, ARMII_RegRnShift = 16, ARMII_S_BitShift = 20, ARMII_W_BitShift = 21, ARMII_AM3_I_BitShift = 22, ARMII_D_BitShift = 22, ARMII_U_BitShift = 23, ARMII_P_BitShift = 24, ARMII_I_BitShift = 25, ARMII_CondShift = 28 }; typedef struct MClassSysReg { const char *Name; arm_sysreg sysreg; uint16_t M1Encoding12; uint16_t M2M3Encoding8; uint16_t Encoding; int FeaturesRequired[2]; // 2 is enough for MClassSysRegsList } MClassSysReg; enum TraceSyncBOpt { CSYNC = 0 }; const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding); const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12); // returns APSR with _ qualifier. // Note: ARMv7-M deprecates using MSR APSR without a _ qualifier static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) { return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF)); } static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) { return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF)); } // returns true if TestFeatures are all present in FeaturesRequired static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures) { return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures); } // lookup system register using 12-bit SYSm value. // Note: the search is uniqued using M1 mask static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) { return lookupMClassSysRegByM1Encoding12(SYSm); } static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val) { switch (val) { default: // llvm_unreachable("Unknown trace synchronization barrier operation"); return NULL; case CSYNC: return "csync"; } } #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMDisassembler.c000064400000000000000000005035570072674642500206770ustar 00000000000000//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_ARM #include #include #include #include #include "ARMAddressingModes.h" #include "ARMBaseInfo.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCRegisterInfo.h" #include "../../LEB128.h" #include "../../MCDisassembler.h" #include "../../cs_priv.h" #include "../../utils.h" #include "ARMDisassembler.h" #include "ARMMapping.h" #define GET_SUBTARGETINFO_ENUM #include "ARMGenSubtargetInfo.inc" #define GET_INSTRINFO_MC_DESC #include "ARMGenInstrInfo.inc" #define GET_INSTRINFO_ENUM #include "ARMGenInstrInfo.inc" static bool ITStatus_push_back(ARM_ITStatus *it, char v) { if (it->size >= sizeof(it->ITStates)) { // TODO: consider warning user. it->size = 0; } it->ITStates[it->size] = v; it->size++; return true; } // Returns true if the current instruction is in an IT block static bool ITStatus_instrInITBlock(ARM_ITStatus *it) { //return !ITStates.empty(); return (it->size > 0); } // Returns true if current instruction is the last instruction in an IT block static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) { return (it->size == 1); } // Handles the condition code status of instructions in IT blocks // Returns the condition code for instruction in IT block static unsigned ITStatus_getITCC(ARM_ITStatus *it) { unsigned CC = ARMCC_AL; if (ITStatus_instrInITBlock(it)) //CC = ITStates.back(); CC = it->ITStates[it->size-1]; return CC; } // Advances the IT block state to the next T or E static void ITStatus_advanceITState(ARM_ITStatus *it) { //ITStates.pop_back(); it->size--; } // Called when decoding an IT instruction. Sets the IT state for the following // instructions that for the IT block. Firstcond and Mask correspond to the // fields in the IT instruction encoding. static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) { // (3 - the number of trailing zeros) is the number of then / else. unsigned CondBit0 = Firstcond & 1; unsigned NumTZ = CountTrailingZeros_32(Mask); unsigned char CCBits = (unsigned char)Firstcond & 0xf; unsigned Pos; //assert(NumTZ <= 3 && "Invalid IT mask!"); // push condition codes onto the stack the correct order for the pops for (Pos = NumTZ + 1; Pos <= 3; ++Pos) { bool T = ((Mask >> Pos) & 1) == (int)CondBit0; if (T) ITStatus_push_back(it, CCBits); else ITStatus_push_back(it, CCBits ^ 1); } ITStatus_push_back(it, CCBits); } /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. static bool Check(DecodeStatus *Out, DecodeStatus In) { switch (In) { case MCDisassembler_Success: // Out stays the same. return true; case MCDisassembler_SoftFail: *Out = In; return true; case MCDisassembler_Fail: *Out = In; return false; default: // never reached return false; } } // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, unsigned Insn, uint64_t Adddress, const void *Decoder); static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder); static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder); static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder); static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder); static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); // Hacky: enable all features for disassembler bool ARM_getFeatureBits(unsigned int mode, unsigned int feature) { if ((mode & CS_MODE_V8) == 0) { // not V8 mode if (feature == ARM_HasV8Ops || feature == ARM_HasV8_1aOps || feature == ARM_HasV8_4aOps || feature == ARM_HasV8_3aOps) // HasV8MBaselineOps return false; } else { if (feature == ARM_FeatureVFPOnlySP) return false; } if ((mode & CS_MODE_MCLASS) == 0) { if (feature == ARM_FeatureMClass) return false; } if ((mode & CS_MODE_THUMB) == 0) { // not Thumb if (feature == ARM_FeatureThumb2 || feature == ARM_ModeThumb) return false; // FIXME: what mode enables D16? if (feature == ARM_FeatureD16) return false; } else { // Thumb if (feature == ARM_FeatureD16) return false; } if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0) return false; // we support everything return true; } #include "ARMGenDisassemblerTables.inc" static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val == 0xF) return MCDisassembler_Fail; // AL predicate is not allowed on Thumb1 branches. if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Val); if (Val == ARMCC_AL) { MCOperand_CreateReg0(Inst, 0); } else MCOperand_CreateReg0(Inst, ARM_CPSR); return MCDisassembler_Success; } #define GET_REGINFO_MC_DESC #include "ARMGenRegisterInfo.inc" void ARM_init(MCRegisterInfo *MRI) { /* InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 103, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, ARMSubRegIdxLists, 57, ARMSubRegIdxRanges, ARMRegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, 0, 0, ARMMCRegisterClasses, 103, 0, 0, ARMRegDiffLists, 0, ARMSubRegIdxLists, 57, 0); } // Post-decoding checks static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn, DecodeStatus Result) { switch (MCInst_getOpcode(MI)) { case ARM_HVC: { // HVC is undefined if condition = 0xf otherwise upredictable // if condition != 0xe uint32_t Cond = (Insn >> 28) & 0xF; if (Cond == 0xF) return MCDisassembler_Fail; if (Cond != 0xE) return MCDisassembler_SoftFail; return Result; } default: return Result; } } static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address) { uint32_t insn; DecodeStatus result; *Size = 0; if (code_len < 4) // not enough data return MCDisassembler_Fail; if (MI->flat_insn->detail) { unsigned int i; memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm)); for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { MI->flat_insn->detail->arm.operands[i].vector_index = -1; MI->flat_insn->detail->arm.operands[i].neon_lane = -1; } } if (MODE_IS_BIG_ENDIAN(ud->mode)) insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); else insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | (code[1] << 8) | (code[0] << 0); // Calling the auto-generated decoder function. result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address); if (result != MCDisassembler_Fail) { result = checkDecodedInstruction(MI, insn, result); if (result != MCDisassembler_Fail) *Size = 4; return result; } // VFP and NEON instructions, similarly, are shared between ARM // and Thumb modes. MCInst_clear(MI); result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) return MCDisassembler_Fail; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) return MCDisassembler_Fail; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) return MCDisassembler_Fail; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } result = decodeInstruction_4(DecoderTableCoProc32, MI, insn, Address); if (result != MCDisassembler_Fail) { result = checkDecodedInstruction(MI, insn, result); if (result != MCDisassembler_Fail) *Size = 4; return result; } MCInst_clear(MI); *Size = 0; return MCDisassembler_Fail; } // Thumb1 instructions don't have explicit S bits. Rather, they // implicitly set CPSR. Since it's not represented in the encoding, the // auto-generated decoder won't inject the CPSR operand. We need to fix // that as a post-pass. static void AddThumb1SBit(MCInst *MI, bool InITBlock) { const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; unsigned i; for (i = 0; i < NumOps; ++i) { if (i == MCInst_getNumOperands(MI)) break; if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) continue; MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); return; } } //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); } // Most Thumb instructions don't have explicit predicates in the // encoding, but rather get their predicates from IT context. We need // to fix up the predicate operands using this context information as a // post-pass. static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) { DecodeStatus S = MCDisassembler_Success; const MCOperandInfo *OpInfo; unsigned short NumOps; unsigned int i; unsigned CC; // A few instructions actually have predicates encoded in them. Don't // try to overwrite it if we're seeing one of those. switch (MCInst_getOpcode(MI)) { case ARM_tBcc: case ARM_t2Bcc: case ARM_tCBZ: case ARM_tCBNZ: case ARM_tCPS: case ARM_t2CPS3p: case ARM_t2CPS2p: case ARM_t2CPS1p: case ARM_tMOVSr: case ARM_tSETEND: // Some instructions (mostly conditional branches) are not // allowed in IT blocks. if (ITStatus_instrInITBlock(&(ud->ITBlock))) S = MCDisassembler_SoftFail; else return MCDisassembler_Success; break; case ARM_t2HINT: if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0x10) S = MCDisassembler_SoftFail; break; case ARM_tB: case ARM_t2B: case ARM_t2TBB: case ARM_t2TBH: // Some instructions (mostly unconditional branches) can // only appears at the end of, or outside of, an IT. // if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) S = MCDisassembler_SoftFail; break; default: break; } // If we're in an IT block, base the predicate on that. Otherwise, // assume a predicate of AL. CC = ITStatus_getITCC(&(ud->ITBlock)); if (CC == 0xF) CC = ARMCC_AL; if (ITStatus_instrInITBlock(&(ud->ITBlock))) ITStatus_advanceITState(&(ud->ITBlock)); OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; for (i = 0; i < NumOps; ++i) { if (i == MCInst_getNumOperands(MI)) break; if (MCOperandInfo_isPredicate(&OpInfo[i])) { MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); if (CC == ARMCC_AL) MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); else MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); return S; } } MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); if (CC == ARMCC_AL) MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0)); else MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR)); return S; } // Thumb VFP instructions are a special case. Because we share their // encodings between ARM and Thumb modes, and they are predicable in ARM // mode, the auto-generated decoder will give them an (incorrect) // predicate operand. We need to rewrite these operands based on the IT // context as a post-pass. static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) { unsigned CC; unsigned short NumOps; const MCOperandInfo *OpInfo; unsigned i; CC = ITStatus_getITCC(&(ud->ITBlock)); if (ITStatus_instrInITBlock(&(ud->ITBlock))) ITStatus_advanceITState(&(ud->ITBlock)); OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; for (i = 0; i < NumOps; ++i) { if (MCOperandInfo_isPredicate(&OpInfo[i])) { MCOperand_setImm(MCInst_getOperand(MI, i), CC); if (CC == ARMCC_AL) MCOperand_setReg(MCInst_getOperand(MI, i + 1), 0); else MCOperand_setReg(MCInst_getOperand(MI, i + 1), ARM_CPSR); return; } } } static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address) { uint16_t insn16; DecodeStatus result; bool InITBlock; unsigned Firstcond, Mask; uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; size_t i; // We want to read exactly 2 bytes of data. if (code_len < 2) // not enough data return MCDisassembler_Fail; if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm)); for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) { MI->flat_insn->detail->arm.operands[i].vector_index = -1; MI->flat_insn->detail->arm.operands[i].neon_lane = -1; } } if (MODE_IS_BIG_ENDIAN(ud->mode)) insn16 = (code[0] << 8) | code[1]; else insn16 = (code[1] << 8) | code[0]; result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address); if (result != MCDisassembler_Fail) { *Size = 2; Check(&result, AddThumbPredicate(ud, MI)); return result; } MCInst_clear(MI); result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address); if (result) { *Size = 2; InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); Check(&result, AddThumbPredicate(ud, MI)); AddThumb1SBit(MI, InITBlock); return result; } MCInst_clear(MI); result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address); if (result != MCDisassembler_Fail) { *Size = 2; // Nested IT blocks are UNPREDICTABLE. Must be checked before we add // the Thumb predicate. if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) return MCDisassembler_SoftFail; Check(&result, AddThumbPredicate(ud, MI)); // If we find an IT instruction, we need to parse its condition // code and mask operands so that we can apply them correctly // to the subsequent instructions. if (MCInst_getOpcode(MI) == ARM_t2IT) { Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); // An IT instruction that would give a 'NV' predicate is unpredictable. // if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask)) // CS << "unpredictable IT predicate sequence"; } return result; } // We want to read exactly 4 bytes of data. if (code_len < 4) // not enough data return MCDisassembler_Fail; if (MODE_IS_BIG_ENDIAN(ud->mode)) insn32 = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); else insn32 = (code[3] << 8) | (code[2] << 0) | ((uint32_t) code[1] << 24) | (code[0] << 16); MCInst_clear(MI); result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address); if (result != MCDisassembler_Fail) { *Size = 4; InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); Check(&result, AddThumbPredicate(ud, MI)); AddThumb1SBit(MI, InITBlock); return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address); if (result != MCDisassembler_Fail) { *Size = 4; Check(&result, AddThumbPredicate(ud, MI)); return result; } if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { MCInst_clear(MI); result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address); if (result != MCDisassembler_Fail) { *Size = 4; UpdateThumbVFPPredicate(ud, MI); return result; } } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { MCInst_clear(MI); result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address); if (result != MCDisassembler_Fail) { *Size = 4; Check(&result, AddThumbPredicate(ud, MI)); return result; } } if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { MCInst_clear(MI); NEONLdStInsn = insn32; NEONLdStInsn &= 0xF0FFFFFF; NEONLdStInsn |= 0x04000000; result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address); if (result != MCDisassembler_Fail) { *Size = 4; Check(&result, AddThumbPredicate(ud, MI)); return result; } } if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { MCInst_clear(MI); NEONDataInsn = insn32; NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address); if (result != MCDisassembler_Fail) { *Size = 4; Check(&result, AddThumbPredicate(ud, MI)); return result; } } MCInst_clear(MI); NEONCryptoInsn = insn32; NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } MCInst_clear(MI); NEONv8Insn = insn32; NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } MCInst_clear(MI); result = decodeInstruction_4(DecoderTableThumb2CoProc32, MI, insn32, Address); if (result != MCDisassembler_Fail) { *Size = 4; Check(&result, AddThumbPredicate(ud, MI)); return result; } MCInst_clear(MI); *Size = 0; return MCDisassembler_Fail; } bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); // TODO: fix table gen to eliminate these special cases if (instr->Opcode == ARM_t__brkdiv0) return false; //return status == MCDisassembler_Success; return status != MCDisassembler_Fail; } bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); //return status == MCDisassembler_Success; return status != MCDisassembler_Fail; } static const uint16_t GPRDecoderTable[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC }; static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 15) return MCDisassembler_Fail; Register = GPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; if (RegNo == 15) S = MCDisassembler_SoftFail; Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; if (RegNo == 15) { MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); return MCDisassembler_Success; } Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) return MCDisassembler_Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } static const uint16_t GPRPairDecoderTable[] = { ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP }; static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned RegisterPair; DecodeStatus S = MCDisassembler_Success; if (RegNo > 13) return MCDisassembler_Fail; if ((RegNo & 1) || RegNo == 0xe) S = MCDisassembler_SoftFail; RegisterPair = GPRPairDecoderTable[RegNo / 2]; MCOperand_CreateReg0(Inst, RegisterPair); return S; } static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register = 0; switch (RegNo) { case 0: Register = ARM_R0; break; case 1: Register = ARM_R1; break; case 2: Register = ARM_R2; break; case 3: Register = ARM_R3; break; case 9: Register = ARM_R9; break; case 12: Register = ARM_R12; break; default: return MCDisassembler_Fail; } MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; if ((RegNo == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) || RegNo == 15) S = MCDisassembler_SoftFail; Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); return S; } static const uint16_t SPRDecoderTable[] = { ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31 }; static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31) return MCDisassembler_Fail; Register = SPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); } static const uint16_t DPRDecoderTable[] = { ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31 }; static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31 || (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD16) && RegNo > 15)) return MCDisassembler_Fail; Register = DPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 7) return MCDisassembler_Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 15) return MCDisassembler_Fail; return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); } static const uint16_t QPRDecoderTable[] = { ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 }; static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 31 || (RegNo & 1) != 0) return MCDisassembler_Fail; RegNo >>= 1; Register = QPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static const uint16_t DPairDecoderTable[] = { ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15 }; static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 30) return MCDisassembler_Fail; Register = DPairDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static const uint16_t DPairSpacedDecoderTable[] = { ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31 }; static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Register; if (RegNo > 29) return MCDisassembler_Fail; Register = DPairSpacedDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); return MCDisassembler_Success; } static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val) MCOperand_CreateReg0(Inst, ARM_CPSR); else MCOperand_CreateReg0(Inst, 0); return MCDisassembler_Success; } static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; ARM_AM_ShiftOpc Shift; unsigned Op; unsigned Rm = fieldFromInstruction_4(Val, 0, 4); unsigned type = fieldFromInstruction_4(Val, 5, 2); unsigned imm = fieldFromInstruction_4(Val, 7, 5); // Register-immediate if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; Shift = ARM_AM_lsl; switch (type) { case 0: Shift = ARM_AM_lsl; break; case 1: Shift = ARM_AM_lsr; break; case 2: Shift = ARM_AM_asr; break; case 3: Shift = ARM_AM_ror; break; } if (Shift == ARM_AM_ror && imm == 0) Shift = ARM_AM_rrx; Op = Shift | (imm << 3); MCOperand_CreateImm0(Inst, Op); return S; } static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; ARM_AM_ShiftOpc Shift; unsigned Rm = fieldFromInstruction_4(Val, 0, 4); unsigned type = fieldFromInstruction_4(Val, 5, 2); unsigned Rs = fieldFromInstruction_4(Val, 8, 4); // Register-register if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) return MCDisassembler_Fail; Shift = ARM_AM_lsl; switch (type) { case 0: Shift = ARM_AM_lsl; break; case 1: Shift = ARM_AM_lsr; break; case 2: Shift = ARM_AM_asr; break; case 3: Shift = ARM_AM_ror; break; } MCOperand_CreateImm0(Inst, Shift); return S; } static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { unsigned i; DecodeStatus S = MCDisassembler_Success; unsigned opcode; bool NeedDisjointWriteback = false; unsigned WritebackReg = 0; opcode = MCInst_getOpcode(Inst); switch (opcode) { default: break; case ARM_LDMIA_UPD: case ARM_LDMDB_UPD: case ARM_LDMIB_UPD: case ARM_LDMDA_UPD: case ARM_t2LDMIA_UPD: case ARM_t2LDMDB_UPD: case ARM_t2STMIA_UPD: case ARM_t2STMDB_UPD: NeedDisjointWriteback = true; WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); break; } // Empty register lists are not allowed. if (Val == 0) return MCDisassembler_Fail; for (i = 0; i < 16; ++i) { if (Val & (1 << i)) { if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) return MCDisassembler_Fail; // Writeback not allowed if Rn is in the target list. if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size - 1]))) Check(&S, MCDisassembler_SoftFail); } } return S; } static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned i; unsigned Vd = fieldFromInstruction_4(Val, 8, 5); unsigned regs = fieldFromInstruction_4(Val, 0, 8); // In case of unpredictable encoding, tweak the operands. if (regs == 0 || (Vd + regs) > 32) { regs = Vd + regs > 32 ? 32 - Vd : regs; regs = (1u > regs? 1u : regs); S = MCDisassembler_SoftFail; } if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; for (i = 0; i < (regs - 1); ++i) { if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler_Fail; } return S; } static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned i; unsigned Vd = fieldFromInstruction_4(Val, 8, 5); unsigned regs = fieldFromInstruction_4(Val, 1, 7); // In case of unpredictable encoding, tweak the operands. if (regs == 0 || regs > 16 || (Vd + regs) > 32) { regs = Vd + regs > 32 ? 32 - Vd : regs; regs = (1u > regs? 1u : regs); regs = (16u > regs? regs : 16u); S = MCDisassembler_SoftFail; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; for (i = 0; i < (regs - 1); ++i) { if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) return MCDisassembler_Fail; } return S; } static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { // This operand encodes a mask of contiguous zeros between a specified MSB // and LSB. To decode it, we create the mask of all bits MSB-and-lower, // the mask of all bits LSB-and-lower, and then xor them to create // the mask of that's all ones on [msb, lsb]. Finally we not it to // create the final mask. unsigned msb = fieldFromInstruction_4(Val, 5, 5); unsigned lsb = fieldFromInstruction_4(Val, 0, 5); uint32_t lsb_mask, msb_mask; DecodeStatus S = MCDisassembler_Success; if (lsb > msb) { Check(&S, MCDisassembler_SoftFail); // The check above will cause the warning for the "potentially undefined // instruction encoding" but we can't build a bad MCOperand value here // with a lsb > msb or else printing the MCInst will cause a crash. lsb = msb; } msb_mask = 0xFFFFFFFF; if (msb != 31) msb_mask = (1U << (msb + 1)) - 1; lsb_mask = (1U << lsb) - 1; MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); return S; } static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 8); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned U = fieldFromInstruction_4(Insn, 23, 1); switch (MCInst_getOpcode(Inst)) { case ARM_LDC_OFFSET: case ARM_LDC_PRE: case ARM_LDC_POST: case ARM_LDC_OPTION: case ARM_LDCL_OFFSET: case ARM_LDCL_PRE: case ARM_LDCL_POST: case ARM_LDCL_OPTION: case ARM_STC_OFFSET: case ARM_STC_PRE: case ARM_STC_POST: case ARM_STC_OPTION: case ARM_STCL_OFFSET: case ARM_STCL_PRE: case ARM_STCL_POST: case ARM_STCL_OPTION: case ARM_t2LDC_OFFSET: case ARM_t2LDC_PRE: case ARM_t2LDC_POST: case ARM_t2LDC_OPTION: case ARM_t2LDCL_OFFSET: case ARM_t2LDCL_PRE: case ARM_t2LDCL_POST: case ARM_t2LDCL_OPTION: case ARM_t2STC_OFFSET: case ARM_t2STC_PRE: case ARM_t2STC_POST: case ARM_t2STC_OPTION: case ARM_t2STCL_OFFSET: case ARM_t2STCL_PRE: case ARM_t2STCL_POST: case ARM_t2STCL_OPTION: if (coproc == 0xA || coproc == 0xB) return MCDisassembler_Fail; break; default: break; } if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14)) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, coproc); MCOperand_CreateImm0(Inst, CRd); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; switch (MCInst_getOpcode(Inst)) { case ARM_t2LDC2_OFFSET: case ARM_t2LDC2L_OFFSET: case ARM_t2LDC2_PRE: case ARM_t2LDC2L_PRE: case ARM_t2STC2_OFFSET: case ARM_t2STC2L_OFFSET: case ARM_t2STC2_PRE: case ARM_t2STC2L_PRE: case ARM_LDC2_OFFSET: case ARM_LDC2L_OFFSET: case ARM_LDC2_PRE: case ARM_LDC2L_PRE: case ARM_STC2_OFFSET: case ARM_STC2L_OFFSET: case ARM_STC2_PRE: case ARM_STC2L_PRE: case ARM_t2LDC_OFFSET: case ARM_t2LDCL_OFFSET: case ARM_t2LDC_PRE: case ARM_t2LDCL_PRE: case ARM_t2STC_OFFSET: case ARM_t2STCL_OFFSET: case ARM_t2STC_PRE: case ARM_t2STCL_PRE: case ARM_LDC_OFFSET: case ARM_LDCL_OFFSET: case ARM_LDC_PRE: case ARM_LDCL_PRE: case ARM_STC_OFFSET: case ARM_STCL_OFFSET: case ARM_STC_PRE: case ARM_STCL_PRE: imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); MCOperand_CreateImm0(Inst, imm); break; case ARM_t2LDC2_POST: case ARM_t2LDC2L_POST: case ARM_t2STC2_POST: case ARM_t2STC2L_POST: case ARM_LDC2_POST: case ARM_LDC2L_POST: case ARM_STC2_POST: case ARM_STC2L_POST: case ARM_t2LDC_POST: case ARM_t2LDCL_POST: case ARM_t2STC_POST: case ARM_t2STCL_POST: case ARM_LDC_POST: case ARM_LDCL_POST: case ARM_STC_POST: case ARM_STCL_POST: imm |= U << 8; // fall through. default: // The 'option' variant doesn't encode 'U' in the immediate since // the immediate is unsigned [0,255]. MCOperand_CreateImm0(Inst, imm); break; } switch (MCInst_getOpcode(Inst)) { case ARM_LDC_OFFSET: case ARM_LDC_PRE: case ARM_LDC_POST: case ARM_LDC_OPTION: case ARM_LDCL_OFFSET: case ARM_LDCL_PRE: case ARM_LDCL_POST: case ARM_LDCL_OPTION: case ARM_STC_OFFSET: case ARM_STC_PRE: case ARM_STC_POST: case ARM_STC_OPTION: case ARM_STCL_OFFSET: case ARM_STCL_PRE: case ARM_STCL_POST: case ARM_STCL_OPTION: if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } return S; } static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; ARM_AM_AddrOpc Op; ARM_AM_ShiftOpc Opc; bool writeback; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 12); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned reg = fieldFromInstruction_4(Insn, 25, 1); unsigned P = fieldFromInstruction_4(Insn, 24, 1); unsigned W = fieldFromInstruction_4(Insn, 21, 1); unsigned idx_mode = 0, amt, tmp; // On stores, the writeback operand precedes Rt. switch (MCInst_getOpcode(Inst)) { case ARM_STR_POST_IMM: case ARM_STR_POST_REG: case ARM_STRB_POST_IMM: case ARM_STRB_POST_REG: case ARM_STRT_POST_REG: case ARM_STRT_POST_IMM: case ARM_STRBT_POST_REG: case ARM_STRBT_POST_IMM: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; // On loads, the writeback operand comes after Rt. switch (MCInst_getOpcode(Inst)) { case ARM_LDR_POST_IMM: case ARM_LDR_POST_REG: case ARM_LDRB_POST_IMM: case ARM_LDRB_POST_REG: case ARM_LDRBT_POST_REG: case ARM_LDRBT_POST_IMM: case ARM_LDRT_POST_REG: case ARM_LDRT_POST_IMM: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; Op = ARM_AM_add; if (!fieldFromInstruction_4(Insn, 23, 1)) Op = ARM_AM_sub; writeback = (P == 0) || (W == 1); if (P && writeback) idx_mode = ARMII_IndexModePre; else if (!P && writeback) idx_mode = ARMII_IndexModePost; if (writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler_SoftFail; // UNPREDICTABLE if (reg) { if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; Opc = ARM_AM_lsl; switch(fieldFromInstruction_4(Insn, 5, 2)) { case 0: Opc = ARM_AM_lsl; break; case 1: Opc = ARM_AM_lsr; break; case 2: Opc = ARM_AM_asr; break; case 3: Opc = ARM_AM_ror; break; default: return MCDisassembler_Fail; } amt = fieldFromInstruction_4(Insn, 7, 5); if (Opc == ARM_AM_ror && amt == 0) Opc = ARM_AM_rrx; imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); MCOperand_CreateImm0(Inst, imm); } else { MCOperand_CreateReg0(Inst, 0); tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); MCOperand_CreateImm0(Inst, tmp); } if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; ARM_AM_ShiftOpc ShOp; unsigned shift; unsigned Rn = fieldFromInstruction_4(Val, 13, 4); unsigned Rm = fieldFromInstruction_4(Val, 0, 4); unsigned type = fieldFromInstruction_4(Val, 5, 2); unsigned imm = fieldFromInstruction_4(Val, 7, 5); unsigned U = fieldFromInstruction_4(Val, 12, 1); ShOp = ARM_AM_lsl; switch (type) { case 0: ShOp = ARM_AM_lsl; break; case 1: ShOp = ARM_AM_lsr; break; case 2: ShOp = ARM_AM_asr; break; case 3: ShOp = ARM_AM_ror; break; } if (ShOp == ARM_AM_ror && imm == 0) ShOp = ARM_AM_rrx; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (U) shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); else shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); MCOperand_CreateImm0(Inst, shift); return S; } static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned type = fieldFromInstruction_4(Insn, 22, 1); unsigned imm = fieldFromInstruction_4(Insn, 8, 4); unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned W = fieldFromInstruction_4(Insn, 21, 1); unsigned P = fieldFromInstruction_4(Insn, 24, 1); unsigned Rt2 = Rt + 1; bool writeback = (W == 1) | (P == 0); // For {LD,ST}RD, Rt must be even, else undefined. switch (MCInst_getOpcode(Inst)) { case ARM_STRD: case ARM_STRD_PRE: case ARM_STRD_POST: case ARM_LDRD: case ARM_LDRD_PRE: case ARM_LDRD_POST: if (Rt & 0x1) S = MCDisassembler_SoftFail; break; default: break; } switch (MCInst_getOpcode(Inst)) { case ARM_STRD: case ARM_STRD_PRE: case ARM_STRD_POST: if (P == 0 && W == 1) S = MCDisassembler_SoftFail; if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) S = MCDisassembler_SoftFail; if (type && Rm == 15) S = MCDisassembler_SoftFail; if (Rt2 == 15) S = MCDisassembler_SoftFail; if (!type && fieldFromInstruction_4(Insn, 8, 4)) S = MCDisassembler_SoftFail; break; case ARM_STRH: case ARM_STRH_PRE: case ARM_STRH_POST: if (Rt == 15) S = MCDisassembler_SoftFail; if (writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler_SoftFail; if (!type && Rm == 15) S = MCDisassembler_SoftFail; break; case ARM_LDRD: case ARM_LDRD_PRE: case ARM_LDRD_POST: if (type && Rn == 15) { if (Rt2 == 15) S = MCDisassembler_SoftFail; break; } if (P == 0 && W == 1) S = MCDisassembler_SoftFail; if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) S = MCDisassembler_SoftFail; if (!type && writeback && Rn == 15) S = MCDisassembler_SoftFail; if (writeback && (Rn == Rt || Rn == Rt2)) S = MCDisassembler_SoftFail; break; case ARM_LDRH: case ARM_LDRH_PRE: case ARM_LDRH_POST: if (type && Rn == 15) { if (Rt == 15) S = MCDisassembler_SoftFail; break; } if (Rt == 15) S = MCDisassembler_SoftFail; if (!type && Rm == 15) S = MCDisassembler_SoftFail; if (!type && writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler_SoftFail; break; case ARM_LDRSH: case ARM_LDRSH_PRE: case ARM_LDRSH_POST: case ARM_LDRSB: case ARM_LDRSB_PRE: case ARM_LDRSB_POST: if (type && Rn == 15){ if (Rt == 15) S = MCDisassembler_SoftFail; break; } if (type && (Rt == 15 || (writeback && Rn == Rt))) S = MCDisassembler_SoftFail; if (!type && (Rt == 15 || Rm == 15)) S = MCDisassembler_SoftFail; if (!type && writeback && (Rn == 15 || Rn == Rt)) S = MCDisassembler_SoftFail; break; default: break; } if (writeback) { // Writeback Inst->writeback = true; if (P) U |= ARMII_IndexModePre << 9; else U |= ARMII_IndexModePost << 9; // On stores, the writeback operand precedes Rt. switch (MCInst_getOpcode(Inst)) { case ARM_STRD: case ARM_STRD_PRE: case ARM_STRD_POST: case ARM_STRH: case ARM_STRH_PRE: case ARM_STRH_POST: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; switch (MCInst_getOpcode(Inst)) { case ARM_STRD: case ARM_STRD_PRE: case ARM_STRD_POST: case ARM_LDRD: case ARM_LDRD_PRE: case ARM_LDRD_POST: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } if (writeback) { // On loads, the writeback operand comes after Rt. switch (MCInst_getOpcode(Inst)) { case ARM_LDRD: case ARM_LDRD_PRE: case ARM_LDRD_POST: case ARM_LDRH: case ARM_LDRH_PRE: case ARM_LDRH_POST: case ARM_LDRSH: case ARM_LDRSH_PRE: case ARM_LDRSH_POST: case ARM_LDRSB: case ARM_LDRSB_PRE: case ARM_LDRSB_POST: case ARM_LDRHTr: case ARM_LDRSBTr: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (type) { MCOperand_CreateReg0(Inst, 0); MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); } else { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, U); } if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned mode = fieldFromInstruction_4(Insn, 23, 2); switch (mode) { case 0: mode = ARM_AM_da; break; case 1: mode = ARM_AM_ia; break; case 2: mode = ARM_AM_db; break; case 3: mode = ARM_AM_ib; break; } MCOperand_CreateImm0(Inst, mode); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); if (pred == 0xF) { // Ambiguous with RFE and SRS switch (MCInst_getOpcode(Inst)) { case ARM_LDMDA: MCInst_setOpcode(Inst, ARM_RFEDA); break; case ARM_LDMDA_UPD: MCInst_setOpcode(Inst, ARM_RFEDA_UPD); break; case ARM_LDMDB: MCInst_setOpcode(Inst, ARM_RFEDB); break; case ARM_LDMDB_UPD: MCInst_setOpcode(Inst, ARM_RFEDB_UPD); break; case ARM_LDMIA: MCInst_setOpcode(Inst, ARM_RFEIA); break; case ARM_LDMIA_UPD: MCInst_setOpcode(Inst, ARM_RFEIA_UPD); break; case ARM_LDMIB: MCInst_setOpcode(Inst, ARM_RFEIB); break; case ARM_LDMIB_UPD: MCInst_setOpcode(Inst, ARM_RFEIB_UPD); break; case ARM_STMDA: MCInst_setOpcode(Inst, ARM_SRSDA); break; case ARM_STMDA_UPD: MCInst_setOpcode(Inst, ARM_SRSDA_UPD); break; case ARM_STMDB: MCInst_setOpcode(Inst, ARM_SRSDB); break; case ARM_STMDB_UPD: MCInst_setOpcode(Inst, ARM_SRSDB_UPD); break; case ARM_STMIA: MCInst_setOpcode(Inst, ARM_SRSIA); break; case ARM_STMIA_UPD: MCInst_setOpcode(Inst, ARM_SRSIA_UPD); break; case ARM_STMIB: MCInst_setOpcode(Inst, ARM_SRSIB); break; case ARM_STMIB_UPD: MCInst_setOpcode(Inst, ARM_SRSIB_UPD); break; default: return MCDisassembler_Fail; } // For stores (which become SRS's, the only operand is the mode. if (fieldFromInstruction_4(Insn, 20, 1) == 0) { // Check SRS encoding constraints if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && fieldFromInstruction_4(Insn, 20, 1) == 0)) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); return S; } return DecodeRFEInstruction(Inst, Insn, Address, Decoder); } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; // Tied if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) return MCDisassembler_Fail; return S; } // Check for UNPREDICTABLE predicated ESB instruction static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8); DecodeStatus result = MCDisassembler_Success; MCOperand_CreateImm0(Inst, imm8); if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, // so all predicates should be allowed. if (imm8 == 0x10 && pred != 0xe && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) result = MCDisassembler_SoftFail; return result; } static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned imod = fieldFromInstruction_4(Insn, 18, 2); unsigned M = fieldFromInstruction_4(Insn, 17, 1); unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); unsigned mode = fieldFromInstruction_4(Insn, 0, 5); DecodeStatus S = MCDisassembler_Success; // This decoder is called from multiple location that do not check // the full encoding is valid before they do. if (fieldFromInstruction_4(Insn, 5, 1) != 0 || fieldFromInstruction_4(Insn, 16, 1) != 0 || fieldFromInstruction_4(Insn, 20, 8) != 0x10) return MCDisassembler_Fail; // imod == '01' --> UNPREDICTABLE // NOTE: Even though this is technically UNPREDICTABLE, we choose to // return failure here. The '01' imod value is unprintable, so there's // nothing useful we could do even if we returned UNPREDICTABLE. if (imod == 1) return MCDisassembler_Fail; if (imod && M) { MCInst_setOpcode(Inst, ARM_CPS3p); MCOperand_CreateImm0(Inst, imod); MCOperand_CreateImm0(Inst, iflags); MCOperand_CreateImm0(Inst, mode); } else if (imod && !M) { MCInst_setOpcode(Inst, ARM_CPS2p); MCOperand_CreateImm0(Inst, imod); MCOperand_CreateImm0(Inst, iflags); if (mode) S = MCDisassembler_SoftFail; } else if (!imod && M) { MCInst_setOpcode(Inst, ARM_CPS1p); MCOperand_CreateImm0(Inst, mode); if (iflags) S = MCDisassembler_SoftFail; } else { // imod == '00' && M == '0' --> UNPREDICTABLE MCInst_setOpcode(Inst, ARM_CPS1p); MCOperand_CreateImm0(Inst, mode); S = MCDisassembler_SoftFail; } return S; } static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned imod = fieldFromInstruction_4(Insn, 9, 2); unsigned M = fieldFromInstruction_4(Insn, 8, 1); unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); unsigned mode = fieldFromInstruction_4(Insn, 0, 5); DecodeStatus S = MCDisassembler_Success; // imod == '01' --> UNPREDICTABLE // NOTE: Even though this is technically UNPREDICTABLE, we choose to // return failure here. The '01' imod value is unprintable, so there's // nothing useful we could do even if we returned UNPREDICTABLE. if (imod == 1) return MCDisassembler_Fail; if (imod && M) { MCInst_setOpcode(Inst, ARM_t2CPS3p); MCOperand_CreateImm0(Inst, imod); MCOperand_CreateImm0(Inst, iflags); MCOperand_CreateImm0(Inst, mode); } else if (imod && !M) { MCInst_setOpcode(Inst, ARM_t2CPS2p); MCOperand_CreateImm0(Inst, imod); MCOperand_CreateImm0(Inst, iflags); if (mode) S = MCDisassembler_SoftFail; } else if (!imod && M) { MCInst_setOpcode(Inst, ARM_t2CPS1p); MCOperand_CreateImm0(Inst, mode); if (iflags) S = MCDisassembler_SoftFail; } else { // imod == '00' && M == '0' --> this is a HINT instruction int imm = fieldFromInstruction_4(Insn, 0, 8); // HINT are defined only for immediate in [0..4] if (imm > 4) return MCDisassembler_Fail; MCInst_setOpcode(Inst, ARM_t2HINT); MCOperand_CreateImm0(Inst, imm); } return S; } static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); unsigned imm = 0; imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned imm = 0; imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); if (MCInst_getOpcode(Inst) == ARM_MOVTi16) if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, imm); if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Pred = fieldFromInstruction_4(Insn, 28, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); if (Pred == 0xF) return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Imm = fieldFromInstruction_4(Insn, 9, 1); if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) || !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) return MCDisassembler_Fail; // Decoder can be called from DecodeTST, which does not check the full // encoding is valid. if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 || fieldFromInstruction_4(Insn, 4, 4) != 0) return MCDisassembler_Fail; if (fieldFromInstruction_4(Insn, 10, 10) != 0 || fieldFromInstruction_4(Insn, 0, 4) != 0) S = MCDisassembler_SoftFail; MCInst_setOpcode(Inst, ARM_SETPAN); MCOperand_CreateImm0(Inst, Imm); return S; } static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned add = fieldFromInstruction_4(Val, 12, 1); unsigned imm = fieldFromInstruction_4(Val, 0, 12); unsigned Rn = fieldFromInstruction_4(Val, 13, 4); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!add) imm *= (unsigned int)-1; if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; MCOperand_CreateImm0(Inst, imm); //if (Rn == 15) // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); return S; } static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 9, 4); // U == 1 to add imm, 0 to subtract it. unsigned U = fieldFromInstruction_4(Val, 8, 1); unsigned imm = fieldFromInstruction_4(Val, 0, 8); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (U) MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); else MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); return S; } static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 9, 4); // U == 1 to add imm, 0 to subtract it. unsigned U = fieldFromInstruction_4(Val, 8, 1); unsigned imm = fieldFromInstruction_4(Val, 0, 8); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (U) MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_add, imm)); else MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_sub, imm)); return S; } static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); } static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus Status = MCDisassembler_Success; // Note the J1 and J2 values are from the encoded instruction. So here // change them to I1 and I2 values via as documented: // I1 = NOT(J1 EOR S); // I2 = NOT(J2 EOR S); // and build the imm32 with one trailing zero as documented: // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); unsigned S = fieldFromInstruction_4(Insn, 26, 1); unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); unsigned I1 = !(J1 ^ S); unsigned I2 = !(J2 ^ S); unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; int imm32 = SignExtend32(tmp << 1, 25); MCOperand_CreateImm0(Inst, imm32); return Status; } static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred = fieldFromInstruction_4(Insn, 28, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; if (pred == 0xF) { MCInst_setOpcode(Inst, ARM_BLXi); imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); return S; } MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rm = fieldFromInstruction_4(Val, 0, 4); unsigned align = fieldFromInstruction_4(Val, 4, 2); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!align) MCOperand_CreateImm0(Inst, 0); else MCOperand_CreateImm0(Inst, 4 << align); return S; } static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned wb, Rn, Rm; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; wb = fieldFromInstruction_4(Insn, 16, 4); Rn = fieldFromInstruction_4(Insn, 16, 4); Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; Rm = fieldFromInstruction_4(Insn, 0, 4); // First output register switch (MCInst_getOpcode(Inst)) { case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VLD2b16: case ARM_VLD2b32: case ARM_VLD2b8: case ARM_VLD2b16wb_fixed: case ARM_VLD2b16wb_register: case ARM_VLD2b32wb_fixed: case ARM_VLD2b32wb_register: case ARM_VLD2b8wb_fixed: case ARM_VLD2b8wb_register: if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; } // Second output register switch (MCInst_getOpcode(Inst)) { case ARM_VLD3d8: case ARM_VLD3d16: case ARM_VLD3d32: case ARM_VLD3d8_UPD: case ARM_VLD3d16_UPD: case ARM_VLD3d32_UPD: case ARM_VLD4d8: case ARM_VLD4d16: case ARM_VLD4d32: case ARM_VLD4d8_UPD: case ARM_VLD4d16_UPD: case ARM_VLD4d32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VLD3q8: case ARM_VLD3q16: case ARM_VLD3q32: case ARM_VLD3q8_UPD: case ARM_VLD3q16_UPD: case ARM_VLD3q32_UPD: case ARM_VLD4q8: case ARM_VLD4q16: case ARM_VLD4q32: case ARM_VLD4q8_UPD: case ARM_VLD4q16_UPD: case ARM_VLD4q32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler_Fail; default: break; } // Third output register switch(MCInst_getOpcode(Inst)) { case ARM_VLD3d8: case ARM_VLD3d16: case ARM_VLD3d32: case ARM_VLD3d8_UPD: case ARM_VLD3d16_UPD: case ARM_VLD3d32_UPD: case ARM_VLD4d8: case ARM_VLD4d16: case ARM_VLD4d32: case ARM_VLD4d8_UPD: case ARM_VLD4d16_UPD: case ARM_VLD4d32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VLD3q8: case ARM_VLD3q16: case ARM_VLD3q32: case ARM_VLD3q8_UPD: case ARM_VLD3q16_UPD: case ARM_VLD3q32_UPD: case ARM_VLD4q8: case ARM_VLD4q16: case ARM_VLD4q32: case ARM_VLD4q8_UPD: case ARM_VLD4q16_UPD: case ARM_VLD4q32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } // Fourth output register switch (MCInst_getOpcode(Inst)) { case ARM_VLD4d8: case ARM_VLD4d16: case ARM_VLD4d32: case ARM_VLD4d8_UPD: case ARM_VLD4d16_UPD: case ARM_VLD4d32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VLD4q8: case ARM_VLD4q16: case ARM_VLD4q32: case ARM_VLD4q8_UPD: case ARM_VLD4q16_UPD: case ARM_VLD4q32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } // Writeback operand switch (MCInst_getOpcode(Inst)) { case ARM_VLD1d8wb_fixed: case ARM_VLD1d16wb_fixed: case ARM_VLD1d32wb_fixed: case ARM_VLD1d64wb_fixed: case ARM_VLD1d8wb_register: case ARM_VLD1d16wb_register: case ARM_VLD1d32wb_register: case ARM_VLD1d64wb_register: case ARM_VLD1q8wb_fixed: case ARM_VLD1q16wb_fixed: case ARM_VLD1q32wb_fixed: case ARM_VLD1q64wb_fixed: case ARM_VLD1q8wb_register: case ARM_VLD1q16wb_register: case ARM_VLD1q32wb_register: case ARM_VLD1q64wb_register: case ARM_VLD1d8Twb_fixed: case ARM_VLD1d8Twb_register: case ARM_VLD1d16Twb_fixed: case ARM_VLD1d16Twb_register: case ARM_VLD1d32Twb_fixed: case ARM_VLD1d32Twb_register: case ARM_VLD1d64Twb_fixed: case ARM_VLD1d64Twb_register: case ARM_VLD1d8Qwb_fixed: case ARM_VLD1d8Qwb_register: case ARM_VLD1d16Qwb_fixed: case ARM_VLD1d16Qwb_register: case ARM_VLD1d32Qwb_fixed: case ARM_VLD1d32Qwb_register: case ARM_VLD1d64Qwb_fixed: case ARM_VLD1d64Qwb_register: case ARM_VLD2d8wb_fixed: case ARM_VLD2d16wb_fixed: case ARM_VLD2d32wb_fixed: case ARM_VLD2q8wb_fixed: case ARM_VLD2q16wb_fixed: case ARM_VLD2q32wb_fixed: case ARM_VLD2d8wb_register: case ARM_VLD2d16wb_register: case ARM_VLD2d32wb_register: case ARM_VLD2q8wb_register: case ARM_VLD2q16wb_register: case ARM_VLD2q32wb_register: case ARM_VLD2b8wb_fixed: case ARM_VLD2b16wb_fixed: case ARM_VLD2b32wb_fixed: case ARM_VLD2b8wb_register: case ARM_VLD2b16wb_register: case ARM_VLD2b32wb_register: MCOperand_CreateImm0(Inst, 0); break; case ARM_VLD3d8_UPD: case ARM_VLD3d16_UPD: case ARM_VLD3d32_UPD: case ARM_VLD3q8_UPD: case ARM_VLD3q16_UPD: case ARM_VLD3q32_UPD: case ARM_VLD4d8_UPD: case ARM_VLD4d16_UPD: case ARM_VLD4d32_UPD: case ARM_VLD4q8_UPD: case ARM_VLD4q16_UPD: case ARM_VLD4q32_UPD: if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } // AddrMode6 Base (register+alignment) if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; // AddrMode6 Offset (register) switch (MCInst_getOpcode(Inst)) { default: // The below have been updated to have explicit am6offset split // between fixed and register offset. For those instructions not // yet updated, we need to add an additional reg0 operand for the // fixed variant. // // The fixed offset encodes as Rm == 0xd, so we check for that. if (Rm == 0xd) { MCOperand_CreateReg0(Inst, 0); break; } // Fall through to handle the register offset variant. case ARM_VLD1d8wb_fixed: case ARM_VLD1d16wb_fixed: case ARM_VLD1d32wb_fixed: case ARM_VLD1d64wb_fixed: case ARM_VLD1d8Twb_fixed: case ARM_VLD1d16Twb_fixed: case ARM_VLD1d32Twb_fixed: case ARM_VLD1d64Twb_fixed: case ARM_VLD1d8Qwb_fixed: case ARM_VLD1d16Qwb_fixed: case ARM_VLD1d32Qwb_fixed: case ARM_VLD1d64Qwb_fixed: case ARM_VLD1d8wb_register: case ARM_VLD1d16wb_register: case ARM_VLD1d32wb_register: case ARM_VLD1d64wb_register: case ARM_VLD1q8wb_fixed: case ARM_VLD1q16wb_fixed: case ARM_VLD1q32wb_fixed: case ARM_VLD1q64wb_fixed: case ARM_VLD1q8wb_register: case ARM_VLD1q16wb_register: case ARM_VLD1q32wb_register: case ARM_VLD1q64wb_register: // The fixed offset post-increment encodes Rm == 0xd. The no-writeback // variant encodes Rm == 0xf. Anything else is a register offset post- // increment and we need to add the register operand to the instruction. if (Rm != 0xD && Rm != 0xF && !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VLD2d8wb_fixed: case ARM_VLD2d16wb_fixed: case ARM_VLD2d32wb_fixed: case ARM_VLD2b8wb_fixed: case ARM_VLD2b16wb_fixed: case ARM_VLD2b32wb_fixed: case ARM_VLD2q8wb_fixed: case ARM_VLD2q16wb_fixed: case ARM_VLD2q32wb_fixed: break; } return S; } static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned load; unsigned type = fieldFromInstruction_4(Insn, 8, 4); unsigned align = fieldFromInstruction_4(Insn, 4, 2); if (type == 6 && (align & 2)) return MCDisassembler_Fail; if (type == 7 && (align & 2)) return MCDisassembler_Fail; if (type == 10 && align == 3) return MCDisassembler_Fail; load = fieldFromInstruction_4(Insn, 21, 1); return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : DecodeVSTInstruction(Inst, Insn, Address, Decoder); } static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned type, align, load; unsigned size = fieldFromInstruction_4(Insn, 6, 2); if (size == 3) return MCDisassembler_Fail; type = fieldFromInstruction_4(Insn, 8, 4); align = fieldFromInstruction_4(Insn, 4, 2); if (type == 8 && align == 3) return MCDisassembler_Fail; if (type == 9 && align == 3) return MCDisassembler_Fail; load = fieldFromInstruction_4(Insn, 21, 1); return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : DecodeVSTInstruction(Inst, Insn, Address, Decoder); } static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned align, load; unsigned size = fieldFromInstruction_4(Insn, 6, 2); if (size == 3) return MCDisassembler_Fail; align = fieldFromInstruction_4(Insn, 4, 2); if (align & 2) return MCDisassembler_Fail; load = fieldFromInstruction_4(Insn, 21, 1); return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : DecodeVSTInstruction(Inst, Insn, Address, Decoder); } static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned load; unsigned size = fieldFromInstruction_4(Insn, 6, 2); if (size == 3) return MCDisassembler_Fail; load = fieldFromInstruction_4(Insn, 21, 1); return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) : DecodeVSTInstruction(Inst, Insn, Address, Decoder); } static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned wb, Rn, Rm; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; wb = fieldFromInstruction_4(Insn, 16, 4); Rn = fieldFromInstruction_4(Insn, 16, 4); Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; Rm = fieldFromInstruction_4(Insn, 0, 4); // Writeback Operand switch (MCInst_getOpcode(Inst)) { case ARM_VST1d8wb_fixed: case ARM_VST1d16wb_fixed: case ARM_VST1d32wb_fixed: case ARM_VST1d64wb_fixed: case ARM_VST1d8wb_register: case ARM_VST1d16wb_register: case ARM_VST1d32wb_register: case ARM_VST1d64wb_register: case ARM_VST1q8wb_fixed: case ARM_VST1q16wb_fixed: case ARM_VST1q32wb_fixed: case ARM_VST1q64wb_fixed: case ARM_VST1q8wb_register: case ARM_VST1q16wb_register: case ARM_VST1q32wb_register: case ARM_VST1q64wb_register: case ARM_VST1d8Twb_fixed: case ARM_VST1d16Twb_fixed: case ARM_VST1d32Twb_fixed: case ARM_VST1d64Twb_fixed: case ARM_VST1d8Twb_register: case ARM_VST1d16Twb_register: case ARM_VST1d32Twb_register: case ARM_VST1d64Twb_register: case ARM_VST1d8Qwb_fixed: case ARM_VST1d16Qwb_fixed: case ARM_VST1d32Qwb_fixed: case ARM_VST1d64Qwb_fixed: case ARM_VST1d8Qwb_register: case ARM_VST1d16Qwb_register: case ARM_VST1d32Qwb_register: case ARM_VST1d64Qwb_register: case ARM_VST2d8wb_fixed: case ARM_VST2d16wb_fixed: case ARM_VST2d32wb_fixed: case ARM_VST2d8wb_register: case ARM_VST2d16wb_register: case ARM_VST2d32wb_register: case ARM_VST2q8wb_fixed: case ARM_VST2q16wb_fixed: case ARM_VST2q32wb_fixed: case ARM_VST2q8wb_register: case ARM_VST2q16wb_register: case ARM_VST2q32wb_register: case ARM_VST2b8wb_fixed: case ARM_VST2b16wb_fixed: case ARM_VST2b32wb_fixed: case ARM_VST2b8wb_register: case ARM_VST2b16wb_register: case ARM_VST2b32wb_register: if (Rm == 0xF) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, 0); break; case ARM_VST3d8_UPD: case ARM_VST3d16_UPD: case ARM_VST3d32_UPD: case ARM_VST3q8_UPD: case ARM_VST3q16_UPD: case ARM_VST3q32_UPD: case ARM_VST4d8_UPD: case ARM_VST4d16_UPD: case ARM_VST4d32_UPD: case ARM_VST4q8_UPD: case ARM_VST4q16_UPD: case ARM_VST4q32_UPD: if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } // AddrMode6 Base (register+alignment) if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; // AddrMode6 Offset (register) switch (MCInst_getOpcode(Inst)) { default: if (Rm == 0xD) MCOperand_CreateReg0(Inst, 0); else if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } break; case ARM_VST1d8wb_fixed: case ARM_VST1d16wb_fixed: case ARM_VST1d32wb_fixed: case ARM_VST1d64wb_fixed: case ARM_VST1q8wb_fixed: case ARM_VST1q16wb_fixed: case ARM_VST1q32wb_fixed: case ARM_VST1q64wb_fixed: case ARM_VST1d8Twb_fixed: case ARM_VST1d16Twb_fixed: case ARM_VST1d32Twb_fixed: case ARM_VST1d64Twb_fixed: case ARM_VST1d8Qwb_fixed: case ARM_VST1d16Qwb_fixed: case ARM_VST1d32Qwb_fixed: case ARM_VST1d64Qwb_fixed: case ARM_VST2d8wb_fixed: case ARM_VST2d16wb_fixed: case ARM_VST2d32wb_fixed: case ARM_VST2q8wb_fixed: case ARM_VST2q16wb_fixed: case ARM_VST2q32wb_fixed: case ARM_VST2b8wb_fixed: case ARM_VST2b16wb_fixed: case ARM_VST2b32wb_fixed: break; } // First input register switch (MCInst_getOpcode(Inst)) { case ARM_VST1q16: case ARM_VST1q32: case ARM_VST1q64: case ARM_VST1q8: case ARM_VST1q16wb_fixed: case ARM_VST1q16wb_register: case ARM_VST1q32wb_fixed: case ARM_VST1q32wb_register: case ARM_VST1q64wb_fixed: case ARM_VST1q64wb_register: case ARM_VST1q8wb_fixed: case ARM_VST1q8wb_register: case ARM_VST2d16: case ARM_VST2d32: case ARM_VST2d8: case ARM_VST2d16wb_fixed: case ARM_VST2d16wb_register: case ARM_VST2d32wb_fixed: case ARM_VST2d32wb_register: case ARM_VST2d8wb_fixed: case ARM_VST2d8wb_register: if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VST2b16: case ARM_VST2b32: case ARM_VST2b8: case ARM_VST2b16wb_fixed: case ARM_VST2b16wb_register: case ARM_VST2b32wb_fixed: case ARM_VST2b32wb_register: case ARM_VST2b8wb_fixed: case ARM_VST2b8wb_register: if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; } // Second input register switch (MCInst_getOpcode(Inst)) { case ARM_VST3d8: case ARM_VST3d16: case ARM_VST3d32: case ARM_VST3d8_UPD: case ARM_VST3d16_UPD: case ARM_VST3d32_UPD: case ARM_VST4d8: case ARM_VST4d16: case ARM_VST4d32: case ARM_VST4d8_UPD: case ARM_VST4d16_UPD: case ARM_VST4d32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VST3q8: case ARM_VST3q16: case ARM_VST3q32: case ARM_VST3q8_UPD: case ARM_VST3q16_UPD: case ARM_VST3q32_UPD: case ARM_VST4q8: case ARM_VST4q16: case ARM_VST4q32: case ARM_VST4q8_UPD: case ARM_VST4q16_UPD: case ARM_VST4q32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } // Third input register switch (MCInst_getOpcode(Inst)) { case ARM_VST3d8: case ARM_VST3d16: case ARM_VST3d32: case ARM_VST3d8_UPD: case ARM_VST3d16_UPD: case ARM_VST3d32_UPD: case ARM_VST4d8: case ARM_VST4d16: case ARM_VST4d32: case ARM_VST4d8_UPD: case ARM_VST4d16_UPD: case ARM_VST4d32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VST3q8: case ARM_VST3q16: case ARM_VST3q32: case ARM_VST3q8_UPD: case ARM_VST3q16_UPD: case ARM_VST3q32_UPD: case ARM_VST4q8: case ARM_VST4q16: case ARM_VST4q32: case ARM_VST4q8_UPD: case ARM_VST4q16_UPD: case ARM_VST4q32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } // Fourth input register switch (MCInst_getOpcode(Inst)) { case ARM_VST4d8: case ARM_VST4d16: case ARM_VST4d32: case ARM_VST4d8_UPD: case ARM_VST4d16_UPD: case ARM_VST4d32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VST4q8: case ARM_VST4q16: case ARM_VST4q32: case ARM_VST4q8_UPD: case ARM_VST4q16_UPD: case ARM_VST4q32_UPD: if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } return S; } static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn, Rm, align, size; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; Rn = fieldFromInstruction_4(Insn, 16, 4); Rm = fieldFromInstruction_4(Insn, 0, 4); align = fieldFromInstruction_4(Insn, 4, 1); size = fieldFromInstruction_4(Insn, 6, 2); if (size == 0 && align == 1) return MCDisassembler_Fail; align *= (1 << size); switch (MCInst_getOpcode(Inst)) { case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; } if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); // The fixed offset post-increment encodes Rm == 0xd. The no-writeback // variant encodes Rm == 0xf. Anything else is a register offset post- // increment and we need to add the register operand to the instruction. if (Rm != 0xD && Rm != 0xF && !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn, Rm, align, size; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; Rn = fieldFromInstruction_4(Insn, 16, 4); Rm = fieldFromInstruction_4(Insn, 0, 4); align = fieldFromInstruction_4(Insn, 4, 1); size = 1 << fieldFromInstruction_4(Insn, 6, 2); align *= 2 * size; switch (MCInst_getOpcode(Inst)) { case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; } if (Rm != 0xF) MCOperand_CreateImm0(Inst, 0); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xD && Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } return S; } static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn, Rm, inc; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; Rn = fieldFromInstruction_4(Insn, 16, 4); Rm = fieldFromInstruction_4(Insn, 0, 4); inc = fieldFromInstruction_4(Insn, 5, 1) + 1; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) return MCDisassembler_Fail; if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, 0); if (Rm == 0xD) MCOperand_CreateReg0(Inst, 0); else if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } return S; } static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn, Rm, size, inc, align; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; Rn = fieldFromInstruction_4(Insn, 16, 4); Rm = fieldFromInstruction_4(Insn, 0, 4); size = fieldFromInstruction_4(Insn, 6, 2); inc = fieldFromInstruction_4(Insn, 5, 1) + 1; align = fieldFromInstruction_4(Insn, 4, 1); if (size == 0x3) { if (align == 0) return MCDisassembler_Fail; align = 16; } else { if (size == 2) { align *= 8; } else { size = 1 << size; align *= 4 * size; } } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3*inc) % 32, Address, Decoder))) return MCDisassembler_Fail; if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm == 0xD) MCOperand_CreateReg0(Inst, 0); else if (Rm != 0xF) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } return S; } static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned imm, Q; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; imm = fieldFromInstruction_4(Insn, 0, 4); imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; Q = fieldFromInstruction_4(Insn, 6, 1); if (Q) { if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; } else { if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; } MCOperand_CreateImm0(Inst, imm); switch (MCInst_getOpcode(Inst)) { case ARM_VORRiv4i16: case ARM_VORRiv2i32: case ARM_VBICiv4i16: case ARM_VBICiv2i32: if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; case ARM_VORRiv8i16: case ARM_VORRiv4i32: case ARM_VBICiv8i16: case ARM_VBICiv4i32: if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; break; default: break; } return S; } static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rm, size; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; Rm = fieldFromInstruction_4(Insn, 0, 4); Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; size = fieldFromInstruction_4(Insn, 18, 2); if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, 8 << size); return S; } static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, 8 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, 16 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, 32 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, 64 - Val); return MCDisassembler_Success; } static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn, Rm, op; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; Rn = fieldFromInstruction_4(Insn, 16, 4); Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; Rm = fieldFromInstruction_4(Insn, 0, 4); Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; op = fieldFromInstruction_4(Insn, 6, 1); if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (op) { if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; // Writeback } switch (MCInst_getOpcode(Inst)) { case ARM_VTBL2: case ARM_VTBX2: if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned dst = fieldFromInstruction_2(Insn, 8, 3); unsigned imm = fieldFromInstruction_2(Insn, 0, 8); if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) return MCDisassembler_Fail; switch(MCInst_getOpcode(Inst)) { default: return MCDisassembler_Fail; case ARM_tADR: break; // tADR does not explicitly represent the PC as an operand. case ARM_tADDrSPi: MCOperand_CreateReg0(Inst, ARM_SP); break; } MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); return MCDisassembler_Success; } static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); return MCDisassembler_Success; } static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, Val << 1); return MCDisassembler_Success; } static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 0, 3); unsigned Rm = fieldFromInstruction_4(Val, 3, 3); if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 0, 3); unsigned imm = fieldFromInstruction_4(Val, 3, 5); if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { unsigned imm = Val << 2; MCOperand_CreateImm0(Inst, imm); //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); return MCDisassembler_Success; } static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateReg0(Inst, ARM_SP); MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 6, 4); unsigned Rm = fieldFromInstruction_4(Val, 2, 4); unsigned imm = fieldFromInstruction_4(Val, 0, 2); // Thumb stores cannot use PC as dest register. switch (MCInst_getOpcode(Inst)) { case ARM_t2STRHs: case ARM_t2STRBs: case ARM_t2STRs: if (Rn == 15) return MCDisassembler_Fail; default: break; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned addrmode; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); if (Rn == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRBs: MCInst_setOpcode(Inst, ARM_t2LDRBpci); break; case ARM_t2LDRHs: MCInst_setOpcode(Inst, ARM_t2LDRHpci); break; case ARM_t2LDRSHs: MCInst_setOpcode(Inst, ARM_t2LDRSHpci); break; case ARM_t2LDRSBs: MCInst_setOpcode(Inst, ARM_t2LDRSBpci); break; case ARM_t2LDRs: MCInst_setOpcode(Inst, ARM_t2LDRpci); break; case ARM_t2PLDs: MCInst_setOpcode(Inst, ARM_t2PLDpci); break; case ARM_t2PLIs: MCInst_setOpcode(Inst, ARM_t2PLIpci); break; default: return MCDisassembler_Fail; } return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); } if (Rt == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRSHs: return MCDisassembler_Fail; case ARM_t2LDRHs: MCInst_setOpcode(Inst, ARM_t2PLDWs); break; case ARM_t2LDRSBs: MCInst_setOpcode(Inst, ARM_t2PLIs); default: break; } } switch (MCInst_getOpcode(Inst)) { case ARM_t2PLDs: break; case ARM_t2PLIs: if (!hasV7Ops) return MCDisassembler_Fail; break; case ARM_t2PLDWs: if (!hasV7Ops || !hasMP) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; } addrmode = fieldFromInstruction_4(Insn, 4, 2); addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned U = fieldFromInstruction_4(Insn, 9, 1); unsigned imm = fieldFromInstruction_4(Insn, 0, 8); unsigned add = fieldFromInstruction_4(Insn, 9, 1); bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); imm |= (U << 8); imm |= (Rn << 9); if (Rn == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRi8: MCInst_setOpcode(Inst, ARM_t2LDRpci); break; case ARM_t2LDRBi8: MCInst_setOpcode(Inst, ARM_t2LDRBpci); break; case ARM_t2LDRSBi8: MCInst_setOpcode(Inst, ARM_t2LDRSBpci); break; case ARM_t2LDRHi8: MCInst_setOpcode(Inst, ARM_t2LDRHpci); break; case ARM_t2LDRSHi8: MCInst_setOpcode(Inst, ARM_t2LDRSHpci); break; case ARM_t2PLDi8: MCInst_setOpcode(Inst, ARM_t2PLDpci); break; case ARM_t2PLIi8: MCInst_setOpcode(Inst, ARM_t2PLIpci); break; default: return MCDisassembler_Fail; } return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); } if (Rt == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRSHi8: return MCDisassembler_Fail; case ARM_t2LDRHi8: if (!add) MCInst_setOpcode(Inst, ARM_t2PLDWi8); break; case ARM_t2LDRSBi8: MCInst_setOpcode(Inst, ARM_t2PLIi8); break; default: break; } } switch (MCInst_getOpcode(Inst)) { case ARM_t2PLDi8: break; case ARM_t2PLIi8: if (!hasV7Ops) return MCDisassembler_Fail; break; case ARM_t2PLDWi8: if (!hasV7Ops || !hasMP) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 12); bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP); bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); imm |= (Rn << 13); if (Rn == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRi12: MCInst_setOpcode(Inst, ARM_t2LDRpci); break; case ARM_t2LDRHi12: MCInst_setOpcode(Inst, ARM_t2LDRHpci); break; case ARM_t2LDRSHi12: MCInst_setOpcode(Inst, ARM_t2LDRSHpci); break; case ARM_t2LDRBi12: MCInst_setOpcode(Inst, ARM_t2LDRBpci); break; case ARM_t2LDRSBi12: MCInst_setOpcode(Inst, ARM_t2LDRSBpci); break; case ARM_t2PLDi12: MCInst_setOpcode(Inst, ARM_t2PLDpci); break; case ARM_t2PLIi12: MCInst_setOpcode(Inst, ARM_t2PLIpci); break; default: return MCDisassembler_Fail; } return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); } if (Rt == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRSHi12: return MCDisassembler_Fail; case ARM_t2LDRHi12: MCInst_setOpcode(Inst, ARM_t2PLDWi12); break; case ARM_t2LDRSBi12: MCInst_setOpcode(Inst, ARM_t2PLIi12); break; default: break; } } switch (MCInst_getOpcode(Inst)) { case ARM_t2PLDi12: break; case ARM_t2PLIi12: if (!hasV7Ops) return MCDisassembler_Fail; break; case ARM_t2PLDWi12: if (!hasV7Ops || !hasMP) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 8); imm |= (Rn << 9); if (Rn == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRT: MCInst_setOpcode(Inst, ARM_t2LDRpci); break; case ARM_t2LDRBT: MCInst_setOpcode(Inst, ARM_t2LDRBpci); break; case ARM_t2LDRHT: MCInst_setOpcode(Inst, ARM_t2LDRHpci); break; case ARM_t2LDRSBT: MCInst_setOpcode(Inst, ARM_t2LDRSBpci); break; case ARM_t2LDRSHT: MCInst_setOpcode(Inst, ARM_t2LDRSHpci); break; default: return MCDisassembler_Fail; } return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); } if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, uint64_t Address, const void* Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned U = fieldFromInstruction_4(Insn, 23, 1); int imm = fieldFromInstruction_4(Insn, 0, 12); bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops); if (Rt == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRBpci: case ARM_t2LDRHpci: MCInst_setOpcode(Inst, ARM_t2PLDpci); break; case ARM_t2LDRSBpci: MCInst_setOpcode(Inst, ARM_t2PLIpci); break; case ARM_t2LDRSHpci: return MCDisassembler_Fail; default: break; } } switch(MCInst_getOpcode(Inst)) { case ARM_t2PLDpci: break; case ARM_t2PLIpci: if (!hasV7Ops) return MCDisassembler_Fail; break; default: if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; } if (!U) { // Special case for #-0. if (imm == 0) imm = INT32_MIN; else imm = -imm; } MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val == 0) MCOperand_CreateImm0(Inst, INT32_MIN); else { int imm = Val & 0xFF; if (!(Val & 0x100)) imm *= -1; MCOperand_CreateImm0(Inst, imm * 4); } return MCDisassembler_Success; } static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 9, 4); unsigned imm = fieldFromInstruction_4(Val, 0, 9); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 8, 4); unsigned imm = fieldFromInstruction_4(Val, 0, 8); if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { int imm = Val & 0xFF; if (Val == 0) imm = INT32_MIN; else if (!(Val & 0x100)) imm *= -1; MCOperand_CreateImm0(Inst, imm); return MCDisassembler_Success; } static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 9, 4); unsigned imm = fieldFromInstruction_4(Val, 0, 9); // Thumb stores cannot use PC as dest register. switch (MCInst_getOpcode(Inst)) { case ARM_t2STRT: case ARM_t2STRBT: case ARM_t2STRHT: case ARM_t2STRi8: case ARM_t2STRHi8: case ARM_t2STRBi8: if (Rn == 15) return MCDisassembler_Fail; break; default: break; } // Some instructions always use an additive offset. switch (MCInst_getOpcode(Inst)) { case ARM_t2LDRT: case ARM_t2LDRBT: case ARM_t2LDRHT: case ARM_t2LDRSBT: case ARM_t2LDRSHT: case ARM_t2STRT: case ARM_t2STRBT: case ARM_t2STRHT: imm |= 0x100; break; default: break; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned load; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned addr = fieldFromInstruction_4(Insn, 0, 8); addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; addr |= Rn << 9; load = fieldFromInstruction_4(Insn, 20, 1); if (Rn == 15) { switch (MCInst_getOpcode(Inst)) { case ARM_t2LDR_PRE: case ARM_t2LDR_POST: MCInst_setOpcode(Inst, ARM_t2LDRpci); break; case ARM_t2LDRB_PRE: case ARM_t2LDRB_POST: MCInst_setOpcode(Inst, ARM_t2LDRBpci); break; case ARM_t2LDRH_PRE: case ARM_t2LDRH_POST: MCInst_setOpcode(Inst, ARM_t2LDRHpci); break; case ARM_t2LDRSB_PRE: case ARM_t2LDRSB_POST: if (Rt == 15) MCInst_setOpcode(Inst, ARM_t2PLIpci); else MCInst_setOpcode(Inst, ARM_t2LDRSBpci); break; case ARM_t2LDRSH_PRE: case ARM_t2LDRSH_POST: MCInst_setOpcode(Inst, ARM_t2LDRSHpci); break; default: return MCDisassembler_Fail; } return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); } if (!load) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (load) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Val, 13, 4); unsigned imm = fieldFromInstruction_4(Val, 0, 12); // Thumb stores cannot use PC as dest register. switch (MCInst_getOpcode(Inst)) { case ARM_t2STRi12: case ARM_t2STRBi12: case ARM_t2STRHi12: if (Rn == 15) return MCDisassembler_Fail; default: break; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, imm); return S; } static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { unsigned imm = fieldFromInstruction_2(Insn, 0, 7); MCOperand_CreateReg0(Inst, ARM_SP); MCOperand_CreateReg0(Inst, ARM_SP); MCOperand_CreateImm0(Inst, imm); return MCDisassembler_Success; } static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, ARM_SP); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler_Fail; } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); MCOperand_CreateReg0(Inst, ARM_SP); MCOperand_CreateReg0(Inst, ARM_SP); if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } return S; } static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; unsigned flags = fieldFromInstruction_2(Insn, 0, 3); MCOperand_CreateImm0(Inst, imod); MCOperand_CreateImm0(Inst, flags); return MCDisassembler_Success; } static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned add = fieldFromInstruction_4(Insn, 4, 1); if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, add); return S; } static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { // Val is passed in as S:J1:J2:imm10H:imm10L:'0' // Note only one trailing zero not two. Also the J1 and J2 values are from // the encoded instruction. So here change to I1 and I2 values via: // I1 = NOT(J1 EOR S); // I2 = NOT(J2 EOR S); // and build the imm32 with two trailing zeros as documented: // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); unsigned S = (Val >> 23) & 1; unsigned J1 = (Val >> 22) & 1; unsigned J2 = (Val >> 21) & 1; unsigned I1 = !(J1 ^ S); unsigned I2 = !(J2 ^ S); unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); int imm32 = SignExtend32(tmp << 1, 25); MCOperand_CreateImm0(Inst, imm32); return MCDisassembler_Success; } static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val == 0xA || Val == 0xB) return MCDisassembler_Fail; if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && !(Val == 14 || Val == 15)) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); if (Rn == ARM_SP) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned brtarget; unsigned pred = fieldFromInstruction_4(Insn, 22, 4); if (pred == 0xE || pred == 0xF) { unsigned imm; unsigned opc = fieldFromInstruction_4(Insn, 4, 28); switch (opc) { default: return MCDisassembler_Fail; case 0xf3bf8f4: MCInst_setOpcode(Inst, ARM_t2DSB); break; case 0xf3bf8f5: MCInst_setOpcode(Inst, ARM_t2DMB); break; case 0xf3bf8f6: MCInst_setOpcode(Inst, ARM_t2ISB); break; } imm = fieldFromInstruction_4(Insn, 0, 4); return DecodeMemBarrierOption(Inst, imm, Address, Decoder); } brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } // Decode a shifted immediate operand. These basically consist // of an 8-bit value, and a 4-bit directive that specifies either // a splat operation or a rotation. static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); if (ctrl == 0) { unsigned byte = fieldFromInstruction_4(Val, 8, 2); unsigned imm = fieldFromInstruction_4(Val, 0, 8); switch (byte) { case 0: MCOperand_CreateImm0(Inst, imm); break; case 1: MCOperand_CreateImm0(Inst, (imm << 16) | imm); break; case 2: MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); break; case 3: MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); break; } } else { unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; unsigned rot = fieldFromInstruction_4(Val, 7, 5); unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31)); MCOperand_CreateImm0(Inst, imm); } return MCDisassembler_Success; } static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); return MCDisassembler_Success; } static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { // Val is passed in as S:J1:J2:imm10:imm11 // Note no trailing zero after imm11. Also the J1 and J2 values are from // the encoded instruction. So here change to I1 and I2 values via: // I1 = NOT(J1 EOR S); // I2 = NOT(J2 EOR S); // and build the imm32 with one trailing zero as documented: // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); unsigned S = (Val >> 23) & 1; unsigned J1 = (Val >> 22) & 1; unsigned J2 = (Val >> 21) & 1; unsigned I1 = !(J1 ^ S); unsigned I2 = !(J2 ^ S); unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); int imm32 = SignExtend32(tmp << 1, 25); MCOperand_CreateImm0(Inst, imm32); return MCDisassembler_Success; } static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val & ~0xf) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val & ~0xf) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; if (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass)) { unsigned ValLow = Val & 0xff; // Validate the SYSm value first. switch (ValLow) { case 0: // apsr case 1: // iapsr case 2: // eapsr case 3: // xpsr case 5: // ipsr case 6: // epsr case 7: // iepsr case 8: // msp case 9: // psp case 16: // primask case 20: // control break; case 17: // basepri case 18: // basepri_max case 19: // faultmask if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) // Values basepri, basepri_max and faultmask are only valid for v7m. return MCDisassembler_Fail; break; case 0x8a: // msplim_ns case 0x8b: // psplim_ns case 0x91: // basepri_ns case 0x93: // faultmask_ns if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps)) return MCDisassembler_Fail; // LLVM_FALLTHROUGH; case 10: // msplim case 11: // psplim case 0x88: // msp_ns case 0x89: // psp_ns case 0x90: // primask_ns case 0x94: // control_ns case 0x98: // sp_ns if (!ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt)) return MCDisassembler_Fail; break; default: return MCDisassembler_SoftFail; } if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) { unsigned Mask = fieldFromInstruction_4(Val, 10, 2); if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) { // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are // unpredictable. if (Mask != 2) S = MCDisassembler_SoftFail; } else { // The ARMv7-M architecture stores an additional 2-bit mask value in // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if // the NZCVQ bits should be moved by the instruction. Bit mask{0} // indicates the move for the GE{3:0} bits, the mask{0} bit can be set // only if the processor includes the DSP extension. if (Mask == 0 || (Mask != 2 && ValLow > 3) || (!ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && (Mask & 1))) S = MCDisassembler_SoftFail; } } } else { // A/R class if (Val == 0) return MCDisassembler_Fail; } MCOperand_CreateImm0(Inst, Val); return S; } static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { unsigned R = fieldFromInstruction_4(Val, 5, 1); unsigned SysM = fieldFromInstruction_4(Val, 0, 5); // The table of encodings for these banked registers comes from B9.2.3 of the // ARM ARM. There are patterns, but nothing regular enough to make this logic // neater. So by fiat, these values are UNPREDICTABLE: if (!lookupBankedRegByEncoding((R << 5) | SysM)) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); if (Rn == 0xF) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt + 1) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 12); imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; pred = fieldFromInstruction_4(Insn, 28, 4); if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred, Rm; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 12); imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; pred = fieldFromInstruction_4(Insn, 28, 4); Rm = fieldFromInstruction_4(Insn, 0, 4); if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; if (Rm == 0xF) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 12); imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; pred = fieldFromInstruction_4(Insn, 28, 4); if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned imm = fieldFromInstruction_4(Insn, 0, 12); imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; pred = fieldFromInstruction_4(Insn, 28, 4); if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: if (fieldFromInstruction_4(Insn, 4, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 5, 3); break; case 1: if (fieldFromInstruction_4(Insn, 5, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 4, 1)) align = 2; break; case 2: if (fieldFromInstruction_4(Insn, 6, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 7, 1); switch (fieldFromInstruction_4(Insn, 4, 2)) { case 0 : align = 0; break; case 3: align = 4; break; default: return MCDisassembler_Fail; } break; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: if (fieldFromInstruction_4(Insn, 4, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 5, 3); break; case 1: if (fieldFromInstruction_4(Insn, 5, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 4, 1)) align = 2; break; case 2: if (fieldFromInstruction_4(Insn, 6, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 7, 1); switch (fieldFromInstruction_4(Insn, 4, 2)) { case 0: align = 0; break; case 3: align = 4; break; default: return MCDisassembler_Fail; } break; } if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0, inc = 1; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: index = fieldFromInstruction_4(Insn, 5, 3); if (fieldFromInstruction_4(Insn, 4, 1)) align = 2; break; case 1: index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 4, 1)) align = 4; if (fieldFromInstruction_4(Insn, 5, 1)) inc = 2; break; case 2: if (fieldFromInstruction_4(Insn, 5, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 7, 1); if (fieldFromInstruction_4(Insn, 4, 1) != 0) align = 8; if (fieldFromInstruction_4(Insn, 6, 1)) inc = 2; break; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0, inc = 1; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: index = fieldFromInstruction_4(Insn, 5, 3); if (fieldFromInstruction_4(Insn, 4, 1)) align = 2; break; case 1: index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 4, 1)) align = 4; if (fieldFromInstruction_4(Insn, 5, 1)) inc = 2; break; case 2: if (fieldFromInstruction_4(Insn, 5, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 7, 1); if (fieldFromInstruction_4(Insn, 4, 1) != 0) align = 8; if (fieldFromInstruction_4(Insn, 6, 1)) inc = 2; break; } if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0, inc = 1; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: if (fieldFromInstruction_4(Insn, 4, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 5, 3); break; case 1: if (fieldFromInstruction_4(Insn, 4, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 5, 1)) inc = 2; break; case 2: if (fieldFromInstruction_4(Insn, 4, 2)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 7, 1); if (fieldFromInstruction_4(Insn, 6, 1)) inc = 2; break; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) return MCDisassembler_Fail; if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0, inc = 1; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: if (fieldFromInstruction_4(Insn, 4, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 5, 3); break; case 1: if (fieldFromInstruction_4(Insn, 4, 1)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 5, 1)) inc = 2; break; case 2: if (fieldFromInstruction_4(Insn, 4, 2)) return MCDisassembler_Fail; // UNDEFINED index = fieldFromInstruction_4(Insn, 7, 1); if (fieldFromInstruction_4(Insn, 6, 1)) inc = 2; break; } if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0, inc = 1; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: if (fieldFromInstruction_4(Insn, 4, 1)) align = 4; index = fieldFromInstruction_4(Insn, 5, 3); break; case 1: if (fieldFromInstruction_4(Insn, 4, 1)) align = 8; index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 5, 1)) inc = 2; break; case 2: switch (fieldFromInstruction_4(Insn, 4, 2)) { case 0: align = 0; break; case 3: return MCDisassembler_Fail; default: align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; } index = fieldFromInstruction_4(Insn, 7, 1); if (fieldFromInstruction_4(Insn, 6, 1)) inc = 2; break; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) return MCDisassembler_Fail; if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned size, align = 0, index = 0, inc = 1; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; size = fieldFromInstruction_4(Insn, 10, 2); switch (size) { default: return MCDisassembler_Fail; case 0: if (fieldFromInstruction_4(Insn, 4, 1)) align = 4; index = fieldFromInstruction_4(Insn, 5, 3); break; case 1: if (fieldFromInstruction_4(Insn, 4, 1)) align = 8; index = fieldFromInstruction_4(Insn, 6, 2); if (fieldFromInstruction_4(Insn, 5, 1)) inc = 2; break; case 2: switch (fieldFromInstruction_4(Insn, 4, 2)) { case 0: align = 0; break; case 3: return MCDisassembler_Fail; default: align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; } index = fieldFromInstruction_4(Insn, 7, 1); if (fieldFromInstruction_4(Insn, 6, 1)) inc = 2; break; } if (Rm != 0xF) { // Writeback if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, align); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; } else MCOperand_CreateReg0(Inst, 0); } if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, index); return S; } static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned pred = fieldFromInstruction_4(Insn, 4, 4); unsigned mask = fieldFromInstruction_4(Insn, 0, 4); if (pred == 0xF) { pred = 0xE; S = MCDisassembler_SoftFail; } if (mask == 0x0) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, pred); MCOperand_CreateImm0(Inst, mask); return S; } static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned addr = fieldFromInstruction_4(Insn, 0, 8); unsigned W = fieldFromInstruction_4(Insn, 21, 1); unsigned U = fieldFromInstruction_4(Insn, 23, 1); unsigned P = fieldFromInstruction_4(Insn, 24, 1); bool writeback = (W == 1) | (P == 0); addr |= (U << 8) | (Rn << 9); if (writeback && (Rn == Rt || Rn == Rt2)) Check(&S, MCDisassembler_SoftFail); if (Rt == Rt2) Check(&S, MCDisassembler_SoftFail); // Rt if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; // Rt2 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler_Fail; // Writeback operand if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; // addr if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned addr = fieldFromInstruction_4(Insn, 0, 8); unsigned W = fieldFromInstruction_4(Insn, 21, 1); unsigned U = fieldFromInstruction_4(Insn, 23, 1); unsigned P = fieldFromInstruction_4(Insn, 24, 1); bool writeback = (W == 1) | (P == 0); addr |= (U << 8) | (Rn << 9); if (writeback && (Rn == Rt || Rn == Rt2)) Check(&S, MCDisassembler_SoftFail); // Writeback operand if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; // Rt if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; // Rt2 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler_Fail; // addr if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, uint64_t Address, const void *Decoder) { unsigned Val; unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); if (sign1 != sign2) return MCDisassembler_Fail; Val = fieldFromInstruction_4(Insn, 0, 8); Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; Val |= sign1 << 12; MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); return MCDisassembler_Success; } static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, uint64_t Address, const void *Decoder) { // Shift of "asr #32" is not allowed in Thumb2 mode. if (Val == 0x20) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Val); return MCDisassembler_Success; } static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned pred = fieldFromInstruction_4(Insn, 28, 4); if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); S = MCDisassembler_Success; if (Rt == Rn || Rn == Rt2) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); unsigned Vm, imm, cmode, op; unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); imm = fieldFromInstruction_4(Insn, 16, 6); cmode = fieldFromInstruction_4(Insn, 8, 4); op = fieldFromInstruction_4(Insn, 5, 1); // If the top 3 bits of imm are clear, this is a VMOV (immediate) if (!(imm & 0x38)) { if (cmode == 0xF) { if (op == 1) return MCDisassembler_Fail; MCInst_setOpcode(Inst, ARM_VMOVv2f32); } if (hasFullFP16) { if (cmode == 0xE) { if (op == 1) { MCInst_setOpcode(Inst, ARM_VMOVv1i64); } else { MCInst_setOpcode(Inst, ARM_VMOVv8i8); } } if (cmode == 0xD) { if (op == 1) { MCInst_setOpcode(Inst, ARM_VMVNv2i32); } else { MCInst_setOpcode(Inst, ARM_VMOVv2i32); } } if (cmode == 0xC) { if (op == 1) { MCInst_setOpcode(Inst, ARM_VMVNv2i32); } else { MCInst_setOpcode(Inst, ARM_VMOVv2i32); } } } return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); } if (!(imm & 0x20)) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, 64 - imm); return S; } static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16); unsigned Vm, imm, cmode, op; unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); imm = fieldFromInstruction_4(Insn, 16, 6); cmode = fieldFromInstruction_4(Insn, 8, 4); op = fieldFromInstruction_4(Insn, 5, 1); // VMOVv4f32 is ambiguous with these decodings. if (!(imm & 0x38) && cmode == 0xF) { if (op == 1) return MCDisassembler_Fail; MCInst_setOpcode(Inst, ARM_VMOVv4f32); return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); } // If the top 3 bits of imm are clear, this is a VMOV (immediate) if (!(imm & 0x38)) { if (cmode == 0xF) { if (op == 1) return MCDisassembler_Fail; MCInst_setOpcode(Inst, ARM_VMOVv4f32); } if (hasFullFP16) { if (cmode == 0xE) { if (op == 1) { MCInst_setOpcode(Inst, ARM_VMOVv2i64); } else { MCInst_setOpcode(Inst, ARM_VMOVv16i8); } } if (cmode == 0xD) { if (op == 1) { MCInst_setOpcode(Inst, ARM_VMVNv4i32); } else { MCInst_setOpcode(Inst, ARM_VMOVv4i32); } } if (cmode == 0xC) { if (op == 1) { MCInst_setOpcode(Inst, ARM_VMVNv4i32); } else { MCInst_setOpcode(Inst, ARM_VMOVv4i32); } } } return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); } if (!(imm & 0x20)) return MCDisassembler_Fail; if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, 64 - imm); return S; } static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0); unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0); unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0); Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4); Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); if (q) { if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeQPRRegisterClass(Inst, Vn, Address, Decoder))) return MCDisassembler_Fail; } else { if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeDPRRegisterClass(Inst, Vn, Address, Decoder))) return MCDisassembler_Fail; } if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler_Fail; // The lane index does not have any bits in the encoding, because it can only // be 0. MCOperand_CreateImm0(Inst, 0); MCOperand_CreateImm0(Inst, rotate); return S; } static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; unsigned Cond; unsigned Rn = fieldFromInstruction_4(Val, 16, 4); unsigned Rt = fieldFromInstruction_4(Val, 12, 4); unsigned Rm = fieldFromInstruction_4(Val, 0, 4); Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); Cond = fieldFromInstruction_4(Val, 28, 4); if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) S = MCDisassembler_SoftFail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) return MCDisassembler_Fail; return S; } static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus result = MCDisassembler_Success; unsigned CRm = fieldFromInstruction_4(Val, 0, 4); unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); unsigned cop = fieldFromInstruction_4(Val, 8, 4); unsigned Rt = fieldFromInstruction_4(Val, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); if ((cop & ~0x1) == 0xa) return MCDisassembler_Fail; if (Rt == Rt2) result = MCDisassembler_SoftFail; // We have to check if the instruction is MRRC2 // or MCRR2 when constructing the operands for // Inst. Reason is because MRRC2 stores to two // registers so it's tablegen desc has has two // outputs whereas MCRR doesn't store to any // registers so all of it's operands are listed // as inputs, therefore the operand order for // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] if (MCInst_getOpcode(Inst) == ARM_MRRC2) { if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler_Fail; } MCOperand_CreateImm0(Inst, cop); MCOperand_CreateImm0(Inst, opc1); if (MCInst_getOpcode(Inst) == ARM_MCRR2) { if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler_Fail; if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler_Fail; } MCOperand_CreateImm0(Inst, CRm); return result; } static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus result = MCDisassembler_Success; bool HasV8Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops); unsigned Rt = fieldFromInstruction_4(Val, 12, 4); if ((Inst->csh->mode & CS_MODE_THUMB) && !HasV8Ops) { if (Rt == 13 || Rt == 15) result = MCDisassembler_SoftFail; Check(&result, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); } else Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); if (Inst->csh->mode & CS_MODE_THUMB) { MCOperand_CreateImm0(Inst, ARMCC_AL); MCOperand_CreateReg0(Inst, 0); } else { unsigned pred = fieldFromInstruction_4(Val, 28, 4); if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler_Fail; } return result; } #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMDisassembler.h000064400000000000000000000011330072674642500206630ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_ARMDISASSEMBLER_H #define CS_ARMDISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" void ARM_init(MCRegisterInfo *MRI); bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); bool ARM_getFeatureBits(unsigned int mode, unsigned int feature); #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMGenAsmWriter.inc000064400000000000000000010131210072674642500211400ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0, /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0, /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0, /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0, /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0, /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0, /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0, /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0, /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0, /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0, /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, /* 237 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '3', '2', 9, 0, /* 248 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0, /* 260 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '3', '2', 9, 0, /* 271 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0, /* 283 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0, /* 295 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0, /* 307 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0, /* 319 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0, /* 331 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0, /* 343 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0, /* 355 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0, /* 367 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0, /* 379 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0, /* 391 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0, /* 403 */ 'l', 'd', 'c', '2', 9, 0, /* 409 */ 'm', 'r', 'c', '2', 9, 0, /* 415 */ 'm', 'r', 'r', 'c', '2', 9, 0, /* 422 */ 's', 't', 'c', '2', 9, 0, /* 428 */ 'c', 'd', 'p', '2', 9, 0, /* 434 */ 'm', 'c', 'r', '2', 9, 0, /* 440 */ 'm', 'c', 'r', 'r', '2', 9, 0, /* 447 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, /* 462 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, /* 477 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, /* 492 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, /* 507 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, /* 522 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, /* 537 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, /* 552 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, /* 567 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0, /* 579 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0, /* 591 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0, /* 603 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0, /* 615 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0, /* 627 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0, /* 639 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0, /* 651 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0, /* 663 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0, /* 675 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0, /* 687 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0, /* 698 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, /* 713 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, /* 728 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, /* 743 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0, /* 758 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, /* 773 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, /* 788 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, /* 803 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0, /* 818 */ 'v', 'c', 'v', 't', 'a', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, /* 833 */ 'v', 'c', 'v', 't', 'm', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, /* 848 */ 'v', 'c', 'v', 't', 'n', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, /* 863 */ 'v', 'c', 'v', 't', 'p', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0, /* 878 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, /* 893 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, /* 908 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, /* 923 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0, /* 938 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '1', '6', 9, 0, /* 949 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '1', '6', 9, 0, /* 961 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '1', '6', 9, 0, /* 972 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '1', '6', 9, 0, /* 984 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '1', '6', 9, 0, /* 996 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '1', '6', 9, 0, /* 1008 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '1', '6', 9, 0, /* 1020 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '1', '6', 9, 0, /* 1032 */ 'v', 'r', 'i', 'n', 't', 'p', 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't', 'c', 'l', 0, /* 2814 */ 'v', 'a', 'b', 'd', 'l', 0, /* 2820 */ 'v', 'p', 'a', 'd', 'd', 'l', 0, /* 2827 */ 'v', 'a', 'd', 'd', 'l', 0, /* 2833 */ 's', 'e', 'l', 0, /* 2837 */ 'v', 'q', 's', 'h', 'l', 0, /* 2843 */ 'v', 'q', 'r', 's', 'h', 'l', 0, /* 2850 */ 'v', 'r', 's', 'h', 'l', 0, /* 2856 */ 'v', 's', 'h', 'l', 0, /* 2861 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 2875 */ 'v', 's', 'h', 'l', 'l', 0, /* 2881 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0, /* 2889 */ 's', 'm', 'u', 'l', 'l', 0, /* 2895 */ 'u', 'm', 'u', 'l', 'l', 0, /* 2901 */ 'v', 'm', 'u', 'l', 'l', 0, /* 2907 */ 'v', 'b', 's', 'l', 0, /* 2912 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0, /* 2920 */ 'v', 'm', 'l', 's', 'l', 0, /* 2926 */ 's', 't', 'l', 0, /* 2930 */ 's', 'm', 'm', 'u', 'l', 0, /* 2936 */ 'v', 'n', 'm', 'u', 'l', 0, /* 2942 */ 'v', 'm', 'u', 'l', 0, /* 2947 */ 'v', 'm', 'o', 'v', 'l', 0, /* 2953 */ 'v', 'l', 'l', 'd', 'm', 0, /* 2959 */ 'v', 'l', 's', 't', 'm', 0, /* 2965 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0, /* 2973 */ 'v', 's', 'u', 'b', 'h', 'n', 0, /* 2980 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0, /* 2988 */ 'v', 'a', 'd', 'd', 'h', 'n', 0, /* 2995 */ 'v', 'p', 'm', 'i', 'n', 0, /* 3001 */ 'v', 'm', 'i', 'n', 0, /* 3006 */ 'c', 'm', 'n', 0, /* 3010 */ 'v', 'q', 's', 'h', 'r', 'n', 0, /* 3017 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0, /* 3025 */ 'v', 'r', 's', 'h', 'r', 'n', 0, /* 3032 */ 'v', 's', 'h', 'r', 'n', 0, /* 3038 */ 'v', 'o', 'r', 'n', 0, /* 3043 */ 'v', 't', 'r', 'n', 0, /* 3048 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0, /* 3056 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0, /* 3065 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0, /* 3073 */ 'v', 'm', 'v', 'n', 0, /* 3078 */ 'v', 'q', 'm', 'o', 'v', 'n', 0, /* 3085 */ 'v', 'm', 'o', 'v', 'n', 0, /* 3091 */ 't', 'r', 'a', 'p', 0, /* 3096 */ 'c', 'd', 'p', 0, /* 3100 */ 'v', 'z', 'i', 'p', 0, /* 3105 */ 'v', 'c', 'm', 'p', 0, /* 3110 */ 'p', 'o', 'p', 0, /* 3114 */ 'v', 'd', 'u', 'p', 0, /* 3119 */ 'v', 's', 'w', 'p', 0, /* 3124 */ 'v', 'u', 'z', 'p', 0, /* 3129 */ 'v', 'c', 'e', 'q', 0, /* 3134 */ 't', 'e', 'q', 0, /* 3138 */ 's', 'm', 'm', 'l', 'a', 'r', 0, /* 3145 */ 'm', 'c', 'r', 0, /* 3149 */ 'a', 'd', 'r', 0, /* 3153 */ 'v', 'l', 'd', 'r', 0, /* 3158 */ 'v', 'r', 's', 'h', 'r', 0, /* 3164 */ 'v', 's', 'h', 'r', 0, /* 3169 */ 's', 'm', 'm', 'u', 'l', 'r', 0, /* 3176 */ 'v', 'e', 'o', 'r', 0, /* 3181 */ 'r', 'o', 'r', 0, /* 3185 */ 'm', 'c', 'r', 'r', 0, /* 3190 */ 'v', 'o', 'r', 'r', 0, /* 3195 */ 'a', 's', 'r', 0, /* 3199 */ 's', 'm', 'm', 'l', 's', 'r', 0, /* 3206 */ 'v', 'm', 's', 'r', 0, /* 3211 */ 'v', 'r', 'i', 'n', 't', 'r', 0, /* 3218 */ 'v', 's', 't', 'r', 0, /* 3223 */ 'v', 'c', 'v', 't', 'r', 0, /* 3229 */ 'v', 'q', 'a', 'b', 's', 0, /* 3235 */ 'v', 'a', 'b', 's', 0, /* 3240 */ 's', 'u', 'b', 's', 0, /* 3245 */ 'v', 'c', 'l', 's', 0, /* 3250 */ 's', 'm', 'm', 'l', 's', 0, /* 3256 */ 'v', 'n', 'm', 'l', 's', 0, /* 3262 */ 'v', 'm', 'l', 's', 0, /* 3267 */ 'v', 'f', 'm', 's', 0, /* 3272 */ 'v', 'f', 'n', 'm', 's', 0, /* 3278 */ 'b', 'x', 'n', 's', 0, /* 3283 */ 'b', 'l', 'x', 'n', 's', 0, /* 3289 */ 'v', 'r', 'e', 'c', 'p', 's', 0, /* 3296 */ 'v', 'm', 'r', 's', 0, /* 3301 */ 'a', 's', 'r', 's', 0, /* 3306 */ 'l', 's', 'r', 's', 0, /* 3311 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0, /* 3319 */ 'm', 'o', 'v', 's', 0, /* 3324 */ 's', 's', 'a', 't', 0, /* 3329 */ 'u', 's', 'a', 't', 0, /* 3334 */ 't', 't', 'a', 't', 0, /* 3339 */ 's', 'm', 'l', 'a', 'b', 't', 0, /* 3346 */ 'p', 'k', 'h', 'b', 't', 0, /* 3352 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0, /* 3360 */ 's', 'm', 'u', 'l', 'b', 't', 0, /* 3367 */ 'l', 'd', 'r', 'b', 't', 0, /* 3373 */ 's', 't', 'r', 'b', 't', 0, /* 3379 */ 'l', 'd', 'r', 's', 'b', 't', 0, /* 3386 */ 'e', 'r', 'e', 't', 0, /* 3391 */ 'v', 'a', 'c', 'g', 't', 0, /* 3397 */ 'v', 'c', 'g', 't', 0, /* 3402 */ 'l', 'd', 'r', 'h', 't', 0, /* 3408 */ 's', 't', 'r', 'h', 't', 0, /* 3414 */ 'l', 'd', 'r', 's', 'h', 't', 0, /* 3421 */ 'r', 'b', 'i', 't', 0, /* 3426 */ 'v', 'b', 'i', 't', 0, /* 3431 */ 'v', 'c', 'l', 't', 0, /* 3436 */ 'v', 'c', 'n', 't', 0, /* 3441 */ 'h', 'i', 'n', 't', 0, /* 3446 */ 'l', 'd', 'r', 't', 0, /* 3451 */ 'v', 's', 'q', 'r', 't', 0, /* 3457 */ 's', 't', 'r', 't', 0, /* 3462 */ 'v', 't', 's', 't', 0, /* 3467 */ 's', 'm', 'l', 'a', 't', 't', 0, /* 3474 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0, /* 3482 */ 's', 'm', 'u', 'l', 't', 't', 0, /* 3489 */ 't', 't', 't', 0, /* 3493 */ 'v', 'c', 'v', 't', 't', 0, /* 3499 */ 'v', 'j', 'c', 'v', 't', 0, /* 3505 */ 'v', 'c', 'v', 't', 0, /* 3510 */ 'm', 'o', 'v', 't', 0, /* 3515 */ 's', 'm', 'l', 'a', 'w', 't', 0, /* 3522 */ 's', 'm', 'u', 'l', 'w', 't', 0, /* 3529 */ 'v', 'e', 'x', 't', 0, /* 3534 */ 'v', 'q', 's', 'h', 'l', 'u', 0, /* 3541 */ 'r', 'e', 'v', 0, /* 3545 */ 's', 'd', 'i', 'v', 0, /* 3550 */ 'u', 'd', 'i', 'v', 0, /* 3555 */ 'v', 'd', 'i', 'v', 0, /* 3560 */ 'v', 'm', 'o', 'v', 0, /* 3565 */ 'v', 's', 'u', 'b', 'w', 0, /* 3571 */ 'v', 'a', 'd', 'd', 'w', 0, /* 3577 */ 'p', 'l', 'd', 'w', 0, /* 3582 */ 'm', 'o', 'v', 'w', 0, /* 3587 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0, /* 3595 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0, /* 3603 */ 'v', 'p', 'm', 'a', 'x', 0, /* 3609 */ 'v', 'm', 'a', 'x', 0, /* 3614 */ 's', 'h', 's', 'a', 'x', 0, /* 3620 */ 'u', 'h', 's', 'a', 'x', 0, /* 3626 */ 'u', 'q', 's', 'a', 'x', 0, /* 3632 */ 's', 's', 'a', 'x', 0, /* 3637 */ 'u', 's', 'a', 'x', 0, /* 3642 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0, /* 3650 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0, /* 3658 */ 'v', 't', 'b', 'x', 0, /* 3663 */ 's', 'm', 'l', 'a', 'd', 'x', 0, /* 3670 */ 's', 'm', 'u', 'a', 'd', 'x', 0, /* 3677 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0, /* 3685 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0, /* 3693 */ 's', 'm', 'l', 's', 'd', 'x', 0, /* 3700 */ 's', 'm', 'u', 's', 'd', 'x', 0, /* 3707 */ 'l', 'd', 'a', 'e', 'x', 0, /* 3713 */ 's', 't', 'l', 'e', 'x', 0, /* 3719 */ 'l', 'd', 'r', 'e', 'x', 0, /* 3725 */ 'c', 'l', 'r', 'e', 'x', 0, /* 3731 */ 's', 't', 'r', 'e', 'x', 0, /* 3737 */ 's', 'b', 'f', 'x', 0, /* 3742 */ 'u', 'b', 'f', 'x', 0, /* 3747 */ 'b', 'l', 'x', 0, /* 3751 */ 'r', 'r', 'x', 0, /* 3755 */ 's', 'h', 'a', 's', 'x', 0, /* 3761 */ 'u', 'h', 'a', 's', 'x', 0, /* 3767 */ 'u', 'q', 'a', 's', 'x', 0, /* 3773 */ 's', 'a', 's', 'x', 0, /* 3778 */ 'u', 'a', 's', 'x', 0, /* 3783 */ 'v', 'r', 'i', 'n', 't', 'x', 0, /* 3790 */ 'v', 'c', 'l', 'z', 0, /* 3795 */ 'v', 'r', 'i', 'n', 't', 'z', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 1981U, // DBG_VALUE 1991U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 1974U, // BUNDLE 2020U, // LIFETIME_START 1961U, // LIFETIME_END 0U, // STACKMAP 2862U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 1568U, // PATCHABLE_FUNCTION_ENTER 1488U, // PATCHABLE_RET 1614U, // PATCHABLE_FUNCTION_EXIT 1591U, // PATCHABLE_TAIL_CALL 1543U, // PATCHABLE_EVENT_CALL 1519U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // ABS 0U, // ADDSri 0U, // ADDSrr 0U, // ADDSrsi 0U, // ADDSrsr 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 7292U, // ASRi 7292U, // ASRr 0U, // B 0U, // BCCZi64 0U, // BCCi64 0U, // BMOVPCB_CALL 0U, // BMOVPCRX_CALL 0U, // BR_JTadd 0U, // BR_JTm_i12 0U, // BR_JTm_rs 0U, // BR_JTr 0U, // BX_CALL 0U, // CMP_SWAP_16 0U, // CMP_SWAP_32 0U, // CMP_SWAP_64 0U, // CMP_SWAP_8 0U, // CONSTPOOL_ENTRY 0U, // COPY_STRUCT_BYVAL_I32 2001U, // CompilerBarrier 16788832U, // ITasm 0U, // Int_eh_sjlj_dispatchsetup 0U, // Int_eh_sjlj_longjmp 0U, // Int_eh_sjlj_setjmp 0U, // Int_eh_sjlj_setjmp_nofp 0U, // Int_eh_sjlj_setup_dispatch 0U, // JUMPTABLE_ADDRS 0U, // JUMPTABLE_INSTS 0U, // JUMPTABLE_TBB 0U, // JUMPTABLE_TBH 0U, // LDMIA_RET 15656U, // LDRBT_POST 15443U, // LDRConstPool 0U, // LDRLIT_ga_abs 0U, // LDRLIT_ga_pcrel 0U, // LDRLIT_ga_pcrel_ldr 15735U, // LDRT_POST 0U, // LEApcrel 0U, // LEApcrelJT 7013U, // LSLi 7013U, // LSLr 7299U, // LSRi 7299U, // LSRr 0U, // MEMCPY 0U, // MLAv5 0U, // MOVCCi 0U, // MOVCCi16 0U, // MOVCCi32imm 0U, // MOVCCr 0U, // MOVCCsi 0U, // MOVCCsr 0U, // MOVPCRX 0U, // MOVTi16_ga_pcrel 0U, // MOV_ga_pcrel 0U, // MOV_ga_pcrel_ldr 0U, // MOVi16_ga_pcrel 0U, // MOVi32imm 0U, // MOVsra_flag 0U, // MOVsrl_flag 0U, // MULv5 0U, // MVNCCi 0U, // PICADD 0U, // PICLDR 0U, // PICLDRB 0U, // PICLDRH 0U, // PICLDRSB 0U, // PICLDRSH 0U, // PICSTR 0U, // PICSTRB 0U, // PICSTRH 7278U, // RORi 7278U, // RORr 0U, // RRX 20136U, // RRXi 0U, // RSBSri 0U, // RSBSrsi 0U, // RSBSrsr 0U, // SMLALv5 0U, // SMULLv5 0U, // SPACE 15662U, // STRBT_POST 0U, // STRBi_preidx 0U, // STRBr_preidx 0U, // STRH_preidx 15746U, // STRT_POST 0U, // STRi_preidx 0U, // STRr_preidx 0U, // SUBS_PC_LR 0U, // SUBSri 0U, // SUBSrr 0U, // SUBSrsi 0U, // SUBSrsr 0U, // TAILJMPd 0U, // TAILJMPr 0U, // TAILJMPr4 0U, // TCRETURNdi 0U, // TCRETURNri 0U, // TPsoft 0U, // UMLALv5 0U, // UMULLv5 153198U, // VLD1LNdAsm_16 284270U, // VLD1LNdAsm_32 415342U, // VLD1LNdAsm_8 153198U, // VLD1LNdWB_fixed_Asm_16 284270U, // VLD1LNdWB_fixed_Asm_32 415342U, // VLD1LNdWB_fixed_Asm_8 157294U, // VLD1LNdWB_register_Asm_16 288366U, // VLD1LNdWB_register_Asm_32 419438U, // VLD1LNdWB_register_Asm_8 153242U, // VLD2LNdAsm_16 284314U, // VLD2LNdAsm_32 415386U, // VLD2LNdAsm_8 153242U, // VLD2LNdWB_fixed_Asm_16 284314U, // VLD2LNdWB_fixed_Asm_32 415386U, // VLD2LNdWB_fixed_Asm_8 157338U, // VLD2LNdWB_register_Asm_16 288410U, // VLD2LNdWB_register_Asm_32 419482U, // VLD2LNdWB_register_Asm_8 153242U, // VLD2LNqAsm_16 284314U, // VLD2LNqAsm_32 153242U, // VLD2LNqWB_fixed_Asm_16 284314U, // VLD2LNqWB_fixed_Asm_32 157338U, // VLD2LNqWB_register_Asm_16 288410U, // VLD2LNqWB_register_Asm_32 1107457722U, // VLD3DUPdAsm_16 1107588794U, // VLD3DUPdAsm_32 1107719866U, // VLD3DUPdAsm_8 2181199546U, // VLD3DUPdWB_fixed_Asm_16 2181330618U, // VLD3DUPdWB_fixed_Asm_32 2181461690U, // VLD3DUPdWB_fixed_Asm_8 33707706U, // VLD3DUPdWB_register_Asm_16 33838778U, // VLD3DUPdWB_register_Asm_32 33969850U, // VLD3DUPdWB_register_Asm_8 1124234938U, // VLD3DUPqAsm_16 1124366010U, // VLD3DUPqAsm_32 1124497082U, // VLD3DUPqAsm_8 2197976762U, // VLD3DUPqWB_fixed_Asm_16 2198107834U, // VLD3DUPqWB_fixed_Asm_32 2198238906U, // VLD3DUPqWB_fixed_Asm_8 50484922U, // VLD3DUPqWB_register_Asm_16 50615994U, // VLD3DUPqWB_register_Asm_32 50747066U, // VLD3DUPqWB_register_Asm_8 153274U, // VLD3LNdAsm_16 284346U, // VLD3LNdAsm_32 415418U, // VLD3LNdAsm_8 153274U, // VLD3LNdWB_fixed_Asm_16 284346U, // VLD3LNdWB_fixed_Asm_32 415418U, // VLD3LNdWB_fixed_Asm_8 157370U, // VLD3LNdWB_register_Asm_16 288442U, // VLD3LNdWB_register_Asm_32 419514U, // VLD3LNdWB_register_Asm_8 153274U, // VLD3LNqAsm_16 284346U, // VLD3LNqAsm_32 153274U, // VLD3LNqWB_fixed_Asm_16 284346U, // VLD3LNqWB_fixed_Asm_32 157370U, // VLD3LNqWB_register_Asm_16 288442U, // VLD3LNqWB_register_Asm_32 3288495802U, // VLD3dAsm_16 3288626874U, // VLD3dAsm_32 3288757946U, // VLD3dAsm_8 3288495802U, // VLD3dWB_fixed_Asm_16 3288626874U, // VLD3dWB_fixed_Asm_32 3288757946U, // VLD3dWB_fixed_Asm_8 3288487610U, // VLD3dWB_register_Asm_16 3288618682U, // VLD3dWB_register_Asm_32 3288749754U, // VLD3dWB_register_Asm_8 1157789370U, // VLD3qAsm_16 1157920442U, // VLD3qAsm_32 1158051514U, // VLD3qAsm_8 2231531194U, // VLD3qWB_fixed_Asm_16 2231662266U, // VLD3qWB_fixed_Asm_32 2231793338U, // VLD3qWB_fixed_Asm_8 84039354U, // VLD3qWB_register_Asm_16 84170426U, // VLD3qWB_register_Asm_32 84301498U, // VLD3qWB_register_Asm_8 1174566609U, // VLD4DUPdAsm_16 1174697681U, // VLD4DUPdAsm_32 1174828753U, // VLD4DUPdAsm_8 2248308433U, // VLD4DUPdWB_fixed_Asm_16 2248439505U, // VLD4DUPdWB_fixed_Asm_32 2248570577U, // VLD4DUPdWB_fixed_Asm_8 100816593U, // VLD4DUPdWB_register_Asm_16 100947665U, // VLD4DUPdWB_register_Asm_32 101078737U, // VLD4DUPdWB_register_Asm_8 1191343825U, // VLD4DUPqAsm_16 1191474897U, // VLD4DUPqAsm_32 1191605969U, // VLD4DUPqAsm_8 2265085649U, // VLD4DUPqWB_fixed_Asm_16 2265216721U, // VLD4DUPqWB_fixed_Asm_32 2265347793U, // VLD4DUPqWB_fixed_Asm_8 117593809U, // VLD4DUPqWB_register_Asm_16 117724881U, // VLD4DUPqWB_register_Asm_32 117855953U, // VLD4DUPqWB_register_Asm_8 153297U, // VLD4LNdAsm_16 284369U, // VLD4LNdAsm_32 415441U, // VLD4LNdAsm_8 153297U, // VLD4LNdWB_fixed_Asm_16 284369U, // VLD4LNdWB_fixed_Asm_32 415441U, // VLD4LNdWB_fixed_Asm_8 157393U, // VLD4LNdWB_register_Asm_16 288465U, // VLD4LNdWB_register_Asm_32 419537U, // VLD4LNdWB_register_Asm_8 153297U, // VLD4LNqAsm_16 284369U, // VLD4LNqAsm_32 153297U, // VLD4LNqWB_fixed_Asm_16 284369U, // VLD4LNqWB_fixed_Asm_32 157393U, // VLD4LNqWB_register_Asm_16 288465U, // VLD4LNqWB_register_Asm_32 3355604689U, // VLD4dAsm_16 3355735761U, // VLD4dAsm_32 3355866833U, // VLD4dAsm_8 3355604689U, // VLD4dWB_fixed_Asm_16 3355735761U, // VLD4dWB_fixed_Asm_32 3355866833U, // VLD4dWB_fixed_Asm_8 3355596497U, // VLD4dWB_register_Asm_16 3355727569U, // VLD4dWB_register_Asm_32 3355858641U, // VLD4dWB_register_Asm_8 1224898257U, // VLD4qAsm_16 1225029329U, // VLD4qAsm_32 1225160401U, // VLD4qAsm_8 2298640081U, // VLD4qWB_fixed_Asm_16 2298771153U, // VLD4qWB_fixed_Asm_32 2298902225U, // VLD4qWB_fixed_Asm_8 151148241U, // VLD4qWB_register_Asm_16 151279313U, // VLD4qWB_register_Asm_32 151410385U, // VLD4qWB_register_Asm_8 0U, // VMOVD0 0U, // VMOVDcc 0U, // VMOVQ0 0U, // VMOVScc 153209U, // VST1LNdAsm_16 284281U, // VST1LNdAsm_32 415353U, // VST1LNdAsm_8 153209U, // VST1LNdWB_fixed_Asm_16 284281U, // VST1LNdWB_fixed_Asm_32 415353U, // VST1LNdWB_fixed_Asm_8 157305U, // VST1LNdWB_register_Asm_16 288377U, // VST1LNdWB_register_Asm_32 419449U, // VST1LNdWB_register_Asm_8 153269U, // VST2LNdAsm_16 284341U, // VST2LNdAsm_32 415413U, // VST2LNdAsm_8 153269U, // VST2LNdWB_fixed_Asm_16 284341U, // VST2LNdWB_fixed_Asm_32 415413U, // VST2LNdWB_fixed_Asm_8 157365U, // VST2LNdWB_register_Asm_16 288437U, // VST2LNdWB_register_Asm_32 419509U, // VST2LNdWB_register_Asm_8 153269U, // VST2LNqAsm_16 284341U, // VST2LNqAsm_32 153269U, // VST2LNqWB_fixed_Asm_16 284341U, // VST2LNqWB_fixed_Asm_32 157365U, // VST2LNqWB_register_Asm_16 288437U, // VST2LNqWB_register_Asm_32 153285U, // VST3LNdAsm_16 284357U, // VST3LNdAsm_32 415429U, // VST3LNdAsm_8 153285U, // VST3LNdWB_fixed_Asm_16 284357U, // VST3LNdWB_fixed_Asm_32 415429U, // VST3LNdWB_fixed_Asm_8 157381U, // VST3LNdWB_register_Asm_16 288453U, // VST3LNdWB_register_Asm_32 419525U, // VST3LNdWB_register_Asm_8 153285U, // VST3LNqAsm_16 284357U, // VST3LNqAsm_32 153285U, // VST3LNqWB_fixed_Asm_16 284357U, // VST3LNqWB_fixed_Asm_32 157381U, // VST3LNqWB_register_Asm_16 288453U, // VST3LNqWB_register_Asm_32 3288495813U, // VST3dAsm_16 3288626885U, // VST3dAsm_32 3288757957U, // VST3dAsm_8 3288495813U, // VST3dWB_fixed_Asm_16 3288626885U, // VST3dWB_fixed_Asm_32 3288757957U, // VST3dWB_fixed_Asm_8 3288487621U, // VST3dWB_register_Asm_16 3288618693U, // VST3dWB_register_Asm_32 3288749765U, // VST3dWB_register_Asm_8 1157789381U, // VST3qAsm_16 1157920453U, // VST3qAsm_32 1158051525U, // VST3qAsm_8 2231531205U, // VST3qWB_fixed_Asm_16 2231662277U, // VST3qWB_fixed_Asm_32 2231793349U, // VST3qWB_fixed_Asm_8 84039365U, // VST3qWB_register_Asm_16 84170437U, // VST3qWB_register_Asm_32 84301509U, // VST3qWB_register_Asm_8 153302U, // VST4LNdAsm_16 284374U, // VST4LNdAsm_32 415446U, // VST4LNdAsm_8 153302U, // VST4LNdWB_fixed_Asm_16 284374U, // VST4LNdWB_fixed_Asm_32 415446U, // VST4LNdWB_fixed_Asm_8 157398U, // VST4LNdWB_register_Asm_16 288470U, // VST4LNdWB_register_Asm_32 419542U, // VST4LNdWB_register_Asm_8 153302U, // VST4LNqAsm_16 284374U, // VST4LNqAsm_32 153302U, // VST4LNqWB_fixed_Asm_16 284374U, // VST4LNqWB_fixed_Asm_32 157398U, // VST4LNqWB_register_Asm_16 288470U, // VST4LNqWB_register_Asm_32 3355604694U, // VST4dAsm_16 3355735766U, // VST4dAsm_32 3355866838U, // VST4dAsm_8 3355604694U, // VST4dWB_fixed_Asm_16 3355735766U, // VST4dWB_fixed_Asm_32 3355866838U, // VST4dWB_fixed_Asm_8 3355596502U, // VST4dWB_register_Asm_16 3355727574U, // VST4dWB_register_Asm_32 3355858646U, // VST4dWB_register_Asm_8 1224898262U, // VST4qAsm_16 1225029334U, // VST4qAsm_32 1225160406U, // VST4qAsm_8 2298640086U, // VST4qWB_fixed_Asm_16 2298771158U, // VST4qWB_fixed_Asm_32 2298902230U, // VST4qWB_fixed_Asm_8 151148246U, // VST4qWB_register_Asm_16 151279318U, // VST4qWB_register_Asm_32 151410390U, // VST4qWB_register_Asm_8 0U, // WIN__CHKSTK 0U, // WIN__DBZCHK 0U, // t2ABS 0U, // t2ADDSri 0U, // t2ADDSrr 0U, // t2ADDSrs 0U, // t2BR_JT 0U, // t2LDMIA_RET 14508U, // t2LDRBpcrel 15443U, // t2LDRConstPool 14929U, // t2LDRHpcrel 14526U, // t2LDRSBpcrel 14948U, // t2LDRSHpcrel 0U, // t2LDRpci_pic 15443U, // t2LDRpcrel 0U, // t2LEApcrel 0U, // t2LEApcrelJT 0U, // t2MOVCCasr 0U, // t2MOVCCi 0U, // t2MOVCCi16 0U, // t2MOVCCi32imm 0U, // t2MOVCClsl 0U, // t2MOVCClsr 0U, // t2MOVCCr 0U, // t2MOVCCror 31992U, // t2MOVSsi 23800U, // t2MOVSsr 0U, // t2MOVTi16_ga_pcrel 0U, // t2MOV_ga_pcrel 0U, // t2MOVi16_ga_pcrel 0U, // t2MOVi32imm 32234U, // t2MOVsi 24042U, // t2MOVsr 0U, // t2MVNCCi 0U, // t2RSBSri 0U, // t2RSBSrs 0U, // t2STRB_preidx 0U, // t2STRH_preidx 0U, // t2STR_preidx 0U, // t2SUBSri 0U, // t2SUBSrr 0U, // t2SUBSrs 0U, // t2TBB_JT 0U, // t2TBH_JT 0U, // tADCS 0U, // tADDSi3 0U, // tADDSi8 0U, // tADDSrr 0U, // tADDframe 0U, // tADJCALLSTACKDOWN 0U, // tADJCALLSTACKUP 0U, // tBRIND 0U, // tBR_JTr 0U, // tBX_CALL 0U, // tBX_RET 0U, // tBX_RET_vararg 0U, // tBfar 0U, // tLDMIA_UPD 15443U, // tLDRConstPool 0U, // tLDRLIT_ga_abs 0U, // tLDRLIT_ga_pcrel 0U, // tLDR_postidx 0U, // tLDRpci_pic 0U, // tLEApcrel 0U, // tLEApcrelJT 0U, // tMOVCCr_pseudo 0U, // tPOP_RET 0U, // tSBCS 0U, // tSUBSi3 0U, // tSUBSi8 0U, // tSUBSrr 0U, // tTAILJMPd 0U, // tTAILJMPdND 0U, // tTAILJMPr 0U, // tTBB_JT 0U, // tTBH_JT 0U, // tTPsoft 530745U, // ADCri 530745U, // ADCrr 559417U, // ADCrsi 39225U, // ADCrsr 530806U, // ADDri 530806U, // ADDrr 559478U, // ADDrsi 39286U, // ADDrsr 539726U, // ADR 1242211449U, // AESD 1242211457U, // AESE 1258988646U, // AESIMC 1258988656U, // AESMC 530859U, // ANDri 530859U, // ANDrr 559531U, // ANDrsi 39339U, // ANDrsr 555329U, // BFC 547483U, // BFI 530758U, // BICri 530758U, // BICrr 559430U, // BICrsi 39238U, // BICrsr 828725U, // BKPT 828697U, // BL 828772U, // BLX 1074314916U, // BLX_pred 828772U, // BLXi 1074313964U, // BL_pred 828768U, // BX 1074313901U, // BXJ 970304U, // BX_RET 1074314816U, // BX_pred 1074313296U, // Bcc 201907225U, // CDP 219210157U, // CDP2 3726U, // CLREX 540368U, // CLZ 539583U, // CMNri 539583U, // CMNzrr 555967U, // CMNzrsi 547775U, // CMNzrsr 539683U, // CMPri 539683U, // CMPrr 556067U, // CMPrsi 547875U, // CMPrsr 828709U, // CPS1p 1309211869U, // CPS2p 235470045U, // CPS3p 185246891U, // CRC32B 185246899U, // CRC32CB 185246973U, // CRC32CH 185247057U, // CRC32CW 185246965U, // CRC32H 185247049U, // CRC32W 1074313739U, // DBG 66762U, // DMB 66767U, // DSB 531562U, // EORri 531562U, // EORrr 560234U, // EORrsi 40042U, // EORrsr 838971U, // ERET 1326595561U, // FCONSTD 1326726633U, // FCONSTH 1326857705U, // FCONSTS 2332573243U, // FLDMXDB_UPD 572932U, // FLDMXIA 2332573188U, // FLDMXIA_UPD 1625313U, // FMSTAT 2332573251U, // FSTMXDB_UPD 572940U, // FSTMXIA 2332573196U, // FSTMXIA_UPD 1074314610U, // HINT 828720U, // HLT 828638U, // HVC 70868U, // ISB 538616U, // LDA 538701U, // LDAB 540284U, // LDAEX 538905U, // LDAEXB 268974533U, // LDAEXD 539263U, // LDAEXH 539165U, // LDAH 286975243U, // LDC2L_OFFSET 3524977931U, // LDC2L_OPTION 303752459U, // LDC2L_POST 320529675U, // LDC2L_PRE 286974356U, // LDC2_OFFSET 3524977044U, // LDC2_OPTION 303751572U, // LDC2_POST 320528788U, // LDC2_PRE 1275615989U, // LDCL_OFFSET 1275615989U, // LDCL_OPTION 1275615989U, // LDCL_POST 1275615989U, // LDCL_PRE 1275615549U, // LDC_OFFSET 1275615549U, // LDC_OPTION 1275615549U, // LDC_POST 1275615549U, // LDC_PRE 571388U, // LDMDA 2332571644U, // LDMDA_UPD 571519U, // LDMDB 2332571775U, // LDMDB_UPD 572300U, // LDMIA 2332572556U, // LDMIA_UPD 571538U, // LDMIB 2332571794U, // LDMIB_UPD 552232U, // LDRBT_POST_IMM 552232U, // LDRBT_POST_REG 551084U, // LDRB_POST_IMM 551084U, // LDRB_POST_REG 546988U, // LDRB_PRE_IMM 551084U, // LDRB_PRE_REG 555180U, // LDRBi12 546988U, // LDRBrs 551343U, // LDRD 580015U, // LDRD_POST 580015U, // LDRD_PRE 540296U, // LDREX 538919U, // LDREXB 268974547U, // LDREXD 539277U, // LDREXH 547409U, // LDRH 548171U, // LDRHTi 552267U, // LDRHTr 551505U, // LDRH_POST 551505U, // LDRH_PRE 547006U, // LDRSB 548148U, // LDRSBTi 552244U, // LDRSBTr 551102U, // LDRSB_POST 551102U, // LDRSB_PRE 547428U, // LDRSH 548183U, // LDRSHTi 552279U, // LDRSHTr 551524U, // LDRSH_POST 551524U, // LDRSH_PRE 552311U, // LDRT_POST_IMM 552311U, // LDRT_POST_REG 552019U, // LDR_POST_IMM 552019U, // LDR_POST_REG 547923U, // LDR_PRE_IMM 552019U, // LDR_PRE_REG 556115U, // LDRcp 556115U, // LDRi12 547923U, // LDRrs 201907274U, // MCR 168878515U, // MCR2 201878642U, // MCRR 168878521U, // MCRR2 559140U, // MLA 548021U, // MLS 1887722U, // MOVPCLR 556471U, // MOVTi16 544234U, // MOVi 540159U, // MOVi16 544234U, // MOVr 544234U, // MOVr_TC 531946U, // MOVsi 560618U, // MOVsr 336124238U, // MRC 74138U, // MRC2 352872786U, // MRRC 78240U, // MRRC2 2148056290U, // MRS 539874U, // MRSbanked 3221798114U, // MRSsys 369638536U, // MSR 386415752U, // MSRbanked 369638536U, // MSRi 531317U, // MUL 543747U, // MVNi 543747U, // MVNr 531459U, // MVNsi 560131U, // MVNsr 531576U, // ORRri 531576U, // ORRrr 560248U, // ORRrsi 40056U, // ORRrsr 548115U, // PKHBT 547023U, // PKHTB 83290U, // PLDWi12 87386U, // PLDWrs 83171U, // PLDi12 87267U, // PLDrs 83206U, // PLIi12 87302U, // PLIrs 555406U, // QADD 554800U, // QADD16 554903U, // QADD8 556729U, // QASX 555380U, // QDADD 555252U, // QDSUB 556588U, // QSAX 555265U, // QSUB 554762U, // QSUB16 554864U, // QSUB8 539998U, // RBIT 540118U, // REV 538452U, // REV16 539247U, // REVSH 828573U, // RFEDA 2008221U, // RFEDA_UPD 828604U, // RFEDB 2008252U, // RFEDB_UPD 828580U, // RFEIA 2008228U, // RFEIA_UPD 828611U, // RFEIB 2008259U, // RFEIB_UPD 530624U, // RSBri 530624U, // RSBrr 559296U, // RSBrsi 39104U, // RSBrsr 530775U, // RSCri 530775U, // RSCrr 559447U, // RSCrsi 39255U, // RSCrsr 554807U, // SADD16 554909U, // SADD8 556734U, // SASX 530741U, // SBCri 530741U, // SBCrr 559413U, // SBCrsi 39221U, // SBCrsr 548506U, // SBFX 556506U, // SDIV 555794U, // SEL 91368U, // SETEND 828701U, // SETPAN 168468546U, // SHA1C 1258987596U, // SHA1H 168468578U, // SHA1M 168468588U, // SHA1P 168468481U, // SHA1SU0 1242210331U, // SHA1SU1 168468566U, // SHA256H 168468533U, // SHA256H2 1242210317U, // SHA256SU0 168468519U, // SHA256SU1 554783U, // SHADD16 554888U, // SHADD8 556716U, // SHASX 556575U, // SHSAX 554745U, // SHSUB16 554849U, // SHSUB8 1074313546U, // SMC 546910U, // SMLABB 548108U, // SMLABT 547171U, // SMLAD 548432U, // SMLADX 96984U, // SMLAL 579685U, // SMLALBB 580889U, // SMLALBT 579992U, // SMLALD 581214U, // SMLALDX 579797U, // SMLALTB 581011U, // SMLALTT 547016U, // SMLATB 548236U, // SMLATT 547083U, // SMLAWB 548284U, // SMLAWT 547257U, // SMLSD 548462U, // SMLSDX 580003U, // SMLSLD 581222U, // SMLSLDX 546850U, // SMMLA 547907U, // SMMLAR 548019U, // SMMLS 547968U, // SMMLSR 555891U, // SMMUL 556130U, // SMMULR 555369U, // SMUAD 556631U, // SMUADX 555117U, // SMULBB 556321U, // SMULBT 559946U, // SMULL 555229U, // SMULTB 556443U, // SMULTT 555282U, // SMULWB 556483U, // SMULWT 555455U, // SMUSD 556661U, // SMUSDX 828836U, // SRSDA 828788U, // SRSDA_UPD 828858U, // SRSDB 828812U, // SRSDB_UPD 828847U, // SRSIA 828800U, // SRSIA_UPD 828869U, // SRSIB 828824U, // SRSIB_UPD 548093U, // SSAT 554821U, // SSAT16 556593U, // SSAX 554769U, // SSUB16 554870U, // SSUB8 286975250U, // STC2L_OFFSET 3524977938U, // STC2L_OPTION 303752466U, // STC2L_POST 320529682U, // STC2L_PRE 286974375U, // STC2_OFFSET 3524977063U, // STC2_OPTION 303751591U, // STC2_POST 320528807U, // STC2_PRE 1275615994U, // STCL_OFFSET 1275615994U, // STCL_OPTION 1275615994U, // STCL_POST 1275615994U, // STCL_PRE 1275615579U, // STC_OFFSET 1275615579U, // STC_OPTION 1275615579U, // STC_POST 1275615579U, // STC_PRE 539503U, // STL 538782U, // STLB 556674U, // STLEX 555296U, // STLEXB 555468U, // STLEXD 555654U, // STLEXH 539195U, // STLH 571394U, // STMDA 2332571650U, // STMDA_UPD 571526U, // STMDB 2332571782U, // STMDB_UPD 572306U, // STMIA 2332572562U, // STMIA_UPD 571544U, // STMIB 2332571800U, // STMIB_UPD 185101614U, // STRBT_POST_IMM 185101614U, // STRBT_POST_REG 185100465U, // STRB_POST_IMM 185100465U, // STRB_POST_REG 185096369U, // STRB_PRE_IMM 185100465U, // STRB_PRE_REG 555185U, // STRBi12 546993U, // STRBrs 551348U, // STRD 185129396U, // STRD_POST 185129396U, // STRD_PRE 556692U, // STREX 555310U, // STREXB 555482U, // STREXD 555668U, // STREXH 547414U, // STRH 185097553U, // STRHTi 185101649U, // STRHTr 185100886U, // STRH_POST 185100886U, // STRH_PRE 185101698U, // STRT_POST_IMM 185101698U, // STRT_POST_REG 185101460U, // STR_POST_IMM 185101460U, // STR_POST_REG 185097364U, // STR_PRE_IMM 185101460U, // STR_PRE_REG 556180U, // STRi12 547988U, // STRrs 530678U, // SUBri 530678U, // SUBrr 559350U, // SUBrsi 39158U, // SUBrsr 1074313567U, // SVC 556081U, // SWP 555175U, // SWPB 546898U, // SXTAB 546523U, // SXTAB16 547371U, // SXTAH 555242U, // SXTB 554731U, // SXTB16 555637U, // SXTH 539711U, // TEQri 539711U, // TEQrr 556095U, // TEQrsi 547903U, // TEQrsr 3092U, // TRAP 3092U, // TRAPNaCl 99545U, // TSB 540040U, // TSTri 540040U, // TSTrr 556424U, // TSTrsi 548232U, // TSTrsr 554814U, // UADD16 554915U, // UADD8 556739U, // UASX 548511U, // UBFX 828656U, // UDF 556511U, // UDIV 554791U, // UHADD16 554895U, // UHADD8 556722U, // UHASX 556581U, // UHSAX 554753U, // UHSUB16 554856U, // UHSUB8 580285U, // UMAAL 96990U, // UMLAL 559952U, // UMULL 554799U, // UQADD16 554902U, // UQADD8 556728U, // UQASX 556587U, // UQSAX 554761U, // UQSUB16 554863U, // UQSUB8 554882U, // USAD8 546650U, // USADA8 548098U, // USAT 554828U, // USAT16 556598U, // USAX 554776U, // USUB16 554876U, // USUB8 546904U, // UXTAB 546531U, // UXTAB16 547377U, // UXTAH 555247U, // UXTB 554738U, // UXTB16 555642U, // UXTH 169892547U, // VABALsv2i64 170023619U, // VABALsv4i32 170154691U, // VABALsv8i16 170285763U, // VABALuv2i64 170416835U, // VABALuv4i32 170547907U, // VABALuv8i16 170153971U, // VABAsv16i8 169891827U, // VABAsv2i32 170022899U, // VABAsv4i16 169891827U, // VABAsv4i32 170022899U, // VABAsv8i16 170153971U, // VABAsv8i8 170547187U, // VABAuv16i8 170285043U, // VABAuv2i32 170416115U, // VABAuv4i16 170285043U, // VABAuv4i32 170416115U, // VABAuv8i16 170547187U, // VABAuv8i8 186678015U, // VABDLsv2i64 186809087U, // VABDLsv4i32 186940159U, // VABDLsv8i16 187071231U, // VABDLuv2i64 187202303U, // VABDLuv4i32 187333375U, // VABDLuv8i16 253131119U, // VABDfd 253131119U, // VABDfq 253000047U, // VABDhd 253000047U, // VABDhq 186939759U, // VABDsv16i8 186677615U, // VABDsv2i32 186808687U, // VABDsv4i16 186677615U, // VABDsv4i32 186808687U, // VABDsv8i16 186939759U, // VABDsv8i8 187332975U, // VABDuv16i8 187070831U, // VABDuv2i32 187201903U, // VABDuv4i16 187070831U, // VABDuv4i32 187201903U, // VABDuv8i16 187332975U, // VABDuv8i8 252853412U, // VABSD 252984484U, // VABSH 253115556U, // VABSS 253115556U, // VABSfd 253115556U, // VABSfq 252984484U, // VABShd 252984484U, // VABShq 1260666020U, // VABSv16i8 1260403876U, // VABSv2i32 1260534948U, // VABSv4i16 1260403876U, // VABSv4i32 1260534948U, // VABSv8i16 1260666020U, // VABSv8i8 253131233U, // VACGEfd 253131233U, // VACGEfq 253000161U, // VACGEhd 253000161U, // VACGEhq 253132096U, // VACGTfd 253132096U, // VACGTfq 253001024U, // VACGThd 253001024U, // VACGThq 252869011U, // VADDD 253000083U, // VADDH 187464621U, // VADDHNv2i32 187595693U, // VADDHNv4i16 187726765U, // VADDHNv8i8 186678028U, // VADDLsv2i64 186809100U, // VADDLsv4i32 186940172U, // VADDLsv8i16 187071244U, // VADDLuv2i64 187202316U, // VADDLuv4i32 187333388U, // VADDLuv8i16 253131155U, // VADDS 186678772U, // VADDWsv2i64 186809844U, // VADDWsv4i32 186940916U, // VADDWsv8i16 187071988U, // VADDWuv2i64 187203060U, // VADDWuv4i32 187334132U, // VADDWuv8i16 253131155U, // VADDfd 253131155U, // VADDfq 253000083U, // VADDhd 253000083U, // VADDhq 187857299U, // VADDv16i8 187464083U, // VADDv1i64 187595155U, // VADDv2i32 187464083U, // VADDv2i64 187726227U, // VADDv4i16 187595155U, // VADDv4i32 187726227U, // VADDv8i16 187857299U, // VADDv8i8 555434U, // VANDd 555434U, // VANDq 555333U, // VBICd 405698885U, // VBICiv2i32 405829957U, // VBICiv4i16 405698885U, // VBICiv4i32 405829957U, // VBICiv8i16 555333U, // VBICq 547334U, // VBIFd 547334U, // VBIFq 548195U, // VBITd 548195U, // VBITq 547676U, // VBSLd 547676U, // VBSLq 185245957U, // VCADDv2f32 185246658U, // VCADDv4f16 185245957U, // VCADDv4f32 185246658U, // VCADDv8f16 253131834U, // VCEQfd 253131834U, // VCEQfq 253000762U, // VCEQhd 253000762U, // VCEQhq 187857978U, // VCEQv16i8 187595834U, // VCEQv2i32 187726906U, // VCEQv4i16 187595834U, // VCEQv4i32 187726906U, // VCEQv8i16 187857978U, // VCEQv8i8 1261583418U, // VCEQzv16i8 253115450U, // VCEQzv2f32 1261321274U, // VCEQzv2i32 252984378U, // VCEQzv4f16 253115450U, // VCEQzv4f32 1261452346U, // VCEQzv4i16 1261321274U, // VCEQzv4i32 252984378U, // VCEQzv8f16 1261452346U, // VCEQzv8i16 1261583418U, // VCEQzv8i8 253131239U, // VCGEfd 253131239U, // VCGEfq 253000167U, // VCGEhd 253000167U, // VCGEhq 186939879U, // VCGEsv16i8 186677735U, // VCGEsv2i32 186808807U, // VCGEsv4i16 186677735U, // VCGEsv4i32 186808807U, // VCGEsv8i16 186939879U, // VCGEsv8i8 187333095U, // VCGEuv16i8 187070951U, // VCGEuv2i32 187202023U, // VCGEuv4i16 187070951U, // VCGEuv4i32 187202023U, // VCGEuv8i16 187333095U, // VCGEuv8i8 1260665319U, // VCGEzv16i8 253114855U, // VCGEzv2f32 1260403175U, // VCGEzv2i32 252983783U, // VCGEzv4f16 253114855U, // VCGEzv4f32 1260534247U, // VCGEzv4i16 1260403175U, // VCGEzv4i32 252983783U, // VCGEzv8f16 1260534247U, // VCGEzv8i16 1260665319U, // VCGEzv8i8 253132102U, // VCGTfd 253132102U, // VCGTfq 253001030U, // VCGThd 253001030U, // VCGThq 186940742U, // VCGTsv16i8 186678598U, // VCGTsv2i32 186809670U, // VCGTsv4i16 186678598U, // VCGTsv4i32 186809670U, // VCGTsv8i16 186940742U, // VCGTsv8i8 187333958U, // VCGTuv16i8 187071814U, // VCGTuv2i32 187202886U, // VCGTuv4i16 187071814U, // VCGTuv4i32 187202886U, // VCGTuv8i16 187333958U, // VCGTuv8i8 1260666182U, // VCGTzv16i8 253115718U, // VCGTzv2f32 1260404038U, // VCGTzv2i32 252984646U, // VCGTzv4f16 253115718U, // VCGTzv4f32 1260535110U, // VCGTzv4i16 1260404038U, // VCGTzv4i32 252984646U, // VCGTzv8f16 1260535110U, // VCGTzv8i16 1260666182U, // VCGTzv8i8 1260665324U, // VCLEzv16i8 253114860U, // VCLEzv2f32 1260403180U, // VCLEzv2i32 252983788U, // VCLEzv4f16 253114860U, // VCLEzv4f32 1260534252U, // VCLEzv4i16 1260403180U, // VCLEzv4i32 252983788U, // VCLEzv8f16 1260534252U, // VCLEzv8i16 1260665324U, // VCLEzv8i8 1260666030U, // VCLSv16i8 1260403886U, // VCLSv2i32 1260534958U, // VCLSv4i16 1260403886U, // VCLSv4i32 1260534958U, // VCLSv8i16 1260666030U, // VCLSv8i8 1260666216U, // VCLTzv16i8 253115752U, // VCLTzv2f32 1260404072U, // VCLTzv2i32 252984680U, // VCLTzv4f16 253115752U, // VCLTzv4f32 1260535144U, // VCLTzv4i16 1260404072U, // VCLTzv4i32 252984680U, // VCLTzv8f16 1260535144U, // VCLTzv8i16 1260666216U, // VCLTzv8i8 1261584079U, // VCLZv16i8 1261321935U, // VCLZv2i32 1261453007U, // VCLZv4i16 1261321935U, // VCLZv4i32 1261453007U, // VCLZv8i16 1261584079U, // VCLZv8i8 168468718U, // VCMLAv2f32 168468718U, // VCMLAv2f32_indexed 168469419U, // VCMLAv4f16 168469419U, // VCMLAv4f16_indexed 168468718U, // VCMLAv4f32 168468718U, // VCMLAv4f32_indexed 168469419U, // VCMLAv8f16 168469419U, // VCMLAv8f16_indexed 252853282U, // VCMPD 252852728U, // VCMPED 252983800U, // VCMPEH 253114872U, // VCMPES 420657656U, // VCMPEZD 420788728U, // VCMPEZH 420919800U, // VCMPEZS 252984354U, // VCMPH 253115426U, // VCMPS 420658210U, // VCMPZD 420789282U, // VCMPZH 420920354U, // VCMPZS 408941U, // VCNTd 408941U, // VCNTq 1258987638U, // VCVTANSDf 1258988339U, // VCVTANSDh 1258987638U, // VCVTANSQf 1258988339U, // VCVTANSQh 1258987698U, // VCVTANUDf 1258988399U, // VCVTANUDh 1258987698U, // VCVTANUQf 1258988399U, // VCVTANUQh 1258987968U, // VCVTASD 1258988219U, // VCVTASH 1258987638U, // VCVTASS 1258988028U, // VCVTAUD 1258988279U, // VCVTAUH 1258987698U, // VCVTAUS 3422436U, // VCVTBDH 3553508U, // VCVTBHD 3684580U, // VCVTBHS 3815652U, // VCVTBSH 3947954U, // VCVTDS 1258987653U, // VCVTMNSDf 1258988354U, // VCVTMNSDh 1258987653U, // VCVTMNSQf 1258988354U, // VCVTMNSQh 1258987713U, // VCVTMNUDf 1258988414U, // VCVTMNUDh 1258987713U, // VCVTMNUQf 1258988414U, // VCVTMNUQh 1258987983U, // VCVTMSD 1258988234U, // VCVTMSH 1258987653U, // VCVTMSS 1258988043U, // VCVTMUD 1258988294U, // VCVTMUH 1258987713U, // VCVTMUS 1258987668U, // VCVTNNSDf 1258988369U, // VCVTNNSDh 1258987668U, // VCVTNNSQf 1258988369U, // VCVTNNSQh 1258987728U, // VCVTNNUDf 1258988429U, // VCVTNNUDh 1258987728U, // VCVTNNUQf 1258988429U, // VCVTNNUQh 1258987998U, // VCVTNSD 1258988249U, // VCVTNSH 1258987668U, // VCVTNSS 1258988058U, // VCVTNUD 1258988309U, // VCVTNUH 1258987728U, // VCVTNUS 1258987683U, // VCVTPNSDf 1258988384U, // VCVTPNSDh 1258987683U, // VCVTPNSQf 1258988384U, // VCVTPNSQh 1258987743U, // VCVTPNUDf 1258988444U, // VCVTPNUDh 1258987743U, // VCVTPNUQf 1258988444U, // VCVTPNUQh 1258988013U, // VCVTPSD 1258988264U, // VCVTPSH 1258987683U, // VCVTPSS 1258988073U, // VCVTPUD 1258988324U, // VCVTPUH 1258987743U, // VCVTPUS 4079026U, // VCVTSD 3423654U, // VCVTTDH 3554726U, // VCVTTHD 3685798U, // VCVTTHS 3816870U, // VCVTTSH 3816882U, // VCVTf2h 440417714U, // VCVTf2sd 440417714U, // VCVTf2sq 440548786U, // VCVTf2ud 440548786U, // VCVTf2uq 2403368370U, // VCVTf2xsd 2403368370U, // VCVTf2xsq 2403499442U, // VCVTf2xud 2403499442U, // VCVTf2xuq 3685810U, // VCVTh2f 440679858U, // VCVTh2sd 440679858U, // VCVTh2sq 440810930U, // VCVTh2ud 440810930U, // VCVTh2uq 2403630514U, // VCVTh2xsd 2403630514U, // VCVTh2xsq 2403761586U, // VCVTh2xud 2403761586U, // VCVTh2xuq 440942002U, // VCVTs2fd 440942002U, // VCVTs2fq 441073074U, // VCVTs2hd 441073074U, // VCVTs2hq 441204146U, // VCVTu2fd 441204146U, // VCVTu2fq 441335218U, // VCVTu2hd 441335218U, // VCVTu2hq 2403892658U, // VCVTxs2fd 2403892658U, // VCVTxs2fq 2404023730U, // VCVTxs2hd 2404023730U, // VCVTxs2hq 2404154802U, // VCVTxu2fd 2404154802U, // VCVTxu2fq 2404285874U, // VCVTxu2hd 2404285874U, // VCVTxu2hq 252870116U, // VDIVD 253001188U, // VDIVH 253132260U, // VDIVS 146475U, // VDUP16d 146475U, // VDUP16q 277547U, // VDUP32d 277547U, // VDUP32q 408619U, // VDUP8d 408619U, // VDUP8q 162859U, // VDUPLN16d 162859U, // VDUPLN16q 293931U, // VDUPLN32d 293931U, // VDUPLN32q 425003U, // VDUPLN8d 425003U, // VDUPLN8q 556137U, // VEORd 556137U, // VEORq 155082U, // VEXTd16 286154U, // VEXTd32 417226U, // VEXTd8 155082U, // VEXTq16 286154U, // VEXTq32 5266890U, // VEXTq64 417226U, // VEXTq8 2400344115U, // VFMAD 2400475187U, // VFMAH 2400606259U, // VFMAS 2400606259U, // VFMAfd 2400606259U, // VFMAfq 2400475187U, // VFMAhd 2400475187U, // VFMAhq 2400345284U, // VFMSD 2400476356U, // VFMSH 2400607428U, // VFMSS 2400607428U, // VFMSfd 2400607428U, // VFMSfq 2400476356U, // VFMShd 2400476356U, // VFMShq 2400344120U, // VFNMAD 2400475192U, // VFNMAH 2400606264U, // VFNMAS 2400345289U, // VFNMSD 2400476361U, // VFNMSH 2400607433U, // VFNMSS 294377U, // VGETLNi32 3408035305U, // VGETLNs16 3408166377U, // VGETLNs8 3408428521U, // VGETLNu16 3408559593U, // VGETLNu8 186939777U, // VHADDsv16i8 186677633U, // VHADDsv2i32 186808705U, // VHADDsv4i16 186677633U, // VHADDsv4i32 186808705U, // VHADDsv8i16 186939777U, // VHADDsv8i8 187332993U, // VHADDuv16i8 187070849U, // VHADDuv2i32 187201921U, // VHADDuv4i16 187070849U, // VHADDuv4i32 187201921U, // VHADDuv8i16 187332993U, // VHADDuv8i8 186939642U, // VHSUBsv16i8 186677498U, // VHSUBsv2i32 186808570U, // VHSUBsv4i16 186677498U, // VHSUBsv4i32 186808570U, // VHSUBsv8i16 186939642U, // VHSUBsv8i8 187332858U, // VHSUBuv16i8 187070714U, // VHSUBuv2i32 187201786U, // VHSUBuv4i16 187070714U, // VHSUBuv4i32 187201786U, // VHSUBuv8i16 187332858U, // VHSUBuv8i8 1258988577U, // VINSH 441597356U, // VJCVT 3674371694U, // VLD1DUPd16 453138030U, // VLD1DUPd16wb_fixed 453142126U, // VLD1DUPd16wb_register 3674502766U, // VLD1DUPd32 453269102U, // VLD1DUPd32wb_fixed 453273198U, // VLD1DUPd32wb_register 3674633838U, // VLD1DUPd8 453400174U, // VLD1DUPd8wb_fixed 453404270U, // VLD1DUPd8wb_register 3691148910U, // VLD1DUPq16 469915246U, // VLD1DUPq16wb_fixed 469919342U, // VLD1DUPq16wb_register 3691279982U, // VLD1DUPq32 470046318U, // VLD1DUPq32wb_fixed 470050414U, // VLD1DUPq32wb_register 3691411054U, // VLD1DUPq8 470177390U, // VLD1DUPq8wb_fixed 470181486U, // VLD1DUPq8wb_register 1079273070U, // VLD1LNd16 1079350894U, // VLD1LNd16_UPD 1079404142U, // VLD1LNd32 1079481966U, // VLD1LNd32_UPD 1079535214U, // VLD1LNd8 1079613038U, // VLD1LNd8_UPD 0U, // VLD1LNq16Pseudo 0U, // VLD1LNq16Pseudo_UPD 0U, // VLD1LNq32Pseudo 0U, // VLD1LNq32Pseudo_UPD 0U, // VLD1LNq8Pseudo 0U, // VLD1LNq8Pseudo_UPD 3707926126U, // VLD1d16 3355604590U, // VLD1d16Q 0U, // VLD1d16QPseudo 134370926U, // VLD1d16Qwb_fixed 134375022U, // VLD1d16Qwb_register 3288495726U, // VLD1d16T 0U, // VLD1d16TPseudo 67262062U, // VLD1d16Twb_fixed 67266158U, // VLD1d16Twb_register 486692462U, // VLD1d16wb_fixed 486696558U, // VLD1d16wb_register 3708057198U, // VLD1d32 3355735662U, // VLD1d32Q 0U, // VLD1d32QPseudo 134501998U, // VLD1d32Qwb_fixed 134506094U, // VLD1d32Qwb_register 3288626798U, // VLD1d32T 0U, // VLD1d32TPseudo 67393134U, // VLD1d32Twb_fixed 67397230U, // VLD1d32Twb_register 486823534U, // VLD1d32wb_fixed 486827630U, // VLD1d32wb_register 3713037934U, // VLD1d64 3360716398U, // VLD1d64Q 0U, // VLD1d64QPseudo 0U, // VLD1d64QPseudoWB_fixed 0U, // VLD1d64QPseudoWB_register 139482734U, // VLD1d64Qwb_fixed 139486830U, // VLD1d64Qwb_register 3293607534U, // VLD1d64T 0U, // VLD1d64TPseudo 0U, // VLD1d64TPseudoWB_fixed 0U, // VLD1d64TPseudoWB_register 72373870U, // VLD1d64Twb_fixed 72377966U, // VLD1d64Twb_register 491804270U, // VLD1d64wb_fixed 491808366U, // VLD1d64wb_register 3708188270U, // VLD1d8 3355866734U, // VLD1d8Q 0U, // VLD1d8QPseudo 134633070U, // VLD1d8Qwb_fixed 134637166U, // VLD1d8Qwb_register 3288757870U, // VLD1d8T 0U, // VLD1d8TPseudo 67524206U, // VLD1d8Twb_fixed 67528302U, // VLD1d8Twb_register 486954606U, // VLD1d8wb_fixed 486958702U, // VLD1d8wb_register 3724703342U, // VLD1q16 0U, // VLD1q16HighQPseudo 0U, // VLD1q16HighTPseudo 0U, // VLD1q16LowQPseudo_UPD 0U, // VLD1q16LowTPseudo_UPD 503469678U, // VLD1q16wb_fixed 503473774U, // VLD1q16wb_register 3724834414U, // VLD1q32 0U, // VLD1q32HighQPseudo 0U, // VLD1q32HighTPseudo 0U, // VLD1q32LowQPseudo_UPD 0U, // VLD1q32LowTPseudo_UPD 503600750U, // VLD1q32wb_fixed 503604846U, // VLD1q32wb_register 3729815150U, // VLD1q64 0U, // VLD1q64HighQPseudo 0U, // VLD1q64HighTPseudo 0U, // VLD1q64LowQPseudo_UPD 0U, // VLD1q64LowTPseudo_UPD 508581486U, // VLD1q64wb_fixed 508585582U, // VLD1q64wb_register 3724965486U, // VLD1q8 0U, // VLD1q8HighQPseudo 0U, // VLD1q8HighTPseudo 0U, // VLD1q8LowQPseudo_UPD 0U, // VLD1q8LowTPseudo_UPD 503731822U, // VLD1q8wb_fixed 503735918U, // VLD1q8wb_register 3691148954U, // VLD2DUPd16 469915290U, // VLD2DUPd16wb_fixed 469919386U, // VLD2DUPd16wb_register 3741480602U, // VLD2DUPd16x2 520246938U, // VLD2DUPd16x2wb_fixed 520251034U, // VLD2DUPd16x2wb_register 3691280026U, // VLD2DUPd32 470046362U, // VLD2DUPd32wb_fixed 470050458U, // VLD2DUPd32wb_register 3741611674U, // VLD2DUPd32x2 520378010U, // VLD2DUPd32x2wb_fixed 520382106U, // VLD2DUPd32x2wb_register 3691411098U, // VLD2DUPd8 470177434U, // VLD2DUPd8wb_fixed 470181530U, // VLD2DUPd8wb_register 3741742746U, // VLD2DUPd8x2 520509082U, // VLD2DUPd8x2wb_fixed 520513178U, // VLD2DUPd8x2wb_register 0U, // VLD2DUPq16EvenPseudo 0U, // VLD2DUPq16OddPseudo 0U, // VLD2DUPq32EvenPseudo 0U, // VLD2DUPq32OddPseudo 0U, // VLD2DUPq8EvenPseudo 0U, // VLD2DUPq8OddPseudo 1079350938U, // VLD2LNd16 0U, // VLD2LNd16Pseudo 0U, // VLD2LNd16Pseudo_UPD 1079355034U, // VLD2LNd16_UPD 1079482010U, // VLD2LNd32 0U, // VLD2LNd32Pseudo 0U, // VLD2LNd32Pseudo_UPD 1079486106U, // VLD2LNd32_UPD 1079613082U, // VLD2LNd8 0U, // VLD2LNd8Pseudo 0U, // VLD2LNd8Pseudo_UPD 1079617178U, // VLD2LNd8_UPD 1079350938U, // VLD2LNq16 0U, // VLD2LNq16Pseudo 0U, // VLD2LNq16Pseudo_UPD 1079355034U, // VLD2LNq16_UPD 1079482010U, // VLD2LNq32 0U, // VLD2LNq32Pseudo 0U, // VLD2LNq32Pseudo_UPD 1079486106U, // VLD2LNq32_UPD 3758257818U, // VLD2b16 537024154U, // VLD2b16wb_fixed 537028250U, // VLD2b16wb_register 3758388890U, // VLD2b32 537155226U, // VLD2b32wb_fixed 537159322U, // VLD2b32wb_register 3758519962U, // VLD2b8 537286298U, // VLD2b8wb_fixed 537290394U, // VLD2b8wb_register 3724703386U, // VLD2d16 503469722U, // VLD2d16wb_fixed 503473818U, // VLD2d16wb_register 3724834458U, // VLD2d32 503600794U, // VLD2d32wb_fixed 503604890U, // VLD2d32wb_register 3724965530U, // VLD2d8 503731866U, // VLD2d8wb_fixed 503735962U, // VLD2d8wb_register 3355604634U, // VLD2q16 0U, // VLD2q16Pseudo 0U, // VLD2q16PseudoWB_fixed 0U, // VLD2q16PseudoWB_register 134370970U, // VLD2q16wb_fixed 134375066U, // VLD2q16wb_register 3355735706U, // VLD2q32 0U, // VLD2q32Pseudo 0U, // VLD2q32PseudoWB_fixed 0U, // VLD2q32PseudoWB_register 134502042U, // VLD2q32wb_fixed 134506138U, // VLD2q32wb_register 3355866778U, // VLD2q8 0U, // VLD2q8Pseudo 0U, // VLD2q8PseudoWB_fixed 0U, // VLD2q8PseudoWB_register 134633114U, // VLD2q8wb_fixed 134637210U, // VLD2q8wb_register 2153014970U, // VLD3DUPd16 0U, // VLD3DUPd16Pseudo 0U, // VLD3DUPd16Pseudo_UPD 2153092794U, // VLD3DUPd16_UPD 2153146042U, // VLD3DUPd32 0U, // VLD3DUPd32Pseudo 0U, // VLD3DUPd32Pseudo_UPD 2153223866U, // VLD3DUPd32_UPD 2153277114U, // VLD3DUPd8 0U, // VLD3DUPd8Pseudo 0U, // VLD3DUPd8Pseudo_UPD 2153354938U, // VLD3DUPd8_UPD 2153014970U, // VLD3DUPq16 0U, // VLD3DUPq16EvenPseudo 0U, // VLD3DUPq16OddPseudo 2153092794U, // VLD3DUPq16_UPD 2153146042U, // VLD3DUPq32 0U, // VLD3DUPq32EvenPseudo 0U, // VLD3DUPq32OddPseudo 2153223866U, // VLD3DUPq32_UPD 2153277114U, // VLD3DUPq8 0U, // VLD3DUPq8EvenPseudo 0U, // VLD3DUPq8OddPseudo 2153354938U, // VLD3DUPq8_UPD 1079355066U, // VLD3LNd16 0U, // VLD3LNd16Pseudo 0U, // VLD3LNd16Pseudo_UPD 1079359162U, // VLD3LNd16_UPD 1079486138U, // VLD3LNd32 0U, // VLD3LNd32Pseudo 0U, // VLD3LNd32Pseudo_UPD 1079490234U, // VLD3LNd32_UPD 1079617210U, // VLD3LNd8 0U, // VLD3LNd8Pseudo 0U, // VLD3LNd8Pseudo_UPD 1079621306U, // VLD3LNd8_UPD 1079355066U, // VLD3LNq16 0U, // VLD3LNq16Pseudo 0U, // VLD3LNq16Pseudo_UPD 1079359162U, // VLD3LNq16_UPD 1079486138U, // VLD3LNq32 0U, // VLD3LNq32Pseudo 0U, // VLD3LNq32Pseudo_UPD 1079490234U, // VLD3LNq32_UPD 5531322U, // VLD3d16 0U, // VLD3d16Pseudo 0U, // VLD3d16Pseudo_UPD 5609146U, // VLD3d16_UPD 5662394U, // VLD3d32 0U, // VLD3d32Pseudo 0U, // VLD3d32Pseudo_UPD 5740218U, // VLD3d32_UPD 5793466U, // VLD3d8 0U, // VLD3d8Pseudo 0U, // VLD3d8Pseudo_UPD 5871290U, // VLD3d8_UPD 5531322U, // VLD3q16 0U, // VLD3q16Pseudo_UPD 5609146U, // VLD3q16_UPD 0U, // VLD3q16oddPseudo 0U, // VLD3q16oddPseudo_UPD 5662394U, // VLD3q32 0U, // VLD3q32Pseudo_UPD 5740218U, // VLD3q32_UPD 0U, // VLD3q32oddPseudo 0U, // VLD3q32oddPseudo_UPD 5793466U, // VLD3q8 0U, // VLD3q8Pseudo_UPD 5871290U, // VLD3q8_UPD 0U, // VLD3q8oddPseudo 0U, // VLD3q8oddPseudo_UPD 2153043665U, // VLD4DUPd16 0U, // VLD4DUPd16Pseudo 0U, // VLD4DUPd16Pseudo_UPD 2153105105U, // VLD4DUPd16_UPD 2153174737U, // VLD4DUPd32 0U, // VLD4DUPd32Pseudo 0U, // VLD4DUPd32Pseudo_UPD 2153236177U, // VLD4DUPd32_UPD 2153305809U, // VLD4DUPd8 0U, // VLD4DUPd8Pseudo 0U, // VLD4DUPd8Pseudo_UPD 2153367249U, // VLD4DUPd8_UPD 2153043665U, // VLD4DUPq16 0U, // VLD4DUPq16EvenPseudo 0U, // VLD4DUPq16OddPseudo 2153105105U, // VLD4DUPq16_UPD 2153174737U, // VLD4DUPq32 0U, // VLD4DUPq32EvenPseudo 0U, // VLD4DUPq32OddPseudo 2153236177U, // VLD4DUPq32_UPD 2153305809U, // VLD4DUPq8 0U, // VLD4DUPq8EvenPseudo 0U, // VLD4DUPq8OddPseudo 2153367249U, // VLD4DUPq8_UPD 1079359185U, // VLD4LNd16 0U, // VLD4LNd16Pseudo 0U, // VLD4LNd16Pseudo_UPD 1079367377U, // VLD4LNd16_UPD 1079490257U, // VLD4LNd32 0U, // VLD4LNd32Pseudo 0U, // VLD4LNd32Pseudo_UPD 1079498449U, // VLD4LNd32_UPD 1079621329U, // VLD4LNd8 0U, // VLD4LNd8Pseudo 0U, // VLD4LNd8Pseudo_UPD 1079629521U, // VLD4LNd8_UPD 1079359185U, // VLD4LNq16 0U, // VLD4LNq16Pseudo 0U, // VLD4LNq16Pseudo_UPD 1079367377U, // VLD4LNq16_UPD 1079490257U, // VLD4LNq32 0U, // VLD4LNq32Pseudo 0U, // VLD4LNq32Pseudo_UPD 1079498449U, // VLD4LNq32_UPD 5560017U, // VLD4d16 0U, // VLD4d16Pseudo 0U, // VLD4d16Pseudo_UPD 5621457U, // VLD4d16_UPD 5691089U, // VLD4d32 0U, // VLD4d32Pseudo 0U, // VLD4d32Pseudo_UPD 5752529U, // VLD4d32_UPD 5822161U, // VLD4d8 0U, // VLD4d8Pseudo 0U, // VLD4d8Pseudo_UPD 5883601U, // VLD4d8_UPD 5560017U, // VLD4q16 0U, // VLD4q16Pseudo_UPD 5621457U, // VLD4q16_UPD 0U, // VLD4q16oddPseudo 0U, // VLD4q16oddPseudo_UPD 5691089U, // VLD4q32 0U, // VLD4q32Pseudo_UPD 5752529U, // VLD4q32_UPD 0U, // VLD4q32oddPseudo 0U, // VLD4q32oddPseudo_UPD 5822161U, // VLD4q8 0U, // VLD4q8Pseudo_UPD 5883601U, // VLD4q8_UPD 0U, // VLD4q8oddPseudo 0U, // VLD4q8oddPseudo_UPD 2332571774U, // VLDMDDB_UPD 571406U, // VLDMDIA 2332571662U, // VLDMDIA_UPD 0U, // VLDMQIA 2332571774U, // VLDMSDB_UPD 571406U, // VLDMSIA 2332571662U, // VLDMSIA_UPD 556114U, // VLDRD 162898U, // VLDRH 556114U, // VLDRS 1074314122U, // VLLDM 1074314128U, // VLSTM 185246300U, // VMAXNMD 185246693U, // VMAXNMH 185245992U, // VMAXNMNDf 185246693U, // VMAXNMNDh 185245992U, // VMAXNMNQf 185246693U, // VMAXNMNQh 185245992U, // VMAXNMS 253132314U, // VMAXfd 253132314U, // VMAXfq 253001242U, // VMAXhd 253001242U, // VMAXhq 186940954U, // VMAXsv16i8 186678810U, // VMAXsv2i32 186809882U, // VMAXsv4i16 186678810U, // VMAXsv4i32 186809882U, // VMAXsv8i16 186940954U, // VMAXsv8i8 187334170U, // VMAXuv16i8 187072026U, // VMAXuv2i32 187203098U, // VMAXuv4i16 187072026U, // VMAXuv4i32 187203098U, // VMAXuv8i16 187334170U, // VMAXuv8i8 185246288U, // VMINNMD 185246681U, // VMINNMH 185245980U, // VMINNMNDf 185246681U, // VMINNMNDh 185245980U, // VMINNMNQf 185246681U, // VMINNMNQh 185245980U, // VMINNMS 253131706U, // VMINfd 253131706U, // VMINfq 253000634U, // VMINhd 253000634U, // VMINhq 186940346U, // VMINsv16i8 186678202U, // VMINsv2i32 186809274U, // VMINsv4i16 186678202U, // VMINsv4i32 186809274U, // VMINsv8i16 186940346U, // VMINsv8i8 187333562U, // VMINuv16i8 187071418U, // VMINuv2i32 187202490U, // VMINuv4i16 187071418U, // VMINuv4i32 187202490U, // VMINuv8i16 187333562U, // VMINuv8i8 2400344110U, // VMLAD 2400475182U, // VMLAH 169896676U, // VMLALslsv2i32 170027748U, // VMLALslsv4i16 170289892U, // VMLALsluv2i32 170420964U, // VMLALsluv4i16 169892580U, // VMLALsv2i64 170023652U, // VMLALsv4i32 170154724U, // VMLALsv8i16 170285796U, // VMLALuv2i64 170416868U, // VMLALuv4i32 170547940U, // VMLALuv8i16 2400606254U, // VMLAS 2400606254U, // VMLAfd 2400606254U, // VMLAfq 2400475182U, // VMLAhd 2400475182U, // VMLAhq 2400610350U, // VMLAslfd 2400610350U, // VMLAslfq 2400479278U, // VMLAslhd 2400479278U, // VMLAslhq 170813486U, // VMLAslv2i32 170944558U, // VMLAslv4i16 170813486U, // VMLAslv4i32 170944558U, // VMLAslv8i16 171071534U, // VMLAv16i8 170809390U, // VMLAv2i32 170940462U, // VMLAv4i16 170809390U, // VMLAv4i32 170940462U, // VMLAv8i16 171071534U, // VMLAv8i8 2400345279U, // VMLSD 2400476351U, // VMLSH 169896809U, // VMLSLslsv2i32 170027881U, // VMLSLslsv4i16 170290025U, // VMLSLsluv2i32 170421097U, // VMLSLsluv4i16 169892713U, // VMLSLsv2i64 170023785U, // VMLSLsv4i32 170154857U, // VMLSLsv8i16 170285929U, // VMLSLuv2i64 170417001U, // VMLSLuv4i32 170548073U, // VMLSLuv8i16 2400607423U, // VMLSS 2400607423U, // VMLSfd 2400607423U, // VMLSfq 2400476351U, // VMLShd 2400476351U, // VMLShq 2400611519U, // VMLSslfd 2400611519U, // VMLSslfq 2400480447U, // VMLSslhd 2400480447U, // VMLSslhq 170814655U, // VMLSslv2i32 170945727U, // VMLSslv4i16 170814655U, // VMLSslv4i32 170945727U, // VMLSslv8i16 171072703U, // VMLSv16i8 170810559U, // VMLSv2i32 170941631U, // VMLSv4i16 170810559U, // VMLSv4i32 170941631U, // VMLSv8i16 171072703U, // VMLSv8i8 252853737U, // VMOVD 556521U, // VMOVDRR 1258988623U, // VMOVH 252984809U, // VMOVHR 1260403588U, // VMOVLsv2i64 1260534660U, // VMOVLsv4i32 1260665732U, // VMOVLsv8i16 1260796804U, // VMOVLuv2i64 1260927876U, // VMOVLuv4i32 1261058948U, // VMOVLuv8i16 1261190158U, // VMOVNv2i32 1261321230U, // VMOVNv4i16 1261452302U, // VMOVNv8i8 252984809U, // VMOVRH 556521U, // VMOVRRD 548329U, // VMOVRRS 540137U, // VMOVRS 253115881U, // VMOVS 540137U, // VMOVSR 548329U, // VMOVSRR 405945833U, // VMOVv16i8 405552617U, // VMOVv1i64 1326857705U, // VMOVv2f32 405683689U, // VMOVv2i32 405552617U, // VMOVv2i64 1326857705U, // VMOVv4f32 405814761U, // VMOVv4i16 405683689U, // VMOVv4i32 405814761U, // VMOVv8i16 405945833U, // VMOVv8i8 3221798113U, // VMRS 572641U, // VMRS_FPEXC 1074314465U, // VMRS_FPINST 2148056289U, // VMRS_FPINST2 3221798113U, // VMRS_FPSID 572641U, // VMRS_MVFR0 1074314465U, // VMRS_MVFR1 2148056289U, // VMRS_MVFR2 5946503U, // VMSR 6077575U, // VMSR_FPEXC 6208647U, // VMSR_FPINST 6339719U, // VMSR_FPINST2 6470791U, // VMSR_FPSID 252869503U, // VMULD 253000575U, // VMULH 185246384U, // VMULLp64 6585174U, // VMULLp8 186669910U, // VMULLslsv2i32 186800982U, // VMULLslsv4i16 187063126U, // VMULLsluv2i32 187194198U, // VMULLsluv4i16 186678102U, // VMULLsv2i64 186809174U, // VMULLsv4i32 186940246U, // VMULLsv8i16 187071318U, // VMULLuv2i64 187202390U, // VMULLuv4i32 187333462U, // VMULLuv8i16 253131647U, // VMULS 253131647U, // VMULfd 253131647U, // VMULfq 253000575U, // VMULhd 253000575U, // VMULhq 6585215U, // VMULpd 6585215U, // VMULpq 253123455U, // VMULslfd 253123455U, // VMULslfq 252992383U, // VMULslhd 252992383U, // VMULslhq 187587455U, // VMULslv2i32 187718527U, // VMULslv4i16 187587455U, // VMULslv4i32 187718527U, // VMULslv8i16 187857791U, // VMULv16i8 187595647U, // VMULv2i32 187726719U, // VMULv4i16 187595647U, // VMULv4i32 187726719U, // VMULv8i16 187857791U, // VMULv8i8 539650U, // VMVNd 539650U, // VMVNq 405683202U, // VMVNv2i32 405814274U, // VMVNv4i16 405683202U, // VMVNv4i32 405814274U, // VMVNv8i16 252852757U, // VNEGD 252983829U, // VNEGH 253114901U, // VNEGS 253114901U, // VNEGf32q 253114901U, // VNEGfd 252983829U, // VNEGhd 252983829U, // VNEGhq 1260534293U, // VNEGs16d 1260534293U, // VNEGs16q 1260403221U, // VNEGs32d 1260403221U, // VNEGs32q 1260665365U, // VNEGs8d 1260665365U, // VNEGs8q 2400344104U, // VNMLAD 2400475176U, // VNMLAH 2400606248U, // VNMLAS 2400345273U, // VNMLSD 2400476345U, // VNMLSH 2400607417U, // VNMLSS 252869497U, // VNMULD 253000569U, // VNMULH 253131641U, // VNMULS 555999U, // VORNd 555999U, // VORNq 556151U, // VORRd 405699703U, // VORRiv2i32 405830775U, // VORRiv4i16 405699703U, // VORRiv4i32 405830775U, // VORRiv8i16 556151U, // VORRq 1243904713U, // VPADALsv16i8 1243642569U, // VPADALsv2i32 1243773641U, // VPADALsv4i16 1243642569U, // VPADALsv4i32 1243773641U, // VPADALsv8i16 1243904713U, // VPADALsv8i8 1244297929U, // VPADALuv16i8 1244035785U, // VPADALuv2i32 1244166857U, // VPADALuv4i16 1244035785U, // VPADALuv4i32 1244166857U, // VPADALuv8i16 1244297929U, // VPADALuv8i8 1260665605U, // VPADDLsv16i8 1260403461U, // VPADDLsv2i32 1260534533U, // VPADDLsv4i16 1260403461U, // VPADDLsv4i32 1260534533U, // VPADDLsv8i16 1260665605U, // VPADDLsv8i8 1261058821U, // VPADDLuv16i8 1260796677U, // VPADDLuv2i32 1260927749U, // VPADDLuv4i16 1260796677U, // VPADDLuv4i32 1260927749U, // VPADDLuv8i16 1261058821U, // VPADDLuv8i8 253131143U, // VPADDf 253000071U, // VPADDh 187726215U, // VPADDi16 187595143U, // VPADDi32 187857287U, // VPADDi8 253132308U, // VPMAXf 253001236U, // VPMAXh 186809876U, // VPMAXs16 186678804U, // VPMAXs32 186940948U, // VPMAXs8 187203092U, // VPMAXu16 187072020U, // VPMAXu32 187334164U, // VPMAXu8 253131700U, // VPMINf 253000628U, // VPMINh 186809268U, // VPMINs16 186678196U, // VPMINs32 186940340U, // VPMINs8 187202484U, // VPMINu16 187071412U, // VPMINu32 187333556U, // VPMINu8 1260666014U, // VQABSv16i8 1260403870U, // VQABSv2i32 1260534942U, // VQABSv4i16 1260403870U, // VQABSv4i32 1260534942U, // VQABSv8i16 1260666014U, // VQABSv8i8 186939789U, // VQADDsv16i8 191265165U, // VQADDsv1i64 186677645U, // VQADDsv2i32 191265165U, // VQADDsv2i64 186808717U, // VQADDsv4i16 186677645U, // VQADDsv4i32 186808717U, // VQADDsv8i16 186939789U, // VQADDsv8i8 187333005U, // VQADDuv16i8 191396237U, // VQADDuv1i64 187070861U, // VQADDuv2i32 191396237U, // VQADDuv2i64 187201933U, // VQADDuv4i16 187070861U, // VQADDuv4i32 187201933U, // VQADDuv8i16 187333005U, // VQADDuv8i8 169896656U, // VQDMLALslv2i32 170027728U, // VQDMLALslv4i16 169892560U, // VQDMLALv2i64 170023632U, // VQDMLALv4i32 169896801U, // VQDMLSLslv2i32 170027873U, // VQDMLSLslv4i16 169892705U, // VQDMLSLv2i64 170023777U, // VQDMLSLv4i32 186669632U, // VQDMULHslv2i32 186800704U, // VQDMULHslv4i16 186669632U, // VQDMULHslv4i32 186800704U, // VQDMULHslv8i16 186677824U, // VQDMULHv2i32 186808896U, // VQDMULHv4i16 186677824U, // VQDMULHv4i32 186808896U, // VQDMULHv8i16 186669890U, // VQDMULLslv2i32 186800962U, // VQDMULLslv4i16 186678082U, // VQDMULLv2i64 186809154U, // VQDMULLv4i32 1264991226U, // VQMOVNsuv2i32 1260403706U, // VQMOVNsuv4i16 1260534778U, // VQMOVNsuv8i8 1264991239U, // VQMOVNsv2i32 1260403719U, // VQMOVNsv4i16 1260534791U, // VQMOVNsv8i8 1265122311U, // VQMOVNuv2i32 1260796935U, // VQMOVNuv4i16 1260928007U, // VQMOVNuv8i8 1260665359U, // VQNEGv16i8 1260403215U, // VQNEGv2i32 1260534287U, // VQNEGv4i16 1260403215U, // VQNEGv4i32 1260534287U, // VQNEGv8i16 1260665359U, // VQNEGv8i8 169896482U, // VQRDMLAHslv2i32 170027554U, // VQRDMLAHslv4i16 169896482U, // VQRDMLAHslv4i32 170027554U, // VQRDMLAHslv8i16 169892386U, // VQRDMLAHv2i32 170023458U, // VQRDMLAHv4i16 169892386U, // VQRDMLAHv4i32 170023458U, // VQRDMLAHv8i16 169896539U, // VQRDMLSHslv2i32 170027611U, // VQRDMLSHslv4i16 169896539U, // VQRDMLSHslv4i32 170027611U, // VQRDMLSHslv8i16 169892443U, // VQRDMLSHv2i32 170023515U, // VQRDMLSHv4i16 169892443U, // VQRDMLSHv4i32 170023515U, // VQRDMLSHv8i16 186669640U, // VQRDMULHslv2i32 186800712U, // VQRDMULHslv4i16 186669640U, // VQRDMULHslv4i32 186800712U, // VQRDMULHslv8i16 186677832U, // VQRDMULHv2i32 186808904U, // VQRDMULHv4i16 186677832U, // VQRDMULHv4i32 186808904U, // VQRDMULHv8i16 186940188U, // VQRSHLsv16i8 191265564U, // VQRSHLsv1i64 186678044U, // VQRSHLsv2i32 191265564U, // VQRSHLsv2i64 186809116U, // VQRSHLsv4i16 186678044U, // VQRSHLsv4i32 186809116U, // VQRSHLsv8i16 186940188U, // VQRSHLsv8i8 187333404U, // VQRSHLuv16i8 191396636U, // VQRSHLuv1i64 187071260U, // VQRSHLuv2i32 191396636U, // VQRSHLuv2i64 187202332U, // VQRSHLuv4i16 187071260U, // VQRSHLuv4i32 187202332U, // VQRSHLuv8i16 187333404U, // VQRSHLuv8i8 191265738U, // VQRSHRNsv2i32 186678218U, // VQRSHRNsv4i16 186809290U, // VQRSHRNsv8i8 191396810U, // VQRSHRNuv2i32 187071434U, // VQRSHRNuv4i16 187202506U, // VQRSHRNuv8i8 191265777U, // VQRSHRUNv2i32 186678257U, // VQRSHRUNv4i16 186809329U, // VQRSHRUNv8i8 186940182U, // VQSHLsiv16i8 191265558U, // VQSHLsiv1i64 186678038U, // VQSHLsiv2i32 191265558U, // VQSHLsiv2i64 186809110U, // VQSHLsiv4i16 186678038U, // VQSHLsiv4i32 186809110U, // VQSHLsiv8i16 186940182U, // VQSHLsiv8i8 186940879U, // VQSHLsuv16i8 191266255U, // VQSHLsuv1i64 186678735U, // VQSHLsuv2i32 191266255U, // VQSHLsuv2i64 186809807U, // VQSHLsuv4i16 186678735U, // VQSHLsuv4i32 186809807U, // VQSHLsuv8i16 186940879U, // VQSHLsuv8i8 186940182U, // VQSHLsv16i8 191265558U, // VQSHLsv1i64 186678038U, // VQSHLsv2i32 191265558U, // VQSHLsv2i64 186809110U, // VQSHLsv4i16 186678038U, // VQSHLsv4i32 186809110U, // VQSHLsv8i16 186940182U, // VQSHLsv8i8 187333398U, // VQSHLuiv16i8 191396630U, // VQSHLuiv1i64 187071254U, // VQSHLuiv2i32 191396630U, // VQSHLuiv2i64 187202326U, // VQSHLuiv4i16 187071254U, // VQSHLuiv4i32 187202326U, // VQSHLuiv8i16 187333398U, // VQSHLuiv8i8 187333398U, // VQSHLuv16i8 191396630U, // VQSHLuv1i64 187071254U, // VQSHLuv2i32 191396630U, // VQSHLuv2i64 187202326U, // VQSHLuv4i16 187071254U, // VQSHLuv4i32 187202326U, // VQSHLuv8i16 187333398U, // VQSHLuv8i8 191265731U, // VQSHRNsv2i32 186678211U, // VQSHRNsv4i16 186809283U, // VQSHRNsv8i8 191396803U, // VQSHRNuv2i32 187071427U, // VQSHRNuv4i16 187202499U, // VQSHRNuv8i8 191265769U, // VQSHRUNv2i32 186678249U, // VQSHRUNv4i16 186809321U, // VQSHRUNv8i8 186939648U, // VQSUBsv16i8 191265024U, // VQSUBsv1i64 186677504U, // VQSUBsv2i32 191265024U, // VQSUBsv2i64 186808576U, // VQSUBsv4i16 186677504U, // VQSUBsv4i32 186808576U, // VQSUBsv8i16 186939648U, // VQSUBsv8i8 187332864U, // VQSUBuv16i8 191396096U, // VQSUBuv1i64 187070720U, // VQSUBuv2i32 191396096U, // VQSUBuv2i64 187201792U, // VQSUBuv4i16 187070720U, // VQSUBuv4i32 187201792U, // VQSUBuv8i16 187332864U, // VQSUBuv8i8 187464613U, // VRADDHNv2i32 187595685U, // VRADDHNv4i16 187726757U, // VRADDHNv8i8 1260796401U, // VRECPEd 253114865U, // VRECPEfd 253114865U, // VRECPEfq 252983793U, // VRECPEhd 252983793U, // VRECPEhq 1260796401U, // VRECPEq 253131994U, // VRECPSfd 253131994U, // VRECPSfq 253000922U, // VRECPShd 253000922U, // VRECPShq 407379U, // VREV16d8 407379U, // VREV16q8 145022U, // VREV32d16 407166U, // VREV32d8 145022U, // VREV32q16 407166U, // VREV32q8 145098U, // VREV64d16 276170U, // VREV64d32 407242U, // VREV64d8 145098U, // VREV64q16 276170U, // VREV64q32 407242U, // VREV64q8 186939770U, // VRHADDsv16i8 186677626U, // VRHADDsv2i32 186808698U, // VRHADDsv4i16 186677626U, // VRHADDsv4i32 186808698U, // VRHADDsv8i16 186939770U, // VRHADDsv8i8 187332986U, // VRHADDuv16i8 187070842U, // VRHADDuv2i32 187201914U, // VRHADDuv4i16 187070842U, // VRHADDuv4i32 187201914U, // VRHADDuv8i16 187332986U, // VRHADDuv8i8 1258988088U, // VRINTAD 1258988470U, // VRINTAH 1258987769U, // VRINTANDf 1258988470U, // VRINTANDh 1258987769U, // VRINTANQf 1258988470U, // VRINTANQh 1258987769U, // VRINTAS 1258988136U, // VRINTMD 1258988529U, // VRINTMH 1258987828U, // VRINTMNDf 1258988529U, // VRINTMNDh 1258987828U, // VRINTMNQf 1258988529U, // VRINTMNQh 1258987828U, // VRINTMS 1258988148U, // VRINTND 1258988541U, // VRINTNH 1258987840U, // VRINTNNDf 1258988541U, // VRINTNNDh 1258987840U, // VRINTNNQf 1258988541U, // VRINTNNQh 1258987840U, // VRINTNS 1258988160U, // VRINTPD 1258988553U, // VRINTPH 1258987852U, // VRINTPNDf 1258988553U, // VRINTPNDh 1258987852U, // VRINTPNQf 1258988553U, // VRINTPNQh 1258987852U, // VRINTPS 252853388U, // VRINTRD 252984460U, // VRINTRH 253115532U, // VRINTRS 252853960U, // VRINTXD 252985032U, // VRINTXH 1258987900U, // VRINTXNDf 1258988611U, // VRINTXNDh 1258987900U, // VRINTXNQf 1258988611U, // VRINTXNQh 253116104U, // VRINTXS 252853972U, // VRINTZD 252985044U, // VRINTZH 1258987912U, // VRINTZNDf 1258988634U, // VRINTZNDh 1258987912U, // VRINTZNQf 1258988634U, // VRINTZNQh 253116116U, // VRINTZS 186940195U, // VRSHLsv16i8 191265571U, // VRSHLsv1i64 186678051U, // VRSHLsv2i32 191265571U, // VRSHLsv2i64 186809123U, // VRSHLsv4i16 186678051U, // VRSHLsv4i32 186809123U, // VRSHLsv8i16 186940195U, // VRSHLsv8i8 187333411U, // VRSHLuv16i8 191396643U, // VRSHLuv1i64 187071267U, // VRSHLuv2i32 191396643U, // VRSHLuv2i64 187202339U, // VRSHLuv4i16 187071267U, // VRSHLuv4i32 187202339U, // VRSHLuv8i16 187333411U, // VRSHLuv8i8 187464658U, // VRSHRNv2i32 187595730U, // VRSHRNv4i16 187726802U, // VRSHRNv8i8 186940503U, // VRSHRsv16i8 191265879U, // VRSHRsv1i64 186678359U, // VRSHRsv2i32 191265879U, // VRSHRsv2i64 186809431U, // VRSHRsv4i16 186678359U, // VRSHRsv4i32 186809431U, // VRSHRsv8i16 186940503U, // VRSHRsv8i8 187333719U, // VRSHRuv16i8 191396951U, // VRSHRuv1i64 187071575U, // VRSHRuv2i32 191396951U, // VRSHRuv2i64 187202647U, // VRSHRuv4i16 187071575U, // VRSHRuv4i32 187202647U, // VRSHRuv8i16 187333719U, // VRSHRuv8i8 1260796414U, // VRSQRTEd 253114878U, // VRSQRTEfd 253114878U, // VRSQRTEfq 252983806U, // VRSQRTEhd 252983806U, // VRSQRTEhq 1260796414U, // VRSQRTEq 253132016U, // VRSQRTSfd 253132016U, // VRSQRTSfq 253000944U, // VRSQRTShd 253000944U, // VRSQRTShq 170154046U, // VRSRAsv16i8 174479422U, // VRSRAsv1i64 169891902U, // VRSRAsv2i32 174479422U, // VRSRAsv2i64 170022974U, // VRSRAsv4i16 169891902U, // VRSRAsv4i32 170022974U, // VRSRAsv8i16 170154046U, // VRSRAsv8i8 170547262U, // VRSRAuv16i8 174610494U, // VRSRAuv1i64 170285118U, // VRSRAuv2i32 174610494U, // VRSRAuv2i64 170416190U, // VRSRAuv4i16 170285118U, // VRSRAuv4i32 170416190U, // VRSRAuv8i16 170547262U, // VRSRAuv8i8 187464598U, // VRSUBHNv2i32 187595670U, // VRSUBHNv4i16 187726742U, // VRSUBHNv8i8 910473U, // VSDOTD 7070857U, // VSDOTDI 910473U, // VSDOTQ 7070857U, // VSDOTQI 185246348U, // VSELEQD 185246741U, // VSELEQH 185246040U, // VSELEQS 185246276U, // VSELGED 185246669U, // VSELGEH 185245968U, // VSELGES 185246372U, // VSELGTD 185246775U, // VSELGTH 185246064U, // VSELGTS 185246360U, // VSELVSD 185246763U, // VSELVSH 185246052U, // VSELVSS 3221380585U, // VSETLNi16 3221511657U, // VSETLNi32 3221642729U, // VSETLNi8 187726652U, // VSHLLi16 187595580U, // VSHLLi32 187857724U, // VSHLLi8 186678076U, // VSHLLsv2i64 186809148U, // VSHLLsv4i32 186940220U, // VSHLLsv8i16 187071292U, // VSHLLuv2i64 187202364U, // VSHLLuv4i32 187333436U, // VSHLLuv8i16 187857705U, // VSHLiv16i8 187464489U, // VSHLiv1i64 187595561U, // VSHLiv2i32 187464489U, // VSHLiv2i64 187726633U, // VSHLiv4i16 187595561U, // VSHLiv4i32 187726633U, // VSHLiv8i16 187857705U, // VSHLiv8i8 186940201U, // VSHLsv16i8 191265577U, // VSHLsv1i64 186678057U, // VSHLsv2i32 191265577U, // VSHLsv2i64 186809129U, // VSHLsv4i16 186678057U, // VSHLsv4i32 186809129U, // VSHLsv8i16 186940201U, // VSHLsv8i8 187333417U, // VSHLuv16i8 191396649U, // VSHLuv1i64 187071273U, // VSHLuv2i32 191396649U, // VSHLuv2i64 187202345U, // VSHLuv4i16 187071273U, // VSHLuv4i32 187202345U, // VSHLuv8i16 187333417U, // VSHLuv8i8 187464665U, // VSHRNv2i32 187595737U, // VSHRNv4i16 187726809U, // VSHRNv8i8 186940509U, // VSHRsv16i8 191265885U, // VSHRsv1i64 186678365U, // VSHRsv2i32 191265885U, // VSHRsv2i64 186809437U, // VSHRsv4i16 186678365U, // VSHRsv4i32 186809437U, // VSHRsv8i16 186940509U, // VSHRsv8i8 187333725U, // VSHRuv16i8 191396957U, // VSHRuv1i64 187071581U, // VSHRuv2i32 191396957U, // VSHRuv2i64 187202653U, // VSHRuv4i16 187071581U, // VSHRuv4i32 187202653U, // VSHRuv8i16 187333725U, // VSHRuv8i8 7110066U, // VSHTOD 256540082U, // VSHTOH 7241138U, // VSHTOS 443563442U, // VSITOD 443694514U, // VSITOH 440942002U, // VSITOS 416419U, // VSLIv16i8 5266083U, // VSLIv1i64 285347U, // VSLIv2i32 5266083U, // VSLIv2i64 154275U, // VSLIv4i16 285347U, // VSLIv4i32 154275U, // VSLIv8i16 416419U, // VSLIv8i8 1332772274U, // VSLTOD 1332903346U, // VSLTOH 1330150834U, // VSLTOS 252853628U, // VSQRTD 252984700U, // VSQRTH 253115772U, // VSQRTS 170154052U, // VSRAsv16i8 174479428U, // VSRAsv1i64 169891908U, // VSRAsv2i32 174479428U, // VSRAsv2i64 170022980U, // VSRAsv4i16 169891908U, // VSRAsv4i32 170022980U, // VSRAsv8i16 170154052U, // VSRAsv8i8 170547268U, // VSRAuv16i8 174610500U, // VSRAuv1i64 170285124U, // VSRAuv2i32 174610500U, // VSRAuv2i64 170416196U, // VSRAuv4i16 170285124U, // VSRAuv4i32 170416196U, // VSRAuv8i16 170547268U, // VSRAuv8i8 416424U, // VSRIv16i8 5266088U, // VSRIv1i64 285352U, // VSRIv2i32 5266088U, // VSRIv2i64 154280U, // VSRIv4i16 285352U, // VSRIv4i32 154280U, // VSRIv8i16 416424U, // VSRIv8i8 1247041145U, // VST1LNd16 1632949881U, // VST1LNd16_UPD 1247172217U, // VST1LNd32 1633080953U, // VST1LNd32_UPD 1247303289U, // VST1LNd8 1633212025U, // VST1LNd8_UPD 0U, // VST1LNq16Pseudo 0U, // VST1LNq16Pseudo_UPD 0U, // VST1LNq32Pseudo 0U, // VST1LNq32Pseudo_UPD 0U, // VST1LNq8Pseudo 0U, // VST1LNq8Pseudo_UPD 570586745U, // VST1d16 587363961U, // VST1d16Q 0U, // VST1d16QPseudo 604132985U, // VST1d16Qwb_fixed 620914297U, // VST1d16Qwb_register 637695609U, // VST1d16T 0U, // VST1d16TPseudo 654464633U, // VST1d16Twb_fixed 671245945U, // VST1d16Twb_register 688019065U, // VST1d16wb_fixed 704800377U, // VST1d16wb_register 570717817U, // VST1d32 587495033U, // VST1d32Q 0U, // VST1d32QPseudo 604264057U, // VST1d32Qwb_fixed 621045369U, // VST1d32Qwb_register 637826681U, // VST1d32T 0U, // VST1d32TPseudo 654595705U, // VST1d32Twb_fixed 671377017U, // VST1d32Twb_register 688150137U, // VST1d32wb_fixed 704931449U, // VST1d32wb_register 575698553U, // VST1d64 592475769U, // VST1d64Q 0U, // VST1d64QPseudo 0U, // VST1d64QPseudoWB_fixed 0U, // VST1d64QPseudoWB_register 609244793U, // VST1d64Qwb_fixed 626026105U, // VST1d64Qwb_register 642807417U, // VST1d64T 0U, // VST1d64TPseudo 0U, // VST1d64TPseudoWB_fixed 0U, // VST1d64TPseudoWB_register 659576441U, // VST1d64Twb_fixed 676357753U, // VST1d64Twb_register 693130873U, // VST1d64wb_fixed 709912185U, // VST1d64wb_register 570848889U, // VST1d8 587626105U, // VST1d8Q 0U, // VST1d8QPseudo 604395129U, // VST1d8Qwb_fixed 621176441U, // VST1d8Qwb_register 637957753U, // VST1d8T 0U, // VST1d8TPseudo 654726777U, // VST1d8Twb_fixed 671508089U, // VST1d8Twb_register 688281209U, // VST1d8wb_fixed 705062521U, // VST1d8wb_register 721581689U, // VST1q16 0U, // VST1q16HighQPseudo 0U, // VST1q16HighTPseudo 0U, // VST1q16LowQPseudo_UPD 0U, // VST1q16LowTPseudo_UPD 738350713U, // VST1q16wb_fixed 755132025U, // VST1q16wb_register 721712761U, // VST1q32 0U, // VST1q32HighQPseudo 0U, // VST1q32HighTPseudo 0U, // VST1q32LowQPseudo_UPD 0U, // VST1q32LowTPseudo_UPD 738481785U, // VST1q32wb_fixed 755263097U, // VST1q32wb_register 726693497U, // VST1q64 0U, // VST1q64HighQPseudo 0U, // VST1q64HighTPseudo 0U, // VST1q64LowQPseudo_UPD 0U, // VST1q64LowTPseudo_UPD 743462521U, // VST1q64wb_fixed 760243833U, // VST1q64wb_register 721843833U, // VST1q8 0U, // VST1q8HighQPseudo 0U, // VST1q8HighTPseudo 0U, // VST1q8LowQPseudo_UPD 0U, // VST1q8LowTPseudo_UPD 738612857U, // VST1q8wb_fixed 755394169U, // VST1q8wb_register 1247045301U, // VST2LNd16 0U, // VST2LNd16Pseudo 0U, // VST2LNd16Pseudo_UPD 1632999093U, // VST2LNd16_UPD 1247176373U, // VST2LNd32 0U, // VST2LNd32Pseudo 0U, // VST2LNd32Pseudo_UPD 1633130165U, // VST2LNd32_UPD 1247307445U, // VST2LNd8 0U, // VST2LNd8Pseudo 0U, // VST2LNd8Pseudo_UPD 1633261237U, // VST2LNd8_UPD 1247045301U, // VST2LNq16 0U, // VST2LNq16Pseudo 0U, // VST2LNq16Pseudo_UPD 1632999093U, // VST2LNq16_UPD 1247176373U, // VST2LNq32 0U, // VST2LNq32Pseudo 0U, // VST2LNq32Pseudo_UPD 1633130165U, // VST2LNq32_UPD 771913397U, // VST2b16 788682421U, // VST2b16wb_fixed 805463733U, // VST2b16wb_register 772044469U, // VST2b32 788813493U, // VST2b32wb_fixed 805594805U, // VST2b32wb_register 772175541U, // VST2b8 788944565U, // VST2b8wb_fixed 805725877U, // VST2b8wb_register 721581749U, // VST2d16 738350773U, // VST2d16wb_fixed 755132085U, // VST2d16wb_register 721712821U, // VST2d32 738481845U, // VST2d32wb_fixed 755263157U, // VST2d32wb_register 721843893U, // VST2d8 738612917U, // VST2d8wb_fixed 755394229U, // VST2d8wb_register 587364021U, // VST2q16 0U, // VST2q16Pseudo 0U, // VST2q16PseudoWB_fixed 0U, // VST2q16PseudoWB_register 604133045U, // VST2q16wb_fixed 620914357U, // VST2q16wb_register 587495093U, // VST2q32 0U, // VST2q32Pseudo 0U, // VST2q32PseudoWB_fixed 0U, // VST2q32PseudoWB_register 604264117U, // VST2q32wb_fixed 621045429U, // VST2q32wb_register 587626165U, // VST2q8 0U, // VST2q8Pseudo 0U, // VST2q8PseudoWB_fixed 0U, // VST2q8PseudoWB_register 604395189U, // VST2q8wb_fixed 621176501U, // VST2q8wb_register 1247073989U, // VST3LNd16 0U, // VST3LNd16Pseudo 0U, // VST3LNd16Pseudo_UPD 1633011397U, // VST3LNd16_UPD 1247205061U, // VST3LNd32 0U, // VST3LNd32Pseudo 0U, // VST3LNd32Pseudo_UPD 1633142469U, // VST3LNd32_UPD 1247336133U, // VST3LNd8 0U, // VST3LNd8Pseudo 0U, // VST3LNd8Pseudo_UPD 1633273541U, // VST3LNd8_UPD 1247073989U, // VST3LNq16 0U, // VST3LNq16Pseudo 0U, // VST3LNq16Pseudo_UPD 1633011397U, // VST3LNq16_UPD 1247205061U, // VST3LNq32 0U, // VST3LNq32Pseudo 0U, // VST3LNq32Pseudo_UPD 1633142469U, // VST3LNq32_UPD 173303493U, // VST3d16 0U, // VST3d16Pseudo 0U, // VST3d16Pseudo_UPD 559257285U, // VST3d16_UPD 173434565U, // VST3d32 0U, // VST3d32Pseudo 0U, // VST3d32Pseudo_UPD 559388357U, // VST3d32_UPD 173565637U, // VST3d8 0U, // VST3d8Pseudo 0U, // VST3d8Pseudo_UPD 559519429U, // VST3d8_UPD 173303493U, // VST3q16 0U, // VST3q16Pseudo_UPD 559257285U, // VST3q16_UPD 0U, // VST3q16oddPseudo 0U, // VST3q16oddPseudo_UPD 173434565U, // VST3q32 0U, // VST3q32Pseudo_UPD 559388357U, // VST3q32_UPD 0U, // VST3q32oddPseudo 0U, // VST3q32oddPseudo_UPD 173565637U, // VST3q8 0U, // VST3q8Pseudo_UPD 559519429U, // VST3q8_UPD 0U, // VST3q8oddPseudo 0U, // VST3q8oddPseudo_UPD 1247123158U, // VST4LNd16 0U, // VST4LNd16Pseudo 0U, // VST4LNd16Pseudo_UPD 1633003222U, // VST4LNd16_UPD 1247254230U, // VST4LNd32 0U, // VST4LNd32Pseudo 0U, // VST4LNd32Pseudo_UPD 1633134294U, // VST4LNd32_UPD 1247385302U, // VST4LNd8 0U, // VST4LNd8Pseudo 0U, // VST4LNd8Pseudo_UPD 1633265366U, // VST4LNd8_UPD 1247123158U, // VST4LNq16 0U, // VST4LNq16Pseudo 0U, // VST4LNq16Pseudo_UPD 1633003222U, // VST4LNq16_UPD 1247254230U, // VST4LNq32 0U, // VST4LNq32Pseudo 0U, // VST4LNq32Pseudo_UPD 1633134294U, // VST4LNq32_UPD 173332182U, // VST4d16 0U, // VST4d16Pseudo 0U, // VST4d16Pseudo_UPD 559269590U, // VST4d16_UPD 173463254U, // VST4d32 0U, // VST4d32Pseudo 0U, // VST4d32Pseudo_UPD 559400662U, // VST4d32_UPD 173594326U, // VST4d8 0U, // VST4d8Pseudo 0U, // VST4d8Pseudo_UPD 559531734U, // VST4d8_UPD 173332182U, // VST4q16 0U, // VST4q16Pseudo_UPD 559269590U, // VST4q16_UPD 0U, // VST4q16oddPseudo 0U, // VST4q16oddPseudo_UPD 173463254U, // VST4q32 0U, // VST4q32Pseudo_UPD 559400662U, // VST4q32_UPD 0U, // VST4q32oddPseudo 0U, // VST4q32oddPseudo_UPD 173594326U, // VST4q8 0U, // VST4q8Pseudo_UPD 559531734U, // VST4q8_UPD 0U, // VST4q8oddPseudo 0U, // VST4q8oddPseudo_UPD 2332571781U, // VSTMDDB_UPD 571413U, // VSTMDIA 2332571669U, // VSTMDIA_UPD 0U, // VSTMQIA 2332571781U, // VSTMSDB_UPD 571413U, // VSTMSIA 2332571669U, // VSTMSIA_UPD 556179U, // VSTRD 162963U, // VSTRH 556179U, // VSTRS 252868870U, // VSUBD 252999942U, // VSUBH 187464606U, // VSUBHNv2i32 187595678U, // VSUBHNv4i16 187726750U, // VSUBHNv8i8 186677999U, // VSUBLsv2i64 186809071U, // VSUBLsv4i32 186940143U, // VSUBLsv8i16 187071215U, // VSUBLuv2i64 187202287U, // VSUBLuv4i32 187333359U, // VSUBLuv8i16 253131014U, // VSUBS 186678766U, // VSUBWsv2i64 186809838U, // VSUBWsv4i32 186940910U, // VSUBWsv8i16 187071982U, // VSUBWuv2i64 187203054U, // VSUBWuv4i32 187334126U, // VSUBWuv8i16 253131014U, // VSUBfd 253131014U, // VSUBfq 252999942U, // VSUBhd 252999942U, // VSUBhq 187857158U, // VSUBv16i8 187463942U, // VSUBv1i64 187595014U, // VSUBv2i32 187463942U, // VSUBv2i64 187726086U, // VSUBv4i16 187595014U, // VSUBv4i32 187726086U, // VSUBv8i16 187857158U, // VSUBv8i8 547888U, // VSWPd 547888U, // VSWPq 424682U, // VTBL1 424682U, // VTBL2 424682U, // VTBL3 0U, // VTBL3Pseudo 424682U, // VTBL4 0U, // VTBL4Pseudo 417355U, // VTBX1 417355U, // VTBX2 417355U, // VTBX3 0U, // VTBX3Pseudo 417355U, // VTBX4 0U, // VTBX4Pseudo 7634354U, // VTOSHD 256146866U, // VTOSHH 7765426U, // VTOSHS 441597080U, // VTOSIRD 444087448U, // VTOSIRH 440417432U, // VTOSIRS 441597362U, // VTOSIZD 444087730U, // VTOSIZH 440417714U, // VTOSIZS 1330806194U, // VTOSLD 1333296562U, // VTOSLH 1329626546U, // VTOSLS 8027570U, // VTOUHD 256277938U, // VTOUHH 8158642U, // VTOUHS 444480664U, // VTOUIRD 444611736U, // VTOUIRH 440548504U, // VTOUIRS 444480946U, // VTOUIZD 444612018U, // VTOUIZH 440548786U, // VTOUIZS 1333689778U, // VTOULD 1333820850U, // VTOULH 1329757618U, // VTOULS 154596U, // VTRNd16 285668U, // VTRNd32 416740U, // VTRNd8 154596U, // VTRNq16 285668U, // VTRNq32 416740U, // VTRNq8 425351U, // VTSTv16i8 294279U, // VTSTv2i32 163207U, // VTSTv4i16 294279U, // VTSTv4i32 163207U, // VTSTv8i16 425351U, // VTSTv8i8 910483U, // VUDOTD 7070867U, // VUDOTDI 910483U, // VUDOTQ 7070867U, // VUDOTQI 8551858U, // VUHTOD 256802226U, // VUHTOH 8682930U, // VUHTOS 445005234U, // VUITOD 445136306U, // VUITOH 441204146U, // VUITOS 1334214066U, // VULTOD 1334345138U, // VULTOH 1330412978U, // VULTOS 154677U, // VUZPd16 416821U, // VUZPd8 154677U, // VUZPq16 285749U, // VUZPq32 416821U, // VUZPq8 154653U, // VZIPd16 416797U, // VZIPd8 154653U, // VZIPq16 285725U, // VZIPq32 416797U, // VZIPq8 571388U, // sysLDMDA 2332571644U, // sysLDMDA_UPD 571519U, // sysLDMDB 2332571775U, // sysLDMDB_UPD 572300U, // sysLDMIA 2332572556U, // sysLDMIA_UPD 571538U, // sysLDMIB 2332571794U, // sysLDMIB_UPD 571394U, // sysSTMDA 2332571650U, // sysSTMDA_UPD 571526U, // sysSTMDB 2332571782U, // sysSTMDB_UPD 572306U, // sysSTMIA 2332572562U, // sysSTMIA_UPD 571544U, // sysSTMIB 2332571800U, // sysSTMIB_UPD 530745U, // t2ADCri 9050425U, // t2ADCrr 9079097U, // t2ADCrs 9050486U, // t2ADDri 556533U, // t2ADDri12 9050486U, // t2ADDrr 9079158U, // t2ADDrs 9059406U, // t2ADR 530859U, // t2ANDri 9050539U, // t2ANDrr 9079211U, // t2ANDrs 9051260U, // t2ASRri 9051260U, // t2ASRrr 1082832976U, // t2B 555329U, // t2BFC 547483U, // t2BFI 530758U, // t2BICri 9050438U, // t2BICrr 9079110U, // t2BICrs 1074313901U, // t2BXJ 1082832976U, // t2Bcc 201907225U, // t2CDP 201905823U, // t2CDP2 839310U, // t2CLREX 540368U, // t2CLZ 9059263U, // t2CMNri 9059263U, // t2CMNzrr 9075647U, // t2CMNzrs 9059363U, // t2CMPri 9059363U, // t2CMPrr 9075747U, // t2CMPrs 828709U, // t2CPS1p 1317731549U, // t2CPS2p 235470045U, // t2CPS3p 185246891U, // t2CRC32B 185246899U, // t2CRC32CB 185246973U, // t2CRC32CH 185247057U, // t2CRC32CW 185246965U, // t2CRC32H 185247049U, // t2CRC32W 1074313739U, // t2DBG 837235U, // t2DCPS1 837295U, // t2DCPS2 837311U, // t2DCPS3 822655139U, // t2DMB 822655158U, // t2DSB 531562U, // t2EORri 9051242U, // t2EORrr 9079914U, // t2EORrs 1082834290U, // t2HINT 828731U, // t2HVC 839432378U, // t2ISB 17313120U, // t2IT 0U, // t2Int_eh_sjlj_setjmp 0U, // t2Int_eh_sjlj_setjmp_nofp 538616U, // t2LDA 538701U, // t2LDAB 540284U, // t2LDAEX 538905U, // t2LDAEXB 555461U, // t2LDAEXD 539263U, // t2LDAEXH 539165U, // t2LDAH 1275615921U, // t2LDC2L_OFFSET 1275615921U, // t2LDC2L_OPTION 1275615921U, // t2LDC2L_POST 1275615921U, // t2LDC2L_PRE 1275614853U, // t2LDC2_OFFSET 1275614853U, // t2LDC2_OPTION 1275614853U, // t2LDC2_POST 1275614853U, // t2LDC2_PRE 1275615989U, // t2LDCL_OFFSET 1275615989U, // t2LDCL_OPTION 1275615989U, // t2LDCL_POST 1275615989U, // t2LDCL_PRE 1275615549U, // t2LDC_OFFSET 1275615549U, // t2LDC_OPTION 1275615549U, // t2LDC_POST 1275615549U, // t2LDC_PRE 571519U, // t2LDMDB 2332571775U, // t2LDMDB_UPD 9091980U, // t2LDMIA 2341092236U, // t2LDMIA_UPD 556328U, // t2LDRBT 546988U, // t2LDRB_POST 546988U, // t2LDRB_PRE 9074860U, // t2LDRBi12 555180U, // t2LDRBi8 9058476U, // t2LDRBpci 9066668U, // t2LDRBs 551343U, // t2LDRD_POST 551343U, // t2LDRD_PRE 547247U, // t2LDRDi8 556680U, // t2LDREX 538919U, // t2LDREXB 555475U, // t2LDREXD 539277U, // t2LDREXH 556363U, // t2LDRHT 547409U, // t2LDRH_POST 547409U, // t2LDRH_PRE 9075281U, // t2LDRHi12 555601U, // t2LDRHi8 9058897U, // t2LDRHpci 9067089U, // t2LDRHs 556340U, // t2LDRSBT 547006U, // t2LDRSB_POST 547006U, // t2LDRSB_PRE 9074878U, // t2LDRSBi12 555198U, // t2LDRSBi8 9058494U, // t2LDRSBpci 9066686U, // t2LDRSBs 556375U, // t2LDRSHT 547428U, // t2LDRSH_POST 547428U, // t2LDRSH_PRE 9075300U, // t2LDRSHi12 555620U, // t2LDRSHi8 9058916U, // t2LDRSHpci 9067108U, // t2LDRSHs 556407U, // t2LDRT 547923U, // t2LDR_POST 547923U, // t2LDR_PRE 9075795U, // t2LDRi12 556115U, // t2LDRi8 9059411U, // t2LDRpci 9067603U, // t2LDRs 9050981U, // t2LSLri 9050981U, // t2LSLrr 9051267U, // t2LSRri 9051267U, // t2LSRrr 201907274U, // t2MCR 201905828U, // t2MCR2 201878642U, // t2MCRR 201877161U, // t2MCRR2 546852U, // t2MLA 548021U, // t2MLS 556471U, // t2MOVTi16 9063914U, // t2MOVi 540159U, // t2MOVi16 9063914U, // t2MOVr 9059558U, // t2MOVsra_flag 9059563U, // t2MOVsrl_flag 336124238U, // t2MRC 336123530U, // t2MRC2 352872786U, // t2MRRC 352872079U, // t2MRRC2 2148056290U, // t2MRS_AR 539874U, // t2MRS_M 539874U, // t2MRSbanked 3221798114U, // t2MRSsys_AR 369638536U, // t2MSR_AR 369638536U, // t2MSR_M 386415752U, // t2MSRbanked 555893U, // t2MUL 543747U, // t2MVNi 9063427U, // t2MVNr 9051139U, // t2MVNs 531424U, // t2ORNri 531424U, // t2ORNrr 560096U, // t2ORNrs 531576U, // t2ORRri 9051256U, // t2ORRrr 9079928U, // t2ORRrs 548115U, // t2PKHBT 547023U, // t2PKHTB 856178170U, // t2PLDWi12 872955386U, // t2PLDWi8 889748986U, // t2PLDWs 856177055U, // t2PLDi12 872954271U, // t2PLDi8 906541471U, // t2PLDpci 889747871U, // t2PLDs 856177311U, // t2PLIi12 872954527U, // t2PLIi8 906541727U, // t2PLIpci 889748127U, // t2PLIs 555406U, // t2QADD 554800U, // t2QADD16 554903U, // t2QADD8 556729U, // t2QASX 555380U, // t2QDADD 555252U, // t2QDSUB 556588U, // t2QSAX 555265U, // t2QSUB 554762U, // t2QSUB16 554864U, // t2QSUB8 539998U, // t2RBIT 9059798U, // t2REV 9058132U, // t2REV16 9058927U, // t2REVSH 1074313336U, // t2RFEDB 2148055160U, // t2RFEDBW 1074313224U, // t2RFEIA 2148055048U, // t2RFEIAW 9051246U, // t2RORri 9051246U, // t2RORrr 544424U, // t2RRX 9050304U, // t2RSBri 530624U, // t2RSBrr 559296U, // t2RSBrs 554807U, // t2SADD16 554909U, // t2SADD8 556734U, // t2SASX 530741U, // t2SBCri 9050421U, // t2SBCrr 9079093U, // t2SBCrs 548506U, // t2SBFX 556506U, // t2SDIV 555794U, // t2SEL 828701U, // t2SETPAN 838170U, // t2SG 554783U, // t2SHADD16 554888U, // t2SHADD8 556716U, // t2SHASX 556575U, // t2SHSAX 554745U, // t2SHSUB16 554849U, // t2SHSUB8 1074313546U, // t2SMC 546910U, // t2SMLABB 548108U, // t2SMLABT 547171U, // t2SMLAD 548432U, // t2SMLADX 580312U, // t2SMLAL 579685U, // t2SMLALBB 580889U, // t2SMLALBT 579992U, // t2SMLALD 581214U, // t2SMLALDX 579797U, // t2SMLALTB 581011U, // t2SMLALTT 547016U, // t2SMLATB 548236U, // t2SMLATT 547083U, // t2SMLAWB 548284U, // t2SMLAWT 547257U, // t2SMLSD 548462U, // t2SMLSDX 580003U, // t2SMLSLD 581222U, // t2SMLSLDX 546850U, // t2SMMLA 547907U, // t2SMMLAR 548019U, // t2SMMLS 547968U, // t2SMMLSR 555891U, // t2SMMUL 556130U, // t2SMMULR 555369U, // t2SMUAD 556631U, // t2SMUADX 555117U, // t2SMULBB 556321U, // t2SMULBT 547658U, // t2SMULL 555229U, // t2SMULTB 556443U, // t2SMULTT 555282U, // t2SMULWB 556483U, // t2SMULWT 555455U, // t2SMUSD 556661U, // t2SMUSDX 9222284U, // t2SRSDB 9353356U, // t2SRSDB_UPD 9222172U, // t2SRSIA 9353244U, // t2SRSIA_UPD 548093U, // t2SSAT 554821U, // t2SSAT16 556593U, // t2SSAX 554769U, // t2SSUB16 554870U, // t2SSUB8 1275615927U, // t2STC2L_OFFSET 1275615927U, // t2STC2L_OPTION 1275615927U, // t2STC2L_POST 1275615927U, // t2STC2L_PRE 1275614869U, // t2STC2_OFFSET 1275614869U, // t2STC2_OPTION 1275614869U, // t2STC2_POST 1275614869U, // t2STC2_PRE 1275615994U, // t2STCL_OFFSET 1275615994U, // t2STCL_OPTION 1275615994U, // t2STCL_POST 1275615994U, // t2STCL_PRE 1275615579U, // t2STC_OFFSET 1275615579U, // t2STC_OPTION 1275615579U, // t2STC_POST 1275615579U, // t2STC_PRE 539503U, // t2STL 538782U, // t2STLB 556674U, // t2STLEX 555296U, // t2STLEXB 547276U, // t2STLEXD 555654U, // t2STLEXH 539195U, // t2STLH 571526U, // t2STMDB 2332571782U, // t2STMDB_UPD 9091986U, // t2STMIA 2341092242U, // t2STMIA_UPD 556334U, // t2STRBT 185096369U, // t2STRB_POST 185096369U, // t2STRB_PRE 9074865U, // t2STRBi12 555185U, // t2STRBi8 9066673U, // t2STRBs 185100724U, // t2STRD_POST 185100724U, // t2STRD_PRE 547252U, // t2STRDi8 548500U, // t2STREX 555310U, // t2STREXB 547290U, // t2STREXD 555668U, // t2STREXH 556369U, // t2STRHT 185096790U, // t2STRH_POST 185096790U, // t2STRH_PRE 9075286U, // t2STRHi12 555606U, // t2STRHi8 9067094U, // t2STRHs 556418U, // t2STRT 185097364U, // t2STR_POST 185097364U, // t2STR_PRE 9075860U, // t2STRi12 556180U, // t2STRi8 9067668U, // t2STRs 9485481U, // t2SUBS_PC_LR 9050358U, // t2SUBri 556527U, // t2SUBri12 9050358U, // t2SUBrr 9079030U, // t2SUBrs 546898U, // t2SXTAB 546523U, // t2SXTAB16 547371U, // t2SXTAH 9074922U, // t2SXTB 554731U, // t2SXTB16 9075317U, // t2SXTH 923285620U, // t2TBB 940063287U, // t2TBH 9059391U, // t2TEQri 9059391U, // t2TEQrr 9075775U, // t2TEQrs 956872900U, // t2TSB 9059720U, // t2TSTri 9059720U, // t2TSTrr 9076104U, // t2TSTrs 540048U, // t2TT 538697U, // t2TTA 539911U, // t2TTAT 540066U, // t2TTT 554814U, // t2UADD16 554915U, // t2UADD8 556739U, // t2UASX 548511U, // t2UBFX 828738U, // t2UDF 556511U, // t2UDIV 554791U, // t2UHADD16 554895U, // t2UHADD8 556722U, // t2UHASX 556581U, // t2UHSAX 554753U, // t2UHSUB16 554856U, // t2UHSUB8 580285U, // t2UMAAL 580318U, // t2UMLAL 547664U, // t2UMULL 554799U, // t2UQADD16 554902U, // t2UQADD8 556728U, // t2UQASX 556587U, // t2UQSAX 554761U, // t2UQSUB16 554863U, // t2UQSUB8 554882U, // t2USAD8 546650U, // t2USADA8 548098U, // t2USAT 554828U, // t2USAT16 556598U, // t2USAX 554776U, // t2USUB16 554876U, // t2USUB8 546904U, // t2UXTAB 546531U, // t2UXTAB16 547377U, // t2UXTAH 9074927U, // t2UXTB 554738U, // t2UXTB16 9075322U, // t2UXTH 982776121U, // tADC 555382U, // tADDhirr 177469814U, // tADDi3 982776182U, // tADDi8 555382U, // tADDrSP 555382U, // tADDrSPi 177469814U, // tADDrr 555382U, // tADDspi 555382U, // tADDspr 539726U, // tADR 982776235U, // tAND 177470588U, // tASRri 982776956U, // tASRrr 1074313296U, // tB 982776134U, // tBIC 828725U, // tBKPT 1242090220U, // tBL 1242090708U, // tBLXNSr 1242091172U, // tBLXi 1242091172U, // tBLXr 1074314816U, // tBX 1074314447U, // tBXNS 1074313296U, // tBcc 1258988910U, // tCBNZ 1258988905U, // tCBZ 539583U, // tCMNz 539683U, // tCMPhir 539683U, // tCMPi8 539683U, // tCMPr 1308687581U, // tCPS 982776938U, // tEOR 1074314610U, // tHINT 828720U, // tHLT 0U, // tInt_WIN_eh_sjlj_longjmp 0U, // tInt_eh_sjlj_longjmp 0U, // tInt_eh_sjlj_setjmp 572300U, // tLDMIA 555180U, // tLDRBi 555180U, // tLDRBr 555601U, // tLDRHi 555601U, // tLDRHr 555198U, // tLDRSB 555620U, // tLDRSH 556115U, // tLDRi 539731U, // tLDRpci 556115U, // tLDRr 556115U, // tLDRspi 177470309U, // tLSLri 982776677U, // tLSLrr 177470595U, // tLSRri 982776963U, // tLSRrr 1258988842U, // tMOVSr 446037482U, // tMOVi8 540138U, // tMOVr 177470325U, // tMUL 446036995U, // tMVN 982776952U, // tORR 0U, // tPICADD 990432295U, // tPOP 990431850U, // tPUSH 540118U, // tREV 538452U, // tREV16 539247U, // tREVSH 982776942U, // tROR 429258944U, // tRSB 982776117U, // tSBC 91368U, // tSETEND 2332572562U, // tSTMIA_UPD 555185U, // tSTRBi 555185U, // tSTRBr 555606U, // tSTRHi 555606U, // tSTRHr 556180U, // tSTRi 556180U, // tSTRr 556180U, // tSTRspi 177469686U, // tSUBi3 982776054U, // tSUBi8 177469686U, // tSUBrr 555254U, // tSUBspi 1074313567U, // tSVC 538858U, // tSXTB 539253U, // tSXTH 3092U, // tTRAP 540040U, // tTST 828656U, // tUDF 538863U, // tUXTB 539258U, // tUXTH 1636U, // t__brkdiv0 }; static const uint32_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // ABS 0U, // ADDSri 0U, // ADDSrr 0U, // ADDSrsi 0U, // ADDSrsr 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ASRi 0U, // ASRr 0U, // B 0U, // BCCZi64 0U, // BCCi64 0U, // BMOVPCB_CALL 0U, // BMOVPCRX_CALL 0U, // BR_JTadd 0U, // BR_JTm_i12 0U, // BR_JTm_rs 0U, // BR_JTr 0U, // BX_CALL 0U, // CMP_SWAP_16 0U, // CMP_SWAP_32 0U, // CMP_SWAP_64 0U, // CMP_SWAP_8 0U, // CONSTPOOL_ENTRY 0U, // COPY_STRUCT_BYVAL_I32 0U, // CompilerBarrier 0U, // ITasm 0U, // Int_eh_sjlj_dispatchsetup 0U, // Int_eh_sjlj_longjmp 0U, // Int_eh_sjlj_setjmp 0U, // Int_eh_sjlj_setjmp_nofp 0U, // Int_eh_sjlj_setup_dispatch 0U, // JUMPTABLE_ADDRS 0U, // JUMPTABLE_INSTS 0U, // JUMPTABLE_TBB 0U, // JUMPTABLE_TBH 0U, // LDMIA_RET 8U, // LDRBT_POST 1024U, // LDRConstPool 0U, // LDRLIT_ga_abs 0U, // LDRLIT_ga_pcrel 0U, // LDRLIT_ga_pcrel_ldr 8U, // LDRT_POST 0U, // LEApcrel 0U, // LEApcrelJT 0U, // LSLi 0U, // LSLr 0U, // LSRi 0U, // LSRr 0U, // MEMCPY 0U, // MLAv5 0U, // MOVCCi 0U, // MOVCCi16 0U, // MOVCCi32imm 0U, // MOVCCr 0U, // MOVCCsi 0U, // MOVCCsr 0U, // MOVPCRX 0U, // MOVTi16_ga_pcrel 0U, // MOV_ga_pcrel 0U, // MOV_ga_pcrel_ldr 0U, // MOVi16_ga_pcrel 0U, // MOVi32imm 0U, // MOVsra_flag 0U, // MOVsrl_flag 0U, // MULv5 0U, // MVNCCi 0U, // PICADD 0U, // PICLDR 0U, // PICLDRB 0U, // PICLDRH 0U, // PICLDRSB 0U, // PICLDRSH 0U, // PICSTR 0U, // PICSTRB 0U, // PICSTRH 0U, // RORi 0U, // RORr 0U, // RRX 1024U, // RRXi 0U, // RSBSri 0U, // RSBSrsi 0U, // RSBSrsr 0U, // SMLALv5 0U, // SMULLv5 0U, // SPACE 8U, // STRBT_POST 0U, // STRBi_preidx 0U, // STRBr_preidx 0U, // STRH_preidx 8U, // STRT_POST 0U, // STRi_preidx 0U, // STRr_preidx 0U, // SUBS_PC_LR 0U, // SUBSri 0U, // SUBSrr 0U, // SUBSrsi 0U, // SUBSrsr 0U, // TAILJMPd 0U, // TAILJMPr 0U, // TAILJMPr4 0U, // TCRETURNdi 0U, // TCRETURNri 0U, // TPsoft 0U, // UMLALv5 0U, // UMULLv5 1040U, // VLD1LNdAsm_16 1040U, // VLD1LNdAsm_32 1040U, // VLD1LNdAsm_8 2064U, // VLD1LNdWB_fixed_Asm_16 2064U, // VLD1LNdWB_fixed_Asm_32 2064U, // VLD1LNdWB_fixed_Asm_8 32784U, // VLD1LNdWB_register_Asm_16 32784U, // VLD1LNdWB_register_Asm_32 32784U, // VLD1LNdWB_register_Asm_8 1040U, // VLD2LNdAsm_16 1040U, // VLD2LNdAsm_32 1040U, // VLD2LNdAsm_8 2064U, // VLD2LNdWB_fixed_Asm_16 2064U, // VLD2LNdWB_fixed_Asm_32 2064U, // VLD2LNdWB_fixed_Asm_8 32784U, // VLD2LNdWB_register_Asm_16 32784U, // VLD2LNdWB_register_Asm_32 32784U, // VLD2LNdWB_register_Asm_8 1040U, // VLD2LNqAsm_16 1040U, // VLD2LNqAsm_32 2064U, // VLD2LNqWB_fixed_Asm_16 2064U, // VLD2LNqWB_fixed_Asm_32 32784U, // VLD2LNqWB_register_Asm_16 32784U, // VLD2LNqWB_register_Asm_32 0U, // VLD3DUPdAsm_16 0U, // VLD3DUPdAsm_32 0U, // VLD3DUPdAsm_8 0U, // VLD3DUPdWB_fixed_Asm_16 0U, // VLD3DUPdWB_fixed_Asm_32 0U, // VLD3DUPdWB_fixed_Asm_8 1048U, // VLD3DUPdWB_register_Asm_16 1048U, // VLD3DUPdWB_register_Asm_32 1048U, // VLD3DUPdWB_register_Asm_8 0U, // VLD3DUPqAsm_16 0U, // VLD3DUPqAsm_32 0U, // VLD3DUPqAsm_8 0U, // VLD3DUPqWB_fixed_Asm_16 0U, // VLD3DUPqWB_fixed_Asm_32 0U, // VLD3DUPqWB_fixed_Asm_8 1048U, // VLD3DUPqWB_register_Asm_16 1048U, // VLD3DUPqWB_register_Asm_32 1048U, // VLD3DUPqWB_register_Asm_8 1040U, // VLD3LNdAsm_16 1040U, // VLD3LNdAsm_32 1040U, // VLD3LNdAsm_8 2064U, // VLD3LNdWB_fixed_Asm_16 2064U, // VLD3LNdWB_fixed_Asm_32 2064U, // VLD3LNdWB_fixed_Asm_8 32784U, // VLD3LNdWB_register_Asm_16 32784U, // VLD3LNdWB_register_Asm_32 32784U, // VLD3LNdWB_register_Asm_8 1040U, // VLD3LNqAsm_16 1040U, // VLD3LNqAsm_32 2064U, // VLD3LNqWB_fixed_Asm_16 2064U, // VLD3LNqWB_fixed_Asm_32 32784U, // VLD3LNqWB_register_Asm_16 32784U, // VLD3LNqWB_register_Asm_32 32U, // VLD3dAsm_16 32U, // VLD3dAsm_32 32U, // VLD3dAsm_8 40U, // VLD3dWB_fixed_Asm_16 40U, // VLD3dWB_fixed_Asm_32 40U, // VLD3dWB_fixed_Asm_8 68656U, // VLD3dWB_register_Asm_16 68656U, // VLD3dWB_register_Asm_32 68656U, // VLD3dWB_register_Asm_8 0U, // VLD3qAsm_16 0U, // VLD3qAsm_32 0U, // VLD3qAsm_8 0U, // VLD3qWB_fixed_Asm_16 0U, // VLD3qWB_fixed_Asm_32 0U, // VLD3qWB_fixed_Asm_8 1048U, // VLD3qWB_register_Asm_16 1048U, // VLD3qWB_register_Asm_32 1048U, // VLD3qWB_register_Asm_8 0U, // VLD4DUPdAsm_16 0U, // VLD4DUPdAsm_32 0U, // VLD4DUPdAsm_8 0U, // VLD4DUPdWB_fixed_Asm_16 0U, // VLD4DUPdWB_fixed_Asm_32 0U, // VLD4DUPdWB_fixed_Asm_8 1048U, // VLD4DUPdWB_register_Asm_16 1048U, // VLD4DUPdWB_register_Asm_32 1048U, // VLD4DUPdWB_register_Asm_8 0U, // VLD4DUPqAsm_16 0U, // VLD4DUPqAsm_32 0U, // VLD4DUPqAsm_8 0U, // VLD4DUPqWB_fixed_Asm_16 0U, // VLD4DUPqWB_fixed_Asm_32 0U, // VLD4DUPqWB_fixed_Asm_8 1048U, // VLD4DUPqWB_register_Asm_16 1048U, // VLD4DUPqWB_register_Asm_32 1048U, // VLD4DUPqWB_register_Asm_8 1040U, // VLD4LNdAsm_16 1040U, // VLD4LNdAsm_32 1040U, // VLD4LNdAsm_8 2064U, // VLD4LNdWB_fixed_Asm_16 2064U, // VLD4LNdWB_fixed_Asm_32 2064U, // VLD4LNdWB_fixed_Asm_8 32784U, // VLD4LNdWB_register_Asm_16 32784U, // VLD4LNdWB_register_Asm_32 32784U, // VLD4LNdWB_register_Asm_8 1040U, // VLD4LNqAsm_16 1040U, // VLD4LNqAsm_32 2064U, // VLD4LNqWB_fixed_Asm_16 2064U, // VLD4LNqWB_fixed_Asm_32 32784U, // VLD4LNqWB_register_Asm_16 32784U, // VLD4LNqWB_register_Asm_32 32U, // VLD4dAsm_16 32U, // VLD4dAsm_32 32U, // VLD4dAsm_8 40U, // VLD4dWB_fixed_Asm_16 40U, // VLD4dWB_fixed_Asm_32 40U, // VLD4dWB_fixed_Asm_8 68656U, // VLD4dWB_register_Asm_16 68656U, // VLD4dWB_register_Asm_32 68656U, // VLD4dWB_register_Asm_8 0U, // VLD4qAsm_16 0U, // VLD4qAsm_32 0U, // VLD4qAsm_8 0U, // VLD4qWB_fixed_Asm_16 0U, // VLD4qWB_fixed_Asm_32 0U, // VLD4qWB_fixed_Asm_8 1048U, // VLD4qWB_register_Asm_16 1048U, // VLD4qWB_register_Asm_32 1048U, // VLD4qWB_register_Asm_8 0U, // VMOVD0 0U, // VMOVDcc 0U, // VMOVQ0 0U, // VMOVScc 1040U, // VST1LNdAsm_16 1040U, // VST1LNdAsm_32 1040U, // VST1LNdAsm_8 2064U, // VST1LNdWB_fixed_Asm_16 2064U, // VST1LNdWB_fixed_Asm_32 2064U, // VST1LNdWB_fixed_Asm_8 32784U, // VST1LNdWB_register_Asm_16 32784U, // VST1LNdWB_register_Asm_32 32784U, // VST1LNdWB_register_Asm_8 1040U, // VST2LNdAsm_16 1040U, // VST2LNdAsm_32 1040U, // VST2LNdAsm_8 2064U, // VST2LNdWB_fixed_Asm_16 2064U, // VST2LNdWB_fixed_Asm_32 2064U, // VST2LNdWB_fixed_Asm_8 32784U, // VST2LNdWB_register_Asm_16 32784U, // VST2LNdWB_register_Asm_32 32784U, // VST2LNdWB_register_Asm_8 1040U, // VST2LNqAsm_16 1040U, // VST2LNqAsm_32 2064U, // VST2LNqWB_fixed_Asm_16 2064U, // VST2LNqWB_fixed_Asm_32 32784U, // VST2LNqWB_register_Asm_16 32784U, // VST2LNqWB_register_Asm_32 1040U, // VST3LNdAsm_16 1040U, // VST3LNdAsm_32 1040U, // VST3LNdAsm_8 2064U, // VST3LNdWB_fixed_Asm_16 2064U, // VST3LNdWB_fixed_Asm_32 2064U, // VST3LNdWB_fixed_Asm_8 32784U, // VST3LNdWB_register_Asm_16 32784U, // VST3LNdWB_register_Asm_32 32784U, // VST3LNdWB_register_Asm_8 1040U, // VST3LNqAsm_16 1040U, // VST3LNqAsm_32 2064U, // VST3LNqWB_fixed_Asm_16 2064U, // VST3LNqWB_fixed_Asm_32 32784U, // VST3LNqWB_register_Asm_16 32784U, // VST3LNqWB_register_Asm_32 32U, // VST3dAsm_16 32U, // VST3dAsm_32 32U, // VST3dAsm_8 40U, // VST3dWB_fixed_Asm_16 40U, // VST3dWB_fixed_Asm_32 40U, // VST3dWB_fixed_Asm_8 68656U, // VST3dWB_register_Asm_16 68656U, // VST3dWB_register_Asm_32 68656U, // VST3dWB_register_Asm_8 0U, // VST3qAsm_16 0U, // VST3qAsm_32 0U, // VST3qAsm_8 0U, // VST3qWB_fixed_Asm_16 0U, // VST3qWB_fixed_Asm_32 0U, // VST3qWB_fixed_Asm_8 1048U, // VST3qWB_register_Asm_16 1048U, // VST3qWB_register_Asm_32 1048U, // VST3qWB_register_Asm_8 1040U, // VST4LNdAsm_16 1040U, // VST4LNdAsm_32 1040U, // VST4LNdAsm_8 2064U, // VST4LNdWB_fixed_Asm_16 2064U, // VST4LNdWB_fixed_Asm_32 2064U, // VST4LNdWB_fixed_Asm_8 32784U, // VST4LNdWB_register_Asm_16 32784U, // VST4LNdWB_register_Asm_32 32784U, // VST4LNdWB_register_Asm_8 1040U, // VST4LNqAsm_16 1040U, // VST4LNqAsm_32 2064U, // VST4LNqWB_fixed_Asm_16 2064U, // VST4LNqWB_fixed_Asm_32 32784U, // VST4LNqWB_register_Asm_16 32784U, // VST4LNqWB_register_Asm_32 32U, // VST4dAsm_16 32U, // VST4dAsm_32 32U, // VST4dAsm_8 40U, // VST4dWB_fixed_Asm_16 40U, // VST4dWB_fixed_Asm_32 40U, // VST4dWB_fixed_Asm_8 68656U, // VST4dWB_register_Asm_16 68656U, // VST4dWB_register_Asm_32 68656U, // VST4dWB_register_Asm_8 0U, // VST4qAsm_16 0U, // VST4qAsm_32 0U, // VST4qAsm_8 0U, // VST4qWB_fixed_Asm_16 0U, // VST4qWB_fixed_Asm_32 0U, // VST4qWB_fixed_Asm_8 1048U, // VST4qWB_register_Asm_16 1048U, // VST4qWB_register_Asm_32 1048U, // VST4qWB_register_Asm_8 0U, // WIN__CHKSTK 0U, // WIN__DBZCHK 0U, // t2ABS 0U, // t2ADDSri 0U, // t2ADDSrr 0U, // t2ADDSrs 0U, // t2BR_JT 0U, // t2LDMIA_RET 1024U, // t2LDRBpcrel 1024U, // t2LDRConstPool 1024U, // t2LDRHpcrel 1024U, // t2LDRSBpcrel 1024U, // t2LDRSHpcrel 0U, // t2LDRpci_pic 1024U, // t2LDRpcrel 0U, // t2LEApcrel 0U, // t2LEApcrelJT 0U, // t2MOVCCasr 0U, // t2MOVCCi 0U, // t2MOVCCi16 0U, // t2MOVCCi32imm 0U, // t2MOVCClsl 0U, // t2MOVCClsr 0U, // t2MOVCCr 0U, // t2MOVCCror 56U, // t2MOVSsi 64U, // t2MOVSsr 0U, // t2MOVTi16_ga_pcrel 0U, // t2MOV_ga_pcrel 0U, // t2MOVi16_ga_pcrel 0U, // t2MOVi32imm 56U, // t2MOVsi 64U, // t2MOVsr 0U, // t2MVNCCi 0U, // t2RSBSri 0U, // t2RSBSrs 0U, // t2STRB_preidx 0U, // t2STRH_preidx 0U, // t2STR_preidx 0U, // t2SUBSri 0U, // t2SUBSrr 0U, // t2SUBSrs 0U, // t2TBB_JT 0U, // t2TBH_JT 0U, // tADCS 0U, // tADDSi3 0U, // tADDSi8 0U, // tADDSrr 0U, // tADDframe 0U, // tADJCALLSTACKDOWN 0U, // tADJCALLSTACKUP 0U, // tBRIND 0U, // tBR_JTr 0U, // tBX_CALL 0U, // tBX_RET 0U, // tBX_RET_vararg 0U, // tBfar 0U, // tLDMIA_UPD 1024U, // tLDRConstPool 0U, // tLDRLIT_ga_abs 0U, // tLDRLIT_ga_pcrel 0U, // tLDR_postidx 0U, // tLDRpci_pic 0U, // tLEApcrel 0U, // tLEApcrelJT 0U, // tMOVCCr_pseudo 0U, // tPOP_RET 0U, // tSBCS 0U, // tSUBSi3 0U, // tSUBSi8 0U, // tSUBSrr 0U, // tTAILJMPd 0U, // tTAILJMPdND 0U, // tTAILJMPr 0U, // tTBB_JT 0U, // tTBH_JT 0U, // tTPsoft 98304U, // ADCri 0U, // ADCrr 131072U, // ADCrsi 0U, // ADCrsr 98304U, // ADDri 0U, // ADDrr 131072U, // ADDrsi 0U, // ADDrsr 72U, // ADR 0U, // AESD 0U, // AESE 0U, // AESIMC 0U, // AESMC 98304U, // ANDri 0U, // ANDrr 131072U, // ANDrsi 0U, // ANDrsr 80U, // BFC 163928U, // BFI 98304U, // BICri 0U, // BICrr 131072U, // BICrsi 0U, // BICrsr 0U, // BKPT 0U, // BL 0U, // BLX 0U, // BLX_pred 0U, // BLXi 0U, // BL_pred 0U, // BX 0U, // BXJ 0U, // BX_RET 0U, // BX_pred 0U, // Bcc 4145U, // CDP 0U, // CDP2 0U, // CLREX 1024U, // CLZ 96U, // CMNri 1024U, // CMNzrr 104U, // CMNzrsi 64U, // CMNzrsr 96U, // CMPri 1024U, // CMPrr 104U, // CMPrsi 64U, // CMPrsr 0U, // CPS1p 0U, // CPS2p 1112U, // CPS3p 1112U, // CRC32B 1112U, // CRC32CB 1112U, // CRC32CH 1112U, // CRC32CW 1112U, // CRC32H 1112U, // CRC32W 0U, // DBG 0U, // DMB 0U, // DSB 98304U, // EORri 0U, // EORrr 131072U, // EORrsi 0U, // EORrsr 0U, // ERET 1U, // FCONSTD 1U, // FCONSTH 1U, // FCONSTS 33U, // FLDMXDB_UPD 1136U, // FLDMXIA 33U, // FLDMXIA_UPD 0U, // FMSTAT 33U, // FSTMXDB_UPD 1136U, // FSTMXIA 33U, // FSTMXIA_UPD 0U, // HINT 0U, // HLT 0U, // HVC 0U, // ISB 8U, // LDA 8U, // LDAB 8U, // LDAEX 8U, // LDAEXB 0U, // LDAEXD 8U, // LDAEXH 8U, // LDAH 0U, // LDC2L_OFFSET 1U, // LDC2L_OPTION 2U, // LDC2L_POST 0U, // LDC2L_PRE 0U, // LDC2_OFFSET 1U, // LDC2_OPTION 2U, // LDC2_POST 0U, // LDC2_PRE 122U, // LDCL_OFFSET 196738U, // LDCL_OPTION 229506U, // LDCL_POST 138U, // LDCL_PRE 122U, // LDC_OFFSET 196738U, // LDC_OPTION 229506U, // LDC_POST 138U, // LDC_PRE 1136U, // LDMDA 33U, // LDMDA_UPD 1136U, // LDMDB 33U, // LDMDB_UPD 1136U, // LDMIA 33U, // LDMIA_UPD 1136U, // LDMIB 33U, // LDMIB_UPD 262272U, // LDRBT_POST_IMM 262272U, // LDRBT_POST_REG 262272U, // LDRB_POST_IMM 262272U, // LDRB_POST_REG 144U, // LDRB_PRE_IMM 152U, // LDRB_PRE_REG 160U, // LDRBi12 168U, // LDRBrs 294912U, // LDRD 2424832U, // LDRD_POST 360448U, // LDRD_PRE 8U, // LDREX 8U, // LDREXB 0U, // LDREXD 8U, // LDREXH 176U, // LDRH 393344U, // LDRHTi 426112U, // LDRHTr 458880U, // LDRH_POST 184U, // LDRH_PRE 176U, // LDRSB 393344U, // LDRSBTi 426112U, // LDRSBTr 458880U, // LDRSB_POST 184U, // LDRSB_PRE 176U, // LDRSH 393344U, // LDRSHTi 426112U, // LDRSHTr 458880U, // LDRSH_POST 184U, // LDRSH_PRE 262272U, // LDRT_POST_IMM 262272U, // LDRT_POST_REG 262272U, // LDR_POST_IMM 262272U, // LDR_POST_REG 144U, // LDR_PRE_IMM 152U, // LDR_PRE_REG 160U, // LDRcp 160U, // LDRi12 168U, // LDRrs 4690993U, // MCR 192U, // MCR2 6788145U, // MCRR 524312U, // MCRR2 35651584U, // MLA 35651584U, // MLS 0U, // MOVPCLR 1112U, // MOVTi16 96U, // MOVi 1024U, // MOVi16 1024U, // MOVr 1024U, // MOVr_TC 104U, // MOVsi 64U, // MOVsr 0U, // MRC 0U, // MRC2 0U, // MRRC 0U, // MRRC2 2U, // MRS 200U, // MRSbanked 2U, // MRSsys 33U, // MSR 0U, // MSRbanked 3U, // MSRi 0U, // MUL 96U, // MVNi 1024U, // MVNr 104U, // MVNsi 64U, // MVNsr 98304U, // ORRri 0U, // ORRrr 131072U, // ORRrsi 0U, // ORRrsr 8388608U, // PKHBT 10485760U, // PKHTB 0U, // PLDWi12 0U, // PLDWrs 0U, // PLDi12 0U, // PLDrs 0U, // PLIi12 0U, // PLIrs 0U, // QADD 0U, // QADD16 0U, // QADD8 0U, // QASX 0U, // QDADD 0U, // QDSUB 0U, // QSAX 0U, // QSUB 0U, // QSUB16 0U, // QSUB8 1024U, // RBIT 1024U, // REV 1024U, // REV16 1024U, // REVSH 0U, // RFEDA 0U, // RFEDA_UPD 0U, // RFEDB 0U, // RFEDB_UPD 0U, // RFEIA 0U, // RFEIA_UPD 0U, // RFEIB 0U, // RFEIB_UPD 98304U, // RSBri 0U, // RSBrr 131072U, // RSBrsi 0U, // RSBrsr 98304U, // RSCri 0U, // RSCrr 131072U, // RSCrsi 0U, // RSCrsr 0U, // SADD16 0U, // SADD8 0U, // SASX 98304U, // SBCri 0U, // SBCrr 131072U, // SBCrsi 0U, // SBCrsr 69206016U, // SBFX 0U, // SDIV 0U, // SEL 0U, // SETEND 0U, // SETPAN 1048U, // SHA1C 0U, // SHA1H 1048U, // SHA1M 1048U, // SHA1P 1048U, // SHA1SU0 0U, // SHA1SU1 1048U, // SHA256H 1048U, // SHA256H2 0U, // SHA256SU0 1048U, // SHA256SU1 0U, // SHADD16 0U, // SHADD8 0U, // SHASX 0U, // SHSAX 0U, // SHSUB16 0U, // SHSUB8 0U, // SMC 35651584U, // SMLABB 35651584U, // SMLABT 35651584U, // SMLAD 35651584U, // SMLADX 0U, // SMLAL 35651584U, // SMLALBB 35651584U, // SMLALBT 35651584U, // SMLALD 35651584U, // SMLALDX 35651584U, // SMLALTB 35651584U, // SMLALTT 35651584U, // SMLATB 35651584U, // SMLATT 35651584U, // SMLAWB 35651584U, // SMLAWT 35651584U, // SMLSD 35651584U, // SMLSDX 35651584U, // SMLSLD 35651584U, // SMLSLDX 35651584U, // SMMLA 35651584U, // SMMLAR 35651584U, // SMMLS 35651584U, // SMMLSR 0U, // SMMUL 0U, // SMMULR 0U, // SMUAD 0U, // SMUADX 0U, // SMULBB 0U, // SMULBT 35651584U, // SMULL 0U, // SMULTB 0U, // SMULTT 0U, // SMULWB 0U, // SMULWT 0U, // SMUSD 0U, // SMUSDX 0U, // SRSDA 0U, // SRSDA_UPD 0U, // SRSDB 0U, // SRSDB_UPD 0U, // SRSIA 0U, // SRSIA_UPD 0U, // SRSIB 0U, // SRSIB_UPD 6352U, // SSAT 1232U, // SSAT16 0U, // SSAX 0U, // SSUB16 0U, // SSUB8 0U, // STC2L_OFFSET 1U, // STC2L_OPTION 2U, // STC2L_POST 0U, // STC2L_PRE 0U, // STC2_OFFSET 1U, // STC2_OPTION 2U, // STC2_POST 0U, // STC2_PRE 122U, // STCL_OFFSET 196738U, // STCL_OPTION 229506U, // STCL_POST 138U, // STCL_PRE 122U, // STC_OFFSET 196738U, // STC_OPTION 229506U, // STC_POST 138U, // STC_PRE 8U, // STL 8U, // STLB 557056U, // STLEX 557056U, // STLEXB 216U, // STLEXD 557056U, // STLEXH 8U, // STLH 1136U, // STMDA 33U, // STMDA_UPD 1136U, // STMDB 33U, // STMDB_UPD 1136U, // STMIA 33U, // STMIA_UPD 1136U, // STMIB 33U, // STMIB_UPD 262272U, // STRBT_POST_IMM 262272U, // STRBT_POST_REG 262272U, // STRB_POST_IMM 262272U, // STRB_POST_REG 144U, // STRB_PRE_IMM 152U, // STRB_PRE_REG 160U, // STRBi12 168U, // STRBrs 294912U, // STRD 2424920U, // STRD_POST 360536U, // STRD_PRE 557056U, // STREX 557056U, // STREXB 216U, // STREXD 557056U, // STREXH 176U, // STRH 393344U, // STRHTi 426112U, // STRHTr 458880U, // STRH_POST 184U, // STRH_PRE 262272U, // STRT_POST_IMM 262272U, // STRT_POST_REG 262272U, // STR_POST_IMM 262272U, // STR_POST_REG 144U, // STR_PRE_IMM 152U, // STR_PRE_REG 160U, // STRi12 168U, // STRrs 98304U, // SUBri 0U, // SUBrr 131072U, // SUBrsi 0U, // SUBrsr 0U, // SVC 557056U, // SWP 557056U, // SWPB 12582912U, // SXTAB 12582912U, // SXTAB16 12582912U, // SXTAH 7168U, // SXTB 7168U, // SXTB16 7168U, // SXTH 96U, // TEQri 1024U, // TEQrr 104U, // TEQrsi 64U, // TEQrsr 0U, // TRAP 0U, // TRAPNaCl 0U, // TSB 96U, // TSTri 1024U, // TSTrr 104U, // TSTrsi 64U, // TSTrsr 0U, // UADD16 0U, // UADD8 0U, // UASX 69206016U, // UBFX 0U, // UDF 0U, // UDIV 0U, // UHADD16 0U, // UHADD8 0U, // UHASX 0U, // UHSAX 0U, // UHSUB16 0U, // UHSUB8 35651584U, // UMAAL 0U, // UMLAL 35651584U, // UMULL 0U, // UQADD16 0U, // UQADD8 0U, // UQASX 0U, // UQSAX 0U, // UQSUB16 0U, // UQSUB8 0U, // USAD8 35651584U, // USADA8 14680064U, // USAT 0U, // USAT16 0U, // USAX 0U, // USUB16 0U, // USUB8 12582912U, // UXTAB 12582912U, // UXTAB16 12582912U, // UXTAH 7168U, // UXTB 7168U, // UXTB16 7168U, // UXTH 1048U, // VABALsv2i64 1048U, // VABALsv4i32 1048U, // VABALsv8i16 1048U, // VABALuv2i64 1048U, // VABALuv4i32 1048U, // VABALuv8i16 1048U, // VABAsv16i8 1048U, // VABAsv2i32 1048U, // VABAsv4i16 1048U, // VABAsv4i32 1048U, // VABAsv8i16 1048U, // VABAsv8i8 1048U, // VABAuv16i8 1048U, // VABAuv2i32 1048U, // VABAuv4i16 1048U, // VABAuv4i32 1048U, // VABAuv8i16 1048U, // VABAuv8i8 1112U, // VABDLsv2i64 1112U, // VABDLsv4i32 1112U, // VABDLsv8i16 1112U, // VABDLuv2i64 1112U, // VABDLuv4i32 1112U, // VABDLuv8i16 70705U, // VABDfd 70705U, // VABDfq 70705U, // VABDhd 70705U, // VABDhq 1112U, // VABDsv16i8 1112U, // VABDsv2i32 1112U, // VABDsv4i16 1112U, // VABDsv4i32 1112U, // VABDsv8i16 1112U, // VABDsv8i8 1112U, // VABDuv16i8 1112U, // VABDuv2i32 1112U, // VABDuv4i16 1112U, // VABDuv4i32 1112U, // VABDuv8i16 1112U, // VABDuv8i8 33U, // VABSD 33U, // VABSH 33U, // VABSS 33U, // VABSfd 33U, // VABSfq 33U, // VABShd 33U, // VABShq 0U, // VABSv16i8 0U, // VABSv2i32 0U, // VABSv4i16 0U, // VABSv4i32 0U, // VABSv8i16 0U, // VABSv8i8 70705U, // VACGEfd 70705U, // VACGEfq 70705U, // VACGEhd 70705U, // VACGEhq 70705U, // VACGTfd 70705U, // VACGTfq 70705U, // VACGThd 70705U, // VACGThq 70705U, // VADDD 70705U, // VADDH 1112U, // VADDHNv2i32 1112U, // VADDHNv4i16 1112U, // VADDHNv8i8 1112U, // VADDLsv2i64 1112U, // VADDLsv4i32 1112U, // VADDLsv8i16 1112U, // VADDLuv2i64 1112U, // VADDLuv4i32 1112U, // VADDLuv8i16 70705U, // VADDS 1112U, // VADDWsv2i64 1112U, // VADDWsv4i32 1112U, // VADDWsv8i16 1112U, // VADDWuv2i64 1112U, // VADDWuv4i32 1112U, // VADDWuv8i16 70705U, // VADDfd 70705U, // VADDfq 70705U, // VADDhd 70705U, // VADDhq 1112U, // VADDv16i8 1112U, // VADDv1i64 1112U, // VADDv2i32 1112U, // VADDv2i64 1112U, // VADDv4i16 1112U, // VADDv4i32 1112U, // VADDv8i16 1112U, // VADDv8i8 0U, // VANDd 0U, // VANDq 0U, // VBICd 0U, // VBICiv2i32 0U, // VBICiv4i16 0U, // VBICiv4i32 0U, // VBICiv8i16 0U, // VBICq 589912U, // VBIFd 589912U, // VBIFq 589912U, // VBITd 589912U, // VBITq 589912U, // VBSLd 589912U, // VBSLq 622680U, // VCADDv2f32 622680U, // VCADDv4f16 622680U, // VCADDv4f32 622680U, // VCADDv8f16 70705U, // VCEQfd 70705U, // VCEQfq 70705U, // VCEQhd 70705U, // VCEQhq 1112U, // VCEQv16i8 1112U, // VCEQv2i32 1112U, // VCEQv4i16 1112U, // VCEQv4i32 1112U, // VCEQv8i16 1112U, // VCEQv8i8 3U, // VCEQzv16i8 225U, // VCEQzv2f32 3U, // VCEQzv2i32 225U, // VCEQzv4f16 225U, // VCEQzv4f32 3U, // VCEQzv4i16 3U, // VCEQzv4i32 225U, // VCEQzv8f16 3U, // VCEQzv8i16 3U, // VCEQzv8i8 70705U, // VCGEfd 70705U, // VCGEfq 70705U, // VCGEhd 70705U, // VCGEhq 1112U, // VCGEsv16i8 1112U, // VCGEsv2i32 1112U, // VCGEsv4i16 1112U, // VCGEsv4i32 1112U, // VCGEsv8i16 1112U, // VCGEsv8i8 1112U, // VCGEuv16i8 1112U, // VCGEuv2i32 1112U, // VCGEuv4i16 1112U, // VCGEuv4i32 1112U, // VCGEuv8i16 1112U, // VCGEuv8i8 3U, // VCGEzv16i8 225U, // VCGEzv2f32 3U, // VCGEzv2i32 225U, // VCGEzv4f16 225U, // VCGEzv4f32 3U, // VCGEzv4i16 3U, // VCGEzv4i32 225U, // VCGEzv8f16 3U, // VCGEzv8i16 3U, // VCGEzv8i8 70705U, // VCGTfd 70705U, // VCGTfq 70705U, // VCGThd 70705U, // VCGThq 1112U, // VCGTsv16i8 1112U, // VCGTsv2i32 1112U, // VCGTsv4i16 1112U, // VCGTsv4i32 1112U, // VCGTsv8i16 1112U, // VCGTsv8i8 1112U, // VCGTuv16i8 1112U, // VCGTuv2i32 1112U, // VCGTuv4i16 1112U, // VCGTuv4i32 1112U, // VCGTuv8i16 1112U, // VCGTuv8i8 3U, // VCGTzv16i8 225U, // VCGTzv2f32 3U, // VCGTzv2i32 225U, // VCGTzv4f16 225U, // VCGTzv4f32 3U, // VCGTzv4i16 3U, // VCGTzv4i32 225U, // VCGTzv8f16 3U, // VCGTzv8i16 3U, // VCGTzv8i8 3U, // VCLEzv16i8 225U, // VCLEzv2f32 3U, // VCLEzv2i32 225U, // VCLEzv4f16 225U, // VCLEzv4f32 3U, // VCLEzv4i16 3U, // VCLEzv4i32 225U, // VCLEzv8f16 3U, // VCLEzv8i16 3U, // VCLEzv8i8 0U, // VCLSv16i8 0U, // VCLSv2i32 0U, // VCLSv4i16 0U, // VCLSv4i32 0U, // VCLSv8i16 0U, // VCLSv8i8 3U, // VCLTzv16i8 225U, // VCLTzv2f32 3U, // VCLTzv2i32 225U, // VCLTzv4f16 225U, // VCLTzv4f32 3U, // VCLTzv4i16 3U, // VCLTzv4i32 225U, // VCLTzv8f16 3U, // VCLTzv8i16 3U, // VCLTzv8i8 0U, // VCLZv16i8 0U, // VCLZv2i32 0U, // VCLZv4i16 0U, // VCLZv4i32 0U, // VCLZv8i16 0U, // VCLZv8i8 655384U, // VCMLAv2f32 17276952U, // VCMLAv2f32_indexed 655384U, // VCMLAv4f16 17276952U, // VCMLAv4f16_indexed 655384U, // VCMLAv4f32 17276952U, // VCMLAv4f32_indexed 655384U, // VCMLAv8f16 17276952U, // VCMLAv8f16_indexed 33U, // VCMPD 33U, // VCMPED 33U, // VCMPEH 33U, // VCMPES 0U, // VCMPEZD 0U, // VCMPEZH 0U, // VCMPEZS 33U, // VCMPH 33U, // VCMPS 0U, // VCMPZD 0U, // VCMPZH 0U, // VCMPZS 1024U, // VCNTd 1024U, // VCNTq 0U, // VCVTANSDf 0U, // VCVTANSDh 0U, // VCVTANSQf 0U, // VCVTANSQh 0U, // VCVTANUDf 0U, // VCVTANUDh 0U, // VCVTANUQf 0U, // VCVTANUQh 0U, // VCVTASD 0U, // VCVTASH 0U, // VCVTASS 0U, // VCVTAUD 0U, // VCVTAUH 0U, // VCVTAUS 0U, // VCVTBDH 0U, // VCVTBHD 0U, // VCVTBHS 0U, // VCVTBSH 0U, // VCVTDS 0U, // VCVTMNSDf 0U, // VCVTMNSDh 0U, // VCVTMNSQf 0U, // VCVTMNSQh 0U, // VCVTMNUDf 0U, // VCVTMNUDh 0U, // VCVTMNUQf 0U, // VCVTMNUQh 0U, // VCVTMSD 0U, // VCVTMSH 0U, // VCVTMSS 0U, // VCVTMUD 0U, // VCVTMUH 0U, // VCVTMUS 0U, // VCVTNNSDf 0U, // VCVTNNSDh 0U, // VCVTNNSQf 0U, // VCVTNNSQh 0U, // VCVTNNUDf 0U, // VCVTNNUDh 0U, // VCVTNNUQf 0U, // VCVTNNUQh 0U, // VCVTNSD 0U, // VCVTNSH 0U, // VCVTNSS 0U, // VCVTNUD 0U, // VCVTNUH 0U, // VCVTNUS 0U, // VCVTPNSDf 0U, // VCVTPNSDh 0U, // VCVTPNSQf 0U, // VCVTPNSQh 0U, // VCVTPNUDf 0U, // VCVTPNUDh 0U, // VCVTPNUQf 0U, // VCVTPNUQh 0U, // VCVTPSD 0U, // VCVTPSH 0U, // VCVTPSS 0U, // VCVTPUD 0U, // VCVTPUH 0U, // VCVTPUS 0U, // VCVTSD 0U, // VCVTTDH 0U, // VCVTTHD 0U, // VCVTTHS 0U, // VCVTTSH 0U, // VCVTf2h 0U, // VCVTf2sd 0U, // VCVTf2sq 0U, // VCVTf2ud 0U, // VCVTf2uq 35U, // VCVTf2xsd 35U, // VCVTf2xsq 35U, // VCVTf2xud 35U, // VCVTf2xuq 0U, // VCVTh2f 0U, // VCVTh2sd 0U, // VCVTh2sq 0U, // VCVTh2ud 0U, // VCVTh2uq 35U, // VCVTh2xsd 35U, // VCVTh2xsq 35U, // VCVTh2xud 35U, // VCVTh2xuq 0U, // VCVTs2fd 0U, // VCVTs2fq 0U, // VCVTs2hd 0U, // VCVTs2hq 0U, // VCVTu2fd 0U, // VCVTu2fq 0U, // VCVTu2hd 0U, // VCVTu2hq 35U, // VCVTxs2fd 35U, // VCVTxs2fq 35U, // VCVTxs2hd 35U, // VCVTxs2hq 35U, // VCVTxu2fd 35U, // VCVTxu2fq 35U, // VCVTxu2hd 35U, // VCVTxu2hq 70705U, // VDIVD 70705U, // VDIVH 70705U, // VDIVS 1024U, // VDUP16d 1024U, // VDUP16q 1024U, // VDUP32d 1024U, // VDUP32q 1024U, // VDUP8d 1024U, // VDUP8q 9216U, // VDUPLN16d 9216U, // VDUPLN16q 9216U, // VDUPLN32d 9216U, // VDUPLN32q 9216U, // VDUPLN8d 9216U, // VDUPLN8q 0U, // VEORd 0U, // VEORq 35651584U, // VEXTd16 35651584U, // VEXTd32 35651584U, // VEXTd8 35651584U, // VEXTq16 35651584U, // VEXTq32 35651584U, // VEXTq64 35651584U, // VEXTq8 68659U, // VFMAD 68659U, // VFMAH 68659U, // VFMAS 68659U, // VFMAfd 68659U, // VFMAfq 68659U, // VFMAhd 68659U, // VFMAhq 68659U, // VFMSD 68659U, // VFMSH 68659U, // VFMSS 68659U, // VFMSfd 68659U, // VFMSfq 68659U, // VFMShd 68659U, // VFMShq 68659U, // VFNMAD 68659U, // VFNMAH 68659U, // VFNMAS 68659U, // VFNMSD 68659U, // VFNMSH 68659U, // VFNMSS 9216U, // VGETLNi32 3U, // VGETLNs16 3U, // VGETLNs8 3U, // VGETLNu16 3U, // VGETLNu8 1112U, // VHADDsv16i8 1112U, // VHADDsv2i32 1112U, // VHADDsv4i16 1112U, // VHADDsv4i32 1112U, // VHADDsv8i16 1112U, // VHADDsv8i8 1112U, // VHADDuv16i8 1112U, // VHADDuv2i32 1112U, // VHADDuv4i16 1112U, // VHADDuv4i32 1112U, // VHADDuv8i16 1112U, // VHADDuv8i8 1112U, // VHSUBsv16i8 1112U, // VHSUBsv2i32 1112U, // VHSUBsv4i16 1112U, // VHSUBsv4i32 1112U, // VHSUBsv8i16 1112U, // VHSUBsv8i8 1112U, // VHSUBuv16i8 1112U, // VHSUBuv2i32 1112U, // VHSUBuv4i16 1112U, // VHSUBuv4i32 1112U, // VHSUBuv8i16 1112U, // VHSUBuv8i8 0U, // VINSH 0U, // VJCVT 32U, // VLD1DUPd16 44U, // VLD1DUPd16wb_fixed 10292U, // VLD1DUPd16wb_register 32U, // VLD1DUPd32 44U, // VLD1DUPd32wb_fixed 10292U, // VLD1DUPd32wb_register 32U, // VLD1DUPd8 44U, // VLD1DUPd8wb_fixed 10292U, // VLD1DUPd8wb_register 32U, // VLD1DUPq16 44U, // VLD1DUPq16wb_fixed 10292U, // VLD1DUPq16wb_register 32U, // VLD1DUPq32 44U, // VLD1DUPq32wb_fixed 10292U, // VLD1DUPq32wb_register 32U, // VLD1DUPq8 44U, // VLD1DUPq8wb_fixed 10292U, // VLD1DUPq8wb_register 699628U, // VLD1LNd16 732404U, // VLD1LNd16_UPD 699628U, // VLD1LNd32 732404U, // VLD1LNd32_UPD 699628U, // VLD1LNd8 732404U, // VLD1LNd8_UPD 0U, // VLD1LNq16Pseudo 0U, // VLD1LNq16Pseudo_UPD 0U, // VLD1LNq32Pseudo 0U, // VLD1LNq32Pseudo_UPD 0U, // VLD1LNq8Pseudo 0U, // VLD1LNq8Pseudo_UPD 32U, // VLD1d16 32U, // VLD1d16Q 0U, // VLD1d16QPseudo 44U, // VLD1d16Qwb_fixed 10292U, // VLD1d16Qwb_register 32U, // VLD1d16T 0U, // VLD1d16TPseudo 44U, // VLD1d16Twb_fixed 10292U, // VLD1d16Twb_register 44U, // VLD1d16wb_fixed 10292U, // VLD1d16wb_register 32U, // VLD1d32 32U, // VLD1d32Q 0U, // VLD1d32QPseudo 44U, // VLD1d32Qwb_fixed 10292U, // VLD1d32Qwb_register 32U, // VLD1d32T 0U, // VLD1d32TPseudo 44U, // VLD1d32Twb_fixed 10292U, // VLD1d32Twb_register 44U, // VLD1d32wb_fixed 10292U, // VLD1d32wb_register 32U, // VLD1d64 32U, // VLD1d64Q 0U, // VLD1d64QPseudo 0U, // VLD1d64QPseudoWB_fixed 0U, // VLD1d64QPseudoWB_register 44U, // VLD1d64Qwb_fixed 10292U, // VLD1d64Qwb_register 32U, // VLD1d64T 0U, // VLD1d64TPseudo 0U, // VLD1d64TPseudoWB_fixed 0U, // VLD1d64TPseudoWB_register 44U, // VLD1d64Twb_fixed 10292U, // VLD1d64Twb_register 44U, // VLD1d64wb_fixed 10292U, // VLD1d64wb_register 32U, // VLD1d8 32U, // VLD1d8Q 0U, // VLD1d8QPseudo 44U, // VLD1d8Qwb_fixed 10292U, // VLD1d8Qwb_register 32U, // VLD1d8T 0U, // VLD1d8TPseudo 44U, // VLD1d8Twb_fixed 10292U, // VLD1d8Twb_register 44U, // VLD1d8wb_fixed 10292U, // VLD1d8wb_register 32U, // VLD1q16 0U, // VLD1q16HighQPseudo 0U, // VLD1q16HighTPseudo 0U, // VLD1q16LowQPseudo_UPD 0U, // VLD1q16LowTPseudo_UPD 44U, // VLD1q16wb_fixed 10292U, // VLD1q16wb_register 32U, // VLD1q32 0U, // VLD1q32HighQPseudo 0U, // VLD1q32HighTPseudo 0U, // VLD1q32LowQPseudo_UPD 0U, // VLD1q32LowTPseudo_UPD 44U, // VLD1q32wb_fixed 10292U, // VLD1q32wb_register 32U, // VLD1q64 0U, // VLD1q64HighQPseudo 0U, // VLD1q64HighTPseudo 0U, // VLD1q64LowQPseudo_UPD 0U, // VLD1q64LowTPseudo_UPD 44U, // VLD1q64wb_fixed 10292U, // VLD1q64wb_register 32U, // VLD1q8 0U, // VLD1q8HighQPseudo 0U, // VLD1q8HighTPseudo 0U, // VLD1q8LowQPseudo_UPD 0U, // VLD1q8LowTPseudo_UPD 44U, // VLD1q8wb_fixed 10292U, // VLD1q8wb_register 32U, // VLD2DUPd16 44U, // VLD2DUPd16wb_fixed 10292U, // VLD2DUPd16wb_register 32U, // VLD2DUPd16x2 44U, // VLD2DUPd16x2wb_fixed 10292U, // VLD2DUPd16x2wb_register 32U, // VLD2DUPd32 44U, // VLD2DUPd32wb_fixed 10292U, // VLD2DUPd32wb_register 32U, // VLD2DUPd32x2 44U, // VLD2DUPd32x2wb_fixed 10292U, // VLD2DUPd32x2wb_register 32U, // VLD2DUPd8 44U, // VLD2DUPd8wb_fixed 10292U, // VLD2DUPd8wb_register 32U, // VLD2DUPd8x2 44U, // VLD2DUPd8x2wb_fixed 10292U, // VLD2DUPd8x2wb_register 0U, // VLD2DUPq16EvenPseudo 0U, // VLD2DUPq16OddPseudo 0U, // VLD2DUPq32EvenPseudo 0U, // VLD2DUPq32OddPseudo 0U, // VLD2DUPq8EvenPseudo 0U, // VLD2DUPq8OddPseudo 766196U, // VLD2LNd16 0U, // VLD2LNd16Pseudo 0U, // VLD2LNd16Pseudo_UPD 799996U, // VLD2LNd16_UPD 766196U, // VLD2LNd32 0U, // VLD2LNd32Pseudo 0U, // VLD2LNd32Pseudo_UPD 799996U, // VLD2LNd32_UPD 766196U, // VLD2LNd8 0U, // VLD2LNd8Pseudo 0U, // VLD2LNd8Pseudo_UPD 799996U, // VLD2LNd8_UPD 766196U, // VLD2LNq16 0U, // VLD2LNq16Pseudo 0U, // VLD2LNq16Pseudo_UPD 799996U, // VLD2LNq16_UPD 766196U, // VLD2LNq32 0U, // VLD2LNq32Pseudo 0U, // VLD2LNq32Pseudo_UPD 799996U, // VLD2LNq32_UPD 32U, // VLD2b16 44U, // VLD2b16wb_fixed 10292U, // VLD2b16wb_register 32U, // VLD2b32 44U, // VLD2b32wb_fixed 10292U, // VLD2b32wb_register 32U, // VLD2b8 44U, // VLD2b8wb_fixed 10292U, // VLD2b8wb_register 32U, // VLD2d16 44U, // VLD2d16wb_fixed 10292U, // VLD2d16wb_register 32U, // VLD2d32 44U, // VLD2d32wb_fixed 10292U, // VLD2d32wb_register 32U, // VLD2d8 44U, // VLD2d8wb_fixed 10292U, // VLD2d8wb_register 32U, // VLD2q16 0U, // VLD2q16Pseudo 0U, // VLD2q16PseudoWB_fixed 0U, // VLD2q16PseudoWB_register 44U, // VLD2q16wb_fixed 10292U, // VLD2q16wb_register 32U, // VLD2q32 0U, // VLD2q32Pseudo 0U, // VLD2q32PseudoWB_fixed 0U, // VLD2q32PseudoWB_register 44U, // VLD2q32wb_fixed 10292U, // VLD2q32wb_register 32U, // VLD2q8 0U, // VLD2q8Pseudo 0U, // VLD2q8PseudoWB_fixed 0U, // VLD2q8PseudoWB_register 44U, // VLD2q8wb_fixed 10292U, // VLD2q8wb_register 14596U, // VLD3DUPd16 0U, // VLD3DUPd16Pseudo 0U, // VLD3DUPd16Pseudo_UPD 834820U, // VLD3DUPd16_UPD 14596U, // VLD3DUPd32 0U, // VLD3DUPd32Pseudo 0U, // VLD3DUPd32Pseudo_UPD 834820U, // VLD3DUPd32_UPD 14596U, // VLD3DUPd8 0U, // VLD3DUPd8Pseudo 0U, // VLD3DUPd8Pseudo_UPD 834820U, // VLD3DUPd8_UPD 14596U, // VLD3DUPq16 0U, // VLD3DUPq16EvenPseudo 0U, // VLD3DUPq16OddPseudo 834820U, // VLD3DUPq16_UPD 14596U, // VLD3DUPq32 0U, // VLD3DUPq32EvenPseudo 0U, // VLD3DUPq32OddPseudo 834820U, // VLD3DUPq32_UPD 14596U, // VLD3DUPq8 0U, // VLD3DUPq8EvenPseudo 0U, // VLD3DUPq8OddPseudo 834820U, // VLD3DUPq8_UPD 865532U, // VLD3LNd16 0U, // VLD3LNd16Pseudo 0U, // VLD3LNd16Pseudo_UPD 896268U, // VLD3LNd16_UPD 865532U, // VLD3LNd32 0U, // VLD3LNd32Pseudo 0U, // VLD3LNd32Pseudo_UPD 896268U, // VLD3LNd32_UPD 865532U, // VLD3LNd8 0U, // VLD3LNd8Pseudo 0U, // VLD3LNd8Pseudo_UPD 896268U, // VLD3LNd8_UPD 865532U, // VLD3LNq16 0U, // VLD3LNq16Pseudo 0U, // VLD3LNq16Pseudo_UPD 896268U, // VLD3LNq16_UPD 865532U, // VLD3LNq32 0U, // VLD3LNq32Pseudo 0U, // VLD3LNq32Pseudo_UPD 896268U, // VLD3LNq32_UPD 119537664U, // VLD3d16 0U, // VLD3d16Pseudo 0U, // VLD3d16Pseudo_UPD 153092096U, // VLD3d16_UPD 119537664U, // VLD3d32 0U, // VLD3d32Pseudo 0U, // VLD3d32Pseudo_UPD 153092096U, // VLD3d32_UPD 119537664U, // VLD3d8 0U, // VLD3d8Pseudo 0U, // VLD3d8Pseudo_UPD 153092096U, // VLD3d8_UPD 119537664U, // VLD3q16 0U, // VLD3q16Pseudo_UPD 153092096U, // VLD3q16_UPD 0U, // VLD3q16oddPseudo 0U, // VLD3q16oddPseudo_UPD 119537664U, // VLD3q32 0U, // VLD3q32Pseudo_UPD 153092096U, // VLD3q32_UPD 0U, // VLD3q32oddPseudo 0U, // VLD3q32oddPseudo_UPD 119537664U, // VLD3q8 0U, // VLD3q8Pseudo_UPD 153092096U, // VLD3q8_UPD 0U, // VLD3q8oddPseudo 0U, // VLD3q8oddPseudo_UPD 81172U, // VLD4DUPd16 0U, // VLD4DUPd16Pseudo 0U, // VLD4DUPd16Pseudo_UPD 16660U, // VLD4DUPd16_UPD 81172U, // VLD4DUPd32 0U, // VLD4DUPd32Pseudo 0U, // VLD4DUPd32Pseudo_UPD 16660U, // VLD4DUPd32_UPD 81172U, // VLD4DUPd8 0U, // VLD4DUPd8Pseudo 0U, // VLD4DUPd8Pseudo_UPD 16660U, // VLD4DUPd8_UPD 81172U, // VLD4DUPq16 0U, // VLD4DUPq16EvenPseudo 0U, // VLD4DUPq16OddPseudo 16660U, // VLD4DUPq16_UPD 81172U, // VLD4DUPq32 0U, // VLD4DUPq32EvenPseudo 0U, // VLD4DUPq32OddPseudo 16660U, // VLD4DUPq32_UPD 81172U, // VLD4DUPq8 0U, // VLD4DUPq8EvenPseudo 0U, // VLD4DUPq8OddPseudo 16660U, // VLD4DUPq8_UPD 189346060U, // VLD4LNd16 0U, // VLD4LNd16Pseudo 0U, // VLD4LNd16Pseudo_UPD 284U, // VLD4LNd16_UPD 189346060U, // VLD4LNd32 0U, // VLD4LNd32Pseudo 0U, // VLD4LNd32Pseudo_UPD 284U, // VLD4LNd32_UPD 189346060U, // VLD4LNd8 0U, // VLD4LNd8Pseudo 0U, // VLD4LNd8Pseudo_UPD 284U, // VLD4LNd8_UPD 189346060U, // VLD4LNq16 0U, // VLD4LNq16Pseudo 0U, // VLD4LNq16Pseudo_UPD 284U, // VLD4LNq16_UPD 189346060U, // VLD4LNq32 0U, // VLD4LNq32Pseudo 0U, // VLD4LNq32Pseudo_UPD 284U, // VLD4LNq32_UPD 572522496U, // VLD4d16 0U, // VLD4d16Pseudo 0U, // VLD4d16Pseudo_UPD 1646264320U, // VLD4d16_UPD 572522496U, // VLD4d32 0U, // VLD4d32Pseudo 0U, // VLD4d32Pseudo_UPD 1646264320U, // VLD4d32_UPD 572522496U, // VLD4d8 0U, // VLD4d8Pseudo 0U, // VLD4d8Pseudo_UPD 1646264320U, // VLD4d8_UPD 572522496U, // VLD4q16 0U, // VLD4q16Pseudo_UPD 1646264320U, // VLD4q16_UPD 0U, // VLD4q16oddPseudo 0U, // VLD4q16oddPseudo_UPD 572522496U, // VLD4q32 0U, // VLD4q32Pseudo_UPD 1646264320U, // VLD4q32_UPD 0U, // VLD4q32oddPseudo 0U, // VLD4q32oddPseudo_UPD 572522496U, // VLD4q8 0U, // VLD4q8Pseudo_UPD 1646264320U, // VLD4q8_UPD 0U, // VLD4q8oddPseudo 0U, // VLD4q8oddPseudo_UPD 33U, // VLDMDDB_UPD 1136U, // VLDMDIA 33U, // VLDMDIA_UPD 0U, // VLDMQIA 33U, // VLDMSDB_UPD 1136U, // VLDMSIA 33U, // VLDMSIA_UPD 288U, // VLDRD 296U, // VLDRH 288U, // VLDRS 0U, // VLLDM 0U, // VLSTM 1112U, // VMAXNMD 1112U, // VMAXNMH 1112U, // VMAXNMNDf 1112U, // VMAXNMNDh 1112U, // VMAXNMNQf 1112U, // VMAXNMNQh 1112U, // VMAXNMS 70705U, // VMAXfd 70705U, // VMAXfq 70705U, // VMAXhd 70705U, // VMAXhq 1112U, // VMAXsv16i8 1112U, // VMAXsv2i32 1112U, // VMAXsv4i16 1112U, // VMAXsv4i32 1112U, // VMAXsv8i16 1112U, // VMAXsv8i8 1112U, // VMAXuv16i8 1112U, // VMAXuv2i32 1112U, // VMAXuv4i16 1112U, // VMAXuv4i32 1112U, // VMAXuv8i16 1112U, // VMAXuv8i8 1112U, // VMINNMD 1112U, // VMINNMH 1112U, // VMINNMNDf 1112U, // VMINNMNDh 1112U, // VMINNMNQf 1112U, // VMINNMNQh 1112U, // VMINNMS 70705U, // VMINfd 70705U, // VMINfq 70705U, // VMINhd 70705U, // VMINhq 1112U, // VMINsv16i8 1112U, // VMINsv2i32 1112U, // VMINsv4i16 1112U, // VMINsv4i32 1112U, // VMINsv8i16 1112U, // VMINsv8i8 1112U, // VMINuv16i8 1112U, // VMINuv2i32 1112U, // VMINuv4i16 1112U, // VMINuv4i32 1112U, // VMINuv8i16 1112U, // VMINuv8i8 68659U, // VMLAD 68659U, // VMLAH 73752U, // VMLALslsv2i32 73752U, // VMLALslsv4i16 73752U, // VMLALsluv2i32 73752U, // VMLALsluv4i16 1048U, // VMLALsv2i64 1048U, // VMLALsv4i32 1048U, // VMLALsv8i16 1048U, // VMLALuv2i64 1048U, // VMLALuv4i32 1048U, // VMLALuv8i16 68659U, // VMLAS 68659U, // VMLAfd 68659U, // VMLAfq 68659U, // VMLAhd 68659U, // VMLAhq 920627U, // VMLAslfd 920627U, // VMLAslfq 920627U, // VMLAslhd 920627U, // VMLAslhq 73752U, // VMLAslv2i32 73752U, // VMLAslv4i16 73752U, // VMLAslv4i32 73752U, // VMLAslv8i16 1048U, // VMLAv16i8 1048U, // VMLAv2i32 1048U, // VMLAv4i16 1048U, // VMLAv4i32 1048U, // VMLAv8i16 1048U, // VMLAv8i8 68659U, // VMLSD 68659U, // VMLSH 73752U, // VMLSLslsv2i32 73752U, // VMLSLslsv4i16 73752U, // VMLSLsluv2i32 73752U, // VMLSLsluv4i16 1048U, // VMLSLsv2i64 1048U, // VMLSLsv4i32 1048U, // VMLSLsv8i16 1048U, // VMLSLuv2i64 1048U, // VMLSLuv4i32 1048U, // VMLSLuv8i16 68659U, // VMLSS 68659U, // VMLSfd 68659U, // VMLSfq 68659U, // VMLShd 68659U, // VMLShq 920627U, // VMLSslfd 920627U, // VMLSslfq 920627U, // VMLSslhd 920627U, // VMLSslhq 73752U, // VMLSslv2i32 73752U, // VMLSslv4i16 73752U, // VMLSslv4i32 73752U, // VMLSslv8i16 1048U, // VMLSv16i8 1048U, // VMLSv2i32 1048U, // VMLSv4i16 1048U, // VMLSv4i32 1048U, // VMLSv8i16 1048U, // VMLSv8i8 33U, // VMOVD 0U, // VMOVDRR 0U, // VMOVH 33U, // VMOVHR 0U, // VMOVLsv2i64 0U, // VMOVLsv4i32 0U, // VMOVLsv8i16 0U, // VMOVLuv2i64 0U, // VMOVLuv4i32 0U, // VMOVLuv8i16 0U, // VMOVNv2i32 0U, // VMOVNv4i16 0U, // VMOVNv8i8 33U, // VMOVRH 0U, // VMOVRRD 35651584U, // VMOVRRS 1024U, // VMOVRS 33U, // VMOVS 1024U, // VMOVSR 35651584U, // VMOVSRR 0U, // VMOVv16i8 0U, // VMOVv1i64 1U, // VMOVv2f32 0U, // VMOVv2i32 0U, // VMOVv2i64 1U, // VMOVv4f32 0U, // VMOVv4i16 0U, // VMOVv4i32 0U, // VMOVv8i16 0U, // VMOVv8i8 4U, // VMRS 5U, // VMRS_FPEXC 5U, // VMRS_FPINST 5U, // VMRS_FPINST2 5U, // VMRS_FPSID 6U, // VMRS_MVFR0 6U, // VMRS_MVFR1 6U, // VMRS_MVFR2 0U, // VMSR 0U, // VMSR_FPEXC 0U, // VMSR_FPINST 0U, // VMSR_FPINST2 0U, // VMSR_FPSID 70705U, // VMULD 70705U, // VMULH 1112U, // VMULLp64 0U, // VMULLp8 17496U, // VMULLslsv2i32 17496U, // VMULLslsv4i16 17496U, // VMULLsluv2i32 17496U, // VMULLsluv4i16 1112U, // VMULLsv2i64 1112U, // VMULLsv4i32 1112U, // VMULLsv8i16 1112U, // VMULLuv2i64 1112U, // VMULLuv4i32 1112U, // VMULLuv8i16 70705U, // VMULS 70705U, // VMULfd 70705U, // VMULfq 70705U, // VMULhd 70705U, // VMULhq 0U, // VMULpd 0U, // VMULpq 955441U, // VMULslfd 955441U, // VMULslfq 955441U, // VMULslhd 955441U, // VMULslhq 17496U, // VMULslv2i32 17496U, // VMULslv4i16 17496U, // VMULslv4i32 17496U, // VMULslv8i16 1112U, // VMULv16i8 1112U, // VMULv2i32 1112U, // VMULv4i16 1112U, // VMULv4i32 1112U, // VMULv8i16 1112U, // VMULv8i8 1024U, // VMVNd 1024U, // VMVNq 0U, // VMVNv2i32 0U, // VMVNv4i16 0U, // VMVNv4i32 0U, // VMVNv8i16 33U, // VNEGD 33U, // VNEGH 33U, // VNEGS 33U, // VNEGf32q 33U, // VNEGfd 33U, // VNEGhd 33U, // VNEGhq 0U, // VNEGs16d 0U, // VNEGs16q 0U, // VNEGs32d 0U, // VNEGs32q 0U, // VNEGs8d 0U, // VNEGs8q 68659U, // VNMLAD 68659U, // VNMLAH 68659U, // VNMLAS 68659U, // VNMLSD 68659U, // VNMLSH 68659U, // VNMLSS 70705U, // VNMULD 70705U, // VNMULH 70705U, // VNMULS 0U, // VORNd 0U, // VORNq 0U, // VORRd 0U, // VORRiv2i32 0U, // VORRiv4i16 0U, // VORRiv4i32 0U, // VORRiv8i16 0U, // VORRq 0U, // VPADALsv16i8 0U, // VPADALsv2i32 0U, // VPADALsv4i16 0U, // VPADALsv4i32 0U, // VPADALsv8i16 0U, // VPADALsv8i8 0U, // VPADALuv16i8 0U, // VPADALuv2i32 0U, // VPADALuv4i16 0U, // VPADALuv4i32 0U, // VPADALuv8i16 0U, // VPADALuv8i8 0U, // VPADDLsv16i8 0U, // VPADDLsv2i32 0U, // VPADDLsv4i16 0U, // VPADDLsv4i32 0U, // VPADDLsv8i16 0U, // VPADDLsv8i8 0U, // VPADDLuv16i8 0U, // VPADDLuv2i32 0U, // VPADDLuv4i16 0U, // VPADDLuv4i32 0U, // VPADDLuv8i16 0U, // VPADDLuv8i8 70705U, // VPADDf 70705U, // VPADDh 1112U, // VPADDi16 1112U, // VPADDi32 1112U, // VPADDi8 70705U, // VPMAXf 70705U, // VPMAXh 1112U, // VPMAXs16 1112U, // VPMAXs32 1112U, // VPMAXs8 1112U, // VPMAXu16 1112U, // VPMAXu32 1112U, // VPMAXu8 70705U, // VPMINf 70705U, // VPMINh 1112U, // VPMINs16 1112U, // VPMINs32 1112U, // VPMINs8 1112U, // VPMINu16 1112U, // VPMINu32 1112U, // VPMINu8 0U, // VQABSv16i8 0U, // VQABSv2i32 0U, // VQABSv4i16 0U, // VQABSv4i32 0U, // VQABSv8i16 0U, // VQABSv8i8 1112U, // VQADDsv16i8 1112U, // VQADDsv1i64 1112U, // VQADDsv2i32 1112U, // VQADDsv2i64 1112U, // VQADDsv4i16 1112U, // VQADDsv4i32 1112U, // VQADDsv8i16 1112U, // VQADDsv8i8 1112U, // VQADDuv16i8 1112U, // VQADDuv1i64 1112U, // VQADDuv2i32 1112U, // VQADDuv2i64 1112U, // VQADDuv4i16 1112U, // VQADDuv4i32 1112U, // VQADDuv8i16 1112U, // VQADDuv8i8 73752U, // VQDMLALslv2i32 73752U, // VQDMLALslv4i16 1048U, // VQDMLALv2i64 1048U, // VQDMLALv4i32 73752U, // VQDMLSLslv2i32 73752U, // VQDMLSLslv4i16 1048U, // VQDMLSLv2i64 1048U, // VQDMLSLv4i32 17496U, // VQDMULHslv2i32 17496U, // VQDMULHslv4i16 17496U, // VQDMULHslv4i32 17496U, // VQDMULHslv8i16 1112U, // VQDMULHv2i32 1112U, // VQDMULHv4i16 1112U, // VQDMULHv4i32 1112U, // VQDMULHv8i16 17496U, // VQDMULLslv2i32 17496U, // VQDMULLslv4i16 1112U, // VQDMULLv2i64 1112U, // VQDMULLv4i32 0U, // VQMOVNsuv2i32 0U, // VQMOVNsuv4i16 0U, // VQMOVNsuv8i8 0U, // VQMOVNsv2i32 0U, // VQMOVNsv4i16 0U, // VQMOVNsv8i8 0U, // VQMOVNuv2i32 0U, // VQMOVNuv4i16 0U, // VQMOVNuv8i8 0U, // VQNEGv16i8 0U, // VQNEGv2i32 0U, // VQNEGv4i16 0U, // VQNEGv4i32 0U, // VQNEGv8i16 0U, // VQNEGv8i8 73752U, // VQRDMLAHslv2i32 73752U, // VQRDMLAHslv4i16 73752U, // VQRDMLAHslv4i32 73752U, // VQRDMLAHslv8i16 1048U, // VQRDMLAHv2i32 1048U, // VQRDMLAHv4i16 1048U, // VQRDMLAHv4i32 1048U, // VQRDMLAHv8i16 73752U, // VQRDMLSHslv2i32 73752U, // VQRDMLSHslv4i16 73752U, // VQRDMLSHslv4i32 73752U, // VQRDMLSHslv8i16 1048U, // VQRDMLSHv2i32 1048U, // VQRDMLSHv4i16 1048U, // VQRDMLSHv4i32 1048U, // VQRDMLSHv8i16 17496U, // VQRDMULHslv2i32 17496U, // VQRDMULHslv4i16 17496U, // VQRDMULHslv4i32 17496U, // VQRDMULHslv8i16 1112U, // VQRDMULHv2i32 1112U, // VQRDMULHv4i16 1112U, // VQRDMULHv4i32 1112U, // VQRDMULHv8i16 1112U, // VQRSHLsv16i8 1112U, // VQRSHLsv1i64 1112U, // VQRSHLsv2i32 1112U, // VQRSHLsv2i64 1112U, // VQRSHLsv4i16 1112U, // VQRSHLsv4i32 1112U, // VQRSHLsv8i16 1112U, // VQRSHLsv8i8 1112U, // VQRSHLuv16i8 1112U, // VQRSHLuv1i64 1112U, // VQRSHLuv2i32 1112U, // VQRSHLuv2i64 1112U, // VQRSHLuv4i16 1112U, // VQRSHLuv4i32 1112U, // VQRSHLuv8i16 1112U, // VQRSHLuv8i8 1112U, // VQRSHRNsv2i32 1112U, // VQRSHRNsv4i16 1112U, // VQRSHRNsv8i8 1112U, // VQRSHRNuv2i32 1112U, // VQRSHRNuv4i16 1112U, // VQRSHRNuv8i8 1112U, // VQRSHRUNv2i32 1112U, // VQRSHRUNv4i16 1112U, // VQRSHRUNv8i8 1112U, // VQSHLsiv16i8 1112U, // VQSHLsiv1i64 1112U, // VQSHLsiv2i32 1112U, // VQSHLsiv2i64 1112U, // VQSHLsiv4i16 1112U, // VQSHLsiv4i32 1112U, // VQSHLsiv8i16 1112U, // VQSHLsiv8i8 1112U, // VQSHLsuv16i8 1112U, // VQSHLsuv1i64 1112U, // VQSHLsuv2i32 1112U, // VQSHLsuv2i64 1112U, // VQSHLsuv4i16 1112U, // VQSHLsuv4i32 1112U, // VQSHLsuv8i16 1112U, // VQSHLsuv8i8 1112U, // VQSHLsv16i8 1112U, // VQSHLsv1i64 1112U, // VQSHLsv2i32 1112U, // VQSHLsv2i64 1112U, // VQSHLsv4i16 1112U, // VQSHLsv4i32 1112U, // VQSHLsv8i16 1112U, // VQSHLsv8i8 1112U, // VQSHLuiv16i8 1112U, // VQSHLuiv1i64 1112U, // VQSHLuiv2i32 1112U, // VQSHLuiv2i64 1112U, // VQSHLuiv4i16 1112U, // VQSHLuiv4i32 1112U, // VQSHLuiv8i16 1112U, // VQSHLuiv8i8 1112U, // VQSHLuv16i8 1112U, // VQSHLuv1i64 1112U, // VQSHLuv2i32 1112U, // VQSHLuv2i64 1112U, // VQSHLuv4i16 1112U, // VQSHLuv4i32 1112U, // VQSHLuv8i16 1112U, // VQSHLuv8i8 1112U, // VQSHRNsv2i32 1112U, // VQSHRNsv4i16 1112U, // VQSHRNsv8i8 1112U, // VQSHRNuv2i32 1112U, // VQSHRNuv4i16 1112U, // VQSHRNuv8i8 1112U, // VQSHRUNv2i32 1112U, // VQSHRUNv4i16 1112U, // VQSHRUNv8i8 1112U, // VQSUBsv16i8 1112U, // VQSUBsv1i64 1112U, // VQSUBsv2i32 1112U, // VQSUBsv2i64 1112U, // VQSUBsv4i16 1112U, // VQSUBsv4i32 1112U, // VQSUBsv8i16 1112U, // VQSUBsv8i8 1112U, // VQSUBuv16i8 1112U, // VQSUBuv1i64 1112U, // VQSUBuv2i32 1112U, // VQSUBuv2i64 1112U, // VQSUBuv4i16 1112U, // VQSUBuv4i32 1112U, // VQSUBuv8i16 1112U, // VQSUBuv8i8 1112U, // VRADDHNv2i32 1112U, // VRADDHNv4i16 1112U, // VRADDHNv8i8 0U, // VRECPEd 33U, // VRECPEfd 33U, // VRECPEfq 33U, // VRECPEhd 33U, // VRECPEhq 0U, // VRECPEq 70705U, // VRECPSfd 70705U, // VRECPSfq 70705U, // VRECPShd 70705U, // VRECPShq 1024U, // VREV16d8 1024U, // VREV16q8 1024U, // VREV32d16 1024U, // VREV32d8 1024U, // VREV32q16 1024U, // VREV32q8 1024U, // VREV64d16 1024U, // VREV64d32 1024U, // VREV64d8 1024U, // VREV64q16 1024U, // VREV64q32 1024U, // VREV64q8 1112U, // VRHADDsv16i8 1112U, // VRHADDsv2i32 1112U, // VRHADDsv4i16 1112U, // VRHADDsv4i32 1112U, // VRHADDsv8i16 1112U, // VRHADDsv8i8 1112U, // VRHADDuv16i8 1112U, // VRHADDuv2i32 1112U, // VRHADDuv4i16 1112U, // VRHADDuv4i32 1112U, // VRHADDuv8i16 1112U, // VRHADDuv8i8 0U, // VRINTAD 0U, // VRINTAH 0U, // VRINTANDf 0U, // VRINTANDh 0U, // VRINTANQf 0U, // VRINTANQh 0U, // VRINTAS 0U, // VRINTMD 0U, // VRINTMH 0U, // VRINTMNDf 0U, // VRINTMNDh 0U, // VRINTMNQf 0U, // VRINTMNQh 0U, // VRINTMS 0U, // VRINTND 0U, // VRINTNH 0U, // VRINTNNDf 0U, // VRINTNNDh 0U, // VRINTNNQf 0U, // VRINTNNQh 0U, // VRINTNS 0U, // VRINTPD 0U, // VRINTPH 0U, // VRINTPNDf 0U, // VRINTPNDh 0U, // VRINTPNQf 0U, // VRINTPNQh 0U, // VRINTPS 33U, // VRINTRD 33U, // VRINTRH 33U, // VRINTRS 33U, // VRINTXD 33U, // VRINTXH 0U, // VRINTXNDf 0U, // VRINTXNDh 0U, // VRINTXNQf 0U, // VRINTXNQh 33U, // VRINTXS 33U, // VRINTZD 33U, // VRINTZH 0U, // VRINTZNDf 0U, // VRINTZNDh 0U, // VRINTZNQf 0U, // VRINTZNQh 33U, // VRINTZS 1112U, // VRSHLsv16i8 1112U, // VRSHLsv1i64 1112U, // VRSHLsv2i32 1112U, // VRSHLsv2i64 1112U, // VRSHLsv4i16 1112U, // VRSHLsv4i32 1112U, // VRSHLsv8i16 1112U, // VRSHLsv8i8 1112U, // VRSHLuv16i8 1112U, // VRSHLuv1i64 1112U, // VRSHLuv2i32 1112U, // VRSHLuv2i64 1112U, // VRSHLuv4i16 1112U, // VRSHLuv4i32 1112U, // VRSHLuv8i16 1112U, // VRSHLuv8i8 1112U, // VRSHRNv2i32 1112U, // VRSHRNv4i16 1112U, // VRSHRNv8i8 1112U, // VRSHRsv16i8 1112U, // VRSHRsv1i64 1112U, // VRSHRsv2i32 1112U, // VRSHRsv2i64 1112U, // VRSHRsv4i16 1112U, // VRSHRsv4i32 1112U, // VRSHRsv8i16 1112U, // VRSHRsv8i8 1112U, // VRSHRuv16i8 1112U, // VRSHRuv1i64 1112U, // VRSHRuv2i32 1112U, // VRSHRuv2i64 1112U, // VRSHRuv4i16 1112U, // VRSHRuv4i32 1112U, // VRSHRuv8i16 1112U, // VRSHRuv8i8 0U, // VRSQRTEd 33U, // VRSQRTEfd 33U, // VRSQRTEfq 33U, // VRSQRTEhd 33U, // VRSQRTEhq 0U, // VRSQRTEq 70705U, // VRSQRTSfd 70705U, // VRSQRTSfq 70705U, // VRSQRTShd 70705U, // VRSQRTShq 1048U, // VRSRAsv16i8 1048U, // VRSRAsv1i64 1048U, // VRSRAsv2i32 1048U, // VRSRAsv2i64 1048U, // VRSRAsv4i16 1048U, // VRSRAsv4i32 1048U, // VRSRAsv8i16 1048U, // VRSRAsv8i8 1048U, // VRSRAuv16i8 1048U, // VRSRAuv1i64 1048U, // VRSRAuv2i32 1048U, // VRSRAuv2i64 1048U, // VRSRAuv4i16 1048U, // VRSRAuv4i32 1048U, // VRSRAuv8i16 1048U, // VRSRAuv8i8 1112U, // VRSUBHNv2i32 1112U, // VRSUBHNv4i16 1112U, // VRSUBHNv8i8 0U, // VSDOTD 0U, // VSDOTDI 0U, // VSDOTQ 0U, // VSDOTQI 1112U, // VSELEQD 1112U, // VSELEQH 1112U, // VSELEQS 1112U, // VSELGED 1112U, // VSELGEH 1112U, // VSELGES 1112U, // VSELGTD 1112U, // VSELGTH 1112U, // VSELGTS 1112U, // VSELVSD 1112U, // VSELVSH 1112U, // VSELVSS 6U, // VSETLNi16 6U, // VSETLNi32 6U, // VSETLNi8 1112U, // VSHLLi16 1112U, // VSHLLi32 1112U, // VSHLLi8 1112U, // VSHLLsv2i64 1112U, // VSHLLsv4i32 1112U, // VSHLLsv8i16 1112U, // VSHLLuv2i64 1112U, // VSHLLuv4i32 1112U, // VSHLLuv8i16 1112U, // VSHLiv16i8 1112U, // VSHLiv1i64 1112U, // VSHLiv2i32 1112U, // VSHLiv2i64 1112U, // VSHLiv4i16 1112U, // VSHLiv4i32 1112U, // VSHLiv8i16 1112U, // VSHLiv8i8 1112U, // VSHLsv16i8 1112U, // VSHLsv1i64 1112U, // VSHLsv2i32 1112U, // VSHLsv2i64 1112U, // VSHLsv4i16 1112U, // VSHLsv4i32 1112U, // VSHLsv8i16 1112U, // VSHLsv8i8 1112U, // VSHLuv16i8 1112U, // VSHLuv1i64 1112U, // VSHLuv2i32 1112U, // VSHLuv2i64 1112U, // VSHLuv4i16 1112U, // VSHLuv4i32 1112U, // VSHLuv8i16 1112U, // VSHLuv8i8 1112U, // VSHRNv2i32 1112U, // VSHRNv4i16 1112U, // VSHRNv8i8 1112U, // VSHRsv16i8 1112U, // VSHRsv1i64 1112U, // VSHRsv2i32 1112U, // VSHRsv2i64 1112U, // VSHRsv4i16 1112U, // VSHRsv4i32 1112U, // VSHRsv8i16 1112U, // VSHRsv8i8 1112U, // VSHRuv16i8 1112U, // VSHRuv1i64 1112U, // VSHRuv2i32 1112U, // VSHRuv2i64 1112U, // VSHRuv4i16 1112U, // VSHRuv4i32 1112U, // VSHRuv8i16 1112U, // VSHRuv8i8 0U, // VSHTOD 7U, // VSHTOH 0U, // VSHTOS 0U, // VSITOD 0U, // VSITOH 0U, // VSITOS 589912U, // VSLIv16i8 589912U, // VSLIv1i64 589912U, // VSLIv2i32 589912U, // VSLIv2i64 589912U, // VSLIv4i16 589912U, // VSLIv4i32 589912U, // VSLIv8i16 589912U, // VSLIv8i8 7U, // VSLTOD 7U, // VSLTOH 7U, // VSLTOS 33U, // VSQRTD 33U, // VSQRTH 33U, // VSQRTS 1048U, // VSRAsv16i8 1048U, // VSRAsv1i64 1048U, // VSRAsv2i32 1048U, // VSRAsv2i64 1048U, // VSRAsv4i16 1048U, // VSRAsv4i32 1048U, // VSRAsv8i16 1048U, // VSRAsv8i8 1048U, // VSRAuv16i8 1048U, // VSRAuv1i64 1048U, // VSRAuv2i32 1048U, // VSRAuv2i64 1048U, // VSRAuv4i16 1048U, // VSRAuv4i32 1048U, // VSRAuv8i16 1048U, // VSRAuv8i8 589912U, // VSRIv16i8 589912U, // VSRIv1i64 589912U, // VSRIv2i32 589912U, // VSRIv2i64 589912U, // VSRIv4i16 589912U, // VSRIv4i32 589912U, // VSRIv8i16 589912U, // VSRIv8i8 308U, // VST1LNd16 23768380U, // VST1LNd16_UPD 308U, // VST1LNd32 23768380U, // VST1LNd32_UPD 308U, // VST1LNd8 23768380U, // VST1LNd8_UPD 0U, // VST1LNq16Pseudo 0U, // VST1LNq16Pseudo_UPD 0U, // VST1LNq32Pseudo 0U, // VST1LNq32Pseudo_UPD 0U, // VST1LNq8Pseudo 0U, // VST1LNq8Pseudo_UPD 0U, // VST1d16 0U, // VST1d16Q 0U, // VST1d16QPseudo 0U, // VST1d16Qwb_fixed 0U, // VST1d16Qwb_register 0U, // VST1d16T 0U, // VST1d16TPseudo 0U, // VST1d16Twb_fixed 0U, // VST1d16Twb_register 0U, // VST1d16wb_fixed 0U, // VST1d16wb_register 0U, // VST1d32 0U, // VST1d32Q 0U, // VST1d32QPseudo 0U, // VST1d32Qwb_fixed 0U, // VST1d32Qwb_register 0U, // VST1d32T 0U, // VST1d32TPseudo 0U, // VST1d32Twb_fixed 0U, // VST1d32Twb_register 0U, // VST1d32wb_fixed 0U, // VST1d32wb_register 0U, // VST1d64 0U, // VST1d64Q 0U, // VST1d64QPseudo 0U, // VST1d64QPseudoWB_fixed 0U, // VST1d64QPseudoWB_register 0U, // VST1d64Qwb_fixed 0U, // VST1d64Qwb_register 0U, // VST1d64T 0U, // VST1d64TPseudo 0U, // VST1d64TPseudoWB_fixed 0U, // VST1d64TPseudoWB_register 0U, // VST1d64Twb_fixed 0U, // VST1d64Twb_register 0U, // VST1d64wb_fixed 0U, // VST1d64wb_register 0U, // VST1d8 0U, // VST1d8Q 0U, // VST1d8QPseudo 0U, // VST1d8Qwb_fixed 0U, // VST1d8Qwb_register 0U, // VST1d8T 0U, // VST1d8TPseudo 0U, // VST1d8Twb_fixed 0U, // VST1d8Twb_register 0U, // VST1d8wb_fixed 0U, // VST1d8wb_register 0U, // VST1q16 0U, // VST1q16HighQPseudo 0U, // VST1q16HighTPseudo 0U, // VST1q16LowQPseudo_UPD 0U, // VST1q16LowTPseudo_UPD 0U, // VST1q16wb_fixed 0U, // VST1q16wb_register 0U, // VST1q32 0U, // VST1q32HighQPseudo 0U, // VST1q32HighTPseudo 0U, // VST1q32LowQPseudo_UPD 0U, // VST1q32LowTPseudo_UPD 0U, // VST1q32wb_fixed 0U, // VST1q32wb_register 0U, // VST1q64 0U, // VST1q64HighQPseudo 0U, // VST1q64HighTPseudo 0U, // VST1q64LowQPseudo_UPD 0U, // VST1q64LowTPseudo_UPD 0U, // VST1q64wb_fixed 0U, // VST1q64wb_register 0U, // VST1q8 0U, // VST1q8HighQPseudo 0U, // VST1q8HighTPseudo 0U, // VST1q8LowQPseudo_UPD 0U, // VST1q8LowTPseudo_UPD 0U, // VST1q8wb_fixed 0U, // VST1q8wb_register 222900460U, // VST2LNd16 0U, // VST2LNd16Pseudo 0U, // VST2LNd16Pseudo_UPD 995572U, // VST2LNd16_UPD 222900460U, // VST2LNd32 0U, // VST2LNd32Pseudo 0U, // VST2LNd32Pseudo_UPD 995572U, // VST2LNd32_UPD 222900460U, // VST2LNd8 0U, // VST2LNd8Pseudo 0U, // VST2LNd8Pseudo_UPD 995572U, // VST2LNd8_UPD 222900460U, // VST2LNq16 0U, // VST2LNq16Pseudo 0U, // VST2LNq16Pseudo_UPD 995572U, // VST2LNq16_UPD 222900460U, // VST2LNq32 0U, // VST2LNq32Pseudo 0U, // VST2LNq32Pseudo_UPD 995572U, // VST2LNq32_UPD 0U, // VST2b16 0U, // VST2b16wb_fixed 0U, // VST2b16wb_register 0U, // VST2b32 0U, // VST2b32wb_fixed 0U, // VST2b32wb_register 0U, // VST2b8 0U, // VST2b8wb_fixed 0U, // VST2b8wb_register 0U, // VST2d16 0U, // VST2d16wb_fixed 0U, // VST2d16wb_register 0U, // VST2d32 0U, // VST2d32wb_fixed 0U, // VST2d32wb_register 0U, // VST2d8 0U, // VST2d8wb_fixed 0U, // VST2d8wb_register 0U, // VST2q16 0U, // VST2q16Pseudo 0U, // VST2q16PseudoWB_fixed 0U, // VST2q16PseudoWB_register 0U, // VST2q16wb_fixed 0U, // VST2q16wb_register 0U, // VST2q32 0U, // VST2q32Pseudo 0U, // VST2q32PseudoWB_fixed 0U, // VST2q32PseudoWB_register 0U, // VST2q32wb_fixed 0U, // VST2q32wb_register 0U, // VST2q8 0U, // VST2q8Pseudo 0U, // VST2q8PseudoWB_fixed 0U, // VST2q8PseudoWB_register 0U, // VST2q8wb_fixed 0U, // VST2q8wb_register 256454972U, // VST3LNd16 0U, // VST3LNd16Pseudo 0U, // VST3LNd16Pseudo_UPD 324U, // VST3LNd16_UPD 256454972U, // VST3LNd32 0U, // VST3LNd32Pseudo 0U, // VST3LNd32Pseudo_UPD 324U, // VST3LNd32_UPD 256454972U, // VST3LNd8 0U, // VST3LNd8Pseudo 0U, // VST3LNd8Pseudo_UPD 324U, // VST3LNd8_UPD 256454972U, // VST3LNq16 0U, // VST3LNq16Pseudo 0U, // VST3LNq16Pseudo_UPD 324U, // VST3LNq16_UPD 256454972U, // VST3LNq32 0U, // VST3LNq32Pseudo 0U, // VST3LNq32Pseudo_UPD 324U, // VST3LNq32_UPD 287342616U, // VST3d16 0U, // VST3d16Pseudo 0U, // VST3d16Pseudo_UPD 18760U, // VST3d16_UPD 287342616U, // VST3d32 0U, // VST3d32Pseudo 0U, // VST3d32Pseudo_UPD 18760U, // VST3d32_UPD 287342616U, // VST3d8 0U, // VST3d8Pseudo 0U, // VST3d8Pseudo_UPD 18760U, // VST3d8_UPD 287342616U, // VST3q16 0U, // VST3q16Pseudo_UPD 18760U, // VST3q16_UPD 0U, // VST3q16oddPseudo 0U, // VST3q16oddPseudo_UPD 287342616U, // VST3q32 0U, // VST3q32Pseudo_UPD 18760U, // VST3q32_UPD 0U, // VST3q32oddPseudo 0U, // VST3q32oddPseudo_UPD 287342616U, // VST3q8 0U, // VST3q8Pseudo_UPD 18760U, // VST3q8_UPD 0U, // VST3q8oddPseudo 0U, // VST3q8oddPseudo_UPD 323563764U, // VST4LNd16 0U, // VST4LNd16Pseudo 0U, // VST4LNd16Pseudo_UPD 19708U, // VST4LNd16_UPD 323563764U, // VST4LNd32 0U, // VST4LNd32Pseudo 0U, // VST4LNd32Pseudo_UPD 19708U, // VST4LNd32_UPD 323563764U, // VST4LNd8 0U, // VST4LNd8Pseudo 0U, // VST4LNd8Pseudo_UPD 19708U, // VST4LNd8_UPD 323563764U, // VST4LNq16 0U, // VST4LNq16Pseudo 0U, // VST4LNq16Pseudo_UPD 19708U, // VST4LNq16_UPD 323563764U, // VST4LNq32 0U, // VST4LNq32Pseudo 0U, // VST4LNq32Pseudo_UPD 19708U, // VST4LNq32_UPD 337674264U, // VST4d16 0U, // VST4d16Pseudo 0U, // VST4d16Pseudo_UPD 1016136U, // VST4d16_UPD 337674264U, // VST4d32 0U, // VST4d32Pseudo 0U, // VST4d32Pseudo_UPD 1016136U, // VST4d32_UPD 337674264U, // VST4d8 0U, // VST4d8Pseudo 0U, // VST4d8Pseudo_UPD 1016136U, // VST4d8_UPD 337674264U, // VST4q16 0U, // VST4q16Pseudo_UPD 1016136U, // VST4q16_UPD 0U, // VST4q16oddPseudo 0U, // VST4q16oddPseudo_UPD 337674264U, // VST4q32 0U, // VST4q32Pseudo_UPD 1016136U, // VST4q32_UPD 0U, // VST4q32oddPseudo 0U, // VST4q32oddPseudo_UPD 337674264U, // VST4q8 0U, // VST4q8Pseudo_UPD 1016136U, // VST4q8_UPD 0U, // VST4q8oddPseudo 0U, // VST4q8oddPseudo_UPD 33U, // VSTMDDB_UPD 1136U, // VSTMDIA 33U, // VSTMDIA_UPD 0U, // VSTMQIA 33U, // VSTMSDB_UPD 1136U, // VSTMSIA 33U, // VSTMSIA_UPD 288U, // VSTRD 296U, // VSTRH 288U, // VSTRS 70705U, // VSUBD 70705U, // VSUBH 1112U, // VSUBHNv2i32 1112U, // VSUBHNv4i16 1112U, // VSUBHNv8i8 1112U, // VSUBLsv2i64 1112U, // VSUBLsv4i32 1112U, // VSUBLsv8i16 1112U, // VSUBLuv2i64 1112U, // VSUBLuv4i32 1112U, // VSUBLuv8i16 70705U, // VSUBS 1112U, // VSUBWsv2i64 1112U, // VSUBWsv4i32 1112U, // VSUBWsv8i16 1112U, // VSUBWuv2i64 1112U, // VSUBWuv4i32 1112U, // VSUBWuv8i16 70705U, // VSUBfd 70705U, // VSUBfq 70705U, // VSUBhd 70705U, // VSUBhq 1112U, // VSUBv16i8 1112U, // VSUBv1i64 1112U, // VSUBv2i32 1112U, // VSUBv2i64 1112U, // VSUBv4i16 1112U, // VSUBv4i32 1112U, // VSUBv8i16 1112U, // VSUBv8i8 1024U, // VSWPd 1024U, // VSWPq 336U, // VTBL1 344U, // VTBL2 352U, // VTBL3 0U, // VTBL3Pseudo 360U, // VTBL4 0U, // VTBL4Pseudo 368U, // VTBX1 376U, // VTBX2 384U, // VTBX3 0U, // VTBX3Pseudo 392U, // VTBX4 0U, // VTBX4Pseudo 0U, // VTOSHD 7U, // VTOSHH 0U, // VTOSHS 0U, // VTOSIRD 0U, // VTOSIRH 0U, // VTOSIRS 0U, // VTOSIZD 0U, // VTOSIZH 0U, // VTOSIZS 7U, // VTOSLD 7U, // VTOSLH 7U, // VTOSLS 0U, // VTOUHD 7U, // VTOUHH 0U, // VTOUHS 0U, // VTOUIRD 0U, // VTOUIRH 0U, // VTOUIRS 0U, // VTOUIZD 0U, // VTOUIZH 0U, // VTOUIZS 7U, // VTOULD 7U, // VTOULH 7U, // VTOULS 1024U, // VTRNd16 1024U, // VTRNd32 1024U, // VTRNd8 1024U, // VTRNq16 1024U, // VTRNq32 1024U, // VTRNq8 0U, // VTSTv16i8 0U, // VTSTv2i32 0U, // VTSTv4i16 0U, // VTSTv4i32 0U, // VTSTv8i16 0U, // VTSTv8i8 0U, // VUDOTD 0U, // VUDOTDI 0U, // VUDOTQ 0U, // VUDOTQI 0U, // VUHTOD 7U, // VUHTOH 0U, // VUHTOS 0U, // VUITOD 0U, // VUITOH 0U, // VUITOS 7U, // VULTOD 7U, // VULTOH 7U, // VULTOS 1024U, // VUZPd16 1024U, // VUZPd8 1024U, // VUZPq16 1024U, // VUZPq32 1024U, // VUZPq8 1024U, // VZIPd16 1024U, // VZIPd8 1024U, // VZIPq16 1024U, // VZIPq32 1024U, // VZIPq8 20592U, // sysLDMDA 401U, // sysLDMDA_UPD 20592U, // sysLDMDB 401U, // sysLDMDB_UPD 20592U, // sysLDMIA 401U, // sysLDMIA_UPD 20592U, // sysLDMIB 401U, // sysLDMIB_UPD 20592U, // sysSTMDA 401U, // sysSTMDA_UPD 20592U, // sysSTMDB 401U, // sysSTMDB_UPD 20592U, // sysSTMIA 401U, // sysSTMIA_UPD 20592U, // sysSTMIB 401U, // sysSTMIB_UPD 0U, // t2ADCri 0U, // t2ADCrr 1048576U, // t2ADCrs 0U, // t2ADDri 0U, // t2ADDri12 0U, // t2ADDrr 1048576U, // t2ADDrs 72U, // t2ADR 0U, // t2ANDri 0U, // t2ANDrr 1048576U, // t2ANDrs 1081344U, // t2ASRri 0U, // t2ASRrr 0U, // t2B 80U, // t2BFC 163928U, // t2BFI 0U, // t2BICri 0U, // t2BICrr 1048576U, // t2BICrs 0U, // t2BXJ 0U, // t2Bcc 4145U, // t2CDP 4145U, // t2CDP2 0U, // t2CLREX 1024U, // t2CLZ 1024U, // t2CMNri 1024U, // t2CMNzrr 56U, // t2CMNzrs 1024U, // t2CMPri 1024U, // t2CMPrr 56U, // t2CMPrs 0U, // t2CPS1p 0U, // t2CPS2p 1112U, // t2CPS3p 1112U, // t2CRC32B 1112U, // t2CRC32CB 1112U, // t2CRC32CH 1112U, // t2CRC32CW 1112U, // t2CRC32H 1112U, // t2CRC32W 0U, // t2DBG 0U, // t2DCPS1 0U, // t2DCPS2 0U, // t2DCPS3 0U, // t2DMB 0U, // t2DSB 0U, // t2EORri 0U, // t2EORrr 1048576U, // t2EORrs 0U, // t2HINT 0U, // t2HVC 0U, // t2ISB 0U, // t2IT 0U, // t2Int_eh_sjlj_setjmp 0U, // t2Int_eh_sjlj_setjmp_nofp 8U, // t2LDA 8U, // t2LDAB 8U, // t2LDAEX 8U, // t2LDAEXB 557056U, // t2LDAEXD 8U, // t2LDAEXH 8U, // t2LDAH 122U, // t2LDC2L_OFFSET 196738U, // t2LDC2L_OPTION 229506U, // t2LDC2L_POST 138U, // t2LDC2L_PRE 122U, // t2LDC2_OFFSET 196738U, // t2LDC2_OPTION 229506U, // t2LDC2_POST 138U, // t2LDC2_PRE 122U, // t2LDCL_OFFSET 196738U, // t2LDCL_OPTION 229506U, // t2LDCL_POST 138U, // t2LDCL_PRE 122U, // t2LDC_OFFSET 196738U, // t2LDC_OPTION 229506U, // t2LDC_POST 138U, // t2LDC_PRE 1136U, // t2LDMDB 33U, // t2LDMDB_UPD 1136U, // t2LDMIA 33U, // t2LDMIA_UPD 408U, // t2LDRBT 21632U, // t2LDRB_POST 416U, // t2LDRB_PRE 160U, // t2LDRBi12 408U, // t2LDRBi8 424U, // t2LDRBpci 432U, // t2LDRBs 25493504U, // t2LDRD_POST 1114112U, // t2LDRD_PRE 1146880U, // t2LDRDi8 440U, // t2LDREX 8U, // t2LDREXB 557056U, // t2LDREXD 8U, // t2LDREXH 408U, // t2LDRHT 21632U, // t2LDRH_POST 416U, // t2LDRH_PRE 160U, // t2LDRHi12 408U, // t2LDRHi8 424U, // t2LDRHpci 432U, // t2LDRHs 408U, // t2LDRSBT 21632U, // t2LDRSB_POST 416U, // t2LDRSB_PRE 160U, // t2LDRSBi12 408U, // t2LDRSBi8 424U, // t2LDRSBpci 432U, // t2LDRSBs 408U, // t2LDRSHT 21632U, // t2LDRSH_POST 416U, // t2LDRSH_PRE 160U, // t2LDRSHi12 408U, // t2LDRSHi8 424U, // t2LDRSHpci 432U, // t2LDRSHs 408U, // t2LDRT 21632U, // t2LDR_POST 416U, // t2LDR_PRE 160U, // t2LDRi12 408U, // t2LDRi8 424U, // t2LDRpci 432U, // t2LDRs 0U, // t2LSLri 0U, // t2LSLrr 1081344U, // t2LSRri 0U, // t2LSRrr 4690993U, // t2MCR 4690993U, // t2MCR2 6788145U, // t2MCRR 6788145U, // t2MCRR2 35651584U, // t2MLA 35651584U, // t2MLS 1112U, // t2MOVTi16 1024U, // t2MOVi 1024U, // t2MOVi16 1024U, // t2MOVr 22528U, // t2MOVsra_flag 22528U, // t2MOVsrl_flag 0U, // t2MRC 0U, // t2MRC2 0U, // t2MRRC 0U, // t2MRRC2 2U, // t2MRS_AR 448U, // t2MRS_M 200U, // t2MRSbanked 2U, // t2MRSsys_AR 33U, // t2MSR_AR 33U, // t2MSR_M 0U, // t2MSRbanked 0U, // t2MUL 1024U, // t2MVNi 1024U, // t2MVNr 56U, // t2MVNs 0U, // t2ORNri 0U, // t2ORNrr 1048576U, // t2ORNrs 0U, // t2ORRri 0U, // t2ORRrr 1048576U, // t2ORRrs 8388608U, // t2PKHBT 10485760U, // t2PKHTB 0U, // t2PLDWi12 0U, // t2PLDWi8 0U, // t2PLDWs 0U, // t2PLDi12 0U, // t2PLDi8 0U, // t2PLDpci 0U, // t2PLDs 0U, // t2PLIi12 0U, // t2PLIi8 0U, // t2PLIpci 0U, // t2PLIs 0U, // t2QADD 0U, // t2QADD16 0U, // t2QADD8 0U, // t2QASX 0U, // t2QDADD 0U, // t2QDSUB 0U, // t2QSAX 0U, // t2QSUB 0U, // t2QSUB16 0U, // t2QSUB8 1024U, // t2RBIT 1024U, // t2REV 1024U, // t2REV16 1024U, // t2REVSH 0U, // t2RFEDB 0U, // t2RFEDBW 0U, // t2RFEIA 0U, // t2RFEIAW 0U, // t2RORri 0U, // t2RORrr 1024U, // t2RRX 0U, // t2RSBri 0U, // t2RSBrr 1048576U, // t2RSBrs 0U, // t2SADD16 0U, // t2SADD8 0U, // t2SASX 0U, // t2SBCri 0U, // t2SBCrr 1048576U, // t2SBCrs 69206016U, // t2SBFX 0U, // t2SDIV 0U, // t2SEL 0U, // t2SETPAN 0U, // t2SG 0U, // t2SHADD16 0U, // t2SHADD8 0U, // t2SHASX 0U, // t2SHSAX 0U, // t2SHSUB16 0U, // t2SHSUB8 0U, // t2SMC 35651584U, // t2SMLABB 35651584U, // t2SMLABT 35651584U, // t2SMLAD 35651584U, // t2SMLADX 35651584U, // t2SMLAL 35651584U, // t2SMLALBB 35651584U, // t2SMLALBT 35651584U, // t2SMLALD 35651584U, // t2SMLALDX 35651584U, // t2SMLALTB 35651584U, // t2SMLALTT 35651584U, // t2SMLATB 35651584U, // t2SMLATT 35651584U, // t2SMLAWB 35651584U, // t2SMLAWT 35651584U, // t2SMLSD 35651584U, // t2SMLSDX 35651584U, // t2SMLSLD 35651584U, // t2SMLSLDX 35651584U, // t2SMMLA 35651584U, // t2SMMLAR 35651584U, // t2SMMLS 35651584U, // t2SMMLSR 0U, // t2SMMUL 0U, // t2SMMULR 0U, // t2SMUAD 0U, // t2SMUADX 0U, // t2SMULBB 0U, // t2SMULBT 35651584U, // t2SMULL 0U, // t2SMULTB 0U, // t2SMULTT 0U, // t2SMULWB 0U, // t2SMULWT 0U, // t2SMUSD 0U, // t2SMUSDX 0U, // t2SRSDB 0U, // t2SRSDB_UPD 0U, // t2SRSIA 0U, // t2SRSIA_UPD 6352U, // t2SSAT 1232U, // t2SSAT16 0U, // t2SSAX 0U, // t2SSUB16 0U, // t2SSUB8 122U, // t2STC2L_OFFSET 196738U, // t2STC2L_OPTION 229506U, // t2STC2L_POST 138U, // t2STC2L_PRE 122U, // t2STC2_OFFSET 196738U, // t2STC2_OPTION 229506U, // t2STC2_POST 138U, // t2STC2_PRE 122U, // t2STCL_OFFSET 196738U, // t2STCL_OPTION 229506U, // t2STCL_POST 138U, // t2STCL_PRE 122U, // t2STC_OFFSET 196738U, // t2STC_OPTION 229506U, // t2STC_POST 138U, // t2STC_PRE 8U, // t2STL 8U, // t2STLB 557056U, // t2STLEX 557056U, // t2STLEXB 371195904U, // t2STLEXD 557056U, // t2STLEXH 8U, // t2STLH 1136U, // t2STMDB 33U, // t2STMDB_UPD 1136U, // t2STMIA 33U, // t2STMIA_UPD 408U, // t2STRBT 21632U, // t2STRB_POST 416U, // t2STRB_PRE 160U, // t2STRBi12 408U, // t2STRBi8 432U, // t2STRBs 25493592U, // t2STRD_POST 1114200U, // t2STRD_PRE 1146880U, // t2STRDi8 1179648U, // t2STREX 557056U, // t2STREXB 371195904U, // t2STREXD 557056U, // t2STREXH 408U, // t2STRHT 21632U, // t2STRH_POST 416U, // t2STRH_PRE 160U, // t2STRHi12 408U, // t2STRHi8 432U, // t2STRHs 408U, // t2STRT 21632U, // t2STR_POST 416U, // t2STR_PRE 160U, // t2STRi12 408U, // t2STRi8 432U, // t2STRs 0U, // t2SUBS_PC_LR 0U, // t2SUBri 0U, // t2SUBri12 0U, // t2SUBrr 1048576U, // t2SUBrs 12582912U, // t2SXTAB 12582912U, // t2SXTAB16 12582912U, // t2SXTAH 7168U, // t2SXTB 7168U, // t2SXTB16 7168U, // t2SXTH 0U, // t2TBB 0U, // t2TBH 1024U, // t2TEQri 1024U, // t2TEQrr 56U, // t2TEQrs 0U, // t2TSB 1024U, // t2TSTri 1024U, // t2TSTrr 56U, // t2TSTrs 1024U, // t2TT 1024U, // t2TTA 1024U, // t2TTAT 1024U, // t2TTT 0U, // t2UADD16 0U, // t2UADD8 0U, // t2UASX 69206016U, // t2UBFX 0U, // t2UDF 0U, // t2UDIV 0U, // t2UHADD16 0U, // t2UHADD8 0U, // t2UHASX 0U, // t2UHSAX 0U, // t2UHSUB16 0U, // t2UHSUB8 35651584U, // t2UMAAL 35651584U, // t2UMLAL 35651584U, // t2UMULL 0U, // t2UQADD16 0U, // t2UQADD8 0U, // t2UQASX 0U, // t2UQSAX 0U, // t2UQSUB16 0U, // t2UQSUB8 0U, // t2USAD8 35651584U, // t2USADA8 14680064U, // t2USAT 0U, // t2USAT16 0U, // t2USAX 0U, // t2USUB16 0U, // t2USUB8 12582912U, // t2UXTAB 12582912U, // t2UXTAB16 12582912U, // t2UXTAH 7168U, // t2UXTB 7168U, // t2UXTB16 7168U, // t2UXTH 0U, // tADC 1112U, // tADDhirr 1048U, // tADDi3 0U, // tADDi8 0U, // tADDrSP 1212416U, // tADDrSPi 1048U, // tADDrr 456U, // tADDspi 1112U, // tADDspr 464U, // tADR 0U, // tAND 472U, // tASRri 0U, // tASRrr 0U, // tB 0U, // tBIC 0U, // tBKPT 0U, // tBL 0U, // tBLXNSr 0U, // tBLXi 0U, // tBLXr 0U, // tBX 0U, // tBXNS 0U, // tBcc 0U, // tCBNZ 0U, // tCBZ 1024U, // tCMNz 1024U, // tCMPhir 1024U, // tCMPi8 1024U, // tCMPr 0U, // tCPS 0U, // tEOR 0U, // tHINT 0U, // tHLT 0U, // tInt_WIN_eh_sjlj_longjmp 0U, // tInt_eh_sjlj_longjmp 0U, // tInt_eh_sjlj_setjmp 1136U, // tLDMIA 480U, // tLDRBi 488U, // tLDRBr 496U, // tLDRHi 488U, // tLDRHr 488U, // tLDRSB 488U, // tLDRSH 504U, // tLDRi 424U, // tLDRpci 488U, // tLDRr 512U, // tLDRspi 1048U, // tLSLri 0U, // tLSLrr 472U, // tLSRri 0U, // tLSRrr 0U, // tMOVSr 0U, // tMOVi8 1024U, // tMOVr 1048U, // tMUL 0U, // tMVN 0U, // tORR 0U, // tPICADD 0U, // tPOP 0U, // tPUSH 1024U, // tREV 1024U, // tREV16 1024U, // tREVSH 0U, // tROR 0U, // tRSB 0U, // tSBC 0U, // tSETEND 33U, // tSTMIA_UPD 480U, // tSTRBi 488U, // tSTRBr 496U, // tSTRHi 488U, // tSTRHr 504U, // tSTRi 488U, // tSTRr 512U, // tSTRspi 1048U, // tSUBi3 0U, // tSUBi8 1048U, // tSUBrr 456U, // tSUBspi 0U, // tSVC 1024U, // tSXTB 1024U, // tSXTH 0U, // tTRAP 1024U, // tTST 0U, // tUDF 1024U, // tUXTB 1024U, // tUXTH 0U, // t__brkdiv0 }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint64_t Bits = 0; Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 4095)-1); #endif // Fragment 0 encoded into 5 bits for 32 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 31)); switch ((Bits >> 12) & 31) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCri, ADCrr, ADDri, A... printSBitModifierOperand(MI, 5, O); printPredicateOperand(MI, 3, O); break; case 2: // ITasm, t2IT printThumbITMask(MI, 1, O); break; case 3: // LDRBT_POST, LDRConstPool, LDRT_POST, STRBT_POST, STRT_POST, t2LDRBpcre... printPredicateOperand(MI, 2, O); break; case 4: // RRXi, MOVi, MOVr, MOVr_TC, MVNi, MVNr, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... printSBitModifierOperand(MI, 4, O); printPredicateOperand(MI, 2, O); break; case 5: // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... printPredicateOperand(MI, 4, O); break; case 6: // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... printPredicateOperand(MI, 5, O); break; case 7: // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... printPredicateOperand(MI, 3, O); break; case 8: // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... printSBitModifierOperand(MI, 6, O); printPredicateOperand(MI, 4, O); break; case 9: // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... printSBitModifierOperand(MI, 7, O); printPredicateOperand(MI, 5, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printSORegRegOperand(MI, 2, O); return; break; case 10: // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC... printOperand(MI, 0, O); break; case 11: // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... printPredicateOperand(MI, 1, O); break; case 12: // BX_RET, ERET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, t2S... printPredicateOperand(MI, 0, O); break; case 13: // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, SMLALBB, SMLALBT, SMLALD, SMLALDX,... printPredicateOperand(MI, 6, O); break; case 14: // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ... printPImmediate(MI, 0, O); SStream_concat0(O, ", "); break; case 15: // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS printCPSIMod(MI, 0, O); break; case 16: // DMB, DSB printMemBOption(MI, 0, O); return; break; case 17: // ISB printInstSyncBOption(MI, 0, O); return; break; case 18: // MRC2 printPImmediate(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, ", "); printCImmediate(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 19: // MRRC2 printPImmediate(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); return; break; case 20: // PLDWi12, PLDi12, PLIi12 printAddrModeImm12Operand(MI, 0, O, false); return; break; case 21: // PLDWrs, PLDrs, PLIrs printAddrMode2Operand(MI, 0, O); return; break; case 22: // SETEND, tSETEND printSetendOperand(MI, 0, O); return; break; case 23: // SMLAL, UMLAL printSBitModifierOperand(MI, 8, O); printPredicateOperand(MI, 6, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 24: // TSB printTraceSyncBOption(MI, 0, O); return; break; case 25: // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... printPredicateOperand(MI, 7, O); break; case 26: // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... printPredicateOperand(MI, 9, O); break; case 27: // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... printPredicateOperand(MI, 11, O); break; case 28: // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... printPredicateOperand(MI, 8, O); break; case 29: // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... printPredicateOperand(MI, 13, O); break; case 30: // VSDOTD, VSDOTDI, VSDOTQ, VSDOTQI, VUDOTD, VUDOTDI, VUDOTQ, VUDOTQI printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); break; case 31: // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... printSBitModifierOperand(MI, 1, O); break; } // Fragment 1 encoded into 7 bits for 75 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 17) & 127)); switch ((Bits >> 17) & 127) { default: // unreachable case 0: // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LS... SStream_concat0(O, " "); break; case 1: // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2... SStream_concat0(O, ".16\t"); ARM_addVectorDataSize(MI, 16); break; case 2: // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2... SStream_concat0(O, ".32\t"); ARM_addVectorDataSize(MI, 32); break; case 3: // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd... SStream_concat0(O, ".8\t"); ARM_addVectorDataSize(MI, 8); break; case 4: // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... SStream_concat0(O, "\t"); break; case 5: // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... SStream_concat0(O, ", "); break; case 6: // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R... return; break; case 7: // BX_RET SStream_concat0(O, "\tlr"); ARM_addReg(MI, ARM_REG_LR); return; break; case 8: // CDP2, MCR2, MCRR2 printOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 9: // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... SStream_concat0(O, ".f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64); printOperand(MI, 0, O); break; case 10: // FCONSTH, VABDhd, VABDhq, VABSH, VABShd, VABShq, VACGEhd, VACGEhq, VACG... SStream_concat0(O, ".f16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F16); printOperand(MI, 0, O); break; case 11: // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfq, VACGEfd, VACGEfq, VACG... SStream_concat0(O, ".f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32); printOperand(MI, 0, O); break; case 12: // FMSTAT SStream_concat0(O, "\tapsr_nzcv, fpscr"); ARM_addReg(MI, ARM_REG_APSR_NZCV); ARM_addReg(MI, ARM_REG_FPSCR); return; break; case 13: // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O... printCImmediate(MI, 1, O); SStream_concat0(O, ", "); break; case 14: // MOVPCLR SStream_concat0(O, "\tpc, lr"); ARM_addReg(MI, ARM_REG_PC); ARM_addReg(MI, ARM_REG_LR); return; break; case 15: // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD SStream_concat0(O, "!"); return; break; case 16: // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i... SStream_concat0(O, ".s32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S32); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 17: // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i... SStream_concat0(O, ".s16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S16); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 18: // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8... SStream_concat0(O, ".s8\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S8); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 19: // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i... SStream_concat0(O, ".u32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U32); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 20: // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i... SStream_concat0(O, ".u16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U16); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 21: // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8... SStream_concat0(O, ".u8\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U8); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 22: // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V... SStream_concat0(O, ".i64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_I64); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 23: // VADDHNv4i16, VADDv2i32, VADDv4i32, VBICiv2i32, VBICiv4i32, VCEQv2i32, ... SStream_concat0(O, ".i32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_I32); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 24: // VADDHNv8i8, VADDv4i16, VADDv8i16, VBICiv4i16, VBICiv8i16, VCEQv4i16, V... SStream_concat0(O, ".i16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_I16); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 25: // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv... SStream_concat0(O, ".i8\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_I8); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 26: // VCVTBDH, VCVTTDH SStream_concat0(O, ".f16.f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 27: // VCVTBHD, VCVTTHD SStream_concat0(O, ".f64.f16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 28: // VCVTBHS, VCVTTHS, VCVTh2f SStream_concat0(O, ".f32.f16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 29: // VCVTBSH, VCVTTSH, VCVTf2h SStream_concat0(O, ".f16.f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 30: // VCVTDS SStream_concat0(O, ".f64.f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 31: // VCVTSD SStream_concat0(O, ".f32.f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 32: // VCVTf2sd, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSIZS, VTOSLS SStream_concat0(O, ".s32.f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 33: // VCVTf2ud, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUIZS, VTOULS SStream_concat0(O, ".u32.f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 34: // VCVTh2sd, VCVTh2sq, VCVTh2xsd, VCVTh2xsq, VTOSHH SStream_concat0(O, ".s16.f16\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 35: // VCVTh2ud, VCVTh2uq, VCVTh2xud, VCVTh2xuq, VTOUHH SStream_concat0(O, ".u16.f16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 36: // VCVTs2fd, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS SStream_concat0(O, ".f32.s32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 37: // VCVTs2hd, VCVTs2hq, VCVTxs2hd, VCVTxs2hq, VSHTOH SStream_concat0(O, ".f16.s16\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 38: // VCVTu2fd, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS SStream_concat0(O, ".f32.u32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 39: // VCVTu2hd, VCVTu2hq, VCVTxu2hd, VCVTxu2hq, VUHTOH SStream_concat0(O, ".f16.u16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 40: // VEXTq64, VLD1d64, VLD1d64Q, VLD1d64Qwb_fixed, VLD1d64Qwb_register, VLD... SStream_concat0(O, ".64\t"); ARM_addVectorDataSize(MI, 64); break; case 41: // VJCVT, VTOSIRD, VTOSIZD, VTOSLD SStream_concat0(O, ".s32.f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 42: // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... SStream_concat0(O, ".16\t{"); ARM_addVectorDataSize(MI, 16); break; case 43: // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... SStream_concat0(O, ".32\t{"); ARM_addVectorDataSize(MI, 32); break; case 44: // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... SStream_concat0(O, ".8\t{"); ARM_addVectorDataSize(MI, 8); break; case 45: // VMSR SStream_concat0(O, "\tfpscr, "); ARM_addReg(MI, ARM_REG_FPSCR); printOperand(MI, 0, O); return; break; case 46: // VMSR_FPEXC SStream_concat0(O, "\tfpexc, "); ARM_addReg(MI, ARM_REG_FPEXC); printOperand(MI, 0, O); return; break; case 47: // VMSR_FPINST SStream_concat0(O, "\tfpinst, "); ARM_addReg(MI, ARM_REG_FPINST); printOperand(MI, 0, O); return; break; case 48: // VMSR_FPINST2 SStream_concat0(O, "\tfpinst2, "); ARM_addReg(MI, ARM_REG_FPINST2); printOperand(MI, 0, O); return; break; case 49: // VMSR_FPSID SStream_concat0(O, "\tfpsid, "); ARM_addReg(MI, ARM_REG_FPSID); printOperand(MI, 0, O); return; break; case 50: // VMULLp8, VMULpd, VMULpq SStream_concat0(O, ".p8\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_P8); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 51: // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... SStream_concat0(O, ".s64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S64); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 52: // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ... SStream_concat0(O, ".u64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U64); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 53: // VSDOTDI, VSDOTQI, VUDOTDI, VUDOTQI printVectorIndex(MI, 4, O); return; break; case 54: // VSHTOD SStream_concat0(O, ".f64.s16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 55: // VSHTOS SStream_concat0(O, ".f32.s16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 56: // VSITOD, VSLTOD SStream_concat0(O, ".f64.s32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 57: // VSITOH, VSLTOH SStream_concat0(O, ".f16.s32\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 58: // VTOSHD SStream_concat0(O, ".s16.f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 59: // VTOSHS SStream_concat0(O, ".s16.f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 60: // VTOSIRH, VTOSIZH, VTOSLH SStream_concat0(O, ".s32.f16\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 61: // VTOUHD SStream_concat0(O, ".u16.f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 62: // VTOUHS SStream_concat0(O, ".u16.f32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 63: // VTOUIRD, VTOUIZD, VTOULD SStream_concat0(O, ".u32.f64\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 64: // VTOUIRH, VTOUIZH, VTOULH SStream_concat0(O, ".u32.f16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 65: // VUHTOD SStream_concat0(O, ".f64.u16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 66: // VUHTOS SStream_concat0(O, ".f32.u16\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printFBits16(MI, 2, O); return; break; case 67: // VUITOD, VULTOD SStream_concat0(O, ".f64.u32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 68: // VUITOH, VULTOH SStream_concat0(O, ".f16.u32\t"); ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U32); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); break; case 69: // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADR, t2ANDrr, t2ANDrs, ... SStream_concat0(O, ".w\t"); break; case 70: // t2SRSDB, t2SRSIA SStream_concat0(O, "\tsp, "); ARM_addReg(MI, ARM_REG_SP); printOperand(MI, 0, O); return; break; case 71: // t2SRSDB_UPD, t2SRSIA_UPD SStream_concat0(O, "\tsp!, "); ARM_addReg(MI, ARM_REG_SP); printOperand(MI, 0, O); return; break; case 72: // t2SUBS_PC_LR SStream_concat0(O, "\tpc, lr, "); printOperand(MI, 0, O); return; break; case 73: // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... printPredicateOperand(MI, 4, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 74: // tMOVi8, tMVN, tRSB printPredicateOperand(MI, 3, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); break; } // Fragment 2 encoded into 6 bits for 60 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 63)); switch ((Bits >> 24) & 63) { default: // unreachable case 0: // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR... printOperand(MI, 0, O); break; case 1: // ITasm, t2IT printMandatoryPredicateOperand(MI, 0, O); return; break; case 2: // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... printVectorListThreeAllLanes(MI, 0, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); break; case 3: // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... printVectorListThreeSpacedAllLanes(MI, 0, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); break; case 4: // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... printVectorListThree(MI, 0, O); SStream_concat0(O, ", "); break; case 5: // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... printVectorListThreeSpaced(MI, 0, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); break; case 6: // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... printVectorListFourAllLanes(MI, 0, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); break; case 7: // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... printVectorListFourSpacedAllLanes(MI, 0, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); break; case 8: // VLD4dAsm_16, VLD4dAsm_32, VLD4dAsm_8, VLD4dWB_fixed_Asm_16, VLD4dWB_fi... printVectorListFour(MI, 0, O); SStream_concat0(O, ", "); break; case 9: // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... printVectorListFourSpaced(MI, 0, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); break; case 10: // AESD, AESE, MCR2, MCRR2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA1SU1, SHA256... printOperand(MI, 2, O); break; case 11: // AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, FLDM... printOperand(MI, 1, O); break; case 12: // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP... printPImmediate(MI, 0, O); SStream_concat0(O, ", "); break; case 13: // CDP2 printCImmediate(MI, 2, O); SStream_concat0(O, ", "); printCImmediate(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 14: // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS printCPSIFlag(MI, 1, O); break; case 15: // FCONSTD, FCONSTH, FCONSTS, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABS... SStream_concat0(O, ", "); break; case 16: // LDAEXD, LDREXD printGPRPairOperand(MI, 0, O); SStream_concat0(O, ", "); printAddrMode7Operand(MI, 1, O); return; break; case 17: // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET printAddrMode5Operand(MI, 2, O, false); return; break; case 18: // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... printAddrMode7Operand(MI, 2, O); SStream_concat0(O, ", "); break; case 19: // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE printAddrMode5Operand(MI, 2, O, true); SStream_concat0(O, "!"); return; break; case 20: // MRC, t2MRC, t2MRC2 printPImmediate(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, ", "); printCImmediate(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 21: // MRRC, t2MRRC, t2MRRC2 printPImmediate(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); return; break; case 22: // MSR, MSRi, t2MSR_AR, t2MSR_M printMSRMaskOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 23: // MSRbanked, t2MSRbanked printBankedRegOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 24: // VBICiv2i32, VBICiv4i16, VBICiv4i32, VBICiv8i16, VMOVv16i8, VMOVv1i64, ... printNEONModImmOperand(MI, 1, O); return; break; case 25: // VCMPEZD, VCMPEZH, VCMPEZS, VCMPZD, VCMPZH, VCMPZS, tRSB SStream_concat0(O, ", #0"); op_addImm(MI, 0); return; break; case 26: // VCVTf2sd, VCVTf2sq, VCVTf2ud, VCVTf2uq, VCVTh2sd, VCVTh2sq, VCVTh2ud, ... return; break; case 27: // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... printVectorListOneAllLanes(MI, 0, O); SStream_concat0(O, ", "); break; case 28: // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... printVectorListTwoAllLanes(MI, 0, O); SStream_concat0(O, ", "); break; case 29: // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... printVectorListOne(MI, 0, O); SStream_concat0(O, ", "); break; case 30: // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... printVectorListTwo(MI, 0, O); SStream_concat0(O, ", "); break; case 31: // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... printVectorListTwoSpacedAllLanes(MI, 0, O); SStream_concat0(O, ", "); break; case 32: // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... printVectorListTwoSpaced(MI, 0, O); SStream_concat0(O, ", "); break; case 33: // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... printOperand(MI, 4, O); break; case 34: // VST1d16, VST1d32, VST1d64, VST1d8 printVectorListOne(MI, 2, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 0, O); return; break; case 35: // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 printVectorListFour(MI, 2, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 0, O); return; break; case 36: // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... printVectorListFour(MI, 3, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, "!"); return; break; case 37: // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... printVectorListFour(MI, 4, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 38: // VST1d16T, VST1d32T, VST1d64T, VST1d8T printVectorListThree(MI, 2, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 0, O); return; break; case 39: // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed printVectorListThree(MI, 3, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, "!"); return; break; case 40: // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... printVectorListThree(MI, 4, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 41: // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed printVectorListOne(MI, 3, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, "!"); return; break; case 42: // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... printVectorListOne(MI, 4, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 43: // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 printVectorListTwo(MI, 2, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 0, O); return; break; case 44: // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... printVectorListTwo(MI, 3, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, "!"); return; break; case 45: // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... printVectorListTwo(MI, 4, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 46: // VST2b16, VST2b32, VST2b8 printVectorListTwoSpaced(MI, 2, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 0, O); return; break; case 47: // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed printVectorListTwoSpaced(MI, 3, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, "!"); return; break; case 48: // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register printVectorListTwoSpaced(MI, 4, O); SStream_concat0(O, ", "); printAddrMode6Operand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 49: // t2DMB, t2DSB printMemBOption(MI, 0, O); return; break; case 50: // t2ISB printInstSyncBOption(MI, 0, O); return; break; case 51: // t2PLDWi12, t2PLDi12, t2PLIi12 printAddrModeImm12Operand(MI, 0, O, false); return; break; case 52: // t2PLDWi8, t2PLDi8, t2PLIi8 printT2AddrModeImm8Operand(MI, 0, O, false); return; break; case 53: // t2PLDWs, t2PLDs, t2PLIs printT2AddrModeSoRegOperand(MI, 0, O); return; break; case 54: // t2PLDpci, t2PLIpci printThumbLdrLabelOperand(MI, 0, O); return; break; case 55: // t2TBB printAddrModeTBB(MI, 0, O); return; break; case 56: // t2TBH printAddrModeTBH(MI, 0, O); return; break; case 57: // t2TSB printTraceSyncBOption(MI, 0, O); return; break; case 58: // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tORR, tROR, tS... printOperand(MI, 3, O); return; break; case 59: // tPOP, tPUSH printRegisterList(MI, 2, O); return; break; } // Fragment 3 encoded into 5 bits for 30 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 30) & 31)); switch ((Bits >> 30) & 31) { default: // unreachable case 0: // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR... SStream_concat0(O, ", "); break; case 1: // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPqAsm_16, VLD3DUP... return; break; case 2: // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... SStream_concat0(O, "!"); return; break; case 3: // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD3dWB_fixed_Asm_16, VLD3dWB_fi... printAddrMode6Operand(MI, 1, O); break; case 4: // CDP, MCR, MCRR, MSR, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABSH, VAB... printOperand(MI, 1, O); break; case 5: // FCONSTD, FCONSTH, FCONSTS, VMOVv2f32, VMOVv4f32 printFPImmOperand(MI, 1, O); return; break; case 6: // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... SStream_concat0(O, "!, "); printRegisterList(MI, 4, O); break; case 7: // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION printCoprocOptionImm(MI, 3, O); return; break; case 8: // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST printPostIdxImm8s4Operand(MI, 3, O); return; break; case 9: // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,... printCImmediate(MI, 1, O); SStream_concat0(O, ", "); break; case 10: // MRS, t2MRS_AR SStream_concat0(O, ", apsr"); ARM_addReg(MI, ARM_REG_APSR); return; break; case 11: // MRSsys, t2MRSsys_AR SStream_concat0(O, ", spsr"); ARM_addReg(MI, ARM_REG_SPSR); return; break; case 12: // MSRi printModImmOperand(MI, 1, O); return; break; case 13: // VCEQzv16i8, VCEQzv2i32, VCEQzv4i16, VCEQzv4i32, VCEQzv8i16, VCEQzv8i8,... SStream_concat0(O, ", #0"); op_addImm(MI, 0); return; break; case 14: // VCVTf2xsd, VCVTf2xsq, VCVTf2xud, VCVTf2xuq, VCVTh2xsd, VCVTh2xsq, VCVT... printOperand(MI, 2, O); break; case 15: // VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8 printVectorIndex(MI, 2, O); return; break; case 16: // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... printAddrMode6Operand(MI, 2, O); break; case 17: // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... SStream_concat0(O, "["); set_mem_access(MI, true); break; case 18: // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... SStream_concat0(O, "[], "); printOperand(MI, 1, O); SStream_concat0(O, "[], "); printOperand(MI, 2, O); break; case 19: // VMRS SStream_concat0(O, ", fpscr"); ARM_addReg(MI, ARM_REG_FPSCR); return; break; case 20: // VMRS_FPEXC SStream_concat0(O, ", fpexc"); ARM_addReg(MI, ARM_REG_FPEXC); return; break; case 21: // VMRS_FPINST SStream_concat0(O, ", fpinst"); ARM_addReg(MI, ARM_REG_FPINST); return; break; case 22: // VMRS_FPINST2 SStream_concat0(O, ", fpinst2"); ARM_addReg(MI, ARM_REG_FPINST2); return; break; case 23: // VMRS_FPSID SStream_concat0(O, ", fpsid"); ARM_addReg(MI, ARM_REG_FPSID); return; break; case 24: // VMRS_MVFR0 SStream_concat0(O, ", mvfr0"); ARM_addReg(MI, ARM_REG_MVFR0); return; break; case 25: // VMRS_MVFR1 SStream_concat0(O, ", mvfr1"); ARM_addReg(MI, ARM_REG_MVFR1); return; break; case 26: // VMRS_MVFR2 SStream_concat0(O, ", mvfr2"); ARM_addReg(MI, ARM_REG_MVFR2); return; break; case 27: // VSETLNi16, VSETLNi32, VSETLNi8 printVectorIndex(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 28: // VSHTOH, VTOSHH, VTOUHH, VUHTOH printFBits16(MI, 2, O); return; break; case 29: // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS... printFBits32(MI, 2, O); return; break; } // Fragment 4 encoded into 7 bits for 65 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 35) & 127)); switch ((Bits >> 35) & 127) { default: // unreachable case 0: // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2... printOperand(MI, 1, O); break; case 1: // LDRBT_POST, LDRT_POST, STRBT_POST, STRT_POST, LDA, LDAB, LDAEX, LDAEXB... printAddrMode7Operand(MI, 1, O); return; break; case 2: // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... printAddrMode6Operand(MI, 2, O); break; case 3: // VLD3DUPdWB_register_Asm_16, VLD3DUPdWB_register_Asm_32, VLD3DUPdWB_reg... printOperand(MI, 3, O); break; case 4: // VLD3dAsm_16, VLD3dAsm_32, VLD3dAsm_8, VLD4dAsm_16, VLD4dAsm_32, VLD4dA... return; break; case 5: // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d... SStream_concat0(O, "!"); return; break; case 6: // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... SStream_concat0(O, ", "); break; case 7: // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs printT2SOOperand(MI, 1, O); return; break; case 8: // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr printSORegRegOperand(MI, 1, O); return; break; case 9: // ADR, t2ADR printAdrLabelOperand(MI, 1, O, 0); return; break; case 10: // BFC, t2BFC printBitfieldInvMaskImmOperand(MI, 2, O); return; break; case 11: // BFI, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, MOVTi16... printOperand(MI, 2, O); break; case 12: // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri printModImmOperand(MI, 1, O); return; break; case 13: // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi printSORegImmOperand(MI, 1, O); return; break; case 14: // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... printRegisterList(MI, 3, O); break; case 15: // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... printAddrMode5Operand(MI, 2, O, false); return; break; case 16: // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... printAddrMode7Operand(MI, 2, O); break; case 17: // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... printAddrMode5Operand(MI, 2, O, true); SStream_concat0(O, "!"); return; break; case 18: // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM printAddrModeImm12Operand(MI, 2, O, true); SStream_concat0(O, "!"); return; break; case 19: // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG printAddrMode2Operand(MI, 2, O); SStream_concat0(O, "!"); return; break; case 20: // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... printAddrModeImm12Operand(MI, 1, O, false); return; break; case 21: // LDRBrs, LDRrs, STRBrs, STRrs printAddrMode2Operand(MI, 1, O); return; break; case 22: // LDRH, LDRSB, LDRSH, STRH printAddrMode3Operand(MI, 1, O, false); return; break; case 23: // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE printAddrMode3Operand(MI, 2, O, true); SStream_concat0(O, "!"); return; break; case 24: // MCR2 printCImmediate(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 25: // MRSbanked, t2MRSbanked printBankedRegOperand(MI, 1, O); return; break; case 26: // SSAT, SSAT16, t2SSAT, t2SSAT16 printImmPlusOneOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); break; case 27: // STLEXD, STREXD printGPRPairOperand(MI, 1, O); SStream_concat0(O, ", "); printAddrMode7Operand(MI, 2, O); return; break; case 28: // VCEQzv2f32, VCEQzv4f16, VCEQzv4f32, VCEQzv8f16, VCGEzv2f32, VCGEzv4f16... SStream_concat0(O, ", #0"); op_addImm(MI, 0); return; break; case 29: // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... printNoHashImmediate(MI, 4, O); break; case 30: // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... printNoHashImmediate(MI, 6, O); break; case 31: // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... printNoHashImmediate(MI, 8, O); SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 32: // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... SStream_concat0(O, "[]}, "); break; case 33: // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... printNoHashImmediate(MI, 10, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 1, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 10, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 2, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 10, O); break; case 34: // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... SStream_concat0(O, "[], "); printOperand(MI, 3, O); SStream_concat0(O, "[]}, "); break; case 35: // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... printNoHashImmediate(MI, 12, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 1, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 12, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 2, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 12, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 3, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 12, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 5, O); printAddrMode6OffsetOperand(MI, 7, O); return; break; case 36: // VLDRD, VLDRS, VSTRD, VSTRS printAddrMode5Operand(MI, 1, O, false); return; break; case 37: // VLDRH, VSTRH printAddrMode5FP16Operand(MI, 1, O, false); return; break; case 38: // VST1LNd16, VST1LNd32, VST1LNd8 printNoHashImmediate(MI, 3, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 0, O); return; break; case 39: // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... printNoHashImmediate(MI, 5, O); break; case 40: // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... printNoHashImmediate(MI, 7, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 5, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 7, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 6, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 7, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 1, O); printAddrMode6OffsetOperand(MI, 3, O); return; break; case 41: // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... printOperand(MI, 5, O); SStream_concat0(O, ", "); printOperand(MI, 6, O); break; case 42: // VTBL1 printVectorListOne(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 43: // VTBL2 printVectorListTwo(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 44: // VTBL3 printVectorListThree(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 45: // VTBL4 printVectorListFour(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 46: // VTBX1 printVectorListOne(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 47: // VTBX2 printVectorListTwo(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 48: // VTBX3 printVectorListThree(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 49: // VTBX4 printVectorListFour(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 50: // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... SStream_concat0(O, " ^"); ARM_addUserMode(MI); return; break; case 51: // t2LDRBT, t2LDRBi8, t2LDRHT, t2LDRHi8, t2LDRSBT, t2LDRSBi8, t2LDRSHT, t... printT2AddrModeImm8Operand(MI, 1, O, false); return; break; case 52: // t2LDRB_PRE, t2LDRH_PRE, t2LDRSB_PRE, t2LDRSH_PRE, t2LDR_PRE, t2STRB_PR... printT2AddrModeImm8Operand(MI, 2, O, true); SStream_concat0(O, "!"); return; break; case 53: // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci printThumbLdrLabelOperand(MI, 1, O); return; break; case 54: // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs printT2AddrModeSoRegOperand(MI, 1, O); return; break; case 55: // t2LDREX printT2AddrModeImm0_1020s4Operand(MI, 1, O); return; break; case 56: // t2MRS_M printMSRMaskOperand(MI, 1, O); return; break; case 57: // tADDspi, tSUBspi printThumbS4ImmOperand(MI, 2, O); return; break; case 58: // tADR printAdrLabelOperand(MI, 1, O, 2); return; break; case 59: // tASRri, tLSRri printThumbSRImm(MI, 3, O); return; break; case 60: // tLDRBi, tSTRBi printThumbAddrModeImm5S1Operand(MI, 1, O); return; break; case 61: // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr printThumbAddrModeRROperand(MI, 1, O); return; break; case 62: // tLDRHi, tSTRHi printThumbAddrModeImm5S2Operand(MI, 1, O); return; break; case 63: // tLDRi, tSTRi printThumbAddrModeImm5S4Operand(MI, 1, O); return; break; case 64: // tLDRspi, tSTRspi printThumbAddrModeSPOperand(MI, 1, O); return; break; } // Fragment 5 encoded into 5 bits for 23 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 31)); switch ((Bits >> 42) & 31) { default: // unreachable case 0: // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... SStream_concat0(O, ", "); break; case 1: // LDRConstPool, RRXi, VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD2LN... return; break; case 2: // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... SStream_concat0(O, "!"); return; break; case 3: // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... printOperand(MI, 3, O); break; case 4: // CDP, t2CDP, t2CDP2 printCImmediate(MI, 2, O); SStream_concat0(O, ", "); printCImmediate(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 5: // MCR, MCRR, VABDfd, VABDfq, VABDhd, VABDhq, VACGEfd, VACGEfq, VACGEhd, ... printOperand(MI, 2, O); break; case 6: // SSAT, t2SSAT printShiftImmOperand(MI, 3, O); return; break; case 7: // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... printRotImmOperand(MI, 2, O); return; break; case 8: // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... printVectorIndex(MI, 4, O); break; case 9: // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q, VGETLN... printVectorIndex(MI, 2, O); return; break; case 10: // VLD1DUPd16wb_register, VLD1DUPd32wb_register, VLD1DUPd8wb_register, VL... printOperand(MI, 4, O); return; break; case 11: // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... SStream_concat0(O, "]}, "); set_mem_access(MI, false); break; case 12: // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 13: // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... printOperand(MI, 1, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 8, O); break; case 14: // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 printAddrMode6Operand(MI, 3, O); return; break; case 15: // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... printAddrMode6Operand(MI, 4, O); break; case 16: // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... printAddrMode6Operand(MI, 5, O); printAddrMode6OffsetOperand(MI, 7, O); return; break; case 17: // VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4i16, VMULslv2i3... printVectorIndex(MI, 3, O); return; break; case 18: // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... SStream_concat0(O, "}, "); printAddrMode6Operand(MI, 1, O); printAddrMode6OffsetOperand(MI, 3, O); return; break; case 19: // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... printOperand(MI, 5, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 8, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 6, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 8, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 7, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 8, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 1, O); printAddrMode6OffsetOperand(MI, 3, O); return; break; case 20: // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... SStream_concat0(O, " ^"); ARM_addUserMode(MI); return; break; case 21: // t2LDRB_POST, t2LDRH_POST, t2LDRSB_POST, t2LDRSH_POST, t2LDR_POST, t2ST... printT2AddrModeImm8OffsetOperand(MI, 3, O); return; break; case 22: // t2MOVsra_flag, t2MOVsrl_flag SStream_concat0(O, ", #1"); op_addImm(MI, 1); return; break; } // Fragment 6 encoded into 6 bits for 38 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 63)); switch ((Bits >> 47) & 63) { default: // unreachable case 0: // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B... printOperand(MI, 2, O); break; case 1: // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... printOperand(MI, 4, O); break; case 2: // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm... return; break; case 3: // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri printModImmOperand(MI, 2, O); return; break; case 4: // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... printSORegImmOperand(MI, 2, O); return; break; case 5: // BFI, t2BFI printBitfieldInvMaskImmOperand(MI, 3, O); return; break; case 6: // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... printCoprocOptionImm(MI, 3, O); return; break; case 7: // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... printPostIdxImm8s4Operand(MI, 3, O); return; break; case 8: // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... printAddrMode2OffsetOperand(MI, 3, O); return; break; case 9: // LDRD, STRD printAddrMode3Operand(MI, 2, O, false); return; break; case 10: // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST printAddrMode7Operand(MI, 3, O); break; case 11: // LDRD_PRE, STRD_PRE printAddrMode3Operand(MI, 3, O, true); SStream_concat0(O, "!"); return; break; case 12: // LDRHTi, LDRSBTi, LDRSHTi, STRHTi printPostIdxImm8Operand(MI, 3, O); return; break; case 13: // LDRHTr, LDRSBTr, LDRSHTr, STRHTr printPostIdxRegOperand(MI, 3, O); return; break; case 14: // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST printAddrMode3OffsetOperand(MI, 3, O); return; break; case 15: // MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed,... SStream_concat0(O, ", "); break; case 16: // MCRR2 printCImmediate(MI, 4, O); return; break; case 17: // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... printAddrMode7Operand(MI, 2, O); return; break; case 18: // VBIFd, VBIFq, VBITd, VBITq, VBSLd, VBSLq, VLD4LNd16, VLD4LNd32, VLD4LN... printOperand(MI, 3, O); break; case 19: // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16 printComplexRotationOp(MI, 3, O, 180, 90); return; break; case 20: // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16 printComplexRotationOp(MI, 4, O, 90, 0); return; break; case 21: // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... printAddrMode6Operand(MI, 1, O); break; case 22: // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD printAddrMode6Operand(MI, 2, O); printAddrMode6OffsetOperand(MI, 4, O); return; break; case 23: // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 printOperand(MI, 1, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 6, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 2, O); return; break; case 24: // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 3, O); printAddrMode6OffsetOperand(MI, 5, O); return; break; case 25: // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... printAddrMode6OffsetOperand(MI, 6, O); return; break; case 26: // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 2, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 8, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 3, O); return; break; case 27: // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... printAddrMode6Operand(MI, 4, O); printAddrMode6OffsetOperand(MI, 6, O); return; break; case 28: // VMLAslfd, VMLAslfq, VMLAslhd, VMLAslhq, VMLSslfd, VMLSslfq, VMLSslhd, ... printVectorIndex(MI, 4, O); return; break; case 29: // VMULslfd, VMULslfq, VMULslhd, VMULslhq printVectorIndex(MI, 3, O); return; break; case 30: // VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8_UPD, VST2LNq16_UPD, VST2LNq32_U... printOperand(MI, 5, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 6, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 1, O); printAddrMode6OffsetOperand(MI, 3, O); return; break; case 31: // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... printOperand(MI, 7, O); SStream_concat0(O, "}, "); printAddrMode6Operand(MI, 1, O); printAddrMode6OffsetOperand(MI, 3, O); return; break; case 32: // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... printT2SOOperand(MI, 2, O); return; break; case 33: // t2ASRri, t2LSRri printThumbSRImm(MI, 2, O); return; break; case 34: // t2LDRD_PRE, t2STRD_PRE printT2AddrModeImm8s4Operand(MI, 3, O, true); SStream_concat0(O, "!"); return; break; case 35: // t2LDRDi8, t2STRDi8 printT2AddrModeImm8s4Operand(MI, 2, O, false); return; break; case 36: // t2STREX printT2AddrModeImm0_1020s4Operand(MI, 2, O); return; break; case 37: // tADDrSPi printThumbS4ImmOperand(MI, 2, O); return; break; } // Fragment 7 encoded into 4 bits for 13 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 53) & 15)); switch ((Bits >> 53) & 15) { default: // unreachable case 0: // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm... return; break; case 1: // LDRD_POST, MLA, MLS, SBFX, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SML... SStream_concat0(O, ", "); break; case 2: // MCR, t2MCR, t2MCR2 printCImmediate(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 3: // MCRR, t2MCRR, t2MCRR2 printOperand(MI, 3, O); SStream_concat0(O, ", "); printCImmediate(MI, 4, O); return; break; case 4: // PKHBT, t2PKHBT printPKHLSLShiftImm(MI, 3, O); return; break; case 5: // PKHTB, t2PKHTB printPKHASRShiftImm(MI, 3, O); return; break; case 6: // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... printRotImmOperand(MI, 3, O); return; break; case 7: // USAT, t2USAT printShiftImmOperand(MI, 3, O); return; break; case 8: // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16... printComplexRotationOp(MI, 5, O, 90, 0); return; break; case 9: // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... SStream_concat0(O, "}, "); break; case 10: // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... SStream_concat0(O, "["); set_mem_access(MI, true); break; case 11: // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD printAddrMode6OffsetOperand(MI, 3, O); return; break; case 12: // t2LDRD_POST, t2STRD_POST printT2AddrModeImm8s4OffsetOperand(MI, 4, O); return; break; } // Fragment 8 encoded into 4 bits for 12 unique commands. // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 57) & 15)); switch ((Bits >> 57) & 15) { default: // unreachable case 0: // LDRD_POST, STRD_POST printAddrMode3OffsetOperand(MI, 4, O); return; break; case 1: // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... printOperand(MI, 3, O); break; case 2: // SBFX, UBFX, t2SBFX, t2UBFX printImmPlusOneOperand(MI, 3, O); return; break; case 3: // VLD3d16, VLD3d32, VLD3d8, VLD3q16, VLD3q32, VLD3q8 printAddrMode6Operand(MI, 3, O); return; break; case 4: // VLD3d16_UPD, VLD3d32_UPD, VLD3d8_UPD, VLD3q16_UPD, VLD3q32_UPD, VLD3q8... printAddrMode6Operand(MI, 4, O); printAddrMode6OffsetOperand(MI, 6, O); return; break; case 5: // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32 printNoHashImmediate(MI, 10, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 4, O); return; break; case 6: // VST2LNd16, VST2LNd32, VST2LNd8, VST2LNq16, VST2LNq32 printNoHashImmediate(MI, 4, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 0, O); return; break; case 7: // VST3LNd16, VST3LNd32, VST3LNd8, VST3LNq16, VST3LNq32 printNoHashImmediate(MI, 5, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 4, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 5, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 0, O); return; break; case 8: // VST3d16, VST3d32, VST3d8, VST3q16, VST3q32, VST3q8 printAddrMode6Operand(MI, 0, O); return; break; case 9: // VST4LNd16, VST4LNd32, VST4LNd8, VST4LNq16, VST4LNq32 printNoHashImmediate(MI, 6, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 4, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 6, O); SStream_concat0(O, "], "); set_mem_access(MI, false); printOperand(MI, 5, O); SStream_concat0(O, "["); set_mem_access(MI, true); printNoHashImmediate(MI, 6, O); SStream_concat0(O, "]}, "); set_mem_access(MI, false); printAddrMode6Operand(MI, 0, O); return; break; case 10: // VST4d16, VST4d32, VST4d8, VST4q16, VST4q32, VST4q8 printOperand(MI, 5, O); SStream_concat0(O, "}, "); printAddrMode6Operand(MI, 0, O); return; break; case 11: // t2STLEXD, t2STREXD printAddrMode7Operand(MI, 3, O); return; break; } // Fragment 9 encoded into 1 bits for 2 unique commands. // printf("Fragment 9: %"PRIu64"\n", ((Bits >> 61) & 1)); if ((Bits >> 61) & 1) { // VLD4d16, VLD4d16_UPD, VLD4d32, VLD4d32_UPD, VLD4d8, VLD4d8_UPD, VLD4q1... SStream_concat0(O, "}, "); } else { // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... return; } // Fragment 10 encoded into 1 bits for 2 unique commands. // printf("Fragment 10: %"PRIu64"\n", ((Bits >> 62) & 1)); if ((Bits >> 62) & 1) { // VLD4d16_UPD, VLD4d32_UPD, VLD4d8_UPD, VLD4q16_UPD, VLD4q32_UPD, VLD4q8... printAddrMode6Operand(MI, 5, O); printAddrMode6OffsetOperand(MI, 7, O); return; } else { // VLD4d16, VLD4d32, VLD4d8, VLD4q16, VLD4q32, VLD4q8 printAddrMode6Operand(MI, 4, O); return; } } #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static bool printAliasInstr(MCInst *MI, SStream *OS) { unsigned int I = 0, OpIdx, PrintMethodIdx; char *tmpString; const char *AsmString; switch (MCInst_getOpcode(MI)) { default: return false; case ARM_DSB: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) { // (DSB 12) AsmString = "dfb"; break; } return false; case ARM_HINT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { // (HINT 0, pred:$p) AsmString = "nop$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { // (HINT 1, pred:$p) AsmString = "yield$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { // (HINT 2, pred:$p) AsmString = "wfe$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { // (HINT 3, pred:$p) AsmString = "wfi$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { // (HINT 4, pred:$p) AsmString = "sev$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { // (HINT 5, pred:$p) AsmString = "sevl$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) { // (HINT 16, pred:$p) AsmString = "esb$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 && !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) { // (HINT 20, pred:$p) AsmString = "csdb$\xFF\x02\x01"; break; } return false; case ARM_t2DSB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) { // (t2DSB 12, pred:$p) AsmString = "dfb$\xFF\x02\x01"; break; } return false; case ARM_t2HINT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { // (t2HINT 0, pred:$p) AsmString = "nop$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { // (t2HINT 1, pred:$p) AsmString = "yield$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { // (t2HINT 2, pred:$p) AsmString = "wfe$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { // (t2HINT 3, pred:$p) AsmString = "wfi$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { // (t2HINT 4, pred:$p) AsmString = "sev$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { // (t2HINT 5, pred:$p) AsmString = "sevl$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) { // (t2HINT 16, pred:$p) AsmString = "esb$\xFF\x02\x01.w"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) { // (t2HINT 20, pred:$p) AsmString = "csdb$\xFF\x02\x01"; break; } return false; case ARM_t2SUBS_PC_LR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)) { // (t2SUBS_PC_LR 0, pred:$p) AsmString = "eret$\xFF\x02\x01"; break; } return false; case ARM_tHINT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { // (tHINT 0, pred:$p) AsmString = "nop$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { // (tHINT 1, pred:$p) AsmString = "yield$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { // (tHINT 2, pred:$p) AsmString = "wfe$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { // (tHINT 3, pred:$p) AsmString = "wfi$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) { // (tHINT 4, pred:$p) AsmString = "sev$\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) { // (tHINT 5, pred:$p) AsmString = "sevl$\xFF\x02\x01"; break; } return false; } tmpString = cs_strdup(AsmString); while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && AsmString[I] != '\0') ++I; tmpString[I] = 0; SStream_concat0(OS, tmpString); cs_mem_free(tmpString); if (AsmString[I] != '\0') { if (AsmString[I] == ' ' || AsmString[I] == '\t') { SStream_concat0(OS, " "); ++I; } do { if (AsmString[I] == '$') { ++I; if (AsmString[I] == (char)0xff) { ++I; OpIdx = AsmString[I++] - 1; PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } else { if (AsmString[I] == '[') { set_mem_access(MI, true); } else if (AsmString[I] == ']') { set_mem_access(MI, false); } SStream_concat1(OS, AsmString[I++]); } } while (AsmString[I] != '\0'); } return true; } static void printCustomAliasOperand( MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: break; case 0: printPredicateOperand(MI, OpIdx, OS); break; } } #endif // PRINT_ALIAS_INSTR capstone-sys-0.15.0/capstone/arch/ARM/ARMGenDisassemblerTables.inc000064400000000000000000034510140072674642500230040ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /* Automatically generated file, do not edit! */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. //#if defined(_MSC_VER) && !defined(__clang__) //__declspec(noinline) //#endif #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTableARM32[] = { /* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ... /* 3 */ MCD_OPC_FilterValue, 0, 47, 14, 0, // Skip to: 3639 /* 8 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 11 */ MCD_OPC_FilterValue, 0, 110, 7, 0, // Skip to: 1918 /* 16 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 19 */ MCD_OPC_FilterValue, 0, 139, 1, 0, // Skip to: 419 /* 24 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 27 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 155 /* 32 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 35 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 65 /* 40 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 56 /* 45 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 56 /* 52 */ MCD_OPC_Decode, 159, 4, 0, // Opcode: ANDrr /* 56 */ MCD_OPC_CheckPredicate, 0, 92, 32, 0, // Skip to: 8345 /* 61 */ MCD_OPC_Decode, 160, 4, 1, // Opcode: ANDrsi /* 65 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 95 /* 70 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 86 /* 75 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 86 /* 82 */ MCD_OPC_Decode, 245, 6, 0, // Opcode: SUBrr /* 86 */ MCD_OPC_CheckPredicate, 0, 62, 32, 0, // Skip to: 8345 /* 91 */ MCD_OPC_Decode, 246, 6, 1, // Opcode: SUBrsi /* 95 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 125 /* 100 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 116 /* 105 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 116 /* 112 */ MCD_OPC_Decode, 150, 4, 0, // Opcode: ADDrr /* 116 */ MCD_OPC_CheckPredicate, 0, 32, 32, 0, // Skip to: 8345 /* 121 */ MCD_OPC_Decode, 151, 4, 1, // Opcode: ADDrsi /* 125 */ MCD_OPC_FilterValue, 3, 23, 32, 0, // Skip to: 8345 /* 130 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 146 /* 135 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 146 /* 142 */ MCD_OPC_Decode, 239, 5, 0, // Opcode: SBCrr /* 146 */ MCD_OPC_CheckPredicate, 0, 2, 32, 0, // Skip to: 8345 /* 151 */ MCD_OPC_Decode, 240, 5, 1, // Opcode: SBCrsi /* 155 */ MCD_OPC_FilterValue, 1, 249, 31, 0, // Skip to: 8345 /* 160 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 163 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 227 /* 168 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 185 /* 176 */ MCD_OPC_CheckPredicate, 0, 228, 31, 0, // Skip to: 8345 /* 181 */ MCD_OPC_Decode, 161, 4, 2, // Opcode: ANDrsr /* 185 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 199 /* 190 */ MCD_OPC_CheckPredicate, 0, 214, 31, 0, // Skip to: 8345 /* 195 */ MCD_OPC_Decode, 247, 6, 2, // Opcode: SUBrsr /* 199 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 213 /* 204 */ MCD_OPC_CheckPredicate, 0, 200, 31, 0, // Skip to: 8345 /* 209 */ MCD_OPC_Decode, 152, 4, 2, // Opcode: ADDrsr /* 213 */ MCD_OPC_FilterValue, 3, 191, 31, 0, // Skip to: 8345 /* 218 */ MCD_OPC_CheckPredicate, 0, 186, 31, 0, // Skip to: 8345 /* 223 */ MCD_OPC_Decode, 241, 5, 3, // Opcode: SBCrsr /* 227 */ MCD_OPC_FilterValue, 1, 177, 31, 0, // Skip to: 8345 /* 232 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 235 */ MCD_OPC_FilterValue, 0, 71, 0, 0, // Skip to: 311 /* 240 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 243 */ MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 262 /* 248 */ MCD_OPC_CheckPredicate, 1, 156, 31, 0, // Skip to: 8345 /* 253 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 258 */ MCD_OPC_Decode, 188, 5, 4, // Opcode: MUL /* 262 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 283 /* 267 */ MCD_OPC_CheckPredicate, 1, 137, 31, 0, // Skip to: 8345 /* 272 */ MCD_OPC_CheckField, 20, 1, 0, 130, 31, 0, // Skip to: 8345 /* 279 */ MCD_OPC_Decode, 152, 7, 5, // Opcode: UMAAL /* 283 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 297 /* 288 */ MCD_OPC_CheckPredicate, 1, 116, 31, 0, // Skip to: 8345 /* 293 */ MCD_OPC_Decode, 154, 7, 6, // Opcode: UMULL /* 297 */ MCD_OPC_FilterValue, 3, 107, 31, 0, // Skip to: 8345 /* 302 */ MCD_OPC_CheckPredicate, 1, 102, 31, 0, // Skip to: 8345 /* 307 */ MCD_OPC_Decode, 165, 6, 6, // Opcode: SMULL /* 311 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 347 /* 316 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 319 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 333 /* 324 */ MCD_OPC_CheckPredicate, 0, 80, 31, 0, // Skip to: 8345 /* 329 */ MCD_OPC_Decode, 234, 6, 7, // Opcode: STRH_POST /* 333 */ MCD_OPC_FilterValue, 1, 71, 31, 0, // Skip to: 8345 /* 338 */ MCD_OPC_CheckPredicate, 0, 66, 31, 0, // Skip to: 8345 /* 343 */ MCD_OPC_Decode, 143, 5, 7, // Opcode: LDRH_POST /* 347 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 383 /* 352 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 355 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 369 /* 360 */ MCD_OPC_CheckPredicate, 0, 44, 31, 0, // Skip to: 8345 /* 365 */ MCD_OPC_Decode, 134, 5, 7, // Opcode: LDRD_POST /* 369 */ MCD_OPC_FilterValue, 1, 35, 31, 0, // Skip to: 8345 /* 374 */ MCD_OPC_CheckPredicate, 0, 30, 31, 0, // Skip to: 8345 /* 379 */ MCD_OPC_Decode, 148, 5, 7, // Opcode: LDRSB_POST /* 383 */ MCD_OPC_FilterValue, 3, 21, 31, 0, // Skip to: 8345 /* 388 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 391 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 405 /* 396 */ MCD_OPC_CheckPredicate, 0, 8, 31, 0, // Skip to: 8345 /* 401 */ MCD_OPC_Decode, 225, 6, 7, // Opcode: STRD_POST /* 405 */ MCD_OPC_FilterValue, 1, 255, 30, 0, // Skip to: 8345 /* 410 */ MCD_OPC_CheckPredicate, 0, 250, 30, 0, // Skip to: 8345 /* 415 */ MCD_OPC_Decode, 153, 5, 7, // Opcode: LDRSH_POST /* 419 */ MCD_OPC_FilterValue, 1, 241, 30, 0, // Skip to: 8345 /* 424 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 427 */ MCD_OPC_FilterValue, 0, 6, 2, 0, // Skip to: 950 /* 432 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 435 */ MCD_OPC_FilterValue, 0, 152, 1, 0, // Skip to: 848 /* 440 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 443 */ MCD_OPC_FilterValue, 0, 66, 1, 0, // Skip to: 770 /* 448 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... /* 451 */ MCD_OPC_FilterValue, 14, 67, 0, 0, // Skip to: 523 /* 456 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 459 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 491 /* 464 */ MCD_OPC_CheckPredicate, 2, 171, 0, 0, // Skip to: 640 /* 469 */ MCD_OPC_CheckField, 6, 2, 1, 164, 0, 0, // Skip to: 640 /* 476 */ MCD_OPC_CheckField, 4, 1, 0, 157, 0, 0, // Skip to: 640 /* 483 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, /* 487 */ MCD_OPC_Decode, 194, 4, 8, // Opcode: CRC32B /* 491 */ MCD_OPC_FilterValue, 1, 144, 0, 0, // Skip to: 640 /* 496 */ MCD_OPC_CheckPredicate, 2, 139, 0, 0, // Skip to: 640 /* 501 */ MCD_OPC_CheckField, 6, 2, 1, 132, 0, 0, // Skip to: 640 /* 508 */ MCD_OPC_CheckField, 4, 1, 0, 125, 0, 0, // Skip to: 640 /* 515 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, /* 519 */ MCD_OPC_Decode, 195, 4, 8, // Opcode: CRC32CB /* 523 */ MCD_OPC_FilterValue, 15, 112, 0, 0, // Skip to: 640 /* 528 */ MCD_OPC_ExtractField, 10, 8, // Inst{17-10} ... /* 531 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 559 /* 536 */ MCD_OPC_CheckPredicate, 0, 99, 0, 0, // Skip to: 640 /* 541 */ MCD_OPC_CheckField, 9, 1, 0, 92, 0, 0, // Skip to: 640 /* 548 */ MCD_OPC_CheckField, 0, 5, 0, 85, 0, 0, // Skip to: 640 /* 555 */ MCD_OPC_Decode, 192, 4, 9, // Opcode: CPS2p /* 559 */ MCD_OPC_FilterValue, 64, 30, 0, 0, // Skip to: 594 /* 564 */ MCD_OPC_CheckPredicate, 0, 71, 0, 0, // Skip to: 640 /* 569 */ MCD_OPC_CheckField, 18, 2, 0, 64, 0, 0, // Skip to: 640 /* 576 */ MCD_OPC_CheckField, 6, 3, 0, 57, 0, 0, // Skip to: 640 /* 583 */ MCD_OPC_CheckField, 0, 5, 0, 50, 0, 0, // Skip to: 640 /* 590 */ MCD_OPC_Decode, 245, 5, 10, // Opcode: SETEND /* 594 */ MCD_OPC_FilterValue, 128, 1, 40, 0, 0, // Skip to: 640 /* 600 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 603 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 640 /* 608 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 631 /* 613 */ MCD_OPC_CheckField, 18, 2, 0, 11, 0, 0, // Skip to: 631 /* 620 */ MCD_OPC_CheckField, 6, 3, 0, 4, 0, 0, // Skip to: 631 /* 627 */ MCD_OPC_Decode, 191, 4, 9, // Opcode: CPS1p /* 631 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 640 /* 636 */ MCD_OPC_Decode, 193, 4, 9, // Opcode: CPS3p /* 640 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 643 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 684 /* 648 */ MCD_OPC_CheckPredicate, 0, 88, 4, 0, // Skip to: 1765 /* 653 */ MCD_OPC_CheckField, 16, 1, 1, 81, 4, 0, // Skip to: 1765 /* 660 */ MCD_OPC_CheckField, 9, 1, 0, 74, 4, 0, // Skip to: 1765 /* 667 */ MCD_OPC_CheckField, 4, 1, 0, 67, 4, 0, // Skip to: 1765 /* 674 */ MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 56 /* 0xe0000 */, /* 680 */ MCD_OPC_Decode, 182, 5, 11, // Opcode: MRS /* 684 */ MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 709 /* 689 */ MCD_OPC_CheckPredicate, 0, 47, 4, 0, // Skip to: 1765 /* 694 */ MCD_OPC_CheckField, 4, 1, 1, 40, 4, 0, // Skip to: 1765 /* 701 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 705 */ MCD_OPC_Decode, 205, 5, 12, // Opcode: QADD /* 709 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 749 /* 714 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 717 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 731 /* 722 */ MCD_OPC_CheckPredicate, 3, 14, 4, 0, // Skip to: 1765 /* 727 */ MCD_OPC_Decode, 136, 6, 13, // Opcode: SMLABB /* 731 */ MCD_OPC_FilterValue, 1, 5, 4, 0, // Skip to: 1765 /* 736 */ MCD_OPC_CheckPredicate, 4, 0, 4, 0, // Skip to: 1765 /* 741 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 745 */ MCD_OPC_Decode, 249, 6, 14, // Opcode: SWP /* 749 */ MCD_OPC_FilterValue, 3, 243, 3, 0, // Skip to: 1765 /* 754 */ MCD_OPC_CheckPredicate, 3, 238, 3, 0, // Skip to: 1765 /* 759 */ MCD_OPC_CheckField, 4, 1, 0, 231, 3, 0, // Skip to: 1765 /* 766 */ MCD_OPC_Decode, 137, 6, 13, // Opcode: SMLABT /* 770 */ MCD_OPC_FilterValue, 1, 222, 3, 0, // Skip to: 1765 /* 775 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 778 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 806 /* 783 */ MCD_OPC_CheckPredicate, 5, 209, 3, 0, // Skip to: 1765 /* 788 */ MCD_OPC_CheckField, 28, 4, 14, 202, 3, 0, // Skip to: 1765 /* 795 */ MCD_OPC_CheckField, 4, 1, 1, 195, 3, 0, // Skip to: 1765 /* 802 */ MCD_OPC_Decode, 219, 4, 15, // Opcode: HLT /* 806 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 827 /* 811 */ MCD_OPC_CheckPredicate, 3, 181, 3, 0, // Skip to: 1765 /* 816 */ MCD_OPC_CheckField, 4, 1, 0, 174, 3, 0, // Skip to: 1765 /* 823 */ MCD_OPC_Decode, 147, 6, 13, // Opcode: SMLATB /* 827 */ MCD_OPC_FilterValue, 3, 165, 3, 0, // Skip to: 1765 /* 832 */ MCD_OPC_CheckPredicate, 3, 160, 3, 0, // Skip to: 1765 /* 837 */ MCD_OPC_CheckField, 4, 1, 0, 153, 3, 0, // Skip to: 1765 /* 844 */ MCD_OPC_Decode, 148, 6, 13, // Opcode: SMLATT /* 848 */ MCD_OPC_FilterValue, 1, 144, 3, 0, // Skip to: 1765 /* 853 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 856 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 924 /* 861 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 882 /* 866 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 882 /* 873 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 878 */ MCD_OPC_Decode, 137, 7, 16, // Opcode: TSTrr /* 882 */ MCD_OPC_CheckPredicate, 6, 23, 0, 0, // Skip to: 910 /* 887 */ MCD_OPC_CheckField, 28, 4, 15, 16, 0, 0, // Skip to: 910 /* 894 */ MCD_OPC_CheckField, 5, 3, 0, 9, 0, 0, // Skip to: 910 /* 901 */ MCD_OPC_SoftFail, 143, 250, 63 /* 0xffd0f */, 0, /* 906 */ MCD_OPC_Decode, 246, 5, 10, // Opcode: SETPAN /* 910 */ MCD_OPC_CheckPredicate, 0, 82, 3, 0, // Skip to: 1765 /* 915 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 920 */ MCD_OPC_Decode, 138, 7, 17, // Opcode: TSTrsi /* 924 */ MCD_OPC_FilterValue, 1, 68, 3, 0, // Skip to: 1765 /* 929 */ MCD_OPC_CheckPredicate, 0, 63, 3, 0, // Skip to: 1765 /* 934 */ MCD_OPC_CheckField, 7, 1, 0, 56, 3, 0, // Skip to: 1765 /* 941 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 946 */ MCD_OPC_Decode, 139, 7, 18, // Opcode: TSTrsr /* 950 */ MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 1273 /* 955 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 958 */ MCD_OPC_FilterValue, 0, 192, 0, 0, // Skip to: 1155 /* 963 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 966 */ MCD_OPC_FilterValue, 0, 144, 0, 0, // Skip to: 1115 /* 971 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 974 */ MCD_OPC_FilterValue, 0, 22, 0, 0, // Skip to: 1001 /* 979 */ MCD_OPC_CheckPredicate, 0, 13, 3, 0, // Skip to: 1765 /* 984 */ MCD_OPC_CheckField, 9, 1, 0, 6, 3, 0, // Skip to: 1765 /* 991 */ MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 60 /* 0xf0000 */, /* 997 */ MCD_OPC_Decode, 184, 5, 11, // Opcode: MRSsys /* 1001 */ MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 1059 /* 1006 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 1009 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 1034 /* 1014 */ MCD_OPC_CheckPredicate, 2, 234, 2, 0, // Skip to: 1765 /* 1019 */ MCD_OPC_CheckField, 28, 4, 14, 227, 2, 0, // Skip to: 1765 /* 1026 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, /* 1030 */ MCD_OPC_Decode, 199, 4, 8, // Opcode: CRC32W /* 1034 */ MCD_OPC_FilterValue, 1, 214, 2, 0, // Skip to: 1765 /* 1039 */ MCD_OPC_CheckPredicate, 2, 209, 2, 0, // Skip to: 1765 /* 1044 */ MCD_OPC_CheckField, 28, 4, 14, 202, 2, 0, // Skip to: 1765 /* 1051 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, /* 1055 */ MCD_OPC_Decode, 197, 4, 8, // Opcode: CRC32CW /* 1059 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1073 /* 1064 */ MCD_OPC_CheckPredicate, 3, 184, 2, 0, // Skip to: 1765 /* 1069 */ MCD_OPC_Decode, 141, 6, 19, // Opcode: SMLALBB /* 1073 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1087 /* 1078 */ MCD_OPC_CheckPredicate, 3, 170, 2, 0, // Skip to: 1765 /* 1083 */ MCD_OPC_Decode, 145, 6, 19, // Opcode: SMLALTB /* 1087 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1101 /* 1092 */ MCD_OPC_CheckPredicate, 3, 156, 2, 0, // Skip to: 1765 /* 1097 */ MCD_OPC_Decode, 142, 6, 19, // Opcode: SMLALBT /* 1101 */ MCD_OPC_FilterValue, 7, 147, 2, 0, // Skip to: 1765 /* 1106 */ MCD_OPC_CheckPredicate, 3, 142, 2, 0, // Skip to: 1765 /* 1111 */ MCD_OPC_Decode, 146, 6, 19, // Opcode: SMLALTT /* 1115 */ MCD_OPC_FilterValue, 1, 133, 2, 0, // Skip to: 1765 /* 1120 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 1141 /* 1125 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 1141 /* 1132 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 1137 */ MCD_OPC_Decode, 188, 4, 20, // Opcode: CMPrr /* 1141 */ MCD_OPC_CheckPredicate, 0, 107, 2, 0, // Skip to: 1765 /* 1146 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 1151 */ MCD_OPC_Decode, 189, 4, 17, // Opcode: CMPrsi /* 1155 */ MCD_OPC_FilterValue, 1, 93, 2, 0, // Skip to: 1765 /* 1160 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1163 */ MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 1241 /* 1168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1171 */ MCD_OPC_FilterValue, 0, 46, 0, 0, // Skip to: 1222 /* 1176 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 1179 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 1197 /* 1184 */ MCD_OPC_CheckPredicate, 0, 64, 2, 0, // Skip to: 1765 /* 1189 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 1193 */ MCD_OPC_Decode, 209, 5, 21, // Opcode: QDADD /* 1197 */ MCD_OPC_FilterValue, 3, 51, 2, 0, // Skip to: 1765 /* 1202 */ MCD_OPC_CheckPredicate, 7, 46, 2, 0, // Skip to: 1765 /* 1207 */ MCD_OPC_SoftFail, 128, 128, 128, 128, 1 /* 0x10000000 */, 128, 128, 128, 128, 14 /* 0xffffffffe0000000 */, /* 1218 */ MCD_OPC_Decode, 220, 4, 15, // Opcode: HVC /* 1222 */ MCD_OPC_FilterValue, 1, 26, 2, 0, // Skip to: 1765 /* 1227 */ MCD_OPC_CheckPredicate, 0, 21, 2, 0, // Skip to: 1765 /* 1232 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 1237 */ MCD_OPC_Decode, 190, 4, 18, // Opcode: CMPrsr /* 1241 */ MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 1765 /* 1246 */ MCD_OPC_CheckPredicate, 4, 2, 2, 0, // Skip to: 1765 /* 1251 */ MCD_OPC_CheckField, 20, 1, 0, 251, 1, 0, // Skip to: 1765 /* 1258 */ MCD_OPC_CheckField, 5, 2, 0, 244, 1, 0, // Skip to: 1765 /* 1265 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 1269 */ MCD_OPC_Decode, 250, 6, 14, // Opcode: SWPB /* 1273 */ MCD_OPC_FilterValue, 2, 241, 0, 0, // Skip to: 1519 /* 1278 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1281 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1311 /* 1286 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1302 /* 1291 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1302 /* 1298 */ MCD_OPC_Decode, 194, 5, 0, // Opcode: ORRrr /* 1302 */ MCD_OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 1765 /* 1307 */ MCD_OPC_Decode, 195, 5, 1, // Opcode: ORRrsi /* 1311 */ MCD_OPC_FilterValue, 1, 193, 1, 0, // Skip to: 1765 /* 1316 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1319 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1333 /* 1324 */ MCD_OPC_CheckPredicate, 0, 180, 1, 0, // Skip to: 1765 /* 1329 */ MCD_OPC_Decode, 196, 5, 2, // Opcode: ORRrsr /* 1333 */ MCD_OPC_FilterValue, 1, 171, 1, 0, // Skip to: 1765 /* 1338 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1341 */ MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1405 /* 1346 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1349 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1377 /* 1354 */ MCD_OPC_CheckPredicate, 8, 150, 1, 0, // Skip to: 1765 /* 1359 */ MCD_OPC_CheckField, 12, 4, 15, 143, 1, 0, // Skip to: 1765 /* 1366 */ MCD_OPC_CheckField, 5, 2, 0, 136, 1, 0, // Skip to: 1765 /* 1373 */ MCD_OPC_Decode, 201, 6, 22, // Opcode: STL /* 1377 */ MCD_OPC_FilterValue, 1, 127, 1, 0, // Skip to: 1765 /* 1382 */ MCD_OPC_CheckPredicate, 8, 122, 1, 0, // Skip to: 1765 /* 1387 */ MCD_OPC_CheckField, 5, 2, 0, 115, 1, 0, // Skip to: 1765 /* 1394 */ MCD_OPC_CheckField, 0, 4, 15, 108, 1, 0, // Skip to: 1765 /* 1401 */ MCD_OPC_Decode, 222, 4, 23, // Opcode: LDA /* 1405 */ MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1462 /* 1410 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1413 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1434 /* 1418 */ MCD_OPC_CheckPredicate, 9, 86, 1, 0, // Skip to: 1765 /* 1423 */ MCD_OPC_CheckField, 5, 2, 0, 79, 1, 0, // Skip to: 1765 /* 1430 */ MCD_OPC_Decode, 203, 6, 24, // Opcode: STLEX /* 1434 */ MCD_OPC_FilterValue, 1, 70, 1, 0, // Skip to: 1765 /* 1439 */ MCD_OPC_CheckPredicate, 9, 65, 1, 0, // Skip to: 1765 /* 1444 */ MCD_OPC_CheckField, 5, 2, 0, 58, 1, 0, // Skip to: 1765 /* 1451 */ MCD_OPC_CheckField, 0, 4, 15, 51, 1, 0, // Skip to: 1765 /* 1458 */ MCD_OPC_Decode, 224, 4, 23, // Opcode: LDAEX /* 1462 */ MCD_OPC_FilterValue, 15, 42, 1, 0, // Skip to: 1765 /* 1467 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1470 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1491 /* 1475 */ MCD_OPC_CheckPredicate, 0, 29, 1, 0, // Skip to: 1765 /* 1480 */ MCD_OPC_CheckField, 5, 2, 0, 22, 1, 0, // Skip to: 1765 /* 1487 */ MCD_OPC_Decode, 227, 6, 24, // Opcode: STREX /* 1491 */ MCD_OPC_FilterValue, 1, 13, 1, 0, // Skip to: 1765 /* 1496 */ MCD_OPC_CheckPredicate, 0, 8, 1, 0, // Skip to: 1765 /* 1501 */ MCD_OPC_CheckField, 5, 2, 0, 1, 1, 0, // Skip to: 1765 /* 1508 */ MCD_OPC_CheckField, 0, 4, 15, 250, 0, 0, // Skip to: 1765 /* 1515 */ MCD_OPC_Decode, 136, 5, 23, // Opcode: LDREX /* 1519 */ MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1765 /* 1524 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1527 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1557 /* 1532 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1548 /* 1537 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1548 /* 1544 */ MCD_OPC_Decode, 165, 4, 0, // Opcode: BICrr /* 1548 */ MCD_OPC_CheckPredicate, 0, 212, 0, 0, // Skip to: 1765 /* 1553 */ MCD_OPC_Decode, 166, 4, 1, // Opcode: BICrsi /* 1557 */ MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 1765 /* 1562 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1565 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1579 /* 1570 */ MCD_OPC_CheckPredicate, 0, 190, 0, 0, // Skip to: 1765 /* 1575 */ MCD_OPC_Decode, 167, 4, 2, // Opcode: BICrsr /* 1579 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1765 /* 1584 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1587 */ MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1651 /* 1592 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1595 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1623 /* 1600 */ MCD_OPC_CheckPredicate, 8, 160, 0, 0, // Skip to: 1765 /* 1605 */ MCD_OPC_CheckField, 12, 4, 15, 153, 0, 0, // Skip to: 1765 /* 1612 */ MCD_OPC_CheckField, 5, 2, 0, 146, 0, 0, // Skip to: 1765 /* 1619 */ MCD_OPC_Decode, 202, 6, 22, // Opcode: STLB /* 1623 */ MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 1765 /* 1628 */ MCD_OPC_CheckPredicate, 8, 132, 0, 0, // Skip to: 1765 /* 1633 */ MCD_OPC_CheckField, 5, 2, 0, 125, 0, 0, // Skip to: 1765 /* 1640 */ MCD_OPC_CheckField, 0, 4, 15, 118, 0, 0, // Skip to: 1765 /* 1647 */ MCD_OPC_Decode, 223, 4, 23, // Opcode: LDAB /* 1651 */ MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1708 /* 1656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1659 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1680 /* 1664 */ MCD_OPC_CheckPredicate, 9, 96, 0, 0, // Skip to: 1765 /* 1669 */ MCD_OPC_CheckField, 5, 2, 0, 89, 0, 0, // Skip to: 1765 /* 1676 */ MCD_OPC_Decode, 204, 6, 24, // Opcode: STLEXB /* 1680 */ MCD_OPC_FilterValue, 1, 80, 0, 0, // Skip to: 1765 /* 1685 */ MCD_OPC_CheckPredicate, 9, 75, 0, 0, // Skip to: 1765 /* 1690 */ MCD_OPC_CheckField, 5, 2, 0, 68, 0, 0, // Skip to: 1765 /* 1697 */ MCD_OPC_CheckField, 0, 4, 15, 61, 0, 0, // Skip to: 1765 /* 1704 */ MCD_OPC_Decode, 225, 4, 23, // Opcode: LDAEXB /* 1708 */ MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 1765 /* 1713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1716 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1737 /* 1721 */ MCD_OPC_CheckPredicate, 0, 39, 0, 0, // Skip to: 1765 /* 1726 */ MCD_OPC_CheckField, 5, 2, 0, 32, 0, 0, // Skip to: 1765 /* 1733 */ MCD_OPC_Decode, 228, 6, 24, // Opcode: STREXB /* 1737 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 1765 /* 1742 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 1765 /* 1747 */ MCD_OPC_CheckField, 5, 2, 0, 11, 0, 0, // Skip to: 1765 /* 1754 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 1765 /* 1761 */ MCD_OPC_Decode, 137, 5, 23, // Opcode: LDREXB /* 1765 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 1768 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 1810 /* 1773 */ MCD_OPC_CheckPredicate, 7, 167, 25, 0, // Skip to: 8345 /* 1778 */ MCD_OPC_CheckField, 23, 1, 0, 160, 25, 0, // Skip to: 8345 /* 1785 */ MCD_OPC_CheckField, 20, 1, 0, 153, 25, 0, // Skip to: 8345 /* 1792 */ MCD_OPC_CheckField, 9, 3, 1, 146, 25, 0, // Skip to: 8345 /* 1799 */ MCD_OPC_CheckField, 0, 4, 0, 139, 25, 0, // Skip to: 8345 /* 1806 */ MCD_OPC_Decode, 183, 5, 25, // Opcode: MRSbanked /* 1810 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 1846 /* 1815 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1818 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1832 /* 1823 */ MCD_OPC_CheckPredicate, 0, 117, 25, 0, // Skip to: 8345 /* 1828 */ MCD_OPC_Decode, 231, 6, 7, // Opcode: STRH /* 1832 */ MCD_OPC_FilterValue, 1, 108, 25, 0, // Skip to: 8345 /* 1837 */ MCD_OPC_CheckPredicate, 0, 103, 25, 0, // Skip to: 8345 /* 1842 */ MCD_OPC_Decode, 140, 5, 7, // Opcode: LDRH /* 1846 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1882 /* 1851 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1854 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1868 /* 1859 */ MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 8345 /* 1864 */ MCD_OPC_Decode, 133, 5, 7, // Opcode: LDRD /* 1868 */ MCD_OPC_FilterValue, 1, 72, 25, 0, // Skip to: 8345 /* 1873 */ MCD_OPC_CheckPredicate, 0, 67, 25, 0, // Skip to: 8345 /* 1878 */ MCD_OPC_Decode, 145, 5, 7, // Opcode: LDRSB /* 1882 */ MCD_OPC_FilterValue, 15, 58, 25, 0, // Skip to: 8345 /* 1887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1890 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1904 /* 1895 */ MCD_OPC_CheckPredicate, 3, 45, 25, 0, // Skip to: 8345 /* 1900 */ MCD_OPC_Decode, 224, 6, 7, // Opcode: STRD /* 1904 */ MCD_OPC_FilterValue, 1, 36, 25, 0, // Skip to: 8345 /* 1909 */ MCD_OPC_CheckPredicate, 0, 31, 25, 0, // Skip to: 8345 /* 1914 */ MCD_OPC_Decode, 150, 5, 7, // Opcode: LDRSH /* 1918 */ MCD_OPC_FilterValue, 1, 22, 25, 0, // Skip to: 8345 /* 1923 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1926 */ MCD_OPC_FilterValue, 0, 180, 2, 0, // Skip to: 2623 /* 1931 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 1934 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 2002 /* 1939 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 1942 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1972 /* 1947 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1963 /* 1952 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1963 /* 1959 */ MCD_OPC_Decode, 204, 4, 0, // Opcode: EORrr /* 1963 */ MCD_OPC_CheckPredicate, 0, 233, 24, 0, // Skip to: 8345 /* 1968 */ MCD_OPC_Decode, 205, 4, 1, // Opcode: EORrsi /* 1972 */ MCD_OPC_FilterValue, 1, 224, 24, 0, // Skip to: 8345 /* 1977 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1993 /* 1982 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1993 /* 1989 */ MCD_OPC_Decode, 228, 5, 0, // Opcode: RSBrr /* 1993 */ MCD_OPC_CheckPredicate, 0, 203, 24, 0, // Skip to: 8345 /* 1998 */ MCD_OPC_Decode, 229, 5, 1, // Opcode: RSBrsi /* 2002 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 2070 /* 2007 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2010 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2040 /* 2015 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2031 /* 2020 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2031 /* 2027 */ MCD_OPC_Decode, 146, 4, 0, // Opcode: ADCrr /* 2031 */ MCD_OPC_CheckPredicate, 0, 165, 24, 0, // Skip to: 8345 /* 2036 */ MCD_OPC_Decode, 147, 4, 1, // Opcode: ADCrsi /* 2040 */ MCD_OPC_FilterValue, 1, 156, 24, 0, // Skip to: 8345 /* 2045 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2061 /* 2050 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2061 /* 2057 */ MCD_OPC_Decode, 232, 5, 0, // Opcode: RSCrr /* 2061 */ MCD_OPC_CheckPredicate, 0, 135, 24, 0, // Skip to: 8345 /* 2066 */ MCD_OPC_Decode, 233, 5, 1, // Opcode: RSCrsi /* 2070 */ MCD_OPC_FilterValue, 2, 166, 1, 0, // Skip to: 2497 /* 2075 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 2078 */ MCD_OPC_FilterValue, 0, 70, 1, 0, // Skip to: 2409 /* 2083 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 2086 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 2129 /* 2091 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... /* 2094 */ MCD_OPC_FilterValue, 120, 16, 0, 0, // Skip to: 2115 /* 2099 */ MCD_OPC_CheckPredicate, 0, 97, 24, 0, // Skip to: 8345 /* 2104 */ MCD_OPC_CheckField, 8, 1, 0, 90, 24, 0, // Skip to: 8345 /* 2111 */ MCD_OPC_Decode, 185, 5, 26, // Opcode: MSR /* 2115 */ MCD_OPC_FilterValue, 121, 81, 24, 0, // Skip to: 8345 /* 2120 */ MCD_OPC_CheckPredicate, 7, 76, 24, 0, // Skip to: 8345 /* 2125 */ MCD_OPC_Decode, 186, 5, 27, // Opcode: MSRbanked /* 2129 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2158 /* 2134 */ MCD_OPC_CheckPredicate, 0, 62, 24, 0, // Skip to: 8345 /* 2139 */ MCD_OPC_CheckField, 22, 1, 0, 55, 24, 0, // Skip to: 8345 /* 2146 */ MCD_OPC_CheckField, 8, 12, 255, 31, 47, 24, 0, // Skip to: 8345 /* 2154 */ MCD_OPC_Decode, 175, 4, 28, // Opcode: BXJ /* 2158 */ MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 2230 /* 2163 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 2166 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2198 /* 2171 */ MCD_OPC_CheckPredicate, 2, 25, 24, 0, // Skip to: 8345 /* 2176 */ MCD_OPC_CheckField, 28, 4, 14, 18, 24, 0, // Skip to: 8345 /* 2183 */ MCD_OPC_CheckField, 22, 1, 0, 11, 24, 0, // Skip to: 8345 /* 2190 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, /* 2194 */ MCD_OPC_Decode, 198, 4, 8, // Opcode: CRC32H /* 2198 */ MCD_OPC_FilterValue, 1, 254, 23, 0, // Skip to: 8345 /* 2203 */ MCD_OPC_CheckPredicate, 2, 249, 23, 0, // Skip to: 8345 /* 2208 */ MCD_OPC_CheckField, 28, 4, 14, 242, 23, 0, // Skip to: 8345 /* 2215 */ MCD_OPC_CheckField, 22, 1, 0, 235, 23, 0, // Skip to: 8345 /* 2222 */ MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0, /* 2226 */ MCD_OPC_Decode, 196, 4, 8, // Opcode: CRC32CH /* 2230 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 2265 /* 2235 */ MCD_OPC_CheckPredicate, 7, 217, 23, 0, // Skip to: 8345 /* 2240 */ MCD_OPC_CheckField, 22, 1, 1, 210, 23, 0, // Skip to: 8345 /* 2247 */ MCD_OPC_CheckField, 8, 12, 0, 203, 23, 0, // Skip to: 8345 /* 2254 */ MCD_OPC_CheckField, 0, 4, 14, 196, 23, 0, // Skip to: 8345 /* 2261 */ MCD_OPC_Decode, 207, 4, 29, // Opcode: ERET /* 2265 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 2301 /* 2270 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2273 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2287 /* 2278 */ MCD_OPC_CheckPredicate, 3, 174, 23, 0, // Skip to: 8345 /* 2283 */ MCD_OPC_Decode, 149, 6, 13, // Opcode: SMLAWB /* 2287 */ MCD_OPC_FilterValue, 1, 165, 23, 0, // Skip to: 8345 /* 2292 */ MCD_OPC_CheckPredicate, 3, 160, 23, 0, // Skip to: 8345 /* 2297 */ MCD_OPC_Decode, 163, 6, 30, // Opcode: SMULBB /* 2301 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 2337 /* 2306 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2309 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2323 /* 2314 */ MCD_OPC_CheckPredicate, 3, 138, 23, 0, // Skip to: 8345 /* 2319 */ MCD_OPC_Decode, 168, 6, 30, // Opcode: SMULWB /* 2323 */ MCD_OPC_FilterValue, 1, 129, 23, 0, // Skip to: 8345 /* 2328 */ MCD_OPC_CheckPredicate, 3, 124, 23, 0, // Skip to: 8345 /* 2333 */ MCD_OPC_Decode, 166, 6, 30, // Opcode: SMULTB /* 2337 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2373 /* 2342 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2345 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2359 /* 2350 */ MCD_OPC_CheckPredicate, 3, 102, 23, 0, // Skip to: 8345 /* 2355 */ MCD_OPC_Decode, 150, 6, 13, // Opcode: SMLAWT /* 2359 */ MCD_OPC_FilterValue, 1, 93, 23, 0, // Skip to: 8345 /* 2364 */ MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 8345 /* 2369 */ MCD_OPC_Decode, 164, 6, 30, // Opcode: SMULBT /* 2373 */ MCD_OPC_FilterValue, 7, 79, 23, 0, // Skip to: 8345 /* 2378 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2381 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2395 /* 2386 */ MCD_OPC_CheckPredicate, 3, 66, 23, 0, // Skip to: 8345 /* 2391 */ MCD_OPC_Decode, 169, 6, 30, // Opcode: SMULWT /* 2395 */ MCD_OPC_FilterValue, 1, 57, 23, 0, // Skip to: 8345 /* 2400 */ MCD_OPC_CheckPredicate, 3, 52, 23, 0, // Skip to: 8345 /* 2405 */ MCD_OPC_Decode, 167, 6, 30, // Opcode: SMULTT /* 2409 */ MCD_OPC_FilterValue, 1, 43, 23, 0, // Skip to: 8345 /* 2414 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2417 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2457 /* 2422 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2443 /* 2427 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2443 /* 2434 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 2439 */ MCD_OPC_Decode, 130, 7, 20, // Opcode: TEQrr /* 2443 */ MCD_OPC_CheckPredicate, 0, 9, 23, 0, // Skip to: 8345 /* 2448 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 2453 */ MCD_OPC_Decode, 131, 7, 17, // Opcode: TEQrsi /* 2457 */ MCD_OPC_FilterValue, 1, 251, 22, 0, // Skip to: 8345 /* 2462 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2483 /* 2467 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2483 /* 2474 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 2479 */ MCD_OPC_Decode, 184, 4, 20, // Opcode: CMNzrr /* 2483 */ MCD_OPC_CheckPredicate, 0, 225, 22, 0, // Skip to: 8345 /* 2488 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 2493 */ MCD_OPC_Decode, 185, 4, 17, // Opcode: CMNzrsi /* 2497 */ MCD_OPC_FilterValue, 3, 211, 22, 0, // Skip to: 8345 /* 2502 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2505 */ MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 2583 /* 2510 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 2534 /* 2515 */ MCD_OPC_CheckField, 5, 16, 128, 15, 11, 0, 0, // Skip to: 2534 /* 2523 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2534 /* 2530 */ MCD_OPC_Decode, 170, 5, 29, // Opcode: MOVPCLR /* 2534 */ MCD_OPC_ExtractField, 5, 7, // Inst{11-5} ... /* 2537 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2567 /* 2542 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2558 /* 2547 */ MCD_OPC_CheckField, 16, 4, 0, 4, 0, 0, // Skip to: 2558 /* 2554 */ MCD_OPC_Decode, 174, 5, 31, // Opcode: MOVr /* 2558 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 2567 /* 2563 */ MCD_OPC_Decode, 175, 5, 32, // Opcode: MOVr_TC /* 2567 */ MCD_OPC_CheckPredicate, 0, 141, 22, 0, // Skip to: 8345 /* 2572 */ MCD_OPC_CheckField, 16, 4, 0, 134, 22, 0, // Skip to: 8345 /* 2579 */ MCD_OPC_Decode, 176, 5, 33, // Opcode: MOVsi /* 2583 */ MCD_OPC_FilterValue, 1, 125, 22, 0, // Skip to: 8345 /* 2588 */ MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2609 /* 2593 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2609 /* 2600 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, /* 2605 */ MCD_OPC_Decode, 190, 5, 31, // Opcode: MVNr /* 2609 */ MCD_OPC_CheckPredicate, 0, 99, 22, 0, // Skip to: 8345 /* 2614 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, /* 2619 */ MCD_OPC_Decode, 191, 5, 33, // Opcode: MVNsi /* 2623 */ MCD_OPC_FilterValue, 1, 85, 22, 0, // Skip to: 8345 /* 2628 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 2631 */ MCD_OPC_FilterValue, 0, 113, 1, 0, // Skip to: 3005 /* 2636 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... /* 2639 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2653 /* 2644 */ MCD_OPC_CheckPredicate, 0, 64, 22, 0, // Skip to: 8345 /* 2649 */ MCD_OPC_Decode, 206, 4, 2, // Opcode: EORrsr /* 2653 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2667 /* 2658 */ MCD_OPC_CheckPredicate, 0, 50, 22, 0, // Skip to: 8345 /* 2663 */ MCD_OPC_Decode, 230, 5, 2, // Opcode: RSBrsr /* 2667 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2681 /* 2672 */ MCD_OPC_CheckPredicate, 0, 36, 22, 0, // Skip to: 8345 /* 2677 */ MCD_OPC_Decode, 148, 4, 3, // Opcode: ADCrsr /* 2681 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2695 /* 2686 */ MCD_OPC_CheckPredicate, 0, 22, 22, 0, // Skip to: 8345 /* 2691 */ MCD_OPC_Decode, 234, 5, 2, // Opcode: RSCrsr /* 2695 */ MCD_OPC_FilterValue, 4, 163, 0, 0, // Skip to: 2863 /* 2700 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 2703 */ MCD_OPC_FilterValue, 0, 136, 0, 0, // Skip to: 2844 /* 2708 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 2711 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2766 /* 2716 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... /* 2719 */ MCD_OPC_FilterValue, 255, 31, 244, 21, 0, // Skip to: 8345 /* 2725 */ MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2741 /* 2730 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2741 /* 2737 */ MCD_OPC_Decode, 176, 4, 29, // Opcode: BX_RET /* 2741 */ MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2757 /* 2746 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2757 /* 2753 */ MCD_OPC_Decode, 174, 4, 34, // Opcode: BX /* 2757 */ MCD_OPC_CheckPredicate, 10, 207, 21, 0, // Skip to: 8345 /* 2762 */ MCD_OPC_Decode, 177, 4, 28, // Opcode: BX_pred /* 2766 */ MCD_OPC_FilterValue, 1, 34, 0, 0, // Skip to: 2805 /* 2771 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... /* 2774 */ MCD_OPC_FilterValue, 255, 31, 189, 21, 0, // Skip to: 8345 /* 2780 */ MCD_OPC_CheckPredicate, 11, 11, 0, 0, // Skip to: 2796 /* 2785 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2796 /* 2792 */ MCD_OPC_Decode, 170, 4, 34, // Opcode: BLX /* 2796 */ MCD_OPC_CheckPredicate, 11, 168, 21, 0, // Skip to: 8345 /* 2801 */ MCD_OPC_Decode, 171, 4, 28, // Opcode: BLX_pred /* 2805 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2823 /* 2810 */ MCD_OPC_CheckPredicate, 0, 154, 21, 0, // Skip to: 8345 /* 2815 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 2819 */ MCD_OPC_Decode, 212, 5, 21, // Opcode: QSUB /* 2823 */ MCD_OPC_FilterValue, 3, 141, 21, 0, // Skip to: 8345 /* 2828 */ MCD_OPC_CheckPredicate, 0, 136, 21, 0, // Skip to: 8345 /* 2833 */ MCD_OPC_CheckField, 28, 4, 14, 129, 21, 0, // Skip to: 8345 /* 2840 */ MCD_OPC_Decode, 168, 4, 15, // Opcode: BKPT /* 2844 */ MCD_OPC_FilterValue, 1, 120, 21, 0, // Skip to: 8345 /* 2849 */ MCD_OPC_CheckPredicate, 0, 115, 21, 0, // Skip to: 8345 /* 2854 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 2859 */ MCD_OPC_Decode, 132, 7, 18, // Opcode: TEQrsr /* 2863 */ MCD_OPC_FilterValue, 5, 97, 0, 0, // Skip to: 2965 /* 2868 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 2871 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 2946 /* 2876 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 2879 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2907 /* 2884 */ MCD_OPC_CheckPredicate, 11, 80, 21, 0, // Skip to: 8345 /* 2889 */ MCD_OPC_CheckField, 16, 4, 15, 73, 21, 0, // Skip to: 8345 /* 2896 */ MCD_OPC_CheckField, 8, 4, 15, 66, 21, 0, // Skip to: 8345 /* 2903 */ MCD_OPC_Decode, 182, 4, 35, // Opcode: CLZ /* 2907 */ MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2925 /* 2912 */ MCD_OPC_CheckPredicate, 0, 52, 21, 0, // Skip to: 8345 /* 2917 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 2921 */ MCD_OPC_Decode, 210, 5, 21, // Opcode: QDSUB /* 2925 */ MCD_OPC_FilterValue, 3, 39, 21, 0, // Skip to: 8345 /* 2930 */ MCD_OPC_CheckPredicate, 12, 34, 21, 0, // Skip to: 8345 /* 2935 */ MCD_OPC_CheckField, 8, 12, 0, 27, 21, 0, // Skip to: 8345 /* 2942 */ MCD_OPC_Decode, 135, 6, 36, // Opcode: SMC /* 2946 */ MCD_OPC_FilterValue, 1, 18, 21, 0, // Skip to: 8345 /* 2951 */ MCD_OPC_CheckPredicate, 0, 13, 21, 0, // Skip to: 8345 /* 2956 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 2961 */ MCD_OPC_Decode, 186, 4, 18, // Opcode: CMNzrsr /* 2965 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2986 /* 2970 */ MCD_OPC_CheckPredicate, 0, 250, 20, 0, // Skip to: 8345 /* 2975 */ MCD_OPC_CheckField, 16, 4, 0, 243, 20, 0, // Skip to: 8345 /* 2982 */ MCD_OPC_Decode, 177, 5, 37, // Opcode: MOVsr /* 2986 */ MCD_OPC_FilterValue, 7, 234, 20, 0, // Skip to: 8345 /* 2991 */ MCD_OPC_CheckPredicate, 0, 229, 20, 0, // Skip to: 8345 /* 2996 */ MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0, /* 3001 */ MCD_OPC_Decode, 192, 5, 37, // Opcode: MVNsr /* 3005 */ MCD_OPC_FilterValue, 1, 215, 20, 0, // Skip to: 8345 /* 3010 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 3013 */ MCD_OPC_FilterValue, 0, 48, 1, 0, // Skip to: 3322 /* 3018 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... /* 3021 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3035 /* 3026 */ MCD_OPC_CheckPredicate, 1, 194, 20, 0, // Skip to: 8345 /* 3031 */ MCD_OPC_Decode, 168, 5, 38, // Opcode: MLA /* 3035 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3056 /* 3040 */ MCD_OPC_CheckPredicate, 13, 180, 20, 0, // Skip to: 8345 /* 3045 */ MCD_OPC_CheckField, 20, 1, 0, 173, 20, 0, // Skip to: 8345 /* 3052 */ MCD_OPC_Decode, 169, 5, 39, // Opcode: MLS /* 3056 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3070 /* 3061 */ MCD_OPC_CheckPredicate, 1, 159, 20, 0, // Skip to: 8345 /* 3066 */ MCD_OPC_Decode, 153, 7, 40, // Opcode: UMLAL /* 3070 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3084 /* 3075 */ MCD_OPC_CheckPredicate, 1, 145, 20, 0, // Skip to: 8345 /* 3080 */ MCD_OPC_Decode, 140, 6, 40, // Opcode: SMLAL /* 3084 */ MCD_OPC_FilterValue, 6, 89, 0, 0, // Skip to: 3178 /* 3089 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 3092 */ MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3135 /* 3097 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3114 /* 3105 */ MCD_OPC_CheckPredicate, 9, 115, 20, 0, // Skip to: 8345 /* 3110 */ MCD_OPC_Decode, 205, 6, 41, // Opcode: STLEXD /* 3114 */ MCD_OPC_FilterValue, 1, 106, 20, 0, // Skip to: 8345 /* 3119 */ MCD_OPC_CheckPredicate, 9, 101, 20, 0, // Skip to: 8345 /* 3124 */ MCD_OPC_CheckField, 0, 4, 15, 94, 20, 0, // Skip to: 8345 /* 3131 */ MCD_OPC_Decode, 226, 4, 42, // Opcode: LDAEXD /* 3135 */ MCD_OPC_FilterValue, 15, 85, 20, 0, // Skip to: 8345 /* 3140 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3157 /* 3148 */ MCD_OPC_CheckPredicate, 0, 72, 20, 0, // Skip to: 8345 /* 3153 */ MCD_OPC_Decode, 229, 6, 41, // Opcode: STREXD /* 3157 */ MCD_OPC_FilterValue, 1, 63, 20, 0, // Skip to: 8345 /* 3162 */ MCD_OPC_CheckPredicate, 0, 58, 20, 0, // Skip to: 8345 /* 3167 */ MCD_OPC_CheckField, 0, 4, 15, 51, 20, 0, // Skip to: 8345 /* 3174 */ MCD_OPC_Decode, 138, 5, 42, // Opcode: LDREXD /* 3178 */ MCD_OPC_FilterValue, 7, 42, 20, 0, // Skip to: 8345 /* 3183 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 3186 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 3236 /* 3191 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3194 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3215 /* 3199 */ MCD_OPC_CheckPredicate, 8, 21, 20, 0, // Skip to: 8345 /* 3204 */ MCD_OPC_CheckField, 12, 4, 15, 14, 20, 0, // Skip to: 8345 /* 3211 */ MCD_OPC_Decode, 207, 6, 22, // Opcode: STLH /* 3215 */ MCD_OPC_FilterValue, 1, 5, 20, 0, // Skip to: 8345 /* 3220 */ MCD_OPC_CheckPredicate, 8, 0, 20, 0, // Skip to: 8345 /* 3225 */ MCD_OPC_CheckField, 0, 4, 15, 249, 19, 0, // Skip to: 8345 /* 3232 */ MCD_OPC_Decode, 228, 4, 23, // Opcode: LDAH /* 3236 */ MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3279 /* 3241 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3244 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3258 /* 3249 */ MCD_OPC_CheckPredicate, 9, 227, 19, 0, // Skip to: 8345 /* 3254 */ MCD_OPC_Decode, 206, 6, 24, // Opcode: STLEXH /* 3258 */ MCD_OPC_FilterValue, 1, 218, 19, 0, // Skip to: 8345 /* 3263 */ MCD_OPC_CheckPredicate, 9, 213, 19, 0, // Skip to: 8345 /* 3268 */ MCD_OPC_CheckField, 0, 4, 15, 206, 19, 0, // Skip to: 8345 /* 3275 */ MCD_OPC_Decode, 227, 4, 23, // Opcode: LDAEXH /* 3279 */ MCD_OPC_FilterValue, 15, 197, 19, 0, // Skip to: 8345 /* 3284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3287 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3301 /* 3292 */ MCD_OPC_CheckPredicate, 0, 184, 19, 0, // Skip to: 8345 /* 3297 */ MCD_OPC_Decode, 230, 6, 24, // Opcode: STREXH /* 3301 */ MCD_OPC_FilterValue, 1, 175, 19, 0, // Skip to: 8345 /* 3306 */ MCD_OPC_CheckPredicate, 0, 170, 19, 0, // Skip to: 8345 /* 3311 */ MCD_OPC_CheckField, 0, 4, 15, 163, 19, 0, // Skip to: 8345 /* 3318 */ MCD_OPC_Decode, 139, 5, 23, // Opcode: LDREXH /* 3322 */ MCD_OPC_FilterValue, 1, 130, 0, 0, // Skip to: 3457 /* 3327 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3330 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3395 /* 3335 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 3338 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 3381 /* 3343 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3346 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3367 /* 3351 */ MCD_OPC_CheckPredicate, 0, 125, 19, 0, // Skip to: 8345 /* 3356 */ MCD_OPC_CheckField, 8, 4, 0, 118, 19, 0, // Skip to: 8345 /* 3363 */ MCD_OPC_Decode, 233, 6, 43, // Opcode: STRHTr /* 3367 */ MCD_OPC_FilterValue, 1, 109, 19, 0, // Skip to: 8345 /* 3372 */ MCD_OPC_CheckPredicate, 0, 104, 19, 0, // Skip to: 8345 /* 3377 */ MCD_OPC_Decode, 232, 6, 44, // Opcode: STRHTi /* 3381 */ MCD_OPC_FilterValue, 1, 95, 19, 0, // Skip to: 8345 /* 3386 */ MCD_OPC_CheckPredicate, 0, 90, 19, 0, // Skip to: 8345 /* 3391 */ MCD_OPC_Decode, 235, 6, 7, // Opcode: STRH_PRE /* 3395 */ MCD_OPC_FilterValue, 1, 81, 19, 0, // Skip to: 8345 /* 3400 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 3403 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3443 /* 3408 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3411 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3429 /* 3416 */ MCD_OPC_CheckPredicate, 0, 60, 19, 0, // Skip to: 8345 /* 3421 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 3425 */ MCD_OPC_Decode, 142, 5, 45, // Opcode: LDRHTr /* 3429 */ MCD_OPC_FilterValue, 1, 47, 19, 0, // Skip to: 8345 /* 3434 */ MCD_OPC_CheckPredicate, 0, 42, 19, 0, // Skip to: 8345 /* 3439 */ MCD_OPC_Decode, 141, 5, 46, // Opcode: LDRHTi /* 3443 */ MCD_OPC_FilterValue, 1, 33, 19, 0, // Skip to: 8345 /* 3448 */ MCD_OPC_CheckPredicate, 0, 28, 19, 0, // Skip to: 8345 /* 3453 */ MCD_OPC_Decode, 144, 5, 7, // Opcode: LDRH_PRE /* 3457 */ MCD_OPC_FilterValue, 2, 86, 0, 0, // Skip to: 3548 /* 3462 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3465 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3486 /* 3470 */ MCD_OPC_CheckPredicate, 0, 6, 19, 0, // Skip to: 8345 /* 3475 */ MCD_OPC_CheckField, 24, 1, 1, 255, 18, 0, // Skip to: 8345 /* 3482 */ MCD_OPC_Decode, 135, 5, 7, // Opcode: LDRD_PRE /* 3486 */ MCD_OPC_FilterValue, 1, 246, 18, 0, // Skip to: 8345 /* 3491 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 3494 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3534 /* 3499 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3502 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3520 /* 3507 */ MCD_OPC_CheckPredicate, 0, 225, 18, 0, // Skip to: 8345 /* 3512 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 3516 */ MCD_OPC_Decode, 147, 5, 45, // Opcode: LDRSBTr /* 3520 */ MCD_OPC_FilterValue, 1, 212, 18, 0, // Skip to: 8345 /* 3525 */ MCD_OPC_CheckPredicate, 0, 207, 18, 0, // Skip to: 8345 /* 3530 */ MCD_OPC_Decode, 146, 5, 46, // Opcode: LDRSBTi /* 3534 */ MCD_OPC_FilterValue, 1, 198, 18, 0, // Skip to: 8345 /* 3539 */ MCD_OPC_CheckPredicate, 0, 193, 18, 0, // Skip to: 8345 /* 3544 */ MCD_OPC_Decode, 149, 5, 7, // Opcode: LDRSB_PRE /* 3548 */ MCD_OPC_FilterValue, 3, 184, 18, 0, // Skip to: 8345 /* 3553 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3556 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3577 /* 3561 */ MCD_OPC_CheckPredicate, 0, 171, 18, 0, // Skip to: 8345 /* 3566 */ MCD_OPC_CheckField, 24, 1, 1, 164, 18, 0, // Skip to: 8345 /* 3573 */ MCD_OPC_Decode, 226, 6, 7, // Opcode: STRD_PRE /* 3577 */ MCD_OPC_FilterValue, 1, 155, 18, 0, // Skip to: 8345 /* 3582 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 3585 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3625 /* 3590 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3593 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3611 /* 3598 */ MCD_OPC_CheckPredicate, 0, 134, 18, 0, // Skip to: 8345 /* 3603 */ MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0, /* 3607 */ MCD_OPC_Decode, 152, 5, 45, // Opcode: LDRSHTr /* 3611 */ MCD_OPC_FilterValue, 1, 121, 18, 0, // Skip to: 8345 /* 3616 */ MCD_OPC_CheckPredicate, 0, 116, 18, 0, // Skip to: 8345 /* 3621 */ MCD_OPC_Decode, 151, 5, 46, // Opcode: LDRSHTi /* 3625 */ MCD_OPC_FilterValue, 1, 107, 18, 0, // Skip to: 8345 /* 3630 */ MCD_OPC_CheckPredicate, 0, 102, 18, 0, // Skip to: 8345 /* 3635 */ MCD_OPC_Decode, 154, 5, 7, // Opcode: LDRSH_PRE /* 3639 */ MCD_OPC_FilterValue, 1, 0, 2, 0, // Skip to: 4156 /* 3644 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 3647 */ MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 3853 /* 3652 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 3655 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 3735 /* 3660 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 3663 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3677 /* 3668 */ MCD_OPC_CheckPredicate, 0, 46, 0, 0, // Skip to: 3719 /* 3673 */ MCD_OPC_Decode, 158, 4, 47, // Opcode: ANDri /* 3677 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3691 /* 3682 */ MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 3719 /* 3687 */ MCD_OPC_Decode, 244, 6, 47, // Opcode: SUBri /* 3691 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3705 /* 3696 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 3719 /* 3701 */ MCD_OPC_Decode, 149, 4, 47, // Opcode: ADDri /* 3705 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3719 /* 3710 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 3719 /* 3715 */ MCD_OPC_Decode, 238, 5, 47, // Opcode: SBCri /* 3719 */ MCD_OPC_CheckPredicate, 0, 13, 18, 0, // Skip to: 8345 /* 3724 */ MCD_OPC_CheckField, 16, 5, 15, 6, 18, 0, // Skip to: 8345 /* 3731 */ MCD_OPC_Decode, 153, 4, 48, // Opcode: ADR /* 3735 */ MCD_OPC_FilterValue, 1, 253, 17, 0, // Skip to: 8345 /* 3740 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 3743 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3784 /* 3748 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3765 /* 3756 */ MCD_OPC_CheckPredicate, 13, 232, 17, 0, // Skip to: 8345 /* 3761 */ MCD_OPC_Decode, 173, 5, 49, // Opcode: MOVi16 /* 3765 */ MCD_OPC_FilterValue, 1, 223, 17, 0, // Skip to: 8345 /* 3770 */ MCD_OPC_CheckPredicate, 0, 218, 17, 0, // Skip to: 8345 /* 3775 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 3780 */ MCD_OPC_Decode, 136, 7, 50, // Opcode: TSTri /* 3784 */ MCD_OPC_FilterValue, 1, 36, 0, 0, // Skip to: 3825 /* 3789 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3792 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3806 /* 3797 */ MCD_OPC_CheckPredicate, 13, 191, 17, 0, // Skip to: 8345 /* 3802 */ MCD_OPC_Decode, 171, 5, 49, // Opcode: MOVTi16 /* 3806 */ MCD_OPC_FilterValue, 1, 182, 17, 0, // Skip to: 8345 /* 3811 */ MCD_OPC_CheckPredicate, 0, 177, 17, 0, // Skip to: 8345 /* 3816 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 3821 */ MCD_OPC_Decode, 187, 4, 50, // Opcode: CMPri /* 3825 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3839 /* 3830 */ MCD_OPC_CheckPredicate, 0, 158, 17, 0, // Skip to: 8345 /* 3835 */ MCD_OPC_Decode, 193, 5, 47, // Opcode: ORRri /* 3839 */ MCD_OPC_FilterValue, 3, 149, 17, 0, // Skip to: 8345 /* 3844 */ MCD_OPC_CheckPredicate, 0, 144, 17, 0, // Skip to: 8345 /* 3849 */ MCD_OPC_Decode, 164, 4, 47, // Opcode: BICri /* 3853 */ MCD_OPC_FilterValue, 1, 135, 17, 0, // Skip to: 8345 /* 3858 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 3861 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3897 /* 3866 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3869 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3883 /* 3874 */ MCD_OPC_CheckPredicate, 0, 114, 17, 0, // Skip to: 8345 /* 3879 */ MCD_OPC_Decode, 203, 4, 47, // Opcode: EORri /* 3883 */ MCD_OPC_FilterValue, 1, 105, 17, 0, // Skip to: 8345 /* 3888 */ MCD_OPC_CheckPredicate, 0, 100, 17, 0, // Skip to: 8345 /* 3893 */ MCD_OPC_Decode, 227, 5, 47, // Opcode: RSBri /* 3897 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 3933 /* 3902 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 3905 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3919 /* 3910 */ MCD_OPC_CheckPredicate, 0, 78, 17, 0, // Skip to: 8345 /* 3915 */ MCD_OPC_Decode, 145, 4, 47, // Opcode: ADCri /* 3919 */ MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8345 /* 3924 */ MCD_OPC_CheckPredicate, 0, 64, 17, 0, // Skip to: 8345 /* 3929 */ MCD_OPC_Decode, 231, 5, 47, // Opcode: RSCri /* 3933 */ MCD_OPC_FilterValue, 2, 168, 0, 0, // Skip to: 4106 /* 3938 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3941 */ MCD_OPC_FilterValue, 0, 114, 0, 0, // Skip to: 4060 /* 3946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3949 */ MCD_OPC_FilterValue, 15, 39, 17, 0, // Skip to: 8345 /* 3954 */ MCD_OPC_CheckPredicate, 14, 32, 0, 0, // Skip to: 3991 /* 3959 */ MCD_OPC_CheckField, 28, 4, 14, 25, 0, 0, // Skip to: 3991 /* 3966 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 3991 /* 3973 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 3991 /* 3980 */ MCD_OPC_CheckField, 0, 12, 18, 4, 0, 0, // Skip to: 3991 /* 3987 */ MCD_OPC_Decode, 135, 7, 51, // Opcode: TSB /* 3991 */ MCD_OPC_CheckPredicate, 15, 25, 0, 0, // Skip to: 4021 /* 3996 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4021 /* 4003 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4021 /* 4010 */ MCD_OPC_CheckField, 4, 8, 15, 4, 0, 0, // Skip to: 4021 /* 4017 */ MCD_OPC_Decode, 200, 4, 36, // Opcode: DBG /* 4021 */ MCD_OPC_CheckPredicate, 1, 25, 0, 0, // Skip to: 4051 /* 4026 */ MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4051 /* 4033 */ MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4051 /* 4040 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4051 /* 4047 */ MCD_OPC_Decode, 218, 4, 52, // Opcode: HINT /* 4051 */ MCD_OPC_CheckPredicate, 0, 193, 16, 0, // Skip to: 8345 /* 4056 */ MCD_OPC_Decode, 187, 5, 53, // Opcode: MSRi /* 4060 */ MCD_OPC_FilterValue, 1, 184, 16, 0, // Skip to: 8345 /* 4065 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4068 */ MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 4087 /* 4073 */ MCD_OPC_CheckPredicate, 0, 171, 16, 0, // Skip to: 8345 /* 4078 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 4083 */ MCD_OPC_Decode, 129, 7, 50, // Opcode: TEQri /* 4087 */ MCD_OPC_FilterValue, 1, 157, 16, 0, // Skip to: 8345 /* 4092 */ MCD_OPC_CheckPredicate, 0, 152, 16, 0, // Skip to: 8345 /* 4097 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0, /* 4102 */ MCD_OPC_Decode, 183, 4, 50, // Opcode: CMNri /* 4106 */ MCD_OPC_FilterValue, 3, 138, 16, 0, // Skip to: 8345 /* 4111 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 4114 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4135 /* 4119 */ MCD_OPC_CheckPredicate, 0, 125, 16, 0, // Skip to: 8345 /* 4124 */ MCD_OPC_CheckField, 16, 4, 0, 118, 16, 0, // Skip to: 8345 /* 4131 */ MCD_OPC_Decode, 172, 5, 54, // Opcode: MOVi /* 4135 */ MCD_OPC_FilterValue, 1, 109, 16, 0, // Skip to: 8345 /* 4140 */ MCD_OPC_CheckPredicate, 0, 104, 16, 0, // Skip to: 8345 /* 4145 */ MCD_OPC_CheckField, 16, 4, 0, 97, 16, 0, // Skip to: 8345 /* 4152 */ MCD_OPC_Decode, 189, 5, 54, // Opcode: MVNi /* 4156 */ MCD_OPC_FilterValue, 2, 229, 1, 0, // Skip to: 4646 /* 4161 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 4164 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4200 /* 4169 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4172 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4186 /* 4177 */ MCD_OPC_CheckPredicate, 0, 67, 16, 0, // Skip to: 8345 /* 4182 */ MCD_OPC_Decode, 238, 6, 55, // Opcode: STR_POST_IMM /* 4186 */ MCD_OPC_FilterValue, 1, 58, 16, 0, // Skip to: 8345 /* 4191 */ MCD_OPC_CheckPredicate, 0, 53, 16, 0, // Skip to: 8345 /* 4196 */ MCD_OPC_Decode, 242, 6, 56, // Opcode: STRi12 /* 4200 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 4259 /* 4205 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4208 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4222 /* 4213 */ MCD_OPC_CheckPredicate, 0, 31, 16, 0, // Skip to: 8345 /* 4218 */ MCD_OPC_Decode, 157, 5, 55, // Opcode: LDR_POST_IMM /* 4222 */ MCD_OPC_FilterValue, 1, 22, 16, 0, // Skip to: 8345 /* 4227 */ MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4250 /* 4232 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4250 /* 4239 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4250 /* 4246 */ MCD_OPC_Decode, 199, 5, 57, // Opcode: PLDWi12 /* 4250 */ MCD_OPC_CheckPredicate, 0, 250, 15, 0, // Skip to: 8345 /* 4255 */ MCD_OPC_Decode, 162, 5, 56, // Opcode: LDRi12 /* 4259 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 4295 /* 4264 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4281 /* 4272 */ MCD_OPC_CheckPredicate, 0, 228, 15, 0, // Skip to: 8345 /* 4277 */ MCD_OPC_Decode, 236, 6, 55, // Opcode: STRT_POST_IMM /* 4281 */ MCD_OPC_FilterValue, 1, 219, 15, 0, // Skip to: 8345 /* 4286 */ MCD_OPC_CheckPredicate, 0, 214, 15, 0, // Skip to: 8345 /* 4291 */ MCD_OPC_Decode, 240, 6, 58, // Opcode: STR_PRE_IMM /* 4295 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 4331 /* 4300 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4303 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4317 /* 4308 */ MCD_OPC_CheckPredicate, 0, 192, 15, 0, // Skip to: 8345 /* 4313 */ MCD_OPC_Decode, 155, 5, 55, // Opcode: LDRT_POST_IMM /* 4317 */ MCD_OPC_FilterValue, 1, 183, 15, 0, // Skip to: 8345 /* 4322 */ MCD_OPC_CheckPredicate, 0, 178, 15, 0, // Skip to: 8345 /* 4327 */ MCD_OPC_Decode, 159, 5, 59, // Opcode: LDR_PRE_IMM /* 4331 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4367 /* 4336 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4339 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4353 /* 4344 */ MCD_OPC_CheckPredicate, 0, 156, 15, 0, // Skip to: 8345 /* 4349 */ MCD_OPC_Decode, 218, 6, 55, // Opcode: STRB_POST_IMM /* 4353 */ MCD_OPC_FilterValue, 1, 147, 15, 0, // Skip to: 8345 /* 4358 */ MCD_OPC_CheckPredicate, 0, 142, 15, 0, // Skip to: 8345 /* 4363 */ MCD_OPC_Decode, 222, 6, 60, // Opcode: STRBi12 /* 4367 */ MCD_OPC_FilterValue, 5, 77, 0, 0, // Skip to: 4449 /* 4372 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4375 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 4412 /* 4380 */ MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 4403 /* 4385 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4403 /* 4392 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4403 /* 4399 */ MCD_OPC_Decode, 203, 5, 57, // Opcode: PLIi12 /* 4403 */ MCD_OPC_CheckPredicate, 0, 97, 15, 0, // Skip to: 8345 /* 4408 */ MCD_OPC_Decode, 255, 4, 55, // Opcode: LDRB_POST_IMM /* 4412 */ MCD_OPC_FilterValue, 1, 88, 15, 0, // Skip to: 8345 /* 4417 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 4440 /* 4422 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4440 /* 4429 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4440 /* 4436 */ MCD_OPC_Decode, 201, 5, 57, // Opcode: PLDi12 /* 4440 */ MCD_OPC_CheckPredicate, 0, 60, 15, 0, // Skip to: 8345 /* 4445 */ MCD_OPC_Decode, 131, 5, 60, // Opcode: LDRBi12 /* 4449 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4485 /* 4454 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4457 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4471 /* 4462 */ MCD_OPC_CheckPredicate, 0, 38, 15, 0, // Skip to: 8345 /* 4467 */ MCD_OPC_Decode, 216, 6, 55, // Opcode: STRBT_POST_IMM /* 4471 */ MCD_OPC_FilterValue, 1, 29, 15, 0, // Skip to: 8345 /* 4476 */ MCD_OPC_CheckPredicate, 0, 24, 15, 0, // Skip to: 8345 /* 4481 */ MCD_OPC_Decode, 220, 6, 58, // Opcode: STRB_PRE_IMM /* 4485 */ MCD_OPC_FilterValue, 7, 15, 15, 0, // Skip to: 8345 /* 4490 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4507 /* 4498 */ MCD_OPC_CheckPredicate, 0, 2, 15, 0, // Skip to: 8345 /* 4503 */ MCD_OPC_Decode, 253, 4, 55, // Opcode: LDRBT_POST_IMM /* 4507 */ MCD_OPC_FilterValue, 1, 249, 14, 0, // Skip to: 8345 /* 4512 */ MCD_OPC_CheckPredicate, 17, 27, 0, 0, // Skip to: 4544 /* 4517 */ MCD_OPC_CheckField, 28, 4, 15, 20, 0, 0, // Skip to: 4544 /* 4524 */ MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 4544 /* 4531 */ MCD_OPC_CheckField, 0, 20, 159, 224, 63, 4, 0, 0, // Skip to: 4544 /* 4540 */ MCD_OPC_Decode, 181, 4, 51, // Opcode: CLREX /* 4544 */ MCD_OPC_ExtractField, 4, 16, // Inst{19-4} ... /* 4547 */ MCD_OPC_FilterValue, 132, 254, 3, 23, 0, 0, // Skip to: 4577 /* 4554 */ MCD_OPC_CheckPredicate, 18, 78, 0, 0, // Skip to: 4637 /* 4559 */ MCD_OPC_CheckField, 28, 4, 15, 71, 0, 0, // Skip to: 4637 /* 4566 */ MCD_OPC_CheckField, 23, 1, 0, 64, 0, 0, // Skip to: 4637 /* 4573 */ MCD_OPC_Decode, 202, 4, 61, // Opcode: DSB /* 4577 */ MCD_OPC_FilterValue, 133, 254, 3, 23, 0, 0, // Skip to: 4607 /* 4584 */ MCD_OPC_CheckPredicate, 18, 48, 0, 0, // Skip to: 4637 /* 4589 */ MCD_OPC_CheckField, 28, 4, 15, 41, 0, 0, // Skip to: 4637 /* 4596 */ MCD_OPC_CheckField, 23, 1, 0, 34, 0, 0, // Skip to: 4637 /* 4603 */ MCD_OPC_Decode, 201, 4, 61, // Opcode: DMB /* 4607 */ MCD_OPC_FilterValue, 134, 254, 3, 23, 0, 0, // Skip to: 4637 /* 4614 */ MCD_OPC_CheckPredicate, 18, 18, 0, 0, // Skip to: 4637 /* 4619 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4637 /* 4626 */ MCD_OPC_CheckField, 23, 1, 0, 4, 0, 0, // Skip to: 4637 /* 4633 */ MCD_OPC_Decode, 221, 4, 62, // Opcode: ISB /* 4637 */ MCD_OPC_CheckPredicate, 0, 119, 14, 0, // Skip to: 8345 /* 4642 */ MCD_OPC_Decode, 129, 5, 59, // Opcode: LDRB_PRE_IMM /* 4646 */ MCD_OPC_FilterValue, 3, 129, 10, 0, // Skip to: 7340 /* 4651 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 4654 */ MCD_OPC_FilterValue, 0, 200, 2, 0, // Skip to: 5371 /* 4659 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 4662 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 4765 /* 4667 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4670 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4706 /* 4675 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4678 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4692 /* 4683 */ MCD_OPC_CheckPredicate, 0, 73, 14, 0, // Skip to: 8345 /* 4688 */ MCD_OPC_Decode, 239, 6, 55, // Opcode: STR_POST_REG /* 4692 */ MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 8345 /* 4697 */ MCD_OPC_CheckPredicate, 0, 59, 14, 0, // Skip to: 8345 /* 4702 */ MCD_OPC_Decode, 243, 6, 63, // Opcode: STRrs /* 4706 */ MCD_OPC_FilterValue, 1, 50, 14, 0, // Skip to: 8345 /* 4711 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 4714 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4728 /* 4719 */ MCD_OPC_CheckPredicate, 0, 37, 14, 0, // Skip to: 8345 /* 4724 */ MCD_OPC_Decode, 158, 5, 55, // Opcode: LDR_POST_REG /* 4728 */ MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 8345 /* 4733 */ MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4756 /* 4738 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4756 /* 4745 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4756 /* 4752 */ MCD_OPC_Decode, 200, 5, 64, // Opcode: PLDWrs /* 4756 */ MCD_OPC_CheckPredicate, 0, 0, 14, 0, // Skip to: 8345 /* 4761 */ MCD_OPC_Decode, 163, 5, 63, // Opcode: LDRrs /* 4765 */ MCD_OPC_FilterValue, 1, 247, 13, 0, // Skip to: 8345 /* 4770 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 4773 */ MCD_OPC_FilterValue, 0, 202, 0, 0, // Skip to: 4980 /* 4778 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 4781 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 4839 /* 4786 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4789 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 4814 /* 4794 */ MCD_OPC_CheckPredicate, 0, 218, 13, 0, // Skip to: 8345 /* 4799 */ MCD_OPC_CheckField, 20, 1, 1, 211, 13, 0, // Skip to: 8345 /* 4806 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 4810 */ MCD_OPC_Decode, 235, 5, 65, // Opcode: SADD16 /* 4814 */ MCD_OPC_FilterValue, 1, 198, 13, 0, // Skip to: 8345 /* 4819 */ MCD_OPC_CheckPredicate, 0, 193, 13, 0, // Skip to: 8345 /* 4824 */ MCD_OPC_CheckField, 20, 1, 1, 186, 13, 0, // Skip to: 8345 /* 4831 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 4835 */ MCD_OPC_Decode, 236, 5, 65, // Opcode: SADD8 /* 4839 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4860 /* 4844 */ MCD_OPC_CheckPredicate, 1, 168, 13, 0, // Skip to: 8345 /* 4849 */ MCD_OPC_CheckField, 20, 1, 0, 161, 13, 0, // Skip to: 8345 /* 4856 */ MCD_OPC_Decode, 197, 5, 66, // Opcode: PKHBT /* 4860 */ MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 4934 /* 4865 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4868 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 4906 /* 4873 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4876 */ MCD_OPC_FilterValue, 0, 136, 13, 0, // Skip to: 8345 /* 4881 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4897 /* 4886 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4897 /* 4893 */ MCD_OPC_Decode, 161, 6, 67, // Opcode: SMUAD /* 4897 */ MCD_OPC_CheckPredicate, 1, 115, 13, 0, // Skip to: 8345 /* 4902 */ MCD_OPC_Decode, 138, 6, 68, // Opcode: SMLAD /* 4906 */ MCD_OPC_FilterValue, 1, 106, 13, 0, // Skip to: 8345 /* 4911 */ MCD_OPC_CheckPredicate, 19, 101, 13, 0, // Skip to: 8345 /* 4916 */ MCD_OPC_CheckField, 12, 4, 15, 94, 13, 0, // Skip to: 8345 /* 4923 */ MCD_OPC_CheckField, 7, 1, 0, 87, 13, 0, // Skip to: 8345 /* 4930 */ MCD_OPC_Decode, 243, 5, 30, // Opcode: SDIV /* 4934 */ MCD_OPC_FilterValue, 3, 78, 13, 0, // Skip to: 8345 /* 4939 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4942 */ MCD_OPC_FilterValue, 0, 70, 13, 0, // Skip to: 8345 /* 4947 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4950 */ MCD_OPC_FilterValue, 0, 62, 13, 0, // Skip to: 8345 /* 4955 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4971 /* 4960 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4971 /* 4967 */ MCD_OPC_Decode, 161, 7, 30, // Opcode: USAD8 /* 4971 */ MCD_OPC_CheckPredicate, 1, 41, 13, 0, // Skip to: 8345 /* 4976 */ MCD_OPC_Decode, 162, 7, 39, // Opcode: USADA8 /* 4980 */ MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 5098 /* 4985 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 4988 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5020 /* 4993 */ MCD_OPC_CheckPredicate, 0, 19, 13, 0, // Skip to: 8345 /* 4998 */ MCD_OPC_CheckField, 20, 1, 1, 12, 13, 0, // Skip to: 8345 /* 5005 */ MCD_OPC_CheckField, 7, 1, 0, 5, 13, 0, // Skip to: 8345 /* 5012 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5016 */ MCD_OPC_Decode, 237, 5, 65, // Opcode: SASX /* 5020 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5052 /* 5025 */ MCD_OPC_CheckPredicate, 1, 243, 12, 0, // Skip to: 8345 /* 5030 */ MCD_OPC_CheckField, 20, 1, 0, 236, 12, 0, // Skip to: 8345 /* 5037 */ MCD_OPC_CheckField, 7, 1, 1, 229, 12, 0, // Skip to: 8345 /* 5044 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5048 */ MCD_OPC_Decode, 244, 5, 69, // Opcode: SEL /* 5052 */ MCD_OPC_FilterValue, 2, 216, 12, 0, // Skip to: 8345 /* 5057 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 5060 */ MCD_OPC_FilterValue, 0, 208, 12, 0, // Skip to: 8345 /* 5065 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5068 */ MCD_OPC_FilterValue, 0, 200, 12, 0, // Skip to: 8345 /* 5073 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5089 /* 5078 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5089 /* 5085 */ MCD_OPC_Decode, 162, 6, 67, // Opcode: SMUADX /* 5089 */ MCD_OPC_CheckPredicate, 1, 179, 12, 0, // Skip to: 8345 /* 5094 */ MCD_OPC_Decode, 139, 6, 68, // Opcode: SMLADX /* 5098 */ MCD_OPC_FilterValue, 2, 102, 0, 0, // Skip to: 5205 /* 5103 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 5106 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5138 /* 5111 */ MCD_OPC_CheckPredicate, 0, 157, 12, 0, // Skip to: 8345 /* 5116 */ MCD_OPC_CheckField, 20, 1, 1, 150, 12, 0, // Skip to: 8345 /* 5123 */ MCD_OPC_CheckField, 7, 1, 0, 143, 12, 0, // Skip to: 8345 /* 5130 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5134 */ MCD_OPC_Decode, 182, 6, 65, // Opcode: SSAX /* 5138 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5159 /* 5143 */ MCD_OPC_CheckPredicate, 1, 125, 12, 0, // Skip to: 8345 /* 5148 */ MCD_OPC_CheckField, 20, 1, 0, 118, 12, 0, // Skip to: 8345 /* 5155 */ MCD_OPC_Decode, 198, 5, 66, // Opcode: PKHTB /* 5159 */ MCD_OPC_FilterValue, 2, 109, 12, 0, // Skip to: 8345 /* 5164 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 5167 */ MCD_OPC_FilterValue, 0, 101, 12, 0, // Skip to: 8345 /* 5172 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5175 */ MCD_OPC_FilterValue, 0, 93, 12, 0, // Skip to: 8345 /* 5180 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5196 /* 5185 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5196 /* 5192 */ MCD_OPC_Decode, 170, 6, 67, // Opcode: SMUSD /* 5196 */ MCD_OPC_CheckPredicate, 1, 72, 12, 0, // Skip to: 8345 /* 5201 */ MCD_OPC_Decode, 151, 6, 68, // Opcode: SMLSD /* 5205 */ MCD_OPC_FilterValue, 3, 63, 12, 0, // Skip to: 8345 /* 5210 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 5213 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 5271 /* 5218 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 5221 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 5246 /* 5226 */ MCD_OPC_CheckPredicate, 0, 42, 12, 0, // Skip to: 8345 /* 5231 */ MCD_OPC_CheckField, 20, 1, 1, 35, 12, 0, // Skip to: 8345 /* 5238 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5242 */ MCD_OPC_Decode, 183, 6, 65, // Opcode: SSUB16 /* 5246 */ MCD_OPC_FilterValue, 1, 22, 12, 0, // Skip to: 8345 /* 5251 */ MCD_OPC_CheckPredicate, 0, 17, 12, 0, // Skip to: 8345 /* 5256 */ MCD_OPC_CheckField, 20, 1, 1, 10, 12, 0, // Skip to: 8345 /* 5263 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5267 */ MCD_OPC_Decode, 184, 6, 65, // Opcode: SSUB8 /* 5271 */ MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 5325 /* 5276 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 5279 */ MCD_OPC_FilterValue, 0, 245, 11, 0, // Skip to: 8345 /* 5284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5287 */ MCD_OPC_FilterValue, 0, 237, 11, 0, // Skip to: 8345 /* 5292 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5312 /* 5297 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5312 /* 5304 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 5308 */ MCD_OPC_Decode, 255, 6, 70, // Opcode: SXTB16 /* 5312 */ MCD_OPC_CheckPredicate, 1, 212, 11, 0, // Skip to: 8345 /* 5317 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 5321 */ MCD_OPC_Decode, 252, 6, 71, // Opcode: SXTAB16 /* 5325 */ MCD_OPC_FilterValue, 2, 199, 11, 0, // Skip to: 8345 /* 5330 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 5333 */ MCD_OPC_FilterValue, 0, 191, 11, 0, // Skip to: 8345 /* 5338 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5341 */ MCD_OPC_FilterValue, 0, 183, 11, 0, // Skip to: 8345 /* 5346 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5362 /* 5351 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5362 /* 5358 */ MCD_OPC_Decode, 171, 6, 67, // Opcode: SMUSDX /* 5362 */ MCD_OPC_CheckPredicate, 1, 162, 11, 0, // Skip to: 8345 /* 5367 */ MCD_OPC_Decode, 152, 6, 68, // Opcode: SMLSDX /* 5371 */ MCD_OPC_FilterValue, 1, 106, 2, 0, // Skip to: 5994 /* 5376 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 5379 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 5459 /* 5384 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5387 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5423 /* 5392 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 5395 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5409 /* 5400 */ MCD_OPC_CheckPredicate, 0, 124, 11, 0, // Skip to: 8345 /* 5405 */ MCD_OPC_Decode, 237, 6, 55, // Opcode: STRT_POST_REG /* 5409 */ MCD_OPC_FilterValue, 1, 115, 11, 0, // Skip to: 8345 /* 5414 */ MCD_OPC_CheckPredicate, 0, 110, 11, 0, // Skip to: 8345 /* 5419 */ MCD_OPC_Decode, 241, 6, 72, // Opcode: STR_PRE_REG /* 5423 */ MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 8345 /* 5428 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 5431 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5445 /* 5436 */ MCD_OPC_CheckPredicate, 0, 88, 11, 0, // Skip to: 8345 /* 5441 */ MCD_OPC_Decode, 156, 5, 55, // Opcode: LDRT_POST_REG /* 5445 */ MCD_OPC_FilterValue, 1, 79, 11, 0, // Skip to: 8345 /* 5450 */ MCD_OPC_CheckPredicate, 0, 74, 11, 0, // Skip to: 8345 /* 5455 */ MCD_OPC_Decode, 160, 5, 73, // Opcode: LDR_PRE_REG /* 5459 */ MCD_OPC_FilterValue, 1, 65, 11, 0, // Skip to: 8345 /* 5464 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 5467 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 5739 /* 5472 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 5475 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5519 /* 5480 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5483 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5501 /* 5488 */ MCD_OPC_CheckPredicate, 0, 36, 11, 0, // Skip to: 8345 /* 5493 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5497 */ MCD_OPC_Decode, 206, 5, 65, // Opcode: QADD16 /* 5501 */ MCD_OPC_FilterValue, 1, 23, 11, 0, // Skip to: 8345 /* 5506 */ MCD_OPC_CheckPredicate, 0, 18, 11, 0, // Skip to: 8345 /* 5511 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5515 */ MCD_OPC_Decode, 129, 6, 65, // Opcode: SHADD16 /* 5519 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5563 /* 5524 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5527 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5545 /* 5532 */ MCD_OPC_CheckPredicate, 0, 248, 10, 0, // Skip to: 8345 /* 5537 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5541 */ MCD_OPC_Decode, 208, 5, 65, // Opcode: QASX /* 5545 */ MCD_OPC_FilterValue, 1, 235, 10, 0, // Skip to: 8345 /* 5550 */ MCD_OPC_CheckPredicate, 0, 230, 10, 0, // Skip to: 8345 /* 5555 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5559 */ MCD_OPC_Decode, 131, 6, 65, // Opcode: SHASX /* 5563 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 5607 /* 5568 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5571 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5589 /* 5576 */ MCD_OPC_CheckPredicate, 0, 204, 10, 0, // Skip to: 8345 /* 5581 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5585 */ MCD_OPC_Decode, 211, 5, 65, // Opcode: QSAX /* 5589 */ MCD_OPC_FilterValue, 1, 191, 10, 0, // Skip to: 8345 /* 5594 */ MCD_OPC_CheckPredicate, 0, 186, 10, 0, // Skip to: 8345 /* 5599 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5603 */ MCD_OPC_Decode, 132, 6, 65, // Opcode: SHSAX /* 5607 */ MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 5651 /* 5612 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5615 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5633 /* 5620 */ MCD_OPC_CheckPredicate, 0, 160, 10, 0, // Skip to: 8345 /* 5625 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5629 */ MCD_OPC_Decode, 213, 5, 65, // Opcode: QSUB16 /* 5633 */ MCD_OPC_FilterValue, 1, 147, 10, 0, // Skip to: 8345 /* 5638 */ MCD_OPC_CheckPredicate, 0, 142, 10, 0, // Skip to: 8345 /* 5643 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5647 */ MCD_OPC_Decode, 133, 6, 65, // Opcode: SHSUB16 /* 5651 */ MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 5695 /* 5656 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5659 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5677 /* 5664 */ MCD_OPC_CheckPredicate, 0, 116, 10, 0, // Skip to: 8345 /* 5669 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5673 */ MCD_OPC_Decode, 207, 5, 65, // Opcode: QADD8 /* 5677 */ MCD_OPC_FilterValue, 1, 103, 10, 0, // Skip to: 8345 /* 5682 */ MCD_OPC_CheckPredicate, 0, 98, 10, 0, // Skip to: 8345 /* 5687 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5691 */ MCD_OPC_Decode, 130, 6, 65, // Opcode: SHADD8 /* 5695 */ MCD_OPC_FilterValue, 7, 85, 10, 0, // Skip to: 8345 /* 5700 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5703 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5721 /* 5708 */ MCD_OPC_CheckPredicate, 0, 72, 10, 0, // Skip to: 8345 /* 5713 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5717 */ MCD_OPC_Decode, 214, 5, 65, // Opcode: QSUB8 /* 5721 */ MCD_OPC_FilterValue, 1, 59, 10, 0, // Skip to: 8345 /* 5726 */ MCD_OPC_CheckPredicate, 0, 54, 10, 0, // Skip to: 8345 /* 5731 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 5735 */ MCD_OPC_Decode, 134, 6, 65, // Opcode: SHSUB8 /* 5739 */ MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 5938 /* 5744 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 5747 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5761 /* 5752 */ MCD_OPC_CheckPredicate, 1, 28, 10, 0, // Skip to: 8345 /* 5757 */ MCD_OPC_Decode, 180, 6, 74, // Opcode: SSAT /* 5761 */ MCD_OPC_FilterValue, 1, 19, 10, 0, // Skip to: 8345 /* 5766 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 5769 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5826 /* 5774 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5777 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5798 /* 5782 */ MCD_OPC_CheckPredicate, 1, 254, 9, 0, // Skip to: 8345 /* 5787 */ MCD_OPC_CheckField, 8, 4, 15, 247, 9, 0, // Skip to: 8345 /* 5794 */ MCD_OPC_Decode, 181, 6, 75, // Opcode: SSAT16 /* 5798 */ MCD_OPC_FilterValue, 1, 238, 9, 0, // Skip to: 8345 /* 5803 */ MCD_OPC_CheckPredicate, 1, 233, 9, 0, // Skip to: 8345 /* 5808 */ MCD_OPC_CheckField, 16, 4, 15, 226, 9, 0, // Skip to: 8345 /* 5815 */ MCD_OPC_CheckField, 8, 4, 15, 219, 9, 0, // Skip to: 8345 /* 5822 */ MCD_OPC_Decode, 216, 5, 35, // Opcode: REV /* 5826 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 5910 /* 5831 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5834 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5872 /* 5839 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5859 /* 5844 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5859 /* 5851 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 5855 */ MCD_OPC_Decode, 254, 6, 70, // Opcode: SXTB /* 5859 */ MCD_OPC_CheckPredicate, 1, 177, 9, 0, // Skip to: 8345 /* 5864 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 5868 */ MCD_OPC_Decode, 251, 6, 71, // Opcode: SXTAB /* 5872 */ MCD_OPC_FilterValue, 1, 164, 9, 0, // Skip to: 8345 /* 5877 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5897 /* 5882 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5897 /* 5889 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 5893 */ MCD_OPC_Decode, 128, 7, 70, // Opcode: SXTH /* 5897 */ MCD_OPC_CheckPredicate, 1, 139, 9, 0, // Skip to: 8345 /* 5902 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 5906 */ MCD_OPC_Decode, 253, 6, 71, // Opcode: SXTAH /* 5910 */ MCD_OPC_FilterValue, 2, 126, 9, 0, // Skip to: 8345 /* 5915 */ MCD_OPC_CheckPredicate, 1, 121, 9, 0, // Skip to: 8345 /* 5920 */ MCD_OPC_CheckField, 16, 5, 31, 114, 9, 0, // Skip to: 8345 /* 5927 */ MCD_OPC_CheckField, 8, 4, 15, 107, 9, 0, // Skip to: 8345 /* 5934 */ MCD_OPC_Decode, 217, 5, 35, // Opcode: REV16 /* 5938 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 5973 /* 5943 */ MCD_OPC_CheckPredicate, 19, 93, 9, 0, // Skip to: 8345 /* 5948 */ MCD_OPC_CheckField, 20, 1, 1, 86, 9, 0, // Skip to: 8345 /* 5955 */ MCD_OPC_CheckField, 12, 4, 15, 79, 9, 0, // Skip to: 8345 /* 5962 */ MCD_OPC_CheckField, 5, 3, 0, 72, 9, 0, // Skip to: 8345 /* 5969 */ MCD_OPC_Decode, 145, 7, 30, // Opcode: UDIV /* 5973 */ MCD_OPC_FilterValue, 3, 63, 9, 0, // Skip to: 8345 /* 5978 */ MCD_OPC_CheckPredicate, 13, 58, 9, 0, // Skip to: 8345 /* 5983 */ MCD_OPC_CheckField, 5, 2, 2, 51, 9, 0, // Skip to: 8345 /* 5990 */ MCD_OPC_Decode, 242, 5, 76, // Opcode: SBFX /* 5994 */ MCD_OPC_FilterValue, 2, 155, 2, 0, // Skip to: 6666 /* 5999 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 6002 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 6128 /* 6007 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6010 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6046 /* 6015 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 6018 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6032 /* 6023 */ MCD_OPC_CheckPredicate, 0, 13, 9, 0, // Skip to: 8345 /* 6028 */ MCD_OPC_Decode, 219, 6, 55, // Opcode: STRB_POST_REG /* 6032 */ MCD_OPC_FilterValue, 1, 4, 9, 0, // Skip to: 8345 /* 6037 */ MCD_OPC_CheckPredicate, 0, 255, 8, 0, // Skip to: 8345 /* 6042 */ MCD_OPC_Decode, 223, 6, 77, // Opcode: STRBrs /* 6046 */ MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 8345 /* 6051 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 6054 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 6091 /* 6059 */ MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 6082 /* 6064 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6082 /* 6071 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6082 /* 6078 */ MCD_OPC_Decode, 204, 5, 64, // Opcode: PLIrs /* 6082 */ MCD_OPC_CheckPredicate, 0, 210, 8, 0, // Skip to: 8345 /* 6087 */ MCD_OPC_Decode, 128, 5, 55, // Opcode: LDRB_POST_REG /* 6091 */ MCD_OPC_FilterValue, 1, 201, 8, 0, // Skip to: 8345 /* 6096 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 6119 /* 6101 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6119 /* 6108 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6119 /* 6115 */ MCD_OPC_Decode, 202, 5, 64, // Opcode: PLDrs /* 6119 */ MCD_OPC_CheckPredicate, 0, 173, 8, 0, // Skip to: 8345 /* 6124 */ MCD_OPC_Decode, 132, 5, 77, // Opcode: LDRBrs /* 6128 */ MCD_OPC_FilterValue, 1, 164, 8, 0, // Skip to: 8345 /* 6133 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 6136 */ MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6299 /* 6141 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 6144 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6202 /* 6149 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6152 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6177 /* 6157 */ MCD_OPC_CheckPredicate, 0, 135, 8, 0, // Skip to: 8345 /* 6162 */ MCD_OPC_CheckField, 20, 1, 1, 128, 8, 0, // Skip to: 8345 /* 6169 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6173 */ MCD_OPC_Decode, 140, 7, 65, // Opcode: UADD16 /* 6177 */ MCD_OPC_FilterValue, 1, 115, 8, 0, // Skip to: 8345 /* 6182 */ MCD_OPC_CheckPredicate, 0, 110, 8, 0, // Skip to: 8345 /* 6187 */ MCD_OPC_CheckField, 20, 1, 1, 103, 8, 0, // Skip to: 8345 /* 6194 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6198 */ MCD_OPC_Decode, 141, 7, 65, // Opcode: UADD8 /* 6202 */ MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 6269 /* 6207 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6210 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6231 /* 6215 */ MCD_OPC_CheckPredicate, 1, 77, 8, 0, // Skip to: 8345 /* 6220 */ MCD_OPC_CheckField, 7, 1, 0, 70, 8, 0, // Skip to: 8345 /* 6227 */ MCD_OPC_Decode, 143, 6, 19, // Opcode: SMLALD /* 6231 */ MCD_OPC_FilterValue, 1, 61, 8, 0, // Skip to: 8345 /* 6236 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6239 */ MCD_OPC_FilterValue, 0, 53, 8, 0, // Skip to: 8345 /* 6244 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6260 /* 6249 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6260 /* 6256 */ MCD_OPC_Decode, 159, 6, 30, // Opcode: SMMUL /* 6260 */ MCD_OPC_CheckPredicate, 1, 32, 8, 0, // Skip to: 8345 /* 6265 */ MCD_OPC_Decode, 155, 6, 39, // Opcode: SMMLA /* 6269 */ MCD_OPC_FilterValue, 3, 23, 8, 0, // Skip to: 8345 /* 6274 */ MCD_OPC_CheckPredicate, 13, 11, 0, 0, // Skip to: 6290 /* 6279 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 6290 /* 6286 */ MCD_OPC_Decode, 162, 4, 78, // Opcode: BFC /* 6290 */ MCD_OPC_CheckPredicate, 13, 2, 8, 0, // Skip to: 8345 /* 6295 */ MCD_OPC_Decode, 163, 4, 79, // Opcode: BFI /* 6299 */ MCD_OPC_FilterValue, 1, 102, 0, 0, // Skip to: 6406 /* 6304 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6307 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6335 /* 6312 */ MCD_OPC_CheckPredicate, 1, 236, 7, 0, // Skip to: 8345 /* 6317 */ MCD_OPC_CheckField, 23, 2, 2, 229, 7, 0, // Skip to: 8345 /* 6324 */ MCD_OPC_CheckField, 7, 1, 0, 222, 7, 0, // Skip to: 8345 /* 6331 */ MCD_OPC_Decode, 144, 6, 19, // Opcode: SMLALDX /* 6335 */ MCD_OPC_FilterValue, 1, 213, 7, 0, // Skip to: 8345 /* 6340 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 6343 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6368 /* 6348 */ MCD_OPC_CheckPredicate, 0, 200, 7, 0, // Skip to: 8345 /* 6353 */ MCD_OPC_CheckField, 7, 1, 0, 193, 7, 0, // Skip to: 8345 /* 6360 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6364 */ MCD_OPC_Decode, 142, 7, 65, // Opcode: UASX /* 6368 */ MCD_OPC_FilterValue, 2, 180, 7, 0, // Skip to: 8345 /* 6373 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6376 */ MCD_OPC_FilterValue, 0, 172, 7, 0, // Skip to: 8345 /* 6381 */ MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6397 /* 6386 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6397 /* 6393 */ MCD_OPC_Decode, 160, 6, 30, // Opcode: SMMULR /* 6397 */ MCD_OPC_CheckPredicate, 1, 151, 7, 0, // Skip to: 8345 /* 6402 */ MCD_OPC_Decode, 156, 6, 39, // Opcode: SMMLAR /* 6406 */ MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6496 /* 6411 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6414 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6468 /* 6419 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6422 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6443 /* 6427 */ MCD_OPC_CheckPredicate, 1, 121, 7, 0, // Skip to: 8345 /* 6432 */ MCD_OPC_CheckField, 23, 2, 2, 114, 7, 0, // Skip to: 8345 /* 6439 */ MCD_OPC_Decode, 153, 6, 19, // Opcode: SMLSLD /* 6443 */ MCD_OPC_FilterValue, 1, 105, 7, 0, // Skip to: 8345 /* 6448 */ MCD_OPC_CheckPredicate, 0, 100, 7, 0, // Skip to: 8345 /* 6453 */ MCD_OPC_CheckField, 23, 2, 0, 93, 7, 0, // Skip to: 8345 /* 6460 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6464 */ MCD_OPC_Decode, 165, 7, 65, // Opcode: USAX /* 6468 */ MCD_OPC_FilterValue, 1, 80, 7, 0, // Skip to: 8345 /* 6473 */ MCD_OPC_CheckPredicate, 1, 75, 7, 0, // Skip to: 8345 /* 6478 */ MCD_OPC_CheckField, 23, 2, 2, 68, 7, 0, // Skip to: 8345 /* 6485 */ MCD_OPC_CheckField, 20, 1, 1, 61, 7, 0, // Skip to: 8345 /* 6492 */ MCD_OPC_Decode, 157, 6, 39, // Opcode: SMMLS /* 6496 */ MCD_OPC_FilterValue, 3, 52, 7, 0, // Skip to: 8345 /* 6501 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 6504 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6562 /* 6509 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6512 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6537 /* 6517 */ MCD_OPC_CheckPredicate, 0, 31, 7, 0, // Skip to: 8345 /* 6522 */ MCD_OPC_CheckField, 20, 1, 1, 24, 7, 0, // Skip to: 8345 /* 6529 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6533 */ MCD_OPC_Decode, 166, 7, 65, // Opcode: USUB16 /* 6537 */ MCD_OPC_FilterValue, 1, 11, 7, 0, // Skip to: 8345 /* 6542 */ MCD_OPC_CheckPredicate, 0, 6, 7, 0, // Skip to: 8345 /* 6547 */ MCD_OPC_CheckField, 20, 1, 1, 255, 6, 0, // Skip to: 8345 /* 6554 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6558 */ MCD_OPC_Decode, 167, 7, 65, // Opcode: USUB8 /* 6562 */ MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 6616 /* 6567 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6570 */ MCD_OPC_FilterValue, 0, 234, 6, 0, // Skip to: 8345 /* 6575 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6578 */ MCD_OPC_FilterValue, 0, 226, 6, 0, // Skip to: 8345 /* 6583 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 6603 /* 6588 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 6603 /* 6595 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 6599 */ MCD_OPC_Decode, 172, 7, 70, // Opcode: UXTB16 /* 6603 */ MCD_OPC_CheckPredicate, 1, 201, 6, 0, // Skip to: 8345 /* 6608 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 6612 */ MCD_OPC_Decode, 169, 7, 71, // Opcode: UXTAB16 /* 6616 */ MCD_OPC_FilterValue, 2, 188, 6, 0, // Skip to: 8345 /* 6621 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6624 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6645 /* 6629 */ MCD_OPC_CheckPredicate, 1, 175, 6, 0, // Skip to: 8345 /* 6634 */ MCD_OPC_CheckField, 20, 1, 0, 168, 6, 0, // Skip to: 8345 /* 6641 */ MCD_OPC_Decode, 154, 6, 19, // Opcode: SMLSLDX /* 6645 */ MCD_OPC_FilterValue, 1, 159, 6, 0, // Skip to: 8345 /* 6650 */ MCD_OPC_CheckPredicate, 1, 154, 6, 0, // Skip to: 8345 /* 6655 */ MCD_OPC_CheckField, 20, 1, 1, 147, 6, 0, // Skip to: 8345 /* 6662 */ MCD_OPC_Decode, 158, 6, 39, // Opcode: SMMLSR /* 6666 */ MCD_OPC_FilterValue, 3, 138, 6, 0, // Skip to: 8345 /* 6671 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 6674 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 6754 /* 6679 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6682 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6718 /* 6687 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 6690 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6704 /* 6695 */ MCD_OPC_CheckPredicate, 0, 109, 6, 0, // Skip to: 8345 /* 6700 */ MCD_OPC_Decode, 217, 6, 55, // Opcode: STRBT_POST_REG /* 6704 */ MCD_OPC_FilterValue, 1, 100, 6, 0, // Skip to: 8345 /* 6709 */ MCD_OPC_CheckPredicate, 0, 95, 6, 0, // Skip to: 8345 /* 6714 */ MCD_OPC_Decode, 221, 6, 72, // Opcode: STRB_PRE_REG /* 6718 */ MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 8345 /* 6723 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 6726 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6740 /* 6731 */ MCD_OPC_CheckPredicate, 0, 73, 6, 0, // Skip to: 8345 /* 6736 */ MCD_OPC_Decode, 254, 4, 55, // Opcode: LDRBT_POST_REG /* 6740 */ MCD_OPC_FilterValue, 1, 64, 6, 0, // Skip to: 8345 /* 6745 */ MCD_OPC_CheckPredicate, 0, 59, 6, 0, // Skip to: 8345 /* 6750 */ MCD_OPC_Decode, 130, 5, 73, // Opcode: LDRB_PRE_REG /* 6754 */ MCD_OPC_FilterValue, 1, 50, 6, 0, // Skip to: 8345 /* 6759 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 6762 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 7034 /* 6767 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 6770 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 6814 /* 6775 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6778 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6796 /* 6783 */ MCD_OPC_CheckPredicate, 0, 21, 6, 0, // Skip to: 8345 /* 6788 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6792 */ MCD_OPC_Decode, 155, 7, 65, // Opcode: UQADD16 /* 6796 */ MCD_OPC_FilterValue, 1, 8, 6, 0, // Skip to: 8345 /* 6801 */ MCD_OPC_CheckPredicate, 0, 3, 6, 0, // Skip to: 8345 /* 6806 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6810 */ MCD_OPC_Decode, 146, 7, 65, // Opcode: UHADD16 /* 6814 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 6858 /* 6819 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6822 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6840 /* 6827 */ MCD_OPC_CheckPredicate, 0, 233, 5, 0, // Skip to: 8345 /* 6832 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6836 */ MCD_OPC_Decode, 157, 7, 65, // Opcode: UQASX /* 6840 */ MCD_OPC_FilterValue, 1, 220, 5, 0, // Skip to: 8345 /* 6845 */ MCD_OPC_CheckPredicate, 0, 215, 5, 0, // Skip to: 8345 /* 6850 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6854 */ MCD_OPC_Decode, 148, 7, 65, // Opcode: UHASX /* 6858 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 6902 /* 6863 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6866 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6884 /* 6871 */ MCD_OPC_CheckPredicate, 0, 189, 5, 0, // Skip to: 8345 /* 6876 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6880 */ MCD_OPC_Decode, 158, 7, 65, // Opcode: UQSAX /* 6884 */ MCD_OPC_FilterValue, 1, 176, 5, 0, // Skip to: 8345 /* 6889 */ MCD_OPC_CheckPredicate, 0, 171, 5, 0, // Skip to: 8345 /* 6894 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6898 */ MCD_OPC_Decode, 149, 7, 65, // Opcode: UHSAX /* 6902 */ MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 6946 /* 6907 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6910 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6928 /* 6915 */ MCD_OPC_CheckPredicate, 0, 145, 5, 0, // Skip to: 8345 /* 6920 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6924 */ MCD_OPC_Decode, 159, 7, 65, // Opcode: UQSUB16 /* 6928 */ MCD_OPC_FilterValue, 1, 132, 5, 0, // Skip to: 8345 /* 6933 */ MCD_OPC_CheckPredicate, 0, 127, 5, 0, // Skip to: 8345 /* 6938 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6942 */ MCD_OPC_Decode, 150, 7, 65, // Opcode: UHSUB16 /* 6946 */ MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 6990 /* 6951 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6954 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6972 /* 6959 */ MCD_OPC_CheckPredicate, 0, 101, 5, 0, // Skip to: 8345 /* 6964 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6968 */ MCD_OPC_Decode, 156, 7, 65, // Opcode: UQADD8 /* 6972 */ MCD_OPC_FilterValue, 1, 88, 5, 0, // Skip to: 8345 /* 6977 */ MCD_OPC_CheckPredicate, 0, 83, 5, 0, // Skip to: 8345 /* 6982 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 6986 */ MCD_OPC_Decode, 147, 7, 65, // Opcode: UHADD8 /* 6990 */ MCD_OPC_FilterValue, 7, 70, 5, 0, // Skip to: 8345 /* 6995 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6998 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 7016 /* 7003 */ MCD_OPC_CheckPredicate, 0, 57, 5, 0, // Skip to: 8345 /* 7008 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 7012 */ MCD_OPC_Decode, 160, 7, 65, // Opcode: UQSUB8 /* 7016 */ MCD_OPC_FilterValue, 1, 44, 5, 0, // Skip to: 8345 /* 7021 */ MCD_OPC_CheckPredicate, 0, 39, 5, 0, // Skip to: 8345 /* 7026 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */, /* 7030 */ MCD_OPC_Decode, 151, 7, 65, // Opcode: UHSUB8 /* 7034 */ MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 7233 /* 7039 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 7042 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7056 /* 7047 */ MCD_OPC_CheckPredicate, 1, 13, 5, 0, // Skip to: 8345 /* 7052 */ MCD_OPC_Decode, 163, 7, 74, // Opcode: USAT /* 7056 */ MCD_OPC_FilterValue, 1, 4, 5, 0, // Skip to: 8345 /* 7061 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7064 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 7121 /* 7069 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7072 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7093 /* 7077 */ MCD_OPC_CheckPredicate, 1, 239, 4, 0, // Skip to: 8345 /* 7082 */ MCD_OPC_CheckField, 8, 4, 15, 232, 4, 0, // Skip to: 8345 /* 7089 */ MCD_OPC_Decode, 164, 7, 75, // Opcode: USAT16 /* 7093 */ MCD_OPC_FilterValue, 1, 223, 4, 0, // Skip to: 8345 /* 7098 */ MCD_OPC_CheckPredicate, 13, 218, 4, 0, // Skip to: 8345 /* 7103 */ MCD_OPC_CheckField, 16, 4, 15, 211, 4, 0, // Skip to: 8345 /* 7110 */ MCD_OPC_CheckField, 8, 4, 15, 204, 4, 0, // Skip to: 8345 /* 7117 */ MCD_OPC_Decode, 215, 5, 35, // Opcode: RBIT /* 7121 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 7205 /* 7126 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7129 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7167 /* 7134 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7154 /* 7139 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7154 /* 7146 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 7150 */ MCD_OPC_Decode, 171, 7, 70, // Opcode: UXTB /* 7154 */ MCD_OPC_CheckPredicate, 1, 162, 4, 0, // Skip to: 8345 /* 7159 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 7163 */ MCD_OPC_Decode, 168, 7, 71, // Opcode: UXTAB /* 7167 */ MCD_OPC_FilterValue, 1, 149, 4, 0, // Skip to: 8345 /* 7172 */ MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7192 /* 7177 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7192 /* 7184 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 7188 */ MCD_OPC_Decode, 173, 7, 70, // Opcode: UXTH /* 7192 */ MCD_OPC_CheckPredicate, 1, 124, 4, 0, // Skip to: 8345 /* 7197 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, /* 7201 */ MCD_OPC_Decode, 170, 7, 71, // Opcode: UXTAH /* 7205 */ MCD_OPC_FilterValue, 2, 111, 4, 0, // Skip to: 8345 /* 7210 */ MCD_OPC_CheckPredicate, 1, 106, 4, 0, // Skip to: 8345 /* 7215 */ MCD_OPC_CheckField, 16, 5, 31, 99, 4, 0, // Skip to: 8345 /* 7222 */ MCD_OPC_CheckField, 8, 4, 15, 92, 4, 0, // Skip to: 8345 /* 7229 */ MCD_OPC_Decode, 218, 5, 35, // Opcode: REVSH /* 7233 */ MCD_OPC_FilterValue, 3, 83, 4, 0, // Skip to: 8345 /* 7238 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 7241 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7255 /* 7246 */ MCD_OPC_CheckPredicate, 13, 70, 4, 0, // Skip to: 8345 /* 7251 */ MCD_OPC_Decode, 143, 7, 76, // Opcode: UBFX /* 7255 */ MCD_OPC_FilterValue, 3, 61, 4, 0, // Skip to: 8345 /* 7260 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 7263 */ MCD_OPC_FilterValue, 1, 53, 4, 0, // Skip to: 8345 /* 7268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7271 */ MCD_OPC_FilterValue, 1, 45, 4, 0, // Skip to: 8345 /* 7276 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... /* 7279 */ MCD_OPC_FilterValue, 14, 37, 4, 0, // Skip to: 8345 /* 7284 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 7287 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7309 /* 7292 */ MCD_OPC_CheckPredicate, 20, 34, 0, 0, // Skip to: 7331 /* 7297 */ MCD_OPC_CheckField, 8, 12, 222, 29, 26, 0, 0, // Skip to: 7331 /* 7305 */ MCD_OPC_Decode, 134, 7, 51, // Opcode: TRAPNaCl /* 7309 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7331 /* 7314 */ MCD_OPC_CheckPredicate, 0, 12, 0, 0, // Skip to: 7331 /* 7319 */ MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, 0, // Skip to: 7331 /* 7327 */ MCD_OPC_Decode, 133, 7, 51, // Opcode: TRAP /* 7331 */ MCD_OPC_CheckPredicate, 0, 241, 3, 0, // Skip to: 8345 /* 7336 */ MCD_OPC_Decode, 144, 7, 15, // Opcode: UDF /* 7340 */ MCD_OPC_FilterValue, 4, 75, 3, 0, // Skip to: 8188 /* 7345 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... /* 7348 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7362 /* 7353 */ MCD_OPC_CheckPredicate, 0, 219, 3, 0, // Skip to: 8345 /* 7358 */ MCD_OPC_Decode, 208, 6, 80, // Opcode: STMDA /* 7362 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 7400 /* 7367 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7391 /* 7372 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7391 /* 7379 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7391 /* 7387 */ MCD_OPC_Decode, 219, 5, 81, // Opcode: RFEDA /* 7391 */ MCD_OPC_CheckPredicate, 0, 181, 3, 0, // Skip to: 8345 /* 7396 */ MCD_OPC_Decode, 245, 4, 80, // Opcode: LDMDA /* 7400 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7414 /* 7405 */ MCD_OPC_CheckPredicate, 0, 167, 3, 0, // Skip to: 8345 /* 7410 */ MCD_OPC_Decode, 209, 6, 82, // Opcode: STMDA_UPD /* 7414 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 7452 /* 7419 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7443 /* 7424 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7443 /* 7431 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7443 /* 7439 */ MCD_OPC_Decode, 220, 5, 81, // Opcode: RFEDA_UPD /* 7443 */ MCD_OPC_CheckPredicate, 0, 129, 3, 0, // Skip to: 8345 /* 7448 */ MCD_OPC_Decode, 246, 4, 82, // Opcode: LDMDA_UPD /* 7452 */ MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 7491 /* 7457 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7482 /* 7462 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7482 /* 7469 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7482 /* 7478 */ MCD_OPC_Decode, 172, 6, 83, // Opcode: SRSDA /* 7482 */ MCD_OPC_CheckPredicate, 0, 90, 3, 0, // Skip to: 8345 /* 7487 */ MCD_OPC_Decode, 190, 21, 80, // Opcode: sysSTMDA /* 7491 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 7505 /* 7496 */ MCD_OPC_CheckPredicate, 0, 76, 3, 0, // Skip to: 8345 /* 7501 */ MCD_OPC_Decode, 182, 21, 80, // Opcode: sysLDMDA /* 7505 */ MCD_OPC_FilterValue, 6, 34, 0, 0, // Skip to: 7544 /* 7510 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7535 /* 7515 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7535 /* 7522 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7535 /* 7531 */ MCD_OPC_Decode, 173, 6, 83, // Opcode: SRSDA_UPD /* 7535 */ MCD_OPC_CheckPredicate, 0, 37, 3, 0, // Skip to: 8345 /* 7540 */ MCD_OPC_Decode, 191, 21, 82, // Opcode: sysSTMDA_UPD /* 7544 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 7558 /* 7549 */ MCD_OPC_CheckPredicate, 0, 23, 3, 0, // Skip to: 8345 /* 7554 */ MCD_OPC_Decode, 183, 21, 82, // Opcode: sysLDMDA_UPD /* 7558 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7572 /* 7563 */ MCD_OPC_CheckPredicate, 0, 9, 3, 0, // Skip to: 8345 /* 7568 */ MCD_OPC_Decode, 212, 6, 80, // Opcode: STMIA /* 7572 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 7610 /* 7577 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7601 /* 7582 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7601 /* 7589 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7601 /* 7597 */ MCD_OPC_Decode, 223, 5, 81, // Opcode: RFEIA /* 7601 */ MCD_OPC_CheckPredicate, 0, 227, 2, 0, // Skip to: 8345 /* 7606 */ MCD_OPC_Decode, 249, 4, 80, // Opcode: LDMIA /* 7610 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7624 /* 7615 */ MCD_OPC_CheckPredicate, 0, 213, 2, 0, // Skip to: 8345 /* 7620 */ MCD_OPC_Decode, 213, 6, 82, // Opcode: STMIA_UPD /* 7624 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 7662 /* 7629 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7653 /* 7634 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7653 /* 7641 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7653 /* 7649 */ MCD_OPC_Decode, 224, 5, 81, // Opcode: RFEIA_UPD /* 7653 */ MCD_OPC_CheckPredicate, 0, 175, 2, 0, // Skip to: 8345 /* 7658 */ MCD_OPC_Decode, 250, 4, 82, // Opcode: LDMIA_UPD /* 7662 */ MCD_OPC_FilterValue, 12, 34, 0, 0, // Skip to: 7701 /* 7667 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7692 /* 7672 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7692 /* 7679 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7692 /* 7688 */ MCD_OPC_Decode, 176, 6, 83, // Opcode: SRSIA /* 7692 */ MCD_OPC_CheckPredicate, 0, 136, 2, 0, // Skip to: 8345 /* 7697 */ MCD_OPC_Decode, 194, 21, 80, // Opcode: sysSTMIA /* 7701 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 7715 /* 7706 */ MCD_OPC_CheckPredicate, 0, 122, 2, 0, // Skip to: 8345 /* 7711 */ MCD_OPC_Decode, 186, 21, 80, // Opcode: sysLDMIA /* 7715 */ MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 7754 /* 7720 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7745 /* 7725 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7745 /* 7732 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7745 /* 7741 */ MCD_OPC_Decode, 177, 6, 83, // Opcode: SRSIA_UPD /* 7745 */ MCD_OPC_CheckPredicate, 0, 83, 2, 0, // Skip to: 8345 /* 7750 */ MCD_OPC_Decode, 195, 21, 82, // Opcode: sysSTMIA_UPD /* 7754 */ MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 7768 /* 7759 */ MCD_OPC_CheckPredicate, 0, 69, 2, 0, // Skip to: 8345 /* 7764 */ MCD_OPC_Decode, 187, 21, 82, // Opcode: sysLDMIA_UPD /* 7768 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 7782 /* 7773 */ MCD_OPC_CheckPredicate, 0, 55, 2, 0, // Skip to: 8345 /* 7778 */ MCD_OPC_Decode, 210, 6, 80, // Opcode: STMDB /* 7782 */ MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 7820 /* 7787 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7811 /* 7792 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7811 /* 7799 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7811 /* 7807 */ MCD_OPC_Decode, 221, 5, 81, // Opcode: RFEDB /* 7811 */ MCD_OPC_CheckPredicate, 0, 17, 2, 0, // Skip to: 8345 /* 7816 */ MCD_OPC_Decode, 247, 4, 80, // Opcode: LDMDB /* 7820 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 7834 /* 7825 */ MCD_OPC_CheckPredicate, 0, 3, 2, 0, // Skip to: 8345 /* 7830 */ MCD_OPC_Decode, 211, 6, 82, // Opcode: STMDB_UPD /* 7834 */ MCD_OPC_FilterValue, 19, 33, 0, 0, // Skip to: 7872 /* 7839 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7863 /* 7844 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7863 /* 7851 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7863 /* 7859 */ MCD_OPC_Decode, 222, 5, 81, // Opcode: RFEDB_UPD /* 7863 */ MCD_OPC_CheckPredicate, 0, 221, 1, 0, // Skip to: 8345 /* 7868 */ MCD_OPC_Decode, 248, 4, 82, // Opcode: LDMDB_UPD /* 7872 */ MCD_OPC_FilterValue, 20, 34, 0, 0, // Skip to: 7911 /* 7877 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7902 /* 7882 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7902 /* 7889 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7902 /* 7898 */ MCD_OPC_Decode, 174, 6, 83, // Opcode: SRSDB /* 7902 */ MCD_OPC_CheckPredicate, 0, 182, 1, 0, // Skip to: 8345 /* 7907 */ MCD_OPC_Decode, 192, 21, 80, // Opcode: sysSTMDB /* 7911 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 7925 /* 7916 */ MCD_OPC_CheckPredicate, 0, 168, 1, 0, // Skip to: 8345 /* 7921 */ MCD_OPC_Decode, 184, 21, 80, // Opcode: sysLDMDB /* 7925 */ MCD_OPC_FilterValue, 22, 34, 0, 0, // Skip to: 7964 /* 7930 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7955 /* 7935 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7955 /* 7942 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7955 /* 7951 */ MCD_OPC_Decode, 175, 6, 83, // Opcode: SRSDB_UPD /* 7955 */ MCD_OPC_CheckPredicate, 0, 129, 1, 0, // Skip to: 8345 /* 7960 */ MCD_OPC_Decode, 193, 21, 82, // Opcode: sysSTMDB_UPD /* 7964 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 7978 /* 7969 */ MCD_OPC_CheckPredicate, 0, 115, 1, 0, // Skip to: 8345 /* 7974 */ MCD_OPC_Decode, 185, 21, 82, // Opcode: sysLDMDB_UPD /* 7978 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 7992 /* 7983 */ MCD_OPC_CheckPredicate, 0, 101, 1, 0, // Skip to: 8345 /* 7988 */ MCD_OPC_Decode, 214, 6, 80, // Opcode: STMIB /* 7992 */ MCD_OPC_FilterValue, 25, 33, 0, 0, // Skip to: 8030 /* 7997 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8021 /* 8002 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8021 /* 8009 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8021 /* 8017 */ MCD_OPC_Decode, 225, 5, 81, // Opcode: RFEIB /* 8021 */ MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 8345 /* 8026 */ MCD_OPC_Decode, 251, 4, 80, // Opcode: LDMIB /* 8030 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 8044 /* 8035 */ MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 8345 /* 8040 */ MCD_OPC_Decode, 215, 6, 82, // Opcode: STMIB_UPD /* 8044 */ MCD_OPC_FilterValue, 27, 33, 0, 0, // Skip to: 8082 /* 8049 */ MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8073 /* 8054 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8073 /* 8061 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8073 /* 8069 */ MCD_OPC_Decode, 226, 5, 81, // Opcode: RFEIB_UPD /* 8073 */ MCD_OPC_CheckPredicate, 0, 11, 1, 0, // Skip to: 8345 /* 8078 */ MCD_OPC_Decode, 252, 4, 82, // Opcode: LDMIB_UPD /* 8082 */ MCD_OPC_FilterValue, 28, 34, 0, 0, // Skip to: 8121 /* 8087 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8112 /* 8092 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8112 /* 8099 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8112 /* 8108 */ MCD_OPC_Decode, 178, 6, 83, // Opcode: SRSIB /* 8112 */ MCD_OPC_CheckPredicate, 0, 228, 0, 0, // Skip to: 8345 /* 8117 */ MCD_OPC_Decode, 196, 21, 80, // Opcode: sysSTMIB /* 8121 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 8135 /* 8126 */ MCD_OPC_CheckPredicate, 0, 214, 0, 0, // Skip to: 8345 /* 8131 */ MCD_OPC_Decode, 188, 21, 80, // Opcode: sysLDMIB /* 8135 */ MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 8174 /* 8140 */ MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8165 /* 8145 */ MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8165 /* 8152 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8165 /* 8161 */ MCD_OPC_Decode, 179, 6, 83, // Opcode: SRSIB_UPD /* 8165 */ MCD_OPC_CheckPredicate, 0, 175, 0, 0, // Skip to: 8345 /* 8170 */ MCD_OPC_Decode, 197, 21, 82, // Opcode: sysSTMIB_UPD /* 8174 */ MCD_OPC_FilterValue, 31, 166, 0, 0, // Skip to: 8345 /* 8179 */ MCD_OPC_CheckPredicate, 0, 161, 0, 0, // Skip to: 8345 /* 8184 */ MCD_OPC_Decode, 189, 21, 82, // Opcode: sysLDMIB_UPD /* 8188 */ MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8256 /* 8193 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 8196 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8210 /* 8201 */ MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 8240 /* 8206 */ MCD_OPC_Decode, 178, 4, 84, // Opcode: Bcc /* 8210 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 8240 /* 8215 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8231 /* 8220 */ MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 8231 /* 8227 */ MCD_OPC_Decode, 169, 4, 84, // Opcode: BL /* 8231 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 8240 /* 8236 */ MCD_OPC_Decode, 173, 4, 84, // Opcode: BL_pred /* 8240 */ MCD_OPC_CheckPredicate, 11, 100, 0, 0, // Skip to: 8345 /* 8245 */ MCD_OPC_CheckField, 28, 4, 15, 93, 0, 0, // Skip to: 8345 /* 8252 */ MCD_OPC_Decode, 172, 4, 85, // Opcode: BLXi /* 8256 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 8324 /* 8261 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... /* 8264 */ MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 8294 /* 8269 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8285 /* 8274 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8285 /* 8281 */ MCD_OPC_Decode, 167, 5, 86, // Opcode: MCRR2 /* 8285 */ MCD_OPC_CheckPredicate, 0, 55, 0, 0, // Skip to: 8345 /* 8290 */ MCD_OPC_Decode, 166, 5, 87, // Opcode: MCRR /* 8294 */ MCD_OPC_FilterValue, 5, 46, 0, 0, // Skip to: 8345 /* 8299 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8315 /* 8304 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8315 /* 8311 */ MCD_OPC_Decode, 181, 5, 86, // Opcode: MRRC2 /* 8315 */ MCD_OPC_CheckPredicate, 0, 25, 0, 0, // Skip to: 8345 /* 8320 */ MCD_OPC_Decode, 180, 5, 88, // Opcode: MRRC /* 8324 */ MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 8345 /* 8329 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8345 /* 8334 */ MCD_OPC_CheckField, 24, 1, 1, 4, 0, 0, // Skip to: 8345 /* 8341 */ MCD_OPC_Decode, 248, 6, 89, // Opcode: SVC /* 8345 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableCoProc32[] = { /* 0 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 3 */ MCD_OPC_FilterValue, 12, 19, 1, 0, // Skip to: 283 /* 8 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 11 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 49 /* 16 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 19 */ MCD_OPC_FilterValue, 1, 101, 2, 0, // Skip to: 637 /* 24 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 40 /* 29 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 40 /* 36 */ MCD_OPC_Decode, 190, 6, 90, // Opcode: STC2_OPTION /* 40 */ MCD_OPC_CheckPredicate, 0, 80, 2, 0, // Skip to: 637 /* 45 */ MCD_OPC_Decode, 198, 6, 90, // Opcode: STC_OPTION /* 49 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 87 /* 54 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 57 */ MCD_OPC_FilterValue, 1, 63, 2, 0, // Skip to: 637 /* 62 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 78 /* 67 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 78 /* 74 */ MCD_OPC_Decode, 234, 4, 90, // Opcode: LDC2_OPTION /* 78 */ MCD_OPC_CheckPredicate, 0, 42, 2, 0, // Skip to: 637 /* 83 */ MCD_OPC_Decode, 242, 4, 90, // Opcode: LDC_OPTION /* 87 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 117 /* 92 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 108 /* 97 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 108 /* 104 */ MCD_OPC_Decode, 191, 6, 90, // Opcode: STC2_POST /* 108 */ MCD_OPC_CheckPredicate, 0, 12, 2, 0, // Skip to: 637 /* 113 */ MCD_OPC_Decode, 199, 6, 90, // Opcode: STC_POST /* 117 */ MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 147 /* 122 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 138 /* 127 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 138 /* 134 */ MCD_OPC_Decode, 235, 4, 90, // Opcode: LDC2_POST /* 138 */ MCD_OPC_CheckPredicate, 0, 238, 1, 0, // Skip to: 637 /* 143 */ MCD_OPC_Decode, 243, 4, 90, // Opcode: LDC_POST /* 147 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 185 /* 152 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 155 */ MCD_OPC_FilterValue, 1, 221, 1, 0, // Skip to: 637 /* 160 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 176 /* 165 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 176 /* 172 */ MCD_OPC_Decode, 186, 6, 90, // Opcode: STC2L_OPTION /* 176 */ MCD_OPC_CheckPredicate, 0, 200, 1, 0, // Skip to: 637 /* 181 */ MCD_OPC_Decode, 194, 6, 90, // Opcode: STCL_OPTION /* 185 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 223 /* 190 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 193 */ MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 637 /* 198 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 214 /* 203 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 214 /* 210 */ MCD_OPC_Decode, 230, 4, 90, // Opcode: LDC2L_OPTION /* 214 */ MCD_OPC_CheckPredicate, 0, 162, 1, 0, // Skip to: 637 /* 219 */ MCD_OPC_Decode, 238, 4, 90, // Opcode: LDCL_OPTION /* 223 */ MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 253 /* 228 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 244 /* 233 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 244 /* 240 */ MCD_OPC_Decode, 187, 6, 90, // Opcode: STC2L_POST /* 244 */ MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 637 /* 249 */ MCD_OPC_Decode, 195, 6, 90, // Opcode: STCL_POST /* 253 */ MCD_OPC_FilterValue, 7, 123, 1, 0, // Skip to: 637 /* 258 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 274 /* 263 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 274 /* 270 */ MCD_OPC_Decode, 231, 4, 90, // Opcode: LDC2L_POST /* 274 */ MCD_OPC_CheckPredicate, 0, 102, 1, 0, // Skip to: 637 /* 279 */ MCD_OPC_Decode, 239, 4, 90, // Opcode: LDCL_POST /* 283 */ MCD_OPC_FilterValue, 13, 243, 0, 0, // Skip to: 531 /* 288 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 291 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 321 /* 296 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 312 /* 301 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 312 /* 308 */ MCD_OPC_Decode, 189, 6, 90, // Opcode: STC2_OFFSET /* 312 */ MCD_OPC_CheckPredicate, 0, 64, 1, 0, // Skip to: 637 /* 317 */ MCD_OPC_Decode, 197, 6, 90, // Opcode: STC_OFFSET /* 321 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 351 /* 326 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 342 /* 331 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 342 /* 338 */ MCD_OPC_Decode, 233, 4, 90, // Opcode: LDC2_OFFSET /* 342 */ MCD_OPC_CheckPredicate, 0, 34, 1, 0, // Skip to: 637 /* 347 */ MCD_OPC_Decode, 241, 4, 90, // Opcode: LDC_OFFSET /* 351 */ MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 381 /* 356 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 372 /* 361 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 372 /* 368 */ MCD_OPC_Decode, 192, 6, 90, // Opcode: STC2_PRE /* 372 */ MCD_OPC_CheckPredicate, 0, 4, 1, 0, // Skip to: 637 /* 377 */ MCD_OPC_Decode, 200, 6, 90, // Opcode: STC_PRE /* 381 */ MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 411 /* 386 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 402 /* 391 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 402 /* 398 */ MCD_OPC_Decode, 236, 4, 90, // Opcode: LDC2_PRE /* 402 */ MCD_OPC_CheckPredicate, 0, 230, 0, 0, // Skip to: 637 /* 407 */ MCD_OPC_Decode, 244, 4, 90, // Opcode: LDC_PRE /* 411 */ MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 441 /* 416 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 432 /* 421 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 432 /* 428 */ MCD_OPC_Decode, 185, 6, 90, // Opcode: STC2L_OFFSET /* 432 */ MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 637 /* 437 */ MCD_OPC_Decode, 193, 6, 90, // Opcode: STCL_OFFSET /* 441 */ MCD_OPC_FilterValue, 5, 25, 0, 0, // Skip to: 471 /* 446 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 462 /* 451 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 462 /* 458 */ MCD_OPC_Decode, 229, 4, 90, // Opcode: LDC2L_OFFSET /* 462 */ MCD_OPC_CheckPredicate, 0, 170, 0, 0, // Skip to: 637 /* 467 */ MCD_OPC_Decode, 237, 4, 90, // Opcode: LDCL_OFFSET /* 471 */ MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 501 /* 476 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 492 /* 481 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 492 /* 488 */ MCD_OPC_Decode, 188, 6, 90, // Opcode: STC2L_PRE /* 492 */ MCD_OPC_CheckPredicate, 0, 140, 0, 0, // Skip to: 637 /* 497 */ MCD_OPC_Decode, 196, 6, 90, // Opcode: STCL_PRE /* 501 */ MCD_OPC_FilterValue, 7, 131, 0, 0, // Skip to: 637 /* 506 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 522 /* 511 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 522 /* 518 */ MCD_OPC_Decode, 232, 4, 90, // Opcode: LDC2L_PRE /* 522 */ MCD_OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 637 /* 527 */ MCD_OPC_Decode, 240, 4, 90, // Opcode: LDCL_PRE /* 531 */ MCD_OPC_FilterValue, 14, 101, 0, 0, // Skip to: 637 /* 536 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 539 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 569 /* 544 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 560 /* 549 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 560 /* 556 */ MCD_OPC_Decode, 180, 4, 91, // Opcode: CDP2 /* 560 */ MCD_OPC_CheckPredicate, 4, 72, 0, 0, // Skip to: 637 /* 565 */ MCD_OPC_Decode, 179, 4, 92, // Opcode: CDP /* 569 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 637 /* 574 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 577 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 607 /* 582 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 598 /* 587 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 598 /* 594 */ MCD_OPC_Decode, 165, 5, 93, // Opcode: MCR2 /* 598 */ MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 637 /* 603 */ MCD_OPC_Decode, 164, 5, 94, // Opcode: MCR /* 607 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 637 /* 612 */ MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 628 /* 617 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 628 /* 624 */ MCD_OPC_Decode, 179, 5, 95, // Opcode: MRC2 /* 628 */ MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 637 /* 633 */ MCD_OPC_Decode, 178, 5, 96, // Opcode: MRC /* 637 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableNEONData32[] = { /* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 3 */ MCD_OPC_FilterValue, 0, 221, 39, 0, // Skip to: 10213 /* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11 */ MCD_OPC_FilterValue, 0, 73, 6, 0, // Skip to: 1625 /* 16 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 19 */ MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 145 /* 24 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 27 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 64 /* 33 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 36 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 50 /* 41 */ MCD_OPC_CheckPredicate, 21, 75, 72, 0, // Skip to: 18553 /* 46 */ MCD_OPC_Decode, 179, 10, 97, // Opcode: VHADDsv8i8 /* 50 */ MCD_OPC_FilterValue, 1, 66, 72, 0, // Skip to: 18553 /* 55 */ MCD_OPC_CheckPredicate, 21, 61, 72, 0, // Skip to: 18553 /* 60 */ MCD_OPC_Decode, 174, 10, 98, // Opcode: VHADDsv16i8 /* 64 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 86 /* 70 */ MCD_OPC_CheckPredicate, 21, 46, 72, 0, // Skip to: 18553 /* 75 */ MCD_OPC_CheckField, 6, 1, 0, 39, 72, 0, // Skip to: 18553 /* 82 */ MCD_OPC_Decode, 242, 7, 99, // Opcode: VADDLsv8i16 /* 86 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 123 /* 92 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 95 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109 /* 100 */ MCD_OPC_CheckPredicate, 21, 16, 72, 0, // Skip to: 18553 /* 105 */ MCD_OPC_Decode, 185, 10, 97, // Opcode: VHADDuv8i8 /* 109 */ MCD_OPC_FilterValue, 1, 7, 72, 0, // Skip to: 18553 /* 114 */ MCD_OPC_CheckPredicate, 21, 2, 72, 0, // Skip to: 18553 /* 119 */ MCD_OPC_Decode, 180, 10, 98, // Opcode: VHADDuv16i8 /* 123 */ MCD_OPC_FilterValue, 231, 3, 248, 71, 0, // Skip to: 18553 /* 129 */ MCD_OPC_CheckPredicate, 21, 243, 71, 0, // Skip to: 18553 /* 134 */ MCD_OPC_CheckField, 6, 1, 0, 236, 71, 0, // Skip to: 18553 /* 141 */ MCD_OPC_Decode, 245, 7, 99, // Opcode: VADDLuv8i16 /* 145 */ MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 271 /* 150 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 153 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 190 /* 159 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 176 /* 167 */ MCD_OPC_CheckPredicate, 21, 205, 71, 0, // Skip to: 18553 /* 172 */ MCD_OPC_Decode, 240, 16, 97, // Opcode: VRHADDsv8i8 /* 176 */ MCD_OPC_FilterValue, 1, 196, 71, 0, // Skip to: 18553 /* 181 */ MCD_OPC_CheckPredicate, 21, 191, 71, 0, // Skip to: 18553 /* 186 */ MCD_OPC_Decode, 235, 16, 98, // Opcode: VRHADDsv16i8 /* 190 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 212 /* 196 */ MCD_OPC_CheckPredicate, 21, 176, 71, 0, // Skip to: 18553 /* 201 */ MCD_OPC_CheckField, 6, 1, 0, 169, 71, 0, // Skip to: 18553 /* 208 */ MCD_OPC_Decode, 249, 7, 100, // Opcode: VADDWsv8i16 /* 212 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 249 /* 218 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 221 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 235 /* 226 */ MCD_OPC_CheckPredicate, 21, 146, 71, 0, // Skip to: 18553 /* 231 */ MCD_OPC_Decode, 246, 16, 97, // Opcode: VRHADDuv8i8 /* 235 */ MCD_OPC_FilterValue, 1, 137, 71, 0, // Skip to: 18553 /* 240 */ MCD_OPC_CheckPredicate, 21, 132, 71, 0, // Skip to: 18553 /* 245 */ MCD_OPC_Decode, 241, 16, 98, // Opcode: VRHADDuv16i8 /* 249 */ MCD_OPC_FilterValue, 231, 3, 122, 71, 0, // Skip to: 18553 /* 255 */ MCD_OPC_CheckPredicate, 21, 117, 71, 0, // Skip to: 18553 /* 260 */ MCD_OPC_CheckField, 6, 1, 0, 110, 71, 0, // Skip to: 18553 /* 267 */ MCD_OPC_Decode, 252, 7, 100, // Opcode: VADDWuv8i16 /* 271 */ MCD_OPC_FilterValue, 2, 121, 0, 0, // Skip to: 397 /* 276 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 279 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 316 /* 285 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 288 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 302 /* 293 */ MCD_OPC_CheckPredicate, 21, 79, 71, 0, // Skip to: 18553 /* 298 */ MCD_OPC_Decode, 191, 10, 97, // Opcode: VHSUBsv8i8 /* 302 */ MCD_OPC_FilterValue, 1, 70, 71, 0, // Skip to: 18553 /* 307 */ MCD_OPC_CheckPredicate, 21, 65, 71, 0, // Skip to: 18553 /* 312 */ MCD_OPC_Decode, 186, 10, 98, // Opcode: VHSUBsv16i8 /* 316 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 338 /* 322 */ MCD_OPC_CheckPredicate, 21, 50, 71, 0, // Skip to: 18553 /* 327 */ MCD_OPC_CheckField, 6, 1, 0, 43, 71, 0, // Skip to: 18553 /* 334 */ MCD_OPC_Decode, 214, 20, 99, // Opcode: VSUBLsv8i16 /* 338 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 375 /* 344 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 347 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 361 /* 352 */ MCD_OPC_CheckPredicate, 21, 20, 71, 0, // Skip to: 18553 /* 357 */ MCD_OPC_Decode, 197, 10, 97, // Opcode: VHSUBuv8i8 /* 361 */ MCD_OPC_FilterValue, 1, 11, 71, 0, // Skip to: 18553 /* 366 */ MCD_OPC_CheckPredicate, 21, 6, 71, 0, // Skip to: 18553 /* 371 */ MCD_OPC_Decode, 192, 10, 98, // Opcode: VHSUBuv16i8 /* 375 */ MCD_OPC_FilterValue, 231, 3, 252, 70, 0, // Skip to: 18553 /* 381 */ MCD_OPC_CheckPredicate, 21, 247, 70, 0, // Skip to: 18553 /* 386 */ MCD_OPC_CheckField, 6, 1, 0, 240, 70, 0, // Skip to: 18553 /* 393 */ MCD_OPC_Decode, 217, 20, 99, // Opcode: VSUBLuv8i16 /* 397 */ MCD_OPC_FilterValue, 3, 121, 0, 0, // Skip to: 523 /* 402 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 405 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 442 /* 411 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 428 /* 419 */ MCD_OPC_CheckPredicate, 21, 209, 70, 0, // Skip to: 18553 /* 424 */ MCD_OPC_Decode, 210, 8, 97, // Opcode: VCGTsv8i8 /* 428 */ MCD_OPC_FilterValue, 1, 200, 70, 0, // Skip to: 18553 /* 433 */ MCD_OPC_CheckPredicate, 21, 195, 70, 0, // Skip to: 18553 /* 438 */ MCD_OPC_Decode, 205, 8, 98, // Opcode: VCGTsv16i8 /* 442 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 464 /* 448 */ MCD_OPC_CheckPredicate, 21, 180, 70, 0, // Skip to: 18553 /* 453 */ MCD_OPC_CheckField, 6, 1, 0, 173, 70, 0, // Skip to: 18553 /* 460 */ MCD_OPC_Decode, 221, 20, 100, // Opcode: VSUBWsv8i16 /* 464 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 501 /* 470 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 473 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 487 /* 478 */ MCD_OPC_CheckPredicate, 21, 150, 70, 0, // Skip to: 18553 /* 483 */ MCD_OPC_Decode, 216, 8, 97, // Opcode: VCGTuv8i8 /* 487 */ MCD_OPC_FilterValue, 1, 141, 70, 0, // Skip to: 18553 /* 492 */ MCD_OPC_CheckPredicate, 21, 136, 70, 0, // Skip to: 18553 /* 497 */ MCD_OPC_Decode, 211, 8, 98, // Opcode: VCGTuv16i8 /* 501 */ MCD_OPC_FilterValue, 231, 3, 126, 70, 0, // Skip to: 18553 /* 507 */ MCD_OPC_CheckPredicate, 21, 121, 70, 0, // Skip to: 18553 /* 512 */ MCD_OPC_CheckField, 6, 1, 0, 114, 70, 0, // Skip to: 18553 /* 519 */ MCD_OPC_Decode, 224, 20, 100, // Opcode: VSUBWuv8i16 /* 523 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 649 /* 528 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 531 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 568 /* 537 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 540 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 554 /* 545 */ MCD_OPC_CheckPredicate, 21, 83, 70, 0, // Skip to: 18553 /* 550 */ MCD_OPC_Decode, 143, 18, 101, // Opcode: VSHLsv8i8 /* 554 */ MCD_OPC_FilterValue, 1, 74, 70, 0, // Skip to: 18553 /* 559 */ MCD_OPC_CheckPredicate, 21, 69, 70, 0, // Skip to: 18553 /* 564 */ MCD_OPC_Decode, 136, 18, 102, // Opcode: VSHLsv16i8 /* 568 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 590 /* 574 */ MCD_OPC_CheckPredicate, 21, 54, 70, 0, // Skip to: 18553 /* 579 */ MCD_OPC_CheckField, 6, 1, 0, 47, 70, 0, // Skip to: 18553 /* 586 */ MCD_OPC_Decode, 239, 7, 103, // Opcode: VADDHNv8i8 /* 590 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 627 /* 596 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 599 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 613 /* 604 */ MCD_OPC_CheckPredicate, 21, 24, 70, 0, // Skip to: 18553 /* 609 */ MCD_OPC_Decode, 151, 18, 101, // Opcode: VSHLuv8i8 /* 613 */ MCD_OPC_FilterValue, 1, 15, 70, 0, // Skip to: 18553 /* 618 */ MCD_OPC_CheckPredicate, 21, 10, 70, 0, // Skip to: 18553 /* 623 */ MCD_OPC_Decode, 144, 18, 102, // Opcode: VSHLuv16i8 /* 627 */ MCD_OPC_FilterValue, 231, 3, 0, 70, 0, // Skip to: 18553 /* 633 */ MCD_OPC_CheckPredicate, 21, 251, 69, 0, // Skip to: 18553 /* 638 */ MCD_OPC_CheckField, 6, 1, 0, 244, 69, 0, // Skip to: 18553 /* 645 */ MCD_OPC_Decode, 212, 16, 103, // Opcode: VRADDHNv8i8 /* 649 */ MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 775 /* 654 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 657 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 694 /* 663 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 666 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 680 /* 671 */ MCD_OPC_CheckPredicate, 21, 213, 69, 0, // Skip to: 18553 /* 676 */ MCD_OPC_Decode, 171, 17, 101, // Opcode: VRSHLsv8i8 /* 680 */ MCD_OPC_FilterValue, 1, 204, 69, 0, // Skip to: 18553 /* 685 */ MCD_OPC_CheckPredicate, 21, 199, 69, 0, // Skip to: 18553 /* 690 */ MCD_OPC_Decode, 164, 17, 102, // Opcode: VRSHLsv16i8 /* 694 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 716 /* 700 */ MCD_OPC_CheckPredicate, 21, 184, 69, 0, // Skip to: 18553 /* 705 */ MCD_OPC_CheckField, 6, 1, 0, 177, 69, 0, // Skip to: 18553 /* 712 */ MCD_OPC_Decode, 176, 7, 104, // Opcode: VABALsv8i16 /* 716 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 753 /* 722 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 725 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 739 /* 730 */ MCD_OPC_CheckPredicate, 21, 154, 69, 0, // Skip to: 18553 /* 735 */ MCD_OPC_Decode, 179, 17, 101, // Opcode: VRSHLuv8i8 /* 739 */ MCD_OPC_FilterValue, 1, 145, 69, 0, // Skip to: 18553 /* 744 */ MCD_OPC_CheckPredicate, 21, 140, 69, 0, // Skip to: 18553 /* 749 */ MCD_OPC_Decode, 172, 17, 102, // Opcode: VRSHLuv16i8 /* 753 */ MCD_OPC_FilterValue, 231, 3, 130, 69, 0, // Skip to: 18553 /* 759 */ MCD_OPC_CheckPredicate, 21, 125, 69, 0, // Skip to: 18553 /* 764 */ MCD_OPC_CheckField, 6, 1, 0, 118, 69, 0, // Skip to: 18553 /* 771 */ MCD_OPC_Decode, 179, 7, 104, // Opcode: VABALuv8i16 /* 775 */ MCD_OPC_FilterValue, 6, 121, 0, 0, // Skip to: 901 /* 780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 783 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 820 /* 789 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 792 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 806 /* 797 */ MCD_OPC_CheckPredicate, 21, 87, 69, 0, // Skip to: 18553 /* 802 */ MCD_OPC_Decode, 172, 13, 97, // Opcode: VMAXsv8i8 /* 806 */ MCD_OPC_FilterValue, 1, 78, 69, 0, // Skip to: 18553 /* 811 */ MCD_OPC_CheckPredicate, 21, 73, 69, 0, // Skip to: 18553 /* 816 */ MCD_OPC_Decode, 167, 13, 98, // Opcode: VMAXsv16i8 /* 820 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 842 /* 826 */ MCD_OPC_CheckPredicate, 21, 58, 69, 0, // Skip to: 18553 /* 831 */ MCD_OPC_CheckField, 6, 1, 0, 51, 69, 0, // Skip to: 18553 /* 838 */ MCD_OPC_Decode, 211, 20, 103, // Opcode: VSUBHNv8i8 /* 842 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 879 /* 848 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 851 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865 /* 856 */ MCD_OPC_CheckPredicate, 21, 28, 69, 0, // Skip to: 18553 /* 861 */ MCD_OPC_Decode, 178, 13, 97, // Opcode: VMAXuv8i8 /* 865 */ MCD_OPC_FilterValue, 1, 19, 69, 0, // Skip to: 18553 /* 870 */ MCD_OPC_CheckPredicate, 21, 14, 69, 0, // Skip to: 18553 /* 875 */ MCD_OPC_Decode, 173, 13, 98, // Opcode: VMAXuv16i8 /* 879 */ MCD_OPC_FilterValue, 231, 3, 4, 69, 0, // Skip to: 18553 /* 885 */ MCD_OPC_CheckPredicate, 21, 255, 68, 0, // Skip to: 18553 /* 890 */ MCD_OPC_CheckField, 6, 1, 0, 248, 68, 0, // Skip to: 18553 /* 897 */ MCD_OPC_Decode, 227, 17, 103, // Opcode: VRSUBHNv8i8 /* 901 */ MCD_OPC_FilterValue, 7, 121, 0, 0, // Skip to: 1027 /* 906 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 909 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 946 /* 915 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 918 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 932 /* 923 */ MCD_OPC_CheckPredicate, 21, 217, 68, 0, // Skip to: 18553 /* 928 */ MCD_OPC_Decode, 207, 7, 97, // Opcode: VABDsv8i8 /* 932 */ MCD_OPC_FilterValue, 1, 208, 68, 0, // Skip to: 18553 /* 937 */ MCD_OPC_CheckPredicate, 21, 203, 68, 0, // Skip to: 18553 /* 942 */ MCD_OPC_Decode, 202, 7, 98, // Opcode: VABDsv16i8 /* 946 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 968 /* 952 */ MCD_OPC_CheckPredicate, 21, 188, 68, 0, // Skip to: 18553 /* 957 */ MCD_OPC_CheckField, 6, 1, 0, 181, 68, 0, // Skip to: 18553 /* 964 */ MCD_OPC_Decode, 194, 7, 99, // Opcode: VABDLsv8i16 /* 968 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1005 /* 974 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 977 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 991 /* 982 */ MCD_OPC_CheckPredicate, 21, 158, 68, 0, // Skip to: 18553 /* 987 */ MCD_OPC_Decode, 213, 7, 97, // Opcode: VABDuv8i8 /* 991 */ MCD_OPC_FilterValue, 1, 149, 68, 0, // Skip to: 18553 /* 996 */ MCD_OPC_CheckPredicate, 21, 144, 68, 0, // Skip to: 18553 /* 1001 */ MCD_OPC_Decode, 208, 7, 98, // Opcode: VABDuv16i8 /* 1005 */ MCD_OPC_FilterValue, 231, 3, 134, 68, 0, // Skip to: 18553 /* 1011 */ MCD_OPC_CheckPredicate, 21, 129, 68, 0, // Skip to: 18553 /* 1016 */ MCD_OPC_CheckField, 6, 1, 0, 122, 68, 0, // Skip to: 18553 /* 1023 */ MCD_OPC_Decode, 197, 7, 99, // Opcode: VABDLuv8i16 /* 1027 */ MCD_OPC_FilterValue, 8, 121, 0, 0, // Skip to: 1153 /* 1032 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1035 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1072 /* 1041 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1044 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1058 /* 1049 */ MCD_OPC_CheckPredicate, 21, 91, 68, 0, // Skip to: 18553 /* 1054 */ MCD_OPC_Decode, 136, 8, 97, // Opcode: VADDv8i8 /* 1058 */ MCD_OPC_FilterValue, 1, 82, 68, 0, // Skip to: 18553 /* 1063 */ MCD_OPC_CheckPredicate, 21, 77, 68, 0, // Skip to: 18553 /* 1068 */ MCD_OPC_Decode, 129, 8, 98, // Opcode: VADDv16i8 /* 1072 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1094 /* 1078 */ MCD_OPC_CheckPredicate, 21, 62, 68, 0, // Skip to: 18553 /* 1083 */ MCD_OPC_CheckField, 6, 1, 0, 55, 68, 0, // Skip to: 18553 /* 1090 */ MCD_OPC_Decode, 210, 13, 104, // Opcode: VMLALsv8i16 /* 1094 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1131 /* 1100 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1103 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1117 /* 1108 */ MCD_OPC_CheckPredicate, 21, 32, 68, 0, // Skip to: 18553 /* 1113 */ MCD_OPC_Decode, 236, 20, 97, // Opcode: VSUBv8i8 /* 1117 */ MCD_OPC_FilterValue, 1, 23, 68, 0, // Skip to: 18553 /* 1122 */ MCD_OPC_CheckPredicate, 21, 18, 68, 0, // Skip to: 18553 /* 1127 */ MCD_OPC_Decode, 229, 20, 98, // Opcode: VSUBv16i8 /* 1131 */ MCD_OPC_FilterValue, 231, 3, 8, 68, 0, // Skip to: 18553 /* 1137 */ MCD_OPC_CheckPredicate, 21, 3, 68, 0, // Skip to: 18553 /* 1142 */ MCD_OPC_CheckField, 6, 1, 0, 252, 67, 0, // Skip to: 18553 /* 1149 */ MCD_OPC_Decode, 213, 13, 104, // Opcode: VMLALuv8i16 /* 1153 */ MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 1237 /* 1158 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1161 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1199 /* 1166 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1169 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1184 /* 1175 */ MCD_OPC_CheckPredicate, 21, 221, 67, 0, // Skip to: 18553 /* 1180 */ MCD_OPC_Decode, 232, 13, 105, // Opcode: VMLAv8i8 /* 1184 */ MCD_OPC_FilterValue, 230, 3, 211, 67, 0, // Skip to: 18553 /* 1190 */ MCD_OPC_CheckPredicate, 21, 206, 67, 0, // Skip to: 18553 /* 1195 */ MCD_OPC_Decode, 135, 14, 105, // Opcode: VMLSv8i8 /* 1199 */ MCD_OPC_FilterValue, 1, 197, 67, 0, // Skip to: 18553 /* 1204 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1207 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1222 /* 1213 */ MCD_OPC_CheckPredicate, 21, 183, 67, 0, // Skip to: 18553 /* 1218 */ MCD_OPC_Decode, 227, 13, 106, // Opcode: VMLAv16i8 /* 1222 */ MCD_OPC_FilterValue, 230, 3, 173, 67, 0, // Skip to: 18553 /* 1228 */ MCD_OPC_CheckPredicate, 21, 168, 67, 0, // Skip to: 18553 /* 1233 */ MCD_OPC_Decode, 130, 14, 106, // Opcode: VMLSv16i8 /* 1237 */ MCD_OPC_FilterValue, 10, 91, 0, 0, // Skip to: 1333 /* 1242 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1245 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 1267 /* 1251 */ MCD_OPC_CheckPredicate, 21, 145, 67, 0, // Skip to: 18553 /* 1256 */ MCD_OPC_CheckField, 6, 1, 0, 138, 67, 0, // Skip to: 18553 /* 1263 */ MCD_OPC_Decode, 155, 15, 97, // Opcode: VPMAXs8 /* 1267 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1289 /* 1273 */ MCD_OPC_CheckPredicate, 21, 123, 67, 0, // Skip to: 18553 /* 1278 */ MCD_OPC_CheckField, 6, 1, 0, 116, 67, 0, // Skip to: 18553 /* 1285 */ MCD_OPC_Decode, 241, 13, 104, // Opcode: VMLSLsv8i16 /* 1289 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 1311 /* 1295 */ MCD_OPC_CheckPredicate, 21, 101, 67, 0, // Skip to: 18553 /* 1300 */ MCD_OPC_CheckField, 6, 1, 0, 94, 67, 0, // Skip to: 18553 /* 1307 */ MCD_OPC_Decode, 158, 15, 97, // Opcode: VPMAXu8 /* 1311 */ MCD_OPC_FilterValue, 231, 3, 84, 67, 0, // Skip to: 18553 /* 1317 */ MCD_OPC_CheckPredicate, 21, 79, 67, 0, // Skip to: 18553 /* 1322 */ MCD_OPC_CheckField, 6, 1, 0, 72, 67, 0, // Skip to: 18553 /* 1329 */ MCD_OPC_Decode, 244, 13, 104, // Opcode: VMLSLuv8i16 /* 1333 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 1385 /* 1338 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1341 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1363 /* 1347 */ MCD_OPC_CheckPredicate, 21, 49, 67, 0, // Skip to: 18553 /* 1352 */ MCD_OPC_CheckField, 6, 1, 0, 42, 67, 0, // Skip to: 18553 /* 1359 */ MCD_OPC_Decode, 189, 14, 99, // Opcode: VMULLsv8i16 /* 1363 */ MCD_OPC_FilterValue, 231, 3, 32, 67, 0, // Skip to: 18553 /* 1369 */ MCD_OPC_CheckPredicate, 21, 27, 67, 0, // Skip to: 18553 /* 1374 */ MCD_OPC_CheckField, 6, 1, 0, 20, 67, 0, // Skip to: 18553 /* 1381 */ MCD_OPC_Decode, 192, 14, 99, // Opcode: VMULLuv8i16 /* 1385 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1453 /* 1390 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1393 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1431 /* 1398 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1401 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1416 /* 1407 */ MCD_OPC_CheckPredicate, 21, 245, 66, 0, // Skip to: 18553 /* 1412 */ MCD_OPC_Decode, 253, 7, 97, // Opcode: VADDfd /* 1416 */ MCD_OPC_FilterValue, 230, 3, 235, 66, 0, // Skip to: 18553 /* 1422 */ MCD_OPC_CheckPredicate, 21, 230, 66, 0, // Skip to: 18553 /* 1427 */ MCD_OPC_Decode, 146, 15, 97, // Opcode: VPADDf /* 1431 */ MCD_OPC_FilterValue, 1, 221, 66, 0, // Skip to: 18553 /* 1436 */ MCD_OPC_CheckPredicate, 21, 216, 66, 0, // Skip to: 18553 /* 1441 */ MCD_OPC_CheckField, 23, 9, 228, 3, 208, 66, 0, // Skip to: 18553 /* 1449 */ MCD_OPC_Decode, 254, 7, 98, // Opcode: VADDfq /* 1453 */ MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 1557 /* 1458 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1461 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1498 /* 1467 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1484 /* 1475 */ MCD_OPC_CheckPredicate, 21, 177, 66, 0, // Skip to: 18553 /* 1480 */ MCD_OPC_Decode, 155, 8, 97, // Opcode: VCEQfd /* 1484 */ MCD_OPC_FilterValue, 1, 168, 66, 0, // Skip to: 18553 /* 1489 */ MCD_OPC_CheckPredicate, 21, 163, 66, 0, // Skip to: 18553 /* 1494 */ MCD_OPC_Decode, 156, 8, 98, // Opcode: VCEQfq /* 1498 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1520 /* 1504 */ MCD_OPC_CheckPredicate, 21, 148, 66, 0, // Skip to: 18553 /* 1509 */ MCD_OPC_CheckField, 6, 1, 0, 141, 66, 0, // Skip to: 18553 /* 1516 */ MCD_OPC_Decode, 182, 14, 99, // Opcode: VMULLp8 /* 1520 */ MCD_OPC_FilterValue, 230, 3, 131, 66, 0, // Skip to: 18553 /* 1526 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1529 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1543 /* 1534 */ MCD_OPC_CheckPredicate, 21, 118, 66, 0, // Skip to: 18553 /* 1539 */ MCD_OPC_Decode, 175, 8, 97, // Opcode: VCGEfd /* 1543 */ MCD_OPC_FilterValue, 1, 109, 66, 0, // Skip to: 18553 /* 1548 */ MCD_OPC_CheckPredicate, 21, 104, 66, 0, // Skip to: 18553 /* 1553 */ MCD_OPC_Decode, 176, 8, 98, // Opcode: VCGEfq /* 1557 */ MCD_OPC_FilterValue, 15, 95, 66, 0, // Skip to: 18553 /* 1562 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1565 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1603 /* 1570 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1573 */ MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1588 /* 1579 */ MCD_OPC_CheckPredicate, 21, 73, 66, 0, // Skip to: 18553 /* 1584 */ MCD_OPC_Decode, 163, 13, 97, // Opcode: VMAXfd /* 1588 */ MCD_OPC_FilterValue, 230, 3, 63, 66, 0, // Skip to: 18553 /* 1594 */ MCD_OPC_CheckPredicate, 21, 58, 66, 0, // Skip to: 18553 /* 1599 */ MCD_OPC_Decode, 151, 15, 97, // Opcode: VPMAXf /* 1603 */ MCD_OPC_FilterValue, 1, 49, 66, 0, // Skip to: 18553 /* 1608 */ MCD_OPC_CheckPredicate, 21, 44, 66, 0, // Skip to: 18553 /* 1613 */ MCD_OPC_CheckField, 23, 9, 228, 3, 36, 66, 0, // Skip to: 18553 /* 1621 */ MCD_OPC_Decode, 164, 13, 98, // Opcode: VMAXfq /* 1625 */ MCD_OPC_FilterValue, 1, 162, 8, 0, // Skip to: 3840 /* 1630 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1633 */ MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 1789 /* 1638 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1641 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1678 /* 1647 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1650 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1664 /* 1655 */ MCD_OPC_CheckPredicate, 21, 253, 65, 0, // Skip to: 18553 /* 1660 */ MCD_OPC_Decode, 176, 10, 97, // Opcode: VHADDsv4i16 /* 1664 */ MCD_OPC_FilterValue, 1, 244, 65, 0, // Skip to: 18553 /* 1669 */ MCD_OPC_CheckPredicate, 21, 239, 65, 0, // Skip to: 18553 /* 1674 */ MCD_OPC_Decode, 178, 10, 98, // Opcode: VHADDsv8i16 /* 1678 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1715 /* 1684 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1687 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1701 /* 1692 */ MCD_OPC_CheckPredicate, 21, 216, 65, 0, // Skip to: 18553 /* 1697 */ MCD_OPC_Decode, 241, 7, 99, // Opcode: VADDLsv4i32 /* 1701 */ MCD_OPC_FilterValue, 1, 207, 65, 0, // Skip to: 18553 /* 1706 */ MCD_OPC_CheckPredicate, 21, 202, 65, 0, // Skip to: 18553 /* 1711 */ MCD_OPC_Decode, 224, 13, 107, // Opcode: VMLAslv4i16 /* 1715 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1752 /* 1721 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1738 /* 1729 */ MCD_OPC_CheckPredicate, 21, 179, 65, 0, // Skip to: 18553 /* 1734 */ MCD_OPC_Decode, 182, 10, 97, // Opcode: VHADDuv4i16 /* 1738 */ MCD_OPC_FilterValue, 1, 170, 65, 0, // Skip to: 18553 /* 1743 */ MCD_OPC_CheckPredicate, 21, 165, 65, 0, // Skip to: 18553 /* 1748 */ MCD_OPC_Decode, 184, 10, 98, // Opcode: VHADDuv8i16 /* 1752 */ MCD_OPC_FilterValue, 231, 3, 155, 65, 0, // Skip to: 18553 /* 1758 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1761 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1775 /* 1766 */ MCD_OPC_CheckPredicate, 21, 142, 65, 0, // Skip to: 18553 /* 1771 */ MCD_OPC_Decode, 244, 7, 99, // Opcode: VADDLuv4i32 /* 1775 */ MCD_OPC_FilterValue, 1, 133, 65, 0, // Skip to: 18553 /* 1780 */ MCD_OPC_CheckPredicate, 21, 128, 65, 0, // Skip to: 18553 /* 1785 */ MCD_OPC_Decode, 226, 13, 108, // Opcode: VMLAslv8i16 /* 1789 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 1945 /* 1794 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1797 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1834 /* 1803 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1806 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1820 /* 1811 */ MCD_OPC_CheckPredicate, 21, 97, 65, 0, // Skip to: 18553 /* 1816 */ MCD_OPC_Decode, 237, 16, 97, // Opcode: VRHADDsv4i16 /* 1820 */ MCD_OPC_FilterValue, 1, 88, 65, 0, // Skip to: 18553 /* 1825 */ MCD_OPC_CheckPredicate, 21, 83, 65, 0, // Skip to: 18553 /* 1830 */ MCD_OPC_Decode, 239, 16, 98, // Opcode: VRHADDsv8i16 /* 1834 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1871 /* 1840 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1843 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1857 /* 1848 */ MCD_OPC_CheckPredicate, 21, 60, 65, 0, // Skip to: 18553 /* 1853 */ MCD_OPC_Decode, 248, 7, 100, // Opcode: VADDWsv4i32 /* 1857 */ MCD_OPC_FilterValue, 1, 51, 65, 0, // Skip to: 18553 /* 1862 */ MCD_OPC_CheckPredicate, 22, 46, 65, 0, // Skip to: 18553 /* 1867 */ MCD_OPC_Decode, 221, 13, 107, // Opcode: VMLAslhd /* 1871 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1908 /* 1877 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1880 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1894 /* 1885 */ MCD_OPC_CheckPredicate, 21, 23, 65, 0, // Skip to: 18553 /* 1890 */ MCD_OPC_Decode, 243, 16, 97, // Opcode: VRHADDuv4i16 /* 1894 */ MCD_OPC_FilterValue, 1, 14, 65, 0, // Skip to: 18553 /* 1899 */ MCD_OPC_CheckPredicate, 21, 9, 65, 0, // Skip to: 18553 /* 1904 */ MCD_OPC_Decode, 245, 16, 98, // Opcode: VRHADDuv8i16 /* 1908 */ MCD_OPC_FilterValue, 231, 3, 255, 64, 0, // Skip to: 18553 /* 1914 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1917 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1931 /* 1922 */ MCD_OPC_CheckPredicate, 21, 242, 64, 0, // Skip to: 18553 /* 1927 */ MCD_OPC_Decode, 251, 7, 100, // Opcode: VADDWuv4i32 /* 1931 */ MCD_OPC_FilterValue, 1, 233, 64, 0, // Skip to: 18553 /* 1936 */ MCD_OPC_CheckPredicate, 22, 228, 64, 0, // Skip to: 18553 /* 1941 */ MCD_OPC_Decode, 222, 13, 108, // Opcode: VMLAslhq /* 1945 */ MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 2101 /* 1950 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1953 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1990 /* 1959 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1962 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1976 /* 1967 */ MCD_OPC_CheckPredicate, 21, 197, 64, 0, // Skip to: 18553 /* 1972 */ MCD_OPC_Decode, 188, 10, 97, // Opcode: VHSUBsv4i16 /* 1976 */ MCD_OPC_FilterValue, 1, 188, 64, 0, // Skip to: 18553 /* 1981 */ MCD_OPC_CheckPredicate, 21, 183, 64, 0, // Skip to: 18553 /* 1986 */ MCD_OPC_Decode, 190, 10, 98, // Opcode: VHSUBsv8i16 /* 1990 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2027 /* 1996 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1999 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2013 /* 2004 */ MCD_OPC_CheckPredicate, 21, 160, 64, 0, // Skip to: 18553 /* 2009 */ MCD_OPC_Decode, 213, 20, 99, // Opcode: VSUBLsv4i32 /* 2013 */ MCD_OPC_FilterValue, 1, 151, 64, 0, // Skip to: 18553 /* 2018 */ MCD_OPC_CheckPredicate, 21, 146, 64, 0, // Skip to: 18553 /* 2023 */ MCD_OPC_Decode, 205, 13, 109, // Opcode: VMLALslsv4i16 /* 2027 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2064 /* 2033 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2036 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2050 /* 2041 */ MCD_OPC_CheckPredicate, 21, 123, 64, 0, // Skip to: 18553 /* 2046 */ MCD_OPC_Decode, 194, 10, 97, // Opcode: VHSUBuv4i16 /* 2050 */ MCD_OPC_FilterValue, 1, 114, 64, 0, // Skip to: 18553 /* 2055 */ MCD_OPC_CheckPredicate, 21, 109, 64, 0, // Skip to: 18553 /* 2060 */ MCD_OPC_Decode, 196, 10, 98, // Opcode: VHSUBuv8i16 /* 2064 */ MCD_OPC_FilterValue, 231, 3, 99, 64, 0, // Skip to: 18553 /* 2070 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2073 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2087 /* 2078 */ MCD_OPC_CheckPredicate, 21, 86, 64, 0, // Skip to: 18553 /* 2083 */ MCD_OPC_Decode, 216, 20, 99, // Opcode: VSUBLuv4i32 /* 2087 */ MCD_OPC_FilterValue, 1, 77, 64, 0, // Skip to: 18553 /* 2092 */ MCD_OPC_CheckPredicate, 21, 72, 64, 0, // Skip to: 18553 /* 2097 */ MCD_OPC_Decode, 207, 13, 109, // Opcode: VMLALsluv4i16 /* 2101 */ MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 2242 /* 2106 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2109 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2146 /* 2115 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2118 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2132 /* 2123 */ MCD_OPC_CheckPredicate, 21, 41, 64, 0, // Skip to: 18553 /* 2128 */ MCD_OPC_Decode, 207, 8, 97, // Opcode: VCGTsv4i16 /* 2132 */ MCD_OPC_FilterValue, 1, 32, 64, 0, // Skip to: 18553 /* 2137 */ MCD_OPC_CheckPredicate, 21, 27, 64, 0, // Skip to: 18553 /* 2142 */ MCD_OPC_Decode, 209, 8, 98, // Opcode: VCGTsv8i16 /* 2146 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2183 /* 2152 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2155 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2169 /* 2160 */ MCD_OPC_CheckPredicate, 21, 4, 64, 0, // Skip to: 18553 /* 2165 */ MCD_OPC_Decode, 220, 20, 100, // Opcode: VSUBWsv4i32 /* 2169 */ MCD_OPC_FilterValue, 1, 251, 63, 0, // Skip to: 18553 /* 2174 */ MCD_OPC_CheckPredicate, 21, 246, 63, 0, // Skip to: 18553 /* 2179 */ MCD_OPC_Decode, 190, 15, 109, // Opcode: VQDMLALslv4i16 /* 2183 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2220 /* 2189 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2192 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2206 /* 2197 */ MCD_OPC_CheckPredicate, 21, 223, 63, 0, // Skip to: 18553 /* 2202 */ MCD_OPC_Decode, 213, 8, 97, // Opcode: VCGTuv4i16 /* 2206 */ MCD_OPC_FilterValue, 1, 214, 63, 0, // Skip to: 18553 /* 2211 */ MCD_OPC_CheckPredicate, 21, 209, 63, 0, // Skip to: 18553 /* 2216 */ MCD_OPC_Decode, 215, 8, 98, // Opcode: VCGTuv8i16 /* 2220 */ MCD_OPC_FilterValue, 231, 3, 199, 63, 0, // Skip to: 18553 /* 2226 */ MCD_OPC_CheckPredicate, 21, 194, 63, 0, // Skip to: 18553 /* 2231 */ MCD_OPC_CheckField, 6, 1, 0, 187, 63, 0, // Skip to: 18553 /* 2238 */ MCD_OPC_Decode, 223, 20, 100, // Opcode: VSUBWuv4i32 /* 2242 */ MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 2398 /* 2247 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2250 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2287 /* 2256 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2273 /* 2264 */ MCD_OPC_CheckPredicate, 21, 156, 63, 0, // Skip to: 18553 /* 2269 */ MCD_OPC_Decode, 140, 18, 101, // Opcode: VSHLsv4i16 /* 2273 */ MCD_OPC_FilterValue, 1, 147, 63, 0, // Skip to: 18553 /* 2278 */ MCD_OPC_CheckPredicate, 21, 142, 63, 0, // Skip to: 18553 /* 2283 */ MCD_OPC_Decode, 142, 18, 102, // Opcode: VSHLsv8i16 /* 2287 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2324 /* 2293 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2296 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2310 /* 2301 */ MCD_OPC_CheckPredicate, 21, 119, 63, 0, // Skip to: 18553 /* 2306 */ MCD_OPC_Decode, 238, 7, 103, // Opcode: VADDHNv4i16 /* 2310 */ MCD_OPC_FilterValue, 1, 110, 63, 0, // Skip to: 18553 /* 2315 */ MCD_OPC_CheckPredicate, 21, 105, 63, 0, // Skip to: 18553 /* 2320 */ MCD_OPC_Decode, 255, 13, 107, // Opcode: VMLSslv4i16 /* 2324 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2361 /* 2330 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2333 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2347 /* 2338 */ MCD_OPC_CheckPredicate, 21, 82, 63, 0, // Skip to: 18553 /* 2343 */ MCD_OPC_Decode, 148, 18, 101, // Opcode: VSHLuv4i16 /* 2347 */ MCD_OPC_FilterValue, 1, 73, 63, 0, // Skip to: 18553 /* 2352 */ MCD_OPC_CheckPredicate, 21, 68, 63, 0, // Skip to: 18553 /* 2357 */ MCD_OPC_Decode, 150, 18, 102, // Opcode: VSHLuv8i16 /* 2361 */ MCD_OPC_FilterValue, 231, 3, 58, 63, 0, // Skip to: 18553 /* 2367 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2370 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2384 /* 2375 */ MCD_OPC_CheckPredicate, 21, 45, 63, 0, // Skip to: 18553 /* 2380 */ MCD_OPC_Decode, 211, 16, 103, // Opcode: VRADDHNv4i16 /* 2384 */ MCD_OPC_FilterValue, 1, 36, 63, 0, // Skip to: 18553 /* 2389 */ MCD_OPC_CheckPredicate, 21, 31, 63, 0, // Skip to: 18553 /* 2394 */ MCD_OPC_Decode, 129, 14, 108, // Opcode: VMLSslv8i16 /* 2398 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 2554 /* 2403 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2406 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2443 /* 2412 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2415 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2429 /* 2420 */ MCD_OPC_CheckPredicate, 21, 0, 63, 0, // Skip to: 18553 /* 2425 */ MCD_OPC_Decode, 168, 17, 101, // Opcode: VRSHLsv4i16 /* 2429 */ MCD_OPC_FilterValue, 1, 247, 62, 0, // Skip to: 18553 /* 2434 */ MCD_OPC_CheckPredicate, 21, 242, 62, 0, // Skip to: 18553 /* 2439 */ MCD_OPC_Decode, 170, 17, 102, // Opcode: VRSHLsv8i16 /* 2443 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2480 /* 2449 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2452 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2466 /* 2457 */ MCD_OPC_CheckPredicate, 21, 219, 62, 0, // Skip to: 18553 /* 2462 */ MCD_OPC_Decode, 175, 7, 104, // Opcode: VABALsv4i32 /* 2466 */ MCD_OPC_FilterValue, 1, 210, 62, 0, // Skip to: 18553 /* 2471 */ MCD_OPC_CheckPredicate, 22, 205, 62, 0, // Skip to: 18553 /* 2476 */ MCD_OPC_Decode, 252, 13, 107, // Opcode: VMLSslhd /* 2480 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2517 /* 2486 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2489 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2503 /* 2494 */ MCD_OPC_CheckPredicate, 21, 182, 62, 0, // Skip to: 18553 /* 2499 */ MCD_OPC_Decode, 176, 17, 101, // Opcode: VRSHLuv4i16 /* 2503 */ MCD_OPC_FilterValue, 1, 173, 62, 0, // Skip to: 18553 /* 2508 */ MCD_OPC_CheckPredicate, 21, 168, 62, 0, // Skip to: 18553 /* 2513 */ MCD_OPC_Decode, 178, 17, 102, // Opcode: VRSHLuv8i16 /* 2517 */ MCD_OPC_FilterValue, 231, 3, 158, 62, 0, // Skip to: 18553 /* 2523 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2526 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2540 /* 2531 */ MCD_OPC_CheckPredicate, 21, 145, 62, 0, // Skip to: 18553 /* 2536 */ MCD_OPC_Decode, 178, 7, 104, // Opcode: VABALuv4i32 /* 2540 */ MCD_OPC_FilterValue, 1, 136, 62, 0, // Skip to: 18553 /* 2545 */ MCD_OPC_CheckPredicate, 22, 131, 62, 0, // Skip to: 18553 /* 2550 */ MCD_OPC_Decode, 253, 13, 108, // Opcode: VMLSslhq /* 2554 */ MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 2710 /* 2559 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2562 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2599 /* 2568 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2571 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2585 /* 2576 */ MCD_OPC_CheckPredicate, 21, 100, 62, 0, // Skip to: 18553 /* 2581 */ MCD_OPC_Decode, 169, 13, 97, // Opcode: VMAXsv4i16 /* 2585 */ MCD_OPC_FilterValue, 1, 91, 62, 0, // Skip to: 18553 /* 2590 */ MCD_OPC_CheckPredicate, 21, 86, 62, 0, // Skip to: 18553 /* 2595 */ MCD_OPC_Decode, 171, 13, 98, // Opcode: VMAXsv8i16 /* 2599 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2636 /* 2605 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2608 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622 /* 2613 */ MCD_OPC_CheckPredicate, 21, 63, 62, 0, // Skip to: 18553 /* 2618 */ MCD_OPC_Decode, 210, 20, 103, // Opcode: VSUBHNv4i16 /* 2622 */ MCD_OPC_FilterValue, 1, 54, 62, 0, // Skip to: 18553 /* 2627 */ MCD_OPC_CheckPredicate, 21, 49, 62, 0, // Skip to: 18553 /* 2632 */ MCD_OPC_Decode, 236, 13, 109, // Opcode: VMLSLslsv4i16 /* 2636 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2673 /* 2642 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2645 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2659 /* 2650 */ MCD_OPC_CheckPredicate, 21, 26, 62, 0, // Skip to: 18553 /* 2655 */ MCD_OPC_Decode, 175, 13, 97, // Opcode: VMAXuv4i16 /* 2659 */ MCD_OPC_FilterValue, 1, 17, 62, 0, // Skip to: 18553 /* 2664 */ MCD_OPC_CheckPredicate, 21, 12, 62, 0, // Skip to: 18553 /* 2669 */ MCD_OPC_Decode, 177, 13, 98, // Opcode: VMAXuv8i16 /* 2673 */ MCD_OPC_FilterValue, 231, 3, 2, 62, 0, // Skip to: 18553 /* 2679 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2682 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2696 /* 2687 */ MCD_OPC_CheckPredicate, 21, 245, 61, 0, // Skip to: 18553 /* 2692 */ MCD_OPC_Decode, 226, 17, 103, // Opcode: VRSUBHNv4i16 /* 2696 */ MCD_OPC_FilterValue, 1, 236, 61, 0, // Skip to: 18553 /* 2701 */ MCD_OPC_CheckPredicate, 21, 231, 61, 0, // Skip to: 18553 /* 2706 */ MCD_OPC_Decode, 238, 13, 109, // Opcode: VMLSLsluv4i16 /* 2710 */ MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 2851 /* 2715 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2718 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2755 /* 2724 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2727 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2741 /* 2732 */ MCD_OPC_CheckPredicate, 21, 200, 61, 0, // Skip to: 18553 /* 2737 */ MCD_OPC_Decode, 204, 7, 97, // Opcode: VABDsv4i16 /* 2741 */ MCD_OPC_FilterValue, 1, 191, 61, 0, // Skip to: 18553 /* 2746 */ MCD_OPC_CheckPredicate, 21, 186, 61, 0, // Skip to: 18553 /* 2751 */ MCD_OPC_Decode, 206, 7, 98, // Opcode: VABDsv8i16 /* 2755 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2792 /* 2761 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2764 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2778 /* 2769 */ MCD_OPC_CheckPredicate, 21, 163, 61, 0, // Skip to: 18553 /* 2774 */ MCD_OPC_Decode, 193, 7, 99, // Opcode: VABDLsv4i32 /* 2778 */ MCD_OPC_FilterValue, 1, 154, 61, 0, // Skip to: 18553 /* 2783 */ MCD_OPC_CheckPredicate, 21, 149, 61, 0, // Skip to: 18553 /* 2788 */ MCD_OPC_Decode, 194, 15, 109, // Opcode: VQDMLSLslv4i16 /* 2792 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2829 /* 2798 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2815 /* 2806 */ MCD_OPC_CheckPredicate, 21, 126, 61, 0, // Skip to: 18553 /* 2811 */ MCD_OPC_Decode, 210, 7, 97, // Opcode: VABDuv4i16 /* 2815 */ MCD_OPC_FilterValue, 1, 117, 61, 0, // Skip to: 18553 /* 2820 */ MCD_OPC_CheckPredicate, 21, 112, 61, 0, // Skip to: 18553 /* 2825 */ MCD_OPC_Decode, 212, 7, 98, // Opcode: VABDuv8i16 /* 2829 */ MCD_OPC_FilterValue, 231, 3, 102, 61, 0, // Skip to: 18553 /* 2835 */ MCD_OPC_CheckPredicate, 21, 97, 61, 0, // Skip to: 18553 /* 2840 */ MCD_OPC_CheckField, 6, 1, 0, 90, 61, 0, // Skip to: 18553 /* 2847 */ MCD_OPC_Decode, 196, 7, 99, // Opcode: VABDLuv4i32 /* 2851 */ MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 3007 /* 2856 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2859 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2896 /* 2865 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2868 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2882 /* 2873 */ MCD_OPC_CheckPredicate, 21, 59, 61, 0, // Skip to: 18553 /* 2878 */ MCD_OPC_Decode, 133, 8, 97, // Opcode: VADDv4i16 /* 2882 */ MCD_OPC_FilterValue, 1, 50, 61, 0, // Skip to: 18553 /* 2887 */ MCD_OPC_CheckPredicate, 21, 45, 61, 0, // Skip to: 18553 /* 2892 */ MCD_OPC_Decode, 135, 8, 98, // Opcode: VADDv8i16 /* 2896 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2933 /* 2902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2905 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2919 /* 2910 */ MCD_OPC_CheckPredicate, 21, 22, 61, 0, // Skip to: 18553 /* 2915 */ MCD_OPC_Decode, 209, 13, 104, // Opcode: VMLALsv4i32 /* 2919 */ MCD_OPC_FilterValue, 1, 13, 61, 0, // Skip to: 18553 /* 2924 */ MCD_OPC_CheckPredicate, 21, 8, 61, 0, // Skip to: 18553 /* 2929 */ MCD_OPC_Decode, 205, 14, 110, // Opcode: VMULslv4i16 /* 2933 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2970 /* 2939 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2942 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2956 /* 2947 */ MCD_OPC_CheckPredicate, 21, 241, 60, 0, // Skip to: 18553 /* 2952 */ MCD_OPC_Decode, 233, 20, 97, // Opcode: VSUBv4i16 /* 2956 */ MCD_OPC_FilterValue, 1, 232, 60, 0, // Skip to: 18553 /* 2961 */ MCD_OPC_CheckPredicate, 21, 227, 60, 0, // Skip to: 18553 /* 2966 */ MCD_OPC_Decode, 235, 20, 98, // Opcode: VSUBv8i16 /* 2970 */ MCD_OPC_FilterValue, 231, 3, 217, 60, 0, // Skip to: 18553 /* 2976 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2979 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2993 /* 2984 */ MCD_OPC_CheckPredicate, 21, 204, 60, 0, // Skip to: 18553 /* 2989 */ MCD_OPC_Decode, 212, 13, 104, // Opcode: VMLALuv4i32 /* 2993 */ MCD_OPC_FilterValue, 1, 195, 60, 0, // Skip to: 18553 /* 2998 */ MCD_OPC_CheckPredicate, 21, 190, 60, 0, // Skip to: 18553 /* 3003 */ MCD_OPC_Decode, 207, 14, 111, // Opcode: VMULslv8i16 /* 3007 */ MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 3148 /* 3012 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3015 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3052 /* 3021 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3024 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3038 /* 3029 */ MCD_OPC_CheckPredicate, 21, 159, 60, 0, // Skip to: 18553 /* 3034 */ MCD_OPC_Decode, 229, 13, 105, // Opcode: VMLAv4i16 /* 3038 */ MCD_OPC_FilterValue, 1, 150, 60, 0, // Skip to: 18553 /* 3043 */ MCD_OPC_CheckPredicate, 21, 145, 60, 0, // Skip to: 18553 /* 3048 */ MCD_OPC_Decode, 231, 13, 106, // Opcode: VMLAv8i16 /* 3052 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3089 /* 3058 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3061 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3075 /* 3066 */ MCD_OPC_CheckPredicate, 21, 122, 60, 0, // Skip to: 18553 /* 3071 */ MCD_OPC_Decode, 192, 15, 104, // Opcode: VQDMLALv4i32 /* 3075 */ MCD_OPC_FilterValue, 1, 113, 60, 0, // Skip to: 18553 /* 3080 */ MCD_OPC_CheckPredicate, 22, 108, 60, 0, // Skip to: 18553 /* 3085 */ MCD_OPC_Decode, 202, 14, 110, // Opcode: VMULslhd /* 3089 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3126 /* 3095 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3098 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3112 /* 3103 */ MCD_OPC_CheckPredicate, 21, 85, 60, 0, // Skip to: 18553 /* 3108 */ MCD_OPC_Decode, 132, 14, 105, // Opcode: VMLSv4i16 /* 3112 */ MCD_OPC_FilterValue, 1, 76, 60, 0, // Skip to: 18553 /* 3117 */ MCD_OPC_CheckPredicate, 21, 71, 60, 0, // Skip to: 18553 /* 3122 */ MCD_OPC_Decode, 134, 14, 106, // Opcode: VMLSv8i16 /* 3126 */ MCD_OPC_FilterValue, 231, 3, 61, 60, 0, // Skip to: 18553 /* 3132 */ MCD_OPC_CheckPredicate, 22, 56, 60, 0, // Skip to: 18553 /* 3137 */ MCD_OPC_CheckField, 6, 1, 1, 49, 60, 0, // Skip to: 18553 /* 3144 */ MCD_OPC_Decode, 203, 14, 111, // Opcode: VMULslhq /* 3148 */ MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 3274 /* 3153 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3156 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 3178 /* 3162 */ MCD_OPC_CheckPredicate, 21, 26, 60, 0, // Skip to: 18553 /* 3167 */ MCD_OPC_CheckField, 6, 1, 0, 19, 60, 0, // Skip to: 18553 /* 3174 */ MCD_OPC_Decode, 153, 15, 97, // Opcode: VPMAXs16 /* 3178 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3215 /* 3184 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3187 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3201 /* 3192 */ MCD_OPC_CheckPredicate, 21, 252, 59, 0, // Skip to: 18553 /* 3197 */ MCD_OPC_Decode, 240, 13, 104, // Opcode: VMLSLsv4i32 /* 3201 */ MCD_OPC_FilterValue, 1, 243, 59, 0, // Skip to: 18553 /* 3206 */ MCD_OPC_CheckPredicate, 21, 238, 59, 0, // Skip to: 18553 /* 3211 */ MCD_OPC_Decode, 184, 14, 112, // Opcode: VMULLslsv4i16 /* 3215 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3237 /* 3221 */ MCD_OPC_CheckPredicate, 21, 223, 59, 0, // Skip to: 18553 /* 3226 */ MCD_OPC_CheckField, 6, 1, 0, 216, 59, 0, // Skip to: 18553 /* 3233 */ MCD_OPC_Decode, 156, 15, 97, // Opcode: VPMAXu16 /* 3237 */ MCD_OPC_FilterValue, 231, 3, 206, 59, 0, // Skip to: 18553 /* 3243 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3246 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3260 /* 3251 */ MCD_OPC_CheckPredicate, 21, 193, 59, 0, // Skip to: 18553 /* 3256 */ MCD_OPC_Decode, 243, 13, 104, // Opcode: VMLSLuv4i32 /* 3260 */ MCD_OPC_FilterValue, 1, 184, 59, 0, // Skip to: 18553 /* 3265 */ MCD_OPC_CheckPredicate, 21, 179, 59, 0, // Skip to: 18553 /* 3270 */ MCD_OPC_Decode, 186, 14, 112, // Opcode: VMULLsluv4i16 /* 3274 */ MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 3393 /* 3279 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3282 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3319 /* 3288 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3291 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3305 /* 3296 */ MCD_OPC_CheckPredicate, 21, 148, 59, 0, // Skip to: 18553 /* 3301 */ MCD_OPC_Decode, 202, 15, 97, // Opcode: VQDMULHv4i16 /* 3305 */ MCD_OPC_FilterValue, 1, 139, 59, 0, // Skip to: 18553 /* 3310 */ MCD_OPC_CheckPredicate, 21, 134, 59, 0, // Skip to: 18553 /* 3315 */ MCD_OPC_Decode, 204, 15, 98, // Opcode: VQDMULHv8i16 /* 3319 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3356 /* 3325 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3328 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3342 /* 3333 */ MCD_OPC_CheckPredicate, 21, 111, 59, 0, // Skip to: 18553 /* 3338 */ MCD_OPC_Decode, 196, 15, 104, // Opcode: VQDMLSLv4i32 /* 3342 */ MCD_OPC_FilterValue, 1, 102, 59, 0, // Skip to: 18553 /* 3347 */ MCD_OPC_CheckPredicate, 21, 97, 59, 0, // Skip to: 18553 /* 3352 */ MCD_OPC_Decode, 206, 15, 112, // Opcode: VQDMULLslv4i16 /* 3356 */ MCD_OPC_FilterValue, 230, 3, 87, 59, 0, // Skip to: 18553 /* 3362 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3365 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3379 /* 3370 */ MCD_OPC_CheckPredicate, 21, 74, 59, 0, // Skip to: 18553 /* 3375 */ MCD_OPC_Decode, 245, 15, 97, // Opcode: VQRDMULHv4i16 /* 3379 */ MCD_OPC_FilterValue, 1, 65, 59, 0, // Skip to: 18553 /* 3384 */ MCD_OPC_CheckPredicate, 21, 60, 59, 0, // Skip to: 18553 /* 3389 */ MCD_OPC_Decode, 247, 15, 98, // Opcode: VQRDMULHv8i16 /* 3393 */ MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 3477 /* 3398 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3401 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 3439 /* 3406 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3409 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3424 /* 3415 */ MCD_OPC_CheckPredicate, 21, 29, 59, 0, // Skip to: 18553 /* 3420 */ MCD_OPC_Decode, 188, 14, 99, // Opcode: VMULLsv4i32 /* 3424 */ MCD_OPC_FilterValue, 231, 3, 19, 59, 0, // Skip to: 18553 /* 3430 */ MCD_OPC_CheckPredicate, 21, 14, 59, 0, // Skip to: 18553 /* 3435 */ MCD_OPC_Decode, 191, 14, 99, // Opcode: VMULLuv4i32 /* 3439 */ MCD_OPC_FilterValue, 1, 5, 59, 0, // Skip to: 18553 /* 3444 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3447 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3462 /* 3453 */ MCD_OPC_CheckPredicate, 21, 247, 58, 0, // Skip to: 18553 /* 3458 */ MCD_OPC_Decode, 198, 15, 110, // Opcode: VQDMULHslv4i16 /* 3462 */ MCD_OPC_FilterValue, 231, 3, 237, 58, 0, // Skip to: 18553 /* 3468 */ MCD_OPC_CheckPredicate, 21, 232, 58, 0, // Skip to: 18553 /* 3473 */ MCD_OPC_Decode, 200, 15, 111, // Opcode: VQDMULHslv8i16 /* 3477 */ MCD_OPC_FilterValue, 13, 121, 0, 0, // Skip to: 3603 /* 3482 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3485 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3522 /* 3491 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3494 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3508 /* 3499 */ MCD_OPC_CheckPredicate, 22, 201, 58, 0, // Skip to: 18553 /* 3504 */ MCD_OPC_Decode, 255, 7, 97, // Opcode: VADDhd /* 3508 */ MCD_OPC_FilterValue, 1, 192, 58, 0, // Skip to: 18553 /* 3513 */ MCD_OPC_CheckPredicate, 22, 187, 58, 0, // Skip to: 18553 /* 3518 */ MCD_OPC_Decode, 128, 8, 98, // Opcode: VADDhq /* 3522 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3559 /* 3528 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3545 /* 3536 */ MCD_OPC_CheckPredicate, 21, 164, 58, 0, // Skip to: 18553 /* 3541 */ MCD_OPC_Decode, 208, 15, 99, // Opcode: VQDMULLv4i32 /* 3545 */ MCD_OPC_FilterValue, 1, 155, 58, 0, // Skip to: 18553 /* 3550 */ MCD_OPC_CheckPredicate, 21, 150, 58, 0, // Skip to: 18553 /* 3555 */ MCD_OPC_Decode, 241, 15, 110, // Opcode: VQRDMULHslv4i16 /* 3559 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3581 /* 3565 */ MCD_OPC_CheckPredicate, 22, 135, 58, 0, // Skip to: 18553 /* 3570 */ MCD_OPC_CheckField, 6, 1, 0, 128, 58, 0, // Skip to: 18553 /* 3577 */ MCD_OPC_Decode, 147, 15, 97, // Opcode: VPADDh /* 3581 */ MCD_OPC_FilterValue, 231, 3, 118, 58, 0, // Skip to: 18553 /* 3587 */ MCD_OPC_CheckPredicate, 21, 113, 58, 0, // Skip to: 18553 /* 3592 */ MCD_OPC_CheckField, 6, 1, 1, 106, 58, 0, // Skip to: 18553 /* 3599 */ MCD_OPC_Decode, 243, 15, 111, // Opcode: VQRDMULHslv8i16 /* 3603 */ MCD_OPC_FilterValue, 14, 121, 0, 0, // Skip to: 3729 /* 3608 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3611 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3648 /* 3617 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3620 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3634 /* 3625 */ MCD_OPC_CheckPredicate, 22, 75, 58, 0, // Skip to: 18553 /* 3630 */ MCD_OPC_Decode, 157, 8, 97, // Opcode: VCEQhd /* 3634 */ MCD_OPC_FilterValue, 1, 66, 58, 0, // Skip to: 18553 /* 3639 */ MCD_OPC_CheckPredicate, 22, 61, 58, 0, // Skip to: 18553 /* 3644 */ MCD_OPC_Decode, 158, 8, 98, // Opcode: VCEQhq /* 3648 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3670 /* 3654 */ MCD_OPC_CheckPredicate, 23, 46, 58, 0, // Skip to: 18553 /* 3659 */ MCD_OPC_CheckField, 6, 1, 1, 39, 58, 0, // Skip to: 18553 /* 3666 */ MCD_OPC_Decode, 225, 15, 107, // Opcode: VQRDMLAHslv4i16 /* 3670 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3707 /* 3676 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3679 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3693 /* 3684 */ MCD_OPC_CheckPredicate, 22, 16, 58, 0, // Skip to: 18553 /* 3689 */ MCD_OPC_Decode, 177, 8, 97, // Opcode: VCGEhd /* 3693 */ MCD_OPC_FilterValue, 1, 7, 58, 0, // Skip to: 18553 /* 3698 */ MCD_OPC_CheckPredicate, 22, 2, 58, 0, // Skip to: 18553 /* 3703 */ MCD_OPC_Decode, 178, 8, 98, // Opcode: VCGEhq /* 3707 */ MCD_OPC_FilterValue, 231, 3, 248, 57, 0, // Skip to: 18553 /* 3713 */ MCD_OPC_CheckPredicate, 23, 243, 57, 0, // Skip to: 18553 /* 3718 */ MCD_OPC_CheckField, 6, 1, 1, 236, 57, 0, // Skip to: 18553 /* 3725 */ MCD_OPC_Decode, 227, 15, 108, // Opcode: VQRDMLAHslv8i16 /* 3729 */ MCD_OPC_FilterValue, 15, 227, 57, 0, // Skip to: 18553 /* 3734 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3737 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3774 /* 3743 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3746 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3760 /* 3751 */ MCD_OPC_CheckPredicate, 22, 205, 57, 0, // Skip to: 18553 /* 3756 */ MCD_OPC_Decode, 165, 13, 97, // Opcode: VMAXhd /* 3760 */ MCD_OPC_FilterValue, 1, 196, 57, 0, // Skip to: 18553 /* 3765 */ MCD_OPC_CheckPredicate, 22, 191, 57, 0, // Skip to: 18553 /* 3770 */ MCD_OPC_Decode, 166, 13, 98, // Opcode: VMAXhq /* 3774 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3796 /* 3780 */ MCD_OPC_CheckPredicate, 23, 176, 57, 0, // Skip to: 18553 /* 3785 */ MCD_OPC_CheckField, 6, 1, 1, 169, 57, 0, // Skip to: 18553 /* 3792 */ MCD_OPC_Decode, 233, 15, 107, // Opcode: VQRDMLSHslv4i16 /* 3796 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3818 /* 3802 */ MCD_OPC_CheckPredicate, 22, 154, 57, 0, // Skip to: 18553 /* 3807 */ MCD_OPC_CheckField, 6, 1, 0, 147, 57, 0, // Skip to: 18553 /* 3814 */ MCD_OPC_Decode, 152, 15, 97, // Opcode: VPMAXh /* 3818 */ MCD_OPC_FilterValue, 231, 3, 137, 57, 0, // Skip to: 18553 /* 3824 */ MCD_OPC_CheckPredicate, 23, 132, 57, 0, // Skip to: 18553 /* 3829 */ MCD_OPC_CheckField, 6, 1, 1, 125, 57, 0, // Skip to: 18553 /* 3836 */ MCD_OPC_Decode, 235, 15, 108, // Opcode: VQRDMLSHslv8i16 /* 3840 */ MCD_OPC_FilterValue, 2, 155, 8, 0, // Skip to: 6048 /* 3845 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 3848 */ MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 4004 /* 3853 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3856 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3893 /* 3862 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3865 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3879 /* 3870 */ MCD_OPC_CheckPredicate, 21, 86, 57, 0, // Skip to: 18553 /* 3875 */ MCD_OPC_Decode, 175, 10, 97, // Opcode: VHADDsv2i32 /* 3879 */ MCD_OPC_FilterValue, 1, 77, 57, 0, // Skip to: 18553 /* 3884 */ MCD_OPC_CheckPredicate, 21, 72, 57, 0, // Skip to: 18553 /* 3889 */ MCD_OPC_Decode, 177, 10, 98, // Opcode: VHADDsv4i32 /* 3893 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3930 /* 3899 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3902 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3916 /* 3907 */ MCD_OPC_CheckPredicate, 21, 49, 57, 0, // Skip to: 18553 /* 3912 */ MCD_OPC_Decode, 240, 7, 99, // Opcode: VADDLsv2i64 /* 3916 */ MCD_OPC_FilterValue, 1, 40, 57, 0, // Skip to: 18553 /* 3921 */ MCD_OPC_CheckPredicate, 21, 35, 57, 0, // Skip to: 18553 /* 3926 */ MCD_OPC_Decode, 223, 13, 113, // Opcode: VMLAslv2i32 /* 3930 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3967 /* 3936 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3953 /* 3944 */ MCD_OPC_CheckPredicate, 21, 12, 57, 0, // Skip to: 18553 /* 3949 */ MCD_OPC_Decode, 181, 10, 97, // Opcode: VHADDuv2i32 /* 3953 */ MCD_OPC_FilterValue, 1, 3, 57, 0, // Skip to: 18553 /* 3958 */ MCD_OPC_CheckPredicate, 21, 254, 56, 0, // Skip to: 18553 /* 3963 */ MCD_OPC_Decode, 183, 10, 98, // Opcode: VHADDuv4i32 /* 3967 */ MCD_OPC_FilterValue, 231, 3, 244, 56, 0, // Skip to: 18553 /* 3973 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3976 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3990 /* 3981 */ MCD_OPC_CheckPredicate, 21, 231, 56, 0, // Skip to: 18553 /* 3986 */ MCD_OPC_Decode, 243, 7, 99, // Opcode: VADDLuv2i64 /* 3990 */ MCD_OPC_FilterValue, 1, 222, 56, 0, // Skip to: 18553 /* 3995 */ MCD_OPC_CheckPredicate, 21, 217, 56, 0, // Skip to: 18553 /* 4000 */ MCD_OPC_Decode, 225, 13, 114, // Opcode: VMLAslv4i32 /* 4004 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 4160 /* 4009 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4012 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4049 /* 4018 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4021 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4035 /* 4026 */ MCD_OPC_CheckPredicate, 21, 186, 56, 0, // Skip to: 18553 /* 4031 */ MCD_OPC_Decode, 236, 16, 97, // Opcode: VRHADDsv2i32 /* 4035 */ MCD_OPC_FilterValue, 1, 177, 56, 0, // Skip to: 18553 /* 4040 */ MCD_OPC_CheckPredicate, 21, 172, 56, 0, // Skip to: 18553 /* 4045 */ MCD_OPC_Decode, 238, 16, 98, // Opcode: VRHADDsv4i32 /* 4049 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4086 /* 4055 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4058 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4072 /* 4063 */ MCD_OPC_CheckPredicate, 21, 149, 56, 0, // Skip to: 18553 /* 4068 */ MCD_OPC_Decode, 247, 7, 100, // Opcode: VADDWsv2i64 /* 4072 */ MCD_OPC_FilterValue, 1, 140, 56, 0, // Skip to: 18553 /* 4077 */ MCD_OPC_CheckPredicate, 21, 135, 56, 0, // Skip to: 18553 /* 4082 */ MCD_OPC_Decode, 219, 13, 113, // Opcode: VMLAslfd /* 4086 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4123 /* 4092 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4095 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109 /* 4100 */ MCD_OPC_CheckPredicate, 21, 112, 56, 0, // Skip to: 18553 /* 4105 */ MCD_OPC_Decode, 242, 16, 97, // Opcode: VRHADDuv2i32 /* 4109 */ MCD_OPC_FilterValue, 1, 103, 56, 0, // Skip to: 18553 /* 4114 */ MCD_OPC_CheckPredicate, 21, 98, 56, 0, // Skip to: 18553 /* 4119 */ MCD_OPC_Decode, 244, 16, 98, // Opcode: VRHADDuv4i32 /* 4123 */ MCD_OPC_FilterValue, 231, 3, 88, 56, 0, // Skip to: 18553 /* 4129 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4132 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4146 /* 4137 */ MCD_OPC_CheckPredicate, 21, 75, 56, 0, // Skip to: 18553 /* 4142 */ MCD_OPC_Decode, 250, 7, 100, // Opcode: VADDWuv2i64 /* 4146 */ MCD_OPC_FilterValue, 1, 66, 56, 0, // Skip to: 18553 /* 4151 */ MCD_OPC_CheckPredicate, 21, 61, 56, 0, // Skip to: 18553 /* 4156 */ MCD_OPC_Decode, 220, 13, 114, // Opcode: VMLAslfq /* 4160 */ MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 4316 /* 4165 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4168 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4205 /* 4174 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4177 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4191 /* 4182 */ MCD_OPC_CheckPredicate, 21, 30, 56, 0, // Skip to: 18553 /* 4187 */ MCD_OPC_Decode, 187, 10, 97, // Opcode: VHSUBsv2i32 /* 4191 */ MCD_OPC_FilterValue, 1, 21, 56, 0, // Skip to: 18553 /* 4196 */ MCD_OPC_CheckPredicate, 21, 16, 56, 0, // Skip to: 18553 /* 4201 */ MCD_OPC_Decode, 189, 10, 98, // Opcode: VHSUBsv4i32 /* 4205 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4242 /* 4211 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4214 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4228 /* 4219 */ MCD_OPC_CheckPredicate, 21, 249, 55, 0, // Skip to: 18553 /* 4224 */ MCD_OPC_Decode, 212, 20, 99, // Opcode: VSUBLsv2i64 /* 4228 */ MCD_OPC_FilterValue, 1, 240, 55, 0, // Skip to: 18553 /* 4233 */ MCD_OPC_CheckPredicate, 21, 235, 55, 0, // Skip to: 18553 /* 4238 */ MCD_OPC_Decode, 204, 13, 115, // Opcode: VMLALslsv2i32 /* 4242 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4279 /* 4248 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4251 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4265 /* 4256 */ MCD_OPC_CheckPredicate, 21, 212, 55, 0, // Skip to: 18553 /* 4261 */ MCD_OPC_Decode, 193, 10, 97, // Opcode: VHSUBuv2i32 /* 4265 */ MCD_OPC_FilterValue, 1, 203, 55, 0, // Skip to: 18553 /* 4270 */ MCD_OPC_CheckPredicate, 21, 198, 55, 0, // Skip to: 18553 /* 4275 */ MCD_OPC_Decode, 195, 10, 98, // Opcode: VHSUBuv4i32 /* 4279 */ MCD_OPC_FilterValue, 231, 3, 188, 55, 0, // Skip to: 18553 /* 4285 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4288 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4302 /* 4293 */ MCD_OPC_CheckPredicate, 21, 175, 55, 0, // Skip to: 18553 /* 4298 */ MCD_OPC_Decode, 215, 20, 99, // Opcode: VSUBLuv2i64 /* 4302 */ MCD_OPC_FilterValue, 1, 166, 55, 0, // Skip to: 18553 /* 4307 */ MCD_OPC_CheckPredicate, 21, 161, 55, 0, // Skip to: 18553 /* 4312 */ MCD_OPC_Decode, 206, 13, 115, // Opcode: VMLALsluv2i32 /* 4316 */ MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 4457 /* 4321 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4324 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4361 /* 4330 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4333 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4347 /* 4338 */ MCD_OPC_CheckPredicate, 21, 130, 55, 0, // Skip to: 18553 /* 4343 */ MCD_OPC_Decode, 206, 8, 97, // Opcode: VCGTsv2i32 /* 4347 */ MCD_OPC_FilterValue, 1, 121, 55, 0, // Skip to: 18553 /* 4352 */ MCD_OPC_CheckPredicate, 21, 116, 55, 0, // Skip to: 18553 /* 4357 */ MCD_OPC_Decode, 208, 8, 98, // Opcode: VCGTsv4i32 /* 4361 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4398 /* 4367 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4370 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4384 /* 4375 */ MCD_OPC_CheckPredicate, 21, 93, 55, 0, // Skip to: 18553 /* 4380 */ MCD_OPC_Decode, 219, 20, 100, // Opcode: VSUBWsv2i64 /* 4384 */ MCD_OPC_FilterValue, 1, 84, 55, 0, // Skip to: 18553 /* 4389 */ MCD_OPC_CheckPredicate, 21, 79, 55, 0, // Skip to: 18553 /* 4394 */ MCD_OPC_Decode, 189, 15, 115, // Opcode: VQDMLALslv2i32 /* 4398 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4435 /* 4404 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4421 /* 4412 */ MCD_OPC_CheckPredicate, 21, 56, 55, 0, // Skip to: 18553 /* 4417 */ MCD_OPC_Decode, 212, 8, 97, // Opcode: VCGTuv2i32 /* 4421 */ MCD_OPC_FilterValue, 1, 47, 55, 0, // Skip to: 18553 /* 4426 */ MCD_OPC_CheckPredicate, 21, 42, 55, 0, // Skip to: 18553 /* 4431 */ MCD_OPC_Decode, 214, 8, 98, // Opcode: VCGTuv4i32 /* 4435 */ MCD_OPC_FilterValue, 231, 3, 32, 55, 0, // Skip to: 18553 /* 4441 */ MCD_OPC_CheckPredicate, 21, 27, 55, 0, // Skip to: 18553 /* 4446 */ MCD_OPC_CheckField, 6, 1, 0, 20, 55, 0, // Skip to: 18553 /* 4453 */ MCD_OPC_Decode, 222, 20, 100, // Opcode: VSUBWuv2i64 /* 4457 */ MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 4613 /* 4462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4465 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4502 /* 4471 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4474 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4488 /* 4479 */ MCD_OPC_CheckPredicate, 21, 245, 54, 0, // Skip to: 18553 /* 4484 */ MCD_OPC_Decode, 138, 18, 101, // Opcode: VSHLsv2i32 /* 4488 */ MCD_OPC_FilterValue, 1, 236, 54, 0, // Skip to: 18553 /* 4493 */ MCD_OPC_CheckPredicate, 21, 231, 54, 0, // Skip to: 18553 /* 4498 */ MCD_OPC_Decode, 141, 18, 102, // Opcode: VSHLsv4i32 /* 4502 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4539 /* 4508 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4511 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4525 /* 4516 */ MCD_OPC_CheckPredicate, 21, 208, 54, 0, // Skip to: 18553 /* 4521 */ MCD_OPC_Decode, 237, 7, 103, // Opcode: VADDHNv2i32 /* 4525 */ MCD_OPC_FilterValue, 1, 199, 54, 0, // Skip to: 18553 /* 4530 */ MCD_OPC_CheckPredicate, 21, 194, 54, 0, // Skip to: 18553 /* 4535 */ MCD_OPC_Decode, 254, 13, 113, // Opcode: VMLSslv2i32 /* 4539 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4576 /* 4545 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4548 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4562 /* 4553 */ MCD_OPC_CheckPredicate, 21, 171, 54, 0, // Skip to: 18553 /* 4558 */ MCD_OPC_Decode, 146, 18, 101, // Opcode: VSHLuv2i32 /* 4562 */ MCD_OPC_FilterValue, 1, 162, 54, 0, // Skip to: 18553 /* 4567 */ MCD_OPC_CheckPredicate, 21, 157, 54, 0, // Skip to: 18553 /* 4572 */ MCD_OPC_Decode, 149, 18, 102, // Opcode: VSHLuv4i32 /* 4576 */ MCD_OPC_FilterValue, 231, 3, 147, 54, 0, // Skip to: 18553 /* 4582 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4599 /* 4590 */ MCD_OPC_CheckPredicate, 21, 134, 54, 0, // Skip to: 18553 /* 4595 */ MCD_OPC_Decode, 210, 16, 103, // Opcode: VRADDHNv2i32 /* 4599 */ MCD_OPC_FilterValue, 1, 125, 54, 0, // Skip to: 18553 /* 4604 */ MCD_OPC_CheckPredicate, 21, 120, 54, 0, // Skip to: 18553 /* 4609 */ MCD_OPC_Decode, 128, 14, 114, // Opcode: VMLSslv4i32 /* 4613 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 4769 /* 4618 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4621 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4658 /* 4627 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4630 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4644 /* 4635 */ MCD_OPC_CheckPredicate, 21, 89, 54, 0, // Skip to: 18553 /* 4640 */ MCD_OPC_Decode, 166, 17, 101, // Opcode: VRSHLsv2i32 /* 4644 */ MCD_OPC_FilterValue, 1, 80, 54, 0, // Skip to: 18553 /* 4649 */ MCD_OPC_CheckPredicate, 21, 75, 54, 0, // Skip to: 18553 /* 4654 */ MCD_OPC_Decode, 169, 17, 102, // Opcode: VRSHLsv4i32 /* 4658 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4695 /* 4664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4667 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4681 /* 4672 */ MCD_OPC_CheckPredicate, 21, 52, 54, 0, // Skip to: 18553 /* 4677 */ MCD_OPC_Decode, 174, 7, 104, // Opcode: VABALsv2i64 /* 4681 */ MCD_OPC_FilterValue, 1, 43, 54, 0, // Skip to: 18553 /* 4686 */ MCD_OPC_CheckPredicate, 21, 38, 54, 0, // Skip to: 18553 /* 4691 */ MCD_OPC_Decode, 250, 13, 113, // Opcode: VMLSslfd /* 4695 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4732 /* 4701 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4704 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4718 /* 4709 */ MCD_OPC_CheckPredicate, 21, 15, 54, 0, // Skip to: 18553 /* 4714 */ MCD_OPC_Decode, 174, 17, 101, // Opcode: VRSHLuv2i32 /* 4718 */ MCD_OPC_FilterValue, 1, 6, 54, 0, // Skip to: 18553 /* 4723 */ MCD_OPC_CheckPredicate, 21, 1, 54, 0, // Skip to: 18553 /* 4728 */ MCD_OPC_Decode, 177, 17, 102, // Opcode: VRSHLuv4i32 /* 4732 */ MCD_OPC_FilterValue, 231, 3, 247, 53, 0, // Skip to: 18553 /* 4738 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4741 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4755 /* 4746 */ MCD_OPC_CheckPredicate, 21, 234, 53, 0, // Skip to: 18553 /* 4751 */ MCD_OPC_Decode, 177, 7, 104, // Opcode: VABALuv2i64 /* 4755 */ MCD_OPC_FilterValue, 1, 225, 53, 0, // Skip to: 18553 /* 4760 */ MCD_OPC_CheckPredicate, 21, 220, 53, 0, // Skip to: 18553 /* 4765 */ MCD_OPC_Decode, 251, 13, 114, // Opcode: VMLSslfq /* 4769 */ MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 4925 /* 4774 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4777 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4814 /* 4783 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4786 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4800 /* 4791 */ MCD_OPC_CheckPredicate, 21, 189, 53, 0, // Skip to: 18553 /* 4796 */ MCD_OPC_Decode, 168, 13, 97, // Opcode: VMAXsv2i32 /* 4800 */ MCD_OPC_FilterValue, 1, 180, 53, 0, // Skip to: 18553 /* 4805 */ MCD_OPC_CheckPredicate, 21, 175, 53, 0, // Skip to: 18553 /* 4810 */ MCD_OPC_Decode, 170, 13, 98, // Opcode: VMAXsv4i32 /* 4814 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4851 /* 4820 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4823 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4837 /* 4828 */ MCD_OPC_CheckPredicate, 21, 152, 53, 0, // Skip to: 18553 /* 4833 */ MCD_OPC_Decode, 209, 20, 103, // Opcode: VSUBHNv2i32 /* 4837 */ MCD_OPC_FilterValue, 1, 143, 53, 0, // Skip to: 18553 /* 4842 */ MCD_OPC_CheckPredicate, 21, 138, 53, 0, // Skip to: 18553 /* 4847 */ MCD_OPC_Decode, 235, 13, 115, // Opcode: VMLSLslsv2i32 /* 4851 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4888 /* 4857 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4860 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4874 /* 4865 */ MCD_OPC_CheckPredicate, 21, 115, 53, 0, // Skip to: 18553 /* 4870 */ MCD_OPC_Decode, 174, 13, 97, // Opcode: VMAXuv2i32 /* 4874 */ MCD_OPC_FilterValue, 1, 106, 53, 0, // Skip to: 18553 /* 4879 */ MCD_OPC_CheckPredicate, 21, 101, 53, 0, // Skip to: 18553 /* 4884 */ MCD_OPC_Decode, 176, 13, 98, // Opcode: VMAXuv4i32 /* 4888 */ MCD_OPC_FilterValue, 231, 3, 91, 53, 0, // Skip to: 18553 /* 4894 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4897 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4911 /* 4902 */ MCD_OPC_CheckPredicate, 21, 78, 53, 0, // Skip to: 18553 /* 4907 */ MCD_OPC_Decode, 225, 17, 103, // Opcode: VRSUBHNv2i32 /* 4911 */ MCD_OPC_FilterValue, 1, 69, 53, 0, // Skip to: 18553 /* 4916 */ MCD_OPC_CheckPredicate, 21, 64, 53, 0, // Skip to: 18553 /* 4921 */ MCD_OPC_Decode, 237, 13, 115, // Opcode: VMLSLsluv2i32 /* 4925 */ MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 5066 /* 4930 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4933 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4970 /* 4939 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4942 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4956 /* 4947 */ MCD_OPC_CheckPredicate, 21, 33, 53, 0, // Skip to: 18553 /* 4952 */ MCD_OPC_Decode, 203, 7, 97, // Opcode: VABDsv2i32 /* 4956 */ MCD_OPC_FilterValue, 1, 24, 53, 0, // Skip to: 18553 /* 4961 */ MCD_OPC_CheckPredicate, 21, 19, 53, 0, // Skip to: 18553 /* 4966 */ MCD_OPC_Decode, 205, 7, 98, // Opcode: VABDsv4i32 /* 4970 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5007 /* 4976 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4979 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4993 /* 4984 */ MCD_OPC_CheckPredicate, 21, 252, 52, 0, // Skip to: 18553 /* 4989 */ MCD_OPC_Decode, 192, 7, 99, // Opcode: VABDLsv2i64 /* 4993 */ MCD_OPC_FilterValue, 1, 243, 52, 0, // Skip to: 18553 /* 4998 */ MCD_OPC_CheckPredicate, 21, 238, 52, 0, // Skip to: 18553 /* 5003 */ MCD_OPC_Decode, 193, 15, 115, // Opcode: VQDMLSLslv2i32 /* 5007 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5044 /* 5013 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5016 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5030 /* 5021 */ MCD_OPC_CheckPredicate, 21, 215, 52, 0, // Skip to: 18553 /* 5026 */ MCD_OPC_Decode, 209, 7, 97, // Opcode: VABDuv2i32 /* 5030 */ MCD_OPC_FilterValue, 1, 206, 52, 0, // Skip to: 18553 /* 5035 */ MCD_OPC_CheckPredicate, 21, 201, 52, 0, // Skip to: 18553 /* 5040 */ MCD_OPC_Decode, 211, 7, 98, // Opcode: VABDuv4i32 /* 5044 */ MCD_OPC_FilterValue, 231, 3, 191, 52, 0, // Skip to: 18553 /* 5050 */ MCD_OPC_CheckPredicate, 21, 186, 52, 0, // Skip to: 18553 /* 5055 */ MCD_OPC_CheckField, 6, 1, 0, 179, 52, 0, // Skip to: 18553 /* 5062 */ MCD_OPC_Decode, 195, 7, 99, // Opcode: VABDLuv2i64 /* 5066 */ MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 5222 /* 5071 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5074 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5111 /* 5080 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5083 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097 /* 5088 */ MCD_OPC_CheckPredicate, 21, 148, 52, 0, // Skip to: 18553 /* 5093 */ MCD_OPC_Decode, 131, 8, 97, // Opcode: VADDv2i32 /* 5097 */ MCD_OPC_FilterValue, 1, 139, 52, 0, // Skip to: 18553 /* 5102 */ MCD_OPC_CheckPredicate, 21, 134, 52, 0, // Skip to: 18553 /* 5107 */ MCD_OPC_Decode, 134, 8, 98, // Opcode: VADDv4i32 /* 5111 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5148 /* 5117 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5120 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5134 /* 5125 */ MCD_OPC_CheckPredicate, 21, 111, 52, 0, // Skip to: 18553 /* 5130 */ MCD_OPC_Decode, 208, 13, 104, // Opcode: VMLALsv2i64 /* 5134 */ MCD_OPC_FilterValue, 1, 102, 52, 0, // Skip to: 18553 /* 5139 */ MCD_OPC_CheckPredicate, 21, 97, 52, 0, // Skip to: 18553 /* 5144 */ MCD_OPC_Decode, 204, 14, 116, // Opcode: VMULslv2i32 /* 5148 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5185 /* 5154 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5157 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5171 /* 5162 */ MCD_OPC_CheckPredicate, 21, 74, 52, 0, // Skip to: 18553 /* 5167 */ MCD_OPC_Decode, 231, 20, 97, // Opcode: VSUBv2i32 /* 5171 */ MCD_OPC_FilterValue, 1, 65, 52, 0, // Skip to: 18553 /* 5176 */ MCD_OPC_CheckPredicate, 21, 60, 52, 0, // Skip to: 18553 /* 5181 */ MCD_OPC_Decode, 234, 20, 98, // Opcode: VSUBv4i32 /* 5185 */ MCD_OPC_FilterValue, 231, 3, 50, 52, 0, // Skip to: 18553 /* 5191 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5194 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5208 /* 5199 */ MCD_OPC_CheckPredicate, 21, 37, 52, 0, // Skip to: 18553 /* 5204 */ MCD_OPC_Decode, 211, 13, 104, // Opcode: VMLALuv2i64 /* 5208 */ MCD_OPC_FilterValue, 1, 28, 52, 0, // Skip to: 18553 /* 5213 */ MCD_OPC_CheckPredicate, 21, 23, 52, 0, // Skip to: 18553 /* 5218 */ MCD_OPC_Decode, 206, 14, 117, // Opcode: VMULslv4i32 /* 5222 */ MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 5363 /* 5227 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5230 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5267 /* 5236 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5239 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5253 /* 5244 */ MCD_OPC_CheckPredicate, 21, 248, 51, 0, // Skip to: 18553 /* 5249 */ MCD_OPC_Decode, 228, 13, 105, // Opcode: VMLAv2i32 /* 5253 */ MCD_OPC_FilterValue, 1, 239, 51, 0, // Skip to: 18553 /* 5258 */ MCD_OPC_CheckPredicate, 21, 234, 51, 0, // Skip to: 18553 /* 5263 */ MCD_OPC_Decode, 230, 13, 106, // Opcode: VMLAv4i32 /* 5267 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5304 /* 5273 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5290 /* 5281 */ MCD_OPC_CheckPredicate, 21, 211, 51, 0, // Skip to: 18553 /* 5286 */ MCD_OPC_Decode, 191, 15, 104, // Opcode: VQDMLALv2i64 /* 5290 */ MCD_OPC_FilterValue, 1, 202, 51, 0, // Skip to: 18553 /* 5295 */ MCD_OPC_CheckPredicate, 21, 197, 51, 0, // Skip to: 18553 /* 5300 */ MCD_OPC_Decode, 200, 14, 116, // Opcode: VMULslfd /* 5304 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5341 /* 5310 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5313 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5327 /* 5318 */ MCD_OPC_CheckPredicate, 21, 174, 51, 0, // Skip to: 18553 /* 5323 */ MCD_OPC_Decode, 131, 14, 105, // Opcode: VMLSv2i32 /* 5327 */ MCD_OPC_FilterValue, 1, 165, 51, 0, // Skip to: 18553 /* 5332 */ MCD_OPC_CheckPredicate, 21, 160, 51, 0, // Skip to: 18553 /* 5337 */ MCD_OPC_Decode, 133, 14, 106, // Opcode: VMLSv4i32 /* 5341 */ MCD_OPC_FilterValue, 231, 3, 150, 51, 0, // Skip to: 18553 /* 5347 */ MCD_OPC_CheckPredicate, 21, 145, 51, 0, // Skip to: 18553 /* 5352 */ MCD_OPC_CheckField, 6, 1, 1, 138, 51, 0, // Skip to: 18553 /* 5359 */ MCD_OPC_Decode, 201, 14, 117, // Opcode: VMULslfq /* 5363 */ MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 5489 /* 5368 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5371 */ MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 5393 /* 5377 */ MCD_OPC_CheckPredicate, 21, 115, 51, 0, // Skip to: 18553 /* 5382 */ MCD_OPC_CheckField, 6, 1, 0, 108, 51, 0, // Skip to: 18553 /* 5389 */ MCD_OPC_Decode, 154, 15, 97, // Opcode: VPMAXs32 /* 5393 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5430 /* 5399 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5402 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5416 /* 5407 */ MCD_OPC_CheckPredicate, 21, 85, 51, 0, // Skip to: 18553 /* 5412 */ MCD_OPC_Decode, 239, 13, 104, // Opcode: VMLSLsv2i64 /* 5416 */ MCD_OPC_FilterValue, 1, 76, 51, 0, // Skip to: 18553 /* 5421 */ MCD_OPC_CheckPredicate, 21, 71, 51, 0, // Skip to: 18553 /* 5426 */ MCD_OPC_Decode, 183, 14, 118, // Opcode: VMULLslsv2i32 /* 5430 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 5452 /* 5436 */ MCD_OPC_CheckPredicate, 21, 56, 51, 0, // Skip to: 18553 /* 5441 */ MCD_OPC_CheckField, 6, 1, 0, 49, 51, 0, // Skip to: 18553 /* 5448 */ MCD_OPC_Decode, 157, 15, 97, // Opcode: VPMAXu32 /* 5452 */ MCD_OPC_FilterValue, 231, 3, 39, 51, 0, // Skip to: 18553 /* 5458 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5461 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5475 /* 5466 */ MCD_OPC_CheckPredicate, 21, 26, 51, 0, // Skip to: 18553 /* 5471 */ MCD_OPC_Decode, 242, 13, 104, // Opcode: VMLSLuv2i64 /* 5475 */ MCD_OPC_FilterValue, 1, 17, 51, 0, // Skip to: 18553 /* 5480 */ MCD_OPC_CheckPredicate, 21, 12, 51, 0, // Skip to: 18553 /* 5485 */ MCD_OPC_Decode, 185, 14, 118, // Opcode: VMULLsluv2i32 /* 5489 */ MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 5608 /* 5494 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5497 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5534 /* 5503 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5506 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5520 /* 5511 */ MCD_OPC_CheckPredicate, 21, 237, 50, 0, // Skip to: 18553 /* 5516 */ MCD_OPC_Decode, 201, 15, 97, // Opcode: VQDMULHv2i32 /* 5520 */ MCD_OPC_FilterValue, 1, 228, 50, 0, // Skip to: 18553 /* 5525 */ MCD_OPC_CheckPredicate, 21, 223, 50, 0, // Skip to: 18553 /* 5530 */ MCD_OPC_Decode, 203, 15, 98, // Opcode: VQDMULHv4i32 /* 5534 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5571 /* 5540 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5543 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5557 /* 5548 */ MCD_OPC_CheckPredicate, 21, 200, 50, 0, // Skip to: 18553 /* 5553 */ MCD_OPC_Decode, 195, 15, 104, // Opcode: VQDMLSLv2i64 /* 5557 */ MCD_OPC_FilterValue, 1, 191, 50, 0, // Skip to: 18553 /* 5562 */ MCD_OPC_CheckPredicate, 21, 186, 50, 0, // Skip to: 18553 /* 5567 */ MCD_OPC_Decode, 205, 15, 118, // Opcode: VQDMULLslv2i32 /* 5571 */ MCD_OPC_FilterValue, 230, 3, 176, 50, 0, // Skip to: 18553 /* 5577 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5580 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5594 /* 5585 */ MCD_OPC_CheckPredicate, 21, 163, 50, 0, // Skip to: 18553 /* 5590 */ MCD_OPC_Decode, 244, 15, 97, // Opcode: VQRDMULHv2i32 /* 5594 */ MCD_OPC_FilterValue, 1, 154, 50, 0, // Skip to: 18553 /* 5599 */ MCD_OPC_CheckPredicate, 21, 149, 50, 0, // Skip to: 18553 /* 5604 */ MCD_OPC_Decode, 246, 15, 98, // Opcode: VQRDMULHv4i32 /* 5608 */ MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 5692 /* 5613 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5616 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5654 /* 5621 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5624 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5639 /* 5630 */ MCD_OPC_CheckPredicate, 21, 118, 50, 0, // Skip to: 18553 /* 5635 */ MCD_OPC_Decode, 187, 14, 99, // Opcode: VMULLsv2i64 /* 5639 */ MCD_OPC_FilterValue, 231, 3, 108, 50, 0, // Skip to: 18553 /* 5645 */ MCD_OPC_CheckPredicate, 21, 103, 50, 0, // Skip to: 18553 /* 5650 */ MCD_OPC_Decode, 190, 14, 99, // Opcode: VMULLuv2i64 /* 5654 */ MCD_OPC_FilterValue, 1, 94, 50, 0, // Skip to: 18553 /* 5659 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5662 */ MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5677 /* 5668 */ MCD_OPC_CheckPredicate, 21, 80, 50, 0, // Skip to: 18553 /* 5673 */ MCD_OPC_Decode, 197, 15, 116, // Opcode: VQDMULHslv2i32 /* 5677 */ MCD_OPC_FilterValue, 231, 3, 70, 50, 0, // Skip to: 18553 /* 5683 */ MCD_OPC_CheckPredicate, 21, 65, 50, 0, // Skip to: 18553 /* 5688 */ MCD_OPC_Decode, 199, 15, 117, // Opcode: VQDMULHslv4i32 /* 5692 */ MCD_OPC_FilterValue, 13, 136, 0, 0, // Skip to: 5833 /* 5697 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5700 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5737 /* 5706 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5709 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5723 /* 5714 */ MCD_OPC_CheckPredicate, 21, 34, 50, 0, // Skip to: 18553 /* 5719 */ MCD_OPC_Decode, 225, 20, 97, // Opcode: VSUBfd /* 5723 */ MCD_OPC_FilterValue, 1, 25, 50, 0, // Skip to: 18553 /* 5728 */ MCD_OPC_CheckPredicate, 21, 20, 50, 0, // Skip to: 18553 /* 5733 */ MCD_OPC_Decode, 226, 20, 98, // Opcode: VSUBfq /* 5737 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5774 /* 5743 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5746 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5760 /* 5751 */ MCD_OPC_CheckPredicate, 21, 253, 49, 0, // Skip to: 18553 /* 5756 */ MCD_OPC_Decode, 207, 15, 99, // Opcode: VQDMULLv2i64 /* 5760 */ MCD_OPC_FilterValue, 1, 244, 49, 0, // Skip to: 18553 /* 5765 */ MCD_OPC_CheckPredicate, 21, 239, 49, 0, // Skip to: 18553 /* 5770 */ MCD_OPC_Decode, 240, 15, 116, // Opcode: VQRDMULHslv2i32 /* 5774 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5811 /* 5780 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5783 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5797 /* 5788 */ MCD_OPC_CheckPredicate, 21, 216, 49, 0, // Skip to: 18553 /* 5793 */ MCD_OPC_Decode, 198, 7, 97, // Opcode: VABDfd /* 5797 */ MCD_OPC_FilterValue, 1, 207, 49, 0, // Skip to: 18553 /* 5802 */ MCD_OPC_CheckPredicate, 21, 202, 49, 0, // Skip to: 18553 /* 5807 */ MCD_OPC_Decode, 199, 7, 98, // Opcode: VABDfq /* 5811 */ MCD_OPC_FilterValue, 231, 3, 192, 49, 0, // Skip to: 18553 /* 5817 */ MCD_OPC_CheckPredicate, 21, 187, 49, 0, // Skip to: 18553 /* 5822 */ MCD_OPC_CheckField, 6, 1, 1, 180, 49, 0, // Skip to: 18553 /* 5829 */ MCD_OPC_Decode, 242, 15, 117, // Opcode: VQRDMULHslv4i32 /* 5833 */ MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 5937 /* 5838 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5841 */ MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5878 /* 5847 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5850 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5864 /* 5855 */ MCD_OPC_CheckPredicate, 24, 149, 49, 0, // Skip to: 18553 /* 5860 */ MCD_OPC_Decode, 181, 14, 99, // Opcode: VMULLp64 /* 5864 */ MCD_OPC_FilterValue, 1, 140, 49, 0, // Skip to: 18553 /* 5869 */ MCD_OPC_CheckPredicate, 23, 135, 49, 0, // Skip to: 18553 /* 5874 */ MCD_OPC_Decode, 224, 15, 113, // Opcode: VQRDMLAHslv2i32 /* 5878 */ MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5915 /* 5884 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5887 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5901 /* 5892 */ MCD_OPC_CheckPredicate, 21, 112, 49, 0, // Skip to: 18553 /* 5897 */ MCD_OPC_Decode, 201, 8, 97, // Opcode: VCGTfd /* 5901 */ MCD_OPC_FilterValue, 1, 103, 49, 0, // Skip to: 18553 /* 5906 */ MCD_OPC_CheckPredicate, 21, 98, 49, 0, // Skip to: 18553 /* 5911 */ MCD_OPC_Decode, 202, 8, 98, // Opcode: VCGTfq /* 5915 */ MCD_OPC_FilterValue, 231, 3, 88, 49, 0, // Skip to: 18553 /* 5921 */ MCD_OPC_CheckPredicate, 23, 83, 49, 0, // Skip to: 18553 /* 5926 */ MCD_OPC_CheckField, 6, 1, 1, 76, 49, 0, // Skip to: 18553 /* 5933 */ MCD_OPC_Decode, 226, 15, 114, // Opcode: VQRDMLAHslv4i32 /* 5937 */ MCD_OPC_FilterValue, 15, 67, 49, 0, // Skip to: 18553 /* 5942 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5945 */ MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5982 /* 5951 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5954 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5968 /* 5959 */ MCD_OPC_CheckPredicate, 21, 45, 49, 0, // Skip to: 18553 /* 5964 */ MCD_OPC_Decode, 186, 13, 97, // Opcode: VMINfd /* 5968 */ MCD_OPC_FilterValue, 1, 36, 49, 0, // Skip to: 18553 /* 5973 */ MCD_OPC_CheckPredicate, 21, 31, 49, 0, // Skip to: 18553 /* 5978 */ MCD_OPC_Decode, 187, 13, 98, // Opcode: VMINfq /* 5982 */ MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 6004 /* 5988 */ MCD_OPC_CheckPredicate, 23, 16, 49, 0, // Skip to: 18553 /* 5993 */ MCD_OPC_CheckField, 6, 1, 1, 9, 49, 0, // Skip to: 18553 /* 6000 */ MCD_OPC_Decode, 232, 15, 113, // Opcode: VQRDMLSHslv2i32 /* 6004 */ MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 6026 /* 6010 */ MCD_OPC_CheckPredicate, 21, 250, 48, 0, // Skip to: 18553 /* 6015 */ MCD_OPC_CheckField, 6, 1, 0, 243, 48, 0, // Skip to: 18553 /* 6022 */ MCD_OPC_Decode, 159, 15, 97, // Opcode: VPMINf /* 6026 */ MCD_OPC_FilterValue, 231, 3, 233, 48, 0, // Skip to: 18553 /* 6032 */ MCD_OPC_CheckPredicate, 23, 228, 48, 0, // Skip to: 18553 /* 6037 */ MCD_OPC_CheckField, 6, 1, 1, 221, 48, 0, // Skip to: 18553 /* 6044 */ MCD_OPC_Decode, 234, 15, 114, // Opcode: VQRDMLSHslv4i32 /* 6048 */ MCD_OPC_FilterValue, 3, 212, 48, 0, // Skip to: 18553 /* 6053 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6056 */ MCD_OPC_FilterValue, 228, 3, 183, 0, 0, // Skip to: 6245 /* 6062 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6065 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6101 /* 6070 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6073 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6087 /* 6078 */ MCD_OPC_CheckPredicate, 21, 182, 48, 0, // Skip to: 18553 /* 6083 */ MCD_OPC_Decode, 137, 18, 101, // Opcode: VSHLsv1i64 /* 6087 */ MCD_OPC_FilterValue, 1, 173, 48, 0, // Skip to: 18553 /* 6092 */ MCD_OPC_CheckPredicate, 21, 168, 48, 0, // Skip to: 18553 /* 6097 */ MCD_OPC_Decode, 139, 18, 102, // Opcode: VSHLsv2i64 /* 6101 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6137 /* 6106 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6109 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6123 /* 6114 */ MCD_OPC_CheckPredicate, 21, 146, 48, 0, // Skip to: 18553 /* 6119 */ MCD_OPC_Decode, 165, 17, 101, // Opcode: VRSHLsv1i64 /* 6123 */ MCD_OPC_FilterValue, 1, 137, 48, 0, // Skip to: 18553 /* 6128 */ MCD_OPC_CheckPredicate, 21, 132, 48, 0, // Skip to: 18553 /* 6133 */ MCD_OPC_Decode, 167, 17, 102, // Opcode: VRSHLsv2i64 /* 6137 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6173 /* 6142 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6145 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6159 /* 6150 */ MCD_OPC_CheckPredicate, 21, 110, 48, 0, // Skip to: 18553 /* 6155 */ MCD_OPC_Decode, 130, 8, 97, // Opcode: VADDv1i64 /* 6159 */ MCD_OPC_FilterValue, 1, 101, 48, 0, // Skip to: 18553 /* 6164 */ MCD_OPC_CheckPredicate, 21, 96, 48, 0, // Skip to: 18553 /* 6169 */ MCD_OPC_Decode, 132, 8, 98, // Opcode: VADDv2i64 /* 6173 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6209 /* 6178 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6181 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6195 /* 6186 */ MCD_OPC_CheckPredicate, 22, 74, 48, 0, // Skip to: 18553 /* 6191 */ MCD_OPC_Decode, 227, 20, 97, // Opcode: VSUBhd /* 6195 */ MCD_OPC_FilterValue, 1, 65, 48, 0, // Skip to: 18553 /* 6200 */ MCD_OPC_CheckPredicate, 22, 60, 48, 0, // Skip to: 18553 /* 6205 */ MCD_OPC_Decode, 228, 20, 98, // Opcode: VSUBhq /* 6209 */ MCD_OPC_FilterValue, 15, 51, 48, 0, // Skip to: 18553 /* 6214 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6217 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6231 /* 6222 */ MCD_OPC_CheckPredicate, 22, 38, 48, 0, // Skip to: 18553 /* 6227 */ MCD_OPC_Decode, 188, 13, 97, // Opcode: VMINhd /* 6231 */ MCD_OPC_FilterValue, 1, 29, 48, 0, // Skip to: 18553 /* 6236 */ MCD_OPC_CheckPredicate, 22, 24, 48, 0, // Skip to: 18553 /* 6241 */ MCD_OPC_Decode, 189, 13, 98, // Opcode: VMINhq /* 6245 */ MCD_OPC_FilterValue, 229, 3, 119, 0, 0, // Skip to: 6370 /* 6251 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6254 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6308 /* 6259 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 6262 */ MCD_OPC_FilterValue, 0, 254, 47, 0, // Skip to: 18553 /* 6267 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6283 /* 6272 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6283 /* 6279 */ MCD_OPC_Decode, 143, 10, 119, // Opcode: VEXTd32 /* 6283 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6299 /* 6288 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6299 /* 6295 */ MCD_OPC_Decode, 142, 10, 120, // Opcode: VEXTd16 /* 6299 */ MCD_OPC_CheckPredicate, 21, 217, 47, 0, // Skip to: 18553 /* 6304 */ MCD_OPC_Decode, 144, 10, 121, // Opcode: VEXTd8 /* 6308 */ MCD_OPC_FilterValue, 1, 208, 47, 0, // Skip to: 18553 /* 6313 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6329 /* 6318 */ MCD_OPC_CheckField, 8, 3, 0, 4, 0, 0, // Skip to: 6329 /* 6325 */ MCD_OPC_Decode, 147, 10, 122, // Opcode: VEXTq64 /* 6329 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6345 /* 6334 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6345 /* 6341 */ MCD_OPC_Decode, 146, 10, 123, // Opcode: VEXTq32 /* 6345 */ MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6361 /* 6350 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6361 /* 6357 */ MCD_OPC_Decode, 145, 10, 124, // Opcode: VEXTq16 /* 6361 */ MCD_OPC_CheckPredicate, 21, 155, 47, 0, // Skip to: 18553 /* 6366 */ MCD_OPC_Decode, 148, 10, 125, // Opcode: VEXTq8 /* 6370 */ MCD_OPC_FilterValue, 230, 3, 204, 0, 0, // Skip to: 6580 /* 6376 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6379 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6415 /* 6384 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6387 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6401 /* 6392 */ MCD_OPC_CheckPredicate, 21, 124, 47, 0, // Skip to: 18553 /* 6397 */ MCD_OPC_Decode, 145, 18, 101, // Opcode: VSHLuv1i64 /* 6401 */ MCD_OPC_FilterValue, 1, 115, 47, 0, // Skip to: 18553 /* 6406 */ MCD_OPC_CheckPredicate, 21, 110, 47, 0, // Skip to: 18553 /* 6411 */ MCD_OPC_Decode, 147, 18, 102, // Opcode: VSHLuv2i64 /* 6415 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6451 /* 6420 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6423 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6437 /* 6428 */ MCD_OPC_CheckPredicate, 21, 88, 47, 0, // Skip to: 18553 /* 6433 */ MCD_OPC_Decode, 173, 17, 101, // Opcode: VRSHLuv1i64 /* 6437 */ MCD_OPC_FilterValue, 1, 79, 47, 0, // Skip to: 18553 /* 6442 */ MCD_OPC_CheckPredicate, 21, 74, 47, 0, // Skip to: 18553 /* 6447 */ MCD_OPC_Decode, 175, 17, 102, // Opcode: VRSHLuv2i64 /* 6451 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6487 /* 6456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6459 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6473 /* 6464 */ MCD_OPC_CheckPredicate, 21, 52, 47, 0, // Skip to: 18553 /* 6469 */ MCD_OPC_Decode, 230, 20, 97, // Opcode: VSUBv1i64 /* 6473 */ MCD_OPC_FilterValue, 1, 43, 47, 0, // Skip to: 18553 /* 6478 */ MCD_OPC_CheckPredicate, 21, 38, 47, 0, // Skip to: 18553 /* 6483 */ MCD_OPC_Decode, 232, 20, 98, // Opcode: VSUBv2i64 /* 6487 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6523 /* 6492 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6495 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6509 /* 6500 */ MCD_OPC_CheckPredicate, 22, 16, 47, 0, // Skip to: 18553 /* 6505 */ MCD_OPC_Decode, 200, 7, 97, // Opcode: VABDhd /* 6509 */ MCD_OPC_FilterValue, 1, 7, 47, 0, // Skip to: 18553 /* 6514 */ MCD_OPC_CheckPredicate, 22, 2, 47, 0, // Skip to: 18553 /* 6519 */ MCD_OPC_Decode, 201, 7, 98, // Opcode: VABDhq /* 6523 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 6559 /* 6528 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6545 /* 6536 */ MCD_OPC_CheckPredicate, 22, 236, 46, 0, // Skip to: 18553 /* 6541 */ MCD_OPC_Decode, 203, 8, 97, // Opcode: VCGThd /* 6545 */ MCD_OPC_FilterValue, 1, 227, 46, 0, // Skip to: 18553 /* 6550 */ MCD_OPC_CheckPredicate, 22, 222, 46, 0, // Skip to: 18553 /* 6555 */ MCD_OPC_Decode, 204, 8, 98, // Opcode: VCGThq /* 6559 */ MCD_OPC_FilterValue, 15, 213, 46, 0, // Skip to: 18553 /* 6564 */ MCD_OPC_CheckPredicate, 22, 208, 46, 0, // Skip to: 18553 /* 6569 */ MCD_OPC_CheckField, 6, 1, 0, 201, 46, 0, // Skip to: 18553 /* 6576 */ MCD_OPC_Decode, 160, 15, 97, // Opcode: VPMINh /* 6580 */ MCD_OPC_FilterValue, 231, 3, 191, 46, 0, // Skip to: 18553 /* 6586 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6589 */ MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 7097 /* 6594 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 6597 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 6661 /* 6602 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6605 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6619 /* 6610 */ MCD_OPC_CheckPredicate, 21, 162, 46, 0, // Skip to: 18553 /* 6615 */ MCD_OPC_Decode, 231, 16, 126, // Opcode: VREV64d8 /* 6619 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6633 /* 6624 */ MCD_OPC_CheckPredicate, 21, 148, 46, 0, // Skip to: 18553 /* 6629 */ MCD_OPC_Decode, 234, 16, 127, // Opcode: VREV64q8 /* 6633 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6647 /* 6638 */ MCD_OPC_CheckPredicate, 21, 134, 46, 0, // Skip to: 18553 /* 6643 */ MCD_OPC_Decode, 226, 16, 126, // Opcode: VREV32d8 /* 6647 */ MCD_OPC_FilterValue, 3, 125, 46, 0, // Skip to: 18553 /* 6652 */ MCD_OPC_CheckPredicate, 21, 120, 46, 0, // Skip to: 18553 /* 6657 */ MCD_OPC_Decode, 228, 16, 127, // Opcode: VREV32q8 /* 6661 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 6725 /* 6666 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6669 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6683 /* 6674 */ MCD_OPC_CheckPredicate, 21, 98, 46, 0, // Skip to: 18553 /* 6679 */ MCD_OPC_Decode, 226, 8, 126, // Opcode: VCGTzv8i8 /* 6683 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6697 /* 6688 */ MCD_OPC_CheckPredicate, 21, 84, 46, 0, // Skip to: 18553 /* 6693 */ MCD_OPC_Decode, 217, 8, 127, // Opcode: VCGTzv16i8 /* 6697 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6711 /* 6702 */ MCD_OPC_CheckPredicate, 21, 70, 46, 0, // Skip to: 18553 /* 6707 */ MCD_OPC_Decode, 200, 8, 126, // Opcode: VCGEzv8i8 /* 6711 */ MCD_OPC_FilterValue, 3, 61, 46, 0, // Skip to: 18553 /* 6716 */ MCD_OPC_CheckPredicate, 21, 56, 46, 0, // Skip to: 18553 /* 6721 */ MCD_OPC_Decode, 191, 8, 127, // Opcode: VCGEzv16i8 /* 6725 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 6793 /* 6730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6733 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6748 /* 6738 */ MCD_OPC_CheckPredicate, 21, 34, 46, 0, // Skip to: 18553 /* 6743 */ MCD_OPC_Decode, 237, 20, 128, 1, // Opcode: VSWPd /* 6748 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6763 /* 6753 */ MCD_OPC_CheckPredicate, 21, 19, 46, 0, // Skip to: 18553 /* 6758 */ MCD_OPC_Decode, 238, 20, 129, 1, // Opcode: VSWPq /* 6763 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6778 /* 6768 */ MCD_OPC_CheckPredicate, 21, 4, 46, 0, // Skip to: 18553 /* 6773 */ MCD_OPC_Decode, 149, 21, 128, 1, // Opcode: VTRNd8 /* 6778 */ MCD_OPC_FilterValue, 3, 250, 45, 0, // Skip to: 18553 /* 6783 */ MCD_OPC_CheckPredicate, 21, 245, 45, 0, // Skip to: 18553 /* 6788 */ MCD_OPC_Decode, 152, 21, 129, 1, // Opcode: VTRNq8 /* 6793 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 6857 /* 6798 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6815 /* 6806 */ MCD_OPC_CheckPredicate, 21, 222, 45, 0, // Skip to: 18553 /* 6811 */ MCD_OPC_Decode, 229, 16, 126, // Opcode: VREV64d16 /* 6815 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6829 /* 6820 */ MCD_OPC_CheckPredicate, 21, 208, 45, 0, // Skip to: 18553 /* 6825 */ MCD_OPC_Decode, 232, 16, 127, // Opcode: VREV64q16 /* 6829 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6843 /* 6834 */ MCD_OPC_CheckPredicate, 21, 194, 45, 0, // Skip to: 18553 /* 6839 */ MCD_OPC_Decode, 225, 16, 126, // Opcode: VREV32d16 /* 6843 */ MCD_OPC_FilterValue, 3, 185, 45, 0, // Skip to: 18553 /* 6848 */ MCD_OPC_CheckPredicate, 21, 180, 45, 0, // Skip to: 18553 /* 6853 */ MCD_OPC_Decode, 227, 16, 127, // Opcode: VREV32q16 /* 6857 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 6921 /* 6862 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6865 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6879 /* 6870 */ MCD_OPC_CheckPredicate, 21, 158, 45, 0, // Skip to: 18553 /* 6875 */ MCD_OPC_Decode, 222, 8, 126, // Opcode: VCGTzv4i16 /* 6879 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6893 /* 6884 */ MCD_OPC_CheckPredicate, 21, 144, 45, 0, // Skip to: 18553 /* 6889 */ MCD_OPC_Decode, 225, 8, 127, // Opcode: VCGTzv8i16 /* 6893 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6907 /* 6898 */ MCD_OPC_CheckPredicate, 21, 130, 45, 0, // Skip to: 18553 /* 6903 */ MCD_OPC_Decode, 196, 8, 126, // Opcode: VCGEzv4i16 /* 6907 */ MCD_OPC_FilterValue, 3, 121, 45, 0, // Skip to: 18553 /* 6912 */ MCD_OPC_CheckPredicate, 21, 116, 45, 0, // Skip to: 18553 /* 6917 */ MCD_OPC_Decode, 199, 8, 127, // Opcode: VCGEzv8i16 /* 6921 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 6959 /* 6926 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6929 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6944 /* 6934 */ MCD_OPC_CheckPredicate, 21, 94, 45, 0, // Skip to: 18553 /* 6939 */ MCD_OPC_Decode, 147, 21, 128, 1, // Opcode: VTRNd16 /* 6944 */ MCD_OPC_FilterValue, 3, 84, 45, 0, // Skip to: 18553 /* 6949 */ MCD_OPC_CheckPredicate, 21, 79, 45, 0, // Skip to: 18553 /* 6954 */ MCD_OPC_Decode, 150, 21, 129, 1, // Opcode: VTRNq16 /* 6959 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6995 /* 6964 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 6967 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6981 /* 6972 */ MCD_OPC_CheckPredicate, 21, 56, 45, 0, // Skip to: 18553 /* 6977 */ MCD_OPC_Decode, 230, 16, 126, // Opcode: VREV64d32 /* 6981 */ MCD_OPC_FilterValue, 1, 47, 45, 0, // Skip to: 18553 /* 6986 */ MCD_OPC_CheckPredicate, 21, 42, 45, 0, // Skip to: 18553 /* 6991 */ MCD_OPC_Decode, 233, 16, 127, // Opcode: VREV64q32 /* 6995 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7059 /* 7000 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7003 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7017 /* 7008 */ MCD_OPC_CheckPredicate, 21, 20, 45, 0, // Skip to: 18553 /* 7013 */ MCD_OPC_Decode, 219, 8, 126, // Opcode: VCGTzv2i32 /* 7017 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7031 /* 7022 */ MCD_OPC_CheckPredicate, 21, 6, 45, 0, // Skip to: 18553 /* 7027 */ MCD_OPC_Decode, 223, 8, 127, // Opcode: VCGTzv4i32 /* 7031 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7045 /* 7036 */ MCD_OPC_CheckPredicate, 21, 248, 44, 0, // Skip to: 18553 /* 7041 */ MCD_OPC_Decode, 193, 8, 126, // Opcode: VCGEzv2i32 /* 7045 */ MCD_OPC_FilterValue, 3, 239, 44, 0, // Skip to: 18553 /* 7050 */ MCD_OPC_CheckPredicate, 21, 234, 44, 0, // Skip to: 18553 /* 7055 */ MCD_OPC_Decode, 197, 8, 127, // Opcode: VCGEzv4i32 /* 7059 */ MCD_OPC_FilterValue, 10, 225, 44, 0, // Skip to: 18553 /* 7064 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7067 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7082 /* 7072 */ MCD_OPC_CheckPredicate, 21, 212, 44, 0, // Skip to: 18553 /* 7077 */ MCD_OPC_Decode, 148, 21, 128, 1, // Opcode: VTRNd32 /* 7082 */ MCD_OPC_FilterValue, 3, 202, 44, 0, // Skip to: 18553 /* 7087 */ MCD_OPC_CheckPredicate, 21, 197, 44, 0, // Skip to: 18553 /* 7092 */ MCD_OPC_Decode, 151, 21, 129, 1, // Opcode: VTRNq32 /* 7097 */ MCD_OPC_FilterValue, 1, 149, 1, 0, // Skip to: 7507 /* 7102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7105 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7141 /* 7110 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7113 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7127 /* 7118 */ MCD_OPC_CheckPredicate, 21, 166, 44, 0, // Skip to: 18553 /* 7123 */ MCD_OPC_Decode, 223, 16, 126, // Opcode: VREV16d8 /* 7127 */ MCD_OPC_FilterValue, 1, 157, 44, 0, // Skip to: 18553 /* 7132 */ MCD_OPC_CheckPredicate, 21, 152, 44, 0, // Skip to: 18553 /* 7137 */ MCD_OPC_Decode, 224, 16, 127, // Opcode: VREV16q8 /* 7141 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 7205 /* 7146 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7149 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7163 /* 7154 */ MCD_OPC_CheckPredicate, 21, 130, 44, 0, // Skip to: 18553 /* 7159 */ MCD_OPC_Decode, 174, 8, 126, // Opcode: VCEQzv8i8 /* 7163 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7177 /* 7168 */ MCD_OPC_CheckPredicate, 21, 116, 44, 0, // Skip to: 18553 /* 7173 */ MCD_OPC_Decode, 165, 8, 127, // Opcode: VCEQzv16i8 /* 7177 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7191 /* 7182 */ MCD_OPC_CheckPredicate, 21, 102, 44, 0, // Skip to: 18553 /* 7187 */ MCD_OPC_Decode, 236, 8, 126, // Opcode: VCLEzv8i8 /* 7191 */ MCD_OPC_FilterValue, 3, 93, 44, 0, // Skip to: 18553 /* 7196 */ MCD_OPC_CheckPredicate, 21, 88, 44, 0, // Skip to: 18553 /* 7201 */ MCD_OPC_Decode, 227, 8, 127, // Opcode: VCLEzv16i8 /* 7205 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7273 /* 7210 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7228 /* 7218 */ MCD_OPC_CheckPredicate, 21, 66, 44, 0, // Skip to: 18553 /* 7223 */ MCD_OPC_Decode, 173, 21, 128, 1, // Opcode: VUZPd8 /* 7228 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7243 /* 7233 */ MCD_OPC_CheckPredicate, 21, 51, 44, 0, // Skip to: 18553 /* 7238 */ MCD_OPC_Decode, 176, 21, 129, 1, // Opcode: VUZPq8 /* 7243 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7258 /* 7248 */ MCD_OPC_CheckPredicate, 21, 36, 44, 0, // Skip to: 18553 /* 7253 */ MCD_OPC_Decode, 178, 21, 128, 1, // Opcode: VZIPd8 /* 7258 */ MCD_OPC_FilterValue, 3, 26, 44, 0, // Skip to: 18553 /* 7263 */ MCD_OPC_CheckPredicate, 21, 21, 44, 0, // Skip to: 18553 /* 7268 */ MCD_OPC_Decode, 181, 21, 129, 1, // Opcode: VZIPq8 /* 7273 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 7337 /* 7278 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7281 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7295 /* 7286 */ MCD_OPC_CheckPredicate, 21, 254, 43, 0, // Skip to: 18553 /* 7291 */ MCD_OPC_Decode, 170, 8, 126, // Opcode: VCEQzv4i16 /* 7295 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7309 /* 7300 */ MCD_OPC_CheckPredicate, 21, 240, 43, 0, // Skip to: 18553 /* 7305 */ MCD_OPC_Decode, 173, 8, 127, // Opcode: VCEQzv8i16 /* 7309 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7323 /* 7314 */ MCD_OPC_CheckPredicate, 21, 226, 43, 0, // Skip to: 18553 /* 7319 */ MCD_OPC_Decode, 232, 8, 126, // Opcode: VCLEzv4i16 /* 7323 */ MCD_OPC_FilterValue, 3, 217, 43, 0, // Skip to: 18553 /* 7328 */ MCD_OPC_CheckPredicate, 21, 212, 43, 0, // Skip to: 18553 /* 7333 */ MCD_OPC_Decode, 235, 8, 127, // Opcode: VCLEzv8i16 /* 7337 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7405 /* 7342 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7345 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7360 /* 7350 */ MCD_OPC_CheckPredicate, 21, 190, 43, 0, // Skip to: 18553 /* 7355 */ MCD_OPC_Decode, 172, 21, 128, 1, // Opcode: VUZPd16 /* 7360 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7375 /* 7365 */ MCD_OPC_CheckPredicate, 21, 175, 43, 0, // Skip to: 18553 /* 7370 */ MCD_OPC_Decode, 174, 21, 129, 1, // Opcode: VUZPq16 /* 7375 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7390 /* 7380 */ MCD_OPC_CheckPredicate, 21, 160, 43, 0, // Skip to: 18553 /* 7385 */ MCD_OPC_Decode, 177, 21, 128, 1, // Opcode: VZIPd16 /* 7390 */ MCD_OPC_FilterValue, 3, 150, 43, 0, // Skip to: 18553 /* 7395 */ MCD_OPC_CheckPredicate, 21, 145, 43, 0, // Skip to: 18553 /* 7400 */ MCD_OPC_Decode, 179, 21, 129, 1, // Opcode: VZIPq16 /* 7405 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7469 /* 7410 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7413 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7427 /* 7418 */ MCD_OPC_CheckPredicate, 21, 122, 43, 0, // Skip to: 18553 /* 7423 */ MCD_OPC_Decode, 167, 8, 126, // Opcode: VCEQzv2i32 /* 7427 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7441 /* 7432 */ MCD_OPC_CheckPredicate, 21, 108, 43, 0, // Skip to: 18553 /* 7437 */ MCD_OPC_Decode, 171, 8, 127, // Opcode: VCEQzv4i32 /* 7441 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7455 /* 7446 */ MCD_OPC_CheckPredicate, 21, 94, 43, 0, // Skip to: 18553 /* 7451 */ MCD_OPC_Decode, 229, 8, 126, // Opcode: VCLEzv2i32 /* 7455 */ MCD_OPC_FilterValue, 3, 85, 43, 0, // Skip to: 18553 /* 7460 */ MCD_OPC_CheckPredicate, 21, 80, 43, 0, // Skip to: 18553 /* 7465 */ MCD_OPC_Decode, 233, 8, 127, // Opcode: VCLEzv4i32 /* 7469 */ MCD_OPC_FilterValue, 10, 71, 43, 0, // Skip to: 18553 /* 7474 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7477 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7492 /* 7482 */ MCD_OPC_CheckPredicate, 21, 58, 43, 0, // Skip to: 18553 /* 7487 */ MCD_OPC_Decode, 175, 21, 129, 1, // Opcode: VUZPq32 /* 7492 */ MCD_OPC_FilterValue, 3, 48, 43, 0, // Skip to: 18553 /* 7497 */ MCD_OPC_CheckPredicate, 21, 43, 43, 0, // Skip to: 18553 /* 7502 */ MCD_OPC_Decode, 180, 21, 129, 1, // Opcode: VZIPq32 /* 7507 */ MCD_OPC_FilterValue, 2, 251, 1, 0, // Skip to: 8019 /* 7512 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7515 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 7579 /* 7520 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7537 /* 7528 */ MCD_OPC_CheckPredicate, 21, 12, 43, 0, // Skip to: 18553 /* 7533 */ MCD_OPC_Decode, 139, 15, 126, // Opcode: VPADDLsv8i8 /* 7537 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7551 /* 7542 */ MCD_OPC_CheckPredicate, 21, 254, 42, 0, // Skip to: 18553 /* 7547 */ MCD_OPC_Decode, 134, 15, 127, // Opcode: VPADDLsv16i8 /* 7551 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7565 /* 7556 */ MCD_OPC_CheckPredicate, 21, 240, 42, 0, // Skip to: 18553 /* 7561 */ MCD_OPC_Decode, 145, 15, 126, // Opcode: VPADDLuv8i8 /* 7565 */ MCD_OPC_FilterValue, 3, 231, 42, 0, // Skip to: 18553 /* 7570 */ MCD_OPC_CheckPredicate, 21, 226, 42, 0, // Skip to: 18553 /* 7575 */ MCD_OPC_Decode, 140, 15, 127, // Opcode: VPADDLuv16i8 /* 7579 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7615 /* 7584 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7601 /* 7592 */ MCD_OPC_CheckPredicate, 21, 204, 42, 0, // Skip to: 18553 /* 7597 */ MCD_OPC_Decode, 252, 8, 126, // Opcode: VCLTzv8i8 /* 7601 */ MCD_OPC_FilterValue, 1, 195, 42, 0, // Skip to: 18553 /* 7606 */ MCD_OPC_CheckPredicate, 21, 190, 42, 0, // Skip to: 18553 /* 7611 */ MCD_OPC_Decode, 243, 8, 127, // Opcode: VCLTzv16i8 /* 7615 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7683 /* 7620 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7623 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7638 /* 7628 */ MCD_OPC_CheckPredicate, 21, 168, 42, 0, // Skip to: 18553 /* 7633 */ MCD_OPC_Decode, 148, 14, 130, 1, // Opcode: VMOVNv8i8 /* 7638 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7653 /* 7643 */ MCD_OPC_CheckPredicate, 21, 153, 42, 0, // Skip to: 18553 /* 7648 */ MCD_OPC_Decode, 211, 15, 130, 1, // Opcode: VQMOVNsuv8i8 /* 7653 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7668 /* 7658 */ MCD_OPC_CheckPredicate, 21, 138, 42, 0, // Skip to: 18553 /* 7663 */ MCD_OPC_Decode, 214, 15, 130, 1, // Opcode: VQMOVNsv8i8 /* 7668 */ MCD_OPC_FilterValue, 3, 128, 42, 0, // Skip to: 18553 /* 7673 */ MCD_OPC_CheckPredicate, 21, 123, 42, 0, // Skip to: 18553 /* 7678 */ MCD_OPC_Decode, 217, 15, 130, 1, // Opcode: VQMOVNuv8i8 /* 7683 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 7747 /* 7688 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7691 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7705 /* 7696 */ MCD_OPC_CheckPredicate, 21, 100, 42, 0, // Skip to: 18553 /* 7701 */ MCD_OPC_Decode, 136, 15, 126, // Opcode: VPADDLsv4i16 /* 7705 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7719 /* 7710 */ MCD_OPC_CheckPredicate, 21, 86, 42, 0, // Skip to: 18553 /* 7715 */ MCD_OPC_Decode, 138, 15, 127, // Opcode: VPADDLsv8i16 /* 7719 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7733 /* 7724 */ MCD_OPC_CheckPredicate, 21, 72, 42, 0, // Skip to: 18553 /* 7729 */ MCD_OPC_Decode, 142, 15, 126, // Opcode: VPADDLuv4i16 /* 7733 */ MCD_OPC_FilterValue, 3, 63, 42, 0, // Skip to: 18553 /* 7738 */ MCD_OPC_CheckPredicate, 21, 58, 42, 0, // Skip to: 18553 /* 7743 */ MCD_OPC_Decode, 144, 15, 127, // Opcode: VPADDLuv8i16 /* 7747 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 7783 /* 7752 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7755 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7769 /* 7760 */ MCD_OPC_CheckPredicate, 21, 36, 42, 0, // Skip to: 18553 /* 7765 */ MCD_OPC_Decode, 248, 8, 126, // Opcode: VCLTzv4i16 /* 7769 */ MCD_OPC_FilterValue, 1, 27, 42, 0, // Skip to: 18553 /* 7774 */ MCD_OPC_CheckPredicate, 21, 22, 42, 0, // Skip to: 18553 /* 7779 */ MCD_OPC_Decode, 251, 8, 127, // Opcode: VCLTzv8i16 /* 7783 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7851 /* 7788 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7791 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7806 /* 7796 */ MCD_OPC_CheckPredicate, 21, 0, 42, 0, // Skip to: 18553 /* 7801 */ MCD_OPC_Decode, 147, 14, 130, 1, // Opcode: VMOVNv4i16 /* 7806 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7821 /* 7811 */ MCD_OPC_CheckPredicate, 21, 241, 41, 0, // Skip to: 18553 /* 7816 */ MCD_OPC_Decode, 210, 15, 130, 1, // Opcode: VQMOVNsuv4i16 /* 7821 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7836 /* 7826 */ MCD_OPC_CheckPredicate, 21, 226, 41, 0, // Skip to: 18553 /* 7831 */ MCD_OPC_Decode, 213, 15, 130, 1, // Opcode: VQMOVNsv4i16 /* 7836 */ MCD_OPC_FilterValue, 3, 216, 41, 0, // Skip to: 18553 /* 7841 */ MCD_OPC_CheckPredicate, 21, 211, 41, 0, // Skip to: 18553 /* 7846 */ MCD_OPC_Decode, 216, 15, 130, 1, // Opcode: VQMOVNuv4i16 /* 7851 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 7915 /* 7856 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7859 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7873 /* 7864 */ MCD_OPC_CheckPredicate, 21, 188, 41, 0, // Skip to: 18553 /* 7869 */ MCD_OPC_Decode, 135, 15, 126, // Opcode: VPADDLsv2i32 /* 7873 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7887 /* 7878 */ MCD_OPC_CheckPredicate, 21, 174, 41, 0, // Skip to: 18553 /* 7883 */ MCD_OPC_Decode, 137, 15, 127, // Opcode: VPADDLsv4i32 /* 7887 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7901 /* 7892 */ MCD_OPC_CheckPredicate, 21, 160, 41, 0, // Skip to: 18553 /* 7897 */ MCD_OPC_Decode, 141, 15, 126, // Opcode: VPADDLuv2i32 /* 7901 */ MCD_OPC_FilterValue, 3, 151, 41, 0, // Skip to: 18553 /* 7906 */ MCD_OPC_CheckPredicate, 21, 146, 41, 0, // Skip to: 18553 /* 7911 */ MCD_OPC_Decode, 143, 15, 127, // Opcode: VPADDLuv4i32 /* 7915 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7951 /* 7920 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7923 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7937 /* 7928 */ MCD_OPC_CheckPredicate, 21, 124, 41, 0, // Skip to: 18553 /* 7933 */ MCD_OPC_Decode, 245, 8, 126, // Opcode: VCLTzv2i32 /* 7937 */ MCD_OPC_FilterValue, 1, 115, 41, 0, // Skip to: 18553 /* 7942 */ MCD_OPC_CheckPredicate, 21, 110, 41, 0, // Skip to: 18553 /* 7947 */ MCD_OPC_Decode, 249, 8, 127, // Opcode: VCLTzv4i32 /* 7951 */ MCD_OPC_FilterValue, 10, 101, 41, 0, // Skip to: 18553 /* 7956 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 7959 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7974 /* 7964 */ MCD_OPC_CheckPredicate, 21, 88, 41, 0, // Skip to: 18553 /* 7969 */ MCD_OPC_Decode, 146, 14, 130, 1, // Opcode: VMOVNv2i32 /* 7974 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7989 /* 7979 */ MCD_OPC_CheckPredicate, 21, 73, 41, 0, // Skip to: 18553 /* 7984 */ MCD_OPC_Decode, 209, 15, 130, 1, // Opcode: VQMOVNsuv2i32 /* 7989 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8004 /* 7994 */ MCD_OPC_CheckPredicate, 21, 58, 41, 0, // Skip to: 18553 /* 7999 */ MCD_OPC_Decode, 212, 15, 130, 1, // Opcode: VQMOVNsv2i32 /* 8004 */ MCD_OPC_FilterValue, 3, 48, 41, 0, // Skip to: 18553 /* 8009 */ MCD_OPC_CheckPredicate, 21, 43, 41, 0, // Skip to: 18553 /* 8014 */ MCD_OPC_Decode, 215, 15, 130, 1, // Opcode: VQMOVNuv2i32 /* 8019 */ MCD_OPC_FilterValue, 3, 5, 1, 0, // Skip to: 8285 /* 8024 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 8027 */ MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 8091 /* 8032 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8035 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8049 /* 8040 */ MCD_OPC_CheckPredicate, 21, 12, 41, 0, // Skip to: 18553 /* 8045 */ MCD_OPC_Decode, 226, 7, 126, // Opcode: VABSv8i8 /* 8049 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8063 /* 8054 */ MCD_OPC_CheckPredicate, 21, 254, 40, 0, // Skip to: 18553 /* 8059 */ MCD_OPC_Decode, 221, 7, 127, // Opcode: VABSv16i8 /* 8063 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8077 /* 8068 */ MCD_OPC_CheckPredicate, 21, 240, 40, 0, // Skip to: 18553 /* 8073 */ MCD_OPC_Decode, 231, 14, 126, // Opcode: VNEGs8d /* 8077 */ MCD_OPC_FilterValue, 3, 231, 40, 0, // Skip to: 18553 /* 8082 */ MCD_OPC_CheckPredicate, 21, 226, 40, 0, // Skip to: 18553 /* 8087 */ MCD_OPC_Decode, 232, 14, 127, // Opcode: VNEGs8q /* 8091 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 8113 /* 8096 */ MCD_OPC_CheckPredicate, 21, 212, 40, 0, // Skip to: 18553 /* 8101 */ MCD_OPC_CheckField, 6, 2, 0, 205, 40, 0, // Skip to: 18553 /* 8108 */ MCD_OPC_Decode, 249, 17, 131, 1, // Opcode: VSHLLi8 /* 8113 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8177 /* 8118 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8121 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8135 /* 8126 */ MCD_OPC_CheckPredicate, 21, 182, 40, 0, // Skip to: 18553 /* 8131 */ MCD_OPC_Decode, 223, 7, 126, // Opcode: VABSv4i16 /* 8135 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8149 /* 8140 */ MCD_OPC_CheckPredicate, 21, 168, 40, 0, // Skip to: 18553 /* 8145 */ MCD_OPC_Decode, 225, 7, 127, // Opcode: VABSv8i16 /* 8149 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8163 /* 8154 */ MCD_OPC_CheckPredicate, 21, 154, 40, 0, // Skip to: 18553 /* 8159 */ MCD_OPC_Decode, 227, 14, 126, // Opcode: VNEGs16d /* 8163 */ MCD_OPC_FilterValue, 3, 145, 40, 0, // Skip to: 18553 /* 8168 */ MCD_OPC_CheckPredicate, 21, 140, 40, 0, // Skip to: 18553 /* 8173 */ MCD_OPC_Decode, 228, 14, 127, // Opcode: VNEGs16q /* 8177 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 8199 /* 8182 */ MCD_OPC_CheckPredicate, 21, 126, 40, 0, // Skip to: 18553 /* 8187 */ MCD_OPC_CheckField, 6, 2, 0, 119, 40, 0, // Skip to: 18553 /* 8194 */ MCD_OPC_Decode, 247, 17, 131, 1, // Opcode: VSHLLi16 /* 8199 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8263 /* 8204 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8207 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8221 /* 8212 */ MCD_OPC_CheckPredicate, 21, 96, 40, 0, // Skip to: 18553 /* 8217 */ MCD_OPC_Decode, 222, 7, 126, // Opcode: VABSv2i32 /* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8235 /* 8226 */ MCD_OPC_CheckPredicate, 21, 82, 40, 0, // Skip to: 18553 /* 8231 */ MCD_OPC_Decode, 224, 7, 127, // Opcode: VABSv4i32 /* 8235 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8249 /* 8240 */ MCD_OPC_CheckPredicate, 21, 68, 40, 0, // Skip to: 18553 /* 8245 */ MCD_OPC_Decode, 229, 14, 126, // Opcode: VNEGs32d /* 8249 */ MCD_OPC_FilterValue, 3, 59, 40, 0, // Skip to: 18553 /* 8254 */ MCD_OPC_CheckPredicate, 21, 54, 40, 0, // Skip to: 18553 /* 8259 */ MCD_OPC_Decode, 230, 14, 127, // Opcode: VNEGs32q /* 8263 */ MCD_OPC_FilterValue, 10, 45, 40, 0, // Skip to: 18553 /* 8268 */ MCD_OPC_CheckPredicate, 21, 40, 40, 0, // Skip to: 18553 /* 8273 */ MCD_OPC_CheckField, 6, 2, 0, 33, 40, 0, // Skip to: 18553 /* 8280 */ MCD_OPC_Decode, 248, 17, 131, 1, // Opcode: VSHLLi32 /* 8285 */ MCD_OPC_FilterValue, 4, 131, 1, 0, // Skip to: 8677 /* 8290 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 8293 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8357 /* 8298 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8301 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8315 /* 8306 */ MCD_OPC_CheckPredicate, 21, 2, 40, 0, // Skip to: 18553 /* 8311 */ MCD_OPC_Decode, 242, 8, 126, // Opcode: VCLSv8i8 /* 8315 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8329 /* 8320 */ MCD_OPC_CheckPredicate, 21, 244, 39, 0, // Skip to: 18553 /* 8325 */ MCD_OPC_Decode, 237, 8, 127, // Opcode: VCLSv16i8 /* 8329 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8343 /* 8334 */ MCD_OPC_CheckPredicate, 21, 230, 39, 0, // Skip to: 18553 /* 8339 */ MCD_OPC_Decode, 130, 9, 126, // Opcode: VCLZv8i8 /* 8343 */ MCD_OPC_FilterValue, 3, 221, 39, 0, // Skip to: 18553 /* 8348 */ MCD_OPC_CheckPredicate, 21, 216, 39, 0, // Skip to: 18553 /* 8353 */ MCD_OPC_Decode, 253, 8, 127, // Opcode: VCLZv16i8 /* 8357 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 8421 /* 8362 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8365 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8379 /* 8370 */ MCD_OPC_CheckPredicate, 21, 194, 39, 0, // Skip to: 18553 /* 8375 */ MCD_OPC_Decode, 239, 8, 126, // Opcode: VCLSv4i16 /* 8379 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8393 /* 8384 */ MCD_OPC_CheckPredicate, 21, 180, 39, 0, // Skip to: 18553 /* 8389 */ MCD_OPC_Decode, 241, 8, 127, // Opcode: VCLSv8i16 /* 8393 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8407 /* 8398 */ MCD_OPC_CheckPredicate, 21, 166, 39, 0, // Skip to: 18553 /* 8403 */ MCD_OPC_Decode, 255, 8, 126, // Opcode: VCLZv4i16 /* 8407 */ MCD_OPC_FilterValue, 3, 157, 39, 0, // Skip to: 18553 /* 8412 */ MCD_OPC_CheckPredicate, 21, 152, 39, 0, // Skip to: 18553 /* 8417 */ MCD_OPC_Decode, 129, 9, 127, // Opcode: VCLZv8i16 /* 8421 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8485 /* 8426 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8429 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8443 /* 8434 */ MCD_OPC_CheckPredicate, 22, 130, 39, 0, // Skip to: 18553 /* 8439 */ MCD_OPC_Decode, 220, 8, 126, // Opcode: VCGTzv4f16 /* 8443 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8457 /* 8448 */ MCD_OPC_CheckPredicate, 22, 116, 39, 0, // Skip to: 18553 /* 8453 */ MCD_OPC_Decode, 224, 8, 127, // Opcode: VCGTzv8f16 /* 8457 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8471 /* 8462 */ MCD_OPC_CheckPredicate, 22, 102, 39, 0, // Skip to: 18553 /* 8467 */ MCD_OPC_Decode, 194, 8, 126, // Opcode: VCGEzv4f16 /* 8471 */ MCD_OPC_FilterValue, 3, 93, 39, 0, // Skip to: 18553 /* 8476 */ MCD_OPC_CheckPredicate, 22, 88, 39, 0, // Skip to: 18553 /* 8481 */ MCD_OPC_Decode, 198, 8, 127, // Opcode: VCGEzv8f16 /* 8485 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 8549 /* 8490 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8507 /* 8498 */ MCD_OPC_CheckPredicate, 21, 66, 39, 0, // Skip to: 18553 /* 8503 */ MCD_OPC_Decode, 238, 8, 126, // Opcode: VCLSv2i32 /* 8507 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8521 /* 8512 */ MCD_OPC_CheckPredicate, 21, 52, 39, 0, // Skip to: 18553 /* 8517 */ MCD_OPC_Decode, 240, 8, 127, // Opcode: VCLSv4i32 /* 8521 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8535 /* 8526 */ MCD_OPC_CheckPredicate, 21, 38, 39, 0, // Skip to: 18553 /* 8531 */ MCD_OPC_Decode, 254, 8, 126, // Opcode: VCLZv2i32 /* 8535 */ MCD_OPC_FilterValue, 3, 29, 39, 0, // Skip to: 18553 /* 8540 */ MCD_OPC_CheckPredicate, 21, 24, 39, 0, // Skip to: 18553 /* 8545 */ MCD_OPC_Decode, 128, 9, 127, // Opcode: VCLZv4i32 /* 8549 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8613 /* 8554 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8557 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8571 /* 8562 */ MCD_OPC_CheckPredicate, 21, 2, 39, 0, // Skip to: 18553 /* 8567 */ MCD_OPC_Decode, 218, 8, 126, // Opcode: VCGTzv2f32 /* 8571 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8585 /* 8576 */ MCD_OPC_CheckPredicate, 21, 244, 38, 0, // Skip to: 18553 /* 8581 */ MCD_OPC_Decode, 221, 8, 127, // Opcode: VCGTzv4f32 /* 8585 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8599 /* 8590 */ MCD_OPC_CheckPredicate, 21, 230, 38, 0, // Skip to: 18553 /* 8595 */ MCD_OPC_Decode, 192, 8, 126, // Opcode: VCGEzv2f32 /* 8599 */ MCD_OPC_FilterValue, 3, 221, 38, 0, // Skip to: 18553 /* 8604 */ MCD_OPC_CheckPredicate, 21, 216, 38, 0, // Skip to: 18553 /* 8609 */ MCD_OPC_Decode, 195, 8, 127, // Opcode: VCGEzv4f32 /* 8613 */ MCD_OPC_FilterValue, 11, 207, 38, 0, // Skip to: 18553 /* 8618 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8621 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8635 /* 8626 */ MCD_OPC_CheckPredicate, 21, 194, 38, 0, // Skip to: 18553 /* 8631 */ MCD_OPC_Decode, 213, 16, 126, // Opcode: VRECPEd /* 8635 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8649 /* 8640 */ MCD_OPC_CheckPredicate, 21, 180, 38, 0, // Skip to: 18553 /* 8645 */ MCD_OPC_Decode, 218, 16, 127, // Opcode: VRECPEq /* 8649 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8663 /* 8654 */ MCD_OPC_CheckPredicate, 21, 166, 38, 0, // Skip to: 18553 /* 8659 */ MCD_OPC_Decode, 199, 17, 126, // Opcode: VRSQRTEd /* 8663 */ MCD_OPC_FilterValue, 3, 157, 38, 0, // Skip to: 18553 /* 8668 */ MCD_OPC_CheckPredicate, 21, 152, 38, 0, // Skip to: 18553 /* 8673 */ MCD_OPC_Decode, 204, 17, 127, // Opcode: VRSQRTEq /* 8677 */ MCD_OPC_FilterValue, 5, 67, 1, 0, // Skip to: 9005 /* 8682 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 8685 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8749 /* 8690 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8693 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8707 /* 8698 */ MCD_OPC_CheckPredicate, 21, 122, 38, 0, // Skip to: 18553 /* 8703 */ MCD_OPC_Decode, 151, 9, 126, // Opcode: VCNTd /* 8707 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8721 /* 8712 */ MCD_OPC_CheckPredicate, 21, 108, 38, 0, // Skip to: 18553 /* 8717 */ MCD_OPC_Decode, 152, 9, 127, // Opcode: VCNTq /* 8721 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8735 /* 8726 */ MCD_OPC_CheckPredicate, 21, 94, 38, 0, // Skip to: 18553 /* 8731 */ MCD_OPC_Decode, 214, 14, 126, // Opcode: VMVNd /* 8735 */ MCD_OPC_FilterValue, 3, 85, 38, 0, // Skip to: 18553 /* 8740 */ MCD_OPC_CheckPredicate, 21, 80, 38, 0, // Skip to: 18553 /* 8745 */ MCD_OPC_Decode, 215, 14, 127, // Opcode: VMVNq /* 8749 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8813 /* 8754 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8757 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8771 /* 8762 */ MCD_OPC_CheckPredicate, 22, 58, 38, 0, // Skip to: 18553 /* 8767 */ MCD_OPC_Decode, 168, 8, 126, // Opcode: VCEQzv4f16 /* 8771 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8785 /* 8776 */ MCD_OPC_CheckPredicate, 22, 44, 38, 0, // Skip to: 18553 /* 8781 */ MCD_OPC_Decode, 172, 8, 127, // Opcode: VCEQzv8f16 /* 8785 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8799 /* 8790 */ MCD_OPC_CheckPredicate, 22, 30, 38, 0, // Skip to: 18553 /* 8795 */ MCD_OPC_Decode, 230, 8, 126, // Opcode: VCLEzv4f16 /* 8799 */ MCD_OPC_FilterValue, 3, 21, 38, 0, // Skip to: 18553 /* 8804 */ MCD_OPC_CheckPredicate, 22, 16, 38, 0, // Skip to: 18553 /* 8809 */ MCD_OPC_Decode, 234, 8, 127, // Opcode: VCLEzv8f16 /* 8813 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 8877 /* 8818 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8821 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8835 /* 8826 */ MCD_OPC_CheckPredicate, 22, 250, 37, 0, // Skip to: 18553 /* 8831 */ MCD_OPC_Decode, 216, 16, 126, // Opcode: VRECPEhd /* 8835 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8849 /* 8840 */ MCD_OPC_CheckPredicate, 22, 236, 37, 0, // Skip to: 18553 /* 8845 */ MCD_OPC_Decode, 217, 16, 127, // Opcode: VRECPEhq /* 8849 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8863 /* 8854 */ MCD_OPC_CheckPredicate, 22, 222, 37, 0, // Skip to: 18553 /* 8859 */ MCD_OPC_Decode, 202, 17, 126, // Opcode: VRSQRTEhd /* 8863 */ MCD_OPC_FilterValue, 3, 213, 37, 0, // Skip to: 18553 /* 8868 */ MCD_OPC_CheckPredicate, 22, 208, 37, 0, // Skip to: 18553 /* 8873 */ MCD_OPC_Decode, 203, 17, 127, // Opcode: VRSQRTEhq /* 8877 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8941 /* 8882 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8885 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8899 /* 8890 */ MCD_OPC_CheckPredicate, 21, 186, 37, 0, // Skip to: 18553 /* 8895 */ MCD_OPC_Decode, 166, 8, 126, // Opcode: VCEQzv2f32 /* 8899 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8913 /* 8904 */ MCD_OPC_CheckPredicate, 21, 172, 37, 0, // Skip to: 18553 /* 8909 */ MCD_OPC_Decode, 169, 8, 127, // Opcode: VCEQzv4f32 /* 8913 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8927 /* 8918 */ MCD_OPC_CheckPredicate, 21, 158, 37, 0, // Skip to: 18553 /* 8923 */ MCD_OPC_Decode, 228, 8, 126, // Opcode: VCLEzv2f32 /* 8927 */ MCD_OPC_FilterValue, 3, 149, 37, 0, // Skip to: 18553 /* 8932 */ MCD_OPC_CheckPredicate, 21, 144, 37, 0, // Skip to: 18553 /* 8937 */ MCD_OPC_Decode, 231, 8, 127, // Opcode: VCLEzv4f32 /* 8941 */ MCD_OPC_FilterValue, 11, 135, 37, 0, // Skip to: 18553 /* 8946 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 8949 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8963 /* 8954 */ MCD_OPC_CheckPredicate, 21, 122, 37, 0, // Skip to: 18553 /* 8959 */ MCD_OPC_Decode, 214, 16, 126, // Opcode: VRECPEfd /* 8963 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8977 /* 8968 */ MCD_OPC_CheckPredicate, 21, 108, 37, 0, // Skip to: 18553 /* 8973 */ MCD_OPC_Decode, 215, 16, 127, // Opcode: VRECPEfq /* 8977 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8991 /* 8982 */ MCD_OPC_CheckPredicate, 21, 94, 37, 0, // Skip to: 18553 /* 8987 */ MCD_OPC_Decode, 200, 17, 126, // Opcode: VRSQRTEfd /* 8991 */ MCD_OPC_FilterValue, 3, 85, 37, 0, // Skip to: 18553 /* 8996 */ MCD_OPC_CheckPredicate, 21, 80, 37, 0, // Skip to: 18553 /* 9001 */ MCD_OPC_Decode, 201, 17, 127, // Opcode: VRSQRTEfq /* 9005 */ MCD_OPC_FilterValue, 6, 173, 1, 0, // Skip to: 9439 /* 9010 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 9013 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9081 /* 9018 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9021 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9036 /* 9026 */ MCD_OPC_CheckPredicate, 21, 50, 37, 0, // Skip to: 18553 /* 9031 */ MCD_OPC_Decode, 255, 14, 132, 1, // Opcode: VPADALsv8i8 /* 9036 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9051 /* 9041 */ MCD_OPC_CheckPredicate, 21, 35, 37, 0, // Skip to: 18553 /* 9046 */ MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: VPADALsv16i8 /* 9051 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9066 /* 9056 */ MCD_OPC_CheckPredicate, 21, 20, 37, 0, // Skip to: 18553 /* 9061 */ MCD_OPC_Decode, 133, 15, 132, 1, // Opcode: VPADALuv8i8 /* 9066 */ MCD_OPC_FilterValue, 3, 10, 37, 0, // Skip to: 18553 /* 9071 */ MCD_OPC_CheckPredicate, 21, 5, 37, 0, // Skip to: 18553 /* 9076 */ MCD_OPC_Decode, 128, 15, 133, 1, // Opcode: VPADALuv16i8 /* 9081 */ MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 9149 /* 9086 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9089 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9104 /* 9094 */ MCD_OPC_CheckPredicate, 21, 238, 36, 0, // Skip to: 18553 /* 9099 */ MCD_OPC_Decode, 252, 14, 132, 1, // Opcode: VPADALsv4i16 /* 9104 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9119 /* 9109 */ MCD_OPC_CheckPredicate, 21, 223, 36, 0, // Skip to: 18553 /* 9114 */ MCD_OPC_Decode, 254, 14, 133, 1, // Opcode: VPADALsv8i16 /* 9119 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9134 /* 9124 */ MCD_OPC_CheckPredicate, 21, 208, 36, 0, // Skip to: 18553 /* 9129 */ MCD_OPC_Decode, 130, 15, 132, 1, // Opcode: VPADALuv4i16 /* 9134 */ MCD_OPC_FilterValue, 3, 198, 36, 0, // Skip to: 18553 /* 9139 */ MCD_OPC_CheckPredicate, 21, 193, 36, 0, // Skip to: 18553 /* 9144 */ MCD_OPC_Decode, 132, 15, 133, 1, // Opcode: VPADALuv8i16 /* 9149 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 9185 /* 9154 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9157 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9171 /* 9162 */ MCD_OPC_CheckPredicate, 22, 170, 36, 0, // Skip to: 18553 /* 9167 */ MCD_OPC_Decode, 246, 8, 126, // Opcode: VCLTzv4f16 /* 9171 */ MCD_OPC_FilterValue, 1, 161, 36, 0, // Skip to: 18553 /* 9176 */ MCD_OPC_CheckPredicate, 22, 156, 36, 0, // Skip to: 18553 /* 9181 */ MCD_OPC_Decode, 250, 8, 127, // Opcode: VCLTzv8f16 /* 9185 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9207 /* 9190 */ MCD_OPC_CheckPredicate, 25, 142, 36, 0, // Skip to: 18553 /* 9195 */ MCD_OPC_CheckField, 6, 2, 0, 135, 36, 0, // Skip to: 18553 /* 9202 */ MCD_OPC_Decode, 219, 9, 130, 1, // Opcode: VCVTf2h /* 9207 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9271 /* 9212 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9215 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9229 /* 9220 */ MCD_OPC_CheckPredicate, 22, 112, 36, 0, // Skip to: 18553 /* 9225 */ MCD_OPC_Decode, 239, 9, 126, // Opcode: VCVTs2hd /* 9229 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9243 /* 9234 */ MCD_OPC_CheckPredicate, 22, 98, 36, 0, // Skip to: 18553 /* 9239 */ MCD_OPC_Decode, 240, 9, 127, // Opcode: VCVTs2hq /* 9243 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9257 /* 9248 */ MCD_OPC_CheckPredicate, 22, 84, 36, 0, // Skip to: 18553 /* 9253 */ MCD_OPC_Decode, 243, 9, 126, // Opcode: VCVTu2hd /* 9257 */ MCD_OPC_FilterValue, 3, 75, 36, 0, // Skip to: 18553 /* 9262 */ MCD_OPC_CheckPredicate, 22, 70, 36, 0, // Skip to: 18553 /* 9267 */ MCD_OPC_Decode, 244, 9, 127, // Opcode: VCVTu2hq /* 9271 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 9339 /* 9276 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9294 /* 9284 */ MCD_OPC_CheckPredicate, 21, 48, 36, 0, // Skip to: 18553 /* 9289 */ MCD_OPC_Decode, 251, 14, 132, 1, // Opcode: VPADALsv2i32 /* 9294 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9309 /* 9299 */ MCD_OPC_CheckPredicate, 21, 33, 36, 0, // Skip to: 18553 /* 9304 */ MCD_OPC_Decode, 253, 14, 133, 1, // Opcode: VPADALsv4i32 /* 9309 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9324 /* 9314 */ MCD_OPC_CheckPredicate, 21, 18, 36, 0, // Skip to: 18553 /* 9319 */ MCD_OPC_Decode, 129, 15, 132, 1, // Opcode: VPADALuv2i32 /* 9324 */ MCD_OPC_FilterValue, 3, 8, 36, 0, // Skip to: 18553 /* 9329 */ MCD_OPC_CheckPredicate, 21, 3, 36, 0, // Skip to: 18553 /* 9334 */ MCD_OPC_Decode, 131, 15, 133, 1, // Opcode: VPADALuv4i32 /* 9339 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 9375 /* 9344 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9347 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9361 /* 9352 */ MCD_OPC_CheckPredicate, 21, 236, 35, 0, // Skip to: 18553 /* 9357 */ MCD_OPC_Decode, 244, 8, 126, // Opcode: VCLTzv2f32 /* 9361 */ MCD_OPC_FilterValue, 1, 227, 35, 0, // Skip to: 18553 /* 9366 */ MCD_OPC_CheckPredicate, 21, 222, 35, 0, // Skip to: 18553 /* 9371 */ MCD_OPC_Decode, 247, 8, 127, // Opcode: VCLTzv4f32 /* 9375 */ MCD_OPC_FilterValue, 11, 213, 35, 0, // Skip to: 18553 /* 9380 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9383 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9397 /* 9388 */ MCD_OPC_CheckPredicate, 21, 200, 35, 0, // Skip to: 18553 /* 9393 */ MCD_OPC_Decode, 237, 9, 126, // Opcode: VCVTs2fd /* 9397 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9411 /* 9402 */ MCD_OPC_CheckPredicate, 21, 186, 35, 0, // Skip to: 18553 /* 9407 */ MCD_OPC_Decode, 238, 9, 127, // Opcode: VCVTs2fq /* 9411 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9425 /* 9416 */ MCD_OPC_CheckPredicate, 21, 172, 35, 0, // Skip to: 18553 /* 9421 */ MCD_OPC_Decode, 241, 9, 126, // Opcode: VCVTu2fd /* 9425 */ MCD_OPC_FilterValue, 3, 163, 35, 0, // Skip to: 18553 /* 9430 */ MCD_OPC_CheckPredicate, 21, 158, 35, 0, // Skip to: 18553 /* 9435 */ MCD_OPC_Decode, 242, 9, 127, // Opcode: VCVTu2fq /* 9439 */ MCD_OPC_FilterValue, 7, 217, 1, 0, // Skip to: 9917 /* 9444 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 9447 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 9511 /* 9452 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9455 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9469 /* 9460 */ MCD_OPC_CheckPredicate, 21, 128, 35, 0, // Skip to: 18553 /* 9465 */ MCD_OPC_Decode, 172, 15, 126, // Opcode: VQABSv8i8 /* 9469 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9483 /* 9474 */ MCD_OPC_CheckPredicate, 21, 114, 35, 0, // Skip to: 18553 /* 9479 */ MCD_OPC_Decode, 167, 15, 127, // Opcode: VQABSv16i8 /* 9483 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9497 /* 9488 */ MCD_OPC_CheckPredicate, 21, 100, 35, 0, // Skip to: 18553 /* 9493 */ MCD_OPC_Decode, 223, 15, 126, // Opcode: VQNEGv8i8 /* 9497 */ MCD_OPC_FilterValue, 3, 91, 35, 0, // Skip to: 18553 /* 9502 */ MCD_OPC_CheckPredicate, 21, 86, 35, 0, // Skip to: 18553 /* 9507 */ MCD_OPC_Decode, 218, 15, 127, // Opcode: VQNEGv16i8 /* 9511 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 9575 /* 9516 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9519 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9533 /* 9524 */ MCD_OPC_CheckPredicate, 21, 64, 35, 0, // Skip to: 18553 /* 9529 */ MCD_OPC_Decode, 169, 15, 126, // Opcode: VQABSv4i16 /* 9533 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9547 /* 9538 */ MCD_OPC_CheckPredicate, 21, 50, 35, 0, // Skip to: 18553 /* 9543 */ MCD_OPC_Decode, 171, 15, 127, // Opcode: VQABSv8i16 /* 9547 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9561 /* 9552 */ MCD_OPC_CheckPredicate, 21, 36, 35, 0, // Skip to: 18553 /* 9557 */ MCD_OPC_Decode, 220, 15, 126, // Opcode: VQNEGv4i16 /* 9561 */ MCD_OPC_FilterValue, 3, 27, 35, 0, // Skip to: 18553 /* 9566 */ MCD_OPC_CheckPredicate, 21, 22, 35, 0, // Skip to: 18553 /* 9571 */ MCD_OPC_Decode, 222, 15, 127, // Opcode: VQNEGv8i16 /* 9575 */ MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 9639 /* 9580 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9583 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9597 /* 9588 */ MCD_OPC_CheckPredicate, 22, 0, 35, 0, // Skip to: 18553 /* 9593 */ MCD_OPC_Decode, 219, 7, 126, // Opcode: VABShd /* 9597 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9611 /* 9602 */ MCD_OPC_CheckPredicate, 22, 242, 34, 0, // Skip to: 18553 /* 9607 */ MCD_OPC_Decode, 220, 7, 127, // Opcode: VABShq /* 9611 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9625 /* 9616 */ MCD_OPC_CheckPredicate, 22, 228, 34, 0, // Skip to: 18553 /* 9621 */ MCD_OPC_Decode, 225, 14, 126, // Opcode: VNEGhd /* 9625 */ MCD_OPC_FilterValue, 3, 219, 34, 0, // Skip to: 18553 /* 9630 */ MCD_OPC_CheckPredicate, 22, 214, 34, 0, // Skip to: 18553 /* 9635 */ MCD_OPC_Decode, 226, 14, 127, // Opcode: VNEGhq /* 9639 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9661 /* 9644 */ MCD_OPC_CheckPredicate, 25, 200, 34, 0, // Skip to: 18553 /* 9649 */ MCD_OPC_CheckField, 6, 2, 0, 193, 34, 0, // Skip to: 18553 /* 9656 */ MCD_OPC_Decode, 228, 9, 134, 1, // Opcode: VCVTh2f /* 9661 */ MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9725 /* 9666 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9669 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9683 /* 9674 */ MCD_OPC_CheckPredicate, 22, 170, 34, 0, // Skip to: 18553 /* 9679 */ MCD_OPC_Decode, 229, 9, 126, // Opcode: VCVTh2sd /* 9683 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9697 /* 9688 */ MCD_OPC_CheckPredicate, 22, 156, 34, 0, // Skip to: 18553 /* 9693 */ MCD_OPC_Decode, 230, 9, 127, // Opcode: VCVTh2sq /* 9697 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9711 /* 9702 */ MCD_OPC_CheckPredicate, 22, 142, 34, 0, // Skip to: 18553 /* 9707 */ MCD_OPC_Decode, 231, 9, 126, // Opcode: VCVTh2ud /* 9711 */ MCD_OPC_FilterValue, 3, 133, 34, 0, // Skip to: 18553 /* 9716 */ MCD_OPC_CheckPredicate, 22, 128, 34, 0, // Skip to: 18553 /* 9721 */ MCD_OPC_Decode, 232, 9, 127, // Opcode: VCVTh2uq /* 9725 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 9789 /* 9730 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9733 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9747 /* 9738 */ MCD_OPC_CheckPredicate, 21, 106, 34, 0, // Skip to: 18553 /* 9743 */ MCD_OPC_Decode, 168, 15, 126, // Opcode: VQABSv2i32 /* 9747 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9761 /* 9752 */ MCD_OPC_CheckPredicate, 21, 92, 34, 0, // Skip to: 18553 /* 9757 */ MCD_OPC_Decode, 170, 15, 127, // Opcode: VQABSv4i32 /* 9761 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9775 /* 9766 */ MCD_OPC_CheckPredicate, 21, 78, 34, 0, // Skip to: 18553 /* 9771 */ MCD_OPC_Decode, 219, 15, 126, // Opcode: VQNEGv2i32 /* 9775 */ MCD_OPC_FilterValue, 3, 69, 34, 0, // Skip to: 18553 /* 9780 */ MCD_OPC_CheckPredicate, 21, 64, 34, 0, // Skip to: 18553 /* 9785 */ MCD_OPC_Decode, 221, 15, 127, // Opcode: VQNEGv4i32 /* 9789 */ MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 9853 /* 9794 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9797 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9811 /* 9802 */ MCD_OPC_CheckPredicate, 21, 42, 34, 0, // Skip to: 18553 /* 9807 */ MCD_OPC_Decode, 217, 7, 126, // Opcode: VABSfd /* 9811 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9825 /* 9816 */ MCD_OPC_CheckPredicate, 21, 28, 34, 0, // Skip to: 18553 /* 9821 */ MCD_OPC_Decode, 218, 7, 127, // Opcode: VABSfq /* 9825 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9839 /* 9830 */ MCD_OPC_CheckPredicate, 21, 14, 34, 0, // Skip to: 18553 /* 9835 */ MCD_OPC_Decode, 224, 14, 126, // Opcode: VNEGfd /* 9839 */ MCD_OPC_FilterValue, 3, 5, 34, 0, // Skip to: 18553 /* 9844 */ MCD_OPC_CheckPredicate, 21, 0, 34, 0, // Skip to: 18553 /* 9849 */ MCD_OPC_Decode, 223, 14, 127, // Opcode: VNEGf32q /* 9853 */ MCD_OPC_FilterValue, 11, 247, 33, 0, // Skip to: 18553 /* 9858 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 9861 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9875 /* 9866 */ MCD_OPC_CheckPredicate, 21, 234, 33, 0, // Skip to: 18553 /* 9871 */ MCD_OPC_Decode, 220, 9, 126, // Opcode: VCVTf2sd /* 9875 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9889 /* 9880 */ MCD_OPC_CheckPredicate, 21, 220, 33, 0, // Skip to: 18553 /* 9885 */ MCD_OPC_Decode, 221, 9, 127, // Opcode: VCVTf2sq /* 9889 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9903 /* 9894 */ MCD_OPC_CheckPredicate, 21, 206, 33, 0, // Skip to: 18553 /* 9899 */ MCD_OPC_Decode, 222, 9, 126, // Opcode: VCVTf2ud /* 9903 */ MCD_OPC_FilterValue, 3, 197, 33, 0, // Skip to: 18553 /* 9908 */ MCD_OPC_CheckPredicate, 21, 192, 33, 0, // Skip to: 18553 /* 9913 */ MCD_OPC_Decode, 223, 9, 127, // Opcode: VCVTf2uq /* 9917 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 9955 /* 9922 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 9925 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9940 /* 9930 */ MCD_OPC_CheckPredicate, 21, 170, 33, 0, // Skip to: 18553 /* 9935 */ MCD_OPC_Decode, 239, 20, 135, 1, // Opcode: VTBL1 /* 9940 */ MCD_OPC_FilterValue, 1, 160, 33, 0, // Skip to: 18553 /* 9945 */ MCD_OPC_CheckPredicate, 21, 155, 33, 0, // Skip to: 18553 /* 9950 */ MCD_OPC_Decode, 245, 20, 135, 1, // Opcode: VTBX1 /* 9955 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 9993 /* 9960 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 9963 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9978 /* 9968 */ MCD_OPC_CheckPredicate, 21, 132, 33, 0, // Skip to: 18553 /* 9973 */ MCD_OPC_Decode, 240, 20, 135, 1, // Opcode: VTBL2 /* 9978 */ MCD_OPC_FilterValue, 1, 122, 33, 0, // Skip to: 18553 /* 9983 */ MCD_OPC_CheckPredicate, 21, 117, 33, 0, // Skip to: 18553 /* 9988 */ MCD_OPC_Decode, 246, 20, 135, 1, // Opcode: VTBX2 /* 9993 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 10031 /* 9998 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 10001 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10016 /* 10006 */ MCD_OPC_CheckPredicate, 21, 94, 33, 0, // Skip to: 18553 /* 10011 */ MCD_OPC_Decode, 241, 20, 135, 1, // Opcode: VTBL3 /* 10016 */ MCD_OPC_FilterValue, 1, 84, 33, 0, // Skip to: 18553 /* 10021 */ MCD_OPC_CheckPredicate, 21, 79, 33, 0, // Skip to: 18553 /* 10026 */ MCD_OPC_Decode, 247, 20, 135, 1, // Opcode: VTBX3 /* 10031 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 10069 /* 10036 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 10039 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10054 /* 10044 */ MCD_OPC_CheckPredicate, 21, 56, 33, 0, // Skip to: 18553 /* 10049 */ MCD_OPC_Decode, 243, 20, 135, 1, // Opcode: VTBL4 /* 10054 */ MCD_OPC_FilterValue, 1, 46, 33, 0, // Skip to: 18553 /* 10059 */ MCD_OPC_CheckPredicate, 21, 41, 33, 0, // Skip to: 18553 /* 10064 */ MCD_OPC_Decode, 249, 20, 135, 1, // Opcode: VTBX4 /* 10069 */ MCD_OPC_FilterValue, 12, 31, 33, 0, // Skip to: 18553 /* 10074 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 10077 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 10145 /* 10082 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 10085 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10130 /* 10090 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 10093 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10115 /* 10098 */ MCD_OPC_CheckPredicate, 21, 2, 33, 0, // Skip to: 18553 /* 10103 */ MCD_OPC_CheckField, 18, 1, 1, 251, 32, 0, // Skip to: 18553 /* 10110 */ MCD_OPC_Decode, 136, 10, 136, 1, // Opcode: VDUPLN32d /* 10115 */ MCD_OPC_FilterValue, 1, 241, 32, 0, // Skip to: 18553 /* 10120 */ MCD_OPC_CheckPredicate, 21, 236, 32, 0, // Skip to: 18553 /* 10125 */ MCD_OPC_Decode, 134, 10, 137, 1, // Opcode: VDUPLN16d /* 10130 */ MCD_OPC_FilterValue, 1, 226, 32, 0, // Skip to: 18553 /* 10135 */ MCD_OPC_CheckPredicate, 21, 221, 32, 0, // Skip to: 18553 /* 10140 */ MCD_OPC_Decode, 138, 10, 138, 1, // Opcode: VDUPLN8d /* 10145 */ MCD_OPC_FilterValue, 1, 211, 32, 0, // Skip to: 18553 /* 10150 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... /* 10153 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10198 /* 10158 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... /* 10161 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10183 /* 10166 */ MCD_OPC_CheckPredicate, 21, 190, 32, 0, // Skip to: 18553 /* 10171 */ MCD_OPC_CheckField, 18, 1, 1, 183, 32, 0, // Skip to: 18553 /* 10178 */ MCD_OPC_Decode, 137, 10, 139, 1, // Opcode: VDUPLN32q /* 10183 */ MCD_OPC_FilterValue, 1, 173, 32, 0, // Skip to: 18553 /* 10188 */ MCD_OPC_CheckPredicate, 21, 168, 32, 0, // Skip to: 18553 /* 10193 */ MCD_OPC_Decode, 135, 10, 140, 1, // Opcode: VDUPLN16q /* 10198 */ MCD_OPC_FilterValue, 1, 158, 32, 0, // Skip to: 18553 /* 10203 */ MCD_OPC_CheckPredicate, 21, 153, 32, 0, // Skip to: 18553 /* 10208 */ MCD_OPC_Decode, 139, 10, 141, 1, // Opcode: VDUPLN8q /* 10213 */ MCD_OPC_FilterValue, 1, 143, 32, 0, // Skip to: 18553 /* 10218 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 10221 */ MCD_OPC_FilterValue, 0, 21, 17, 0, // Skip to: 14599 /* 10226 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 10229 */ MCD_OPC_FilterValue, 0, 9, 8, 0, // Skip to: 12291 /* 10234 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 10237 */ MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 10397 /* 10242 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 10245 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10283 /* 10250 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10253 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10268 /* 10259 */ MCD_OPC_CheckPredicate, 21, 97, 32, 0, // Skip to: 18553 /* 10264 */ MCD_OPC_Decode, 180, 15, 97, // Opcode: VQADDsv8i8 /* 10268 */ MCD_OPC_FilterValue, 243, 1, 87, 32, 0, // Skip to: 18553 /* 10274 */ MCD_OPC_CheckPredicate, 21, 82, 32, 0, // Skip to: 18553 /* 10279 */ MCD_OPC_Decode, 188, 15, 97, // Opcode: VQADDuv8i8 /* 10283 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10321 /* 10288 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10291 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10306 /* 10297 */ MCD_OPC_CheckPredicate, 21, 59, 32, 0, // Skip to: 18553 /* 10302 */ MCD_OPC_Decode, 177, 15, 97, // Opcode: VQADDsv4i16 /* 10306 */ MCD_OPC_FilterValue, 243, 1, 49, 32, 0, // Skip to: 18553 /* 10312 */ MCD_OPC_CheckPredicate, 21, 44, 32, 0, // Skip to: 18553 /* 10317 */ MCD_OPC_Decode, 185, 15, 97, // Opcode: VQADDuv4i16 /* 10321 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10359 /* 10326 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10329 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10344 /* 10335 */ MCD_OPC_CheckPredicate, 21, 21, 32, 0, // Skip to: 18553 /* 10340 */ MCD_OPC_Decode, 175, 15, 97, // Opcode: VQADDsv2i32 /* 10344 */ MCD_OPC_FilterValue, 243, 1, 11, 32, 0, // Skip to: 18553 /* 10350 */ MCD_OPC_CheckPredicate, 21, 6, 32, 0, // Skip to: 18553 /* 10355 */ MCD_OPC_Decode, 183, 15, 97, // Opcode: VQADDuv2i32 /* 10359 */ MCD_OPC_FilterValue, 3, 253, 31, 0, // Skip to: 18553 /* 10364 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10367 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10382 /* 10373 */ MCD_OPC_CheckPredicate, 21, 239, 31, 0, // Skip to: 18553 /* 10378 */ MCD_OPC_Decode, 174, 15, 97, // Opcode: VQADDsv1i64 /* 10382 */ MCD_OPC_FilterValue, 243, 1, 229, 31, 0, // Skip to: 18553 /* 10388 */ MCD_OPC_CheckPredicate, 21, 224, 31, 0, // Skip to: 18553 /* 10393 */ MCD_OPC_Decode, 182, 15, 97, // Opcode: VQADDuv1i64 /* 10397 */ MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 10557 /* 10402 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 10405 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10443 /* 10410 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10413 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10428 /* 10419 */ MCD_OPC_CheckPredicate, 21, 193, 31, 0, // Skip to: 18553 /* 10424 */ MCD_OPC_Decode, 137, 8, 97, // Opcode: VANDd /* 10428 */ MCD_OPC_FilterValue, 243, 1, 183, 31, 0, // Skip to: 18553 /* 10434 */ MCD_OPC_CheckPredicate, 21, 178, 31, 0, // Skip to: 18553 /* 10439 */ MCD_OPC_Decode, 140, 10, 97, // Opcode: VEORd /* 10443 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10481 /* 10448 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10451 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10466 /* 10457 */ MCD_OPC_CheckPredicate, 21, 155, 31, 0, // Skip to: 18553 /* 10462 */ MCD_OPC_Decode, 139, 8, 97, // Opcode: VBICd /* 10466 */ MCD_OPC_FilterValue, 243, 1, 145, 31, 0, // Skip to: 18553 /* 10472 */ MCD_OPC_CheckPredicate, 21, 140, 31, 0, // Skip to: 18553 /* 10477 */ MCD_OPC_Decode, 149, 8, 105, // Opcode: VBSLd /* 10481 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10519 /* 10486 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10489 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10504 /* 10495 */ MCD_OPC_CheckPredicate, 21, 117, 31, 0, // Skip to: 18553 /* 10500 */ MCD_OPC_Decode, 244, 14, 97, // Opcode: VORRd /* 10504 */ MCD_OPC_FilterValue, 243, 1, 107, 31, 0, // Skip to: 18553 /* 10510 */ MCD_OPC_CheckPredicate, 21, 102, 31, 0, // Skip to: 18553 /* 10515 */ MCD_OPC_Decode, 147, 8, 105, // Opcode: VBITd /* 10519 */ MCD_OPC_FilterValue, 3, 93, 31, 0, // Skip to: 18553 /* 10524 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10527 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10542 /* 10533 */ MCD_OPC_CheckPredicate, 21, 79, 31, 0, // Skip to: 18553 /* 10538 */ MCD_OPC_Decode, 242, 14, 97, // Opcode: VORNd /* 10542 */ MCD_OPC_FilterValue, 243, 1, 69, 31, 0, // Skip to: 18553 /* 10548 */ MCD_OPC_CheckPredicate, 21, 64, 31, 0, // Skip to: 18553 /* 10553 */ MCD_OPC_Decode, 145, 8, 105, // Opcode: VBIFd /* 10557 */ MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 10717 /* 10562 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 10565 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10603 /* 10570 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10573 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10588 /* 10579 */ MCD_OPC_CheckPredicate, 21, 33, 31, 0, // Skip to: 18553 /* 10584 */ MCD_OPC_Decode, 201, 16, 97, // Opcode: VQSUBsv8i8 /* 10588 */ MCD_OPC_FilterValue, 243, 1, 23, 31, 0, // Skip to: 18553 /* 10594 */ MCD_OPC_CheckPredicate, 21, 18, 31, 0, // Skip to: 18553 /* 10599 */ MCD_OPC_Decode, 209, 16, 97, // Opcode: VQSUBuv8i8 /* 10603 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10641 /* 10608 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10611 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10626 /* 10617 */ MCD_OPC_CheckPredicate, 21, 251, 30, 0, // Skip to: 18553 /* 10622 */ MCD_OPC_Decode, 198, 16, 97, // Opcode: VQSUBsv4i16 /* 10626 */ MCD_OPC_FilterValue, 243, 1, 241, 30, 0, // Skip to: 18553 /* 10632 */ MCD_OPC_CheckPredicate, 21, 236, 30, 0, // Skip to: 18553 /* 10637 */ MCD_OPC_Decode, 206, 16, 97, // Opcode: VQSUBuv4i16 /* 10641 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10679 /* 10646 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10649 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10664 /* 10655 */ MCD_OPC_CheckPredicate, 21, 213, 30, 0, // Skip to: 18553 /* 10660 */ MCD_OPC_Decode, 196, 16, 97, // Opcode: VQSUBsv2i32 /* 10664 */ MCD_OPC_FilterValue, 243, 1, 203, 30, 0, // Skip to: 18553 /* 10670 */ MCD_OPC_CheckPredicate, 21, 198, 30, 0, // Skip to: 18553 /* 10675 */ MCD_OPC_Decode, 204, 16, 97, // Opcode: VQSUBuv2i32 /* 10679 */ MCD_OPC_FilterValue, 3, 189, 30, 0, // Skip to: 18553 /* 10684 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10687 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10702 /* 10693 */ MCD_OPC_CheckPredicate, 21, 175, 30, 0, // Skip to: 18553 /* 10698 */ MCD_OPC_Decode, 195, 16, 97, // Opcode: VQSUBsv1i64 /* 10702 */ MCD_OPC_FilterValue, 243, 1, 165, 30, 0, // Skip to: 18553 /* 10708 */ MCD_OPC_CheckPredicate, 21, 160, 30, 0, // Skip to: 18553 /* 10713 */ MCD_OPC_Decode, 203, 16, 97, // Opcode: VQSUBuv1i64 /* 10717 */ MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 10839 /* 10722 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 10725 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10763 /* 10730 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10733 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10748 /* 10739 */ MCD_OPC_CheckPredicate, 21, 129, 30, 0, // Skip to: 18553 /* 10744 */ MCD_OPC_Decode, 184, 8, 97, // Opcode: VCGEsv8i8 /* 10748 */ MCD_OPC_FilterValue, 243, 1, 119, 30, 0, // Skip to: 18553 /* 10754 */ MCD_OPC_CheckPredicate, 21, 114, 30, 0, // Skip to: 18553 /* 10759 */ MCD_OPC_Decode, 190, 8, 97, // Opcode: VCGEuv8i8 /* 10763 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10801 /* 10768 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10771 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10786 /* 10777 */ MCD_OPC_CheckPredicate, 21, 91, 30, 0, // Skip to: 18553 /* 10782 */ MCD_OPC_Decode, 181, 8, 97, // Opcode: VCGEsv4i16 /* 10786 */ MCD_OPC_FilterValue, 243, 1, 81, 30, 0, // Skip to: 18553 /* 10792 */ MCD_OPC_CheckPredicate, 21, 76, 30, 0, // Skip to: 18553 /* 10797 */ MCD_OPC_Decode, 187, 8, 97, // Opcode: VCGEuv4i16 /* 10801 */ MCD_OPC_FilterValue, 2, 67, 30, 0, // Skip to: 18553 /* 10806 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10809 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10824 /* 10815 */ MCD_OPC_CheckPredicate, 21, 53, 30, 0, // Skip to: 18553 /* 10820 */ MCD_OPC_Decode, 180, 8, 97, // Opcode: VCGEsv2i32 /* 10824 */ MCD_OPC_FilterValue, 243, 1, 43, 30, 0, // Skip to: 18553 /* 10830 */ MCD_OPC_CheckPredicate, 21, 38, 30, 0, // Skip to: 18553 /* 10835 */ MCD_OPC_Decode, 186, 8, 97, // Opcode: VCGEuv2i32 /* 10839 */ MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 10999 /* 10844 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 10847 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10885 /* 10852 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10855 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10870 /* 10861 */ MCD_OPC_CheckPredicate, 21, 7, 30, 0, // Skip to: 18553 /* 10866 */ MCD_OPC_Decode, 168, 16, 101, // Opcode: VQSHLsv8i8 /* 10870 */ MCD_OPC_FilterValue, 243, 1, 253, 29, 0, // Skip to: 18553 /* 10876 */ MCD_OPC_CheckPredicate, 21, 248, 29, 0, // Skip to: 18553 /* 10881 */ MCD_OPC_Decode, 184, 16, 101, // Opcode: VQSHLuv8i8 /* 10885 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10923 /* 10890 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10893 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10908 /* 10899 */ MCD_OPC_CheckPredicate, 21, 225, 29, 0, // Skip to: 18553 /* 10904 */ MCD_OPC_Decode, 165, 16, 101, // Opcode: VQSHLsv4i16 /* 10908 */ MCD_OPC_FilterValue, 243, 1, 215, 29, 0, // Skip to: 18553 /* 10914 */ MCD_OPC_CheckPredicate, 21, 210, 29, 0, // Skip to: 18553 /* 10919 */ MCD_OPC_Decode, 181, 16, 101, // Opcode: VQSHLuv4i16 /* 10923 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10961 /* 10928 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10931 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10946 /* 10937 */ MCD_OPC_CheckPredicate, 21, 187, 29, 0, // Skip to: 18553 /* 10942 */ MCD_OPC_Decode, 163, 16, 101, // Opcode: VQSHLsv2i32 /* 10946 */ MCD_OPC_FilterValue, 243, 1, 177, 29, 0, // Skip to: 18553 /* 10952 */ MCD_OPC_CheckPredicate, 21, 172, 29, 0, // Skip to: 18553 /* 10957 */ MCD_OPC_Decode, 179, 16, 101, // Opcode: VQSHLuv2i32 /* 10961 */ MCD_OPC_FilterValue, 3, 163, 29, 0, // Skip to: 18553 /* 10966 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 10969 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10984 /* 10975 */ MCD_OPC_CheckPredicate, 21, 149, 29, 0, // Skip to: 18553 /* 10980 */ MCD_OPC_Decode, 162, 16, 101, // Opcode: VQSHLsv1i64 /* 10984 */ MCD_OPC_FilterValue, 243, 1, 139, 29, 0, // Skip to: 18553 /* 10990 */ MCD_OPC_CheckPredicate, 21, 134, 29, 0, // Skip to: 18553 /* 10995 */ MCD_OPC_Decode, 178, 16, 101, // Opcode: VQSHLuv1i64 /* 10999 */ MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 11159 /* 11004 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11007 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11045 /* 11012 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11015 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11030 /* 11021 */ MCD_OPC_CheckPredicate, 21, 103, 29, 0, // Skip to: 18553 /* 11026 */ MCD_OPC_Decode, 255, 15, 101, // Opcode: VQRSHLsv8i8 /* 11030 */ MCD_OPC_FilterValue, 243, 1, 93, 29, 0, // Skip to: 18553 /* 11036 */ MCD_OPC_CheckPredicate, 21, 88, 29, 0, // Skip to: 18553 /* 11041 */ MCD_OPC_Decode, 135, 16, 101, // Opcode: VQRSHLuv8i8 /* 11045 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11083 /* 11050 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11053 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11068 /* 11059 */ MCD_OPC_CheckPredicate, 21, 65, 29, 0, // Skip to: 18553 /* 11064 */ MCD_OPC_Decode, 252, 15, 101, // Opcode: VQRSHLsv4i16 /* 11068 */ MCD_OPC_FilterValue, 243, 1, 55, 29, 0, // Skip to: 18553 /* 11074 */ MCD_OPC_CheckPredicate, 21, 50, 29, 0, // Skip to: 18553 /* 11079 */ MCD_OPC_Decode, 132, 16, 101, // Opcode: VQRSHLuv4i16 /* 11083 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11121 /* 11088 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11091 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11106 /* 11097 */ MCD_OPC_CheckPredicate, 21, 27, 29, 0, // Skip to: 18553 /* 11102 */ MCD_OPC_Decode, 250, 15, 101, // Opcode: VQRSHLsv2i32 /* 11106 */ MCD_OPC_FilterValue, 243, 1, 17, 29, 0, // Skip to: 18553 /* 11112 */ MCD_OPC_CheckPredicate, 21, 12, 29, 0, // Skip to: 18553 /* 11117 */ MCD_OPC_Decode, 130, 16, 101, // Opcode: VQRSHLuv2i32 /* 11121 */ MCD_OPC_FilterValue, 3, 3, 29, 0, // Skip to: 18553 /* 11126 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11129 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11144 /* 11135 */ MCD_OPC_CheckPredicate, 21, 245, 28, 0, // Skip to: 18553 /* 11140 */ MCD_OPC_Decode, 249, 15, 101, // Opcode: VQRSHLsv1i64 /* 11144 */ MCD_OPC_FilterValue, 243, 1, 235, 28, 0, // Skip to: 18553 /* 11150 */ MCD_OPC_CheckPredicate, 21, 230, 28, 0, // Skip to: 18553 /* 11155 */ MCD_OPC_Decode, 129, 16, 101, // Opcode: VQRSHLuv1i64 /* 11159 */ MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 11281 /* 11164 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11167 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11205 /* 11172 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11175 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11190 /* 11181 */ MCD_OPC_CheckPredicate, 21, 199, 28, 0, // Skip to: 18553 /* 11186 */ MCD_OPC_Decode, 195, 13, 97, // Opcode: VMINsv8i8 /* 11190 */ MCD_OPC_FilterValue, 243, 1, 189, 28, 0, // Skip to: 18553 /* 11196 */ MCD_OPC_CheckPredicate, 21, 184, 28, 0, // Skip to: 18553 /* 11201 */ MCD_OPC_Decode, 201, 13, 97, // Opcode: VMINuv8i8 /* 11205 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11243 /* 11210 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11213 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11228 /* 11219 */ MCD_OPC_CheckPredicate, 21, 161, 28, 0, // Skip to: 18553 /* 11224 */ MCD_OPC_Decode, 192, 13, 97, // Opcode: VMINsv4i16 /* 11228 */ MCD_OPC_FilterValue, 243, 1, 151, 28, 0, // Skip to: 18553 /* 11234 */ MCD_OPC_CheckPredicate, 21, 146, 28, 0, // Skip to: 18553 /* 11239 */ MCD_OPC_Decode, 198, 13, 97, // Opcode: VMINuv4i16 /* 11243 */ MCD_OPC_FilterValue, 2, 137, 28, 0, // Skip to: 18553 /* 11248 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11251 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11266 /* 11257 */ MCD_OPC_CheckPredicate, 21, 123, 28, 0, // Skip to: 18553 /* 11262 */ MCD_OPC_Decode, 191, 13, 97, // Opcode: VMINsv2i32 /* 11266 */ MCD_OPC_FilterValue, 243, 1, 113, 28, 0, // Skip to: 18553 /* 11272 */ MCD_OPC_CheckPredicate, 21, 108, 28, 0, // Skip to: 18553 /* 11277 */ MCD_OPC_Decode, 197, 13, 97, // Opcode: VMINuv2i32 /* 11281 */ MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 11403 /* 11286 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11289 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11327 /* 11294 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11297 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11312 /* 11303 */ MCD_OPC_CheckPredicate, 21, 77, 28, 0, // Skip to: 18553 /* 11308 */ MCD_OPC_Decode, 185, 7, 105, // Opcode: VABAsv8i8 /* 11312 */ MCD_OPC_FilterValue, 243, 1, 67, 28, 0, // Skip to: 18553 /* 11318 */ MCD_OPC_CheckPredicate, 21, 62, 28, 0, // Skip to: 18553 /* 11323 */ MCD_OPC_Decode, 191, 7, 105, // Opcode: VABAuv8i8 /* 11327 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11365 /* 11332 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11335 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11350 /* 11341 */ MCD_OPC_CheckPredicate, 21, 39, 28, 0, // Skip to: 18553 /* 11346 */ MCD_OPC_Decode, 182, 7, 105, // Opcode: VABAsv4i16 /* 11350 */ MCD_OPC_FilterValue, 243, 1, 29, 28, 0, // Skip to: 18553 /* 11356 */ MCD_OPC_CheckPredicate, 21, 24, 28, 0, // Skip to: 18553 /* 11361 */ MCD_OPC_Decode, 188, 7, 105, // Opcode: VABAuv4i16 /* 11365 */ MCD_OPC_FilterValue, 2, 15, 28, 0, // Skip to: 18553 /* 11370 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11373 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11388 /* 11379 */ MCD_OPC_CheckPredicate, 21, 1, 28, 0, // Skip to: 18553 /* 11384 */ MCD_OPC_Decode, 181, 7, 105, // Opcode: VABAsv2i32 /* 11388 */ MCD_OPC_FilterValue, 243, 1, 247, 27, 0, // Skip to: 18553 /* 11394 */ MCD_OPC_CheckPredicate, 21, 242, 27, 0, // Skip to: 18553 /* 11399 */ MCD_OPC_Decode, 187, 7, 105, // Opcode: VABAuv2i32 /* 11403 */ MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 11525 /* 11408 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11411 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11449 /* 11416 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11419 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11434 /* 11425 */ MCD_OPC_CheckPredicate, 21, 211, 27, 0, // Skip to: 18553 /* 11430 */ MCD_OPC_Decode, 158, 21, 97, // Opcode: VTSTv8i8 /* 11434 */ MCD_OPC_FilterValue, 243, 1, 201, 27, 0, // Skip to: 18553 /* 11440 */ MCD_OPC_CheckPredicate, 21, 196, 27, 0, // Skip to: 18553 /* 11445 */ MCD_OPC_Decode, 164, 8, 97, // Opcode: VCEQv8i8 /* 11449 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11487 /* 11454 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11457 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11472 /* 11463 */ MCD_OPC_CheckPredicate, 21, 173, 27, 0, // Skip to: 18553 /* 11468 */ MCD_OPC_Decode, 155, 21, 97, // Opcode: VTSTv4i16 /* 11472 */ MCD_OPC_FilterValue, 243, 1, 163, 27, 0, // Skip to: 18553 /* 11478 */ MCD_OPC_CheckPredicate, 21, 158, 27, 0, // Skip to: 18553 /* 11483 */ MCD_OPC_Decode, 161, 8, 97, // Opcode: VCEQv4i16 /* 11487 */ MCD_OPC_FilterValue, 2, 149, 27, 0, // Skip to: 18553 /* 11492 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11495 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11510 /* 11501 */ MCD_OPC_CheckPredicate, 21, 135, 27, 0, // Skip to: 18553 /* 11506 */ MCD_OPC_Decode, 154, 21, 97, // Opcode: VTSTv2i32 /* 11510 */ MCD_OPC_FilterValue, 243, 1, 125, 27, 0, // Skip to: 18553 /* 11516 */ MCD_OPC_CheckPredicate, 21, 120, 27, 0, // Skip to: 18553 /* 11521 */ MCD_OPC_Decode, 160, 8, 97, // Opcode: VCEQv2i32 /* 11525 */ MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 11615 /* 11530 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11533 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11571 /* 11538 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11541 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11556 /* 11547 */ MCD_OPC_CheckPredicate, 21, 89, 27, 0, // Skip to: 18553 /* 11552 */ MCD_OPC_Decode, 213, 14, 97, // Opcode: VMULv8i8 /* 11556 */ MCD_OPC_FilterValue, 243, 1, 79, 27, 0, // Skip to: 18553 /* 11562 */ MCD_OPC_CheckPredicate, 21, 74, 27, 0, // Skip to: 18553 /* 11567 */ MCD_OPC_Decode, 198, 14, 97, // Opcode: VMULpd /* 11571 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 11593 /* 11576 */ MCD_OPC_CheckPredicate, 21, 60, 27, 0, // Skip to: 18553 /* 11581 */ MCD_OPC_CheckField, 24, 8, 242, 1, 52, 27, 0, // Skip to: 18553 /* 11589 */ MCD_OPC_Decode, 210, 14, 97, // Opcode: VMULv4i16 /* 11593 */ MCD_OPC_FilterValue, 2, 43, 27, 0, // Skip to: 18553 /* 11598 */ MCD_OPC_CheckPredicate, 21, 38, 27, 0, // Skip to: 18553 /* 11603 */ MCD_OPC_CheckField, 24, 8, 242, 1, 30, 27, 0, // Skip to: 18553 /* 11611 */ MCD_OPC_Decode, 209, 14, 97, // Opcode: VMULv2i32 /* 11615 */ MCD_OPC_FilterValue, 10, 117, 0, 0, // Skip to: 11737 /* 11620 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11623 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11661 /* 11628 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11631 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11646 /* 11637 */ MCD_OPC_CheckPredicate, 21, 255, 26, 0, // Skip to: 18553 /* 11642 */ MCD_OPC_Decode, 163, 15, 97, // Opcode: VPMINs8 /* 11646 */ MCD_OPC_FilterValue, 243, 1, 245, 26, 0, // Skip to: 18553 /* 11652 */ MCD_OPC_CheckPredicate, 21, 240, 26, 0, // Skip to: 18553 /* 11657 */ MCD_OPC_Decode, 166, 15, 97, // Opcode: VPMINu8 /* 11661 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11699 /* 11666 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11669 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11684 /* 11675 */ MCD_OPC_CheckPredicate, 21, 217, 26, 0, // Skip to: 18553 /* 11680 */ MCD_OPC_Decode, 161, 15, 97, // Opcode: VPMINs16 /* 11684 */ MCD_OPC_FilterValue, 243, 1, 207, 26, 0, // Skip to: 18553 /* 11690 */ MCD_OPC_CheckPredicate, 21, 202, 26, 0, // Skip to: 18553 /* 11695 */ MCD_OPC_Decode, 164, 15, 97, // Opcode: VPMINu16 /* 11699 */ MCD_OPC_FilterValue, 2, 193, 26, 0, // Skip to: 18553 /* 11704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11707 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11722 /* 11713 */ MCD_OPC_CheckPredicate, 21, 179, 26, 0, // Skip to: 18553 /* 11718 */ MCD_OPC_Decode, 162, 15, 97, // Opcode: VPMINs32 /* 11722 */ MCD_OPC_FilterValue, 243, 1, 169, 26, 0, // Skip to: 18553 /* 11728 */ MCD_OPC_CheckPredicate, 21, 164, 26, 0, // Skip to: 18553 /* 11733 */ MCD_OPC_Decode, 165, 15, 97, // Opcode: VPMINu32 /* 11737 */ MCD_OPC_FilterValue, 11, 101, 0, 0, // Skip to: 11843 /* 11742 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11745 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11767 /* 11750 */ MCD_OPC_CheckPredicate, 21, 142, 26, 0, // Skip to: 18553 /* 11755 */ MCD_OPC_CheckField, 24, 8, 242, 1, 134, 26, 0, // Skip to: 18553 /* 11763 */ MCD_OPC_Decode, 150, 15, 97, // Opcode: VPADDi8 /* 11767 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11805 /* 11772 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11775 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11790 /* 11781 */ MCD_OPC_CheckPredicate, 21, 111, 26, 0, // Skip to: 18553 /* 11786 */ MCD_OPC_Decode, 148, 15, 97, // Opcode: VPADDi16 /* 11790 */ MCD_OPC_FilterValue, 243, 1, 101, 26, 0, // Skip to: 18553 /* 11796 */ MCD_OPC_CheckPredicate, 23, 96, 26, 0, // Skip to: 18553 /* 11801 */ MCD_OPC_Decode, 229, 15, 105, // Opcode: VQRDMLAHv4i16 /* 11805 */ MCD_OPC_FilterValue, 2, 87, 26, 0, // Skip to: 18553 /* 11810 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11813 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11828 /* 11819 */ MCD_OPC_CheckPredicate, 21, 73, 26, 0, // Skip to: 18553 /* 11824 */ MCD_OPC_Decode, 149, 15, 97, // Opcode: VPADDi32 /* 11828 */ MCD_OPC_FilterValue, 243, 1, 63, 26, 0, // Skip to: 18553 /* 11834 */ MCD_OPC_CheckPredicate, 23, 58, 26, 0, // Skip to: 18553 /* 11839 */ MCD_OPC_Decode, 228, 15, 105, // Opcode: VQRDMLAHv2i32 /* 11843 */ MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 11971 /* 11848 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11851 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11873 /* 11856 */ MCD_OPC_CheckPredicate, 26, 36, 26, 0, // Skip to: 18553 /* 11861 */ MCD_OPC_CheckField, 24, 8, 242, 1, 28, 26, 0, // Skip to: 18553 /* 11869 */ MCD_OPC_Decode, 152, 10, 105, // Opcode: VFMAfd /* 11873 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11911 /* 11878 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11881 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11896 /* 11887 */ MCD_OPC_CheckPredicate, 22, 5, 26, 0, // Skip to: 18553 /* 11892 */ MCD_OPC_Decode, 154, 10, 105, // Opcode: VFMAhd /* 11896 */ MCD_OPC_FilterValue, 243, 1, 251, 25, 0, // Skip to: 18553 /* 11902 */ MCD_OPC_CheckPredicate, 23, 246, 25, 0, // Skip to: 18553 /* 11907 */ MCD_OPC_Decode, 237, 15, 105, // Opcode: VQRDMLSHv4i16 /* 11911 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11949 /* 11916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11919 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11934 /* 11925 */ MCD_OPC_CheckPredicate, 26, 223, 25, 0, // Skip to: 18553 /* 11930 */ MCD_OPC_Decode, 159, 10, 105, // Opcode: VFMSfd /* 11934 */ MCD_OPC_FilterValue, 243, 1, 213, 25, 0, // Skip to: 18553 /* 11940 */ MCD_OPC_CheckPredicate, 23, 208, 25, 0, // Skip to: 18553 /* 11945 */ MCD_OPC_Decode, 236, 15, 105, // Opcode: VQRDMLSHv2i32 /* 11949 */ MCD_OPC_FilterValue, 3, 199, 25, 0, // Skip to: 18553 /* 11954 */ MCD_OPC_CheckPredicate, 22, 194, 25, 0, // Skip to: 18553 /* 11959 */ MCD_OPC_CheckField, 24, 8, 242, 1, 186, 25, 0, // Skip to: 18553 /* 11967 */ MCD_OPC_Decode, 161, 10, 105, // Opcode: VFMShd /* 11971 */ MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 12099 /* 11976 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11979 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12017 /* 11984 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 11987 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12002 /* 11993 */ MCD_OPC_CheckPredicate, 21, 155, 25, 0, // Skip to: 18553 /* 11998 */ MCD_OPC_Decode, 215, 13, 105, // Opcode: VMLAfd /* 12002 */ MCD_OPC_FilterValue, 243, 1, 145, 25, 0, // Skip to: 18553 /* 12008 */ MCD_OPC_CheckPredicate, 21, 140, 25, 0, // Skip to: 18553 /* 12013 */ MCD_OPC_Decode, 194, 14, 97, // Opcode: VMULfd /* 12017 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 12055 /* 12022 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 12025 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12040 /* 12031 */ MCD_OPC_CheckPredicate, 22, 117, 25, 0, // Skip to: 18553 /* 12036 */ MCD_OPC_Decode, 217, 13, 105, // Opcode: VMLAhd /* 12040 */ MCD_OPC_FilterValue, 243, 1, 107, 25, 0, // Skip to: 18553 /* 12046 */ MCD_OPC_CheckPredicate, 22, 102, 25, 0, // Skip to: 18553 /* 12051 */ MCD_OPC_Decode, 196, 14, 97, // Opcode: VMULhd /* 12055 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12077 /* 12060 */ MCD_OPC_CheckPredicate, 21, 88, 25, 0, // Skip to: 18553 /* 12065 */ MCD_OPC_CheckField, 24, 8, 242, 1, 80, 25, 0, // Skip to: 18553 /* 12073 */ MCD_OPC_Decode, 246, 13, 105, // Opcode: VMLSfd /* 12077 */ MCD_OPC_FilterValue, 3, 71, 25, 0, // Skip to: 18553 /* 12082 */ MCD_OPC_CheckPredicate, 22, 66, 25, 0, // Skip to: 18553 /* 12087 */ MCD_OPC_CheckField, 24, 8, 242, 1, 58, 25, 0, // Skip to: 18553 /* 12095 */ MCD_OPC_Decode, 248, 13, 105, // Opcode: VMLShd /* 12099 */ MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 12195 /* 12104 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 12107 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12129 /* 12112 */ MCD_OPC_CheckPredicate, 21, 36, 25, 0, // Skip to: 18553 /* 12117 */ MCD_OPC_CheckField, 24, 8, 243, 1, 28, 25, 0, // Skip to: 18553 /* 12125 */ MCD_OPC_Decode, 227, 7, 97, // Opcode: VACGEfd /* 12129 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12151 /* 12134 */ MCD_OPC_CheckPredicate, 22, 14, 25, 0, // Skip to: 18553 /* 12139 */ MCD_OPC_CheckField, 24, 8, 243, 1, 6, 25, 0, // Skip to: 18553 /* 12147 */ MCD_OPC_Decode, 229, 7, 97, // Opcode: VACGEhd /* 12151 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12173 /* 12156 */ MCD_OPC_CheckPredicate, 21, 248, 24, 0, // Skip to: 18553 /* 12161 */ MCD_OPC_CheckField, 24, 8, 243, 1, 240, 24, 0, // Skip to: 18553 /* 12169 */ MCD_OPC_Decode, 231, 7, 97, // Opcode: VACGTfd /* 12173 */ MCD_OPC_FilterValue, 3, 231, 24, 0, // Skip to: 18553 /* 12178 */ MCD_OPC_CheckPredicate, 22, 226, 24, 0, // Skip to: 18553 /* 12183 */ MCD_OPC_CheckField, 24, 8, 243, 1, 218, 24, 0, // Skip to: 18553 /* 12191 */ MCD_OPC_Decode, 233, 7, 97, // Opcode: VACGThd /* 12195 */ MCD_OPC_FilterValue, 15, 209, 24, 0, // Skip to: 18553 /* 12200 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 12203 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12225 /* 12208 */ MCD_OPC_CheckPredicate, 21, 196, 24, 0, // Skip to: 18553 /* 12213 */ MCD_OPC_CheckField, 24, 8, 242, 1, 188, 24, 0, // Skip to: 18553 /* 12221 */ MCD_OPC_Decode, 219, 16, 97, // Opcode: VRECPSfd /* 12225 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12247 /* 12230 */ MCD_OPC_CheckPredicate, 22, 174, 24, 0, // Skip to: 18553 /* 12235 */ MCD_OPC_CheckField, 24, 8, 242, 1, 166, 24, 0, // Skip to: 18553 /* 12243 */ MCD_OPC_Decode, 221, 16, 97, // Opcode: VRECPShd /* 12247 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12269 /* 12252 */ MCD_OPC_CheckPredicate, 21, 152, 24, 0, // Skip to: 18553 /* 12257 */ MCD_OPC_CheckField, 24, 8, 242, 1, 144, 24, 0, // Skip to: 18553 /* 12265 */ MCD_OPC_Decode, 205, 17, 97, // Opcode: VRSQRTSfd /* 12269 */ MCD_OPC_FilterValue, 3, 135, 24, 0, // Skip to: 18553 /* 12274 */ MCD_OPC_CheckPredicate, 22, 130, 24, 0, // Skip to: 18553 /* 12279 */ MCD_OPC_CheckField, 24, 8, 242, 1, 122, 24, 0, // Skip to: 18553 /* 12287 */ MCD_OPC_Decode, 207, 17, 97, // Opcode: VRSQRTShd /* 12291 */ MCD_OPC_FilterValue, 1, 113, 24, 0, // Skip to: 18553 /* 12296 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 12299 */ MCD_OPC_FilterValue, 0, 209, 7, 0, // Skip to: 14305 /* 12304 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 12307 */ MCD_OPC_FilterValue, 121, 97, 24, 0, // Skip to: 18553 /* 12312 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 12315 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 12459 /* 12320 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 12323 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12421 /* 12328 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12331 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12383 /* 12336 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12339 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12361 /* 12344 */ MCD_OPC_CheckPredicate, 21, 231, 6, 0, // Skip to: 14116 /* 12349 */ MCD_OPC_CheckField, 19, 1, 1, 224, 6, 0, // Skip to: 14116 /* 12356 */ MCD_OPC_Decode, 162, 18, 142, 1, // Opcode: VSHRsv8i8 /* 12361 */ MCD_OPC_FilterValue, 1, 214, 6, 0, // Skip to: 14116 /* 12366 */ MCD_OPC_CheckPredicate, 21, 209, 6, 0, // Skip to: 14116 /* 12371 */ MCD_OPC_CheckField, 19, 1, 1, 202, 6, 0, // Skip to: 14116 /* 12378 */ MCD_OPC_Decode, 170, 18, 142, 1, // Opcode: VSHRuv8i8 /* 12383 */ MCD_OPC_FilterValue, 1, 192, 6, 0, // Skip to: 14116 /* 12388 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12391 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12406 /* 12396 */ MCD_OPC_CheckPredicate, 21, 179, 6, 0, // Skip to: 14116 /* 12401 */ MCD_OPC_Decode, 159, 18, 143, 1, // Opcode: VSHRsv4i16 /* 12406 */ MCD_OPC_FilterValue, 1, 169, 6, 0, // Skip to: 14116 /* 12411 */ MCD_OPC_CheckPredicate, 21, 164, 6, 0, // Skip to: 14116 /* 12416 */ MCD_OPC_Decode, 167, 18, 143, 1, // Opcode: VSHRuv4i16 /* 12421 */ MCD_OPC_FilterValue, 1, 154, 6, 0, // Skip to: 14116 /* 12426 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12429 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12444 /* 12434 */ MCD_OPC_CheckPredicate, 21, 141, 6, 0, // Skip to: 14116 /* 12439 */ MCD_OPC_Decode, 157, 18, 144, 1, // Opcode: VSHRsv2i32 /* 12444 */ MCD_OPC_FilterValue, 1, 131, 6, 0, // Skip to: 14116 /* 12449 */ MCD_OPC_CheckPredicate, 21, 126, 6, 0, // Skip to: 14116 /* 12454 */ MCD_OPC_Decode, 165, 18, 144, 1, // Opcode: VSHRuv2i32 /* 12459 */ MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 12603 /* 12464 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 12467 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12565 /* 12472 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12475 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12527 /* 12480 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12483 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12505 /* 12488 */ MCD_OPC_CheckPredicate, 21, 87, 6, 0, // Skip to: 14116 /* 12493 */ MCD_OPC_CheckField, 19, 1, 1, 80, 6, 0, // Skip to: 14116 /* 12500 */ MCD_OPC_Decode, 198, 18, 145, 1, // Opcode: VSRAsv8i8 /* 12505 */ MCD_OPC_FilterValue, 1, 70, 6, 0, // Skip to: 14116 /* 12510 */ MCD_OPC_CheckPredicate, 21, 65, 6, 0, // Skip to: 14116 /* 12515 */ MCD_OPC_CheckField, 19, 1, 1, 58, 6, 0, // Skip to: 14116 /* 12522 */ MCD_OPC_Decode, 206, 18, 145, 1, // Opcode: VSRAuv8i8 /* 12527 */ MCD_OPC_FilterValue, 1, 48, 6, 0, // Skip to: 14116 /* 12532 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12535 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550 /* 12540 */ MCD_OPC_CheckPredicate, 21, 35, 6, 0, // Skip to: 14116 /* 12545 */ MCD_OPC_Decode, 195, 18, 146, 1, // Opcode: VSRAsv4i16 /* 12550 */ MCD_OPC_FilterValue, 1, 25, 6, 0, // Skip to: 14116 /* 12555 */ MCD_OPC_CheckPredicate, 21, 20, 6, 0, // Skip to: 14116 /* 12560 */ MCD_OPC_Decode, 203, 18, 146, 1, // Opcode: VSRAuv4i16 /* 12565 */ MCD_OPC_FilterValue, 1, 10, 6, 0, // Skip to: 14116 /* 12570 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12573 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12588 /* 12578 */ MCD_OPC_CheckPredicate, 21, 253, 5, 0, // Skip to: 14116 /* 12583 */ MCD_OPC_Decode, 193, 18, 147, 1, // Opcode: VSRAsv2i32 /* 12588 */ MCD_OPC_FilterValue, 1, 243, 5, 0, // Skip to: 14116 /* 12593 */ MCD_OPC_CheckPredicate, 21, 238, 5, 0, // Skip to: 14116 /* 12598 */ MCD_OPC_Decode, 201, 18, 147, 1, // Opcode: VSRAuv2i32 /* 12603 */ MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 12747 /* 12608 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 12611 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12709 /* 12616 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12619 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12671 /* 12624 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12627 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12649 /* 12632 */ MCD_OPC_CheckPredicate, 21, 199, 5, 0, // Skip to: 14116 /* 12637 */ MCD_OPC_CheckField, 19, 1, 1, 192, 5, 0, // Skip to: 14116 /* 12644 */ MCD_OPC_Decode, 190, 17, 142, 1, // Opcode: VRSHRsv8i8 /* 12649 */ MCD_OPC_FilterValue, 1, 182, 5, 0, // Skip to: 14116 /* 12654 */ MCD_OPC_CheckPredicate, 21, 177, 5, 0, // Skip to: 14116 /* 12659 */ MCD_OPC_CheckField, 19, 1, 1, 170, 5, 0, // Skip to: 14116 /* 12666 */ MCD_OPC_Decode, 198, 17, 142, 1, // Opcode: VRSHRuv8i8 /* 12671 */ MCD_OPC_FilterValue, 1, 160, 5, 0, // Skip to: 14116 /* 12676 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12679 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12694 /* 12684 */ MCD_OPC_CheckPredicate, 21, 147, 5, 0, // Skip to: 14116 /* 12689 */ MCD_OPC_Decode, 187, 17, 143, 1, // Opcode: VRSHRsv4i16 /* 12694 */ MCD_OPC_FilterValue, 1, 137, 5, 0, // Skip to: 14116 /* 12699 */ MCD_OPC_CheckPredicate, 21, 132, 5, 0, // Skip to: 14116 /* 12704 */ MCD_OPC_Decode, 195, 17, 143, 1, // Opcode: VRSHRuv4i16 /* 12709 */ MCD_OPC_FilterValue, 1, 122, 5, 0, // Skip to: 14116 /* 12714 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12717 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12732 /* 12722 */ MCD_OPC_CheckPredicate, 21, 109, 5, 0, // Skip to: 14116 /* 12727 */ MCD_OPC_Decode, 185, 17, 144, 1, // Opcode: VRSHRsv2i32 /* 12732 */ MCD_OPC_FilterValue, 1, 99, 5, 0, // Skip to: 14116 /* 12737 */ MCD_OPC_CheckPredicate, 21, 94, 5, 0, // Skip to: 14116 /* 12742 */ MCD_OPC_Decode, 193, 17, 144, 1, // Opcode: VRSHRuv2i32 /* 12747 */ MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 12891 /* 12752 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 12755 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12853 /* 12760 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12763 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12815 /* 12768 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12771 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12793 /* 12776 */ MCD_OPC_CheckPredicate, 21, 55, 5, 0, // Skip to: 14116 /* 12781 */ MCD_OPC_CheckField, 19, 1, 1, 48, 5, 0, // Skip to: 14116 /* 12788 */ MCD_OPC_Decode, 216, 17, 145, 1, // Opcode: VRSRAsv8i8 /* 12793 */ MCD_OPC_FilterValue, 1, 38, 5, 0, // Skip to: 14116 /* 12798 */ MCD_OPC_CheckPredicate, 21, 33, 5, 0, // Skip to: 14116 /* 12803 */ MCD_OPC_CheckField, 19, 1, 1, 26, 5, 0, // Skip to: 14116 /* 12810 */ MCD_OPC_Decode, 224, 17, 145, 1, // Opcode: VRSRAuv8i8 /* 12815 */ MCD_OPC_FilterValue, 1, 16, 5, 0, // Skip to: 14116 /* 12820 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12823 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12838 /* 12828 */ MCD_OPC_CheckPredicate, 21, 3, 5, 0, // Skip to: 14116 /* 12833 */ MCD_OPC_Decode, 213, 17, 146, 1, // Opcode: VRSRAsv4i16 /* 12838 */ MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 14116 /* 12843 */ MCD_OPC_CheckPredicate, 21, 244, 4, 0, // Skip to: 14116 /* 12848 */ MCD_OPC_Decode, 221, 17, 146, 1, // Opcode: VRSRAuv4i16 /* 12853 */ MCD_OPC_FilterValue, 1, 234, 4, 0, // Skip to: 14116 /* 12858 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 12861 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12876 /* 12866 */ MCD_OPC_CheckPredicate, 21, 221, 4, 0, // Skip to: 14116 /* 12871 */ MCD_OPC_Decode, 211, 17, 147, 1, // Opcode: VRSRAsv2i32 /* 12876 */ MCD_OPC_FilterValue, 1, 211, 4, 0, // Skip to: 14116 /* 12881 */ MCD_OPC_CheckPredicate, 21, 206, 4, 0, // Skip to: 14116 /* 12886 */ MCD_OPC_Decode, 219, 17, 147, 1, // Opcode: VRSRAuv2i32 /* 12891 */ MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 12980 /* 12896 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 12899 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 12958 /* 12904 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12907 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 12936 /* 12912 */ MCD_OPC_CheckPredicate, 21, 175, 4, 0, // Skip to: 14116 /* 12917 */ MCD_OPC_CheckField, 24, 1, 1, 168, 4, 0, // Skip to: 14116 /* 12924 */ MCD_OPC_CheckField, 19, 1, 1, 161, 4, 0, // Skip to: 14116 /* 12931 */ MCD_OPC_Decode, 214, 18, 145, 1, // Opcode: VSRIv8i8 /* 12936 */ MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 14116 /* 12941 */ MCD_OPC_CheckPredicate, 21, 146, 4, 0, // Skip to: 14116 /* 12946 */ MCD_OPC_CheckField, 24, 1, 1, 139, 4, 0, // Skip to: 14116 /* 12953 */ MCD_OPC_Decode, 211, 18, 146, 1, // Opcode: VSRIv4i16 /* 12958 */ MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 14116 /* 12963 */ MCD_OPC_CheckPredicate, 21, 124, 4, 0, // Skip to: 14116 /* 12968 */ MCD_OPC_CheckField, 24, 1, 1, 117, 4, 0, // Skip to: 14116 /* 12975 */ MCD_OPC_Decode, 209, 18, 147, 1, // Opcode: VSRIv2i32 /* 12980 */ MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 13124 /* 12985 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 12988 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13086 /* 12993 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 12996 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13048 /* 13001 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13004 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13026 /* 13009 */ MCD_OPC_CheckPredicate, 21, 78, 4, 0, // Skip to: 14116 /* 13014 */ MCD_OPC_CheckField, 19, 1, 1, 71, 4, 0, // Skip to: 14116 /* 13021 */ MCD_OPC_Decode, 135, 18, 148, 1, // Opcode: VSHLiv8i8 /* 13026 */ MCD_OPC_FilterValue, 1, 61, 4, 0, // Skip to: 14116 /* 13031 */ MCD_OPC_CheckPredicate, 21, 56, 4, 0, // Skip to: 14116 /* 13036 */ MCD_OPC_CheckField, 19, 1, 1, 49, 4, 0, // Skip to: 14116 /* 13043 */ MCD_OPC_Decode, 184, 18, 149, 1, // Opcode: VSLIv8i8 /* 13048 */ MCD_OPC_FilterValue, 1, 39, 4, 0, // Skip to: 14116 /* 13053 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13056 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13071 /* 13061 */ MCD_OPC_CheckPredicate, 21, 26, 4, 0, // Skip to: 14116 /* 13066 */ MCD_OPC_Decode, 132, 18, 150, 1, // Opcode: VSHLiv4i16 /* 13071 */ MCD_OPC_FilterValue, 1, 16, 4, 0, // Skip to: 14116 /* 13076 */ MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 14116 /* 13081 */ MCD_OPC_Decode, 181, 18, 151, 1, // Opcode: VSLIv4i16 /* 13086 */ MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 14116 /* 13091 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13109 /* 13099 */ MCD_OPC_CheckPredicate, 21, 244, 3, 0, // Skip to: 14116 /* 13104 */ MCD_OPC_Decode, 130, 18, 152, 1, // Opcode: VSHLiv2i32 /* 13109 */ MCD_OPC_FilterValue, 1, 234, 3, 0, // Skip to: 14116 /* 13114 */ MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 14116 /* 13119 */ MCD_OPC_Decode, 179, 18, 153, 1, // Opcode: VSLIv2i32 /* 13124 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 13213 /* 13129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 13132 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 13191 /* 13137 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13140 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13169 /* 13145 */ MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 14116 /* 13150 */ MCD_OPC_CheckField, 24, 1, 1, 191, 3, 0, // Skip to: 14116 /* 13157 */ MCD_OPC_CheckField, 19, 1, 1, 184, 3, 0, // Skip to: 14116 /* 13164 */ MCD_OPC_Decode, 160, 16, 148, 1, // Opcode: VQSHLsuv8i8 /* 13169 */ MCD_OPC_FilterValue, 1, 174, 3, 0, // Skip to: 14116 /* 13174 */ MCD_OPC_CheckPredicate, 21, 169, 3, 0, // Skip to: 14116 /* 13179 */ MCD_OPC_CheckField, 24, 1, 1, 162, 3, 0, // Skip to: 14116 /* 13186 */ MCD_OPC_Decode, 157, 16, 150, 1, // Opcode: VQSHLsuv4i16 /* 13191 */ MCD_OPC_FilterValue, 1, 152, 3, 0, // Skip to: 14116 /* 13196 */ MCD_OPC_CheckPredicate, 21, 147, 3, 0, // Skip to: 14116 /* 13201 */ MCD_OPC_CheckField, 24, 1, 1, 140, 3, 0, // Skip to: 14116 /* 13208 */ MCD_OPC_Decode, 155, 16, 152, 1, // Opcode: VQSHLsuv2i32 /* 13213 */ MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 13357 /* 13218 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 13221 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13319 /* 13226 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13229 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13281 /* 13234 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13237 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13259 /* 13242 */ MCD_OPC_CheckPredicate, 21, 101, 3, 0, // Skip to: 14116 /* 13247 */ MCD_OPC_CheckField, 19, 1, 1, 94, 3, 0, // Skip to: 14116 /* 13254 */ MCD_OPC_Decode, 152, 16, 148, 1, // Opcode: VQSHLsiv8i8 /* 13259 */ MCD_OPC_FilterValue, 1, 84, 3, 0, // Skip to: 14116 /* 13264 */ MCD_OPC_CheckPredicate, 21, 79, 3, 0, // Skip to: 14116 /* 13269 */ MCD_OPC_CheckField, 19, 1, 1, 72, 3, 0, // Skip to: 14116 /* 13276 */ MCD_OPC_Decode, 176, 16, 148, 1, // Opcode: VQSHLuiv8i8 /* 13281 */ MCD_OPC_FilterValue, 1, 62, 3, 0, // Skip to: 14116 /* 13286 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13289 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13304 /* 13294 */ MCD_OPC_CheckPredicate, 21, 49, 3, 0, // Skip to: 14116 /* 13299 */ MCD_OPC_Decode, 149, 16, 150, 1, // Opcode: VQSHLsiv4i16 /* 13304 */ MCD_OPC_FilterValue, 1, 39, 3, 0, // Skip to: 14116 /* 13309 */ MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 14116 /* 13314 */ MCD_OPC_Decode, 173, 16, 150, 1, // Opcode: VQSHLuiv4i16 /* 13319 */ MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 14116 /* 13324 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13327 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13342 /* 13332 */ MCD_OPC_CheckPredicate, 21, 11, 3, 0, // Skip to: 14116 /* 13337 */ MCD_OPC_Decode, 147, 16, 152, 1, // Opcode: VQSHLsiv2i32 /* 13342 */ MCD_OPC_FilterValue, 1, 1, 3, 0, // Skip to: 14116 /* 13347 */ MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 14116 /* 13352 */ MCD_OPC_Decode, 171, 16, 152, 1, // Opcode: VQSHLuiv2i32 /* 13357 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 13501 /* 13362 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 13365 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13463 /* 13370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13373 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13425 /* 13378 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13381 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13403 /* 13386 */ MCD_OPC_CheckPredicate, 21, 213, 2, 0, // Skip to: 14116 /* 13391 */ MCD_OPC_CheckField, 19, 1, 1, 206, 2, 0, // Skip to: 14116 /* 13398 */ MCD_OPC_Decode, 154, 18, 154, 1, // Opcode: VSHRNv8i8 /* 13403 */ MCD_OPC_FilterValue, 1, 196, 2, 0, // Skip to: 14116 /* 13408 */ MCD_OPC_CheckPredicate, 21, 191, 2, 0, // Skip to: 14116 /* 13413 */ MCD_OPC_CheckField, 19, 1, 1, 184, 2, 0, // Skip to: 14116 /* 13420 */ MCD_OPC_Decode, 193, 16, 154, 1, // Opcode: VQSHRUNv8i8 /* 13425 */ MCD_OPC_FilterValue, 1, 174, 2, 0, // Skip to: 14116 /* 13430 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13433 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13448 /* 13438 */ MCD_OPC_CheckPredicate, 21, 161, 2, 0, // Skip to: 14116 /* 13443 */ MCD_OPC_Decode, 153, 18, 155, 1, // Opcode: VSHRNv4i16 /* 13448 */ MCD_OPC_FilterValue, 1, 151, 2, 0, // Skip to: 14116 /* 13453 */ MCD_OPC_CheckPredicate, 21, 146, 2, 0, // Skip to: 14116 /* 13458 */ MCD_OPC_Decode, 192, 16, 155, 1, // Opcode: VQSHRUNv4i16 /* 13463 */ MCD_OPC_FilterValue, 1, 136, 2, 0, // Skip to: 14116 /* 13468 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13471 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13486 /* 13476 */ MCD_OPC_CheckPredicate, 21, 123, 2, 0, // Skip to: 14116 /* 13481 */ MCD_OPC_Decode, 152, 18, 156, 1, // Opcode: VSHRNv2i32 /* 13486 */ MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 14116 /* 13491 */ MCD_OPC_CheckPredicate, 21, 108, 2, 0, // Skip to: 14116 /* 13496 */ MCD_OPC_Decode, 191, 16, 156, 1, // Opcode: VQSHRUNv2i32 /* 13501 */ MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 13645 /* 13506 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 13509 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13607 /* 13514 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13517 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13569 /* 13522 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13525 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13547 /* 13530 */ MCD_OPC_CheckPredicate, 21, 69, 2, 0, // Skip to: 14116 /* 13535 */ MCD_OPC_CheckField, 19, 1, 1, 62, 2, 0, // Skip to: 14116 /* 13542 */ MCD_OPC_Decode, 187, 16, 154, 1, // Opcode: VQSHRNsv8i8 /* 13547 */ MCD_OPC_FilterValue, 1, 52, 2, 0, // Skip to: 14116 /* 13552 */ MCD_OPC_CheckPredicate, 21, 47, 2, 0, // Skip to: 14116 /* 13557 */ MCD_OPC_CheckField, 19, 1, 1, 40, 2, 0, // Skip to: 14116 /* 13564 */ MCD_OPC_Decode, 190, 16, 154, 1, // Opcode: VQSHRNuv8i8 /* 13569 */ MCD_OPC_FilterValue, 1, 30, 2, 0, // Skip to: 14116 /* 13574 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13577 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13592 /* 13582 */ MCD_OPC_CheckPredicate, 21, 17, 2, 0, // Skip to: 14116 /* 13587 */ MCD_OPC_Decode, 186, 16, 155, 1, // Opcode: VQSHRNsv4i16 /* 13592 */ MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 14116 /* 13597 */ MCD_OPC_CheckPredicate, 21, 2, 2, 0, // Skip to: 14116 /* 13602 */ MCD_OPC_Decode, 189, 16, 155, 1, // Opcode: VQSHRNuv4i16 /* 13607 */ MCD_OPC_FilterValue, 1, 248, 1, 0, // Skip to: 14116 /* 13612 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13615 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13630 /* 13620 */ MCD_OPC_CheckPredicate, 21, 235, 1, 0, // Skip to: 14116 /* 13625 */ MCD_OPC_Decode, 185, 16, 156, 1, // Opcode: VQSHRNsv2i32 /* 13630 */ MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 14116 /* 13635 */ MCD_OPC_CheckPredicate, 21, 220, 1, 0, // Skip to: 14116 /* 13640 */ MCD_OPC_Decode, 188, 16, 156, 1, // Opcode: VQSHRNuv2i32 /* 13645 */ MCD_OPC_FilterValue, 10, 243, 0, 0, // Skip to: 13893 /* 13650 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 13653 */ MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 13821 /* 13658 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 13661 */ MCD_OPC_FilterValue, 0, 83, 0, 0, // Skip to: 13749 /* 13666 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13669 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 13709 /* 13674 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 13677 */ MCD_OPC_FilterValue, 1, 178, 1, 0, // Skip to: 14116 /* 13682 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13699 /* 13687 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13699 /* 13694 */ MCD_OPC_Decode, 142, 14, 134, 1, // Opcode: VMOVLsv8i16 /* 13699 */ MCD_OPC_CheckPredicate, 21, 156, 1, 0, // Skip to: 14116 /* 13704 */ MCD_OPC_Decode, 252, 17, 157, 1, // Opcode: VSHLLsv8i16 /* 13709 */ MCD_OPC_FilterValue, 1, 146, 1, 0, // Skip to: 14116 /* 13714 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 13717 */ MCD_OPC_FilterValue, 1, 138, 1, 0, // Skip to: 14116 /* 13722 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13739 /* 13727 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13739 /* 13734 */ MCD_OPC_Decode, 145, 14, 134, 1, // Opcode: VMOVLuv8i16 /* 13739 */ MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 14116 /* 13744 */ MCD_OPC_Decode, 255, 17, 157, 1, // Opcode: VSHLLuv8i16 /* 13749 */ MCD_OPC_FilterValue, 1, 106, 1, 0, // Skip to: 14116 /* 13754 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13757 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13789 /* 13762 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13779 /* 13767 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13779 /* 13774 */ MCD_OPC_Decode, 141, 14, 134, 1, // Opcode: VMOVLsv4i32 /* 13779 */ MCD_OPC_CheckPredicate, 21, 76, 1, 0, // Skip to: 14116 /* 13784 */ MCD_OPC_Decode, 251, 17, 158, 1, // Opcode: VSHLLsv4i32 /* 13789 */ MCD_OPC_FilterValue, 1, 66, 1, 0, // Skip to: 14116 /* 13794 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13811 /* 13799 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13811 /* 13806 */ MCD_OPC_Decode, 144, 14, 134, 1, // Opcode: VMOVLuv4i32 /* 13811 */ MCD_OPC_CheckPredicate, 21, 44, 1, 0, // Skip to: 14116 /* 13816 */ MCD_OPC_Decode, 254, 17, 158, 1, // Opcode: VSHLLuv4i32 /* 13821 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 14116 /* 13826 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13829 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13861 /* 13834 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13851 /* 13839 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13851 /* 13846 */ MCD_OPC_Decode, 140, 14, 134, 1, // Opcode: VMOVLsv2i64 /* 13851 */ MCD_OPC_CheckPredicate, 21, 4, 1, 0, // Skip to: 14116 /* 13856 */ MCD_OPC_Decode, 250, 17, 159, 1, // Opcode: VSHLLsv2i64 /* 13861 */ MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 14116 /* 13866 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13883 /* 13871 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13883 /* 13878 */ MCD_OPC_Decode, 143, 14, 134, 1, // Opcode: VMOVLuv2i64 /* 13883 */ MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 14116 /* 13888 */ MCD_OPC_Decode, 253, 17, 159, 1, // Opcode: VSHLLuv2i64 /* 13893 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 13931 /* 13898 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13901 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13916 /* 13906 */ MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 14116 /* 13911 */ MCD_OPC_Decode, 247, 9, 160, 1, // Opcode: VCVTxs2hd /* 13916 */ MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 14116 /* 13921 */ MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 14116 /* 13926 */ MCD_OPC_Decode, 251, 9, 160, 1, // Opcode: VCVTxu2hd /* 13931 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 13969 /* 13936 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 13939 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13954 /* 13944 */ MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 14116 /* 13949 */ MCD_OPC_Decode, 233, 9, 160, 1, // Opcode: VCVTh2xsd /* 13954 */ MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 14116 /* 13959 */ MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 14116 /* 13964 */ MCD_OPC_Decode, 235, 9, 160, 1, // Opcode: VCVTh2xud /* 13969 */ MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 14054 /* 13974 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 13977 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13999 /* 13982 */ MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 14021 /* 13987 */ MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 14021 /* 13994 */ MCD_OPC_Decode, 165, 14, 161, 1, // Opcode: VMOVv8i8 /* 13999 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14021 /* 14004 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14021 /* 14009 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 14021 /* 14016 */ MCD_OPC_Decode, 157, 14, 161, 1, // Opcode: VMOVv1i64 /* 14021 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 14024 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14039 /* 14029 */ MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 14116 /* 14034 */ MCD_OPC_Decode, 245, 9, 160, 1, // Opcode: VCVTxs2fd /* 14039 */ MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 14116 /* 14044 */ MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 14116 /* 14049 */ MCD_OPC_Decode, 249, 9, 160, 1, // Opcode: VCVTxu2fd /* 14054 */ MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 14116 /* 14059 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 14062 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14077 /* 14067 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 14092 /* 14072 */ MCD_OPC_Decode, 224, 9, 160, 1, // Opcode: VCVTf2xsd /* 14077 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14092 /* 14082 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 14092 /* 14087 */ MCD_OPC_Decode, 226, 9, 160, 1, // Opcode: VCVTf2xud /* 14092 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 14116 /* 14097 */ MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 14116 /* 14104 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 14116 /* 14111 */ MCD_OPC_Decode, 158, 14, 161, 1, // Opcode: VMOVv2f32 /* 14116 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 14119 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 14212 /* 14124 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... /* 14127 */ MCD_OPC_FilterValue, 0, 69, 17, 0, // Skip to: 18553 /* 14132 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 14135 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14157 /* 14140 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14202 /* 14145 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14202 /* 14152 */ MCD_OPC_Decode, 162, 14, 161, 1, // Opcode: VMOVv4i16 /* 14157 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14202 /* 14162 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 14165 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14180 /* 14170 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14202 /* 14175 */ MCD_OPC_Decode, 245, 14, 161, 1, // Opcode: VORRiv2i32 /* 14180 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14202 /* 14185 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14202 /* 14190 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14202 /* 14197 */ MCD_OPC_Decode, 246, 14, 161, 1, // Opcode: VORRiv4i16 /* 14202 */ MCD_OPC_CheckPredicate, 21, 250, 16, 0, // Skip to: 18553 /* 14207 */ MCD_OPC_Decode, 159, 14, 161, 1, // Opcode: VMOVv2i32 /* 14212 */ MCD_OPC_FilterValue, 1, 240, 16, 0, // Skip to: 18553 /* 14217 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... /* 14220 */ MCD_OPC_FilterValue, 0, 232, 16, 0, // Skip to: 18553 /* 14225 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 14228 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14250 /* 14233 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14295 /* 14238 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14295 /* 14245 */ MCD_OPC_Decode, 217, 14, 161, 1, // Opcode: VMVNv4i16 /* 14250 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14295 /* 14255 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 14258 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14273 /* 14263 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14295 /* 14268 */ MCD_OPC_Decode, 140, 8, 161, 1, // Opcode: VBICiv2i32 /* 14273 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14295 /* 14278 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14295 /* 14283 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14295 /* 14290 */ MCD_OPC_Decode, 141, 8, 161, 1, // Opcode: VBICiv4i16 /* 14295 */ MCD_OPC_CheckPredicate, 21, 157, 16, 0, // Skip to: 18553 /* 14300 */ MCD_OPC_Decode, 216, 14, 161, 1, // Opcode: VMVNv2i32 /* 14305 */ MCD_OPC_FilterValue, 1, 147, 16, 0, // Skip to: 18553 /* 14310 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 14313 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 14353 /* 14318 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14321 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14337 /* 14327 */ MCD_OPC_CheckPredicate, 21, 125, 16, 0, // Skip to: 18553 /* 14332 */ MCD_OPC_Decode, 156, 18, 162, 1, // Opcode: VSHRsv1i64 /* 14337 */ MCD_OPC_FilterValue, 243, 1, 114, 16, 0, // Skip to: 18553 /* 14343 */ MCD_OPC_CheckPredicate, 21, 109, 16, 0, // Skip to: 18553 /* 14348 */ MCD_OPC_Decode, 164, 18, 162, 1, // Opcode: VSHRuv1i64 /* 14353 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 14393 /* 14358 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14361 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14377 /* 14367 */ MCD_OPC_CheckPredicate, 21, 85, 16, 0, // Skip to: 18553 /* 14372 */ MCD_OPC_Decode, 192, 18, 163, 1, // Opcode: VSRAsv1i64 /* 14377 */ MCD_OPC_FilterValue, 243, 1, 74, 16, 0, // Skip to: 18553 /* 14383 */ MCD_OPC_CheckPredicate, 21, 69, 16, 0, // Skip to: 18553 /* 14388 */ MCD_OPC_Decode, 200, 18, 163, 1, // Opcode: VSRAuv1i64 /* 14393 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 14433 /* 14398 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14401 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14417 /* 14407 */ MCD_OPC_CheckPredicate, 21, 45, 16, 0, // Skip to: 18553 /* 14412 */ MCD_OPC_Decode, 184, 17, 162, 1, // Opcode: VRSHRsv1i64 /* 14417 */ MCD_OPC_FilterValue, 243, 1, 34, 16, 0, // Skip to: 18553 /* 14423 */ MCD_OPC_CheckPredicate, 21, 29, 16, 0, // Skip to: 18553 /* 14428 */ MCD_OPC_Decode, 192, 17, 162, 1, // Opcode: VRSHRuv1i64 /* 14433 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 14473 /* 14438 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14441 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14457 /* 14447 */ MCD_OPC_CheckPredicate, 21, 5, 16, 0, // Skip to: 18553 /* 14452 */ MCD_OPC_Decode, 210, 17, 163, 1, // Opcode: VRSRAsv1i64 /* 14457 */ MCD_OPC_FilterValue, 243, 1, 250, 15, 0, // Skip to: 18553 /* 14463 */ MCD_OPC_CheckPredicate, 21, 245, 15, 0, // Skip to: 18553 /* 14468 */ MCD_OPC_Decode, 218, 17, 163, 1, // Opcode: VRSRAuv1i64 /* 14473 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 14496 /* 14478 */ MCD_OPC_CheckPredicate, 21, 230, 15, 0, // Skip to: 18553 /* 14483 */ MCD_OPC_CheckField, 24, 8, 243, 1, 222, 15, 0, // Skip to: 18553 /* 14491 */ MCD_OPC_Decode, 208, 18, 163, 1, // Opcode: VSRIv1i64 /* 14496 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 14536 /* 14501 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14504 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14520 /* 14510 */ MCD_OPC_CheckPredicate, 21, 198, 15, 0, // Skip to: 18553 /* 14515 */ MCD_OPC_Decode, 129, 18, 164, 1, // Opcode: VSHLiv1i64 /* 14520 */ MCD_OPC_FilterValue, 243, 1, 187, 15, 0, // Skip to: 18553 /* 14526 */ MCD_OPC_CheckPredicate, 21, 182, 15, 0, // Skip to: 18553 /* 14531 */ MCD_OPC_Decode, 178, 18, 165, 1, // Opcode: VSLIv1i64 /* 14536 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 14559 /* 14541 */ MCD_OPC_CheckPredicate, 21, 167, 15, 0, // Skip to: 18553 /* 14546 */ MCD_OPC_CheckField, 24, 8, 243, 1, 159, 15, 0, // Skip to: 18553 /* 14554 */ MCD_OPC_Decode, 154, 16, 164, 1, // Opcode: VQSHLsuv1i64 /* 14559 */ MCD_OPC_FilterValue, 7, 149, 15, 0, // Skip to: 18553 /* 14564 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14567 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14583 /* 14573 */ MCD_OPC_CheckPredicate, 21, 135, 15, 0, // Skip to: 18553 /* 14578 */ MCD_OPC_Decode, 146, 16, 164, 1, // Opcode: VQSHLsiv1i64 /* 14583 */ MCD_OPC_FilterValue, 243, 1, 124, 15, 0, // Skip to: 18553 /* 14589 */ MCD_OPC_CheckPredicate, 21, 119, 15, 0, // Skip to: 18553 /* 14594 */ MCD_OPC_Decode, 170, 16, 164, 1, // Opcode: VQSHLuiv1i64 /* 14599 */ MCD_OPC_FilterValue, 1, 109, 15, 0, // Skip to: 18553 /* 14604 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 14607 */ MCD_OPC_FilterValue, 0, 89, 7, 0, // Skip to: 16493 /* 14612 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 14615 */ MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 14775 /* 14620 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 14623 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14661 /* 14628 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14631 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14646 /* 14637 */ MCD_OPC_CheckPredicate, 21, 71, 15, 0, // Skip to: 18553 /* 14642 */ MCD_OPC_Decode, 173, 15, 98, // Opcode: VQADDsv16i8 /* 14646 */ MCD_OPC_FilterValue, 243, 1, 61, 15, 0, // Skip to: 18553 /* 14652 */ MCD_OPC_CheckPredicate, 21, 56, 15, 0, // Skip to: 18553 /* 14657 */ MCD_OPC_Decode, 181, 15, 98, // Opcode: VQADDuv16i8 /* 14661 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14699 /* 14666 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14669 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14684 /* 14675 */ MCD_OPC_CheckPredicate, 21, 33, 15, 0, // Skip to: 18553 /* 14680 */ MCD_OPC_Decode, 179, 15, 98, // Opcode: VQADDsv8i16 /* 14684 */ MCD_OPC_FilterValue, 243, 1, 23, 15, 0, // Skip to: 18553 /* 14690 */ MCD_OPC_CheckPredicate, 21, 18, 15, 0, // Skip to: 18553 /* 14695 */ MCD_OPC_Decode, 187, 15, 98, // Opcode: VQADDuv8i16 /* 14699 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14737 /* 14704 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14707 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14722 /* 14713 */ MCD_OPC_CheckPredicate, 21, 251, 14, 0, // Skip to: 18553 /* 14718 */ MCD_OPC_Decode, 178, 15, 98, // Opcode: VQADDsv4i32 /* 14722 */ MCD_OPC_FilterValue, 243, 1, 241, 14, 0, // Skip to: 18553 /* 14728 */ MCD_OPC_CheckPredicate, 21, 236, 14, 0, // Skip to: 18553 /* 14733 */ MCD_OPC_Decode, 186, 15, 98, // Opcode: VQADDuv4i32 /* 14737 */ MCD_OPC_FilterValue, 3, 227, 14, 0, // Skip to: 18553 /* 14742 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14745 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14760 /* 14751 */ MCD_OPC_CheckPredicate, 21, 213, 14, 0, // Skip to: 18553 /* 14756 */ MCD_OPC_Decode, 176, 15, 98, // Opcode: VQADDsv2i64 /* 14760 */ MCD_OPC_FilterValue, 243, 1, 203, 14, 0, // Skip to: 18553 /* 14766 */ MCD_OPC_CheckPredicate, 21, 198, 14, 0, // Skip to: 18553 /* 14771 */ MCD_OPC_Decode, 184, 15, 98, // Opcode: VQADDuv2i64 /* 14775 */ MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 14935 /* 14780 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 14783 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14821 /* 14788 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14791 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14806 /* 14797 */ MCD_OPC_CheckPredicate, 21, 167, 14, 0, // Skip to: 18553 /* 14802 */ MCD_OPC_Decode, 138, 8, 98, // Opcode: VANDq /* 14806 */ MCD_OPC_FilterValue, 243, 1, 157, 14, 0, // Skip to: 18553 /* 14812 */ MCD_OPC_CheckPredicate, 21, 152, 14, 0, // Skip to: 18553 /* 14817 */ MCD_OPC_Decode, 141, 10, 98, // Opcode: VEORq /* 14821 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14859 /* 14826 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14829 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14844 /* 14835 */ MCD_OPC_CheckPredicate, 21, 129, 14, 0, // Skip to: 18553 /* 14840 */ MCD_OPC_Decode, 144, 8, 98, // Opcode: VBICq /* 14844 */ MCD_OPC_FilterValue, 243, 1, 119, 14, 0, // Skip to: 18553 /* 14850 */ MCD_OPC_CheckPredicate, 21, 114, 14, 0, // Skip to: 18553 /* 14855 */ MCD_OPC_Decode, 150, 8, 106, // Opcode: VBSLq /* 14859 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14897 /* 14864 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14867 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14882 /* 14873 */ MCD_OPC_CheckPredicate, 21, 91, 14, 0, // Skip to: 18553 /* 14878 */ MCD_OPC_Decode, 249, 14, 98, // Opcode: VORRq /* 14882 */ MCD_OPC_FilterValue, 243, 1, 81, 14, 0, // Skip to: 18553 /* 14888 */ MCD_OPC_CheckPredicate, 21, 76, 14, 0, // Skip to: 18553 /* 14893 */ MCD_OPC_Decode, 148, 8, 106, // Opcode: VBITq /* 14897 */ MCD_OPC_FilterValue, 3, 67, 14, 0, // Skip to: 18553 /* 14902 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14905 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14920 /* 14911 */ MCD_OPC_CheckPredicate, 21, 53, 14, 0, // Skip to: 18553 /* 14916 */ MCD_OPC_Decode, 243, 14, 98, // Opcode: VORNq /* 14920 */ MCD_OPC_FilterValue, 243, 1, 43, 14, 0, // Skip to: 18553 /* 14926 */ MCD_OPC_CheckPredicate, 21, 38, 14, 0, // Skip to: 18553 /* 14931 */ MCD_OPC_Decode, 146, 8, 106, // Opcode: VBIFq /* 14935 */ MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 15095 /* 14940 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 14943 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14981 /* 14948 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14951 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14966 /* 14957 */ MCD_OPC_CheckPredicate, 21, 7, 14, 0, // Skip to: 18553 /* 14962 */ MCD_OPC_Decode, 194, 16, 98, // Opcode: VQSUBsv16i8 /* 14966 */ MCD_OPC_FilterValue, 243, 1, 253, 13, 0, // Skip to: 18553 /* 14972 */ MCD_OPC_CheckPredicate, 21, 248, 13, 0, // Skip to: 18553 /* 14977 */ MCD_OPC_Decode, 202, 16, 98, // Opcode: VQSUBuv16i8 /* 14981 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15019 /* 14986 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 14989 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15004 /* 14995 */ MCD_OPC_CheckPredicate, 21, 225, 13, 0, // Skip to: 18553 /* 15000 */ MCD_OPC_Decode, 200, 16, 98, // Opcode: VQSUBsv8i16 /* 15004 */ MCD_OPC_FilterValue, 243, 1, 215, 13, 0, // Skip to: 18553 /* 15010 */ MCD_OPC_CheckPredicate, 21, 210, 13, 0, // Skip to: 18553 /* 15015 */ MCD_OPC_Decode, 208, 16, 98, // Opcode: VQSUBuv8i16 /* 15019 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15057 /* 15024 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15027 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15042 /* 15033 */ MCD_OPC_CheckPredicate, 21, 187, 13, 0, // Skip to: 18553 /* 15038 */ MCD_OPC_Decode, 199, 16, 98, // Opcode: VQSUBsv4i32 /* 15042 */ MCD_OPC_FilterValue, 243, 1, 177, 13, 0, // Skip to: 18553 /* 15048 */ MCD_OPC_CheckPredicate, 21, 172, 13, 0, // Skip to: 18553 /* 15053 */ MCD_OPC_Decode, 207, 16, 98, // Opcode: VQSUBuv4i32 /* 15057 */ MCD_OPC_FilterValue, 3, 163, 13, 0, // Skip to: 18553 /* 15062 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15065 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15080 /* 15071 */ MCD_OPC_CheckPredicate, 21, 149, 13, 0, // Skip to: 18553 /* 15076 */ MCD_OPC_Decode, 197, 16, 98, // Opcode: VQSUBsv2i64 /* 15080 */ MCD_OPC_FilterValue, 243, 1, 139, 13, 0, // Skip to: 18553 /* 15086 */ MCD_OPC_CheckPredicate, 21, 134, 13, 0, // Skip to: 18553 /* 15091 */ MCD_OPC_Decode, 205, 16, 98, // Opcode: VQSUBuv2i64 /* 15095 */ MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 15217 /* 15100 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15103 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15141 /* 15108 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15111 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15126 /* 15117 */ MCD_OPC_CheckPredicate, 21, 103, 13, 0, // Skip to: 18553 /* 15122 */ MCD_OPC_Decode, 179, 8, 98, // Opcode: VCGEsv16i8 /* 15126 */ MCD_OPC_FilterValue, 243, 1, 93, 13, 0, // Skip to: 18553 /* 15132 */ MCD_OPC_CheckPredicate, 21, 88, 13, 0, // Skip to: 18553 /* 15137 */ MCD_OPC_Decode, 185, 8, 98, // Opcode: VCGEuv16i8 /* 15141 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15179 /* 15146 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15149 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15164 /* 15155 */ MCD_OPC_CheckPredicate, 21, 65, 13, 0, // Skip to: 18553 /* 15160 */ MCD_OPC_Decode, 183, 8, 98, // Opcode: VCGEsv8i16 /* 15164 */ MCD_OPC_FilterValue, 243, 1, 55, 13, 0, // Skip to: 18553 /* 15170 */ MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 18553 /* 15175 */ MCD_OPC_Decode, 189, 8, 98, // Opcode: VCGEuv8i16 /* 15179 */ MCD_OPC_FilterValue, 2, 41, 13, 0, // Skip to: 18553 /* 15184 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15187 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15202 /* 15193 */ MCD_OPC_CheckPredicate, 21, 27, 13, 0, // Skip to: 18553 /* 15198 */ MCD_OPC_Decode, 182, 8, 98, // Opcode: VCGEsv4i32 /* 15202 */ MCD_OPC_FilterValue, 243, 1, 17, 13, 0, // Skip to: 18553 /* 15208 */ MCD_OPC_CheckPredicate, 21, 12, 13, 0, // Skip to: 18553 /* 15213 */ MCD_OPC_Decode, 188, 8, 98, // Opcode: VCGEuv4i32 /* 15217 */ MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 15377 /* 15222 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15225 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15263 /* 15230 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15233 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15248 /* 15239 */ MCD_OPC_CheckPredicate, 21, 237, 12, 0, // Skip to: 18553 /* 15244 */ MCD_OPC_Decode, 161, 16, 102, // Opcode: VQSHLsv16i8 /* 15248 */ MCD_OPC_FilterValue, 243, 1, 227, 12, 0, // Skip to: 18553 /* 15254 */ MCD_OPC_CheckPredicate, 21, 222, 12, 0, // Skip to: 18553 /* 15259 */ MCD_OPC_Decode, 177, 16, 102, // Opcode: VQSHLuv16i8 /* 15263 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15301 /* 15268 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15271 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15286 /* 15277 */ MCD_OPC_CheckPredicate, 21, 199, 12, 0, // Skip to: 18553 /* 15282 */ MCD_OPC_Decode, 167, 16, 102, // Opcode: VQSHLsv8i16 /* 15286 */ MCD_OPC_FilterValue, 243, 1, 189, 12, 0, // Skip to: 18553 /* 15292 */ MCD_OPC_CheckPredicate, 21, 184, 12, 0, // Skip to: 18553 /* 15297 */ MCD_OPC_Decode, 183, 16, 102, // Opcode: VQSHLuv8i16 /* 15301 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15339 /* 15306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15309 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15324 /* 15315 */ MCD_OPC_CheckPredicate, 21, 161, 12, 0, // Skip to: 18553 /* 15320 */ MCD_OPC_Decode, 166, 16, 102, // Opcode: VQSHLsv4i32 /* 15324 */ MCD_OPC_FilterValue, 243, 1, 151, 12, 0, // Skip to: 18553 /* 15330 */ MCD_OPC_CheckPredicate, 21, 146, 12, 0, // Skip to: 18553 /* 15335 */ MCD_OPC_Decode, 182, 16, 102, // Opcode: VQSHLuv4i32 /* 15339 */ MCD_OPC_FilterValue, 3, 137, 12, 0, // Skip to: 18553 /* 15344 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15347 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15362 /* 15353 */ MCD_OPC_CheckPredicate, 21, 123, 12, 0, // Skip to: 18553 /* 15358 */ MCD_OPC_Decode, 164, 16, 102, // Opcode: VQSHLsv2i64 /* 15362 */ MCD_OPC_FilterValue, 243, 1, 113, 12, 0, // Skip to: 18553 /* 15368 */ MCD_OPC_CheckPredicate, 21, 108, 12, 0, // Skip to: 18553 /* 15373 */ MCD_OPC_Decode, 180, 16, 102, // Opcode: VQSHLuv2i64 /* 15377 */ MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 15537 /* 15382 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15385 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15423 /* 15390 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15393 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15408 /* 15399 */ MCD_OPC_CheckPredicate, 21, 77, 12, 0, // Skip to: 18553 /* 15404 */ MCD_OPC_Decode, 248, 15, 102, // Opcode: VQRSHLsv16i8 /* 15408 */ MCD_OPC_FilterValue, 243, 1, 67, 12, 0, // Skip to: 18553 /* 15414 */ MCD_OPC_CheckPredicate, 21, 62, 12, 0, // Skip to: 18553 /* 15419 */ MCD_OPC_Decode, 128, 16, 102, // Opcode: VQRSHLuv16i8 /* 15423 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15461 /* 15428 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15431 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15446 /* 15437 */ MCD_OPC_CheckPredicate, 21, 39, 12, 0, // Skip to: 18553 /* 15442 */ MCD_OPC_Decode, 254, 15, 102, // Opcode: VQRSHLsv8i16 /* 15446 */ MCD_OPC_FilterValue, 243, 1, 29, 12, 0, // Skip to: 18553 /* 15452 */ MCD_OPC_CheckPredicate, 21, 24, 12, 0, // Skip to: 18553 /* 15457 */ MCD_OPC_Decode, 134, 16, 102, // Opcode: VQRSHLuv8i16 /* 15461 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15499 /* 15466 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15469 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15484 /* 15475 */ MCD_OPC_CheckPredicate, 21, 1, 12, 0, // Skip to: 18553 /* 15480 */ MCD_OPC_Decode, 253, 15, 102, // Opcode: VQRSHLsv4i32 /* 15484 */ MCD_OPC_FilterValue, 243, 1, 247, 11, 0, // Skip to: 18553 /* 15490 */ MCD_OPC_CheckPredicate, 21, 242, 11, 0, // Skip to: 18553 /* 15495 */ MCD_OPC_Decode, 133, 16, 102, // Opcode: VQRSHLuv4i32 /* 15499 */ MCD_OPC_FilterValue, 3, 233, 11, 0, // Skip to: 18553 /* 15504 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15507 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15522 /* 15513 */ MCD_OPC_CheckPredicate, 21, 219, 11, 0, // Skip to: 18553 /* 15518 */ MCD_OPC_Decode, 251, 15, 102, // Opcode: VQRSHLsv2i64 /* 15522 */ MCD_OPC_FilterValue, 243, 1, 209, 11, 0, // Skip to: 18553 /* 15528 */ MCD_OPC_CheckPredicate, 21, 204, 11, 0, // Skip to: 18553 /* 15533 */ MCD_OPC_Decode, 131, 16, 102, // Opcode: VQRSHLuv2i64 /* 15537 */ MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 15659 /* 15542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15545 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15583 /* 15550 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15553 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15568 /* 15559 */ MCD_OPC_CheckPredicate, 21, 173, 11, 0, // Skip to: 18553 /* 15564 */ MCD_OPC_Decode, 190, 13, 98, // Opcode: VMINsv16i8 /* 15568 */ MCD_OPC_FilterValue, 243, 1, 163, 11, 0, // Skip to: 18553 /* 15574 */ MCD_OPC_CheckPredicate, 21, 158, 11, 0, // Skip to: 18553 /* 15579 */ MCD_OPC_Decode, 196, 13, 98, // Opcode: VMINuv16i8 /* 15583 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15621 /* 15588 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15591 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15606 /* 15597 */ MCD_OPC_CheckPredicate, 21, 135, 11, 0, // Skip to: 18553 /* 15602 */ MCD_OPC_Decode, 194, 13, 98, // Opcode: VMINsv8i16 /* 15606 */ MCD_OPC_FilterValue, 243, 1, 125, 11, 0, // Skip to: 18553 /* 15612 */ MCD_OPC_CheckPredicate, 21, 120, 11, 0, // Skip to: 18553 /* 15617 */ MCD_OPC_Decode, 200, 13, 98, // Opcode: VMINuv8i16 /* 15621 */ MCD_OPC_FilterValue, 2, 111, 11, 0, // Skip to: 18553 /* 15626 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15629 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15644 /* 15635 */ MCD_OPC_CheckPredicate, 21, 97, 11, 0, // Skip to: 18553 /* 15640 */ MCD_OPC_Decode, 193, 13, 98, // Opcode: VMINsv4i32 /* 15644 */ MCD_OPC_FilterValue, 243, 1, 87, 11, 0, // Skip to: 18553 /* 15650 */ MCD_OPC_CheckPredicate, 21, 82, 11, 0, // Skip to: 18553 /* 15655 */ MCD_OPC_Decode, 199, 13, 98, // Opcode: VMINuv4i32 /* 15659 */ MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 15781 /* 15664 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15667 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15705 /* 15672 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15675 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15690 /* 15681 */ MCD_OPC_CheckPredicate, 21, 51, 11, 0, // Skip to: 18553 /* 15686 */ MCD_OPC_Decode, 180, 7, 106, // Opcode: VABAsv16i8 /* 15690 */ MCD_OPC_FilterValue, 243, 1, 41, 11, 0, // Skip to: 18553 /* 15696 */ MCD_OPC_CheckPredicate, 21, 36, 11, 0, // Skip to: 18553 /* 15701 */ MCD_OPC_Decode, 186, 7, 106, // Opcode: VABAuv16i8 /* 15705 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15743 /* 15710 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15713 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15728 /* 15719 */ MCD_OPC_CheckPredicate, 21, 13, 11, 0, // Skip to: 18553 /* 15724 */ MCD_OPC_Decode, 184, 7, 106, // Opcode: VABAsv8i16 /* 15728 */ MCD_OPC_FilterValue, 243, 1, 3, 11, 0, // Skip to: 18553 /* 15734 */ MCD_OPC_CheckPredicate, 21, 254, 10, 0, // Skip to: 18553 /* 15739 */ MCD_OPC_Decode, 190, 7, 106, // Opcode: VABAuv8i16 /* 15743 */ MCD_OPC_FilterValue, 2, 245, 10, 0, // Skip to: 18553 /* 15748 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15751 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15766 /* 15757 */ MCD_OPC_CheckPredicate, 21, 231, 10, 0, // Skip to: 18553 /* 15762 */ MCD_OPC_Decode, 183, 7, 106, // Opcode: VABAsv4i32 /* 15766 */ MCD_OPC_FilterValue, 243, 1, 221, 10, 0, // Skip to: 18553 /* 15772 */ MCD_OPC_CheckPredicate, 21, 216, 10, 0, // Skip to: 18553 /* 15777 */ MCD_OPC_Decode, 189, 7, 106, // Opcode: VABAuv4i32 /* 15781 */ MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 15903 /* 15786 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15789 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15827 /* 15794 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15797 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15812 /* 15803 */ MCD_OPC_CheckPredicate, 21, 185, 10, 0, // Skip to: 18553 /* 15808 */ MCD_OPC_Decode, 153, 21, 98, // Opcode: VTSTv16i8 /* 15812 */ MCD_OPC_FilterValue, 243, 1, 175, 10, 0, // Skip to: 18553 /* 15818 */ MCD_OPC_CheckPredicate, 21, 170, 10, 0, // Skip to: 18553 /* 15823 */ MCD_OPC_Decode, 159, 8, 98, // Opcode: VCEQv16i8 /* 15827 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15865 /* 15832 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15835 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15850 /* 15841 */ MCD_OPC_CheckPredicate, 21, 147, 10, 0, // Skip to: 18553 /* 15846 */ MCD_OPC_Decode, 157, 21, 98, // Opcode: VTSTv8i16 /* 15850 */ MCD_OPC_FilterValue, 243, 1, 137, 10, 0, // Skip to: 18553 /* 15856 */ MCD_OPC_CheckPredicate, 21, 132, 10, 0, // Skip to: 18553 /* 15861 */ MCD_OPC_Decode, 163, 8, 98, // Opcode: VCEQv8i16 /* 15865 */ MCD_OPC_FilterValue, 2, 123, 10, 0, // Skip to: 18553 /* 15870 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15873 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15888 /* 15879 */ MCD_OPC_CheckPredicate, 21, 109, 10, 0, // Skip to: 18553 /* 15884 */ MCD_OPC_Decode, 156, 21, 98, // Opcode: VTSTv4i32 /* 15888 */ MCD_OPC_FilterValue, 243, 1, 99, 10, 0, // Skip to: 18553 /* 15894 */ MCD_OPC_CheckPredicate, 21, 94, 10, 0, // Skip to: 18553 /* 15899 */ MCD_OPC_Decode, 162, 8, 98, // Opcode: VCEQv4i32 /* 15903 */ MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 15993 /* 15908 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 15911 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15949 /* 15916 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 15919 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15934 /* 15925 */ MCD_OPC_CheckPredicate, 21, 63, 10, 0, // Skip to: 18553 /* 15930 */ MCD_OPC_Decode, 208, 14, 98, // Opcode: VMULv16i8 /* 15934 */ MCD_OPC_FilterValue, 243, 1, 53, 10, 0, // Skip to: 18553 /* 15940 */ MCD_OPC_CheckPredicate, 21, 48, 10, 0, // Skip to: 18553 /* 15945 */ MCD_OPC_Decode, 199, 14, 98, // Opcode: VMULpq /* 15949 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15971 /* 15954 */ MCD_OPC_CheckPredicate, 21, 34, 10, 0, // Skip to: 18553 /* 15959 */ MCD_OPC_CheckField, 24, 8, 242, 1, 26, 10, 0, // Skip to: 18553 /* 15967 */ MCD_OPC_Decode, 212, 14, 98, // Opcode: VMULv8i16 /* 15971 */ MCD_OPC_FilterValue, 2, 17, 10, 0, // Skip to: 18553 /* 15976 */ MCD_OPC_CheckPredicate, 21, 12, 10, 0, // Skip to: 18553 /* 15981 */ MCD_OPC_CheckField, 24, 8, 242, 1, 4, 10, 0, // Skip to: 18553 /* 15989 */ MCD_OPC_Decode, 211, 14, 98, // Opcode: VMULv4i32 /* 15993 */ MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 16045 /* 15998 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 16001 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16023 /* 16006 */ MCD_OPC_CheckPredicate, 23, 238, 9, 0, // Skip to: 18553 /* 16011 */ MCD_OPC_CheckField, 24, 8, 243, 1, 230, 9, 0, // Skip to: 18553 /* 16019 */ MCD_OPC_Decode, 231, 15, 106, // Opcode: VQRDMLAHv8i16 /* 16023 */ MCD_OPC_FilterValue, 2, 221, 9, 0, // Skip to: 18553 /* 16028 */ MCD_OPC_CheckPredicate, 23, 216, 9, 0, // Skip to: 18553 /* 16033 */ MCD_OPC_CheckField, 24, 8, 243, 1, 208, 9, 0, // Skip to: 18553 /* 16041 */ MCD_OPC_Decode, 230, 15, 106, // Opcode: VQRDMLAHv4i32 /* 16045 */ MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 16173 /* 16050 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 16053 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16075 /* 16058 */ MCD_OPC_CheckPredicate, 26, 186, 9, 0, // Skip to: 18553 /* 16063 */ MCD_OPC_CheckField, 24, 8, 242, 1, 178, 9, 0, // Skip to: 18553 /* 16071 */ MCD_OPC_Decode, 153, 10, 106, // Opcode: VFMAfq /* 16075 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16113 /* 16080 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 16083 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16098 /* 16089 */ MCD_OPC_CheckPredicate, 22, 155, 9, 0, // Skip to: 18553 /* 16094 */ MCD_OPC_Decode, 155, 10, 106, // Opcode: VFMAhq /* 16098 */ MCD_OPC_FilterValue, 243, 1, 145, 9, 0, // Skip to: 18553 /* 16104 */ MCD_OPC_CheckPredicate, 23, 140, 9, 0, // Skip to: 18553 /* 16109 */ MCD_OPC_Decode, 239, 15, 106, // Opcode: VQRDMLSHv8i16 /* 16113 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16151 /* 16118 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 16121 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16136 /* 16127 */ MCD_OPC_CheckPredicate, 26, 117, 9, 0, // Skip to: 18553 /* 16132 */ MCD_OPC_Decode, 160, 10, 106, // Opcode: VFMSfq /* 16136 */ MCD_OPC_FilterValue, 243, 1, 107, 9, 0, // Skip to: 18553 /* 16142 */ MCD_OPC_CheckPredicate, 23, 102, 9, 0, // Skip to: 18553 /* 16147 */ MCD_OPC_Decode, 238, 15, 106, // Opcode: VQRDMLSHv4i32 /* 16151 */ MCD_OPC_FilterValue, 3, 93, 9, 0, // Skip to: 18553 /* 16156 */ MCD_OPC_CheckPredicate, 22, 88, 9, 0, // Skip to: 18553 /* 16161 */ MCD_OPC_CheckField, 24, 8, 242, 1, 80, 9, 0, // Skip to: 18553 /* 16169 */ MCD_OPC_Decode, 162, 10, 106, // Opcode: VFMShq /* 16173 */ MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 16301 /* 16178 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 16181 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16219 /* 16186 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 16189 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16204 /* 16195 */ MCD_OPC_CheckPredicate, 21, 49, 9, 0, // Skip to: 18553 /* 16200 */ MCD_OPC_Decode, 216, 13, 106, // Opcode: VMLAfq /* 16204 */ MCD_OPC_FilterValue, 243, 1, 39, 9, 0, // Skip to: 18553 /* 16210 */ MCD_OPC_CheckPredicate, 21, 34, 9, 0, // Skip to: 18553 /* 16215 */ MCD_OPC_Decode, 195, 14, 98, // Opcode: VMULfq /* 16219 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16257 /* 16224 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 16227 */ MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16242 /* 16233 */ MCD_OPC_CheckPredicate, 22, 11, 9, 0, // Skip to: 18553 /* 16238 */ MCD_OPC_Decode, 218, 13, 106, // Opcode: VMLAhq /* 16242 */ MCD_OPC_FilterValue, 243, 1, 1, 9, 0, // Skip to: 18553 /* 16248 */ MCD_OPC_CheckPredicate, 22, 252, 8, 0, // Skip to: 18553 /* 16253 */ MCD_OPC_Decode, 197, 14, 98, // Opcode: VMULhq /* 16257 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16279 /* 16262 */ MCD_OPC_CheckPredicate, 21, 238, 8, 0, // Skip to: 18553 /* 16267 */ MCD_OPC_CheckField, 24, 8, 242, 1, 230, 8, 0, // Skip to: 18553 /* 16275 */ MCD_OPC_Decode, 247, 13, 106, // Opcode: VMLSfq /* 16279 */ MCD_OPC_FilterValue, 3, 221, 8, 0, // Skip to: 18553 /* 16284 */ MCD_OPC_CheckPredicate, 22, 216, 8, 0, // Skip to: 18553 /* 16289 */ MCD_OPC_CheckField, 24, 8, 242, 1, 208, 8, 0, // Skip to: 18553 /* 16297 */ MCD_OPC_Decode, 249, 13, 106, // Opcode: VMLShq /* 16301 */ MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 16397 /* 16306 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 16309 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16331 /* 16314 */ MCD_OPC_CheckPredicate, 21, 186, 8, 0, // Skip to: 18553 /* 16319 */ MCD_OPC_CheckField, 24, 8, 243, 1, 178, 8, 0, // Skip to: 18553 /* 16327 */ MCD_OPC_Decode, 228, 7, 98, // Opcode: VACGEfq /* 16331 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16353 /* 16336 */ MCD_OPC_CheckPredicate, 22, 164, 8, 0, // Skip to: 18553 /* 16341 */ MCD_OPC_CheckField, 24, 8, 243, 1, 156, 8, 0, // Skip to: 18553 /* 16349 */ MCD_OPC_Decode, 230, 7, 98, // Opcode: VACGEhq /* 16353 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16375 /* 16358 */ MCD_OPC_CheckPredicate, 21, 142, 8, 0, // Skip to: 18553 /* 16363 */ MCD_OPC_CheckField, 24, 8, 243, 1, 134, 8, 0, // Skip to: 18553 /* 16371 */ MCD_OPC_Decode, 232, 7, 98, // Opcode: VACGTfq /* 16375 */ MCD_OPC_FilterValue, 3, 125, 8, 0, // Skip to: 18553 /* 16380 */ MCD_OPC_CheckPredicate, 22, 120, 8, 0, // Skip to: 18553 /* 16385 */ MCD_OPC_CheckField, 24, 8, 243, 1, 112, 8, 0, // Skip to: 18553 /* 16393 */ MCD_OPC_Decode, 234, 7, 98, // Opcode: VACGThq /* 16397 */ MCD_OPC_FilterValue, 15, 103, 8, 0, // Skip to: 18553 /* 16402 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 16405 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16427 /* 16410 */ MCD_OPC_CheckPredicate, 21, 90, 8, 0, // Skip to: 18553 /* 16415 */ MCD_OPC_CheckField, 24, 8, 242, 1, 82, 8, 0, // Skip to: 18553 /* 16423 */ MCD_OPC_Decode, 220, 16, 98, // Opcode: VRECPSfq /* 16427 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16449 /* 16432 */ MCD_OPC_CheckPredicate, 22, 68, 8, 0, // Skip to: 18553 /* 16437 */ MCD_OPC_CheckField, 24, 8, 242, 1, 60, 8, 0, // Skip to: 18553 /* 16445 */ MCD_OPC_Decode, 222, 16, 98, // Opcode: VRECPShq /* 16449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16471 /* 16454 */ MCD_OPC_CheckPredicate, 21, 46, 8, 0, // Skip to: 18553 /* 16459 */ MCD_OPC_CheckField, 24, 8, 242, 1, 38, 8, 0, // Skip to: 18553 /* 16467 */ MCD_OPC_Decode, 206, 17, 98, // Opcode: VRSQRTSfq /* 16471 */ MCD_OPC_FilterValue, 3, 29, 8, 0, // Skip to: 18553 /* 16476 */ MCD_OPC_CheckPredicate, 22, 24, 8, 0, // Skip to: 18553 /* 16481 */ MCD_OPC_CheckField, 24, 8, 242, 1, 16, 8, 0, // Skip to: 18553 /* 16489 */ MCD_OPC_Decode, 208, 17, 98, // Opcode: VRSQRTShq /* 16493 */ MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 18553 /* 16498 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 16501 */ MCD_OPC_FilterValue, 0, 217, 6, 0, // Skip to: 18259 /* 16506 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 16509 */ MCD_OPC_FilterValue, 121, 247, 7, 0, // Skip to: 18553 /* 16514 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16517 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 16661 /* 16522 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 16525 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16623 /* 16530 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 16533 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16585 /* 16538 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16541 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16563 /* 16546 */ MCD_OPC_CheckPredicate, 21, 239, 5, 0, // Skip to: 18070 /* 16551 */ MCD_OPC_CheckField, 19, 1, 1, 232, 5, 0, // Skip to: 18070 /* 16558 */ MCD_OPC_Decode, 155, 18, 166, 1, // Opcode: VSHRsv16i8 /* 16563 */ MCD_OPC_FilterValue, 1, 222, 5, 0, // Skip to: 18070 /* 16568 */ MCD_OPC_CheckPredicate, 21, 217, 5, 0, // Skip to: 18070 /* 16573 */ MCD_OPC_CheckField, 19, 1, 1, 210, 5, 0, // Skip to: 18070 /* 16580 */ MCD_OPC_Decode, 163, 18, 166, 1, // Opcode: VSHRuv16i8 /* 16585 */ MCD_OPC_FilterValue, 1, 200, 5, 0, // Skip to: 18070 /* 16590 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16593 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16608 /* 16598 */ MCD_OPC_CheckPredicate, 21, 187, 5, 0, // Skip to: 18070 /* 16603 */ MCD_OPC_Decode, 161, 18, 167, 1, // Opcode: VSHRsv8i16 /* 16608 */ MCD_OPC_FilterValue, 1, 177, 5, 0, // Skip to: 18070 /* 16613 */ MCD_OPC_CheckPredicate, 21, 172, 5, 0, // Skip to: 18070 /* 16618 */ MCD_OPC_Decode, 169, 18, 167, 1, // Opcode: VSHRuv8i16 /* 16623 */ MCD_OPC_FilterValue, 1, 162, 5, 0, // Skip to: 18070 /* 16628 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16631 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16646 /* 16636 */ MCD_OPC_CheckPredicate, 21, 149, 5, 0, // Skip to: 18070 /* 16641 */ MCD_OPC_Decode, 160, 18, 168, 1, // Opcode: VSHRsv4i32 /* 16646 */ MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 18070 /* 16651 */ MCD_OPC_CheckPredicate, 21, 134, 5, 0, // Skip to: 18070 /* 16656 */ MCD_OPC_Decode, 168, 18, 168, 1, // Opcode: VSHRuv4i32 /* 16661 */ MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 16805 /* 16666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 16669 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16767 /* 16674 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 16677 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16729 /* 16682 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16685 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16707 /* 16690 */ MCD_OPC_CheckPredicate, 21, 95, 5, 0, // Skip to: 18070 /* 16695 */ MCD_OPC_CheckField, 19, 1, 1, 88, 5, 0, // Skip to: 18070 /* 16702 */ MCD_OPC_Decode, 191, 18, 169, 1, // Opcode: VSRAsv16i8 /* 16707 */ MCD_OPC_FilterValue, 1, 78, 5, 0, // Skip to: 18070 /* 16712 */ MCD_OPC_CheckPredicate, 21, 73, 5, 0, // Skip to: 18070 /* 16717 */ MCD_OPC_CheckField, 19, 1, 1, 66, 5, 0, // Skip to: 18070 /* 16724 */ MCD_OPC_Decode, 199, 18, 169, 1, // Opcode: VSRAuv16i8 /* 16729 */ MCD_OPC_FilterValue, 1, 56, 5, 0, // Skip to: 18070 /* 16734 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16752 /* 16742 */ MCD_OPC_CheckPredicate, 21, 43, 5, 0, // Skip to: 18070 /* 16747 */ MCD_OPC_Decode, 197, 18, 170, 1, // Opcode: VSRAsv8i16 /* 16752 */ MCD_OPC_FilterValue, 1, 33, 5, 0, // Skip to: 18070 /* 16757 */ MCD_OPC_CheckPredicate, 21, 28, 5, 0, // Skip to: 18070 /* 16762 */ MCD_OPC_Decode, 205, 18, 170, 1, // Opcode: VSRAuv8i16 /* 16767 */ MCD_OPC_FilterValue, 1, 18, 5, 0, // Skip to: 18070 /* 16772 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16790 /* 16780 */ MCD_OPC_CheckPredicate, 21, 5, 5, 0, // Skip to: 18070 /* 16785 */ MCD_OPC_Decode, 196, 18, 171, 1, // Opcode: VSRAsv4i32 /* 16790 */ MCD_OPC_FilterValue, 1, 251, 4, 0, // Skip to: 18070 /* 16795 */ MCD_OPC_CheckPredicate, 21, 246, 4, 0, // Skip to: 18070 /* 16800 */ MCD_OPC_Decode, 204, 18, 171, 1, // Opcode: VSRAuv4i32 /* 16805 */ MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 16949 /* 16810 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 16813 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16911 /* 16818 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 16821 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16873 /* 16826 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16829 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16851 /* 16834 */ MCD_OPC_CheckPredicate, 21, 207, 4, 0, // Skip to: 18070 /* 16839 */ MCD_OPC_CheckField, 19, 1, 1, 200, 4, 0, // Skip to: 18070 /* 16846 */ MCD_OPC_Decode, 183, 17, 166, 1, // Opcode: VRSHRsv16i8 /* 16851 */ MCD_OPC_FilterValue, 1, 190, 4, 0, // Skip to: 18070 /* 16856 */ MCD_OPC_CheckPredicate, 21, 185, 4, 0, // Skip to: 18070 /* 16861 */ MCD_OPC_CheckField, 19, 1, 1, 178, 4, 0, // Skip to: 18070 /* 16868 */ MCD_OPC_Decode, 191, 17, 166, 1, // Opcode: VRSHRuv16i8 /* 16873 */ MCD_OPC_FilterValue, 1, 168, 4, 0, // Skip to: 18070 /* 16878 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16881 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16896 /* 16886 */ MCD_OPC_CheckPredicate, 21, 155, 4, 0, // Skip to: 18070 /* 16891 */ MCD_OPC_Decode, 189, 17, 167, 1, // Opcode: VRSHRsv8i16 /* 16896 */ MCD_OPC_FilterValue, 1, 145, 4, 0, // Skip to: 18070 /* 16901 */ MCD_OPC_CheckPredicate, 21, 140, 4, 0, // Skip to: 18070 /* 16906 */ MCD_OPC_Decode, 197, 17, 167, 1, // Opcode: VRSHRuv8i16 /* 16911 */ MCD_OPC_FilterValue, 1, 130, 4, 0, // Skip to: 18070 /* 16916 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16919 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16934 /* 16924 */ MCD_OPC_CheckPredicate, 21, 117, 4, 0, // Skip to: 18070 /* 16929 */ MCD_OPC_Decode, 188, 17, 168, 1, // Opcode: VRSHRsv4i32 /* 16934 */ MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 18070 /* 16939 */ MCD_OPC_CheckPredicate, 21, 102, 4, 0, // Skip to: 18070 /* 16944 */ MCD_OPC_Decode, 196, 17, 168, 1, // Opcode: VRSHRuv4i32 /* 16949 */ MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 17093 /* 16954 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 16957 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17055 /* 16962 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 16965 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17017 /* 16970 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 16973 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16995 /* 16978 */ MCD_OPC_CheckPredicate, 21, 63, 4, 0, // Skip to: 18070 /* 16983 */ MCD_OPC_CheckField, 19, 1, 1, 56, 4, 0, // Skip to: 18070 /* 16990 */ MCD_OPC_Decode, 209, 17, 169, 1, // Opcode: VRSRAsv16i8 /* 16995 */ MCD_OPC_FilterValue, 1, 46, 4, 0, // Skip to: 18070 /* 17000 */ MCD_OPC_CheckPredicate, 21, 41, 4, 0, // Skip to: 18070 /* 17005 */ MCD_OPC_CheckField, 19, 1, 1, 34, 4, 0, // Skip to: 18070 /* 17012 */ MCD_OPC_Decode, 217, 17, 169, 1, // Opcode: VRSRAuv16i8 /* 17017 */ MCD_OPC_FilterValue, 1, 24, 4, 0, // Skip to: 18070 /* 17022 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17025 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17040 /* 17030 */ MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 18070 /* 17035 */ MCD_OPC_Decode, 215, 17, 170, 1, // Opcode: VRSRAsv8i16 /* 17040 */ MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 18070 /* 17045 */ MCD_OPC_CheckPredicate, 21, 252, 3, 0, // Skip to: 18070 /* 17050 */ MCD_OPC_Decode, 223, 17, 170, 1, // Opcode: VRSRAuv8i16 /* 17055 */ MCD_OPC_FilterValue, 1, 242, 3, 0, // Skip to: 18070 /* 17060 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17063 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17078 /* 17068 */ MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 18070 /* 17073 */ MCD_OPC_Decode, 214, 17, 171, 1, // Opcode: VRSRAsv4i32 /* 17078 */ MCD_OPC_FilterValue, 1, 219, 3, 0, // Skip to: 18070 /* 17083 */ MCD_OPC_CheckPredicate, 21, 214, 3, 0, // Skip to: 18070 /* 17088 */ MCD_OPC_Decode, 222, 17, 171, 1, // Opcode: VRSRAuv4i32 /* 17093 */ MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 17182 /* 17098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17101 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17160 /* 17106 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 17109 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17138 /* 17114 */ MCD_OPC_CheckPredicate, 21, 183, 3, 0, // Skip to: 18070 /* 17119 */ MCD_OPC_CheckField, 24, 1, 1, 176, 3, 0, // Skip to: 18070 /* 17126 */ MCD_OPC_CheckField, 19, 1, 1, 169, 3, 0, // Skip to: 18070 /* 17133 */ MCD_OPC_Decode, 207, 18, 169, 1, // Opcode: VSRIv16i8 /* 17138 */ MCD_OPC_FilterValue, 1, 159, 3, 0, // Skip to: 18070 /* 17143 */ MCD_OPC_CheckPredicate, 21, 154, 3, 0, // Skip to: 18070 /* 17148 */ MCD_OPC_CheckField, 24, 1, 1, 147, 3, 0, // Skip to: 18070 /* 17155 */ MCD_OPC_Decode, 213, 18, 170, 1, // Opcode: VSRIv8i16 /* 17160 */ MCD_OPC_FilterValue, 1, 137, 3, 0, // Skip to: 18070 /* 17165 */ MCD_OPC_CheckPredicate, 21, 132, 3, 0, // Skip to: 18070 /* 17170 */ MCD_OPC_CheckField, 24, 1, 1, 125, 3, 0, // Skip to: 18070 /* 17177 */ MCD_OPC_Decode, 212, 18, 171, 1, // Opcode: VSRIv4i32 /* 17182 */ MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 17326 /* 17187 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17190 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17288 /* 17195 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 17198 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17250 /* 17203 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17206 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17228 /* 17211 */ MCD_OPC_CheckPredicate, 21, 86, 3, 0, // Skip to: 18070 /* 17216 */ MCD_OPC_CheckField, 19, 1, 1, 79, 3, 0, // Skip to: 18070 /* 17223 */ MCD_OPC_Decode, 128, 18, 172, 1, // Opcode: VSHLiv16i8 /* 17228 */ MCD_OPC_FilterValue, 1, 69, 3, 0, // Skip to: 18070 /* 17233 */ MCD_OPC_CheckPredicate, 21, 64, 3, 0, // Skip to: 18070 /* 17238 */ MCD_OPC_CheckField, 19, 1, 1, 57, 3, 0, // Skip to: 18070 /* 17245 */ MCD_OPC_Decode, 177, 18, 173, 1, // Opcode: VSLIv16i8 /* 17250 */ MCD_OPC_FilterValue, 1, 47, 3, 0, // Skip to: 18070 /* 17255 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17258 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17273 /* 17263 */ MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 18070 /* 17268 */ MCD_OPC_Decode, 134, 18, 174, 1, // Opcode: VSHLiv8i16 /* 17273 */ MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 18070 /* 17278 */ MCD_OPC_CheckPredicate, 21, 19, 3, 0, // Skip to: 18070 /* 17283 */ MCD_OPC_Decode, 183, 18, 175, 1, // Opcode: VSLIv8i16 /* 17288 */ MCD_OPC_FilterValue, 1, 9, 3, 0, // Skip to: 18070 /* 17293 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17311 /* 17301 */ MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 18070 /* 17306 */ MCD_OPC_Decode, 133, 18, 176, 1, // Opcode: VSHLiv4i32 /* 17311 */ MCD_OPC_FilterValue, 1, 242, 2, 0, // Skip to: 18070 /* 17316 */ MCD_OPC_CheckPredicate, 21, 237, 2, 0, // Skip to: 18070 /* 17321 */ MCD_OPC_Decode, 182, 18, 177, 1, // Opcode: VSLIv4i32 /* 17326 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 17415 /* 17331 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17334 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17393 /* 17339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 17342 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17371 /* 17347 */ MCD_OPC_CheckPredicate, 21, 206, 2, 0, // Skip to: 18070 /* 17352 */ MCD_OPC_CheckField, 24, 1, 1, 199, 2, 0, // Skip to: 18070 /* 17359 */ MCD_OPC_CheckField, 19, 1, 1, 192, 2, 0, // Skip to: 18070 /* 17366 */ MCD_OPC_Decode, 153, 16, 172, 1, // Opcode: VQSHLsuv16i8 /* 17371 */ MCD_OPC_FilterValue, 1, 182, 2, 0, // Skip to: 18070 /* 17376 */ MCD_OPC_CheckPredicate, 21, 177, 2, 0, // Skip to: 18070 /* 17381 */ MCD_OPC_CheckField, 24, 1, 1, 170, 2, 0, // Skip to: 18070 /* 17388 */ MCD_OPC_Decode, 159, 16, 174, 1, // Opcode: VQSHLsuv8i16 /* 17393 */ MCD_OPC_FilterValue, 1, 160, 2, 0, // Skip to: 18070 /* 17398 */ MCD_OPC_CheckPredicate, 21, 155, 2, 0, // Skip to: 18070 /* 17403 */ MCD_OPC_CheckField, 24, 1, 1, 148, 2, 0, // Skip to: 18070 /* 17410 */ MCD_OPC_Decode, 158, 16, 176, 1, // Opcode: VQSHLsuv4i32 /* 17415 */ MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 17559 /* 17420 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17423 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17521 /* 17428 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 17431 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17483 /* 17436 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17439 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17461 /* 17444 */ MCD_OPC_CheckPredicate, 21, 109, 2, 0, // Skip to: 18070 /* 17449 */ MCD_OPC_CheckField, 19, 1, 1, 102, 2, 0, // Skip to: 18070 /* 17456 */ MCD_OPC_Decode, 145, 16, 172, 1, // Opcode: VQSHLsiv16i8 /* 17461 */ MCD_OPC_FilterValue, 1, 92, 2, 0, // Skip to: 18070 /* 17466 */ MCD_OPC_CheckPredicate, 21, 87, 2, 0, // Skip to: 18070 /* 17471 */ MCD_OPC_CheckField, 19, 1, 1, 80, 2, 0, // Skip to: 18070 /* 17478 */ MCD_OPC_Decode, 169, 16, 172, 1, // Opcode: VQSHLuiv16i8 /* 17483 */ MCD_OPC_FilterValue, 1, 70, 2, 0, // Skip to: 18070 /* 17488 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17491 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17506 /* 17496 */ MCD_OPC_CheckPredicate, 21, 57, 2, 0, // Skip to: 18070 /* 17501 */ MCD_OPC_Decode, 151, 16, 174, 1, // Opcode: VQSHLsiv8i16 /* 17506 */ MCD_OPC_FilterValue, 1, 47, 2, 0, // Skip to: 18070 /* 17511 */ MCD_OPC_CheckPredicate, 21, 42, 2, 0, // Skip to: 18070 /* 17516 */ MCD_OPC_Decode, 175, 16, 174, 1, // Opcode: VQSHLuiv8i16 /* 17521 */ MCD_OPC_FilterValue, 1, 32, 2, 0, // Skip to: 18070 /* 17526 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17529 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17544 /* 17534 */ MCD_OPC_CheckPredicate, 21, 19, 2, 0, // Skip to: 18070 /* 17539 */ MCD_OPC_Decode, 150, 16, 176, 1, // Opcode: VQSHLsiv4i32 /* 17544 */ MCD_OPC_FilterValue, 1, 9, 2, 0, // Skip to: 18070 /* 17549 */ MCD_OPC_CheckPredicate, 21, 4, 2, 0, // Skip to: 18070 /* 17554 */ MCD_OPC_Decode, 174, 16, 176, 1, // Opcode: VQSHLuiv4i32 /* 17559 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 17703 /* 17564 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17567 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17665 /* 17572 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 17575 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17627 /* 17580 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17583 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17605 /* 17588 */ MCD_OPC_CheckPredicate, 21, 221, 1, 0, // Skip to: 18070 /* 17593 */ MCD_OPC_CheckField, 19, 1, 1, 214, 1, 0, // Skip to: 18070 /* 17600 */ MCD_OPC_Decode, 182, 17, 154, 1, // Opcode: VRSHRNv8i8 /* 17605 */ MCD_OPC_FilterValue, 1, 204, 1, 0, // Skip to: 18070 /* 17610 */ MCD_OPC_CheckPredicate, 21, 199, 1, 0, // Skip to: 18070 /* 17615 */ MCD_OPC_CheckField, 19, 1, 1, 192, 1, 0, // Skip to: 18070 /* 17622 */ MCD_OPC_Decode, 144, 16, 154, 1, // Opcode: VQRSHRUNv8i8 /* 17627 */ MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 18070 /* 17632 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17635 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17650 /* 17640 */ MCD_OPC_CheckPredicate, 21, 169, 1, 0, // Skip to: 18070 /* 17645 */ MCD_OPC_Decode, 181, 17, 155, 1, // Opcode: VRSHRNv4i16 /* 17650 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 18070 /* 17655 */ MCD_OPC_CheckPredicate, 21, 154, 1, 0, // Skip to: 18070 /* 17660 */ MCD_OPC_Decode, 143, 16, 155, 1, // Opcode: VQRSHRUNv4i16 /* 17665 */ MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 18070 /* 17670 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17673 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17688 /* 17678 */ MCD_OPC_CheckPredicate, 21, 131, 1, 0, // Skip to: 18070 /* 17683 */ MCD_OPC_Decode, 180, 17, 156, 1, // Opcode: VRSHRNv2i32 /* 17688 */ MCD_OPC_FilterValue, 1, 121, 1, 0, // Skip to: 18070 /* 17693 */ MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 18070 /* 17698 */ MCD_OPC_Decode, 142, 16, 156, 1, // Opcode: VQRSHRUNv2i32 /* 17703 */ MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 17847 /* 17708 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 17711 */ MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17809 /* 17716 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 17719 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17771 /* 17724 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17727 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17749 /* 17732 */ MCD_OPC_CheckPredicate, 21, 77, 1, 0, // Skip to: 18070 /* 17737 */ MCD_OPC_CheckField, 19, 1, 1, 70, 1, 0, // Skip to: 18070 /* 17744 */ MCD_OPC_Decode, 138, 16, 154, 1, // Opcode: VQRSHRNsv8i8 /* 17749 */ MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 18070 /* 17754 */ MCD_OPC_CheckPredicate, 21, 55, 1, 0, // Skip to: 18070 /* 17759 */ MCD_OPC_CheckField, 19, 1, 1, 48, 1, 0, // Skip to: 18070 /* 17766 */ MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: VQRSHRNuv8i8 /* 17771 */ MCD_OPC_FilterValue, 1, 38, 1, 0, // Skip to: 18070 /* 17776 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17779 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17794 /* 17784 */ MCD_OPC_CheckPredicate, 21, 25, 1, 0, // Skip to: 18070 /* 17789 */ MCD_OPC_Decode, 137, 16, 155, 1, // Opcode: VQRSHRNsv4i16 /* 17794 */ MCD_OPC_FilterValue, 1, 15, 1, 0, // Skip to: 18070 /* 17799 */ MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 18070 /* 17804 */ MCD_OPC_Decode, 140, 16, 155, 1, // Opcode: VQRSHRNuv4i16 /* 17809 */ MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 18070 /* 17814 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17817 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17832 /* 17822 */ MCD_OPC_CheckPredicate, 21, 243, 0, 0, // Skip to: 18070 /* 17827 */ MCD_OPC_Decode, 136, 16, 156, 1, // Opcode: VQRSHRNsv2i32 /* 17832 */ MCD_OPC_FilterValue, 1, 233, 0, 0, // Skip to: 18070 /* 17837 */ MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 18070 /* 17842 */ MCD_OPC_Decode, 139, 16, 156, 1, // Opcode: VQRSHRNuv2i32 /* 17847 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 17885 /* 17852 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17855 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17870 /* 17860 */ MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 18070 /* 17865 */ MCD_OPC_Decode, 248, 9, 178, 1, // Opcode: VCVTxs2hq /* 17870 */ MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 18070 /* 17875 */ MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 18070 /* 17880 */ MCD_OPC_Decode, 252, 9, 178, 1, // Opcode: VCVTxu2hq /* 17885 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 17923 /* 17890 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17893 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17908 /* 17898 */ MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 18070 /* 17903 */ MCD_OPC_Decode, 234, 9, 178, 1, // Opcode: VCVTh2xsq /* 17908 */ MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 18070 /* 17913 */ MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 18070 /* 17918 */ MCD_OPC_Decode, 236, 9, 178, 1, // Opcode: VCVTh2xuq /* 17923 */ MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 18008 /* 17928 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 17931 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17953 /* 17936 */ MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 17975 /* 17941 */ MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 17975 /* 17948 */ MCD_OPC_Decode, 156, 14, 161, 1, // Opcode: VMOVv16i8 /* 17953 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 17975 /* 17958 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 17975 /* 17963 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 17975 /* 17970 */ MCD_OPC_Decode, 160, 14, 161, 1, // Opcode: VMOVv2i64 /* 17975 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 17978 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17993 /* 17983 */ MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 18070 /* 17988 */ MCD_OPC_Decode, 246, 9, 178, 1, // Opcode: VCVTxs2fq /* 17993 */ MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 18070 /* 17998 */ MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 18070 /* 18003 */ MCD_OPC_Decode, 250, 9, 178, 1, // Opcode: VCVTxu2fq /* 18008 */ MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 18070 /* 18013 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... /* 18016 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18031 /* 18021 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 18046 /* 18026 */ MCD_OPC_Decode, 225, 9, 178, 1, // Opcode: VCVTf2xsq /* 18031 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18046 /* 18036 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18046 /* 18041 */ MCD_OPC_Decode, 227, 9, 178, 1, // Opcode: VCVTf2xuq /* 18046 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 18070 /* 18051 */ MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 18070 /* 18058 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 18070 /* 18065 */ MCD_OPC_Decode, 161, 14, 161, 1, // Opcode: VMOVv4f32 /* 18070 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 18073 */ MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 18166 /* 18078 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... /* 18081 */ MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 18553 /* 18086 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 18089 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18111 /* 18094 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18156 /* 18099 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18156 /* 18106 */ MCD_OPC_Decode, 164, 14, 161, 1, // Opcode: VMOVv8i16 /* 18111 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18156 /* 18116 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 18119 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18134 /* 18124 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18156 /* 18129 */ MCD_OPC_Decode, 247, 14, 161, 1, // Opcode: VORRiv4i32 /* 18134 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18156 /* 18139 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18156 /* 18144 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18156 /* 18151 */ MCD_OPC_Decode, 248, 14, 161, 1, // Opcode: VORRiv8i16 /* 18156 */ MCD_OPC_CheckPredicate, 21, 136, 1, 0, // Skip to: 18553 /* 18161 */ MCD_OPC_Decode, 163, 14, 161, 1, // Opcode: VMOVv4i32 /* 18166 */ MCD_OPC_FilterValue, 1, 126, 1, 0, // Skip to: 18553 /* 18171 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... /* 18174 */ MCD_OPC_FilterValue, 0, 118, 1, 0, // Skip to: 18553 /* 18179 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 18182 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18204 /* 18187 */ MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18249 /* 18192 */ MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18249 /* 18199 */ MCD_OPC_Decode, 219, 14, 161, 1, // Opcode: VMVNv8i16 /* 18204 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18249 /* 18209 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 18212 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18227 /* 18217 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18249 /* 18222 */ MCD_OPC_Decode, 142, 8, 161, 1, // Opcode: VBICiv4i32 /* 18227 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18249 /* 18232 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18249 /* 18237 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18249 /* 18244 */ MCD_OPC_Decode, 143, 8, 161, 1, // Opcode: VBICiv8i16 /* 18249 */ MCD_OPC_CheckPredicate, 21, 43, 1, 0, // Skip to: 18553 /* 18254 */ MCD_OPC_Decode, 218, 14, 161, 1, // Opcode: VMVNv4i32 /* 18259 */ MCD_OPC_FilterValue, 1, 33, 1, 0, // Skip to: 18553 /* 18264 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 18267 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 18307 /* 18272 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 18275 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18291 /* 18281 */ MCD_OPC_CheckPredicate, 21, 11, 1, 0, // Skip to: 18553 /* 18286 */ MCD_OPC_Decode, 158, 18, 179, 1, // Opcode: VSHRsv2i64 /* 18291 */ MCD_OPC_FilterValue, 243, 1, 0, 1, 0, // Skip to: 18553 /* 18297 */ MCD_OPC_CheckPredicate, 21, 251, 0, 0, // Skip to: 18553 /* 18302 */ MCD_OPC_Decode, 166, 18, 179, 1, // Opcode: VSHRuv2i64 /* 18307 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 18347 /* 18312 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 18315 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18331 /* 18321 */ MCD_OPC_CheckPredicate, 21, 227, 0, 0, // Skip to: 18553 /* 18326 */ MCD_OPC_Decode, 194, 18, 180, 1, // Opcode: VSRAsv2i64 /* 18331 */ MCD_OPC_FilterValue, 243, 1, 216, 0, 0, // Skip to: 18553 /* 18337 */ MCD_OPC_CheckPredicate, 21, 211, 0, 0, // Skip to: 18553 /* 18342 */ MCD_OPC_Decode, 202, 18, 180, 1, // Opcode: VSRAuv2i64 /* 18347 */ MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 18387 /* 18352 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 18355 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18371 /* 18361 */ MCD_OPC_CheckPredicate, 21, 187, 0, 0, // Skip to: 18553 /* 18366 */ MCD_OPC_Decode, 186, 17, 179, 1, // Opcode: VRSHRsv2i64 /* 18371 */ MCD_OPC_FilterValue, 243, 1, 176, 0, 0, // Skip to: 18553 /* 18377 */ MCD_OPC_CheckPredicate, 21, 171, 0, 0, // Skip to: 18553 /* 18382 */ MCD_OPC_Decode, 194, 17, 179, 1, // Opcode: VRSHRuv2i64 /* 18387 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 18427 /* 18392 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 18395 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18411 /* 18401 */ MCD_OPC_CheckPredicate, 21, 147, 0, 0, // Skip to: 18553 /* 18406 */ MCD_OPC_Decode, 212, 17, 180, 1, // Opcode: VRSRAsv2i64 /* 18411 */ MCD_OPC_FilterValue, 243, 1, 136, 0, 0, // Skip to: 18553 /* 18417 */ MCD_OPC_CheckPredicate, 21, 131, 0, 0, // Skip to: 18553 /* 18422 */ MCD_OPC_Decode, 220, 17, 180, 1, // Opcode: VRSRAuv2i64 /* 18427 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 18450 /* 18432 */ MCD_OPC_CheckPredicate, 21, 116, 0, 0, // Skip to: 18553 /* 18437 */ MCD_OPC_CheckField, 24, 8, 243, 1, 108, 0, 0, // Skip to: 18553 /* 18445 */ MCD_OPC_Decode, 210, 18, 180, 1, // Opcode: VSRIv2i64 /* 18450 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 18490 /* 18455 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 18458 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18474 /* 18464 */ MCD_OPC_CheckPredicate, 21, 84, 0, 0, // Skip to: 18553 /* 18469 */ MCD_OPC_Decode, 131, 18, 181, 1, // Opcode: VSHLiv2i64 /* 18474 */ MCD_OPC_FilterValue, 243, 1, 73, 0, 0, // Skip to: 18553 /* 18480 */ MCD_OPC_CheckPredicate, 21, 68, 0, 0, // Skip to: 18553 /* 18485 */ MCD_OPC_Decode, 180, 18, 182, 1, // Opcode: VSLIv2i64 /* 18490 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 18513 /* 18495 */ MCD_OPC_CheckPredicate, 21, 53, 0, 0, // Skip to: 18553 /* 18500 */ MCD_OPC_CheckField, 24, 8, 243, 1, 45, 0, 0, // Skip to: 18553 /* 18508 */ MCD_OPC_Decode, 156, 16, 181, 1, // Opcode: VQSHLsuv2i64 /* 18513 */ MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 18553 /* 18518 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 18521 */ MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18537 /* 18527 */ MCD_OPC_CheckPredicate, 21, 21, 0, 0, // Skip to: 18553 /* 18532 */ MCD_OPC_Decode, 148, 16, 181, 1, // Opcode: VQSHLsiv2i64 /* 18537 */ MCD_OPC_FilterValue, 243, 1, 10, 0, 0, // Skip to: 18553 /* 18543 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18553 /* 18548 */ MCD_OPC_Decode, 172, 16, 181, 1, // Opcode: VQSHLuiv2i64 /* 18553 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableNEONDup32[] = { /* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ... /* 3 */ MCD_OPC_FilterValue, 56, 121, 0, 0, // Skip to: 129 /* 8 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 11 */ MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 77 /* 16 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 19 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 48 /* 24 */ MCD_OPC_CheckPredicate, 27, 183, 1, 0, // Skip to: 468 /* 29 */ MCD_OPC_CheckField, 8, 4, 11, 176, 1, 0, // Skip to: 468 /* 36 */ MCD_OPC_CheckField, 6, 1, 0, 169, 1, 0, // Skip to: 468 /* 43 */ MCD_OPC_Decode, 245, 17, 183, 1, // Opcode: VSETLNi32 /* 48 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 468 /* 53 */ MCD_OPC_CheckPredicate, 27, 154, 1, 0, // Skip to: 468 /* 58 */ MCD_OPC_CheckField, 8, 4, 11, 147, 1, 0, // Skip to: 468 /* 65 */ MCD_OPC_CheckField, 6, 1, 0, 140, 1, 0, // Skip to: 468 /* 72 */ MCD_OPC_Decode, 169, 10, 184, 1, // Opcode: VGETLNi32 /* 77 */ MCD_OPC_FilterValue, 48, 130, 1, 0, // Skip to: 468 /* 82 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 85 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 107 /* 90 */ MCD_OPC_CheckPredicate, 21, 117, 1, 0, // Skip to: 468 /* 95 */ MCD_OPC_CheckField, 8, 4, 11, 110, 1, 0, // Skip to: 468 /* 102 */ MCD_OPC_Decode, 244, 17, 185, 1, // Opcode: VSETLNi16 /* 107 */ MCD_OPC_FilterValue, 1, 100, 1, 0, // Skip to: 468 /* 112 */ MCD_OPC_CheckPredicate, 21, 95, 1, 0, // Skip to: 468 /* 117 */ MCD_OPC_CheckField, 8, 4, 11, 88, 1, 0, // Skip to: 468 /* 124 */ MCD_OPC_Decode, 170, 10, 186, 1, // Opcode: VGETLNs16 /* 129 */ MCD_OPC_FilterValue, 57, 61, 0, 0, // Skip to: 195 /* 134 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 137 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 166 /* 142 */ MCD_OPC_CheckPredicate, 21, 65, 1, 0, // Skip to: 468 /* 147 */ MCD_OPC_CheckField, 8, 4, 11, 58, 1, 0, // Skip to: 468 /* 154 */ MCD_OPC_CheckField, 0, 5, 16, 51, 1, 0, // Skip to: 468 /* 161 */ MCD_OPC_Decode, 246, 17, 187, 1, // Opcode: VSETLNi8 /* 166 */ MCD_OPC_FilterValue, 1, 41, 1, 0, // Skip to: 468 /* 171 */ MCD_OPC_CheckPredicate, 21, 36, 1, 0, // Skip to: 468 /* 176 */ MCD_OPC_CheckField, 8, 4, 11, 29, 1, 0, // Skip to: 468 /* 183 */ MCD_OPC_CheckField, 0, 5, 16, 22, 1, 0, // Skip to: 468 /* 190 */ MCD_OPC_Decode, 171, 10, 188, 1, // Opcode: VGETLNs8 /* 195 */ MCD_OPC_FilterValue, 58, 165, 0, 0, // Skip to: 365 /* 200 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 203 */ MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 269 /* 208 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 211 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 240 /* 216 */ MCD_OPC_CheckPredicate, 21, 247, 0, 0, // Skip to: 468 /* 221 */ MCD_OPC_CheckField, 8, 4, 11, 240, 0, 0, // Skip to: 468 /* 228 */ MCD_OPC_CheckField, 6, 1, 0, 233, 0, 0, // Skip to: 468 /* 235 */ MCD_OPC_Decode, 130, 10, 189, 1, // Opcode: VDUP32d /* 240 */ MCD_OPC_FilterValue, 2, 223, 0, 0, // Skip to: 468 /* 245 */ MCD_OPC_CheckPredicate, 21, 218, 0, 0, // Skip to: 468 /* 250 */ MCD_OPC_CheckField, 8, 4, 11, 211, 0, 0, // Skip to: 468 /* 257 */ MCD_OPC_CheckField, 6, 1, 0, 204, 0, 0, // Skip to: 468 /* 264 */ MCD_OPC_Decode, 131, 10, 190, 1, // Opcode: VDUP32q /* 269 */ MCD_OPC_FilterValue, 48, 194, 0, 0, // Skip to: 468 /* 274 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 277 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 343 /* 282 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 285 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 314 /* 290 */ MCD_OPC_CheckPredicate, 21, 173, 0, 0, // Skip to: 468 /* 295 */ MCD_OPC_CheckField, 8, 4, 11, 166, 0, 0, // Skip to: 468 /* 302 */ MCD_OPC_CheckField, 6, 1, 0, 159, 0, 0, // Skip to: 468 /* 309 */ MCD_OPC_Decode, 128, 10, 189, 1, // Opcode: VDUP16d /* 314 */ MCD_OPC_FilterValue, 1, 149, 0, 0, // Skip to: 468 /* 319 */ MCD_OPC_CheckPredicate, 21, 144, 0, 0, // Skip to: 468 /* 324 */ MCD_OPC_CheckField, 8, 4, 11, 137, 0, 0, // Skip to: 468 /* 331 */ MCD_OPC_CheckField, 6, 1, 0, 130, 0, 0, // Skip to: 468 /* 338 */ MCD_OPC_Decode, 129, 10, 190, 1, // Opcode: VDUP16q /* 343 */ MCD_OPC_FilterValue, 1, 120, 0, 0, // Skip to: 468 /* 348 */ MCD_OPC_CheckPredicate, 21, 115, 0, 0, // Skip to: 468 /* 353 */ MCD_OPC_CheckField, 8, 4, 11, 108, 0, 0, // Skip to: 468 /* 360 */ MCD_OPC_Decode, 172, 10, 186, 1, // Opcode: VGETLNu16 /* 365 */ MCD_OPC_FilterValue, 59, 98, 0, 0, // Skip to: 468 /* 370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 373 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 439 /* 378 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 381 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 410 /* 386 */ MCD_OPC_CheckPredicate, 21, 77, 0, 0, // Skip to: 468 /* 391 */ MCD_OPC_CheckField, 8, 4, 11, 70, 0, 0, // Skip to: 468 /* 398 */ MCD_OPC_CheckField, 0, 7, 16, 63, 0, 0, // Skip to: 468 /* 405 */ MCD_OPC_Decode, 132, 10, 189, 1, // Opcode: VDUP8d /* 410 */ MCD_OPC_FilterValue, 1, 53, 0, 0, // Skip to: 468 /* 415 */ MCD_OPC_CheckPredicate, 21, 48, 0, 0, // Skip to: 468 /* 420 */ MCD_OPC_CheckField, 8, 4, 11, 41, 0, 0, // Skip to: 468 /* 427 */ MCD_OPC_CheckField, 0, 7, 16, 34, 0, 0, // Skip to: 468 /* 434 */ MCD_OPC_Decode, 133, 10, 190, 1, // Opcode: VDUP8q /* 439 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 468 /* 444 */ MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 468 /* 449 */ MCD_OPC_CheckField, 8, 4, 11, 12, 0, 0, // Skip to: 468 /* 456 */ MCD_OPC_CheckField, 0, 5, 16, 5, 0, 0, // Skip to: 468 /* 463 */ MCD_OPC_Decode, 173, 10, 188, 1, // Opcode: VGETLNu8 /* 468 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableNEONLoadStore32[] = { /* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 3 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 319 /* 8 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 11 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 165 /* 16 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 19 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 124 /* 25 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 28 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 60 /* 33 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 50 /* 38 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 50 /* 45 */ MCD_OPC_Decode, 178, 20, 191, 1, // Opcode: VST4d8 /* 50 */ MCD_OPC_CheckPredicate, 21, 246, 25, 0, // Skip to: 6701 /* 55 */ MCD_OPC_Decode, 181, 20, 191, 1, // Opcode: VST4d8_UPD /* 60 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 92 /* 65 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 82 /* 70 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 82 /* 77 */ MCD_OPC_Decode, 170, 20, 191, 1, // Opcode: VST4d16 /* 82 */ MCD_OPC_CheckPredicate, 21, 214, 25, 0, // Skip to: 6701 /* 87 */ MCD_OPC_Decode, 173, 20, 191, 1, // Opcode: VST4d16_UPD /* 92 */ MCD_OPC_FilterValue, 2, 204, 25, 0, // Skip to: 6701 /* 97 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 114 /* 102 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 114 /* 109 */ MCD_OPC_Decode, 174, 20, 191, 1, // Opcode: VST4d32 /* 114 */ MCD_OPC_CheckPredicate, 21, 182, 25, 0, // Skip to: 6701 /* 119 */ MCD_OPC_Decode, 177, 20, 191, 1, // Opcode: VST4d32_UPD /* 124 */ MCD_OPC_FilterValue, 233, 3, 171, 25, 0, // Skip to: 6701 /* 130 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 133 */ MCD_OPC_FilterValue, 0, 163, 25, 0, // Skip to: 6701 /* 138 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 155 /* 143 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 155 /* 150 */ MCD_OPC_Decode, 219, 18, 192, 1, // Opcode: VST1LNd8 /* 155 */ MCD_OPC_CheckPredicate, 21, 141, 25, 0, // Skip to: 6701 /* 160 */ MCD_OPC_Decode, 220, 18, 192, 1, // Opcode: VST1LNd8_UPD /* 165 */ MCD_OPC_FilterValue, 2, 131, 25, 0, // Skip to: 6701 /* 170 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 173 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 278 /* 179 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 182 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 214 /* 187 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 204 /* 192 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 204 /* 199 */ MCD_OPC_Decode, 253, 12, 191, 1, // Opcode: VLD4d8 /* 204 */ MCD_OPC_CheckPredicate, 21, 92, 25, 0, // Skip to: 6701 /* 209 */ MCD_OPC_Decode, 128, 13, 191, 1, // Opcode: VLD4d8_UPD /* 214 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 246 /* 219 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 236 /* 224 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 236 /* 231 */ MCD_OPC_Decode, 245, 12, 191, 1, // Opcode: VLD4d16 /* 236 */ MCD_OPC_CheckPredicate, 21, 60, 25, 0, // Skip to: 6701 /* 241 */ MCD_OPC_Decode, 248, 12, 191, 1, // Opcode: VLD4d16_UPD /* 246 */ MCD_OPC_FilterValue, 2, 50, 25, 0, // Skip to: 6701 /* 251 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 268 /* 256 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 268 /* 263 */ MCD_OPC_Decode, 249, 12, 191, 1, // Opcode: VLD4d32 /* 268 */ MCD_OPC_CheckPredicate, 21, 28, 25, 0, // Skip to: 6701 /* 273 */ MCD_OPC_Decode, 252, 12, 191, 1, // Opcode: VLD4d32_UPD /* 278 */ MCD_OPC_FilterValue, 233, 3, 17, 25, 0, // Skip to: 6701 /* 284 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 287 */ MCD_OPC_FilterValue, 0, 9, 25, 0, // Skip to: 6701 /* 292 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 309 /* 297 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 309 /* 304 */ MCD_OPC_Decode, 222, 10, 193, 1, // Opcode: VLD1LNd8 /* 309 */ MCD_OPC_CheckPredicate, 21, 243, 24, 0, // Skip to: 6701 /* 314 */ MCD_OPC_Decode, 223, 10, 193, 1, // Opcode: VLD1LNd8_UPD /* 319 */ MCD_OPC_FilterValue, 1, 39, 1, 0, // Skip to: 619 /* 324 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 327 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 473 /* 332 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 335 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 440 /* 341 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 344 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 376 /* 349 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 366 /* 354 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 366 /* 361 */ MCD_OPC_Decode, 192, 20, 191, 1, // Opcode: VST4q8 /* 366 */ MCD_OPC_CheckPredicate, 21, 186, 24, 0, // Skip to: 6701 /* 371 */ MCD_OPC_Decode, 194, 20, 191, 1, // Opcode: VST4q8_UPD /* 376 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 408 /* 381 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 398 /* 386 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 398 /* 393 */ MCD_OPC_Decode, 182, 20, 191, 1, // Opcode: VST4q16 /* 398 */ MCD_OPC_CheckPredicate, 21, 154, 24, 0, // Skip to: 6701 /* 403 */ MCD_OPC_Decode, 184, 20, 191, 1, // Opcode: VST4q16_UPD /* 408 */ MCD_OPC_FilterValue, 2, 144, 24, 0, // Skip to: 6701 /* 413 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 430 /* 418 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 430 /* 425 */ MCD_OPC_Decode, 187, 20, 191, 1, // Opcode: VST4q32 /* 430 */ MCD_OPC_CheckPredicate, 21, 122, 24, 0, // Skip to: 6701 /* 435 */ MCD_OPC_Decode, 189, 20, 191, 1, // Opcode: VST4q32_UPD /* 440 */ MCD_OPC_FilterValue, 233, 3, 111, 24, 0, // Skip to: 6701 /* 446 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 463 /* 451 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 463 /* 458 */ MCD_OPC_Decode, 183, 19, 194, 1, // Opcode: VST2LNd8 /* 463 */ MCD_OPC_CheckPredicate, 21, 89, 24, 0, // Skip to: 6701 /* 468 */ MCD_OPC_Decode, 186, 19, 194, 1, // Opcode: VST2LNd8_UPD /* 473 */ MCD_OPC_FilterValue, 2, 79, 24, 0, // Skip to: 6701 /* 478 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 481 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 586 /* 487 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 490 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 522 /* 495 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 512 /* 500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 512 /* 507 */ MCD_OPC_Decode, 139, 13, 191, 1, // Opcode: VLD4q8 /* 512 */ MCD_OPC_CheckPredicate, 21, 40, 24, 0, // Skip to: 6701 /* 517 */ MCD_OPC_Decode, 141, 13, 191, 1, // Opcode: VLD4q8_UPD /* 522 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 554 /* 527 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 544 /* 532 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 544 /* 539 */ MCD_OPC_Decode, 129, 13, 191, 1, // Opcode: VLD4q16 /* 544 */ MCD_OPC_CheckPredicate, 21, 8, 24, 0, // Skip to: 6701 /* 549 */ MCD_OPC_Decode, 131, 13, 191, 1, // Opcode: VLD4q16_UPD /* 554 */ MCD_OPC_FilterValue, 2, 254, 23, 0, // Skip to: 6701 /* 559 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 576 /* 564 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 576 /* 571 */ MCD_OPC_Decode, 134, 13, 191, 1, // Opcode: VLD4q32 /* 576 */ MCD_OPC_CheckPredicate, 21, 232, 23, 0, // Skip to: 6701 /* 581 */ MCD_OPC_Decode, 136, 13, 191, 1, // Opcode: VLD4q32_UPD /* 586 */ MCD_OPC_FilterValue, 233, 3, 221, 23, 0, // Skip to: 6701 /* 592 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 609 /* 597 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 609 /* 604 */ MCD_OPC_Decode, 210, 11, 195, 1, // Opcode: VLD2LNd8 /* 609 */ MCD_OPC_CheckPredicate, 21, 199, 23, 0, // Skip to: 6701 /* 614 */ MCD_OPC_Decode, 213, 11, 195, 1, // Opcode: VLD2LNd8_UPD /* 619 */ MCD_OPC_FilterValue, 2, 247, 1, 0, // Skip to: 1127 /* 624 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 627 */ MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 877 /* 632 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 635 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 836 /* 641 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 644 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 692 /* 649 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 652 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 667 /* 657 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 682 /* 662 */ MCD_OPC_Decode, 139, 19, 196, 1, // Opcode: VST1d8Qwb_fixed /* 667 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 682 /* 672 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 682 /* 677 */ MCD_OPC_Decode, 137, 19, 196, 1, // Opcode: VST1d8Q /* 682 */ MCD_OPC_CheckPredicate, 21, 126, 23, 0, // Skip to: 6701 /* 687 */ MCD_OPC_Decode, 140, 19, 196, 1, // Opcode: VST1d8Qwb_register /* 692 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 740 /* 697 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 700 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 715 /* 705 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 730 /* 710 */ MCD_OPC_Decode, 230, 18, 196, 1, // Opcode: VST1d16Qwb_fixed /* 715 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 730 /* 720 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 730 /* 725 */ MCD_OPC_Decode, 228, 18, 196, 1, // Opcode: VST1d16Q /* 730 */ MCD_OPC_CheckPredicate, 21, 78, 23, 0, // Skip to: 6701 /* 735 */ MCD_OPC_Decode, 231, 18, 196, 1, // Opcode: VST1d16Qwb_register /* 740 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 788 /* 745 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 748 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 763 /* 753 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 778 /* 758 */ MCD_OPC_Decode, 241, 18, 196, 1, // Opcode: VST1d32Qwb_fixed /* 763 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 778 /* 768 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 778 /* 773 */ MCD_OPC_Decode, 239, 18, 196, 1, // Opcode: VST1d32Q /* 778 */ MCD_OPC_CheckPredicate, 21, 30, 23, 0, // Skip to: 6701 /* 783 */ MCD_OPC_Decode, 242, 18, 196, 1, // Opcode: VST1d32Qwb_register /* 788 */ MCD_OPC_FilterValue, 3, 20, 23, 0, // Skip to: 6701 /* 793 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 796 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 811 /* 801 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 826 /* 806 */ MCD_OPC_Decode, 254, 18, 196, 1, // Opcode: VST1d64Qwb_fixed /* 811 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 826 /* 816 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 826 /* 821 */ MCD_OPC_Decode, 250, 18, 196, 1, // Opcode: VST1d64Q /* 826 */ MCD_OPC_CheckPredicate, 21, 238, 22, 0, // Skip to: 6701 /* 831 */ MCD_OPC_Decode, 255, 18, 196, 1, // Opcode: VST1d64Qwb_register /* 836 */ MCD_OPC_FilterValue, 233, 3, 227, 22, 0, // Skip to: 6701 /* 842 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 845 */ MCD_OPC_FilterValue, 0, 219, 22, 0, // Skip to: 6701 /* 850 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 867 /* 855 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 867 /* 862 */ MCD_OPC_Decode, 239, 19, 197, 1, // Opcode: VST3LNd8 /* 867 */ MCD_OPC_CheckPredicate, 21, 197, 22, 0, // Skip to: 6701 /* 872 */ MCD_OPC_Decode, 242, 19, 197, 1, // Opcode: VST3LNd8_UPD /* 877 */ MCD_OPC_FilterValue, 2, 187, 22, 0, // Skip to: 6701 /* 882 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 885 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 1086 /* 891 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 894 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 942 /* 899 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 902 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 917 /* 907 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 932 /* 912 */ MCD_OPC_Decode, 142, 11, 196, 1, // Opcode: VLD1d8Qwb_fixed /* 917 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 932 /* 922 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 932 /* 927 */ MCD_OPC_Decode, 140, 11, 196, 1, // Opcode: VLD1d8Q /* 932 */ MCD_OPC_CheckPredicate, 21, 132, 22, 0, // Skip to: 6701 /* 937 */ MCD_OPC_Decode, 143, 11, 196, 1, // Opcode: VLD1d8Qwb_register /* 942 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 990 /* 947 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 950 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 965 /* 955 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 980 /* 960 */ MCD_OPC_Decode, 233, 10, 196, 1, // Opcode: VLD1d16Qwb_fixed /* 965 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 980 /* 970 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 980 /* 975 */ MCD_OPC_Decode, 231, 10, 196, 1, // Opcode: VLD1d16Q /* 980 */ MCD_OPC_CheckPredicate, 21, 84, 22, 0, // Skip to: 6701 /* 985 */ MCD_OPC_Decode, 234, 10, 196, 1, // Opcode: VLD1d16Qwb_register /* 990 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 1038 /* 995 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 998 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1013 /* 1003 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1028 /* 1008 */ MCD_OPC_Decode, 244, 10, 196, 1, // Opcode: VLD1d32Qwb_fixed /* 1013 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1028 /* 1018 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1028 /* 1023 */ MCD_OPC_Decode, 242, 10, 196, 1, // Opcode: VLD1d32Q /* 1028 */ MCD_OPC_CheckPredicate, 21, 36, 22, 0, // Skip to: 6701 /* 1033 */ MCD_OPC_Decode, 245, 10, 196, 1, // Opcode: VLD1d32Qwb_register /* 1038 */ MCD_OPC_FilterValue, 3, 26, 22, 0, // Skip to: 6701 /* 1043 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1046 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1061 /* 1051 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1076 /* 1056 */ MCD_OPC_Decode, 129, 11, 196, 1, // Opcode: VLD1d64Qwb_fixed /* 1061 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1076 /* 1066 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1076 /* 1071 */ MCD_OPC_Decode, 253, 10, 196, 1, // Opcode: VLD1d64Q /* 1076 */ MCD_OPC_CheckPredicate, 21, 244, 21, 0, // Skip to: 6701 /* 1081 */ MCD_OPC_Decode, 130, 11, 196, 1, // Opcode: VLD1d64Qwb_register /* 1086 */ MCD_OPC_FilterValue, 233, 3, 233, 21, 0, // Skip to: 6701 /* 1092 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1095 */ MCD_OPC_FilterValue, 0, 225, 21, 0, // Skip to: 6701 /* 1100 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1117 /* 1105 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1117 /* 1112 */ MCD_OPC_Decode, 162, 12, 198, 1, // Opcode: VLD3LNd8 /* 1117 */ MCD_OPC_CheckPredicate, 21, 203, 21, 0, // Skip to: 6701 /* 1122 */ MCD_OPC_Decode, 165, 12, 198, 1, // Opcode: VLD3LNd8_UPD /* 1127 */ MCD_OPC_FilterValue, 3, 135, 1, 0, // Skip to: 1523 /* 1132 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 1135 */ MCD_OPC_FilterValue, 0, 189, 0, 0, // Skip to: 1329 /* 1140 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1143 */ MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1296 /* 1149 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1152 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1200 /* 1157 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1160 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1175 /* 1165 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1190 /* 1170 */ MCD_OPC_Decode, 229, 19, 199, 1, // Opcode: VST2q8wb_fixed /* 1175 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1190 /* 1180 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1190 /* 1185 */ MCD_OPC_Decode, 225, 19, 199, 1, // Opcode: VST2q8 /* 1190 */ MCD_OPC_CheckPredicate, 21, 130, 21, 0, // Skip to: 6701 /* 1195 */ MCD_OPC_Decode, 230, 19, 199, 1, // Opcode: VST2q8wb_register /* 1200 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1248 /* 1205 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1208 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1223 /* 1213 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1238 /* 1218 */ MCD_OPC_Decode, 217, 19, 199, 1, // Opcode: VST2q16wb_fixed /* 1223 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1238 /* 1228 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1238 /* 1233 */ MCD_OPC_Decode, 213, 19, 199, 1, // Opcode: VST2q16 /* 1238 */ MCD_OPC_CheckPredicate, 21, 82, 21, 0, // Skip to: 6701 /* 1243 */ MCD_OPC_Decode, 218, 19, 199, 1, // Opcode: VST2q16wb_register /* 1248 */ MCD_OPC_FilterValue, 2, 72, 21, 0, // Skip to: 6701 /* 1253 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1256 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1271 /* 1261 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1286 /* 1266 */ MCD_OPC_Decode, 223, 19, 199, 1, // Opcode: VST2q32wb_fixed /* 1271 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1286 /* 1276 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1286 /* 1281 */ MCD_OPC_Decode, 219, 19, 199, 1, // Opcode: VST2q32 /* 1286 */ MCD_OPC_CheckPredicate, 21, 34, 21, 0, // Skip to: 6701 /* 1291 */ MCD_OPC_Decode, 224, 19, 199, 1, // Opcode: VST2q32wb_register /* 1296 */ MCD_OPC_FilterValue, 233, 3, 23, 21, 0, // Skip to: 6701 /* 1302 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1319 /* 1307 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1319 /* 1314 */ MCD_OPC_Decode, 158, 20, 200, 1, // Opcode: VST4LNd8 /* 1319 */ MCD_OPC_CheckPredicate, 21, 1, 21, 0, // Skip to: 6701 /* 1324 */ MCD_OPC_Decode, 161, 20, 200, 1, // Opcode: VST4LNd8_UPD /* 1329 */ MCD_OPC_FilterValue, 2, 247, 20, 0, // Skip to: 6701 /* 1334 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1337 */ MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1490 /* 1343 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1346 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1394 /* 1351 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1354 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1369 /* 1359 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1384 /* 1364 */ MCD_OPC_Decode, 128, 12, 199, 1, // Opcode: VLD2q8wb_fixed /* 1369 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1384 /* 1374 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1384 /* 1379 */ MCD_OPC_Decode, 252, 11, 199, 1, // Opcode: VLD2q8 /* 1384 */ MCD_OPC_CheckPredicate, 21, 192, 20, 0, // Skip to: 6701 /* 1389 */ MCD_OPC_Decode, 129, 12, 199, 1, // Opcode: VLD2q8wb_register /* 1394 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1442 /* 1399 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1402 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1417 /* 1407 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1432 /* 1412 */ MCD_OPC_Decode, 244, 11, 199, 1, // Opcode: VLD2q16wb_fixed /* 1417 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1432 /* 1422 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1432 /* 1427 */ MCD_OPC_Decode, 240, 11, 199, 1, // Opcode: VLD2q16 /* 1432 */ MCD_OPC_CheckPredicate, 21, 144, 20, 0, // Skip to: 6701 /* 1437 */ MCD_OPC_Decode, 245, 11, 199, 1, // Opcode: VLD2q16wb_register /* 1442 */ MCD_OPC_FilterValue, 2, 134, 20, 0, // Skip to: 6701 /* 1447 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 1450 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1465 /* 1455 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1480 /* 1460 */ MCD_OPC_Decode, 250, 11, 199, 1, // Opcode: VLD2q32wb_fixed /* 1465 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1480 /* 1470 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1480 /* 1475 */ MCD_OPC_Decode, 246, 11, 199, 1, // Opcode: VLD2q32 /* 1480 */ MCD_OPC_CheckPredicate, 21, 96, 20, 0, // Skip to: 6701 /* 1485 */ MCD_OPC_Decode, 251, 11, 199, 1, // Opcode: VLD2q32wb_register /* 1490 */ MCD_OPC_FilterValue, 233, 3, 85, 20, 0, // Skip to: 6701 /* 1496 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1513 /* 1501 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1513 /* 1508 */ MCD_OPC_Decode, 233, 12, 201, 1, // Opcode: VLD4LNd8 /* 1513 */ MCD_OPC_CheckPredicate, 21, 63, 20, 0, // Skip to: 6701 /* 1518 */ MCD_OPC_Decode, 236, 12, 201, 1, // Opcode: VLD4LNd8_UPD /* 1523 */ MCD_OPC_FilterValue, 4, 54, 1, 0, // Skip to: 1838 /* 1528 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 1531 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 1685 /* 1536 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1539 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1644 /* 1545 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 1548 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1580 /* 1553 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1570 /* 1558 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1570 /* 1565 */ MCD_OPC_Decode, 131, 20, 202, 1, // Opcode: VST3d8 /* 1570 */ MCD_OPC_CheckPredicate, 21, 6, 20, 0, // Skip to: 6701 /* 1575 */ MCD_OPC_Decode, 134, 20, 202, 1, // Opcode: VST3d8_UPD /* 1580 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1612 /* 1585 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1602 /* 1590 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1602 /* 1597 */ MCD_OPC_Decode, 251, 19, 202, 1, // Opcode: VST3d16 /* 1602 */ MCD_OPC_CheckPredicate, 21, 230, 19, 0, // Skip to: 6701 /* 1607 */ MCD_OPC_Decode, 254, 19, 202, 1, // Opcode: VST3d16_UPD /* 1612 */ MCD_OPC_FilterValue, 4, 220, 19, 0, // Skip to: 6701 /* 1617 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1634 /* 1622 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1634 /* 1629 */ MCD_OPC_Decode, 255, 19, 202, 1, // Opcode: VST3d32 /* 1634 */ MCD_OPC_CheckPredicate, 21, 198, 19, 0, // Skip to: 6701 /* 1639 */ MCD_OPC_Decode, 130, 20, 202, 1, // Opcode: VST3d32_UPD /* 1644 */ MCD_OPC_FilterValue, 233, 3, 187, 19, 0, // Skip to: 6701 /* 1650 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 1653 */ MCD_OPC_FilterValue, 0, 179, 19, 0, // Skip to: 6701 /* 1658 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1675 /* 1663 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1675 /* 1670 */ MCD_OPC_Decode, 215, 18, 192, 1, // Opcode: VST1LNd16 /* 1675 */ MCD_OPC_CheckPredicate, 21, 157, 19, 0, // Skip to: 6701 /* 1680 */ MCD_OPC_Decode, 216, 18, 192, 1, // Opcode: VST1LNd16_UPD /* 1685 */ MCD_OPC_FilterValue, 2, 147, 19, 0, // Skip to: 6701 /* 1690 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1693 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1798 /* 1699 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 1702 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1734 /* 1707 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1724 /* 1712 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1724 /* 1719 */ MCD_OPC_Decode, 182, 12, 202, 1, // Opcode: VLD3d8 /* 1724 */ MCD_OPC_CheckPredicate, 21, 108, 19, 0, // Skip to: 6701 /* 1729 */ MCD_OPC_Decode, 185, 12, 202, 1, // Opcode: VLD3d8_UPD /* 1734 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1766 /* 1739 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1756 /* 1744 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1756 /* 1751 */ MCD_OPC_Decode, 174, 12, 202, 1, // Opcode: VLD3d16 /* 1756 */ MCD_OPC_CheckPredicate, 21, 76, 19, 0, // Skip to: 6701 /* 1761 */ MCD_OPC_Decode, 177, 12, 202, 1, // Opcode: VLD3d16_UPD /* 1766 */ MCD_OPC_FilterValue, 4, 66, 19, 0, // Skip to: 6701 /* 1771 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1788 /* 1776 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1788 /* 1783 */ MCD_OPC_Decode, 178, 12, 202, 1, // Opcode: VLD3d32 /* 1788 */ MCD_OPC_CheckPredicate, 21, 44, 19, 0, // Skip to: 6701 /* 1793 */ MCD_OPC_Decode, 181, 12, 202, 1, // Opcode: VLD3d32_UPD /* 1798 */ MCD_OPC_FilterValue, 233, 3, 33, 19, 0, // Skip to: 6701 /* 1804 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1821 /* 1809 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1821 /* 1816 */ MCD_OPC_Decode, 218, 10, 193, 1, // Opcode: VLD1LNd16 /* 1821 */ MCD_OPC_CheckPredicate, 21, 11, 19, 0, // Skip to: 6701 /* 1826 */ MCD_OPC_CheckField, 5, 1, 0, 4, 19, 0, // Skip to: 6701 /* 1833 */ MCD_OPC_Decode, 219, 10, 193, 1, // Opcode: VLD1LNd16_UPD /* 1838 */ MCD_OPC_FilterValue, 5, 137, 1, 0, // Skip to: 2236 /* 1843 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 1846 */ MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 2146 /* 1851 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 1854 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 2000 /* 1859 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1862 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1967 /* 1868 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1871 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1903 /* 1876 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1893 /* 1881 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1893 /* 1888 */ MCD_OPC_Decode, 145, 20, 202, 1, // Opcode: VST3q8 /* 1893 */ MCD_OPC_CheckPredicate, 21, 195, 18, 0, // Skip to: 6701 /* 1898 */ MCD_OPC_Decode, 147, 20, 202, 1, // Opcode: VST3q8_UPD /* 1903 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 1935 /* 1908 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1925 /* 1913 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1925 /* 1920 */ MCD_OPC_Decode, 135, 20, 202, 1, // Opcode: VST3q16 /* 1925 */ MCD_OPC_CheckPredicate, 21, 163, 18, 0, // Skip to: 6701 /* 1930 */ MCD_OPC_Decode, 137, 20, 202, 1, // Opcode: VST3q16_UPD /* 1935 */ MCD_OPC_FilterValue, 2, 153, 18, 0, // Skip to: 6701 /* 1940 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1957 /* 1945 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1957 /* 1952 */ MCD_OPC_Decode, 140, 20, 202, 1, // Opcode: VST3q32 /* 1957 */ MCD_OPC_CheckPredicate, 21, 131, 18, 0, // Skip to: 6701 /* 1962 */ MCD_OPC_Decode, 142, 20, 202, 1, // Opcode: VST3q32_UPD /* 1967 */ MCD_OPC_FilterValue, 233, 3, 120, 18, 0, // Skip to: 6701 /* 1973 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1990 /* 1978 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1990 /* 1985 */ MCD_OPC_Decode, 175, 19, 194, 1, // Opcode: VST2LNd16 /* 1990 */ MCD_OPC_CheckPredicate, 21, 98, 18, 0, // Skip to: 6701 /* 1995 */ MCD_OPC_Decode, 178, 19, 194, 1, // Opcode: VST2LNd16_UPD /* 2000 */ MCD_OPC_FilterValue, 2, 88, 18, 0, // Skip to: 6701 /* 2005 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2008 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 2113 /* 2014 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 2017 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2049 /* 2022 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2039 /* 2027 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2039 /* 2034 */ MCD_OPC_Decode, 196, 12, 202, 1, // Opcode: VLD3q8 /* 2039 */ MCD_OPC_CheckPredicate, 21, 49, 18, 0, // Skip to: 6701 /* 2044 */ MCD_OPC_Decode, 198, 12, 202, 1, // Opcode: VLD3q8_UPD /* 2049 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 2081 /* 2054 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2071 /* 2059 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2071 /* 2066 */ MCD_OPC_Decode, 186, 12, 202, 1, // Opcode: VLD3q16 /* 2071 */ MCD_OPC_CheckPredicate, 21, 17, 18, 0, // Skip to: 6701 /* 2076 */ MCD_OPC_Decode, 188, 12, 202, 1, // Opcode: VLD3q16_UPD /* 2081 */ MCD_OPC_FilterValue, 2, 7, 18, 0, // Skip to: 6701 /* 2086 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2103 /* 2091 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2103 /* 2098 */ MCD_OPC_Decode, 191, 12, 202, 1, // Opcode: VLD3q32 /* 2103 */ MCD_OPC_CheckPredicate, 21, 241, 17, 0, // Skip to: 6701 /* 2108 */ MCD_OPC_Decode, 193, 12, 202, 1, // Opcode: VLD3q32_UPD /* 2113 */ MCD_OPC_FilterValue, 233, 3, 230, 17, 0, // Skip to: 6701 /* 2119 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2136 /* 2124 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2136 /* 2131 */ MCD_OPC_Decode, 202, 11, 195, 1, // Opcode: VLD2LNd16 /* 2136 */ MCD_OPC_CheckPredicate, 21, 208, 17, 0, // Skip to: 6701 /* 2141 */ MCD_OPC_Decode, 205, 11, 195, 1, // Opcode: VLD2LNd16_UPD /* 2146 */ MCD_OPC_FilterValue, 1, 198, 17, 0, // Skip to: 6701 /* 2151 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 2154 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 2195 /* 2159 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2162 */ MCD_OPC_FilterValue, 233, 3, 181, 17, 0, // Skip to: 6701 /* 2168 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2185 /* 2173 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2185 /* 2180 */ MCD_OPC_Decode, 187, 19, 194, 1, // Opcode: VST2LNq16 /* 2185 */ MCD_OPC_CheckPredicate, 21, 159, 17, 0, // Skip to: 6701 /* 2190 */ MCD_OPC_Decode, 190, 19, 194, 1, // Opcode: VST2LNq16_UPD /* 2195 */ MCD_OPC_FilterValue, 2, 149, 17, 0, // Skip to: 6701 /* 2200 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2203 */ MCD_OPC_FilterValue, 233, 3, 140, 17, 0, // Skip to: 6701 /* 2209 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2226 /* 2214 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2226 /* 2221 */ MCD_OPC_Decode, 214, 11, 195, 1, // Opcode: VLD2LNq16 /* 2226 */ MCD_OPC_CheckPredicate, 21, 118, 17, 0, // Skip to: 6701 /* 2231 */ MCD_OPC_Decode, 217, 11, 195, 1, // Opcode: VLD2LNq16_UPD /* 2236 */ MCD_OPC_FilterValue, 6, 108, 2, 0, // Skip to: 2861 /* 2241 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 2244 */ MCD_OPC_FilterValue, 0, 49, 1, 0, // Skip to: 2554 /* 2249 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2252 */ MCD_OPC_FilterValue, 232, 3, 223, 0, 0, // Skip to: 2481 /* 2258 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 2261 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2316 /* 2266 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2269 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2284 /* 2274 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2306 /* 2279 */ MCD_OPC_Decode, 143, 19, 196, 1, // Opcode: VST1d8Twb_fixed /* 2284 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2306 /* 2289 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2306 /* 2294 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2306 /* 2301 */ MCD_OPC_Decode, 141, 19, 196, 1, // Opcode: VST1d8T /* 2306 */ MCD_OPC_CheckPredicate, 21, 38, 17, 0, // Skip to: 6701 /* 2311 */ MCD_OPC_Decode, 144, 19, 196, 1, // Opcode: VST1d8Twb_register /* 2316 */ MCD_OPC_FilterValue, 1, 50, 0, 0, // Skip to: 2371 /* 2321 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2324 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2339 /* 2329 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2361 /* 2334 */ MCD_OPC_Decode, 234, 18, 196, 1, // Opcode: VST1d16Twb_fixed /* 2339 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2361 /* 2344 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2361 /* 2349 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2361 /* 2356 */ MCD_OPC_Decode, 232, 18, 196, 1, // Opcode: VST1d16T /* 2361 */ MCD_OPC_CheckPredicate, 21, 239, 16, 0, // Skip to: 6701 /* 2366 */ MCD_OPC_Decode, 235, 18, 196, 1, // Opcode: VST1d16Twb_register /* 2371 */ MCD_OPC_FilterValue, 2, 50, 0, 0, // Skip to: 2426 /* 2376 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2379 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2394 /* 2384 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2416 /* 2389 */ MCD_OPC_Decode, 245, 18, 196, 1, // Opcode: VST1d32Twb_fixed /* 2394 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2416 /* 2399 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2416 /* 2404 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2416 /* 2411 */ MCD_OPC_Decode, 243, 18, 196, 1, // Opcode: VST1d32T /* 2416 */ MCD_OPC_CheckPredicate, 21, 184, 16, 0, // Skip to: 6701 /* 2421 */ MCD_OPC_Decode, 246, 18, 196, 1, // Opcode: VST1d32Twb_register /* 2426 */ MCD_OPC_FilterValue, 3, 174, 16, 0, // Skip to: 6701 /* 2431 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2434 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2449 /* 2439 */ MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2471 /* 2444 */ MCD_OPC_Decode, 132, 19, 196, 1, // Opcode: VST1d64Twb_fixed /* 2449 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2471 /* 2454 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2471 /* 2459 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2471 /* 2466 */ MCD_OPC_Decode, 128, 19, 196, 1, // Opcode: VST1d64T /* 2471 */ MCD_OPC_CheckPredicate, 21, 129, 16, 0, // Skip to: 6701 /* 2476 */ MCD_OPC_Decode, 133, 19, 196, 1, // Opcode: VST1d64Twb_register /* 2481 */ MCD_OPC_FilterValue, 233, 3, 118, 16, 0, // Skip to: 6701 /* 2487 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 2490 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2522 /* 2495 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2512 /* 2500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2512 /* 2507 */ MCD_OPC_Decode, 231, 19, 197, 1, // Opcode: VST3LNd16 /* 2512 */ MCD_OPC_CheckPredicate, 21, 88, 16, 0, // Skip to: 6701 /* 2517 */ MCD_OPC_Decode, 234, 19, 197, 1, // Opcode: VST3LNd16_UPD /* 2522 */ MCD_OPC_FilterValue, 2, 78, 16, 0, // Skip to: 6701 /* 2527 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2544 /* 2532 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2544 /* 2539 */ MCD_OPC_Decode, 243, 19, 197, 1, // Opcode: VST3LNq16 /* 2544 */ MCD_OPC_CheckPredicate, 21, 56, 16, 0, // Skip to: 6701 /* 2549 */ MCD_OPC_Decode, 246, 19, 197, 1, // Opcode: VST3LNq16_UPD /* 2554 */ MCD_OPC_FilterValue, 2, 46, 16, 0, // Skip to: 6701 /* 2559 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 2562 */ MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 2812 /* 2567 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2570 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 2771 /* 2576 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 2579 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2627 /* 2584 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2587 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2602 /* 2592 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2617 /* 2597 */ MCD_OPC_Decode, 146, 11, 196, 1, // Opcode: VLD1d8Twb_fixed /* 2602 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2617 /* 2607 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2617 /* 2612 */ MCD_OPC_Decode, 144, 11, 196, 1, // Opcode: VLD1d8T /* 2617 */ MCD_OPC_CheckPredicate, 21, 239, 15, 0, // Skip to: 6701 /* 2622 */ MCD_OPC_Decode, 147, 11, 196, 1, // Opcode: VLD1d8Twb_register /* 2627 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2675 /* 2632 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2635 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2650 /* 2640 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2665 /* 2645 */ MCD_OPC_Decode, 237, 10, 196, 1, // Opcode: VLD1d16Twb_fixed /* 2650 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2665 /* 2655 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2665 /* 2660 */ MCD_OPC_Decode, 235, 10, 196, 1, // Opcode: VLD1d16T /* 2665 */ MCD_OPC_CheckPredicate, 21, 191, 15, 0, // Skip to: 6701 /* 2670 */ MCD_OPC_Decode, 238, 10, 196, 1, // Opcode: VLD1d16Twb_register /* 2675 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 2723 /* 2680 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2683 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2698 /* 2688 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2713 /* 2693 */ MCD_OPC_Decode, 248, 10, 196, 1, // Opcode: VLD1d32Twb_fixed /* 2698 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2713 /* 2703 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2713 /* 2708 */ MCD_OPC_Decode, 246, 10, 196, 1, // Opcode: VLD1d32T /* 2713 */ MCD_OPC_CheckPredicate, 21, 143, 15, 0, // Skip to: 6701 /* 2718 */ MCD_OPC_Decode, 249, 10, 196, 1, // Opcode: VLD1d32Twb_register /* 2723 */ MCD_OPC_FilterValue, 3, 133, 15, 0, // Skip to: 6701 /* 2728 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2731 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2746 /* 2736 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2761 /* 2741 */ MCD_OPC_Decode, 135, 11, 196, 1, // Opcode: VLD1d64Twb_fixed /* 2746 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2761 /* 2751 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2761 /* 2756 */ MCD_OPC_Decode, 131, 11, 196, 1, // Opcode: VLD1d64T /* 2761 */ MCD_OPC_CheckPredicate, 21, 95, 15, 0, // Skip to: 6701 /* 2766 */ MCD_OPC_Decode, 136, 11, 196, 1, // Opcode: VLD1d64Twb_register /* 2771 */ MCD_OPC_FilterValue, 233, 3, 84, 15, 0, // Skip to: 6701 /* 2777 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 2780 */ MCD_OPC_FilterValue, 0, 76, 15, 0, // Skip to: 6701 /* 2785 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2802 /* 2790 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2802 /* 2797 */ MCD_OPC_Decode, 154, 12, 198, 1, // Opcode: VLD3LNd16 /* 2802 */ MCD_OPC_CheckPredicate, 21, 54, 15, 0, // Skip to: 6701 /* 2807 */ MCD_OPC_Decode, 157, 12, 198, 1, // Opcode: VLD3LNd16_UPD /* 2812 */ MCD_OPC_FilterValue, 1, 44, 15, 0, // Skip to: 6701 /* 2817 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 2820 */ MCD_OPC_FilterValue, 0, 36, 15, 0, // Skip to: 6701 /* 2825 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2828 */ MCD_OPC_FilterValue, 233, 3, 27, 15, 0, // Skip to: 6701 /* 2834 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2851 /* 2839 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2851 /* 2846 */ MCD_OPC_Decode, 166, 12, 198, 1, // Opcode: VLD3LNq16 /* 2851 */ MCD_OPC_CheckPredicate, 21, 5, 15, 0, // Skip to: 6701 /* 2856 */ MCD_OPC_Decode, 169, 12, 198, 1, // Opcode: VLD3LNq16_UPD /* 2861 */ MCD_OPC_FilterValue, 7, 73, 2, 0, // Skip to: 3451 /* 2866 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 2869 */ MCD_OPC_FilterValue, 0, 231, 1, 0, // Skip to: 3361 /* 2874 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 2877 */ MCD_OPC_FilterValue, 0, 237, 0, 0, // Skip to: 3119 /* 2882 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2885 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3086 /* 2891 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 2894 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2942 /* 2899 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2902 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2917 /* 2907 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2932 /* 2912 */ MCD_OPC_Decode, 145, 19, 196, 1, // Opcode: VST1d8wb_fixed /* 2917 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2932 /* 2922 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2932 /* 2927 */ MCD_OPC_Decode, 136, 19, 196, 1, // Opcode: VST1d8 /* 2932 */ MCD_OPC_CheckPredicate, 21, 180, 14, 0, // Skip to: 6701 /* 2937 */ MCD_OPC_Decode, 146, 19, 196, 1, // Opcode: VST1d8wb_register /* 2942 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2990 /* 2947 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2950 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2965 /* 2955 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2980 /* 2960 */ MCD_OPC_Decode, 236, 18, 196, 1, // Opcode: VST1d16wb_fixed /* 2965 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2980 /* 2970 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2980 /* 2975 */ MCD_OPC_Decode, 227, 18, 196, 1, // Opcode: VST1d16 /* 2980 */ MCD_OPC_CheckPredicate, 21, 132, 14, 0, // Skip to: 6701 /* 2985 */ MCD_OPC_Decode, 237, 18, 196, 1, // Opcode: VST1d16wb_register /* 2990 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3038 /* 2995 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2998 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3013 /* 3003 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3028 /* 3008 */ MCD_OPC_Decode, 247, 18, 196, 1, // Opcode: VST1d32wb_fixed /* 3013 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3028 /* 3018 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3028 /* 3023 */ MCD_OPC_Decode, 238, 18, 196, 1, // Opcode: VST1d32 /* 3028 */ MCD_OPC_CheckPredicate, 21, 84, 14, 0, // Skip to: 6701 /* 3033 */ MCD_OPC_Decode, 248, 18, 196, 1, // Opcode: VST1d32wb_register /* 3038 */ MCD_OPC_FilterValue, 3, 74, 14, 0, // Skip to: 6701 /* 3043 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3046 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3061 /* 3051 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3076 /* 3056 */ MCD_OPC_Decode, 134, 19, 196, 1, // Opcode: VST1d64wb_fixed /* 3061 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3076 /* 3066 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3076 /* 3071 */ MCD_OPC_Decode, 249, 18, 196, 1, // Opcode: VST1d64 /* 3076 */ MCD_OPC_CheckPredicate, 21, 36, 14, 0, // Skip to: 6701 /* 3081 */ MCD_OPC_Decode, 135, 19, 196, 1, // Opcode: VST1d64wb_register /* 3086 */ MCD_OPC_FilterValue, 233, 3, 25, 14, 0, // Skip to: 6701 /* 3092 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3109 /* 3097 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3109 /* 3104 */ MCD_OPC_Decode, 150, 20, 200, 1, // Opcode: VST4LNd16 /* 3109 */ MCD_OPC_CheckPredicate, 21, 3, 14, 0, // Skip to: 6701 /* 3114 */ MCD_OPC_Decode, 153, 20, 200, 1, // Opcode: VST4LNd16_UPD /* 3119 */ MCD_OPC_FilterValue, 2, 249, 13, 0, // Skip to: 6701 /* 3124 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3127 */ MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3328 /* 3133 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 3136 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3184 /* 3141 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3144 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3159 /* 3149 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3174 /* 3154 */ MCD_OPC_Decode, 148, 11, 196, 1, // Opcode: VLD1d8wb_fixed /* 3159 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3174 /* 3164 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3174 /* 3169 */ MCD_OPC_Decode, 139, 11, 196, 1, // Opcode: VLD1d8 /* 3174 */ MCD_OPC_CheckPredicate, 21, 194, 13, 0, // Skip to: 6701 /* 3179 */ MCD_OPC_Decode, 149, 11, 196, 1, // Opcode: VLD1d8wb_register /* 3184 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 3232 /* 3189 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3192 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3207 /* 3197 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3222 /* 3202 */ MCD_OPC_Decode, 239, 10, 196, 1, // Opcode: VLD1d16wb_fixed /* 3207 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3222 /* 3212 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3222 /* 3217 */ MCD_OPC_Decode, 230, 10, 196, 1, // Opcode: VLD1d16 /* 3222 */ MCD_OPC_CheckPredicate, 21, 146, 13, 0, // Skip to: 6701 /* 3227 */ MCD_OPC_Decode, 240, 10, 196, 1, // Opcode: VLD1d16wb_register /* 3232 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3280 /* 3237 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3240 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3255 /* 3245 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3270 /* 3250 */ MCD_OPC_Decode, 250, 10, 196, 1, // Opcode: VLD1d32wb_fixed /* 3255 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3270 /* 3260 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3270 /* 3265 */ MCD_OPC_Decode, 241, 10, 196, 1, // Opcode: VLD1d32 /* 3270 */ MCD_OPC_CheckPredicate, 21, 98, 13, 0, // Skip to: 6701 /* 3275 */ MCD_OPC_Decode, 251, 10, 196, 1, // Opcode: VLD1d32wb_register /* 3280 */ MCD_OPC_FilterValue, 3, 88, 13, 0, // Skip to: 6701 /* 3285 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3288 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3303 /* 3293 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3318 /* 3298 */ MCD_OPC_Decode, 137, 11, 196, 1, // Opcode: VLD1d64wb_fixed /* 3303 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3318 /* 3308 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3318 /* 3313 */ MCD_OPC_Decode, 252, 10, 196, 1, // Opcode: VLD1d64 /* 3318 */ MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 6701 /* 3323 */ MCD_OPC_Decode, 138, 11, 196, 1, // Opcode: VLD1d64wb_register /* 3328 */ MCD_OPC_FilterValue, 233, 3, 39, 13, 0, // Skip to: 6701 /* 3334 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3351 /* 3339 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3351 /* 3346 */ MCD_OPC_Decode, 225, 12, 201, 1, // Opcode: VLD4LNd16 /* 3351 */ MCD_OPC_CheckPredicate, 21, 17, 13, 0, // Skip to: 6701 /* 3356 */ MCD_OPC_Decode, 228, 12, 201, 1, // Opcode: VLD4LNd16_UPD /* 3361 */ MCD_OPC_FilterValue, 1, 7, 13, 0, // Skip to: 6701 /* 3366 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 3369 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3410 /* 3374 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3377 */ MCD_OPC_FilterValue, 233, 3, 246, 12, 0, // Skip to: 6701 /* 3383 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3400 /* 3388 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3400 /* 3395 */ MCD_OPC_Decode, 162, 20, 200, 1, // Opcode: VST4LNq16 /* 3400 */ MCD_OPC_CheckPredicate, 21, 224, 12, 0, // Skip to: 6701 /* 3405 */ MCD_OPC_Decode, 165, 20, 200, 1, // Opcode: VST4LNq16_UPD /* 3410 */ MCD_OPC_FilterValue, 2, 214, 12, 0, // Skip to: 6701 /* 3415 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3418 */ MCD_OPC_FilterValue, 233, 3, 205, 12, 0, // Skip to: 6701 /* 3424 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3441 /* 3429 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3441 /* 3436 */ MCD_OPC_Decode, 237, 12, 201, 1, // Opcode: VLD4LNq16 /* 3441 */ MCD_OPC_CheckPredicate, 21, 183, 12, 0, // Skip to: 6701 /* 3446 */ MCD_OPC_Decode, 240, 12, 201, 1, // Opcode: VLD4LNq16_UPD /* 3451 */ MCD_OPC_FilterValue, 8, 185, 1, 0, // Skip to: 3897 /* 3456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3459 */ MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 3759 /* 3464 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 3467 */ MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 3613 /* 3472 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3475 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3580 /* 3481 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 3484 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3532 /* 3489 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3492 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3507 /* 3497 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3522 /* 3502 */ MCD_OPC_Decode, 211, 19, 199, 1, // Opcode: VST2d8wb_fixed /* 3507 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3522 /* 3512 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3522 /* 3517 */ MCD_OPC_Decode, 210, 19, 199, 1, // Opcode: VST2d8 /* 3522 */ MCD_OPC_CheckPredicate, 21, 102, 12, 0, // Skip to: 6701 /* 3527 */ MCD_OPC_Decode, 212, 19, 199, 1, // Opcode: VST2d8wb_register /* 3532 */ MCD_OPC_FilterValue, 1, 92, 12, 0, // Skip to: 6701 /* 3537 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3540 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3555 /* 3545 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3570 /* 3550 */ MCD_OPC_Decode, 208, 19, 199, 1, // Opcode: VST2d32wb_fixed /* 3555 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3570 /* 3560 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3570 /* 3565 */ MCD_OPC_Decode, 207, 19, 199, 1, // Opcode: VST2d32 /* 3570 */ MCD_OPC_CheckPredicate, 21, 54, 12, 0, // Skip to: 6701 /* 3575 */ MCD_OPC_Decode, 209, 19, 199, 1, // Opcode: VST2d32wb_register /* 3580 */ MCD_OPC_FilterValue, 233, 3, 43, 12, 0, // Skip to: 6701 /* 3586 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3603 /* 3591 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3603 /* 3598 */ MCD_OPC_Decode, 217, 18, 192, 1, // Opcode: VST1LNd32 /* 3603 */ MCD_OPC_CheckPredicate, 21, 21, 12, 0, // Skip to: 6701 /* 3608 */ MCD_OPC_Decode, 218, 18, 192, 1, // Opcode: VST1LNd32_UPD /* 3613 */ MCD_OPC_FilterValue, 2, 11, 12, 0, // Skip to: 6701 /* 3618 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3621 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3726 /* 3627 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 3630 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3678 /* 3635 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3638 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3653 /* 3643 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3668 /* 3648 */ MCD_OPC_Decode, 238, 11, 199, 1, // Opcode: VLD2d8wb_fixed /* 3653 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3668 /* 3658 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3668 /* 3663 */ MCD_OPC_Decode, 237, 11, 199, 1, // Opcode: VLD2d8 /* 3668 */ MCD_OPC_CheckPredicate, 21, 212, 11, 0, // Skip to: 6701 /* 3673 */ MCD_OPC_Decode, 239, 11, 199, 1, // Opcode: VLD2d8wb_register /* 3678 */ MCD_OPC_FilterValue, 1, 202, 11, 0, // Skip to: 6701 /* 3683 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3686 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3701 /* 3691 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3716 /* 3696 */ MCD_OPC_Decode, 235, 11, 199, 1, // Opcode: VLD2d32wb_fixed /* 3701 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3716 /* 3706 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3716 /* 3711 */ MCD_OPC_Decode, 234, 11, 199, 1, // Opcode: VLD2d32 /* 3716 */ MCD_OPC_CheckPredicate, 21, 164, 11, 0, // Skip to: 6701 /* 3721 */ MCD_OPC_Decode, 236, 11, 199, 1, // Opcode: VLD2d32wb_register /* 3726 */ MCD_OPC_FilterValue, 233, 3, 153, 11, 0, // Skip to: 6701 /* 3732 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3749 /* 3737 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3749 /* 3744 */ MCD_OPC_Decode, 220, 10, 193, 1, // Opcode: VLD1LNd32 /* 3749 */ MCD_OPC_CheckPredicate, 21, 131, 11, 0, // Skip to: 6701 /* 3754 */ MCD_OPC_Decode, 221, 10, 193, 1, // Opcode: VLD1LNd32_UPD /* 3759 */ MCD_OPC_FilterValue, 1, 121, 11, 0, // Skip to: 6701 /* 3764 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 3767 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3832 /* 3772 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 3775 */ MCD_OPC_FilterValue, 0, 105, 11, 0, // Skip to: 6701 /* 3780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3783 */ MCD_OPC_FilterValue, 232, 3, 96, 11, 0, // Skip to: 6701 /* 3789 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3792 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3807 /* 3797 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3822 /* 3802 */ MCD_OPC_Decode, 205, 19, 199, 1, // Opcode: VST2d16wb_fixed /* 3807 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3822 /* 3812 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3822 /* 3817 */ MCD_OPC_Decode, 204, 19, 199, 1, // Opcode: VST2d16 /* 3822 */ MCD_OPC_CheckPredicate, 21, 58, 11, 0, // Skip to: 6701 /* 3827 */ MCD_OPC_Decode, 206, 19, 199, 1, // Opcode: VST2d16wb_register /* 3832 */ MCD_OPC_FilterValue, 2, 48, 11, 0, // Skip to: 6701 /* 3837 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 3840 */ MCD_OPC_FilterValue, 0, 40, 11, 0, // Skip to: 6701 /* 3845 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3848 */ MCD_OPC_FilterValue, 232, 3, 31, 11, 0, // Skip to: 6701 /* 3854 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3857 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3872 /* 3862 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3887 /* 3867 */ MCD_OPC_Decode, 232, 11, 199, 1, // Opcode: VLD2d16wb_fixed /* 3872 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3887 /* 3877 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3887 /* 3882 */ MCD_OPC_Decode, 231, 11, 199, 1, // Opcode: VLD2d16 /* 3887 */ MCD_OPC_CheckPredicate, 21, 249, 10, 0, // Skip to: 6701 /* 3892 */ MCD_OPC_Decode, 233, 11, 199, 1, // Opcode: VLD2d16wb_register /* 3897 */ MCD_OPC_FilterValue, 9, 27, 2, 0, // Skip to: 4441 /* 3902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 3905 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4221 /* 3910 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 3913 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4067 /* 3918 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 3921 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4026 /* 3927 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 3930 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3978 /* 3935 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3938 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3953 /* 3943 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3968 /* 3948 */ MCD_OPC_Decode, 202, 19, 199, 1, // Opcode: VST2b8wb_fixed /* 3953 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3968 /* 3958 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3968 /* 3963 */ MCD_OPC_Decode, 201, 19, 199, 1, // Opcode: VST2b8 /* 3968 */ MCD_OPC_CheckPredicate, 21, 168, 10, 0, // Skip to: 6701 /* 3973 */ MCD_OPC_Decode, 203, 19, 199, 1, // Opcode: VST2b8wb_register /* 3978 */ MCD_OPC_FilterValue, 1, 158, 10, 0, // Skip to: 6701 /* 3983 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 3986 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4001 /* 3991 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4016 /* 3996 */ MCD_OPC_Decode, 199, 19, 199, 1, // Opcode: VST2b32wb_fixed /* 4001 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4016 /* 4006 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4016 /* 4011 */ MCD_OPC_Decode, 198, 19, 199, 1, // Opcode: VST2b32 /* 4016 */ MCD_OPC_CheckPredicate, 21, 120, 10, 0, // Skip to: 6701 /* 4021 */ MCD_OPC_Decode, 200, 19, 199, 1, // Opcode: VST2b32wb_register /* 4026 */ MCD_OPC_FilterValue, 233, 3, 109, 10, 0, // Skip to: 6701 /* 4032 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 4035 */ MCD_OPC_FilterValue, 0, 101, 10, 0, // Skip to: 6701 /* 4040 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4057 /* 4045 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4057 /* 4052 */ MCD_OPC_Decode, 179, 19, 194, 1, // Opcode: VST2LNd32 /* 4057 */ MCD_OPC_CheckPredicate, 21, 79, 10, 0, // Skip to: 6701 /* 4062 */ MCD_OPC_Decode, 182, 19, 194, 1, // Opcode: VST2LNd32_UPD /* 4067 */ MCD_OPC_FilterValue, 2, 69, 10, 0, // Skip to: 6701 /* 4072 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4075 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4180 /* 4081 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4084 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4132 /* 4089 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4092 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4107 /* 4097 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4122 /* 4102 */ MCD_OPC_Decode, 229, 11, 199, 1, // Opcode: VLD2b8wb_fixed /* 4107 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4122 /* 4112 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4122 /* 4117 */ MCD_OPC_Decode, 228, 11, 199, 1, // Opcode: VLD2b8 /* 4122 */ MCD_OPC_CheckPredicate, 21, 14, 10, 0, // Skip to: 6701 /* 4127 */ MCD_OPC_Decode, 230, 11, 199, 1, // Opcode: VLD2b8wb_register /* 4132 */ MCD_OPC_FilterValue, 1, 4, 10, 0, // Skip to: 6701 /* 4137 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4140 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4155 /* 4145 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4170 /* 4150 */ MCD_OPC_Decode, 226, 11, 199, 1, // Opcode: VLD2b32wb_fixed /* 4155 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4170 /* 4160 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4170 /* 4165 */ MCD_OPC_Decode, 225, 11, 199, 1, // Opcode: VLD2b32 /* 4170 */ MCD_OPC_CheckPredicate, 21, 222, 9, 0, // Skip to: 6701 /* 4175 */ MCD_OPC_Decode, 227, 11, 199, 1, // Opcode: VLD2b32wb_register /* 4180 */ MCD_OPC_FilterValue, 233, 3, 211, 9, 0, // Skip to: 6701 /* 4186 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 4189 */ MCD_OPC_FilterValue, 0, 203, 9, 0, // Skip to: 6701 /* 4194 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4211 /* 4199 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4211 /* 4206 */ MCD_OPC_Decode, 206, 11, 195, 1, // Opcode: VLD2LNd32 /* 4211 */ MCD_OPC_CheckPredicate, 21, 181, 9, 0, // Skip to: 6701 /* 4216 */ MCD_OPC_Decode, 209, 11, 195, 1, // Opcode: VLD2LNd32_UPD /* 4221 */ MCD_OPC_FilterValue, 1, 171, 9, 0, // Skip to: 6701 /* 4226 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 4229 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 4335 /* 4234 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4237 */ MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4294 /* 4243 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4246 */ MCD_OPC_FilterValue, 0, 146, 9, 0, // Skip to: 6701 /* 4251 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4254 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4269 /* 4259 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4284 /* 4264 */ MCD_OPC_Decode, 196, 19, 199, 1, // Opcode: VST2b16wb_fixed /* 4269 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4284 /* 4274 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4284 /* 4279 */ MCD_OPC_Decode, 195, 19, 199, 1, // Opcode: VST2b16 /* 4284 */ MCD_OPC_CheckPredicate, 21, 108, 9, 0, // Skip to: 6701 /* 4289 */ MCD_OPC_Decode, 197, 19, 199, 1, // Opcode: VST2b16wb_register /* 4294 */ MCD_OPC_FilterValue, 233, 3, 97, 9, 0, // Skip to: 6701 /* 4300 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 4303 */ MCD_OPC_FilterValue, 0, 89, 9, 0, // Skip to: 6701 /* 4308 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4325 /* 4313 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4325 /* 4320 */ MCD_OPC_Decode, 191, 19, 194, 1, // Opcode: VST2LNq32 /* 4325 */ MCD_OPC_CheckPredicate, 21, 67, 9, 0, // Skip to: 6701 /* 4330 */ MCD_OPC_Decode, 194, 19, 194, 1, // Opcode: VST2LNq32_UPD /* 4335 */ MCD_OPC_FilterValue, 2, 57, 9, 0, // Skip to: 6701 /* 4340 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4343 */ MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4400 /* 4349 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4352 */ MCD_OPC_FilterValue, 0, 40, 9, 0, // Skip to: 6701 /* 4357 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4360 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4375 /* 4365 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4390 /* 4370 */ MCD_OPC_Decode, 223, 11, 199, 1, // Opcode: VLD2b16wb_fixed /* 4375 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4390 /* 4380 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4390 /* 4385 */ MCD_OPC_Decode, 222, 11, 199, 1, // Opcode: VLD2b16 /* 4390 */ MCD_OPC_CheckPredicate, 21, 2, 9, 0, // Skip to: 6701 /* 4395 */ MCD_OPC_Decode, 224, 11, 199, 1, // Opcode: VLD2b16wb_register /* 4400 */ MCD_OPC_FilterValue, 233, 3, 247, 8, 0, // Skip to: 6701 /* 4406 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 4409 */ MCD_OPC_FilterValue, 0, 239, 8, 0, // Skip to: 6701 /* 4414 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4431 /* 4419 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4431 /* 4426 */ MCD_OPC_Decode, 218, 11, 195, 1, // Opcode: VLD2LNq32 /* 4431 */ MCD_OPC_CheckPredicate, 21, 217, 8, 0, // Skip to: 6701 /* 4436 */ MCD_OPC_Decode, 221, 11, 195, 1, // Opcode: VLD2LNq32_UPD /* 4441 */ MCD_OPC_FilterValue, 10, 123, 2, 0, // Skip to: 5081 /* 4446 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 4449 */ MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4765 /* 4454 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 4457 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4611 /* 4462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4465 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4570 /* 4471 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4474 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4522 /* 4479 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4482 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4497 /* 4487 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4512 /* 4492 */ MCD_OPC_Decode, 173, 19, 196, 1, // Opcode: VST1q8wb_fixed /* 4497 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4512 /* 4502 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4512 /* 4507 */ MCD_OPC_Decode, 168, 19, 196, 1, // Opcode: VST1q8 /* 4512 */ MCD_OPC_CheckPredicate, 21, 136, 8, 0, // Skip to: 6701 /* 4517 */ MCD_OPC_Decode, 174, 19, 196, 1, // Opcode: VST1q8wb_register /* 4522 */ MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 6701 /* 4527 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4530 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4545 /* 4535 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4560 /* 4540 */ MCD_OPC_Decode, 159, 19, 196, 1, // Opcode: VST1q32wb_fixed /* 4545 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4560 /* 4550 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4560 /* 4555 */ MCD_OPC_Decode, 154, 19, 196, 1, // Opcode: VST1q32 /* 4560 */ MCD_OPC_CheckPredicate, 21, 88, 8, 0, // Skip to: 6701 /* 4565 */ MCD_OPC_Decode, 160, 19, 196, 1, // Opcode: VST1q32wb_register /* 4570 */ MCD_OPC_FilterValue, 233, 3, 77, 8, 0, // Skip to: 6701 /* 4576 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 4579 */ MCD_OPC_FilterValue, 0, 69, 8, 0, // Skip to: 6701 /* 4584 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4601 /* 4589 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4601 /* 4596 */ MCD_OPC_Decode, 235, 19, 197, 1, // Opcode: VST3LNd32 /* 4601 */ MCD_OPC_CheckPredicate, 21, 47, 8, 0, // Skip to: 6701 /* 4606 */ MCD_OPC_Decode, 238, 19, 197, 1, // Opcode: VST3LNd32_UPD /* 4611 */ MCD_OPC_FilterValue, 2, 37, 8, 0, // Skip to: 6701 /* 4616 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4619 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4724 /* 4625 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4628 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4676 /* 4633 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4636 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4651 /* 4641 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4666 /* 4646 */ MCD_OPC_Decode, 176, 11, 196, 1, // Opcode: VLD1q8wb_fixed /* 4651 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4666 /* 4656 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4666 /* 4661 */ MCD_OPC_Decode, 171, 11, 196, 1, // Opcode: VLD1q8 /* 4666 */ MCD_OPC_CheckPredicate, 21, 238, 7, 0, // Skip to: 6701 /* 4671 */ MCD_OPC_Decode, 177, 11, 196, 1, // Opcode: VLD1q8wb_register /* 4676 */ MCD_OPC_FilterValue, 1, 228, 7, 0, // Skip to: 6701 /* 4681 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4684 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4699 /* 4689 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4714 /* 4694 */ MCD_OPC_Decode, 162, 11, 196, 1, // Opcode: VLD1q32wb_fixed /* 4699 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4714 /* 4704 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4714 /* 4709 */ MCD_OPC_Decode, 157, 11, 196, 1, // Opcode: VLD1q32 /* 4714 */ MCD_OPC_CheckPredicate, 21, 190, 7, 0, // Skip to: 6701 /* 4719 */ MCD_OPC_Decode, 163, 11, 196, 1, // Opcode: VLD1q32wb_register /* 4724 */ MCD_OPC_FilterValue, 233, 3, 179, 7, 0, // Skip to: 6701 /* 4730 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 4733 */ MCD_OPC_FilterValue, 0, 171, 7, 0, // Skip to: 6701 /* 4738 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4755 /* 4743 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4755 /* 4750 */ MCD_OPC_Decode, 158, 12, 198, 1, // Opcode: VLD3LNd32 /* 4755 */ MCD_OPC_CheckPredicate, 21, 149, 7, 0, // Skip to: 6701 /* 4760 */ MCD_OPC_Decode, 161, 12, 198, 1, // Opcode: VLD3LNd32_UPD /* 4765 */ MCD_OPC_FilterValue, 1, 139, 7, 0, // Skip to: 6701 /* 4770 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 4773 */ MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4927 /* 4778 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4781 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4886 /* 4787 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4790 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4838 /* 4795 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4798 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4813 /* 4803 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4828 /* 4808 */ MCD_OPC_Decode, 152, 19, 196, 1, // Opcode: VST1q16wb_fixed /* 4813 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4828 /* 4818 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4828 /* 4823 */ MCD_OPC_Decode, 147, 19, 196, 1, // Opcode: VST1q16 /* 4828 */ MCD_OPC_CheckPredicate, 21, 76, 7, 0, // Skip to: 6701 /* 4833 */ MCD_OPC_Decode, 153, 19, 196, 1, // Opcode: VST1q16wb_register /* 4838 */ MCD_OPC_FilterValue, 1, 66, 7, 0, // Skip to: 6701 /* 4843 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4846 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4861 /* 4851 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4876 /* 4856 */ MCD_OPC_Decode, 166, 19, 196, 1, // Opcode: VST1q64wb_fixed /* 4861 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4876 /* 4866 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4876 /* 4871 */ MCD_OPC_Decode, 161, 19, 196, 1, // Opcode: VST1q64 /* 4876 */ MCD_OPC_CheckPredicate, 21, 28, 7, 0, // Skip to: 6701 /* 4881 */ MCD_OPC_Decode, 167, 19, 196, 1, // Opcode: VST1q64wb_register /* 4886 */ MCD_OPC_FilterValue, 233, 3, 17, 7, 0, // Skip to: 6701 /* 4892 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 4895 */ MCD_OPC_FilterValue, 0, 9, 7, 0, // Skip to: 6701 /* 4900 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4917 /* 4905 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4917 /* 4912 */ MCD_OPC_Decode, 247, 19, 197, 1, // Opcode: VST3LNq32 /* 4917 */ MCD_OPC_CheckPredicate, 21, 243, 6, 0, // Skip to: 6701 /* 4922 */ MCD_OPC_Decode, 250, 19, 197, 1, // Opcode: VST3LNq32_UPD /* 4927 */ MCD_OPC_FilterValue, 2, 233, 6, 0, // Skip to: 6701 /* 4932 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 4935 */ MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 5040 /* 4941 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4944 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4992 /* 4949 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 4952 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4967 /* 4957 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4982 /* 4962 */ MCD_OPC_Decode, 155, 11, 196, 1, // Opcode: VLD1q16wb_fixed /* 4967 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4982 /* 4972 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4982 /* 4977 */ MCD_OPC_Decode, 150, 11, 196, 1, // Opcode: VLD1q16 /* 4982 */ MCD_OPC_CheckPredicate, 21, 178, 6, 0, // Skip to: 6701 /* 4987 */ MCD_OPC_Decode, 156, 11, 196, 1, // Opcode: VLD1q16wb_register /* 4992 */ MCD_OPC_FilterValue, 1, 168, 6, 0, // Skip to: 6701 /* 4997 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5000 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5015 /* 5005 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5030 /* 5010 */ MCD_OPC_Decode, 169, 11, 196, 1, // Opcode: VLD1q64wb_fixed /* 5015 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5030 /* 5020 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5030 /* 5025 */ MCD_OPC_Decode, 164, 11, 196, 1, // Opcode: VLD1q64 /* 5030 */ MCD_OPC_CheckPredicate, 21, 130, 6, 0, // Skip to: 6701 /* 5035 */ MCD_OPC_Decode, 170, 11, 196, 1, // Opcode: VLD1q64wb_register /* 5040 */ MCD_OPC_FilterValue, 233, 3, 119, 6, 0, // Skip to: 6701 /* 5046 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 5049 */ MCD_OPC_FilterValue, 0, 111, 6, 0, // Skip to: 6701 /* 5054 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5071 /* 5059 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5071 /* 5066 */ MCD_OPC_Decode, 170, 12, 198, 1, // Opcode: VLD3LNq32 /* 5071 */ MCD_OPC_CheckPredicate, 21, 89, 6, 0, // Skip to: 6701 /* 5076 */ MCD_OPC_Decode, 173, 12, 198, 1, // Opcode: VLD3LNq32_UPD /* 5081 */ MCD_OPC_FilterValue, 11, 183, 0, 0, // Skip to: 5269 /* 5086 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 5089 */ MCD_OPC_FilterValue, 0, 85, 0, 0, // Skip to: 5179 /* 5094 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5097 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5138 /* 5102 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5105 */ MCD_OPC_FilterValue, 233, 3, 54, 6, 0, // Skip to: 6701 /* 5111 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5128 /* 5116 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5128 /* 5123 */ MCD_OPC_Decode, 154, 20, 200, 1, // Opcode: VST4LNd32 /* 5128 */ MCD_OPC_CheckPredicate, 21, 32, 6, 0, // Skip to: 6701 /* 5133 */ MCD_OPC_Decode, 157, 20, 200, 1, // Opcode: VST4LNd32_UPD /* 5138 */ MCD_OPC_FilterValue, 2, 22, 6, 0, // Skip to: 6701 /* 5143 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5146 */ MCD_OPC_FilterValue, 233, 3, 13, 6, 0, // Skip to: 6701 /* 5152 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5169 /* 5157 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5169 /* 5164 */ MCD_OPC_Decode, 229, 12, 201, 1, // Opcode: VLD4LNd32 /* 5169 */ MCD_OPC_CheckPredicate, 21, 247, 5, 0, // Skip to: 6701 /* 5174 */ MCD_OPC_Decode, 232, 12, 201, 1, // Opcode: VLD4LNd32_UPD /* 5179 */ MCD_OPC_FilterValue, 1, 237, 5, 0, // Skip to: 6701 /* 5184 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5187 */ MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5228 /* 5192 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5195 */ MCD_OPC_FilterValue, 233, 3, 220, 5, 0, // Skip to: 6701 /* 5201 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5218 /* 5206 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5218 /* 5213 */ MCD_OPC_Decode, 166, 20, 200, 1, // Opcode: VST4LNq32 /* 5218 */ MCD_OPC_CheckPredicate, 21, 198, 5, 0, // Skip to: 6701 /* 5223 */ MCD_OPC_Decode, 169, 20, 200, 1, // Opcode: VST4LNq32_UPD /* 5228 */ MCD_OPC_FilterValue, 2, 188, 5, 0, // Skip to: 6701 /* 5233 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5236 */ MCD_OPC_FilterValue, 233, 3, 179, 5, 0, // Skip to: 6701 /* 5242 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5259 /* 5247 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5259 /* 5254 */ MCD_OPC_Decode, 241, 12, 201, 1, // Opcode: VLD4LNq32 /* 5259 */ MCD_OPC_CheckPredicate, 21, 157, 5, 0, // Skip to: 6701 /* 5264 */ MCD_OPC_Decode, 244, 12, 201, 1, // Opcode: VLD4LNq32_UPD /* 5269 */ MCD_OPC_FilterValue, 12, 137, 1, 0, // Skip to: 5667 /* 5274 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 5277 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5342 /* 5282 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5285 */ MCD_OPC_FilterValue, 2, 131, 5, 0, // Skip to: 6701 /* 5290 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5293 */ MCD_OPC_FilterValue, 233, 3, 122, 5, 0, // Skip to: 6701 /* 5299 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5302 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5317 /* 5307 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5332 /* 5312 */ MCD_OPC_Decode, 207, 10, 203, 1, // Opcode: VLD1DUPd8wb_fixed /* 5317 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5332 /* 5322 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5332 /* 5327 */ MCD_OPC_Decode, 206, 10, 203, 1, // Opcode: VLD1DUPd8 /* 5332 */ MCD_OPC_CheckPredicate, 21, 84, 5, 0, // Skip to: 6701 /* 5337 */ MCD_OPC_Decode, 208, 10, 203, 1, // Opcode: VLD1DUPd8wb_register /* 5342 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5407 /* 5347 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5350 */ MCD_OPC_FilterValue, 2, 66, 5, 0, // Skip to: 6701 /* 5355 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5358 */ MCD_OPC_FilterValue, 233, 3, 57, 5, 0, // Skip to: 6701 /* 5364 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5367 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5382 /* 5372 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5397 /* 5377 */ MCD_OPC_Decode, 216, 10, 203, 1, // Opcode: VLD1DUPq8wb_fixed /* 5382 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5397 /* 5387 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5397 /* 5392 */ MCD_OPC_Decode, 215, 10, 203, 1, // Opcode: VLD1DUPq8 /* 5397 */ MCD_OPC_CheckPredicate, 21, 19, 5, 0, // Skip to: 6701 /* 5402 */ MCD_OPC_Decode, 217, 10, 203, 1, // Opcode: VLD1DUPq8wb_register /* 5407 */ MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5472 /* 5412 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5415 */ MCD_OPC_FilterValue, 2, 1, 5, 0, // Skip to: 6701 /* 5420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5423 */ MCD_OPC_FilterValue, 233, 3, 248, 4, 0, // Skip to: 6701 /* 5429 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5432 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5447 /* 5437 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5462 /* 5442 */ MCD_OPC_Decode, 201, 10, 203, 1, // Opcode: VLD1DUPd16wb_fixed /* 5447 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5462 /* 5452 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5462 /* 5457 */ MCD_OPC_Decode, 200, 10, 203, 1, // Opcode: VLD1DUPd16 /* 5462 */ MCD_OPC_CheckPredicate, 21, 210, 4, 0, // Skip to: 6701 /* 5467 */ MCD_OPC_Decode, 202, 10, 203, 1, // Opcode: VLD1DUPd16wb_register /* 5472 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5537 /* 5477 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5480 */ MCD_OPC_FilterValue, 2, 192, 4, 0, // Skip to: 6701 /* 5485 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5488 */ MCD_OPC_FilterValue, 233, 3, 183, 4, 0, // Skip to: 6701 /* 5494 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5497 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5512 /* 5502 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5527 /* 5507 */ MCD_OPC_Decode, 210, 10, 203, 1, // Opcode: VLD1DUPq16wb_fixed /* 5512 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5527 /* 5517 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5527 /* 5522 */ MCD_OPC_Decode, 209, 10, 203, 1, // Opcode: VLD1DUPq16 /* 5527 */ MCD_OPC_CheckPredicate, 21, 145, 4, 0, // Skip to: 6701 /* 5532 */ MCD_OPC_Decode, 211, 10, 203, 1, // Opcode: VLD1DUPq16wb_register /* 5537 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 5602 /* 5542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5545 */ MCD_OPC_FilterValue, 2, 127, 4, 0, // Skip to: 6701 /* 5550 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5553 */ MCD_OPC_FilterValue, 233, 3, 118, 4, 0, // Skip to: 6701 /* 5559 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5562 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5577 /* 5567 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5592 /* 5572 */ MCD_OPC_Decode, 204, 10, 203, 1, // Opcode: VLD1DUPd32wb_fixed /* 5577 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5592 /* 5582 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5592 /* 5587 */ MCD_OPC_Decode, 203, 10, 203, 1, // Opcode: VLD1DUPd32 /* 5592 */ MCD_OPC_CheckPredicate, 21, 80, 4, 0, // Skip to: 6701 /* 5597 */ MCD_OPC_Decode, 205, 10, 203, 1, // Opcode: VLD1DUPd32wb_register /* 5602 */ MCD_OPC_FilterValue, 5, 70, 4, 0, // Skip to: 6701 /* 5607 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5610 */ MCD_OPC_FilterValue, 2, 62, 4, 0, // Skip to: 6701 /* 5615 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5618 */ MCD_OPC_FilterValue, 233, 3, 53, 4, 0, // Skip to: 6701 /* 5624 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5627 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5642 /* 5632 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5657 /* 5637 */ MCD_OPC_Decode, 213, 10, 203, 1, // Opcode: VLD1DUPq32wb_fixed /* 5642 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5657 /* 5647 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5657 /* 5652 */ MCD_OPC_Decode, 212, 10, 203, 1, // Opcode: VLD1DUPq32 /* 5657 */ MCD_OPC_CheckPredicate, 21, 15, 4, 0, // Skip to: 6701 /* 5662 */ MCD_OPC_Decode, 214, 10, 203, 1, // Opcode: VLD1DUPq32wb_register /* 5667 */ MCD_OPC_FilterValue, 13, 137, 1, 0, // Skip to: 6065 /* 5672 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 5675 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5740 /* 5680 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5683 */ MCD_OPC_FilterValue, 2, 245, 3, 0, // Skip to: 6701 /* 5688 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5691 */ MCD_OPC_FilterValue, 233, 3, 236, 3, 0, // Skip to: 6701 /* 5697 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5700 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5715 /* 5705 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5730 /* 5710 */ MCD_OPC_Decode, 191, 11, 204, 1, // Opcode: VLD2DUPd8wb_fixed /* 5715 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5730 /* 5720 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5730 /* 5725 */ MCD_OPC_Decode, 190, 11, 204, 1, // Opcode: VLD2DUPd8 /* 5730 */ MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 6701 /* 5735 */ MCD_OPC_Decode, 192, 11, 204, 1, // Opcode: VLD2DUPd8wb_register /* 5740 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5805 /* 5745 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5748 */ MCD_OPC_FilterValue, 2, 180, 3, 0, // Skip to: 6701 /* 5753 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5756 */ MCD_OPC_FilterValue, 233, 3, 171, 3, 0, // Skip to: 6701 /* 5762 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5765 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5780 /* 5770 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5795 /* 5775 */ MCD_OPC_Decode, 194, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_fixed /* 5780 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5795 /* 5785 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5795 /* 5790 */ MCD_OPC_Decode, 193, 11, 204, 1, // Opcode: VLD2DUPd8x2 /* 5795 */ MCD_OPC_CheckPredicate, 21, 133, 3, 0, // Skip to: 6701 /* 5800 */ MCD_OPC_Decode, 195, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_register /* 5805 */ MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5870 /* 5810 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5813 */ MCD_OPC_FilterValue, 2, 115, 3, 0, // Skip to: 6701 /* 5818 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5821 */ MCD_OPC_FilterValue, 233, 3, 106, 3, 0, // Skip to: 6701 /* 5827 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5830 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5845 /* 5835 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5860 /* 5840 */ MCD_OPC_Decode, 179, 11, 204, 1, // Opcode: VLD2DUPd16wb_fixed /* 5845 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5860 /* 5850 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5860 /* 5855 */ MCD_OPC_Decode, 178, 11, 204, 1, // Opcode: VLD2DUPd16 /* 5860 */ MCD_OPC_CheckPredicate, 21, 68, 3, 0, // Skip to: 6701 /* 5865 */ MCD_OPC_Decode, 180, 11, 204, 1, // Opcode: VLD2DUPd16wb_register /* 5870 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5935 /* 5875 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5878 */ MCD_OPC_FilterValue, 2, 50, 3, 0, // Skip to: 6701 /* 5883 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5886 */ MCD_OPC_FilterValue, 233, 3, 41, 3, 0, // Skip to: 6701 /* 5892 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5895 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5910 /* 5900 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5925 /* 5905 */ MCD_OPC_Decode, 182, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_fixed /* 5910 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5925 /* 5915 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5925 /* 5920 */ MCD_OPC_Decode, 181, 11, 204, 1, // Opcode: VLD2DUPd16x2 /* 5925 */ MCD_OPC_CheckPredicate, 21, 3, 3, 0, // Skip to: 6701 /* 5930 */ MCD_OPC_Decode, 183, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_register /* 5935 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 6000 /* 5940 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 5943 */ MCD_OPC_FilterValue, 2, 241, 2, 0, // Skip to: 6701 /* 5948 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 5951 */ MCD_OPC_FilterValue, 233, 3, 232, 2, 0, // Skip to: 6701 /* 5957 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 5960 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5975 /* 5965 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5990 /* 5970 */ MCD_OPC_Decode, 185, 11, 204, 1, // Opcode: VLD2DUPd32wb_fixed /* 5975 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5990 /* 5980 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5990 /* 5985 */ MCD_OPC_Decode, 184, 11, 204, 1, // Opcode: VLD2DUPd32 /* 5990 */ MCD_OPC_CheckPredicate, 21, 194, 2, 0, // Skip to: 6701 /* 5995 */ MCD_OPC_Decode, 186, 11, 204, 1, // Opcode: VLD2DUPd32wb_register /* 6000 */ MCD_OPC_FilterValue, 5, 184, 2, 0, // Skip to: 6701 /* 6005 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6008 */ MCD_OPC_FilterValue, 2, 176, 2, 0, // Skip to: 6701 /* 6013 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6016 */ MCD_OPC_FilterValue, 233, 3, 167, 2, 0, // Skip to: 6701 /* 6022 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 6025 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 6040 /* 6030 */ MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 6055 /* 6035 */ MCD_OPC_Decode, 188, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_fixed /* 6040 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 6055 /* 6045 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6055 /* 6050 */ MCD_OPC_Decode, 187, 11, 204, 1, // Opcode: VLD2DUPd32x2 /* 6055 */ MCD_OPC_CheckPredicate, 21, 129, 2, 0, // Skip to: 6701 /* 6060 */ MCD_OPC_Decode, 189, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_register /* 6065 */ MCD_OPC_FilterValue, 14, 41, 1, 0, // Skip to: 6367 /* 6070 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 6073 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6122 /* 6078 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6081 */ MCD_OPC_FilterValue, 2, 103, 2, 0, // Skip to: 6701 /* 6086 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6089 */ MCD_OPC_FilterValue, 233, 3, 94, 2, 0, // Skip to: 6701 /* 6095 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6112 /* 6100 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6112 /* 6107 */ MCD_OPC_Decode, 138, 12, 205, 1, // Opcode: VLD3DUPd8 /* 6112 */ MCD_OPC_CheckPredicate, 21, 72, 2, 0, // Skip to: 6701 /* 6117 */ MCD_OPC_Decode, 141, 12, 205, 1, // Opcode: VLD3DUPd8_UPD /* 6122 */ MCD_OPC_FilterValue, 2, 44, 0, 0, // Skip to: 6171 /* 6127 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6130 */ MCD_OPC_FilterValue, 2, 54, 2, 0, // Skip to: 6701 /* 6135 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6138 */ MCD_OPC_FilterValue, 233, 3, 45, 2, 0, // Skip to: 6701 /* 6144 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6161 /* 6149 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6161 /* 6156 */ MCD_OPC_Decode, 150, 12, 205, 1, // Opcode: VLD3DUPq8 /* 6161 */ MCD_OPC_CheckPredicate, 21, 23, 2, 0, // Skip to: 6701 /* 6166 */ MCD_OPC_Decode, 153, 12, 205, 1, // Opcode: VLD3DUPq8_UPD /* 6171 */ MCD_OPC_FilterValue, 4, 44, 0, 0, // Skip to: 6220 /* 6176 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6179 */ MCD_OPC_FilterValue, 2, 5, 2, 0, // Skip to: 6701 /* 6184 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6187 */ MCD_OPC_FilterValue, 233, 3, 252, 1, 0, // Skip to: 6701 /* 6193 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6210 /* 6198 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6210 /* 6205 */ MCD_OPC_Decode, 130, 12, 205, 1, // Opcode: VLD3DUPd16 /* 6210 */ MCD_OPC_CheckPredicate, 21, 230, 1, 0, // Skip to: 6701 /* 6215 */ MCD_OPC_Decode, 133, 12, 205, 1, // Opcode: VLD3DUPd16_UPD /* 6220 */ MCD_OPC_FilterValue, 6, 44, 0, 0, // Skip to: 6269 /* 6225 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6228 */ MCD_OPC_FilterValue, 2, 212, 1, 0, // Skip to: 6701 /* 6233 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6236 */ MCD_OPC_FilterValue, 233, 3, 203, 1, 0, // Skip to: 6701 /* 6242 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6259 /* 6247 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6259 /* 6254 */ MCD_OPC_Decode, 142, 12, 205, 1, // Opcode: VLD3DUPq16 /* 6259 */ MCD_OPC_CheckPredicate, 21, 181, 1, 0, // Skip to: 6701 /* 6264 */ MCD_OPC_Decode, 145, 12, 205, 1, // Opcode: VLD3DUPq16_UPD /* 6269 */ MCD_OPC_FilterValue, 8, 44, 0, 0, // Skip to: 6318 /* 6274 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6277 */ MCD_OPC_FilterValue, 2, 163, 1, 0, // Skip to: 6701 /* 6282 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6285 */ MCD_OPC_FilterValue, 233, 3, 154, 1, 0, // Skip to: 6701 /* 6291 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6308 /* 6296 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6308 /* 6303 */ MCD_OPC_Decode, 134, 12, 205, 1, // Opcode: VLD3DUPd32 /* 6308 */ MCD_OPC_CheckPredicate, 21, 132, 1, 0, // Skip to: 6701 /* 6313 */ MCD_OPC_Decode, 137, 12, 205, 1, // Opcode: VLD3DUPd32_UPD /* 6318 */ MCD_OPC_FilterValue, 10, 122, 1, 0, // Skip to: 6701 /* 6323 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6326 */ MCD_OPC_FilterValue, 2, 114, 1, 0, // Skip to: 6701 /* 6331 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6334 */ MCD_OPC_FilterValue, 233, 3, 105, 1, 0, // Skip to: 6701 /* 6340 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6357 /* 6345 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6357 /* 6352 */ MCD_OPC_Decode, 146, 12, 205, 1, // Opcode: VLD3DUPq32 /* 6357 */ MCD_OPC_CheckPredicate, 21, 83, 1, 0, // Skip to: 6701 /* 6362 */ MCD_OPC_Decode, 149, 12, 205, 1, // Opcode: VLD3DUPq32_UPD /* 6367 */ MCD_OPC_FilterValue, 15, 73, 1, 0, // Skip to: 6701 /* 6372 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 6375 */ MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6538 /* 6380 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6383 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6489 /* 6388 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6391 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6440 /* 6396 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6399 */ MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 6701 /* 6404 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6407 */ MCD_OPC_FilterValue, 233, 3, 32, 1, 0, // Skip to: 6701 /* 6413 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6430 /* 6418 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6430 /* 6425 */ MCD_OPC_Decode, 209, 12, 206, 1, // Opcode: VLD4DUPd8 /* 6430 */ MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 6701 /* 6435 */ MCD_OPC_Decode, 212, 12, 206, 1, // Opcode: VLD4DUPd8_UPD /* 6440 */ MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 6701 /* 6445 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6448 */ MCD_OPC_FilterValue, 2, 248, 0, 0, // Skip to: 6701 /* 6453 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6456 */ MCD_OPC_FilterValue, 233, 3, 239, 0, 0, // Skip to: 6701 /* 6462 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6479 /* 6467 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6479 /* 6474 */ MCD_OPC_Decode, 201, 12, 206, 1, // Opcode: VLD4DUPd16 /* 6479 */ MCD_OPC_CheckPredicate, 21, 217, 0, 0, // Skip to: 6701 /* 6484 */ MCD_OPC_Decode, 204, 12, 206, 1, // Opcode: VLD4DUPd16_UPD /* 6489 */ MCD_OPC_FilterValue, 1, 207, 0, 0, // Skip to: 6701 /* 6494 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6497 */ MCD_OPC_FilterValue, 2, 199, 0, 0, // Skip to: 6701 /* 6502 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6505 */ MCD_OPC_FilterValue, 233, 3, 190, 0, 0, // Skip to: 6701 /* 6511 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6528 /* 6516 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6528 /* 6523 */ MCD_OPC_Decode, 205, 12, 206, 1, // Opcode: VLD4DUPd32 /* 6528 */ MCD_OPC_CheckPredicate, 21, 168, 0, 0, // Skip to: 6701 /* 6533 */ MCD_OPC_Decode, 208, 12, 206, 1, // Opcode: VLD4DUPd32_UPD /* 6538 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 6701 /* 6543 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6546 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6652 /* 6551 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 6554 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6603 /* 6559 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6562 */ MCD_OPC_FilterValue, 2, 134, 0, 0, // Skip to: 6701 /* 6567 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6570 */ MCD_OPC_FilterValue, 233, 3, 125, 0, 0, // Skip to: 6701 /* 6576 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6593 /* 6581 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6593 /* 6588 */ MCD_OPC_Decode, 221, 12, 206, 1, // Opcode: VLD4DUPq8 /* 6593 */ MCD_OPC_CheckPredicate, 21, 103, 0, 0, // Skip to: 6701 /* 6598 */ MCD_OPC_Decode, 224, 12, 206, 1, // Opcode: VLD4DUPq8_UPD /* 6603 */ MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 6701 /* 6608 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6611 */ MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6701 /* 6616 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6619 */ MCD_OPC_FilterValue, 233, 3, 76, 0, 0, // Skip to: 6701 /* 6625 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6642 /* 6630 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6642 /* 6637 */ MCD_OPC_Decode, 213, 12, 206, 1, // Opcode: VLD4DUPq16 /* 6642 */ MCD_OPC_CheckPredicate, 21, 54, 0, 0, // Skip to: 6701 /* 6647 */ MCD_OPC_Decode, 216, 12, 206, 1, // Opcode: VLD4DUPq16_UPD /* 6652 */ MCD_OPC_FilterValue, 1, 44, 0, 0, // Skip to: 6701 /* 6657 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 6660 */ MCD_OPC_FilterValue, 2, 36, 0, 0, // Skip to: 6701 /* 6665 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 6668 */ MCD_OPC_FilterValue, 233, 3, 27, 0, 0, // Skip to: 6701 /* 6674 */ MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6691 /* 6679 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6691 /* 6686 */ MCD_OPC_Decode, 217, 12, 206, 1, // Opcode: VLD4DUPq32 /* 6691 */ MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6701 /* 6696 */ MCD_OPC_Decode, 220, 12, 206, 1, // Opcode: VLD4DUPq32_UPD /* 6701 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableThumb16[] = { /* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25 /* 8 */ MCD_OPC_CheckPredicate, 28, 181, 4, 0, // Skip to: 1218 /* 13 */ MCD_OPC_CheckField, 6, 6, 0, 174, 4, 0, // Skip to: 1218 /* 20 */ MCD_OPC_Decode, 236, 24, 207, 1, // Opcode: tMOVSr /* 25 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 47 /* 30 */ MCD_OPC_CheckPredicate, 28, 159, 4, 0, // Skip to: 1218 /* 35 */ MCD_OPC_CheckField, 11, 1, 1, 152, 4, 0, // Skip to: 1218 /* 42 */ MCD_OPC_Decode, 212, 24, 208, 1, // Opcode: tCMPi8 /* 47 */ MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 311 /* 52 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 55 */ MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 296 /* 60 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 63 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 116 /* 68 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 71 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 86 /* 76 */ MCD_OPC_CheckPredicate, 28, 113, 4, 0, // Skip to: 1218 /* 81 */ MCD_OPC_Decode, 140, 25, 207, 1, // Opcode: tTST /* 86 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101 /* 91 */ MCD_OPC_CheckPredicate, 28, 98, 4, 0, // Skip to: 1218 /* 96 */ MCD_OPC_Decode, 213, 24, 207, 1, // Opcode: tCMPr /* 101 */ MCD_OPC_FilterValue, 3, 88, 4, 0, // Skip to: 1218 /* 106 */ MCD_OPC_CheckPredicate, 28, 83, 4, 0, // Skip to: 1218 /* 111 */ MCD_OPC_Decode, 210, 24, 207, 1, // Opcode: tCMNz /* 116 */ MCD_OPC_FilterValue, 4, 51, 0, 0, // Skip to: 172 /* 121 */ MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 138 /* 126 */ MCD_OPC_CheckField, 3, 4, 13, 5, 0, 0, // Skip to: 138 /* 133 */ MCD_OPC_Decode, 189, 24, 209, 1, // Opcode: tADDrSP /* 138 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 162 /* 143 */ MCD_OPC_CheckField, 7, 1, 1, 12, 0, 0, // Skip to: 162 /* 150 */ MCD_OPC_CheckField, 0, 3, 5, 5, 0, 0, // Skip to: 162 /* 157 */ MCD_OPC_Decode, 193, 24, 209, 1, // Opcode: tADDspr /* 162 */ MCD_OPC_CheckPredicate, 28, 27, 4, 0, // Skip to: 1218 /* 167 */ MCD_OPC_Decode, 186, 24, 210, 1, // Opcode: tADDhirr /* 172 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 187 /* 177 */ MCD_OPC_CheckPredicate, 28, 12, 4, 0, // Skip to: 1218 /* 182 */ MCD_OPC_Decode, 211, 24, 211, 1, // Opcode: tCMPhir /* 187 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 202 /* 192 */ MCD_OPC_CheckPredicate, 28, 253, 3, 0, // Skip to: 1218 /* 197 */ MCD_OPC_Decode, 238, 24, 211, 1, // Opcode: tMOVr /* 202 */ MCD_OPC_FilterValue, 7, 243, 3, 0, // Skip to: 1218 /* 207 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 210 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 248 /* 215 */ MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 235 /* 220 */ MCD_OPC_CheckField, 2, 1, 1, 8, 0, 0, // Skip to: 235 /* 227 */ MCD_OPC_SoftFail, 3, 0, /* 230 */ MCD_OPC_Decode, 206, 24, 212, 1, // Opcode: tBXNS /* 235 */ MCD_OPC_CheckPredicate, 28, 210, 3, 0, // Skip to: 1218 /* 240 */ MCD_OPC_SoftFail, 7, 0, /* 243 */ MCD_OPC_Decode, 205, 24, 212, 1, // Opcode: tBX /* 248 */ MCD_OPC_FilterValue, 1, 197, 3, 0, // Skip to: 1218 /* 253 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 256 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 278 /* 261 */ MCD_OPC_CheckPredicate, 30, 184, 3, 0, // Skip to: 1218 /* 266 */ MCD_OPC_CheckField, 0, 2, 0, 177, 3, 0, // Skip to: 1218 /* 273 */ MCD_OPC_Decode, 204, 24, 212, 1, // Opcode: tBLXr /* 278 */ MCD_OPC_FilterValue, 1, 167, 3, 0, // Skip to: 1218 /* 283 */ MCD_OPC_CheckPredicate, 29, 162, 3, 0, // Skip to: 1218 /* 288 */ MCD_OPC_SoftFail, 3, 0, /* 291 */ MCD_OPC_Decode, 202, 24, 213, 1, // Opcode: tBLXNSr /* 296 */ MCD_OPC_FilterValue, 1, 149, 3, 0, // Skip to: 1218 /* 301 */ MCD_OPC_CheckPredicate, 28, 144, 3, 0, // Skip to: 1218 /* 306 */ MCD_OPC_Decode, 229, 24, 214, 1, // Opcode: tLDRpci /* 311 */ MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 439 /* 316 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... /* 319 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 334 /* 324 */ MCD_OPC_CheckPredicate, 28, 121, 3, 0, // Skip to: 1218 /* 329 */ MCD_OPC_Decode, 130, 25, 215, 1, // Opcode: tSTRr /* 334 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 349 /* 339 */ MCD_OPC_CheckPredicate, 28, 106, 3, 0, // Skip to: 1218 /* 344 */ MCD_OPC_Decode, 128, 25, 215, 1, // Opcode: tSTRHr /* 349 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 364 /* 354 */ MCD_OPC_CheckPredicate, 28, 91, 3, 0, // Skip to: 1218 /* 359 */ MCD_OPC_Decode, 254, 24, 215, 1, // Opcode: tSTRBr /* 364 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 379 /* 369 */ MCD_OPC_CheckPredicate, 28, 76, 3, 0, // Skip to: 1218 /* 374 */ MCD_OPC_Decode, 226, 24, 215, 1, // Opcode: tLDRSB /* 379 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 394 /* 384 */ MCD_OPC_CheckPredicate, 28, 61, 3, 0, // Skip to: 1218 /* 389 */ MCD_OPC_Decode, 230, 24, 215, 1, // Opcode: tLDRr /* 394 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 409 /* 399 */ MCD_OPC_CheckPredicate, 28, 46, 3, 0, // Skip to: 1218 /* 404 */ MCD_OPC_Decode, 225, 24, 215, 1, // Opcode: tLDRHr /* 409 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 424 /* 414 */ MCD_OPC_CheckPredicate, 28, 31, 3, 0, // Skip to: 1218 /* 419 */ MCD_OPC_Decode, 223, 24, 215, 1, // Opcode: tLDRBr /* 424 */ MCD_OPC_FilterValue, 7, 21, 3, 0, // Skip to: 1218 /* 429 */ MCD_OPC_CheckPredicate, 28, 16, 3, 0, // Skip to: 1218 /* 434 */ MCD_OPC_Decode, 227, 24, 215, 1, // Opcode: tLDRSH /* 439 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 477 /* 444 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 447 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 462 /* 452 */ MCD_OPC_CheckPredicate, 28, 249, 2, 0, // Skip to: 1218 /* 457 */ MCD_OPC_Decode, 129, 25, 216, 1, // Opcode: tSTRi /* 462 */ MCD_OPC_FilterValue, 1, 239, 2, 0, // Skip to: 1218 /* 467 */ MCD_OPC_CheckPredicate, 28, 234, 2, 0, // Skip to: 1218 /* 472 */ MCD_OPC_Decode, 228, 24, 216, 1, // Opcode: tLDRi /* 477 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 515 /* 482 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 500 /* 490 */ MCD_OPC_CheckPredicate, 28, 211, 2, 0, // Skip to: 1218 /* 495 */ MCD_OPC_Decode, 253, 24, 216, 1, // Opcode: tSTRBi /* 500 */ MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 1218 /* 505 */ MCD_OPC_CheckPredicate, 28, 196, 2, 0, // Skip to: 1218 /* 510 */ MCD_OPC_Decode, 222, 24, 216, 1, // Opcode: tLDRBi /* 515 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 553 /* 520 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 523 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 538 /* 528 */ MCD_OPC_CheckPredicate, 28, 173, 2, 0, // Skip to: 1218 /* 533 */ MCD_OPC_Decode, 255, 24, 216, 1, // Opcode: tSTRHi /* 538 */ MCD_OPC_FilterValue, 1, 163, 2, 0, // Skip to: 1218 /* 543 */ MCD_OPC_CheckPredicate, 28, 158, 2, 0, // Skip to: 1218 /* 548 */ MCD_OPC_Decode, 224, 24, 216, 1, // Opcode: tLDRHi /* 553 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 591 /* 558 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 561 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 576 /* 566 */ MCD_OPC_CheckPredicate, 28, 135, 2, 0, // Skip to: 1218 /* 571 */ MCD_OPC_Decode, 131, 25, 217, 1, // Opcode: tSTRspi /* 576 */ MCD_OPC_FilterValue, 1, 125, 2, 0, // Skip to: 1218 /* 581 */ MCD_OPC_CheckPredicate, 28, 120, 2, 0, // Skip to: 1218 /* 586 */ MCD_OPC_Decode, 231, 24, 217, 1, // Opcode: tLDRspi /* 591 */ MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 629 /* 596 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 599 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 614 /* 604 */ MCD_OPC_CheckPredicate, 28, 97, 2, 0, // Skip to: 1218 /* 609 */ MCD_OPC_Decode, 194, 24, 218, 1, // Opcode: tADR /* 614 */ MCD_OPC_FilterValue, 1, 87, 2, 0, // Skip to: 1218 /* 619 */ MCD_OPC_CheckPredicate, 28, 82, 2, 0, // Skip to: 1218 /* 624 */ MCD_OPC_Decode, 190, 24, 218, 1, // Opcode: tADDrSPi /* 629 */ MCD_OPC_FilterValue, 11, 187, 1, 0, // Skip to: 1077 /* 634 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 637 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 790 /* 642 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 645 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 775 /* 650 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 653 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 714 /* 658 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 676 /* 666 */ MCD_OPC_CheckPredicate, 28, 35, 2, 0, // Skip to: 1218 /* 671 */ MCD_OPC_Decode, 192, 24, 219, 1, // Opcode: tADDspi /* 676 */ MCD_OPC_FilterValue, 1, 25, 2, 0, // Skip to: 1218 /* 681 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 684 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 699 /* 689 */ MCD_OPC_CheckPredicate, 31, 12, 2, 0, // Skip to: 1218 /* 694 */ MCD_OPC_Decode, 138, 25, 207, 1, // Opcode: tSXTH /* 699 */ MCD_OPC_FilterValue, 1, 2, 2, 0, // Skip to: 1218 /* 704 */ MCD_OPC_CheckPredicate, 31, 253, 1, 0, // Skip to: 1218 /* 709 */ MCD_OPC_Decode, 137, 25, 207, 1, // Opcode: tSXTB /* 714 */ MCD_OPC_FilterValue, 1, 243, 1, 0, // Skip to: 1218 /* 719 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 722 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 737 /* 727 */ MCD_OPC_CheckPredicate, 28, 230, 1, 0, // Skip to: 1218 /* 732 */ MCD_OPC_Decode, 135, 25, 219, 1, // Opcode: tSUBspi /* 737 */ MCD_OPC_FilterValue, 1, 220, 1, 0, // Skip to: 1218 /* 742 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 745 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 760 /* 750 */ MCD_OPC_CheckPredicate, 31, 207, 1, 0, // Skip to: 1218 /* 755 */ MCD_OPC_Decode, 143, 25, 207, 1, // Opcode: tUXTH /* 760 */ MCD_OPC_FilterValue, 1, 197, 1, 0, // Skip to: 1218 /* 765 */ MCD_OPC_CheckPredicate, 31, 192, 1, 0, // Skip to: 1218 /* 770 */ MCD_OPC_Decode, 142, 25, 207, 1, // Opcode: tUXTB /* 775 */ MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 1218 /* 780 */ MCD_OPC_CheckPredicate, 32, 177, 1, 0, // Skip to: 1218 /* 785 */ MCD_OPC_Decode, 209, 24, 220, 1, // Opcode: tCBZ /* 790 */ MCD_OPC_FilterValue, 1, 95, 0, 0, // Skip to: 890 /* 795 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 813 /* 803 */ MCD_OPC_CheckPredicate, 28, 154, 1, 0, // Skip to: 1218 /* 808 */ MCD_OPC_Decode, 244, 24, 221, 1, // Opcode: tPUSH /* 813 */ MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 1218 /* 818 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... /* 821 */ MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 839 /* 826 */ MCD_OPC_CheckPredicate, 33, 131, 1, 0, // Skip to: 1218 /* 831 */ MCD_OPC_SoftFail, 7, 16, /* 834 */ MCD_OPC_Decode, 149, 23, 222, 1, // Opcode: t2SETPAN /* 839 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 868 /* 844 */ MCD_OPC_CheckPredicate, 34, 113, 1, 0, // Skip to: 1218 /* 849 */ MCD_OPC_CheckField, 4, 1, 1, 106, 1, 0, // Skip to: 1218 /* 856 */ MCD_OPC_CheckField, 0, 3, 0, 99, 1, 0, // Skip to: 1218 /* 863 */ MCD_OPC_Decode, 251, 24, 222, 1, // Opcode: tSETEND /* 868 */ MCD_OPC_FilterValue, 3, 89, 1, 0, // Skip to: 1218 /* 873 */ MCD_OPC_CheckPredicate, 28, 84, 1, 0, // Skip to: 1218 /* 878 */ MCD_OPC_CheckField, 3, 1, 0, 77, 1, 0, // Skip to: 1218 /* 885 */ MCD_OPC_Decode, 214, 24, 223, 1, // Opcode: tCPS /* 890 */ MCD_OPC_FilterValue, 2, 114, 0, 0, // Skip to: 1009 /* 895 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 898 */ MCD_OPC_FilterValue, 0, 91, 0, 0, // Skip to: 994 /* 903 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 906 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 928 /* 911 */ MCD_OPC_CheckPredicate, 31, 46, 1, 0, // Skip to: 1218 /* 916 */ MCD_OPC_CheckField, 9, 1, 1, 39, 1, 0, // Skip to: 1218 /* 923 */ MCD_OPC_Decode, 245, 24, 207, 1, // Opcode: tREV /* 928 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 950 /* 933 */ MCD_OPC_CheckPredicate, 31, 24, 1, 0, // Skip to: 1218 /* 938 */ MCD_OPC_CheckField, 9, 1, 1, 17, 1, 0, // Skip to: 1218 /* 945 */ MCD_OPC_Decode, 246, 24, 207, 1, // Opcode: tREV16 /* 950 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 972 /* 955 */ MCD_OPC_CheckPredicate, 35, 2, 1, 0, // Skip to: 1218 /* 960 */ MCD_OPC_CheckField, 9, 1, 1, 251, 0, 0, // Skip to: 1218 /* 967 */ MCD_OPC_Decode, 217, 24, 224, 1, // Opcode: tHLT /* 972 */ MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1218 /* 977 */ MCD_OPC_CheckPredicate, 31, 236, 0, 0, // Skip to: 1218 /* 982 */ MCD_OPC_CheckField, 9, 1, 1, 229, 0, 0, // Skip to: 1218 /* 989 */ MCD_OPC_Decode, 247, 24, 207, 1, // Opcode: tREVSH /* 994 */ MCD_OPC_FilterValue, 1, 219, 0, 0, // Skip to: 1218 /* 999 */ MCD_OPC_CheckPredicate, 32, 214, 0, 0, // Skip to: 1218 /* 1004 */ MCD_OPC_Decode, 208, 24, 220, 1, // Opcode: tCBNZ /* 1009 */ MCD_OPC_FilterValue, 3, 204, 0, 0, // Skip to: 1218 /* 1014 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 1017 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1032 /* 1022 */ MCD_OPC_CheckPredicate, 28, 191, 0, 0, // Skip to: 1218 /* 1027 */ MCD_OPC_Decode, 243, 24, 225, 1, // Opcode: tPOP /* 1032 */ MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1218 /* 1037 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 1040 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1055 /* 1045 */ MCD_OPC_CheckPredicate, 28, 168, 0, 0, // Skip to: 1218 /* 1050 */ MCD_OPC_Decode, 200, 24, 226, 1, // Opcode: tBKPT /* 1055 */ MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 1218 /* 1060 */ MCD_OPC_CheckPredicate, 36, 153, 0, 0, // Skip to: 1218 /* 1065 */ MCD_OPC_CheckField, 0, 4, 0, 146, 0, 0, // Skip to: 1218 /* 1072 */ MCD_OPC_Decode, 216, 24, 227, 1, // Opcode: tHINT /* 1077 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 1115 /* 1082 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 1085 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1100 /* 1090 */ MCD_OPC_CheckPredicate, 28, 123, 0, 0, // Skip to: 1218 /* 1095 */ MCD_OPC_Decode, 252, 24, 228, 1, // Opcode: tSTMIA_UPD /* 1100 */ MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 1218 /* 1105 */ MCD_OPC_CheckPredicate, 28, 108, 0, 0, // Skip to: 1218 /* 1110 */ MCD_OPC_Decode, 221, 24, 229, 1, // Opcode: tLDMIA /* 1115 */ MCD_OPC_FilterValue, 13, 76, 0, 0, // Skip to: 1196 /* 1120 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... /* 1123 */ MCD_OPC_FilterValue, 249, 29, 9, 0, 0, // Skip to: 1138 /* 1129 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 1153 /* 1134 */ MCD_OPC_Decode, 144, 25, 51, // Opcode: t__brkdiv0 /* 1138 */ MCD_OPC_FilterValue, 254, 29, 9, 0, 0, // Skip to: 1153 /* 1144 */ MCD_OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 1153 /* 1149 */ MCD_OPC_Decode, 139, 25, 51, // Opcode: tTRAP /* 1153 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1156 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1171 /* 1161 */ MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 1186 /* 1166 */ MCD_OPC_Decode, 141, 25, 226, 1, // Opcode: tUDF /* 1171 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1186 /* 1176 */ MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 1186 /* 1181 */ MCD_OPC_Decode, 136, 25, 226, 1, // Opcode: tSVC /* 1186 */ MCD_OPC_CheckPredicate, 28, 27, 0, 0, // Skip to: 1218 /* 1191 */ MCD_OPC_Decode, 207, 24, 230, 1, // Opcode: tBcc /* 1196 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1218 /* 1201 */ MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 1218 /* 1206 */ MCD_OPC_CheckField, 11, 1, 0, 5, 0, 0, // Skip to: 1218 /* 1213 */ MCD_OPC_Decode, 198, 24, 231, 1, // Opcode: tB /* 1218 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableThumb32[] = { /* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 3 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39 /* 8 */ MCD_OPC_CheckPredicate, 37, 55, 0, 0, // Skip to: 68 /* 13 */ MCD_OPC_CheckField, 27, 5, 30, 48, 0, 0, // Skip to: 68 /* 20 */ MCD_OPC_CheckField, 14, 2, 3, 41, 0, 0, // Skip to: 68 /* 27 */ MCD_OPC_CheckField, 0, 1, 0, 34, 0, 0, // Skip to: 68 /* 34 */ MCD_OPC_Decode, 203, 24, 232, 1, // Opcode: tBLXi /* 39 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 68 /* 44 */ MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 68 /* 49 */ MCD_OPC_CheckField, 27, 5, 30, 12, 0, 0, // Skip to: 68 /* 56 */ MCD_OPC_CheckField, 14, 2, 3, 5, 0, 0, // Skip to: 68 /* 63 */ MCD_OPC_Decode, 201, 24, 233, 1, // Opcode: tBL /* 68 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableThumb216[] = { /* 0 */ MCD_OPC_CheckPredicate, 38, 13, 0, 0, // Skip to: 18 /* 5 */ MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, 0, // Skip to: 18 /* 13 */ MCD_OPC_Decode, 250, 21, 234, 1, // Opcode: t2IT /* 18 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableThumb232[] = { /* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... /* 3 */ MCD_OPC_FilterValue, 29, 124, 8, 0, // Skip to: 2180 /* 8 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 11 */ MCD_OPC_FilterValue, 0, 223, 1, 0, // Skip to: 495 /* 16 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... /* 19 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 73 /* 24 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 27 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 50 /* 32 */ MCD_OPC_CheckPredicate, 39, 210, 31, 0, // Skip to: 8183 /* 37 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 201, 31, 0, // Skip to: 8183 /* 46 */ MCD_OPC_Decode, 194, 23, 83, // Opcode: t2SRSDB /* 50 */ MCD_OPC_FilterValue, 1, 192, 31, 0, // Skip to: 8183 /* 55 */ MCD_OPC_CheckPredicate, 39, 187, 31, 0, // Skip to: 8183 /* 60 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 178, 31, 0, // Skip to: 8183 /* 69 */ MCD_OPC_Decode, 130, 23, 81, // Opcode: t2RFEDB /* 73 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 125 /* 78 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 81 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 110 /* 86 */ MCD_OPC_CheckPredicate, 38, 156, 31, 0, // Skip to: 8183 /* 91 */ MCD_OPC_CheckField, 15, 1, 0, 149, 31, 0, // Skip to: 8183 /* 98 */ MCD_OPC_CheckField, 13, 1, 0, 142, 31, 0, // Skip to: 8183 /* 105 */ MCD_OPC_Decode, 228, 23, 235, 1, // Opcode: t2STMIA /* 110 */ MCD_OPC_FilterValue, 1, 132, 31, 0, // Skip to: 8183 /* 115 */ MCD_OPC_CheckPredicate, 38, 127, 31, 0, // Skip to: 8183 /* 120 */ MCD_OPC_Decode, 150, 22, 236, 1, // Opcode: t2LDMIA /* 125 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 177 /* 130 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 133 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 162 /* 138 */ MCD_OPC_CheckPredicate, 38, 104, 31, 0, // Skip to: 8183 /* 143 */ MCD_OPC_CheckField, 15, 1, 0, 97, 31, 0, // Skip to: 8183 /* 150 */ MCD_OPC_CheckField, 13, 1, 0, 90, 31, 0, // Skip to: 8183 /* 157 */ MCD_OPC_Decode, 226, 23, 235, 1, // Opcode: t2STMDB /* 162 */ MCD_OPC_FilterValue, 1, 80, 31, 0, // Skip to: 8183 /* 167 */ MCD_OPC_CheckPredicate, 38, 75, 31, 0, // Skip to: 8183 /* 172 */ MCD_OPC_Decode, 148, 22, 236, 1, // Opcode: t2LDMDB /* 177 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 231 /* 182 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 185 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 208 /* 190 */ MCD_OPC_CheckPredicate, 39, 52, 31, 0, // Skip to: 8183 /* 195 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 43, 31, 0, // Skip to: 8183 /* 204 */ MCD_OPC_Decode, 196, 23, 83, // Opcode: t2SRSIA /* 208 */ MCD_OPC_FilterValue, 1, 34, 31, 0, // Skip to: 8183 /* 213 */ MCD_OPC_CheckPredicate, 39, 29, 31, 0, // Skip to: 8183 /* 218 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 20, 31, 0, // Skip to: 8183 /* 227 */ MCD_OPC_Decode, 132, 23, 81, // Opcode: t2RFEIA /* 231 */ MCD_OPC_FilterValue, 4, 83, 0, 0, // Skip to: 319 /* 236 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 261 /* 241 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 261 /* 248 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 261 /* 256 */ MCD_OPC_Decode, 145, 24, 237, 1, // Opcode: t2TSTrr /* 261 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 285 /* 266 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 285 /* 273 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 285 /* 280 */ MCD_OPC_Decode, 146, 24, 238, 1, // Opcode: t2TSTrs /* 285 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 309 /* 290 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 309 /* 297 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 309 /* 304 */ MCD_OPC_Decode, 207, 21, 239, 1, // Opcode: t2ANDrr /* 309 */ MCD_OPC_CheckPredicate, 38, 189, 30, 0, // Skip to: 8183 /* 314 */ MCD_OPC_Decode, 208, 21, 240, 1, // Opcode: t2ANDrs /* 319 */ MCD_OPC_FilterValue, 5, 83, 0, 0, // Skip to: 407 /* 324 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 349 /* 329 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 349 /* 336 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 349 /* 344 */ MCD_OPC_Decode, 141, 24, 237, 1, // Opcode: t2TEQrr /* 349 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 373 /* 354 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 373 /* 361 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 373 /* 368 */ MCD_OPC_Decode, 142, 24, 238, 1, // Opcode: t2TEQrs /* 373 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 397 /* 378 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 397 /* 385 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 397 /* 392 */ MCD_OPC_Decode, 245, 21, 239, 1, // Opcode: t2EORrr /* 397 */ MCD_OPC_CheckPredicate, 38, 101, 30, 0, // Skip to: 8183 /* 402 */ MCD_OPC_Decode, 246, 21, 240, 1, // Opcode: t2EORrs /* 407 */ MCD_OPC_FilterValue, 6, 91, 30, 0, // Skip to: 8183 /* 412 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 437 /* 417 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 437 /* 424 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 437 /* 432 */ MCD_OPC_Decode, 224, 21, 237, 1, // Opcode: t2CMNzrr /* 437 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 461 /* 442 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 461 /* 449 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 461 /* 456 */ MCD_OPC_Decode, 225, 21, 238, 1, // Opcode: t2CMNzrs /* 461 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 485 /* 466 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 485 /* 473 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 485 /* 480 */ MCD_OPC_Decode, 203, 21, 241, 1, // Opcode: t2ADDrr /* 485 */ MCD_OPC_CheckPredicate, 38, 13, 30, 0, // Skip to: 8183 /* 490 */ MCD_OPC_Decode, 204, 21, 242, 1, // Opcode: t2ADDrs /* 495 */ MCD_OPC_FilterValue, 1, 86, 1, 0, // Skip to: 842 /* 500 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... /* 503 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 557 /* 508 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 511 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 534 /* 516 */ MCD_OPC_CheckPredicate, 39, 238, 29, 0, // Skip to: 8183 /* 521 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 229, 29, 0, // Skip to: 8183 /* 530 */ MCD_OPC_Decode, 195, 23, 83, // Opcode: t2SRSDB_UPD /* 534 */ MCD_OPC_FilterValue, 1, 220, 29, 0, // Skip to: 8183 /* 539 */ MCD_OPC_CheckPredicate, 39, 215, 29, 0, // Skip to: 8183 /* 544 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 206, 29, 0, // Skip to: 8183 /* 553 */ MCD_OPC_Decode, 131, 23, 81, // Opcode: t2RFEDBW /* 557 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 609 /* 562 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 565 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 594 /* 570 */ MCD_OPC_CheckPredicate, 38, 184, 29, 0, // Skip to: 8183 /* 575 */ MCD_OPC_CheckField, 15, 1, 0, 177, 29, 0, // Skip to: 8183 /* 582 */ MCD_OPC_CheckField, 13, 1, 0, 170, 29, 0, // Skip to: 8183 /* 589 */ MCD_OPC_Decode, 229, 23, 243, 1, // Opcode: t2STMIA_UPD /* 594 */ MCD_OPC_FilterValue, 1, 160, 29, 0, // Skip to: 8183 /* 599 */ MCD_OPC_CheckPredicate, 38, 155, 29, 0, // Skip to: 8183 /* 604 */ MCD_OPC_Decode, 151, 22, 244, 1, // Opcode: t2LDMIA_UPD /* 609 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 661 /* 614 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 617 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 646 /* 622 */ MCD_OPC_CheckPredicate, 38, 132, 29, 0, // Skip to: 8183 /* 627 */ MCD_OPC_CheckField, 15, 1, 0, 125, 29, 0, // Skip to: 8183 /* 634 */ MCD_OPC_CheckField, 13, 1, 0, 118, 29, 0, // Skip to: 8183 /* 641 */ MCD_OPC_Decode, 227, 23, 243, 1, // Opcode: t2STMDB_UPD /* 646 */ MCD_OPC_FilterValue, 1, 108, 29, 0, // Skip to: 8183 /* 651 */ MCD_OPC_CheckPredicate, 38, 103, 29, 0, // Skip to: 8183 /* 656 */ MCD_OPC_Decode, 149, 22, 244, 1, // Opcode: t2LDMDB_UPD /* 661 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 715 /* 666 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 669 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 692 /* 674 */ MCD_OPC_CheckPredicate, 39, 80, 29, 0, // Skip to: 8183 /* 679 */ MCD_OPC_CheckField, 5, 15, 128, 220, 1, 71, 29, 0, // Skip to: 8183 /* 688 */ MCD_OPC_Decode, 197, 23, 83, // Opcode: t2SRSIA_UPD /* 692 */ MCD_OPC_FilterValue, 1, 62, 29, 0, // Skip to: 8183 /* 697 */ MCD_OPC_CheckPredicate, 39, 57, 29, 0, // Skip to: 8183 /* 702 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 48, 29, 0, // Skip to: 8183 /* 711 */ MCD_OPC_Decode, 133, 23, 81, // Opcode: t2RFEIAW /* 715 */ MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 754 /* 720 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 744 /* 725 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 744 /* 732 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 744 /* 739 */ MCD_OPC_Decode, 215, 21, 239, 1, // Opcode: t2BICrr /* 744 */ MCD_OPC_CheckPredicate, 38, 10, 29, 0, // Skip to: 8183 /* 749 */ MCD_OPC_Decode, 216, 21, 240, 1, // Opcode: t2BICrs /* 754 */ MCD_OPC_FilterValue, 7, 0, 29, 0, // Skip to: 8183 /* 759 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 784 /* 764 */ MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 784 /* 771 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 784 /* 779 */ MCD_OPC_Decode, 227, 21, 237, 1, // Opcode: t2CMPrr /* 784 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 808 /* 789 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 808 /* 796 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 808 /* 803 */ MCD_OPC_Decode, 228, 21, 238, 1, // Opcode: t2CMPrs /* 808 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 832 /* 813 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 832 /* 820 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 832 /* 827 */ MCD_OPC_Decode, 130, 24, 241, 1, // Opcode: t2SUBrr /* 832 */ MCD_OPC_CheckPredicate, 38, 178, 28, 0, // Skip to: 8183 /* 837 */ MCD_OPC_Decode, 131, 24, 242, 1, // Opcode: t2SUBrs /* 842 */ MCD_OPC_FilterValue, 2, 70, 4, 0, // Skip to: 1941 /* 847 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... /* 850 */ MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1579 /* 855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 858 */ MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 1219 /* 863 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 866 */ MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 984 /* 871 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 874 */ MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 899 /* 879 */ MCD_OPC_CheckPredicate, 29, 90, 0, 0, // Skip to: 974 /* 884 */ MCD_OPC_CheckField, 12, 4, 15, 83, 0, 0, // Skip to: 974 /* 891 */ MCD_OPC_SoftFail, 63, 0, /* 894 */ MCD_OPC_Decode, 147, 24, 245, 1, // Opcode: t2TT /* 899 */ MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 924 /* 904 */ MCD_OPC_CheckPredicate, 29, 65, 0, 0, // Skip to: 974 /* 909 */ MCD_OPC_CheckField, 12, 4, 15, 58, 0, 0, // Skip to: 974 /* 916 */ MCD_OPC_SoftFail, 63, 0, /* 919 */ MCD_OPC_Decode, 150, 24, 245, 1, // Opcode: t2TTT /* 924 */ MCD_OPC_FilterValue, 2, 20, 0, 0, // Skip to: 949 /* 929 */ MCD_OPC_CheckPredicate, 29, 40, 0, 0, // Skip to: 974 /* 934 */ MCD_OPC_CheckField, 12, 4, 15, 33, 0, 0, // Skip to: 974 /* 941 */ MCD_OPC_SoftFail, 63, 0, /* 944 */ MCD_OPC_Decode, 148, 24, 245, 1, // Opcode: t2TTA /* 949 */ MCD_OPC_FilterValue, 3, 20, 0, 0, // Skip to: 974 /* 954 */ MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 974 /* 959 */ MCD_OPC_CheckField, 12, 4, 15, 8, 0, 0, // Skip to: 974 /* 966 */ MCD_OPC_SoftFail, 63, 0, /* 969 */ MCD_OPC_Decode, 149, 24, 245, 1, // Opcode: t2TTAT /* 974 */ MCD_OPC_CheckPredicate, 32, 36, 28, 0, // Skip to: 8183 /* 979 */ MCD_OPC_Decode, 239, 23, 246, 1, // Opcode: t2STREX /* 984 */ MCD_OPC_FilterValue, 1, 26, 28, 0, // Skip to: 8183 /* 989 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 992 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1014 /* 997 */ MCD_OPC_CheckPredicate, 32, 13, 28, 0, // Skip to: 8183 /* 1002 */ MCD_OPC_CheckField, 8, 4, 15, 6, 28, 0, // Skip to: 8183 /* 1009 */ MCD_OPC_Decode, 240, 23, 247, 1, // Opcode: t2STREXB /* 1014 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1036 /* 1019 */ MCD_OPC_CheckPredicate, 32, 247, 27, 0, // Skip to: 8183 /* 1024 */ MCD_OPC_CheckField, 8, 4, 15, 240, 27, 0, // Skip to: 8183 /* 1031 */ MCD_OPC_Decode, 242, 23, 247, 1, // Opcode: t2STREXH /* 1036 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1051 /* 1041 */ MCD_OPC_CheckPredicate, 39, 225, 27, 0, // Skip to: 8183 /* 1046 */ MCD_OPC_Decode, 241, 23, 248, 1, // Opcode: t2STREXD /* 1051 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1080 /* 1056 */ MCD_OPC_CheckPredicate, 40, 210, 27, 0, // Skip to: 8183 /* 1061 */ MCD_OPC_CheckField, 8, 4, 15, 203, 27, 0, // Skip to: 8183 /* 1068 */ MCD_OPC_CheckField, 0, 4, 15, 196, 27, 0, // Skip to: 8183 /* 1075 */ MCD_OPC_Decode, 220, 23, 249, 1, // Opcode: t2STLB /* 1080 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1109 /* 1085 */ MCD_OPC_CheckPredicate, 40, 181, 27, 0, // Skip to: 8183 /* 1090 */ MCD_OPC_CheckField, 8, 4, 15, 174, 27, 0, // Skip to: 8183 /* 1097 */ MCD_OPC_CheckField, 0, 4, 15, 167, 27, 0, // Skip to: 8183 /* 1104 */ MCD_OPC_Decode, 225, 23, 249, 1, // Opcode: t2STLH /* 1109 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1138 /* 1114 */ MCD_OPC_CheckPredicate, 40, 152, 27, 0, // Skip to: 8183 /* 1119 */ MCD_OPC_CheckField, 8, 4, 15, 145, 27, 0, // Skip to: 8183 /* 1126 */ MCD_OPC_CheckField, 0, 4, 15, 138, 27, 0, // Skip to: 8183 /* 1133 */ MCD_OPC_Decode, 219, 23, 249, 1, // Opcode: t2STL /* 1138 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1160 /* 1143 */ MCD_OPC_CheckPredicate, 41, 123, 27, 0, // Skip to: 8183 /* 1148 */ MCD_OPC_CheckField, 8, 4, 15, 116, 27, 0, // Skip to: 8183 /* 1155 */ MCD_OPC_Decode, 222, 23, 247, 1, // Opcode: t2STLEXB /* 1160 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1182 /* 1165 */ MCD_OPC_CheckPredicate, 41, 101, 27, 0, // Skip to: 8183 /* 1170 */ MCD_OPC_CheckField, 8, 4, 15, 94, 27, 0, // Skip to: 8183 /* 1177 */ MCD_OPC_Decode, 224, 23, 247, 1, // Opcode: t2STLEXH /* 1182 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1204 /* 1187 */ MCD_OPC_CheckPredicate, 41, 79, 27, 0, // Skip to: 8183 /* 1192 */ MCD_OPC_CheckField, 8, 4, 15, 72, 27, 0, // Skip to: 8183 /* 1199 */ MCD_OPC_Decode, 221, 23, 247, 1, // Opcode: t2STLEX /* 1204 */ MCD_OPC_FilterValue, 15, 62, 27, 0, // Skip to: 8183 /* 1209 */ MCD_OPC_CheckPredicate, 42, 57, 27, 0, // Skip to: 8183 /* 1214 */ MCD_OPC_Decode, 223, 23, 248, 1, // Opcode: t2STLEXD /* 1219 */ MCD_OPC_FilterValue, 1, 47, 27, 0, // Skip to: 8183 /* 1224 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 1227 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1249 /* 1232 */ MCD_OPC_CheckPredicate, 32, 34, 27, 0, // Skip to: 8183 /* 1237 */ MCD_OPC_CheckField, 8, 4, 15, 27, 27, 0, // Skip to: 8183 /* 1244 */ MCD_OPC_Decode, 162, 22, 250, 1, // Opcode: t2LDREX /* 1249 */ MCD_OPC_FilterValue, 1, 17, 27, 0, // Skip to: 8183 /* 1254 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 1257 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1280 /* 1262 */ MCD_OPC_CheckPredicate, 38, 4, 27, 0, // Skip to: 8183 /* 1267 */ MCD_OPC_CheckField, 8, 8, 240, 1, 252, 26, 0, // Skip to: 8183 /* 1275 */ MCD_OPC_Decode, 138, 24, 251, 1, // Opcode: t2TBB /* 1280 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 1303 /* 1285 */ MCD_OPC_CheckPredicate, 38, 237, 26, 0, // Skip to: 8183 /* 1290 */ MCD_OPC_CheckField, 8, 8, 240, 1, 229, 26, 0, // Skip to: 8183 /* 1298 */ MCD_OPC_Decode, 139, 24, 251, 1, // Opcode: t2TBH /* 1303 */ MCD_OPC_FilterValue, 4, 24, 0, 0, // Skip to: 1332 /* 1308 */ MCD_OPC_CheckPredicate, 32, 214, 26, 0, // Skip to: 8183 /* 1313 */ MCD_OPC_CheckField, 8, 4, 15, 207, 26, 0, // Skip to: 8183 /* 1320 */ MCD_OPC_CheckField, 0, 4, 15, 200, 26, 0, // Skip to: 8183 /* 1327 */ MCD_OPC_Decode, 163, 22, 249, 1, // Opcode: t2LDREXB /* 1332 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1361 /* 1337 */ MCD_OPC_CheckPredicate, 32, 185, 26, 0, // Skip to: 8183 /* 1342 */ MCD_OPC_CheckField, 8, 4, 15, 178, 26, 0, // Skip to: 8183 /* 1349 */ MCD_OPC_CheckField, 0, 4, 15, 171, 26, 0, // Skip to: 8183 /* 1356 */ MCD_OPC_Decode, 165, 22, 249, 1, // Opcode: t2LDREXH /* 1361 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1383 /* 1366 */ MCD_OPC_CheckPredicate, 39, 156, 26, 0, // Skip to: 8183 /* 1371 */ MCD_OPC_CheckField, 0, 4, 15, 149, 26, 0, // Skip to: 8183 /* 1378 */ MCD_OPC_Decode, 164, 22, 252, 1, // Opcode: t2LDREXD /* 1383 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1412 /* 1388 */ MCD_OPC_CheckPredicate, 40, 134, 26, 0, // Skip to: 8183 /* 1393 */ MCD_OPC_CheckField, 8, 4, 15, 127, 26, 0, // Skip to: 8183 /* 1400 */ MCD_OPC_CheckField, 0, 4, 15, 120, 26, 0, // Skip to: 8183 /* 1407 */ MCD_OPC_Decode, 254, 21, 249, 1, // Opcode: t2LDAB /* 1412 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1441 /* 1417 */ MCD_OPC_CheckPredicate, 40, 105, 26, 0, // Skip to: 8183 /* 1422 */ MCD_OPC_CheckField, 8, 4, 15, 98, 26, 0, // Skip to: 8183 /* 1429 */ MCD_OPC_CheckField, 0, 4, 15, 91, 26, 0, // Skip to: 8183 /* 1436 */ MCD_OPC_Decode, 131, 22, 249, 1, // Opcode: t2LDAH /* 1441 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1470 /* 1446 */ MCD_OPC_CheckPredicate, 40, 76, 26, 0, // Skip to: 8183 /* 1451 */ MCD_OPC_CheckField, 8, 4, 15, 69, 26, 0, // Skip to: 8183 /* 1458 */ MCD_OPC_CheckField, 0, 4, 15, 62, 26, 0, // Skip to: 8183 /* 1465 */ MCD_OPC_Decode, 253, 21, 249, 1, // Opcode: t2LDA /* 1470 */ MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 1499 /* 1475 */ MCD_OPC_CheckPredicate, 41, 47, 26, 0, // Skip to: 8183 /* 1480 */ MCD_OPC_CheckField, 8, 4, 15, 40, 26, 0, // Skip to: 8183 /* 1487 */ MCD_OPC_CheckField, 0, 4, 15, 33, 26, 0, // Skip to: 8183 /* 1494 */ MCD_OPC_Decode, 128, 22, 249, 1, // Opcode: t2LDAEXB /* 1499 */ MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 1528 /* 1504 */ MCD_OPC_CheckPredicate, 41, 18, 26, 0, // Skip to: 8183 /* 1509 */ MCD_OPC_CheckField, 8, 4, 15, 11, 26, 0, // Skip to: 8183 /* 1516 */ MCD_OPC_CheckField, 0, 4, 15, 4, 26, 0, // Skip to: 8183 /* 1523 */ MCD_OPC_Decode, 130, 22, 249, 1, // Opcode: t2LDAEXH /* 1528 */ MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 1557 /* 1533 */ MCD_OPC_CheckPredicate, 41, 245, 25, 0, // Skip to: 8183 /* 1538 */ MCD_OPC_CheckField, 8, 4, 15, 238, 25, 0, // Skip to: 8183 /* 1545 */ MCD_OPC_CheckField, 0, 4, 15, 231, 25, 0, // Skip to: 8183 /* 1552 */ MCD_OPC_Decode, 255, 21, 249, 1, // Opcode: t2LDAEX /* 1557 */ MCD_OPC_FilterValue, 15, 221, 25, 0, // Skip to: 8183 /* 1562 */ MCD_OPC_CheckPredicate, 42, 216, 25, 0, // Skip to: 8183 /* 1567 */ MCD_OPC_CheckField, 0, 4, 15, 209, 25, 0, // Skip to: 8183 /* 1574 */ MCD_OPC_Decode, 129, 22, 252, 1, // Opcode: t2LDAEXD /* 1579 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1617 /* 1584 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1587 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1602 /* 1592 */ MCD_OPC_CheckPredicate, 38, 186, 25, 0, // Skip to: 8183 /* 1597 */ MCD_OPC_Decode, 238, 23, 253, 1, // Opcode: t2STRDi8 /* 1602 */ MCD_OPC_FilterValue, 1, 176, 25, 0, // Skip to: 8183 /* 1607 */ MCD_OPC_CheckPredicate, 38, 171, 25, 0, // Skip to: 8183 /* 1612 */ MCD_OPC_Decode, 161, 22, 253, 1, // Opcode: t2LDRDi8 /* 1617 */ MCD_OPC_FilterValue, 2, 233, 0, 0, // Skip to: 1855 /* 1622 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 1625 */ MCD_OPC_FilterValue, 0, 173, 0, 0, // Skip to: 1803 /* 1630 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 1633 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1673 /* 1638 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1641 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 1702 /* 1646 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1663 /* 1651 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1663 /* 1658 */ MCD_OPC_Decode, 207, 22, 254, 1, // Opcode: t2MOVr /* 1663 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1702 /* 1668 */ MCD_OPC_Decode, 229, 22, 239, 1, // Opcode: t2ORRrr /* 1673 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 1702 /* 1678 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1702 /* 1683 */ MCD_OPC_CheckField, 16, 4, 15, 12, 0, 0, // Skip to: 1702 /* 1690 */ MCD_OPC_CheckField, 12, 3, 0, 5, 0, 0, // Skip to: 1702 /* 1697 */ MCD_OPC_Decode, 136, 23, 255, 1, // Opcode: t2RRX /* 1702 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 1705 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1727 /* 1710 */ MCD_OPC_CheckPredicate, 38, 78, 0, 0, // Skip to: 1793 /* 1715 */ MCD_OPC_CheckField, 16, 4, 15, 71, 0, 0, // Skip to: 1793 /* 1722 */ MCD_OPC_Decode, 194, 22, 128, 2, // Opcode: t2LSLri /* 1727 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1749 /* 1732 */ MCD_OPC_CheckPredicate, 38, 56, 0, 0, // Skip to: 1793 /* 1737 */ MCD_OPC_CheckField, 16, 4, 15, 49, 0, 0, // Skip to: 1793 /* 1744 */ MCD_OPC_Decode, 196, 22, 128, 2, // Opcode: t2LSRri /* 1749 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1771 /* 1754 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1793 /* 1759 */ MCD_OPC_CheckField, 16, 4, 15, 27, 0, 0, // Skip to: 1793 /* 1766 */ MCD_OPC_Decode, 209, 21, 128, 2, // Opcode: t2ASRri /* 1771 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1793 /* 1776 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1793 /* 1781 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1793 /* 1788 */ MCD_OPC_Decode, 134, 23, 128, 2, // Opcode: t2RORri /* 1793 */ MCD_OPC_CheckPredicate, 38, 241, 24, 0, // Skip to: 8183 /* 1798 */ MCD_OPC_Decode, 230, 22, 240, 1, // Opcode: t2ORRrs /* 1803 */ MCD_OPC_FilterValue, 1, 231, 24, 0, // Skip to: 8183 /* 1808 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 1811 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1833 /* 1816 */ MCD_OPC_CheckPredicate, 43, 218, 24, 0, // Skip to: 8183 /* 1821 */ MCD_OPC_CheckField, 20, 1, 0, 211, 24, 0, // Skip to: 8183 /* 1828 */ MCD_OPC_Decode, 231, 22, 129, 2, // Opcode: t2PKHBT /* 1833 */ MCD_OPC_FilterValue, 2, 201, 24, 0, // Skip to: 8183 /* 1838 */ MCD_OPC_CheckPredicate, 43, 196, 24, 0, // Skip to: 8183 /* 1843 */ MCD_OPC_CheckField, 20, 1, 0, 189, 24, 0, // Skip to: 8183 /* 1850 */ MCD_OPC_Decode, 232, 22, 129, 2, // Opcode: t2PKHTB /* 1855 */ MCD_OPC_FilterValue, 3, 179, 24, 0, // Skip to: 8183 /* 1860 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 1863 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 1902 /* 1868 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1892 /* 1873 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1892 /* 1880 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1892 /* 1887 */ MCD_OPC_Decode, 199, 21, 239, 1, // Opcode: t2ADCrr /* 1892 */ MCD_OPC_CheckPredicate, 38, 142, 24, 0, // Skip to: 8183 /* 1897 */ MCD_OPC_Decode, 200, 21, 240, 1, // Opcode: t2ADCrs /* 1902 */ MCD_OPC_FilterValue, 1, 132, 24, 0, // Skip to: 8183 /* 1907 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1931 /* 1912 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1931 /* 1919 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1931 /* 1926 */ MCD_OPC_Decode, 138, 23, 239, 1, // Opcode: t2RSBrr /* 1931 */ MCD_OPC_CheckPredicate, 38, 103, 24, 0, // Skip to: 8183 /* 1936 */ MCD_OPC_Decode, 139, 23, 240, 1, // Opcode: t2RSBrs /* 1941 */ MCD_OPC_FilterValue, 3, 93, 24, 0, // Skip to: 8183 /* 1946 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... /* 1949 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1987 /* 1954 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1957 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1972 /* 1962 */ MCD_OPC_CheckPredicate, 38, 72, 24, 0, // Skip to: 8183 /* 1967 */ MCD_OPC_Decode, 236, 23, 130, 2, // Opcode: t2STRD_POST /* 1972 */ MCD_OPC_FilterValue, 1, 62, 24, 0, // Skip to: 8183 /* 1977 */ MCD_OPC_CheckPredicate, 38, 57, 24, 0, // Skip to: 8183 /* 1982 */ MCD_OPC_Decode, 159, 22, 131, 2, // Opcode: t2LDRD_POST /* 1987 */ MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 2050 /* 1992 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 1995 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2010 /* 2000 */ MCD_OPC_CheckPredicate, 38, 34, 24, 0, // Skip to: 8183 /* 2005 */ MCD_OPC_Decode, 237, 23, 132, 2, // Opcode: t2STRD_PRE /* 2010 */ MCD_OPC_FilterValue, 1, 24, 24, 0, // Skip to: 8183 /* 2015 */ MCD_OPC_CheckPredicate, 44, 20, 0, 0, // Skip to: 2040 /* 2020 */ MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 2040 /* 2027 */ MCD_OPC_CheckField, 0, 20, 255, 210, 63, 4, 0, 0, // Skip to: 2040 /* 2036 */ MCD_OPC_Decode, 150, 23, 51, // Opcode: t2SG /* 2040 */ MCD_OPC_CheckPredicate, 38, 250, 23, 0, // Skip to: 8183 /* 2045 */ MCD_OPC_Decode, 160, 22, 133, 2, // Opcode: t2LDRD_PRE /* 2050 */ MCD_OPC_FilterValue, 2, 78, 0, 0, // Skip to: 2133 /* 2055 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 2058 */ MCD_OPC_FilterValue, 0, 232, 23, 0, // Skip to: 8183 /* 2063 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 2066 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2106 /* 2071 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2074 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2106 /* 2079 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2096 /* 2084 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2096 /* 2091 */ MCD_OPC_Decode, 223, 22, 255, 1, // Opcode: t2MVNr /* 2096 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 2106 /* 2101 */ MCD_OPC_Decode, 226, 22, 239, 1, // Opcode: t2ORNrr /* 2106 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2123 /* 2111 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2123 /* 2118 */ MCD_OPC_Decode, 224, 22, 134, 2, // Opcode: t2MVNs /* 2123 */ MCD_OPC_CheckPredicate, 38, 167, 23, 0, // Skip to: 8183 /* 2128 */ MCD_OPC_Decode, 227, 22, 240, 1, // Opcode: t2ORNrs /* 2133 */ MCD_OPC_FilterValue, 3, 157, 23, 0, // Skip to: 8183 /* 2138 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 2141 */ MCD_OPC_FilterValue, 0, 149, 23, 0, // Skip to: 8183 /* 2146 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2170 /* 2151 */ MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2170 /* 2158 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2170 /* 2165 */ MCD_OPC_Decode, 144, 23, 239, 1, // Opcode: t2SBCrr /* 2170 */ MCD_OPC_CheckPredicate, 38, 120, 23, 0, // Skip to: 8183 /* 2175 */ MCD_OPC_Decode, 145, 23, 240, 1, // Opcode: t2SBCrs /* 2180 */ MCD_OPC_FilterValue, 30, 153, 5, 0, // Skip to: 3618 /* 2185 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... /* 2188 */ MCD_OPC_FilterValue, 0, 179, 2, 0, // Skip to: 2884 /* 2193 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 2196 */ MCD_OPC_FilterValue, 0, 160, 0, 0, // Skip to: 2361 /* 2201 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 2204 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2243 /* 2209 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2233 /* 2214 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2233 /* 2221 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2233 /* 2228 */ MCD_OPC_Decode, 144, 24, 135, 2, // Opcode: t2TSTri /* 2233 */ MCD_OPC_CheckPredicate, 38, 57, 23, 0, // Skip to: 8183 /* 2238 */ MCD_OPC_Decode, 206, 21, 136, 2, // Opcode: t2ANDri /* 2243 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2258 /* 2248 */ MCD_OPC_CheckPredicate, 38, 42, 23, 0, // Skip to: 8183 /* 2253 */ MCD_OPC_Decode, 214, 21, 136, 2, // Opcode: t2BICri /* 2258 */ MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 2290 /* 2263 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2280 /* 2268 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2280 /* 2275 */ MCD_OPC_Decode, 205, 22, 137, 2, // Opcode: t2MOVi /* 2280 */ MCD_OPC_CheckPredicate, 38, 10, 23, 0, // Skip to: 8183 /* 2285 */ MCD_OPC_Decode, 228, 22, 136, 2, // Opcode: t2ORRri /* 2290 */ MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2322 /* 2295 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2312 /* 2300 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2312 /* 2307 */ MCD_OPC_Decode, 222, 22, 137, 2, // Opcode: t2MVNi /* 2312 */ MCD_OPC_CheckPredicate, 38, 234, 22, 0, // Skip to: 8183 /* 2317 */ MCD_OPC_Decode, 225, 22, 136, 2, // Opcode: t2ORNri /* 2322 */ MCD_OPC_FilterValue, 4, 224, 22, 0, // Skip to: 8183 /* 2327 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2351 /* 2332 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2351 /* 2339 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2351 /* 2346 */ MCD_OPC_Decode, 140, 24, 135, 2, // Opcode: t2TEQri /* 2351 */ MCD_OPC_CheckPredicate, 38, 195, 22, 0, // Skip to: 8183 /* 2356 */ MCD_OPC_Decode, 244, 21, 136, 2, // Opcode: t2EORri /* 2361 */ MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 2492 /* 2366 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... /* 2369 */ MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2408 /* 2374 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2398 /* 2379 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2398 /* 2386 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2398 /* 2393 */ MCD_OPC_Decode, 223, 21, 135, 2, // Opcode: t2CMNri /* 2398 */ MCD_OPC_CheckPredicate, 38, 148, 22, 0, // Skip to: 8183 /* 2403 */ MCD_OPC_Decode, 201, 21, 138, 2, // Opcode: t2ADDri /* 2408 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2423 /* 2413 */ MCD_OPC_CheckPredicate, 38, 133, 22, 0, // Skip to: 8183 /* 2418 */ MCD_OPC_Decode, 198, 21, 136, 2, // Opcode: t2ADCri /* 2423 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2438 /* 2428 */ MCD_OPC_CheckPredicate, 38, 118, 22, 0, // Skip to: 8183 /* 2433 */ MCD_OPC_Decode, 143, 23, 136, 2, // Opcode: t2SBCri /* 2438 */ MCD_OPC_FilterValue, 5, 34, 0, 0, // Skip to: 2477 /* 2443 */ MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2467 /* 2448 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2467 /* 2455 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2467 /* 2462 */ MCD_OPC_Decode, 226, 21, 135, 2, // Opcode: t2CMPri /* 2467 */ MCD_OPC_CheckPredicate, 38, 79, 22, 0, // Skip to: 8183 /* 2472 */ MCD_OPC_Decode, 128, 24, 138, 2, // Opcode: t2SUBri /* 2477 */ MCD_OPC_FilterValue, 6, 69, 22, 0, // Skip to: 8183 /* 2482 */ MCD_OPC_CheckPredicate, 38, 64, 22, 0, // Skip to: 8183 /* 2487 */ MCD_OPC_Decode, 137, 23, 136, 2, // Opcode: t2RSBri /* 2492 */ MCD_OPC_FilterValue, 2, 132, 0, 0, // Skip to: 2629 /* 2497 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2500 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2577 /* 2505 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 2508 */ MCD_OPC_FilterValue, 0, 38, 22, 0, // Skip to: 8183 /* 2513 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 2516 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2538 /* 2521 */ MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 2560 /* 2526 */ MCD_OPC_CheckField, 23, 1, 0, 27, 0, 0, // Skip to: 2560 /* 2533 */ MCD_OPC_Decode, 202, 21, 139, 2, // Opcode: t2ADDri12 /* 2538 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2560 /* 2543 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2560 /* 2548 */ MCD_OPC_CheckField, 23, 1, 1, 5, 0, 0, // Skip to: 2560 /* 2555 */ MCD_OPC_Decode, 129, 24, 139, 2, // Opcode: t2SUBri12 /* 2560 */ MCD_OPC_CheckPredicate, 38, 242, 21, 0, // Skip to: 8183 /* 2565 */ MCD_OPC_CheckField, 16, 4, 15, 235, 21, 0, // Skip to: 8183 /* 2572 */ MCD_OPC_Decode, 205, 21, 140, 2, // Opcode: t2ADR /* 2577 */ MCD_OPC_FilterValue, 1, 225, 21, 0, // Skip to: 8183 /* 2582 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 2585 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2607 /* 2590 */ MCD_OPC_CheckPredicate, 32, 212, 21, 0, // Skip to: 8183 /* 2595 */ MCD_OPC_CheckField, 20, 2, 0, 205, 21, 0, // Skip to: 8183 /* 2602 */ MCD_OPC_Decode, 206, 22, 141, 2, // Opcode: t2MOVi16 /* 2607 */ MCD_OPC_FilterValue, 1, 195, 21, 0, // Skip to: 8183 /* 2612 */ MCD_OPC_CheckPredicate, 32, 190, 21, 0, // Skip to: 8183 /* 2617 */ MCD_OPC_CheckField, 20, 2, 0, 183, 21, 0, // Skip to: 8183 /* 2624 */ MCD_OPC_Decode, 204, 22, 141, 2, // Opcode: t2MOVTi16 /* 2629 */ MCD_OPC_FilterValue, 3, 173, 21, 0, // Skip to: 8183 /* 2634 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... /* 2637 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2714 /* 2642 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 2645 */ MCD_OPC_FilterValue, 0, 157, 21, 0, // Skip to: 8183 /* 2650 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 2653 */ MCD_OPC_FilterValue, 0, 149, 21, 0, // Skip to: 8183 /* 2658 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 2661 */ MCD_OPC_FilterValue, 0, 141, 21, 0, // Skip to: 8183 /* 2666 */ MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2704 /* 2671 */ MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2704 /* 2678 */ MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2704 /* 2685 */ MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2704 /* 2692 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2704 /* 2699 */ MCD_OPC_Decode, 199, 23, 142, 2, // Opcode: t2SSAT16 /* 2704 */ MCD_OPC_CheckPredicate, 38, 98, 21, 0, // Skip to: 8183 /* 2709 */ MCD_OPC_Decode, 198, 23, 143, 2, // Opcode: t2SSAT /* 2714 */ MCD_OPC_FilterValue, 1, 66, 0, 0, // Skip to: 2785 /* 2719 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 2722 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2737 /* 2727 */ MCD_OPC_CheckPredicate, 38, 75, 21, 0, // Skip to: 8183 /* 2732 */ MCD_OPC_Decode, 146, 23, 144, 2, // Opcode: t2SBFX /* 2737 */ MCD_OPC_FilterValue, 2, 65, 21, 0, // Skip to: 8183 /* 2742 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 2745 */ MCD_OPC_FilterValue, 0, 57, 21, 0, // Skip to: 8183 /* 2750 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 2753 */ MCD_OPC_FilterValue, 0, 49, 21, 0, // Skip to: 8183 /* 2758 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2775 /* 2763 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2775 /* 2770 */ MCD_OPC_Decode, 212, 21, 145, 2, // Opcode: t2BFC /* 2775 */ MCD_OPC_CheckPredicate, 38, 27, 21, 0, // Skip to: 8183 /* 2780 */ MCD_OPC_Decode, 213, 21, 146, 2, // Opcode: t2BFI /* 2785 */ MCD_OPC_FilterValue, 2, 72, 0, 0, // Skip to: 2862 /* 2790 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 2793 */ MCD_OPC_FilterValue, 0, 9, 21, 0, // Skip to: 8183 /* 2798 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 2801 */ MCD_OPC_FilterValue, 0, 1, 21, 0, // Skip to: 8183 /* 2806 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 2809 */ MCD_OPC_FilterValue, 0, 249, 20, 0, // Skip to: 8183 /* 2814 */ MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2852 /* 2819 */ MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2852 /* 2826 */ MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2852 /* 2833 */ MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2852 /* 2840 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2852 /* 2847 */ MCD_OPC_Decode, 175, 24, 142, 2, // Opcode: t2USAT16 /* 2852 */ MCD_OPC_CheckPredicate, 38, 206, 20, 0, // Skip to: 8183 /* 2857 */ MCD_OPC_Decode, 174, 24, 143, 2, // Opcode: t2USAT /* 2862 */ MCD_OPC_FilterValue, 3, 196, 20, 0, // Skip to: 8183 /* 2867 */ MCD_OPC_CheckPredicate, 38, 191, 20, 0, // Skip to: 8183 /* 2872 */ MCD_OPC_CheckField, 20, 2, 0, 184, 20, 0, // Skip to: 8183 /* 2879 */ MCD_OPC_Decode, 154, 24, 144, 2, // Opcode: t2UBFX /* 2884 */ MCD_OPC_FilterValue, 1, 174, 20, 0, // Skip to: 8183 /* 2889 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 2892 */ MCD_OPC_FilterValue, 0, 187, 2, 0, // Skip to: 3596 /* 2897 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... /* 2900 */ MCD_OPC_FilterValue, 0, 158, 20, 0, // Skip to: 8183 /* 2905 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... /* 2908 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2937 /* 2913 */ MCD_OPC_CheckPredicate, 46, 166, 0, 0, // Skip to: 3084 /* 2918 */ MCD_OPC_CheckField, 16, 11, 143, 15, 158, 0, 0, // Skip to: 3084 /* 2926 */ MCD_OPC_CheckField, 13, 1, 0, 151, 0, 0, // Skip to: 3084 /* 2933 */ MCD_OPC_Decode, 239, 21, 51, // Opcode: t2DCPS1 /* 2937 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 2966 /* 2942 */ MCD_OPC_CheckPredicate, 46, 137, 0, 0, // Skip to: 3084 /* 2947 */ MCD_OPC_CheckField, 16, 11, 143, 15, 129, 0, 0, // Skip to: 3084 /* 2955 */ MCD_OPC_CheckField, 13, 1, 0, 122, 0, 0, // Skip to: 3084 /* 2962 */ MCD_OPC_Decode, 240, 21, 51, // Opcode: t2DCPS2 /* 2966 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 2995 /* 2971 */ MCD_OPC_CheckPredicate, 46, 108, 0, 0, // Skip to: 3084 /* 2976 */ MCD_OPC_CheckField, 16, 11, 143, 15, 100, 0, 0, // Skip to: 3084 /* 2984 */ MCD_OPC_CheckField, 13, 1, 0, 93, 0, 0, // Skip to: 3084 /* 2991 */ MCD_OPC_Decode, 241, 21, 51, // Opcode: t2DCPS3 /* 2995 */ MCD_OPC_FilterValue, 18, 24, 0, 0, // Skip to: 3024 /* 3000 */ MCD_OPC_CheckPredicate, 47, 79, 0, 0, // Skip to: 3084 /* 3005 */ MCD_OPC_CheckField, 16, 11, 175, 7, 71, 0, 0, // Skip to: 3084 /* 3013 */ MCD_OPC_CheckField, 13, 1, 0, 64, 0, 0, // Skip to: 3084 /* 3020 */ MCD_OPC_Decode, 143, 24, 51, // Opcode: t2TSB /* 3024 */ MCD_OPC_FilterValue, 128, 30, 24, 0, 0, // Skip to: 3054 /* 3030 */ MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3084 /* 3035 */ MCD_OPC_CheckField, 20, 7, 60, 42, 0, 0, // Skip to: 3084 /* 3042 */ MCD_OPC_CheckField, 13, 1, 0, 35, 0, 0, // Skip to: 3084 /* 3049 */ MCD_OPC_Decode, 217, 21, 147, 2, // Opcode: t2BXJ /* 3054 */ MCD_OPC_FilterValue, 175, 30, 24, 0, 0, // Skip to: 3084 /* 3060 */ MCD_OPC_CheckPredicate, 48, 19, 0, 0, // Skip to: 3084 /* 3065 */ MCD_OPC_CheckField, 16, 11, 191, 7, 11, 0, 0, // Skip to: 3084 /* 3073 */ MCD_OPC_CheckField, 13, 1, 0, 4, 0, 0, // Skip to: 3084 /* 3080 */ MCD_OPC_Decode, 221, 21, 51, // Opcode: t2CLREX /* 3084 */ MCD_OPC_ExtractField, 16, 11, // Inst{26-16} ... /* 3087 */ MCD_OPC_FilterValue, 175, 7, 131, 0, 0, // Skip to: 3224 /* 3093 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 3096 */ MCD_OPC_FilterValue, 0, 68, 0, 0, // Skip to: 3169 /* 3101 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 3104 */ MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 3389 /* 3109 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 3112 */ MCD_OPC_FilterValue, 0, 16, 1, 0, // Skip to: 3389 /* 3117 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 3120 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3152 /* 3125 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3142 /* 3130 */ MCD_OPC_CheckField, 4, 4, 15, 5, 0, 0, // Skip to: 3142 /* 3137 */ MCD_OPC_Decode, 238, 21, 148, 2, // Opcode: t2DBG /* 3142 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3152 /* 3147 */ MCD_OPC_Decode, 247, 21, 226, 1, // Opcode: t2HINT /* 3152 */ MCD_OPC_CheckPredicate, 39, 232, 0, 0, // Skip to: 3389 /* 3157 */ MCD_OPC_CheckField, 0, 5, 0, 225, 0, 0, // Skip to: 3389 /* 3164 */ MCD_OPC_Decode, 230, 21, 149, 2, // Opcode: t2CPS2p /* 3169 */ MCD_OPC_FilterValue, 1, 215, 0, 0, // Skip to: 3389 /* 3174 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 3177 */ MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 3389 /* 3182 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 3185 */ MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 3389 /* 3190 */ MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3214 /* 3195 */ MCD_OPC_CheckField, 9, 2, 0, 12, 0, 0, // Skip to: 3214 /* 3202 */ MCD_OPC_CheckField, 5, 3, 0, 5, 0, 0, // Skip to: 3214 /* 3209 */ MCD_OPC_Decode, 229, 21, 149, 2, // Opcode: t2CPS1p /* 3214 */ MCD_OPC_CheckPredicate, 39, 170, 0, 0, // Skip to: 3389 /* 3219 */ MCD_OPC_Decode, 231, 21, 149, 2, // Opcode: t2CPS3p /* 3224 */ MCD_OPC_FilterValue, 191, 7, 69, 0, 0, // Skip to: 3299 /* 3230 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... /* 3233 */ MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 3255 /* 3239 */ MCD_OPC_CheckPredicate, 49, 145, 0, 0, // Skip to: 3389 /* 3244 */ MCD_OPC_CheckField, 13, 1, 0, 138, 0, 0, // Skip to: 3389 /* 3251 */ MCD_OPC_Decode, 243, 21, 61, // Opcode: t2DSB /* 3255 */ MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 3277 /* 3261 */ MCD_OPC_CheckPredicate, 49, 123, 0, 0, // Skip to: 3389 /* 3266 */ MCD_OPC_CheckField, 13, 1, 0, 116, 0, 0, // Skip to: 3389 /* 3273 */ MCD_OPC_Decode, 242, 21, 61, // Opcode: t2DMB /* 3277 */ MCD_OPC_FilterValue, 246, 1, 106, 0, 0, // Skip to: 3389 /* 3283 */ MCD_OPC_CheckPredicate, 49, 101, 0, 0, // Skip to: 3389 /* 3288 */ MCD_OPC_CheckField, 13, 1, 0, 94, 0, 0, // Skip to: 3389 /* 3295 */ MCD_OPC_Decode, 249, 21, 62, // Opcode: t2ISB /* 3299 */ MCD_OPC_FilterValue, 222, 7, 24, 0, 0, // Skip to: 3329 /* 3305 */ MCD_OPC_CheckPredicate, 39, 79, 0, 0, // Skip to: 3389 /* 3310 */ MCD_OPC_CheckField, 13, 1, 0, 72, 0, 0, // Skip to: 3389 /* 3317 */ MCD_OPC_CheckField, 8, 4, 15, 65, 0, 0, // Skip to: 3389 /* 3324 */ MCD_OPC_Decode, 255, 23, 226, 1, // Opcode: t2SUBS_PC_LR /* 3329 */ MCD_OPC_FilterValue, 239, 7, 24, 0, 0, // Skip to: 3359 /* 3335 */ MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3389 /* 3340 */ MCD_OPC_CheckField, 13, 1, 0, 42, 0, 0, // Skip to: 3389 /* 3347 */ MCD_OPC_CheckField, 0, 8, 0, 35, 0, 0, // Skip to: 3389 /* 3354 */ MCD_OPC_Decode, 214, 22, 150, 2, // Opcode: t2MRS_AR /* 3359 */ MCD_OPC_FilterValue, 255, 7, 24, 0, 0, // Skip to: 3389 /* 3365 */ MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3389 /* 3370 */ MCD_OPC_CheckField, 13, 1, 0, 12, 0, 0, // Skip to: 3389 /* 3377 */ MCD_OPC_CheckField, 0, 8, 0, 5, 0, 0, // Skip to: 3389 /* 3384 */ MCD_OPC_Decode, 217, 22, 150, 2, // Opcode: t2MRSsys_AR /* 3389 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 3392 */ MCD_OPC_FilterValue, 0, 122, 0, 0, // Skip to: 3519 /* 3397 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... /* 3400 */ MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3452 /* 3405 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... /* 3408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3430 /* 3413 */ MCD_OPC_CheckPredicate, 39, 123, 0, 0, // Skip to: 3541 /* 3418 */ MCD_OPC_CheckField, 0, 5, 0, 116, 0, 0, // Skip to: 3541 /* 3425 */ MCD_OPC_Decode, 218, 22, 151, 2, // Opcode: t2MSR_AR /* 3430 */ MCD_OPC_FilterValue, 1, 106, 0, 0, // Skip to: 3541 /* 3435 */ MCD_OPC_CheckPredicate, 50, 101, 0, 0, // Skip to: 3541 /* 3440 */ MCD_OPC_CheckField, 0, 4, 0, 94, 0, 0, // Skip to: 3541 /* 3447 */ MCD_OPC_Decode, 220, 22, 152, 2, // Opcode: t2MSRbanked /* 3452 */ MCD_OPC_FilterValue, 31, 24, 0, 0, // Skip to: 3481 /* 3457 */ MCD_OPC_CheckPredicate, 50, 79, 0, 0, // Skip to: 3541 /* 3462 */ MCD_OPC_CheckField, 5, 3, 1, 72, 0, 0, // Skip to: 3541 /* 3469 */ MCD_OPC_CheckField, 0, 4, 0, 65, 0, 0, // Skip to: 3541 /* 3476 */ MCD_OPC_Decode, 216, 22, 153, 2, // Opcode: t2MRSbanked /* 3481 */ MCD_OPC_FilterValue, 63, 55, 0, 0, // Skip to: 3541 /* 3486 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3489 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3504 /* 3494 */ MCD_OPC_CheckPredicate, 51, 42, 0, 0, // Skip to: 3541 /* 3499 */ MCD_OPC_Decode, 248, 21, 154, 2, // Opcode: t2HVC /* 3504 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 3541 /* 3509 */ MCD_OPC_CheckPredicate, 52, 27, 0, 0, // Skip to: 3541 /* 3514 */ MCD_OPC_Decode, 157, 23, 155, 2, // Opcode: t2SMC /* 3519 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3541 /* 3524 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3541 /* 3529 */ MCD_OPC_CheckField, 20, 7, 127, 5, 0, 0, // Skip to: 3541 /* 3536 */ MCD_OPC_Decode, 155, 24, 154, 2, // Opcode: t2UDF /* 3541 */ MCD_OPC_ExtractField, 21, 6, // Inst{26-21} ... /* 3544 */ MCD_OPC_FilterValue, 28, 15, 0, 0, // Skip to: 3564 /* 3549 */ MCD_OPC_CheckPredicate, 53, 32, 0, 0, // Skip to: 3586 /* 3554 */ MCD_OPC_SoftFail, 128, 198, 64 /* 0x102300 */, 0, /* 3559 */ MCD_OPC_Decode, 219, 22, 156, 2, // Opcode: t2MSR_M /* 3564 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 3586 /* 3569 */ MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 3586 /* 3574 */ MCD_OPC_SoftFail, 128, 192, 64 /* 0x102000 */, 128, 128, 60 /* 0xf0000 */, /* 3581 */ MCD_OPC_Decode, 215, 22, 157, 2, // Opcode: t2MRS_M /* 3586 */ MCD_OPC_CheckPredicate, 38, 240, 17, 0, // Skip to: 8183 /* 3591 */ MCD_OPC_Decode, 218, 21, 158, 2, // Opcode: t2Bcc /* 3596 */ MCD_OPC_FilterValue, 1, 230, 17, 0, // Skip to: 8183 /* 3601 */ MCD_OPC_CheckPredicate, 32, 225, 17, 0, // Skip to: 8183 /* 3606 */ MCD_OPC_CheckField, 14, 1, 0, 218, 17, 0, // Skip to: 8183 /* 3613 */ MCD_OPC_Decode, 211, 21, 159, 2, // Opcode: t2B /* 3618 */ MCD_OPC_FilterValue, 31, 208, 17, 0, // Skip to: 8183 /* 3623 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 3626 */ MCD_OPC_FilterValue, 0, 96, 6, 0, // Skip to: 5263 /* 3631 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... /* 3634 */ MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 3995 /* 3639 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 3642 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 3772 /* 3647 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 3650 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 3757 /* 3655 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 3658 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3680 /* 3663 */ MCD_OPC_CheckPredicate, 38, 163, 17, 0, // Skip to: 8183 /* 3668 */ MCD_OPC_CheckField, 6, 4, 0, 156, 17, 0, // Skip to: 8183 /* 3675 */ MCD_OPC_Decode, 235, 23, 160, 2, // Opcode: t2STRBs /* 3680 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3702 /* 3685 */ MCD_OPC_CheckPredicate, 38, 141, 17, 0, // Skip to: 8183 /* 3690 */ MCD_OPC_CheckField, 8, 1, 1, 134, 17, 0, // Skip to: 8183 /* 3697 */ MCD_OPC_Decode, 231, 23, 161, 2, // Opcode: t2STRB_POST /* 3702 */ MCD_OPC_FilterValue, 3, 124, 17, 0, // Skip to: 8183 /* 3707 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 3710 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3742 /* 3715 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3732 /* 3720 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 3732 /* 3727 */ MCD_OPC_Decode, 230, 23, 162, 2, // Opcode: t2STRBT /* 3732 */ MCD_OPC_CheckPredicate, 38, 94, 17, 0, // Skip to: 8183 /* 3737 */ MCD_OPC_Decode, 234, 23, 163, 2, // Opcode: t2STRBi8 /* 3742 */ MCD_OPC_FilterValue, 1, 84, 17, 0, // Skip to: 8183 /* 3747 */ MCD_OPC_CheckPredicate, 38, 79, 17, 0, // Skip to: 8183 /* 3752 */ MCD_OPC_Decode, 232, 23, 161, 2, // Opcode: t2STRB_PRE /* 3757 */ MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8183 /* 3762 */ MCD_OPC_CheckPredicate, 38, 64, 17, 0, // Skip to: 8183 /* 3767 */ MCD_OPC_Decode, 233, 23, 164, 2, // Opcode: t2STRBi12 /* 3772 */ MCD_OPC_FilterValue, 1, 54, 17, 0, // Skip to: 8183 /* 3777 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 3780 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 3928 /* 3785 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 3788 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3828 /* 3793 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 3796 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 3960 /* 3801 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3818 /* 3806 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3818 /* 3813 */ MCD_OPC_Decode, 239, 22, 165, 2, // Opcode: t2PLDs /* 3818 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 3960 /* 3823 */ MCD_OPC_Decode, 158, 22, 165, 2, // Opcode: t2LDRBs /* 3828 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3850 /* 3833 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 3960 /* 3838 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 3960 /* 3845 */ MCD_OPC_Decode, 153, 22, 161, 2, // Opcode: t2LDRB_POST /* 3850 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 3960 /* 3855 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 3858 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 3913 /* 3863 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 3866 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3888 /* 3871 */ MCD_OPC_CheckPredicate, 38, 27, 0, 0, // Skip to: 3903 /* 3876 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 3903 /* 3883 */ MCD_OPC_Decode, 237, 22, 166, 2, // Opcode: t2PLDi8 /* 3888 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3903 /* 3893 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3903 /* 3898 */ MCD_OPC_Decode, 152, 22, 167, 2, // Opcode: t2LDRBT /* 3903 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 3960 /* 3908 */ MCD_OPC_Decode, 156, 22, 166, 2, // Opcode: t2LDRBi8 /* 3913 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 3960 /* 3918 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 3960 /* 3923 */ MCD_OPC_Decode, 154, 22, 161, 2, // Opcode: t2LDRB_PRE /* 3928 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 3960 /* 3933 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3950 /* 3938 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3950 /* 3945 */ MCD_OPC_Decode, 236, 22, 168, 2, // Opcode: t2PLDi12 /* 3950 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3960 /* 3955 */ MCD_OPC_Decode, 155, 22, 168, 2, // Opcode: t2LDRBi12 /* 3960 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 3963 */ MCD_OPC_FilterValue, 15, 119, 16, 0, // Skip to: 8183 /* 3968 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3985 /* 3973 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3985 /* 3980 */ MCD_OPC_Decode, 238, 22, 169, 2, // Opcode: t2PLDpci /* 3985 */ MCD_OPC_CheckPredicate, 38, 97, 16, 0, // Skip to: 8183 /* 3990 */ MCD_OPC_Decode, 157, 22, 169, 2, // Opcode: t2LDRBpci /* 3995 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 4226 /* 4000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4003 */ MCD_OPC_FilterValue, 1, 79, 16, 0, // Skip to: 8183 /* 4008 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 4011 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 4159 /* 4016 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 4019 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4059 /* 4024 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 4027 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 4191 /* 4032 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4049 /* 4037 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4049 /* 4044 */ MCD_OPC_Decode, 243, 22, 165, 2, // Opcode: t2PLIs /* 4049 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 4191 /* 4054 */ MCD_OPC_Decode, 179, 22, 165, 2, // Opcode: t2LDRSBs /* 4059 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4081 /* 4064 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 4191 /* 4069 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 4191 /* 4076 */ MCD_OPC_Decode, 174, 22, 161, 2, // Opcode: t2LDRSB_POST /* 4081 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 4191 /* 4086 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 4089 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 4144 /* 4094 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 4097 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4119 /* 4102 */ MCD_OPC_CheckPredicate, 54, 27, 0, 0, // Skip to: 4134 /* 4107 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 4134 /* 4114 */ MCD_OPC_Decode, 241, 22, 166, 2, // Opcode: t2PLIi8 /* 4119 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4134 /* 4124 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4134 /* 4129 */ MCD_OPC_Decode, 173, 22, 167, 2, // Opcode: t2LDRSBT /* 4134 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 4191 /* 4139 */ MCD_OPC_Decode, 177, 22, 166, 2, // Opcode: t2LDRSBi8 /* 4144 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4191 /* 4149 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 4191 /* 4154 */ MCD_OPC_Decode, 175, 22, 161, 2, // Opcode: t2LDRSB_PRE /* 4159 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 4191 /* 4164 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4181 /* 4169 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4181 /* 4176 */ MCD_OPC_Decode, 240, 22, 168, 2, // Opcode: t2PLIi12 /* 4181 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4191 /* 4186 */ MCD_OPC_Decode, 176, 22, 168, 2, // Opcode: t2LDRSBi12 /* 4191 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 4194 */ MCD_OPC_FilterValue, 15, 144, 15, 0, // Skip to: 8183 /* 4199 */ MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4216 /* 4204 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4216 /* 4211 */ MCD_OPC_Decode, 242, 22, 169, 2, // Opcode: t2PLIpci /* 4216 */ MCD_OPC_CheckPredicate, 38, 122, 15, 0, // Skip to: 8183 /* 4221 */ MCD_OPC_Decode, 178, 22, 169, 2, // Opcode: t2LDRSBpci /* 4226 */ MCD_OPC_FilterValue, 2, 207, 2, 0, // Skip to: 4950 /* 4231 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 4234 */ MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 4654 /* 4239 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 4242 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 4324 /* 4247 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 4250 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4272 /* 4255 */ MCD_OPC_CheckPredicate, 38, 83, 15, 0, // Skip to: 8183 /* 4260 */ MCD_OPC_CheckField, 12, 4, 15, 76, 15, 0, // Skip to: 8183 /* 4267 */ MCD_OPC_Decode, 195, 22, 239, 1, // Opcode: t2LSLrr /* 4272 */ MCD_OPC_FilterValue, 1, 66, 15, 0, // Skip to: 8183 /* 4277 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4280 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4302 /* 4285 */ MCD_OPC_CheckPredicate, 45, 53, 15, 0, // Skip to: 8183 /* 4290 */ MCD_OPC_CheckField, 12, 4, 15, 46, 15, 0, // Skip to: 8183 /* 4297 */ MCD_OPC_Decode, 141, 23, 170, 2, // Opcode: t2SADD8 /* 4302 */ MCD_OPC_FilterValue, 1, 36, 15, 0, // Skip to: 8183 /* 4307 */ MCD_OPC_CheckPredicate, 45, 31, 15, 0, // Skip to: 8183 /* 4312 */ MCD_OPC_CheckField, 12, 4, 15, 24, 15, 0, // Skip to: 8183 /* 4319 */ MCD_OPC_Decode, 140, 23, 170, 2, // Opcode: t2SADD16 /* 4324 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 4390 /* 4329 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4332 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4361 /* 4337 */ MCD_OPC_CheckPredicate, 45, 1, 15, 0, // Skip to: 8183 /* 4342 */ MCD_OPC_CheckField, 23, 1, 1, 250, 14, 0, // Skip to: 8183 /* 4349 */ MCD_OPC_CheckField, 12, 4, 15, 243, 14, 0, // Skip to: 8183 /* 4356 */ MCD_OPC_Decode, 246, 22, 170, 2, // Opcode: t2QADD8 /* 4361 */ MCD_OPC_FilterValue, 1, 233, 14, 0, // Skip to: 8183 /* 4366 */ MCD_OPC_CheckPredicate, 45, 228, 14, 0, // Skip to: 8183 /* 4371 */ MCD_OPC_CheckField, 23, 1, 1, 221, 14, 0, // Skip to: 8183 /* 4378 */ MCD_OPC_CheckField, 12, 4, 15, 214, 14, 0, // Skip to: 8183 /* 4385 */ MCD_OPC_Decode, 245, 22, 170, 2, // Opcode: t2QADD16 /* 4390 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 4456 /* 4395 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4398 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4427 /* 4403 */ MCD_OPC_CheckPredicate, 45, 191, 14, 0, // Skip to: 8183 /* 4408 */ MCD_OPC_CheckField, 23, 1, 1, 184, 14, 0, // Skip to: 8183 /* 4415 */ MCD_OPC_CheckField, 12, 4, 15, 177, 14, 0, // Skip to: 8183 /* 4422 */ MCD_OPC_Decode, 152, 23, 170, 2, // Opcode: t2SHADD8 /* 4427 */ MCD_OPC_FilterValue, 1, 167, 14, 0, // Skip to: 8183 /* 4432 */ MCD_OPC_CheckPredicate, 45, 162, 14, 0, // Skip to: 8183 /* 4437 */ MCD_OPC_CheckField, 23, 1, 1, 155, 14, 0, // Skip to: 8183 /* 4444 */ MCD_OPC_CheckField, 12, 4, 15, 148, 14, 0, // Skip to: 8183 /* 4451 */ MCD_OPC_Decode, 151, 23, 170, 2, // Opcode: t2SHADD16 /* 4456 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 4522 /* 4461 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4464 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4493 /* 4469 */ MCD_OPC_CheckPredicate, 45, 125, 14, 0, // Skip to: 8183 /* 4474 */ MCD_OPC_CheckField, 23, 1, 1, 118, 14, 0, // Skip to: 8183 /* 4481 */ MCD_OPC_CheckField, 12, 4, 15, 111, 14, 0, // Skip to: 8183 /* 4488 */ MCD_OPC_Decode, 152, 24, 170, 2, // Opcode: t2UADD8 /* 4493 */ MCD_OPC_FilterValue, 1, 101, 14, 0, // Skip to: 8183 /* 4498 */ MCD_OPC_CheckPredicate, 45, 96, 14, 0, // Skip to: 8183 /* 4503 */ MCD_OPC_CheckField, 23, 1, 1, 89, 14, 0, // Skip to: 8183 /* 4510 */ MCD_OPC_CheckField, 12, 4, 15, 82, 14, 0, // Skip to: 8183 /* 4517 */ MCD_OPC_Decode, 151, 24, 170, 2, // Opcode: t2UADD16 /* 4522 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 4588 /* 4527 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4530 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4559 /* 4535 */ MCD_OPC_CheckPredicate, 45, 59, 14, 0, // Skip to: 8183 /* 4540 */ MCD_OPC_CheckField, 23, 1, 1, 52, 14, 0, // Skip to: 8183 /* 4547 */ MCD_OPC_CheckField, 12, 4, 15, 45, 14, 0, // Skip to: 8183 /* 4554 */ MCD_OPC_Decode, 167, 24, 170, 2, // Opcode: t2UQADD8 /* 4559 */ MCD_OPC_FilterValue, 1, 35, 14, 0, // Skip to: 8183 /* 4564 */ MCD_OPC_CheckPredicate, 45, 30, 14, 0, // Skip to: 8183 /* 4569 */ MCD_OPC_CheckField, 23, 1, 1, 23, 14, 0, // Skip to: 8183 /* 4576 */ MCD_OPC_CheckField, 12, 4, 15, 16, 14, 0, // Skip to: 8183 /* 4583 */ MCD_OPC_Decode, 166, 24, 170, 2, // Opcode: t2UQADD16 /* 4588 */ MCD_OPC_FilterValue, 6, 6, 14, 0, // Skip to: 8183 /* 4593 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4596 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4625 /* 4601 */ MCD_OPC_CheckPredicate, 45, 249, 13, 0, // Skip to: 8183 /* 4606 */ MCD_OPC_CheckField, 23, 1, 1, 242, 13, 0, // Skip to: 8183 /* 4613 */ MCD_OPC_CheckField, 12, 4, 15, 235, 13, 0, // Skip to: 8183 /* 4620 */ MCD_OPC_Decode, 158, 24, 170, 2, // Opcode: t2UHADD8 /* 4625 */ MCD_OPC_FilterValue, 1, 225, 13, 0, // Skip to: 8183 /* 4630 */ MCD_OPC_CheckPredicate, 45, 220, 13, 0, // Skip to: 8183 /* 4635 */ MCD_OPC_CheckField, 23, 1, 1, 213, 13, 0, // Skip to: 8183 /* 4642 */ MCD_OPC_CheckField, 12, 4, 15, 206, 13, 0, // Skip to: 8183 /* 4649 */ MCD_OPC_Decode, 157, 24, 170, 2, // Opcode: t2UHADD16 /* 4654 */ MCD_OPC_FilterValue, 1, 196, 13, 0, // Skip to: 8183 /* 4659 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4662 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 4806 /* 4667 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 4670 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4710 /* 4675 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4678 */ MCD_OPC_FilterValue, 15, 172, 13, 0, // Skip to: 8183 /* 4683 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4700 /* 4688 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4700 /* 4695 */ MCD_OPC_Decode, 137, 24, 171, 2, // Opcode: t2SXTH /* 4700 */ MCD_OPC_CheckPredicate, 43, 150, 13, 0, // Skip to: 8183 /* 4705 */ MCD_OPC_Decode, 134, 24, 172, 2, // Opcode: t2SXTAH /* 4710 */ MCD_OPC_FilterValue, 1, 140, 13, 0, // Skip to: 8183 /* 4715 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 4718 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4740 /* 4723 */ MCD_OPC_CheckPredicate, 45, 127, 13, 0, // Skip to: 8183 /* 4728 */ MCD_OPC_CheckField, 12, 4, 15, 120, 13, 0, // Skip to: 8183 /* 4735 */ MCD_OPC_Decode, 244, 22, 173, 2, // Opcode: t2QADD /* 4740 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4762 /* 4745 */ MCD_OPC_CheckPredicate, 45, 105, 13, 0, // Skip to: 8183 /* 4750 */ MCD_OPC_CheckField, 12, 4, 15, 98, 13, 0, // Skip to: 8183 /* 4757 */ MCD_OPC_Decode, 248, 22, 173, 2, // Opcode: t2QDADD /* 4762 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4784 /* 4767 */ MCD_OPC_CheckPredicate, 45, 83, 13, 0, // Skip to: 8183 /* 4772 */ MCD_OPC_CheckField, 12, 4, 15, 76, 13, 0, // Skip to: 8183 /* 4779 */ MCD_OPC_Decode, 251, 22, 173, 2, // Opcode: t2QSUB /* 4784 */ MCD_OPC_FilterValue, 3, 66, 13, 0, // Skip to: 8183 /* 4789 */ MCD_OPC_CheckPredicate, 45, 61, 13, 0, // Skip to: 8183 /* 4794 */ MCD_OPC_CheckField, 12, 4, 15, 54, 13, 0, // Skip to: 8183 /* 4801 */ MCD_OPC_Decode, 249, 22, 173, 2, // Opcode: t2QDSUB /* 4806 */ MCD_OPC_FilterValue, 1, 44, 13, 0, // Skip to: 8183 /* 4811 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 4814 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4854 /* 4819 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4822 */ MCD_OPC_FilterValue, 15, 28, 13, 0, // Skip to: 8183 /* 4827 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4844 /* 4832 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4844 /* 4839 */ MCD_OPC_Decode, 184, 24, 171, 2, // Opcode: t2UXTH /* 4844 */ MCD_OPC_CheckPredicate, 43, 6, 13, 0, // Skip to: 8183 /* 4849 */ MCD_OPC_Decode, 181, 24, 172, 2, // Opcode: t2UXTAH /* 4854 */ MCD_OPC_FilterValue, 1, 252, 12, 0, // Skip to: 8183 /* 4859 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 4862 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4884 /* 4867 */ MCD_OPC_CheckPredicate, 38, 239, 12, 0, // Skip to: 8183 /* 4872 */ MCD_OPC_CheckField, 12, 4, 15, 232, 12, 0, // Skip to: 8183 /* 4879 */ MCD_OPC_Decode, 255, 22, 174, 2, // Opcode: t2REV /* 4884 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4906 /* 4889 */ MCD_OPC_CheckPredicate, 38, 217, 12, 0, // Skip to: 8183 /* 4894 */ MCD_OPC_CheckField, 12, 4, 15, 210, 12, 0, // Skip to: 8183 /* 4901 */ MCD_OPC_Decode, 128, 23, 174, 2, // Opcode: t2REV16 /* 4906 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4928 /* 4911 */ MCD_OPC_CheckPredicate, 38, 195, 12, 0, // Skip to: 8183 /* 4916 */ MCD_OPC_CheckField, 12, 4, 15, 188, 12, 0, // Skip to: 8183 /* 4923 */ MCD_OPC_Decode, 254, 22, 174, 2, // Opcode: t2RBIT /* 4928 */ MCD_OPC_FilterValue, 3, 178, 12, 0, // Skip to: 8183 /* 4933 */ MCD_OPC_CheckPredicate, 38, 173, 12, 0, // Skip to: 8183 /* 4938 */ MCD_OPC_CheckField, 12, 4, 15, 166, 12, 0, // Skip to: 8183 /* 4945 */ MCD_OPC_Decode, 129, 23, 174, 2, // Opcode: t2REVSH /* 4950 */ MCD_OPC_FilterValue, 3, 156, 12, 0, // Skip to: 8183 /* 4955 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 4958 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 5061 /* 4963 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4966 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5021 /* 4971 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 4974 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5006 /* 4979 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4996 /* 4984 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4996 /* 4991 */ MCD_OPC_Decode, 221, 22, 170, 2, // Opcode: t2MUL /* 4996 */ MCD_OPC_CheckPredicate, 38, 110, 12, 0, // Skip to: 8183 /* 5001 */ MCD_OPC_Decode, 202, 22, 175, 2, // Opcode: t2MLA /* 5006 */ MCD_OPC_FilterValue, 1, 100, 12, 0, // Skip to: 8183 /* 5011 */ MCD_OPC_CheckPredicate, 38, 95, 12, 0, // Skip to: 8183 /* 5016 */ MCD_OPC_Decode, 187, 23, 176, 2, // Opcode: t2SMULL /* 5021 */ MCD_OPC_FilterValue, 1, 85, 12, 0, // Skip to: 8183 /* 5026 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5029 */ MCD_OPC_FilterValue, 0, 77, 12, 0, // Skip to: 8183 /* 5034 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5051 /* 5039 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5051 /* 5046 */ MCD_OPC_Decode, 185, 23, 170, 2, // Opcode: t2SMULBB /* 5051 */ MCD_OPC_CheckPredicate, 45, 55, 12, 0, // Skip to: 8183 /* 5056 */ MCD_OPC_Decode, 158, 23, 175, 2, // Opcode: t2SMLABB /* 5061 */ MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 5131 /* 5066 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5069 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5091 /* 5074 */ MCD_OPC_CheckPredicate, 38, 32, 12, 0, // Skip to: 8183 /* 5079 */ MCD_OPC_CheckField, 23, 1, 0, 25, 12, 0, // Skip to: 8183 /* 5086 */ MCD_OPC_Decode, 203, 22, 175, 2, // Opcode: t2MLS /* 5091 */ MCD_OPC_FilterValue, 1, 15, 12, 0, // Skip to: 8183 /* 5096 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5099 */ MCD_OPC_FilterValue, 0, 7, 12, 0, // Skip to: 8183 /* 5104 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5121 /* 5109 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5121 /* 5116 */ MCD_OPC_Decode, 186, 23, 170, 2, // Opcode: t2SMULBT /* 5121 */ MCD_OPC_CheckPredicate, 45, 241, 11, 0, // Skip to: 8183 /* 5126 */ MCD_OPC_Decode, 159, 23, 175, 2, // Opcode: t2SMLABT /* 5131 */ MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 5179 /* 5136 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5139 */ MCD_OPC_FilterValue, 1, 223, 11, 0, // Skip to: 8183 /* 5144 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5147 */ MCD_OPC_FilterValue, 0, 215, 11, 0, // Skip to: 8183 /* 5152 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5169 /* 5157 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5169 /* 5164 */ MCD_OPC_Decode, 188, 23, 170, 2, // Opcode: t2SMULTB /* 5169 */ MCD_OPC_CheckPredicate, 45, 193, 11, 0, // Skip to: 8183 /* 5174 */ MCD_OPC_Decode, 169, 23, 175, 2, // Opcode: t2SMLATB /* 5179 */ MCD_OPC_FilterValue, 3, 43, 0, 0, // Skip to: 5227 /* 5184 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5187 */ MCD_OPC_FilterValue, 1, 175, 11, 0, // Skip to: 8183 /* 5192 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5195 */ MCD_OPC_FilterValue, 0, 167, 11, 0, // Skip to: 8183 /* 5200 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5217 /* 5205 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5217 /* 5212 */ MCD_OPC_Decode, 189, 23, 170, 2, // Opcode: t2SMULTT /* 5217 */ MCD_OPC_CheckPredicate, 45, 145, 11, 0, // Skip to: 8183 /* 5222 */ MCD_OPC_Decode, 170, 23, 175, 2, // Opcode: t2SMLATT /* 5227 */ MCD_OPC_FilterValue, 15, 135, 11, 0, // Skip to: 8183 /* 5232 */ MCD_OPC_CheckPredicate, 55, 130, 11, 0, // Skip to: 8183 /* 5237 */ MCD_OPC_CheckField, 23, 1, 1, 123, 11, 0, // Skip to: 8183 /* 5244 */ MCD_OPC_CheckField, 20, 1, 1, 116, 11, 0, // Skip to: 8183 /* 5251 */ MCD_OPC_CheckField, 12, 4, 15, 109, 11, 0, // Skip to: 8183 /* 5258 */ MCD_OPC_Decode, 147, 23, 170, 2, // Opcode: t2SDIV /* 5263 */ MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 6421 /* 5268 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... /* 5271 */ MCD_OPC_FilterValue, 0, 82, 1, 0, // Skip to: 5614 /* 5276 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5279 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 5409 /* 5284 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5287 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5394 /* 5292 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 5295 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5317 /* 5300 */ MCD_OPC_CheckPredicate, 38, 62, 11, 0, // Skip to: 8183 /* 5305 */ MCD_OPC_CheckField, 6, 4, 0, 55, 11, 0, // Skip to: 8183 /* 5312 */ MCD_OPC_Decode, 248, 23, 160, 2, // Opcode: t2STRHs /* 5317 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5339 /* 5322 */ MCD_OPC_CheckPredicate, 38, 40, 11, 0, // Skip to: 8183 /* 5327 */ MCD_OPC_CheckField, 8, 1, 1, 33, 11, 0, // Skip to: 8183 /* 5334 */ MCD_OPC_Decode, 244, 23, 161, 2, // Opcode: t2STRH_POST /* 5339 */ MCD_OPC_FilterValue, 3, 23, 11, 0, // Skip to: 8183 /* 5344 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5347 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5379 /* 5352 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5369 /* 5357 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5369 /* 5364 */ MCD_OPC_Decode, 243, 23, 162, 2, // Opcode: t2STRHT /* 5369 */ MCD_OPC_CheckPredicate, 38, 249, 10, 0, // Skip to: 8183 /* 5374 */ MCD_OPC_Decode, 247, 23, 163, 2, // Opcode: t2STRHi8 /* 5379 */ MCD_OPC_FilterValue, 1, 239, 10, 0, // Skip to: 8183 /* 5384 */ MCD_OPC_CheckPredicate, 38, 234, 10, 0, // Skip to: 8183 /* 5389 */ MCD_OPC_Decode, 245, 23, 161, 2, // Opcode: t2STRH_PRE /* 5394 */ MCD_OPC_FilterValue, 1, 224, 10, 0, // Skip to: 8183 /* 5399 */ MCD_OPC_CheckPredicate, 38, 219, 10, 0, // Skip to: 8183 /* 5404 */ MCD_OPC_Decode, 246, 23, 164, 2, // Opcode: t2STRHi12 /* 5409 */ MCD_OPC_FilterValue, 1, 209, 10, 0, // Skip to: 8183 /* 5414 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5417 */ MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 5565 /* 5422 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 5425 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5465 /* 5430 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 5433 */ MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 5597 /* 5438 */ MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5455 /* 5443 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5455 /* 5450 */ MCD_OPC_Decode, 235, 22, 165, 2, // Opcode: t2PLDWs /* 5455 */ MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 5597 /* 5460 */ MCD_OPC_Decode, 172, 22, 165, 2, // Opcode: t2LDRHs /* 5465 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5487 /* 5470 */ MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 5597 /* 5475 */ MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 5597 /* 5482 */ MCD_OPC_Decode, 167, 22, 161, 2, // Opcode: t2LDRH_POST /* 5487 */ MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 5597 /* 5492 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5495 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5550 /* 5500 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... /* 5503 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5525 /* 5508 */ MCD_OPC_CheckPredicate, 56, 27, 0, 0, // Skip to: 5540 /* 5513 */ MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 5540 /* 5520 */ MCD_OPC_Decode, 234, 22, 166, 2, // Opcode: t2PLDWi8 /* 5525 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5540 /* 5530 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5540 /* 5535 */ MCD_OPC_Decode, 166, 22, 167, 2, // Opcode: t2LDRHT /* 5540 */ MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 5597 /* 5545 */ MCD_OPC_Decode, 170, 22, 166, 2, // Opcode: t2LDRHi8 /* 5550 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 5597 /* 5555 */ MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 5597 /* 5560 */ MCD_OPC_Decode, 168, 22, 161, 2, // Opcode: t2LDRH_PRE /* 5565 */ MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5597 /* 5570 */ MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5587 /* 5575 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5587 /* 5582 */ MCD_OPC_Decode, 233, 22, 168, 2, // Opcode: t2PLDWi12 /* 5587 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5597 /* 5592 */ MCD_OPC_Decode, 169, 22, 168, 2, // Opcode: t2LDRHi12 /* 5597 */ MCD_OPC_CheckPredicate, 38, 21, 10, 0, // Skip to: 8183 /* 5602 */ MCD_OPC_CheckField, 16, 4, 15, 14, 10, 0, // Skip to: 8183 /* 5609 */ MCD_OPC_Decode, 171, 22, 169, 2, // Opcode: t2LDRHpci /* 5614 */ MCD_OPC_FilterValue, 1, 150, 0, 0, // Skip to: 5769 /* 5619 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5622 */ MCD_OPC_FilterValue, 1, 252, 9, 0, // Skip to: 8183 /* 5627 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5630 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5737 /* 5635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 5638 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5660 /* 5643 */ MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 5752 /* 5648 */ MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 5752 /* 5655 */ MCD_OPC_Decode, 186, 22, 165, 2, // Opcode: t2LDRSHs /* 5660 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5682 /* 5665 */ MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 5752 /* 5670 */ MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 5752 /* 5677 */ MCD_OPC_Decode, 181, 22, 161, 2, // Opcode: t2LDRSH_POST /* 5682 */ MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 5752 /* 5687 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5690 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5722 /* 5695 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5712 /* 5700 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5712 /* 5707 */ MCD_OPC_Decode, 180, 22, 167, 2, // Opcode: t2LDRSHT /* 5712 */ MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 5752 /* 5717 */ MCD_OPC_Decode, 184, 22, 166, 2, // Opcode: t2LDRSHi8 /* 5722 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 5752 /* 5727 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 5752 /* 5732 */ MCD_OPC_Decode, 182, 22, 161, 2, // Opcode: t2LDRSH_PRE /* 5737 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5752 /* 5742 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5752 /* 5747 */ MCD_OPC_Decode, 183, 22, 168, 2, // Opcode: t2LDRSHi12 /* 5752 */ MCD_OPC_CheckPredicate, 38, 122, 9, 0, // Skip to: 8183 /* 5757 */ MCD_OPC_CheckField, 16, 4, 15, 115, 9, 0, // Skip to: 8183 /* 5764 */ MCD_OPC_Decode, 185, 22, 169, 2, // Opcode: t2LDRSHpci /* 5769 */ MCD_OPC_FilterValue, 2, 156, 1, 0, // Skip to: 6186 /* 5774 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 5777 */ MCD_OPC_FilterValue, 0, 242, 0, 0, // Skip to: 6024 /* 5782 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 5785 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 5844 /* 5790 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 5793 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5815 /* 5798 */ MCD_OPC_CheckPredicate, 38, 76, 9, 0, // Skip to: 8183 /* 5803 */ MCD_OPC_CheckField, 12, 4, 15, 69, 9, 0, // Skip to: 8183 /* 5810 */ MCD_OPC_Decode, 197, 22, 239, 1, // Opcode: t2LSRrr /* 5815 */ MCD_OPC_FilterValue, 1, 59, 9, 0, // Skip to: 8183 /* 5820 */ MCD_OPC_CheckPredicate, 45, 54, 9, 0, // Skip to: 8183 /* 5825 */ MCD_OPC_CheckField, 20, 1, 0, 47, 9, 0, // Skip to: 8183 /* 5832 */ MCD_OPC_CheckField, 12, 4, 15, 40, 9, 0, // Skip to: 8183 /* 5839 */ MCD_OPC_Decode, 142, 23, 170, 2, // Opcode: t2SASX /* 5844 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5880 /* 5849 */ MCD_OPC_CheckPredicate, 45, 25, 9, 0, // Skip to: 8183 /* 5854 */ MCD_OPC_CheckField, 23, 1, 1, 18, 9, 0, // Skip to: 8183 /* 5861 */ MCD_OPC_CheckField, 20, 1, 0, 11, 9, 0, // Skip to: 8183 /* 5868 */ MCD_OPC_CheckField, 12, 4, 15, 4, 9, 0, // Skip to: 8183 /* 5875 */ MCD_OPC_Decode, 247, 22, 170, 2, // Opcode: t2QASX /* 5880 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 5916 /* 5885 */ MCD_OPC_CheckPredicate, 45, 245, 8, 0, // Skip to: 8183 /* 5890 */ MCD_OPC_CheckField, 23, 1, 1, 238, 8, 0, // Skip to: 8183 /* 5897 */ MCD_OPC_CheckField, 20, 1, 0, 231, 8, 0, // Skip to: 8183 /* 5904 */ MCD_OPC_CheckField, 12, 4, 15, 224, 8, 0, // Skip to: 8183 /* 5911 */ MCD_OPC_Decode, 153, 23, 170, 2, // Opcode: t2SHASX /* 5916 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 5952 /* 5921 */ MCD_OPC_CheckPredicate, 45, 209, 8, 0, // Skip to: 8183 /* 5926 */ MCD_OPC_CheckField, 23, 1, 1, 202, 8, 0, // Skip to: 8183 /* 5933 */ MCD_OPC_CheckField, 20, 1, 0, 195, 8, 0, // Skip to: 8183 /* 5940 */ MCD_OPC_CheckField, 12, 4, 15, 188, 8, 0, // Skip to: 8183 /* 5947 */ MCD_OPC_Decode, 153, 24, 170, 2, // Opcode: t2UASX /* 5952 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 5988 /* 5957 */ MCD_OPC_CheckPredicate, 45, 173, 8, 0, // Skip to: 8183 /* 5962 */ MCD_OPC_CheckField, 23, 1, 1, 166, 8, 0, // Skip to: 8183 /* 5969 */ MCD_OPC_CheckField, 20, 1, 0, 159, 8, 0, // Skip to: 8183 /* 5976 */ MCD_OPC_CheckField, 12, 4, 15, 152, 8, 0, // Skip to: 8183 /* 5983 */ MCD_OPC_Decode, 168, 24, 170, 2, // Opcode: t2UQASX /* 5988 */ MCD_OPC_FilterValue, 6, 142, 8, 0, // Skip to: 8183 /* 5993 */ MCD_OPC_CheckPredicate, 45, 137, 8, 0, // Skip to: 8183 /* 5998 */ MCD_OPC_CheckField, 23, 1, 1, 130, 8, 0, // Skip to: 8183 /* 6005 */ MCD_OPC_CheckField, 20, 1, 0, 123, 8, 0, // Skip to: 8183 /* 6012 */ MCD_OPC_CheckField, 12, 4, 15, 116, 8, 0, // Skip to: 8183 /* 6019 */ MCD_OPC_Decode, 159, 24, 170, 2, // Opcode: t2UHASX /* 6024 */ MCD_OPC_FilterValue, 1, 106, 8, 0, // Skip to: 8183 /* 6029 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6032 */ MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 6109 /* 6037 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6040 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6080 /* 6045 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6048 */ MCD_OPC_FilterValue, 15, 82, 8, 0, // Skip to: 8183 /* 6053 */ MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6070 /* 6058 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6070 /* 6065 */ MCD_OPC_Decode, 136, 24, 171, 2, // Opcode: t2SXTB16 /* 6070 */ MCD_OPC_CheckPredicate, 43, 60, 8, 0, // Skip to: 8183 /* 6075 */ MCD_OPC_Decode, 133, 24, 172, 2, // Opcode: t2SXTAB16 /* 6080 */ MCD_OPC_FilterValue, 1, 50, 8, 0, // Skip to: 8183 /* 6085 */ MCD_OPC_CheckPredicate, 45, 45, 8, 0, // Skip to: 8183 /* 6090 */ MCD_OPC_CheckField, 12, 4, 15, 38, 8, 0, // Skip to: 8183 /* 6097 */ MCD_OPC_CheckField, 4, 3, 0, 31, 8, 0, // Skip to: 8183 /* 6104 */ MCD_OPC_Decode, 148, 23, 177, 2, // Opcode: t2SEL /* 6109 */ MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 8183 /* 6114 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6117 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6157 /* 6122 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6125 */ MCD_OPC_FilterValue, 15, 5, 8, 0, // Skip to: 8183 /* 6130 */ MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6147 /* 6135 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6147 /* 6142 */ MCD_OPC_Decode, 183, 24, 171, 2, // Opcode: t2UXTB16 /* 6147 */ MCD_OPC_CheckPredicate, 43, 239, 7, 0, // Skip to: 8183 /* 6152 */ MCD_OPC_Decode, 180, 24, 172, 2, // Opcode: t2UXTAB16 /* 6157 */ MCD_OPC_FilterValue, 1, 229, 7, 0, // Skip to: 8183 /* 6162 */ MCD_OPC_CheckPredicate, 38, 224, 7, 0, // Skip to: 8183 /* 6167 */ MCD_OPC_CheckField, 12, 4, 15, 217, 7, 0, // Skip to: 8183 /* 6174 */ MCD_OPC_CheckField, 4, 3, 0, 210, 7, 0, // Skip to: 8183 /* 6181 */ MCD_OPC_Decode, 222, 21, 174, 2, // Opcode: t2CLZ /* 6186 */ MCD_OPC_FilterValue, 3, 200, 7, 0, // Skip to: 8183 /* 6191 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 6194 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 6297 /* 6199 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6202 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 6257 /* 6207 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6210 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6242 /* 6215 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6232 /* 6220 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6232 /* 6227 */ MCD_OPC_Decode, 183, 23, 170, 2, // Opcode: t2SMUAD /* 6232 */ MCD_OPC_CheckPredicate, 45, 154, 7, 0, // Skip to: 8183 /* 6237 */ MCD_OPC_Decode, 160, 23, 175, 2, // Opcode: t2SMLAD /* 6242 */ MCD_OPC_FilterValue, 1, 144, 7, 0, // Skip to: 8183 /* 6247 */ MCD_OPC_CheckPredicate, 38, 139, 7, 0, // Skip to: 8183 /* 6252 */ MCD_OPC_Decode, 165, 24, 176, 2, // Opcode: t2UMULL /* 6257 */ MCD_OPC_FilterValue, 1, 129, 7, 0, // Skip to: 8183 /* 6262 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6265 */ MCD_OPC_FilterValue, 0, 121, 7, 0, // Skip to: 8183 /* 6270 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6287 /* 6275 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6287 /* 6282 */ MCD_OPC_Decode, 190, 23, 170, 2, // Opcode: t2SMULWB /* 6287 */ MCD_OPC_CheckPredicate, 45, 99, 7, 0, // Skip to: 8183 /* 6292 */ MCD_OPC_Decode, 171, 23, 175, 2, // Opcode: t2SMLAWB /* 6297 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 6385 /* 6302 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6305 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6345 /* 6310 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6313 */ MCD_OPC_FilterValue, 0, 73, 7, 0, // Skip to: 8183 /* 6318 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6335 /* 6323 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6335 /* 6330 */ MCD_OPC_Decode, 184, 23, 170, 2, // Opcode: t2SMUADX /* 6335 */ MCD_OPC_CheckPredicate, 45, 51, 7, 0, // Skip to: 8183 /* 6340 */ MCD_OPC_Decode, 161, 23, 175, 2, // Opcode: t2SMLADX /* 6345 */ MCD_OPC_FilterValue, 1, 41, 7, 0, // Skip to: 8183 /* 6350 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6353 */ MCD_OPC_FilterValue, 0, 33, 7, 0, // Skip to: 8183 /* 6358 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6375 /* 6363 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6375 /* 6370 */ MCD_OPC_Decode, 191, 23, 170, 2, // Opcode: t2SMULWT /* 6375 */ MCD_OPC_CheckPredicate, 45, 11, 7, 0, // Skip to: 8183 /* 6380 */ MCD_OPC_Decode, 172, 23, 175, 2, // Opcode: t2SMLAWT /* 6385 */ MCD_OPC_FilterValue, 15, 1, 7, 0, // Skip to: 8183 /* 6390 */ MCD_OPC_CheckPredicate, 55, 252, 6, 0, // Skip to: 8183 /* 6395 */ MCD_OPC_CheckField, 23, 1, 1, 245, 6, 0, // Skip to: 8183 /* 6402 */ MCD_OPC_CheckField, 20, 1, 1, 238, 6, 0, // Skip to: 8183 /* 6409 */ MCD_OPC_CheckField, 12, 4, 15, 231, 6, 0, // Skip to: 8183 /* 6416 */ MCD_OPC_Decode, 156, 24, 170, 2, // Opcode: t2UDIV /* 6421 */ MCD_OPC_FilterValue, 2, 107, 5, 0, // Skip to: 7813 /* 6426 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... /* 6429 */ MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 6714 /* 6434 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6437 */ MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 6567 /* 6442 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6445 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6552 /* 6450 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 6453 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6475 /* 6458 */ MCD_OPC_CheckPredicate, 38, 184, 6, 0, // Skip to: 8183 /* 6463 */ MCD_OPC_CheckField, 6, 4, 0, 177, 6, 0, // Skip to: 8183 /* 6470 */ MCD_OPC_Decode, 254, 23, 178, 2, // Opcode: t2STRs /* 6475 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6497 /* 6480 */ MCD_OPC_CheckPredicate, 38, 162, 6, 0, // Skip to: 8183 /* 6485 */ MCD_OPC_CheckField, 8, 1, 1, 155, 6, 0, // Skip to: 8183 /* 6492 */ MCD_OPC_Decode, 250, 23, 161, 2, // Opcode: t2STR_POST /* 6497 */ MCD_OPC_FilterValue, 3, 145, 6, 0, // Skip to: 8183 /* 6502 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 6505 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6537 /* 6510 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6527 /* 6515 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6527 /* 6522 */ MCD_OPC_Decode, 249, 23, 162, 2, // Opcode: t2STRT /* 6527 */ MCD_OPC_CheckPredicate, 38, 115, 6, 0, // Skip to: 8183 /* 6532 */ MCD_OPC_Decode, 253, 23, 179, 2, // Opcode: t2STRi8 /* 6537 */ MCD_OPC_FilterValue, 1, 105, 6, 0, // Skip to: 8183 /* 6542 */ MCD_OPC_CheckPredicate, 38, 100, 6, 0, // Skip to: 8183 /* 6547 */ MCD_OPC_Decode, 251, 23, 161, 2, // Opcode: t2STR_PRE /* 6552 */ MCD_OPC_FilterValue, 1, 90, 6, 0, // Skip to: 8183 /* 6557 */ MCD_OPC_CheckPredicate, 38, 85, 6, 0, // Skip to: 8183 /* 6562 */ MCD_OPC_Decode, 252, 23, 180, 2, // Opcode: t2STRi12 /* 6567 */ MCD_OPC_FilterValue, 1, 75, 6, 0, // Skip to: 8183 /* 6572 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6575 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6682 /* 6580 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 6583 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6605 /* 6588 */ MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 6697 /* 6593 */ MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 6697 /* 6600 */ MCD_OPC_Decode, 193, 22, 165, 2, // Opcode: t2LDRs /* 6605 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6627 /* 6610 */ MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 6697 /* 6615 */ MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 6697 /* 6622 */ MCD_OPC_Decode, 188, 22, 161, 2, // Opcode: t2LDR_POST /* 6627 */ MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 6697 /* 6632 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 6635 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6667 /* 6640 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6657 /* 6645 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6657 /* 6652 */ MCD_OPC_Decode, 187, 22, 167, 2, // Opcode: t2LDRT /* 6657 */ MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 6697 /* 6662 */ MCD_OPC_Decode, 191, 22, 166, 2, // Opcode: t2LDRi8 /* 6667 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 6697 /* 6672 */ MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 6697 /* 6677 */ MCD_OPC_Decode, 189, 22, 161, 2, // Opcode: t2LDR_PRE /* 6682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6697 /* 6687 */ MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 6697 /* 6692 */ MCD_OPC_Decode, 190, 22, 168, 2, // Opcode: t2LDRi12 /* 6697 */ MCD_OPC_CheckPredicate, 38, 201, 5, 0, // Skip to: 8183 /* 6702 */ MCD_OPC_CheckField, 16, 4, 15, 194, 5, 0, // Skip to: 8183 /* 6709 */ MCD_OPC_Decode, 192, 22, 169, 2, // Opcode: t2LDRpci /* 6714 */ MCD_OPC_FilterValue, 2, 163, 2, 0, // Skip to: 7394 /* 6719 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 6722 */ MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 7142 /* 6727 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 6730 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 6812 /* 6735 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 6738 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6760 /* 6743 */ MCD_OPC_CheckPredicate, 38, 155, 5, 0, // Skip to: 8183 /* 6748 */ MCD_OPC_CheckField, 12, 4, 15, 148, 5, 0, // Skip to: 8183 /* 6755 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: t2ASRrr /* 6760 */ MCD_OPC_FilterValue, 1, 138, 5, 0, // Skip to: 8183 /* 6765 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6768 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6790 /* 6773 */ MCD_OPC_CheckPredicate, 45, 125, 5, 0, // Skip to: 8183 /* 6778 */ MCD_OPC_CheckField, 12, 4, 15, 118, 5, 0, // Skip to: 8183 /* 6785 */ MCD_OPC_Decode, 202, 23, 170, 2, // Opcode: t2SSUB8 /* 6790 */ MCD_OPC_FilterValue, 1, 108, 5, 0, // Skip to: 8183 /* 6795 */ MCD_OPC_CheckPredicate, 45, 103, 5, 0, // Skip to: 8183 /* 6800 */ MCD_OPC_CheckField, 12, 4, 15, 96, 5, 0, // Skip to: 8183 /* 6807 */ MCD_OPC_Decode, 201, 23, 170, 2, // Opcode: t2SSUB16 /* 6812 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 6878 /* 6817 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6820 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6849 /* 6825 */ MCD_OPC_CheckPredicate, 45, 73, 5, 0, // Skip to: 8183 /* 6830 */ MCD_OPC_CheckField, 23, 1, 1, 66, 5, 0, // Skip to: 8183 /* 6837 */ MCD_OPC_CheckField, 12, 4, 15, 59, 5, 0, // Skip to: 8183 /* 6844 */ MCD_OPC_Decode, 253, 22, 170, 2, // Opcode: t2QSUB8 /* 6849 */ MCD_OPC_FilterValue, 1, 49, 5, 0, // Skip to: 8183 /* 6854 */ MCD_OPC_CheckPredicate, 45, 44, 5, 0, // Skip to: 8183 /* 6859 */ MCD_OPC_CheckField, 23, 1, 1, 37, 5, 0, // Skip to: 8183 /* 6866 */ MCD_OPC_CheckField, 12, 4, 15, 30, 5, 0, // Skip to: 8183 /* 6873 */ MCD_OPC_Decode, 252, 22, 170, 2, // Opcode: t2QSUB16 /* 6878 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 6944 /* 6883 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6886 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6915 /* 6891 */ MCD_OPC_CheckPredicate, 45, 7, 5, 0, // Skip to: 8183 /* 6896 */ MCD_OPC_CheckField, 23, 1, 1, 0, 5, 0, // Skip to: 8183 /* 6903 */ MCD_OPC_CheckField, 12, 4, 15, 249, 4, 0, // Skip to: 8183 /* 6910 */ MCD_OPC_Decode, 156, 23, 170, 2, // Opcode: t2SHSUB8 /* 6915 */ MCD_OPC_FilterValue, 1, 239, 4, 0, // Skip to: 8183 /* 6920 */ MCD_OPC_CheckPredicate, 45, 234, 4, 0, // Skip to: 8183 /* 6925 */ MCD_OPC_CheckField, 23, 1, 1, 227, 4, 0, // Skip to: 8183 /* 6932 */ MCD_OPC_CheckField, 12, 4, 15, 220, 4, 0, // Skip to: 8183 /* 6939 */ MCD_OPC_Decode, 155, 23, 170, 2, // Opcode: t2SHSUB16 /* 6944 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 7010 /* 6949 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6952 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6981 /* 6957 */ MCD_OPC_CheckPredicate, 45, 197, 4, 0, // Skip to: 8183 /* 6962 */ MCD_OPC_CheckField, 23, 1, 1, 190, 4, 0, // Skip to: 8183 /* 6969 */ MCD_OPC_CheckField, 12, 4, 15, 183, 4, 0, // Skip to: 8183 /* 6976 */ MCD_OPC_Decode, 178, 24, 170, 2, // Opcode: t2USUB8 /* 6981 */ MCD_OPC_FilterValue, 1, 173, 4, 0, // Skip to: 8183 /* 6986 */ MCD_OPC_CheckPredicate, 45, 168, 4, 0, // Skip to: 8183 /* 6991 */ MCD_OPC_CheckField, 23, 1, 1, 161, 4, 0, // Skip to: 8183 /* 6998 */ MCD_OPC_CheckField, 12, 4, 15, 154, 4, 0, // Skip to: 8183 /* 7005 */ MCD_OPC_Decode, 177, 24, 170, 2, // Opcode: t2USUB16 /* 7010 */ MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 7076 /* 7015 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7018 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7047 /* 7023 */ MCD_OPC_CheckPredicate, 45, 131, 4, 0, // Skip to: 8183 /* 7028 */ MCD_OPC_CheckField, 23, 1, 1, 124, 4, 0, // Skip to: 8183 /* 7035 */ MCD_OPC_CheckField, 12, 4, 15, 117, 4, 0, // Skip to: 8183 /* 7042 */ MCD_OPC_Decode, 171, 24, 170, 2, // Opcode: t2UQSUB8 /* 7047 */ MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 8183 /* 7052 */ MCD_OPC_CheckPredicate, 45, 102, 4, 0, // Skip to: 8183 /* 7057 */ MCD_OPC_CheckField, 23, 1, 1, 95, 4, 0, // Skip to: 8183 /* 7064 */ MCD_OPC_CheckField, 12, 4, 15, 88, 4, 0, // Skip to: 8183 /* 7071 */ MCD_OPC_Decode, 170, 24, 170, 2, // Opcode: t2UQSUB16 /* 7076 */ MCD_OPC_FilterValue, 6, 78, 4, 0, // Skip to: 8183 /* 7081 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7084 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7113 /* 7089 */ MCD_OPC_CheckPredicate, 45, 65, 4, 0, // Skip to: 8183 /* 7094 */ MCD_OPC_CheckField, 23, 1, 1, 58, 4, 0, // Skip to: 8183 /* 7101 */ MCD_OPC_CheckField, 12, 4, 15, 51, 4, 0, // Skip to: 8183 /* 7108 */ MCD_OPC_Decode, 162, 24, 170, 2, // Opcode: t2UHSUB8 /* 7113 */ MCD_OPC_FilterValue, 1, 41, 4, 0, // Skip to: 8183 /* 7118 */ MCD_OPC_CheckPredicate, 45, 36, 4, 0, // Skip to: 8183 /* 7123 */ MCD_OPC_CheckField, 23, 1, 1, 29, 4, 0, // Skip to: 8183 /* 7130 */ MCD_OPC_CheckField, 12, 4, 15, 22, 4, 0, // Skip to: 8183 /* 7137 */ MCD_OPC_Decode, 161, 24, 170, 2, // Opcode: t2UHSUB16 /* 7142 */ MCD_OPC_FilterValue, 1, 12, 4, 0, // Skip to: 8183 /* 7147 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7150 */ MCD_OPC_FilterValue, 0, 117, 0, 0, // Skip to: 7272 /* 7155 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 7158 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7198 /* 7163 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7166 */ MCD_OPC_FilterValue, 15, 244, 3, 0, // Skip to: 8183 /* 7171 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7188 /* 7176 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7188 /* 7183 */ MCD_OPC_Decode, 135, 24, 171, 2, // Opcode: t2SXTB /* 7188 */ MCD_OPC_CheckPredicate, 43, 222, 3, 0, // Skip to: 8183 /* 7193 */ MCD_OPC_Decode, 132, 24, 172, 2, // Opcode: t2SXTAB /* 7198 */ MCD_OPC_FilterValue, 1, 212, 3, 0, // Skip to: 8183 /* 7203 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 7206 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7228 /* 7211 */ MCD_OPC_CheckPredicate, 57, 199, 3, 0, // Skip to: 8183 /* 7216 */ MCD_OPC_CheckField, 12, 4, 15, 192, 3, 0, // Skip to: 8183 /* 7223 */ MCD_OPC_Decode, 232, 21, 170, 2, // Opcode: t2CRC32B /* 7228 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7250 /* 7233 */ MCD_OPC_CheckPredicate, 57, 177, 3, 0, // Skip to: 8183 /* 7238 */ MCD_OPC_CheckField, 12, 4, 15, 170, 3, 0, // Skip to: 8183 /* 7245 */ MCD_OPC_Decode, 236, 21, 170, 2, // Opcode: t2CRC32H /* 7250 */ MCD_OPC_FilterValue, 2, 160, 3, 0, // Skip to: 8183 /* 7255 */ MCD_OPC_CheckPredicate, 57, 155, 3, 0, // Skip to: 8183 /* 7260 */ MCD_OPC_CheckField, 12, 4, 15, 148, 3, 0, // Skip to: 8183 /* 7267 */ MCD_OPC_Decode, 237, 21, 170, 2, // Opcode: t2CRC32W /* 7272 */ MCD_OPC_FilterValue, 1, 138, 3, 0, // Skip to: 8183 /* 7277 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 7280 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7320 /* 7285 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7288 */ MCD_OPC_FilterValue, 15, 122, 3, 0, // Skip to: 8183 /* 7293 */ MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7310 /* 7298 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7310 /* 7305 */ MCD_OPC_Decode, 182, 24, 171, 2, // Opcode: t2UXTB /* 7310 */ MCD_OPC_CheckPredicate, 43, 100, 3, 0, // Skip to: 8183 /* 7315 */ MCD_OPC_Decode, 179, 24, 172, 2, // Opcode: t2UXTAB /* 7320 */ MCD_OPC_FilterValue, 1, 90, 3, 0, // Skip to: 8183 /* 7325 */ MCD_OPC_ExtractField, 4, 3, // Inst{6-4} ... /* 7328 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7350 /* 7333 */ MCD_OPC_CheckPredicate, 57, 77, 3, 0, // Skip to: 8183 /* 7338 */ MCD_OPC_CheckField, 12, 4, 15, 70, 3, 0, // Skip to: 8183 /* 7345 */ MCD_OPC_Decode, 233, 21, 170, 2, // Opcode: t2CRC32CB /* 7350 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7372 /* 7355 */ MCD_OPC_CheckPredicate, 57, 55, 3, 0, // Skip to: 8183 /* 7360 */ MCD_OPC_CheckField, 12, 4, 15, 48, 3, 0, // Skip to: 8183 /* 7367 */ MCD_OPC_Decode, 234, 21, 170, 2, // Opcode: t2CRC32CH /* 7372 */ MCD_OPC_FilterValue, 2, 38, 3, 0, // Skip to: 8183 /* 7377 */ MCD_OPC_CheckPredicate, 57, 33, 3, 0, // Skip to: 8183 /* 7382 */ MCD_OPC_CheckField, 12, 4, 15, 26, 3, 0, // Skip to: 8183 /* 7389 */ MCD_OPC_Decode, 235, 21, 170, 2, // Opcode: t2CRC32CW /* 7394 */ MCD_OPC_FilterValue, 3, 16, 3, 0, // Skip to: 8183 /* 7399 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 7402 */ MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 7505 /* 7407 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7410 */ MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 7465 /* 7415 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 7418 */ MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7450 /* 7423 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7440 /* 7428 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7440 /* 7435 */ MCD_OPC_Decode, 192, 23, 170, 2, // Opcode: t2SMUSD /* 7440 */ MCD_OPC_CheckPredicate, 45, 226, 2, 0, // Skip to: 8183 /* 7445 */ MCD_OPC_Decode, 173, 23, 175, 2, // Opcode: t2SMLSD /* 7450 */ MCD_OPC_FilterValue, 1, 216, 2, 0, // Skip to: 8183 /* 7455 */ MCD_OPC_CheckPredicate, 38, 211, 2, 0, // Skip to: 8183 /* 7460 */ MCD_OPC_Decode, 162, 23, 181, 2, // Opcode: t2SMLAL /* 7465 */ MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 8183 /* 7470 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 7473 */ MCD_OPC_FilterValue, 0, 193, 2, 0, // Skip to: 8183 /* 7478 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7495 /* 7483 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7495 /* 7490 */ MCD_OPC_Decode, 181, 23, 170, 2, // Opcode: t2SMMUL /* 7495 */ MCD_OPC_CheckPredicate, 45, 171, 2, 0, // Skip to: 8183 /* 7500 */ MCD_OPC_Decode, 177, 23, 175, 2, // Opcode: t2SMMLA /* 7505 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 7593 /* 7510 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7513 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7553 /* 7518 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 7521 */ MCD_OPC_FilterValue, 0, 145, 2, 0, // Skip to: 8183 /* 7526 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7543 /* 7531 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7543 /* 7538 */ MCD_OPC_Decode, 193, 23, 170, 2, // Opcode: t2SMUSDX /* 7543 */ MCD_OPC_CheckPredicate, 45, 123, 2, 0, // Skip to: 8183 /* 7548 */ MCD_OPC_Decode, 174, 23, 175, 2, // Opcode: t2SMLSDX /* 7553 */ MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 8183 /* 7558 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 7561 */ MCD_OPC_FilterValue, 0, 105, 2, 0, // Skip to: 8183 /* 7566 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7583 /* 7571 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7583 /* 7578 */ MCD_OPC_Decode, 182, 23, 170, 2, // Opcode: t2SMMULR /* 7583 */ MCD_OPC_CheckPredicate, 45, 83, 2, 0, // Skip to: 8183 /* 7588 */ MCD_OPC_Decode, 178, 23, 175, 2, // Opcode: t2SMMLAR /* 7593 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 7622 /* 7598 */ MCD_OPC_CheckPredicate, 45, 68, 2, 0, // Skip to: 8183 /* 7603 */ MCD_OPC_CheckField, 23, 1, 1, 61, 2, 0, // Skip to: 8183 /* 7610 */ MCD_OPC_CheckField, 20, 1, 0, 54, 2, 0, // Skip to: 8183 /* 7617 */ MCD_OPC_Decode, 163, 23, 181, 2, // Opcode: t2SMLALBB /* 7622 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 7651 /* 7627 */ MCD_OPC_CheckPredicate, 45, 39, 2, 0, // Skip to: 8183 /* 7632 */ MCD_OPC_CheckField, 23, 1, 1, 32, 2, 0, // Skip to: 8183 /* 7639 */ MCD_OPC_CheckField, 20, 1, 0, 25, 2, 0, // Skip to: 8183 /* 7646 */ MCD_OPC_Decode, 164, 23, 181, 2, // Opcode: t2SMLALBT /* 7651 */ MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 7680 /* 7656 */ MCD_OPC_CheckPredicate, 45, 10, 2, 0, // Skip to: 8183 /* 7661 */ MCD_OPC_CheckField, 23, 1, 1, 3, 2, 0, // Skip to: 8183 /* 7668 */ MCD_OPC_CheckField, 20, 1, 0, 252, 1, 0, // Skip to: 8183 /* 7675 */ MCD_OPC_Decode, 167, 23, 181, 2, // Opcode: t2SMLALTB /* 7680 */ MCD_OPC_FilterValue, 11, 24, 0, 0, // Skip to: 7709 /* 7685 */ MCD_OPC_CheckPredicate, 45, 237, 1, 0, // Skip to: 8183 /* 7690 */ MCD_OPC_CheckField, 23, 1, 1, 230, 1, 0, // Skip to: 8183 /* 7697 */ MCD_OPC_CheckField, 20, 1, 0, 223, 1, 0, // Skip to: 8183 /* 7704 */ MCD_OPC_Decode, 168, 23, 181, 2, // Opcode: t2SMLALTT /* 7709 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 7761 /* 7714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7717 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7739 /* 7722 */ MCD_OPC_CheckPredicate, 45, 200, 1, 0, // Skip to: 8183 /* 7727 */ MCD_OPC_CheckField, 23, 1, 1, 193, 1, 0, // Skip to: 8183 /* 7734 */ MCD_OPC_Decode, 165, 23, 181, 2, // Opcode: t2SMLALD /* 7739 */ MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 8183 /* 7744 */ MCD_OPC_CheckPredicate, 45, 178, 1, 0, // Skip to: 8183 /* 7749 */ MCD_OPC_CheckField, 23, 1, 1, 171, 1, 0, // Skip to: 8183 /* 7756 */ MCD_OPC_Decode, 175, 23, 181, 2, // Opcode: t2SMLSLD /* 7761 */ MCD_OPC_FilterValue, 13, 161, 1, 0, // Skip to: 8183 /* 7766 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7769 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7791 /* 7774 */ MCD_OPC_CheckPredicate, 45, 148, 1, 0, // Skip to: 8183 /* 7779 */ MCD_OPC_CheckField, 23, 1, 1, 141, 1, 0, // Skip to: 8183 /* 7786 */ MCD_OPC_Decode, 166, 23, 181, 2, // Opcode: t2SMLALDX /* 7791 */ MCD_OPC_FilterValue, 1, 131, 1, 0, // Skip to: 8183 /* 7796 */ MCD_OPC_CheckPredicate, 45, 126, 1, 0, // Skip to: 8183 /* 7801 */ MCD_OPC_CheckField, 23, 1, 1, 119, 1, 0, // Skip to: 8183 /* 7808 */ MCD_OPC_Decode, 176, 23, 181, 2, // Opcode: t2SMLSLDX /* 7813 */ MCD_OPC_FilterValue, 3, 109, 1, 0, // Skip to: 8183 /* 7818 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 7821 */ MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 7957 /* 7826 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... /* 7829 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 7851 /* 7834 */ MCD_OPC_CheckPredicate, 38, 88, 1, 0, // Skip to: 8183 /* 7839 */ MCD_OPC_CheckField, 12, 4, 15, 81, 1, 0, // Skip to: 8183 /* 7846 */ MCD_OPC_Decode, 135, 23, 239, 1, // Opcode: t2RORrr /* 7851 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7880 /* 7856 */ MCD_OPC_CheckPredicate, 45, 66, 1, 0, // Skip to: 8183 /* 7861 */ MCD_OPC_CheckField, 20, 1, 0, 59, 1, 0, // Skip to: 8183 /* 7868 */ MCD_OPC_CheckField, 12, 4, 15, 52, 1, 0, // Skip to: 8183 /* 7875 */ MCD_OPC_Decode, 200, 23, 170, 2, // Opcode: t2SSAX /* 7880 */ MCD_OPC_FilterValue, 6, 50, 0, 0, // Skip to: 7935 /* 7885 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 7888 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7903 /* 7893 */ MCD_OPC_CheckPredicate, 45, 29, 1, 0, // Skip to: 8183 /* 7898 */ MCD_OPC_Decode, 179, 23, 175, 2, // Opcode: t2SMMLS /* 7903 */ MCD_OPC_FilterValue, 1, 19, 1, 0, // Skip to: 8183 /* 7908 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7925 /* 7913 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7925 /* 7920 */ MCD_OPC_Decode, 172, 24, 170, 2, // Opcode: t2USAD8 /* 7925 */ MCD_OPC_CheckPredicate, 45, 253, 0, 0, // Skip to: 8183 /* 7930 */ MCD_OPC_Decode, 173, 24, 175, 2, // Opcode: t2USADA8 /* 7935 */ MCD_OPC_FilterValue, 7, 243, 0, 0, // Skip to: 8183 /* 7940 */ MCD_OPC_CheckPredicate, 38, 238, 0, 0, // Skip to: 8183 /* 7945 */ MCD_OPC_CheckField, 20, 1, 0, 231, 0, 0, // Skip to: 8183 /* 7952 */ MCD_OPC_Decode, 164, 24, 181, 2, // Opcode: t2UMLAL /* 7957 */ MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 8016 /* 7962 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... /* 7965 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7994 /* 7970 */ MCD_OPC_CheckPredicate, 45, 208, 0, 0, // Skip to: 8183 /* 7975 */ MCD_OPC_CheckField, 20, 1, 0, 201, 0, 0, // Skip to: 8183 /* 7982 */ MCD_OPC_CheckField, 12, 4, 15, 194, 0, 0, // Skip to: 8183 /* 7989 */ MCD_OPC_Decode, 250, 22, 170, 2, // Opcode: t2QSAX /* 7994 */ MCD_OPC_FilterValue, 6, 184, 0, 0, // Skip to: 8183 /* 7999 */ MCD_OPC_CheckPredicate, 45, 179, 0, 0, // Skip to: 8183 /* 8004 */ MCD_OPC_CheckField, 20, 1, 0, 172, 0, 0, // Skip to: 8183 /* 8011 */ MCD_OPC_Decode, 180, 23, 175, 2, // Opcode: t2SMMLSR /* 8016 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 8052 /* 8021 */ MCD_OPC_CheckPredicate, 45, 157, 0, 0, // Skip to: 8183 /* 8026 */ MCD_OPC_CheckField, 23, 4, 5, 150, 0, 0, // Skip to: 8183 /* 8033 */ MCD_OPC_CheckField, 20, 1, 0, 143, 0, 0, // Skip to: 8183 /* 8040 */ MCD_OPC_CheckField, 12, 4, 15, 136, 0, 0, // Skip to: 8183 /* 8047 */ MCD_OPC_Decode, 154, 23, 170, 2, // Opcode: t2SHSAX /* 8052 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 8088 /* 8057 */ MCD_OPC_CheckPredicate, 45, 121, 0, 0, // Skip to: 8183 /* 8062 */ MCD_OPC_CheckField, 23, 4, 5, 114, 0, 0, // Skip to: 8183 /* 8069 */ MCD_OPC_CheckField, 20, 1, 0, 107, 0, 0, // Skip to: 8183 /* 8076 */ MCD_OPC_CheckField, 12, 4, 15, 100, 0, 0, // Skip to: 8183 /* 8083 */ MCD_OPC_Decode, 176, 24, 170, 2, // Opcode: t2USAX /* 8088 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 8124 /* 8093 */ MCD_OPC_CheckPredicate, 45, 85, 0, 0, // Skip to: 8183 /* 8098 */ MCD_OPC_CheckField, 23, 4, 5, 78, 0, 0, // Skip to: 8183 /* 8105 */ MCD_OPC_CheckField, 20, 1, 0, 71, 0, 0, // Skip to: 8183 /* 8112 */ MCD_OPC_CheckField, 12, 4, 15, 64, 0, 0, // Skip to: 8183 /* 8119 */ MCD_OPC_Decode, 169, 24, 170, 2, // Opcode: t2UQSAX /* 8124 */ MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 8183 /* 8129 */ MCD_OPC_ExtractField, 23, 4, // Inst{26-23} ... /* 8132 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 8161 /* 8137 */ MCD_OPC_CheckPredicate, 45, 41, 0, 0, // Skip to: 8183 /* 8142 */ MCD_OPC_CheckField, 20, 1, 0, 34, 0, 0, // Skip to: 8183 /* 8149 */ MCD_OPC_CheckField, 12, 4, 15, 27, 0, 0, // Skip to: 8183 /* 8156 */ MCD_OPC_Decode, 160, 24, 170, 2, // Opcode: t2UHSAX /* 8161 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 8183 /* 8166 */ MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 8183 /* 8171 */ MCD_OPC_CheckField, 20, 1, 0, 5, 0, 0, // Skip to: 8183 /* 8178 */ MCD_OPC_Decode, 163, 24, 181, 2, // Opcode: t2UMAAL /* 8183 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableThumb2CoProc32[] = { /* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 3 */ MCD_OPC_FilterValue, 236, 1, 175, 0, 0, // Skip to: 184 /* 9 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 12 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 33 /* 17 */ MCD_OPC_CheckPredicate, 38, 191, 2, 0, // Skip to: 725 /* 22 */ MCD_OPC_CheckField, 23, 1, 1, 184, 2, 0, // Skip to: 725 /* 29 */ MCD_OPC_Decode, 216, 23, 90, // Opcode: t2STC_OPTION /* 33 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 54 /* 38 */ MCD_OPC_CheckPredicate, 38, 170, 2, 0, // Skip to: 725 /* 43 */ MCD_OPC_CheckField, 23, 1, 1, 163, 2, 0, // Skip to: 725 /* 50 */ MCD_OPC_Decode, 145, 22, 90, // Opcode: t2LDC_OPTION /* 54 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 68 /* 59 */ MCD_OPC_CheckPredicate, 38, 149, 2, 0, // Skip to: 725 /* 64 */ MCD_OPC_Decode, 217, 23, 90, // Opcode: t2STC_POST /* 68 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82 /* 73 */ MCD_OPC_CheckPredicate, 38, 135, 2, 0, // Skip to: 725 /* 78 */ MCD_OPC_Decode, 146, 22, 90, // Opcode: t2LDC_POST /* 82 */ MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 119 /* 87 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 90 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 105 /* 95 */ MCD_OPC_CheckPredicate, 38, 113, 2, 0, // Skip to: 725 /* 100 */ MCD_OPC_Decode, 200, 22, 182, 2, // Opcode: t2MCRR /* 105 */ MCD_OPC_FilterValue, 1, 103, 2, 0, // Skip to: 725 /* 110 */ MCD_OPC_CheckPredicate, 38, 98, 2, 0, // Skip to: 725 /* 115 */ MCD_OPC_Decode, 212, 23, 90, // Opcode: t2STCL_OPTION /* 119 */ MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 156 /* 124 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 127 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 142 /* 132 */ MCD_OPC_CheckPredicate, 38, 76, 2, 0, // Skip to: 725 /* 137 */ MCD_OPC_Decode, 212, 22, 183, 2, // Opcode: t2MRRC /* 142 */ MCD_OPC_FilterValue, 1, 66, 2, 0, // Skip to: 725 /* 147 */ MCD_OPC_CheckPredicate, 38, 61, 2, 0, // Skip to: 725 /* 152 */ MCD_OPC_Decode, 141, 22, 90, // Opcode: t2LDCL_OPTION /* 156 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 170 /* 161 */ MCD_OPC_CheckPredicate, 38, 47, 2, 0, // Skip to: 725 /* 166 */ MCD_OPC_Decode, 213, 23, 90, // Opcode: t2STCL_POST /* 170 */ MCD_OPC_FilterValue, 7, 38, 2, 0, // Skip to: 725 /* 175 */ MCD_OPC_CheckPredicate, 38, 33, 2, 0, // Skip to: 725 /* 180 */ MCD_OPC_Decode, 142, 22, 90, // Opcode: t2LDCL_POST /* 184 */ MCD_OPC_FilterValue, 237, 1, 115, 0, 0, // Skip to: 305 /* 190 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 193 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207 /* 198 */ MCD_OPC_CheckPredicate, 38, 10, 2, 0, // Skip to: 725 /* 203 */ MCD_OPC_Decode, 215, 23, 90, // Opcode: t2STC_OFFSET /* 207 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 221 /* 212 */ MCD_OPC_CheckPredicate, 38, 252, 1, 0, // Skip to: 725 /* 217 */ MCD_OPC_Decode, 144, 22, 90, // Opcode: t2LDC_OFFSET /* 221 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 235 /* 226 */ MCD_OPC_CheckPredicate, 38, 238, 1, 0, // Skip to: 725 /* 231 */ MCD_OPC_Decode, 218, 23, 90, // Opcode: t2STC_PRE /* 235 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 249 /* 240 */ MCD_OPC_CheckPredicate, 38, 224, 1, 0, // Skip to: 725 /* 245 */ MCD_OPC_Decode, 147, 22, 90, // Opcode: t2LDC_PRE /* 249 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 263 /* 254 */ MCD_OPC_CheckPredicate, 38, 210, 1, 0, // Skip to: 725 /* 259 */ MCD_OPC_Decode, 211, 23, 90, // Opcode: t2STCL_OFFSET /* 263 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 277 /* 268 */ MCD_OPC_CheckPredicate, 38, 196, 1, 0, // Skip to: 725 /* 273 */ MCD_OPC_Decode, 140, 22, 90, // Opcode: t2LDCL_OFFSET /* 277 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 291 /* 282 */ MCD_OPC_CheckPredicate, 38, 182, 1, 0, // Skip to: 725 /* 287 */ MCD_OPC_Decode, 214, 23, 90, // Opcode: t2STCL_PRE /* 291 */ MCD_OPC_FilterValue, 7, 173, 1, 0, // Skip to: 725 /* 296 */ MCD_OPC_CheckPredicate, 38, 168, 1, 0, // Skip to: 725 /* 301 */ MCD_OPC_Decode, 143, 22, 90, // Opcode: t2LDCL_PRE /* 305 */ MCD_OPC_FilterValue, 238, 1, 53, 0, 0, // Skip to: 364 /* 311 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 314 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 328 /* 319 */ MCD_OPC_CheckPredicate, 58, 145, 1, 0, // Skip to: 725 /* 324 */ MCD_OPC_Decode, 219, 21, 91, // Opcode: t2CDP /* 328 */ MCD_OPC_FilterValue, 1, 136, 1, 0, // Skip to: 725 /* 333 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 336 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 350 /* 341 */ MCD_OPC_CheckPredicate, 38, 123, 1, 0, // Skip to: 725 /* 346 */ MCD_OPC_Decode, 198, 22, 93, // Opcode: t2MCR /* 350 */ MCD_OPC_FilterValue, 1, 114, 1, 0, // Skip to: 725 /* 355 */ MCD_OPC_CheckPredicate, 38, 109, 1, 0, // Skip to: 725 /* 360 */ MCD_OPC_Decode, 210, 22, 95, // Opcode: t2MRC /* 364 */ MCD_OPC_FilterValue, 252, 1, 175, 0, 0, // Skip to: 545 /* 370 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 373 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 394 /* 378 */ MCD_OPC_CheckPredicate, 59, 86, 1, 0, // Skip to: 725 /* 383 */ MCD_OPC_CheckField, 23, 1, 1, 79, 1, 0, // Skip to: 725 /* 390 */ MCD_OPC_Decode, 208, 23, 90, // Opcode: t2STC2_OPTION /* 394 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 415 /* 399 */ MCD_OPC_CheckPredicate, 59, 65, 1, 0, // Skip to: 725 /* 404 */ MCD_OPC_CheckField, 23, 1, 1, 58, 1, 0, // Skip to: 725 /* 411 */ MCD_OPC_Decode, 137, 22, 90, // Opcode: t2LDC2_OPTION /* 415 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 429 /* 420 */ MCD_OPC_CheckPredicate, 59, 44, 1, 0, // Skip to: 725 /* 425 */ MCD_OPC_Decode, 209, 23, 90, // Opcode: t2STC2_POST /* 429 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 443 /* 434 */ MCD_OPC_CheckPredicate, 59, 30, 1, 0, // Skip to: 725 /* 439 */ MCD_OPC_Decode, 138, 22, 90, // Opcode: t2LDC2_POST /* 443 */ MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 480 /* 448 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 451 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 466 /* 456 */ MCD_OPC_CheckPredicate, 58, 8, 1, 0, // Skip to: 725 /* 461 */ MCD_OPC_Decode, 201, 22, 182, 2, // Opcode: t2MCRR2 /* 466 */ MCD_OPC_FilterValue, 1, 254, 0, 0, // Skip to: 725 /* 471 */ MCD_OPC_CheckPredicate, 59, 249, 0, 0, // Skip to: 725 /* 476 */ MCD_OPC_Decode, 204, 23, 90, // Opcode: t2STC2L_OPTION /* 480 */ MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 517 /* 485 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 488 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 503 /* 493 */ MCD_OPC_CheckPredicate, 58, 227, 0, 0, // Skip to: 725 /* 498 */ MCD_OPC_Decode, 213, 22, 183, 2, // Opcode: t2MRRC2 /* 503 */ MCD_OPC_FilterValue, 1, 217, 0, 0, // Skip to: 725 /* 508 */ MCD_OPC_CheckPredicate, 59, 212, 0, 0, // Skip to: 725 /* 513 */ MCD_OPC_Decode, 133, 22, 90, // Opcode: t2LDC2L_OPTION /* 517 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 531 /* 522 */ MCD_OPC_CheckPredicate, 59, 198, 0, 0, // Skip to: 725 /* 527 */ MCD_OPC_Decode, 205, 23, 90, // Opcode: t2STC2L_POST /* 531 */ MCD_OPC_FilterValue, 7, 189, 0, 0, // Skip to: 725 /* 536 */ MCD_OPC_CheckPredicate, 59, 184, 0, 0, // Skip to: 725 /* 541 */ MCD_OPC_Decode, 134, 22, 90, // Opcode: t2LDC2L_POST /* 545 */ MCD_OPC_FilterValue, 253, 1, 115, 0, 0, // Skip to: 666 /* 551 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... /* 554 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 568 /* 559 */ MCD_OPC_CheckPredicate, 59, 161, 0, 0, // Skip to: 725 /* 564 */ MCD_OPC_Decode, 207, 23, 90, // Opcode: t2STC2_OFFSET /* 568 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 582 /* 573 */ MCD_OPC_CheckPredicate, 59, 147, 0, 0, // Skip to: 725 /* 578 */ MCD_OPC_Decode, 136, 22, 90, // Opcode: t2LDC2_OFFSET /* 582 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 596 /* 587 */ MCD_OPC_CheckPredicate, 59, 133, 0, 0, // Skip to: 725 /* 592 */ MCD_OPC_Decode, 210, 23, 90, // Opcode: t2STC2_PRE /* 596 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 610 /* 601 */ MCD_OPC_CheckPredicate, 59, 119, 0, 0, // Skip to: 725 /* 606 */ MCD_OPC_Decode, 139, 22, 90, // Opcode: t2LDC2_PRE /* 610 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 624 /* 615 */ MCD_OPC_CheckPredicate, 59, 105, 0, 0, // Skip to: 725 /* 620 */ MCD_OPC_Decode, 203, 23, 90, // Opcode: t2STC2L_OFFSET /* 624 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 638 /* 629 */ MCD_OPC_CheckPredicate, 59, 91, 0, 0, // Skip to: 725 /* 634 */ MCD_OPC_Decode, 132, 22, 90, // Opcode: t2LDC2L_OFFSET /* 638 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 652 /* 643 */ MCD_OPC_CheckPredicate, 59, 77, 0, 0, // Skip to: 725 /* 648 */ MCD_OPC_Decode, 206, 23, 90, // Opcode: t2STC2L_PRE /* 652 */ MCD_OPC_FilterValue, 7, 68, 0, 0, // Skip to: 725 /* 657 */ MCD_OPC_CheckPredicate, 59, 63, 0, 0, // Skip to: 725 /* 662 */ MCD_OPC_Decode, 135, 22, 90, // Opcode: t2LDC2L_PRE /* 666 */ MCD_OPC_FilterValue, 254, 1, 53, 0, 0, // Skip to: 725 /* 672 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 675 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 689 /* 680 */ MCD_OPC_CheckPredicate, 58, 40, 0, 0, // Skip to: 725 /* 685 */ MCD_OPC_Decode, 220, 21, 91, // Opcode: t2CDP2 /* 689 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 725 /* 694 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 697 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 711 /* 702 */ MCD_OPC_CheckPredicate, 58, 18, 0, 0, // Skip to: 725 /* 707 */ MCD_OPC_Decode, 199, 22, 93, // Opcode: t2MCR2 /* 711 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 725 /* 716 */ MCD_OPC_CheckPredicate, 58, 4, 0, 0, // Skip to: 725 /* 721 */ MCD_OPC_Decode, 211, 22, 95, // Opcode: t2MRC2 /* 725 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableThumbSBit16[] = { /* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... /* 3 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18 /* 8 */ MCD_OPC_CheckPredicate, 28, 95, 1, 0, // Skip to: 364 /* 13 */ MCD_OPC_Decode, 232, 24, 184, 2, // Opcode: tLSLri /* 18 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 33 /* 23 */ MCD_OPC_CheckPredicate, 28, 80, 1, 0, // Skip to: 364 /* 28 */ MCD_OPC_Decode, 234, 24, 184, 2, // Opcode: tLSRri /* 33 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 48 /* 38 */ MCD_OPC_CheckPredicate, 28, 65, 1, 0, // Skip to: 364 /* 43 */ MCD_OPC_Decode, 196, 24, 184, 2, // Opcode: tASRri /* 48 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 116 /* 53 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 56 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71 /* 61 */ MCD_OPC_CheckPredicate, 28, 42, 1, 0, // Skip to: 364 /* 66 */ MCD_OPC_Decode, 191, 24, 185, 2, // Opcode: tADDrr /* 71 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 86 /* 76 */ MCD_OPC_CheckPredicate, 28, 27, 1, 0, // Skip to: 364 /* 81 */ MCD_OPC_Decode, 134, 25, 185, 2, // Opcode: tSUBrr /* 86 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101 /* 91 */ MCD_OPC_CheckPredicate, 28, 12, 1, 0, // Skip to: 364 /* 96 */ MCD_OPC_Decode, 187, 24, 186, 2, // Opcode: tADDi3 /* 101 */ MCD_OPC_FilterValue, 3, 2, 1, 0, // Skip to: 364 /* 106 */ MCD_OPC_CheckPredicate, 28, 253, 0, 0, // Skip to: 364 /* 111 */ MCD_OPC_Decode, 132, 25, 186, 2, // Opcode: tSUBi3 /* 116 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 131 /* 121 */ MCD_OPC_CheckPredicate, 28, 238, 0, 0, // Skip to: 364 /* 126 */ MCD_OPC_Decode, 237, 24, 208, 1, // Opcode: tMOVi8 /* 131 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 146 /* 136 */ MCD_OPC_CheckPredicate, 28, 223, 0, 0, // Skip to: 364 /* 141 */ MCD_OPC_Decode, 188, 24, 187, 2, // Opcode: tADDi8 /* 146 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 161 /* 151 */ MCD_OPC_CheckPredicate, 28, 208, 0, 0, // Skip to: 364 /* 156 */ MCD_OPC_Decode, 133, 25, 187, 2, // Opcode: tSUBi8 /* 161 */ MCD_OPC_FilterValue, 8, 198, 0, 0, // Skip to: 364 /* 166 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 169 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 184 /* 174 */ MCD_OPC_CheckPredicate, 28, 185, 0, 0, // Skip to: 364 /* 179 */ MCD_OPC_Decode, 195, 24, 188, 2, // Opcode: tAND /* 184 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 199 /* 189 */ MCD_OPC_CheckPredicate, 28, 170, 0, 0, // Skip to: 364 /* 194 */ MCD_OPC_Decode, 215, 24, 188, 2, // Opcode: tEOR /* 199 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 214 /* 204 */ MCD_OPC_CheckPredicate, 28, 155, 0, 0, // Skip to: 364 /* 209 */ MCD_OPC_Decode, 233, 24, 188, 2, // Opcode: tLSLrr /* 214 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 229 /* 219 */ MCD_OPC_CheckPredicate, 28, 140, 0, 0, // Skip to: 364 /* 224 */ MCD_OPC_Decode, 235, 24, 188, 2, // Opcode: tLSRrr /* 229 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 244 /* 234 */ MCD_OPC_CheckPredicate, 28, 125, 0, 0, // Skip to: 364 /* 239 */ MCD_OPC_Decode, 197, 24, 188, 2, // Opcode: tASRrr /* 244 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 259 /* 249 */ MCD_OPC_CheckPredicate, 28, 110, 0, 0, // Skip to: 364 /* 254 */ MCD_OPC_Decode, 185, 24, 188, 2, // Opcode: tADC /* 259 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 274 /* 264 */ MCD_OPC_CheckPredicate, 28, 95, 0, 0, // Skip to: 364 /* 269 */ MCD_OPC_Decode, 250, 24, 188, 2, // Opcode: tSBC /* 274 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 289 /* 279 */ MCD_OPC_CheckPredicate, 28, 80, 0, 0, // Skip to: 364 /* 284 */ MCD_OPC_Decode, 248, 24, 188, 2, // Opcode: tROR /* 289 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 304 /* 294 */ MCD_OPC_CheckPredicate, 28, 65, 0, 0, // Skip to: 364 /* 299 */ MCD_OPC_Decode, 249, 24, 207, 1, // Opcode: tRSB /* 304 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 319 /* 309 */ MCD_OPC_CheckPredicate, 28, 50, 0, 0, // Skip to: 364 /* 314 */ MCD_OPC_Decode, 241, 24, 188, 2, // Opcode: tORR /* 319 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 334 /* 324 */ MCD_OPC_CheckPredicate, 28, 35, 0, 0, // Skip to: 364 /* 329 */ MCD_OPC_Decode, 239, 24, 189, 2, // Opcode: tMUL /* 334 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 349 /* 339 */ MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 364 /* 344 */ MCD_OPC_Decode, 199, 24, 188, 2, // Opcode: tBIC /* 349 */ MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 364 /* 354 */ MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 364 /* 359 */ MCD_OPC_Decode, 240, 24, 207, 1, // Opcode: tMVN /* 364 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableVFP32[] = { /* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 3 */ MCD_OPC_FilterValue, 0, 21, 2, 0, // Skip to: 541 /* 8 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 11 */ MCD_OPC_FilterValue, 9, 130, 0, 0, // Skip to: 146 /* 16 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 19 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 34 /* 24 */ MCD_OPC_CheckPredicate, 60, 247, 16, 0, // Skip to: 4372 /* 29 */ MCD_OPC_Decode, 205, 20, 190, 2, // Opcode: VSTRH /* 34 */ MCD_OPC_FilterValue, 14, 237, 16, 0, // Skip to: 4372 /* 39 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 42 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 110 /* 47 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 50 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 88 /* 55 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 58 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73 /* 63 */ MCD_OPC_CheckPredicate, 60, 208, 16, 0, // Skip to: 4372 /* 68 */ MCD_OPC_Decode, 203, 13, 191, 2, // Opcode: VMLAH /* 73 */ MCD_OPC_FilterValue, 1, 198, 16, 0, // Skip to: 4372 /* 78 */ MCD_OPC_CheckPredicate, 60, 193, 16, 0, // Skip to: 4372 /* 83 */ MCD_OPC_Decode, 254, 9, 192, 2, // Opcode: VDIVH /* 88 */ MCD_OPC_FilterValue, 1, 183, 16, 0, // Skip to: 4372 /* 93 */ MCD_OPC_CheckPredicate, 60, 178, 16, 0, // Skip to: 4372 /* 98 */ MCD_OPC_CheckField, 23, 1, 0, 171, 16, 0, // Skip to: 4372 /* 105 */ MCD_OPC_Decode, 234, 13, 191, 2, // Opcode: VMLSH /* 110 */ MCD_OPC_FilterValue, 1, 161, 16, 0, // Skip to: 4372 /* 115 */ MCD_OPC_CheckPredicate, 60, 156, 16, 0, // Skip to: 4372 /* 120 */ MCD_OPC_CheckField, 22, 2, 0, 149, 16, 0, // Skip to: 4372 /* 127 */ MCD_OPC_CheckField, 5, 2, 0, 142, 16, 0, // Skip to: 4372 /* 134 */ MCD_OPC_CheckField, 0, 4, 0, 135, 16, 0, // Skip to: 4372 /* 141 */ MCD_OPC_Decode, 139, 14, 193, 2, // Opcode: VMOVHR /* 146 */ MCD_OPC_FilterValue, 10, 189, 0, 0, // Skip to: 340 /* 151 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 154 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 213 /* 159 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 162 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 198 /* 167 */ MCD_OPC_CheckPredicate, 27, 104, 16, 0, // Skip to: 4372 /* 172 */ MCD_OPC_CheckField, 22, 1, 1, 97, 16, 0, // Skip to: 4372 /* 179 */ MCD_OPC_CheckField, 6, 2, 0, 90, 16, 0, // Skip to: 4372 /* 186 */ MCD_OPC_CheckField, 4, 1, 1, 83, 16, 0, // Skip to: 4372 /* 193 */ MCD_OPC_Decode, 155, 14, 194, 2, // Opcode: VMOVSRR /* 198 */ MCD_OPC_FilterValue, 1, 73, 16, 0, // Skip to: 4372 /* 203 */ MCD_OPC_CheckPredicate, 27, 68, 16, 0, // Skip to: 4372 /* 208 */ MCD_OPC_Decode, 202, 20, 195, 2, // Opcode: VSTMSIA /* 213 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 228 /* 218 */ MCD_OPC_CheckPredicate, 27, 53, 16, 0, // Skip to: 4372 /* 223 */ MCD_OPC_Decode, 206, 20, 196, 2, // Opcode: VSTRS /* 228 */ MCD_OPC_FilterValue, 14, 43, 16, 0, // Skip to: 4372 /* 233 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 236 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 304 /* 241 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 244 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 282 /* 249 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 252 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 267 /* 257 */ MCD_OPC_CheckPredicate, 27, 14, 16, 0, // Skip to: 4372 /* 262 */ MCD_OPC_Decode, 214, 13, 197, 2, // Opcode: VMLAS /* 267 */ MCD_OPC_FilterValue, 1, 4, 16, 0, // Skip to: 4372 /* 272 */ MCD_OPC_CheckPredicate, 27, 255, 15, 0, // Skip to: 4372 /* 277 */ MCD_OPC_Decode, 255, 9, 198, 2, // Opcode: VDIVS /* 282 */ MCD_OPC_FilterValue, 1, 245, 15, 0, // Skip to: 4372 /* 287 */ MCD_OPC_CheckPredicate, 27, 240, 15, 0, // Skip to: 4372 /* 292 */ MCD_OPC_CheckField, 23, 1, 0, 233, 15, 0, // Skip to: 4372 /* 299 */ MCD_OPC_Decode, 245, 13, 197, 2, // Opcode: VMLSS /* 304 */ MCD_OPC_FilterValue, 1, 223, 15, 0, // Skip to: 4372 /* 309 */ MCD_OPC_CheckPredicate, 27, 218, 15, 0, // Skip to: 4372 /* 314 */ MCD_OPC_CheckField, 22, 2, 0, 211, 15, 0, // Skip to: 4372 /* 321 */ MCD_OPC_CheckField, 5, 2, 0, 204, 15, 0, // Skip to: 4372 /* 328 */ MCD_OPC_CheckField, 0, 4, 0, 197, 15, 0, // Skip to: 4372 /* 335 */ MCD_OPC_Decode, 154, 14, 199, 2, // Opcode: VMOVSR /* 340 */ MCD_OPC_FilterValue, 11, 187, 15, 0, // Skip to: 4372 /* 345 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 348 */ MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 437 /* 353 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 356 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 392 /* 361 */ MCD_OPC_CheckPredicate, 27, 166, 15, 0, // Skip to: 4372 /* 366 */ MCD_OPC_CheckField, 22, 1, 1, 159, 15, 0, // Skip to: 4372 /* 373 */ MCD_OPC_CheckField, 6, 2, 0, 152, 15, 0, // Skip to: 4372 /* 380 */ MCD_OPC_CheckField, 4, 1, 1, 145, 15, 0, // Skip to: 4372 /* 387 */ MCD_OPC_Decode, 137, 14, 200, 2, // Opcode: VMOVDRR /* 392 */ MCD_OPC_FilterValue, 1, 135, 15, 0, // Skip to: 4372 /* 397 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 400 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 415 /* 405 */ MCD_OPC_CheckPredicate, 27, 122, 15, 0, // Skip to: 4372 /* 410 */ MCD_OPC_Decode, 198, 20, 201, 2, // Opcode: VSTMDIA /* 415 */ MCD_OPC_FilterValue, 1, 112, 15, 0, // Skip to: 4372 /* 420 */ MCD_OPC_CheckPredicate, 27, 107, 15, 0, // Skip to: 4372 /* 425 */ MCD_OPC_CheckField, 22, 1, 0, 100, 15, 0, // Skip to: 4372 /* 432 */ MCD_OPC_Decode, 216, 4, 202, 2, // Opcode: FSTMXIA /* 437 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 452 /* 442 */ MCD_OPC_CheckPredicate, 27, 85, 15, 0, // Skip to: 4372 /* 447 */ MCD_OPC_Decode, 204, 20, 203, 2, // Opcode: VSTRD /* 452 */ MCD_OPC_FilterValue, 14, 75, 15, 0, // Skip to: 4372 /* 457 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 460 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 512 /* 465 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 468 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 490 /* 473 */ MCD_OPC_CheckPredicate, 61, 54, 15, 0, // Skip to: 4372 /* 478 */ MCD_OPC_CheckField, 4, 1, 0, 47, 15, 0, // Skip to: 4372 /* 485 */ MCD_OPC_Decode, 202, 13, 204, 2, // Opcode: VMLAD /* 490 */ MCD_OPC_FilterValue, 1, 37, 15, 0, // Skip to: 4372 /* 495 */ MCD_OPC_CheckPredicate, 61, 32, 15, 0, // Skip to: 4372 /* 500 */ MCD_OPC_CheckField, 4, 1, 0, 25, 15, 0, // Skip to: 4372 /* 507 */ MCD_OPC_Decode, 253, 9, 205, 2, // Opcode: VDIVD /* 512 */ MCD_OPC_FilterValue, 1, 15, 15, 0, // Skip to: 4372 /* 517 */ MCD_OPC_CheckPredicate, 61, 10, 15, 0, // Skip to: 4372 /* 522 */ MCD_OPC_CheckField, 23, 1, 0, 3, 15, 0, // Skip to: 4372 /* 529 */ MCD_OPC_CheckField, 4, 1, 0, 252, 14, 0, // Skip to: 4372 /* 536 */ MCD_OPC_Decode, 233, 13, 204, 2, // Opcode: VMLSD /* 541 */ MCD_OPC_FilterValue, 1, 76, 2, 0, // Skip to: 1134 /* 546 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 549 */ MCD_OPC_FilterValue, 9, 146, 0, 0, // Skip to: 700 /* 554 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 557 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 572 /* 562 */ MCD_OPC_CheckPredicate, 60, 221, 14, 0, // Skip to: 4372 /* 567 */ MCD_OPC_Decode, 152, 13, 190, 2, // Opcode: VLDRH /* 572 */ MCD_OPC_FilterValue, 14, 211, 14, 0, // Skip to: 4372 /* 577 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 580 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 664 /* 585 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 588 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 626 /* 593 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 596 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 611 /* 601 */ MCD_OPC_CheckPredicate, 60, 182, 14, 0, // Skip to: 4372 /* 606 */ MCD_OPC_Decode, 237, 14, 191, 2, // Opcode: VNMLSH /* 611 */ MCD_OPC_FilterValue, 1, 172, 14, 0, // Skip to: 4372 /* 616 */ MCD_OPC_CheckPredicate, 60, 167, 14, 0, // Skip to: 4372 /* 621 */ MCD_OPC_Decode, 167, 10, 191, 2, // Opcode: VFNMSH /* 626 */ MCD_OPC_FilterValue, 1, 157, 14, 0, // Skip to: 4372 /* 631 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 634 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 649 /* 639 */ MCD_OPC_CheckPredicate, 60, 144, 14, 0, // Skip to: 4372 /* 644 */ MCD_OPC_Decode, 234, 14, 191, 2, // Opcode: VNMLAH /* 649 */ MCD_OPC_FilterValue, 1, 134, 14, 0, // Skip to: 4372 /* 654 */ MCD_OPC_CheckPredicate, 60, 129, 14, 0, // Skip to: 4372 /* 659 */ MCD_OPC_Decode, 164, 10, 191, 2, // Opcode: VFNMAH /* 664 */ MCD_OPC_FilterValue, 1, 119, 14, 0, // Skip to: 4372 /* 669 */ MCD_OPC_CheckPredicate, 60, 114, 14, 0, // Skip to: 4372 /* 674 */ MCD_OPC_CheckField, 22, 2, 0, 107, 14, 0, // Skip to: 4372 /* 681 */ MCD_OPC_CheckField, 5, 2, 0, 100, 14, 0, // Skip to: 4372 /* 688 */ MCD_OPC_CheckField, 0, 4, 0, 93, 14, 0, // Skip to: 4372 /* 695 */ MCD_OPC_Decode, 149, 14, 206, 2, // Opcode: VMOVRH /* 700 */ MCD_OPC_FilterValue, 10, 205, 0, 0, // Skip to: 910 /* 705 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 708 */ MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 767 /* 713 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 716 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 752 /* 721 */ MCD_OPC_CheckPredicate, 27, 62, 14, 0, // Skip to: 4372 /* 726 */ MCD_OPC_CheckField, 22, 1, 1, 55, 14, 0, // Skip to: 4372 /* 733 */ MCD_OPC_CheckField, 6, 2, 0, 48, 14, 0, // Skip to: 4372 /* 740 */ MCD_OPC_CheckField, 4, 1, 1, 41, 14, 0, // Skip to: 4372 /* 747 */ MCD_OPC_Decode, 151, 14, 207, 2, // Opcode: VMOVRRS /* 752 */ MCD_OPC_FilterValue, 1, 31, 14, 0, // Skip to: 4372 /* 757 */ MCD_OPC_CheckPredicate, 27, 26, 14, 0, // Skip to: 4372 /* 762 */ MCD_OPC_Decode, 149, 13, 195, 2, // Opcode: VLDMSIA /* 767 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 782 /* 772 */ MCD_OPC_CheckPredicate, 27, 11, 14, 0, // Skip to: 4372 /* 777 */ MCD_OPC_Decode, 153, 13, 196, 2, // Opcode: VLDRS /* 782 */ MCD_OPC_FilterValue, 14, 1, 14, 0, // Skip to: 4372 /* 787 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 790 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 874 /* 795 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 798 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 836 /* 803 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 806 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 821 /* 811 */ MCD_OPC_CheckPredicate, 27, 228, 13, 0, // Skip to: 4372 /* 816 */ MCD_OPC_Decode, 238, 14, 197, 2, // Opcode: VNMLSS /* 821 */ MCD_OPC_FilterValue, 1, 218, 13, 0, // Skip to: 4372 /* 826 */ MCD_OPC_CheckPredicate, 62, 213, 13, 0, // Skip to: 4372 /* 831 */ MCD_OPC_Decode, 168, 10, 197, 2, // Opcode: VFNMSS /* 836 */ MCD_OPC_FilterValue, 1, 203, 13, 0, // Skip to: 4372 /* 841 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 844 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 859 /* 849 */ MCD_OPC_CheckPredicate, 27, 190, 13, 0, // Skip to: 4372 /* 854 */ MCD_OPC_Decode, 235, 14, 197, 2, // Opcode: VNMLAS /* 859 */ MCD_OPC_FilterValue, 1, 180, 13, 0, // Skip to: 4372 /* 864 */ MCD_OPC_CheckPredicate, 62, 175, 13, 0, // Skip to: 4372 /* 869 */ MCD_OPC_Decode, 165, 10, 197, 2, // Opcode: VFNMAS /* 874 */ MCD_OPC_FilterValue, 1, 165, 13, 0, // Skip to: 4372 /* 879 */ MCD_OPC_CheckPredicate, 27, 160, 13, 0, // Skip to: 4372 /* 884 */ MCD_OPC_CheckField, 22, 2, 0, 153, 13, 0, // Skip to: 4372 /* 891 */ MCD_OPC_CheckField, 5, 2, 0, 146, 13, 0, // Skip to: 4372 /* 898 */ MCD_OPC_CheckField, 0, 4, 0, 139, 13, 0, // Skip to: 4372 /* 905 */ MCD_OPC_Decode, 152, 14, 208, 2, // Opcode: VMOVRS /* 910 */ MCD_OPC_FilterValue, 11, 129, 13, 0, // Skip to: 4372 /* 915 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 918 */ MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 1007 /* 923 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 926 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 962 /* 931 */ MCD_OPC_CheckPredicate, 27, 108, 13, 0, // Skip to: 4372 /* 936 */ MCD_OPC_CheckField, 22, 1, 1, 101, 13, 0, // Skip to: 4372 /* 943 */ MCD_OPC_CheckField, 6, 2, 0, 94, 13, 0, // Skip to: 4372 /* 950 */ MCD_OPC_CheckField, 4, 1, 1, 87, 13, 0, // Skip to: 4372 /* 957 */ MCD_OPC_Decode, 150, 14, 209, 2, // Opcode: VMOVRRD /* 962 */ MCD_OPC_FilterValue, 1, 77, 13, 0, // Skip to: 4372 /* 967 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 970 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 985 /* 975 */ MCD_OPC_CheckPredicate, 27, 64, 13, 0, // Skip to: 4372 /* 980 */ MCD_OPC_Decode, 145, 13, 201, 2, // Opcode: VLDMDIA /* 985 */ MCD_OPC_FilterValue, 1, 54, 13, 0, // Skip to: 4372 /* 990 */ MCD_OPC_CheckPredicate, 27, 49, 13, 0, // Skip to: 4372 /* 995 */ MCD_OPC_CheckField, 22, 1, 0, 42, 13, 0, // Skip to: 4372 /* 1002 */ MCD_OPC_Decode, 212, 4, 202, 2, // Opcode: FLDMXIA /* 1007 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1022 /* 1012 */ MCD_OPC_CheckPredicate, 27, 27, 13, 0, // Skip to: 4372 /* 1017 */ MCD_OPC_Decode, 151, 13, 203, 2, // Opcode: VLDRD /* 1022 */ MCD_OPC_FilterValue, 14, 17, 13, 0, // Skip to: 4372 /* 1027 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1030 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1082 /* 1035 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 1038 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1060 /* 1043 */ MCD_OPC_CheckPredicate, 61, 252, 12, 0, // Skip to: 4372 /* 1048 */ MCD_OPC_CheckField, 4, 1, 0, 245, 12, 0, // Skip to: 4372 /* 1055 */ MCD_OPC_Decode, 236, 14, 204, 2, // Opcode: VNMLSD /* 1060 */ MCD_OPC_FilterValue, 1, 235, 12, 0, // Skip to: 4372 /* 1065 */ MCD_OPC_CheckPredicate, 63, 230, 12, 0, // Skip to: 4372 /* 1070 */ MCD_OPC_CheckField, 4, 1, 0, 223, 12, 0, // Skip to: 4372 /* 1077 */ MCD_OPC_Decode, 166, 10, 204, 2, // Opcode: VFNMSD /* 1082 */ MCD_OPC_FilterValue, 1, 213, 12, 0, // Skip to: 4372 /* 1087 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... /* 1090 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1112 /* 1095 */ MCD_OPC_CheckPredicate, 61, 200, 12, 0, // Skip to: 4372 /* 1100 */ MCD_OPC_CheckField, 4, 1, 0, 193, 12, 0, // Skip to: 4372 /* 1107 */ MCD_OPC_Decode, 233, 14, 204, 2, // Opcode: VNMLAD /* 1112 */ MCD_OPC_FilterValue, 1, 183, 12, 0, // Skip to: 4372 /* 1117 */ MCD_OPC_CheckPredicate, 63, 178, 12, 0, // Skip to: 4372 /* 1122 */ MCD_OPC_CheckField, 4, 1, 0, 171, 12, 0, // Skip to: 4372 /* 1129 */ MCD_OPC_Decode, 163, 10, 204, 2, // Opcode: VFNMAD /* 1134 */ MCD_OPC_FilterValue, 2, 132, 2, 0, // Skip to: 1783 /* 1139 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... /* 1142 */ MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1172 /* 1147 */ MCD_OPC_CheckPredicate, 64, 148, 12, 0, // Skip to: 4372 /* 1152 */ MCD_OPC_CheckField, 22, 1, 0, 141, 12, 0, // Skip to: 4372 /* 1159 */ MCD_OPC_CheckField, 0, 16, 128, 20, 133, 12, 0, // Skip to: 4372 /* 1167 */ MCD_OPC_Decode, 155, 13, 210, 2, // Opcode: VLSTM /* 1172 */ MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1240 /* 1177 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1180 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1195 /* 1185 */ MCD_OPC_CheckPredicate, 27, 110, 12, 0, // Skip to: 4372 /* 1190 */ MCD_OPC_Decode, 203, 20, 211, 2, // Opcode: VSTMSIA_UPD /* 1195 */ MCD_OPC_FilterValue, 11, 100, 12, 0, // Skip to: 4372 /* 1200 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 1203 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1218 /* 1208 */ MCD_OPC_CheckPredicate, 27, 87, 12, 0, // Skip to: 4372 /* 1213 */ MCD_OPC_Decode, 199, 20, 212, 2, // Opcode: VSTMDIA_UPD /* 1218 */ MCD_OPC_FilterValue, 1, 77, 12, 0, // Skip to: 4372 /* 1223 */ MCD_OPC_CheckPredicate, 27, 72, 12, 0, // Skip to: 4372 /* 1228 */ MCD_OPC_CheckField, 22, 1, 0, 65, 12, 0, // Skip to: 4372 /* 1235 */ MCD_OPC_Decode, 217, 4, 213, 2, // Opcode: FSTMXIA_UPD /* 1240 */ MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1308 /* 1245 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1248 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1263 /* 1253 */ MCD_OPC_CheckPredicate, 27, 42, 12, 0, // Skip to: 4372 /* 1258 */ MCD_OPC_Decode, 201, 20, 211, 2, // Opcode: VSTMSDB_UPD /* 1263 */ MCD_OPC_FilterValue, 11, 32, 12, 0, // Skip to: 4372 /* 1268 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 1271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1286 /* 1276 */ MCD_OPC_CheckPredicate, 27, 19, 12, 0, // Skip to: 4372 /* 1281 */ MCD_OPC_Decode, 197, 20, 212, 2, // Opcode: VSTMDDB_UPD /* 1286 */ MCD_OPC_FilterValue, 1, 9, 12, 0, // Skip to: 4372 /* 1291 */ MCD_OPC_CheckPredicate, 27, 4, 12, 0, // Skip to: 4372 /* 1296 */ MCD_OPC_CheckField, 22, 1, 0, 253, 11, 0, // Skip to: 4372 /* 1303 */ MCD_OPC_Decode, 215, 4, 213, 2, // Opcode: FSTMXDB_UPD /* 1308 */ MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 1472 /* 1313 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1316 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1368 /* 1321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1324 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1346 /* 1329 */ MCD_OPC_CheckPredicate, 60, 222, 11, 0, // Skip to: 4372 /* 1334 */ MCD_OPC_CheckField, 4, 1, 0, 215, 11, 0, // Skip to: 4372 /* 1341 */ MCD_OPC_Decode, 180, 14, 192, 2, // Opcode: VMULH /* 1346 */ MCD_OPC_FilterValue, 1, 205, 11, 0, // Skip to: 4372 /* 1351 */ MCD_OPC_CheckPredicate, 60, 200, 11, 0, // Skip to: 4372 /* 1356 */ MCD_OPC_CheckField, 4, 1, 0, 193, 11, 0, // Skip to: 4372 /* 1363 */ MCD_OPC_Decode, 240, 14, 192, 2, // Opcode: VNMULH /* 1368 */ MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 1420 /* 1373 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1376 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1398 /* 1381 */ MCD_OPC_CheckPredicate, 27, 170, 11, 0, // Skip to: 4372 /* 1386 */ MCD_OPC_CheckField, 4, 1, 0, 163, 11, 0, // Skip to: 4372 /* 1393 */ MCD_OPC_Decode, 193, 14, 198, 2, // Opcode: VMULS /* 1398 */ MCD_OPC_FilterValue, 1, 153, 11, 0, // Skip to: 4372 /* 1403 */ MCD_OPC_CheckPredicate, 27, 148, 11, 0, // Skip to: 4372 /* 1408 */ MCD_OPC_CheckField, 4, 1, 0, 141, 11, 0, // Skip to: 4372 /* 1415 */ MCD_OPC_Decode, 241, 14, 198, 2, // Opcode: VNMULS /* 1420 */ MCD_OPC_FilterValue, 11, 131, 11, 0, // Skip to: 4372 /* 1425 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1428 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1450 /* 1433 */ MCD_OPC_CheckPredicate, 61, 118, 11, 0, // Skip to: 4372 /* 1438 */ MCD_OPC_CheckField, 4, 1, 0, 111, 11, 0, // Skip to: 4372 /* 1445 */ MCD_OPC_Decode, 179, 14, 205, 2, // Opcode: VMULD /* 1450 */ MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 4372 /* 1455 */ MCD_OPC_CheckPredicate, 61, 96, 11, 0, // Skip to: 4372 /* 1460 */ MCD_OPC_CheckField, 4, 1, 0, 89, 11, 0, // Skip to: 4372 /* 1467 */ MCD_OPC_Decode, 239, 14, 205, 2, // Opcode: VNMULD /* 1472 */ MCD_OPC_FilterValue, 29, 79, 11, 0, // Skip to: 4372 /* 1477 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1480 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1532 /* 1485 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1488 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1510 /* 1493 */ MCD_OPC_CheckPredicate, 60, 58, 11, 0, // Skip to: 4372 /* 1498 */ MCD_OPC_CheckField, 4, 1, 0, 51, 11, 0, // Skip to: 4372 /* 1505 */ MCD_OPC_Decode, 150, 10, 191, 2, // Opcode: VFMAH /* 1510 */ MCD_OPC_FilterValue, 1, 41, 11, 0, // Skip to: 4372 /* 1515 */ MCD_OPC_CheckPredicate, 60, 36, 11, 0, // Skip to: 4372 /* 1520 */ MCD_OPC_CheckField, 4, 1, 0, 29, 11, 0, // Skip to: 4372 /* 1527 */ MCD_OPC_Decode, 157, 10, 191, 2, // Opcode: VFMSH /* 1532 */ MCD_OPC_FilterValue, 10, 194, 0, 0, // Skip to: 1731 /* 1537 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1540 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1578 /* 1545 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1548 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1563 /* 1553 */ MCD_OPC_CheckPredicate, 62, 254, 10, 0, // Skip to: 4372 /* 1558 */ MCD_OPC_Decode, 151, 10, 197, 2, // Opcode: VFMAS /* 1563 */ MCD_OPC_FilterValue, 1, 244, 10, 0, // Skip to: 4372 /* 1568 */ MCD_OPC_CheckPredicate, 62, 239, 10, 0, // Skip to: 4372 /* 1573 */ MCD_OPC_Decode, 158, 10, 197, 2, // Opcode: VFMSS /* 1578 */ MCD_OPC_FilterValue, 1, 229, 10, 0, // Skip to: 4372 /* 1583 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 1586 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1615 /* 1591 */ MCD_OPC_CheckPredicate, 27, 216, 10, 0, // Skip to: 4372 /* 1596 */ MCD_OPC_CheckField, 22, 1, 1, 209, 10, 0, // Skip to: 4372 /* 1603 */ MCD_OPC_CheckField, 7, 1, 0, 202, 10, 0, // Skip to: 4372 /* 1610 */ MCD_OPC_Decode, 178, 14, 214, 2, // Opcode: VMSR_FPSID /* 1615 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 1644 /* 1620 */ MCD_OPC_CheckPredicate, 27, 187, 10, 0, // Skip to: 4372 /* 1625 */ MCD_OPC_CheckField, 22, 1, 1, 180, 10, 0, // Skip to: 4372 /* 1632 */ MCD_OPC_CheckField, 7, 1, 0, 173, 10, 0, // Skip to: 4372 /* 1639 */ MCD_OPC_Decode, 174, 14, 214, 2, // Opcode: VMSR /* 1644 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1673 /* 1649 */ MCD_OPC_CheckPredicate, 27, 158, 10, 0, // Skip to: 4372 /* 1654 */ MCD_OPC_CheckField, 22, 1, 1, 151, 10, 0, // Skip to: 4372 /* 1661 */ MCD_OPC_CheckField, 7, 1, 0, 144, 10, 0, // Skip to: 4372 /* 1668 */ MCD_OPC_Decode, 175, 14, 214, 2, // Opcode: VMSR_FPEXC /* 1673 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1702 /* 1678 */ MCD_OPC_CheckPredicate, 27, 129, 10, 0, // Skip to: 4372 /* 1683 */ MCD_OPC_CheckField, 22, 1, 1, 122, 10, 0, // Skip to: 4372 /* 1690 */ MCD_OPC_CheckField, 7, 1, 0, 115, 10, 0, // Skip to: 4372 /* 1697 */ MCD_OPC_Decode, 176, 14, 214, 2, // Opcode: VMSR_FPINST /* 1702 */ MCD_OPC_FilterValue, 10, 105, 10, 0, // Skip to: 4372 /* 1707 */ MCD_OPC_CheckPredicate, 27, 100, 10, 0, // Skip to: 4372 /* 1712 */ MCD_OPC_CheckField, 22, 1, 1, 93, 10, 0, // Skip to: 4372 /* 1719 */ MCD_OPC_CheckField, 7, 1, 0, 86, 10, 0, // Skip to: 4372 /* 1726 */ MCD_OPC_Decode, 177, 14, 214, 2, // Opcode: VMSR_FPINST2 /* 1731 */ MCD_OPC_FilterValue, 11, 76, 10, 0, // Skip to: 4372 /* 1736 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1739 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1761 /* 1744 */ MCD_OPC_CheckPredicate, 63, 63, 10, 0, // Skip to: 4372 /* 1749 */ MCD_OPC_CheckField, 4, 1, 0, 56, 10, 0, // Skip to: 4372 /* 1756 */ MCD_OPC_Decode, 149, 10, 204, 2, // Opcode: VFMAD /* 1761 */ MCD_OPC_FilterValue, 1, 46, 10, 0, // Skip to: 4372 /* 1766 */ MCD_OPC_CheckPredicate, 63, 41, 10, 0, // Skip to: 4372 /* 1771 */ MCD_OPC_CheckField, 4, 1, 0, 34, 10, 0, // Skip to: 4372 /* 1778 */ MCD_OPC_Decode, 156, 10, 204, 2, // Opcode: VFMSD /* 1783 */ MCD_OPC_FilterValue, 3, 24, 10, 0, // Skip to: 4372 /* 1788 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... /* 1791 */ MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1821 /* 1796 */ MCD_OPC_CheckPredicate, 64, 11, 10, 0, // Skip to: 4372 /* 1801 */ MCD_OPC_CheckField, 22, 1, 0, 4, 10, 0, // Skip to: 4372 /* 1808 */ MCD_OPC_CheckField, 0, 16, 128, 20, 252, 9, 0, // Skip to: 4372 /* 1816 */ MCD_OPC_Decode, 154, 13, 210, 2, // Opcode: VLLDM /* 1821 */ MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1889 /* 1826 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1829 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1844 /* 1834 */ MCD_OPC_CheckPredicate, 27, 229, 9, 0, // Skip to: 4372 /* 1839 */ MCD_OPC_Decode, 150, 13, 211, 2, // Opcode: VLDMSIA_UPD /* 1844 */ MCD_OPC_FilterValue, 11, 219, 9, 0, // Skip to: 4372 /* 1849 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 1852 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1867 /* 1857 */ MCD_OPC_CheckPredicate, 27, 206, 9, 0, // Skip to: 4372 /* 1862 */ MCD_OPC_Decode, 146, 13, 212, 2, // Opcode: VLDMDIA_UPD /* 1867 */ MCD_OPC_FilterValue, 1, 196, 9, 0, // Skip to: 4372 /* 1872 */ MCD_OPC_CheckPredicate, 27, 191, 9, 0, // Skip to: 4372 /* 1877 */ MCD_OPC_CheckField, 22, 1, 0, 184, 9, 0, // Skip to: 4372 /* 1884 */ MCD_OPC_Decode, 213, 4, 213, 2, // Opcode: FLDMXIA_UPD /* 1889 */ MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1957 /* 1894 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1897 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1912 /* 1902 */ MCD_OPC_CheckPredicate, 27, 161, 9, 0, // Skip to: 4372 /* 1907 */ MCD_OPC_Decode, 148, 13, 211, 2, // Opcode: VLDMSDB_UPD /* 1912 */ MCD_OPC_FilterValue, 11, 151, 9, 0, // Skip to: 4372 /* 1917 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 1920 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1935 /* 1925 */ MCD_OPC_CheckPredicate, 27, 138, 9, 0, // Skip to: 4372 /* 1930 */ MCD_OPC_Decode, 144, 13, 212, 2, // Opcode: VLDMDDB_UPD /* 1935 */ MCD_OPC_FilterValue, 1, 128, 9, 0, // Skip to: 4372 /* 1940 */ MCD_OPC_CheckPredicate, 27, 123, 9, 0, // Skip to: 4372 /* 1945 */ MCD_OPC_CheckField, 22, 1, 0, 116, 9, 0, // Skip to: 4372 /* 1952 */ MCD_OPC_Decode, 211, 4, 213, 2, // Opcode: FLDMXDB_UPD /* 1957 */ MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 2121 /* 1962 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1965 */ MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 2017 /* 1970 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1973 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1995 /* 1978 */ MCD_OPC_CheckPredicate, 60, 85, 9, 0, // Skip to: 4372 /* 1983 */ MCD_OPC_CheckField, 4, 1, 0, 78, 9, 0, // Skip to: 4372 /* 1990 */ MCD_OPC_Decode, 236, 7, 192, 2, // Opcode: VADDH /* 1995 */ MCD_OPC_FilterValue, 1, 68, 9, 0, // Skip to: 4372 /* 2000 */ MCD_OPC_CheckPredicate, 60, 63, 9, 0, // Skip to: 4372 /* 2005 */ MCD_OPC_CheckField, 4, 1, 0, 56, 9, 0, // Skip to: 4372 /* 2012 */ MCD_OPC_Decode, 208, 20, 192, 2, // Opcode: VSUBH /* 2017 */ MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 2069 /* 2022 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2025 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2047 /* 2030 */ MCD_OPC_CheckPredicate, 27, 33, 9, 0, // Skip to: 4372 /* 2035 */ MCD_OPC_CheckField, 4, 1, 0, 26, 9, 0, // Skip to: 4372 /* 2042 */ MCD_OPC_Decode, 246, 7, 198, 2, // Opcode: VADDS /* 2047 */ MCD_OPC_FilterValue, 1, 16, 9, 0, // Skip to: 4372 /* 2052 */ MCD_OPC_CheckPredicate, 27, 11, 9, 0, // Skip to: 4372 /* 2057 */ MCD_OPC_CheckField, 4, 1, 0, 4, 9, 0, // Skip to: 4372 /* 2064 */ MCD_OPC_Decode, 218, 20, 198, 2, // Opcode: VSUBS /* 2069 */ MCD_OPC_FilterValue, 11, 250, 8, 0, // Skip to: 4372 /* 2074 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2077 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2099 /* 2082 */ MCD_OPC_CheckPredicate, 61, 237, 8, 0, // Skip to: 4372 /* 2087 */ MCD_OPC_CheckField, 4, 1, 0, 230, 8, 0, // Skip to: 4372 /* 2094 */ MCD_OPC_Decode, 235, 7, 205, 2, // Opcode: VADDD /* 2099 */ MCD_OPC_FilterValue, 1, 220, 8, 0, // Skip to: 4372 /* 2104 */ MCD_OPC_CheckPredicate, 61, 215, 8, 0, // Skip to: 4372 /* 2109 */ MCD_OPC_CheckField, 4, 1, 0, 208, 8, 0, // Skip to: 4372 /* 2116 */ MCD_OPC_Decode, 207, 20, 205, 2, // Opcode: VSUBD /* 2121 */ MCD_OPC_FilterValue, 29, 198, 8, 0, // Skip to: 4372 /* 2126 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... /* 2129 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 2151 /* 2134 */ MCD_OPC_CheckPredicate, 60, 185, 8, 0, // Skip to: 4372 /* 2139 */ MCD_OPC_CheckField, 4, 2, 0, 178, 8, 0, // Skip to: 4372 /* 2146 */ MCD_OPC_Decode, 209, 4, 215, 2, // Opcode: FCONSTH /* 2151 */ MCD_OPC_FilterValue, 37, 11, 1, 0, // Skip to: 2423 /* 2156 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 2159 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2181 /* 2164 */ MCD_OPC_CheckPredicate, 60, 155, 8, 0, // Skip to: 4372 /* 2169 */ MCD_OPC_CheckField, 4, 1, 0, 148, 8, 0, // Skip to: 4372 /* 2176 */ MCD_OPC_Decode, 221, 14, 216, 2, // Opcode: VNEGH /* 2181 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2203 /* 2186 */ MCD_OPC_CheckPredicate, 60, 133, 8, 0, // Skip to: 4372 /* 2191 */ MCD_OPC_CheckField, 4, 1, 0, 126, 8, 0, // Skip to: 4372 /* 2198 */ MCD_OPC_Decode, 146, 9, 216, 2, // Opcode: VCMPH /* 2203 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2225 /* 2208 */ MCD_OPC_CheckPredicate, 60, 111, 8, 0, // Skip to: 4372 /* 2213 */ MCD_OPC_CheckField, 0, 6, 0, 104, 8, 0, // Skip to: 4372 /* 2220 */ MCD_OPC_Decode, 149, 9, 217, 2, // Opcode: VCMPZH /* 2225 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2247 /* 2230 */ MCD_OPC_CheckPredicate, 60, 89, 8, 0, // Skip to: 4372 /* 2235 */ MCD_OPC_CheckField, 4, 1, 0, 82, 8, 0, // Skip to: 4372 /* 2242 */ MCD_OPC_Decode, 148, 17, 218, 2, // Opcode: VRINTRH /* 2247 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2269 /* 2252 */ MCD_OPC_CheckPredicate, 60, 67, 8, 0, // Skip to: 4372 /* 2257 */ MCD_OPC_CheckField, 4, 1, 0, 60, 8, 0, // Skip to: 4372 /* 2264 */ MCD_OPC_Decode, 151, 17, 218, 2, // Opcode: VRINTXH /* 2269 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2291 /* 2274 */ MCD_OPC_CheckPredicate, 60, 45, 8, 0, // Skip to: 4372 /* 2279 */ MCD_OPC_CheckField, 4, 1, 0, 38, 8, 0, // Skip to: 4372 /* 2286 */ MCD_OPC_Decode, 167, 21, 219, 2, // Opcode: VUITOH /* 2291 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2313 /* 2296 */ MCD_OPC_CheckPredicate, 60, 23, 8, 0, // Skip to: 4372 /* 2301 */ MCD_OPC_CheckField, 4, 1, 0, 16, 8, 0, // Skip to: 4372 /* 2308 */ MCD_OPC_Decode, 172, 18, 220, 2, // Opcode: VSHTOH /* 2313 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2335 /* 2318 */ MCD_OPC_CheckPredicate, 60, 1, 8, 0, // Skip to: 4372 /* 2323 */ MCD_OPC_CheckField, 4, 1, 0, 250, 7, 0, // Skip to: 4372 /* 2330 */ MCD_OPC_Decode, 164, 21, 220, 2, // Opcode: VUHTOH /* 2335 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2357 /* 2340 */ MCD_OPC_CheckPredicate, 60, 235, 7, 0, // Skip to: 4372 /* 2345 */ MCD_OPC_CheckField, 4, 1, 0, 228, 7, 0, // Skip to: 4372 /* 2352 */ MCD_OPC_Decode, 139, 21, 218, 2, // Opcode: VTOUIRH /* 2357 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2379 /* 2362 */ MCD_OPC_CheckPredicate, 60, 213, 7, 0, // Skip to: 4372 /* 2367 */ MCD_OPC_CheckField, 4, 1, 0, 206, 7, 0, // Skip to: 4372 /* 2374 */ MCD_OPC_Decode, 255, 20, 218, 2, // Opcode: VTOSIRH /* 2379 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2401 /* 2384 */ MCD_OPC_CheckPredicate, 60, 191, 7, 0, // Skip to: 4372 /* 2389 */ MCD_OPC_CheckField, 4, 1, 0, 184, 7, 0, // Skip to: 4372 /* 2396 */ MCD_OPC_Decode, 252, 20, 220, 2, // Opcode: VTOSHH /* 2401 */ MCD_OPC_FilterValue, 15, 174, 7, 0, // Skip to: 4372 /* 2406 */ MCD_OPC_CheckPredicate, 60, 169, 7, 0, // Skip to: 4372 /* 2411 */ MCD_OPC_CheckField, 4, 1, 0, 162, 7, 0, // Skip to: 4372 /* 2418 */ MCD_OPC_Decode, 136, 21, 220, 2, // Opcode: VTOUHH /* 2423 */ MCD_OPC_FilterValue, 39, 11, 1, 0, // Skip to: 2695 /* 2428 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 2431 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2453 /* 2436 */ MCD_OPC_CheckPredicate, 60, 139, 7, 0, // Skip to: 4372 /* 2441 */ MCD_OPC_CheckField, 4, 1, 0, 132, 7, 0, // Skip to: 4372 /* 2448 */ MCD_OPC_Decode, 215, 7, 218, 2, // Opcode: VABSH /* 2453 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2475 /* 2458 */ MCD_OPC_CheckPredicate, 60, 117, 7, 0, // Skip to: 4372 /* 2463 */ MCD_OPC_CheckField, 4, 1, 0, 110, 7, 0, // Skip to: 4372 /* 2470 */ MCD_OPC_Decode, 189, 18, 218, 2, // Opcode: VSQRTH /* 2475 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2497 /* 2480 */ MCD_OPC_CheckPredicate, 60, 95, 7, 0, // Skip to: 4372 /* 2485 */ MCD_OPC_CheckField, 4, 1, 0, 88, 7, 0, // Skip to: 4372 /* 2492 */ MCD_OPC_Decode, 141, 9, 216, 2, // Opcode: VCMPEH /* 2497 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2519 /* 2502 */ MCD_OPC_CheckPredicate, 60, 73, 7, 0, // Skip to: 4372 /* 2507 */ MCD_OPC_CheckField, 0, 6, 0, 66, 7, 0, // Skip to: 4372 /* 2514 */ MCD_OPC_Decode, 144, 9, 217, 2, // Opcode: VCMPEZH /* 2519 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2541 /* 2524 */ MCD_OPC_CheckPredicate, 60, 51, 7, 0, // Skip to: 4372 /* 2529 */ MCD_OPC_CheckField, 4, 1, 0, 44, 7, 0, // Skip to: 4372 /* 2536 */ MCD_OPC_Decode, 158, 17, 218, 2, // Opcode: VRINTZH /* 2541 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2563 /* 2546 */ MCD_OPC_CheckPredicate, 60, 29, 7, 0, // Skip to: 4372 /* 2551 */ MCD_OPC_CheckField, 4, 1, 0, 22, 7, 0, // Skip to: 4372 /* 2558 */ MCD_OPC_Decode, 175, 18, 219, 2, // Opcode: VSITOH /* 2563 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2585 /* 2568 */ MCD_OPC_CheckPredicate, 60, 7, 7, 0, // Skip to: 4372 /* 2573 */ MCD_OPC_CheckField, 4, 1, 0, 0, 7, 0, // Skip to: 4372 /* 2580 */ MCD_OPC_Decode, 186, 18, 220, 2, // Opcode: VSLTOH /* 2585 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2607 /* 2590 */ MCD_OPC_CheckPredicate, 60, 241, 6, 0, // Skip to: 4372 /* 2595 */ MCD_OPC_CheckField, 4, 1, 0, 234, 6, 0, // Skip to: 4372 /* 2602 */ MCD_OPC_Decode, 170, 21, 220, 2, // Opcode: VULTOH /* 2607 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2629 /* 2612 */ MCD_OPC_CheckPredicate, 60, 219, 6, 0, // Skip to: 4372 /* 2617 */ MCD_OPC_CheckField, 4, 1, 0, 212, 6, 0, // Skip to: 4372 /* 2624 */ MCD_OPC_Decode, 142, 21, 221, 2, // Opcode: VTOUIZH /* 2629 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2651 /* 2634 */ MCD_OPC_CheckPredicate, 60, 197, 6, 0, // Skip to: 4372 /* 2639 */ MCD_OPC_CheckField, 4, 1, 0, 190, 6, 0, // Skip to: 4372 /* 2646 */ MCD_OPC_Decode, 130, 21, 221, 2, // Opcode: VTOSIZH /* 2651 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2673 /* 2656 */ MCD_OPC_CheckPredicate, 60, 175, 6, 0, // Skip to: 4372 /* 2661 */ MCD_OPC_CheckField, 4, 1, 0, 168, 6, 0, // Skip to: 4372 /* 2668 */ MCD_OPC_Decode, 133, 21, 220, 2, // Opcode: VTOSLH /* 2673 */ MCD_OPC_FilterValue, 15, 158, 6, 0, // Skip to: 4372 /* 2678 */ MCD_OPC_CheckPredicate, 60, 153, 6, 0, // Skip to: 4372 /* 2683 */ MCD_OPC_CheckField, 4, 1, 0, 146, 6, 0, // Skip to: 4372 /* 2690 */ MCD_OPC_Decode, 145, 21, 220, 2, // Opcode: VTOULH /* 2695 */ MCD_OPC_FilterValue, 40, 20, 1, 0, // Skip to: 2976 /* 2700 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 2703 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2718 /* 2708 */ MCD_OPC_CheckPredicate, 65, 123, 6, 0, // Skip to: 4372 /* 2713 */ MCD_OPC_Decode, 210, 4, 222, 2, // Opcode: FCONSTS /* 2718 */ MCD_OPC_FilterValue, 1, 113, 6, 0, // Skip to: 4372 /* 2723 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 2726 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2755 /* 2731 */ MCD_OPC_CheckPredicate, 27, 100, 6, 0, // Skip to: 4372 /* 2736 */ MCD_OPC_CheckField, 22, 1, 1, 93, 6, 0, // Skip to: 4372 /* 2743 */ MCD_OPC_CheckField, 0, 4, 0, 86, 6, 0, // Skip to: 4372 /* 2750 */ MCD_OPC_Decode, 170, 14, 214, 2, // Opcode: VMRS_FPSID /* 2755 */ MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 2802 /* 2760 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... /* 2763 */ MCD_OPC_FilterValue, 0, 68, 6, 0, // Skip to: 4372 /* 2768 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... /* 2771 */ MCD_OPC_FilterValue, 1, 60, 6, 0, // Skip to: 4372 /* 2776 */ MCD_OPC_CheckPredicate, 27, 11, 0, 0, // Skip to: 2792 /* 2781 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 2792 /* 2788 */ MCD_OPC_Decode, 214, 4, 29, // Opcode: FMSTAT /* 2792 */ MCD_OPC_CheckPredicate, 27, 39, 6, 0, // Skip to: 4372 /* 2797 */ MCD_OPC_Decode, 166, 14, 214, 2, // Opcode: VMRS /* 2802 */ MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 2831 /* 2807 */ MCD_OPC_CheckPredicate, 66, 24, 6, 0, // Skip to: 4372 /* 2812 */ MCD_OPC_CheckField, 22, 1, 1, 17, 6, 0, // Skip to: 4372 /* 2819 */ MCD_OPC_CheckField, 0, 4, 0, 10, 6, 0, // Skip to: 4372 /* 2826 */ MCD_OPC_Decode, 173, 14, 214, 2, // Opcode: VMRS_MVFR2 /* 2831 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 2860 /* 2836 */ MCD_OPC_CheckPredicate, 27, 251, 5, 0, // Skip to: 4372 /* 2841 */ MCD_OPC_CheckField, 22, 1, 1, 244, 5, 0, // Skip to: 4372 /* 2848 */ MCD_OPC_CheckField, 0, 4, 0, 237, 5, 0, // Skip to: 4372 /* 2855 */ MCD_OPC_Decode, 172, 14, 214, 2, // Opcode: VMRS_MVFR1 /* 2860 */ MCD_OPC_FilterValue, 7, 24, 0, 0, // Skip to: 2889 /* 2865 */ MCD_OPC_CheckPredicate, 27, 222, 5, 0, // Skip to: 4372 /* 2870 */ MCD_OPC_CheckField, 22, 1, 1, 215, 5, 0, // Skip to: 4372 /* 2877 */ MCD_OPC_CheckField, 0, 4, 0, 208, 5, 0, // Skip to: 4372 /* 2884 */ MCD_OPC_Decode, 171, 14, 214, 2, // Opcode: VMRS_MVFR0 /* 2889 */ MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 2918 /* 2894 */ MCD_OPC_CheckPredicate, 27, 193, 5, 0, // Skip to: 4372 /* 2899 */ MCD_OPC_CheckField, 22, 1, 1, 186, 5, 0, // Skip to: 4372 /* 2906 */ MCD_OPC_CheckField, 0, 4, 0, 179, 5, 0, // Skip to: 4372 /* 2913 */ MCD_OPC_Decode, 167, 14, 214, 2, // Opcode: VMRS_FPEXC /* 2918 */ MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 2947 /* 2923 */ MCD_OPC_CheckPredicate, 27, 164, 5, 0, // Skip to: 4372 /* 2928 */ MCD_OPC_CheckField, 22, 1, 1, 157, 5, 0, // Skip to: 4372 /* 2935 */ MCD_OPC_CheckField, 0, 4, 0, 150, 5, 0, // Skip to: 4372 /* 2942 */ MCD_OPC_Decode, 168, 14, 214, 2, // Opcode: VMRS_FPINST /* 2947 */ MCD_OPC_FilterValue, 10, 140, 5, 0, // Skip to: 4372 /* 2952 */ MCD_OPC_CheckPredicate, 27, 135, 5, 0, // Skip to: 4372 /* 2957 */ MCD_OPC_CheckField, 22, 1, 1, 128, 5, 0, // Skip to: 4372 /* 2964 */ MCD_OPC_CheckField, 0, 4, 0, 121, 5, 0, // Skip to: 4372 /* 2971 */ MCD_OPC_Decode, 169, 14, 214, 2, // Opcode: VMRS_FPINST2 /* 2976 */ MCD_OPC_FilterValue, 41, 77, 1, 0, // Skip to: 3314 /* 2981 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 2984 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3006 /* 2989 */ MCD_OPC_CheckPredicate, 27, 98, 5, 0, // Skip to: 4372 /* 2994 */ MCD_OPC_CheckField, 4, 1, 0, 91, 5, 0, // Skip to: 4372 /* 3001 */ MCD_OPC_Decode, 153, 14, 218, 2, // Opcode: VMOVS /* 3006 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3028 /* 3011 */ MCD_OPC_CheckPredicate, 27, 76, 5, 0, // Skip to: 4372 /* 3016 */ MCD_OPC_CheckField, 4, 1, 0, 69, 5, 0, // Skip to: 4372 /* 3023 */ MCD_OPC_Decode, 222, 14, 218, 2, // Opcode: VNEGS /* 3028 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3050 /* 3033 */ MCD_OPC_CheckPredicate, 67, 54, 5, 0, // Skip to: 4372 /* 3038 */ MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 4372 /* 3045 */ MCD_OPC_Decode, 169, 9, 218, 2, // Opcode: VCVTBHS /* 3050 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3072 /* 3055 */ MCD_OPC_CheckPredicate, 67, 32, 5, 0, // Skip to: 4372 /* 3060 */ MCD_OPC_CheckField, 4, 1, 0, 25, 5, 0, // Skip to: 4372 /* 3067 */ MCD_OPC_Decode, 170, 9, 218, 2, // Opcode: VCVTBSH /* 3072 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3094 /* 3077 */ MCD_OPC_CheckPredicate, 27, 10, 5, 0, // Skip to: 4372 /* 3082 */ MCD_OPC_CheckField, 4, 1, 0, 3, 5, 0, // Skip to: 4372 /* 3089 */ MCD_OPC_Decode, 147, 9, 218, 2, // Opcode: VCMPS /* 3094 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3116 /* 3099 */ MCD_OPC_CheckPredicate, 27, 244, 4, 0, // Skip to: 4372 /* 3104 */ MCD_OPC_CheckField, 0, 6, 0, 237, 4, 0, // Skip to: 4372 /* 3111 */ MCD_OPC_Decode, 150, 9, 223, 2, // Opcode: VCMPZS /* 3116 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3138 /* 3121 */ MCD_OPC_CheckPredicate, 66, 222, 4, 0, // Skip to: 4372 /* 3126 */ MCD_OPC_CheckField, 4, 1, 0, 215, 4, 0, // Skip to: 4372 /* 3133 */ MCD_OPC_Decode, 149, 17, 218, 2, // Opcode: VRINTRS /* 3138 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3160 /* 3143 */ MCD_OPC_CheckPredicate, 66, 200, 4, 0, // Skip to: 4372 /* 3148 */ MCD_OPC_CheckField, 4, 1, 0, 193, 4, 0, // Skip to: 4372 /* 3155 */ MCD_OPC_Decode, 156, 17, 218, 2, // Opcode: VRINTXS /* 3160 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3182 /* 3165 */ MCD_OPC_CheckPredicate, 27, 178, 4, 0, // Skip to: 4372 /* 3170 */ MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 4372 /* 3177 */ MCD_OPC_Decode, 168, 21, 218, 2, // Opcode: VUITOS /* 3182 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3204 /* 3187 */ MCD_OPC_CheckPredicate, 27, 156, 4, 0, // Skip to: 4372 /* 3192 */ MCD_OPC_CheckField, 4, 1, 0, 149, 4, 0, // Skip to: 4372 /* 3199 */ MCD_OPC_Decode, 173, 18, 220, 2, // Opcode: VSHTOS /* 3204 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3226 /* 3209 */ MCD_OPC_CheckPredicate, 27, 134, 4, 0, // Skip to: 4372 /* 3214 */ MCD_OPC_CheckField, 4, 1, 0, 127, 4, 0, // Skip to: 4372 /* 3221 */ MCD_OPC_Decode, 165, 21, 220, 2, // Opcode: VUHTOS /* 3226 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3248 /* 3231 */ MCD_OPC_CheckPredicate, 27, 112, 4, 0, // Skip to: 4372 /* 3236 */ MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 4372 /* 3243 */ MCD_OPC_Decode, 140, 21, 218, 2, // Opcode: VTOUIRS /* 3248 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3270 /* 3253 */ MCD_OPC_CheckPredicate, 27, 90, 4, 0, // Skip to: 4372 /* 3258 */ MCD_OPC_CheckField, 4, 1, 0, 83, 4, 0, // Skip to: 4372 /* 3265 */ MCD_OPC_Decode, 128, 21, 218, 2, // Opcode: VTOSIRS /* 3270 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3292 /* 3275 */ MCD_OPC_CheckPredicate, 27, 68, 4, 0, // Skip to: 4372 /* 3280 */ MCD_OPC_CheckField, 4, 1, 0, 61, 4, 0, // Skip to: 4372 /* 3287 */ MCD_OPC_Decode, 253, 20, 220, 2, // Opcode: VTOSHS /* 3292 */ MCD_OPC_FilterValue, 15, 51, 4, 0, // Skip to: 4372 /* 3297 */ MCD_OPC_CheckPredicate, 27, 46, 4, 0, // Skip to: 4372 /* 3302 */ MCD_OPC_CheckField, 4, 1, 0, 39, 4, 0, // Skip to: 4372 /* 3309 */ MCD_OPC_Decode, 137, 21, 220, 2, // Opcode: VTOUHS /* 3314 */ MCD_OPC_FilterValue, 43, 77, 1, 0, // Skip to: 3652 /* 3319 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 3322 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3344 /* 3327 */ MCD_OPC_CheckPredicate, 27, 16, 4, 0, // Skip to: 4372 /* 3332 */ MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 4372 /* 3339 */ MCD_OPC_Decode, 216, 7, 218, 2, // Opcode: VABSS /* 3344 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3366 /* 3349 */ MCD_OPC_CheckPredicate, 27, 250, 3, 0, // Skip to: 4372 /* 3354 */ MCD_OPC_CheckField, 4, 1, 0, 243, 3, 0, // Skip to: 4372 /* 3361 */ MCD_OPC_Decode, 190, 18, 218, 2, // Opcode: VSQRTS /* 3366 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3388 /* 3371 */ MCD_OPC_CheckPredicate, 67, 228, 3, 0, // Skip to: 4372 /* 3376 */ MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 4372 /* 3383 */ MCD_OPC_Decode, 217, 9, 218, 2, // Opcode: VCVTTHS /* 3388 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3410 /* 3393 */ MCD_OPC_CheckPredicate, 67, 206, 3, 0, // Skip to: 4372 /* 3398 */ MCD_OPC_CheckField, 4, 1, 0, 199, 3, 0, // Skip to: 4372 /* 3405 */ MCD_OPC_Decode, 218, 9, 218, 2, // Opcode: VCVTTSH /* 3410 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3432 /* 3415 */ MCD_OPC_CheckPredicate, 27, 184, 3, 0, // Skip to: 4372 /* 3420 */ MCD_OPC_CheckField, 4, 1, 0, 177, 3, 0, // Skip to: 4372 /* 3427 */ MCD_OPC_Decode, 142, 9, 218, 2, // Opcode: VCMPES /* 3432 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3454 /* 3437 */ MCD_OPC_CheckPredicate, 27, 162, 3, 0, // Skip to: 4372 /* 3442 */ MCD_OPC_CheckField, 0, 6, 0, 155, 3, 0, // Skip to: 4372 /* 3449 */ MCD_OPC_Decode, 145, 9, 223, 2, // Opcode: VCMPEZS /* 3454 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3476 /* 3459 */ MCD_OPC_CheckPredicate, 66, 140, 3, 0, // Skip to: 4372 /* 3464 */ MCD_OPC_CheckField, 4, 1, 0, 133, 3, 0, // Skip to: 4372 /* 3471 */ MCD_OPC_Decode, 163, 17, 218, 2, // Opcode: VRINTZS /* 3476 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3498 /* 3481 */ MCD_OPC_CheckPredicate, 61, 118, 3, 0, // Skip to: 4372 /* 3486 */ MCD_OPC_CheckField, 4, 1, 0, 111, 3, 0, // Skip to: 4372 /* 3493 */ MCD_OPC_Decode, 171, 9, 224, 2, // Opcode: VCVTDS /* 3498 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3520 /* 3503 */ MCD_OPC_CheckPredicate, 27, 96, 3, 0, // Skip to: 4372 /* 3508 */ MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 4372 /* 3515 */ MCD_OPC_Decode, 176, 18, 218, 2, // Opcode: VSITOS /* 3520 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3542 /* 3525 */ MCD_OPC_CheckPredicate, 27, 74, 3, 0, // Skip to: 4372 /* 3530 */ MCD_OPC_CheckField, 4, 1, 0, 67, 3, 0, // Skip to: 4372 /* 3537 */ MCD_OPC_Decode, 187, 18, 220, 2, // Opcode: VSLTOS /* 3542 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3564 /* 3547 */ MCD_OPC_CheckPredicate, 27, 52, 3, 0, // Skip to: 4372 /* 3552 */ MCD_OPC_CheckField, 4, 1, 0, 45, 3, 0, // Skip to: 4372 /* 3559 */ MCD_OPC_Decode, 171, 21, 220, 2, // Opcode: VULTOS /* 3564 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3586 /* 3569 */ MCD_OPC_CheckPredicate, 27, 30, 3, 0, // Skip to: 4372 /* 3574 */ MCD_OPC_CheckField, 4, 1, 0, 23, 3, 0, // Skip to: 4372 /* 3581 */ MCD_OPC_Decode, 143, 21, 218, 2, // Opcode: VTOUIZS /* 3586 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3608 /* 3591 */ MCD_OPC_CheckPredicate, 27, 8, 3, 0, // Skip to: 4372 /* 3596 */ MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 4372 /* 3603 */ MCD_OPC_Decode, 131, 21, 218, 2, // Opcode: VTOSIZS /* 3608 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3630 /* 3613 */ MCD_OPC_CheckPredicate, 27, 242, 2, 0, // Skip to: 4372 /* 3618 */ MCD_OPC_CheckField, 4, 1, 0, 235, 2, 0, // Skip to: 4372 /* 3625 */ MCD_OPC_Decode, 134, 21, 220, 2, // Opcode: VTOSLS /* 3630 */ MCD_OPC_FilterValue, 15, 225, 2, 0, // Skip to: 4372 /* 3635 */ MCD_OPC_CheckPredicate, 27, 220, 2, 0, // Skip to: 4372 /* 3640 */ MCD_OPC_CheckField, 4, 1, 0, 213, 2, 0, // Skip to: 4372 /* 3647 */ MCD_OPC_Decode, 146, 21, 220, 2, // Opcode: VTOULS /* 3652 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 3674 /* 3657 */ MCD_OPC_CheckPredicate, 68, 198, 2, 0, // Skip to: 4372 /* 3662 */ MCD_OPC_CheckField, 4, 2, 0, 191, 2, 0, // Skip to: 4372 /* 3669 */ MCD_OPC_Decode, 208, 4, 225, 2, // Opcode: FCONSTD /* 3674 */ MCD_OPC_FilterValue, 45, 77, 1, 0, // Skip to: 4012 /* 3679 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 3682 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3704 /* 3687 */ MCD_OPC_CheckPredicate, 61, 168, 2, 0, // Skip to: 4372 /* 3692 */ MCD_OPC_CheckField, 4, 1, 0, 161, 2, 0, // Skip to: 4372 /* 3699 */ MCD_OPC_Decode, 136, 14, 226, 2, // Opcode: VMOVD /* 3704 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3726 /* 3709 */ MCD_OPC_CheckPredicate, 61, 146, 2, 0, // Skip to: 4372 /* 3714 */ MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 4372 /* 3721 */ MCD_OPC_Decode, 220, 14, 226, 2, // Opcode: VNEGD /* 3726 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3748 /* 3731 */ MCD_OPC_CheckPredicate, 69, 124, 2, 0, // Skip to: 4372 /* 3736 */ MCD_OPC_CheckField, 4, 1, 0, 117, 2, 0, // Skip to: 4372 /* 3743 */ MCD_OPC_Decode, 168, 9, 224, 2, // Opcode: VCVTBHD /* 3748 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3770 /* 3753 */ MCD_OPC_CheckPredicate, 69, 102, 2, 0, // Skip to: 4372 /* 3758 */ MCD_OPC_CheckField, 4, 1, 0, 95, 2, 0, // Skip to: 4372 /* 3765 */ MCD_OPC_Decode, 167, 9, 227, 2, // Opcode: VCVTBDH /* 3770 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3792 /* 3775 */ MCD_OPC_CheckPredicate, 61, 80, 2, 0, // Skip to: 4372 /* 3780 */ MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 4372 /* 3787 */ MCD_OPC_Decode, 139, 9, 226, 2, // Opcode: VCMPD /* 3792 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3814 /* 3797 */ MCD_OPC_CheckPredicate, 61, 58, 2, 0, // Skip to: 4372 /* 3802 */ MCD_OPC_CheckField, 0, 6, 0, 51, 2, 0, // Skip to: 4372 /* 3809 */ MCD_OPC_Decode, 148, 9, 228, 2, // Opcode: VCMPZD /* 3814 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3836 /* 3819 */ MCD_OPC_CheckPredicate, 69, 36, 2, 0, // Skip to: 4372 /* 3824 */ MCD_OPC_CheckField, 4, 1, 0, 29, 2, 0, // Skip to: 4372 /* 3831 */ MCD_OPC_Decode, 147, 17, 226, 2, // Opcode: VRINTRD /* 3836 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3858 /* 3841 */ MCD_OPC_CheckPredicate, 69, 14, 2, 0, // Skip to: 4372 /* 3846 */ MCD_OPC_CheckField, 4, 1, 0, 7, 2, 0, // Skip to: 4372 /* 3853 */ MCD_OPC_Decode, 150, 17, 226, 2, // Opcode: VRINTXD /* 3858 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3880 /* 3863 */ MCD_OPC_CheckPredicate, 61, 248, 1, 0, // Skip to: 4372 /* 3868 */ MCD_OPC_CheckField, 4, 1, 0, 241, 1, 0, // Skip to: 4372 /* 3875 */ MCD_OPC_Decode, 166, 21, 224, 2, // Opcode: VUITOD /* 3880 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3902 /* 3885 */ MCD_OPC_CheckPredicate, 61, 226, 1, 0, // Skip to: 4372 /* 3890 */ MCD_OPC_CheckField, 4, 1, 0, 219, 1, 0, // Skip to: 4372 /* 3897 */ MCD_OPC_Decode, 171, 18, 229, 2, // Opcode: VSHTOD /* 3902 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3924 /* 3907 */ MCD_OPC_CheckPredicate, 61, 204, 1, 0, // Skip to: 4372 /* 3912 */ MCD_OPC_CheckField, 4, 1, 0, 197, 1, 0, // Skip to: 4372 /* 3919 */ MCD_OPC_Decode, 163, 21, 229, 2, // Opcode: VUHTOD /* 3924 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3946 /* 3929 */ MCD_OPC_CheckPredicate, 61, 182, 1, 0, // Skip to: 4372 /* 3934 */ MCD_OPC_CheckField, 4, 1, 0, 175, 1, 0, // Skip to: 4372 /* 3941 */ MCD_OPC_Decode, 138, 21, 227, 2, // Opcode: VTOUIRD /* 3946 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3968 /* 3951 */ MCD_OPC_CheckPredicate, 61, 160, 1, 0, // Skip to: 4372 /* 3956 */ MCD_OPC_CheckField, 4, 1, 0, 153, 1, 0, // Skip to: 4372 /* 3963 */ MCD_OPC_Decode, 254, 20, 227, 2, // Opcode: VTOSIRD /* 3968 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3990 /* 3973 */ MCD_OPC_CheckPredicate, 61, 138, 1, 0, // Skip to: 4372 /* 3978 */ MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 4372 /* 3985 */ MCD_OPC_Decode, 251, 20, 229, 2, // Opcode: VTOSHD /* 3990 */ MCD_OPC_FilterValue, 15, 121, 1, 0, // Skip to: 4372 /* 3995 */ MCD_OPC_CheckPredicate, 61, 116, 1, 0, // Skip to: 4372 /* 4000 */ MCD_OPC_CheckField, 4, 1, 0, 109, 1, 0, // Skip to: 4372 /* 4007 */ MCD_OPC_Decode, 135, 21, 229, 2, // Opcode: VTOUHD /* 4012 */ MCD_OPC_FilterValue, 47, 99, 1, 0, // Skip to: 4372 /* 4017 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 4020 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4042 /* 4025 */ MCD_OPC_CheckPredicate, 61, 86, 1, 0, // Skip to: 4372 /* 4030 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 4372 /* 4037 */ MCD_OPC_Decode, 214, 7, 226, 2, // Opcode: VABSD /* 4042 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4064 /* 4047 */ MCD_OPC_CheckPredicate, 61, 64, 1, 0, // Skip to: 4372 /* 4052 */ MCD_OPC_CheckField, 4, 1, 0, 57, 1, 0, // Skip to: 4372 /* 4059 */ MCD_OPC_Decode, 188, 18, 226, 2, // Opcode: VSQRTD /* 4064 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4086 /* 4069 */ MCD_OPC_CheckPredicate, 69, 42, 1, 0, // Skip to: 4372 /* 4074 */ MCD_OPC_CheckField, 4, 1, 0, 35, 1, 0, // Skip to: 4372 /* 4081 */ MCD_OPC_Decode, 216, 9, 224, 2, // Opcode: VCVTTHD /* 4086 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4108 /* 4091 */ MCD_OPC_CheckPredicate, 69, 20, 1, 0, // Skip to: 4372 /* 4096 */ MCD_OPC_CheckField, 4, 1, 0, 13, 1, 0, // Skip to: 4372 /* 4103 */ MCD_OPC_Decode, 215, 9, 227, 2, // Opcode: VCVTTDH /* 4108 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4130 /* 4113 */ MCD_OPC_CheckPredicate, 61, 254, 0, 0, // Skip to: 4372 /* 4118 */ MCD_OPC_CheckField, 4, 1, 0, 247, 0, 0, // Skip to: 4372 /* 4125 */ MCD_OPC_Decode, 140, 9, 226, 2, // Opcode: VCMPED /* 4130 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4152 /* 4135 */ MCD_OPC_CheckPredicate, 61, 232, 0, 0, // Skip to: 4372 /* 4140 */ MCD_OPC_CheckField, 0, 6, 0, 225, 0, 0, // Skip to: 4372 /* 4147 */ MCD_OPC_Decode, 143, 9, 228, 2, // Opcode: VCMPEZD /* 4152 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4174 /* 4157 */ MCD_OPC_CheckPredicate, 69, 210, 0, 0, // Skip to: 4372 /* 4162 */ MCD_OPC_CheckField, 4, 1, 0, 203, 0, 0, // Skip to: 4372 /* 4169 */ MCD_OPC_Decode, 157, 17, 226, 2, // Opcode: VRINTZD /* 4174 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4196 /* 4179 */ MCD_OPC_CheckPredicate, 61, 188, 0, 0, // Skip to: 4372 /* 4184 */ MCD_OPC_CheckField, 4, 1, 0, 181, 0, 0, // Skip to: 4372 /* 4191 */ MCD_OPC_Decode, 214, 9, 227, 2, // Opcode: VCVTSD /* 4196 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4218 /* 4201 */ MCD_OPC_CheckPredicate, 61, 166, 0, 0, // Skip to: 4372 /* 4206 */ MCD_OPC_CheckField, 4, 1, 0, 159, 0, 0, // Skip to: 4372 /* 4213 */ MCD_OPC_Decode, 174, 18, 224, 2, // Opcode: VSITOD /* 4218 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4240 /* 4223 */ MCD_OPC_CheckPredicate, 70, 144, 0, 0, // Skip to: 4372 /* 4228 */ MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 4372 /* 4235 */ MCD_OPC_Decode, 199, 10, 227, 2, // Opcode: VJCVT /* 4240 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4262 /* 4245 */ MCD_OPC_CheckPredicate, 61, 122, 0, 0, // Skip to: 4372 /* 4250 */ MCD_OPC_CheckField, 4, 1, 0, 115, 0, 0, // Skip to: 4372 /* 4257 */ MCD_OPC_Decode, 185, 18, 229, 2, // Opcode: VSLTOD /* 4262 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4284 /* 4267 */ MCD_OPC_CheckPredicate, 61, 100, 0, 0, // Skip to: 4372 /* 4272 */ MCD_OPC_CheckField, 4, 1, 0, 93, 0, 0, // Skip to: 4372 /* 4279 */ MCD_OPC_Decode, 169, 21, 229, 2, // Opcode: VULTOD /* 4284 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4306 /* 4289 */ MCD_OPC_CheckPredicate, 61, 78, 0, 0, // Skip to: 4372 /* 4294 */ MCD_OPC_CheckField, 4, 1, 0, 71, 0, 0, // Skip to: 4372 /* 4301 */ MCD_OPC_Decode, 141, 21, 227, 2, // Opcode: VTOUIZD /* 4306 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4328 /* 4311 */ MCD_OPC_CheckPredicate, 61, 56, 0, 0, // Skip to: 4372 /* 4316 */ MCD_OPC_CheckField, 4, 1, 0, 49, 0, 0, // Skip to: 4372 /* 4323 */ MCD_OPC_Decode, 129, 21, 227, 2, // Opcode: VTOSIZD /* 4328 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4350 /* 4333 */ MCD_OPC_CheckPredicate, 61, 34, 0, 0, // Skip to: 4372 /* 4338 */ MCD_OPC_CheckField, 4, 1, 0, 27, 0, 0, // Skip to: 4372 /* 4345 */ MCD_OPC_Decode, 132, 21, 229, 2, // Opcode: VTOSLD /* 4350 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 4372 /* 4355 */ MCD_OPC_CheckPredicate, 61, 12, 0, 0, // Skip to: 4372 /* 4360 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 4372 /* 4367 */ MCD_OPC_Decode, 144, 21, 229, 2, // Opcode: VTOULD /* 4372 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableVFPV832[] = { /* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 3 */ MCD_OPC_FilterValue, 8, 87, 1, 0, // Skip to: 351 /* 8 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 11 */ MCD_OPC_FilterValue, 0, 165, 0, 0, // Skip to: 181 /* 16 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 19 */ MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 129 /* 24 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 27 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 56 /* 32 */ MCD_OPC_CheckPredicate, 71, 220, 9, 0, // Skip to: 2561 /* 37 */ MCD_OPC_CheckField, 23, 1, 1, 213, 9, 0, // Skip to: 2561 /* 44 */ MCD_OPC_CheckField, 4, 1, 0, 206, 9, 0, // Skip to: 2561 /* 51 */ MCD_OPC_Decode, 152, 8, 230, 2, // Opcode: VCADDv4f16 /* 56 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 85 /* 61 */ MCD_OPC_CheckPredicate, 72, 191, 9, 0, // Skip to: 2561 /* 66 */ MCD_OPC_CheckField, 23, 1, 1, 184, 9, 0, // Skip to: 2561 /* 73 */ MCD_OPC_CheckField, 4, 1, 0, 177, 9, 0, // Skip to: 2561 /* 80 */ MCD_OPC_Decode, 151, 8, 230, 2, // Opcode: VCADDv2f32 /* 85 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 107 /* 90 */ MCD_OPC_CheckPredicate, 71, 162, 9, 0, // Skip to: 2561 /* 95 */ MCD_OPC_CheckField, 4, 1, 0, 155, 9, 0, // Skip to: 2561 /* 102 */ MCD_OPC_Decode, 133, 9, 231, 2, // Opcode: VCMLAv4f16 /* 107 */ MCD_OPC_FilterValue, 3, 145, 9, 0, // Skip to: 2561 /* 112 */ MCD_OPC_CheckPredicate, 72, 140, 9, 0, // Skip to: 2561 /* 117 */ MCD_OPC_CheckField, 4, 1, 0, 133, 9, 0, // Skip to: 2561 /* 124 */ MCD_OPC_Decode, 131, 9, 231, 2, // Opcode: VCMLAv2f32 /* 129 */ MCD_OPC_FilterValue, 127, 123, 9, 0, // Skip to: 2561 /* 134 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 137 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 159 /* 142 */ MCD_OPC_CheckPredicate, 71, 110, 9, 0, // Skip to: 2561 /* 147 */ MCD_OPC_CheckField, 4, 1, 0, 103, 9, 0, // Skip to: 2561 /* 154 */ MCD_OPC_Decode, 134, 9, 232, 2, // Opcode: VCMLAv4f16_indexed /* 159 */ MCD_OPC_FilterValue, 1, 93, 9, 0, // Skip to: 2561 /* 164 */ MCD_OPC_CheckPredicate, 72, 88, 9, 0, // Skip to: 2561 /* 169 */ MCD_OPC_CheckField, 4, 1, 0, 81, 9, 0, // Skip to: 2561 /* 176 */ MCD_OPC_Decode, 132, 9, 233, 2, // Opcode: VCMLAv2f32_indexed /* 181 */ MCD_OPC_FilterValue, 1, 71, 9, 0, // Skip to: 2561 /* 186 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 189 */ MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 299 /* 194 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 197 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 226 /* 202 */ MCD_OPC_CheckPredicate, 71, 50, 9, 0, // Skip to: 2561 /* 207 */ MCD_OPC_CheckField, 23, 1, 1, 43, 9, 0, // Skip to: 2561 /* 214 */ MCD_OPC_CheckField, 4, 1, 0, 36, 9, 0, // Skip to: 2561 /* 221 */ MCD_OPC_Decode, 154, 8, 234, 2, // Opcode: VCADDv8f16 /* 226 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 255 /* 231 */ MCD_OPC_CheckPredicate, 72, 21, 9, 0, // Skip to: 2561 /* 236 */ MCD_OPC_CheckField, 23, 1, 1, 14, 9, 0, // Skip to: 2561 /* 243 */ MCD_OPC_CheckField, 4, 1, 0, 7, 9, 0, // Skip to: 2561 /* 250 */ MCD_OPC_Decode, 153, 8, 234, 2, // Opcode: VCADDv4f32 /* 255 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 277 /* 260 */ MCD_OPC_CheckPredicate, 71, 248, 8, 0, // Skip to: 2561 /* 265 */ MCD_OPC_CheckField, 4, 1, 0, 241, 8, 0, // Skip to: 2561 /* 272 */ MCD_OPC_Decode, 137, 9, 235, 2, // Opcode: VCMLAv8f16 /* 277 */ MCD_OPC_FilterValue, 3, 231, 8, 0, // Skip to: 2561 /* 282 */ MCD_OPC_CheckPredicate, 72, 226, 8, 0, // Skip to: 2561 /* 287 */ MCD_OPC_CheckField, 4, 1, 0, 219, 8, 0, // Skip to: 2561 /* 294 */ MCD_OPC_Decode, 135, 9, 235, 2, // Opcode: VCMLAv4f32 /* 299 */ MCD_OPC_FilterValue, 127, 209, 8, 0, // Skip to: 2561 /* 304 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... /* 307 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 329 /* 312 */ MCD_OPC_CheckPredicate, 71, 196, 8, 0, // Skip to: 2561 /* 317 */ MCD_OPC_CheckField, 4, 1, 0, 189, 8, 0, // Skip to: 2561 /* 324 */ MCD_OPC_Decode, 138, 9, 236, 2, // Opcode: VCMLAv8f16_indexed /* 329 */ MCD_OPC_FilterValue, 1, 179, 8, 0, // Skip to: 2561 /* 334 */ MCD_OPC_CheckPredicate, 72, 174, 8, 0, // Skip to: 2561 /* 339 */ MCD_OPC_CheckField, 4, 1, 0, 167, 8, 0, // Skip to: 2561 /* 346 */ MCD_OPC_Decode, 136, 9, 233, 2, // Opcode: VCMLAv4f32_indexed /* 351 */ MCD_OPC_FilterValue, 9, 123, 2, 0, // Skip to: 991 /* 356 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 359 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 451 /* 364 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 367 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 421 /* 372 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 375 */ MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 398 /* 381 */ MCD_OPC_CheckPredicate, 60, 127, 8, 0, // Skip to: 2561 /* 386 */ MCD_OPC_CheckField, 4, 1, 0, 120, 8, 0, // Skip to: 2561 /* 393 */ MCD_OPC_Decode, 233, 17, 237, 2, // Opcode: VSELEQH /* 398 */ MCD_OPC_FilterValue, 253, 3, 109, 8, 0, // Skip to: 2561 /* 404 */ MCD_OPC_CheckPredicate, 60, 104, 8, 0, // Skip to: 2561 /* 409 */ MCD_OPC_CheckField, 4, 1, 0, 97, 8, 0, // Skip to: 2561 /* 416 */ MCD_OPC_Decode, 157, 13, 237, 2, // Opcode: VMAXNMH /* 421 */ MCD_OPC_FilterValue, 1, 87, 8, 0, // Skip to: 2561 /* 426 */ MCD_OPC_CheckPredicate, 60, 82, 8, 0, // Skip to: 2561 /* 431 */ MCD_OPC_CheckField, 23, 9, 253, 3, 74, 8, 0, // Skip to: 2561 /* 439 */ MCD_OPC_CheckField, 4, 1, 0, 67, 8, 0, // Skip to: 2561 /* 446 */ MCD_OPC_Decode, 180, 13, 237, 2, // Opcode: VMINNMH /* 451 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 488 /* 456 */ MCD_OPC_CheckPredicate, 60, 52, 8, 0, // Skip to: 2561 /* 461 */ MCD_OPC_CheckField, 23, 9, 252, 3, 44, 8, 0, // Skip to: 2561 /* 469 */ MCD_OPC_CheckField, 6, 1, 0, 37, 8, 0, // Skip to: 2561 /* 476 */ MCD_OPC_CheckField, 4, 1, 0, 30, 8, 0, // Skip to: 2561 /* 483 */ MCD_OPC_Decode, 242, 17, 237, 2, // Opcode: VSELVSH /* 488 */ MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 525 /* 493 */ MCD_OPC_CheckPredicate, 60, 15, 8, 0, // Skip to: 2561 /* 498 */ MCD_OPC_CheckField, 23, 9, 252, 3, 7, 8, 0, // Skip to: 2561 /* 506 */ MCD_OPC_CheckField, 6, 1, 0, 0, 8, 0, // Skip to: 2561 /* 513 */ MCD_OPC_CheckField, 4, 1, 0, 249, 7, 0, // Skip to: 2561 /* 520 */ MCD_OPC_Decode, 236, 17, 237, 2, // Opcode: VSELGEH /* 525 */ MCD_OPC_FilterValue, 3, 239, 7, 0, // Skip to: 2561 /* 530 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 533 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 563 /* 538 */ MCD_OPC_CheckPredicate, 60, 226, 7, 0, // Skip to: 2561 /* 543 */ MCD_OPC_CheckField, 23, 9, 252, 3, 218, 7, 0, // Skip to: 2561 /* 551 */ MCD_OPC_CheckField, 4, 1, 0, 211, 7, 0, // Skip to: 2561 /* 558 */ MCD_OPC_Decode, 239, 17, 237, 2, // Opcode: VSELGTH /* 563 */ MCD_OPC_FilterValue, 1, 201, 7, 0, // Skip to: 2561 /* 568 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 571 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 608 /* 576 */ MCD_OPC_CheckPredicate, 60, 188, 7, 0, // Skip to: 2561 /* 581 */ MCD_OPC_CheckField, 23, 9, 253, 3, 180, 7, 0, // Skip to: 2561 /* 589 */ MCD_OPC_CheckField, 7, 1, 0, 173, 7, 0, // Skip to: 2561 /* 596 */ MCD_OPC_CheckField, 4, 1, 0, 166, 7, 0, // Skip to: 2561 /* 603 */ MCD_OPC_Decode, 248, 16, 238, 2, // Opcode: VRINTAH /* 608 */ MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 645 /* 613 */ MCD_OPC_CheckPredicate, 60, 151, 7, 0, // Skip to: 2561 /* 618 */ MCD_OPC_CheckField, 23, 9, 253, 3, 143, 7, 0, // Skip to: 2561 /* 626 */ MCD_OPC_CheckField, 7, 1, 0, 136, 7, 0, // Skip to: 2561 /* 633 */ MCD_OPC_CheckField, 4, 1, 0, 129, 7, 0, // Skip to: 2561 /* 640 */ MCD_OPC_Decode, 134, 17, 238, 2, // Opcode: VRINTNH /* 645 */ MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 682 /* 650 */ MCD_OPC_CheckPredicate, 60, 114, 7, 0, // Skip to: 2561 /* 655 */ MCD_OPC_CheckField, 23, 9, 253, 3, 106, 7, 0, // Skip to: 2561 /* 663 */ MCD_OPC_CheckField, 7, 1, 0, 99, 7, 0, // Skip to: 2561 /* 670 */ MCD_OPC_CheckField, 4, 1, 0, 92, 7, 0, // Skip to: 2561 /* 677 */ MCD_OPC_Decode, 141, 17, 238, 2, // Opcode: VRINTPH /* 682 */ MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 719 /* 687 */ MCD_OPC_CheckPredicate, 60, 77, 7, 0, // Skip to: 2561 /* 692 */ MCD_OPC_CheckField, 23, 9, 253, 3, 69, 7, 0, // Skip to: 2561 /* 700 */ MCD_OPC_CheckField, 7, 1, 0, 62, 7, 0, // Skip to: 2561 /* 707 */ MCD_OPC_CheckField, 4, 1, 0, 55, 7, 0, // Skip to: 2561 /* 714 */ MCD_OPC_Decode, 255, 16, 238, 2, // Opcode: VRINTMH /* 719 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 787 /* 724 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 727 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 757 /* 732 */ MCD_OPC_CheckPredicate, 60, 32, 7, 0, // Skip to: 2561 /* 737 */ MCD_OPC_CheckField, 23, 9, 253, 3, 24, 7, 0, // Skip to: 2561 /* 745 */ MCD_OPC_CheckField, 4, 1, 0, 17, 7, 0, // Skip to: 2561 /* 752 */ MCD_OPC_Decode, 165, 9, 239, 2, // Opcode: VCVTAUH /* 757 */ MCD_OPC_FilterValue, 1, 7, 7, 0, // Skip to: 2561 /* 762 */ MCD_OPC_CheckPredicate, 60, 2, 7, 0, // Skip to: 2561 /* 767 */ MCD_OPC_CheckField, 23, 9, 253, 3, 250, 6, 0, // Skip to: 2561 /* 775 */ MCD_OPC_CheckField, 4, 1, 0, 243, 6, 0, // Skip to: 2561 /* 782 */ MCD_OPC_Decode, 162, 9, 239, 2, // Opcode: VCVTASH /* 787 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 855 /* 792 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 795 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 825 /* 800 */ MCD_OPC_CheckPredicate, 60, 220, 6, 0, // Skip to: 2561 /* 805 */ MCD_OPC_CheckField, 23, 9, 253, 3, 212, 6, 0, // Skip to: 2561 /* 813 */ MCD_OPC_CheckField, 4, 1, 0, 205, 6, 0, // Skip to: 2561 /* 820 */ MCD_OPC_Decode, 198, 9, 239, 2, // Opcode: VCVTNUH /* 825 */ MCD_OPC_FilterValue, 1, 195, 6, 0, // Skip to: 2561 /* 830 */ MCD_OPC_CheckPredicate, 60, 190, 6, 0, // Skip to: 2561 /* 835 */ MCD_OPC_CheckField, 23, 9, 253, 3, 182, 6, 0, // Skip to: 2561 /* 843 */ MCD_OPC_CheckField, 4, 1, 0, 175, 6, 0, // Skip to: 2561 /* 850 */ MCD_OPC_Decode, 195, 9, 239, 2, // Opcode: VCVTNSH /* 855 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 923 /* 860 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 863 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 893 /* 868 */ MCD_OPC_CheckPredicate, 60, 152, 6, 0, // Skip to: 2561 /* 873 */ MCD_OPC_CheckField, 23, 9, 253, 3, 144, 6, 0, // Skip to: 2561 /* 881 */ MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2561 /* 888 */ MCD_OPC_Decode, 212, 9, 239, 2, // Opcode: VCVTPUH /* 893 */ MCD_OPC_FilterValue, 1, 127, 6, 0, // Skip to: 2561 /* 898 */ MCD_OPC_CheckPredicate, 60, 122, 6, 0, // Skip to: 2561 /* 903 */ MCD_OPC_CheckField, 23, 9, 253, 3, 114, 6, 0, // Skip to: 2561 /* 911 */ MCD_OPC_CheckField, 4, 1, 0, 107, 6, 0, // Skip to: 2561 /* 918 */ MCD_OPC_Decode, 209, 9, 239, 2, // Opcode: VCVTPSH /* 923 */ MCD_OPC_FilterValue, 15, 97, 6, 0, // Skip to: 2561 /* 928 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 931 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 961 /* 936 */ MCD_OPC_CheckPredicate, 60, 84, 6, 0, // Skip to: 2561 /* 941 */ MCD_OPC_CheckField, 23, 9, 253, 3, 76, 6, 0, // Skip to: 2561 /* 949 */ MCD_OPC_CheckField, 4, 1, 0, 69, 6, 0, // Skip to: 2561 /* 956 */ MCD_OPC_Decode, 184, 9, 239, 2, // Opcode: VCVTMUH /* 961 */ MCD_OPC_FilterValue, 1, 59, 6, 0, // Skip to: 2561 /* 966 */ MCD_OPC_CheckPredicate, 60, 54, 6, 0, // Skip to: 2561 /* 971 */ MCD_OPC_CheckField, 23, 9, 253, 3, 46, 6, 0, // Skip to: 2561 /* 979 */ MCD_OPC_CheckField, 4, 1, 0, 39, 6, 0, // Skip to: 2561 /* 986 */ MCD_OPC_Decode, 181, 9, 239, 2, // Opcode: VCVTMSH /* 991 */ MCD_OPC_FilterValue, 10, 191, 2, 0, // Skip to: 1699 /* 996 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 999 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 1091 /* 1004 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1007 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 1061 /* 1012 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1015 */ MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 1038 /* 1021 */ MCD_OPC_CheckPredicate, 66, 255, 5, 0, // Skip to: 2561 /* 1026 */ MCD_OPC_CheckField, 4, 1, 0, 248, 5, 0, // Skip to: 2561 /* 1033 */ MCD_OPC_Decode, 234, 17, 240, 2, // Opcode: VSELEQS /* 1038 */ MCD_OPC_FilterValue, 253, 3, 237, 5, 0, // Skip to: 2561 /* 1044 */ MCD_OPC_CheckPredicate, 66, 232, 5, 0, // Skip to: 2561 /* 1049 */ MCD_OPC_CheckField, 4, 1, 0, 225, 5, 0, // Skip to: 2561 /* 1056 */ MCD_OPC_Decode, 162, 13, 240, 2, // Opcode: VMAXNMS /* 1061 */ MCD_OPC_FilterValue, 1, 215, 5, 0, // Skip to: 2561 /* 1066 */ MCD_OPC_CheckPredicate, 66, 210, 5, 0, // Skip to: 2561 /* 1071 */ MCD_OPC_CheckField, 23, 9, 253, 3, 202, 5, 0, // Skip to: 2561 /* 1079 */ MCD_OPC_CheckField, 4, 1, 0, 195, 5, 0, // Skip to: 2561 /* 1086 */ MCD_OPC_Decode, 185, 13, 240, 2, // Opcode: VMINNMS /* 1091 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 1128 /* 1096 */ MCD_OPC_CheckPredicate, 66, 180, 5, 0, // Skip to: 2561 /* 1101 */ MCD_OPC_CheckField, 23, 9, 252, 3, 172, 5, 0, // Skip to: 2561 /* 1109 */ MCD_OPC_CheckField, 6, 1, 0, 165, 5, 0, // Skip to: 2561 /* 1116 */ MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2561 /* 1123 */ MCD_OPC_Decode, 243, 17, 240, 2, // Opcode: VSELVSS /* 1128 */ MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 1165 /* 1133 */ MCD_OPC_CheckPredicate, 66, 143, 5, 0, // Skip to: 2561 /* 1138 */ MCD_OPC_CheckField, 23, 9, 252, 3, 135, 5, 0, // Skip to: 2561 /* 1146 */ MCD_OPC_CheckField, 6, 1, 0, 128, 5, 0, // Skip to: 2561 /* 1153 */ MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2561 /* 1160 */ MCD_OPC_Decode, 237, 17, 240, 2, // Opcode: VSELGES /* 1165 */ MCD_OPC_FilterValue, 3, 111, 5, 0, // Skip to: 2561 /* 1170 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1173 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1203 /* 1178 */ MCD_OPC_CheckPredicate, 66, 98, 5, 0, // Skip to: 2561 /* 1183 */ MCD_OPC_CheckField, 23, 9, 252, 3, 90, 5, 0, // Skip to: 2561 /* 1191 */ MCD_OPC_CheckField, 4, 1, 0, 83, 5, 0, // Skip to: 2561 /* 1198 */ MCD_OPC_Decode, 240, 17, 240, 2, // Opcode: VSELGTS /* 1203 */ MCD_OPC_FilterValue, 1, 73, 5, 0, // Skip to: 2561 /* 1208 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 1211 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1279 /* 1216 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1219 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1249 /* 1224 */ MCD_OPC_CheckPredicate, 60, 52, 5, 0, // Skip to: 2561 /* 1229 */ MCD_OPC_CheckField, 23, 9, 253, 3, 44, 5, 0, // Skip to: 2561 /* 1237 */ MCD_OPC_CheckField, 4, 1, 0, 37, 5, 0, // Skip to: 2561 /* 1244 */ MCD_OPC_Decode, 138, 14, 238, 2, // Opcode: VMOVH /* 1249 */ MCD_OPC_FilterValue, 1, 27, 5, 0, // Skip to: 2561 /* 1254 */ MCD_OPC_CheckPredicate, 60, 22, 5, 0, // Skip to: 2561 /* 1259 */ MCD_OPC_CheckField, 23, 9, 253, 3, 14, 5, 0, // Skip to: 2561 /* 1267 */ MCD_OPC_CheckField, 4, 1, 0, 7, 5, 0, // Skip to: 2561 /* 1274 */ MCD_OPC_Decode, 198, 10, 238, 2, // Opcode: VINSH /* 1279 */ MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 1316 /* 1284 */ MCD_OPC_CheckPredicate, 66, 248, 4, 0, // Skip to: 2561 /* 1289 */ MCD_OPC_CheckField, 23, 9, 253, 3, 240, 4, 0, // Skip to: 2561 /* 1297 */ MCD_OPC_CheckField, 7, 1, 0, 233, 4, 0, // Skip to: 2561 /* 1304 */ MCD_OPC_CheckField, 4, 1, 0, 226, 4, 0, // Skip to: 2561 /* 1311 */ MCD_OPC_Decode, 253, 16, 238, 2, // Opcode: VRINTAS /* 1316 */ MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 1353 /* 1321 */ MCD_OPC_CheckPredicate, 66, 211, 4, 0, // Skip to: 2561 /* 1326 */ MCD_OPC_CheckField, 23, 9, 253, 3, 203, 4, 0, // Skip to: 2561 /* 1334 */ MCD_OPC_CheckField, 7, 1, 0, 196, 4, 0, // Skip to: 2561 /* 1341 */ MCD_OPC_CheckField, 4, 1, 0, 189, 4, 0, // Skip to: 2561 /* 1348 */ MCD_OPC_Decode, 139, 17, 238, 2, // Opcode: VRINTNS /* 1353 */ MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 1390 /* 1358 */ MCD_OPC_CheckPredicate, 66, 174, 4, 0, // Skip to: 2561 /* 1363 */ MCD_OPC_CheckField, 23, 9, 253, 3, 166, 4, 0, // Skip to: 2561 /* 1371 */ MCD_OPC_CheckField, 7, 1, 0, 159, 4, 0, // Skip to: 2561 /* 1378 */ MCD_OPC_CheckField, 4, 1, 0, 152, 4, 0, // Skip to: 2561 /* 1385 */ MCD_OPC_Decode, 146, 17, 238, 2, // Opcode: VRINTPS /* 1390 */ MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 1427 /* 1395 */ MCD_OPC_CheckPredicate, 66, 137, 4, 0, // Skip to: 2561 /* 1400 */ MCD_OPC_CheckField, 23, 9, 253, 3, 129, 4, 0, // Skip to: 2561 /* 1408 */ MCD_OPC_CheckField, 7, 1, 0, 122, 4, 0, // Skip to: 2561 /* 1415 */ MCD_OPC_CheckField, 4, 1, 0, 115, 4, 0, // Skip to: 2561 /* 1422 */ MCD_OPC_Decode, 132, 17, 238, 2, // Opcode: VRINTMS /* 1427 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 1495 /* 1432 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1435 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1465 /* 1440 */ MCD_OPC_CheckPredicate, 66, 92, 4, 0, // Skip to: 2561 /* 1445 */ MCD_OPC_CheckField, 23, 9, 253, 3, 84, 4, 0, // Skip to: 2561 /* 1453 */ MCD_OPC_CheckField, 4, 1, 0, 77, 4, 0, // Skip to: 2561 /* 1460 */ MCD_OPC_Decode, 166, 9, 238, 2, // Opcode: VCVTAUS /* 1465 */ MCD_OPC_FilterValue, 1, 67, 4, 0, // Skip to: 2561 /* 1470 */ MCD_OPC_CheckPredicate, 66, 62, 4, 0, // Skip to: 2561 /* 1475 */ MCD_OPC_CheckField, 23, 9, 253, 3, 54, 4, 0, // Skip to: 2561 /* 1483 */ MCD_OPC_CheckField, 4, 1, 0, 47, 4, 0, // Skip to: 2561 /* 1490 */ MCD_OPC_Decode, 163, 9, 238, 2, // Opcode: VCVTASS /* 1495 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1563 /* 1500 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1503 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1533 /* 1508 */ MCD_OPC_CheckPredicate, 66, 24, 4, 0, // Skip to: 2561 /* 1513 */ MCD_OPC_CheckField, 23, 9, 253, 3, 16, 4, 0, // Skip to: 2561 /* 1521 */ MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 2561 /* 1528 */ MCD_OPC_Decode, 199, 9, 238, 2, // Opcode: VCVTNUS /* 1533 */ MCD_OPC_FilterValue, 1, 255, 3, 0, // Skip to: 2561 /* 1538 */ MCD_OPC_CheckPredicate, 66, 250, 3, 0, // Skip to: 2561 /* 1543 */ MCD_OPC_CheckField, 23, 9, 253, 3, 242, 3, 0, // Skip to: 2561 /* 1551 */ MCD_OPC_CheckField, 4, 1, 0, 235, 3, 0, // Skip to: 2561 /* 1558 */ MCD_OPC_Decode, 196, 9, 238, 2, // Opcode: VCVTNSS /* 1563 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 1631 /* 1568 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1571 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1601 /* 1576 */ MCD_OPC_CheckPredicate, 66, 212, 3, 0, // Skip to: 2561 /* 1581 */ MCD_OPC_CheckField, 23, 9, 253, 3, 204, 3, 0, // Skip to: 2561 /* 1589 */ MCD_OPC_CheckField, 4, 1, 0, 197, 3, 0, // Skip to: 2561 /* 1596 */ MCD_OPC_Decode, 213, 9, 238, 2, // Opcode: VCVTPUS /* 1601 */ MCD_OPC_FilterValue, 1, 187, 3, 0, // Skip to: 2561 /* 1606 */ MCD_OPC_CheckPredicate, 66, 182, 3, 0, // Skip to: 2561 /* 1611 */ MCD_OPC_CheckField, 23, 9, 253, 3, 174, 3, 0, // Skip to: 2561 /* 1619 */ MCD_OPC_CheckField, 4, 1, 0, 167, 3, 0, // Skip to: 2561 /* 1626 */ MCD_OPC_Decode, 210, 9, 238, 2, // Opcode: VCVTPSS /* 1631 */ MCD_OPC_FilterValue, 15, 157, 3, 0, // Skip to: 2561 /* 1636 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1639 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1669 /* 1644 */ MCD_OPC_CheckPredicate, 66, 144, 3, 0, // Skip to: 2561 /* 1649 */ MCD_OPC_CheckField, 23, 9, 253, 3, 136, 3, 0, // Skip to: 2561 /* 1657 */ MCD_OPC_CheckField, 4, 1, 0, 129, 3, 0, // Skip to: 2561 /* 1664 */ MCD_OPC_Decode, 185, 9, 238, 2, // Opcode: VCVTMUS /* 1669 */ MCD_OPC_FilterValue, 1, 119, 3, 0, // Skip to: 2561 /* 1674 */ MCD_OPC_CheckPredicate, 66, 114, 3, 0, // Skip to: 2561 /* 1679 */ MCD_OPC_CheckField, 23, 9, 253, 3, 106, 3, 0, // Skip to: 2561 /* 1687 */ MCD_OPC_CheckField, 4, 1, 0, 99, 3, 0, // Skip to: 2561 /* 1694 */ MCD_OPC_Decode, 182, 9, 238, 2, // Opcode: VCVTMSS /* 1699 */ MCD_OPC_FilterValue, 11, 113, 2, 0, // Skip to: 2329 /* 1704 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 1707 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 1796 /* 1712 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1715 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1767 /* 1720 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 1723 */ MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 1745 /* 1729 */ MCD_OPC_CheckPredicate, 69, 59, 3, 0, // Skip to: 2561 /* 1734 */ MCD_OPC_CheckField, 4, 1, 0, 52, 3, 0, // Skip to: 2561 /* 1741 */ MCD_OPC_Decode, 232, 17, 97, // Opcode: VSELEQD /* 1745 */ MCD_OPC_FilterValue, 253, 3, 42, 3, 0, // Skip to: 2561 /* 1751 */ MCD_OPC_CheckPredicate, 69, 37, 3, 0, // Skip to: 2561 /* 1756 */ MCD_OPC_CheckField, 4, 1, 0, 30, 3, 0, // Skip to: 2561 /* 1763 */ MCD_OPC_Decode, 156, 13, 97, // Opcode: VMAXNMD /* 1767 */ MCD_OPC_FilterValue, 1, 21, 3, 0, // Skip to: 2561 /* 1772 */ MCD_OPC_CheckPredicate, 69, 16, 3, 0, // Skip to: 2561 /* 1777 */ MCD_OPC_CheckField, 23, 9, 253, 3, 8, 3, 0, // Skip to: 2561 /* 1785 */ MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 2561 /* 1792 */ MCD_OPC_Decode, 179, 13, 97, // Opcode: VMINNMD /* 1796 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 1832 /* 1801 */ MCD_OPC_CheckPredicate, 69, 243, 2, 0, // Skip to: 2561 /* 1806 */ MCD_OPC_CheckField, 23, 9, 252, 3, 235, 2, 0, // Skip to: 2561 /* 1814 */ MCD_OPC_CheckField, 6, 1, 0, 228, 2, 0, // Skip to: 2561 /* 1821 */ MCD_OPC_CheckField, 4, 1, 0, 221, 2, 0, // Skip to: 2561 /* 1828 */ MCD_OPC_Decode, 241, 17, 97, // Opcode: VSELVSD /* 1832 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1868 /* 1837 */ MCD_OPC_CheckPredicate, 69, 207, 2, 0, // Skip to: 2561 /* 1842 */ MCD_OPC_CheckField, 23, 9, 252, 3, 199, 2, 0, // Skip to: 2561 /* 1850 */ MCD_OPC_CheckField, 6, 1, 0, 192, 2, 0, // Skip to: 2561 /* 1857 */ MCD_OPC_CheckField, 4, 1, 0, 185, 2, 0, // Skip to: 2561 /* 1864 */ MCD_OPC_Decode, 235, 17, 97, // Opcode: VSELGED /* 1868 */ MCD_OPC_FilterValue, 3, 176, 2, 0, // Skip to: 2561 /* 1873 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1876 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1905 /* 1881 */ MCD_OPC_CheckPredicate, 69, 163, 2, 0, // Skip to: 2561 /* 1886 */ MCD_OPC_CheckField, 23, 9, 252, 3, 155, 2, 0, // Skip to: 2561 /* 1894 */ MCD_OPC_CheckField, 4, 1, 0, 148, 2, 0, // Skip to: 2561 /* 1901 */ MCD_OPC_Decode, 238, 17, 97, // Opcode: VSELGTD /* 1905 */ MCD_OPC_FilterValue, 1, 139, 2, 0, // Skip to: 2561 /* 1910 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 1913 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 1949 /* 1918 */ MCD_OPC_CheckPredicate, 69, 126, 2, 0, // Skip to: 2561 /* 1923 */ MCD_OPC_CheckField, 23, 9, 253, 3, 118, 2, 0, // Skip to: 2561 /* 1931 */ MCD_OPC_CheckField, 7, 1, 0, 111, 2, 0, // Skip to: 2561 /* 1938 */ MCD_OPC_CheckField, 4, 1, 0, 104, 2, 0, // Skip to: 2561 /* 1945 */ MCD_OPC_Decode, 247, 16, 126, // Opcode: VRINTAD /* 1949 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 1985 /* 1954 */ MCD_OPC_CheckPredicate, 69, 90, 2, 0, // Skip to: 2561 /* 1959 */ MCD_OPC_CheckField, 23, 9, 253, 3, 82, 2, 0, // Skip to: 2561 /* 1967 */ MCD_OPC_CheckField, 7, 1, 0, 75, 2, 0, // Skip to: 2561 /* 1974 */ MCD_OPC_CheckField, 4, 1, 0, 68, 2, 0, // Skip to: 2561 /* 1981 */ MCD_OPC_Decode, 133, 17, 126, // Opcode: VRINTND /* 1985 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2021 /* 1990 */ MCD_OPC_CheckPredicate, 69, 54, 2, 0, // Skip to: 2561 /* 1995 */ MCD_OPC_CheckField, 23, 9, 253, 3, 46, 2, 0, // Skip to: 2561 /* 2003 */ MCD_OPC_CheckField, 7, 1, 0, 39, 2, 0, // Skip to: 2561 /* 2010 */ MCD_OPC_CheckField, 4, 1, 0, 32, 2, 0, // Skip to: 2561 /* 2017 */ MCD_OPC_Decode, 140, 17, 126, // Opcode: VRINTPD /* 2021 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2057 /* 2026 */ MCD_OPC_CheckPredicate, 69, 18, 2, 0, // Skip to: 2561 /* 2031 */ MCD_OPC_CheckField, 23, 9, 253, 3, 10, 2, 0, // Skip to: 2561 /* 2039 */ MCD_OPC_CheckField, 7, 1, 0, 3, 2, 0, // Skip to: 2561 /* 2046 */ MCD_OPC_CheckField, 4, 1, 0, 252, 1, 0, // Skip to: 2561 /* 2053 */ MCD_OPC_Decode, 254, 16, 126, // Opcode: VRINTMD /* 2057 */ MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 2125 /* 2062 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 2065 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2095 /* 2070 */ MCD_OPC_CheckPredicate, 69, 230, 1, 0, // Skip to: 2561 /* 2075 */ MCD_OPC_CheckField, 23, 9, 253, 3, 222, 1, 0, // Skip to: 2561 /* 2083 */ MCD_OPC_CheckField, 4, 1, 0, 215, 1, 0, // Skip to: 2561 /* 2090 */ MCD_OPC_Decode, 164, 9, 241, 2, // Opcode: VCVTAUD /* 2095 */ MCD_OPC_FilterValue, 1, 205, 1, 0, // Skip to: 2561 /* 2100 */ MCD_OPC_CheckPredicate, 69, 200, 1, 0, // Skip to: 2561 /* 2105 */ MCD_OPC_CheckField, 23, 9, 253, 3, 192, 1, 0, // Skip to: 2561 /* 2113 */ MCD_OPC_CheckField, 4, 1, 0, 185, 1, 0, // Skip to: 2561 /* 2120 */ MCD_OPC_Decode, 161, 9, 241, 2, // Opcode: VCVTASD /* 2125 */ MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 2193 /* 2130 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 2133 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2163 /* 2138 */ MCD_OPC_CheckPredicate, 69, 162, 1, 0, // Skip to: 2561 /* 2143 */ MCD_OPC_CheckField, 23, 9, 253, 3, 154, 1, 0, // Skip to: 2561 /* 2151 */ MCD_OPC_CheckField, 4, 1, 0, 147, 1, 0, // Skip to: 2561 /* 2158 */ MCD_OPC_Decode, 197, 9, 241, 2, // Opcode: VCVTNUD /* 2163 */ MCD_OPC_FilterValue, 1, 137, 1, 0, // Skip to: 2561 /* 2168 */ MCD_OPC_CheckPredicate, 69, 132, 1, 0, // Skip to: 2561 /* 2173 */ MCD_OPC_CheckField, 23, 9, 253, 3, 124, 1, 0, // Skip to: 2561 /* 2181 */ MCD_OPC_CheckField, 4, 1, 0, 117, 1, 0, // Skip to: 2561 /* 2188 */ MCD_OPC_Decode, 194, 9, 241, 2, // Opcode: VCVTNSD /* 2193 */ MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 2261 /* 2198 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 2201 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2231 /* 2206 */ MCD_OPC_CheckPredicate, 69, 94, 1, 0, // Skip to: 2561 /* 2211 */ MCD_OPC_CheckField, 23, 9, 253, 3, 86, 1, 0, // Skip to: 2561 /* 2219 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 2561 /* 2226 */ MCD_OPC_Decode, 211, 9, 241, 2, // Opcode: VCVTPUD /* 2231 */ MCD_OPC_FilterValue, 1, 69, 1, 0, // Skip to: 2561 /* 2236 */ MCD_OPC_CheckPredicate, 69, 64, 1, 0, // Skip to: 2561 /* 2241 */ MCD_OPC_CheckField, 23, 9, 253, 3, 56, 1, 0, // Skip to: 2561 /* 2249 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2561 /* 2256 */ MCD_OPC_Decode, 208, 9, 241, 2, // Opcode: VCVTPSD /* 2261 */ MCD_OPC_FilterValue, 15, 39, 1, 0, // Skip to: 2561 /* 2266 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 2269 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2299 /* 2274 */ MCD_OPC_CheckPredicate, 69, 26, 1, 0, // Skip to: 2561 /* 2279 */ MCD_OPC_CheckField, 23, 9, 253, 3, 18, 1, 0, // Skip to: 2561 /* 2287 */ MCD_OPC_CheckField, 4, 1, 0, 11, 1, 0, // Skip to: 2561 /* 2294 */ MCD_OPC_Decode, 183, 9, 241, 2, // Opcode: VCVTMUD /* 2299 */ MCD_OPC_FilterValue, 1, 1, 1, 0, // Skip to: 2561 /* 2304 */ MCD_OPC_CheckPredicate, 69, 252, 0, 0, // Skip to: 2561 /* 2309 */ MCD_OPC_CheckField, 23, 9, 253, 3, 244, 0, 0, // Skip to: 2561 /* 2317 */ MCD_OPC_CheckField, 4, 1, 0, 237, 0, 0, // Skip to: 2561 /* 2324 */ MCD_OPC_Decode, 180, 9, 241, 2, // Opcode: VCVTMSD /* 2329 */ MCD_OPC_FilterValue, 13, 227, 0, 0, // Skip to: 2561 /* 2334 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 2337 */ MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 2449 /* 2342 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2345 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2397 /* 2350 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2353 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2375 /* 2359 */ MCD_OPC_CheckPredicate, 73, 197, 0, 0, // Skip to: 2561 /* 2364 */ MCD_OPC_CheckField, 20, 2, 2, 190, 0, 0, // Skip to: 2561 /* 2371 */ MCD_OPC_Decode, 228, 17, 105, // Opcode: VSDOTD /* 2375 */ MCD_OPC_FilterValue, 252, 3, 180, 0, 0, // Skip to: 2561 /* 2381 */ MCD_OPC_CheckPredicate, 73, 175, 0, 0, // Skip to: 2561 /* 2386 */ MCD_OPC_CheckField, 20, 2, 2, 168, 0, 0, // Skip to: 2561 /* 2393 */ MCD_OPC_Decode, 229, 17, 113, // Opcode: VSDOTDI /* 2397 */ MCD_OPC_FilterValue, 1, 159, 0, 0, // Skip to: 2561 /* 2402 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2405 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2427 /* 2411 */ MCD_OPC_CheckPredicate, 73, 145, 0, 0, // Skip to: 2561 /* 2416 */ MCD_OPC_CheckField, 20, 2, 2, 138, 0, 0, // Skip to: 2561 /* 2423 */ MCD_OPC_Decode, 230, 17, 106, // Opcode: VSDOTQ /* 2427 */ MCD_OPC_FilterValue, 252, 3, 128, 0, 0, // Skip to: 2561 /* 2433 */ MCD_OPC_CheckPredicate, 73, 123, 0, 0, // Skip to: 2561 /* 2438 */ MCD_OPC_CheckField, 20, 2, 2, 116, 0, 0, // Skip to: 2561 /* 2445 */ MCD_OPC_Decode, 231, 17, 114, // Opcode: VSDOTQI /* 2449 */ MCD_OPC_FilterValue, 1, 107, 0, 0, // Skip to: 2561 /* 2454 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2457 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2509 /* 2462 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2465 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2487 /* 2471 */ MCD_OPC_CheckPredicate, 73, 85, 0, 0, // Skip to: 2561 /* 2476 */ MCD_OPC_CheckField, 20, 2, 2, 78, 0, 0, // Skip to: 2561 /* 2483 */ MCD_OPC_Decode, 159, 21, 105, // Opcode: VUDOTD /* 2487 */ MCD_OPC_FilterValue, 252, 3, 68, 0, 0, // Skip to: 2561 /* 2493 */ MCD_OPC_CheckPredicate, 73, 63, 0, 0, // Skip to: 2561 /* 2498 */ MCD_OPC_CheckField, 20, 2, 2, 56, 0, 0, // Skip to: 2561 /* 2505 */ MCD_OPC_Decode, 160, 21, 113, // Opcode: VUDOTDI /* 2509 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 2561 /* 2514 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 2517 */ MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2539 /* 2523 */ MCD_OPC_CheckPredicate, 73, 33, 0, 0, // Skip to: 2561 /* 2528 */ MCD_OPC_CheckField, 20, 2, 2, 26, 0, 0, // Skip to: 2561 /* 2535 */ MCD_OPC_Decode, 161, 21, 106, // Opcode: VUDOTQ /* 2539 */ MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 2561 /* 2545 */ MCD_OPC_CheckPredicate, 73, 11, 0, 0, // Skip to: 2561 /* 2550 */ MCD_OPC_CheckField, 20, 2, 2, 4, 0, 0, // Skip to: 2561 /* 2557 */ MCD_OPC_Decode, 162, 21, 114, // Opcode: VUDOTQI /* 2561 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTablev8Crypto32[] = { /* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 3 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 83 /* 8 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 11 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 47 /* 17 */ MCD_OPC_CheckPredicate, 24, 12, 2, 0, // Skip to: 546 /* 22 */ MCD_OPC_CheckField, 8, 4, 12, 5, 2, 0, // Skip to: 546 /* 29 */ MCD_OPC_CheckField, 6, 1, 1, 254, 1, 0, // Skip to: 546 /* 36 */ MCD_OPC_CheckField, 4, 1, 0, 247, 1, 0, // Skip to: 546 /* 43 */ MCD_OPC_Decode, 247, 5, 106, // Opcode: SHA1C /* 47 */ MCD_OPC_FilterValue, 230, 3, 237, 1, 0, // Skip to: 546 /* 53 */ MCD_OPC_CheckPredicate, 24, 232, 1, 0, // Skip to: 546 /* 58 */ MCD_OPC_CheckField, 8, 4, 12, 225, 1, 0, // Skip to: 546 /* 65 */ MCD_OPC_CheckField, 6, 1, 1, 218, 1, 0, // Skip to: 546 /* 72 */ MCD_OPC_CheckField, 4, 1, 0, 211, 1, 0, // Skip to: 546 /* 79 */ MCD_OPC_Decode, 253, 5, 106, // Opcode: SHA256H /* 83 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 163 /* 88 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 91 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 127 /* 97 */ MCD_OPC_CheckPredicate, 24, 188, 1, 0, // Skip to: 546 /* 102 */ MCD_OPC_CheckField, 8, 4, 12, 181, 1, 0, // Skip to: 546 /* 109 */ MCD_OPC_CheckField, 6, 1, 1, 174, 1, 0, // Skip to: 546 /* 116 */ MCD_OPC_CheckField, 4, 1, 0, 167, 1, 0, // Skip to: 546 /* 123 */ MCD_OPC_Decode, 250, 5, 106, // Opcode: SHA1P /* 127 */ MCD_OPC_FilterValue, 230, 3, 157, 1, 0, // Skip to: 546 /* 133 */ MCD_OPC_CheckPredicate, 24, 152, 1, 0, // Skip to: 546 /* 138 */ MCD_OPC_CheckField, 8, 4, 12, 145, 1, 0, // Skip to: 546 /* 145 */ MCD_OPC_CheckField, 6, 1, 1, 138, 1, 0, // Skip to: 546 /* 152 */ MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 546 /* 159 */ MCD_OPC_Decode, 254, 5, 106, // Opcode: SHA256H2 /* 163 */ MCD_OPC_FilterValue, 2, 75, 0, 0, // Skip to: 243 /* 168 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... /* 171 */ MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 207 /* 177 */ MCD_OPC_CheckPredicate, 24, 108, 1, 0, // Skip to: 546 /* 182 */ MCD_OPC_CheckField, 8, 4, 12, 101, 1, 0, // Skip to: 546 /* 189 */ MCD_OPC_CheckField, 6, 1, 1, 94, 1, 0, // Skip to: 546 /* 196 */ MCD_OPC_CheckField, 4, 1, 0, 87, 1, 0, // Skip to: 546 /* 203 */ MCD_OPC_Decode, 249, 5, 106, // Opcode: SHA1M /* 207 */ MCD_OPC_FilterValue, 230, 3, 77, 1, 0, // Skip to: 546 /* 213 */ MCD_OPC_CheckPredicate, 24, 72, 1, 0, // Skip to: 546 /* 218 */ MCD_OPC_CheckField, 8, 4, 12, 65, 1, 0, // Skip to: 546 /* 225 */ MCD_OPC_CheckField, 6, 1, 1, 58, 1, 0, // Skip to: 546 /* 232 */ MCD_OPC_CheckField, 4, 1, 0, 51, 1, 0, // Skip to: 546 /* 239 */ MCD_OPC_Decode, 128, 6, 106, // Opcode: SHA256SU1 /* 243 */ MCD_OPC_FilterValue, 3, 42, 1, 0, // Skip to: 546 /* 248 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 251 */ MCD_OPC_FilterValue, 2, 38, 0, 0, // Skip to: 294 /* 256 */ MCD_OPC_CheckPredicate, 24, 29, 1, 0, // Skip to: 546 /* 261 */ MCD_OPC_CheckField, 23, 9, 231, 3, 21, 1, 0, // Skip to: 546 /* 269 */ MCD_OPC_CheckField, 16, 4, 9, 14, 1, 0, // Skip to: 546 /* 276 */ MCD_OPC_CheckField, 6, 2, 3, 7, 1, 0, // Skip to: 546 /* 283 */ MCD_OPC_CheckField, 4, 1, 0, 0, 1, 0, // Skip to: 546 /* 290 */ MCD_OPC_Decode, 248, 5, 127, // Opcode: SHA1H /* 294 */ MCD_OPC_FilterValue, 3, 211, 0, 0, // Skip to: 510 /* 299 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 302 */ MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 339 /* 307 */ MCD_OPC_CheckPredicate, 24, 234, 0, 0, // Skip to: 546 /* 312 */ MCD_OPC_CheckField, 23, 9, 231, 3, 226, 0, 0, // Skip to: 546 /* 320 */ MCD_OPC_CheckField, 16, 4, 0, 219, 0, 0, // Skip to: 546 /* 327 */ MCD_OPC_CheckField, 4, 1, 0, 212, 0, 0, // Skip to: 546 /* 334 */ MCD_OPC_Decode, 155, 4, 133, 1, // Opcode: AESE /* 339 */ MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 376 /* 344 */ MCD_OPC_CheckPredicate, 24, 197, 0, 0, // Skip to: 546 /* 349 */ MCD_OPC_CheckField, 23, 9, 231, 3, 189, 0, 0, // Skip to: 546 /* 357 */ MCD_OPC_CheckField, 16, 4, 0, 182, 0, 0, // Skip to: 546 /* 364 */ MCD_OPC_CheckField, 4, 1, 0, 175, 0, 0, // Skip to: 546 /* 371 */ MCD_OPC_Decode, 154, 4, 133, 1, // Opcode: AESD /* 376 */ MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 443 /* 381 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 384 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 413 /* 389 */ MCD_OPC_CheckPredicate, 24, 152, 0, 0, // Skip to: 546 /* 394 */ MCD_OPC_CheckField, 23, 9, 231, 3, 144, 0, 0, // Skip to: 546 /* 402 */ MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 546 /* 409 */ MCD_OPC_Decode, 157, 4, 127, // Opcode: AESMC /* 413 */ MCD_OPC_FilterValue, 10, 128, 0, 0, // Skip to: 546 /* 418 */ MCD_OPC_CheckPredicate, 24, 123, 0, 0, // Skip to: 546 /* 423 */ MCD_OPC_CheckField, 23, 9, 231, 3, 115, 0, 0, // Skip to: 546 /* 431 */ MCD_OPC_CheckField, 4, 1, 0, 108, 0, 0, // Skip to: 546 /* 438 */ MCD_OPC_Decode, 252, 5, 133, 1, // Opcode: SHA1SU1 /* 443 */ MCD_OPC_FilterValue, 3, 98, 0, 0, // Skip to: 546 /* 448 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 451 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 480 /* 456 */ MCD_OPC_CheckPredicate, 24, 85, 0, 0, // Skip to: 546 /* 461 */ MCD_OPC_CheckField, 23, 9, 231, 3, 77, 0, 0, // Skip to: 546 /* 469 */ MCD_OPC_CheckField, 4, 1, 0, 70, 0, 0, // Skip to: 546 /* 476 */ MCD_OPC_Decode, 156, 4, 127, // Opcode: AESIMC /* 480 */ MCD_OPC_FilterValue, 10, 61, 0, 0, // Skip to: 546 /* 485 */ MCD_OPC_CheckPredicate, 24, 56, 0, 0, // Skip to: 546 /* 490 */ MCD_OPC_CheckField, 23, 9, 231, 3, 48, 0, 0, // Skip to: 546 /* 498 */ MCD_OPC_CheckField, 4, 1, 0, 41, 0, 0, // Skip to: 546 /* 505 */ MCD_OPC_Decode, 255, 5, 133, 1, // Opcode: SHA256SU0 /* 510 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 546 /* 515 */ MCD_OPC_CheckPredicate, 24, 26, 0, 0, // Skip to: 546 /* 520 */ MCD_OPC_CheckField, 23, 9, 228, 3, 18, 0, 0, // Skip to: 546 /* 528 */ MCD_OPC_CheckField, 6, 1, 1, 11, 0, 0, // Skip to: 546 /* 535 */ MCD_OPC_CheckField, 4, 1, 0, 4, 0, 0, // Skip to: 546 /* 542 */ MCD_OPC_Decode, 251, 5, 106, // Opcode: SHA1SU0 /* 546 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTablev8NEON32[] = { /* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 3 */ MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 275 /* 8 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 11 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 77 /* 16 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 19 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 48 /* 24 */ MCD_OPC_CheckPredicate, 74, 110, 8, 0, // Skip to: 2187 /* 29 */ MCD_OPC_CheckField, 23, 9, 231, 3, 102, 8, 0, // Skip to: 2187 /* 37 */ MCD_OPC_CheckField, 4, 1, 0, 95, 8, 0, // Skip to: 2187 /* 44 */ MCD_OPC_Decode, 154, 9, 126, // Opcode: VCVTANSDh /* 48 */ MCD_OPC_FilterValue, 59, 86, 8, 0, // Skip to: 2187 /* 53 */ MCD_OPC_CheckPredicate, 75, 81, 8, 0, // Skip to: 2187 /* 58 */ MCD_OPC_CheckField, 23, 9, 231, 3, 73, 8, 0, // Skip to: 2187 /* 66 */ MCD_OPC_CheckField, 4, 1, 0, 66, 8, 0, // Skip to: 2187 /* 73 */ MCD_OPC_Decode, 153, 9, 126, // Opcode: VCVTANSDf /* 77 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 143 /* 82 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 85 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 114 /* 90 */ MCD_OPC_CheckPredicate, 74, 44, 8, 0, // Skip to: 2187 /* 95 */ MCD_OPC_CheckField, 23, 9, 231, 3, 36, 8, 0, // Skip to: 2187 /* 103 */ MCD_OPC_CheckField, 4, 1, 0, 29, 8, 0, // Skip to: 2187 /* 110 */ MCD_OPC_Decode, 156, 9, 127, // Opcode: VCVTANSQh /* 114 */ MCD_OPC_FilterValue, 59, 20, 8, 0, // Skip to: 2187 /* 119 */ MCD_OPC_CheckPredicate, 75, 15, 8, 0, // Skip to: 2187 /* 124 */ MCD_OPC_CheckField, 23, 9, 231, 3, 7, 8, 0, // Skip to: 2187 /* 132 */ MCD_OPC_CheckField, 4, 1, 0, 0, 8, 0, // Skip to: 2187 /* 139 */ MCD_OPC_Decode, 155, 9, 127, // Opcode: VCVTANSQf /* 143 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 209 /* 148 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 151 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 180 /* 156 */ MCD_OPC_CheckPredicate, 74, 234, 7, 0, // Skip to: 2187 /* 161 */ MCD_OPC_CheckField, 23, 9, 231, 3, 226, 7, 0, // Skip to: 2187 /* 169 */ MCD_OPC_CheckField, 4, 1, 0, 219, 7, 0, // Skip to: 2187 /* 176 */ MCD_OPC_Decode, 158, 9, 126, // Opcode: VCVTANUDh /* 180 */ MCD_OPC_FilterValue, 59, 210, 7, 0, // Skip to: 2187 /* 185 */ MCD_OPC_CheckPredicate, 75, 205, 7, 0, // Skip to: 2187 /* 190 */ MCD_OPC_CheckField, 23, 9, 231, 3, 197, 7, 0, // Skip to: 2187 /* 198 */ MCD_OPC_CheckField, 4, 1, 0, 190, 7, 0, // Skip to: 2187 /* 205 */ MCD_OPC_Decode, 157, 9, 126, // Opcode: VCVTANUDf /* 209 */ MCD_OPC_FilterValue, 3, 181, 7, 0, // Skip to: 2187 /* 214 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 217 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 246 /* 222 */ MCD_OPC_CheckPredicate, 74, 168, 7, 0, // Skip to: 2187 /* 227 */ MCD_OPC_CheckField, 23, 9, 231, 3, 160, 7, 0, // Skip to: 2187 /* 235 */ MCD_OPC_CheckField, 4, 1, 0, 153, 7, 0, // Skip to: 2187 /* 242 */ MCD_OPC_Decode, 160, 9, 127, // Opcode: VCVTANUQh /* 246 */ MCD_OPC_FilterValue, 59, 144, 7, 0, // Skip to: 2187 /* 251 */ MCD_OPC_CheckPredicate, 75, 139, 7, 0, // Skip to: 2187 /* 256 */ MCD_OPC_CheckField, 23, 9, 231, 3, 131, 7, 0, // Skip to: 2187 /* 264 */ MCD_OPC_CheckField, 4, 1, 0, 124, 7, 0, // Skip to: 2187 /* 271 */ MCD_OPC_Decode, 159, 9, 127, // Opcode: VCVTANUQf /* 275 */ MCD_OPC_FilterValue, 1, 11, 1, 0, // Skip to: 547 /* 280 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 283 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 349 /* 288 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 291 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 320 /* 296 */ MCD_OPC_CheckPredicate, 74, 94, 7, 0, // Skip to: 2187 /* 301 */ MCD_OPC_CheckField, 23, 9, 231, 3, 86, 7, 0, // Skip to: 2187 /* 309 */ MCD_OPC_CheckField, 4, 1, 0, 79, 7, 0, // Skip to: 2187 /* 316 */ MCD_OPC_Decode, 187, 9, 126, // Opcode: VCVTNNSDh /* 320 */ MCD_OPC_FilterValue, 59, 70, 7, 0, // Skip to: 2187 /* 325 */ MCD_OPC_CheckPredicate, 75, 65, 7, 0, // Skip to: 2187 /* 330 */ MCD_OPC_CheckField, 23, 9, 231, 3, 57, 7, 0, // Skip to: 2187 /* 338 */ MCD_OPC_CheckField, 4, 1, 0, 50, 7, 0, // Skip to: 2187 /* 345 */ MCD_OPC_Decode, 186, 9, 126, // Opcode: VCVTNNSDf /* 349 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 415 /* 354 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 357 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 386 /* 362 */ MCD_OPC_CheckPredicate, 74, 28, 7, 0, // Skip to: 2187 /* 367 */ MCD_OPC_CheckField, 23, 9, 231, 3, 20, 7, 0, // Skip to: 2187 /* 375 */ MCD_OPC_CheckField, 4, 1, 0, 13, 7, 0, // Skip to: 2187 /* 382 */ MCD_OPC_Decode, 189, 9, 127, // Opcode: VCVTNNSQh /* 386 */ MCD_OPC_FilterValue, 59, 4, 7, 0, // Skip to: 2187 /* 391 */ MCD_OPC_CheckPredicate, 75, 255, 6, 0, // Skip to: 2187 /* 396 */ MCD_OPC_CheckField, 23, 9, 231, 3, 247, 6, 0, // Skip to: 2187 /* 404 */ MCD_OPC_CheckField, 4, 1, 0, 240, 6, 0, // Skip to: 2187 /* 411 */ MCD_OPC_Decode, 188, 9, 127, // Opcode: VCVTNNSQf /* 415 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 481 /* 420 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 423 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 452 /* 428 */ MCD_OPC_CheckPredicate, 74, 218, 6, 0, // Skip to: 2187 /* 433 */ MCD_OPC_CheckField, 23, 9, 231, 3, 210, 6, 0, // Skip to: 2187 /* 441 */ MCD_OPC_CheckField, 4, 1, 0, 203, 6, 0, // Skip to: 2187 /* 448 */ MCD_OPC_Decode, 191, 9, 126, // Opcode: VCVTNNUDh /* 452 */ MCD_OPC_FilterValue, 59, 194, 6, 0, // Skip to: 2187 /* 457 */ MCD_OPC_CheckPredicate, 75, 189, 6, 0, // Skip to: 2187 /* 462 */ MCD_OPC_CheckField, 23, 9, 231, 3, 181, 6, 0, // Skip to: 2187 /* 470 */ MCD_OPC_CheckField, 4, 1, 0, 174, 6, 0, // Skip to: 2187 /* 477 */ MCD_OPC_Decode, 190, 9, 126, // Opcode: VCVTNNUDf /* 481 */ MCD_OPC_FilterValue, 3, 165, 6, 0, // Skip to: 2187 /* 486 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 489 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 518 /* 494 */ MCD_OPC_CheckPredicate, 74, 152, 6, 0, // Skip to: 2187 /* 499 */ MCD_OPC_CheckField, 23, 9, 231, 3, 144, 6, 0, // Skip to: 2187 /* 507 */ MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2187 /* 514 */ MCD_OPC_Decode, 193, 9, 127, // Opcode: VCVTNNUQh /* 518 */ MCD_OPC_FilterValue, 59, 128, 6, 0, // Skip to: 2187 /* 523 */ MCD_OPC_CheckPredicate, 75, 123, 6, 0, // Skip to: 2187 /* 528 */ MCD_OPC_CheckField, 23, 9, 231, 3, 115, 6, 0, // Skip to: 2187 /* 536 */ MCD_OPC_CheckField, 4, 1, 0, 108, 6, 0, // Skip to: 2187 /* 543 */ MCD_OPC_Decode, 192, 9, 127, // Opcode: VCVTNNUQf /* 547 */ MCD_OPC_FilterValue, 2, 11, 1, 0, // Skip to: 819 /* 552 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 555 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 621 /* 560 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 563 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 592 /* 568 */ MCD_OPC_CheckPredicate, 74, 78, 6, 0, // Skip to: 2187 /* 573 */ MCD_OPC_CheckField, 23, 9, 231, 3, 70, 6, 0, // Skip to: 2187 /* 581 */ MCD_OPC_CheckField, 4, 1, 0, 63, 6, 0, // Skip to: 2187 /* 588 */ MCD_OPC_Decode, 201, 9, 126, // Opcode: VCVTPNSDh /* 592 */ MCD_OPC_FilterValue, 59, 54, 6, 0, // Skip to: 2187 /* 597 */ MCD_OPC_CheckPredicate, 75, 49, 6, 0, // Skip to: 2187 /* 602 */ MCD_OPC_CheckField, 23, 9, 231, 3, 41, 6, 0, // Skip to: 2187 /* 610 */ MCD_OPC_CheckField, 4, 1, 0, 34, 6, 0, // Skip to: 2187 /* 617 */ MCD_OPC_Decode, 200, 9, 126, // Opcode: VCVTPNSDf /* 621 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 687 /* 626 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 629 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 658 /* 634 */ MCD_OPC_CheckPredicate, 74, 12, 6, 0, // Skip to: 2187 /* 639 */ MCD_OPC_CheckField, 23, 9, 231, 3, 4, 6, 0, // Skip to: 2187 /* 647 */ MCD_OPC_CheckField, 4, 1, 0, 253, 5, 0, // Skip to: 2187 /* 654 */ MCD_OPC_Decode, 203, 9, 127, // Opcode: VCVTPNSQh /* 658 */ MCD_OPC_FilterValue, 59, 244, 5, 0, // Skip to: 2187 /* 663 */ MCD_OPC_CheckPredicate, 75, 239, 5, 0, // Skip to: 2187 /* 668 */ MCD_OPC_CheckField, 23, 9, 231, 3, 231, 5, 0, // Skip to: 2187 /* 676 */ MCD_OPC_CheckField, 4, 1, 0, 224, 5, 0, // Skip to: 2187 /* 683 */ MCD_OPC_Decode, 202, 9, 127, // Opcode: VCVTPNSQf /* 687 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 753 /* 692 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 695 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 724 /* 700 */ MCD_OPC_CheckPredicate, 74, 202, 5, 0, // Skip to: 2187 /* 705 */ MCD_OPC_CheckField, 23, 9, 231, 3, 194, 5, 0, // Skip to: 2187 /* 713 */ MCD_OPC_CheckField, 4, 1, 0, 187, 5, 0, // Skip to: 2187 /* 720 */ MCD_OPC_Decode, 205, 9, 126, // Opcode: VCVTPNUDh /* 724 */ MCD_OPC_FilterValue, 59, 178, 5, 0, // Skip to: 2187 /* 729 */ MCD_OPC_CheckPredicate, 75, 173, 5, 0, // Skip to: 2187 /* 734 */ MCD_OPC_CheckField, 23, 9, 231, 3, 165, 5, 0, // Skip to: 2187 /* 742 */ MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2187 /* 749 */ MCD_OPC_Decode, 204, 9, 126, // Opcode: VCVTPNUDf /* 753 */ MCD_OPC_FilterValue, 3, 149, 5, 0, // Skip to: 2187 /* 758 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 761 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 790 /* 766 */ MCD_OPC_CheckPredicate, 74, 136, 5, 0, // Skip to: 2187 /* 771 */ MCD_OPC_CheckField, 23, 9, 231, 3, 128, 5, 0, // Skip to: 2187 /* 779 */ MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2187 /* 786 */ MCD_OPC_Decode, 207, 9, 127, // Opcode: VCVTPNUQh /* 790 */ MCD_OPC_FilterValue, 59, 112, 5, 0, // Skip to: 2187 /* 795 */ MCD_OPC_CheckPredicate, 75, 107, 5, 0, // Skip to: 2187 /* 800 */ MCD_OPC_CheckField, 23, 9, 231, 3, 99, 5, 0, // Skip to: 2187 /* 808 */ MCD_OPC_CheckField, 4, 1, 0, 92, 5, 0, // Skip to: 2187 /* 815 */ MCD_OPC_Decode, 206, 9, 127, // Opcode: VCVTPNUQf /* 819 */ MCD_OPC_FilterValue, 3, 11, 1, 0, // Skip to: 1091 /* 824 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 827 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 893 /* 832 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 835 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 864 /* 840 */ MCD_OPC_CheckPredicate, 74, 62, 5, 0, // Skip to: 2187 /* 845 */ MCD_OPC_CheckField, 23, 9, 231, 3, 54, 5, 0, // Skip to: 2187 /* 853 */ MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 2187 /* 860 */ MCD_OPC_Decode, 173, 9, 126, // Opcode: VCVTMNSDh /* 864 */ MCD_OPC_FilterValue, 59, 38, 5, 0, // Skip to: 2187 /* 869 */ MCD_OPC_CheckPredicate, 75, 33, 5, 0, // Skip to: 2187 /* 874 */ MCD_OPC_CheckField, 23, 9, 231, 3, 25, 5, 0, // Skip to: 2187 /* 882 */ MCD_OPC_CheckField, 4, 1, 0, 18, 5, 0, // Skip to: 2187 /* 889 */ MCD_OPC_Decode, 172, 9, 126, // Opcode: VCVTMNSDf /* 893 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 959 /* 898 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 901 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 930 /* 906 */ MCD_OPC_CheckPredicate, 74, 252, 4, 0, // Skip to: 2187 /* 911 */ MCD_OPC_CheckField, 23, 9, 231, 3, 244, 4, 0, // Skip to: 2187 /* 919 */ MCD_OPC_CheckField, 4, 1, 0, 237, 4, 0, // Skip to: 2187 /* 926 */ MCD_OPC_Decode, 175, 9, 127, // Opcode: VCVTMNSQh /* 930 */ MCD_OPC_FilterValue, 59, 228, 4, 0, // Skip to: 2187 /* 935 */ MCD_OPC_CheckPredicate, 75, 223, 4, 0, // Skip to: 2187 /* 940 */ MCD_OPC_CheckField, 23, 9, 231, 3, 215, 4, 0, // Skip to: 2187 /* 948 */ MCD_OPC_CheckField, 4, 1, 0, 208, 4, 0, // Skip to: 2187 /* 955 */ MCD_OPC_Decode, 174, 9, 127, // Opcode: VCVTMNSQf /* 959 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1025 /* 964 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 967 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 996 /* 972 */ MCD_OPC_CheckPredicate, 74, 186, 4, 0, // Skip to: 2187 /* 977 */ MCD_OPC_CheckField, 23, 9, 231, 3, 178, 4, 0, // Skip to: 2187 /* 985 */ MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 2187 /* 992 */ MCD_OPC_Decode, 177, 9, 126, // Opcode: VCVTMNUDh /* 996 */ MCD_OPC_FilterValue, 59, 162, 4, 0, // Skip to: 2187 /* 1001 */ MCD_OPC_CheckPredicate, 75, 157, 4, 0, // Skip to: 2187 /* 1006 */ MCD_OPC_CheckField, 23, 9, 231, 3, 149, 4, 0, // Skip to: 2187 /* 1014 */ MCD_OPC_CheckField, 4, 1, 0, 142, 4, 0, // Skip to: 2187 /* 1021 */ MCD_OPC_Decode, 176, 9, 126, // Opcode: VCVTMNUDf /* 1025 */ MCD_OPC_FilterValue, 3, 133, 4, 0, // Skip to: 2187 /* 1030 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1033 */ MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1062 /* 1038 */ MCD_OPC_CheckPredicate, 74, 120, 4, 0, // Skip to: 2187 /* 1043 */ MCD_OPC_CheckField, 23, 9, 231, 3, 112, 4, 0, // Skip to: 2187 /* 1051 */ MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 2187 /* 1058 */ MCD_OPC_Decode, 179, 9, 127, // Opcode: VCVTMNUQh /* 1062 */ MCD_OPC_FilterValue, 59, 96, 4, 0, // Skip to: 2187 /* 1067 */ MCD_OPC_CheckPredicate, 75, 91, 4, 0, // Skip to: 2187 /* 1072 */ MCD_OPC_CheckField, 23, 9, 231, 3, 83, 4, 0, // Skip to: 2187 /* 1080 */ MCD_OPC_CheckField, 4, 1, 0, 76, 4, 0, // Skip to: 2187 /* 1087 */ MCD_OPC_Decode, 178, 9, 127, // Opcode: VCVTMNUQf /* 1091 */ MCD_OPC_FilterValue, 4, 11, 1, 0, // Skip to: 1363 /* 1096 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1099 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1165 /* 1104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1107 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1136 /* 1112 */ MCD_OPC_CheckPredicate, 74, 46, 4, 0, // Skip to: 2187 /* 1117 */ MCD_OPC_CheckField, 23, 9, 231, 3, 38, 4, 0, // Skip to: 2187 /* 1125 */ MCD_OPC_CheckField, 4, 1, 0, 31, 4, 0, // Skip to: 2187 /* 1132 */ MCD_OPC_Decode, 136, 17, 126, // Opcode: VRINTNNDh /* 1136 */ MCD_OPC_FilterValue, 58, 22, 4, 0, // Skip to: 2187 /* 1141 */ MCD_OPC_CheckPredicate, 75, 17, 4, 0, // Skip to: 2187 /* 1146 */ MCD_OPC_CheckField, 23, 9, 231, 3, 9, 4, 0, // Skip to: 2187 /* 1154 */ MCD_OPC_CheckField, 4, 1, 0, 2, 4, 0, // Skip to: 2187 /* 1161 */ MCD_OPC_Decode, 135, 17, 126, // Opcode: VRINTNNDf /* 1165 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1231 /* 1170 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1173 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1202 /* 1178 */ MCD_OPC_CheckPredicate, 74, 236, 3, 0, // Skip to: 2187 /* 1183 */ MCD_OPC_CheckField, 23, 9, 231, 3, 228, 3, 0, // Skip to: 2187 /* 1191 */ MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 2187 /* 1198 */ MCD_OPC_Decode, 138, 17, 127, // Opcode: VRINTNNQh /* 1202 */ MCD_OPC_FilterValue, 58, 212, 3, 0, // Skip to: 2187 /* 1207 */ MCD_OPC_CheckPredicate, 75, 207, 3, 0, // Skip to: 2187 /* 1212 */ MCD_OPC_CheckField, 23, 9, 231, 3, 199, 3, 0, // Skip to: 2187 /* 1220 */ MCD_OPC_CheckField, 4, 1, 0, 192, 3, 0, // Skip to: 2187 /* 1227 */ MCD_OPC_Decode, 137, 17, 127, // Opcode: VRINTNNQf /* 1231 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1297 /* 1236 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1239 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1268 /* 1244 */ MCD_OPC_CheckPredicate, 74, 170, 3, 0, // Skip to: 2187 /* 1249 */ MCD_OPC_CheckField, 23, 9, 231, 3, 162, 3, 0, // Skip to: 2187 /* 1257 */ MCD_OPC_CheckField, 4, 1, 0, 155, 3, 0, // Skip to: 2187 /* 1264 */ MCD_OPC_Decode, 153, 17, 126, // Opcode: VRINTXNDh /* 1268 */ MCD_OPC_FilterValue, 58, 146, 3, 0, // Skip to: 2187 /* 1273 */ MCD_OPC_CheckPredicate, 75, 141, 3, 0, // Skip to: 2187 /* 1278 */ MCD_OPC_CheckField, 23, 9, 231, 3, 133, 3, 0, // Skip to: 2187 /* 1286 */ MCD_OPC_CheckField, 4, 1, 0, 126, 3, 0, // Skip to: 2187 /* 1293 */ MCD_OPC_Decode, 152, 17, 126, // Opcode: VRINTXNDf /* 1297 */ MCD_OPC_FilterValue, 3, 117, 3, 0, // Skip to: 2187 /* 1302 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1305 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1334 /* 1310 */ MCD_OPC_CheckPredicate, 74, 104, 3, 0, // Skip to: 2187 /* 1315 */ MCD_OPC_CheckField, 23, 9, 231, 3, 96, 3, 0, // Skip to: 2187 /* 1323 */ MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 2187 /* 1330 */ MCD_OPC_Decode, 155, 17, 127, // Opcode: VRINTXNQh /* 1334 */ MCD_OPC_FilterValue, 58, 80, 3, 0, // Skip to: 2187 /* 1339 */ MCD_OPC_CheckPredicate, 75, 75, 3, 0, // Skip to: 2187 /* 1344 */ MCD_OPC_CheckField, 23, 9, 231, 3, 67, 3, 0, // Skip to: 2187 /* 1352 */ MCD_OPC_CheckField, 4, 1, 0, 60, 3, 0, // Skip to: 2187 /* 1359 */ MCD_OPC_Decode, 154, 17, 127, // Opcode: VRINTXNQf /* 1363 */ MCD_OPC_FilterValue, 5, 11, 1, 0, // Skip to: 1635 /* 1368 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1371 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1437 /* 1376 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1379 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1408 /* 1384 */ MCD_OPC_CheckPredicate, 74, 30, 3, 0, // Skip to: 2187 /* 1389 */ MCD_OPC_CheckField, 23, 9, 231, 3, 22, 3, 0, // Skip to: 2187 /* 1397 */ MCD_OPC_CheckField, 4, 1, 0, 15, 3, 0, // Skip to: 2187 /* 1404 */ MCD_OPC_Decode, 250, 16, 126, // Opcode: VRINTANDh /* 1408 */ MCD_OPC_FilterValue, 58, 6, 3, 0, // Skip to: 2187 /* 1413 */ MCD_OPC_CheckPredicate, 75, 1, 3, 0, // Skip to: 2187 /* 1418 */ MCD_OPC_CheckField, 23, 9, 231, 3, 249, 2, 0, // Skip to: 2187 /* 1426 */ MCD_OPC_CheckField, 4, 1, 0, 242, 2, 0, // Skip to: 2187 /* 1433 */ MCD_OPC_Decode, 249, 16, 126, // Opcode: VRINTANDf /* 1437 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1503 /* 1442 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1445 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1474 /* 1450 */ MCD_OPC_CheckPredicate, 74, 220, 2, 0, // Skip to: 2187 /* 1455 */ MCD_OPC_CheckField, 23, 9, 231, 3, 212, 2, 0, // Skip to: 2187 /* 1463 */ MCD_OPC_CheckField, 4, 1, 0, 205, 2, 0, // Skip to: 2187 /* 1470 */ MCD_OPC_Decode, 252, 16, 127, // Opcode: VRINTANQh /* 1474 */ MCD_OPC_FilterValue, 58, 196, 2, 0, // Skip to: 2187 /* 1479 */ MCD_OPC_CheckPredicate, 75, 191, 2, 0, // Skip to: 2187 /* 1484 */ MCD_OPC_CheckField, 23, 9, 231, 3, 183, 2, 0, // Skip to: 2187 /* 1492 */ MCD_OPC_CheckField, 4, 1, 0, 176, 2, 0, // Skip to: 2187 /* 1499 */ MCD_OPC_Decode, 251, 16, 127, // Opcode: VRINTANQf /* 1503 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1569 /* 1508 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1511 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1540 /* 1516 */ MCD_OPC_CheckPredicate, 74, 154, 2, 0, // Skip to: 2187 /* 1521 */ MCD_OPC_CheckField, 23, 9, 231, 3, 146, 2, 0, // Skip to: 2187 /* 1529 */ MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 2187 /* 1536 */ MCD_OPC_Decode, 160, 17, 126, // Opcode: VRINTZNDh /* 1540 */ MCD_OPC_FilterValue, 58, 130, 2, 0, // Skip to: 2187 /* 1545 */ MCD_OPC_CheckPredicate, 75, 125, 2, 0, // Skip to: 2187 /* 1550 */ MCD_OPC_CheckField, 23, 9, 231, 3, 117, 2, 0, // Skip to: 2187 /* 1558 */ MCD_OPC_CheckField, 4, 1, 0, 110, 2, 0, // Skip to: 2187 /* 1565 */ MCD_OPC_Decode, 159, 17, 126, // Opcode: VRINTZNDf /* 1569 */ MCD_OPC_FilterValue, 3, 101, 2, 0, // Skip to: 2187 /* 1574 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1577 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1606 /* 1582 */ MCD_OPC_CheckPredicate, 74, 88, 2, 0, // Skip to: 2187 /* 1587 */ MCD_OPC_CheckField, 23, 9, 231, 3, 80, 2, 0, // Skip to: 2187 /* 1595 */ MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 2187 /* 1602 */ MCD_OPC_Decode, 162, 17, 127, // Opcode: VRINTZNQh /* 1606 */ MCD_OPC_FilterValue, 58, 64, 2, 0, // Skip to: 2187 /* 1611 */ MCD_OPC_CheckPredicate, 75, 59, 2, 0, // Skip to: 2187 /* 1616 */ MCD_OPC_CheckField, 23, 9, 231, 3, 51, 2, 0, // Skip to: 2187 /* 1624 */ MCD_OPC_CheckField, 4, 1, 0, 44, 2, 0, // Skip to: 2187 /* 1631 */ MCD_OPC_Decode, 161, 17, 127, // Opcode: VRINTZNQf /* 1635 */ MCD_OPC_FilterValue, 6, 135, 0, 0, // Skip to: 1775 /* 1640 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1643 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1709 /* 1648 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1651 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1680 /* 1656 */ MCD_OPC_CheckPredicate, 74, 14, 2, 0, // Skip to: 2187 /* 1661 */ MCD_OPC_CheckField, 23, 9, 231, 3, 6, 2, 0, // Skip to: 2187 /* 1669 */ MCD_OPC_CheckField, 4, 1, 0, 255, 1, 0, // Skip to: 2187 /* 1676 */ MCD_OPC_Decode, 129, 17, 126, // Opcode: VRINTMNDh /* 1680 */ MCD_OPC_FilterValue, 58, 246, 1, 0, // Skip to: 2187 /* 1685 */ MCD_OPC_CheckPredicate, 75, 241, 1, 0, // Skip to: 2187 /* 1690 */ MCD_OPC_CheckField, 23, 9, 231, 3, 233, 1, 0, // Skip to: 2187 /* 1698 */ MCD_OPC_CheckField, 4, 1, 0, 226, 1, 0, // Skip to: 2187 /* 1705 */ MCD_OPC_Decode, 128, 17, 126, // Opcode: VRINTMNDf /* 1709 */ MCD_OPC_FilterValue, 3, 217, 1, 0, // Skip to: 2187 /* 1714 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1717 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1746 /* 1722 */ MCD_OPC_CheckPredicate, 74, 204, 1, 0, // Skip to: 2187 /* 1727 */ MCD_OPC_CheckField, 23, 9, 231, 3, 196, 1, 0, // Skip to: 2187 /* 1735 */ MCD_OPC_CheckField, 4, 1, 0, 189, 1, 0, // Skip to: 2187 /* 1742 */ MCD_OPC_Decode, 131, 17, 127, // Opcode: VRINTMNQh /* 1746 */ MCD_OPC_FilterValue, 58, 180, 1, 0, // Skip to: 2187 /* 1751 */ MCD_OPC_CheckPredicate, 75, 175, 1, 0, // Skip to: 2187 /* 1756 */ MCD_OPC_CheckField, 23, 9, 231, 3, 167, 1, 0, // Skip to: 2187 /* 1764 */ MCD_OPC_CheckField, 4, 1, 0, 160, 1, 0, // Skip to: 2187 /* 1771 */ MCD_OPC_Decode, 130, 17, 127, // Opcode: VRINTMNQf /* 1775 */ MCD_OPC_FilterValue, 7, 135, 0, 0, // Skip to: 1915 /* 1780 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 1783 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1849 /* 1788 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1791 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1820 /* 1796 */ MCD_OPC_CheckPredicate, 74, 130, 1, 0, // Skip to: 2187 /* 1801 */ MCD_OPC_CheckField, 23, 9, 231, 3, 122, 1, 0, // Skip to: 2187 /* 1809 */ MCD_OPC_CheckField, 4, 1, 0, 115, 1, 0, // Skip to: 2187 /* 1816 */ MCD_OPC_Decode, 143, 17, 126, // Opcode: VRINTPNDh /* 1820 */ MCD_OPC_FilterValue, 58, 106, 1, 0, // Skip to: 2187 /* 1825 */ MCD_OPC_CheckPredicate, 75, 101, 1, 0, // Skip to: 2187 /* 1830 */ MCD_OPC_CheckField, 23, 9, 231, 3, 93, 1, 0, // Skip to: 2187 /* 1838 */ MCD_OPC_CheckField, 4, 1, 0, 86, 1, 0, // Skip to: 2187 /* 1845 */ MCD_OPC_Decode, 142, 17, 126, // Opcode: VRINTPNDf /* 1849 */ MCD_OPC_FilterValue, 3, 77, 1, 0, // Skip to: 2187 /* 1854 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... /* 1857 */ MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1886 /* 1862 */ MCD_OPC_CheckPredicate, 74, 64, 1, 0, // Skip to: 2187 /* 1867 */ MCD_OPC_CheckField, 23, 9, 231, 3, 56, 1, 0, // Skip to: 2187 /* 1875 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2187 /* 1882 */ MCD_OPC_Decode, 145, 17, 127, // Opcode: VRINTPNQh /* 1886 */ MCD_OPC_FilterValue, 58, 40, 1, 0, // Skip to: 2187 /* 1891 */ MCD_OPC_CheckPredicate, 75, 35, 1, 0, // Skip to: 2187 /* 1896 */ MCD_OPC_CheckField, 23, 9, 231, 3, 27, 1, 0, // Skip to: 2187 /* 1904 */ MCD_OPC_CheckField, 4, 1, 0, 20, 1, 0, // Skip to: 2187 /* 1911 */ MCD_OPC_Decode, 144, 17, 127, // Opcode: VRINTPNQf /* 1915 */ MCD_OPC_FilterValue, 15, 11, 1, 0, // Skip to: 2187 /* 1920 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... /* 1923 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1989 /* 1928 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1931 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1960 /* 1936 */ MCD_OPC_CheckPredicate, 75, 246, 0, 0, // Skip to: 2187 /* 1941 */ MCD_OPC_CheckField, 23, 9, 230, 3, 238, 0, 0, // Skip to: 2187 /* 1949 */ MCD_OPC_CheckField, 4, 1, 1, 231, 0, 0, // Skip to: 2187 /* 1956 */ MCD_OPC_Decode, 158, 13, 97, // Opcode: VMAXNMNDf /* 1960 */ MCD_OPC_FilterValue, 1, 222, 0, 0, // Skip to: 2187 /* 1965 */ MCD_OPC_CheckPredicate, 75, 217, 0, 0, // Skip to: 2187 /* 1970 */ MCD_OPC_CheckField, 23, 9, 230, 3, 209, 0, 0, // Skip to: 2187 /* 1978 */ MCD_OPC_CheckField, 4, 1, 1, 202, 0, 0, // Skip to: 2187 /* 1985 */ MCD_OPC_Decode, 160, 13, 98, // Opcode: VMAXNMNQf /* 1989 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 2055 /* 1994 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 1997 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2026 /* 2002 */ MCD_OPC_CheckPredicate, 74, 180, 0, 0, // Skip to: 2187 /* 2007 */ MCD_OPC_CheckField, 23, 9, 230, 3, 172, 0, 0, // Skip to: 2187 /* 2015 */ MCD_OPC_CheckField, 4, 1, 1, 165, 0, 0, // Skip to: 2187 /* 2022 */ MCD_OPC_Decode, 159, 13, 97, // Opcode: VMAXNMNDh /* 2026 */ MCD_OPC_FilterValue, 1, 156, 0, 0, // Skip to: 2187 /* 2031 */ MCD_OPC_CheckPredicate, 74, 151, 0, 0, // Skip to: 2187 /* 2036 */ MCD_OPC_CheckField, 23, 9, 230, 3, 143, 0, 0, // Skip to: 2187 /* 2044 */ MCD_OPC_CheckField, 4, 1, 1, 136, 0, 0, // Skip to: 2187 /* 2051 */ MCD_OPC_Decode, 161, 13, 98, // Opcode: VMAXNMNQh /* 2055 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 2121 /* 2060 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2063 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2092 /* 2068 */ MCD_OPC_CheckPredicate, 75, 114, 0, 0, // Skip to: 2187 /* 2073 */ MCD_OPC_CheckField, 23, 9, 230, 3, 106, 0, 0, // Skip to: 2187 /* 2081 */ MCD_OPC_CheckField, 4, 1, 1, 99, 0, 0, // Skip to: 2187 /* 2088 */ MCD_OPC_Decode, 181, 13, 97, // Opcode: VMINNMNDf /* 2092 */ MCD_OPC_FilterValue, 1, 90, 0, 0, // Skip to: 2187 /* 2097 */ MCD_OPC_CheckPredicate, 75, 85, 0, 0, // Skip to: 2187 /* 2102 */ MCD_OPC_CheckField, 23, 9, 230, 3, 77, 0, 0, // Skip to: 2187 /* 2110 */ MCD_OPC_CheckField, 4, 1, 1, 70, 0, 0, // Skip to: 2187 /* 2117 */ MCD_OPC_Decode, 183, 13, 98, // Opcode: VMINNMNQf /* 2121 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 2187 /* 2126 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 2129 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2158 /* 2134 */ MCD_OPC_CheckPredicate, 74, 48, 0, 0, // Skip to: 2187 /* 2139 */ MCD_OPC_CheckField, 23, 9, 230, 3, 40, 0, 0, // Skip to: 2187 /* 2147 */ MCD_OPC_CheckField, 4, 1, 1, 33, 0, 0, // Skip to: 2187 /* 2154 */ MCD_OPC_Decode, 182, 13, 97, // Opcode: VMINNMNDh /* 2158 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2187 /* 2163 */ MCD_OPC_CheckPredicate, 74, 19, 0, 0, // Skip to: 2187 /* 2168 */ MCD_OPC_CheckField, 23, 9, 230, 3, 11, 0, 0, // Skip to: 2187 /* 2176 */ MCD_OPC_CheckField, 4, 1, 1, 4, 0, 0, // Skip to: 2187 /* 2183 */ MCD_OPC_Decode, 184, 13, 98, // Opcode: VMINNMNQh /* 2187 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) { switch (Idx) { default: /* llvm_unreachable("Invalid index!");*/ case 0: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb)); case 1: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops)); case 2: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC)); case 3: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TEOps)); case 4: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); case 5: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); case 6: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); case 7: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); case 8: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease)); case 9: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); case 10: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV4TOps)); case 11: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps)); case 12: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone)); case 13: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6T2Ops)); case 14: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps)); case 15: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)); case 16: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP)); case 17: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)); case 18: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB)); case 19: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivARM)); case 20: return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNaClTrap)); case 21: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON)); case 22: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); case 23: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); case 24: return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCrypto)); case 25: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16)); case 26: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4)); case 27: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2)); case 28: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb)); case 29: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); case 30: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps)); case 31: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops)); case 32: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps)); case 33: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps)); case 34: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); case 35: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); case 36: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)); case 37: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); case 38: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); case 39: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); case 40: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease)); case 41: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); case 42: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); case 43: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); case 44: return (ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); case 45: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)); case 46: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); case 47: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps)); case 48: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex)); case 49: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB)); case 50: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); case 51: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)); case 52: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone)); case 53: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)); case 54: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)); case 55: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps)); case 56: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP)); case 57: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC)); case 58: return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)); case 59: return (!ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)); case 60: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); case 61: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); case 62: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4)); case 63: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); case 64: return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MMainlineOps) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt)); case 65: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3)); case 66: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8)); case 67: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16)); case 68: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); case 69: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP)); case 70: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps)); case 71: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); case 72: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps)); case 73: return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDotProd)); case 74: return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16)); case 75: return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON)); } } #define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, bool *Decoder) \ { \ InsnType tmp; \ /* printf("Idx = %u\n", Idx); */\ switch (Idx) { \ default: /* llvm_unreachable("Invalid index!");*/ \ case 0: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 1: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 7) << 5; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 2: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 2) << 5; \ tmp |= fieldname(insn, 8, 4) << 8; \ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 3: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 2) << 5; \ tmp |= fieldname(insn, 8, 4) << 8; \ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 4: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 5: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 6: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 7: \ if (!Check(&S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 8: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 9: \ if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 10: \ tmp = fieldname(insn, 9, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 11: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 12: \ if (!Check(&S, DecodeQADDInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 13: \ if (!Check(&S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 14: \ if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 15: \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 8, 12) << 4; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 16: \ if (!Check(&S, DecodeTSTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 17: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 7) << 5; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 18: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 2) << 5; \ tmp |= fieldname(insn, 8, 4) << 8; \ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 19: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 20: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 21: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 22: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 23: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 24: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 25: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 5; \ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 26: \ tmp = 0; \ tmp |= fieldname(insn, 16, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 27: \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 5; \ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 28: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 29: \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 30: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 31: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 32: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 33: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 7) << 5; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 34: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 35: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 36: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 37: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 2) << 5; \ tmp |= fieldname(insn, 8, 4) << 8; \ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 38: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 39: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 40: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 41: \ if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 42: \ if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 43: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 23, 1) << 4; \ if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 44: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 8, 4) << 4; \ tmp |= fieldname(insn, 23, 1) << 8; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 45: \ if (!Check(&S, DecodeLDR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 46: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 8, 4) << 4; \ tmp |= fieldname(insn, 23, 1) << 8; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 47: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 12); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 48: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 22, 2) << 12; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 49: \ if (!Check(&S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 50: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 12); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 51: \ return S; \ case 52: \ if (!Check(&S, DecodeHINTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 53: \ tmp = 0; \ tmp |= fieldname(insn, 16, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 12); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 54: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 12); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 55: \ if (!Check(&S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 56: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 16, 4) << 13; \ tmp |= fieldname(insn, 23, 1) << 12; \ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 57: \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 16, 4) << 13; \ tmp |= fieldname(insn, 23, 1) << 12; \ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 58: \ if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 59: \ if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 60: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 16, 4) << 13; \ tmp |= fieldname(insn, 23, 1) << 12; \ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 61: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 62: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 63: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 7) << 5; \ tmp |= fieldname(insn, 16, 4) << 13; \ tmp |= fieldname(insn, 23, 1) << 12; \ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 64: \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 7) << 5; \ tmp |= fieldname(insn, 16, 4) << 13; \ tmp |= fieldname(insn, 23, 1) << 12; \ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 65: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 66: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 7, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 67: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 68: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 69: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 70: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 2); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 71: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 2); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 72: \ if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 73: \ if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 74: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 1) << 5; \ tmp |= fieldname(insn, 7, 5) << 0; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 75: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 76: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 7, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 77: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 7) << 5; \ tmp |= fieldname(insn, 16, 4) << 13; \ tmp |= fieldname(insn, 23, 1) << 12; \ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 78: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 5; \ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 79: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 5; \ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 80: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 81: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 82: \ if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 83: \ tmp = fieldname(insn, 0, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 84: \ if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 85: \ tmp = 0; \ tmp |= fieldname(insn, 0, 24) << 1; \ tmp |= fieldname(insn, 24, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 86: \ if (!Check(&S, DecoderForMRRC2AndMCRR2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 87: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 88: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 89: \ tmp = fieldname(insn, 0, 24); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 90: \ if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 91: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 92: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 93: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 94: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 95: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 96: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 97: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 98: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 99: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 100: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 101: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 102: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 103: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 104: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 105: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 106: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 107: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 0; \ tmp |= fieldname(insn, 5, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 108: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 0; \ tmp |= fieldname(insn, 5, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 109: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 0; \ tmp |= fieldname(insn, 5, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 110: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 0; \ tmp |= fieldname(insn, 5, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 111: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 0; \ tmp |= fieldname(insn, 5, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 112: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 0; \ tmp |= fieldname(insn, 5, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 113: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 114: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 115: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 116: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 117: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 118: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 119: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 120: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 121: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 122: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 123: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 124: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 125: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 126: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 127: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 128: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 129: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 130: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 131: \ if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 132: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 133: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 134: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 135: \ if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 136: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 137: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 138: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 139: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 140: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 141: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 17, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 142: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 143: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 144: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 145: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 146: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 147: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 148: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 149: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 150: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 151: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 152: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 153: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 154: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 155: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 156: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 157: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 158: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 159: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 160: \ if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 161: \ if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 162: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 163: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 164: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 165: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 166: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 167: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 168: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 169: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 170: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 171: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 172: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 173: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 174: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 175: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 176: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 177: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 178: \ if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 179: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 180: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 181: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 182: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 183: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 184: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 185: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 1) << 0; \ tmp |= fieldname(insn, 21, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 186: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 1) << 0; \ tmp |= fieldname(insn, 21, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 187: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 2) << 0; \ tmp |= fieldname(insn, 21, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 188: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 2) << 0; \ tmp |= fieldname(insn, 21, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 189: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 190: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 191: \ if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 192: \ if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 193: \ if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 194: \ if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 195: \ if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 196: \ if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 197: \ if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 198: \ if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 199: \ if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 200: \ if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 201: \ if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 202: \ if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 203: \ if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 204: \ if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 205: \ if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 206: \ if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 207: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 208: \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 209: \ if (!Check(&S, DecodeThumbAddSPReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 210: \ tmp = 0; \ tmp |= fieldname(insn, 0, 3) << 0; \ tmp |= fieldname(insn, 7, 1) << 3; \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 3) << 0; \ tmp |= fieldname(insn, 7, 1) << 3; \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 211: \ tmp = 0; \ tmp |= fieldname(insn, 0, 3) << 0; \ tmp |= fieldname(insn, 7, 1) << 3; \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 212: \ tmp = fieldname(insn, 3, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 213: \ tmp = fieldname(insn, 3, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 214: \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 215: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 6); \ if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 216: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 8); \ if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 217: \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 218: \ if (!Check(&S, DecodeThumbAddSpecialReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 219: \ if (!Check(&S, DecodeThumbAddSPImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 220: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 5) << 0; \ tmp |= fieldname(insn, 9, 1) << 5; \ if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 221: \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 8, 1) << 14; \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 222: \ tmp = fieldname(insn, 3, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 223: \ if (!Check(&S, DecodeThumbCPS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 224: \ tmp = fieldname(insn, 0, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 225: \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 8, 1) << 15; \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 226: \ tmp = fieldname(insn, 0, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 227: \ tmp = fieldname(insn, 4, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 228: \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 229: \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 230: \ tmp = fieldname(insn, 0, 8); \ if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 231: \ tmp = fieldname(insn, 0, 11); \ if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 232: \ tmp = 0; \ tmp |= fieldname(insn, 1, 10) << 1; \ tmp |= fieldname(insn, 11, 1) << 21; \ tmp |= fieldname(insn, 13, 1) << 22; \ tmp |= fieldname(insn, 16, 10) << 11; \ tmp |= fieldname(insn, 26, 1) << 23; \ if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 233: \ tmp = 0; \ tmp |= fieldname(insn, 0, 11) << 0; \ tmp |= fieldname(insn, 11, 1) << 21; \ tmp |= fieldname(insn, 13, 1) << 22; \ tmp |= fieldname(insn, 16, 10) << 11; \ tmp |= fieldname(insn, 26, 1) << 23; \ if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 234: \ if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 235: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 13) << 0; \ tmp |= fieldname(insn, 14, 1) << 14; \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 236: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 237: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 238: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 4, 4) << 5; \ tmp |= fieldname(insn, 12, 3) << 9; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 239: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 240: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 4, 4) << 5; \ tmp |= fieldname(insn, 12, 3) << 9; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 241: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 242: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 4, 4) << 5; \ tmp |= fieldname(insn, 12, 3) << 9; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 243: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 13) << 0; \ tmp |= fieldname(insn, 14, 1) << 14; \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 244: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 245: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 246: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 8; \ if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 247: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 248: \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 249: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 250: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 8; \ if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 251: \ if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 252: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 253: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 9; \ tmp |= fieldname(insn, 23, 1) << 8; \ if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 254: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 255: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 256: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 2) << 0; \ tmp |= fieldname(insn, 12, 3) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 257: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 2) << 0; \ tmp |= fieldname(insn, 12, 3) << 2; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 258: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 23, 1) << 8; \ if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 259: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 23, 1) << 8; \ if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 260: \ if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 261: \ if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 262: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 4, 4) << 5; \ tmp |= fieldname(insn, 12, 3) << 9; \ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 263: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 3) << 8; \ tmp |= fieldname(insn, 26, 1) << 11; \ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 264: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 3) << 8; \ tmp |= fieldname(insn, 26, 1) << 11; \ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 265: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 3) << 8; \ tmp |= fieldname(insn, 26, 1) << 11; \ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 266: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 3) << 8; \ tmp |= fieldname(insn, 26, 1) << 11; \ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 20, 1); \ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 267: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 3) << 8; \ tmp |= fieldname(insn, 26, 1) << 11; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 268: \ if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 269: \ if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 270: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 271: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 2) << 0; \ tmp |= fieldname(insn, 12, 3) << 2; \ tmp |= fieldname(insn, 21, 1) << 5; \ if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 272: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 6, 2) << 0; \ tmp |= fieldname(insn, 12, 3) << 2; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 273: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 5) << 5; \ tmp |= fieldname(insn, 6, 2) << 0; \ tmp |= fieldname(insn, 12, 3) << 2; \ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 274: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 5) << 5; \ tmp |= fieldname(insn, 6, 2) << 0; \ tmp |= fieldname(insn, 12, 3) << 2; \ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 275: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 276: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 277: \ if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 278: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 279: \ tmp = 0; \ tmp |= fieldname(insn, 8, 4) << 0; \ tmp |= fieldname(insn, 20, 1) << 4; \ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 280: \ tmp = 0; \ tmp |= fieldname(insn, 4, 1) << 4; \ tmp |= fieldname(insn, 8, 4) << 0; \ tmp |= fieldname(insn, 20, 1) << 5; \ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 281: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 4, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ tmp |= fieldname(insn, 20, 1) << 5; \ if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 282: \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 16, 4) << 12; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 283: \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 284: \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 10, 2) << 10; \ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 285: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 286: \ if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 287: \ if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 288: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 2; \ tmp |= fieldname(insn, 4, 2) << 0; \ tmp |= fieldname(insn, 16, 4) << 6; \ if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 289: \ if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 290: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 9; \ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 291: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 9, 1) << 8; \ tmp |= fieldname(insn, 16, 4) << 9; \ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 292: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 16, 4) << 13; \ if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 293: \ if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 294: \ if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 295: \ if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 296: \ if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 297: \ if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 298: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 299: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 300: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 301: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 302: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 303: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 304: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 305: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 306: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 2; \ tmp |= fieldname(insn, 4, 2) << 0; \ tmp |= fieldname(insn, 16, 4) << 6; \ if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 307: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 9, 1) << 8; \ tmp |= fieldname(insn, 16, 4) << 9; \ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 308: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 12) << 0; \ tmp |= fieldname(insn, 16, 4) << 13; \ if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 309: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 310: \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 311: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 4); \ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 312: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 313: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 314: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 315: \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 316: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 317: \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 3, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 318: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 9; \ tmp |= fieldname(insn, 23, 1) << 8; \ if (!Check(&S, DecodeAddrMode5FP16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 319: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 320: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 321: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 322: \ if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 323: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 4) << 9; \ tmp |= fieldname(insn, 22, 1) << 8; \ if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 324: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 9; \ tmp |= fieldname(insn, 23, 1) << 8; \ if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 325: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 326: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 327: \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 328: \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 329: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 7) << 1; \ tmp |= fieldname(insn, 12, 4) << 8; \ tmp |= fieldname(insn, 22, 1) << 12; \ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 330: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 7) << 1; \ tmp |= fieldname(insn, 12, 4) << 8; \ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 331: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 16, 4) << 9; \ tmp |= fieldname(insn, 23, 1) << 8; \ if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 332: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 333: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 334: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 335: \ if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 336: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 337: \ tmp = fieldname(insn, 12, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 338: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 339: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 8) << 0; \ tmp |= fieldname(insn, 12, 4) << 9; \ tmp |= fieldname(insn, 22, 1) << 8; \ if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 340: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 7) << 1; \ tmp |= fieldname(insn, 12, 4) << 8; \ tmp |= fieldname(insn, 22, 1) << 12; \ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 341: \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 7) << 1; \ tmp |= fieldname(insn, 12, 4) << 8; \ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 342: \ if (!Check(&S, DecodeForVMRSandVMSR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 343: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 16, 4) << 4; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 344: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 345: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 346: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 347: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 348: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 349: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 350: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 16, 4) << 4; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 351: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 352: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 353: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 16, 4) << 4; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 354: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 355: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 356: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 357: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 28, 4); \ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 358: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 359: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 23, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 360: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 20, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 361: \ if (!Check(&S, DecodeNEONComplexLane64Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 362: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 24, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 363: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 23, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 364: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 0; \ tmp |= fieldname(insn, 22, 1) << 4; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 4; \ tmp |= fieldname(insn, 16, 4) << 0; \ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 4); \ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 20, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 365: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 366: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 367: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 368: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 16, 4) << 1; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 1; \ tmp |= fieldname(insn, 5, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 369: \ tmp = 0; \ tmp |= fieldname(insn, 12, 4) << 1; \ tmp |= fieldname(insn, 22, 1) << 0; \ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 4) << 0; \ tmp |= fieldname(insn, 5, 1) << 4; \ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address) \ { \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail, DecodeComplete = true; \ uint32_t ExpectedValue; \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ /* Decode the field value. */ \ Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ /* Decode the field value. */ \ ExpectedValue = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ /* Decode the Predicate Index value. */ \ PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Check the predicate. */ \ if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ Ptr += NumToSkip; \ /* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ /* Decode the Opcode value. */ \ Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_clear(MI); \ MCInst_setOpcode(MI, Opc); \ S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ /* assert(DecodeComplete); */ \ return S; \ } \ case MCD_OPC_TryDecode: { \ /* Decode the Opcode value. */ \ Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Perform the decode operation. */ \ MCInst_setOpcode(MI, Opc); \ S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ if (DecodeComplete) { \ /* Decoding complete. */ \ return S; \ } else { \ /* assert(S == MCDisassembler_Fail); */ \ /* If the decoding was incomplete, skip. */ \ Ptr += NumToSkip; \ /* Reset decode status. This also drops a SoftFail status that could be */ \ /* set before the decode attempt. */ \ S = MCDisassembler_Success; \ } \ break; \ } \ case MCD_OPC_SoftFail: { \ /* Decode the mask values. */ \ PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ } FieldFromInstruction(fieldFromInstruction_2, uint16_t) DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) capstone-sys-0.15.0/capstone/arch/ARM/ARMGenInstrInfo.inc000064400000000000000000010615160072674642500211510ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { ARM_PHI = 0, ARM_INLINEASM = 1, ARM_CFI_INSTRUCTION = 2, ARM_EH_LABEL = 3, ARM_GC_LABEL = 4, ARM_ANNOTATION_LABEL = 5, ARM_KILL = 6, ARM_EXTRACT_SUBREG = 7, ARM_INSERT_SUBREG = 8, ARM_IMPLICIT_DEF = 9, ARM_SUBREG_TO_REG = 10, ARM_COPY_TO_REGCLASS = 11, ARM_DBG_VALUE = 12, ARM_DBG_LABEL = 13, ARM_REG_SEQUENCE = 14, ARM_COPY = 15, ARM_BUNDLE = 16, ARM_LIFETIME_START = 17, ARM_LIFETIME_END = 18, ARM_STACKMAP = 19, ARM_FENTRY_CALL = 20, ARM_PATCHPOINT = 21, ARM_LOAD_STACK_GUARD = 22, ARM_STATEPOINT = 23, ARM_LOCAL_ESCAPE = 24, ARM_FAULTING_OP = 25, ARM_PATCHABLE_OP = 26, ARM_PATCHABLE_FUNCTION_ENTER = 27, ARM_PATCHABLE_RET = 28, ARM_PATCHABLE_FUNCTION_EXIT = 29, ARM_PATCHABLE_TAIL_CALL = 30, ARM_PATCHABLE_EVENT_CALL = 31, ARM_PATCHABLE_TYPED_EVENT_CALL = 32, ARM_ICALL_BRANCH_FUNNEL = 33, ARM_G_ADD = 34, ARM_G_SUB = 35, ARM_G_MUL = 36, ARM_G_SDIV = 37, ARM_G_UDIV = 38, ARM_G_SREM = 39, ARM_G_UREM = 40, ARM_G_AND = 41, ARM_G_OR = 42, ARM_G_XOR = 43, ARM_G_IMPLICIT_DEF = 44, ARM_G_PHI = 45, ARM_G_FRAME_INDEX = 46, ARM_G_GLOBAL_VALUE = 47, ARM_G_EXTRACT = 48, ARM_G_UNMERGE_VALUES = 49, ARM_G_INSERT = 50, ARM_G_MERGE_VALUES = 51, ARM_G_PTRTOINT = 52, ARM_G_INTTOPTR = 53, ARM_G_BITCAST = 54, ARM_G_LOAD = 55, ARM_G_SEXTLOAD = 56, ARM_G_ZEXTLOAD = 57, ARM_G_STORE = 58, ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, ARM_G_ATOMIC_CMPXCHG = 60, ARM_G_ATOMICRMW_XCHG = 61, ARM_G_ATOMICRMW_ADD = 62, ARM_G_ATOMICRMW_SUB = 63, ARM_G_ATOMICRMW_AND = 64, ARM_G_ATOMICRMW_NAND = 65, ARM_G_ATOMICRMW_OR = 66, ARM_G_ATOMICRMW_XOR = 67, ARM_G_ATOMICRMW_MAX = 68, ARM_G_ATOMICRMW_MIN = 69, ARM_G_ATOMICRMW_UMAX = 70, ARM_G_ATOMICRMW_UMIN = 71, ARM_G_BRCOND = 72, ARM_G_BRINDIRECT = 73, ARM_G_INTRINSIC = 74, ARM_G_INTRINSIC_W_SIDE_EFFECTS = 75, ARM_G_ANYEXT = 76, ARM_G_TRUNC = 77, ARM_G_CONSTANT = 78, ARM_G_FCONSTANT = 79, ARM_G_VASTART = 80, ARM_G_VAARG = 81, ARM_G_SEXT = 82, ARM_G_ZEXT = 83, ARM_G_SHL = 84, ARM_G_LSHR = 85, ARM_G_ASHR = 86, ARM_G_ICMP = 87, ARM_G_FCMP = 88, ARM_G_SELECT = 89, ARM_G_UADDE = 90, ARM_G_USUBE = 91, ARM_G_SADDO = 92, ARM_G_SSUBO = 93, ARM_G_UMULO = 94, ARM_G_SMULO = 95, ARM_G_UMULH = 96, ARM_G_SMULH = 97, ARM_G_FADD = 98, ARM_G_FSUB = 99, ARM_G_FMUL = 100, ARM_G_FMA = 101, ARM_G_FDIV = 102, ARM_G_FREM = 103, ARM_G_FPOW = 104, ARM_G_FEXP = 105, ARM_G_FEXP2 = 106, ARM_G_FLOG = 107, ARM_G_FLOG2 = 108, ARM_G_FNEG = 109, ARM_G_FPEXT = 110, ARM_G_FPTRUNC = 111, ARM_G_FPTOSI = 112, ARM_G_FPTOUI = 113, ARM_G_SITOFP = 114, ARM_G_UITOFP = 115, ARM_G_FABS = 116, ARM_G_GEP = 117, ARM_G_PTR_MASK = 118, ARM_G_BR = 119, ARM_G_INSERT_VECTOR_ELT = 120, ARM_G_EXTRACT_VECTOR_ELT = 121, ARM_G_SHUFFLE_VECTOR = 122, ARM_G_BSWAP = 123, ARM_G_ADDRSPACE_CAST = 124, ARM_G_BLOCK_ADDR = 125, ARM_ABS = 126, ARM_ADDSri = 127, ARM_ADDSrr = 128, ARM_ADDSrsi = 129, ARM_ADDSrsr = 130, ARM_ADJCALLSTACKDOWN = 131, ARM_ADJCALLSTACKUP = 132, ARM_ASRi = 133, ARM_ASRr = 134, ARM_B = 135, ARM_BCCZi64 = 136, ARM_BCCi64 = 137, ARM_BMOVPCB_CALL = 138, ARM_BMOVPCRX_CALL = 139, ARM_BR_JTadd = 140, ARM_BR_JTm_i12 = 141, ARM_BR_JTm_rs = 142, ARM_BR_JTr = 143, ARM_BX_CALL = 144, ARM_CMP_SWAP_16 = 145, ARM_CMP_SWAP_32 = 146, ARM_CMP_SWAP_64 = 147, ARM_CMP_SWAP_8 = 148, ARM_CONSTPOOL_ENTRY = 149, ARM_COPY_STRUCT_BYVAL_I32 = 150, ARM_CompilerBarrier = 151, ARM_ITasm = 152, ARM_Int_eh_sjlj_dispatchsetup = 153, ARM_Int_eh_sjlj_setup_dispatch = 157, ARM_JUMPTABLE_ADDRS = 158, ARM_JUMPTABLE_INSTS = 159, ARM_JUMPTABLE_TBB = 160, ARM_JUMPTABLE_TBH = 161, ARM_LDMIA_RET = 162, ARM_LDRBT_POST = 163, ARM_LDRConstPool = 164, ARM_LDRLIT_ga_abs = 165, ARM_LDRLIT_ga_pcrel = 166, ARM_LDRLIT_ga_pcrel_ldr = 167, ARM_LDRT_POST = 168, ARM_LEApcrel = 169, ARM_LEApcrelJT = 170, ARM_LSLi = 171, ARM_LSLr = 172, ARM_LSRi = 173, ARM_LSRr = 174, ARM_MEMCPY = 175, ARM_MLAv5 = 176, ARM_MOVCCi = 177, ARM_MOVCCi16 = 178, ARM_MOVCCi32imm = 179, ARM_MOVCCr = 180, ARM_MOVCCsi = 181, ARM_MOVCCsr = 182, ARM_MOVPCRX = 183, ARM_MOVTi16_ga_pcrel = 184, ARM_MOV_ga_pcrel = 185, ARM_MOV_ga_pcrel_ldr = 186, ARM_MOVi16_ga_pcrel = 187, ARM_MOVi32imm = 188, ARM_MOVsra_flag = 189, ARM_MOVsrl_flag = 190, ARM_MULv5 = 191, ARM_MVNCCi = 192, ARM_PICADD = 193, ARM_PICLDR = 194, ARM_PICLDRB = 195, ARM_PICLDRH = 196, ARM_PICLDRSB = 197, ARM_PICLDRSH = 198, ARM_PICSTR = 199, ARM_PICSTRB = 200, ARM_PICSTRH = 201, ARM_RORi = 202, ARM_RORr = 203, ARM_RRX = 204, ARM_RRXi = 205, ARM_RSBSri = 206, ARM_RSBSrsi = 207, ARM_RSBSrsr = 208, ARM_SMLALv5 = 209, ARM_SMULLv5 = 210, ARM_SPACE = 211, ARM_STRBT_POST = 212, ARM_STRBi_preidx = 213, ARM_STRBr_preidx = 214, ARM_STRH_preidx = 215, ARM_STRT_POST = 216, ARM_STRi_preidx = 217, ARM_STRr_preidx = 218, ARM_SUBS_PC_LR = 219, ARM_SUBSri = 220, ARM_SUBSrr = 221, ARM_SUBSrsi = 222, ARM_SUBSrsr = 223, ARM_TAILJMPd = 224, ARM_TAILJMPr = 225, ARM_TAILJMPr4 = 226, ARM_TCRETURNdi = 227, ARM_TCRETURNri = 228, ARM_TPsoft = 229, ARM_UMLALv5 = 230, ARM_UMULLv5 = 231, ARM_VLD1LNdAsm_16 = 232, ARM_VLD1LNdAsm_32 = 233, ARM_VLD1LNdAsm_8 = 234, ARM_VLD1LNdWB_fixed_Asm_16 = 235, ARM_VLD1LNdWB_fixed_Asm_32 = 236, ARM_VLD1LNdWB_fixed_Asm_8 = 237, ARM_VLD1LNdWB_register_Asm_16 = 238, ARM_VLD1LNdWB_register_Asm_32 = 239, ARM_VLD1LNdWB_register_Asm_8 = 240, ARM_VLD2LNdAsm_16 = 241, ARM_VLD2LNdAsm_32 = 242, ARM_VLD2LNdAsm_8 = 243, ARM_VLD2LNdWB_fixed_Asm_16 = 244, ARM_VLD2LNdWB_fixed_Asm_32 = 245, ARM_VLD2LNdWB_fixed_Asm_8 = 246, ARM_VLD2LNdWB_register_Asm_16 = 247, ARM_VLD2LNdWB_register_Asm_32 = 248, ARM_VLD2LNdWB_register_Asm_8 = 249, ARM_VLD2LNqAsm_16 = 250, ARM_VLD2LNqAsm_32 = 251, ARM_VLD2LNqWB_fixed_Asm_16 = 252, ARM_VLD2LNqWB_fixed_Asm_32 = 253, ARM_VLD2LNqWB_register_Asm_16 = 254, ARM_VLD2LNqWB_register_Asm_32 = 255, ARM_VLD3DUPdAsm_16 = 256, ARM_VLD3DUPdAsm_32 = 257, ARM_VLD3DUPdAsm_8 = 258, ARM_VLD3DUPdWB_fixed_Asm_16 = 259, ARM_VLD3DUPdWB_fixed_Asm_32 = 260, ARM_VLD3DUPdWB_fixed_Asm_8 = 261, ARM_VLD3DUPdWB_register_Asm_16 = 262, ARM_VLD3DUPdWB_register_Asm_32 = 263, ARM_VLD3DUPdWB_register_Asm_8 = 264, ARM_VLD3DUPqAsm_16 = 265, ARM_VLD3DUPqAsm_32 = 266, ARM_VLD3DUPqAsm_8 = 267, ARM_VLD3DUPqWB_fixed_Asm_16 = 268, ARM_VLD3DUPqWB_fixed_Asm_32 = 269, ARM_VLD3DUPqWB_fixed_Asm_8 = 270, ARM_VLD3DUPqWB_register_Asm_16 = 271, ARM_VLD3DUPqWB_register_Asm_32 = 272, ARM_VLD3DUPqWB_register_Asm_8 = 273, ARM_VLD3LNdAsm_16 = 274, ARM_VLD3LNdAsm_32 = 275, ARM_VLD3LNdAsm_8 = 276, ARM_VLD3LNdWB_fixed_Asm_16 = 277, ARM_VLD3LNdWB_fixed_Asm_32 = 278, ARM_VLD3LNdWB_fixed_Asm_8 = 279, ARM_VLD3LNdWB_register_Asm_16 = 280, ARM_VLD3LNdWB_register_Asm_32 = 281, ARM_VLD3LNdWB_register_Asm_8 = 282, ARM_VLD3LNqAsm_16 = 283, ARM_VLD3LNqAsm_32 = 284, ARM_VLD3LNqWB_fixed_Asm_16 = 285, ARM_VLD3LNqWB_fixed_Asm_32 = 286, ARM_VLD3LNqWB_register_Asm_16 = 287, ARM_VLD3LNqWB_register_Asm_32 = 288, ARM_VLD3dAsm_16 = 289, ARM_VLD3dAsm_32 = 290, ARM_VLD3dAsm_8 = 291, ARM_VLD3dWB_fixed_Asm_16 = 292, ARM_VLD3dWB_fixed_Asm_32 = 293, ARM_VLD3dWB_fixed_Asm_8 = 294, ARM_VLD3dWB_register_Asm_16 = 295, ARM_VLD3dWB_register_Asm_32 = 296, ARM_VLD3dWB_register_Asm_8 = 297, ARM_VLD3qAsm_16 = 298, ARM_VLD3qAsm_32 = 299, ARM_VLD3qAsm_8 = 300, ARM_VLD3qWB_fixed_Asm_16 = 301, ARM_VLD3qWB_fixed_Asm_32 = 302, ARM_VLD3qWB_fixed_Asm_8 = 303, ARM_VLD3qWB_register_Asm_16 = 304, ARM_VLD3qWB_register_Asm_32 = 305, ARM_VLD3qWB_register_Asm_8 = 306, ARM_VLD4DUPdAsm_16 = 307, ARM_VLD4DUPdAsm_32 = 308, ARM_VLD4DUPdAsm_8 = 309, ARM_VLD4DUPdWB_fixed_Asm_16 = 310, ARM_VLD4DUPdWB_fixed_Asm_32 = 311, ARM_VLD4DUPdWB_fixed_Asm_8 = 312, ARM_VLD4DUPdWB_register_Asm_16 = 313, ARM_VLD4DUPdWB_register_Asm_32 = 314, ARM_VLD4DUPdWB_register_Asm_8 = 315, ARM_VLD4DUPqAsm_16 = 316, ARM_VLD4DUPqAsm_32 = 317, ARM_VLD4DUPqAsm_8 = 318, ARM_VLD4DUPqWB_fixed_Asm_16 = 319, ARM_VLD4DUPqWB_fixed_Asm_32 = 320, ARM_VLD4DUPqWB_fixed_Asm_8 = 321, ARM_VLD4DUPqWB_register_Asm_16 = 322, ARM_VLD4DUPqWB_register_Asm_32 = 323, ARM_VLD4DUPqWB_register_Asm_8 = 324, ARM_VLD4LNdAsm_16 = 325, ARM_VLD4LNdAsm_32 = 326, ARM_VLD4LNdAsm_8 = 327, ARM_VLD4LNdWB_fixed_Asm_16 = 328, ARM_VLD4LNdWB_fixed_Asm_32 = 329, ARM_VLD4LNdWB_fixed_Asm_8 = 330, ARM_VLD4LNdWB_register_Asm_16 = 331, ARM_VLD4LNdWB_register_Asm_32 = 332, ARM_VLD4LNdWB_register_Asm_8 = 333, ARM_VLD4LNqAsm_16 = 334, ARM_VLD4LNqAsm_32 = 335, ARM_VLD4LNqWB_fixed_Asm_16 = 336, ARM_VLD4LNqWB_fixed_Asm_32 = 337, ARM_VLD4LNqWB_register_Asm_16 = 338, ARM_VLD4LNqWB_register_Asm_32 = 339, ARM_VLD4dAsm_16 = 340, ARM_VLD4dAsm_32 = 341, ARM_VLD4dAsm_8 = 342, ARM_VLD4dWB_fixed_Asm_16 = 343, ARM_VLD4dWB_fixed_Asm_32 = 344, ARM_VLD4dWB_fixed_Asm_8 = 345, ARM_VLD4dWB_register_Asm_16 = 346, ARM_VLD4dWB_register_Asm_32 = 347, ARM_VLD4dWB_register_Asm_8 = 348, ARM_VLD4qAsm_16 = 349, ARM_VLD4qAsm_32 = 350, ARM_VLD4qAsm_8 = 351, ARM_VLD4qWB_fixed_Asm_16 = 352, ARM_VLD4qWB_fixed_Asm_32 = 353, ARM_VLD4qWB_fixed_Asm_8 = 354, ARM_VLD4qWB_register_Asm_16 = 355, ARM_VLD4qWB_register_Asm_32 = 356, ARM_VLD4qWB_register_Asm_8 = 357, ARM_VMOVD0 = 358, ARM_VMOVDcc = 359, ARM_VMOVQ0 = 360, ARM_VMOVScc = 361, ARM_VST1LNdAsm_16 = 362, ARM_VST1LNdAsm_32 = 363, ARM_VST1LNdAsm_8 = 364, ARM_VST1LNdWB_fixed_Asm_16 = 365, ARM_VST1LNdWB_fixed_Asm_32 = 366, ARM_VST1LNdWB_fixed_Asm_8 = 367, ARM_VST1LNdWB_register_Asm_16 = 368, ARM_VST1LNdWB_register_Asm_32 = 369, ARM_VST1LNdWB_register_Asm_8 = 370, ARM_VST2LNdAsm_16 = 371, ARM_VST2LNdAsm_32 = 372, ARM_VST2LNdAsm_8 = 373, ARM_VST2LNdWB_fixed_Asm_16 = 374, ARM_VST2LNdWB_fixed_Asm_32 = 375, ARM_VST2LNdWB_fixed_Asm_8 = 376, ARM_VST2LNdWB_register_Asm_16 = 377, ARM_VST2LNdWB_register_Asm_32 = 378, ARM_VST2LNdWB_register_Asm_8 = 379, ARM_VST2LNqAsm_16 = 380, ARM_VST2LNqAsm_32 = 381, ARM_VST2LNqWB_fixed_Asm_16 = 382, ARM_VST2LNqWB_fixed_Asm_32 = 383, ARM_VST2LNqWB_register_Asm_16 = 384, ARM_VST2LNqWB_register_Asm_32 = 385, ARM_VST3LNdAsm_16 = 386, ARM_VST3LNdAsm_32 = 387, ARM_VST3LNdAsm_8 = 388, ARM_VST3LNdWB_fixed_Asm_16 = 389, ARM_VST3LNdWB_fixed_Asm_32 = 390, ARM_VST3LNdWB_fixed_Asm_8 = 391, ARM_VST3LNdWB_register_Asm_16 = 392, ARM_VST3LNdWB_register_Asm_32 = 393, ARM_VST3LNdWB_register_Asm_8 = 394, ARM_VST3LNqAsm_16 = 395, ARM_VST3LNqAsm_32 = 396, ARM_VST3LNqWB_fixed_Asm_16 = 397, ARM_VST3LNqWB_fixed_Asm_32 = 398, ARM_VST3LNqWB_register_Asm_16 = 399, ARM_VST3LNqWB_register_Asm_32 = 400, ARM_VST3dAsm_16 = 401, ARM_VST3dAsm_32 = 402, ARM_VST3dAsm_8 = 403, ARM_VST3dWB_fixed_Asm_16 = 404, ARM_VST3dWB_fixed_Asm_32 = 405, ARM_VST3dWB_fixed_Asm_8 = 406, ARM_VST3dWB_register_Asm_16 = 407, ARM_VST3dWB_register_Asm_32 = 408, ARM_VST3dWB_register_Asm_8 = 409, ARM_VST3qAsm_16 = 410, ARM_VST3qAsm_32 = 411, ARM_VST3qAsm_8 = 412, ARM_VST3qWB_fixed_Asm_16 = 413, ARM_VST3qWB_fixed_Asm_32 = 414, ARM_VST3qWB_fixed_Asm_8 = 415, ARM_VST3qWB_register_Asm_16 = 416, ARM_VST3qWB_register_Asm_32 = 417, ARM_VST3qWB_register_Asm_8 = 418, ARM_VST4LNdAsm_16 = 419, ARM_VST4LNdAsm_32 = 420, ARM_VST4LNdAsm_8 = 421, ARM_VST4LNdWB_fixed_Asm_16 = 422, ARM_VST4LNdWB_fixed_Asm_32 = 423, ARM_VST4LNdWB_fixed_Asm_8 = 424, ARM_VST4LNdWB_register_Asm_16 = 425, ARM_VST4LNdWB_register_Asm_32 = 426, ARM_VST4LNdWB_register_Asm_8 = 427, ARM_VST4LNqAsm_16 = 428, ARM_VST4LNqAsm_32 = 429, ARM_VST4LNqWB_fixed_Asm_16 = 430, ARM_VST4LNqWB_fixed_Asm_32 = 431, ARM_VST4LNqWB_register_Asm_16 = 432, ARM_VST4LNqWB_register_Asm_32 = 433, ARM_VST4dAsm_16 = 434, ARM_VST4dAsm_32 = 435, ARM_VST4dAsm_8 = 436, ARM_VST4dWB_fixed_Asm_16 = 437, ARM_VST4dWB_fixed_Asm_32 = 438, ARM_VST4dWB_fixed_Asm_8 = 439, ARM_VST4dWB_register_Asm_16 = 440, ARM_VST4dWB_register_Asm_32 = 441, ARM_VST4dWB_register_Asm_8 = 442, ARM_VST4qAsm_16 = 443, ARM_VST4qAsm_32 = 444, ARM_VST4qAsm_8 = 445, ARM_VST4qWB_fixed_Asm_16 = 446, ARM_VST4qWB_fixed_Asm_32 = 447, ARM_VST4qWB_fixed_Asm_8 = 448, ARM_VST4qWB_register_Asm_16 = 449, ARM_VST4qWB_register_Asm_32 = 450, ARM_VST4qWB_register_Asm_8 = 451, ARM_t2ABS = 454, ARM_t2ADDSri = 455, ARM_t2ADDSrr = 456, ARM_t2ADDSrs = 457, ARM_t2BR_JT = 458, ARM_t2LDMIA_RET = 459, ARM_t2LDRBpcrel = 460, ARM_t2LDRConstPool = 461, ARM_t2LDRHpcrel = 462, ARM_t2LDRSBpcrel = 463, ARM_t2LDRSHpcrel = 464, ARM_t2LDRpci_pic = 465, ARM_t2LDRpcrel = 466, ARM_t2LEApcrel = 467, ARM_t2LEApcrelJT = 468, ARM_t2MOVCCasr = 469, ARM_t2MOVCCi = 470, ARM_t2MOVCCi16 = 471, ARM_t2MOVCCi32imm = 472, ARM_t2MOVCClsl = 473, ARM_t2MOVCClsr = 474, ARM_t2MOVCCr = 475, ARM_t2MOVCCror = 476, ARM_t2MOVSsi = 477, ARM_t2MOVSsr = 478, ARM_t2MOVTi16_ga_pcrel = 479, ARM_t2MOV_ga_pcrel = 480, ARM_t2MOVi16_ga_pcrel = 481, ARM_t2MOVi32imm = 482, ARM_t2MOVsi = 483, ARM_t2MOVsr = 484, ARM_t2MVNCCi = 485, ARM_t2RSBSri = 486, ARM_t2RSBSrs = 487, ARM_t2STRB_preidx = 488, ARM_t2STRH_preidx = 489, ARM_t2STR_preidx = 490, ARM_t2SUBSri = 491, ARM_t2SUBSrr = 492, ARM_t2SUBSrs = 493, ARM_t2TBB_JT = 494, ARM_t2TBH_JT = 495, ARM_tADCS = 496, ARM_tADDSi3 = 497, ARM_tADDSi8 = 498, ARM_tADDSrr = 499, ARM_tADDframe = 500, ARM_tADJCALLSTACKDOWN = 501, ARM_tADJCALLSTACKUP = 502, ARM_tBRIND = 503, ARM_tBR_JTr = 504, ARM_tBX_CALL = 505, ARM_tBX_RET = 506, ARM_tBX_RET_vararg = 507, ARM_tBfar = 508, ARM_tLDMIA_UPD = 509, ARM_tLDRConstPool = 510, ARM_tLDRLIT_ga_abs = 511, ARM_tLDRLIT_ga_pcrel = 512, ARM_tLDR_postidx = 513, ARM_tLDRpci_pic = 514, ARM_tLEApcrel = 515, ARM_tLEApcrelJT = 516, ARM_tMOVCCr_pseudo = 517, ARM_tPOP_RET = 518, ARM_tSBCS = 519, ARM_tSUBSi3 = 520, ARM_tSUBSi8 = 521, ARM_tSUBSrr = 522, ARM_tTAILJMPd = 523, ARM_tTAILJMPdND = 524, ARM_tTAILJMPr = 525, ARM_tTBB_JT = 526, ARM_tTBH_JT = 527, ARM_tTPsoft = 528, ARM_ADCri = 529, ARM_ADCrr = 530, ARM_ADCrsi = 531, ARM_ADCrsr = 532, ARM_ADDri = 533, ARM_ADDrr = 534, ARM_ADDrsi = 535, ARM_ADDrsr = 536, ARM_ADR = 537, ARM_AESD = 538, ARM_AESE = 539, ARM_AESIMC = 540, ARM_AESMC = 541, ARM_ANDri = 542, ARM_ANDrr = 543, ARM_ANDrsi = 544, ARM_ANDrsr = 545, ARM_BFC = 546, ARM_BFI = 547, ARM_BICri = 548, ARM_BICrr = 549, ARM_BICrsi = 550, ARM_BICrsr = 551, ARM_BKPT = 552, ARM_BL = 553, ARM_BLX = 554, ARM_BLX_pred = 555, ARM_BLXi = 556, ARM_BL_pred = 557, ARM_BX = 558, ARM_BXJ = 559, ARM_BX_RET = 560, ARM_BX_pred = 561, ARM_Bcc = 562, ARM_CDP = 563, ARM_CDP2 = 564, ARM_CLREX = 565, ARM_CLZ = 566, ARM_CMNri = 567, ARM_CMNzrr = 568, ARM_CMNzrsi = 569, ARM_CMNzrsr = 570, ARM_CMPri = 571, ARM_CMPrr = 572, ARM_CMPrsi = 573, ARM_CMPrsr = 574, ARM_CPS1p = 575, ARM_CPS2p = 576, ARM_CPS3p = 577, ARM_CRC32B = 578, ARM_CRC32CB = 579, ARM_CRC32CH = 580, ARM_CRC32CW = 581, ARM_CRC32H = 582, ARM_CRC32W = 583, ARM_DBG = 584, ARM_DMB = 585, ARM_DSB = 586, ARM_EORri = 587, ARM_EORrr = 588, ARM_EORrsi = 589, ARM_EORrsr = 590, ARM_ERET = 591, ARM_FCONSTD = 592, ARM_FCONSTH = 593, ARM_FCONSTS = 594, ARM_FLDMXDB_UPD = 595, ARM_FLDMXIA = 596, ARM_FLDMXIA_UPD = 597, ARM_FMSTAT = 598, ARM_FSTMXDB_UPD = 599, ARM_FSTMXIA = 600, ARM_FSTMXIA_UPD = 601, ARM_HINT = 602, ARM_HLT = 603, ARM_HVC = 604, ARM_ISB = 605, ARM_LDA = 606, ARM_LDAB = 607, ARM_LDAEX = 608, ARM_LDAEXB = 609, ARM_LDAEXD = 610, ARM_LDAEXH = 611, ARM_LDAH = 612, ARM_LDC2L_OFFSET = 613, ARM_LDC2L_OPTION = 614, ARM_LDC2L_POST = 615, ARM_LDC2L_PRE = 616, ARM_LDC2_OFFSET = 617, ARM_LDC2_OPTION = 618, ARM_LDC2_POST = 619, ARM_LDC2_PRE = 620, ARM_LDCL_OFFSET = 621, ARM_LDCL_OPTION = 622, ARM_LDCL_POST = 623, ARM_LDCL_PRE = 624, ARM_LDC_OFFSET = 625, ARM_LDC_OPTION = 626, ARM_LDC_POST = 627, ARM_LDC_PRE = 628, ARM_LDMDA = 629, ARM_LDMDA_UPD = 630, ARM_LDMDB = 631, ARM_LDMDB_UPD = 632, ARM_LDMIA = 633, ARM_LDMIA_UPD = 634, ARM_LDMIB = 635, ARM_LDMIB_UPD = 636, ARM_LDRBT_POST_IMM = 637, ARM_LDRBT_POST_REG = 638, ARM_LDRB_POST_IMM = 639, ARM_LDRB_POST_REG = 640, ARM_LDRB_PRE_IMM = 641, ARM_LDRB_PRE_REG = 642, ARM_LDRBi12 = 643, ARM_LDRBrs = 644, ARM_LDRD = 645, ARM_LDRD_POST = 646, ARM_LDRD_PRE = 647, ARM_LDREX = 648, ARM_LDREXB = 649, ARM_LDREXD = 650, ARM_LDREXH = 651, ARM_LDRH = 652, ARM_LDRHTi = 653, ARM_LDRHTr = 654, ARM_LDRH_POST = 655, ARM_LDRH_PRE = 656, ARM_LDRSB = 657, ARM_LDRSBTi = 658, ARM_LDRSBTr = 659, ARM_LDRSB_POST = 660, ARM_LDRSB_PRE = 661, ARM_LDRSH = 662, ARM_LDRSHTi = 663, ARM_LDRSHTr = 664, ARM_LDRSH_POST = 665, ARM_LDRSH_PRE = 666, ARM_LDRT_POST_IMM = 667, ARM_LDRT_POST_REG = 668, ARM_LDR_POST_IMM = 669, ARM_LDR_POST_REG = 670, ARM_LDR_PRE_IMM = 671, ARM_LDR_PRE_REG = 672, ARM_LDRcp = 673, ARM_LDRi12 = 674, ARM_LDRrs = 675, ARM_MCR = 676, ARM_MCR2 = 677, ARM_MCRR = 678, ARM_MCRR2 = 679, ARM_MLA = 680, ARM_MLS = 681, ARM_MOVPCLR = 682, ARM_MOVTi16 = 683, ARM_MOVi = 684, ARM_MOVi16 = 685, ARM_MOVr = 686, ARM_MOVr_TC = 687, ARM_MOVsi = 688, ARM_MOVsr = 689, ARM_MRC = 690, ARM_MRC2 = 691, ARM_MRRC = 692, ARM_MRRC2 = 693, ARM_MRS = 694, ARM_MRSbanked = 695, ARM_MRSsys = 696, ARM_MSR = 697, ARM_MSRbanked = 698, ARM_MSRi = 699, ARM_MUL = 700, ARM_MVNi = 701, ARM_MVNr = 702, ARM_MVNsi = 703, ARM_MVNsr = 704, ARM_ORRri = 705, ARM_ORRrr = 706, ARM_ORRrsi = 707, ARM_ORRrsr = 708, ARM_PKHBT = 709, ARM_PKHTB = 710, ARM_PLDWi12 = 711, ARM_PLDWrs = 712, ARM_PLDi12 = 713, ARM_PLDrs = 714, ARM_PLIi12 = 715, ARM_PLIrs = 716, ARM_QADD = 717, ARM_QADD16 = 718, ARM_QADD8 = 719, ARM_QASX = 720, ARM_QDADD = 721, ARM_QDSUB = 722, ARM_QSAX = 723, ARM_QSUB = 724, ARM_QSUB16 = 725, ARM_QSUB8 = 726, ARM_RBIT = 727, ARM_REV = 728, ARM_REV16 = 729, ARM_REVSH = 730, ARM_RFEDA = 731, ARM_RFEDA_UPD = 732, ARM_RFEDB = 733, ARM_RFEDB_UPD = 734, ARM_RFEIA = 735, ARM_RFEIA_UPD = 736, ARM_RFEIB = 737, ARM_RFEIB_UPD = 738, ARM_RSBri = 739, ARM_RSBrr = 740, ARM_RSBrsi = 741, ARM_RSBrsr = 742, ARM_RSCri = 743, ARM_RSCrr = 744, ARM_RSCrsi = 745, ARM_RSCrsr = 746, ARM_SADD16 = 747, ARM_SADD8 = 748, ARM_SASX = 749, ARM_SBCri = 750, ARM_SBCrr = 751, ARM_SBCrsi = 752, ARM_SBCrsr = 753, ARM_SBFX = 754, ARM_SDIV = 755, ARM_SEL = 756, ARM_SETEND = 757, ARM_SETPAN = 758, ARM_SHA1C = 759, ARM_SHA1H = 760, ARM_SHA1M = 761, ARM_SHA1P = 762, ARM_SHA1SU0 = 763, ARM_SHA1SU1 = 764, ARM_SHA256H = 765, ARM_SHA256H2 = 766, ARM_SHA256SU0 = 767, ARM_SHA256SU1 = 768, ARM_SHADD16 = 769, ARM_SHADD8 = 770, ARM_SHASX = 771, ARM_SHSAX = 772, ARM_SHSUB16 = 773, ARM_SHSUB8 = 774, ARM_SMC = 775, ARM_SMLABB = 776, ARM_SMLABT = 777, ARM_SMLAD = 778, ARM_SMLADX = 779, ARM_SMLAL = 780, ARM_SMLALBB = 781, ARM_SMLALBT = 782, ARM_SMLALD = 783, ARM_SMLALDX = 784, ARM_SMLALTB = 785, ARM_SMLALTT = 786, ARM_SMLATB = 787, ARM_SMLATT = 788, ARM_SMLAWB = 789, ARM_SMLAWT = 790, ARM_SMLSD = 791, ARM_SMLSDX = 792, ARM_SMLSLD = 793, ARM_SMLSLDX = 794, ARM_SMMLA = 795, ARM_SMMLAR = 796, ARM_SMMLS = 797, ARM_SMMLSR = 798, ARM_SMMUL = 799, ARM_SMMULR = 800, ARM_SMUAD = 801, ARM_SMUADX = 802, ARM_SMULBB = 803, ARM_SMULBT = 804, ARM_SMULL = 805, ARM_SMULTB = 806, ARM_SMULTT = 807, ARM_SMULWB = 808, ARM_SMULWT = 809, ARM_SMUSD = 810, ARM_SMUSDX = 811, ARM_SRSDA = 812, ARM_SRSDA_UPD = 813, ARM_SRSDB = 814, ARM_SRSDB_UPD = 815, ARM_SRSIA = 816, ARM_SRSIA_UPD = 817, ARM_SRSIB = 818, ARM_SRSIB_UPD = 819, ARM_SSAT = 820, ARM_SSAT16 = 821, ARM_SSAX = 822, ARM_SSUB16 = 823, ARM_SSUB8 = 824, ARM_STC2L_OFFSET = 825, ARM_STC2L_OPTION = 826, ARM_STC2L_POST = 827, ARM_STC2L_PRE = 828, ARM_STC2_OFFSET = 829, ARM_STC2_OPTION = 830, ARM_STC2_POST = 831, ARM_STC2_PRE = 832, ARM_STCL_OFFSET = 833, ARM_STCL_OPTION = 834, ARM_STCL_POST = 835, ARM_STCL_PRE = 836, ARM_STC_OFFSET = 837, ARM_STC_OPTION = 838, ARM_STC_POST = 839, ARM_STC_PRE = 840, ARM_STL = 841, ARM_STLB = 842, ARM_STLEX = 843, ARM_STLEXB = 844, ARM_STLEXD = 845, ARM_STLEXH = 846, ARM_STLH = 847, ARM_STMDA = 848, ARM_STMDA_UPD = 849, ARM_STMDB = 850, ARM_STMDB_UPD = 851, ARM_STMIA = 852, ARM_STMIA_UPD = 853, ARM_STMIB = 854, ARM_STMIB_UPD = 855, ARM_STRBT_POST_IMM = 856, ARM_STRBT_POST_REG = 857, ARM_STRB_POST_IMM = 858, ARM_STRB_POST_REG = 859, ARM_STRB_PRE_IMM = 860, ARM_STRB_PRE_REG = 861, ARM_STRBi12 = 862, ARM_STRBrs = 863, ARM_STRD = 864, ARM_STRD_POST = 865, ARM_STRD_PRE = 866, ARM_STREX = 867, ARM_STREXB = 868, ARM_STREXD = 869, ARM_STREXH = 870, ARM_STRH = 871, ARM_STRHTi = 872, ARM_STRHTr = 873, ARM_STRH_POST = 874, ARM_STRH_PRE = 875, ARM_STRT_POST_IMM = 876, ARM_STRT_POST_REG = 877, ARM_STR_POST_IMM = 878, ARM_STR_POST_REG = 879, ARM_STR_PRE_IMM = 880, ARM_STR_PRE_REG = 881, ARM_STRi12 = 882, ARM_STRrs = 883, ARM_SUBri = 884, ARM_SUBrr = 885, ARM_SUBrsi = 886, ARM_SUBrsr = 887, ARM_SVC = 888, ARM_SWP = 889, ARM_SWPB = 890, ARM_SXTAB = 891, ARM_SXTAB16 = 892, ARM_SXTAH = 893, ARM_SXTB = 894, ARM_SXTB16 = 895, ARM_SXTH = 896, ARM_TEQri = 897, ARM_TEQrr = 898, ARM_TEQrsi = 899, ARM_TEQrsr = 900, ARM_TRAP = 901, ARM_TRAPNaCl = 902, ARM_TSB = 903, ARM_TSTri = 904, ARM_TSTrr = 905, ARM_TSTrsi = 906, ARM_TSTrsr = 907, ARM_UADD16 = 908, ARM_UADD8 = 909, ARM_UASX = 910, ARM_UBFX = 911, ARM_UDF = 912, ARM_UDIV = 913, ARM_UHADD16 = 914, ARM_UHADD8 = 915, ARM_UHASX = 916, ARM_UHSAX = 917, ARM_UHSUB16 = 918, ARM_UHSUB8 = 919, ARM_UMAAL = 920, ARM_UMLAL = 921, ARM_UMULL = 922, ARM_UQADD16 = 923, ARM_UQADD8 = 924, ARM_UQASX = 925, ARM_UQSAX = 926, ARM_UQSUB16 = 927, ARM_UQSUB8 = 928, ARM_USAD8 = 929, ARM_USADA8 = 930, ARM_USAT = 931, ARM_USAT16 = 932, ARM_USAX = 933, ARM_USUB16 = 934, ARM_USUB8 = 935, ARM_UXTAB = 936, ARM_UXTAB16 = 937, ARM_UXTAH = 938, ARM_UXTB = 939, ARM_UXTB16 = 940, ARM_UXTH = 941, ARM_VABALsv2i64 = 942, ARM_VABALsv4i32 = 943, ARM_VABALsv8i16 = 944, ARM_VABALuv2i64 = 945, ARM_VABALuv4i32 = 946, ARM_VABALuv8i16 = 947, ARM_VABAsv16i8 = 948, ARM_VABAsv2i32 = 949, ARM_VABAsv4i16 = 950, ARM_VABAsv4i32 = 951, ARM_VABAsv8i16 = 952, ARM_VABAsv8i8 = 953, ARM_VABAuv16i8 = 954, ARM_VABAuv2i32 = 955, ARM_VABAuv4i16 = 956, ARM_VABAuv4i32 = 957, ARM_VABAuv8i16 = 958, ARM_VABAuv8i8 = 959, ARM_VABDLsv2i64 = 960, ARM_VABDLsv4i32 = 961, ARM_VABDLsv8i16 = 962, ARM_VABDLuv2i64 = 963, ARM_VABDLuv4i32 = 964, ARM_VABDLuv8i16 = 965, ARM_VABDfd = 966, ARM_VABDfq = 967, ARM_VABDhd = 968, ARM_VABDhq = 969, ARM_VABDsv16i8 = 970, ARM_VABDsv2i32 = 971, ARM_VABDsv4i16 = 972, ARM_VABDsv4i32 = 973, ARM_VABDsv8i16 = 974, ARM_VABDsv8i8 = 975, ARM_VABDuv16i8 = 976, ARM_VABDuv2i32 = 977, ARM_VABDuv4i16 = 978, ARM_VABDuv4i32 = 979, ARM_VABDuv8i16 = 980, ARM_VABDuv8i8 = 981, ARM_VABSD = 982, ARM_VABSH = 983, ARM_VABSS = 984, ARM_VABSfd = 985, ARM_VABSfq = 986, ARM_VABShd = 987, ARM_VABShq = 988, ARM_VABSv16i8 = 989, ARM_VABSv2i32 = 990, ARM_VABSv4i16 = 991, ARM_VABSv4i32 = 992, ARM_VABSv8i16 = 993, ARM_VABSv8i8 = 994, ARM_VACGEfd = 995, ARM_VACGEfq = 996, ARM_VACGEhd = 997, ARM_VACGEhq = 998, ARM_VACGTfd = 999, ARM_VACGTfq = 1000, ARM_VACGThd = 1001, ARM_VACGThq = 1002, ARM_VADDD = 1003, ARM_VADDH = 1004, ARM_VADDHNv2i32 = 1005, ARM_VADDHNv4i16 = 1006, ARM_VADDHNv8i8 = 1007, ARM_VADDLsv2i64 = 1008, ARM_VADDLsv4i32 = 1009, ARM_VADDLsv8i16 = 1010, ARM_VADDLuv2i64 = 1011, ARM_VADDLuv4i32 = 1012, ARM_VADDLuv8i16 = 1013, ARM_VADDS = 1014, ARM_VADDWsv2i64 = 1015, ARM_VADDWsv4i32 = 1016, ARM_VADDWsv8i16 = 1017, ARM_VADDWuv2i64 = 1018, ARM_VADDWuv4i32 = 1019, ARM_VADDWuv8i16 = 1020, ARM_VADDfd = 1021, ARM_VADDfq = 1022, ARM_VADDhd = 1023, ARM_VADDhq = 1024, ARM_VADDv16i8 = 1025, ARM_VADDv1i64 = 1026, ARM_VADDv2i32 = 1027, ARM_VADDv2i64 = 1028, ARM_VADDv4i16 = 1029, ARM_VADDv4i32 = 1030, ARM_VADDv8i16 = 1031, ARM_VADDv8i8 = 1032, ARM_VANDd = 1033, ARM_VANDq = 1034, ARM_VBICd = 1035, ARM_VBICiv2i32 = 1036, ARM_VBICiv4i16 = 1037, ARM_VBICiv4i32 = 1038, ARM_VBICiv8i16 = 1039, ARM_VBICq = 1040, ARM_VBIFd = 1041, ARM_VBIFq = 1042, ARM_VBITd = 1043, ARM_VBITq = 1044, ARM_VBSLd = 1045, ARM_VBSLq = 1046, ARM_VCADDv2f32 = 1047, ARM_VCADDv4f16 = 1048, ARM_VCADDv4f32 = 1049, ARM_VCADDv8f16 = 1050, ARM_VCEQfd = 1051, ARM_VCEQfq = 1052, ARM_VCEQhd = 1053, ARM_VCEQhq = 1054, ARM_VCEQv16i8 = 1055, ARM_VCEQv2i32 = 1056, ARM_VCEQv4i16 = 1057, ARM_VCEQv4i32 = 1058, ARM_VCEQv8i16 = 1059, ARM_VCEQv8i8 = 1060, ARM_VCEQzv16i8 = 1061, ARM_VCEQzv2f32 = 1062, ARM_VCEQzv2i32 = 1063, ARM_VCEQzv4f16 = 1064, ARM_VCEQzv4f32 = 1065, ARM_VCEQzv4i16 = 1066, ARM_VCEQzv4i32 = 1067, ARM_VCEQzv8f16 = 1068, ARM_VCEQzv8i16 = 1069, ARM_VCEQzv8i8 = 1070, ARM_VCGEfd = 1071, ARM_VCGEfq = 1072, ARM_VCGEhd = 1073, ARM_VCGEhq = 1074, ARM_VCGEsv16i8 = 1075, ARM_VCGEsv2i32 = 1076, ARM_VCGEsv4i16 = 1077, ARM_VCGEsv4i32 = 1078, ARM_VCGEsv8i16 = 1079, ARM_VCGEsv8i8 = 1080, ARM_VCGEuv16i8 = 1081, ARM_VCGEuv2i32 = 1082, ARM_VCGEuv4i16 = 1083, ARM_VCGEuv4i32 = 1084, ARM_VCGEuv8i16 = 1085, ARM_VCGEuv8i8 = 1086, ARM_VCGEzv16i8 = 1087, ARM_VCGEzv2f32 = 1088, ARM_VCGEzv2i32 = 1089, ARM_VCGEzv4f16 = 1090, ARM_VCGEzv4f32 = 1091, ARM_VCGEzv4i16 = 1092, ARM_VCGEzv4i32 = 1093, ARM_VCGEzv8f16 = 1094, ARM_VCGEzv8i16 = 1095, ARM_VCGEzv8i8 = 1096, ARM_VCGTfd = 1097, ARM_VCGTfq = 1098, ARM_VCGThd = 1099, ARM_VCGThq = 1100, ARM_VCGTsv16i8 = 1101, ARM_VCGTsv2i32 = 1102, ARM_VCGTsv4i16 = 1103, ARM_VCGTsv4i32 = 1104, ARM_VCGTsv8i16 = 1105, ARM_VCGTsv8i8 = 1106, ARM_VCGTuv16i8 = 1107, ARM_VCGTuv2i32 = 1108, ARM_VCGTuv4i16 = 1109, ARM_VCGTuv4i32 = 1110, ARM_VCGTuv8i16 = 1111, ARM_VCGTuv8i8 = 1112, ARM_VCGTzv16i8 = 1113, ARM_VCGTzv2f32 = 1114, ARM_VCGTzv2i32 = 1115, ARM_VCGTzv4f16 = 1116, ARM_VCGTzv4f32 = 1117, ARM_VCGTzv4i16 = 1118, ARM_VCGTzv4i32 = 1119, ARM_VCGTzv8f16 = 1120, ARM_VCGTzv8i16 = 1121, ARM_VCGTzv8i8 = 1122, ARM_VCLEzv16i8 = 1123, ARM_VCLEzv2f32 = 1124, ARM_VCLEzv2i32 = 1125, ARM_VCLEzv4f16 = 1126, ARM_VCLEzv4f32 = 1127, ARM_VCLEzv4i16 = 1128, ARM_VCLEzv4i32 = 1129, ARM_VCLEzv8f16 = 1130, ARM_VCLEzv8i16 = 1131, ARM_VCLEzv8i8 = 1132, ARM_VCLSv16i8 = 1133, ARM_VCLSv2i32 = 1134, ARM_VCLSv4i16 = 1135, ARM_VCLSv4i32 = 1136, ARM_VCLSv8i16 = 1137, ARM_VCLSv8i8 = 1138, ARM_VCLTzv16i8 = 1139, ARM_VCLTzv2f32 = 1140, ARM_VCLTzv2i32 = 1141, ARM_VCLTzv4f16 = 1142, ARM_VCLTzv4f32 = 1143, ARM_VCLTzv4i16 = 1144, ARM_VCLTzv4i32 = 1145, ARM_VCLTzv8f16 = 1146, ARM_VCLTzv8i16 = 1147, ARM_VCLTzv8i8 = 1148, ARM_VCLZv16i8 = 1149, ARM_VCLZv2i32 = 1150, ARM_VCLZv4i16 = 1151, ARM_VCLZv4i32 = 1152, ARM_VCLZv8i16 = 1153, ARM_VCLZv8i8 = 1154, ARM_VCMLAv2f32 = 1155, ARM_VCMLAv2f32_indexed = 1156, ARM_VCMLAv4f16 = 1157, ARM_VCMLAv4f16_indexed = 1158, ARM_VCMLAv4f32 = 1159, ARM_VCMLAv4f32_indexed = 1160, ARM_VCMLAv8f16 = 1161, ARM_VCMLAv8f16_indexed = 1162, ARM_VCMPD = 1163, ARM_VCMPED = 1164, ARM_VCMPEH = 1165, ARM_VCMPES = 1166, ARM_VCMPEZD = 1167, ARM_VCMPEZH = 1168, ARM_VCMPEZS = 1169, ARM_VCMPH = 1170, ARM_VCMPS = 1171, ARM_VCMPZD = 1172, ARM_VCMPZH = 1173, ARM_VCMPZS = 1174, ARM_VCNTd = 1175, ARM_VCNTq = 1176, ARM_VCVTANSDf = 1177, ARM_VCVTANSDh = 1178, ARM_VCVTANSQf = 1179, ARM_VCVTANSQh = 1180, ARM_VCVTANUDf = 1181, ARM_VCVTANUDh = 1182, ARM_VCVTANUQf = 1183, ARM_VCVTANUQh = 1184, ARM_VCVTASD = 1185, ARM_VCVTASH = 1186, ARM_VCVTASS = 1187, ARM_VCVTAUD = 1188, ARM_VCVTAUH = 1189, ARM_VCVTAUS = 1190, ARM_VCVTBDH = 1191, ARM_VCVTBHD = 1192, ARM_VCVTBHS = 1193, ARM_VCVTBSH = 1194, ARM_VCVTDS = 1195, ARM_VCVTMNSDf = 1196, ARM_VCVTMNSDh = 1197, ARM_VCVTMNSQf = 1198, ARM_VCVTMNSQh = 1199, ARM_VCVTMNUDf = 1200, ARM_VCVTMNUDh = 1201, ARM_VCVTMNUQf = 1202, ARM_VCVTMNUQh = 1203, ARM_VCVTMSD = 1204, ARM_VCVTMSH = 1205, ARM_VCVTMSS = 1206, ARM_VCVTMUD = 1207, ARM_VCVTMUH = 1208, ARM_VCVTMUS = 1209, ARM_VCVTNNSDf = 1210, ARM_VCVTNNSDh = 1211, ARM_VCVTNNSQf = 1212, ARM_VCVTNNSQh = 1213, ARM_VCVTNNUDf = 1214, ARM_VCVTNNUDh = 1215, ARM_VCVTNNUQf = 1216, ARM_VCVTNNUQh = 1217, ARM_VCVTNSD = 1218, ARM_VCVTNSH = 1219, ARM_VCVTNSS = 1220, ARM_VCVTNUD = 1221, ARM_VCVTNUH = 1222, ARM_VCVTNUS = 1223, ARM_VCVTPNSDf = 1224, ARM_VCVTPNSDh = 1225, ARM_VCVTPNSQf = 1226, ARM_VCVTPNSQh = 1227, ARM_VCVTPNUDf = 1228, ARM_VCVTPNUDh = 1229, ARM_VCVTPNUQf = 1230, ARM_VCVTPNUQh = 1231, ARM_VCVTPSD = 1232, ARM_VCVTPSH = 1233, ARM_VCVTPSS = 1234, ARM_VCVTPUD = 1235, ARM_VCVTPUH = 1236, ARM_VCVTPUS = 1237, ARM_VCVTSD = 1238, ARM_VCVTTDH = 1239, ARM_VCVTTHD = 1240, ARM_VCVTTHS = 1241, ARM_VCVTTSH = 1242, ARM_VCVTf2h = 1243, ARM_VCVTf2sd = 1244, ARM_VCVTf2sq = 1245, ARM_VCVTf2ud = 1246, ARM_VCVTf2uq = 1247, ARM_VCVTf2xsd = 1248, ARM_VCVTf2xsq = 1249, ARM_VCVTf2xud = 1250, ARM_VCVTf2xuq = 1251, ARM_VCVTh2f = 1252, ARM_VCVTh2sd = 1253, ARM_VCVTh2sq = 1254, ARM_VCVTh2ud = 1255, ARM_VCVTh2uq = 1256, ARM_VCVTh2xsd = 1257, ARM_VCVTh2xsq = 1258, ARM_VCVTh2xud = 1259, ARM_VCVTh2xuq = 1260, ARM_VCVTs2fd = 1261, ARM_VCVTs2fq = 1262, ARM_VCVTs2hd = 1263, ARM_VCVTs2hq = 1264, ARM_VCVTu2fd = 1265, ARM_VCVTu2fq = 1266, ARM_VCVTu2hd = 1267, ARM_VCVTu2hq = 1268, ARM_VCVTxs2fd = 1269, ARM_VCVTxs2fq = 1270, ARM_VCVTxs2hd = 1271, ARM_VCVTxs2hq = 1272, ARM_VCVTxu2fd = 1273, ARM_VCVTxu2fq = 1274, ARM_VCVTxu2hd = 1275, ARM_VCVTxu2hq = 1276, ARM_VDIVD = 1277, ARM_VDIVH = 1278, ARM_VDIVS = 1279, ARM_VDUP16d = 1280, ARM_VDUP16q = 1281, ARM_VDUP32d = 1282, ARM_VDUP32q = 1283, ARM_VDUP8d = 1284, ARM_VDUP8q = 1285, ARM_VDUPLN16d = 1286, ARM_VDUPLN16q = 1287, ARM_VDUPLN32d = 1288, ARM_VDUPLN32q = 1289, ARM_VDUPLN8d = 1290, ARM_VDUPLN8q = 1291, ARM_VEORd = 1292, ARM_VEORq = 1293, ARM_VEXTd16 = 1294, ARM_VEXTd32 = 1295, ARM_VEXTd8 = 1296, ARM_VEXTq16 = 1297, ARM_VEXTq32 = 1298, ARM_VEXTq64 = 1299, ARM_VEXTq8 = 1300, ARM_VFMAD = 1301, ARM_VFMAH = 1302, ARM_VFMAS = 1303, ARM_VFMAfd = 1304, ARM_VFMAfq = 1305, ARM_VFMAhd = 1306, ARM_VFMAhq = 1307, ARM_VFMSD = 1308, ARM_VFMSH = 1309, ARM_VFMSS = 1310, ARM_VFMSfd = 1311, ARM_VFMSfq = 1312, ARM_VFMShd = 1313, ARM_VFMShq = 1314, ARM_VFNMAD = 1315, ARM_VFNMAH = 1316, ARM_VFNMAS = 1317, ARM_VFNMSD = 1318, ARM_VFNMSH = 1319, ARM_VFNMSS = 1320, ARM_VGETLNi32 = 1321, ARM_VGETLNs16 = 1322, ARM_VGETLNs8 = 1323, ARM_VGETLNu16 = 1324, ARM_VGETLNu8 = 1325, ARM_VHADDsv16i8 = 1326, ARM_VHADDsv2i32 = 1327, ARM_VHADDsv4i16 = 1328, ARM_VHADDsv4i32 = 1329, ARM_VHADDsv8i16 = 1330, ARM_VHADDsv8i8 = 1331, ARM_VHADDuv16i8 = 1332, ARM_VHADDuv2i32 = 1333, ARM_VHADDuv4i16 = 1334, ARM_VHADDuv4i32 = 1335, ARM_VHADDuv8i16 = 1336, ARM_VHADDuv8i8 = 1337, ARM_VHSUBsv16i8 = 1338, ARM_VHSUBsv2i32 = 1339, ARM_VHSUBsv4i16 = 1340, ARM_VHSUBsv4i32 = 1341, ARM_VHSUBsv8i16 = 1342, ARM_VHSUBsv8i8 = 1343, ARM_VHSUBuv16i8 = 1344, ARM_VHSUBuv2i32 = 1345, ARM_VHSUBuv4i16 = 1346, ARM_VHSUBuv4i32 = 1347, ARM_VHSUBuv8i16 = 1348, ARM_VHSUBuv8i8 = 1349, ARM_VINSH = 1350, ARM_VJCVT = 1351, ARM_VLD1DUPd16 = 1352, ARM_VLD1DUPd16wb_fixed = 1353, ARM_VLD1DUPd16wb_register = 1354, ARM_VLD1DUPd32 = 1355, ARM_VLD1DUPd32wb_fixed = 1356, ARM_VLD1DUPd32wb_register = 1357, ARM_VLD1DUPd8 = 1358, ARM_VLD1DUPd8wb_fixed = 1359, ARM_VLD1DUPd8wb_register = 1360, ARM_VLD1DUPq16 = 1361, ARM_VLD1DUPq16wb_fixed = 1362, ARM_VLD1DUPq16wb_register = 1363, ARM_VLD1DUPq32 = 1364, ARM_VLD1DUPq32wb_fixed = 1365, ARM_VLD1DUPq32wb_register = 1366, ARM_VLD1DUPq8 = 1367, ARM_VLD1DUPq8wb_fixed = 1368, ARM_VLD1DUPq8wb_register = 1369, ARM_VLD1LNd16 = 1370, ARM_VLD1LNd16_UPD = 1371, ARM_VLD1LNd32 = 1372, ARM_VLD1LNd32_UPD = 1373, ARM_VLD1LNd8 = 1374, ARM_VLD1LNd8_UPD = 1375, ARM_VLD1d16 = 1382, ARM_VLD1d16Q = 1383, ARM_VLD1d16Qwb_fixed = 1385, ARM_VLD1d16Qwb_register = 1386, ARM_VLD1d16T = 1387, ARM_VLD1d16Twb_fixed = 1389, ARM_VLD1d16Twb_register = 1390, ARM_VLD1d16wb_fixed = 1391, ARM_VLD1d16wb_register = 1392, ARM_VLD1d32 = 1393, ARM_VLD1d32Q = 1394, ARM_VLD1d32Qwb_fixed = 1396, ARM_VLD1d32Qwb_register = 1397, ARM_VLD1d32T = 1398, ARM_VLD1d32Twb_fixed = 1400, ARM_VLD1d32Twb_register = 1401, ARM_VLD1d32wb_fixed = 1402, ARM_VLD1d32wb_register = 1403, ARM_VLD1d64 = 1404, ARM_VLD1d64Q = 1405, ARM_VLD1d64Qwb_fixed = 1409, ARM_VLD1d64Qwb_register = 1410, ARM_VLD1d64T = 1411, ARM_VLD1d64Twb_fixed = 1415, ARM_VLD1d64Twb_register = 1416, ARM_VLD1d64wb_fixed = 1417, ARM_VLD1d64wb_register = 1418, ARM_VLD1d8 = 1419, ARM_VLD1d8Q = 1420, ARM_VLD1d8Qwb_fixed = 1422, ARM_VLD1d8Qwb_register = 1423, ARM_VLD1d8T = 1424, ARM_VLD1d8Twb_fixed = 1426, ARM_VLD1d8Twb_register = 1427, ARM_VLD1d8wb_fixed = 1428, ARM_VLD1d8wb_register = 1429, ARM_VLD1q16 = 1430, ARM_VLD1q16wb_fixed = 1435, ARM_VLD1q16wb_register = 1436, ARM_VLD1q32 = 1437, ARM_VLD1q32wb_fixed = 1442, ARM_VLD1q32wb_register = 1443, ARM_VLD1q64 = 1444, ARM_VLD1q64wb_fixed = 1449, ARM_VLD1q64wb_register = 1450, ARM_VLD1q8 = 1451, ARM_VLD1q8wb_fixed = 1456, ARM_VLD1q8wb_register = 1457, ARM_VLD2DUPd16 = 1458, ARM_VLD2DUPd16wb_fixed = 1459, ARM_VLD2DUPd16wb_register = 1460, ARM_VLD2DUPd16x2 = 1461, ARM_VLD2DUPd16x2wb_fixed = 1462, ARM_VLD2DUPd16x2wb_register = 1463, ARM_VLD2DUPd32 = 1464, ARM_VLD2DUPd32wb_fixed = 1465, ARM_VLD2DUPd32wb_register = 1466, ARM_VLD2DUPd32x2 = 1467, ARM_VLD2DUPd32x2wb_fixed = 1468, ARM_VLD2DUPd32x2wb_register = 1469, ARM_VLD2DUPd8 = 1470, ARM_VLD2DUPd8wb_fixed = 1471, ARM_VLD2DUPd8wb_register = 1472, ARM_VLD2DUPd8x2 = 1473, ARM_VLD2DUPd8x2wb_fixed = 1474, ARM_VLD2DUPd8x2wb_register = 1475, ARM_VLD2LNd16 = 1482, ARM_VLD2LNd16_UPD = 1485, ARM_VLD2LNd32 = 1486, ARM_VLD2LNd32_UPD = 1489, ARM_VLD2LNd8 = 1490, ARM_VLD2LNd8_UPD = 1493, ARM_VLD2LNq16 = 1494, ARM_VLD2LNq16_UPD = 1497, ARM_VLD2LNq32 = 1498, ARM_VLD2LNq32_UPD = 1501, ARM_VLD2b16 = 1502, ARM_VLD2b16wb_fixed = 1503, ARM_VLD2b16wb_register = 1504, ARM_VLD2b32 = 1505, ARM_VLD2b32wb_fixed = 1506, ARM_VLD2b32wb_register = 1507, ARM_VLD2b8 = 1508, ARM_VLD2b8wb_fixed = 1509, ARM_VLD2b8wb_register = 1510, ARM_VLD2d16 = 1511, ARM_VLD2d16wb_fixed = 1512, ARM_VLD2d16wb_register = 1513, ARM_VLD2d32 = 1514, ARM_VLD2d32wb_fixed = 1515, ARM_VLD2d32wb_register = 1516, ARM_VLD2d8 = 1517, ARM_VLD2d8wb_fixed = 1518, ARM_VLD2d8wb_register = 1519, ARM_VLD2q16 = 1520, ARM_VLD2q16wb_fixed = 1524, ARM_VLD2q16wb_register = 1525, ARM_VLD2q32 = 1526, ARM_VLD2q32wb_fixed = 1530, ARM_VLD2q32wb_register = 1531, ARM_VLD2q8 = 1532, ARM_VLD2q8wb_fixed = 1536, ARM_VLD2q8wb_register = 1537, ARM_VLD3DUPd16 = 1538, ARM_VLD3DUPd16_UPD = 1541, ARM_VLD3DUPd32 = 1542, ARM_VLD3DUPd32_UPD = 1545, ARM_VLD3DUPd8 = 1546, ARM_VLD3DUPd8_UPD = 1549, ARM_VLD3DUPq16 = 1550, ARM_VLD3DUPq16_UPD = 1553, ARM_VLD3DUPq32 = 1554, ARM_VLD3DUPq32_UPD = 1557, ARM_VLD3DUPq8 = 1558, ARM_VLD3DUPq8_UPD = 1561, ARM_VLD3LNd16 = 1562, ARM_VLD3LNd16_UPD = 1565, ARM_VLD3LNd32 = 1566, ARM_VLD3LNd32_UPD = 1569, ARM_VLD3LNd8 = 1570, ARM_VLD3LNd8_UPD = 1573, ARM_VLD3LNq16 = 1574, ARM_VLD3LNq16_UPD = 1577, ARM_VLD3LNq32 = 1578, ARM_VLD3LNq32_UPD = 1581, ARM_VLD3d16 = 1582, ARM_VLD3d16_UPD = 1585, ARM_VLD3d32 = 1586, ARM_VLD3d32_UPD = 1589, ARM_VLD3d8 = 1590, ARM_VLD3d8_UPD = 1593, ARM_VLD3q16 = 1594, ARM_VLD3q16_UPD = 1596, ARM_VLD3q32 = 1599, ARM_VLD3q32_UPD = 1601, ARM_VLD3q8 = 1604, ARM_VLD3q8_UPD = 1606, ARM_VLD4DUPd16 = 1609, ARM_VLD4DUPd16_UPD = 1612, ARM_VLD4DUPd32 = 1613, ARM_VLD4DUPd32_UPD = 1616, ARM_VLD4DUPd8 = 1617, ARM_VLD4DUPd8_UPD = 1620, ARM_VLD4DUPq16 = 1621, ARM_VLD4DUPq16_UPD = 1624, ARM_VLD4DUPq32 = 1625, ARM_VLD4DUPq32_UPD = 1628, ARM_VLD4DUPq8 = 1629, ARM_VLD4DUPq8_UPD = 1632, ARM_VLD4LNd16 = 1633, ARM_VLD4LNd16_UPD = 1636, ARM_VLD4LNd32 = 1637, ARM_VLD4LNd32_UPD = 1640, ARM_VLD4LNd8 = 1641, ARM_VLD4LNd8_UPD = 1644, ARM_VLD4LNq16 = 1645, ARM_VLD4LNq16_UPD = 1648, ARM_VLD4LNq32 = 1649, ARM_VLD4LNq32_UPD = 1652, ARM_VLD4d16 = 1653, ARM_VLD4d16_UPD = 1656, ARM_VLD4d32 = 1657, ARM_VLD4d32_UPD = 1660, ARM_VLD4d8 = 1661, ARM_VLD4d8_UPD = 1664, ARM_VLD4q16 = 1665, ARM_VLD4q16_UPD = 1667, ARM_VLD4q32 = 1670, ARM_VLD4q32_UPD = 1672, ARM_VLD4q8 = 1675, ARM_VLD4q8_UPD = 1677, ARM_VLDMDDB_UPD = 1680, ARM_VLDMDIA = 1681, ARM_VLDMDIA_UPD = 1682, ARM_VLDMQIA = 1683, ARM_VLDMSDB_UPD = 1684, ARM_VLDMSIA = 1685, ARM_VLDMSIA_UPD = 1686, ARM_VLDRD = 1687, ARM_VLDRH = 1688, ARM_VLDRS = 1689, ARM_VLLDM = 1690, ARM_VLSTM = 1691, ARM_VMAXNMD = 1692, ARM_VMAXNMH = 1693, ARM_VMAXNMNDf = 1694, ARM_VMAXNMNDh = 1695, ARM_VMAXNMNQf = 1696, ARM_VMAXNMNQh = 1697, ARM_VMAXNMS = 1698, ARM_VMAXfd = 1699, ARM_VMAXfq = 1700, ARM_VMAXhd = 1701, ARM_VMAXhq = 1702, ARM_VMAXsv16i8 = 1703, ARM_VMAXsv2i32 = 1704, ARM_VMAXsv4i16 = 1705, ARM_VMAXsv4i32 = 1706, ARM_VMAXsv8i16 = 1707, ARM_VMAXsv8i8 = 1708, ARM_VMAXuv16i8 = 1709, ARM_VMAXuv2i32 = 1710, ARM_VMAXuv4i16 = 1711, ARM_VMAXuv4i32 = 1712, ARM_VMAXuv8i16 = 1713, ARM_VMAXuv8i8 = 1714, ARM_VMINNMD = 1715, ARM_VMINNMH = 1716, ARM_VMINNMNDf = 1717, ARM_VMINNMNDh = 1718, ARM_VMINNMNQf = 1719, ARM_VMINNMNQh = 1720, ARM_VMINNMS = 1721, ARM_VMINfd = 1722, ARM_VMINfq = 1723, ARM_VMINhd = 1724, ARM_VMINhq = 1725, ARM_VMINsv16i8 = 1726, ARM_VMINsv2i32 = 1727, ARM_VMINsv4i16 = 1728, ARM_VMINsv4i32 = 1729, ARM_VMINsv8i16 = 1730, ARM_VMINsv8i8 = 1731, ARM_VMINuv16i8 = 1732, ARM_VMINuv2i32 = 1733, ARM_VMINuv4i16 = 1734, ARM_VMINuv4i32 = 1735, ARM_VMINuv8i16 = 1736, ARM_VMINuv8i8 = 1737, ARM_VMLAD = 1738, ARM_VMLAH = 1739, ARM_VMLALslsv2i32 = 1740, ARM_VMLALslsv4i16 = 1741, ARM_VMLALsluv2i32 = 1742, ARM_VMLALsluv4i16 = 1743, ARM_VMLALsv2i64 = 1744, ARM_VMLALsv4i32 = 1745, ARM_VMLALsv8i16 = 1746, ARM_VMLALuv2i64 = 1747, ARM_VMLALuv4i32 = 1748, ARM_VMLALuv8i16 = 1749, ARM_VMLAS = 1750, ARM_VMLAfd = 1751, ARM_VMLAfq = 1752, ARM_VMLAhd = 1753, ARM_VMLAhq = 1754, ARM_VMLAslfd = 1755, ARM_VMLAslfq = 1756, ARM_VMLAslhd = 1757, ARM_VMLAslhq = 1758, ARM_VMLAslv2i32 = 1759, ARM_VMLAslv4i16 = 1760, ARM_VMLAslv4i32 = 1761, ARM_VMLAslv8i16 = 1762, ARM_VMLAv16i8 = 1763, ARM_VMLAv2i32 = 1764, ARM_VMLAv4i16 = 1765, ARM_VMLAv4i32 = 1766, ARM_VMLAv8i16 = 1767, ARM_VMLAv8i8 = 1768, ARM_VMLSD = 1769, ARM_VMLSH = 1770, ARM_VMLSLslsv2i32 = 1771, ARM_VMLSLslsv4i16 = 1772, ARM_VMLSLsluv2i32 = 1773, ARM_VMLSLsluv4i16 = 1774, ARM_VMLSLsv2i64 = 1775, ARM_VMLSLsv4i32 = 1776, ARM_VMLSLsv8i16 = 1777, ARM_VMLSLuv2i64 = 1778, ARM_VMLSLuv4i32 = 1779, ARM_VMLSLuv8i16 = 1780, ARM_VMLSS = 1781, ARM_VMLSfd = 1782, ARM_VMLSfq = 1783, ARM_VMLShd = 1784, ARM_VMLShq = 1785, ARM_VMLSslfd = 1786, ARM_VMLSslfq = 1787, ARM_VMLSslhd = 1788, ARM_VMLSslhq = 1789, ARM_VMLSslv2i32 = 1790, ARM_VMLSslv4i16 = 1791, ARM_VMLSslv4i32 = 1792, ARM_VMLSslv8i16 = 1793, ARM_VMLSv16i8 = 1794, ARM_VMLSv2i32 = 1795, ARM_VMLSv4i16 = 1796, ARM_VMLSv4i32 = 1797, ARM_VMLSv8i16 = 1798, ARM_VMLSv8i8 = 1799, ARM_VMOVD = 1800, ARM_VMOVDRR = 1801, ARM_VMOVH = 1802, ARM_VMOVHR = 1803, ARM_VMOVLsv2i64 = 1804, ARM_VMOVLsv4i32 = 1805, ARM_VMOVLsv8i16 = 1806, ARM_VMOVLuv2i64 = 1807, ARM_VMOVLuv4i32 = 1808, ARM_VMOVLuv8i16 = 1809, ARM_VMOVNv2i32 = 1810, ARM_VMOVNv4i16 = 1811, ARM_VMOVNv8i8 = 1812, ARM_VMOVRH = 1813, ARM_VMOVRRD = 1814, ARM_VMOVRRS = 1815, ARM_VMOVRS = 1816, ARM_VMOVS = 1817, ARM_VMOVSR = 1818, ARM_VMOVSRR = 1819, ARM_VMOVv16i8 = 1820, ARM_VMOVv1i64 = 1821, ARM_VMOVv2f32 = 1822, ARM_VMOVv2i32 = 1823, ARM_VMOVv2i64 = 1824, ARM_VMOVv4f32 = 1825, ARM_VMOVv4i16 = 1826, ARM_VMOVv4i32 = 1827, ARM_VMOVv8i16 = 1828, ARM_VMOVv8i8 = 1829, ARM_VMRS = 1830, ARM_VMRS_FPEXC = 1831, ARM_VMRS_FPINST = 1832, ARM_VMRS_FPINST2 = 1833, ARM_VMRS_FPSID = 1834, ARM_VMRS_MVFR0 = 1835, ARM_VMRS_MVFR1 = 1836, ARM_VMRS_MVFR2 = 1837, ARM_VMSR = 1838, ARM_VMSR_FPEXC = 1839, ARM_VMSR_FPINST = 1840, ARM_VMSR_FPINST2 = 1841, ARM_VMSR_FPSID = 1842, ARM_VMULD = 1843, ARM_VMULH = 1844, ARM_VMULLp64 = 1845, ARM_VMULLp8 = 1846, ARM_VMULLslsv2i32 = 1847, ARM_VMULLslsv4i16 = 1848, ARM_VMULLsluv2i32 = 1849, ARM_VMULLsluv4i16 = 1850, ARM_VMULLsv2i64 = 1851, ARM_VMULLsv4i32 = 1852, ARM_VMULLsv8i16 = 1853, ARM_VMULLuv2i64 = 1854, ARM_VMULLuv4i32 = 1855, ARM_VMULLuv8i16 = 1856, ARM_VMULS = 1857, ARM_VMULfd = 1858, ARM_VMULfq = 1859, ARM_VMULhd = 1860, ARM_VMULhq = 1861, ARM_VMULpd = 1862, ARM_VMULpq = 1863, ARM_VMULslfd = 1864, ARM_VMULslfq = 1865, ARM_VMULslhd = 1866, ARM_VMULslhq = 1867, ARM_VMULslv2i32 = 1868, ARM_VMULslv4i16 = 1869, ARM_VMULslv4i32 = 1870, ARM_VMULslv8i16 = 1871, ARM_VMULv16i8 = 1872, ARM_VMULv2i32 = 1873, ARM_VMULv4i16 = 1874, ARM_VMULv4i32 = 1875, ARM_VMULv8i16 = 1876, ARM_VMULv8i8 = 1877, ARM_VMVNd = 1878, ARM_VMVNq = 1879, ARM_VMVNv2i32 = 1880, ARM_VMVNv4i16 = 1881, ARM_VMVNv4i32 = 1882, ARM_VMVNv8i16 = 1883, ARM_VNEGD = 1884, ARM_VNEGH = 1885, ARM_VNEGS = 1886, ARM_VNEGf32q = 1887, ARM_VNEGfd = 1888, ARM_VNEGhd = 1889, ARM_VNEGhq = 1890, ARM_VNEGs16d = 1891, ARM_VNEGs16q = 1892, ARM_VNEGs32d = 1893, ARM_VNEGs32q = 1894, ARM_VNEGs8d = 1895, ARM_VNEGs8q = 1896, ARM_VNMLAD = 1897, ARM_VNMLAH = 1898, ARM_VNMLAS = 1899, ARM_VNMLSD = 1900, ARM_VNMLSH = 1901, ARM_VNMLSS = 1902, ARM_VNMULD = 1903, ARM_VNMULH = 1904, ARM_VNMULS = 1905, ARM_VORNd = 1906, ARM_VORNq = 1907, ARM_VORRd = 1908, ARM_VORRiv2i32 = 1909, ARM_VORRiv4i16 = 1910, ARM_VORRiv4i32 = 1911, ARM_VORRiv8i16 = 1912, ARM_VORRq = 1913, ARM_VPADALsv16i8 = 1914, ARM_VPADALsv2i32 = 1915, ARM_VPADALsv4i16 = 1916, ARM_VPADALsv4i32 = 1917, ARM_VPADALsv8i16 = 1918, ARM_VPADALsv8i8 = 1919, ARM_VPADALuv16i8 = 1920, ARM_VPADALuv2i32 = 1921, ARM_VPADALuv4i16 = 1922, ARM_VPADALuv4i32 = 1923, ARM_VPADALuv8i16 = 1924, ARM_VPADALuv8i8 = 1925, ARM_VPADDLsv16i8 = 1926, ARM_VPADDLsv2i32 = 1927, ARM_VPADDLsv4i16 = 1928, ARM_VPADDLsv4i32 = 1929, ARM_VPADDLsv8i16 = 1930, ARM_VPADDLsv8i8 = 1931, ARM_VPADDLuv16i8 = 1932, ARM_VPADDLuv2i32 = 1933, ARM_VPADDLuv4i16 = 1934, ARM_VPADDLuv4i32 = 1935, ARM_VPADDLuv8i16 = 1936, ARM_VPADDLuv8i8 = 1937, ARM_VPADDf = 1938, ARM_VPADDh = 1939, ARM_VPADDi16 = 1940, ARM_VPADDi32 = 1941, ARM_VPADDi8 = 1942, ARM_VPMAXf = 1943, ARM_VPMAXh = 1944, ARM_VPMAXs16 = 1945, ARM_VPMAXs32 = 1946, ARM_VPMAXs8 = 1947, ARM_VPMAXu16 = 1948, ARM_VPMAXu32 = 1949, ARM_VPMAXu8 = 1950, ARM_VPMINf = 1951, ARM_VPMINh = 1952, ARM_VPMINs16 = 1953, ARM_VPMINs32 = 1954, ARM_VPMINs8 = 1955, ARM_VPMINu16 = 1956, ARM_VPMINu32 = 1957, ARM_VPMINu8 = 1958, ARM_VQABSv16i8 = 1959, ARM_VQABSv2i32 = 1960, ARM_VQABSv4i16 = 1961, ARM_VQABSv4i32 = 1962, ARM_VQABSv8i16 = 1963, ARM_VQABSv8i8 = 1964, ARM_VQADDsv16i8 = 1965, ARM_VQADDsv1i64 = 1966, ARM_VQADDsv2i32 = 1967, ARM_VQADDsv2i64 = 1968, ARM_VQADDsv4i16 = 1969, ARM_VQADDsv4i32 = 1970, ARM_VQADDsv8i16 = 1971, ARM_VQADDsv8i8 = 1972, ARM_VQADDuv16i8 = 1973, ARM_VQADDuv1i64 = 1974, ARM_VQADDuv2i32 = 1975, ARM_VQADDuv2i64 = 1976, ARM_VQADDuv4i16 = 1977, ARM_VQADDuv4i32 = 1978, ARM_VQADDuv8i16 = 1979, ARM_VQADDuv8i8 = 1980, ARM_VQDMLALslv2i32 = 1981, ARM_VQDMLALslv4i16 = 1982, ARM_VQDMLALv2i64 = 1983, ARM_VQDMLALv4i32 = 1984, ARM_VQDMLSLslv2i32 = 1985, ARM_VQDMLSLslv4i16 = 1986, ARM_VQDMLSLv2i64 = 1987, ARM_VQDMLSLv4i32 = 1988, ARM_VQDMULHslv2i32 = 1989, ARM_VQDMULHslv4i16 = 1990, ARM_VQDMULHslv4i32 = 1991, ARM_VQDMULHslv8i16 = 1992, ARM_VQDMULHv2i32 = 1993, ARM_VQDMULHv4i16 = 1994, ARM_VQDMULHv4i32 = 1995, ARM_VQDMULHv8i16 = 1996, ARM_VQDMULLslv2i32 = 1997, ARM_VQDMULLslv4i16 = 1998, ARM_VQDMULLv2i64 = 1999, ARM_VQDMULLv4i32 = 2000, ARM_VQMOVNsuv2i32 = 2001, ARM_VQMOVNsuv4i16 = 2002, ARM_VQMOVNsuv8i8 = 2003, ARM_VQMOVNsv2i32 = 2004, ARM_VQMOVNsv4i16 = 2005, ARM_VQMOVNsv8i8 = 2006, ARM_VQMOVNuv2i32 = 2007, ARM_VQMOVNuv4i16 = 2008, ARM_VQMOVNuv8i8 = 2009, ARM_VQNEGv16i8 = 2010, ARM_VQNEGv2i32 = 2011, ARM_VQNEGv4i16 = 2012, ARM_VQNEGv4i32 = 2013, ARM_VQNEGv8i16 = 2014, ARM_VQNEGv8i8 = 2015, ARM_VQRDMLAHslv2i32 = 2016, ARM_VQRDMLAHslv4i16 = 2017, ARM_VQRDMLAHslv4i32 = 2018, ARM_VQRDMLAHslv8i16 = 2019, ARM_VQRDMLAHv2i32 = 2020, ARM_VQRDMLAHv4i16 = 2021, ARM_VQRDMLAHv4i32 = 2022, ARM_VQRDMLAHv8i16 = 2023, ARM_VQRDMLSHslv2i32 = 2024, ARM_VQRDMLSHslv4i16 = 2025, ARM_VQRDMLSHslv4i32 = 2026, ARM_VQRDMLSHslv8i16 = 2027, ARM_VQRDMLSHv2i32 = 2028, ARM_VQRDMLSHv4i16 = 2029, ARM_VQRDMLSHv4i32 = 2030, ARM_VQRDMLSHv8i16 = 2031, ARM_VQRDMULHslv2i32 = 2032, ARM_VQRDMULHslv4i16 = 2033, ARM_VQRDMULHslv4i32 = 2034, ARM_VQRDMULHslv8i16 = 2035, ARM_VQRDMULHv2i32 = 2036, ARM_VQRDMULHv4i16 = 2037, ARM_VQRDMULHv4i32 = 2038, ARM_VQRDMULHv8i16 = 2039, ARM_VQRSHLsv16i8 = 2040, ARM_VQRSHLsv1i64 = 2041, ARM_VQRSHLsv2i32 = 2042, ARM_VQRSHLsv2i64 = 2043, ARM_VQRSHLsv4i16 = 2044, ARM_VQRSHLsv4i32 = 2045, ARM_VQRSHLsv8i16 = 2046, ARM_VQRSHLsv8i8 = 2047, ARM_VQRSHLuv16i8 = 2048, ARM_VQRSHLuv1i64 = 2049, ARM_VQRSHLuv2i32 = 2050, ARM_VQRSHLuv2i64 = 2051, ARM_VQRSHLuv4i16 = 2052, ARM_VQRSHLuv4i32 = 2053, ARM_VQRSHLuv8i16 = 2054, ARM_VQRSHLuv8i8 = 2055, ARM_VQRSHRNsv2i32 = 2056, ARM_VQRSHRNsv4i16 = 2057, ARM_VQRSHRNsv8i8 = 2058, ARM_VQRSHRNuv2i32 = 2059, ARM_VQRSHRNuv4i16 = 2060, ARM_VQRSHRNuv8i8 = 2061, ARM_VQRSHRUNv2i32 = 2062, ARM_VQRSHRUNv4i16 = 2063, ARM_VQRSHRUNv8i8 = 2064, ARM_VQSHLsiv16i8 = 2065, ARM_VQSHLsiv1i64 = 2066, ARM_VQSHLsiv2i32 = 2067, ARM_VQSHLsiv2i64 = 2068, ARM_VQSHLsiv4i16 = 2069, ARM_VQSHLsiv4i32 = 2070, ARM_VQSHLsiv8i16 = 2071, ARM_VQSHLsiv8i8 = 2072, ARM_VQSHLsuv16i8 = 2073, ARM_VQSHLsuv1i64 = 2074, ARM_VQSHLsuv2i32 = 2075, ARM_VQSHLsuv2i64 = 2076, ARM_VQSHLsuv4i16 = 2077, ARM_VQSHLsuv4i32 = 2078, ARM_VQSHLsuv8i16 = 2079, ARM_VQSHLsuv8i8 = 2080, ARM_VQSHLsv16i8 = 2081, ARM_VQSHLsv1i64 = 2082, ARM_VQSHLsv2i32 = 2083, ARM_VQSHLsv2i64 = 2084, ARM_VQSHLsv4i16 = 2085, ARM_VQSHLsv4i32 = 2086, ARM_VQSHLsv8i16 = 2087, ARM_VQSHLsv8i8 = 2088, ARM_VQSHLuiv16i8 = 2089, ARM_VQSHLuiv1i64 = 2090, ARM_VQSHLuiv2i32 = 2091, ARM_VQSHLuiv2i64 = 2092, ARM_VQSHLuiv4i16 = 2093, ARM_VQSHLuiv4i32 = 2094, ARM_VQSHLuiv8i16 = 2095, ARM_VQSHLuiv8i8 = 2096, ARM_VQSHLuv16i8 = 2097, ARM_VQSHLuv1i64 = 2098, ARM_VQSHLuv2i32 = 2099, ARM_VQSHLuv2i64 = 2100, ARM_VQSHLuv4i16 = 2101, ARM_VQSHLuv4i32 = 2102, ARM_VQSHLuv8i16 = 2103, ARM_VQSHLuv8i8 = 2104, ARM_VQSHRNsv2i32 = 2105, ARM_VQSHRNsv4i16 = 2106, ARM_VQSHRNsv8i8 = 2107, ARM_VQSHRNuv2i32 = 2108, ARM_VQSHRNuv4i16 = 2109, ARM_VQSHRNuv8i8 = 2110, ARM_VQSHRUNv2i32 = 2111, ARM_VQSHRUNv4i16 = 2112, ARM_VQSHRUNv8i8 = 2113, ARM_VQSUBsv16i8 = 2114, ARM_VQSUBsv1i64 = 2115, ARM_VQSUBsv2i32 = 2116, ARM_VQSUBsv2i64 = 2117, ARM_VQSUBsv4i16 = 2118, ARM_VQSUBsv4i32 = 2119, ARM_VQSUBsv8i16 = 2120, ARM_VQSUBsv8i8 = 2121, ARM_VQSUBuv16i8 = 2122, ARM_VQSUBuv1i64 = 2123, ARM_VQSUBuv2i32 = 2124, ARM_VQSUBuv2i64 = 2125, ARM_VQSUBuv4i16 = 2126, ARM_VQSUBuv4i32 = 2127, ARM_VQSUBuv8i16 = 2128, ARM_VQSUBuv8i8 = 2129, ARM_VRADDHNv2i32 = 2130, ARM_VRADDHNv4i16 = 2131, ARM_VRADDHNv8i8 = 2132, ARM_VRECPEd = 2133, ARM_VRECPEfd = 2134, ARM_VRECPEfq = 2135, ARM_VRECPEhd = 2136, ARM_VRECPEhq = 2137, ARM_VRECPEq = 2138, ARM_VRECPSfd = 2139, ARM_VRECPSfq = 2140, ARM_VRECPShd = 2141, ARM_VRECPShq = 2142, ARM_VREV16d8 = 2143, ARM_VREV16q8 = 2144, ARM_VREV32d16 = 2145, ARM_VREV32d8 = 2146, ARM_VREV32q16 = 2147, ARM_VREV32q8 = 2148, ARM_VREV64d16 = 2149, ARM_VREV64d32 = 2150, ARM_VREV64d8 = 2151, ARM_VREV64q16 = 2152, ARM_VREV64q32 = 2153, ARM_VREV64q8 = 2154, ARM_VRHADDsv16i8 = 2155, ARM_VRHADDsv2i32 = 2156, ARM_VRHADDsv4i16 = 2157, ARM_VRHADDsv4i32 = 2158, ARM_VRHADDsv8i16 = 2159, ARM_VRHADDsv8i8 = 2160, ARM_VRHADDuv16i8 = 2161, ARM_VRHADDuv2i32 = 2162, ARM_VRHADDuv4i16 = 2163, ARM_VRHADDuv4i32 = 2164, ARM_VRHADDuv8i16 = 2165, ARM_VRHADDuv8i8 = 2166, ARM_VRINTAD = 2167, ARM_VRINTAH = 2168, ARM_VRINTANDf = 2169, ARM_VRINTANDh = 2170, ARM_VRINTANQf = 2171, ARM_VRINTANQh = 2172, ARM_VRINTAS = 2173, ARM_VRINTMD = 2174, ARM_VRINTMH = 2175, ARM_VRINTMNDf = 2176, ARM_VRINTMNDh = 2177, ARM_VRINTMNQf = 2178, ARM_VRINTMNQh = 2179, ARM_VRINTMS = 2180, ARM_VRINTND = 2181, ARM_VRINTNH = 2182, ARM_VRINTNNDf = 2183, ARM_VRINTNNDh = 2184, ARM_VRINTNNQf = 2185, ARM_VRINTNNQh = 2186, ARM_VRINTNS = 2187, ARM_VRINTPD = 2188, ARM_VRINTPH = 2189, ARM_VRINTPNDf = 2190, ARM_VRINTPNDh = 2191, ARM_VRINTPNQf = 2192, ARM_VRINTPNQh = 2193, ARM_VRINTPS = 2194, ARM_VRINTRD = 2195, ARM_VRINTRH = 2196, ARM_VRINTRS = 2197, ARM_VRINTXD = 2198, ARM_VRINTXH = 2199, ARM_VRINTXNDf = 2200, ARM_VRINTXNDh = 2201, ARM_VRINTXNQf = 2202, ARM_VRINTXNQh = 2203, ARM_VRINTXS = 2204, ARM_VRINTZD = 2205, ARM_VRINTZH = 2206, ARM_VRINTZNDf = 2207, ARM_VRINTZNDh = 2208, ARM_VRINTZNQf = 2209, ARM_VRINTZNQh = 2210, ARM_VRINTZS = 2211, ARM_VRSHLsv16i8 = 2212, ARM_VRSHLsv1i64 = 2213, ARM_VRSHLsv2i32 = 2214, ARM_VRSHLsv2i64 = 2215, ARM_VRSHLsv4i16 = 2216, ARM_VRSHLsv4i32 = 2217, ARM_VRSHLsv8i16 = 2218, ARM_VRSHLsv8i8 = 2219, ARM_VRSHLuv16i8 = 2220, ARM_VRSHLuv1i64 = 2221, ARM_VRSHLuv2i32 = 2222, ARM_VRSHLuv2i64 = 2223, ARM_VRSHLuv4i16 = 2224, ARM_VRSHLuv4i32 = 2225, ARM_VRSHLuv8i16 = 2226, ARM_VRSHLuv8i8 = 2227, ARM_VRSHRNv2i32 = 2228, ARM_VRSHRNv4i16 = 2229, ARM_VRSHRNv8i8 = 2230, ARM_VRSHRsv16i8 = 2231, ARM_VRSHRsv1i64 = 2232, ARM_VRSHRsv2i32 = 2233, ARM_VRSHRsv2i64 = 2234, ARM_VRSHRsv4i16 = 2235, ARM_VRSHRsv4i32 = 2236, ARM_VRSHRsv8i16 = 2237, ARM_VRSHRsv8i8 = 2238, ARM_VRSHRuv16i8 = 2239, ARM_VRSHRuv1i64 = 2240, ARM_VRSHRuv2i32 = 2241, ARM_VRSHRuv2i64 = 2242, ARM_VRSHRuv4i16 = 2243, ARM_VRSHRuv4i32 = 2244, ARM_VRSHRuv8i16 = 2245, ARM_VRSHRuv8i8 = 2246, ARM_VRSQRTEd = 2247, ARM_VRSQRTEfd = 2248, ARM_VRSQRTEfq = 2249, ARM_VRSQRTEhd = 2250, ARM_VRSQRTEhq = 2251, ARM_VRSQRTEq = 2252, ARM_VRSQRTSfd = 2253, ARM_VRSQRTSfq = 2254, ARM_VRSQRTShd = 2255, ARM_VRSQRTShq = 2256, ARM_VRSRAsv16i8 = 2257, ARM_VRSRAsv1i64 = 2258, ARM_VRSRAsv2i32 = 2259, ARM_VRSRAsv2i64 = 2260, ARM_VRSRAsv4i16 = 2261, ARM_VRSRAsv4i32 = 2262, ARM_VRSRAsv8i16 = 2263, ARM_VRSRAsv8i8 = 2264, ARM_VRSRAuv16i8 = 2265, ARM_VRSRAuv1i64 = 2266, ARM_VRSRAuv2i32 = 2267, ARM_VRSRAuv2i64 = 2268, ARM_VRSRAuv4i16 = 2269, ARM_VRSRAuv4i32 = 2270, ARM_VRSRAuv8i16 = 2271, ARM_VRSRAuv8i8 = 2272, ARM_VRSUBHNv2i32 = 2273, ARM_VRSUBHNv4i16 = 2274, ARM_VRSUBHNv8i8 = 2275, ARM_VSDOTD = 2276, ARM_VSDOTDI = 2277, ARM_VSDOTQ = 2278, ARM_VSDOTQI = 2279, ARM_VSELEQD = 2280, ARM_VSELEQH = 2281, ARM_VSELEQS = 2282, ARM_VSELGED = 2283, ARM_VSELGEH = 2284, ARM_VSELGES = 2285, ARM_VSELGTD = 2286, ARM_VSELGTH = 2287, ARM_VSELGTS = 2288, ARM_VSELVSD = 2289, ARM_VSELVSH = 2290, ARM_VSELVSS = 2291, ARM_VSETLNi16 = 2292, ARM_VSETLNi32 = 2293, ARM_VSETLNi8 = 2294, ARM_VSHLLi16 = 2295, ARM_VSHLLi32 = 2296, ARM_VSHLLi8 = 2297, ARM_VSHLLsv2i64 = 2298, ARM_VSHLLsv4i32 = 2299, ARM_VSHLLsv8i16 = 2300, ARM_VSHLLuv2i64 = 2301, ARM_VSHLLuv4i32 = 2302, ARM_VSHLLuv8i16 = 2303, ARM_VSHLiv16i8 = 2304, ARM_VSHLiv1i64 = 2305, ARM_VSHLiv2i32 = 2306, ARM_VSHLiv2i64 = 2307, ARM_VSHLiv4i16 = 2308, ARM_VSHLiv4i32 = 2309, ARM_VSHLiv8i16 = 2310, ARM_VSHLiv8i8 = 2311, ARM_VSHLsv16i8 = 2312, ARM_VSHLsv1i64 = 2313, ARM_VSHLsv2i32 = 2314, ARM_VSHLsv2i64 = 2315, ARM_VSHLsv4i16 = 2316, ARM_VSHLsv4i32 = 2317, ARM_VSHLsv8i16 = 2318, ARM_VSHLsv8i8 = 2319, ARM_VSHLuv16i8 = 2320, ARM_VSHLuv1i64 = 2321, ARM_VSHLuv2i32 = 2322, ARM_VSHLuv2i64 = 2323, ARM_VSHLuv4i16 = 2324, ARM_VSHLuv4i32 = 2325, ARM_VSHLuv8i16 = 2326, ARM_VSHLuv8i8 = 2327, ARM_VSHRNv2i32 = 2328, ARM_VSHRNv4i16 = 2329, ARM_VSHRNv8i8 = 2330, ARM_VSHRsv16i8 = 2331, ARM_VSHRsv1i64 = 2332, ARM_VSHRsv2i32 = 2333, ARM_VSHRsv2i64 = 2334, ARM_VSHRsv4i16 = 2335, ARM_VSHRsv4i32 = 2336, ARM_VSHRsv8i16 = 2337, ARM_VSHRsv8i8 = 2338, ARM_VSHRuv16i8 = 2339, ARM_VSHRuv1i64 = 2340, ARM_VSHRuv2i32 = 2341, ARM_VSHRuv2i64 = 2342, ARM_VSHRuv4i16 = 2343, ARM_VSHRuv4i32 = 2344, ARM_VSHRuv8i16 = 2345, ARM_VSHRuv8i8 = 2346, ARM_VSHTOD = 2347, ARM_VSHTOH = 2348, ARM_VSHTOS = 2349, ARM_VSITOD = 2350, ARM_VSITOH = 2351, ARM_VSITOS = 2352, ARM_VSLIv16i8 = 2353, ARM_VSLIv1i64 = 2354, ARM_VSLIv2i32 = 2355, ARM_VSLIv2i64 = 2356, ARM_VSLIv4i16 = 2357, ARM_VSLIv4i32 = 2358, ARM_VSLIv8i16 = 2359, ARM_VSLIv8i8 = 2360, ARM_VSLTOD = 2361, ARM_VSLTOH = 2362, ARM_VSLTOS = 2363, ARM_VSQRTD = 2364, ARM_VSQRTH = 2365, ARM_VSQRTS = 2366, ARM_VSRAsv16i8 = 2367, ARM_VSRAsv1i64 = 2368, ARM_VSRAsv2i32 = 2369, ARM_VSRAsv2i64 = 2370, ARM_VSRAsv4i16 = 2371, ARM_VSRAsv4i32 = 2372, ARM_VSRAsv8i16 = 2373, ARM_VSRAsv8i8 = 2374, ARM_VSRAuv16i8 = 2375, ARM_VSRAuv1i64 = 2376, ARM_VSRAuv2i32 = 2377, ARM_VSRAuv2i64 = 2378, ARM_VSRAuv4i16 = 2379, ARM_VSRAuv4i32 = 2380, ARM_VSRAuv8i16 = 2381, ARM_VSRAuv8i8 = 2382, ARM_VSRIv16i8 = 2383, ARM_VSRIv1i64 = 2384, ARM_VSRIv2i32 = 2385, ARM_VSRIv2i64 = 2386, ARM_VSRIv4i16 = 2387, ARM_VSRIv4i32 = 2388, ARM_VSRIv8i16 = 2389, ARM_VSRIv8i8 = 2390, ARM_VST1LNd16 = 2391, ARM_VST1LNd16_UPD = 2392, ARM_VST1LNd32 = 2393, ARM_VST1LNd32_UPD = 2394, ARM_VST1LNd8 = 2395, ARM_VST1LNd8_UPD = 2396, ARM_VST1d16 = 2403, ARM_VST1d16Q = 2404, ARM_VST1d16Qwb_fixed = 2406, ARM_VST1d16Qwb_register = 2407, ARM_VST1d16T = 2408, ARM_VST1d16Twb_fixed = 2410, ARM_VST1d16Twb_register = 2411, ARM_VST1d16wb_fixed = 2412, ARM_VST1d16wb_register = 2413, ARM_VST1d32 = 2414, ARM_VST1d32Q = 2415, ARM_VST1d32Qwb_fixed = 2417, ARM_VST1d32Qwb_register = 2418, ARM_VST1d32T = 2419, ARM_VST1d32Twb_fixed = 2421, ARM_VST1d32Twb_register = 2422, ARM_VST1d32wb_fixed = 2423, ARM_VST1d32wb_register = 2424, ARM_VST1d64 = 2425, ARM_VST1d64Q = 2426, ARM_VST1d64Qwb_fixed = 2430, ARM_VST1d64Qwb_register = 2431, ARM_VST1d64T = 2432, ARM_VST1d64Twb_fixed = 2436, ARM_VST1d64Twb_register = 2437, ARM_VST1d64wb_fixed = 2438, ARM_VST1d64wb_register = 2439, ARM_VST1d8 = 2440, ARM_VST1d8Q = 2441, ARM_VST1d8Qwb_fixed = 2443, ARM_VST1d8Qwb_register = 2444, ARM_VST1d8T = 2445, ARM_VST1d8Twb_fixed = 2447, ARM_VST1d8Twb_register = 2448, ARM_VST1d8wb_fixed = 2449, ARM_VST1d8wb_register = 2450, ARM_VST1q16 = 2451, ARM_VST1q16wb_fixed = 2456, ARM_VST1q16wb_register = 2457, ARM_VST1q32 = 2458, ARM_VST1q32wb_fixed = 2463, ARM_VST1q32wb_register = 2464, ARM_VST1q64 = 2465, ARM_VST1q64wb_fixed = 2470, ARM_VST1q64wb_register = 2471, ARM_VST1q8 = 2472, ARM_VST1q8wb_fixed = 2477, ARM_VST1q8wb_register = 2478, ARM_VST2LNd16 = 2479, ARM_VST2LNd16_UPD = 2482, ARM_VST2LNd32 = 2483, ARM_VST2LNd32_UPD = 2486, ARM_VST2LNd8 = 2487, ARM_VST2LNd8_UPD = 2490, ARM_VST2LNq16 = 2491, ARM_VST2LNq16_UPD = 2494, ARM_VST2LNq32 = 2495, ARM_VST2LNq32_UPD = 2498, ARM_VST2b16 = 2499, ARM_VST2b16wb_fixed = 2500, ARM_VST2b16wb_register = 2501, ARM_VST2b32 = 2502, ARM_VST2b32wb_fixed = 2503, ARM_VST2b32wb_register = 2504, ARM_VST2b8 = 2505, ARM_VST2b8wb_fixed = 2506, ARM_VST2b8wb_register = 2507, ARM_VST2d16 = 2508, ARM_VST2d16wb_fixed = 2509, ARM_VST2d16wb_register = 2510, ARM_VST2d32 = 2511, ARM_VST2d32wb_fixed = 2512, ARM_VST2d32wb_register = 2513, ARM_VST2d8 = 2514, ARM_VST2d8wb_fixed = 2515, ARM_VST2d8wb_register = 2516, ARM_VST2q16 = 2517, ARM_VST2q16wb_fixed = 2521, ARM_VST2q16wb_register = 2522, ARM_VST2q32 = 2523, ARM_VST2q32wb_fixed = 2527, ARM_VST2q32wb_register = 2528, ARM_VST2q8 = 2529, ARM_VST2q8wb_fixed = 2533, ARM_VST2q8wb_register = 2534, ARM_VST3LNd16 = 2535, ARM_VST3LNd16_UPD = 2538, ARM_VST3LNd32 = 2539, ARM_VST3LNd32_UPD = 2542, ARM_VST3LNd8 = 2543, ARM_VST3LNd8_UPD = 2546, ARM_VST3LNq16 = 2547, ARM_VST3LNq16_UPD = 2550, ARM_VST3LNq32 = 2551, ARM_VST3LNq32_UPD = 2554, ARM_VST3d16 = 2555, ARM_VST3d16_UPD = 2558, ARM_VST3d32 = 2559, ARM_VST3d32_UPD = 2562, ARM_VST3d8 = 2563, ARM_VST3d8_UPD = 2566, ARM_VST3q16 = 2567, ARM_VST3q16_UPD = 2569, ARM_VST3q32 = 2572, ARM_VST3q32_UPD = 2574, ARM_VST3q8 = 2577, ARM_VST3q8_UPD = 2579, ARM_VST4LNd16 = 2582, ARM_VST4LNd16_UPD = 2585, ARM_VST4LNd32 = 2586, ARM_VST4LNd32_UPD = 2589, ARM_VST4LNd8 = 2590, ARM_VST4LNd8_UPD = 2593, ARM_VST4LNq16 = 2594, ARM_VST4LNq16_UPD = 2597, ARM_VST4LNq32 = 2598, ARM_VST4LNq32_UPD = 2601, ARM_VST4d16 = 2602, ARM_VST4d16_UPD = 2605, ARM_VST4d32 = 2606, ARM_VST4d32_UPD = 2609, ARM_VST4d8 = 2610, ARM_VST4d8_UPD = 2613, ARM_VST4q16 = 2614, ARM_VST4q16_UPD = 2616, ARM_VST4q32 = 2619, ARM_VST4q32_UPD = 2621, ARM_VST4q8 = 2624, ARM_VST4q8_UPD = 2626, ARM_VSTMDDB_UPD = 2629, ARM_VSTMDIA = 2630, ARM_VSTMDIA_UPD = 2631, ARM_VSTMQIA = 2632, ARM_VSTMSDB_UPD = 2633, ARM_VSTMSIA = 2634, ARM_VSTMSIA_UPD = 2635, ARM_VSTRD = 2636, ARM_VSTRH = 2637, ARM_VSTRS = 2638, ARM_VSUBD = 2639, ARM_VSUBH = 2640, ARM_VSUBHNv2i32 = 2641, ARM_VSUBHNv4i16 = 2642, ARM_VSUBHNv8i8 = 2643, ARM_VSUBLsv2i64 = 2644, ARM_VSUBLsv4i32 = 2645, ARM_VSUBLsv8i16 = 2646, ARM_VSUBLuv2i64 = 2647, ARM_VSUBLuv4i32 = 2648, ARM_VSUBLuv8i16 = 2649, ARM_VSUBS = 2650, ARM_VSUBWsv2i64 = 2651, ARM_VSUBWsv4i32 = 2652, ARM_VSUBWsv8i16 = 2653, ARM_VSUBWuv2i64 = 2654, ARM_VSUBWuv4i32 = 2655, ARM_VSUBWuv8i16 = 2656, ARM_VSUBfd = 2657, ARM_VSUBfq = 2658, ARM_VSUBhd = 2659, ARM_VSUBhq = 2660, ARM_VSUBv16i8 = 2661, ARM_VSUBv1i64 = 2662, ARM_VSUBv2i32 = 2663, ARM_VSUBv2i64 = 2664, ARM_VSUBv4i16 = 2665, ARM_VSUBv4i32 = 2666, ARM_VSUBv8i16 = 2667, ARM_VSUBv8i8 = 2668, ARM_VSWPd = 2669, ARM_VSWPq = 2670, ARM_VTBL1 = 2671, ARM_VTBL2 = 2672, ARM_VTBL3 = 2673, ARM_VTBL4 = 2675, ARM_VTBX1 = 2677, ARM_VTBX2 = 2678, ARM_VTBX3 = 2679, ARM_VTBX4 = 2681, ARM_VTOSHD = 2683, ARM_VTOSHH = 2684, ARM_VTOSHS = 2685, ARM_VTOSIRD = 2686, ARM_VTOSIRH = 2687, ARM_VTOSIRS = 2688, ARM_VTOSIZD = 2689, ARM_VTOSIZH = 2690, ARM_VTOSIZS = 2691, ARM_VTOSLD = 2692, ARM_VTOSLH = 2693, ARM_VTOSLS = 2694, ARM_VTOUHD = 2695, ARM_VTOUHH = 2696, ARM_VTOUHS = 2697, ARM_VTOUIRD = 2698, ARM_VTOUIRH = 2699, ARM_VTOUIRS = 2700, ARM_VTOUIZD = 2701, ARM_VTOUIZH = 2702, ARM_VTOUIZS = 2703, ARM_VTOULD = 2704, ARM_VTOULH = 2705, ARM_VTOULS = 2706, ARM_VTRNd16 = 2707, ARM_VTRNd32 = 2708, ARM_VTRNd8 = 2709, ARM_VTRNq16 = 2710, ARM_VTRNq32 = 2711, ARM_VTRNq8 = 2712, ARM_VTSTv16i8 = 2713, ARM_VTSTv2i32 = 2714, ARM_VTSTv4i16 = 2715, ARM_VTSTv4i32 = 2716, ARM_VTSTv8i16 = 2717, ARM_VTSTv8i8 = 2718, ARM_VUDOTD = 2719, ARM_VUDOTDI = 2720, ARM_VUDOTQ = 2721, ARM_VUDOTQI = 2722, ARM_VUHTOD = 2723, ARM_VUHTOH = 2724, ARM_VUHTOS = 2725, ARM_VUITOD = 2726, ARM_VUITOH = 2727, ARM_VUITOS = 2728, ARM_VULTOD = 2729, ARM_VULTOH = 2730, ARM_VULTOS = 2731, ARM_VUZPd16 = 2732, ARM_VUZPd8 = 2733, ARM_VUZPq16 = 2734, ARM_VUZPq32 = 2735, ARM_VUZPq8 = 2736, ARM_VZIPd16 = 2737, ARM_VZIPd8 = 2738, ARM_VZIPq16 = 2739, ARM_VZIPq32 = 2740, ARM_VZIPq8 = 2741, ARM_sysLDMDA = 2742, ARM_sysLDMDA_UPD = 2743, ARM_sysLDMDB = 2744, ARM_sysLDMDB_UPD = 2745, ARM_sysLDMIA = 2746, ARM_sysLDMIA_UPD = 2747, ARM_sysLDMIB = 2748, ARM_sysLDMIB_UPD = 2749, ARM_sysSTMDA = 2750, ARM_sysSTMDA_UPD = 2751, ARM_sysSTMDB = 2752, ARM_sysSTMDB_UPD = 2753, ARM_sysSTMIA = 2754, ARM_sysSTMIA_UPD = 2755, ARM_sysSTMIB = 2756, ARM_sysSTMIB_UPD = 2757, ARM_t2ADCri = 2758, ARM_t2ADCrr = 2759, ARM_t2ADCrs = 2760, ARM_t2ADDri = 2761, ARM_t2ADDri12 = 2762, ARM_t2ADDrr = 2763, ARM_t2ADDrs = 2764, ARM_t2ADR = 2765, ARM_t2ANDri = 2766, ARM_t2ANDrr = 2767, ARM_t2ANDrs = 2768, ARM_t2ASRri = 2769, ARM_t2ASRrr = 2770, ARM_t2B = 2771, ARM_t2BFC = 2772, ARM_t2BFI = 2773, ARM_t2BICri = 2774, ARM_t2BICrr = 2775, ARM_t2BICrs = 2776, ARM_t2BXJ = 2777, ARM_t2Bcc = 2778, ARM_t2CDP = 2779, ARM_t2CDP2 = 2780, ARM_t2CLREX = 2781, ARM_t2CLZ = 2782, ARM_t2CMNri = 2783, ARM_t2CMNzrr = 2784, ARM_t2CMNzrs = 2785, ARM_t2CMPri = 2786, ARM_t2CMPrr = 2787, ARM_t2CMPrs = 2788, ARM_t2CPS1p = 2789, ARM_t2CPS2p = 2790, ARM_t2CPS3p = 2791, ARM_t2CRC32B = 2792, ARM_t2CRC32CB = 2793, ARM_t2CRC32CH = 2794, ARM_t2CRC32CW = 2795, ARM_t2CRC32H = 2796, ARM_t2CRC32W = 2797, ARM_t2DBG = 2798, ARM_t2DCPS1 = 2799, ARM_t2DCPS2 = 2800, ARM_t2DCPS3 = 2801, ARM_t2DMB = 2802, ARM_t2DSB = 2803, ARM_t2EORri = 2804, ARM_t2EORrr = 2805, ARM_t2EORrs = 2806, ARM_t2HINT = 2807, ARM_t2HVC = 2808, ARM_t2ISB = 2809, ARM_t2IT = 2810, ARM_t2LDA = 2813, ARM_t2LDAB = 2814, ARM_t2LDAEX = 2815, ARM_t2LDAEXB = 2816, ARM_t2LDAEXD = 2817, ARM_t2LDAEXH = 2818, ARM_t2LDAH = 2819, ARM_t2LDC2L_OFFSET = 2820, ARM_t2LDC2L_OPTION = 2821, ARM_t2LDC2L_POST = 2822, ARM_t2LDC2L_PRE = 2823, ARM_t2LDC2_OFFSET = 2824, ARM_t2LDC2_OPTION = 2825, ARM_t2LDC2_POST = 2826, ARM_t2LDC2_PRE = 2827, ARM_t2LDCL_OFFSET = 2828, ARM_t2LDCL_OPTION = 2829, ARM_t2LDCL_POST = 2830, ARM_t2LDCL_PRE = 2831, ARM_t2LDC_OFFSET = 2832, ARM_t2LDC_OPTION = 2833, ARM_t2LDC_POST = 2834, ARM_t2LDC_PRE = 2835, ARM_t2LDMDB = 2836, ARM_t2LDMDB_UPD = 2837, ARM_t2LDMIA = 2838, ARM_t2LDMIA_UPD = 2839, ARM_t2LDRBT = 2840, ARM_t2LDRB_POST = 2841, ARM_t2LDRB_PRE = 2842, ARM_t2LDRBi12 = 2843, ARM_t2LDRBi8 = 2844, ARM_t2LDRBpci = 2845, ARM_t2LDRBs = 2846, ARM_t2LDRD_POST = 2847, ARM_t2LDRD_PRE = 2848, ARM_t2LDRDi8 = 2849, ARM_t2LDREX = 2850, ARM_t2LDREXB = 2851, ARM_t2LDREXD = 2852, ARM_t2LDREXH = 2853, ARM_t2LDRHT = 2854, ARM_t2LDRH_POST = 2855, ARM_t2LDRH_PRE = 2856, ARM_t2LDRHi12 = 2857, ARM_t2LDRHi8 = 2858, ARM_t2LDRHpci = 2859, ARM_t2LDRHs = 2860, ARM_t2LDRSBT = 2861, ARM_t2LDRSB_POST = 2862, ARM_t2LDRSB_PRE = 2863, ARM_t2LDRSBi12 = 2864, ARM_t2LDRSBi8 = 2865, ARM_t2LDRSBpci = 2866, ARM_t2LDRSBs = 2867, ARM_t2LDRSHT = 2868, ARM_t2LDRSH_POST = 2869, ARM_t2LDRSH_PRE = 2870, ARM_t2LDRSHi12 = 2871, ARM_t2LDRSHi8 = 2872, ARM_t2LDRSHpci = 2873, ARM_t2LDRSHs = 2874, ARM_t2LDRT = 2875, ARM_t2LDR_POST = 2876, ARM_t2LDR_PRE = 2877, ARM_t2LDRi12 = 2878, ARM_t2LDRi8 = 2879, ARM_t2LDRpci = 2880, ARM_t2LDRs = 2881, ARM_t2LSLri = 2882, ARM_t2LSLrr = 2883, ARM_t2LSRri = 2884, ARM_t2LSRrr = 2885, ARM_t2MCR = 2886, ARM_t2MCR2 = 2887, ARM_t2MCRR = 2888, ARM_t2MCRR2 = 2889, ARM_t2MLA = 2890, ARM_t2MLS = 2891, ARM_t2MOVTi16 = 2892, ARM_t2MOVi = 2893, ARM_t2MOVi16 = 2894, ARM_t2MOVr = 2895, ARM_t2MOVsra_flag = 2896, ARM_t2MOVsrl_flag = 2897, ARM_t2MRC = 2898, ARM_t2MRC2 = 2899, ARM_t2MRRC = 2900, ARM_t2MRRC2 = 2901, ARM_t2MRS_AR = 2902, ARM_t2MRS_M = 2903, ARM_t2MRSbanked = 2904, ARM_t2MRSsys_AR = 2905, ARM_t2MSR_AR = 2906, ARM_t2MSR_M = 2907, ARM_t2MSRbanked = 2908, ARM_t2MUL = 2909, ARM_t2MVNi = 2910, ARM_t2MVNr = 2911, ARM_t2MVNs = 2912, ARM_t2ORNri = 2913, ARM_t2ORNrr = 2914, ARM_t2ORNrs = 2915, ARM_t2ORRri = 2916, ARM_t2ORRrr = 2917, ARM_t2ORRrs = 2918, ARM_t2PKHBT = 2919, ARM_t2PKHTB = 2920, ARM_t2PLDWi12 = 2921, ARM_t2PLDWi8 = 2922, ARM_t2PLDWs = 2923, ARM_t2PLDi12 = 2924, ARM_t2PLDi8 = 2925, ARM_t2PLDpci = 2926, ARM_t2PLDs = 2927, ARM_t2PLIi12 = 2928, ARM_t2PLIi8 = 2929, ARM_t2PLIpci = 2930, ARM_t2PLIs = 2931, ARM_t2QADD = 2932, ARM_t2QADD16 = 2933, ARM_t2QADD8 = 2934, ARM_t2QASX = 2935, ARM_t2QDADD = 2936, ARM_t2QDSUB = 2937, ARM_t2QSAX = 2938, ARM_t2QSUB = 2939, ARM_t2QSUB16 = 2940, ARM_t2QSUB8 = 2941, ARM_t2RBIT = 2942, ARM_t2REV = 2943, ARM_t2REV16 = 2944, ARM_t2REVSH = 2945, ARM_t2RFEDB = 2946, ARM_t2RFEDBW = 2947, ARM_t2RFEIA = 2948, ARM_t2RFEIAW = 2949, ARM_t2RORri = 2950, ARM_t2RORrr = 2951, ARM_t2RRX = 2952, ARM_t2RSBri = 2953, ARM_t2RSBrr = 2954, ARM_t2RSBrs = 2955, ARM_t2SADD16 = 2956, ARM_t2SADD8 = 2957, ARM_t2SASX = 2958, ARM_t2SBCri = 2959, ARM_t2SBCrr = 2960, ARM_t2SBCrs = 2961, ARM_t2SBFX = 2962, ARM_t2SDIV = 2963, ARM_t2SEL = 2964, ARM_t2SETPAN = 2965, ARM_t2SG = 2966, ARM_t2SHADD16 = 2967, ARM_t2SHADD8 = 2968, ARM_t2SHASX = 2969, ARM_t2SHSAX = 2970, ARM_t2SHSUB16 = 2971, ARM_t2SHSUB8 = 2972, ARM_t2SMC = 2973, ARM_t2SMLABB = 2974, ARM_t2SMLABT = 2975, ARM_t2SMLAD = 2976, ARM_t2SMLADX = 2977, ARM_t2SMLAL = 2978, ARM_t2SMLALBB = 2979, ARM_t2SMLALBT = 2980, ARM_t2SMLALD = 2981, ARM_t2SMLALDX = 2982, ARM_t2SMLALTB = 2983, ARM_t2SMLALTT = 2984, ARM_t2SMLATB = 2985, ARM_t2SMLATT = 2986, ARM_t2SMLAWB = 2987, ARM_t2SMLAWT = 2988, ARM_t2SMLSD = 2989, ARM_t2SMLSDX = 2990, ARM_t2SMLSLD = 2991, ARM_t2SMLSLDX = 2992, ARM_t2SMMLA = 2993, ARM_t2SMMLAR = 2994, ARM_t2SMMLS = 2995, ARM_t2SMMLSR = 2996, ARM_t2SMMUL = 2997, ARM_t2SMMULR = 2998, ARM_t2SMUAD = 2999, ARM_t2SMUADX = 3000, ARM_t2SMULBB = 3001, ARM_t2SMULBT = 3002, ARM_t2SMULL = 3003, ARM_t2SMULTB = 3004, ARM_t2SMULTT = 3005, ARM_t2SMULWB = 3006, ARM_t2SMULWT = 3007, ARM_t2SMUSD = 3008, ARM_t2SMUSDX = 3009, ARM_t2SRSDB = 3010, ARM_t2SRSDB_UPD = 3011, ARM_t2SRSIA = 3012, ARM_t2SRSIA_UPD = 3013, ARM_t2SSAT = 3014, ARM_t2SSAT16 = 3015, ARM_t2SSAX = 3016, ARM_t2SSUB16 = 3017, ARM_t2SSUB8 = 3018, ARM_t2STC2L_OFFSET = 3019, ARM_t2STC2L_OPTION = 3020, ARM_t2STC2L_POST = 3021, ARM_t2STC2L_PRE = 3022, ARM_t2STC2_OFFSET = 3023, ARM_t2STC2_OPTION = 3024, ARM_t2STC2_POST = 3025, ARM_t2STC2_PRE = 3026, ARM_t2STCL_OFFSET = 3027, ARM_t2STCL_OPTION = 3028, ARM_t2STCL_POST = 3029, ARM_t2STCL_PRE = 3030, ARM_t2STC_OFFSET = 3031, ARM_t2STC_OPTION = 3032, ARM_t2STC_POST = 3033, ARM_t2STC_PRE = 3034, ARM_t2STL = 3035, ARM_t2STLB = 3036, ARM_t2STLEX = 3037, ARM_t2STLEXB = 3038, ARM_t2STLEXD = 3039, ARM_t2STLEXH = 3040, ARM_t2STLH = 3041, ARM_t2STMDB = 3042, ARM_t2STMDB_UPD = 3043, ARM_t2STMIA = 3044, ARM_t2STMIA_UPD = 3045, ARM_t2STRBT = 3046, ARM_t2STRB_POST = 3047, ARM_t2STRB_PRE = 3048, ARM_t2STRBi12 = 3049, ARM_t2STRBi8 = 3050, ARM_t2STRBs = 3051, ARM_t2STRD_POST = 3052, ARM_t2STRD_PRE = 3053, ARM_t2STRDi8 = 3054, ARM_t2STREX = 3055, ARM_t2STREXB = 3056, ARM_t2STREXD = 3057, ARM_t2STREXH = 3058, ARM_t2STRHT = 3059, ARM_t2STRH_POST = 3060, ARM_t2STRH_PRE = 3061, ARM_t2STRHi12 = 3062, ARM_t2STRHi8 = 3063, ARM_t2STRHs = 3064, ARM_t2STRT = 3065, ARM_t2STR_POST = 3066, ARM_t2STR_PRE = 3067, ARM_t2STRi12 = 3068, ARM_t2STRi8 = 3069, ARM_t2STRs = 3070, ARM_t2SUBS_PC_LR = 3071, ARM_t2SUBri = 3072, ARM_t2SUBri12 = 3073, ARM_t2SUBrr = 3074, ARM_t2SUBrs = 3075, ARM_t2SXTAB = 3076, ARM_t2SXTAB16 = 3077, ARM_t2SXTAH = 3078, ARM_t2SXTB = 3079, ARM_t2SXTB16 = 3080, ARM_t2SXTH = 3081, ARM_t2TBB = 3082, ARM_t2TBH = 3083, ARM_t2TEQri = 3084, ARM_t2TEQrr = 3085, ARM_t2TEQrs = 3086, ARM_t2TSB = 3087, ARM_t2TSTri = 3088, ARM_t2TSTrr = 3089, ARM_t2TSTrs = 3090, ARM_t2TT = 3091, ARM_t2TTA = 3092, ARM_t2TTAT = 3093, ARM_t2TTT = 3094, ARM_t2UADD16 = 3095, ARM_t2UADD8 = 3096, ARM_t2UASX = 3097, ARM_t2UBFX = 3098, ARM_t2UDF = 3099, ARM_t2UDIV = 3100, ARM_t2UHADD16 = 3101, ARM_t2UHADD8 = 3102, ARM_t2UHASX = 3103, ARM_t2UHSAX = 3104, ARM_t2UHSUB16 = 3105, ARM_t2UHSUB8 = 3106, ARM_t2UMAAL = 3107, ARM_t2UMLAL = 3108, ARM_t2UMULL = 3109, ARM_t2UQADD16 = 3110, ARM_t2UQADD8 = 3111, ARM_t2UQASX = 3112, ARM_t2UQSAX = 3113, ARM_t2UQSUB16 = 3114, ARM_t2UQSUB8 = 3115, ARM_t2USAD8 = 3116, ARM_t2USADA8 = 3117, ARM_t2USAT = 3118, ARM_t2USAT16 = 3119, ARM_t2USAX = 3120, ARM_t2USUB16 = 3121, ARM_t2USUB8 = 3122, ARM_t2UXTAB = 3123, ARM_t2UXTAB16 = 3124, ARM_t2UXTAH = 3125, ARM_t2UXTB = 3126, ARM_t2UXTB16 = 3127, ARM_t2UXTH = 3128, ARM_tADC = 3129, ARM_tADDhirr = 3130, ARM_tADDi3 = 3131, ARM_tADDi8 = 3132, ARM_tADDrSP = 3133, ARM_tADDrSPi = 3134, ARM_tADDrr = 3135, ARM_tADDspi = 3136, ARM_tADDspr = 3137, ARM_tADR = 3138, ARM_tAND = 3139, ARM_tASRri = 3140, ARM_tASRrr = 3141, ARM_tB = 3142, ARM_tBIC = 3143, ARM_tBKPT = 3144, ARM_tBL = 3145, ARM_tBLXNSr = 3146, ARM_tBLXi = 3147, ARM_tBLXr = 3148, ARM_tBX = 3149, ARM_tBXNS = 3150, ARM_tBcc = 3151, ARM_tCBNZ = 3152, ARM_tCBZ = 3153, ARM_tCMNz = 3154, ARM_tCMPhir = 3155, ARM_tCMPi8 = 3156, ARM_tCMPr = 3157, ARM_tCPS = 3158, ARM_tEOR = 3159, ARM_tHINT = 3160, ARM_tHLT = 3161, ARM_tLDMIA = 3165, ARM_tLDRBi = 3166, ARM_tLDRBr = 3167, ARM_tLDRHi = 3168, ARM_tLDRHr = 3169, ARM_tLDRSB = 3170, ARM_tLDRSH = 3171, ARM_tLDRi = 3172, ARM_tLDRpci = 3173, ARM_tLDRr = 3174, ARM_tLDRspi = 3175, ARM_tLSLri = 3176, ARM_tLSLrr = 3177, ARM_tLSRri = 3178, ARM_tLSRrr = 3179, ARM_tMOVSr = 3180, ARM_tMOVi8 = 3181, ARM_tMOVr = 3182, ARM_tMUL = 3183, ARM_tMVN = 3184, ARM_tORR = 3185, ARM_tPICADD = 3186, ARM_tPOP = 3187, ARM_tPUSH = 3188, ARM_tREV = 3189, ARM_tREV16 = 3190, ARM_tREVSH = 3191, ARM_tROR = 3192, ARM_tRSB = 3193, ARM_tSBC = 3194, ARM_tSETEND = 3195, ARM_tSTMIA_UPD = 3196, ARM_tSTRBi = 3197, ARM_tSTRBr = 3198, ARM_tSTRHi = 3199, ARM_tSTRHr = 3200, ARM_tSTRi = 3201, ARM_tSTRr = 3202, ARM_tSTRspi = 3203, ARM_tSUBi3 = 3204, ARM_tSUBi8 = 3205, ARM_tSUBrr = 3206, ARM_tSUBspi = 3207, ARM_tSVC = 3208, ARM_tSXTB = 3209, ARM_tSXTH = 3210, ARM_tTRAP = 3211, ARM_tTST = 3212, ARM_tUDF = 3213, ARM_tUXTB = 3214, ARM_tUXTH = 3215, ARM_t__brkdiv0 = 3216, ARM_INSTRUCTION_LIST_END = 3217 }; #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC #define nullptr 0 static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { ARM_NoRegister, ARM_APSR = 1, ARM_APSR_NZCV = 2, ARM_CPSR = 3, ARM_FPEXC = 4, ARM_FPINST = 5, ARM_FPSCR = 6, ARM_FPSCR_NZCV = 7, ARM_FPSID = 8, ARM_ITSTATE = 9, ARM_LR = 10, ARM_PC = 11, ARM_SP = 12, ARM_SPSR = 13, ARM_D0 = 14, ARM_D1 = 15, ARM_D2 = 16, ARM_D3 = 17, ARM_D4 = 18, ARM_D5 = 19, ARM_D6 = 20, ARM_D7 = 21, ARM_D8 = 22, ARM_D9 = 23, ARM_D10 = 24, ARM_D11 = 25, ARM_D12 = 26, ARM_D13 = 27, ARM_D14 = 28, ARM_D15 = 29, ARM_D16 = 30, ARM_D17 = 31, ARM_D18 = 32, ARM_D19 = 33, ARM_D20 = 34, ARM_D21 = 35, ARM_D22 = 36, ARM_D23 = 37, ARM_D24 = 38, ARM_D25 = 39, ARM_D26 = 40, ARM_D27 = 41, ARM_D28 = 42, ARM_D29 = 43, ARM_D30 = 44, ARM_D31 = 45, ARM_FPINST2 = 46, ARM_MVFR0 = 47, ARM_MVFR1 = 48, ARM_MVFR2 = 49, ARM_Q0 = 50, ARM_Q1 = 51, ARM_Q2 = 52, ARM_Q3 = 53, ARM_Q4 = 54, ARM_Q5 = 55, ARM_Q6 = 56, ARM_Q7 = 57, ARM_Q8 = 58, ARM_Q9 = 59, ARM_Q10 = 60, ARM_Q11 = 61, ARM_Q12 = 62, ARM_Q13 = 63, ARM_Q14 = 64, ARM_Q15 = 65, ARM_R0 = 66, ARM_R1 = 67, ARM_R2 = 68, ARM_R3 = 69, ARM_R4 = 70, ARM_R5 = 71, ARM_R6 = 72, ARM_R7 = 73, ARM_R8 = 74, ARM_R9 = 75, ARM_R10 = 76, ARM_R11 = 77, ARM_R12 = 78, ARM_S0 = 79, ARM_S1 = 80, ARM_S2 = 81, ARM_S3 = 82, ARM_S4 = 83, ARM_S5 = 84, ARM_S6 = 85, ARM_S7 = 86, ARM_S8 = 87, ARM_S9 = 88, ARM_S10 = 89, ARM_S11 = 90, ARM_S12 = 91, ARM_S13 = 92, ARM_S14 = 93, ARM_S15 = 94, ARM_S16 = 95, ARM_S17 = 96, ARM_S18 = 97, ARM_S19 = 98, ARM_S20 = 99, ARM_S21 = 100, ARM_S22 = 101, ARM_S23 = 102, ARM_S24 = 103, ARM_S25 = 104, ARM_S26 = 105, ARM_S27 = 106, ARM_S28 = 107, ARM_S29 = 108, ARM_S30 = 109, ARM_S31 = 110, ARM_D0_D2 = 111, ARM_D1_D3 = 112, ARM_D2_D4 = 113, ARM_D3_D5 = 114, ARM_D4_D6 = 115, ARM_D5_D7 = 116, ARM_D6_D8 = 117, ARM_D7_D9 = 118, ARM_D8_D10 = 119, ARM_D9_D11 = 120, ARM_D10_D12 = 121, ARM_D11_D13 = 122, ARM_D12_D14 = 123, ARM_D13_D15 = 124, ARM_D14_D16 = 125, ARM_D15_D17 = 126, ARM_D16_D18 = 127, ARM_D17_D19 = 128, ARM_D18_D20 = 129, ARM_D19_D21 = 130, ARM_D20_D22 = 131, ARM_D21_D23 = 132, ARM_D22_D24 = 133, ARM_D23_D25 = 134, ARM_D24_D26 = 135, ARM_D25_D27 = 136, ARM_D26_D28 = 137, ARM_D27_D29 = 138, ARM_D28_D30 = 139, ARM_D29_D31 = 140, ARM_Q0_Q1 = 141, ARM_Q1_Q2 = 142, ARM_Q2_Q3 = 143, ARM_Q3_Q4 = 144, ARM_Q4_Q5 = 145, ARM_Q5_Q6 = 146, ARM_Q6_Q7 = 147, ARM_Q7_Q8 = 148, ARM_Q8_Q9 = 149, ARM_Q9_Q10 = 150, ARM_Q10_Q11 = 151, ARM_Q11_Q12 = 152, ARM_Q12_Q13 = 153, ARM_Q13_Q14 = 154, ARM_Q14_Q15 = 155, ARM_Q0_Q1_Q2_Q3 = 156, ARM_Q1_Q2_Q3_Q4 = 157, ARM_Q2_Q3_Q4_Q5 = 158, ARM_Q3_Q4_Q5_Q6 = 159, ARM_Q4_Q5_Q6_Q7 = 160, ARM_Q5_Q6_Q7_Q8 = 161, ARM_Q6_Q7_Q8_Q9 = 162, ARM_Q7_Q8_Q9_Q10 = 163, ARM_Q8_Q9_Q10_Q11 = 164, ARM_Q9_Q10_Q11_Q12 = 165, ARM_Q10_Q11_Q12_Q13 = 166, ARM_Q11_Q12_Q13_Q14 = 167, ARM_Q12_Q13_Q14_Q15 = 168, ARM_R12_SP = 169, ARM_R0_R1 = 170, ARM_R2_R3 = 171, ARM_R4_R5 = 172, ARM_R6_R7 = 173, ARM_R8_R9 = 174, ARM_R10_R11 = 175, ARM_D0_D1_D2 = 176, ARM_D1_D2_D3 = 177, ARM_D2_D3_D4 = 178, ARM_D3_D4_D5 = 179, ARM_D4_D5_D6 = 180, ARM_D5_D6_D7 = 181, ARM_D6_D7_D8 = 182, ARM_D7_D8_D9 = 183, ARM_D8_D9_D10 = 184, ARM_D9_D10_D11 = 185, ARM_D10_D11_D12 = 186, ARM_D11_D12_D13 = 187, ARM_D12_D13_D14 = 188, ARM_D13_D14_D15 = 189, ARM_D14_D15_D16 = 190, ARM_D15_D16_D17 = 191, ARM_D16_D17_D18 = 192, ARM_D17_D18_D19 = 193, ARM_D18_D19_D20 = 194, ARM_D19_D20_D21 = 195, ARM_D20_D21_D22 = 196, ARM_D21_D22_D23 = 197, ARM_D22_D23_D24 = 198, ARM_D23_D24_D25 = 199, ARM_D24_D25_D26 = 200, ARM_D25_D26_D27 = 201, ARM_D26_D27_D28 = 202, ARM_D27_D28_D29 = 203, ARM_D28_D29_D30 = 204, ARM_D29_D30_D31 = 205, ARM_D0_D2_D4 = 206, ARM_D1_D3_D5 = 207, ARM_D2_D4_D6 = 208, ARM_D3_D5_D7 = 209, ARM_D4_D6_D8 = 210, ARM_D5_D7_D9 = 211, ARM_D6_D8_D10 = 212, ARM_D7_D9_D11 = 213, ARM_D8_D10_D12 = 214, ARM_D9_D11_D13 = 215, ARM_D10_D12_D14 = 216, ARM_D11_D13_D15 = 217, ARM_D12_D14_D16 = 218, ARM_D13_D15_D17 = 219, ARM_D14_D16_D18 = 220, ARM_D15_D17_D19 = 221, ARM_D16_D18_D20 = 222, ARM_D17_D19_D21 = 223, ARM_D18_D20_D22 = 224, ARM_D19_D21_D23 = 225, ARM_D20_D22_D24 = 226, ARM_D21_D23_D25 = 227, ARM_D22_D24_D26 = 228, ARM_D23_D25_D27 = 229, ARM_D24_D26_D28 = 230, ARM_D25_D27_D29 = 231, ARM_D26_D28_D30 = 232, ARM_D27_D29_D31 = 233, ARM_D0_D2_D4_D6 = 234, ARM_D1_D3_D5_D7 = 235, ARM_D2_D4_D6_D8 = 236, ARM_D3_D5_D7_D9 = 237, ARM_D4_D6_D8_D10 = 238, ARM_D5_D7_D9_D11 = 239, ARM_D6_D8_D10_D12 = 240, ARM_D7_D9_D11_D13 = 241, ARM_D8_D10_D12_D14 = 242, ARM_D9_D11_D13_D15 = 243, ARM_D10_D12_D14_D16 = 244, ARM_D11_D13_D15_D17 = 245, ARM_D12_D14_D16_D18 = 246, ARM_D13_D15_D17_D19 = 247, ARM_D14_D16_D18_D20 = 248, ARM_D15_D17_D19_D21 = 249, ARM_D16_D18_D20_D22 = 250, ARM_D17_D19_D21_D23 = 251, ARM_D18_D20_D22_D24 = 252, ARM_D19_D21_D23_D25 = 253, ARM_D20_D22_D24_D26 = 254, ARM_D21_D23_D25_D27 = 255, ARM_D22_D24_D26_D28 = 256, ARM_D23_D25_D27_D29 = 257, ARM_D24_D26_D28_D30 = 258, ARM_D25_D27_D29_D31 = 259, ARM_D1_D2 = 260, ARM_D3_D4 = 261, ARM_D5_D6 = 262, ARM_D7_D8 = 263, ARM_D9_D10 = 264, ARM_D11_D12 = 265, ARM_D13_D14 = 266, ARM_D15_D16 = 267, ARM_D17_D18 = 268, ARM_D19_D20 = 269, ARM_D21_D22 = 270, ARM_D23_D24 = 271, ARM_D25_D26 = 272, ARM_D27_D28 = 273, ARM_D29_D30 = 274, ARM_D1_D2_D3_D4 = 275, ARM_D3_D4_D5_D6 = 276, ARM_D5_D6_D7_D8 = 277, ARM_D7_D8_D9_D10 = 278, ARM_D9_D10_D11_D12 = 279, ARM_D11_D12_D13_D14 = 280, ARM_D13_D14_D15_D16 = 281, ARM_D15_D16_D17_D18 = 282, ARM_D17_D18_D19_D20 = 283, ARM_D19_D20_D21_D22 = 284, ARM_D21_D22_D23_D24 = 285, ARM_D23_D24_D25_D26 = 286, ARM_D25_D26_D27_D28 = 287, ARM_D27_D28_D29_D30 = 288, ARM_NUM_TARGET_REGS // 289 }; // Register classes enum { ARM_HPRRegClassID = 0, ARM_SPRRegClassID = 1, ARM_GPRRegClassID = 2, ARM_GPRwithAPSRRegClassID = 3, ARM_SPR_8RegClassID = 4, ARM_GPRnopcRegClassID = 5, ARM_rGPRRegClassID = 6, ARM_tGPRwithpcRegClassID = 7, ARM_hGPRRegClassID = 8, ARM_tGPRRegClassID = 9, ARM_GPRnopc_and_hGPRRegClassID = 10, ARM_hGPR_and_rGPRRegClassID = 11, ARM_tcGPRRegClassID = 12, ARM_tGPR_and_tcGPRRegClassID = 13, ARM_CCRRegClassID = 14, ARM_GPRspRegClassID = 15, ARM_hGPR_and_tGPRwithpcRegClassID = 16, ARM_hGPR_and_tcGPRRegClassID = 17, ARM_DPRRegClassID = 18, ARM_DPR_VFP2RegClassID = 19, ARM_DPR_8RegClassID = 20, ARM_GPRPairRegClassID = 21, ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 22, ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 23, ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 24, ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 25, ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26, ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 27, ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 28, ARM_DPairSpcRegClassID = 29, ARM_DPairSpc_with_ssub_0RegClassID = 30, ARM_DPairSpc_with_ssub_4RegClassID = 31, ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32, ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33, ARM_DPairRegClassID = 34, ARM_DPair_with_ssub_0RegClassID = 35, ARM_QPRRegClassID = 36, ARM_DPair_with_ssub_2RegClassID = 37, ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 38, ARM_QPR_VFP2RegClassID = 39, ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 40, ARM_QPR_8RegClassID = 41, ARM_DTripleRegClassID = 42, ARM_DTripleSpcRegClassID = 43, ARM_DTripleSpc_with_ssub_0RegClassID = 44, ARM_DTriple_with_ssub_0RegClassID = 45, ARM_DTriple_with_qsub_0_in_QPRRegClassID = 46, ARM_DTriple_with_ssub_2RegClassID = 47, ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48, ARM_DTripleSpc_with_ssub_4RegClassID = 49, ARM_DTriple_with_ssub_4RegClassID = 50, ARM_DTripleSpc_with_ssub_8RegClassID = 51, ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52, ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 53, ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54, ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55, ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 56, ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57, ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58, ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59, ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 60, ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61, ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62, ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 63, ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64, ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65, ARM_DQuadSpcRegClassID = 66, ARM_DQuadSpc_with_ssub_0RegClassID = 67, ARM_DQuadSpc_with_ssub_4RegClassID = 68, ARM_DQuadSpc_with_ssub_8RegClassID = 69, ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70, ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71, ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72, ARM_DQuadRegClassID = 73, ARM_DQuad_with_ssub_0RegClassID = 74, ARM_DQuad_with_ssub_2RegClassID = 75, ARM_QQPRRegClassID = 76, ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77, ARM_DQuad_with_ssub_4RegClassID = 78, ARM_DQuad_with_ssub_6RegClassID = 79, ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 80, ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81, ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82, ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 83, ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84, ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85, ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 86, ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87, ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 88, ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89, ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 90, ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 91, ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92, ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93, ARM_QQQQPRRegClassID = 94, ARM_QQQQPR_with_ssub_0RegClassID = 95, ARM_QQQQPR_with_ssub_4RegClassID = 96, ARM_QQQQPR_with_ssub_8RegClassID = 97, ARM_QQQQPR_with_ssub_12RegClassID = 98, ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99, ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100, ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101, ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102, }; // Subregister indices enum { ARM_NoSubRegister, ARM_dsub_0, // 1 ARM_dsub_1, // 2 ARM_dsub_2, // 3 ARM_dsub_3, // 4 ARM_dsub_4, // 5 ARM_dsub_5, // 6 ARM_dsub_6, // 7 ARM_dsub_7, // 8 ARM_gsub_0, // 9 ARM_gsub_1, // 10 ARM_qqsub_0, // 11 ARM_qqsub_1, // 12 ARM_qsub_0, // 13 ARM_qsub_1, // 14 ARM_qsub_2, // 15 ARM_qsub_3, // 16 ARM_ssub_0, // 17 ARM_ssub_1, // 18 ARM_ssub_2, // 19 ARM_ssub_3, // 20 ARM_ssub_4, // 21 ARM_ssub_5, // 22 ARM_ssub_6, // 23 ARM_ssub_7, // 24 ARM_ssub_8, // 25 ARM_ssub_9, // 26 ARM_ssub_10, // 27 ARM_ssub_11, // 28 ARM_ssub_12, // 29 ARM_ssub_13, // 30 ARM_dsub_7_then_ssub_0, // 31 ARM_dsub_7_then_ssub_1, // 32 ARM_ssub_0_ssub_1_ssub_4_ssub_5, // 33 ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34 ARM_ssub_2_ssub_3_ssub_6_ssub_7, // 35 ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36 ARM_ssub_2_ssub_3_ssub_4_ssub_5, // 37 ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38 ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39 ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40 ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41 ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42 ARM_ssub_4_ssub_5_ssub_8_ssub_9, // 43 ARM_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44 ARM_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45 ARM_ssub_6_ssub_7_dsub_5, // 46 ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47 ARM_ssub_6_ssub_7_dsub_5_dsub_7, // 48 ARM_ssub_6_ssub_7_ssub_8_ssub_9, // 49 ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50 ARM_ssub_8_ssub_9_ssub_12_ssub_13, // 51 ARM_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52 ARM_dsub_5_dsub_7, // 53 ARM_dsub_5_ssub_12_ssub_13_dsub_7, // 54 ARM_dsub_5_ssub_12_ssub_13, // 55 ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56 ARM_NUM_TARGET_SUBREGS }; #endif // GET_REGINFO_ENUM #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg ARMRegDiffLists[] = { /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0, /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0, /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0, /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0, /* 91 */ 40, 1, 1, 1, 1, 1, 0, /* 98 */ 65196, 1, 1, 1, 1, 1, 0, /* 105 */ 40, 1, 1, 1, 1, 0, /* 111 */ 42, 1, 1, 1, 1, 0, /* 117 */ 42, 1, 1, 1, 0, /* 122 */ 64510, 1, 1, 1, 0, /* 127 */ 65015, 1, 1, 1, 0, /* 132 */ 65282, 1, 1, 1, 0, /* 137 */ 65348, 1, 1, 1, 0, /* 142 */ 13, 1, 1, 0, /* 146 */ 42, 1, 1, 0, /* 150 */ 65388, 1, 1, 0, /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, /* 254 */ 65489, 133, 65416, 1, 1, 0, /* 260 */ 65490, 133, 65416, 1, 1, 0, /* 266 */ 65491, 133, 65416, 1, 1, 0, /* 272 */ 65492, 133, 65416, 1, 1, 0, /* 278 */ 65493, 133, 65416, 1, 1, 0, /* 284 */ 65494, 133, 65416, 1, 1, 0, /* 290 */ 65495, 133, 65416, 1, 1, 0, /* 296 */ 65496, 133, 65416, 1, 1, 0, /* 302 */ 65497, 133, 65416, 1, 1, 0, /* 308 */ 65498, 133, 65416, 1, 1, 0, /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0, /* 332 */ 65136, 1, 3, 1, 3, 1, 0, /* 339 */ 65326, 1, 3, 1, 0, /* 344 */ 13, 1, 0, /* 347 */ 14, 1, 0, /* 350 */ 65, 1, 0, /* 353 */ 65500, 65, 1, 65471, 66, 1, 0, /* 360 */ 65291, 66, 1, 65470, 67, 1, 0, /* 367 */ 65439, 65, 1, 65472, 67, 1, 0, /* 374 */ 65501, 67, 1, 65469, 68, 1, 0, /* 381 */ 65439, 66, 1, 65471, 68, 1, 0, /* 388 */ 65292, 68, 1, 65468, 69, 1, 0, /* 395 */ 65439, 67, 1, 65470, 69, 1, 0, /* 402 */ 65502, 69, 1, 65467, 70, 1, 0, /* 409 */ 65439, 68, 1, 65469, 70, 1, 0, /* 416 */ 65293, 70, 1, 65466, 71, 1, 0, /* 423 */ 65439, 69, 1, 65468, 71, 1, 0, /* 430 */ 65503, 71, 1, 65465, 72, 1, 0, /* 437 */ 65439, 70, 1, 65467, 72, 1, 0, /* 444 */ 65294, 72, 1, 65464, 73, 1, 0, /* 451 */ 65439, 71, 1, 65466, 73, 1, 0, /* 458 */ 65504, 73, 1, 65463, 74, 1, 0, /* 465 */ 65439, 72, 1, 65465, 74, 1, 0, /* 472 */ 65295, 74, 1, 65462, 75, 1, 0, /* 479 */ 65439, 73, 1, 65464, 75, 1, 0, /* 486 */ 65505, 75, 1, 65461, 76, 1, 0, /* 493 */ 65439, 74, 1, 65463, 76, 1, 0, /* 500 */ 65296, 76, 1, 65460, 77, 1, 0, /* 507 */ 65439, 75, 1, 65462, 77, 1, 0, /* 514 */ 65506, 77, 1, 65459, 78, 1, 0, /* 521 */ 65439, 76, 1, 65461, 78, 1, 0, /* 528 */ 65297, 78, 1, 65458, 79, 1, 0, /* 535 */ 65439, 77, 1, 65460, 79, 1, 0, /* 542 */ 65507, 79, 1, 65457, 80, 1, 0, /* 549 */ 65439, 78, 1, 65459, 80, 1, 0, /* 556 */ 65045, 1, 0, /* 559 */ 65260, 1, 0, /* 562 */ 65299, 1, 0, /* 565 */ 65300, 1, 0, /* 568 */ 65301, 1, 0, /* 571 */ 65302, 1, 0, /* 574 */ 65303, 1, 0, /* 577 */ 65304, 1, 0, /* 580 */ 65305, 1, 0, /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, /* 600 */ 65488, 13, 121, 65416, 1, 0, /* 606 */ 65489, 13, 121, 65416, 1, 0, /* 612 */ 65490, 13, 121, 65416, 1, 0, /* 618 */ 65491, 13, 121, 65416, 1, 0, /* 624 */ 65492, 13, 121, 65416, 1, 0, /* 630 */ 65493, 13, 121, 65416, 1, 0, /* 636 */ 65494, 13, 121, 65416, 1, 0, /* 642 */ 65495, 13, 121, 65416, 1, 0, /* 648 */ 65496, 13, 121, 65416, 1, 0, /* 654 */ 65497, 13, 121, 65416, 1, 0, /* 660 */ 65498, 13, 121, 65416, 1, 0, /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, /* 765 */ 65488, 133, 65416, 1, 0, /* 770 */ 65499, 134, 65416, 1, 0, /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, /* 783 */ 65432, 1, 0, /* 786 */ 65433, 1, 0, /* 789 */ 65434, 1, 0, /* 792 */ 65435, 1, 0, /* 795 */ 65436, 1, 0, /* 798 */ 65437, 1, 0, /* 801 */ 65464, 1, 0, /* 804 */ 65508, 1, 0, /* 807 */ 65509, 1, 0, /* 810 */ 65510, 1, 0, /* 813 */ 65511, 1, 0, /* 816 */ 65512, 1, 0, /* 819 */ 65513, 1, 0, /* 822 */ 65514, 1, 0, /* 825 */ 65515, 1, 0, /* 828 */ 65520, 1, 0, /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0, /* 839 */ 65136, 1, 3, 1, 2, 0, /* 845 */ 65326, 1, 2, 0, /* 849 */ 65080, 1, 3, 1, 2, 2, 0, /* 856 */ 65136, 1, 2, 2, 0, /* 861 */ 65080, 1, 2, 2, 2, 0, /* 867 */ 65330, 2, 2, 2, 0, /* 872 */ 65080, 1, 3, 2, 2, 0, /* 878 */ 65358, 2, 2, 0, /* 882 */ 65080, 1, 3, 1, 3, 2, 0, /* 889 */ 65136, 1, 3, 2, 0, /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0, /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0, /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0, /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0, /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0, /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0, /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0, /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0, /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0, /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0, /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0, /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0, /* 1038 */ 65344, 2, 2, 93, 2, 0, /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0, /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0, /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0, /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0, /* 1080 */ 65439, 2, 0, /* 1083 */ 65453, 2, 0, /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0, /* 1094 */ 65136, 1, 3, 1, 3, 0, /* 1100 */ 65326, 1, 3, 0, /* 1104 */ 5, 0, /* 1106 */ 140, 65486, 13, 0, /* 1110 */ 14, 0, /* 1112 */ 126, 65501, 15, 0, /* 1116 */ 10, 66, 0, /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0, /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0, /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0, /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0, /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0, /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0, /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0, /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0, /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0, /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0, /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0, /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0, /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0, /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0, /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0, /* 1359 */ 91, 0, /* 1361 */ 98, 0, /* 1363 */ 99, 0, /* 1365 */ 100, 0, /* 1367 */ 101, 0, /* 1369 */ 102, 0, /* 1371 */ 103, 0, /* 1373 */ 104, 0, /* 1375 */ 65374, 1, 1, 20, 75, 135, 0, /* 1382 */ 65374, 1, 1, 21, 74, 136, 0, /* 1389 */ 65374, 1, 1, 22, 73, 137, 0, /* 1396 */ 65374, 1, 1, 23, 72, 138, 0, /* 1403 */ 65374, 1, 1, 24, 71, 139, 0, /* 1410 */ 65374, 1, 1, 25, 70, 140, 0, /* 1417 */ 65374, 1, 1, 26, 69, 141, 0, /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0, /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0, /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0, /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0, /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0, /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0, /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0, /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0, /* 1526 */ 157, 0, /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0, /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0, /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0, /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0, /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0, /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0, /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0, /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0, /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0, /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, /* 2455 */ 65487, 13, 121, 65416, 0, /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, /* 2468 */ 65466, 1, 65486, 133, 65416, 0, /* 2474 */ 65487, 133, 65416, 0, /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0, /* 2509 */ 65452, 1, 65500, 134, 65417, 0, /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0, /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0, /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0, /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0, /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0, /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0, /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0, /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0, /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0, /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0, /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0, /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0, /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0, /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0, /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0, /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0, /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0, /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0, /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, /* 2832 */ 26, 65446, 92, 65445, 0, /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, /* 3839 */ 65298, 80, 1, 65456, 0, /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, /* 3948 */ 65439, 80, 1, 65457, 0, /* 3953 */ 28, 65457, 0, /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, /* 4002 */ 26, 65458, 80, 65457, 0, /* 4007 */ 65439, 79, 1, 65458, 0, /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0, /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0, /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0, /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0, /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0, /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0, /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0, /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0, /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0, /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0, /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0, /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0, /* 4114 */ 65445, 65470, 0, /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0, /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0, /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0, /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0, /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0, /* 4182 */ 65534, 0, /* 4184 */ 65535, 0, }; static const uint16_t ARMSubRegIdxLists[] = { /* 0 */ 1, 2, 0, /* 3 */ 1, 17, 18, 2, 0, /* 8 */ 1, 3, 0, /* 11 */ 1, 17, 18, 3, 0, /* 16 */ 9, 10, 0, /* 19 */ 17, 18, 0, /* 22 */ 1, 17, 18, 2, 19, 20, 0, /* 29 */ 1, 17, 18, 3, 21, 22, 0, /* 36 */ 1, 2, 3, 13, 33, 37, 0, /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, /* 188 */ 1, 3, 5, 33, 43, 0, /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0, /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0, /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0, /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, }; static const MCRegisterDesc ARMRegDesc[] = { { 12, 0, 0, 0, 0, 0 }, { 1235, 16, 16, 2, 66945, 0 }, { 1268, 16, 16, 2, 66945, 0 }, { 1240, 16, 16, 2, 66945, 0 }, { 1199, 16, 16, 2, 66945, 0 }, { 1250, 16, 16, 2, 66945, 0 }, { 1226, 16, 16, 2, 17664, 0 }, { 1257, 16, 16, 2, 17664, 0 }, { 1205, 16, 16, 2, 66913, 0 }, { 1211, 16, 16, 2, 66913, 0 }, { 1232, 16, 16, 2, 66913, 0 }, { 1196, 16, 16, 2, 66913, 0 }, { 1223, 16, 1526, 2, 66913, 0 }, { 1245, 16, 16, 2, 66913, 0 }, { 119, 350, 4013, 19, 13250, 8 }, { 248, 357, 2479, 19, 13250, 8 }, { 363, 364, 3957, 19, 13250, 8 }, { 479, 378, 3845, 19, 13250, 8 }, { 605, 392, 3893, 19, 13250, 8 }, { 723, 406, 3724, 19, 13250, 8 }, { 837, 420, 3780, 19, 13250, 8 }, { 943, 434, 3604, 19, 13250, 8 }, { 1057, 448, 3664, 19, 13250, 8 }, { 1163, 462, 3484, 19, 13250, 8 }, { 9, 476, 3544, 19, 13250, 8 }, { 141, 490, 3364, 19, 13250, 8 }, { 282, 504, 3424, 19, 13250, 8 }, { 408, 518, 3244, 19, 13250, 8 }, { 523, 532, 3304, 19, 13250, 8 }, { 649, 546, 3149, 19, 13250, 8 }, { 768, 16, 3208, 2, 17761, 0 }, { 882, 16, 3078, 2, 17761, 0 }, { 988, 16, 3113, 2, 17761, 0 }, { 1102, 16, 3008, 2, 17761, 0 }, { 59, 16, 3043, 2, 17761, 0 }, { 192, 16, 2938, 2, 17761, 0 }, { 336, 16, 2973, 2, 17761, 0 }, { 456, 16, 2868, 2, 17761, 0 }, { 575, 16, 2903, 2, 17761, 0 }, { 697, 16, 2797, 2, 17761, 0 }, { 804, 16, 2837, 2, 17761, 0 }, { 914, 16, 2363, 2, 17761, 0 }, { 1024, 16, 2411, 2, 17761, 0 }, { 1134, 16, 2384, 2, 17761, 0 }, { 95, 16, 2429, 2, 17761, 0 }, { 224, 16, 2789, 2, 17761, 0 }, { 390, 16, 16, 2, 17761, 0 }, { 125, 16, 16, 2, 17761, 0 }, { 257, 16, 16, 2, 17761, 0 }, { 381, 16, 16, 2, 17761, 0 }, { 122, 353, 1112, 22, 2196, 11 }, { 254, 374, 775, 22, 2196, 11 }, { 378, 402, 314, 22, 2196, 11 }, { 500, 430, 244, 22, 2196, 11 }, { 629, 458, 234, 22, 2196, 11 }, { 744, 486, 224, 22, 2196, 11 }, { 861, 514, 214, 22, 2196, 11 }, { 964, 542, 204, 22, 2196, 11 }, { 1081, 804, 194, 0, 12818, 20 }, { 1184, 807, 184, 0, 12818, 20 }, { 35, 810, 174, 0, 12818, 20 }, { 168, 813, 164, 0, 12818, 20 }, { 312, 816, 154, 0, 12818, 20 }, { 436, 819, 591, 0, 12818, 20 }, { 555, 822, 2447, 0, 12818, 20 }, { 677, 825, 1106, 0, 12818, 20 }, { 128, 16, 1373, 2, 66913, 0 }, { 260, 16, 1371, 2, 66913, 0 }, { 384, 16, 1371, 2, 66913, 0 }, { 506, 16, 1369, 2, 66913, 0 }, { 632, 16, 1369, 2, 66913, 0 }, { 750, 16, 1367, 2, 66913, 0 }, { 864, 16, 1367, 2, 66913, 0 }, { 970, 16, 1365, 2, 66913, 0 }, { 1084, 16, 1365, 2, 66913, 0 }, { 1190, 16, 1363, 2, 66913, 0 }, { 39, 16, 1363, 2, 66913, 0 }, { 176, 16, 1361, 2, 66913, 0 }, { 316, 16, 1359, 2, 66913, 0 }, { 131, 16, 4021, 2, 65585, 0 }, { 269, 16, 4012, 2, 65585, 0 }, { 387, 16, 2490, 2, 65585, 0 }, { 509, 16, 2478, 2, 65585, 0 }, { 635, 16, 3974, 2, 65585, 0 }, { 753, 16, 3956, 2, 65585, 0 }, { 867, 16, 3863, 2, 65585, 0 }, { 973, 16, 3844, 2, 65585, 0 }, { 1087, 16, 3914, 2, 65585, 0 }, { 1193, 16, 3892, 2, 65585, 0 }, { 43, 16, 3745, 2, 65585, 0 }, { 180, 16, 3723, 2, 65585, 0 }, { 320, 16, 3803, 2, 65585, 0 }, { 440, 16, 3779, 2, 65585, 0 }, { 559, 16, 3627, 2, 65585, 0 }, { 681, 16, 3603, 2, 65585, 0 }, { 788, 16, 3687, 2, 65585, 0 }, { 898, 16, 3663, 2, 65585, 0 }, { 1008, 16, 3507, 2, 65585, 0 }, { 1118, 16, 3483, 2, 65585, 0 }, { 79, 16, 3567, 2, 65585, 0 }, { 212, 16, 3543, 2, 65585, 0 }, { 356, 16, 3387, 2, 65585, 0 }, { 472, 16, 3363, 2, 65585, 0 }, { 595, 16, 3447, 2, 65585, 0 }, { 713, 16, 3423, 2, 65585, 0 }, { 824, 16, 3267, 2, 65585, 0 }, { 930, 16, 3243, 2, 65585, 0 }, { 1044, 16, 3327, 2, 65585, 0 }, { 1150, 16, 3303, 2, 65585, 0 }, { 115, 16, 3172, 2, 65585, 0 }, { 244, 16, 3148, 2, 65585, 0 }, { 360, 367, 4015, 29, 5426, 23 }, { 476, 381, 2502, 29, 5426, 23 }, { 602, 395, 3992, 29, 5426, 23 }, { 720, 409, 3882, 29, 5426, 23 }, { 834, 423, 3936, 29, 5426, 23 }, { 940, 437, 3767, 29, 5426, 23 }, { 1054, 451, 3827, 29, 5426, 23 }, { 1160, 465, 3651, 29, 5426, 23 }, { 6, 479, 3711, 29, 5426, 23 }, { 151, 493, 3531, 29, 5426, 23 }, { 278, 507, 3591, 29, 5426, 23 }, { 404, 521, 3411, 29, 5426, 23 }, { 519, 535, 3471, 29, 5426, 23 }, { 645, 549, 3291, 29, 5426, 23 }, { 764, 4007, 3351, 11, 17602, 35 }, { 878, 3948, 3196, 11, 13522, 35 }, { 984, 1080, 3231, 8, 17329, 39 }, { 1098, 1080, 3101, 8, 17329, 39 }, { 55, 1080, 3136, 8, 17329, 39 }, { 204, 1080, 3031, 8, 17329, 39 }, { 332, 1080, 3066, 8, 17329, 39 }, { 452, 1080, 2961, 8, 17329, 39 }, { 571, 1080, 2996, 8, 17329, 39 }, { 693, 1080, 2891, 8, 17329, 39 }, { 800, 1080, 2926, 8, 17329, 39 }, { 910, 1080, 2820, 8, 17329, 39 }, { 1020, 1080, 2858, 8, 17329, 39 }, { 1130, 1080, 2401, 8, 17329, 39 }, { 91, 1080, 2440, 8, 17329, 39 }, { 236, 1080, 2791, 8, 17329, 39 }, { 251, 1339, 1114, 168, 1044, 57 }, { 375, 1319, 347, 168, 1044, 57 }, { 497, 1299, 142, 168, 1044, 57 }, { 626, 1279, 142, 168, 1044, 57 }, { 741, 1259, 142, 168, 1044, 57 }, { 858, 1239, 142, 168, 1044, 57 }, { 961, 1219, 142, 168, 1044, 57 }, { 1078, 1203, 142, 88, 1456, 74 }, { 1181, 1191, 142, 76, 2114, 87 }, { 32, 1179, 142, 76, 2114, 87 }, { 164, 1167, 142, 76, 2114, 87 }, { 308, 1155, 142, 76, 2114, 87 }, { 432, 1143, 142, 76, 2114, 87 }, { 551, 1131, 344, 76, 2114, 87 }, { 673, 1119, 1108, 76, 2114, 87 }, { 491, 2156, 16, 474, 4, 149 }, { 620, 2101, 16, 474, 4, 149 }, { 735, 2046, 16, 474, 4, 149 }, { 852, 1991, 16, 474, 4, 149 }, { 955, 1936, 16, 474, 4, 149 }, { 1072, 1885, 16, 423, 272, 166 }, { 1175, 1838, 16, 376, 512, 181 }, { 26, 1795, 16, 333, 720, 194 }, { 158, 1756, 16, 294, 1186, 205 }, { 301, 1717, 16, 294, 1186, 205 }, { 424, 1678, 16, 294, 1186, 205 }, { 543, 1639, 16, 294, 1186, 205 }, { 665, 1600, 16, 294, 1186, 205 }, { 1219, 4114, 16, 16, 17856, 2 }, { 263, 783, 16, 16, 8946, 5 }, { 503, 786, 16, 16, 8946, 5 }, { 747, 789, 16, 16, 8946, 5 }, { 967, 792, 16, 16, 8946, 5 }, { 1187, 795, 16, 16, 8946, 5 }, { 172, 798, 16, 16, 8946, 5 }, { 366, 1513, 1113, 63, 1570, 28 }, { 482, 4169, 2511, 63, 1570, 28 }, { 611, 1500, 778, 63, 1570, 28 }, { 726, 4156, 770, 63, 1570, 28 }, { 843, 1487, 317, 63, 1570, 28 }, { 946, 4143, 660, 63, 1570, 28 }, { 1063, 1474, 308, 63, 1570, 28 }, { 1166, 4130, 654, 63, 1570, 28 }, { 16, 1461, 302, 63, 1570, 28 }, { 134, 4117, 648, 63, 1570, 28 }, { 289, 1448, 296, 63, 1570, 28 }, { 412, 4101, 642, 63, 1570, 28 }, { 531, 1435, 290, 63, 1570, 28 }, { 653, 4088, 636, 63, 1570, 28 }, { 776, 1424, 284, 52, 1680, 42 }, { 886, 4079, 630, 43, 1872, 48 }, { 996, 1417, 278, 36, 2401, 53 }, { 1106, 4072, 624, 36, 2401, 53 }, { 67, 1410, 272, 36, 2401, 53 }, { 184, 4065, 618, 36, 2401, 53 }, { 344, 1403, 266, 36, 2401, 53 }, { 460, 4058, 612, 36, 2401, 53 }, { 583, 1396, 260, 36, 2401, 53 }, { 701, 4051, 606, 36, 2401, 53 }, { 812, 1389, 254, 36, 2401, 53 }, { 918, 4044, 600, 36, 2401, 53 }, { 1032, 1382, 765, 36, 2401, 53 }, { 1138, 4037, 2455, 36, 2401, 53 }, { 103, 1375, 2474, 36, 2401, 53 }, { 216, 4030, 1107, 36, 2401, 53 }, { 599, 1026, 4018, 212, 5314, 92 }, { 717, 1014, 3953, 212, 5314, 92 }, { 831, 1002, 4002, 212, 5314, 92 }, { 937, 990, 3909, 212, 5314, 92 }, { 1051, 978, 3909, 212, 5314, 92 }, { 1157, 966, 3798, 212, 5314, 92 }, { 3, 954, 3798, 212, 5314, 92 }, { 148, 942, 3682, 212, 5314, 92 }, { 275, 930, 3682, 212, 5314, 92 }, { 401, 918, 3562, 212, 5314, 92 }, { 515, 906, 3562, 212, 5314, 92 }, { 641, 894, 3442, 212, 5314, 92 }, { 760, 1070, 3442, 202, 17506, 99 }, { 874, 1060, 3322, 202, 13426, 99 }, { 980, 1052, 3322, 194, 14226, 105 }, { 1094, 1044, 3226, 194, 13698, 105 }, { 51, 1038, 3226, 188, 14049, 110 }, { 200, 1038, 3131, 188, 14049, 110 }, { 328, 1038, 3131, 188, 14049, 110 }, { 448, 1038, 3061, 188, 14049, 110 }, { 567, 1038, 3061, 188, 14049, 110 }, { 689, 1038, 2991, 188, 14049, 110 }, { 796, 1038, 2991, 188, 14049, 110 }, { 906, 1038, 2921, 188, 14049, 110 }, { 1016, 1038, 2921, 188, 14049, 110 }, { 1126, 1038, 2832, 188, 14049, 110 }, { 87, 1038, 2855, 188, 14049, 110 }, { 232, 1038, 2794, 188, 14049, 110 }, { 828, 2677, 4010, 276, 5170, 114 }, { 934, 2659, 3951, 276, 5170, 114 }, { 1048, 2641, 3951, 276, 5170, 114 }, { 1154, 2623, 3842, 276, 5170, 114 }, { 0, 2605, 3842, 276, 5170, 114 }, { 145, 2587, 3743, 276, 5170, 114 }, { 272, 2569, 3743, 276, 5170, 114 }, { 398, 2551, 3625, 276, 5170, 114 }, { 512, 2533, 3625, 276, 5170, 114 }, { 638, 2515, 3505, 276, 5170, 114 }, { 756, 2773, 3505, 260, 17378, 123 }, { 870, 2757, 3385, 260, 13298, 123 }, { 976, 2743, 3385, 246, 14114, 131 }, { 1090, 2729, 3265, 246, 13586, 131 }, { 47, 2717, 3265, 234, 13954, 138 }, { 196, 2705, 3170, 234, 13778, 138 }, { 324, 2695, 3170, 224, 13873, 144 }, { 444, 2695, 3099, 224, 13873, 144 }, { 563, 2695, 3099, 224, 13873, 144 }, { 685, 2695, 3029, 224, 13873, 144 }, { 792, 2695, 3029, 224, 13873, 144 }, { 902, 2695, 2959, 224, 13873, 144 }, { 1012, 2695, 2959, 224, 13873, 144 }, { 1122, 2695, 2856, 224, 13873, 144 }, { 83, 2695, 2856, 224, 13873, 144 }, { 228, 2695, 2795, 224, 13873, 144 }, { 369, 360, 2509, 22, 1956, 11 }, { 614, 388, 583, 22, 1956, 11 }, { 846, 416, 756, 22, 1956, 11 }, { 1066, 444, 747, 22, 1956, 11 }, { 19, 472, 738, 22, 1956, 11 }, { 293, 500, 729, 22, 1956, 11 }, { 535, 528, 720, 22, 1956, 11 }, { 780, 3839, 711, 3, 2336, 16 }, { 1000, 562, 702, 0, 8898, 20 }, { 71, 565, 693, 0, 8898, 20 }, { 348, 568, 684, 0, 8898, 20 }, { 587, 571, 675, 0, 8898, 20 }, { 816, 574, 666, 0, 8898, 20 }, { 1036, 577, 2460, 0, 8898, 20 }, { 107, 580, 2468, 0, 8898, 20 }, { 608, 2343, 2488, 148, 900, 57 }, { 840, 2323, 588, 148, 900, 57 }, { 1060, 2303, 588, 148, 900, 57 }, { 13, 2283, 588, 148, 900, 57 }, { 286, 2263, 588, 148, 900, 57 }, { 527, 2243, 588, 148, 900, 57 }, { 772, 2225, 588, 130, 1328, 66 }, { 992, 2211, 588, 116, 1776, 81 }, { 63, 1588, 588, 104, 2034, 87 }, { 340, 1576, 588, 104, 2034, 87 }, { 579, 1564, 588, 104, 2034, 87 }, { 808, 1552, 588, 104, 2034, 87 }, { 1028, 1540, 588, 104, 2034, 87 }, { 99, 1528, 2382, 104, 2034, 87 }, }; // HPR Register Class... static const MCPhysReg HPR[] = { ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, }; // HPR Bit set. static const uint8_t HPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // SPR Register Class... static const MCPhysReg SPR[] = { ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, }; // SPR Bit set. static const uint8_t SPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // GPR Register Class... static const MCPhysReg GPR[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, }; // GPR Bit set. static const uint8_t GPRBits[] = { 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, }; // GPRwithAPSR Register Class... static const MCPhysReg GPRwithAPSR[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, }; // GPRwithAPSR Bit set. static const uint8_t GPRwithAPSRBits[] = { 0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, }; // SPR_8 Register Class... static const MCPhysReg SPR_8[] = { ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, }; // SPR_8 Bit set. static const uint8_t SPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, }; // GPRnopc Register Class... static const MCPhysReg GPRnopc[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, }; // GPRnopc Bit set. static const uint8_t GPRnopcBits[] = { 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, }; // rGPR Register Class... static const MCPhysReg rGPR[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, }; // rGPR Bit set. static const uint8_t rGPRBits[] = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, }; // tGPRwithpc Register Class... static const MCPhysReg tGPRwithpc[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC, }; // tGPRwithpc Bit set. static const uint8_t tGPRwithpcBits[] = { 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // hGPR Register Class... static const MCPhysReg hGPR[] = { ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, }; // hGPR Bit set. static const uint8_t hGPRBits[] = { 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, }; // tGPR Register Class... static const MCPhysReg tGPR[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, }; // tGPR Bit set. static const uint8_t tGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // GPRnopc_and_hGPR Register Class... static const MCPhysReg GPRnopc_and_hGPR[] = { ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, }; // GPRnopc_and_hGPR Bit set. static const uint8_t GPRnopc_and_hGPRBits[] = { 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, }; // hGPR_and_rGPR Register Class... static const MCPhysReg hGPR_and_rGPR[] = { ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, }; // hGPR_and_rGPR Bit set. static const uint8_t hGPR_and_rGPRBits[] = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, }; // tcGPR Register Class... static const MCPhysReg tcGPR[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, }; // tcGPR Bit set. static const uint8_t tcGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, }; // tGPR_and_tcGPR Register Class... static const MCPhysReg tGPR_and_tcGPR[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, }; // tGPR_and_tcGPR Bit set. static const uint8_t tGPR_and_tcGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, }; // CCR Register Class... static const MCPhysReg CCR[] = { ARM_CPSR, }; // CCR Bit set. static const uint8_t CCRBits[] = { 0x08, }; // GPRsp Register Class... static const MCPhysReg GPRsp[] = { ARM_SP, }; // GPRsp Bit set. static const uint8_t GPRspBits[] = { 0x00, 0x10, }; // hGPR_and_tGPRwithpc Register Class... static const MCPhysReg hGPR_and_tGPRwithpc[] = { ARM_PC, }; // hGPR_and_tGPRwithpc Bit set. static const uint8_t hGPR_and_tGPRwithpcBits[] = { 0x00, 0x08, }; // hGPR_and_tcGPR Register Class... static const MCPhysReg hGPR_and_tcGPR[] = { ARM_R12, }; // hGPR_and_tcGPR Bit set. static const uint8_t hGPR_and_tcGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, }; // DPR Register Class... static const MCPhysReg DPR[] = { ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, }; // DPR Bit set. static const uint8_t DPRBits[] = { 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, }; // DPR_VFP2 Register Class... static const MCPhysReg DPR_VFP2[] = { ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, }; // DPR_VFP2 Bit set. static const uint8_t DPR_VFP2Bits[] = { 0x00, 0xc0, 0xff, 0x3f, }; // DPR_8 Register Class... static const MCPhysReg DPR_8[] = { ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, }; // DPR_8 Bit set. static const uint8_t DPR_8Bits[] = { 0x00, 0xc0, 0x3f, }; // GPRPair Register Class... static const MCPhysReg GPRPair[] = { ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, }; // GPRPair Bit set. static const uint8_t GPRPairBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, }; // GPRPair_with_gsub_1_in_rGPR Register Class... static const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = { ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, }; // GPRPair_with_gsub_1_in_rGPR Bit set. static const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, }; // GPRPair_with_gsub_0_in_tGPR Register Class... static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, }; // GPRPair_with_gsub_0_in_tGPR Bit set. static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, }; // GPRPair_with_gsub_0_in_hGPR Register Class... static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, }; // GPRPair_with_gsub_0_in_hGPR Bit set. static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, }; // GPRPair_with_gsub_0_in_tcGPR Register Class... static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { ARM_R0_R1, ARM_R2_R3, ARM_R12_SP, }; // GPRPair_with_gsub_0_in_tcGPR Bit set. static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, }; // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class... static const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = { ARM_R8_R9, ARM_R10_R11, }; // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set. static const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, }; // GPRPair_with_gsub_1_in_tcGPR Register Class... static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { ARM_R0_R1, ARM_R2_R3, }; // GPRPair_with_gsub_1_in_tcGPR Bit set. static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, }; // GPRPair_with_gsub_1_in_GPRsp Register Class... static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { ARM_R12_SP, }; // GPRPair_with_gsub_1_in_GPRsp Bit set. static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, }; // DPairSpc Register Class... static const MCPhysReg DPairSpc[] = { ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, }; // DPairSpc Bit set. static const uint8_t DPairSpcBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, }; // DPairSpc_with_ssub_0 Register Class... static const MCPhysReg DPairSpc_with_ssub_0[] = { ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, }; // DPairSpc_with_ssub_0 Bit set. static const uint8_t DPairSpc_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, }; // DPairSpc_with_ssub_4 Register Class... static const MCPhysReg DPairSpc_with_ssub_4[] = { ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, }; // DPairSpc_with_ssub_4 Bit set. static const uint8_t DPairSpc_with_ssub_4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, }; // DPairSpc_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, }; // DPairSpc_with_dsub_0_in_DPR_8 Bit set. static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, }; // DPairSpc_with_dsub_2_in_DPR_8 Register Class... static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, }; // DPairSpc_with_dsub_2_in_DPR_8 Bit set. static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, }; // DPair Register Class... static const MCPhysReg DPair[] = { ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15, }; // DPair Bit set. static const uint8_t DPairBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, }; // DPair_with_ssub_0 Register Class... static const MCPhysReg DPair_with_ssub_0[] = { ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, }; // DPair_with_ssub_0 Bit set. static const uint8_t DPair_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, }; // QPR Register Class... static const MCPhysReg QPR[] = { ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, }; // QPR Bit set. static const uint8_t QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // DPair_with_ssub_2 Register Class... static const MCPhysReg DPair_with_ssub_2[] = { ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, }; // DPair_with_ssub_2 Bit set. static const uint8_t DPair_with_ssub_2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, }; // DPair_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, }; // DPair_with_dsub_0_in_DPR_8 Bit set. static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, }; // QPR_VFP2 Register Class... static const MCPhysReg QPR_VFP2[] = { ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, }; // QPR_VFP2 Bit set. static const uint8_t QPR_VFP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // DPair_with_dsub_1_in_DPR_8 Register Class... static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, }; // DPair_with_dsub_1_in_DPR_8 Bit set. static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, }; // QPR_8 Register Class... static const MCPhysReg QPR_8[] = { ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, }; // QPR_8 Bit set. static const uint8_t QPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, }; // DTriple Register Class... static const MCPhysReg DTriple[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31, }; // DTriple Bit set. static const uint8_t DTripleBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, }; // DTripleSpc Register Class... static const MCPhysReg DTripleSpc[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, }; // DTripleSpc Bit set. static const uint8_t DTripleSpcBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, }; // DTripleSpc_with_ssub_0 Register Class... static const MCPhysReg DTripleSpc_with_ssub_0[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, }; // DTripleSpc_with_ssub_0 Bit set. static const uint8_t DTripleSpc_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, }; // DTriple_with_ssub_0 Register Class... static const MCPhysReg DTriple_with_ssub_0[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, }; // DTriple_with_ssub_0 Bit set. static const uint8_t DTriple_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, }; // DTriple_with_qsub_0_in_QPR Register Class... static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = { ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, }; // DTriple_with_qsub_0_in_QPR Bit set. static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, }; // DTriple_with_ssub_2 Register Class... static const MCPhysReg DTriple_with_ssub_2[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, }; // DTriple_with_ssub_2 Bit set. static const uint8_t DTriple_with_ssub_2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, }; // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, }; // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, }; // DTripleSpc_with_ssub_4 Register Class... static const MCPhysReg DTripleSpc_with_ssub_4[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, }; // DTripleSpc_with_ssub_4 Bit set. static const uint8_t DTripleSpc_with_ssub_4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, }; // DTriple_with_ssub_4 Register Class... static const MCPhysReg DTriple_with_ssub_4[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, }; // DTriple_with_ssub_4 Bit set. static const uint8_t DTriple_with_ssub_4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, }; // DTripleSpc_with_ssub_8 Register Class... static const MCPhysReg DTripleSpc_with_ssub_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, }; // DTripleSpc_with_ssub_8 Bit set. static const uint8_t DTripleSpc_with_ssub_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, }; // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, }; // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, }; // DTriple_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, }; // DTriple_with_dsub_0_in_DPR_8 Bit set. static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, }; // DTriple_with_qsub_0_in_QPR_VFP2 Register Class... static const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = { ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, }; // DTriple_with_qsub_0_in_QPR_VFP2 Bit set. static const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, }; // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, }; // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, }; // DTriple_with_dsub_1_in_DPR_8 Register Class... static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, }; // DTriple_with_dsub_1_in_DPR_8 Bit set. static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, }; // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class... static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = { ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, }; // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set. static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, }; // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class... static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = { ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, }; // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set. static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, }; // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, }; // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, }; // DTriple_with_dsub_2_in_DPR_8 Register Class... static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, }; // DTriple_with_dsub_2_in_DPR_8 Bit set. static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, }; // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, }; // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, }; // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, }; // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, }; // DTriple_with_qsub_0_in_QPR_8 Register Class... static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, }; // DTriple_with_qsub_0_in_QPR_8 Bit set. static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, }; // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class... static const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = { ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, }; // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set. static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, }; // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, }; // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, }; // DQuadSpc Register Class... static const MCPhysReg DQuadSpc[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, }; // DQuadSpc Bit set. static const uint8_t DQuadSpcBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, }; // DQuadSpc_with_ssub_0 Register Class... static const MCPhysReg DQuadSpc_with_ssub_0[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, }; // DQuadSpc_with_ssub_0 Bit set. static const uint8_t DQuadSpc_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, }; // DQuadSpc_with_ssub_4 Register Class... static const MCPhysReg DQuadSpc_with_ssub_4[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, }; // DQuadSpc_with_ssub_4 Bit set. static const uint8_t DQuadSpc_with_ssub_4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, }; // DQuadSpc_with_ssub_8 Register Class... static const MCPhysReg DQuadSpc_with_ssub_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, }; // DQuadSpc_with_ssub_8 Bit set. static const uint8_t DQuadSpc_with_ssub_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, }; // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, }; // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, }; // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, }; // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, }; // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, }; // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, }; // DQuad Register Class... static const MCPhysReg DQuad[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15, }; // DQuad Bit set. static const uint8_t DQuadBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, }; // DQuad_with_ssub_0 Register Class... static const MCPhysReg DQuad_with_ssub_0[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, }; // DQuad_with_ssub_0 Bit set. static const uint8_t DQuad_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // DQuad_with_ssub_2 Register Class... static const MCPhysReg DQuad_with_ssub_2[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, }; // DQuad_with_ssub_2 Bit set. static const uint8_t DQuad_with_ssub_2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, }; // QQPR Register Class... static const MCPhysReg QQPR[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, }; // QQPR Bit set. static const uint8_t QQPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, }; // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, }; // DQuad_with_ssub_4 Register Class... static const MCPhysReg DQuad_with_ssub_4[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, }; // DQuad_with_ssub_4 Bit set. static const uint8_t DQuad_with_ssub_4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, }; // DQuad_with_ssub_6 Register Class... static const MCPhysReg DQuad_with_ssub_6[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, }; // DQuad_with_ssub_6 Bit set. static const uint8_t DQuad_with_ssub_6Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, }; // DQuad_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, }; // DQuad_with_dsub_0_in_DPR_8 Bit set. static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // DQuad_with_qsub_0_in_QPR_VFP2 Register Class... static const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, }; // DQuad_with_qsub_0_in_QPR_VFP2 Bit set. static const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, }; // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // DQuad_with_dsub_1_in_DPR_8 Register Class... static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, }; // DQuad_with_dsub_1_in_DPR_8 Bit set. static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, }; // DQuad_with_qsub_1_in_QPR_VFP2 Register Class... static const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, }; // DQuad_with_qsub_1_in_QPR_VFP2 Bit set. static const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class... static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, }; // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set. static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, }; // DQuad_with_dsub_2_in_DPR_8 Register Class... static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, }; // DQuad_with_dsub_2_in_DPR_8 Bit set. static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, }; // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, }; // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, }; // DQuad_with_dsub_3_in_DPR_8 Register Class... static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, }; // DQuad_with_dsub_3_in_DPR_8 Bit set. static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, }; // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, }; // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // DQuad_with_qsub_0_in_QPR_8 Register Class... static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, }; // DQuad_with_qsub_0_in_QPR_8 Bit set. static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, }; // DQuad_with_qsub_1_in_QPR_8 Register Class... static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, }; // DQuad_with_qsub_1_in_QPR_8 Bit set. static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, }; // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, }; // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, }; // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... static const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, }; // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, }; // QQQQPR Register Class... static const MCPhysReg QQQQPR[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15, }; // QQQQPR Bit set. static const uint8_t QQQQPRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, }; // QQQQPR_with_ssub_0 Register Class... static const MCPhysReg QQQQPR_with_ssub_0[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, }; // QQQQPR_with_ssub_0 Bit set. static const uint8_t QQQQPR_with_ssub_0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, }; // QQQQPR_with_ssub_4 Register Class... static const MCPhysReg QQQQPR_with_ssub_4[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, }; // QQQQPR_with_ssub_4 Bit set. static const uint8_t QQQQPR_with_ssub_4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, }; // QQQQPR_with_ssub_8 Register Class... static const MCPhysReg QQQQPR_with_ssub_8[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, }; // QQQQPR_with_ssub_8 Bit set. static const uint8_t QQQQPR_with_ssub_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, }; // QQQQPR_with_ssub_12 Register Class... static const MCPhysReg QQQQPR_with_ssub_12[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, }; // QQQQPR_with_ssub_12 Bit set. static const uint8_t QQQQPR_with_ssub_12Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, }; // QQQQPR_with_dsub_0_in_DPR_8 Register Class... static const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, }; // QQQQPR_with_dsub_0_in_DPR_8 Bit set. static const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, }; // QQQQPR_with_dsub_2_in_DPR_8 Register Class... static const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, }; // QQQQPR_with_dsub_2_in_DPR_8 Bit set. static const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, }; // QQQQPR_with_dsub_4_in_DPR_8 Register Class... static const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = { ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, }; // QQQQPR_with_dsub_4_in_DPR_8 Bit set. static const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, }; // QQQQPR_with_dsub_6_in_DPR_8 Register Class... static const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = { ARM_Q0_Q1_Q2_Q3, }; // QQQQPR_with_dsub_6_in_DPR_8 Bit set. static const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, }; static const MCRegisterClass ARMMCRegisterClasses[] = { { HPR, HPRBits, sizeof(HPRBits) }, { SPR, SPRBits, sizeof(SPRBits) }, { GPR, GPRBits, sizeof(GPRBits) }, { GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits) }, { SPR_8, SPR_8Bits, sizeof(SPR_8Bits) }, { GPRnopc, GPRnopcBits, sizeof(GPRnopcBits) }, { rGPR, rGPRBits, sizeof(rGPRBits) }, { tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits) }, { hGPR, hGPRBits, sizeof(hGPRBits) }, { tGPR, tGPRBits, sizeof(tGPRBits) }, { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, sizeof(GPRnopc_and_hGPRBits) }, { hGPR_and_rGPR, hGPR_and_rGPRBits, sizeof(hGPR_and_rGPRBits) }, { tcGPR, tcGPRBits, sizeof(tcGPRBits) }, { tGPR_and_tcGPR, tGPR_and_tcGPRBits, sizeof(tGPR_and_tcGPRBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { GPRsp, GPRspBits, sizeof(GPRspBits) }, { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, sizeof(hGPR_and_tGPRwithpcBits) }, { hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits) }, { DPR, DPRBits, sizeof(DPRBits) }, { DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits) }, { DPR_8, DPR_8Bits, sizeof(DPR_8Bits) }, { GPRPair, GPRPairBits, sizeof(GPRPairBits) }, { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, sizeof(GPRPair_with_gsub_1_in_rGPRBits) }, { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, sizeof(GPRPair_with_gsub_0_in_tGPRBits) }, { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPair_with_gsub_0_in_hGPRBits) }, { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, sizeof(GPRPair_with_gsub_0_in_tcGPRBits) }, { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits) }, { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, sizeof(GPRPair_with_gsub_1_in_tcGPRBits) }, { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, sizeof(GPRPair_with_gsub_1_in_GPRspBits) }, { DPairSpc, DPairSpcBits, sizeof(DPairSpcBits) }, { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, sizeof(DPairSpc_with_ssub_0Bits) }, { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, sizeof(DPairSpc_with_ssub_4Bits) }, { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits) }, { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits) }, { DPair, DPairBits, sizeof(DPairBits) }, { DPair_with_ssub_0, DPair_with_ssub_0Bits, sizeof(DPair_with_ssub_0Bits) }, { QPR, QPRBits, sizeof(QPRBits) }, { DPair_with_ssub_2, DPair_with_ssub_2Bits, sizeof(DPair_with_ssub_2Bits) }, { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, sizeof(DPair_with_dsub_0_in_DPR_8Bits) }, { QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits) }, { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, sizeof(DPair_with_dsub_1_in_DPR_8Bits) }, { QPR_8, QPR_8Bits, sizeof(QPR_8Bits) }, { DTriple, DTripleBits, sizeof(DTripleBits) }, { DTripleSpc, DTripleSpcBits, sizeof(DTripleSpcBits) }, { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, sizeof(DTripleSpc_with_ssub_0Bits) }, { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, sizeof(DTriple_with_ssub_0Bits) }, { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_qsub_0_in_QPRBits) }, { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, sizeof(DTriple_with_ssub_2Bits) }, { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, sizeof(DTripleSpc_with_ssub_4Bits) }, { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, sizeof(DTriple_with_ssub_4Bits) }, { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, sizeof(DTripleSpc_with_ssub_8Bits) }, { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits) }, { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, sizeof(DTriple_with_dsub_0_in_DPR_8Bits) }, { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits) }, { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, sizeof(DTriple_with_dsub_1_in_DPR_8Bits) }, { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) }, { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits) }, { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits) }, { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, sizeof(DTriple_with_dsub_2_in_DPR_8Bits) }, { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits) }, { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, sizeof(DTriple_with_qsub_0_in_QPR_8Bits) }, { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits) }, { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) }, { DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits) }, { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, sizeof(DQuadSpc_with_ssub_0Bits) }, { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, sizeof(DQuadSpc_with_ssub_4Bits) }, { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, sizeof(DQuadSpc_with_ssub_8Bits) }, { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits) }, { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits) }, { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits) }, { DQuad, DQuadBits, sizeof(DQuadBits) }, { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, sizeof(DQuad_with_ssub_0Bits) }, { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, sizeof(DQuad_with_ssub_2Bits) }, { QQPR, QQPRBits, sizeof(QQPRBits) }, { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, sizeof(DQuad_with_ssub_4Bits) }, { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, sizeof(DQuad_with_ssub_6Bits) }, { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, sizeof(DQuad_with_dsub_0_in_DPR_8Bits) }, { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits) }, { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, sizeof(DQuad_with_dsub_1_in_DPR_8Bits) }, { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits) }, { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) }, { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, sizeof(DQuad_with_dsub_2_in_DPR_8Bits) }, { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, sizeof(DQuad_with_dsub_3_in_DPR_8Bits) }, { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, sizeof(DQuad_with_qsub_0_in_QPR_8Bits) }, { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, sizeof(DQuad_with_qsub_1_in_QPR_8Bits) }, { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) }, { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) }, { QQQQPR, QQQQPRBits, sizeof(QQQQPRBits) }, { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, sizeof(QQQQPR_with_ssub_0Bits) }, { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, sizeof(QQQQPR_with_ssub_4Bits) }, { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, sizeof(QQQQPR_with_ssub_8Bits) }, { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, sizeof(QQQQPR_with_ssub_12Bits) }, { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits) }, { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits) }, { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits) }, { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/ARM/ARMGenRegisterName.inc000064400000000000000000000261220072674642500216140ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, /* 39 */ 'd', '1', '0', 0, /* 43 */ 'q', '1', '0', 0, /* 47 */ 's', '1', '0', 0, /* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, /* 83 */ 'd', '2', '0', 0, /* 87 */ 's', '2', '0', 0, /* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, /* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, /* 123 */ 'd', '3', '0', 0, /* 127 */ 's', '3', '0', 0, /* 131 */ 'd', '0', 0, /* 134 */ 'q', '0', 0, /* 137 */ 'm', 'v', 'f', 'r', '0', 0, /* 143 */ 's', '0', 0, /* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, /* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, /* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, /* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0, /* 192 */ 'd', '1', '1', 0, /* 196 */ 'q', '1', '1', 0, /* 200 */ 's', '1', '1', 0, /* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, /* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, /* 232 */ 'd', '2', '1', 0, /* 236 */ 's', '2', '1', 0, /* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, /* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, /* 268 */ 'd', '3', '1', 0, /* 272 */ 's', '3', '1', 0, /* 276 */ 'Q', '0', '_', 'Q', '1', 0, /* 282 */ 'R', '0', '_', 'R', '1', 0, /* 288 */ 'd', '1', 0, /* 291 */ 'q', '1', 0, /* 294 */ 'm', 'v', 'f', 'r', '1', 0, /* 300 */ 's', '1', 0, /* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, /* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, /* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, /* 347 */ 'd', '1', '2', 0, /* 351 */ 'q', '1', '2', 0, /* 355 */ 's', '1', '2', 0, /* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, /* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, /* 391 */ 'd', '2', '2', 0, /* 395 */ 's', '2', '2', 0, /* 399 */ 'D', '0', '_', 'D', '2', 0, /* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, /* 414 */ 'Q', '1', '_', 'Q', '2', 0, /* 420 */ 'd', '2', 0, /* 423 */ 'q', '2', 0, /* 426 */ 'm', 'v', 'f', 'r', '2', 0, /* 432 */ 's', '2', 0, /* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, /* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, /* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, /* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, /* 485 */ 'd', '1', '3', 0, /* 489 */ 'q', '1', '3', 0, /* 493 */ 's', '1', '3', 0, /* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, /* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, /* 525 */ 'd', '2', '3', 0, /* 529 */ 's', '2', '3', 0, /* 533 */ 'D', '1', '_', 'D', '3', 0, /* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, /* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, /* 560 */ 'R', '2', '_', 'R', '3', 0, /* 566 */ 'd', '3', 0, /* 569 */ 'q', '3', 0, /* 572 */ 'r', '3', 0, /* 575 */ 's', '3', 0, /* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, /* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, /* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, /* 625 */ 'd', '1', '4', 0, /* 629 */ 'q', '1', '4', 0, /* 633 */ 's', '1', '4', 0, /* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, /* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, /* 669 */ 'd', '2', '4', 0, /* 673 */ 's', '2', '4', 0, /* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, /* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, /* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, /* 710 */ 'd', '4', 0, /* 713 */ 'q', '4', 0, /* 716 */ 'r', '4', 0, /* 719 */ 's', '4', 0, /* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, /* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, /* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, /* 765 */ 'd', '1', '5', 0, /* 769 */ 'q', '1', '5', 0, /* 773 */ 's', '1', '5', 0, /* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, /* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, /* 805 */ 'd', '2', '5', 0, /* 809 */ 's', '2', '5', 0, /* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, /* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, /* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, /* 843 */ 'R', '4', '_', 'R', '5', 0, /* 849 */ 'd', '5', 0, /* 852 */ 'q', '5', 0, /* 855 */ 'r', '5', 0, /* 858 */ 's', '5', 0, /* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, /* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, /* 893 */ 'd', '1', '6', 0, /* 897 */ 's', '1', '6', 0, /* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, /* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, /* 933 */ 'd', '2', '6', 0, /* 937 */ 's', '2', '6', 0, /* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, /* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, /* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, /* 977 */ 'd', '6', 0, /* 980 */ 'q', '6', 0, /* 983 */ 'r', '6', 0, /* 986 */ 's', '6', 0, /* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, /* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, /* 1017 */ 'd', '1', '7', 0, /* 1021 */ 's', '1', '7', 0, /* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, /* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, /* 1053 */ 'd', '2', '7', 0, /* 1057 */ 's', '2', '7', 0, /* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, /* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, /* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, /* 1094 */ 'R', '6', '_', 'R', '7', 0, /* 1100 */ 'd', '7', 0, /* 1103 */ 'q', '7', 0, /* 1106 */ 'r', '7', 0, /* 1109 */ 's', '7', 0, /* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, /* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, /* 1144 */ 'd', '1', '8', 0, /* 1148 */ 's', '1', '8', 0, /* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, /* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, /* 1184 */ 'd', '2', '8', 0, /* 1188 */ 's', '2', '8', 0, /* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, /* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, /* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, /* 1228 */ 'd', '8', 0, /* 1231 */ 'q', '8', 0, /* 1234 */ 'r', '8', 0, /* 1237 */ 's', '8', 0, /* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, /* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, /* 1268 */ 'd', '1', '9', 0, /* 1272 */ 's', '1', '9', 0, /* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, /* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, /* 1304 */ 'd', '2', '9', 0, /* 1308 */ 's', '2', '9', 0, /* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, /* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, /* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, /* 1345 */ 'R', '8', '_', 'R', '9', 0, /* 1351 */ 'd', '9', 0, /* 1354 */ 'q', '9', 0, /* 1357 */ 's', '9', 0, /* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0, /* 1367 */ 's', 'b', 0, /* 1370 */ 'p', 'c', 0, /* 1373 */ 'f', 'p', 'e', 'x', 'c', 0, /* 1379 */ 'f', 'p', 's', 'i', 'd', 0, /* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, /* 1393 */ 's', 'l', 0, /* 1396 */ 'f', 'p', 0, /* 1399 */ 'i', 'p', 0, /* 1402 */ 's', 'p', 0, /* 1405 */ 'f', 'p', 's', 'c', 'r', 0, /* 1411 */ 'l', 'r', 0, /* 1414 */ 'a', 'p', 's', 'r', 0, /* 1419 */ 'c', 'p', 's', 'r', 0, /* 1424 */ 's', 'p', 's', 'r', 0, /* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0, /* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, /* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, }; static const uint16_t RegAsmOffset[] = { 1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131, 288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625, 765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184, 1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980, 1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716, 855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858, 986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272, 87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533, 680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997, 1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260, 276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617, 757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749, 1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207, 1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379, 513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195, 1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363, 501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0, 157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637, 777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601, 885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593, 877, 1128, 67, 375, 653, 917, 1168, 107, }; return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/ARM/ARMGenRegisterName_digit.inc000064400000000000000000000261600072674642500227760ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName_digit(unsigned RegNo) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, /* 39 */ 'd', '1', '0', 0, /* 43 */ 'q', '1', '0', 0, /* 47 */ 'r', '1', '0', 0, /* 51 */ 's', '1', '0', 0, /* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, /* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, /* 87 */ 'd', '2', '0', 0, /* 91 */ 's', '2', '0', 0, /* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, /* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, /* 127 */ 'd', '3', '0', 0, /* 131 */ 's', '3', '0', 0, /* 135 */ 'd', '0', 0, /* 138 */ 'q', '0', 0, /* 141 */ 'm', 'v', 'f', 'r', '0', 0, /* 147 */ 's', '0', 0, /* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, /* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, /* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, /* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0, /* 196 */ 'd', '1', '1', 0, /* 200 */ 'q', '1', '1', 0, /* 204 */ 'r', '1', '1', 0, /* 208 */ 's', '1', '1', 0, /* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, /* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, /* 240 */ 'd', '2', '1', 0, /* 244 */ 's', '2', '1', 0, /* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, /* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, /* 276 */ 'd', '3', '1', 0, /* 280 */ 's', '3', '1', 0, /* 284 */ 'Q', '0', '_', 'Q', '1', 0, /* 290 */ 'R', '0', '_', 'R', '1', 0, /* 296 */ 'd', '1', 0, /* 299 */ 'q', '1', 0, /* 302 */ 'm', 'v', 'f', 'r', '1', 0, /* 308 */ 's', '1', 0, /* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, /* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, /* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, /* 355 */ 'd', '1', '2', 0, /* 359 */ 'q', '1', '2', 0, /* 363 */ 'r', '1', '2', 0, /* 367 */ 's', '1', '2', 0, /* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, /* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, /* 403 */ 'd', '2', '2', 0, /* 407 */ 's', '2', '2', 0, /* 411 */ 'D', '0', '_', 'D', '2', 0, /* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, /* 426 */ 'Q', '1', '_', 'Q', '2', 0, /* 432 */ 'd', '2', 0, /* 435 */ 'q', '2', 0, /* 438 */ 'm', 'v', 'f', 'r', '2', 0, /* 444 */ 's', '2', 0, /* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, /* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, /* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, /* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, /* 497 */ 'd', '1', '3', 0, /* 501 */ 'q', '1', '3', 0, /* 505 */ 'r', '1', '3', 0, /* 509 */ 's', '1', '3', 0, /* 513 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, /* 529 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, /* 541 */ 'd', '2', '3', 0, /* 545 */ 's', '2', '3', 0, /* 549 */ 'D', '1', '_', 'D', '3', 0, /* 555 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, /* 564 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, /* 576 */ 'R', '2', '_', 'R', '3', 0, /* 582 */ 'd', '3', 0, /* 585 */ 'q', '3', 0, /* 588 */ 'r', '3', 0, /* 591 */ 's', '3', 0, /* 594 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, /* 609 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, /* 625 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, /* 641 */ 'd', '1', '4', 0, /* 645 */ 'q', '1', '4', 0, /* 649 */ 'r', '1', '4', 0, /* 653 */ 's', '1', '4', 0, /* 657 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, /* 673 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, /* 689 */ 'd', '2', '4', 0, /* 693 */ 's', '2', '4', 0, /* 697 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, /* 706 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, /* 718 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, /* 730 */ 'd', '4', 0, /* 733 */ 'q', '4', 0, /* 736 */ 'r', '4', 0, /* 739 */ 's', '4', 0, /* 742 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, /* 757 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, /* 769 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, /* 785 */ 'd', '1', '5', 0, /* 789 */ 'q', '1', '5', 0, /* 793 */ 's', '1', '5', 0, /* 797 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, /* 813 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, /* 825 */ 'd', '2', '5', 0, /* 829 */ 's', '2', '5', 0, /* 833 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, /* 842 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, /* 851 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, /* 863 */ 'R', '4', '_', 'R', '5', 0, /* 869 */ 'd', '5', 0, /* 872 */ 'q', '5', 0, /* 875 */ 'r', '5', 0, /* 878 */ 's', '5', 0, /* 881 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, /* 897 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, /* 913 */ 'd', '1', '6', 0, /* 917 */ 's', '1', '6', 0, /* 921 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, /* 937 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, /* 953 */ 'd', '2', '6', 0, /* 957 */ 's', '2', '6', 0, /* 961 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, /* 973 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, /* 985 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, /* 997 */ 'd', '6', 0, /* 1000 */ 'q', '6', 0, /* 1003 */ 'r', '6', 0, /* 1006 */ 's', '6', 0, /* 1009 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, /* 1025 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, /* 1037 */ 'd', '1', '7', 0, /* 1041 */ 's', '1', '7', 0, /* 1045 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, /* 1061 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, /* 1073 */ 'd', '2', '7', 0, /* 1077 */ 's', '2', '7', 0, /* 1081 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, /* 1093 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, /* 1102 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, /* 1114 */ 'R', '6', '_', 'R', '7', 0, /* 1120 */ 'd', '7', 0, /* 1123 */ 'q', '7', 0, /* 1126 */ 'r', '7', 0, /* 1129 */ 's', '7', 0, /* 1132 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, /* 1148 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, /* 1164 */ 'd', '1', '8', 0, /* 1168 */ 's', '1', '8', 0, /* 1172 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, /* 1188 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, /* 1204 */ 'd', '2', '8', 0, /* 1208 */ 's', '2', '8', 0, /* 1212 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, /* 1224 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, /* 1236 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, /* 1248 */ 'd', '8', 0, /* 1251 */ 'q', '8', 0, /* 1254 */ 'r', '8', 0, /* 1257 */ 's', '8', 0, /* 1260 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, /* 1276 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, /* 1288 */ 'd', '1', '9', 0, /* 1292 */ 's', '1', '9', 0, /* 1296 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, /* 1312 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, /* 1324 */ 'd', '2', '9', 0, /* 1328 */ 's', '2', '9', 0, /* 1332 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, /* 1344 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, /* 1353 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, /* 1365 */ 'R', '8', '_', 'R', '9', 0, /* 1371 */ 'd', '9', 0, /* 1374 */ 'q', '9', 0, /* 1377 */ 'r', '9', 0, /* 1380 */ 's', '9', 0, /* 1383 */ 'R', '1', '2', '_', 'S', 'P', 0, /* 1390 */ 'p', 'c', 0, /* 1393 */ 'f', 'p', 'e', 'x', 'c', 0, /* 1399 */ 'f', 'p', 's', 'i', 'd', 0, /* 1405 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, /* 1413 */ 'f', 'p', 's', 'c', 'r', 0, /* 1419 */ 'a', 'p', 's', 'r', 0, /* 1424 */ 'c', 'p', 's', 'r', 0, /* 1429 */ 's', 'p', 's', 'r', 0, /* 1434 */ 'f', 'p', 'i', 'n', 's', 't', 0, /* 1441 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, /* 1452 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, }; static const uint16_t RegAsmOffset[] = { 1419, 1452, 1424, 1393, 1434, 1413, 1441, 1399, 1405, 649, 1390, 505, 1429, 135, 296, 432, 582, 730, 869, 997, 1120, 1248, 1371, 39, 196, 355, 497, 641, 785, 913, 1037, 1164, 1288, 87, 240, 403, 541, 689, 825, 953, 1073, 1204, 1324, 127, 276, 447, 141, 302, 438, 138, 299, 435, 585, 733, 872, 1000, 1123, 1251, 1374, 43, 200, 359, 501, 645, 789, 144, 305, 441, 588, 736, 875, 1003, 1126, 1254, 1377, 47, 204, 363, 147, 308, 444, 591, 739, 878, 1006, 1129, 1257, 1380, 51, 208, 367, 509, 653, 793, 917, 1041, 1168, 1292, 91, 244, 407, 545, 693, 829, 957, 1077, 1208, 1328, 131, 280, 411, 549, 700, 836, 967, 1087, 1218, 1338, 6, 167, 317, 461, 601, 749, 889, 1017, 1140, 1268, 63, 232, 379, 521, 665, 805, 929, 1053, 1180, 1304, 103, 268, 284, 426, 570, 724, 857, 991, 1108, 1242, 1359, 32, 180, 347, 489, 633, 777, 564, 718, 851, 985, 1102, 1236, 1353, 26, 174, 340, 481, 625, 769, 1383, 290, 576, 863, 1114, 1365, 188, 417, 555, 709, 842, 976, 1093, 1227, 1344, 16, 150, 328, 469, 613, 757, 901, 1025, 1152, 1276, 75, 212, 391, 529, 677, 813, 941, 1061, 1192, 1312, 115, 248, 697, 833, 964, 1084, 1215, 1335, 3, 164, 314, 458, 597, 745, 885, 1013, 1136, 1264, 59, 228, 375, 517, 661, 801, 925, 1049, 1176, 1300, 99, 264, 961, 1081, 1212, 1332, 0, 161, 311, 455, 594, 742, 881, 1009, 1132, 1260, 55, 224, 371, 513, 657, 797, 921, 1045, 1172, 1296, 95, 260, 420, 712, 979, 1230, 19, 332, 617, 905, 1156, 79, 395, 681, 945, 1196, 119, 706, 973, 1224, 13, 325, 609, 897, 1148, 71, 387, 673, 937, 1188, 111, }; return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/ARM/ARMGenSubtargetInfo.inc000064400000000000000000000104640072674642500220050ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ enum { ARM_ARMv2 = 0, ARM_ARMv2a = 1, ARM_ARMv3 = 2, ARM_ARMv3m = 3, ARM_ARMv4 = 4, ARM_ARMv4t = 5, ARM_ARMv5t = 6, ARM_ARMv5te = 7, ARM_ARMv5tej = 8, ARM_ARMv6 = 9, ARM_ARMv6j = 10, ARM_ARMv6k = 11, ARM_ARMv6kz = 12, ARM_ARMv6m = 13, ARM_ARMv6sm = 14, ARM_ARMv6t2 = 15, ARM_ARMv7a = 16, ARM_ARMv7em = 17, ARM_ARMv7k = 18, ARM_ARMv7m = 19, ARM_ARMv7r = 20, ARM_ARMv7s = 21, ARM_ARMv7ve = 22, ARM_ARMv8a = 23, ARM_ARMv8mBaseline = 24, ARM_ARMv8mMainline = 25, ARM_ARMv8r = 26, ARM_ARMv81a = 27, ARM_ARMv82a = 28, ARM_ARMv83a = 29, ARM_ARMv84a = 30, ARM_Feature8MSecExt = 31, ARM_FeatureAClass = 32, ARM_FeatureAES = 33, ARM_FeatureAcquireRelease = 34, ARM_FeatureAvoidMOVsShOp = 35, ARM_FeatureAvoidPartialCPSR = 36, ARM_FeatureCRC = 37, ARM_FeatureCheapPredicableCPSR = 38, ARM_FeatureCheckVLDnAlign = 39, ARM_FeatureCrypto = 40, ARM_FeatureD16 = 41, ARM_FeatureDB = 42, ARM_FeatureDFB = 43, ARM_FeatureDSP = 44, ARM_FeatureDontWidenVMOVS = 45, ARM_FeatureDotProd = 46, ARM_FeatureExecuteOnly = 47, ARM_FeatureExpandMLx = 48, ARM_FeatureFP16 = 49, ARM_FeatureFPAO = 50, ARM_FeatureFPARMv8 = 51, ARM_FeatureFullFP16 = 52, ARM_FeatureFuseAES = 53, ARM_FeatureFuseLiterals = 54, ARM_FeatureHWDivARM = 55, ARM_FeatureHWDivThumb = 56, ARM_FeatureHasNoBranchPredictor = 57, ARM_FeatureHasRetAddrStack = 58, ARM_FeatureHasSlowFPVMLx = 59, ARM_FeatureHasVMLxHazards = 60, ARM_FeatureLongCalls = 61, ARM_FeatureMClass = 62, ARM_FeatureMP = 63, ARM_FeatureMuxedUnits = 64, ARM_FeatureNEON = 65, ARM_FeatureNEONForFP = 66, ARM_FeatureNEONForFPMovs = 67, ARM_FeatureNaClTrap = 68, ARM_FeatureNoARM = 69, ARM_FeatureNoMovt = 70, ARM_FeatureNoNegativeImmediates = 71, ARM_FeatureNoPostRASched = 72, ARM_FeatureNonpipelinedVFP = 73, ARM_FeaturePerfMon = 74, ARM_FeaturePref32BitThumb = 75, ARM_FeaturePrefISHSTBarrier = 76, ARM_FeaturePreferVMOVSR = 77, ARM_FeatureProfUnpredicate = 78, ARM_FeatureRAS = 79, ARM_FeatureRClass = 80, ARM_FeatureReadTp = 81, ARM_FeatureReserveR9 = 82, ARM_FeatureSHA2 = 83, ARM_FeatureSlowFPBrcc = 84, ARM_FeatureSlowLoadDSubreg = 85, ARM_FeatureSlowOddRegister = 86, ARM_FeatureSlowVDUP32 = 87, ARM_FeatureSlowVGETLNi32 = 88, ARM_FeatureSplatVFPToNeon = 89, ARM_FeatureStrictAlign = 90, ARM_FeatureThumb2 = 91, ARM_FeatureTrustZone = 92, ARM_FeatureUseAA = 93, ARM_FeatureUseMISched = 94, ARM_FeatureV7Clrex = 95, ARM_FeatureVFP2 = 96, ARM_FeatureVFP3 = 97, ARM_FeatureVFP4 = 98, ARM_FeatureVFPOnlySP = 99, ARM_FeatureVMLxForwarding = 100, ARM_FeatureVirtualization = 101, ARM_FeatureZCZeroing = 102, ARM_HasV4TOps = 103, ARM_HasV5TEOps = 104, ARM_HasV5TOps = 105, ARM_HasV6KOps = 106, ARM_HasV6MOps = 107, ARM_HasV6Ops = 108, ARM_HasV6T2Ops = 109, ARM_HasV7Ops = 110, ARM_HasV8MBaselineOps = 111, ARM_HasV8MMainlineOps = 112, ARM_HasV8Ops = 113, ARM_HasV8_1aOps = 114, ARM_HasV8_2aOps = 115, ARM_HasV8_3aOps = 116, ARM_HasV8_4aOps = 117, ARM_IWMMXT = 118, ARM_IWMMXT2 = 119, ARM_ModeSoftFloat = 120, ARM_ModeThumb = 121, ARM_ProcA5 = 122, ARM_ProcA7 = 123, ARM_ProcA8 = 124, ARM_ProcA9 = 125, ARM_ProcA12 = 126, ARM_ProcA15 = 127, ARM_ProcA17 = 128, ARM_ProcA32 = 129, ARM_ProcA35 = 130, ARM_ProcA53 = 131, ARM_ProcA55 = 132, ARM_ProcA57 = 133, ARM_ProcA72 = 134, ARM_ProcA73 = 135, ARM_ProcA75 = 136, ARM_ProcExynosM1 = 137, ARM_ProcKrait = 138, ARM_ProcKryo = 139, ARM_ProcM3 = 140, ARM_ProcR4 = 141, ARM_ProcR5 = 142, ARM_ProcR7 = 143, ARM_ProcR52 = 144, ARM_ProcSwift = 145, ARM_XScale = 146, }; capstone-sys-0.15.0/capstone/arch/ARM/ARMGenSystemRegister.inc000064400000000000000000000211210072674642500222120ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* GenSystemRegister Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ enum BankedRegValues { elr_hyp = 0, lr_abt = 1, lr_fiq = 2, lr_irq = 3, lr_mon = 4, lr_svc = 5, lr_und = 6, lr_usr = 7, r10_fiq = 8, r10_usr = 9, r11_fiq = 10, r11_usr = 11, r12_fiq = 12, r12_usr = 13, r8_fiq = 14, r8_usr = 15, r9_fiq = 16, r9_usr = 17, sp_abt = 18, sp_fiq = 19, sp_hyp = 20, sp_irq = 21, sp_mon = 22, sp_svc = 23, sp_und = 24, sp_usr = 25, spsr_abt = 26, spsr_fiq = 27, spsr_hyp = 28, spsr_irq = 29, spsr_mon = 30, spsr_svc = 31, spsr_und = 32, }; static const MClassSysReg MClassSysRegsList[] = { { "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0 { "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1 { "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2 { "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01, {ARM_FeatureDSP} }, // 3 { "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402, {ARM_FeatureDSP} }, // 4 { "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02, {ARM_FeatureDSP} }, // 5 { "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403, {ARM_FeatureDSP} }, // 6 { "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03, {ARM_FeatureDSP} }, // 7 { "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800, { 0 } }, // 8 { "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800, { 0 } }, // 9 { "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801, { 0 } }, // 10 { "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801, { 0 } }, // 11 { "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802, { 0 } }, // 12 { "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802, { 0 } }, // 13 { "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803, { 0 } }, // 14 { "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803, { 0 } }, // 15 { "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805, { 0 } }, // 16 { "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806, { 0 } }, // 17 { "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807, { 0 } }, // 18 { "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808, { 0 } }, // 19 { "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809, { 0 } }, // 20 { "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A, {ARM_HasV8MBaselineOps} }, // 21 { "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B, {ARM_HasV8MBaselineOps} }, // 22 { "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810, { 0 } }, // 23 { "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811, {ARM_HasV7Ops} }, // 24 { "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812, {ARM_HasV7Ops} }, // 25 { "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813, {ARM_HasV7Ops} }, // 26 { "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814, { 0 } }, // 27 { "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888, {ARM_Feature8MSecExt} }, // 28 { "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889, {ARM_Feature8MSecExt} }, // 29 { "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 30 { "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 31 { "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890, { 0 } }, // 32 { "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 33 { "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 34 { "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894, {ARM_Feature8MSecExt} }, // 35 { "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36 }; static const BankedReg BankedRegsList[] = { { "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0 { "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1 { "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2 { "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3 { "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4 { "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5 { "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6 { "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7 { "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8 { "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9 { "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10 { "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11 { "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12 { "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13 { "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14 { "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15 { "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16 { "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17 { "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18 { "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19 { "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20 { "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21 { "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22 { "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23 { "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24 { "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25 { "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26 { "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27 { "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28 { "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29 { "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30 { "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31 { "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32 }; const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x0, 0 }, { 0x1, 2 }, { 0x2, 4 }, { 0x3, 6 }, { 0x100, 8 }, { 0x101, 10 }, { 0x102, 12 }, { 0x103, 14 }, { 0x105, 16 }, { 0x106, 17 }, { 0x107, 18 }, { 0x108, 19 }, { 0x109, 20 }, { 0x10A, 21 }, { 0x10B, 22 }, { 0x110, 23 }, { 0x111, 24 }, { 0x112, 25 }, { 0x113, 26 }, { 0x114, 27 }, { 0x188, 28 }, { 0x189, 29 }, { 0x18A, 30 }, { 0x18B, 31 }, { 0x190, 32 }, { 0x191, 33 }, { 0x193, 34 }, { 0x194, 35 }, { 0x198, 36 }, { 0x200, 9 }, { 0x201, 11 }, { 0x202, 13 }, { 0x203, 15 }, { 0x300, 1 }, { 0x301, 3 }, { 0x302, 5 }, { 0x303, 7 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else return &MClassSysRegsList[Index[i].index]; } const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x400, 0 }, { 0x401, 2 }, { 0x402, 4 }, { 0x403, 6 }, { 0x800, 8 }, { 0x801, 10 }, { 0x802, 12 }, { 0x803, 14 }, { 0x805, 16 }, { 0x806, 17 }, { 0x807, 18 }, { 0x808, 19 }, { 0x809, 20 }, { 0x80A, 21 }, { 0x80B, 22 }, { 0x810, 23 }, { 0x811, 24 }, { 0x812, 25 }, { 0x813, 26 }, { 0x814, 27 }, { 0x888, 28 }, { 0x889, 29 }, { 0x88A, 30 }, { 0x88B, 31 }, { 0x890, 32 }, { 0x891, 33 }, { 0x893, 34 }, { 0x894, 35 }, { 0x898, 36 }, { 0xC00, 1 }, { 0xC01, 3 }, { 0xC02, 5 }, { 0xC03, 7 }, { 0x1800, 9 }, { 0x1801, 11 }, { 0x1802, 13 }, { 0x1803, 15 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else return &MClassSysRegsList[Index[i].index]; } const BankedReg *lookupBankedRegByEncoding(uint8_t encoding) { unsigned int i; static const struct IndexType Index[] = { { 0x0, 0 }, { 0x1, 1 }, { 0x2, 2 }, { 0x3, 3 }, { 0x4, 4 }, { 0x5, 5 }, { 0x6, 6 }, { 0x8, 7 }, { 0x9, 8 }, { 0xA, 9 }, { 0xB, 10 }, { 0xC, 11 }, { 0xD, 12 }, { 0xE, 13 }, { 0x10, 14 }, { 0x11, 15 }, { 0x12, 16 }, { 0x13, 17 }, { 0x14, 18 }, { 0x15, 19 }, { 0x16, 20 }, { 0x17, 21 }, { 0x1C, 22 }, { 0x1D, 23 }, { 0x1E, 24 }, { 0x1F, 25 }, { 0x2E, 26 }, { 0x30, 27 }, { 0x32, 28 }, { 0x34, 29 }, { 0x36, 30 }, { 0x3C, 31 }, { 0x3E, 32 }, }; i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else return &BankedRegsList[Index[i].index]; } capstone-sys-0.15.0/capstone/arch/ARM/ARMInstPrinter.c000064400000000000000000003304050072674642500205310ustar 00000000000000//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an ARM MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_ARM #include // DEBUG #include #include #include #include "ARMInstPrinter.h" #include "ARMAddressingModes.h" #include "ARMBaseInfo.h" #include "ARMDisassembler.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../utils.h" #include "ARMMapping.h" #define GET_SUBTARGETINFO_ENUM #include "ARMGenSubtargetInfo.inc" #include "ARMGenSystemRegister.inc" static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo); // Autogenerated by tblgen. static void printInstruction(MCInst *MI, SStream *O); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0); static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned); static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale); static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O); static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder); static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); #ifndef CAPSTONE_DIET // copy & normalize access info static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index) { const uint8_t *arr = ARM_get_op_access(h, id); if (!arr || arr[index] == CS_AC_IGNORE) return 0; return arr[index]; } #endif static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (status) { #ifndef CAPSTONE_DIET uint8_t access; #endif MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; MI->ac_idx++; #endif } else { // done, create the next operand slot MI->flat_insn->detail->arm.op_count++; } } static void op_addImm(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; MI->flat_insn->detail->arm.op_count++; } } #define GET_INSTRINFO_ENUM #include "ARMGenInstrInfo.inc" static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS); #define PRINT_ALIAS_INSTR #include "ARMGenAsmWriter.inc" #include "ARMGenRegisterName.inc" #include "ARMGenRegisterName_digit.inc" void ARM_getRegName(cs_struct *handle, int value) { if (value == CS_OPT_SYNTAX_NOREGNAME) { handle->get_regname = getRegisterName_digit; handle->reg_name = ARM_reg_name2;; } else { handle->get_regname = getRegisterName; handle->reg_name = ARM_reg_name;; } } /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. /// /// getSORegOffset returns an integer from 0-31, representing '32' as 0. static unsigned translateShiftImm(unsigned imm) { // lsr #32 and asr #32 exist, but should be encoded as a 0. //assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); if (imm == 0) return 32; return imm; } /// Prints the shift value with an immediate value. static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) { if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) return; SStream_concat0(O, ", "); //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); if (MI->csh->detail) { if (MI->csh->doing_mem) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; else MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; } if (ShOpc != ARM_AM_rrx) { SStream_concat0(O, " "); SStream_concat(O, "#%u", translateShiftImm(ShImm)); if (MI->csh->detail) { if (MI->csh->doing_mem) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm); else MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm); } } } static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) { #ifndef CAPSTONE_DIET SStream_concat0(OS, h->get_regname(RegNo)); #endif } // TODO static const name_map insn_update_flgs[] = { { ARM_INS_CMN, "cmn" }, { ARM_INS_CMP, "cmp" }, { ARM_INS_TEQ, "teq" }, { ARM_INS_TST, "tst" }, { ARM_INS_ADC, "adcs" }, { ARM_INS_ADD, "adds" }, { ARM_INS_AND, "ands" }, { ARM_INS_ASR, "asrs" }, { ARM_INS_BIC, "bics" }, { ARM_INS_EOR, "eors" }, { ARM_INS_LSL, "lsls" }, { ARM_INS_LSR, "lsrs" }, { ARM_INS_MLA, "mlas" }, { ARM_INS_MOV, "movs" }, { ARM_INS_MUL, "muls" }, { ARM_INS_MVN, "mvns" }, { ARM_INS_ORN, "orns" }, { ARM_INS_ORR, "orrs" }, { ARM_INS_ROR, "rors" }, { ARM_INS_RRX, "rrxs" }, { ARM_INS_RSB, "rsbs" }, { ARM_INS_RSC, "rscs" }, { ARM_INS_SBC, "sbcs" }, { ARM_INS_SMLAL, "smlals" }, { ARM_INS_SMULL, "smulls" }, { ARM_INS_SUB, "subs" }, { ARM_INS_UMLAL, "umlals" }, { ARM_INS_UMULL, "umulls" }, { ARM_INS_UADD8, "uadd8" }, }; void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { if (((cs_struct *)ud)->detail != CS_OPT_ON) return; // check if this insn requests write-back if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { insn->detail->arm.writeback = true; } else if (mci->csh->mode & CS_MODE_THUMB) { // handle some special instructions with writeback //printf(">> Opcode = %u\n", mci->Opcode); switch(mci->Opcode) { default: break; case ARM_t2LDC2L_PRE: case ARM_t2LDC2_PRE: case ARM_t2LDCL_PRE: case ARM_t2LDC_PRE: case ARM_t2LDRB_PRE: case ARM_t2LDRD_PRE: case ARM_t2LDRH_PRE: case ARM_t2LDRSB_PRE: case ARM_t2LDRSH_PRE: case ARM_t2LDR_PRE: case ARM_t2STC2L_PRE: case ARM_t2STC2_PRE: case ARM_t2STCL_PRE: case ARM_t2STC_PRE: case ARM_t2STRB_PRE: case ARM_t2STRD_PRE: case ARM_t2STRH_PRE: case ARM_t2STR_PRE: case ARM_t2LDC2L_POST: case ARM_t2LDC2_POST: case ARM_t2LDCL_POST: case ARM_t2LDC_POST: case ARM_t2LDRB_POST: case ARM_t2LDRD_POST: case ARM_t2LDRH_POST: case ARM_t2LDRSB_POST: case ARM_t2LDRSH_POST: case ARM_t2LDR_POST: case ARM_t2STC2L_POST: case ARM_t2STC2_POST: case ARM_t2STCL_POST: case ARM_t2STC_POST: case ARM_t2STRB_POST: case ARM_t2STRD_POST: case ARM_t2STRH_POST: case ARM_t2STR_POST: insn->detail->arm.writeback = true; break; } } else { // ARM mode // handle some special instructions with writeback //printf(">> Opcode = %u\n", mci->Opcode); switch(mci->Opcode) { default: break; case ARM_LDC2L_PRE: case ARM_LDC2_PRE: case ARM_LDCL_PRE: case ARM_LDC_PRE: case ARM_LDRD_PRE: case ARM_LDRH_PRE: case ARM_LDRSB_PRE: case ARM_LDRSH_PRE: case ARM_STC2L_PRE: case ARM_STC2_PRE: case ARM_STCL_PRE: case ARM_STC_PRE: case ARM_STRD_PRE: case ARM_STRH_PRE: case ARM_LDC2L_POST: case ARM_LDC2_POST: case ARM_LDCL_POST: case ARM_LDC_POST: case ARM_LDRBT_POST: case ARM_LDRD_POST: case ARM_LDRH_POST: case ARM_LDRSB_POST: case ARM_LDRSH_POST: case ARM_STC2L_POST: case ARM_STC2_POST: case ARM_STCL_POST: case ARM_STC_POST: case ARM_STRBT_POST: case ARM_STRD_POST: case ARM_STRH_POST: case ARM_LDRB_POST_IMM: case ARM_LDR_POST_IMM: case ARM_LDR_POST_REG: case ARM_STRB_POST_IMM: case ARM_STR_POST_IMM: case ARM_STR_POST_REG: insn->detail->arm.writeback = true; break; } } // check if this insn requests update flags if (insn->detail->arm.update_flags == false) { // some insn still update flags, regardless of tabgen info unsigned int i, j; for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { if (insn->id == insn_update_flgs[i].id && !strncmp(insn_asm, insn_update_flgs[i].name, strlen(insn_update_flgs[i].name))) { insn->detail->arm.update_flags = true; // we have to update regs_write array as well for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { if (insn->detail->regs_write[j] == 0) { insn->detail->regs_write[j] = ARM_REG_CPSR; break; } } break; } } } // instruction should not have invalid CC if (insn->detail->arm.cc == ARM_CC_INVALID) { insn->detail->arm.cc = ARM_CC_AL; } // manual fix for some special instructions // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); switch(mci->Opcode) { default: break; case ARM_MOVPCLR: insn->detail->arm.operands[0].type = ARM_OP_REG; insn->detail->arm.operands[0].reg = ARM_REG_PC; insn->detail->arm.operands[0].access = CS_AC_WRITE; insn->detail->arm.operands[1].type = ARM_OP_REG; insn->detail->arm.operands[1].reg = ARM_REG_LR; insn->detail->arm.operands[1].access = CS_AC_READ; insn->detail->arm.op_count = 2; break; } } void ARM_printInst(MCInst *MI, SStream *O, void *Info) { MCRegisterInfo *MRI = (MCRegisterInfo *)Info; unsigned Opcode = MCInst_getOpcode(MI), tmp, i; //printf(">>> Opcode = %u\n", Opcode); switch (Opcode) { // Check for MOVs and print canonical forms, instead. case ARM_MOVsr: { // FIXME: Thumb variants? unsigned int opc; MCOperand *Dst = MCInst_getOperand(MI, 0); MCOperand *MO1 = MCInst_getOperand(MI, 1); MCOperand *MO2 = MCInst_getOperand(MI, 2); MCOperand *MO3 = MCInst_getOperand(MI, 3); opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); switch (opc) { default: break; case ARM_AM_asr: MCInst_setOpcodePub(MI, ARM_INS_ASR); break; case ARM_AM_lsl: MCInst_setOpcodePub(MI, ARM_INS_LSL); break; case ARM_AM_lsr: MCInst_setOpcodePub(MI, ARM_INS_LSR); break; case ARM_AM_ror: MCInst_setOpcodePub(MI, ARM_INS_ROR); break; case ARM_AM_rrx: MCInst_setOpcodePub(MI, ARM_INS_RRX); break; } printSBitModifierOperand(MI, 6, O); printPredicateOperand(MI, 4, O); SStream_concat0(O, "\t"); printRegName(MI->csh, O, MCOperand_getReg(Dst)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } return; } case ARM_MOVsi: { // FIXME: Thumb variants? unsigned int opc; MCOperand *Dst = MCInst_getOperand(MI, 0); MCOperand *MO1 = MCInst_getOperand(MI, 1); MCOperand *MO2 = MCInst_getOperand(MI, 2); opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); SStream_concat0(O, ARM_AM_getShiftOpcStr(opc)); switch(opc) { default: break; case ARM_AM_asr: MCInst_setOpcodePub(MI, ARM_INS_ASR); break; case ARM_AM_lsl: MCInst_setOpcodePub(MI, ARM_INS_LSL); break; case ARM_AM_lsr: MCInst_setOpcodePub(MI, ARM_INS_LSR); break; case ARM_AM_ror: MCInst_setOpcodePub(MI, ARM_INS_ROR); break; case ARM_AM_rrx: MCInst_setOpcodePub(MI, ARM_INS_RRX); break; } printSBitModifierOperand(MI, 5, O); printPredicateOperand(MI, 3, O); SStream_concat0(O, "\t"); printRegName(MI->csh, O, MCOperand_getReg(Dst)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } if (opc == ARM_AM_rrx) { //printAnnotation(O, Annot); return; } SStream_concat0(O, ", "); tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); printUInt32Bang(O, tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)opc; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; } return; } // A8.6.123 PUSH case ARM_STMDB_UPD: case ARM_t2STMDB_UPD: if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && MCInst_getNumOperands(MI) > 5) { // Should only print PUSH if there are at least two registers in the list. SStream_concat0(O, "push"); MCInst_setOpcodePub(MI, ARM_INS_PUSH); printPredicateOperand(MI, 2, O); if (Opcode == ARM_t2STMDB_UPD) SStream_concat0(O, ".w"); SStream_concat0(O, "\t"); if (MI->csh->detail) { MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; MI->flat_insn->detail->regs_read_count++; MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; MI->flat_insn->detail->regs_write_count++; } printRegisterList(MI, 4, O); return; } else break; case ARM_STR_PRE_IMM: if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { SStream_concat0(O, "push"); MCInst_setOpcodePub(MI, ARM_INS_PUSH); printPredicateOperand(MI, 4, O); SStream_concat0(O, "\t{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; #endif MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); return; } else break; // A8.6.122 POP case ARM_LDMIA_UPD: case ARM_t2LDMIA_UPD: if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && MCInst_getNumOperands(MI) > 5) { // Should only print POP if there are at least two registers in the list. SStream_concat0(O, "pop"); MCInst_setOpcodePub(MI, ARM_INS_POP); printPredicateOperand(MI, 2, O); if (Opcode == ARM_t2LDMIA_UPD) SStream_concat0(O, ".w"); SStream_concat0(O, "\t"); // unlike LDM, POP only write to registers, so skip the 1st access code MI->ac_idx = 1; if (MI->csh->detail) { MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; MI->flat_insn->detail->regs_read_count++; MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; MI->flat_insn->detail->regs_write_count++; } printRegisterList(MI, 4, O); return; } break; case ARM_LDR_POST_IMM: if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { MCOperand *MO2 = MCInst_getOperand(MI, 4); if (getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) { SStream_concat0(O, "pop"); MCInst_setOpcodePub(MI, ARM_INS_POP); printPredicateOperand(MI, 5, O); SStream_concat0(O, "\t{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE; MI->flat_insn->detail->arm.op_count++; // this instruction implicitly read/write SP register MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; MI->flat_insn->detail->regs_read_count++; MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; MI->flat_insn->detail->regs_write_count++; } SStream_concat0(O, "}"); return; } } break; // A8.6.355 VPUSH case ARM_VSTMSDB_UPD: case ARM_VSTMDDB_UPD: if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { SStream_concat0(O, "vpush"); MCInst_setOpcodePub(MI, ARM_INS_VPUSH); printPredicateOperand(MI, 2, O); SStream_concat0(O, "\t"); printRegisterList(MI, 4, O); return; } break; // A8.6.354 VPOP case ARM_VLDMSIA_UPD: case ARM_VLDMDIA_UPD: if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { SStream_concat0(O, "vpop"); MCInst_setOpcodePub(MI, ARM_INS_VPOP); printPredicateOperand(MI, 2, O); SStream_concat0(O, "\t"); printRegisterList(MI, 4, O); return; } break; case ARM_tLDMIA: { bool Writeback = true; unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); unsigned i; for (i = 3; i < MCInst_getNumOperands(MI); ++i) { if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) Writeback = false; } SStream_concat0(O, "ldm"); MCInst_setOpcodePub(MI, ARM_INS_LDM); printPredicateOperand(MI, 1, O); SStream_concat0(O, "\t"); printRegName(MI->csh, O, BaseReg); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE; MI->flat_insn->detail->arm.op_count++; } if (Writeback) { MI->writeback = true; SStream_concat0(O, "!"); } SStream_concat0(O, ", "); printRegisterList(MI, 3, O); return; } // Combine 2 GPRs from disassember into a GPRPair to match with instr def. // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, // a single GPRPair reg operand is used in the .td file to replace the two // GPRs. However, when decoding them, the two GRPs cannot be automatically // expressed as a GPRPair, so we have to manually merge them. // FIXME: We would really like to be able to tablegen'erate this. case ARM_LDREXD: case ARM_STREXD: case ARM_LDAEXD: case ARM_STLEXD: { const MCRegisterClass *MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); if (MCRegisterClass_contains(MRC, Reg)) { MCInst NewMI; MCInst_Init(&NewMI); MCInst_setOpcode(&NewMI, Opcode); if (isStore) MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); // Copy the rest operands into NewMI. for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); printInstruction(&NewMI, O); return; } break; } case ARM_TSB: case ARM_t2TSB: SStream_concat0(O, "tsb\tcsync"); MCInst_setOpcodePub(MI, ARM_INS_TSB); // TODO: add csync to operands[]? return; } MI->MRI = MRI; if (!printAliasInstr(MI, O)) { printInstruction(MI, O); } } static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { int32_t imm; MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { unsigned Reg = MCOperand_getReg(Op); printRegName(MI->csh, O, Reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg; else MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg; } else { #ifndef CAPSTONE_DIET uint8_t access; #endif MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; MI->ac_idx++; #endif MI->flat_insn->detail->arm.op_count++; } } } else if (MCOperand_isImm(Op)) { unsigned int opc = MCInst_getOpcode(MI); imm = (int32_t)MCOperand_getImm(Op); // relative branch only has relative offset, so we have to update it // to reflect absolute address. // Note: in ARM, PC is always 2 instructions ahead, so we have to // add 8 in ARM mode, or 4 in Thumb mode // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); if (ARM_rel_branch(MI->csh, opc)) { uint32_t address; // only do this for relative branch if (MI->csh->mode & CS_MODE_THUMB) { address = (uint32_t)MI->address + 4; if (ARM_blx_to_arm_mode(MI->csh, opc)) { // here need to align down to the nearest 4-byte address #define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width) address = _ALIGN_DOWN(address, 4); #undef _ALIGN_DOWN } } else { address = (uint32_t)MI->address + 8; } imm += address; printUInt32Bang(O, imm); } else { switch(MI->flat_insn->id) { default: if (MI->csh->imm_unsigned) printUInt32Bang(O, imm); else printInt32Bang(O, imm); break; case ARM_INS_AND: case ARM_INS_ORR: case ARM_INS_EOR: case ARM_INS_BIC: case ARM_INS_MVN: // do not print number in negative form printUInt32Bang(O, imm); break; } } if (MI->csh->detail) { if (MI->csh->doing_mem) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm; else { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; MI->flat_insn->detail->arm.op_count++; } } } } static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); int32_t OffImm; bool isSub; SStream_concat0(O, "[pc, "); OffImm = (int32_t)MCOperand_getImm(MO1); isSub = OffImm < 0; // Special value for #-0. All others are normal. if (OffImm == INT32_MIN) OffImm = 0; if (isSub) { SStream_concat(O, "#-0x%x", -OffImm); } else { printUInt32Bang(O, OffImm); } SStream_concat0(O, "]"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } } // so_reg is a 4-operand unit corresponding to register forms of the A5.1 // "Addressing Mode 1 - Data-processing operands" forms. This includes: // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2); ARM_AM_ShiftOpc ShOpc; printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; MI->flat_insn->detail->arm.op_count++; } // Print the shift opc. ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); SStream_concat0(O, ", "); SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); if (ShOpc == ARM_AM_rrx) return; SStream_concat0(O, " "); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2); } static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } // Print the shift opc. printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), getSORegOffset((unsigned int)MCOperand_getImm(MO2))); } //===--------------------------------------------------------------------===// // Addressing Mode #2 //===--------------------------------------------------------------------===// static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); unsigned int imm3 = (unsigned int)MCOperand_getImm(MO3); ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); } if (!MCOperand_getReg(MO2)) { unsigned tmp = getAM2Offset(imm3); if (tmp) { // Don't print +0. subtracted = getAM2Op(imm3); SStream_concat0(O, ", "); if (tmp > HEX_THRESHOLD) SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); else SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op(imm3); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; } } SStream_concat0(O, "]"); set_mem_access(MI, false); return; } SStream_concat0(O, ", "); SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; } printRegImmShift(MI, O, getAM2ShiftOpc(imm3), getAM2Offset(imm3)); SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); SStream_concat0(O, ", lsl #1]"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1; } set_mem_access(MI, false); } static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, Op); if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, Op, O); return; } //#ifndef NDEBUG // const MCOperand &MO3 = MI->getOperand(Op + 2); // unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); // assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op"); //#endif printAM2PreOrOffsetIndexOp(MI, Op, O); } static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); if (!MCOperand_getReg(MO1)) { unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); if (ImmOffs > HEX_THRESHOLD) SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); else SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; MI->flat_insn->detail->arm.op_count++; } return; } SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; MI->flat_insn->detail->arm.op_count++; } printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), getAM2Offset((unsigned int)MCOperand_getImm(MO2))); } //===--------------------------------------------------------------------===// // Addressing Mode #3 //===--------------------------------------------------------------------===// static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op+1); MCOperand *MO3 = MCInst_getOperand(MI, Op+2); ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); unsigned ImmOffs; SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); if (MCOperand_getReg(MO2)) { SStream_concat0(O, ", "); SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); if (sign == ARM_AM_sub) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; } } SStream_concat0(O, "]"); set_mem_access(MI, false); return; } // If the op is sub we have to print the immediate even if it is 0 ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { if (ImmOffs > HEX_THRESHOLD) SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); else SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); } if (MI->csh->detail) { if (sign == ARM_AM_sub) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; } else MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs; } SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, Op); if (!MCOperand_isReg(MO1)) { // For label symbolic references. printOperand(MI, Op, O); return; } printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); } static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); unsigned ImmOffs; if (MCOperand_getReg(MO1)) { SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; MI->flat_insn->detail->arm.op_count++; } return; } ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); if (ImmOffs > HEX_THRESHOLD) SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); else SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; MI->flat_insn->detail->arm.op_count++; } } static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); unsigned Imm = (unsigned int)MCOperand_getImm(MO); if ((Imm & 0xff) > HEX_THRESHOLD) SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); else SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff; MI->flat_insn->detail->arm.op_count++; } } static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } } static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); int Imm = (int)MCOperand_getImm(MO); if (((Imm & 0xff) << 2) > HEX_THRESHOLD) { SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); } else { SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); } if (MI->csh->detail) { int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; MI->flat_insn->detail->arm.op_count++; } } static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0) { unsigned ImmOffs; MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); ARM_AM_AddrOpc Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, OpNum, O); return; } SStream_concat0(O, "["); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; } ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { if (ImmOffs * 4 > HEX_THRESHOLD) SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 4); else SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 4); if (MI->csh->detail) { if (Op) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4; else MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4; } } SStream_concat0(O, "]"); if (MI->csh->detail) { MI->flat_insn->detail->arm.op_count++; } } static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); unsigned ImmOffs = getAM5FP16Offset((unsigned)MCOperand_getImm(MO2)); unsigned Op = getAM5FP16Op((unsigned)MCOperand_getImm(MO2)); if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, OpNum, O); return; } SStream_concat0(O, "["); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; } if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) { if (ImmOffs * 2 > HEX_THRESHOLD) SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); else SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2); if (MI->csh->detail) { if (Op) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 2; else MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 2; } } SStream_concat0(O, "]"); if (MI->csh->detail) { MI->flat_insn->detail->arm.op_count++; } } static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); unsigned tmp; SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); tmp = (unsigned int)MCOperand_getImm(MO2); if (tmp) { if (tmp << 3 > HEX_THRESHOLD) SStream_concat(O, ":0x%x", (tmp << 3)); else SStream_concat(O, ":%u", (tmp << 3)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3; } SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_getReg(MO) == 0) { MI->writeback = true; SStream_concat0(O, "!"); } else { SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO); MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } } } static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); uint32_t v = ~(uint32_t)MCOperand_getImm(MO); int32_t lsb = CountTrailingZeros_32(v); int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); printUInt32Bang(O, lsb); if (width > HEX_THRESHOLD) SStream_concat(O, ", #0x%x", width); else SStream_concat(O, ", #%u", width); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb; MI->flat_insn->detail->arm.op_count++; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width; MI->flat_insn->detail->arm.op_count++; } } static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) { unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, ARM_MB_MemBOptToString(val, ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops))); if (MI->csh->detail) { MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); } } static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) { unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); } static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) { unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val)); // TODO: add to detail? } static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); bool isASR = (ShiftOp & (1 << 5)) != 0; unsigned Amt = ShiftOp & 0x1f; if (isASR) { unsigned tmp = Amt == 0 ? 32 : Amt; if (tmp > HEX_THRESHOLD) SStream_concat(O, ", asr #0x%x", tmp); else SStream_concat(O, ", asr #%u", tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; } } else if (Amt) { if (Amt > HEX_THRESHOLD) SStream_concat(O, ", lsl #0x%x", Amt); else SStream_concat(O, ", lsl #%u", Amt); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt; } } } static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (Imm == 0) return; //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); if (Imm > HEX_THRESHOLD) SStream_concat(O, ", lsl #0x%x", Imm); else SStream_concat(O, ", lsl #%u", Imm); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; } } static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // A shift amount of 32 is encoded as 0. if (Imm == 0) Imm = 32; //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); if (Imm > HEX_THRESHOLD) SStream_concat(O, ", asr #0x%x", Imm); else SStream_concat(O, ", asr #%u", Imm); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; } } // FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) { unsigned i, e; #ifndef CAPSTONE_DIET uint8_t access = 0; #endif SStream_concat0(O, "{"); #ifndef CAPSTONE_DIET if (MI->csh->detail) { access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); } #endif for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { if (i != OpNum) SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET if (MI->csh->detail) { MI->ac_idx++; } #endif } static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0); MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1)); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1); MI->flat_insn->detail->arm.op_count++; } } // SETEND BE/LE static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); if (MCOperand_getImm(Op)) { SStream_concat0(O, "be"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE; MI->flat_insn->detail->arm.op_count++; } } else { SStream_concat0(O, "le"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE; MI->flat_insn->detail->arm.op_count++; } } } static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); unsigned int mode = (unsigned int)MCOperand_getImm(Op); SStream_concat0(O, ARM_PROC_IModToString(mode)); if (MI->csh->detail) { MI->flat_insn->detail->arm.cps_mode = mode; } } static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); unsigned IFlags = (unsigned int)MCOperand_getImm(Op); int i; for (i = 2; i >= 0; --i) if (IFlags & (1 << i)) { SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); } if (IFlags == 0) { SStream_concat0(O, "none"); IFlags = ARM_CPSFLAG_NONE; } if (MI->csh->detail) { MI->flat_insn->detail->arm.cps_flag = IFlags; } } static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf; unsigned reg; if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { const MClassSysReg *TheReg; unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm unsigned Opcode = MCInst_getOpcode(MI); if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) { TheReg = lookupMClassSysRegBy12bitSYSmValue(SYSm); if (TheReg && MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) { SStream_concat0(O, TheReg->Name); ARM_addSysReg(MI, TheReg->sysreg); return; } } // Handle the basic 8-bit mask. SYSm &= 0xff; if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) { // ARMv7-M deprecates using MSR APSR without a _ qualifier as an // alias for MSR APSR_nzcvq. TheReg = lookupMClassSysRegAPSRNonDeprecated(SYSm); if (TheReg) { SStream_concat0(O, TheReg->Name); ARM_addSysReg(MI, TheReg->sysreg); return; } } TheReg = lookupMClassSysRegBy8bitSYSmValue(SYSm); if (TheReg) { SStream_concat0(O, TheReg->Name); ARM_addSysReg(MI, TheReg->sysreg); return; } if (SYSm > HEX_THRESHOLD) SStream_concat(O, "%x", SYSm); else SStream_concat(O, "%u", SYSm); if (MI->csh->detail) MCOperand_CreateImm0(MI, SYSm); return; } // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { SStream_concat0(O, "apsr_"); switch (Mask) { default: // llvm_unreachable("Unexpected mask value!"); case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; } } if (SpecRegRBit) { SStream_concat0(O, "spsr"); } else { SStream_concat0(O, "cpsr"); } reg = 0; if (Mask) { SStream_concat0(O, "_"); if (Mask & 8) { SStream_concat0(O, "f"); reg += ARM_SYSREG_SPSR_F; } if (Mask & 4) { SStream_concat0(O, "s"); reg += ARM_SYSREG_SPSR_S; } if (Mask & 2) { SStream_concat0(O, "x"); reg += ARM_SYSREG_SPSR_X; } if (Mask & 1) { SStream_concat0(O, "c"); reg += ARM_SYSREG_SPSR_C; } ARM_addSysReg(MI, reg); } } static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); const BankedReg *TheReg = lookupBankedRegByEncoding(Banked); SStream_concat0(O, TheReg->Name); ARM_addSysReg(MI, TheReg->sysreg); } static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // Handle the undefined 15 CC value here for printing so we don't abort(). if ((unsigned)CC == 15) { SStream_concat0(O, ""); if (MI->csh->detail) MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; } else { if (CC != ARMCC_AL) { SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); } if (MI->csh->detail) MI->flat_insn->detail->arm.cc = CC + 1; } } static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); if (MI->csh->detail) MI->flat_insn->detail->arm.cc = CC + 1; } static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) { if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && // "Expect ARM CPSR register!"); SStream_concat0(O, "s"); if (MI->csh->detail) MI->flat_insn->detail->arm.update_flags = true; } } static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printUInt32(O, tmp); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->arm.op_count--; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp; MI->ac_idx--; // consecutive operands share the same access right } else { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } } static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) { unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat(O, "p%u", imm); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; MI->flat_insn->detail->arm.op_count++; } } static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) { unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat(O, "c%u", imm); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; MI->flat_insn->detail->arm.op_count++; } } static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (tmp > HEX_THRESHOLD) SStream_concat(O, "{0x%x}", tmp); else SStream_concat(O, "{%u}", tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale) { MCOperand *MO = MCInst_getOperand(MI, OpNum); int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; if (OffImm == INT32_MIN) { SStream_concat0(O, "#-0"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; MI->flat_insn->detail->arm.op_count++; } } else { if (OffImm < 0) SStream_concat(O, "#-0x%x", -OffImm); else { if (OffImm > HEX_THRESHOLD) SStream_concat(O, "#0x%x", OffImm); else SStream_concat(O, "#%u", OffImm); } if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; MI->flat_insn->detail->arm.op_count++; } } } static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; printUInt32Bang(O, tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned tmp = Imm == 0 ? 32 : Imm; printUInt32Bang(O, tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum - 1)); unsigned CondBit0 = Firstcond & 1; unsigned NumTZ = CountTrailingZeros_32(Mask); //assert(NumTZ <= 3 && "Invalid IT mask!"); unsigned Pos, e; for (Pos = 3, e = NumTZ; Pos > e; --Pos) { bool T = ((Mask >> Pos) & 1) == CondBit0; if (T) SStream_concat0(O, "t"); else SStream_concat0(O, "e"); // TODO: detail for this t/e } } static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); unsigned RegNum; if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, Op, O); return; } SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); RegNum = MCOperand_getReg(MO2); if (RegNum) { SStream_concat0(O, ", "); printRegName(MI->csh, O, RegNum); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum; } SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, unsigned Scale) { MCOperand *MO1 = MCInst_getOperand(MI, Op); MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); unsigned ImmOffs, tmp; if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, Op, O); return; } SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); ImmOffs = (unsigned int)MCOperand_getImm(MO2); if (ImmOffs) { tmp = ImmOffs * Scale; SStream_concat0(O, ", "); printUInt32Bang(O, tmp); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; } SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) { printThumbAddrModeImm5SOperand(MI, Op, O, 1); } static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) { printThumbAddrModeImm5SOperand(MI, Op, O, 2); } static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) { printThumbAddrModeImm5SOperand(MI, Op, O, 4); } static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) { printThumbAddrModeImm5SOperand(MI, Op, O, 4); } // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); unsigned Reg = MCOperand_getReg(MO1); printRegName(MI->csh, O, Reg); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ; MI->flat_insn->detail->arm.op_count++; } // Print the shift opc. //assert(MO2.isImm() && "Not a valid t2_so_reg value!"); printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), getSORegOffset((unsigned int)MCOperand_getImm(MO2))); } static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); int32_t OffImm; bool isSub; if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, OpNum, O); return; } SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); OffImm = (int32_t)MCOperand_getImm(MO2); isSub = OffImm < 0; // Special value for #-0. All others are normal. if (OffImm == INT32_MIN) OffImm = 0; if (isSub) { if (OffImm < -HEX_THRESHOLD) SStream_concat(O, ", #-0x%x", -OffImm); else SStream_concat(O, ", #-%u", -OffImm); } else if (AlwaysPrintImm0 || OffImm > 0) { if (OffImm >= 0) { if (OffImm > HEX_THRESHOLD) SStream_concat(O, ", #0x%x", OffImm); else SStream_concat(O, ", #%u", OffImm); } else { if (OffImm < -HEX_THRESHOLD) SStream_concat(O, ", #-0x%x", -OffImm); else SStream_concat(O, ", #-%u", -OffImm); } } if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); int32_t OffImm; bool isSub; SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); OffImm = (int32_t)MCOperand_getImm(MO2); isSub = OffImm < 0; // Don't print +0. if (OffImm == INT32_MIN) OffImm = 0; if (isSub) SStream_concat(O, ", #-0x%x", -OffImm); else if (AlwaysPrintImm0 || OffImm > 0) { if (OffImm > HEX_THRESHOLD) SStream_concat(O, ", #0x%x", OffImm); else SStream_concat(O, ", #%u", OffImm); } if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); int32_t OffImm; bool isSub; if (!MCOperand_isReg(MO1)) { // For label symbolic references. printOperand(MI, OpNum, O); return; } SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); OffImm = (int32_t)MCOperand_getImm(MO2); isSub = OffImm < 0; //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); // Don't print +0. if (OffImm == INT32_MIN) OffImm = 0; if (isSub) { SStream_concat(O, ", #-0x%x", -OffImm); } else if (AlwaysPrintImm0 || OffImm > 0) { if (OffImm > HEX_THRESHOLD) SStream_concat(O, ", #0x%x", OffImm); else SStream_concat(O, ", #%u", OffImm); } if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1); unsigned tmp; SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); if (MCOperand_getImm(MO2)) { SStream_concat0(O, ", "); tmp = (unsigned int)MCOperand_getImm(MO2) * 4; printUInt32Bang(O, tmp); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; } SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); int32_t OffImm = (int32_t)MCOperand_getImm(MO1); SStream_concat0(O, ", "); if (OffImm == INT32_MIN) { SStream_concat0(O, "#-0"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; MI->flat_insn->detail->arm.op_count++; } } else { printInt32Bang(O, OffImm); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; MI->flat_insn->detail->arm.op_count++; } } } static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); int32_t OffImm = (int32_t)MCOperand_getImm(MO1); //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); SStream_concat0(O, ", "); if (OffImm == INT32_MIN) { SStream_concat0(O, "#-0"); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; MI->flat_insn->detail->arm.op_count++; } } else { printInt32Bang(O, OffImm); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; MI->flat_insn->detail->arm.op_count++; } } } static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); unsigned ShAmt; SStream_concat0(O, "["); set_mem_access(MI, true); printRegName(MI->csh, O, MCOperand_getReg(MO1)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!"); SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MO2)); if (MI->csh->detail) MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); ShAmt = (unsigned int)MCOperand_getImm(MO3); if (ShAmt) { //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); SStream_concat0(O, ", lsl "); SStream_concat(O, "#%u", ShAmt); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt; } } SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point SStream_concat(O, "#"); #else SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); #endif if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); MI->flat_insn->detail->arm.op_count++; } } static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned EltBits; uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); if (Val > HEX_THRESHOLD) SStream_concat(O, "#0x%"PRIx64, Val); else SStream_concat(O, "#%"PRIu64, Val); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val; MI->flat_insn->detail->arm.op_count++; } } static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printUInt32Bang(O, Imm + 1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1; MI->flat_insn->detail->arm.op_count++; } } static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (Imm == 0) return; SStream_concat0(O, ", ror #"); switch (Imm) { default: //assert (0 && "illegal ror immediate!"); case 1: SStream_concat0(O, "8"); break; case 2: SStream_concat0(O, "16"); break; case 3: SStream_concat0(O, "24"); break; } if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8; } } static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); unsigned Bits = MCOperand_getImm(Op) & 0xFF; unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; int32_t Rotated; bool PrintUnsigned = false; switch (MCInst_getOpcode(MI)) { case ARM_MOVi: // Movs to PC should be treated unsigned PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC); break; case ARM_MSRi: // Movs to special registers should be treated unsigned PrintUnsigned = true; break; } Rotated = rotr32(Bits, Rot); if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) { // #rot has the least possible value if (PrintUnsigned) { if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD) SStream_concat(O, "#0x%x", Rotated); else SStream_concat(O, "#%u", Rotated); } else if (Rotated >= 0) { if (Rotated > HEX_THRESHOLD) SStream_concat(O, "#0x%x", Rotated); else SStream_concat(O, "#%u", Rotated); } else { SStream_concat(O, "#0x%x", Rotated); } if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated; MI->flat_insn->detail->arm.op_count++; } return; } // Explicit #bits, #rot implied SStream_concat(O, "#%u, #%u", Bits, Rot); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits; MI->flat_insn->detail->arm.op_count++; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot; MI->flat_insn->detail->arm.op_count++; } } static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp; tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printUInt32Bang(O, tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp; tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printUInt32Bang(O, tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) { unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); if (tmp > HEX_THRESHOLD) SStream_concat(O, "[0x%x]", tmp); else SStream_concat(O, "[%u]", tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp; } } static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) { SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } SStream_concat0(O, "}"); } static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; #endif unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif SStream_concat0(O, "{"); printRegName(MI->csh, O, Reg0); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, Reg1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; #endif unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif SStream_concat0(O, "{"); printRegName(MI->csh, O, Reg0); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, Reg1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; #endif unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif SStream_concat0(O, "{"); printRegName(MI->csh, O, Reg0); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, Reg1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; #endif unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); #ifndef CAPSTONE_DIET access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif SStream_concat0(O, "{"); printRegName(MI->csh, O, Reg0); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, Reg1); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[], "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "[]}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) { #ifndef CAPSTONE_DIET uint8_t access; access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); #endif // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. SStream_concat0(O, "{"); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, ", "); printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; #ifndef CAPSTONE_DIET MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access; #endif MI->flat_insn->detail->arm.op_count++; } SStream_concat0(O, "}"); #ifndef CAPSTONE_DIET MI->ac_idx++; #endif } static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); unsigned tmp = (unsigned)((Val * Angle) + Remainder); printUInt32Bang(O, tmp); if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; MI->flat_insn->detail->arm.op_count++; } } void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) { if (MI->csh->detail) { MI->flat_insn->detail->arm.vector_data = vd; } } void ARM_addVectorDataSize(MCInst *MI, int size) { if (MI->csh->detail) { MI->flat_insn->detail->arm.vector_size = size; } } void ARM_addReg(MCInst *MI, int reg) { if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; MI->flat_insn->detail->arm.op_count++; } } void ARM_addUserMode(MCInst *MI) { if (MI->csh->detail) { MI->flat_insn->detail->arm.usermode = true; } } void ARM_addSysReg(MCInst *MI, arm_sysreg reg) { if (MI->csh->detail) { MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG; MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; MI->flat_insn->detail->arm.op_count++; } } #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMInstPrinter.h000064400000000000000000000024110072674642500205270ustar 00000000000000//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an ARM MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_ARMINSTPRINTER_H #define CS_ARMINSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void ARM_printInst(MCInst *MI, SStream *O, void *Info); void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci); // setup handle->get_regname void ARM_getRegName(cs_struct *handle, int value); // specify vector data type for vector instructions void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd); void ARM_addVectorDataSize(MCInst *MI, int size); void ARM_addReg(MCInst *MI, int reg); // load usermode registers (LDM, STM) void ARM_addUserMode(MCInst *MI); // sysreg for MRS/MSR void ARM_addSysReg(MCInst *MI, arm_sysreg reg); #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMMapping.c000064400000000000000000000306760072674642500176520ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_ARM #include // debug #include #include "../../cs_priv.h" #include "ARMMapping.h" #define GET_INSTRINFO_ENUM #include "ARMGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { { ARM_REG_INVALID, NULL }, { ARM_REG_APSR, "apsr"}, { ARM_REG_APSR_NZCV, "apsr_nzcv"}, { ARM_REG_CPSR, "cpsr"}, { ARM_REG_FPEXC, "fpexc"}, { ARM_REG_FPINST, "fpinst"}, { ARM_REG_FPSCR, "fpscr"}, { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, { ARM_REG_FPSID, "fpsid"}, { ARM_REG_ITSTATE, "itstate"}, { ARM_REG_LR, "lr"}, { ARM_REG_PC, "pc"}, { ARM_REG_SP, "sp"}, { ARM_REG_SPSR, "spsr"}, { ARM_REG_D0, "d0"}, { ARM_REG_D1, "d1"}, { ARM_REG_D2, "d2"}, { ARM_REG_D3, "d3"}, { ARM_REG_D4, "d4"}, { ARM_REG_D5, "d5"}, { ARM_REG_D6, "d6"}, { ARM_REG_D7, "d7"}, { ARM_REG_D8, "d8"}, { ARM_REG_D9, "d9"}, { ARM_REG_D10, "d10"}, { ARM_REG_D11, "d11"}, { ARM_REG_D12, "d12"}, { ARM_REG_D13, "d13"}, { ARM_REG_D14, "d14"}, { ARM_REG_D15, "d15"}, { ARM_REG_D16, "d16"}, { ARM_REG_D17, "d17"}, { ARM_REG_D18, "d18"}, { ARM_REG_D19, "d19"}, { ARM_REG_D20, "d20"}, { ARM_REG_D21, "d21"}, { ARM_REG_D22, "d22"}, { ARM_REG_D23, "d23"}, { ARM_REG_D24, "d24"}, { ARM_REG_D25, "d25"}, { ARM_REG_D26, "d26"}, { ARM_REG_D27, "d27"}, { ARM_REG_D28, "d28"}, { ARM_REG_D29, "d29"}, { ARM_REG_D30, "d30"}, { ARM_REG_D31, "d31"}, { ARM_REG_FPINST2, "fpinst2"}, { ARM_REG_MVFR0, "mvfr0"}, { ARM_REG_MVFR1, "mvfr1"}, { ARM_REG_MVFR2, "mvfr2"}, { ARM_REG_Q0, "q0"}, { ARM_REG_Q1, "q1"}, { ARM_REG_Q2, "q2"}, { ARM_REG_Q3, "q3"}, { ARM_REG_Q4, "q4"}, { ARM_REG_Q5, "q5"}, { ARM_REG_Q6, "q6"}, { ARM_REG_Q7, "q7"}, { ARM_REG_Q8, "q8"}, { ARM_REG_Q9, "q9"}, { ARM_REG_Q10, "q10"}, { ARM_REG_Q11, "q11"}, { ARM_REG_Q12, "q12"}, { ARM_REG_Q13, "q13"}, { ARM_REG_Q14, "q14"}, { ARM_REG_Q15, "q15"}, { ARM_REG_R0, "r0"}, { ARM_REG_R1, "r1"}, { ARM_REG_R2, "r2"}, { ARM_REG_R3, "r3"}, { ARM_REG_R4, "r4"}, { ARM_REG_R5, "r5"}, { ARM_REG_R6, "r6"}, { ARM_REG_R7, "r7"}, { ARM_REG_R8, "r8"}, { ARM_REG_R9, "sb"}, { ARM_REG_R10, "sl"}, { ARM_REG_R11, "fp"}, { ARM_REG_R12, "ip"}, { ARM_REG_S0, "s0"}, { ARM_REG_S1, "s1"}, { ARM_REG_S2, "s2"}, { ARM_REG_S3, "s3"}, { ARM_REG_S4, "s4"}, { ARM_REG_S5, "s5"}, { ARM_REG_S6, "s6"}, { ARM_REG_S7, "s7"}, { ARM_REG_S8, "s8"}, { ARM_REG_S9, "s9"}, { ARM_REG_S10, "s10"}, { ARM_REG_S11, "s11"}, { ARM_REG_S12, "s12"}, { ARM_REG_S13, "s13"}, { ARM_REG_S14, "s14"}, { ARM_REG_S15, "s15"}, { ARM_REG_S16, "s16"}, { ARM_REG_S17, "s17"}, { ARM_REG_S18, "s18"}, { ARM_REG_S19, "s19"}, { ARM_REG_S20, "s20"}, { ARM_REG_S21, "s21"}, { ARM_REG_S22, "s22"}, { ARM_REG_S23, "s23"}, { ARM_REG_S24, "s24"}, { ARM_REG_S25, "s25"}, { ARM_REG_S26, "s26"}, { ARM_REG_S27, "s27"}, { ARM_REG_S28, "s28"}, { ARM_REG_S29, "s29"}, { ARM_REG_S30, "s30"}, { ARM_REG_S31, "s31"}, }; static const name_map reg_name_maps2[] = { { ARM_REG_INVALID, NULL }, { ARM_REG_APSR, "apsr"}, { ARM_REG_APSR_NZCV, "apsr_nzcv"}, { ARM_REG_CPSR, "cpsr"}, { ARM_REG_FPEXC, "fpexc"}, { ARM_REG_FPINST, "fpinst"}, { ARM_REG_FPSCR, "fpscr"}, { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, { ARM_REG_FPSID, "fpsid"}, { ARM_REG_ITSTATE, "itstate"}, { ARM_REG_LR, "lr"}, { ARM_REG_PC, "pc"}, { ARM_REG_SP, "sp"}, { ARM_REG_SPSR, "spsr"}, { ARM_REG_D0, "d0"}, { ARM_REG_D1, "d1"}, { ARM_REG_D2, "d2"}, { ARM_REG_D3, "d3"}, { ARM_REG_D4, "d4"}, { ARM_REG_D5, "d5"}, { ARM_REG_D6, "d6"}, { ARM_REG_D7, "d7"}, { ARM_REG_D8, "d8"}, { ARM_REG_D9, "d9"}, { ARM_REG_D10, "d10"}, { ARM_REG_D11, "d11"}, { ARM_REG_D12, "d12"}, { ARM_REG_D13, "d13"}, { ARM_REG_D14, "d14"}, { ARM_REG_D15, "d15"}, { ARM_REG_D16, "d16"}, { ARM_REG_D17, "d17"}, { ARM_REG_D18, "d18"}, { ARM_REG_D19, "d19"}, { ARM_REG_D20, "d20"}, { ARM_REG_D21, "d21"}, { ARM_REG_D22, "d22"}, { ARM_REG_D23, "d23"}, { ARM_REG_D24, "d24"}, { ARM_REG_D25, "d25"}, { ARM_REG_D26, "d26"}, { ARM_REG_D27, "d27"}, { ARM_REG_D28, "d28"}, { ARM_REG_D29, "d29"}, { ARM_REG_D30, "d30"}, { ARM_REG_D31, "d31"}, { ARM_REG_FPINST2, "fpinst2"}, { ARM_REG_MVFR0, "mvfr0"}, { ARM_REG_MVFR1, "mvfr1"}, { ARM_REG_MVFR2, "mvfr2"}, { ARM_REG_Q0, "q0"}, { ARM_REG_Q1, "q1"}, { ARM_REG_Q2, "q2"}, { ARM_REG_Q3, "q3"}, { ARM_REG_Q4, "q4"}, { ARM_REG_Q5, "q5"}, { ARM_REG_Q6, "q6"}, { ARM_REG_Q7, "q7"}, { ARM_REG_Q8, "q8"}, { ARM_REG_Q9, "q9"}, { ARM_REG_Q10, "q10"}, { ARM_REG_Q11, "q11"}, { ARM_REG_Q12, "q12"}, { ARM_REG_Q13, "q13"}, { ARM_REG_Q14, "q14"}, { ARM_REG_Q15, "q15"}, { ARM_REG_R0, "r0"}, { ARM_REG_R1, "r1"}, { ARM_REG_R2, "r2"}, { ARM_REG_R3, "r3"}, { ARM_REG_R4, "r4"}, { ARM_REG_R5, "r5"}, { ARM_REG_R6, "r6"}, { ARM_REG_R7, "r7"}, { ARM_REG_R8, "r8"}, { ARM_REG_R9, "r9"}, { ARM_REG_R10, "r10"}, { ARM_REG_R11, "r11"}, { ARM_REG_R12, "r12"}, { ARM_REG_S0, "s0"}, { ARM_REG_S1, "s1"}, { ARM_REG_S2, "s2"}, { ARM_REG_S3, "s3"}, { ARM_REG_S4, "s4"}, { ARM_REG_S5, "s5"}, { ARM_REG_S6, "s6"}, { ARM_REG_S7, "s7"}, { ARM_REG_S8, "s8"}, { ARM_REG_S9, "s9"}, { ARM_REG_S10, "s10"}, { ARM_REG_S11, "s11"}, { ARM_REG_S12, "s12"}, { ARM_REG_S13, "s13"}, { ARM_REG_S14, "s14"}, { ARM_REG_S15, "s15"}, { ARM_REG_S16, "s16"}, { ARM_REG_S17, "s17"}, { ARM_REG_S18, "s18"}, { ARM_REG_S19, "s19"}, { ARM_REG_S20, "s20"}, { ARM_REG_S21, "s21"}, { ARM_REG_S22, "s22"}, { ARM_REG_S23, "s23"}, { ARM_REG_S24, "s24"}, { ARM_REG_S25, "s25"}, { ARM_REG_S26, "s26"}, { ARM_REG_S27, "s27"}, { ARM_REG_S28, "s28"}, { ARM_REG_S29, "s29"}, { ARM_REG_S30, "s30"}, { ARM_REG_S31, "s31"}, }; #endif const char *ARM_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } const char *ARM_reg_name2(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps2)) return NULL; return reg_name_maps2[reg].name; #else return NULL; #endif } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "ARMMappingInsn.inc" }; // look for @id in @insns // return -1 if not found static unsigned int find_insn(unsigned int id) { // binary searching since the IDs are sorted in order unsigned int left, right, m; unsigned int max = ARR_SIZE(insns); right = max - 1; if (id < insns[0].id || id > insns[right].id) // not found return -1; left = 0; while(left <= right) { m = (left + right) / 2; if (id == insns[m].id) { return m; } if (id < insns[m].id) right = m - 1; else left = m + 1; } // not found // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); return -1; } void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned int i = find_insn(id); if (i != -1) { insn->id = insns[i].mapid; // printf("id = %u, mapid = %u\n", id, insn->id); if (h->detail) { #ifndef CAPSTONE_DIET cs_struct handle; handle.detail = h->detail; memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP; insn->detail->groups_count++; } #endif } } } #ifndef CAPSTONE_DIET static const char * const insn_name_maps[] = { NULL, // ARM_INS_INVALID #include "ARMMappingInsnName.inc" }; #endif const char *ARM_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= ARM_INS_ENDING) return NULL; return insn_name_maps[id]; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { ARM_GRP_INVALID, NULL }, { ARM_GRP_JUMP, "jump" }, { ARM_GRP_CALL, "call" }, { ARM_GRP_INT, "int" }, { ARM_GRP_PRIVILEGE, "privilege" }, { ARM_GRP_BRANCH_RELATIVE, "branch_relative" }, // architecture-specific groups { ARM_GRP_CRYPTO, "crypto" }, { ARM_GRP_DATABARRIER, "databarrier" }, { ARM_GRP_DIVIDE, "divide" }, { ARM_GRP_FPARMV8, "fparmv8" }, { ARM_GRP_MULTPRO, "multpro" }, { ARM_GRP_NEON, "neon" }, { ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" }, { ARM_GRP_THUMB2DSP, "THUMB2DSP" }, { ARM_GRP_TRUSTZONE, "TRUSTZONE" }, { ARM_GRP_V4T, "v4t" }, { ARM_GRP_V5T, "v5t" }, { ARM_GRP_V5TE, "v5te" }, { ARM_GRP_V6, "v6" }, { ARM_GRP_V6T2, "v6t2" }, { ARM_GRP_V7, "v7" }, { ARM_GRP_V8, "v8" }, { ARM_GRP_VFP2, "vfp2" }, { ARM_GRP_VFP3, "vfp3" }, { ARM_GRP_VFP4, "vfp4" }, { ARM_GRP_ARM, "arm" }, { ARM_GRP_MCLASS, "mclass" }, { ARM_GRP_NOTMCLASS, "notmclass" }, { ARM_GRP_THUMB, "thumb" }, { ARM_GRP_THUMB1ONLY, "thumb1only" }, { ARM_GRP_THUMB2, "thumb2" }, { ARM_GRP_PREV8, "prev8" }, { ARM_GRP_FPVMLX, "fpvmlx" }, { ARM_GRP_MULOPS, "mulops" }, { ARM_GRP_CRC, "crc" }, { ARM_GRP_DPVFP, "dpvfp" }, { ARM_GRP_V6M, "v6m" }, { ARM_GRP_VIRTUALIZATION, "virtualization" }, }; #endif const char *ARM_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // list all relative branch instructions // ie: insns[i].branch && !insns[i].indirect_branch static const unsigned int insn_rel[] = { ARM_BL, ARM_BLX_pred, ARM_Bcc, ARM_t2B, ARM_t2Bcc, ARM_tB, ARM_tBcc, ARM_tCBNZ, ARM_tCBZ, ARM_BL_pred, ARM_BLXi, ARM_tBL, ARM_tBLXi, 0 }; static const unsigned int insn_blx_rel_to_arm[] = { ARM_tBLXi, 0 }; // check if this insn is relative branch bool ARM_rel_branch(cs_struct *h, unsigned int id) { int i; for (i = 0; insn_rel[i]; i++) { if (id == insn_rel[i]) { return true; } } // not found return false; } bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) { int i; for (i = 0; insn_blx_rel_to_arm[i]; i++) if (id == insn_blx_rel_to_arm[i]) return true; // not found return false; } #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { uint8_t access[7]; } insn_op; static const insn_op insn_ops[] = { { // NULL item { 0 } }, #include "ARMMappingInsnOp.inc" }; // given internal insn id, return operand access info const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id) { int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { return insn_ops[i].access; } return NULL; } void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count) { uint8_t i; uint8_t read_count, write_count; cs_arm *arm = &(insn->detail->arm); read_count = insn->detail->regs_read_count; write_count = insn->detail->regs_write_count; // implicit registers memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); // explicit registers for (i = 0; i < arm->op_count; i++) { cs_arm_op *op = &(arm->operands[i]); switch((int)op->type) { case ARM_OP_REG: if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { regs_read[read_count] = (uint16_t)op->reg; read_count++; } if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { regs_write[write_count] = (uint16_t)op->reg; write_count++; } break; case ARM_OP_MEM: // registers appeared in memory references always being read if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { regs_read[read_count] = (uint16_t)op->mem.base; read_count++; } if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { regs_read[read_count] = (uint16_t)op->mem.index; read_count++; } if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) { regs_write[write_count] = (uint16_t)op->mem.base; write_count++; } default: break; } } *regs_read_count = read_count; *regs_write_count = write_count; } #endif #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMMapping.h000064400000000000000000000021650072674642500176470ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_ARM_MAP_H #define CS_ARM_MAP_H #include "../../include/capstone/capstone.h" #include "../../utils.h" // return name of regiser in friendly string const char *ARM_reg_name(csh handle, unsigned int reg); const char *ARM_reg_name2(csh handle, unsigned int reg); // given internal insn id, return public instruction ID void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *ARM_insn_name(csh handle, unsigned int id); const char *ARM_group_name(csh handle, unsigned int id); // check if this insn is relative branch bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id); void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); typedef struct BankedReg { const char *Name; arm_sysreg sysreg; uint16_t Encoding; } BankedReg; const BankedReg *lookupBankedRegByEncoding(uint8_t encoding); #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMMappingInsn.inc000064400000000000000000010720700072674642500210240ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { ARM_ASRi, ARM_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_ASRr, ARM_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_ITasm, ARM_INS_IT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LDRBT_POST, ARM_INS_LDRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LDRConstPool, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LDRT_POST, ARM_INS_LDRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LSLi, ARM_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LSLr, ARM_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LSRi, ARM_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_LSRr, ARM_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_RORi, ARM_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_RORr, ARM_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_RRXi, ARM_INS_RRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_STRBT_POST, ARM_INS_STRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_STRT_POST, ARM_INS_STRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdAsm_16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdAsm_32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdAsm_8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdAsm_16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdAsm_32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdAsm_8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNqAsm_16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNqAsm_32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdAsm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdAsm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdAsm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqAsm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqAsm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqAsm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdAsm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdAsm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdAsm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNqAsm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNqAsm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dAsm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dAsm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dAsm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qAsm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qAsm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qAsm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdAsm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdAsm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdAsm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqAsm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqAsm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqAsm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdAsm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdAsm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdAsm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNqAsm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNqAsm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dAsm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dAsm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dAsm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qAsm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qAsm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qAsm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdAsm_16, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdAsm_32, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdAsm_8, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdAsm_16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdAsm_32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdAsm_8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNqAsm_16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNqAsm_32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdAsm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdAsm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdAsm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNqAsm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNqAsm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dAsm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dAsm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dAsm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dWB_register_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dWB_register_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3dWB_register_Asm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qAsm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qAsm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qAsm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qWB_register_Asm_16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qWB_register_Asm_32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST3qWB_register_Asm_8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdAsm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdAsm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdAsm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNqAsm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNqAsm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dAsm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dAsm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dAsm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dWB_register_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dWB_register_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4dWB_register_Asm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qAsm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qAsm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qAsm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qWB_register_Asm_16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qWB_register_Asm_32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VST4qWB_register_Asm_8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2LDRBpcrel, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2LDRConstPool, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2LDRHpcrel, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2LDRSBpcrel, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2LDRSHpcrel, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2LDRpcrel, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2MOVSsi, ARM_INS_MOVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2MOVSsr, ARM_INS_MOVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2MOVsi, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2MOVsr, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_tLDRConstPool, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_ADCri, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADCrr, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADCrsi, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADCrsr, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADDri, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADDrr, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADDrsi, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADDrsr, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ADR, ARM_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_AESD, ARM_INS_AESD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_AESE, ARM_INS_AESE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_AESIMC, ARM_INS_AESIMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_AESMC, ARM_INS_AESMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_ANDri, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ANDrr, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ANDrsi, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ANDrsr, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_BFC, ARM_INS_BFC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_BFI, ARM_INS_BFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_BICri, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_BICrr, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_BICrsi, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_BICrsr, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_BKPT, ARM_INS_BKPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_BL, ARM_INS_BL, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 #endif }, { ARM_BLX, ARM_INS_BLX, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1 #endif }, { ARM_BLX_pred, ARM_INS_BLX, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 #endif }, { ARM_BLXi, ARM_INS_BLX, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0 #endif }, { ARM_BL_pred, ARM_INS_BL, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 #endif }, { ARM_BX, ARM_INS_BX, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 #endif }, { ARM_BXJ, ARM_INS_BXJ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1 #endif }, { ARM_BX_RET, ARM_INS_BX, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 #endif }, { ARM_BX_pred, ARM_INS_BX, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 #endif }, { ARM_Bcc, ARM_INS_B, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 #endif }, { ARM_CDP, ARM_INS_CDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_CDP2, ARM_INS_CDP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_CLREX, ARM_INS_CLREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_CLZ, ARM_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 #endif }, { ARM_CMNri, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMNzrr, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMNzrsi, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMNzrsr, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMPri, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMPrr, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMPrsi, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CMPrsr, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CPS1p, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CPS2p, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CPS3p, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_CRC32B, ARM_INS_CRC32B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_CRC32CB, ARM_INS_CRC32CB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_CRC32CH, ARM_INS_CRC32CH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_CRC32CW, ARM_INS_CRC32CW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_CRC32H, ARM_INS_CRC32H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_CRC32W, ARM_INS_CRC32W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_DBG, ARM_INS_DBG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_DMB, ARM_INS_DMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 #endif }, { ARM_DSB, ARM_INS_DSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 #endif }, { ARM_EORri, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_EORrr, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_EORrsi, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_EORrsr, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ERET, ARM_INS_ERET, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_FCONSTD, ARM_INS_FCONSTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_FCONSTH, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_FCONSTS, ARM_INS_FCONSTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 #endif }, { ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_FLDMXIA, ARM_INS_FLDMIAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_FMSTAT, ARM_INS_FMSTAT, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_FSTMXIA, ARM_INS_FSTMIAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_HINT, ARM_INS_HINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_HLT, ARM_INS_HLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_HVC, ARM_INS_HVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_ISB, ARM_INS_ISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 #endif }, { ARM_LDA, ARM_INS_LDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDAB, ARM_INS_LDAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDAEX, ARM_INS_LDAEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDAEXB, ARM_INS_LDAEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDAEXD, ARM_INS_LDAEXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDAEXH, ARM_INS_LDAEXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDAH, ARM_INS_LDAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_LDC2L_OFFSET, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2L_OPTION, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2L_POST, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2L_PRE, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2_OFFSET, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2_OPTION, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2_POST, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDC2_PRE, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_LDCL_OFFSET, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDCL_OPTION, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDCL_POST, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDCL_PRE, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDC_OFFSET, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDC_OPTION, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDC_POST, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDC_PRE, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMDA, ARM_INS_LDMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMDA_UPD, ARM_INS_LDMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMDB, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMDB_UPD, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMIA, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMIA_UPD, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMIB, ARM_INS_LDMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDMIB_UPD, ARM_INS_LDMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRBT_POST_REG, ARM_INS_LDRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRB_POST_IMM, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRB_POST_REG, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRB_PRE_IMM, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRB_PRE_REG, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRBi12, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRBrs, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRD, ARM_INS_LDRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_LDRD_POST, ARM_INS_LDRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRD_PRE, ARM_INS_LDRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDREX, ARM_INS_LDREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDREXB, ARM_INS_LDREXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDREXD, ARM_INS_LDREXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDREXH, ARM_INS_LDREXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRH, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRHTi, ARM_INS_LDRHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRHTr, ARM_INS_LDRHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRH_POST, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRH_PRE, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSB, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSBTi, ARM_INS_LDRSBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSBTr, ARM_INS_LDRSBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSB_POST, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSB_PRE, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSH, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSHTi, ARM_INS_LDRSHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSHTr, ARM_INS_LDRSHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSH_POST, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRSH_PRE, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRT_POST_IMM, ARM_INS_LDRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRT_POST_REG, ARM_INS_LDRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDR_POST_IMM, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDR_POST_REG, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDR_PRE_IMM, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDR_PRE_REG, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRcp, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRi12, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_LDRrs, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MCR, ARM_INS_MCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MCR2, ARM_INS_MCR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_MCRR, ARM_INS_MCRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MCRR2, ARM_INS_MCRR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_MLA, ARM_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_MLS, ARM_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_MOVPCLR, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MOVTi16, ARM_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_MOVi, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MOVi16, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_MOVr, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MOVr_TC, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MOVsi, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MOVsr, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MRC, ARM_INS_MRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MRC2, ARM_INS_MRC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_MRRC, ARM_INS_MRRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MRRC2, ARM_INS_MRRC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_MRS, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MRSbanked, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_MRSsys, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MSR, ARM_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MSRbanked, ARM_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_MSRi, ARM_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MUL, ARM_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_MVNi, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MVNr, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MVNsi, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_MVNsr, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ORRri, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ORRrr, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ORRrsi, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_ORRrsr, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_PKHBT, ARM_INS_PKHBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_PKHTB, ARM_INS_PKHTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_PLDWi12, ARM_INS_PLDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 #endif }, { ARM_PLDWrs, ARM_INS_PLDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 #endif }, { ARM_PLDi12, ARM_INS_PLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_PLDrs, ARM_INS_PLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_PLIi12, ARM_INS_PLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_PLIrs, ARM_INS_PLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_QADD, ARM_INS_QADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QADD16, ARM_INS_QADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QADD8, ARM_INS_QADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QASX, ARM_INS_QASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QDADD, ARM_INS_QDADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QDSUB, ARM_INS_QDSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QSAX, ARM_INS_QSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QSUB, ARM_INS_QSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QSUB16, ARM_INS_QSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_QSUB8, ARM_INS_QSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RBIT, ARM_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_REV, ARM_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_REV16, ARM_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_REVSH, ARM_INS_REVSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_RFEDA, ARM_INS_RFEDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEDA_UPD, ARM_INS_RFEDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEDB, ARM_INS_RFEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEDB_UPD, ARM_INS_RFEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEIA, ARM_INS_RFEIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEIA_UPD, ARM_INS_RFEIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEIB, ARM_INS_RFEIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RFEIB_UPD, ARM_INS_RFEIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSBri, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSBrr, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSBrsi, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSBrsr, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSCri, ARM_INS_RSC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSCrr, ARM_INS_RSC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSCrsi, ARM_INS_RSC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_RSCrsr, ARM_INS_RSC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SADD16, ARM_INS_SADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SADD8, ARM_INS_SADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SASX, ARM_INS_SASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SBCri, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SBCrr, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SBCrsi, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SBCrsr, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SBFX, ARM_INS_SBFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_SDIV, ARM_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SEL, ARM_INS_SEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SETEND, ARM_INS_SETEND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SETPAN, ARM_INS_SETPAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_SHA1C, ARM_INS_SHA1C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA1H, ARM_INS_SHA1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA1M, ARM_INS_SHA1M, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA1P, ARM_INS_SHA1P, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA1SU0, ARM_INS_SHA1SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA1SU1, ARM_INS_SHA1SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA256H, ARM_INS_SHA256H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA256H2, ARM_INS_SHA256H2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA256SU0, ARM_INS_SHA256SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHA256SU1, ARM_INS_SHA256SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_SHADD16, ARM_INS_SHADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SHADD8, ARM_INS_SHADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SHASX, ARM_INS_SHASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SHSAX, ARM_INS_SHSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SHSUB16, ARM_INS_SHSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SHSUB8, ARM_INS_SHSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SMC, ARM_INS_SMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 #endif }, { ARM_SMLABB, ARM_INS_SMLABB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMLABT, ARM_INS_SMLABT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMLAD, ARM_INS_SMLAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLADX, ARM_INS_SMLADX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLAL, ARM_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLALBB, ARM_INS_SMLALBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMLALBT, ARM_INS_SMLALBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMLALD, ARM_INS_SMLALD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLALDX, ARM_INS_SMLALDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLALTB, ARM_INS_SMLALTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMLALTT, ARM_INS_SMLALTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMLATB, ARM_INS_SMLATB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMLATT, ARM_INS_SMLATT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMLAWB, ARM_INS_SMLAWB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMLAWT, ARM_INS_SMLAWT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMLSD, ARM_INS_SMLSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLSDX, ARM_INS_SMLSDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLSLD, ARM_INS_SMLSLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMLSLDX, ARM_INS_SMLSLDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMMLA, ARM_INS_SMMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMMLAR, ARM_INS_SMMLAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMMLS, ARM_INS_SMMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_SMMLSR, ARM_INS_SMMLSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMMUL, ARM_INS_SMMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMMULR, ARM_INS_SMMULR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMUAD, ARM_INS_SMUAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMUADX, ARM_INS_SMUADX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMULBB, ARM_INS_SMULBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMULBT, ARM_INS_SMULBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMULL, ARM_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMULTB, ARM_INS_SMULTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMULTT, ARM_INS_SMULTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMULWB, ARM_INS_SMULWB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMULWT, ARM_INS_SMULWT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_SMUSD, ARM_INS_SMUSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SMUSDX, ARM_INS_SMUSDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SRSDA, ARM_INS_SRSDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSDA_UPD, ARM_INS_SRSDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSDB, ARM_INS_SRSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSDB_UPD, ARM_INS_SRSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSIA, ARM_INS_SRSIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSIA_UPD, ARM_INS_SRSIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSIB, ARM_INS_SRSIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SRSIB_UPD, ARM_INS_SRSIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SSAT, ARM_INS_SSAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SSAT16, ARM_INS_SSAT16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SSAX, ARM_INS_SSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SSUB16, ARM_INS_SSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SSUB8, ARM_INS_SSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STC2L_OFFSET, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2L_OPTION, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2L_POST, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2L_PRE, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2_OFFSET, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2_OPTION, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2_POST, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STC2_PRE, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_STCL_OFFSET, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STCL_OPTION, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STCL_POST, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STCL_PRE, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STC_OFFSET, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STC_OPTION, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STC_POST, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STC_PRE, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STL, ARM_INS_STL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STLB, ARM_INS_STLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STLEX, ARM_INS_STLEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STLEXB, ARM_INS_STLEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STLEXD, ARM_INS_STLEXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STLEXH, ARM_INS_STLEXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STLH, ARM_INS_STLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_STMDA, ARM_INS_STMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMDA_UPD, ARM_INS_STMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMDB, ARM_INS_STMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMDB_UPD, ARM_INS_STMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMIA, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMIA_UPD, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMIB, ARM_INS_STMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STMIB_UPD, ARM_INS_STMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRBT_POST_IMM, ARM_INS_STRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRBT_POST_REG, ARM_INS_STRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRB_POST_IMM, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRB_POST_REG, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRB_PRE_IMM, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRB_PRE_REG, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRBi12, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRBrs, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRD, ARM_INS_STRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 #endif }, { ARM_STRD_POST, ARM_INS_STRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRD_PRE, ARM_INS_STRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STREX, ARM_INS_STREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STREXB, ARM_INS_STREXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STREXD, ARM_INS_STREXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STREXH, ARM_INS_STREXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRH, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRHTi, ARM_INS_STRHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRHTr, ARM_INS_STRHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRH_POST, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRH_PRE, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRT_POST_IMM, ARM_INS_STRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRT_POST_REG, ARM_INS_STRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STR_POST_IMM, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STR_POST_REG, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STR_PRE_IMM, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STR_PRE_REG, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRi12, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_STRrs, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SUBri, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SUBrr, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SUBrsi, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SUBrsr, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_SVC, ARM_INS_SVC, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_INT, 0 }, 0, 0 #endif }, { ARM_SWP, ARM_INS_SWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_SWPB, ARM_INS_SWPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_SXTAB, ARM_INS_SXTAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SXTAB16, ARM_INS_SXTAB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SXTAH, ARM_INS_SXTAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SXTB, ARM_INS_SXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SXTB16, ARM_INS_SXTB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_SXTH, ARM_INS_SXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_TEQri, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TEQrr, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TEQrsi, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TEQrsr, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TRAP, ARM_INS_TRAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TRAPNaCl, ARM_INS_TRAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TSB, ARM_INS_TSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_TSTri, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TSTrr, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TSTrsi, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_TSTrsr, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UADD16, ARM_INS_UADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UADD8, ARM_INS_UADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UASX, ARM_INS_UASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UBFX, ARM_INS_UBFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 #endif }, { ARM_UDF, ARM_INS_UDF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UDIV, ARM_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UHADD16, ARM_INS_UHADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UHADD8, ARM_INS_UHADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UHASX, ARM_INS_UHASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UHSAX, ARM_INS_UHSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UHSUB16, ARM_INS_UHSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UHSUB8, ARM_INS_UHSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UMAAL, ARM_INS_UMAAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UMLAL, ARM_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UMULL, ARM_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UQADD16, ARM_INS_UQADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UQADD8, ARM_INS_UQADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UQASX, ARM_INS_UQASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UQSAX, ARM_INS_UQSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UQSUB16, ARM_INS_UQSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UQSUB8, ARM_INS_UQSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_USAD8, ARM_INS_USAD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_USADA8, ARM_INS_USADA8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_USAT, ARM_INS_USAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_USAT16, ARM_INS_USAT16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_USAX, ARM_INS_USAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_USUB16, ARM_INS_USUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_USUB8, ARM_INS_USUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_UXTAB, ARM_INS_UXTAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UXTAB16, ARM_INS_UXTAB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UXTAH, ARM_INS_UXTAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UXTB, ARM_INS_UXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UXTB16, ARM_INS_UXTB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_UXTH, ARM_INS_UXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_VABALsv2i64, ARM_INS_VABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABALsv4i32, ARM_INS_VABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABALsv8i16, ARM_INS_VABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABALuv2i64, ARM_INS_VABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABALuv4i32, ARM_INS_VABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABALuv8i16, ARM_INS_VABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAsv16i8, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAsv2i32, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAsv4i16, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAsv4i32, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAsv8i16, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAsv8i8, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAuv16i8, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAuv2i32, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAuv4i16, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAuv4i32, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAuv8i16, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABAuv8i8, ARM_INS_VABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDLsv2i64, ARM_INS_VABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDLsv4i32, ARM_INS_VABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDLsv8i16, ARM_INS_VABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDLuv2i64, ARM_INS_VABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDLuv4i32, ARM_INS_VABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDLuv8i16, ARM_INS_VABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDfd, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDfq, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDhd, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VABDhq, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VABDsv16i8, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDsv2i32, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDsv4i16, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDsv4i32, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDsv8i16, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDsv8i8, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDuv16i8, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDuv2i32, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDuv4i16, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDuv4i32, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDuv8i16, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABDuv8i8, ARM_INS_VABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSD, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VABSH, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VABSS, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VABSfd, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSfq, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABShd, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VABShq, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VABSv16i8, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSv2i32, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSv4i16, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSv4i32, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSv8i16, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VABSv8i8, ARM_INS_VABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VACGEfd, ARM_INS_VACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGEfq, ARM_INS_VACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGEhd, ARM_INS_VACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGEhq, ARM_INS_VACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGTfd, ARM_INS_VACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGTfq, ARM_INS_VACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGThd, ARM_INS_VACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VACGThq, ARM_INS_VACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VADDD, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VADDH, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VADDHNv2i32, ARM_INS_VADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDHNv4i16, ARM_INS_VADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDHNv8i8, ARM_INS_VADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDLsv2i64, ARM_INS_VADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDLsv4i32, ARM_INS_VADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDLsv8i16, ARM_INS_VADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDLuv2i64, ARM_INS_VADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDLuv4i32, ARM_INS_VADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDLuv8i16, ARM_INS_VADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDS, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VADDWsv2i64, ARM_INS_VADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDWsv4i32, ARM_INS_VADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDWsv8i16, ARM_INS_VADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDWuv2i64, ARM_INS_VADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDWuv4i32, ARM_INS_VADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDWuv8i16, ARM_INS_VADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDfd, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDfq, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDhd, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VADDhq, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VADDv16i8, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv1i64, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv2i32, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv2i64, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv4i16, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv4i32, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv8i16, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VADDv8i8, ARM_INS_VADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VANDd, ARM_INS_VAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VANDq, ARM_INS_VAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBICd, ARM_INS_VBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBICiv2i32, ARM_INS_VBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBICiv4i16, ARM_INS_VBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBICiv4i32, ARM_INS_VBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBICiv8i16, ARM_INS_VBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBICq, ARM_INS_VBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBIFd, ARM_INS_VBIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBIFq, ARM_INS_VBIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBITd, ARM_INS_VBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBITq, ARM_INS_VBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBSLd, ARM_INS_VBSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VBSLq, ARM_INS_VBSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCADDv2f32, ARM_INS_VCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCADDv4f16, ARM_INS_VCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCADDv4f32, ARM_INS_VCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCADDv8f16, ARM_INS_VCADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCEQfd, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQfq, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQhd, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCEQhq, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCEQv16i8, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQv2i32, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQv4i16, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQv4i32, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQv8i16, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQv8i8, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv16i8, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv2f32, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv2i32, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv4f16, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCEQzv4f32, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv4i16, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv4i32, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv8f16, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCEQzv8i16, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCEQzv8i8, ARM_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEfd, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEfq, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEhd, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGEhq, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGEsv16i8, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEsv2i32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEsv4i16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEsv4i32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEsv8i16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEsv8i8, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEuv16i8, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEuv2i32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEuv4i16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEuv4i32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEuv8i16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEuv8i8, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv16i8, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv2f32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv2i32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv4f16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGEzv4f32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv4i16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv4i32, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv8f16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGEzv8i16, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGEzv8i8, ARM_INS_VCGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTfd, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTfq, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGThd, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGThq, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGTsv16i8, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTsv2i32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTsv4i16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTsv4i32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTsv8i16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTsv8i8, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTuv16i8, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTuv2i32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTuv4i16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTuv4i32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTuv8i16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTuv8i8, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv16i8, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv2f32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv2i32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv4f16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGTzv4f32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv4i16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv4i32, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv8f16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCGTzv8i16, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCGTzv8i8, ARM_INS_VCGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv16i8, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv2f32, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv2i32, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv4f16, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCLEzv4f32, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv4i16, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv4i32, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv8f16, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCLEzv8i16, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLEzv8i8, ARM_INS_VCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLSv16i8, ARM_INS_VCLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLSv2i32, ARM_INS_VCLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLSv4i16, ARM_INS_VCLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLSv4i32, ARM_INS_VCLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLSv8i16, ARM_INS_VCLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLSv8i8, ARM_INS_VCLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv16i8, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv2f32, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv2i32, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv4f16, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCLTzv4f32, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv4i16, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv4i32, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv8f16, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCLTzv8i16, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLTzv8i8, ARM_INS_VCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLZv16i8, ARM_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLZv2i32, ARM_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLZv4i16, ARM_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLZv4i32, ARM_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLZv8i16, ARM_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCLZv8i8, ARM_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCMLAv2f32, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv4f16, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv4f32, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv8f16, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMPD, ARM_INS_VCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCMPED, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCMPEH, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMPES, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCMPEZD, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCMPEZH, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMPEZS, ARM_INS_VCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCMPH, ARM_INS_VCMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMPS, ARM_INS_VCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCMPZD, ARM_INS_VCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCMPZH, ARM_INS_VCMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCMPZS, ARM_INS_VCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCNTd, ARM_INS_VCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCNTq, ARM_INS_VCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTANSDf, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANSDh, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANSQf, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANSQh, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANUDf, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANUDh, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANUQf, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTANUQh, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTASD, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTASH, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTASS, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTAUD, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTAUH, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTAUS, ARM_INS_VCVTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTBDH, ARM_INS_VCVTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTBHD, ARM_INS_VCVTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTBHS, ARM_INS_VCVTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCVTBSH, ARM_INS_VCVTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCVTDS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTMNSDf, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNSDh, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNSQf, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNSQh, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNUDf, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNUDh, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNUQf, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMNUQh, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMSD, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTMSH, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMSS, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTMUD, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTMUH, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTMUS, ARM_INS_VCVTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTNNSDf, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNSDh, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNSQf, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNSQh, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNUDf, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNUDh, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNUQf, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNNUQh, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNSD, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTNSH, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNSS, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTNUD, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTNUH, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTNUS, ARM_INS_VCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTPNSDf, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNSDh, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNSQf, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNSQh, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNUDf, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNUDh, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNUQf, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPNUQh, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPSD, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTPSH, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPSS, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTPUD, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTPUH, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTPUS, ARM_INS_VCVTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VCVTSD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTTDH, ARM_INS_VCVTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTTHD, ARM_INS_VCVTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VCVTTHS, ARM_INS_VCVTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCVTTSH, ARM_INS_VCVTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VCVTf2h, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2sd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2sq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2ud, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2uq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2xsd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2xsq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2xud, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTf2xuq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTh2f, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTh2sd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2sq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2ud, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2uq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2xsd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2xsq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2xud, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTh2xuq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTs2fd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTs2fq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTs2hd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTs2hq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTu2fd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTu2fq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTu2hd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTu2hq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTxs2fd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTxs2fq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTxs2hd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTxs2hq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTxu2fd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTxu2fq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VCVTxu2hd, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VCVTxu2hq, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VDIVD, ARM_INS_VDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VDIVH, ARM_INS_VDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VDIVS, ARM_INS_VDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VDUP16d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUP16q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUP32d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUP32q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUP8d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUP8q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUPLN16d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUPLN16q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUPLN32d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUPLN32q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUPLN8d, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VDUPLN8q, ARM_INS_VDUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEORd, ARM_INS_VEOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEORq, ARM_INS_VEOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTd16, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTd32, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTd8, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTq16, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTq32, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTq64, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VEXTq8, ARM_INS_VEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VFMAD, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VFMAH, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFMAS, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFMAfd, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFMAfq, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFMAhd, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFMAhq, ARM_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFMSD, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VFMSH, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFMSS, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFMSfd, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFMSfq, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFMShd, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFMShq, ARM_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFNMAD, ARM_INS_VFNMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VFNMAH, ARM_INS_VFNMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFNMAS, ARM_INS_VFNMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VFNMSD, ARM_INS_VFNMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VFNMSH, ARM_INS_VFNMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VFNMSS, ARM_INS_VFNMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 #endif }, { ARM_VGETLNi32, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VGETLNs16, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VGETLNs8, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VGETLNu16, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VGETLNu8, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDsv16i8, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDsv2i32, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDsv4i16, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDsv4i32, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDsv8i16, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDsv8i8, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDuv16i8, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDuv2i32, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDuv4i16, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDuv4i32, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDuv8i16, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHADDuv8i8, ARM_INS_VHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBsv16i8, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBsv2i32, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBsv4i16, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBsv4i32, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBsv8i16, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBsv8i8, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBuv16i8, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBuv2i32, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBuv4i16, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBuv4i32, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBuv8i16, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VHSUBuv8i8, ARM_INS_VHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VINSH, ARM_INS_VINS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VJCVT, ARM_INS_VJCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLD1DUPd16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd16wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd32wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPd8wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq16wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq32wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1DUPq8wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1LNd16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1LNd16_UPD, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1LNd32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1LNd32_UPD, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1LNd8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1LNd8_UPD, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16Q, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16Qwb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16T, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16Twb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16Twb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d16wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32Q, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32Qwb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32T, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32Twb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32Twb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d32wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64Q, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64Qwb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64T, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64Twb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64Twb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d64wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8Q, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8Qwb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8T, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8Twb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8Twb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1d8wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q16, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q16wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q16wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q32, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q32wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q32wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q64, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q64wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q64wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q8, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q8wb_fixed, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD1q8wb_register, ARM_INS_VLD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd16wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd16x2, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd32wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd32x2, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd8wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd8x2, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNd16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNd16_UPD, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNd32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNd32_UPD, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNd8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNd8_UPD, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNq16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNq16_UPD, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNq32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2LNq32_UPD, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b16wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b16wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b32wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b32wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b8wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2b8wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d16wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d16wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d32wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d32wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d8wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2d8wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q16, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q16wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q16wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q32, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q32wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q32wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q8, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q8wb_fixed, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD2q8wb_register, ARM_INS_VLD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPd16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPd16_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPd32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPd32_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPd8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPd8_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPq16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPq16_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPq32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPq32_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPq8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3DUPq8_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNd16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNd16_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNd32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNd32_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNd8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNd8_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNq16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNq16_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNq32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3LNq32_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3d16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3d16_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3d32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3d32_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3d8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3d8_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3q16, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3q16_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3q32, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3q32_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3q8, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD3q8_UPD, ARM_INS_VLD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPd16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPd16_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPd32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPd32_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPd8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPd8_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPq16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPq16_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPq32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPq32_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPq8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4DUPq8_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNd16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNd16_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNd32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNd32_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNd8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNd8_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNq16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNq16_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNq32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4LNq32_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4d16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4d16_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4d32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4d32_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4d8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4d8_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4q16, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4q16_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4q32, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4q32_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4q8, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLD4q8_UPD, ARM_INS_VLD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDMDIA, ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDMSIA, ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDRD, ARM_INS_VLDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLDRH, ARM_INS_VLDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLDRS, ARM_INS_VLDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VLLDM, ARM_INS_VLLDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VLSTM, ARM_INS_VLSTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXNMD, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VMAXNMH, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXNMNDf, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXNMNDh, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXNMNQf, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXNMNQh, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXNMS, ARM_INS_VMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VMAXfd, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXfq, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXhd, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXhq, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMAXsv16i8, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXsv2i32, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXsv4i16, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXsv4i32, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXsv8i16, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXsv8i8, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXuv16i8, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXuv2i32, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXuv4i16, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXuv4i32, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXuv8i16, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMAXuv8i8, ARM_INS_VMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINNMD, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VMINNMH, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINNMNDf, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINNMNDh, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINNMNQf, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINNMNQh, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINNMS, ARM_INS_VMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VMINfd, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINfq, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINhd, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINhq, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMINsv16i8, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINsv2i32, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINsv4i16, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINsv4i32, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINsv8i16, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINsv8i8, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINuv16i8, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINuv2i32, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINuv4i16, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINuv4i32, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINuv8i16, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMINuv8i8, ARM_INS_VMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAD, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLAH, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLALslsv2i32, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALslsv4i16, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALsluv2i32, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALsluv4i16, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALsv2i64, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALsv4i32, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALsv8i16, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALuv2i64, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALuv4i32, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLALuv8i16, ARM_INS_VMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAS, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLAfd, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLAfq, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLAhd, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLAhq, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLAslfd, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLAslfq, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLAslhd, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLAslhq, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLAslv2i32, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAslv4i16, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAslv4i32, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAslv8i16, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAv16i8, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAv2i32, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAv4i16, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAv4i32, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAv8i16, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLAv8i8, ARM_INS_VMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSD, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLSH, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLSLslsv2i32, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLslsv4i16, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLsluv2i32, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLsluv4i16, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLsv2i64, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLsv4i32, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLsv8i16, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLuv2i64, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLuv4i32, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSLuv8i16, ARM_INS_VMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSS, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLSfd, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLSfq, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLShd, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLShq, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLSslfd, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLSslfq, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VMLSslhd, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLSslhq, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMLSslv2i32, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSslv4i16, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSslv4i32, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSslv8i16, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSv16i8, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSv2i32, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSv4i16, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSv4i32, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSv8i16, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMLSv8i8, ARM_INS_VMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVD, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VMOVDRR, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVH, ARM_INS_VMOVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMOVHR, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMOVLsv2i64, ARM_INS_VMOVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVLsv4i32, ARM_INS_VMOVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVLsv8i16, ARM_INS_VMOVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVLuv2i64, ARM_INS_VMOVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVLuv4i32, ARM_INS_VMOVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVLuv8i16, ARM_INS_VMOVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVNv2i32, ARM_INS_VMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVNv4i16, ARM_INS_VMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVNv8i8, ARM_INS_VMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVRH, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMOVRRD, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVRRS, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVRS, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVS, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVSR, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVSRR, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMOVv16i8, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv1i64, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv2f32, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv2i32, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv2i64, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv4f32, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv4i16, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv4i32, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv8i16, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMOVv8i8, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMRS, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_FPEXC, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_FPINST, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_FPINST2, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_FPSID, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_MVFR0, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_MVFR1, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMRS_MVFR2, ARM_INS_VMRS, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VMSR, ARM_INS_VMSR, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMSR_FPEXC, ARM_INS_VMSR, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMSR_FPINST, ARM_INS_VMSR, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMSR_FPINST2, ARM_INS_VMSR, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMSR_FPSID, ARM_INS_VMSR, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMULD, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VMULH, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMULLp64, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 #endif }, { ARM_VMULLp8, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLslsv2i32, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLslsv4i16, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLsluv2i32, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLsluv4i16, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLsv2i64, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLsv4i32, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLsv8i16, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLuv2i64, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLuv4i32, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULLuv8i16, ARM_INS_VMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULS, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VMULfd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULfq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULhd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMULhq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMULpd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULpq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULslfd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULslfq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULslhd, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMULslhq, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VMULslv2i32, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULslv4i16, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULslv4i32, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULslv8i16, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULv16i8, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULv2i32, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULv4i16, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULv4i32, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULv8i16, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMULv8i8, ARM_INS_VMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMVNd, ARM_INS_VMVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMVNq, ARM_INS_VMVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMVNv2i32, ARM_INS_VMVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMVNv4i16, ARM_INS_VMVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMVNv4i32, ARM_INS_VMVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VMVNv8i16, ARM_INS_VMVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGD, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VNEGH, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VNEGS, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VNEGf32q, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGfd, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGhd, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VNEGhq, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VNEGs16d, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGs16q, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGs32d, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGs32q, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGs8d, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNEGs8q, ARM_INS_VNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VNMLAD, ARM_INS_VNMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VNMLAH, ARM_INS_VNMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VNMLAS, ARM_INS_VNMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VNMLSD, ARM_INS_VNMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VNMLSH, ARM_INS_VNMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VNMLSS, ARM_INS_VNMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 #endif }, { ARM_VNMULD, ARM_INS_VNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VNMULH, ARM_INS_VNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VNMULS, ARM_INS_VNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VORNd, ARM_INS_VORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORNq, ARM_INS_VORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORRd, ARM_INS_VORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORRiv2i32, ARM_INS_VORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORRiv4i16, ARM_INS_VORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORRiv4i32, ARM_INS_VORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORRiv8i16, ARM_INS_VORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VORRq, ARM_INS_VORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALsv16i8, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALsv2i32, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALsv4i16, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALsv4i32, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALsv8i16, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALsv8i8, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALuv16i8, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALuv2i32, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALuv4i16, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALuv4i32, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALuv8i16, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADALuv8i8, ARM_INS_VPADAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLsv16i8, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLsv2i32, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLsv4i16, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLsv4i32, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLsv8i16, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLsv8i8, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLuv16i8, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLuv2i32, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLuv4i16, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLuv4i32, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLuv8i16, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDLuv8i8, ARM_INS_VPADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDf, ARM_INS_VPADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDh, ARM_INS_VPADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VPADDi16, ARM_INS_VPADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDi32, ARM_INS_VPADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPADDi8, ARM_INS_VPADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXf, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXh, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VPMAXs16, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXs32, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXs8, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXu16, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXu32, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMAXu8, ARM_INS_VPMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINf, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINh, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VPMINs16, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINs32, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINs8, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINu16, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINu32, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VPMINu8, ARM_INS_VPMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQABSv16i8, ARM_INS_VQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQABSv2i32, ARM_INS_VQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQABSv4i16, ARM_INS_VQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQABSv4i32, ARM_INS_VQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQABSv8i16, ARM_INS_VQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQABSv8i8, ARM_INS_VQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv16i8, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv1i64, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv2i32, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv2i64, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv4i16, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv4i32, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv8i16, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDsv8i8, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv16i8, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv1i64, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv2i32, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv2i64, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv4i16, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv4i32, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv8i16, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQADDuv8i8, ARM_INS_VQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLALv2i64, ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLALv4i32, ARM_INS_VQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHslv2i32, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHslv4i16, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHslv4i32, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHslv8i16, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHv2i32, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHv4i16, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHv4i32, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULHv8i16, ARM_INS_VQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULLslv2i32, ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULLslv4i16, ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULLv2i64, ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQDMULLv4i32, ARM_INS_VQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNsv2i32, ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNsv4i16, ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNuv2i32, ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNuv4i16, ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQNEGv16i8, ARM_INS_VQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQNEGv2i32, ARM_INS_VQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQNEGv4i16, ARM_INS_VQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQNEGv4i32, ARM_INS_VQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQNEGv8i16, ARM_INS_VQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQNEGv8i8, ARM_INS_VQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv16i8, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv1i64, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv2i32, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv2i64, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv4i16, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv4i32, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv8i16, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv16i8, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv1i64, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv2i32, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv2i64, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv4i16, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv4i32, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv8i16, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv16i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv1i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv2i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv2i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv4i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv4i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv8i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsiv8i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv16i8, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv1i64, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv2i32, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv2i64, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv4i16, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv4i32, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv8i16, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv16i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv1i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv2i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv2i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv4i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv4i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv8i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLsv8i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv16i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv1i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv2i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv2i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv4i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv4i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv8i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuiv8i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv16i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv1i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv2i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv2i64, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv4i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv4i32, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv8i16, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHLuv8i8, ARM_INS_VQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRNsv2i32, ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRNsv4i16, ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRNuv2i32, ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRNuv4i16, ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv16i8, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv1i64, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv2i32, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv2i64, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv4i16, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv4i32, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv8i16, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBsv8i8, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv16i8, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv1i64, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv2i32, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv2i64, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv4i16, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv4i32, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv8i16, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VQSUBuv8i8, ARM_INS_VQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRADDHNv2i32, ARM_INS_VRADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRADDHNv4i16, ARM_INS_VRADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRADDHNv8i8, ARM_INS_VRADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPEd, ARM_INS_VRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPEfd, ARM_INS_VRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPEfq, ARM_INS_VRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPEhd, ARM_INS_VRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRECPEhq, ARM_INS_VRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRECPEq, ARM_INS_VRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPSfd, ARM_INS_VRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPSfq, ARM_INS_VRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRECPShd, ARM_INS_VRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRECPShq, ARM_INS_VRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VREV16d8, ARM_INS_VREV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV16q8, ARM_INS_VREV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV32d16, ARM_INS_VREV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV32d8, ARM_INS_VREV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV32q16, ARM_INS_VREV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV32q8, ARM_INS_VREV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV64d16, ARM_INS_VREV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV64d32, ARM_INS_VREV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV64d8, ARM_INS_VREV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV64q16, ARM_INS_VREV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV64q32, ARM_INS_VREV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VREV64q8, ARM_INS_VREV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDsv16i8, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDsv2i32, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDsv4i16, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDsv4i32, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDsv8i16, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDsv8i8, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDuv16i8, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDuv2i32, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDuv4i16, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDuv4i32, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDuv8i16, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRHADDuv8i8, ARM_INS_VRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRINTAD, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTAH, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTANDf, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTANDh, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTANQf, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTANQh, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTAS, ARM_INS_VRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRINTMD, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTMH, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTMNDf, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTMNDh, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTMNQf, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTMNQh, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTMS, ARM_INS_VRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRINTND, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTNH, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTNNDf, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTNNDh, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTNNQf, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTNNQh, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTNS, ARM_INS_VRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRINTPD, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTPH, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTPNDf, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTPNDh, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTPNQf, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTPNQh, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTPS, ARM_INS_VRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRINTRD, ARM_INS_VRINTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTRH, ARM_INS_VRINTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTRS, ARM_INS_VRINTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRINTXD, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTXH, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTXNDf, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTXNDh, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTXNQf, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTXNQh, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTXS, ARM_INS_VRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRINTZD, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VRINTZH, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTZNDf, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTZNDh, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTZNQf, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTZNQh, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRINTZS, ARM_INS_VRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VRSHLsv16i8, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv1i64, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv2i32, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv2i64, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv4i16, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv4i32, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv8i16, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLsv8i8, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv16i8, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv1i64, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv2i32, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv2i64, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv4i16, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv4i32, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv8i16, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHLuv8i8, ARM_INS_VRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRNv2i32, ARM_INS_VRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRNv4i16, ARM_INS_VRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRNv8i8, ARM_INS_VRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv16i8, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv1i64, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv2i32, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv2i64, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv4i16, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv4i32, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv8i16, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRsv8i8, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv16i8, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv1i64, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv2i32, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv2i64, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv4i16, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv4i32, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv8i16, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSHRuv8i8, ARM_INS_VRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTEd, ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTEfd, ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTEfq, ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTEhd, ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRSQRTEhq, ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRSQRTEq, ARM_INS_VRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTSfd, ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTSfq, ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSQRTShd, ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRSQRTShq, ARM_INS_VRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VRSRAsv16i8, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv1i64, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv2i32, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv2i64, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv4i16, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv4i32, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv8i16, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAsv8i8, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv16i8, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv1i64, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv2i32, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv2i64, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv4i16, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv4i32, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv8i16, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSRAuv8i8, ARM_INS_VRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSDOTD, ARM_INS_VSDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSDOTDI, ARM_INS_VSDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSDOTQ, ARM_INS_VSDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSDOTQI, ARM_INS_VSDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSELEQD, ARM_INS_VSELEQ, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSELEQH, ARM_INS_VSELEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSELEQS, ARM_INS_VSELEQ, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VSELGED, ARM_INS_VSELGE, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSELGEH, ARM_INS_VSELGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSELGES, ARM_INS_VSELGE, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VSELGTD, ARM_INS_VSELGT, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSELGTH, ARM_INS_VSELGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSELGTS, ARM_INS_VSELGT, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VSELVSD, ARM_INS_VSELVS, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSELVSH, ARM_INS_VSELVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSELVSS, ARM_INS_VSELVS, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 #endif }, { ARM_VSETLNi16, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSETLNi32, ARM_INS_FMDHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSETLNi8, ARM_INS_VMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLi16, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLi32, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLi8, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLsv2i64, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLsv4i32, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLsv8i16, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLuv2i64, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLuv4i32, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLLuv8i16, ARM_INS_VSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv16i8, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv1i64, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv2i32, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv2i64, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv4i16, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv4i32, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv8i16, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLiv8i8, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv16i8, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv1i64, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv2i32, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv2i64, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv4i16, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv4i32, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv8i16, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLsv8i8, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv16i8, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv1i64, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv2i32, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv2i64, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv4i16, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv4i32, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv8i16, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHLuv8i8, ARM_INS_VSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRNv2i32, ARM_INS_VSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRNv4i16, ARM_INS_VSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRNv8i8, ARM_INS_VSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv16i8, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv1i64, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv2i32, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv2i64, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv4i16, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv4i32, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv8i16, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRsv8i8, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv16i8, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv1i64, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv2i32, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv2i64, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv4i16, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv4i32, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv8i16, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHRuv8i8, ARM_INS_VSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSHTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSHTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSHTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSITOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSITOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSITOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSLIv16i8, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv1i64, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv2i32, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv2i64, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv4i16, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv4i32, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv8i16, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLIv8i8, ARM_INS_VSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSLTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSLTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSLTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSQRTD, ARM_INS_VSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSQRTH, ARM_INS_VSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSQRTS, ARM_INS_VSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSRAsv16i8, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv1i64, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv2i32, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv2i64, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv4i16, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv4i32, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv8i16, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAsv8i8, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv16i8, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv1i64, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv2i32, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv2i64, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv4i16, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv4i32, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv8i16, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRAuv8i8, ARM_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv16i8, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv1i64, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv2i32, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv2i64, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv4i16, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv4i32, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv8i16, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSRIv8i8, ARM_INS_VSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1LNd16, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1LNd16_UPD, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1LNd32, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1LNd32_UPD, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1LNd8, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1LNd8_UPD, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16Q, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16Qwb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16Qwb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16T, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16Twb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16Twb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d16wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32Q, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32Qwb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32Qwb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32T, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32Twb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32Twb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d32wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64Q, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64Qwb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64Qwb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64T, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64Twb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64Twb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d64wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8Q, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8Qwb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8Qwb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8T, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8Twb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8Twb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1d8wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q16, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q16wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q16wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q32, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q32wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q32wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q64, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q64wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q64wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q8, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q8wb_fixed, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST1q8wb_register, ARM_INS_VST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNd16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNd16_UPD, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNd32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNd32_UPD, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNd8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNd8_UPD, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNq16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNq16_UPD, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNq32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2LNq32_UPD, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b16wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b16wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b32wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b32wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b8wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2b8wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d16wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d16wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d32wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d32wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d8wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2d8wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q16, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q16wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q16wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q32, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q32wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q32wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q8, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q8wb_fixed, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST2q8wb_register, ARM_INS_VST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNd16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNd16_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNd32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNd32_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNd8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNd8_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNq16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNq16_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNq32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3LNq32_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3d16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3d16_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3d32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3d32_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3d8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3d8_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3q16, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3q16_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3q32, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3q32_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3q8, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST3q8_UPD, ARM_INS_VST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNd16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNd16_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNd32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNd32_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNd8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNd8_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNq16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNq16_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNq32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4LNq32_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4d16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4d16_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4d32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4d32_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4d8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4d8_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4q16, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4q16_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4q32, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4q32_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4q8, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VST4q8_UPD, ARM_INS_VST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTMDIA, ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTMSIA, ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTRD, ARM_INS_VSTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSTRH, ARM_INS_VSTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSTRS, ARM_INS_VSTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSUBD, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VSUBH, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSUBHNv2i32, ARM_INS_VSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBHNv4i16, ARM_INS_VSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBHNv8i8, ARM_INS_VSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBLsv2i64, ARM_INS_VSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBLsv4i32, ARM_INS_VSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBLsv8i16, ARM_INS_VSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBLuv2i64, ARM_INS_VSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBLuv4i32, ARM_INS_VSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBLuv8i16, ARM_INS_VSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBS, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VSUBWsv2i64, ARM_INS_VSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBWsv4i32, ARM_INS_VSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBWsv8i16, ARM_INS_VSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBWuv2i64, ARM_INS_VSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBWuv4i32, ARM_INS_VSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBWuv8i16, ARM_INS_VSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBfd, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBfq, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBhd, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSUBhq, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VSUBv16i8, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv1i64, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv2i32, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv2i64, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv4i16, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv4i32, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv8i16, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSUBv8i8, ARM_INS_VSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSWPd, ARM_INS_VSWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VSWPq, ARM_INS_VSWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBL1, ARM_INS_VTBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBL2, ARM_INS_VTBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBL3, ARM_INS_VTBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBL4, ARM_INS_VTBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBX1, ARM_INS_VTBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBX2, ARM_INS_VTBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBX3, ARM_INS_VTBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTBX4, ARM_INS_VTBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTOSHD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOSHH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOSHS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOSIRD, ARM_INS_VCVTR, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOSIRH, ARM_INS_VCVTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOSIRS, ARM_INS_VCVTR, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOSIZD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOSIZH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOSIZS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOSLD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOSLH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOSLS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOUHD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOUHH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOUHS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOUIRD, ARM_INS_VCVTR, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOUIRH, ARM_INS_VCVTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOUIRS, ARM_INS_VCVTR, #ifndef CAPSTONE_DIET { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOUIZD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOUIZH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOUIZS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTOULD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VTOULH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VTOULS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VTRNd16, ARM_INS_VTRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTRNd32, ARM_INS_VTRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTRNd8, ARM_INS_VTRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTRNq16, ARM_INS_VTRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTRNq32, ARM_INS_VTRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTRNq8, ARM_INS_VTRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTSTv16i8, ARM_INS_VTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTSTv2i32, ARM_INS_VTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTSTv4i16, ARM_INS_VTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTSTv4i32, ARM_INS_VTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTSTv8i16, ARM_INS_VTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VTSTv8i8, ARM_INS_VTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VUDOTD, ARM_INS_VUDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VUDOTDI, ARM_INS_VUDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VUDOTQ, ARM_INS_VUDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VUDOTQI, ARM_INS_VUDOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VUHTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VUHTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VUHTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VUITOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VUITOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VUITOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VULTOD, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 #endif }, { ARM_VULTOH, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_VULTOS, ARM_INS_VCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 #endif }, { ARM_VUZPd16, ARM_INS_VUZP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VUZPd8, ARM_INS_VUZP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VUZPq16, ARM_INS_VUZP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VUZPq32, ARM_INS_VUZP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VUZPq8, ARM_INS_VUZP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VZIPd16, ARM_INS_VZIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VZIPd8, ARM_INS_VZIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VZIPq16, ARM_INS_VZIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VZIPq32, ARM_INS_VZIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_VZIPq8, ARM_INS_VZIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 #endif }, { ARM_sysLDMDA, ARM_INS_LDMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMDA_UPD, ARM_INS_LDMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMDB, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMDB_UPD, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMIA, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMIA_UPD, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMIB, ARM_INS_LDMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysLDMIB_UPD, ARM_INS_LDMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMDA, ARM_INS_STMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMDA_UPD, ARM_INS_STMDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMDB, ARM_INS_STMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMDB_UPD, ARM_INS_STMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMIA, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMIA_UPD, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMIB, ARM_INS_STMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_sysSTMIB_UPD, ARM_INS_STMIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 #endif }, { ARM_t2ADCri, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADCrr, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADCrs, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADDri, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADDri12, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADDrr, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADDrs, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ADR, ARM_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ANDri, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ANDrr, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ANDrs, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ASRri, ARM_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ASRrr, ARM_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2B, ARM_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 #endif }, { ARM_t2BFC, ARM_INS_BFC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2BFI, ARM_INS_BFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2BICri, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2BICrr, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2BICrs, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2BXJ, ARM_INS_BXJ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, 0, 1 #endif }, { ARM_t2Bcc, ARM_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 #endif }, { ARM_t2CDP, ARM_INS_CDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_t2CDP2, ARM_INS_CDP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_t2CLREX, ARM_INS_CLREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_t2CLZ, ARM_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CMNri, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CMNzrr, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CMNzrs, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CMPri, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CMPrr, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CMPrs, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2CPS1p, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2CPS2p, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2CPS3p, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2CRC32B, ARM_INS_CRC32B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_t2CRC32CB, ARM_INS_CRC32CB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_t2CRC32CH, ARM_INS_CRC32CH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_t2CRC32CW, ARM_INS_CRC32CW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_t2CRC32H, ARM_INS_CRC32H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_t2CRC32W, ARM_INS_CRC32W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 #endif }, { ARM_t2DBG, ARM_INS_DBG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2DCPS1, ARM_INS_DCPS1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2DCPS2, ARM_INS_DCPS2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2DCPS3, ARM_INS_DCPS3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2DMB, ARM_INS_DMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 #endif }, { ARM_t2DSB, ARM_INS_DSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 #endif }, { ARM_t2EORri, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2EORrr, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2EORrs, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2HINT, ARM_INS_HINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2HVC, ARM_INS_HVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_t2ISB, ARM_INS_ISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 #endif }, { ARM_t2IT, ARM_INS_IT, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDA, ARM_INS_LDA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDAB, ARM_INS_LDAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDAEX, ARM_INS_LDAEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDAEXB, ARM_INS_LDAEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDAEXD, ARM_INS_LDAEXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDAEXH, ARM_INS_LDAEXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDAH, ARM_INS_LDAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2L_OPTION, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2L_POST, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2L_PRE, ARM_INS_LDC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2_OFFSET, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2_OPTION, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2_POST, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC2_PRE, ARM_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDCL_OFFSET, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDCL_OPTION, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDCL_POST, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDCL_PRE, ARM_INS_LDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC_OFFSET, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC_OPTION, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC_POST, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDC_PRE, ARM_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDMDB, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDMDB_UPD, ARM_INS_LDMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDMIA, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDMIA_UPD, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRBT, ARM_INS_LDRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRB_POST, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRB_PRE, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRBi12, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRBi8, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRBpci, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRBs, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRD_POST, ARM_INS_LDRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRD_PRE, ARM_INS_LDRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRDi8, ARM_INS_LDRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDREX, ARM_INS_LDREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDREXB, ARM_INS_LDREXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDREXD, ARM_INS_LDREXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2LDREXH, ARM_INS_LDREXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRHT, ARM_INS_LDRHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRH_POST, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRH_PRE, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRHi12, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRHi8, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRHpci, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRHs, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSBT, ARM_INS_LDRSBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSB_POST, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSB_PRE, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSBi12, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSBi8, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSBpci, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSBs, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSHT, ARM_INS_LDRSHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSH_POST, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSH_PRE, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSHi12, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSHi8, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSHpci, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRSHs, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRT, ARM_INS_LDRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDR_POST, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDR_PRE, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRi12, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRi8, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRpci, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LDRs, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LSLri, ARM_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LSLrr, ARM_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LSRri, ARM_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2LSRrr, ARM_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MCR, ARM_INS_MCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MCR2, ARM_INS_MCR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_t2MCRR, ARM_INS_MCRR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MCRR2, ARM_INS_MCRR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_t2MLA, ARM_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2MLS, ARM_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2MOVTi16, ARM_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MOVi, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MOVi16, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MOVr, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MOVsra_flag, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MOVsrl_flag, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MRC, ARM_INS_MRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MRC2, ARM_INS_MRC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_t2MRRC, ARM_INS_MRRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MRRC2, ARM_INS_MRRC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 #endif }, { ARM_t2MRS_AR, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2MRS_M, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 #endif }, { ARM_t2MRSbanked, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_t2MRSsys_AR, ARM_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2MSR_AR, ARM_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2MSR_M, ARM_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 #endif }, { ARM_t2MSRbanked, ARM_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 #endif }, { ARM_t2MUL, ARM_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MVNi, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MVNr, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2MVNs, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ORNri, ARM_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ORNrr, ARM_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ORNrs, ARM_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ORRri, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ORRrr, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2ORRrs, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PKHBT, ARM_INS_PKHBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PKHTB, ARM_INS_PKHTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PLDWi12, ARM_INS_PLDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 #endif }, { ARM_t2PLDWi8, ARM_INS_PLDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 #endif }, { ARM_t2PLDWs, ARM_INS_PLDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 #endif }, { ARM_t2PLDi12, ARM_INS_PLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PLDi8, ARM_INS_PLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PLDpci, ARM_INS_PLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PLDs, ARM_INS_PLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2PLIi12, ARM_INS_PLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_t2PLIi8, ARM_INS_PLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_t2PLIpci, ARM_INS_PLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_t2PLIs, ARM_INS_PLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 #endif }, { ARM_t2QADD, ARM_INS_QADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QADD16, ARM_INS_QADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QADD8, ARM_INS_QADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QASX, ARM_INS_QASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QDADD, ARM_INS_QDADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QDSUB, ARM_INS_QDSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QSAX, ARM_INS_QSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QSUB, ARM_INS_QSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QSUB16, ARM_INS_QSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2QSUB8, ARM_INS_QSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2RBIT, ARM_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2REV, ARM_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2REV16, ARM_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2REVSH, ARM_INS_REVSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2RFEDB, ARM_INS_RFEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2RFEDBW, ARM_INS_RFEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2RFEIA, ARM_INS_RFEIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2RFEIAW, ARM_INS_RFEIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2RORri, ARM_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2RORrr, ARM_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2RRX, ARM_INS_RRX, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2RSBri, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2RSBrr, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2RSBrs, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SADD16, ARM_INS_SADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SADD8, ARM_INS_SADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SASX, ARM_INS_SASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SBCri, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SBCrr, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SBCrs, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SBFX, ARM_INS_SBFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SDIV, ARM_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SEL, ARM_INS_SEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SETPAN, ARM_INS_SETPAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2SG, ARM_INS_SG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2SHADD16, ARM_INS_SHADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SHADD8, ARM_INS_SHADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SHASX, ARM_INS_SHASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SHSAX, ARM_INS_SHSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SHSUB16, ARM_INS_SHSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SHSUB8, ARM_INS_SHSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMC, ARM_INS_SMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 #endif }, { ARM_t2SMLABB, ARM_INS_SMLABB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMLABT, ARM_INS_SMLABT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMLAD, ARM_INS_SMLAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLADX, ARM_INS_SMLADX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLAL, ARM_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SMLALBB, ARM_INS_SMLALBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLALBT, ARM_INS_SMLALBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLALD, ARM_INS_SMLALD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLALDX, ARM_INS_SMLALDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLALTB, ARM_INS_SMLALTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLALTT, ARM_INS_SMLALTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLATB, ARM_INS_SMLATB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMLATT, ARM_INS_SMLATT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMLAWB, ARM_INS_SMLAWB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMLAWT, ARM_INS_SMLAWT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMLSD, ARM_INS_SMLSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLSDX, ARM_INS_SMLSDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLSLD, ARM_INS_SMLSLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMLSLDX, ARM_INS_SMLSLDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMMLA, ARM_INS_SMMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMMLAR, ARM_INS_SMMLAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMMLS, ARM_INS_SMMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 #endif }, { ARM_t2SMMLSR, ARM_INS_SMMLSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMMUL, ARM_INS_SMMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMMULR, ARM_INS_SMMULR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMUAD, ARM_INS_SMUAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMUADX, ARM_INS_SMUADX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMULBB, ARM_INS_SMULBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMULBT, ARM_INS_SMULBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMULL, ARM_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SMULTB, ARM_INS_SMULTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMULTT, ARM_INS_SMULTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMULWB, ARM_INS_SMULWB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMULWT, ARM_INS_SMULWT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMUSD, ARM_INS_SMUSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SMUSDX, ARM_INS_SMUSDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SRSDB, ARM_INS_SRSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2SRSDB_UPD, ARM_INS_SRSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2SRSIA, ARM_INS_SRSIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2SRSIA_UPD, ARM_INS_SRSIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2SSAT, ARM_INS_SSAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SSAT16, ARM_INS_SSAT16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SSAX, ARM_INS_SSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SSUB16, ARM_INS_SSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2SSUB8, ARM_INS_SSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2STC2L_OFFSET, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2L_OPTION, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2L_POST, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2L_PRE, ARM_INS_STC2L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2_OFFSET, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2_OPTION, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2_POST, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC2_PRE, ARM_INS_STC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STCL_OFFSET, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STCL_OPTION, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STCL_POST, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STCL_PRE, ARM_INS_STCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC_OFFSET, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC_OPTION, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC_POST, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STC_PRE, ARM_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STL, ARM_INS_STL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STLB, ARM_INS_STLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STLEX, ARM_INS_STLEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STLEXB, ARM_INS_STLEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STLEXD, ARM_INS_STLEXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STLEXH, ARM_INS_STLEXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STLH, ARM_INS_STLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_t2STMDB, ARM_INS_STMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STMDB_UPD, ARM_INS_STMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STMIA, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STMIA_UPD, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRBT, ARM_INS_STRBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRB_POST, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRB_PRE, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRBi12, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRBi8, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRBs, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRD_POST, ARM_INS_STRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRD_PRE, ARM_INS_STRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRDi8, ARM_INS_STRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STREX, ARM_INS_STREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STREXB, ARM_INS_STREXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STREXD, ARM_INS_STREXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2STREXH, ARM_INS_STREXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRHT, ARM_INS_STRHT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRH_POST, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRH_PRE, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRHi12, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRHi8, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRHs, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRT, ARM_INS_STRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STR_POST, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STR_PRE, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRi12, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRi8, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2STRs, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SUBS_PC_LR, ARM_INS_SUBS, #ifndef CAPSTONE_DIET { ARM_REG_SPSR, ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_REG_CPSR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_t2SUBri, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SUBri12, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SUBrr, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SUBrs, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SXTAB, ARM_INS_SXTAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SXTAB16, ARM_INS_SXTAB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SXTAH, ARM_INS_SXTAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SXTB, ARM_INS_SXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2SXTB16, ARM_INS_SXTB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0 #endif }, { ARM_t2SXTH, ARM_INS_SXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TBB, ARM_INS_TBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 #endif }, { ARM_t2TBH, ARM_INS_TBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 #endif }, { ARM_t2TEQri, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TEQrr, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TEQrs, ARM_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TSB, ARM_INS_TSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2TSTri, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TSTrr, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TSTrs, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2TT, ARM_INS_TT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2TTA, ARM_INS_TTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2TTAT, ARM_INS_TTAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2TTT, ARM_INS_TTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_t2UADD16, ARM_INS_UADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UADD8, ARM_INS_UADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UASX, ARM_INS_UASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UBFX, ARM_INS_UBFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UDF, ARM_INS_UDF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UDIV, ARM_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UHADD16, ARM_INS_UHADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UHADD8, ARM_INS_UHADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UHASX, ARM_INS_UHASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UHSAX, ARM_INS_UHSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UHSUB16, ARM_INS_UHSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UHSUB8, ARM_INS_UHSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UMAAL, ARM_INS_UMAAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UMLAL, ARM_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UMULL, ARM_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UQADD16, ARM_INS_UQADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UQADD8, ARM_INS_UQADD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UQASX, ARM_INS_UQASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UQSAX, ARM_INS_UQSAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UQSUB16, ARM_INS_UQSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UQSUB8, ARM_INS_UQSUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2USAD8, ARM_INS_USAD8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2USADA8, ARM_INS_USADA8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2USAT, ARM_INS_USAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2USAT16, ARM_INS_USAT16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2USAX, ARM_INS_USAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2USUB16, ARM_INS_USUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2USUB8, ARM_INS_USUB8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 #endif }, { ARM_t2UXTAB, ARM_INS_UXTAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UXTAB16, ARM_INS_UXTAB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UXTAH, ARM_INS_UXTAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UXTB, ARM_INS_UXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UXTB16, ARM_INS_UXTB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_t2UXTH, ARM_INS_UXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 #endif }, { ARM_tADC, ARM_INS_ADC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDhirr, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDi3, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDi8, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDrSP, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDrSPi, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDrr, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDspi, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADDspr, ARM_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tADR, ARM_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tAND, ARM_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tASRri, ARM_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tASRrr, ARM_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tB, ARM_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 #endif }, { ARM_tBIC, ARM_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tBKPT, ARM_INS_BKPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tBL, ARM_INS_BL, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0 #endif }, { ARM_tBLXNSr, ARM_INS_BLXNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_tBLXi, ARM_INS_BLX, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0 #endif }, { ARM_tBLXr, ARM_INS_BLX, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_CALL, 0 }, 0, 1 #endif }, { ARM_tBX, ARM_INS_BX, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 #endif }, { ARM_tBXNS, ARM_INS_BXNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { ARM_tBcc, ARM_INS_B, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 #endif }, { ARM_tCBNZ, ARM_INS_CBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 #endif }, { ARM_tCBZ, ARM_INS_CBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0 #endif }, { ARM_tCMNz, ARM_INS_CMN, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tCMPhir, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tCMPi8, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tCMPr, ARM_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tCPS, ARM_INS_CPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tEOR, ARM_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tHINT, ARM_INS_HINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 #endif }, { ARM_tHLT, ARM_INS_HLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 #endif }, { ARM_tLDMIA, ARM_INS_LDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRBi, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRBr, ARM_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRHi, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRHr, ARM_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRSB, ARM_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRSH, ARM_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRi, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRpci, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRr, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLDRspi, ARM_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLSLri, ARM_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLSLrr, ARM_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLSRri, ARM_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tLSRrr, ARM_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tMOVSr, ARM_INS_MOVS, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tMOVi8, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tMOVr, ARM_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tMUL, ARM_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tMVN, ARM_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tORR, ARM_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tPOP, ARM_INS_POP, #ifndef CAPSTONE_DIET { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tPUSH, ARM_INS_PUSH, #ifndef CAPSTONE_DIET { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tREV, ARM_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_tREV16, ARM_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_tREVSH, ARM_INS_REVSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_tROR, ARM_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tRSB, ARM_INS_RSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSBC, ARM_INS_SBC, #ifndef CAPSTONE_DIET { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSETEND, ARM_INS_SETEND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0 }, 0, 0 #endif }, { ARM_tSTMIA_UPD, ARM_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRBi, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRBr, ARM_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRHi, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRHr, ARM_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRi, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRr, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSTRspi, ARM_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSUBi3, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSUBi8, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSUBrr, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSUBspi, ARM_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tSVC, ARM_INS_SVC, #ifndef CAPSTONE_DIET { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_INT, 0 }, 0, 0 #endif }, { ARM_tSXTB, ARM_INS_SXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_tSXTH, ARM_INS_SXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_tTRAP, ARM_INS_TRAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 #endif }, { ARM_tTST, ARM_INS_TST, #ifndef CAPSTONE_DIET { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 #endif }, { ARM_tUDF, ARM_INS_UDF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 #endif }, { ARM_tUXTB, ARM_INS_UXTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, { ARM_tUXTH, ARM_INS_UXTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/ARM/ARMMappingInsnName.inc000064400000000000000000000316230072674642500216230ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ "adc", // ARM_INS_ADC, "add", // ARM_INS_ADD, "addw", // ARM_INS_ADDW, "adr", // ARM_INS_ADR, "aesd", // ARM_INS_AESD, "aese", // ARM_INS_AESE, "aesimc", // ARM_INS_AESIMC, "aesmc", // ARM_INS_AESMC, "and", // ARM_INS_AND, "asr", // ARM_INS_ASR, "b", // ARM_INS_B, "bfc", // ARM_INS_BFC, "bfi", // ARM_INS_BFI, "bic", // ARM_INS_BIC, "bkpt", // ARM_INS_BKPT, "bl", // ARM_INS_BL, "blx", // ARM_INS_BLX, "blxns", // ARM_INS_BLXNS, "bx", // ARM_INS_BX, "bxj", // ARM_INS_BXJ, "bxns", // ARM_INS_BXNS, "cbnz", // ARM_INS_CBNZ, "cbz", // ARM_INS_CBZ, "cdp", // ARM_INS_CDP, "cdp2", // ARM_INS_CDP2, "clrex", // ARM_INS_CLREX, "clz", // ARM_INS_CLZ, "cmn", // ARM_INS_CMN, "cmp", // ARM_INS_CMP, "cps", // ARM_INS_CPS, "crc32b", // ARM_INS_CRC32B, "crc32cb", // ARM_INS_CRC32CB, "crc32ch", // ARM_INS_CRC32CH, "crc32cw", // ARM_INS_CRC32CW, "crc32h", // ARM_INS_CRC32H, "crc32w", // ARM_INS_CRC32W, "csdb", // ARM_INS_CSDB, "dbg", // ARM_INS_DBG, "dcps1", // ARM_INS_DCPS1, "dcps2", // ARM_INS_DCPS2, "dcps3", // ARM_INS_DCPS3, "dfb", // ARM_INS_DFB, "dmb", // ARM_INS_DMB, "dsb", // ARM_INS_DSB, "eor", // ARM_INS_EOR, "eret", // ARM_INS_ERET, "esb", // ARM_INS_ESB, "faddd", // ARM_INS_FADDD, "fadds", // ARM_INS_FADDS, "fcmpzd", // ARM_INS_FCMPZD, "fcmpzs", // ARM_INS_FCMPZS, "fconstd", // ARM_INS_FCONSTD, "fconsts", // ARM_INS_FCONSTS, "fldmdbx", // ARM_INS_FLDMDBX, "fldmiax", // ARM_INS_FLDMIAX, "fmdhr", // ARM_INS_FMDHR, "fmdlr", // ARM_INS_FMDLR, "fmstat", // ARM_INS_FMSTAT, "fstmdbx", // ARM_INS_FSTMDBX, "fstmiax", // ARM_INS_FSTMIAX, "fsubd", // ARM_INS_FSUBD, "fsubs", // ARM_INS_FSUBS, "hint", // ARM_INS_HINT, "hlt", // ARM_INS_HLT, "hvc", // ARM_INS_HVC, "isb", // ARM_INS_ISB, "it", // ARM_INS_IT, "lda", // ARM_INS_LDA, "ldab", // ARM_INS_LDAB, "ldaex", // ARM_INS_LDAEX, "ldaexb", // ARM_INS_LDAEXB, "ldaexd", // ARM_INS_LDAEXD, "ldaexh", // ARM_INS_LDAEXH, "ldah", // ARM_INS_LDAH, "ldc", // ARM_INS_LDC, "ldc2", // ARM_INS_LDC2, "ldc2l", // ARM_INS_LDC2L, "ldcl", // ARM_INS_LDCL, "ldm", // ARM_INS_LDM, "ldmda", // ARM_INS_LDMDA, "ldmdb", // ARM_INS_LDMDB, "ldmib", // ARM_INS_LDMIB, "ldr", // ARM_INS_LDR, "ldrb", // ARM_INS_LDRB, "ldrbt", // ARM_INS_LDRBT, "ldrd", // ARM_INS_LDRD, "ldrex", // ARM_INS_LDREX, "ldrexb", // ARM_INS_LDREXB, "ldrexd", // ARM_INS_LDREXD, "ldrexh", // ARM_INS_LDREXH, "ldrh", // ARM_INS_LDRH, "ldrht", // ARM_INS_LDRHT, "ldrsb", // ARM_INS_LDRSB, "ldrsbt", // ARM_INS_LDRSBT, "ldrsh", // ARM_INS_LDRSH, "ldrsht", // ARM_INS_LDRSHT, "ldrt", // ARM_INS_LDRT, "lsl", // ARM_INS_LSL, "lsr", // ARM_INS_LSR, "mcr", // ARM_INS_MCR, "mcr2", // ARM_INS_MCR2, "mcrr", // ARM_INS_MCRR, "mcrr2", // ARM_INS_MCRR2, "mla", // ARM_INS_MLA, "mls", // ARM_INS_MLS, "mov", // ARM_INS_MOV, "movs", // ARM_INS_MOVS, "movt", // ARM_INS_MOVT, "movw", // ARM_INS_MOVW, "mrc", // ARM_INS_MRC, "mrc2", // ARM_INS_MRC2, "mrrc", // ARM_INS_MRRC, "mrrc2", // ARM_INS_MRRC2, "mrs", // ARM_INS_MRS, "msr", // ARM_INS_MSR, "mul", // ARM_INS_MUL, "mvn", // ARM_INS_MVN, "neg", // ARM_INS_NEG, "nop", // ARM_INS_NOP, "orn", // ARM_INS_ORN, "orr", // ARM_INS_ORR, "pkhbt", // ARM_INS_PKHBT, "pkhtb", // ARM_INS_PKHTB, "pld", // ARM_INS_PLD, "pldw", // ARM_INS_PLDW, "pli", // ARM_INS_PLI, "pop", // ARM_INS_POP, "push", // ARM_INS_PUSH, "qadd", // ARM_INS_QADD, "qadd16", // ARM_INS_QADD16, "qadd8", // ARM_INS_QADD8, "qasx", // ARM_INS_QASX, "qdadd", // ARM_INS_QDADD, "qdsub", // ARM_INS_QDSUB, "qsax", // ARM_INS_QSAX, "qsub", // ARM_INS_QSUB, "qsub16", // ARM_INS_QSUB16, "qsub8", // ARM_INS_QSUB8, "rbit", // ARM_INS_RBIT, "rev", // ARM_INS_REV, "rev16", // ARM_INS_REV16, "revsh", // ARM_INS_REVSH, "rfeda", // ARM_INS_RFEDA, "rfedb", // ARM_INS_RFEDB, "rfeia", // ARM_INS_RFEIA, "rfeib", // ARM_INS_RFEIB, "ror", // ARM_INS_ROR, "rrx", // ARM_INS_RRX, "rsb", // ARM_INS_RSB, "rsc", // ARM_INS_RSC, "sadd16", // ARM_INS_SADD16, "sadd8", // ARM_INS_SADD8, "sasx", // ARM_INS_SASX, "sbc", // ARM_INS_SBC, "sbfx", // ARM_INS_SBFX, "sdiv", // ARM_INS_SDIV, "sel", // ARM_INS_SEL, "setend", // ARM_INS_SETEND, "setpan", // ARM_INS_SETPAN, "sev", // ARM_INS_SEV, "sevl", // ARM_INS_SEVL, "sg", // ARM_INS_SG, "sha1c", // ARM_INS_SHA1C, "sha1h", // ARM_INS_SHA1H, "sha1m", // ARM_INS_SHA1M, "sha1p", // ARM_INS_SHA1P, "sha1su0", // ARM_INS_SHA1SU0, "sha1su1", // ARM_INS_SHA1SU1, "sha256h", // ARM_INS_SHA256H, "sha256h2", // ARM_INS_SHA256H2, "sha256su0", // ARM_INS_SHA256SU0, "sha256su1", // ARM_INS_SHA256SU1, "shadd16", // ARM_INS_SHADD16, "shadd8", // ARM_INS_SHADD8, "shasx", // ARM_INS_SHASX, "shsax", // ARM_INS_SHSAX, "shsub16", // ARM_INS_SHSUB16, "shsub8", // ARM_INS_SHSUB8, "smc", // ARM_INS_SMC, "smlabb", // ARM_INS_SMLABB, "smlabt", // ARM_INS_SMLABT, "smlad", // ARM_INS_SMLAD, "smladx", // ARM_INS_SMLADX, "smlal", // ARM_INS_SMLAL, "smlalbb", // ARM_INS_SMLALBB, "smlalbt", // ARM_INS_SMLALBT, "smlald", // ARM_INS_SMLALD, "smlaldx", // ARM_INS_SMLALDX, "smlaltb", // ARM_INS_SMLALTB, "smlaltt", // ARM_INS_SMLALTT, "smlatb", // ARM_INS_SMLATB, "smlatt", // ARM_INS_SMLATT, "smlawb", // ARM_INS_SMLAWB, "smlawt", // ARM_INS_SMLAWT, "smlsd", // ARM_INS_SMLSD, "smlsdx", // ARM_INS_SMLSDX, "smlsld", // ARM_INS_SMLSLD, "smlsldx", // ARM_INS_SMLSLDX, "smmla", // ARM_INS_SMMLA, "smmlar", // ARM_INS_SMMLAR, "smmls", // ARM_INS_SMMLS, "smmlsr", // ARM_INS_SMMLSR, "smmul", // ARM_INS_SMMUL, "smmulr", // ARM_INS_SMMULR, "smuad", // ARM_INS_SMUAD, "smuadx", // ARM_INS_SMUADX, "smulbb", // ARM_INS_SMULBB, "smulbt", // ARM_INS_SMULBT, "smull", // ARM_INS_SMULL, "smultb", // ARM_INS_SMULTB, "smultt", // ARM_INS_SMULTT, "smulwb", // ARM_INS_SMULWB, "smulwt", // ARM_INS_SMULWT, "smusd", // ARM_INS_SMUSD, "smusdx", // ARM_INS_SMUSDX, "srsda", // ARM_INS_SRSDA, "srsdb", // ARM_INS_SRSDB, "srsia", // ARM_INS_SRSIA, "srsib", // ARM_INS_SRSIB, "ssat", // ARM_INS_SSAT, "ssat16", // ARM_INS_SSAT16, "ssax", // ARM_INS_SSAX, "ssub16", // ARM_INS_SSUB16, "ssub8", // ARM_INS_SSUB8, "stc", // ARM_INS_STC, "stc2", // ARM_INS_STC2, "stc2l", // ARM_INS_STC2L, "stcl", // ARM_INS_STCL, "stl", // ARM_INS_STL, "stlb", // ARM_INS_STLB, "stlex", // ARM_INS_STLEX, "stlexb", // ARM_INS_STLEXB, "stlexd", // ARM_INS_STLEXD, "stlexh", // ARM_INS_STLEXH, "stlh", // ARM_INS_STLH, "stm", // ARM_INS_STM, "stmda", // ARM_INS_STMDA, "stmdb", // ARM_INS_STMDB, "stmib", // ARM_INS_STMIB, "str", // ARM_INS_STR, "strb", // ARM_INS_STRB, "strbt", // ARM_INS_STRBT, "strd", // ARM_INS_STRD, "strex", // ARM_INS_STREX, "strexb", // ARM_INS_STREXB, "strexd", // ARM_INS_STREXD, "strexh", // ARM_INS_STREXH, "strh", // ARM_INS_STRH, "strht", // ARM_INS_STRHT, "strt", // ARM_INS_STRT, "sub", // ARM_INS_SUB, "subs", // ARM_INS_SUBS, "subw", // ARM_INS_SUBW, "svc", // ARM_INS_SVC, "swp", // ARM_INS_SWP, "swpb", // ARM_INS_SWPB, "sxtab", // ARM_INS_SXTAB, "sxtab16", // ARM_INS_SXTAB16, "sxtah", // ARM_INS_SXTAH, "sxtb", // ARM_INS_SXTB, "sxtb16", // ARM_INS_SXTB16, "sxth", // ARM_INS_SXTH, "tbb", // ARM_INS_TBB, "tbh", // ARM_INS_TBH, "teq", // ARM_INS_TEQ, "trap", // ARM_INS_TRAP, "tsb", // ARM_INS_TSB, "tst", // ARM_INS_TST, "tt", // ARM_INS_TT, "tta", // ARM_INS_TTA, "ttat", // ARM_INS_TTAT, "ttt", // ARM_INS_TTT, "uadd16", // ARM_INS_UADD16, "uadd8", // ARM_INS_UADD8, "uasx", // ARM_INS_UASX, "ubfx", // ARM_INS_UBFX, "udf", // ARM_INS_UDF, "udiv", // ARM_INS_UDIV, "uhadd16", // ARM_INS_UHADD16, "uhadd8", // ARM_INS_UHADD8, "uhasx", // ARM_INS_UHASX, "uhsax", // ARM_INS_UHSAX, "uhsub16", // ARM_INS_UHSUB16, "uhsub8", // ARM_INS_UHSUB8, "umaal", // ARM_INS_UMAAL, "umlal", // ARM_INS_UMLAL, "umull", // ARM_INS_UMULL, "uqadd16", // ARM_INS_UQADD16, "uqadd8", // ARM_INS_UQADD8, "uqasx", // ARM_INS_UQASX, "uqsax", // ARM_INS_UQSAX, "uqsub16", // ARM_INS_UQSUB16, "uqsub8", // ARM_INS_UQSUB8, "usad8", // ARM_INS_USAD8, "usada8", // ARM_INS_USADA8, "usat", // ARM_INS_USAT, "usat16", // ARM_INS_USAT16, "usax", // ARM_INS_USAX, "usub16", // ARM_INS_USUB16, "usub8", // ARM_INS_USUB8, "uxtab", // ARM_INS_UXTAB, "uxtab16", // ARM_INS_UXTAB16, "uxtah", // ARM_INS_UXTAH, "uxtb", // ARM_INS_UXTB, "uxtb16", // ARM_INS_UXTB16, "uxth", // ARM_INS_UXTH, "vaba", // ARM_INS_VABA, "vabal", // ARM_INS_VABAL, "vabd", // ARM_INS_VABD, "vabdl", // ARM_INS_VABDL, "vabs", // ARM_INS_VABS, "vacge", // ARM_INS_VACGE, "vacgt", // ARM_INS_VACGT, "vacle", // ARM_INS_VACLE, "vaclt", // ARM_INS_VACLT, "vadd", // ARM_INS_VADD, "vaddhn", // ARM_INS_VADDHN, "vaddl", // ARM_INS_VADDL, "vaddw", // ARM_INS_VADDW, "vand", // ARM_INS_VAND, "vbic", // ARM_INS_VBIC, "vbif", // ARM_INS_VBIF, "vbit", // ARM_INS_VBIT, "vbsl", // ARM_INS_VBSL, "vcadd", // ARM_INS_VCADD, "vceq", // ARM_INS_VCEQ, "vcge", // ARM_INS_VCGE, "vcgt", // ARM_INS_VCGT, "vcle", // ARM_INS_VCLE, "vcls", // ARM_INS_VCLS, "vclt", // ARM_INS_VCLT, "vclz", // ARM_INS_VCLZ, "vcmla", // ARM_INS_VCMLA, "vcmp", // ARM_INS_VCMP, "vcmpe", // ARM_INS_VCMPE, "vcnt", // ARM_INS_VCNT, "vcvt", // ARM_INS_VCVT, "vcvta", // ARM_INS_VCVTA, "vcvtb", // ARM_INS_VCVTB, "vcvtm", // ARM_INS_VCVTM, "vcvtn", // ARM_INS_VCVTN, "vcvtp", // ARM_INS_VCVTP, "vcvtr", // ARM_INS_VCVTR, "vcvtt", // ARM_INS_VCVTT, "vdiv", // ARM_INS_VDIV, "vdup", // ARM_INS_VDUP, "veor", // ARM_INS_VEOR, "vext", // ARM_INS_VEXT, "vfma", // ARM_INS_VFMA, "vfms", // ARM_INS_VFMS, "vfnma", // ARM_INS_VFNMA, "vfnms", // ARM_INS_VFNMS, "vhadd", // ARM_INS_VHADD, "vhsub", // ARM_INS_VHSUB, "vins", // ARM_INS_VINS, "vjcvt", // ARM_INS_VJCVT, "vld1", // ARM_INS_VLD1, "vld2", // ARM_INS_VLD2, "vld3", // ARM_INS_VLD3, "vld4", // ARM_INS_VLD4, "vldmdb", // ARM_INS_VLDMDB, "vldmia", // ARM_INS_VLDMIA, "vldr", // ARM_INS_VLDR, "vlldm", // ARM_INS_VLLDM, "vlstm", // ARM_INS_VLSTM, "vmax", // ARM_INS_VMAX, "vmaxnm", // ARM_INS_VMAXNM, "vmin", // ARM_INS_VMIN, "vminnm", // ARM_INS_VMINNM, "vmla", // ARM_INS_VMLA, "vmlal", // ARM_INS_VMLAL, "vmls", // ARM_INS_VMLS, "vmlsl", // ARM_INS_VMLSL, "vmov", // ARM_INS_VMOV, "vmovl", // ARM_INS_VMOVL, "vmovn", // ARM_INS_VMOVN, "vmovx", // ARM_INS_VMOVX, "vmrs", // ARM_INS_VMRS, "vmsr", // ARM_INS_VMSR, "vmul", // ARM_INS_VMUL, "vmull", // ARM_INS_VMULL, "vmvn", // ARM_INS_VMVN, "vneg", // ARM_INS_VNEG, "vnmla", // ARM_INS_VNMLA, "vnmls", // ARM_INS_VNMLS, "vnmul", // ARM_INS_VNMUL, "vorn", // ARM_INS_VORN, "vorr", // ARM_INS_VORR, "vpadal", // ARM_INS_VPADAL, "vpadd", // ARM_INS_VPADD, "vpaddl", // ARM_INS_VPADDL, "vpmax", // ARM_INS_VPMAX, "vpmin", // ARM_INS_VPMIN, "vpop", // ARM_INS_VPOP, "vpush", // ARM_INS_VPUSH, "vqabs", // ARM_INS_VQABS, "vqadd", // ARM_INS_VQADD, "vqdmlal", // ARM_INS_VQDMLAL, "vqdmlsl", // ARM_INS_VQDMLSL, "vqdmulh", // ARM_INS_VQDMULH, "vqdmull", // ARM_INS_VQDMULL, "vqmovn", // ARM_INS_VQMOVN, "vqmovun", // ARM_INS_VQMOVUN, "vqneg", // ARM_INS_VQNEG, "vqrdmlah", // ARM_INS_VQRDMLAH, "vqrdmlsh", // ARM_INS_VQRDMLSH, "vqrdmulh", // ARM_INS_VQRDMULH, "vqrshl", // ARM_INS_VQRSHL, "vqrshrn", // ARM_INS_VQRSHRN, "vqrshrun", // ARM_INS_VQRSHRUN, "vqshl", // ARM_INS_VQSHL, "vqshlu", // ARM_INS_VQSHLU, "vqshrn", // ARM_INS_VQSHRN, "vqshrun", // ARM_INS_VQSHRUN, "vqsub", // ARM_INS_VQSUB, "vraddhn", // ARM_INS_VRADDHN, "vrecpe", // ARM_INS_VRECPE, "vrecps", // ARM_INS_VRECPS, "vrev16", // ARM_INS_VREV16, "vrev32", // ARM_INS_VREV32, "vrev64", // ARM_INS_VREV64, "vrhadd", // ARM_INS_VRHADD, "vrinta", // ARM_INS_VRINTA, "vrintm", // ARM_INS_VRINTM, "vrintn", // ARM_INS_VRINTN, "vrintp", // ARM_INS_VRINTP, "vrintr", // ARM_INS_VRINTR, "vrintx", // ARM_INS_VRINTX, "vrintz", // ARM_INS_VRINTZ, "vrshl", // ARM_INS_VRSHL, "vrshr", // ARM_INS_VRSHR, "vrshrn", // ARM_INS_VRSHRN, "vrsqrte", // ARM_INS_VRSQRTE, "vrsqrts", // ARM_INS_VRSQRTS, "vrsra", // ARM_INS_VRSRA, "vrsubhn", // ARM_INS_VRSUBHN, "vsdot", // ARM_INS_VSDOT, "vseleq", // ARM_INS_VSELEQ, "vselge", // ARM_INS_VSELGE, "vselgt", // ARM_INS_VSELGT, "vselvs", // ARM_INS_VSELVS, "vshl", // ARM_INS_VSHL, "vshll", // ARM_INS_VSHLL, "vshr", // ARM_INS_VSHR, "vshrn", // ARM_INS_VSHRN, "vsli", // ARM_INS_VSLI, "vsqrt", // ARM_INS_VSQRT, "vsra", // ARM_INS_VSRA, "vsri", // ARM_INS_VSRI, "vst1", // ARM_INS_VST1, "vst2", // ARM_INS_VST2, "vst3", // ARM_INS_VST3, "vst4", // ARM_INS_VST4, "vstmdb", // ARM_INS_VSTMDB, "vstmia", // ARM_INS_VSTMIA, "vstr", // ARM_INS_VSTR, "vsub", // ARM_INS_VSUB, "vsubhn", // ARM_INS_VSUBHN, "vsubl", // ARM_INS_VSUBL, "vsubw", // ARM_INS_VSUBW, "vswp", // ARM_INS_VSWP, "vtbl", // ARM_INS_VTBL, "vtbx", // ARM_INS_VTBX, "vtrn", // ARM_INS_VTRN, "vtst", // ARM_INS_VTST, "vudot", // ARM_INS_VUDOT, "vuzp", // ARM_INS_VUZP, "vzip", // ARM_INS_VZIP, "wfe", // ARM_INS_WFE, "wfi", // ARM_INS_WFI, "yield", // ARM_INS_YIELD, capstone-sys-0.15.0/capstone/arch/ARM/ARMMappingInsnOp.inc000064400000000000000000006514040072674642500213260ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { /* ARM_ASRi, ARM_INS_ASR: asr */ { 0 } }, { /* ARM_ASRr, ARM_INS_ASR: asr */ { 0 } }, { /* ARM_ITasm, ARM_INS_IT: it */ { 0 } }, { /* ARM_LDRBT_POST, ARM_INS_LDRBT: ldrbt */ { 0 } }, { /* ARM_LDRConstPool, ARM_INS_LDR: ldr */ { 0 } }, { /* ARM_LDRT_POST, ARM_INS_LDRT: ldrt */ { 0 } }, { /* ARM_LSLi, ARM_INS_LSL: lsl */ { 0 } }, { /* ARM_LSLr, ARM_INS_LSL: lsl */ { 0 } }, { /* ARM_LSRi, ARM_INS_LSR: lsr */ { 0 } }, { /* ARM_LSRr, ARM_INS_LSR: lsr */ { 0 } }, { /* ARM_RORi, ARM_INS_ROR: ror */ { 0 } }, { /* ARM_RORr, ARM_INS_ROR: ror */ { 0 } }, { /* ARM_RRXi, ARM_INS_RRX: rrx */ { 0 } }, { /* ARM_STRBT_POST, ARM_INS_STRBT: strbt */ { 0 } }, { /* ARM_STRT_POST, ARM_INS_STRT: strt */ { 0 } }, { /* ARM_VLD1LNdAsm_16, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdAsm_32, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdAsm_8, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdWB_fixed_Asm_16, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdWB_fixed_Asm_32, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdWB_fixed_Asm_8, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdWB_register_Asm_16, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdWB_register_Asm_32, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD1LNdWB_register_Asm_8, ARM_INS_VLD1: vld1 */ { 0 } }, { /* ARM_VLD2LNdAsm_16, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdAsm_32, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdAsm_8, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdWB_fixed_Asm_8, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdWB_register_Asm_16, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdWB_register_Asm_32, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNdWB_register_Asm_8, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNqAsm_16, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNqAsm_32, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNqWB_fixed_Asm_16, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNqWB_fixed_Asm_32, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNqWB_register_Asm_16, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD2LNqWB_register_Asm_32, ARM_INS_VLD2: vld2 */ { 0 } }, { /* ARM_VLD3DUPdAsm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdAsm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdAsm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqAsm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqAsm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqAsm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3DUPqWB_register_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdAsm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdAsm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdAsm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdWB_register_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdWB_register_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNdWB_register_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNqAsm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNqAsm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNqWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNqWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNqWB_register_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3LNqWB_register_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dAsm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dAsm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dAsm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dWB_register_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dWB_register_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3dWB_register_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qAsm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qAsm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qAsm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qWB_fixed_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qWB_fixed_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qWB_fixed_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qWB_register_Asm_16, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qWB_register_Asm_32, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD3qWB_register_Asm_8, ARM_INS_VLD3: vld3 */ { 0 } }, { /* ARM_VLD4DUPdAsm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdAsm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdAsm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqAsm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqAsm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqAsm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4DUPqWB_register_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdAsm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdAsm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdAsm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdWB_register_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdWB_register_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNdWB_register_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNqAsm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNqAsm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNqWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNqWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNqWB_register_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4LNqWB_register_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dAsm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dAsm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dAsm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dWB_register_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dWB_register_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4dWB_register_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qAsm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qAsm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qAsm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qWB_fixed_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qWB_fixed_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qWB_fixed_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qWB_register_Asm_16, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qWB_register_Asm_32, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VLD4qWB_register_Asm_8, ARM_INS_VLD4: vld4 */ { 0 } }, { /* ARM_VST1LNdAsm_16, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdAsm_32, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdAsm_8, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdWB_fixed_Asm_16, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdWB_fixed_Asm_32, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdWB_fixed_Asm_8, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdWB_register_Asm_16, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdWB_register_Asm_32, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST1LNdWB_register_Asm_8, ARM_INS_VST1: vst1 */ { 0 } }, { /* ARM_VST2LNdAsm_16, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdAsm_32, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdAsm_8, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdWB_fixed_Asm_8, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdWB_register_Asm_16, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdWB_register_Asm_32, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNdWB_register_Asm_8, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNqAsm_16, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNqAsm_32, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNqWB_fixed_Asm_16, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNqWB_fixed_Asm_32, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNqWB_register_Asm_16, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST2LNqWB_register_Asm_32, ARM_INS_VST2: vst2 */ { 0 } }, { /* ARM_VST3LNdAsm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdAsm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdAsm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdWB_register_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdWB_register_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNdWB_register_Asm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNqAsm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNqAsm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNqWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNqWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNqWB_register_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3LNqWB_register_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dAsm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dAsm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dAsm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dWB_register_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dWB_register_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3dWB_register_Asm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qAsm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qAsm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qAsm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qWB_fixed_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qWB_fixed_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qWB_fixed_Asm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qWB_register_Asm_16, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qWB_register_Asm_32, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST3qWB_register_Asm_8, ARM_INS_VST3: vst3 */ { 0 } }, { /* ARM_VST4LNdAsm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdAsm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdAsm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdWB_register_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdWB_register_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNdWB_register_Asm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNqAsm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNqAsm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNqWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNqWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNqWB_register_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4LNqWB_register_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dAsm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dAsm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dAsm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dWB_register_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dWB_register_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4dWB_register_Asm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qAsm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qAsm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qAsm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qWB_fixed_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qWB_fixed_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qWB_fixed_Asm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qWB_register_Asm_16, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qWB_register_Asm_32, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_VST4qWB_register_Asm_8, ARM_INS_VST4: vst4 */ { 0 } }, { /* ARM_t2LDRBpcrel, ARM_INS_LDRB: ldrb */ { 0 } }, { /* ARM_t2LDRConstPool, ARM_INS_LDR: ldr */ { 0 } }, { /* ARM_t2LDRHpcrel, ARM_INS_LDRH: ldrh */ { 0 } }, { /* ARM_t2LDRSBpcrel, ARM_INS_LDRSB: ldrsb */ { 0 } }, { /* ARM_t2LDRSHpcrel, ARM_INS_LDRSH: ldrsh */ { 0 } }, { /* ARM_t2LDRpcrel, ARM_INS_LDR: ldr */ { 0 } }, { /* ARM_t2MOVSsi, ARM_INS_MOVS: movs */ { 0 } }, { /* ARM_t2MOVSsr, ARM_INS_MOVS: movs */ { 0 } }, { /* ARM_t2MOVsi, ARM_INS_MOV: mov */ { 0 } }, { /* ARM_t2MOVsr, ARM_INS_MOV: mov */ { 0 } }, { /* ARM_tLDRConstPool, ARM_INS_LDR: ldr */ { 0 } }, { /* ARM_ADCri, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ADCrr, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ADCrsi, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ADCrsr, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ADDri, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ADDrr, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ADDrsi, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ADDrsr, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ADR, ARM_INS_ADR: adr */ { CS_AC_WRITE, 0 } }, { /* ARM_AESD, ARM_INS_AESD: aesd */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_AESE, ARM_INS_AESE: aese */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_AESIMC, ARM_INS_AESIMC: aesimc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_AESMC, ARM_INS_AESMC: aesmc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ANDri, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ANDrr, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ANDrsi, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ANDrsr, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_BFC, ARM_INS_BFC: bfc */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_BFI, ARM_INS_BFI: bfi */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_BICri, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_BICrr, ARM_INS_BIC: bic */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_BICrsi, ARM_INS_BIC: bic */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_BICrsr, ARM_INS_BIC: bic */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_BKPT, ARM_INS_BKPT: bkpt */ { 0 } }, { /* ARM_BL, ARM_INS_BL: bl */ { 0 } }, { /* ARM_BLX, ARM_INS_BLX: blx */ { CS_AC_READ, 0 } }, { /* ARM_BLX_pred, ARM_INS_BLX: blx */ { CS_AC_READ, 0 } }, { /* ARM_BLXi, ARM_INS_BLX: blx */ { 0 } }, { /* ARM_BL_pred, ARM_INS_BL: bl */ { 0 } }, { /* ARM_BX, ARM_INS_BX: bx */ { CS_AC_READ, 0 } }, { /* ARM_BXJ, ARM_INS_BXJ: bxj */ { CS_AC_READ, 0 } }, { /* ARM_BX_RET, ARM_INS_BX: bx */ { 0 } }, { /* ARM_BX_pred, ARM_INS_BX: bx */ { CS_AC_READ, 0 } }, { /* ARM_Bcc, ARM_INS_B: b */ { 0 } }, { /* ARM_CDP, ARM_INS_CDP: cdp */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_CDP2, ARM_INS_CDP2: cdp2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_CLREX, ARM_INS_CLREX: clrex */ { 0 } }, { /* ARM_CLZ, ARM_INS_CLZ: clz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_CMNri, ARM_INS_CMN: cmn */ { CS_AC_READ, 0 } }, { /* ARM_CMNzrr, ARM_INS_CMN: cmn */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CMNzrsi, ARM_INS_CMN: cmn */ { CS_AC_READ, 0 } }, { /* ARM_CMNzrsr, ARM_INS_CMN: cmn */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CMPri, ARM_INS_CMN: cmn */ { CS_AC_READ, 0 } }, { /* ARM_CMPrr, ARM_INS_CMP: cmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CMPrsi, ARM_INS_CMP: cmp */ { CS_AC_READ, 0 } }, { /* ARM_CMPrsr, ARM_INS_CMP: cmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CPS1p, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_CPS2p, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_CPS3p, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_CRC32B, ARM_INS_CRC32B: crc32b */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CRC32H, ARM_INS_CRC32H: crc32h */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_CRC32W, ARM_INS_CRC32W: crc32w */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_DBG, ARM_INS_DBG: dbg */ { 0 } }, { /* ARM_DMB, ARM_INS_DMB: dmb */ { 0 } }, { /* ARM_DSB, ARM_INS_DFB: dfb */ { 0 } }, { /* ARM_EORri, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_EORrr, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_EORrsi, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_EORrsr, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ERET, ARM_INS_ERET: eret */ { 0 } }, { /* ARM_FCONSTD, ARM_INS_FCONSTD: fconstd */ { CS_AC_WRITE, 0 } }, { /* ARM_FCONSTH, ARM_INS_VMOV: vmov */ { 0 } }, { /* ARM_FCONSTS, ARM_INS_FCONSTS: fconsts */ { CS_AC_WRITE, 0 } }, { /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax */ { CS_AC_READ, 0 } }, { /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_FMSTAT, ARM_INS_FMSTAT: fmstat */ { 0 } }, { /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax */ { CS_AC_READ, 0 } }, { /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_HINT, ARM_INS_CSDB: csdb */ { 0 } }, { /* ARM_HLT, ARM_INS_HLT: hlt */ { 0 } }, { /* ARM_HVC, ARM_INS_HVC: hvc */ { 0 } }, { /* ARM_ISB, ARM_INS_ISB: isb */ { 0 } }, { /* ARM_LDA, ARM_INS_LDA: lda */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDAB, ARM_INS_LDAB: ldab */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDAEX, ARM_INS_LDAEX: ldaex */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDAH, ARM_INS_LDAH: ldah */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC_OPTION, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC_POST, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDC_PRE, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDMDA, ARM_INS_LDMDA: ldmda */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_LDMIA, ARM_INS_LDM: ldm */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_LDMIB, ARM_INS_LDMIB: ldmib */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRBi12, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRBrs, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRD, ARM_INS_LDRD: ldrd */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_LDREX, ARM_INS_LDREX: ldrex */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRH, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, 0 } }, { /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, 0 } }, { /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, 0 } }, { /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, 0 } }, { /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, 0 } }, { /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, 0 } }, { /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt $addr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRi12, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_LDRrs, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_MCR, ARM_INS_MCR: mcr */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_MCR2, ARM_INS_MCR2: mcr2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_MCRR, ARM_INS_MCRR: mcrr */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MLA, ARM_INS_MLA: mla */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MLS, ARM_INS_MLS: mls */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MOVPCLR, ARM_INS_MOV: mov */ { 0 } }, { /* ARM_MOVTi16, ARM_INS_MOVT: movt */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_MOVi, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_MOVi16, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_MOVr, ARM_INS_MOV: mov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_MOVr_TC, ARM_INS_MOV: mov */ { 0 } }, { /* ARM_MOVsi, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_MOVsr, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_MRC, ARM_INS_MRC: mrc */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_MRC2, ARM_INS_MRC2: mrc2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_MRRC, ARM_INS_MRRC: mrrc */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MRS, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_MRSbanked, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_MRSsys, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_MSR, ARM_INS_MSR: msr */ { CS_AC_READ, 0 } }, { /* ARM_MSRbanked, ARM_INS_MSR: msr */ { CS_AC_READ, 0 } }, { /* ARM_MSRi, ARM_INS_MSR: msr */ { 0 } }, { /* ARM_MUL, ARM_INS_MUL: mul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_MVNi, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_MVNr, ARM_INS_MVN: mvn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_MVNsi, ARM_INS_MVN: mvn */ { CS_AC_WRITE, 0 } }, { /* ARM_MVNsr, ARM_INS_MVN: mvn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ORRri, ARM_INS_ORR: orr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ORRrr, ARM_INS_ORR: orr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_ORRrsi, ARM_INS_ORR: orr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_ORRrsr, ARM_INS_ORR: orr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_PLDWi12, ARM_INS_PLDW: pldw */ { CS_AC_READ, 0 } }, { /* ARM_PLDWrs, ARM_INS_PLDW: pldw */ { CS_AC_READ, 0 } }, { /* ARM_PLDi12, ARM_INS_PLD: pld */ { CS_AC_READ, 0 } }, { /* ARM_PLDrs, ARM_INS_PLD: pld */ { CS_AC_READ, 0 } }, { /* ARM_PLIi12, ARM_INS_PLI: pli */ { CS_AC_READ, 0 } }, { /* ARM_PLIrs, ARM_INS_PLI: pli */ { CS_AC_READ, 0 } }, { /* ARM_QADD, ARM_INS_QADD: qadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QADD16, ARM_INS_QADD16: qadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QADD8, ARM_INS_QADD8: qadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QASX, ARM_INS_QASX: qasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QDADD, ARM_INS_QDADD: qdadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QDSUB, ARM_INS_QDSUB: qdsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QSAX, ARM_INS_QSAX: qsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QSUB, ARM_INS_QSUB: qsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QSUB16, ARM_INS_QSUB16: qsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_RBIT, ARM_INS_RBIT: rbit */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_REV, ARM_INS_REV: rev */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_REV16, ARM_INS_REV16: rev16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_REVSH, ARM_INS_REVSH: revsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_RFEDA, ARM_INS_RFEDA: rfeda */ { CS_AC_READ, 0 } }, { /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda */ { CS_AC_READ, 0 } }, { /* ARM_RFEDB, ARM_INS_RFEDB: rfedb */ { CS_AC_READ, 0 } }, { /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb */ { CS_AC_READ, 0 } }, { /* ARM_RFEIA, ARM_INS_RFEIA: rfeia */ { CS_AC_READ, 0 } }, { /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia */ { CS_AC_READ, 0 } }, { /* ARM_RFEIB, ARM_INS_RFEIB: rfeib */ { CS_AC_READ, 0 } }, { /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib */ { CS_AC_READ, 0 } }, { /* ARM_RSBri, ARM_INS_NEG: neg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_RSBrr, ARM_INS_RSB: rsb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_RSBrsi, ARM_INS_RSB: rsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_RSBrsr, ARM_INS_RSB: rsb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_RSCri, ARM_INS_RSC: rsc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_RSCrr, ARM_INS_RSC: rsc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_RSCrsi, ARM_INS_RSC: rsc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_RSCrsr, ARM_INS_RSC: rsc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SADD16, ARM_INS_SADD16: sadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SADD8, ARM_INS_SADD8: sadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SASX, ARM_INS_SASX: sasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SBCri, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SBCrr, ARM_INS_SBC: sbc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SBCrsi, ARM_INS_SBC: sbc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SBCrsr, ARM_INS_SBC: sbc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SBFX, ARM_INS_SBFX: sbfx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SDIV, ARM_INS_SDIV: sdiv */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SEL, ARM_INS_SEL: sel */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SETEND, ARM_INS_SETEND: setend */ { 0 } }, { /* ARM_SETPAN, ARM_INS_SETPAN: setpan */ { 0 } }, { /* ARM_SHA1C, ARM_INS_SHA1C: sha1c */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHA1H, ARM_INS_SHA1H: sha1h */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SHA1M, ARM_INS_SHA1M: sha1m */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHA1P, ARM_INS_SHA1P: sha1p */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SHA256H, ARM_INS_SHA256H: sha256h */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHADD16, ARM_INS_SHADD16: shadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHADD8, ARM_INS_SHADD8: shadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHASX, ARM_INS_SHASX: shasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHSAX, ARM_INS_SHSAX: shsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMC, ARM_INS_SMC: smc */ { 0 } }, { /* ARM_SMLABB, ARM_INS_SMLABB: smlabb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLABT, ARM_INS_SMLABT: smlabt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLAD, ARM_INS_SMLAD: smlad */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLADX, ARM_INS_SMLADX: smladx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLAL, ARM_INS_SMLAL: smlal */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLALD, ARM_INS_SMLALD: smlald */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLATB, ARM_INS_SMLATB: smlatb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLATT, ARM_INS_SMLATT: smlatt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLSD, ARM_INS_SMLSD: smlsd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMMLA, ARM_INS_SMMLA: smmla */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMMLS, ARM_INS_SMMLS: smmls */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMMUL, ARM_INS_SMMUL: smmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMMULR, ARM_INS_SMMULR: smmulr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMUAD, ARM_INS_SMUAD: smuad */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMUADX, ARM_INS_SMUADX: smuadx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULBB, ARM_INS_SMULBB: smulbb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULBT, ARM_INS_SMULBT: smulbt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULL, ARM_INS_SMULL: smull */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULTB, ARM_INS_SMULTB: smultb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULTT, ARM_INS_SMULTT: smultt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULWB, ARM_INS_SMULWB: smulwb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMULWT, ARM_INS_SMULWT: smulwt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMUSD, ARM_INS_SMUSD: smusd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SRSDA, ARM_INS_SRSDA: srsda */ { 0 } }, { /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda */ { 0 } }, { /* ARM_SRSDB, ARM_INS_SRSDB: srsdb */ { 0 } }, { /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb */ { 0 } }, { /* ARM_SRSIA, ARM_INS_SRSIA: srsia */ { 0 } }, { /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia */ { 0 } }, { /* ARM_SRSIB, ARM_INS_SRSIB: srsib */ { 0 } }, { /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib */ { 0 } }, { /* ARM_SSAT, ARM_INS_SSAT: ssat */ { CS_AC_WRITE, 0 } }, { /* ARM_SSAT16, ARM_INS_SSAT16: ssat16 */ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_SSAX, ARM_INS_SSAX: ssax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SSUB16, ARM_INS_SSUB16: ssub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SSUB8, ARM_INS_SSUB8: ssub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2_POST, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC2_PRE, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STCL_OPTION, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STCL_POST, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STCL_PRE, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC_OFFSET, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC_OPTION, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC_POST, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STC_PRE, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STL, ARM_INS_STL: stl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STLB, ARM_INS_STLB: stlb */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STLEX, ARM_INS_STLEX: stlex */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STLEXB, ARM_INS_STLEXB: stlexb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STLEXD, ARM_INS_STLEXD: stlexd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STLEXH, ARM_INS_STLEXH: stlexh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STLH, ARM_INS_STLH: stlh */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STMDA, ARM_INS_STMDA: stmda */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_STMDB, ARM_INS_STMDB: stmdb */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STMDB_UPD, ARM_INS_PUSH: push */ { CS_AC_READ, 0 } }, { /* ARM_STMIA, ARM_INS_STM: stm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STMIA_UPD, ARM_INS_STM: stm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_STMIB, ARM_INS_STMIB: stmib */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRB_POST_REG, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRBi12, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRBrs, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRD, ARM_INS_STRD: strd */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRD_POST, ARM_INS_STRD: strd */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRD_PRE, ARM_INS_STRD: strd */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STREX, ARM_INS_STREX: strex */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STREXB, ARM_INS_STREXB: strexb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STREXD, ARM_INS_STREXD: strexd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STREXH, ARM_INS_STREXH: strexh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRH, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRHTi, ARM_INS_STRHT: strht */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRHTr, ARM_INS_STRHT: strht */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRH_POST, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_STRH_PRE, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRT_POST_REG, ARM_INS_STRT: strt */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STR_POST_IMM, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STR_POST_REG, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STR_PRE_IMM, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STR_PRE_REG, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRi12, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_STRrs, ARM_INS_STR: str */ { CS_AC_READ, 0 } }, { /* ARM_SUBri, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SUBrr, ARM_INS_SUB: sub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SUBrsi, ARM_INS_SUB: sub */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SUBrsr, ARM_INS_SUB: sub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SVC, ARM_INS_SVC: svc */ { 0 } }, { /* ARM_SWP, ARM_INS_SWP: swp */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SWPB, ARM_INS_SWPB: swpb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_SXTAB, ARM_INS_SXTAB: sxtab */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SXTAH, ARM_INS_SXTAH: sxtah */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_SXTB, ARM_INS_SXTB: sxtb */ { CS_AC_WRITE, 0 } }, { /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16 */ { CS_AC_WRITE, 0 } }, { /* ARM_SXTH, ARM_INS_SXTH: sxth */ { CS_AC_WRITE, 0 } }, { /* ARM_TEQri, ARM_INS_TEQ: teq */ { CS_AC_READ, 0 } }, { /* ARM_TEQrr, ARM_INS_TEQ: teq */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_TEQrsi, ARM_INS_TEQ: teq */ { CS_AC_READ, 0 } }, { /* ARM_TEQrsr, ARM_INS_TEQ: teq */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_TRAP, ARM_INS_TRAP: trap */ { 0 } }, { /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ { 0 } }, { /* ARM_TSB, ARM_INS_TSB: tsb */ { 0 } }, { /* ARM_TSTri, ARM_INS_TST: tst */ { CS_AC_READ, 0 } }, { /* ARM_TSTrr, ARM_INS_TST: tst */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_TSTrsi, ARM_INS_TST: tst */ { CS_AC_READ, 0 } }, { /* ARM_TSTrsr, ARM_INS_TST: tst */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UADD16, ARM_INS_UADD16: uadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UADD8, ARM_INS_UADD8: uadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UASX, ARM_INS_UASX: uasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UBFX, ARM_INS_UBFX: ubfx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_UDF, ARM_INS_UDF: udf */ { 0 } }, { /* ARM_UDIV, ARM_INS_UDIV: udiv */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UHASX, ARM_INS_UHASX: uhasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UHSAX, ARM_INS_UHSAX: uhsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UMAAL, ARM_INS_UMAAL: umaal */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UMLAL, ARM_INS_UMLAL: umlal */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UMULL, ARM_INS_UMULL: umull */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UQASX, ARM_INS_UQASX: uqasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UQSAX, ARM_INS_UQSAX: uqsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_USAD8, ARM_INS_USAD8: usad8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_USADA8, ARM_INS_USADA8: usada8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_USAT, ARM_INS_USAT: usat */ { CS_AC_WRITE, 0 } }, { /* ARM_USAT16, ARM_INS_USAT16: usat16 */ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_USAX, ARM_INS_USAX: usax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_USUB16, ARM_INS_USUB16: usub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_USUB8, ARM_INS_USUB8: usub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_UXTAB, ARM_INS_UXTAB: uxtab */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_UXTAH, ARM_INS_UXTAH: uxtah */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_UXTB, ARM_INS_UXTB: uxtb */ { CS_AC_WRITE, 0 } }, { /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16 */ { CS_AC_WRITE, 0 } }, { /* ARM_UXTH, ARM_INS_UXTH: uxth */ { CS_AC_WRITE, 0 } }, { /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAsv16i8, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAsv2i32, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAsv4i16, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAsv4i32, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAsv8i16, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAsv8i8, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAuv16i8, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAuv2i32, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAuv4i16, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAuv4i32, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAuv8i16, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABAuv8i8, ARM_INS_VABA: vaba */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDfd, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDfq, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDhd, ARM_INS_VABD: vabd */ { 0 } }, { /* ARM_VABDhq, ARM_INS_VABD: vabd */ { 0 } }, { /* ARM_VABDsv16i8, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDsv2i32, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDsv4i16, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDsv4i32, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDsv8i16, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDsv8i8, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDuv16i8, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDuv2i32, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDuv4i16, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDuv4i32, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDuv8i16, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABDuv8i8, ARM_INS_VABD: vabd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VABSD, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSH, ARM_INS_VABS: vabs */ { 0 } }, { /* ARM_VABSS, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSfd, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSfq, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABShd, ARM_INS_VABS: vabs */ { 0 } }, { /* ARM_VABShq, ARM_INS_VABS: vabs */ { 0 } }, { /* ARM_VABSv16i8, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSv2i32, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSv4i16, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSv4i32, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSv8i16, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VABSv8i8, ARM_INS_VABS: vabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VACGEfd, ARM_INS_VACGE: vacge */ { 0 } }, { /* ARM_VACGEfq, ARM_INS_VACGE: vacge */ { 0 } }, { /* ARM_VACGEhd, ARM_INS_VACGE: vacge */ { 0 } }, { /* ARM_VACGEhq, ARM_INS_VACGE: vacge */ { 0 } }, { /* ARM_VACGTfd, ARM_INS_VACGT: vacgt */ { 0 } }, { /* ARM_VACGTfq, ARM_INS_VACGT: vacgt */ { 0 } }, { /* ARM_VACGThd, ARM_INS_VACGT: vacgt */ { 0 } }, { /* ARM_VACGThq, ARM_INS_VACGT: vacgt */ { 0 } }, { /* ARM_VADDD, ARM_INS_FADDD: faddd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDH, ARM_INS_VADD: vadd */ { 0 } }, { /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDS, ARM_INS_FADDS: fadds */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDfd, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDfq, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDhd, ARM_INS_VADD: vadd */ { 0 } }, { /* ARM_VADDhq, ARM_INS_VADD: vadd */ { 0 } }, { /* ARM_VADDv16i8, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv1i64, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv2i32, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv2i64, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv4i16, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv4i32, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv8i16, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VADDv8i8, ARM_INS_VADD: vadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VANDd, ARM_INS_VAND: vand */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VANDq, ARM_INS_VAND: vand */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBICd, ARM_INS_VBIC: vbic */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBICiv2i32, ARM_INS_VAND: vand */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VBICiv4i16, ARM_INS_VAND: vand */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VBICiv4i32, ARM_INS_VAND: vand */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VBICiv8i16, ARM_INS_VAND: vand */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VBICq, ARM_INS_VBIC: vbic */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBIFd, ARM_INS_VBIF: vbif */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBIFq, ARM_INS_VBIF: vbif */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBITd, ARM_INS_VBIT: vbit */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBITq, ARM_INS_VBIT: vbit */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBSLd, ARM_INS_VBSL: vbsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VBSLq, ARM_INS_VBSL: vbsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCADDv2f32, ARM_INS_VCADD: vcadd */ { 0 } }, { /* ARM_VCADDv4f16, ARM_INS_VCADD: vcadd */ { 0 } }, { /* ARM_VCADDv4f32, ARM_INS_VCADD: vcadd */ { 0 } }, { /* ARM_VCADDv8f16, ARM_INS_VCADD: vcadd */ { 0 } }, { /* ARM_VCEQfd, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQfq, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQhd, ARM_INS_VCEQ: vceq */ { 0 } }, { /* ARM_VCEQhq, ARM_INS_VCEQ: vceq */ { 0 } }, { /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv4f16, ARM_INS_VCEQ: vceq */ { 0 } }, { /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv8f16, ARM_INS_VCEQ: vceq */ { 0 } }, { /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEfd, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEfq, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEhd, ARM_INS_VCGE: vcge */ { 0 } }, { /* ARM_VCGEhq, ARM_INS_VCGE: vcge */ { 0 } }, { /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv4f16, ARM_INS_VCGE: vcge */ { 0 } }, { /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv8f16, ARM_INS_VCGE: vcge */ { 0 } }, { /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTfd, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTfq, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGThd, ARM_INS_VCGT: vcgt */ { 0 } }, { /* ARM_VCGThq, ARM_INS_VCGT: vcgt */ { 0 } }, { /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv4f16, ARM_INS_VCGT: vcgt */ { 0 } }, { /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv8f16, ARM_INS_VCGT: vcgt */ { 0 } }, { /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv4f16, ARM_INS_VCLE: vcle */ { 0 } }, { /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv8f16, ARM_INS_VCLE: vcle */ { 0 } }, { /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv4f16, ARM_INS_VCLT: vclt */ { 0 } }, { /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv8f16, ARM_INS_VCLT: vclt */ { 0 } }, { /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCMLAv2f32, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv2f32_indexed, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv4f16, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv4f16_indexed, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv4f32, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv4f32_indexed, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv8f16, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMLAv8f16_indexed, ARM_INS_VCMLA: vcmla */ { 0 } }, { /* ARM_VCMPD, ARM_INS_VCMP: vcmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCMPEH, ARM_INS_VCMPE: vcmpe */ { 0 } }, { /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe */ { CS_AC_READ, 0 } }, { /* ARM_VCMPEZH, ARM_INS_VCMPE: vcmpe */ { 0 } }, { /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe */ { CS_AC_READ, 0 } }, { /* ARM_VCMPH, ARM_INS_VCMP: vcmp */ { 0 } }, { /* ARM_VCMPS, ARM_INS_VCMP: vcmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VCMPZD, ARM_INS_FCMPZD: fcmpzd */ { CS_AC_READ, 0 } }, { /* ARM_VCMPZH, ARM_INS_VCMP: vcmp */ { 0 } }, { /* ARM_VCMPZS, ARM_INS_FCMPZS: fcmpzs */ { CS_AC_READ, 0 } }, { /* ARM_VCNTd, ARM_INS_VCNT: vcnt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCNTq, ARM_INS_VCNT: vcnt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTANSDf, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANSDh, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANSQf, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANSQh, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANUDf, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANUDh, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANUQf, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTANUQh, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTASH, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTAUH, ARM_INS_VCVTA: vcvta */ { 0 } }, { /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTDS, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTMNSDf, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNSDh, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNSQf, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNSQh, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNUDf, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNUDh, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNUQf, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMNUQh, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTMSH, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTMUH, ARM_INS_VCVTM: vcvtm */ { 0 } }, { /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTNNSDf, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNSDh, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNSQf, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNSQh, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNUDf, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNUDh, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNUQf, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNNUQh, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTNSH, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTNUH, ARM_INS_VCVTN: vcvtn */ { 0 } }, { /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTPNSDf, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNSDh, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNSQf, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNSQh, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNUDf, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNUDh, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNUQf, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPNUQh, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTPSH, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTPUH, ARM_INS_VCVTP: vcvtp */ { 0 } }, { /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTSD, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTh2sd, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2sq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2ud, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2uq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2xsd, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2xsq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2xud, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTh2xuq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTs2hd, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTs2hq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTu2hd, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTu2hq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTxs2hd, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTxs2hq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VCVTxu2hd, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VCVTxu2hq, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VDIVD, ARM_INS_VDIV: vdiv */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VDIVH, ARM_INS_VDIV: vdiv */ { 0 } }, { /* ARM_VDIVS, ARM_INS_VDIV: vdiv */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VDUP16d, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUP16q, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUP32d, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUP32q, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUP8d, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUP8q, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VEORd, ARM_INS_VEOR: veor */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEORq, ARM_INS_VEOR: veor */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTd16, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTd32, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTd8, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTq16, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTq32, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTq64, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VEXTq8, ARM_INS_VEXT: vext */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMAD, ARM_INS_VFMA: vfma */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMAH, ARM_INS_VFMA: vfma */ { 0 } }, { /* ARM_VFMAS, ARM_INS_VFMA: vfma */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMAfd, ARM_INS_VFMA: vfma */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMAfq, ARM_INS_VFMA: vfma */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMAhd, ARM_INS_VFMA: vfma */ { 0 } }, { /* ARM_VFMAhq, ARM_INS_VFMA: vfma */ { 0 } }, { /* ARM_VFMSD, ARM_INS_VFMS: vfms */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMSH, ARM_INS_VFMS: vfms */ { 0 } }, { /* ARM_VFMSS, ARM_INS_VFMS: vfms */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMSfd, ARM_INS_VFMS: vfms */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMSfq, ARM_INS_VFMS: vfms */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFMShd, ARM_INS_VFMS: vfms */ { 0 } }, { /* ARM_VFMShq, ARM_INS_VFMS: vfms */ { 0 } }, { /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFNMAH, ARM_INS_VFNMA: vfnma */ { 0 } }, { /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VFNMSH, ARM_INS_VFNMS: vfnms */ { 0 } }, { /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VGETLNi32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VGETLNs16, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VGETLNs8, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VGETLNu16, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VGETLNu8, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VINSH, ARM_INS_VINS: vins */ { 0 } }, { /* ARM_VJCVT, ARM_INS_VJCVT: vjcvt */ { 0 } }, { /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, 0 } }, { /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1 */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, 0 } }, { /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1 */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, 0 } }, { /* ARM_VLD1d16, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d16T, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d32, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d32T, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d64, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d64T, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d8, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d8T, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1q16, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1q32, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1q64, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD1q8, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane] $dst2[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD2b16, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2b32, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2b8, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2d16, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2d32, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2d8, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2q16, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2q32, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD2q8, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3d16, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3d32, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3d8, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3q16, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3q32, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD3q8, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane] $dst2[$lane] $dst3[$lane] $dst4[$lane]\} $rn$rm */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4d16, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4d32, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4d8, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4q16, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4q32, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLD4q8, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4 */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia */ { CS_AC_READ, 0 } }, { /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia */ { CS_AC_READ, 0 } }, { /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VLDRD, ARM_INS_VLDR: vldr */ { CS_AC_WRITE, 0 } }, { /* ARM_VLDRH, ARM_INS_VLDR: vldr */ { 0 } }, { /* ARM_VLDRS, ARM_INS_VLDR: vldr */ { CS_AC_WRITE, 0 } }, { /* ARM_VLLDM, ARM_INS_VLLDM: vlldm */ { 0 } }, { /* ARM_VLSTM, ARM_INS_VLSTM: vlstm */ { 0 } }, { /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXNMH, ARM_INS_VMAXNM: vmaxnm */ { 0 } }, { /* ARM_VMAXNMNDf, ARM_INS_VMAXNM: vmaxnm */ { 0 } }, { /* ARM_VMAXNMNDh, ARM_INS_VMAXNM: vmaxnm */ { 0 } }, { /* ARM_VMAXNMNQf, ARM_INS_VMAXNM: vmaxnm */ { 0 } }, { /* ARM_VMAXNMNQh, ARM_INS_VMAXNM: vmaxnm */ { 0 } }, { /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXfd, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXfq, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXhd, ARM_INS_VMAX: vmax */ { 0 } }, { /* ARM_VMAXhq, ARM_INS_VMAX: vmax */ { 0 } }, { /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINNMH, ARM_INS_VMINNM: vminnm */ { 0 } }, { /* ARM_VMINNMNDf, ARM_INS_VMINNM: vminnm */ { 0 } }, { /* ARM_VMINNMNDh, ARM_INS_VMINNM: vminnm */ { 0 } }, { /* ARM_VMINNMNQf, ARM_INS_VMINNM: vminnm */ { 0 } }, { /* ARM_VMINNMNQh, ARM_INS_VMINNM: vminnm */ { 0 } }, { /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINfd, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINfq, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINhd, ARM_INS_VMIN: vmin */ { 0 } }, { /* ARM_VMINhq, ARM_INS_VMIN: vmin */ { 0 } }, { /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAD, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAH, ARM_INS_VMLA: vmla */ { 0 } }, { /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAS, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAfd, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAfq, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAhd, ARM_INS_VMLA: vmla */ { 0 } }, { /* ARM_VMLAhq, ARM_INS_VMLA: vmla */ { 0 } }, { /* ARM_VMLAslfd, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLAslfq, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLAslhd, ARM_INS_VMLA: vmla */ { 0 } }, { /* ARM_VMLAslhq, ARM_INS_VMLA: vmla */ { 0 } }, { /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSD, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSH, ARM_INS_VMLS: vmls */ { 0 } }, { /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSS, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSfd, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSfq, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLShd, ARM_INS_VMLS: vmls */ { 0 } }, { /* ARM_VMLShq, ARM_INS_VMLS: vmls */ { 0 } }, { /* ARM_VMLSslfd, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSslfq, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSslhd, ARM_INS_VMLS: vmls */ { 0 } }, { /* ARM_VMLSslhq, ARM_INS_VMLS: vmls */ { 0 } }, { /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMOVD, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVDRR, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMOVH, ARM_INS_VMOVX: vmovx */ { 0 } }, { /* ARM_VMOVHR, ARM_INS_VMOV: vmov */ { 0 } }, { /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVRH, ARM_INS_VMOV: vmov */ { 0 } }, { /* ARM_VMOVRRD, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVRRS, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMOVRS, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVS, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVSR, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMOVSRR, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs */ { CS_AC_WRITE, 0 } }, { /* ARM_VMSR, ARM_INS_VMSR: vmsr */ { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr */ { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr */ { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr */ { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr */ { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_VMULD, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULH, ARM_INS_VMUL: vmul */ { 0 } }, { /* ARM_VMULLp64, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLp8, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULS, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULfd, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULfq, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULhd, ARM_INS_VMUL: vmul */ { 0 } }, { /* ARM_VMULhq, ARM_INS_VMUL: vmul */ { 0 } }, { /* ARM_VMULpd, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULpq, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULslfd, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULslfq, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULslhd, ARM_INS_VMUL: vmul */ { 0 } }, { /* ARM_VMULslhq, ARM_INS_VMUL: vmul */ { 0 } }, { /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMULv16i8, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULv2i32, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULv4i16, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULv4i32, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULv8i16, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMULv8i8, ARM_INS_VMUL: vmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VMVNd, ARM_INS_VMVN: vmvn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMVNq, ARM_INS_VMVN: vmvn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VMVNv2i32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn */ { CS_AC_WRITE, 0 } }, { /* ARM_VMVNv4i32, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, 0 } }, { /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn */ { CS_AC_WRITE, 0 } }, { /* ARM_VNEGD, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGH, ARM_INS_VNEG: vneg */ { 0 } }, { /* ARM_VNEGS, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGf32q, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGfd, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGhd, ARM_INS_VNEG: vneg */ { 0 } }, { /* ARM_VNEGhq, ARM_INS_VNEG: vneg */ { 0 } }, { /* ARM_VNEGs16d, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGs16q, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGs32d, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGs32q, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGs8d, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNEGs8q, ARM_INS_VNEG: vneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VNMLAH, ARM_INS_VNMLA: vnmla */ { 0 } }, { /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VNMLSH, ARM_INS_VNMLS: vnmls */ { 0 } }, { /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VNMULD, ARM_INS_VNMUL: vnmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VNMULH, ARM_INS_VNMUL: vnmul */ { 0 } }, { /* ARM_VNMULS, ARM_INS_VNMUL: vnmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VORNd, ARM_INS_VORN: vorn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VORNq, ARM_INS_VORN: vorn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VORRd, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VORRiv2i32, ARM_INS_VORR: vorr */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VORRiv4i16, ARM_INS_VORR: vorr */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VORRiv4i32, ARM_INS_VORR: vorr */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VORRiv8i16, ARM_INS_VORR: vorr */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VORRq, ARM_INS_VMOV: vmov */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VPADDf, ARM_INS_VPADD: vpadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPADDh, ARM_INS_VPADD: vpadd */ { 0 } }, { /* ARM_VPADDi16, ARM_INS_VPADD: vpadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPADDi32, ARM_INS_VPADD: vpadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPADDi8, ARM_INS_VPADD: vpadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXh, ARM_INS_VPMAX: vpmax */ { 0 } }, { /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINf, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINh, ARM_INS_VPMIN: vpmin */ { 0 } }, { /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRDMLAHslv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHslv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHslv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHslv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHv2i32, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHv4i16, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHv4i32, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLAHv8i16, ARM_INS_VQRDMLAH: vqrdmlah */ { 0 } }, { /* ARM_VQRDMLSHslv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHslv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHslv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHslv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHv2i32, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHv4i16, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHv4i32, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMLSHv8i16, ARM_INS_VQRDMLSH: vqrdmlsh */ { 0 } }, { /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRECPEhd, ARM_INS_VRECPE: vrecpe */ { 0 } }, { /* ARM_VRECPEhq, ARM_INS_VRECPE: vrecpe */ { 0 } }, { /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRECPShd, ARM_INS_VRECPS: vrecps */ { 0 } }, { /* ARM_VRECPShq, ARM_INS_VRECPS: vrecps */ { 0 } }, { /* ARM_VREV16d8, ARM_INS_VREV16: vrev16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV16q8, ARM_INS_VREV16: vrev16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV32d16, ARM_INS_VREV32: vrev32 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV32d8, ARM_INS_VREV32: vrev32 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV32q16, ARM_INS_VREV32: vrev32 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV32q8, ARM_INS_VREV32: vrev32 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV64d16, ARM_INS_VREV64: vrev64 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV64d32, ARM_INS_VREV64: vrev64 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV64d8, ARM_INS_VREV64: vrev64 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV64q16, ARM_INS_VREV64: vrev64 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV64q32, ARM_INS_VREV64: vrev64 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VREV64q8, ARM_INS_VREV64: vrev64 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTAH, ARM_INS_VRINTA: vrinta */ { 0 } }, { /* ARM_VRINTANDf, ARM_INS_VRINTA: vrinta */ { 0 } }, { /* ARM_VRINTANDh, ARM_INS_VRINTA: vrinta */ { 0 } }, { /* ARM_VRINTANQf, ARM_INS_VRINTA: vrinta */ { 0 } }, { /* ARM_VRINTANQh, ARM_INS_VRINTA: vrinta */ { 0 } }, { /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTMH, ARM_INS_VRINTM: vrintm */ { 0 } }, { /* ARM_VRINTMNDf, ARM_INS_VRINTM: vrintm */ { 0 } }, { /* ARM_VRINTMNDh, ARM_INS_VRINTM: vrintm */ { 0 } }, { /* ARM_VRINTMNQf, ARM_INS_VRINTM: vrintm */ { 0 } }, { /* ARM_VRINTMNQh, ARM_INS_VRINTM: vrintm */ { 0 } }, { /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTND, ARM_INS_VRINTN: vrintn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTNH, ARM_INS_VRINTN: vrintn */ { 0 } }, { /* ARM_VRINTNNDf, ARM_INS_VRINTN: vrintn */ { 0 } }, { /* ARM_VRINTNNDh, ARM_INS_VRINTN: vrintn */ { 0 } }, { /* ARM_VRINTNNQf, ARM_INS_VRINTN: vrintn */ { 0 } }, { /* ARM_VRINTNNQh, ARM_INS_VRINTN: vrintn */ { 0 } }, { /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTPH, ARM_INS_VRINTP: vrintp */ { 0 } }, { /* ARM_VRINTPNDf, ARM_INS_VRINTP: vrintp */ { 0 } }, { /* ARM_VRINTPNDh, ARM_INS_VRINTP: vrintp */ { 0 } }, { /* ARM_VRINTPNQf, ARM_INS_VRINTP: vrintp */ { 0 } }, { /* ARM_VRINTPNQh, ARM_INS_VRINTP: vrintp */ { 0 } }, { /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTRH, ARM_INS_VRINTR: vrintr */ { 0 } }, { /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTXH, ARM_INS_VRINTX: vrintx */ { 0 } }, { /* ARM_VRINTXNDf, ARM_INS_VRINTX: vrintx */ { 0 } }, { /* ARM_VRINTXNDh, ARM_INS_VRINTX: vrintx */ { 0 } }, { /* ARM_VRINTXNQf, ARM_INS_VRINTX: vrintx */ { 0 } }, { /* ARM_VRINTXNQh, ARM_INS_VRINTX: vrintx */ { 0 } }, { /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRINTZH, ARM_INS_VRINTZ: vrintz */ { 0 } }, { /* ARM_VRINTZNDf, ARM_INS_VRINTZ: vrintz */ { 0 } }, { /* ARM_VRINTZNDh, ARM_INS_VRINTZ: vrintz */ { 0 } }, { /* ARM_VRINTZNQf, ARM_INS_VRINTZ: vrintz */ { 0 } }, { /* ARM_VRINTZNQh, ARM_INS_VRINTZ: vrintz */ { 0 } }, { /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSQRTEhd, ARM_INS_VRSQRTE: vrsqrte */ { 0 } }, { /* ARM_VRSQRTEhq, ARM_INS_VRSQRTE: vrsqrte */ { 0 } }, { /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSQRTShd, ARM_INS_VRSQRTS: vrsqrts */ { 0 } }, { /* ARM_VRSQRTShq, ARM_INS_VRSQRTS: vrsqrts */ { 0 } }, { /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSDOTD, ARM_INS_VSDOT: vsdot */ { 0 } }, { /* ARM_VSDOTDI, ARM_INS_VSDOT: vsdot */ { 0 } }, { /* ARM_VSDOTQ, ARM_INS_VSDOT: vsdot */ { 0 } }, { /* ARM_VSDOTQI, ARM_INS_VSDOT: vsdot */ { 0 } }, { /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELEQH, ARM_INS_VSELEQ: vseleq */ { 0 } }, { /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELGED, ARM_INS_VSELGE: vselge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELGEH, ARM_INS_VSELGE: vselge */ { 0 } }, { /* ARM_VSELGES, ARM_INS_VSELGE: vselge */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELGTH, ARM_INS_VSELGT: vselgt */ { 0 } }, { /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSELVSH, ARM_INS_VSELVS: vselvs */ { 0 } }, { /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSETLNi16, ARM_INS_VMOV: vmov */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSETLNi32, ARM_INS_FMDHR: fmdhr */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSETLNi8, ARM_INS_VMOV: vmov */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSHTOD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSHTOH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VSHTOS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSITOD, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSITOH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VSITOS, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSLTOD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSLTOH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VSLTOS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSQRTH, ARM_INS_VSQRT: vsqrt */ { 0 } }, { /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VST1LNd16, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1 */ { CS_AC_READ, 0 } }, { /* ARM_VST1LNd32, ARM_INS_VST1: vst1 */ { CS_AC_READ, 0 } }, { /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1 */ { CS_AC_READ, 0 } }, { /* ARM_VST1LNd8, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1 */ { CS_AC_READ, 0 } }, { /* ARM_VST1d16, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16Q, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16T, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32Q, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32T, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64Q, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64T, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8Q, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8T, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q16, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q32, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q64, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q8, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane] $src2[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane] $src2[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane] $src2[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b16, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b32, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b8, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d16, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d32, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d8, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q16, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q32, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q8, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3d16, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3d32, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3d8, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3q16, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3q32, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3q8, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane] $src2[$lane] $src3[$lane] $src4[$lane]\} $rn$rm */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4d16, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4d32, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4d8, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4q16, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4q32, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4q8, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSTMDDB_UPD, ARM_INS_VPUSH: vpush */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia */ { CS_AC_READ, 0 } }, { /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSTMSDB_UPD, ARM_INS_VPUSH: vpush */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia */ { CS_AC_READ, 0 } }, { /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VSTRD, ARM_INS_VSTR: vstr */ { CS_AC_READ, 0 } }, { /* ARM_VSTRH, ARM_INS_VSTR: vstr */ { 0 } }, { /* ARM_VSTRS, ARM_INS_VSTR: vstr */ { CS_AC_READ, 0 } }, { /* ARM_VSUBD, ARM_INS_FSUBD: fsubd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBH, ARM_INS_VSUB: vsub */ { 0 } }, { /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBS, ARM_INS_FSUBS: fsubs */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBfd, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBfq, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBhd, ARM_INS_VSUB: vsub */ { 0 } }, { /* ARM_VSUBhq, ARM_INS_VSUB: vsub */ { 0 } }, { /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VSWPd, ARM_INS_VSWP: vswp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VSWPq, ARM_INS_VSWP: vswp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTBL1, ARM_INS_VTBL: vtbl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBL2, ARM_INS_VTBL: vtbl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBL3, ARM_INS_VTBL: vtbl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBL4, ARM_INS_VTBL: vtbl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBX1, ARM_INS_VTBX: vtbx */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBX2, ARM_INS_VTBX: vtbx */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBX3, ARM_INS_VTBX: vtbx */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTBX4, ARM_INS_VTBX: vtbx */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTOSHD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOSHH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VTOSHS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOSIRH, ARM_INS_VCVTR: vcvtr */ { 0 } }, { /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOSIZH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOSLD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOSLH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VTOSLS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOUHD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOUHH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VTOUHS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOUIRH, ARM_INS_VCVTR: vcvtr */ { 0 } }, { /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOUIZH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VTOULD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTOULH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VTOULS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VTRNd16, ARM_INS_VTRN: vtrn */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTRNd32, ARM_INS_VTRN: vtrn */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTRNd8, ARM_INS_VTRN: vtrn */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTRNq16, ARM_INS_VTRN: vtrn */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTRNq32, ARM_INS_VTRN: vtrn */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTRNq8, ARM_INS_VTRN: vtrn */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VTSTv16i8, ARM_INS_VTST: vtst */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTSTv2i32, ARM_INS_VTST: vtst */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTSTv4i16, ARM_INS_VTST: vtst */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTSTv4i32, ARM_INS_VTST: vtst */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTSTv8i16, ARM_INS_VTST: vtst */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VTSTv8i8, ARM_INS_VTST: vtst */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_VUDOTD, ARM_INS_VUDOT: vudot */ { 0 } }, { /* ARM_VUDOTDI, ARM_INS_VUDOT: vudot */ { 0 } }, { /* ARM_VUDOTQ, ARM_INS_VUDOT: vudot */ { 0 } }, { /* ARM_VUDOTQI, ARM_INS_VUDOT: vudot */ { 0 } }, { /* ARM_VUHTOD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VUHTOH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VUHTOS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VUITOD, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VUITOH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VUITOS, ARM_INS_VCVT: vcvt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_VULTOD, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VULTOH, ARM_INS_VCVT: vcvt */ { 0 } }, { /* ARM_VULTOS, ARM_INS_VCVT: vcvt */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_VUZPd16, ARM_INS_VUZP: vuzp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VUZPd8, ARM_INS_VUZP: vuzp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VUZPq16, ARM_INS_VUZP: vuzp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VUZPq32, ARM_INS_VUZP: vuzp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VUZPq8, ARM_INS_VUZP: vuzp */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VZIPd16, ARM_INS_VZIP: vzip */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VZIPd8, ARM_INS_VZIP: vzip */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VZIPq16, ARM_INS_VZIP: vzip */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VZIPq32, ARM_INS_VZIP: vzip */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_VZIPq8, ARM_INS_VZIP: vzip */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMIA, ARM_INS_LDM: ldm */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_sysSTMDA, ARM_INS_STMDA: stmda */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_sysSTMIA, ARM_INS_STM: stm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_sysSTMIB, ARM_INS_STMIB: stmib */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ADCri, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ADCrr, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2ADCrs, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ADDri, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ADDri12, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ADDrr, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2ADDrs, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ADR, ARM_INS_ADD: add */ { CS_AC_WRITE, 0 } }, { /* ARM_t2ANDri, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ANDrr, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2ANDrs, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ASRri, ARM_INS_ASR: asr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ASRrr, ARM_INS_ASR: asr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2B, ARM_INS_B: b */ { 0 } }, { /* ARM_t2BFC, ARM_INS_BFC: bfc */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_t2BFI, ARM_INS_BFI: bfi */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2BICri, ARM_INS_AND: and */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2BICrr, ARM_INS_BIC: bic */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2BICrs, ARM_INS_BIC: bic */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2BXJ, ARM_INS_BXJ: bxj */ { CS_AC_READ, 0 } }, { /* ARM_t2Bcc, ARM_INS_B: b */ { 0 } }, { /* ARM_t2CDP, ARM_INS_CDP: cdp */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_t2CDP2, ARM_INS_CDP2: cdp2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_t2CLREX, ARM_INS_CLREX: clrex */ { 0 } }, { /* ARM_t2CLZ, ARM_INS_CLZ: clz */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2CMNri, ARM_INS_CMN: cmn */ { CS_AC_READ, 0 } }, { /* ARM_t2CMNzrr, ARM_INS_CMN: cmn */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CMNzrs, ARM_INS_CMN: cmn */ { CS_AC_READ, 0 } }, { /* ARM_t2CMPri, ARM_INS_CMN: cmn */ { CS_AC_READ, 0 } }, { /* ARM_t2CMPrr, ARM_INS_CMP: cmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CMPrs, ARM_INS_CMP: cmp */ { CS_AC_READ, 0 } }, { /* ARM_t2CPS1p, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_t2CPS2p, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_t2CPS3p, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2DBG, ARM_INS_DBG: dbg */ { 0 } }, { /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1 */ { 0 } }, { /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2 */ { 0 } }, { /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3 */ { 0 } }, { /* ARM_t2DMB, ARM_INS_DMB: dmb */ { 0 } }, { /* ARM_t2DSB, ARM_INS_DFB: dfb */ { 0 } }, { /* ARM_t2EORri, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2EORrr, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2EORrs, ARM_INS_EOR: eor */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2HINT, ARM_INS_CSDB: csdb */ { 0 } }, { /* ARM_t2HVC, ARM_INS_HVC: hvc */ { 0 } }, { /* ARM_t2ISB, ARM_INS_ISB: isb */ { 0 } }, { /* ARM_t2IT, ARM_INS_IT: it */ { 0 } }, { /* ARM_t2LDA, ARM_INS_LDA: lda */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDAB, ARM_INS_LDAB: ldab */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDAH, ARM_INS_LDAH: ldah */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC_POST, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_t2LDMIA, ARM_INS_LDM: ldm */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd */ { CS_AC_WRITE, CS_AC_WRITE, 0 } }, { /* ARM_t2LDREX, ARM_INS_LDREX: ldrex */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LDRT, ARM_INS_LDRT: ldrt */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDR_POST, ARM_INS_LDR: ldr */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRi12, ARM_INS_LDR: ldr */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRi8, ARM_INS_LDR: ldr */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRpci, ARM_INS_LDR: ldr */ { CS_AC_WRITE, 0 } }, { /* ARM_t2LDRs, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LSLri, ARM_INS_LSL: lsl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LSLrr, ARM_INS_LSL: lsl */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2LSRri, ARM_INS_LSR: lsr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2LSRrr, ARM_INS_LSR: lsr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MCR, ARM_INS_MCR: mcr */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_t2MCR2, ARM_INS_MCR2: mcr2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_t2MCRR, ARM_INS_MCRR: mcrr */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MLA, ARM_INS_MLA: mla */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MLS, ARM_INS_MLS: mls */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MOVTi16, ARM_INS_MOVT: movt */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_t2MOVi, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MOVi16, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MOVr, ARM_INS_LSL: lsl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd $rm #1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd $rm #1 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2MRC, ARM_INS_MRC: mrc */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_t2MRC2, ARM_INS_MRC2: mrc2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* ARM_t2MRRC, ARM_INS_MRRC: mrrc */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2 */ { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MRS_AR, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MRS_M, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MRSbanked, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MSR_AR, ARM_INS_MSR: msr */ { CS_AC_READ, 0 } }, { /* ARM_t2MSR_M, ARM_INS_MSR: msr */ { CS_AC_READ, 0 } }, { /* ARM_t2MSRbanked, ARM_INS_MSR: msr */ { CS_AC_READ, 0 } }, { /* ARM_t2MUL, ARM_INS_MUL: mul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2MVNi, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_t2MVNr, ARM_INS_MVN: mvn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2MVNs, ARM_INS_MVN: mvn */ { CS_AC_WRITE, 0 } }, { /* ARM_t2ORNri, ARM_INS_ORN: orn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ORNrr, ARM_INS_ORN: orn */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2ORNrs, ARM_INS_ORN: orn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ORRri, ARM_INS_ORN: orn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2ORRrr, ARM_INS_ORR: orr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2ORRrs, ARM_INS_ORR: orr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw */ { CS_AC_READ, 0 } }, { /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw */ { CS_AC_READ, 0 } }, { /* ARM_t2PLDWs, ARM_INS_PLDW: pldw */ { CS_AC_READ, 0 } }, { /* ARM_t2PLDi12, ARM_INS_PLD: pld */ { CS_AC_READ, 0 } }, { /* ARM_t2PLDi8, ARM_INS_PLD: pld */ { CS_AC_READ, 0 } }, { /* ARM_t2PLDpci, ARM_INS_PLD: pld */ { CS_AC_READ, 0 } }, { /* ARM_t2PLDs, ARM_INS_PLD: pld */ { CS_AC_READ, 0 } }, { /* ARM_t2PLIi12, ARM_INS_PLI: pli */ { CS_AC_READ, 0 } }, { /* ARM_t2PLIi8, ARM_INS_PLI: pli */ { CS_AC_READ, 0 } }, { /* ARM_t2PLIpci, ARM_INS_PLI: pli */ { CS_AC_READ, 0 } }, { /* ARM_t2PLIs, ARM_INS_PLI: pli */ { CS_AC_READ, 0 } }, { /* ARM_t2QADD, ARM_INS_QADD: qadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QADD16, ARM_INS_QADD16: qadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QADD8, ARM_INS_QADD8: qadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QASX, ARM_INS_QASX: qasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QDADD, ARM_INS_QDADD: qdadd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QSAX, ARM_INS_QSAX: qsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QSUB, ARM_INS_QSUB: qsub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2RBIT, ARM_INS_RBIT: rbit */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2REV, ARM_INS_REV: rev */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2REV16, ARM_INS_REV16: rev16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2REVSH, ARM_INS_REVSH: revsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb */ { CS_AC_READ, 0 } }, { /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb */ { CS_AC_READ, 0 } }, { /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia */ { CS_AC_READ, 0 } }, { /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia */ { CS_AC_READ, 0 } }, { /* ARM_t2RORri, ARM_INS_ROR: ror */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2RORrr, ARM_INS_ROR: ror */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2RRX, ARM_INS_RRX: rrx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2RSBri, ARM_INS_NEG: neg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2RSBrr, ARM_INS_RSB: rsb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2RSBrs, ARM_INS_RSB: rsb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SADD16, ARM_INS_SADD16: sadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SADD8, ARM_INS_SADD8: sadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SASX, ARM_INS_SASX: sasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SBCri, ARM_INS_ADC: adc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SBCrr, ARM_INS_SBC: sbc */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SBCrs, ARM_INS_SBC: sbc */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SBFX, ARM_INS_SBFX: sbfx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SDIV, ARM_INS_SDIV: sdiv */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SEL, ARM_INS_SEL: sel */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SETPAN, ARM_INS_SETPAN: setpan */ { 0 } }, { /* ARM_t2SG, ARM_INS_SG: sg */ { 0 } }, { /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SHASX, ARM_INS_SHASX: shasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMC, ARM_INS_SMC: smc */ { 0 } }, { /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULL, ARM_INS_SMULL: smull */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb */ { 0 } }, { /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb */ { 0 } }, { /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia */ { 0 } }, { /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia */ { 0 } }, { /* ARM_t2SSAT, ARM_INS_SSAT: ssat */ { CS_AC_WRITE, 0 } }, { /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16 */ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_t2SSAX, ARM_INS_SSAX: ssax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2_POST, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2 */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STCL_POST, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC_OFFSET, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC_OPTION, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC_POST, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STC_PRE, ARM_INS_STC: stc */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STL, ARM_INS_STL: stl */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STLB, ARM_INS_STLB: stlb */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STLEX, ARM_INS_STLEX: stlex */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STLH, ARM_INS_STLH: stlh */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STMDB, ARM_INS_STMDB: stmdb */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STMDB_UPD, ARM_INS_PUSH: push */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STMIA, ARM_INS_STM: stm */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STMIA_UPD, ARM_INS_STM: stm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2STRBT, ARM_INS_STRBT: strbt */ { CS_AC_WRITE, 0 } }, { /* ARM_t2STRB_POST, ARM_INS_STRB: strb */ { CS_AC_READ, 0 } }, { /* ARM_t2STRB_PRE, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRBi12, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRBi8, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRBs, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRD_POST, ARM_INS_STRD: strd */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STRD_PRE, ARM_INS_STRD: strd */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STRDi8, ARM_INS_STRD: strd */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STREX, ARM_INS_STREX: strex */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2STREXB, ARM_INS_STREXB: strexb */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STREXD, ARM_INS_STREXD: strexd */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STREXH, ARM_INS_STREXH: strexh */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2STRHT, ARM_INS_STRHT: strht */ { CS_AC_WRITE, 0 } }, { /* ARM_t2STRH_POST, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRH_PRE, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRHi12, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRHi8, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRHs, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRT, ARM_INS_STRT: strt */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STR_POST, ARM_INS_STR: str */ { CS_AC_READ, 0 } }, { /* ARM_t2STR_PRE, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRi12, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRi8, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2STRs, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_t2SUBS_PC_LR, ARM_INS_ERET: eret */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SUBri, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SUBri12, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SUBrr, ARM_INS_SUB: sub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2SUBrs, ARM_INS_SUB: sub */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SXTB, ARM_INS_SXTB: sxtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2SXTH, ARM_INS_SXTH: sxth */ { CS_AC_WRITE, 0 } }, { /* ARM_t2TBB, ARM_INS_TBB: tbb */ { CS_AC_READ, 0 } }, { /* ARM_t2TBH, ARM_INS_TBH: tbh */ { CS_AC_READ, 0 } }, { /* ARM_t2TEQri, ARM_INS_TEQ: teq */ { CS_AC_READ, 0 } }, { /* ARM_t2TEQrr, ARM_INS_TEQ: teq */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2TEQrs, ARM_INS_TEQ: teq */ { CS_AC_READ, 0 } }, { /* ARM_t2TSB, ARM_INS_TSB: tsb */ { 0 } }, { /* ARM_t2TSTri, ARM_INS_TST: tst */ { CS_AC_READ, 0 } }, { /* ARM_t2TSTrr, ARM_INS_TST: tst */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2TSTrs, ARM_INS_TST: tst */ { CS_AC_READ, 0 } }, { /* ARM_t2TT, ARM_INS_TT: tt */ { 0 } }, { /* ARM_t2TTA, ARM_INS_TTA: tta */ { 0 } }, { /* ARM_t2TTAT, ARM_INS_TTAT: ttat */ { 0 } }, { /* ARM_t2TTT, ARM_INS_TTT: ttt */ { 0 } }, { /* ARM_t2UADD16, ARM_INS_UADD16: uadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UADD8, ARM_INS_UADD8: uadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UASX, ARM_INS_UASX: uasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UBFX, ARM_INS_UBFX: ubfx */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2UDF, ARM_INS_UDF: udf */ { 0 } }, { /* ARM_t2UDIV, ARM_INS_UDIV: udiv */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UHASX, ARM_INS_UHASX: uhasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UMULL, ARM_INS_UMULL: umull */ { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UQASX, ARM_INS_UQASX: uqasx */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2USAD8, ARM_INS_USAD8: usad8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2USADA8, ARM_INS_USADA8: usada8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2USAT, ARM_INS_USAT: usat */ { CS_AC_WRITE, 0 } }, { /* ARM_t2USAT16, ARM_INS_USAT16: usat16 */ { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* ARM_t2USAX, ARM_INS_USAX: usax */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2USUB16, ARM_INS_USUB16: usub16 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2USUB8, ARM_INS_USUB8: usub8 */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_t2UXTB, ARM_INS_UXTB: uxtb */ { CS_AC_WRITE, 0 } }, { /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16 */ { CS_AC_WRITE, 0 } }, { /* ARM_t2UXTH, ARM_INS_UXTH: uxth */ { CS_AC_WRITE, 0 } }, { /* ARM_tADC, ARM_INS_ADC: adc */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tADDhirr, ARM_INS_ADD: add */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tADDi3, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tADDi8, ARM_INS_ADD: add */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_tADDrSP, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tADDrSPi, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tADDrr, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tADDspi, ARM_INS_ADD: add */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_tADDspr, ARM_INS_ADD: add */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tADR, ARM_INS_ADR: adr */ { CS_AC_WRITE, 0 } }, { /* ARM_tAND, ARM_INS_AND: and */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tASRri, ARM_INS_ASR: asr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tASRrr, ARM_INS_ASR: asr */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tB, ARM_INS_B: b */ { 0 } }, { /* ARM_tBIC, ARM_INS_BIC: bic */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tBKPT, ARM_INS_BKPT: bkpt */ { 0 } }, { /* ARM_tBL, ARM_INS_BL: bl */ { 0 } }, { /* ARM_tBLXNSr, ARM_INS_BLXNS: blxns */ { 0 } }, { /* ARM_tBLXi, ARM_INS_BLX: blx */ { 0 } }, { /* ARM_tBLXr, ARM_INS_BLX: blx */ { CS_AC_READ, 0 } }, { /* ARM_tBX, ARM_INS_BX: bx */ { CS_AC_READ, 0 } }, { /* ARM_tBXNS, ARM_INS_BXNS: bxns */ { 0 } }, { /* ARM_tBcc, ARM_INS_B: b */ { 0 } }, { /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz */ { CS_AC_READ, 0 } }, { /* ARM_tCBZ, ARM_INS_CBZ: cbz */ { CS_AC_READ, 0 } }, { /* ARM_tCMNz, ARM_INS_CMN: cmn */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tCMPhir, ARM_INS_CMP: cmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tCMPi8, ARM_INS_CMP: cmp */ { CS_AC_READ, 0 } }, { /* ARM_tCMPr, ARM_INS_CMP: cmp */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tCPS, ARM_INS_CPS: cps */ { 0 } }, { /* ARM_tEOR, ARM_INS_EOR: eor */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tHINT, ARM_INS_HINT: hint */ { 0 } }, { /* ARM_tHLT, ARM_INS_HLT: hlt */ { 0 } }, { /* ARM_tLDMIA, ARM_INS_LDM: ldm */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRBi, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRBr, ARM_INS_LDRB: ldrb */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRHi, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRHr, ARM_INS_LDRH: ldrh */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh */ { CS_AC_WRITE, 0 } }, { /* ARM_tLDRi, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLDRpci, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLDRr, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLDRspi, ARM_INS_LDR: ldr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLSLri, ARM_INS_LSL: lsl */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLSLrr, ARM_INS_LSL: lsl */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLSRri, ARM_INS_LSR: lsr */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tLSRrr, ARM_INS_LSR: lsr */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tMOVSr, ARM_INS_MOVS: movs */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tMOVi8, ARM_INS_MOV: mov */ { CS_AC_WRITE, 0 } }, { /* ARM_tMOVr, ARM_INS_MOV: mov */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tMUL, ARM_INS_MUL: mul */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_tMVN, ARM_INS_MVN: mvn */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tORR, ARM_INS_ORR: orr */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tPOP, ARM_INS_POP: pop */ { CS_AC_WRITE, 0 } }, { /* ARM_tPUSH, ARM_INS_PUSH: push */ { CS_AC_READ, 0 } }, { /* ARM_tREV, ARM_INS_REV: rev */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tREV16, ARM_INS_REV16: rev16 */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tREVSH, ARM_INS_REVSH: revsh */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tROR, ARM_INS_ROR: ror */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tRSB, ARM_INS_NEG: neg */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tSBC, ARM_INS_SBC: sbc */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tSETEND, ARM_INS_SETEND: setend */ { 0 } }, { /* ARM_tSTMIA_UPD, ARM_INS_STM: stm */ { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tSTRBi, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSTRBr, ARM_INS_STRB: strb */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSTRHi, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSTRHr, ARM_INS_STRH: strh */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSTRi, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSTRr, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSTRspi, ARM_INS_STR: str */ { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* ARM_tSUBi3, ARM_INS_ADD: add */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tSUBi8, ARM_INS_ADD: add */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_tSUBrr, ARM_INS_SUB: sub */ { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tSUBspi, ARM_INS_ADD: add */ { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* ARM_tSVC, ARM_INS_SVC: svc */ { 0 } }, { /* ARM_tSXTB, ARM_INS_SXTB: sxtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tSXTH, ARM_INS_SXTH: sxth */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tTRAP, ARM_INS_TRAP: trap */ { 0 } }, { /* ARM_tTST, ARM_INS_TST: tst */ { CS_AC_READ, CS_AC_READ, 0 } }, { /* ARM_tUDF, ARM_INS_UDF: udf */ { 0 } }, { /* ARM_tUXTB, ARM_INS_UXTB: uxtb */ { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* ARM_tUXTH, ARM_INS_UXTH: uxth */ { CS_AC_WRITE, CS_AC_READ, 0 } }, capstone-sys-0.15.0/capstone/arch/ARM/ARMModule.c000064400000000000000000000024120072674642500174670ustar 00000000000000/* Capstone Disassembly Engine */ /* By Dang Hoang Vu 2013 */ #ifdef CAPSTONE_HAS_ARM #include "../../cs_priv.h" #include "../../MCRegisterInfo.h" #include "ARMDisassembler.h" #include "ARMInstPrinter.h" #include "ARMMapping.h" #include "ARMModule.h" cs_err ARM_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); ARM_init(mri); ARM_getRegName(ud, 0); // use default get_regname ud->printer = ARM_printInst; ud->printer_info = mri; ud->reg_name = ARM_reg_name; ud->insn_id = ARM_get_insn_id; ud->insn_name = ARM_insn_name; ud->group_name = ARM_group_name; ud->post_printer = ARM_post_printer; #ifndef CAPSTONE_DIET ud->reg_access = ARM_reg_access; #endif if (ud->mode & CS_MODE_THUMB) ud->disasm = Thumb_getInstruction; else ud->disasm = ARM_getInstruction; return CS_ERR_OK; } cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value) { switch(type) { case CS_OPT_MODE: if (value & CS_MODE_THUMB) handle->disasm = Thumb_getInstruction; else handle->disasm = ARM_getInstruction; handle->mode = (cs_mode)value; break; case CS_OPT_SYNTAX: ARM_getRegName(handle, (int)value); handle->syntax = (int)value; break; default: break; } return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/ARM/ARMModule.h000064400000000000000000000004310072674642500174730ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_ARM_MODULE_H #define CS_ARM_MODULE_H #include "../../utils.h" cs_err ARM_global_init(cs_struct *ud); cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFConstants.h000064400000000000000000000054470072674642500202160ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ /* This file defines constants and macros used for parsing a BPF instruction */ #ifndef CS_BPF_CONSTANTS_H #define CS_BPF_CONSTANTS_H #define BPF_CLASS(code) ((code) & 0x7) ///< Instruction classes #define BPF_CLASS_LD 0x00 #define BPF_CLASS_LDX 0x01 #define BPF_CLASS_ST 0x02 #define BPF_CLASS_STX 0x03 #define BPF_CLASS_ALU 0x04 #define BPF_CLASS_JMP 0x05 #define BPF_CLASS_RET 0x06 ///< cBPF only #define BPF_CLASS_MISC 0x07 ///< cBPF only #define BPF_CLASS_ALU64 0x07 ///< eBPF only #define BPF_OP(code) ((code) & 0xf0) ///< Types of ALU instruction #define BPF_ALU_ADD 0x00 #define BPF_ALU_SUB 0x10 #define BPF_ALU_MUL 0x20 #define BPF_ALU_DIV 0x30 #define BPF_ALU_OR 0x40 #define BPF_ALU_AND 0x50 #define BPF_ALU_LSH 0x60 #define BPF_ALU_RSH 0x70 #define BPF_ALU_NEG 0x80 #define BPF_ALU_MOD 0x90 #define BPF_ALU_XOR 0xa0 #define BPF_ALU_MOV 0xb0 ///< eBPF only: mov reg to reg #define BPF_ALU_ARSH 0xc0 ///< eBPF only: sign extending shift right #define BPF_ALU_END 0xd0 ///< eBPF only: endianness conversion ///< Types of jmp instruction #define BPF_JUMP_JA 0x00 ///< goto #define BPF_JUMP_JEQ 0x10 ///< '==' #define BPF_JUMP_JGT 0x20 ///< unsigned '>' #define BPF_JUMP_JGE 0x30 ///< unsigned '>=' #define BPF_JUMP_JSET 0x40 ///< '&' #define BPF_JUMP_JNE 0x50 ///< eBPF only: '!=' */ #define BPF_JUMP_JSGT 0x60 ///< eBPF only: signed '>' #define BPF_JUMP_JSGE 0x70 ///< eBPF only: signed '>=' #define BPF_JUMP_CALL 0x80 ///< eBPF only: function call #define BPF_JUMP_EXIT 0x90 ///< eBPF only: exit #define BPF_JUMP_JLT 0xa0 ///< eBPF only: unsigned '<' #define BPF_JUMP_JLE 0xb0 ///< eBPF only: unsigned '<=' #define BPF_JUMP_JSLT 0xc0 ///< eBPF only: signed '<' #define BPF_JUMP_JSLE 0xd0 ///< eBPF only: signed '<=' #define BPF_SRC(code) ((code) & 0x08) #define BPF_RVAL(code) ((code) & 0x18) /* cBPF only: for return types */ ///< Source operand #define BPF_SRC_K 0x00 #define BPF_SRC_X 0x08 #define BPF_SRC_A 0x10 /* cBPF only */ #define BPF_SRC_LITTLE BPF_SRC_K #define BPF_SRC_BIG BPF_SRC_X #define BPF_SIZE(code) ((code) & 0x18) ///< Size modifier #define BPF_SIZE_W 0x00 ///< word #define BPF_SIZE_H 0x08 ///< half word #define BPF_SIZE_B 0x10 ///< byte #define BPF_SIZE_DW 0x18 ///< eBPF only: double word #define BPF_MODE(code) ((code) & 0xe0) ///< Mode modifier #define BPF_MODE_IMM 0x00 ///< used for 32-bit mov in cBPF and 64-bit in eBPF #define BPF_MODE_ABS 0x20 #define BPF_MODE_IND 0x40 #define BPF_MODE_MEM 0x60 #define BPF_MODE_LEN 0x80 ///< cBPF only, reserved in eBPF #define BPF_MODE_MSH 0xa0 ///< cBPF only, reserved in eBPF #define BPF_MODE_XADD 0xc0 ///< eBPF only: exclusive add #define BPF_MISCOP(code) ((code) & 0x80) ///< Operation of misc #define BPF_MISCOP_TAX 0x00 #define BPF_MISCOP_TXA 0x80 #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFDisassembler.c000064400000000000000000000257020072674642500206460ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifdef CAPSTONE_HAS_BPF #include #include // offsetof macro #include "BPFConstants.h" #include "BPFDisassembler.h" #include "BPFMapping.h" #include "../../cs_priv.h" static uint16_t read_u16(cs_struct *ud, const uint8_t *code) { if (MODE_IS_BIG_ENDIAN(ud->mode)) return (((uint16_t)code[0] << 8) | code[1]); else return (((uint16_t)code[1] << 8) | code[0]); } static uint32_t read_u32(cs_struct *ud, const uint8_t *code) { if (MODE_IS_BIG_ENDIAN(ud->mode)) return ((uint32_t)read_u16(ud, code) << 16) | read_u16(ud, code + 2); else return ((uint32_t)read_u16(ud, code + 2) << 16) | read_u16(ud, code); } ///< Malloc bpf_internal, also checks if code_len is large enough. static bpf_internal *alloc_bpf_internal(size_t code_len) { bpf_internal *bpf; if (code_len < 8) return NULL; bpf = cs_mem_malloc(sizeof(bpf_internal)); if (bpf == NULL) return NULL; /* default value */ bpf->insn_size = 8; return bpf; } ///< Fetch a cBPF structure from code static bpf_internal* fetch_cbpf(cs_struct *ud, const uint8_t *code, size_t code_len) { bpf_internal *bpf; bpf = alloc_bpf_internal(code_len); if (bpf == NULL) return NULL; bpf->op = read_u16(ud, code); bpf->jt = code[2]; bpf->jf = code[3]; bpf->k = read_u32(ud, code + 4); return bpf; } ///< Fetch an eBPF structure from code static bpf_internal* fetch_ebpf(cs_struct *ud, const uint8_t *code, size_t code_len) { bpf_internal *bpf; bpf = alloc_bpf_internal(code_len); if (bpf == NULL) return NULL; bpf->op = (uint16_t)code[0]; // eBPF has one 16-byte instruction: BPF_LD | BPF_DW | BPF_IMM, // in this case imm is combined with the next block's imm. if (bpf->op == (BPF_CLASS_LD | BPF_SIZE_DW | BPF_MODE_IMM)) { if (code_len < 16) { cs_mem_free(bpf); return NULL; } bpf->k = read_u32(ud, code + 4) | (((uint64_t)read_u32(ud, code + 12)) << 32); bpf->insn_size = 16; } else { bpf->dst = code[1] & 0xf; bpf->src = (code[1] & 0xf0) >> 4; bpf->offset = read_u16(ud, code + 2); bpf->k = read_u32(ud, code + 4); } return bpf; } #define CHECK_READABLE_REG(ud, reg) do { \ if (! ((reg) >= BPF_REG_R0 && (reg) <= BPF_REG_R10)) \ return false; \ } while (0) #define CHECK_WRITABLE_REG(ud, reg) do { \ if (! ((reg) >= BPF_REG_R0 && (reg) < BPF_REG_R10)) \ return false; \ } while (0) #define CHECK_READABLE_AND_PUSH(ud, MI, r) do { \ CHECK_READABLE_REG(ud, r + BPF_REG_R0); \ MCOperand_CreateReg0(MI, r + BPF_REG_R0); \ } while (0) #define CHECK_WRITABLE_AND_PUSH(ud, MI, r) do { \ CHECK_WRITABLE_REG(ud, r + BPF_REG_R0); \ MCOperand_CreateReg0(MI, r + BPF_REG_R0); \ } while (0) static bool decodeLoad(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { if (!EBPF_MODE(ud)) { /* * +-----+-----------+--------------------+ * | ldb | [k] | [x+k] | * | ldh | [k] | [x+k] | * +-----+-----------+--------------------+ */ if (BPF_SIZE(bpf->op) == BPF_SIZE_DW) return false; if (BPF_SIZE(bpf->op) == BPF_SIZE_B || BPF_SIZE(bpf->op) == BPF_SIZE_H) { /* no ldx */ if (BPF_CLASS(bpf->op) != BPF_CLASS_LD) return false; /* can only be BPF_ABS and BPF_IND */ if (BPF_MODE(bpf->op) == BPF_MODE_ABS) { MCOperand_CreateImm0(MI, bpf->k); return true; } else if (BPF_MODE(bpf->op) == BPF_MODE_IND) { MCOperand_CreateReg0(MI, BPF_REG_X); MCOperand_CreateImm0(MI, bpf->k); return true; } return false; } /* * +-----+----+------+------+-----+-------+ * | ld | #k | #len | M[k] | [k] | [x+k] | * +-----+----+------+------+-----+-------+ * | ldx | #k | #len | M[k] | 4*([k]&0xf) | * +-----+----+------+------+-------------+ */ switch (BPF_MODE(bpf->op)) { default: break; case BPF_MODE_IMM: MCOperand_CreateImm0(MI, bpf->k); return true; case BPF_MODE_LEN: return true; case BPF_MODE_MEM: MCOperand_CreateImm0(MI, bpf->k); return true; } if (BPF_CLASS(bpf->op) == BPF_CLASS_LD) { if (BPF_MODE(bpf->op) == BPF_MODE_ABS) { MCOperand_CreateImm0(MI, bpf->k); return true; } else if (BPF_MODE(bpf->op) == BPF_MODE_IND) { MCOperand_CreateReg0(MI, BPF_REG_X); MCOperand_CreateImm0(MI, bpf->k); return true; } } else { /* LDX */ if (BPF_MODE(bpf->op) == BPF_MODE_MSH) { MCOperand_CreateImm0(MI, bpf->k); return true; } } return false; } /* eBPF mode */ /* * - IMM: lddw imm64 * - ABS: ld{w,h,b,dw} [k] * - IND: ld{w,h,b,dw} [src+k] * - MEM: ldx{w,h,b,dw} dst, [src+off] */ if (BPF_CLASS(bpf->op) == BPF_CLASS_LD) { switch (BPF_MODE(bpf->op)) { case BPF_MODE_IMM: if (bpf->op != (BPF_CLASS_LD | BPF_SIZE_DW | BPF_MODE_IMM)) return false; MCOperand_CreateImm0(MI, bpf->k); return true; case BPF_MODE_ABS: MCOperand_CreateImm0(MI, bpf->k); return true; case BPF_MODE_IND: CHECK_READABLE_AND_PUSH(ud, MI, bpf->src); MCOperand_CreateImm0(MI, bpf->k); return true; } return false; } /* LDX */ if (BPF_MODE(bpf->op) == BPF_MODE_MEM) { CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst); CHECK_READABLE_AND_PUSH(ud, MI, bpf->src); MCOperand_CreateImm0(MI, bpf->offset); return true; } return false; } static bool decodeStore(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { /* in cBPF, only BPF_ST* | BPF_MEM | BPF_W is valid * while in eBPF: * - BPF_STX | BPF_XADD | BPF_{W,DW} * - BPF_ST* | BPF_MEM | BPF_{W,H,B,DW} * are valid */ if (!EBPF_MODE(ud)) { /* can only store to M[] */ if (bpf->op != (BPF_CLASS(bpf->op) | BPF_MODE_MEM | BPF_SIZE_W)) return false; MCOperand_CreateImm0(MI, bpf->k); return true; } /* eBPF */ if (BPF_MODE(bpf->op) == BPF_MODE_XADD) { if (BPF_CLASS(bpf->op) != BPF_CLASS_STX) return false; if (BPF_SIZE(bpf->op) != BPF_SIZE_W && BPF_SIZE(bpf->op) != BPF_SIZE_DW) return false; /* xadd [dst + off], src */ CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst); MCOperand_CreateImm0(MI, bpf->offset); CHECK_READABLE_AND_PUSH(ud, MI, bpf->src); return true; } if (BPF_MODE(bpf->op) != BPF_MODE_MEM) return false; /* st [dst + off], src */ CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst); MCOperand_CreateImm0(MI, bpf->offset); if (BPF_CLASS(bpf->op) == BPF_CLASS_ST) MCOperand_CreateImm0(MI, bpf->k); else CHECK_READABLE_AND_PUSH(ud, MI, bpf->src); return true; } static bool decodeALU(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { /* Set MI->Operands */ /* cBPF */ if (!EBPF_MODE(ud)) { if (BPF_OP(bpf->op) > BPF_ALU_XOR) return false; /* cBPF's NEG has no operands */ if (BPF_OP(bpf->op) == BPF_ALU_NEG) return true; if (BPF_SRC(bpf->op) == BPF_SRC_K) MCOperand_CreateImm0(MI, bpf->k); else /* BPF_SRC_X */ MCOperand_CreateReg0(MI, BPF_REG_X); return true; } /* eBPF */ if (BPF_OP(bpf->op) > BPF_ALU_END) return false; /* ALU64 class doesn't have ENDian */ /* ENDian's imm must be one of 16, 32, 64 */ if (BPF_OP(bpf->op) == BPF_ALU_END) { if (BPF_CLASS(bpf->op) == BPF_CLASS_ALU64) return false; if (bpf->k != 16 && bpf->k != 32 && bpf->k != 64) return false; } /* - op dst, imm * - op dst, src * - neg dst * - le dst */ /* every ALU instructions have dst op */ CHECK_WRITABLE_AND_PUSH(ud, MI, bpf->dst); /* special cases */ if (BPF_OP(bpf->op) == BPF_ALU_NEG) return true; if (BPF_OP(bpf->op) == BPF_ALU_END) { /* bpf->k must be one of 16, 32, 64 */ MCInst_setOpcode(MI, MCInst_getOpcode(MI) | ((uint32_t)bpf->k << 4)); return true; } /* normal cases */ if (BPF_SRC(bpf->op) == BPF_SRC_K) { MCOperand_CreateImm0(MI, bpf->k); } else { /* BPF_SRC_X */ CHECK_READABLE_AND_PUSH(ud, MI, bpf->src); } return true; } static bool decodeJump(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { /* cBPF and eBPF are very different in class jump */ if (!EBPF_MODE(ud)) { if (BPF_OP(bpf->op) > BPF_JUMP_JSET) return false; /* ja is a special case of jumps */ if (BPF_OP(bpf->op) == BPF_JUMP_JA) { MCOperand_CreateImm0(MI, bpf->k); return true; } if (BPF_SRC(bpf->op) == BPF_SRC_K) MCOperand_CreateImm0(MI, bpf->k); else /* BPF_SRC_X */ MCOperand_CreateReg0(MI, BPF_REG_X); MCOperand_CreateImm0(MI, bpf->jt); MCOperand_CreateImm0(MI, bpf->jf); } else { if (BPF_OP(bpf->op) > BPF_JUMP_JSLE) return false; /* No operands for exit */ if (BPF_OP(bpf->op) == BPF_JUMP_EXIT) return bpf->op == (BPF_CLASS_JMP | BPF_JUMP_EXIT); if (BPF_OP(bpf->op) == BPF_JUMP_CALL) { if (bpf->op != (BPF_CLASS_JMP | BPF_JUMP_CALL)) return false; MCOperand_CreateImm0(MI, bpf->k); return true; } /* ja is a special case of jumps */ if (BPF_OP(bpf->op) == BPF_JUMP_JA) { if (BPF_SRC(bpf->op) != BPF_SRC_K) return false; MCOperand_CreateImm0(MI, bpf->offset); return true; } /* dst, src, +off */ CHECK_READABLE_AND_PUSH(ud, MI, bpf->dst); if (BPF_SRC(bpf->op) == BPF_SRC_K) MCOperand_CreateImm0(MI, bpf->k); else CHECK_READABLE_AND_PUSH(ud, MI, bpf->src); MCOperand_CreateImm0(MI, bpf->offset); } return true; } static bool decodeReturn(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { /* Here only handles the BPF_RET class in cBPF */ switch (BPF_RVAL(bpf->op)) { case BPF_SRC_K: MCOperand_CreateImm0(MI, bpf->k); return true; case BPF_SRC_X: MCOperand_CreateReg0(MI, BPF_REG_X); return true; case BPF_SRC_A: MCOperand_CreateReg0(MI, BPF_REG_A); return true; } return false; } static bool decodeMISC(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { uint16_t op = bpf->op ^ BPF_CLASS_MISC; return op == BPF_MISCOP_TAX || op == BPF_MISCOP_TXA; } ///< 1. Check if the instruction is valid ///< 2. Set MI->opcode ///< 3. Set MI->Operands static bool getInstruction(cs_struct *ud, MCInst *MI, bpf_internal *bpf) { cs_detail *detail; detail = MI->flat_insn->detail; // initialize detail if (detail) { memset(detail, 0, offsetof(cs_detail, bpf) + sizeof(cs_bpf)); } MCInst_clear(MI); MCInst_setOpcode(MI, bpf->op); switch (BPF_CLASS(bpf->op)) { default: /* should never happen */ return false; case BPF_CLASS_LD: case BPF_CLASS_LDX: return decodeLoad(ud, MI, bpf); case BPF_CLASS_ST: case BPF_CLASS_STX: return decodeStore(ud, MI, bpf); case BPF_CLASS_ALU: return decodeALU(ud, MI, bpf); case BPF_CLASS_JMP: return decodeJump(ud, MI, bpf); case BPF_CLASS_RET: /* eBPF doesn't have this class */ if (EBPF_MODE(ud)) return false; return decodeReturn(ud, MI, bpf); case BPF_CLASS_MISC: /* case BPF_CLASS_ALU64: */ if (EBPF_MODE(ud)) return decodeALU(ud, MI, bpf); else return decodeMISC(ud, MI, bpf); } } bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { cs_struct *cs; bpf_internal *bpf; cs = (cs_struct*)ud; if (EBPF_MODE(cs)) bpf = fetch_ebpf(cs, code, code_len); else bpf = fetch_cbpf(cs, code, code_len); if (bpf == NULL) return false; if (!getInstruction(cs, instr, bpf)) { cs_mem_free(bpf); return false; } *size = bpf->insn_size; cs_mem_free(bpf); return true; } #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFDisassembler.h000064400000000000000000000010610072674642500206430ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifndef CS_BPF_DISASSEMBLER_H #define CS_BPF_DISASSEMBLER_H #include "../../MCInst.h" typedef struct bpf_internal { uint16_t op; uint64_t k; /* for cBPF */ uint8_t jt; uint8_t jf; /* for eBPF */ uint8_t dst; uint8_t src; uint16_t offset; /* length of this bpf instruction */ uint8_t insn_size; } bpf_internal; bool BPF_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFInstPrinter.c000064400000000000000000000161130072674642500205060ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #include #include "BPFConstants.h" #include "BPFInstPrinter.h" #include "BPFMapping.h" static cs_bpf_op *expand_bpf_operands(cs_bpf *bpf) { /* assert(bpf->op_count < 3); */ return &bpf->operands[bpf->op_count++]; } static void push_op_reg(cs_bpf *bpf, bpf_op_type val, uint8_t ac_mode) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_REG; op->reg = val; op->access = ac_mode; } static void push_op_imm(cs_bpf *bpf, uint64_t val) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_IMM; op->imm = val; } static void push_op_off(cs_bpf *bpf, uint32_t val) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_OFF; op->off = val; } static void push_op_mem(cs_bpf *bpf, bpf_reg reg, uint32_t val) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_MEM; op->mem.base = reg; op->mem.disp = val; } static void push_op_mmem(cs_bpf *bpf, uint32_t val) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_MMEM; op->mmem = val; } static void push_op_msh(cs_bpf *bpf, uint32_t val) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_MSH; op->msh = val; } static void push_op_ext(cs_bpf *bpf, bpf_ext_type val) { cs_bpf_op *op = expand_bpf_operands(bpf); op->type = BPF_OP_EXT; op->ext = val; } static void convert_operands(MCInst *MI, cs_bpf *bpf) { unsigned opcode = MCInst_getOpcode(MI); unsigned mc_op_count = MCInst_getNumOperands(MI); MCOperand *op; MCOperand *op2; unsigned i; bpf->op_count = 0; if (BPF_CLASS(opcode) == BPF_CLASS_LD || BPF_CLASS(opcode) == BPF_CLASS_LDX) { switch (BPF_MODE(opcode)) { case BPF_MODE_IMM: push_op_imm(bpf, MCOperand_getImm(MCInst_getOperand(MI, 0))); break; case BPF_MODE_ABS: op = MCInst_getOperand(MI, 0); push_op_mem(bpf, BPF_REG_INVALID, (uint32_t)MCOperand_getImm(op)); break; case BPF_MODE_IND: op = MCInst_getOperand(MI, 0); op2 = MCInst_getOperand(MI, 1); push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2)); break; case BPF_MODE_MEM: if (EBPF_MODE(MI->csh)) { /* ldx{w,h,b,dw} dst, [src+off] */ push_op_reg(bpf, MCOperand_getReg(MCInst_getOperand(MI, 0)), CS_AC_WRITE); op = MCInst_getOperand(MI, 1); op2 = MCInst_getOperand(MI, 2); push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2)); } else { push_op_mmem(bpf, (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, 0))); } break; case BPF_MODE_LEN: push_op_ext(bpf, BPF_EXT_LEN); break; case BPF_MODE_MSH: op = MCInst_getOperand(MI, 0); push_op_msh(bpf, (uint32_t)MCOperand_getImm(op)); break; /* case BPF_MODE_XADD: // not exists */ } return; } if (BPF_CLASS(opcode) == BPF_CLASS_ST || BPF_CLASS(opcode) == BPF_CLASS_STX) { if (!EBPF_MODE(MI->csh)) { // cBPF has only one case - st* M[k] push_op_mmem(bpf, (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, 0))); return; } /* eBPF has two cases: * - st [dst + off], src * - xadd [dst + off], src * they have same form of operands. */ op = MCInst_getOperand(MI, 0); op2 = MCInst_getOperand(MI, 1); push_op_mem(bpf, MCOperand_getReg(op), (uint32_t)MCOperand_getImm(op2)); op = MCInst_getOperand(MI, 2); if (MCOperand_isImm(op)) push_op_imm(bpf, MCOperand_getImm(op)); else if (MCOperand_isReg(op)) push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ); return; } if (BPF_CLASS(opcode) == BPF_CLASS_JMP) { for (i = 0; i < mc_op_count; i++) { op = MCInst_getOperand(MI, i); if (MCOperand_isImm(op)) { /* decide the imm is BPF_OP_IMM or BPF_OP_OFF type here */ /* * 1. ja +off * 2. j {x,k}, +jt, +jf // cBPF * 3. j dst_reg, {src_reg, k}, +off // eBPF */ if (BPF_OP(opcode) == BPF_JUMP_JA || (!EBPF_MODE(MI->csh) && i >= 1) || (EBPF_MODE(MI->csh) && i == 2)) push_op_off(bpf, (uint32_t)MCOperand_getImm(op)); else push_op_imm(bpf, MCOperand_getImm(op)); } else if (MCOperand_isReg(op)) { push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ); } } return; } if (!EBPF_MODE(MI->csh)) { /* In cBPF mode, all registers in operands are accessed as read */ for (i = 0; i < mc_op_count; i++) { op = MCInst_getOperand(MI, i); if (MCOperand_isImm(op)) push_op_imm(bpf, MCOperand_getImm(op)); else if (MCOperand_isReg(op)) push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ); } return; } /* remain cases are: eBPF mode && ALU */ /* if (BPF_CLASS(opcode) == BPF_CLASS_ALU || BPF_CLASS(opcode) == BPF_CLASS_ALU64) */ /* We have three types: * 1. {l,b}e dst // dst = byteswap(dst) * 2. neg dst // dst = -dst * 3. dst, {src_reg, imm} // dst = dst src * so we can simply check the number of operands, * exactly one operand means we are in case 1. and 2., * otherwise in case 3. */ if (mc_op_count == 1) { op = MCInst_getOperand(MI, 0); push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ | CS_AC_WRITE); } else { // if (mc_op_count == 2) op = MCInst_getOperand(MI, 0); push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ | CS_AC_WRITE); op = MCInst_getOperand(MI, 1); if (MCOperand_isImm(op)) push_op_imm(bpf, MCOperand_getImm(op)); else if (MCOperand_isReg(op)) push_op_reg(bpf, MCOperand_getReg(op), CS_AC_READ); } } static void print_operand(MCInst *MI, struct SStream *O, const cs_bpf_op *op) { switch (op->type) { case BPF_OP_INVALID: SStream_concat(O, "invalid"); break; case BPF_OP_REG: SStream_concat(O, BPF_reg_name((csh)MI->csh, op->reg)); break; case BPF_OP_IMM: SStream_concat(O, "0x%" PRIx64, op->imm); break; case BPF_OP_OFF: SStream_concat(O, "+0x%x", op->off); break; case BPF_OP_MEM: SStream_concat(O, "["); if (op->mem.base != BPF_REG_INVALID) SStream_concat(O, BPF_reg_name((csh)MI->csh, op->mem.base)); if (op->mem.disp != 0) { if (op->mem.base != BPF_REG_INVALID) SStream_concat(O, "+"); SStream_concat(O, "0x%x", op->mem.disp); } if (op->mem.base == BPF_REG_INVALID && op->mem.disp == 0) // special case SStream_concat(O, "0x0"); SStream_concat(O, "]"); break; case BPF_OP_MMEM: SStream_concat(O, "m[0x%x]", op->mmem); break; case BPF_OP_MSH: SStream_concat(O, "4*([0x%x]&0xf)", op->msh); break; case BPF_OP_EXT: switch (op->ext) { case BPF_EXT_LEN: SStream_concat(O, "#len"); break; } break; } } /* * 1. human readable mnemonic * 2. set pubOpcode (BPF_INSN_*) * 3. set detail->bpf.operands * */ void BPF_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) { int i; cs_insn insn; cs_bpf bpf; insn.detail = NULL; /* set pubOpcode as instruction id */ BPF_get_insn_id((cs_struct*)MI->csh, &insn, MCInst_getOpcode(MI)); MCInst_setOpcodePub(MI, insn.id); SStream_concat(O, BPF_insn_name((csh)MI->csh, insn.id)); convert_operands(MI, &bpf); for (i = 0; i < bpf.op_count; i++) { if (i == 0) SStream_concat(O, "\t"); else SStream_concat(O, ", "); print_operand(MI, O, &bpf.operands[i]); } #ifndef CAPSTONE_DIET if (MI->flat_insn->detail) { MI->flat_insn->detail->bpf = bpf; } #endif } capstone-sys-0.15.0/capstone/arch/BPF/BPFInstPrinter.h000064400000000000000000000005050072674642500205110ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifndef CS_BPFINSTPRINTER_H #define CS_BPFINSTPRINTER_H #include #include "../../MCInst.h" #include "../../SStream.h" struct SStream; void BPF_printInst(MCInst *MI, struct SStream *O, void *Info); #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFMapping.c000064400000000000000000000247670072674642500176360ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #include #include "BPFConstants.h" #include "BPFMapping.h" #include "../../utils.h" #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { { BPF_GRP_INVALID, NULL }, { BPF_GRP_LOAD, "load" }, { BPF_GRP_STORE, "store" }, { BPF_GRP_ALU, "alu" }, { BPF_GRP_JUMP, "jump" }, { BPF_GRP_CALL, "call" }, { BPF_GRP_RETURN, "return" }, { BPF_GRP_MISC, "misc" }, }; #endif const char *BPF_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[BPF_INS_ENDING] = { { BPF_INS_INVALID, NULL }, { BPF_INS_ADD, "add" }, { BPF_INS_SUB, "sub" }, { BPF_INS_MUL, "mul" }, { BPF_INS_DIV, "div" }, { BPF_INS_OR, "or" }, { BPF_INS_AND, "and" }, { BPF_INS_LSH, "lsh" }, { BPF_INS_RSH, "rsh" }, { BPF_INS_NEG, "neg" }, { BPF_INS_MOD, "mod" }, { BPF_INS_XOR, "xor" }, { BPF_INS_MOV, "mov" }, { BPF_INS_ARSH, "arsh" }, { BPF_INS_ADD64, "add64" }, { BPF_INS_SUB64, "sub64" }, { BPF_INS_MUL64, "mul64" }, { BPF_INS_DIV64, "div64" }, { BPF_INS_OR64, "or64" }, { BPF_INS_AND64, "and64" }, { BPF_INS_LSH64, "lsh64" }, { BPF_INS_RSH64, "rsh64" }, { BPF_INS_NEG64, "neg64" }, { BPF_INS_MOD64, "mod64" }, { BPF_INS_XOR64, "xor64" }, { BPF_INS_MOV64, "mov64" }, { BPF_INS_ARSH64, "arsh64" }, { BPF_INS_LE16, "le16" }, { BPF_INS_LE32, "le32" }, { BPF_INS_LE64, "le64" }, { BPF_INS_BE16, "be16" }, { BPF_INS_BE32, "be32" }, { BPF_INS_BE64, "be64" }, { BPF_INS_LDW, "ldw" }, { BPF_INS_LDH, "ldh" }, { BPF_INS_LDB, "ldb" }, { BPF_INS_LDDW, "lddw" }, { BPF_INS_LDXW, "ldxw" }, { BPF_INS_LDXH, "ldxh" }, { BPF_INS_LDXB, "ldxb" }, { BPF_INS_LDXDW, "ldxdw" }, { BPF_INS_STW, "stw" }, { BPF_INS_STH, "sth" }, { BPF_INS_STB, "stb" }, { BPF_INS_STDW, "stdw" }, { BPF_INS_STXW, "stxw" }, { BPF_INS_STXH, "stxh" }, { BPF_INS_STXB, "stxb" }, { BPF_INS_STXDW, "stxdw" }, { BPF_INS_XADDW, "xaddw" }, { BPF_INS_XADDDW, "xadddw" }, { BPF_INS_JMP, "jmp" }, { BPF_INS_JEQ, "jeq" }, { BPF_INS_JGT, "jgt" }, { BPF_INS_JGE, "jge" }, { BPF_INS_JSET, "jset" }, { BPF_INS_JNE, "jne" }, { BPF_INS_JSGT, "jsgt" }, { BPF_INS_JSGE, "jsge" }, { BPF_INS_CALL, "call" }, { BPF_INS_EXIT, "exit" }, { BPF_INS_JLT, "jlt" }, { BPF_INS_JLE, "jle" }, { BPF_INS_JSLT, "jslt" }, { BPF_INS_JSLE, "jsle" }, { BPF_INS_RET, "ret" }, { BPF_INS_TAX, "tax" }, { BPF_INS_TXA, "txa" }, }; #endif const char *BPF_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET /* We have some special cases because 'ld' in cBPF is equivalent to 'ldw' * in eBPF, and we don't want to see 'ldw' appears in cBPF mode. */ if (!EBPF_MODE(handle)) { switch (id) { case BPF_INS_LD: return "ld"; case BPF_INS_LDX: return "ldx"; case BPF_INS_ST: return "st"; case BPF_INS_STX: return "stx"; } } return id2name(insn_name_maps, ARR_SIZE(insn_name_maps), id); #else return NULL; #endif } const char *BPF_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (EBPF_MODE(handle)) { if (reg < BPF_REG_R0 || reg > BPF_REG_R10) return NULL; static const char reg_names[11][4] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" }; return reg_names[reg - BPF_REG_R0]; } /* cBPF mode */ if (reg == BPF_REG_A) return "a"; else if (reg == BPF_REG_X) return "x"; else return NULL; #else return NULL; #endif } static bpf_insn op2insn_ld(unsigned opcode) { #define CASE(c) case BPF_SIZE_##c: \ if (BPF_CLASS(opcode) == BPF_CLASS_LD) \ return BPF_INS_LD##c; \ else \ return BPF_INS_LDX##c; switch (BPF_SIZE(opcode)) { CASE(W); CASE(H); CASE(B); CASE(DW); } #undef CASE return BPF_INS_INVALID; } static bpf_insn op2insn_st(unsigned opcode) { /* * - BPF_STX | BPF_XADD | BPF_{W,DW} * - BPF_ST* | BPF_MEM | BPF_{W,H,B,DW} */ if (opcode == (BPF_CLASS_STX | BPF_MODE_XADD | BPF_SIZE_W)) return BPF_INS_XADDW; if (opcode == (BPF_CLASS_STX | BPF_MODE_XADD | BPF_SIZE_DW)) return BPF_INS_XADDDW; /* should be BPF_MEM */ #define CASE(c) case BPF_SIZE_##c: \ if (BPF_CLASS(opcode) == BPF_CLASS_ST) \ return BPF_INS_ST##c; \ else \ return BPF_INS_STX##c; switch (BPF_SIZE(opcode)) { CASE(W); CASE(H); CASE(B); CASE(DW); } #undef CASE return BPF_INS_INVALID; } static bpf_insn op2insn_alu(unsigned opcode) { /* Endian is a special case */ if (BPF_OP(opcode) == BPF_ALU_END) { switch (opcode ^ BPF_CLASS_ALU ^ BPF_ALU_END) { case BPF_SRC_LITTLE | (16 << 4): return BPF_INS_LE16; case BPF_SRC_LITTLE | (32 << 4): return BPF_INS_LE32; case BPF_SRC_LITTLE | (64 << 4): return BPF_INS_LE64; case BPF_SRC_BIG | (16 << 4): return BPF_INS_BE16; case BPF_SRC_BIG | (32 << 4): return BPF_INS_BE32; case BPF_SRC_BIG | (64 << 4): return BPF_INS_BE64; } return BPF_INS_INVALID; } #define CASE(c) case BPF_ALU_##c: \ if (BPF_CLASS(opcode) == BPF_CLASS_ALU) \ return BPF_INS_##c; \ else \ return BPF_INS_##c##64; switch (BPF_OP(opcode)) { CASE(ADD); CASE(SUB); CASE(MUL); CASE(DIV); CASE(OR); CASE(AND); CASE(LSH); CASE(RSH); CASE(NEG); CASE(MOD); CASE(XOR); CASE(MOV); CASE(ARSH); } #undef CASE return BPF_INS_INVALID; } static bpf_insn op2insn_jmp(unsigned opcode) { #define CASE(c) case BPF_JUMP_##c: return BPF_INS_##c switch (BPF_OP(opcode)) { case BPF_JUMP_JA: return BPF_INS_JMP; CASE(JEQ); CASE(JGT); CASE(JGE); CASE(JSET); CASE(JNE); CASE(JSGT); CASE(JSGE); CASE(CALL); CASE(EXIT); CASE(JLT); CASE(JLE); CASE(JSLT); CASE(JSLE); } #undef CASE return BPF_INS_INVALID; } static void update_regs_access(cs_struct *ud, cs_detail *detail, bpf_insn insn_id, unsigned int opcode) { if (insn_id == BPF_INS_INVALID) return; #define PUSH_READ(r) do { \ detail->regs_read[detail->regs_read_count] = r; \ detail->regs_read_count++; \ } while (0) #define PUSH_WRITE(r) do { \ detail->regs_write[detail->regs_write_count] = r; \ detail->regs_write_count++; \ } while (0) /* * In eBPF mode, only these instructions have implicit registers access: * - ld{w,h,b,dw} * // w: r0 * - exit // r: r0 */ if (EBPF_MODE(ud)) { switch (insn_id) { default: break; case BPF_INS_LDW: case BPF_INS_LDH: case BPF_INS_LDB: case BPF_INS_LDDW: PUSH_WRITE(BPF_REG_R0); break; case BPF_INS_EXIT: PUSH_READ(BPF_REG_R0); break; } return; } /* cBPF mode */ switch (BPF_CLASS(opcode)) { default: break; case BPF_CLASS_LD: PUSH_WRITE(BPF_REG_A); break; case BPF_CLASS_LDX: PUSH_WRITE(BPF_REG_X); break; case BPF_CLASS_ST: PUSH_READ(BPF_REG_A); break; case BPF_CLASS_STX: PUSH_READ(BPF_REG_X); break; case BPF_CLASS_ALU: PUSH_READ(BPF_REG_A); PUSH_WRITE(BPF_REG_A); break; case BPF_CLASS_JMP: if (insn_id != BPF_INS_JMP) // except the unconditional jump PUSH_READ(BPF_REG_A); break; /* case BPF_CLASS_RET: */ case BPF_CLASS_MISC: if (insn_id == BPF_INS_TAX) { PUSH_READ(BPF_REG_A); PUSH_WRITE(BPF_REG_X); } else { PUSH_READ(BPF_REG_X); PUSH_WRITE(BPF_REG_A); } break; } } /* * 1. Convert opcode(id) to BPF_INS_* * 2. Set regs_read/regs_write/groups */ void BPF_get_insn_id(cs_struct *ud, cs_insn *insn, unsigned int opcode) { // No need to care the mode (cBPF or eBPF) since all checks has be done in // BPF_getInstruction, we can simply map opcode to BPF_INS_*. cs_detail *detail; bpf_insn id = BPF_INS_INVALID; bpf_insn_group grp; detail = insn->detail; #ifndef CAPSTONE_DIET #define PUSH_GROUP(grp) do { \ if (detail) { \ detail->groups[detail->groups_count] = grp; \ detail->groups_count++; \ } \ } while(0) #else #define PUSH_GROUP #endif switch (BPF_CLASS(opcode)) { default: // will never happen break; case BPF_CLASS_LD: case BPF_CLASS_LDX: id = op2insn_ld(opcode); PUSH_GROUP(BPF_GRP_LOAD); break; case BPF_CLASS_ST: case BPF_CLASS_STX: id = op2insn_st(opcode); PUSH_GROUP(BPF_GRP_STORE); break; case BPF_CLASS_ALU: id = op2insn_alu(opcode); PUSH_GROUP(BPF_GRP_ALU); break; case BPF_CLASS_JMP: grp = BPF_GRP_JUMP; id = op2insn_jmp(opcode); if (id == BPF_INS_CALL) grp = BPF_GRP_CALL; else if (id == BPF_INS_EXIT) grp = BPF_GRP_RETURN; PUSH_GROUP(grp); break; case BPF_CLASS_RET: id = BPF_INS_RET; PUSH_GROUP(BPF_GRP_RETURN); break; // BPF_CLASS_MISC and BPF_CLASS_ALU64 have exactly same value case BPF_CLASS_MISC: /* case BPF_CLASS_ALU64: */ if (EBPF_MODE(ud)) { // ALU64 in eBPF id = op2insn_alu(opcode); PUSH_GROUP(BPF_GRP_ALU); } else { if (BPF_MISCOP(opcode) == BPF_MISCOP_TXA) id = BPF_INS_TXA; else id = BPF_INS_TAX; PUSH_GROUP(BPF_GRP_MISC); } break; } insn->id = id; #undef PUSH_GROUP #ifndef CAPSTONE_DIET if (detail) { update_regs_access(ud, detail, id, opcode); } #endif } static void sort_and_uniq(cs_regs arr, uint8_t n, uint8_t *new_n) { /* arr is always a tiny (usually n < 3) array, * a simple O(n^2) sort is efficient enough. */ int i; int j; int iMin; int tmp; /* a modified selection sort for sorting and making unique */ for (j = 0; j < n; j++) { /* arr[iMin] will be min(arr[j .. n-1]) */ iMin = j; for (i = j + 1; i < n; i++) { if (arr[i] < arr[iMin]) iMin = i; } if (j != 0 && arr[iMin] == arr[j - 1]) { // duplicate ele found arr[iMin] = arr[n - 1]; --n; } else { tmp = arr[iMin]; arr[iMin] = arr[j]; arr[j] = tmp; } } *new_n = n; } void BPF_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count) { unsigned i; uint8_t read_count, write_count; const cs_bpf *bpf = &(insn->detail->bpf); read_count = insn->detail->regs_read_count; write_count = insn->detail->regs_write_count; // implicit registers memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); for (i = 0; i < bpf->op_count; i++) { const cs_bpf_op *op = &(bpf->operands[i]); switch (op->type) { default: break; case BPF_OP_REG: if (op->access & CS_AC_READ) { regs_read[read_count] = op->reg; read_count++; } if (op->access & CS_AC_WRITE) { regs_write[write_count] = op->reg; write_count++; } break; case BPF_OP_MEM: if (op->mem.base != BPF_REG_INVALID) { regs_read[read_count] = op->mem.base; read_count++; } break; } } sort_and_uniq(regs_read, read_count, regs_read_count); sort_and_uniq(regs_write, write_count, regs_write_count); } capstone-sys-0.15.0/capstone/arch/BPF/BPFMapping.h000064400000000000000000000012210072674642500176170ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifndef CS_BPFMAPPING_H #define CS_BPFMAPPING_H #include #include "../../cs_priv.h" #define EBPF_MODE(ud) (((cs_struct*)ud)->mode & CS_MODE_BPF_EXTENDED) const char *BPF_group_name(csh handle, unsigned int id); const char *BPF_insn_name(csh handle, unsigned int id); const char *BPF_reg_name(csh handle, unsigned int reg); void BPF_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); void BPF_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFModule.c000064400000000000000000000012760072674642500174560ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifdef CAPSTONE_HAS_BPF #include "BPFDisassembler.h" #include "BPFInstPrinter.h" #include "BPFMapping.h" #include "BPFModule.h" cs_err BPF_global_init(cs_struct *ud) { ud->printer = BPF_printInst; ud->reg_name = BPF_reg_name; ud->insn_id = BPF_get_insn_id; ud->insn_name = BPF_insn_name; ud->group_name = BPF_group_name; #ifndef CAPSTONE_DIET ud->reg_access = BPF_reg_access; #endif ud->disasm = BPF_getInstruction; return CS_ERR_OK; } cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_MODE) handle->mode = (cs_mode)value; return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/BPF/BPFModule.h000064400000000000000000000004360072674642500174600ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifndef CS_BPF_MODULE_H #define CS_BPF_MODULE_H #include "../../utils.h" cs_err BPF_global_init(cs_struct *ud); cs_err BPF_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/EVM/EVMDisassembler.c000064400000000000000000000137430072674642500207100ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #include #include // offsetof macro // alternatively #include "../../utils.h" like everyone else #include "EVMDisassembler.h" #include "EVMMapping.h" static const short opcodes[256] = { EVM_INS_STOP, EVM_INS_ADD, EVM_INS_MUL, EVM_INS_SUB, EVM_INS_DIV, EVM_INS_SDIV, EVM_INS_MOD, EVM_INS_SMOD, EVM_INS_ADDMOD, EVM_INS_MULMOD, EVM_INS_EXP, EVM_INS_SIGNEXTEND, -1, -1, -1, -1, EVM_INS_LT, EVM_INS_GT, EVM_INS_SLT, EVM_INS_SGT, EVM_INS_EQ, EVM_INS_ISZERO, EVM_INS_AND, EVM_INS_OR, EVM_INS_XOR, EVM_INS_NOT, EVM_INS_BYTE, -1, -1, -1, -1, -1, EVM_INS_SHA3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, EVM_INS_ADDRESS, EVM_INS_BALANCE, EVM_INS_ORIGIN, EVM_INS_CALLER, EVM_INS_CALLVALUE, EVM_INS_CALLDATALOAD, EVM_INS_CALLDATASIZE, EVM_INS_CALLDATACOPY, EVM_INS_CODESIZE, EVM_INS_CODECOPY, EVM_INS_GASPRICE, EVM_INS_EXTCODESIZE, EVM_INS_EXTCODECOPY, EVM_INS_RETURNDATASIZE, EVM_INS_RETURNDATACOPY, -1, EVM_INS_BLOCKHASH, EVM_INS_COINBASE, EVM_INS_TIMESTAMP, EVM_INS_NUMBER, EVM_INS_DIFFICULTY, EVM_INS_GASLIMIT, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, EVM_INS_POP, EVM_INS_MLOAD, EVM_INS_MSTORE, EVM_INS_MSTORE8, EVM_INS_SLOAD, EVM_INS_SSTORE, EVM_INS_JUMP, EVM_INS_JUMPI, EVM_INS_PC, EVM_INS_MSIZE, EVM_INS_GAS, EVM_INS_JUMPDEST, -1, -1, -1, -1, EVM_INS_PUSH1, EVM_INS_PUSH2, EVM_INS_PUSH3, EVM_INS_PUSH4, EVM_INS_PUSH5, EVM_INS_PUSH6, EVM_INS_PUSH7, EVM_INS_PUSH8, EVM_INS_PUSH9, EVM_INS_PUSH10, EVM_INS_PUSH11, EVM_INS_PUSH12, EVM_INS_PUSH13, EVM_INS_PUSH14, EVM_INS_PUSH15, EVM_INS_PUSH16, EVM_INS_PUSH17, EVM_INS_PUSH18, EVM_INS_PUSH19, EVM_INS_PUSH20, EVM_INS_PUSH21, EVM_INS_PUSH22, EVM_INS_PUSH23, EVM_INS_PUSH24, EVM_INS_PUSH25, EVM_INS_PUSH26, EVM_INS_PUSH27, EVM_INS_PUSH28, EVM_INS_PUSH29, EVM_INS_PUSH30, EVM_INS_PUSH31, EVM_INS_PUSH32, EVM_INS_DUP1, EVM_INS_DUP2, EVM_INS_DUP3, EVM_INS_DUP4, EVM_INS_DUP5, EVM_INS_DUP6, EVM_INS_DUP7, EVM_INS_DUP8, EVM_INS_DUP9, EVM_INS_DUP10, EVM_INS_DUP11, EVM_INS_DUP12, EVM_INS_DUP13, EVM_INS_DUP14, EVM_INS_DUP15, EVM_INS_DUP16, EVM_INS_SWAP1, EVM_INS_SWAP2, EVM_INS_SWAP3, EVM_INS_SWAP4, EVM_INS_SWAP5, EVM_INS_SWAP6, EVM_INS_SWAP7, EVM_INS_SWAP8, EVM_INS_SWAP9, EVM_INS_SWAP10, EVM_INS_SWAP11, EVM_INS_SWAP12, EVM_INS_SWAP13, EVM_INS_SWAP14, EVM_INS_SWAP15, EVM_INS_SWAP16, EVM_INS_LOG0, EVM_INS_LOG1, EVM_INS_LOG2, EVM_INS_LOG3, EVM_INS_LOG4, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, EVM_INS_CREATE, EVM_INS_CALL, EVM_INS_CALLCODE, EVM_INS_RETURN, EVM_INS_DELEGATECALL, EVM_INS_CALLBLACKBOX, -1, -1, -1, -1, EVM_INS_STATICCALL, -1, -1, EVM_INS_REVERT, -1, EVM_INS_SUICIDE, }; bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) { unsigned char opcode; if (code_len == 0) return false; opcode = code[0]; if (opcodes[opcode] == -1) { // invalid opcode return false; } // valid opcode MI->address = address; MI->OpcodePub = MI->Opcode = opcode; if (opcode >= EVM_INS_PUSH1 && opcode <= EVM_INS_PUSH32) { unsigned char len = (opcode - EVM_INS_PUSH1 + 1); if (code_len < 1 + len) { // not enough data return false; } *size = 1 + len; memcpy(MI->evm_data, code + 1, len); } else *size = 1; if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, evm)+sizeof(cs_evm)); EVM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode); if (MI->flat_insn->detail->evm.pop) { MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_READ; MI->flat_insn->detail->groups_count++; } if (MI->flat_insn->detail->evm.push) { MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_WRITE; MI->flat_insn->detail->groups_count++; } // setup groups switch(opcode) { default: break; case EVM_INS_ADD: case EVM_INS_MUL: case EVM_INS_SUB: case EVM_INS_DIV: case EVM_INS_SDIV: case EVM_INS_MOD: case EVM_INS_SMOD: case EVM_INS_ADDMOD: case EVM_INS_MULMOD: case EVM_INS_EXP: case EVM_INS_SIGNEXTEND: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MATH; MI->flat_insn->detail->groups_count++; break; case EVM_INS_MSTORE: case EVM_INS_MSTORE8: case EVM_INS_CALLDATACOPY: case EVM_INS_CODECOPY: case EVM_INS_EXTCODECOPY: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_WRITE; MI->flat_insn->detail->groups_count++; break; case EVM_INS_MLOAD: case EVM_INS_CREATE: case EVM_INS_CALL: case EVM_INS_CALLCODE: case EVM_INS_RETURN: case EVM_INS_DELEGATECALL: case EVM_INS_REVERT: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_READ; MI->flat_insn->detail->groups_count++; break; case EVM_INS_SSTORE: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_WRITE; MI->flat_insn->detail->groups_count++; break; case EVM_INS_SLOAD: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_READ; MI->flat_insn->detail->groups_count++; break; case EVM_INS_JUMP: case EVM_INS_JUMPI: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_JUMP; MI->flat_insn->detail->groups_count++; break; case EVM_INS_STOP: case EVM_INS_SUICIDE: MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_HALT; MI->flat_insn->detail->groups_count++; break; } } return true; } capstone-sys-0.15.0/capstone/arch/EVM/EVMDisassembler.h000064400000000000000000000004470072674642500207120ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #ifndef CS_EVMDISASSEMBLER_H #define CS_EVMDISASSEMBLER_H #include "../../MCInst.h" bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/EVM/EVMInstPrinter.c000064400000000000000000000007420072674642500205470ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #include "EVMInstPrinter.h" #include "EVMMapping.h" void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) { SStream_concat(O, EVM_insn_name((csh)MI->csh, MI->Opcode)); if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) { unsigned int i; SStream_concat0(O, "\t"); for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) { SStream_concat(O, "%02x", MI->evm_data[i]); } } } capstone-sys-0.15.0/capstone/arch/EVM/EVMInstPrinter.h000064400000000000000000000005050072674642500205510ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #ifndef CS_EVMINSTPRINTER_H #define CS_EVMINSTPRINTER_H #include "capstone/capstone.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../cs_priv.h" struct SStream; void EVM_printInst(MCInst *MI, struct SStream *O, void *Info); #endif capstone-sys-0.15.0/capstone/arch/EVM/EVMMapping.c000064400000000000000000000220600072674642500176560ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #ifdef CAPSTONE_HAS_EVM #include #include "../../cs_priv.h" #include "../../utils.h" #include "EVMMapping.h" #ifndef CAPSTONE_DIET static const cs_evm insns[256] = { #include "EVMMappingInsn.inc" }; #endif // look for @id in @insns, given its size in @max. // return -1 if not found static int evm_insn_find(const cs_evm *insns, unsigned int max, unsigned int id) { if (id >= max) return -1; if (insns[id].fee == 0xffffffff) // unused opcode return -1; return (int)id; } // fill in details void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { insn->id = id; #ifndef CAPSTONE_DIET if (evm_insn_find(insns, ARR_SIZE(insns), id) > 0) { if (h->detail) { memcpy(&insn->detail->evm, &insns[id], sizeof(insns[id])); } } #endif } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[256] = { { EVM_INS_STOP, "stop" }, { EVM_INS_ADD, "add" }, { EVM_INS_MUL, "mul" }, { EVM_INS_SUB, "sub" }, { EVM_INS_DIV, "div" }, { EVM_INS_SDIV, "sdiv" }, { EVM_INS_MOD, "mod" }, { EVM_INS_SMOD, "smod" }, { EVM_INS_ADDMOD, "addmod" }, { EVM_INS_MULMOD, "mulmod" }, { EVM_INS_EXP, "exp" }, { EVM_INS_SIGNEXTEND, "signextend" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_LT, "lt" }, { EVM_INS_GT, "gt" }, { EVM_INS_SLT, "slt" }, { EVM_INS_SGT, "sgt" }, { EVM_INS_EQ, "eq" }, { EVM_INS_ISZERO, "iszero" }, { EVM_INS_AND, "and" }, { EVM_INS_OR, "or" }, { EVM_INS_XOR, "xor" }, { EVM_INS_NOT, "not" }, { EVM_INS_BYTE, "byte" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_SHA3, "sha3" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_ADDRESS, "address" }, { EVM_INS_BALANCE, "balance" }, { EVM_INS_ORIGIN, "origin" }, { EVM_INS_CALLER, "caller" }, { EVM_INS_CALLVALUE, "callvalue" }, { EVM_INS_CALLDATALOAD, "calldataload" }, { EVM_INS_CALLDATASIZE, "calldatasize" }, { EVM_INS_CALLDATACOPY, "calldatacopy" }, { EVM_INS_CODESIZE, "codesize" }, { EVM_INS_CODECOPY, "codecopy" }, { EVM_INS_GASPRICE, "gasprice" }, { EVM_INS_EXTCODESIZE, "extcodesize" }, { EVM_INS_EXTCODECOPY, "extcodecopy" }, { EVM_INS_RETURNDATASIZE, "returndatasize" }, { EVM_INS_RETURNDATACOPY, "returndatacopy" }, { EVM_INS_INVALID, NULL }, { EVM_INS_BLOCKHASH, "blockhash" }, { EVM_INS_COINBASE, "coinbase" }, { EVM_INS_TIMESTAMP, "timestamp" }, { EVM_INS_NUMBER, "number" }, { EVM_INS_DIFFICULTY, "difficulty" }, { EVM_INS_GASLIMIT, "gaslimit" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_POP, "pop" }, { EVM_INS_MLOAD, "mload" }, { EVM_INS_MSTORE, "mstore" }, { EVM_INS_MSTORE8, "mstore8" }, { EVM_INS_SLOAD, "sload" }, { EVM_INS_SSTORE, "sstore" }, { EVM_INS_JUMP, "jump" }, { EVM_INS_JUMPI, "jumpi" }, { EVM_INS_PC, "pc" }, { EVM_INS_MSIZE, "msize" }, { EVM_INS_GAS, "gas" }, { EVM_INS_JUMPDEST, "jumpdest" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_PUSH1, "push1" }, { EVM_INS_PUSH2, "push2" }, { EVM_INS_PUSH3, "push3" }, { EVM_INS_PUSH4, "push4" }, { EVM_INS_PUSH5, "push5" }, { EVM_INS_PUSH6, "push6" }, { EVM_INS_PUSH7, "push7" }, { EVM_INS_PUSH8, "push8" }, { EVM_INS_PUSH9, "push9" }, { EVM_INS_PUSH10, "push10" }, { EVM_INS_PUSH11, "push11" }, { EVM_INS_PUSH12, "push12" }, { EVM_INS_PUSH13, "push13" }, { EVM_INS_PUSH14, "push14" }, { EVM_INS_PUSH15, "push15" }, { EVM_INS_PUSH16, "push16" }, { EVM_INS_PUSH17, "push17" }, { EVM_INS_PUSH18, "push18" }, { EVM_INS_PUSH19, "push19" }, { EVM_INS_PUSH20, "push20" }, { EVM_INS_PUSH21, "push21" }, { EVM_INS_PUSH22, "push22" }, { EVM_INS_PUSH23, "push23" }, { EVM_INS_PUSH24, "push24" }, { EVM_INS_PUSH25, "push25" }, { EVM_INS_PUSH26, "push26" }, { EVM_INS_PUSH27, "push27" }, { EVM_INS_PUSH28, "push28" }, { EVM_INS_PUSH29, "push29" }, { EVM_INS_PUSH30, "push30" }, { EVM_INS_PUSH31, "push31" }, { EVM_INS_PUSH32, "push32" }, { EVM_INS_DUP1, "dup1" }, { EVM_INS_DUP2, "dup2" }, { EVM_INS_DUP3, "dup3" }, { EVM_INS_DUP4, "dup4" }, { EVM_INS_DUP5, "dup5" }, { EVM_INS_DUP6, "dup6" }, { EVM_INS_DUP7, "dup7" }, { EVM_INS_DUP8, "dup8" }, { EVM_INS_DUP9, "dup9" }, { EVM_INS_DUP10, "dup10" }, { EVM_INS_DUP11, "dup11" }, { EVM_INS_DUP12, "dup12" }, { EVM_INS_DUP13, "dup13" }, { EVM_INS_DUP14, "dup14" }, { EVM_INS_DUP15, "dup15" }, { EVM_INS_DUP16, "dup16" }, { EVM_INS_SWAP1, "swap1" }, { EVM_INS_SWAP2, "swap2" }, { EVM_INS_SWAP3, "swap3" }, { EVM_INS_SWAP4, "swap4" }, { EVM_INS_SWAP5, "swap5" }, { EVM_INS_SWAP6, "swap6" }, { EVM_INS_SWAP7, "swap7" }, { EVM_INS_SWAP8, "swap8" }, { EVM_INS_SWAP9, "swap9" }, { EVM_INS_SWAP10, "swap10" }, { EVM_INS_SWAP11, "swap11" }, { EVM_INS_SWAP12, "swap12" }, { EVM_INS_SWAP13, "swap13" }, { EVM_INS_SWAP14, "swap14" }, { EVM_INS_SWAP15, "swap15" }, { EVM_INS_SWAP16, "swap16" }, { EVM_INS_LOG0, "log0" }, { EVM_INS_LOG1, "log1" }, { EVM_INS_LOG2, "log2" }, { EVM_INS_LOG3, "log3" }, { EVM_INS_LOG4, "log4" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_CREATE, "create" }, { EVM_INS_CALL, "call" }, { EVM_INS_CALLCODE, "callcode" }, { EVM_INS_RETURN, "return" }, { EVM_INS_DELEGATECALL, "delegatecall" }, { EVM_INS_CALLBLACKBOX, "callblackbox" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_STATICCALL, "staticcall" }, { EVM_INS_INVALID, NULL }, { EVM_INS_INVALID, NULL }, { EVM_INS_REVERT, "revert" }, { EVM_INS_INVALID, NULL }, { EVM_INS_SUICIDE, "suicide" }, }; #endif const char *EVM_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= ARR_SIZE(insn_name_maps)) return NULL; else return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { EVM_GRP_INVALID, NULL }, { EVM_GRP_JUMP, "jump" }, // special groups { EVM_GRP_MATH, "math" }, { EVM_GRP_STACK_WRITE, "stack_write" }, { EVM_GRP_STACK_READ, "stack_read" }, { EVM_GRP_MEM_WRITE, "mem_write" }, { EVM_GRP_MEM_READ, "mem_read" }, { EVM_GRP_STORE_WRITE, "store_write" }, { EVM_GRP_STORE_READ, "store_read" }, { EVM_GRP_HALT, "halt" }, }; #endif const char *EVM_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } #endif capstone-sys-0.15.0/capstone/arch/EVM/EVMMapping.h000064400000000000000000000004300072674642500176600ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #include void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *EVM_insn_name(csh handle, unsigned int id); const char *EVM_group_name(csh handle, unsigned int id); capstone-sys-0.15.0/capstone/arch/EVM/EVMMappingInsn.inc000064400000000000000000000156410072674642500210440ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ { 0, 0, 0 }, // STOP { 2, 1, 3 }, // ADD { 2, 1, 5 }, // MUL { 2, 1, 3 }, // SUB { 2, 1, 5 }, // DIV { 2, 1, 5 }, // SDIV { 2, 1, 5 }, // MOD { 2, 1, 5 }, // SMOD { 3, 1, 8 }, // ADDMOD { 3, 1, 8 }, // MULMOD { 2, 1, 10 }, // EXP { 2, 1, 5 }, // SIGNEXTEND { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 2, 1, 3 }, // LT { 2, 1, 3 }, // GT { 2, 1, 3 }, // SLT { 2, 1, 3 }, // SGT { 2, 1, 3 }, // EQ { 1, 1, 3 }, // ISZERO { 2, 1, 3 }, // AND { 2, 1, 3 }, // OR { 2, 1, 3 }, // XOR { 1, 1, 3 }, // NOT { 2, 1, 3 }, // BYTE { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 2, 1, 30 }, // SHA3 { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 1, 2 }, // ADDRESS { 1, 1, 20 }, // BALANCE { 0, 1, 2 }, // ORIGIN { 0, 1, 2 }, // CALLER { 0, 1, 2 }, // CALLVALUE { 1, 1, 3 }, // CALLDATALOAD { 0, 1, 2 }, // CALLDATASIZE { 3, 0, 3 }, // CALLDATACOPY { 0, 1, 2 }, // CODESIZE { 3, 0, 3 }, // CODECOPY { 0, 1, 2 }, // GASPRICE { 1, 1, 20 }, // EXTCODESIZE { 4, 0, 20 }, // EXTCODECOPY { 0, 1, 2 }, // RETURNDATASIZE { 3, 0, 3 }, // RETURNDATACOPY { 0, 0, 0xffffffff }, // unused { 1, 1, 20 }, // BLOCKHASH { 0, 1, 2 }, // COINBASE { 0, 1, 2 }, // TIMESTAMP { 0, 1, 2 }, // NUMBER { 0, 1, 2 }, // DIFFICULTY { 0, 1, 2 }, // GASLIMIT { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 1, 0, 2 }, // POP { 1, 1, 3 }, // MLOAD { 2, 0, 3 }, // MSTORE { 2, 0, 3 }, // MSTORE8 { 1, 1, 50 }, // SLOAD { 2, 0, 0 }, // SSTORE { 1, 0, 8 }, // JUMP { 2, 0, 10 }, // JUMPI { 0, 1, 2 }, // GETPC { 0, 1, 2 }, // MSIZE { 0, 1, 2 }, // GAS { 0, 0, 1 }, // JUMPDEST { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 1, 3 }, // PUSH1 { 0, 1, 3 }, // PUSH2 { 0, 1, 3 }, // PUSH3 { 0, 1, 3 }, // PUSH4 { 0, 1, 3 }, // PUSH5 { 0, 1, 3 }, // PUSH6 { 0, 1, 3 }, // PUSH7 { 0, 1, 3 }, // PUSH8 { 0, 1, 3 }, // PUSH9 { 0, 1, 3 }, // PUSH10 { 0, 1, 3 }, // PUSH11 { 0, 1, 3 }, // PUSH12 { 0, 1, 3 }, // PUSH13 { 0, 1, 3 }, // PUSH14 { 0, 1, 3 }, // PUSH15 { 0, 1, 3 }, // PUSH16 { 0, 1, 3 }, // PUSH17 { 0, 1, 3 }, // PUSH18 { 0, 1, 3 }, // PUSH19 { 0, 1, 3 }, // PUSH20 { 0, 1, 3 }, // PUSH21 { 0, 1, 3 }, // PUSH22 { 0, 1, 3 }, // PUSH23 { 0, 1, 3 }, // PUSH24 { 0, 1, 3 }, // PUSH25 { 0, 1, 3 }, // PUSH26 { 0, 1, 3 }, // PUSH27 { 0, 1, 3 }, // PUSH28 { 0, 1, 3 }, // PUSH29 { 0, 1, 3 }, // PUSH30 { 0, 1, 3 }, // PUSH31 { 0, 1, 3 }, // PUSH32 { 1, 2, 3 }, // DUP1 { 2, 3, 3 }, // DUP2 { 3, 4, 3 }, // DUP3 { 4, 5, 3 }, // DUP4 { 5, 6, 3 }, // DUP5 { 6, 7, 3 }, // DUP6 { 7, 8, 3 }, // DUP7 { 8, 9, 3 }, // DUP8 { 9, 10, 3 }, // DUP9 { 10, 11, 3 }, // DUP10 { 11, 12, 3 }, // DUP11 { 12, 13, 3 }, // DUP12 { 13, 14, 3 }, // DUP13 { 14, 15, 3 }, // DUP14 { 15, 16, 3 }, // DUP15 { 16, 17, 3 }, // DUP16 { 2, 2, 3 }, // SWAP1 { 3, 3, 3 }, // SWAP2 { 4, 4, 3 }, // SWAP3 { 5, 5, 3 }, // SWAP4 { 6, 6, 3 }, // SWAP5 { 7, 7, 3 }, // SWAP6 { 8, 8, 3 }, // SWAP7 { 9, 9, 3 }, // SWAP8 { 10, 10, 3 }, // SWAP9 { 11, 11, 3 }, // SWAP10 { 12, 12, 3 }, // SWAP11 { 13, 13, 3 }, // SWAP12 { 14, 14, 3 }, // SWAP13 { 15, 15, 3 }, // SWAP14 { 16, 16, 3 }, // SWAP15 { 17, 17, 3 }, // SWAP16 { 2, 0, 375 }, // LOG0 { 3, 0, 750 }, // LOG1 { 4, 0, 1125 }, // LOG2 { 5, 0, 1500 }, // LOG3 { 6, 0, 1875 }, // LOG4 { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 3, 1, 32000 }, // CREATE { 7, 1, 40 }, // CALL { 7, 1, 40 }, // CALLCODE { 2, 0, 0 }, // RETURN { 6, 1, 40 }, // DELEGATECALL { 7, 1, 40 }, // CALLBLACKBOX { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 6, 1, 40 }, // STATICCALL { 0, 0, 0xffffffff }, // unused { 0, 0, 0xffffffff }, // unused { 2, 0, 0 }, // REVERT { 0, 0, 0xffffffff }, // unused { 1, 0, 0 }, // SUICIDE capstone-sys-0.15.0/capstone/arch/EVM/EVMModule.c000064400000000000000000000012130072674642500175050ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh, 2018 */ #ifdef CAPSTONE_HAS_EVM #include "../../cs_priv.h" #include "EVMDisassembler.h" #include "EVMInstPrinter.h" #include "EVMMapping.h" #include "EVMModule.h" cs_err EVM_global_init(cs_struct *ud) { // verify if requested mode is valid if (ud->mode) return CS_ERR_MODE; ud->printer = EVM_printInst; ud->printer_info = NULL; ud->insn_id = EVM_get_insn_id; ud->insn_name = EVM_insn_name; ud->group_name = EVM_group_name; ud->disasm = EVM_getInstruction; return CS_ERR_OK; } cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value) { return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/EVM/EVMModule.h000064400000000000000000000004310072674642500175130ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_EVM_MODULE_H #define CS_EVM_MODULE_H #include "../../utils.h" cs_err EVM_global_init(cs_struct *ud); cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XDisassembler.c000064400000000000000000001607770072674642500212100ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ /* ======================================================================== */ /* ================================ INCLUDES ============================== */ /* ======================================================================== */ #include #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCRegisterInfo.h" #include "M680XInstPrinter.h" #include "M680XDisassembler.h" #include "M680XDisassemblerInternals.h" #ifdef CAPSTONE_HAS_M680X #ifndef DECL_SPEC #ifdef _MSC_VER #define DECL_SPEC __cdecl #else #define DECL_SPEC #endif // _MSC_VER #endif // DECL_SPEC /* ======================================================================== */ /* ============================ GENERAL DEFINES =========================== */ /* ======================================================================== */ /* ======================================================================== */ /* =============================== PROTOTYPES ============================= */ /* ======================================================================== */ typedef enum insn_hdlr_id { illgl_hid, rel8_hid, rel16_hid, imm8_hid, imm16_hid, imm32_hid, dir_hid, ext_hid, idxX_hid, idxY_hid, idx09_hid, inh_hid, rr09_hid, rbits_hid, bitmv_hid, tfm_hid, opidx_hid, opidxdr_hid, idxX0_hid, idxX16_hid, imm8rel_hid, idxS_hid, idxS16_hid, idxXp_hid, idxX0p_hid, idx12_hid, idx12s_hid, rr12_hid, loop_hid, index_hid, imm8i12x_hid, imm16i12x_hid, exti12x_hid, HANDLER_ID_ENDING, } insn_hdlr_id; // Access modes for the first 4 operands. If there are more than // four operands they use the same access mode as the 4th operand. // // u: unchanged // r: (r)read access // w: (w)write access // m: (m)odify access (= read + write) // typedef enum e_access_mode { uuuu, rrrr, wwww, rwww, rrrm, rmmm, wrrr, mrrr, mwww, mmmm, mwrr, mmrr, wmmm, rruu, muuu, ACCESS_MODE_ENDING, } e_access_mode; // Access type values are compatible with enum cs_ac_type: typedef enum e_access { UNCHANGED = CS_AC_INVALID, READ = CS_AC_READ, WRITE = CS_AC_WRITE, MODIFY = (CS_AC_READ | CS_AC_WRITE), } e_access; /* Properties of one instruction in PAGE1 (without prefix) */ typedef struct inst_page1 { unsigned insn : 9; // A value of type m680x_insn unsigned handler_id1 : 6; // Type insn_hdlr_id, first instr. handler id unsigned handler_id2 : 6; // Type insn_hdlr_id, second instr. handler id } inst_page1; /* Properties of one instruction in any other PAGE X */ typedef struct inst_pageX { unsigned opcode : 8; // The opcode byte unsigned insn : 9; // A value of type m680x_insn unsigned handler_id1 : 6; // Type insn_hdlr_id, first instr. handler id unsigned handler_id2 : 6; // Type insn_hdlr_id, second instr. handler id } inst_pageX; typedef struct insn_props { unsigned group : 4; unsigned access_mode : 5; // A value of type e_access_mode unsigned reg0 : 5; // A value of type m680x_reg unsigned reg1 : 5; // A value of type m680x_reg bool cc_modified : 1; bool update_reg_access : 1; } insn_props; #include "m6800.inc" #include "m6801.inc" #include "hd6301.inc" #include "m6811.inc" #include "cpu12.inc" #include "m6805.inc" #include "m6808.inc" #include "hcs08.inc" #include "m6809.inc" #include "hd6309.inc" #include "insn_props.inc" ////////////////////////////////////////////////////////////////////////////// // M680X instuctions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2). // A reader is needed to read a byte or word from a given memory address. // See also X86 reader(...) static bool read_byte(const m680x_info *info, uint8_t *byte, uint16_t address) { if (address < info->offset || (uint32_t)(address - info->offset) >= info->size) // out of code buffer range return false; *byte = info->code[address - info->offset]; return true; } static bool read_byte_sign_extended(const m680x_info *info, int16_t *word, uint16_t address) { if (address < info->offset || (uint32_t)(address - info->offset) >= info->size) // out of code buffer range return false; *word = (int16_t) info->code[address - info->offset]; if (*word & 0x80) *word |= 0xFF00; return true; } static bool read_word(const m680x_info *info, uint16_t *word, uint16_t address) { if (address < info->offset || (uint32_t)(address + 1 - info->offset) >= info->size) // out of code buffer range return false; *word = (uint16_t)info->code[address - info->offset] << 8; *word |= (uint16_t)info->code[address + 1 - info->offset]; return true; } static bool read_sdword(const m680x_info *info, int32_t *sdword, uint16_t address) { if (address < info->offset || (uint32_t)(address + 3 - info->offset) >= info->size) // out of code buffer range return false; *sdword = (uint32_t)info->code[address - info->offset] << 24; *sdword |= (uint32_t)info->code[address + 1 - info->offset] << 16; *sdword |= (uint32_t)info->code[address + 2 - info->offset] << 8; *sdword |= (uint32_t)info->code[address + 3 - info->offset]; return true; } // For PAGE2 and PAGE3 opcodes when using an an array of inst_page1 most // entries have M680X_INS_ILLGL. To avoid wasting memory an inst_pageX is // used which contains the opcode. Using a binary search for the right opcode // is much faster (= O(log n) ) in comparison to a linear search ( = O(n) ). static int binary_search(const inst_pageX *const inst_pageX_table, size_t table_size, unsigned int opcode) { // As part of the algorithm last may get negative. // => signed integer has to be used. int first = 0; int last = (int)table_size - 1; int middle = (first + last) / 2; while (first <= last) { if (inst_pageX_table[middle].opcode < opcode) { first = middle + 1; } else if (inst_pageX_table[middle].opcode == opcode) { return middle; /* item found */ } else last = middle - 1; middle = (first + last) / 2; } if (first > last) return -1; /* item not found */ return -2; } void M680X_get_insn_id(cs_struct *handle, cs_insn *insn, unsigned int id) { const m680x_info *const info = (const m680x_info *)handle->printer_info; const cpu_tables *cpu = info->cpu; uint8_t insn_prefix = (id >> 8) & 0xff; // opcode is the first instruction byte without the prefix. uint8_t opcode = id & 0xff; int index; int i; insn->id = M680X_INS_ILLGL; for (i = 0; i < ARR_SIZE(cpu->pageX_prefix); ++i) { if (cpu->pageX_table_size[i] == 0 || (cpu->inst_pageX_table[i] == NULL)) break; if (cpu->pageX_prefix[i] == insn_prefix) { index = binary_search(cpu->inst_pageX_table[i], cpu->pageX_table_size[i], opcode); insn->id = (index >= 0) ? cpu->inst_pageX_table[i][index].insn : M680X_INS_ILLGL; return; } } if (insn_prefix != 0) return; insn->id = cpu->inst_page1_table[id].insn; if (insn->id != M680X_INS_ILLGL) return; // Check if opcode byte is present in an overlay table for (i = 0; i < ARR_SIZE(cpu->overlay_table_size); ++i) { if (cpu->overlay_table_size[i] == 0 || (cpu->inst_overlay_table[i] == NULL)) break; if ((index = binary_search(cpu->inst_overlay_table[i], cpu->overlay_table_size[i], opcode)) >= 0) { insn->id = cpu->inst_overlay_table[i][index].insn; return; } } } static void add_insn_group(cs_detail *detail, m680x_group_type group) { if (detail != NULL && (group != M680X_GRP_INVALID) && (group != M680X_GRP_ENDING)) detail->groups[detail->groups_count++] = (uint8_t)group; } static bool exists_reg_list(uint16_t *regs, uint8_t count, m680x_reg reg) { uint8_t i; for (i = 0; i < count; ++i) { if (regs[i] == (uint16_t)reg) return true; } return false; } static void add_reg_to_rw_list(MCInst *MI, m680x_reg reg, e_access access) { cs_detail *detail = MI->flat_insn->detail; if (detail == NULL || (reg == M680X_REG_INVALID)) return; switch (access) { case MODIFY: if (!exists_reg_list(detail->regs_read, detail->regs_read_count, reg)) detail->regs_read[detail->regs_read_count++] = (uint16_t)reg; // intentionally fall through case WRITE: if (!exists_reg_list(detail->regs_write, detail->regs_write_count, reg)) detail->regs_write[detail->regs_write_count++] = (uint16_t)reg; break; case READ: if (!exists_reg_list(detail->regs_read, detail->regs_read_count, reg)) detail->regs_read[detail->regs_read_count++] = (uint16_t)reg; break; case UNCHANGED: default: break; } } static void update_am_reg_list(MCInst *MI, m680x_info *info, cs_m680x_op *op, e_access access) { if (MI->flat_insn->detail == NULL) return; switch (op->type) { case M680X_OP_REGISTER: add_reg_to_rw_list(MI, op->reg, access); break; case M680X_OP_INDEXED: add_reg_to_rw_list(MI, op->idx.base_reg, READ); if (op->idx.base_reg == M680X_REG_X && info->cpu->reg_byte_size[M680X_REG_H]) add_reg_to_rw_list(MI, M680X_REG_H, READ); if (op->idx.offset_reg != M680X_REG_INVALID) add_reg_to_rw_list(MI, op->idx.offset_reg, READ); if (op->idx.inc_dec) { add_reg_to_rw_list(MI, op->idx.base_reg, WRITE); if (op->idx.base_reg == M680X_REG_X && info->cpu->reg_byte_size[M680X_REG_H]) add_reg_to_rw_list(MI, M680X_REG_H, WRITE); } break; default: break; } } static const e_access g_access_mode_to_access[4][15] = { { UNCHANGED, READ, WRITE, READ, READ, READ, WRITE, MODIFY, MODIFY, MODIFY, MODIFY, MODIFY, WRITE, READ, MODIFY, }, { UNCHANGED, READ, WRITE, WRITE, READ, MODIFY, READ, READ, WRITE, MODIFY, WRITE, MODIFY, MODIFY, READ, UNCHANGED, }, { UNCHANGED, READ, WRITE, WRITE, READ, MODIFY, READ, READ, WRITE, MODIFY, READ, READ, MODIFY, UNCHANGED, UNCHANGED, }, { UNCHANGED, READ, WRITE, WRITE, MODIFY, MODIFY, READ, READ, WRITE, MODIFY, READ, READ, MODIFY, UNCHANGED, UNCHANGED, }, }; static e_access get_access(int operator_index, e_access_mode access_mode) { int idx = (operator_index > 3) ? 3 : operator_index; return g_access_mode_to_access[idx][access_mode]; } static void build_regs_read_write_counts(MCInst *MI, m680x_info *info, e_access_mode access_mode) { cs_m680x *m680x = &info->m680x; int i; if (MI->flat_insn->detail == NULL || (!m680x->op_count)) return; for (i = 0; i < m680x->op_count; ++i) { e_access access = get_access(i, access_mode); update_am_reg_list(MI, info, &m680x->operands[i], access); } } static void add_operators_access(MCInst *MI, m680x_info *info, e_access_mode access_mode) { cs_m680x *m680x = &info->m680x; int offset = 0; int i; if (MI->flat_insn->detail == NULL || (!m680x->op_count) || (access_mode == uuuu)) return; for (i = 0; i < m680x->op_count; ++i) { e_access access; // Ugly fix: MULD has a register operand, an immediate operand // AND an implicitly changed register W if (info->insn == M680X_INS_MULD && (i == 1)) offset = 1; access = get_access(i + offset, access_mode); m680x->operands[i].access = access; } } typedef struct insn_to_changed_regs { m680x_insn insn; e_access_mode access_mode; m680x_reg regs[10]; } insn_to_changed_regs; static void set_changed_regs_read_write_counts(MCInst *MI, m680x_info *info) { //TABLE #define EOL M680X_REG_INVALID static const insn_to_changed_regs changed_regs[] = { { M680X_INS_BSR, mmmm, { M680X_REG_S, EOL } }, { M680X_INS_CALL, mmmm, { M680X_REG_S, EOL } }, { M680X_INS_CWAI, mrrr, { M680X_REG_S, M680X_REG_PC, M680X_REG_U, M680X_REG_Y, M680X_REG_X, M680X_REG_DP, M680X_REG_D, M680X_REG_CC, EOL }, }, { M680X_INS_DAA, mrrr, { M680X_REG_A, EOL } }, { M680X_INS_DIV, mmrr, { M680X_REG_A, M680X_REG_H, M680X_REG_X, EOL } }, { M680X_INS_EDIV, mmrr, { M680X_REG_D, M680X_REG_Y, M680X_REG_X, EOL } }, { M680X_INS_EDIVS, mmrr, { M680X_REG_D, M680X_REG_Y, M680X_REG_X, EOL } }, { M680X_INS_EMACS, mrrr, { M680X_REG_X, M680X_REG_Y, EOL } }, { M680X_INS_EMAXM, rrrr, { M680X_REG_D, EOL } }, { M680X_INS_EMINM, rrrr, { M680X_REG_D, EOL } }, { M680X_INS_EMUL, mmrr, { M680X_REG_D, M680X_REG_Y, EOL } }, { M680X_INS_EMULS, mmrr, { M680X_REG_D, M680X_REG_Y, EOL } }, { M680X_INS_ETBL, wmmm, { M680X_REG_A, M680X_REG_B, EOL } }, { M680X_INS_FDIV, mmmm, { M680X_REG_D, M680X_REG_X, EOL } }, { M680X_INS_IDIV, mmmm, { M680X_REG_D, M680X_REG_X, EOL } }, { M680X_INS_IDIVS, mmmm, { M680X_REG_D, M680X_REG_X, EOL } }, { M680X_INS_JSR, mmmm, { M680X_REG_S, EOL } }, { M680X_INS_LBSR, mmmm, { M680X_REG_S, EOL } }, { M680X_INS_MAXM, rrrr, { M680X_REG_A, EOL } }, { M680X_INS_MINM, rrrr, { M680X_REG_A, EOL } }, { M680X_INS_MEM, mmrr, { M680X_REG_X, M680X_REG_Y, M680X_REG_A, EOL } }, { M680X_INS_MUL, mmmm, { M680X_REG_A, M680X_REG_B, EOL } }, { M680X_INS_MULD, mwrr, { M680X_REG_D, M680X_REG_W, EOL } }, { M680X_INS_PSHA, rmmm, { M680X_REG_A, M680X_REG_S, EOL } }, { M680X_INS_PSHB, rmmm, { M680X_REG_B, M680X_REG_S, EOL } }, { M680X_INS_PSHC, rmmm, { M680X_REG_CC, M680X_REG_S, EOL } }, { M680X_INS_PSHD, rmmm, { M680X_REG_D, M680X_REG_S, EOL } }, { M680X_INS_PSHH, rmmm, { M680X_REG_H, M680X_REG_S, EOL } }, { M680X_INS_PSHX, rmmm, { M680X_REG_X, M680X_REG_S, EOL } }, { M680X_INS_PSHY, rmmm, { M680X_REG_Y, M680X_REG_S, EOL } }, { M680X_INS_PULA, wmmm, { M680X_REG_A, M680X_REG_S, EOL } }, { M680X_INS_PULB, wmmm, { M680X_REG_B, M680X_REG_S, EOL } }, { M680X_INS_PULC, wmmm, { M680X_REG_CC, M680X_REG_S, EOL } }, { M680X_INS_PULD, wmmm, { M680X_REG_D, M680X_REG_S, EOL } }, { M680X_INS_PULH, wmmm, { M680X_REG_H, M680X_REG_S, EOL } }, { M680X_INS_PULX, wmmm, { M680X_REG_X, M680X_REG_S, EOL } }, { M680X_INS_PULY, wmmm, { M680X_REG_Y, M680X_REG_S, EOL } }, { M680X_INS_REV, mmrr, { M680X_REG_A, M680X_REG_X, M680X_REG_Y, EOL } }, { M680X_INS_REVW, mmmm, { M680X_REG_A, M680X_REG_X, M680X_REG_Y, EOL } }, { M680X_INS_RTC, mwww, { M680X_REG_S, M680X_REG_PC, EOL } }, { M680X_INS_RTI, mwww, { M680X_REG_S, M680X_REG_CC, M680X_REG_B, M680X_REG_A, M680X_REG_DP, M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_PC, EOL }, }, { M680X_INS_RTS, mwww, { M680X_REG_S, M680X_REG_PC, EOL } }, { M680X_INS_SEX, wrrr, { M680X_REG_A, M680X_REG_B, EOL } }, { M680X_INS_SEXW, rwww, { M680X_REG_W, M680X_REG_D, EOL } }, { M680X_INS_SWI, mmrr, { M680X_REG_S, M680X_REG_PC, M680X_REG_U, M680X_REG_Y, M680X_REG_X, M680X_REG_DP, M680X_REG_A, M680X_REG_B, M680X_REG_CC, EOL } }, { M680X_INS_SWI2, mmrr, { M680X_REG_S, M680X_REG_PC, M680X_REG_U, M680X_REG_Y, M680X_REG_X, M680X_REG_DP, M680X_REG_A, M680X_REG_B, M680X_REG_CC, EOL }, }, { M680X_INS_SWI3, mmrr, { M680X_REG_S, M680X_REG_PC, M680X_REG_U, M680X_REG_Y, M680X_REG_X, M680X_REG_DP, M680X_REG_A, M680X_REG_B, M680X_REG_CC, EOL }, }, { M680X_INS_TBL, wrrr, { M680X_REG_A, M680X_REG_B, EOL } }, { M680X_INS_WAI, mrrr, { M680X_REG_S, M680X_REG_PC, M680X_REG_X, M680X_REG_A, M680X_REG_B, M680X_REG_CC, EOL } }, { M680X_INS_WAV, rmmm, { M680X_REG_A, M680X_REG_B, M680X_REG_X, M680X_REG_Y, EOL } }, { M680X_INS_WAVR, rmmm, { M680X_REG_A, M680X_REG_B, M680X_REG_X, M680X_REG_Y, EOL } }, }; int i, j; if (MI->flat_insn->detail == NULL) return; for (i = 0; i < ARR_SIZE(changed_regs); ++i) { if (info->insn == changed_regs[i].insn) { e_access_mode access_mode = changed_regs[i].access_mode; for (j = 0; changed_regs[i].regs[j] != EOL; ++j) { e_access access; m680x_reg reg = changed_regs[i].regs[j]; if (!info->cpu->reg_byte_size[reg]) { if (info->insn != M680X_INS_MUL) continue; // Hack for M68HC05: MUL uses reg. A,X reg = M680X_REG_X; } access = get_access(j, access_mode); add_reg_to_rw_list(MI, reg, access); } } } #undef EOL } typedef struct insn_desc { uint32_t opcode; m680x_insn insn; insn_hdlr_id hid[2]; uint16_t insn_size; } insn_desc; // If successfull return the additional byte size needed for M6809 // indexed addressing mode (including the indexed addressing post_byte). // On error return -1. static int get_indexed09_post_byte_size(const m680x_info *info, uint16_t address) { uint8_t ir = 0; uint8_t post_byte; // Read the indexed addressing post byte. if (!read_byte(info, &post_byte, address)) return -1; // Depending on the indexed addressing mode more bytes have to be read. switch (post_byte & 0x9F) { case 0x87: case 0x8A: case 0x8E: case 0x8F: case 0x90: case 0x92: case 0x97: case 0x9A: case 0x9E: return -1; // illegal indexed post bytes case 0x88: // n8,R case 0x8C: // n8,PCR case 0x98: // [n8,R] case 0x9C: // [n8,PCR] if (!read_byte(info, &ir, address + 1)) return -1; return 2; case 0x89: // n16,R case 0x8D: // n16,PCR case 0x99: // [n16,R] case 0x9D: // [n16,PCR] if (!read_byte(info, &ir, address + 2)) return -1; return 3; case 0x9F: // [n] if ((post_byte & 0x60) != 0 || !read_byte(info, &ir, address + 2)) return -1; return 3; } // Any other indexed post byte is valid and // no additional bytes have to be read. return 1; } // If successfull return the additional byte size needed for CPU12 // indexed addressing mode (including the indexed addressing post_byte). // On error return -1. static int get_indexed12_post_byte_size(const m680x_info *info, uint16_t address, bool is_subset) { uint8_t ir; uint8_t post_byte; // Read the indexed addressing post byte. if (!read_byte(info, &post_byte, address)) return -1; // Depending on the indexed addressing mode more bytes have to be read. if (!(post_byte & 0x20)) // n5,R return 1; switch (post_byte & 0xe7) { case 0xe0: case 0xe1: // n9,R if (is_subset) return -1; if (!read_byte(info, &ir, address)) return -1; return 2; case 0xe2: // n16,R case 0xe3: // [n16,R] if (is_subset) return -1; if (!read_byte(info, &ir, address + 1)) return -1; return 3; case 0xe4: // A,R case 0xe5: // B,R case 0xe6: // D,R case 0xe7: // [D,R] default: // n,-r n,+r n,r- n,r+ break; } return 1; } // Check for M6809/HD6309 TFR/EXG instruction for valid register static bool is_tfr09_reg_valid(const m680x_info *info, uint8_t reg_nibble) { if (info->cpu->tfr_reg_valid != NULL) return info->cpu->tfr_reg_valid[reg_nibble]; return true; // e.g. for the M6309 all registers are valid } // Check for CPU12 TFR/EXG instruction for valid register static bool is_exg_tfr12_post_byte_valid(const m680x_info *info, uint8_t post_byte) { return !(post_byte & 0x08); } static bool is_tfm_reg_valid(const m680x_info *info, uint8_t reg_nibble) { // HD6809 TFM instruction: Only register X,Y,U,S,D is allowed return reg_nibble <= 4; } // If successfull return the additional byte size needed for CPU12 // loop instructions DBEQ/DBNE/IBEQ/IBNE/TBEQ/TBNE (including the post byte). // On error return -1. static int get_loop_post_byte_size(const m680x_info *info, uint16_t address) { uint8_t post_byte; uint8_t rr; if (!read_byte(info, &post_byte, address)) return -1; // According to documentation bit 3 is don't care and not checked here. if ((post_byte >= 0xc0) || ((post_byte & 0x07) == 2) || ((post_byte & 0x07) == 3)) return -1; if (!read_byte(info, &rr, address + 1)) return -1; return 2; } // If successfull return the additional byte size needed for HD6309 // bit move instructions BAND/BEOR/BIAND/BIEOR/BIOR/BOR/LDBT/STBT // (including the post byte). // On error return -1. static int get_bitmv_post_byte_size(const m680x_info *info, uint16_t address) { uint8_t post_byte; uint8_t rr; if (!read_byte(info, &post_byte, address)) return -1; if ((post_byte & 0xc0) == 0xc0) return -1; // Invalid register specified else { if (!read_byte(info, &rr, address + 1)) return -1; } return 2; } static bool is_sufficient_code_size(const m680x_info *info, uint16_t address, insn_desc *insn_description) { int i; bool retval = true; uint16_t size = 0; int sz; for (i = 0; i < 2; i++) { uint8_t ir = 0; bool is_subset = false; switch (insn_description->hid[i]) { case imm32_hid: if ((retval = read_byte(info, &ir, address + size + 3))) size += 4; break; case ext_hid: case imm16_hid: case rel16_hid: case imm8rel_hid: case opidxdr_hid: case idxX16_hid: case idxS16_hid: if ((retval = read_byte(info, &ir, address + size + 1))) size += 2; break; case rel8_hid: case dir_hid: case rbits_hid: case imm8_hid: case idxX_hid: case idxXp_hid: case idxY_hid: case idxS_hid: case index_hid: if ((retval = read_byte(info, &ir, address + size))) size++; break; case illgl_hid: case inh_hid: case idxX0_hid: case idxX0p_hid: case opidx_hid: retval = true; break; case idx09_hid: sz = get_indexed09_post_byte_size(info, address + size); if (sz >= 0) size += sz; else retval = false; break; case idx12s_hid: is_subset = true; // intentionally fall through case idx12_hid: sz = get_indexed12_post_byte_size(info, address + size, is_subset); if (sz >= 0) size += sz; else retval = false; break; case exti12x_hid: case imm16i12x_hid: sz = get_indexed12_post_byte_size(info, address + size, false); if (sz >= 0) { size += sz; if ((retval = read_byte(info, &ir, address + size + 1))) size += 2; } else retval = false; break; case imm8i12x_hid: sz = get_indexed12_post_byte_size(info, address + size, false); if (sz >= 0) { size += sz; if ((retval = read_byte(info, &ir, address + size))) size++; } else retval = false; break; case tfm_hid: if ((retval = read_byte(info, &ir, address + size))) { size++; retval = is_tfm_reg_valid(info, (ir >> 4) & 0x0F) && is_tfm_reg_valid(info, ir & 0x0F); } break; case rr09_hid: if ((retval = read_byte(info, &ir, address + size))) { size++; retval = is_tfr09_reg_valid(info, (ir >> 4) & 0x0F) && is_tfr09_reg_valid(info, ir & 0x0F); } break; case rr12_hid: if ((retval = read_byte(info, &ir, address + size))) { size++; retval = is_exg_tfr12_post_byte_valid(info, ir); } break; case bitmv_hid: sz = get_bitmv_post_byte_size(info, address + size); if (sz >= 0) size += sz; else retval = false; break; case loop_hid: sz = get_loop_post_byte_size(info, address + size); if (sz >= 0) size += sz; else retval = false; break; default: CS_ASSERT(0 && "Unexpected instruction handler id"); retval = false; break; } if (!retval) return false; } insn_description->insn_size += size; return retval; } // Check for a valid M680X instruction AND for enough bytes in the code buffer // Return an instruction description in insn_desc. static bool decode_insn(const m680x_info *info, uint16_t address, insn_desc *insn_description) { const inst_pageX *inst_table = NULL; const cpu_tables *cpu = info->cpu; size_t table_size = 0; uint16_t base_address = address; uint8_t ir; // instruction register int i; int index; if (!read_byte(info, &ir, address++)) return false; insn_description->insn = M680X_INS_ILLGL; insn_description->opcode = ir; // Check if a page prefix byte is present for (i = 0; i < ARR_SIZE(cpu->pageX_table_size); ++i) { if (cpu->pageX_table_size[i] == 0 || (cpu->inst_pageX_table[i] == NULL)) break; if ((cpu->pageX_prefix[i] == ir)) { // Get pageX instruction and handler id. // Abort for illegal instr. inst_table = cpu->inst_pageX_table[i]; table_size = cpu->pageX_table_size[i]; if (!read_byte(info, &ir, address++)) return false; insn_description->opcode = (insn_description->opcode << 8) | ir; if ((index = binary_search(inst_table, table_size, ir)) < 0) return false; insn_description->hid[0] = inst_table[index].handler_id1; insn_description->hid[1] = inst_table[index].handler_id2; insn_description->insn = inst_table[index].insn; break; } } if (insn_description->insn == M680X_INS_ILLGL) { // Get page1 insn description insn_description->insn = cpu->inst_page1_table[ir].insn; insn_description->hid[0] = cpu->inst_page1_table[ir].handler_id1; insn_description->hid[1] = cpu->inst_page1_table[ir].handler_id2; } if (insn_description->insn == M680X_INS_ILLGL) { // Check if opcode byte is present in an overlay table for (i = 0; i < ARR_SIZE(cpu->overlay_table_size); ++i) { if (cpu->overlay_table_size[i] == 0 || (cpu->inst_overlay_table[i] == NULL)) break; inst_table = cpu->inst_overlay_table[i]; table_size = cpu->overlay_table_size[i]; if ((index = binary_search(inst_table, table_size, ir)) >= 0) { insn_description->hid[0] = inst_table[index].handler_id1; insn_description->hid[1] = inst_table[index].handler_id2; insn_description->insn = inst_table[index].insn; break; } } } insn_description->insn_size = address - base_address; return (insn_description->insn != M680X_INS_ILLGL) && (insn_description->insn != M680X_INS_INVLD) && is_sufficient_code_size(info, address, insn_description); } static void illegal_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x_op *op0 = &info->m680x.operands[info->m680x.op_count++]; uint8_t temp8 = 0; info->insn = M680X_INS_ILLGL; read_byte(info, &temp8, (*address)++); op0->imm = (int32_t)temp8 & 0xff; op0->type = M680X_OP_IMMEDIATE; op0->size = 1; } static void inherent_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { // There is nothing to do here :-) } static void add_reg_operand(m680x_info *info, m680x_reg reg) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_REGISTER; op->reg = reg; op->size = info->cpu->reg_byte_size[reg]; } static void set_operand_size(m680x_info *info, cs_m680x_op *op, uint8_t default_size) { cs_m680x *m680x = &info->m680x; if (info->insn == M680X_INS_JMP || info->insn == M680X_INS_JSR) op->size = 0; else if (info->insn == M680X_INS_DIVD || ((info->insn == M680X_INS_AIS || info->insn == M680X_INS_AIX) && op->type != M680X_OP_REGISTER)) op->size = 1; else if (info->insn == M680X_INS_DIVQ || info->insn == M680X_INS_MOVW) op->size = 2; else if (info->insn == M680X_INS_EMACS) op->size = 4; else if ((m680x->op_count > 0) && (m680x->operands[0].type == M680X_OP_REGISTER)) op->size = m680x->operands[0].size; else op->size = default_size; } static const m680x_reg reg_s_reg_ids[] = { M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_DP, M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_PC, }; static const m680x_reg reg_u_reg_ids[] = { M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_DP, M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC, }; static void reg_bits_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x_op *op0 = &info->m680x.operands[0]; uint8_t reg_bits = 0; uint16_t bit_index; const m680x_reg *reg_to_reg_ids = NULL; read_byte(info, ®_bits, (*address)++); switch (op0->reg) { case M680X_REG_U: reg_to_reg_ids = ®_u_reg_ids[0]; break; case M680X_REG_S: reg_to_reg_ids = ®_s_reg_ids[0]; break; default: CS_ASSERT(0 && "Unexpected operand0 register"); break; } if ((info->insn == M680X_INS_PULU || (info->insn == M680X_INS_PULS)) && ((reg_bits & 0x80) != 0)) // PULS xxx,PC or PULU xxx,PC which is like return from // subroutine (RTS) add_insn_group(MI->flat_insn->detail, M680X_GRP_RET); for (bit_index = 0; bit_index < 8; ++bit_index) { if (reg_bits & (1 << bit_index)) add_reg_operand(info, reg_to_reg_ids[bit_index]); } } static const m680x_reg g_tfr_exg_reg_ids[] = { /* 16-bit registers */ M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_S, M680X_REG_PC, M680X_REG_W, M680X_REG_V, /* 8-bit registers */ M680X_REG_A, M680X_REG_B, M680X_REG_CC, M680X_REG_DP, M680X_REG_0, M680X_REG_0, M680X_REG_E, M680X_REG_F, }; static void reg_reg09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint8_t regs = 0; read_byte(info, ®s, (*address)++); add_reg_operand(info, g_tfr_exg_reg_ids[regs >> 4]); add_reg_operand(info, g_tfr_exg_reg_ids[regs & 0x0f]); if ((regs & 0x0f) == 0x05) { // EXG xxx,PC or TFR xxx,PC which is like a JMP add_insn_group(MI->flat_insn->detail, M680X_GRP_JUMP); } } static void reg_reg12_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { static const m680x_reg g_tfr_exg12_reg0_ids[] = { M680X_REG_A, M680X_REG_B, M680X_REG_CC, M680X_REG_TMP3, M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S, }; static const m680x_reg g_tfr_exg12_reg1_ids[] = { M680X_REG_A, M680X_REG_B, M680X_REG_CC, M680X_REG_TMP2, M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S, }; uint8_t regs = 0; read_byte(info, ®s, (*address)++); // The opcode of this instruction depends on // the msb of its post byte. if (regs & 0x80) info->insn = M680X_INS_EXG; else info->insn = M680X_INS_TFR; add_reg_operand(info, g_tfr_exg12_reg0_ids[(regs >> 4) & 0x07]); add_reg_operand(info, g_tfr_exg12_reg1_ids[regs & 0x07]); } static void add_rel_operand(m680x_info *info, int16_t offset, uint16_t address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_RELATIVE; op->size = 0; op->rel.offset = offset; op->rel.address = address; } static void relative8_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { int16_t offset = 0; read_byte_sign_extended(info, &offset, (*address)++); add_rel_operand(info, offset, *address + offset); add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL); if ((info->insn != M680X_INS_BRA) && (info->insn != M680X_INS_BSR) && (info->insn != M680X_INS_BRN)) add_reg_to_rw_list(MI, M680X_REG_CC, READ); } static void relative16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint16_t offset = 0; read_word(info, &offset, *address); *address += 2; add_rel_operand(info, (int16_t)offset, *address + offset); add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL); if ((info->insn != M680X_INS_LBRA) && (info->insn != M680X_INS_LBSR) && (info->insn != M680X_INS_LBRN)) add_reg_to_rw_list(MI, M680X_REG_CC, READ); } static const m680x_reg g_rr5_to_reg_ids[] = { M680X_REG_X, M680X_REG_Y, M680X_REG_U, M680X_REG_S, }; static void add_indexed_operand(m680x_info *info, m680x_reg base_reg, bool post_inc_dec, uint8_t inc_dec, uint8_t offset_bits, uint16_t offset, bool no_comma) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_INDEXED; set_operand_size(info, op, 1); op->idx.base_reg = base_reg; op->idx.offset_reg = M680X_REG_INVALID; op->idx.inc_dec = inc_dec; if (inc_dec && post_inc_dec) op->idx.flags |= M680X_IDX_POST_INC_DEC; if (offset_bits != M680X_OFFSET_NONE) { op->idx.offset = offset; op->idx.offset_addr = 0; } op->idx.offset_bits = offset_bits; op->idx.flags |= (no_comma ? M680X_IDX_NO_COMMA : 0); } // M6800/1/2/3 indexed mode handler static void indexedX_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint8_t offset = 0; read_byte(info, &offset, (*address)++); add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_BITS_8, (uint16_t)offset, false); } static void indexedY_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint8_t offset = 0; read_byte(info, &offset, (*address)++); add_indexed_operand(info, M680X_REG_Y, false, 0, M680X_OFFSET_BITS_8, (uint16_t)offset, false); } // M6809/M6309 indexed mode handler static void indexed09_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; uint8_t post_byte = 0; uint16_t offset = 0; int16_t soffset = 0; read_byte(info, &post_byte, (*address)++); op->type = M680X_OP_INDEXED; set_operand_size(info, op, 1); op->idx.base_reg = g_rr5_to_reg_ids[(post_byte >> 5) & 0x03]; op->idx.offset_reg = M680X_REG_INVALID; if (!(post_byte & 0x80)) { // n5,R if ((post_byte & 0x10) == 0x10) op->idx.offset = post_byte | 0xfff0; else op->idx.offset = post_byte & 0x0f; op->idx.offset_addr = op->idx.offset + *address; op->idx.offset_bits = M680X_OFFSET_BITS_5; } else { if ((post_byte & 0x10) == 0x10) op->idx.flags |= M680X_IDX_INDIRECT; // indexed addressing switch (post_byte & 0x1f) { case 0x00: // ,R+ op->idx.inc_dec = 1; op->idx.flags |= M680X_IDX_POST_INC_DEC; break; case 0x11: // [,R++] case 0x01: // ,R++ op->idx.inc_dec = 2; op->idx.flags |= M680X_IDX_POST_INC_DEC; break; case 0x02: // ,-R op->idx.inc_dec = -1; break; case 0x13: // [,--R] case 0x03: // ,--R op->idx.inc_dec = -2; break; case 0x14: // [,R] case 0x04: // ,R break; case 0x15: // [B,R] case 0x05: // B,R op->idx.offset_reg = M680X_REG_B; break; case 0x16: // [A,R] case 0x06: // A,R op->idx.offset_reg = M680X_REG_A; break; case 0x1c: // [n8,PCR] case 0x0c: // n8,PCR op->idx.base_reg = M680X_REG_PC; read_byte_sign_extended(info, &soffset, (*address)++); op->idx.offset_addr = offset + *address; op->idx.offset = soffset; op->idx.offset_bits = M680X_OFFSET_BITS_8; break; case 0x18: // [n8,R] case 0x08: // n8,R read_byte_sign_extended(info, &soffset, (*address)++); op->idx.offset = soffset; op->idx.offset_bits = M680X_OFFSET_BITS_8; break; case 0x1d: // [n16,PCR] case 0x0d: // n16,PCR op->idx.base_reg = M680X_REG_PC; read_word(info, &offset, *address); *address += 2; op->idx.offset_addr = offset + *address; op->idx.offset = (int16_t)offset; op->idx.offset_bits = M680X_OFFSET_BITS_16; break; case 0x19: // [n16,R] case 0x09: // n16,R read_word(info, &offset, *address); *address += 2; op->idx.offset = (int16_t)offset; op->idx.offset_bits = M680X_OFFSET_BITS_16; break; case 0x1b: // [D,R] case 0x0b: // D,R op->idx.offset_reg = M680X_REG_D; break; case 0x1f: // [n16] op->type = M680X_OP_EXTENDED; op->ext.indirect = true; read_word(info, &op->ext.address, *address); *address += 2; break; default: op->idx.base_reg = M680X_REG_INVALID; break; } } if (((info->insn == M680X_INS_LEAU) || (info->insn == M680X_INS_LEAS) || (info->insn == M680X_INS_LEAX) || (info->insn == M680X_INS_LEAY)) && (m680x->operands[0].reg == M680X_REG_X || (m680x->operands[0].reg == M680X_REG_Y))) // Only LEAX and LEAY modify CC register add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY); } static const m680x_reg g_idx12_to_reg_ids[4] = { M680X_REG_X, M680X_REG_Y, M680X_REG_S, M680X_REG_PC, }; static const m680x_reg g_or12_to_reg_ids[3] = { M680X_REG_A, M680X_REG_B, M680X_REG_D }; // CPU12 indexed mode handler static void indexed12_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; uint8_t post_byte = 0; uint8_t offset8 = 0; read_byte(info, &post_byte, (*address)++); op->type = M680X_OP_INDEXED; set_operand_size(info, op, 1); op->idx.offset_reg = M680X_REG_INVALID; if (!(post_byte & 0x20)) { // n5,R n5 is a 5-bit signed offset op->idx.base_reg = g_idx12_to_reg_ids[(post_byte >> 6) & 0x03]; if ((post_byte & 0x10) == 0x10) op->idx.offset = post_byte | 0xfff0; else op->idx.offset = post_byte & 0x0f; op->idx.offset_addr = op->idx.offset + *address; op->idx.offset_bits = M680X_OFFSET_BITS_5; } else { if ((post_byte & 0xe0) == 0xe0) op->idx.base_reg = g_idx12_to_reg_ids[(post_byte >> 3) & 0x03]; switch (post_byte & 0xe7) { case 0xe0: case 0xe1: // n9,R read_byte(info, &offset8, (*address)++); op->idx.offset = offset8; if (post_byte & 0x01) // sign extension op->idx.offset |= 0xff00; op->idx.offset_bits = M680X_OFFSET_BITS_9; if (op->idx.base_reg == M680X_REG_PC) op->idx.offset_addr = op->idx.offset + *address; break; case 0xe3: // [n16,R] op->idx.flags |= M680X_IDX_INDIRECT; // intentionally fall through case 0xe2: // n16,R read_word(info, (uint16_t *)&op->idx.offset, *address); (*address) += 2; op->idx.offset_bits = M680X_OFFSET_BITS_16; if (op->idx.base_reg == M680X_REG_PC) op->idx.offset_addr = op->idx.offset + *address; break; case 0xe4: // A,R case 0xe5: // B,R case 0xe6: // D,R op->idx.offset_reg = g_or12_to_reg_ids[post_byte & 0x03]; break; case 0xe7: // [D,R] op->idx.offset_reg = M680X_REG_D; op->idx.flags |= M680X_IDX_INDIRECT; break; default: // n,-r n,+r n,r- n,r+ // PC is not allowed in this mode op->idx.base_reg = g_idx12_to_reg_ids[(post_byte >> 6) & 0x03]; op->idx.inc_dec = post_byte & 0x0f; if (op->idx.inc_dec & 0x08) // evtl. sign extend value op->idx.inc_dec |= 0xf0; if (op->idx.inc_dec >= 0) op->idx.inc_dec++; if (post_byte & 0x10) op->idx.flags |= M680X_IDX_POST_INC_DEC; break; } } } static void index_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_CONSTANT; read_byte(info, &op->const_val, (*address)++); }; static void direct_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_DIRECT; set_operand_size(info, op, 1); read_byte(info, &op->direct_addr, (*address)++); }; static void extended_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_EXTENDED; set_operand_size(info, op, 1); read_word(info, &op->ext.address, *address); *address += 2; } static void immediate_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; uint16_t word = 0; int16_t sword = 0; op->type = M680X_OP_IMMEDIATE; set_operand_size(info, op, 1); switch (op->size) { case 1: read_byte_sign_extended(info, &sword, *address); op->imm = sword; break; case 2: read_word(info, &word, *address); op->imm = (int16_t)word; break; case 4: read_sdword(info, &op->imm, *address); break; default: op->imm = 0; CS_ASSERT(0 && "Unexpected immediate byte size"); } *address += op->size; } // handler for bit move instructions, e.g: BAND A,5,1,$40 Used by HD6309 static void bit_move_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { static const m680x_reg m680x_reg[] = { M680X_REG_CC, M680X_REG_A, M680X_REG_B, M680X_REG_INVALID, }; uint8_t post_byte = 0; cs_m680x *m680x = &info->m680x; cs_m680x_op *op; read_byte(info, &post_byte, *address); (*address)++; // operand[0] = register add_reg_operand(info, m680x_reg[post_byte >> 6]); // operand[1] = bit index in source operand op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_CONSTANT; op->const_val = (post_byte >> 3) & 0x07; // operand[2] = bit index in destination operand op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_CONSTANT; op->const_val = post_byte & 0x07; direct_hdlr(MI, info, address); } // handler for TFM instruction, e.g: TFM X+,Y+ Used by HD6309 static void tfm_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { static const uint8_t inc_dec_r0[] = { 1, -1, 1, 0, }; static const uint8_t inc_dec_r1[] = { 1, -1, 0, 1, }; uint8_t regs = 0; uint8_t index = (MI->Opcode & 0xff) - 0x38; read_byte(info, ®s, *address); add_indexed_operand(info, g_tfr_exg_reg_ids[regs >> 4], true, inc_dec_r0[index], M680X_OFFSET_NONE, 0, true); add_indexed_operand(info, g_tfr_exg_reg_ids[regs & 0x0f], true, inc_dec_r1[index], M680X_OFFSET_NONE, 0, true); add_reg_to_rw_list(MI, M680X_REG_W, READ | WRITE); } static void opidx_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; // bit index is coded in Opcode op->type = M680X_OP_CONSTANT; op->const_val = (MI->Opcode & 0x0e) >> 1; } // handler for bit test and branch instruction. Used by M6805. // The bit index is part of the opcode. // Example: BRSET 3,<$40,LOOP static void opidx_dir_rel_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; // bit index is coded in Opcode op->type = M680X_OP_CONSTANT; op->const_val = (MI->Opcode & 0x0e) >> 1; direct_hdlr(MI, info, address); relative8_hdlr(MI, info, address); add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY); } static void indexedX0_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_NONE, 0, false); } static void indexedX16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint16_t offset = 0; read_word(info, &offset, *address); *address += 2; add_indexed_operand(info, M680X_REG_X, false, 0, M680X_OFFSET_BITS_16, offset, false); } static void imm_rel_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { immediate_hdlr(MI, info, address); relative8_hdlr(MI, info, address); } static void indexedS_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint8_t offset = 0; read_byte(info, &offset, (*address)++); add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_8, (uint16_t)offset, false); } static void indexedS16_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint16_t offset = 0; read_word(info, &offset, *address); address += 2; add_indexed_operand(info, M680X_REG_S, false, 0, M680X_OFFSET_BITS_16, offset, false); } static void indexedX0p_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { add_indexed_operand(info, M680X_REG_X, true, 1, M680X_OFFSET_NONE, 0, true); } static void indexedXp_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { uint8_t offset = 0; read_byte(info, &offset, (*address)++); add_indexed_operand(info, M680X_REG_X, true, 1, M680X_OFFSET_BITS_8, (uint16_t)offset, false); } static void imm_idx12_x_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op = &m680x->operands[m680x->op_count++]; indexed12_hdlr(MI, info, address); op->type = M680X_OP_IMMEDIATE; if (info->insn == M680X_INS_MOVW) { uint16_t imm16 = 0; read_word(info, &imm16, *address); op->imm = (int16_t)imm16; op->size = 2; } else { uint8_t imm8 = 0; read_byte(info, &imm8, *address); op->imm = (int8_t)imm8; op->size = 1; } set_operand_size(info, op, 1); } static void ext_idx12_x_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { cs_m680x *m680x = &info->m680x; cs_m680x_op *op0 = &m680x->operands[m680x->op_count++]; uint16_t imm16 = 0; indexed12_hdlr(MI, info, address); read_word(info, &imm16, *address); op0->type = M680X_OP_EXTENDED; op0->ext.address = (int16_t)imm16; set_operand_size(info, op0, 1); } // handler for CPU12 DBEQ/DNBE/IBEQ/IBNE/TBEQ/TBNE instructions. // Example: DBNE X,$1000 static void loop_hdlr(MCInst *MI, m680x_info *info, uint16_t *address) { static const m680x_reg index_to_reg_id[] = { M680X_REG_A, M680X_REG_B, M680X_REG_INVALID, M680X_REG_INVALID, M680X_REG_D, M680X_REG_X, M680X_REG_Y, M680X_REG_S, }; static const m680x_insn index_to_insn_id[] = { M680X_INS_DBEQ, M680X_INS_DBNE, M680X_INS_TBEQ, M680X_INS_TBNE, M680X_INS_IBEQ, M680X_INS_IBNE, M680X_INS_ILLGL, M680X_INS_ILLGL }; cs_m680x *m680x = &info->m680x; uint8_t post_byte = 0; uint8_t rel = 0; cs_m680x_op *op; read_byte(info, &post_byte, (*address)++); info->insn = index_to_insn_id[(post_byte >> 5) & 0x07]; if (info->insn == M680X_INS_ILLGL) { illegal_hdlr(MI, info, address); }; read_byte(info, &rel, (*address)++); add_reg_operand(info, index_to_reg_id[post_byte & 0x07]); op = &m680x->operands[m680x->op_count++]; op->type = M680X_OP_RELATIVE; op->rel.offset = (post_byte & 0x10) ? 0xff00 | rel : rel; op->rel.address = *address + op->rel.offset; add_insn_group(MI->flat_insn->detail, M680X_GRP_BRAREL); } static void (*const g_insn_handler[])(MCInst *, m680x_info *, uint16_t *) = { illegal_hdlr, relative8_hdlr, relative16_hdlr, immediate_hdlr, // 8-bit immediate_hdlr, // 16-bit immediate_hdlr, // 32-bit direct_hdlr, extended_hdlr, indexedX_hdlr, indexedY_hdlr, indexed09_hdlr, inherent_hdlr, reg_reg09_hdlr, reg_bits_hdlr, bit_move_hdlr, tfm_hdlr, opidx_hdlr, opidx_dir_rel_hdlr, indexedX0_hdlr, indexedX16_hdlr, imm_rel_hdlr, indexedS_hdlr, indexedS16_hdlr, indexedXp_hdlr, indexedX0p_hdlr, indexed12_hdlr, indexed12_hdlr, // subset of indexed12 reg_reg12_hdlr, loop_hdlr, index_hdlr, imm_idx12_x_hdlr, imm_idx12_x_hdlr, ext_idx12_x_hdlr, }; /* handler function pointers */ /* Disasemble one instruction at address and store in str_buff */ static unsigned int m680x_disassemble(MCInst *MI, m680x_info *info, uint16_t address) { cs_m680x *m680x = &info->m680x; cs_detail *detail = MI->flat_insn->detail; uint16_t base_address = address; insn_desc insn_description; e_access_mode access_mode; if (detail != NULL) { memset(detail, 0, offsetof(cs_detail, m680x)+sizeof(cs_m680x)); } memset(&insn_description, 0, sizeof(insn_description)); memset(m680x, 0, sizeof(*m680x)); info->insn_size = 1; if (decode_insn(info, address, &insn_description)) { m680x_reg reg; if (insn_description.opcode > 0xff) address += 2; // 8-bit opcode + page prefix else address++; // 8-bit opcode only info->insn = insn_description.insn; MCInst_setOpcode(MI, insn_description.opcode); reg = g_insn_props[info->insn].reg0; if (reg != M680X_REG_INVALID) { if (reg == M680X_REG_HX && (!info->cpu->reg_byte_size[reg])) reg = M680X_REG_X; add_reg_operand(info, reg); // First (or second) operand is a register which is // part of the mnemonic m680x->flags |= M680X_FIRST_OP_IN_MNEM; reg = g_insn_props[info->insn].reg1; if (reg != M680X_REG_INVALID) { if (reg == M680X_REG_HX && (!info->cpu->reg_byte_size[reg])) reg = M680X_REG_X; add_reg_operand(info, reg); m680x->flags |= M680X_SECOND_OP_IN_MNEM; } } // Call addressing mode specific instruction handler (g_insn_handler[insn_description.hid[0]])(MI, info, &address); (g_insn_handler[insn_description.hid[1]])(MI, info, &address); add_insn_group(detail, g_insn_props[info->insn].group); if (g_insn_props[info->insn].cc_modified && (info->cpu->insn_cc_not_modified[0] != info->insn) && (info->cpu->insn_cc_not_modified[1] != info->insn)) add_reg_to_rw_list(MI, M680X_REG_CC, MODIFY); access_mode = g_insn_props[info->insn].access_mode; // Fix for M6805 BSET/BCLR. It has a differnt operand order // in comparison to the M6811 if ((info->cpu->insn_cc_not_modified[0] == info->insn) || (info->cpu->insn_cc_not_modified[1] == info->insn)) access_mode = rmmm; build_regs_read_write_counts(MI, info, access_mode); add_operators_access(MI, info, access_mode); if (g_insn_props[info->insn].update_reg_access) set_changed_regs_read_write_counts(MI, info); info->insn_size = (uint8_t)insn_description.insn_size; return info->insn_size; } else MCInst_setOpcode(MI, insn_description.opcode); // Illegal instruction address = base_address; illegal_hdlr(MI, info, &address); return 1; } // Tables to get the byte size of a register on the CPU // based on an enum m680x_reg value. // Invalid registers return 0. static const uint8_t g_m6800_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 2, 0, 0 }; static const uint8_t g_m6805_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0, 2, 0, 0 }; static const uint8_t g_m6808_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 1, 1, 0, 2, 0, 0, 0, 2, 0, 0 }; static const uint8_t g_m6801_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 0, 2, 0, 0, 0, 2, 0, 0 }; static const uint8_t g_m6811_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 2, 2, 0, 0, 0, 2, 0, 0 }; static const uint8_t g_cpu12_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 1, 0, 0, 0, 2, 0, 1, 0, 0, 0, 0, 2, 2, 2, 0, 0, 0, 2, 2, 2 }; static const uint8_t g_m6809_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 1, 0, 0, 0, 2, 0, 1, 1, 0, 0, 0, 2, 2, 2, 2, 0, 0, 2, 0, 0 }; static const uint8_t g_hd6309_reg_byte_size[22] = { // A B E F 0 D W CC DP MD HX H X Y S U V Q PC T2 T3 0, 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, 0, 0, 2, 2, 2, 2, 2, 4, 2, 0, 0 }; // Table to check for a valid register nibble on the M6809 CPU // used for TFR and EXG instruction. static const bool m6809_tfr_reg_valid[16] = { true, true, true, true, true, true, false, false, true, true, true, true, false, false, false, false, }; static const cpu_tables g_cpu_tables[] = { { // M680X_CPU_TYPE_INVALID NULL, { NULL, NULL }, { 0, 0 }, { 0x00, 0x00, 0x00 }, { NULL, NULL, NULL }, { 0, 0, 0 }, NULL, NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_6301 &g_m6800_inst_page1_table[0], { &g_m6801_inst_overlay_table[0], &g_hd6301_inst_overlay_table[0] }, { ARR_SIZE(g_m6801_inst_overlay_table), ARR_SIZE(g_hd6301_inst_overlay_table) }, { 0x00, 0x00, 0x00 }, { NULL, NULL, NULL }, { 0, 0, 0 }, &g_m6801_reg_byte_size[0], NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_6309 &g_m6809_inst_page1_table[0], { &g_hd6309_inst_overlay_table[0], NULL }, { ARR_SIZE(g_hd6309_inst_overlay_table), 0 }, { 0x10, 0x11, 0x00 }, { &g_hd6309_inst_page2_table[0], &g_hd6309_inst_page3_table[0], NULL }, { ARR_SIZE(g_hd6309_inst_page2_table), ARR_SIZE(g_hd6309_inst_page3_table), 0 }, &g_hd6309_reg_byte_size[0], NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_6800 &g_m6800_inst_page1_table[0], { NULL, NULL }, { 0, 0 }, { 0x00, 0x00, 0x00 }, { NULL, NULL, NULL }, { 0, 0, 0 }, &g_m6800_reg_byte_size[0], NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_6801 &g_m6800_inst_page1_table[0], { &g_m6801_inst_overlay_table[0], NULL }, { ARR_SIZE(g_m6801_inst_overlay_table), 0 }, { 0x00, 0x00, 0x00 }, { NULL, NULL, NULL }, { 0, 0, 0 }, &g_m6801_reg_byte_size[0], NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_6805 &g_m6805_inst_page1_table[0], { NULL, NULL }, { 0, 0 }, { 0x00, 0x00, 0x00 }, { NULL, NULL, NULL }, { 0, 0, 0 }, &g_m6805_reg_byte_size[0], NULL, { M680X_INS_BCLR, M680X_INS_BSET } }, { // M680X_CPU_TYPE_6808 &g_m6805_inst_page1_table[0], { &g_m6808_inst_overlay_table[0], NULL }, { ARR_SIZE(g_m6808_inst_overlay_table), 0 }, { 0x9E, 0x00, 0x00 }, { &g_m6808_inst_page2_table[0], NULL, NULL }, { ARR_SIZE(g_m6808_inst_page2_table), 0, 0 }, &g_m6808_reg_byte_size[0], NULL, { M680X_INS_BCLR, M680X_INS_BSET } }, { // M680X_CPU_TYPE_6809 &g_m6809_inst_page1_table[0], { NULL, NULL }, { 0, 0 }, { 0x10, 0x11, 0x00 }, { &g_m6809_inst_page2_table[0], &g_m6809_inst_page3_table[0], NULL }, { ARR_SIZE(g_m6809_inst_page2_table), ARR_SIZE(g_m6809_inst_page3_table), 0 }, &g_m6809_reg_byte_size[0], &m6809_tfr_reg_valid[0], { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_6811 &g_m6800_inst_page1_table[0], { &g_m6801_inst_overlay_table[0], &g_m6811_inst_overlay_table[0] }, { ARR_SIZE(g_m6801_inst_overlay_table), ARR_SIZE(g_m6811_inst_overlay_table) }, { 0x18, 0x1A, 0xCD }, { &g_m6811_inst_page2_table[0], &g_m6811_inst_page3_table[0], &g_m6811_inst_page4_table[0] }, { ARR_SIZE(g_m6811_inst_page2_table), ARR_SIZE(g_m6811_inst_page3_table), ARR_SIZE(g_m6811_inst_page4_table) }, &g_m6811_reg_byte_size[0], NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_CPU12 &g_cpu12_inst_page1_table[0], { NULL, NULL }, { 0, 0 }, { 0x18, 0x00, 0x00 }, { &g_cpu12_inst_page2_table[0], NULL, NULL }, { ARR_SIZE(g_cpu12_inst_page2_table), 0, 0 }, &g_cpu12_reg_byte_size[0], NULL, { M680X_INS_INVLD, M680X_INS_INVLD } }, { // M680X_CPU_TYPE_HCS08 &g_m6805_inst_page1_table[0], { &g_m6808_inst_overlay_table[0], &g_hcs08_inst_overlay_table[0] }, { ARR_SIZE(g_m6808_inst_overlay_table), ARR_SIZE(g_hcs08_inst_overlay_table) }, { 0x9E, 0x00, 0x00 }, { &g_hcs08_inst_page2_table[0], NULL, NULL }, { ARR_SIZE(g_hcs08_inst_page2_table), 0, 0 }, &g_m6808_reg_byte_size[0], NULL, { M680X_INS_BCLR, M680X_INS_BSET } }, }; static bool m680x_setup_internals(m680x_info *info, e_cpu_type cpu_type, uint16_t address, const uint8_t *code, uint16_t code_len) { if (cpu_type == M680X_CPU_TYPE_INVALID) { return false; } info->code = code; info->size = code_len; info->offset = address; info->cpu_type = cpu_type; info->cpu = &g_cpu_tables[info->cpu_type]; return true; } bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) { unsigned int insn_size = 0; e_cpu_type cpu_type = M680X_CPU_TYPE_INVALID; // No default CPU type cs_struct *handle = (cs_struct *)ud; m680x_info *info = (m680x_info *)handle->printer_info; MCInst_clear(MI); if (handle->mode & CS_MODE_M680X_6800) cpu_type = M680X_CPU_TYPE_6800; else if (handle->mode & CS_MODE_M680X_6801) cpu_type = M680X_CPU_TYPE_6801; else if (handle->mode & CS_MODE_M680X_6805) cpu_type = M680X_CPU_TYPE_6805; else if (handle->mode & CS_MODE_M680X_6808) cpu_type = M680X_CPU_TYPE_6808; else if (handle->mode & CS_MODE_M680X_HCS08) cpu_type = M680X_CPU_TYPE_HCS08; else if (handle->mode & CS_MODE_M680X_6809) cpu_type = M680X_CPU_TYPE_6809; else if (handle->mode & CS_MODE_M680X_6301) cpu_type = M680X_CPU_TYPE_6301; else if (handle->mode & CS_MODE_M680X_6309) cpu_type = M680X_CPU_TYPE_6309; else if (handle->mode & CS_MODE_M680X_6811) cpu_type = M680X_CPU_TYPE_6811; else if (handle->mode & CS_MODE_M680X_CPU12) cpu_type = M680X_CPU_TYPE_CPU12; if (cpu_type != M680X_CPU_TYPE_INVALID && m680x_setup_internals(info, cpu_type, (uint16_t)address, code, (uint16_t)code_len)) insn_size = m680x_disassemble(MI, info, (uint16_t)address); if (insn_size == 0) { *size = 1; return false; } // Make sure we always stay within range if (insn_size > code_len) { *size = (uint16_t)code_len; return false; } else *size = (uint16_t)insn_size; return true; } cs_err M680X_disassembler_init(cs_struct *ud) { if (M680X_REG_ENDING != ARR_SIZE(g_m6800_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6800_reg_byte_size)); return CS_ERR_MODE; } if (M680X_REG_ENDING != ARR_SIZE(g_m6801_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6801_reg_byte_size)); return CS_ERR_MODE; } if (M680X_REG_ENDING != ARR_SIZE(g_m6805_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6805_reg_byte_size)); return CS_ERR_MODE; } if (M680X_REG_ENDING != ARR_SIZE(g_m6808_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6808_reg_byte_size)); return CS_ERR_MODE; } if (M680X_REG_ENDING != ARR_SIZE(g_m6811_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6811_reg_byte_size)); return CS_ERR_MODE; } if (M680X_REG_ENDING != ARR_SIZE(g_cpu12_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_cpu12_reg_byte_size)); return CS_ERR_MODE; } if (M680X_REG_ENDING != ARR_SIZE(g_m6809_reg_byte_size)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(g_m6809_reg_byte_size)); return CS_ERR_MODE; } if (M680X_INS_ENDING != ARR_SIZE(g_insn_props)) { CS_ASSERT(M680X_INS_ENDING == ARR_SIZE(g_insn_props)); return CS_ERR_MODE; } if (M680X_CPU_TYPE_ENDING != ARR_SIZE(g_cpu_tables)) { CS_ASSERT(M680X_CPU_TYPE_ENDING == ARR_SIZE(g_cpu_tables)); return CS_ERR_MODE; } if (HANDLER_ID_ENDING != ARR_SIZE(g_insn_handler)) { CS_ASSERT(HANDLER_ID_ENDING == ARR_SIZE(g_insn_handler)); return CS_ERR_MODE; } if (ACCESS_MODE_ENDING != MATRIX_SIZE(g_access_mode_to_access)) { CS_ASSERT(ACCESS_MODE_ENDING == MATRIX_SIZE(g_access_mode_to_access)); return CS_ERR_MODE; } return CS_ERR_OK; } #ifndef CAPSTONE_DIET void M680X_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count) { if (insn->detail == NULL) { *regs_read_count = 0; *regs_write_count = 0; } else { *regs_read_count = insn->detail->regs_read_count; *regs_write_count = insn->detail->regs_write_count; memcpy(regs_read, insn->detail->regs_read, *regs_read_count * sizeof(insn->detail->regs_read[0])); memcpy(regs_write, insn->detail->regs_write, *regs_write_count * sizeof(insn->detail->regs_write[0])); } } #endif #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XDisassembler.h000064400000000000000000000010510072674642500211700ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #ifndef CS_M680XDISASSEMBLER_H #define CS_M680XDISASSEMBLER_H #include "../../MCInst.h" bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); void M680X_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XDisassemblerInternals.h000064400000000000000000000035550072674642500230630ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #ifndef CS_M680XDISASSEMBLERINTERNALS_H #define CS_M680XDISASSEMBLERINTERNALS_H #include "../../MCInst.h" #include "../../include/capstone/m680x.h" typedef enum e_cpu_type { M680X_CPU_TYPE_INVALID, M680X_CPU_TYPE_6301, // M680X Hitachi HD6301,HD6303 mode M680X_CPU_TYPE_6309, // M680X Hitachi HD6309 mode M680X_CPU_TYPE_6800, // M680X Motorola 6800,6802 mode M680X_CPU_TYPE_6801, // M680X Motorola 6801,6803 mode M680X_CPU_TYPE_6805, // M680X Motorola/Freescale M68HC05 mode M680X_CPU_TYPE_6808, // M680X Motorola/Freescale M68HC08 mode M680X_CPU_TYPE_6809, // M680X Motorola 6809 mode M680X_CPU_TYPE_6811, // M680X Motorola/Freescale M68HC11 mode M680X_CPU_TYPE_CPU12, // M680X Motorola/Freescale CPU12 mode // used on M68HC12/HCS12 M680X_CPU_TYPE_HCS08, // M680X Freescale HCS08 mode M680X_CPU_TYPE_ENDING, } e_cpu_type; struct inst_page1; struct inst_pageX; typedef struct { const struct inst_page1 *inst_page1_table; const struct inst_pageX *inst_overlay_table[2]; size_t overlay_table_size[2]; uint8_t pageX_prefix[3]; const struct inst_pageX *inst_pageX_table[3]; size_t pageX_table_size[3]; const uint8_t *reg_byte_size; const bool *tfr_reg_valid; m680x_insn insn_cc_not_modified[2]; } cpu_tables; /* Private, For internal use only */ typedef struct m680x_info { const uint8_t *code; // code buffer uint32_t size; // byte size of code uint16_t offset; // address offset of first byte in code buffer e_cpu_type cpu_type; // The CPU type to be used for disassembling cs_m680x m680x; // M680X specific properties const cpu_tables *cpu; m680x_insn insn; // Instruction ID uint8_t insn_size; // byte size of instruction } m680x_info; extern cs_err M680X_disassembler_init(cs_struct *ud); extern cs_err M680X_instprinter_init(cs_struct *ud); #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XInstPrinter.c000064400000000000000000000222600072674642500210340ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #ifdef CAPSTONE_HAS_M680X #include #include #include #include #include "../../cs_priv.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../utils.h" #include "M680XInstPrinter.h" #include "M680XDisassembler.h" #include "M680XDisassemblerInternals.h" #ifndef CAPSTONE_DIET static const char s_reg_names[][10] = { "", "a", "b", "e", "f", "0", "d", "w", "cc", "dp", "md", "hx", "h", "x", "y", "s", "u", "v", "q", "pc", "tmp2", "tmp3", }; static const char s_instruction_names[][6] = { "invld", "aba", "abx", "aby", "adc", "adca", "adcb", "adcd", "adcr", "add", "adda", "addb", "addd", "adde", "addf", "addr", "addw", "aim", "ais", "aix", "and", "anda", "andb", "andcc", "andd", "andr", "asl", "asla", "aslb", "asld", "asr", "asra", "asrb", "asrd", "asrx", "band", "bcc", "bclr", "bcs", "beor", "beq", "bge", "bgnd", "bgt", "bhcc", "bhcs", "bhi", "biand", "bieor", "bih", "bil", "bior", "bit", "bita", "bitb", "bitd", "bitmd", "ble", "bls", "blt", "bmc", "bmi", "bms", "bne", "bor", "bpl", "brclr", "brset", "bra", "brn", "bset", "bsr", "bvc", "bvs", "call", "cba", "cbeq", "cbeqa", "cbeqx", "clc", "cli", "clr", "clra", "clrb", "clrd", "clre", "clrf", "clrh", "clrw", "clrx", "clv", "cmp", "cmpa", "cmpb", "cmpd", "cmpe", "cmpf", "cmpr", "cmps", "cmpu", "cmpw", "cmpx", "cmpy", "com", "coma", "comb", "comd", "come", "comf", "comw", "comx", "cpd", "cphx", "cps", "cpx", "cpy", "cwai", "daa", "dbeq", "dbne", "dbnz", "dbnza", "dbnzx", "dec", "deca", "decb", "decd", "dece", "decf", "decw", "decx", "des", "dex", "dey", "div", "divd", "divq", "ediv", "edivs", "eim", "emacs", "emaxd", "emaxm", "emind", "eminm", "emul", "emuls", "eor", "eora", "eorb", "eord", "eorr", "etbl", "exg", "fdiv", "ibeq", "ibne", "idiv", "idivs", "illgl", "inc", "inca", "incb", "incd", "ince", "incf", "incw", "incx", "ins", "inx", "iny", "jmp", "jsr", "lbcc", "lbcs", "lbeq", "lbge", "lbgt", "lbhi", "lble", "lbls", "lblt", "lbmi", "lbne", "lbpl", "lbra", "lbrn", "lbsr", "lbvc", "lbvs", "lda", "ldaa", "ldab", "ldb", "ldbt", "ldd", "lde", "ldf", "ldhx", "ldmd", "ldq", "lds", "ldu", "ldw", "ldx", "ldy", "leas", "leau", "leax", "leay", "lsl", "lsla", "lslb", "lsld", "lslx", "lsr", "lsra", "lsrb", "lsrd", "lsrw", "lsrx", "maxa", "maxm", "mem", "mina", "minm", "mov", "movb", "movw", "mul", "muld", "neg", "nega", "negb", "negd", "negx", "nop", "nsa", "oim", "ora", "oraa", "orab", "orb", "orcc", "ord", "orr", "psha", "pshb", "pshc", "pshd", "pshh", "pshs", "pshsw", "pshu", "pshuw", "pshx", "pshy", "pula", "pulb", "pulc", "puld", "pulh", "puls", "pulsw", "pulu", "puluw", "pulx", "puly", "rev", "revw", "rol", "rola", "rolb", "rold", "rolw", "rolx", "ror", "rora", "rorb", "rord", "rorw", "rorx", "rsp", "rtc", "rti", "rts", "sba", "sbc", "sbca", "sbcb", "sbcd", "sbcr", "sec", "sei", "sev", "sex", "sexw", "slp", "sta", "staa", "stab", "stb", "stbt", "std", "ste", "stf", "stop", "sthx", "stq", "sts", "stu", "stw", "stx", "sty", "sub", "suba", "subb", "subd", "sube", "subf", "subr", "subw", "swi", "swi2", "swi3", "sync", "tab", "tap", "tax", "tba", "tbeq", "tbl", "tbne", "test", "tfm", "tfr", "tim", "tpa", "tst", "tsta", "tstb", "tstd", "tste", "tstf", "tstw", "tstx", "tsx", "tsy", "txa", "txs", "tys", "wai", "wait", "wav", "wavr", "xgdx", "xgdy", }; static const name_map s_group_names[] = { { M680X_GRP_INVALID, "" }, { M680X_GRP_JUMP, "jump" }, { M680X_GRP_CALL, "call" }, { M680X_GRP_RET, "return" }, { M680X_GRP_INT, "interrupt" }, { M680X_GRP_IRET, "interrupt_return" }, { M680X_GRP_PRIV, "privileged" }, { M680X_GRP_BRAREL, "branch_relative" }, }; #endif static void printRegName(cs_struct *handle, SStream *OS, unsigned int reg) { #ifndef CAPSTONE_DIET SStream_concat(OS, handle->reg_name((csh)handle, reg)); #endif } static void printInstructionName(cs_struct *handle, SStream *OS, unsigned int insn) { #ifndef CAPSTONE_DIET SStream_concat(OS, handle->insn_name((csh)handle, insn)); #endif } static uint32_t get_unsigned(int32_t value, int byte_size) { switch (byte_size) { case 1: return (uint32_t)(value & 0xff); case 2: return (uint32_t)(value & 0xffff); default: case 4: return (uint32_t)value; } } static void printIncDec(bool isPost, SStream *O, m680x_info *info, cs_m680x_op *op) { static const char s_inc_dec[][3] = { "--", "-", "", "+", "++" }; if (!op->idx.inc_dec) return; if ((!isPost && !(op->idx.flags & M680X_IDX_POST_INC_DEC)) || (isPost && (op->idx.flags & M680X_IDX_POST_INC_DEC))) { const char *prePostfix = ""; if (info->cpu_type == M680X_CPU_TYPE_CPU12) prePostfix = (op->idx.inc_dec < 0) ? "-" : "+"; else if (op->idx.inc_dec >= -2 && (op->idx.inc_dec <= 2)) { prePostfix = (char *)s_inc_dec[op->idx.inc_dec + 2]; } SStream_concat(O, prePostfix); } } static void printOperand(MCInst *MI, SStream *O, m680x_info *info, cs_m680x_op *op) { switch (op->type) { case M680X_OP_REGISTER: printRegName(MI->csh, O, op->reg); break; case M680X_OP_CONSTANT: SStream_concat(O, "%u", op->const_val); break; case M680X_OP_IMMEDIATE: if (MI->csh->imm_unsigned) SStream_concat(O, "#%u", get_unsigned(op->imm, op->size)); else SStream_concat(O, "#%d", op->imm); break; case M680X_OP_INDEXED: if (op->idx.flags & M680X_IDX_INDIRECT) SStream_concat(O, "["); if (op->idx.offset_reg != M680X_REG_INVALID) printRegName(MI->csh, O, op->idx.offset_reg); else if (op->idx.offset_bits > 0) { if (op->idx.base_reg == M680X_REG_PC) SStream_concat(O, "$%04x", op->idx.offset_addr); else SStream_concat(O, "%d", op->idx.offset); } else if (op->idx.inc_dec != 0 && info->cpu_type == M680X_CPU_TYPE_CPU12) SStream_concat(O, "%d", abs(op->idx.inc_dec)); if (!(op->idx.flags & M680X_IDX_NO_COMMA)) SStream_concat(O, ", "); printIncDec(false, O, info, op); printRegName(MI->csh, O, op->idx.base_reg); if (op->idx.base_reg == M680X_REG_PC && (op->idx.offset_bits > 0)) SStream_concat(O, "r"); printIncDec(true, O, info, op); if (op->idx.flags & M680X_IDX_INDIRECT) SStream_concat(O, "]"); break; case M680X_OP_RELATIVE: SStream_concat(O, "$%04x", op->rel.address); break; case M680X_OP_DIRECT: SStream_concat(O, "$%02x", op->direct_addr); break; case M680X_OP_EXTENDED: if (op->ext.indirect) SStream_concat(O, "[$%04x]", op->ext.address); else { if (op->ext.address < 256) { SStream_concat(O, ">$%04x", op->ext.address); } else { SStream_concat(O, "$%04x", op->ext.address); } } break; default: SStream_concat(O, ""); break; } } static const char *getDelimiter(m680x_info *info, cs_m680x *m680x) { bool indexed = false; int count = 0; int i; if (info->insn == M680X_INS_TFM) return ", "; if (m680x->op_count > 1) { for (i = 0; i < m680x->op_count; ++i) { if (m680x->operands[i].type == M680X_OP_INDEXED) indexed = true; if (m680x->operands[i].type != M680X_OP_REGISTER) count++; } } return (indexed && (count >= 1)) ? "; " : ", "; }; void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo) { m680x_info *info = (m680x_info *)PrinterInfo; cs_m680x *m680x = &info->m680x; cs_detail *detail = MI->flat_insn->detail; int suppress_operands = 0; const char *delimiter = getDelimiter(info, m680x); int i; if (detail != NULL) memcpy(&detail->m680x, m680x, sizeof(cs_m680x)); if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) { if (m680x->op_count) SStream_concat(O, "fcb $%02x", m680x->operands[0].imm); else SStream_concat(O, "fcb $"); return; } printInstructionName(MI->csh, O, info->insn); SStream_concat(O, " "); if ((m680x->flags & M680X_FIRST_OP_IN_MNEM) != 0) suppress_operands++; if ((m680x->flags & M680X_SECOND_OP_IN_MNEM) != 0) suppress_operands++; for (i = 0; i < m680x->op_count; ++i) { if (i >= suppress_operands) { printOperand(MI, O, info, &m680x->operands[i]); if ((i + 1) != m680x->op_count) SStream_concat(O, delimiter); } } } const char *M680X_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(s_reg_names)) return NULL; return s_reg_names[(int)reg]; #else return NULL; #endif } const char *M680X_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= ARR_SIZE(s_instruction_names)) return NULL; else return s_instruction_names[(int)id]; #else return NULL; #endif } const char *M680X_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(s_group_names, ARR_SIZE(s_group_names), id); #else return NULL; #endif } cs_err M680X_instprinter_init(cs_struct *ud) { #ifndef CAPSTONE_DIET if (M680X_REG_ENDING != ARR_SIZE(s_reg_names)) { CS_ASSERT(M680X_REG_ENDING == ARR_SIZE(s_reg_names)); return CS_ERR_MODE; } if (M680X_INS_ENDING != ARR_SIZE(s_instruction_names)) { CS_ASSERT(M680X_INS_ENDING == ARR_SIZE(s_instruction_names)); return CS_ERR_MODE; } if (M680X_GRP_ENDING != ARR_SIZE(s_group_names)) { CS_ASSERT(M680X_GRP_ENDING == ARR_SIZE(s_group_names)); return CS_ERR_MODE; } #endif return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XInstPrinter.h000064400000000000000000000012220072674642500210340ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #ifndef CS_M680XINSTPRINTER_H #define CS_M680XINSTPRINTER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" struct SStream; void M680X_init(MCRegisterInfo *MRI); void M680X_printInst(MCInst *MI, struct SStream *O, void *Info); const char *M680X_reg_name(csh handle, unsigned int reg); const char *M680X_insn_name(csh handle, unsigned int id); const char *M680X_group_name(csh handle, unsigned int id); void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci); #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XModule.c000064400000000000000000000035350072674642500200040ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #ifdef CAPSTONE_HAS_M680X #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "M680XDisassembler.h" #include "M680XDisassemblerInternals.h" #include "M680XInstPrinter.h" #include "M680XModule.h" cs_err M680X_global_init(cs_struct *ud) { m680x_info *info; cs_err errcode; /* Do some validation checks */ errcode = M680X_disassembler_init(ud); if (errcode != CS_ERR_OK) return errcode; errcode = M680X_instprinter_init(ud); if (errcode != CS_ERR_OK) return errcode; // verify if requested mode is valid if (ud->mode & ~(CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08)) { // At least one mode is not supported by M680X return CS_ERR_MODE; } if (!(ud->mode & (CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08))) { // At least the cpu type has to be selected. No default. return CS_ERR_MODE; } info = cs_mem_malloc(sizeof(m680x_info)); if (!info) return CS_ERR_MEM; ud->printer = M680X_printInst; ud->printer_info = info; ud->getinsn_info = NULL; ud->disasm = M680X_getInstruction; ud->reg_name = M680X_reg_name; ud->insn_id = M680X_get_insn_id; ud->insn_name = M680X_insn_name; ud->group_name = M680X_group_name; ud->skipdata_size = 1; ud->post_printer = NULL; #ifndef CAPSTONE_DIET ud->reg_access = M680X_reg_access; #endif return CS_ERR_OK; } cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value) { //TODO return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/M680X/M680XModule.h000064400000000000000000000004410072674642500200020ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_M680X_MODULE_H #define CS_M680X_MODULE_H #include "../../utils.h" cs_err M680X_global_init(cs_struct *ud); cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/M680X/cpu12.inc000064400000000000000000000313330072674642500173320ustar 00000000000000 // CPU12 instructions on PAGE1 static const inst_page1 g_cpu12_inst_page1_table[256] = { // 0x0x { M680X_INS_BGND, inh_hid, inh_hid }, { M680X_INS_MEM, inh_hid, inh_hid }, { M680X_INS_INY, inh_hid, inh_hid }, { M680X_INS_DEY, inh_hid, inh_hid }, { M680X_INS_DBEQ, loop_hid, inh_hid }, // or DBNE/IBEQ/IBNE/TBEQ/TBNE { M680X_INS_JMP, idx12_hid, inh_hid }, { M680X_INS_JMP, ext_hid, inh_hid }, { M680X_INS_BSR, rel8_hid, inh_hid }, { M680X_INS_INX, inh_hid, inh_hid }, { M680X_INS_DEX, inh_hid, inh_hid }, { M680X_INS_RTC, inh_hid, inh_hid }, { M680X_INS_RTI, inh_hid, inh_hid }, { M680X_INS_BSET, idx12_hid, imm8_hid }, { M680X_INS_BCLR, idx12_hid, imm8_hid }, { M680X_INS_BRSET, idx12_hid, imm8rel_hid }, { M680X_INS_BRCLR, idx12_hid, imm8rel_hid }, // 0x1x { M680X_INS_ANDCC, imm8_hid, inh_hid }, { M680X_INS_EDIV, inh_hid, inh_hid }, { M680X_INS_MUL, inh_hid, inh_hid }, { M680X_INS_EMUL, inh_hid, inh_hid }, { M680X_INS_ORCC, imm8_hid, inh_hid }, { M680X_INS_JSR, idx12_hid, inh_hid }, { M680X_INS_JSR, ext_hid, inh_hid }, { M680X_INS_JSR, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LEAY, idx12_hid, inh_hid }, { M680X_INS_LEAX, idx12_hid, inh_hid }, { M680X_INS_LEAS, idx12_hid, inh_hid }, { M680X_INS_BSET, ext_hid, imm8_hid }, { M680X_INS_BCLR, ext_hid, imm8_hid }, { M680X_INS_BRSET, ext_hid, imm8rel_hid }, { M680X_INS_BRCLR, ext_hid, imm8rel_hid }, // 0x2x, relative branch instructions { M680X_INS_BRA, rel8_hid, inh_hid }, { M680X_INS_BRN, rel8_hid, inh_hid }, { M680X_INS_BHI, rel8_hid, inh_hid }, { M680X_INS_BLS, rel8_hid, inh_hid }, { M680X_INS_BCC, rel8_hid, inh_hid }, { M680X_INS_BCS, rel8_hid, inh_hid }, { M680X_INS_BNE, rel8_hid, inh_hid }, { M680X_INS_BEQ, rel8_hid, inh_hid }, { M680X_INS_BVC, rel8_hid, inh_hid }, { M680X_INS_BVS, rel8_hid, inh_hid }, { M680X_INS_BPL, rel8_hid, inh_hid }, { M680X_INS_BMI, rel8_hid, inh_hid }, { M680X_INS_BGE, rel8_hid, inh_hid }, { M680X_INS_BLT, rel8_hid, inh_hid }, { M680X_INS_BGT, rel8_hid, inh_hid }, { M680X_INS_BLE, rel8_hid, inh_hid }, // 0x3x { M680X_INS_PULX, inh_hid, inh_hid }, { M680X_INS_PULY, inh_hid, inh_hid }, { M680X_INS_PULA, inh_hid, inh_hid }, { M680X_INS_PULB, inh_hid, inh_hid }, { M680X_INS_PSHX, inh_hid, inh_hid }, { M680X_INS_PSHY, inh_hid, inh_hid }, { M680X_INS_PSHA, inh_hid, inh_hid }, { M680X_INS_PSHB, inh_hid, inh_hid }, { M680X_INS_PULC, inh_hid, inh_hid }, { M680X_INS_PSHC, inh_hid, inh_hid }, { M680X_INS_PULD, inh_hid, inh_hid }, { M680X_INS_PSHD, inh_hid, inh_hid }, { M680X_INS_WAVR, inh_hid, inh_hid }, { M680X_INS_RTS, inh_hid, inh_hid }, { M680X_INS_WAI, inh_hid, inh_hid }, { M680X_INS_SWI, inh_hid, inh_hid }, // 0x4x { M680X_INS_NEGA, inh_hid, inh_hid }, { M680X_INS_COMA, inh_hid, inh_hid }, { M680X_INS_INCA, inh_hid, inh_hid }, { M680X_INS_DECA, inh_hid, inh_hid }, { M680X_INS_LSRA, inh_hid, inh_hid }, { M680X_INS_ROLA, inh_hid, inh_hid }, { M680X_INS_RORA, inh_hid, inh_hid }, { M680X_INS_ASRA, inh_hid, inh_hid }, { M680X_INS_ASLA, inh_hid, inh_hid }, { M680X_INS_LSRD, inh_hid, inh_hid }, { M680X_INS_CALL, ext_hid, index_hid }, { M680X_INS_CALL, idx12_hid, index_hid }, { M680X_INS_BSET, dir_hid, imm8_hid }, { M680X_INS_BCLR, dir_hid, imm8_hid }, { M680X_INS_BRSET, dir_hid, imm8rel_hid }, { M680X_INS_BRCLR, dir_hid, imm8rel_hid }, // 0x5x { M680X_INS_NEGB, inh_hid, inh_hid }, { M680X_INS_COMB, inh_hid, inh_hid }, { M680X_INS_INCB, inh_hid, inh_hid }, { M680X_INS_DECB, inh_hid, inh_hid }, { M680X_INS_LSRB, inh_hid, inh_hid }, { M680X_INS_ROLB, inh_hid, inh_hid }, { M680X_INS_RORB, inh_hid, inh_hid }, { M680X_INS_ASRB, inh_hid, inh_hid }, { M680X_INS_ASLB, inh_hid, inh_hid }, { M680X_INS_ASLD, inh_hid, inh_hid }, { M680X_INS_STAA, dir_hid, inh_hid }, { M680X_INS_STAB, dir_hid, inh_hid }, { M680X_INS_STD, dir_hid, inh_hid }, { M680X_INS_STY, dir_hid, inh_hid }, { M680X_INS_STX, dir_hid, inh_hid }, { M680X_INS_STS, dir_hid, inh_hid }, // 0x6x { M680X_INS_NEG, idx12_hid, inh_hid }, { M680X_INS_COM, idx12_hid, inh_hid }, { M680X_INS_INC, idx12_hid, inh_hid }, { M680X_INS_DEC, idx12_hid, inh_hid }, { M680X_INS_LSR, idx12_hid, inh_hid }, { M680X_INS_ROL, idx12_hid, inh_hid }, { M680X_INS_ROR, idx12_hid, inh_hid }, { M680X_INS_ASR, idx12_hid, inh_hid }, { M680X_INS_ASL, idx12_hid, inh_hid }, { M680X_INS_CLR, idx12_hid, inh_hid }, { M680X_INS_STAA, idx12_hid, inh_hid }, { M680X_INS_STAB, idx12_hid, inh_hid }, { M680X_INS_STD, idx12_hid, inh_hid }, { M680X_INS_STY, idx12_hid, inh_hid }, { M680X_INS_STX, idx12_hid, inh_hid }, { M680X_INS_STS, idx12_hid, inh_hid }, // 0x7x { M680X_INS_NEG, ext_hid, inh_hid }, { M680X_INS_COM, ext_hid, inh_hid }, { M680X_INS_INC, ext_hid, inh_hid }, { M680X_INS_DEC, ext_hid, inh_hid }, { M680X_INS_LSR, ext_hid, inh_hid }, { M680X_INS_ROL, ext_hid, inh_hid }, { M680X_INS_ROR, ext_hid, inh_hid }, { M680X_INS_ASR, ext_hid, inh_hid }, { M680X_INS_ASL, ext_hid, inh_hid }, { M680X_INS_CLR, ext_hid, inh_hid }, { M680X_INS_STAA, ext_hid, inh_hid }, { M680X_INS_STAB, ext_hid, inh_hid }, { M680X_INS_STD, ext_hid, inh_hid }, { M680X_INS_STY, ext_hid, inh_hid }, { M680X_INS_STX, ext_hid, inh_hid }, { M680X_INS_STS, ext_hid, inh_hid }, // 0x8x { M680X_INS_SUBA, imm8_hid, inh_hid }, { M680X_INS_CMPA, imm8_hid, inh_hid }, { M680X_INS_SBCA, imm8_hid, inh_hid }, { M680X_INS_SUBD, imm16_hid, inh_hid }, { M680X_INS_ANDA, imm8_hid, inh_hid }, { M680X_INS_BITA, imm8_hid, inh_hid }, { M680X_INS_LDAA, imm8_hid, inh_hid }, { M680X_INS_CLRA, inh_hid, inh_hid }, { M680X_INS_EORA, imm8_hid, inh_hid }, { M680X_INS_ADCA, imm8_hid, inh_hid }, { M680X_INS_ORAA, imm8_hid, inh_hid }, { M680X_INS_ADDA, imm8_hid, inh_hid }, { M680X_INS_CPD, imm16_hid, inh_hid }, { M680X_INS_CPY, imm16_hid, inh_hid }, { M680X_INS_CPX, imm16_hid, inh_hid }, { M680X_INS_CPS, imm16_hid, inh_hid }, // 0x9x { M680X_INS_SUBA, dir_hid, inh_hid }, { M680X_INS_CMPA, dir_hid, inh_hid }, { M680X_INS_SBCA, dir_hid, inh_hid }, { M680X_INS_SUBD, dir_hid, inh_hid }, { M680X_INS_ANDA, dir_hid, inh_hid }, { M680X_INS_BITA, dir_hid, inh_hid }, { M680X_INS_LDAA, dir_hid, inh_hid }, { M680X_INS_TSTA, inh_hid, inh_hid }, { M680X_INS_EORA, dir_hid, inh_hid }, { M680X_INS_ADCA, dir_hid, inh_hid }, { M680X_INS_ORAA, dir_hid, inh_hid }, { M680X_INS_ADDA, dir_hid, inh_hid }, { M680X_INS_CPD, dir_hid, inh_hid }, { M680X_INS_CPY, dir_hid, inh_hid }, { M680X_INS_CPX, dir_hid, inh_hid }, { M680X_INS_CPS, dir_hid, inh_hid }, // 0xAx { M680X_INS_SUBA, idx12_hid, inh_hid }, { M680X_INS_CMPA, idx12_hid, inh_hid }, { M680X_INS_SBCA, idx12_hid, inh_hid }, { M680X_INS_SUBD, idx12_hid, inh_hid }, { M680X_INS_ANDA, idx12_hid, inh_hid }, { M680X_INS_BITA, idx12_hid, inh_hid }, { M680X_INS_LDAA, idx12_hid, inh_hid }, { M680X_INS_NOP, inh_hid, inh_hid }, { M680X_INS_EORA, idx12_hid, inh_hid }, { M680X_INS_ADCA, idx12_hid, inh_hid }, { M680X_INS_ORAA, idx12_hid, inh_hid }, { M680X_INS_ADDA, idx12_hid, inh_hid }, { M680X_INS_CPD, idx12_hid, inh_hid }, { M680X_INS_CPY, idx12_hid, inh_hid }, { M680X_INS_CPX, idx12_hid, inh_hid }, { M680X_INS_CPS, idx12_hid, inh_hid }, // 0xBx { M680X_INS_SUBA, ext_hid, inh_hid }, { M680X_INS_CMPA, ext_hid, inh_hid }, { M680X_INS_SBCA, ext_hid, inh_hid }, { M680X_INS_SUBD, ext_hid, inh_hid }, { M680X_INS_ANDA, ext_hid, inh_hid }, { M680X_INS_BITA, ext_hid, inh_hid }, { M680X_INS_LDAA, ext_hid, inh_hid }, { M680X_INS_TFR, rr12_hid, inh_hid }, // or EXG { M680X_INS_EORA, ext_hid, inh_hid }, { M680X_INS_ADCA, ext_hid, inh_hid }, { M680X_INS_ORAA, ext_hid, inh_hid }, { M680X_INS_ADDA, ext_hid, inh_hid }, { M680X_INS_CPD, ext_hid, inh_hid }, { M680X_INS_CPY, ext_hid, inh_hid }, { M680X_INS_CPX, ext_hid, inh_hid }, { M680X_INS_CPS, ext_hid, inh_hid }, // 0xCx { M680X_INS_SUBB, imm8_hid, inh_hid }, { M680X_INS_CMPB, imm8_hid, inh_hid }, { M680X_INS_SBCB, imm8_hid, inh_hid }, { M680X_INS_ADDD, imm16_hid, inh_hid }, { M680X_INS_ANDB, imm8_hid, inh_hid }, { M680X_INS_BITB, imm8_hid, inh_hid }, { M680X_INS_LDAB, imm8_hid, inh_hid }, { M680X_INS_CLRB, inh_hid, inh_hid }, { M680X_INS_EORB, imm8_hid, inh_hid }, { M680X_INS_ADCB, imm8_hid, inh_hid }, { M680X_INS_ORAB, imm8_hid, inh_hid }, { M680X_INS_ADDB, imm8_hid, inh_hid }, { M680X_INS_LDD, imm16_hid, inh_hid }, { M680X_INS_LDY, imm16_hid, inh_hid }, { M680X_INS_LDX, imm16_hid, inh_hid }, { M680X_INS_LDS, imm16_hid, inh_hid }, // 0xDx { M680X_INS_SUBB, dir_hid, inh_hid }, { M680X_INS_CMPB, dir_hid, inh_hid }, { M680X_INS_SBCB, dir_hid, inh_hid }, { M680X_INS_ADDD, dir_hid, inh_hid }, { M680X_INS_ANDB, dir_hid, inh_hid }, { M680X_INS_BITB, dir_hid, inh_hid }, { M680X_INS_LDAB, dir_hid, inh_hid }, { M680X_INS_TSTB, inh_hid, inh_hid }, { M680X_INS_EORB, dir_hid, inh_hid }, { M680X_INS_ADCB, dir_hid, inh_hid }, { M680X_INS_ORAB, dir_hid, inh_hid }, { M680X_INS_ADDB, dir_hid, inh_hid }, { M680X_INS_LDD, dir_hid, inh_hid }, { M680X_INS_LDY, dir_hid, inh_hid }, { M680X_INS_LDX, dir_hid, inh_hid }, { M680X_INS_LDS, dir_hid, inh_hid }, // 0xEx { M680X_INS_SUBB, idx12_hid, inh_hid }, { M680X_INS_CMPB, idx12_hid, inh_hid }, { M680X_INS_SBCB, idx12_hid, inh_hid }, { M680X_INS_ADDD, idx12_hid, inh_hid }, { M680X_INS_ANDB, idx12_hid, inh_hid }, { M680X_INS_BITB, idx12_hid, inh_hid }, { M680X_INS_LDAB, idx12_hid, inh_hid }, { M680X_INS_TST, idx12_hid, inh_hid }, { M680X_INS_EORB, idx12_hid, inh_hid }, { M680X_INS_ADCB, idx12_hid, inh_hid }, { M680X_INS_ORAB, idx12_hid, inh_hid }, { M680X_INS_ADDB, idx12_hid, inh_hid }, { M680X_INS_LDD, idx12_hid, inh_hid }, { M680X_INS_LDY, idx12_hid, inh_hid }, { M680X_INS_LDX, idx12_hid, inh_hid }, { M680X_INS_LDS, idx12_hid, inh_hid }, // 0xFx { M680X_INS_SUBA, ext_hid, inh_hid }, { M680X_INS_CMPA, ext_hid, inh_hid }, { M680X_INS_SBCA, ext_hid, inh_hid }, { M680X_INS_ADDD, ext_hid, inh_hid }, { M680X_INS_ANDA, ext_hid, inh_hid }, { M680X_INS_BITA, ext_hid, inh_hid }, { M680X_INS_LDAA, ext_hid, inh_hid }, { M680X_INS_TST, ext_hid, inh_hid }, { M680X_INS_EORA, ext_hid, inh_hid }, { M680X_INS_ADCA, ext_hid, inh_hid }, { M680X_INS_ORAA, ext_hid, inh_hid }, { M680X_INS_ADDA, ext_hid, inh_hid }, { M680X_INS_LDD, ext_hid, inh_hid }, { M680X_INS_LDY, ext_hid, inh_hid }, { M680X_INS_LDX, ext_hid, inh_hid }, { M680X_INS_LDS, ext_hid, inh_hid }, }; // CPU12 instructions on PAGE2 static const inst_pageX g_cpu12_inst_page2_table[] = { { 0x00, M680X_INS_MOVW, imm16i12x_hid, inh_hid }, { 0x01, M680X_INS_MOVW, exti12x_hid, inh_hid }, { 0x02, M680X_INS_MOVW, idx12_hid, idx12_hid }, { 0x03, M680X_INS_MOVW, imm16_hid, ext_hid }, { 0x04, M680X_INS_MOVW, ext_hid, ext_hid }, { 0x05, M680X_INS_MOVW, idx12_hid, ext_hid }, { 0x06, M680X_INS_ABA, inh_hid, inh_hid }, { 0x07, M680X_INS_DAA, inh_hid, inh_hid }, { 0x08, M680X_INS_MOVB, imm8i12x_hid, inh_hid }, { 0x09, M680X_INS_MOVB, exti12x_hid, inh_hid }, { 0x0a, M680X_INS_MOVB, idx12_hid, idx12_hid }, { 0x0b, M680X_INS_MOVB, imm8_hid, ext_hid }, { 0x0c, M680X_INS_MOVB, ext_hid, ext_hid }, { 0x0d, M680X_INS_MOVB, idx12_hid, ext_hid }, { 0x0e, M680X_INS_TAB, inh_hid, inh_hid }, { 0x0f, M680X_INS_TBA, inh_hid, inh_hid }, { 0x10, M680X_INS_IDIV, inh_hid, inh_hid }, { 0x11, M680X_INS_FDIV, inh_hid, inh_hid }, { 0x12, M680X_INS_EMACS, ext_hid, inh_hid }, { 0x13, M680X_INS_EMULS, inh_hid, inh_hid }, { 0x14, M680X_INS_EDIVS, inh_hid, inh_hid }, { 0x15, M680X_INS_IDIVS, inh_hid, inh_hid }, { 0x16, M680X_INS_SBA, inh_hid, inh_hid }, { 0x17, M680X_INS_CBA, inh_hid, inh_hid }, { 0x18, M680X_INS_MAXA, idx12_hid, inh_hid }, { 0x19, M680X_INS_MINA, idx12_hid, inh_hid }, { 0x1a, M680X_INS_EMAXD, idx12_hid, inh_hid }, { 0x1b, M680X_INS_EMIND, idx12_hid, inh_hid }, { 0x1c, M680X_INS_MAXM, idx12_hid, inh_hid }, { 0x1d, M680X_INS_MINM, idx12_hid, inh_hid }, { 0x1e, M680X_INS_EMAXM, idx12_hid, inh_hid }, { 0x1f, M680X_INS_EMINM, idx12_hid, inh_hid }, { 0x20, M680X_INS_LBRA, rel16_hid, inh_hid }, { 0x21, M680X_INS_LBRN, rel16_hid, inh_hid }, { 0x22, M680X_INS_LBHI, rel16_hid, inh_hid }, { 0x23, M680X_INS_LBLS, rel16_hid, inh_hid }, { 0x24, M680X_INS_LBCC, rel16_hid, inh_hid }, { 0x25, M680X_INS_LBCS, rel16_hid, inh_hid }, { 0x26, M680X_INS_LBNE, rel16_hid, inh_hid }, { 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid }, { 0x28, M680X_INS_LBVC, rel16_hid, inh_hid }, { 0x29, M680X_INS_LBVS, rel16_hid, inh_hid }, { 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid }, { 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid }, { 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid }, { 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid }, { 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid }, { 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid }, { 0x3a, M680X_INS_REV, inh_hid, inh_hid }, { 0x3b, M680X_INS_REVW, inh_hid, inh_hid }, { 0x3c, M680X_INS_WAV, inh_hid, inh_hid }, { 0x3d, M680X_INS_TBL, idx12s_hid, inh_hid }, { 0x3e, M680X_INS_STOP, inh_hid, inh_hid }, { 0x3f, M680X_INS_ETBL, idx12s_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/hcs08.inc000064400000000000000000000047640072674642500173350ustar 00000000000000 // Additional instructions only supported on HCS08 static const inst_pageX g_hcs08_inst_overlay_table[] = { { 0x32, M680X_INS_LDHX, ext_hid, inh_hid }, { 0x3e, M680X_INS_CPHX, ext_hid, inh_hid }, { 0x82, M680X_INS_BGND, inh_hid, inh_hid }, { 0x96, M680X_INS_STHX, ext_hid, inh_hid }, }; // HCS08 PAGE2 instructions (prefix 0x9E) static const inst_pageX g_hcs08_inst_page2_table[] = { { 0x60, M680X_INS_NEG, idxS_hid, inh_hid }, { 0x61, M680X_INS_CBEQ, idxS_hid,rel8_hid }, { 0x63, M680X_INS_COM, idxS_hid, inh_hid }, { 0x64, M680X_INS_LSR, idxS_hid, inh_hid }, { 0x66, M680X_INS_ROR, idxS_hid, inh_hid }, { 0x67, M680X_INS_ASR, idxS_hid, inh_hid }, { 0x68, M680X_INS_LSL, idxS_hid, inh_hid }, { 0x69, M680X_INS_ROL, idxS_hid, inh_hid }, { 0x6a, M680X_INS_DEC, idxS_hid, inh_hid }, { 0x6b, M680X_INS_DBNZ, idxS_hid,rel8_hid }, { 0x6c, M680X_INS_INC, idxS_hid, inh_hid }, { 0x6d, M680X_INS_TST, idxS_hid, inh_hid }, { 0x6f, M680X_INS_CLR, idxS_hid, inh_hid }, { 0xae, M680X_INS_LDHX, idxX0_hid, inh_hid }, { 0xbe, M680X_INS_LDHX, idxX16_hid, inh_hid }, { 0xce, M680X_INS_LDHX, idxX_hid, inh_hid }, { 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid }, { 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid }, { 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid }, { 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid }, { 0xd4, M680X_INS_AND, idxS16_hid, inh_hid }, { 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid }, { 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid }, { 0xd7, M680X_INS_STA, idxS16_hid, inh_hid }, { 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid }, { 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid }, { 0xda, M680X_INS_ORA, idxS16_hid, inh_hid }, { 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid }, { 0xde, M680X_INS_LDX, idxS16_hid, inh_hid }, { 0xdf, M680X_INS_STX, idxS16_hid, inh_hid }, { 0xe0, M680X_INS_SUB, idxS_hid, inh_hid }, { 0xe1, M680X_INS_CMP, idxS_hid, inh_hid }, { 0xe2, M680X_INS_SBC, idxS_hid, inh_hid }, { 0xe3, M680X_INS_CPX, idxS_hid, inh_hid }, { 0xe4, M680X_INS_AND, idxS_hid, inh_hid }, { 0xe5, M680X_INS_BIT, idxS_hid, inh_hid }, { 0xe6, M680X_INS_LDA, idxS_hid, inh_hid }, { 0xe7, M680X_INS_STA, idxS_hid, inh_hid }, { 0xe8, M680X_INS_EOR, idxS_hid, inh_hid }, { 0xe9, M680X_INS_ADC, idxS_hid, inh_hid }, { 0xea, M680X_INS_ORA, idxS_hid, inh_hid }, { 0xeb, M680X_INS_ADD, idxS_hid, inh_hid }, { 0xee, M680X_INS_LDX, idxS_hid, inh_hid }, { 0xef, M680X_INS_STX, idxS_hid, inh_hid }, { 0xf3, M680X_INS_CPHX, idxS_hid, inh_hid }, { 0xfe, M680X_INS_LDHX, idxS_hid, inh_hid }, { 0xff, M680X_INS_STHX, idxS_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/hd6301.inc000064400000000000000000000010720072674642500173020ustar 00000000000000 // Additional instructions only supported on HD6301/3 static const inst_pageX g_hd6301_inst_overlay_table[] = { { 0x18, M680X_INS_XGDX, inh_hid, inh_hid }, { 0x1a, M680X_INS_SLP, inh_hid, inh_hid }, { 0x61, M680X_INS_AIM, imm8_hid, idxX_hid }, { 0x62, M680X_INS_OIM, imm8_hid, idxX_hid }, { 0x65, M680X_INS_EIM, imm8_hid, idxX_hid }, { 0x6B, M680X_INS_TIM, imm8_hid, idxX_hid }, { 0x71, M680X_INS_AIM, imm8_hid, dir_hid }, { 0x72, M680X_INS_OIM, imm8_hid, dir_hid }, { 0x75, M680X_INS_EIM, imm8_hid, dir_hid }, { 0x7B, M680X_INS_TIM, imm8_hid, dir_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/hd6309.inc000064400000000000000000000263070072674642500173220ustar 00000000000000 // The following array has to be sorted by increasing // opcodes. Otherwise the binary_search will fail. // // Additional instructions only supported on HD6309 PAGE1 static const inst_pageX g_hd6309_inst_overlay_table[] = { { 0x01, M680X_INS_OIM, imm8_hid, dir_hid }, { 0x02, M680X_INS_AIM, imm8_hid, dir_hid }, { 0x05, M680X_INS_EIM, imm8_hid, dir_hid }, { 0x0B, M680X_INS_TIM, imm8_hid, dir_hid }, { 0x14, M680X_INS_SEXW, inh_hid, inh_hid }, { 0x61, M680X_INS_OIM, imm8_hid, idx09_hid }, { 0x62, M680X_INS_AIM, imm8_hid, idx09_hid }, { 0x65, M680X_INS_EIM, imm8_hid, idx09_hid }, { 0x6B, M680X_INS_TIM, imm8_hid, idx09_hid }, { 0x71, M680X_INS_OIM, imm8_hid, ext_hid }, { 0x72, M680X_INS_AIM, imm8_hid, ext_hid }, { 0x75, M680X_INS_EIM, imm8_hid, ext_hid }, { 0x7B, M680X_INS_TIM, imm8_hid, ext_hid }, { 0xCD, M680X_INS_LDQ, imm32_hid, inh_hid }, }; // The following array has to be sorted by increasing // opcodes. Otherwise the binary_search will fail. // // HD6309 PAGE2 instructions (with prefix 0x10) static const inst_pageX g_hd6309_inst_page2_table[] = { // 0x2x, relative long branch instructions { 0x21, M680X_INS_LBRN, rel16_hid, inh_hid }, { 0x22, M680X_INS_LBHI, rel16_hid, inh_hid }, { 0x23, M680X_INS_LBLS, rel16_hid, inh_hid }, { 0x24, M680X_INS_LBCC, rel16_hid, inh_hid }, { 0x25, M680X_INS_LBCS, rel16_hid, inh_hid }, { 0x26, M680X_INS_LBNE, rel16_hid, inh_hid }, { 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid }, { 0x28, M680X_INS_LBVC, rel16_hid, inh_hid }, { 0x29, M680X_INS_LBVS, rel16_hid, inh_hid }, { 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid }, { 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid }, { 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid }, { 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid }, { 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid }, { 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid }, // 0x3x { 0x30, M680X_INS_ADDR, rr09_hid, inh_hid }, { 0x31, M680X_INS_ADCR, rr09_hid, inh_hid }, { 0x32, M680X_INS_SUBR, rr09_hid, inh_hid }, { 0x33, M680X_INS_SBCR, rr09_hid, inh_hid }, { 0x34, M680X_INS_ANDR, rr09_hid, inh_hid }, { 0x35, M680X_INS_ORR, rr09_hid, inh_hid }, { 0x36, M680X_INS_EORR, rr09_hid, inh_hid }, { 0x37, M680X_INS_CMPR, rr09_hid, inh_hid }, { 0x38, M680X_INS_PSHSW, inh_hid, inh_hid }, { 0x39, M680X_INS_PULSW, inh_hid, inh_hid }, { 0x3a, M680X_INS_PSHUW, inh_hid, inh_hid }, { 0x3b, M680X_INS_PULUW, inh_hid, inh_hid }, { 0x3f, M680X_INS_SWI2, inh_hid, inh_hid }, // 0x4x, Register D instructions { 0x40, M680X_INS_NEGD, inh_hid, inh_hid }, { 0x43, M680X_INS_COMD, inh_hid, inh_hid }, { 0x44, M680X_INS_LSRD, inh_hid, inh_hid }, { 0x46, M680X_INS_RORD, inh_hid, inh_hid }, { 0x47, M680X_INS_ASRD, inh_hid, inh_hid }, { 0x48, M680X_INS_LSLD, inh_hid, inh_hid }, { 0x49, M680X_INS_ROLD, inh_hid, inh_hid }, { 0x4a, M680X_INS_DECD, inh_hid, inh_hid }, { 0x4c, M680X_INS_INCD, inh_hid, inh_hid }, { 0x4d, M680X_INS_TSTD, inh_hid, inh_hid }, { 0x4f, M680X_INS_CLRD, inh_hid, inh_hid }, // 0x5x, Register W instructions { 0x53, M680X_INS_COMW, inh_hid, inh_hid }, { 0x54, M680X_INS_LSRW, inh_hid, inh_hid }, { 0x56, M680X_INS_RORW, inh_hid, inh_hid }, { 0x59, M680X_INS_ROLW, inh_hid, inh_hid }, { 0x5a, M680X_INS_DECW, inh_hid, inh_hid }, { 0x5c, M680X_INS_INCW, inh_hid, inh_hid }, { 0x5d, M680X_INS_TSTW, inh_hid, inh_hid }, { 0x5f, M680X_INS_CLRW, inh_hid, inh_hid }, // 0x8x, immediate instructionY with register D,W,Y { 0x80, M680X_INS_SUBW, imm16_hid, inh_hid }, { 0x81, M680X_INS_CMPW, imm16_hid, inh_hid }, { 0x82, M680X_INS_SBCD, imm16_hid, inh_hid }, { 0x83, M680X_INS_CMPD, imm16_hid, inh_hid }, { 0x84, M680X_INS_ANDD, imm16_hid, inh_hid }, { 0x85, M680X_INS_BITD, imm16_hid, inh_hid }, { 0x86, M680X_INS_LDW, imm16_hid, inh_hid }, { 0x88, M680X_INS_EORD, imm16_hid, inh_hid }, { 0x89, M680X_INS_ADCD, imm16_hid, inh_hid }, { 0x8a, M680X_INS_ORD, imm16_hid, inh_hid }, { 0x8b, M680X_INS_ADDW, imm16_hid, inh_hid }, { 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid }, { 0x8e, M680X_INS_LDY, imm16_hid, inh_hid }, // 0x9x, direct instructions with register D,W,Y { 0x90, M680X_INS_SUBW, dir_hid, inh_hid }, { 0x91, M680X_INS_CMPW, dir_hid, inh_hid }, { 0x92, M680X_INS_SBCD, dir_hid, inh_hid }, { 0x93, M680X_INS_CMPD, dir_hid, inh_hid }, { 0x94, M680X_INS_ANDD, dir_hid, inh_hid }, { 0x95, M680X_INS_BITD, dir_hid, inh_hid }, { 0x96, M680X_INS_LDW, dir_hid, inh_hid }, { 0x97, M680X_INS_STW, dir_hid, inh_hid }, { 0x98, M680X_INS_EORD, dir_hid, inh_hid }, { 0x99, M680X_INS_ADCD, dir_hid, inh_hid }, { 0x9a, M680X_INS_ORD, dir_hid, inh_hid }, { 0x9b, M680X_INS_ADDW, dir_hid, inh_hid }, { 0x9c, M680X_INS_CMPY, dir_hid, inh_hid }, { 0x9e, M680X_INS_LDY, dir_hid, inh_hid }, { 0x9f, M680X_INS_STY, dir_hid, inh_hid }, // 0xAx, indexed instructions with register D,W,Y { 0xa0, M680X_INS_SUBW, idx09_hid, inh_hid }, { 0xa1, M680X_INS_CMPW, idx09_hid, inh_hid }, { 0xa2, M680X_INS_SBCD, idx09_hid, inh_hid }, { 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid }, { 0xa4, M680X_INS_ANDD, idx09_hid, inh_hid }, { 0xa5, M680X_INS_BITD, idx09_hid, inh_hid }, { 0xa6, M680X_INS_LDW, idx09_hid, inh_hid }, { 0xa7, M680X_INS_STW, idx09_hid, inh_hid }, { 0xa8, M680X_INS_EORD, idx09_hid, inh_hid }, { 0xa9, M680X_INS_ADCD, idx09_hid, inh_hid }, { 0xaa, M680X_INS_ORD, idx09_hid, inh_hid }, { 0xab, M680X_INS_ADDW, idx09_hid, inh_hid }, { 0xac, M680X_INS_CMPY, idx09_hid, inh_hid }, { 0xae, M680X_INS_LDY, idx09_hid, inh_hid }, { 0xaf, M680X_INS_STY, idx09_hid, inh_hid }, // 0xBx, extended instructions with register D,W,Y { 0xb0, M680X_INS_SUBW, ext_hid, inh_hid }, { 0xb1, M680X_INS_CMPW, ext_hid, inh_hid }, { 0xb2, M680X_INS_SBCD, ext_hid, inh_hid }, { 0xb3, M680X_INS_CMPD, ext_hid, inh_hid }, { 0xb4, M680X_INS_ANDD, ext_hid, inh_hid }, { 0xb5, M680X_INS_BITD, ext_hid, inh_hid }, { 0xb6, M680X_INS_LDW, ext_hid, inh_hid }, { 0xb7, M680X_INS_STW, ext_hid, inh_hid }, { 0xb8, M680X_INS_EORD, ext_hid, inh_hid }, { 0xb9, M680X_INS_ADCD, ext_hid, inh_hid }, { 0xba, M680X_INS_ORD, ext_hid, inh_hid }, { 0xbb, M680X_INS_ADDW, ext_hid, inh_hid }, { 0xbc, M680X_INS_CMPY, ext_hid, inh_hid }, { 0xbe, M680X_INS_LDY, ext_hid, inh_hid }, { 0xbf, M680X_INS_STY, ext_hid, inh_hid }, // 0xCx, immediate instructions with register S { 0xce, M680X_INS_LDS, imm16_hid, inh_hid }, // 0xDx, direct instructions with register S,Q { 0xdc, M680X_INS_LDQ, dir_hid, inh_hid }, { 0xdd, M680X_INS_STQ, dir_hid, inh_hid }, { 0xde, M680X_INS_LDS, dir_hid, inh_hid }, { 0xdf, M680X_INS_STS, dir_hid, inh_hid }, // 0xEx, indexed instructions with register S,Q { 0xec, M680X_INS_LDQ, idx09_hid, inh_hid }, { 0xed, M680X_INS_STQ, idx09_hid, inh_hid }, { 0xee, M680X_INS_LDS, idx09_hid, inh_hid }, { 0xef, M680X_INS_STS, idx09_hid, inh_hid }, // 0xFx, extended instructions with register S,Q { 0xfc, M680X_INS_LDQ, ext_hid, inh_hid }, { 0xfd, M680X_INS_STQ, ext_hid, inh_hid }, { 0xfe, M680X_INS_LDS, ext_hid, inh_hid }, { 0xff, M680X_INS_STS, ext_hid, inh_hid }, }; // The following array has to be sorted by increasing // opcodes. Otherwise the binary_search will fail. // // HD6309 PAGE3 instructions (with prefix 0x11) static const inst_pageX g_hd6309_inst_page3_table[] = { { 0x30, M680X_INS_BAND, bitmv_hid, inh_hid }, { 0x31, M680X_INS_BIAND, bitmv_hid, inh_hid }, { 0x32, M680X_INS_BOR, bitmv_hid, inh_hid }, { 0x33, M680X_INS_BIOR, bitmv_hid, inh_hid }, { 0x34, M680X_INS_BEOR, bitmv_hid, inh_hid }, { 0x35, M680X_INS_BIEOR, bitmv_hid, inh_hid }, { 0x36, M680X_INS_LDBT, bitmv_hid, inh_hid }, { 0x37, M680X_INS_STBT, bitmv_hid, inh_hid }, { 0x38, M680X_INS_TFM, tfm_hid, inh_hid }, { 0x39, M680X_INS_TFM, tfm_hid, inh_hid }, { 0x3a, M680X_INS_TFM, tfm_hid, inh_hid }, { 0x3b, M680X_INS_TFM, tfm_hid, inh_hid }, { 0x3c, M680X_INS_BITMD, imm8_hid, inh_hid }, { 0x3d, M680X_INS_LDMD, imm8_hid, inh_hid }, { 0x3f, M680X_INS_SWI3, inh_hid, inh_hid }, // 0x4x, Register E instructions { 0x43, M680X_INS_COME, inh_hid, inh_hid }, { 0x4a, M680X_INS_DECE, inh_hid, inh_hid }, { 0x4c, M680X_INS_INCE, inh_hid, inh_hid }, { 0x4d, M680X_INS_TSTE, inh_hid, inh_hid }, { 0x4f, M680X_INS_CLRE, inh_hid, inh_hid }, // 0x5x, Register F instructions { 0x53, M680X_INS_COMF, inh_hid, inh_hid }, { 0x5a, M680X_INS_DECF, inh_hid, inh_hid }, { 0x5c, M680X_INS_INCF, inh_hid, inh_hid }, { 0x5d, M680X_INS_TSTF, inh_hid, inh_hid }, { 0x5f, M680X_INS_CLRF, inh_hid, inh_hid }, // 0x8x, immediate instructions with register U,S,E { 0x80, M680X_INS_SUBE, imm8_hid, inh_hid }, { 0x81, M680X_INS_CMPE, imm8_hid, inh_hid }, { 0x83, M680X_INS_CMPU, imm16_hid, inh_hid }, { 0x86, M680X_INS_LDE, imm8_hid, inh_hid }, { 0x8b, M680X_INS_ADDE, imm8_hid, inh_hid }, { 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid }, { 0x8d, M680X_INS_DIVD, imm8_hid, inh_hid }, { 0x8e, M680X_INS_DIVQ, imm16_hid, inh_hid }, { 0x8f, M680X_INS_MULD, imm16_hid, inh_hid }, // 0x9x, direct instructions with register U,S,E,Q { 0x90, M680X_INS_SUBE, dir_hid, inh_hid }, { 0x91, M680X_INS_CMPE, dir_hid, inh_hid }, { 0x93, M680X_INS_CMPU, dir_hid, inh_hid }, { 0x96, M680X_INS_LDE, dir_hid, inh_hid }, { 0x97, M680X_INS_STE, dir_hid, inh_hid }, { 0x9b, M680X_INS_ADDE, dir_hid, inh_hid }, { 0x9c, M680X_INS_CMPS, dir_hid, inh_hid }, { 0x9d, M680X_INS_DIVD, dir_hid, inh_hid }, { 0x9e, M680X_INS_DIVQ, dir_hid, inh_hid }, { 0x9f, M680X_INS_MULD, dir_hid, inh_hid }, // 0xAx, indexed instructions with register U,S,D,Q { 0xa0, M680X_INS_SUBE, idx09_hid, inh_hid }, { 0xa1, M680X_INS_CMPE, idx09_hid, inh_hid }, { 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid }, { 0xa6, M680X_INS_LDE, idx09_hid, inh_hid }, { 0xa7, M680X_INS_STE, idx09_hid, inh_hid }, { 0xab, M680X_INS_ADDE, idx09_hid, inh_hid }, { 0xac, M680X_INS_CMPS, idx09_hid, inh_hid }, { 0xad, M680X_INS_DIVD, idx09_hid, inh_hid }, { 0xae, M680X_INS_DIVQ, idx09_hid, inh_hid }, { 0xaf, M680X_INS_MULD, idx09_hid, inh_hid }, // 0xBx, extended instructions with register U,S,D,Q { 0xb0, M680X_INS_SUBE, ext_hid, inh_hid }, { 0xb1, M680X_INS_CMPE, ext_hid, inh_hid }, { 0xb3, M680X_INS_CMPU, ext_hid, inh_hid }, { 0xb6, M680X_INS_LDE, ext_hid, inh_hid }, { 0xb7, M680X_INS_STE, ext_hid, inh_hid }, { 0xbb, M680X_INS_ADDE, ext_hid, inh_hid }, { 0xbc, M680X_INS_CMPS, ext_hid, inh_hid }, { 0xbd, M680X_INS_DIVD, ext_hid, inh_hid }, { 0xbe, M680X_INS_DIVQ, ext_hid, inh_hid }, { 0xbf, M680X_INS_MULD, ext_hid, inh_hid }, // 0xCx, immediate instructions with register F { 0xc0, M680X_INS_SUBF, imm8_hid, inh_hid }, { 0xc1, M680X_INS_CMPF, imm8_hid, inh_hid }, { 0xc6, M680X_INS_LDF, imm8_hid, inh_hid }, { 0xcb, M680X_INS_ADDF, imm8_hid, inh_hid }, // 0xDx, direct instructions with register F { 0xd0, M680X_INS_SUBF, dir_hid, inh_hid }, { 0xd1, M680X_INS_CMPF, dir_hid, inh_hid }, { 0xd6, M680X_INS_LDF, dir_hid, inh_hid }, { 0xd7, M680X_INS_STF, dir_hid, inh_hid }, { 0xdb, M680X_INS_ADDF, dir_hid, inh_hid }, // 0xEx, indexed instructions with register F { 0xe0, M680X_INS_SUBF, idx09_hid, inh_hid }, { 0xe1, M680X_INS_CMPF, idx09_hid, inh_hid }, { 0xe6, M680X_INS_LDF, idx09_hid, inh_hid }, { 0xe7, M680X_INS_STF, idx09_hid, inh_hid }, { 0xeb, M680X_INS_ADDF, idx09_hid, inh_hid }, // 0xFx, extended instructions with register F { 0xf0, M680X_INS_SUBF, ext_hid, inh_hid }, { 0xf1, M680X_INS_CMPF, ext_hid, inh_hid }, { 0xf6, M680X_INS_LDF, ext_hid, inh_hid }, { 0xf7, M680X_INS_STF, ext_hid, inh_hid }, { 0xfb, M680X_INS_ADDF, ext_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/insn_props.inc000064400000000000000000000462210072674642500205740ustar 00000000000000 // These temporary defines keep the following table short and handy. #define NOG M680X_GRP_INVALID #define NOR M680X_REG_INVALID static const insn_props g_insn_props[] = { { NOG, uuuu, NOR, NOR, false, false }, // INVLD { NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // ABA { NOG, rmmm, M680X_REG_B, M680X_REG_X, false, false }, // ABX { NOG, rmmm, M680X_REG_B, M680X_REG_Y, false, false }, // ABY { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADC { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADCA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADCB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADCD { NOG, rmmm, NOR, NOR, true, false }, // ADCR { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADD { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADDA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADDB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADDD { NOG, mrrr, M680X_REG_E, NOR, true, false }, // ADDE { NOG, mrrr, M680X_REG_F, NOR, true, false }, // ADDF { NOG, rmmm, NOR, NOR, true, false }, // ADDR { NOG, mrrr, M680X_REG_W, NOR, true, false }, // ADDW { NOG, rmmm, NOR, NOR, true, false }, // AIM { NOG, mrrr, M680X_REG_S, NOR, false, false }, // AIS { NOG, mrrr, M680X_REG_HX, NOR, false, false }, // AIX { NOG, mrrr, M680X_REG_A, NOR, true, false }, // AND { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ANDA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ANDB { NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ANDCC { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ANDD { NOG, rmmm, NOR, NOR, true, false }, // ANDR { NOG, mrrr, NOR, NOR, true, false }, // ASL { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASLA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASLB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASLD { NOG, mrrr, NOR, NOR, true, false }, // ASR { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASRA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASRB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASRD { NOG, mrrr, M680X_REG_X, NOR, true, false }, // ASRX { NOG, mrrr, NOR, NOR, false, false }, // BAND { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCC { NOG, mrrr, NOR, NOR, true, false }, // BCLR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCS { NOG, mrrr, NOR, NOR, false, false }, // BEOR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BEQ { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGE { NOG, uuuu, NOR, NOR, false, false }, // BGND { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGT { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCC { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCS { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHI { NOG, mrrr, NOR, NOR, false, false }, // BIAND { NOG, mrrr, NOR, NOR, false, false }, // BIEOR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIH { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIL { NOG, mrrr, NOR, NOR, false, false }, // BIOR { NOG, rrrr, M680X_REG_A, NOR, true, false }, // BIT { NOG, rrrr, M680X_REG_A, NOR, true, false }, // BITA { NOG, rrrr, M680X_REG_B, NOR, true, false }, // BITB { NOG, rrrr, M680X_REG_D, NOR, true, false }, // BITD { NOG, rrrr, M680X_REG_MD, NOR, true, false }, // BITMD { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLE { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLS { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLT { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMC { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMI { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMS { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BNE { NOG, mrrr, NOR, NOR, false, false }, // BOR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BPL { M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRCLR { M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRSET { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRA { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRN never branches { NOG, mrrr, NOR, NOR, true, false }, // BSET { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // BSR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVC { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVS { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // CALL { NOG, rrrr, M680X_REG_B, M680X_REG_A, true, false }, // CBA { M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQ { M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQA { M680X_GRP_JUMP, rruu, M680X_REG_X, NOR, false, false }, // CBEQX { NOG, uuuu, NOR, NOR, true, false }, // CLC { NOG, uuuu, NOR, NOR, true, false }, // CLI { NOG, wrrr, NOR, NOR, true, false }, // CLR { NOG, wrrr, M680X_REG_A, NOR, true, false }, // CLRA { NOG, wrrr, M680X_REG_B, NOR, true, false }, // CLRB { NOG, wrrr, M680X_REG_D, NOR, true, false }, // CLRD { NOG, wrrr, M680X_REG_E, NOR, true, false }, // CLRE { NOG, wrrr, M680X_REG_F, NOR, true, false }, // CLRF { NOG, wrrr, M680X_REG_H, NOR, true, false }, // CLRH { NOG, wrrr, M680X_REG_W, NOR, true, false }, // CLRW { NOG, wrrr, M680X_REG_X, NOR, true, false }, // CLRX { NOG, uuuu, NOR, NOR, true, false }, // CLV { NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMP { NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMPA { NOG, rrrr, M680X_REG_B, NOR, true, false }, // CMPB { NOG, rrrr, M680X_REG_D, NOR, true, false }, // CMPD { NOG, rrrr, M680X_REG_E, NOR, true, false }, // CMPE { NOG, rrrr, M680X_REG_F, NOR, true, false }, // CMPF { NOG, rrrr, NOR, NOR, true, false }, // CMPR { NOG, rrrr, M680X_REG_S, NOR, true, false }, // CMPS { NOG, rrrr, M680X_REG_U, NOR, true, false }, // CMPU { NOG, rrrr, M680X_REG_W, NOR, true, false }, // CMPW { NOG, rrrr, M680X_REG_X, NOR, true, false }, // CMPX { NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CMPY { NOG, mrrr, NOR, NOR, true, false }, // COM { NOG, mrrr, M680X_REG_A, NOR, true, false }, // COMA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // COMB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // COMD { NOG, mrrr, M680X_REG_E, NOR, true, false }, // COME { NOG, mrrr, M680X_REG_F, NOR, true, false }, // COMF { NOG, mrrr, M680X_REG_W, NOR, true, false }, // COMW { NOG, mrrr, M680X_REG_X, NOR, true, false }, // COMX { NOG, rrrr, M680X_REG_D, NOR, true, false }, // CPD { NOG, rrrr, M680X_REG_HX, NOR, true, false }, // CPHX { NOG, rrrr, M680X_REG_S, NOR, true, false }, // CPS { NOG, rrrr, M680X_REG_X, NOR, true, false }, // CPX { NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CPY { NOG, mrrr, NOR, NOR, true, true }, // CWAI { NOG, mrrr, NOR, NOR, true, true }, // DAA { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBEQ { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNE { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNZ { M680X_GRP_JUMP, muuu, M680X_REG_A, NOR, false, false }, // DBNZA { M680X_GRP_JUMP, muuu, M680X_REG_X, NOR, false, false }, // DBNZX { NOG, mrrr, NOR, NOR, true, false }, // DEC { NOG, mrrr, M680X_REG_A, NOR, true, false }, // DECA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // DECB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // DECD { NOG, mrrr, M680X_REG_E, NOR, true, false }, // DECE { NOG, mrrr, M680X_REG_F, NOR, true, false }, // DECF { NOG, mrrr, M680X_REG_W, NOR, true, false }, // DECW { NOG, mrrr, M680X_REG_X, NOR, true, false }, // DECX { NOG, mrrr, M680X_REG_S, NOR, false, false }, // DES { NOG, mrrr, M680X_REG_X, NOR, true, false }, // DEX { NOG, mrrr, M680X_REG_Y, NOR, true, false }, // DEY { NOG, mmrr, NOR, NOR, true, true }, // DIV { NOG, mrrr, M680X_REG_D, NOR, true, false }, // DIVD { NOG, mrrr, M680X_REG_Q, NOR, true, false }, // DIVQ { NOG, mmrr, NOR, NOR, true, true }, // EDIV { NOG, mmrr, NOR, NOR, true, true }, // EDIVS { NOG, rmmm, NOR, NOR, true, false }, // EIM { NOG, mrrr, NOR, NOR, true, true }, // EMACS { NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMAXD { NOG, mrrr, NOR, NOR, true, true }, // EMAXM { NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMIND { NOG, mrrr, NOR, NOR, true, true }, // EMINM { NOG, mmrr, NOR, NOR, true, true }, // EMUL { NOG, mmrr, NOR, NOR, true, true }, // EMULS { NOG, mrrr, M680X_REG_A, NOR, true, false }, // EOR { NOG, mrrr, M680X_REG_A, NOR, true, false }, // EORA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // EORB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // EORD { NOG, rmmm, NOR, NOR, true, false }, // EORR { NOG, rmmm, NOR, NOR, true, true }, // ETBL { NOG, mmmm, NOR, NOR, false, false }, // EXG { NOG, mmmm, NOR, NOR, true, true }, // FDIV { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBEQ { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBNE { NOG, mmmm, NOR, NOR, true, true }, // IDIV { NOG, mmmm, NOR, NOR, true, true }, // IDIVS { NOG, uuuu, NOR, NOR, false, false }, // ILLGL { NOG, mrrr, NOR, NOR, true, false }, // INC { NOG, mrrr, M680X_REG_A, NOR, true, false }, // INCA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // INCB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // INCD { NOG, mrrr, M680X_REG_E, NOR, true, false }, // INCE { NOG, mrrr, M680X_REG_F, NOR, true, false }, // INCF { NOG, mrrr, M680X_REG_W, NOR, true, false }, // INCW { NOG, mrrr, M680X_REG_X, NOR, true, false }, // INCX { NOG, mrrr, M680X_REG_S, NOR, false, false }, // INS { NOG, mrrr, M680X_REG_X, NOR, true, false }, // INX { NOG, mrrr, M680X_REG_Y, NOR, true, false }, // INY { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // JMP { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // JSR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCC { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCS { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBEQ { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGE { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGT { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBHI { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLE { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLS { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLT { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBMI { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBNE { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBPL { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRA { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRN never branches { M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // LBSR { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVC { M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVS { NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDA { NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDAA { NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDAB { NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDB { NOG, mrrr, NOR, NOR, false, false }, // LDBT { NOG, wrrr, M680X_REG_D, NOR, true, false }, // LDD { NOG, wrrr, M680X_REG_E, NOR, true, false }, // LDE { NOG, wrrr, M680X_REG_F, NOR, true, false }, // LDF { NOG, wrrr, M680X_REG_HX, NOR, true, false }, // LDHX { NOG, mrrr, M680X_REG_MD, NOR, false, false }, // LDMD { NOG, wrrr, M680X_REG_Q, NOR, true, false }, // LDQ { NOG, wrrr, M680X_REG_S, NOR, true, false }, // LDS { NOG, wrrr, M680X_REG_U, NOR, true, false }, // LDU { NOG, wrrr, M680X_REG_W, NOR, true, false }, // LDW { NOG, wrrr, M680X_REG_X, NOR, true, false }, // LDX { NOG, wrrr, M680X_REG_Y, NOR, true, false }, // LDY { NOG, wrrr, M680X_REG_S, NOR, false, false }, // LEAS { NOG, wrrr, M680X_REG_U, NOR, false, false }, // LEAU { NOG, wrrr, M680X_REG_X, NOR, false, false }, // LEAX { NOG, wrrr, M680X_REG_Y, NOR, false, false }, // LEAY { NOG, mrrr, NOR, NOR, true, false }, // LSL { NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSLA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSLB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSLD { NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSLX { NOG, mrrr, NOR, NOR, true, false }, // LSR { NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSRA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSRB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSRD { NOG, mrrr, M680X_REG_W, NOR, true, false }, // LSRW { NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSRX { NOG, mrrr, M680X_REG_A, NOR, true, false }, // MAXA { NOG, mrrr, NOR, NOR, true, true }, // MAXM { NOG, mmrr, NOR, NOR, true, true }, // MEM { NOG, mrrr, M680X_REG_A, NOR, true, false }, // MINA { NOG, mrrr, NOR, NOR, true, true }, // MINM { NOG, rwww, NOR, NOR, true, false }, // MOV { NOG, rwww, NOR, NOR, false, false }, // MOVB { NOG, rwww, NOR, NOR, false, false }, // MOVW { NOG, mmmm, NOR, NOR, true, true }, // MUL { NOG, mwrr, M680X_REG_D, NOR, true, true }, // MULD { NOG, mrrr, NOR, NOR, true, false }, // NEG { NOG, mrrr, M680X_REG_A, NOR, true, false }, // NEGA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // NEGB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // NEGD { NOG, mrrr, M680X_REG_X, NOR, true, false }, // NEGX { NOG, uuuu, NOR, NOR, false, false }, // NOP { NOG, mrrr, M680X_REG_A, NOR, true, false }, // NSA { NOG, rmmm, NOR, NOR, true, false }, // OIM { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORA { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORAA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORAB { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORB { NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ORCC { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ORD { NOG, rmmm, NOR, NOR, true, false }, // ORR { NOG, rmmm, M680X_REG_A, NOR, false, true }, // PSHA { NOG, rmmm, M680X_REG_B, NOR, false, true }, // PSHB { NOG, rmmm, M680X_REG_CC, NOR, false, true }, // PSHC { NOG, rmmm, M680X_REG_D, NOR, false, true }, // PSHD { NOG, rmmm, M680X_REG_H, NOR, false, true }, // PSHH { NOG, mrrr, M680X_REG_S, NOR, false, false }, // PSHS { NOG, mrrr, M680X_REG_S, M680X_REG_W, false, false }, // PSHSW { NOG, mrrr, M680X_REG_U, NOR, false, false }, // PSHU { NOG, mrrr, M680X_REG_U, M680X_REG_W, false, false }, // PSHUW { NOG, rmmm, M680X_REG_X, NOR, false, true }, // PSHX { NOG, rmmm, M680X_REG_Y, NOR, false, true }, // PSHY { NOG, wmmm, M680X_REG_A, NOR, false, true }, // PULA { NOG, wmmm, M680X_REG_B, NOR, false, true }, // PULB { NOG, wmmm, M680X_REG_CC, NOR, false, true }, // PULC { NOG, wmmm, M680X_REG_D, NOR, false, true }, // PULD { NOG, wmmm, M680X_REG_H, NOR, false, true }, // PULH { NOG, mwww, M680X_REG_S, NOR, false, false }, // PULS { NOG, mwww, M680X_REG_S, M680X_REG_W, false, false }, // PULSW { NOG, mwww, M680X_REG_U, NOR, false, false }, // PULU { NOG, mwww, M680X_REG_U, M680X_REG_W, false, false }, // PULUW { NOG, wmmm, M680X_REG_X, NOR, false, true }, // PULX { NOG, wmmm, M680X_REG_Y, NOR, false, true }, // PULY { NOG, mmrr, NOR, NOR, true, true }, // REV { NOG, mmmm, NOR, NOR, true, true }, // REVW { NOG, mrrr, NOR, NOR, true, false }, // ROL { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ROLA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ROLB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ROLD { NOG, mrrr, M680X_REG_W, NOR, true, false }, // ROLW { NOG, mrrr, M680X_REG_X, NOR, true, false }, // ROLX { NOG, mrrr, NOR, NOR, true, false }, // ROR { NOG, mrrr, M680X_REG_A, NOR, true, false }, // RORA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // RORB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // RORD { NOG, mrrr, M680X_REG_W, NOR, true, false }, // RORW { NOG, mrrr, M680X_REG_X, NOR, true, false }, // RORX { NOG, wrrr, M680X_REG_S, NOR, false, false }, // RSP { M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTC { M680X_GRP_IRET, mwww, NOR, NOR, false, true }, // RTI { M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTS { NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // SBA { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBC { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBCA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // SBCB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // SBCD { NOG, rmmm, NOR, NOR, true, false }, // SBCR { NOG, uuuu, NOR, NOR, true, false }, // SEC { NOG, uuuu, NOR, NOR, true, false }, // SEI { NOG, uuuu, NOR, NOR, true, false }, // SEV { NOG, wrrr, NOR, NOR, true, true }, // SEX { NOG, rwww, M680X_REG_W, NOR, true, true }, // SEXW { NOG, uuuu, NOR, NOR, false, false }, // SLP { NOG, rwww, M680X_REG_A, NOR, true, false }, // STA { NOG, rwww, M680X_REG_A, NOR, true, false }, // STAA { NOG, rwww, M680X_REG_B, NOR, true, false }, // STAB { NOG, rwww, M680X_REG_B, NOR, true, false }, // STB { NOG, rrrm, NOR, NOR, false, false }, // STBT { NOG, rwww, M680X_REG_D, NOR, true, false }, // STD { NOG, rwww, M680X_REG_E, NOR, true, false }, // STE { NOG, rwww, M680X_REG_F, NOR, true, false }, // STF { NOG, uuuu, NOR, NOR, false, false }, // STOP { NOG, rwww, M680X_REG_HX, NOR, true, false }, // STHX { NOG, rwww, M680X_REG_Q, NOR, true, false }, // STQ { NOG, rwww, M680X_REG_S, NOR, true, false }, // STS { NOG, rwww, M680X_REG_U, NOR, true, false }, // STU { NOG, rwww, M680X_REG_W, NOR, true, false }, // STW { NOG, rwww, M680X_REG_X, NOR, true, false }, // STX { NOG, rwww, M680X_REG_Y, NOR, true, false }, // STY { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUB { NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUBA { NOG, mrrr, M680X_REG_B, NOR, true, false }, // SUBB { NOG, mrrr, M680X_REG_D, NOR, true, false }, // SUBD { NOG, mrrr, M680X_REG_E, NOR, true, false }, // SUBE { NOG, mrrr, M680X_REG_F, NOR, true, false }, // SUBF { NOG, rmmm, NOR, NOR, true, false }, // SUBR { NOG, mrrr, M680X_REG_W, NOR, true, false }, // SUBW { M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI { M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI2 { M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI3 { NOG, uuuu, NOR, NOR, false, false }, // SYNC { NOG, rwww, M680X_REG_A, M680X_REG_B, true, false }, // TAB { NOG, rwww, M680X_REG_A, M680X_REG_CC, false, false }, // TAP { NOG, rwww, M680X_REG_A, M680X_REG_X, false, false }, // TAX { NOG, rwww, M680X_REG_B, M680X_REG_A, true, false }, // TBA { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBEQ { NOG, rmmm, NOR, NOR, true, true }, // TBL { M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBNE { NOG, uuuu, NOR, NOR, false, false }, // TEST { NOG, rwww, NOR, NOR, false, false }, // TFM { NOG, rwww, NOR, NOR, false, false }, // TFR { NOG, rrrr, NOR, NOR, true, false }, // TIM { NOG, rwww, M680X_REG_CC, M680X_REG_A, false, false }, // TPA { NOG, rrrr, NOR, NOR, true, false }, // TST { NOG, rrrr, M680X_REG_A, NOR, true, false }, // TSTA { NOG, rrrr, M680X_REG_B, NOR, true, false }, // TSTB { NOG, rrrr, M680X_REG_D, NOR, true, false }, // TSTD { NOG, rrrr, M680X_REG_E, NOR, true, false }, // TSTE { NOG, rrrr, M680X_REG_F, NOR, true, false }, // TSTF { NOG, rrrr, M680X_REG_W, NOR, true, false }, // TSTW { NOG, rrrr, M680X_REG_X, NOR, true, false }, // TSTX { NOG, rwww, M680X_REG_S, M680X_REG_HX, false, false }, // TSX { NOG, rwww, M680X_REG_S, M680X_REG_Y, false, false }, // TSY { NOG, rwww, M680X_REG_X, M680X_REG_A, false, false }, // TXA { NOG, rwww, M680X_REG_HX, M680X_REG_S, false, false }, // TXS { NOG, rwww, M680X_REG_Y, M680X_REG_S, false, false }, // TYS { NOG, mrrr, NOR, NOR, true, true }, // WAI { NOG, uuuu, NOR, NOR, true, false }, // WAIT { NOG, uuuu, NOR, NOR, true, true }, // WAV { NOG, uuuu, NOR, NOR, true, true }, // WAVR { NOG, mmmm, M680X_REG_D, M680X_REG_X, false, false }, // XGDX { NOG, mmmm, M680X_REG_D, M680X_REG_Y, false, false }, // XGDY }; #undef NOR #undef NOG capstone-sys-0.15.0/capstone/arch/M680X/m6800.inc000064400000000000000000000252370072674642500171600ustar 00000000000000 // M6800/2 instructions static const inst_page1 g_m6800_inst_page1_table[256] = { // 0x0x, inherent instructions { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_NOP, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_TAP, inh_hid, inh_hid }, { M680X_INS_TPA, inh_hid, inh_hid }, { M680X_INS_INX, inh_hid, inh_hid }, { M680X_INS_DEX, inh_hid, inh_hid }, { M680X_INS_CLV, inh_hid, inh_hid }, { M680X_INS_SEV, inh_hid, inh_hid }, { M680X_INS_CLC, inh_hid, inh_hid }, { M680X_INS_SEC, inh_hid, inh_hid }, { M680X_INS_CLI, inh_hid, inh_hid }, { M680X_INS_SEI, inh_hid, inh_hid }, // 0x1x, inherent instructions { M680X_INS_SBA, inh_hid, inh_hid }, { M680X_INS_CBA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_TAB, inh_hid, inh_hid }, { M680X_INS_TBA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_DAA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ABA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, // 0x2x, relative branch instructions { M680X_INS_BRA, rel8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_BHI, rel8_hid, inh_hid }, { M680X_INS_BLS, rel8_hid, inh_hid }, { M680X_INS_BCC, rel8_hid, inh_hid }, { M680X_INS_BCS, rel8_hid, inh_hid }, { M680X_INS_BNE, rel8_hid, inh_hid }, { M680X_INS_BEQ, rel8_hid, inh_hid }, { M680X_INS_BVC, rel8_hid, inh_hid }, { M680X_INS_BVS, rel8_hid, inh_hid }, { M680X_INS_BPL, rel8_hid, inh_hid }, { M680X_INS_BMI, rel8_hid, inh_hid }, { M680X_INS_BGE, rel8_hid, inh_hid }, { M680X_INS_BLT, rel8_hid, inh_hid }, { M680X_INS_BGT, rel8_hid, inh_hid }, { M680X_INS_BLE, rel8_hid, inh_hid }, // 0x3x, inherent instructions { M680X_INS_TSX, inh_hid, inh_hid }, { M680X_INS_INS, inh_hid, inh_hid }, { M680X_INS_PULA, inh_hid, inh_hid }, { M680X_INS_PULB, inh_hid, inh_hid }, { M680X_INS_DES, inh_hid, inh_hid }, { M680X_INS_TXS, inh_hid, inh_hid }, { M680X_INS_PSHA, inh_hid, inh_hid }, { M680X_INS_PSHB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RTS, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RTI, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_WAI, inh_hid, inh_hid }, { M680X_INS_SWI, inh_hid, inh_hid }, // 0x4x, Register A instructions { M680X_INS_NEGA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COMA, inh_hid, inh_hid }, { M680X_INS_LSRA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RORA, inh_hid, inh_hid }, { M680X_INS_ASRA, inh_hid, inh_hid }, { M680X_INS_ASLA, inh_hid, inh_hid }, { M680X_INS_ROLA, inh_hid, inh_hid }, { M680X_INS_DECA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INCA, inh_hid, inh_hid }, { M680X_INS_TSTA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLRA, inh_hid, inh_hid }, // 0x5x, Register B instructions { M680X_INS_NEGB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COMB, inh_hid, inh_hid }, { M680X_INS_LSRB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RORB, inh_hid, inh_hid }, { M680X_INS_ASRB, inh_hid, inh_hid }, { M680X_INS_ASLB, inh_hid, inh_hid }, { M680X_INS_ROLB, inh_hid, inh_hid }, { M680X_INS_DECB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INCB, inh_hid, inh_hid }, { M680X_INS_TSTB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLRB, inh_hid, inh_hid }, // 0x6x, indexed instructions { M680X_INS_NEG, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, idxX_hid, inh_hid }, { M680X_INS_LSR, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, idxX_hid, inh_hid }, { M680X_INS_ASR, idxX_hid, inh_hid }, { M680X_INS_ASL, idxX_hid, inh_hid }, { M680X_INS_ROL, idxX_hid, inh_hid }, { M680X_INS_DEC, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, idxX_hid, inh_hid }, { M680X_INS_TST, idxX_hid, inh_hid }, { M680X_INS_JMP, idxX_hid, inh_hid }, { M680X_INS_CLR, idxX_hid, inh_hid }, // 0x7x, extended instructions { M680X_INS_NEG, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, ext_hid, inh_hid }, { M680X_INS_LSR, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, ext_hid, inh_hid }, { M680X_INS_ASR, ext_hid, inh_hid }, { M680X_INS_ASL, ext_hid, inh_hid }, { M680X_INS_ROL, ext_hid, inh_hid }, { M680X_INS_DEC, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, ext_hid, inh_hid }, { M680X_INS_TST, ext_hid, inh_hid }, { M680X_INS_JMP, ext_hid, inh_hid }, { M680X_INS_CLR, ext_hid, inh_hid }, // 0x8x, immediate instructions with Register A,X,S { M680X_INS_SUBA, imm8_hid, inh_hid }, { M680X_INS_CMPA, imm8_hid, inh_hid }, { M680X_INS_SBCA, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDA, imm8_hid, inh_hid }, { M680X_INS_BITA, imm8_hid, inh_hid }, { M680X_INS_LDAA, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_EORA, imm8_hid, inh_hid }, { M680X_INS_ADCA, imm8_hid, inh_hid }, { M680X_INS_ORAA, imm8_hid, inh_hid }, { M680X_INS_ADDA, imm8_hid, inh_hid }, { M680X_INS_CPX, imm16_hid, inh_hid }, { M680X_INS_BSR, rel8_hid, inh_hid }, { M680X_INS_LDS, imm16_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, // 0x9x, direct instructions with register A,X,S { M680X_INS_SUBA, dir_hid, inh_hid }, { M680X_INS_CMPA, dir_hid, inh_hid }, { M680X_INS_SBCA, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDA, dir_hid, inh_hid }, { M680X_INS_BITA, dir_hid, inh_hid }, { M680X_INS_LDAA, dir_hid, inh_hid }, { M680X_INS_STAA, dir_hid, inh_hid }, { M680X_INS_EORA, dir_hid, inh_hid }, { M680X_INS_ADCA, dir_hid, inh_hid }, { M680X_INS_ORAA, dir_hid, inh_hid }, { M680X_INS_ADDA, dir_hid, inh_hid }, { M680X_INS_CPX, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LDS, dir_hid, inh_hid }, { M680X_INS_STS, dir_hid, inh_hid }, // 0xAx, indexed instructions with Register A,X { M680X_INS_SUBA, idxX_hid, inh_hid }, { M680X_INS_CMPA, idxX_hid, inh_hid }, { M680X_INS_SBCA, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDA, idxX_hid, inh_hid }, { M680X_INS_BITA, idxX_hid, inh_hid }, { M680X_INS_LDAA, idxX_hid, inh_hid }, { M680X_INS_STAA, idxX_hid, inh_hid }, { M680X_INS_EORA, idxX_hid, inh_hid }, { M680X_INS_ADCA, idxX_hid, inh_hid }, { M680X_INS_ORAA, idxX_hid, inh_hid }, { M680X_INS_ADDA, idxX_hid, inh_hid }, { M680X_INS_CPX, idxX_hid, inh_hid }, { M680X_INS_JSR, idxX_hid, inh_hid }, { M680X_INS_LDS, idxX_hid, inh_hid }, { M680X_INS_STS, idxX_hid, inh_hid }, // 0xBx, extended instructions with register A,X,S { M680X_INS_SUBA, ext_hid, inh_hid }, { M680X_INS_CMPA, ext_hid, inh_hid }, { M680X_INS_SBCA, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDA, ext_hid, inh_hid }, { M680X_INS_BITA, ext_hid, inh_hid }, { M680X_INS_LDAA, ext_hid, inh_hid }, { M680X_INS_STAA, ext_hid, inh_hid }, { M680X_INS_EORA, ext_hid, inh_hid }, { M680X_INS_ADCA, ext_hid, inh_hid }, { M680X_INS_ORAA, ext_hid, inh_hid }, { M680X_INS_ADDA, ext_hid, inh_hid }, { M680X_INS_CPX, ext_hid, inh_hid }, { M680X_INS_JSR, ext_hid, inh_hid }, { M680X_INS_LDS, ext_hid, inh_hid }, { M680X_INS_STS, ext_hid, inh_hid }, // 0xCx, immediate instructions with register B,X { M680X_INS_SUBB, imm8_hid, inh_hid }, { M680X_INS_CMPB, imm8_hid, inh_hid }, { M680X_INS_SBCB, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDB, imm8_hid, inh_hid }, { M680X_INS_BITB, imm8_hid, inh_hid }, { M680X_INS_LDAB, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_EORB, imm8_hid, inh_hid }, { M680X_INS_ADCB, imm8_hid, inh_hid }, { M680X_INS_ORAB, imm8_hid, inh_hid }, { M680X_INS_ADDB, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LDX, imm16_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, // 0xDx direct instructions with register B,X { M680X_INS_SUBB, dir_hid, inh_hid }, { M680X_INS_CMPB, dir_hid, inh_hid }, { M680X_INS_SBCB, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDB, dir_hid, inh_hid }, { M680X_INS_BITB, dir_hid, inh_hid }, { M680X_INS_LDAB, dir_hid, inh_hid }, { M680X_INS_STAB, dir_hid, inh_hid }, { M680X_INS_EORB, dir_hid, inh_hid }, { M680X_INS_ADCB, dir_hid, inh_hid }, { M680X_INS_ORAB, dir_hid, inh_hid }, { M680X_INS_ADDB, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LDX, dir_hid, inh_hid }, { M680X_INS_STX, dir_hid, inh_hid }, // 0xEx, indexed instruction with register B,X { M680X_INS_SUBB, idxX_hid, inh_hid }, { M680X_INS_CMPB, idxX_hid, inh_hid }, { M680X_INS_SBCB, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDB, idxX_hid, inh_hid }, { M680X_INS_BITB, idxX_hid, inh_hid }, { M680X_INS_LDAB, idxX_hid, inh_hid }, { M680X_INS_STAB, idxX_hid, inh_hid }, { M680X_INS_EORB, idxX_hid, inh_hid }, { M680X_INS_ADCB, idxX_hid, inh_hid }, { M680X_INS_ORAB, idxX_hid, inh_hid }, { M680X_INS_ADDB, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LDX, idxX_hid, inh_hid }, { M680X_INS_STX, idxX_hid, inh_hid }, // 0xFx, extended instructions with register B,U { M680X_INS_SUBB, ext_hid, inh_hid }, { M680X_INS_CMPB, ext_hid, inh_hid }, { M680X_INS_SBCB, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDB, ext_hid, inh_hid }, { M680X_INS_BITB, ext_hid, inh_hid }, { M680X_INS_LDAB, ext_hid, inh_hid }, { M680X_INS_STAB, ext_hid, inh_hid }, { M680X_INS_EORB, ext_hid, inh_hid }, { M680X_INS_ADCB, ext_hid, inh_hid }, { M680X_INS_ORAB, ext_hid, inh_hid }, { M680X_INS_ADDB, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LDX, ext_hid, inh_hid }, { M680X_INS_STX, ext_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/m6801.inc000064400000000000000000000031400072674642500171460ustar 00000000000000 // Additional instructions only supported on M6801/3 static const inst_pageX g_m6801_inst_overlay_table[] = { // 0x0x, inherent instructions { 0x04, M680X_INS_LSRD, inh_hid, inh_hid }, { 0x05, M680X_INS_ASLD, inh_hid, inh_hid }, // 0x2x, relative branch instructions { 0x21, M680X_INS_BRN, rel8_hid, inh_hid }, // 0x3x, inherent instructions { 0x38, M680X_INS_PULX, inh_hid, inh_hid }, { 0x3A, M680X_INS_ABX, inh_hid, inh_hid }, { 0x3C, M680X_INS_PSHX, inh_hid, inh_hid }, { 0x3D, M680X_INS_MUL, inh_hid, inh_hid }, // 0x8x, immediate instructions with Register D { 0x83, M680X_INS_SUBD, imm16_hid, inh_hid }, // 0x9x, direct instructions with register D { 0x93, M680X_INS_SUBD, dir_hid, inh_hid }, { 0x9D, M680X_INS_JSR, dir_hid, inh_hid }, // 0xAx, indexed instructions with Register D { 0xA3, M680X_INS_SUBD, idxX_hid, inh_hid }, // 0xBx, extended instructions with register D { 0xB3, M680X_INS_SUBD, ext_hid, inh_hid }, // 0xCx, immediate instructions with register D { 0xC3, M680X_INS_ADDD, imm16_hid, inh_hid }, { 0xCC, M680X_INS_LDD, imm16_hid, inh_hid }, // 0xDx direct instructions with register D { 0xD3, M680X_INS_ADDD, dir_hid, inh_hid }, { 0xDC, M680X_INS_LDD, dir_hid, inh_hid }, { 0xDD, M680X_INS_STD, dir_hid, inh_hid }, // 0xEx, indexed instruction with register D { 0xE3, M680X_INS_ADDD, idxX_hid, inh_hid }, { 0xEC, M680X_INS_LDD, idxX_hid, inh_hid }, { 0xED, M680X_INS_STD, idxX_hid, inh_hid }, // 0xFx, extended instructions with register D { 0xF3, M680X_INS_ADDD, ext_hid, inh_hid }, { 0xFC, M680X_INS_LDD, ext_hid, inh_hid }, { 0xFD, M680X_INS_STD, ext_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/m6805.inc000064400000000000000000000253720072674642500171650ustar 00000000000000 // M68HC05 instructions static const inst_page1 g_m6805_inst_page1_table[256] = { // 0x0x, bit manipulation instructions { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, { M680X_INS_BRSET, opidxdr_hid, inh_hid }, { M680X_INS_BRCLR, opidxdr_hid, inh_hid }, // 0x1x, bit set/clear instructions { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, { M680X_INS_BCLR, opidx_hid, dir_hid }, { M680X_INS_BSET, opidx_hid, dir_hid }, // 0x2x, relative branch instructions { M680X_INS_BRA, rel8_hid, inh_hid }, { M680X_INS_BRN, rel8_hid, inh_hid }, { M680X_INS_BHI, rel8_hid, inh_hid }, { M680X_INS_BLS, rel8_hid, inh_hid }, { M680X_INS_BCC, rel8_hid, inh_hid }, { M680X_INS_BCS, rel8_hid, inh_hid }, { M680X_INS_BNE, rel8_hid, inh_hid }, { M680X_INS_BEQ, rel8_hid, inh_hid }, { M680X_INS_BHCC, rel8_hid, inh_hid }, { M680X_INS_BHCS, rel8_hid, inh_hid }, { M680X_INS_BPL, rel8_hid, inh_hid }, { M680X_INS_BMI, rel8_hid, inh_hid }, { M680X_INS_BMC, rel8_hid, inh_hid }, { M680X_INS_BMS, rel8_hid, inh_hid }, { M680X_INS_BIL, rel8_hid, inh_hid }, { M680X_INS_BIH, rel8_hid, inh_hid }, // 0x3x, direct instructions { M680X_INS_NEG, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, dir_hid, inh_hid }, { M680X_INS_LSR, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, dir_hid, inh_hid }, { M680X_INS_ASR, dir_hid, inh_hid }, { M680X_INS_LSL, dir_hid, inh_hid }, { M680X_INS_ROL, dir_hid, inh_hid }, { M680X_INS_DEC, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, dir_hid, inh_hid }, { M680X_INS_TST, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLR, dir_hid, inh_hid }, // 0x4x, inherent instructions { M680X_INS_NEGA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_MUL, inh_hid, inh_hid }, { M680X_INS_COMA, inh_hid, inh_hid }, { M680X_INS_LSRA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RORA, inh_hid, inh_hid }, { M680X_INS_ASRA, inh_hid, inh_hid }, { M680X_INS_LSLA, inh_hid, inh_hid }, { M680X_INS_ROLA, inh_hid, inh_hid }, { M680X_INS_DECA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INCA, inh_hid, inh_hid }, { M680X_INS_TSTA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLRA, inh_hid, inh_hid }, // 0x5x, inherent instructions { M680X_INS_NEGX, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COMX, inh_hid, inh_hid }, { M680X_INS_LSRX, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RORX, inh_hid, inh_hid }, { M680X_INS_ASRX, inh_hid, inh_hid }, { M680X_INS_LSLX, inh_hid, inh_hid }, { M680X_INS_ROLX, inh_hid, inh_hid }, { M680X_INS_DECX, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INCX, inh_hid, inh_hid }, { M680X_INS_TSTX, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLRX, inh_hid, inh_hid }, // 0x6x, indexed, 1 byte offset instructions { M680X_INS_NEG, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, idxX_hid, inh_hid }, { M680X_INS_LSR, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, idxX_hid, inh_hid }, { M680X_INS_ASR, idxX_hid, inh_hid }, { M680X_INS_LSL, idxX_hid, inh_hid }, { M680X_INS_ROL, idxX_hid, inh_hid }, { M680X_INS_DEC, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, idxX_hid, inh_hid }, { M680X_INS_TST, idxX_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLR, idxX_hid, inh_hid }, // 0x7x, indexed, no offset instructions { M680X_INS_NEG, idxX0_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, idxX0_hid, inh_hid }, { M680X_INS_LSR, idxX0_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, idxX0_hid, inh_hid }, { M680X_INS_ASR, idxX0_hid, inh_hid }, { M680X_INS_LSL, idxX0_hid, inh_hid }, { M680X_INS_ROL, idxX0_hid, inh_hid }, { M680X_INS_DEC, idxX0_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, idxX0_hid, inh_hid }, { M680X_INS_TST, idxX0_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLR, idxX0_hid, inh_hid }, // 0x8x, inherent instructions { M680X_INS_RTI, inh_hid, inh_hid }, { M680X_INS_RTS, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_SWI, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_STOP, inh_hid, inh_hid }, { M680X_INS_WAIT, inh_hid, inh_hid }, // 0x9x, inherent instructions { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_TAX, inh_hid, inh_hid }, { M680X_INS_CLC, inh_hid, inh_hid }, { M680X_INS_SEC, inh_hid, inh_hid }, { M680X_INS_CLI, inh_hid, inh_hid }, { M680X_INS_SEI, inh_hid, inh_hid }, { M680X_INS_RSP, inh_hid, inh_hid }, { M680X_INS_NOP, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_TXA, inh_hid, inh_hid }, // 0xAx, immediate instructions with reg. A { M680X_INS_SUB, imm8_hid, inh_hid }, { M680X_INS_CMP, imm8_hid, inh_hid }, { M680X_INS_SBC, imm8_hid, inh_hid }, { M680X_INS_CPX, imm8_hid, inh_hid }, { M680X_INS_AND, imm8_hid, inh_hid }, { M680X_INS_BIT, imm8_hid, inh_hid }, { M680X_INS_LDA, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_EOR, imm8_hid, inh_hid }, { M680X_INS_ADC, imm8_hid, inh_hid }, { M680X_INS_ORA, imm8_hid, inh_hid }, { M680X_INS_ADD, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_BSR, rel8_hid, inh_hid }, { M680X_INS_LDX, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, // 0xBx, direct instructions with reg. A { M680X_INS_SUB, dir_hid, inh_hid }, { M680X_INS_CMP, dir_hid, inh_hid }, { M680X_INS_SBC, dir_hid, inh_hid }, { M680X_INS_CPX, dir_hid, inh_hid }, { M680X_INS_AND, dir_hid, inh_hid }, { M680X_INS_BIT, dir_hid, inh_hid }, { M680X_INS_LDA, dir_hid, inh_hid }, { M680X_INS_STA, dir_hid, inh_hid }, { M680X_INS_EOR, dir_hid, inh_hid }, { M680X_INS_ADC, dir_hid, inh_hid }, { M680X_INS_ORA, dir_hid, inh_hid }, { M680X_INS_ADD, dir_hid, inh_hid }, { M680X_INS_JMP, dir_hid, inh_hid }, { M680X_INS_JSR, dir_hid, inh_hid }, { M680X_INS_LDX, dir_hid, inh_hid }, { M680X_INS_STX, dir_hid, inh_hid }, // 0xCx, extended instructions with reg. A { M680X_INS_SUB, ext_hid, inh_hid }, { M680X_INS_CMP, ext_hid, inh_hid }, { M680X_INS_SBC, ext_hid, inh_hid }, { M680X_INS_CPX, ext_hid, inh_hid }, { M680X_INS_AND, ext_hid, inh_hid }, { M680X_INS_BIT, ext_hid, inh_hid }, { M680X_INS_LDA, ext_hid, inh_hid }, { M680X_INS_STA, ext_hid, inh_hid }, { M680X_INS_EOR, ext_hid, inh_hid }, { M680X_INS_ADC, ext_hid, inh_hid }, { M680X_INS_ORA, ext_hid, inh_hid }, { M680X_INS_ADD, ext_hid, inh_hid }, { M680X_INS_JMP, ext_hid, inh_hid }, { M680X_INS_JSR, ext_hid, inh_hid }, { M680X_INS_LDX, ext_hid, inh_hid }, { M680X_INS_STX, ext_hid, inh_hid }, // 0xDx, indexed with 2 byte offset instructions with reg. A { M680X_INS_SUB, idxX16_hid, inh_hid }, { M680X_INS_CMP, idxX16_hid, inh_hid }, { M680X_INS_SBC, idxX16_hid, inh_hid }, { M680X_INS_CPX, idxX16_hid, inh_hid }, { M680X_INS_AND, idxX16_hid, inh_hid }, { M680X_INS_BIT, idxX16_hid, inh_hid }, { M680X_INS_LDA, idxX16_hid, inh_hid }, { M680X_INS_STA, idxX16_hid, inh_hid }, { M680X_INS_EOR, idxX16_hid, inh_hid }, { M680X_INS_ADC, idxX16_hid, inh_hid }, { M680X_INS_ORA, idxX16_hid, inh_hid }, { M680X_INS_ADD, idxX16_hid, inh_hid }, { M680X_INS_JMP, idxX16_hid, inh_hid }, { M680X_INS_JSR, idxX16_hid, inh_hid }, { M680X_INS_LDX, idxX16_hid, inh_hid }, { M680X_INS_STX, idxX16_hid, inh_hid }, // 0xEx, indexed with 1 byte offset instructions with reg. A { M680X_INS_SUB, idxX_hid, inh_hid }, { M680X_INS_CMP, idxX_hid, inh_hid }, { M680X_INS_SBC, idxX_hid, inh_hid }, { M680X_INS_CPX, idxX_hid, inh_hid }, { M680X_INS_AND, idxX_hid, inh_hid }, { M680X_INS_BIT, idxX_hid, inh_hid }, { M680X_INS_LDA, idxX_hid, inh_hid }, { M680X_INS_STA, idxX_hid, inh_hid }, { M680X_INS_EOR, idxX_hid, inh_hid }, { M680X_INS_ADC, idxX_hid, inh_hid }, { M680X_INS_ORA, idxX_hid, inh_hid }, { M680X_INS_ADD, idxX_hid, inh_hid }, { M680X_INS_JMP, idxX_hid, inh_hid }, { M680X_INS_JSR, idxX_hid, inh_hid }, { M680X_INS_LDX, idxX_hid, inh_hid }, { M680X_INS_STX, idxX_hid, inh_hid }, // 0xFx, indexed without offset instructions with reg. A { M680X_INS_SUB, idxX0_hid, inh_hid }, { M680X_INS_CMP, idxX0_hid, inh_hid }, { M680X_INS_SBC, idxX0_hid, inh_hid }, { M680X_INS_CPX, idxX0_hid, inh_hid }, { M680X_INS_AND, idxX0_hid, inh_hid }, { M680X_INS_BIT, idxX0_hid, inh_hid }, { M680X_INS_LDA, idxX0_hid, inh_hid }, { M680X_INS_STA, idxX0_hid, inh_hid }, { M680X_INS_EOR, idxX0_hid, inh_hid }, { M680X_INS_ADC, idxX0_hid, inh_hid }, { M680X_INS_ORA, idxX0_hid, inh_hid }, { M680X_INS_ADD, idxX0_hid, inh_hid }, { M680X_INS_JMP, idxX0_hid, inh_hid }, { M680X_INS_JSR, idxX0_hid, inh_hid }, { M680X_INS_LDX, idxX0_hid, inh_hid }, { M680X_INS_STX, idxX0_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/m6808.inc000064400000000000000000000075760072674642500171760ustar 00000000000000 // Additional instructions only supported on M68HC08 static const inst_pageX g_m6808_inst_overlay_table[] = { { 0x31, M680X_INS_CBEQ, dir_hid, rel8_hid }, { 0x35, M680X_INS_STHX, dir_hid, inh_hid }, { 0x3b, M680X_INS_DBNZ, dir_hid, rel8_hid }, { 0x41, M680X_INS_CBEQA, imm8rel_hid, inh_hid }, { 0x45, M680X_INS_LDHX, imm16_hid, inh_hid }, { 0x4b, M680X_INS_DBNZA, rel8_hid, inh_hid }, { 0x4e, M680X_INS_MOV, dir_hid, dir_hid }, { 0x51, M680X_INS_CBEQX, imm8rel_hid, inh_hid }, { 0x52, M680X_INS_DIV, inh_hid, inh_hid }, { 0x55, M680X_INS_LDHX, dir_hid, inh_hid }, { 0x5b, M680X_INS_DBNZX, rel8_hid, inh_hid }, { 0x5e, M680X_INS_MOV, dir_hid, idxX0p_hid }, { 0x61, M680X_INS_CBEQ, idxXp_hid, rel8_hid }, { 0x62, M680X_INS_NSA, inh_hid, inh_hid }, { 0x65, M680X_INS_CPHX, imm16_hid, inh_hid }, { 0x6b, M680X_INS_DBNZ, idxX_hid, rel8_hid }, { 0x6e, M680X_INS_MOV, imm8_hid, dir_hid }, { 0x71, M680X_INS_CBEQ, idxX0p_hid, rel8_hid }, { 0x72, M680X_INS_DAA, inh_hid, inh_hid }, { 0x75, M680X_INS_CPHX, dir_hid, inh_hid }, { 0x7b, M680X_INS_DBNZ, idxX0_hid, rel8_hid }, { 0x7e, M680X_INS_MOV, idxX0p_hid, dir_hid }, { 0x84, M680X_INS_TAP, inh_hid, inh_hid }, { 0x85, M680X_INS_TPA, inh_hid, inh_hid }, { 0x86, M680X_INS_PULA, inh_hid, inh_hid }, { 0x87, M680X_INS_PSHA, inh_hid, inh_hid }, { 0x88, M680X_INS_PULX, inh_hid, inh_hid }, { 0x89, M680X_INS_PSHX, inh_hid, inh_hid }, { 0x8a, M680X_INS_PULH, inh_hid, inh_hid }, { 0x8b, M680X_INS_PSHH, inh_hid, inh_hid }, { 0x8c, M680X_INS_CLRH, inh_hid, inh_hid }, { 0x90, M680X_INS_BGE, rel8_hid, inh_hid }, { 0x91, M680X_INS_BLT, rel8_hid, inh_hid }, { 0x92, M680X_INS_BGT, rel8_hid, inh_hid }, { 0x93, M680X_INS_BLE, rel8_hid, inh_hid }, { 0x94, M680X_INS_TXS, inh_hid, inh_hid }, { 0x95, M680X_INS_TSX, inh_hid, inh_hid }, { 0x97, M680X_INS_TAX, inh_hid, inh_hid }, { 0x9f, M680X_INS_TXA, inh_hid, inh_hid }, { 0xa7, M680X_INS_AIS, imm8_hid, inh_hid }, { 0xaf, M680X_INS_AIX, imm8_hid, inh_hid }, }; // M68HC08 PAGE2 instructions (prefix 0x9E) static const inst_pageX g_m6808_inst_page2_table[] = { { 0x60, M680X_INS_NEG, idxS_hid, inh_hid }, { 0x61, M680X_INS_CBEQ, idxS_hid, rel8_hid }, { 0x63, M680X_INS_COM, idxS_hid, inh_hid }, { 0x64, M680X_INS_LSR, idxS_hid, inh_hid }, { 0x66, M680X_INS_ROR, idxS_hid, inh_hid }, { 0x67, M680X_INS_ASR, idxS_hid, inh_hid }, { 0x68, M680X_INS_LSL, idxS_hid, inh_hid }, { 0x69, M680X_INS_ROL, idxS_hid, inh_hid }, { 0x6a, M680X_INS_DEC, idxS_hid, inh_hid }, { 0x6b, M680X_INS_DBNZ, idxS_hid, rel8_hid }, { 0x6c, M680X_INS_INC, idxS_hid, inh_hid }, { 0x6d, M680X_INS_TST, idxS_hid, inh_hid }, { 0x6f, M680X_INS_CLR, idxS_hid, inh_hid }, { 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid }, { 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid }, { 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid }, { 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid }, { 0xd4, M680X_INS_AND, idxS16_hid, inh_hid }, { 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid }, { 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid }, { 0xd7, M680X_INS_STA, idxS16_hid, inh_hid }, { 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid }, { 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid }, { 0xda, M680X_INS_ORA, idxS16_hid, inh_hid }, { 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid }, { 0xde, M680X_INS_LDX, idxS16_hid, inh_hid }, { 0xdf, M680X_INS_STX, idxS16_hid, inh_hid }, { 0xe0, M680X_INS_SUB, idxS_hid, inh_hid }, { 0xe1, M680X_INS_CMP, idxS_hid, inh_hid }, { 0xe2, M680X_INS_SBC, idxS_hid, inh_hid }, { 0xe3, M680X_INS_CPX, idxS_hid, inh_hid }, { 0xe4, M680X_INS_AND, idxS_hid, inh_hid }, { 0xe5, M680X_INS_BIT, idxS_hid, inh_hid }, { 0xe6, M680X_INS_LDA, idxS_hid, inh_hid }, { 0xe7, M680X_INS_STA, idxS_hid, inh_hid }, { 0xe8, M680X_INS_EOR, idxS_hid, inh_hid }, { 0xe9, M680X_INS_ADC, idxS_hid, inh_hid }, { 0xea, M680X_INS_ORA, idxS_hid, inh_hid }, { 0xeb, M680X_INS_ADD, idxS_hid, inh_hid }, { 0xee, M680X_INS_LDX, idxS_hid, inh_hid }, { 0xef, M680X_INS_STX, idxS_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/m6809.inc000064400000000000000000000335070072674642500171700ustar 00000000000000 // M6809/HD6309 PAGE1 instructions static const inst_page1 g_m6809_inst_page1_table[256] = { // 0x0x, direct instructions { M680X_INS_NEG, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, dir_hid, inh_hid }, { M680X_INS_LSR, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, dir_hid, inh_hid }, { M680X_INS_ASR, dir_hid, inh_hid }, { M680X_INS_LSL, dir_hid, inh_hid }, { M680X_INS_ROL, dir_hid, inh_hid }, { M680X_INS_DEC, dir_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, dir_hid, inh_hid }, { M680X_INS_TST, dir_hid, inh_hid }, { M680X_INS_JMP, dir_hid, inh_hid }, { M680X_INS_CLR, dir_hid, inh_hid }, // 0x1x, misc instructions { M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE2 { M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE3 { M680X_INS_NOP, inh_hid, inh_hid }, { M680X_INS_SYNC, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LBRA, rel16_hid, inh_hid }, { M680X_INS_LBSR, rel16_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_DAA, inh_hid, inh_hid }, { M680X_INS_ORCC, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ANDCC, imm8_hid, inh_hid }, { M680X_INS_SEX, inh_hid, inh_hid }, { M680X_INS_EXG, rr09_hid, inh_hid }, { M680X_INS_TFR, rr09_hid, inh_hid }, // 0x2x, relative branch instructions { M680X_INS_BRA, rel8_hid, inh_hid }, { M680X_INS_BRN, rel8_hid, inh_hid }, { M680X_INS_BHI, rel8_hid, inh_hid }, { M680X_INS_BLS, rel8_hid, inh_hid }, { M680X_INS_BCC, rel8_hid, inh_hid }, { M680X_INS_BCS, rel8_hid, inh_hid }, { M680X_INS_BNE, rel8_hid, inh_hid }, { M680X_INS_BEQ, rel8_hid, inh_hid }, { M680X_INS_BVC, rel8_hid, inh_hid }, { M680X_INS_BVS, rel8_hid, inh_hid }, { M680X_INS_BPL, rel8_hid, inh_hid }, { M680X_INS_BMI, rel8_hid, inh_hid }, { M680X_INS_BGE, rel8_hid, inh_hid }, { M680X_INS_BLT, rel8_hid, inh_hid }, { M680X_INS_BGT, rel8_hid, inh_hid }, { M680X_INS_BLE, rel8_hid, inh_hid }, // 0x3x, misc instructions { M680X_INS_LEAX, idx09_hid, inh_hid }, { M680X_INS_LEAY, idx09_hid, inh_hid }, { M680X_INS_LEAS, idx09_hid, inh_hid }, { M680X_INS_LEAU, idx09_hid, inh_hid }, { M680X_INS_PSHS, rbits_hid, inh_hid }, { M680X_INS_PULS, rbits_hid, inh_hid }, { M680X_INS_PSHU, rbits_hid, inh_hid }, { M680X_INS_PULU, rbits_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RTS, inh_hid, inh_hid }, { M680X_INS_ABX, inh_hid, inh_hid }, { M680X_INS_RTI, inh_hid, inh_hid }, { M680X_INS_CWAI, imm8_hid, inh_hid }, { M680X_INS_MUL, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_SWI, inh_hid, inh_hid }, // 0x4x, Register A instructions { M680X_INS_NEGA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COMA, inh_hid, inh_hid }, { M680X_INS_LSRA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RORA, inh_hid, inh_hid }, { M680X_INS_ASRA, inh_hid, inh_hid }, { M680X_INS_LSLA, inh_hid, inh_hid }, { M680X_INS_ROLA, inh_hid, inh_hid }, { M680X_INS_DECA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INCA, inh_hid, inh_hid }, { M680X_INS_TSTA, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLRA, inh_hid, inh_hid }, // 0x5x, Register B instructions { M680X_INS_NEGB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COMB, inh_hid, inh_hid }, { M680X_INS_LSRB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_RORB, inh_hid, inh_hid }, { M680X_INS_ASRB, inh_hid, inh_hid }, { M680X_INS_LSLB, inh_hid, inh_hid }, { M680X_INS_ROLB, inh_hid, inh_hid }, { M680X_INS_DECB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INCB, inh_hid, inh_hid }, { M680X_INS_TSTB, inh_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_CLRB, inh_hid, inh_hid }, // 0x6x, indexed instructions { M680X_INS_NEG, idx09_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, idx09_hid, inh_hid }, { M680X_INS_LSR, idx09_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, idx09_hid, inh_hid }, { M680X_INS_ASR, idx09_hid, inh_hid }, { M680X_INS_LSL, idx09_hid, inh_hid }, { M680X_INS_ROL, idx09_hid, inh_hid }, { M680X_INS_DEC, idx09_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, idx09_hid, inh_hid }, { M680X_INS_TST, idx09_hid, inh_hid }, { M680X_INS_JMP, idx09_hid, inh_hid }, { M680X_INS_CLR, idx09_hid, inh_hid }, // 0x7x, extended instructions { M680X_INS_NEG, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_COM, ext_hid, inh_hid }, { M680X_INS_LSR, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_ROR, ext_hid, inh_hid }, { M680X_INS_ASR, ext_hid, inh_hid }, { M680X_INS_LSL, ext_hid, inh_hid }, { M680X_INS_ROL, ext_hid, inh_hid }, { M680X_INS_DEC, ext_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_INC, ext_hid, inh_hid }, { M680X_INS_TST, ext_hid, inh_hid }, { M680X_INS_JMP, ext_hid, inh_hid }, { M680X_INS_CLR, ext_hid, inh_hid }, // 0x8x, immediate instructions with Register A,D,X { M680X_INS_SUBA, imm8_hid, inh_hid }, { M680X_INS_CMPA, imm8_hid, inh_hid }, { M680X_INS_SBCA, imm8_hid, inh_hid }, { M680X_INS_SUBD, imm16_hid, inh_hid }, { M680X_INS_ANDA, imm8_hid, inh_hid }, { M680X_INS_BITA, imm8_hid, inh_hid }, { M680X_INS_LDA, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_EORA, imm8_hid, inh_hid }, { M680X_INS_ADCA, imm8_hid, inh_hid }, { M680X_INS_ORA, imm8_hid, inh_hid }, { M680X_INS_ADDA, imm8_hid, inh_hid }, { M680X_INS_CMPX, imm16_hid, inh_hid }, { M680X_INS_BSR, rel8_hid, inh_hid }, { M680X_INS_LDX, imm16_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, // 0x9x, direct instructions with register A,D,X { M680X_INS_SUBA, dir_hid, inh_hid }, { M680X_INS_CMPA, dir_hid, inh_hid }, { M680X_INS_SBCA, dir_hid, inh_hid }, { M680X_INS_SUBD, dir_hid, inh_hid }, { M680X_INS_ANDA, dir_hid, inh_hid }, { M680X_INS_BITA, dir_hid, inh_hid }, { M680X_INS_LDA, dir_hid, inh_hid }, { M680X_INS_STA, dir_hid, inh_hid }, { M680X_INS_EORA, dir_hid, inh_hid }, { M680X_INS_ADCA, dir_hid, inh_hid }, { M680X_INS_ORA, dir_hid, inh_hid }, { M680X_INS_ADDA, dir_hid, inh_hid }, { M680X_INS_CMPX, dir_hid, inh_hid }, { M680X_INS_JSR, dir_hid, inh_hid }, { M680X_INS_LDX, dir_hid, inh_hid }, { M680X_INS_STX, dir_hid, inh_hid }, // 0xAx, indexed instructions with Register A,D,X { M680X_INS_SUBA, idx09_hid, inh_hid }, { M680X_INS_CMPA, idx09_hid, inh_hid }, { M680X_INS_SBCA, idx09_hid, inh_hid }, { M680X_INS_SUBD, idx09_hid, inh_hid }, { M680X_INS_ANDA, idx09_hid, inh_hid }, { M680X_INS_BITA, idx09_hid, inh_hid }, { M680X_INS_LDA, idx09_hid, inh_hid }, { M680X_INS_STA, idx09_hid, inh_hid }, { M680X_INS_EORA, idx09_hid, inh_hid }, { M680X_INS_ADCA, idx09_hid, inh_hid }, { M680X_INS_ORA, idx09_hid, inh_hid }, { M680X_INS_ADDA, idx09_hid, inh_hid }, { M680X_INS_CMPX, idx09_hid, inh_hid }, { M680X_INS_JSR, idx09_hid, inh_hid }, { M680X_INS_LDX, idx09_hid, inh_hid }, { M680X_INS_STX, idx09_hid, inh_hid }, // 0xBx, extended instructions with register A,D,X { M680X_INS_SUBA, ext_hid, inh_hid }, { M680X_INS_CMPA, ext_hid, inh_hid }, { M680X_INS_SBCA, ext_hid, inh_hid }, { M680X_INS_SUBD, ext_hid, inh_hid }, { M680X_INS_ANDA, ext_hid, inh_hid }, { M680X_INS_BITA, ext_hid, inh_hid }, { M680X_INS_LDA, ext_hid, inh_hid }, { M680X_INS_STA, ext_hid, inh_hid }, { M680X_INS_EORA, ext_hid, inh_hid }, { M680X_INS_ADCA, ext_hid, inh_hid }, { M680X_INS_ORA, ext_hid, inh_hid }, { M680X_INS_ADDA, ext_hid, inh_hid }, { M680X_INS_CMPX, ext_hid, inh_hid }, { M680X_INS_JSR, ext_hid, inh_hid }, { M680X_INS_LDX, ext_hid, inh_hid }, { M680X_INS_STX, ext_hid, inh_hid }, // 0xCx, immediate instructions with register B,D,U { M680X_INS_SUBB, imm8_hid, inh_hid }, { M680X_INS_CMPB, imm8_hid, inh_hid }, { M680X_INS_SBCB, imm8_hid, inh_hid }, { M680X_INS_ADDD, imm16_hid, inh_hid }, { M680X_INS_ANDB, imm8_hid, inh_hid }, { M680X_INS_BITB, imm8_hid, inh_hid }, { M680X_INS_LDB, imm8_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_EORB, imm8_hid, inh_hid }, { M680X_INS_ADCB, imm8_hid, inh_hid }, { M680X_INS_ORB, imm8_hid, inh_hid }, { M680X_INS_ADDB, imm8_hid, inh_hid }, { M680X_INS_LDD, imm16_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, { M680X_INS_LDU, imm16_hid, inh_hid }, { M680X_INS_ILLGL, illgl_hid, inh_hid }, // 0xDx direct instructions with register B,D,U { M680X_INS_SUBB, dir_hid, inh_hid }, { M680X_INS_CMPB, dir_hid, inh_hid }, { M680X_INS_SBCB, dir_hid, inh_hid }, { M680X_INS_ADDD, dir_hid, inh_hid }, { M680X_INS_ANDB, dir_hid, inh_hid }, { M680X_INS_BITB, dir_hid, inh_hid }, { M680X_INS_LDB, dir_hid, inh_hid }, { M680X_INS_STB, dir_hid, inh_hid }, { M680X_INS_EORB, dir_hid, inh_hid }, { M680X_INS_ADCB, dir_hid, inh_hid }, { M680X_INS_ORB, dir_hid, inh_hid }, { M680X_INS_ADDB, dir_hid, inh_hid }, { M680X_INS_LDD, dir_hid, inh_hid }, { M680X_INS_STD, dir_hid, inh_hid }, { M680X_INS_LDU, dir_hid, inh_hid }, { M680X_INS_STU, dir_hid, inh_hid }, // 0xEx, indexed instruction with register B,D,U { M680X_INS_SUBB, idx09_hid, inh_hid }, { M680X_INS_CMPB, idx09_hid, inh_hid }, { M680X_INS_SBCB, idx09_hid, inh_hid }, { M680X_INS_ADDD, idx09_hid, inh_hid }, { M680X_INS_ANDB, idx09_hid, inh_hid }, { M680X_INS_BITB, idx09_hid, inh_hid }, { M680X_INS_LDB, idx09_hid, inh_hid }, { M680X_INS_STB, idx09_hid, inh_hid }, { M680X_INS_EORB, idx09_hid, inh_hid }, { M680X_INS_ADCB, idx09_hid, inh_hid }, { M680X_INS_ORB, idx09_hid, inh_hid }, { M680X_INS_ADDB, idx09_hid, inh_hid }, { M680X_INS_LDD, idx09_hid, inh_hid }, { M680X_INS_STD, idx09_hid, inh_hid }, { M680X_INS_LDU, idx09_hid, inh_hid }, { M680X_INS_STU, idx09_hid, inh_hid }, // 0xFx, extended instructions with register B,D,U { M680X_INS_SUBB, ext_hid, inh_hid }, { M680X_INS_CMPB, ext_hid, inh_hid }, { M680X_INS_SBCB, ext_hid, inh_hid }, { M680X_INS_ADDD, ext_hid, inh_hid }, { M680X_INS_ANDB, ext_hid, inh_hid }, { M680X_INS_BITB, ext_hid, inh_hid }, { M680X_INS_LDB, ext_hid, inh_hid }, { M680X_INS_STB, ext_hid, inh_hid }, { M680X_INS_EORB, ext_hid, inh_hid }, { M680X_INS_ADCB, ext_hid, inh_hid }, { M680X_INS_ORB, ext_hid, inh_hid }, { M680X_INS_ADDB, ext_hid, inh_hid }, { M680X_INS_LDD, ext_hid, inh_hid }, { M680X_INS_STD, ext_hid, inh_hid }, { M680X_INS_LDU, ext_hid, inh_hid }, { M680X_INS_STU, ext_hid, inh_hid }, }; // The following array has to be sorted by increasing // opcodes. Otherwise the binary_search will fail. // // M6809 PAGE2 instructions (with prefix 0x10) static const inst_pageX g_m6809_inst_page2_table[] = { // 0x2x, relative long branch instructions { 0x21, M680X_INS_LBRN, rel16_hid, inh_hid }, { 0x22, M680X_INS_LBHI, rel16_hid, inh_hid }, { 0x23, M680X_INS_LBLS, rel16_hid, inh_hid }, { 0x24, M680X_INS_LBCC, rel16_hid, inh_hid }, { 0x25, M680X_INS_LBCS, rel16_hid, inh_hid }, { 0x26, M680X_INS_LBNE, rel16_hid, inh_hid }, { 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid }, { 0x28, M680X_INS_LBVC, rel16_hid, inh_hid }, { 0x29, M680X_INS_LBVS, rel16_hid, inh_hid }, { 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid }, { 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid }, { 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid }, { 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid }, { 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid }, { 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid }, // 0x3x { 0x3f, M680X_INS_SWI2, inh_hid, inh_hid }, // 0x8x, immediate instructions with register D,Y { 0x83, M680X_INS_CMPD, imm16_hid, inh_hid }, { 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid }, { 0x8e, M680X_INS_LDY, imm16_hid, inh_hid }, // 0x9x, direct instructions with register D,Y { 0x93, M680X_INS_CMPD, dir_hid, inh_hid }, { 0x9c, M680X_INS_CMPY, dir_hid, inh_hid }, { 0x9e, M680X_INS_LDY, dir_hid, inh_hid }, { 0x9f, M680X_INS_STY, dir_hid, inh_hid }, // 0xAx, indexed instructions with register D,Y { 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid }, { 0xac, M680X_INS_CMPY, idx09_hid, inh_hid }, { 0xae, M680X_INS_LDY, idx09_hid, inh_hid }, { 0xaf, M680X_INS_STY, idx09_hid, inh_hid }, // 0xBx, extended instructions with register D,Y { 0xb3, M680X_INS_CMPD, ext_hid, inh_hid }, { 0xbc, M680X_INS_CMPY, ext_hid, inh_hid }, { 0xbe, M680X_INS_LDY, ext_hid, inh_hid }, { 0xbf, M680X_INS_STY, ext_hid, inh_hid }, // 0xCx, immediate instructions with register S { 0xce, M680X_INS_LDS, imm16_hid, inh_hid }, // 0xDx, direct instructions with register S { 0xde, M680X_INS_LDS, dir_hid, inh_hid }, { 0xdf, M680X_INS_STS, dir_hid, inh_hid }, // 0xEx, indexed instructions with register S { 0xee, M680X_INS_LDS, idx09_hid, inh_hid }, { 0xef, M680X_INS_STS, idx09_hid, inh_hid }, // 0xFx, extended instructions with register S { 0xfe, M680X_INS_LDS, ext_hid, inh_hid }, { 0xff, M680X_INS_STS, ext_hid, inh_hid }, }; // The following array has to be sorted by increasing // opcodes. Otherwise the binary_search will fail. // // M6809 PAGE3 instructions (with prefix 0x11) static const inst_pageX g_m6809_inst_page3_table[] = { { 0x3f, M680X_INS_SWI3, inh_hid, inh_hid }, // 0x8x, immediate instructions with register U,S { 0x83, M680X_INS_CMPU, imm16_hid, inh_hid }, { 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid }, // 0x9x, direct instructions with register U,S { 0x93, M680X_INS_CMPU, dir_hid, inh_hid }, { 0x9c, M680X_INS_CMPS, dir_hid, inh_hid }, // 0xAx, indexed instructions with register U,S { 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid }, { 0xac, M680X_INS_CMPS, idx09_hid, inh_hid }, // 0xBx, extended instructions with register U,S { 0xb3, M680X_INS_CMPU, ext_hid, inh_hid }, { 0xbc, M680X_INS_CMPS, ext_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M680X/m6811.inc000064400000000000000000000104600072674642500171520ustar 00000000000000 // Additional instructions only supported on M68HC11 static const inst_pageX g_m6811_inst_overlay_table[] = { { 0x00, M680X_INS_TEST, inh_hid, inh_hid }, { 0x02, M680X_INS_IDIV, inh_hid, inh_hid }, { 0x03, M680X_INS_FDIV, inh_hid, inh_hid }, { 0x12, M680X_INS_BRSET, dir_hid, imm8rel_hid }, { 0x13, M680X_INS_BRCLR, dir_hid, imm8rel_hid }, { 0x14, M680X_INS_BSET, dir_hid, imm8_hid }, { 0x15, M680X_INS_BCLR, dir_hid, imm8_hid }, { 0x1c, M680X_INS_BSET, idxX_hid, imm8_hid }, { 0x1d, M680X_INS_BCLR, idxX_hid, imm8_hid }, { 0x1e, M680X_INS_BRSET, idxX_hid, imm8rel_hid }, { 0x1f, M680X_INS_BRCLR, idxX_hid, imm8rel_hid }, { 0x8f, M680X_INS_XGDX, inh_hid, inh_hid }, { 0xcf, M680X_INS_STOP, inh_hid, inh_hid }, }; // M68HC11 PAGE2 instructions static const inst_pageX g_m6811_inst_page2_table[] = { { 0x08, M680X_INS_INY, inh_hid, inh_hid }, { 0x09, M680X_INS_DEY, inh_hid, inh_hid }, { 0x1c, M680X_INS_BSET, idxY_hid, imm8_hid }, { 0x1d, M680X_INS_BCLR, idxY_hid, imm8_hid }, { 0x1e, M680X_INS_BRSET, idxY_hid, imm8rel_hid }, { 0x1f, M680X_INS_BRCLR, idxY_hid, imm8rel_hid }, { 0x30, M680X_INS_TSY, inh_hid, inh_hid }, { 0x35, M680X_INS_TYS, inh_hid, inh_hid }, { 0x38, M680X_INS_PULY, inh_hid, inh_hid }, { 0x3a, M680X_INS_ABY, inh_hid, inh_hid }, { 0x3c, M680X_INS_PSHY, inh_hid, inh_hid }, { 0x60, M680X_INS_NEG, idxY_hid, inh_hid }, { 0x63, M680X_INS_COM, idxY_hid, inh_hid }, { 0x64, M680X_INS_LSR, idxY_hid, inh_hid }, { 0x66, M680X_INS_ROR, idxY_hid, inh_hid }, { 0x67, M680X_INS_ASR, idxY_hid, inh_hid }, { 0x68, M680X_INS_ASL, idxY_hid, inh_hid }, { 0x69, M680X_INS_ROL, idxY_hid, inh_hid }, { 0x6a, M680X_INS_DEC, idxY_hid, inh_hid }, { 0x6c, M680X_INS_INC, idxY_hid, inh_hid }, { 0x6d, M680X_INS_TST, idxY_hid, inh_hid }, { 0x6e, M680X_INS_JMP, idxY_hid, inh_hid }, { 0x6f, M680X_INS_CLR, idxY_hid, inh_hid }, { 0x8c, M680X_INS_CPY, imm16_hid, inh_hid }, { 0x8f, M680X_INS_XGDY, inh_hid, inh_hid }, { 0x9c, M680X_INS_CPY, dir_hid, inh_hid }, { 0xa0, M680X_INS_SUBA, idxY_hid, inh_hid }, { 0xa1, M680X_INS_CMPA, idxY_hid, inh_hid }, { 0xa2, M680X_INS_SBCA, idxY_hid, inh_hid }, { 0xa3, M680X_INS_SUBD, idxY_hid, inh_hid }, { 0xa4, M680X_INS_ANDA, idxY_hid, inh_hid }, { 0xa5, M680X_INS_BITA, idxY_hid, inh_hid }, { 0xa6, M680X_INS_LDAA, idxY_hid, inh_hid }, { 0xa7, M680X_INS_STAA, idxY_hid, inh_hid }, { 0xa8, M680X_INS_EORA, idxY_hid, inh_hid }, { 0xa9, M680X_INS_ADCA, idxY_hid, inh_hid }, { 0xaa, M680X_INS_ORAA, idxY_hid, inh_hid }, { 0xab, M680X_INS_ADDA, idxY_hid, inh_hid }, { 0xac, M680X_INS_CPY, idxY_hid, inh_hid }, { 0xad, M680X_INS_JSR, idxY_hid, inh_hid }, { 0xae, M680X_INS_LDS, idxY_hid, inh_hid }, { 0xaf, M680X_INS_STS, idxY_hid, inh_hid }, { 0xbc, M680X_INS_CPY, ext_hid, inh_hid }, { 0xce, M680X_INS_LDY, imm16_hid, inh_hid }, { 0xde, M680X_INS_LDY, dir_hid, inh_hid }, { 0xdf, M680X_INS_STY, dir_hid, inh_hid }, { 0xe0, M680X_INS_SUBB, idxY_hid, inh_hid }, { 0xe1, M680X_INS_CMPB, idxY_hid, inh_hid }, { 0xe2, M680X_INS_SBCB, idxY_hid, inh_hid }, { 0xe3, M680X_INS_ADDD, idxY_hid, inh_hid }, { 0xe4, M680X_INS_ANDB, idxY_hid, inh_hid }, { 0xe5, M680X_INS_BITB, idxY_hid, inh_hid }, { 0xe6, M680X_INS_LDAB, idxY_hid, inh_hid }, { 0xe7, M680X_INS_STAB, idxY_hid, inh_hid }, { 0xe8, M680X_INS_EORB, idxY_hid, inh_hid }, { 0xe9, M680X_INS_ADCB, idxY_hid, inh_hid }, { 0xea, M680X_INS_ORAB, idxY_hid, inh_hid }, { 0xeb, M680X_INS_ADDB, idxY_hid, inh_hid }, { 0xec, M680X_INS_LDD, idxY_hid, inh_hid }, { 0xed, M680X_INS_STD, idxY_hid, inh_hid }, { 0xee, M680X_INS_LDY, idxY_hid, inh_hid }, { 0xef, M680X_INS_STY, idxY_hid, inh_hid }, { 0xfe, M680X_INS_LDY, ext_hid, inh_hid }, { 0xff, M680X_INS_STY, ext_hid, inh_hid }, }; // M68HC11 PAGE3 instructions static const inst_pageX g_m6811_inst_page3_table[] = { { 0x83, M680X_INS_CPD, imm16_hid, inh_hid }, { 0x93, M680X_INS_CPD, dir_hid, inh_hid }, { 0xa3, M680X_INS_CPD, idxX_hid, inh_hid }, { 0xac, M680X_INS_CPY, idxX_hid, inh_hid }, { 0xb3, M680X_INS_CPD, ext_hid, inh_hid }, { 0xee, M680X_INS_LDY, idxX_hid, inh_hid }, { 0xef, M680X_INS_STY, idxX_hid, inh_hid }, }; // M68HC11 PAGE4 instructions static const inst_pageX g_m6811_inst_page4_table[] = { { 0xa3, M680X_INS_CPD, idxY_hid, inh_hid }, { 0xac, M680X_INS_CPX, idxY_hid, inh_hid }, { 0xee, M680X_INS_LDX, idxY_hid, inh_hid }, { 0xef, M680X_INS_STX, idxY_hid, inh_hid }, }; capstone-sys-0.15.0/capstone/arch/M68K/M68KDisassembler.c000064400000000000000000002543540072674642500210110ustar 00000000000000/* ======================================================================== */ /* ========================= LICENSING & COPYRIGHT ======================== */ /* ======================================================================== */ /* * MUSASHI * Version 3.4 * * A portable Motorola M680x0 processor emulation engine. * Copyright 1998-2001 Karl Stenerud. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ /* The code below is based on MUSASHI but has been heavily modified for Capstone by * Daniel Collin 2015-2019 */ /* ======================================================================== */ /* ================================ INCLUDES ============================== */ /* ======================================================================== */ #include #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCRegisterInfo.h" #include "M68KInstPrinter.h" #include "M68KDisassembler.h" /* ======================================================================== */ /* ============================ GENERAL DEFINES =========================== */ /* ======================================================================== */ /* Bit Isolation Functions */ #define BIT_0(A) ((A) & 0x00000001) #define BIT_1(A) ((A) & 0x00000002) #define BIT_2(A) ((A) & 0x00000004) #define BIT_3(A) ((A) & 0x00000008) #define BIT_4(A) ((A) & 0x00000010) #define BIT_5(A) ((A) & 0x00000020) #define BIT_6(A) ((A) & 0x00000040) #define BIT_7(A) ((A) & 0x00000080) #define BIT_8(A) ((A) & 0x00000100) #define BIT_9(A) ((A) & 0x00000200) #define BIT_A(A) ((A) & 0x00000400) #define BIT_B(A) ((A) & 0x00000800) #define BIT_C(A) ((A) & 0x00001000) #define BIT_D(A) ((A) & 0x00002000) #define BIT_E(A) ((A) & 0x00004000) #define BIT_F(A) ((A) & 0x00008000) #define BIT_10(A) ((A) & 0x00010000) #define BIT_11(A) ((A) & 0x00020000) #define BIT_12(A) ((A) & 0x00040000) #define BIT_13(A) ((A) & 0x00080000) #define BIT_14(A) ((A) & 0x00100000) #define BIT_15(A) ((A) & 0x00200000) #define BIT_16(A) ((A) & 0x00400000) #define BIT_17(A) ((A) & 0x00800000) #define BIT_18(A) ((A) & 0x01000000) #define BIT_19(A) ((A) & 0x02000000) #define BIT_1A(A) ((A) & 0x04000000) #define BIT_1B(A) ((A) & 0x08000000) #define BIT_1C(A) ((A) & 0x10000000) #define BIT_1D(A) ((A) & 0x20000000) #define BIT_1E(A) ((A) & 0x40000000) #define BIT_1F(A) ((A) & 0x80000000) /* These are the CPU types understood by this disassembler */ #define TYPE_68000 1 #define TYPE_68010 2 #define TYPE_68020 4 #define TYPE_68030 8 #define TYPE_68040 16 #define M68000_ONLY TYPE_68000 #define M68010_ONLY TYPE_68010 #define M68010_LESS (TYPE_68000 | TYPE_68010) #define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040) #define M68020_ONLY TYPE_68020 #define M68020_LESS (TYPE_68010 | TYPE_68020) #define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040) #define M68030_ONLY TYPE_68030 #define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030) #define M68030_PLUS (TYPE_68030 | TYPE_68040) #define M68040_PLUS TYPE_68040 enum { M68K_CPU_TYPE_INVALID, M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010, M68K_CPU_TYPE_68EC020, M68K_CPU_TYPE_68020, M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ }; /* Extension word formats */ #define EXT_8BIT_DISPLACEMENT(A) ((A)&0xff) #define EXT_FULL(A) BIT_8(A) #define EXT_EFFECTIVE_ZERO(A) (((A)&0xe4) == 0xc4 || ((A)&0xe2) == 0xc0) #define EXT_BASE_REGISTER_PRESENT(A) (!BIT_7(A)) #define EXT_INDEX_REGISTER_PRESENT(A) (!BIT_6(A)) #define EXT_INDEX_REGISTER(A) (((A)>>12)&7) #define EXT_INDEX_PRE_POST(A) (EXT_INDEX_PRESENT(A) && (A)&3) #define EXT_INDEX_PRE(A) (EXT_INDEX_PRESENT(A) && ((A)&7) < 4 && ((A)&7) != 0) #define EXT_INDEX_POST(A) (EXT_INDEX_PRESENT(A) && ((A)&7) > 4) #define EXT_INDEX_SCALE(A) (((A)>>9)&3) #define EXT_INDEX_LONG(A) BIT_B(A) #define EXT_INDEX_AR(A) BIT_F(A) #define EXT_BASE_DISPLACEMENT_PRESENT(A) (((A)&0x30) > 0x10) #define EXT_BASE_DISPLACEMENT_WORD(A) (((A)&0x30) == 0x20) #define EXT_BASE_DISPLACEMENT_LONG(A) (((A)&0x30) == 0x30) #define EXT_OUTER_DISPLACEMENT_PRESENT(A) (((A)&3) > 1 && ((A)&0x47) < 0x44) #define EXT_OUTER_DISPLACEMENT_WORD(A) (((A)&3) == 2 && ((A)&0x47) < 0x44) #define EXT_OUTER_DISPLACEMENT_LONG(A) (((A)&3) == 3 && ((A)&0x47) < 0x44) #define IS_BITSET(val,b) ((val) & (1 << (b))) #define BITFIELD_MASK(sb,eb) (((1 << ((sb) + 1))-1) & (~((1 << (eb))-1))) #define BITFIELD(val,sb,eb) ((BITFIELD_MASK(sb,eb) & (val)) >> (eb)) /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// static unsigned int m68k_read_disassembler_16(const m68k_info *info, const uint64_t addr) { const uint16_t v0 = info->code[addr + 0]; const uint16_t v1 = info->code[addr + 1]; return (v0 << 8) | v1; } static unsigned int m68k_read_disassembler_32(const m68k_info *info, const uint64_t addr) { const uint32_t v0 = info->code[addr + 0]; const uint32_t v1 = info->code[addr + 1]; const uint32_t v2 = info->code[addr + 2]; const uint32_t v3 = info->code[addr + 3]; return (v0 << 24) | (v1 << 16) | (v2 << 8) | v3; } static uint64_t m68k_read_disassembler_64(const m68k_info *info, const uint64_t addr) { const uint64_t v0 = info->code[addr + 0]; const uint64_t v1 = info->code[addr + 1]; const uint64_t v2 = info->code[addr + 2]; const uint64_t v3 = info->code[addr + 3]; const uint64_t v4 = info->code[addr + 4]; const uint64_t v5 = info->code[addr + 5]; const uint64_t v6 = info->code[addr + 6]; const uint64_t v7 = info->code[addr + 7]; return (v0 << 56) | (v1 << 48) | (v2 << 40) | (v3 << 32) | (v4 << 24) | (v5 << 16) | (v6 << 8) | v7; } static unsigned int m68k_read_safe_16(const m68k_info *info, const uint64_t address) { const uint64_t addr = (address - info->baseAddress) & info->address_mask; if (info->code_len < addr + 2) { return 0xaaaa; } return m68k_read_disassembler_16(info, addr); } static unsigned int m68k_read_safe_32(const m68k_info *info, const uint64_t address) { const uint64_t addr = (address - info->baseAddress) & info->address_mask; if (info->code_len < addr + 4) { return 0xaaaaaaaa; } return m68k_read_disassembler_32(info, addr); } static uint64_t m68k_read_safe_64(const m68k_info *info, const uint64_t address) { const uint64_t addr = (address - info->baseAddress) & info->address_mask; if (info->code_len < addr + 8) { return 0xaaaaaaaaaaaaaaaaLL; } return m68k_read_disassembler_64(info, addr); } /* ======================================================================== */ /* =============================== PROTOTYPES ============================= */ /* ======================================================================== */ /* make signed integers 100% portably */ static int make_int_8(int value); static int make_int_16(int value); /* Stuff to build the opcode handler jump table */ static void d68000_invalid(m68k_info *info); static int instruction_is_valid(m68k_info *info, const unsigned int word_check); typedef struct { void (*instruction)(m68k_info *info); /* handler function */ uint16_t word2_mask; /* mask the 2nd word */ uint16_t word2_match; /* what to match after masking */ } instruction_struct; /* ======================================================================== */ /* ================================= DATA ================================= */ /* ======================================================================== */ static const instruction_struct g_instruction_table[0x10000]; /* used by ops like asr, ror, addq, etc */ static const uint32_t g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7}; static const uint32_t g_5bit_data_table[32] = { 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }; static const m68k_insn s_branch_lut[] = { M68K_INS_INVALID, M68K_INS_INVALID, M68K_INS_BHI, M68K_INS_BLS, M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ, M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI, M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE, }; static const m68k_insn s_dbcc_lut[] = { M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS, M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ, M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI, M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE, }; static const m68k_insn s_scc_lut[] = { M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS, M68K_INS_SCC, M68K_INS_SCS, M68K_INS_SNE, M68K_INS_SEQ, M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI, M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE, }; static const m68k_insn s_trap_lut[] = { M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS, M68K_INS_TRAPCC, M68K_INS_TRAPCS, M68K_INS_TRAPNE, M68K_INS_TRAPEQ, M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI, M68K_INS_TRAPGE, M68K_INS_TRAPLT, M68K_INS_TRAPGT, M68K_INS_TRAPLE, }; /* ======================================================================== */ /* =========================== UTILITY FUNCTIONS ========================== */ /* ======================================================================== */ #define LIMIT_CPU_TYPES(info, ALLOWED_CPU_TYPES) \ do { \ if (!(info->type & ALLOWED_CPU_TYPES)) { \ d68000_invalid(info); \ return; \ } \ } while (0) static unsigned int peek_imm_8(const m68k_info *info) { return (m68k_read_safe_16((info), (info)->pc)&0xff); } static unsigned int peek_imm_16(const m68k_info *info) { return m68k_read_safe_16((info), (info)->pc); } static unsigned int peek_imm_32(const m68k_info *info) { return m68k_read_safe_32((info), (info)->pc); } static unsigned long long peek_imm_64(const m68k_info *info) { return m68k_read_safe_64((info), (info)->pc); } static unsigned int read_imm_8(m68k_info *info) { const unsigned int value = peek_imm_8(info); (info)->pc+=2; return value; } static unsigned int read_imm_16(m68k_info *info) { const unsigned int value = peek_imm_16(info); (info)->pc+=2; return value; } static unsigned int read_imm_32(m68k_info *info) { const unsigned int value = peek_imm_32(info); (info)->pc+=4; return value; } static unsigned long long read_imm_64(m68k_info *info) { const unsigned long long value = peek_imm_64(info); (info)->pc+=8; return value; } /* Fake a split interface */ #define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0) #define get_ea_mode_str_16(instruction) get_ea_mode_str(instruction, 1) #define get_ea_mode_str_32(instruction) get_ea_mode_str(instruction, 2) #define get_imm_str_s8() get_imm_str_s(0) #define get_imm_str_s16() get_imm_str_s(1) #define get_imm_str_s32() get_imm_str_s(2) #define get_imm_str_u8() get_imm_str_u(0) #define get_imm_str_u16() get_imm_str_u(1) #define get_imm_str_u32() get_imm_str_u(2) /* 100% portable signed int generators */ static int make_int_8(int value) { return (value & 0x80) ? value | ~0xff : value & 0xff; } static int make_int_16(int value) { return (value & 0x8000) ? value | ~0xffff : value & 0xffff; } static void get_with_index_address_mode(m68k_info *info, cs_m68k_op* op, uint32_t instruction, uint32_t size, bool is_pc) { uint32_t extension = read_imm_16(info); op->address_mode = M68K_AM_AREGI_INDEX_BASE_DISP; if (EXT_FULL(extension)) { uint32_t preindex; uint32_t postindex; op->mem.base_reg = M68K_REG_INVALID; op->mem.index_reg = M68K_REG_INVALID; /* Not sure how to deal with this? if (EXT_EFFECTIVE_ZERO(extension)) { strcpy(mode, "0"); break; } */ op->mem.in_disp = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32(info) : read_imm_16(info)) : 0; op->mem.out_disp = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32(info) : read_imm_16(info)) : 0; if (EXT_BASE_REGISTER_PRESENT(extension)) { if (is_pc) { op->mem.base_reg = M68K_REG_PC; } else { op->mem.base_reg = M68K_REG_A0 + (instruction & 7); } } if (EXT_INDEX_REGISTER_PRESENT(extension)) { if (EXT_INDEX_AR(extension)) { op->mem.index_reg = M68K_REG_A0 + EXT_INDEX_REGISTER(extension); } else { op->mem.index_reg = M68K_REG_D0 + EXT_INDEX_REGISTER(extension); } op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0; if (EXT_INDEX_SCALE(extension)) { op->mem.scale = 1 << EXT_INDEX_SCALE(extension); } } preindex = (extension & 7) > 0 && (extension & 7) < 4; postindex = (extension & 7) > 4; if (preindex) { op->address_mode = is_pc ? M68K_AM_PC_MEMI_PRE_INDEX : M68K_AM_MEMI_PRE_INDEX; } else if (postindex) { op->address_mode = is_pc ? M68K_AM_PC_MEMI_POST_INDEX : M68K_AM_MEMI_POST_INDEX; } return; } op->mem.index_reg = (EXT_INDEX_AR(extension) ? M68K_REG_A0 : M68K_REG_D0) + EXT_INDEX_REGISTER(extension); op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0; if (EXT_8BIT_DISPLACEMENT(extension) == 0) { if (is_pc) { op->mem.base_reg = M68K_REG_PC; op->address_mode = M68K_AM_PCI_INDEX_BASE_DISP; } else { op->mem.base_reg = M68K_REG_A0 + (instruction & 7); } } else { if (is_pc) { op->mem.base_reg = M68K_REG_PC; op->address_mode = M68K_AM_PCI_INDEX_8_BIT_DISP; } else { op->mem.base_reg = M68K_REG_A0 + (instruction & 7); op->address_mode = M68K_AM_AREGI_INDEX_8_BIT_DISP; } op->mem.disp = (int8_t)(extension & 0xff); } if (EXT_INDEX_SCALE(extension)) { op->mem.scale = 1 << EXT_INDEX_SCALE(extension); } } /* Make string of effective address mode */ static void get_ea_mode_op(m68k_info *info, cs_m68k_op* op, uint32_t instruction, uint32_t size) { // default to memory op->type = M68K_OP_MEM; switch (instruction & 0x3f) { case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: /* data register direct */ op->address_mode = M68K_AM_REG_DIRECT_DATA; op->reg = M68K_REG_D0 + (instruction & 7); op->type = M68K_OP_REG; break; case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /* address register direct */ op->address_mode = M68K_AM_REG_DIRECT_ADDR; op->reg = M68K_REG_A0 + (instruction & 7); op->type = M68K_OP_REG; break; case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* address register indirect */ op->address_mode = M68K_AM_REGI_ADDR; op->reg = M68K_REG_A0 + (instruction & 7); break; case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: /* address register indirect with postincrement */ op->address_mode = M68K_AM_REGI_ADDR_POST_INC; op->reg = M68K_REG_A0 + (instruction & 7); break; case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: /* address register indirect with predecrement */ op->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; op->reg = M68K_REG_A0 + (instruction & 7); break; case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: /* address register indirect with displacement*/ op->address_mode = M68K_AM_REGI_ADDR_DISP; op->mem.base_reg = M68K_REG_A0 + (instruction & 7); op->mem.disp = (int16_t)read_imm_16(info); break; case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: /* address register indirect with index */ get_with_index_address_mode(info, op, instruction, size, false); break; case 0x38: /* absolute short address */ op->address_mode = M68K_AM_ABSOLUTE_DATA_SHORT; op->imm = read_imm_16(info); break; case 0x39: /* absolute long address */ op->address_mode = M68K_AM_ABSOLUTE_DATA_LONG; op->imm = read_imm_32(info); break; case 0x3a: /* program counter with displacement */ op->address_mode = M68K_AM_PCI_DISP; op->mem.disp = (int16_t)read_imm_16(info); break; case 0x3b: /* program counter with index */ get_with_index_address_mode(info, op, instruction, size, true); break; case 0x3c: op->address_mode = M68K_AM_IMMEDIATE; op->type = M68K_OP_IMM; if (size == 1) op->imm = read_imm_8(info) & 0xff; else if (size == 2) op->imm = read_imm_16(info) & 0xffff; else if (size == 4) op->imm = read_imm_32(info); else op->imm = read_imm_64(info); break; default: break; } } static void set_insn_group(m68k_info *info, m68k_group_type group) { info->groups[info->groups_count++] = (uint8_t)group; } static cs_m68k* build_init_op(m68k_info *info, int opcode, int count, int size) { cs_m68k* ext; MCInst_setOpcode(info->inst, opcode); ext = &info->extension; ext->op_count = (uint8_t)count; ext->op_size.type = M68K_SIZE_TYPE_CPU; ext->op_size.cpu_size = size; return ext; } static void build_re_gen_1(m68k_info *info, bool isDreg, int opcode, uint8_t size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; if (isDreg) { op0->address_mode = M68K_AM_REG_DIRECT_DATA; op0->reg = M68K_REG_D0 + ((info->ir >> 9 ) & 7); } else { op0->address_mode = M68K_AM_REG_DIRECT_ADDR; op0->reg = M68K_REG_A0 + ((info->ir >> 9 ) & 7); } get_ea_mode_op(info, op1, info->ir, size); } static void build_re_1(m68k_info *info, int opcode, uint8_t size) { build_re_gen_1(info, true, opcode, size); } static void build_er_gen_1(m68k_info *info, bool isDreg, int opcode, uint8_t size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, size); if (isDreg) { op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); } else { op1->address_mode = M68K_AM_REG_DIRECT_ADDR; op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); } } static void build_rr(m68k_info *info, int opcode, uint8_t size, int imm) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k_op* op2; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op2 = &ext->operands[2]; op0->address_mode = M68K_AM_REG_DIRECT_DATA; op0->reg = M68K_REG_D0 + (info->ir & 7); op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); if (imm > 0) { ext->op_count = 3; op2->type = M68K_OP_IMM; op2->address_mode = M68K_AM_IMMEDIATE; op2->imm = imm; } } static void build_r(m68k_info *info, int opcode, uint8_t size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_REG_DIRECT_DATA; op0->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + (info->ir & 7); } static void build_imm_ea(m68k_info *info, int opcode, uint8_t size, int imm) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->type = M68K_OP_IMM; op0->address_mode = M68K_AM_IMMEDIATE; op0->imm = imm; get_ea_mode_op(info, op1, info->ir, size); } static void build_3bit_d(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->type = M68K_OP_IMM; op0->address_mode = M68K_AM_IMMEDIATE; op0->imm = g_3bit_qdata_table[(info->ir >> 9) & 7]; op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + (info->ir & 7); } static void build_3bit_ea(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->type = M68K_OP_IMM; op0->address_mode = M68K_AM_IMMEDIATE; op0->imm = g_3bit_qdata_table[(info->ir >> 9) & 7]; get_ea_mode_op(info, op1, info->ir, size); } static void build_mm(m68k_info *info, int opcode, uint8_t size, int imm) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k_op* op2; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op2 = &ext->operands[2]; op0->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; op0->reg = M68K_REG_A0 + (info->ir & 7); op1->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); if (imm > 0) { ext->op_count = 3; op2->type = M68K_OP_IMM; op2->address_mode = M68K_AM_IMMEDIATE; op2->imm = imm; } } static void build_ea(m68k_info *info, int opcode, uint8_t size) { cs_m68k* ext = build_init_op(info, opcode, 1, size); get_ea_mode_op(info, &ext->operands[0], info->ir, size); } static void build_ea_a(m68k_info *info, int opcode, uint8_t size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, size); op1->address_mode = M68K_AM_REG_DIRECT_ADDR; op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); } static void build_ea_ea(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, size); get_ea_mode_op(info, op1, (((info->ir>>9) & 7) | ((info->ir>>3) & 0x38)), size); } static void build_pi_pi(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_REGI_ADDR_POST_INC; op0->reg = M68K_REG_A0 + (info->ir & 7); op1->address_mode = M68K_AM_REGI_ADDR_POST_INC; op1->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); } static void build_imm_special_reg(m68k_info *info, int opcode, int imm, int size, m68k_reg reg) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->type = M68K_OP_IMM; op0->address_mode = M68K_AM_IMMEDIATE; op0->imm = imm; op1->address_mode = M68K_AM_NONE; op1->reg = reg; } static void build_relative_branch(m68k_info *info, int opcode, int size, int displacement) { cs_m68k_op* op; cs_m68k* ext = build_init_op(info, opcode, 1, size); op = &ext->operands[0]; op->type = M68K_OP_BR_DISP; op->address_mode = M68K_AM_BRANCH_DISPLACEMENT; op->br_disp.disp = displacement; op->br_disp.disp_size = size; set_insn_group(info, M68K_GRP_JUMP); set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); } static void build_absolute_jump_with_immediate(m68k_info *info, int opcode, int size, int immediate) { cs_m68k_op* op; cs_m68k* ext = build_init_op(info, opcode, 1, size); op = &ext->operands[0]; op->type = M68K_OP_IMM; op->address_mode = M68K_AM_IMMEDIATE; op->imm = immediate; set_insn_group(info, M68K_GRP_JUMP); } static void build_bcc(m68k_info *info, int size, int displacement) { build_relative_branch(info, s_branch_lut[(info->ir >> 8) & 0xf], size, displacement); } static void build_trap(m68k_info *info, int size, int immediate) { build_absolute_jump_with_immediate(info, s_trap_lut[(info->ir >> 8) & 0xf], size, immediate); } static void build_dbxx(m68k_info *info, int opcode, int size, int displacement) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_REG_DIRECT_DATA; op0->reg = M68K_REG_D0 + (info->ir & 7); op1->type = M68K_OP_BR_DISP; op1->address_mode = M68K_AM_BRANCH_DISPLACEMENT; op1->br_disp.disp = displacement; op1->br_disp.disp_size = M68K_OP_BR_DISP_SIZE_LONG; set_insn_group(info, M68K_GRP_JUMP); set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); } static void build_dbcc(m68k_info *info, int size, int displacement) { build_dbxx(info, s_dbcc_lut[(info->ir >> 8) & 0xf], size, displacement); } static void build_d_d_ea(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k_op* op2; uint32_t extension = read_imm_16(info); cs_m68k* ext = build_init_op(info, opcode, 3, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op2 = &ext->operands[2]; op0->address_mode = M68K_AM_REG_DIRECT_DATA; op0->reg = M68K_REG_D0 + (extension & 7); op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + ((extension >> 6) & 7); get_ea_mode_op(info, op2, info->ir, size); } static void build_bitfield_ins(m68k_info *info, int opcode, int has_d_arg) { uint8_t offset; uint8_t width; cs_m68k_op* op_ea; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 1, 0); uint32_t extension = read_imm_16(info); op_ea = &ext->operands[0]; op1 = &ext->operands[1]; if (BIT_B(extension)) offset = (extension >> 6) & 7; else offset = (extension >> 6) & 31; if (BIT_5(extension)) width = extension & 7; else width = (uint8_t)g_5bit_data_table[extension & 31]; if (has_d_arg) { ext->op_count = 2; op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + ((extension >> 12) & 7); } get_ea_mode_op(info, op_ea, info->ir, 1); op_ea->mem.bitfield = 1; op_ea->mem.width = width; op_ea->mem.offset = offset; } static void build_d(m68k_info *info, int opcode, int size) { cs_m68k* ext = build_init_op(info, opcode, 1, size); cs_m68k_op* op; op = &ext->operands[0]; op->address_mode = M68K_AM_REG_DIRECT_DATA; op->reg = M68K_REG_D0 + (info->ir & 7); } static uint16_t reverse_bits(uint32_t v) { uint32_t r = v; // r will be reversed bits of v; first get LSB of v uint32_t s = 16 - 1; // extra shift needed at end for (v >>= 1; v; v >>= 1) { r <<= 1; r |= v & 1; s--; } return r <<= s; // shift when v's highest bits are zero } static uint8_t reverse_bits_8(uint32_t v) { uint32_t r = v; // r will be reversed bits of v; first get LSB of v uint32_t s = 8 - 1; // extra shift needed at end for (v >>= 1; v; v >>= 1) { r <<= 1; r |= v & 1; s--; } return r <<= s; // shift when v's highest bits are zero } static void build_movem_re(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->type = M68K_OP_REG_BITS; op0->register_bits = read_imm_16(info); get_ea_mode_op(info, op1, info->ir, size); if (op1->address_mode == M68K_AM_REGI_ADDR_PRE_DEC) op0->register_bits = reverse_bits(op0->register_bits); } static void build_movem_er(m68k_info *info, int opcode, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, opcode, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op1->type = M68K_OP_REG_BITS; op1->register_bits = read_imm_16(info); get_ea_mode_op(info, op0, info->ir, size); } static void build_imm(m68k_info *info, int opcode, int data) { cs_m68k_op* op; cs_m68k* ext = build_init_op(info, opcode, 1, 0); MCInst_setOpcode(info->inst, opcode); op = &ext->operands[0]; op->type = M68K_OP_IMM; op->address_mode = M68K_AM_IMMEDIATE; op->imm = data; } static void build_illegal(m68k_info *info, int data) { build_imm(info, M68K_INS_ILLEGAL, data); } static void build_invalid(m68k_info *info, int data) { build_imm(info, M68K_INS_INVALID, data); } static void build_cas2(m68k_info *info, int size) { uint32_t word3; uint32_t extension; cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k_op* op2; cs_m68k* ext = build_init_op(info, M68K_INS_CAS2, 3, size); int reg_0, reg_1; /* cas2 is the only 3 words instruction, word2 and word3 have the same motif bits to check */ word3 = peek_imm_32(info) & 0xffff; if (!instruction_is_valid(info, word3)) return; op0 = &ext->operands[0]; op1 = &ext->operands[1]; op2 = &ext->operands[2]; extension = read_imm_32(info); op0->address_mode = M68K_AM_NONE; op0->type = M68K_OP_REG_PAIR; op0->reg_pair.reg_0 = ((extension >> 16) & 7) + M68K_REG_D0; op0->reg_pair.reg_1 = (extension & 7) + M68K_REG_D0; op1->address_mode = M68K_AM_NONE; op1->type = M68K_OP_REG_PAIR; op1->reg_pair.reg_0 = ((extension >> 22) & 7) + M68K_REG_D0; op1->reg_pair.reg_1 = ((extension >> 6) & 7) + M68K_REG_D0; reg_0 = (extension >> 28) & 7; reg_1 = (extension >> 12) & 7; op2->address_mode = M68K_AM_NONE; op2->type = M68K_OP_REG_PAIR; op2->reg_pair.reg_0 = reg_0 + (BIT_1F(extension) ? 8 : 0) + M68K_REG_D0; op2->reg_pair.reg_1 = reg_1 + (BIT_F(extension) ? 8 : 0) + M68K_REG_D0; } static void build_chk2_cmp2(m68k_info *info, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_CHK2, 2, size); uint32_t extension = read_imm_16(info); if (BIT_B(extension)) MCInst_setOpcode(info->inst, M68K_INS_CHK2); else MCInst_setOpcode(info->inst, M68K_INS_CMP2); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, size); op1->address_mode = M68K_AM_NONE; op1->type = M68K_OP_REG; op1->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); } static void build_move16(m68k_info *info, int data[2], int modes[2]) { cs_m68k* ext = build_init_op(info, M68K_INS_MOVE16, 2, 0); int i; for (i = 0; i < 2; ++i) { cs_m68k_op* op = &ext->operands[i]; const int d = data[i]; const int m = modes[i]; op->type = M68K_OP_MEM; if (m == M68K_AM_REGI_ADDR_POST_INC || m == M68K_AM_REG_DIRECT_ADDR) { op->address_mode = m; op->reg = M68K_REG_A0 + d; } else { op->address_mode = m; op->imm = d; } } } static void build_link(m68k_info *info, int disp, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_LINK, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_A0 + (info->ir & 7); op1->address_mode = M68K_AM_IMMEDIATE; op1->type = M68K_OP_IMM; op1->imm = disp; } static void build_cpush_cinv(m68k_info *info, int op_offset) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_INVALID, 2, 0); switch ((info->ir >> 3) & 3) { // scope // Invalid case 0: d68000_invalid(info); return; // Line case 1: MCInst_setOpcode(info->inst, op_offset + 0); break; // Page case 2: MCInst_setOpcode(info->inst, op_offset + 1); break; // All case 3: ext->op_count = 1; MCInst_setOpcode(info->inst, op_offset + 2); break; } op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_IMMEDIATE; op0->type = M68K_OP_IMM; op0->imm = (info->ir >> 6) & 3; op1->type = M68K_OP_MEM; op1->address_mode = M68K_AM_REG_DIRECT_ADDR; op1->imm = M68K_REG_A0 + (info->ir & 7); } static void build_movep_re(m68k_info *info, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVEP, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); op1->address_mode = M68K_AM_REGI_ADDR_DISP; op1->type = M68K_OP_MEM; op1->mem.base_reg = M68K_REG_A0 + (info->ir & 7); op1->mem.disp = (int16_t)read_imm_16(info); } static void build_movep_er(m68k_info *info, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVEP, 2, size); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_REGI_ADDR_DISP; op0->type = M68K_OP_MEM; op0->mem.base_reg = M68K_REG_A0 + (info->ir & 7); op0->mem.disp = (int16_t)read_imm_16(info); op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); } static void build_moves(m68k_info *info, int size) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVES, 2, size); uint32_t extension = read_imm_16(info); op0 = &ext->operands[0]; op1 = &ext->operands[1]; if (BIT_B(extension)) { op0->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); get_ea_mode_op(info, op1, info->ir, size); } else { get_ea_mode_op(info, op0, info->ir, size); op1->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); } } static void build_er_1(m68k_info *info, int opcode, uint8_t size) { build_er_gen_1(info, true, opcode, size); } /* ======================================================================== */ /* ========================= INSTRUCTION HANDLERS ========================= */ /* ======================================================================== */ /* Instruction handler function names follow this convention: * * d68000_NAME_EXTENSIONS(void) * where NAME is the name of the opcode it handles and EXTENSIONS are any * extensions for special instances of that opcode. * * Examples: * d68000_add_er_8(): add opcode, from effective address to register, * size = byte * * d68000_asr_s_8(): arithmetic shift right, static count, size = byte * * * Common extensions: * 8 : size = byte * 16 : size = word * 32 : size = long * rr : register to register * mm : memory to memory * r : register * s : static * er : effective address -> register * re : register -> effective address * ea : using effective address mode of operation * d : data register direct * a : address register direct * ai : address register indirect * pi : address register indirect with postincrement * pd : address register indirect with predecrement * di : address register indirect with displacement * ix : address register indirect with index * aw : absolute word * al : absolute long */ static void d68000_invalid(m68k_info *info) { build_invalid(info, info->ir); } static void d68000_illegal(m68k_info *info) { build_illegal(info, info->ir); } static void d68000_1010(m68k_info *info) { build_invalid(info, info->ir); } static void d68000_1111(m68k_info *info) { build_invalid(info, info->ir); } static void d68000_abcd_rr(m68k_info *info) { build_rr(info, M68K_INS_ABCD, 1, 0); } static void d68000_abcd_mm(m68k_info *info) { build_mm(info, M68K_INS_ABCD, 1, 0); } static void d68000_add_er_8(m68k_info *info) { build_er_1(info, M68K_INS_ADD, 1); } static void d68000_add_er_16(m68k_info *info) { build_er_1(info, M68K_INS_ADD, 2); } static void d68000_add_er_32(m68k_info *info) { build_er_1(info, M68K_INS_ADD, 4); } static void d68000_add_re_8(m68k_info *info) { build_re_1(info, M68K_INS_ADD, 1); } static void d68000_add_re_16(m68k_info *info) { build_re_1(info, M68K_INS_ADD, 2); } static void d68000_add_re_32(m68k_info *info) { build_re_1(info, M68K_INS_ADD, 4); } static void d68000_adda_16(m68k_info *info) { build_ea_a(info, M68K_INS_ADDA, 2); } static void d68000_adda_32(m68k_info *info) { build_ea_a(info, M68K_INS_ADDA, 4); } static void d68000_addi_8(m68k_info *info) { build_imm_ea(info, M68K_INS_ADDI, 1, read_imm_8(info)); } static void d68000_addi_16(m68k_info *info) { build_imm_ea(info, M68K_INS_ADDI, 2, read_imm_16(info)); } static void d68000_addi_32(m68k_info *info) { build_imm_ea(info, M68K_INS_ADDI, 4, read_imm_32(info)); } static void d68000_addq_8(m68k_info *info) { build_3bit_ea(info, M68K_INS_ADDQ, 1); } static void d68000_addq_16(m68k_info *info) { build_3bit_ea(info, M68K_INS_ADDQ, 2); } static void d68000_addq_32(m68k_info *info) { build_3bit_ea(info, M68K_INS_ADDQ, 4); } static void d68000_addx_rr_8(m68k_info *info) { build_rr(info, M68K_INS_ADDX, 1, 0); } static void d68000_addx_rr_16(m68k_info *info) { build_rr(info, M68K_INS_ADDX, 2, 0); } static void d68000_addx_rr_32(m68k_info *info) { build_rr(info, M68K_INS_ADDX, 4, 0); } static void d68000_addx_mm_8(m68k_info *info) { build_mm(info, M68K_INS_ADDX, 1, 0); } static void d68000_addx_mm_16(m68k_info *info) { build_mm(info, M68K_INS_ADDX, 2, 0); } static void d68000_addx_mm_32(m68k_info *info) { build_mm(info, M68K_INS_ADDX, 4, 0); } static void d68000_and_er_8(m68k_info *info) { build_er_1(info, M68K_INS_AND, 1); } static void d68000_and_er_16(m68k_info *info) { build_er_1(info, M68K_INS_AND, 2); } static void d68000_and_er_32(m68k_info *info) { build_er_1(info, M68K_INS_AND, 4); } static void d68000_and_re_8(m68k_info *info) { build_re_1(info, M68K_INS_AND, 1); } static void d68000_and_re_16(m68k_info *info) { build_re_1(info, M68K_INS_AND, 2); } static void d68000_and_re_32(m68k_info *info) { build_re_1(info, M68K_INS_AND, 4); } static void d68000_andi_8(m68k_info *info) { build_imm_ea(info, M68K_INS_ANDI, 1, read_imm_8(info)); } static void d68000_andi_16(m68k_info *info) { build_imm_ea(info, M68K_INS_ANDI, 2, read_imm_16(info)); } static void d68000_andi_32(m68k_info *info) { build_imm_ea(info, M68K_INS_ANDI, 4, read_imm_32(info)); } static void d68000_andi_to_ccr(m68k_info *info) { build_imm_special_reg(info, M68K_INS_ANDI, read_imm_8(info), 1, M68K_REG_CCR); } static void d68000_andi_to_sr(m68k_info *info) { build_imm_special_reg(info, M68K_INS_ANDI, read_imm_16(info), 2, M68K_REG_SR); } static void d68000_asr_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ASR, 1); } static void d68000_asr_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_ASR, 2); } static void d68000_asr_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_ASR, 4); } static void d68000_asr_r_8(m68k_info *info) { build_r(info, M68K_INS_ASR, 1); } static void d68000_asr_r_16(m68k_info *info) { build_r(info, M68K_INS_ASR, 2); } static void d68000_asr_r_32(m68k_info *info) { build_r(info, M68K_INS_ASR, 4); } static void d68000_asr_ea(m68k_info *info) { build_ea(info, M68K_INS_ASR, 2); } static void d68000_asl_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ASL, 1); } static void d68000_asl_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_ASL, 2); } static void d68000_asl_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_ASL, 4); } static void d68000_asl_r_8(m68k_info *info) { build_r(info, M68K_INS_ASL, 1); } static void d68000_asl_r_16(m68k_info *info) { build_r(info, M68K_INS_ASL, 2); } static void d68000_asl_r_32(m68k_info *info) { build_r(info, M68K_INS_ASL, 4); } static void d68000_asl_ea(m68k_info *info) { build_ea(info, M68K_INS_ASL, 2); } static void d68000_bcc_8(m68k_info *info) { build_bcc(info, 1, make_int_8(info->ir)); } static void d68000_bcc_16(m68k_info *info) { build_bcc(info, 2, make_int_16(read_imm_16(info))); } static void d68020_bcc_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bcc(info, 4, read_imm_32(info)); } static void d68000_bchg_r(m68k_info *info) { build_re_1(info, M68K_INS_BCHG, 1); } static void d68000_bchg_s(m68k_info *info) { build_imm_ea(info, M68K_INS_BCHG, 1, read_imm_8(info)); } static void d68000_bclr_r(m68k_info *info) { build_re_1(info, M68K_INS_BCLR, 1); } static void d68000_bclr_s(m68k_info *info) { build_imm_ea(info, M68K_INS_BCLR, 1, read_imm_8(info)); } static void d68010_bkpt(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_absolute_jump_with_immediate(info, M68K_INS_BKPT, 0, info->ir & 7); } static void d68020_bfchg(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFCHG, false); } static void d68020_bfclr(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFCLR, false); } static void d68020_bfexts(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFEXTS, true); } static void d68020_bfextu(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFEXTU, true); } static void d68020_bfffo(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFFFO, true); } static void d68020_bfins(m68k_info *info) { cs_m68k* ext = &info->extension; cs_m68k_op temp; LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFINS, true); // a bit hacky but we need to flip the args on only this instruction temp = ext->operands[0]; ext->operands[0] = ext->operands[1]; ext->operands[1] = temp; } static void d68020_bfset(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_bitfield_ins(info, M68K_INS_BFSET, false); } static void d68020_bftst(m68k_info *info) { build_bitfield_ins(info, M68K_INS_BFTST, false); } static void d68000_bra_8(m68k_info *info) { build_relative_branch(info, M68K_INS_BRA, 1, make_int_8(info->ir)); } static void d68000_bra_16(m68k_info *info) { build_relative_branch(info, M68K_INS_BRA, 2, make_int_16(read_imm_16(info))); } static void d68020_bra_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_relative_branch(info, M68K_INS_BRA, 4, read_imm_32(info)); } static void d68000_bset_r(m68k_info *info) { build_re_1(info, M68K_INS_BSET, 1); } static void d68000_bset_s(m68k_info *info) { build_imm_ea(info, M68K_INS_BSET, 1, read_imm_8(info)); } static void d68000_bsr_8(m68k_info *info) { build_relative_branch(info, M68K_INS_BSR, 1, make_int_8(info->ir)); } static void d68000_bsr_16(m68k_info *info) { build_relative_branch(info, M68K_INS_BSR, 2, make_int_16(read_imm_16(info))); } static void d68020_bsr_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_relative_branch(info, M68K_INS_BSR, 4, read_imm_32(info)); } static void d68000_btst_r(m68k_info *info) { build_re_1(info, M68K_INS_BTST, 4); } static void d68000_btst_s(m68k_info *info) { build_imm_ea(info, M68K_INS_BTST, 1, read_imm_8(info)); } static void d68020_callm(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_ONLY); build_imm_ea(info, M68K_INS_CALLM, 0, read_imm_8(info)); } static void d68020_cas_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_d_d_ea(info, M68K_INS_CAS, 1); } static void d68020_cas_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_d_d_ea(info, M68K_INS_CAS, 2); } static void d68020_cas_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_d_d_ea(info, M68K_INS_CAS, 4); } static void d68020_cas2_16(m68k_info *info) { build_cas2(info, 2); } static void d68020_cas2_32(m68k_info *info) { build_cas2(info, 4); } static void d68000_chk_16(m68k_info *info) { build_er_1(info, M68K_INS_CHK, 2); } static void d68020_chk_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_er_1(info, M68K_INS_CHK, 4); } static void d68020_chk2_cmp2_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_chk2_cmp2(info, 1); } static void d68020_chk2_cmp2_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_chk2_cmp2(info, 2); } static void d68020_chk2_cmp2_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_chk2_cmp2(info, 4); } static void d68040_cinv(m68k_info *info) { LIMIT_CPU_TYPES(info, M68040_PLUS); build_cpush_cinv(info, M68K_INS_CINVL); } static void d68000_clr_8(m68k_info *info) { build_ea(info, M68K_INS_CLR, 1); } static void d68000_clr_16(m68k_info *info) { build_ea(info, M68K_INS_CLR, 2); } static void d68000_clr_32(m68k_info *info) { build_ea(info, M68K_INS_CLR, 4); } static void d68000_cmp_8(m68k_info *info) { build_er_1(info, M68K_INS_CMP, 1); } static void d68000_cmp_16(m68k_info *info) { build_er_1(info, M68K_INS_CMP, 2); } static void d68000_cmp_32(m68k_info *info) { build_er_1(info, M68K_INS_CMP, 4); } static void d68000_cmpa_16(m68k_info *info) { build_ea_a(info, M68K_INS_CMPA, 2); } static void d68000_cmpa_32(m68k_info *info) { build_ea_a(info, M68K_INS_CMPA, 4); } static void d68000_cmpi_8(m68k_info *info) { build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); } static void d68020_cmpi_pcdi_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); } static void d68020_cmpi_pcix_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); } static void d68000_cmpi_16(m68k_info *info) { build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); } static void d68020_cmpi_pcdi_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); } static void d68020_cmpi_pcix_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); } static void d68000_cmpi_32(m68k_info *info) { build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); } static void d68020_cmpi_pcdi_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); } static void d68020_cmpi_pcix_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); } static void d68000_cmpm_8(m68k_info *info) { build_pi_pi(info, M68K_INS_CMPM, 1); } static void d68000_cmpm_16(m68k_info *info) { build_pi_pi(info, M68K_INS_CMPM, 2); } static void d68000_cmpm_32(m68k_info *info) { build_pi_pi(info, M68K_INS_CMPM, 4); } static void make_cpbcc_operand(cs_m68k_op* op, int size, int displacement) { op->address_mode = M68K_AM_BRANCH_DISPLACEMENT; op->type = M68K_OP_BR_DISP; op->br_disp.disp = displacement; op->br_disp.disp_size = size; } static void d68020_cpbcc_16(m68k_info *info) { cs_m68k_op* op0; cs_m68k* ext; LIMIT_CPU_TYPES(info, M68020_PLUS); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (info->ir & 0x2f); ext = build_init_op(info, M68K_INS_FBF, 1, 2); op0 = &ext->operands[0]; make_cpbcc_operand(op0, M68K_OP_BR_DISP_SIZE_WORD, make_int_16(read_imm_16(info))); set_insn_group(info, M68K_GRP_JUMP); set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); } static void d68020_cpbcc_32(m68k_info *info) { cs_m68k* ext; cs_m68k_op* op0; LIMIT_CPU_TYPES(info, M68020_PLUS); LIMIT_CPU_TYPES(info, M68020_PLUS); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (info->ir & 0x2f); ext = build_init_op(info, M68K_INS_FBF, 1, 4); op0 = &ext->operands[0]; make_cpbcc_operand(op0, M68K_OP_BR_DISP_SIZE_LONG, read_imm_32(info)); set_insn_group(info, M68K_GRP_JUMP); set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); } static void d68020_cpdbcc(m68k_info *info) { cs_m68k* ext; cs_m68k_op* op0; cs_m68k_op* op1; uint32_t ext1, ext2; LIMIT_CPU_TYPES(info, M68020_PLUS); ext1 = read_imm_16(info); ext2 = read_imm_16(info); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (ext1 & 0x2f); ext = build_init_op(info, M68K_INS_FDBF, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->reg = M68K_REG_D0 + (info->ir & 7); make_cpbcc_operand(op1, M68K_OP_BR_DISP_SIZE_WORD, make_int_16(ext2) + 2); set_insn_group(info, M68K_GRP_JUMP); set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); } static void fmove_fpcr(m68k_info *info, uint32_t extension) { cs_m68k_op* special; cs_m68k_op* op_ea; int regsel = (extension >> 10) & 0x7; int dir = (extension >> 13) & 0x1; cs_m68k* ext = build_init_op(info, M68K_INS_FMOVE, 2, 4); special = &ext->operands[0]; op_ea = &ext->operands[1]; if (!dir) { cs_m68k_op* t = special; special = op_ea; op_ea = t; } get_ea_mode_op(info, op_ea, info->ir, 4); if (regsel & 4) special->reg = M68K_REG_FPCR; else if (regsel & 2) special->reg = M68K_REG_FPSR; else if (regsel & 1) special->reg = M68K_REG_FPIAR; } static void fmovem(m68k_info *info, uint32_t extension) { cs_m68k_op* op_reglist; cs_m68k_op* op_ea; int dir = (extension >> 13) & 0x1; int mode = (extension >> 11) & 0x3; uint32_t reglist = extension & 0xff; cs_m68k* ext = build_init_op(info, M68K_INS_FMOVEM, 2, 0); op_reglist = &ext->operands[0]; op_ea = &ext->operands[1]; // flip args around if (!dir) { cs_m68k_op* t = op_reglist; op_reglist = op_ea; op_ea = t; } get_ea_mode_op(info, op_ea, info->ir, 0); switch (mode) { case 1 : // Dynamic list in dn register op_reglist->reg = M68K_REG_D0 + ((reglist >> 4) & 7); break; case 0 : op_reglist->address_mode = M68K_AM_NONE; op_reglist->type = M68K_OP_REG_BITS; op_reglist->register_bits = reglist << 16; break; case 2 : // Static list op_reglist->address_mode = M68K_AM_NONE; op_reglist->type = M68K_OP_REG_BITS; op_reglist->register_bits = ((uint32_t)reverse_bits_8(reglist)) << 16; break; } } static void d68020_cpgen(m68k_info *info) { cs_m68k *ext; cs_m68k_op* op0; cs_m68k_op* op1; bool supports_single_op; uint32_t next; int rm, src, dst, opmode; LIMIT_CPU_TYPES(info, M68020_PLUS); supports_single_op = true; next = read_imm_16(info); rm = (next >> 14) & 0x1; src = (next >> 10) & 0x7; dst = (next >> 7) & 0x7; opmode = next & 0x3f; // special handling for fmovecr if (BITFIELD(info->ir, 5, 0) == 0 && BITFIELD(next, 15, 10) == 0x17) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_FMOVECR, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_IMMEDIATE; op0->type = M68K_OP_IMM; op0->imm = next & 0x3f; op1->reg = M68K_REG_FP0 + ((next >> 7) & 7); return; } // deal with extended move stuff switch ((next >> 13) & 0x7) { // fmovem fpcr case 0x4: // FMOVEM ea, FPCR case 0x5: // FMOVEM FPCR, ea fmove_fpcr(info, next); return; // fmovem list case 0x6: case 0x7: fmovem(info, next); return; } // See comment bellow on why this is being done if ((next >> 6) & 1) opmode &= ~4; // special handling of some instructions here switch (opmode) { case 0x00: MCInst_setOpcode(info->inst, M68K_INS_FMOVE); supports_single_op = false; break; case 0x01: MCInst_setOpcode(info->inst, M68K_INS_FINT); break; case 0x02: MCInst_setOpcode(info->inst, M68K_INS_FSINH); break; case 0x03: MCInst_setOpcode(info->inst, M68K_INS_FINTRZ); break; case 0x04: MCInst_setOpcode(info->inst, M68K_INS_FSQRT); break; case 0x06: MCInst_setOpcode(info->inst, M68K_INS_FLOGNP1); break; case 0x08: MCInst_setOpcode(info->inst, M68K_INS_FETOXM1); break; case 0x09: MCInst_setOpcode(info->inst, M68K_INS_FATANH); break; case 0x0a: MCInst_setOpcode(info->inst, M68K_INS_FATAN); break; case 0x0c: MCInst_setOpcode(info->inst, M68K_INS_FASIN); break; case 0x0d: MCInst_setOpcode(info->inst, M68K_INS_FATANH); break; case 0x0e: MCInst_setOpcode(info->inst, M68K_INS_FSIN); break; case 0x0f: MCInst_setOpcode(info->inst, M68K_INS_FTAN); break; case 0x10: MCInst_setOpcode(info->inst, M68K_INS_FETOX); break; case 0x11: MCInst_setOpcode(info->inst, M68K_INS_FTWOTOX); break; case 0x12: MCInst_setOpcode(info->inst, M68K_INS_FTENTOX); break; case 0x14: MCInst_setOpcode(info->inst, M68K_INS_FLOGN); break; case 0x15: MCInst_setOpcode(info->inst, M68K_INS_FLOG10); break; case 0x16: MCInst_setOpcode(info->inst, M68K_INS_FLOG2); break; case 0x18: MCInst_setOpcode(info->inst, M68K_INS_FABS); break; case 0x19: MCInst_setOpcode(info->inst, M68K_INS_FCOSH); break; case 0x1a: MCInst_setOpcode(info->inst, M68K_INS_FNEG); break; case 0x1c: MCInst_setOpcode(info->inst, M68K_INS_FACOS); break; case 0x1d: MCInst_setOpcode(info->inst, M68K_INS_FCOS); break; case 0x1e: MCInst_setOpcode(info->inst, M68K_INS_FGETEXP); break; case 0x1f: MCInst_setOpcode(info->inst, M68K_INS_FGETMAN); break; case 0x20: MCInst_setOpcode(info->inst, M68K_INS_FDIV); supports_single_op = false; break; case 0x21: MCInst_setOpcode(info->inst, M68K_INS_FMOD); supports_single_op = false; break; case 0x22: MCInst_setOpcode(info->inst, M68K_INS_FADD); supports_single_op = false; break; case 0x23: MCInst_setOpcode(info->inst, M68K_INS_FMUL); supports_single_op = false; break; case 0x24: MCInst_setOpcode(info->inst, M68K_INS_FSGLDIV); supports_single_op = false; break; case 0x25: MCInst_setOpcode(info->inst, M68K_INS_FREM); break; case 0x26: MCInst_setOpcode(info->inst, M68K_INS_FSCALE); break; case 0x27: MCInst_setOpcode(info->inst, M68K_INS_FSGLMUL); break; case 0x28: MCInst_setOpcode(info->inst, M68K_INS_FSUB); supports_single_op = false; break; case 0x38: MCInst_setOpcode(info->inst, M68K_INS_FCMP); supports_single_op = false; break; case 0x3a: MCInst_setOpcode(info->inst, M68K_INS_FTST); break; default: break; } // Some trickery here! It's not documented but if bit 6 is set this is a s/d opcode and then // if bit 2 is set it's a d. As we already have set our opcode in the code above we can just // offset it as the following 2 op codes (if s/d is supported) will always be directly after it if ((next >> 6) & 1) { if ((next >> 2) & 1) info->inst->Opcode += 2; else info->inst->Opcode += 1; } ext = &info->extension; ext->op_count = 2; ext->op_size.type = M68K_SIZE_TYPE_CPU; ext->op_size.cpu_size = 0; // Special case - adjust direction of fmove if ((opmode == 0x00) && ((next >> 13) & 0x1) != 0) { op0 = &ext->operands[1]; op1 = &ext->operands[0]; } else { op0 = &ext->operands[0]; op1 = &ext->operands[1]; } if (rm == 0 && supports_single_op && src == dst) { ext->op_count = 1; op0->reg = M68K_REG_FP0 + dst; return; } if (rm == 1) { switch (src) { case 0x00 : ext->op_size.cpu_size = M68K_CPU_SIZE_LONG; get_ea_mode_op(info, op0, info->ir, 4); break; case 0x06 : ext->op_size.cpu_size = M68K_CPU_SIZE_BYTE; get_ea_mode_op(info, op0, info->ir, 1); break; case 0x04 : ext->op_size.cpu_size = M68K_CPU_SIZE_WORD; get_ea_mode_op(info, op0, info->ir, 2); break; case 0x01 : ext->op_size.type = M68K_SIZE_TYPE_FPU; ext->op_size.fpu_size = M68K_FPU_SIZE_SINGLE; get_ea_mode_op(info, op0, info->ir, 4); op0->type = M68K_OP_FP_SINGLE; break; case 0x05: ext->op_size.type = M68K_SIZE_TYPE_FPU; ext->op_size.fpu_size = M68K_FPU_SIZE_DOUBLE; get_ea_mode_op(info, op0, info->ir, 8); op0->type = M68K_OP_FP_DOUBLE; break; default : ext->op_size.type = M68K_SIZE_TYPE_FPU; ext->op_size.fpu_size = M68K_FPU_SIZE_EXTENDED; break; } } else { op0->reg = M68K_REG_FP0 + src; } op1->reg = M68K_REG_FP0 + dst; } static void d68020_cprestore(m68k_info *info) { cs_m68k* ext; LIMIT_CPU_TYPES(info, M68020_PLUS); ext = build_init_op(info, M68K_INS_FRESTORE, 1, 0); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); } static void d68020_cpsave(m68k_info *info) { cs_m68k* ext; LIMIT_CPU_TYPES(info, M68020_PLUS); ext = build_init_op(info, M68K_INS_FSAVE, 1, 0); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); } static void d68020_cpscc(m68k_info *info) { cs_m68k* ext; LIMIT_CPU_TYPES(info, M68020_PLUS); ext = build_init_op(info, M68K_INS_FSF, 1, 1); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (read_imm_16(info) & 0x2f); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); } static void d68020_cptrapcc_0(m68k_info *info) { uint32_t extension1; LIMIT_CPU_TYPES(info, M68020_PLUS); extension1 = read_imm_16(info); build_init_op(info, M68K_INS_FTRAPF, 0, 0); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (extension1 & 0x2f); } static void d68020_cptrapcc_16(m68k_info *info) { uint32_t extension1, extension2; cs_m68k_op* op0; cs_m68k* ext; LIMIT_CPU_TYPES(info, M68020_PLUS); extension1 = read_imm_16(info); extension2 = read_imm_16(info); ext = build_init_op(info, M68K_INS_FTRAPF, 1, 2); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (extension1 & 0x2f); op0 = &ext->operands[0]; op0->address_mode = M68K_AM_IMMEDIATE; op0->type = M68K_OP_IMM; op0->imm = extension2; } static void d68020_cptrapcc_32(m68k_info *info) { uint32_t extension1, extension2; cs_m68k* ext; cs_m68k_op* op0; LIMIT_CPU_TYPES(info, M68020_PLUS); extension1 = read_imm_16(info); extension2 = read_imm_32(info); ext = build_init_op(info, M68K_INS_FTRAPF, 1, 2); // these are all in row with the extension so just doing a add here is fine info->inst->Opcode += (extension1 & 0x2f); op0 = &ext->operands[0]; op0->address_mode = M68K_AM_IMMEDIATE; op0->type = M68K_OP_IMM; op0->imm = extension2; } static void d68040_cpush(m68k_info *info) { LIMIT_CPU_TYPES(info, M68040_PLUS); build_cpush_cinv(info, M68K_INS_CPUSHL); } static void d68000_dbra(m68k_info *info) { build_dbxx(info, M68K_INS_DBRA, 0, make_int_16(read_imm_16(info))); } static void d68000_dbcc(m68k_info *info) { build_dbcc(info, 0, make_int_16(read_imm_16(info))); } static void d68000_divs(m68k_info *info) { build_er_1(info, M68K_INS_DIVS, 2); } static void d68000_divu(m68k_info *info) { build_er_1(info, M68K_INS_DIVU, 2); } static void d68020_divl(m68k_info *info) { uint32_t extension, insn_signed; cs_m68k* ext; cs_m68k_op* op0; cs_m68k_op* op1; uint32_t reg_0, reg_1; LIMIT_CPU_TYPES(info, M68020_PLUS); extension = read_imm_16(info); insn_signed = 0; if (BIT_B((extension))) insn_signed = 1; ext = build_init_op(info, insn_signed ? M68K_INS_DIVS : M68K_INS_DIVU, 2, 4); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, 4); reg_0 = extension & 7; reg_1 = (extension >> 12) & 7; op1->address_mode = M68K_AM_NONE; op1->type = M68K_OP_REG_PAIR; op1->reg_pair.reg_0 = reg_0 + M68K_REG_D0; op1->reg_pair.reg_1 = reg_1 + M68K_REG_D0; if ((reg_0 == reg_1) || !BIT_A(extension)) { op1->type = M68K_OP_REG; op1->reg = M68K_REG_D0 + reg_1; } } static void d68000_eor_8(m68k_info *info) { build_re_1(info, M68K_INS_EOR, 1); } static void d68000_eor_16(m68k_info *info) { build_re_1(info, M68K_INS_EOR, 2); } static void d68000_eor_32(m68k_info *info) { build_re_1(info, M68K_INS_EOR, 4); } static void d68000_eori_8(m68k_info *info) { build_imm_ea(info, M68K_INS_EORI, 1, read_imm_8(info)); } static void d68000_eori_16(m68k_info *info) { build_imm_ea(info, M68K_INS_EORI, 2, read_imm_16(info)); } static void d68000_eori_32(m68k_info *info) { build_imm_ea(info, M68K_INS_EORI, 4, read_imm_32(info)); } static void d68000_eori_to_ccr(m68k_info *info) { build_imm_special_reg(info, M68K_INS_EORI, read_imm_8(info), 1, M68K_REG_CCR); } static void d68000_eori_to_sr(m68k_info *info) { build_imm_special_reg(info, M68K_INS_EORI, read_imm_16(info), 2, M68K_REG_SR); } static void d68000_exg_dd(m68k_info *info) { build_r(info, M68K_INS_EXG, 4); } static void d68000_exg_aa(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_EXG, 2, 4); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_A0 + ((info->ir >> 9) & 7); op1->address_mode = M68K_AM_NONE; op1->reg = M68K_REG_A0 + (info->ir & 7); } static void d68000_exg_da(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_EXG, 2, 4); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); op1->address_mode = M68K_AM_NONE; op1->reg = M68K_REG_A0 + (info->ir & 7); } static void d68000_ext_16(m68k_info *info) { build_d(info, M68K_INS_EXT, 2); } static void d68000_ext_32(m68k_info *info) { build_d(info, M68K_INS_EXT, 4); } static void d68020_extb_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_d(info, M68K_INS_EXTB, 4); } static void d68000_jmp(m68k_info *info) { cs_m68k* ext = build_init_op(info, M68K_INS_JMP, 1, 0); set_insn_group(info, M68K_GRP_JUMP); get_ea_mode_op(info, &ext->operands[0], info->ir, 4); } static void d68000_jsr(m68k_info *info) { cs_m68k* ext = build_init_op(info, M68K_INS_JSR, 1, 0); set_insn_group(info, M68K_GRP_JUMP); get_ea_mode_op(info, &ext->operands[0], info->ir, 4); } static void d68000_lea(m68k_info *info) { build_ea_a(info, M68K_INS_LEA, 4); } static void d68000_link_16(m68k_info *info) { build_link(info, read_imm_16(info), 2); } static void d68020_link_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_link(info, read_imm_32(info), 4); } static void d68000_lsr_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_LSR, 1); } static void d68000_lsr_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_LSR, 2); } static void d68000_lsr_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_LSR, 4); } static void d68000_lsr_r_8(m68k_info *info) { build_r(info, M68K_INS_LSR, 1); } static void d68000_lsr_r_16(m68k_info *info) { build_r(info, M68K_INS_LSR, 2); } static void d68000_lsr_r_32(m68k_info *info) { build_r(info, M68K_INS_LSR, 4); } static void d68000_lsr_ea(m68k_info *info) { build_ea(info, M68K_INS_LSR, 2); } static void d68000_lsl_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_LSL, 1); } static void d68000_lsl_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_LSL, 2); } static void d68000_lsl_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_LSL, 4); } static void d68000_lsl_r_8(m68k_info *info) { build_r(info, M68K_INS_LSL, 1); } static void d68000_lsl_r_16(m68k_info *info) { build_r(info, M68K_INS_LSL, 2); } static void d68000_lsl_r_32(m68k_info *info) { build_r(info, M68K_INS_LSL, 4); } static void d68000_lsl_ea(m68k_info *info) { build_ea(info, M68K_INS_LSL, 2); } static void d68000_move_8(m68k_info *info) { build_ea_ea(info, M68K_INS_MOVE, 1); } static void d68000_move_16(m68k_info *info) { build_ea_ea(info, M68K_INS_MOVE, 2); } static void d68000_move_32(m68k_info *info) { build_ea_ea(info, M68K_INS_MOVE, 4); } static void d68000_movea_16(m68k_info *info) { build_ea_a(info, M68K_INS_MOVEA, 2); } static void d68000_movea_32(m68k_info *info) { build_ea_a(info, M68K_INS_MOVEA, 4); } static void d68000_move_to_ccr(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, 1); op1->address_mode = M68K_AM_NONE; op1->reg = M68K_REG_CCR; } static void d68010_move_fr_ccr(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext; LIMIT_CPU_TYPES(info, M68010_PLUS); ext = build_init_op(info, M68K_INS_MOVE, 2, 2); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_CCR; get_ea_mode_op(info, op1, info->ir, 1); } static void d68000_move_fr_sr(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_SR; get_ea_mode_op(info, op1, info->ir, 2); } static void d68000_move_to_sr(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 2); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, 2); op1->address_mode = M68K_AM_NONE; op1->reg = M68K_REG_SR; } static void d68000_move_fr_usp(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_USP; op1->address_mode = M68K_AM_NONE; op1->reg = M68K_REG_A0 + (info->ir & 7); } static void d68000_move_to_usp(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVE, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->address_mode = M68K_AM_NONE; op0->reg = M68K_REG_A0 + (info->ir & 7); op1->address_mode = M68K_AM_NONE; op1->reg = M68K_REG_USP; } static void d68010_movec(m68k_info *info) { uint32_t extension; m68k_reg reg; cs_m68k* ext; cs_m68k_op* op0; cs_m68k_op* op1; LIMIT_CPU_TYPES(info, M68010_PLUS); extension = read_imm_16(info); reg = M68K_REG_INVALID; ext = build_init_op(info, M68K_INS_MOVEC, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; switch (extension & 0xfff) { case 0x000: reg = M68K_REG_SFC; break; case 0x001: reg = M68K_REG_DFC; break; case 0x800: reg = M68K_REG_USP; break; case 0x801: reg = M68K_REG_VBR; break; case 0x002: reg = M68K_REG_CACR; break; case 0x802: reg = M68K_REG_CAAR; break; case 0x803: reg = M68K_REG_MSP; break; case 0x804: reg = M68K_REG_ISP; break; case 0x003: reg = M68K_REG_TC; break; case 0x004: reg = M68K_REG_ITT0; break; case 0x005: reg = M68K_REG_ITT1; break; case 0x006: reg = M68K_REG_DTT0; break; case 0x007: reg = M68K_REG_DTT1; break; case 0x805: reg = M68K_REG_MMUSR; break; case 0x806: reg = M68K_REG_URP; break; case 0x807: reg = M68K_REG_SRP; break; } if (BIT_0(info->ir)) { op0->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); op1->reg = reg; } else { op0->reg = reg; op1->reg = (BIT_F(extension) ? M68K_REG_A0 : M68K_REG_D0) + ((extension >> 12) & 7); } } static void d68000_movem_pd_16(m68k_info *info) { build_movem_re(info, M68K_INS_MOVEM, 2); } static void d68000_movem_pd_32(m68k_info *info) { build_movem_re(info, M68K_INS_MOVEM, 4); } static void d68000_movem_er_16(m68k_info *info) { build_movem_er(info, M68K_INS_MOVEM, 2); } static void d68000_movem_er_32(m68k_info *info) { build_movem_er(info, M68K_INS_MOVEM, 4); } static void d68000_movem_re_16(m68k_info *info) { build_movem_re(info, M68K_INS_MOVEM, 2); } static void d68000_movem_re_32(m68k_info *info) { build_movem_re(info, M68K_INS_MOVEM, 4); } static void d68000_movep_re_16(m68k_info *info) { build_movep_re(info, 2); } static void d68000_movep_re_32(m68k_info *info) { build_movep_re(info, 4); } static void d68000_movep_er_16(m68k_info *info) { build_movep_er(info, 2); } static void d68000_movep_er_32(m68k_info *info) { build_movep_er(info, 4); } static void d68010_moves_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_moves(info, 1); } static void d68010_moves_16(m68k_info *info) { //uint32_t extension; LIMIT_CPU_TYPES(info, M68010_PLUS); build_moves(info, 2); } static void d68010_moves_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68010_PLUS); build_moves(info, 4); } static void d68000_moveq(m68k_info *info) { cs_m68k_op* op0; cs_m68k_op* op1; cs_m68k* ext = build_init_op(info, M68K_INS_MOVEQ, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; op0->type = M68K_OP_IMM; op0->address_mode = M68K_AM_IMMEDIATE; op0->imm = (info->ir & 0xff); op1->address_mode = M68K_AM_REG_DIRECT_DATA; op1->reg = M68K_REG_D0 + ((info->ir >> 9) & 7); } static void d68040_move16_pi_pi(m68k_info *info) { int data[] = { info->ir & 7, (read_imm_16(info) >> 12) & 7 }; int modes[] = { M68K_AM_REGI_ADDR_POST_INC, M68K_AM_REGI_ADDR_POST_INC }; LIMIT_CPU_TYPES(info, M68040_PLUS); build_move16(info, data, modes); } static void d68040_move16_pi_al(m68k_info *info) { int data[] = { info->ir & 7, read_imm_32(info) }; int modes[] = { M68K_AM_REGI_ADDR_POST_INC, M68K_AM_ABSOLUTE_DATA_LONG }; LIMIT_CPU_TYPES(info, M68040_PLUS); build_move16(info, data, modes); } static void d68040_move16_al_pi(m68k_info *info) { int data[] = { read_imm_32(info), info->ir & 7 }; int modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, M68K_AM_REGI_ADDR_POST_INC }; LIMIT_CPU_TYPES(info, M68040_PLUS); build_move16(info, data, modes); } static void d68040_move16_ai_al(m68k_info *info) { int data[] = { info->ir & 7, read_imm_32(info) }; int modes[] = { M68K_AM_REG_DIRECT_ADDR, M68K_AM_ABSOLUTE_DATA_LONG }; LIMIT_CPU_TYPES(info, M68040_PLUS); build_move16(info, data, modes); } static void d68040_move16_al_ai(m68k_info *info) { int data[] = { read_imm_32(info), info->ir & 7 }; int modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, M68K_AM_REG_DIRECT_ADDR }; LIMIT_CPU_TYPES(info, M68040_PLUS); build_move16(info, data, modes); } static void d68000_muls(m68k_info *info) { build_er_1(info, M68K_INS_MULS, 2); } static void d68000_mulu(m68k_info *info) { build_er_1(info, M68K_INS_MULU, 2); } static void d68020_mull(m68k_info *info) { uint32_t extension, insn_signed; cs_m68k* ext; cs_m68k_op* op0; cs_m68k_op* op1; uint32_t reg_0, reg_1; LIMIT_CPU_TYPES(info, M68020_PLUS); extension = read_imm_16(info); insn_signed = 0; if (BIT_B((extension))) insn_signed = 1; ext = build_init_op(info, insn_signed ? M68K_INS_MULS : M68K_INS_MULU, 2, 4); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, 4); reg_0 = extension & 7; reg_1 = (extension >> 12) & 7; op1->address_mode = M68K_AM_NONE; op1->type = M68K_OP_REG_PAIR; op1->reg_pair.reg_0 = reg_0 + M68K_REG_D0; op1->reg_pair.reg_1 = reg_1 + M68K_REG_D0; if (!BIT_A(extension)) { op1->type = M68K_OP_REG; op1->reg = M68K_REG_D0 + reg_1; } } static void d68000_nbcd(m68k_info *info) { build_ea(info, M68K_INS_NBCD, 1); } static void d68000_neg_8(m68k_info *info) { build_ea(info, M68K_INS_NEG, 1); } static void d68000_neg_16(m68k_info *info) { build_ea(info, M68K_INS_NEG, 2); } static void d68000_neg_32(m68k_info *info) { build_ea(info, M68K_INS_NEG, 4); } static void d68000_negx_8(m68k_info *info) { build_ea(info, M68K_INS_NEGX, 1); } static void d68000_negx_16(m68k_info *info) { build_ea(info, M68K_INS_NEGX, 2); } static void d68000_negx_32(m68k_info *info) { build_ea(info, M68K_INS_NEGX, 4); } static void d68000_nop(m68k_info *info) { MCInst_setOpcode(info->inst, M68K_INS_NOP); } static void d68000_not_8(m68k_info *info) { build_ea(info, M68K_INS_NOT, 1); } static void d68000_not_16(m68k_info *info) { build_ea(info, M68K_INS_NOT, 2); } static void d68000_not_32(m68k_info *info) { build_ea(info, M68K_INS_NOT, 4); } static void d68000_or_er_8(m68k_info *info) { build_er_1(info, M68K_INS_OR, 1); } static void d68000_or_er_16(m68k_info *info) { build_er_1(info, M68K_INS_OR, 2); } static void d68000_or_er_32(m68k_info *info) { build_er_1(info, M68K_INS_OR, 4); } static void d68000_or_re_8(m68k_info *info) { build_re_1(info, M68K_INS_OR, 1); } static void d68000_or_re_16(m68k_info *info) { build_re_1(info, M68K_INS_OR, 2); } static void d68000_or_re_32(m68k_info *info) { build_re_1(info, M68K_INS_OR, 4); } static void d68000_ori_8(m68k_info *info) { build_imm_ea(info, M68K_INS_ORI, 1, read_imm_8(info)); } static void d68000_ori_16(m68k_info *info) { build_imm_ea(info, M68K_INS_ORI, 2, read_imm_16(info)); } static void d68000_ori_32(m68k_info *info) { build_imm_ea(info, M68K_INS_ORI, 4, read_imm_32(info)); } static void d68000_ori_to_ccr(m68k_info *info) { build_imm_special_reg(info, M68K_INS_ORI, read_imm_8(info), 1, M68K_REG_CCR); } static void d68000_ori_to_sr(m68k_info *info) { build_imm_special_reg(info, M68K_INS_ORI, read_imm_16(info), 2, M68K_REG_SR); } static void d68020_pack_rr(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_rr(info, M68K_INS_PACK, 0, read_imm_16(info)); } static void d68020_pack_mm(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_mm(info, M68K_INS_PACK, 0, read_imm_16(info)); } static void d68000_pea(m68k_info *info) { build_ea(info, M68K_INS_PEA, 4); } static void d68000_reset(m68k_info *info) { MCInst_setOpcode(info->inst, M68K_INS_RESET); } static void d68000_ror_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ROR, 1); } static void d68000_ror_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_ROR, 2); } static void d68000_ror_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_ROR, 4); } static void d68000_ror_r_8(m68k_info *info) { build_r(info, M68K_INS_ROR, 1); } static void d68000_ror_r_16(m68k_info *info) { build_r(info, M68K_INS_ROR, 2); } static void d68000_ror_r_32(m68k_info *info) { build_r(info, M68K_INS_ROR, 4); } static void d68000_ror_ea(m68k_info *info) { build_ea(info, M68K_INS_ROR, 2); } static void d68000_rol_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ROL, 1); } static void d68000_rol_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_ROL, 2); } static void d68000_rol_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_ROL, 4); } static void d68000_rol_r_8(m68k_info *info) { build_r(info, M68K_INS_ROL, 1); } static void d68000_rol_r_16(m68k_info *info) { build_r(info, M68K_INS_ROL, 2); } static void d68000_rol_r_32(m68k_info *info) { build_r(info, M68K_INS_ROL, 4); } static void d68000_rol_ea(m68k_info *info) { build_ea(info, M68K_INS_ROL, 2); } static void d68000_roxr_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXR, 1); } static void d68000_roxr_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXR, 2); } static void d68000_roxr_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXR, 4); } static void d68000_roxr_r_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXR, 4); } static void d68000_roxr_r_16(m68k_info *info) { build_r(info, M68K_INS_ROXR, 2); } static void d68000_roxr_r_32(m68k_info *info) { build_r(info, M68K_INS_ROXR, 4); } static void d68000_roxr_ea(m68k_info *info) { build_ea(info, M68K_INS_ROXR, 2); } static void d68000_roxl_s_8(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXL, 1); } static void d68000_roxl_s_16(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXL, 2); } static void d68000_roxl_s_32(m68k_info *info) { build_3bit_d(info, M68K_INS_ROXL, 4); } static void d68000_roxl_r_8(m68k_info *info) { build_r(info, M68K_INS_ROXL, 1); } static void d68000_roxl_r_16(m68k_info *info) { build_r(info, M68K_INS_ROXL, 2); } static void d68000_roxl_r_32(m68k_info *info) { build_r(info, M68K_INS_ROXL, 4); } static void d68000_roxl_ea(m68k_info *info) { build_ea(info, M68K_INS_ROXL, 2); } static void d68010_rtd(m68k_info *info) { set_insn_group(info, M68K_GRP_RET); LIMIT_CPU_TYPES(info, M68010_PLUS); build_absolute_jump_with_immediate(info, M68K_INS_RTD, 0, read_imm_16(info)); } static void d68000_rte(m68k_info *info) { set_insn_group(info, M68K_GRP_IRET); MCInst_setOpcode(info->inst, M68K_INS_RTE); } static void d68020_rtm(m68k_info *info) { cs_m68k* ext; cs_m68k_op* op; set_insn_group(info, M68K_GRP_RET); LIMIT_CPU_TYPES(info, M68020_ONLY); build_absolute_jump_with_immediate(info, M68K_INS_RTM, 0, 0); ext = &info->extension; op = &ext->operands[0]; op->address_mode = M68K_AM_NONE; op->type = M68K_OP_REG; if (BIT_3(info->ir)) { op->reg = M68K_REG_A0 + (info->ir & 7); } else { op->reg = M68K_REG_D0 + (info->ir & 7); } } static void d68000_rtr(m68k_info *info) { set_insn_group(info, M68K_GRP_RET); MCInst_setOpcode(info->inst, M68K_INS_RTR); } static void d68000_rts(m68k_info *info) { set_insn_group(info, M68K_GRP_RET); MCInst_setOpcode(info->inst, M68K_INS_RTS); } static void d68000_sbcd_rr(m68k_info *info) { build_rr(info, M68K_INS_SBCD, 1, 0); } static void d68000_sbcd_mm(m68k_info *info) { build_mm(info, M68K_INS_SBCD, 0, read_imm_16(info)); } static void d68000_scc(m68k_info *info) { cs_m68k* ext = build_init_op(info, s_scc_lut[(info->ir >> 8) & 0xf], 1, 1); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); } static void d68000_stop(m68k_info *info) { build_absolute_jump_with_immediate(info, M68K_INS_STOP, 0, read_imm_16(info)); } static void d68000_sub_er_8(m68k_info *info) { build_er_1(info, M68K_INS_SUB, 1); } static void d68000_sub_er_16(m68k_info *info) { build_er_1(info, M68K_INS_SUB, 2); } static void d68000_sub_er_32(m68k_info *info) { build_er_1(info, M68K_INS_SUB, 4); } static void d68000_sub_re_8(m68k_info *info) { build_re_1(info, M68K_INS_SUB, 1); } static void d68000_sub_re_16(m68k_info *info) { build_re_1(info, M68K_INS_SUB, 2); } static void d68000_sub_re_32(m68k_info *info) { build_re_1(info, M68K_INS_SUB, 4); } static void d68000_suba_16(m68k_info *info) { build_ea_a(info, M68K_INS_SUBA, 2); } static void d68000_suba_32(m68k_info *info) { build_ea_a(info, M68K_INS_SUBA, 4); } static void d68000_subi_8(m68k_info *info) { build_imm_ea(info, M68K_INS_SUBI, 1, read_imm_8(info)); } static void d68000_subi_16(m68k_info *info) { build_imm_ea(info, M68K_INS_SUBI, 2, read_imm_16(info)); } static void d68000_subi_32(m68k_info *info) { build_imm_ea(info, M68K_INS_SUBI, 4, read_imm_32(info)); } static void d68000_subq_8(m68k_info *info) { build_3bit_ea(info, M68K_INS_SUBQ, 1); } static void d68000_subq_16(m68k_info *info) { build_3bit_ea(info, M68K_INS_SUBQ, 2); } static void d68000_subq_32(m68k_info *info) { build_3bit_ea(info, M68K_INS_SUBQ, 4); } static void d68000_subx_rr_8(m68k_info *info) { build_rr(info, M68K_INS_SUBX, 1, 0); } static void d68000_subx_rr_16(m68k_info *info) { build_rr(info, M68K_INS_SUBX, 2, 0); } static void d68000_subx_rr_32(m68k_info *info) { build_rr(info, M68K_INS_SUBX, 4, 0); } static void d68000_subx_mm_8(m68k_info *info) { build_mm(info, M68K_INS_SUBX, 1, 0); } static void d68000_subx_mm_16(m68k_info *info) { build_mm(info, M68K_INS_SUBX, 2, 0); } static void d68000_subx_mm_32(m68k_info *info) { build_mm(info, M68K_INS_SUBX, 4, 0); } static void d68000_swap(m68k_info *info) { build_d(info, M68K_INS_SWAP, 0); } static void d68000_tas(m68k_info *info) { build_ea(info, M68K_INS_TAS, 1); } static void d68000_trap(m68k_info *info) { build_absolute_jump_with_immediate(info, M68K_INS_TRAP, 0, info->ir&0xf); } static void d68020_trapcc_0(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_trap(info, 0, 0); info->extension.op_count = 0; } static void d68020_trapcc_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_trap(info, 2, read_imm_16(info)); } static void d68020_trapcc_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_trap(info, 4, read_imm_32(info)); } static void d68000_trapv(m68k_info *info) { MCInst_setOpcode(info->inst, M68K_INS_TRAPV); } static void d68000_tst_8(m68k_info *info) { build_ea(info, M68K_INS_TST, 1); } static void d68020_tst_pcdi_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 1); } static void d68020_tst_pcix_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 1); } static void d68020_tst_i_8(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 1); } static void d68000_tst_16(m68k_info *info) { build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_a_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_pcdi_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_pcix_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_i_16(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68000_tst_32(m68k_info *info) { build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_a_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_pcdi_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_pcix_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_i_32(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68000_unlk(m68k_info *info) { cs_m68k_op* op; cs_m68k* ext = build_init_op(info, M68K_INS_UNLK, 1, 0); op = &ext->operands[0]; op->address_mode = M68K_AM_REG_DIRECT_ADDR; op->reg = M68K_REG_A0 + (info->ir & 7); } static void d68020_unpk_rr(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_rr(info, M68K_INS_UNPK, 0, read_imm_16(info)); } static void d68020_unpk_mm(m68k_info *info) { LIMIT_CPU_TYPES(info, M68020_PLUS); build_mm(info, M68K_INS_UNPK, 0, read_imm_16(info)); } /* This table is auto-generated. Look in contrib/m68k_instruction_tbl_gen for more info */ #include "M68KInstructionTable.inc" static int instruction_is_valid(m68k_info *info, const unsigned int word_check) { const unsigned int instruction = info->ir; const instruction_struct *i = &g_instruction_table[instruction]; if ( (i->word2_mask && ((word_check & i->word2_mask) != i->word2_match)) || (i->instruction == d68000_invalid) ) { d68000_invalid(info); return 0; } return 1; } static int exists_reg_list(uint16_t *regs, uint8_t count, m68k_reg reg) { uint8_t i; for (i = 0; i < count; ++i) { if (regs[i] == (uint16_t)reg) return 1; } return 0; } static void add_reg_to_rw_list(m68k_info *info, m68k_reg reg, int write) { if (reg == M68K_REG_INVALID) return; if (write) { if (exists_reg_list(info->regs_write, info->regs_write_count, reg)) return; info->regs_write[info->regs_write_count] = (uint16_t)reg; info->regs_write_count++; } else { if (exists_reg_list(info->regs_read, info->regs_read_count, reg)) return; info->regs_read[info->regs_read_count] = (uint16_t)reg; info->regs_read_count++; } } static void update_am_reg_list(m68k_info *info, cs_m68k_op *op, int write) { switch (op->address_mode) { case M68K_AM_REG_DIRECT_ADDR: case M68K_AM_REG_DIRECT_DATA: add_reg_to_rw_list(info, op->reg, write); break; case M68K_AM_REGI_ADDR_POST_INC: case M68K_AM_REGI_ADDR_PRE_DEC: add_reg_to_rw_list(info, op->reg, 1); break; case M68K_AM_REGI_ADDR: case M68K_AM_REGI_ADDR_DISP: add_reg_to_rw_list(info, op->reg, 0); break; case M68K_AM_AREGI_INDEX_8_BIT_DISP: case M68K_AM_AREGI_INDEX_BASE_DISP: case M68K_AM_MEMI_POST_INDEX: case M68K_AM_MEMI_PRE_INDEX: case M68K_AM_PCI_INDEX_8_BIT_DISP: case M68K_AM_PCI_INDEX_BASE_DISP: case M68K_AM_PC_MEMI_PRE_INDEX: case M68K_AM_PC_MEMI_POST_INDEX: add_reg_to_rw_list(info, op->mem.index_reg, 0); add_reg_to_rw_list(info, op->mem.base_reg, 0); break; // no register(s) in the other addressing modes default: break; } } static void update_bits_range(m68k_info *info, m68k_reg reg_start, uint8_t bits, int write) { int i; for (i = 0; i < 8; ++i) { if (bits & (1 << i)) { add_reg_to_rw_list(info, reg_start + i, write); } } } static void update_reg_list_regbits(m68k_info *info, cs_m68k_op *op, int write) { uint32_t bits = op->register_bits; update_bits_range(info, M68K_REG_D0, bits & 0xff, write); update_bits_range(info, M68K_REG_A0, (bits >> 8) & 0xff, write); update_bits_range(info, M68K_REG_FP0, (bits >> 16) & 0xff, write); } static void update_op_reg_list(m68k_info *info, cs_m68k_op *op, int write) { switch ((int)op->type) { case M68K_OP_REG: add_reg_to_rw_list(info, op->reg, write); break; case M68K_OP_MEM: update_am_reg_list(info, op, write); break; case M68K_OP_REG_BITS: update_reg_list_regbits(info, op, write); break; case M68K_OP_REG_PAIR: add_reg_to_rw_list(info, op->reg_pair.reg_0, write); add_reg_to_rw_list(info, op->reg_pair.reg_1, write); break; } } static void build_regs_read_write_counts(m68k_info *info) { int i; if (!info->extension.op_count) return; if (info->extension.op_count == 1) { update_op_reg_list(info, &info->extension.operands[0], 1); } else { // first operand is always read update_op_reg_list(info, &info->extension.operands[0], 0); // remaning write for (i = 1; i < info->extension.op_count; ++i) update_op_reg_list(info, &info->extension.operands[i], 1); } } static void m68k_setup_internals(m68k_info* info, MCInst* inst, unsigned int pc, unsigned int cpu_type) { info->inst = inst; info->pc = pc; info->ir = 0; info->type = cpu_type; info->address_mask = 0xffffffff; switch(info->type) { case M68K_CPU_TYPE_68000: info->type = TYPE_68000; info->address_mask = 0x00ffffff; break; case M68K_CPU_TYPE_68010: info->type = TYPE_68010; info->address_mask = 0x00ffffff; break; case M68K_CPU_TYPE_68EC020: info->type = TYPE_68020; info->address_mask = 0x00ffffff; break; case M68K_CPU_TYPE_68020: info->type = TYPE_68020; info->address_mask = 0xffffffff; break; case M68K_CPU_TYPE_68030: info->type = TYPE_68030; info->address_mask = 0xffffffff; break; case M68K_CPU_TYPE_68040: info->type = TYPE_68040; info->address_mask = 0xffffffff; break; default: info->address_mask = 0; return; } } /* ======================================================================== */ /* ================================= API ================================== */ /* ======================================================================== */ /* Disasemble one instruction at pc and store in str_buff */ static unsigned int m68k_disassemble(m68k_info *info, uint64_t pc) { MCInst *inst = info->inst; cs_m68k* ext = &info->extension; int i; unsigned int size; inst->Opcode = M68K_INS_INVALID; memset(ext, 0, sizeof(cs_m68k)); ext->op_size.type = M68K_SIZE_TYPE_CPU; for (i = 0; i < M68K_OPERAND_COUNT; ++i) ext->operands[i].type = M68K_OP_REG; info->ir = peek_imm_16(info); if (instruction_is_valid(info, peek_imm_32(info) & 0xffff)) { info->ir = read_imm_16(info); g_instruction_table[info->ir].instruction(info); } size = info->pc - (unsigned int)pc; info->pc = (unsigned int)pc; return size; } bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* inst_info) { #ifdef M68K_DEBUG SStream ss; #endif int s; int cpu_type = M68K_CPU_TYPE_68000; cs_struct* handle = instr->csh; m68k_info *info = (m68k_info*)handle->printer_info; // code len has to be at least 2 bytes to be valid m68k if (code_len < 2) { *size = 0; return false; } if (instr->flat_insn->detail) { memset(instr->flat_insn->detail, 0, offsetof(cs_detail, m68k)+sizeof(cs_m68k)); } info->groups_count = 0; info->regs_read_count = 0; info->regs_write_count = 0; info->code = code; info->code_len = code_len; info->baseAddress = address; if (handle->mode & CS_MODE_M68K_010) cpu_type = M68K_CPU_TYPE_68010; if (handle->mode & CS_MODE_M68K_020) cpu_type = M68K_CPU_TYPE_68020; if (handle->mode & CS_MODE_M68K_030) cpu_type = M68K_CPU_TYPE_68030; if (handle->mode & CS_MODE_M68K_040) cpu_type = M68K_CPU_TYPE_68040; if (handle->mode & CS_MODE_M68K_060) cpu_type = M68K_CPU_TYPE_68040; // 060 = 040 for now m68k_setup_internals(info, instr, (unsigned int)address, cpu_type); s = m68k_disassemble(info, address); if (s == 0) { *size = 2; return false; } build_regs_read_write_counts(info); #ifdef M68K_DEBUG SStream_Init(&ss); M68K_printInst(instr, &ss, info); #endif // Make sure we always stay within range if (s > (int)code_len) *size = (uint16_t)code_len; else *size = (uint16_t)s; return true; } capstone-sys-0.15.0/capstone/arch/M68K/M68KDisassembler.h000064400000000000000000000020310072674642500207750ustar 00000000000000/* Capstone Disassembly Engine */ /* M68K Backend by Daniel Collin 2015-2016 */ #ifndef CS_M68KDISASSEMBLER_H #define CS_M68KDISASSEMBLER_H #include "../../MCInst.h" /* Private, For internal use only */ typedef struct m68k_info { const uint8_t *code; size_t code_len; uint64_t baseAddress; MCInst *inst; unsigned int pc; /* program counter */ unsigned int ir; /* instruction register */ unsigned int type; unsigned int address_mask; /* Address mask to simulate address lines */ cs_m68k extension; uint16_t regs_read[20]; // list of implicit registers read by this insn uint8_t regs_read_count; // number of implicit registers read by this insn uint16_t regs_write[20]; // list of implicit registers modified by this insn uint8_t regs_write_count; // number of implicit registers modified by this insn uint8_t groups[8]; uint8_t groups_count; } m68k_info; bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info); #endif capstone-sys-0.15.0/capstone/arch/M68K/M68KInstPrinter.c000064400000000000000000000335240072674642500206470ustar 00000000000000/* Capstone Disassembly Engine */ /* M68K Backend by Daniel Collin 2015-2016 */ #ifdef _MSC_VER // Disable security warnings for strcat & sprintf #ifndef _CRT_SECURE_NO_WARNINGS #define _CRT_SECURE_NO_WARNINGS #endif //Banned API Usage : strcat / sprintf is a Banned API as listed in dontuse.h for //security purposes. #pragma warning(disable:28719) #endif #include // DEBUG #include #include #include "M68KInstPrinter.h" #include "M68KDisassembler.h" #include "../../cs_priv.h" #include "../../utils.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCRegisterInfo.h" #ifndef CAPSTONE_DIET static const char s_spacing[] = " "; static const char* const s_reg_names[] = { "invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "pc", "sr", "ccr", "sfc", "dfc", "usp", "vbr", "cacr", "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0", "dtt1", "mmusr", "urp", "srp", "fpcr", "fpsr", "fpiar", }; static const char* const s_instruction_names[] = { "invalid", "abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins", "bfset", "bftst", "bkpt", "callm", "cas", "cas2", "chk", "chk2", "clr", "cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl", "cinvp", "cinva", "cpushl", "cpushp", "cpusha", "dbt", "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", "dblt", "dbgt", "dble", "dbra", "divs", "divsl", "divu", "divul", "eor", "eori", "exg", "ext", "extb", "fabs", "fsabs", "fdabs", "facos", "fadd", "fsadd", "fdadd", "fasin", "fatan", "fatanh", "fbf", "fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl", "fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult", "fbule", "fbne", "fbt", "fbsf", "fbseq", "fbgt", "fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle", "fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne", "fbst", "fcmp", "fcos", "fcosh", "fdbf", "fdbeq", "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", "fdbne", "fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne", "fdbst", "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", "flognp1", "fmod", "fmove", "fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv", "fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq", "fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", "fsgl", "fsgle", "fsngle", "fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt", "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt", "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge", "ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec", "movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha", "pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror", "roxl", "roxr", "rtd", "rte", "rtm", "rtr", "rts", "sbcd", "st", "sf", "shi", "sls", "scc", "shs", "scs", "slo", "sne", "seq", "svc", "svs", "spl", "smi", "sge", "slt", "sgt", "sle", "stop", "sub", "suba", "subi", "subq", "subx", "swap", "tas", "trap", "trapv", "trapt", "trapf", "traphi", "trapls", "trapcc", "traphs", "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", "tst", "unlk", "unpk", }; #endif #ifndef CAPSTONE_DIET static const char* getRegName(m68k_reg reg) { return s_reg_names[(int)reg]; } static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix) { unsigned int first = 0; unsigned int run_length = 0; int i; for (i = 0; i < 8; ++i) { if (data & (1 << i)) { first = i; run_length = 0; while (i < 7 && (data & (1 << (i + 1)))) { i++; run_length++; } if (buffer[0] != 0) strcat(buffer, "/"); sprintf(buffer + strlen(buffer), "%s%d", prefix, first); if (run_length > 0) sprintf(buffer + strlen(buffer), "-%s%d", prefix, first + run_length); } } } static void registerBits(SStream* O, const cs_m68k_op* op) { char buffer[128]; unsigned int data = op->register_bits; buffer[0] = 0; if (!data) { SStream_concat(O, "%s", "#$0"); return; } printRegbitsRange(buffer, data & 0xff, "d"); printRegbitsRange(buffer, (data >> 8) & 0xff, "a"); printRegbitsRange(buffer, (data >> 16) & 0xff, "fp"); SStream_concat(O, "%s", buffer); } static void registerPair(SStream* O, const cs_m68k_op* op) { SStream_concat(O, "%s:%s", s_reg_names[op->reg_pair.reg_0], s_reg_names[op->reg_pair.reg_1]); } static void printAddressingMode(SStream* O, unsigned int pc, const cs_m68k* inst, const cs_m68k_op* op) { switch (op->address_mode) { case M68K_AM_NONE: switch (op->type) { case M68K_OP_REG_BITS: registerBits(O, op); break; case M68K_OP_REG_PAIR: registerPair(O, op); break; case M68K_OP_REG: SStream_concat(O, "%s", s_reg_names[op->reg]); break; default: break; } break; case M68K_AM_REG_DIRECT_DATA: SStream_concat(O, "d%d", (op->reg - M68K_REG_D0)); break; case M68K_AM_REG_DIRECT_ADDR: SStream_concat(O, "a%d", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR: SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_POST_INC: SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_PRE_DEC: SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); break; case M68K_AM_PCI_DISP: SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp); break; case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break; case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break; case M68K_AM_IMMEDIATE: if (inst->op_size.type == M68K_SIZE_TYPE_FPU) { #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point SStream_concat(O, "#"); break; #else if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE) SStream_concat(O, "#%f", op->simm); else if (inst->op_size.fpu_size == M68K_FPU_SIZE_DOUBLE) SStream_concat(O, "#%f", op->dimm); else SStream_concat(O, "#"); break; #endif } SStream_concat(O, "#$%x", op->imm); break; case M68K_AM_PCI_INDEX_8_BIT_DISP: SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); break; case M68K_AM_AREGI_INDEX_8_BIT_DISP: SStream_concat(O, "%s$%x(%s,%s%s.%c)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); break; case M68K_AM_PCI_INDEX_BASE_DISP: case M68K_AM_AREGI_INDEX_BASE_DISP: if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp); } else { if (op->mem.in_disp > 0) SStream_concat(O, "$%x", op->mem.in_disp); } SStream_concat(O, "("); if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { SStream_concat(O, "pc,%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); } else { if (op->mem.base_reg != M68K_REG_INVALID) SStream_concat(O, "a%d,%s", op->mem.base_reg - M68K_REG_A0, s_spacing); SStream_concat(O, "%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); } if (op->mem.scale > 0) SStream_concat(O, "%s*%s%d)", s_spacing, s_spacing, op->mem.scale); else SStream_concat(O, ")"); break; // It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. While this is not strictly correct it makes the code // easier and that is what actually happens when the code is executed anyway. case M68K_AM_PC_MEMI_POST_INDEX: case M68K_AM_PC_MEMI_PRE_INDEX: case M68K_AM_MEMI_PRE_INDEX: case M68K_AM_MEMI_POST_INDEX: SStream_concat(O, "(["); if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) { SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp); } else { if (op->mem.in_disp > 0) SStream_concat(O, "$%x", op->mem.in_disp); } if (op->mem.base_reg != M68K_REG_INVALID) { if (op->mem.in_disp > 0) SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg)); else SStream_concat(O, "%s", getRegName(op->mem.base_reg)); } if (op->address_mode == M68K_AM_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_POST_INDEX) SStream_concat(O, "]"); if (op->mem.index_reg != M68K_REG_INVALID) SStream_concat(O, ",%s%s.%c", s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); if (op->mem.scale > 0) SStream_concat(O, "%s*%s%d", s_spacing, s_spacing, op->mem.scale); if (op->address_mode == M68K_AM_MEMI_PRE_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) SStream_concat(O, "]"); if (op->mem.out_disp > 0) SStream_concat(O, ",%s$%x", s_spacing, op->mem.out_disp); SStream_concat(O, ")"); break; case M68K_AM_BRANCH_DISPLACEMENT: SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp); default: break; } if (op->mem.bitfield) SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width); } #endif #define m68k_sizeof_array(array) (int)(sizeof(array)/sizeof(array[0])) #define m68k_min(a, b) (a < b) ? a : b void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo) { #ifndef CAPSTONE_DIET m68k_info *info = (m68k_info *)PrinterInfo; cs_m68k *ext = &info->extension; cs_detail *detail = NULL; int i = 0; detail = MI->flat_insn->detail; if (detail) { int regs_read_count = m68k_min(m68k_sizeof_array(detail->regs_read), info->regs_read_count); int regs_write_count = m68k_min(m68k_sizeof_array(detail->regs_write), info->regs_write_count); int groups_count = m68k_min(m68k_sizeof_array(detail->groups), info->groups_count); memcpy(&detail->m68k, ext, sizeof(cs_m68k)); memcpy(&detail->regs_read, &info->regs_read, regs_read_count * sizeof(uint16_t)); detail->regs_read_count = regs_read_count; memcpy(&detail->regs_write, &info->regs_write, regs_write_count * sizeof(uint16_t)); detail->regs_write_count = regs_write_count; memcpy(&detail->groups, &info->groups, groups_count); detail->groups_count = groups_count; } if (MI->Opcode == M68K_INS_INVALID) { if (ext->op_count) SStream_concat(O, "dc.w $%x", ext->operands[0].imm); else SStream_concat(O, "dc.w $"); return; } SStream_concat0(O, (char*)s_instruction_names[MI->Opcode]); switch (ext->op_size.type) { case M68K_SIZE_TYPE_INVALID : break; case M68K_SIZE_TYPE_CPU : switch (ext->op_size.cpu_size) { case M68K_CPU_SIZE_BYTE: SStream_concat0(O, ".b"); break; case M68K_CPU_SIZE_WORD: SStream_concat0(O, ".w"); break; case M68K_CPU_SIZE_LONG: SStream_concat0(O, ".l"); break; case M68K_CPU_SIZE_NONE: break; } break; case M68K_SIZE_TYPE_FPU : switch (ext->op_size.fpu_size) { case M68K_FPU_SIZE_SINGLE: SStream_concat0(O, ".s"); break; case M68K_FPU_SIZE_DOUBLE: SStream_concat0(O, ".d"); break; case M68K_FPU_SIZE_EXTENDED: SStream_concat0(O, ".x"); break; case M68K_FPU_SIZE_NONE: break; } break; } SStream_concat0(O, " "); // this one is a bit spacial so we do special things if (MI->Opcode == M68K_INS_CAS2) { int reg_value_0, reg_value_1; printAddressingMode(O, info->pc, ext, &ext->operands[0]); SStream_concat0(O, ","); printAddressingMode(O, info->pc, ext, &ext->operands[1]); SStream_concat0(O, ","); reg_value_0 = ext->operands[2].register_bits >> 4; reg_value_1 = ext->operands[2].register_bits & 0xf; SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]); return; } for (i = 0; i < ext->op_count; ++i) { printAddressingMode(O, info->pc, ext, &ext->operands[i]); if ((i + 1) != ext->op_count) SStream_concat(O, ",%s", s_spacing); } #endif } const char* M68K_reg_name(csh handle, unsigned int reg) { #ifdef CAPSTONE_DIET return NULL; #else if (reg >= ARR_SIZE(s_reg_names)) { return NULL; } return s_reg_names[(int)reg]; #endif } void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id) { insn->id = id; // These id's matches for 68k } const char* M68K_insn_name(csh handle, unsigned int id) { #ifdef CAPSTONE_DIET return NULL; #else return s_instruction_names[id]; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { { M68K_GRP_INVALID , NULL }, { M68K_GRP_JUMP, "jump" }, { M68K_GRP_RET , "ret" }, { M68K_GRP_IRET, "iret" }, { M68K_GRP_BRANCH_RELATIVE, "branch_relative" }, }; #endif const char *M68K_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/M68K/M68KInstPrinter.h000064400000000000000000000012730072674642500206500ustar 00000000000000/* Capstone Disassembly Engine */ /* M68K Backend by Daniel Collin 2015 */ #ifndef CS_M68KINSTPRINTER_H #define CS_M68KINSTPRINTER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" struct SStream; void M68K_init(MCRegisterInfo *MRI); void M68K_printInst(MCInst* MI, struct SStream* O, void* Info); const char* M68K_reg_name(csh handle, unsigned int reg); void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id); const char *M68K_insn_name(csh handle, unsigned int id); const char* M68K_group_name(csh handle, unsigned int id); void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci); #endif capstone-sys-0.15.0/capstone/arch/M68K/M68KInstructionTable.inc000064400000000000000000075123100072674642500222100ustar 00000000000000/* This table is auto-generated. DO NOT MANUALLY EDIT! Look in M68KInstructionTblGen.c for more info */ static const instruction_struct g_instruction_table[] = { { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_ori_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_to_ccr, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_ori_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_to_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_ori_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68020_chk2_cmp2_8, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_andi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_to_ccr, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_andi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_to_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_andi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68020_chk2_cmp2_16, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_subi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_subi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_subi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68020_chk2_cmp2_32, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_addi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_addi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_addi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_rtm, 0x0, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68020_callm, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_btst_s, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_bchg_s, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_bclr_s, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_bset_s, 0xfe00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_eori_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_to_ccr, 0xff00, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_eori_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_to_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_eori_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68020_cas_8, 0xfe38, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68000_cmpi_8, 0x0, 0x0 }, { d68020_cmpi_pcdi_8, 0x0, 0x0 }, { d68020_cmpi_pcix_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68000_cmpi_16, 0x0, 0x0 }, { d68020_cmpi_pcdi_16, 0x0, 0x0 }, { d68020_cmpi_pcix_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68000_cmpi_32, 0x0, 0x0 }, { d68020_cmpi_pcdi_32, 0x0, 0x0 }, { d68020_cmpi_pcix_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68020_cas_16, 0xfe38, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_cas2_16, 0xe38, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68010_moves_8, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68010_moves_16, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68010_moves_32, 0x7ff, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68020_cas_32, 0xfe38, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_cas2_32, 0xe38, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_movep_er_16, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_btst_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_movep_er_32, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_bchg_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_movep_re_16, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_bclr_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_movep_re_32, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_bset_r, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { d68000_move_8, 0x0, 0x0 }, { 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}, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_negx_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_negx_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_clr_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_clr_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_clr_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68010_move_fr_ccr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_neg_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_neg_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_neg_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_move_to_ccr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_not_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_not_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_not_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_move_to_sr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68020_link_32, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_nbcd, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68000_swap, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68010_bkpt, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_pea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_ext_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_pd_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_movem_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_ext_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_pd_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_movem_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68020_extb_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68000_tst_8, 0x0, 0x0 }, { d68020_tst_pcdi_8, 0x0, 0x0 }, { d68020_tst_pcix_8, 0x0, 0x0 }, { d68020_tst_i_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68020_tst_a_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68000_tst_16, 0x0, 0x0 }, { d68020_tst_pcdi_16, 0x0, 0x0 }, { d68020_tst_pcix_16, 0x0, 0x0 }, { d68020_tst_i_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68020_tst_a_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68000_tst_32, 0x0, 0x0 }, { d68020_tst_pcdi_32, 0x0, 0x0 }, { d68020_tst_pcix_32, 0x0, 0x0 }, { d68020_tst_i_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_tas, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_illegal, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68020_mull, 0x83f8, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68020_divl, 0x83f8, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_movem_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_movem_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_trap, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_link_16, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_unlk, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_to_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_move_fr_usp, 0x0, 0x0 }, { d68000_reset, 0x0, 0x0 }, { d68000_nop, 0x0, 0x0 }, { d68000_stop, 0x0, 0x0 }, { d68000_rte, 0x0, 0x0 }, { d68010_rtd, 0x0, 0x0 }, { d68000_rts, 0x0, 0x0 }, { d68000_trapv, 0x0, 0x0 }, { d68000_rtr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68010_movec, 0x0, 0x0 }, { d68010_movec, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_jsr, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_jmp, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68020_chk_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_chk_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_lea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 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0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_dbra, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 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d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_addq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_addq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_addq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_subq_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_subq_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_subq_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_dbcc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68000_scc, 0x0, 0x0 }, { d68020_trapcc_16, 0x0, 0x0 }, { d68020_trapcc_32, 0x0, 0x0 }, { d68020_trapcc_0, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_bra_16, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { d68000_bra_8, 0x0, 0x0 }, { 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d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68000_bsr_8, 0x0, 0x0 }, { d68020_bsr_32, 0x0, 0x0 }, { d68000_bcc_16, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68000_bcc_8, 0x0, 0x0 }, { d68020_bcc_32, 0x0, 0x0 }, { d68000_bcc_16, 0x0, 0x0 }, { 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0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { 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d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_or_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_or_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_or_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_divu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_rr, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_sbcd_mm, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_or_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_rr, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68020_pack_mm, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_or_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_rr, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68020_unpk_mm, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_or_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_divs, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_suba_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_sub_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_sub_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_sub_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_suba_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_rr_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_subx_mm_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_sub_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_rr_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_subx_mm_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_sub_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_rr_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_subx_mm_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { d68000_sub_re_32, 0x0, 0x0 }, { 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d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_1010, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_cmp_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_cmp_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_cmpa_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_cmpm_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_eor_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_cmpm_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_eor_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_cmpm_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_eor_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_cmpa_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_and_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_and_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_and_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_mulu, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_rr, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_abcd_mm, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_and_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_dd, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_exg_aa, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_and_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_exg_da, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_and_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_muls, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_add_er_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_add_er_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_add_er_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_adda_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_rr_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_addx_mm_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_add_re_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_rr_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_addx_mm_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_add_re_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_rr_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_addx_mm_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_add_re_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_adda_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_asr_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_asl_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_lsr_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_lsl_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_roxr_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_roxl_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_ror_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_rol_ea, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68020_bftst, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68020_bfextu, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68020_bfchg, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68020_bfexts, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68020_bfclr, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68020_bfffo, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_asr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_lsr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_roxr_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_ror_s_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_asr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_lsr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_roxr_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_ror_r_8, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_asr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_lsr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_roxr_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_ror_s_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_asr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_lsr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_roxr_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_ror_r_16, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_asr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_lsr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_roxr_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_ror_s_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_asr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_lsr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_roxr_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68000_ror_r_32, 0x0, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68020_bfset, 0xf000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_asl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_lsl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_roxl_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_rol_s_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_asl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_lsl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_roxl_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_rol_r_8, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_asl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_lsl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_roxl_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_rol_s_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_asl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_lsl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_roxl_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_rol_r_16, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_asl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_lsl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_roxl_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_rol_s_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_asl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_lsl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_roxl_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68000_rol_r_32, 0x0, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68020_bfins, 0x8000, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_al_pi, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_ai_al, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_al_ai, 0x0, 0x0 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68040_move16_pi_pi, 0x8fff, 0x8000 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpdbcc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 }, { d68000_1111, 0x0, 0x0 } }; capstone-sys-0.15.0/capstone/arch/M68K/M68KModule.c000064400000000000000000000015000072674642500176000ustar 00000000000000/* Capstone Disassembly Engine */ /* M68K Backend by Daniel Collin 2015 */ #ifdef CAPSTONE_HAS_M68K #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "M68KDisassembler.h" #include "M68KInstPrinter.h" #include "M68KModule.h" cs_err M68K_global_init(cs_struct *ud) { m68k_info *info; info = cs_mem_malloc(sizeof(m68k_info)); if (!info) { return CS_ERR_MEM; } ud->printer = M68K_printInst; ud->printer_info = info; ud->getinsn_info = NULL; ud->disasm = M68K_getInstruction; ud->skipdata_size = 2; ud->post_printer = NULL; ud->reg_name = M68K_reg_name; ud->insn_id = M68K_get_insn_id; ud->insn_name = M68K_insn_name; ud->group_name = M68K_group_name; return CS_ERR_OK; } cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value) { return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/M68K/M68KModule.h000064400000000000000000000004350072674642500176130ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_M68K_MODULE_H #define CS_M68K_MODULE_H #include "../../utils.h" cs_err M68K_global_init(cs_struct *ud); cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/MOS65XX/MOS65XXDisassembler.c000064400000000000000000000321140072674642500220050ustar 00000000000000/* Capstone Disassembly Engine */ /* MOS65XX Backend by Sebastian Macke 2018 */ #include "capstone/mos65xx.h" #include "MOS65XXDisassembler.h" #include "MOS65XXDisassemblerInternals.h" typedef struct OpInfo { mos65xx_insn ins; mos65xx_address_mode am; int operand_bytes; } OpInfo; static const struct OpInfo OpInfoTable[]= { #include "m6502.inc" #include "m65c02.inc" #include "mw65c02.inc" #include "m65816.inc" }; static const char* const RegNames[] = { "invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K" }; #ifndef CAPSTONE_DIET static const char* const GroupNames[] = { NULL, "jump", "call", "ret", "int", "iret", "branch_relative" }; typedef struct InstructionInfo { const char* name; mos65xx_group_type group_type; mos65xx_reg write, read; bool modifies_status; } InstructionInfo; static const struct InstructionInfo InstructionInfoTable[]= { #include "instruction_info.inc" }; #endif #ifndef CAPSTONE_DIET static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type) { int i; cs_detail *detail = MI->flat_insn->detail; InstructionInfo insinfo = InstructionInfoTable[opinfo.ins]; detail->mos65xx.am = opinfo.am; detail->mos65xx.modifies_flags = insinfo.modifies_status; detail->groups_count = 0; detail->regs_read_count = 0; detail->regs_write_count = 0; detail->mos65xx.op_count = 0; if (insinfo.group_type != MOS65XX_GRP_INVALID) { detail->groups[detail->groups_count] = insinfo.group_type; detail->groups_count++; } if (opinfo.am == MOS65XX_AM_REL || opinfo.am == MOS65XX_AM_ZP_REL) { detail->groups[detail->groups_count] = MOS65XX_GRP_BRANCH_RELATIVE; detail->groups_count++; } if (insinfo.read != MOS65XX_REG_INVALID) { detail->regs_read[detail->regs_read_count++] = insinfo.read; } else switch(opinfo.am) { case MOS65XX_AM_ACC: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC; break; case MOS65XX_AM_ZP_Y: case MOS65XX_AM_ZP_IND_Y: case MOS65XX_AM_ABS_Y: case MOS65XX_AM_ZP_IND_LONG_Y: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y; break; case MOS65XX_AM_ZP_X: case MOS65XX_AM_ZP_X_IND: case MOS65XX_AM_ABS_X: case MOS65XX_AM_ABS_X_IND: case MOS65XX_AM_ABS_LONG_X: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X; break; case MOS65XX_AM_SR: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP; break; case MOS65XX_AM_SR_IND_Y: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP; detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y; break; default: break; } if (insinfo.write != MOS65XX_REG_INVALID) { detail->regs_write[detail->regs_write_count++] = insinfo.write; } else if (opinfo.am == MOS65XX_AM_ACC) { detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC; } switch(opinfo.ins) { case MOS65XX_INS_ADC: case MOS65XX_INS_SBC: case MOS65XX_INS_ROL: case MOS65XX_INS_ROR: /* these read carry flag (and decimal for ADC/SBC) */ detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P; break; /* stack operations */ case MOS65XX_INS_JSL: case MOS65XX_INS_JSR: case MOS65XX_INS_PEA: case MOS65XX_INS_PEI: case MOS65XX_INS_PER: case MOS65XX_INS_PHA: case MOS65XX_INS_PHB: case MOS65XX_INS_PHD: case MOS65XX_INS_PHK: case MOS65XX_INS_PHP: case MOS65XX_INS_PHX: case MOS65XX_INS_PHY: case MOS65XX_INS_PLA: case MOS65XX_INS_PLB: case MOS65XX_INS_PLD: case MOS65XX_INS_PLP: case MOS65XX_INS_PLX: case MOS65XX_INS_PLY: case MOS65XX_INS_RTI: case MOS65XX_INS_RTL: case MOS65XX_INS_RTS: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP; detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP; break; default: break; } if (cpu_type == MOS65XX_CPU_TYPE_65816) { switch (opinfo.am) { case MOS65XX_AM_ZP: case MOS65XX_AM_ZP_X: case MOS65XX_AM_ZP_Y: case MOS65XX_AM_ZP_IND: case MOS65XX_AM_ZP_X_IND: case MOS65XX_AM_ZP_IND_Y: case MOS65XX_AM_ZP_IND_LONG: case MOS65XX_AM_ZP_IND_LONG_Y: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_DP; break; case MOS65XX_AM_BLOCK: detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC; detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X; detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y; detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC; detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_X; detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_Y; detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_B; break; default: break; } switch (opinfo.am) { case MOS65XX_AM_ZP_IND: case MOS65XX_AM_ZP_X_IND: case MOS65XX_AM_ZP_IND_Y: case MOS65XX_AM_ABS: case MOS65XX_AM_ABS_X: case MOS65XX_AM_ABS_Y: case MOS65XX_AM_ABS_X_IND: /* these depend on the databank to generate a 24-bit address */ /* exceptions: PEA, PEI, and JMP (abs) */ if (opinfo.ins == MOS65XX_INS_PEI || opinfo.ins == MOS65XX_INS_PEA) break; detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_B; break; default: break; } } if (insinfo.modifies_status) { detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P; } switch(opinfo.am) { case MOS65XX_AM_IMP: break; case MOS65XX_AM_IMM: detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_IMM; detail->mos65xx.operands[detail->mos65xx.op_count].imm = MI->Operands[0].ImmVal; detail->mos65xx.op_count++; break; case MOS65XX_AM_ACC: detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_REG; detail->mos65xx.operands[detail->mos65xx.op_count].reg = MOS65XX_REG_ACC; detail->mos65xx.op_count++; break; case MOS65XX_AM_REL: { int value = MI->Operands[0].ImmVal; if (MI->op1_size == 1) value = 2 + (signed char)value; else value = 3 + (signed short)value; detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM; detail->mos65xx.operands[detail->mos65xx.op_count].mem = (MI->address + value) & 0xffff; detail->mos65xx.op_count++; break; } case MOS65XX_AM_ZP_REL: { int value = 3 + (signed char)MI->Operands[1].ImmVal; /* BBR0, zp, rel and BBS0, zp, rel */ detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM; detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal; detail->mos65xx.operands[detail->mos65xx.op_count+1].type = MOS65XX_OP_MEM; detail->mos65xx.operands[detail->mos65xx.op_count+1].mem = (MI->address + value) & 0xffff; detail->mos65xx.op_count+=2; break; } default: for (i = 0; i < MI->size; ++i) { detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM; detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[i].ImmVal; detail->mos65xx.op_count++; } break; } } #endif void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) { #ifndef CAPSTONE_DIET unsigned int value; unsigned opcode = MCInst_getOpcode(MI); mos65xx_info *info = (mos65xx_info *)PrinterInfo; OpInfo opinfo = OpInfoTable[opcode]; const char *prefix = info->hex_prefix ? info->hex_prefix : "0x"; SStream_concat0(O, InstructionInfoTable[opinfo.ins].name); switch (opinfo.ins) { /* special case - bit included as part of the instruction name */ case MOS65XX_INS_BBR: case MOS65XX_INS_BBS: case MOS65XX_INS_RMB: case MOS65XX_INS_SMB: SStream_concat(O, "%d", (opcode >> 4) & 0x07); break; default: break; } value = MI->Operands[0].ImmVal; switch (opinfo.am) { default: break; case MOS65XX_AM_IMP: break; case MOS65XX_AM_ACC: SStream_concat(O, " a"); break; case MOS65XX_AM_IMM: if (MI->imm_size == 1) SStream_concat(O, " #%s%02x", prefix, value); else SStream_concat(O, " #%s%04x", prefix, value); break; case MOS65XX_AM_ZP: SStream_concat(O, " %s%02x", prefix, value); break; case MOS65XX_AM_ABS: SStream_concat(O, " %s%04x", prefix, value); break; case MOS65XX_AM_ABS_LONG_X: SStream_concat(O, " %s%06x, x", prefix, value); break; case MOS65XX_AM_INT: SStream_concat(O, " %s%02x", prefix, value); break; case MOS65XX_AM_ABS_X: SStream_concat(O, " %s%04x, x", prefix, value); break; case MOS65XX_AM_ABS_Y: SStream_concat(O, " %s%04x, y", prefix, value); break; case MOS65XX_AM_ABS_LONG: SStream_concat(O, " %s%06x", prefix, value); break; case MOS65XX_AM_ZP_X: SStream_concat(O, " %s%02x, x", prefix, value); break; case MOS65XX_AM_ZP_Y: SStream_concat(O, " %s%02x, y", prefix, value); break; case MOS65XX_AM_REL: if (MI->op1_size == 1) value = 2 + (signed char)value; else value = 3 + (signed short)value; SStream_concat(O, " %s%04x", prefix, (MI->address + value) & 0xffff); break; case MOS65XX_AM_ABS_IND: SStream_concat(O, " (%s%04x)", prefix, value); break; case MOS65XX_AM_ABS_X_IND: SStream_concat(O, " (%s%04x, x)", prefix, value); break; case MOS65XX_AM_ABS_IND_LONG: SStream_concat(O, " [%s%04x]", prefix, value); break; case MOS65XX_AM_ZP_IND: SStream_concat(O, " (%s%02x)", prefix, value); break; case MOS65XX_AM_ZP_X_IND: SStream_concat(O, " (%s%02x, x)", prefix, value); break; case MOS65XX_AM_ZP_IND_Y: SStream_concat(O, " (%s%02x), y", prefix, value); break; case MOS65XX_AM_ZP_IND_LONG: SStream_concat(O, " [%s%02x]", prefix, value); break; case MOS65XX_AM_ZP_IND_LONG_Y: SStream_concat(O, " [%s%02x], y", prefix, value); break; case MOS65XX_AM_SR: SStream_concat(O, " %s%02x, s", prefix, value); break; case MOS65XX_AM_SR_IND_Y: SStream_concat(O, " (%s%02x, s), y", prefix, value); break; case MOS65XX_AM_BLOCK: SStream_concat(O, " %s%02x, %s%02x", prefix, MI->Operands[0].ImmVal, prefix, MI->Operands[1].ImmVal); break; case MOS65XX_AM_ZP_REL: value = 3 + (signed char)MI->Operands[1].ImmVal; /* BBR0, zp, rel and BBS0, zp, rel */ SStream_concat(O, " %s%02x, %s%04x", prefix, MI->Operands[0].ImmVal, prefix, (MI->address + value) & 0xffff); break; } #endif } bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) { int i; unsigned char opcode; unsigned char len; unsigned cpu_offset = 0; int cpu_type = MOS65XX_CPU_TYPE_6502; cs_struct* handle = MI->csh; mos65xx_info *info = (mos65xx_info *)handle->printer_info; OpInfo opinfo; if (code_len == 0) { *size = 1; return false; } cpu_type = info->cpu_type; cpu_offset = cpu_type * 256; opcode = code[0]; opinfo = OpInfoTable[cpu_offset + opcode]; if (opinfo.ins == MOS65XX_INS_INVALID) { *size = 1; return false; } len = opinfo.operand_bytes + 1; if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) { switch(opinfo.ins) { case MOS65XX_INS_CPX: case MOS65XX_INS_CPY: case MOS65XX_INS_LDX: case MOS65XX_INS_LDY: if (info->long_x) ++len; break; case MOS65XX_INS_ADC: case MOS65XX_INS_AND: case MOS65XX_INS_BIT: case MOS65XX_INS_CMP: case MOS65XX_INS_EOR: case MOS65XX_INS_LDA: case MOS65XX_INS_ORA: case MOS65XX_INS_SBC: if (info->long_m) ++len; break; default: break; } } if (code_len < len) { *size = 1; return false; } MI->address = address; MCInst_setOpcode(MI, cpu_offset + opcode); MCInst_setOpcodePub(MI, opinfo.ins); *size = len; /* needed to differentiate relative vs relative long */ MI->op1_size = len - 1; if (opinfo.ins == MOS65XX_INS_NOP) { for (i = 1; i < len; ++i) MCOperand_CreateImm0(MI, code[i]); } switch (opinfo.am) { case MOS65XX_AM_ZP_REL: MCOperand_CreateImm0(MI, code[1]); MCOperand_CreateImm0(MI, code[2]); break; case MOS65XX_AM_BLOCK: MCOperand_CreateImm0(MI, code[2]); MCOperand_CreateImm0(MI, code[1]); break; case MOS65XX_AM_IMP: case MOS65XX_AM_ACC: break; case MOS65XX_AM_IMM: MI->has_imm = 1; MI->imm_size = len - 1; /* 65816 immediate is either 1 or 2 bytes */ /* drop through */ default: if (len == 2) MCOperand_CreateImm0(MI, code[1]); else if (len == 3) MCOperand_CreateImm0(MI, (code[2]<<8) | code[1]); else if (len == 4) MCOperand_CreateImm0(MI, (code[3]<<16) | (code[2]<<8) | code[1]); break; } #ifndef CAPSTONE_DIET if (MI->flat_insn->detail) { fillDetails(MI, opinfo, cpu_type); } #endif return true; } const char *MOS65XX_insn_name(csh handle, unsigned int id) { #ifdef CAPSTONE_DIET return NULL; #else if (id >= ARR_SIZE(InstructionInfoTable)) { return NULL; } return InstructionInfoTable[id].name; #endif } const char* MOS65XX_reg_name(csh handle, unsigned int reg) { #ifdef CAPSTONE_DIET return NULL; #else if (reg >= ARR_SIZE(RegNames)) { return NULL; } return RegNames[(int)reg]; #endif } void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { /* id is cpu_offset + opcode */ if (id < ARR_SIZE(OpInfoTable)) { insn->id = OpInfoTable[id].ins; } } const char *MOS65XX_group_name(csh handle, unsigned int id) { #ifdef CAPSTONE_DIET return NULL; #else if (id >= ARR_SIZE(GroupNames)) { return NULL; } return GroupNames[(int)id]; #endif } capstone-sys-0.15.0/capstone/arch/MOS65XX/MOS65XXDisassembler.h000064400000000000000000000013520072674642500220120ustar 00000000000000/* Capstone Disassembly Engine */ /* MOS65XX Backend by Sebastian Macke 2018 */ #ifndef CAPSTONE_MOS65XXDISASSEMBLER_H #define CAPSTONE_MOS65XXDISASSEMBLER_H #include "../../utils.h" void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo); void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *MOS65XX_insn_name(csh handle, unsigned int id); const char *MOS65XX_group_name(csh handle, unsigned int id); const char* MOS65XX_reg_name(csh handle, unsigned int reg); bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *inst_info); #endif //CAPSTONE_MOS65XXDISASSEMBLER_H capstone-sys-0.15.0/capstone/arch/MOS65XX/MOS65XXDisassemblerInternals.h000064400000000000000000000005550072674642500236760ustar 00000000000000#ifndef CS_MOS65XXDISASSEMBLERINTERNALS_H #define CS_MOS65XXDISASSEMBLERINTERNALS_H #include "capstone/mos65xx.h" enum { MOS65XX_CPU_TYPE_6502, MOS65XX_CPU_TYPE_65C02, MOS65XX_CPU_TYPE_W65C02, MOS65XX_CPU_TYPE_65816, }; typedef struct mos65xx_info { const char *hex_prefix; unsigned cpu_type; unsigned long_m; unsigned long_x; } mos65xx_info; #endif capstone-sys-0.15.0/capstone/arch/MOS65XX/MOS65XXModule.c000064400000000000000000000036560072674642500206260ustar 00000000000000/* Capstone Disassembly Engine */ /* MOS65XX Backend by Sebastian Macke 2018 */ #ifdef CAPSTONE_HAS_MOS65XX #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "MOS65XXDisassembler.h" #include "MOS65XXDisassemblerInternals.h" #include "MOS65XXModule.h" cs_err MOS65XX_global_init(cs_struct *ud) { mos65xx_info *info; info = cs_mem_malloc(sizeof(*info)); info->hex_prefix = NULL; info->cpu_type = MOS65XX_CPU_TYPE_6502; info->long_m = 0; info->long_x = 0; ud->printer = MOS65XX_printInst; ud->printer_info = info; ud->insn_id = MOS65XX_get_insn_id; ud->insn_name = MOS65XX_insn_name; ud->group_name = MOS65XX_group_name; ud->disasm = MOS65XX_getInstruction; ud->reg_name = MOS65XX_reg_name; if (ud->mode) { MOS65XX_option(ud, CS_OPT_MODE, ud->mode); } return CS_ERR_OK; } cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value) { mos65xx_info *info = (mos65xx_info *)handle->printer_info; switch(type) { default: break; case CS_OPT_MODE: if (value & CS_MODE_MOS65XX_6502) info->cpu_type = MOS65XX_CPU_TYPE_6502; if (value & CS_MODE_MOS65XX_65C02) info->cpu_type = MOS65XX_CPU_TYPE_65C02; if (value & CS_MODE_MOS65XX_W65C02) info->cpu_type = MOS65XX_CPU_TYPE_W65C02; if (value & (CS_MODE_MOS65XX_65816|CS_MODE_MOS65XX_65816_LONG_M|CS_MODE_MOS65XX_65816_LONG_X)) info->cpu_type = MOS65XX_CPU_TYPE_65816; info->long_m = value & CS_MODE_MOS65XX_65816_LONG_M ? 1 : 0; info->long_x = value & CS_MODE_MOS65XX_65816_LONG_X ? 1 : 0; handle->mode = (cs_mode)value; break; case CS_OPT_SYNTAX: switch(value) { default: // wrong syntax value handle->errnum = CS_ERR_OPTION; return CS_ERR_OPTION; case CS_OPT_SYNTAX_DEFAULT: info->hex_prefix = NULL; break; case CS_OPT_SYNTAX_MOTOROLA: info->hex_prefix = "$"; break; } handle->syntax = (int)value; break; } return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/MOS65XX/MOS65XXModule.h000064400000000000000000000004470072674642500206260ustar 00000000000000/* Capstone Disassembly Engine */ /* By Sebastian Macke , 2018 */ #ifndef CS_MOS65XX_MODULE_H #define CS_MOS65XX_MODULE_H #include "../../utils.h" cs_err MOS65XX_global_init(cs_struct *ud); cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/MOS65XX/instruction_info.inc000064400000000000000000000222770072674642500223120ustar 00000000000000/* * MOS65XX_GRP_BRANCH_RELATIVE handled elsewhere based on address mode * MOS65XX_REG_SP handled elsewhere for push/pop instructions * BLOCK moves handled elsewhere. * MOS65XX_REG_Y handled elsewhere for abs,y zp, y etc * MOS65XX_REG_X handled elsewhere for abs,x zp, x etc * MOS65XX_REG_DP handled elsewhere for zp zp,x zp,y etc */ { "invalid", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "adc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true }, { "and", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true }, { "asl", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "bbr", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bbs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bcc", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bcs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "beq", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bit", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true }, { "bmi", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bne", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bpl", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bra", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "brk", MOS65XX_GRP_INT, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "brl", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "bvc", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "bvs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "clc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "cld", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "cli", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "clv", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "cmp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true }, { "cop", MOS65XX_GRP_INT, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "cpx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, true }, { "cpy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, true }, { "dec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "dex", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true }, { "dey", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true }, { "eor", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true }, { "inc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "inx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true }, { "iny", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true }, { "jml", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "jmp", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "jsl", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "jsr", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "lda", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, { "ldx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true }, { "ldy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true }, { "lsr", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "mvn", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "mvp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "nop", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "ora", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true }, { "pea", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "pei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "per", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "pha", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false }, { "phb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_B, false }, { "phd", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_DP, false }, { "phk", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_K, false }, { "php", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_P, false }, { "phx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false }, { "phy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false }, { "pla", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true }, { "plb", MOS65XX_GRP_INVALID, MOS65XX_REG_B, MOS65XX_REG_INVALID, true }, { "pld", MOS65XX_GRP_INVALID, MOS65XX_REG_DP, MOS65XX_REG_INVALID, true }, { "plp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "plx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true }, { "ply", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true }, { "rep", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "rmb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "rol", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "ror", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "rti", MOS65XX_GRP_IRET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "rtl", MOS65XX_GRP_RET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "rts", MOS65XX_GRP_RET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "sbc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true }, { "sec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "sed", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "sei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "sep", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true }, { "smb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "sta", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false }, { "stp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "stx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false }, { "sty", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false }, { "stz", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "tax", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_ACC, true }, { "tay", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_ACC, true }, { "tcd", MOS65XX_GRP_INVALID, MOS65XX_REG_DP, MOS65XX_REG_ACC, true }, { "tcs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_ACC, false }, { "tdc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_DP, true }, { "trb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true }, { "tsb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true }, { "tsc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_SP, true }, { "tsx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_SP, true }, { "txa", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_X, true }, { "txs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_X, false }, { "txy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_X, true }, { "tya", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_Y, true }, { "tyx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_Y, true }, { "wai", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "wdm", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false }, { "xba", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true }, { "xce", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },capstone-sys-0.15.0/capstone/arch/MOS65XX/m6502.inc000064400000000000000000000370000072674642500174550ustar 00000000000000{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x02 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x03 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x04 { MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05 { MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x07 { MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08 { MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09 { MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0b { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0c { MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d { MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0f { MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x12 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x13 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x14 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15 { MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x17 { MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18 { MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1b { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1c { MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d { MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1f { MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x22 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x23 { MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24 { MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25 { MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x27 { MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28 { MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29 { MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x2b { MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c { MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d { MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x2f { MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x32 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x33 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x34 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35 { MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x37 { MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38 { MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3b { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3c { MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d { MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3f { MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x42 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x43 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x44 { MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45 { MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x47 { MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48 { MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49 { MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x4b { MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c { MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d { MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x4f { MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x52 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x53 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x54 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55 { MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x57 { MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58 { MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5b { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5c { MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d { MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5f { MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x62 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x63 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x64 { MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65 { MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x67 { MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68 { MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69 { MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x6b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c { MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d { MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x6f { MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x72 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x73 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x74 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75 { MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x77 { MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78 { MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7b { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7c { MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d { MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7f { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x80 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x82 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x83 { MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84 { MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85 { MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x87 { MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x89 { MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x8b { MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c { MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d { MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x8f { MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x92 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x93 { MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95 { MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x97 { MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98 { MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99 { MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9b { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9c { MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9e { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9f { MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1 { MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xa3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xa7 { MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8 { MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9 { MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xab { MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac { MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad { MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xaf { MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb2 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb7 { MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8 { MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9 { MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xbb { MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc { MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd { MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xbf { MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc2 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc3 { MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc7 { MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8 { MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9 { MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xcb { MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc { MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd { MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xcf { MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd2 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd3 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd7 { MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8 { MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xda { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdb { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdc { MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd { MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdf { MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe2 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe3 { MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5 { MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe7 { MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8 { MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xeb { MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec { MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed { MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xef { MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf2 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf3 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5 { MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf7 { MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8 { MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9 { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfa { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfb { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfc { MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd { MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe { MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xff capstone-sys-0.15.0/capstone/arch/MOS65XX/m65816.inc000064400000000000000000000370000072674642500175520ustar 00000000000000{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01 { MOS65XX_INS_COP , MOS65XX_AM_INT , 1 }, // 0x02 { MOS65XX_INS_ORA , MOS65XX_AM_SR , 1 }, // 0x03 { MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04 { MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05 { MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x07 { MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08 { MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09 { MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a { MOS65XX_INS_PHD , MOS65XX_AM_IMP , 0 }, // 0x0b { MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c { MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d { MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e { MOS65XX_INS_ORA , MOS65XX_AM_ABS_LONG , 3 }, // 0x0f { MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12 { MOS65XX_INS_ORA , MOS65XX_AM_SR_IND_Y , 1 }, // 0x13 { MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15 { MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x17 { MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18 { MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19 { MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a { MOS65XX_INS_TCS , MOS65XX_AM_IMP , 0 }, // 0x1b { MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c { MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d { MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e { MOS65XX_INS_ORA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x1f { MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21 { MOS65XX_INS_JSL , MOS65XX_AM_ABS_LONG , 3 }, // 0x22 { MOS65XX_INS_AND , MOS65XX_AM_SR , 1 }, // 0x23 { MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24 { MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25 { MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x27 { MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28 { MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29 { MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a { MOS65XX_INS_PLD , MOS65XX_AM_IMP , 0 }, // 0x2b { MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c { MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d { MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e { MOS65XX_INS_AND , MOS65XX_AM_ABS_LONG , 3 }, // 0x2f { MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32 { MOS65XX_INS_AND , MOS65XX_AM_SR_IND_Y , 1 }, // 0x33 { MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35 { MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x37 { MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38 { MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39 { MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a { MOS65XX_INS_TSC , MOS65XX_AM_IMP , 0 }, // 0x3b { MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c { MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d { MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e { MOS65XX_INS_AND , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x3f { MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41 { MOS65XX_INS_WDM , MOS65XX_AM_INT , 1 }, // 0x42 { MOS65XX_INS_EOR , MOS65XX_AM_SR , 1 }, // 0x43 { MOS65XX_INS_MVP , MOS65XX_AM_BLOCK , 2 }, // 0x44 { MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45 { MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x47 { MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48 { MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49 { MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a { MOS65XX_INS_PHK , MOS65XX_AM_IMP , 0 }, // 0x4b { MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c { MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d { MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e { MOS65XX_INS_EOR , MOS65XX_AM_ABS_LONG , 3 }, // 0x4f { MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52 { MOS65XX_INS_EOR , MOS65XX_AM_SR_IND_Y , 1 }, // 0x53 { MOS65XX_INS_MVN , MOS65XX_AM_BLOCK , 2 }, // 0x54 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55 { MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x57 { MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58 { MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59 { MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a { MOS65XX_INS_TCD , MOS65XX_AM_IMP , 0 }, // 0x5b { MOS65XX_INS_JML , MOS65XX_AM_ABS_LONG , 3 }, // 0x5c { MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d { MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e { MOS65XX_INS_EOR , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x5f { MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61 { MOS65XX_INS_PER , MOS65XX_AM_REL , 2 }, // 0x62 { MOS65XX_INS_ADC , MOS65XX_AM_SR , 1 }, // 0x63 { MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64 { MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65 { MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x67 { MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68 { MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69 { MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a { MOS65XX_INS_RTL , MOS65XX_AM_IMP , 0 }, // 0x6b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c { MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d { MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e { MOS65XX_INS_ADC , MOS65XX_AM_ABS_LONG , 3 }, // 0x6f { MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72 { MOS65XX_INS_ADC , MOS65XX_AM_SR_IND_Y , 1 }, // 0x73 { MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75 { MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x77 { MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78 { MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79 { MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a { MOS65XX_INS_TDC , MOS65XX_AM_IMP , 0 }, // 0x7b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c { MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d { MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e { MOS65XX_INS_ADC , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x7f { MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81 { MOS65XX_INS_BRL , MOS65XX_AM_REL , 2 }, // 0x82 { MOS65XX_INS_STA , MOS65XX_AM_SR , 1 }, // 0x83 { MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84 { MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85 { MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x87 { MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88 { MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89 { MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a { MOS65XX_INS_PHB , MOS65XX_AM_IMP , 0 }, // 0x8b { MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c { MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d { MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e { MOS65XX_INS_STA , MOS65XX_AM_ABS_LONG , 3 }, // 0x8f { MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92 { MOS65XX_INS_STA , MOS65XX_AM_SR_IND_Y , 1 }, // 0x93 { MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95 { MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x97 { MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98 { MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99 { MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a { MOS65XX_INS_TXY , MOS65XX_AM_IMP , 0 }, // 0x9b { MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c { MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d { MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e { MOS65XX_INS_STA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x9f { MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1 { MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2 { MOS65XX_INS_LDA , MOS65XX_AM_SR , 1 }, // 0xa3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xa7 { MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8 { MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9 { MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa { MOS65XX_INS_PLB , MOS65XX_AM_IMP , 0 }, // 0xab { MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac { MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad { MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae { MOS65XX_INS_LDA , MOS65XX_AM_ABS_LONG , 3 }, // 0xaf { MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2 { MOS65XX_INS_LDA , MOS65XX_AM_SR_IND_Y , 1 }, // 0xb3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xb7 { MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8 { MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9 { MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba { MOS65XX_INS_TYX , MOS65XX_AM_IMP , 0 }, // 0xbb { MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc { MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd { MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe { MOS65XX_INS_LDA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xbf { MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1 { MOS65XX_INS_REP , MOS65XX_AM_IMM , 1 }, // 0xc2 { MOS65XX_INS_CMP , MOS65XX_AM_SR , 1 }, // 0xc3 { MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xc7 { MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8 { MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9 { MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca { MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb { MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc { MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd { MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce { MOS65XX_INS_CMP , MOS65XX_AM_ABS_LONG , 3 }, // 0xcf { MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2 { MOS65XX_INS_CMP , MOS65XX_AM_SR_IND_Y , 1 }, // 0xd3 { MOS65XX_INS_PEI , MOS65XX_AM_ZP_IND , 1 }, // 0xd4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xd7 { MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8 { MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9 { MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda { MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb { MOS65XX_INS_JML , MOS65XX_AM_ABS_IND_LONG , 2 }, // 0xdc { MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd { MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde { MOS65XX_INS_CMP , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xdf { MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1 { MOS65XX_INS_SEP , MOS65XX_AM_IMM , 1 }, // 0xe2 { MOS65XX_INS_SBC , MOS65XX_AM_SR , 1 }, // 0xe3 { MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5 { MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xe7 { MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8 { MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea { MOS65XX_INS_XBA , MOS65XX_AM_IMP , 0 }, // 0xeb { MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec { MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed { MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee { MOS65XX_INS_SBC , MOS65XX_AM_ABS_LONG , 3 }, // 0xef { MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2 { MOS65XX_INS_SBC , MOS65XX_AM_SR_IND_Y , 1 }, // 0xf3 { MOS65XX_INS_PEA , MOS65XX_AM_ABS , 2 }, // 0xf4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5 { MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xf7 { MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8 { MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9 { MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa { MOS65XX_INS_XCE , MOS65XX_AM_IMP , 0 }, // 0xfb { MOS65XX_INS_JSR , MOS65XX_AM_ABS_X_IND , 2 }, // 0xfc { MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd { MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe { MOS65XX_INS_SBC , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xff capstone-sys-0.15.0/capstone/arch/MOS65XX/m65c02.inc000064400000000000000000000370000072674642500176200ustar 00000000000000{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x02 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x03 { MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04 { MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05 { MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x07 { MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08 { MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09 { MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0b { MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c { MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d { MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0f { MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x13 { MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15 { MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x17 { MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18 { MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19 { MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1b { MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c { MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d { MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1f { MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x22 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x23 { MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24 { MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25 { MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x27 { MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28 { MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29 { MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2b { MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c { MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d { MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2f { MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x33 { MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35 { MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x37 { MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38 { MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39 { MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3b { MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c { MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d { MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3f { MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x42 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x43 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x44 { MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45 { MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x47 { MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48 { MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49 { MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4b { MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c { MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d { MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4f { MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x53 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x54 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55 { MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x57 { MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58 { MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59 { MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5b { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0x5c { MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d { MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5f { MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x62 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x63 { MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64 { MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65 { MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x67 { MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68 { MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69 { MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c { MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d { MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6f { MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x73 { MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75 { MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x77 { MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78 { MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79 { MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c { MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d { MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7f { MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x82 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x83 { MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84 { MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85 { MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x87 { MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88 { MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89 { MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8b { MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c { MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d { MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8f { MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x93 { MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95 { MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x97 { MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98 { MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99 { MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9b { MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c { MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d { MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9f { MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1 { MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa7 { MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8 { MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9 { MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xab { MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac { MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad { MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xaf { MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb7 { MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8 { MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9 { MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbb { MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc { MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd { MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbf { MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xc2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc3 { MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc7 { MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8 { MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9 { MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca { MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb { MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc { MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd { MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xcf { MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd3 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xd4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd7 { MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8 { MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9 { MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda { MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xdc { MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd { MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xdf { MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xe2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe3 { MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5 { MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe7 { MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8 { MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xeb { MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec { MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed { MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xef { MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf3 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xf4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5 { MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf7 { MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8 { MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9 { MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xfb { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xfc { MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd { MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xff capstone-sys-0.15.0/capstone/arch/MOS65XX/mw65c02.inc000064400000000000000000000370000072674642500200070ustar 00000000000000{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x02 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x03 { MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04 { MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05 { MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x07 { MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08 { MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09 { MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0b { MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c { MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d { MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x0f { MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x13 { MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14 { MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15 { MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x17 { MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18 { MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19 { MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1b { MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c { MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d { MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x1f { MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x22 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x23 { MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24 { MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25 { MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x27 { MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28 { MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29 { MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2b { MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c { MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d { MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x2f { MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31 { MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x33 { MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34 { MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35 { MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x37 { MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38 { MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39 { MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3b { MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c { MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d { MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x3f { MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x42 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x43 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x44 { MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45 { MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x47 { MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48 { MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49 { MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4b { MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c { MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d { MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x4f { MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x53 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x54 { MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55 { MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x57 { MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58 { MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59 { MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5b { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0x5c { MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d { MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x5f { MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x62 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x63 { MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64 { MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65 { MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x67 { MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68 { MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69 { MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c { MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d { MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x6f { MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x73 { MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74 { MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75 { MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76 { MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x77 { MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78 { MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79 { MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7b { MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c { MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d { MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e { MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x7f { MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x82 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x83 { MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84 { MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85 { MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0x87 { MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88 { MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89 { MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8b { MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c { MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d { MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0x8f { MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91 { MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x93 { MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94 { MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95 { MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0x97 { MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98 { MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99 { MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9b { MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c { MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d { MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0x9f { MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1 { MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xa7 { MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8 { MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9 { MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xab { MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac { MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad { MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xaf { MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb3 { MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4 { MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5 { MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xb7 { MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8 { MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9 { MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbb { MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc { MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd { MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xbf { MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xc2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc3 { MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xc7 { MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8 { MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9 { MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca { MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb { MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc { MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd { MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xcf { MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd3 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xd4 { MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5 { MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xd7 { MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8 { MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9 { MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda { MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xdc { MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd { MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xdf { MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xe2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe3 { MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5 { MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xe7 { MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8 { MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xeb { MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec { MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed { MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xef { MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf3 { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xf4 { MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5 { MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6 { MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xf7 { MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8 { MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9 { MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xfb { MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xfc { MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd { MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe { MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xff capstone-sys-0.15.0/capstone/arch/Mips/MipsDisassembler.c000064400000000000000000001454530072674642500214560ustar 00000000000000//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file is part of the Mips Disassembler. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_MIPS #include #include #include "capstone/platform.h" #include "MipsDisassembler.h" #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" #include "../../MathExtras.h" //#include "Mips.h" //#include "MipsRegisterInfo.h" //#include "MipsSubtarget.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCInst.h" //#include "llvm/MC/MCSubtargetInfo.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeJumpTarget(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is // shifted left by 1 bit. static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is // shifted left by 1 bit. static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); // DecodeBranchTargetMM - Decode microMIPS branch offset, which is // shifted left by 1 bit. static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); // DecodeJumpTargetMM - Decode microMIPS jump target, which is // shifted left by 1 bit. static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeCacheOpR6(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMemMMImm4(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeLiSimm7(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeSimm4(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeSimm16(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); // Decode the immediate field of an LSA instruction which // is off by one. static DecodeStatus DecodeLSAImm(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeInsSize(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeExtSize(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't /// handle. static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); static DecodeStatus DecodeMovePRegPair(MCInst *Inst, uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder); #define GET_SUBTARGETINFO_ENUM #include "MipsGenSubtargetInfo.inc" // Hacky: enable all features for disassembler static uint64_t getFeatureBits(int mode) { uint64_t Bits = (uint64_t)-1; // include every features at first // By default we do not support Mips1 Bits &= ~Mips_FeatureMips1; // No MicroMips Bits &= ~Mips_FeatureMicroMips; // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() // some features are mutually execlusive if (mode & CS_MODE_16) { //Bits &= ~Mips_FeatureMips32r2; //Bits &= ~Mips_FeatureMips32; //Bits &= ~Mips_FeatureFPIdx; //Bits &= ~Mips_FeatureBitCount; //Bits &= ~Mips_FeatureSwap; //Bits &= ~Mips_FeatureSEInReg; //Bits &= ~Mips_FeatureMips64r2; //Bits &= ~Mips_FeatureFP64Bit; } else if (mode & CS_MODE_32) { Bits &= ~Mips_FeatureMips16; Bits &= ~Mips_FeatureFP64Bit; Bits &= ~Mips_FeatureMips64r2; Bits &= ~Mips_FeatureMips32r6; Bits &= ~Mips_FeatureMips64r6; } else if (mode & CS_MODE_64) { Bits &= ~Mips_FeatureMips16; Bits &= ~Mips_FeatureMips64r6; Bits &= ~Mips_FeatureMips32r6; } else if (mode & CS_MODE_MIPS32R6) { Bits |= Mips_FeatureMips32r6; Bits &= ~Mips_FeatureMips16; Bits &= ~Mips_FeatureFP64Bit; Bits &= ~Mips_FeatureMips64r6; Bits &= ~Mips_FeatureMips64r2; } if (mode & CS_MODE_MICRO) { Bits |= Mips_FeatureMicroMips; Bits &= ~Mips_FeatureMips4_32r2; Bits &= ~Mips_FeatureMips2; } return Bits; } #include "MipsGenDisassemblerTables.inc" #define GET_REGINFO_ENUM #include "MipsGenRegisterInfo.inc" #define GET_REGINFO_MC_DESC #include "MipsGenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" void Mips_init(MCRegisterInfo *MRI) { // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, // MipsMCRegisterClasses, 62, // MipsRegUnitRoots, // 273, // MipsRegDiffLists, // MipsLaneMaskLists, // MipsRegStrings, // MipsRegClassStrings, // MipsSubRegIdxLists, // 12, // MipsSubRegIdxRanges, // MipsRegEncodingTable); MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, 0, 0, MipsMCRegisterClasses, 62, 0, 0, MipsRegDiffLists, 0, MipsSubRegIdxLists, 12, 0); } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted /// according to the given endianess. static void readInstruction16(unsigned char *code, uint32_t *insn, bool isBigEndian) { // We want to read exactly 2 Bytes of data. if (isBigEndian) *insn = (code[0] << 8) | code[1]; else *insn = (code[1] << 8) | code[0]; } /// readInstruction - read four bytes from the MemoryObject /// and return 32 bit word sorted according to the given endianess static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) { // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) // always precede the low 16 bits in the instruction stream (that is, they // are placed at lower addresses in the instruction stream). // // microMIPS byte ordering: // Big-endian: 0 | 1 | 2 | 3 // Little-endian: 1 | 0 | 3 | 2 // We want to read exactly 4 Bytes of data. if (isBigEndian) { // Encoded as a big-endian 32-bit word in the stream. *insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); } else { if (isMicroMips) { *insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) | ((uint32_t) code[1] << 24); } else { *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24); } } } static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) { uint32_t Insn; DecodeStatus Result; if (instr->flat_insn->detail) { memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips)); } if (mode & CS_MODE_MICRO) { if (code_len < 2) // not enough data return MCDisassembler_Fail; readInstruction16((unsigned char*)code, &Insn, isBigEndian); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 2; return Result; } if (code_len < 4) // not enough data return MCDisassembler_Fail; readInstruction32((unsigned char*)code, &Insn, isBigEndian, true); //DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 4; return Result; } return MCDisassembler_Fail; } if (code_len < 4) // not enough data return MCDisassembler_Fail; readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) { // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 4; return Result; } } if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) { // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 4; return Result; } } if (mode & CS_MODE_MIPS32R6) { // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 4; return Result; } } if (mode & CS_MODE_MIPS64) { // DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 4; return Result; } } // DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 4; return Result; } return MCDisassembler_Fail; } bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { cs_struct *handle = (cs_struct *)(uintptr_t)ud; DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, code, code_len, size, address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); return status == MCDisassembler_Success; } static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) { const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); return rc->RegsBegin[RegNo]; } static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); // The size of the n field depends on the element size // The register class also depends on this. uint32_t tmp = fieldFromInstruction(insn, 17, 5); unsigned NSize = 0; DecodeFN RegDecoder = NULL; if ((tmp & 0x18) == 0x00) { // INSVE_B NSize = 4; RegDecoder = DecodeMSA128BRegisterClass; } else if ((tmp & 0x1c) == 0x10) { // INSVE_H NSize = 3; RegDecoder = DecodeMSA128HRegisterClass; } else if ((tmp & 0x1e) == 0x18) { // INSVE_W NSize = 2; RegDecoder = DecodeMSA128WRegisterClass; } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D NSize = 1; RegDecoder = DecodeMSA128DRegisterClass; } //else llvm_unreachable("Invalid encoding"); //assert(NSize != 0 && RegDecoder != nullptr); if (NSize == 0 || RegDecoder == NULL) return MCDisassembler_Fail; // $wd tmp = fieldFromInstruction(insn, 6, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; // $wd_in if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; // $n tmp = fieldFromInstruction(insn, 16, NSize); MCOperand_CreateImm0(MI, tmp); // $ws tmp = fieldFromInstruction(insn, 11, 5); if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; // $n2 MCOperand_CreateImm0(MI, 0); return MCDisassembler_Success; } static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier // ISA's instead). // // We have: // 0b001000 sssss ttttt iiiiiiiiiiiiiiii // BOVC if rs >= rt // BEQZALC if rs == 0 && rt != 0 // BEQC if rs < rt && rs != 0 uint32_t Rs = fieldFromInstruction(insn, 21, 5); uint32_t Rt = fieldFromInstruction(insn, 16, 5); uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rs >= Rt) { MCInst_setOpcode(MI, Mips_BOVC); HasRs = true; } else if (Rs != 0 && Rs < Rt) { MCInst_setOpcode(MI, Mips_BEQC); HasRs = true; } else MCInst_setOpcode(MI, Mips_BEQZALC); if (HasRs) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); MCOperand_CreateImm0(MI, Imm); return MCDisassembler_Success; } static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the ADDI instruction from the earlier // ISA's instead). // // We have: // 0b011000 sssss ttttt iiiiiiiiiiiiiiii // BNVC if rs >= rt // BNEZALC if rs == 0 && rt != 0 // BNEC if rs < rt && rs != 0 uint32_t Rs = fieldFromInstruction(insn, 21, 5); uint32_t Rt = fieldFromInstruction(insn, 16, 5); uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rs >= Rt) { MCInst_setOpcode(MI, Mips_BNVC); HasRs = true; } else if (Rs != 0 && Rs < Rt) { MCInst_setOpcode(MI, Mips_BNEC); HasRs = true; } else MCInst_setOpcode(MI, Mips_BNEZALC); if (HasRs) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); MCOperand_CreateImm0(MI, Imm); return MCDisassembler_Success; } static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier // ISA's instead). // // We have: // 0b010110 sssss ttttt iiiiiiiiiiiiiiii // Invalid if rs == 0 // BLEZC if rs == 0 && rt != 0 // BGEZC if rs == rt && rt != 0 // BGEC if rs != rt && rs != 0 && rt != 0 uint32_t Rs = fieldFromInstruction(insn, 21, 5); uint32_t Rt = fieldFromInstruction(insn, 16, 5); uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) MCInst_setOpcode(MI, Mips_BLEZC); else if (Rs == Rt) MCInst_setOpcode(MI, Mips_BGEZC); else { HasRs = true; MCInst_setOpcode(MI, Mips_BGEC); } if (HasRs) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); MCOperand_CreateImm0(MI, Imm); return MCDisassembler_Success; } static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZL instruction from the earlier // ISA's instead). // // We have: // 0b010111 sssss ttttt iiiiiiiiiiiiiiii // Invalid if rs == 0 // BGTZC if rs == 0 && rt != 0 // BLTZC if rs == rt && rt != 0 // BLTC if rs != rt && rs != 0 && rt != 0 bool HasRs = false; uint32_t Rs = fieldFromInstruction(insn, 21, 5); uint32_t Rt = fieldFromInstruction(insn, 16, 5); uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) MCInst_setOpcode(MI, Mips_BGTZC); else if (Rs == Rt) MCInst_setOpcode(MI, Mips_BLTZC); else { MCInst_setOpcode(MI, Mips_BLTC); HasRs = true; } if (HasRs) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); MCOperand_CreateImm0(MI, Imm); return MCDisassembler_Success; } static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BGTZ instruction from the earlier // ISA's instead). // // We have: // 0b000111 sssss ttttt iiiiiiiiiiiiiiii // BGTZ if rt == 0 // BGTZALC if rs == 0 && rt != 0 // BLTZALC if rs != 0 && rs == rt // BLTUC if rs != 0 && rs != rt uint32_t Rs = fieldFromInstruction(insn, 21, 5); uint32_t Rt = fieldFromInstruction(insn, 16, 5); uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; bool HasRt = false; if (Rt == 0) { MCInst_setOpcode(MI, Mips_BGTZ); HasRs = true; } else if (Rs == 0) { MCInst_setOpcode(MI, Mips_BGTZALC); HasRt = true; } else if (Rs == Rt) { MCInst_setOpcode(MI, Mips_BLTZALC); HasRs = true; } else { MCInst_setOpcode(MI, Mips_BLTUC); HasRs = true; HasRt = true; } if (HasRs) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); if (HasRt) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); MCOperand_CreateImm0(MI, Imm); return MCDisassembler_Success; } static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder) { // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled // (otherwise we would have matched the BLEZL instruction from the earlier // ISA's instead). // // We have: // 0b000110 sssss ttttt iiiiiiiiiiiiiiii // Invalid if rs == 0 // BLEZALC if rs == 0 && rt != 0 // BGEZALC if rs == rt && rt != 0 // BGEUC if rs != rt && rs != 0 && rt != 0 uint32_t Rs = fieldFromInstruction(insn, 21, 5); uint32_t Rt = fieldFromInstruction(insn, 16, 5); uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rt == 0) return MCDisassembler_Fail; else if (Rs == 0) MCInst_setOpcode(MI, Mips_BLEZALC); else if (Rs == Rt) MCInst_setOpcode(MI, Mips_BGEZALC); else { HasRs = true; MCInst_setOpcode(MI, Mips_BGEUC); } if (HasRs) MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); MCOperand_CreateImm0(MI, Imm); return MCDisassembler_Success; } static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { return MCDisassembler_Fail; } static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 7) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 7) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 7) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { // if (static_cast(Decoder)->isGP64()) if (Inst->csh->mode & CS_MODE_MIPS64) return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 7) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 7) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeMem(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); int opcode = MCInst_getOpcode(Inst); Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); if (opcode == Mips_SC || opcode == Mips_SCD) { MCOperand_CreateReg0(Inst, Reg); } MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeCacheOp(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Hint = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); MCOperand_CreateImm0(Inst, Hint); return MCDisassembler_Success; } static DecodeStatus DecodeCacheOpMM(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xfff, 12); unsigned Base = fieldFromInstruction(Insn, 16, 5); unsigned Hint = fieldFromInstruction(Insn, 21, 5); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); MCOperand_CreateImm0(Inst, Hint); return MCDisassembler_Success; } static DecodeStatus DecodeCacheOpR6(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = fieldFromInstruction(Insn, 7, 9); unsigned Hint = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); MCOperand_CreateImm0(Inst, Hint); return MCDisassembler_Success; } static DecodeStatus DecodeSyncI(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Base = fieldFromInstruction(Insn, 21, 5); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); unsigned Reg = fieldFromInstruction(Insn, 6, 5); unsigned Base = fieldFromInstruction(Insn, 11, 5); Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); // MCOperand_CreateImm0(Inst, Offset); // The immediate field of an LD/ST instruction is scaled which means it must // be multiplied (when decoding) by the size (in bytes) of the instructions' // data format. // .b - 1 byte // .h - 2 bytes // .w - 4 bytes // .d - 8 bytes switch(MCInst_getOpcode(Inst)) { default: //assert (0 && "Unexpected instruction"); return MCDisassembler_Fail; break; case Mips_LD_B: case Mips_ST_B: MCOperand_CreateImm0(Inst, Offset); break; case Mips_LD_H: case Mips_ST_H: MCOperand_CreateImm0(Inst, Offset * 2); break; case Mips_LD_W: case Mips_ST_W: MCOperand_CreateImm0(Inst, Offset * 4); break; case Mips_LD_D: case Mips_ST_D: MCOperand_CreateImm0(Inst, Offset * 8); break; } return MCDisassembler_Success; } static DecodeStatus DecodeMemMMImm4(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Offset = Insn & 0xf; unsigned Reg = fieldFromInstruction(Insn, 7, 3); unsigned Base = fieldFromInstruction(Insn, 4, 3); switch (MCInst_getOpcode(Inst)) { case Mips_LBU16_MM: case Mips_LHU16_MM: case Mips_LW16_MM: if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; break; case Mips_SB16_MM: case Mips_SH16_MM: case Mips_SW16_MM: if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; break; } if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; switch (MCInst_getOpcode(Inst)) { case Mips_LBU16_MM: if (Offset == 0xf) MCOperand_CreateImm0(Inst, -1); else MCOperand_CreateImm0(Inst, Offset); break; case Mips_SB16_MM: MCOperand_CreateImm0(Inst, Offset); break; case Mips_LHU16_MM: case Mips_SH16_MM: MCOperand_CreateImm0(Inst, Offset << 1); break; case Mips_LW16_MM: case Mips_SW16_MM: MCOperand_CreateImm0(Inst, Offset << 2); break; } return MCDisassembler_Success; } static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Offset = Insn & 0x1F; unsigned Reg = fieldFromInstruction(Insn, 5, 5); Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Mips_SP); MCOperand_CreateImm0(Inst, Offset << 2); return MCDisassembler_Success; } static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Offset = Insn & 0x7F; unsigned Reg = fieldFromInstruction(Insn, 7, 3); Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Mips_GP); MCOperand_CreateImm0(Inst, Offset << 2); return MCDisassembler_Success; } static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xf, 4); if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, Mips_SP); MCOperand_CreateImm0(Inst, Offset * 4); return MCDisassembler_Success; } static DecodeStatus DecodeMemMMImm12(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0x0fff, 12); unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5); Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); switch (MCInst_getOpcode(Inst)) { case Mips_SWM32_MM: case Mips_LWM32_MM: if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); break; case Mips_SC_MM: MCOperand_CreateReg0(Inst, Reg); // fallthrough default: MCOperand_CreateReg0(Inst, Reg); if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM) MCOperand_CreateReg0(Inst, Reg + 1); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); } return MCDisassembler_Success; } static DecodeStatus DecodeMemMMImm16(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5); Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0xffff, 16); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int Offset = SignExtend32(Insn & 0x07ff, 11); unsigned Reg = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 11, 5); Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); MCOperand_CreateReg0(Inst, Reg); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); unsigned Rt = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 21, 5); Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); Base = getReg(Decoder, Mips_GPR32RegClassID, Base); if (MCInst_getOpcode(Inst) == Mips_SC_R6 || MCInst_getOpcode(Inst) == Mips_SCD_R6) { MCOperand_CreateReg0(Inst, Rt); } MCOperand_CreateReg0(Inst, Rt); MCOperand_CreateReg0(Inst, Base); MCOperand_CreateImm0(Inst, Offset); return MCDisassembler_Success; } static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { // Currently only hardware register 29 is supported. if (RegNo != 29) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, Mips_HWR29); return MCDisassembler_Success; } static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 30 || RegNo % 2) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo >= 4) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo >= 4) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo >= 4) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 7) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) { uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; MCOperand_CreateImm0(Inst, TargetAddress); return MCDisassembler_Success; } static DecodeStatus DecodeJumpTarget(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); MCOperand_CreateImm0(Inst, TargetAddress); return MCDisassembler_Success; } static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) { int32_t BranchOffset = SignExtend32(Offset, 21) * 4; MCOperand_CreateImm0(Inst, BranchOffset); return MCDisassembler_Success; } static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) { int32_t BranchOffset = SignExtend32(Offset, 26) * 4; MCOperand_CreateImm0(Inst, BranchOffset); return MCDisassembler_Success; } static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) { int32_t BranchOffset = SignExtend32(Offset, 7) * 2; MCOperand_CreateImm0(Inst, BranchOffset); return MCDisassembler_Success; } static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) { int32_t BranchOffset = SignExtend32(Offset, 10) * 2; MCOperand_CreateImm0(Inst, BranchOffset); return MCDisassembler_Success; } static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) { int32_t BranchOffset = SignExtend32(Offset, 16) * 2; MCOperand_CreateImm0(Inst, BranchOffset); return MCDisassembler_Success; } static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; MCOperand_CreateImm0(Inst, JumpOffset); return MCDisassembler_Success; } static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) { if (Value == 0) MCOperand_CreateImm0(Inst, 1); else if (Value == 0x7) MCOperand_CreateImm0(Inst, -1); else MCOperand_CreateImm0(Inst, Value << 2); return MCDisassembler_Success; } static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, Value << 2); return MCDisassembler_Success; } static DecodeStatus DecodeLiSimm7(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) { if (Value == 0x7F) MCOperand_CreateImm0(Inst, -1); else MCOperand_CreateImm0(Inst, Value); return MCDisassembler_Success; } static DecodeStatus DecodeSimm4(MCInst *Inst, unsigned Value, uint64_t Address, MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Value, 4)); return MCDisassembler_Success; } static DecodeStatus DecodeSimm16(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); return MCDisassembler_Success; } static DecodeStatus DecodeLSAImm(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { // We add one to the immediate field as it was encoded as 'imm - 1'. MCOperand_CreateImm0(Inst, Insn + 1); return MCDisassembler_Success; } static DecodeStatus DecodeInsSize(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { // First we need to grab the pos(lsb) from MCInst. int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); int Size = (int) Insn - Pos + 1; MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); return MCDisassembler_Success; } static DecodeStatus DecodeExtSize(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { int Size = (int)Insn + 1; MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); return MCDisassembler_Success; } static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); return MCDisassembler_Success; } static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); return MCDisassembler_Success; } static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { int32_t DecodedValue; switch (Insn) { case 0: DecodedValue = 256; break; case 1: DecodedValue = 257; break; case 510: DecodedValue = -258; break; case 511: DecodedValue = -257; break; default: DecodedValue = SignExtend32(Insn, 9); break; } MCOperand_CreateImm0(Inst, DecodedValue * 4); return MCDisassembler_Success; } static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { // Insn must be >= 0, since it is unsigned that condition is always true. // assert(Insn < 16); int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535}; if (Insn >= 16) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, DecodedValues[Insn]); return MCDisassembler_Success; } static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, Insn << 2); return MCDisassembler_Success; } static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) { unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_FP}; unsigned RegNum; unsigned int i; unsigned RegLst = fieldFromInstruction(Insn, 21, 5); // Empty register lists are not allowed. if (RegLst == 0) return MCDisassembler_Fail; RegNum = RegLst & 0xf; for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++) MCOperand_CreateReg0(Inst, Regs[i]); if (RegLst & 0x10) MCOperand_CreateReg0(Inst, Mips_RA); return MCDisassembler_Success; } static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3}; unsigned RegLst = fieldFromInstruction(Insn, 4, 2); unsigned RegNum = RegLst & 0x3; unsigned int i; for (i = 0; i <= RegNum; i++) MCOperand_CreateReg0(Inst, Regs[i]); MCOperand_CreateReg0(Inst, Mips_RA); return MCDisassembler_Success; } static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { unsigned RegPair = fieldFromInstruction(Insn, 7, 3); switch (RegPair) { default: return MCDisassembler_Fail; case 0: MCOperand_CreateReg0(Inst, Mips_A1); MCOperand_CreateReg0(Inst, Mips_A2); break; case 1: MCOperand_CreateReg0(Inst, Mips_A1); MCOperand_CreateReg0(Inst, Mips_A3); break; case 2: MCOperand_CreateReg0(Inst, Mips_A2); MCOperand_CreateReg0(Inst, Mips_A3); break; case 3: MCOperand_CreateReg0(Inst, Mips_A0); MCOperand_CreateReg0(Inst, Mips_S5); break; case 4: MCOperand_CreateReg0(Inst, Mips_A0); MCOperand_CreateReg0(Inst, Mips_S6); break; case 5: MCOperand_CreateReg0(Inst, Mips_A0); MCOperand_CreateReg0(Inst, Mips_A1); break; case 6: MCOperand_CreateReg0(Inst, Mips_A0); MCOperand_CreateReg0(Inst, Mips_A2); break; case 7: MCOperand_CreateReg0(Inst, Mips_A0); MCOperand_CreateReg0(Inst, Mips_A3); break; } return MCDisassembler_Success; } static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) { MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4); return MCDisassembler_Success; } #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsDisassembler.h000064400000000000000000000006550072674642500214550ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_MIPSDISASSEMBLER_H #define CS_MIPSDISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCInst.h" #include "../../MCRegisterInfo.h" void Mips_init(MCRegisterInfo *MRI); bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsGenAsmWriter.inc000064400000000000000000005211260072674642500217320ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) { static const uint32_t OpInfo[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 9396U, // DBG_VALUE 0U, // REG_SEQUENCE 0U, // COPY 9389U, // BUNDLE 9406U, // LIFETIME_START 9376U, // LIFETIME_END 0U, // STACKMAP 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // FRAME_ALLOC 21660U, // ABSQ_S_PH 18025U, // ABSQ_S_QB 24850U, // ABSQ_S_W 134237992U, // ADD 18294U, // ADDIUPC 18294U, // ADDIUPC_MM 22527U, // ADDIUR1SP_MM 134234410U, // ADDIUR2_MM 8683851U, // ADDIUS5_MM 546875U, // ADDIUSP_MM 134239193U, // ADDQH_PH 134239310U, // ADDQH_R_PH 134242253U, // ADDQH_R_W 134241856U, // ADDQH_W 134239267U, // ADDQ_PH 134239366U, // ADDQ_S_PH 134242558U, // ADDQ_S_W 134236055U, // ADDSC 134234730U, // ADDS_A_B 134236180U, // ADDS_A_D 134238138U, // ADDS_A_H 134241564U, // ADDS_A_W 134235198U, // ADDS_S_B 134237269U, // ADDS_S_D 134238695U, // ADDS_S_H 134242608U, // ADDS_S_W 134235413U, // ADDS_U_B 134237736U, // ADDS_U_D 134238973U, // ADDS_U_H 134243026U, // ADDS_U_W 134234575U, // ADDU16_MM 134235621U, // ADDUH_QB 134235729U, // ADDUH_R_QB 134239465U, // ADDU_PH 134235834U, // ADDU_QB 134239410U, // ADDU_S_PH 134235775U, // ADDU_S_QB 2281718627U, // ADDVI_B 2281720348U, // ADDVI_D 2281722002U, // ADDVI_H 2281725637U, // ADDVI_W 134235491U, // ADDV_B 134237836U, // ADDV_D 134239051U, // ADDV_H 134243126U, // ADDV_W 134236094U, // ADDWC 134234712U, // ADD_A_B 134236161U, // ADD_A_D 134238120U, // ADD_A_H 134241545U, // ADD_A_W 134237992U, // ADD_MM 134239685U, // ADDi 134239685U, // ADDi_MM 134241307U, // ADDiu 134241307U, // ADDiu_MM 134241261U, // ADDu 134241261U, // ADDu_MM 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 134240158U, // ALIGN 18286U, // ALUIPC 134238014U, // AND 835930U, // AND16_MM 134238014U, // AND64 134234471U, // ANDI16_MM 2281718486U, // ANDI_B 134238014U, // AND_MM 134241389U, // AND_V 0U, // AND_V_D_PSEUDO 0U, // AND_V_H_PSEUDO 0U, // AND_V_W_PSEUDO 134239691U, // ANDi 134239691U, // ANDi64 134239691U, // ANDi_MM 134238028U, // APPEND 134235092U, // ASUB_S_B 134237099U, // ASUB_S_D 134238527U, // ASUB_S_H 134242388U, // ASUB_S_W 134235307U, // ASUB_U_B 134237566U, // ASUB_U_D 134238815U, // ASUB_U_H 134242856U, // ASUB_U_W 0U, // ATOMIC_CMP_SWAP_I16 0U, // ATOMIC_CMP_SWAP_I32 0U, // ATOMIC_CMP_SWAP_I64 0U, // ATOMIC_CMP_SWAP_I8 0U, // ATOMIC_LOAD_ADD_I16 0U, // ATOMIC_LOAD_ADD_I32 0U, // ATOMIC_LOAD_ADD_I64 0U, // ATOMIC_LOAD_ADD_I8 0U, // ATOMIC_LOAD_AND_I16 0U, // ATOMIC_LOAD_AND_I32 0U, // ATOMIC_LOAD_AND_I64 0U, // ATOMIC_LOAD_AND_I8 0U, // ATOMIC_LOAD_NAND_I16 0U, // ATOMIC_LOAD_NAND_I32 0U, // ATOMIC_LOAD_NAND_I64 0U, // ATOMIC_LOAD_NAND_I8 0U, // ATOMIC_LOAD_OR_I16 0U, // ATOMIC_LOAD_OR_I32 0U, // ATOMIC_LOAD_OR_I64 0U, // ATOMIC_LOAD_OR_I8 0U, // ATOMIC_LOAD_SUB_I16 0U, // ATOMIC_LOAD_SUB_I32 0U, // ATOMIC_LOAD_SUB_I64 0U, // ATOMIC_LOAD_SUB_I8 0U, // ATOMIC_LOAD_XOR_I16 0U, // ATOMIC_LOAD_XOR_I32 0U, // ATOMIC_LOAD_XOR_I64 0U, // ATOMIC_LOAD_XOR_I8 0U, // ATOMIC_SWAP_I16 0U, // ATOMIC_SWAP_I32 0U, // ATOMIC_SWAP_I64 0U, // ATOMIC_SWAP_I8 134239795U, // AUI 18279U, // AUIPC 134235178U, // AVER_S_B 134237249U, // AVER_S_D 134238665U, // AVER_S_H 134242588U, // AVER_S_W 134235393U, // AVER_U_B 134237716U, // AVER_U_D 134238953U, // AVER_U_H 134243006U, // AVER_U_W 134235120U, // AVE_S_B 134237181U, // AVE_S_D 134238597U, // AVE_S_H 134242470U, // AVE_S_W 134235335U, // AVE_U_B 134237648U, // AVE_U_D 134238885U, // AVE_U_H 134242938U, // AVE_U_W 23579U, // AddiuRxImmX16 1072155U, // AddiuRxPcImmX16 285236251U, // AddiuRxRxImm16 16800795U, // AddiuRxRxImmX16 25189403U, // AddiuRxRyOffMemX16 1336343U, // AddiuSpImm16 549911U, // AddiuSpImmX16 134241261U, // AdduRxRyRz16 16797502U, // AndRxRxRy16 0U, // B 541013U, // B16_MM 134241260U, // BADDu 546393U, // BAL 542494U, // BALC 134240157U, // BALIGN 0U, // BAL_BR 167788585U, // BBIT0 167788717U, // BBIT032 167788710U, // BBIT1 167788726U, // BBIT132 542473U, // BC 20351U, // BC0F 22218U, // BC0FL 23455U, // BC0T 22347U, // BC0TL 25733U, // BC1EQZ 20357U, // BC1F 22225U, // BC1FL 20357U, // BC1F_MM 25717U, // BC1NEZ 23461U, // BC1T 22354U, // BC1TL 23461U, // BC1T_MM 25741U, // BC2EQZ 20363U, // BC2F 22232U, // BC2FL 25725U, // BC2NEZ 23467U, // BC2T 22361U, // BC2TL 20369U, // BC3F 22239U, // BC3FL 23473U, // BC3T 22368U, // BC3TL 2281718555U, // BCLRI_B 2281720292U, // BCLRI_D 2281721946U, // BCLRI_H 2281725581U, // BCLRI_W 134235059U, // BCLR_B 134237023U, // BCLR_D 134238494U, // BCLR_H 134242304U, // BCLR_W 134240340U, // BEQ 134240340U, // BEQ64 134236044U, // BEQC 134240063U, // BEQL 16882U, // BEQZ16_MM 18246U, // BEQZALC 18394U, // BEQZC 18394U, // BEQZC_MM 134240340U, // BEQ_MM 134235917U, // BGEC 134236068U, // BGEUC 25500U, // BGEZ 25500U, // BGEZ64 22115U, // BGEZAL 18219U, // BGEZALC 22311U, // BGEZALL 23424U, // BGEZALS_MM 22115U, // BGEZAL_MM 18373U, // BGEZC 22391U, // BGEZL 25500U, // BGEZ_MM 25560U, // BGTZ 25560U, // BGTZ64 18255U, // BGTZALC 18401U, // BGTZC 22405U, // BGTZL 25560U, // BGTZ_MM 2298495744U, // BINSLI_B 2298497481U, // BINSLI_D 2298499135U, // BINSLI_H 2298502770U, // BINSLI_W 151012243U, // BINSL_B 151014033U, // BINSL_D 151015601U, // BINSL_H 151019280U, // BINSL_W 2298495805U, // BINSRI_B 2298497526U, // BINSRI_D 2298499180U, // BINSRI_H 2298502815U, // BINSRI_W 151012291U, // BINSR_B 151014289U, // BINSR_D 151015726U, // BINSR_H 151019570U, // BINSR_W 23733U, // BITREV 22477U, // BITSWAP 25506U, // BLEZ 25506U, // BLEZ64 18228U, // BLEZALC 18380U, // BLEZC 22398U, // BLEZL 25506U, // BLEZ_MM 134236062U, // BLTC 134236075U, // BLTUC 25566U, // BLTZ 25566U, // BLTZ64 22123U, // BLTZAL 18264U, // BLTZALC 22320U, // BLTZALL 23433U, // BLTZALS_MM 22123U, // BLTZAL_MM 18408U, // BLTZC 22412U, // BLTZL 25566U, // BLTZ_MM 2298495860U, // BMNZI_B 151018662U, // BMNZ_V 2298495852U, // BMZI_B 151018648U, // BMZ_V 134238058U, // BNE 134238058U, // BNE64 134235923U, // BNEC 2281718494U, // BNEGI_B 2281720240U, // BNEGI_D 2281721894U, // BNEGI_H 2281725529U, // BNEGI_W 134234814U, // BNEG_B 134236568U, // BNEG_D 134238222U, // BNEG_H 134241776U, // BNEG_W 134239940U, // BNEL 16874U, // BNEZ16_MM 18237U, // BNEZALC 18387U, // BNEZC 18387U, // BNEZC_MM 134238058U, // BNE_MM 134236082U, // BNVC 17803U, // BNZ_B 20233U, // BNZ_D 21363U, // BNZ_H 23711U, // BNZ_V 25463U, // BNZ_W 134236088U, // BOVC 540871U, // BPOSGE32 0U, // BPOSGE32_PSEUDO 22080U, // BREAK 65909U, // BREAK16_MM 22080U, // BREAK_MM 2298495719U, // BSELI_B 0U, // BSEL_D_PSEUDO 0U, // BSEL_FD_PSEUDO 0U, // BSEL_FW_PSEUDO 0U, // BSEL_H_PSEUDO 151018620U, // BSEL_V 0U, // BSEL_W_PSEUDO 2281718609U, // BSETI_B 2281720330U, // BSETI_D 2281721984U, // BSETI_H 2281725619U, // BSETI_W 134235275U, // BSET_B 134237385U, // BSET_D 134238783U, // BSET_H 134242762U, // BSET_W 17797U, // BZ_B 20217U, // BZ_D 21357U, // BZ_H 23698U, // BZ_V 25457U, // BZ_W 541278U, // B_MM_Pseudo 402678723U, // BeqzRxImm16 25539U, // BeqzRxImmX16 1327710U, // Bimm16 541278U, // BimmX16 402678696U, // BnezRxImm16 25512U, // BnezRxImmX16 9368U, // Break16 1598417U, // Bteqz16 536893428U, // BteqzT8CmpX16 536892936U, // BteqzT8CmpiX16 536894397U, // BteqzT8SltX16 536892966U, // BteqzT8SltiX16 536894505U, // BteqzT8SltiuX16 536894541U, // BteqzT8SltuX16 549841U, // BteqzX16 1598390U, // Btnez16 671111156U, // BtnezT8CmpX16 671110664U, // BtnezT8CmpiX16 671112125U, // BtnezT8SltX16 671110694U, // BtnezT8SltiX16 671112233U, // BtnezT8SltiuX16 671112269U, // BtnezT8SltuX16 549814U, // BtnezX16 0U, // BuildPairF64 0U, // BuildPairF64_64 85859U, // CACHE 85859U, // CACHE_MM 85859U, // CACHE_R6 19003U, // CEIL_L_D64 23031U, // CEIL_L_S 20179U, // CEIL_W_D32 20179U, // CEIL_W_D64 20179U, // CEIL_W_MM 23353U, // CEIL_W_S 23353U, // CEIL_W_S_MM 134234890U, // CEQI_B 134236627U, // CEQI_D 134238281U, // CEQI_H 134241916U, // CEQI_W 134235044U, // CEQ_B 134236930U, // CEQ_D 134238472U, // CEQ_H 134242192U, // CEQ_W 16444U, // CFC1 16444U, // CFC1_MM 16968U, // CFCMSA 134243407U, // CINS 134243363U, // CINS32 19639U, // CLASS_D 23205U, // CLASS_S 134235129U, // CLEI_S_B 134237190U, // CLEI_S_D 134238606U, // CLEI_S_H 134242479U, // CLEI_S_W 2281718992U, // CLEI_U_B 2281721305U, // CLEI_U_D 2281722542U, // CLEI_U_H 2281726595U, // CLEI_U_W 134235111U, // CLE_S_B 134237172U, // CLE_S_D 134238588U, // CLE_S_H 134242461U, // CLE_S_W 134235326U, // CLE_U_B 134237639U, // CLE_U_D 134238876U, // CLE_U_H 134242929U, // CLE_U_W 22452U, // CLO 22452U, // CLO_MM 22452U, // CLO_R6 134235149U, // CLTI_S_B 134237210U, // CLTI_S_D 134238626U, // CLTI_S_H 134242499U, // CLTI_S_W 2281719012U, // CLTI_U_B 2281721325U, // CLTI_U_D 2281722562U, // CLTI_U_H 2281726615U, // CLTI_U_W 134235217U, // CLT_S_B 134237288U, // CLT_S_D 134238714U, // CLT_S_H 134242627U, // CLT_S_W 134235444U, // CLT_U_B 134237767U, // CLT_U_D 134239004U, // CLT_U_H 134243057U, // CLT_U_W 25534U, // CLZ 25534U, // CLZ_MM 25534U, // CLZ_R6 134235667U, // CMPGDU_EQ_QB 134235572U, // CMPGDU_LE_QB 134235786U, // CMPGDU_LT_QB 134235681U, // CMPGU_EQ_QB 134235586U, // CMPGU_LE_QB 134235800U, // CMPGU_LT_QB 17966U, // CMPU_EQ_QB 17871U, // CMPU_LE_QB 18085U, // CMPU_LT_QB 134236919U, // CMP_EQ_D 21548U, // CMP_EQ_PH 134240864U, // CMP_EQ_S 134236489U, // CMP_F_D 134240675U, // CMP_F_S 134236333U, // CMP_LE_D 21444U, // CMP_LE_PH 134240596U, // CMP_LE_S 134237410U, // CMP_LT_D 21717U, // CMP_LT_PH 134240959U, // CMP_LT_S 134236507U, // CMP_SAF_D 134240685U, // CMP_SAF_S 134236946U, // CMP_SEQ_D 134240883U, // CMP_SEQ_S 134236370U, // CMP_SLE_D 134240625U, // CMP_SLE_S 134237437U, // CMP_SLT_D 134240978U, // CMP_SLT_S 134236994U, // CMP_SUEQ_D 134240914U, // CMP_SUEQ_S 134236418U, // CMP_SULE_D 134240656U, // CMP_SULE_S 134237485U, // CMP_SULT_D 134241009U, // CMP_SULT_S 134236876U, // CMP_SUN_D 134240837U, // CMP_SUN_S 134236974U, // CMP_UEQ_D 134240903U, // CMP_UEQ_S 134236398U, // CMP_ULE_D 134240645U, // CMP_ULE_S 134237465U, // CMP_ULT_D 134240998U, // CMP_ULT_S 134236858U, // CMP_UN_D 134240827U, // CMP_UN_S 9454U, // CONSTPOOL_ENTRY 0U, // COPY_FD_PSEUDO 0U, // COPY_FW_PSEUDO 2952807544U, // COPY_S_B 2952809637U, // COPY_S_D 2952811052U, // COPY_S_H 2952814987U, // COPY_S_W 2952807759U, // COPY_U_B 2952810104U, // COPY_U_D 2952811319U, // COPY_U_H 2952815394U, // COPY_U_W 1867863U, // CTC1 1867863U, // CTC1_MM 16976U, // CTCMSA 22833U, // CVT_D32_S 23896U, // CVT_D32_W 23896U, // CVT_D32_W_MM 22087U, // CVT_D64_L 22833U, // CVT_D64_S 23896U, // CVT_D64_W 22833U, // CVT_D_S_MM 19024U, // CVT_L_D64 19024U, // CVT_L_D64_MM 23052U, // CVT_L_S 23052U, // CVT_L_S_MM 19362U, // CVT_S_D32 19362U, // CVT_S_D32_MM 19362U, // CVT_S_D64 22096U, // CVT_S_L 24651U, // CVT_S_W 24651U, // CVT_S_W_MM 20200U, // CVT_W_D32 20200U, // CVT_W_D64 20200U, // CVT_W_MM 23374U, // CVT_W_S 23374U, // CVT_W_S_MM 19183U, // C_EQ_D32 19183U, // C_EQ_D64 23128U, // C_EQ_S 18754U, // C_F_D32 18754U, // C_F_D64 22940U, // C_F_S 18597U, // C_LE_D32 18597U, // C_LE_D64 22860U, // C_LE_S 19674U, // C_LT_D32 19674U, // C_LT_D64 23223U, // C_LT_S 18588U, // C_NGE_D32 18588U, // C_NGE_D64 22851U, // C_NGE_S 18623U, // C_NGLE_D32 18623U, // C_NGLE_D64 22878U, // C_NGLE_S 19040U, // C_NGL_D32 19040U, // C_NGL_D64 23068U, // C_NGL_S 19665U, // C_NGT_D32 19665U, // C_NGT_D64 23214U, // C_NGT_S 18633U, // C_OLE_D32 18633U, // C_OLE_D64 22888U, // C_OLE_S 19700U, // C_OLT_D32 19700U, // C_OLT_D64 23241U, // C_OLT_S 19209U, // C_SEQ_D32 19209U, // C_SEQ_D64 23146U, // C_SEQ_S 18824U, // C_SF_D32 18824U, // C_SF_D64 22986U, // C_SF_S 19237U, // C_UEQ_D32 19237U, // C_UEQ_D64 23166U, // C_UEQ_S 18661U, // C_ULE_D32 18661U, // C_ULE_D64 22908U, // C_ULE_S 19728U, // C_ULT_D32 19728U, // C_ULT_D64 23261U, // C_ULT_S 19122U, // C_UN_D32 19122U, // C_UN_D64 23091U, // C_UN_S 22516U, // CmpRxRy16 939546120U, // CmpiRxImm16 22024U, // CmpiRxImmX16 549945U, // Constant32 134237991U, // DADD 134239684U, // DADDi 134241306U, // DADDiu 134241267U, // DADDu 8689123U, // DAHI 134240165U, // DALIGN 8689184U, // DATI 134239794U, // DAUI 22476U, // DBITSWAP 22451U, // DCLO 22451U, // DCLO_R6 25533U, // DCLZ 25533U, // DCLZ_R6 134241469U, // DDIV 134241377U, // DDIVU 9480U, // DERET 9480U, // DERET_MM 134243425U, // DEXT 134243400U, // DEXTM 134243438U, // DEXTU 546247U, // DI 134243413U, // DINS 134243393U, // DINSM 134243431U, // DINSU 134241470U, // DIV 134241378U, // DIVU 134235238U, // DIV_S_B 134237331U, // DIV_S_D 134238735U, // DIV_S_H 134242670U, // DIV_S_W 134235453U, // DIV_U_B 134237798U, // DIV_U_D 134239013U, // DIV_U_H 134243088U, // DIV_U_W 546247U, // DI_MM 134234690U, // DLSA 134234690U, // DLSA_R6 134234121U, // DMFC0 16450U, // DMFC1 134234372U, // DMFC2 134238036U, // DMOD 134241281U, // DMODU 134234128U, // DMTC0 1867869U, // DMTC1 134234379U, // DMTC2 134239671U, // DMUH 134241299U, // DMUHU 134240103U, // DMUL 23495U, // DMULT 23641U, // DMULTu 134241343U, // DMULU 134240103U, // DMUL_R6 134237239U, // DOTP_S_D 134238655U, // DOTP_S_H 134242538U, // DOTP_S_W 134237706U, // DOTP_U_D 134238943U, // DOTP_U_H 134242996U, // DOTP_U_W 151014368U, // DPADD_S_D 151015784U, // DPADD_S_H 151019657U, // DPADD_S_W 151014835U, // DPADD_U_D 151016072U, // DPADD_U_H 151020125U, // DPADD_U_W 134239524U, // DPAQX_SA_W_PH 134239607U, // DPAQX_S_W_PH 134241998U, // DPAQ_SA_L_W 134239566U, // DPAQ_S_W_PH 134239859U, // DPAU_H_QBL 134240355U, // DPAU_H_QBR 134239645U, // DPAX_W_PH 134239514U, // DPA_W_PH 22521U, // DPOP 134239539U, // DPSQX_SA_W_PH 134239621U, // DPSQX_S_W_PH 134242011U, // DPSQ_SA_L_W 134239594U, // DPSQ_S_W_PH 151014335U, // DPSUB_S_D 151015763U, // DPSUB_S_H 151019624U, // DPSUB_S_W 151014802U, // DPSUB_U_D 151016051U, // DPSUB_U_H 151020092U, // DPSUB_U_W 134239871U, // DPSU_H_QBL 134240367U, // DPSU_H_QBR 134239656U, // DPSX_W_PH 134239635U, // DPS_W_PH 134240512U, // DROTR 134234351U, // DROTR32 134241513U, // DROTRV 21370U, // DSBH 25610U, // DSDIV 20275U, // DSHD 134240057U, // DSLL 134234321U, // DSLL32 1073764153U, // DSLL64_32 134241475U, // DSLLV 134234684U, // DSRA 134234303U, // DSRA32 134241454U, // DSRAV 134240069U, // DSRL 134234329U, // DSRL32 134241482U, // DSRLV 134235901U, // DSUB 134241246U, // DSUBu 25596U, // DUDIV 25611U, // DivRxRy16 25597U, // DivuRxRy16 9438U, // EHB 9438U, // EHB_MM 546259U, // EI 546259U, // EI_MM 9481U, // ERET 9481U, // ERET_MM 134243426U, // EXT 134240324U, // EXTP 134240221U, // EXTPDP 134241497U, // EXTPDPV 134241506U, // EXTPV 134242731U, // EXTRV_RS_W 134242285U, // EXTRV_R_W 134238744U, // EXTRV_S_H 134243168U, // EXTRV_W 134242720U, // EXTR_RS_W 134242264U, // EXTR_R_W 134238675U, // EXTR_S_H 134242363U, // EXTR_W 134243419U, // EXTS 134243371U, // EXTS32 134243426U, // EXT_MM 0U, // ExtractElementF64 0U, // ExtractElementF64_64 0U, // FABS_D 19631U, // FABS_D32 19631U, // FABS_D64 19631U, // FABS_MM 23198U, // FABS_S 23198U, // FABS_S_MM 0U, // FABS_W 134236265U, // FADD_D 134236266U, // FADD_D32 134236266U, // FADD_D64 134236266U, // FADD_MM 134240572U, // FADD_S 134240572U, // FADD_S_MM 134241633U, // FADD_W 134236499U, // FCAF_D 134241752U, // FCAF_W 134236929U, // FCEQ_D 134242191U, // FCEQ_W 19638U, // FCLASS_D 25015U, // FCLASS_W 134236343U, // FCLE_D 134241675U, // FCLE_W 134237420U, // FCLT_D 134242770U, // FCLT_W 2204821U, // FCMP_D32 2204821U, // FCMP_D32_MM 2204821U, // FCMP_D64 2466965U, // FCMP_S32 2466965U, // FCMP_S32_MM 134236439U, // FCNE_D 134241709U, // FCNE_W 134237039U, // FCOR_D 134242320U, // FCOR_W 134236985U, // FCUEQ_D 134242207U, // FCUEQ_W 134236409U, // FCULE_D 134241691U, // FCULE_W 134237476U, // FCULT_D 134242786U, // FCULT_W 134236455U, // FCUNE_D 134241725U, // FCUNE_W 134236868U, // FCUN_D 134242097U, // FCUN_W 134237862U, // FDIV_D 134237863U, // FDIV_D32 134237863U, // FDIV_D64 134237863U, // FDIV_MM 134241045U, // FDIV_S 134241045U, // FDIV_S_MM 134243152U, // FDIV_W 134238402U, // FEXDO_H 134242113U, // FEXDO_W 134236152U, // FEXP2_D 0U, // FEXP2_D_1_PSEUDO 134241536U, // FEXP2_W 0U, // FEXP2_W_1_PSEUDO 19064U, // FEXUPL_D 24311U, // FEXUPL_W 19327U, // FEXUPR_D 24608U, // FEXUPR_W 19569U, // FFINT_S_D 24908U, // FFINT_S_W 20048U, // FFINT_U_D 25338U, // FFINT_U_W 19074U, // FFQL_D 24321U, // FFQL_W 19337U, // FFQR_D 24618U, // FFQR_W 17277U, // FILL_B 19049U, // FILL_D 0U, // FILL_FD_PSEUDO 0U, // FILL_FW_PSEUDO 20635U, // FILL_H 24296U, // FILL_W 18415U, // FLOG2_D 23799U, // FLOG2_W 19013U, // FLOOR_L_D64 23041U, // FLOOR_L_S 20189U, // FLOOR_W_D32 20189U, // FLOOR_W_D64 20189U, // FLOOR_W_MM 23363U, // FLOOR_W_S 23363U, // FLOOR_W_S_MM 151013489U, // FMADD_D 151018857U, // FMADD_W 134236190U, // FMAX_A_D 134241574U, // FMAX_A_W 134237937U, // FMAX_D 134243177U, // FMAX_W 134236170U, // FMIN_A_D 134241554U, // FMIN_A_W 134236842U, // FMIN_D 134242089U, // FMIN_W 20150U, // FMOV_D32 20150U, // FMOV_D32_MM 20150U, // FMOV_D64 23324U, // FMOV_S 23324U, // FMOV_S_MM 151013447U, // FMSUB_D 151018815U, // FMSUB_W 134236826U, // FMUL_D 134236827U, // FMUL_D32 134236827U, // FMUL_D64 134236827U, // FMUL_MM 134240805U, // FMUL_S 134240805U, // FMUL_S_MM 134242073U, // FMUL_W 18841U, // FNEG_D32 18841U, // FNEG_D64 18841U, // FNEG_MM 23002U, // FNEG_S 23002U, // FNEG_S_MM 19175U, // FRCP_D 24394U, // FRCP_W 19786U, // FRINT_D 25084U, // FRINT_W 19814U, // FRSQRT_D 25112U, // FRSQRT_W 134236518U, // FSAF_D 134241760U, // FSAF_W 134236957U, // FSEQ_D 134242199U, // FSEQ_W 134236381U, // FSLE_D 134241683U, // FSLE_W 134237448U, // FSLT_D 134242778U, // FSLT_W 134236447U, // FSNE_D 134241717U, // FSNE_W 134237047U, // FSOR_D 134242328U, // FSOR_W 19805U, // FSQRT_D 19806U, // FSQRT_D32 19806U, // FSQRT_D64 19806U, // FSQRT_MM 23301U, // FSQRT_S 23301U, // FSQRT_S_MM 25103U, // FSQRT_W 134236223U, // FSUB_D 134236224U, // FSUB_D32 134236224U, // FSUB_D64 134236224U, // FSUB_MM 134240554U, // FSUB_S 134240554U, // FSUB_S_MM 134241591U, // FSUB_W 134237006U, // FSUEQ_D 134242216U, // FSUEQ_W 134236430U, // FSULE_D 134241700U, // FSULE_W 134237497U, // FSULT_D 134242795U, // FSULT_W 134236464U, // FSUNE_D 134241734U, // FSUNE_W 134236887U, // FSUN_D 134242105U, // FSUN_W 19580U, // FTINT_S_D 24919U, // FTINT_S_W 20059U, // FTINT_U_D 25349U, // FTINT_U_W 134238479U, // FTQ_H 134242225U, // FTQ_W 19402U, // FTRUNC_S_D 24691U, // FTRUNC_S_W 19869U, // FTRUNC_U_D 25159U, // FTRUNC_U_W 1224758783U, // GotPrologue16 134237142U, // HADD_S_D 134238558U, // HADD_S_H 134242431U, // HADD_S_W 134237609U, // HADD_U_D 134238846U, // HADD_U_H 134242899U, // HADD_U_W 134237109U, // HSUB_S_D 134238537U, // HSUB_S_H 134242398U, // HSUB_S_W 134237576U, // HSUB_U_D 134238825U, // HSUB_U_H 134242866U, // HSUB_U_W 134235508U, // ILVEV_B 134237853U, // ILVEV_D 134239068U, // ILVEV_H 134243143U, // ILVEV_W 134235036U, // ILVL_B 134236834U, // ILVL_D 134238394U, // ILVL_H 134242081U, // ILVL_W 134234788U, // ILVOD_B 134236307U, // ILVOD_D 134238196U, // ILVOD_H 134241666U, // ILVOD_W 134235084U, // ILVR_B 134237082U, // ILVR_D 134238519U, // ILVR_H 134242371U, // ILVR_W 134243408U, // INS 44582043U, // INSERT_B 0U, // INSERT_B_VIDX_PSEUDO 44584275U, // INSERT_D 0U, // INSERT_D_VIDX_PSEUDO 0U, // INSERT_FD_PSEUDO 0U, // INSERT_FD_VIDX_PSEUDO 0U, // INSERT_FW_PSEUDO 0U, // INSERT_FW_VIDX_PSEUDO 44585551U, // INSERT_H 0U, // INSERT_H_VIDX_PSEUDO 44589573U, // INSERT_W 0U, // INSERT_W_VIDX_PSEUDO 16801009U, // INSV 52970157U, // INSVE_B 52971833U, // INSVE_D 52973565U, // INSVE_H 52977103U, // INSVE_W 134243408U, // INS_MM 546365U, // J 546398U, // JAL 22768U, // JALR 547056U, // JALR16_MM 22768U, // JALR64 0U, // JALR64Pseudo 0U, // JALRPseudo 541104U, // JALRS16_MM 23442U, // JALRS_MM 17822U, // JALR_HB 22768U, // JALR_MM 547706U, // JALS_MM 549771U, // JALX 549771U, // JALX_MM 546398U, // JAL_MM 18212U, // JIALC 18201U, // JIC 547052U, // JR 541091U, // JR16_MM 547052U, // JR64 546873U, // JRADDIUSP 542610U, // JRC16_MM 542103U, // JR_HB 542103U, // JR_HB_R6 547052U, // JR_MM 546365U, // J_MM 2905694U, // Jal16 3167838U, // JalB16 546398U, // JalOneReg 22110U, // JalTwoReg 9430U, // JrRa16 9421U, // JrcRa16 549872U, // JrcRx16 540673U, // JumpLinkReg16 58738087U, // LB 58738087U, // LB64 58737088U, // LBU16_MM 1358979985U, // LBUX 58738087U, // LB_MM 58743769U, // LBu 58743769U, // LBu64 58743769U, // LBu_MM 58740538U, // LD 58736688U, // LDC1 58736688U, // LDC164 58736688U, // LDC1_MM 58736888U, // LDC2 58736888U, // LDC2_R6 58736947U, // LDC3 17103U, // LDI_B 18857U, // LDI_D 20511U, // LDI_H 24146U, // LDI_W 58742458U, // LDL 18273U, // LDPC 58742954U, // LDR 1358970992U, // LDXC1 1358970992U, // LDXC164 58737301U, // LD_B 58738820U, // LD_D 58740709U, // LD_H 58744179U, // LD_W 25189403U, // LEA_ADDiu 25189402U, // LEA_ADDiu64 25189403U, // LEA_ADDiu_MM 58741643U, // LH 58741643U, // LH64 58737111U, // LHU16_MM 1358979974U, // LHX 58741643U, // LH_MM 58743822U, // LHu 58743822U, // LHu64 58743822U, // LHu_MM 16751U, // LI16_MM 58742563U, // LL 58740537U, // LLD 58740537U, // LLD_R6 58742563U, // LL_MM 58742563U, // LL_R6 58736647U, // LOAD_ACC128 58736647U, // LOAD_ACC64 58736647U, // LOAD_ACC64DSP 58742794U, // LOAD_CCOND_DSP 0U, // LONG_BRANCH_ADDiu 0U, // LONG_BRANCH_DADDiu 0U, // LONG_BRANCH_LUi 134234691U, // LSA 134234691U, // LSA_R6 1358971006U, // LUXC1 1358971006U, // LUXC164 1358971006U, // LUXC1_MM 33576504U, // LUi 33576504U, // LUi64 33576504U, // LUi_MM 58745726U, // LW 58737118U, // LW16_MM 58745726U, // LW64 58736740U, // LWC1 58736740U, // LWC1_MM 58736914U, // LWC2 58736914U, // LWC2_R6 58736959U, // LWC3 58745726U, // LWGP_MM 58742637U, // LWL 58742637U, // LWL64 58742637U, // LWL_MM 3522956U, // LWM16_MM 3522785U, // LWM32_MM 3528595U, // LWM_MM 18310U, // LWPC 137290U, // LWP_MM 58743054U, // LWR 58743054U, // LWR64 58743054U, // LWR_MM 58745726U, // LWSP_MM 18303U, // LWUPC 58743912U, // LWU_MM 1358979991U, // LWX 1358971020U, // LWXC1 1358971020U, // LWXC1_MM 1358977945U, // LWXS_MM 58745726U, // LW_MM 58743912U, // LWu 58738087U, // LbRxRyOffMemX16 58743769U, // LbuRxRyOffMemX16 58741643U, // LhRxRyOffMemX16 58743822U, // LhuRxRyOffMemX16 939546111U, // LiRxImm16 22005U, // LiRxImmAlignX16 22015U, // LiRxImmX16 33571334U, // LoadAddr32Imm 58737158U, // LoadAddr32Reg 33576447U, // LoadImm32Reg 22019U, // LoadImm64Reg 3695486U, // LwConstant32 268460926U, // LwRxPcTcp16 25470U, // LwRxPcTcpX16 58745726U, // LwRxRyOffMemX16 1493197694U, // LwRxSpImmX16 20269U, // MADD 151013751U, // MADDF_D 151017921U, // MADDF_S 151015667U, // MADDR_Q_H 151019386U, // MADDR_Q_W 23546U, // MADDU 134241274U, // MADDU_DSP 23546U, // MADDU_MM 151012706U, // MADDV_B 151015051U, // MADDV_D 151016266U, // MADDV_H 151020341U, // MADDV_W 134236274U, // MADD_D32 134236274U, // MADD_D32_MM 134236274U, // MADD_D64 134237997U, // MADD_DSP 20269U, // MADD_MM 151015637U, // MADD_Q_H 151019356U, // MADD_Q_W 134240571U, // MADD_S 134240571U, // MADD_S_MM 134239974U, // MAQ_SA_W_PHL 134240436U, // MAQ_SA_W_PHR 134240002U, // MAQ_S_W_PHL 134240464U, // MAQ_S_W_PHR 134236215U, // MAXA_D 134240544U, // MAXA_S 134235159U, // MAXI_S_B 134237220U, // MAXI_S_D 134238636U, // MAXI_S_H 134242509U, // MAXI_S_W 2281719022U, // MAXI_U_B 2281721335U, // MAXI_U_D 2281722572U, // MAXI_U_H 2281726625U, // MAXI_U_W 134234740U, // MAX_A_B 134236191U, // MAX_A_D 134238148U, // MAX_A_H 134241575U, // MAX_A_W 134237938U, // MAX_D 134241111U, // MAX_S 134235247U, // MAX_S_B 134237340U, // MAX_S_D 134238755U, // MAX_S_H 134242690U, // MAX_S_W 134235462U, // MAX_U_B 134237807U, // MAX_U_D 134239022U, // MAX_U_H 134243097U, // MAX_U_W 134234122U, // MFC0 16451U, // MFC1 16451U, // MFC1_MM 134234373U, // MFC2 16457U, // MFHC1_D32 16457U, // MFHC1_D64 16457U, // MFHC1_MM 546281U, // MFHI 546281U, // MFHI16_MM 546281U, // MFHI64 21993U, // MFHI_DSP 546281U, // MFHI_MM 546745U, // MFLO 546745U, // MFLO16_MM 546745U, // MFLO64 22457U, // MFLO_DSP 546745U, // MFLO_MM 134236200U, // MINA_D 134240536U, // MINA_S 134235139U, // MINI_S_B 134237200U, // MINI_S_D 134238616U, // MINI_S_H 134242489U, // MINI_S_W 2281719002U, // MINI_U_B 2281721315U, // MINI_U_D 2281722552U, // MINI_U_H 2281726605U, // MINI_U_W 134234721U, // MIN_A_B 134236171U, // MIN_A_D 134238129U, // MIN_A_H 134241555U, // MIN_A_W 134236843U, // MIN_D 134240812U, // MIN_S 134235169U, // MIN_S_B 134237230U, // MIN_S_D 134238646U, // MIN_S_H 134242529U, // MIN_S_W 134235384U, // MIN_U_B 134237697U, // MIN_U_D 134238934U, // MIN_U_H 134242987U, // MIN_U_W 0U, // MIPSeh_return32 0U, // MIPSeh_return64 134238037U, // MOD 134235899U, // MODSUB 134241282U, // MODU 134235102U, // MOD_S_B 134237163U, // MOD_S_D 134238579U, // MOD_S_H 134242452U, // MOD_S_W 134235317U, // MOD_U_B 134237630U, // MOD_U_D 134238867U, // MOD_U_H 134242920U, // MOD_U_W 20345U, // MOVE16_MM 67491813U, // MOVEP_MM 23668U, // MOVE_V 134236560U, // MOVF_D32 134236560U, // MOVF_D32_MM 134236560U, // MOVF_D64 134238109U, // MOVF_I 134238109U, // MOVF_I64 134238109U, // MOVF_I_MM 134240722U, // MOVF_S 134240722U, // MOVF_S_MM 134236895U, // MOVN_I64_D64 134240173U, // MOVN_I64_I 134240173U, // MOVN_I64_I64 134240848U, // MOVN_I64_S 134236895U, // MOVN_I_D32 134236895U, // MOVN_I_D32_MM 134236895U, // MOVN_I_D64 134240173U, // MOVN_I_I 134240173U, // MOVN_I_I64 134240173U, // MOVN_I_MM 134240848U, // MOVN_I_S 134240848U, // MOVN_I_S_MM 134237558U, // MOVT_D32 134237558U, // MOVT_D32_MM 134237558U, // MOVT_D64 134241235U, // MOVT_I 134241235U, // MOVT_I64 134241235U, // MOVT_I_MM 134241037U, // MOVT_S 134241037U, // MOVT_S_MM 134237978U, // MOVZ_I64_D64 134243300U, // MOVZ_I64_I 134243300U, // MOVZ_I64_I64 134241138U, // MOVZ_I64_S 134237978U, // MOVZ_I_D32 134237978U, // MOVZ_I_D32_MM 134237978U, // MOVZ_I_D64 134243300U, // MOVZ_I_I 134243300U, // MOVZ_I_I64 134243300U, // MOVZ_I_MM 134241138U, // MOVZ_I_S 134241138U, // MOVZ_I_S_MM 18179U, // MSUB 151013742U, // MSUBF_D 151017912U, // MSUBF_S 151015656U, // MSUBR_Q_H 151019375U, // MSUBR_Q_W 23525U, // MSUBU 134241253U, // MSUBU_DSP 23525U, // MSUBU_MM 151012697U, // MSUBV_B 151015042U, // MSUBV_D 151016257U, // MSUBV_H 151020332U, // MSUBV_W 134236232U, // MSUB_D32 134236232U, // MSUB_D32_MM 134236232U, // MSUB_D64 134235907U, // MSUB_DSP 18179U, // MSUB_MM 151015627U, // MSUB_Q_H 151019346U, // MSUB_Q_W 134240553U, // MSUB_S 134240553U, // MSUB_S_MM 134234129U, // MTC0 1867870U, // MTC1 1867870U, // MTC1_MM 134234380U, // MTC2 1884240U, // MTHC1_D32 1884240U, // MTHC1_D64 1884240U, // MTHC1_MM 546287U, // MTHI 546287U, // MTHI64 1873391U, // MTHI_DSP 546287U, // MTHI_MM 1873900U, // MTHLIP 546758U, // MTLO 546758U, // MTLO64 1873862U, // MTLO_DSP 546758U, // MTLO_MM 540701U, // MTM0 540826U, // MTM1 540958U, // MTM2 540707U, // MTP0 540832U, // MTP1 540964U, // MTP2 134239672U, // MUH 134241300U, // MUHU 134240104U, // MUL 134240015U, // MULEQ_S_W_PHL 134240477U, // MULEQ_S_W_PHR 134239883U, // MULEU_S_PH_QBL 134240379U, // MULEU_S_PH_QBR 134239433U, // MULQ_RS_PH 134242709U, // MULQ_RS_W 134239377U, // MULQ_S_PH 134242568U, // MULQ_S_W 134238462U, // MULR_Q_H 134242181U, // MULR_Q_W 134239579U, // MULSAQ_S_W_PH 134239554U, // MULSA_W_PH 23496U, // MULT 134241370U, // MULTU_DSP 134241224U, // MULT_DSP 23496U, // MULT_MM 23642U, // MULTu 23642U, // MULTu_MM 134241337U, // MULU 134235517U, // MULV_B 134237870U, // MULV_D 134239077U, // MULV_H 134243160U, // MULV_W 134240104U, // MUL_MM 134239250U, // MUL_PH 134238431U, // MUL_Q_H 134242150U, // MUL_Q_W 134240104U, // MUL_R6 134239345U, // MUL_S_PH 546281U, // Mfhi16 546745U, // Mflo16 20345U, // Move32R16 20345U, // MoveR3216 23496U, // MultRxRy16 75799496U, // MultRxRyRz16 23642U, // MultuRxRy16 75799642U, // MultuRxRyRz16 17028U, // NLOC_B 18521U, // NLOC_D 20436U, // NLOC_H 23880U, // NLOC_W 17036U, // NLZC_B 18529U, // NLZC_D 20444U, // NLZC_H 23888U, // NLZC_W 134236282U, // NMADD_D32 134236282U, // NMADD_D32_MM 134236282U, // NMADD_D64 134240570U, // NMADD_S 134240570U, // NMADD_S_MM 134236240U, // NMSUB_D32 134236240U, // NMSUB_D32_MM 134236240U, // NMSUB_D64 134240552U, // NMSUB_S 134240552U, // NMSUB_S_MM 0U, // NOP 134240502U, // NOR 134240502U, // NOR64 2281718573U, // NORI_B 134240502U, // NOR_MM 134241412U, // NOR_V 0U, // NOR_V_D_PSEUDO 0U, // NOR_V_H_PSEUDO 0U, // NOR_V_W_PSEUDO 16825U, // NOT16_MM 20387U, // NegRxRy16 23502U, // NotRxRy16 134240503U, // OR 836010U, // OR16_MM 134240503U, // OR64 2281718574U, // ORI_B 134240503U, // OR_MM 134241413U, // OR_V 0U, // OR_V_D_PSEUDO 0U, // OR_V_H_PSEUDO 0U, // OR_V_W_PSEUDO 134239771U, // ORi 134239771U, // ORi64 134239771U, // ORi_MM 16799991U, // OrRxRxRy16 134239239U, // PACKRL_PH 9442U, // PAUSE 9442U, // PAUSE_MM 134235499U, // PCKEV_B 134237844U, // PCKEV_D 134239059U, // PCKEV_H 134243134U, // PCKEV_W 134234779U, // PCKOD_B 134236298U, // PCKOD_D 134238187U, // PCKOD_H 134241657U, // PCKOD_W 17555U, // PCNT_B 19778U, // PCNT_D 21063U, // PCNT_H 25076U, // PCNT_W 134239203U, // PICK_PH 134235631U, // PICK_QB 22522U, // POP 22186U, // PRECEQU_PH_QBL 16906U, // PRECEQU_PH_QBLA 22682U, // PRECEQU_PH_QBR 16939U, // PRECEQU_PH_QBRA 22260U, // PRECEQ_W_PHL 22722U, // PRECEQ_W_PHR 22171U, // PRECEU_PH_QBL 16890U, // PRECEU_PH_QBLA 22667U, // PRECEU_PH_QBR 16923U, // PRECEU_PH_QBRA 134239155U, // PRECRQU_S_QB_PH 134241800U, // PRECRQ_PH_W 134239128U, // PRECRQ_QB_PH 134241831U, // PRECRQ_RS_PH_W 134239142U, // PRECR_QB_PH 134241784U, // PRECR_SRA_PH_W 134241813U, // PRECR_SRA_R_PH_W 85911U, // PREF 85911U, // PREF_MM 85911U, // PREF_R6 134238019U, // PREPEND 0U, // PseudoCMPU_EQ_QB 0U, // PseudoCMPU_LE_QB 0U, // PseudoCMPU_LT_QB 0U, // PseudoCMP_EQ_PH 0U, // PseudoCMP_LE_PH 0U, // PseudoCMP_LT_PH 16391U, // PseudoCVT_D32_W 16391U, // PseudoCVT_D64_L 16391U, // PseudoCVT_D64_W 16391U, // PseudoCVT_S_L 16391U, // PseudoCVT_S_W 0U, // PseudoDMULT 0U, // PseudoDMULTu 0U, // PseudoDSDIV 0U, // PseudoDUDIV 0U, // PseudoIndirectBranch 0U, // PseudoIndirectBranch64 0U, // PseudoMADD 0U, // PseudoMADDU 0U, // PseudoMFHI 0U, // PseudoMFHI64 0U, // PseudoMFLO 0U, // PseudoMFLO64 0U, // PseudoMSUB 0U, // PseudoMSUBU 0U, // PseudoMTLOHI 0U, // PseudoMTLOHI64 0U, // PseudoMTLOHI_DSP 0U, // PseudoMULT 0U, // PseudoMULTu 0U, // PseudoPICK_PH 0U, // PseudoPICK_QB 0U, // PseudoReturn 0U, // PseudoReturn64 0U, // PseudoSDIV 0U, // PseudoSELECTFP_F_D32 0U, // PseudoSELECTFP_F_D64 0U, // PseudoSELECTFP_F_I 0U, // PseudoSELECTFP_F_I64 0U, // PseudoSELECTFP_F_S 0U, // PseudoSELECTFP_T_D32 0U, // PseudoSELECTFP_T_D64 0U, // PseudoSELECTFP_T_I 0U, // PseudoSELECTFP_T_I64 0U, // PseudoSELECTFP_T_S 0U, // PseudoSELECT_D32 0U, // PseudoSELECT_D64 0U, // PseudoSELECT_I 0U, // PseudoSELECT_I64 0U, // PseudoSELECT_S 0U, // PseudoUDIV 18155U, // RADDU_W_QB 33577003U, // RDDSP 22791U, // RDHWR 22791U, // RDHWR64 22791U, // RDHWR_MM 21766U, // REPLV_PH 18135U, // REPLV_QB 33575925U, // REPL_PH 33572353U, // REPL_QB 19787U, // RINT_D 23293U, // RINT_S 134240513U, // ROTR 134241514U, // ROTRV 134241514U, // ROTRV_MM 134240513U, // ROTR_MM 18992U, // ROUND_L_D64 23020U, // ROUND_L_S 20168U, // ROUND_W_D32 20168U, // ROUND_W_D64 20168U, // ROUND_W_MM 23342U, // ROUND_W_S 23342U, // ROUND_W_S_MM 0U, // Restore16 0U, // RestoreX16 0U, // RetRA 0U, // RetRA16 134235208U, // SAT_S_B 134237279U, // SAT_S_D 2281722353U, // SAT_S_H 134242618U, // SAT_S_W 134235435U, // SAT_U_B 134237758U, // SAT_U_D 2281722643U, // SAT_U_H 134243048U, // SAT_U_W 58738423U, // SB 58736980U, // SB16_MM 58738423U, // SB64 58738423U, // SB_MM 3966874U, // SC 3968802U, // SCD 3968802U, // SCD_R6 3966874U, // SC_MM 3966874U, // SC_R6 58740570U, // SD 546774U, // SDBBP 65946U, // SDBBP16_MM 546774U, // SDBBP_MM 546774U, // SDBBP_R6 58736694U, // SDC1 58736694U, // SDC164 58736694U, // SDC1_MM 58736894U, // SDC2 58736894U, // SDC2_R6 58736953U, // SDC3 25611U, // SDIV 25611U, // SDIV_MM 58742463U, // SDL 58742959U, // SDR 1358970999U, // SDXC1 1358970999U, // SDXC164 17810U, // SEB 17810U, // SEB64 17810U, // SEB_MM 21382U, // SEH 21382U, // SEH64 21382U, // SEH_MM 134243273U, // SELEQZ 134243273U, // SELEQZ64 134237968U, // SELEQZ_D 134241128U, // SELEQZ_S 134243246U, // SELNEZ 134243246U, // SELNEZ64 134237951U, // SELNEZ_D 134241118U, // SELNEZ_S 151013977U, // SEL_D 151018005U, // SEL_S 134240345U, // SEQ 134239758U, // SEQi 58742195U, // SH 58736993U, // SH16_MM 58742195U, // SH64 2281718455U, // SHF_B 2281721863U, // SHF_H 2281725417U, // SHF_W 22463U, // SHILO 23761U, // SHILOV 134239484U, // SHLLV_PH 134235853U, // SHLLV_QB 134239421U, // SHLLV_S_PH 134242679U, // SHLLV_S_W 134239212U, // SHLL_PH 134235640U, // SHLL_QB 134239334U, // SHLL_S_PH 134242519U, // SHLL_S_W 134239474U, // SHRAV_PH 134235843U, // SHRAV_QB 134239322U, // SHRAV_R_PH 134235741U, // SHRAV_R_QB 134242274U, // SHRAV_R_W 134239119U, // SHRA_PH 134235563U, // SHRA_QB 134239287U, // SHRA_R_PH 134235706U, // SHRA_R_QB 134242232U, // SHRA_R_W 134239504U, // SHRLV_PH 134235873U, // SHRLV_QB 134239230U, // SHRL_PH 134235658U, // SHRL_QB 58742195U, // SH_MM 2969584334U, // SLDI_B 2969586088U, // SLDI_D 2969587742U, // SLDI_H 2969591377U, // SLDI_W 822100628U, // SLD_B 822102147U, // SLD_D 822104036U, // SLD_H 822107506U, // SLD_W 134240058U, // SLL 134234494U, // SLL16_MM 1610635066U, // SLL64_32 1610635066U, // SLL64_64 2281718512U, // SLLI_B 2281720249U, // SLLI_D 2281721903U, // SLLI_H 2281725538U, // SLLI_W 134241476U, // SLLV 134241476U, // SLLV_MM 134235013U, // SLL_B 134236785U, // SLL_D 134238371U, // SLL_H 134240058U, // SLL_MM 134242032U, // SLL_W 134241213U, // SLT 134241213U, // SLT64 134241213U, // SLT_MM 134239782U, // SLTi 134239782U, // SLTi64 134239782U, // SLTi_MM 134241321U, // SLTiu 134241321U, // SLTiu64 134241321U, // SLTiu_MM 134241357U, // SLTu 134241357U, // SLTu64 134241357U, // SLTu_MM 134238063U, // SNE 134239703U, // SNEi 0U, // SNZ_B_PSEUDO 0U, // SNZ_D_PSEUDO 0U, // SNZ_H_PSEUDO 0U, // SNZ_V_PSEUDO 0U, // SNZ_W_PSEUDO 2952807239U, // SPLATI_B 2952808960U, // SPLATI_D 2952810614U, // SPLATI_H 2952814249U, // SPLATI_W 805323906U, // SPLAT_B 805326016U, // SPLAT_D 805327414U, // SPLAT_H 805331393U, // SPLAT_W 134234685U, // SRA 2281718470U, // SRAI_B 2281720224U, // SRAI_D 2281721878U, // SRAI_H 2281725513U, // SRAI_W 134234898U, // SRARI_B 134236635U, // SRARI_D 2281721937U, // SRARI_H 134241924U, // SRARI_W 134235051U, // SRAR_B 134237015U, // SRAR_D 134238486U, // SRAR_H 134242296U, // SRAR_W 134241455U, // SRAV 134241455U, // SRAV_MM 134234749U, // SRA_B 134236208U, // SRA_D 134238157U, // SRA_H 134234685U, // SRA_MM 134241584U, // SRA_W 134240070U, // SRL 134234501U, // SRL16_MM 2281718520U, // SRLI_B 2281720257U, // SRLI_D 2281721911U, // SRLI_H 2281725546U, // SRLI_W 134234916U, // SRLRI_B 134236653U, // SRLRI_D 2281721955U, // SRLRI_H 134241942U, // SRLRI_W 134235067U, // SRLR_B 134237031U, // SRLR_D 134238502U, // SRLR_H 134242312U, // SRLR_W 134241483U, // SRLV 134241483U, // SRLV_MM 134235020U, // SRL_B 134236810U, // SRL_D 134238378U, // SRL_H 134240070U, // SRL_MM 134242057U, // SRL_W 9463U, // SSNOP 9463U, // SSNOP_MM 58736647U, // STORE_ACC128 58736647U, // STORE_ACC64 58736647U, // STORE_ACC64DSP 58742810U, // STORE_CCOND_DSP 58737829U, // ST_B 58740080U, // ST_D 58741337U, // ST_H 58745378U, // ST_W 134235902U, // SUB 134239183U, // SUBQH_PH 134239298U, // SUBQH_R_PH 134242242U, // SUBQH_R_W 134241847U, // SUBQH_W 134239258U, // SUBQ_PH 134239355U, // SUBQ_S_PH 134242548U, // SUBQ_S_W 134235423U, // SUBSUS_U_B 134237746U, // SUBSUS_U_D 134238983U, // SUBSUS_U_H 134243036U, // SUBSUS_U_W 134235226U, // SUBSUU_S_B 134237319U, // SUBSUU_S_D 134238723U, // SUBSUU_S_H 134242658U, // SUBSUU_S_W 134235188U, // SUBS_S_B 134237259U, // SUBS_S_D 134238685U, // SUBS_S_H 134242598U, // SUBS_S_W 134235403U, // SUBS_U_B 134237726U, // SUBS_U_D 134238963U, // SUBS_U_H 134243016U, // SUBS_U_W 134234567U, // SUBU16_MM 134235611U, // SUBUH_QB 134235717U, // SUBUH_R_QB 134239456U, // SUBU_PH 134235825U, // SUBU_QB 134239399U, // SUBU_S_PH 134235764U, // SUBU_S_QB 2281718618U, // SUBVI_B 2281720339U, // SUBVI_D 2281721993U, // SUBVI_H 2281725628U, // SUBVI_W 134235482U, // SUBV_B 134237827U, // SUBV_D 134239042U, // SUBV_H 134243117U, // SUBV_W 134235902U, // SUB_MM 134241247U, // SUBu 134241247U, // SUBu_MM 1358971013U, // SUXC1 1358971013U, // SUXC164 1358971013U, // SUXC1_MM 58745730U, // SW 58737124U, // SW16_MM 58745730U, // SW64 58736746U, // SWC1 58736746U, // SWC1_MM 58736920U, // SWC2 58736920U, // SWC2_R6 58736965U, // SWC3 58742642U, // SWL 58742642U, // SWL64 58742642U, // SWL_MM 3522963U, // SWM16_MM 3522792U, // SWM32_MM 3528600U, // SWM_MM 137295U, // SWP_MM 58743059U, // SWR 58743059U, // SWR64 58743059U, // SWR_MM 58745730U, // SWSP_MM 1358971027U, // SWXC1 1358971027U, // SWXC1_MM 58745730U, // SW_MM 549939U, // SYNC 153021U, // SYNCI 549939U, // SYNC_MM 546590U, // SYSCALL 546590U, // SYSCALL_MM 0U, // SZ_B_PSEUDO 0U, // SZ_D_PSEUDO 0U, // SZ_H_PSEUDO 0U, // SZ_V_PSEUDO 0U, // SZ_W_PSEUDO 0U, // Save16 0U, // SaveX16 58738423U, // SbRxRyOffMemX16 549866U, // SebRx16 549878U, // SehRx16 4367299U, // SelBeqZ 4367272U, // SelBneZ 1828886516U, // SelTBteqZCmp 1828886024U, // SelTBteqZCmpi 1828887485U, // SelTBteqZSlt 1828886054U, // SelTBteqZSlti 1828887593U, // SelTBteqZSltiu 1828887629U, // SelTBteqZSltu 1963104244U, // SelTBtneZCmp 1963103752U, // SelTBtneZCmpi 1963105213U, // SelTBtneZSlt 1963103782U, // SelTBtneZSlti 1963105321U, // SelTBtneZSltiu 1963105357U, // SelTBtneZSltu 58742195U, // ShRxRyOffMemX16 134240058U, // SllX16 16800964U, // SllvRxRy16 92576701U, // SltCCRxRy16 23485U, // SltRxRy16 92575270U, // SltiCCRxImmX16 939546150U, // SltiRxImm16 22054U, // SltiRxImmX16 92576809U, // SltiuCCRxImmX16 939547689U, // SltiuRxImm16 23593U, // SltiuRxImmX16 92576845U, // SltuCCRxRy16 23629U, // SltuRxRy16 92576845U, // SltuRxRyRz16 134234685U, // SraX16 16800943U, // SravRxRy16 134240070U, // SrlX16 16800971U, // SrlvRxRy16 134241247U, // SubuRxRyRz16 58745730U, // SwRxRyOffMemX16 1493197698U, // SwRxSpImmX16 0U, // TAILCALL 0U, // TAILCALL64_R 0U, // TAILCALL_R 134240350U, // TEQ 33576468U, // TEQI 33576468U, // TEQI_MM 134240350U, // TEQ_MM 134238046U, // TGE 33576401U, // TGEI 33578018U, // TGEIU 33578018U, // TGEIU_MM 33576401U, // TGEI_MM 134241288U, // TGEU 134241288U, // TGEU_MM 134238046U, // TGE_MM 9458U, // TLBP 9458U, // TLBP_MM 9469U, // TLBR 9469U, // TLBR_MM 9448U, // TLBWI 9448U, // TLBWI_MM 9474U, // TLBWR 9474U, // TLBWR_MM 134241218U, // TLT 33576492U, // TLTI 33578032U, // TLTIU_MM 33576492U, // TLTI_MM 134241363U, // TLTU 134241363U, // TLTU_MM 134241218U, // TLT_MM 134238068U, // TNE 33576413U, // TNEI 33576413U, // TNEI_MM 134238068U, // TNE_MM 0U, // TRAP 18981U, // TRUNC_L_D64 23009U, // TRUNC_L_S 20157U, // TRUNC_W_D32 20157U, // TRUNC_W_D64 20157U, // TRUNC_W_MM 23331U, // TRUNC_W_S 23331U, // TRUNC_W_S_MM 33578032U, // TTLTIU 25597U, // UDIV 25597U, // UDIV_MM 134241335U, // V3MULU 134234135U, // VMM0 134241350U, // VMULU 151012022U, // VSHF_B 151013760U, // VSHF_D 151015430U, // VSHF_H 151018984U, // VSHF_W 9486U, // WAIT 547767U, // WAIT_MM 33577010U, // WRDSP 21376U, // WSBH 21376U, // WSBH_MM 134240507U, // XOR 836009U, // XOR16_MM 134240507U, // XOR64 2281718581U, // XORI_B 134240507U, // XOR_MM 134241419U, // XOR_V 0U, // XOR_V_D_PSEUDO 0U, // XOR_V_H_PSEUDO 0U, // XOR_V_W_PSEUDO 134239770U, // XORi 134239770U, // XORi64 134239770U, // XORi_MM 16799995U, // XorRxRxRy16 0U }; static const uint8_t OpInfo2[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // FRAME_ALLOC 0U, // ABSQ_S_PH 0U, // ABSQ_S_QB 0U, // ABSQ_S_W 0U, // ADD 0U, // ADDIUPC 0U, // ADDIUPC_MM 0U, // ADDIUR1SP_MM 0U, // ADDIUR2_MM 0U, // ADDIUS5_MM 0U, // ADDIUSP_MM 0U, // ADDQH_PH 0U, // ADDQH_R_PH 0U, // ADDQH_R_W 0U, // ADDQH_W 0U, // ADDQ_PH 0U, // ADDQ_S_PH 0U, // ADDQ_S_W 0U, // ADDSC 0U, // ADDS_A_B 0U, // ADDS_A_D 0U, // ADDS_A_H 0U, // ADDS_A_W 0U, // ADDS_S_B 0U, // ADDS_S_D 0U, // ADDS_S_H 0U, // ADDS_S_W 0U, // ADDS_U_B 0U, // ADDS_U_D 0U, // ADDS_U_H 0U, // ADDS_U_W 0U, // ADDU16_MM 0U, // ADDUH_QB 0U, // ADDUH_R_QB 0U, // ADDU_PH 0U, // ADDU_QB 0U, // ADDU_S_PH 0U, // ADDU_S_QB 0U, // ADDVI_B 0U, // ADDVI_D 0U, // ADDVI_H 0U, // ADDVI_W 0U, // ADDV_B 0U, // ADDV_D 0U, // ADDV_H 0U, // ADDV_W 0U, // ADDWC 0U, // ADD_A_B 0U, // ADD_A_D 0U, // ADD_A_H 0U, // ADD_A_W 0U, // ADD_MM 0U, // ADDi 0U, // ADDi_MM 0U, // ADDiu 0U, // ADDiu_MM 0U, // ADDu 0U, // ADDu_MM 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 4U, // ALIGN 0U, // ALUIPC 0U, // AND 0U, // AND16_MM 0U, // AND64 0U, // ANDI16_MM 0U, // ANDI_B 0U, // AND_MM 0U, // AND_V 0U, // AND_V_D_PSEUDO 0U, // AND_V_H_PSEUDO 0U, // AND_V_W_PSEUDO 1U, // ANDi 1U, // ANDi64 1U, // ANDi_MM 1U, // APPEND 0U, // ASUB_S_B 0U, // ASUB_S_D 0U, // ASUB_S_H 0U, // ASUB_S_W 0U, // ASUB_U_B 0U, // ASUB_U_D 0U, // ASUB_U_H 0U, // ASUB_U_W 0U, // ATOMIC_CMP_SWAP_I16 0U, // ATOMIC_CMP_SWAP_I32 0U, // ATOMIC_CMP_SWAP_I64 0U, // ATOMIC_CMP_SWAP_I8 0U, // ATOMIC_LOAD_ADD_I16 0U, // ATOMIC_LOAD_ADD_I32 0U, // ATOMIC_LOAD_ADD_I64 0U, // ATOMIC_LOAD_ADD_I8 0U, // ATOMIC_LOAD_AND_I16 0U, // ATOMIC_LOAD_AND_I32 0U, // ATOMIC_LOAD_AND_I64 0U, // ATOMIC_LOAD_AND_I8 0U, // ATOMIC_LOAD_NAND_I16 0U, // ATOMIC_LOAD_NAND_I32 0U, // ATOMIC_LOAD_NAND_I64 0U, // ATOMIC_LOAD_NAND_I8 0U, // ATOMIC_LOAD_OR_I16 0U, // ATOMIC_LOAD_OR_I32 0U, // ATOMIC_LOAD_OR_I64 0U, // ATOMIC_LOAD_OR_I8 0U, // ATOMIC_LOAD_SUB_I16 0U, // ATOMIC_LOAD_SUB_I32 0U, // ATOMIC_LOAD_SUB_I64 0U, // ATOMIC_LOAD_SUB_I8 0U, // ATOMIC_LOAD_XOR_I16 0U, // ATOMIC_LOAD_XOR_I32 0U, // ATOMIC_LOAD_XOR_I64 0U, // ATOMIC_LOAD_XOR_I8 0U, // ATOMIC_SWAP_I16 0U, // ATOMIC_SWAP_I32 0U, // ATOMIC_SWAP_I64 0U, // ATOMIC_SWAP_I8 0U, // AUI 0U, // AUIPC 0U, // AVER_S_B 0U, // AVER_S_D 0U, // AVER_S_H 0U, // AVER_S_W 0U, // AVER_U_B 0U, // AVER_U_D 0U, // AVER_U_H 0U, // AVER_U_W 0U, // AVE_S_B 0U, // AVE_S_D 0U, // AVE_S_H 0U, // AVE_S_W 0U, // AVE_U_B 0U, // AVE_U_D 0U, // AVE_U_H 0U, // AVE_U_W 0U, // AddiuRxImmX16 0U, // AddiuRxPcImmX16 0U, // AddiuRxRxImm16 0U, // AddiuRxRxImmX16 0U, // AddiuRxRyOffMemX16 0U, // AddiuSpImm16 0U, // AddiuSpImmX16 0U, // AdduRxRyRz16 0U, // AndRxRxRy16 0U, // B 0U, // B16_MM 0U, // BADDu 0U, // BAL 0U, // BALC 1U, // BALIGN 0U, // BAL_BR 0U, // BBIT0 0U, // BBIT032 0U, // BBIT1 0U, // BBIT132 0U, // BC 0U, // BC0F 0U, // BC0FL 0U, // BC0T 0U, // BC0TL 0U, // BC1EQZ 0U, // BC1F 0U, // BC1FL 0U, // BC1F_MM 0U, // BC1NEZ 0U, // BC1T 0U, // BC1TL 0U, // BC1T_MM 0U, // BC2EQZ 0U, // BC2F 0U, // BC2FL 0U, // BC2NEZ 0U, // BC2T 0U, // BC2TL 0U, // BC3F 0U, // BC3FL 0U, // BC3T 0U, // BC3TL 0U, // BCLRI_B 0U, // BCLRI_D 0U, // BCLRI_H 0U, // BCLRI_W 0U, // BCLR_B 0U, // BCLR_D 0U, // BCLR_H 0U, // BCLR_W 0U, // BEQ 0U, // BEQ64 0U, // BEQC 0U, // BEQL 0U, // BEQZ16_MM 0U, // BEQZALC 0U, // BEQZC 0U, // BEQZC_MM 0U, // BEQ_MM 0U, // BGEC 0U, // BGEUC 0U, // BGEZ 0U, // BGEZ64 0U, // BGEZAL 0U, // BGEZALC 0U, // BGEZALL 0U, // BGEZALS_MM 0U, // BGEZAL_MM 0U, // BGEZC 0U, // BGEZL 0U, // BGEZ_MM 0U, // BGTZ 0U, // BGTZ64 0U, // BGTZALC 0U, // BGTZC 0U, // BGTZL 0U, // BGTZ_MM 1U, // BINSLI_B 1U, // BINSLI_D 1U, // BINSLI_H 1U, // BINSLI_W 2U, // BINSL_B 2U, // BINSL_D 2U, // BINSL_H 2U, // BINSL_W 1U, // BINSRI_B 1U, // BINSRI_D 1U, // BINSRI_H 1U, // BINSRI_W 2U, // BINSR_B 2U, // BINSR_D 2U, // BINSR_H 2U, // BINSR_W 0U, // BITREV 0U, // BITSWAP 0U, // BLEZ 0U, // BLEZ64 0U, // BLEZALC 0U, // BLEZC 0U, // BLEZL 0U, // BLEZ_MM 0U, // BLTC 0U, // BLTUC 0U, // BLTZ 0U, // BLTZ64 0U, // BLTZAL 0U, // BLTZALC 0U, // BLTZALL 0U, // BLTZALS_MM 0U, // BLTZAL_MM 0U, // BLTZC 0U, // BLTZL 0U, // BLTZ_MM 1U, // BMNZI_B 2U, // BMNZ_V 1U, // BMZI_B 2U, // BMZ_V 0U, // BNE 0U, // BNE64 0U, // BNEC 0U, // BNEGI_B 0U, // BNEGI_D 0U, // BNEGI_H 0U, // BNEGI_W 0U, // BNEG_B 0U, // BNEG_D 0U, // BNEG_H 0U, // BNEG_W 0U, // BNEL 0U, // BNEZ16_MM 0U, // BNEZALC 0U, // BNEZC 0U, // BNEZC_MM 0U, // BNE_MM 0U, // BNVC 0U, // BNZ_B 0U, // BNZ_D 0U, // BNZ_H 0U, // BNZ_V 0U, // BNZ_W 0U, // BOVC 0U, // BPOSGE32 0U, // BPOSGE32_PSEUDO 0U, // BREAK 0U, // BREAK16_MM 0U, // BREAK_MM 1U, // BSELI_B 0U, // BSEL_D_PSEUDO 0U, // BSEL_FD_PSEUDO 0U, // BSEL_FW_PSEUDO 0U, // BSEL_H_PSEUDO 2U, // BSEL_V 0U, // BSEL_W_PSEUDO 0U, // BSETI_B 0U, // BSETI_D 0U, // BSETI_H 0U, // BSETI_W 0U, // BSET_B 0U, // BSET_D 0U, // BSET_H 0U, // BSET_W 0U, // BZ_B 0U, // BZ_D 0U, // BZ_H 0U, // BZ_V 0U, // BZ_W 0U, // B_MM_Pseudo 0U, // BeqzRxImm16 0U, // BeqzRxImmX16 0U, // Bimm16 0U, // BimmX16 0U, // BnezRxImm16 0U, // BnezRxImmX16 0U, // Break16 0U, // Bteqz16 0U, // BteqzT8CmpX16 0U, // BteqzT8CmpiX16 0U, // BteqzT8SltX16 0U, // BteqzT8SltiX16 0U, // BteqzT8SltiuX16 0U, // BteqzT8SltuX16 0U, // BteqzX16 0U, // Btnez16 0U, // BtnezT8CmpX16 0U, // BtnezT8CmpiX16 0U, // BtnezT8SltX16 0U, // BtnezT8SltiX16 0U, // BtnezT8SltiuX16 0U, // BtnezT8SltuX16 0U, // BtnezX16 0U, // BuildPairF64 0U, // BuildPairF64_64 0U, // CACHE 0U, // CACHE_MM 0U, // CACHE_R6 0U, // CEIL_L_D64 0U, // CEIL_L_S 0U, // CEIL_W_D32 0U, // CEIL_W_D64 0U, // CEIL_W_MM 0U, // CEIL_W_S 0U, // CEIL_W_S_MM 0U, // CEQI_B 0U, // CEQI_D 0U, // CEQI_H 0U, // CEQI_W 0U, // CEQ_B 0U, // CEQ_D 0U, // CEQ_H 0U, // CEQ_W 0U, // CFC1 0U, // CFC1_MM 0U, // CFCMSA 5U, // CINS 5U, // CINS32 0U, // CLASS_D 0U, // CLASS_S 0U, // CLEI_S_B 0U, // CLEI_S_D 0U, // CLEI_S_H 0U, // CLEI_S_W 0U, // CLEI_U_B 0U, // CLEI_U_D 0U, // CLEI_U_H 0U, // CLEI_U_W 0U, // CLE_S_B 0U, // CLE_S_D 0U, // CLE_S_H 0U, // CLE_S_W 0U, // CLE_U_B 0U, // CLE_U_D 0U, // CLE_U_H 0U, // CLE_U_W 0U, // CLO 0U, // CLO_MM 0U, // CLO_R6 0U, // CLTI_S_B 0U, // CLTI_S_D 0U, // CLTI_S_H 0U, // CLTI_S_W 0U, // CLTI_U_B 0U, // CLTI_U_D 0U, // CLTI_U_H 0U, // CLTI_U_W 0U, // CLT_S_B 0U, // CLT_S_D 0U, // CLT_S_H 0U, // CLT_S_W 0U, // CLT_U_B 0U, // CLT_U_D 0U, // CLT_U_H 0U, // CLT_U_W 0U, // CLZ 0U, // CLZ_MM 0U, // CLZ_R6 0U, // CMPGDU_EQ_QB 0U, // CMPGDU_LE_QB 0U, // CMPGDU_LT_QB 0U, // CMPGU_EQ_QB 0U, // CMPGU_LE_QB 0U, // CMPGU_LT_QB 0U, // CMPU_EQ_QB 0U, // CMPU_LE_QB 0U, // CMPU_LT_QB 0U, // CMP_EQ_D 0U, // CMP_EQ_PH 0U, // CMP_EQ_S 0U, // CMP_F_D 0U, // CMP_F_S 0U, // CMP_LE_D 0U, // CMP_LE_PH 0U, // CMP_LE_S 0U, // CMP_LT_D 0U, // CMP_LT_PH 0U, // CMP_LT_S 0U, // CMP_SAF_D 0U, // CMP_SAF_S 0U, // CMP_SEQ_D 0U, // CMP_SEQ_S 0U, // CMP_SLE_D 0U, // CMP_SLE_S 0U, // CMP_SLT_D 0U, // CMP_SLT_S 0U, // CMP_SUEQ_D 0U, // CMP_SUEQ_S 0U, // CMP_SULE_D 0U, // CMP_SULE_S 0U, // CMP_SULT_D 0U, // CMP_SULT_S 0U, // CMP_SUN_D 0U, // CMP_SUN_S 0U, // CMP_UEQ_D 0U, // CMP_UEQ_S 0U, // CMP_ULE_D 0U, // CMP_ULE_S 0U, // CMP_ULT_D 0U, // CMP_ULT_S 0U, // CMP_UN_D 0U, // CMP_UN_S 0U, // CONSTPOOL_ENTRY 0U, // COPY_FD_PSEUDO 0U, // COPY_FW_PSEUDO 8U, // COPY_S_B 8U, // COPY_S_D 8U, // COPY_S_H 8U, // COPY_S_W 8U, // COPY_U_B 8U, // COPY_U_D 8U, // COPY_U_H 8U, // COPY_U_W 0U, // CTC1 0U, // CTC1_MM 0U, // CTCMSA 0U, // CVT_D32_S 0U, // CVT_D32_W 0U, // CVT_D32_W_MM 0U, // CVT_D64_L 0U, // CVT_D64_S 0U, // CVT_D64_W 0U, // CVT_D_S_MM 0U, // CVT_L_D64 0U, // CVT_L_D64_MM 0U, // CVT_L_S 0U, // CVT_L_S_MM 0U, // CVT_S_D32 0U, // CVT_S_D32_MM 0U, // CVT_S_D64 0U, // CVT_S_L 0U, // CVT_S_W 0U, // CVT_S_W_MM 0U, // CVT_W_D32 0U, // CVT_W_D64 0U, // CVT_W_MM 0U, // CVT_W_S 0U, // CVT_W_S_MM 0U, // C_EQ_D32 0U, // C_EQ_D64 0U, // C_EQ_S 0U, // C_F_D32 0U, // C_F_D64 0U, // C_F_S 0U, // C_LE_D32 0U, // C_LE_D64 0U, // C_LE_S 0U, // C_LT_D32 0U, // C_LT_D64 0U, // C_LT_S 0U, // C_NGE_D32 0U, // C_NGE_D64 0U, // C_NGE_S 0U, // C_NGLE_D32 0U, // C_NGLE_D64 0U, // C_NGLE_S 0U, // C_NGL_D32 0U, // C_NGL_D64 0U, // C_NGL_S 0U, // C_NGT_D32 0U, // C_NGT_D64 0U, // C_NGT_S 0U, // C_OLE_D32 0U, // C_OLE_D64 0U, // C_OLE_S 0U, // C_OLT_D32 0U, // C_OLT_D64 0U, // C_OLT_S 0U, // C_SEQ_D32 0U, // C_SEQ_D64 0U, // C_SEQ_S 0U, // C_SF_D32 0U, // C_SF_D64 0U, // C_SF_S 0U, // C_UEQ_D32 0U, // C_UEQ_D64 0U, // C_UEQ_S 0U, // C_ULE_D32 0U, // C_ULE_D64 0U, // C_ULE_S 0U, // C_ULT_D32 0U, // C_ULT_D64 0U, // C_ULT_S 0U, // C_UN_D32 0U, // C_UN_D64 0U, // C_UN_S 0U, // CmpRxRy16 0U, // CmpiRxImm16 0U, // CmpiRxImmX16 0U, // Constant32 0U, // DADD 0U, // DADDi 0U, // DADDiu 0U, // DADDu 0U, // DAHI 4U, // DALIGN 0U, // DATI 0U, // DAUI 0U, // DBITSWAP 0U, // DCLO 0U, // DCLO_R6 0U, // DCLZ 0U, // DCLZ_R6 0U, // DDIV 0U, // DDIVU 0U, // DERET 0U, // DERET_MM 21U, // DEXT 21U, // DEXTM 21U, // DEXTU 0U, // DI 21U, // DINS 21U, // DINSM 21U, // DINSU 0U, // DIV 0U, // DIVU 0U, // DIV_S_B 0U, // DIV_S_D 0U, // DIV_S_H 0U, // DIV_S_W 0U, // DIV_U_B 0U, // DIV_U_D 0U, // DIV_U_H 0U, // DIV_U_W 0U, // DI_MM 4U, // DLSA 4U, // DLSA_R6 1U, // DMFC0 0U, // DMFC1 1U, // DMFC2 0U, // DMOD 0U, // DMODU 1U, // DMTC0 0U, // DMTC1 1U, // DMTC2 0U, // DMUH 0U, // DMUHU 0U, // DMUL 0U, // DMULT 0U, // DMULTu 0U, // DMULU 0U, // DMUL_R6 0U, // DOTP_S_D 0U, // DOTP_S_H 0U, // DOTP_S_W 0U, // DOTP_U_D 0U, // DOTP_U_H 0U, // DOTP_U_W 2U, // DPADD_S_D 2U, // DPADD_S_H 2U, // DPADD_S_W 2U, // DPADD_U_D 2U, // DPADD_U_H 2U, // DPADD_U_W 0U, // DPAQX_SA_W_PH 0U, // DPAQX_S_W_PH 0U, // DPAQ_SA_L_W 0U, // DPAQ_S_W_PH 0U, // DPAU_H_QBL 0U, // DPAU_H_QBR 0U, // DPAX_W_PH 0U, // DPA_W_PH 0U, // DPOP 0U, // DPSQX_SA_W_PH 0U, // DPSQX_S_W_PH 0U, // DPSQ_SA_L_W 0U, // DPSQ_S_W_PH 2U, // DPSUB_S_D 2U, // DPSUB_S_H 2U, // DPSUB_S_W 2U, // DPSUB_U_D 2U, // DPSUB_U_H 2U, // DPSUB_U_W 0U, // DPSU_H_QBL 0U, // DPSU_H_QBR 0U, // DPSX_W_PH 0U, // DPS_W_PH 1U, // DROTR 1U, // DROTR32 0U, // DROTRV 0U, // DSBH 0U, // DSDIV 0U, // DSHD 1U, // DSLL 1U, // DSLL32 0U, // DSLL64_32 0U, // DSLLV 1U, // DSRA 1U, // DSRA32 0U, // DSRAV 1U, // DSRL 1U, // DSRL32 0U, // DSRLV 0U, // DSUB 0U, // DSUBu 0U, // DUDIV 0U, // DivRxRy16 0U, // DivuRxRy16 0U, // EHB 0U, // EHB_MM 0U, // EI 0U, // EI_MM 0U, // ERET 0U, // ERET_MM 21U, // EXT 1U, // EXTP 1U, // EXTPDP 0U, // EXTPDPV 0U, // EXTPV 0U, // EXTRV_RS_W 0U, // EXTRV_R_W 0U, // EXTRV_S_H 0U, // EXTRV_W 1U, // EXTR_RS_W 1U, // EXTR_R_W 1U, // EXTR_S_H 1U, // EXTR_W 5U, // EXTS 5U, // EXTS32 21U, // EXT_MM 0U, // ExtractElementF64 0U, // ExtractElementF64_64 0U, // FABS_D 0U, // FABS_D32 0U, // FABS_D64 0U, // FABS_MM 0U, // FABS_S 0U, // FABS_S_MM 0U, // FABS_W 0U, // FADD_D 0U, // FADD_D32 0U, // FADD_D64 0U, // FADD_MM 0U, // FADD_S 0U, // FADD_S_MM 0U, // FADD_W 0U, // FCAF_D 0U, // FCAF_W 0U, // FCEQ_D 0U, // FCEQ_W 0U, // FCLASS_D 0U, // FCLASS_W 0U, // FCLE_D 0U, // FCLE_W 0U, // FCLT_D 0U, // FCLT_W 0U, // FCMP_D32 0U, // FCMP_D32_MM 0U, // FCMP_D64 0U, // FCMP_S32 0U, // FCMP_S32_MM 0U, // FCNE_D 0U, // FCNE_W 0U, // FCOR_D 0U, // FCOR_W 0U, // FCUEQ_D 0U, // FCUEQ_W 0U, // FCULE_D 0U, // FCULE_W 0U, // FCULT_D 0U, // FCULT_W 0U, // FCUNE_D 0U, // FCUNE_W 0U, // FCUN_D 0U, // FCUN_W 0U, // FDIV_D 0U, // FDIV_D32 0U, // FDIV_D64 0U, // FDIV_MM 0U, // FDIV_S 0U, // FDIV_S_MM 0U, // FDIV_W 0U, // FEXDO_H 0U, // FEXDO_W 0U, // FEXP2_D 0U, // FEXP2_D_1_PSEUDO 0U, // FEXP2_W 0U, // FEXP2_W_1_PSEUDO 0U, // FEXUPL_D 0U, // FEXUPL_W 0U, // FEXUPR_D 0U, // FEXUPR_W 0U, // FFINT_S_D 0U, // FFINT_S_W 0U, // FFINT_U_D 0U, // FFINT_U_W 0U, // FFQL_D 0U, // FFQL_W 0U, // FFQR_D 0U, // FFQR_W 0U, // FILL_B 0U, // FILL_D 0U, // FILL_FD_PSEUDO 0U, // FILL_FW_PSEUDO 0U, // FILL_H 0U, // FILL_W 0U, // FLOG2_D 0U, // FLOG2_W 0U, // FLOOR_L_D64 0U, // FLOOR_L_S 0U, // FLOOR_W_D32 0U, // FLOOR_W_D64 0U, // FLOOR_W_MM 0U, // FLOOR_W_S 0U, // FLOOR_W_S_MM 2U, // FMADD_D 2U, // FMADD_W 0U, // FMAX_A_D 0U, // FMAX_A_W 0U, // FMAX_D 0U, // FMAX_W 0U, // FMIN_A_D 0U, // FMIN_A_W 0U, // FMIN_D 0U, // FMIN_W 0U, // FMOV_D32 0U, // FMOV_D32_MM 0U, // FMOV_D64 0U, // FMOV_S 0U, // FMOV_S_MM 2U, // FMSUB_D 2U, // FMSUB_W 0U, // FMUL_D 0U, // FMUL_D32 0U, // FMUL_D64 0U, // FMUL_MM 0U, // FMUL_S 0U, // FMUL_S_MM 0U, // FMUL_W 0U, // FNEG_D32 0U, // FNEG_D64 0U, // FNEG_MM 0U, // FNEG_S 0U, // FNEG_S_MM 0U, // FRCP_D 0U, // FRCP_W 0U, // FRINT_D 0U, // FRINT_W 0U, // FRSQRT_D 0U, // FRSQRT_W 0U, // FSAF_D 0U, // FSAF_W 0U, // FSEQ_D 0U, // FSEQ_W 0U, // FSLE_D 0U, // FSLE_W 0U, // FSLT_D 0U, // FSLT_W 0U, // FSNE_D 0U, // FSNE_W 0U, // FSOR_D 0U, // FSOR_W 0U, // FSQRT_D 0U, // FSQRT_D32 0U, // FSQRT_D64 0U, // FSQRT_MM 0U, // FSQRT_S 0U, // FSQRT_S_MM 0U, // FSQRT_W 0U, // FSUB_D 0U, // FSUB_D32 0U, // FSUB_D64 0U, // FSUB_MM 0U, // FSUB_S 0U, // FSUB_S_MM 0U, // FSUB_W 0U, // FSUEQ_D 0U, // FSUEQ_W 0U, // FSULE_D 0U, // FSULE_W 0U, // FSULT_D 0U, // FSULT_W 0U, // FSUNE_D 0U, // FSUNE_W 0U, // FSUN_D 0U, // FSUN_W 0U, // FTINT_S_D 0U, // FTINT_S_W 0U, // FTINT_U_D 0U, // FTINT_U_W 0U, // FTQ_H 0U, // FTQ_W 0U, // FTRUNC_S_D 0U, // FTRUNC_S_W 0U, // FTRUNC_U_D 0U, // FTRUNC_U_W 0U, // GotPrologue16 0U, // HADD_S_D 0U, // HADD_S_H 0U, // HADD_S_W 0U, // HADD_U_D 0U, // HADD_U_H 0U, // HADD_U_W 0U, // HSUB_S_D 0U, // HSUB_S_H 0U, // HSUB_S_W 0U, // HSUB_U_D 0U, // HSUB_U_H 0U, // HSUB_U_W 0U, // ILVEV_B 0U, // ILVEV_D 0U, // ILVEV_H 0U, // ILVEV_W 0U, // ILVL_B 0U, // ILVL_D 0U, // ILVL_H 0U, // ILVL_W 0U, // ILVOD_B 0U, // ILVOD_D 0U, // ILVOD_H 0U, // ILVOD_W 0U, // ILVR_B 0U, // ILVR_D 0U, // ILVR_H 0U, // ILVR_W 21U, // INS 0U, // INSERT_B 0U, // INSERT_B_VIDX_PSEUDO 0U, // INSERT_D 0U, // INSERT_D_VIDX_PSEUDO 0U, // INSERT_FD_PSEUDO 0U, // INSERT_FD_VIDX_PSEUDO 0U, // INSERT_FW_PSEUDO 0U, // INSERT_FW_VIDX_PSEUDO 0U, // INSERT_H 0U, // INSERT_H_VIDX_PSEUDO 0U, // INSERT_W 0U, // INSERT_W_VIDX_PSEUDO 0U, // INSV 0U, // INSVE_B 0U, // INSVE_D 0U, // INSVE_H 0U, // INSVE_W 21U, // INS_MM 0U, // J 0U, // JAL 0U, // JALR 0U, // JALR16_MM 0U, // JALR64 0U, // JALR64Pseudo 0U, // JALRPseudo 0U, // JALRS16_MM 0U, // JALRS_MM 0U, // JALR_HB 0U, // JALR_MM 0U, // JALS_MM 0U, // JALX 0U, // JALX_MM 0U, // JAL_MM 0U, // JIALC 0U, // JIC 0U, // JR 0U, // JR16_MM 0U, // JR64 0U, // JRADDIUSP 0U, // JRC16_MM 0U, // JR_HB 0U, // JR_HB_R6 0U, // JR_MM 0U, // J_MM 0U, // Jal16 0U, // JalB16 0U, // JalOneReg 0U, // JalTwoReg 0U, // JrRa16 0U, // JrcRa16 0U, // JrcRx16 0U, // JumpLinkReg16 0U, // LB 0U, // LB64 0U, // LBU16_MM 0U, // LBUX 0U, // LB_MM 0U, // LBu 0U, // LBu64 0U, // LBu_MM 0U, // LD 0U, // LDC1 0U, // LDC164 0U, // LDC1_MM 0U, // LDC2 0U, // LDC2_R6 0U, // LDC3 0U, // LDI_B 0U, // LDI_D 0U, // LDI_H 0U, // LDI_W 0U, // LDL 0U, // LDPC 0U, // LDR 0U, // LDXC1 0U, // LDXC164 0U, // LD_B 0U, // LD_D 0U, // LD_H 0U, // LD_W 0U, // LEA_ADDiu 0U, // LEA_ADDiu64 0U, // LEA_ADDiu_MM 0U, // LH 0U, // LH64 0U, // LHU16_MM 0U, // LHX 0U, // LH_MM 0U, // LHu 0U, // LHu64 0U, // LHu_MM 0U, // LI16_MM 0U, // LL 0U, // LLD 0U, // LLD_R6 0U, // LL_MM 0U, // LL_R6 0U, // LOAD_ACC128 0U, // LOAD_ACC64 0U, // LOAD_ACC64DSP 0U, // LOAD_CCOND_DSP 0U, // LONG_BRANCH_ADDiu 0U, // LONG_BRANCH_DADDiu 0U, // LONG_BRANCH_LUi 4U, // LSA 4U, // LSA_R6 0U, // LUXC1 0U, // LUXC164 0U, // LUXC1_MM 0U, // LUi 0U, // LUi64 0U, // LUi_MM 0U, // LW 0U, // LW16_MM 0U, // LW64 0U, // LWC1 0U, // LWC1_MM 0U, // LWC2 0U, // LWC2_R6 0U, // LWC3 0U, // LWGP_MM 0U, // LWL 0U, // LWL64 0U, // LWL_MM 0U, // LWM16_MM 0U, // LWM32_MM 0U, // LWM_MM 0U, // LWPC 0U, // LWP_MM 0U, // LWR 0U, // LWR64 0U, // LWR_MM 0U, // LWSP_MM 0U, // LWUPC 0U, // LWU_MM 0U, // LWX 0U, // LWXC1 0U, // LWXC1_MM 0U, // LWXS_MM 0U, // LW_MM 0U, // LWu 0U, // LbRxRyOffMemX16 0U, // LbuRxRyOffMemX16 0U, // LhRxRyOffMemX16 0U, // LhuRxRyOffMemX16 0U, // LiRxImm16 0U, // LiRxImmAlignX16 0U, // LiRxImmX16 0U, // LoadAddr32Imm 0U, // LoadAddr32Reg 0U, // LoadImm32Reg 0U, // LoadImm64Reg 0U, // LwConstant32 0U, // LwRxPcTcp16 0U, // LwRxPcTcpX16 0U, // LwRxRyOffMemX16 0U, // LwRxSpImmX16 0U, // MADD 2U, // MADDF_D 2U, // MADDF_S 2U, // MADDR_Q_H 2U, // MADDR_Q_W 0U, // MADDU 0U, // MADDU_DSP 0U, // MADDU_MM 2U, // MADDV_B 2U, // MADDV_D 2U, // MADDV_H 2U, // MADDV_W 20U, // MADD_D32 20U, // MADD_D32_MM 20U, // MADD_D64 0U, // MADD_DSP 0U, // MADD_MM 2U, // MADD_Q_H 2U, // MADD_Q_W 20U, // MADD_S 20U, // MADD_S_MM 0U, // MAQ_SA_W_PHL 0U, // MAQ_SA_W_PHR 0U, // MAQ_S_W_PHL 0U, // MAQ_S_W_PHR 0U, // MAXA_D 0U, // MAXA_S 0U, // MAXI_S_B 0U, // MAXI_S_D 0U, // MAXI_S_H 0U, // MAXI_S_W 0U, // MAXI_U_B 0U, // MAXI_U_D 0U, // MAXI_U_H 0U, // MAXI_U_W 0U, // MAX_A_B 0U, // MAX_A_D 0U, // MAX_A_H 0U, // MAX_A_W 0U, // MAX_D 0U, // MAX_S 0U, // MAX_S_B 0U, // MAX_S_D 0U, // MAX_S_H 0U, // MAX_S_W 0U, // MAX_U_B 0U, // MAX_U_D 0U, // MAX_U_H 0U, // MAX_U_W 1U, // MFC0 0U, // MFC1 0U, // MFC1_MM 1U, // MFC2 0U, // MFHC1_D32 0U, // MFHC1_D64 0U, // MFHC1_MM 0U, // MFHI 0U, // MFHI16_MM 0U, // MFHI64 0U, // MFHI_DSP 0U, // MFHI_MM 0U, // MFLO 0U, // MFLO16_MM 0U, // MFLO64 0U, // MFLO_DSP 0U, // MFLO_MM 0U, // MINA_D 0U, // MINA_S 0U, // MINI_S_B 0U, // MINI_S_D 0U, // MINI_S_H 0U, // MINI_S_W 0U, // MINI_U_B 0U, // MINI_U_D 0U, // MINI_U_H 0U, // MINI_U_W 0U, // MIN_A_B 0U, // MIN_A_D 0U, // MIN_A_H 0U, // MIN_A_W 0U, // MIN_D 0U, // MIN_S 0U, // MIN_S_B 0U, // MIN_S_D 0U, // MIN_S_H 0U, // MIN_S_W 0U, // MIN_U_B 0U, // MIN_U_D 0U, // MIN_U_H 0U, // MIN_U_W 0U, // MIPSeh_return32 0U, // MIPSeh_return64 0U, // MOD 0U, // MODSUB 0U, // MODU 0U, // MOD_S_B 0U, // MOD_S_D 0U, // MOD_S_H 0U, // MOD_S_W 0U, // MOD_U_B 0U, // MOD_U_D 0U, // MOD_U_H 0U, // MOD_U_W 0U, // MOVE16_MM 0U, // MOVEP_MM 0U, // MOVE_V 0U, // MOVF_D32 0U, // MOVF_D32_MM 0U, // MOVF_D64 0U, // MOVF_I 0U, // MOVF_I64 0U, // MOVF_I_MM 0U, // MOVF_S 0U, // MOVF_S_MM 0U, // MOVN_I64_D64 0U, // MOVN_I64_I 0U, // MOVN_I64_I64 0U, // MOVN_I64_S 0U, // MOVN_I_D32 0U, // MOVN_I_D32_MM 0U, // MOVN_I_D64 0U, // MOVN_I_I 0U, // MOVN_I_I64 0U, // MOVN_I_MM 0U, // MOVN_I_S 0U, // MOVN_I_S_MM 0U, // MOVT_D32 0U, // MOVT_D32_MM 0U, // MOVT_D64 0U, // MOVT_I 0U, // MOVT_I64 0U, // MOVT_I_MM 0U, // MOVT_S 0U, // MOVT_S_MM 0U, // MOVZ_I64_D64 0U, // MOVZ_I64_I 0U, // MOVZ_I64_I64 0U, // MOVZ_I64_S 0U, // MOVZ_I_D32 0U, // MOVZ_I_D32_MM 0U, // MOVZ_I_D64 0U, // MOVZ_I_I 0U, // MOVZ_I_I64 0U, // MOVZ_I_MM 0U, // MOVZ_I_S 0U, // MOVZ_I_S_MM 0U, // MSUB 2U, // MSUBF_D 2U, // MSUBF_S 2U, // MSUBR_Q_H 2U, // MSUBR_Q_W 0U, // MSUBU 0U, // MSUBU_DSP 0U, // MSUBU_MM 2U, // MSUBV_B 2U, // MSUBV_D 2U, // MSUBV_H 2U, // MSUBV_W 20U, // MSUB_D32 20U, // MSUB_D32_MM 20U, // MSUB_D64 0U, // MSUB_DSP 0U, // MSUB_MM 2U, // MSUB_Q_H 2U, // MSUB_Q_W 20U, // MSUB_S 20U, // MSUB_S_MM 1U, // MTC0 0U, // MTC1 0U, // MTC1_MM 1U, // MTC2 0U, // MTHC1_D32 0U, // MTHC1_D64 0U, // MTHC1_MM 0U, // MTHI 0U, // MTHI64 0U, // MTHI_DSP 0U, // MTHI_MM 0U, // MTHLIP 0U, // MTLO 0U, // MTLO64 0U, // MTLO_DSP 0U, // MTLO_MM 0U, // MTM0 0U, // MTM1 0U, // MTM2 0U, // MTP0 0U, // MTP1 0U, // MTP2 0U, // MUH 0U, // MUHU 0U, // MUL 0U, // MULEQ_S_W_PHL 0U, // MULEQ_S_W_PHR 0U, // MULEU_S_PH_QBL 0U, // MULEU_S_PH_QBR 0U, // MULQ_RS_PH 0U, // MULQ_RS_W 0U, // MULQ_S_PH 0U, // MULQ_S_W 0U, // MULR_Q_H 0U, // MULR_Q_W 0U, // MULSAQ_S_W_PH 0U, // MULSA_W_PH 0U, // MULT 0U, // MULTU_DSP 0U, // MULT_DSP 0U, // MULT_MM 0U, // MULTu 0U, // MULTu_MM 0U, // MULU 0U, // MULV_B 0U, // MULV_D 0U, // MULV_H 0U, // MULV_W 0U, // MUL_MM 0U, // MUL_PH 0U, // MUL_Q_H 0U, // MUL_Q_W 0U, // MUL_R6 0U, // MUL_S_PH 0U, // Mfhi16 0U, // Mflo16 0U, // Move32R16 0U, // MoveR3216 0U, // MultRxRy16 0U, // MultRxRyRz16 0U, // MultuRxRy16 0U, // MultuRxRyRz16 0U, // NLOC_B 0U, // NLOC_D 0U, // NLOC_H 0U, // NLOC_W 0U, // NLZC_B 0U, // NLZC_D 0U, // NLZC_H 0U, // NLZC_W 20U, // NMADD_D32 20U, // NMADD_D32_MM 20U, // NMADD_D64 20U, // NMADD_S 20U, // NMADD_S_MM 20U, // NMSUB_D32 20U, // NMSUB_D32_MM 20U, // NMSUB_D64 20U, // NMSUB_S 20U, // NMSUB_S_MM 0U, // NOP 0U, // NOR 0U, // NOR64 0U, // NORI_B 0U, // NOR_MM 0U, // NOR_V 0U, // NOR_V_D_PSEUDO 0U, // NOR_V_H_PSEUDO 0U, // NOR_V_W_PSEUDO 0U, // NOT16_MM 0U, // NegRxRy16 0U, // NotRxRy16 0U, // OR 0U, // OR16_MM 0U, // OR64 0U, // ORI_B 0U, // OR_MM 0U, // OR_V 0U, // OR_V_D_PSEUDO 0U, // OR_V_H_PSEUDO 0U, // OR_V_W_PSEUDO 1U, // ORi 1U, // ORi64 1U, // ORi_MM 0U, // OrRxRxRy16 0U, // PACKRL_PH 0U, // PAUSE 0U, // PAUSE_MM 0U, // PCKEV_B 0U, // PCKEV_D 0U, // PCKEV_H 0U, // PCKEV_W 0U, // PCKOD_B 0U, // PCKOD_D 0U, // PCKOD_H 0U, // PCKOD_W 0U, // PCNT_B 0U, // PCNT_D 0U, // PCNT_H 0U, // PCNT_W 0U, // PICK_PH 0U, // PICK_QB 0U, // POP 0U, // PRECEQU_PH_QBL 0U, // PRECEQU_PH_QBLA 0U, // PRECEQU_PH_QBR 0U, // PRECEQU_PH_QBRA 0U, // PRECEQ_W_PHL 0U, // PRECEQ_W_PHR 0U, // PRECEU_PH_QBL 0U, // PRECEU_PH_QBLA 0U, // PRECEU_PH_QBR 0U, // PRECEU_PH_QBRA 0U, // PRECRQU_S_QB_PH 0U, // PRECRQ_PH_W 0U, // PRECRQ_QB_PH 0U, // PRECRQ_RS_PH_W 0U, // PRECR_QB_PH 1U, // PRECR_SRA_PH_W 1U, // PRECR_SRA_R_PH_W 0U, // PREF 0U, // PREF_MM 0U, // PREF_R6 1U, // PREPEND 0U, // PseudoCMPU_EQ_QB 0U, // PseudoCMPU_LE_QB 0U, // PseudoCMPU_LT_QB 0U, // PseudoCMP_EQ_PH 0U, // PseudoCMP_LE_PH 0U, // PseudoCMP_LT_PH 0U, // PseudoCVT_D32_W 0U, // PseudoCVT_D64_L 0U, // PseudoCVT_D64_W 0U, // PseudoCVT_S_L 0U, // PseudoCVT_S_W 0U, // PseudoDMULT 0U, // PseudoDMULTu 0U, // PseudoDSDIV 0U, // PseudoDUDIV 0U, // PseudoIndirectBranch 0U, // PseudoIndirectBranch64 0U, // PseudoMADD 0U, // PseudoMADDU 0U, // PseudoMFHI 0U, // PseudoMFHI64 0U, // PseudoMFLO 0U, // PseudoMFLO64 0U, // PseudoMSUB 0U, // PseudoMSUBU 0U, // PseudoMTLOHI 0U, // PseudoMTLOHI64 0U, // PseudoMTLOHI_DSP 0U, // PseudoMULT 0U, // PseudoMULTu 0U, // PseudoPICK_PH 0U, // PseudoPICK_QB 0U, // PseudoReturn 0U, // PseudoReturn64 0U, // PseudoSDIV 0U, // PseudoSELECTFP_F_D32 0U, // PseudoSELECTFP_F_D64 0U, // PseudoSELECTFP_F_I 0U, // PseudoSELECTFP_F_I64 0U, // PseudoSELECTFP_F_S 0U, // PseudoSELECTFP_T_D32 0U, // PseudoSELECTFP_T_D64 0U, // PseudoSELECTFP_T_I 0U, // PseudoSELECTFP_T_I64 0U, // PseudoSELECTFP_T_S 0U, // PseudoSELECT_D32 0U, // PseudoSELECT_D64 0U, // PseudoSELECT_I 0U, // PseudoSELECT_I64 0U, // PseudoSELECT_S 0U, // PseudoUDIV 0U, // RADDU_W_QB 0U, // RDDSP 0U, // RDHWR 0U, // RDHWR64 0U, // RDHWR_MM 0U, // REPLV_PH 0U, // REPLV_QB 0U, // REPL_PH 0U, // REPL_QB 0U, // RINT_D 0U, // RINT_S 1U, // ROTR 0U, // ROTRV 0U, // ROTRV_MM 1U, // ROTR_MM 0U, // ROUND_L_D64 0U, // ROUND_L_S 0U, // ROUND_W_D32 0U, // ROUND_W_D64 0U, // ROUND_W_MM 0U, // ROUND_W_S 0U, // ROUND_W_S_MM 0U, // Restore16 0U, // RestoreX16 0U, // RetRA 0U, // RetRA16 1U, // SAT_S_B 1U, // SAT_S_D 0U, // SAT_S_H 1U, // SAT_S_W 1U, // SAT_U_B 1U, // SAT_U_D 0U, // SAT_U_H 1U, // SAT_U_W 0U, // SB 0U, // SB16_MM 0U, // SB64 0U, // SB_MM 0U, // SC 0U, // SCD 0U, // SCD_R6 0U, // SC_MM 0U, // SC_R6 0U, // SD 0U, // SDBBP 0U, // SDBBP16_MM 0U, // SDBBP_MM 0U, // SDBBP_R6 0U, // SDC1 0U, // SDC164 0U, // SDC1_MM 0U, // SDC2 0U, // SDC2_R6 0U, // SDC3 0U, // SDIV 0U, // SDIV_MM 0U, // SDL 0U, // SDR 0U, // SDXC1 0U, // SDXC164 0U, // SEB 0U, // SEB64 0U, // SEB_MM 0U, // SEH 0U, // SEH64 0U, // SEH_MM 0U, // SELEQZ 0U, // SELEQZ64 0U, // SELEQZ_D 0U, // SELEQZ_S 0U, // SELNEZ 0U, // SELNEZ64 0U, // SELNEZ_D 0U, // SELNEZ_S 2U, // SEL_D 2U, // SEL_S 0U, // SEQ 0U, // SEQi 0U, // SH 0U, // SH16_MM 0U, // SH64 0U, // SHF_B 0U, // SHF_H 0U, // SHF_W 0U, // SHILO 0U, // SHILOV 0U, // SHLLV_PH 0U, // SHLLV_QB 0U, // SHLLV_S_PH 0U, // SHLLV_S_W 1U, // SHLL_PH 1U, // SHLL_QB 1U, // SHLL_S_PH 1U, // SHLL_S_W 0U, // SHRAV_PH 0U, // SHRAV_QB 0U, // SHRAV_R_PH 0U, // SHRAV_R_QB 0U, // SHRAV_R_W 1U, // SHRA_PH 1U, // SHRA_QB 1U, // SHRA_R_PH 1U, // SHRA_R_QB 1U, // SHRA_R_W 0U, // SHRLV_PH 0U, // SHRLV_QB 1U, // SHRL_PH 1U, // SHRL_QB 0U, // SH_MM 9U, // SLDI_B 9U, // SLDI_D 9U, // SLDI_H 9U, // SLDI_W 10U, // SLD_B 10U, // SLD_D 10U, // SLD_H 10U, // SLD_W 1U, // SLL 0U, // SLL16_MM 0U, // SLL64_32 0U, // SLL64_64 0U, // SLLI_B 0U, // SLLI_D 0U, // SLLI_H 0U, // SLLI_W 0U, // SLLV 0U, // SLLV_MM 0U, // SLL_B 0U, // SLL_D 0U, // SLL_H 1U, // SLL_MM 0U, // SLL_W 0U, // SLT 0U, // SLT64 0U, // SLT_MM 0U, // SLTi 0U, // SLTi64 0U, // SLTi_MM 0U, // SLTiu 0U, // SLTiu64 0U, // SLTiu_MM 0U, // SLTu 0U, // SLTu64 0U, // SLTu_MM 0U, // SNE 0U, // SNEi 0U, // SNZ_B_PSEUDO 0U, // SNZ_D_PSEUDO 0U, // SNZ_H_PSEUDO 0U, // SNZ_V_PSEUDO 0U, // SNZ_W_PSEUDO 8U, // SPLATI_B 8U, // SPLATI_D 8U, // SPLATI_H 8U, // SPLATI_W 8U, // SPLAT_B 8U, // SPLAT_D 8U, // SPLAT_H 8U, // SPLAT_W 1U, // SRA 0U, // SRAI_B 0U, // SRAI_D 0U, // SRAI_H 0U, // SRAI_W 1U, // SRARI_B 1U, // SRARI_D 0U, // SRARI_H 1U, // SRARI_W 0U, // SRAR_B 0U, // SRAR_D 0U, // SRAR_H 0U, // SRAR_W 0U, // SRAV 0U, // SRAV_MM 0U, // SRA_B 0U, // SRA_D 0U, // SRA_H 1U, // SRA_MM 0U, // SRA_W 1U, // SRL 0U, // SRL16_MM 0U, // SRLI_B 0U, // SRLI_D 0U, // SRLI_H 0U, // SRLI_W 1U, // SRLRI_B 1U, // SRLRI_D 0U, // SRLRI_H 1U, // SRLRI_W 0U, // SRLR_B 0U, // SRLR_D 0U, // SRLR_H 0U, // SRLR_W 0U, // SRLV 0U, // SRLV_MM 0U, // SRL_B 0U, // SRL_D 0U, // SRL_H 1U, // SRL_MM 0U, // SRL_W 0U, // SSNOP 0U, // SSNOP_MM 0U, // STORE_ACC128 0U, // STORE_ACC64 0U, // STORE_ACC64DSP 0U, // STORE_CCOND_DSP 0U, // ST_B 0U, // ST_D 0U, // ST_H 0U, // ST_W 0U, // SUB 0U, // SUBQH_PH 0U, // SUBQH_R_PH 0U, // SUBQH_R_W 0U, // SUBQH_W 0U, // SUBQ_PH 0U, // SUBQ_S_PH 0U, // SUBQ_S_W 0U, // SUBSUS_U_B 0U, // SUBSUS_U_D 0U, // SUBSUS_U_H 0U, // SUBSUS_U_W 0U, // SUBSUU_S_B 0U, // SUBSUU_S_D 0U, // SUBSUU_S_H 0U, // SUBSUU_S_W 0U, // SUBS_S_B 0U, // SUBS_S_D 0U, // SUBS_S_H 0U, // SUBS_S_W 0U, // SUBS_U_B 0U, // SUBS_U_D 0U, // SUBS_U_H 0U, // SUBS_U_W 0U, // SUBU16_MM 0U, // SUBUH_QB 0U, // SUBUH_R_QB 0U, // SUBU_PH 0U, // SUBU_QB 0U, // SUBU_S_PH 0U, // SUBU_S_QB 0U, // SUBVI_B 0U, // SUBVI_D 0U, // SUBVI_H 0U, // SUBVI_W 0U, // SUBV_B 0U, // SUBV_D 0U, // SUBV_H 0U, // SUBV_W 0U, // SUB_MM 0U, // SUBu 0U, // SUBu_MM 0U, // SUXC1 0U, // SUXC164 0U, // SUXC1_MM 0U, // SW 0U, // SW16_MM 0U, // SW64 0U, // SWC1 0U, // SWC1_MM 0U, // SWC2 0U, // SWC2_R6 0U, // SWC3 0U, // SWL 0U, // SWL64 0U, // SWL_MM 0U, // SWM16_MM 0U, // SWM32_MM 0U, // SWM_MM 0U, // SWP_MM 0U, // SWR 0U, // SWR64 0U, // SWR_MM 0U, // SWSP_MM 0U, // SWXC1 0U, // SWXC1_MM 0U, // SW_MM 0U, // SYNC 0U, // SYNCI 0U, // SYNC_MM 0U, // SYSCALL 0U, // SYSCALL_MM 0U, // SZ_B_PSEUDO 0U, // SZ_D_PSEUDO 0U, // SZ_H_PSEUDO 0U, // SZ_V_PSEUDO 0U, // SZ_W_PSEUDO 0U, // Save16 0U, // SaveX16 0U, // SbRxRyOffMemX16 0U, // SebRx16 0U, // SehRx16 0U, // SelBeqZ 0U, // SelBneZ 0U, // SelTBteqZCmp 0U, // SelTBteqZCmpi 0U, // SelTBteqZSlt 0U, // SelTBteqZSlti 0U, // SelTBteqZSltiu 0U, // SelTBteqZSltu 0U, // SelTBtneZCmp 0U, // SelTBtneZCmpi 0U, // SelTBtneZSlt 0U, // SelTBtneZSlti 0U, // SelTBtneZSltiu 0U, // SelTBtneZSltu 0U, // ShRxRyOffMemX16 1U, // SllX16 0U, // SllvRxRy16 0U, // SltCCRxRy16 0U, // SltRxRy16 0U, // SltiCCRxImmX16 0U, // SltiRxImm16 0U, // SltiRxImmX16 0U, // SltiuCCRxImmX16 0U, // SltiuRxImm16 0U, // SltiuRxImmX16 0U, // SltuCCRxRy16 0U, // SltuRxRy16 0U, // SltuRxRyRz16 1U, // SraX16 0U, // SravRxRy16 1U, // SrlX16 0U, // SrlvRxRy16 0U, // SubuRxRyRz16 0U, // SwRxRyOffMemX16 0U, // SwRxSpImmX16 0U, // TAILCALL 0U, // TAILCALL64_R 0U, // TAILCALL_R 1U, // TEQ 0U, // TEQI 0U, // TEQI_MM 1U, // TEQ_MM 1U, // TGE 0U, // TGEI 0U, // TGEIU 0U, // TGEIU_MM 0U, // TGEI_MM 1U, // TGEU 1U, // TGEU_MM 1U, // TGE_MM 0U, // TLBP 0U, // TLBP_MM 0U, // TLBR 0U, // TLBR_MM 0U, // TLBWI 0U, // TLBWI_MM 0U, // TLBWR 0U, // TLBWR_MM 1U, // TLT 0U, // TLTI 0U, // TLTIU_MM 0U, // TLTI_MM 1U, // TLTU 1U, // TLTU_MM 1U, // TLT_MM 1U, // TNE 0U, // TNEI 0U, // TNEI_MM 1U, // TNE_MM 0U, // TRAP 0U, // TRUNC_L_D64 0U, // TRUNC_L_S 0U, // TRUNC_W_D32 0U, // TRUNC_W_D64 0U, // TRUNC_W_MM 0U, // TRUNC_W_S 0U, // TRUNC_W_S_MM 0U, // TTLTIU 0U, // UDIV 0U, // UDIV_MM 0U, // V3MULU 0U, // VMM0 0U, // VMULU 2U, // VSHF_B 2U, // VSHF_D 2U, // VSHF_H 2U, // VSHF_W 0U, // WAIT 0U, // WAIT_MM 0U, // WRDSP 0U, // WSBH 0U, // WSBH_MM 0U, // XOR 0U, // XOR16_MM 0U, // XOR64 0U, // XORI_B 0U, // XOR_MM 0U, // XOR_V 0U, // XOR_V_D_PSEUDO 0U, // XOR_V_H_PSEUDO 0U, // XOR_V_W_PSEUDO 1U, // XORi 1U, // XORi64 1U, // XORi_MM 0U, // XorRxRxRy16 0U }; #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, /* 22 */ 'v', 'm', 'm', '0', 9, 0, /* 28 */ 'm', 't', 'm', '0', 9, 0, /* 34 */ 'm', 't', 'p', '0', 9, 0, /* 40 */ 'b', 'b', 'i', 't', '0', 9, 0, /* 47 */ 'l', 'd', 'c', '1', 9, 0, /* 53 */ 's', 'd', 'c', '1', 9, 0, /* 59 */ 'c', 'f', 'c', '1', 9, 0, /* 65 */ 'd', 'm', 'f', 'c', '1', 9, 0, /* 72 */ 'm', 'f', 'h', 'c', '1', 9, 0, /* 79 */ 'm', 't', 'h', 'c', '1', 9, 0, /* 86 */ 'c', 't', 'c', '1', 9, 0, /* 92 */ 'd', 'm', 't', 'c', '1', 9, 0, /* 99 */ 'l', 'w', 'c', '1', 9, 0, /* 105 */ 's', 'w', 'c', '1', 9, 0, /* 111 */ 'l', 'd', 'x', 'c', '1', 9, 0, /* 118 */ 's', 'd', 'x', 'c', '1', 9, 0, /* 125 */ 'l', 'u', 'x', 'c', '1', 9, 0, /* 132 */ 's', 'u', 'x', 'c', '1', 9, 0, /* 139 */ 'l', 'w', 'x', 'c', '1', 9, 0, /* 146 */ 's', 'w', 'x', 'c', '1', 9, 0, /* 153 */ 'm', 't', 'm', '1', 9, 0, /* 159 */ 'm', 't', 'p', '1', 9, 0, /* 165 */ 'b', 'b', 'i', 't', '1', 9, 0, /* 172 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0, /* 181 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0, /* 190 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, /* 198 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, /* 208 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, /* 216 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, /* 224 */ 'l', 'w', 'm', '3', '2', 9, 0, /* 231 */ 's', 'w', 'm', '3', '2', 9, 0, /* 238 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, /* 247 */ 'l', 'd', 'c', '2', 9, 0, /* 253 */ 's', 'd', 'c', '2', 9, 0, /* 259 */ 'd', 'm', 'f', 'c', '2', 9, 0, /* 266 */ 'd', 'm', 't', 'c', '2', 9, 0, /* 273 */ 'l', 'w', 'c', '2', 9, 0, /* 279 */ 's', 'w', 'c', '2', 9, 0, /* 285 */ 'm', 't', 'm', '2', 9, 0, /* 291 */ 'm', 't', 'p', '2', 9, 0, /* 297 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0, /* 306 */ 'l', 'd', 'c', '3', 9, 0, /* 312 */ 's', 'd', 'c', '3', 9, 0, /* 318 */ 'l', 'w', 'c', '3', 9, 0, /* 324 */ 's', 'w', 'c', '3', 9, 0, /* 330 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0, /* 339 */ 's', 'b', '1', '6', 9, 0, /* 345 */ 'a', 'n', 'd', '1', '6', 9, 0, /* 352 */ 's', 'h', '1', '6', 9, 0, /* 358 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0, /* 366 */ 'l', 'i', '1', '6', 9, 0, /* 372 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0, /* 381 */ 's', 'l', 'l', '1', '6', 9, 0, /* 388 */ 's', 'r', 'l', '1', '6', 9, 0, /* 395 */ 'l', 'w', 'm', '1', '6', 9, 0, /* 402 */ 's', 'w', 'm', '1', '6', 9, 0, /* 409 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0, /* 418 */ 'j', 'r', '1', '6', 9, 0, /* 424 */ 'x', 'o', 'r', '1', '6', 9, 0, /* 431 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0, /* 440 */ 'n', 'o', 't', '1', '6', 9, 0, /* 447 */ 'l', 'b', 'u', '1', '6', 9, 0, /* 454 */ 's', 'u', 'b', 'u', '1', '6', 9, 0, /* 462 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0, /* 470 */ 'l', 'h', 'u', '1', '6', 9, 0, /* 477 */ 'l', 'w', '1', '6', 9, 0, /* 483 */ 's', 'w', '1', '6', 9, 0, /* 489 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0, /* 497 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0, /* 505 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, /* 521 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, /* 538 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, /* 554 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, /* 571 */ 'd', 's', 'r', 'a', 9, 0, /* 577 */ 'd', 'l', 's', 'a', 9, 0, /* 583 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, /* 591 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, /* 599 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, /* 608 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, /* 617 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, /* 627 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, /* 636 */ 's', 'r', 'a', '.', 'b', 9, 0, /* 643 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, /* 651 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, /* 659 */ 's', 'l', 'd', '.', 'b', 9, 0, /* 666 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, /* 675 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, /* 684 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, /* 693 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, /* 701 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, /* 709 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, /* 717 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, /* 725 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, /* 733 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, /* 742 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, /* 751 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, /* 759 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, /* 767 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, /* 777 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, /* 785 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, /* 794 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, /* 803 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, /* 812 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, /* 820 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, /* 828 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, /* 838 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, /* 848 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, /* 857 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, /* 866 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, /* 875 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, /* 883 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, /* 892 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, /* 900 */ 's', 'l', 'l', '.', 'b', 9, 0, /* 907 */ 's', 'r', 'l', '.', 'b', 9, 0, /* 914 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, /* 923 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, /* 931 */ 'c', 'e', 'q', '.', 'b', 9, 0, /* 938 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, /* 946 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, /* 954 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, /* 962 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, /* 971 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, /* 979 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, /* 989 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, /* 998 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, /* 1007 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, /* 1016 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, /* 1026 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, /* 1036 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, /* 1046 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, /* 1056 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, /* 1065 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, /* 1075 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, /* 1085 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 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7471 */ 's', 'r', 'a', '.', 'w', 9, 0, /* 7478 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0, /* 7486 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0, /* 7495 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0, /* 7503 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0, /* 7511 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, /* 7520 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0, /* 7528 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0, /* 7537 */ 's', 'l', 'd', '.', 'w', 9, 0, /* 7544 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0, /* 7553 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0, /* 7562 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0, /* 7570 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0, /* 7578 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0, /* 7587 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0, /* 7596 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0, /* 7604 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0, /* 7612 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0, /* 7621 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0, /* 7630 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0, /* 7639 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0, /* 7647 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0, /* 7655 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0, /* 7663 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0, /* 7671 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0, /* 7687 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0, /* 7700 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0, /* 7718 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0, /* 7734 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0, /* 7743 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0, /* 7752 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0, /* 7760 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, /* 7768 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, /* 7777 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, /* 7785 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, /* 7793 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, /* 7803 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, /* 7811 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, /* 7820 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, /* 7829 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, /* 7838 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, /* 7848 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, /* 7858 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, /* 7867 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, /* 7876 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, /* 7885 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, /* 7898 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, /* 7911 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, /* 7919 */ 's', 'l', 'l', '.', 'w', 9, 0, /* 7926 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, /* 7936 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, /* 7944 */ 's', 'r', 'l', '.', 'w', 9, 0, /* 7951 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, /* 7960 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, /* 7968 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, /* 7976 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, /* 7984 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, /* 7992 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, /* 8000 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, /* 8009 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, /* 8017 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, /* 8027 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, /* 8037 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, /* 8046 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, /* 8057 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, /* 8068 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, /* 8078 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, /* 8086 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, /* 8094 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, /* 8103 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, /* 8112 */ 'f', 't', 'q', '.', 'w', 9, 0, /* 8119 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, /* 8129 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, /* 8140 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, /* 8151 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, /* 8161 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, /* 8172 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, /* 8183 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, /* 8191 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, /* 8199 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, /* 8207 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, /* 8215 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, /* 8223 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, /* 8233 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, /* 8241 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, /* 8250 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, /* 8258 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, /* 8266 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, /* 8275 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, /* 8285 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, /* 8295 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, /* 8306 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, /* 8318 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, /* 8328 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, /* 8339 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, /* 8348 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, /* 8357 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, /* 8366 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, /* 8376 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, /* 8386 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, /* 8396 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, /* 8406 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, /* 8416 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, /* 8425 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, /* 8435 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, /* 8445 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, /* 8455 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, /* 8465 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, /* 8475 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, /* 8485 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, /* 8495 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, /* 8505 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, /* 8514 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, /* 8523 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, /* 8534 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, /* 8545 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, /* 8557 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, /* 8566 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, /* 8577 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, /* 8586 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, /* 8596 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, /* 8607 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, /* 8618 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, /* 8630 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, /* 8640 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, /* 8649 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, /* 8657 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, /* 8665 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, /* 8673 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, /* 8682 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, /* 8691 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, /* 8699 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, /* 8708 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, /* 8718 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, /* 8727 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, /* 8737 */ 's', 't', '.', 'w', 9, 0, /* 8743 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, /* 8753 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, /* 8763 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, /* 8774 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, /* 8786 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, /* 8796 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, /* 8807 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, /* 8816 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, /* 8825 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, /* 8834 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, /* 8844 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, /* 8854 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, /* 8864 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, /* 8874 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, /* 8883 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, /* 8893 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, /* 8903 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, /* 8913 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, /* 8923 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, /* 8935 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, /* 8944 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, /* 8953 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, /* 8964 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, /* 8975 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, /* 8984 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, /* 8993 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, /* 9003 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, /* 9012 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, /* 9021 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, /* 9030 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, /* 9039 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, /* 9047 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, /* 9055 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, /* 9064 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, /* 9072 */ 'b', 'z', '.', 'w', 9, 0, /* 9078 */ 'b', 'n', 'z', '.', 'w', 9, 0, /* 9085 */ 'l', 'w', 9, 0, /* 9089 */ 's', 'w', 9, 0, /* 9093 */ 'l', 'h', 'x', 9, 0, /* 9098 */ 'j', 'a', 'l', 'x', 9, 0, /* 9104 */ 'l', 'b', 'u', 'x', 9, 0, /* 9110 */ 'l', 'w', 'x', 9, 0, /* 9115 */ 'b', 'g', 'e', 'z', 9, 0, /* 9121 */ 'b', 'l', 'e', 'z', 9, 0, /* 9127 */ 'b', 'n', 'e', 'z', 9, 0, /* 9133 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, /* 9141 */ 'b', 't', 'n', 'e', 'z', 9, 0, /* 9148 */ 'd', 'c', 'l', 'z', 9, 0, /* 9154 */ 'b', 'e', 'q', 'z', 9, 0, /* 9160 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, /* 9168 */ 'b', 't', 'e', 'q', 'z', 9, 0, /* 9175 */ 'b', 'g', 't', 'z', 9, 0, /* 9181 */ 'b', 'l', 't', 'z', 9, 0, /* 9187 */ 'm', 'o', 'v', 'z', 9, 0, /* 9193 */ 's', 'e', 'b', 9, 32, 0, /* 9199 */ 'j', 'r', 'c', 9, 32, 0, /* 9205 */ 's', 'e', 'h', 9, 32, 0, /* 9211 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, /* 9225 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, /* 9238 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, /* 9250 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, /* 9258 */ 'e', 'x', 't', 's', '3', '2', 32, 0, /* 9266 */ 's', 'y', 'n', 'c', 32, 0, /* 9272 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, /* 9280 */ 'd', 'i', 'n', 's', 'm', 32, 0, /* 9287 */ 'd', 'e', 'x', 't', 'm', 32, 0, /* 9294 */ 'c', 'i', 'n', 's', 32, 0, /* 9300 */ 'd', 'i', 'n', 's', 32, 0, /* 9306 */ 'e', 'x', 't', 's', 32, 0, /* 9312 */ 'd', 'e', 'x', 't', 32, 0, /* 9318 */ 'd', 'i', 'n', 's', 'u', 32, 0, /* 9325 */ 'd', 'e', 'x', 't', 'u', 32, 0, /* 9332 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, /* 9340 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, /* 9348 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, /* 9356 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, /* 9364 */ 'c', '.', 0, /* 9367 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, /* 9375 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 9388 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 9395 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 9405 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 9420 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, /* 9429 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, /* 9437 */ 'e', 'h', 'b', 0, /* 9441 */ 'p', 'a', 'u', 's', 'e', 0, /* 9447 */ 't', 'l', 'b', 'w', 'i', 0, /* 9453 */ 'f', 'o', 'o', 0, /* 9457 */ 't', 'l', 'b', 'p', 0, /* 9462 */ 's', 's', 'n', 'o', 'p', 0, /* 9468 */ 't', 'l', 'b', 'r', 0, /* 9473 */ 't', 'l', 'b', 'w', 'r', 0, /* 9479 */ 'd', 'e', 'r', 'e', 't', 0, /* 9485 */ 'w', 'a', 'i', 't', 0, }; #endif // Emit the opcode for the instruction. uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; uint64_t Bits = (Bits2 << 32) | Bits1; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 16383)-1); #endif // Fragment 0 encoded into 4 bits for 11 unique commands. //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15); switch ((Bits >> 14) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN... return; break; case 1: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... printOperand(MI, 0, O); break; case 2: // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,... printOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 3: // AND16_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, OR16_MM, XOR16_MM printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 4: // BREAK16_MM, SDBBP16_MM printUnsignedImm8(MI, 0, O); return; break; case 5: // CACHE, CACHE_MM, CACHE_R6, PREF, PREF_MM, PREF_R6 printUnsignedImm(MI, 2, O); SStream_concat0(O, ", "); printMemOperand(MI, 0, O); return; break; case 6: // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM printFCCOperand(MI, 2, O); break; case 7: // LWM16_MM, LWM32_MM, LWM_MM, MOVEP_MM, SWM16_MM, SWM32_MM, SWM_MM printRegisterList(MI, 0, O); SStream_concat0(O, ", "); break; case 8: // LWP_MM, SWP_MM printRegisterPair(MI, 0, O); SStream_concat0(O, ", "); printMemOperand(MI, 2, O); return; break; case 9: // SYNCI printMemOperand(MI, 0, O); return; break; case 10: // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... printOperand(MI, 3, O); break; } // Fragment 1 encoded into 5 bits for 17 unique commands. //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31); switch ((Bits >> 18) & 31) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... SStream_concat0(O, ", "); break; case 1: // ADDIUS5_MM, DAHI, DATI, MOVEP_MM, MultRxRyRz16, MultuRxRyRz16, SltCCRx... printOperand(MI, 2, O); break; case 2: // ADDIUSP_MM, AddiuSpImmX16, B16_MM, BAL, BALC, BC, BPOSGE32, B_MM_Pseud... return; break; case 3: // AND16_MM, OR16_MM, XOR16_MM printOperand(MI, 1, O); return; break; case 4: // AddiuRxPcImmX16 SStream_concat0(O, ", $pc, "); printOperand(MI, 1, O); return; break; case 5: // AddiuSpImm16, Bimm16 SStream_concat0(O, " # 16 bit inst"); return; break; case 6: // Bteqz16, Btnez16 SStream_concat0(O, " # 16 bit inst"); return; break; case 7: // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M... printOperand(MI, 0, O); return; break; case 8: // FCMP_D32, FCMP_D32_MM, FCMP_D64 SStream_concat0(O, ".d\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 9: // FCMP_S32, FCMP_S32_MM SStream_concat0(O, ".s\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 10: // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... SStream_concat0(O, "["); break; case 11: // Jal16 SStream_concat0(O, "\n\tnop"); return; break; case 12: // JalB16 SStream_concat0(O, "\t# branch\n\tnop"); return; break; case 13: // LWM16_MM, LWM32_MM, LWM_MM, SWM16_MM, SWM32_MM, SWM_MM printMemOperand(MI, 1, O); return; break; case 14: // LwConstant32 SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); printOperand(MI, 1, O); SStream_concat0(O, "\n2:"); return; break; case 15: // SC, SCD, SCD_R6, SC_MM, SC_R6 printMemOperand(MI, 2, O); return; break; case 16: // SelBeqZ, SelBneZ SStream_concat0(O, ", .+4\n\t\n\tmove "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; } // Fragment 2 encoded into 4 bits for 12 unique commands. //printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15); switch ((Bits >> 23) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM... printOperand(MI, 1, O); break; case 1: // ADDIUS5_MM, DAHI, DATI return; break; case 2: // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... printOperand(MI, 2, O); break; case 3: // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM printMemOperandEA(MI, 1, O); return; break; case 4: // BBIT0, BBIT032, BBIT1, BBIT132, LUi, LUi64, LUi_MM, LoadAddr32Imm, Loa... printUnsignedImm(MI, 1, O); break; case 5: // INSERT_B, INSERT_D, INSERT_H, INSERT_W printUnsignedImm(MI, 3, O); SStream_concat0(O, "], "); printOperand(MI, 2, O); return; break; case 6: // INSVE_B, INSVE_D, INSVE_H, INSVE_W printUnsignedImm(MI, 2, O); SStream_concat0(O, "], "); printOperand(MI, 3, O); SStream_concat0(O, "["); printUnsignedImm(MI, 4, O); SStream_concat0(O, "]"); return; break; case 7: // LB, LB64, LBU16_MM, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_... printMemOperand(MI, 1, O); return; break; case 8: // MOVEP_MM SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 9: // MultRxRyRz16, MultuRxRyRz16 SStream_concat0(O, "\n\tmflo\t"); printOperand(MI, 0, O); return; break; case 10: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... printOperand(MI, 4, O); break; case 11: // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... SStream_concat0(O, "\n\tmove\t"); printOperand(MI, 0, O); SStream_concat0(O, ", $t8"); return; break; } // Fragment 3 encoded into 4 bits for 15 unique commands. //printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15); switch ((Bits >> 27) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU... return; break; case 1: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... SStream_concat0(O, ", "); break; case 2: // AddiuRxRxImm16, LwRxPcTcp16 SStream_concat0(O, "\t# 16 bit inst"); return; break; case 3: // BeqzRxImm16, BnezRxImm16 SStream_concat0(O, " # 16 bit inst"); return; break; case 4: // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... SStream_concat0(O, "\n\tbteqz\t"); printOperand(MI, 2, O); return; break; case 5: // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... SStream_concat0(O, "\n\tbtnez\t"); printOperand(MI, 2, O); return; break; case 6: // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... SStream_concat0(O, "["); break; case 7: // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 SStream_concat0(O, " \t# 16 bit inst"); return; break; case 8: // DSLL64_32 SStream_concat0(O, ", 32"); return; break; case 9: // GotPrologue16 SStream_concat0(O, "\n\taddiu\t"); printOperand(MI, 1, O); SStream_concat0(O, ", $pc, "); printOperand(MI, 3, O); SStream_concat0(O, "\n "); return; break; case 10: // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... SStream_concat0(O, "("); printOperand(MI, 1, O); SStream_concat0(O, ")"); return; break; case 11: // LwRxSpImmX16, SwRxSpImmX16 SStream_concat0(O, " ( "); printOperand(MI, 1, O); SStream_concat0(O, " ); "); return; break; case 12: // SLL64_32, SLL64_64 SStream_concat0(O, ", 0"); return; break; case 13: // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 14: // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; } // Fragment 4 encoded into 3 bits for 5 unique commands. //printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7); switch ((Bits >> 31) & 7) { default: // llvm_unreachable("Invalid command number."); case 0: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... printOperand(MI, 2, O); break; case 1: // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... printUnsignedImm8(MI, 2, O); break; case 2: // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... printUnsignedImm(MI, 2, O); break; case 3: // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... printUnsignedImm8(MI, 3, O); break; case 4: // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... printOperand(MI, 3, O); break; } // Fragment 5 encoded into 2 bits for 3 unique commands. //printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3); switch ((Bits >> 34) & 3) { default: // llvm_unreachable("Invalid command number."); case 0: // ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD... return; break; case 1: // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... SStream_concat0(O, ", "); break; case 2: // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... SStream_concat0(O, "]"); return; break; } // Fragment 6 encoded into 1 bits for 2 unique commands. //printf("Frag-6: %"PRIu64"\n", (Bits >> 36) & 1); if ((Bits >> 36) & 1) { // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... printOperand(MI, 3, O); return; } else { // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 printUnsignedImm(MI, 3, O); return; } } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 394 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'f', '1', '0', 0, /* 4 */ 'w', '1', '0', 0, /* 8 */ 'f', '2', '0', 0, /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, /* 25 */ 'w', '2', '0', 0, /* 29 */ 'f', '3', '0', 0, /* 33 */ 'w', '3', '0', 0, /* 37 */ 'a', '0', 0, /* 40 */ 'a', 'c', '0', 0, /* 44 */ 'f', 'c', 'c', '0', 0, /* 49 */ 'f', '0', 0, /* 52 */ 'k', '0', 0, /* 55 */ 'm', 'p', 'l', '0', 0, /* 60 */ 'p', '0', 0, /* 63 */ 's', '0', 0, /* 66 */ 't', '0', 0, /* 69 */ 'v', '0', 0, /* 72 */ 'w', '0', 0, /* 75 */ 'f', '1', '1', 0, /* 79 */ 'w', '1', '1', 0, /* 83 */ 'f', '2', '1', 0, /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, /* 100 */ 'w', '2', '1', 0, /* 104 */ 'f', '3', '1', 0, /* 108 */ 'w', '3', '1', 0, /* 112 */ 'a', '1', 0, /* 115 */ 'a', 'c', '1', 0, /* 119 */ 'f', 'c', 'c', '1', 0, /* 124 */ 'f', '1', 0, /* 127 */ 'k', '1', 0, /* 130 */ 'm', 'p', 'l', '1', 0, /* 135 */ 'p', '1', 0, /* 138 */ 's', '1', 0, /* 141 */ 't', '1', 0, /* 144 */ 'v', '1', 0, /* 147 */ 'w', '1', 0, /* 150 */ 'f', '1', '2', 0, /* 154 */ 'w', '1', '2', 0, /* 158 */ 'f', '2', '2', 0, /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, /* 175 */ 'w', '2', '2', 0, /* 179 */ 'a', '2', 0, /* 182 */ 'a', 'c', '2', 0, /* 186 */ 'f', 'c', 'c', '2', 0, /* 191 */ 'f', '2', 0, /* 194 */ 'm', 'p', 'l', '2', 0, /* 199 */ 'p', '2', 0, /* 202 */ 's', '2', 0, /* 205 */ 't', '2', 0, /* 208 */ 'w', '2', 0, /* 211 */ 'f', '1', '3', 0, /* 215 */ 'w', '1', '3', 0, /* 219 */ 'f', '2', '3', 0, /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, /* 236 */ 'w', '2', '3', 0, /* 240 */ 'a', '3', 0, /* 243 */ 'a', 'c', '3', 0, /* 247 */ 'f', 'c', 'c', '3', 0, /* 252 */ 'f', '3', 0, /* 255 */ 's', '3', 0, /* 258 */ 't', '3', 0, /* 261 */ 'w', '3', 0, /* 264 */ 'f', '1', '4', 0, /* 268 */ 'w', '1', '4', 0, /* 272 */ 'f', '2', '4', 0, /* 276 */ 'w', '2', '4', 0, /* 280 */ 'f', 'c', 'c', '4', 0, /* 285 */ 'f', '4', 0, /* 288 */ 's', '4', 0, /* 291 */ 't', '4', 0, /* 294 */ 'w', '4', 0, /* 297 */ 'f', '1', '5', 0, /* 301 */ 'w', '1', '5', 0, /* 305 */ 'f', '2', '5', 0, /* 309 */ 'w', '2', '5', 0, /* 313 */ 'f', 'c', 'c', '5', 0, /* 318 */ 'f', '5', 0, /* 321 */ 's', '5', 0, /* 324 */ 't', '5', 0, /* 327 */ 'w', '5', 0, /* 330 */ 'f', '1', '6', 0, /* 334 */ 'w', '1', '6', 0, /* 338 */ 'f', '2', '6', 0, /* 342 */ 'w', '2', '6', 0, /* 346 */ 'f', 'c', 'c', '6', 0, /* 351 */ 'f', '6', 0, /* 354 */ 's', '6', 0, /* 357 */ 't', '6', 0, /* 360 */ 'w', '6', 0, /* 363 */ 'f', '1', '7', 0, /* 367 */ 'w', '1', '7', 0, /* 371 */ 'f', '2', '7', 0, /* 375 */ 'w', '2', '7', 0, /* 379 */ 'f', 'c', 'c', '7', 0, /* 384 */ 'f', '7', 0, /* 387 */ 's', '7', 0, /* 390 */ 't', '7', 0, /* 393 */ 'w', '7', 0, /* 396 */ 'f', '1', '8', 0, /* 400 */ 'w', '1', '8', 0, /* 404 */ 'f', '2', '8', 0, /* 408 */ 'w', '2', '8', 0, /* 412 */ 'f', '8', 0, /* 415 */ 't', '8', 0, /* 418 */ 'w', '8', 0, /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, /* 437 */ 'f', '1', '9', 0, /* 441 */ 'w', '1', '9', 0, /* 445 */ 'f', '2', '9', 0, /* 449 */ 'w', '2', '9', 0, /* 453 */ 'f', '9', 0, /* 456 */ 't', '9', 0, /* 459 */ 'w', '9', 0, /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, /* 469 */ 'r', 'a', 0, /* 472 */ 'h', 'w', 'r', '_', 'c', 'c', 0, /* 479 */ 'p', 'c', 0, /* 482 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, /* 491 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, /* 502 */ 'h', 'i', 0, /* 505 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0, /* 516 */ 'l', 'o', 0, /* 519 */ 'z', 'e', 'r', 'o', 0, /* 524 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0, /* 539 */ 'f', 'p', 0, /* 542 */ 'g', 'p', 0, /* 545 */ 's', 'p', 0, /* 548 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0, /* 558 */ 'D', 'S', 'P', 'P', 'o', 's', 0, /* 565 */ 'a', 't', 0, /* 568 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, /* 578 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, }; static const uint16_t RegAsmOffset[] = { 565, 482, 578, 462, 491, 558, 568, 539, 542, 152, 77, 2, 332, 266, 299, 213, 365, 479, 469, 545, 519, 37, 112, 179, 240, 40, 115, 182, 243, 565, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 539, 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, 542, 40, 115, 182, 243, 505, 524, 472, 548, 266, 299, 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, 255, 288, 321, 354, 387, 545, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, 276, 309, 342, 375, 408, 449, 33, 108, 519, 37, 112, 179, 240, 40, 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, 421, 502, 52, 127, 516, 63, 138, 202, 255, 288, 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, 144, }; //printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]); //int i; //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); //printf("-------------------------\n"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS) { } static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) { #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) const char *AsmString; char *tmp, *AsmMnem, *AsmOps, *c; int OpIdx, PrintMethodIdx; MCRegisterInfo *MRI = (MCRegisterInfo *)info; switch (MCInst_getOpcode(MI)) { default: return NULL; case Mips_ADDu: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) { // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) AsmString = "move $\x01, $\x02"; break; } return NULL; case Mips_BC0F: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC0F CC0, brtarget:$offset) AsmString = "bc0f $\x02"; break; } return NULL; case Mips_BC0FL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC0FL CC0, brtarget:$offset) AsmString = "bc0fl $\x02"; break; } return NULL; case Mips_BC0T: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC0T CC0, brtarget:$offset) AsmString = "bc0t $\x02"; break; } return NULL; case Mips_BC0TL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC0TL CC0, brtarget:$offset) AsmString = "bc0tl $\x02"; break; } return NULL; case Mips_BC1F: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { // (BC1F FCC0, brtarget:$offset) AsmString = "bc1f $\x02"; break; } return NULL; case Mips_BC1FL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { // (BC1FL FCC0, brtarget:$offset) AsmString = "bc1fl $\x02"; break; } return NULL; case Mips_BC1T: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { // (BC1T FCC0, brtarget:$offset) AsmString = "bc1t $\x02"; break; } return NULL; case Mips_BC1TL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { // (BC1TL FCC0, brtarget:$offset) AsmString = "bc1tl $\x02"; break; } return NULL; case Mips_BC2F: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC2F CC0, brtarget:$offset) AsmString = "bc2f $\x02"; break; } return NULL; case Mips_BC2FL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC2FL CC0, brtarget:$offset) AsmString = "bc2fl $\x02"; break; } return NULL; case Mips_BC2T: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC2T CC0, brtarget:$offset) AsmString = "bc2t $\x02"; break; } return NULL; case Mips_BC2TL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC2TL CC0, brtarget:$offset) AsmString = "bc2tl $\x02"; break; } return NULL; case Mips_BC3F: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC3F CC0, brtarget:$offset) AsmString = "bc3f $\x02"; break; } return NULL; case Mips_BC3FL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC3FL CC0, brtarget:$offset) AsmString = "bc3fl $\x02"; break; } return NULL; case Mips_BC3T: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC3T CC0, brtarget:$offset) AsmString = "bc3t $\x02"; break; } return NULL; case Mips_BC3TL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { // (BC3TL CC0, brtarget:$offset) AsmString = "bc3tl $\x02"; break; } return NULL; case Mips_BREAK: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BREAK 0, 0) AsmString = "break"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BREAK uimm10:$imm, 0) AsmString = "break $\x01"; break; } return NULL; case Mips_DADDu: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) { // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) AsmString = "move $\x01, $\x02"; break; } return NULL; case Mips_DI: if (MCInst_getNumOperands(MI) == 1 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { // (DI ZERO) AsmString = "di"; break; } return NULL; case Mips_EI: if (MCInst_getNumOperands(MI) == 1 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { // (EI ZERO) AsmString = "ei"; break; } return NULL; case Mips_JALR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { // (JALR ZERO, GPR32Opnd:$rs) AsmString = "jr $\x02"; break; } return NULL; case Mips_JALR64: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) { // (JALR64 ZERO_64, GPR64Opnd:$rs) AsmString = "jr $\x02"; break; } return NULL; case Mips_JALR_HB: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { // (JALR_HB RA, GPR32Opnd:$rs) AsmString = "jalr.hb $\x02"; break; } return NULL; case Mips_MOVE16_MM: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO) { // (MOVE16_MM ZERO, ZERO) AsmString = "nop"; break; } return NULL; case Mips_SDBBP: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (SDBBP 0) AsmString = "sdbbp"; break; } return NULL; case Mips_SDBBP_R6: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (SDBBP_R6 0) AsmString = "sdbbp"; break; } return NULL; case Mips_SLL: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (SLL ZERO, ZERO, 0) AsmString = "nop"; break; } return NULL; case Mips_SLL_MM: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (SLL_MM ZERO, ZERO, 0) AsmString = "nop"; break; } return NULL; case Mips_SUB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) AsmString = "neg $\x01, $\x03"; break; } return NULL; case Mips_SUBu: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) AsmString = "negu $\x01, $\x03"; break; } return NULL; case Mips_SYNC: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (SYNC 0) AsmString = "sync"; break; } return NULL; case Mips_SYSCALL: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (SYSCALL 0) AsmString = "syscall"; break; } return NULL; case Mips_TEQ: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) AsmString = "teq $\x01, $\x02"; break; } return NULL; case Mips_TGE: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) AsmString = "tge $\x01, $\x02"; break; } return NULL; case Mips_TGEU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) AsmString = "tgeu $\x01, $\x02"; break; } return NULL; case Mips_TLT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) AsmString = "tlt $\x01, $\x02"; break; } return NULL; case Mips_TLTU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) AsmString = "tltu $\x01, $\x02"; break; } return NULL; case Mips_TNE: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) AsmString = "tne $\x01, $\x02"; break; } return NULL; case Mips_WAIT_MM: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (WAIT_MM 0) AsmString = "wait"; break; } return NULL; } tmp = cs_strdup(AsmString); AsmMnem = tmp; for(AsmOps = tmp; *AsmOps; AsmOps++) { if (*AsmOps == ' ' || *AsmOps == '\t') { *AsmOps = '\0'; AsmOps++; break; } } SStream_concat0(OS, AsmMnem); if (*AsmOps) { SStream_concat0(OS, "\t"); for (c = AsmOps; *c; c++) { if (*c == '$') { c += 1; if (*c == (char)0xff) { c += 1; OpIdx = *c - 1; c += 1; PrintMethodIdx = *c - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, *c - 1, OS); } else { SStream_concat(OS, "%c", *c); } } } return tmp; } #endif // PRINT_ALIAS_INSTR capstone-sys-0.15.0/capstone/arch/Mips/MipsGenDisassemblerTables.inc000064400000000000000000014727600072674642500235770ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * Mips Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTableCOP3_32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 /* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 /* 11 */ MCD_OPC_Decode, 220, 7, 10, // Opcode: LWC3 /* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 /* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 /* 23 */ MCD_OPC_Decode, 167, 7, 10, // Opcode: LDC3 /* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 /* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 /* 35 */ MCD_OPC_Decode, 242, 12, 10, // Opcode: SWC3 /* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 /* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 /* 47 */ MCD_OPC_Decode, 161, 11, 10, // Opcode: SDC3 /* 51 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMicroMips16[] = { /* 0 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 3 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 33 /* 7 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 10 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 21 /* 14 */ MCD_OPC_CheckPredicate, 3, 19, 2, // Skip to: 549 /* 18 */ MCD_OPC_Decode, 52, 11, // Opcode: ADDU16_MM /* 21 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 549 /* 25 */ MCD_OPC_CheckPredicate, 3, 8, 2, // Skip to: 549 /* 29 */ MCD_OPC_Decode, 214, 12, 11, // Opcode: SUBU16_MM /* 33 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 45 /* 37 */ MCD_OPC_CheckPredicate, 3, 252, 1, // Skip to: 549 /* 41 */ MCD_OPC_Decode, 155, 7, 12, // Opcode: LBU16_MM /* 45 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 57 /* 49 */ MCD_OPC_CheckPredicate, 3, 240, 1, // Skip to: 549 /* 53 */ MCD_OPC_Decode, 233, 8, 13, // Opcode: MOVE16_MM /* 57 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 88 /* 61 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 64 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 76 /* 68 */ MCD_OPC_CheckPredicate, 3, 221, 1, // Skip to: 549 /* 72 */ MCD_OPC_Decode, 226, 11, 14, // Opcode: SLL16_MM /* 76 */ MCD_OPC_FilterValue, 1, 213, 1, // Skip to: 549 /* 80 */ MCD_OPC_CheckPredicate, 3, 209, 1, // Skip to: 549 /* 84 */ MCD_OPC_Decode, 160, 12, 14, // Opcode: SRL16_MM /* 88 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 100 /* 92 */ MCD_OPC_CheckPredicate, 3, 197, 1, // Skip to: 549 /* 96 */ MCD_OPC_Decode, 186, 7, 12, // Opcode: LHU16_MM /* 100 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 111 /* 104 */ MCD_OPC_CheckPredicate, 3, 185, 1, // Skip to: 549 /* 108 */ MCD_OPC_Decode, 86, 15, // Opcode: ANDI16_MM /* 111 */ MCD_OPC_FilterValue, 17, 226, 0, // Skip to: 341 /* 115 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 /* 122 */ MCD_OPC_CheckPredicate, 3, 167, 1, // Skip to: 549 /* 126 */ MCD_OPC_Decode, 130, 10, 16, // Opcode: NOT16_MM /* 130 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 142 /* 134 */ MCD_OPC_CheckPredicate, 3, 155, 1, // Skip to: 549 /* 138 */ MCD_OPC_Decode, 237, 13, 17, // Opcode: XOR16_MM /* 142 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 153 /* 146 */ MCD_OPC_CheckPredicate, 3, 143, 1, // Skip to: 549 /* 150 */ MCD_OPC_Decode, 84, 17, // Opcode: AND16_MM /* 153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 165 /* 157 */ MCD_OPC_CheckPredicate, 3, 132, 1, // Skip to: 549 /* 161 */ MCD_OPC_Decode, 134, 10, 17, // Opcode: OR16_MM /* 165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 177 /* 169 */ MCD_OPC_CheckPredicate, 3, 120, 1, // Skip to: 549 /* 173 */ MCD_OPC_Decode, 225, 7, 18, // Opcode: LWM16_MM /* 177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 189 /* 181 */ MCD_OPC_CheckPredicate, 3, 108, 1, // Skip to: 549 /* 185 */ MCD_OPC_Decode, 246, 12, 18, // Opcode: SWM16_MM /* 189 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 220 /* 193 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 208 /* 200 */ MCD_OPC_CheckPredicate, 3, 89, 1, // Skip to: 549 /* 204 */ MCD_OPC_Decode, 137, 7, 19, // Opcode: JR16_MM /* 208 */ MCD_OPC_FilterValue, 1, 81, 1, // Skip to: 549 /* 212 */ MCD_OPC_CheckPredicate, 3, 77, 1, // Skip to: 549 /* 216 */ MCD_OPC_Decode, 140, 7, 19, // Opcode: JRC16_MM /* 220 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 251 /* 224 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... /* 227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 239 /* 231 */ MCD_OPC_CheckPredicate, 3, 58, 1, // Skip to: 549 /* 235 */ MCD_OPC_Decode, 250, 6, 19, // Opcode: JALR16_MM /* 239 */ MCD_OPC_FilterValue, 1, 50, 1, // Skip to: 549 /* 243 */ MCD_OPC_CheckPredicate, 3, 46, 1, // Skip to: 549 /* 247 */ MCD_OPC_Decode, 254, 6, 19, // Opcode: JALRS16_MM /* 251 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 269 /* 255 */ MCD_OPC_CheckPredicate, 3, 34, 1, // Skip to: 549 /* 259 */ MCD_OPC_CheckField, 5, 1, 0, 28, 1, // Skip to: 549 /* 265 */ MCD_OPC_Decode, 187, 8, 19, // Opcode: MFHI16_MM /* 269 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 287 /* 273 */ MCD_OPC_CheckPredicate, 3, 16, 1, // Skip to: 549 /* 277 */ MCD_OPC_CheckField, 5, 1, 0, 10, 1, // Skip to: 549 /* 283 */ MCD_OPC_Decode, 192, 8, 19, // Opcode: MFLO16_MM /* 287 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 305 /* 291 */ MCD_OPC_CheckPredicate, 3, 254, 0, // Skip to: 549 /* 295 */ MCD_OPC_CheckField, 4, 2, 0, 248, 0, // Skip to: 549 /* 301 */ MCD_OPC_Decode, 172, 2, 20, // Opcode: BREAK16_MM /* 305 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 323 /* 309 */ MCD_OPC_CheckPredicate, 3, 236, 0, // Skip to: 549 /* 313 */ MCD_OPC_CheckField, 4, 2, 0, 230, 0, // Skip to: 549 /* 319 */ MCD_OPC_Decode, 153, 11, 20, // Opcode: SDBBP16_MM /* 323 */ MCD_OPC_FilterValue, 12, 222, 0, // Skip to: 549 /* 327 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 549 /* 331 */ MCD_OPC_CheckField, 5, 1, 0, 212, 0, // Skip to: 549 /* 337 */ MCD_OPC_Decode, 139, 7, 21, // Opcode: JRADDIUSP /* 341 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 353 /* 345 */ MCD_OPC_CheckPredicate, 3, 200, 0, // Skip to: 549 /* 349 */ MCD_OPC_Decode, 233, 7, 22, // Opcode: LWSP_MM /* 353 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 382 /* 357 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 360 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 371 /* 364 */ MCD_OPC_CheckPredicate, 3, 181, 0, // Skip to: 549 /* 368 */ MCD_OPC_Decode, 30, 23, // Opcode: ADDIUS5_MM /* 371 */ MCD_OPC_FilterValue, 1, 174, 0, // Skip to: 549 /* 375 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 549 /* 379 */ MCD_OPC_Decode, 31, 24, // Opcode: ADDIUSP_MM /* 382 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 394 /* 386 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 549 /* 390 */ MCD_OPC_Decode, 221, 7, 25, // Opcode: LWGP_MM /* 394 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 406 /* 398 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 549 /* 402 */ MCD_OPC_Decode, 214, 7, 12, // Opcode: LW16_MM /* 406 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 435 /* 410 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 413 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 424 /* 417 */ MCD_OPC_CheckPredicate, 3, 128, 0, // Skip to: 549 /* 421 */ MCD_OPC_Decode, 29, 26, // Opcode: ADDIUR2_MM /* 424 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 549 /* 428 */ MCD_OPC_CheckPredicate, 3, 117, 0, // Skip to: 549 /* 432 */ MCD_OPC_Decode, 28, 27, // Opcode: ADDIUR1SP_MM /* 435 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 453 /* 439 */ MCD_OPC_CheckPredicate, 3, 106, 0, // Skip to: 549 /* 443 */ MCD_OPC_CheckField, 0, 1, 0, 100, 0, // Skip to: 549 /* 449 */ MCD_OPC_Decode, 234, 8, 28, // Opcode: MOVEP_MM /* 453 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 465 /* 457 */ MCD_OPC_CheckPredicate, 3, 88, 0, // Skip to: 549 /* 461 */ MCD_OPC_Decode, 143, 11, 12, // Opcode: SB16_MM /* 465 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 477 /* 469 */ MCD_OPC_CheckPredicate, 3, 76, 0, // Skip to: 549 /* 473 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BEQZ16_MM /* 477 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 489 /* 481 */ MCD_OPC_CheckPredicate, 3, 64, 0, // Skip to: 549 /* 485 */ MCD_OPC_Decode, 187, 11, 12, // Opcode: SH16_MM /* 489 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 501 /* 493 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 549 /* 497 */ MCD_OPC_Decode, 157, 2, 29, // Opcode: BNEZ16_MM /* 501 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 513 /* 505 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 549 /* 509 */ MCD_OPC_Decode, 253, 12, 22, // Opcode: SWSP_MM /* 513 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 525 /* 517 */ MCD_OPC_CheckPredicate, 4, 28, 0, // Skip to: 549 /* 521 */ MCD_OPC_Decode, 165, 1, 30, // Opcode: B16_MM /* 525 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 537 /* 529 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 549 /* 533 */ MCD_OPC_Decode, 236, 12, 12, // Opcode: SW16_MM /* 537 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 549 /* 541 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 549 /* 545 */ MCD_OPC_Decode, 192, 7, 31, // Opcode: LI16_MM /* 549 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMicroMips32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 0, 189, 3, // Skip to: 964 /* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 10 */ MCD_OPC_FilterValue, 0, 90, 0, // Skip to: 104 /* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 17 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 68 /* 21 */ MCD_OPC_ExtractField, 11, 15, // Inst{25-11} ... /* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 /* 28 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 60 /* 32 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: SSNOP_MM /* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 /* 40 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 60 /* 44 */ MCD_OPC_Decode, 140, 5, 0, // Opcode: EHB_MM /* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 /* 52 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 60 /* 56 */ MCD_OPC_Decode, 148, 10, 0, // Opcode: PAUSE_MM /* 60 */ MCD_OPC_CheckPredicate, 3, 38, 6, // Skip to: 1638 /* 64 */ MCD_OPC_Decode, 238, 11, 32, // Opcode: SLL_MM /* 68 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 80 /* 72 */ MCD_OPC_CheckPredicate, 3, 26, 6, // Skip to: 1638 /* 76 */ MCD_OPC_Decode, 178, 12, 32, // Opcode: SRL_MM /* 80 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 92 /* 84 */ MCD_OPC_CheckPredicate, 3, 14, 6, // Skip to: 1638 /* 88 */ MCD_OPC_Decode, 157, 12, 32, // Opcode: SRA_MM /* 92 */ MCD_OPC_FilterValue, 3, 6, 6, // Skip to: 1638 /* 96 */ MCD_OPC_CheckPredicate, 3, 2, 6, // Skip to: 1638 /* 100 */ MCD_OPC_Decode, 250, 10, 32, // Opcode: ROTR_MM /* 104 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 116 /* 108 */ MCD_OPC_CheckPredicate, 3, 246, 5, // Skip to: 1638 /* 112 */ MCD_OPC_Decode, 173, 2, 33, // Opcode: BREAK_MM /* 116 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 128 /* 120 */ MCD_OPC_CheckPredicate, 3, 234, 5, // Skip to: 1638 /* 124 */ MCD_OPC_Decode, 246, 6, 34, // Opcode: INS_MM /* 128 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 312 /* 132 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 135 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 147 /* 139 */ MCD_OPC_CheckPredicate, 3, 215, 5, // Skip to: 1638 /* 143 */ MCD_OPC_Decode, 234, 11, 35, // Opcode: SLLV_MM /* 147 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 159 /* 151 */ MCD_OPC_CheckPredicate, 3, 203, 5, // Skip to: 1638 /* 155 */ MCD_OPC_Decode, 174, 12, 35, // Opcode: SRLV_MM /* 159 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 171 /* 163 */ MCD_OPC_CheckPredicate, 3, 191, 5, // Skip to: 1638 /* 167 */ MCD_OPC_Decode, 153, 12, 35, // Opcode: SRAV_MM /* 171 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 183 /* 175 */ MCD_OPC_CheckPredicate, 3, 179, 5, // Skip to: 1638 /* 179 */ MCD_OPC_Decode, 249, 10, 35, // Opcode: ROTRV_MM /* 183 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 194 /* 187 */ MCD_OPC_CheckPredicate, 3, 167, 5, // Skip to: 1638 /* 191 */ MCD_OPC_Decode, 72, 36, // Opcode: ADD_MM /* 194 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 205 /* 198 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1638 /* 202 */ MCD_OPC_Decode, 78, 36, // Opcode: ADDu_MM /* 205 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 217 /* 209 */ MCD_OPC_CheckPredicate, 3, 145, 5, // Skip to: 1638 /* 213 */ MCD_OPC_Decode, 229, 12, 36, // Opcode: SUB_MM /* 217 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 229 /* 221 */ MCD_OPC_CheckPredicate, 3, 133, 5, // Skip to: 1638 /* 225 */ MCD_OPC_Decode, 231, 12, 36, // Opcode: SUBu_MM /* 229 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 241 /* 233 */ MCD_OPC_CheckPredicate, 3, 121, 5, // Skip to: 1638 /* 237 */ MCD_OPC_Decode, 217, 9, 36, // Opcode: MUL_MM /* 241 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 252 /* 245 */ MCD_OPC_CheckPredicate, 3, 109, 5, // Skip to: 1638 /* 249 */ MCD_OPC_Decode, 88, 36, // Opcode: AND_MM /* 252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 264 /* 256 */ MCD_OPC_CheckPredicate, 3, 98, 5, // Skip to: 1638 /* 260 */ MCD_OPC_Decode, 137, 10, 36, // Opcode: OR_MM /* 264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 276 /* 268 */ MCD_OPC_CheckPredicate, 3, 86, 5, // Skip to: 1638 /* 272 */ MCD_OPC_Decode, 253, 9, 36, // Opcode: NOR_MM /* 276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 288 /* 280 */ MCD_OPC_CheckPredicate, 3, 74, 5, // Skip to: 1638 /* 284 */ MCD_OPC_Decode, 240, 13, 36, // Opcode: XOR_MM /* 288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 300 /* 292 */ MCD_OPC_CheckPredicate, 3, 62, 5, // Skip to: 1638 /* 296 */ MCD_OPC_Decode, 242, 11, 36, // Opcode: SLT_MM /* 300 */ MCD_OPC_FilterValue, 14, 54, 5, // Skip to: 1638 /* 304 */ MCD_OPC_CheckPredicate, 3, 50, 5, // Skip to: 1638 /* 308 */ MCD_OPC_Decode, 251, 11, 36, // Opcode: SLTu_MM /* 312 */ MCD_OPC_FilterValue, 24, 39, 0, // Skip to: 355 /* 316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 319 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 331 /* 323 */ MCD_OPC_CheckPredicate, 3, 31, 5, // Skip to: 1638 /* 327 */ MCD_OPC_Decode, 253, 8, 37, // Opcode: MOVN_I_MM /* 331 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 343 /* 335 */ MCD_OPC_CheckPredicate, 3, 19, 5, // Skip to: 1638 /* 339 */ MCD_OPC_Decode, 145, 9, 37, // Opcode: MOVZ_I_MM /* 343 */ MCD_OPC_FilterValue, 4, 11, 5, // Skip to: 1638 /* 347 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1638 /* 351 */ MCD_OPC_Decode, 239, 7, 38, // Opcode: LWXS_MM /* 355 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 367 /* 359 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1638 /* 363 */ MCD_OPC_Decode, 160, 5, 39, // Opcode: EXT_MM /* 367 */ MCD_OPC_FilterValue, 60, 243, 4, // Skip to: 1638 /* 371 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... /* 374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 386 /* 378 */ MCD_OPC_CheckPredicate, 3, 232, 4, // Skip to: 1638 /* 382 */ MCD_OPC_Decode, 185, 13, 40, // Opcode: TEQ_MM /* 386 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 398 /* 390 */ MCD_OPC_CheckPredicate, 3, 220, 4, // Skip to: 1638 /* 394 */ MCD_OPC_Decode, 193, 13, 40, // Opcode: TGE_MM /* 398 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 525 /* 402 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 405 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 423 /* 409 */ MCD_OPC_CheckPredicate, 3, 201, 4, // Skip to: 1638 /* 413 */ MCD_OPC_CheckField, 16, 10, 0, 195, 4, // Skip to: 1638 /* 419 */ MCD_OPC_Decode, 195, 13, 0, // Opcode: TLBP_MM /* 423 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 441 /* 427 */ MCD_OPC_CheckPredicate, 3, 183, 4, // Skip to: 1638 /* 431 */ MCD_OPC_CheckField, 16, 10, 0, 177, 4, // Skip to: 1638 /* 437 */ MCD_OPC_Decode, 197, 13, 0, // Opcode: TLBR_MM /* 441 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 459 /* 445 */ MCD_OPC_CheckPredicate, 3, 165, 4, // Skip to: 1638 /* 449 */ MCD_OPC_CheckField, 16, 10, 0, 159, 4, // Skip to: 1638 /* 455 */ MCD_OPC_Decode, 199, 13, 0, // Opcode: TLBWI_MM /* 459 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 477 /* 463 */ MCD_OPC_CheckPredicate, 3, 147, 4, // Skip to: 1638 /* 467 */ MCD_OPC_CheckField, 16, 10, 0, 141, 4, // Skip to: 1638 /* 473 */ MCD_OPC_Decode, 201, 13, 0, // Opcode: TLBWR_MM /* 477 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 489 /* 481 */ MCD_OPC_CheckPredicate, 3, 129, 4, // Skip to: 1638 /* 485 */ MCD_OPC_Decode, 232, 13, 41, // Opcode: WAIT_MM /* 489 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 507 /* 493 */ MCD_OPC_CheckPredicate, 3, 117, 4, // Skip to: 1638 /* 497 */ MCD_OPC_CheckField, 16, 10, 0, 111, 4, // Skip to: 1638 /* 503 */ MCD_OPC_Decode, 175, 4, 0, // Opcode: DERET_MM /* 507 */ MCD_OPC_FilterValue, 15, 103, 4, // Skip to: 1638 /* 511 */ MCD_OPC_CheckPredicate, 3, 99, 4, // Skip to: 1638 /* 515 */ MCD_OPC_CheckField, 16, 10, 0, 93, 4, // Skip to: 1638 /* 521 */ MCD_OPC_Decode, 144, 5, 0, // Opcode: ERET_MM /* 525 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 537 /* 529 */ MCD_OPC_CheckPredicate, 3, 81, 4, // Skip to: 1638 /* 533 */ MCD_OPC_Decode, 192, 13, 40, // Opcode: TGEU_MM /* 537 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 580 /* 541 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 544 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 562 /* 548 */ MCD_OPC_CheckPredicate, 3, 62, 4, // Skip to: 1638 /* 552 */ MCD_OPC_CheckField, 21, 5, 0, 56, 4, // Skip to: 1638 /* 558 */ MCD_OPC_Decode, 193, 4, 42, // Opcode: DI_MM /* 562 */ MCD_OPC_FilterValue, 5, 48, 4, // Skip to: 1638 /* 566 */ MCD_OPC_CheckPredicate, 3, 44, 4, // Skip to: 1638 /* 570 */ MCD_OPC_CheckField, 21, 5, 0, 38, 4, // Skip to: 1638 /* 576 */ MCD_OPC_Decode, 142, 5, 42, // Opcode: EI_MM /* 580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 592 /* 584 */ MCD_OPC_CheckPredicate, 3, 26, 4, // Skip to: 1638 /* 588 */ MCD_OPC_Decode, 208, 13, 40, // Opcode: TLT_MM /* 592 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 604 /* 596 */ MCD_OPC_CheckPredicate, 3, 14, 4, // Skip to: 1638 /* 600 */ MCD_OPC_Decode, 207, 13, 40, // Opcode: TLTU_MM /* 604 */ MCD_OPC_FilterValue, 44, 171, 0, // Skip to: 779 /* 608 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 611 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 623 /* 615 */ MCD_OPC_CheckPredicate, 3, 251, 3, // Skip to: 1638 /* 619 */ MCD_OPC_Decode, 170, 11, 43, // Opcode: SEB_MM /* 623 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 635 /* 627 */ MCD_OPC_CheckPredicate, 3, 239, 3, // Skip to: 1638 /* 631 */ MCD_OPC_Decode, 173, 11, 43, // Opcode: SEH_MM /* 635 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 647 /* 639 */ MCD_OPC_CheckPredicate, 3, 227, 3, // Skip to: 1638 /* 643 */ MCD_OPC_Decode, 134, 3, 43, // Opcode: CLO_MM /* 647 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 659 /* 651 */ MCD_OPC_CheckPredicate, 3, 215, 3, // Skip to: 1638 /* 655 */ MCD_OPC_Decode, 153, 3, 43, // Opcode: CLZ_MM /* 659 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 671 /* 663 */ MCD_OPC_CheckPredicate, 3, 203, 3, // Skip to: 1638 /* 667 */ MCD_OPC_Decode, 240, 10, 44, // Opcode: RDHWR_MM /* 671 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 683 /* 675 */ MCD_OPC_CheckPredicate, 3, 191, 3, // Skip to: 1638 /* 679 */ MCD_OPC_Decode, 235, 13, 43, // Opcode: WSBH_MM /* 683 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 695 /* 687 */ MCD_OPC_CheckPredicate, 3, 179, 3, // Skip to: 1638 /* 691 */ MCD_OPC_Decode, 209, 9, 45, // Opcode: MULT_MM /* 695 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 707 /* 699 */ MCD_OPC_CheckPredicate, 3, 167, 3, // Skip to: 1638 /* 703 */ MCD_OPC_Decode, 211, 9, 45, // Opcode: MULTu_MM /* 707 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 719 /* 711 */ MCD_OPC_CheckPredicate, 3, 155, 3, // Skip to: 1638 /* 715 */ MCD_OPC_Decode, 163, 11, 45, // Opcode: SDIV_MM /* 719 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 731 /* 723 */ MCD_OPC_CheckPredicate, 3, 143, 3, // Skip to: 1638 /* 727 */ MCD_OPC_Decode, 223, 13, 45, // Opcode: UDIV_MM /* 731 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 743 /* 735 */ MCD_OPC_CheckPredicate, 3, 131, 3, // Skip to: 1638 /* 739 */ MCD_OPC_Decode, 146, 8, 45, // Opcode: MADD_MM /* 743 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 755 /* 747 */ MCD_OPC_CheckPredicate, 3, 119, 3, // Skip to: 1638 /* 751 */ MCD_OPC_Decode, 137, 8, 45, // Opcode: MADDU_MM /* 755 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 767 /* 759 */ MCD_OPC_CheckPredicate, 3, 107, 3, // Skip to: 1638 /* 763 */ MCD_OPC_Decode, 164, 9, 45, // Opcode: MSUB_MM /* 767 */ MCD_OPC_FilterValue, 15, 99, 3, // Skip to: 1638 /* 771 */ MCD_OPC_CheckPredicate, 3, 95, 3, // Skip to: 1638 /* 775 */ MCD_OPC_Decode, 155, 9, 45, // Opcode: MSUBU_MM /* 779 */ MCD_OPC_FilterValue, 45, 45, 0, // Skip to: 828 /* 783 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 786 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 804 /* 790 */ MCD_OPC_CheckPredicate, 3, 76, 3, // Skip to: 1638 /* 794 */ MCD_OPC_CheckField, 21, 5, 0, 70, 3, // Skip to: 1638 /* 800 */ MCD_OPC_Decode, 131, 13, 46, // Opcode: SYNC_MM /* 804 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 816 /* 808 */ MCD_OPC_CheckPredicate, 3, 58, 3, // Skip to: 1638 /* 812 */ MCD_OPC_Decode, 133, 13, 41, // Opcode: SYSCALL_MM /* 816 */ MCD_OPC_FilterValue, 13, 50, 3, // Skip to: 1638 /* 820 */ MCD_OPC_CheckPredicate, 3, 46, 3, // Skip to: 1638 /* 824 */ MCD_OPC_Decode, 154, 11, 41, // Opcode: SDBBP_MM /* 828 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 840 /* 832 */ MCD_OPC_CheckPredicate, 3, 34, 3, // Skip to: 1638 /* 836 */ MCD_OPC_Decode, 212, 13, 40, // Opcode: TNE_MM /* 840 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 919 /* 844 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 847 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 865 /* 851 */ MCD_OPC_CheckPredicate, 3, 15, 3, // Skip to: 1638 /* 855 */ MCD_OPC_CheckField, 21, 5, 0, 9, 3, // Skip to: 1638 /* 861 */ MCD_OPC_Decode, 190, 8, 42, // Opcode: MFHI_MM /* 865 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 883 /* 869 */ MCD_OPC_CheckPredicate, 3, 253, 2, // Skip to: 1638 /* 873 */ MCD_OPC_CheckField, 21, 5, 0, 247, 2, // Skip to: 1638 /* 879 */ MCD_OPC_Decode, 195, 8, 42, // Opcode: MFLO_MM /* 883 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 901 /* 887 */ MCD_OPC_CheckPredicate, 3, 235, 2, // Skip to: 1638 /* 891 */ MCD_OPC_CheckField, 21, 5, 0, 229, 2, // Skip to: 1638 /* 897 */ MCD_OPC_Decode, 179, 9, 42, // Opcode: MTHI_MM /* 901 */ MCD_OPC_FilterValue, 3, 221, 2, // Skip to: 1638 /* 905 */ MCD_OPC_CheckPredicate, 3, 217, 2, // Skip to: 1638 /* 909 */ MCD_OPC_CheckField, 21, 5, 0, 211, 2, // Skip to: 1638 /* 915 */ MCD_OPC_Decode, 184, 9, 42, // Opcode: MTLO_MM /* 919 */ MCD_OPC_FilterValue, 60, 203, 2, // Skip to: 1638 /* 923 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 926 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 952 /* 930 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 944 /* 934 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 944 /* 940 */ MCD_OPC_Decode, 143, 7, 42, // Opcode: JR_MM /* 944 */ MCD_OPC_CheckPredicate, 3, 178, 2, // Skip to: 1638 /* 948 */ MCD_OPC_Decode, 129, 7, 43, // Opcode: JALR_MM /* 952 */ MCD_OPC_FilterValue, 4, 170, 2, // Skip to: 1638 /* 956 */ MCD_OPC_CheckPredicate, 3, 166, 2, // Skip to: 1638 /* 960 */ MCD_OPC_Decode, 255, 6, 43, // Opcode: JALRS_MM /* 964 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 975 /* 968 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 1638 /* 972 */ MCD_OPC_Decode, 74, 47, // Opcode: ADDi_MM /* 975 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 987 /* 979 */ MCD_OPC_CheckPredicate, 3, 143, 2, // Skip to: 1638 /* 983 */ MCD_OPC_Decode, 160, 7, 48, // Opcode: LBu_MM /* 987 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 999 /* 991 */ MCD_OPC_CheckPredicate, 3, 131, 2, // Skip to: 1638 /* 995 */ MCD_OPC_Decode, 145, 11, 48, // Opcode: SB_MM /* 999 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1011 /* 1003 */ MCD_OPC_CheckPredicate, 3, 119, 2, // Skip to: 1638 /* 1007 */ MCD_OPC_Decode, 157, 7, 48, // Opcode: LB_MM /* 1011 */ MCD_OPC_FilterValue, 8, 63, 0, // Skip to: 1078 /* 1015 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 1018 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1030 /* 1022 */ MCD_OPC_CheckPredicate, 3, 100, 2, // Skip to: 1638 /* 1026 */ MCD_OPC_Decode, 229, 7, 49, // Opcode: LWP_MM /* 1030 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1042 /* 1034 */ MCD_OPC_CheckPredicate, 3, 88, 2, // Skip to: 1638 /* 1038 */ MCD_OPC_Decode, 226, 7, 49, // Opcode: LWM32_MM /* 1042 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1054 /* 1046 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1638 /* 1050 */ MCD_OPC_Decode, 221, 2, 50, // Opcode: CACHE_MM /* 1054 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1066 /* 1058 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1638 /* 1062 */ MCD_OPC_Decode, 249, 12, 49, // Opcode: SWP_MM /* 1066 */ MCD_OPC_FilterValue, 13, 56, 2, // Skip to: 1638 /* 1070 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1638 /* 1074 */ MCD_OPC_Decode, 247, 12, 49, // Opcode: SWM32_MM /* 1078 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1089 /* 1082 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 1638 /* 1086 */ MCD_OPC_Decode, 76, 47, // Opcode: ADDiu_MM /* 1089 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1101 /* 1093 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1638 /* 1097 */ MCD_OPC_Decode, 191, 7, 48, // Opcode: LHu_MM /* 1101 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1113 /* 1105 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1638 /* 1109 */ MCD_OPC_Decode, 216, 11, 48, // Opcode: SH_MM /* 1113 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1125 /* 1117 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1638 /* 1121 */ MCD_OPC_Decode, 188, 7, 48, // Opcode: LH_MM /* 1125 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1336 /* 1129 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 1132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1144 /* 1136 */ MCD_OPC_CheckPredicate, 3, 242, 1, // Skip to: 1638 /* 1140 */ MCD_OPC_Decode, 140, 2, 51, // Opcode: BLTZ_MM /* 1144 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1156 /* 1148 */ MCD_OPC_CheckPredicate, 3, 230, 1, // Skip to: 1638 /* 1152 */ MCD_OPC_Decode, 137, 2, 51, // Opcode: BLTZAL_MM /* 1156 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1168 /* 1160 */ MCD_OPC_CheckPredicate, 3, 218, 1, // Skip to: 1638 /* 1164 */ MCD_OPC_Decode, 226, 1, 51, // Opcode: BGEZ_MM /* 1168 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1180 /* 1172 */ MCD_OPC_CheckPredicate, 3, 206, 1, // Skip to: 1638 /* 1176 */ MCD_OPC_Decode, 223, 1, 51, // Opcode: BGEZAL_MM /* 1180 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1192 /* 1184 */ MCD_OPC_CheckPredicate, 3, 194, 1, // Skip to: 1638 /* 1188 */ MCD_OPC_Decode, 128, 2, 51, // Opcode: BLEZ_MM /* 1192 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1204 /* 1196 */ MCD_OPC_CheckPredicate, 3, 182, 1, // Skip to: 1638 /* 1200 */ MCD_OPC_Decode, 160, 2, 51, // Opcode: BNEZC_MM /* 1204 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1216 /* 1208 */ MCD_OPC_CheckPredicate, 3, 170, 1, // Skip to: 1638 /* 1212 */ MCD_OPC_Decode, 232, 1, 51, // Opcode: BGTZ_MM /* 1216 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1228 /* 1220 */ MCD_OPC_CheckPredicate, 3, 158, 1, // Skip to: 1638 /* 1224 */ MCD_OPC_Decode, 213, 1, 51, // Opcode: BEQZC_MM /* 1228 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1240 /* 1232 */ MCD_OPC_CheckPredicate, 3, 146, 1, // Skip to: 1638 /* 1236 */ MCD_OPC_Decode, 205, 13, 52, // Opcode: TLTI_MM /* 1240 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1252 /* 1244 */ MCD_OPC_CheckPredicate, 3, 134, 1, // Skip to: 1638 /* 1248 */ MCD_OPC_Decode, 190, 13, 52, // Opcode: TGEI_MM /* 1252 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1264 /* 1256 */ MCD_OPC_CheckPredicate, 3, 122, 1, // Skip to: 1638 /* 1260 */ MCD_OPC_Decode, 204, 13, 52, // Opcode: TLTIU_MM /* 1264 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1276 /* 1268 */ MCD_OPC_CheckPredicate, 3, 110, 1, // Skip to: 1638 /* 1272 */ MCD_OPC_Decode, 189, 13, 52, // Opcode: TGEIU_MM /* 1276 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1288 /* 1280 */ MCD_OPC_CheckPredicate, 3, 98, 1, // Skip to: 1638 /* 1284 */ MCD_OPC_Decode, 211, 13, 52, // Opcode: TNEI_MM /* 1288 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1300 /* 1292 */ MCD_OPC_CheckPredicate, 3, 86, 1, // Skip to: 1638 /* 1296 */ MCD_OPC_Decode, 212, 7, 52, // Opcode: LUi_MM /* 1300 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1312 /* 1304 */ MCD_OPC_CheckPredicate, 3, 74, 1, // Skip to: 1638 /* 1308 */ MCD_OPC_Decode, 184, 13, 52, // Opcode: TEQI_MM /* 1312 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1324 /* 1316 */ MCD_OPC_CheckPredicate, 3, 62, 1, // Skip to: 1638 /* 1320 */ MCD_OPC_Decode, 136, 2, 51, // Opcode: BLTZALS_MM /* 1324 */ MCD_OPC_FilterValue, 19, 54, 1, // Skip to: 1638 /* 1328 */ MCD_OPC_CheckPredicate, 3, 50, 1, // Skip to: 1638 /* 1332 */ MCD_OPC_Decode, 222, 1, 51, // Opcode: BGEZALS_MM /* 1336 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1348 /* 1340 */ MCD_OPC_CheckPredicate, 3, 38, 1, // Skip to: 1638 /* 1344 */ MCD_OPC_Decode, 144, 10, 53, // Opcode: ORi_MM /* 1348 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1381 /* 1352 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... /* 1355 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1368 /* 1360 */ MCD_OPC_CheckPredicate, 3, 18, 1, // Skip to: 1638 /* 1364 */ MCD_OPC_Decode, 241, 8, 54, // Opcode: MOVF_I_MM /* 1368 */ MCD_OPC_FilterValue, 251, 18, 9, 1, // Skip to: 1638 /* 1373 */ MCD_OPC_CheckPredicate, 3, 5, 1, // Skip to: 1638 /* 1377 */ MCD_OPC_Decode, 133, 9, 54, // Opcode: MOVT_I_MM /* 1381 */ MCD_OPC_FilterValue, 24, 99, 0, // Skip to: 1484 /* 1385 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 1388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1400 /* 1392 */ MCD_OPC_CheckPredicate, 3, 242, 0, // Skip to: 1638 /* 1396 */ MCD_OPC_Decode, 224, 7, 49, // Opcode: LWL_MM /* 1400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1412 /* 1404 */ MCD_OPC_CheckPredicate, 3, 230, 0, // Skip to: 1638 /* 1408 */ MCD_OPC_Decode, 232, 7, 49, // Opcode: LWR_MM /* 1412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1424 /* 1416 */ MCD_OPC_CheckPredicate, 3, 218, 0, // Skip to: 1638 /* 1420 */ MCD_OPC_Decode, 182, 10, 50, // Opcode: PREF_MM /* 1424 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1436 /* 1428 */ MCD_OPC_CheckPredicate, 3, 206, 0, // Skip to: 1638 /* 1432 */ MCD_OPC_Decode, 196, 7, 49, // Opcode: LL_MM /* 1436 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1448 /* 1440 */ MCD_OPC_CheckPredicate, 3, 194, 0, // Skip to: 1638 /* 1444 */ MCD_OPC_Decode, 245, 12, 49, // Opcode: SWL_MM /* 1448 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1460 /* 1452 */ MCD_OPC_CheckPredicate, 3, 182, 0, // Skip to: 1638 /* 1456 */ MCD_OPC_Decode, 252, 12, 49, // Opcode: SWR_MM /* 1460 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1472 /* 1464 */ MCD_OPC_CheckPredicate, 3, 170, 0, // Skip to: 1638 /* 1468 */ MCD_OPC_Decode, 149, 11, 49, // Opcode: SC_MM /* 1472 */ MCD_OPC_FilterValue, 14, 162, 0, // Skip to: 1638 /* 1476 */ MCD_OPC_CheckPredicate, 3, 158, 0, // Skip to: 1638 /* 1480 */ MCD_OPC_Decode, 235, 7, 49, // Opcode: LWU_MM /* 1484 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1496 /* 1488 */ MCD_OPC_CheckPredicate, 3, 146, 0, // Skip to: 1638 /* 1492 */ MCD_OPC_Decode, 247, 13, 53, // Opcode: XORi_MM /* 1496 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1508 /* 1500 */ MCD_OPC_CheckPredicate, 3, 134, 0, // Skip to: 1638 /* 1504 */ MCD_OPC_Decode, 130, 7, 55, // Opcode: JALS_MM /* 1508 */ MCD_OPC_FilterValue, 30, 7, 0, // Skip to: 1519 /* 1512 */ MCD_OPC_CheckPredicate, 3, 122, 0, // Skip to: 1638 /* 1516 */ MCD_OPC_Decode, 27, 56, // Opcode: ADDIUPC_MM /* 1519 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1531 /* 1523 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1638 /* 1527 */ MCD_OPC_Decode, 245, 11, 47, // Opcode: SLTi_MM /* 1531 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1543 /* 1535 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1638 /* 1539 */ MCD_OPC_Decode, 214, 1, 57, // Opcode: BEQ_MM /* 1543 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1555 /* 1547 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1638 /* 1551 */ MCD_OPC_Decode, 248, 11, 47, // Opcode: SLTiu_MM /* 1555 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1567 /* 1559 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1638 /* 1563 */ MCD_OPC_Decode, 161, 2, 57, // Opcode: BNE_MM /* 1567 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1578 /* 1571 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1638 /* 1575 */ MCD_OPC_Decode, 95, 53, // Opcode: ANDi_MM /* 1578 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1590 /* 1582 */ MCD_OPC_CheckPredicate, 3, 52, 0, // Skip to: 1638 /* 1586 */ MCD_OPC_Decode, 144, 7, 55, // Opcode: J_MM /* 1590 */ MCD_OPC_FilterValue, 60, 8, 0, // Skip to: 1602 /* 1594 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1638 /* 1598 */ MCD_OPC_Decode, 132, 7, 55, // Opcode: JALX_MM /* 1602 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1614 /* 1606 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1638 /* 1610 */ MCD_OPC_Decode, 133, 7, 55, // Opcode: JAL_MM /* 1614 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1626 /* 1618 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1638 /* 1622 */ MCD_OPC_Decode, 128, 13, 48, // Opcode: SW_MM /* 1626 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1638 /* 1630 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1638 /* 1634 */ MCD_OPC_Decode, 240, 7, 48, // Opcode: LW_MM /* 1638 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 /* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 /* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 17 */ MCD_OPC_FilterValue, 0, 137, 53, // Skip to: 13726 /* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... /* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 /* 28 */ MCD_OPC_CheckPredicate, 5, 28, 0, // Skip to: 60 /* 32 */ MCD_OPC_Decode, 180, 12, 0, // Opcode: SSNOP /* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 /* 40 */ MCD_OPC_CheckPredicate, 5, 16, 0, // Skip to: 60 /* 44 */ MCD_OPC_Decode, 139, 5, 0, // Opcode: EHB /* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 /* 52 */ MCD_OPC_CheckPredicate, 6, 4, 0, // Skip to: 60 /* 56 */ MCD_OPC_Decode, 147, 10, 0, // Opcode: PAUSE /* 60 */ MCD_OPC_CheckPredicate, 1, 94, 53, // Skip to: 13726 /* 64 */ MCD_OPC_Decode, 225, 11, 58, // Opcode: SLL /* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 /* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 /* 79 */ MCD_OPC_CheckPredicate, 7, 75, 53, // Skip to: 13726 /* 83 */ MCD_OPC_CheckField, 6, 5, 0, 69, 53, // Skip to: 13726 /* 89 */ MCD_OPC_Decode, 239, 8, 59, // Opcode: MOVF_I /* 93 */ MCD_OPC_FilterValue, 1, 61, 53, // Skip to: 13726 /* 97 */ MCD_OPC_CheckPredicate, 7, 57, 53, // Skip to: 13726 /* 101 */ MCD_OPC_CheckField, 6, 5, 0, 51, 53, // Skip to: 13726 /* 107 */ MCD_OPC_Decode, 131, 9, 59, // Opcode: MOVT_I /* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 /* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 /* 122 */ MCD_OPC_CheckPredicate, 1, 32, 53, // Skip to: 13726 /* 126 */ MCD_OPC_Decode, 159, 12, 58, // Opcode: SRL /* 130 */ MCD_OPC_FilterValue, 1, 24, 53, // Skip to: 13726 /* 134 */ MCD_OPC_CheckPredicate, 6, 20, 53, // Skip to: 13726 /* 138 */ MCD_OPC_Decode, 247, 10, 58, // Opcode: ROTR /* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 /* 146 */ MCD_OPC_CheckPredicate, 5, 8, 53, // Skip to: 13726 /* 150 */ MCD_OPC_CheckField, 21, 5, 0, 2, 53, // Skip to: 13726 /* 156 */ MCD_OPC_Decode, 139, 12, 58, // Opcode: SRA /* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 /* 164 */ MCD_OPC_CheckPredicate, 5, 246, 52, // Skip to: 13726 /* 168 */ MCD_OPC_CheckField, 6, 5, 0, 240, 52, // Skip to: 13726 /* 174 */ MCD_OPC_Decode, 233, 11, 36, // Opcode: SLLV /* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 /* 182 */ MCD_OPC_CheckPredicate, 8, 228, 52, // Skip to: 13726 /* 186 */ MCD_OPC_CheckField, 8, 3, 0, 222, 52, // Skip to: 13726 /* 192 */ MCD_OPC_Decode, 205, 7, 60, // Opcode: LSA /* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 /* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 /* 207 */ MCD_OPC_CheckPredicate, 5, 203, 52, // Skip to: 13726 /* 211 */ MCD_OPC_Decode, 173, 12, 36, // Opcode: SRLV /* 215 */ MCD_OPC_FilterValue, 1, 195, 52, // Skip to: 13726 /* 219 */ MCD_OPC_CheckPredicate, 6, 191, 52, // Skip to: 13726 /* 223 */ MCD_OPC_Decode, 248, 10, 36, // Opcode: ROTRV /* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 /* 231 */ MCD_OPC_CheckPredicate, 5, 179, 52, // Skip to: 13726 /* 235 */ MCD_OPC_CheckField, 6, 5, 0, 173, 52, // Skip to: 13726 /* 241 */ MCD_OPC_Decode, 152, 12, 36, // Opcode: SRAV /* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 /* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... /* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 /* 256 */ MCD_OPC_CheckPredicate, 5, 154, 52, // Skip to: 13726 /* 260 */ MCD_OPC_Decode, 136, 7, 61, // Opcode: JR /* 264 */ MCD_OPC_FilterValue, 16, 146, 52, // Skip to: 13726 /* 268 */ MCD_OPC_CheckPredicate, 9, 142, 52, // Skip to: 13726 /* 272 */ MCD_OPC_Decode, 141, 7, 61, // Opcode: JR_HB /* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 /* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 /* 287 */ MCD_OPC_CheckPredicate, 1, 123, 52, // Skip to: 13726 /* 291 */ MCD_OPC_CheckField, 16, 5, 0, 117, 52, // Skip to: 13726 /* 297 */ MCD_OPC_Decode, 249, 6, 62, // Opcode: JALR /* 301 */ MCD_OPC_FilterValue, 16, 109, 52, // Skip to: 13726 /* 305 */ MCD_OPC_CheckPredicate, 10, 105, 52, // Skip to: 13726 /* 309 */ MCD_OPC_CheckField, 16, 5, 0, 99, 52, // Skip to: 13726 /* 315 */ MCD_OPC_Decode, 128, 7, 62, // Opcode: JALR_HB /* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 /* 323 */ MCD_OPC_CheckPredicate, 7, 87, 52, // Skip to: 13726 /* 327 */ MCD_OPC_CheckField, 6, 5, 0, 81, 52, // Skip to: 13726 /* 333 */ MCD_OPC_Decode, 143, 9, 63, // Opcode: MOVZ_I_I /* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 /* 341 */ MCD_OPC_CheckPredicate, 7, 69, 52, // Skip to: 13726 /* 345 */ MCD_OPC_CheckField, 6, 5, 0, 63, 52, // Skip to: 13726 /* 351 */ MCD_OPC_Decode, 251, 8, 63, // Opcode: MOVN_I_I /* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 /* 359 */ MCD_OPC_CheckPredicate, 5, 51, 52, // Skip to: 13726 /* 363 */ MCD_OPC_Decode, 132, 13, 64, // Opcode: SYSCALL /* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 /* 371 */ MCD_OPC_CheckPredicate, 5, 39, 52, // Skip to: 13726 /* 375 */ MCD_OPC_Decode, 171, 2, 33, // Opcode: BREAK /* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 /* 383 */ MCD_OPC_CheckPredicate, 10, 27, 52, // Skip to: 13726 /* 387 */ MCD_OPC_Decode, 129, 13, 65, // Opcode: SYNC /* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 /* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 398 */ MCD_OPC_FilterValue, 0, 12, 52, // Skip to: 13726 /* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 405 */ MCD_OPC_FilterValue, 0, 5, 52, // Skip to: 13726 /* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 412 */ MCD_OPC_FilterValue, 0, 254, 51, // Skip to: 13726 /* 416 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 430 /* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 /* 426 */ MCD_OPC_Decode, 186, 8, 66, // Opcode: MFHI /* 430 */ MCD_OPC_CheckPredicate, 12, 236, 51, // Skip to: 13726 /* 434 */ MCD_OPC_Decode, 189, 8, 67, // Opcode: MFHI_DSP /* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 /* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 445 */ MCD_OPC_FilterValue, 0, 221, 51, // Skip to: 13726 /* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... /* 452 */ MCD_OPC_FilterValue, 0, 214, 51, // Skip to: 13726 /* 456 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 470 /* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 /* 466 */ MCD_OPC_Decode, 176, 9, 61, // Opcode: MTHI /* 470 */ MCD_OPC_CheckPredicate, 12, 196, 51, // Skip to: 13726 /* 474 */ MCD_OPC_Decode, 178, 9, 68, // Opcode: MTHI_DSP /* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 /* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 485 */ MCD_OPC_FilterValue, 0, 181, 51, // Skip to: 13726 /* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 492 */ MCD_OPC_FilterValue, 0, 174, 51, // Skip to: 13726 /* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 499 */ MCD_OPC_FilterValue, 0, 167, 51, // Skip to: 13726 /* 503 */ MCD_OPC_CheckPredicate, 11, 10, 0, // Skip to: 517 /* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 /* 513 */ MCD_OPC_Decode, 191, 8, 66, // Opcode: MFLO /* 517 */ MCD_OPC_CheckPredicate, 12, 149, 51, // Skip to: 13726 /* 521 */ MCD_OPC_Decode, 194, 8, 67, // Opcode: MFLO_DSP /* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 /* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 532 */ MCD_OPC_FilterValue, 0, 134, 51, // Skip to: 13726 /* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... /* 539 */ MCD_OPC_FilterValue, 0, 127, 51, // Skip to: 13726 /* 543 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 557 /* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 /* 553 */ MCD_OPC_Decode, 181, 9, 61, // Opcode: MTLO /* 557 */ MCD_OPC_CheckPredicate, 12, 109, 51, // Skip to: 13726 /* 561 */ MCD_OPC_Decode, 183, 9, 69, // Opcode: MTLO_DSP /* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 /* 569 */ MCD_OPC_CheckPredicate, 14, 97, 51, // Skip to: 13726 /* 573 */ MCD_OPC_CheckField, 8, 3, 0, 91, 51, // Skip to: 13726 /* 579 */ MCD_OPC_Decode, 194, 4, 70, // Opcode: DLSA /* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 /* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 590 */ MCD_OPC_FilterValue, 0, 76, 51, // Skip to: 13726 /* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 597 */ MCD_OPC_FilterValue, 0, 69, 51, // Skip to: 13726 /* 601 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 615 /* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 /* 611 */ MCD_OPC_Decode, 206, 9, 43, // Opcode: MULT /* 615 */ MCD_OPC_CheckPredicate, 12, 51, 51, // Skip to: 13726 /* 619 */ MCD_OPC_Decode, 208, 9, 71, // Opcode: MULT_DSP /* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 /* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 630 */ MCD_OPC_FilterValue, 0, 36, 51, // Skip to: 13726 /* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 637 */ MCD_OPC_FilterValue, 0, 29, 51, // Skip to: 13726 /* 641 */ MCD_OPC_CheckPredicate, 13, 10, 0, // Skip to: 655 /* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 /* 651 */ MCD_OPC_Decode, 210, 9, 43, // Opcode: MULTu /* 655 */ MCD_OPC_CheckPredicate, 12, 11, 51, // Skip to: 13726 /* 659 */ MCD_OPC_Decode, 207, 9, 71, // Opcode: MULTU_DSP /* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 /* 667 */ MCD_OPC_CheckPredicate, 13, 255, 50, // Skip to: 13726 /* 671 */ MCD_OPC_CheckField, 6, 10, 0, 249, 50, // Skip to: 13726 /* 677 */ MCD_OPC_Decode, 162, 11, 43, // Opcode: SDIV /* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 /* 685 */ MCD_OPC_CheckPredicate, 13, 237, 50, // Skip to: 13726 /* 689 */ MCD_OPC_CheckField, 6, 10, 0, 231, 50, // Skip to: 13726 /* 695 */ MCD_OPC_Decode, 222, 13, 43, // Opcode: UDIV /* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 /* 703 */ MCD_OPC_CheckPredicate, 5, 219, 50, // Skip to: 13726 /* 707 */ MCD_OPC_CheckField, 6, 5, 0, 213, 50, // Skip to: 13726 /* 713 */ MCD_OPC_Decode, 25, 35, // Opcode: ADD /* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 /* 720 */ MCD_OPC_CheckPredicate, 5, 202, 50, // Skip to: 13726 /* 724 */ MCD_OPC_CheckField, 6, 5, 0, 196, 50, // Skip to: 13726 /* 730 */ MCD_OPC_Decode, 77, 35, // Opcode: ADDu /* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 /* 737 */ MCD_OPC_CheckPredicate, 5, 185, 50, // Skip to: 13726 /* 741 */ MCD_OPC_CheckField, 6, 5, 0, 179, 50, // Skip to: 13726 /* 747 */ MCD_OPC_Decode, 190, 12, 35, // Opcode: SUB /* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 /* 755 */ MCD_OPC_CheckPredicate, 5, 167, 50, // Skip to: 13726 /* 759 */ MCD_OPC_CheckField, 6, 5, 0, 161, 50, // Skip to: 13726 /* 765 */ MCD_OPC_Decode, 230, 12, 35, // Opcode: SUBu /* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 /* 773 */ MCD_OPC_CheckPredicate, 1, 149, 50, // Skip to: 13726 /* 777 */ MCD_OPC_CheckField, 6, 5, 0, 143, 50, // Skip to: 13726 /* 783 */ MCD_OPC_Decode, 83, 35, // Opcode: AND /* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 /* 790 */ MCD_OPC_CheckPredicate, 1, 132, 50, // Skip to: 13726 /* 794 */ MCD_OPC_CheckField, 6, 5, 0, 126, 50, // Skip to: 13726 /* 800 */ MCD_OPC_Decode, 133, 10, 35, // Opcode: OR /* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 /* 808 */ MCD_OPC_CheckPredicate, 1, 114, 50, // Skip to: 13726 /* 812 */ MCD_OPC_CheckField, 6, 5, 0, 108, 50, // Skip to: 13726 /* 818 */ MCD_OPC_Decode, 236, 13, 35, // Opcode: XOR /* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 /* 826 */ MCD_OPC_CheckPredicate, 5, 96, 50, // Skip to: 13726 /* 830 */ MCD_OPC_CheckField, 6, 5, 0, 90, 50, // Skip to: 13726 /* 836 */ MCD_OPC_Decode, 250, 9, 35, // Opcode: NOR /* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 /* 844 */ MCD_OPC_CheckPredicate, 5, 78, 50, // Skip to: 13726 /* 848 */ MCD_OPC_CheckField, 6, 5, 0, 72, 50, // Skip to: 13726 /* 854 */ MCD_OPC_Decode, 240, 11, 35, // Opcode: SLT /* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 /* 862 */ MCD_OPC_CheckPredicate, 5, 60, 50, // Skip to: 13726 /* 866 */ MCD_OPC_CheckField, 6, 5, 0, 54, 50, // Skip to: 13726 /* 872 */ MCD_OPC_Decode, 249, 11, 35, // Opcode: SLTu /* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 /* 880 */ MCD_OPC_CheckPredicate, 15, 42, 50, // Skip to: 13726 /* 884 */ MCD_OPC_Decode, 186, 13, 72, // Opcode: TGE /* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 /* 892 */ MCD_OPC_CheckPredicate, 15, 30, 50, // Skip to: 13726 /* 896 */ MCD_OPC_Decode, 191, 13, 72, // Opcode: TGEU /* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 /* 904 */ MCD_OPC_CheckPredicate, 15, 18, 50, // Skip to: 13726 /* 908 */ MCD_OPC_Decode, 202, 13, 72, // Opcode: TLT /* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 /* 916 */ MCD_OPC_CheckPredicate, 15, 6, 50, // Skip to: 13726 /* 920 */ MCD_OPC_Decode, 206, 13, 72, // Opcode: TLTU /* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 /* 928 */ MCD_OPC_CheckPredicate, 15, 250, 49, // Skip to: 13726 /* 932 */ MCD_OPC_Decode, 182, 13, 72, // Opcode: TEQ /* 936 */ MCD_OPC_FilterValue, 54, 242, 49, // Skip to: 13726 /* 940 */ MCD_OPC_CheckPredicate, 15, 238, 49, // Skip to: 13726 /* 944 */ MCD_OPC_Decode, 209, 13, 72, // Opcode: TNE /* 948 */ MCD_OPC_FilterValue, 1, 201, 0, // Skip to: 1153 /* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 /* 959 */ MCD_OPC_CheckPredicate, 5, 219, 49, // Skip to: 13726 /* 963 */ MCD_OPC_Decode, 131, 2, 73, // Opcode: BLTZ /* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 /* 971 */ MCD_OPC_CheckPredicate, 5, 207, 49, // Skip to: 13726 /* 975 */ MCD_OPC_Decode, 217, 1, 73, // Opcode: BGEZ /* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 /* 983 */ MCD_OPC_CheckPredicate, 16, 195, 49, // Skip to: 13726 /* 987 */ MCD_OPC_Decode, 139, 2, 73, // Opcode: BLTZL /* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 /* 995 */ MCD_OPC_CheckPredicate, 16, 183, 49, // Skip to: 13726 /* 999 */ MCD_OPC_Decode, 225, 1, 73, // Opcode: BGEZL /* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 /* 1007 */ MCD_OPC_CheckPredicate, 16, 171, 49, // Skip to: 13726 /* 1011 */ MCD_OPC_Decode, 187, 13, 74, // Opcode: TGEI /* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 /* 1019 */ MCD_OPC_CheckPredicate, 16, 159, 49, // Skip to: 13726 /* 1023 */ MCD_OPC_Decode, 188, 13, 74, // Opcode: TGEIU /* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 /* 1031 */ MCD_OPC_CheckPredicate, 16, 147, 49, // Skip to: 13726 /* 1035 */ MCD_OPC_Decode, 203, 13, 74, // Opcode: TLTI /* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 /* 1043 */ MCD_OPC_CheckPredicate, 16, 135, 49, // Skip to: 13726 /* 1047 */ MCD_OPC_Decode, 221, 13, 74, // Opcode: TTLTIU /* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 /* 1055 */ MCD_OPC_CheckPredicate, 16, 123, 49, // Skip to: 13726 /* 1059 */ MCD_OPC_Decode, 183, 13, 74, // Opcode: TEQI /* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 /* 1067 */ MCD_OPC_CheckPredicate, 16, 111, 49, // Skip to: 13726 /* 1071 */ MCD_OPC_Decode, 210, 13, 74, // Opcode: TNEI /* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 /* 1079 */ MCD_OPC_CheckPredicate, 13, 99, 49, // Skip to: 13726 /* 1083 */ MCD_OPC_Decode, 133, 2, 73, // Opcode: BLTZAL /* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 /* 1091 */ MCD_OPC_CheckPredicate, 13, 87, 49, // Skip to: 13726 /* 1095 */ MCD_OPC_Decode, 219, 1, 73, // Opcode: BGEZAL /* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 /* 1103 */ MCD_OPC_CheckPredicate, 16, 75, 49, // Skip to: 13726 /* 1107 */ MCD_OPC_Decode, 135, 2, 73, // Opcode: BLTZALL /* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 /* 1115 */ MCD_OPC_CheckPredicate, 16, 63, 49, // Skip to: 13726 /* 1119 */ MCD_OPC_Decode, 221, 1, 73, // Opcode: BGEZALL /* 1123 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 1141 /* 1127 */ MCD_OPC_CheckPredicate, 12, 51, 49, // Skip to: 13726 /* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 45, 49, // Skip to: 13726 /* 1137 */ MCD_OPC_Decode, 169, 2, 75, // Opcode: BPOSGE32 /* 1141 */ MCD_OPC_FilterValue, 31, 37, 49, // Skip to: 13726 /* 1145 */ MCD_OPC_CheckPredicate, 6, 33, 49, // Skip to: 13726 /* 1149 */ MCD_OPC_Decode, 130, 13, 76, // Opcode: SYNCI /* 1153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1165 /* 1157 */ MCD_OPC_CheckPredicate, 10, 21, 49, // Skip to: 13726 /* 1161 */ MCD_OPC_Decode, 247, 6, 77, // Opcode: J /* 1165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1177 /* 1169 */ MCD_OPC_CheckPredicate, 5, 9, 49, // Skip to: 13726 /* 1173 */ MCD_OPC_Decode, 248, 6, 77, // Opcode: JAL /* 1177 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1189 /* 1181 */ MCD_OPC_CheckPredicate, 5, 253, 48, // Skip to: 13726 /* 1185 */ MCD_OPC_Decode, 206, 1, 78, // Opcode: BEQ /* 1189 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1201 /* 1193 */ MCD_OPC_CheckPredicate, 5, 241, 48, // Skip to: 13726 /* 1197 */ MCD_OPC_Decode, 145, 2, 78, // Opcode: BNE /* 1201 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1219 /* 1205 */ MCD_OPC_CheckPredicate, 5, 229, 48, // Skip to: 13726 /* 1209 */ MCD_OPC_CheckField, 16, 5, 0, 223, 48, // Skip to: 13726 /* 1215 */ MCD_OPC_Decode, 251, 1, 73, // Opcode: BLEZ /* 1219 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1237 /* 1223 */ MCD_OPC_CheckPredicate, 5, 211, 48, // Skip to: 13726 /* 1227 */ MCD_OPC_CheckField, 16, 5, 0, 205, 48, // Skip to: 13726 /* 1233 */ MCD_OPC_Decode, 227, 1, 73, // Opcode: BGTZ /* 1237 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1248 /* 1241 */ MCD_OPC_CheckPredicate, 13, 193, 48, // Skip to: 13726 /* 1245 */ MCD_OPC_Decode, 73, 79, // Opcode: ADDi /* 1248 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1259 /* 1252 */ MCD_OPC_CheckPredicate, 1, 182, 48, // Skip to: 13726 /* 1256 */ MCD_OPC_Decode, 75, 79, // Opcode: ADDiu /* 1259 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1271 /* 1263 */ MCD_OPC_CheckPredicate, 5, 171, 48, // Skip to: 13726 /* 1267 */ MCD_OPC_Decode, 243, 11, 79, // Opcode: SLTi /* 1271 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1283 /* 1275 */ MCD_OPC_CheckPredicate, 5, 159, 48, // Skip to: 13726 /* 1279 */ MCD_OPC_Decode, 246, 11, 79, // Opcode: SLTiu /* 1283 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1294 /* 1287 */ MCD_OPC_CheckPredicate, 1, 147, 48, // Skip to: 13726 /* 1291 */ MCD_OPC_Decode, 93, 80, // Opcode: ANDi /* 1294 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1306 /* 1298 */ MCD_OPC_CheckPredicate, 5, 136, 48, // Skip to: 13726 /* 1302 */ MCD_OPC_Decode, 142, 10, 80, // Opcode: ORi /* 1306 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1318 /* 1310 */ MCD_OPC_CheckPredicate, 5, 124, 48, // Skip to: 13726 /* 1314 */ MCD_OPC_Decode, 245, 13, 80, // Opcode: XORi /* 1318 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1336 /* 1322 */ MCD_OPC_CheckPredicate, 5, 112, 48, // Skip to: 13726 /* 1326 */ MCD_OPC_CheckField, 21, 5, 0, 106, 48, // Skip to: 13726 /* 1332 */ MCD_OPC_Decode, 210, 7, 52, // Opcode: LUi /* 1336 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1560 /* 1340 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 1343 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1361 /* 1347 */ MCD_OPC_CheckPredicate, 10, 87, 48, // Skip to: 13726 /* 1351 */ MCD_OPC_CheckField, 3, 8, 0, 81, 48, // Skip to: 13726 /* 1357 */ MCD_OPC_Decode, 179, 8, 81, // Opcode: MFC0 /* 1361 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1379 /* 1365 */ MCD_OPC_CheckPredicate, 10, 69, 48, // Skip to: 13726 /* 1369 */ MCD_OPC_CheckField, 3, 8, 0, 63, 48, // Skip to: 13726 /* 1375 */ MCD_OPC_Decode, 169, 9, 81, // Opcode: MTC0 /* 1379 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1434 /* 1383 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 1386 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1398 /* 1390 */ MCD_OPC_CheckPredicate, 13, 44, 48, // Skip to: 13726 /* 1394 */ MCD_OPC_Decode, 176, 1, 82, // Opcode: BC0F /* 1398 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1410 /* 1402 */ MCD_OPC_CheckPredicate, 13, 32, 48, // Skip to: 13726 /* 1406 */ MCD_OPC_Decode, 178, 1, 82, // Opcode: BC0T /* 1410 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1422 /* 1414 */ MCD_OPC_CheckPredicate, 13, 20, 48, // Skip to: 13726 /* 1418 */ MCD_OPC_Decode, 177, 1, 82, // Opcode: BC0FL /* 1422 */ MCD_OPC_FilterValue, 3, 12, 48, // Skip to: 13726 /* 1426 */ MCD_OPC_CheckPredicate, 13, 8, 48, // Skip to: 13726 /* 1430 */ MCD_OPC_Decode, 179, 1, 82, // Opcode: BC0TL /* 1434 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1469 /* 1438 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... /* 1441 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1455 /* 1447 */ MCD_OPC_CheckPredicate, 6, 243, 47, // Skip to: 13726 /* 1451 */ MCD_OPC_Decode, 179, 4, 42, // Opcode: DI /* 1455 */ MCD_OPC_FilterValue, 160, 192, 1, 233, 47, // Skip to: 13726 /* 1461 */ MCD_OPC_CheckPredicate, 6, 229, 47, // Skip to: 13726 /* 1465 */ MCD_OPC_Decode, 141, 5, 42, // Opcode: EI /* 1469 */ MCD_OPC_FilterValue, 16, 221, 47, // Skip to: 13726 /* 1473 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... /* 1476 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1488 /* 1480 */ MCD_OPC_CheckPredicate, 5, 210, 47, // Skip to: 13726 /* 1484 */ MCD_OPC_Decode, 196, 13, 0, // Opcode: TLBR /* 1488 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1500 /* 1492 */ MCD_OPC_CheckPredicate, 5, 198, 47, // Skip to: 13726 /* 1496 */ MCD_OPC_Decode, 198, 13, 0, // Opcode: TLBWI /* 1500 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1512 /* 1504 */ MCD_OPC_CheckPredicate, 5, 186, 47, // Skip to: 13726 /* 1508 */ MCD_OPC_Decode, 200, 13, 0, // Opcode: TLBWR /* 1512 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1524 /* 1516 */ MCD_OPC_CheckPredicate, 5, 174, 47, // Skip to: 13726 /* 1520 */ MCD_OPC_Decode, 194, 13, 0, // Opcode: TLBP /* 1524 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1536 /* 1528 */ MCD_OPC_CheckPredicate, 17, 162, 47, // Skip to: 13726 /* 1532 */ MCD_OPC_Decode, 143, 5, 0, // Opcode: ERET /* 1536 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1548 /* 1540 */ MCD_OPC_CheckPredicate, 10, 150, 47, // Skip to: 13726 /* 1544 */ MCD_OPC_Decode, 174, 4, 0, // Opcode: DERET /* 1548 */ MCD_OPC_FilterValue, 32, 142, 47, // Skip to: 13726 /* 1552 */ MCD_OPC_CheckPredicate, 18, 138, 47, // Skip to: 13726 /* 1556 */ MCD_OPC_Decode, 231, 13, 0, // Opcode: WAIT /* 1560 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3121 /* 1564 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 1567 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1585 /* 1571 */ MCD_OPC_CheckPredicate, 5, 119, 47, // Skip to: 13726 /* 1575 */ MCD_OPC_CheckField, 0, 11, 0, 113, 47, // Skip to: 13726 /* 1581 */ MCD_OPC_Decode, 180, 8, 83, // Opcode: MFC1 /* 1585 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1603 /* 1589 */ MCD_OPC_CheckPredicate, 19, 101, 47, // Skip to: 13726 /* 1593 */ MCD_OPC_CheckField, 0, 11, 0, 95, 47, // Skip to: 13726 /* 1599 */ MCD_OPC_Decode, 197, 4, 84, // Opcode: DMFC1 /* 1603 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1621 /* 1607 */ MCD_OPC_CheckPredicate, 5, 83, 47, // Skip to: 13726 /* 1611 */ MCD_OPC_CheckField, 0, 11, 0, 77, 47, // Skip to: 13726 /* 1617 */ MCD_OPC_Decode, 238, 2, 85, // Opcode: CFC1 /* 1621 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1639 /* 1625 */ MCD_OPC_CheckPredicate, 20, 65, 47, // Skip to: 13726 /* 1629 */ MCD_OPC_CheckField, 0, 11, 0, 59, 47, // Skip to: 13726 /* 1635 */ MCD_OPC_Decode, 183, 8, 86, // Opcode: MFHC1_D32 /* 1639 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1657 /* 1643 */ MCD_OPC_CheckPredicate, 5, 47, 47, // Skip to: 13726 /* 1647 */ MCD_OPC_CheckField, 0, 11, 0, 41, 47, // Skip to: 13726 /* 1653 */ MCD_OPC_Decode, 170, 9, 87, // Opcode: MTC1 /* 1657 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1675 /* 1661 */ MCD_OPC_CheckPredicate, 19, 29, 47, // Skip to: 13726 /* 1665 */ MCD_OPC_CheckField, 0, 11, 0, 23, 47, // Skip to: 13726 /* 1671 */ MCD_OPC_Decode, 202, 4, 88, // Opcode: DMTC1 /* 1675 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1693 /* 1679 */ MCD_OPC_CheckPredicate, 5, 11, 47, // Skip to: 13726 /* 1683 */ MCD_OPC_CheckField, 0, 11, 0, 5, 47, // Skip to: 13726 /* 1689 */ MCD_OPC_Decode, 210, 3, 89, // Opcode: CTC1 /* 1693 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1711 /* 1697 */ MCD_OPC_CheckPredicate, 20, 249, 46, // Skip to: 13726 /* 1701 */ MCD_OPC_CheckField, 0, 11, 0, 243, 46, // Skip to: 13726 /* 1707 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: MTHC1_D32 /* 1711 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1766 /* 1715 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 1718 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1730 /* 1722 */ MCD_OPC_CheckPredicate, 13, 224, 46, // Skip to: 13726 /* 1726 */ MCD_OPC_Decode, 181, 1, 91, // Opcode: BC1F /* 1730 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1742 /* 1734 */ MCD_OPC_CheckPredicate, 13, 212, 46, // Skip to: 13726 /* 1738 */ MCD_OPC_Decode, 185, 1, 91, // Opcode: BC1T /* 1742 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1754 /* 1746 */ MCD_OPC_CheckPredicate, 16, 200, 46, // Skip to: 13726 /* 1750 */ MCD_OPC_Decode, 182, 1, 91, // Opcode: BC1FL /* 1754 */ MCD_OPC_FilterValue, 3, 192, 46, // Skip to: 13726 /* 1758 */ MCD_OPC_CheckPredicate, 16, 188, 46, // Skip to: 13726 /* 1762 */ MCD_OPC_Decode, 186, 1, 91, // Opcode: BC1TL /* 1766 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1778 /* 1770 */ MCD_OPC_CheckPredicate, 8, 176, 46, // Skip to: 13726 /* 1774 */ MCD_OPC_Decode, 192, 2, 92, // Opcode: BZ_V /* 1778 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1790 /* 1782 */ MCD_OPC_CheckPredicate, 8, 164, 46, // Skip to: 13726 /* 1786 */ MCD_OPC_Decode, 166, 2, 92, // Opcode: BNZ_V /* 1790 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2386 /* 1794 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 1797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1809 /* 1801 */ MCD_OPC_CheckPredicate, 5, 145, 46, // Skip to: 13726 /* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S /* 1809 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1821 /* 1813 */ MCD_OPC_CheckPredicate, 5, 133, 46, // Skip to: 13726 /* 1817 */ MCD_OPC_Decode, 176, 6, 93, // Opcode: FSUB_S /* 1821 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1833 /* 1825 */ MCD_OPC_CheckPredicate, 5, 121, 46, // Skip to: 13726 /* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S /* 1833 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1845 /* 1837 */ MCD_OPC_CheckPredicate, 5, 109, 46, // Skip to: 13726 /* 1841 */ MCD_OPC_Decode, 210, 5, 93, // Opcode: FDIV_S /* 1845 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1863 /* 1849 */ MCD_OPC_CheckPredicate, 15, 97, 46, // Skip to: 13726 /* 1853 */ MCD_OPC_CheckField, 16, 5, 0, 91, 46, // Skip to: 13726 /* 1859 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: FSQRT_S /* 1863 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1881 /* 1867 */ MCD_OPC_CheckPredicate, 5, 79, 46, // Skip to: 13726 /* 1871 */ MCD_OPC_CheckField, 16, 5, 0, 73, 46, // Skip to: 13726 /* 1877 */ MCD_OPC_Decode, 167, 5, 94, // Opcode: FABS_S /* 1881 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1899 /* 1885 */ MCD_OPC_CheckPredicate, 5, 61, 46, // Skip to: 13726 /* 1889 */ MCD_OPC_CheckField, 16, 5, 0, 55, 46, // Skip to: 13726 /* 1895 */ MCD_OPC_Decode, 131, 6, 94, // Opcode: FMOV_S /* 1899 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1917 /* 1903 */ MCD_OPC_CheckPredicate, 5, 43, 46, // Skip to: 13726 /* 1907 */ MCD_OPC_CheckField, 16, 5, 0, 37, 46, // Skip to: 13726 /* 1913 */ MCD_OPC_Decode, 145, 6, 94, // Opcode: FNEG_S /* 1917 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1935 /* 1921 */ MCD_OPC_CheckPredicate, 15, 25, 46, // Skip to: 13726 /* 1925 */ MCD_OPC_CheckField, 16, 5, 0, 19, 46, // Skip to: 13726 /* 1931 */ MCD_OPC_Decode, 128, 11, 94, // Opcode: ROUND_W_S /* 1935 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1953 /* 1939 */ MCD_OPC_CheckPredicate, 15, 7, 46, // Skip to: 13726 /* 1943 */ MCD_OPC_CheckField, 16, 5, 0, 1, 46, // Skip to: 13726 /* 1949 */ MCD_OPC_Decode, 219, 13, 94, // Opcode: TRUNC_W_S /* 1953 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1971 /* 1957 */ MCD_OPC_CheckPredicate, 15, 245, 45, // Skip to: 13726 /* 1961 */ MCD_OPC_CheckField, 16, 5, 0, 239, 45, // Skip to: 13726 /* 1967 */ MCD_OPC_Decode, 228, 2, 94, // Opcode: CEIL_W_S /* 1971 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1989 /* 1975 */ MCD_OPC_CheckPredicate, 15, 227, 45, // Skip to: 13726 /* 1979 */ MCD_OPC_CheckField, 16, 5, 0, 221, 45, // Skip to: 13726 /* 1985 */ MCD_OPC_Decode, 244, 5, 94, // Opcode: FLOOR_W_S /* 1989 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2020 /* 1993 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 1996 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2008 /* 2000 */ MCD_OPC_CheckPredicate, 7, 202, 45, // Skip to: 13726 /* 2004 */ MCD_OPC_Decode, 242, 8, 95, // Opcode: MOVF_S /* 2008 */ MCD_OPC_FilterValue, 1, 194, 45, // Skip to: 13726 /* 2012 */ MCD_OPC_CheckPredicate, 7, 190, 45, // Skip to: 13726 /* 2016 */ MCD_OPC_Decode, 134, 9, 95, // Opcode: MOVT_S /* 2020 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2032 /* 2024 */ MCD_OPC_CheckPredicate, 7, 178, 45, // Skip to: 13726 /* 2028 */ MCD_OPC_Decode, 146, 9, 96, // Opcode: MOVZ_I_S /* 2032 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2044 /* 2036 */ MCD_OPC_CheckPredicate, 7, 166, 45, // Skip to: 13726 /* 2040 */ MCD_OPC_Decode, 254, 8, 96, // Opcode: MOVN_I_S /* 2044 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2062 /* 2048 */ MCD_OPC_CheckPredicate, 21, 154, 45, // Skip to: 13726 /* 2052 */ MCD_OPC_CheckField, 16, 5, 0, 148, 45, // Skip to: 13726 /* 2058 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: CVT_D32_S /* 2062 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2080 /* 2066 */ MCD_OPC_CheckPredicate, 5, 136, 45, // Skip to: 13726 /* 2070 */ MCD_OPC_CheckField, 16, 5, 0, 130, 45, // Skip to: 13726 /* 2076 */ MCD_OPC_Decode, 233, 3, 94, // Opcode: CVT_W_S /* 2080 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2098 /* 2084 */ MCD_OPC_CheckPredicate, 22, 118, 45, // Skip to: 13726 /* 2088 */ MCD_OPC_CheckField, 16, 5, 0, 112, 45, // Skip to: 13726 /* 2094 */ MCD_OPC_Decode, 222, 3, 98, // Opcode: CVT_L_S /* 2098 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2116 /* 2102 */ MCD_OPC_CheckPredicate, 13, 100, 45, // Skip to: 13726 /* 2106 */ MCD_OPC_CheckField, 6, 5, 0, 94, 45, // Skip to: 13726 /* 2112 */ MCD_OPC_Decode, 240, 3, 99, // Opcode: C_F_S /* 2116 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2134 /* 2120 */ MCD_OPC_CheckPredicate, 13, 82, 45, // Skip to: 13726 /* 2124 */ MCD_OPC_CheckField, 6, 5, 0, 76, 45, // Skip to: 13726 /* 2130 */ MCD_OPC_Decode, 154, 4, 99, // Opcode: C_UN_S /* 2134 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2152 /* 2138 */ MCD_OPC_CheckPredicate, 13, 64, 45, // Skip to: 13726 /* 2142 */ MCD_OPC_CheckField, 6, 5, 0, 58, 45, // Skip to: 13726 /* 2148 */ MCD_OPC_Decode, 237, 3, 99, // Opcode: C_EQ_S /* 2152 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2170 /* 2156 */ MCD_OPC_CheckPredicate, 13, 46, 45, // Skip to: 13726 /* 2160 */ MCD_OPC_CheckField, 6, 5, 0, 40, 45, // Skip to: 13726 /* 2166 */ MCD_OPC_Decode, 145, 4, 99, // Opcode: C_UEQ_S /* 2170 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2188 /* 2174 */ MCD_OPC_CheckPredicate, 13, 28, 45, // Skip to: 13726 /* 2178 */ MCD_OPC_CheckField, 6, 5, 0, 22, 45, // Skip to: 13726 /* 2184 */ MCD_OPC_Decode, 136, 4, 99, // Opcode: C_OLT_S /* 2188 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2206 /* 2192 */ MCD_OPC_CheckPredicate, 13, 10, 45, // Skip to: 13726 /* 2196 */ MCD_OPC_CheckField, 6, 5, 0, 4, 45, // Skip to: 13726 /* 2202 */ MCD_OPC_Decode, 151, 4, 99, // Opcode: C_ULT_S /* 2206 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2224 /* 2210 */ MCD_OPC_CheckPredicate, 13, 248, 44, // Skip to: 13726 /* 2214 */ MCD_OPC_CheckField, 6, 5, 0, 242, 44, // Skip to: 13726 /* 2220 */ MCD_OPC_Decode, 133, 4, 99, // Opcode: C_OLE_S /* 2224 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2242 /* 2228 */ MCD_OPC_CheckPredicate, 13, 230, 44, // Skip to: 13726 /* 2232 */ MCD_OPC_CheckField, 6, 5, 0, 224, 44, // Skip to: 13726 /* 2238 */ MCD_OPC_Decode, 148, 4, 99, // Opcode: C_ULE_S /* 2242 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2260 /* 2246 */ MCD_OPC_CheckPredicate, 13, 212, 44, // Skip to: 13726 /* 2250 */ MCD_OPC_CheckField, 6, 5, 0, 206, 44, // Skip to: 13726 /* 2256 */ MCD_OPC_Decode, 142, 4, 99, // Opcode: C_SF_S /* 2260 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2278 /* 2264 */ MCD_OPC_CheckPredicate, 13, 194, 44, // Skip to: 13726 /* 2268 */ MCD_OPC_CheckField, 6, 5, 0, 188, 44, // Skip to: 13726 /* 2274 */ MCD_OPC_Decode, 252, 3, 99, // Opcode: C_NGLE_S /* 2278 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2296 /* 2282 */ MCD_OPC_CheckPredicate, 13, 176, 44, // Skip to: 13726 /* 2286 */ MCD_OPC_CheckField, 6, 5, 0, 170, 44, // Skip to: 13726 /* 2292 */ MCD_OPC_Decode, 139, 4, 99, // Opcode: C_SEQ_S /* 2296 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2314 /* 2300 */ MCD_OPC_CheckPredicate, 13, 158, 44, // Skip to: 13726 /* 2304 */ MCD_OPC_CheckField, 6, 5, 0, 152, 44, // Skip to: 13726 /* 2310 */ MCD_OPC_Decode, 255, 3, 99, // Opcode: C_NGL_S /* 2314 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2332 /* 2318 */ MCD_OPC_CheckPredicate, 13, 140, 44, // Skip to: 13726 /* 2322 */ MCD_OPC_CheckField, 6, 5, 0, 134, 44, // Skip to: 13726 /* 2328 */ MCD_OPC_Decode, 246, 3, 99, // Opcode: C_LT_S /* 2332 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2350 /* 2336 */ MCD_OPC_CheckPredicate, 13, 122, 44, // Skip to: 13726 /* 2340 */ MCD_OPC_CheckField, 6, 5, 0, 116, 44, // Skip to: 13726 /* 2346 */ MCD_OPC_Decode, 249, 3, 99, // Opcode: C_NGE_S /* 2350 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2368 /* 2354 */ MCD_OPC_CheckPredicate, 13, 104, 44, // Skip to: 13726 /* 2358 */ MCD_OPC_CheckField, 6, 5, 0, 98, 44, // Skip to: 13726 /* 2364 */ MCD_OPC_Decode, 243, 3, 99, // Opcode: C_LE_S /* 2368 */ MCD_OPC_FilterValue, 63, 90, 44, // Skip to: 13726 /* 2372 */ MCD_OPC_CheckPredicate, 13, 86, 44, // Skip to: 13726 /* 2376 */ MCD_OPC_CheckField, 6, 5, 0, 80, 44, // Skip to: 13726 /* 2382 */ MCD_OPC_Decode, 130, 4, 99, // Opcode: C_NGT_S /* 2386 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2982 /* 2390 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 2393 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2405 /* 2397 */ MCD_OPC_CheckPredicate, 21, 61, 44, // Skip to: 13726 /* 2401 */ MCD_OPC_Decode, 171, 5, 100, // Opcode: FADD_D32 /* 2405 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2417 /* 2409 */ MCD_OPC_CheckPredicate, 21, 49, 44, // Skip to: 13726 /* 2413 */ MCD_OPC_Decode, 173, 6, 100, // Opcode: FSUB_D32 /* 2417 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2429 /* 2421 */ MCD_OPC_CheckPredicate, 21, 37, 44, // Skip to: 13726 /* 2425 */ MCD_OPC_Decode, 136, 6, 100, // Opcode: FMUL_D32 /* 2429 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2441 /* 2433 */ MCD_OPC_CheckPredicate, 21, 25, 44, // Skip to: 13726 /* 2437 */ MCD_OPC_Decode, 207, 5, 100, // Opcode: FDIV_D32 /* 2441 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2459 /* 2445 */ MCD_OPC_CheckPredicate, 23, 13, 44, // Skip to: 13726 /* 2449 */ MCD_OPC_CheckField, 16, 5, 0, 7, 44, // Skip to: 13726 /* 2455 */ MCD_OPC_Decode, 166, 6, 101, // Opcode: FSQRT_D32 /* 2459 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2477 /* 2463 */ MCD_OPC_CheckPredicate, 21, 251, 43, // Skip to: 13726 /* 2467 */ MCD_OPC_CheckField, 16, 5, 0, 245, 43, // Skip to: 13726 /* 2473 */ MCD_OPC_Decode, 164, 5, 101, // Opcode: FABS_D32 /* 2477 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2495 /* 2481 */ MCD_OPC_CheckPredicate, 21, 233, 43, // Skip to: 13726 /* 2485 */ MCD_OPC_CheckField, 16, 5, 0, 227, 43, // Skip to: 13726 /* 2491 */ MCD_OPC_Decode, 128, 6, 101, // Opcode: FMOV_D32 /* 2495 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2513 /* 2499 */ MCD_OPC_CheckPredicate, 21, 215, 43, // Skip to: 13726 /* 2503 */ MCD_OPC_CheckField, 16, 5, 0, 209, 43, // Skip to: 13726 /* 2509 */ MCD_OPC_Decode, 142, 6, 101, // Opcode: FNEG_D32 /* 2513 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2531 /* 2517 */ MCD_OPC_CheckPredicate, 23, 197, 43, // Skip to: 13726 /* 2521 */ MCD_OPC_CheckField, 16, 5, 0, 191, 43, // Skip to: 13726 /* 2527 */ MCD_OPC_Decode, 253, 10, 102, // Opcode: ROUND_W_D32 /* 2531 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2549 /* 2535 */ MCD_OPC_CheckPredicate, 23, 179, 43, // Skip to: 13726 /* 2539 */ MCD_OPC_CheckField, 16, 5, 0, 173, 43, // Skip to: 13726 /* 2545 */ MCD_OPC_Decode, 216, 13, 102, // Opcode: TRUNC_W_D32 /* 2549 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2567 /* 2553 */ MCD_OPC_CheckPredicate, 23, 161, 43, // Skip to: 13726 /* 2557 */ MCD_OPC_CheckField, 16, 5, 0, 155, 43, // Skip to: 13726 /* 2563 */ MCD_OPC_Decode, 225, 2, 102, // Opcode: CEIL_W_D32 /* 2567 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2585 /* 2571 */ MCD_OPC_CheckPredicate, 23, 143, 43, // Skip to: 13726 /* 2575 */ MCD_OPC_CheckField, 16, 5, 0, 137, 43, // Skip to: 13726 /* 2581 */ MCD_OPC_Decode, 241, 5, 102, // Opcode: FLOOR_W_D32 /* 2585 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2616 /* 2589 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 2592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2604 /* 2596 */ MCD_OPC_CheckPredicate, 24, 118, 43, // Skip to: 13726 /* 2600 */ MCD_OPC_Decode, 236, 8, 103, // Opcode: MOVF_D32 /* 2604 */ MCD_OPC_FilterValue, 1, 110, 43, // Skip to: 13726 /* 2608 */ MCD_OPC_CheckPredicate, 24, 106, 43, // Skip to: 13726 /* 2612 */ MCD_OPC_Decode, 128, 9, 103, // Opcode: MOVT_D32 /* 2616 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2628 /* 2620 */ MCD_OPC_CheckPredicate, 24, 94, 43, // Skip to: 13726 /* 2624 */ MCD_OPC_Decode, 140, 9, 104, // Opcode: MOVZ_I_D32 /* 2628 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2640 /* 2632 */ MCD_OPC_CheckPredicate, 24, 82, 43, // Skip to: 13726 /* 2636 */ MCD_OPC_Decode, 248, 8, 104, // Opcode: MOVN_I_D32 /* 2640 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2658 /* 2644 */ MCD_OPC_CheckPredicate, 21, 70, 43, // Skip to: 13726 /* 2648 */ MCD_OPC_CheckField, 16, 5, 0, 64, 43, // Skip to: 13726 /* 2654 */ MCD_OPC_Decode, 224, 3, 102, // Opcode: CVT_S_D32 /* 2658 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2676 /* 2662 */ MCD_OPC_CheckPredicate, 21, 52, 43, // Skip to: 13726 /* 2666 */ MCD_OPC_CheckField, 16, 5, 0, 46, 43, // Skip to: 13726 /* 2672 */ MCD_OPC_Decode, 230, 3, 102, // Opcode: CVT_W_D32 /* 2676 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2694 /* 2680 */ MCD_OPC_CheckPredicate, 22, 34, 43, // Skip to: 13726 /* 2684 */ MCD_OPC_CheckField, 16, 5, 0, 28, 43, // Skip to: 13726 /* 2690 */ MCD_OPC_Decode, 220, 3, 105, // Opcode: CVT_L_D64 /* 2694 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2712 /* 2698 */ MCD_OPC_CheckPredicate, 25, 16, 43, // Skip to: 13726 /* 2702 */ MCD_OPC_CheckField, 6, 5, 0, 10, 43, // Skip to: 13726 /* 2708 */ MCD_OPC_Decode, 238, 3, 106, // Opcode: C_F_D32 /* 2712 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2730 /* 2716 */ MCD_OPC_CheckPredicate, 25, 254, 42, // Skip to: 13726 /* 2720 */ MCD_OPC_CheckField, 6, 5, 0, 248, 42, // Skip to: 13726 /* 2726 */ MCD_OPC_Decode, 152, 4, 106, // Opcode: C_UN_D32 /* 2730 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2748 /* 2734 */ MCD_OPC_CheckPredicate, 25, 236, 42, // Skip to: 13726 /* 2738 */ MCD_OPC_CheckField, 6, 5, 0, 230, 42, // Skip to: 13726 /* 2744 */ MCD_OPC_Decode, 235, 3, 106, // Opcode: C_EQ_D32 /* 2748 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2766 /* 2752 */ MCD_OPC_CheckPredicate, 25, 218, 42, // Skip to: 13726 /* 2756 */ MCD_OPC_CheckField, 6, 5, 0, 212, 42, // Skip to: 13726 /* 2762 */ MCD_OPC_Decode, 143, 4, 106, // Opcode: C_UEQ_D32 /* 2766 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2784 /* 2770 */ MCD_OPC_CheckPredicate, 25, 200, 42, // Skip to: 13726 /* 2774 */ MCD_OPC_CheckField, 6, 5, 0, 194, 42, // Skip to: 13726 /* 2780 */ MCD_OPC_Decode, 134, 4, 106, // Opcode: C_OLT_D32 /* 2784 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2802 /* 2788 */ MCD_OPC_CheckPredicate, 25, 182, 42, // Skip to: 13726 /* 2792 */ MCD_OPC_CheckField, 6, 5, 0, 176, 42, // Skip to: 13726 /* 2798 */ MCD_OPC_Decode, 149, 4, 106, // Opcode: C_ULT_D32 /* 2802 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2820 /* 2806 */ MCD_OPC_CheckPredicate, 25, 164, 42, // Skip to: 13726 /* 2810 */ MCD_OPC_CheckField, 6, 5, 0, 158, 42, // Skip to: 13726 /* 2816 */ MCD_OPC_Decode, 131, 4, 106, // Opcode: C_OLE_D32 /* 2820 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2838 /* 2824 */ MCD_OPC_CheckPredicate, 25, 146, 42, // Skip to: 13726 /* 2828 */ MCD_OPC_CheckField, 6, 5, 0, 140, 42, // Skip to: 13726 /* 2834 */ MCD_OPC_Decode, 146, 4, 106, // Opcode: C_ULE_D32 /* 2838 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2856 /* 2842 */ MCD_OPC_CheckPredicate, 25, 128, 42, // Skip to: 13726 /* 2846 */ MCD_OPC_CheckField, 6, 5, 0, 122, 42, // Skip to: 13726 /* 2852 */ MCD_OPC_Decode, 140, 4, 106, // Opcode: C_SF_D32 /* 2856 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2874 /* 2860 */ MCD_OPC_CheckPredicate, 25, 110, 42, // Skip to: 13726 /* 2864 */ MCD_OPC_CheckField, 6, 5, 0, 104, 42, // Skip to: 13726 /* 2870 */ MCD_OPC_Decode, 250, 3, 106, // Opcode: C_NGLE_D32 /* 2874 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2892 /* 2878 */ MCD_OPC_CheckPredicate, 25, 92, 42, // Skip to: 13726 /* 2882 */ MCD_OPC_CheckField, 6, 5, 0, 86, 42, // Skip to: 13726 /* 2888 */ MCD_OPC_Decode, 137, 4, 106, // Opcode: C_SEQ_D32 /* 2892 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2910 /* 2896 */ MCD_OPC_CheckPredicate, 25, 74, 42, // Skip to: 13726 /* 2900 */ MCD_OPC_CheckField, 6, 5, 0, 68, 42, // Skip to: 13726 /* 2906 */ MCD_OPC_Decode, 253, 3, 106, // Opcode: C_NGL_D32 /* 2910 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2928 /* 2914 */ MCD_OPC_CheckPredicate, 25, 56, 42, // Skip to: 13726 /* 2918 */ MCD_OPC_CheckField, 6, 5, 0, 50, 42, // Skip to: 13726 /* 2924 */ MCD_OPC_Decode, 244, 3, 106, // Opcode: C_LT_D32 /* 2928 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2946 /* 2932 */ MCD_OPC_CheckPredicate, 25, 38, 42, // Skip to: 13726 /* 2936 */ MCD_OPC_CheckField, 6, 5, 0, 32, 42, // Skip to: 13726 /* 2942 */ MCD_OPC_Decode, 247, 3, 106, // Opcode: C_NGE_D32 /* 2946 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2964 /* 2950 */ MCD_OPC_CheckPredicate, 25, 20, 42, // Skip to: 13726 /* 2954 */ MCD_OPC_CheckField, 6, 5, 0, 14, 42, // Skip to: 13726 /* 2960 */ MCD_OPC_Decode, 241, 3, 106, // Opcode: C_LE_D32 /* 2964 */ MCD_OPC_FilterValue, 63, 6, 42, // Skip to: 13726 /* 2968 */ MCD_OPC_CheckPredicate, 25, 2, 42, // Skip to: 13726 /* 2972 */ MCD_OPC_CheckField, 6, 5, 0, 252, 41, // Skip to: 13726 /* 2978 */ MCD_OPC_Decode, 128, 4, 106, // Opcode: C_NGT_D32 /* 2982 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3025 /* 2986 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 2989 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3007 /* 2993 */ MCD_OPC_CheckPredicate, 5, 233, 41, // Skip to: 13726 /* 2997 */ MCD_OPC_CheckField, 16, 5, 0, 227, 41, // Skip to: 13726 /* 3003 */ MCD_OPC_Decode, 228, 3, 94, // Opcode: CVT_S_W /* 3007 */ MCD_OPC_FilterValue, 33, 219, 41, // Skip to: 13726 /* 3011 */ MCD_OPC_CheckPredicate, 21, 215, 41, // Skip to: 13726 /* 3015 */ MCD_OPC_CheckField, 16, 5, 0, 209, 41, // Skip to: 13726 /* 3021 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: CVT_D32_W /* 3025 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3037 /* 3029 */ MCD_OPC_CheckPredicate, 8, 197, 41, // Skip to: 13726 /* 3033 */ MCD_OPC_Decode, 189, 2, 92, // Opcode: BZ_B /* 3037 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3049 /* 3041 */ MCD_OPC_CheckPredicate, 8, 185, 41, // Skip to: 13726 /* 3045 */ MCD_OPC_Decode, 191, 2, 107, // Opcode: BZ_H /* 3049 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3061 /* 3053 */ MCD_OPC_CheckPredicate, 8, 173, 41, // Skip to: 13726 /* 3057 */ MCD_OPC_Decode, 193, 2, 108, // Opcode: BZ_W /* 3061 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3073 /* 3065 */ MCD_OPC_CheckPredicate, 8, 161, 41, // Skip to: 13726 /* 3069 */ MCD_OPC_Decode, 190, 2, 109, // Opcode: BZ_D /* 3073 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3085 /* 3077 */ MCD_OPC_CheckPredicate, 8, 149, 41, // Skip to: 13726 /* 3081 */ MCD_OPC_Decode, 163, 2, 92, // Opcode: BNZ_B /* 3085 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3097 /* 3089 */ MCD_OPC_CheckPredicate, 8, 137, 41, // Skip to: 13726 /* 3093 */ MCD_OPC_Decode, 165, 2, 107, // Opcode: BNZ_H /* 3097 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3109 /* 3101 */ MCD_OPC_CheckPredicate, 8, 125, 41, // Skip to: 13726 /* 3105 */ MCD_OPC_Decode, 167, 2, 108, // Opcode: BNZ_W /* 3109 */ MCD_OPC_FilterValue, 31, 117, 41, // Skip to: 13726 /* 3113 */ MCD_OPC_CheckPredicate, 8, 113, 41, // Skip to: 13726 /* 3117 */ MCD_OPC_Decode, 164, 2, 109, // Opcode: BNZ_D /* 3121 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3219 /* 3125 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 3128 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3146 /* 3132 */ MCD_OPC_CheckPredicate, 5, 94, 41, // Skip to: 13726 /* 3136 */ MCD_OPC_CheckField, 3, 8, 0, 88, 41, // Skip to: 13726 /* 3142 */ MCD_OPC_Decode, 182, 8, 81, // Opcode: MFC2 /* 3146 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3164 /* 3150 */ MCD_OPC_CheckPredicate, 5, 76, 41, // Skip to: 13726 /* 3154 */ MCD_OPC_CheckField, 3, 8, 0, 70, 41, // Skip to: 13726 /* 3160 */ MCD_OPC_Decode, 172, 9, 81, // Opcode: MTC2 /* 3164 */ MCD_OPC_FilterValue, 8, 62, 41, // Skip to: 13726 /* 3168 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 3171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3183 /* 3175 */ MCD_OPC_CheckPredicate, 13, 51, 41, // Skip to: 13726 /* 3179 */ MCD_OPC_Decode, 189, 1, 82, // Opcode: BC2F /* 3183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3195 /* 3187 */ MCD_OPC_CheckPredicate, 13, 39, 41, // Skip to: 13726 /* 3191 */ MCD_OPC_Decode, 192, 1, 82, // Opcode: BC2T /* 3195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3207 /* 3199 */ MCD_OPC_CheckPredicate, 13, 27, 41, // Skip to: 13726 /* 3203 */ MCD_OPC_Decode, 190, 1, 82, // Opcode: BC2FL /* 3207 */ MCD_OPC_FilterValue, 3, 19, 41, // Skip to: 13726 /* 3211 */ MCD_OPC_CheckPredicate, 13, 15, 41, // Skip to: 13726 /* 3215 */ MCD_OPC_Decode, 193, 1, 82, // Opcode: BC2TL /* 3219 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3488 /* 3223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 3226 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3281 /* 3230 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 3233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3245 /* 3237 */ MCD_OPC_CheckPredicate, 13, 40, 0, // Skip to: 3281 /* 3241 */ MCD_OPC_Decode, 194, 1, 82, // Opcode: BC3F /* 3245 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3257 /* 3249 */ MCD_OPC_CheckPredicate, 13, 28, 0, // Skip to: 3281 /* 3253 */ MCD_OPC_Decode, 196, 1, 82, // Opcode: BC3T /* 3257 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3269 /* 3261 */ MCD_OPC_CheckPredicate, 13, 16, 0, // Skip to: 3281 /* 3265 */ MCD_OPC_Decode, 195, 1, 82, // Opcode: BC3FL /* 3269 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3281 /* 3273 */ MCD_OPC_CheckPredicate, 13, 4, 0, // Skip to: 3281 /* 3277 */ MCD_OPC_Decode, 197, 1, 82, // Opcode: BC3TL /* 3281 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 3284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3302 /* 3288 */ MCD_OPC_CheckPredicate, 26, 194, 40, // Skip to: 13726 /* 3292 */ MCD_OPC_CheckField, 11, 5, 0, 188, 40, // Skip to: 13726 /* 3298 */ MCD_OPC_Decode, 237, 7, 110, // Opcode: LWXC1 /* 3302 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3320 /* 3306 */ MCD_OPC_CheckPredicate, 27, 176, 40, // Skip to: 13726 /* 3310 */ MCD_OPC_CheckField, 11, 5, 0, 170, 40, // Skip to: 13726 /* 3316 */ MCD_OPC_Decode, 175, 7, 111, // Opcode: LDXC1 /* 3320 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3338 /* 3324 */ MCD_OPC_CheckPredicate, 28, 158, 40, // Skip to: 13726 /* 3328 */ MCD_OPC_CheckField, 11, 5, 0, 152, 40, // Skip to: 13726 /* 3334 */ MCD_OPC_Decode, 207, 7, 111, // Opcode: LUXC1 /* 3338 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3356 /* 3342 */ MCD_OPC_CheckPredicate, 26, 140, 40, // Skip to: 13726 /* 3346 */ MCD_OPC_CheckField, 6, 5, 0, 134, 40, // Skip to: 13726 /* 3352 */ MCD_OPC_Decode, 254, 12, 112, // Opcode: SWXC1 /* 3356 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3374 /* 3360 */ MCD_OPC_CheckPredicate, 27, 122, 40, // Skip to: 13726 /* 3364 */ MCD_OPC_CheckField, 6, 5, 0, 116, 40, // Skip to: 13726 /* 3370 */ MCD_OPC_Decode, 166, 11, 113, // Opcode: SDXC1 /* 3374 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3392 /* 3378 */ MCD_OPC_CheckPredicate, 28, 104, 40, // Skip to: 13726 /* 3382 */ MCD_OPC_CheckField, 6, 5, 0, 98, 40, // Skip to: 13726 /* 3388 */ MCD_OPC_Decode, 232, 12, 113, // Opcode: SUXC1 /* 3392 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3404 /* 3396 */ MCD_OPC_CheckPredicate, 26, 86, 40, // Skip to: 13726 /* 3400 */ MCD_OPC_Decode, 149, 8, 114, // Opcode: MADD_S /* 3404 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3416 /* 3408 */ MCD_OPC_CheckPredicate, 29, 74, 40, // Skip to: 13726 /* 3412 */ MCD_OPC_Decode, 142, 8, 115, // Opcode: MADD_D32 /* 3416 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3428 /* 3420 */ MCD_OPC_CheckPredicate, 26, 62, 40, // Skip to: 13726 /* 3424 */ MCD_OPC_Decode, 167, 9, 114, // Opcode: MSUB_S /* 3428 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3440 /* 3432 */ MCD_OPC_CheckPredicate, 29, 50, 40, // Skip to: 13726 /* 3436 */ MCD_OPC_Decode, 160, 9, 115, // Opcode: MSUB_D32 /* 3440 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3452 /* 3444 */ MCD_OPC_CheckPredicate, 26, 38, 40, // Skip to: 13726 /* 3448 */ MCD_OPC_Decode, 242, 9, 114, // Opcode: NMADD_S /* 3452 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3464 /* 3456 */ MCD_OPC_CheckPredicate, 29, 26, 40, // Skip to: 13726 /* 3460 */ MCD_OPC_Decode, 239, 9, 115, // Opcode: NMADD_D32 /* 3464 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3476 /* 3468 */ MCD_OPC_CheckPredicate, 26, 14, 40, // Skip to: 13726 /* 3472 */ MCD_OPC_Decode, 247, 9, 114, // Opcode: NMSUB_S /* 3476 */ MCD_OPC_FilterValue, 57, 6, 40, // Skip to: 13726 /* 3480 */ MCD_OPC_CheckPredicate, 29, 2, 40, // Skip to: 13726 /* 3484 */ MCD_OPC_Decode, 244, 9, 115, // Opcode: NMSUB_D32 /* 3488 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3500 /* 3492 */ MCD_OPC_CheckPredicate, 16, 246, 39, // Skip to: 13726 /* 3496 */ MCD_OPC_Decode, 209, 1, 78, // Opcode: BEQL /* 3500 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3512 /* 3504 */ MCD_OPC_CheckPredicate, 16, 234, 39, // Skip to: 13726 /* 3508 */ MCD_OPC_Decode, 156, 2, 78, // Opcode: BNEL /* 3512 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3530 /* 3516 */ MCD_OPC_CheckPredicate, 16, 222, 39, // Skip to: 13726 /* 3520 */ MCD_OPC_CheckField, 16, 5, 0, 216, 39, // Skip to: 13726 /* 3526 */ MCD_OPC_Decode, 255, 1, 73, // Opcode: BLEZL /* 3530 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3548 /* 3534 */ MCD_OPC_CheckPredicate, 16, 204, 39, // Skip to: 13726 /* 3538 */ MCD_OPC_CheckField, 16, 5, 0, 198, 39, // Skip to: 13726 /* 3544 */ MCD_OPC_Decode, 231, 1, 73, // Opcode: BGTZL /* 3548 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3781 /* 3552 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 3555 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3595 /* 3559 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 3562 */ MCD_OPC_FilterValue, 0, 176, 39, // Skip to: 13726 /* 3566 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 3569 */ MCD_OPC_FilterValue, 0, 169, 39, // Skip to: 13726 /* 3573 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3587 /* 3577 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3587 /* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD /* 3587 */ MCD_OPC_CheckPredicate, 12, 151, 39, // Skip to: 13726 /* 3591 */ MCD_OPC_Decode, 145, 8, 116, // Opcode: MADD_DSP /* 3595 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3635 /* 3599 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 3602 */ MCD_OPC_FilterValue, 0, 136, 39, // Skip to: 13726 /* 3606 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 3609 */ MCD_OPC_FilterValue, 0, 129, 39, // Skip to: 13726 /* 3613 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3627 /* 3617 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3627 /* 3623 */ MCD_OPC_Decode, 135, 8, 43, // Opcode: MADDU /* 3627 */ MCD_OPC_CheckPredicate, 12, 111, 39, // Skip to: 13726 /* 3631 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MADDU_DSP /* 3635 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3653 /* 3639 */ MCD_OPC_CheckPredicate, 9, 99, 39, // Skip to: 13726 /* 3643 */ MCD_OPC_CheckField, 6, 5, 0, 93, 39, // Skip to: 13726 /* 3649 */ MCD_OPC_Decode, 193, 9, 35, // Opcode: MUL /* 3653 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3693 /* 3657 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 3660 */ MCD_OPC_FilterValue, 0, 78, 39, // Skip to: 13726 /* 3664 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 3667 */ MCD_OPC_FilterValue, 0, 71, 39, // Skip to: 13726 /* 3671 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3685 /* 3675 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3685 /* 3681 */ MCD_OPC_Decode, 148, 9, 43, // Opcode: MSUB /* 3685 */ MCD_OPC_CheckPredicate, 12, 53, 39, // Skip to: 13726 /* 3689 */ MCD_OPC_Decode, 163, 9, 116, // Opcode: MSUB_DSP /* 3693 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3733 /* 3697 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 3700 */ MCD_OPC_FilterValue, 0, 38, 39, // Skip to: 13726 /* 3704 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 3707 */ MCD_OPC_FilterValue, 0, 31, 39, // Skip to: 13726 /* 3711 */ MCD_OPC_CheckPredicate, 9, 10, 0, // Skip to: 3725 /* 3715 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3725 /* 3721 */ MCD_OPC_Decode, 153, 9, 43, // Opcode: MSUBU /* 3725 */ MCD_OPC_CheckPredicate, 12, 13, 39, // Skip to: 13726 /* 3729 */ MCD_OPC_Decode, 154, 9, 116, // Opcode: MSUBU_DSP /* 3733 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3751 /* 3737 */ MCD_OPC_CheckPredicate, 9, 1, 39, // Skip to: 13726 /* 3741 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13726 /* 3747 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: CLZ /* 3751 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3769 /* 3755 */ MCD_OPC_CheckPredicate, 9, 239, 38, // Skip to: 13726 /* 3759 */ MCD_OPC_CheckField, 6, 5, 0, 233, 38, // Skip to: 13726 /* 3765 */ MCD_OPC_Decode, 133, 3, 117, // Opcode: CLO /* 3769 */ MCD_OPC_FilterValue, 63, 225, 38, // Skip to: 13726 /* 3773 */ MCD_OPC_CheckPredicate, 9, 221, 38, // Skip to: 13726 /* 3777 */ MCD_OPC_Decode, 152, 11, 64, // Opcode: SDBBP /* 3781 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3793 /* 3785 */ MCD_OPC_CheckPredicate, 9, 209, 38, // Skip to: 13726 /* 3789 */ MCD_OPC_Decode, 131, 7, 77, // Opcode: JALX /* 3793 */ MCD_OPC_FilterValue, 30, 28, 28, // Skip to: 10993 /* 3797 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 3800 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3854 /* 3804 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 3807 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3818 /* 3811 */ MCD_OPC_CheckPredicate, 8, 183, 38, // Skip to: 13726 /* 3815 */ MCD_OPC_Decode, 87, 118, // Opcode: ANDI_B /* 3818 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3830 /* 3822 */ MCD_OPC_CheckPredicate, 8, 172, 38, // Skip to: 13726 /* 3826 */ MCD_OPC_Decode, 136, 10, 118, // Opcode: ORI_B /* 3830 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3842 /* 3834 */ MCD_OPC_CheckPredicate, 8, 160, 38, // Skip to: 13726 /* 3838 */ MCD_OPC_Decode, 252, 9, 118, // Opcode: NORI_B /* 3842 */ MCD_OPC_FilterValue, 3, 152, 38, // Skip to: 13726 /* 3846 */ MCD_OPC_CheckPredicate, 8, 148, 38, // Skip to: 13726 /* 3850 */ MCD_OPC_Decode, 239, 13, 118, // Opcode: XORI_B /* 3854 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3897 /* 3858 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 3861 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3873 /* 3865 */ MCD_OPC_CheckPredicate, 8, 129, 38, // Skip to: 13726 /* 3869 */ MCD_OPC_Decode, 141, 2, 119, // Opcode: BMNZI_B /* 3873 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3885 /* 3877 */ MCD_OPC_CheckPredicate, 8, 117, 38, // Skip to: 13726 /* 3881 */ MCD_OPC_Decode, 143, 2, 119, // Opcode: BMZI_B /* 3885 */ MCD_OPC_FilterValue, 2, 109, 38, // Skip to: 13726 /* 3889 */ MCD_OPC_CheckPredicate, 8, 105, 38, // Skip to: 13726 /* 3893 */ MCD_OPC_Decode, 174, 2, 119, // Opcode: BSELI_B /* 3897 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3940 /* 3901 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... /* 3904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3916 /* 3908 */ MCD_OPC_CheckPredicate, 8, 86, 38, // Skip to: 13726 /* 3912 */ MCD_OPC_Decode, 189, 11, 118, // Opcode: SHF_B /* 3916 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3928 /* 3920 */ MCD_OPC_CheckPredicate, 8, 74, 38, // Skip to: 13726 /* 3924 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SHF_H /* 3928 */ MCD_OPC_FilterValue, 2, 66, 38, // Skip to: 13726 /* 3932 */ MCD_OPC_CheckPredicate, 8, 62, 38, // Skip to: 13726 /* 3936 */ MCD_OPC_Decode, 191, 11, 121, // Opcode: SHF_W /* 3940 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4231 /* 3944 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 3947 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3958 /* 3951 */ MCD_OPC_CheckPredicate, 8, 43, 38, // Skip to: 13726 /* 3955 */ MCD_OPC_Decode, 59, 122, // Opcode: ADDVI_B /* 3958 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3969 /* 3962 */ MCD_OPC_CheckPredicate, 8, 32, 38, // Skip to: 13726 /* 3966 */ MCD_OPC_Decode, 61, 123, // Opcode: ADDVI_H /* 3969 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3980 /* 3973 */ MCD_OPC_CheckPredicate, 8, 21, 38, // Skip to: 13726 /* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W /* 3980 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3991 /* 3984 */ MCD_OPC_CheckPredicate, 8, 10, 38, // Skip to: 13726 /* 3988 */ MCD_OPC_Decode, 60, 125, // Opcode: ADDVI_D /* 3991 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4003 /* 3995 */ MCD_OPC_CheckPredicate, 8, 255, 37, // Skip to: 13726 /* 3999 */ MCD_OPC_Decode, 221, 12, 122, // Opcode: SUBVI_B /* 4003 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4015 /* 4007 */ MCD_OPC_CheckPredicate, 8, 243, 37, // Skip to: 13726 /* 4011 */ MCD_OPC_Decode, 223, 12, 123, // Opcode: SUBVI_H /* 4015 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4027 /* 4019 */ MCD_OPC_CheckPredicate, 8, 231, 37, // Skip to: 13726 /* 4023 */ MCD_OPC_Decode, 224, 12, 124, // Opcode: SUBVI_W /* 4027 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4039 /* 4031 */ MCD_OPC_CheckPredicate, 8, 219, 37, // Skip to: 13726 /* 4035 */ MCD_OPC_Decode, 222, 12, 125, // Opcode: SUBVI_D /* 4039 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4051 /* 4043 */ MCD_OPC_CheckPredicate, 8, 207, 37, // Skip to: 13726 /* 4047 */ MCD_OPC_Decode, 157, 8, 122, // Opcode: MAXI_S_B /* 4051 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4063 /* 4055 */ MCD_OPC_CheckPredicate, 8, 195, 37, // Skip to: 13726 /* 4059 */ MCD_OPC_Decode, 159, 8, 123, // Opcode: MAXI_S_H /* 4063 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4075 /* 4067 */ MCD_OPC_CheckPredicate, 8, 183, 37, // Skip to: 13726 /* 4071 */ MCD_OPC_Decode, 160, 8, 124, // Opcode: MAXI_S_W /* 4075 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4087 /* 4079 */ MCD_OPC_CheckPredicate, 8, 171, 37, // Skip to: 13726 /* 4083 */ MCD_OPC_Decode, 158, 8, 125, // Opcode: MAXI_S_D /* 4087 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4099 /* 4091 */ MCD_OPC_CheckPredicate, 8, 159, 37, // Skip to: 13726 /* 4095 */ MCD_OPC_Decode, 161, 8, 122, // Opcode: MAXI_U_B /* 4099 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4111 /* 4103 */ MCD_OPC_CheckPredicate, 8, 147, 37, // Skip to: 13726 /* 4107 */ MCD_OPC_Decode, 163, 8, 123, // Opcode: MAXI_U_H /* 4111 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4123 /* 4115 */ MCD_OPC_CheckPredicate, 8, 135, 37, // Skip to: 13726 /* 4119 */ MCD_OPC_Decode, 164, 8, 124, // Opcode: MAXI_U_W /* 4123 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4135 /* 4127 */ MCD_OPC_CheckPredicate, 8, 123, 37, // Skip to: 13726 /* 4131 */ MCD_OPC_Decode, 162, 8, 125, // Opcode: MAXI_U_D /* 4135 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4147 /* 4139 */ MCD_OPC_CheckPredicate, 8, 111, 37, // Skip to: 13726 /* 4143 */ MCD_OPC_Decode, 198, 8, 122, // Opcode: MINI_S_B /* 4147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4159 /* 4151 */ MCD_OPC_CheckPredicate, 8, 99, 37, // Skip to: 13726 /* 4155 */ MCD_OPC_Decode, 200, 8, 123, // Opcode: MINI_S_H /* 4159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4171 /* 4163 */ MCD_OPC_CheckPredicate, 8, 87, 37, // Skip to: 13726 /* 4167 */ MCD_OPC_Decode, 201, 8, 124, // Opcode: MINI_S_W /* 4171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4183 /* 4175 */ MCD_OPC_CheckPredicate, 8, 75, 37, // Skip to: 13726 /* 4179 */ MCD_OPC_Decode, 199, 8, 125, // Opcode: MINI_S_D /* 4183 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4195 /* 4187 */ MCD_OPC_CheckPredicate, 8, 63, 37, // Skip to: 13726 /* 4191 */ MCD_OPC_Decode, 202, 8, 122, // Opcode: MINI_U_B /* 4195 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4207 /* 4199 */ MCD_OPC_CheckPredicate, 8, 51, 37, // Skip to: 13726 /* 4203 */ MCD_OPC_Decode, 204, 8, 123, // Opcode: MINI_U_H /* 4207 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4219 /* 4211 */ MCD_OPC_CheckPredicate, 8, 39, 37, // Skip to: 13726 /* 4215 */ MCD_OPC_Decode, 205, 8, 124, // Opcode: MINI_U_W /* 4219 */ MCD_OPC_FilterValue, 23, 31, 37, // Skip to: 13726 /* 4223 */ MCD_OPC_CheckPredicate, 8, 27, 37, // Skip to: 13726 /* 4227 */ MCD_OPC_Decode, 203, 8, 125, // Opcode: MINI_U_D /* 4231 */ MCD_OPC_FilterValue, 7, 37, 1, // Skip to: 4528 /* 4235 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 4238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4250 /* 4242 */ MCD_OPC_CheckPredicate, 8, 8, 37, // Skip to: 13726 /* 4246 */ MCD_OPC_Decode, 230, 2, 122, // Opcode: CEQI_B /* 4250 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4262 /* 4254 */ MCD_OPC_CheckPredicate, 8, 252, 36, // Skip to: 13726 /* 4258 */ MCD_OPC_Decode, 232, 2, 123, // Opcode: CEQI_H /* 4262 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4274 /* 4266 */ MCD_OPC_CheckPredicate, 8, 240, 36, // Skip to: 13726 /* 4270 */ MCD_OPC_Decode, 233, 2, 124, // Opcode: CEQI_W /* 4274 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4286 /* 4278 */ MCD_OPC_CheckPredicate, 8, 228, 36, // Skip to: 13726 /* 4282 */ MCD_OPC_Decode, 231, 2, 125, // Opcode: CEQI_D /* 4286 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4298 /* 4290 */ MCD_OPC_CheckPredicate, 8, 216, 36, // Skip to: 13726 /* 4294 */ MCD_OPC_Decode, 136, 3, 122, // Opcode: CLTI_S_B /* 4298 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4310 /* 4302 */ MCD_OPC_CheckPredicate, 8, 204, 36, // Skip to: 13726 /* 4306 */ MCD_OPC_Decode, 138, 3, 123, // Opcode: CLTI_S_H /* 4310 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4322 /* 4314 */ MCD_OPC_CheckPredicate, 8, 192, 36, // Skip to: 13726 /* 4318 */ MCD_OPC_Decode, 139, 3, 124, // Opcode: CLTI_S_W /* 4322 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4334 /* 4326 */ MCD_OPC_CheckPredicate, 8, 180, 36, // Skip to: 13726 /* 4330 */ MCD_OPC_Decode, 137, 3, 125, // Opcode: CLTI_S_D /* 4334 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4346 /* 4338 */ MCD_OPC_CheckPredicate, 8, 168, 36, // Skip to: 13726 /* 4342 */ MCD_OPC_Decode, 140, 3, 122, // Opcode: CLTI_U_B /* 4346 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4358 /* 4350 */ MCD_OPC_CheckPredicate, 8, 156, 36, // Skip to: 13726 /* 4354 */ MCD_OPC_Decode, 142, 3, 123, // Opcode: CLTI_U_H /* 4358 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4370 /* 4362 */ MCD_OPC_CheckPredicate, 8, 144, 36, // Skip to: 13726 /* 4366 */ MCD_OPC_Decode, 143, 3, 124, // Opcode: CLTI_U_W /* 4370 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4382 /* 4374 */ MCD_OPC_CheckPredicate, 8, 132, 36, // Skip to: 13726 /* 4378 */ MCD_OPC_Decode, 141, 3, 125, // Opcode: CLTI_U_D /* 4382 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4394 /* 4386 */ MCD_OPC_CheckPredicate, 8, 120, 36, // Skip to: 13726 /* 4390 */ MCD_OPC_Decode, 245, 2, 122, // Opcode: CLEI_S_B /* 4394 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4406 /* 4398 */ MCD_OPC_CheckPredicate, 8, 108, 36, // Skip to: 13726 /* 4402 */ MCD_OPC_Decode, 247, 2, 123, // Opcode: CLEI_S_H /* 4406 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4418 /* 4410 */ MCD_OPC_CheckPredicate, 8, 96, 36, // Skip to: 13726 /* 4414 */ MCD_OPC_Decode, 248, 2, 124, // Opcode: CLEI_S_W /* 4418 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4430 /* 4422 */ MCD_OPC_CheckPredicate, 8, 84, 36, // Skip to: 13726 /* 4426 */ MCD_OPC_Decode, 246, 2, 125, // Opcode: CLEI_S_D /* 4430 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4442 /* 4434 */ MCD_OPC_CheckPredicate, 8, 72, 36, // Skip to: 13726 /* 4438 */ MCD_OPC_Decode, 249, 2, 122, // Opcode: CLEI_U_B /* 4442 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4454 /* 4446 */ MCD_OPC_CheckPredicate, 8, 60, 36, // Skip to: 13726 /* 4450 */ MCD_OPC_Decode, 251, 2, 123, // Opcode: CLEI_U_H /* 4454 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4466 /* 4458 */ MCD_OPC_CheckPredicate, 8, 48, 36, // Skip to: 13726 /* 4462 */ MCD_OPC_Decode, 252, 2, 124, // Opcode: CLEI_U_W /* 4466 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4478 /* 4470 */ MCD_OPC_CheckPredicate, 8, 36, 36, // Skip to: 13726 /* 4474 */ MCD_OPC_Decode, 250, 2, 125, // Opcode: CLEI_U_D /* 4478 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4490 /* 4482 */ MCD_OPC_CheckPredicate, 8, 24, 36, // Skip to: 13726 /* 4486 */ MCD_OPC_Decode, 168, 7, 126, // Opcode: LDI_B /* 4490 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4502 /* 4494 */ MCD_OPC_CheckPredicate, 8, 12, 36, // Skip to: 13726 /* 4498 */ MCD_OPC_Decode, 170, 7, 127, // Opcode: LDI_H /* 4502 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 4515 /* 4506 */ MCD_OPC_CheckPredicate, 8, 0, 36, // Skip to: 13726 /* 4510 */ MCD_OPC_Decode, 171, 7, 128, 1, // Opcode: LDI_W /* 4515 */ MCD_OPC_FilterValue, 27, 247, 35, // Skip to: 13726 /* 4519 */ MCD_OPC_CheckPredicate, 8, 243, 35, // Skip to: 13726 /* 4523 */ MCD_OPC_Decode, 169, 7, 129, 1, // Opcode: LDI_D /* 4528 */ MCD_OPC_FilterValue, 9, 61, 2, // Skip to: 5105 /* 4532 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 4535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4548 /* 4539 */ MCD_OPC_CheckPredicate, 8, 223, 35, // Skip to: 13726 /* 4543 */ MCD_OPC_Decode, 230, 11, 130, 1, // Opcode: SLLI_D /* 4548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 4606 /* 4552 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4555 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4567 /* 4559 */ MCD_OPC_CheckPredicate, 8, 203, 35, // Skip to: 13726 /* 4563 */ MCD_OPC_Decode, 232, 11, 124, // Opcode: SLLI_W /* 4567 */ MCD_OPC_FilterValue, 1, 195, 35, // Skip to: 13726 /* 4571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4574 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4587 /* 4578 */ MCD_OPC_CheckPredicate, 8, 184, 35, // Skip to: 13726 /* 4582 */ MCD_OPC_Decode, 231, 11, 131, 1, // Opcode: SLLI_H /* 4587 */ MCD_OPC_FilterValue, 1, 175, 35, // Skip to: 13726 /* 4591 */ MCD_OPC_CheckPredicate, 8, 171, 35, // Skip to: 13726 /* 4595 */ MCD_OPC_CheckField, 19, 1, 0, 165, 35, // Skip to: 13726 /* 4601 */ MCD_OPC_Decode, 229, 11, 132, 1, // Opcode: SLLI_B /* 4606 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4619 /* 4610 */ MCD_OPC_CheckPredicate, 8, 152, 35, // Skip to: 13726 /* 4614 */ MCD_OPC_Decode, 141, 12, 130, 1, // Opcode: SRAI_D /* 4619 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 4677 /* 4623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4638 /* 4630 */ MCD_OPC_CheckPredicate, 8, 132, 35, // Skip to: 13726 /* 4634 */ MCD_OPC_Decode, 143, 12, 124, // Opcode: SRAI_W /* 4638 */ MCD_OPC_FilterValue, 1, 124, 35, // Skip to: 13726 /* 4642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4645 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4658 /* 4649 */ MCD_OPC_CheckPredicate, 8, 113, 35, // Skip to: 13726 /* 4653 */ MCD_OPC_Decode, 142, 12, 131, 1, // Opcode: SRAI_H /* 4658 */ MCD_OPC_FilterValue, 1, 104, 35, // Skip to: 13726 /* 4662 */ MCD_OPC_CheckPredicate, 8, 100, 35, // Skip to: 13726 /* 4666 */ MCD_OPC_CheckField, 19, 1, 0, 94, 35, // Skip to: 13726 /* 4672 */ MCD_OPC_Decode, 140, 12, 132, 1, // Opcode: SRAI_B /* 4677 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 4690 /* 4681 */ MCD_OPC_CheckPredicate, 8, 81, 35, // Skip to: 13726 /* 4685 */ MCD_OPC_Decode, 162, 12, 130, 1, // Opcode: SRLI_D /* 4690 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 4748 /* 4694 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4697 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4709 /* 4701 */ MCD_OPC_CheckPredicate, 8, 61, 35, // Skip to: 13726 /* 4705 */ MCD_OPC_Decode, 164, 12, 124, // Opcode: SRLI_W /* 4709 */ MCD_OPC_FilterValue, 1, 53, 35, // Skip to: 13726 /* 4713 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4716 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4729 /* 4720 */ MCD_OPC_CheckPredicate, 8, 42, 35, // Skip to: 13726 /* 4724 */ MCD_OPC_Decode, 163, 12, 131, 1, // Opcode: SRLI_H /* 4729 */ MCD_OPC_FilterValue, 1, 33, 35, // Skip to: 13726 /* 4733 */ MCD_OPC_CheckPredicate, 8, 29, 35, // Skip to: 13726 /* 4737 */ MCD_OPC_CheckField, 19, 1, 0, 23, 35, // Skip to: 13726 /* 4743 */ MCD_OPC_Decode, 161, 12, 132, 1, // Opcode: SRLI_B /* 4748 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 4761 /* 4752 */ MCD_OPC_CheckPredicate, 8, 10, 35, // Skip to: 13726 /* 4756 */ MCD_OPC_Decode, 199, 1, 130, 1, // Opcode: BCLRI_D /* 4761 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 4819 /* 4765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4768 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4780 /* 4772 */ MCD_OPC_CheckPredicate, 8, 246, 34, // Skip to: 13726 /* 4776 */ MCD_OPC_Decode, 201, 1, 124, // Opcode: BCLRI_W /* 4780 */ MCD_OPC_FilterValue, 1, 238, 34, // Skip to: 13726 /* 4784 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4787 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4800 /* 4791 */ MCD_OPC_CheckPredicate, 8, 227, 34, // Skip to: 13726 /* 4795 */ MCD_OPC_Decode, 200, 1, 131, 1, // Opcode: BCLRI_H /* 4800 */ MCD_OPC_FilterValue, 1, 218, 34, // Skip to: 13726 /* 4804 */ MCD_OPC_CheckPredicate, 8, 214, 34, // Skip to: 13726 /* 4808 */ MCD_OPC_CheckField, 19, 1, 0, 208, 34, // Skip to: 13726 /* 4814 */ MCD_OPC_Decode, 198, 1, 132, 1, // Opcode: BCLRI_B /* 4819 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 4832 /* 4823 */ MCD_OPC_CheckPredicate, 8, 195, 34, // Skip to: 13726 /* 4827 */ MCD_OPC_Decode, 182, 2, 130, 1, // Opcode: BSETI_D /* 4832 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 4890 /* 4836 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4839 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4851 /* 4843 */ MCD_OPC_CheckPredicate, 8, 175, 34, // Skip to: 13726 /* 4847 */ MCD_OPC_Decode, 184, 2, 124, // Opcode: BSETI_W /* 4851 */ MCD_OPC_FilterValue, 1, 167, 34, // Skip to: 13726 /* 4855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4858 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4871 /* 4862 */ MCD_OPC_CheckPredicate, 8, 156, 34, // Skip to: 13726 /* 4866 */ MCD_OPC_Decode, 183, 2, 131, 1, // Opcode: BSETI_H /* 4871 */ MCD_OPC_FilterValue, 1, 147, 34, // Skip to: 13726 /* 4875 */ MCD_OPC_CheckPredicate, 8, 143, 34, // Skip to: 13726 /* 4879 */ MCD_OPC_CheckField, 19, 1, 0, 137, 34, // Skip to: 13726 /* 4885 */ MCD_OPC_Decode, 181, 2, 132, 1, // Opcode: BSETI_B /* 4890 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 4903 /* 4894 */ MCD_OPC_CheckPredicate, 8, 124, 34, // Skip to: 13726 /* 4898 */ MCD_OPC_Decode, 149, 2, 130, 1, // Opcode: BNEGI_D /* 4903 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 4961 /* 4907 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4910 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4922 /* 4914 */ MCD_OPC_CheckPredicate, 8, 104, 34, // Skip to: 13726 /* 4918 */ MCD_OPC_Decode, 151, 2, 124, // Opcode: BNEGI_W /* 4922 */ MCD_OPC_FilterValue, 1, 96, 34, // Skip to: 13726 /* 4926 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 4929 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4942 /* 4933 */ MCD_OPC_CheckPredicate, 8, 85, 34, // Skip to: 13726 /* 4937 */ MCD_OPC_Decode, 150, 2, 131, 1, // Opcode: BNEGI_H /* 4942 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13726 /* 4946 */ MCD_OPC_CheckPredicate, 8, 72, 34, // Skip to: 13726 /* 4950 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13726 /* 4956 */ MCD_OPC_Decode, 148, 2, 132, 1, // Opcode: BNEGI_B /* 4961 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 4974 /* 4965 */ MCD_OPC_CheckPredicate, 8, 53, 34, // Skip to: 13726 /* 4969 */ MCD_OPC_Decode, 234, 1, 133, 1, // Opcode: BINSLI_D /* 4974 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 5033 /* 4978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 4981 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4994 /* 4985 */ MCD_OPC_CheckPredicate, 8, 33, 34, // Skip to: 13726 /* 4989 */ MCD_OPC_Decode, 236, 1, 134, 1, // Opcode: BINSLI_W /* 4994 */ MCD_OPC_FilterValue, 1, 24, 34, // Skip to: 13726 /* 4998 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5001 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5014 /* 5005 */ MCD_OPC_CheckPredicate, 8, 13, 34, // Skip to: 13726 /* 5009 */ MCD_OPC_Decode, 235, 1, 135, 1, // Opcode: BINSLI_H /* 5014 */ MCD_OPC_FilterValue, 1, 4, 34, // Skip to: 13726 /* 5018 */ MCD_OPC_CheckPredicate, 8, 0, 34, // Skip to: 13726 /* 5022 */ MCD_OPC_CheckField, 19, 1, 0, 250, 33, // Skip to: 13726 /* 5028 */ MCD_OPC_Decode, 233, 1, 136, 1, // Opcode: BINSLI_B /* 5033 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5046 /* 5037 */ MCD_OPC_CheckPredicate, 8, 237, 33, // Skip to: 13726 /* 5041 */ MCD_OPC_Decode, 242, 1, 133, 1, // Opcode: BINSRI_D /* 5046 */ MCD_OPC_FilterValue, 15, 228, 33, // Skip to: 13726 /* 5050 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 5053 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5066 /* 5057 */ MCD_OPC_CheckPredicate, 8, 217, 33, // Skip to: 13726 /* 5061 */ MCD_OPC_Decode, 244, 1, 134, 1, // Opcode: BINSRI_W /* 5066 */ MCD_OPC_FilterValue, 1, 208, 33, // Skip to: 13726 /* 5070 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5073 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5086 /* 5077 */ MCD_OPC_CheckPredicate, 8, 197, 33, // Skip to: 13726 /* 5081 */ MCD_OPC_Decode, 243, 1, 135, 1, // Opcode: BINSRI_H /* 5086 */ MCD_OPC_FilterValue, 1, 188, 33, // Skip to: 13726 /* 5090 */ MCD_OPC_CheckPredicate, 8, 184, 33, // Skip to: 13726 /* 5094 */ MCD_OPC_CheckField, 19, 1, 0, 178, 33, // Skip to: 13726 /* 5100 */ MCD_OPC_Decode, 241, 1, 136, 1, // Opcode: BINSRI_B /* 5105 */ MCD_OPC_FilterValue, 10, 31, 1, // Skip to: 5396 /* 5109 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 5112 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5125 /* 5116 */ MCD_OPC_CheckPredicate, 8, 158, 33, // Skip to: 13726 /* 5120 */ MCD_OPC_Decode, 135, 11, 130, 1, // Opcode: SAT_S_D /* 5125 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 5183 /* 5129 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 5132 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5144 /* 5136 */ MCD_OPC_CheckPredicate, 8, 138, 33, // Skip to: 13726 /* 5140 */ MCD_OPC_Decode, 137, 11, 124, // Opcode: SAT_S_W /* 5144 */ MCD_OPC_FilterValue, 1, 130, 33, // Skip to: 13726 /* 5148 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5164 /* 5155 */ MCD_OPC_CheckPredicate, 8, 119, 33, // Skip to: 13726 /* 5159 */ MCD_OPC_Decode, 136, 11, 131, 1, // Opcode: SAT_S_H /* 5164 */ MCD_OPC_FilterValue, 1, 110, 33, // Skip to: 13726 /* 5168 */ MCD_OPC_CheckPredicate, 8, 106, 33, // Skip to: 13726 /* 5172 */ MCD_OPC_CheckField, 19, 1, 0, 100, 33, // Skip to: 13726 /* 5178 */ MCD_OPC_Decode, 134, 11, 132, 1, // Opcode: SAT_S_B /* 5183 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5196 /* 5187 */ MCD_OPC_CheckPredicate, 8, 87, 33, // Skip to: 13726 /* 5191 */ MCD_OPC_Decode, 139, 11, 130, 1, // Opcode: SAT_U_D /* 5196 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 5254 /* 5200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 5203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5215 /* 5207 */ MCD_OPC_CheckPredicate, 8, 67, 33, // Skip to: 13726 /* 5211 */ MCD_OPC_Decode, 141, 11, 124, // Opcode: SAT_U_W /* 5215 */ MCD_OPC_FilterValue, 1, 59, 33, // Skip to: 13726 /* 5219 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5222 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5235 /* 5226 */ MCD_OPC_CheckPredicate, 8, 48, 33, // Skip to: 13726 /* 5230 */ MCD_OPC_Decode, 140, 11, 131, 1, // Opcode: SAT_U_H /* 5235 */ MCD_OPC_FilterValue, 1, 39, 33, // Skip to: 13726 /* 5239 */ MCD_OPC_CheckPredicate, 8, 35, 33, // Skip to: 13726 /* 5243 */ MCD_OPC_CheckField, 19, 1, 0, 29, 33, // Skip to: 13726 /* 5249 */ MCD_OPC_Decode, 138, 11, 132, 1, // Opcode: SAT_U_B /* 5254 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5267 /* 5258 */ MCD_OPC_CheckPredicate, 8, 16, 33, // Skip to: 13726 /* 5262 */ MCD_OPC_Decode, 145, 12, 130, 1, // Opcode: SRARI_D /* 5267 */ MCD_OPC_FilterValue, 5, 54, 0, // Skip to: 5325 /* 5271 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 5274 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5286 /* 5278 */ MCD_OPC_CheckPredicate, 8, 252, 32, // Skip to: 13726 /* 5282 */ MCD_OPC_Decode, 147, 12, 124, // Opcode: SRARI_W /* 5286 */ MCD_OPC_FilterValue, 1, 244, 32, // Skip to: 13726 /* 5290 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5293 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5306 /* 5297 */ MCD_OPC_CheckPredicate, 8, 233, 32, // Skip to: 13726 /* 5301 */ MCD_OPC_Decode, 146, 12, 131, 1, // Opcode: SRARI_H /* 5306 */ MCD_OPC_FilterValue, 1, 224, 32, // Skip to: 13726 /* 5310 */ MCD_OPC_CheckPredicate, 8, 220, 32, // Skip to: 13726 /* 5314 */ MCD_OPC_CheckField, 19, 1, 0, 214, 32, // Skip to: 13726 /* 5320 */ MCD_OPC_Decode, 144, 12, 132, 1, // Opcode: SRARI_B /* 5325 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5338 /* 5329 */ MCD_OPC_CheckPredicate, 8, 201, 32, // Skip to: 13726 /* 5333 */ MCD_OPC_Decode, 166, 12, 130, 1, // Opcode: SRLRI_D /* 5338 */ MCD_OPC_FilterValue, 7, 192, 32, // Skip to: 13726 /* 5342 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... /* 5345 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5357 /* 5349 */ MCD_OPC_CheckPredicate, 8, 181, 32, // Skip to: 13726 /* 5353 */ MCD_OPC_Decode, 168, 12, 124, // Opcode: SRLRI_W /* 5357 */ MCD_OPC_FilterValue, 1, 173, 32, // Skip to: 13726 /* 5361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 5364 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5377 /* 5368 */ MCD_OPC_CheckPredicate, 8, 162, 32, // Skip to: 13726 /* 5372 */ MCD_OPC_Decode, 167, 12, 131, 1, // Opcode: SRLRI_H /* 5377 */ MCD_OPC_FilterValue, 1, 153, 32, // Skip to: 13726 /* 5381 */ MCD_OPC_CheckPredicate, 8, 149, 32, // Skip to: 13726 /* 5385 */ MCD_OPC_CheckField, 19, 1, 0, 143, 32, // Skip to: 13726 /* 5391 */ MCD_OPC_Decode, 165, 12, 132, 1, // Opcode: SRLRI_B /* 5396 */ MCD_OPC_FilterValue, 13, 163, 1, // Skip to: 5819 /* 5400 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 5403 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5416 /* 5407 */ MCD_OPC_CheckPredicate, 8, 123, 32, // Skip to: 13726 /* 5411 */ MCD_OPC_Decode, 235, 11, 137, 1, // Opcode: SLL_B /* 5416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5429 /* 5420 */ MCD_OPC_CheckPredicate, 8, 110, 32, // Skip to: 13726 /* 5424 */ MCD_OPC_Decode, 237, 11, 138, 1, // Opcode: SLL_H /* 5429 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5442 /* 5433 */ MCD_OPC_CheckPredicate, 8, 97, 32, // Skip to: 13726 /* 5437 */ MCD_OPC_Decode, 239, 11, 139, 1, // Opcode: SLL_W /* 5442 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5455 /* 5446 */ MCD_OPC_CheckPredicate, 8, 84, 32, // Skip to: 13726 /* 5450 */ MCD_OPC_Decode, 236, 11, 140, 1, // Opcode: SLL_D /* 5455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5468 /* 5459 */ MCD_OPC_CheckPredicate, 8, 71, 32, // Skip to: 13726 /* 5463 */ MCD_OPC_Decode, 154, 12, 137, 1, // Opcode: SRA_B /* 5468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5481 /* 5472 */ MCD_OPC_CheckPredicate, 8, 58, 32, // Skip to: 13726 /* 5476 */ MCD_OPC_Decode, 156, 12, 138, 1, // Opcode: SRA_H /* 5481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5494 /* 5485 */ MCD_OPC_CheckPredicate, 8, 45, 32, // Skip to: 13726 /* 5489 */ MCD_OPC_Decode, 158, 12, 139, 1, // Opcode: SRA_W /* 5494 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5507 /* 5498 */ MCD_OPC_CheckPredicate, 8, 32, 32, // Skip to: 13726 /* 5502 */ MCD_OPC_Decode, 155, 12, 140, 1, // Opcode: SRA_D /* 5507 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5520 /* 5511 */ MCD_OPC_CheckPredicate, 8, 19, 32, // Skip to: 13726 /* 5515 */ MCD_OPC_Decode, 175, 12, 137, 1, // Opcode: SRL_B /* 5520 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5533 /* 5524 */ MCD_OPC_CheckPredicate, 8, 6, 32, // Skip to: 13726 /* 5528 */ MCD_OPC_Decode, 177, 12, 138, 1, // Opcode: SRL_H /* 5533 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5546 /* 5537 */ MCD_OPC_CheckPredicate, 8, 249, 31, // Skip to: 13726 /* 5541 */ MCD_OPC_Decode, 179, 12, 139, 1, // Opcode: SRL_W /* 5546 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5559 /* 5550 */ MCD_OPC_CheckPredicate, 8, 236, 31, // Skip to: 13726 /* 5554 */ MCD_OPC_Decode, 176, 12, 140, 1, // Opcode: SRL_D /* 5559 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5572 /* 5563 */ MCD_OPC_CheckPredicate, 8, 223, 31, // Skip to: 13726 /* 5567 */ MCD_OPC_Decode, 202, 1, 137, 1, // Opcode: BCLR_B /* 5572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5585 /* 5576 */ MCD_OPC_CheckPredicate, 8, 210, 31, // Skip to: 13726 /* 5580 */ MCD_OPC_Decode, 204, 1, 138, 1, // Opcode: BCLR_H /* 5585 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 5598 /* 5589 */ MCD_OPC_CheckPredicate, 8, 197, 31, // Skip to: 13726 /* 5593 */ MCD_OPC_Decode, 205, 1, 139, 1, // Opcode: BCLR_W /* 5598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5611 /* 5602 */ MCD_OPC_CheckPredicate, 8, 184, 31, // Skip to: 13726 /* 5606 */ MCD_OPC_Decode, 203, 1, 140, 1, // Opcode: BCLR_D /* 5611 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 5624 /* 5615 */ MCD_OPC_CheckPredicate, 8, 171, 31, // Skip to: 13726 /* 5619 */ MCD_OPC_Decode, 185, 2, 137, 1, // Opcode: BSET_B /* 5624 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 5637 /* 5628 */ MCD_OPC_CheckPredicate, 8, 158, 31, // Skip to: 13726 /* 5632 */ MCD_OPC_Decode, 187, 2, 138, 1, // Opcode: BSET_H /* 5637 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 5650 /* 5641 */ MCD_OPC_CheckPredicate, 8, 145, 31, // Skip to: 13726 /* 5645 */ MCD_OPC_Decode, 188, 2, 139, 1, // Opcode: BSET_W /* 5650 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 5663 /* 5654 */ MCD_OPC_CheckPredicate, 8, 132, 31, // Skip to: 13726 /* 5658 */ MCD_OPC_Decode, 186, 2, 140, 1, // Opcode: BSET_D /* 5663 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 5676 /* 5667 */ MCD_OPC_CheckPredicate, 8, 119, 31, // Skip to: 13726 /* 5671 */ MCD_OPC_Decode, 152, 2, 137, 1, // Opcode: BNEG_B /* 5676 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 5689 /* 5680 */ MCD_OPC_CheckPredicate, 8, 106, 31, // Skip to: 13726 /* 5684 */ MCD_OPC_Decode, 154, 2, 138, 1, // Opcode: BNEG_H /* 5689 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 5702 /* 5693 */ MCD_OPC_CheckPredicate, 8, 93, 31, // Skip to: 13726 /* 5697 */ MCD_OPC_Decode, 155, 2, 139, 1, // Opcode: BNEG_W /* 5702 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 5715 /* 5706 */ MCD_OPC_CheckPredicate, 8, 80, 31, // Skip to: 13726 /* 5710 */ MCD_OPC_Decode, 153, 2, 140, 1, // Opcode: BNEG_D /* 5715 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 5728 /* 5719 */ MCD_OPC_CheckPredicate, 8, 67, 31, // Skip to: 13726 /* 5723 */ MCD_OPC_Decode, 237, 1, 141, 1, // Opcode: BINSL_B /* 5728 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 5741 /* 5732 */ MCD_OPC_CheckPredicate, 8, 54, 31, // Skip to: 13726 /* 5736 */ MCD_OPC_Decode, 239, 1, 142, 1, // Opcode: BINSL_H /* 5741 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 5754 /* 5745 */ MCD_OPC_CheckPredicate, 8, 41, 31, // Skip to: 13726 /* 5749 */ MCD_OPC_Decode, 240, 1, 143, 1, // Opcode: BINSL_W /* 5754 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 5767 /* 5758 */ MCD_OPC_CheckPredicate, 8, 28, 31, // Skip to: 13726 /* 5762 */ MCD_OPC_Decode, 238, 1, 144, 1, // Opcode: BINSL_D /* 5767 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 5780 /* 5771 */ MCD_OPC_CheckPredicate, 8, 15, 31, // Skip to: 13726 /* 5775 */ MCD_OPC_Decode, 245, 1, 141, 1, // Opcode: BINSR_B /* 5780 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 5793 /* 5784 */ MCD_OPC_CheckPredicate, 8, 2, 31, // Skip to: 13726 /* 5788 */ MCD_OPC_Decode, 247, 1, 142, 1, // Opcode: BINSR_H /* 5793 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 5806 /* 5797 */ MCD_OPC_CheckPredicate, 8, 245, 30, // Skip to: 13726 /* 5801 */ MCD_OPC_Decode, 248, 1, 143, 1, // Opcode: BINSR_W /* 5806 */ MCD_OPC_FilterValue, 31, 236, 30, // Skip to: 13726 /* 5810 */ MCD_OPC_CheckPredicate, 8, 232, 30, // Skip to: 13726 /* 5814 */ MCD_OPC_Decode, 246, 1, 144, 1, // Opcode: BINSR_D /* 5819 */ MCD_OPC_FilterValue, 14, 159, 1, // Skip to: 6238 /* 5823 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 5826 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5838 /* 5830 */ MCD_OPC_CheckPredicate, 8, 212, 30, // Skip to: 13726 /* 5834 */ MCD_OPC_Decode, 63, 137, 1, // Opcode: ADDV_B /* 5838 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5850 /* 5842 */ MCD_OPC_CheckPredicate, 8, 200, 30, // Skip to: 13726 /* 5846 */ MCD_OPC_Decode, 65, 138, 1, // Opcode: ADDV_H /* 5850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5862 /* 5854 */ MCD_OPC_CheckPredicate, 8, 188, 30, // Skip to: 13726 /* 5858 */ MCD_OPC_Decode, 66, 139, 1, // Opcode: ADDV_W /* 5862 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5874 /* 5866 */ MCD_OPC_CheckPredicate, 8, 176, 30, // Skip to: 13726 /* 5870 */ MCD_OPC_Decode, 64, 140, 1, // Opcode: ADDV_D /* 5874 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 5887 /* 5878 */ MCD_OPC_CheckPredicate, 8, 164, 30, // Skip to: 13726 /* 5882 */ MCD_OPC_Decode, 225, 12, 137, 1, // Opcode: SUBV_B /* 5887 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 5900 /* 5891 */ MCD_OPC_CheckPredicate, 8, 151, 30, // Skip to: 13726 /* 5895 */ MCD_OPC_Decode, 227, 12, 138, 1, // Opcode: SUBV_H /* 5900 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 5913 /* 5904 */ MCD_OPC_CheckPredicate, 8, 138, 30, // Skip to: 13726 /* 5908 */ MCD_OPC_Decode, 228, 12, 139, 1, // Opcode: SUBV_W /* 5913 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 5926 /* 5917 */ MCD_OPC_CheckPredicate, 8, 125, 30, // Skip to: 13726 /* 5921 */ MCD_OPC_Decode, 226, 12, 140, 1, // Opcode: SUBV_D /* 5926 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 5939 /* 5930 */ MCD_OPC_CheckPredicate, 8, 112, 30, // Skip to: 13726 /* 5934 */ MCD_OPC_Decode, 171, 8, 137, 1, // Opcode: MAX_S_B /* 5939 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 5952 /* 5943 */ MCD_OPC_CheckPredicate, 8, 99, 30, // Skip to: 13726 /* 5947 */ MCD_OPC_Decode, 173, 8, 138, 1, // Opcode: MAX_S_H /* 5952 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 5965 /* 5956 */ MCD_OPC_CheckPredicate, 8, 86, 30, // Skip to: 13726 /* 5960 */ MCD_OPC_Decode, 174, 8, 139, 1, // Opcode: MAX_S_W /* 5965 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 5978 /* 5969 */ MCD_OPC_CheckPredicate, 8, 73, 30, // Skip to: 13726 /* 5973 */ MCD_OPC_Decode, 172, 8, 140, 1, // Opcode: MAX_S_D /* 5978 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 5991 /* 5982 */ MCD_OPC_CheckPredicate, 8, 60, 30, // Skip to: 13726 /* 5986 */ MCD_OPC_Decode, 175, 8, 137, 1, // Opcode: MAX_U_B /* 5991 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6004 /* 5995 */ MCD_OPC_CheckPredicate, 8, 47, 30, // Skip to: 13726 /* 5999 */ MCD_OPC_Decode, 177, 8, 138, 1, // Opcode: MAX_U_H /* 6004 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6017 /* 6008 */ MCD_OPC_CheckPredicate, 8, 34, 30, // Skip to: 13726 /* 6012 */ MCD_OPC_Decode, 178, 8, 139, 1, // Opcode: MAX_U_W /* 6017 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6030 /* 6021 */ MCD_OPC_CheckPredicate, 8, 21, 30, // Skip to: 13726 /* 6025 */ MCD_OPC_Decode, 176, 8, 140, 1, // Opcode: MAX_U_D /* 6030 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6043 /* 6034 */ MCD_OPC_CheckPredicate, 8, 8, 30, // Skip to: 13726 /* 6038 */ MCD_OPC_Decode, 212, 8, 137, 1, // Opcode: MIN_S_B /* 6043 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6056 /* 6047 */ MCD_OPC_CheckPredicate, 8, 251, 29, // Skip to: 13726 /* 6051 */ MCD_OPC_Decode, 214, 8, 138, 1, // Opcode: MIN_S_H /* 6056 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6069 /* 6060 */ MCD_OPC_CheckPredicate, 8, 238, 29, // Skip to: 13726 /* 6064 */ MCD_OPC_Decode, 215, 8, 139, 1, // Opcode: MIN_S_W /* 6069 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6082 /* 6073 */ MCD_OPC_CheckPredicate, 8, 225, 29, // Skip to: 13726 /* 6077 */ MCD_OPC_Decode, 213, 8, 140, 1, // Opcode: MIN_S_D /* 6082 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6095 /* 6086 */ MCD_OPC_CheckPredicate, 8, 212, 29, // Skip to: 13726 /* 6090 */ MCD_OPC_Decode, 216, 8, 137, 1, // Opcode: MIN_U_B /* 6095 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6108 /* 6099 */ MCD_OPC_CheckPredicate, 8, 199, 29, // Skip to: 13726 /* 6103 */ MCD_OPC_Decode, 218, 8, 138, 1, // Opcode: MIN_U_H /* 6108 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6121 /* 6112 */ MCD_OPC_CheckPredicate, 8, 186, 29, // Skip to: 13726 /* 6116 */ MCD_OPC_Decode, 219, 8, 139, 1, // Opcode: MIN_U_W /* 6121 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6134 /* 6125 */ MCD_OPC_CheckPredicate, 8, 173, 29, // Skip to: 13726 /* 6129 */ MCD_OPC_Decode, 217, 8, 140, 1, // Opcode: MIN_U_D /* 6134 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6147 /* 6138 */ MCD_OPC_CheckPredicate, 8, 160, 29, // Skip to: 13726 /* 6142 */ MCD_OPC_Decode, 165, 8, 137, 1, // Opcode: MAX_A_B /* 6147 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6160 /* 6151 */ MCD_OPC_CheckPredicate, 8, 147, 29, // Skip to: 13726 /* 6155 */ MCD_OPC_Decode, 167, 8, 138, 1, // Opcode: MAX_A_H /* 6160 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6173 /* 6164 */ MCD_OPC_CheckPredicate, 8, 134, 29, // Skip to: 13726 /* 6168 */ MCD_OPC_Decode, 168, 8, 139, 1, // Opcode: MAX_A_W /* 6173 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6186 /* 6177 */ MCD_OPC_CheckPredicate, 8, 121, 29, // Skip to: 13726 /* 6181 */ MCD_OPC_Decode, 166, 8, 140, 1, // Opcode: MAX_A_D /* 6186 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6199 /* 6190 */ MCD_OPC_CheckPredicate, 8, 108, 29, // Skip to: 13726 /* 6194 */ MCD_OPC_Decode, 206, 8, 137, 1, // Opcode: MIN_A_B /* 6199 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6212 /* 6203 */ MCD_OPC_CheckPredicate, 8, 95, 29, // Skip to: 13726 /* 6207 */ MCD_OPC_Decode, 208, 8, 138, 1, // Opcode: MIN_A_H /* 6212 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6225 /* 6216 */ MCD_OPC_CheckPredicate, 8, 82, 29, // Skip to: 13726 /* 6220 */ MCD_OPC_Decode, 209, 8, 139, 1, // Opcode: MIN_A_W /* 6225 */ MCD_OPC_FilterValue, 31, 73, 29, // Skip to: 13726 /* 6229 */ MCD_OPC_CheckPredicate, 8, 69, 29, // Skip to: 13726 /* 6233 */ MCD_OPC_Decode, 207, 8, 140, 1, // Opcode: MIN_A_D /* 6238 */ MCD_OPC_FilterValue, 15, 7, 1, // Skip to: 6505 /* 6242 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 6245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6258 /* 6249 */ MCD_OPC_CheckPredicate, 8, 49, 29, // Skip to: 13726 /* 6253 */ MCD_OPC_Decode, 234, 2, 137, 1, // Opcode: CEQ_B /* 6258 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6271 /* 6262 */ MCD_OPC_CheckPredicate, 8, 36, 29, // Skip to: 13726 /* 6266 */ MCD_OPC_Decode, 236, 2, 138, 1, // Opcode: CEQ_H /* 6271 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6284 /* 6275 */ MCD_OPC_CheckPredicate, 8, 23, 29, // Skip to: 13726 /* 6279 */ MCD_OPC_Decode, 237, 2, 139, 1, // Opcode: CEQ_W /* 6284 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6297 /* 6288 */ MCD_OPC_CheckPredicate, 8, 10, 29, // Skip to: 13726 /* 6292 */ MCD_OPC_Decode, 235, 2, 140, 1, // Opcode: CEQ_D /* 6297 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6310 /* 6301 */ MCD_OPC_CheckPredicate, 8, 253, 28, // Skip to: 13726 /* 6305 */ MCD_OPC_Decode, 144, 3, 137, 1, // Opcode: CLT_S_B /* 6310 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6323 /* 6314 */ MCD_OPC_CheckPredicate, 8, 240, 28, // Skip to: 13726 /* 6318 */ MCD_OPC_Decode, 146, 3, 138, 1, // Opcode: CLT_S_H /* 6323 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6336 /* 6327 */ MCD_OPC_CheckPredicate, 8, 227, 28, // Skip to: 13726 /* 6331 */ MCD_OPC_Decode, 147, 3, 139, 1, // Opcode: CLT_S_W /* 6336 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6349 /* 6340 */ MCD_OPC_CheckPredicate, 8, 214, 28, // Skip to: 13726 /* 6344 */ MCD_OPC_Decode, 145, 3, 140, 1, // Opcode: CLT_S_D /* 6349 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6362 /* 6353 */ MCD_OPC_CheckPredicate, 8, 201, 28, // Skip to: 13726 /* 6357 */ MCD_OPC_Decode, 148, 3, 137, 1, // Opcode: CLT_U_B /* 6362 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 6375 /* 6366 */ MCD_OPC_CheckPredicate, 8, 188, 28, // Skip to: 13726 /* 6370 */ MCD_OPC_Decode, 150, 3, 138, 1, // Opcode: CLT_U_H /* 6375 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 6388 /* 6379 */ MCD_OPC_CheckPredicate, 8, 175, 28, // Skip to: 13726 /* 6383 */ MCD_OPC_Decode, 151, 3, 139, 1, // Opcode: CLT_U_W /* 6388 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 6401 /* 6392 */ MCD_OPC_CheckPredicate, 8, 162, 28, // Skip to: 13726 /* 6396 */ MCD_OPC_Decode, 149, 3, 140, 1, // Opcode: CLT_U_D /* 6401 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6414 /* 6405 */ MCD_OPC_CheckPredicate, 8, 149, 28, // Skip to: 13726 /* 6409 */ MCD_OPC_Decode, 253, 2, 137, 1, // Opcode: CLE_S_B /* 6414 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6427 /* 6418 */ MCD_OPC_CheckPredicate, 8, 136, 28, // Skip to: 13726 /* 6422 */ MCD_OPC_Decode, 255, 2, 138, 1, // Opcode: CLE_S_H /* 6427 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6440 /* 6431 */ MCD_OPC_CheckPredicate, 8, 123, 28, // Skip to: 13726 /* 6435 */ MCD_OPC_Decode, 128, 3, 139, 1, // Opcode: CLE_S_W /* 6440 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6453 /* 6444 */ MCD_OPC_CheckPredicate, 8, 110, 28, // Skip to: 13726 /* 6448 */ MCD_OPC_Decode, 254, 2, 140, 1, // Opcode: CLE_S_D /* 6453 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6466 /* 6457 */ MCD_OPC_CheckPredicate, 8, 97, 28, // Skip to: 13726 /* 6461 */ MCD_OPC_Decode, 129, 3, 137, 1, // Opcode: CLE_U_B /* 6466 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6479 /* 6470 */ MCD_OPC_CheckPredicate, 8, 84, 28, // Skip to: 13726 /* 6474 */ MCD_OPC_Decode, 131, 3, 138, 1, // Opcode: CLE_U_H /* 6479 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6492 /* 6483 */ MCD_OPC_CheckPredicate, 8, 71, 28, // Skip to: 13726 /* 6487 */ MCD_OPC_Decode, 132, 3, 139, 1, // Opcode: CLE_U_W /* 6492 */ MCD_OPC_FilterValue, 23, 62, 28, // Skip to: 13726 /* 6496 */ MCD_OPC_CheckPredicate, 8, 58, 28, // Skip to: 13726 /* 6500 */ MCD_OPC_Decode, 130, 3, 140, 1, // Opcode: CLE_U_D /* 6505 */ MCD_OPC_FilterValue, 16, 147, 1, // Skip to: 6912 /* 6509 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 6512 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6524 /* 6516 */ MCD_OPC_CheckPredicate, 8, 38, 28, // Skip to: 13726 /* 6520 */ MCD_OPC_Decode, 68, 137, 1, // Opcode: ADD_A_B /* 6524 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6536 /* 6528 */ MCD_OPC_CheckPredicate, 8, 26, 28, // Skip to: 13726 /* 6532 */ MCD_OPC_Decode, 70, 138, 1, // Opcode: ADD_A_H /* 6536 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6548 /* 6540 */ MCD_OPC_CheckPredicate, 8, 14, 28, // Skip to: 13726 /* 6544 */ MCD_OPC_Decode, 71, 139, 1, // Opcode: ADD_A_W /* 6548 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6560 /* 6552 */ MCD_OPC_CheckPredicate, 8, 2, 28, // Skip to: 13726 /* 6556 */ MCD_OPC_Decode, 69, 140, 1, // Opcode: ADD_A_D /* 6560 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6572 /* 6564 */ MCD_OPC_CheckPredicate, 8, 246, 27, // Skip to: 13726 /* 6568 */ MCD_OPC_Decode, 40, 137, 1, // Opcode: ADDS_A_B /* 6572 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6584 /* 6576 */ MCD_OPC_CheckPredicate, 8, 234, 27, // Skip to: 13726 /* 6580 */ MCD_OPC_Decode, 42, 138, 1, // Opcode: ADDS_A_H /* 6584 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6596 /* 6588 */ MCD_OPC_CheckPredicate, 8, 222, 27, // Skip to: 13726 /* 6592 */ MCD_OPC_Decode, 43, 139, 1, // Opcode: ADDS_A_W /* 6596 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6608 /* 6600 */ MCD_OPC_CheckPredicate, 8, 210, 27, // Skip to: 13726 /* 6604 */ MCD_OPC_Decode, 41, 140, 1, // Opcode: ADDS_A_D /* 6608 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6620 /* 6612 */ MCD_OPC_CheckPredicate, 8, 198, 27, // Skip to: 13726 /* 6616 */ MCD_OPC_Decode, 44, 137, 1, // Opcode: ADDS_S_B /* 6620 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6632 /* 6624 */ MCD_OPC_CheckPredicate, 8, 186, 27, // Skip to: 13726 /* 6628 */ MCD_OPC_Decode, 46, 138, 1, // Opcode: ADDS_S_H /* 6632 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6644 /* 6636 */ MCD_OPC_CheckPredicate, 8, 174, 27, // Skip to: 13726 /* 6640 */ MCD_OPC_Decode, 47, 139, 1, // Opcode: ADDS_S_W /* 6644 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6656 /* 6648 */ MCD_OPC_CheckPredicate, 8, 162, 27, // Skip to: 13726 /* 6652 */ MCD_OPC_Decode, 45, 140, 1, // Opcode: ADDS_S_D /* 6656 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6668 /* 6660 */ MCD_OPC_CheckPredicate, 8, 150, 27, // Skip to: 13726 /* 6664 */ MCD_OPC_Decode, 48, 137, 1, // Opcode: ADDS_U_B /* 6668 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6680 /* 6672 */ MCD_OPC_CheckPredicate, 8, 138, 27, // Skip to: 13726 /* 6676 */ MCD_OPC_Decode, 50, 138, 1, // Opcode: ADDS_U_H /* 6680 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6692 /* 6684 */ MCD_OPC_CheckPredicate, 8, 126, 27, // Skip to: 13726 /* 6688 */ MCD_OPC_Decode, 51, 139, 1, // Opcode: ADDS_U_W /* 6692 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6704 /* 6696 */ MCD_OPC_CheckPredicate, 8, 114, 27, // Skip to: 13726 /* 6700 */ MCD_OPC_Decode, 49, 140, 1, // Opcode: ADDS_U_D /* 6704 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 6717 /* 6708 */ MCD_OPC_CheckPredicate, 8, 102, 27, // Skip to: 13726 /* 6712 */ MCD_OPC_Decode, 147, 1, 137, 1, // Opcode: AVE_S_B /* 6717 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 6730 /* 6721 */ MCD_OPC_CheckPredicate, 8, 89, 27, // Skip to: 13726 /* 6725 */ MCD_OPC_Decode, 149, 1, 138, 1, // Opcode: AVE_S_H /* 6730 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 6743 /* 6734 */ MCD_OPC_CheckPredicate, 8, 76, 27, // Skip to: 13726 /* 6738 */ MCD_OPC_Decode, 150, 1, 139, 1, // Opcode: AVE_S_W /* 6743 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 6756 /* 6747 */ MCD_OPC_CheckPredicate, 8, 63, 27, // Skip to: 13726 /* 6751 */ MCD_OPC_Decode, 148, 1, 140, 1, // Opcode: AVE_S_D /* 6756 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 6769 /* 6760 */ MCD_OPC_CheckPredicate, 8, 50, 27, // Skip to: 13726 /* 6764 */ MCD_OPC_Decode, 151, 1, 137, 1, // Opcode: AVE_U_B /* 6769 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 6782 /* 6773 */ MCD_OPC_CheckPredicate, 8, 37, 27, // Skip to: 13726 /* 6777 */ MCD_OPC_Decode, 153, 1, 138, 1, // Opcode: AVE_U_H /* 6782 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 6795 /* 6786 */ MCD_OPC_CheckPredicate, 8, 24, 27, // Skip to: 13726 /* 6790 */ MCD_OPC_Decode, 154, 1, 139, 1, // Opcode: AVE_U_W /* 6795 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 6808 /* 6799 */ MCD_OPC_CheckPredicate, 8, 11, 27, // Skip to: 13726 /* 6803 */ MCD_OPC_Decode, 152, 1, 140, 1, // Opcode: AVE_U_D /* 6808 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 6821 /* 6812 */ MCD_OPC_CheckPredicate, 8, 254, 26, // Skip to: 13726 /* 6816 */ MCD_OPC_Decode, 139, 1, 137, 1, // Opcode: AVER_S_B /* 6821 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 6834 /* 6825 */ MCD_OPC_CheckPredicate, 8, 241, 26, // Skip to: 13726 /* 6829 */ MCD_OPC_Decode, 141, 1, 138, 1, // Opcode: AVER_S_H /* 6834 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 6847 /* 6838 */ MCD_OPC_CheckPredicate, 8, 228, 26, // Skip to: 13726 /* 6842 */ MCD_OPC_Decode, 142, 1, 139, 1, // Opcode: AVER_S_W /* 6847 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 6860 /* 6851 */ MCD_OPC_CheckPredicate, 8, 215, 26, // Skip to: 13726 /* 6855 */ MCD_OPC_Decode, 140, 1, 140, 1, // Opcode: AVER_S_D /* 6860 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 6873 /* 6864 */ MCD_OPC_CheckPredicate, 8, 202, 26, // Skip to: 13726 /* 6868 */ MCD_OPC_Decode, 143, 1, 137, 1, // Opcode: AVER_U_B /* 6873 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 6886 /* 6877 */ MCD_OPC_CheckPredicate, 8, 189, 26, // Skip to: 13726 /* 6881 */ MCD_OPC_Decode, 145, 1, 138, 1, // Opcode: AVER_U_H /* 6886 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 6899 /* 6890 */ MCD_OPC_CheckPredicate, 8, 176, 26, // Skip to: 13726 /* 6894 */ MCD_OPC_Decode, 146, 1, 139, 1, // Opcode: AVER_U_W /* 6899 */ MCD_OPC_FilterValue, 31, 167, 26, // Skip to: 13726 /* 6903 */ MCD_OPC_CheckPredicate, 8, 163, 26, // Skip to: 13726 /* 6907 */ MCD_OPC_Decode, 144, 1, 140, 1, // Opcode: AVER_U_D /* 6912 */ MCD_OPC_FilterValue, 17, 51, 1, // Skip to: 7223 /* 6916 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 6919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6932 /* 6923 */ MCD_OPC_CheckPredicate, 8, 143, 26, // Skip to: 13726 /* 6927 */ MCD_OPC_Decode, 206, 12, 137, 1, // Opcode: SUBS_S_B /* 6932 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6945 /* 6936 */ MCD_OPC_CheckPredicate, 8, 130, 26, // Skip to: 13726 /* 6940 */ MCD_OPC_Decode, 208, 12, 138, 1, // Opcode: SUBS_S_H /* 6945 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6958 /* 6949 */ MCD_OPC_CheckPredicate, 8, 117, 26, // Skip to: 13726 /* 6953 */ MCD_OPC_Decode, 209, 12, 139, 1, // Opcode: SUBS_S_W /* 6958 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6971 /* 6962 */ MCD_OPC_CheckPredicate, 8, 104, 26, // Skip to: 13726 /* 6966 */ MCD_OPC_Decode, 207, 12, 140, 1, // Opcode: SUBS_S_D /* 6971 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 6984 /* 6975 */ MCD_OPC_CheckPredicate, 8, 91, 26, // Skip to: 13726 /* 6979 */ MCD_OPC_Decode, 210, 12, 137, 1, // Opcode: SUBS_U_B /* 6984 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 6997 /* 6988 */ MCD_OPC_CheckPredicate, 8, 78, 26, // Skip to: 13726 /* 6992 */ MCD_OPC_Decode, 212, 12, 138, 1, // Opcode: SUBS_U_H /* 6997 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7010 /* 7001 */ MCD_OPC_CheckPredicate, 8, 65, 26, // Skip to: 13726 /* 7005 */ MCD_OPC_Decode, 213, 12, 139, 1, // Opcode: SUBS_U_W /* 7010 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7023 /* 7014 */ MCD_OPC_CheckPredicate, 8, 52, 26, // Skip to: 13726 /* 7018 */ MCD_OPC_Decode, 211, 12, 140, 1, // Opcode: SUBS_U_D /* 7023 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7036 /* 7027 */ MCD_OPC_CheckPredicate, 8, 39, 26, // Skip to: 13726 /* 7031 */ MCD_OPC_Decode, 198, 12, 137, 1, // Opcode: SUBSUS_U_B /* 7036 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7049 /* 7040 */ MCD_OPC_CheckPredicate, 8, 26, 26, // Skip to: 13726 /* 7044 */ MCD_OPC_Decode, 200, 12, 138, 1, // Opcode: SUBSUS_U_H /* 7049 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7062 /* 7053 */ MCD_OPC_CheckPredicate, 8, 13, 26, // Skip to: 13726 /* 7057 */ MCD_OPC_Decode, 201, 12, 139, 1, // Opcode: SUBSUS_U_W /* 7062 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7075 /* 7066 */ MCD_OPC_CheckPredicate, 8, 0, 26, // Skip to: 13726 /* 7070 */ MCD_OPC_Decode, 199, 12, 140, 1, // Opcode: SUBSUS_U_D /* 7075 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7088 /* 7079 */ MCD_OPC_CheckPredicate, 8, 243, 25, // Skip to: 13726 /* 7083 */ MCD_OPC_Decode, 202, 12, 137, 1, // Opcode: SUBSUU_S_B /* 7088 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7101 /* 7092 */ MCD_OPC_CheckPredicate, 8, 230, 25, // Skip to: 13726 /* 7096 */ MCD_OPC_Decode, 204, 12, 138, 1, // Opcode: SUBSUU_S_H /* 7101 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7114 /* 7105 */ MCD_OPC_CheckPredicate, 8, 217, 25, // Skip to: 13726 /* 7109 */ MCD_OPC_Decode, 205, 12, 139, 1, // Opcode: SUBSUU_S_W /* 7114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7127 /* 7118 */ MCD_OPC_CheckPredicate, 8, 204, 25, // Skip to: 13726 /* 7122 */ MCD_OPC_Decode, 203, 12, 140, 1, // Opcode: SUBSUU_S_D /* 7127 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7139 /* 7131 */ MCD_OPC_CheckPredicate, 8, 191, 25, // Skip to: 13726 /* 7135 */ MCD_OPC_Decode, 97, 137, 1, // Opcode: ASUB_S_B /* 7139 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7151 /* 7143 */ MCD_OPC_CheckPredicate, 8, 179, 25, // Skip to: 13726 /* 7147 */ MCD_OPC_Decode, 99, 138, 1, // Opcode: ASUB_S_H /* 7151 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7163 /* 7155 */ MCD_OPC_CheckPredicate, 8, 167, 25, // Skip to: 13726 /* 7159 */ MCD_OPC_Decode, 100, 139, 1, // Opcode: ASUB_S_W /* 7163 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7175 /* 7167 */ MCD_OPC_CheckPredicate, 8, 155, 25, // Skip to: 13726 /* 7171 */ MCD_OPC_Decode, 98, 140, 1, // Opcode: ASUB_S_D /* 7175 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7187 /* 7179 */ MCD_OPC_CheckPredicate, 8, 143, 25, // Skip to: 13726 /* 7183 */ MCD_OPC_Decode, 101, 137, 1, // Opcode: ASUB_U_B /* 7187 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7199 /* 7191 */ MCD_OPC_CheckPredicate, 8, 131, 25, // Skip to: 13726 /* 7195 */ MCD_OPC_Decode, 103, 138, 1, // Opcode: ASUB_U_H /* 7199 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7211 /* 7203 */ MCD_OPC_CheckPredicate, 8, 119, 25, // Skip to: 13726 /* 7207 */ MCD_OPC_Decode, 104, 139, 1, // Opcode: ASUB_U_W /* 7211 */ MCD_OPC_FilterValue, 23, 111, 25, // Skip to: 13726 /* 7215 */ MCD_OPC_CheckPredicate, 8, 107, 25, // Skip to: 13726 /* 7219 */ MCD_OPC_Decode, 102, 140, 1, // Opcode: ASUB_U_D /* 7223 */ MCD_OPC_FilterValue, 18, 111, 1, // Skip to: 7594 /* 7227 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 7230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7243 /* 7234 */ MCD_OPC_CheckPredicate, 8, 88, 25, // Skip to: 13726 /* 7238 */ MCD_OPC_Decode, 213, 9, 137, 1, // Opcode: MULV_B /* 7243 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7256 /* 7247 */ MCD_OPC_CheckPredicate, 8, 75, 25, // Skip to: 13726 /* 7251 */ MCD_OPC_Decode, 215, 9, 138, 1, // Opcode: MULV_H /* 7256 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7269 /* 7260 */ MCD_OPC_CheckPredicate, 8, 62, 25, // Skip to: 13726 /* 7264 */ MCD_OPC_Decode, 216, 9, 139, 1, // Opcode: MULV_W /* 7269 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7282 /* 7273 */ MCD_OPC_CheckPredicate, 8, 49, 25, // Skip to: 13726 /* 7277 */ MCD_OPC_Decode, 214, 9, 140, 1, // Opcode: MULV_D /* 7282 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7295 /* 7286 */ MCD_OPC_CheckPredicate, 8, 36, 25, // Skip to: 13726 /* 7290 */ MCD_OPC_Decode, 138, 8, 141, 1, // Opcode: MADDV_B /* 7295 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7308 /* 7299 */ MCD_OPC_CheckPredicate, 8, 23, 25, // Skip to: 13726 /* 7303 */ MCD_OPC_Decode, 140, 8, 142, 1, // Opcode: MADDV_H /* 7308 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7321 /* 7312 */ MCD_OPC_CheckPredicate, 8, 10, 25, // Skip to: 13726 /* 7316 */ MCD_OPC_Decode, 141, 8, 143, 1, // Opcode: MADDV_W /* 7321 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7334 /* 7325 */ MCD_OPC_CheckPredicate, 8, 253, 24, // Skip to: 13726 /* 7329 */ MCD_OPC_Decode, 139, 8, 144, 1, // Opcode: MADDV_D /* 7334 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7347 /* 7338 */ MCD_OPC_CheckPredicate, 8, 240, 24, // Skip to: 13726 /* 7342 */ MCD_OPC_Decode, 156, 9, 141, 1, // Opcode: MSUBV_B /* 7347 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7360 /* 7351 */ MCD_OPC_CheckPredicate, 8, 227, 24, // Skip to: 13726 /* 7355 */ MCD_OPC_Decode, 158, 9, 142, 1, // Opcode: MSUBV_H /* 7360 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7373 /* 7364 */ MCD_OPC_CheckPredicate, 8, 214, 24, // Skip to: 13726 /* 7368 */ MCD_OPC_Decode, 159, 9, 143, 1, // Opcode: MSUBV_W /* 7373 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7386 /* 7377 */ MCD_OPC_CheckPredicate, 8, 201, 24, // Skip to: 13726 /* 7381 */ MCD_OPC_Decode, 157, 9, 144, 1, // Opcode: MSUBV_D /* 7386 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 7399 /* 7390 */ MCD_OPC_CheckPredicate, 8, 188, 24, // Skip to: 13726 /* 7394 */ MCD_OPC_Decode, 185, 4, 137, 1, // Opcode: DIV_S_B /* 7399 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7412 /* 7403 */ MCD_OPC_CheckPredicate, 8, 175, 24, // Skip to: 13726 /* 7407 */ MCD_OPC_Decode, 187, 4, 138, 1, // Opcode: DIV_S_H /* 7412 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7425 /* 7416 */ MCD_OPC_CheckPredicate, 8, 162, 24, // Skip to: 13726 /* 7420 */ MCD_OPC_Decode, 188, 4, 139, 1, // Opcode: DIV_S_W /* 7425 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7438 /* 7429 */ MCD_OPC_CheckPredicate, 8, 149, 24, // Skip to: 13726 /* 7433 */ MCD_OPC_Decode, 186, 4, 140, 1, // Opcode: DIV_S_D /* 7438 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 7451 /* 7442 */ MCD_OPC_CheckPredicate, 8, 136, 24, // Skip to: 13726 /* 7446 */ MCD_OPC_Decode, 189, 4, 137, 1, // Opcode: DIV_U_B /* 7451 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7464 /* 7455 */ MCD_OPC_CheckPredicate, 8, 123, 24, // Skip to: 13726 /* 7459 */ MCD_OPC_Decode, 191, 4, 138, 1, // Opcode: DIV_U_H /* 7464 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7477 /* 7468 */ MCD_OPC_CheckPredicate, 8, 110, 24, // Skip to: 13726 /* 7472 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: DIV_U_W /* 7477 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 7490 /* 7481 */ MCD_OPC_CheckPredicate, 8, 97, 24, // Skip to: 13726 /* 7485 */ MCD_OPC_Decode, 190, 4, 140, 1, // Opcode: DIV_U_D /* 7490 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 7503 /* 7494 */ MCD_OPC_CheckPredicate, 8, 84, 24, // Skip to: 13726 /* 7498 */ MCD_OPC_Decode, 225, 8, 137, 1, // Opcode: MOD_S_B /* 7503 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 7516 /* 7507 */ MCD_OPC_CheckPredicate, 8, 71, 24, // Skip to: 13726 /* 7511 */ MCD_OPC_Decode, 227, 8, 138, 1, // Opcode: MOD_S_H /* 7516 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 7529 /* 7520 */ MCD_OPC_CheckPredicate, 8, 58, 24, // Skip to: 13726 /* 7524 */ MCD_OPC_Decode, 228, 8, 139, 1, // Opcode: MOD_S_W /* 7529 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 7542 /* 7533 */ MCD_OPC_CheckPredicate, 8, 45, 24, // Skip to: 13726 /* 7537 */ MCD_OPC_Decode, 226, 8, 140, 1, // Opcode: MOD_S_D /* 7542 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 7555 /* 7546 */ MCD_OPC_CheckPredicate, 8, 32, 24, // Skip to: 13726 /* 7550 */ MCD_OPC_Decode, 229, 8, 137, 1, // Opcode: MOD_U_B /* 7555 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 7568 /* 7559 */ MCD_OPC_CheckPredicate, 8, 19, 24, // Skip to: 13726 /* 7563 */ MCD_OPC_Decode, 231, 8, 138, 1, // Opcode: MOD_U_H /* 7568 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 7581 /* 7572 */ MCD_OPC_CheckPredicate, 8, 6, 24, // Skip to: 13726 /* 7576 */ MCD_OPC_Decode, 232, 8, 139, 1, // Opcode: MOD_U_W /* 7581 */ MCD_OPC_FilterValue, 31, 253, 23, // Skip to: 13726 /* 7585 */ MCD_OPC_CheckPredicate, 8, 249, 23, // Skip to: 13726 /* 7589 */ MCD_OPC_Decode, 230, 8, 140, 1, // Opcode: MOD_U_D /* 7594 */ MCD_OPC_FilterValue, 19, 237, 0, // Skip to: 7835 /* 7598 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 7601 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7614 /* 7605 */ MCD_OPC_CheckPredicate, 8, 229, 23, // Skip to: 13726 /* 7609 */ MCD_OPC_Decode, 212, 4, 145, 1, // Opcode: DOTP_S_H /* 7614 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7627 /* 7618 */ MCD_OPC_CheckPredicate, 8, 216, 23, // Skip to: 13726 /* 7622 */ MCD_OPC_Decode, 213, 4, 146, 1, // Opcode: DOTP_S_W /* 7627 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7640 /* 7631 */ MCD_OPC_CheckPredicate, 8, 203, 23, // Skip to: 13726 /* 7635 */ MCD_OPC_Decode, 211, 4, 147, 1, // Opcode: DOTP_S_D /* 7640 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7653 /* 7644 */ MCD_OPC_CheckPredicate, 8, 190, 23, // Skip to: 13726 /* 7648 */ MCD_OPC_Decode, 215, 4, 145, 1, // Opcode: DOTP_U_H /* 7653 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7666 /* 7657 */ MCD_OPC_CheckPredicate, 8, 177, 23, // Skip to: 13726 /* 7661 */ MCD_OPC_Decode, 216, 4, 146, 1, // Opcode: DOTP_U_W /* 7666 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7679 /* 7670 */ MCD_OPC_CheckPredicate, 8, 164, 23, // Skip to: 13726 /* 7674 */ MCD_OPC_Decode, 214, 4, 147, 1, // Opcode: DOTP_U_D /* 7679 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7692 /* 7683 */ MCD_OPC_CheckPredicate, 8, 151, 23, // Skip to: 13726 /* 7687 */ MCD_OPC_Decode, 218, 4, 148, 1, // Opcode: DPADD_S_H /* 7692 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7705 /* 7696 */ MCD_OPC_CheckPredicate, 8, 138, 23, // Skip to: 13726 /* 7700 */ MCD_OPC_Decode, 219, 4, 149, 1, // Opcode: DPADD_S_W /* 7705 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7718 /* 7709 */ MCD_OPC_CheckPredicate, 8, 125, 23, // Skip to: 13726 /* 7713 */ MCD_OPC_Decode, 217, 4, 150, 1, // Opcode: DPADD_S_D /* 7718 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7731 /* 7722 */ MCD_OPC_CheckPredicate, 8, 112, 23, // Skip to: 13726 /* 7726 */ MCD_OPC_Decode, 221, 4, 148, 1, // Opcode: DPADD_U_H /* 7731 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7744 /* 7735 */ MCD_OPC_CheckPredicate, 8, 99, 23, // Skip to: 13726 /* 7739 */ MCD_OPC_Decode, 222, 4, 149, 1, // Opcode: DPADD_U_W /* 7744 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 7757 /* 7748 */ MCD_OPC_CheckPredicate, 8, 86, 23, // Skip to: 13726 /* 7752 */ MCD_OPC_Decode, 220, 4, 150, 1, // Opcode: DPADD_U_D /* 7757 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 7770 /* 7761 */ MCD_OPC_CheckPredicate, 8, 73, 23, // Skip to: 13726 /* 7765 */ MCD_OPC_Decode, 237, 4, 148, 1, // Opcode: DPSUB_S_H /* 7770 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 7783 /* 7774 */ MCD_OPC_CheckPredicate, 8, 60, 23, // Skip to: 13726 /* 7778 */ MCD_OPC_Decode, 238, 4, 149, 1, // Opcode: DPSUB_S_W /* 7783 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 7796 /* 7787 */ MCD_OPC_CheckPredicate, 8, 47, 23, // Skip to: 13726 /* 7791 */ MCD_OPC_Decode, 236, 4, 150, 1, // Opcode: DPSUB_S_D /* 7796 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 7809 /* 7800 */ MCD_OPC_CheckPredicate, 8, 34, 23, // Skip to: 13726 /* 7804 */ MCD_OPC_Decode, 240, 4, 148, 1, // Opcode: DPSUB_U_H /* 7809 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 7822 /* 7813 */ MCD_OPC_CheckPredicate, 8, 21, 23, // Skip to: 13726 /* 7817 */ MCD_OPC_Decode, 241, 4, 149, 1, // Opcode: DPSUB_U_W /* 7822 */ MCD_OPC_FilterValue, 23, 12, 23, // Skip to: 13726 /* 7826 */ MCD_OPC_CheckPredicate, 8, 8, 23, // Skip to: 13726 /* 7830 */ MCD_OPC_Decode, 239, 4, 150, 1, // Opcode: DPSUB_U_D /* 7835 */ MCD_OPC_FilterValue, 20, 163, 1, // Skip to: 8258 /* 7839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 7842 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7855 /* 7846 */ MCD_OPC_CheckPredicate, 8, 244, 22, // Skip to: 13726 /* 7850 */ MCD_OPC_Decode, 221, 11, 151, 1, // Opcode: SLD_B /* 7855 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7868 /* 7859 */ MCD_OPC_CheckPredicate, 8, 231, 22, // Skip to: 13726 /* 7863 */ MCD_OPC_Decode, 223, 11, 152, 1, // Opcode: SLD_H /* 7868 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7881 /* 7872 */ MCD_OPC_CheckPredicate, 8, 218, 22, // Skip to: 13726 /* 7876 */ MCD_OPC_Decode, 224, 11, 153, 1, // Opcode: SLD_W /* 7881 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7894 /* 7885 */ MCD_OPC_CheckPredicate, 8, 205, 22, // Skip to: 13726 /* 7889 */ MCD_OPC_Decode, 222, 11, 154, 1, // Opcode: SLD_D /* 7894 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7907 /* 7898 */ MCD_OPC_CheckPredicate, 8, 192, 22, // Skip to: 13726 /* 7902 */ MCD_OPC_Decode, 135, 12, 155, 1, // Opcode: SPLAT_B /* 7907 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7920 /* 7911 */ MCD_OPC_CheckPredicate, 8, 179, 22, // Skip to: 13726 /* 7915 */ MCD_OPC_Decode, 137, 12, 156, 1, // Opcode: SPLAT_H /* 7920 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7933 /* 7924 */ MCD_OPC_CheckPredicate, 8, 166, 22, // Skip to: 13726 /* 7928 */ MCD_OPC_Decode, 138, 12, 157, 1, // Opcode: SPLAT_W /* 7933 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7946 /* 7937 */ MCD_OPC_CheckPredicate, 8, 153, 22, // Skip to: 13726 /* 7941 */ MCD_OPC_Decode, 136, 12, 158, 1, // Opcode: SPLAT_D /* 7946 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7959 /* 7950 */ MCD_OPC_CheckPredicate, 8, 140, 22, // Skip to: 13726 /* 7954 */ MCD_OPC_Decode, 149, 10, 137, 1, // Opcode: PCKEV_B /* 7959 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7972 /* 7963 */ MCD_OPC_CheckPredicate, 8, 127, 22, // Skip to: 13726 /* 7967 */ MCD_OPC_Decode, 151, 10, 138, 1, // Opcode: PCKEV_H /* 7972 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7985 /* 7976 */ MCD_OPC_CheckPredicate, 8, 114, 22, // Skip to: 13726 /* 7980 */ MCD_OPC_Decode, 152, 10, 139, 1, // Opcode: PCKEV_W /* 7985 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7998 /* 7989 */ MCD_OPC_CheckPredicate, 8, 101, 22, // Skip to: 13726 /* 7993 */ MCD_OPC_Decode, 150, 10, 140, 1, // Opcode: PCKEV_D /* 7998 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8011 /* 8002 */ MCD_OPC_CheckPredicate, 8, 88, 22, // Skip to: 13726 /* 8006 */ MCD_OPC_Decode, 153, 10, 137, 1, // Opcode: PCKOD_B /* 8011 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 8024 /* 8015 */ MCD_OPC_CheckPredicate, 8, 75, 22, // Skip to: 13726 /* 8019 */ MCD_OPC_Decode, 155, 10, 138, 1, // Opcode: PCKOD_H /* 8024 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 8037 /* 8028 */ MCD_OPC_CheckPredicate, 8, 62, 22, // Skip to: 13726 /* 8032 */ MCD_OPC_Decode, 156, 10, 139, 1, // Opcode: PCKOD_W /* 8037 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 8050 /* 8041 */ MCD_OPC_CheckPredicate, 8, 49, 22, // Skip to: 13726 /* 8045 */ MCD_OPC_Decode, 154, 10, 140, 1, // Opcode: PCKOD_D /* 8050 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8063 /* 8054 */ MCD_OPC_CheckPredicate, 8, 36, 22, // Skip to: 13726 /* 8058 */ MCD_OPC_Decode, 216, 6, 137, 1, // Opcode: ILVL_B /* 8063 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8076 /* 8067 */ MCD_OPC_CheckPredicate, 8, 23, 22, // Skip to: 13726 /* 8071 */ MCD_OPC_Decode, 218, 6, 138, 1, // Opcode: ILVL_H /* 8076 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8089 /* 8080 */ MCD_OPC_CheckPredicate, 8, 10, 22, // Skip to: 13726 /* 8084 */ MCD_OPC_Decode, 219, 6, 139, 1, // Opcode: ILVL_W /* 8089 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8102 /* 8093 */ MCD_OPC_CheckPredicate, 8, 253, 21, // Skip to: 13726 /* 8097 */ MCD_OPC_Decode, 217, 6, 140, 1, // Opcode: ILVL_D /* 8102 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8115 /* 8106 */ MCD_OPC_CheckPredicate, 8, 240, 21, // Skip to: 13726 /* 8110 */ MCD_OPC_Decode, 224, 6, 137, 1, // Opcode: ILVR_B /* 8115 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8128 /* 8119 */ MCD_OPC_CheckPredicate, 8, 227, 21, // Skip to: 13726 /* 8123 */ MCD_OPC_Decode, 226, 6, 138, 1, // Opcode: ILVR_H /* 8128 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8141 /* 8132 */ MCD_OPC_CheckPredicate, 8, 214, 21, // Skip to: 13726 /* 8136 */ MCD_OPC_Decode, 227, 6, 139, 1, // Opcode: ILVR_W /* 8141 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8154 /* 8145 */ MCD_OPC_CheckPredicate, 8, 201, 21, // Skip to: 13726 /* 8149 */ MCD_OPC_Decode, 225, 6, 140, 1, // Opcode: ILVR_D /* 8154 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 8167 /* 8158 */ MCD_OPC_CheckPredicate, 8, 188, 21, // Skip to: 13726 /* 8162 */ MCD_OPC_Decode, 212, 6, 137, 1, // Opcode: ILVEV_B /* 8167 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8180 /* 8171 */ MCD_OPC_CheckPredicate, 8, 175, 21, // Skip to: 13726 /* 8175 */ MCD_OPC_Decode, 214, 6, 138, 1, // Opcode: ILVEV_H /* 8180 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8193 /* 8184 */ MCD_OPC_CheckPredicate, 8, 162, 21, // Skip to: 13726 /* 8188 */ MCD_OPC_Decode, 215, 6, 139, 1, // Opcode: ILVEV_W /* 8193 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8206 /* 8197 */ MCD_OPC_CheckPredicate, 8, 149, 21, // Skip to: 13726 /* 8201 */ MCD_OPC_Decode, 213, 6, 140, 1, // Opcode: ILVEV_D /* 8206 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 8219 /* 8210 */ MCD_OPC_CheckPredicate, 8, 136, 21, // Skip to: 13726 /* 8214 */ MCD_OPC_Decode, 220, 6, 137, 1, // Opcode: ILVOD_B /* 8219 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8232 /* 8223 */ MCD_OPC_CheckPredicate, 8, 123, 21, // Skip to: 13726 /* 8227 */ MCD_OPC_Decode, 222, 6, 138, 1, // Opcode: ILVOD_H /* 8232 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8245 /* 8236 */ MCD_OPC_CheckPredicate, 8, 110, 21, // Skip to: 13726 /* 8240 */ MCD_OPC_Decode, 223, 6, 139, 1, // Opcode: ILVOD_W /* 8245 */ MCD_OPC_FilterValue, 31, 101, 21, // Skip to: 13726 /* 8249 */ MCD_OPC_CheckPredicate, 8, 97, 21, // Skip to: 13726 /* 8253 */ MCD_OPC_Decode, 221, 6, 140, 1, // Opcode: ILVOD_D /* 8258 */ MCD_OPC_FilterValue, 21, 59, 1, // Skip to: 8577 /* 8262 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 8265 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8278 /* 8269 */ MCD_OPC_CheckPredicate, 8, 77, 21, // Skip to: 13726 /* 8273 */ MCD_OPC_Decode, 227, 13, 141, 1, // Opcode: VSHF_B /* 8278 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8291 /* 8282 */ MCD_OPC_CheckPredicate, 8, 64, 21, // Skip to: 13726 /* 8286 */ MCD_OPC_Decode, 229, 13, 142, 1, // Opcode: VSHF_H /* 8291 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8304 /* 8295 */ MCD_OPC_CheckPredicate, 8, 51, 21, // Skip to: 13726 /* 8299 */ MCD_OPC_Decode, 230, 13, 143, 1, // Opcode: VSHF_W /* 8304 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8317 /* 8308 */ MCD_OPC_CheckPredicate, 8, 38, 21, // Skip to: 13726 /* 8312 */ MCD_OPC_Decode, 228, 13, 144, 1, // Opcode: VSHF_D /* 8317 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8330 /* 8321 */ MCD_OPC_CheckPredicate, 8, 25, 21, // Skip to: 13726 /* 8325 */ MCD_OPC_Decode, 148, 12, 137, 1, // Opcode: SRAR_B /* 8330 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 8343 /* 8334 */ MCD_OPC_CheckPredicate, 8, 12, 21, // Skip to: 13726 /* 8338 */ MCD_OPC_Decode, 150, 12, 138, 1, // Opcode: SRAR_H /* 8343 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 8356 /* 8347 */ MCD_OPC_CheckPredicate, 8, 255, 20, // Skip to: 13726 /* 8351 */ MCD_OPC_Decode, 151, 12, 139, 1, // Opcode: SRAR_W /* 8356 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 8369 /* 8360 */ MCD_OPC_CheckPredicate, 8, 242, 20, // Skip to: 13726 /* 8364 */ MCD_OPC_Decode, 149, 12, 140, 1, // Opcode: SRAR_D /* 8369 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8382 /* 8373 */ MCD_OPC_CheckPredicate, 8, 229, 20, // Skip to: 13726 /* 8377 */ MCD_OPC_Decode, 169, 12, 137, 1, // Opcode: SRLR_B /* 8382 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 8395 /* 8386 */ MCD_OPC_CheckPredicate, 8, 216, 20, // Skip to: 13726 /* 8390 */ MCD_OPC_Decode, 171, 12, 138, 1, // Opcode: SRLR_H /* 8395 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 8408 /* 8399 */ MCD_OPC_CheckPredicate, 8, 203, 20, // Skip to: 13726 /* 8403 */ MCD_OPC_Decode, 172, 12, 139, 1, // Opcode: SRLR_W /* 8408 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 8421 /* 8412 */ MCD_OPC_CheckPredicate, 8, 190, 20, // Skip to: 13726 /* 8416 */ MCD_OPC_Decode, 170, 12, 140, 1, // Opcode: SRLR_D /* 8421 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 8434 /* 8425 */ MCD_OPC_CheckPredicate, 8, 177, 20, // Skip to: 13726 /* 8429 */ MCD_OPC_Decode, 201, 6, 145, 1, // Opcode: HADD_S_H /* 8434 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 8447 /* 8438 */ MCD_OPC_CheckPredicate, 8, 164, 20, // Skip to: 13726 /* 8442 */ MCD_OPC_Decode, 202, 6, 146, 1, // Opcode: HADD_S_W /* 8447 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 8460 /* 8451 */ MCD_OPC_CheckPredicate, 8, 151, 20, // Skip to: 13726 /* 8455 */ MCD_OPC_Decode, 200, 6, 147, 1, // Opcode: HADD_S_D /* 8460 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 8473 /* 8464 */ MCD_OPC_CheckPredicate, 8, 138, 20, // Skip to: 13726 /* 8468 */ MCD_OPC_Decode, 204, 6, 145, 1, // Opcode: HADD_U_H /* 8473 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 8486 /* 8477 */ MCD_OPC_CheckPredicate, 8, 125, 20, // Skip to: 13726 /* 8481 */ MCD_OPC_Decode, 205, 6, 146, 1, // Opcode: HADD_U_W /* 8486 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 8499 /* 8490 */ MCD_OPC_CheckPredicate, 8, 112, 20, // Skip to: 13726 /* 8494 */ MCD_OPC_Decode, 203, 6, 147, 1, // Opcode: HADD_U_D /* 8499 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 8512 /* 8503 */ MCD_OPC_CheckPredicate, 8, 99, 20, // Skip to: 13726 /* 8507 */ MCD_OPC_Decode, 207, 6, 145, 1, // Opcode: HSUB_S_H /* 8512 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 8525 /* 8516 */ MCD_OPC_CheckPredicate, 8, 86, 20, // Skip to: 13726 /* 8520 */ MCD_OPC_Decode, 208, 6, 146, 1, // Opcode: HSUB_S_W /* 8525 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 8538 /* 8529 */ MCD_OPC_CheckPredicate, 8, 73, 20, // Skip to: 13726 /* 8533 */ MCD_OPC_Decode, 206, 6, 147, 1, // Opcode: HSUB_S_D /* 8538 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 8551 /* 8542 */ MCD_OPC_CheckPredicate, 8, 60, 20, // Skip to: 13726 /* 8546 */ MCD_OPC_Decode, 210, 6, 145, 1, // Opcode: HSUB_U_H /* 8551 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 8564 /* 8555 */ MCD_OPC_CheckPredicate, 8, 47, 20, // Skip to: 13726 /* 8559 */ MCD_OPC_Decode, 211, 6, 146, 1, // Opcode: HSUB_U_W /* 8564 */ MCD_OPC_FilterValue, 31, 38, 20, // Skip to: 13726 /* 8568 */ MCD_OPC_CheckPredicate, 8, 34, 20, // Skip to: 13726 /* 8572 */ MCD_OPC_Decode, 209, 6, 147, 1, // Opcode: HSUB_U_D /* 8577 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 9067 /* 8581 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... /* 8584 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8597 /* 8588 */ MCD_OPC_CheckPredicate, 8, 14, 20, // Skip to: 13726 /* 8592 */ MCD_OPC_Decode, 217, 11, 159, 1, // Opcode: SLDI_B /* 8597 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8616 /* 8601 */ MCD_OPC_CheckPredicate, 8, 1, 20, // Skip to: 13726 /* 8605 */ MCD_OPC_CheckField, 19, 1, 0, 251, 19, // Skip to: 13726 /* 8611 */ MCD_OPC_Decode, 219, 11, 160, 1, // Opcode: SLDI_H /* 8616 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8674 /* 8620 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... /* 8623 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8636 /* 8627 */ MCD_OPC_CheckPredicate, 8, 231, 19, // Skip to: 13726 /* 8631 */ MCD_OPC_Decode, 220, 11, 161, 1, // Opcode: SLDI_W /* 8636 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8655 /* 8640 */ MCD_OPC_CheckPredicate, 8, 218, 19, // Skip to: 13726 /* 8644 */ MCD_OPC_CheckField, 17, 1, 0, 212, 19, // Skip to: 13726 /* 8650 */ MCD_OPC_Decode, 218, 11, 162, 1, // Opcode: SLDI_D /* 8655 */ MCD_OPC_FilterValue, 3, 203, 19, // Skip to: 13726 /* 8659 */ MCD_OPC_CheckPredicate, 8, 199, 19, // Skip to: 13726 /* 8663 */ MCD_OPC_CheckField, 16, 2, 2, 193, 19, // Skip to: 13726 /* 8669 */ MCD_OPC_Decode, 212, 3, 163, 1, // Opcode: CTCMSA /* 8674 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8687 /* 8678 */ MCD_OPC_CheckPredicate, 8, 180, 19, // Skip to: 13726 /* 8682 */ MCD_OPC_Decode, 131, 12, 164, 1, // Opcode: SPLATI_B /* 8687 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8706 /* 8691 */ MCD_OPC_CheckPredicate, 8, 167, 19, // Skip to: 13726 /* 8695 */ MCD_OPC_CheckField, 19, 1, 0, 161, 19, // Skip to: 13726 /* 8701 */ MCD_OPC_Decode, 133, 12, 165, 1, // Opcode: SPLATI_H /* 8706 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8764 /* 8710 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... /* 8713 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8726 /* 8717 */ MCD_OPC_CheckPredicate, 8, 141, 19, // Skip to: 13726 /* 8721 */ MCD_OPC_Decode, 134, 12, 166, 1, // Opcode: SPLATI_W /* 8726 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8745 /* 8730 */ MCD_OPC_CheckPredicate, 8, 128, 19, // Skip to: 13726 /* 8734 */ MCD_OPC_CheckField, 17, 1, 0, 122, 19, // Skip to: 13726 /* 8740 */ MCD_OPC_Decode, 132, 12, 167, 1, // Opcode: SPLATI_D /* 8745 */ MCD_OPC_FilterValue, 3, 113, 19, // Skip to: 13726 /* 8749 */ MCD_OPC_CheckPredicate, 8, 109, 19, // Skip to: 13726 /* 8753 */ MCD_OPC_CheckField, 16, 2, 2, 103, 19, // Skip to: 13726 /* 8759 */ MCD_OPC_Decode, 240, 2, 168, 1, // Opcode: CFCMSA /* 8764 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8777 /* 8768 */ MCD_OPC_CheckPredicate, 8, 90, 19, // Skip to: 13726 /* 8772 */ MCD_OPC_Decode, 202, 3, 169, 1, // Opcode: COPY_S_B /* 8777 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8796 /* 8781 */ MCD_OPC_CheckPredicate, 8, 77, 19, // Skip to: 13726 /* 8785 */ MCD_OPC_CheckField, 19, 1, 0, 71, 19, // Skip to: 13726 /* 8791 */ MCD_OPC_Decode, 204, 3, 170, 1, // Opcode: COPY_S_H /* 8796 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8854 /* 8800 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... /* 8803 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8816 /* 8807 */ MCD_OPC_CheckPredicate, 8, 51, 19, // Skip to: 13726 /* 8811 */ MCD_OPC_Decode, 205, 3, 171, 1, // Opcode: COPY_S_W /* 8816 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8835 /* 8820 */ MCD_OPC_CheckPredicate, 14, 38, 19, // Skip to: 13726 /* 8824 */ MCD_OPC_CheckField, 17, 1, 0, 32, 19, // Skip to: 13726 /* 8830 */ MCD_OPC_Decode, 203, 3, 172, 1, // Opcode: COPY_S_D /* 8835 */ MCD_OPC_FilterValue, 3, 23, 19, // Skip to: 13726 /* 8839 */ MCD_OPC_CheckPredicate, 8, 19, 19, // Skip to: 13726 /* 8843 */ MCD_OPC_CheckField, 16, 2, 2, 13, 19, // Skip to: 13726 /* 8849 */ MCD_OPC_Decode, 235, 8, 173, 1, // Opcode: MOVE_V /* 8854 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8867 /* 8858 */ MCD_OPC_CheckPredicate, 8, 0, 19, // Skip to: 13726 /* 8862 */ MCD_OPC_Decode, 206, 3, 169, 1, // Opcode: COPY_U_B /* 8867 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8886 /* 8871 */ MCD_OPC_CheckPredicate, 8, 243, 18, // Skip to: 13726 /* 8875 */ MCD_OPC_CheckField, 19, 1, 0, 237, 18, // Skip to: 13726 /* 8881 */ MCD_OPC_Decode, 208, 3, 170, 1, // Opcode: COPY_U_H /* 8886 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8925 /* 8890 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... /* 8893 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8906 /* 8897 */ MCD_OPC_CheckPredicate, 8, 217, 18, // Skip to: 13726 /* 8901 */ MCD_OPC_Decode, 209, 3, 171, 1, // Opcode: COPY_U_W /* 8906 */ MCD_OPC_FilterValue, 2, 208, 18, // Skip to: 13726 /* 8910 */ MCD_OPC_CheckPredicate, 14, 204, 18, // Skip to: 13726 /* 8914 */ MCD_OPC_CheckField, 17, 1, 0, 198, 18, // Skip to: 13726 /* 8920 */ MCD_OPC_Decode, 207, 3, 172, 1, // Opcode: COPY_U_D /* 8925 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8938 /* 8929 */ MCD_OPC_CheckPredicate, 8, 185, 18, // Skip to: 13726 /* 8933 */ MCD_OPC_Decode, 229, 6, 174, 1, // Opcode: INSERT_B /* 8938 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8957 /* 8942 */ MCD_OPC_CheckPredicate, 8, 172, 18, // Skip to: 13726 /* 8946 */ MCD_OPC_CheckField, 19, 1, 0, 166, 18, // Skip to: 13726 /* 8952 */ MCD_OPC_Decode, 237, 6, 175, 1, // Opcode: INSERT_H /* 8957 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8996 /* 8961 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... /* 8964 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8977 /* 8968 */ MCD_OPC_CheckPredicate, 8, 146, 18, // Skip to: 13726 /* 8972 */ MCD_OPC_Decode, 239, 6, 176, 1, // Opcode: INSERT_W /* 8977 */ MCD_OPC_FilterValue, 2, 137, 18, // Skip to: 13726 /* 8981 */ MCD_OPC_CheckPredicate, 14, 133, 18, // Skip to: 13726 /* 8985 */ MCD_OPC_CheckField, 17, 1, 0, 127, 18, // Skip to: 13726 /* 8991 */ MCD_OPC_Decode, 231, 6, 177, 1, // Opcode: INSERT_D /* 8996 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9009 /* 9000 */ MCD_OPC_CheckPredicate, 8, 114, 18, // Skip to: 13726 /* 9004 */ MCD_OPC_Decode, 242, 6, 178, 1, // Opcode: INSVE_B /* 9009 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 9028 /* 9013 */ MCD_OPC_CheckPredicate, 8, 101, 18, // Skip to: 13726 /* 9017 */ MCD_OPC_CheckField, 19, 1, 0, 95, 18, // Skip to: 13726 /* 9023 */ MCD_OPC_Decode, 244, 6, 178, 1, // Opcode: INSVE_H /* 9028 */ MCD_OPC_FilterValue, 23, 86, 18, // Skip to: 13726 /* 9032 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... /* 9035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9048 /* 9039 */ MCD_OPC_CheckPredicate, 8, 75, 18, // Skip to: 13726 /* 9043 */ MCD_OPC_Decode, 245, 6, 178, 1, // Opcode: INSVE_W /* 9048 */ MCD_OPC_FilterValue, 2, 66, 18, // Skip to: 13726 /* 9052 */ MCD_OPC_CheckPredicate, 8, 62, 18, // Skip to: 13726 /* 9056 */ MCD_OPC_CheckField, 17, 1, 0, 56, 18, // Skip to: 13726 /* 9062 */ MCD_OPC_Decode, 243, 6, 178, 1, // Opcode: INSVE_D /* 9067 */ MCD_OPC_FilterValue, 26, 163, 1, // Skip to: 9490 /* 9071 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 9074 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9087 /* 9078 */ MCD_OPC_CheckPredicate, 8, 36, 18, // Skip to: 13726 /* 9082 */ MCD_OPC_Decode, 178, 5, 139, 1, // Opcode: FCAF_W /* 9087 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9100 /* 9091 */ MCD_OPC_CheckPredicate, 8, 23, 18, // Skip to: 13726 /* 9095 */ MCD_OPC_Decode, 177, 5, 140, 1, // Opcode: FCAF_D /* 9100 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9113 /* 9104 */ MCD_OPC_CheckPredicate, 8, 10, 18, // Skip to: 13726 /* 9108 */ MCD_OPC_Decode, 205, 5, 139, 1, // Opcode: FCUN_W /* 9113 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9126 /* 9117 */ MCD_OPC_CheckPredicate, 8, 253, 17, // Skip to: 13726 /* 9121 */ MCD_OPC_Decode, 204, 5, 140, 1, // Opcode: FCUN_D /* 9126 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9139 /* 9130 */ MCD_OPC_CheckPredicate, 8, 240, 17, // Skip to: 13726 /* 9134 */ MCD_OPC_Decode, 180, 5, 139, 1, // Opcode: FCEQ_W /* 9139 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9152 /* 9143 */ MCD_OPC_CheckPredicate, 8, 227, 17, // Skip to: 13726 /* 9147 */ MCD_OPC_Decode, 179, 5, 140, 1, // Opcode: FCEQ_D /* 9152 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9165 /* 9156 */ MCD_OPC_CheckPredicate, 8, 214, 17, // Skip to: 13726 /* 9160 */ MCD_OPC_Decode, 197, 5, 139, 1, // Opcode: FCUEQ_W /* 9165 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9178 /* 9169 */ MCD_OPC_CheckPredicate, 8, 201, 17, // Skip to: 13726 /* 9173 */ MCD_OPC_Decode, 196, 5, 140, 1, // Opcode: FCUEQ_D /* 9178 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9191 /* 9182 */ MCD_OPC_CheckPredicate, 8, 188, 17, // Skip to: 13726 /* 9186 */ MCD_OPC_Decode, 186, 5, 139, 1, // Opcode: FCLT_W /* 9191 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9204 /* 9195 */ MCD_OPC_CheckPredicate, 8, 175, 17, // Skip to: 13726 /* 9199 */ MCD_OPC_Decode, 185, 5, 140, 1, // Opcode: FCLT_D /* 9204 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9217 /* 9208 */ MCD_OPC_CheckPredicate, 8, 162, 17, // Skip to: 13726 /* 9212 */ MCD_OPC_Decode, 201, 5, 139, 1, // Opcode: FCULT_W /* 9217 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9230 /* 9221 */ MCD_OPC_CheckPredicate, 8, 149, 17, // Skip to: 13726 /* 9225 */ MCD_OPC_Decode, 200, 5, 140, 1, // Opcode: FCULT_D /* 9230 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9243 /* 9234 */ MCD_OPC_CheckPredicate, 8, 136, 17, // Skip to: 13726 /* 9238 */ MCD_OPC_Decode, 184, 5, 139, 1, // Opcode: FCLE_W /* 9243 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9256 /* 9247 */ MCD_OPC_CheckPredicate, 8, 123, 17, // Skip to: 13726 /* 9251 */ MCD_OPC_Decode, 183, 5, 140, 1, // Opcode: FCLE_D /* 9256 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9269 /* 9260 */ MCD_OPC_CheckPredicate, 8, 110, 17, // Skip to: 13726 /* 9264 */ MCD_OPC_Decode, 199, 5, 139, 1, // Opcode: FCULE_W /* 9269 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9282 /* 9273 */ MCD_OPC_CheckPredicate, 8, 97, 17, // Skip to: 13726 /* 9277 */ MCD_OPC_Decode, 198, 5, 140, 1, // Opcode: FCULE_D /* 9282 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9295 /* 9286 */ MCD_OPC_CheckPredicate, 8, 84, 17, // Skip to: 13726 /* 9290 */ MCD_OPC_Decode, 154, 6, 139, 1, // Opcode: FSAF_W /* 9295 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9308 /* 9299 */ MCD_OPC_CheckPredicate, 8, 71, 17, // Skip to: 13726 /* 9303 */ MCD_OPC_Decode, 153, 6, 140, 1, // Opcode: FSAF_D /* 9308 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 9321 /* 9312 */ MCD_OPC_CheckPredicate, 8, 58, 17, // Skip to: 13726 /* 9316 */ MCD_OPC_Decode, 188, 6, 139, 1, // Opcode: FSUN_W /* 9321 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 9334 /* 9325 */ MCD_OPC_CheckPredicate, 8, 45, 17, // Skip to: 13726 /* 9329 */ MCD_OPC_Decode, 187, 6, 140, 1, // Opcode: FSUN_D /* 9334 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9347 /* 9338 */ MCD_OPC_CheckPredicate, 8, 32, 17, // Skip to: 13726 /* 9342 */ MCD_OPC_Decode, 156, 6, 139, 1, // Opcode: FSEQ_W /* 9347 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9360 /* 9351 */ MCD_OPC_CheckPredicate, 8, 19, 17, // Skip to: 13726 /* 9355 */ MCD_OPC_Decode, 155, 6, 140, 1, // Opcode: FSEQ_D /* 9360 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 9373 /* 9364 */ MCD_OPC_CheckPredicate, 8, 6, 17, // Skip to: 13726 /* 9368 */ MCD_OPC_Decode, 180, 6, 139, 1, // Opcode: FSUEQ_W /* 9373 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 9386 /* 9377 */ MCD_OPC_CheckPredicate, 8, 249, 16, // Skip to: 13726 /* 9381 */ MCD_OPC_Decode, 179, 6, 140, 1, // Opcode: FSUEQ_D /* 9386 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9399 /* 9390 */ MCD_OPC_CheckPredicate, 8, 236, 16, // Skip to: 13726 /* 9394 */ MCD_OPC_Decode, 160, 6, 139, 1, // Opcode: FSLT_W /* 9399 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9412 /* 9403 */ MCD_OPC_CheckPredicate, 8, 223, 16, // Skip to: 13726 /* 9407 */ MCD_OPC_Decode, 159, 6, 140, 1, // Opcode: FSLT_D /* 9412 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9425 /* 9416 */ MCD_OPC_CheckPredicate, 8, 210, 16, // Skip to: 13726 /* 9420 */ MCD_OPC_Decode, 184, 6, 139, 1, // Opcode: FSULT_W /* 9425 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9438 /* 9429 */ MCD_OPC_CheckPredicate, 8, 197, 16, // Skip to: 13726 /* 9433 */ MCD_OPC_Decode, 183, 6, 140, 1, // Opcode: FSULT_D /* 9438 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9451 /* 9442 */ MCD_OPC_CheckPredicate, 8, 184, 16, // Skip to: 13726 /* 9446 */ MCD_OPC_Decode, 158, 6, 139, 1, // Opcode: FSLE_W /* 9451 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9464 /* 9455 */ MCD_OPC_CheckPredicate, 8, 171, 16, // Skip to: 13726 /* 9459 */ MCD_OPC_Decode, 157, 6, 140, 1, // Opcode: FSLE_D /* 9464 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9477 /* 9468 */ MCD_OPC_CheckPredicate, 8, 158, 16, // Skip to: 13726 /* 9472 */ MCD_OPC_Decode, 182, 6, 139, 1, // Opcode: FSULE_W /* 9477 */ MCD_OPC_FilterValue, 31, 149, 16, // Skip to: 13726 /* 9481 */ MCD_OPC_CheckPredicate, 8, 145, 16, // Skip to: 13726 /* 9485 */ MCD_OPC_Decode, 181, 6, 140, 1, // Opcode: FSULE_D /* 9490 */ MCD_OPC_FilterValue, 27, 85, 1, // Skip to: 9835 /* 9494 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 9497 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9510 /* 9501 */ MCD_OPC_CheckPredicate, 8, 125, 16, // Skip to: 13726 /* 9505 */ MCD_OPC_Decode, 176, 5, 139, 1, // Opcode: FADD_W /* 9510 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9523 /* 9514 */ MCD_OPC_CheckPredicate, 8, 112, 16, // Skip to: 13726 /* 9518 */ MCD_OPC_Decode, 170, 5, 140, 1, // Opcode: FADD_D /* 9523 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9536 /* 9527 */ MCD_OPC_CheckPredicate, 8, 99, 16, // Skip to: 13726 /* 9531 */ MCD_OPC_Decode, 178, 6, 139, 1, // Opcode: FSUB_W /* 9536 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9549 /* 9540 */ MCD_OPC_CheckPredicate, 8, 86, 16, // Skip to: 13726 /* 9544 */ MCD_OPC_Decode, 172, 6, 140, 1, // Opcode: FSUB_D /* 9549 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9562 /* 9553 */ MCD_OPC_CheckPredicate, 8, 73, 16, // Skip to: 13726 /* 9557 */ MCD_OPC_Decode, 141, 6, 139, 1, // Opcode: FMUL_W /* 9562 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9575 /* 9566 */ MCD_OPC_CheckPredicate, 8, 60, 16, // Skip to: 13726 /* 9570 */ MCD_OPC_Decode, 135, 6, 140, 1, // Opcode: FMUL_D /* 9575 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9588 /* 9579 */ MCD_OPC_CheckPredicate, 8, 47, 16, // Skip to: 13726 /* 9583 */ MCD_OPC_Decode, 212, 5, 139, 1, // Opcode: FDIV_W /* 9588 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9601 /* 9592 */ MCD_OPC_CheckPredicate, 8, 34, 16, // Skip to: 13726 /* 9596 */ MCD_OPC_Decode, 206, 5, 140, 1, // Opcode: FDIV_D /* 9601 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9614 /* 9605 */ MCD_OPC_CheckPredicate, 8, 21, 16, // Skip to: 13726 /* 9609 */ MCD_OPC_Decode, 247, 5, 143, 1, // Opcode: FMADD_W /* 9614 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9627 /* 9618 */ MCD_OPC_CheckPredicate, 8, 8, 16, // Skip to: 13726 /* 9622 */ MCD_OPC_Decode, 246, 5, 144, 1, // Opcode: FMADD_D /* 9627 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9640 /* 9631 */ MCD_OPC_CheckPredicate, 8, 251, 15, // Skip to: 13726 /* 9635 */ MCD_OPC_Decode, 134, 6, 143, 1, // Opcode: FMSUB_W /* 9640 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9653 /* 9644 */ MCD_OPC_CheckPredicate, 8, 238, 15, // Skip to: 13726 /* 9648 */ MCD_OPC_Decode, 133, 6, 144, 1, // Opcode: FMSUB_D /* 9653 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 9666 /* 9657 */ MCD_OPC_CheckPredicate, 8, 225, 15, // Skip to: 13726 /* 9661 */ MCD_OPC_Decode, 217, 5, 139, 1, // Opcode: FEXP2_W /* 9666 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 9679 /* 9670 */ MCD_OPC_CheckPredicate, 8, 212, 15, // Skip to: 13726 /* 9674 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: FEXP2_D /* 9679 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9692 /* 9683 */ MCD_OPC_CheckPredicate, 8, 199, 15, // Skip to: 13726 /* 9687 */ MCD_OPC_Decode, 213, 5, 179, 1, // Opcode: FEXDO_H /* 9692 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9705 /* 9696 */ MCD_OPC_CheckPredicate, 8, 186, 15, // Skip to: 13726 /* 9700 */ MCD_OPC_Decode, 214, 5, 180, 1, // Opcode: FEXDO_W /* 9705 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9718 /* 9709 */ MCD_OPC_CheckPredicate, 8, 173, 15, // Skip to: 13726 /* 9713 */ MCD_OPC_Decode, 193, 6, 179, 1, // Opcode: FTQ_H /* 9718 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9731 /* 9722 */ MCD_OPC_CheckPredicate, 8, 160, 15, // Skip to: 13726 /* 9726 */ MCD_OPC_Decode, 194, 6, 180, 1, // Opcode: FTQ_W /* 9731 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 9744 /* 9735 */ MCD_OPC_CheckPredicate, 8, 147, 15, // Skip to: 13726 /* 9739 */ MCD_OPC_Decode, 255, 5, 139, 1, // Opcode: FMIN_W /* 9744 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 9757 /* 9748 */ MCD_OPC_CheckPredicate, 8, 134, 15, // Skip to: 13726 /* 9752 */ MCD_OPC_Decode, 254, 5, 140, 1, // Opcode: FMIN_D /* 9757 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 9770 /* 9761 */ MCD_OPC_CheckPredicate, 8, 121, 15, // Skip to: 13726 /* 9765 */ MCD_OPC_Decode, 253, 5, 139, 1, // Opcode: FMIN_A_W /* 9770 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 9783 /* 9774 */ MCD_OPC_CheckPredicate, 8, 108, 15, // Skip to: 13726 /* 9778 */ MCD_OPC_Decode, 252, 5, 140, 1, // Opcode: FMIN_A_D /* 9783 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 9796 /* 9787 */ MCD_OPC_CheckPredicate, 8, 95, 15, // Skip to: 13726 /* 9791 */ MCD_OPC_Decode, 251, 5, 139, 1, // Opcode: FMAX_W /* 9796 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 9809 /* 9800 */ MCD_OPC_CheckPredicate, 8, 82, 15, // Skip to: 13726 /* 9804 */ MCD_OPC_Decode, 250, 5, 140, 1, // Opcode: FMAX_D /* 9809 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 9822 /* 9813 */ MCD_OPC_CheckPredicate, 8, 69, 15, // Skip to: 13726 /* 9817 */ MCD_OPC_Decode, 249, 5, 139, 1, // Opcode: FMAX_A_W /* 9822 */ MCD_OPC_FilterValue, 31, 60, 15, // Skip to: 13726 /* 9826 */ MCD_OPC_CheckPredicate, 8, 56, 15, // Skip to: 13726 /* 9830 */ MCD_OPC_Decode, 248, 5, 140, 1, // Opcode: FMAX_A_D /* 9835 */ MCD_OPC_FilterValue, 28, 59, 1, // Skip to: 10154 /* 9839 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 9842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9855 /* 9846 */ MCD_OPC_CheckPredicate, 8, 36, 15, // Skip to: 13726 /* 9850 */ MCD_OPC_Decode, 195, 5, 139, 1, // Opcode: FCOR_W /* 9855 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9868 /* 9859 */ MCD_OPC_CheckPredicate, 8, 23, 15, // Skip to: 13726 /* 9863 */ MCD_OPC_Decode, 194, 5, 140, 1, // Opcode: FCOR_D /* 9868 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9881 /* 9872 */ MCD_OPC_CheckPredicate, 8, 10, 15, // Skip to: 13726 /* 9876 */ MCD_OPC_Decode, 203, 5, 139, 1, // Opcode: FCUNE_W /* 9881 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9894 /* 9885 */ MCD_OPC_CheckPredicate, 8, 253, 14, // Skip to: 13726 /* 9889 */ MCD_OPC_Decode, 202, 5, 140, 1, // Opcode: FCUNE_D /* 9894 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9907 /* 9898 */ MCD_OPC_CheckPredicate, 8, 240, 14, // Skip to: 13726 /* 9902 */ MCD_OPC_Decode, 193, 5, 139, 1, // Opcode: FCNE_W /* 9907 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9920 /* 9911 */ MCD_OPC_CheckPredicate, 8, 227, 14, // Skip to: 13726 /* 9915 */ MCD_OPC_Decode, 192, 5, 140, 1, // Opcode: FCNE_D /* 9920 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 9933 /* 9924 */ MCD_OPC_CheckPredicate, 8, 214, 14, // Skip to: 13726 /* 9928 */ MCD_OPC_Decode, 219, 9, 138, 1, // Opcode: MUL_Q_H /* 9933 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 9946 /* 9937 */ MCD_OPC_CheckPredicate, 8, 201, 14, // Skip to: 13726 /* 9941 */ MCD_OPC_Decode, 220, 9, 139, 1, // Opcode: MUL_Q_W /* 9946 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 9959 /* 9950 */ MCD_OPC_CheckPredicate, 8, 188, 14, // Skip to: 13726 /* 9954 */ MCD_OPC_Decode, 147, 8, 142, 1, // Opcode: MADD_Q_H /* 9959 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 9972 /* 9963 */ MCD_OPC_CheckPredicate, 8, 175, 14, // Skip to: 13726 /* 9967 */ MCD_OPC_Decode, 148, 8, 143, 1, // Opcode: MADD_Q_W /* 9972 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 9985 /* 9976 */ MCD_OPC_CheckPredicate, 8, 162, 14, // Skip to: 13726 /* 9980 */ MCD_OPC_Decode, 165, 9, 142, 1, // Opcode: MSUB_Q_H /* 9985 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 9998 /* 9989 */ MCD_OPC_CheckPredicate, 8, 149, 14, // Skip to: 13726 /* 9993 */ MCD_OPC_Decode, 166, 9, 143, 1, // Opcode: MSUB_Q_W /* 9998 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10011 /* 10002 */ MCD_OPC_CheckPredicate, 8, 136, 14, // Skip to: 13726 /* 10006 */ MCD_OPC_Decode, 164, 6, 139, 1, // Opcode: FSOR_W /* 10011 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10024 /* 10015 */ MCD_OPC_CheckPredicate, 8, 123, 14, // Skip to: 13726 /* 10019 */ MCD_OPC_Decode, 163, 6, 140, 1, // Opcode: FSOR_D /* 10024 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10037 /* 10028 */ MCD_OPC_CheckPredicate, 8, 110, 14, // Skip to: 13726 /* 10032 */ MCD_OPC_Decode, 186, 6, 139, 1, // Opcode: FSUNE_W /* 10037 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10050 /* 10041 */ MCD_OPC_CheckPredicate, 8, 97, 14, // Skip to: 13726 /* 10045 */ MCD_OPC_Decode, 185, 6, 140, 1, // Opcode: FSUNE_D /* 10050 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10063 /* 10054 */ MCD_OPC_CheckPredicate, 8, 84, 14, // Skip to: 13726 /* 10058 */ MCD_OPC_Decode, 162, 6, 139, 1, // Opcode: FSNE_W /* 10063 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10076 /* 10067 */ MCD_OPC_CheckPredicate, 8, 71, 14, // Skip to: 13726 /* 10071 */ MCD_OPC_Decode, 161, 6, 140, 1, // Opcode: FSNE_D /* 10076 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10089 /* 10080 */ MCD_OPC_CheckPredicate, 8, 58, 14, // Skip to: 13726 /* 10084 */ MCD_OPC_Decode, 202, 9, 138, 1, // Opcode: MULR_Q_H /* 10089 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10102 /* 10093 */ MCD_OPC_CheckPredicate, 8, 45, 14, // Skip to: 13726 /* 10097 */ MCD_OPC_Decode, 203, 9, 139, 1, // Opcode: MULR_Q_W /* 10102 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10115 /* 10106 */ MCD_OPC_CheckPredicate, 8, 32, 14, // Skip to: 13726 /* 10110 */ MCD_OPC_Decode, 133, 8, 142, 1, // Opcode: MADDR_Q_H /* 10115 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10128 /* 10119 */ MCD_OPC_CheckPredicate, 8, 19, 14, // Skip to: 13726 /* 10123 */ MCD_OPC_Decode, 134, 8, 143, 1, // Opcode: MADDR_Q_W /* 10128 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10141 /* 10132 */ MCD_OPC_CheckPredicate, 8, 6, 14, // Skip to: 13726 /* 10136 */ MCD_OPC_Decode, 151, 9, 142, 1, // Opcode: MSUBR_Q_H /* 10141 */ MCD_OPC_FilterValue, 29, 253, 13, // Skip to: 13726 /* 10145 */ MCD_OPC_CheckPredicate, 8, 249, 13, // Skip to: 13726 /* 10149 */ MCD_OPC_Decode, 152, 9, 143, 1, // Opcode: MSUBR_Q_W /* 10154 */ MCD_OPC_FilterValue, 30, 219, 2, // Skip to: 10889 /* 10158 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 10161 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10173 /* 10165 */ MCD_OPC_CheckPredicate, 8, 229, 13, // Skip to: 13726 /* 10169 */ MCD_OPC_Decode, 89, 137, 1, // Opcode: AND_V /* 10173 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10186 /* 10177 */ MCD_OPC_CheckPredicate, 8, 217, 13, // Skip to: 13726 /* 10181 */ MCD_OPC_Decode, 138, 10, 137, 1, // Opcode: OR_V /* 10186 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10199 /* 10190 */ MCD_OPC_CheckPredicate, 8, 204, 13, // Skip to: 13726 /* 10194 */ MCD_OPC_Decode, 254, 9, 137, 1, // Opcode: NOR_V /* 10199 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10212 /* 10203 */ MCD_OPC_CheckPredicate, 8, 191, 13, // Skip to: 13726 /* 10207 */ MCD_OPC_Decode, 241, 13, 137, 1, // Opcode: XOR_V /* 10212 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10225 /* 10216 */ MCD_OPC_CheckPredicate, 8, 178, 13, // Skip to: 13726 /* 10220 */ MCD_OPC_Decode, 142, 2, 141, 1, // Opcode: BMNZ_V /* 10225 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10238 /* 10229 */ MCD_OPC_CheckPredicate, 8, 165, 13, // Skip to: 13726 /* 10233 */ MCD_OPC_Decode, 144, 2, 141, 1, // Opcode: BMZ_V /* 10238 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10251 /* 10242 */ MCD_OPC_CheckPredicate, 8, 152, 13, // Skip to: 13726 /* 10246 */ MCD_OPC_Decode, 179, 2, 141, 1, // Opcode: BSEL_V /* 10251 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10466 /* 10255 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 10258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10271 /* 10262 */ MCD_OPC_CheckPredicate, 8, 132, 13, // Skip to: 13726 /* 10266 */ MCD_OPC_Decode, 231, 5, 181, 1, // Opcode: FILL_B /* 10271 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10284 /* 10275 */ MCD_OPC_CheckPredicate, 8, 119, 13, // Skip to: 13726 /* 10279 */ MCD_OPC_Decode, 235, 5, 182, 1, // Opcode: FILL_H /* 10284 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10297 /* 10288 */ MCD_OPC_CheckPredicate, 8, 106, 13, // Skip to: 13726 /* 10292 */ MCD_OPC_Decode, 236, 5, 183, 1, // Opcode: FILL_W /* 10297 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10310 /* 10301 */ MCD_OPC_CheckPredicate, 14, 93, 13, // Skip to: 13726 /* 10305 */ MCD_OPC_Decode, 232, 5, 184, 1, // Opcode: FILL_D /* 10310 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10323 /* 10314 */ MCD_OPC_CheckPredicate, 8, 80, 13, // Skip to: 13726 /* 10318 */ MCD_OPC_Decode, 157, 10, 173, 1, // Opcode: PCNT_B /* 10323 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10336 /* 10327 */ MCD_OPC_CheckPredicate, 8, 67, 13, // Skip to: 13726 /* 10331 */ MCD_OPC_Decode, 159, 10, 185, 1, // Opcode: PCNT_H /* 10336 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10349 /* 10340 */ MCD_OPC_CheckPredicate, 8, 54, 13, // Skip to: 13726 /* 10344 */ MCD_OPC_Decode, 160, 10, 186, 1, // Opcode: PCNT_W /* 10349 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10362 /* 10353 */ MCD_OPC_CheckPredicate, 8, 41, 13, // Skip to: 13726 /* 10357 */ MCD_OPC_Decode, 158, 10, 187, 1, // Opcode: PCNT_D /* 10362 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10375 /* 10366 */ MCD_OPC_CheckPredicate, 8, 28, 13, // Skip to: 13726 /* 10370 */ MCD_OPC_Decode, 231, 9, 173, 1, // Opcode: NLOC_B /* 10375 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10388 /* 10379 */ MCD_OPC_CheckPredicate, 8, 15, 13, // Skip to: 13726 /* 10383 */ MCD_OPC_Decode, 233, 9, 185, 1, // Opcode: NLOC_H /* 10388 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10401 /* 10392 */ MCD_OPC_CheckPredicate, 8, 2, 13, // Skip to: 13726 /* 10396 */ MCD_OPC_Decode, 234, 9, 186, 1, // Opcode: NLOC_W /* 10401 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10414 /* 10405 */ MCD_OPC_CheckPredicate, 8, 245, 12, // Skip to: 13726 /* 10409 */ MCD_OPC_Decode, 232, 9, 187, 1, // Opcode: NLOC_D /* 10414 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10427 /* 10418 */ MCD_OPC_CheckPredicate, 8, 232, 12, // Skip to: 13726 /* 10422 */ MCD_OPC_Decode, 235, 9, 173, 1, // Opcode: NLZC_B /* 10427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10440 /* 10431 */ MCD_OPC_CheckPredicate, 8, 219, 12, // Skip to: 13726 /* 10435 */ MCD_OPC_Decode, 237, 9, 185, 1, // Opcode: NLZC_H /* 10440 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10453 /* 10444 */ MCD_OPC_CheckPredicate, 8, 206, 12, // Skip to: 13726 /* 10448 */ MCD_OPC_Decode, 238, 9, 186, 1, // Opcode: NLZC_W /* 10453 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13726 /* 10457 */ MCD_OPC_CheckPredicate, 8, 193, 12, // Skip to: 13726 /* 10461 */ MCD_OPC_Decode, 236, 9, 187, 1, // Opcode: NLZC_D /* 10466 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13726 /* 10470 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 10473 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10486 /* 10477 */ MCD_OPC_CheckPredicate, 8, 173, 12, // Skip to: 13726 /* 10481 */ MCD_OPC_Decode, 182, 5, 186, 1, // Opcode: FCLASS_W /* 10486 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10499 /* 10490 */ MCD_OPC_CheckPredicate, 8, 160, 12, // Skip to: 13726 /* 10494 */ MCD_OPC_Decode, 181, 5, 187, 1, // Opcode: FCLASS_D /* 10499 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10512 /* 10503 */ MCD_OPC_CheckPredicate, 8, 147, 12, // Skip to: 13726 /* 10507 */ MCD_OPC_Decode, 196, 6, 186, 1, // Opcode: FTRUNC_S_W /* 10512 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10525 /* 10516 */ MCD_OPC_CheckPredicate, 8, 134, 12, // Skip to: 13726 /* 10520 */ MCD_OPC_Decode, 195, 6, 187, 1, // Opcode: FTRUNC_S_D /* 10525 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10538 /* 10529 */ MCD_OPC_CheckPredicate, 8, 121, 12, // Skip to: 13726 /* 10533 */ MCD_OPC_Decode, 198, 6, 186, 1, // Opcode: FTRUNC_U_W /* 10538 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10551 /* 10542 */ MCD_OPC_CheckPredicate, 8, 108, 12, // Skip to: 13726 /* 10546 */ MCD_OPC_Decode, 197, 6, 187, 1, // Opcode: FTRUNC_U_D /* 10551 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10564 /* 10555 */ MCD_OPC_CheckPredicate, 8, 95, 12, // Skip to: 13726 /* 10559 */ MCD_OPC_Decode, 171, 6, 186, 1, // Opcode: FSQRT_W /* 10564 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10577 /* 10568 */ MCD_OPC_CheckPredicate, 8, 82, 12, // Skip to: 13726 /* 10572 */ MCD_OPC_Decode, 165, 6, 187, 1, // Opcode: FSQRT_D /* 10577 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10590 /* 10581 */ MCD_OPC_CheckPredicate, 8, 69, 12, // Skip to: 13726 /* 10585 */ MCD_OPC_Decode, 152, 6, 186, 1, // Opcode: FRSQRT_W /* 10590 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10603 /* 10594 */ MCD_OPC_CheckPredicate, 8, 56, 12, // Skip to: 13726 /* 10598 */ MCD_OPC_Decode, 151, 6, 187, 1, // Opcode: FRSQRT_D /* 10603 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10616 /* 10607 */ MCD_OPC_CheckPredicate, 8, 43, 12, // Skip to: 13726 /* 10611 */ MCD_OPC_Decode, 148, 6, 186, 1, // Opcode: FRCP_W /* 10616 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10629 /* 10620 */ MCD_OPC_CheckPredicate, 8, 30, 12, // Skip to: 13726 /* 10624 */ MCD_OPC_Decode, 147, 6, 187, 1, // Opcode: FRCP_D /* 10629 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10642 /* 10633 */ MCD_OPC_CheckPredicate, 8, 17, 12, // Skip to: 13726 /* 10637 */ MCD_OPC_Decode, 150, 6, 186, 1, // Opcode: FRINT_W /* 10642 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10655 /* 10646 */ MCD_OPC_CheckPredicate, 8, 4, 12, // Skip to: 13726 /* 10650 */ MCD_OPC_Decode, 149, 6, 187, 1, // Opcode: FRINT_D /* 10655 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10668 /* 10659 */ MCD_OPC_CheckPredicate, 8, 247, 11, // Skip to: 13726 /* 10663 */ MCD_OPC_Decode, 238, 5, 186, 1, // Opcode: FLOG2_W /* 10668 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10681 /* 10672 */ MCD_OPC_CheckPredicate, 8, 234, 11, // Skip to: 13726 /* 10676 */ MCD_OPC_Decode, 237, 5, 187, 1, // Opcode: FLOG2_D /* 10681 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10694 /* 10685 */ MCD_OPC_CheckPredicate, 8, 221, 11, // Skip to: 13726 /* 10689 */ MCD_OPC_Decode, 220, 5, 188, 1, // Opcode: FEXUPL_W /* 10694 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10707 /* 10698 */ MCD_OPC_CheckPredicate, 8, 208, 11, // Skip to: 13726 /* 10702 */ MCD_OPC_Decode, 219, 5, 189, 1, // Opcode: FEXUPL_D /* 10707 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10720 /* 10711 */ MCD_OPC_CheckPredicate, 8, 195, 11, // Skip to: 13726 /* 10715 */ MCD_OPC_Decode, 222, 5, 188, 1, // Opcode: FEXUPR_W /* 10720 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10733 /* 10724 */ MCD_OPC_CheckPredicate, 8, 182, 11, // Skip to: 13726 /* 10728 */ MCD_OPC_Decode, 221, 5, 189, 1, // Opcode: FEXUPR_D /* 10733 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10746 /* 10737 */ MCD_OPC_CheckPredicate, 8, 169, 11, // Skip to: 13726 /* 10741 */ MCD_OPC_Decode, 228, 5, 188, 1, // Opcode: FFQL_W /* 10746 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10759 /* 10750 */ MCD_OPC_CheckPredicate, 8, 156, 11, // Skip to: 13726 /* 10754 */ MCD_OPC_Decode, 227, 5, 189, 1, // Opcode: FFQL_D /* 10759 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10772 /* 10763 */ MCD_OPC_CheckPredicate, 8, 143, 11, // Skip to: 13726 /* 10767 */ MCD_OPC_Decode, 230, 5, 188, 1, // Opcode: FFQR_W /* 10772 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10785 /* 10776 */ MCD_OPC_CheckPredicate, 8, 130, 11, // Skip to: 13726 /* 10780 */ MCD_OPC_Decode, 229, 5, 189, 1, // Opcode: FFQR_D /* 10785 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10798 /* 10789 */ MCD_OPC_CheckPredicate, 8, 117, 11, // Skip to: 13726 /* 10793 */ MCD_OPC_Decode, 190, 6, 186, 1, // Opcode: FTINT_S_W /* 10798 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10811 /* 10802 */ MCD_OPC_CheckPredicate, 8, 104, 11, // Skip to: 13726 /* 10806 */ MCD_OPC_Decode, 189, 6, 187, 1, // Opcode: FTINT_S_D /* 10811 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10824 /* 10815 */ MCD_OPC_CheckPredicate, 8, 91, 11, // Skip to: 13726 /* 10819 */ MCD_OPC_Decode, 192, 6, 186, 1, // Opcode: FTINT_U_W /* 10824 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10837 /* 10828 */ MCD_OPC_CheckPredicate, 8, 78, 11, // Skip to: 13726 /* 10832 */ MCD_OPC_Decode, 191, 6, 187, 1, // Opcode: FTINT_U_D /* 10837 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10850 /* 10841 */ MCD_OPC_CheckPredicate, 8, 65, 11, // Skip to: 13726 /* 10845 */ MCD_OPC_Decode, 224, 5, 186, 1, // Opcode: FFINT_S_W /* 10850 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10863 /* 10854 */ MCD_OPC_CheckPredicate, 8, 52, 11, // Skip to: 13726 /* 10858 */ MCD_OPC_Decode, 223, 5, 187, 1, // Opcode: FFINT_S_D /* 10863 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10876 /* 10867 */ MCD_OPC_CheckPredicate, 8, 39, 11, // Skip to: 13726 /* 10871 */ MCD_OPC_Decode, 226, 5, 186, 1, // Opcode: FFINT_U_W /* 10876 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13726 /* 10880 */ MCD_OPC_CheckPredicate, 8, 26, 11, // Skip to: 13726 /* 10884 */ MCD_OPC_Decode, 225, 5, 187, 1, // Opcode: FFINT_U_D /* 10889 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10902 /* 10893 */ MCD_OPC_CheckPredicate, 8, 13, 11, // Skip to: 13726 /* 10897 */ MCD_OPC_Decode, 177, 7, 190, 1, // Opcode: LD_B /* 10902 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10915 /* 10906 */ MCD_OPC_CheckPredicate, 8, 0, 11, // Skip to: 13726 /* 10910 */ MCD_OPC_Decode, 179, 7, 190, 1, // Opcode: LD_H /* 10915 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10928 /* 10919 */ MCD_OPC_CheckPredicate, 8, 243, 10, // Skip to: 13726 /* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W /* 10928 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10941 /* 10932 */ MCD_OPC_CheckPredicate, 8, 230, 10, // Skip to: 13726 /* 10936 */ MCD_OPC_Decode, 178, 7, 190, 1, // Opcode: LD_D /* 10941 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10954 /* 10945 */ MCD_OPC_CheckPredicate, 8, 217, 10, // Skip to: 13726 /* 10949 */ MCD_OPC_Decode, 186, 12, 190, 1, // Opcode: ST_B /* 10954 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10967 /* 10958 */ MCD_OPC_CheckPredicate, 8, 204, 10, // Skip to: 13726 /* 10962 */ MCD_OPC_Decode, 188, 12, 190, 1, // Opcode: ST_H /* 10967 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10980 /* 10971 */ MCD_OPC_CheckPredicate, 8, 191, 10, // Skip to: 13726 /* 10975 */ MCD_OPC_Decode, 189, 12, 190, 1, // Opcode: ST_W /* 10980 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13726 /* 10984 */ MCD_OPC_CheckPredicate, 8, 178, 10, // Skip to: 13726 /* 10988 */ MCD_OPC_Decode, 187, 12, 190, 1, // Opcode: ST_D /* 10993 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13414 /* 10997 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 11000 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11013 /* 11004 */ MCD_OPC_CheckPredicate, 6, 158, 10, // Skip to: 13726 /* 11008 */ MCD_OPC_Decode, 145, 5, 191, 1, // Opcode: EXT /* 11013 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11026 /* 11017 */ MCD_OPC_CheckPredicate, 6, 145, 10, // Skip to: 13726 /* 11021 */ MCD_OPC_Decode, 228, 6, 192, 1, // Opcode: INS /* 11026 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 11072 /* 11030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 11033 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11046 /* 11037 */ MCD_OPC_CheckPredicate, 12, 125, 10, // Skip to: 13726 /* 11041 */ MCD_OPC_Decode, 236, 7, 193, 1, // Opcode: LWX /* 11046 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11059 /* 11050 */ MCD_OPC_CheckPredicate, 12, 112, 10, // Skip to: 13726 /* 11054 */ MCD_OPC_Decode, 187, 7, 193, 1, // Opcode: LHX /* 11059 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13726 /* 11063 */ MCD_OPC_CheckPredicate, 12, 99, 10, // Skip to: 13726 /* 11067 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: LBUX /* 11072 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11091 /* 11076 */ MCD_OPC_CheckPredicate, 12, 86, 10, // Skip to: 13726 /* 11080 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13726 /* 11086 */ MCD_OPC_Decode, 241, 6, 194, 1, // Opcode: INSV /* 11091 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11402 /* 11095 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 11098 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11110 /* 11102 */ MCD_OPC_CheckPredicate, 12, 60, 10, // Skip to: 13726 /* 11106 */ MCD_OPC_Decode, 56, 195, 1, // Opcode: ADDU_QB /* 11110 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11123 /* 11114 */ MCD_OPC_CheckPredicate, 12, 48, 10, // Skip to: 13726 /* 11118 */ MCD_OPC_Decode, 218, 12, 195, 1, // Opcode: SUBU_QB /* 11123 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11135 /* 11127 */ MCD_OPC_CheckPredicate, 12, 35, 10, // Skip to: 13726 /* 11131 */ MCD_OPC_Decode, 58, 195, 1, // Opcode: ADDU_S_QB /* 11135 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11148 /* 11139 */ MCD_OPC_CheckPredicate, 12, 23, 10, // Skip to: 13726 /* 11143 */ MCD_OPC_Decode, 220, 12, 195, 1, // Opcode: SUBU_S_QB /* 11148 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11161 /* 11152 */ MCD_OPC_CheckPredicate, 12, 10, 10, // Skip to: 13726 /* 11156 */ MCD_OPC_Decode, 196, 9, 195, 1, // Opcode: MULEU_S_PH_QBL /* 11161 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11174 /* 11165 */ MCD_OPC_CheckPredicate, 12, 253, 9, // Skip to: 13726 /* 11169 */ MCD_OPC_Decode, 197, 9, 195, 1, // Opcode: MULEU_S_PH_QBR /* 11174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11186 /* 11178 */ MCD_OPC_CheckPredicate, 30, 240, 9, // Skip to: 13726 /* 11182 */ MCD_OPC_Decode, 55, 195, 1, // Opcode: ADDU_PH /* 11186 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11199 /* 11190 */ MCD_OPC_CheckPredicate, 30, 228, 9, // Skip to: 13726 /* 11194 */ MCD_OPC_Decode, 217, 12, 195, 1, // Opcode: SUBU_PH /* 11199 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11211 /* 11203 */ MCD_OPC_CheckPredicate, 12, 215, 9, // Skip to: 13726 /* 11207 */ MCD_OPC_Decode, 36, 195, 1, // Opcode: ADDQ_PH /* 11211 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11224 /* 11215 */ MCD_OPC_CheckPredicate, 12, 203, 9, // Skip to: 13726 /* 11219 */ MCD_OPC_Decode, 195, 12, 195, 1, // Opcode: SUBQ_PH /* 11224 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11236 /* 11228 */ MCD_OPC_CheckPredicate, 30, 190, 9, // Skip to: 13726 /* 11232 */ MCD_OPC_Decode, 57, 195, 1, // Opcode: ADDU_S_PH /* 11236 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11249 /* 11240 */ MCD_OPC_CheckPredicate, 30, 178, 9, // Skip to: 13726 /* 11244 */ MCD_OPC_Decode, 219, 12, 195, 1, // Opcode: SUBU_S_PH /* 11249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 11261 /* 11253 */ MCD_OPC_CheckPredicate, 12, 165, 9, // Skip to: 13726 /* 11257 */ MCD_OPC_Decode, 37, 195, 1, // Opcode: ADDQ_S_PH /* 11261 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11274 /* 11265 */ MCD_OPC_CheckPredicate, 12, 153, 9, // Skip to: 13726 /* 11269 */ MCD_OPC_Decode, 196, 12, 195, 1, // Opcode: SUBQ_S_PH /* 11274 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 11285 /* 11278 */ MCD_OPC_CheckPredicate, 12, 140, 9, // Skip to: 13726 /* 11282 */ MCD_OPC_Decode, 39, 35, // Opcode: ADDSC /* 11285 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 11296 /* 11289 */ MCD_OPC_CheckPredicate, 12, 129, 9, // Skip to: 13726 /* 11293 */ MCD_OPC_Decode, 67, 35, // Opcode: ADDWC /* 11296 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 11308 /* 11300 */ MCD_OPC_CheckPredicate, 12, 118, 9, // Skip to: 13726 /* 11304 */ MCD_OPC_Decode, 223, 8, 35, // Opcode: MODSUB /* 11308 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 11327 /* 11312 */ MCD_OPC_CheckPredicate, 12, 106, 9, // Skip to: 13726 /* 11316 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13726 /* 11322 */ MCD_OPC_Decode, 236, 10, 196, 1, // Opcode: RADDU_W_QB /* 11327 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 11338 /* 11331 */ MCD_OPC_CheckPredicate, 12, 87, 9, // Skip to: 13726 /* 11335 */ MCD_OPC_Decode, 38, 35, // Opcode: ADDQ_S_W /* 11338 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11350 /* 11342 */ MCD_OPC_CheckPredicate, 12, 76, 9, // Skip to: 13726 /* 11346 */ MCD_OPC_Decode, 197, 12, 35, // Opcode: SUBQ_S_W /* 11350 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 11363 /* 11354 */ MCD_OPC_CheckPredicate, 12, 64, 9, // Skip to: 13726 /* 11358 */ MCD_OPC_Decode, 194, 9, 197, 1, // Opcode: MULEQ_S_W_PHL /* 11363 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11376 /* 11367 */ MCD_OPC_CheckPredicate, 12, 51, 9, // Skip to: 13726 /* 11371 */ MCD_OPC_Decode, 195, 9, 197, 1, // Opcode: MULEQ_S_W_PHR /* 11376 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11389 /* 11380 */ MCD_OPC_CheckPredicate, 30, 38, 9, // Skip to: 13726 /* 11384 */ MCD_OPC_Decode, 200, 9, 195, 1, // Opcode: MULQ_S_PH /* 11389 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13726 /* 11393 */ MCD_OPC_CheckPredicate, 12, 25, 9, // Skip to: 13726 /* 11397 */ MCD_OPC_Decode, 198, 9, 195, 1, // Opcode: MULQ_RS_PH /* 11402 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11731 /* 11406 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 11409 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11428 /* 11413 */ MCD_OPC_CheckPredicate, 12, 5, 9, // Skip to: 13726 /* 11417 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13726 /* 11423 */ MCD_OPC_Decode, 161, 3, 198, 1, // Opcode: CMPU_EQ_QB /* 11428 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11447 /* 11432 */ MCD_OPC_CheckPredicate, 12, 242, 8, // Skip to: 13726 /* 11436 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13726 /* 11442 */ MCD_OPC_Decode, 163, 3, 198, 1, // Opcode: CMPU_LT_QB /* 11447 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11466 /* 11451 */ MCD_OPC_CheckPredicate, 12, 223, 8, // Skip to: 13726 /* 11455 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13726 /* 11461 */ MCD_OPC_Decode, 162, 3, 198, 1, // Opcode: CMPU_LE_QB /* 11466 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11479 /* 11470 */ MCD_OPC_CheckPredicate, 12, 204, 8, // Skip to: 13726 /* 11474 */ MCD_OPC_Decode, 162, 10, 195, 1, // Opcode: PICK_QB /* 11479 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11492 /* 11483 */ MCD_OPC_CheckPredicate, 12, 191, 8, // Skip to: 13726 /* 11487 */ MCD_OPC_Decode, 158, 3, 197, 1, // Opcode: CMPGU_EQ_QB /* 11492 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11505 /* 11496 */ MCD_OPC_CheckPredicate, 12, 178, 8, // Skip to: 13726 /* 11500 */ MCD_OPC_Decode, 160, 3, 197, 1, // Opcode: CMPGU_LT_QB /* 11505 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11518 /* 11509 */ MCD_OPC_CheckPredicate, 12, 165, 8, // Skip to: 13726 /* 11513 */ MCD_OPC_Decode, 159, 3, 197, 1, // Opcode: CMPGU_LE_QB /* 11518 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11537 /* 11522 */ MCD_OPC_CheckPredicate, 12, 152, 8, // Skip to: 13726 /* 11526 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13726 /* 11532 */ MCD_OPC_Decode, 165, 3, 198, 1, // Opcode: CMP_EQ_PH /* 11537 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11556 /* 11541 */ MCD_OPC_CheckPredicate, 12, 133, 8, // Skip to: 13726 /* 11545 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13726 /* 11551 */ MCD_OPC_Decode, 173, 3, 198, 1, // Opcode: CMP_LT_PH /* 11556 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11575 /* 11560 */ MCD_OPC_CheckPredicate, 12, 114, 8, // Skip to: 13726 /* 11564 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13726 /* 11570 */ MCD_OPC_Decode, 170, 3, 198, 1, // Opcode: CMP_LE_PH /* 11575 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11588 /* 11579 */ MCD_OPC_CheckPredicate, 12, 95, 8, // Skip to: 13726 /* 11583 */ MCD_OPC_Decode, 161, 10, 195, 1, // Opcode: PICK_PH /* 11588 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11601 /* 11592 */ MCD_OPC_CheckPredicate, 12, 82, 8, // Skip to: 13726 /* 11596 */ MCD_OPC_Decode, 176, 10, 195, 1, // Opcode: PRECRQ_QB_PH /* 11601 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11614 /* 11605 */ MCD_OPC_CheckPredicate, 30, 69, 8, // Skip to: 13726 /* 11609 */ MCD_OPC_Decode, 178, 10, 195, 1, // Opcode: PRECR_QB_PH /* 11614 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11627 /* 11618 */ MCD_OPC_CheckPredicate, 12, 56, 8, // Skip to: 13726 /* 11622 */ MCD_OPC_Decode, 146, 10, 195, 1, // Opcode: PACKRL_PH /* 11627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11640 /* 11631 */ MCD_OPC_CheckPredicate, 12, 43, 8, // Skip to: 13726 /* 11635 */ MCD_OPC_Decode, 174, 10, 195, 1, // Opcode: PRECRQU_S_QB_PH /* 11640 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11653 /* 11644 */ MCD_OPC_CheckPredicate, 12, 30, 8, // Skip to: 13726 /* 11648 */ MCD_OPC_Decode, 175, 10, 199, 1, // Opcode: PRECRQ_PH_W /* 11653 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11666 /* 11657 */ MCD_OPC_CheckPredicate, 12, 17, 8, // Skip to: 13726 /* 11661 */ MCD_OPC_Decode, 177, 10, 199, 1, // Opcode: PRECRQ_RS_PH_W /* 11666 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11679 /* 11670 */ MCD_OPC_CheckPredicate, 30, 4, 8, // Skip to: 13726 /* 11674 */ MCD_OPC_Decode, 155, 3, 197, 1, // Opcode: CMPGDU_EQ_QB /* 11679 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11692 /* 11683 */ MCD_OPC_CheckPredicate, 30, 247, 7, // Skip to: 13726 /* 11687 */ MCD_OPC_Decode, 157, 3, 197, 1, // Opcode: CMPGDU_LT_QB /* 11692 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11705 /* 11696 */ MCD_OPC_CheckPredicate, 30, 234, 7, // Skip to: 13726 /* 11700 */ MCD_OPC_Decode, 156, 3, 197, 1, // Opcode: CMPGDU_LE_QB /* 11705 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11718 /* 11709 */ MCD_OPC_CheckPredicate, 30, 221, 7, // Skip to: 13726 /* 11713 */ MCD_OPC_Decode, 179, 10, 200, 1, // Opcode: PRECR_SRA_PH_W /* 11718 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13726 /* 11722 */ MCD_OPC_CheckPredicate, 30, 208, 7, // Skip to: 13726 /* 11726 */ MCD_OPC_Decode, 180, 10, 200, 1, // Opcode: PRECR_SRA_R_PH_W /* 11731 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 12065 /* 11735 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 11738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11756 /* 11742 */ MCD_OPC_CheckPredicate, 30, 188, 7, // Skip to: 13726 /* 11746 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13726 /* 11752 */ MCD_OPC_Decode, 23, 201, 1, // Opcode: ABSQ_S_QB /* 11756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11769 /* 11760 */ MCD_OPC_CheckPredicate, 12, 170, 7, // Skip to: 13726 /* 11764 */ MCD_OPC_Decode, 244, 10, 202, 1, // Opcode: REPL_QB /* 11769 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11788 /* 11773 */ MCD_OPC_CheckPredicate, 12, 157, 7, // Skip to: 13726 /* 11777 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13726 /* 11783 */ MCD_OPC_Decode, 242, 10, 203, 1, // Opcode: REPLV_QB /* 11788 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11807 /* 11792 */ MCD_OPC_CheckPredicate, 12, 138, 7, // Skip to: 13726 /* 11796 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13726 /* 11802 */ MCD_OPC_Decode, 164, 10, 201, 1, // Opcode: PRECEQU_PH_QBL /* 11807 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11826 /* 11811 */ MCD_OPC_CheckPredicate, 12, 119, 7, // Skip to: 13726 /* 11815 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13726 /* 11821 */ MCD_OPC_Decode, 166, 10, 201, 1, // Opcode: PRECEQU_PH_QBR /* 11826 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11845 /* 11830 */ MCD_OPC_CheckPredicate, 12, 100, 7, // Skip to: 13726 /* 11834 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13726 /* 11840 */ MCD_OPC_Decode, 165, 10, 201, 1, // Opcode: PRECEQU_PH_QBLA /* 11845 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11864 /* 11849 */ MCD_OPC_CheckPredicate, 12, 81, 7, // Skip to: 13726 /* 11853 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13726 /* 11859 */ MCD_OPC_Decode, 167, 10, 201, 1, // Opcode: PRECEQU_PH_QBRA /* 11864 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11882 /* 11868 */ MCD_OPC_CheckPredicate, 12, 62, 7, // Skip to: 13726 /* 11872 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13726 /* 11878 */ MCD_OPC_Decode, 22, 201, 1, // Opcode: ABSQ_S_PH /* 11882 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11895 /* 11886 */ MCD_OPC_CheckPredicate, 12, 44, 7, // Skip to: 13726 /* 11890 */ MCD_OPC_Decode, 243, 10, 202, 1, // Opcode: REPL_PH /* 11895 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11914 /* 11899 */ MCD_OPC_CheckPredicate, 12, 31, 7, // Skip to: 13726 /* 11903 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13726 /* 11909 */ MCD_OPC_Decode, 241, 10, 203, 1, // Opcode: REPLV_PH /* 11914 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11933 /* 11918 */ MCD_OPC_CheckPredicate, 12, 12, 7, // Skip to: 13726 /* 11922 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13726 /* 11928 */ MCD_OPC_Decode, 168, 10, 204, 1, // Opcode: PRECEQ_W_PHL /* 11933 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11952 /* 11937 */ MCD_OPC_CheckPredicate, 12, 249, 6, // Skip to: 13726 /* 11941 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13726 /* 11947 */ MCD_OPC_Decode, 169, 10, 204, 1, // Opcode: PRECEQ_W_PHR /* 11952 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11970 /* 11956 */ MCD_OPC_CheckPredicate, 12, 230, 6, // Skip to: 13726 /* 11960 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13726 /* 11966 */ MCD_OPC_Decode, 24, 205, 1, // Opcode: ABSQ_S_W /* 11970 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11989 /* 11974 */ MCD_OPC_CheckPredicate, 12, 212, 6, // Skip to: 13726 /* 11978 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13726 /* 11984 */ MCD_OPC_Decode, 249, 1, 205, 1, // Opcode: BITREV /* 11989 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 12008 /* 11993 */ MCD_OPC_CheckPredicate, 12, 193, 6, // Skip to: 13726 /* 11997 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13726 /* 12003 */ MCD_OPC_Decode, 170, 10, 201, 1, // Opcode: PRECEU_PH_QBL /* 12008 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 12027 /* 12012 */ MCD_OPC_CheckPredicate, 12, 174, 6, // Skip to: 13726 /* 12016 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13726 /* 12022 */ MCD_OPC_Decode, 172, 10, 201, 1, // Opcode: PRECEU_PH_QBR /* 12027 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 12046 /* 12031 */ MCD_OPC_CheckPredicate, 12, 155, 6, // Skip to: 13726 /* 12035 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13726 /* 12041 */ MCD_OPC_Decode, 171, 10, 201, 1, // Opcode: PRECEU_PH_QBLA /* 12046 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13726 /* 12050 */ MCD_OPC_CheckPredicate, 12, 136, 6, // Skip to: 13726 /* 12054 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13726 /* 12060 */ MCD_OPC_Decode, 173, 10, 201, 1, // Opcode: PRECEU_PH_QBRA /* 12065 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 12356 /* 12069 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 12072 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12085 /* 12076 */ MCD_OPC_CheckPredicate, 12, 110, 6, // Skip to: 13726 /* 12080 */ MCD_OPC_Decode, 199, 11, 206, 1, // Opcode: SHLL_QB /* 12085 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12098 /* 12089 */ MCD_OPC_CheckPredicate, 12, 97, 6, // Skip to: 13726 /* 12093 */ MCD_OPC_Decode, 215, 11, 206, 1, // Opcode: SHRL_QB /* 12098 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12111 /* 12102 */ MCD_OPC_CheckPredicate, 12, 84, 6, // Skip to: 13726 /* 12106 */ MCD_OPC_Decode, 195, 11, 207, 1, // Opcode: SHLLV_QB /* 12111 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12124 /* 12115 */ MCD_OPC_CheckPredicate, 12, 71, 6, // Skip to: 13726 /* 12119 */ MCD_OPC_Decode, 213, 11, 207, 1, // Opcode: SHRLV_QB /* 12124 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12137 /* 12128 */ MCD_OPC_CheckPredicate, 30, 58, 6, // Skip to: 13726 /* 12132 */ MCD_OPC_Decode, 208, 11, 206, 1, // Opcode: SHRA_QB /* 12137 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 12150 /* 12141 */ MCD_OPC_CheckPredicate, 30, 45, 6, // Skip to: 13726 /* 12145 */ MCD_OPC_Decode, 210, 11, 206, 1, // Opcode: SHRA_R_QB /* 12150 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 12163 /* 12154 */ MCD_OPC_CheckPredicate, 30, 32, 6, // Skip to: 13726 /* 12158 */ MCD_OPC_Decode, 203, 11, 207, 1, // Opcode: SHRAV_QB /* 12163 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 12176 /* 12167 */ MCD_OPC_CheckPredicate, 30, 19, 6, // Skip to: 13726 /* 12171 */ MCD_OPC_Decode, 205, 11, 207, 1, // Opcode: SHRAV_R_QB /* 12176 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 12189 /* 12180 */ MCD_OPC_CheckPredicate, 12, 6, 6, // Skip to: 13726 /* 12184 */ MCD_OPC_Decode, 198, 11, 206, 1, // Opcode: SHLL_PH /* 12189 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12202 /* 12193 */ MCD_OPC_CheckPredicate, 12, 249, 5, // Skip to: 13726 /* 12197 */ MCD_OPC_Decode, 207, 11, 206, 1, // Opcode: SHRA_PH /* 12202 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 12215 /* 12206 */ MCD_OPC_CheckPredicate, 12, 236, 5, // Skip to: 13726 /* 12210 */ MCD_OPC_Decode, 194, 11, 207, 1, // Opcode: SHLLV_PH /* 12215 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12228 /* 12219 */ MCD_OPC_CheckPredicate, 12, 223, 5, // Skip to: 13726 /* 12223 */ MCD_OPC_Decode, 202, 11, 207, 1, // Opcode: SHRAV_PH /* 12228 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12241 /* 12232 */ MCD_OPC_CheckPredicate, 12, 210, 5, // Skip to: 13726 /* 12236 */ MCD_OPC_Decode, 200, 11, 206, 1, // Opcode: SHLL_S_PH /* 12241 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 12254 /* 12245 */ MCD_OPC_CheckPredicate, 12, 197, 5, // Skip to: 13726 /* 12249 */ MCD_OPC_Decode, 209, 11, 206, 1, // Opcode: SHRA_R_PH /* 12254 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12267 /* 12258 */ MCD_OPC_CheckPredicate, 12, 184, 5, // Skip to: 13726 /* 12262 */ MCD_OPC_Decode, 196, 11, 207, 1, // Opcode: SHLLV_S_PH /* 12267 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 12280 /* 12271 */ MCD_OPC_CheckPredicate, 12, 171, 5, // Skip to: 13726 /* 12275 */ MCD_OPC_Decode, 204, 11, 207, 1, // Opcode: SHRAV_R_PH /* 12280 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 12293 /* 12284 */ MCD_OPC_CheckPredicate, 12, 158, 5, // Skip to: 13726 /* 12288 */ MCD_OPC_Decode, 201, 11, 208, 1, // Opcode: SHLL_S_W /* 12293 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 12306 /* 12297 */ MCD_OPC_CheckPredicate, 12, 145, 5, // Skip to: 13726 /* 12301 */ MCD_OPC_Decode, 211, 11, 208, 1, // Opcode: SHRA_R_W /* 12306 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12318 /* 12310 */ MCD_OPC_CheckPredicate, 12, 132, 5, // Skip to: 13726 /* 12314 */ MCD_OPC_Decode, 197, 11, 36, // Opcode: SHLLV_S_W /* 12318 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 12330 /* 12322 */ MCD_OPC_CheckPredicate, 12, 120, 5, // Skip to: 13726 /* 12326 */ MCD_OPC_Decode, 206, 11, 36, // Opcode: SHRAV_R_W /* 12330 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 12343 /* 12334 */ MCD_OPC_CheckPredicate, 30, 108, 5, // Skip to: 13726 /* 12338 */ MCD_OPC_Decode, 214, 11, 206, 1, // Opcode: SHRL_PH /* 12343 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13726 /* 12347 */ MCD_OPC_CheckPredicate, 30, 95, 5, // Skip to: 13726 /* 12351 */ MCD_OPC_Decode, 212, 11, 207, 1, // Opcode: SHRLV_PH /* 12356 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12559 /* 12360 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 12363 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12375 /* 12367 */ MCD_OPC_CheckPredicate, 30, 75, 5, // Skip to: 13726 /* 12371 */ MCD_OPC_Decode, 53, 195, 1, // Opcode: ADDUH_QB /* 12375 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12388 /* 12379 */ MCD_OPC_CheckPredicate, 30, 63, 5, // Skip to: 13726 /* 12383 */ MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: SUBUH_QB /* 12388 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12400 /* 12392 */ MCD_OPC_CheckPredicate, 30, 50, 5, // Skip to: 13726 /* 12396 */ MCD_OPC_Decode, 54, 195, 1, // Opcode: ADDUH_R_QB /* 12400 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12413 /* 12404 */ MCD_OPC_CheckPredicate, 30, 38, 5, // Skip to: 13726 /* 12408 */ MCD_OPC_Decode, 216, 12, 195, 1, // Opcode: SUBUH_R_QB /* 12413 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12425 /* 12417 */ MCD_OPC_CheckPredicate, 30, 25, 5, // Skip to: 13726 /* 12421 */ MCD_OPC_Decode, 32, 195, 1, // Opcode: ADDQH_PH /* 12425 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12438 /* 12429 */ MCD_OPC_CheckPredicate, 30, 13, 5, // Skip to: 13726 /* 12433 */ MCD_OPC_Decode, 191, 12, 195, 1, // Opcode: SUBQH_PH /* 12438 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12450 /* 12442 */ MCD_OPC_CheckPredicate, 30, 0, 5, // Skip to: 13726 /* 12446 */ MCD_OPC_Decode, 33, 195, 1, // Opcode: ADDQH_R_PH /* 12450 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12463 /* 12454 */ MCD_OPC_CheckPredicate, 30, 244, 4, // Skip to: 13726 /* 12458 */ MCD_OPC_Decode, 192, 12, 195, 1, // Opcode: SUBQH_R_PH /* 12463 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12476 /* 12467 */ MCD_OPC_CheckPredicate, 30, 231, 4, // Skip to: 13726 /* 12471 */ MCD_OPC_Decode, 218, 9, 195, 1, // Opcode: MUL_PH /* 12476 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12489 /* 12480 */ MCD_OPC_CheckPredicate, 30, 218, 4, // Skip to: 13726 /* 12484 */ MCD_OPC_Decode, 222, 9, 195, 1, // Opcode: MUL_S_PH /* 12489 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12500 /* 12493 */ MCD_OPC_CheckPredicate, 30, 205, 4, // Skip to: 13726 /* 12497 */ MCD_OPC_Decode, 35, 35, // Opcode: ADDQH_W /* 12500 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12512 /* 12504 */ MCD_OPC_CheckPredicate, 30, 194, 4, // Skip to: 13726 /* 12508 */ MCD_OPC_Decode, 194, 12, 35, // Opcode: SUBQH_W /* 12512 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12523 /* 12516 */ MCD_OPC_CheckPredicate, 30, 182, 4, // Skip to: 13726 /* 12520 */ MCD_OPC_Decode, 34, 35, // Opcode: ADDQH_R_W /* 12523 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12535 /* 12527 */ MCD_OPC_CheckPredicate, 30, 171, 4, // Skip to: 13726 /* 12531 */ MCD_OPC_Decode, 193, 12, 35, // Opcode: SUBQH_R_W /* 12535 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12547 /* 12539 */ MCD_OPC_CheckPredicate, 30, 159, 4, // Skip to: 13726 /* 12543 */ MCD_OPC_Decode, 201, 9, 35, // Opcode: MULQ_S_W /* 12547 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13726 /* 12551 */ MCD_OPC_CheckPredicate, 30, 147, 4, // Skip to: 13726 /* 12555 */ MCD_OPC_Decode, 199, 9, 35, // Opcode: MULQ_RS_W /* 12559 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12623 /* 12563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 12566 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12585 /* 12570 */ MCD_OPC_CheckPredicate, 6, 128, 4, // Skip to: 13726 /* 12574 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13726 /* 12580 */ MCD_OPC_Decode, 234, 13, 205, 1, // Opcode: WSBH /* 12585 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12604 /* 12589 */ MCD_OPC_CheckPredicate, 6, 109, 4, // Skip to: 13726 /* 12593 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13726 /* 12599 */ MCD_OPC_Decode, 168, 11, 205, 1, // Opcode: SEB /* 12604 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13726 /* 12608 */ MCD_OPC_CheckPredicate, 6, 90, 4, // Skip to: 13726 /* 12612 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13726 /* 12618 */ MCD_OPC_Decode, 171, 11, 205, 1, // Opcode: SEH /* 12623 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 13026 /* 12627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 12630 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12648 /* 12634 */ MCD_OPC_CheckPredicate, 30, 64, 4, // Skip to: 13726 /* 12638 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13726 /* 12644 */ MCD_OPC_Decode, 230, 4, 116, // Opcode: DPA_W_PH /* 12648 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12666 /* 12652 */ MCD_OPC_CheckPredicate, 30, 46, 4, // Skip to: 13726 /* 12656 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13726 /* 12662 */ MCD_OPC_Decode, 245, 4, 116, // Opcode: DPS_W_PH /* 12666 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12684 /* 12670 */ MCD_OPC_CheckPredicate, 30, 28, 4, // Skip to: 13726 /* 12674 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13726 /* 12680 */ MCD_OPC_Decode, 205, 9, 116, // Opcode: MULSA_W_PH /* 12684 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12702 /* 12688 */ MCD_OPC_CheckPredicate, 12, 10, 4, // Skip to: 13726 /* 12692 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13726 /* 12698 */ MCD_OPC_Decode, 227, 4, 116, // Opcode: DPAU_H_QBL /* 12702 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12720 /* 12706 */ MCD_OPC_CheckPredicate, 12, 248, 3, // Skip to: 13726 /* 12710 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13726 /* 12716 */ MCD_OPC_Decode, 226, 4, 116, // Opcode: DPAQ_S_W_PH /* 12720 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12738 /* 12724 */ MCD_OPC_CheckPredicate, 12, 230, 3, // Skip to: 13726 /* 12728 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13726 /* 12734 */ MCD_OPC_Decode, 235, 4, 116, // Opcode: DPSQ_S_W_PH /* 12738 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12756 /* 12742 */ MCD_OPC_CheckPredicate, 12, 212, 3, // Skip to: 13726 /* 12746 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13726 /* 12752 */ MCD_OPC_Decode, 204, 9, 116, // Opcode: MULSAQ_S_W_PH /* 12756 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12774 /* 12760 */ MCD_OPC_CheckPredicate, 12, 194, 3, // Skip to: 13726 /* 12764 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13726 /* 12770 */ MCD_OPC_Decode, 228, 4, 116, // Opcode: DPAU_H_QBR /* 12774 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12792 /* 12778 */ MCD_OPC_CheckPredicate, 30, 176, 3, // Skip to: 13726 /* 12782 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13726 /* 12788 */ MCD_OPC_Decode, 229, 4, 116, // Opcode: DPAX_W_PH /* 12792 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12810 /* 12796 */ MCD_OPC_CheckPredicate, 30, 158, 3, // Skip to: 13726 /* 12800 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13726 /* 12806 */ MCD_OPC_Decode, 244, 4, 116, // Opcode: DPSX_W_PH /* 12810 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12828 /* 12814 */ MCD_OPC_CheckPredicate, 12, 140, 3, // Skip to: 13726 /* 12818 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13726 /* 12824 */ MCD_OPC_Decode, 242, 4, 116, // Opcode: DPSU_H_QBL /* 12828 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12846 /* 12832 */ MCD_OPC_CheckPredicate, 12, 122, 3, // Skip to: 13726 /* 12836 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13726 /* 12842 */ MCD_OPC_Decode, 225, 4, 116, // Opcode: DPAQ_SA_L_W /* 12846 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12864 /* 12850 */ MCD_OPC_CheckPredicate, 12, 104, 3, // Skip to: 13726 /* 12854 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13726 /* 12860 */ MCD_OPC_Decode, 234, 4, 116, // Opcode: DPSQ_SA_L_W /* 12864 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12882 /* 12868 */ MCD_OPC_CheckPredicate, 12, 86, 3, // Skip to: 13726 /* 12872 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13726 /* 12878 */ MCD_OPC_Decode, 243, 4, 116, // Opcode: DPSU_H_QBR /* 12882 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12900 /* 12886 */ MCD_OPC_CheckPredicate, 12, 68, 3, // Skip to: 13726 /* 12890 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13726 /* 12896 */ MCD_OPC_Decode, 151, 8, 116, // Opcode: MAQ_SA_W_PHL /* 12900 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12918 /* 12904 */ MCD_OPC_CheckPredicate, 12, 50, 3, // Skip to: 13726 /* 12908 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13726 /* 12914 */ MCD_OPC_Decode, 152, 8, 116, // Opcode: MAQ_SA_W_PHR /* 12918 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12936 /* 12922 */ MCD_OPC_CheckPredicate, 12, 32, 3, // Skip to: 13726 /* 12926 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13726 /* 12932 */ MCD_OPC_Decode, 153, 8, 116, // Opcode: MAQ_S_W_PHL /* 12936 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12954 /* 12940 */ MCD_OPC_CheckPredicate, 12, 14, 3, // Skip to: 13726 /* 12944 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13726 /* 12950 */ MCD_OPC_Decode, 154, 8, 116, // Opcode: MAQ_S_W_PHR /* 12954 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12972 /* 12958 */ MCD_OPC_CheckPredicate, 30, 252, 2, // Skip to: 13726 /* 12962 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13726 /* 12968 */ MCD_OPC_Decode, 224, 4, 116, // Opcode: DPAQX_S_W_PH /* 12972 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12990 /* 12976 */ MCD_OPC_CheckPredicate, 30, 234, 2, // Skip to: 13726 /* 12980 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13726 /* 12986 */ MCD_OPC_Decode, 233, 4, 116, // Opcode: DPSQX_S_W_PH /* 12990 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 13008 /* 12994 */ MCD_OPC_CheckPredicate, 30, 216, 2, // Skip to: 13726 /* 12998 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13726 /* 13004 */ MCD_OPC_Decode, 223, 4, 116, // Opcode: DPAQX_SA_W_PH /* 13008 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13726 /* 13012 */ MCD_OPC_CheckPredicate, 30, 198, 2, // Skip to: 13726 /* 13016 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13726 /* 13022 */ MCD_OPC_Decode, 232, 4, 116, // Opcode: DPSQX_SA_W_PH /* 13026 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 13071 /* 13030 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 13033 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13045 /* 13037 */ MCD_OPC_CheckPredicate, 30, 173, 2, // Skip to: 13726 /* 13041 */ MCD_OPC_Decode, 96, 209, 1, // Opcode: APPEND /* 13045 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13058 /* 13049 */ MCD_OPC_CheckPredicate, 30, 161, 2, // Skip to: 13726 /* 13053 */ MCD_OPC_Decode, 184, 10, 209, 1, // Opcode: PREPEND /* 13058 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13726 /* 13062 */ MCD_OPC_CheckPredicate, 30, 148, 2, // Skip to: 13726 /* 13066 */ MCD_OPC_Decode, 169, 1, 209, 1, // Opcode: BALIGN /* 13071 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13389 /* 13075 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 13078 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13097 /* 13082 */ MCD_OPC_CheckPredicate, 12, 128, 2, // Skip to: 13726 /* 13086 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13726 /* 13092 */ MCD_OPC_Decode, 157, 5, 210, 1, // Opcode: EXTR_W /* 13097 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 13116 /* 13101 */ MCD_OPC_CheckPredicate, 12, 109, 2, // Skip to: 13726 /* 13105 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13726 /* 13111 */ MCD_OPC_Decode, 153, 5, 211, 1, // Opcode: EXTRV_W /* 13116 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 13135 /* 13120 */ MCD_OPC_CheckPredicate, 12, 90, 2, // Skip to: 13726 /* 13124 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13726 /* 13130 */ MCD_OPC_Decode, 146, 5, 210, 1, // Opcode: EXTP /* 13135 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 13154 /* 13139 */ MCD_OPC_CheckPredicate, 12, 71, 2, // Skip to: 13726 /* 13143 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13726 /* 13149 */ MCD_OPC_Decode, 149, 5, 211, 1, // Opcode: EXTPV /* 13154 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 13173 /* 13158 */ MCD_OPC_CheckPredicate, 12, 52, 2, // Skip to: 13726 /* 13162 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13726 /* 13168 */ MCD_OPC_Decode, 155, 5, 210, 1, // Opcode: EXTR_R_W /* 13173 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 13192 /* 13177 */ MCD_OPC_CheckPredicate, 12, 33, 2, // Skip to: 13726 /* 13181 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13726 /* 13187 */ MCD_OPC_Decode, 151, 5, 211, 1, // Opcode: EXTRV_R_W /* 13192 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 13211 /* 13196 */ MCD_OPC_CheckPredicate, 12, 14, 2, // Skip to: 13726 /* 13200 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13726 /* 13206 */ MCD_OPC_Decode, 154, 5, 210, 1, // Opcode: EXTR_RS_W /* 13211 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 13230 /* 13215 */ MCD_OPC_CheckPredicate, 12, 251, 1, // Skip to: 13726 /* 13219 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13726 /* 13225 */ MCD_OPC_Decode, 150, 5, 211, 1, // Opcode: EXTRV_RS_W /* 13230 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 13249 /* 13234 */ MCD_OPC_CheckPredicate, 12, 232, 1, // Skip to: 13726 /* 13238 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13726 /* 13244 */ MCD_OPC_Decode, 147, 5, 210, 1, // Opcode: EXTPDP /* 13249 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 13268 /* 13253 */ MCD_OPC_CheckPredicate, 12, 213, 1, // Skip to: 13726 /* 13257 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13726 /* 13263 */ MCD_OPC_Decode, 148, 5, 211, 1, // Opcode: EXTPDPV /* 13268 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 13287 /* 13272 */ MCD_OPC_CheckPredicate, 12, 194, 1, // Skip to: 13726 /* 13276 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13726 /* 13282 */ MCD_OPC_Decode, 156, 5, 210, 1, // Opcode: EXTR_S_H /* 13287 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 13306 /* 13291 */ MCD_OPC_CheckPredicate, 12, 175, 1, // Skip to: 13726 /* 13295 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13726 /* 13301 */ MCD_OPC_Decode, 152, 5, 211, 1, // Opcode: EXTRV_S_H /* 13306 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 13319 /* 13310 */ MCD_OPC_CheckPredicate, 12, 156, 1, // Skip to: 13726 /* 13314 */ MCD_OPC_Decode, 237, 10, 212, 1, // Opcode: RDDSP /* 13319 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 13332 /* 13323 */ MCD_OPC_CheckPredicate, 12, 143, 1, // Skip to: 13726 /* 13327 */ MCD_OPC_Decode, 233, 13, 213, 1, // Opcode: WRDSP /* 13332 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 13351 /* 13336 */ MCD_OPC_CheckPredicate, 12, 130, 1, // Skip to: 13726 /* 13340 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13726 /* 13346 */ MCD_OPC_Decode, 192, 11, 214, 1, // Opcode: SHILO /* 13351 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 13370 /* 13355 */ MCD_OPC_CheckPredicate, 12, 111, 1, // Skip to: 13726 /* 13359 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13726 /* 13365 */ MCD_OPC_Decode, 193, 11, 215, 1, // Opcode: SHILOV /* 13370 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13726 /* 13374 */ MCD_OPC_CheckPredicate, 12, 92, 1, // Skip to: 13726 /* 13378 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13726 /* 13384 */ MCD_OPC_Decode, 180, 9, 215, 1, // Opcode: MTHLIP /* 13389 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13726 /* 13393 */ MCD_OPC_CheckPredicate, 5, 73, 1, // Skip to: 13726 /* 13397 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13726 /* 13403 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13726 /* 13409 */ MCD_OPC_Decode, 238, 10, 216, 1, // Opcode: RDHWR /* 13414 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13427 /* 13418 */ MCD_OPC_CheckPredicate, 5, 48, 1, // Skip to: 13726 /* 13422 */ MCD_OPC_Decode, 153, 7, 217, 1, // Opcode: LB /* 13427 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13440 /* 13431 */ MCD_OPC_CheckPredicate, 5, 35, 1, // Skip to: 13726 /* 13435 */ MCD_OPC_Decode, 184, 7, 217, 1, // Opcode: LH /* 13440 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13453 /* 13444 */ MCD_OPC_CheckPredicate, 11, 22, 1, // Skip to: 13726 /* 13448 */ MCD_OPC_Decode, 222, 7, 217, 1, // Opcode: LWL /* 13453 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13466 /* 13457 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13726 /* 13461 */ MCD_OPC_Decode, 213, 7, 217, 1, // Opcode: LW /* 13466 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13479 /* 13470 */ MCD_OPC_CheckPredicate, 5, 252, 0, // Skip to: 13726 /* 13474 */ MCD_OPC_Decode, 158, 7, 217, 1, // Opcode: LBu /* 13479 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13492 /* 13483 */ MCD_OPC_CheckPredicate, 5, 239, 0, // Skip to: 13726 /* 13487 */ MCD_OPC_Decode, 189, 7, 217, 1, // Opcode: LHu /* 13492 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13505 /* 13496 */ MCD_OPC_CheckPredicate, 11, 226, 0, // Skip to: 13726 /* 13500 */ MCD_OPC_Decode, 230, 7, 217, 1, // Opcode: LWR /* 13505 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13518 /* 13509 */ MCD_OPC_CheckPredicate, 5, 213, 0, // Skip to: 13726 /* 13513 */ MCD_OPC_Decode, 142, 11, 217, 1, // Opcode: SB /* 13518 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13531 /* 13522 */ MCD_OPC_CheckPredicate, 5, 200, 0, // Skip to: 13726 /* 13526 */ MCD_OPC_Decode, 186, 11, 217, 1, // Opcode: SH /* 13531 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13544 /* 13535 */ MCD_OPC_CheckPredicate, 11, 187, 0, // Skip to: 13726 /* 13539 */ MCD_OPC_Decode, 243, 12, 217, 1, // Opcode: SWL /* 13544 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13557 /* 13548 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13726 /* 13552 */ MCD_OPC_Decode, 235, 12, 217, 1, // Opcode: SW /* 13557 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13570 /* 13561 */ MCD_OPC_CheckPredicate, 11, 161, 0, // Skip to: 13726 /* 13565 */ MCD_OPC_Decode, 250, 12, 217, 1, // Opcode: SWR /* 13570 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13583 /* 13574 */ MCD_OPC_CheckPredicate, 31, 148, 0, // Skip to: 13726 /* 13578 */ MCD_OPC_Decode, 220, 2, 218, 1, // Opcode: CACHE /* 13583 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13596 /* 13587 */ MCD_OPC_CheckPredicate, 32, 135, 0, // Skip to: 13726 /* 13591 */ MCD_OPC_Decode, 193, 7, 217, 1, // Opcode: LL /* 13596 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13609 /* 13600 */ MCD_OPC_CheckPredicate, 5, 122, 0, // Skip to: 13726 /* 13604 */ MCD_OPC_Decode, 216, 7, 219, 1, // Opcode: LWC1 /* 13609 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13622 /* 13613 */ MCD_OPC_CheckPredicate, 33, 109, 0, // Skip to: 13726 /* 13617 */ MCD_OPC_Decode, 218, 7, 220, 1, // Opcode: LWC2 /* 13622 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13635 /* 13626 */ MCD_OPC_CheckPredicate, 31, 96, 0, // Skip to: 13726 /* 13630 */ MCD_OPC_Decode, 181, 10, 218, 1, // Opcode: PREF /* 13635 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13648 /* 13639 */ MCD_OPC_CheckPredicate, 34, 83, 0, // Skip to: 13726 /* 13643 */ MCD_OPC_Decode, 162, 7, 219, 1, // Opcode: LDC1 /* 13648 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13661 /* 13652 */ MCD_OPC_CheckPredicate, 35, 70, 0, // Skip to: 13726 /* 13656 */ MCD_OPC_Decode, 165, 7, 220, 1, // Opcode: LDC2 /* 13661 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13674 /* 13665 */ MCD_OPC_CheckPredicate, 32, 57, 0, // Skip to: 13726 /* 13669 */ MCD_OPC_Decode, 146, 11, 217, 1, // Opcode: SC /* 13674 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13687 /* 13678 */ MCD_OPC_CheckPredicate, 5, 44, 0, // Skip to: 13726 /* 13682 */ MCD_OPC_Decode, 238, 12, 219, 1, // Opcode: SWC1 /* 13687 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13700 /* 13691 */ MCD_OPC_CheckPredicate, 33, 31, 0, // Skip to: 13726 /* 13695 */ MCD_OPC_Decode, 240, 12, 220, 1, // Opcode: SWC2 /* 13700 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13713 /* 13704 */ MCD_OPC_CheckPredicate, 34, 18, 0, // Skip to: 13726 /* 13708 */ MCD_OPC_Decode, 156, 11, 219, 1, // Opcode: SDC1 /* 13713 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13726 /* 13717 */ MCD_OPC_CheckPredicate, 35, 5, 0, // Skip to: 13726 /* 13721 */ MCD_OPC_Decode, 159, 11, 220, 1, // Opcode: SDC2 /* 13726 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32r6_64r632[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 /* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 /* 14 */ MCD_OPC_CheckPredicate, 36, 37, 7, // Skip to: 1847 /* 18 */ MCD_OPC_CheckField, 8, 3, 0, 31, 7, // Skip to: 1847 /* 24 */ MCD_OPC_Decode, 206, 7, 221, 1, // Opcode: LSA_R6 /* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 /* 33 */ MCD_OPC_CheckPredicate, 36, 18, 7, // Skip to: 1847 /* 37 */ MCD_OPC_CheckField, 6, 15, 16, 12, 7, // Skip to: 1847 /* 43 */ MCD_OPC_Decode, 142, 7, 61, // Opcode: JR_HB_R6 /* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 /* 51 */ MCD_OPC_CheckPredicate, 36, 0, 7, // Skip to: 1847 /* 55 */ MCD_OPC_Decode, 155, 11, 64, // Opcode: SDBBP_R6 /* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 /* 63 */ MCD_OPC_CheckPredicate, 36, 244, 6, // Skip to: 1847 /* 67 */ MCD_OPC_CheckField, 16, 5, 0, 238, 6, // Skip to: 1847 /* 73 */ MCD_OPC_CheckField, 6, 5, 1, 232, 6, // Skip to: 1847 /* 79 */ MCD_OPC_Decode, 154, 3, 62, // Opcode: CLZ_R6 /* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 /* 87 */ MCD_OPC_CheckPredicate, 36, 220, 6, // Skip to: 1847 /* 91 */ MCD_OPC_CheckField, 16, 5, 0, 214, 6, // Skip to: 1847 /* 97 */ MCD_OPC_CheckField, 6, 5, 1, 208, 6, // Skip to: 1847 /* 103 */ MCD_OPC_Decode, 135, 3, 62, // Opcode: CLO_R6 /* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 /* 111 */ MCD_OPC_CheckPredicate, 37, 196, 6, // Skip to: 1847 /* 115 */ MCD_OPC_CheckField, 16, 5, 0, 190, 6, // Skip to: 1847 /* 121 */ MCD_OPC_CheckField, 6, 5, 1, 184, 6, // Skip to: 1847 /* 127 */ MCD_OPC_Decode, 171, 4, 222, 1, // Opcode: DCLZ_R6 /* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 /* 136 */ MCD_OPC_CheckPredicate, 37, 171, 6, // Skip to: 1847 /* 140 */ MCD_OPC_CheckField, 16, 5, 0, 165, 6, // Skip to: 1847 /* 146 */ MCD_OPC_CheckField, 6, 5, 1, 159, 6, // Skip to: 1847 /* 152 */ MCD_OPC_Decode, 169, 4, 222, 1, // Opcode: DCLO_R6 /* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 /* 161 */ MCD_OPC_CheckPredicate, 37, 146, 6, // Skip to: 1847 /* 165 */ MCD_OPC_CheckField, 8, 3, 0, 140, 6, // Skip to: 1847 /* 171 */ MCD_OPC_Decode, 195, 4, 223, 1, // Opcode: DLSA_R6 /* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 /* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 /* 187 */ MCD_OPC_CheckPredicate, 36, 120, 6, // Skip to: 1847 /* 191 */ MCD_OPC_Decode, 221, 9, 35, // Opcode: MUL_R6 /* 195 */ MCD_OPC_FilterValue, 3, 112, 6, // Skip to: 1847 /* 199 */ MCD_OPC_CheckPredicate, 36, 108, 6, // Skip to: 1847 /* 203 */ MCD_OPC_Decode, 191, 9, 35, // Opcode: MUH /* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 /* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 /* 218 */ MCD_OPC_CheckPredicate, 36, 89, 6, // Skip to: 1847 /* 222 */ MCD_OPC_Decode, 212, 9, 35, // Opcode: MULU /* 226 */ MCD_OPC_FilterValue, 3, 81, 6, // Skip to: 1847 /* 230 */ MCD_OPC_CheckPredicate, 36, 77, 6, // Skip to: 1847 /* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU /* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 /* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 /* 249 */ MCD_OPC_CheckPredicate, 36, 58, 6, // Skip to: 1847 /* 253 */ MCD_OPC_Decode, 183, 4, 35, // Opcode: DIV /* 257 */ MCD_OPC_FilterValue, 3, 50, 6, // Skip to: 1847 /* 261 */ MCD_OPC_CheckPredicate, 36, 46, 6, // Skip to: 1847 /* 265 */ MCD_OPC_Decode, 222, 8, 35, // Opcode: MOD /* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 /* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 /* 280 */ MCD_OPC_CheckPredicate, 36, 27, 6, // Skip to: 1847 /* 284 */ MCD_OPC_Decode, 184, 4, 35, // Opcode: DIVU /* 288 */ MCD_OPC_FilterValue, 3, 19, 6, // Skip to: 1847 /* 292 */ MCD_OPC_CheckPredicate, 36, 15, 6, // Skip to: 1847 /* 296 */ MCD_OPC_Decode, 224, 8, 35, // Opcode: MODU /* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 /* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 /* 311 */ MCD_OPC_CheckPredicate, 37, 252, 5, // Skip to: 1847 /* 315 */ MCD_OPC_Decode, 210, 4, 224, 1, // Opcode: DMUL_R6 /* 320 */ MCD_OPC_FilterValue, 3, 243, 5, // Skip to: 1847 /* 324 */ MCD_OPC_CheckPredicate, 37, 239, 5, // Skip to: 1847 /* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH /* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 /* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 /* 344 */ MCD_OPC_CheckPredicate, 37, 219, 5, // Skip to: 1847 /* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU /* 353 */ MCD_OPC_FilterValue, 3, 210, 5, // Skip to: 1847 /* 357 */ MCD_OPC_CheckPredicate, 37, 206, 5, // Skip to: 1847 /* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU /* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 /* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 /* 377 */ MCD_OPC_CheckPredicate, 37, 186, 5, // Skip to: 1847 /* 381 */ MCD_OPC_Decode, 172, 4, 224, 1, // Opcode: DDIV /* 386 */ MCD_OPC_FilterValue, 3, 177, 5, // Skip to: 1847 /* 390 */ MCD_OPC_CheckPredicate, 37, 173, 5, // Skip to: 1847 /* 394 */ MCD_OPC_Decode, 199, 4, 224, 1, // Opcode: DMOD /* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 /* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 /* 410 */ MCD_OPC_CheckPredicate, 37, 153, 5, // Skip to: 1847 /* 414 */ MCD_OPC_Decode, 173, 4, 224, 1, // Opcode: DDIVU /* 419 */ MCD_OPC_FilterValue, 3, 144, 5, // Skip to: 1847 /* 423 */ MCD_OPC_CheckPredicate, 37, 140, 5, // Skip to: 1847 /* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU /* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 /* 436 */ MCD_OPC_CheckPredicate, 38, 127, 5, // Skip to: 1847 /* 440 */ MCD_OPC_CheckField, 6, 5, 0, 121, 5, // Skip to: 1847 /* 446 */ MCD_OPC_Decode, 174, 11, 35, // Opcode: SELEQZ /* 450 */ MCD_OPC_FilterValue, 55, 113, 5, // Skip to: 1847 /* 454 */ MCD_OPC_CheckPredicate, 38, 109, 5, // Skip to: 1847 /* 458 */ MCD_OPC_CheckField, 6, 5, 0, 103, 5, // Skip to: 1847 /* 464 */ MCD_OPC_Decode, 178, 11, 35, // Opcode: SELNEZ /* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 /* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 /* 479 */ MCD_OPC_CheckPredicate, 37, 84, 5, // Skip to: 1847 /* 483 */ MCD_OPC_Decode, 163, 4, 225, 1, // Opcode: DAHI /* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 /* 492 */ MCD_OPC_CheckPredicate, 36, 71, 5, // Skip to: 1847 /* 496 */ MCD_OPC_CheckField, 21, 5, 0, 65, 5, // Skip to: 1847 /* 502 */ MCD_OPC_Decode, 167, 1, 75, // Opcode: BAL /* 506 */ MCD_OPC_FilterValue, 30, 57, 5, // Skip to: 1847 /* 510 */ MCD_OPC_CheckPredicate, 37, 53, 5, // Skip to: 1847 /* 514 */ MCD_OPC_Decode, 165, 4, 225, 1, // Opcode: DATI /* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 /* 523 */ MCD_OPC_CheckPredicate, 36, 40, 5, // Skip to: 1847 /* 527 */ MCD_OPC_Decode, 220, 1, 226, 1, // Opcode: BGEZALC /* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 /* 536 */ MCD_OPC_CheckPredicate, 36, 27, 5, // Skip to: 1847 /* 540 */ MCD_OPC_Decode, 134, 2, 227, 1, // Opcode: BLTZALC /* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 /* 549 */ MCD_OPC_CheckPredicate, 36, 14, 5, // Skip to: 1847 /* 553 */ MCD_OPC_Decode, 208, 1, 228, 1, // Opcode: BEQC /* 558 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 570 /* 562 */ MCD_OPC_CheckPredicate, 36, 1, 5, // Skip to: 1847 /* 566 */ MCD_OPC_Decode, 137, 1, 47, // Opcode: AUI /* 570 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1347 /* 574 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 577 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 590 /* 581 */ MCD_OPC_CheckPredicate, 36, 238, 4, // Skip to: 1847 /* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ /* 590 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 603 /* 594 */ MCD_OPC_CheckPredicate, 36, 225, 4, // Skip to: 1847 /* 598 */ MCD_OPC_Decode, 184, 1, 229, 1, // Opcode: BC1NEZ /* 603 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 757 /* 607 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 610 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 623 /* 614 */ MCD_OPC_CheckPredicate, 36, 205, 4, // Skip to: 1847 /* 618 */ MCD_OPC_Decode, 183, 11, 230, 1, // Opcode: SEL_S /* 623 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 635 /* 627 */ MCD_OPC_CheckPredicate, 36, 192, 4, // Skip to: 1847 /* 631 */ MCD_OPC_Decode, 177, 11, 93, // Opcode: SELEQZ_S /* 635 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 647 /* 639 */ MCD_OPC_CheckPredicate, 36, 180, 4, // Skip to: 1847 /* 643 */ MCD_OPC_Decode, 181, 11, 93, // Opcode: SELNEZ_S /* 647 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 660 /* 651 */ MCD_OPC_CheckPredicate, 36, 168, 4, // Skip to: 1847 /* 655 */ MCD_OPC_Decode, 132, 8, 231, 1, // Opcode: MADDF_S /* 660 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 673 /* 664 */ MCD_OPC_CheckPredicate, 36, 155, 4, // Skip to: 1847 /* 668 */ MCD_OPC_Decode, 150, 9, 231, 1, // Opcode: MSUBF_S /* 673 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 691 /* 677 */ MCD_OPC_CheckPredicate, 36, 142, 4, // Skip to: 1847 /* 681 */ MCD_OPC_CheckField, 16, 5, 0, 136, 4, // Skip to: 1847 /* 687 */ MCD_OPC_Decode, 246, 10, 94, // Opcode: RINT_S /* 691 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 709 /* 695 */ MCD_OPC_CheckPredicate, 36, 124, 4, // Skip to: 1847 /* 699 */ MCD_OPC_CheckField, 16, 5, 0, 118, 4, // Skip to: 1847 /* 705 */ MCD_OPC_Decode, 244, 2, 94, // Opcode: CLASS_S /* 709 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 721 /* 713 */ MCD_OPC_CheckPredicate, 36, 106, 4, // Skip to: 1847 /* 717 */ MCD_OPC_Decode, 211, 8, 93, // Opcode: MIN_S /* 721 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 733 /* 725 */ MCD_OPC_CheckPredicate, 36, 94, 4, // Skip to: 1847 /* 729 */ MCD_OPC_Decode, 170, 8, 93, // Opcode: MAX_S /* 733 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 745 /* 737 */ MCD_OPC_CheckPredicate, 36, 82, 4, // Skip to: 1847 /* 741 */ MCD_OPC_Decode, 197, 8, 93, // Opcode: MINA_S /* 745 */ MCD_OPC_FilterValue, 31, 74, 4, // Skip to: 1847 /* 749 */ MCD_OPC_CheckPredicate, 36, 70, 4, // Skip to: 1847 /* 753 */ MCD_OPC_Decode, 156, 8, 93, // Opcode: MAXA_S /* 757 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 917 /* 761 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 764 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 777 /* 768 */ MCD_OPC_CheckPredicate, 36, 51, 4, // Skip to: 1847 /* 772 */ MCD_OPC_Decode, 182, 11, 232, 1, // Opcode: SEL_D /* 777 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 790 /* 781 */ MCD_OPC_CheckPredicate, 36, 38, 4, // Skip to: 1847 /* 785 */ MCD_OPC_Decode, 176, 11, 233, 1, // Opcode: SELEQZ_D /* 790 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 803 /* 794 */ MCD_OPC_CheckPredicate, 36, 25, 4, // Skip to: 1847 /* 798 */ MCD_OPC_Decode, 180, 11, 233, 1, // Opcode: SELNEZ_D /* 803 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 816 /* 807 */ MCD_OPC_CheckPredicate, 36, 12, 4, // Skip to: 1847 /* 811 */ MCD_OPC_Decode, 131, 8, 234, 1, // Opcode: MADDF_D /* 816 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 829 /* 820 */ MCD_OPC_CheckPredicate, 36, 255, 3, // Skip to: 1847 /* 824 */ MCD_OPC_Decode, 149, 9, 234, 1, // Opcode: MSUBF_D /* 829 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 847 /* 833 */ MCD_OPC_CheckPredicate, 36, 242, 3, // Skip to: 1847 /* 837 */ MCD_OPC_CheckField, 16, 5, 0, 236, 3, // Skip to: 1847 /* 843 */ MCD_OPC_Decode, 245, 10, 105, // Opcode: RINT_D /* 847 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 865 /* 851 */ MCD_OPC_CheckPredicate, 36, 224, 3, // Skip to: 1847 /* 855 */ MCD_OPC_CheckField, 16, 5, 0, 218, 3, // Skip to: 1847 /* 861 */ MCD_OPC_Decode, 243, 2, 105, // Opcode: CLASS_D /* 865 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 878 /* 869 */ MCD_OPC_CheckPredicate, 36, 206, 3, // Skip to: 1847 /* 873 */ MCD_OPC_Decode, 210, 8, 233, 1, // Opcode: MIN_D /* 878 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 891 /* 882 */ MCD_OPC_CheckPredicate, 36, 193, 3, // Skip to: 1847 /* 886 */ MCD_OPC_Decode, 169, 8, 233, 1, // Opcode: MAX_D /* 891 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 904 /* 895 */ MCD_OPC_CheckPredicate, 36, 180, 3, // Skip to: 1847 /* 899 */ MCD_OPC_Decode, 196, 8, 233, 1, // Opcode: MINA_D /* 904 */ MCD_OPC_FilterValue, 31, 171, 3, // Skip to: 1847 /* 908 */ MCD_OPC_CheckPredicate, 36, 167, 3, // Skip to: 1847 /* 912 */ MCD_OPC_Decode, 155, 8, 233, 1, // Opcode: MAXA_D /* 917 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1132 /* 921 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 924 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 937 /* 928 */ MCD_OPC_CheckPredicate, 36, 147, 3, // Skip to: 1847 /* 932 */ MCD_OPC_Decode, 168, 3, 235, 1, // Opcode: CMP_F_S /* 937 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 950 /* 941 */ MCD_OPC_CheckPredicate, 36, 134, 3, // Skip to: 1847 /* 945 */ MCD_OPC_Decode, 198, 3, 235, 1, // Opcode: CMP_UN_S /* 950 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 963 /* 954 */ MCD_OPC_CheckPredicate, 36, 121, 3, // Skip to: 1847 /* 958 */ MCD_OPC_Decode, 166, 3, 235, 1, // Opcode: CMP_EQ_S /* 963 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 976 /* 967 */ MCD_OPC_CheckPredicate, 36, 108, 3, // Skip to: 1847 /* 971 */ MCD_OPC_Decode, 192, 3, 235, 1, // Opcode: CMP_UEQ_S /* 976 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 989 /* 980 */ MCD_OPC_CheckPredicate, 36, 95, 3, // Skip to: 1847 /* 984 */ MCD_OPC_Decode, 174, 3, 235, 1, // Opcode: CMP_LT_S /* 989 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1002 /* 993 */ MCD_OPC_CheckPredicate, 36, 82, 3, // Skip to: 1847 /* 997 */ MCD_OPC_Decode, 196, 3, 235, 1, // Opcode: CMP_ULT_S /* 1002 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1015 /* 1006 */ MCD_OPC_CheckPredicate, 36, 69, 3, // Skip to: 1847 /* 1010 */ MCD_OPC_Decode, 171, 3, 235, 1, // Opcode: CMP_LE_S /* 1015 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1028 /* 1019 */ MCD_OPC_CheckPredicate, 36, 56, 3, // Skip to: 1847 /* 1023 */ MCD_OPC_Decode, 194, 3, 235, 1, // Opcode: CMP_ULE_S /* 1028 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1041 /* 1032 */ MCD_OPC_CheckPredicate, 36, 43, 3, // Skip to: 1847 /* 1036 */ MCD_OPC_Decode, 176, 3, 235, 1, // Opcode: CMP_SAF_S /* 1041 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1054 /* 1045 */ MCD_OPC_CheckPredicate, 36, 30, 3, // Skip to: 1847 /* 1049 */ MCD_OPC_Decode, 190, 3, 235, 1, // Opcode: CMP_SUN_S /* 1054 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1067 /* 1058 */ MCD_OPC_CheckPredicate, 36, 17, 3, // Skip to: 1847 /* 1062 */ MCD_OPC_Decode, 178, 3, 235, 1, // Opcode: CMP_SEQ_S /* 1067 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1080 /* 1071 */ MCD_OPC_CheckPredicate, 36, 4, 3, // Skip to: 1847 /* 1075 */ MCD_OPC_Decode, 184, 3, 235, 1, // Opcode: CMP_SUEQ_S /* 1080 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1093 /* 1084 */ MCD_OPC_CheckPredicate, 36, 247, 2, // Skip to: 1847 /* 1088 */ MCD_OPC_Decode, 182, 3, 235, 1, // Opcode: CMP_SLT_S /* 1093 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1106 /* 1097 */ MCD_OPC_CheckPredicate, 36, 234, 2, // Skip to: 1847 /* 1101 */ MCD_OPC_Decode, 188, 3, 235, 1, // Opcode: CMP_SULT_S /* 1106 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1119 /* 1110 */ MCD_OPC_CheckPredicate, 36, 221, 2, // Skip to: 1847 /* 1114 */ MCD_OPC_Decode, 180, 3, 235, 1, // Opcode: CMP_SLE_S /* 1119 */ MCD_OPC_FilterValue, 15, 212, 2, // Skip to: 1847 /* 1123 */ MCD_OPC_CheckPredicate, 36, 208, 2, // Skip to: 1847 /* 1127 */ MCD_OPC_Decode, 186, 3, 235, 1, // Opcode: CMP_SULE_S /* 1132 */ MCD_OPC_FilterValue, 21, 199, 2, // Skip to: 1847 /* 1136 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 1139 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1152 /* 1143 */ MCD_OPC_CheckPredicate, 36, 188, 2, // Skip to: 1847 /* 1147 */ MCD_OPC_Decode, 167, 3, 236, 1, // Opcode: CMP_F_D /* 1152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1165 /* 1156 */ MCD_OPC_CheckPredicate, 36, 175, 2, // Skip to: 1847 /* 1160 */ MCD_OPC_Decode, 197, 3, 236, 1, // Opcode: CMP_UN_D /* 1165 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1178 /* 1169 */ MCD_OPC_CheckPredicate, 36, 162, 2, // Skip to: 1847 /* 1173 */ MCD_OPC_Decode, 164, 3, 236, 1, // Opcode: CMP_EQ_D /* 1178 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1191 /* 1182 */ MCD_OPC_CheckPredicate, 36, 149, 2, // Skip to: 1847 /* 1186 */ MCD_OPC_Decode, 191, 3, 236, 1, // Opcode: CMP_UEQ_D /* 1191 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1204 /* 1195 */ MCD_OPC_CheckPredicate, 36, 136, 2, // Skip to: 1847 /* 1199 */ MCD_OPC_Decode, 172, 3, 236, 1, // Opcode: CMP_LT_D /* 1204 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1217 /* 1208 */ MCD_OPC_CheckPredicate, 36, 123, 2, // Skip to: 1847 /* 1212 */ MCD_OPC_Decode, 195, 3, 236, 1, // Opcode: CMP_ULT_D /* 1217 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1230 /* 1221 */ MCD_OPC_CheckPredicate, 36, 110, 2, // Skip to: 1847 /* 1225 */ MCD_OPC_Decode, 169, 3, 236, 1, // Opcode: CMP_LE_D /* 1230 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1243 /* 1234 */ MCD_OPC_CheckPredicate, 36, 97, 2, // Skip to: 1847 /* 1238 */ MCD_OPC_Decode, 193, 3, 236, 1, // Opcode: CMP_ULE_D /* 1243 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1256 /* 1247 */ MCD_OPC_CheckPredicate, 36, 84, 2, // Skip to: 1847 /* 1251 */ MCD_OPC_Decode, 175, 3, 236, 1, // Opcode: CMP_SAF_D /* 1256 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1269 /* 1260 */ MCD_OPC_CheckPredicate, 36, 71, 2, // Skip to: 1847 /* 1264 */ MCD_OPC_Decode, 189, 3, 236, 1, // Opcode: CMP_SUN_D /* 1269 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1282 /* 1273 */ MCD_OPC_CheckPredicate, 36, 58, 2, // Skip to: 1847 /* 1277 */ MCD_OPC_Decode, 177, 3, 236, 1, // Opcode: CMP_SEQ_D /* 1282 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1295 /* 1286 */ MCD_OPC_CheckPredicate, 36, 45, 2, // Skip to: 1847 /* 1290 */ MCD_OPC_Decode, 183, 3, 236, 1, // Opcode: CMP_SUEQ_D /* 1295 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1308 /* 1299 */ MCD_OPC_CheckPredicate, 36, 32, 2, // Skip to: 1847 /* 1303 */ MCD_OPC_Decode, 181, 3, 236, 1, // Opcode: CMP_SLT_D /* 1308 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1321 /* 1312 */ MCD_OPC_CheckPredicate, 36, 19, 2, // Skip to: 1847 /* 1316 */ MCD_OPC_Decode, 187, 3, 236, 1, // Opcode: CMP_SULT_D /* 1321 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1334 /* 1325 */ MCD_OPC_CheckPredicate, 36, 6, 2, // Skip to: 1847 /* 1329 */ MCD_OPC_Decode, 179, 3, 236, 1, // Opcode: CMP_SLE_D /* 1334 */ MCD_OPC_FilterValue, 15, 253, 1, // Skip to: 1847 /* 1338 */ MCD_OPC_CheckPredicate, 36, 249, 1, // Skip to: 1847 /* 1342 */ MCD_OPC_Decode, 185, 3, 236, 1, // Opcode: CMP_SULE_D /* 1347 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1432 /* 1351 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 1354 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1367 /* 1358 */ MCD_OPC_CheckPredicate, 36, 229, 1, // Skip to: 1847 /* 1362 */ MCD_OPC_Decode, 188, 1, 237, 1, // Opcode: BC2EQZ /* 1367 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1380 /* 1371 */ MCD_OPC_CheckPredicate, 36, 216, 1, // Skip to: 1847 /* 1375 */ MCD_OPC_Decode, 219, 7, 238, 1, // Opcode: LWC2_R6 /* 1380 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1393 /* 1384 */ MCD_OPC_CheckPredicate, 36, 203, 1, // Skip to: 1847 /* 1388 */ MCD_OPC_Decode, 241, 12, 238, 1, // Opcode: SWC2_R6 /* 1393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1406 /* 1397 */ MCD_OPC_CheckPredicate, 36, 190, 1, // Skip to: 1847 /* 1401 */ MCD_OPC_Decode, 191, 1, 237, 1, // Opcode: BC2NEZ /* 1406 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1419 /* 1410 */ MCD_OPC_CheckPredicate, 36, 177, 1, // Skip to: 1847 /* 1414 */ MCD_OPC_Decode, 166, 7, 238, 1, // Opcode: LDC2_R6 /* 1419 */ MCD_OPC_FilterValue, 15, 168, 1, // Skip to: 1847 /* 1423 */ MCD_OPC_CheckPredicate, 36, 164, 1, // Skip to: 1847 /* 1427 */ MCD_OPC_Decode, 160, 11, 238, 1, // Opcode: SDC2_R6 /* 1432 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1445 /* 1436 */ MCD_OPC_CheckPredicate, 36, 151, 1, // Skip to: 1847 /* 1440 */ MCD_OPC_Decode, 224, 1, 239, 1, // Opcode: BGEZC /* 1445 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1458 /* 1449 */ MCD_OPC_CheckPredicate, 36, 138, 1, // Skip to: 1847 /* 1453 */ MCD_OPC_Decode, 138, 2, 240, 1, // Opcode: BLTZC /* 1458 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1471 /* 1462 */ MCD_OPC_CheckPredicate, 36, 125, 1, // Skip to: 1847 /* 1466 */ MCD_OPC_Decode, 147, 2, 241, 1, // Opcode: BNEC /* 1471 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1484 /* 1475 */ MCD_OPC_CheckPredicate, 37, 112, 1, // Skip to: 1847 /* 1479 */ MCD_OPC_Decode, 166, 4, 242, 1, // Opcode: DAUI /* 1484 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1670 /* 1488 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 1491 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1535 /* 1495 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 1498 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1523 /* 1502 */ MCD_OPC_CheckPredicate, 36, 85, 1, // Skip to: 1847 /* 1506 */ MCD_OPC_CheckField, 21, 5, 0, 79, 1, // Skip to: 1847 /* 1512 */ MCD_OPC_CheckField, 6, 2, 0, 73, 1, // Skip to: 1847 /* 1518 */ MCD_OPC_Decode, 250, 1, 205, 1, // Opcode: BITSWAP /* 1523 */ MCD_OPC_FilterValue, 2, 64, 1, // Skip to: 1847 /* 1527 */ MCD_OPC_CheckPredicate, 36, 60, 1, // Skip to: 1847 /* 1531 */ MCD_OPC_Decode, 81, 221, 1, // Opcode: ALIGN /* 1535 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1580 /* 1539 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 1542 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1567 /* 1546 */ MCD_OPC_CheckPredicate, 37, 41, 1, // Skip to: 1847 /* 1550 */ MCD_OPC_CheckField, 21, 5, 0, 35, 1, // Skip to: 1847 /* 1556 */ MCD_OPC_CheckField, 6, 3, 0, 29, 1, // Skip to: 1847 /* 1562 */ MCD_OPC_Decode, 167, 4, 243, 1, // Opcode: DBITSWAP /* 1567 */ MCD_OPC_FilterValue, 1, 20, 1, // Skip to: 1847 /* 1571 */ MCD_OPC_CheckPredicate, 37, 16, 1, // Skip to: 1847 /* 1575 */ MCD_OPC_Decode, 164, 4, 244, 1, // Opcode: DALIGN /* 1580 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1599 /* 1584 */ MCD_OPC_CheckPredicate, 36, 3, 1, // Skip to: 1847 /* 1588 */ MCD_OPC_CheckField, 6, 1, 0, 253, 0, // Skip to: 1847 /* 1594 */ MCD_OPC_Decode, 222, 2, 245, 1, // Opcode: CACHE_R6 /* 1599 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1612 /* 1603 */ MCD_OPC_CheckPredicate, 36, 240, 0, // Skip to: 1847 /* 1607 */ MCD_OPC_Decode, 150, 11, 246, 1, // Opcode: SC_R6 /* 1612 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1625 /* 1616 */ MCD_OPC_CheckPredicate, 36, 227, 0, // Skip to: 1847 /* 1620 */ MCD_OPC_Decode, 148, 11, 246, 1, // Opcode: SCD_R6 /* 1625 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1644 /* 1629 */ MCD_OPC_CheckPredicate, 36, 214, 0, // Skip to: 1847 /* 1633 */ MCD_OPC_CheckField, 6, 1, 0, 208, 0, // Skip to: 1847 /* 1639 */ MCD_OPC_Decode, 183, 10, 245, 1, // Opcode: PREF_R6 /* 1644 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1657 /* 1648 */ MCD_OPC_CheckPredicate, 36, 195, 0, // Skip to: 1847 /* 1652 */ MCD_OPC_Decode, 197, 7, 246, 1, // Opcode: LL_R6 /* 1657 */ MCD_OPC_FilterValue, 55, 186, 0, // Skip to: 1847 /* 1661 */ MCD_OPC_CheckPredicate, 36, 182, 0, // Skip to: 1847 /* 1665 */ MCD_OPC_Decode, 195, 7, 246, 1, // Opcode: LLD_R6 /* 1670 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1683 /* 1674 */ MCD_OPC_CheckPredicate, 36, 169, 0, // Skip to: 1847 /* 1678 */ MCD_OPC_Decode, 175, 1, 247, 1, // Opcode: BC /* 1683 */ MCD_OPC_FilterValue, 54, 23, 0, // Skip to: 1710 /* 1687 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1701 /* 1691 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1701 /* 1697 */ MCD_OPC_Decode, 135, 7, 52, // Opcode: JIC /* 1701 */ MCD_OPC_CheckPredicate, 36, 142, 0, // Skip to: 1847 /* 1705 */ MCD_OPC_Decode, 212, 1, 248, 1, // Opcode: BEQZC /* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 /* 1714 */ MCD_OPC_CheckPredicate, 36, 129, 0, // Skip to: 1847 /* 1718 */ MCD_OPC_Decode, 168, 1, 247, 1, // Opcode: BALC /* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 /* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... /* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 /* 1734 */ MCD_OPC_CheckPredicate, 36, 109, 0, // Skip to: 1847 /* 1738 */ MCD_OPC_Decode, 26, 249, 1, // Opcode: ADDIUPC /* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 /* 1746 */ MCD_OPC_CheckPredicate, 36, 97, 0, // Skip to: 1847 /* 1750 */ MCD_OPC_Decode, 228, 7, 249, 1, // Opcode: LWPC /* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 /* 1759 */ MCD_OPC_CheckPredicate, 36, 84, 0, // Skip to: 1847 /* 1763 */ MCD_OPC_Decode, 234, 7, 249, 1, // Opcode: LWUPC /* 1768 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 1847 /* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 /* 1779 */ MCD_OPC_CheckPredicate, 37, 64, 0, // Skip to: 1847 /* 1783 */ MCD_OPC_Decode, 173, 7, 250, 1, // Opcode: LDPC /* 1788 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 1847 /* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 /* 1799 */ MCD_OPC_CheckPredicate, 36, 44, 0, // Skip to: 1847 /* 1803 */ MCD_OPC_Decode, 138, 1, 251, 1, // Opcode: AUIPC /* 1808 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 1847 /* 1812 */ MCD_OPC_CheckPredicate, 36, 31, 0, // Skip to: 1847 /* 1816 */ MCD_OPC_Decode, 82, 251, 1, // Opcode: ALUIPC /* 1820 */ MCD_OPC_FilterValue, 62, 23, 0, // Skip to: 1847 /* 1824 */ MCD_OPC_CheckPredicate, 36, 10, 0, // Skip to: 1838 /* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 1838 /* 1834 */ MCD_OPC_Decode, 134, 7, 52, // Opcode: JIALC /* 1838 */ MCD_OPC_CheckPredicate, 36, 5, 0, // Skip to: 1847 /* 1842 */ MCD_OPC_Decode, 159, 2, 248, 1, // Opcode: BNEZC /* 1847 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { /* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... /* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 /* 7 */ MCD_OPC_CheckPredicate, 39, 30, 0, // Skip to: 41 /* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 /* 17 */ MCD_OPC_Decode, 175, 11, 224, 1, // Opcode: SELEQZ64 /* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 /* 26 */ MCD_OPC_CheckPredicate, 39, 11, 0, // Skip to: 41 /* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 /* 36 */ MCD_OPC_Decode, 179, 11, 224, 1, // Opcode: SELNEZ64 /* 41 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableMips6432[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 /* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 /* 14 */ MCD_OPC_CheckPredicate, 19, 42, 9, // Skip to: 2364 /* 18 */ MCD_OPC_CheckField, 6, 5, 0, 36, 9, // Skip to: 2364 /* 24 */ MCD_OPC_Decode, 255, 4, 252, 1, // Opcode: DSLLV /* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 /* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 /* 40 */ MCD_OPC_CheckPredicate, 19, 16, 9, // Skip to: 2364 /* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV /* 49 */ MCD_OPC_FilterValue, 1, 7, 9, // Skip to: 2364 /* 53 */ MCD_OPC_CheckPredicate, 40, 3, 9, // Skip to: 2364 /* 57 */ MCD_OPC_Decode, 248, 4, 252, 1, // Opcode: DROTRV /* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 /* 66 */ MCD_OPC_CheckPredicate, 19, 246, 8, // Skip to: 2364 /* 70 */ MCD_OPC_CheckField, 6, 5, 0, 240, 8, // Skip to: 2364 /* 76 */ MCD_OPC_Decode, 130, 5, 252, 1, // Opcode: DSRAV /* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 /* 85 */ MCD_OPC_CheckPredicate, 41, 227, 8, // Skip to: 2364 /* 89 */ MCD_OPC_CheckField, 6, 10, 0, 221, 8, // Skip to: 2364 /* 95 */ MCD_OPC_Decode, 207, 4, 253, 1, // Opcode: DMULT /* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 /* 104 */ MCD_OPC_CheckPredicate, 41, 208, 8, // Skip to: 2364 /* 108 */ MCD_OPC_CheckField, 6, 10, 0, 202, 8, // Skip to: 2364 /* 114 */ MCD_OPC_Decode, 208, 4, 253, 1, // Opcode: DMULTu /* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 /* 123 */ MCD_OPC_CheckPredicate, 41, 189, 8, // Skip to: 2364 /* 127 */ MCD_OPC_CheckField, 6, 10, 0, 183, 8, // Skip to: 2364 /* 133 */ MCD_OPC_Decode, 250, 4, 253, 1, // Opcode: DSDIV /* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 /* 142 */ MCD_OPC_CheckPredicate, 41, 170, 8, // Skip to: 2364 /* 146 */ MCD_OPC_CheckField, 6, 10, 0, 164, 8, // Skip to: 2364 /* 152 */ MCD_OPC_Decode, 136, 5, 253, 1, // Opcode: DUDIV /* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 /* 161 */ MCD_OPC_CheckPredicate, 19, 151, 8, // Skip to: 2364 /* 165 */ MCD_OPC_CheckField, 6, 5, 0, 145, 8, // Skip to: 2364 /* 171 */ MCD_OPC_Decode, 159, 4, 224, 1, // Opcode: DADD /* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 /* 180 */ MCD_OPC_CheckPredicate, 19, 132, 8, // Skip to: 2364 /* 184 */ MCD_OPC_CheckField, 6, 5, 0, 126, 8, // Skip to: 2364 /* 190 */ MCD_OPC_Decode, 162, 4, 224, 1, // Opcode: DADDu /* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 /* 199 */ MCD_OPC_CheckPredicate, 19, 113, 8, // Skip to: 2364 /* 203 */ MCD_OPC_CheckField, 6, 5, 0, 107, 8, // Skip to: 2364 /* 209 */ MCD_OPC_Decode, 134, 5, 224, 1, // Opcode: DSUB /* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 /* 218 */ MCD_OPC_CheckPredicate, 19, 94, 8, // Skip to: 2364 /* 222 */ MCD_OPC_CheckField, 6, 5, 0, 88, 8, // Skip to: 2364 /* 228 */ MCD_OPC_Decode, 135, 5, 224, 1, // Opcode: DSUBu /* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 /* 237 */ MCD_OPC_CheckPredicate, 19, 75, 8, // Skip to: 2364 /* 241 */ MCD_OPC_CheckField, 21, 5, 0, 69, 8, // Skip to: 2364 /* 247 */ MCD_OPC_Decode, 252, 4, 254, 1, // Opcode: DSLL /* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 /* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 /* 263 */ MCD_OPC_CheckPredicate, 19, 49, 8, // Skip to: 2364 /* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL /* 272 */ MCD_OPC_FilterValue, 1, 40, 8, // Skip to: 2364 /* 276 */ MCD_OPC_CheckPredicate, 40, 36, 8, // Skip to: 2364 /* 280 */ MCD_OPC_Decode, 246, 4, 254, 1, // Opcode: DROTR /* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 /* 289 */ MCD_OPC_CheckPredicate, 19, 23, 8, // Skip to: 2364 /* 293 */ MCD_OPC_CheckField, 21, 5, 0, 17, 8, // Skip to: 2364 /* 299 */ MCD_OPC_Decode, 128, 5, 254, 1, // Opcode: DSRA /* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 /* 308 */ MCD_OPC_CheckPredicate, 19, 4, 8, // Skip to: 2364 /* 312 */ MCD_OPC_CheckField, 21, 5, 0, 254, 7, // Skip to: 2364 /* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32 /* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 /* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 /* 334 */ MCD_OPC_CheckPredicate, 19, 234, 7, // Skip to: 2364 /* 338 */ MCD_OPC_Decode, 132, 5, 254, 1, // Opcode: DSRL32 /* 343 */ MCD_OPC_FilterValue, 1, 225, 7, // Skip to: 2364 /* 347 */ MCD_OPC_CheckPredicate, 40, 221, 7, // Skip to: 2364 /* 351 */ MCD_OPC_Decode, 247, 4, 254, 1, // Opcode: DROTR32 /* 356 */ MCD_OPC_FilterValue, 63, 212, 7, // Skip to: 2364 /* 360 */ MCD_OPC_CheckPredicate, 19, 208, 7, // Skip to: 2364 /* 364 */ MCD_OPC_CheckField, 21, 5, 0, 202, 7, // Skip to: 2364 /* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32 /* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 /* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 /* 386 */ MCD_OPC_CheckPredicate, 42, 182, 7, // Skip to: 2364 /* 390 */ MCD_OPC_CheckField, 3, 8, 0, 176, 7, // Skip to: 2364 /* 396 */ MCD_OPC_Decode, 196, 4, 255, 1, // Opcode: DMFC0 /* 401 */ MCD_OPC_FilterValue, 5, 167, 7, // Skip to: 2364 /* 405 */ MCD_OPC_CheckPredicate, 42, 163, 7, // Skip to: 2364 /* 409 */ MCD_OPC_CheckField, 3, 8, 0, 157, 7, // Skip to: 2364 /* 415 */ MCD_OPC_Decode, 201, 4, 255, 1, // Opcode: DMTC0 /* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 /* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 /* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 /* 438 */ MCD_OPC_CheckPredicate, 43, 130, 7, // Skip to: 2364 /* 442 */ MCD_OPC_CheckField, 6, 5, 0, 124, 7, // Skip to: 2364 /* 448 */ MCD_OPC_Decode, 184, 8, 128, 2, // Opcode: MFHC1_D64 /* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 /* 457 */ MCD_OPC_CheckPredicate, 43, 111, 7, // Skip to: 2364 /* 461 */ MCD_OPC_CheckField, 6, 5, 0, 105, 7, // Skip to: 2364 /* 467 */ MCD_OPC_Decode, 174, 9, 129, 2, // Opcode: MTHC1_D64 /* 472 */ MCD_OPC_FilterValue, 17, 96, 7, // Skip to: 2364 /* 476 */ MCD_OPC_CheckPredicate, 44, 92, 7, // Skip to: 2364 /* 480 */ MCD_OPC_Decode, 172, 5, 233, 1, // Opcode: FADD_D64 /* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 /* 489 */ MCD_OPC_CheckPredicate, 44, 79, 7, // Skip to: 2364 /* 493 */ MCD_OPC_CheckField, 21, 5, 17, 73, 7, // Skip to: 2364 /* 499 */ MCD_OPC_Decode, 174, 6, 233, 1, // Opcode: FSUB_D64 /* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 /* 508 */ MCD_OPC_CheckPredicate, 44, 60, 7, // Skip to: 2364 /* 512 */ MCD_OPC_CheckField, 21, 5, 17, 54, 7, // Skip to: 2364 /* 518 */ MCD_OPC_Decode, 137, 6, 233, 1, // Opcode: FMUL_D64 /* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 /* 527 */ MCD_OPC_CheckPredicate, 44, 41, 7, // Skip to: 2364 /* 531 */ MCD_OPC_CheckField, 21, 5, 17, 35, 7, // Skip to: 2364 /* 537 */ MCD_OPC_Decode, 208, 5, 233, 1, // Opcode: FDIV_D64 /* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 /* 546 */ MCD_OPC_CheckPredicate, 45, 22, 7, // Skip to: 2364 /* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 15, 7, // Skip to: 2364 /* 557 */ MCD_OPC_Decode, 167, 6, 105, // Opcode: FSQRT_D64 /* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 /* 565 */ MCD_OPC_CheckPredicate, 44, 3, 7, // Skip to: 2364 /* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 252, 6, // Skip to: 2364 /* 576 */ MCD_OPC_Decode, 165, 5, 105, // Opcode: FABS_D64 /* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 /* 584 */ MCD_OPC_CheckPredicate, 44, 240, 6, // Skip to: 2364 /* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 233, 6, // Skip to: 2364 /* 595 */ MCD_OPC_Decode, 130, 6, 105, // Opcode: FMOV_D64 /* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 /* 603 */ MCD_OPC_CheckPredicate, 44, 221, 6, // Skip to: 2364 /* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 214, 6, // Skip to: 2364 /* 614 */ MCD_OPC_Decode, 143, 6, 105, // Opcode: FNEG_D64 /* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 /* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 /* 630 */ MCD_OPC_CheckPredicate, 44, 194, 6, // Skip to: 2364 /* 634 */ MCD_OPC_Decode, 252, 10, 98, // Opcode: ROUND_L_S /* 638 */ MCD_OPC_FilterValue, 160, 4, 185, 6, // Skip to: 2364 /* 643 */ MCD_OPC_CheckPredicate, 44, 181, 6, // Skip to: 2364 /* 647 */ MCD_OPC_Decode, 251, 10, 105, // Opcode: ROUND_L_D64 /* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 /* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 /* 663 */ MCD_OPC_CheckPredicate, 44, 161, 6, // Skip to: 2364 /* 667 */ MCD_OPC_Decode, 215, 13, 98, // Opcode: TRUNC_L_S /* 671 */ MCD_OPC_FilterValue, 160, 4, 152, 6, // Skip to: 2364 /* 676 */ MCD_OPC_CheckPredicate, 44, 148, 6, // Skip to: 2364 /* 680 */ MCD_OPC_Decode, 214, 13, 105, // Opcode: TRUNC_L_D64 /* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 /* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 /* 696 */ MCD_OPC_CheckPredicate, 44, 128, 6, // Skip to: 2364 /* 700 */ MCD_OPC_Decode, 224, 2, 98, // Opcode: CEIL_L_S /* 704 */ MCD_OPC_FilterValue, 160, 4, 119, 6, // Skip to: 2364 /* 709 */ MCD_OPC_CheckPredicate, 44, 115, 6, // Skip to: 2364 /* 713 */ MCD_OPC_Decode, 223, 2, 105, // Opcode: CEIL_L_D64 /* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 /* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 /* 729 */ MCD_OPC_CheckPredicate, 44, 95, 6, // Skip to: 2364 /* 733 */ MCD_OPC_Decode, 240, 5, 98, // Opcode: FLOOR_L_S /* 737 */ MCD_OPC_FilterValue, 160, 4, 86, 6, // Skip to: 2364 /* 742 */ MCD_OPC_CheckPredicate, 44, 82, 6, // Skip to: 2364 /* 746 */ MCD_OPC_Decode, 239, 5, 105, // Opcode: FLOOR_L_D64 /* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 /* 754 */ MCD_OPC_CheckPredicate, 45, 70, 6, // Skip to: 2364 /* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 63, 6, // Skip to: 2364 /* 765 */ MCD_OPC_Decode, 254, 10, 130, 2, // Opcode: ROUND_W_D64 /* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 /* 774 */ MCD_OPC_CheckPredicate, 45, 50, 6, // Skip to: 2364 /* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 43, 6, // Skip to: 2364 /* 785 */ MCD_OPC_Decode, 217, 13, 130, 2, // Opcode: TRUNC_W_D64 /* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 /* 794 */ MCD_OPC_CheckPredicate, 45, 30, 6, // Skip to: 2364 /* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 23, 6, // Skip to: 2364 /* 805 */ MCD_OPC_Decode, 226, 2, 130, 2, // Opcode: CEIL_W_D64 /* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 /* 814 */ MCD_OPC_CheckPredicate, 45, 10, 6, // Skip to: 2364 /* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 3, 6, // Skip to: 2364 /* 825 */ MCD_OPC_Decode, 242, 5, 130, 2, // Opcode: FLOOR_W_D64 /* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 /* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... /* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 /* 841 */ MCD_OPC_CheckPredicate, 46, 239, 5, // Skip to: 2364 /* 845 */ MCD_OPC_CheckField, 21, 5, 17, 233, 5, // Skip to: 2364 /* 851 */ MCD_OPC_Decode, 238, 8, 131, 2, // Opcode: MOVF_D64 /* 856 */ MCD_OPC_FilterValue, 1, 224, 5, // Skip to: 2364 /* 860 */ MCD_OPC_CheckPredicate, 46, 220, 5, // Skip to: 2364 /* 864 */ MCD_OPC_CheckField, 21, 5, 17, 214, 5, // Skip to: 2364 /* 870 */ MCD_OPC_Decode, 130, 9, 131, 2, // Opcode: MOVT_D64 /* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 /* 879 */ MCD_OPC_CheckPredicate, 46, 201, 5, // Skip to: 2364 /* 883 */ MCD_OPC_CheckField, 21, 5, 17, 195, 5, // Skip to: 2364 /* 889 */ MCD_OPC_Decode, 142, 9, 132, 2, // Opcode: MOVZ_I_D64 /* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 /* 898 */ MCD_OPC_CheckPredicate, 46, 182, 5, // Skip to: 2364 /* 902 */ MCD_OPC_CheckField, 21, 5, 17, 176, 5, // Skip to: 2364 /* 908 */ MCD_OPC_Decode, 250, 8, 132, 2, // Opcode: MOVN_I_D64 /* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 /* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 /* 925 */ MCD_OPC_CheckPredicate, 44, 155, 5, // Skip to: 2364 /* 929 */ MCD_OPC_Decode, 226, 3, 130, 2, // Opcode: CVT_S_D64 /* 934 */ MCD_OPC_FilterValue, 160, 5, 145, 5, // Skip to: 2364 /* 939 */ MCD_OPC_CheckPredicate, 44, 141, 5, // Skip to: 2364 /* 943 */ MCD_OPC_Decode, 227, 3, 130, 2, // Opcode: CVT_S_L /* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 /* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 /* 960 */ MCD_OPC_CheckPredicate, 44, 120, 5, // Skip to: 2364 /* 964 */ MCD_OPC_Decode, 217, 3, 98, // Opcode: CVT_D64_S /* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 /* 973 */ MCD_OPC_CheckPredicate, 44, 107, 5, // Skip to: 2364 /* 977 */ MCD_OPC_Decode, 218, 3, 98, // Opcode: CVT_D64_W /* 981 */ MCD_OPC_FilterValue, 160, 5, 98, 5, // Skip to: 2364 /* 986 */ MCD_OPC_CheckPredicate, 44, 94, 5, // Skip to: 2364 /* 990 */ MCD_OPC_Decode, 216, 3, 105, // Opcode: CVT_D64_L /* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 /* 998 */ MCD_OPC_CheckPredicate, 44, 82, 5, // Skip to: 2364 /* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 75, 5, // Skip to: 2364 /* 1009 */ MCD_OPC_Decode, 231, 3, 130, 2, // Opcode: CVT_W_D64 /* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 /* 1018 */ MCD_OPC_CheckPredicate, 47, 62, 5, // Skip to: 2364 /* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 56, 5, // Skip to: 2364 /* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 50, 5, // Skip to: 2364 /* 1034 */ MCD_OPC_Decode, 239, 3, 133, 2, // Opcode: C_F_D64 /* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 /* 1043 */ MCD_OPC_CheckPredicate, 47, 37, 5, // Skip to: 2364 /* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 31, 5, // Skip to: 2364 /* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 25, 5, // Skip to: 2364 /* 1059 */ MCD_OPC_Decode, 153, 4, 133, 2, // Opcode: C_UN_D64 /* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 /* 1068 */ MCD_OPC_CheckPredicate, 47, 12, 5, // Skip to: 2364 /* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 6, 5, // Skip to: 2364 /* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 0, 5, // Skip to: 2364 /* 1084 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: C_EQ_D64 /* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 /* 1093 */ MCD_OPC_CheckPredicate, 47, 243, 4, // Skip to: 2364 /* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 237, 4, // Skip to: 2364 /* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 231, 4, // Skip to: 2364 /* 1109 */ MCD_OPC_Decode, 144, 4, 133, 2, // Opcode: C_UEQ_D64 /* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 /* 1118 */ MCD_OPC_CheckPredicate, 47, 218, 4, // Skip to: 2364 /* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 212, 4, // Skip to: 2364 /* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 206, 4, // Skip to: 2364 /* 1134 */ MCD_OPC_Decode, 135, 4, 133, 2, // Opcode: C_OLT_D64 /* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 /* 1143 */ MCD_OPC_CheckPredicate, 47, 193, 4, // Skip to: 2364 /* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 187, 4, // Skip to: 2364 /* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 181, 4, // Skip to: 2364 /* 1159 */ MCD_OPC_Decode, 150, 4, 133, 2, // Opcode: C_ULT_D64 /* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 /* 1168 */ MCD_OPC_CheckPredicate, 47, 168, 4, // Skip to: 2364 /* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 162, 4, // Skip to: 2364 /* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 156, 4, // Skip to: 2364 /* 1184 */ MCD_OPC_Decode, 132, 4, 133, 2, // Opcode: C_OLE_D64 /* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 /* 1193 */ MCD_OPC_CheckPredicate, 47, 143, 4, // Skip to: 2364 /* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 137, 4, // Skip to: 2364 /* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 131, 4, // Skip to: 2364 /* 1209 */ MCD_OPC_Decode, 147, 4, 133, 2, // Opcode: C_ULE_D64 /* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 /* 1218 */ MCD_OPC_CheckPredicate, 47, 118, 4, // Skip to: 2364 /* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 112, 4, // Skip to: 2364 /* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 106, 4, // Skip to: 2364 /* 1234 */ MCD_OPC_Decode, 141, 4, 133, 2, // Opcode: C_SF_D64 /* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 /* 1243 */ MCD_OPC_CheckPredicate, 47, 93, 4, // Skip to: 2364 /* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 87, 4, // Skip to: 2364 /* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 81, 4, // Skip to: 2364 /* 1259 */ MCD_OPC_Decode, 251, 3, 133, 2, // Opcode: C_NGLE_D64 /* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 /* 1268 */ MCD_OPC_CheckPredicate, 47, 68, 4, // Skip to: 2364 /* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 62, 4, // Skip to: 2364 /* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 56, 4, // Skip to: 2364 /* 1284 */ MCD_OPC_Decode, 138, 4, 133, 2, // Opcode: C_SEQ_D64 /* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 /* 1293 */ MCD_OPC_CheckPredicate, 47, 43, 4, // Skip to: 2364 /* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 37, 4, // Skip to: 2364 /* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 31, 4, // Skip to: 2364 /* 1309 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: C_NGL_D64 /* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 /* 1318 */ MCD_OPC_CheckPredicate, 47, 18, 4, // Skip to: 2364 /* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 12, 4, // Skip to: 2364 /* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 6, 4, // Skip to: 2364 /* 1334 */ MCD_OPC_Decode, 245, 3, 133, 2, // Opcode: C_LT_D64 /* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 /* 1343 */ MCD_OPC_CheckPredicate, 47, 249, 3, // Skip to: 2364 /* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 243, 3, // Skip to: 2364 /* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 237, 3, // Skip to: 2364 /* 1359 */ MCD_OPC_Decode, 248, 3, 133, 2, // Opcode: C_NGE_D64 /* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 /* 1368 */ MCD_OPC_CheckPredicate, 47, 224, 3, // Skip to: 2364 /* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 218, 3, // Skip to: 2364 /* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 212, 3, // Skip to: 2364 /* 1384 */ MCD_OPC_Decode, 242, 3, 133, 2, // Opcode: C_LE_D64 /* 1389 */ MCD_OPC_FilterValue, 63, 203, 3, // Skip to: 2364 /* 1393 */ MCD_OPC_CheckPredicate, 47, 199, 3, // Skip to: 2364 /* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 193, 3, // Skip to: 2364 /* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 187, 3, // Skip to: 2364 /* 1409 */ MCD_OPC_Decode, 129, 4, 133, 2, // Opcode: C_NGT_D64 /* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 /* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 /* 1425 */ MCD_OPC_CheckPredicate, 42, 167, 3, // Skip to: 2364 /* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 161, 3, // Skip to: 2364 /* 1435 */ MCD_OPC_Decode, 198, 4, 255, 1, // Opcode: DMFC2 /* 1440 */ MCD_OPC_FilterValue, 5, 152, 3, // Skip to: 2364 /* 1444 */ MCD_OPC_CheckPredicate, 42, 148, 3, // Skip to: 2364 /* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 142, 3, // Skip to: 2364 /* 1454 */ MCD_OPC_Decode, 203, 4, 255, 1, // Opcode: DMTC2 /* 1459 */ MCD_OPC_FilterValue, 19, 131, 0, // Skip to: 1594 /* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 /* 1470 */ MCD_OPC_CheckPredicate, 48, 122, 3, // Skip to: 2364 /* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 116, 3, // Skip to: 2364 /* 1480 */ MCD_OPC_Decode, 176, 7, 134, 2, // Opcode: LDXC164 /* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 /* 1489 */ MCD_OPC_CheckPredicate, 49, 103, 3, // Skip to: 2364 /* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 97, 3, // Skip to: 2364 /* 1499 */ MCD_OPC_Decode, 208, 7, 134, 2, // Opcode: LUXC164 /* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 /* 1508 */ MCD_OPC_CheckPredicate, 48, 84, 3, // Skip to: 2364 /* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 78, 3, // Skip to: 2364 /* 1518 */ MCD_OPC_Decode, 167, 11, 135, 2, // Opcode: SDXC164 /* 1523 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1542 /* 1527 */ MCD_OPC_CheckPredicate, 49, 65, 3, // Skip to: 2364 /* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 59, 3, // Skip to: 2364 /* 1537 */ MCD_OPC_Decode, 233, 12, 135, 2, // Opcode: SUXC164 /* 1542 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 1555 /* 1546 */ MCD_OPC_CheckPredicate, 48, 46, 3, // Skip to: 2364 /* 1550 */ MCD_OPC_Decode, 144, 8, 136, 2, // Opcode: MADD_D64 /* 1555 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 1568 /* 1559 */ MCD_OPC_CheckPredicate, 48, 33, 3, // Skip to: 2364 /* 1563 */ MCD_OPC_Decode, 162, 9, 136, 2, // Opcode: MSUB_D64 /* 1568 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 1581 /* 1572 */ MCD_OPC_CheckPredicate, 48, 20, 3, // Skip to: 2364 /* 1576 */ MCD_OPC_Decode, 241, 9, 136, 2, // Opcode: NMADD_D64 /* 1581 */ MCD_OPC_FilterValue, 57, 11, 3, // Skip to: 2364 /* 1585 */ MCD_OPC_CheckPredicate, 48, 7, 3, // Skip to: 2364 /* 1589 */ MCD_OPC_Decode, 246, 9, 136, 2, // Opcode: NMSUB_D64 /* 1594 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1607 /* 1598 */ MCD_OPC_CheckPredicate, 41, 250, 2, // Skip to: 2364 /* 1602 */ MCD_OPC_Decode, 160, 4, 137, 2, // Opcode: DADDi /* 1607 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1620 /* 1611 */ MCD_OPC_CheckPredicate, 19, 237, 2, // Skip to: 2364 /* 1615 */ MCD_OPC_Decode, 161, 4, 137, 2, // Opcode: DADDiu /* 1620 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1633 /* 1624 */ MCD_OPC_CheckPredicate, 41, 224, 2, // Skip to: 2364 /* 1628 */ MCD_OPC_Decode, 172, 7, 217, 1, // Opcode: LDL /* 1633 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1646 /* 1637 */ MCD_OPC_CheckPredicate, 41, 211, 2, // Skip to: 2364 /* 1641 */ MCD_OPC_Decode, 174, 7, 217, 1, // Opcode: LDR /* 1646 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2065 /* 1650 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 1653 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1672 /* 1657 */ MCD_OPC_CheckPredicate, 50, 191, 2, // Skip to: 2364 /* 1661 */ MCD_OPC_CheckField, 6, 5, 0, 185, 2, // Skip to: 2364 /* 1667 */ MCD_OPC_Decode, 206, 4, 224, 1, // Opcode: DMUL /* 1672 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1691 /* 1676 */ MCD_OPC_CheckPredicate, 50, 172, 2, // Skip to: 2364 /* 1680 */ MCD_OPC_CheckField, 6, 15, 0, 166, 2, // Skip to: 2364 /* 1686 */ MCD_OPC_Decode, 185, 9, 138, 2, // Opcode: MTM0 /* 1691 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1710 /* 1695 */ MCD_OPC_CheckPredicate, 50, 153, 2, // Skip to: 2364 /* 1699 */ MCD_OPC_CheckField, 6, 15, 0, 147, 2, // Skip to: 2364 /* 1705 */ MCD_OPC_Decode, 188, 9, 138, 2, // Opcode: MTP0 /* 1710 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1729 /* 1714 */ MCD_OPC_CheckPredicate, 50, 134, 2, // Skip to: 2364 /* 1718 */ MCD_OPC_CheckField, 6, 15, 0, 128, 2, // Skip to: 2364 /* 1724 */ MCD_OPC_Decode, 189, 9, 138, 2, // Opcode: MTP1 /* 1729 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1748 /* 1733 */ MCD_OPC_CheckPredicate, 50, 115, 2, // Skip to: 2364 /* 1737 */ MCD_OPC_CheckField, 6, 15, 0, 109, 2, // Skip to: 2364 /* 1743 */ MCD_OPC_Decode, 190, 9, 138, 2, // Opcode: MTP2 /* 1748 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1767 /* 1752 */ MCD_OPC_CheckPredicate, 50, 96, 2, // Skip to: 2364 /* 1756 */ MCD_OPC_CheckField, 6, 15, 0, 90, 2, // Skip to: 2364 /* 1762 */ MCD_OPC_Decode, 186, 9, 138, 2, // Opcode: MTM1 /* 1767 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1786 /* 1771 */ MCD_OPC_CheckPredicate, 50, 77, 2, // Skip to: 2364 /* 1775 */ MCD_OPC_CheckField, 6, 15, 0, 71, 2, // Skip to: 2364 /* 1781 */ MCD_OPC_Decode, 187, 9, 138, 2, // Opcode: MTM2 /* 1786 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1805 /* 1790 */ MCD_OPC_CheckPredicate, 50, 58, 2, // Skip to: 2364 /* 1794 */ MCD_OPC_CheckField, 6, 5, 0, 52, 2, // Skip to: 2364 /* 1800 */ MCD_OPC_Decode, 226, 13, 224, 1, // Opcode: VMULU /* 1805 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1824 /* 1809 */ MCD_OPC_CheckPredicate, 50, 39, 2, // Skip to: 2364 /* 1813 */ MCD_OPC_CheckField, 6, 5, 0, 33, 2, // Skip to: 2364 /* 1819 */ MCD_OPC_Decode, 225, 13, 224, 1, // Opcode: VMM0 /* 1824 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1843 /* 1828 */ MCD_OPC_CheckPredicate, 50, 20, 2, // Skip to: 2364 /* 1832 */ MCD_OPC_CheckField, 6, 5, 0, 14, 2, // Skip to: 2364 /* 1838 */ MCD_OPC_Decode, 224, 13, 224, 1, // Opcode: V3MULU /* 1843 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1862 /* 1847 */ MCD_OPC_CheckPredicate, 51, 1, 2, // Skip to: 2364 /* 1851 */ MCD_OPC_CheckField, 6, 5, 0, 251, 1, // Skip to: 2364 /* 1857 */ MCD_OPC_Decode, 170, 4, 139, 2, // Opcode: DCLZ /* 1862 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1881 /* 1866 */ MCD_OPC_CheckPredicate, 51, 238, 1, // Skip to: 2364 /* 1870 */ MCD_OPC_CheckField, 6, 5, 0, 232, 1, // Skip to: 2364 /* 1876 */ MCD_OPC_Decode, 168, 4, 139, 2, // Opcode: DCLO /* 1881 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1900 /* 1885 */ MCD_OPC_CheckPredicate, 50, 219, 1, // Skip to: 2364 /* 1889 */ MCD_OPC_CheckField, 6, 5, 0, 213, 1, // Skip to: 2364 /* 1895 */ MCD_OPC_Decode, 166, 1, 224, 1, // Opcode: BADDu /* 1900 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1919 /* 1904 */ MCD_OPC_CheckPredicate, 50, 200, 1, // Skip to: 2364 /* 1908 */ MCD_OPC_CheckField, 6, 5, 0, 194, 1, // Skip to: 2364 /* 1914 */ MCD_OPC_Decode, 184, 11, 224, 1, // Opcode: SEQ /* 1919 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1938 /* 1923 */ MCD_OPC_CheckPredicate, 50, 181, 1, // Skip to: 2364 /* 1927 */ MCD_OPC_CheckField, 6, 5, 0, 175, 1, // Skip to: 2364 /* 1933 */ MCD_OPC_Decode, 252, 11, 224, 1, // Opcode: SNE /* 1938 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1962 /* 1942 */ MCD_OPC_CheckPredicate, 50, 162, 1, // Skip to: 2364 /* 1946 */ MCD_OPC_CheckField, 16, 5, 0, 156, 1, // Skip to: 2364 /* 1952 */ MCD_OPC_CheckField, 6, 5, 0, 150, 1, // Skip to: 2364 /* 1958 */ MCD_OPC_Decode, 163, 10, 62, // Opcode: POP /* 1962 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1987 /* 1966 */ MCD_OPC_CheckPredicate, 50, 138, 1, // Skip to: 2364 /* 1970 */ MCD_OPC_CheckField, 16, 5, 0, 132, 1, // Skip to: 2364 /* 1976 */ MCD_OPC_CheckField, 6, 5, 0, 126, 1, // Skip to: 2364 /* 1982 */ MCD_OPC_Decode, 231, 4, 222, 1, // Opcode: DPOP /* 1987 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 2000 /* 1991 */ MCD_OPC_CheckPredicate, 50, 113, 1, // Skip to: 2364 /* 1995 */ MCD_OPC_Decode, 185, 11, 140, 2, // Opcode: SEQi /* 2000 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 2013 /* 2004 */ MCD_OPC_CheckPredicate, 50, 100, 1, // Skip to: 2364 /* 2008 */ MCD_OPC_Decode, 253, 11, 140, 2, // Opcode: SNEi /* 2013 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2026 /* 2017 */ MCD_OPC_CheckPredicate, 50, 87, 1, // Skip to: 2364 /* 2021 */ MCD_OPC_Decode, 241, 2, 141, 2, // Opcode: CINS /* 2026 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 2039 /* 2030 */ MCD_OPC_CheckPredicate, 50, 74, 1, // Skip to: 2364 /* 2034 */ MCD_OPC_Decode, 242, 2, 141, 2, // Opcode: CINS32 /* 2039 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2052 /* 2043 */ MCD_OPC_CheckPredicate, 50, 61, 1, // Skip to: 2364 /* 2047 */ MCD_OPC_Decode, 158, 5, 141, 2, // Opcode: EXTS /* 2052 */ MCD_OPC_FilterValue, 59, 52, 1, // Skip to: 2364 /* 2056 */ MCD_OPC_CheckPredicate, 50, 48, 1, // Skip to: 2364 /* 2060 */ MCD_OPC_Decode, 159, 5, 141, 2, // Opcode: EXTS32 /* 2065 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2195 /* 2069 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 2072 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2085 /* 2076 */ MCD_OPC_CheckPredicate, 6, 28, 1, // Skip to: 2364 /* 2080 */ MCD_OPC_Decode, 177, 4, 142, 2, // Opcode: DEXTM /* 2085 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2098 /* 2089 */ MCD_OPC_CheckPredicate, 6, 15, 1, // Skip to: 2364 /* 2093 */ MCD_OPC_Decode, 178, 4, 142, 2, // Opcode: DEXTU /* 2098 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2111 /* 2102 */ MCD_OPC_CheckPredicate, 6, 2, 1, // Skip to: 2364 /* 2106 */ MCD_OPC_Decode, 176, 4, 142, 2, // Opcode: DEXT /* 2111 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2124 /* 2115 */ MCD_OPC_CheckPredicate, 6, 245, 0, // Skip to: 2364 /* 2119 */ MCD_OPC_Decode, 181, 4, 143, 2, // Opcode: DINSM /* 2124 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2137 /* 2128 */ MCD_OPC_CheckPredicate, 6, 232, 0, // Skip to: 2364 /* 2132 */ MCD_OPC_Decode, 182, 4, 143, 2, // Opcode: DINSU /* 2137 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2150 /* 2141 */ MCD_OPC_CheckPredicate, 6, 219, 0, // Skip to: 2364 /* 2145 */ MCD_OPC_Decode, 180, 4, 143, 2, // Opcode: DINS /* 2150 */ MCD_OPC_FilterValue, 36, 210, 0, // Skip to: 2364 /* 2154 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 2157 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2176 /* 2161 */ MCD_OPC_CheckPredicate, 40, 199, 0, // Skip to: 2364 /* 2165 */ MCD_OPC_CheckField, 21, 5, 0, 193, 0, // Skip to: 2364 /* 2171 */ MCD_OPC_Decode, 249, 4, 243, 1, // Opcode: DSBH /* 2176 */ MCD_OPC_FilterValue, 5, 184, 0, // Skip to: 2364 /* 2180 */ MCD_OPC_CheckPredicate, 40, 180, 0, // Skip to: 2364 /* 2184 */ MCD_OPC_CheckField, 21, 5, 0, 174, 0, // Skip to: 2364 /* 2190 */ MCD_OPC_Decode, 251, 4, 243, 1, // Opcode: DSHD /* 2195 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2208 /* 2199 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 2364 /* 2203 */ MCD_OPC_Decode, 241, 7, 217, 1, // Opcode: LWu /* 2208 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2221 /* 2212 */ MCD_OPC_CheckPredicate, 41, 148, 0, // Skip to: 2364 /* 2216 */ MCD_OPC_Decode, 164, 11, 217, 1, // Opcode: SDL /* 2221 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2234 /* 2225 */ MCD_OPC_CheckPredicate, 41, 135, 0, // Skip to: 2364 /* 2229 */ MCD_OPC_Decode, 165, 11, 217, 1, // Opcode: SDR /* 2234 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 2247 /* 2238 */ MCD_OPC_CheckPredicate, 50, 122, 0, // Skip to: 2364 /* 2242 */ MCD_OPC_Decode, 171, 1, 144, 2, // Opcode: BBIT0 /* 2247 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2260 /* 2251 */ MCD_OPC_CheckPredicate, 41, 109, 0, // Skip to: 2364 /* 2255 */ MCD_OPC_Decode, 194, 7, 217, 1, // Opcode: LLD /* 2260 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2273 /* 2264 */ MCD_OPC_CheckPredicate, 52, 96, 0, // Skip to: 2364 /* 2268 */ MCD_OPC_Decode, 163, 7, 219, 1, // Opcode: LDC164 /* 2273 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 2286 /* 2277 */ MCD_OPC_CheckPredicate, 50, 83, 0, // Skip to: 2364 /* 2281 */ MCD_OPC_Decode, 172, 1, 144, 2, // Opcode: BBIT032 /* 2286 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2299 /* 2290 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 2364 /* 2294 */ MCD_OPC_Decode, 161, 7, 217, 1, // Opcode: LD /* 2299 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2312 /* 2303 */ MCD_OPC_CheckPredicate, 50, 57, 0, // Skip to: 2364 /* 2307 */ MCD_OPC_Decode, 173, 1, 144, 2, // Opcode: BBIT1 /* 2312 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2325 /* 2316 */ MCD_OPC_CheckPredicate, 41, 44, 0, // Skip to: 2364 /* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD /* 2325 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2338 /* 2329 */ MCD_OPC_CheckPredicate, 52, 31, 0, // Skip to: 2364 /* 2333 */ MCD_OPC_Decode, 157, 11, 219, 1, // Opcode: SDC164 /* 2338 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 2351 /* 2342 */ MCD_OPC_CheckPredicate, 50, 18, 0, // Skip to: 2364 /* 2346 */ MCD_OPC_Decode, 174, 1, 144, 2, // Opcode: BBIT132 /* 2351 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2364 /* 2355 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 2364 /* 2359 */ MCD_OPC_Decode, 151, 11, 217, 1, // Opcode: SD /* 2364 */ MCD_OPC_Fail, 0 }; static bool getbool(uint64_t b) { return b != 0; } static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { default: // llvm_unreachable("Invalid index!"); case 0: return getbool((Bits & Mips_FeatureMips16)); case 1: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); case 2: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMicroMips)); case 3: return getbool((Bits & Mips_FeatureMicroMips)); case 4: return getbool((Bits & Mips_FeatureMips32) && (Bits & Mips_FeatureMicroMips)); case 5: return getbool(!(Bits & Mips_FeatureMips16)); case 6: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); case 7: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 8: return getbool((Bits & Mips_FeatureMSA)); case 9: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 10: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); case 11: return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); case 12: return getbool((Bits & Mips_FeatureDSP)); case 13: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 14: return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); case 15: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); case 16: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 17: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); case 18: return getbool(!(Bits & Mips_FeatureMicroMips)); case 19: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); case 20: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); case 21: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); case 22: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); case 23: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); case 24: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 25: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); case 26: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 27: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); case 28: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 29: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 30: return getbool((Bits & Mips_FeatureDSPR2)); case 31: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 32: return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); case 33: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); case 34: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); case 35: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); case 36: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); case 37: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); case 38: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); case 39: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); case 40: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); case 41: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 42: return getbool((Bits & Mips_FeatureMips64)); case 43: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); case 44: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); case 45: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); case 46: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 47: return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); case 48: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 49: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); case 50: return getbool((Bits & Mips_FeatureCnMips)); case 51: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); case 52: return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); } } #define DecodeToMCInst(fname,fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, void *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ default: \ case 0: \ return S; \ case 1: \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 2: \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 3: \ tmp = 0; \ tmp |= fieldname(insn, 3, 2) << 3; \ tmp |= fieldname(insn, 5, 3) << 0; \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 4: \ tmp = fieldname(insn, 0, 4); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 5: \ tmp = fieldname(insn, 2, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 6: \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 7: \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 8: \ tmp = 0; \ tmp |= fieldname(insn, 0, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 11; \ tmp |= fieldname(insn, 21, 6) << 5; \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 9: \ tmp = fieldname(insn, 5, 3); \ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 10: \ if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 11: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 12: \ if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 13: \ tmp = fieldname(insn, 5, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 14: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 15: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 16: \ tmp = fieldname(insn, 3, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 17: \ tmp = fieldname(insn, 3, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 3, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 18: \ if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 19: \ tmp = fieldname(insn, 0, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 20: \ tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 21: \ tmp = fieldname(insn, 0, 5); \ if (DecodeUImm5lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 22: \ if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 23: \ tmp = fieldname(insn, 5, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 4); \ if (DecodeSimm4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 24: \ tmp = fieldname(insn, 1, 9); \ if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 25: \ if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 26: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 3); \ if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 27: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 6); \ if (DecodeUImm6Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 28: \ tmp = fieldname(insn, 7, 3); \ if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 3); \ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 3); \ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 29: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 7); \ if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 30: \ tmp = fieldname(insn, 0, 10); \ if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 31: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 7); \ if (DecodeLiSimm7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 32: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 33: \ tmp = fieldname(insn, 16, 10); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 6, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 34: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 35: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 36: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 37: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 38: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 39: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 40: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 41: \ tmp = fieldname(insn, 16, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 42: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 43: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 44: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 45: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 46: \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 47: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 48: \ if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 49: \ if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 50: \ if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 51: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 52: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 53: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 54: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 3); \ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 55: \ if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 56: \ tmp = fieldname(insn, 23, 3); \ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 23); \ if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 57: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 58: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 59: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 3); \ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 60: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 2); \ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 61: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 62: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 63: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 64: \ tmp = fieldname(insn, 6, 20); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 65: \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 66: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 67: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 68: \ tmp = fieldname(insn, 11, 2); \ if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 69: \ tmp = fieldname(insn, 11, 2); \ if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 70: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 2); \ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 71: \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 72: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 73: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 74: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 75: \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 76: \ if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 77: \ if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 78: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 79: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 80: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 81: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 82: \ tmp = fieldname(insn, 18, 3); \ if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 83: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 84: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 85: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 86: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 87: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 88: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 89: \ tmp = fieldname(insn, 11, 5); \ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 90: \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 91: \ tmp = fieldname(insn, 18, 3); \ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 92: \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 93: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 94: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 95: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 3); \ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 96: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 97: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 98: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 99: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 100: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 101: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 102: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 103: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 3); \ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 104: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 105: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 106: \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 107: \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 108: \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 109: \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 110: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 111: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 112: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 113: \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 114: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 115: \ tmp = fieldname(insn, 6, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 116: \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 117: \ tmp = 0; \ tmp |= fieldname(insn, 11, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 118: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 119: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 120: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 121: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 122: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 123: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 124: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 125: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 126: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 127: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 128: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 129: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 130: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 131: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 132: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 133: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 134: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 135: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 136: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 137: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 138: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 139: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 140: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 141: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 142: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 143: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 144: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 145: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 146: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 147: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 148: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 149: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 150: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 151: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 152: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 153: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 154: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 155: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 156: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 157: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 158: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 159: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 160: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 161: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 162: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 163: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 164: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 165: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 166: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 167: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 168: \ tmp = fieldname(insn, 6, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 169: \ tmp = fieldname(insn, 6, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 170: \ tmp = fieldname(insn, 6, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 171: \ tmp = fieldname(insn, 6, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 172: \ tmp = fieldname(insn, 6, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 173: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 174: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 175: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 176: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 177: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 178: \ if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 179: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 180: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 181: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 182: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 183: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 184: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 185: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 186: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 187: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 188: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 189: \ tmp = fieldname(insn, 6, 5); \ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 190: \ if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 191: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 192: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 193: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 194: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 195: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 196: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 197: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 198: \ tmp = fieldname(insn, 21, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 199: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 200: \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 201: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 202: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 203: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 204: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 205: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 206: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 207: \ tmp = fieldname(insn, 11, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 208: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 209: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 210: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 211: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 212: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 213: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 214: \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 6); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 215: \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 216: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 217: \ if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 218: \ if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 219: \ if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 220: \ if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 221: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 222: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 223: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 224: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 225: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 226: \ if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 227: \ if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 228: \ if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 229: \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 230: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 231: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 232: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 233: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 234: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 235: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 236: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 237: \ tmp = fieldname(insn, 16, 5); \ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 238: \ if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 239: \ if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 240: \ if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 241: \ if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 242: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 243: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 244: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 245: \ if (DecodeCacheOpR6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 246: \ if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 247: \ tmp = fieldname(insn, 0, 26); \ if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 248: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 21); \ if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 249: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 19); \ if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 250: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 18); \ if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 251: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 252: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 253: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 254: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 255: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 256: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 257: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 258: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 259: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 3); \ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 260: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 261: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 262: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 263: \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 264: \ tmp = fieldname(insn, 6, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 265: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 266: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 267: \ tmp = 0; \ tmp |= fieldname(insn, 11, 5) << 0; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 268: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 269: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 270: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 271: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 6, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 272: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 0, 16); \ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \ { \ uint64_t Bits = getFeatureBits(feature); \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0, ExpectedValue; \ DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail; \ for (;;) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ Pred = checkDecoderPredicate(PIdx, Bits); \ if (!Pred) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_setOpcode(MI, Opc); \ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ } \ case MCD_OPC_SoftFail: { \ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ } FieldFromInstruction(fieldFromInstruction, uint32_t) DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) capstone-sys-0.15.0/capstone/arch/Mips/MipsGenInstrInfo.inc000064400000000000000000001316430072674642500217310ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Instruction Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { Mips_PHI = 0, Mips_INLINEASM = 1, Mips_CFI_INSTRUCTION = 2, Mips_EH_LABEL = 3, Mips_GC_LABEL = 4, Mips_KILL = 5, Mips_EXTRACT_SUBREG = 6, Mips_INSERT_SUBREG = 7, Mips_IMPLICIT_DEF = 8, Mips_SUBREG_TO_REG = 9, Mips_COPY_TO_REGCLASS = 10, Mips_DBG_VALUE = 11, Mips_REG_SEQUENCE = 12, Mips_COPY = 13, Mips_BUNDLE = 14, Mips_LIFETIME_START = 15, Mips_LIFETIME_END = 16, Mips_STACKMAP = 17, Mips_PATCHPOINT = 18, Mips_LOAD_STACK_GUARD = 19, Mips_STATEPOINT = 20, Mips_FRAME_ALLOC = 21, Mips_ABSQ_S_PH = 22, Mips_ABSQ_S_QB = 23, Mips_ABSQ_S_W = 24, Mips_ADD = 25, Mips_ADDIUPC = 26, Mips_ADDIUPC_MM = 27, Mips_ADDIUR1SP_MM = 28, Mips_ADDIUR2_MM = 29, Mips_ADDIUS5_MM = 30, Mips_ADDIUSP_MM = 31, Mips_ADDQH_PH = 32, Mips_ADDQH_R_PH = 33, Mips_ADDQH_R_W = 34, Mips_ADDQH_W = 35, Mips_ADDQ_PH = 36, Mips_ADDQ_S_PH = 37, Mips_ADDQ_S_W = 38, Mips_ADDSC = 39, Mips_ADDS_A_B = 40, Mips_ADDS_A_D = 41, Mips_ADDS_A_H = 42, Mips_ADDS_A_W = 43, Mips_ADDS_S_B = 44, Mips_ADDS_S_D = 45, Mips_ADDS_S_H = 46, Mips_ADDS_S_W = 47, Mips_ADDS_U_B = 48, Mips_ADDS_U_D = 49, Mips_ADDS_U_H = 50, Mips_ADDS_U_W = 51, Mips_ADDU16_MM = 52, Mips_ADDUH_QB = 53, Mips_ADDUH_R_QB = 54, Mips_ADDU_PH = 55, Mips_ADDU_QB = 56, Mips_ADDU_S_PH = 57, Mips_ADDU_S_QB = 58, Mips_ADDVI_B = 59, Mips_ADDVI_D = 60, Mips_ADDVI_H = 61, Mips_ADDVI_W = 62, Mips_ADDV_B = 63, Mips_ADDV_D = 64, Mips_ADDV_H = 65, Mips_ADDV_W = 66, Mips_ADDWC = 67, Mips_ADD_A_B = 68, Mips_ADD_A_D = 69, Mips_ADD_A_H = 70, Mips_ADD_A_W = 71, Mips_ADD_MM = 72, Mips_ADDi = 73, Mips_ADDi_MM = 74, Mips_ADDiu = 75, Mips_ADDiu_MM = 76, Mips_ADDu = 77, Mips_ADDu_MM = 78, Mips_ADJCALLSTACKDOWN = 79, Mips_ADJCALLSTACKUP = 80, Mips_ALIGN = 81, Mips_ALUIPC = 82, Mips_AND = 83, Mips_AND16_MM = 84, Mips_AND64 = 85, Mips_ANDI16_MM = 86, Mips_ANDI_B = 87, Mips_AND_MM = 88, Mips_AND_V = 89, Mips_AND_V_D_PSEUDO = 90, Mips_AND_V_H_PSEUDO = 91, Mips_AND_V_W_PSEUDO = 92, Mips_ANDi = 93, Mips_ANDi64 = 94, Mips_ANDi_MM = 95, Mips_APPEND = 96, Mips_ASUB_S_B = 97, Mips_ASUB_S_D = 98, Mips_ASUB_S_H = 99, Mips_ASUB_S_W = 100, Mips_ASUB_U_B = 101, Mips_ASUB_U_D = 102, Mips_ASUB_U_H = 103, Mips_ASUB_U_W = 104, Mips_ATOMIC_CMP_SWAP_I16 = 105, Mips_ATOMIC_CMP_SWAP_I32 = 106, Mips_ATOMIC_CMP_SWAP_I64 = 107, Mips_ATOMIC_CMP_SWAP_I8 = 108, Mips_ATOMIC_LOAD_ADD_I16 = 109, Mips_ATOMIC_LOAD_ADD_I32 = 110, Mips_ATOMIC_LOAD_ADD_I64 = 111, Mips_ATOMIC_LOAD_ADD_I8 = 112, Mips_ATOMIC_LOAD_AND_I16 = 113, Mips_ATOMIC_LOAD_AND_I32 = 114, Mips_ATOMIC_LOAD_AND_I64 = 115, Mips_ATOMIC_LOAD_AND_I8 = 116, Mips_ATOMIC_LOAD_NAND_I16 = 117, Mips_ATOMIC_LOAD_NAND_I32 = 118, Mips_ATOMIC_LOAD_NAND_I64 = 119, Mips_ATOMIC_LOAD_NAND_I8 = 120, Mips_ATOMIC_LOAD_OR_I16 = 121, Mips_ATOMIC_LOAD_OR_I32 = 122, Mips_ATOMIC_LOAD_OR_I64 = 123, Mips_ATOMIC_LOAD_OR_I8 = 124, Mips_ATOMIC_LOAD_SUB_I16 = 125, Mips_ATOMIC_LOAD_SUB_I32 = 126, Mips_ATOMIC_LOAD_SUB_I64 = 127, Mips_ATOMIC_LOAD_SUB_I8 = 128, Mips_ATOMIC_LOAD_XOR_I16 = 129, Mips_ATOMIC_LOAD_XOR_I32 = 130, Mips_ATOMIC_LOAD_XOR_I64 = 131, Mips_ATOMIC_LOAD_XOR_I8 = 132, Mips_ATOMIC_SWAP_I16 = 133, Mips_ATOMIC_SWAP_I32 = 134, Mips_ATOMIC_SWAP_I64 = 135, Mips_ATOMIC_SWAP_I8 = 136, Mips_AUI = 137, Mips_AUIPC = 138, Mips_AVER_S_B = 139, Mips_AVER_S_D = 140, Mips_AVER_S_H = 141, Mips_AVER_S_W = 142, Mips_AVER_U_B = 143, Mips_AVER_U_D = 144, Mips_AVER_U_H = 145, Mips_AVER_U_W = 146, Mips_AVE_S_B = 147, Mips_AVE_S_D = 148, Mips_AVE_S_H = 149, Mips_AVE_S_W = 150, Mips_AVE_U_B = 151, Mips_AVE_U_D = 152, Mips_AVE_U_H = 153, Mips_AVE_U_W = 154, Mips_AddiuRxImmX16 = 155, Mips_AddiuRxPcImmX16 = 156, Mips_AddiuRxRxImm16 = 157, Mips_AddiuRxRxImmX16 = 158, Mips_AddiuRxRyOffMemX16 = 159, Mips_AddiuSpImm16 = 160, Mips_AddiuSpImmX16 = 161, Mips_AdduRxRyRz16 = 162, Mips_AndRxRxRy16 = 163, Mips_B = 164, Mips_B16_MM = 165, Mips_BADDu = 166, Mips_BAL = 167, Mips_BALC = 168, Mips_BALIGN = 169, Mips_BAL_BR = 170, Mips_BBIT0 = 171, Mips_BBIT032 = 172, Mips_BBIT1 = 173, Mips_BBIT132 = 174, Mips_BC = 175, Mips_BC0F = 176, Mips_BC0FL = 177, Mips_BC0T = 178, Mips_BC0TL = 179, Mips_BC1EQZ = 180, Mips_BC1F = 181, Mips_BC1FL = 182, Mips_BC1F_MM = 183, Mips_BC1NEZ = 184, Mips_BC1T = 185, Mips_BC1TL = 186, Mips_BC1T_MM = 187, Mips_BC2EQZ = 188, Mips_BC2F = 189, Mips_BC2FL = 190, Mips_BC2NEZ = 191, Mips_BC2T = 192, Mips_BC2TL = 193, Mips_BC3F = 194, Mips_BC3FL = 195, Mips_BC3T = 196, Mips_BC3TL = 197, Mips_BCLRI_B = 198, Mips_BCLRI_D = 199, Mips_BCLRI_H = 200, Mips_BCLRI_W = 201, Mips_BCLR_B = 202, Mips_BCLR_D = 203, Mips_BCLR_H = 204, Mips_BCLR_W = 205, Mips_BEQ = 206, Mips_BEQ64 = 207, Mips_BEQC = 208, Mips_BEQL = 209, Mips_BEQZ16_MM = 210, Mips_BEQZALC = 211, Mips_BEQZC = 212, Mips_BEQZC_MM = 213, Mips_BEQ_MM = 214, Mips_BGEC = 215, Mips_BGEUC = 216, Mips_BGEZ = 217, Mips_BGEZ64 = 218, Mips_BGEZAL = 219, Mips_BGEZALC = 220, Mips_BGEZALL = 221, Mips_BGEZALS_MM = 222, Mips_BGEZAL_MM = 223, Mips_BGEZC = 224, Mips_BGEZL = 225, Mips_BGEZ_MM = 226, Mips_BGTZ = 227, Mips_BGTZ64 = 228, Mips_BGTZALC = 229, Mips_BGTZC = 230, Mips_BGTZL = 231, Mips_BGTZ_MM = 232, Mips_BINSLI_B = 233, Mips_BINSLI_D = 234, Mips_BINSLI_H = 235, Mips_BINSLI_W = 236, Mips_BINSL_B = 237, Mips_BINSL_D = 238, Mips_BINSL_H = 239, Mips_BINSL_W = 240, Mips_BINSRI_B = 241, Mips_BINSRI_D = 242, Mips_BINSRI_H = 243, Mips_BINSRI_W = 244, Mips_BINSR_B = 245, Mips_BINSR_D = 246, Mips_BINSR_H = 247, Mips_BINSR_W = 248, Mips_BITREV = 249, Mips_BITSWAP = 250, Mips_BLEZ = 251, Mips_BLEZ64 = 252, Mips_BLEZALC = 253, Mips_BLEZC = 254, Mips_BLEZL = 255, Mips_BLEZ_MM = 256, Mips_BLTC = 257, Mips_BLTUC = 258, Mips_BLTZ = 259, Mips_BLTZ64 = 260, Mips_BLTZAL = 261, Mips_BLTZALC = 262, Mips_BLTZALL = 263, Mips_BLTZALS_MM = 264, Mips_BLTZAL_MM = 265, Mips_BLTZC = 266, Mips_BLTZL = 267, Mips_BLTZ_MM = 268, Mips_BMNZI_B = 269, Mips_BMNZ_V = 270, Mips_BMZI_B = 271, Mips_BMZ_V = 272, Mips_BNE = 273, Mips_BNE64 = 274, Mips_BNEC = 275, Mips_BNEGI_B = 276, Mips_BNEGI_D = 277, Mips_BNEGI_H = 278, Mips_BNEGI_W = 279, Mips_BNEG_B = 280, Mips_BNEG_D = 281, Mips_BNEG_H = 282, Mips_BNEG_W = 283, Mips_BNEL = 284, Mips_BNEZ16_MM = 285, Mips_BNEZALC = 286, Mips_BNEZC = 287, Mips_BNEZC_MM = 288, Mips_BNE_MM = 289, Mips_BNVC = 290, Mips_BNZ_B = 291, Mips_BNZ_D = 292, Mips_BNZ_H = 293, Mips_BNZ_V = 294, Mips_BNZ_W = 295, Mips_BOVC = 296, Mips_BPOSGE32 = 297, Mips_BPOSGE32_PSEUDO = 298, Mips_BREAK = 299, Mips_BREAK16_MM = 300, Mips_BREAK_MM = 301, Mips_BSELI_B = 302, Mips_BSEL_D_PSEUDO = 303, Mips_BSEL_FD_PSEUDO = 304, Mips_BSEL_FW_PSEUDO = 305, Mips_BSEL_H_PSEUDO = 306, Mips_BSEL_V = 307, Mips_BSEL_W_PSEUDO = 308, Mips_BSETI_B = 309, Mips_BSETI_D = 310, Mips_BSETI_H = 311, Mips_BSETI_W = 312, Mips_BSET_B = 313, Mips_BSET_D = 314, Mips_BSET_H = 315, Mips_BSET_W = 316, Mips_BZ_B = 317, Mips_BZ_D = 318, Mips_BZ_H = 319, Mips_BZ_V = 320, Mips_BZ_W = 321, Mips_B_MM_Pseudo = 322, Mips_BeqzRxImm16 = 323, Mips_BeqzRxImmX16 = 324, Mips_Bimm16 = 325, Mips_BimmX16 = 326, Mips_BnezRxImm16 = 327, Mips_BnezRxImmX16 = 328, Mips_Break16 = 329, Mips_Bteqz16 = 330, Mips_BteqzT8CmpX16 = 331, Mips_BteqzT8CmpiX16 = 332, Mips_BteqzT8SltX16 = 333, Mips_BteqzT8SltiX16 = 334, Mips_BteqzT8SltiuX16 = 335, Mips_BteqzT8SltuX16 = 336, Mips_BteqzX16 = 337, Mips_Btnez16 = 338, Mips_BtnezT8CmpX16 = 339, Mips_BtnezT8CmpiX16 = 340, Mips_BtnezT8SltX16 = 341, Mips_BtnezT8SltiX16 = 342, Mips_BtnezT8SltiuX16 = 343, Mips_BtnezT8SltuX16 = 344, Mips_BtnezX16 = 345, Mips_BuildPairF64 = 346, Mips_BuildPairF64_64 = 347, Mips_CACHE = 348, Mips_CACHE_MM = 349, Mips_CACHE_R6 = 350, Mips_CEIL_L_D64 = 351, Mips_CEIL_L_S = 352, Mips_CEIL_W_D32 = 353, Mips_CEIL_W_D64 = 354, Mips_CEIL_W_MM = 355, Mips_CEIL_W_S = 356, Mips_CEIL_W_S_MM = 357, Mips_CEQI_B = 358, Mips_CEQI_D = 359, Mips_CEQI_H = 360, Mips_CEQI_W = 361, Mips_CEQ_B = 362, Mips_CEQ_D = 363, Mips_CEQ_H = 364, Mips_CEQ_W = 365, Mips_CFC1 = 366, Mips_CFC1_MM = 367, Mips_CFCMSA = 368, Mips_CINS = 369, Mips_CINS32 = 370, Mips_CLASS_D = 371, Mips_CLASS_S = 372, Mips_CLEI_S_B = 373, Mips_CLEI_S_D = 374, Mips_CLEI_S_H = 375, Mips_CLEI_S_W = 376, Mips_CLEI_U_B = 377, Mips_CLEI_U_D = 378, Mips_CLEI_U_H = 379, Mips_CLEI_U_W = 380, Mips_CLE_S_B = 381, Mips_CLE_S_D = 382, Mips_CLE_S_H = 383, Mips_CLE_S_W = 384, Mips_CLE_U_B = 385, Mips_CLE_U_D = 386, Mips_CLE_U_H = 387, Mips_CLE_U_W = 388, Mips_CLO = 389, Mips_CLO_MM = 390, Mips_CLO_R6 = 391, Mips_CLTI_S_B = 392, Mips_CLTI_S_D = 393, Mips_CLTI_S_H = 394, Mips_CLTI_S_W = 395, Mips_CLTI_U_B = 396, Mips_CLTI_U_D = 397, Mips_CLTI_U_H = 398, Mips_CLTI_U_W = 399, Mips_CLT_S_B = 400, Mips_CLT_S_D = 401, Mips_CLT_S_H = 402, Mips_CLT_S_W = 403, Mips_CLT_U_B = 404, Mips_CLT_U_D = 405, Mips_CLT_U_H = 406, Mips_CLT_U_W = 407, Mips_CLZ = 408, Mips_CLZ_MM = 409, Mips_CLZ_R6 = 410, Mips_CMPGDU_EQ_QB = 411, Mips_CMPGDU_LE_QB = 412, Mips_CMPGDU_LT_QB = 413, Mips_CMPGU_EQ_QB = 414, Mips_CMPGU_LE_QB = 415, Mips_CMPGU_LT_QB = 416, Mips_CMPU_EQ_QB = 417, Mips_CMPU_LE_QB = 418, Mips_CMPU_LT_QB = 419, Mips_CMP_EQ_D = 420, Mips_CMP_EQ_PH = 421, Mips_CMP_EQ_S = 422, Mips_CMP_F_D = 423, Mips_CMP_F_S = 424, Mips_CMP_LE_D = 425, Mips_CMP_LE_PH = 426, Mips_CMP_LE_S = 427, Mips_CMP_LT_D = 428, Mips_CMP_LT_PH = 429, Mips_CMP_LT_S = 430, Mips_CMP_SAF_D = 431, Mips_CMP_SAF_S = 432, Mips_CMP_SEQ_D = 433, Mips_CMP_SEQ_S = 434, Mips_CMP_SLE_D = 435, Mips_CMP_SLE_S = 436, Mips_CMP_SLT_D = 437, Mips_CMP_SLT_S = 438, Mips_CMP_SUEQ_D = 439, Mips_CMP_SUEQ_S = 440, Mips_CMP_SULE_D = 441, Mips_CMP_SULE_S = 442, Mips_CMP_SULT_D = 443, Mips_CMP_SULT_S = 444, Mips_CMP_SUN_D = 445, Mips_CMP_SUN_S = 446, Mips_CMP_UEQ_D = 447, Mips_CMP_UEQ_S = 448, Mips_CMP_ULE_D = 449, Mips_CMP_ULE_S = 450, Mips_CMP_ULT_D = 451, Mips_CMP_ULT_S = 452, Mips_CMP_UN_D = 453, Mips_CMP_UN_S = 454, Mips_CONSTPOOL_ENTRY = 455, Mips_COPY_FD_PSEUDO = 456, Mips_COPY_FW_PSEUDO = 457, Mips_COPY_S_B = 458, Mips_COPY_S_D = 459, Mips_COPY_S_H = 460, Mips_COPY_S_W = 461, Mips_COPY_U_B = 462, Mips_COPY_U_D = 463, Mips_COPY_U_H = 464, Mips_COPY_U_W = 465, Mips_CTC1 = 466, Mips_CTC1_MM = 467, Mips_CTCMSA = 468, Mips_CVT_D32_S = 469, Mips_CVT_D32_W = 470, Mips_CVT_D32_W_MM = 471, Mips_CVT_D64_L = 472, Mips_CVT_D64_S = 473, Mips_CVT_D64_W = 474, Mips_CVT_D_S_MM = 475, Mips_CVT_L_D64 = 476, Mips_CVT_L_D64_MM = 477, Mips_CVT_L_S = 478, Mips_CVT_L_S_MM = 479, Mips_CVT_S_D32 = 480, Mips_CVT_S_D32_MM = 481, Mips_CVT_S_D64 = 482, Mips_CVT_S_L = 483, Mips_CVT_S_W = 484, Mips_CVT_S_W_MM = 485, Mips_CVT_W_D32 = 486, Mips_CVT_W_D64 = 487, Mips_CVT_W_MM = 488, Mips_CVT_W_S = 489, Mips_CVT_W_S_MM = 490, Mips_C_EQ_D32 = 491, Mips_C_EQ_D64 = 492, Mips_C_EQ_S = 493, Mips_C_F_D32 = 494, Mips_C_F_D64 = 495, Mips_C_F_S = 496, Mips_C_LE_D32 = 497, Mips_C_LE_D64 = 498, Mips_C_LE_S = 499, Mips_C_LT_D32 = 500, Mips_C_LT_D64 = 501, Mips_C_LT_S = 502, Mips_C_NGE_D32 = 503, Mips_C_NGE_D64 = 504, Mips_C_NGE_S = 505, Mips_C_NGLE_D32 = 506, Mips_C_NGLE_D64 = 507, Mips_C_NGLE_S = 508, Mips_C_NGL_D32 = 509, Mips_C_NGL_D64 = 510, Mips_C_NGL_S = 511, Mips_C_NGT_D32 = 512, Mips_C_NGT_D64 = 513, Mips_C_NGT_S = 514, Mips_C_OLE_D32 = 515, Mips_C_OLE_D64 = 516, Mips_C_OLE_S = 517, Mips_C_OLT_D32 = 518, Mips_C_OLT_D64 = 519, Mips_C_OLT_S = 520, Mips_C_SEQ_D32 = 521, Mips_C_SEQ_D64 = 522, Mips_C_SEQ_S = 523, Mips_C_SF_D32 = 524, Mips_C_SF_D64 = 525, Mips_C_SF_S = 526, Mips_C_UEQ_D32 = 527, Mips_C_UEQ_D64 = 528, Mips_C_UEQ_S = 529, Mips_C_ULE_D32 = 530, Mips_C_ULE_D64 = 531, Mips_C_ULE_S = 532, Mips_C_ULT_D32 = 533, Mips_C_ULT_D64 = 534, Mips_C_ULT_S = 535, Mips_C_UN_D32 = 536, Mips_C_UN_D64 = 537, Mips_C_UN_S = 538, Mips_CmpRxRy16 = 539, Mips_CmpiRxImm16 = 540, Mips_CmpiRxImmX16 = 541, Mips_Constant32 = 542, Mips_DADD = 543, Mips_DADDi = 544, Mips_DADDiu = 545, Mips_DADDu = 546, Mips_DAHI = 547, Mips_DALIGN = 548, Mips_DATI = 549, Mips_DAUI = 550, Mips_DBITSWAP = 551, Mips_DCLO = 552, Mips_DCLO_R6 = 553, Mips_DCLZ = 554, Mips_DCLZ_R6 = 555, Mips_DDIV = 556, Mips_DDIVU = 557, Mips_DERET = 558, Mips_DERET_MM = 559, Mips_DEXT = 560, Mips_DEXTM = 561, Mips_DEXTU = 562, Mips_DI = 563, Mips_DINS = 564, Mips_DINSM = 565, Mips_DINSU = 566, Mips_DIV = 567, Mips_DIVU = 568, Mips_DIV_S_B = 569, Mips_DIV_S_D = 570, Mips_DIV_S_H = 571, Mips_DIV_S_W = 572, Mips_DIV_U_B = 573, Mips_DIV_U_D = 574, Mips_DIV_U_H = 575, Mips_DIV_U_W = 576, Mips_DI_MM = 577, Mips_DLSA = 578, Mips_DLSA_R6 = 579, Mips_DMFC0 = 580, Mips_DMFC1 = 581, Mips_DMFC2 = 582, Mips_DMOD = 583, Mips_DMODU = 584, Mips_DMTC0 = 585, Mips_DMTC1 = 586, Mips_DMTC2 = 587, Mips_DMUH = 588, Mips_DMUHU = 589, Mips_DMUL = 590, Mips_DMULT = 591, Mips_DMULTu = 592, Mips_DMULU = 593, Mips_DMUL_R6 = 594, Mips_DOTP_S_D = 595, Mips_DOTP_S_H = 596, Mips_DOTP_S_W = 597, Mips_DOTP_U_D = 598, Mips_DOTP_U_H = 599, Mips_DOTP_U_W = 600, Mips_DPADD_S_D = 601, Mips_DPADD_S_H = 602, Mips_DPADD_S_W = 603, Mips_DPADD_U_D = 604, Mips_DPADD_U_H = 605, Mips_DPADD_U_W = 606, Mips_DPAQX_SA_W_PH = 607, Mips_DPAQX_S_W_PH = 608, Mips_DPAQ_SA_L_W = 609, Mips_DPAQ_S_W_PH = 610, Mips_DPAU_H_QBL = 611, Mips_DPAU_H_QBR = 612, Mips_DPAX_W_PH = 613, Mips_DPA_W_PH = 614, Mips_DPOP = 615, Mips_DPSQX_SA_W_PH = 616, Mips_DPSQX_S_W_PH = 617, Mips_DPSQ_SA_L_W = 618, Mips_DPSQ_S_W_PH = 619, Mips_DPSUB_S_D = 620, Mips_DPSUB_S_H = 621, Mips_DPSUB_S_W = 622, Mips_DPSUB_U_D = 623, Mips_DPSUB_U_H = 624, Mips_DPSUB_U_W = 625, Mips_DPSU_H_QBL = 626, Mips_DPSU_H_QBR = 627, Mips_DPSX_W_PH = 628, Mips_DPS_W_PH = 629, Mips_DROTR = 630, Mips_DROTR32 = 631, Mips_DROTRV = 632, Mips_DSBH = 633, Mips_DSDIV = 634, Mips_DSHD = 635, Mips_DSLL = 636, Mips_DSLL32 = 637, Mips_DSLL64_32 = 638, Mips_DSLLV = 639, Mips_DSRA = 640, Mips_DSRA32 = 641, Mips_DSRAV = 642, Mips_DSRL = 643, Mips_DSRL32 = 644, Mips_DSRLV = 645, Mips_DSUB = 646, Mips_DSUBu = 647, Mips_DUDIV = 648, Mips_DivRxRy16 = 649, Mips_DivuRxRy16 = 650, Mips_EHB = 651, Mips_EHB_MM = 652, Mips_EI = 653, Mips_EI_MM = 654, Mips_ERET = 655, Mips_ERET_MM = 656, Mips_EXT = 657, Mips_EXTP = 658, Mips_EXTPDP = 659, Mips_EXTPDPV = 660, Mips_EXTPV = 661, Mips_EXTRV_RS_W = 662, Mips_EXTRV_R_W = 663, Mips_EXTRV_S_H = 664, Mips_EXTRV_W = 665, Mips_EXTR_RS_W = 666, Mips_EXTR_R_W = 667, Mips_EXTR_S_H = 668, Mips_EXTR_W = 669, Mips_EXTS = 670, Mips_EXTS32 = 671, Mips_EXT_MM = 672, Mips_ExtractElementF64 = 673, Mips_ExtractElementF64_64 = 674, Mips_FABS_D = 675, Mips_FABS_D32 = 676, Mips_FABS_D64 = 677, Mips_FABS_MM = 678, Mips_FABS_S = 679, Mips_FABS_S_MM = 680, Mips_FABS_W = 681, Mips_FADD_D = 682, Mips_FADD_D32 = 683, Mips_FADD_D64 = 684, Mips_FADD_MM = 685, Mips_FADD_S = 686, Mips_FADD_S_MM = 687, Mips_FADD_W = 688, Mips_FCAF_D = 689, Mips_FCAF_W = 690, Mips_FCEQ_D = 691, Mips_FCEQ_W = 692, Mips_FCLASS_D = 693, Mips_FCLASS_W = 694, Mips_FCLE_D = 695, Mips_FCLE_W = 696, Mips_FCLT_D = 697, Mips_FCLT_W = 698, Mips_FCMP_D32 = 699, Mips_FCMP_D32_MM = 700, Mips_FCMP_D64 = 701, Mips_FCMP_S32 = 702, Mips_FCMP_S32_MM = 703, Mips_FCNE_D = 704, Mips_FCNE_W = 705, Mips_FCOR_D = 706, Mips_FCOR_W = 707, Mips_FCUEQ_D = 708, Mips_FCUEQ_W = 709, Mips_FCULE_D = 710, Mips_FCULE_W = 711, Mips_FCULT_D = 712, Mips_FCULT_W = 713, Mips_FCUNE_D = 714, Mips_FCUNE_W = 715, Mips_FCUN_D = 716, Mips_FCUN_W = 717, Mips_FDIV_D = 718, Mips_FDIV_D32 = 719, Mips_FDIV_D64 = 720, Mips_FDIV_MM = 721, Mips_FDIV_S = 722, Mips_FDIV_S_MM = 723, Mips_FDIV_W = 724, Mips_FEXDO_H = 725, Mips_FEXDO_W = 726, Mips_FEXP2_D = 727, Mips_FEXP2_D_1_PSEUDO = 728, Mips_FEXP2_W = 729, Mips_FEXP2_W_1_PSEUDO = 730, Mips_FEXUPL_D = 731, Mips_FEXUPL_W = 732, Mips_FEXUPR_D = 733, Mips_FEXUPR_W = 734, Mips_FFINT_S_D = 735, Mips_FFINT_S_W = 736, Mips_FFINT_U_D = 737, Mips_FFINT_U_W = 738, Mips_FFQL_D = 739, Mips_FFQL_W = 740, Mips_FFQR_D = 741, Mips_FFQR_W = 742, Mips_FILL_B = 743, Mips_FILL_D = 744, Mips_FILL_FD_PSEUDO = 745, Mips_FILL_FW_PSEUDO = 746, Mips_FILL_H = 747, Mips_FILL_W = 748, Mips_FLOG2_D = 749, Mips_FLOG2_W = 750, Mips_FLOOR_L_D64 = 751, Mips_FLOOR_L_S = 752, Mips_FLOOR_W_D32 = 753, Mips_FLOOR_W_D64 = 754, Mips_FLOOR_W_MM = 755, Mips_FLOOR_W_S = 756, Mips_FLOOR_W_S_MM = 757, Mips_FMADD_D = 758, Mips_FMADD_W = 759, Mips_FMAX_A_D = 760, Mips_FMAX_A_W = 761, Mips_FMAX_D = 762, Mips_FMAX_W = 763, Mips_FMIN_A_D = 764, Mips_FMIN_A_W = 765, Mips_FMIN_D = 766, Mips_FMIN_W = 767, Mips_FMOV_D32 = 768, Mips_FMOV_D32_MM = 769, Mips_FMOV_D64 = 770, Mips_FMOV_S = 771, Mips_FMOV_S_MM = 772, Mips_FMSUB_D = 773, Mips_FMSUB_W = 774, Mips_FMUL_D = 775, Mips_FMUL_D32 = 776, Mips_FMUL_D64 = 777, Mips_FMUL_MM = 778, Mips_FMUL_S = 779, Mips_FMUL_S_MM = 780, Mips_FMUL_W = 781, Mips_FNEG_D32 = 782, Mips_FNEG_D64 = 783, Mips_FNEG_MM = 784, Mips_FNEG_S = 785, Mips_FNEG_S_MM = 786, Mips_FRCP_D = 787, Mips_FRCP_W = 788, Mips_FRINT_D = 789, Mips_FRINT_W = 790, Mips_FRSQRT_D = 791, Mips_FRSQRT_W = 792, Mips_FSAF_D = 793, Mips_FSAF_W = 794, Mips_FSEQ_D = 795, Mips_FSEQ_W = 796, Mips_FSLE_D = 797, Mips_FSLE_W = 798, Mips_FSLT_D = 799, Mips_FSLT_W = 800, Mips_FSNE_D = 801, Mips_FSNE_W = 802, Mips_FSOR_D = 803, Mips_FSOR_W = 804, Mips_FSQRT_D = 805, Mips_FSQRT_D32 = 806, Mips_FSQRT_D64 = 807, Mips_FSQRT_MM = 808, Mips_FSQRT_S = 809, Mips_FSQRT_S_MM = 810, Mips_FSQRT_W = 811, Mips_FSUB_D = 812, Mips_FSUB_D32 = 813, Mips_FSUB_D64 = 814, Mips_FSUB_MM = 815, Mips_FSUB_S = 816, Mips_FSUB_S_MM = 817, Mips_FSUB_W = 818, Mips_FSUEQ_D = 819, Mips_FSUEQ_W = 820, Mips_FSULE_D = 821, Mips_FSULE_W = 822, Mips_FSULT_D = 823, Mips_FSULT_W = 824, Mips_FSUNE_D = 825, Mips_FSUNE_W = 826, Mips_FSUN_D = 827, Mips_FSUN_W = 828, Mips_FTINT_S_D = 829, Mips_FTINT_S_W = 830, Mips_FTINT_U_D = 831, Mips_FTINT_U_W = 832, Mips_FTQ_H = 833, Mips_FTQ_W = 834, Mips_FTRUNC_S_D = 835, Mips_FTRUNC_S_W = 836, Mips_FTRUNC_U_D = 837, Mips_FTRUNC_U_W = 838, Mips_GotPrologue16 = 839, Mips_HADD_S_D = 840, Mips_HADD_S_H = 841, Mips_HADD_S_W = 842, Mips_HADD_U_D = 843, Mips_HADD_U_H = 844, Mips_HADD_U_W = 845, Mips_HSUB_S_D = 846, Mips_HSUB_S_H = 847, Mips_HSUB_S_W = 848, Mips_HSUB_U_D = 849, Mips_HSUB_U_H = 850, Mips_HSUB_U_W = 851, Mips_ILVEV_B = 852, Mips_ILVEV_D = 853, Mips_ILVEV_H = 854, Mips_ILVEV_W = 855, Mips_ILVL_B = 856, Mips_ILVL_D = 857, Mips_ILVL_H = 858, Mips_ILVL_W = 859, Mips_ILVOD_B = 860, Mips_ILVOD_D = 861, Mips_ILVOD_H = 862, Mips_ILVOD_W = 863, Mips_ILVR_B = 864, Mips_ILVR_D = 865, Mips_ILVR_H = 866, Mips_ILVR_W = 867, Mips_INS = 868, Mips_INSERT_B = 869, Mips_INSERT_B_VIDX_PSEUDO = 870, Mips_INSERT_D = 871, Mips_INSERT_D_VIDX_PSEUDO = 872, Mips_INSERT_FD_PSEUDO = 873, Mips_INSERT_FD_VIDX_PSEUDO = 874, Mips_INSERT_FW_PSEUDO = 875, Mips_INSERT_FW_VIDX_PSEUDO = 876, Mips_INSERT_H = 877, Mips_INSERT_H_VIDX_PSEUDO = 878, Mips_INSERT_W = 879, Mips_INSERT_W_VIDX_PSEUDO = 880, Mips_INSV = 881, Mips_INSVE_B = 882, Mips_INSVE_D = 883, Mips_INSVE_H = 884, Mips_INSVE_W = 885, Mips_INS_MM = 886, Mips_J = 887, Mips_JAL = 888, Mips_JALR = 889, Mips_JALR16_MM = 890, Mips_JALR64 = 891, Mips_JALR64Pseudo = 892, Mips_JALRPseudo = 893, Mips_JALRS16_MM = 894, Mips_JALRS_MM = 895, Mips_JALR_HB = 896, Mips_JALR_MM = 897, Mips_JALS_MM = 898, Mips_JALX = 899, Mips_JALX_MM = 900, Mips_JAL_MM = 901, Mips_JIALC = 902, Mips_JIC = 903, Mips_JR = 904, Mips_JR16_MM = 905, Mips_JR64 = 906, Mips_JRADDIUSP = 907, Mips_JRC16_MM = 908, Mips_JR_HB = 909, Mips_JR_HB_R6 = 910, Mips_JR_MM = 911, Mips_J_MM = 912, Mips_Jal16 = 913, Mips_JalB16 = 914, Mips_JalOneReg = 915, Mips_JalTwoReg = 916, Mips_JrRa16 = 917, Mips_JrcRa16 = 918, Mips_JrcRx16 = 919, Mips_JumpLinkReg16 = 920, Mips_LB = 921, Mips_LB64 = 922, Mips_LBU16_MM = 923, Mips_LBUX = 924, Mips_LB_MM = 925, Mips_LBu = 926, Mips_LBu64 = 927, Mips_LBu_MM = 928, Mips_LD = 929, Mips_LDC1 = 930, Mips_LDC164 = 931, Mips_LDC1_MM = 932, Mips_LDC2 = 933, Mips_LDC2_R6 = 934, Mips_LDC3 = 935, Mips_LDI_B = 936, Mips_LDI_D = 937, Mips_LDI_H = 938, Mips_LDI_W = 939, Mips_LDL = 940, Mips_LDPC = 941, Mips_LDR = 942, Mips_LDXC1 = 943, Mips_LDXC164 = 944, Mips_LD_B = 945, Mips_LD_D = 946, Mips_LD_H = 947, Mips_LD_W = 948, Mips_LEA_ADDiu = 949, Mips_LEA_ADDiu64 = 950, Mips_LEA_ADDiu_MM = 951, Mips_LH = 952, Mips_LH64 = 953, Mips_LHU16_MM = 954, Mips_LHX = 955, Mips_LH_MM = 956, Mips_LHu = 957, Mips_LHu64 = 958, Mips_LHu_MM = 959, Mips_LI16_MM = 960, Mips_LL = 961, Mips_LLD = 962, Mips_LLD_R6 = 963, Mips_LL_MM = 964, Mips_LL_R6 = 965, Mips_LOAD_ACC128 = 966, Mips_LOAD_ACC64 = 967, Mips_LOAD_ACC64DSP = 968, Mips_LOAD_CCOND_DSP = 969, Mips_LONG_BRANCH_ADDiu = 970, Mips_LONG_BRANCH_DADDiu = 971, Mips_LONG_BRANCH_LUi = 972, Mips_LSA = 973, Mips_LSA_R6 = 974, Mips_LUXC1 = 975, Mips_LUXC164 = 976, Mips_LUXC1_MM = 977, Mips_LUi = 978, Mips_LUi64 = 979, Mips_LUi_MM = 980, Mips_LW = 981, Mips_LW16_MM = 982, Mips_LW64 = 983, Mips_LWC1 = 984, Mips_LWC1_MM = 985, Mips_LWC2 = 986, Mips_LWC2_R6 = 987, Mips_LWC3 = 988, Mips_LWGP_MM = 989, Mips_LWL = 990, Mips_LWL64 = 991, Mips_LWL_MM = 992, Mips_LWM16_MM = 993, Mips_LWM32_MM = 994, Mips_LWM_MM = 995, Mips_LWPC = 996, Mips_LWP_MM = 997, Mips_LWR = 998, Mips_LWR64 = 999, Mips_LWR_MM = 1000, Mips_LWSP_MM = 1001, Mips_LWUPC = 1002, Mips_LWU_MM = 1003, Mips_LWX = 1004, Mips_LWXC1 = 1005, Mips_LWXC1_MM = 1006, Mips_LWXS_MM = 1007, Mips_LW_MM = 1008, Mips_LWu = 1009, Mips_LbRxRyOffMemX16 = 1010, Mips_LbuRxRyOffMemX16 = 1011, Mips_LhRxRyOffMemX16 = 1012, Mips_LhuRxRyOffMemX16 = 1013, Mips_LiRxImm16 = 1014, Mips_LiRxImmAlignX16 = 1015, Mips_LiRxImmX16 = 1016, Mips_LoadAddr32Imm = 1017, Mips_LoadAddr32Reg = 1018, Mips_LoadImm32Reg = 1019, Mips_LoadImm64Reg = 1020, Mips_LwConstant32 = 1021, Mips_LwRxPcTcp16 = 1022, Mips_LwRxPcTcpX16 = 1023, Mips_LwRxRyOffMemX16 = 1024, Mips_LwRxSpImmX16 = 1025, Mips_MADD = 1026, Mips_MADDF_D = 1027, Mips_MADDF_S = 1028, Mips_MADDR_Q_H = 1029, Mips_MADDR_Q_W = 1030, Mips_MADDU = 1031, Mips_MADDU_DSP = 1032, Mips_MADDU_MM = 1033, Mips_MADDV_B = 1034, Mips_MADDV_D = 1035, Mips_MADDV_H = 1036, Mips_MADDV_W = 1037, Mips_MADD_D32 = 1038, Mips_MADD_D32_MM = 1039, Mips_MADD_D64 = 1040, Mips_MADD_DSP = 1041, Mips_MADD_MM = 1042, Mips_MADD_Q_H = 1043, Mips_MADD_Q_W = 1044, Mips_MADD_S = 1045, Mips_MADD_S_MM = 1046, Mips_MAQ_SA_W_PHL = 1047, Mips_MAQ_SA_W_PHR = 1048, Mips_MAQ_S_W_PHL = 1049, Mips_MAQ_S_W_PHR = 1050, Mips_MAXA_D = 1051, Mips_MAXA_S = 1052, Mips_MAXI_S_B = 1053, Mips_MAXI_S_D = 1054, Mips_MAXI_S_H = 1055, Mips_MAXI_S_W = 1056, Mips_MAXI_U_B = 1057, Mips_MAXI_U_D = 1058, Mips_MAXI_U_H = 1059, Mips_MAXI_U_W = 1060, Mips_MAX_A_B = 1061, Mips_MAX_A_D = 1062, Mips_MAX_A_H = 1063, Mips_MAX_A_W = 1064, Mips_MAX_D = 1065, Mips_MAX_S = 1066, Mips_MAX_S_B = 1067, Mips_MAX_S_D = 1068, Mips_MAX_S_H = 1069, Mips_MAX_S_W = 1070, Mips_MAX_U_B = 1071, Mips_MAX_U_D = 1072, Mips_MAX_U_H = 1073, Mips_MAX_U_W = 1074, Mips_MFC0 = 1075, Mips_MFC1 = 1076, Mips_MFC1_MM = 1077, Mips_MFC2 = 1078, Mips_MFHC1_D32 = 1079, Mips_MFHC1_D64 = 1080, Mips_MFHC1_MM = 1081, Mips_MFHI = 1082, Mips_MFHI16_MM = 1083, Mips_MFHI64 = 1084, Mips_MFHI_DSP = 1085, Mips_MFHI_MM = 1086, Mips_MFLO = 1087, Mips_MFLO16_MM = 1088, Mips_MFLO64 = 1089, Mips_MFLO_DSP = 1090, Mips_MFLO_MM = 1091, Mips_MINA_D = 1092, Mips_MINA_S = 1093, Mips_MINI_S_B = 1094, Mips_MINI_S_D = 1095, Mips_MINI_S_H = 1096, Mips_MINI_S_W = 1097, Mips_MINI_U_B = 1098, Mips_MINI_U_D = 1099, Mips_MINI_U_H = 1100, Mips_MINI_U_W = 1101, Mips_MIN_A_B = 1102, Mips_MIN_A_D = 1103, Mips_MIN_A_H = 1104, Mips_MIN_A_W = 1105, Mips_MIN_D = 1106, Mips_MIN_S = 1107, Mips_MIN_S_B = 1108, Mips_MIN_S_D = 1109, Mips_MIN_S_H = 1110, Mips_MIN_S_W = 1111, Mips_MIN_U_B = 1112, Mips_MIN_U_D = 1113, Mips_MIN_U_H = 1114, Mips_MIN_U_W = 1115, Mips_MIPSeh_return32 = 1116, Mips_MIPSeh_return64 = 1117, Mips_MOD = 1118, Mips_MODSUB = 1119, Mips_MODU = 1120, Mips_MOD_S_B = 1121, Mips_MOD_S_D = 1122, Mips_MOD_S_H = 1123, Mips_MOD_S_W = 1124, Mips_MOD_U_B = 1125, Mips_MOD_U_D = 1126, Mips_MOD_U_H = 1127, Mips_MOD_U_W = 1128, Mips_MOVE16_MM = 1129, Mips_MOVEP_MM = 1130, Mips_MOVE_V = 1131, Mips_MOVF_D32 = 1132, Mips_MOVF_D32_MM = 1133, Mips_MOVF_D64 = 1134, Mips_MOVF_I = 1135, Mips_MOVF_I64 = 1136, Mips_MOVF_I_MM = 1137, Mips_MOVF_S = 1138, Mips_MOVF_S_MM = 1139, Mips_MOVN_I64_D64 = 1140, Mips_MOVN_I64_I = 1141, Mips_MOVN_I64_I64 = 1142, Mips_MOVN_I64_S = 1143, Mips_MOVN_I_D32 = 1144, Mips_MOVN_I_D32_MM = 1145, Mips_MOVN_I_D64 = 1146, Mips_MOVN_I_I = 1147, Mips_MOVN_I_I64 = 1148, Mips_MOVN_I_MM = 1149, Mips_MOVN_I_S = 1150, Mips_MOVN_I_S_MM = 1151, Mips_MOVT_D32 = 1152, Mips_MOVT_D32_MM = 1153, Mips_MOVT_D64 = 1154, Mips_MOVT_I = 1155, Mips_MOVT_I64 = 1156, Mips_MOVT_I_MM = 1157, Mips_MOVT_S = 1158, Mips_MOVT_S_MM = 1159, Mips_MOVZ_I64_D64 = 1160, Mips_MOVZ_I64_I = 1161, Mips_MOVZ_I64_I64 = 1162, Mips_MOVZ_I64_S = 1163, Mips_MOVZ_I_D32 = 1164, Mips_MOVZ_I_D32_MM = 1165, Mips_MOVZ_I_D64 = 1166, Mips_MOVZ_I_I = 1167, Mips_MOVZ_I_I64 = 1168, Mips_MOVZ_I_MM = 1169, Mips_MOVZ_I_S = 1170, Mips_MOVZ_I_S_MM = 1171, Mips_MSUB = 1172, Mips_MSUBF_D = 1173, Mips_MSUBF_S = 1174, Mips_MSUBR_Q_H = 1175, Mips_MSUBR_Q_W = 1176, Mips_MSUBU = 1177, Mips_MSUBU_DSP = 1178, Mips_MSUBU_MM = 1179, Mips_MSUBV_B = 1180, Mips_MSUBV_D = 1181, Mips_MSUBV_H = 1182, Mips_MSUBV_W = 1183, Mips_MSUB_D32 = 1184, Mips_MSUB_D32_MM = 1185, Mips_MSUB_D64 = 1186, Mips_MSUB_DSP = 1187, Mips_MSUB_MM = 1188, Mips_MSUB_Q_H = 1189, Mips_MSUB_Q_W = 1190, Mips_MSUB_S = 1191, Mips_MSUB_S_MM = 1192, Mips_MTC0 = 1193, Mips_MTC1 = 1194, Mips_MTC1_MM = 1195, Mips_MTC2 = 1196, Mips_MTHC1_D32 = 1197, Mips_MTHC1_D64 = 1198, Mips_MTHC1_MM = 1199, Mips_MTHI = 1200, Mips_MTHI64 = 1201, Mips_MTHI_DSP = 1202, Mips_MTHI_MM = 1203, Mips_MTHLIP = 1204, Mips_MTLO = 1205, Mips_MTLO64 = 1206, Mips_MTLO_DSP = 1207, Mips_MTLO_MM = 1208, Mips_MTM0 = 1209, Mips_MTM1 = 1210, Mips_MTM2 = 1211, Mips_MTP0 = 1212, Mips_MTP1 = 1213, Mips_MTP2 = 1214, Mips_MUH = 1215, Mips_MUHU = 1216, Mips_MUL = 1217, Mips_MULEQ_S_W_PHL = 1218, Mips_MULEQ_S_W_PHR = 1219, Mips_MULEU_S_PH_QBL = 1220, Mips_MULEU_S_PH_QBR = 1221, Mips_MULQ_RS_PH = 1222, Mips_MULQ_RS_W = 1223, Mips_MULQ_S_PH = 1224, Mips_MULQ_S_W = 1225, Mips_MULR_Q_H = 1226, Mips_MULR_Q_W = 1227, Mips_MULSAQ_S_W_PH = 1228, Mips_MULSA_W_PH = 1229, Mips_MULT = 1230, Mips_MULTU_DSP = 1231, Mips_MULT_DSP = 1232, Mips_MULT_MM = 1233, Mips_MULTu = 1234, Mips_MULTu_MM = 1235, Mips_MULU = 1236, Mips_MULV_B = 1237, Mips_MULV_D = 1238, Mips_MULV_H = 1239, Mips_MULV_W = 1240, Mips_MUL_MM = 1241, Mips_MUL_PH = 1242, Mips_MUL_Q_H = 1243, Mips_MUL_Q_W = 1244, Mips_MUL_R6 = 1245, Mips_MUL_S_PH = 1246, Mips_Mfhi16 = 1247, Mips_Mflo16 = 1248, Mips_Move32R16 = 1249, Mips_MoveR3216 = 1250, Mips_MultRxRy16 = 1251, Mips_MultRxRyRz16 = 1252, Mips_MultuRxRy16 = 1253, Mips_MultuRxRyRz16 = 1254, Mips_NLOC_B = 1255, Mips_NLOC_D = 1256, Mips_NLOC_H = 1257, Mips_NLOC_W = 1258, Mips_NLZC_B = 1259, Mips_NLZC_D = 1260, Mips_NLZC_H = 1261, Mips_NLZC_W = 1262, Mips_NMADD_D32 = 1263, Mips_NMADD_D32_MM = 1264, Mips_NMADD_D64 = 1265, Mips_NMADD_S = 1266, Mips_NMADD_S_MM = 1267, Mips_NMSUB_D32 = 1268, Mips_NMSUB_D32_MM = 1269, Mips_NMSUB_D64 = 1270, Mips_NMSUB_S = 1271, Mips_NMSUB_S_MM = 1272, Mips_NOP = 1273, Mips_NOR = 1274, Mips_NOR64 = 1275, Mips_NORI_B = 1276, Mips_NOR_MM = 1277, Mips_NOR_V = 1278, Mips_NOR_V_D_PSEUDO = 1279, Mips_NOR_V_H_PSEUDO = 1280, Mips_NOR_V_W_PSEUDO = 1281, Mips_NOT16_MM = 1282, Mips_NegRxRy16 = 1283, Mips_NotRxRy16 = 1284, Mips_OR = 1285, Mips_OR16_MM = 1286, Mips_OR64 = 1287, Mips_ORI_B = 1288, Mips_OR_MM = 1289, Mips_OR_V = 1290, Mips_OR_V_D_PSEUDO = 1291, Mips_OR_V_H_PSEUDO = 1292, Mips_OR_V_W_PSEUDO = 1293, Mips_ORi = 1294, Mips_ORi64 = 1295, Mips_ORi_MM = 1296, Mips_OrRxRxRy16 = 1297, Mips_PACKRL_PH = 1298, Mips_PAUSE = 1299, Mips_PAUSE_MM = 1300, Mips_PCKEV_B = 1301, Mips_PCKEV_D = 1302, Mips_PCKEV_H = 1303, Mips_PCKEV_W = 1304, Mips_PCKOD_B = 1305, Mips_PCKOD_D = 1306, Mips_PCKOD_H = 1307, Mips_PCKOD_W = 1308, Mips_PCNT_B = 1309, Mips_PCNT_D = 1310, Mips_PCNT_H = 1311, Mips_PCNT_W = 1312, Mips_PICK_PH = 1313, Mips_PICK_QB = 1314, Mips_POP = 1315, Mips_PRECEQU_PH_QBL = 1316, Mips_PRECEQU_PH_QBLA = 1317, Mips_PRECEQU_PH_QBR = 1318, Mips_PRECEQU_PH_QBRA = 1319, Mips_PRECEQ_W_PHL = 1320, Mips_PRECEQ_W_PHR = 1321, Mips_PRECEU_PH_QBL = 1322, Mips_PRECEU_PH_QBLA = 1323, Mips_PRECEU_PH_QBR = 1324, Mips_PRECEU_PH_QBRA = 1325, Mips_PRECRQU_S_QB_PH = 1326, Mips_PRECRQ_PH_W = 1327, Mips_PRECRQ_QB_PH = 1328, Mips_PRECRQ_RS_PH_W = 1329, Mips_PRECR_QB_PH = 1330, Mips_PRECR_SRA_PH_W = 1331, Mips_PRECR_SRA_R_PH_W = 1332, Mips_PREF = 1333, Mips_PREF_MM = 1334, Mips_PREF_R6 = 1335, Mips_PREPEND = 1336, Mips_PseudoCMPU_EQ_QB = 1337, Mips_PseudoCMPU_LE_QB = 1338, Mips_PseudoCMPU_LT_QB = 1339, Mips_PseudoCMP_EQ_PH = 1340, Mips_PseudoCMP_LE_PH = 1341, Mips_PseudoCMP_LT_PH = 1342, Mips_PseudoCVT_D32_W = 1343, Mips_PseudoCVT_D64_L = 1344, Mips_PseudoCVT_D64_W = 1345, Mips_PseudoCVT_S_L = 1346, Mips_PseudoCVT_S_W = 1347, Mips_PseudoDMULT = 1348, Mips_PseudoDMULTu = 1349, Mips_PseudoDSDIV = 1350, Mips_PseudoDUDIV = 1351, Mips_PseudoIndirectBranch = 1352, Mips_PseudoIndirectBranch64 = 1353, Mips_PseudoMADD = 1354, Mips_PseudoMADDU = 1355, Mips_PseudoMFHI = 1356, Mips_PseudoMFHI64 = 1357, Mips_PseudoMFLO = 1358, Mips_PseudoMFLO64 = 1359, Mips_PseudoMSUB = 1360, Mips_PseudoMSUBU = 1361, Mips_PseudoMTLOHI = 1362, Mips_PseudoMTLOHI64 = 1363, Mips_PseudoMTLOHI_DSP = 1364, Mips_PseudoMULT = 1365, Mips_PseudoMULTu = 1366, Mips_PseudoPICK_PH = 1367, Mips_PseudoPICK_QB = 1368, Mips_PseudoReturn = 1369, Mips_PseudoReturn64 = 1370, Mips_PseudoSDIV = 1371, Mips_PseudoSELECTFP_F_D32 = 1372, Mips_PseudoSELECTFP_F_D64 = 1373, Mips_PseudoSELECTFP_F_I = 1374, Mips_PseudoSELECTFP_F_I64 = 1375, Mips_PseudoSELECTFP_F_S = 1376, Mips_PseudoSELECTFP_T_D32 = 1377, Mips_PseudoSELECTFP_T_D64 = 1378, Mips_PseudoSELECTFP_T_I = 1379, Mips_PseudoSELECTFP_T_I64 = 1380, Mips_PseudoSELECTFP_T_S = 1381, Mips_PseudoSELECT_D32 = 1382, Mips_PseudoSELECT_D64 = 1383, Mips_PseudoSELECT_I = 1384, Mips_PseudoSELECT_I64 = 1385, Mips_PseudoSELECT_S = 1386, Mips_PseudoUDIV = 1387, Mips_RADDU_W_QB = 1388, Mips_RDDSP = 1389, Mips_RDHWR = 1390, Mips_RDHWR64 = 1391, Mips_RDHWR_MM = 1392, Mips_REPLV_PH = 1393, Mips_REPLV_QB = 1394, Mips_REPL_PH = 1395, Mips_REPL_QB = 1396, Mips_RINT_D = 1397, Mips_RINT_S = 1398, Mips_ROTR = 1399, Mips_ROTRV = 1400, Mips_ROTRV_MM = 1401, Mips_ROTR_MM = 1402, Mips_ROUND_L_D64 = 1403, Mips_ROUND_L_S = 1404, Mips_ROUND_W_D32 = 1405, Mips_ROUND_W_D64 = 1406, Mips_ROUND_W_MM = 1407, Mips_ROUND_W_S = 1408, Mips_ROUND_W_S_MM = 1409, Mips_Restore16 = 1410, Mips_RestoreX16 = 1411, Mips_RetRA = 1412, Mips_RetRA16 = 1413, Mips_SAT_S_B = 1414, Mips_SAT_S_D = 1415, Mips_SAT_S_H = 1416, Mips_SAT_S_W = 1417, Mips_SAT_U_B = 1418, Mips_SAT_U_D = 1419, Mips_SAT_U_H = 1420, Mips_SAT_U_W = 1421, Mips_SB = 1422, Mips_SB16_MM = 1423, Mips_SB64 = 1424, Mips_SB_MM = 1425, Mips_SC = 1426, Mips_SCD = 1427, Mips_SCD_R6 = 1428, Mips_SC_MM = 1429, Mips_SC_R6 = 1430, Mips_SD = 1431, Mips_SDBBP = 1432, Mips_SDBBP16_MM = 1433, Mips_SDBBP_MM = 1434, Mips_SDBBP_R6 = 1435, Mips_SDC1 = 1436, Mips_SDC164 = 1437, Mips_SDC1_MM = 1438, Mips_SDC2 = 1439, Mips_SDC2_R6 = 1440, Mips_SDC3 = 1441, Mips_SDIV = 1442, Mips_SDIV_MM = 1443, Mips_SDL = 1444, Mips_SDR = 1445, Mips_SDXC1 = 1446, Mips_SDXC164 = 1447, Mips_SEB = 1448, Mips_SEB64 = 1449, Mips_SEB_MM = 1450, Mips_SEH = 1451, Mips_SEH64 = 1452, Mips_SEH_MM = 1453, Mips_SELEQZ = 1454, Mips_SELEQZ64 = 1455, Mips_SELEQZ_D = 1456, Mips_SELEQZ_S = 1457, Mips_SELNEZ = 1458, Mips_SELNEZ64 = 1459, Mips_SELNEZ_D = 1460, Mips_SELNEZ_S = 1461, Mips_SEL_D = 1462, Mips_SEL_S = 1463, Mips_SEQ = 1464, Mips_SEQi = 1465, Mips_SH = 1466, Mips_SH16_MM = 1467, Mips_SH64 = 1468, Mips_SHF_B = 1469, Mips_SHF_H = 1470, Mips_SHF_W = 1471, Mips_SHILO = 1472, Mips_SHILOV = 1473, Mips_SHLLV_PH = 1474, Mips_SHLLV_QB = 1475, Mips_SHLLV_S_PH = 1476, Mips_SHLLV_S_W = 1477, Mips_SHLL_PH = 1478, Mips_SHLL_QB = 1479, Mips_SHLL_S_PH = 1480, Mips_SHLL_S_W = 1481, Mips_SHRAV_PH = 1482, Mips_SHRAV_QB = 1483, Mips_SHRAV_R_PH = 1484, Mips_SHRAV_R_QB = 1485, Mips_SHRAV_R_W = 1486, Mips_SHRA_PH = 1487, Mips_SHRA_QB = 1488, Mips_SHRA_R_PH = 1489, Mips_SHRA_R_QB = 1490, Mips_SHRA_R_W = 1491, Mips_SHRLV_PH = 1492, Mips_SHRLV_QB = 1493, Mips_SHRL_PH = 1494, Mips_SHRL_QB = 1495, Mips_SH_MM = 1496, Mips_SLDI_B = 1497, Mips_SLDI_D = 1498, Mips_SLDI_H = 1499, Mips_SLDI_W = 1500, Mips_SLD_B = 1501, Mips_SLD_D = 1502, Mips_SLD_H = 1503, Mips_SLD_W = 1504, Mips_SLL = 1505, Mips_SLL16_MM = 1506, Mips_SLL64_32 = 1507, Mips_SLL64_64 = 1508, Mips_SLLI_B = 1509, Mips_SLLI_D = 1510, Mips_SLLI_H = 1511, Mips_SLLI_W = 1512, Mips_SLLV = 1513, Mips_SLLV_MM = 1514, Mips_SLL_B = 1515, Mips_SLL_D = 1516, Mips_SLL_H = 1517, Mips_SLL_MM = 1518, Mips_SLL_W = 1519, Mips_SLT = 1520, Mips_SLT64 = 1521, Mips_SLT_MM = 1522, Mips_SLTi = 1523, Mips_SLTi64 = 1524, Mips_SLTi_MM = 1525, Mips_SLTiu = 1526, Mips_SLTiu64 = 1527, Mips_SLTiu_MM = 1528, Mips_SLTu = 1529, Mips_SLTu64 = 1530, Mips_SLTu_MM = 1531, Mips_SNE = 1532, Mips_SNEi = 1533, Mips_SNZ_B_PSEUDO = 1534, Mips_SNZ_D_PSEUDO = 1535, Mips_SNZ_H_PSEUDO = 1536, Mips_SNZ_V_PSEUDO = 1537, Mips_SNZ_W_PSEUDO = 1538, Mips_SPLATI_B = 1539, Mips_SPLATI_D = 1540, Mips_SPLATI_H = 1541, Mips_SPLATI_W = 1542, Mips_SPLAT_B = 1543, Mips_SPLAT_D = 1544, Mips_SPLAT_H = 1545, Mips_SPLAT_W = 1546, Mips_SRA = 1547, Mips_SRAI_B = 1548, Mips_SRAI_D = 1549, Mips_SRAI_H = 1550, Mips_SRAI_W = 1551, Mips_SRARI_B = 1552, Mips_SRARI_D = 1553, Mips_SRARI_H = 1554, Mips_SRARI_W = 1555, Mips_SRAR_B = 1556, Mips_SRAR_D = 1557, Mips_SRAR_H = 1558, Mips_SRAR_W = 1559, Mips_SRAV = 1560, Mips_SRAV_MM = 1561, Mips_SRA_B = 1562, Mips_SRA_D = 1563, Mips_SRA_H = 1564, Mips_SRA_MM = 1565, Mips_SRA_W = 1566, Mips_SRL = 1567, Mips_SRL16_MM = 1568, Mips_SRLI_B = 1569, Mips_SRLI_D = 1570, Mips_SRLI_H = 1571, Mips_SRLI_W = 1572, Mips_SRLRI_B = 1573, Mips_SRLRI_D = 1574, Mips_SRLRI_H = 1575, Mips_SRLRI_W = 1576, Mips_SRLR_B = 1577, Mips_SRLR_D = 1578, Mips_SRLR_H = 1579, Mips_SRLR_W = 1580, Mips_SRLV = 1581, Mips_SRLV_MM = 1582, Mips_SRL_B = 1583, Mips_SRL_D = 1584, Mips_SRL_H = 1585, Mips_SRL_MM = 1586, Mips_SRL_W = 1587, Mips_SSNOP = 1588, Mips_SSNOP_MM = 1589, Mips_STORE_ACC128 = 1590, Mips_STORE_ACC64 = 1591, Mips_STORE_ACC64DSP = 1592, Mips_STORE_CCOND_DSP = 1593, Mips_ST_B = 1594, Mips_ST_D = 1595, Mips_ST_H = 1596, Mips_ST_W = 1597, Mips_SUB = 1598, Mips_SUBQH_PH = 1599, Mips_SUBQH_R_PH = 1600, Mips_SUBQH_R_W = 1601, Mips_SUBQH_W = 1602, Mips_SUBQ_PH = 1603, Mips_SUBQ_S_PH = 1604, Mips_SUBQ_S_W = 1605, Mips_SUBSUS_U_B = 1606, Mips_SUBSUS_U_D = 1607, Mips_SUBSUS_U_H = 1608, Mips_SUBSUS_U_W = 1609, Mips_SUBSUU_S_B = 1610, Mips_SUBSUU_S_D = 1611, Mips_SUBSUU_S_H = 1612, Mips_SUBSUU_S_W = 1613, Mips_SUBS_S_B = 1614, Mips_SUBS_S_D = 1615, Mips_SUBS_S_H = 1616, Mips_SUBS_S_W = 1617, Mips_SUBS_U_B = 1618, Mips_SUBS_U_D = 1619, Mips_SUBS_U_H = 1620, Mips_SUBS_U_W = 1621, Mips_SUBU16_MM = 1622, Mips_SUBUH_QB = 1623, Mips_SUBUH_R_QB = 1624, Mips_SUBU_PH = 1625, Mips_SUBU_QB = 1626, Mips_SUBU_S_PH = 1627, Mips_SUBU_S_QB = 1628, Mips_SUBVI_B = 1629, Mips_SUBVI_D = 1630, Mips_SUBVI_H = 1631, Mips_SUBVI_W = 1632, Mips_SUBV_B = 1633, Mips_SUBV_D = 1634, Mips_SUBV_H = 1635, Mips_SUBV_W = 1636, Mips_SUB_MM = 1637, Mips_SUBu = 1638, Mips_SUBu_MM = 1639, Mips_SUXC1 = 1640, Mips_SUXC164 = 1641, Mips_SUXC1_MM = 1642, Mips_SW = 1643, Mips_SW16_MM = 1644, Mips_SW64 = 1645, Mips_SWC1 = 1646, Mips_SWC1_MM = 1647, Mips_SWC2 = 1648, Mips_SWC2_R6 = 1649, Mips_SWC3 = 1650, Mips_SWL = 1651, Mips_SWL64 = 1652, Mips_SWL_MM = 1653, Mips_SWM16_MM = 1654, Mips_SWM32_MM = 1655, Mips_SWM_MM = 1656, Mips_SWP_MM = 1657, Mips_SWR = 1658, Mips_SWR64 = 1659, Mips_SWR_MM = 1660, Mips_SWSP_MM = 1661, Mips_SWXC1 = 1662, Mips_SWXC1_MM = 1663, Mips_SW_MM = 1664, Mips_SYNC = 1665, Mips_SYNCI = 1666, Mips_SYNC_MM = 1667, Mips_SYSCALL = 1668, Mips_SYSCALL_MM = 1669, Mips_SZ_B_PSEUDO = 1670, Mips_SZ_D_PSEUDO = 1671, Mips_SZ_H_PSEUDO = 1672, Mips_SZ_V_PSEUDO = 1673, Mips_SZ_W_PSEUDO = 1674, Mips_Save16 = 1675, Mips_SaveX16 = 1676, Mips_SbRxRyOffMemX16 = 1677, Mips_SebRx16 = 1678, Mips_SehRx16 = 1679, Mips_SelBeqZ = 1680, Mips_SelBneZ = 1681, Mips_SelTBteqZCmp = 1682, Mips_SelTBteqZCmpi = 1683, Mips_SelTBteqZSlt = 1684, Mips_SelTBteqZSlti = 1685, Mips_SelTBteqZSltiu = 1686, Mips_SelTBteqZSltu = 1687, Mips_SelTBtneZCmp = 1688, Mips_SelTBtneZCmpi = 1689, Mips_SelTBtneZSlt = 1690, Mips_SelTBtneZSlti = 1691, Mips_SelTBtneZSltiu = 1692, Mips_SelTBtneZSltu = 1693, Mips_ShRxRyOffMemX16 = 1694, Mips_SllX16 = 1695, Mips_SllvRxRy16 = 1696, Mips_SltCCRxRy16 = 1697, Mips_SltRxRy16 = 1698, Mips_SltiCCRxImmX16 = 1699, Mips_SltiRxImm16 = 1700, Mips_SltiRxImmX16 = 1701, Mips_SltiuCCRxImmX16 = 1702, Mips_SltiuRxImm16 = 1703, Mips_SltiuRxImmX16 = 1704, Mips_SltuCCRxRy16 = 1705, Mips_SltuRxRy16 = 1706, Mips_SltuRxRyRz16 = 1707, Mips_SraX16 = 1708, Mips_SravRxRy16 = 1709, Mips_SrlX16 = 1710, Mips_SrlvRxRy16 = 1711, Mips_SubuRxRyRz16 = 1712, Mips_SwRxRyOffMemX16 = 1713, Mips_SwRxSpImmX16 = 1714, Mips_TAILCALL = 1715, Mips_TAILCALL64_R = 1716, Mips_TAILCALL_R = 1717, Mips_TEQ = 1718, Mips_TEQI = 1719, Mips_TEQI_MM = 1720, Mips_TEQ_MM = 1721, Mips_TGE = 1722, Mips_TGEI = 1723, Mips_TGEIU = 1724, Mips_TGEIU_MM = 1725, Mips_TGEI_MM = 1726, Mips_TGEU = 1727, Mips_TGEU_MM = 1728, Mips_TGE_MM = 1729, Mips_TLBP = 1730, Mips_TLBP_MM = 1731, Mips_TLBR = 1732, Mips_TLBR_MM = 1733, Mips_TLBWI = 1734, Mips_TLBWI_MM = 1735, Mips_TLBWR = 1736, Mips_TLBWR_MM = 1737, Mips_TLT = 1738, Mips_TLTI = 1739, Mips_TLTIU_MM = 1740, Mips_TLTI_MM = 1741, Mips_TLTU = 1742, Mips_TLTU_MM = 1743, Mips_TLT_MM = 1744, Mips_TNE = 1745, Mips_TNEI = 1746, Mips_TNEI_MM = 1747, Mips_TNE_MM = 1748, Mips_TRAP = 1749, Mips_TRUNC_L_D64 = 1750, Mips_TRUNC_L_S = 1751, Mips_TRUNC_W_D32 = 1752, Mips_TRUNC_W_D64 = 1753, Mips_TRUNC_W_MM = 1754, Mips_TRUNC_W_S = 1755, Mips_TRUNC_W_S_MM = 1756, Mips_TTLTIU = 1757, Mips_UDIV = 1758, Mips_UDIV_MM = 1759, Mips_V3MULU = 1760, Mips_VMM0 = 1761, Mips_VMULU = 1762, Mips_VSHF_B = 1763, Mips_VSHF_D = 1764, Mips_VSHF_H = 1765, Mips_VSHF_W = 1766, Mips_WAIT = 1767, Mips_WAIT_MM = 1768, Mips_WRDSP = 1769, Mips_WSBH = 1770, Mips_WSBH_MM = 1771, Mips_XOR = 1772, Mips_XOR16_MM = 1773, Mips_XOR64 = 1774, Mips_XORI_B = 1775, Mips_XOR_MM = 1776, Mips_XOR_V = 1777, Mips_XOR_V_D_PSEUDO = 1778, Mips_XOR_V_H_PSEUDO = 1779, Mips_XOR_V_W_PSEUDO = 1780, Mips_XORi = 1781, Mips_XORi64 = 1782, Mips_XORi_MM = 1783, Mips_XorRxRxRy16 = 1784, Mips_INSTRUCTION_LIST_END = 1785 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/Mips/MipsGenRegisterInfo.inc000064400000000000000000001747030072674642500224220ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { Mips_NoRegister, Mips_AT = 1, Mips_DSPCCond = 2, Mips_DSPCarry = 3, Mips_DSPEFI = 4, Mips_DSPOutFlag = 5, Mips_DSPPos = 6, Mips_DSPSCount = 7, Mips_FP = 8, Mips_GP = 9, Mips_MSAAccess = 10, Mips_MSACSR = 11, Mips_MSAIR = 12, Mips_MSAMap = 13, Mips_MSAModify = 14, Mips_MSARequest = 15, Mips_MSASave = 16, Mips_MSAUnmap = 17, Mips_PC = 18, Mips_RA = 19, Mips_SP = 20, Mips_ZERO = 21, Mips_A0 = 22, Mips_A1 = 23, Mips_A2 = 24, Mips_A3 = 25, Mips_AC0 = 26, Mips_AC1 = 27, Mips_AC2 = 28, Mips_AC3 = 29, Mips_AT_64 = 30, Mips_CC0 = 31, Mips_CC1 = 32, Mips_CC2 = 33, Mips_CC3 = 34, Mips_CC4 = 35, Mips_CC5 = 36, Mips_CC6 = 37, Mips_CC7 = 38, Mips_COP20 = 39, Mips_COP21 = 40, Mips_COP22 = 41, Mips_COP23 = 42, Mips_COP24 = 43, Mips_COP25 = 44, Mips_COP26 = 45, Mips_COP27 = 46, Mips_COP28 = 47, Mips_COP29 = 48, Mips_COP30 = 49, Mips_COP31 = 50, Mips_COP32 = 51, Mips_COP33 = 52, Mips_COP34 = 53, Mips_COP35 = 54, Mips_COP36 = 55, Mips_COP37 = 56, Mips_COP38 = 57, Mips_COP39 = 58, Mips_COP210 = 59, Mips_COP211 = 60, Mips_COP212 = 61, Mips_COP213 = 62, Mips_COP214 = 63, Mips_COP215 = 64, Mips_COP216 = 65, Mips_COP217 = 66, Mips_COP218 = 67, Mips_COP219 = 68, Mips_COP220 = 69, Mips_COP221 = 70, Mips_COP222 = 71, Mips_COP223 = 72, Mips_COP224 = 73, Mips_COP225 = 74, Mips_COP226 = 75, Mips_COP227 = 76, Mips_COP228 = 77, Mips_COP229 = 78, Mips_COP230 = 79, Mips_COP231 = 80, Mips_COP310 = 81, Mips_COP311 = 82, Mips_COP312 = 83, Mips_COP313 = 84, Mips_COP314 = 85, Mips_COP315 = 86, Mips_COP316 = 87, Mips_COP317 = 88, Mips_COP318 = 89, Mips_COP319 = 90, Mips_COP320 = 91, Mips_COP321 = 92, Mips_COP322 = 93, Mips_COP323 = 94, Mips_COP324 = 95, Mips_COP325 = 96, Mips_COP326 = 97, Mips_COP327 = 98, Mips_COP328 = 99, Mips_COP329 = 100, Mips_COP330 = 101, Mips_COP331 = 102, Mips_D0 = 103, Mips_D1 = 104, Mips_D2 = 105, Mips_D3 = 106, Mips_D4 = 107, Mips_D5 = 108, Mips_D6 = 109, Mips_D7 = 110, Mips_D8 = 111, Mips_D9 = 112, Mips_D10 = 113, Mips_D11 = 114, Mips_D12 = 115, Mips_D13 = 116, Mips_D14 = 117, Mips_D15 = 118, Mips_DSPOutFlag20 = 119, Mips_DSPOutFlag21 = 120, Mips_DSPOutFlag22 = 121, Mips_DSPOutFlag23 = 122, Mips_F0 = 123, Mips_F1 = 124, Mips_F2 = 125, Mips_F3 = 126, Mips_F4 = 127, Mips_F5 = 128, Mips_F6 = 129, Mips_F7 = 130, Mips_F8 = 131, Mips_F9 = 132, Mips_F10 = 133, Mips_F11 = 134, Mips_F12 = 135, Mips_F13 = 136, Mips_F14 = 137, Mips_F15 = 138, Mips_F16 = 139, Mips_F17 = 140, Mips_F18 = 141, Mips_F19 = 142, Mips_F20 = 143, Mips_F21 = 144, Mips_F22 = 145, Mips_F23 = 146, Mips_F24 = 147, Mips_F25 = 148, Mips_F26 = 149, Mips_F27 = 150, Mips_F28 = 151, Mips_F29 = 152, Mips_F30 = 153, Mips_F31 = 154, Mips_FCC0 = 155, Mips_FCC1 = 156, Mips_FCC2 = 157, Mips_FCC3 = 158, Mips_FCC4 = 159, Mips_FCC5 = 160, Mips_FCC6 = 161, Mips_FCC7 = 162, Mips_FCR0 = 163, Mips_FCR1 = 164, Mips_FCR2 = 165, Mips_FCR3 = 166, Mips_FCR4 = 167, Mips_FCR5 = 168, Mips_FCR6 = 169, Mips_FCR7 = 170, Mips_FCR8 = 171, Mips_FCR9 = 172, Mips_FCR10 = 173, Mips_FCR11 = 174, Mips_FCR12 = 175, Mips_FCR13 = 176, Mips_FCR14 = 177, Mips_FCR15 = 178, Mips_FCR16 = 179, Mips_FCR17 = 180, Mips_FCR18 = 181, Mips_FCR19 = 182, Mips_FCR20 = 183, Mips_FCR21 = 184, Mips_FCR22 = 185, Mips_FCR23 = 186, Mips_FCR24 = 187, Mips_FCR25 = 188, Mips_FCR26 = 189, Mips_FCR27 = 190, Mips_FCR28 = 191, Mips_FCR29 = 192, Mips_FCR30 = 193, Mips_FCR31 = 194, Mips_FP_64 = 195, Mips_F_HI0 = 196, Mips_F_HI1 = 197, Mips_F_HI2 = 198, Mips_F_HI3 = 199, Mips_F_HI4 = 200, Mips_F_HI5 = 201, Mips_F_HI6 = 202, Mips_F_HI7 = 203, Mips_F_HI8 = 204, Mips_F_HI9 = 205, Mips_F_HI10 = 206, Mips_F_HI11 = 207, Mips_F_HI12 = 208, Mips_F_HI13 = 209, Mips_F_HI14 = 210, Mips_F_HI15 = 211, Mips_F_HI16 = 212, Mips_F_HI17 = 213, Mips_F_HI18 = 214, Mips_F_HI19 = 215, Mips_F_HI20 = 216, Mips_F_HI21 = 217, Mips_F_HI22 = 218, Mips_F_HI23 = 219, Mips_F_HI24 = 220, Mips_F_HI25 = 221, Mips_F_HI26 = 222, Mips_F_HI27 = 223, Mips_F_HI28 = 224, Mips_F_HI29 = 225, Mips_F_HI30 = 226, Mips_F_HI31 = 227, Mips_GP_64 = 228, Mips_HI0 = 229, Mips_HI1 = 230, Mips_HI2 = 231, Mips_HI3 = 232, Mips_HWR0 = 233, Mips_HWR1 = 234, Mips_HWR2 = 235, Mips_HWR3 = 236, Mips_HWR4 = 237, Mips_HWR5 = 238, Mips_HWR6 = 239, Mips_HWR7 = 240, Mips_HWR8 = 241, Mips_HWR9 = 242, Mips_HWR10 = 243, Mips_HWR11 = 244, Mips_HWR12 = 245, Mips_HWR13 = 246, Mips_HWR14 = 247, Mips_HWR15 = 248, Mips_HWR16 = 249, Mips_HWR17 = 250, Mips_HWR18 = 251, Mips_HWR19 = 252, Mips_HWR20 = 253, Mips_HWR21 = 254, Mips_HWR22 = 255, Mips_HWR23 = 256, Mips_HWR24 = 257, Mips_HWR25 = 258, Mips_HWR26 = 259, Mips_HWR27 = 260, Mips_HWR28 = 261, Mips_HWR29 = 262, Mips_HWR30 = 263, Mips_HWR31 = 264, Mips_K0 = 265, Mips_K1 = 266, Mips_LO0 = 267, Mips_LO1 = 268, Mips_LO2 = 269, Mips_LO3 = 270, Mips_MPL0 = 271, Mips_MPL1 = 272, Mips_MPL2 = 273, Mips_P0 = 274, Mips_P1 = 275, Mips_P2 = 276, Mips_RA_64 = 277, Mips_S0 = 278, Mips_S1 = 279, Mips_S2 = 280, Mips_S3 = 281, Mips_S4 = 282, Mips_S5 = 283, Mips_S6 = 284, Mips_S7 = 285, Mips_SP_64 = 286, Mips_T0 = 287, Mips_T1 = 288, Mips_T2 = 289, Mips_T3 = 290, Mips_T4 = 291, Mips_T5 = 292, Mips_T6 = 293, Mips_T7 = 294, Mips_T8 = 295, Mips_T9 = 296, Mips_V0 = 297, Mips_V1 = 298, Mips_W0 = 299, Mips_W1 = 300, Mips_W2 = 301, Mips_W3 = 302, Mips_W4 = 303, Mips_W5 = 304, Mips_W6 = 305, Mips_W7 = 306, Mips_W8 = 307, Mips_W9 = 308, Mips_W10 = 309, Mips_W11 = 310, Mips_W12 = 311, Mips_W13 = 312, Mips_W14 = 313, Mips_W15 = 314, Mips_W16 = 315, Mips_W17 = 316, Mips_W18 = 317, Mips_W19 = 318, Mips_W20 = 319, Mips_W21 = 320, Mips_W22 = 321, Mips_W23 = 322, Mips_W24 = 323, Mips_W25 = 324, Mips_W26 = 325, Mips_W27 = 326, Mips_W28 = 327, Mips_W29 = 328, Mips_W30 = 329, Mips_W31 = 330, Mips_ZERO_64 = 331, Mips_A0_64 = 332, Mips_A1_64 = 333, Mips_A2_64 = 334, Mips_A3_64 = 335, Mips_AC0_64 = 336, Mips_D0_64 = 337, Mips_D1_64 = 338, Mips_D2_64 = 339, Mips_D3_64 = 340, Mips_D4_64 = 341, Mips_D5_64 = 342, Mips_D6_64 = 343, Mips_D7_64 = 344, Mips_D8_64 = 345, Mips_D9_64 = 346, Mips_D10_64 = 347, Mips_D11_64 = 348, Mips_D12_64 = 349, Mips_D13_64 = 350, Mips_D14_64 = 351, Mips_D15_64 = 352, Mips_D16_64 = 353, Mips_D17_64 = 354, Mips_D18_64 = 355, Mips_D19_64 = 356, Mips_D20_64 = 357, Mips_D21_64 = 358, Mips_D22_64 = 359, Mips_D23_64 = 360, Mips_D24_64 = 361, Mips_D25_64 = 362, Mips_D26_64 = 363, Mips_D27_64 = 364, Mips_D28_64 = 365, Mips_D29_64 = 366, Mips_D30_64 = 367, Mips_D31_64 = 368, Mips_DSPOutFlag16_19 = 369, Mips_HI0_64 = 370, Mips_K0_64 = 371, Mips_K1_64 = 372, Mips_LO0_64 = 373, Mips_S0_64 = 374, Mips_S1_64 = 375, Mips_S2_64 = 376, Mips_S3_64 = 377, Mips_S4_64 = 378, Mips_S5_64 = 379, Mips_S6_64 = 380, Mips_S7_64 = 381, Mips_T0_64 = 382, Mips_T1_64 = 383, Mips_T2_64 = 384, Mips_T3_64 = 385, Mips_T4_64 = 386, Mips_T5_64 = 387, Mips_T6_64 = 388, Mips_T7_64 = 389, Mips_T8_64 = 390, Mips_T9_64 = 391, Mips_V0_64 = 392, Mips_V1_64 = 393, Mips_NUM_TARGET_REGS // 394 }; // Register classes enum { Mips_OddSPRegClassID = 0, Mips_CCRRegClassID = 1, Mips_COP2RegClassID = 2, Mips_COP3RegClassID = 3, Mips_DSPRRegClassID = 4, Mips_FGR32RegClassID = 5, Mips_FGRCCRegClassID = 6, Mips_FGRH32RegClassID = 7, Mips_GPR32RegClassID = 8, Mips_HWRegsRegClassID = 9, Mips_OddSP_with_sub_hiRegClassID = 10, Mips_FGR32_and_OddSPRegClassID = 11, Mips_FGRH32_and_OddSPRegClassID = 12, Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, Mips_CPU16RegsPlusSPRegClassID = 14, Mips_CCRegClassID = 15, Mips_CPU16RegsRegClassID = 16, Mips_FCCRegClassID = 17, Mips_GPRMM16RegClassID = 18, Mips_GPRMM16MovePRegClassID = 19, Mips_GPRMM16ZeroRegClassID = 20, Mips_MSACtrlRegClassID = 21, Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23, Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24, Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, Mips_HI32DSPRegClassID = 26, Mips_LO32DSPRegClassID = 27, Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, Mips_CPURARegRegClassID = 29, Mips_CPUSPRegRegClassID = 30, Mips_DSPCCRegClassID = 31, Mips_HI32RegClassID = 32, Mips_LO32RegClassID = 33, Mips_FGR64RegClassID = 34, Mips_GPR64RegClassID = 35, Mips_AFGR64RegClassID = 36, Mips_FGR64_and_OddSPRegClassID = 37, Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, Mips_AFGR64_and_OddSPRegClassID = 39, Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, Mips_ACC64DSPRegClassID = 44, Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, Mips_OCTEON_MPLRegClassID = 48, Mips_OCTEON_PRegClassID = 49, Mips_ACC64RegClassID = 50, Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51, Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, Mips_HI64RegClassID = 53, Mips_LO64RegClassID = 54, Mips_MSA128BRegClassID = 55, Mips_MSA128DRegClassID = 56, Mips_MSA128HRegClassID = 57, Mips_MSA128WRegClassID = 58, Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59, Mips_MSA128WEvensRegClassID = 60, Mips_ACC128RegClassID = 61, }; #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg MipsRegDiffLists[] = { /* 0 */ 0, 0, /* 2 */ 4, 1, 1, 1, 1, 0, /* 8 */ 364, 65286, 1, 1, 1, 0, /* 14 */ 20, 1, 0, /* 17 */ 21, 1, 0, /* 20 */ 22, 1, 0, /* 23 */ 23, 1, 0, /* 26 */ 24, 1, 0, /* 29 */ 25, 1, 0, /* 32 */ 26, 1, 0, /* 35 */ 27, 1, 0, /* 38 */ 28, 1, 0, /* 41 */ 29, 1, 0, /* 44 */ 30, 1, 0, /* 47 */ 31, 1, 0, /* 50 */ 32, 1, 0, /* 53 */ 33, 1, 0, /* 56 */ 34, 1, 0, /* 59 */ 35, 1, 0, /* 62 */ 65439, 1, 0, /* 65 */ 65513, 1, 0, /* 68 */ 3, 0, /* 70 */ 4, 0, /* 72 */ 6, 0, /* 74 */ 11, 0, /* 76 */ 12, 0, /* 78 */ 22, 0, /* 80 */ 23, 0, /* 82 */ 29, 0, /* 84 */ 30, 0, /* 86 */ 65308, 72, 0, /* 89 */ 65346, 72, 0, /* 92 */ 38, 65322, 73, 0, /* 96 */ 95, 0, /* 98 */ 96, 0, /* 100 */ 106, 0, /* 102 */ 187, 0, /* 104 */ 219, 0, /* 106 */ 258, 0, /* 108 */ 266, 0, /* 110 */ 310, 0, /* 112 */ 65031, 0, /* 114 */ 65108, 0, /* 116 */ 65172, 0, /* 118 */ 65226, 0, /* 120 */ 65229, 0, /* 122 */ 65270, 0, /* 124 */ 65278, 0, /* 126 */ 65295, 0, /* 128 */ 65317, 0, /* 130 */ 37, 65430, 103, 65395, 65333, 0, /* 136 */ 65349, 0, /* 138 */ 65395, 0, /* 140 */ 65410, 0, /* 142 */ 65415, 0, /* 144 */ 65419, 0, /* 146 */ 65420, 0, /* 148 */ 65421, 0, /* 150 */ 65422, 0, /* 152 */ 65430, 0, /* 154 */ 65440, 0, /* 156 */ 65441, 0, /* 158 */ 141, 65498, 0, /* 161 */ 65516, 234, 65498, 0, /* 165 */ 65515, 235, 65498, 0, /* 169 */ 65514, 236, 65498, 0, /* 173 */ 65513, 237, 65498, 0, /* 177 */ 65512, 238, 65498, 0, /* 181 */ 65511, 239, 65498, 0, /* 185 */ 65510, 240, 65498, 0, /* 189 */ 65509, 241, 65498, 0, /* 193 */ 65508, 242, 65498, 0, /* 197 */ 65507, 243, 65498, 0, /* 201 */ 65506, 244, 65498, 0, /* 205 */ 65505, 245, 65498, 0, /* 209 */ 65504, 246, 65498, 0, /* 213 */ 65503, 247, 65498, 0, /* 217 */ 65502, 248, 65498, 0, /* 221 */ 65501, 249, 65498, 0, /* 225 */ 65500, 250, 65498, 0, /* 229 */ 65295, 347, 65499, 0, /* 233 */ 65333, 344, 65502, 0, /* 237 */ 65507, 0, /* 239 */ 65510, 0, /* 241 */ 65511, 0, /* 243 */ 65512, 0, /* 245 */ 65516, 0, /* 247 */ 65521, 0, /* 249 */ 65522, 0, /* 251 */ 65535, 0, }; static const uint16_t MipsSubRegIdxLists[] = { /* 0 */ 1, 0, /* 2 */ 3, 4, 5, 6, 7, 0, /* 8 */ 2, 9, 8, 0, /* 12 */ 9, 1, 8, 10, 11, 0, }; static const MCRegisterDesc MipsRegDesc[] = { // Descriptors { 6, 0, 0, 0, 0, 0 }, { 2007, 1, 82, 1, 4017, 0 }, { 2010, 1, 1, 1, 4017, 0 }, { 2102, 1, 1, 1, 4017, 0 }, { 1973, 1, 1, 1, 4017, 0 }, { 2027, 8, 1, 2, 32, 4 }, { 2054, 1, 1, 1, 1089, 0 }, { 2071, 1, 1, 1, 1089, 0 }, { 1985, 1, 102, 1, 1089, 0 }, { 1988, 1, 104, 1, 1089, 0 }, { 2061, 1, 1, 1, 1089, 0 }, { 2000, 1, 1, 1, 1089, 0 }, { 1994, 1, 1, 1, 1089, 0 }, { 2038, 1, 1, 1, 1089, 0 }, { 2092, 1, 1, 1, 1089, 0 }, { 2081, 1, 1, 1, 1089, 0 }, { 2019, 1, 1, 1, 1089, 0 }, { 2045, 1, 1, 1, 1089, 0 }, { 1970, 1, 1, 1, 1089, 0 }, { 1967, 1, 106, 1, 1089, 0 }, { 1991, 1, 108, 1, 1089, 0 }, { 1980, 1, 110, 1, 1089, 0 }, { 152, 1, 110, 1, 1089, 0 }, { 365, 1, 110, 1, 1089, 0 }, { 537, 1, 110, 1, 1089, 0 }, { 703, 1, 110, 1, 1089, 0 }, { 155, 190, 110, 9, 1042, 10 }, { 368, 190, 1, 9, 1042, 10 }, { 540, 190, 1, 9, 1042, 10 }, { 706, 190, 1, 9, 1042, 10 }, { 1271, 237, 1, 0, 0, 2 }, { 160, 1, 1, 1, 1153, 0 }, { 373, 1, 1, 1, 1153, 0 }, { 545, 1, 1, 1, 1153, 0 }, { 711, 1, 1, 1, 1153, 0 }, { 1278, 1, 1, 1, 1153, 0 }, { 1412, 1, 1, 1, 1153, 0 }, { 1542, 1, 1, 1, 1153, 0 }, { 1672, 1, 1, 1, 1153, 0 }, { 70, 1, 1, 1, 1153, 0 }, { 283, 1, 1, 1, 1153, 0 }, { 496, 1, 1, 1, 1153, 0 }, { 662, 1, 1, 1, 1153, 0 }, { 820, 1, 1, 1, 1153, 0 }, { 1383, 1, 1, 1, 1153, 0 }, { 1513, 1, 1, 1, 1153, 0 }, { 1643, 1, 1, 1, 1153, 0 }, { 1773, 1, 1, 1, 1153, 0 }, { 1911, 1, 1, 1, 1153, 0 }, { 130, 1, 1, 1, 1153, 0 }, { 343, 1, 1, 1, 1153, 0 }, { 531, 1, 1, 1, 1153, 0 }, { 697, 1, 1, 1, 1153, 0 }, { 842, 1, 1, 1, 1153, 0 }, { 1405, 1, 1, 1, 1153, 0 }, { 1535, 1, 1, 1, 1153, 0 }, { 1665, 1, 1, 1, 1153, 0 }, { 1795, 1, 1, 1, 1153, 0 }, { 1933, 1, 1, 1, 1153, 0 }, { 0, 1, 1, 1, 1153, 0 }, { 213, 1, 1, 1, 1153, 0 }, { 426, 1, 1, 1, 1153, 0 }, { 592, 1, 1, 1, 1153, 0 }, { 750, 1, 1, 1, 1153, 0 }, { 1313, 1, 1, 1, 1153, 0 }, { 1447, 1, 1, 1, 1153, 0 }, { 1577, 1, 1, 1, 1153, 0 }, { 1707, 1, 1, 1, 1153, 0 }, { 1829, 1, 1, 1, 1153, 0 }, { 45, 1, 1, 1, 1153, 0 }, { 258, 1, 1, 1, 1153, 0 }, { 471, 1, 1, 1, 1153, 0 }, { 637, 1, 1, 1, 1153, 0 }, { 795, 1, 1, 1, 1153, 0 }, { 1358, 1, 1, 1, 1153, 0 }, { 1488, 1, 1, 1, 1153, 0 }, { 1618, 1, 1, 1, 1153, 0 }, { 1748, 1, 1, 1, 1153, 0 }, { 1886, 1, 1, 1, 1153, 0 }, { 105, 1, 1, 1, 1153, 0 }, { 318, 1, 1, 1, 1153, 0 }, { 7, 1, 1, 1, 1153, 0 }, { 220, 1, 1, 1, 1153, 0 }, { 433, 1, 1, 1, 1153, 0 }, { 599, 1, 1, 1, 1153, 0 }, { 757, 1, 1, 1, 1153, 0 }, { 1320, 1, 1, 1, 1153, 0 }, { 1454, 1, 1, 1, 1153, 0 }, { 1584, 1, 1, 1, 1153, 0 }, { 1714, 1, 1, 1, 1153, 0 }, { 1836, 1, 1, 1, 1153, 0 }, { 52, 1, 1, 1, 1153, 0 }, { 265, 1, 1, 1, 1153, 0 }, { 478, 1, 1, 1, 1153, 0 }, { 644, 1, 1, 1, 1153, 0 }, { 802, 1, 1, 1, 1153, 0 }, { 1365, 1, 1, 1, 1153, 0 }, { 1495, 1, 1, 1, 1153, 0 }, { 1625, 1, 1, 1, 1153, 0 }, { 1755, 1, 1, 1, 1153, 0 }, { 1893, 1, 1, 1, 1153, 0 }, { 112, 1, 1, 1, 1153, 0 }, { 325, 1, 1, 1, 1153, 0 }, { 164, 14, 1, 9, 994, 10 }, { 377, 17, 1, 9, 994, 10 }, { 549, 20, 1, 9, 994, 10 }, { 715, 23, 1, 9, 994, 10 }, { 1282, 26, 1, 9, 994, 10 }, { 1416, 29, 1, 9, 994, 10 }, { 1546, 32, 1, 9, 994, 10 }, { 1676, 35, 1, 9, 994, 10 }, { 1801, 38, 1, 9, 994, 10 }, { 1939, 41, 1, 9, 994, 10 }, { 14, 44, 1, 9, 994, 10 }, { 227, 47, 1, 9, 994, 10 }, { 440, 50, 1, 9, 994, 10 }, { 606, 53, 1, 9, 994, 10 }, { 764, 56, 1, 9, 994, 10 }, { 1327, 59, 1, 9, 994, 10 }, { 92, 1, 150, 1, 2401, 0 }, { 305, 1, 148, 1, 2401, 0 }, { 518, 1, 146, 1, 2401, 0 }, { 684, 1, 144, 1, 2401, 0 }, { 167, 1, 161, 1, 3985, 0 }, { 380, 1, 165, 1, 3985, 0 }, { 552, 1, 165, 1, 3985, 0 }, { 718, 1, 169, 1, 3985, 0 }, { 1285, 1, 169, 1, 3985, 0 }, { 1419, 1, 173, 1, 3985, 0 }, { 1549, 1, 173, 1, 3985, 0 }, { 1679, 1, 177, 1, 3985, 0 }, { 1804, 1, 177, 1, 3985, 0 }, { 1942, 1, 181, 1, 3985, 0 }, { 18, 1, 181, 1, 3985, 0 }, { 231, 1, 185, 1, 3985, 0 }, { 444, 1, 185, 1, 3985, 0 }, { 610, 1, 189, 1, 3985, 0 }, { 768, 1, 189, 1, 3985, 0 }, { 1331, 1, 193, 1, 3985, 0 }, { 1461, 1, 193, 1, 3985, 0 }, { 1591, 1, 197, 1, 3985, 0 }, { 1721, 1, 197, 1, 3985, 0 }, { 1843, 1, 201, 1, 3985, 0 }, { 59, 1, 201, 1, 3985, 0 }, { 272, 1, 205, 1, 3985, 0 }, { 485, 1, 205, 1, 3985, 0 }, { 651, 1, 209, 1, 3985, 0 }, { 809, 1, 209, 1, 3985, 0 }, { 1372, 1, 213, 1, 3985, 0 }, { 1502, 1, 213, 1, 3985, 0 }, { 1632, 1, 217, 1, 3985, 0 }, { 1762, 1, 217, 1, 3985, 0 }, { 1900, 1, 221, 1, 3985, 0 }, { 119, 1, 221, 1, 3985, 0 }, { 332, 1, 225, 1, 3985, 0 }, { 159, 1, 1, 1, 3985, 0 }, { 372, 1, 1, 1, 3985, 0 }, { 544, 1, 1, 1, 3985, 0 }, { 710, 1, 1, 1, 3985, 0 }, { 1277, 1, 1, 1, 3985, 0 }, { 1411, 1, 1, 1, 3985, 0 }, { 1541, 1, 1, 1, 3985, 0 }, { 1671, 1, 1, 1, 3985, 0 }, { 191, 1, 1, 1, 3985, 0 }, { 404, 1, 1, 1, 3985, 0 }, { 573, 1, 1, 1, 3985, 0 }, { 731, 1, 1, 1, 3985, 0 }, { 1294, 1, 1, 1, 3985, 0 }, { 1428, 1, 1, 1, 3985, 0 }, { 1558, 1, 1, 1, 3985, 0 }, { 1688, 1, 1, 1, 3985, 0 }, { 1813, 1, 1, 1, 3985, 0 }, { 1951, 1, 1, 1, 3985, 0 }, { 29, 1, 1, 1, 3985, 0 }, { 242, 1, 1, 1, 3985, 0 }, { 455, 1, 1, 1, 3985, 0 }, { 621, 1, 1, 1, 3985, 0 }, { 779, 1, 1, 1, 3985, 0 }, { 1342, 1, 1, 1, 3985, 0 }, { 1472, 1, 1, 1, 3985, 0 }, { 1602, 1, 1, 1, 3985, 0 }, { 1732, 1, 1, 1, 3985, 0 }, { 1854, 1, 1, 1, 3985, 0 }, { 76, 1, 1, 1, 3985, 0 }, { 289, 1, 1, 1, 3985, 0 }, { 502, 1, 1, 1, 3985, 0 }, { 668, 1, 1, 1, 3985, 0 }, { 826, 1, 1, 1, 3985, 0 }, { 1389, 1, 1, 1, 3985, 0 }, { 1519, 1, 1, 1, 3985, 0 }, { 1649, 1, 1, 1, 3985, 0 }, { 1779, 1, 1, 1, 3985, 0 }, { 1917, 1, 1, 1, 3985, 0 }, { 136, 1, 1, 1, 3985, 0 }, { 349, 1, 1, 1, 3985, 0 }, { 1253, 136, 1, 0, 1184, 2 }, { 170, 1, 158, 1, 3953, 0 }, { 383, 1, 158, 1, 3953, 0 }, { 555, 1, 158, 1, 3953, 0 }, { 721, 1, 158, 1, 3953, 0 }, { 1288, 1, 158, 1, 3953, 0 }, { 1422, 1, 158, 1, 3953, 0 }, { 1552, 1, 158, 1, 3953, 0 }, { 1682, 1, 158, 1, 3953, 0 }, { 1807, 1, 158, 1, 3953, 0 }, { 1945, 1, 158, 1, 3953, 0 }, { 22, 1, 158, 1, 3953, 0 }, { 235, 1, 158, 1, 3953, 0 }, { 448, 1, 158, 1, 3953, 0 }, { 614, 1, 158, 1, 3953, 0 }, { 772, 1, 158, 1, 3953, 0 }, { 1335, 1, 158, 1, 3953, 0 }, { 1465, 1, 158, 1, 3953, 0 }, { 1595, 1, 158, 1, 3953, 0 }, { 1725, 1, 158, 1, 3953, 0 }, { 1847, 1, 158, 1, 3953, 0 }, { 63, 1, 158, 1, 3953, 0 }, { 276, 1, 158, 1, 3953, 0 }, { 489, 1, 158, 1, 3953, 0 }, { 655, 1, 158, 1, 3953, 0 }, { 813, 1, 158, 1, 3953, 0 }, { 1376, 1, 158, 1, 3953, 0 }, { 1506, 1, 158, 1, 3953, 0 }, { 1636, 1, 158, 1, 3953, 0 }, { 1766, 1, 158, 1, 3953, 0 }, { 1904, 1, 158, 1, 3953, 0 }, { 123, 1, 158, 1, 3953, 0 }, { 336, 1, 158, 1, 3953, 0 }, { 1259, 128, 1, 0, 1216, 2 }, { 172, 1, 233, 1, 1826, 0 }, { 385, 1, 134, 1, 1826, 0 }, { 557, 1, 134, 1, 1826, 0 }, { 723, 1, 134, 1, 1826, 0 }, { 196, 1, 1, 1, 3921, 0 }, { 409, 1, 1, 1, 3921, 0 }, { 578, 1, 1, 1, 3921, 0 }, { 736, 1, 1, 1, 3921, 0 }, { 1299, 1, 1, 1, 3921, 0 }, { 1433, 1, 1, 1, 3921, 0 }, { 1563, 1, 1, 1, 3921, 0 }, { 1693, 1, 1, 1, 3921, 0 }, { 1818, 1, 1, 1, 3921, 0 }, { 1956, 1, 1, 1, 3921, 0 }, { 35, 1, 1, 1, 3921, 0 }, { 248, 1, 1, 1, 3921, 0 }, { 461, 1, 1, 1, 3921, 0 }, { 627, 1, 1, 1, 3921, 0 }, { 785, 1, 1, 1, 3921, 0 }, { 1348, 1, 1, 1, 3921, 0 }, { 1478, 1, 1, 1, 3921, 0 }, { 1608, 1, 1, 1, 3921, 0 }, { 1738, 1, 1, 1, 3921, 0 }, { 1860, 1, 1, 1, 3921, 0 }, { 82, 1, 1, 1, 3921, 0 }, { 295, 1, 1, 1, 3921, 0 }, { 508, 1, 1, 1, 3921, 0 }, { 674, 1, 1, 1, 3921, 0 }, { 832, 1, 1, 1, 3921, 0 }, { 1395, 1, 1, 1, 3921, 0 }, { 1525, 1, 1, 1, 3921, 0 }, { 1655, 1, 1, 1, 3921, 0 }, { 1785, 1, 1, 1, 3921, 0 }, { 1923, 1, 1, 1, 3921, 0 }, { 142, 1, 1, 1, 3921, 0 }, { 355, 1, 1, 1, 3921, 0 }, { 176, 1, 100, 1, 3921, 0 }, { 389, 1, 100, 1, 3921, 0 }, { 184, 1, 229, 1, 1794, 0 }, { 397, 1, 126, 1, 1794, 0 }, { 566, 1, 126, 1, 1794, 0 }, { 727, 1, 126, 1, 1794, 0 }, { 179, 1, 1, 1, 3889, 0 }, { 392, 1, 1, 1, 3889, 0 }, { 561, 1, 1, 1, 3889, 0 }, { 188, 1, 1, 1, 3889, 0 }, { 401, 1, 1, 1, 3889, 0 }, { 570, 1, 1, 1, 3889, 0 }, { 1239, 124, 1, 0, 1248, 2 }, { 201, 1, 98, 1, 3857, 0 }, { 414, 1, 98, 1, 3857, 0 }, { 583, 1, 98, 1, 3857, 0 }, { 741, 1, 98, 1, 3857, 0 }, { 1304, 1, 98, 1, 3857, 0 }, { 1438, 1, 98, 1, 3857, 0 }, { 1568, 1, 98, 1, 3857, 0 }, { 1698, 1, 98, 1, 3857, 0 }, { 1265, 122, 1, 0, 1280, 2 }, { 204, 1, 96, 1, 3825, 0 }, { 417, 1, 96, 1, 3825, 0 }, { 586, 1, 96, 1, 3825, 0 }, { 744, 1, 96, 1, 3825, 0 }, { 1307, 1, 96, 1, 3825, 0 }, { 1441, 1, 96, 1, 3825, 0 }, { 1571, 1, 96, 1, 3825, 0 }, { 1701, 1, 96, 1, 3825, 0 }, { 1823, 1, 96, 1, 3825, 0 }, { 1961, 1, 96, 1, 3825, 0 }, { 207, 1, 96, 1, 3825, 0 }, { 420, 1, 96, 1, 3825, 0 }, { 210, 92, 1, 8, 1425, 10 }, { 423, 92, 1, 8, 1425, 10 }, { 589, 92, 1, 8, 1425, 10 }, { 747, 92, 1, 8, 1425, 10 }, { 1310, 92, 1, 8, 1425, 10 }, { 1444, 92, 1, 8, 1425, 10 }, { 1574, 92, 1, 8, 1425, 10 }, { 1704, 92, 1, 8, 1425, 10 }, { 1826, 92, 1, 8, 1425, 10 }, { 1964, 92, 1, 8, 1425, 10 }, { 41, 92, 1, 8, 1425, 10 }, { 254, 92, 1, 8, 1425, 10 }, { 467, 92, 1, 8, 1425, 10 }, { 633, 92, 1, 8, 1425, 10 }, { 791, 92, 1, 8, 1425, 10 }, { 1354, 92, 1, 8, 1425, 10 }, { 1484, 92, 1, 8, 1425, 10 }, { 1614, 92, 1, 8, 1425, 10 }, { 1744, 92, 1, 8, 1425, 10 }, { 1866, 92, 1, 8, 1425, 10 }, { 88, 92, 1, 8, 1425, 10 }, { 301, 92, 1, 8, 1425, 10 }, { 514, 92, 1, 8, 1425, 10 }, { 680, 92, 1, 8, 1425, 10 }, { 838, 92, 1, 8, 1425, 10 }, { 1401, 92, 1, 8, 1425, 10 }, { 1531, 92, 1, 8, 1425, 10 }, { 1661, 92, 1, 8, 1425, 10 }, { 1791, 92, 1, 8, 1425, 10 }, { 1929, 92, 1, 8, 1425, 10 }, { 148, 92, 1, 8, 1425, 10 }, { 361, 92, 1, 8, 1425, 10 }, { 1245, 118, 1, 0, 1921, 2 }, { 869, 118, 1, 0, 1921, 2 }, { 947, 118, 1, 0, 1921, 2 }, { 997, 118, 1, 0, 1921, 2 }, { 1035, 118, 1, 0, 1921, 2 }, { 875, 130, 1, 12, 656, 10 }, { 882, 93, 159, 9, 1377, 10 }, { 953, 93, 159, 9, 1377, 10 }, { 1003, 93, 159, 9, 1377, 10 }, { 1041, 93, 159, 9, 1377, 10 }, { 1073, 93, 159, 9, 1377, 10 }, { 1105, 93, 159, 9, 1377, 10 }, { 1137, 93, 159, 9, 1377, 10 }, { 1169, 93, 159, 9, 1377, 10 }, { 1201, 93, 159, 9, 1377, 10 }, { 1227, 93, 159, 9, 1377, 10 }, { 848, 93, 159, 9, 1377, 10 }, { 926, 93, 159, 9, 1377, 10 }, { 983, 93, 159, 9, 1377, 10 }, { 1021, 93, 159, 9, 1377, 10 }, { 1059, 93, 159, 9, 1377, 10 }, { 1091, 93, 159, 9, 1377, 10 }, { 1123, 93, 159, 9, 1377, 10 }, { 1155, 93, 159, 9, 1377, 10 }, { 1187, 93, 159, 9, 1377, 10 }, { 1213, 93, 159, 9, 1377, 10 }, { 855, 93, 159, 9, 1377, 10 }, { 933, 93, 159, 9, 1377, 10 }, { 990, 93, 159, 9, 1377, 10 }, { 1028, 93, 159, 9, 1377, 10 }, { 1066, 93, 159, 9, 1377, 10 }, { 1098, 93, 159, 9, 1377, 10 }, { 1130, 93, 159, 9, 1377, 10 }, { 1162, 93, 159, 9, 1377, 10 }, { 1194, 93, 159, 9, 1377, 10 }, { 1220, 93, 159, 9, 1377, 10 }, { 862, 93, 159, 9, 1377, 10 }, { 940, 93, 159, 9, 1377, 10 }, { 1870, 1, 116, 1, 1120, 0 }, { 888, 138, 235, 0, 1344, 2 }, { 895, 152, 1, 0, 2241, 2 }, { 959, 152, 1, 0, 2241, 2 }, { 901, 152, 231, 0, 1312, 2 }, { 908, 154, 1, 0, 2273, 2 }, { 965, 154, 1, 0, 2273, 2 }, { 1009, 154, 1, 0, 2273, 2 }, { 1047, 154, 1, 0, 2273, 2 }, { 1079, 154, 1, 0, 2273, 2 }, { 1111, 154, 1, 0, 2273, 2 }, { 1143, 154, 1, 0, 2273, 2 }, { 1175, 154, 1, 0, 2273, 2 }, { 914, 156, 1, 0, 2273, 2 }, { 971, 156, 1, 0, 2273, 2 }, { 1015, 156, 1, 0, 2273, 2 }, { 1053, 156, 1, 0, 2273, 2 }, { 1085, 156, 1, 0, 2273, 2 }, { 1117, 156, 1, 0, 2273, 2 }, { 1149, 156, 1, 0, 2273, 2 }, { 1181, 156, 1, 0, 2273, 2 }, { 1207, 156, 1, 0, 2273, 2 }, { 1233, 156, 1, 0, 2273, 2 }, { 920, 156, 1, 0, 2273, 2 }, { 977, 156, 1, 0, 2273, 2 }, }; // OddSP Register Class... static const MCPhysReg OddSP[] = { Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // OddSP Bit set. static const uint8_t OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // CCR Register Class... static const MCPhysReg CCR[] = { Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, }; // CCR Bit set. static const uint8_t CCRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // COP2 Register Class... static const MCPhysReg COP2[] = { Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, }; // COP2 Bit set. static const uint8_t COP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, }; // COP3 Register Class... static const MCPhysReg COP3[] = { Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, }; // COP3 Bit set. static const uint8_t COP3Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, }; // DSPR Register Class... static const MCPhysReg DSPR[] = { Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // DSPR Bit set. static const uint8_t DSPRBits[] = { 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, }; // FGR32 Register Class... static const MCPhysReg FGR32[] = { Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGR32 Bit set. static const uint8_t FGR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // FGRCC Register Class... static const MCPhysReg FGRCC[] = { Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, }; // FGRCC Bit set. static const uint8_t FGRCCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // FGRH32 Register Class... static const MCPhysReg FGRH32[] = { Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, }; // FGRH32 Bit set. static const uint8_t FGRH32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, }; // GPR32 Register Class... static const MCPhysReg GPR32[] = { Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, }; // GPR32 Bit set. static const uint8_t GPR32Bits[] = { 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, }; // HWRegs Register Class... static const MCPhysReg HWRegs[] = { Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, }; // HWRegs Bit set. static const uint8_t HWRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // OddSP_with_sub_hi Register Class... static const MCPhysReg OddSP_with_sub_hi[] = { Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // OddSP_with_sub_hi Bit set. static const uint8_t OddSP_with_sub_hiBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // FGR32_and_OddSP Register Class... static const MCPhysReg FGR32_and_OddSP[] = { Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, }; // FGR32_and_OddSP Bit set. static const uint8_t FGR32_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, }; // FGRH32_and_OddSP Register Class... static const MCPhysReg FGRH32_and_OddSP[] = { Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, }; // FGRH32_and_OddSP Bit set. static const uint8_t FGRH32_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, }; // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // CPU16RegsPlusSP Register Class... static const MCPhysReg CPU16RegsPlusSP[] = { Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, }; // CPU16RegsPlusSP Bit set. static const uint8_t CPU16RegsPlusSPBits[] = { 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // CC Register Class... static const MCPhysReg CC[] = { Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, }; // CC Bit set. static const uint8_t CCBits[] = { 0x00, 0x00, 0x00, 0x80, 0x7f, }; // CPU16Regs Register Class... static const MCPhysReg CPU16Regs[] = { Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, }; // CPU16Regs Bit set. static const uint8_t CPU16RegsBits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // FCC Register Class... static const MCPhysReg FCC[] = { Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, }; // FCC Bit set. static const uint8_t FCCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // GPRMM16 Register Class... static const MCPhysReg GPRMM16[] = { Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // GPRMM16 Bit set. static const uint8_t GPRMM16Bits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // GPRMM16MoveP Register Class... static const MCPhysReg GPRMM16MoveP[] = { Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4, }; // GPRMM16MoveP Bit set. static const uint8_t GPRMM16MovePBits[] = { 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, }; // GPRMM16Zero Register Class... static const MCPhysReg GPRMM16Zero[] = { Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // GPRMM16Zero Bit set. static const uint8_t GPRMM16ZeroBits[] = { 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // MSACtrl Register Class... static const MCPhysReg MSACtrl[] = { Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, }; // MSACtrl Bit set. static const uint8_t MSACtrlBits[] = { 0x00, 0xfc, 0x03, }; // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, }; // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, }; // CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, }; // CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // CPU16Regs_and_GPRMM16MoveP Register Class... static const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { Mips_S1, Mips_V0, Mips_V1, Mips_S0, }; // CPU16Regs_and_GPRMM16MoveP Bit set. static const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // GPRMM16MoveP_and_GPRMM16Zero Register Class... static const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_GPRMM16Zero Bit set. static const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // HI32DSP Register Class... static const MCPhysReg HI32DSP[] = { Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, }; // HI32DSP Bit set. static const uint8_t HI32DSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, }; // LO32DSP Register Class... static const MCPhysReg LO32DSP[] = { Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, }; // LO32DSP Bit set. static const uint8_t LO32DSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { Mips_S1, Mips_V0, Mips_V1, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // CPURAReg Register Class... static const MCPhysReg CPURAReg[] = { Mips_RA, }; // CPURAReg Bit set. static const uint8_t CPURARegBits[] = { 0x00, 0x00, 0x08, }; // CPUSPReg Register Class... static const MCPhysReg CPUSPReg[] = { Mips_SP, }; // CPUSPReg Bit set. static const uint8_t CPUSPRegBits[] = { 0x00, 0x00, 0x10, }; // DSPCC Register Class... static const MCPhysReg DSPCC[] = { Mips_DSPCCond, }; // DSPCC Bit set. static const uint8_t DSPCCBits[] = { 0x04, }; // HI32 Register Class... static const MCPhysReg HI32[] = { Mips_HI0, }; // HI32 Bit set. static const uint8_t HI32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // LO32 Register Class... static const MCPhysReg LO32[] = { Mips_LO0, }; // LO32 Bit set. static const uint8_t LO32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; // FGR64 Register Class... static const MCPhysReg FGR64[] = { Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, }; // FGR64 Bit set. static const uint8_t FGR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR64 Register Class... static const MCPhysReg GPR64[] = { Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, }; // GPR64 Bit set. static const uint8_t GPR64Bits[] = { 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; // AFGR64 Register Class... static const MCPhysReg AFGR64[] = { Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, }; // AFGR64 Bit set. static const uint8_t AFGR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, }; // FGR64_and_OddSP Register Class... static const MCPhysReg FGR64_and_OddSP[] = { Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, }; // FGR64_and_OddSP Bit set. static const uint8_t FGR64_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // AFGR64_and_OddSP Register Class... static const MCPhysReg AFGR64_and_OddSP[] = { Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, }; // AFGR64_and_OddSP Bit set. static const uint8_t AFGR64_and_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, }; // GPR64_with_sub_32_in_CPU16Regs Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // ACC64DSP Register Class... static const MCPhysReg ACC64DSP[] = { Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, }; // ACC64DSP Bit set. static const uint8_t ACC64DSPBits[] = { 0x00, 0x00, 0x00, 0x3c, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. static const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... static const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { Mips_V0_64, Mips_V1_64, Mips_S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. static const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // OCTEON_MPL Register Class... static const MCPhysReg OCTEON_MPL[] = { Mips_MPL0, Mips_MPL1, Mips_MPL2, }; // OCTEON_MPL Bit set. static const uint8_t OCTEON_MPLBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, }; // OCTEON_P Register Class... static const MCPhysReg OCTEON_P[] = { Mips_P0, Mips_P1, Mips_P2, }; // OCTEON_P Bit set. static const uint8_t OCTEON_PBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, }; // ACC64 Register Class... static const MCPhysReg ACC64[] = { Mips_AC0, }; // ACC64 Bit set. static const uint8_t ACC64Bits[] = { 0x00, 0x00, 0x00, 0x04, }; // GPR64_with_sub_32_in_CPURAReg Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { Mips_RA_64, }; // GPR64_with_sub_32_in_CPURAReg Bit set. static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // GPR64_with_sub_32_in_CPUSPReg Register Class... static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { Mips_SP_64, }; // GPR64_with_sub_32_in_CPUSPReg Bit set. static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, }; // HI64 Register Class... static const MCPhysReg HI64[] = { Mips_HI0_64, }; // HI64 Bit set. static const uint8_t HI64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // LO64 Register Class... static const MCPhysReg LO64[] = { Mips_LO0_64, }; // LO64 Bit set. static const uint8_t LO64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // MSA128B Register Class... static const MCPhysReg MSA128B[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128B Bit set. static const uint8_t MSA128BBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128D Register Class... static const MCPhysReg MSA128D[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128D Bit set. static const uint8_t MSA128DBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128H Register Class... static const MCPhysReg MSA128H[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128H Bit set. static const uint8_t MSA128HBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128W Register Class... static const MCPhysReg MSA128W[] = { Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, }; // MSA128W Bit set. static const uint8_t MSA128WBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128B_with_sub_64_in_OddSP Register Class... static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, }; // MSA128B_with_sub_64_in_OddSP Bit set. static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, }; // MSA128WEvens Register Class... static const MCPhysReg MSA128WEvens[] = { Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30, }; // MSA128WEvens Bit set. static const uint8_t MSA128WEvensBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, }; // ACC128 Register Class... static const MCPhysReg ACC128[] = { Mips_AC0_64, }; // ACC128 Bit set. static const uint8_t ACC128Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; static const MCRegisterClass MipsMCRegisterClasses[] = { { OddSP, OddSPBits, sizeof(OddSPBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { COP2, COP2Bits, sizeof(COP2Bits) }, { COP3, COP3Bits, sizeof(COP3Bits) }, { DSPR, DSPRBits, sizeof(DSPRBits) }, { FGR32, FGR32Bits, sizeof(FGR32Bits) }, { FGRCC, FGRCCBits, sizeof(FGRCCBits) }, { FGRH32, FGRH32Bits, sizeof(FGRH32Bits) }, { GPR32, GPR32Bits, sizeof(GPR32Bits) }, { HWRegs, HWRegsBits, sizeof(HWRegsBits) }, { OddSP_with_sub_hi, OddSP_with_sub_hiBits, sizeof(OddSP_with_sub_hiBits) }, { FGR32_and_OddSP, FGR32_and_OddSPBits, sizeof(FGR32_and_OddSPBits) }, { FGRH32_and_OddSP, FGRH32_and_OddSPBits, sizeof(FGRH32_and_OddSPBits) }, { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits) }, { CPU16RegsPlusSP, CPU16RegsPlusSPBits, sizeof(CPU16RegsPlusSPBits) }, { CC, CCBits, sizeof(CCBits) }, { CPU16Regs, CPU16RegsBits, sizeof(CPU16RegsBits) }, { FCC, FCCBits, sizeof(FCCBits) }, { GPRMM16, GPRMM16Bits, sizeof(GPRMM16Bits) }, { GPRMM16MoveP, GPRMM16MovePBits, sizeof(GPRMM16MovePBits) }, { GPRMM16Zero, GPRMM16ZeroBits, sizeof(GPRMM16ZeroBits) }, { MSACtrl, MSACtrlBits, sizeof(MSACtrlBits) }, { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits) }, { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, sizeof(CPU16Regs_and_GPRMM16ZeroBits) }, { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, sizeof(CPU16Regs_and_GPRMM16MovePBits) }, { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits) }, { HI32DSP, HI32DSPBits, sizeof(HI32DSPBits) }, { LO32DSP, LO32DSPBits, sizeof(LO32DSPBits) }, { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, { CPURAReg, CPURARegBits, sizeof(CPURARegBits) }, { CPUSPReg, CPUSPRegBits, sizeof(CPUSPRegBits) }, { DSPCC, DSPCCBits, sizeof(DSPCCBits) }, { HI32, HI32Bits, sizeof(HI32Bits) }, { LO32, LO32Bits, sizeof(LO32Bits) }, { FGR64, FGR64Bits, sizeof(FGR64Bits) }, { GPR64, GPR64Bits, sizeof(GPR64Bits) }, { AFGR64, AFGR64Bits, sizeof(AFGR64Bits) }, { FGR64_and_OddSP, FGR64_and_OddSPBits, sizeof(FGR64_and_OddSPBits) }, { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits) }, { AFGR64_and_OddSP, AFGR64_and_OddSPBits, sizeof(AFGR64_and_OddSPBits) }, { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, sizeof(GPR64_with_sub_32_in_CPU16RegsBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits) }, { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits) }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits) }, { ACC64DSP, ACC64DSPBits, sizeof(ACC64DSPBits) }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits) }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits) }, { OCTEON_MPL, OCTEON_MPLBits, sizeof(OCTEON_MPLBits) }, { OCTEON_P, OCTEON_PBits, sizeof(OCTEON_PBits) }, { ACC64, ACC64Bits, sizeof(ACC64Bits) }, { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, sizeof(GPR64_with_sub_32_in_CPURARegBits) }, { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, sizeof(GPR64_with_sub_32_in_CPUSPRegBits) }, { HI64, HI64Bits, sizeof(HI64Bits) }, { LO64, LO64Bits, sizeof(LO64Bits) }, { MSA128B, MSA128BBits, sizeof(MSA128BBits) }, { MSA128D, MSA128DBits, sizeof(MSA128DBits) }, { MSA128H, MSA128HBits, sizeof(MSA128HBits) }, { MSA128W, MSA128WBits, sizeof(MSA128WBits) }, { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, sizeof(MSA128B_with_sub_64_in_OddSPBits) }, { MSA128WEvens, MSA128WEvensBits, sizeof(MSA128WEvensBits) }, { ACC128, ACC128Bits, sizeof(ACC128Bits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/Mips/MipsGenSubtargetInfo.inc000064400000000000000000000041750072674642500225710ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM #define Mips_FeatureCnMips (1ULL << 0) #define Mips_FeatureDSP (1ULL << 1) #define Mips_FeatureDSPR2 (1ULL << 2) #define Mips_FeatureFP64Bit (1ULL << 3) #define Mips_FeatureFPXX (1ULL << 4) #define Mips_FeatureGP64Bit (1ULL << 5) #define Mips_FeatureMSA (1ULL << 6) #define Mips_FeatureMicroMips (1ULL << 7) #define Mips_FeatureMips1 (1ULL << 8) #define Mips_FeatureMips2 (1ULL << 9) #define Mips_FeatureMips3 (1ULL << 10) #define Mips_FeatureMips3_32 (1ULL << 11) #define Mips_FeatureMips3_32r2 (1ULL << 12) #define Mips_FeatureMips4 (1ULL << 13) #define Mips_FeatureMips4_32 (1ULL << 14) #define Mips_FeatureMips4_32r2 (1ULL << 15) #define Mips_FeatureMips5 (1ULL << 16) #define Mips_FeatureMips5_32r2 (1ULL << 17) #define Mips_FeatureMips16 (1ULL << 18) #define Mips_FeatureMips32 (1ULL << 19) #define Mips_FeatureMips32r2 (1ULL << 20) #define Mips_FeatureMips32r3 (1ULL << 21) #define Mips_FeatureMips32r5 (1ULL << 22) #define Mips_FeatureMips32r6 (1ULL << 23) #define Mips_FeatureMips64 (1ULL << 24) #define Mips_FeatureMips64r2 (1ULL << 25) #define Mips_FeatureMips64r3 (1ULL << 26) #define Mips_FeatureMips64r5 (1ULL << 27) #define Mips_FeatureMips64r6 (1ULL << 28) #define Mips_FeatureNaN2008 (1ULL << 29) #define Mips_FeatureNoABICalls (1ULL << 30) #define Mips_FeatureNoOddSPReg (1ULL << 31) #define Mips_FeatureSingleFloat (1ULL << 32) #define Mips_FeatureVFPU (1ULL << 33) #endif // GET_SUBTARGETINFO_ENUM capstone-sys-0.15.0/capstone/arch/Mips/MipsInstPrinter.c000064400000000000000000000266520072674642500213210ustar 00000000000000//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an Mips MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_MIPS #include #include #include // debug #include #include "MipsInstPrinter.h" #include "../../MCInst.h" #include "../../utils.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "MipsMapping.h" #include "MipsInstPrinter.h" static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); static char *printAliasInstr(MCInst *MI, SStream *O, void *info); static char *printAlias(MCInst *MI, SStream *OS); // These enumeration declarations were originally in MipsInstrInfo.h but // had to be moved here to avoid circular dependencies between // LLVMMipsCodeGen and LLVMMipsAsmPrinter. // Mips Condition Codes typedef enum Mips_CondCode { // To be used with float branch True Mips_FCOND_F, Mips_FCOND_UN, Mips_FCOND_OEQ, Mips_FCOND_UEQ, Mips_FCOND_OLT, Mips_FCOND_ULT, Mips_FCOND_OLE, Mips_FCOND_ULE, Mips_FCOND_SF, Mips_FCOND_NGLE, Mips_FCOND_SEQ, Mips_FCOND_NGL, Mips_FCOND_LT, Mips_FCOND_NGE, Mips_FCOND_LE, Mips_FCOND_NGT, // To be used with float branch False // This conditions have the same mnemonic as the // above ones, but are used with a branch False; Mips_FCOND_T, Mips_FCOND_OR, Mips_FCOND_UNE, Mips_FCOND_ONE, Mips_FCOND_UGE, Mips_FCOND_OGE, Mips_FCOND_UGT, Mips_FCOND_OGT, Mips_FCOND_ST, Mips_FCOND_GLE, Mips_FCOND_SNE, Mips_FCOND_GL, Mips_FCOND_NLT, Mips_FCOND_GE, Mips_FCOND_NLE, Mips_FCOND_GT } Mips_CondCode; #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" static const char *getRegisterName(unsigned RegNo); static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); static void set_mem_access(MCInst *MI, bool status) { MI->csh->doing_mem = status; if (MI->csh->detail != CS_OPT_ON) return; if (status) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; } else { // done, create the next operand slot MI->flat_insn->detail->mips.op_count++; } } static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) { return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); } static const char* MipsFCCToString(Mips_CondCode CC) { switch (CC) { default: return 0; // never reach case Mips_FCOND_F: case Mips_FCOND_T: return "f"; case Mips_FCOND_UN: case Mips_FCOND_OR: return "un"; case Mips_FCOND_OEQ: case Mips_FCOND_UNE: return "eq"; case Mips_FCOND_UEQ: case Mips_FCOND_ONE: return "ueq"; case Mips_FCOND_OLT: case Mips_FCOND_UGE: return "olt"; case Mips_FCOND_ULT: case Mips_FCOND_OGE: return "ult"; case Mips_FCOND_OLE: case Mips_FCOND_UGT: return "ole"; case Mips_FCOND_ULE: case Mips_FCOND_OGT: return "ule"; case Mips_FCOND_SF: case Mips_FCOND_ST: return "sf"; case Mips_FCOND_NGLE: case Mips_FCOND_GLE: return "ngle"; case Mips_FCOND_SEQ: case Mips_FCOND_SNE: return "seq"; case Mips_FCOND_NGL: case Mips_FCOND_GL: return "ngl"; case Mips_FCOND_LT: case Mips_FCOND_NLT: return "lt"; case Mips_FCOND_NGE: case Mips_FCOND_GE: return "nge"; case Mips_FCOND_LE: case Mips_FCOND_NLE: return "le"; case Mips_FCOND_NGT: case Mips_FCOND_GT: return "ngt"; } } static void printRegName(SStream *OS, unsigned RegNo) { SStream_concat(OS, "$%s", getRegisterName(RegNo)); } void Mips_printInst(MCInst *MI, SStream *O, void *info) { char *mnem; switch (MCInst_getOpcode(MI)) { default: break; case Mips_Save16: case Mips_SaveX16: case Mips_Restore16: case Mips_RestoreX16: return; } // Try to print any aliases first. mnem = printAliasInstr(MI, O, info); if (!mnem) { mnem = printAlias(MI, O); if (!mnem) { printInstruction(MI, O, NULL); } } if (mnem) { // fixup instruction id due to the change in alias instruction MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); cs_mem_free(mnem); } } static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op; if (OpNo >= MI->size) return; Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { unsigned int reg = MCOperand_getReg(Op); printRegName(O, reg); reg = Mips_map_register(reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; } else { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; MI->flat_insn->detail->mips.op_count++; } } } else if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op); if (MI->csh->doing_mem) { if (imm) { // only print Imm offset if it is not 0 printInt64(O, imm); } if (MI->csh->detail) MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; } else { printInt64(O, imm); if (MI->csh->detail) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; MI->flat_insn->detail->mips.op_count++; } } } } static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, opNum); if (MCOperand_isImm(MO)) { int64_t imm = MCOperand_getImm(MO); printInt64(O, imm); if (MI->csh->detail) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; MI->flat_insn->detail->mips.op_count++; } } else printOperand(MI, opNum, O); } static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, opNum); if (MCOperand_isImm(MO)) { uint8_t imm = (uint8_t)MCOperand_getImm(MO); if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%x", imm); else SStream_concat(O, "%u", imm); if (MI->csh->detail) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; MI->flat_insn->detail->mips.op_count++; } } else printOperand(MI, opNum, O); } static void printMemOperand(MCInst *MI, int opNum, SStream *O) { // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) // opNum can be invalid if instruction had reglist as operand. // MemOperand is always last operand of instruction (base + offset). switch (MCInst_getOpcode(MI)) { default: break; case Mips_SWM32_MM: case Mips_LWM32_MM: case Mips_SWM16_MM: case Mips_LWM16_MM: opNum = MCInst_getNumOperands(MI) - 2; break; } set_mem_access(MI, true); printOperand(MI, opNum + 1, O); SStream_concat0(O, "("); printOperand(MI, opNum, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } // TODO??? static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) { // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. printOperand(MI, opNum, O); SStream_concat0(O, ", "); printOperand(MI, opNum + 1, O); return; } static void printFCCOperand(MCInst *MI, int opNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, opNum); SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); } static void printRegisterPair(MCInst *MI, int opNum, SStream *O) { printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum))); } static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS) { SStream_concat(OS, "%s\t", Str); printOperand(MI, OpNo, OS); return cs_strdup(Str); } static char *printAlias2(const char *Str, MCInst *MI, unsigned OpNo0, unsigned OpNo1, SStream *OS) { char *tmp; tmp = printAlias1(Str, MI, OpNo0, OS); SStream_concat0(OS, ", "); printOperand(MI, OpNo1, OS); return tmp; } #define GET_REGINFO_ENUM #include "MipsGenRegisterInfo.inc" static char *printAlias(MCInst *MI, SStream *OS) { switch (MCInst_getOpcode(MI)) { case Mips_BEQ: case Mips_BEQ_MM: // beq $zero, $zero, $L2 => b $L2 // beq $r0, $zero, $L2 => beqz $r0, $L2 if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) return printAlias1("b", MI, 2, OS); if (isReg(MI, 1, Mips_ZERO)) return printAlias2("beqz", MI, 0, 2, OS); return NULL; case Mips_BEQ64: // beq $r0, $zero, $L2 => beqz $r0, $L2 if (isReg(MI, 1, Mips_ZERO_64)) return printAlias2("beqz", MI, 0, 2, OS); return NULL; case Mips_BNE: // bne $r0, $zero, $L2 => bnez $r0, $L2 if (isReg(MI, 1, Mips_ZERO)) return printAlias2("bnez", MI, 0, 2, OS); return NULL; case Mips_BNE64: // bne $r0, $zero, $L2 => bnez $r0, $L2 if (isReg(MI, 1, Mips_ZERO_64)) return printAlias2("bnez", MI, 0, 2, OS); return NULL; case Mips_BGEZAL: // bgezal $zero, $L1 => bal $L1 if (isReg(MI, 0, Mips_ZERO)) return printAlias1("bal", MI, 1, OS); return NULL; case Mips_BC1T: // bc1t $fcc0, $L1 => bc1t $L1 if (isReg(MI, 0, Mips_FCC0)) return printAlias1("bc1t", MI, 1, OS); return NULL; case Mips_BC1F: // bc1f $fcc0, $L1 => bc1f $L1 if (isReg(MI, 0, Mips_FCC0)) return printAlias1("bc1f", MI, 1, OS); return NULL; case Mips_JALR: // jalr $ra, $r1 => jalr $r1 if (isReg(MI, 0, Mips_RA)) return printAlias1("jalr", MI, 1, OS); return NULL; case Mips_JALR64: // jalr $ra, $r1 => jalr $r1 if (isReg(MI, 0, Mips_RA_64)) return printAlias1("jalr", MI, 1, OS); return NULL; case Mips_NOR: case Mips_NOR_MM: // nor $r0, $r1, $zero => not $r0, $r1 if (isReg(MI, 2, Mips_ZERO)) return printAlias2("not", MI, 0, 1, OS); return NULL; case Mips_NOR64: // nor $r0, $r1, $zero => not $r0, $r1 if (isReg(MI, 2, Mips_ZERO_64)) return printAlias2("not", MI, 0, 1, OS); return NULL; case Mips_OR: // or $r0, $r1, $zero => move $r0, $r1 if (isReg(MI, 2, Mips_ZERO)) return printAlias2("move", MI, 0, 1, OS); return NULL; default: return NULL; } } static void printRegisterList(MCInst *MI, int opNum, SStream *O) { int i, e, reg; // - 2 because register List is always first operand of instruction and it is // always followed by memory operand (base + offset). for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { if (i != opNum) SStream_concat0(O, ", "); reg = MCOperand_getReg(MCInst_getOperand(MI, i)); printRegName(O, reg); if (MI->csh->detail) { MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; MI->flat_insn->detail->mips.op_count++; } } } #define PRINT_ALIAS_INSTR #include "MipsGenAsmWriter.inc" #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsInstPrinter.h000064400000000000000000000013530072674642500213150ustar 00000000000000//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints a Mips MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_MIPSINSTPRINTER_H #define CS_MIPSINSTPRINTER_H #include "../../MCInst.h" #include "../../SStream.h" void Mips_printInst(MCInst *MI, SStream *O, void *info); #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsMapping.c000064400000000000000000000775360072674642500204420ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_MIPS #include // debug #include #include "../../utils.h" #include "MipsMapping.h" #define GET_INSTRINFO_ENUM #include "MipsGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { { MIPS_REG_INVALID, NULL }, { MIPS_REG_PC, "pc"}, //{ MIPS_REG_0, "0"}, { MIPS_REG_0, "zero"}, { MIPS_REG_1, "at"}, //{ MIPS_REG_1, "1"}, { MIPS_REG_2, "v0"}, //{ MIPS_REG_2, "2"}, { MIPS_REG_3, "v1"}, //{ MIPS_REG_3, "3"}, { MIPS_REG_4, "a0"}, //{ MIPS_REG_4, "4"}, { MIPS_REG_5, "a1"}, //{ MIPS_REG_5, "5"}, { MIPS_REG_6, "a2"}, //{ MIPS_REG_6, "6"}, { MIPS_REG_7, "a3"}, //{ MIPS_REG_7, "7"}, { MIPS_REG_8, "t0"}, //{ MIPS_REG_8, "8"}, { MIPS_REG_9, "t1"}, //{ MIPS_REG_9, "9"}, { MIPS_REG_10, "t2"}, //{ MIPS_REG_10, "10"}, { MIPS_REG_11, "t3"}, //{ MIPS_REG_11, "11"}, { MIPS_REG_12, "t4"}, //{ MIPS_REG_12, "12"}, { MIPS_REG_13, "t5"}, //{ MIPS_REG_13, "13"}, { MIPS_REG_14, "t6"}, //{ MIPS_REG_14, "14"}, { MIPS_REG_15, "t7"}, //{ MIPS_REG_15, "15"}, { MIPS_REG_16, "s0"}, //{ MIPS_REG_16, "16"}, { MIPS_REG_17, "s1"}, //{ MIPS_REG_17, "17"}, { MIPS_REG_18, "s2"}, //{ MIPS_REG_18, "18"}, { MIPS_REG_19, "s3"}, //{ MIPS_REG_19, "19"}, { MIPS_REG_20, "s4"}, //{ MIPS_REG_20, "20"}, { MIPS_REG_21, "s5"}, //{ MIPS_REG_21, "21"}, { MIPS_REG_22, "s6"}, //{ MIPS_REG_22, "22"}, { MIPS_REG_23, "s7"}, //{ MIPS_REG_23, "23"}, { MIPS_REG_24, "t8"}, //{ MIPS_REG_24, "24"}, { MIPS_REG_25, "t9"}, //{ MIPS_REG_25, "25"}, { MIPS_REG_26, "k0"}, //{ MIPS_REG_26, "26"}, { MIPS_REG_27, "k1"}, //{ MIPS_REG_27, "27"}, { MIPS_REG_28, "gp"}, //{ MIPS_REG_28, "28"}, { MIPS_REG_29, "sp"}, //{ MIPS_REG_29, "29"}, { MIPS_REG_30, "fp"}, //{ MIPS_REG_30, "30"}, { MIPS_REG_31, "ra"}, //{ MIPS_REG_31, "31"}, { MIPS_REG_DSPCCOND, "dspccond"}, { MIPS_REG_DSPCARRY, "dspcarry"}, { MIPS_REG_DSPEFI, "dspefi"}, { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, { MIPS_REG_DSPPOS, "dsppos"}, { MIPS_REG_DSPSCOUNT, "dspscount"}, { MIPS_REG_AC0, "ac0"}, { MIPS_REG_AC1, "ac1"}, { MIPS_REG_AC2, "ac2"}, { MIPS_REG_AC3, "ac3"}, { MIPS_REG_CC0, "cc0"}, { MIPS_REG_CC1, "cc1"}, { MIPS_REG_CC2, "cc2"}, { MIPS_REG_CC3, "cc3"}, { MIPS_REG_CC4, "cc4"}, { MIPS_REG_CC5, "cc5"}, { MIPS_REG_CC6, "cc6"}, { MIPS_REG_CC7, "cc7"}, { MIPS_REG_F0, "f0"}, { MIPS_REG_F1, "f1"}, { MIPS_REG_F2, "f2"}, { MIPS_REG_F3, "f3"}, { MIPS_REG_F4, "f4"}, { MIPS_REG_F5, "f5"}, { MIPS_REG_F6, "f6"}, { MIPS_REG_F7, "f7"}, { MIPS_REG_F8, "f8"}, { MIPS_REG_F9, "f9"}, { MIPS_REG_F10, "f10"}, { MIPS_REG_F11, "f11"}, { MIPS_REG_F12, "f12"}, { MIPS_REG_F13, "f13"}, { MIPS_REG_F14, "f14"}, { MIPS_REG_F15, "f15"}, { MIPS_REG_F16, "f16"}, { MIPS_REG_F17, "f17"}, { MIPS_REG_F18, "f18"}, { MIPS_REG_F19, "f19"}, { MIPS_REG_F20, "f20"}, { MIPS_REG_F21, "f21"}, { MIPS_REG_F22, "f22"}, { MIPS_REG_F23, "f23"}, { MIPS_REG_F24, "f24"}, { MIPS_REG_F25, "f25"}, { MIPS_REG_F26, "f26"}, { MIPS_REG_F27, "f27"}, { MIPS_REG_F28, "f28"}, { MIPS_REG_F29, "f29"}, { MIPS_REG_F30, "f30"}, { MIPS_REG_F31, "f31"}, { MIPS_REG_FCC0, "fcc0"}, { MIPS_REG_FCC1, "fcc1"}, { MIPS_REG_FCC2, "fcc2"}, { MIPS_REG_FCC3, "fcc3"}, { MIPS_REG_FCC4, "fcc4"}, { MIPS_REG_FCC5, "fcc5"}, { MIPS_REG_FCC6, "fcc6"}, { MIPS_REG_FCC7, "fcc7"}, { MIPS_REG_W0, "w0"}, { MIPS_REG_W1, "w1"}, { MIPS_REG_W2, "w2"}, { MIPS_REG_W3, "w3"}, { MIPS_REG_W4, "w4"}, { MIPS_REG_W5, "w5"}, { MIPS_REG_W6, "w6"}, { MIPS_REG_W7, "w7"}, { MIPS_REG_W8, "w8"}, { MIPS_REG_W9, "w9"}, { MIPS_REG_W10, "w10"}, { MIPS_REG_W11, "w11"}, { MIPS_REG_W12, "w12"}, { MIPS_REG_W13, "w13"}, { MIPS_REG_W14, "w14"}, { MIPS_REG_W15, "w15"}, { MIPS_REG_W16, "w16"}, { MIPS_REG_W17, "w17"}, { MIPS_REG_W18, "w18"}, { MIPS_REG_W19, "w19"}, { MIPS_REG_W20, "w20"}, { MIPS_REG_W21, "w21"}, { MIPS_REG_W22, "w22"}, { MIPS_REG_W23, "w23"}, { MIPS_REG_W24, "w24"}, { MIPS_REG_W25, "w25"}, { MIPS_REG_W26, "w26"}, { MIPS_REG_W27, "w27"}, { MIPS_REG_W28, "w28"}, { MIPS_REG_W29, "w29"}, { MIPS_REG_W30, "w30"}, { MIPS_REG_W31, "w31"}, { MIPS_REG_HI, "hi"}, { MIPS_REG_LO, "lo"}, { MIPS_REG_P0, "p0"}, { MIPS_REG_P1, "p1"}, { MIPS_REG_P2, "p2"}, { MIPS_REG_MPL0, "mpl0"}, { MIPS_REG_MPL1, "mpl1"}, { MIPS_REG_MPL2, "mpl2"}, }; #endif const char *Mips_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "MipsMappingInsn.inc" }; // given internal insn id, return public instruction info void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned int i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; insn->detail->groups_count++; } #endif } } } static const name_map insn_name_maps[] = { { MIPS_INS_INVALID, NULL }, { MIPS_INS_ABSQ_S, "absq_s" }, { MIPS_INS_ADD, "add" }, { MIPS_INS_ADDIUPC, "addiupc" }, { MIPS_INS_ADDIUR1SP, "addiur1sp" }, { MIPS_INS_ADDIUR2, "addiur2" }, { MIPS_INS_ADDIUS5, "addius5" }, { MIPS_INS_ADDIUSP, "addiusp" }, { MIPS_INS_ADDQH, "addqh" }, { MIPS_INS_ADDQH_R, "addqh_r" }, { MIPS_INS_ADDQ, "addq" }, { MIPS_INS_ADDQ_S, "addq_s" }, { MIPS_INS_ADDSC, "addsc" }, { MIPS_INS_ADDS_A, "adds_a" }, { MIPS_INS_ADDS_S, "adds_s" }, { MIPS_INS_ADDS_U, "adds_u" }, { MIPS_INS_ADDU16, "addu16" }, { MIPS_INS_ADDUH, "adduh" }, { MIPS_INS_ADDUH_R, "adduh_r" }, { MIPS_INS_ADDU, "addu" }, { MIPS_INS_ADDU_S, "addu_s" }, { MIPS_INS_ADDVI, "addvi" }, { MIPS_INS_ADDV, "addv" }, { MIPS_INS_ADDWC, "addwc" }, { MIPS_INS_ADD_A, "add_a" }, { MIPS_INS_ADDI, "addi" }, { MIPS_INS_ADDIU, "addiu" }, { MIPS_INS_ALIGN, "align" }, { MIPS_INS_ALUIPC, "aluipc" }, { MIPS_INS_AND, "and" }, { MIPS_INS_AND16, "and16" }, { MIPS_INS_ANDI16, "andi16" }, { MIPS_INS_ANDI, "andi" }, { MIPS_INS_APPEND, "append" }, { MIPS_INS_ASUB_S, "asub_s" }, { MIPS_INS_ASUB_U, "asub_u" }, { MIPS_INS_AUI, "aui" }, { MIPS_INS_AUIPC, "auipc" }, { MIPS_INS_AVER_S, "aver_s" }, { MIPS_INS_AVER_U, "aver_u" }, { MIPS_INS_AVE_S, "ave_s" }, { MIPS_INS_AVE_U, "ave_u" }, { MIPS_INS_B16, "b16" }, { MIPS_INS_BADDU, "baddu" }, { MIPS_INS_BAL, "bal" }, { MIPS_INS_BALC, "balc" }, { MIPS_INS_BALIGN, "balign" }, { MIPS_INS_BBIT0, "bbit0" }, { MIPS_INS_BBIT032, "bbit032" }, { MIPS_INS_BBIT1, "bbit1" }, { MIPS_INS_BBIT132, "bbit132" }, { MIPS_INS_BC, "bc" }, { MIPS_INS_BC0F, "bc0f" }, { MIPS_INS_BC0FL, "bc0fl" }, { MIPS_INS_BC0T, "bc0t" }, { MIPS_INS_BC0TL, "bc0tl" }, { MIPS_INS_BC1EQZ, "bc1eqz" }, { MIPS_INS_BC1F, "bc1f" }, { MIPS_INS_BC1FL, "bc1fl" }, { MIPS_INS_BC1NEZ, "bc1nez" }, { MIPS_INS_BC1T, "bc1t" }, { MIPS_INS_BC1TL, "bc1tl" }, { MIPS_INS_BC2EQZ, "bc2eqz" }, { MIPS_INS_BC2F, "bc2f" }, { MIPS_INS_BC2FL, "bc2fl" }, { MIPS_INS_BC2NEZ, "bc2nez" }, { MIPS_INS_BC2T, "bc2t" }, { MIPS_INS_BC2TL, "bc2tl" }, { MIPS_INS_BC3F, "bc3f" }, { MIPS_INS_BC3FL, "bc3fl" }, { MIPS_INS_BC3T, "bc3t" }, { MIPS_INS_BC3TL, "bc3tl" }, { MIPS_INS_BCLRI, "bclri" }, { MIPS_INS_BCLR, "bclr" }, { MIPS_INS_BEQ, "beq" }, { MIPS_INS_BEQC, "beqc" }, { MIPS_INS_BEQL, "beql" }, { MIPS_INS_BEQZ16, "beqz16" }, { MIPS_INS_BEQZALC, "beqzalc" }, { MIPS_INS_BEQZC, "beqzc" }, { MIPS_INS_BGEC, "bgec" }, { MIPS_INS_BGEUC, "bgeuc" }, { MIPS_INS_BGEZ, "bgez" }, { MIPS_INS_BGEZAL, "bgezal" }, { MIPS_INS_BGEZALC, "bgezalc" }, { MIPS_INS_BGEZALL, "bgezall" }, { MIPS_INS_BGEZALS, "bgezals" }, { MIPS_INS_BGEZC, "bgezc" }, { MIPS_INS_BGEZL, "bgezl" }, { MIPS_INS_BGTZ, "bgtz" }, { MIPS_INS_BGTZALC, "bgtzalc" }, { MIPS_INS_BGTZC, "bgtzc" }, { MIPS_INS_BGTZL, "bgtzl" }, { MIPS_INS_BINSLI, "binsli" }, { MIPS_INS_BINSL, "binsl" }, { MIPS_INS_BINSRI, "binsri" }, { MIPS_INS_BINSR, "binsr" }, { MIPS_INS_BITREV, "bitrev" }, { MIPS_INS_BITSWAP, "bitswap" }, { MIPS_INS_BLEZ, "blez" }, { MIPS_INS_BLEZALC, "blezalc" }, { MIPS_INS_BLEZC, "blezc" }, { MIPS_INS_BLEZL, "blezl" }, { MIPS_INS_BLTC, "bltc" }, { MIPS_INS_BLTUC, "bltuc" }, { MIPS_INS_BLTZ, "bltz" }, { MIPS_INS_BLTZAL, "bltzal" }, { MIPS_INS_BLTZALC, "bltzalc" }, { MIPS_INS_BLTZALL, "bltzall" }, { MIPS_INS_BLTZALS, "bltzals" }, { MIPS_INS_BLTZC, "bltzc" }, { MIPS_INS_BLTZL, "bltzl" }, { MIPS_INS_BMNZI, "bmnzi" }, { MIPS_INS_BMNZ, "bmnz" }, { MIPS_INS_BMZI, "bmzi" }, { MIPS_INS_BMZ, "bmz" }, { MIPS_INS_BNE, "bne" }, { MIPS_INS_BNEC, "bnec" }, { MIPS_INS_BNEGI, "bnegi" }, { MIPS_INS_BNEG, "bneg" }, { MIPS_INS_BNEL, "bnel" }, { MIPS_INS_BNEZ16, "bnez16" }, { MIPS_INS_BNEZALC, "bnezalc" }, { MIPS_INS_BNEZC, "bnezc" }, { MIPS_INS_BNVC, "bnvc" }, { MIPS_INS_BNZ, "bnz" }, { MIPS_INS_BOVC, "bovc" }, { MIPS_INS_BPOSGE32, "bposge32" }, { MIPS_INS_BREAK, "break" }, { MIPS_INS_BREAK16, "break16" }, { MIPS_INS_BSELI, "bseli" }, { MIPS_INS_BSEL, "bsel" }, { MIPS_INS_BSETI, "bseti" }, { MIPS_INS_BSET, "bset" }, { MIPS_INS_BZ, "bz" }, { MIPS_INS_BEQZ, "beqz" }, { MIPS_INS_B, "b" }, { MIPS_INS_BNEZ, "bnez" }, { MIPS_INS_BTEQZ, "bteqz" }, { MIPS_INS_BTNEZ, "btnez" }, { MIPS_INS_CACHE, "cache" }, { MIPS_INS_CEIL, "ceil" }, { MIPS_INS_CEQI, "ceqi" }, { MIPS_INS_CEQ, "ceq" }, { MIPS_INS_CFC1, "cfc1" }, { MIPS_INS_CFCMSA, "cfcmsa" }, { MIPS_INS_CINS, "cins" }, { MIPS_INS_CINS32, "cins32" }, { MIPS_INS_CLASS, "class" }, { MIPS_INS_CLEI_S, "clei_s" }, { MIPS_INS_CLEI_U, "clei_u" }, { MIPS_INS_CLE_S, "cle_s" }, { MIPS_INS_CLE_U, "cle_u" }, { MIPS_INS_CLO, "clo" }, { MIPS_INS_CLTI_S, "clti_s" }, { MIPS_INS_CLTI_U, "clti_u" }, { MIPS_INS_CLT_S, "clt_s" }, { MIPS_INS_CLT_U, "clt_u" }, { MIPS_INS_CLZ, "clz" }, { MIPS_INS_CMPGDU, "cmpgdu" }, { MIPS_INS_CMPGU, "cmpgu" }, { MIPS_INS_CMPU, "cmpu" }, { MIPS_INS_CMP, "cmp" }, { MIPS_INS_COPY_S, "copy_s" }, { MIPS_INS_COPY_U, "copy_u" }, { MIPS_INS_CTC1, "ctc1" }, { MIPS_INS_CTCMSA, "ctcmsa" }, { MIPS_INS_CVT, "cvt" }, { MIPS_INS_C, "c" }, { MIPS_INS_CMPI, "cmpi" }, { MIPS_INS_DADD, "dadd" }, { MIPS_INS_DADDI, "daddi" }, { MIPS_INS_DADDIU, "daddiu" }, { MIPS_INS_DADDU, "daddu" }, { MIPS_INS_DAHI, "dahi" }, { MIPS_INS_DALIGN, "dalign" }, { MIPS_INS_DATI, "dati" }, { MIPS_INS_DAUI, "daui" }, { MIPS_INS_DBITSWAP, "dbitswap" }, { MIPS_INS_DCLO, "dclo" }, { MIPS_INS_DCLZ, "dclz" }, { MIPS_INS_DDIV, "ddiv" }, { MIPS_INS_DDIVU, "ddivu" }, { MIPS_INS_DERET, "deret" }, { MIPS_INS_DEXT, "dext" }, { MIPS_INS_DEXTM, "dextm" }, { MIPS_INS_DEXTU, "dextu" }, { MIPS_INS_DI, "di" }, { MIPS_INS_DINS, "dins" }, { MIPS_INS_DINSM, "dinsm" }, { MIPS_INS_DINSU, "dinsu" }, { MIPS_INS_DIV, "div" }, { MIPS_INS_DIVU, "divu" }, { MIPS_INS_DIV_S, "div_s" }, { MIPS_INS_DIV_U, "div_u" }, { MIPS_INS_DLSA, "dlsa" }, { MIPS_INS_DMFC0, "dmfc0" }, { MIPS_INS_DMFC1, "dmfc1" }, { MIPS_INS_DMFC2, "dmfc2" }, { MIPS_INS_DMOD, "dmod" }, { MIPS_INS_DMODU, "dmodu" }, { MIPS_INS_DMTC0, "dmtc0" }, { MIPS_INS_DMTC1, "dmtc1" }, { MIPS_INS_DMTC2, "dmtc2" }, { MIPS_INS_DMUH, "dmuh" }, { MIPS_INS_DMUHU, "dmuhu" }, { MIPS_INS_DMUL, "dmul" }, { MIPS_INS_DMULT, "dmult" }, { MIPS_INS_DMULTU, "dmultu" }, { MIPS_INS_DMULU, "dmulu" }, { MIPS_INS_DOTP_S, "dotp_s" }, { MIPS_INS_DOTP_U, "dotp_u" }, { MIPS_INS_DPADD_S, "dpadd_s" }, { MIPS_INS_DPADD_U, "dpadd_u" }, { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, { MIPS_INS_DPAQX_S, "dpaqx_s" }, { MIPS_INS_DPAQ_SA, "dpaq_sa" }, { MIPS_INS_DPAQ_S, "dpaq_s" }, { MIPS_INS_DPAU, "dpau" }, { MIPS_INS_DPAX, "dpax" }, { MIPS_INS_DPA, "dpa" }, { MIPS_INS_DPOP, "dpop" }, { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, { MIPS_INS_DPSQX_S, "dpsqx_s" }, { MIPS_INS_DPSQ_SA, "dpsq_sa" }, { MIPS_INS_DPSQ_S, "dpsq_s" }, { MIPS_INS_DPSUB_S, "dpsub_s" }, { MIPS_INS_DPSUB_U, "dpsub_u" }, { MIPS_INS_DPSU, "dpsu" }, { MIPS_INS_DPSX, "dpsx" }, { MIPS_INS_DPS, "dps" }, { MIPS_INS_DROTR, "drotr" }, { MIPS_INS_DROTR32, "drotr32" }, { MIPS_INS_DROTRV, "drotrv" }, { MIPS_INS_DSBH, "dsbh" }, { MIPS_INS_DSHD, "dshd" }, { MIPS_INS_DSLL, "dsll" }, { MIPS_INS_DSLL32, "dsll32" }, { MIPS_INS_DSLLV, "dsllv" }, { MIPS_INS_DSRA, "dsra" }, { MIPS_INS_DSRA32, "dsra32" }, { MIPS_INS_DSRAV, "dsrav" }, { MIPS_INS_DSRL, "dsrl" }, { MIPS_INS_DSRL32, "dsrl32" }, { MIPS_INS_DSRLV, "dsrlv" }, { MIPS_INS_DSUB, "dsub" }, { MIPS_INS_DSUBU, "dsubu" }, { MIPS_INS_EHB, "ehb" }, { MIPS_INS_EI, "ei" }, { MIPS_INS_ERET, "eret" }, { MIPS_INS_EXT, "ext" }, { MIPS_INS_EXTP, "extp" }, { MIPS_INS_EXTPDP, "extpdp" }, { MIPS_INS_EXTPDPV, "extpdpv" }, { MIPS_INS_EXTPV, "extpv" }, { MIPS_INS_EXTRV_RS, "extrv_rs" }, { MIPS_INS_EXTRV_R, "extrv_r" }, { MIPS_INS_EXTRV_S, "extrv_s" }, { MIPS_INS_EXTRV, "extrv" }, { MIPS_INS_EXTR_RS, "extr_rs" }, { MIPS_INS_EXTR_R, "extr_r" }, { MIPS_INS_EXTR_S, "extr_s" }, { MIPS_INS_EXTR, "extr" }, { MIPS_INS_EXTS, "exts" }, { MIPS_INS_EXTS32, "exts32" }, { MIPS_INS_ABS, "abs" }, { MIPS_INS_FADD, "fadd" }, { MIPS_INS_FCAF, "fcaf" }, { MIPS_INS_FCEQ, "fceq" }, { MIPS_INS_FCLASS, "fclass" }, { MIPS_INS_FCLE, "fcle" }, { MIPS_INS_FCLT, "fclt" }, { MIPS_INS_FCNE, "fcne" }, { MIPS_INS_FCOR, "fcor" }, { MIPS_INS_FCUEQ, "fcueq" }, { MIPS_INS_FCULE, "fcule" }, { MIPS_INS_FCULT, "fcult" }, { MIPS_INS_FCUNE, "fcune" }, { MIPS_INS_FCUN, "fcun" }, { MIPS_INS_FDIV, "fdiv" }, { MIPS_INS_FEXDO, "fexdo" }, { MIPS_INS_FEXP2, "fexp2" }, { MIPS_INS_FEXUPL, "fexupl" }, { MIPS_INS_FEXUPR, "fexupr" }, { MIPS_INS_FFINT_S, "ffint_s" }, { MIPS_INS_FFINT_U, "ffint_u" }, { MIPS_INS_FFQL, "ffql" }, { MIPS_INS_FFQR, "ffqr" }, { MIPS_INS_FILL, "fill" }, { MIPS_INS_FLOG2, "flog2" }, { MIPS_INS_FLOOR, "floor" }, { MIPS_INS_FMADD, "fmadd" }, { MIPS_INS_FMAX_A, "fmax_a" }, { MIPS_INS_FMAX, "fmax" }, { MIPS_INS_FMIN_A, "fmin_a" }, { MIPS_INS_FMIN, "fmin" }, { MIPS_INS_MOV, "mov" }, { MIPS_INS_FMSUB, "fmsub" }, { MIPS_INS_FMUL, "fmul" }, { MIPS_INS_MUL, "mul" }, { MIPS_INS_NEG, "neg" }, { MIPS_INS_FRCP, "frcp" }, { MIPS_INS_FRINT, "frint" }, { MIPS_INS_FRSQRT, "frsqrt" }, { MIPS_INS_FSAF, "fsaf" }, { MIPS_INS_FSEQ, "fseq" }, { MIPS_INS_FSLE, "fsle" }, { MIPS_INS_FSLT, "fslt" }, { MIPS_INS_FSNE, "fsne" }, { MIPS_INS_FSOR, "fsor" }, { MIPS_INS_FSQRT, "fsqrt" }, { MIPS_INS_SQRT, "sqrt" }, { MIPS_INS_FSUB, "fsub" }, { MIPS_INS_SUB, "sub" }, { MIPS_INS_FSUEQ, "fsueq" }, { MIPS_INS_FSULE, "fsule" }, { MIPS_INS_FSULT, "fsult" }, { MIPS_INS_FSUNE, "fsune" }, { MIPS_INS_FSUN, "fsun" }, { MIPS_INS_FTINT_S, "ftint_s" }, { MIPS_INS_FTINT_U, "ftint_u" }, { MIPS_INS_FTQ, "ftq" }, { MIPS_INS_FTRUNC_S, "ftrunc_s" }, { MIPS_INS_FTRUNC_U, "ftrunc_u" }, { MIPS_INS_HADD_S, "hadd_s" }, { MIPS_INS_HADD_U, "hadd_u" }, { MIPS_INS_HSUB_S, "hsub_s" }, { MIPS_INS_HSUB_U, "hsub_u" }, { MIPS_INS_ILVEV, "ilvev" }, { MIPS_INS_ILVL, "ilvl" }, { MIPS_INS_ILVOD, "ilvod" }, { MIPS_INS_ILVR, "ilvr" }, { MIPS_INS_INS, "ins" }, { MIPS_INS_INSERT, "insert" }, { MIPS_INS_INSV, "insv" }, { MIPS_INS_INSVE, "insve" }, { MIPS_INS_J, "j" }, { MIPS_INS_JAL, "jal" }, { MIPS_INS_JALR, "jalr" }, { MIPS_INS_JALRS16, "jalrs16" }, { MIPS_INS_JALRS, "jalrs" }, { MIPS_INS_JALS, "jals" }, { MIPS_INS_JALX, "jalx" }, { MIPS_INS_JIALC, "jialc" }, { MIPS_INS_JIC, "jic" }, { MIPS_INS_JR, "jr" }, { MIPS_INS_JR16, "jr16" }, { MIPS_INS_JRADDIUSP, "jraddiusp" }, { MIPS_INS_JRC, "jrc" }, { MIPS_INS_JALRC, "jalrc" }, { MIPS_INS_LB, "lb" }, { MIPS_INS_LBU16, "lbu16" }, { MIPS_INS_LBUX, "lbux" }, { MIPS_INS_LBU, "lbu" }, { MIPS_INS_LD, "ld" }, { MIPS_INS_LDC1, "ldc1" }, { MIPS_INS_LDC2, "ldc2" }, { MIPS_INS_LDC3, "ldc3" }, { MIPS_INS_LDI, "ldi" }, { MIPS_INS_LDL, "ldl" }, { MIPS_INS_LDPC, "ldpc" }, { MIPS_INS_LDR, "ldr" }, { MIPS_INS_LDXC1, "ldxc1" }, { MIPS_INS_LH, "lh" }, { MIPS_INS_LHU16, "lhu16" }, { MIPS_INS_LHX, "lhx" }, { MIPS_INS_LHU, "lhu" }, { MIPS_INS_LI16, "li16" }, { MIPS_INS_LL, "ll" }, { MIPS_INS_LLD, "lld" }, { MIPS_INS_LSA, "lsa" }, { MIPS_INS_LUXC1, "luxc1" }, { MIPS_INS_LUI, "lui" }, { MIPS_INS_LW, "lw" }, { MIPS_INS_LW16, "lw16" }, { MIPS_INS_LWC1, "lwc1" }, { MIPS_INS_LWC2, "lwc2" }, { MIPS_INS_LWC3, "lwc3" }, { MIPS_INS_LWL, "lwl" }, { MIPS_INS_LWM16, "lwm16" }, { MIPS_INS_LWM32, "lwm32" }, { MIPS_INS_LWPC, "lwpc" }, { MIPS_INS_LWP, "lwp" }, { MIPS_INS_LWR, "lwr" }, { MIPS_INS_LWUPC, "lwupc" }, { MIPS_INS_LWU, "lwu" }, { MIPS_INS_LWX, "lwx" }, { MIPS_INS_LWXC1, "lwxc1" }, { MIPS_INS_LWXS, "lwxs" }, { MIPS_INS_LI, "li" }, { MIPS_INS_MADD, "madd" }, { MIPS_INS_MADDF, "maddf" }, { MIPS_INS_MADDR_Q, "maddr_q" }, { MIPS_INS_MADDU, "maddu" }, { MIPS_INS_MADDV, "maddv" }, { MIPS_INS_MADD_Q, "madd_q" }, { MIPS_INS_MAQ_SA, "maq_sa" }, { MIPS_INS_MAQ_S, "maq_s" }, { MIPS_INS_MAXA, "maxa" }, { MIPS_INS_MAXI_S, "maxi_s" }, { MIPS_INS_MAXI_U, "maxi_u" }, { MIPS_INS_MAX_A, "max_a" }, { MIPS_INS_MAX, "max" }, { MIPS_INS_MAX_S, "max_s" }, { MIPS_INS_MAX_U, "max_u" }, { MIPS_INS_MFC0, "mfc0" }, { MIPS_INS_MFC1, "mfc1" }, { MIPS_INS_MFC2, "mfc2" }, { MIPS_INS_MFHC1, "mfhc1" }, { MIPS_INS_MFHI, "mfhi" }, { MIPS_INS_MFLO, "mflo" }, { MIPS_INS_MINA, "mina" }, { MIPS_INS_MINI_S, "mini_s" }, { MIPS_INS_MINI_U, "mini_u" }, { MIPS_INS_MIN_A, "min_a" }, { MIPS_INS_MIN, "min" }, { MIPS_INS_MIN_S, "min_s" }, { MIPS_INS_MIN_U, "min_u" }, { MIPS_INS_MOD, "mod" }, { MIPS_INS_MODSUB, "modsub" }, { MIPS_INS_MODU, "modu" }, { MIPS_INS_MOD_S, "mod_s" }, { MIPS_INS_MOD_U, "mod_u" }, { MIPS_INS_MOVE, "move" }, { MIPS_INS_MOVEP, "movep" }, { MIPS_INS_MOVF, "movf" }, { MIPS_INS_MOVN, "movn" }, { MIPS_INS_MOVT, "movt" }, { MIPS_INS_MOVZ, "movz" }, { MIPS_INS_MSUB, "msub" }, { MIPS_INS_MSUBF, "msubf" }, { MIPS_INS_MSUBR_Q, "msubr_q" }, { MIPS_INS_MSUBU, "msubu" }, { MIPS_INS_MSUBV, "msubv" }, { MIPS_INS_MSUB_Q, "msub_q" }, { MIPS_INS_MTC0, "mtc0" }, { MIPS_INS_MTC1, "mtc1" }, { MIPS_INS_MTC2, "mtc2" }, { MIPS_INS_MTHC1, "mthc1" }, { MIPS_INS_MTHI, "mthi" }, { MIPS_INS_MTHLIP, "mthlip" }, { MIPS_INS_MTLO, "mtlo" }, { MIPS_INS_MTM0, "mtm0" }, { MIPS_INS_MTM1, "mtm1" }, { MIPS_INS_MTM2, "mtm2" }, { MIPS_INS_MTP0, "mtp0" }, { MIPS_INS_MTP1, "mtp1" }, { MIPS_INS_MTP2, "mtp2" }, { MIPS_INS_MUH, "muh" }, { MIPS_INS_MUHU, "muhu" }, { MIPS_INS_MULEQ_S, "muleq_s" }, { MIPS_INS_MULEU_S, "muleu_s" }, { MIPS_INS_MULQ_RS, "mulq_rs" }, { MIPS_INS_MULQ_S, "mulq_s" }, { MIPS_INS_MULR_Q, "mulr_q" }, { MIPS_INS_MULSAQ_S, "mulsaq_s" }, { MIPS_INS_MULSA, "mulsa" }, { MIPS_INS_MULT, "mult" }, { MIPS_INS_MULTU, "multu" }, { MIPS_INS_MULU, "mulu" }, { MIPS_INS_MULV, "mulv" }, { MIPS_INS_MUL_Q, "mul_q" }, { MIPS_INS_MUL_S, "mul_s" }, { MIPS_INS_NLOC, "nloc" }, { MIPS_INS_NLZC, "nlzc" }, { MIPS_INS_NMADD, "nmadd" }, { MIPS_INS_NMSUB, "nmsub" }, { MIPS_INS_NOR, "nor" }, { MIPS_INS_NORI, "nori" }, { MIPS_INS_NOT16, "not16" }, { MIPS_INS_NOT, "not" }, { MIPS_INS_OR, "or" }, { MIPS_INS_OR16, "or16" }, { MIPS_INS_ORI, "ori" }, { MIPS_INS_PACKRL, "packrl" }, { MIPS_INS_PAUSE, "pause" }, { MIPS_INS_PCKEV, "pckev" }, { MIPS_INS_PCKOD, "pckod" }, { MIPS_INS_PCNT, "pcnt" }, { MIPS_INS_PICK, "pick" }, { MIPS_INS_POP, "pop" }, { MIPS_INS_PRECEQU, "precequ" }, { MIPS_INS_PRECEQ, "preceq" }, { MIPS_INS_PRECEU, "preceu" }, { MIPS_INS_PRECRQU_S, "precrqu_s" }, { MIPS_INS_PRECRQ, "precrq" }, { MIPS_INS_PRECRQ_RS, "precrq_rs" }, { MIPS_INS_PRECR, "precr" }, { MIPS_INS_PRECR_SRA, "precr_sra" }, { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, { MIPS_INS_PREF, "pref" }, { MIPS_INS_PREPEND, "prepend" }, { MIPS_INS_RADDU, "raddu" }, { MIPS_INS_RDDSP, "rddsp" }, { MIPS_INS_RDHWR, "rdhwr" }, { MIPS_INS_REPLV, "replv" }, { MIPS_INS_REPL, "repl" }, { MIPS_INS_RINT, "rint" }, { MIPS_INS_ROTR, "rotr" }, { MIPS_INS_ROTRV, "rotrv" }, { MIPS_INS_ROUND, "round" }, { MIPS_INS_SAT_S, "sat_s" }, { MIPS_INS_SAT_U, "sat_u" }, { MIPS_INS_SB, "sb" }, { MIPS_INS_SB16, "sb16" }, { MIPS_INS_SC, "sc" }, { MIPS_INS_SCD, "scd" }, { MIPS_INS_SD, "sd" }, { MIPS_INS_SDBBP, "sdbbp" }, { MIPS_INS_SDBBP16, "sdbbp16" }, { MIPS_INS_SDC1, "sdc1" }, { MIPS_INS_SDC2, "sdc2" }, { MIPS_INS_SDC3, "sdc3" }, { MIPS_INS_SDL, "sdl" }, { MIPS_INS_SDR, "sdr" }, { MIPS_INS_SDXC1, "sdxc1" }, { MIPS_INS_SEB, "seb" }, { MIPS_INS_SEH, "seh" }, { MIPS_INS_SELEQZ, "seleqz" }, { MIPS_INS_SELNEZ, "selnez" }, { MIPS_INS_SEL, "sel" }, { MIPS_INS_SEQ, "seq" }, { MIPS_INS_SEQI, "seqi" }, { MIPS_INS_SH, "sh" }, { MIPS_INS_SH16, "sh16" }, { MIPS_INS_SHF, "shf" }, { MIPS_INS_SHILO, "shilo" }, { MIPS_INS_SHILOV, "shilov" }, { MIPS_INS_SHLLV, "shllv" }, { MIPS_INS_SHLLV_S, "shllv_s" }, { MIPS_INS_SHLL, "shll" }, { MIPS_INS_SHLL_S, "shll_s" }, { MIPS_INS_SHRAV, "shrav" }, { MIPS_INS_SHRAV_R, "shrav_r" }, { MIPS_INS_SHRA, "shra" }, { MIPS_INS_SHRA_R, "shra_r" }, { MIPS_INS_SHRLV, "shrlv" }, { MIPS_INS_SHRL, "shrl" }, { MIPS_INS_SLDI, "sldi" }, { MIPS_INS_SLD, "sld" }, { MIPS_INS_SLL, "sll" }, { MIPS_INS_SLL16, "sll16" }, { MIPS_INS_SLLI, "slli" }, { MIPS_INS_SLLV, "sllv" }, { MIPS_INS_SLT, "slt" }, { MIPS_INS_SLTI, "slti" }, { MIPS_INS_SLTIU, "sltiu" }, { MIPS_INS_SLTU, "sltu" }, { MIPS_INS_SNE, "sne" }, { MIPS_INS_SNEI, "snei" }, { MIPS_INS_SPLATI, "splati" }, { MIPS_INS_SPLAT, "splat" }, { MIPS_INS_SRA, "sra" }, { MIPS_INS_SRAI, "srai" }, { MIPS_INS_SRARI, "srari" }, { MIPS_INS_SRAR, "srar" }, { MIPS_INS_SRAV, "srav" }, { MIPS_INS_SRL, "srl" }, { MIPS_INS_SRL16, "srl16" }, { MIPS_INS_SRLI, "srli" }, { MIPS_INS_SRLRI, "srlri" }, { MIPS_INS_SRLR, "srlr" }, { MIPS_INS_SRLV, "srlv" }, { MIPS_INS_SSNOP, "ssnop" }, { MIPS_INS_ST, "st" }, { MIPS_INS_SUBQH, "subqh" }, { MIPS_INS_SUBQH_R, "subqh_r" }, { MIPS_INS_SUBQ, "subq" }, { MIPS_INS_SUBQ_S, "subq_s" }, { MIPS_INS_SUBSUS_U, "subsus_u" }, { MIPS_INS_SUBSUU_S, "subsuu_s" }, { MIPS_INS_SUBS_S, "subs_s" }, { MIPS_INS_SUBS_U, "subs_u" }, { MIPS_INS_SUBU16, "subu16" }, { MIPS_INS_SUBUH, "subuh" }, { MIPS_INS_SUBUH_R, "subuh_r" }, { MIPS_INS_SUBU, "subu" }, { MIPS_INS_SUBU_S, "subu_s" }, { MIPS_INS_SUBVI, "subvi" }, { MIPS_INS_SUBV, "subv" }, { MIPS_INS_SUXC1, "suxc1" }, { MIPS_INS_SW, "sw" }, { MIPS_INS_SW16, "sw16" }, { MIPS_INS_SWC1, "swc1" }, { MIPS_INS_SWC2, "swc2" }, { MIPS_INS_SWC3, "swc3" }, { MIPS_INS_SWL, "swl" }, { MIPS_INS_SWM16, "swm16" }, { MIPS_INS_SWM32, "swm32" }, { MIPS_INS_SWP, "swp" }, { MIPS_INS_SWR, "swr" }, { MIPS_INS_SWXC1, "swxc1" }, { MIPS_INS_SYNC, "sync" }, { MIPS_INS_SYNCI, "synci" }, { MIPS_INS_SYSCALL, "syscall" }, { MIPS_INS_TEQ, "teq" }, { MIPS_INS_TEQI, "teqi" }, { MIPS_INS_TGE, "tge" }, { MIPS_INS_TGEI, "tgei" }, { MIPS_INS_TGEIU, "tgeiu" }, { MIPS_INS_TGEU, "tgeu" }, { MIPS_INS_TLBP, "tlbp" }, { MIPS_INS_TLBR, "tlbr" }, { MIPS_INS_TLBWI, "tlbwi" }, { MIPS_INS_TLBWR, "tlbwr" }, { MIPS_INS_TLT, "tlt" }, { MIPS_INS_TLTI, "tlti" }, { MIPS_INS_TLTIU, "tltiu" }, { MIPS_INS_TLTU, "tltu" }, { MIPS_INS_TNE, "tne" }, { MIPS_INS_TNEI, "tnei" }, { MIPS_INS_TRUNC, "trunc" }, { MIPS_INS_V3MULU, "v3mulu" }, { MIPS_INS_VMM0, "vmm0" }, { MIPS_INS_VMULU, "vmulu" }, { MIPS_INS_VSHF, "vshf" }, { MIPS_INS_WAIT, "wait" }, { MIPS_INS_WRDSP, "wrdsp" }, { MIPS_INS_WSBH, "wsbh" }, { MIPS_INS_XOR, "xor" }, { MIPS_INS_XOR16, "xor16" }, { MIPS_INS_XORI, "xori" }, // alias instructions { MIPS_INS_NOP, "nop" }, { MIPS_INS_NEGU, "negu" }, { MIPS_INS_JALR_HB, "jalr.hb" }, { MIPS_INS_JR_HB, "jr.hb" }, }; const char *Mips_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= MIPS_INS_ENDING) return NULL; return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { MIPS_GRP_INVALID, NULL }, { MIPS_GRP_JUMP, "jump" }, { MIPS_GRP_CALL, "call" }, { MIPS_GRP_RET, "ret" }, { MIPS_GRP_INT, "int" }, { MIPS_GRP_IRET, "iret" }, { MIPS_GRP_PRIVILEGE, "privileged" }, { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" }, // architecture-specific groups { MIPS_GRP_BITCOUNT, "bitcount" }, { MIPS_GRP_DSP, "dsp" }, { MIPS_GRP_DSPR2, "dspr2" }, { MIPS_GRP_FPIDX, "fpidx" }, { MIPS_GRP_MSA, "msa" }, { MIPS_GRP_MIPS32R2, "mips32r2" }, { MIPS_GRP_MIPS64, "mips64" }, { MIPS_GRP_MIPS64R2, "mips64r2" }, { MIPS_GRP_SEINREG, "seinreg" }, { MIPS_GRP_STDENC, "stdenc" }, { MIPS_GRP_SWAP, "swap" }, { MIPS_GRP_MICROMIPS, "micromips" }, { MIPS_GRP_MIPS16MODE, "mips16mode" }, { MIPS_GRP_FP64BIT, "fp64bit" }, { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, { MIPS_GRP_NOTNACL, "notnacl" }, { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, { MIPS_GRP_CNMIPS, "cnmips" }, { MIPS_GRP_MIPS32, "mips32" }, { MIPS_GRP_MIPS32R6, "mips32r6" }, { MIPS_GRP_MIPS64R6, "mips64r6" }, { MIPS_GRP_MIPS2, "mips2" }, { MIPS_GRP_MIPS3, "mips3" }, { MIPS_GRP_MIPS3_32, "mips3_32"}, { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, { MIPS_GRP_MIPS4_32, "mips4_32" }, { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, { MIPS_GRP_GP32BIT, "gp32bit" }, { MIPS_GRP_GP64BIT, "gp64bit" }, }; #endif const char *Mips_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // map instruction name to public instruction ID mips_reg Mips_map_insn(const char *name) { // handle special alias first unsigned int i; // NOTE: skip first NULL name in insn_name_maps i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); return (i != -1)? i : MIPS_REG_INVALID; } // map internal raw register to 'public' register mips_reg Mips_map_register(unsigned int r) { // for some reasons different Mips modes can map different register number to // the same Mips register. this function handles the issue for exposing Mips // operands by mapping internal registers to 'public' register. static const unsigned int map[] = { 0, MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, MIPS_REG_3, MIPS_REG_7, MIPS_REG_PC, MIPS_REG_RA, MIPS_REG_SP, MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, 0, 0, 0, 0, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1 }; if (r < ARR_SIZE(map)) return map[r]; // cannot find this register return 0; } #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsMapping.h000064400000000000000000000012770072674642500204340ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_MIPS_MAP_H #define CS_MIPS_MAP_H #include "capstone/capstone.h" // return name of regiser in friendly string const char *Mips_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *Mips_insn_name(csh handle, unsigned int id); const char *Mips_group_name(csh handle, unsigned int id); // map instruction name to instruction ID mips_reg Mips_map_insn(const char *name); // map internal raw register to 'public' register mips_reg Mips_map_register(unsigned int r); #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsMappingInsn.inc000064400000000000000000005674700072674642500216220ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADD, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ADDIUPC, MIPS_INS_ADDIUPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDQH_PH, MIPS_INS_ADDQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDQH_W, MIPS_INS_ADDQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDQ_PH, MIPS_INS_ADDQ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADDSC, MIPS_INS_ADDSC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADDS_A_B, MIPS_INS_ADDS_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_A_D, MIPS_INS_ADDS_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_A_H, MIPS_INS_ADDS_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_A_W, MIPS_INS_ADDS_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_S_B, MIPS_INS_ADDS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_S_D, MIPS_INS_ADDS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_S_H, MIPS_INS_ADDS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_S_W, MIPS_INS_ADDS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_U_B, MIPS_INS_ADDS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_U_D, MIPS_INS_ADDS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_U_H, MIPS_INS_ADDS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDS_U_W, MIPS_INS_ADDS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDU16_MM, MIPS_INS_ADDU16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDUH_QB, MIPS_INS_ADDUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDU_PH, MIPS_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDU_QB, MIPS_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADDU_S_PH, MIPS_INS_ADDU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ADDU_S_QB, MIPS_INS_ADDU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADDVI_B, MIPS_INS_ADDVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDVI_D, MIPS_INS_ADDVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDVI_H, MIPS_INS_ADDVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDVI_W, MIPS_INS_ADDVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDV_B, MIPS_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDV_D, MIPS_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDV_H, MIPS_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDV_W, MIPS_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADDWC, MIPS_INS_ADDWC, #ifndef CAPSTONE_DIET { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_ADD_A_B, MIPS_INS_ADD_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADD_A_D, MIPS_INS_ADD_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADD_A_H, MIPS_INS_ADD_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADD_A_W, MIPS_INS_ADD_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ADD_MM, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDi, MIPS_INS_ADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_ADDi_MM, MIPS_INS_ADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDiu, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDiu_MM, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ADDu, MIPS_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ADDu_MM, MIPS_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ALIGN, MIPS_INS_ALIGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_ALUIPC, MIPS_INS_ALUIPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_AND, MIPS_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_AND16_MM, MIPS_INS_AND16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_AND64, MIPS_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ANDI16_MM, MIPS_INS_ANDI16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ANDI_B, MIPS_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AND_MM, MIPS_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_AND_V, MIPS_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ANDi, MIPS_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_ANDi64, MIPS_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ANDi_MM, MIPS_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_APPEND, MIPS_INS_APPEND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_ASUB_S_B, MIPS_INS_ASUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_S_D, MIPS_INS_ASUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_S_H, MIPS_INS_ASUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_S_W, MIPS_INS_ASUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_U_B, MIPS_INS_ASUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_U_D, MIPS_INS_ASUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_U_H, MIPS_INS_ASUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ASUB_U_W, MIPS_INS_ASUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AUI, MIPS_INS_AUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_AUIPC, MIPS_INS_AUIPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_AVER_S_B, MIPS_INS_AVER_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_S_D, MIPS_INS_AVER_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_S_H, MIPS_INS_AVER_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_S_W, MIPS_INS_AVER_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_U_B, MIPS_INS_AVER_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_U_D, MIPS_INS_AVER_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_U_H, MIPS_INS_AVER_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVER_U_W, MIPS_INS_AVER_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_S_B, MIPS_INS_AVE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_S_D, MIPS_INS_AVE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_S_H, MIPS_INS_AVE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_S_W, MIPS_INS_AVE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_U_B, MIPS_INS_AVE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_U_D, MIPS_INS_AVE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_U_H, MIPS_INS_AVE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AVE_U_W, MIPS_INS_AVE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_AddiuRxImmX16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AddiuRxRxImm16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AddiuSpImm16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AddiuSpImmX16, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AdduRxRyRz16, MIPS_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_AndRxRxRy16, MIPS_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_B16_MM, MIPS_INS_B16, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BADDu, MIPS_INS_BADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_BAL, MIPS_INS_BAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BALC, MIPS_INS_BALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BALIGN, MIPS_INS_BALIGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_BBIT0, MIPS_INS_BBIT0, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 #endif }, { Mips_BBIT032, MIPS_INS_BBIT032, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 #endif }, { Mips_BBIT1, MIPS_INS_BBIT1, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 #endif }, { Mips_BBIT132, MIPS_INS_BBIT132, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0 #endif }, { Mips_BC, MIPS_INS_BC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BC0F, MIPS_INS_BC0F, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC0FL, MIPS_INS_BC0FL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC0T, MIPS_INS_BC0T, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC0TL, MIPS_INS_BC0TL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC1EQZ, MIPS_INS_BC1EQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BC1F, MIPS_INS_BC1F, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC1FL, MIPS_INS_BC1FL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC1F_MM, MIPS_INS_BC1F, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BC1NEZ, MIPS_INS_BC1NEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BC1T, MIPS_INS_BC1T, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC1TL, MIPS_INS_BC1TL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC1T_MM, MIPS_INS_BC1T, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BC2EQZ, MIPS_INS_BC2EQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BC2F, MIPS_INS_BC2F, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC2FL, MIPS_INS_BC2FL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC2NEZ, MIPS_INS_BC2NEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BC2T, MIPS_INS_BC2T, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC2TL, MIPS_INS_BC2TL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC3F, MIPS_INS_BC3F, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC3FL, MIPS_INS_BC3FL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC3T, MIPS_INS_BC3T, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BC3TL, MIPS_INS_BC3TL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BCLRI_B, MIPS_INS_BCLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLRI_D, MIPS_INS_BCLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLRI_H, MIPS_INS_BCLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLRI_W, MIPS_INS_BCLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLR_B, MIPS_INS_BCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLR_D, MIPS_INS_BCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLR_H, MIPS_INS_BCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BCLR_W, MIPS_INS_BCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BEQ, MIPS_INS_BEQ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BEQ64, MIPS_INS_BEQ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BEQC, MIPS_INS_BEQC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BEQL, MIPS_INS_BEQL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BEQZ16_MM, MIPS_INS_BEQZ16, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BEQZALC, MIPS_INS_BEQZALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BEQZC, MIPS_INS_BEQZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BEQZC_MM, MIPS_INS_BEQZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BEQ_MM, MIPS_INS_BEQ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BGEC, MIPS_INS_BGEC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BGEUC, MIPS_INS_BGEUC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BGEZ, MIPS_INS_BGEZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BGEZ64, MIPS_INS_BGEZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BGEZAL, MIPS_INS_BGEZAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_BGEZALC, MIPS_INS_BGEZALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BGEZALL, MIPS_INS_BGEZALL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_BGEZALS_MM, MIPS_INS_BGEZALS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_BGEZAL_MM, MIPS_INS_BGEZAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_BGEZC, MIPS_INS_BGEZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BGEZL, MIPS_INS_BGEZL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BGEZ_MM, MIPS_INS_BGEZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BGTZ, MIPS_INS_BGTZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BGTZ64, MIPS_INS_BGTZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BGTZALC, MIPS_INS_BGTZALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BGTZC, MIPS_INS_BGTZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BGTZL, MIPS_INS_BGTZL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BGTZ_MM, MIPS_INS_BGTZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BINSLI_B, MIPS_INS_BINSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSLI_D, MIPS_INS_BINSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSLI_H, MIPS_INS_BINSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSLI_W, MIPS_INS_BINSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSL_B, MIPS_INS_BINSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSL_D, MIPS_INS_BINSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSL_H, MIPS_INS_BINSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSL_W, MIPS_INS_BINSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSRI_B, MIPS_INS_BINSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSRI_D, MIPS_INS_BINSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSRI_H, MIPS_INS_BINSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSRI_W, MIPS_INS_BINSRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSR_B, MIPS_INS_BINSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSR_D, MIPS_INS_BINSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSR_H, MIPS_INS_BINSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BINSR_W, MIPS_INS_BINSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BITREV, MIPS_INS_BITREV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_BITSWAP, MIPS_INS_BITSWAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_BLEZ, MIPS_INS_BLEZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BLEZ64, MIPS_INS_BLEZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BLEZALC, MIPS_INS_BLEZALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BLEZC, MIPS_INS_BLEZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BLEZL, MIPS_INS_BLEZL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BLEZ_MM, MIPS_INS_BLEZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BLTC, MIPS_INS_BLTC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BLTUC, MIPS_INS_BLTUC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BLTZ, MIPS_INS_BLTZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BLTZ64, MIPS_INS_BLTZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BLTZAL, MIPS_INS_BLTZAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_BLTZALC, MIPS_INS_BLTZALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BLTZALL, MIPS_INS_BLTZALL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_BLTZALS_MM, MIPS_INS_BLTZALS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_BLTZAL_MM, MIPS_INS_BLTZAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_BLTZC, MIPS_INS_BLTZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BLTZL, MIPS_INS_BLTZL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BLTZ_MM, MIPS_INS_BLTZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BMNZI_B, MIPS_INS_BMNZI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BMNZ_V, MIPS_INS_BMNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BMZI_B, MIPS_INS_BMZI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BMZ_V, MIPS_INS_BMZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNE, MIPS_INS_BNE, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BNE64, MIPS_INS_BNE, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_BNEC, MIPS_INS_BNEC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BNEGI_B, MIPS_INS_BNEGI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEGI_D, MIPS_INS_BNEGI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEGI_H, MIPS_INS_BNEGI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEGI_W, MIPS_INS_BNEGI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEG_B, MIPS_INS_BNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEG_D, MIPS_INS_BNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEG_H, MIPS_INS_BNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEG_W, MIPS_INS_BNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BNEL, MIPS_INS_BNEL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 #endif }, { Mips_BNEZ16_MM, MIPS_INS_BNEZ16, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BNEZALC, MIPS_INS_BNEZALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BNEZC, MIPS_INS_BNEZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BNEZC_MM, MIPS_INS_BNEZC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BNE_MM, MIPS_INS_BNE, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0 #endif }, { Mips_BNVC, MIPS_INS_BNVC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BNZ_B, MIPS_INS_BNZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BNZ_D, MIPS_INS_BNZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BNZ_H, MIPS_INS_BNZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BNZ_V, MIPS_INS_BNZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BNZ_W, MIPS_INS_BNZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BOVC, MIPS_INS_BOVC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 #endif }, { Mips_BPOSGE32, MIPS_INS_BPOSGE32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0 #endif }, { Mips_BREAK, MIPS_INS_BREAK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_BREAK16_MM, MIPS_INS_BREAK16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_BREAK_MM, MIPS_INS_BREAK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_BSELI_B, MIPS_INS_BSELI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSEL_V, MIPS_INS_BSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSETI_B, MIPS_INS_BSETI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSETI_D, MIPS_INS_BSETI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSETI_H, MIPS_INS_BSETI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSETI_W, MIPS_INS_BSETI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSET_B, MIPS_INS_BSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSET_D, MIPS_INS_BSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSET_H, MIPS_INS_BSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BSET_W, MIPS_INS_BSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_BZ_B, MIPS_INS_BZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BZ_D, MIPS_INS_BZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BZ_H, MIPS_INS_BZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BZ_V, MIPS_INS_BZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BZ_W, MIPS_INS_BZ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0 #endif }, { Mips_BeqzRxImm16, MIPS_INS_BEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_BeqzRxImmX16, MIPS_INS_BEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_Bimm16, MIPS_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_BimmX16, MIPS_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_BnezRxImm16, MIPS_INS_BNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_BnezRxImmX16, MIPS_INS_BNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_Break16, MIPS_INS_BREAK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_Bteqz16, MIPS_INS_BTEQZ, #ifndef CAPSTONE_DIET { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_BteqzX16, MIPS_INS_BTEQZ, #ifndef CAPSTONE_DIET { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_Btnez16, MIPS_INS_BTNEZ, #ifndef CAPSTONE_DIET { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_BtnezX16, MIPS_INS_BTNEZ, #ifndef CAPSTONE_DIET { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0 #endif }, { Mips_CACHE, MIPS_INS_CACHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_CACHE_MM, MIPS_INS_CACHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CACHE_R6, MIPS_INS_CACHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CEIL_L_D64, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CEIL_L_S, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CEIL_W_D32, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_CEIL_W_D64, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CEIL_W_MM, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CEIL_W_S, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_CEIL_W_S_MM, MIPS_INS_CEIL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CEQI_B, MIPS_INS_CEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQI_D, MIPS_INS_CEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQI_H, MIPS_INS_CEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQI_W, MIPS_INS_CEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQ_B, MIPS_INS_CEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQ_D, MIPS_INS_CEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQ_H, MIPS_INS_CEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CEQ_W, MIPS_INS_CEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CFC1, MIPS_INS_CFC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_CFC1_MM, MIPS_INS_CFC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CFCMSA, MIPS_INS_CFCMSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CINS, MIPS_INS_CINS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_CINS32, MIPS_INS_CINS32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_CLASS_D, MIPS_INS_CLASS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CLASS_S, MIPS_INS_CLASS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CLEI_S_B, MIPS_INS_CLEI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_S_D, MIPS_INS_CLEI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_S_H, MIPS_INS_CLEI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_S_W, MIPS_INS_CLEI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_U_B, MIPS_INS_CLEI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_U_D, MIPS_INS_CLEI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_U_H, MIPS_INS_CLEI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLEI_U_W, MIPS_INS_CLEI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_S_B, MIPS_INS_CLE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_S_D, MIPS_INS_CLE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_S_H, MIPS_INS_CLE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_S_W, MIPS_INS_CLE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_U_B, MIPS_INS_CLE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_U_D, MIPS_INS_CLE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_U_H, MIPS_INS_CLE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLE_U_W, MIPS_INS_CLE_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLO, MIPS_INS_CLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_CLO_MM, MIPS_INS_CLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CLO_R6, MIPS_INS_CLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CLTI_S_B, MIPS_INS_CLTI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_S_D, MIPS_INS_CLTI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_S_H, MIPS_INS_CLTI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_S_W, MIPS_INS_CLTI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_U_B, MIPS_INS_CLTI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_U_D, MIPS_INS_CLTI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_U_H, MIPS_INS_CLTI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLTI_U_W, MIPS_INS_CLTI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_S_B, MIPS_INS_CLT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_S_D, MIPS_INS_CLT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_S_H, MIPS_INS_CLT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_S_W, MIPS_INS_CLT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_U_B, MIPS_INS_CLT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_U_D, MIPS_INS_CLT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_U_H, MIPS_INS_CLT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLT_U_W, MIPS_INS_CLT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CLZ, MIPS_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_CLZ_MM, MIPS_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CLZ_R6, MIPS_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMPU_EQ_QB, MIPS_INS_CMPU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMPU_LE_QB, MIPS_INS_CMPU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMPU_LT_QB, MIPS_INS_CMPU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMP_EQ_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_EQ_PH, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMP_EQ_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_F_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_F_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_LE_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_LE_PH, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMP_LE_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_LT_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_LT_PH, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_CMP_LT_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SAF_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SAF_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SEQ_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SEQ_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SLE_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SLE_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SLT_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SLT_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SUEQ_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SUEQ_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SULE_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SULE_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SULT_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SULT_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SUN_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_SUN_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_UEQ_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_UEQ_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_ULE_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_ULE_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_ULT_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_ULT_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_UN_D, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_CMP_UN_S, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_COPY_S_B, MIPS_INS_COPY_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_COPY_S_D, MIPS_INS_COPY_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_COPY_S_H, MIPS_INS_COPY_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_COPY_S_W, MIPS_INS_COPY_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_COPY_U_B, MIPS_INS_COPY_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_COPY_U_D, MIPS_INS_COPY_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_COPY_U_H, MIPS_INS_COPY_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_COPY_U_W, MIPS_INS_COPY_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CTC1, MIPS_INS_CTC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_CTC1_MM, MIPS_INS_CTC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CTCMSA, MIPS_INS_CTCMSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_CVT_D32_S, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_D32_W, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_D32_W_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_D64_L, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_D64_S, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_D64_W, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_D_S_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_L_D64, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 #endif }, { Mips_CVT_L_D64_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_L_S, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 #endif }, { Mips_CVT_L_S_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_S_D32, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_S_D32_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_S_D64, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_S_L, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_S_W, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_CVT_S_W_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_W_D32, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_W_D64, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_CVT_W_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_CVT_W_S, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_CVT_W_S_MM, MIPS_INS_CVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_C_EQ_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_EQ_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_EQ_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_F_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_F_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_F_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_LE_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_LE_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_LE_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_LT_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_LT_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_LT_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_NGE_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGE_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGE_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_NGLE_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGLE_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGLE_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_NGL_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGL_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGL_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_NGT_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGT_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_NGT_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_OLE_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_OLE_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_OLE_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_OLT_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_OLT_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_OLT_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_SEQ_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_SEQ_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_SEQ_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_SF_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_SF_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_SF_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_UEQ_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_UEQ_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_UEQ_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_ULE_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_ULE_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_ULE_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_ULT_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_ULT_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_ULT_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_C_UN_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_C_UN_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_C_UN_S, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_CmpRxRy16, MIPS_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_CmpiRxImm16, MIPS_INS_CMPI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_CmpiRxImmX16, MIPS_INS_CMPI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_DADD, MIPS_INS_DADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DADDi, MIPS_INS_DADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DADDiu, MIPS_INS_DADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DADDu, MIPS_INS_DADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DAHI, MIPS_INS_DAHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DALIGN, MIPS_INS_DALIGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DATI, MIPS_INS_DATI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DAUI, MIPS_INS_DAUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DBITSWAP, MIPS_INS_DBITSWAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DCLO, MIPS_INS_DCLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DCLO_R6, MIPS_INS_DCLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DCLZ, MIPS_INS_DCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DCLZ_R6, MIPS_INS_DCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DDIV, MIPS_INS_DDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DDIVU, MIPS_INS_DDIVU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DERET, MIPS_INS_DERET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 #endif }, { Mips_DERET_MM, MIPS_INS_DERET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_DEXT, MIPS_INS_DEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DEXTM, MIPS_INS_DEXTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DEXTU, MIPS_INS_DEXTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DI, MIPS_INS_DI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DINS, MIPS_INS_DINS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DINSM, MIPS_INS_DINSM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DINSU, MIPS_INS_DINSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_DIV, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_DIVU, MIPS_INS_DIVU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_DIV_S_B, MIPS_INS_DIV_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_S_D, MIPS_INS_DIV_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_S_H, MIPS_INS_DIV_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_S_W, MIPS_INS_DIV_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_U_B, MIPS_INS_DIV_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_U_D, MIPS_INS_DIV_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_U_H, MIPS_INS_DIV_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DIV_U_W, MIPS_INS_DIV_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DI_MM, MIPS_INS_DI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_DLSA, MIPS_INS_DLSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_DLSA_R6, MIPS_INS_DLSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMFC0, MIPS_INS_DMFC0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_DMFC1, MIPS_INS_DMFC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DMFC2, MIPS_INS_DMFC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_DMOD, MIPS_INS_DMOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMODU, MIPS_INS_DMODU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMTC0, MIPS_INS_DMTC0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_DMTC1, MIPS_INS_DMTC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DMTC2, MIPS_INS_DMTC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_DMUH, MIPS_INS_DMUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMUHU, MIPS_INS_DMUHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMUL, MIPS_INS_DMUL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_DMULT, MIPS_INS_DMULT, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMULTu, MIPS_INS_DMULTU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMULU, MIPS_INS_DMULU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DMUL_R6, MIPS_INS_DMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_DOTP_S_D, MIPS_INS_DOTP_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DOTP_S_H, MIPS_INS_DOTP_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DOTP_S_W, MIPS_INS_DOTP_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DOTP_U_D, MIPS_INS_DOTP_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DOTP_U_H, MIPS_INS_DOTP_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DOTP_U_W, MIPS_INS_DOTP_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPADD_S_D, MIPS_INS_DPADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPADD_S_H, MIPS_INS_DPADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPADD_S_W, MIPS_INS_DPADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPADD_U_D, MIPS_INS_DPADD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPADD_U_H, MIPS_INS_DPADD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPADD_U_W, MIPS_INS_DPADD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPAU_H_QBL, MIPS_INS_DPAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPAU_H_QBR, MIPS_INS_DPAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPAX_W_PH, MIPS_INS_DPAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPA_W_PH, MIPS_INS_DPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPOP, MIPS_INS_DPOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_DPSU_H_QBL, MIPS_INS_DPSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPSU_H_QBR, MIPS_INS_DPSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_DPSX_W_PH, MIPS_INS_DPSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DPS_W_PH, MIPS_INS_DPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_DROTR, MIPS_INS_DROTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 #endif }, { Mips_DROTR32, MIPS_INS_DROTR32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 #endif }, { Mips_DROTRV, MIPS_INS_DROTRV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 #endif }, { Mips_DSBH, MIPS_INS_DSBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 #endif }, { Mips_DSDIV, MIPS_INS_DDIV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DSHD, MIPS_INS_DSHD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 #endif }, { Mips_DSLL, MIPS_INS_DSLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSLL32, MIPS_INS_DSLL32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSLL64_32, MIPS_INS_DSLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_DSLLV, MIPS_INS_DSLLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSRA, MIPS_INS_DSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSRA32, MIPS_INS_DSRA32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSRAV, MIPS_INS_DSRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSRL, MIPS_INS_DSRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSRL32, MIPS_INS_DSRL32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSRLV, MIPS_INS_DSRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSUB, MIPS_INS_DSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DSUBu, MIPS_INS_DSUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_DUDIV, MIPS_INS_DDIVU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_DivRxRy16, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_DivuRxRy16, MIPS_INS_DIVU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_EHB, MIPS_INS_EHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_EHB_MM, MIPS_INS_EHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_EI, MIPS_INS_EI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_EI_MM, MIPS_INS_EI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ERET, MIPS_INS_ERET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0 #endif }, { Mips_ERET_MM, MIPS_INS_ERET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_EXT, MIPS_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_EXTP, MIPS_INS_EXTP, #ifndef CAPSTONE_DIET { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTPDP, MIPS_INS_EXTPDP, #ifndef CAPSTONE_DIET { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTPDPV, MIPS_INS_EXTPDPV, #ifndef CAPSTONE_DIET { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTPV, MIPS_INS_EXTPV, #ifndef CAPSTONE_DIET { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTRV_W, MIPS_INS_EXTRV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTR_R_W, MIPS_INS_EXTR_R, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTR_S_H, MIPS_INS_EXTR_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTR_W, MIPS_INS_EXTR, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_EXTS, MIPS_INS_EXTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_EXTS32, MIPS_INS_EXTS32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_EXT_MM, MIPS_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FABS_D32, MIPS_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FABS_D64, MIPS_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FABS_MM, MIPS_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FABS_S, MIPS_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FABS_S_MM, MIPS_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FADD_D, MIPS_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FADD_D32, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FADD_D64, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FADD_MM, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FADD_S, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FADD_S_MM, MIPS_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FADD_W, MIPS_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCAF_D, MIPS_INS_FCAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCAF_W, MIPS_INS_FCAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCEQ_D, MIPS_INS_FCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCEQ_W, MIPS_INS_FCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCLASS_D, MIPS_INS_FCLASS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCLASS_W, MIPS_INS_FCLASS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCLE_D, MIPS_INS_FCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCLE_W, MIPS_INS_FCLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCLT_D, MIPS_INS_FCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCLT_W, MIPS_INS_FCLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCMP_D32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FCMP_D32_MM, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FCMP_D64, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FCMP_S32, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_FCMP_S32_MM, MIPS_INS_C, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FCNE_D, MIPS_INS_FCNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCNE_W, MIPS_INS_FCNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCOR_D, MIPS_INS_FCOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCOR_W, MIPS_INS_FCOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCUEQ_D, MIPS_INS_FCUEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCUEQ_W, MIPS_INS_FCUEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCULE_D, MIPS_INS_FCULE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCULE_W, MIPS_INS_FCULE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCULT_D, MIPS_INS_FCULT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCULT_W, MIPS_INS_FCULT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCUNE_D, MIPS_INS_FCUNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCUNE_W, MIPS_INS_FCUNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCUN_D, MIPS_INS_FCUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FCUN_W, MIPS_INS_FCUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FDIV_D, MIPS_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FDIV_D32, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FDIV_D64, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FDIV_MM, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FDIV_S, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FDIV_S_MM, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FDIV_W, MIPS_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXDO_H, MIPS_INS_FEXDO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXDO_W, MIPS_INS_FEXDO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXP2_D, MIPS_INS_FEXP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXP2_W, MIPS_INS_FEXP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXUPL_D, MIPS_INS_FEXUPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXUPL_W, MIPS_INS_FEXUPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXUPR_D, MIPS_INS_FEXUPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FEXUPR_W, MIPS_INS_FEXUPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFINT_S_D, MIPS_INS_FFINT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFINT_S_W, MIPS_INS_FFINT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFINT_U_D, MIPS_INS_FFINT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFINT_U_W, MIPS_INS_FFINT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFQL_D, MIPS_INS_FFQL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFQL_W, MIPS_INS_FFQL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFQR_D, MIPS_INS_FFQR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FFQR_W, MIPS_INS_FFQR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FILL_B, MIPS_INS_FILL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FILL_D, MIPS_INS_FILL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_FILL_H, MIPS_INS_FILL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FILL_W, MIPS_INS_FILL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FLOG2_D, MIPS_INS_FLOG2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FLOG2_W, MIPS_INS_FLOG2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FLOOR_L_D64, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FLOOR_L_S, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FLOOR_W_D32, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FLOOR_W_D64, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FLOOR_W_MM, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FLOOR_W_S, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FMADD_D, MIPS_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMADD_W, MIPS_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMAX_A_D, MIPS_INS_FMAX_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMAX_A_W, MIPS_INS_FMAX_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMAX_D, MIPS_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMAX_W, MIPS_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMIN_A_D, MIPS_INS_FMIN_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMIN_A_W, MIPS_INS_FMIN_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMIN_D, MIPS_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMIN_W, MIPS_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMOV_D32, MIPS_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FMOV_D32_MM, MIPS_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FMOV_D64, MIPS_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FMOV_S, MIPS_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FMOV_S_MM, MIPS_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FMSUB_D, MIPS_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMSUB_W, MIPS_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMUL_D, MIPS_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FMUL_D32, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FMUL_D64, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FMUL_MM, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FMUL_S, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FMUL_S_MM, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FMUL_W, MIPS_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FNEG_D32, MIPS_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FNEG_D64, MIPS_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FNEG_MM, MIPS_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FNEG_S, MIPS_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FNEG_S_MM, MIPS_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FRCP_D, MIPS_INS_FRCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FRCP_W, MIPS_INS_FRCP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FRINT_D, MIPS_INS_FRINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FRINT_W, MIPS_INS_FRINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FRSQRT_D, MIPS_INS_FRSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FRSQRT_W, MIPS_INS_FRSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSAF_D, MIPS_INS_FSAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSAF_W, MIPS_INS_FSAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSEQ_D, MIPS_INS_FSEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSEQ_W, MIPS_INS_FSEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSLE_D, MIPS_INS_FSLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSLE_W, MIPS_INS_FSLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSLT_D, MIPS_INS_FSLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSLT_W, MIPS_INS_FSLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSNE_D, MIPS_INS_FSNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSNE_W, MIPS_INS_FSNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSOR_D, MIPS_INS_FSOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSOR_W, MIPS_INS_FSOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSQRT_D, MIPS_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSQRT_D32, MIPS_INS_SQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FSQRT_D64, MIPS_INS_SQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FSQRT_MM, MIPS_INS_SQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FSQRT_S, MIPS_INS_SQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_FSQRT_S_MM, MIPS_INS_SQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FSQRT_W, MIPS_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUB_D, MIPS_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUB_D32, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_FSUB_D64, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_FSUB_MM, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FSUB_S, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_FSUB_S_MM, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_FSUB_W, MIPS_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUEQ_D, MIPS_INS_FSUEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUEQ_W, MIPS_INS_FSUEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSULE_D, MIPS_INS_FSULE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSULE_W, MIPS_INS_FSULE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSULT_D, MIPS_INS_FSULT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSULT_W, MIPS_INS_FSULT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUNE_D, MIPS_INS_FSUNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUNE_W, MIPS_INS_FSUNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUN_D, MIPS_INS_FSUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FSUN_W, MIPS_INS_FSUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTINT_S_D, MIPS_INS_FTINT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTINT_S_W, MIPS_INS_FTINT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTINT_U_D, MIPS_INS_FTINT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTINT_U_W, MIPS_INS_FTINT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTQ_H, MIPS_INS_FTQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTQ_W, MIPS_INS_FTQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HADD_S_D, MIPS_INS_HADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HADD_S_H, MIPS_INS_HADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HADD_S_W, MIPS_INS_HADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HADD_U_D, MIPS_INS_HADD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HADD_U_H, MIPS_INS_HADD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HADD_U_W, MIPS_INS_HADD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HSUB_S_D, MIPS_INS_HSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HSUB_S_H, MIPS_INS_HSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HSUB_S_W, MIPS_INS_HSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HSUB_U_D, MIPS_INS_HSUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HSUB_U_H, MIPS_INS_HSUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_HSUB_U_W, MIPS_INS_HSUB_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVEV_B, MIPS_INS_ILVEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVEV_D, MIPS_INS_ILVEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVEV_H, MIPS_INS_ILVEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVEV_W, MIPS_INS_ILVEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVL_B, MIPS_INS_ILVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVL_D, MIPS_INS_ILVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVL_H, MIPS_INS_ILVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVL_W, MIPS_INS_ILVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVOD_B, MIPS_INS_ILVOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVOD_D, MIPS_INS_ILVOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVOD_H, MIPS_INS_ILVOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVOD_W, MIPS_INS_ILVOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVR_B, MIPS_INS_ILVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVR_D, MIPS_INS_ILVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVR_H, MIPS_INS_ILVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ILVR_W, MIPS_INS_ILVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INS, MIPS_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_INSERT_B, MIPS_INS_INSERT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INSERT_D, MIPS_INS_INSERT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_INSERT_H, MIPS_INS_INSERT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INSERT_W, MIPS_INS_INSERT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INSV, MIPS_INS_INSV, #ifndef CAPSTONE_DIET { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_INSVE_B, MIPS_INS_INSVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INSVE_D, MIPS_INS_INSVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INSVE_H, MIPS_INS_INSVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INSVE_W, MIPS_INS_INSVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_INS_MM, MIPS_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_J, MIPS_INS_J, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 #endif }, { Mips_JAL, MIPS_INS_JAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_JALR, MIPS_INS_JALR, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_JALR16_MM, MIPS_INS_JALR, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_JALR64, MIPS_INS_JALR, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_JALRS16_MM, MIPS_INS_JALRS16, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_JALRS_MM, MIPS_INS_JALRS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_JALR_HB, MIPS_INS_JALR_HB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1 #endif }, { Mips_JALR_MM, MIPS_INS_JALR, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_JALS_MM, MIPS_INS_JALS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_JALX, MIPS_INS_JALX, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_JALX_MM, MIPS_INS_JALX, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_JAL_MM, MIPS_INS_JAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_JIALC, MIPS_INS_JIALC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_JIC, MIPS_INS_JIC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_JR, MIPS_INS_JR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 #endif }, { Mips_JR16_MM, MIPS_INS_JR16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 #endif }, { Mips_JR64, MIPS_INS_JR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 #endif }, { Mips_JRADDIUSP, MIPS_INS_JRADDIUSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 #endif }, { Mips_JRC16_MM, MIPS_INS_JRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 #endif }, { Mips_JR_HB, MIPS_INS_JR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1 #endif }, { Mips_JR_HB_R6, MIPS_INS_JR_HB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1 #endif }, { Mips_JR_MM, MIPS_INS_JR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 #endif }, { Mips_J_MM, MIPS_INS_J, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_Jal16, MIPS_INS_JAL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_JrRa16, MIPS_INS_JR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 #endif }, { Mips_JrcRa16, MIPS_INS_JRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 #endif }, { Mips_JrcRx16, MIPS_INS_JRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 #endif }, { Mips_JumpLinkReg16, MIPS_INS_JALRC, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0 #endif }, { Mips_LB, MIPS_INS_LB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LB64, MIPS_INS_LB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LBU16_MM, MIPS_INS_LBU16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LBUX, MIPS_INS_LBUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_LB_MM, MIPS_INS_LB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LBu, MIPS_INS_LBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LBu64, MIPS_INS_LBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LBu_MM, MIPS_INS_LBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LD, MIPS_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_LDC1, MIPS_INS_LDC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_LDC164, MIPS_INS_LDC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_LDC1_MM, MIPS_INS_LDC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LDC2, MIPS_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LDC2_R6, MIPS_INS_LDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LDC3, MIPS_INS_LDC3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LDI_B, MIPS_INS_LDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LDI_D, MIPS_INS_LDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LDI_H, MIPS_INS_LDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LDI_W, MIPS_INS_LDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LDL, MIPS_INS_LDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_LDPC, MIPS_INS_LDPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 #endif }, { Mips_LDR, MIPS_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_LDXC1, MIPS_INS_LDXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 #endif }, { Mips_LDXC164, MIPS_INS_LDXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_LD_B, MIPS_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LD_D, MIPS_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LD_H, MIPS_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LD_W, MIPS_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LEA_ADDiu, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LEA_ADDiu64, MIPS_INS_DADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LH, MIPS_INS_LH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LH64, MIPS_INS_LH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LHU16_MM, MIPS_INS_LHU16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LHX, MIPS_INS_LHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_LH_MM, MIPS_INS_LH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LHu, MIPS_INS_LHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LHu64, MIPS_INS_LHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LHu_MM, MIPS_INS_LHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LI16_MM, MIPS_INS_LI16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LL, MIPS_INS_LL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LLD, MIPS_INS_LLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_LLD_R6, MIPS_INS_LLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LL_MM, MIPS_INS_LL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LL_R6, MIPS_INS_LL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LSA, MIPS_INS_LSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_LSA_R6, MIPS_INS_LSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LUXC1, MIPS_INS_LUXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 #endif }, { Mips_LUXC164, MIPS_INS_LUXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_LUXC1_MM, MIPS_INS_LUXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LUi, MIPS_INS_LUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LUi64, MIPS_INS_LUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LUi_MM, MIPS_INS_LUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LW, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LW16_MM, MIPS_INS_LW16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LW64, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LWC1, MIPS_INS_LWC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LWC1_MM, MIPS_INS_LWC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWC2, MIPS_INS_LWC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWC2_R6, MIPS_INS_LWC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LWC3, MIPS_INS_LWC3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWGP_MM, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWL, MIPS_INS_LWL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWL64, MIPS_INS_LWL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LWL_MM, MIPS_INS_LWL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWM16_MM, MIPS_INS_LWM16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWM32_MM, MIPS_INS_LWM32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWPC, MIPS_INS_LWPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LWP_MM, MIPS_INS_LWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWR, MIPS_INS_LWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWR64, MIPS_INS_LWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_LWR_MM, MIPS_INS_LWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWSP_MM, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWUPC, MIPS_INS_LWUPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_LWU_MM, MIPS_INS_LWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWX, MIPS_INS_LWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_LWXC1, MIPS_INS_LWXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 #endif }, { Mips_LWXC1_MM, MIPS_INS_LWXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWXS_MM, MIPS_INS_LWXS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LW_MM, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_LWu, MIPS_INS_LWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_LbRxRyOffMemX16, MIPS_INS_LB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LhRxRyOffMemX16, MIPS_INS_LH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LiRxImm16, MIPS_INS_LI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LiRxImmX16, MIPS_INS_LI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LwRxPcTcp16, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LwRxPcTcpX16, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LwRxRyOffMemX16, MIPS_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_LwRxSpImmX16, MIPS_INS_LW, #ifndef CAPSTONE_DIET { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_MADD, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MADDF_D, MIPS_INS_MADDF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MADDF_S, MIPS_INS_MADDF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADDU, MIPS_INS_MADDU, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MADDU_DSP, MIPS_INS_MADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MADDU_MM, MIPS_INS_MADDU, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MADDV_B, MIPS_INS_MADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADDV_D, MIPS_INS_MADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADDV_H, MIPS_INS_MADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADDV_W, MIPS_INS_MADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADD_D32, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MADD_D32_MM, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MADD_D64, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MADD_DSP, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MADD_MM, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MADD_Q_H, MIPS_INS_MADD_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADD_Q_W, MIPS_INS_MADD_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MADD_S, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MADD_S_MM, MIPS_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MAXA_D, MIPS_INS_MAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MAXA_S, MIPS_INS_MAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MAXI_S_B, MIPS_INS_MAXI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_S_D, MIPS_INS_MAXI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_S_H, MIPS_INS_MAXI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_S_W, MIPS_INS_MAXI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_U_B, MIPS_INS_MAXI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_U_D, MIPS_INS_MAXI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_U_H, MIPS_INS_MAXI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAXI_U_W, MIPS_INS_MAXI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_A_B, MIPS_INS_MAX_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_A_D, MIPS_INS_MAX_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_A_H, MIPS_INS_MAX_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_A_W, MIPS_INS_MAX_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_D, MIPS_INS_MAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MAX_S, MIPS_INS_MAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MAX_S_B, MIPS_INS_MAX_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_S_D, MIPS_INS_MAX_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_S_H, MIPS_INS_MAX_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_S_W, MIPS_INS_MAX_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_U_B, MIPS_INS_MAX_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_U_D, MIPS_INS_MAX_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_U_H, MIPS_INS_MAX_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MAX_U_W, MIPS_INS_MAX_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MFC0, MIPS_INS_MFC0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 #endif }, { Mips_MFC1, MIPS_INS_MFC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_MFC1_MM, MIPS_INS_MFC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFC2, MIPS_INS_MFC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_MFHC1_D32, MIPS_INS_MFHC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_MFHC1_D64, MIPS_INS_MFHC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_MFHC1_MM, MIPS_INS_MFHC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFHI, MIPS_INS_MFHI, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFHI16_MM, MIPS_INS_MFHI, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFHI64, MIPS_INS_MFHI, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MFHI_DSP, MIPS_INS_MFHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MFHI_MM, MIPS_INS_MFHI, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFLO, MIPS_INS_MFLO, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFLO16_MM, MIPS_INS_MFLO, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MFLO64, MIPS_INS_MFLO, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MFLO_DSP, MIPS_INS_MFLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MFLO_MM, MIPS_INS_MFLO, #ifndef CAPSTONE_DIET { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MINA_D, MIPS_INS_MINA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MINA_S, MIPS_INS_MINA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MINI_S_B, MIPS_INS_MINI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_S_D, MIPS_INS_MINI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_S_H, MIPS_INS_MINI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_S_W, MIPS_INS_MINI_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_U_B, MIPS_INS_MINI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_U_D, MIPS_INS_MINI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_U_H, MIPS_INS_MINI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MINI_U_W, MIPS_INS_MINI_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_A_B, MIPS_INS_MIN_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_A_D, MIPS_INS_MIN_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_A_H, MIPS_INS_MIN_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_A_W, MIPS_INS_MIN_A, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_D, MIPS_INS_MIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MIN_S, MIPS_INS_MIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MIN_S_B, MIPS_INS_MIN_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_S_D, MIPS_INS_MIN_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_S_H, MIPS_INS_MIN_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_S_W, MIPS_INS_MIN_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_U_B, MIPS_INS_MIN_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_U_D, MIPS_INS_MIN_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_U_H, MIPS_INS_MIN_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MIN_U_W, MIPS_INS_MIN_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD, MIPS_INS_MOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MODSUB, MIPS_INS_MODSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MODU, MIPS_INS_MODU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MOD_S_B, MIPS_INS_MOD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_S_D, MIPS_INS_MOD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_S_H, MIPS_INS_MOD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_S_W, MIPS_INS_MOD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_U_B, MIPS_INS_MOD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_U_D, MIPS_INS_MOD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_U_H, MIPS_INS_MOD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOD_U_W, MIPS_INS_MOD_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOVE16_MM, MIPS_INS_MOVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVEP_MM, MIPS_INS_MOVEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVE_V, MIPS_INS_MOVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MOVF_D32, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVF_D32_MM, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVF_D64, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVF_I, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVF_I64, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 #endif }, { Mips_MOVF_I_MM, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVF_S, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVF_S_MM, MIPS_INS_MOVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVN_I64_D64, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I64_I, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I64_I64, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I64_S, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 #endif }, { Mips_MOVN_I_D32, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVN_I_D64, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I_I, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I_I64, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I_MM, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVN_I_S, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVN_I_S_MM, MIPS_INS_MOVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVT_D32, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVT_D32_MM, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVT_D64, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVT_I, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVT_I64, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 #endif }, { Mips_MOVT_I_MM, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVT_S, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVT_S_MM, MIPS_INS_MOVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I64_I, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I64_S, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_D32, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_D64, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_I, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_I64, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_MM, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_S, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MSUB, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MSUBF_D, MIPS_INS_MSUBF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MSUBF_S, MIPS_INS_MSUBF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUBU, MIPS_INS_MSUBU, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MSUBU_DSP, MIPS_INS_MSUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MSUBU_MM, MIPS_INS_MSUBU, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MSUBV_B, MIPS_INS_MSUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUBV_D, MIPS_INS_MSUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUBV_H, MIPS_INS_MSUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUBV_W, MIPS_INS_MSUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUB_D32, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MSUB_D32_MM, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MSUB_D64, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MSUB_DSP, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MSUB_MM, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MSUB_S, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MSUB_S_MM, MIPS_INS_MSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MTC0, MIPS_INS_MTC0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 #endif }, { Mips_MTC1, MIPS_INS_MTC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_MTC1_MM, MIPS_INS_MTC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MTC2, MIPS_INS_MTC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_MTHC1_D32, MIPS_INS_MTHC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_MTHC1_D64, MIPS_INS_MTHC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_MTHC1_MM, MIPS_INS_MTHC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MTHI, MIPS_INS_MTHI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MTHI64, MIPS_INS_MTHI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MTHI_DSP, MIPS_INS_MTHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MTHI_MM, MIPS_INS_MTHI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MTHLIP, MIPS_INS_MTHLIP, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MTLO, MIPS_INS_MTLO, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MTLO64, MIPS_INS_MTLO, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MTLO_DSP, MIPS_INS_MTLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MTLO_MM, MIPS_INS_MTLO, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MTM0, MIPS_INS_MTM0, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_MTM1, MIPS_INS_MTM1, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_MTM2, MIPS_INS_MTM2, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_MTP0, MIPS_INS_MTP0, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_MTP1, MIPS_INS_MTP1, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_MTP2, MIPS_INS_MTP2, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_MUH, MIPS_INS_MUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MUHU, MIPS_INS_MUHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MUL, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_MULQ_S_PH, MIPS_INS_MULQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_MULQ_S_W, MIPS_INS_MULQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_MULR_Q_H, MIPS_INS_MULR_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MULR_Q_W, MIPS_INS_MULR_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULSA_W_PH, MIPS_INS_MULSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_MULT, MIPS_INS_MULT, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MULTU_DSP, MIPS_INS_MULTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULT_DSP, MIPS_INS_MULT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_MULT_MM, MIPS_INS_MULT, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MULTu, MIPS_INS_MULTU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_MULTu_MM, MIPS_INS_MULTU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MULU, MIPS_INS_MULU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MULV_B, MIPS_INS_MULV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MULV_D, MIPS_INS_MULV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MULV_H, MIPS_INS_MULV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MULV_W, MIPS_INS_MULV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MUL_MM, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_MUL_PH, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_MUL_Q_H, MIPS_INS_MUL_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MUL_Q_W, MIPS_INS_MUL_Q, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_MUL_R6, MIPS_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_MUL_S_PH, MIPS_INS_MUL_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_Mfhi16, MIPS_INS_MFHI, #ifndef CAPSTONE_DIET { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_Mflo16, MIPS_INS_MFLO, #ifndef CAPSTONE_DIET { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_Move32R16, MIPS_INS_MOVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_MoveR3216, MIPS_INS_MOVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_NLOC_B, MIPS_INS_NLOC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLOC_D, MIPS_INS_NLOC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLOC_H, MIPS_INS_NLOC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLOC_W, MIPS_INS_NLOC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLZC_B, MIPS_INS_NLZC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLZC_D, MIPS_INS_NLZC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLZC_H, MIPS_INS_NLZC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NLZC_W, MIPS_INS_NLZC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NMADD_D32, MIPS_INS_NMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 #endif }, { Mips_NMADD_D32_MM, MIPS_INS_NMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_NMADD_D64, MIPS_INS_NMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 #endif }, { Mips_NMADD_S, MIPS_INS_NMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 #endif }, { Mips_NMADD_S_MM, MIPS_INS_NMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_NMSUB_D32, MIPS_INS_NMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 #endif }, { Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_NMSUB_D64, MIPS_INS_NMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 #endif }, { Mips_NMSUB_S, MIPS_INS_NMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 #endif }, { Mips_NMSUB_S_MM, MIPS_INS_NMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_NOR, MIPS_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_NOR64, MIPS_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_NORI_B, MIPS_INS_NORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NOR_MM, MIPS_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_NOR_V, MIPS_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_NOT16_MM, MIPS_INS_NOT16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_NegRxRy16, MIPS_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_NotRxRy16, MIPS_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_OR, MIPS_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_OR16_MM, MIPS_INS_OR16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_OR64, MIPS_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ORI_B, MIPS_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_OR_MM, MIPS_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_OR_V, MIPS_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ORi, MIPS_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ORi64, MIPS_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_ORi_MM, MIPS_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_OrRxRxRy16, MIPS_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_PACKRL_PH, MIPS_INS_PACKRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PAUSE, MIPS_INS_PAUSE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_PAUSE_MM, MIPS_INS_PAUSE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_PCKEV_B, MIPS_INS_PCKEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKEV_D, MIPS_INS_PCKEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKEV_H, MIPS_INS_PCKEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKEV_W, MIPS_INS_PCKEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKOD_B, MIPS_INS_PCKOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKOD_D, MIPS_INS_PCKOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKOD_H, MIPS_INS_PCKOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCKOD_W, MIPS_INS_PCKOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCNT_B, MIPS_INS_PCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCNT_D, MIPS_INS_PCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCNT_H, MIPS_INS_PCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PCNT_W, MIPS_INS_PCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_PICK_PH, MIPS_INS_PICK, #ifndef CAPSTONE_DIET { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PICK_QB, MIPS_INS_PICK, #ifndef CAPSTONE_DIET { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_POP, MIPS_INS_POP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_PRECR_QB_PH, MIPS_INS_PRECR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_PREF, MIPS_INS_PREF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_PREF_MM, MIPS_INS_PREF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_PREF_R6, MIPS_INS_PREF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_PREPEND, MIPS_INS_PREPEND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_RADDU_W_QB, MIPS_INS_RADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_RDDSP, MIPS_INS_RDDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_RDHWR, MIPS_INS_RDHWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_RDHWR64, MIPS_INS_RDHWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_RDHWR_MM, MIPS_INS_RDHWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_REPLV_PH, MIPS_INS_REPLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_REPLV_QB, MIPS_INS_REPLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_REPL_PH, MIPS_INS_REPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_REPL_QB, MIPS_INS_REPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_RINT_D, MIPS_INS_RINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_RINT_S, MIPS_INS_RINT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_ROTR, MIPS_INS_ROTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_ROTRV, MIPS_INS_ROTRV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_ROTRV_MM, MIPS_INS_ROTRV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ROTR_MM, MIPS_INS_ROTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ROUND_L_D64, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_ROUND_L_S, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_ROUND_W_D32, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_ROUND_W_D64, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_ROUND_W_MM, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ROUND_W_S, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_ROUND_W_S_MM, MIPS_INS_ROUND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SAT_S_B, MIPS_INS_SAT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_S_D, MIPS_INS_SAT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_S_H, MIPS_INS_SAT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_S_W, MIPS_INS_SAT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_U_B, MIPS_INS_SAT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_U_D, MIPS_INS_SAT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_U_H, MIPS_INS_SAT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SAT_U_W, MIPS_INS_SAT_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SB, MIPS_INS_SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SB16_MM, MIPS_INS_SB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SB64, MIPS_INS_SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SB_MM, MIPS_INS_SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SC, MIPS_INS_SC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SCD, MIPS_INS_SCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SCD_R6, MIPS_INS_SCD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SC_MM, MIPS_INS_SC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SC_R6, MIPS_INS_SC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SD, MIPS_INS_SD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 #endif }, { Mips_SDBBP, MIPS_INS_SDBBP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SDBBP16_MM, MIPS_INS_SDBBP16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SDBBP_MM, MIPS_INS_SDBBP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SDBBP_R6, MIPS_INS_SDBBP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SDC1, MIPS_INS_SDC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_SDC164, MIPS_INS_SDC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_SDC1_MM, MIPS_INS_SDC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SDC2, MIPS_INS_SDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SDC2_R6, MIPS_INS_SDC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SDC3, MIPS_INS_SDC3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SDIV, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SDIV_MM, MIPS_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SDL, MIPS_INS_SDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SDR, MIPS_INS_SDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SDXC1, MIPS_INS_SDXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 #endif }, { Mips_SDXC164, MIPS_INS_SDXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SEB, MIPS_INS_SEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_SEB64, MIPS_INS_SEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_SEB_MM, MIPS_INS_SEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SEH, MIPS_INS_SEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_SEH64, MIPS_INS_SEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_SEH_MM, MIPS_INS_SEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SELEQZ, MIPS_INS_SELEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELEQZ64, MIPS_INS_SELEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELEQZ_D, MIPS_INS_SELEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELEQZ_S, MIPS_INS_SELEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELNEZ, MIPS_INS_SELNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELNEZ64, MIPS_INS_SELNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELNEZ_D, MIPS_INS_SELNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SELNEZ_S, MIPS_INS_SELNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SEL_D, MIPS_INS_SEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SEL_S, MIPS_INS_SEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SEQ, MIPS_INS_SEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_SEQi, MIPS_INS_SEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_SH, MIPS_INS_SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SH16_MM, MIPS_INS_SH16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SH64, MIPS_INS_SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SHF_B, MIPS_INS_SHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SHF_H, MIPS_INS_SHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SHF_W, MIPS_INS_SHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SHILO, MIPS_INS_SHILO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHILOV, MIPS_INS_SHILOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLLV_PH, MIPS_INS_SHLLV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLLV_QB, MIPS_INS_SHLLV, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLL_PH, MIPS_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLL_QB, MIPS_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLL_S_PH, MIPS_INS_SHLL_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHLL_S_W, MIPS_INS_SHLL_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRAV_PH, MIPS_INS_SHRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRAV_QB, MIPS_INS_SHRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRA_PH, MIPS_INS_SHRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRA_QB, MIPS_INS_SHRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SHRA_R_PH, MIPS_INS_SHRA_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRA_R_QB, MIPS_INS_SHRA_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SHRA_R_W, MIPS_INS_SHRA_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRLV_PH, MIPS_INS_SHRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SHRLV_QB, MIPS_INS_SHRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SHRL_PH, MIPS_INS_SHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SHRL_QB, MIPS_INS_SHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SH_MM, MIPS_INS_SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLDI_B, MIPS_INS_SLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLDI_D, MIPS_INS_SLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLDI_H, MIPS_INS_SLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLDI_W, MIPS_INS_SLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLD_B, MIPS_INS_SLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLD_D, MIPS_INS_SLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLD_H, MIPS_INS_SLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLD_W, MIPS_INS_SLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLL, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLL16_MM, MIPS_INS_SLL16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLL64_32, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLL64_64, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLLI_B, MIPS_INS_SLLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLLI_D, MIPS_INS_SLLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLLI_H, MIPS_INS_SLLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLLI_W, MIPS_INS_SLLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLLV, MIPS_INS_SLLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLLV_MM, MIPS_INS_SLLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLL_B, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLL_D, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLL_H, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLL_MM, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLL_W, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SLT, MIPS_INS_SLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLT64, MIPS_INS_SLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLT_MM, MIPS_INS_SLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLTi, MIPS_INS_SLTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLTi64, MIPS_INS_SLTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLTi_MM, MIPS_INS_SLTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLTiu, MIPS_INS_SLTIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLTiu64, MIPS_INS_SLTIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLTiu_MM, MIPS_INS_SLTIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SLTu, MIPS_INS_SLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLTu64, MIPS_INS_SLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SLTu_MM, MIPS_INS_SLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SNE, MIPS_INS_SNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_SNEi, MIPS_INS_SNEI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_SPLATI_B, MIPS_INS_SPLATI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLATI_D, MIPS_INS_SPLATI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLATI_H, MIPS_INS_SPLATI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLATI_W, MIPS_INS_SPLATI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLAT_B, MIPS_INS_SPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLAT_D, MIPS_INS_SPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLAT_H, MIPS_INS_SPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SPLAT_W, MIPS_INS_SPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRA, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SRAI_B, MIPS_INS_SRAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAI_D, MIPS_INS_SRAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAI_H, MIPS_INS_SRAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAI_W, MIPS_INS_SRAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRARI_B, MIPS_INS_SRARI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRARI_D, MIPS_INS_SRARI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRARI_H, MIPS_INS_SRARI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRARI_W, MIPS_INS_SRARI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAR_B, MIPS_INS_SRAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAR_D, MIPS_INS_SRAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAR_H, MIPS_INS_SRAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAR_W, MIPS_INS_SRAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRAV, MIPS_INS_SRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SRAV_MM, MIPS_INS_SRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SRA_B, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRA_D, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRA_H, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRA_MM, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SRA_W, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRL, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SRL16_MM, MIPS_INS_SRL16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SRLI_B, MIPS_INS_SRLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLI_D, MIPS_INS_SRLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLI_H, MIPS_INS_SRLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLI_W, MIPS_INS_SRLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLRI_B, MIPS_INS_SRLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLRI_D, MIPS_INS_SRLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLRI_H, MIPS_INS_SRLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLRI_W, MIPS_INS_SRLRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLR_B, MIPS_INS_SRLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLR_D, MIPS_INS_SRLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLR_H, MIPS_INS_SRLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLR_W, MIPS_INS_SRLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRLV, MIPS_INS_SRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SRLV_MM, MIPS_INS_SRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SRL_B, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRL_D, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRL_H, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SRL_MM, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SRL_W, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SSNOP, MIPS_INS_SSNOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SSNOP_MM, MIPS_INS_SSNOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_ST_B, MIPS_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ST_D, MIPS_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ST_H, MIPS_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_ST_W, MIPS_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUB, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SUBQH_PH, MIPS_INS_SUBQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBQH_W, MIPS_INS_SUBQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBQ_PH, MIPS_INS_SUBQ, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_S_B, MIPS_INS_SUBS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_S_D, MIPS_INS_SUBS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_S_H, MIPS_INS_SUBS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_S_W, MIPS_INS_SUBS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_U_B, MIPS_INS_SUBS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_U_D, MIPS_INS_SUBS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_U_H, MIPS_INS_SUBS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBS_U_W, MIPS_INS_SUBS_U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBU16_MM, MIPS_INS_SUBU16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SUBUH_QB, MIPS_INS_SUBUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBU_PH, MIPS_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBU_QB, MIPS_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SUBU_S_PH, MIPS_INS_SUBU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 #endif }, { Mips_SUBU_S_QB, MIPS_INS_SUBU_S, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_SUBVI_B, MIPS_INS_SUBVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBVI_D, MIPS_INS_SUBVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBVI_H, MIPS_INS_SUBVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBVI_W, MIPS_INS_SUBVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBV_B, MIPS_INS_SUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBV_D, MIPS_INS_SUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBV_H, MIPS_INS_SUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUBV_W, MIPS_INS_SUBV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_SUB_MM, MIPS_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SUBu, MIPS_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SUBu_MM, MIPS_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SUXC1, MIPS_INS_SUXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 #endif }, { Mips_SUXC164, MIPS_INS_SUXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_SUXC1_MM, MIPS_INS_SUXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SW, MIPS_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SW16_MM, MIPS_INS_SW16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SW64, MIPS_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SWC1, MIPS_INS_SWC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SWC1_MM, MIPS_INS_SWC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWC2, MIPS_INS_SWC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWC2_R6, MIPS_INS_SWC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 #endif }, { Mips_SWC3, MIPS_INS_SWC3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWL, MIPS_INS_SWL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWL64, MIPS_INS_SWL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SWL_MM, MIPS_INS_SWL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWM16_MM, MIPS_INS_SWM16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWM32_MM, MIPS_INS_SWM32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWP_MM, MIPS_INS_SWP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWR, MIPS_INS_SWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWR64, MIPS_INS_SWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_SWR_MM, MIPS_INS_SWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWSP_MM, MIPS_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SWXC1, MIPS_INS_SWXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 #endif }, { Mips_SWXC1_MM, MIPS_INS_SWXC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SW_MM, MIPS_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SYNC, MIPS_INS_SYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 #endif }, { Mips_SYNCI, MIPS_INS_SYNCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_SYNC_MM, MIPS_INS_SYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_SYSCALL, MIPS_INS_SYSCALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0 #endif }, { Mips_SYSCALL_MM, MIPS_INS_SYSCALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0 #endif }, { Mips_SbRxRyOffMemX16, MIPS_INS_SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SebRx16, MIPS_INS_SEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SehRx16, MIPS_INS_SEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_ShRxRyOffMemX16, MIPS_INS_SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SllX16, MIPS_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SllvRxRy16, MIPS_INS_SLLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SltRxRy16, MIPS_INS_SLT, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SltiRxImm16, MIPS_INS_SLTI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SltiRxImmX16, MIPS_INS_SLTI, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SltiuRxImm16, MIPS_INS_SLTIU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SltiuRxImmX16, MIPS_INS_SLTIU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SltuRxRy16, MIPS_INS_SLTU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SraX16, MIPS_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SravRxRy16, MIPS_INS_SRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SrlX16, MIPS_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SrlvRxRy16, MIPS_INS_SRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SubuRxRyRz16, MIPS_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SwRxRyOffMemX16, MIPS_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_SwRxSpImmX16, MIPS_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, { Mips_TEQ, MIPS_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TEQI, MIPS_INS_TEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_TEQI_MM, MIPS_INS_TEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TEQ_MM, MIPS_INS_TEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TGE, MIPS_INS_TGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TGEI, MIPS_INS_TGEI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_TGEIU, MIPS_INS_TGEIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_TGEIU_MM, MIPS_INS_TGEIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TGEI_MM, MIPS_INS_TGEI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TGEU, MIPS_INS_TGEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TGEU_MM, MIPS_INS_TGEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TGE_MM, MIPS_INS_TGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLBP, MIPS_INS_TLBP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_TLBP_MM, MIPS_INS_TLBP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLBR, MIPS_INS_TLBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_TLBR_MM, MIPS_INS_TLBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLBWI, MIPS_INS_TLBWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_TLBWI_MM, MIPS_INS_TLBWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLBWR, MIPS_INS_TLBWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_TLBWR_MM, MIPS_INS_TLBWR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLT, MIPS_INS_TLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TLTI, MIPS_INS_TLTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_TLTIU_MM, MIPS_INS_TLTIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLTI_MM, MIPS_INS_TLTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLTU, MIPS_INS_TLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TLTU_MM, MIPS_INS_TLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TLT_MM, MIPS_INS_TLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TNE, MIPS_INS_TNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TNEI, MIPS_INS_TNEI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_TNEI_MM, MIPS_INS_TNEI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TNE_MM, MIPS_INS_TNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TRUNC_L_D64, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_TRUNC_L_S, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_TRUNC_W_D32, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 #endif }, { Mips_TRUNC_W_D64, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 #endif }, { Mips_TRUNC_W_MM, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TRUNC_W_S, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 #endif }, { Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_TTLTIU, MIPS_INS_TLTIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_UDIV, MIPS_INS_DIVU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 #endif }, { Mips_UDIV_MM, MIPS_INS_DIVU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_V3MULU, MIPS_INS_V3MULU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_VMM0, MIPS_INS_VMM0, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_VMULU, MIPS_INS_VMULU, #ifndef CAPSTONE_DIET { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 #endif }, { Mips_VSHF_B, MIPS_INS_VSHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_VSHF_D, MIPS_INS_VSHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_VSHF_H, MIPS_INS_VSHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_VSHF_W, MIPS_INS_VSHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_WAIT, MIPS_INS_WAIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_WAIT_MM, MIPS_INS_WAIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_WRDSP, MIPS_INS_WRDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 #endif }, { Mips_WSBH, MIPS_INS_WSBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 #endif }, { Mips_WSBH_MM, MIPS_INS_WSBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_XOR, MIPS_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 #endif }, { Mips_XOR16_MM, MIPS_INS_XOR16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_XOR64, MIPS_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_XORI_B, MIPS_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_XOR_MM, MIPS_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_XOR_V, MIPS_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 #endif }, { Mips_XORi, MIPS_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_XORi64, MIPS_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 #endif }, { Mips_XORi_MM, MIPS_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 #endif }, { Mips_XorRxRxRy16, MIPS_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/Mips/MipsModule.c000064400000000000000000000020000072674642500202420ustar 00000000000000/* Capstone Disassembly Engine */ /* By Dang Hoang Vu 2013 */ #ifdef CAPSTONE_HAS_MIPS #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "MipsDisassembler.h" #include "MipsInstPrinter.h" #include "MipsMapping.h" #include "MipsModule.h" // Returns mode value with implied bits set static cs_mode updated_mode(cs_mode mode) { if (mode & CS_MODE_MIPS32R6) { mode |= CS_MODE_32; } return mode; } cs_err Mips_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); Mips_init(mri); ud->printer = Mips_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->reg_name = Mips_reg_name; ud->insn_id = Mips_get_insn_id; ud->insn_name = Mips_insn_name; ud->group_name = Mips_group_name; ud->disasm = Mips_getInstruction; return CS_ERR_OK; } cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_MODE) { handle->mode = updated_mode(value); return CS_ERR_OK; } return CS_ERR_OPTION; } #endif capstone-sys-0.15.0/capstone/arch/Mips/MipsModule.h000064400000000000000000000004350072674642500202610ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_MIPS_MODULE_H #define CS_MIPS_MODULE_H #include "../../utils.h" cs_err Mips_global_init(cs_struct *ud); cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCDisassembler.c000064400000000000000000000417420072674642500215730ustar 00000000000000//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_POWERPC #include // DEBUG #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "PPCDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" #define GET_REGINFO_ENUM #include "PPCGenRegisterInfo.inc" // FIXME: These can be generated by TableGen from the existing register // encoding values! static const unsigned CRRegs[] = { PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3, PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7 }; static const unsigned CRBITRegs[] = { PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN }; static const unsigned FRegs[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F14, PPC_F15, PPC_F16, PPC_F17, PPC_F18, PPC_F19, PPC_F20, PPC_F21, PPC_F22, PPC_F23, PPC_F24, PPC_F25, PPC_F26, PPC_F27, PPC_F28, PPC_F29, PPC_F30, PPC_F31 }; static const unsigned VFRegs[] = { PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 }; static const unsigned VRegs[] = { PPC_V0, PPC_V1, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V20, PPC_V21, PPC_V22, PPC_V23, PPC_V24, PPC_V25, PPC_V26, PPC_V27, PPC_V28, PPC_V29, PPC_V30, PPC_V31 }; static const unsigned VSRegs[] = { PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15, PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19, PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23, PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27, PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31, PPC_V0, PPC_V1, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V20, PPC_V21, PPC_V22, PPC_V23, PPC_V24, PPC_V25, PPC_V26, PPC_V27, PPC_V28, PPC_V29, PPC_V30, PPC_V31 }; static const unsigned VSFRegs[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F14, PPC_F15, PPC_F16, PPC_F17, PPC_F18, PPC_F19, PPC_F20, PPC_F21, PPC_F22, PPC_F23, PPC_F24, PPC_F25, PPC_F26, PPC_F27, PPC_F28, PPC_F29, PPC_F30, PPC_F31, PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 }; static const unsigned VSSRegs[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F14, PPC_F15, PPC_F16, PPC_F17, PPC_F18, PPC_F19, PPC_F20, PPC_F21, PPC_F22, PPC_F23, PPC_F24, PPC_F25, PPC_F26, PPC_F27, PPC_F28, PPC_F29, PPC_F30, PPC_F31, PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 }; static const unsigned GPRegs[] = { PPC_R0, PPC_R1, PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R13, PPC_R14, PPC_R15, PPC_R16, PPC_R17, PPC_R18, PPC_R19, PPC_R20, PPC_R21, PPC_R22, PPC_R23, PPC_R24, PPC_R25, PPC_R26, PPC_R27, PPC_R28, PPC_R29, PPC_R30, PPC_R31 }; static const unsigned GP0Regs[] = { PPC_ZERO, PPC_R1, PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R13, PPC_R14, PPC_R15, PPC_R16, PPC_R17, PPC_R18, PPC_R19, PPC_R20, PPC_R21, PPC_R22, PPC_R23, PPC_R24, PPC_R25, PPC_R26, PPC_R27, PPC_R28, PPC_R29, PPC_R30, PPC_R31 }; static const unsigned G8Regs[] = { PPC_X0, PPC_X1, PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X13, PPC_X14, PPC_X15, PPC_X16, PPC_X17, PPC_X18, PPC_X19, PPC_X20, PPC_X21, PPC_X22, PPC_X23, PPC_X24, PPC_X25, PPC_X26, PPC_X27, PPC_X28, PPC_X29, PPC_X30, PPC_X31 }; static const unsigned G80Regs[] = { PPC_ZERO8, PPC_X1, PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X13, PPC_X14, PPC_X15, PPC_X16, PPC_X17, PPC_X18, PPC_X19, PPC_X20, PPC_X21, PPC_X22, PPC_X23, PPC_X24, PPC_X25, PPC_X26, PPC_X27, PPC_X28, PPC_X29, PPC_X30, PPC_X31 }; static const unsigned QFRegs[] = { PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15, PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23, PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27, PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31 }; static const unsigned SPERegs[] = { PPC_S0, PPC_S1, PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S13, PPC_S14, PPC_S15, PPC_S16, PPC_S17, PPC_S18, PPC_S19, PPC_S20, PPC_S21, PPC_S22, PPC_S23, PPC_S24, PPC_S25, PPC_S26, PPC_S27, PPC_S28, PPC_S29, PPC_S30, PPC_S31 }; #if 0 static uint64_t getFeatureBits(int feature) { // enable all features return (uint64_t)-1; } #endif static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs, size_t RegsLen) { if (RegNo >= RegsLen / sizeof(unsigned)) { return MCDisassembler_Fail; } MCOperand_CreateReg0(Inst, Regs[RegNo]); return MCDisassembler_Success; } static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs)); } static DecodeStatus DecodeCRRC0RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs)); } static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, CRBITRegs, sizeof(CRBITRegs)); } static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs)); } static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs)); } static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VFRegs, sizeof(VFRegs)); } static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VRegs, sizeof(VRegs)); } static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSRegs, sizeof(VSRegs)); } static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSFRegs, sizeof(VSFRegs)); } static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, VSSRegs, sizeof(VSSRegs)); } static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs)); } static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, GP0Regs, sizeof(GP0Regs)); } static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, G8Regs, sizeof(G8Regs)); } static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, G80Regs, sizeof(G80Regs)); } #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, QFRegs, sizeof(QFRegs)); } static DecodeStatus DecodeSPE4RCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs)); } static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SPERegs, sizeof(SPERegs)); } #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { //assert(isUInt(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, Imm); return MCDisassembler_Success; } static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { // assert(isUInt(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); return MCDisassembler_Success; } #define GET_INSTRINFO_ENUM #include "PPCGenInstrInfo.inc" static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the memri field (imm, reg), which has the low 16-bits as the // displacement and the next 5 bits as the register #. uint64_t Base = Imm >> 16; uint64_t Disp = Imm & 0xFFFF; // assert(Base < 32 && "Invalid base register"); if (Base >= 32) return MCDisassembler_Fail; switch (MCInst_getOpcode(Inst)) { default: break; case PPC_LBZU: case PPC_LHAU: case PPC_LHZU: case PPC_LWZU: case PPC_LFSU: case PPC_LFDU: // Add the tied output operand. MCOperand_CreateReg0(Inst, GP0Regs[Base]); break; case PPC_STBU: case PPC_STHU: case PPC_STWU: case PPC_STFSU: case PPC_STFDU: MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); break; } MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16)); MCOperand_CreateReg0(Inst, GP0Regs[Base]); return MCDisassembler_Success; } static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the memrix field (imm, reg), which has the low 14-bits as the // displacement and the next 5 bits as the register #. uint64_t Base = Imm >> 14; uint64_t Disp = Imm & 0x3FFF; // assert(Base < 32 && "Invalid base register"); if (Base >= 32) return MCDisassembler_Fail; if (MCInst_getOpcode(Inst) == PPC_LDU) // Add the tied output operand. MCOperand_CreateReg0(Inst, GP0Regs[Base]); else if (MCInst_getOpcode(Inst) == PPC_STDU) MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16)); MCOperand_CreateReg0(Inst, GP0Regs[Base]); return MCDisassembler_Success; } static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the memrix16 field (imm, reg), which has the low 12-bits as the // displacement with 16-byte aligned, and the next 5 bits as the register #. uint64_t Base = Imm >> 12; uint64_t Disp = Imm & 0xFFF; // assert(Base < 32 && "Invalid base register"); if (Base >= 32) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, SignExtend64(Disp << 4, 16)); MCOperand_CreateReg0(Inst, GP0Regs[Base]); return MCDisassembler_Success; } static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the spe8disp field (imm, reg), which has the low 5-bits as the // displacement with 8-byte aligned, and the next 5 bits as the register #. uint64_t Base = Imm >> 5; uint64_t Disp = Imm & 0x1F; // assert(Base < 32 && "Invalid base register"); if (Base >= 32) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Disp << 3); MCOperand_CreateReg0(Inst, GP0Regs[Base]); return MCDisassembler_Success; } static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the spe4disp field (imm, reg), which has the low 5-bits as the // displacement with 4-byte aligned, and the next 5 bits as the register #. uint64_t Base = Imm >> 5; uint64_t Disp = Imm & 0x1F; // assert(Base < 32 && "Invalid base register"); if (Base >= 32) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Disp << 2); MCOperand_CreateReg0(Inst, GP0Regs[Base]); return MCDisassembler_Success; } static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // Decode the spe2disp field (imm, reg), which has the low 5-bits as the // displacement with 2-byte aligned, and the next 5 bits as the register #. uint64_t Base = Imm >> 5; uint64_t Disp = Imm & 0x1F; // assert(Base < 32 && "Invalid base register"); if (Base >= 32) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Disp << 1); MCOperand_CreateReg0(Inst, GP0Regs[Base]); return MCDisassembler_Success; } static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // The cr bit encoding is 0x80 >> cr_reg_num. unsigned Zeros = CountTrailingZeros_64(Imm); // assert(Zeros < 8 && "Invalid CR bit value"); if (Zeros >= 8) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); return MCDisassembler_Success; } #include "PPCGenDisassemblerTables.inc" static DecodeStatus getInstruction(MCInst *MI, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address, MCRegisterInfo *MRI) { uint32_t insn; DecodeStatus result; // Get the four bytes of the instruction. if (code_len < 4) { // not enough data *Size = 0; return MCDisassembler_Fail; } // The instruction is big-endian encoded. if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) insn = ((uint32_t) code[0] << 24) | (code[1] << 16) | (code[2] << 8) | (code[3] << 0); else // little endian insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | (code[1] << 8) | (code[0] << 0); if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc) + sizeof(cs_ppc)); } if (MI->csh->mode & CS_MODE_QPX) { result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } // failed to decode MCInst_clear(MI); } else if (MI->csh->mode & CS_MODE_SPE) { result = decodeInstruction_4(DecoderTableSPE32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } // failed to decode MCInst_clear(MI); } result = decodeInstruction_4(DecoderTable32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; return result; } // cannot decode, report error MCInst_clear(MI); *Size = 0; return MCDisassembler_Fail; } bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { DecodeStatus status = getInstruction(instr, code, code_len, size, address, (MCRegisterInfo *)info); return status == MCDisassembler_Success; } #define GET_REGINFO_MC_DESC #include "PPCGenRegisterInfo.inc" void PPC_init(MCRegisterInfo *MRI) { /* InitMCRegisterInfo(PPCRegDesc, 344, RA, PC, PPCMCRegisterClasses, 36, PPCRegUnitRoots, 171, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 7, PPCSubRegIdxRanges, PPCRegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 344, 0, 0, PPCMCRegisterClasses, 36, 0, 0, PPCRegDiffLists, 0, PPCSubRegIdxLists, 7, 0); } #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCDisassembler.h000064400000000000000000000006460072674642500215760ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_PPCDISASSEMBLER_H #define CS_PPCDISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void PPC_init(MCRegisterInfo *MRI); bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCGenAsmWriter.inc000064400000000000000000014006560072674642500220600ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, /* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0, /* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0, /* 33 */ 'b', 'd', 'z', 'a', '+', 32, 0, /* 40 */ 'b', 'd', 'n', 'z', 'a', '+', 32, 0, /* 48 */ 'b', 'd', 'z', 'l', '+', 32, 0, /* 55 */ 'b', 'd', 'n', 'z', 'l', '+', 32, 0, /* 63 */ 'b', 'd', 'z', '+', 32, 0, /* 69 */ 'b', 'd', 'n', 'z', '+', 32, 0, /* 76 */ 'b', 'c', 'l', 32, '2', '0', ',', 32, '3', '1', ',', 32, 0, /* 89 */ 'b', 'c', 't', 'r', 'l', 10, 9, 'l', 'd', 32, '2', ',', 32, 0, /* 103 */ 'b', 'c', 32, '1', '2', ',', 32, 0, /* 111 */ 'b', 'c', 'l', 32, '1', '2', ',', 32, 0, /* 120 */ 'b', 'c', 'l', 'r', 'l', 32, '1', '2', ',', 32, 0, /* 131 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '1', '2', ',', 32, 0, /* 143 */ 'b', 'c', 'l', 'r', 32, '1', '2', ',', 32, 0, /* 153 */ 'b', 'c', 'c', 't', 'r', 32, '1', '2', ',', 32, 0, /* 164 */ 'b', 'c', 32, '4', ',', 32, 0, /* 171 */ 'b', 'c', 'l', 32, '4', ',', 32, 0, /* 179 */ 'b', 'c', 'l', 'r', 'l', 32, '4', ',', 32, 0, /* 189 */ 'b', 'c', 'c', 't', 'r', 'l', 32, '4', ',', 32, 0, /* 200 */ 'b', 'c', 'l', 'r', 32, '4', ',', 32, 0, /* 209 */ 'b', 'c', 'c', 't', 'r', 32, '4', ',', 32, 0, /* 219 */ 'm', 't', 's', 'p', 'r', 32, '2', '5', '6', ',', 32, 0, /* 231 */ 'b', 'd', 'z', 'l', 'a', '-', 32, 0, /* 239 */ 'b', 'd', 'n', 'z', 'l', 'a', '-', 32, 0, /* 248 */ 'b', 'd', 'z', 'a', '-', 32, 0, /* 255 */ 'b', 'd', 'n', 'z', 'a', '-', 32, 0, /* 263 */ 'b', 'd', 'z', 'l', '-', 32, 0, /* 270 */ 'b', 'd', 'n', 'z', 'l', '-', 32, 0, /* 278 */ 'b', 'd', 'z', '-', 32, 0, /* 284 */ 'b', 'd', 'n', 'z', '-', 32, 0, /* 291 */ 'v', 'c', 'm', 'p', 'n', 'e', 'b', '.', 32, 0, /* 301 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'b', '.', 32, 0, /* 312 */ 'e', 'x', 't', 's', 'b', '.', 32, 0, /* 320 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'b', '.', 32, 0, /* 331 */ 'f', 's', 'u', 'b', '.', 32, 0, /* 338 */ 'f', 'm', 's', 'u', 'b', '.', 32, 0, /* 346 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 32, 0, /* 355 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'b', '.', 32, 0, /* 366 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'b', '.', 32, 0, /* 377 */ 'a', 'd', 'd', 'c', '.', 32, 0, /* 384 */ 'a', 'n', 'd', 'c', '.', 32, 0, /* 391 */ 't', 'a', 'b', 'o', 'r', 't', 'd', 'c', '.', 32, 0, /* 402 */ 's', 'u', 'b', 'f', 'c', '.', 32, 0, /* 410 */ 's', 'u', 'b', 'i', 'c', '.', 32, 0, /* 418 */ 'a', 'd', 'd', 'i', 'c', '.', 32, 0, /* 426 */ 'r', 'l', 'd', 'i', 'c', '.', 32, 0, /* 434 */ 'b', 'c', 'd', 't', 'r', 'u', 'n', 'c', '.', 32, 0, /* 445 */ 'b', 'c', 'd', 'u', 't', 'r', 'u', 'n', 'c', '.', 32, 0, /* 457 */ 'o', 'r', 'c', '.', 32, 0, /* 463 */ 't', 'a', 'b', 'o', 'r', 't', 'w', 'c', '.', 32, 0, /* 474 */ 's', 'r', 'a', 'd', '.', 32, 0, /* 481 */ 'f', 'a', 'd', 'd', '.', 32, 0, /* 488 */ 'f', 'm', 'a', 'd', 'd', '.', 32, 0, /* 496 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 32, 0, /* 505 */ 'm', 'u', 'l', 'h', 'd', '.', 32, 0, /* 513 */ 'f', 'c', 'f', 'i', 'd', '.', 32, 0, /* 521 */ 'f', 'c', 't', 'i', 'd', '.', 32, 0, /* 529 */ 'm', 'u', 'l', 'l', 'd', '.', 32, 0, /* 537 */ 's', 'l', 'd', '.', 32, 0, /* 543 */ 'n', 'a', 'n', 'd', '.', 32, 0, /* 550 */ 't', 'e', 'n', 'd', '.', 32, 0, /* 557 */ 's', 'r', 'd', '.', 32, 0, /* 563 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', '.', 32, 0, /* 574 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', '.', 32, 0, /* 585 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', '.', 32, 0, /* 596 */ 'd', 'i', 'v', 'd', '.', 32, 0, /* 603 */ 'c', 'n', 't', 'l', 'z', 'd', '.', 32, 0, /* 612 */ 'c', 'n', 't', 't', 'z', 'd', '.', 32, 0, /* 621 */ 'a', 'd', 'd', 'e', '.', 32, 0, /* 628 */ 'd', 'i', 'v', 'd', 'e', '.', 32, 0, /* 636 */ 's', 'u', 'b', 'f', 'e', '.', 32, 0, /* 644 */ 'a', 'd', 'd', 'm', 'e', '.', 32, 0, /* 652 */ 's', 'u', 'b', 'f', 'm', 'e', '.', 32, 0, /* 661 */ 'f', 'r', 'e', '.', 32, 0, /* 667 */ 'f', 'r', 's', 'q', 'r', 't', 'e', '.', 32, 0, /* 677 */ 'p', 'a', 's', 't', 'e', '.', 32, 0, /* 685 */ 'd', 'i', 'v', 'w', 'e', '.', 32, 0, /* 693 */ 'a', 'd', 'd', 'z', 'e', '.', 32, 0, /* 701 */ 's', 'u', 'b', 'f', 'z', 'e', '.', 32, 0, /* 710 */ 's', 'u', 'b', 'f', '.', 32, 0, /* 717 */ 'm', 't', 'f', 's', 'f', '.', 32, 0, /* 725 */ 'f', 'n', 'e', 'g', '.', 32, 0, /* 732 */ 'v', 'c', 'm', 'p', 'n', 'e', 'h', '.', 32, 0, /* 742 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', '.', 32, 0, /* 753 */ 'e', 'x', 't', 's', 'h', '.', 32, 0, /* 761 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', '.', 32, 0, /* 772 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', '.', 32, 0, /* 783 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'h', '.', 32, 0, /* 794 */ 't', 'a', 'b', 'o', 'r', 't', 'd', 'c', 'i', '.', 32, 0, /* 806 */ 't', 'a', 'b', 'o', 'r', 't', 'w', 'c', 'i', '.', 32, 0, /* 818 */ 's', 'r', 'a', 'd', 'i', '.', 32, 0, /* 826 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', '.', 32, 0, /* 837 */ 'e', 'x', 't', 'l', 'd', 'i', '.', 32, 0, /* 846 */ 'a', 'n', 'd', 'i', '.', 32, 0, /* 853 */ 'c', 'l', 'r', 'r', 'd', 'i', '.', 32, 0, /* 862 */ 'i', 'n', 's', 'r', 'd', 'i', '.', 32, 0, /* 871 */ 'r', 'o', 't', 'r', 'd', 'i', '.', 32, 0, /* 880 */ 'e', 'x', 't', 'r', 'd', 'i', '.', 32, 0, /* 889 */ 'm', 't', 'f', 's', 'f', 'i', '.', 32, 0, /* 898 */ 'e', 'x', 't', 's', 'w', 's', 'l', 'i', '.', 32, 0, /* 909 */ 'r', 'l', 'd', 'i', 'm', 'i', '.', 32, 0, /* 918 */ 'r', 'l', 'w', 'i', 'm', 'i', '.', 32, 0, /* 927 */ 's', 'r', 'a', 'w', 'i', '.', 32, 0, /* 935 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', '.', 32, 0, /* 946 */ 'i', 'n', 's', 'l', 'w', 'i', '.', 32, 0, /* 955 */ 'e', 'x', 't', 'l', 'w', 'i', '.', 32, 0, /* 964 */ 'c', 'l', 'r', 'r', 'w', 'i', '.', 32, 0, /* 973 */ 'i', 'n', 's', 'r', 'w', 'i', '.', 32, 0, /* 982 */ 'r', 'o', 't', 'r', 'w', 'i', '.', 32, 0, /* 991 */ 'e', 'x', 't', 'r', 'w', 'i', '.', 32, 0, /* 1000 */ 'r', 'l', 'd', 'c', 'l', '.', 32, 0, /* 1008 */ 'r', 'l', 'd', 'i', 'c', 'l', '.', 32, 0, /* 1017 */ 'f', 's', 'e', 'l', '.', 32, 0, /* 1024 */ 'f', 'm', 'u', 'l', '.', 32, 0, /* 1031 */ 't', 'r', 'e', 'c', 'l', 'a', 'i', 'm', '.', 32, 0, /* 1042 */ 'f', 'r', 'i', 'm', '.', 32, 0, /* 1049 */ 'r', 'l', 'w', 'i', 'n', 'm', '.', 32, 0, /* 1058 */ 'r', 'l', 'w', 'n', 'm', '.', 32, 0, /* 1066 */ 'b', 'c', 'd', 'c', 'f', 'n', '.', 32, 0, /* 1075 */ 'b', 'c', 'd', 'c', 'p', 's', 'g', 'n', '.', 32, 0, /* 1086 */ 'f', 'c', 'p', 's', 'g', 'n', '.', 32, 0, /* 1095 */ 'b', 'c', 'd', 's', 'e', 't', 's', 'g', 'n', '.', 32, 0, /* 1107 */ 't', 'b', 'e', 'g', 'i', 'n', '.', 32, 0, /* 1116 */ 'f', 'r', 'i', 'n', '.', 32, 0, /* 1123 */ 'b', 'c', 'd', 'c', 't', 'n', '.', 32, 0, /* 1132 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', '.', 32, 0, /* 1144 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', '.', 32, 0, /* 1156 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', '.', 32, 0, /* 1168 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', '.', 32, 0, /* 1178 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', '.', 32, 0, /* 1189 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', '.', 32, 0, /* 1200 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', '.', 32, 0, /* 1211 */ 'f', 'r', 'i', 'p', '.', 32, 0, /* 1218 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', '.', 32, 0, /* 1230 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', '.', 32, 0, /* 1242 */ 'f', 'r', 's', 'p', '.', 32, 0, /* 1249 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', '.', 32, 0, /* 1261 */ 'i', 'c', 'b', 'l', 'q', '.', 32, 0, /* 1269 */ 'b', 'c', 'd', 'c', 'f', 's', 'q', '.', 32, 0, /* 1279 */ 'b', 'c', 'd', 'c', 't', 's', 'q', '.', 32, 0, /* 1289 */ 'r', 'l', 'd', 'c', 'r', '.', 32, 0, /* 1297 */ 'r', 'l', 'd', 'i', 'c', 'r', '.', 32, 0, /* 1306 */ 'f', 'm', 'r', '.', 32, 0, /* 1312 */ 'n', 'o', 'r', '.', 32, 0, /* 1318 */ 'x', 'o', 'r', '.', 32, 0, /* 1324 */ 'b', 'c', 'd', 's', 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0, /* 3542 */ 'c', 'm', 'p', 'l', 'd', 32, 0, /* 3549 */ 'm', 'f', 'v', 's', 'r', 'l', 'd', 32, 0, /* 3558 */ 'v', 'r', 'l', 'd', 32, 0, /* 3564 */ 'v', 's', 'l', 'd', 32, 0, /* 3570 */ 'v', 'b', 'p', 'e', 'r', 'm', 'd', 32, 0, /* 3579 */ 'v', 'p', 'm', 's', 'u', 'm', 'd', 32, 0, /* 3588 */ 'x', 'x', 'l', 'a', 'n', 'd', 32, 0, /* 3596 */ 'x', 'x', 'l', 'n', 'a', 'n', 'd', 32, 0, /* 3605 */ 'c', 'r', 'n', 'a', 'n', 'd', 32, 0, /* 3613 */ 'e', 'v', 'n', 'a', 'n', 'd', 32, 0, /* 3621 */ 'c', 'r', 'a', 'n', 'd', 32, 0, /* 3628 */ 'e', 'v', 'a', 'n', 'd', 32, 0, /* 3635 */ 'c', 'm', 'p', 'd', 32, 0, /* 3641 */ 'x', 'x', 'b', 'r', 'd', 32, 0, /* 3648 */ 'm', 't', 'm', 's', 'r', 'd', 32, 0, /* 3656 */ 'm', 'f', 'v', 's', 'r', 'd', 32, 0, /* 3664 */ 'm', 't', 'v', 's', 'r', 'd', 32, 0, /* 3672 */ 'm', 'o', 'd', 's', 'd', 32, 0, /* 3679 */ 'v', 'm', 'i', 'n', 's', 'd', 32, 0, /* 3687 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'd', 32, 0, /* 3697 */ 'v', 'm', 'a', 'x', 's', 'd', 32, 0, /* 3705 */ 'l', 'x', 's', 'd', 32, 0, /* 3711 */ 's', 't', 'x', 's', 'd', 32, 0, /* 3718 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'd', 32, 0, /* 3729 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 32, 0, /* 3739 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'd', 32, 0, /* 3749 */ 's', 't', 'd', 32, 0, /* 3754 */ 'm', 'o', 'd', 'u', 'd', 32, 0, /* 3761 */ 'v', 'm', 'i', 'n', 'u', 'd', 32, 0, /* 3769 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'd', 32, 0, /* 3779 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'd', 32, 0, /* 3789 */ 'v', 'm', 'a', 'x', 'u', 'd', 32, 0, /* 3797 */ 'd', 'i', 'v', 'd', 32, 0, /* 3803 */ 'v', 'c', 'l', 'z', 'd', 32, 0, /* 3810 */ 'c', 'n', 't', 'l', 'z', 'd', 32, 0, /* 3818 */ 'v', 'c', 't', 'z', 'd', 32, 0, /* 3825 */ 'c', 'n', 't', 't', 'z', 'd', 32, 0, /* 3833 */ 'm', 'f', 'b', 'h', 'r', 'b', 'e', 32, 0, /* 3842 */ 'm', 'f', 'f', 's', 'c', 'e', 32, 0, /* 3850 */ 'a', 'd', 'd', 'e', 32, 0, /* 3856 */ 'd', 'i', 'v', 'd', 'e', 32, 0, /* 3863 */ 's', 'l', 'b', 'm', 'f', 'e', 'e', 32, 0, /* 3872 */ 'w', 'r', 't', 'e', 'e', 32, 0, /* 3879 */ 's', 'u', 'b', 'f', 'e', 32, 0, /* 3886 */ 'e', 'v', 'l', 'w', 'h', 'e', 32, 0, /* 3894 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 32, 0, /* 3903 */ 's', 'l', 'b', 'i', 'e', 32, 0, /* 3910 */ 't', 'l', 'b', 'i', 'e', 32, 0, /* 3917 */ 'a', 'd', 'd', 'm', 'e', 32, 0, /* 3924 */ 's', 'u', 'b', 'f', 'm', 'e', 32, 0, /* 3932 */ 't', 'l', 'b', 'r', 'e', 32, 0, /* 3939 */ 'q', 'v', 'f', 'r', 'e', 32, 0, /* 3946 */ 's', 'l', 'b', 'm', 't', 'e', 32, 0, /* 3954 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 32, 0, /* 3965 */ 'p', 'a', 's', 't', 'e', 32, 0, /* 3972 */ 't', 'l', 'b', 'w', 'e', 32, 0, /* 3979 */ 'd', 'i', 'v', 'w', 'e', 32, 0, /* 3986 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 32, 0, /* 3995 */ 'a', 'd', 'd', 'z', 'e', 32, 0, /* 4002 */ 's', 'u', 'b', 'f', 'z', 'e', 32, 0, /* 4010 */ 'd', 'c', 'b', 'f', 32, 0, /* 4016 */ 's', 'u', 'b', 'f', 32, 0, /* 4022 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 32, 0, /* 4032 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'f', 32, 0, /* 4042 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 32, 0, /* 4052 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 32, 0, /* 4061 */ 'm', 'c', 'r', 'f', 32, 0, /* 4067 */ 'm', 'f', 'o', 'c', 'r', 'f', 32, 0, /* 4075 */ 'm', 't', 'o', 'c', 'r', 'f', 32, 0, /* 4083 */ 'm', 't', 'c', 'r', 'f', 32, 0, /* 4090 */ 'e', 'f', 'd', 'c', 'f', 's', 'f', 32, 0, /* 4099 */ 'e', 'f', 's', 'c', 'f', 's', 'f', 32, 0, /* 4108 */ 'e', 'v', 'f', 's', 'c', 'f', 's', 'f', 32, 0, /* 4118 */ 'm', 't', 'f', 's', 'f', 32, 0, /* 4125 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 32, 0, /* 4135 */ 'e', 'v', 'm', 'w', 'h', 's', 's', 'f', 32, 0, /* 4145 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 32, 0, /* 4155 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 32, 0, /* 4164 */ 'e', 'f', 'd', 'c', 't', 's', 'f', 32, 0, /* 4173 */ 'e', 'f', 's', 'c', 't', 's', 'f', 32, 0, /* 4182 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'f', 32, 0, /* 4192 */ 'e', 'f', 'd', 'c', 'f', 'u', 'f', 32, 0, /* 4201 */ 'e', 'f', 's', 'c', 'f', 'u', 'f', 32, 0, /* 4210 */ 'e', 'v', 'f', 's', 'c', 'f', 'u', 'f', 32, 0, /* 4220 */ 'e', 'f', 'd', 'c', 't', 'u', 'f', 32, 0, /* 4229 */ 'e', 'f', 's', 'c', 't', 'u', 'f', 32, 0, /* 4238 */ 's', 'l', 'b', 'i', 'e', 'g', 32, 0, /* 4246 */ 'e', 'f', 'd', 'n', 'e', 'g', 32, 0, /* 4254 */ 'q', 'v', 'f', 'n', 'e', 'g', 32, 0, /* 4262 */ 'e', 'f', 's', 'n', 'e', 'g', 32, 0, /* 4270 */ 'e', 'v', 'f', 's', 'n', 'e', 'g', 32, 0, /* 4279 */ 'e', 'v', 'n', 'e', 'g', 32, 0, /* 4286 */ 'v', 's', 'r', 'a', 'h', 32, 0, /* 4293 */ 'e', 'v', 'l', 'd', 'h', 32, 0, /* 4300 */ 'e', 'v', 's', 't', 'd', 'h', 32, 0, /* 4308 */ 'v', 'c', 'm', 'p', 'n', 'e', 'h', 32, 0, /* 4317 */ 'v', 'm', 'r', 'g', 'h', 'h', 32, 0, /* 4325 */ 'v', 'm', 'r', 'g', 'l', 'h', 32, 0, /* 4333 */ 'v', 'r', 'l', 'h', 32, 0, /* 4339 */ 'v', 's', 'l', 'h', 32, 0, /* 4345 */ 'v', 'p', 'm', 's', 'u', 'm', 'h', 32, 0, /* 4354 */ 'x', 'x', 'b', 'r', 'h', 32, 0, /* 4361 */ 'v', 's', 'r', 'h', 32, 0, /* 4367 */ 'v', 'm', 'u', 'l', 'e', 's', 'h', 32, 0, /* 4376 */ 'v', 'a', 'v', 'g', 's', 'h', 32, 0, /* 4384 */ 'v', 'u', 'p', 'k', 'h', 's', 'h', 32, 0, /* 4393 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'h', 32, 0, /* 4403 */ 'v', 'u', 'p', 'k', 'l', 's', 'h', 32, 0, /* 4412 */ 'v', 'm', 'i', 'n', 's', 'h', 32, 0, /* 4420 */ 'v', 'm', 'u', 'l', 'o', 's', 'h', 32, 0, /* 4429 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'h', 32, 0, /* 4439 */ 'e', 'v', 'e', 'x', 't', 's', 'h', 32, 0, /* 4448 */ 'v', 'm', 'a', 'x', 's', 'h', 32, 0, /* 4456 */ 'v', 's', 'p', 'l', 't', 'h', 32, 0, /* 4464 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'h', 32, 0, /* 4474 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'h', 32, 0, /* 4484 */ 's', 't', 'h', 32, 0, /* 4489 */ 'v', 'a', 'b', 's', 'd', 'u', 'h', 32, 0, /* 4498 */ 'v', 'm', 'u', 'l', 'e', 'u', 'h', 32, 0, /* 4507 */ 'v', 'a', 'v', 'g', 'u', 'h', 32, 0, /* 4515 */ 'v', 'm', 'i', 'n', 'u', 'h', 32, 0, /* 4523 */ 'v', 'm', 'u', 'l', 'o', 'u', 'h', 32, 0, /* 4532 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'h', 32, 0, /* 4542 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'h', 32, 0, /* 4554 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'h', 32, 0, /* 4564 */ 'v', 'm', 'a', 'x', 'u', 'h', 32, 0, /* 4572 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'h', 32, 0, /* 4582 */ 'v', 'c', 'l', 'z', 'h', 32, 0, /* 4589 */ 'v', 'c', 't', 'z', 'h', 32, 0, /* 4596 */ 'd', 'c', 'b', 'i', 32, 0, /* 4602 */ 'i', 'c', 'b', 'i', 32, 0, /* 4608 */ 's', 'u', 'b', 'i', 32, 0, /* 4614 */ 'd', 'c', 'c', 'c', 'i', 32, 0, /* 4621 */ 'i', 'c', 'c', 'c', 'i', 32, 0, /* 4628 */ 'q', 'v', 'g', 'p', 'c', 'i', 32, 0, /* 4636 */ 's', 'r', 'a', 'd', 'i', 32, 0, /* 4643 */ 'a', 'd', 'd', 'i', 32, 0, /* 4649 */ 'c', 'm', 'p', 'l', 'd', 'i', 32, 0, /* 4657 */ 'c', 'l', 'r', 'l', 's', 'l', 'd', 'i', 32, 0, /* 4667 */ 'e', 'x', 't', 'l', 'd', 'i', 32, 0, /* 4675 */ 'x', 'x', 'p', 'e', 'r', 'm', 'd', 'i', 32, 0, /* 4685 */ 'c', 'm', 'p', 'd', 'i', 32, 0, /* 4692 */ 'c', 'l', 'r', 'r', 'd', 'i', 32, 0, /* 4700 */ 'i', 'n', 's', 'r', 'd', 'i', 32, 0, /* 4708 */ 'r', 'o', 't', 'r', 'd', 'i', 32, 0, /* 4716 */ 'e', 'x', 't', 'r', 'd', 'i', 32, 0, /* 4724 */ 't', 'd', 'i', 32, 0, /* 4729 */ 'w', 'r', 't', 'e', 'e', 'i', 32, 0, /* 4737 */ 'm', 't', 'f', 's', 'f', 'i', 32, 0, /* 4745 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'f', 'i', 32, 0, /* 4756 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 32, 0, /* 4767 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 'h', 'i', 32, 0, /* 4780 */ 't', 'l', 'b', 'l', 'i', 32, 0, /* 4787 */ 'm', 'u', 'l', 'l', 'i', 32, 0, /* 4794 */ 'e', 'x', 't', 's', 'w', 's', 'l', 'i', 32, 0, /* 4804 */ 'v', 'r', 'l', 'd', 'm', 'i', 32, 0, /* 4812 */ 'r', 'l', 'd', 'i', 'm', 'i', 32, 0, /* 4820 */ 'r', 'l', 'w', 'i', 'm', 'i', 32, 0, /* 4828 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 32, 0, /* 4838 */ 'e', 'v', 'm', 'w', 'h', 's', 'm', 'i', 32, 0, /* 4848 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 32, 0, /* 4858 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 32, 0, /* 4867 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 32, 0, /* 4877 */ 'e', 'v', 'm', 'w', 'h', 'u', 'm', 'i', 32, 0, /* 4887 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 32, 0, /* 4897 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 32, 0, /* 4907 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 32, 0, /* 4916 */ 'v', 'r', 'l', 'w', 'm', 'i', 32, 0, /* 4924 */ 'q', 'v', 'a', 'l', 'i', 'g', 'n', 'i', 32, 0, /* 4934 */ 'm', 'f', 'f', 's', 'c', 'r', 'n', 'i', 32, 0, /* 4944 */ 'm', 'f', 'f', 's', 'c', 'd', 'r', 'n', 'i', 32, 0, /* 4955 */ 'v', 's', 'l', 'd', 'o', 'i', 32, 0, /* 4963 */ 'x', 's', 'r', 'd', 'p', 'i', 32, 0, /* 4971 */ 'x', 'v', 'r', 'd', 'p', 'i', 32, 0, /* 4979 */ 'x', 's', 'r', 'q', 'p', 'i', 32, 0, /* 4987 */ 'x', 'v', 'r', 's', 'p', 'i', 32, 0, /* 4995 */ 'x', 'o', 'r', 'i', 32, 0, /* 5001 */ 'e', 'f', 'd', 'c', 'f', 's', 'i', 32, 0, /* 5010 */ 'e', 'f', 's', 'c', 'f', 's', 'i', 32, 0, /* 5019 */ 'e', 'v', 'f', 's', 'c', 'f', 's', 'i', 32, 0, /* 5029 */ 'e', 'f', 'd', 'c', 't', 's', 'i', 32, 0, /* 5038 */ 'e', 'f', 's', 'c', 't', 's', 'i', 32, 0, /* 5047 */ 'e', 'v', 'f', 's', 'c', 't', 's', 'i', 32, 0, /* 5057 */ 'q', 'v', 'e', 's', 'p', 'l', 'a', 't', 'i', 32, 0, /* 5068 */ 'e', 'v', 's', 'p', 'l', 'a', 't', 'i', 32, 0, /* 5078 */ 'e', 'f', 'd', 'c', 'f', 'u', 'i', 32, 0, /* 5087 */ 'e', 'f', 's', 'c', 'f', 'u', 'i', 32, 0, /* 5096 */ 'e', 'v', 'f', 's', 'c', 'f', 'u', 'i', 32, 0, /* 5106 */ 'e', 'f', 'd', 'c', 't', 'u', 'i', 32, 0, /* 5115 */ 'e', 'f', 's', 'c', 't', 'u', 'i', 32, 0, /* 5124 */ 'e', 'v', 'f', 's', 'c', 't', 'u', 'i', 32, 0, /* 5134 */ 's', 'r', 'a', 'w', 'i', 32, 0, /* 5141 */ 'x', 'x', 's', 'l', 'd', 'w', 'i', 32, 0, /* 5150 */ 'c', 'm', 'p', 'l', 'w', 'i', 32, 0, /* 5158 */ 'e', 'v', 'r', 'l', 'w', 'i', 32, 0, /* 5166 */ 'c', 'l', 'r', 'l', 's', 'l', 'w', 'i', 32, 0, /* 5176 */ 'i', 'n', 's', 'l', 'w', 'i', 32, 0, /* 5184 */ 'e', 'v', 's', 'l', 'w', 'i', 32, 0, /* 5192 */ 'e', 'x', 't', 'l', 'w', 'i', 32, 0, /* 5200 */ 'c', 'm', 'p', 'w', 'i', 32, 0, /* 5207 */ 'c', 'l', 'r', 'r', 'w', 'i', 32, 0, /* 5215 */ 'i', 'n', 's', 'r', 'w', 'i', 32, 0, /* 5223 */ 'r', 'o', 't', 'r', 'w', 'i', 32, 0, /* 5231 */ 'e', 'x', 't', 'r', 'w', 'i', 32, 0, /* 5239 */ 'l', 's', 'w', 'i', 32, 0, /* 5245 */ 's', 't', 's', 'w', 'i', 32, 0, /* 5252 */ 't', 'w', 'i', 32, 0, /* 5257 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 'i', 32, 0, /* 5268 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 'i', 32, 0, /* 5278 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'x', 'i', 32, 0, /* 5289 */ 'q', 'v', 's', 't', 'f', 's', 'x', 'i', 32, 0, /* 5299 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'u', 'x', 'i', 32, 0, /* 5311 */ 'q', 'v', 's', 't', 'f', 'd', 'u', 'x', 'i', 32, 0, /* 5322 */ 'q', 'v', 's', 't', 'f', 'c', 's', 'u', 'x', 'i', 32, 0, /* 5334 */ 'q', 'v', 's', 't', 'f', 's', 'u', 'x', 'i', 32, 0, /* 5345 */ 't', 'c', 'h', 'e', 'c', 'k', 32, 0, /* 5353 */ 'q', 'v', 'f', 'l', 'o', 'g', 'i', 'c', 'a', 'l', 32, 0, /* 5365 */ 'b', 'l', 32, 0, /* 5369 */ 'b', 'c', 'l', 32, 0, /* 5374 */ 'r', 'l', 'd', 'c', 'l', 32, 0, /* 5381 */ 'r', 'l', 'd', 'i', 'c', 'l', 32, 0, /* 5389 */ 't', 'l', 'b', 'i', 'e', 'l', 32, 0, /* 5397 */ 'q', 'v', 'f', 's', 'e', 'l', 32, 0, /* 5405 */ 'i', 's', 'e', 'l', 32, 0, /* 5411 */ 'v', 's', 'e', 'l', 32, 0, /* 5417 */ 'x', 'x', 's', 'e', 'l', 32, 0, /* 5424 */ 'd', 'c', 'b', 'f', 'l', 32, 0, /* 5431 */ 'l', 'x', 'v', 'l', 'l', 32, 0, /* 5438 */ 's', 't', 'x', 'v', 'l', 'l', 32, 0, /* 5446 */ 'b', 'c', 'l', 'r', 'l', 32, 0, /* 5453 */ 'b', 'c', 'c', 't', 'r', 'l', 32, 0, /* 5461 */ 'm', 'f', 'f', 's', 'l', 32, 0, /* 5468 */ 'l', 'v', 's', 'l', 32, 0, /* 5474 */ 'e', 'f', 'd', 'm', 'u', 'l', 32, 0, /* 5482 */ 'q', 'v', 'f', 'm', 'u', 'l', 32, 0, /* 5490 */ 'e', 'f', 's', 'm', 'u', 'l', 32, 0, /* 5498 */ 'e', 'v', 'f', 's', 'm', 'u', 'l', 32, 0, /* 5507 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 32, 0, /* 5516 */ 'l', 'x', 'v', 'l', 32, 0, /* 5522 */ 's', 't', 'x', 'v', 'l', 32, 0, /* 5529 */ 'l', 'v', 'x', 'l', 32, 0, /* 5535 */ 's', 't', 'v', 'x', 'l', 32, 0, /* 5542 */ 'd', 'c', 'b', 'z', 'l', 32, 0, /* 5549 */ 'b', 'd', 'z', 'l', 32, 0, /* 5555 */ 'b', 'd', 'n', 'z', 'l', 32, 0, /* 5562 */ 'v', 'm', 's', 'u', 'm', 'm', 'b', 'm', 32, 0, /* 5572 */ 'v', 's', 'u', 'b', 'u', 'b', 'm', 32, 0, /* 5581 */ 'v', 'a', 'd', 'd', 'u', 'b', 'm', 32, 0, /* 5590 */ 'v', 'm', 's', 'u', 'm', 'u', 'b', 'm', 32, 0, /* 5600 */ 'v', 's', 'u', 'b', 'u', 'd', 'm', 32, 0, /* 5609 */ 'v', 'a', 'd', 'd', 'u', 'd', 'm', 32, 0, /* 5618 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 'm', 32, 0, /* 5628 */ 'v', 's', 'u', 'b', 'u', 'h', 'm', 32, 0, /* 5637 */ 'v', 'm', 'l', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0, /* 5648 */ 'v', 'a', 'd', 'd', 'u', 'h', 'm', 32, 0, /* 5657 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 'm', 32, 0, /* 5667 */ 'v', 'r', 'f', 'i', 'm', 32, 0, /* 5674 */ 'x', 's', 'r', 'd', 'p', 'i', 'm', 32, 0, /* 5683 */ 'x', 'v', 'r', 'd', 'p', 'i', 'm', 32, 0, /* 5692 */ 'x', 'v', 'r', 's', 'p', 'i', 'm', 32, 0, /* 5701 */ 'q', 'v', 'f', 'r', 'i', 'm', 32, 0, /* 5709 */ 'v', 'r', 'l', 'd', 'n', 'm', 32, 0, /* 5717 */ 'r', 'l', 'w', 'i', 'n', 'm', 32, 0, /* 5725 */ 'v', 'r', 'l', 'w', 'n', 'm', 32, 0, /* 5733 */ 'v', 's', 'u', 'b', 'u', 'q', 'm', 32, 0, /* 5742 */ 'v', 'a', 'd', 'd', 'u', 'q', 'm', 32, 0, /* 5751 */ 'v', 's', 'u', 'b', 'e', 'u', 'q', 'm', 32, 0, /* 5761 */ 'v', 'a', 'd', 'd', 'e', 'u', 'q', 'm', 32, 0, /* 5771 */ 'q', 'v', 'f', 'p', 'e', 'r', 'm', 32, 0, /* 5780 */ 'v', 'p', 'e', 'r', 'm', 32, 0, /* 5787 */ 'x', 'x', 'p', 'e', 'r', 'm', 32, 0, /* 5795 */ 'v', 'p', 'k', 'u', 'd', 'u', 'm', 32, 0, /* 5804 */ 'v', 'p', 'k', 'u', 'h', 'u', 'm', 32, 0, /* 5813 */ 'v', 'p', 'k', 'u', 'w', 'u', 'm', 32, 0, /* 5822 */ 'v', 's', 'u', 'b', 'u', 'w', 'm', 32, 0, /* 5831 */ 'v', 'a', 'd', 'd', 'u', 'w', 'm', 32, 0, /* 5840 */ 'v', 'm', 'u', 'l', 'u', 'w', 'm', 32, 0, /* 5849 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'f', 'a', 'n', 32, 0, /* 5862 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'f', 'a', 'n', 32, 0, /* 5875 */ 'e', 'v', 'm', 'w', 's', 'm', 'f', 'a', 'n', 32, 0, /* 5886 */ 'e', 'v', 'm', 'w', 's', 's', 'f', 'a', 'n', 32, 0, /* 5897 */ 'e', 'v', 'm', 'h', 'e', 'g', 's', 'm', 'i', 'a', 'n', 32, 0, /* 5910 */ 'e', 'v', 'm', 'h', 'o', 'g', 's', 'm', 'i', 'a', 'n', 32, 0, /* 5923 */ 'e', 'v', 'm', 'w', 's', 'm', 'i', 'a', 'n', 32, 0, /* 5934 */ 'e', 'v', 'm', 'h', 'e', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0, /* 5947 */ 'e', 'v', 'm', 'h', 'o', 'g', 'u', 'm', 'i', 'a', 'n', 32, 0, /* 5960 */ 'e', 'v', 'm', 'w', 'u', 'm', 'i', 'a', 'n', 32, 0, /* 5971 */ 'q', 'v', 'f', 't', 's', 't', 'n', 'a', 'n', 32, 0, /* 5982 */ 'q', 'v', 'f', 'c', 'p', 's', 'g', 'n', 32, 0, /* 5992 */ 'v', 'r', 'f', 'i', 'n', 32, 0, /* 5999 */ 'q', 'v', 'f', 'r', 'i', 'n', 32, 0, /* 6007 */ 'm', 'f', 's', 'r', 'i', 'n', 32, 0, /* 6015 */ 'm', 't', 's', 'r', 'i', 'n', 32, 0, /* 6023 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 'n', 32, 0, /* 6034 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 'n', 32, 0, /* 6045 */ 'd', 'a', 'r', 'n', 32, 0, /* 6051 */ 'm', 'f', 'f', 's', 'c', 'r', 'n', 32, 0, /* 6060 */ 'm', 'f', 'f', 's', 'c', 'd', 'r', 'n', 32, 0, /* 6070 */ 'e', 'v', 's', 't', 'w', 'h', 'o', 32, 0, /* 6079 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'l', 'o', 32, 0, /* 6090 */ 'e', 'v', 'm', 'e', 'r', 'g', 'e', 'h', 'i', 'l', 'o', 32, 0, /* 6103 */ 'v', 's', 'l', 'o', 32, 0, /* 6109 */ 'x', 's', 'c', 'v', 'q', 'p', 'd', 'p', 'o', 32, 0, /* 6120 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'q', 'p', 'o', 32, 0, /* 6132 */ 'x', 's', 'm', 's', 'u', 'b', 'q', 'p', 'o', 32, 0, /* 6143 */ 'x', 's', 's', 'u', 'b', 'q', 'p', 'o', 32, 0, /* 6153 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0, /* 6165 */ 'x', 's', 'm', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0, /* 6176 */ 'x', 's', 'a', 'd', 'd', 'q', 'p', 'o', 32, 0, /* 6186 */ 'x', 's', 'm', 'u', 'l', 'q', 'p', 'o', 32, 0, /* 6196 */ 'x', 's', 's', 'q', 'r', 't', 'q', 'p', 'o', 32, 0, /* 6207 */ 'x', 's', 'd', 'i', 'v', 'q', 'p', 'o', 32, 0, /* 6217 */ 'v', 's', 'r', 'o', 32, 0, /* 6223 */ 'e', 'v', 's', 't', 'w', 'w', 'o', 32, 0, /* 6232 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, /* 6244 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, /* 6256 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, /* 6267 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 'd', 'p', 32, 0, /* 6278 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, /* 6290 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, /* 6302 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, /* 6313 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 'd', 'p', 32, 0, /* 6324 */ 'x', 's', 's', 'u', 'b', 'd', 'p', 32, 0, /* 6333 */ 'x', 'v', 's', 'u', 'b', 'd', 'p', 32, 0, /* 6342 */ 'x', 's', 't', 's', 't', 'd', 'c', 'd', 'p', 32, 0, /* 6353 */ 'x', 'v', 't', 's', 't', 'd', 'c', 'd', 'p', 32, 0, /* 6364 */ 'x', 's', 'm', 'i', 'n', 'c', 'd', 'p', 32, 0, /* 6374 */ 'x', 's', 'm', 'a', 'x', 'c', 'd', 'p', 32, 0, /* 6384 */ 'x', 's', 'a', 'd', 'd', 'd', 'p', 32, 0, /* 6393 */ 'x', 'v', 'a', 'd', 'd', 'd', 'p', 32, 0, /* 6402 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0, /* 6413 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 'd', 'p', 32, 0, /* 6424 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0, /* 6435 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 'd', 'p', 32, 0, /* 6446 */ 'x', 's', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0, /* 6457 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 'd', 'p', 32, 0, /* 6468 */ 'x', 's', 'r', 'e', 'd', 'p', 32, 0, /* 6476 */ 'x', 'v', 'r', 'e', 'd', 'p', 32, 0, /* 6484 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0, /* 6496 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 'd', 'p', 32, 0, /* 6508 */ 'x', 's', 'n', 'e', 'g', 'd', 'p', 32, 0, /* 6517 */ 'x', 'v', 'n', 'e', 'g', 'd', 'p', 32, 0, /* 6526 */ 'x', 's', 'x', 's', 'i', 'g', 'd', 'p', 32, 0, /* 6536 */ 'x', 'v', 'x', 's', 'i', 'g', 'd', 'p', 32, 0, /* 6546 */ 'x', 's', 'm', 'i', 'n', 'j', 'd', 'p', 32, 0, /* 6556 */ 'x', 's', 'm', 'a', 'x', 'j', 'd', 'p', 32, 0, /* 6566 */ 'x', 's', 'm', 'u', 'l', 'd', 'p', 32, 0, /* 6575 */ 'x', 'v', 'm', 'u', 'l', 'd', 'p', 32, 0, /* 6584 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, /* 6596 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, /* 6608 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, /* 6619 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 'd', 'p', 32, 0, /* 6630 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, /* 6642 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, /* 6654 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, /* 6665 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 'd', 'p', 32, 0, /* 6676 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0, /* 6687 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 'd', 'p', 32, 0, /* 6698 */ 'x', 's', 'm', 'i', 'n', 'd', 'p', 32, 0, /* 6707 */ 'x', 'v', 'm', 'i', 'n', 'd', 'p', 32, 0, /* 6716 */ 'x', 's', 'c', 'm', 'p', 'o', 'd', 'p', 32, 0, /* 6726 */ 'x', 's', 'c', 'v', 'h', 'p', 'd', 'p', 32, 0, /* 6736 */ 'x', 's', 'c', 'v', 'q', 'p', 'd', 'p', 32, 0, /* 6746 */ 'x', 's', 'c', 'v', 's', 'p', 'd', 'p', 32, 0, /* 6756 */ 'x', 'v', 'c', 'v', 's', 'p', 'd', 'p', 32, 0, /* 6766 */ 'x', 's', 'i', 'e', 'x', 'p', 'd', 'p', 32, 0, /* 6776 */ 'x', 'v', 'i', 'e', 'x', 'p', 'd', 'p', 32, 0, /* 6786 */ 'x', 's', 'c', 'm', 'p', 'e', 'x', 'p', 'd', 'p', 32, 0, /* 6798 */ 'x', 's', 'x', 'e', 'x', 'p', 'd', 'p', 32, 0, /* 6808 */ 'x', 'v', 'x', 'e', 'x', 'p', 'd', 'p', 32, 0, /* 6818 */ 'x', 's', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0, /* 6829 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 'd', 'p', 32, 0, /* 6840 */ 'x', 's', 'n', 'a', 'b', 's', 'd', 'p', 32, 0, /* 6850 */ 'x', 'v', 'n', 'a', 'b', 's', 'd', 'p', 32, 0, /* 6860 */ 'x', 's', 'a', 'b', 's', 'd', 'p', 32, 0, /* 6869 */ 'x', 'v', 'a', 'b', 's', 'd', 'p', 32, 0, /* 6878 */ 'x', 's', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0, /* 6889 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 'd', 'p', 32, 0, /* 6900 */ 'x', 's', 's', 'q', 'r', 't', 'd', 'p', 32, 0, /* 6910 */ 'x', 's', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0, /* 6921 */ 'x', 'v', 't', 's', 'q', 'r', 't', 'd', 'p', 32, 0, /* 6932 */ 'x', 'v', 's', 'q', 'r', 't', 'd', 'p', 32, 0, /* 6942 */ 'x', 's', 'c', 'm', 'p', 'u', 'd', 'p', 32, 0, /* 6952 */ 'x', 's', 'd', 'i', 'v', 'd', 'p', 32, 0, /* 6961 */ 'x', 's', 't', 'd', 'i', 'v', 'd', 'p', 32, 0, /* 6971 */ 'x', 'v', 't', 'd', 'i', 'v', 'd', 'p', 32, 0, /* 6981 */ 'x', 'v', 'd', 'i', 'v', 'd', 'p', 32, 0, /* 6990 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 'd', 'p', 32, 0, /* 7001 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 'd', 'p', 32, 0, /* 7012 */ 'x', 's', 'm', 'a', 'x', 'd', 'p', 32, 0, /* 7021 */ 'x', 'v', 'm', 'a', 'x', 'd', 'p', 32, 0, /* 7030 */ 'd', 'c', 'b', 'f', 'e', 'p', 32, 0, /* 7038 */ 'i', 'c', 'b', 'i', 'e', 'p', 32, 0, /* 7046 */ 'd', 'c', 'b', 'z', 'l', 'e', 'p', 32, 0, /* 7055 */ 'd', 'c', 'b', 't', 'e', 'p', 32, 0, /* 7063 */ 'd', 'c', 'b', 's', 't', 'e', 'p', 32, 0, /* 7072 */ 'd', 'c', 'b', 't', 's', 't', 'e', 'p', 32, 0, /* 7082 */ 'd', 'c', 'b', 'z', 'e', 'p', 32, 0, /* 7090 */ 'v', 'c', 'm', 'p', 'b', 'f', 'p', 32, 0, /* 7099 */ 'v', 'n', 'm', 's', 'u', 'b', 'f', 'p', 32, 0, /* 7109 */ 'v', 's', 'u', 'b', 'f', 'p', 32, 0, /* 7117 */ 'v', 'm', 'a', 'd', 'd', 'f', 'p', 32, 0, /* 7126 */ 'v', 'a', 'd', 'd', 'f', 'p', 32, 0, /* 7134 */ 'v', 'l', 'o', 'g', 'e', 'f', 'p', 32, 0, /* 7143 */ 'v', 'c', 'm', 'p', 'g', 'e', 'f', 'p', 32, 0, /* 7153 */ 'v', 'r', 'e', 'f', 'p', 32, 0, /* 7160 */ 'v', 'e', 'x', 'p', 't', 'e', 'f', 'p', 32, 0, /* 7170 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 'f', 'p', 32, 0, /* 7181 */ 'v', 'm', 'i', 'n', 'f', 'p', 32, 0, /* 7189 */ 'v', 'c', 'm', 'p', 'e', 'q', 'f', 'p', 32, 0, /* 7199 */ 'v', 'c', 'm', 'p', 'g', 't', 'f', 'p', 32, 0, /* 7209 */ 'v', 'm', 'a', 'x', 'f', 'p', 32, 0, /* 7217 */ 'x', 's', 'c', 'v', 'd', 'p', 'h', 'p', 32, 0, /* 7227 */ 'x', 'v', 'c', 'v', 's', 'p', 'h', 'p', 32, 0, /* 7237 */ 'v', 'r', 'f', 'i', 'p', 32, 0, /* 7244 */ 'x', 's', 'r', 'd', 'p', 'i', 'p', 32, 0, /* 7253 */ 'x', 'v', 'r', 'd', 'p', 'i', 'p', 32, 0, /* 7262 */ 'x', 'v', 'r', 's', 'p', 'i', 'p', 32, 0, /* 7271 */ 'q', 'v', 'f', 'r', 'i', 'p', 32, 0, /* 7279 */ 'd', 'c', 'b', 'f', 'l', 'p', 32, 0, /* 7287 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'q', 'p', 32, 0, /* 7298 */ 'x', 's', 'm', 's', 'u', 'b', 'q', 'p', 32, 0, /* 7308 */ 'x', 's', 's', 'u', 'b', 'q', 'p', 32, 0, /* 7317 */ 'x', 's', 't', 's', 't', 'd', 'c', 'q', 'p', 32, 0, /* 7328 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'q', 'p', 32, 0, /* 7339 */ 'x', 's', 'm', 'a', 'd', 'd', 'q', 'p', 32, 0, /* 7349 */ 'x', 's', 'a', 'd', 'd', 'q', 'p', 32, 0, /* 7358 */ 'x', 's', 'c', 'v', 's', 'd', 'q', 'p', 32, 0, /* 7368 */ 'x', 's', 'c', 'v', 'u', 'd', 'q', 'p', 32, 0, /* 7378 */ 'x', 's', 'n', 'e', 'g', 'q', 'p', 32, 0, /* 7387 */ 'x', 's', 'x', 's', 'i', 'g', 'q', 'p', 32, 0, /* 7397 */ 'x', 's', 'm', 'u', 'l', 'q', 'p', 32, 0, /* 7406 */ 'x', 's', 'c', 'p', 's', 'g', 'n', 'q', 'p', 32, 0, /* 7417 */ 'x', 's', 'c', 'm', 'p', 'o', 'q', 'p', 32, 0, /* 7427 */ 'x', 's', 'c', 'v', 'd', 'p', 'q', 'p', 32, 0, /* 7437 */ 'x', 's', 'i', 'e', 'x', 'p', 'q', 'p', 32, 0, /* 7447 */ 'x', 's', 'c', 'm', 'p', 'e', 'x', 'p', 'q', 'p', 32, 0, /* 7459 */ 'x', 's', 'x', 'e', 'x', 'p', 'q', 'p', 32, 0, /* 7469 */ 'x', 's', 'n', 'a', 'b', 's', 'q', 'p', 32, 0, /* 7479 */ 'x', 's', 'a', 'b', 's', 'q', 'p', 32, 0, /* 7488 */ 'x', 's', 's', 'q', 'r', 't', 'q', 'p', 32, 0, /* 7498 */ 'x', 's', 'c', 'm', 'p', 'u', 'q', 'p', 32, 0, /* 7508 */ 'x', 's', 'd', 'i', 'v', 'q', 'p', 32, 0, /* 7517 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, /* 7529 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, /* 7541 */ 'x', 's', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, /* 7552 */ 'x', 'v', 'm', 's', 'u', 'b', 'a', 's', 'p', 32, 0, /* 7563 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, /* 7575 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, /* 7587 */ 'x', 's', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, /* 7598 */ 'x', 'v', 'm', 'a', 'd', 'd', 'a', 's', 'p', 32, 0, /* 7609 */ 'x', 's', 's', 'u', 'b', 's', 'p', 32, 0, /* 7618 */ 'x', 'v', 's', 'u', 'b', 's', 'p', 32, 0, /* 7627 */ 'x', 's', 't', 's', 't', 'd', 'c', 's', 'p', 32, 0, /* 7638 */ 'x', 'v', 't', 's', 't', 'd', 'c', 's', 'p', 32, 0, /* 7649 */ 'x', 's', 'a', 'd', 'd', 's', 'p', 32, 0, /* 7658 */ 'x', 'v', 'a', 'd', 'd', 's', 'p', 32, 0, /* 7667 */ 'x', 's', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0, /* 7678 */ 'x', 'v', 'c', 'v', 's', 'x', 'd', 's', 'p', 32, 0, /* 7689 */ 'x', 's', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0, /* 7700 */ 'x', 'v', 'c', 'v', 'u', 'x', 'd', 's', 'p', 32, 0, /* 7711 */ 'x', 'v', 'c', 'm', 'p', 'g', 'e', 's', 'p', 32, 0, /* 7722 */ 'x', 's', 'r', 'e', 's', 'p', 32, 0, /* 7730 */ 'x', 'v', 'r', 'e', 's', 'p', 32, 0, /* 7738 */ 'x', 's', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0, /* 7750 */ 'x', 'v', 'r', 's', 'q', 'r', 't', 'e', 's', 'p', 32, 0, /* 7762 */ 'x', 'v', 'n', 'e', 'g', 's', 'p', 32, 0, /* 7771 */ 'x', 'v', 'x', 's', 'i', 'g', 's', 'p', 32, 0, /* 7781 */ 'x', 's', 'm', 'u', 'l', 's', 'p', 32, 0, /* 7790 */ 'x', 'v', 'm', 'u', 'l', 's', 'p', 32, 0, /* 7799 */ 'x', 's', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, /* 7811 */ 'x', 'v', 'n', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, /* 7823 */ 'x', 's', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, /* 7834 */ 'x', 'v', 'm', 's', 'u', 'b', 'm', 's', 'p', 32, 0, /* 7845 */ 'x', 's', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, /* 7857 */ 'x', 'v', 'n', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, /* 7869 */ 'x', 's', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, /* 7880 */ 'x', 'v', 'm', 'a', 'd', 'd', 'm', 's', 'p', 32, 0, /* 7891 */ 'x', 'v', 'c', 'p', 's', 'g', 'n', 's', 'p', 32, 0, /* 7902 */ 'x', 'v', 'm', 'i', 'n', 's', 'p', 32, 0, /* 7911 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'p', 32, 0, /* 7921 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'p', 32, 0, /* 7931 */ 'x', 'v', 'c', 'v', 'h', 'p', 's', 'p', 32, 0, /* 7941 */ 'x', 'v', 'i', 'e', 'x', 'p', 's', 'p', 32, 0, /* 7951 */ 'x', 'v', 'x', 'e', 'x', 'p', 's', 'p', 32, 0, /* 7961 */ 'x', 'v', 'c', 'm', 'p', 'e', 'q', 's', 'p', 32, 0, /* 7972 */ 'q', 'v', 'f', 'r', 's', 'p', 32, 0, /* 7980 */ 'x', 's', 'r', 's', 'p', 32, 0, /* 7987 */ 'x', 'v', 'n', 'a', 'b', 's', 's', 'p', 32, 0, /* 7997 */ 'x', 'v', 'a', 'b', 's', 's', 'p', 32, 0, /* 8006 */ 'l', 'x', 's', 's', 'p', 32, 0, /* 8013 */ 's', 't', 'x', 's', 's', 'p', 32, 0, /* 8021 */ 'x', 'v', 'c', 'm', 'p', 'g', 't', 's', 'p', 32, 0, /* 8032 */ 'x', 's', 's', 'q', 'r', 't', 's', 'p', 32, 0, /* 8042 */ 'x', 'v', 't', 's', 'q', 'r', 't', 's', 'p', 32, 0, /* 8053 */ 'x', 'v', 's', 'q', 'r', 't', 's', 'p', 32, 0, /* 8063 */ 'x', 's', 'd', 'i', 'v', 's', 'p', 32, 0, /* 8072 */ 'x', 'v', 't', 'd', 'i', 'v', 's', 'p', 32, 0, /* 8082 */ 'x', 'v', 'd', 'i', 'v', 's', 'p', 32, 0, /* 8091 */ 'x', 'v', 'c', 'v', 's', 'x', 'w', 's', 'p', 32, 0, /* 8102 */ 'x', 'v', 'c', 'v', 'u', 'x', 'w', 's', 'p', 32, 0, /* 8113 */ 'x', 'v', 'm', 'a', 'x', 's', 'p', 32, 0, /* 8122 */ 'x', 's', 'r', 'q', 'p', 'x', 'p', 32, 0, /* 8131 */ 'v', 'p', 'r', 't', 'y', 'b', 'q', 32, 0, /* 8140 */ 'e', 'f', 'd', 'c', 'm', 'p', 'e', 'q', 32, 0, /* 8150 */ 'q', 'v', 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, /* 8160 */ 'e', 'f', 's', 'c', 'm', 'p', 'e', 'q', 32, 0, /* 8170 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'e', 'q', 32, 0, /* 8181 */ 'e', 'v', 'c', 'm', 'p', 'e', 'q', 32, 0, /* 8190 */ 'e', 'f', 'd', 't', 's', 't', 'e', 'q', 32, 0, /* 8200 */ 'e', 'f', 's', 't', 's', 't', 'e', 'q', 32, 0, /* 8210 */ 'e', 'v', 'f', 's', 't', 's', 't', 'e', 'q', 32, 0, /* 8221 */ 'v', 'b', 'p', 'e', 'r', 'm', 'q', 32, 0, /* 8230 */ 'x', 'x', 'b', 'r', 'q', 32, 0, /* 8237 */ 'v', 'm', 'u', 'l', '1', '0', 'u', 'q', 32, 0, /* 8247 */ 'v', 'm', 'u', 'l', '1', '0', 'c', 'u', 'q', 32, 0, /* 8258 */ 'v', 's', 'u', 'b', 'c', 'u', 'q', 32, 0, /* 8267 */ 'v', 'a', 'd', 'd', 'c', 'u', 'q', 32, 0, /* 8276 */ 'v', 'm', 'u', 'l', '1', '0', 'e', 'c', 'u', 'q', 32, 0, /* 8288 */ 'v', 's', 'u', 'b', 'e', 'c', 'u', 'q', 32, 0, /* 8298 */ 'v', 'a', 'd', 'd', 'e', 'c', 'u', 'q', 32, 0, /* 8308 */ 'v', 'm', 'u', 'l', '1', '0', 'e', 'u', 'q', 32, 0, /* 8319 */ '#', 'T', 'C', '_', 'R', 'E', 'T', 'U', 'R', 'N', 'r', 32, 0, /* 8332 */ 'm', 'b', 'a', 'r', 32, 0, /* 8338 */ 'm', 'f', 'd', 'c', 'r', 32, 0, /* 8345 */ 'r', 'l', 'd', 'c', 'r', 32, 0, /* 8352 */ 'm', 't', 'd', 'c', 'r', 32, 0, /* 8359 */ 'm', 'f', 'c', 'r', 32, 0, /* 8365 */ 'r', 'l', 'd', 'i', 'c', 'r', 32, 0, /* 8373 */ 'm', 'f', 'v', 's', 'c', 'r', 32, 0, /* 8381 */ 'm', 't', 'v', 's', 'c', 'r', 32, 0, /* 8389 */ 'v', 'n', 'c', 'i', 'p', 'h', 'e', 'r', 32, 0, /* 8399 */ 'v', 'c', 'i', 'p', 'h', 'e', 'r', 32, 0, /* 8408 */ 'b', 'c', 'l', 'r', 32, 0, /* 8414 */ 'm', 'f', 'l', 'r', 32, 0, /* 8420 */ 'm', 't', 'l', 'r', 32, 0, /* 8426 */ 'q', 'v', 'f', 'm', 'r', 32, 0, /* 8433 */ 'm', 'f', 'p', 'm', 'r', 32, 0, /* 8440 */ 'm', 't', 'p', 'm', 'r', 32, 0, /* 8447 */ 'v', 'p', 'e', 'r', 'm', 'r', 32, 0, /* 8455 */ 'x', 'x', 'p', 'e', 'r', 'm', 'r', 32, 0, /* 8464 */ 'x', 'x', 'l', 'o', 'r', 32, 0, /* 8471 */ 'x', 'x', 'l', 'n', 'o', 'r', 32, 0, /* 8479 */ 'c', 'r', 'n', 'o', 'r', 32, 0, /* 8486 */ 'e', 'v', 'n', 'o', 'r', 32, 0, /* 8493 */ 'c', 'r', 'o', 'r', 32, 0, /* 8499 */ 'e', 'v', 'o', 'r', 32, 0, /* 8505 */ 'x', 'x', 'l', 'x', 'o', 'r', 32, 0, /* 8513 */ 'v', 'p', 'e', 'r', 'm', 'x', 'o', 'r', 32, 0, /* 8523 */ 'c', 'r', 'x', 'o', 'r', 32, 0, /* 8530 */ 'e', 'v', 'x', 'o', 'r', 32, 0, /* 8537 */ 'm', 'f', 's', 'p', 'r', 32, 0, /* 8544 */ 'm', 't', 's', 'p', 'r', 32, 0, /* 8551 */ 'm', 'f', 's', 'r', 32, 0, /* 8557 */ 'm', 'f', 'm', 's', 'r', 32, 0, /* 8564 */ 'm', 't', 'm', 's', 'r', 32, 0, /* 8571 */ 'm', 't', 's', 'r', 32, 0, /* 8577 */ 'l', 'v', 's', 'r', 32, 0, /* 8583 */ 'b', 'c', 'c', 't', 'r', 32, 0, /* 8590 */ 'm', 'f', 'c', 't', 'r', 32, 0, /* 8597 */ 'm', 't', 'c', 't', 'r', 32, 0, /* 8604 */ 'e', 'f', 'd', 'a', 'b', 's', 32, 0, /* 8612 */ 'q', 'v', 'f', 'a', 'b', 's', 32, 0, /* 8620 */ 'e', 'f', 'd', 'n', 'a', 'b', 's', 32, 0, /* 8629 */ 'q', 'v', 'f', 'n', 'a', 'b', 's', 32, 0, /* 8638 */ 'e', 'f', 's', 'n', 'a', 'b', 's', 32, 0, /* 8647 */ 'e', 'v', 'f', 's', 'n', 'a', 'b', 's', 32, 0, /* 8657 */ 'e', 'f', 's', 'a', 'b', 's', 32, 0, /* 8665 */ 'e', 'v', 'f', 's', 'a', 'b', 's', 32, 0, /* 8674 */ 'e', 'v', 'a', 'b', 's', 32, 0, /* 8681 */ 'v', 's', 'u', 'm', '4', 's', 'b', 's', 32, 0, /* 8691 */ 'v', 's', 'u', 'b', 's', 'b', 's', 32, 0, /* 8700 */ 'v', 'a', 'd', 'd', 's', 'b', 's', 32, 0, /* 8709 */ 'v', 's', 'u', 'm', '4', 'u', 'b', 's', 32, 0, /* 8719 */ 'v', 's', 'u', 'b', 'u', 'b', 's', 32, 0, /* 8728 */ 'v', 'a', 'd', 'd', 'u', 'b', 's', 32, 0, /* 8737 */ 'q', 'v', 'f', 's', 'u', 'b', 's', 32, 0, /* 8746 */ 'q', 'v', 'f', 'm', 's', 'u', 'b', 's', 32, 0, /* 8756 */ 'q', 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 32, 0, /* 8767 */ 'q', 'v', 'f', 'a', 'd', 'd', 's', 32, 0, /* 8776 */ 'q', 'v', 'f', 'm', 'a', 'd', 'd', 's', 32, 0, /* 8786 */ 'q', 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 32, 0, /* 8797 */ 'q', 'v', 'f', 'x', 'x', 'c', 'p', 'n', 'm', 'a', 'd', 'd', 's', 32, 0, /* 8812 */ 'q', 'v', 'f', 'x', 'x', 'n', 'p', 'm', 'a', 'd', 'd', 's', 32, 0, /* 8826 */ 'q', 'v', 'f', 'x', 'm', 'a', 'd', 'd', 's', 32, 0, /* 8837 */ 'q', 'v', 'f', 'x', 'x', 'm', 'a', 'd', 'd', 's', 32, 0, /* 8849 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 's', 32, 0, /* 8859 */ 'd', 'c', 'b', 't', 'd', 's', 32, 0, /* 8867 */ 'd', 'c', 'b', 't', 's', 't', 'd', 's', 32, 0, /* 8877 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0, /* 8889 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'd', 's', 32, 0, /* 8901 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'd', 's', 32, 0, /* 8913 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0, /* 8925 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'd', 's', 32, 0, /* 8937 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'd', 's', 32, 0, /* 8949 */ 'q', 'v', 'f', 'r', 'e', 's', 32, 0, /* 8957 */ 'q', 'v', 'f', 'r', 's', 'q', 'r', 't', 'e', 's', 32, 0, /* 8969 */ 'e', 'f', 'd', 'c', 'f', 's', 32, 0, /* 8977 */ 'm', 'f', 'f', 's', 32, 0, /* 8983 */ 'l', 'f', 's', 32, 0, /* 8988 */ 'm', 'c', 'r', 'f', 's', 32, 0, /* 8995 */ 's', 't', 'f', 's', 32, 0, /* 9001 */ 'v', 's', 'u', 'm', '4', 's', 'h', 's', 32, 0, /* 9011 */ 'v', 's', 'u', 'b', 's', 'h', 's', 32, 0, /* 9020 */ 'v', 'm', 'h', 'a', 'd', 'd', 's', 'h', 's', 32, 0, /* 9031 */ 'v', 'm', 'h', 'r', 'a', 'd', 'd', 's', 'h', 's', 32, 0, /* 9043 */ 'v', 'a', 'd', 'd', 's', 'h', 's', 32, 0, /* 9052 */ 'v', 'm', 's', 'u', 'm', 's', 'h', 's', 32, 0, /* 9062 */ 'v', 's', 'u', 'b', 'u', 'h', 's', 32, 0, /* 9071 */ 'v', 'a', 'd', 'd', 'u', 'h', 's', 32, 0, /* 9080 */ 'v', 'm', 's', 'u', 'm', 'u', 'h', 's', 32, 0, /* 9090 */ 's', 'u', 'b', 'i', 's', 32, 0, /* 9097 */ 's', 'u', 'b', 'p', 'c', 'i', 's', 32, 0, /* 9106 */ 'a', 'd', 'd', 'p', 'c', 'i', 's', 32, 0, /* 9115 */ 'a', 'd', 'd', 'i', 's', 32, 0, /* 9122 */ 'l', 'i', 's', 32, 0, /* 9127 */ 'x', 'o', 'r', 'i', 's', 32, 0, /* 9134 */ 'e', 'v', 's', 'r', 'w', 'i', 's', 32, 0, /* 9143 */ 'i', 'c', 'b', 't', 'l', 's', 32, 0, /* 9151 */ 'q', 'v', 'f', 'm', 'u', 'l', 's', 32, 0, /* 9160 */ 'q', 'v', 'f', 'x', 'm', 'u', 'l', 's', 32, 0, /* 9170 */ 'e', 'v', 'l', 'w', 'h', 'o', 's', 32, 0, /* 9179 */ 'v', 'p', 'k', 's', 'd', 's', 's', 32, 0, /* 9188 */ 'v', 'p', 'k', 's', 'h', 's', 's', 32, 0, /* 9197 */ 'v', 'p', 'k', 's', 'w', 's', 's', 32, 0, /* 9206 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 's', 32, 0, /* 9216 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 's', 32, 0, /* 9226 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, /* 9234 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 's', 32, 0, /* 9245 */ 'v', 'p', 'k', 's', 'd', 'u', 's', 32, 0, /* 9254 */ 'v', 'p', 'k', 'u', 'd', 'u', 's', 32, 0, /* 9263 */ 'v', 'p', 'k', 's', 'h', 'u', 's', 32, 0, /* 9272 */ 'v', 'p', 'k', 'u', 'h', 'u', 's', 32, 0, /* 9281 */ 'v', 'p', 'k', 's', 'w', 'u', 's', 32, 0, /* 9290 */ 'v', 'p', 'k', 'u', 'w', 'u', 's', 32, 0, /* 9299 */ 'f', 'd', 'i', 'v', 's', 32, 0, /* 9306 */ 'e', 'v', 's', 'r', 'w', 's', 32, 0, /* 9314 */ 'm', 't', 'v', 's', 'r', 'w', 's', 32, 0, /* 9323 */ 'v', 's', 'u', 'm', '2', 's', 'w', 's', 32, 0, /* 9333 */ 'v', 's', 'u', 'b', 's', 'w', 's', 32, 0, /* 9342 */ 'v', 'a', 'd', 'd', 's', 'w', 's', 32, 0, /* 9351 */ 'v', 's', 'u', 'm', 's', 'w', 's', 32, 0, /* 9360 */ 'v', 's', 'u', 'b', 'u', 'w', 's', 32, 0, /* 9369 */ 'v', 'a', 'd', 'd', 'u', 'w', 's', 32, 0, /* 9378 */ 'e', 'v', 'd', 'i', 'v', 'w', 's', 32, 0, /* 9387 */ 'x', 's', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0, /* 9399 */ 'x', 'v', 'c', 'v', 'd', 'p', 's', 'x', 'w', 's', 32, 0, /* 9411 */ 'x', 'v', 'c', 'v', 's', 'p', 's', 'x', 'w', 's', 32, 0, /* 9423 */ 'x', 's', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0, /* 9435 */ 'x', 'v', 'c', 'v', 'd', 'p', 'u', 'x', 'w', 's', 32, 0, /* 9447 */ 'x', 'v', 'c', 'v', 's', 'p', 'u', 'x', 'w', 's', 32, 0, /* 9459 */ 'v', 'c', 't', 's', 'x', 's', 32, 0, /* 9467 */ 'v', 'c', 't', 'u', 'x', 's', 32, 0, /* 9475 */ 'l', 'd', 'a', 't', 32, 0, /* 9481 */ 's', 't', 'd', 'a', 't', 32, 0, /* 9488 */ 'e', 'v', 'l', 'h', 'h', 'e', 's', 'p', 'l', 'a', 't', 32, 0, /* 9501 */ 'e', 'v', 'l', 'w', 'h', 's', 'p', 'l', 'a', 't', 32, 0, /* 9513 */ 'e', 'v', 'l', 'h', 'h', 'o', 's', 's', 'p', 'l', 'a', 't', 32, 0, /* 9527 */ 'e', 'v', 'l', 'h', 'h', 'o', 'u', 's', 'p', 'l', 'a', 't', 32, 0, /* 9541 */ 'e', 'v', 'l', 'w', 'w', 's', 'p', 'l', 'a', 't', 32, 0, /* 9553 */ 'l', 'w', 'a', 't', 32, 0, /* 9559 */ 's', 't', 'w', 'a', 't', 32, 0, /* 9566 */ 'd', 'c', 'b', 't', 32, 0, /* 9572 */ 'i', 'c', 'b', 't', 32, 0, /* 9578 */ 'd', 'c', 'b', 't', 'c', 't', 32, 0, /* 9586 */ 'd', 'c', 'b', 't', 's', 't', 'c', 't', 32, 0, /* 9596 */ 'e', 'f', 'd', 'c', 'm', 'p', 'g', 't', 32, 0, /* 9606 */ 'q', 'v', 'f', 'c', 'm', 'p', 'g', 't', 32, 0, /* 9616 */ 'e', 'f', 's', 'c', 'm', 'p', 'g', 't', 32, 0, /* 9626 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'g', 't', 32, 0, /* 9637 */ 'e', 'f', 'd', 't', 's', 't', 'g', 't', 32, 0, /* 9647 */ 'e', 'f', 's', 't', 's', 't', 'g', 't', 32, 0, /* 9657 */ 'e', 'v', 'f', 's', 't', 's', 't', 'g', 't', 32, 0, /* 9668 */ 'w', 'a', 'i', 't', 32, 0, /* 9674 */ 'e', 'f', 'd', 'c', 'm', 'p', 'l', 't', 32, 0, /* 9684 */ 'q', 'v', 'f', 'c', 'm', 'p', 'l', 't', 32, 0, /* 9694 */ 'e', 'f', 's', 'c', 'm', 'p', 'l', 't', 32, 0, /* 9704 */ 'e', 'v', 'f', 's', 'c', 'm', 'p', 'l', 't', 32, 0, /* 9715 */ 'e', 'f', 'd', 't', 's', 't', 'l', 't', 32, 0, /* 9725 */ 'e', 'f', 's', 't', 's', 't', 'l', 't', 32, 0, /* 9735 */ 'e', 'v', 'f', 's', 't', 's', 't', 'l', 't', 32, 0, /* 9746 */ 'f', 's', 'q', 'r', 't', 32, 0, /* 9753 */ 'f', 't', 's', 'q', 'r', 't', 32, 0, /* 9761 */ 'p', 'a', 's', 't', 'e', '_', 'l', 'a', 's', 't', 32, 0, /* 9773 */ 'v', 'n', 'c', 'i', 'p', 'h', 'e', 'r', 'l', 'a', 's', 't', 32, 0, /* 9787 */ 'v', 'c', 'i', 'p', 'h', 'e', 'r', 'l', 'a', 's', 't', 32, 0, /* 9800 */ 'd', 'c', 'b', 's', 't', 32, 0, /* 9807 */ 'd', 's', 't', 32, 0, /* 9812 */ 'c', 'o', 'p', 'y', '_', 'f', 'i', 'r', 's', 't', 32, 0, /* 9824 */ 'd', 'c', 'b', 't', 's', 't', 32, 0, /* 9832 */ 'd', 's', 't', 's', 't', 32, 0, /* 9839 */ 'd', 'c', 'b', 't', 't', 32, 0, /* 9846 */ 'd', 's', 't', 't', 32, 0, /* 9852 */ 'd', 'c', 'b', 't', 's', 't', 't', 32, 0, /* 9861 */ 'd', 's', 't', 's', 't', 't', 32, 0, /* 9869 */ 'l', 'h', 'a', 'u', 32, 0, /* 9875 */ 's', 't', 'b', 'u', 32, 0, /* 9881 */ 'l', 'f', 'd', 'u', 32, 0, /* 9887 */ 's', 't', 'f', 'd', 'u', 32, 0, /* 9894 */ 'm', 'a', 'd', 'd', 'h', 'd', 'u', 32, 0, /* 9903 */ 'm', 'u', 'l', 'h', 'd', 'u', 32, 0, /* 9911 */ 'q', 'v', 'f', 'c', 'f', 'i', 'd', 'u', 32, 0, /* 9921 */ 'q', 'v', 'f', 'c', 't', 'i', 'd', 'u', 32, 0, /* 9931 */ 'l', 'd', 'u', 32, 0, /* 9936 */ 's', 't', 'd', 'u', 32, 0, /* 9942 */ 'd', 'i', 'v', 'd', 'u', 32, 0, /* 9949 */ 'd', 'i', 'v', 'd', 'e', 'u', 32, 0, /* 9957 */ 'd', 'i', 'v', 'w', 'e', 'u', 32, 0, /* 9965 */ 's', 't', 'h', 'u', 32, 0, /* 9971 */ 'e', 'v', 's', 'r', 'w', 'i', 'u', 32, 0, /* 9980 */ 'e', 'v', 'l', 'w', 'h', 'o', 'u', 32, 0, /* 9989 */ 'f', 'c', 'm', 'p', 'u', 32, 0, /* 9996 */ 'l', 'f', 's', 'u', 32, 0, /* 10002 */ 's', 't', 'f', 's', 'u', 32, 0, /* 10009 */ 'e', 'v', 'c', 'm', 'p', 'g', 't', 'u', 32, 0, /* 10019 */ 'e', 'v', 'c', 'm', 'p', 'l', 't', 'u', 32, 0, /* 10029 */ 'm', 'u', 'l', 'h', 'w', 'u', 32, 0, /* 10037 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 'u', 32, 0, /* 10047 */ 'e', 'v', 's', 'r', 'w', 'u', 32, 0, /* 10055 */ 's', 't', 'w', 'u', 32, 0, /* 10061 */ 'e', 'v', 'd', 'i', 'v', 'w', 'u', 32, 0, /* 10070 */ 'l', 'b', 'z', 'u', 32, 0, /* 10076 */ 'l', 'h', 'z', 'u', 32, 0, /* 10082 */ 'l', 'w', 'z', 'u', 32, 0, /* 10088 */ 's', 'l', 'b', 'm', 'f', 'e', 'v', 32, 0, /* 10097 */ 'e', 'f', 'd', 'd', 'i', 'v', 32, 0, /* 10105 */ 'f', 'd', 'i', 'v', 32, 0, /* 10111 */ 'e', 'f', 's', 'd', 'i', 'v', 32, 0, /* 10119 */ 'e', 'v', 'f', 's', 'd', 'i', 'v', 32, 0, /* 10128 */ 'f', 't', 'd', 'i', 'v', 32, 0, /* 10135 */ 'v', 's', 'l', 'v', 32, 0, /* 10141 */ 'x', 'x', 'l', 'e', 'q', 'v', 32, 0, /* 10149 */ 'c', 'r', 'e', 'q', 'v', 32, 0, /* 10156 */ 'e', 'v', 'e', 'q', 'v', 32, 0, /* 10163 */ 'v', 's', 'r', 'v', 32, 0, /* 10169 */ 'l', 'x', 'v', 32, 0, /* 10174 */ 's', 't', 'x', 'v', 32, 0, /* 10180 */ 'v', 'e', 'x', 't', 's', 'b', '2', 'w', 32, 0, /* 10190 */ 'v', 'e', 'x', 't', 's', 'h', '2', 'w', 32, 0, /* 10200 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'a', 'w', 32, 0, /* 10213 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'a', 'w', 32, 0, /* 10226 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'a', 'w', 32, 0, /* 10239 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'a', 'w', 32, 0, /* 10252 */ 'e', 'v', 'a', 'd', 'd', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10265 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10278 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10292 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10305 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10318 */ 'e', 'v', 'a', 'd', 'd', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10331 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10344 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10358 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10371 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'a', 'w', 32, 0, /* 10384 */ 'e', 'v', 'a', 'd', 'd', 's', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10397 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10410 */ 'e', 'v', 's', 'u', 'b', 'f', 's', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10424 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10437 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10450 */ 'e', 'v', 'a', 'd', 'd', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10463 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10476 */ 'e', 'v', 's', 'u', 'b', 'f', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10490 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10503 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'a', 'w', 32, 0, /* 10516 */ 'v', 's', 'h', 'a', 's', 'i', 'g', 'm', 'a', 'w', 32, 0, /* 10528 */ 'v', 's', 'r', 'a', 'w', 32, 0, /* 10535 */ 'v', 'p', 'r', 't', 'y', 'b', 'w', 32, 0, /* 10544 */ 'e', 'v', 'a', 'd', 'd', 'w', 32, 0, /* 10552 */ 'e', 'v', 'l', 'd', 'w', 32, 0, /* 10559 */ 'e', 'v', 'r', 'n', 'd', 'w', 32, 0, /* 10567 */ 'e', 'v', 's', 't', 'd', 'w', 32, 0, /* 10575 */ 'v', 'm', 'r', 'g', 'e', 'w', 32, 0, /* 10583 */ 'v', 'c', 'm', 'p', 'n', 'e', 'w', 32, 0, /* 10592 */ 'e', 'v', 's', 'u', 'b', 'f', 'w', 32, 0, /* 10601 */ 'e', 'v', 's', 'u', 'b', 'i', 'f', 'w', 32, 0, /* 10611 */ 'v', 'n', 'e', 'g', 'w', 32, 0, /* 10618 */ 'v', 'm', 'r', 'g', 'h', 'w', 32, 0, /* 10626 */ 'x', 'x', 'm', 'r', 'g', 'h', 'w', 32, 0, /* 10635 */ 'm', 'u', 'l', 'h', 'w', 32, 0, /* 10642 */ 'e', 'v', 'a', 'd', 'd', 'i', 'w', 32, 0, /* 10651 */ 'q', 'v', 'f', 'c', 't', 'i', 'w', 32, 0, /* 10660 */ 'v', 'm', 'r', 'g', 'l', 'w', 32, 0, /* 10668 */ 'x', 'x', 'm', 'r', 'g', 'l', 'w', 32, 0, /* 10677 */ 'm', 'u', 'l', 'l', 'w', 32, 0, /* 10684 */ 'c', 'm', 'p', 'l', 'w', 32, 0, /* 10691 */ 'e', 'v', 'r', 'l', 'w', 32, 0, /* 10698 */ 'e', 'v', 's', 'l', 'w', 32, 0, /* 10705 */ 'l', 'm', 'w', 32, 0, /* 10710 */ 's', 't', 'm', 'w', 32, 0, /* 10716 */ 'v', 'p', 'm', 's', 'u', 'm', 'w', 32, 0, /* 10725 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'f', 'a', 'n', 'w', 32, 0, /* 10738 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'f', 'a', 'n', 'w', 32, 0, /* 10751 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'f', 'a', 'n', 'w', 32, 0, /* 10764 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'f', 'a', 'n', 'w', 32, 0, /* 10777 */ 'e', 'v', 'm', 'h', 'e', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, /* 10790 */ 'e', 'v', 'm', 'w', 'l', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, /* 10803 */ 'e', 'v', 'm', 'h', 'o', 's', 'm', 'i', 'a', 'n', 'w', 32, 0, /* 10816 */ 'e', 'v', 'm', 'h', 'e', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, /* 10829 */ 'e', 'v', 'm', 'w', 'l', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, /* 10842 */ 'e', 'v', 'm', 'h', 'o', 'u', 'm', 'i', 'a', 'n', 'w', 32, 0, /* 10855 */ 'e', 'v', 'm', 'h', 'e', 's', 's', 'i', 'a', 'n', 'w', 32, 0, /* 10868 */ 'e', 'v', 'm', 'w', 'l', 's', 's', 'i', 'a', 'n', 'w', 32, 0, /* 10881 */ 'e', 'v', 'm', 'h', 'o', 's', 's', 'i', 'a', 'n', 'w', 32, 0, /* 10894 */ 'e', 'v', 'm', 'h', 'e', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, /* 10907 */ 'e', 'v', 'm', 'w', 'l', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, /* 10920 */ 'e', 'v', 'm', 'h', 'o', 'u', 's', 'i', 'a', 'n', 'w', 32, 0, /* 10933 */ 'v', 'm', 'r', 'g', 'o', 'w', 32, 0, /* 10941 */ 'c', 'm', 'p', 'w', 32, 0, /* 10947 */ 'x', 'x', 'b', 'r', 'w', 32, 0, /* 10954 */ 'v', 's', 'r', 'w', 32, 0, /* 10960 */ 'm', 'o', 'd', 's', 'w', 32, 0, /* 10967 */ 'v', 'm', 'u', 'l', 'e', 's', 'w', 32, 0, /* 10976 */ 'v', 'a', 'v', 'g', 's', 'w', 32, 0, /* 10984 */ 'v', 'u', 'p', 'k', 'h', 's', 'w', 32, 0, /* 10993 */ 'v', 's', 'p', 'l', 't', 'i', 's', 'w', 32, 0, /* 11003 */ 'v', 'u', 'p', 'k', 'l', 's', 'w', 32, 0, /* 11012 */ 'e', 'v', 'c', 'n', 't', 'l', 's', 'w', 32, 0, /* 11022 */ 'v', 'm', 'i', 'n', 's', 'w', 32, 0, /* 11030 */ 'v', 'm', 'u', 'l', 'o', 's', 'w', 32, 0, /* 11039 */ 'v', 'c', 'm', 'p', 'g', 't', 's', 'w', 32, 0, /* 11049 */ 'e', 'x', 't', 's', 'w', 32, 0, /* 11056 */ 'v', 'm', 'a', 'x', 's', 'w', 32, 0, /* 11064 */ 'v', 's', 'p', 'l', 't', 'w', 32, 0, /* 11072 */ 'x', 'x', 's', 'p', 'l', 't', 'w', 32, 0, /* 11081 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 32, 0, /* 11091 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'w', 32, 0, /* 11101 */ 'x', 'x', 'i', 'n', 's', 'e', 'r', 't', 'w', 32, 0, /* 11112 */ 's', 't', 'w', 32, 0, /* 11117 */ 'v', 's', 'u', 'b', 'c', 'u', 'w', 32, 0, /* 11126 */ 'v', 'a', 'd', 'd', 'c', 'u', 'w', 32, 0, /* 11135 */ 'm', 'o', 'd', 'u', 'w', 32, 0, /* 11142 */ 'v', 'a', 'b', 's', 'd', 'u', 'w', 32, 0, /* 11151 */ 'v', 'm', 'u', 'l', 'e', 'u', 'w', 32, 0, /* 11160 */ 'v', 'a', 'v', 'g', 'u', 'w', 32, 0, /* 11168 */ 'v', 'm', 'i', 'n', 'u', 'w', 32, 0, /* 11176 */ 'v', 'm', 'u', 'l', 'o', 'u', 'w', 32, 0, /* 11185 */ 'v', 'c', 'm', 'p', 'e', 'q', 'u', 'w', 32, 0, /* 11195 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'w', 32, 0, /* 11207 */ 'x', 'x', 'e', 'x', 't', 'r', 'a', 'c', 't', 'u', 'w', 32, 0, /* 11220 */ 'v', 'c', 'm', 'p', 'g', 't', 'u', 'w', 32, 0, /* 11230 */ 'v', 'm', 'a', 'x', 'u', 'w', 32, 0, /* 11238 */ 'd', 'i', 'v', 'w', 32, 0, /* 11244 */ 'v', 'c', 'm', 'p', 'n', 'e', 'z', 'w', 32, 0, /* 11254 */ 'v', 'c', 'l', 'z', 'w', 32, 0, /* 11261 */ 'e', 'v', 'c', 'n', 't', 'l', 'z', 'w', 32, 0, /* 11271 */ 'v', 'c', 't', 'z', 'w', 32, 0, /* 11278 */ 'c', 'n', 't', 't', 'z', 'w', 32, 0, /* 11286 */ 'l', 'x', 'v', 'd', '2', 'x', 32, 0, /* 11294 */ 's', 't', 'x', 'v', 'd', '2', 'x', 32, 0, /* 11303 */ 'l', 'x', 'v', 'w', '4', 'x', 32, 0, /* 11311 */ 's', 't', 'x', 'v', 'w', '4', 'x', 32, 0, /* 11320 */ 'l', 'x', 'v', 'b', '1', '6', 'x', 32, 0, /* 11329 */ 's', 't', 'x', 'v', 'b', '1', '6', 'x', 32, 0, /* 11339 */ 'l', 'x', 'v', 'h', '8', 'x', 32, 0, /* 11347 */ 's', 't', 'x', 'v', 'h', '8', 'x', 32, 0, /* 11356 */ 'l', 'h', 'a', 'x', 32, 0, /* 11362 */ 't', 'l', 'b', 'i', 'v', 'a', 'x', 32, 0, /* 11371 */ 'q', 'v', 'l', 'f', 'i', 'w', 'a', 'x', 32, 0, /* 11381 */ 'l', 'x', 's', 'i', 'w', 'a', 'x', 32, 0, /* 11390 */ 'l', 'w', 'a', 'x', 32, 0, /* 11396 */ 'l', 'v', 'e', 'b', 'x', 32, 0, /* 11403 */ 's', 't', 'v', 'e', 'b', 'x', 32, 0, /* 11411 */ 's', 't', 'x', 's', 'i', 'b', 'x', 32, 0, /* 11420 */ 's', 't', 'b', 'x', 32, 0, /* 11426 */ 'q', 'v', 'l', 'f', 'c', 'd', 'x', 32, 0, /* 11435 */ 'q', 'v', 's', 't', 'f', 'c', 'd', 'x', 32, 0, /* 11445 */ 'e', 'v', 'l', 'd', 'd', 'x', 32, 0, /* 11453 */ 'e', 'v', 's', 't', 'd', 'd', 'x', 32, 0, /* 11462 */ 'q', 'v', 'l', 'f', 'd', 'x', 32, 0, /* 11470 */ 'q', 'v', 's', 't', 'f', 'd', 'x', 32, 0, /* 11479 */ 'q', 'v', 'l', 'p', 'c', 'l', 'd', 'x', 32, 0, /* 11489 */ 'q', 'v', 'l', 'p', 'c', 'r', 'd', 'x', 32, 0, /* 11499 */ 'l', 'x', 's', 'd', 'x', 32, 0, /* 11506 */ 's', 't', 'x', 's', 'd', 'x', 32, 0, /* 11514 */ 's', 't', 'd', 'x', 32, 0, /* 11520 */ 'e', 'v', 'l', 'w', 'h', 'e', 'x', 32, 0, /* 11529 */ 'e', 'v', 's', 't', 'w', 'h', 'e', 'x', 32, 0, /* 11539 */ 'e', 'v', 's', 't', 'w', 'w', 'e', 'x', 32, 0, /* 11549 */ 'e', 'v', 'l', 'd', 'h', 'x', 32, 0, /* 11557 */ 'e', 'v', 's', 't', 'd', 'h', 'x', 32, 0, /* 11566 */ 'l', 'v', 'e', 'h', 'x', 32, 0, /* 11573 */ 's', 't', 'v', 'e', 'h', 'x', 32, 0, /* 11581 */ 's', 't', 'x', 's', 'i', 'h', 'x', 32, 0, /* 11590 */ 's', 't', 'h', 'x', 32, 0, /* 11596 */ 's', 't', 'b', 'c', 'i', 'x', 32, 0, /* 11604 */ 'l', 'd', 'c', 'i', 'x', 32, 0, /* 11611 */ 's', 't', 'd', 'c', 'i', 'x', 32, 0, /* 11619 */ 's', 't', 'h', 'c', 'i', 'x', 32, 0, /* 11627 */ 's', 't', 'w', 'c', 'i', 'x', 32, 0, /* 11635 */ 'l', 'b', 'z', 'c', 'i', 'x', 32, 0, /* 11643 */ 'l', 'h', 'z', 'c', 'i', 'x', 32, 0, /* 11651 */ 'l', 'w', 'z', 'c', 'i', 'x', 32, 0, /* 11659 */ 'x', 's', 'r', 'q', 'p', 'i', 'x', 32, 0, /* 11668 */ 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0, /* 14276 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0, /* 14295 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0, /* 14314 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '8', 0, /* 14325 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', 0, /* 14346 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', 0, /* 14366 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', '8', 0, /* 14379 */ '#', 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', '8', 0, /* 14395 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', '8', 0, /* 14412 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', '8', 0, /* 14429 */ '#', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'i', '8', 0, /* 14445 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'o', 'c', 'H', 'A', 0, /* 14457 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'g', 'd', 'H', 'A', 0, /* 14471 */ '#', 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'l', 'd', 'H', 'A', 0, /* 14485 */ '#', 'A', 'D', 'D', 'I', 'S', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'H', 'A', 0, /* 14502 */ '#', 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', 0, /* 14517 */ '#', 'R', 'e', 'a', 'd', 'T', 'B', 0, /* 14525 */ '#', 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', 0, /* 14535 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'B', 'R', 'C', 0, /* 14551 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'B', 'R', 'C', 0, /* 14564 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'R', 'C', 0, /* 14580 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'F', 'R', 'C', 0, /* 14593 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'F', 'R', 'C', 0, /* 14610 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'F', 'R', 'C', 0, /* 14624 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'R', 'R', 'C', 0, /* 14640 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'R', 'R', 'C', 0, /* 14653 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'S', 'R', 'C', 0, /* 14669 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'Q', 'S', 'R', 'C', 0, /* 14682 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'S', 'R', 'C', 0, /* 14699 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'S', 'R', 'C', 0, /* 14713 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'V', 'S', 'R', 'C', 0, /* 14729 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'V', 'S', 'R', 'C', 0, /* 14742 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'L', 'D', 0, /* 14757 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 14770 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 14777 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'S', 'P', 'E', 0, /* 14792 */ '#', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 'P', 'E', 0, /* 14804 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 14814 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0, /* 14830 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'V', 'R', 'S', 'A', 'V', 'E', 0, /* 14844 */ '#', 'L', 'D', 't', 'o', 'c', 'J', 'T', 'I', 0, /* 14854 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, /* 14864 */ '#', 'L', 'D', 't', 'o', 'c', 'L', 0, /* 14872 */ '#', 'A', 'D', 'D', 'I', 't', 'o', 'c', 'L', 0, /* 14882 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 0, /* 14894 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 0, /* 14906 */ '#', 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', 0, /* 14919 */ '#', 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', 0, /* 14932 */ '#', 'U', 'p', 'd', 'a', 't', 'e', 'G', 'B', 'R', 0, /* 14943 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 0, /* 14955 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 0, /* 14965 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', 0, /* 14981 */ '#', 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', 0, /* 14997 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', 0, /* 15011 */ '#', 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', 0, /* 15023 */ '#', 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', 0, /* 15035 */ '#', 'M', 'o', 'v', 'e', 'G', 'O', 'T', 't', 'o', 'L', 'R', 0, /* 15048 */ '#', 'T', 'C', 'H', 'E', 'C', 'K', '_', 'R', 'E', 'T', 0, /* 15060 */ '#', 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', 0, /* 15075 */ '#', 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 'B', 'I', 'T', 0, /* 15090 */ '#', 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 'B', 'I', 'T', 0, /* 15103 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', 0, /* 15119 */ '#', 'A', 'N', 'D', 'I', 'o', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', 0, /* 15135 */ '#', 'P', 'P', 'C', '3', '2', 'G', 'O', 'T', 0, /* 15145 */ '#', 'P', 'P', 'C', '3', '2', 'P', 'I', 'C', 'G', 'O', 'T', 0, /* 15158 */ '#', 'L', 'D', 't', 'o', 'c', 'C', 'P', 'T', 0, /* 15168 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 15183 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 0, /* 15198 */ '#', 'L', 'I', 'W', 'A', 'X', 0, /* 15205 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'L', 'D', 'X', 0, /* 15221 */ '#', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 'X', 0, /* 15237 */ '#', 'S', 'T', 'I', 'W', 'X', 0, /* 15244 */ '#', 'L', 'I', 'W', 'Z', 'X', 0, /* 15251 */ 'b', 'c', 'a', 0, /* 15255 */ 's', 'l', 'b', 'i', 'a', 0, /* 15261 */ 't', 'l', 'b', 'i', 'a', 0, /* 15267 */ 'b', 'c', 'l', 'a', 0, /* 15272 */ 'c', 'l', 'r', 'b', 'h', 'r', 'b', 0, /* 15280 */ 'b', 'c', 0, /* 15283 */ 's', 'l', 'b', 's', 'y', 'n', 'c', 0, /* 15291 */ 't', 'l', 'b', 's', 'y', 'n', 'c', 0, /* 15299 */ 'm', 's', 'g', 's', 'y', 'n', 'c', 0, /* 15307 */ 'i', 's', 'y', 'n', 'c', 0, /* 15313 */ 'm', 's', 'y', 'n', 'c', 0, /* 15319 */ '#', 'L', 'D', 't', 'o', 'c', 0, /* 15326 */ '#', 'L', 'W', 'Z', 't', 'o', 'c', 0, /* 15334 */ 'h', 'r', 'f', 'i', 'd', 0, /* 15340 */ 't', 'l', 'b', 'r', 'e', 0, /* 15346 */ 't', 'l', 'b', 'w', 'e', 0, /* 15352 */ 'r', 'f', 'c', 'i', 0, /* 15357 */ 'r', 'f', 'm', 'c', 'i', 0, /* 15363 */ 'r', 'f', 'd', 'i', 0, /* 15368 */ 'r', 'f', 'i', 0, /* 15372 */ 'b', 'c', 'l', 0, /* 15376 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 15390 */ 'd', 's', 's', 'a', 'l', 'l', 0, /* 15397 */ 'b', 'l', 'r', 'l', 0, /* 15402 */ 'b', 'd', 'z', 'l', 'r', 'l', 0, /* 15409 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', 0, /* 15417 */ 'b', 'c', 't', 'r', 'l', 0, /* 15423 */ 'a', 't', 't', 'n', 0, /* 15428 */ 'e', 'i', 'e', 'i', 'o', 0, /* 15434 */ 'n', 'a', 'p', 0, /* 15438 */ 't', 'r', 'a', 'p', 0, /* 15443 */ 'n', 'o', 'p', 0, /* 15447 */ 's', 't', 'o', 'p', 0, /* 15452 */ 'b', 'l', 'r', 0, /* 15456 */ 'b', 'd', 'z', 'l', 'r', 0, /* 15462 */ 'b', 'd', 'n', 'z', 'l', 'r', 0, /* 15469 */ 'b', 'c', 't', 'r', 0, /* 15474 */ 'c', 'p', '_', 'a', 'b', 'o', 'r', 't', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 14805U, // DBG_VALUE 14855U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 14771U, // BUNDLE 15169U, // LIFETIME_START 14758U, // LIFETIME_END 0U, // STACKMAP 15377U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 12827U, // PATCHABLE_FUNCTION_ENTER 12747U, // PATCHABLE_RET 12873U, // PATCHABLE_FUNCTION_EXIT 12850U, // PATCHABLE_TAIL_CALL 12802U, // PATCHABLE_EVENT_CALL 12778U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 14087U, // CFENCE8 21042U, // CLRLSLDI 17211U, // CLRLSLDIo 21551U, // CLRLSLWI 17320U, // CLRLSLWIo 21077U, // CLRRDI 17238U, // CLRRDIo 21592U, // CLRRWI 17349U, // CLRRWIo 536897109U, // CP_COPY_FIRST 536899711U, // CP_COPYx 536897058U, // CP_PASTE_LAST 536891262U, // CP_PASTEx 562481U, // DCBFL 564336U, // DCBFLP 561067U, // DCBFx 553690475U, // DCBTCT 553689756U, // DCBTDS 553690483U, // DCBTSTCT 553689764U, // DCBTSTDS 566909U, // DCBTSTT 566881U, // DCBTSTx 566896U, // DCBTT 566623U, // DCBTx 13334U, // DFLOADf32 13646U, // DFLOADf64 13356U, // DFSTOREf32 13668U, // DFSTOREf64 21052U, // EXTLDI 17222U, // EXTLDIo 21577U, // EXTLWI 17340U, // EXTLWIo 21101U, // EXTRDI 17265U, // EXTRDIo 21616U, // EXTRWI 17376U, // EXTRWIo 21561U, // INSLWI 17331U, // INSLWIo 21085U, // INSRDI 17247U, // INSRDIo 21600U, // INSRWI 17358U, // INSRWIo 33573242U, // LAx 15199U, // LIWAX 15245U, // LIWZX 21205U, // RLWIMIbm 17303U, // RLWIMIobm 22102U, // RLWINMbm 17434U, // RLWINMobm 22111U, // RLWNMbm 17443U, // RLWNMobm 21093U, // ROTRDI 17256U, // ROTRDIo 21608U, // ROTRWI 17367U, // ROTRWIo 21046U, // SLDI 17215U, // SLDIo 21555U, // SLWI 17324U, // SLWIo 14743U, // SPILLTOVSR_LD 15206U, // SPILLTOVSR_LDX 15184U, // SPILLTOVSR_ST 15222U, // SPILLTOVSR_STX 21087U, // SRDI 17249U, // SRDIo 21602U, // SRWI 17360U, // SRWIo 15238U, // STIWX 20993U, // SUBI 19522U, // SUBIC 16795U, // SUBICo 25475U, // SUBIS 50357130U, // SUBPCIS 13345U, // XFLOADf32 13657U, // XFLOADf64 13368U, // XFSTOREf32 13680U, // XFSTOREf64 19705U, // ADD4 19705U, // ADD4TLS 16867U, // ADD4o 19705U, // ADD8 19705U, // ADD8TLS 19705U, // ADD8TLS_ 16867U, // ADD8o 19484U, // ADDC 19484U, // ADDC8 16762U, // ADDC8o 16762U, // ADDCo 20235U, // ADDE 20235U, // ADDE8 17006U, // ADDE8o 17006U, // ADDEo 21028U, // ADDI 21028U, // ADDI8 19529U, // ADDIC 19529U, // ADDIC8 16803U, // ADDICo 25500U, // ADDIS 25500U, // ADDIS8 14503U, // ADDISdtprelHA 12929U, // ADDISdtprelHA32 14486U, // ADDISgotTprelHA 14458U, // ADDIStlsgdHA 14472U, // ADDIStlsldHA 14446U, // ADDIStocHA 14920U, // ADDIdtprelL 13218U, // ADDIdtprelL32 14883U, // ADDItlsgdL 13175U, // ADDItlsgdL32 14966U, // ADDItlsgdLADDR 13270U, // ADDItlsgdLADDR32 14895U, // ADDItlsldL 13189U, // ADDItlsldL32 14982U, // ADDItlsldLADDR 13288U, // ADDItlsldLADDR32 14873U, // ADDItocL 536891214U, // ADDME 536891214U, // ADDME8 536887941U, // ADDME8o 536887941U, // ADDMEo 536896403U, // ADDPCIS 536891292U, // ADDZE 536891292U, // ADDZE8 536887990U, // ADDZE8o 536887990U, // ADDZEo 51111U, // ADJCALLSTACKDOWN 51130U, // ADJCALLSTACKUP 19976U, // AND 19976U, // AND8 16929U, // AND8o 19493U, // ANDC 19493U, // ANDC8 16769U, // ANDC8o 16769U, // ANDCo 17833U, // ANDISo 17833U, // ANDISo8 17231U, // ANDIo 17231U, // ANDIo8 15104U, // ANDIo_1_EQ_BIT 14396U, // ANDIo_1_EQ_BIT8 15120U, // ANDIo_1_GT_BIT 14413U, // ANDIo_1_GT_BIT8 16929U, // ANDo 1141917528U, // ATOMIC_CMP_SWAP_I16 1141917506U, // ATOMIC_CMP_SWAP_I32 13504U, // ATOMIC_CMP_SWAP_I64 14257U, // ATOMIC_CMP_SWAP_I8 13868U, // ATOMIC_LOAD_ADD_I16 12967U, // ATOMIC_LOAD_ADD_I32 13401U, // ATOMIC_LOAD_ADD_I64 14155U, // ATOMIC_LOAD_ADD_I8 13911U, // ATOMIC_LOAD_AND_I16 13010U, // ATOMIC_LOAD_AND_I32 13692U, // ATOMIC_LOAD_AND_I64 14196U, // ATOMIC_LOAD_AND_I8 14055U, // ATOMIC_LOAD_MAX_I16 13154U, // ATOMIC_LOAD_MAX_I32 13588U, // ATOMIC_LOAD_MAX_I64 14347U, // ATOMIC_LOAD_MAX_I8 13954U, // ATOMIC_LOAD_MIN_I16 13053U, // ATOMIC_LOAD_MIN_I32 13466U, // ATOMIC_LOAD_MIN_I64 14237U, // ATOMIC_LOAD_MIN_I8 13889U, // ATOMIC_LOAD_NAND_I16 12988U, // ATOMIC_LOAD_NAND_I32 13422U, // ATOMIC_LOAD_NAND_I64 14175U, // ATOMIC_LOAD_NAND_I8 14013U, // ATOMIC_LOAD_OR_I16 13112U, // ATOMIC_LOAD_OR_I32 13546U, // ATOMIC_LOAD_OR_I64 14296U, // ATOMIC_LOAD_OR_I8 13847U, // ATOMIC_LOAD_SUB_I16 12946U, // ATOMIC_LOAD_SUB_I32 13380U, // ATOMIC_LOAD_SUB_I64 14121U, // ATOMIC_LOAD_SUB_I8 14033U, // ATOMIC_LOAD_UMAX_I16 13132U, // ATOMIC_LOAD_UMAX_I32 13566U, // ATOMIC_LOAD_UMAX_I64 14326U, // ATOMIC_LOAD_UMAX_I8 13932U, // ATOMIC_LOAD_UMIN_I16 13031U, // ATOMIC_LOAD_UMIN_I32 13444U, // ATOMIC_LOAD_UMIN_I64 14216U, // ATOMIC_LOAD_UMIN_I8 13992U, // ATOMIC_LOAD_XOR_I16 13091U, // ATOMIC_LOAD_XOR_I32 13525U, // ATOMIC_LOAD_XOR_I64 14277U, // ATOMIC_LOAD_XOR_I8 13975U, // ATOMIC_SWAP_I16 13074U, // ATOMIC_SWAP_I32 13487U, // ATOMIC_SWAP_I64 14430U, // ATOMIC_SWAP_I8 15424U, // ATTN 592514U, // B 608340U, // BA 83902568U, // BC 1686447U, // BCC 2210735U, // BCCA 2735023U, // BCCCTR 2735023U, // BCCCTR8 3259311U, // BCCCTRL 3259311U, // BCCCTRL8 3783599U, // BCCL 4307887U, // BCCLA 4832175U, // BCCLR 5356463U, // BCCLRL 5783706U, // BCCTR 5783706U, // BCCTR8 5783762U, // BCCTR8n 5783684U, // BCCTRL 5783684U, // BCCTRL8 5783742U, // BCCTRL8n 5783742U, // BCCTRLn 5783762U, // BCCTRn 17451U, // BCDCFNo 17654U, // BCDCFSQo 18172U, // BCDCFZo 17460U, // BCDCPSGNo 536888420U, // BCDCTNo 536888576U, // BCDCTSQo 18188U, // BCDCTZo 17480U, // BCDSETSGNo 17709U, // BCDSRo 17765U, // BCDSo 16819U, // BCDTRUNCo 17858U, // BCDUSo 16830U, // BCDUTRUNCo 83902576U, // BCL 5783696U, // BCLR 5783673U, // BCLRL 5783732U, // BCLRLn 5783753U, // BCLRn 589901U, // BCLalways 83902636U, // BCLn 15470U, // BCTR 15470U, // BCTR8 15418U, // BCTRL 15418U, // BCTRL8 114778U, // BCTRL8_LDinto_toc 83902629U, // BCn 602413U, // BDNZ 602413U, // BDNZ8 608887U, // BDNZA 606464U, // BDNZAm 606249U, // BDNZAp 595380U, // BDNZL 608651U, // BDNZLA 606448U, // BDNZLAm 606233U, // BDNZLAp 15463U, // BDNZLR 15463U, // BDNZLR8 15410U, // BDNZLRL 12723U, // BDNZLRLm 12680U, // BDNZLRLp 12739U, // BDNZLRm 12696U, // BDNZLRp 590095U, // BDNZLm 589880U, // BDNZLp 590109U, // BDNZm 589894U, // BDNZp 602256U, // BDZ 602256U, // BDZ8 608881U, // BDZA 606457U, // BDZAm 606242U, // BDZAp 595374U, // BDZL 608644U, // BDZLA 606440U, // BDZLAm 606225U, // BDZLAp 15457U, // BDZLR 15457U, // BDZLR8 15403U, // BDZLRL 12715U, // BDZLRLm 12672U, // BDZLRLp 12732U, // BDZLRm 12689U, // BDZLRp 590088U, // BDZLm 589873U, // BDZLp 590103U, // BDZm 589888U, // BDZp 595190U, // BL 595190U, // BL8 6362358U, // BL8_NOP 6427894U, // BL8_NOP_TLS 660726U, // BL8_TLS 660726U, // BL8_TLS_ 608633U, // BLA 608633U, // BLA8 6375801U, // BLA8_NOP 15453U, // BLR 15453U, // BLR8 15398U, // BLRL 660726U, // BL_TLS 19956U, // BPERMD 19585U, // BRINC 15273U, // CLRBHRB 19160U, // CMPB 19160U, // CMPB8 20020U, // CMPD 21070U, // CMPDI 19166U, // CMPEQB 19927U, // CMPLD 21034U, // CMPLDI 27069U, // CMPLW 21535U, // CMPLWI 100682470U, // CMPRB 100682470U, // CMPRB8 27326U, // CMPW 21585U, // CMPWI 536891107U, // CNTLZD 536887900U, // CNTLZDo 536898560U, // CNTLZW 536898560U, // CNTLZW8 536889017U, // CNTLZW8o 536889017U, // CNTLZWo 536891122U, // CNTTZD 536887909U, // CNTTZDo 536898575U, // CNTTZW 536898575U, // CNTTZW8 536889026U, // CNTTZW8o 536889026U, // CNTTZWo 15475U, // CP_ABORT 28799U, // CP_COPY 28799U, // CP_COPY8 20350U, // CP_PASTE 20350U, // CP_PASTE8 17062U, // CP_PASTE8o 17062U, // CP_PASTEo 13806U, // CR6SET 13792U, // CR6UNSET 20006U, // CRAND 19499U, // CRANDC 26534U, // CREQV 19990U, // CRNAND 24864U, // CRNOR 24878U, // CROR 19606U, // CRORC 117467046U, // CRSET 117465420U, // CRUNSET 24908U, // CRXOR 1686447U, // CTRL_DEP 536893342U, // DARN 559186U, // DCBA 151467U, // DCBF 564087U, // DCBFEP 561653U, // DCBI 566857U, // DCBST 564120U, // DCBSTEP 157023U, // DCBT 170896U, // DCBTEP 157281U, // DCBTST 170913U, // DCBTSTEP 569477U, // DCBZ 564139U, // DCBZEP 562599U, // DCBZL 564103U, // DCBZLEP 536891911U, // DCCCI 20182U, // DIVD 20241U, // DIVDE 26334U, // DIVDEU 17936U, // DIVDEUo 17013U, // DIVDEo 26327U, // DIVDU 17928U, // DIVDUo 16981U, // DIVDo 27623U, // DIVW 20364U, // DIVWE 26342U, // DIVWEU 17945U, // DIVWEUo 17070U, // DIVWEo 26448U, // DIVWU 17972U, // DIVWUo 18087U, // DIVWo 713696U, // DSS 15391U, // DSSALL 1745036880U, // DST 1745036880U, // DST64 1745036905U, // DSTST 1745036905U, // DSTST64 1745036934U, // DSTSTT 1745036934U, // DSTSTT64 1745036919U, // DSTT 1745036919U, // DSTT64 14526U, // DYNALLOC 14076U, // DYNALLOC8 15061U, // DYNAREAOFFSET 14380U, // DYNAREAOFFSET8 536895901U, // EFDABS 19702U, // EFDADD 536896266U, // EFDCFS 536891387U, // EFDCFSF 536892298U, // EFDCFSI 536890788U, // EFDCFSID 536891489U, // EFDCFUF 536892375U, // EFDCFUI 536890807U, // EFDCFUID 24525U, // EFDCMPEQ 25981U, // EFDCMPGT 26059U, // EFDCMPLT 536891461U, // EFDCTSF 536892326U, // EFDCTSI 536899733U, // EFDCTSIDZ 536899834U, // EFDCTSIZ 536891517U, // EFDCTUF 536892403U, // EFDCTUI 536899754U, // EFDCTUIDZ 536899865U, // EFDCTUIZ 26482U, // EFDDIV 21859U, // EFDMUL 536895917U, // EFDNABS 536891543U, // EFDNEG 19374U, // EFDSUB 24575U, // EFDTSTEQ 26022U, // EFDTSTGT 26100U, // EFDTSTLT 536895954U, // EFSABS 19785U, // EFSADD 536890738U, // EFSCFD 536891396U, // EFSCFSF 536892307U, // EFSCFSI 536891498U, // EFSCFUF 536892384U, // EFSCFUI 24545U, // EFSCMPEQ 26001U, // EFSCMPGT 26079U, // EFSCMPLT 536891470U, // EFSCTSF 536892335U, // EFSCTSI 536899844U, // EFSCTSIZ 536891526U, // EFSCTUF 536892412U, // EFSCTUI 536899875U, // EFSCTUIZ 26496U, // EFSDIV 21875U, // EFSMUL 536895935U, // EFSNABS 536891559U, // EFSNEG 19409U, // EFSSUB 24585U, // EFSTSTEQ 26032U, // EFSTSTGT 26110U, // EFSTSTLT 13233U, // EH_SjLj_LongJmp32 13609U, // EH_SjLj_LongJmp64 13252U, // EH_SjLj_SetJmp32 13628U, // EH_SjLj_SetJmp64 589825U, // EH_SjLj_Setup 26529U, // EQV 26529U, // EQV8 17987U, // EQV8o 17987U, // EQVo 536895971U, // EVABS 16804243U, // EVADDIW 536897549U, // EVADDSMIAAW 536897681U, // EVADDSSIAAW 536897615U, // EVADDUMIAAW 536897747U, // EVADDUSIAAW 26929U, // EVADDW 20013U, // EVAND 19507U, // EVANDC 24566U, // EVCMPEQ 25591U, // EVCMPGTS 26394U, // EVCMPGTU 25601U, // EVCMPLTS 26404U, // EVCMPLTU 536898309U, // EVCNTLSW 536898558U, // EVCNTLZW 25763U, // EVDIVWS 26446U, // EVDIVWU 26541U, // EVEQV 536890171U, // EVEXTSB 536891736U, // EVEXTSH 536895962U, // EVFSABS 19793U, // EVFSADD 536891405U, // EVFSCFSF 536892316U, // EVFSCFSI 536891507U, // EVFSCFUF 536892393U, // EVFSCFUI 24555U, // EVFSCMPEQ 26011U, // EVFSCMPGT 26089U, // EVFSCMPLT 536891479U, // EVFSCTSF 536892344U, // EVFSCTSI 536899854U, // EVFSCTSIZ 536891479U, // EVFSCTUF 536892421U, // EVFSCTUI 536899854U, // EVFSCTUIZ 26504U, // EVFSDIV 21883U, // EVFSMUL 536895944U, // EVFSNABS 536891567U, // EVFSNEG 19417U, // EVFSSUB 24595U, // EVFSTSTEQ 26042U, // EVFSTSTGT 26120U, // EVFSTSTLT 33574234U, // EVLDD 604007606U, // EVLDDX 33575110U, // EVLDH 604007710U, // EVLDHX 33581369U, // EVLDW 604008463U, // EVLDWX 33580305U, // EVLHHESPLAT 604008203U, // EVLHHESPLATX 33580330U, // EVLHHOSSPLAT 604008230U, // EVLHHOSSPLATX 33580344U, // EVLHHOUSPLAT 604008245U, // EVLHHOUSPLATX 33574703U, // EVLWHE 604007681U, // EVLWHEX 33579987U, // EVLWHOS 604008175U, // EVLWHOSX 33580797U, // EVLWHOU 604008361U, // EVLWHOUX 33580318U, // EVLWHSPLAT 604008217U, // EVLWHSPLATX 33580358U, // EVLWWSPLAT 604008260U, // EVLWWSPLATX 21141U, // EVMERGEHI 22475U, // EVMERGEHILO 22464U, // EVMERGELO 21152U, // EVMERGELOHI 18392U, // EVMHEGSMFAA 22234U, // EVMHEGSMFAN 18440U, // EVMHEGSMIAA 22282U, // EVMHEGSMIAN 18477U, // EVMHEGUMIAA 22319U, // EVMHEGUMIAN 20407U, // EVMHESMF 18525U, // EVMHESMFA 26585U, // EVMHESMFAAW 27110U, // EVMHESMFANW 21213U, // EVMHESMI 18616U, // EVMHESMIA 26650U, // EVMHESMIAAW 27162U, // EVMHESMIANW 20510U, // EVMHESSF 18568U, // EVMHESSFA 26611U, // EVMHESSFAAW 27136U, // EVMHESSFANW 26782U, // EVMHESSIAAW 27240U, // EVMHESSIANW 21252U, // EVMHEUMI 18659U, // EVMHEUMIA 26716U, // EVMHEUMIAAW 27201U, // EVMHEUMIANW 26848U, // EVMHEUSIAAW 27279U, // EVMHEUSIANW 18405U, // EVMHOGSMFAA 22247U, // EVMHOGSMFAN 18453U, // EVMHOGSMIAA 22295U, // EVMHOGSMIAN 18490U, // EVMHOGUMIAA 22332U, // EVMHOGUMIAN 20427U, // EVMHOSMF 18547U, // EVMHOSMFA 26598U, // EVMHOSMFAAW 27123U, // EVMHOSMFANW 21233U, // EVMHOSMI 18638U, // EVMHOSMIA 26690U, // EVMHOSMIAAW 27188U, // EVMHOSMIANW 20530U, // EVMHOSSF 18590U, // EVMHOSSFA 26624U, // EVMHOSSFAAW 27149U, // EVMHOSSFANW 26822U, // EVMHOSSIAAW 27266U, // EVMHOSSIANW 21282U, // EVMHOUMI 18692U, // EVMHOUMIA 26756U, // EVMHOUMIAAW 27227U, // EVMHOUMIANW 26888U, // EVMHOUSIAAW 27305U, // EVMHOUSIANW 536889747U, // EVMRA 20417U, // EVMWHSMF 18536U, // EVMWHSMFA 21223U, // EVMWHSMI 18627U, // EVMWHSMIA 20520U, // EVMWHSSF 18579U, // EVMWHSSFA 21262U, // EVMWHUMI 18670U, // EVMWHUMIA 26677U, // EVMWLSMIAAW 27175U, // EVMWLSMIANW 26809U, // EVMWLSSIAAW 27253U, // EVMWLSSIANW 21272U, // EVMWLUMI 18681U, // EVMWLUMIA 26743U, // EVMWLUMIAAW 27214U, // EVMWLUMIANW 26875U, // EVMWLUSIAAW 27292U, // EVMWLUSIANW 20437U, // EVMWSMF 18558U, // EVMWSMFA 18418U, // EVMWSMFAA 22260U, // EVMWSMFAN 21243U, // EVMWSMI 18649U, // EVMWSMIA 18466U, // EVMWSMIAA 22308U, // EVMWSMIAN 20540U, // EVMWSSF 18601U, // EVMWSSFA 18429U, // EVMWSSFAA 22271U, // EVMWSSFAN 21292U, // EVMWUMI 18703U, // EVMWUMIA 18503U, // EVMWUMIAA 22345U, // EVMWUMIAN 19998U, // EVNAND 536891576U, // EVNEG 24871U, // EVNOR 24884U, // EVOR 19613U, // EVORC 27076U, // EVRLW 21543U, // EVRLWI 536897856U, // EVRNDW 2154328480U, // EVSEL 27083U, // EVSLW 21569U, // EVSLWI 151016074U, // EVSPLATFI 151016397U, // EVSPLATI 25519U, // EVSRWIS 26356U, // EVSRWIU 25691U, // EVSRWS 26432U, // EVSRWU 33574250U, // EVSTDD 604007614U, // EVSTDDX 33575117U, // EVSTDH 604007718U, // EVSTDHX 33581384U, // EVSTDW 604008471U, // EVSTDWX 33574711U, // EVSTWHE 604007690U, // EVSTWHEX 33576887U, // EVSTWHO 604007872U, // EVSTWHOX 33574803U, // EVSTWWE 604007700U, // EVSTWWEX 33577040U, // EVSTWWO 604007882U, // EVSTWWOX 536897575U, // EVSUBFSMIAAW 536897707U, // EVSUBFSSIAAW 536897641U, // EVSUBFUMIAAW 536897773U, // EVSUBFUSIAAW 26977U, // EVSUBFW 167799146U, // EVSUBIFW 24915U, // EVXOR 536890173U, // EXTSB 536890173U, // EXTSB8 536890173U, // EXTSB8_32_64 536887609U, // EXTSB8o 536887609U, // EXTSBo 536891738U, // EXTSH 536891738U, // EXTSH8 536891738U, // EXTSH8_32_64 536888050U, // EXTSH8o 536888050U, // EXTSHo 536898346U, // EXTSW 21179U, // EXTSWSLI 17283U, // EXTSWSLIo 536898346U, // EXTSW_32 536898346U, // EXTSW_32_64 536888969U, // EXTSW_32_64o 536888969U, // EXTSWo 15429U, // EnforceIEIO 536895911U, // FABSD 536888635U, // FABSDo 536895911U, // FABSS 536888635U, // FABSSo 19712U, // FADD 25154U, // FADDS 17772U, // FADDSo 16866U, // FADDo 0U, // FADDrtz 536890781U, // FCFID 536896148U, // FCFIDS 536888711U, // FCFIDSo 536897210U, // FCFIDU 536896533U, // FCFIDUS 536888778U, // FCFIDUSo 536888822U, // FCFIDUo 536887810U, // FCFIDo 26374U, // FCMPUD 26374U, // FCMPUS 22369U, // FCPSGND 17471U, // FCPSGNDo 22369U, // FCPSGNS 17471U, // FCPSGNSo 536890800U, // FCTID 536897220U, // FCTIDU 536899893U, // FCTIDUZ 536889109U, // FCTIDUZo 536888831U, // FCTIDUo 536899746U, // FCTIDZ 536889075U, // FCTIDZo 536887818U, // FCTIDo 536897950U, // FCTIW 536897336U, // FCTIWU 536899904U, // FCTIWUZ 536889119U, // FCTIWUZo 536888875U, // FCTIWUo 536899915U, // FCTIWZ 536889129U, // FCTIWZo 536888930U, // FCTIWo 26490U, // FDIV 25684U, // FDIVS 17876U, // FDIVSo 17980U, // FDIVo 19720U, // FMADD 25163U, // FMADDS 17780U, // FMADDSo 16873U, // FMADDo 536895725U, // FMR 536888603U, // FMRo 19392U, // FMSUB 25133U, // FMSUBS 17746U, // FMSUBSo 16723U, // FMSUBo 21869U, // FMUL 25538U, // FMULS 17841U, // FMULSo 17409U, // FMULo 536895928U, // FNABSD 536888642U, // FNABSDo 536895928U, // FNABSS 536888642U, // FNABSSo 536891553U, // FNEGD 536888022U, // FNEGDo 536891553U, // FNEGS 536888022U, // FNEGSo 19729U, // FNMADD 25173U, // FNMADDS 17789U, // FNMADDSo 16881U, // FNMADDo 19401U, // FNMSUB 25143U, // FNMSUBS 17755U, // FNMSUBSo 16731U, // FNMSUBo 536891238U, // FRE 536896248U, // FRES 536888720U, // FRESo 536887958U, // FREo 536893000U, // FRIMD 536888339U, // FRIMDo 536893000U, // FRIMS 536888339U, // FRIMSo 536893298U, // FRIND 536888413U, // FRINDo 536893298U, // FRINS 536888413U, // FRINSo 536894570U, // FRIPD 536888508U, // FRIPDo 536894570U, // FRIPS 536888508U, // FRIPSo 536899828U, // FRIZD 536889093U, // FRIZDo 536899828U, // FRIZS 536889093U, // FRIZSo 536895271U, // FRSP 536888539U, // FRSPo 536891253U, // FRSQRTE 536896256U, // FRSQRTES 536888727U, // FRSQRTESo 536887964U, // FRSQRTEo 21784U, // FSELD 17402U, // FSELDo 21784U, // FSELS 17402U, // FSELSo 536897043U, // FSQRT 536896523U, // FSQRTS 536888761U, // FSQRTSo 536888805U, // FSQRTo 19384U, // FSUB 25124U, // FSUBS 17738U, // FSUBSo 16716U, // FSUBo 26513U, // FTDIV 536897050U, // FTSQRT 15012U, // GETtlsADDR 13321U, // GETtlsADDR32 14998U, // GETtlsldADDR 13306U, // GETtlsldADDR32 15335U, // HRFID 561659U, // ICBI 564095U, // ICBIEP 216186U, // ICBLC 214254U, // ICBLQ 222565U, // ICBT 222136U, // ICBTLS 536891918U, // ICCCI 21790U, // ISEL 21790U, // ISEL8 15308U, // ISYNC 184568186U, // LA 604007996U, // LBARX 2751491644U, // LBARXL 604007892U, // LBEPX 33583243U, // LBZ 33583243U, // LBZ8 28020U, // LBZCIX 201353047U, // LBZU 201353047U, // LBZU8 218132450U, // LBZUX 218132450U, // LBZUX8 604008529U, // LBZX 604008529U, // LBZX8 28753U, // LBZXTLS 28753U, // LBZXTLS_ 28753U, // LBZXTLS_32 33574340U, // LD 604008003U, // LDARX 2751491651U, // LDARXL 25860U, // LDAT 604008024U, // LDBRX 27989U, // LDCIX 604007859U, // LDMX 201352908U, // LDU 218132366U, // LDUX 604007645U, // LDX 27869U, // LDXTLS 27869U, // LDXTLS_ 14907U, // LDgotTprelL 13203U, // LDgotTprelL32 15320U, // LDtoc 15159U, // LDtocBA 15159U, // LDtocCPT 14845U, // LDtocJTI 14865U, // LDtocL 33574266U, // LFD 604007907U, // LFDEPX 201352858U, // LFDU 218132349U, // LFDUX 604007625U, // LFDX 604007534U, // LFIWAX 604008552U, // LFIWZX 33579800U, // LFS 201352973U, // LFSU 218132426U, // LFSUX 604008150U, // LFSX 33573043U, // LHA 33573043U, // LHA8 604008010U, // LHARX 2751491658U, // LHARXL 201352846U, // LHAU 201352846U, // LHAU8 218132305U, // LHAUX 218132305U, // LHAUX8 604007517U, // LHAX 604007517U, // LHAX8 604008039U, // LHBRX 604008039U, // LHBRX8 604007924U, // LHEPX 33583307U, // LHZ 33583307U, // LHZ8 28028U, // LHZCIX 201353053U, // LHZU 201353053U, // LHZU8 218132457U, // LHZUX 218132457U, // LHZUX8 604008544U, // LHZX 604008544U, // LHZX8 28768U, // LHZXTLS 28768U, // LHZXTLS_ 28768U, // LHZXTLS_32 50352816U, // LI 50352816U, // LI8 50357155U, // LIS 50357155U, // LIS8 33581522U, // LMW 21624U, // LSWI 604007557U, // LVEBX 604007727U, // LVEHX 604008480U, // LVEWX 604001629U, // LVSL 604004738U, // LVSR 604008439U, // LVX 604001690U, // LVXL 33573274U, // LWA 604008017U, // LWARX 2751491665U, // LWARXL 25938U, // LWAT 218132312U, // LWAUX 604007551U, // LWAX 604007551U, // LWAX_32 33573274U, // LWA_32 604008064U, // LWBRX 604008064U, // LWBRX8 604007939U, // LWEPX 33583443U, // LWZ 33583443U, // LWZ8 28036U, // LWZCIX 201353059U, // LWZU 201353059U, // LWZU8 218132464U, // LWZUX 218132464U, // LWZUX8 604008569U, // LWZX 604008569U, // LWZX8 28793U, // LWZXTLS 28793U, // LWZXTLS_ 28793U, // LWZXTLS_32 15327U, // LWZtoc 33574522U, // LXSD 604007660U, // LXSDX 604008520U, // LXSIBZX 604008535U, // LXSIHZX 604007542U, // LXSIWAX 604008560U, // LXSIWZX 33578823U, // LXSSP 604007979U, // LXSSPX 33580986U, // LXV 604007481U, // LXVB16X 604007447U, // LXVD2X 604008133U, // LXVDSX 604007500U, // LXVH8X 21901U, // LXVL 21816U, // LXVLL 604007464U, // LXVW4X 604008195U, // LXVWSX 604008450U, // LXVX 19852U, // MADDHD 26279U, // MADDHDU 19912U, // MADDLD 712845U, // MBAR 536891358U, // MCRF 536896285U, // MCRFS 552611U, // MCRXRX 234901242U, // MFBHRBE 549032U, // MFCR 549032U, // MFCR8 549263U, // MFCTR 549263U, // MFCTR8 536895635U, // MFDCR 549650U, // MFFS 536893357U, // MFFSCDRN 251679569U, // MFFSCDRNI 544515U, // MFFSCE 536893348U, // MFFSCRN 268456775U, // MFFSCRNI 546134U, // MFFSL 542114U, // MFFSo 549087U, // MFLR 549087U, // MFLR8 549230U, // MFMSR 285233124U, // MFOCRF 285233124U, // MFOCRF8 536895730U, // MFPMR 536895834U, // MFSPR 536895834U, // MFSPR8 302014824U, // MFSR 536893304U, // MFSRIN 536890194U, // MFTB 7364954U, // MFTB8 536890953U, // MFVRD 7889242U, // MFVRSAVE 7889242U, // MFVRSAVEv 549046U, // MFVSCR 536890953U, // MFVSRD 536890846U, // MFVSRLD 536899928U, // MFVSRWZ 20057U, // MODSD 27345U, // MODSW 20139U, // MODUD 27520U, // MODUW 15300U, // MSGSYNC 15314U, // MSYNC 536891380U, // MTCRF 536891380U, // MTCRF8 549270U, // MTCTR 549270U, // MTCTR8 549270U, // MTCTR8loop 549270U, // MTCTRloop 654516385U, // MTDCR 706354U, // MTFSB0 706362U, // MTFSB1 20503U, // MTFSF 21122U, // MTFSFI 17274U, // MTFSFIo 536891415U, // MTFSFb 17102U, // MTFSFo 549093U, // MTLR 549093U, // MTLR8 536895861U, // MTMSR 536890945U, // MTMSRD 233452U, // MTOCRF 233452U, // MTOCRF8 536895737U, // MTPMR 536895841U, // MTSPR 536895841U, // MTSPR8 254332U, // MTSR 536893312U, // MTSRIN 540892U, // MTVRSAVE 721116U, // MTVRSAVEv 549054U, // MTVSCR 536890961U, // MTVSRD 19809U, // MTVSRDD 536889759U, // MTVSRWA 536896611U, // MTVSRWS 536899937U, // MTVSRWZ 19860U, // MULHD 26288U, // MULHDU 17901U, // MULHDUo 16890U, // MULHDo 27020U, // MULHW 26414U, // MULHWU 17954U, // MULHWUo 18010U, // MULHWo 19920U, // MULLD 16914U, // MULLDo 21172U, // MULLI 21172U, // MULLI8 27062U, // MULLW 18026U, // MULLWo 15036U, // MoveGOTtoLR 15024U, // MovePCtoLR 14367U, // MovePCtoLR8 19984U, // NAND 19984U, // NAND8 16928U, // NAND8o 16928U, // NANDo 15435U, // NAP 536891546U, // NEG 536891546U, // NEG8 536888023U, // NEG8o 536888023U, // NEGo 15444U, // NOP 12905U, // NOP_GT_PWR6 12917U, // NOP_GT_PWR7 24859U, // NOR 24859U, // NOR8 17697U, // NOR8o 17697U, // NORo 24852U, // OR 24852U, // OR8 17698U, // OR8o 19601U, // ORC 19601U, // ORC8 16842U, // ORC8o 16842U, // ORCo 21381U, // ORI 21381U, // ORI8 25513U, // ORIS 25513U, // ORIS8 17698U, // ORo 536890209U, // POPCNTB 536891027U, // POPCNTD 536898379U, // POPCNTW 15136U, // PPC32GOT 15146U, // PPC32PICGOT 21309U, // QVALIGNI 21309U, // QVALIGNIb 21309U, // QVALIGNIs 21442U, // QVESPLATI 21442U, // QVESPLATIb 21442U, // QVESPLATIs 536895909U, // QVFABS 536895909U, // QVFABSs 19710U, // QVFADD 25152U, // QVFADDS 25152U, // QVFADDSs 536890779U, // QVFCFID 536896146U, // QVFCFIDS 536897208U, // QVFCFIDU 536896531U, // QVFCFIDUS 536890779U, // QVFCFIDb 24535U, // QVFCMPEQ 24535U, // QVFCMPEQb 24535U, // QVFCMPEQbs 25991U, // QVFCMPGT 25991U, // QVFCMPGTb 25991U, // QVFCMPGTbs 26069U, // QVFCMPLT 26069U, // QVFCMPLTb 26069U, // QVFCMPLTbs 22367U, // QVFCPSGN 22367U, // QVFCPSGNs 536890798U, // QVFCTID 536897218U, // QVFCTIDU 536899891U, // QVFCTIDUZ 536899744U, // QVFCTIDZ 536890798U, // QVFCTIDb 536897948U, // QVFCTIW 536897334U, // QVFCTIWU 536899902U, // QVFCTIWUZ 536899913U, // QVFCTIWZ 21738U, // QVFLOGICAL 21738U, // QVFLOGICALb 21738U, // QVFLOGICALs 19718U, // QVFMADD 25161U, // QVFMADDS 25161U, // QVFMADDSs 536895723U, // QVFMR 536895723U, // QVFMRb 536895723U, // QVFMRs 19390U, // QVFMSUB 25131U, // QVFMSUBS 25131U, // QVFMSUBSs 21867U, // QVFMUL 25536U, // QVFMULS 25536U, // QVFMULSs 536895926U, // QVFNABS 536895926U, // QVFNABSs 536891551U, // QVFNEG 536891551U, // QVFNEGs 19727U, // QVFNMADD 25171U, // QVFNMADDS 25171U, // QVFNMADDSs 19399U, // QVFNMSUB 25141U, // QVFNMSUBS 25141U, // QVFNMSUBSs 22156U, // QVFPERM 22156U, // QVFPERMs 536891236U, // QVFRE 536896246U, // QVFRES 536896246U, // QVFRESs 536892998U, // QVFRIM 536892998U, // QVFRIMs 536893296U, // QVFRIN 536893296U, // QVFRINs 536894568U, // QVFRIP 536894568U, // QVFRIPs 536899826U, // QVFRIZ 536899826U, // QVFRIZs 536895269U, // QVFRSP 536895269U, // QVFRSPs 536891251U, // QVFRSQRTE 536896254U, // QVFRSQRTES 536896254U, // QVFRSQRTESs 21782U, // QVFSEL 21782U, // QVFSELb 21782U, // QVFSELbb 21782U, // QVFSELbs 19382U, // QVFSUB 25122U, // QVFSUBS 25122U, // QVFSUBSs 22356U, // QVFTSTNAN 22356U, // QVFTSTNANb 22356U, // QVFTSTNANbs 19764U, // QVFXMADD 25211U, // QVFXMADDS 21892U, // QVFXMUL 25545U, // QVFXMULS 19737U, // QVFXXCPNMADD 25182U, // QVFXXCPNMADDS 19774U, // QVFXXMADD 25222U, // QVFXXMADDS 19751U, // QVFXXNPMADD 25197U, // QVFXXNPMADDS 318788117U, // QVGPCI 604008294U, // QVLFCDUX 603998723U, // QVLFCDUXA 604007587U, // QVLFCDX 603998643U, // QVLFCDXA 604008371U, // QVLFCSUX 603998767U, // QVLFCSUXA 604008114U, // QVLFCSX 603998683U, // QVLFCSXA 604008114U, // QVLFCSXs 218132347U, // QVLFDUX 603998746U, // QVLFDUXA 604007623U, // QVLFDX 603998664U, // QVLFDXA 604007623U, // QVLFDXb 604007532U, // QVLFIWAX 603998632U, // QVLFIWAXA 604008550U, // QVLFIWZX 603998822U, // QVLFIWZXA 218132424U, // QVLFSUX 603998790U, // QVLFSUXA 604008148U, // QVLFSX 603998704U, // QVLFSXA 604008148U, // QVLFSXb 604008148U, // QVLFSXs 604007640U, // QVLPCLDX 604008165U, // QVLPCLSX 8416997U, // QVLPCLSXint 604007650U, // QVLPCRDX 604008185U, // QVLPCRSX 604008304U, // QVSTFCDUX 603998734U, // QVSTFCDUXA 604001460U, // QVSTFCDUXI 603998535U, // QVSTFCDUXIA 604007596U, // QVSTFCDX 603998653U, // QVSTFCDXA 604001418U, // QVSTFCDXI 603998489U, // QVSTFCDXIA 604008381U, // QVSTFCSUX 603998778U, // QVSTFCSUXA 604001483U, // QVSTFCSUXI 603998560U, // QVSTFCSUXIA 604008123U, // QVSTFCSX 603998693U, // QVSTFCSXA 604001439U, // QVSTFCSXI 603998512U, // QVSTFCSXIA 604008123U, // QVSTFCSXs 218312580U, // QVSTFDUX 603998756U, // QVSTFDUXA 604001472U, // QVSTFDUXI 603998548U, // QVSTFDUXIA 604007631U, // QVSTFDX 603998673U, // QVSTFDXA 604001429U, // QVSTFDXI 603998501U, // QVSTFDXIA 604007631U, // QVSTFDXb 604008495U, // QVSTFIWX 603998811U, // QVSTFIWXA 218312657U, // QVSTFSUX 603998800U, // QVSTFSUXA 604001495U, // QVSTFSUXI 603998573U, // QVSTFSUXIA 218312657U, // QVSTFSUXs 604008156U, // QVSTFSX 603998713U, // QVSTFSXA 604001450U, // QVSTFSXI 603998524U, // QVSTFSXIA 604008156U, // QVSTFSXs 14944U, // RESTORE_CR 15076U, // RESTORE_CRBIT 14815U, // RESTORE_VRSAVE 15353U, // RFCI 15364U, // RFDI 264837U, // RFEBB 15369U, // RFI 15336U, // RFID 15358U, // RFMCI 21759U, // RLDCL 17385U, // RLDCLo 24730U, // RLDCR 17674U, // RLDCRo 19536U, // RLDIC 21766U, // RLDICL 21766U, // RLDICL_32 21766U, // RLDICL_32_64 17393U, // RLDICL_32o 17393U, // RLDICLo 24750U, // RLDICR 24750U, // RLDICR_32 17682U, // RLDICRo 16811U, // RLDICo 3355464397U, // RLDIMI 3355460494U, // RLDIMIo 3892335317U, // RLWIMI 3892335317U, // RLWIMI8 3892331415U, // RLWIMI8o 3892331415U, // RLWIMIo 22102U, // RLWINM 22102U, // RLWINM8 17434U, // RLWINM8o 17434U, // RLWINMo 22111U, // RLWNM 22111U, // RLWNM8 17443U, // RLWNM8o 17443U, // RLWNMo 14518U, // ReadTB 543908U, // SC 13820U, // SELECT_CC_F16 13742U, // SELECT_CC_F4 14096U, // SELECT_CC_F8 13767U, // SELECT_CC_I4 14141U, // SELECT_CC_I8 14536U, // SELECT_CC_QBRC 14565U, // SELECT_CC_QFRC 14654U, // SELECT_CC_QSRC 14778U, // SELECT_CC_SPE 13713U, // SELECT_CC_SPE4 14625U, // SELECT_CC_VRRC 14594U, // SELECT_CC_VSFRC 14714U, // SELECT_CC_VSRC 14683U, // SELECT_CC_VSSRC 13835U, // SELECT_F16 13756U, // SELECT_F4 14110U, // SELECT_F8 13781U, // SELECT_I4 14315U, // SELECT_I8 14552U, // SELECT_QBRC 14581U, // SELECT_QFRC 14670U, // SELECT_QSRC 14793U, // SELECT_SPE 13729U, // SELECT_SPE4 14641U, // SELECT_VRRC 14611U, // SELECT_VSFRC 14730U, // SELECT_VSRC 14700U, // SELECT_VSSRC 536890188U, // SETB 15256U, // SLBIA 544576U, // SLBIE 536891535U, // SLBIEG 536891160U, // SLBMFEE 536897385U, // SLBMFEV 536891243U, // SLBMTE 15284U, // SLBSYNC 19950U, // SLD 16922U, // SLDo 27085U, // SLW 27085U, // SLW8 18034U, // SLW8o 18034U, // SLWo 33583443U, // SPELWZ 604008569U, // SPELWZX 33581929U, // SPESTW 604008514U, // SPESTWX 14956U, // SPILL_CR 15091U, // SPILL_CRBIT 14831U, // SPILL_VRSAVE 19680U, // SRAD 21021U, // SRADI 21021U, // SRADI_32 17203U, // SRADIo 16859U, // SRADo 26914U, // SRAW 21519U, // SRAWI 17312U, // SRAWIo 17993U, // SRAWo 20036U, // SRD 16942U, // SRDo 27340U, // SRW 27340U, // SRW8 18040U, // SRW8o 18040U, // SRWo 33573748U, // STB 33573748U, // STB8 27981U, // STBCIX 603997899U, // STBCX 604007899U, // STBEPX 201533076U, // STBU 201533076U, // STBU8 218312543U, // STBUX 218312543U, // STBUX8 604007581U, // STBX 604007581U, // STBX8 27805U, // STBXTLS 27805U, // STBXTLS_ 27805U, // STBXTLS_32 33574566U, // STD 25866U, // STDAT 604008031U, // STDBRX 27996U, // STDCIX 603997907U, // STDCX 201533137U, // STDU 218312596U, // STDUX 604007675U, // STDX 27899U, // STDXTLS 27899U, // STDXTLS_ 33574271U, // STFD 604007915U, // STFDEPX 201533088U, // STFDU 218312582U, // STFDUX 604007633U, // STFDX 604008497U, // STFIWX 33579812U, // STFS 201533203U, // STFSU 218312659U, // STFSUX 604008158U, // STFSX 33575301U, // STH 33575301U, // STH8 604008046U, // STHBRX 28004U, // STHCIX 603997915U, // STHCX 604007931U, // STHEPX 201533166U, // STHU 201533166U, // STHU8 218312610U, // STHUX 218312610U, // STHUX8 604007751U, // STHX 604007751U, // STHX8 27975U, // STHXTLS 27975U, // STHXTLS_ 27975U, // STHXTLS_32 33581527U, // STMW 15448U, // STOP 21630U, // STSWI 604007564U, // STVEBX 604007734U, // STVEHX 604008487U, // STVEWX 604008444U, // STVX 604001696U, // STVXL 33581929U, // STW 33581929U, // STW8 25944U, // STWAT 604008071U, // STWBRX 28012U, // STWCIX 603997923U, // STWCX 604007946U, // STWEPX 201533256U, // STWU 201533256U, // STWU8 218312667U, // STWUX 218312667U, // STWUX8 604008514U, // STWX 604008514U, // STWX8 28738U, // STWXTLS 28738U, // STWXTLS_ 28738U, // STWXTLS_32 33574528U, // STXSD 604007667U, // STXSDX 604007572U, // STXSIBX 604007572U, // STXSIBXv 604007742U, // STXSIHX 604007742U, // STXSIHXv 604008505U, // STXSIWX 33578830U, // STXSSP 604007987U, // STXSSPX 33580991U, // STXV 604007490U, // STXVB16X 604007455U, // STXVD2X 604007508U, // STXVH8X 21907U, // STXVL 21823U, // STXVLL 604007472U, // STXVW4X 604008456U, // STXVX 20401U, // SUBF 20401U, // SUBF8 17095U, // SUBF8o 19515U, // SUBFC 19515U, // SUBFC8 16787U, // SUBFC8o 16787U, // SUBFCo 20264U, // SUBFE 20264U, // SUBFE8 17021U, // SUBFE8o 17021U, // SUBFEo 19543U, // SUBFIC 19543U, // SUBFIC8 536891221U, // SUBFME 536891221U, // SUBFME8 536887949U, // SUBFME8o 536887949U, // SUBFMEo 536891299U, // SUBFZE 536891299U, // SUBFZE8 536887998U, // SUBFZE8o 536887998U, // SUBFZEo 17095U, // SUBFo 543880U, // SYNC 722396U, // TABORT 9191816U, // TABORTDC 9716507U, // TABORTDCI 9191888U, // TABORTWC 9716519U, // TABORTWCI 592514U, // TAILB 592514U, // TAILB8 608340U, // TAILBA 608340U, // TAILBA8 15470U, // TAILBCTR 15470U, // TAILBCTR8 263252U, // TBEGIN 546018U, // TCHECK 15049U, // TCHECK_RET 538003403U, // TCRETURNai 538003310U, // TCRETURNai8 537988294U, // TCRETURNdi 537986940U, // TCRETURNdi8 537944192U, // TCRETURNri 537937802U, // TCRETURNri8 183950U, // TD 184949U, // TDI 819751U, // TEND 15262U, // TLBIA 661327687U, // TLBIE 546062U, // TLBIEL 536898659U, // TLBIVAX 544193U, // TLBLD 545453U, // TLBLI 15341U, // TLBRE 20317U, // TLBRE2 536899243U, // TLBSX 28331U, // TLBSX2 18155U, // TLBSX2D 15292U, // TLBSYNC 15347U, // TLBWE 20357U, // TLBWE2 15439U, // TRAP 12895U, // TRECHKPT 721928U, // TRECLAIM 820533U, // TSR 191293U, // TW 185477U, // TWI 536889240U, // UPDATE_VRSAVE 14933U, // UpdateGBR 19321U, // VABSDUB 20874U, // VABSDUH 27527U, // VABSDUW 24652U, // VADDCUQ 27511U, // VADDCUW 24683U, // VADDECUQ 22146U, // VADDEUQM 23511U, // VADDFP 25085U, // VADDSBS 25428U, // VADDSHS 25727U, // VADDSWS 21966U, // VADDUBM 25113U, // VADDUBS 21994U, // VADDUDM 22033U, // VADDUHM 25456U, // VADDUHS 22127U, // VADDUQM 22216U, // VADDUWM 25754U, // VADDUWS 20014U, // VAND 19508U, // VANDC 19196U, // VAVGSB 20761U, // VAVGSH 27361U, // VAVGSW 19339U, // VAVGUB 20892U, // VAVGUH 27545U, // VAVGUW 19955U, // VBPERMD 24606U, // VBPERMQ 134246093U, // VCFSX 536899277U, // VCFSX_0 134246299U, // VCFUX 536899483U, // VCFUX_0 24784U, // VCIPHER 26172U, // VCIPHERLAST 536890378U, // VCLZB 536891100U, // VCLZD 536891879U, // VCLZH 536889996U, // VCLZLSBB 536898551U, // VCLZW 23475U, // VCMPBFP 17553U, // VCMPBFPo 23574U, // VCMPEQFP 17574U, // VCMPEQFPo 19364U, // VCMPEQUB 16705U, // VCMPEQUBo 20154U, // VCMPEQUD 16959U, // VCMPEQUDo 20917U, // VCMPEQUH 17146U, // VCMPEQUHo 27570U, // VCMPEQUW 18065U, // VCMPEQUWo 23528U, // VCMPGEFP 17563U, // VCMPGEFPo 23584U, // VCMPGTFP 17585U, // VCMPGTFPo 19249U, // VCMPGTSB 16686U, // VCMPGTSBo 20072U, // VCMPGTSD 16948U, // VCMPGTSDo 20814U, // VCMPGTSH 17127U, // VCMPGTSHo 27424U, // VCMPGTSW 18046U, // VCMPGTSWo 19438U, // VCMPGTUB 16740U, // VCMPGTUBo 20164U, // VCMPGTUD 16970U, // VCMPGTUDo 20939U, // VCMPGTUH 17157U, // VCMPGTUHo 27605U, // VCMPGTUW 18076U, // VCMPGTUWo 19104U, // VCMPNEB 16676U, // VCMPNEBo 20693U, // VCMPNEH 17117U, // VCMPNEHo 26968U, // VCMPNEW 18000U, // VCMPNEWo 19456U, // VCMPNEZB 16751U, // VCMPNEZBo 20957U, // VCMPNEZH 17168U, // VCMPNEZHo 27629U, // VCMPNEZW 18094U, // VCMPNEZWo 134243572U, // VCTSXS 536896756U, // VCTSXS_0 134243580U, // VCTUXS 536896764U, // VCTUXS_0 536890385U, // VCTZB 536891115U, // VCTZD 536891886U, // VCTZH 536890006U, // VCTZLSBB 536898568U, // VCTZW 26542U, // VEQV 536894457U, // VEXPTEFP 1207979655U, // VEXTRACTD 1207978978U, // VEXTRACTUB 1207980479U, // VEXTRACTUH 1207987132U, // VEXTRACTUW 536890536U, // VEXTSB2D 536890536U, // VEXTSB2Ds 536897477U, // VEXTSB2W 536897477U, // VEXTSB2Ws 536890546U, // VEXTSH2D 536890546U, // VEXTSH2Ds 536897487U, // VEXTSH2W 536897487U, // VEXTSH2Ws 536890556U, // VEXTSW2D 536890556U, // VEXTSW2Ds 28053U, // VEXTUBLX 28278U, // VEXTUBRX 28063U, // VEXTUHLX 28303U, // VEXTUHRX 28073U, // VEXTUWLX 28313U, // VEXTUWRX 536890598U, // VGBBD 335563626U, // VINSERTB 1207979676U, // VINSERTD 335565179U, // VINSERTH 1207987028U, // VINSERTW 536894431U, // VLOGEFP 23502U, // VMADDFP 23594U, // VMAXFP 19268U, // VMAXSB 20082U, // VMAXSD 20833U, // VMAXSH 27441U, // VMAXSW 19448U, // VMAXUB 20174U, // VMAXUD 20949U, // VMAXUH 27615U, // VMAXUW 25405U, // VMHADDSHS 25416U, // VMHRADDSHS 23566U, // VMINFP 19232U, // VMINSB 20064U, // VMINSD 20797U, // VMINSH 27407U, // VMINSW 19347U, // VMINUB 20146U, // VMINUD 20900U, // VMINUH 27553U, // VMINUW 22022U, // VMLADDUHM 26960U, // VMRGEW 19113U, // VMRGHB 20702U, // VMRGHH 27003U, // VMRGHW 19131U, // VMRGLB 20710U, // VMRGLH 27045U, // VMRGLW 27318U, // VMRGOW 21947U, // VMSUMMBM 22003U, // VMSUMSHM 25437U, // VMSUMSHS 21975U, // VMSUMUBM 22042U, // VMSUMUHM 25465U, // VMSUMUHS 536895544U, // VMUL10CUQ 24661U, // VMUL10ECUQ 24693U, // VMUL10EUQ 536895534U, // VMUL10UQ 19187U, // VMULESB 20752U, // VMULESH 27352U, // VMULESW 19330U, // VMULEUB 20883U, // VMULEUH 27536U, // VMULEUW 19240U, // VMULOSB 20805U, // VMULOSH 27415U, // VMULOSW 19355U, // VMULOUB 20908U, // VMULOUH 27561U, // VMULOUW 22225U, // VMULUWM 19999U, // VNAND 24774U, // VNCIPHER 26158U, // VNCIPHERLAST 536890757U, // VNEGD 536897908U, // VNEGW 23484U, // VNMSUBFP 24872U, // VNOR 24885U, // VOR 19614U, // VORC 22165U, // VPERM 24832U, // VPERMR 24898U, // VPERMXOR 28187U, // VPKPX 25564U, // VPKSDSS 25630U, // VPKSDUS 25573U, // VPKSHSS 25648U, // VPKSHUS 25582U, // VPKSWSS 25666U, // VPKSWUS 22180U, // VPKUDUM 25639U, // VPKUDUS 22189U, // VPKUHUM 25657U, // VPKUHUS 22198U, // VPKUWUM 25675U, // VPKUWUS 19151U, // VPMSUMB 19964U, // VPMSUMD 20730U, // VPMSUMH 27101U, // VPMSUMW 536890208U, // VPOPCNTB 536891026U, // VPOPCNTD 536891761U, // VPOPCNTH 536898378U, // VPOPCNTW 536890605U, // VPRTYBD 536895428U, // VPRTYBQ 536897832U, // VPRTYBW 536894450U, // VREFP 536892964U, // VRFIM 536893289U, // VRFIN 536894534U, // VRFIP 536899792U, // VRFIZ 19139U, // VRLB 19943U, // VRLD 21189U, // VRLDMI 22094U, // VRLDNM 20718U, // VRLH 27077U, // VRLW 21301U, // VRLWMI 22110U, // VRLWNM 536894467U, // VRSQRTEFP 536899001U, // VSBOX 21796U, // VSEL 19667U, // VSHASIGMAD 26901U, // VSHASIGMAW 21854U, // VSL 19145U, // VSLB 19949U, // VSLD 21340U, // VSLDOI 20724U, // VSLH 22488U, // VSLO 26520U, // VSLV 27084U, // VSLW 134237016U, // VSPLTB 134237016U, // VSPLTBs 134238569U, // VSPLTH 134238569U, // VSPLTHs 151014157U, // VSPLTISB 151015722U, // VSPLTISH 151022322U, // VSPLTISW 134245177U, // VSPLTW 24963U, // VSR 19070U, // VSRAB 19679U, // VSRAD 20671U, // VSRAH 26913U, // VSRAW 19181U, // VSRB 20043U, // VSRD 20746U, // VSRH 22602U, // VSRO 26548U, // VSRV 27339U, // VSRW 24643U, // VSUBCUQ 27502U, // VSUBCUW 24673U, // VSUBECUQ 22136U, // VSUBEUQM 23494U, // VSUBFP 25076U, // VSUBSBS 25396U, // VSUBSHS 25718U, // VSUBSWS 21957U, // VSUBUBM 25104U, // VSUBUBS 21985U, // VSUBUDM 22013U, // VSUBUHM 25447U, // VSUBUHS 22118U, // VSUBUQM 22207U, // VSUBUWM 25745U, // VSUBUWS 25708U, // VSUM2SWS 25066U, // VSUM4SBS 25386U, // VSUM4SHS 25094U, // VSUM4UBS 25736U, // VSUMSWS 536899090U, // VUPKHPX 536890116U, // VUPKHSB 536891681U, // VUPKHSH 536898281U, // VUPKHSW 536899106U, // VUPKLPX 536890135U, // VUPKLSB 536891700U, // VUPKLSH 536898300U, // VUPKLSW 24916U, // VXOR 117465428U, // V_SET0 117465428U, // V_SET0B 117465428U, // V_SET0H 9988850U, // V_SETALLONES 9988850U, // V_SETALLONESB 9988850U, // V_SETALLONESH 550341U, // WAIT 544545U, // WRTEE 545402U, // WRTEEI 24893U, // XOR 24893U, // XOR8 17703U, // XOR8o 21380U, // XORI 21380U, // XORI8 25512U, // XORIS 25512U, // XORIS8 17703U, // XORo 536894157U, // XSABSDP 536894776U, // XSABSQP 22769U, // XSADDDP 23734U, // XSADDQP 22561U, // XSADDQPO 24034U, // XSADDSP 23203U, // XSCMPEQDP 23171U, // XSCMPEXPDP 23832U, // XSCMPEXPQP 22831U, // XSCMPGEDP 23263U, // XSCMPGTDP 23101U, // XSCMPODP 23802U, // XSCMPOQP 23327U, // XSCMPUDP 23883U, // XSCMPUQP 23061U, // XSCPSGNDP 23791U, // XSCPSGNQP 536894514U, // XSCVDPHP 536894724U, // XSCVDPQP 536895208U, // XSCVDPSP 536893331U, // XSCVDPSPN 536896174U, // XSCVDPSXDS 536896174U, // XSCVDPSXDSs 536896684U, // XSCVDPSXWS 536896684U, // XSCVDPSXWSs 536896210U, // XSCVDPUXDS 536896210U, // XSCVDPUXDSs 536896720U, // XSCVDPUXWS 536896720U, // XSCVDPUXWSs 536894023U, // XSCVHPDP 536894033U, // XSCVQPDP 536893406U, // XSCVQPDPO 536899765U, // XSCVQPSDZ 536899946U, // XSCVQPSWZ 536899776U, // XSCVQPUDZ 536899957U, // XSCVQPUWZ 536894655U, // XSCVSDQP 536894043U, // XSCVSPDP 536893320U, // XSCVSPDPN 536893699U, // XSCVSXDDP 536894964U, // XSCVSXDSP 536894665U, // XSCVUDQP 536893721U, // XSCVUXDDP 536894986U, // XSCVUXDSP 23337U, // XSDIVDP 23893U, // XSDIVQP 22592U, // XSDIVQPO 24448U, // XSDIVSP 23151U, // XSIEXPDP 23822U, // XSIEXPQP 1744853151U, // XSMADDADP 1744854436U, // XSMADDASP 1744853503U, // XSMADDMDP 1744854718U, // XSMADDMSP 1744854188U, // XSMADDQP 1744853014U, // XSMADDQPO 22759U, // XSMAXCDP 23397U, // XSMAXDP 22941U, // XSMAXJDP 22749U, // XSMINCDP 23083U, // XSMINDP 22931U, // XSMINJDP 1744853105U, // XSMSUBADP 1744854390U, // XSMSUBASP 1744853457U, // XSMSUBMDP 1744854672U, // XSMSUBMSP 1744854147U, // XSMSUBQP 1744852981U, // XSMSUBQPO 22951U, // XSMULDP 23782U, // XSMULQP 22571U, // XSMULQPO 24166U, // XSMULSP 536894137U, // XSNABSDP 536894766U, // XSNABSQP 536893805U, // XSNEGDP 536894675U, // XSNEGQP 1744853127U, // XSNMADDADP 1744854412U, // XSNMADDASP 1744853479U, // XSNMADDMDP 1744854694U, // XSNMADDMSP 1744854177U, // XSNMADDQP 1744853002U, // XSNMADDQPO 1744853081U, // XSNMSUBADP 1744854366U, // XSNMSUBASP 1744853433U, // XSNMSUBMDP 1744854648U, // XSNMSUBMSP 1744854136U, // XSNMSUBQP 1744852969U, // XSNMSUBQPO 536892260U, // XSRDPI 536890463U, // XSRDPIC 536892971U, // XSRDPIM 536894541U, // XSRDPIP 536899799U, // XSRDPIZ 536893765U, // XSREDP 536895019U, // XSRESP 117740404U, // XSRQPI 117747084U, // XSRQPIX 117743547U, // XSRQPXP 536895277U, // XSRSP 536893781U, // XSRSQRTEDP 536895035U, // XSRSQRTESP 536894197U, // XSSQRTDP 536894785U, // XSSQRTQP 536893493U, // XSSQRTQPO 536895329U, // XSSQRTSP 22709U, // XSSUBDP 23693U, // XSSUBQP 22528U, // XSSUBQPO 23994U, // XSSUBSP 23346U, // XSTDIVDP 536894207U, // XSTSQRTDP 2281724103U, // XSTSTDCDP 2281725078U, // XSTSTDCQP 2281725388U, // XSTSTDCSP 536894095U, // XSXEXPDP 536894756U, // XSXEXPQP 536893823U, // XSXSIGDP 536894684U, // XSXSIGQP 536894166U, // XVABSDP 536895294U, // XVABSSP 22778U, // XVADDDP 24043U, // XVADDSP 23214U, // XVCMPEQDP 17529U, // XVCMPEQDPo 24346U, // XVCMPEQSP 17615U, // XVCMPEQSPo 22842U, // XVCMPGEDP 17517U, // XVCMPGEDPo 24096U, // XVCMPGESP 17603U, // XVCMPGESPo 23274U, // XVCMPGTDP 17541U, // XVCMPGTDPo 24406U, // XVCMPGTSP 17634U, // XVCMPGTSPo 23072U, // XVCPSGNDP 24276U, // XVCPSGNSP 536895218U, // XVCVDPSP 536896186U, // XVCVDPSXDS 536896696U, // XVCVDPSXWS 536896222U, // XVCVDPUXDS 536896732U, // XVCVDPUXWS 536895228U, // XVCVHPSP 536894053U, // XVCVSPDP 536894524U, // XVCVSPHP 536896198U, // XVCVSPSXDS 536896708U, // XVCVSPSXWS 536896234U, // XVCVSPUXDS 536896744U, // XVCVSPUXWS 536893710U, // XVCVSXDDP 536894975U, // XVCVSXDSP 536894287U, // XVCVSXWDP 536895388U, // XVCVSXWSP 536893732U, // XVCVUXDDP 536894997U, // XVCVUXDSP 536894298U, // XVCVUXWDP 536895399U, // XVCVUXWSP 23366U, // XVDIVDP 24467U, // XVDIVSP 23161U, // XVIEXPDP 24326U, // XVIEXPSP 1744853162U, // XVMADDADP 1744854447U, // XVMADDASP 1744853514U, // XVMADDMDP 1744854729U, // XVMADDMSP 23406U, // XVMAXDP 24498U, // XVMAXSP 23092U, // XVMINDP 24287U, // XVMINSP 1744853116U, // XVMSUBADP 1744854401U, // XVMSUBASP 1744853468U, // XVMSUBMDP 1744854683U, // XVMSUBMSP 22960U, // XVMULDP 24175U, // XVMULSP 536894147U, // XVNABSDP 536895284U, // XVNABSSP 536893814U, // XVNEGDP 536895059U, // XVNEGSP 1744853139U, // XVNMADDADP 1744854424U, // XVNMADDASP 1744853491U, // XVNMADDMDP 1744854706U, // XVNMADDMSP 1744853093U, // XVNMSUBADP 1744854378U, // XVNMSUBASP 1744853445U, // XVNMSUBMDP 1744854660U, // XVNMSUBMSP 536892268U, // XVRDPI 536890472U, // XVRDPIC 536892980U, // XVRDPIM 536894550U, // XVRDPIP 536899808U, // XVRDPIZ 536893773U, // XVREDP 536895027U, // XVRESP 536892284U, // XVRSPI 536890481U, // XVRSPIC 536892989U, // XVRSPIM 536894559U, // XVRSPIP 536899817U, // XVRSPIZ 536893793U, // XVRSQRTEDP 536895047U, // XVRSQRTESP 536894229U, // XVSQRTDP 536895350U, // XVSQRTSP 22718U, // XVSUBDP 24003U, // XVSUBSP 23356U, // XVTDIVDP 24457U, // XVTDIVSP 536894218U, // XVTSQRTDP 536895339U, // XVTSQRTSP 2281724114U, // XVTSTDCDP 2281725399U, // XVTSTDCSP 536894105U, // XVXEXPDP 536895248U, // XVXEXPSP 536893833U, // XVXSIGDP 536895068U, // XVXSIGSP 536890938U, // XXBRD 536891651U, // XXBRH 536895527U, // XXBRQ 536898244U, // XXBRW 27592U, // XXEXTRACTUW 2818599774U, // XXINSERTW 19973U, // XXLAND 19490U, // XXLANDC 26526U, // XXLEQV 19981U, // XXLNAND 24856U, // XXLNOR 24849U, // XXLOR 19598U, // XXLORC 24849U, // XXLORf 24890U, // XXLXOR 117465402U, // XXLXORdpz 117465402U, // XXLXORspz 117465402U, // XXLXORz 27011U, // XXMRGHW 27053U, // XXMRGLW 22172U, // XXPERM 21060U, // XXPERMDI 21060U, // XXPERMDIs 24840U, // XXPERMR 21802U, // XXSEL 21526U, // XXSLDWI 21526U, // XXSLDWIs 352340657U, // XXSPLTIB 27457U, // XXSPLTW 27457U, // XXSPLTWs 183320U, // gBC 182360U, // gBCA 10812308U, // gBCAat 188808U, // gBCCTR 185678U, // gBCCTRL 185594U, // gBCL 182654U, // gBCLA 10812324U, // gBCLAat 188633U, // gBCLR 185671U, // gBCLRL 11336717U, // gBCLat 11336625U, // gBCat }; static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // CFENCE8 0U, // CLRLSLDI 0U, // CLRLSLDIo 66U, // CLRLSLWI 66U, // CLRLSLWIo 32U, // CLRRDI 32U, // CLRRDIo 34U, // CLRRWI 34U, // CLRRWIo 0U, // CP_COPY_FIRST 0U, // CP_COPYx 0U, // CP_PASTE_LAST 0U, // CP_PASTEx 0U, // DCBFL 0U, // DCBFLP 0U, // DCBFx 0U, // DCBTCT 0U, // DCBTDS 0U, // DCBTSTCT 0U, // DCBTSTDS 0U, // DCBTSTT 0U, // DCBTSTx 0U, // DCBTT 0U, // DCBTx 0U, // DFLOADf32 0U, // DFLOADf64 0U, // DFSTOREf32 0U, // DFSTOREf64 0U, // EXTLDI 0U, // EXTLDIo 66U, // EXTLWI 66U, // EXTLWIo 0U, // EXTRDI 0U, // EXTRDIo 66U, // EXTRWI 66U, // EXTRWIo 66U, // INSLWI 66U, // INSLWIo 0U, // INSRDI 0U, // INSRDIo 66U, // INSRWI 66U, // INSRWIo 0U, // LAx 0U, // LIWAX 0U, // LIWZX 130U, // RLWIMIbm 130U, // RLWIMIobm 130U, // RLWINMbm 130U, // RLWINMobm 130U, // RLWNMbm 130U, // RLWNMobm 32U, // ROTRDI 32U, // ROTRDIo 34U, // ROTRWI 34U, // ROTRWIo 32U, // SLDI 32U, // SLDIo 34U, // SLWI 34U, // SLWIo 0U, // SPILLTOVSR_LD 0U, // SPILLTOVSR_LDX 0U, // SPILLTOVSR_ST 0U, // SPILLTOVSR_STX 32U, // SRDI 32U, // SRDIo 34U, // SRWI 34U, // SRWIo 0U, // STIWX 4U, // SUBI 4U, // SUBIC 4U, // SUBICo 4U, // SUBIS 0U, // SUBPCIS 0U, // XFLOADf32 0U, // XFLOADf64 0U, // XFSTOREf32 0U, // XFSTOREf64 38U, // ADD4 38U, // ADD4TLS 38U, // ADD4o 38U, // ADD8 38U, // ADD8TLS 38U, // ADD8TLS_ 38U, // ADD8o 38U, // ADDC 38U, // ADDC8 38U, // ADDC8o 38U, // ADDCo 38U, // ADDE 38U, // ADDE8 38U, // ADDE8o 38U, // ADDEo 4U, // ADDI 4U, // ADDI8 4U, // ADDIC 4U, // ADDIC8 4U, // ADDICo 4U, // ADDIS 4U, // ADDIS8 0U, // ADDISdtprelHA 0U, // ADDISdtprelHA32 0U, // ADDISgotTprelHA 0U, // ADDIStlsgdHA 0U, // ADDIStlsldHA 0U, // ADDIStocHA 0U, // ADDIdtprelL 0U, // ADDIdtprelL32 0U, // ADDItlsgdL 0U, // ADDItlsgdL32 0U, // ADDItlsgdLADDR 0U, // ADDItlsgdLADDR32 0U, // ADDItlsldL 0U, // ADDItlsldL32 0U, // ADDItlsldLADDR 0U, // ADDItlsldLADDR32 0U, // ADDItocL 0U, // ADDME 0U, // ADDME8 0U, // ADDME8o 0U, // ADDMEo 0U, // ADDPCIS 0U, // ADDZE 0U, // ADDZE8 0U, // ADDZE8o 0U, // ADDZEo 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 38U, // AND 38U, // AND8 38U, // AND8o 38U, // ANDC 38U, // ANDC8 38U, // ANDC8o 38U, // ANDCo 8U, // ANDISo 8U, // ANDISo8 8U, // ANDIo 8U, // ANDIo8 0U, // ANDIo_1_EQ_BIT 0U, // ANDIo_1_EQ_BIT8 0U, // ANDIo_1_GT_BIT 0U, // ANDIo_1_GT_BIT8 38U, // ANDo 0U, // ATOMIC_CMP_SWAP_I16 0U, // ATOMIC_CMP_SWAP_I32 0U, // ATOMIC_CMP_SWAP_I64 0U, // ATOMIC_CMP_SWAP_I8 0U, // ATOMIC_LOAD_ADD_I16 0U, // ATOMIC_LOAD_ADD_I32 0U, // ATOMIC_LOAD_ADD_I64 0U, // ATOMIC_LOAD_ADD_I8 0U, // ATOMIC_LOAD_AND_I16 0U, // ATOMIC_LOAD_AND_I32 0U, // ATOMIC_LOAD_AND_I64 0U, // ATOMIC_LOAD_AND_I8 0U, // ATOMIC_LOAD_MAX_I16 0U, // ATOMIC_LOAD_MAX_I32 0U, // ATOMIC_LOAD_MAX_I64 0U, // ATOMIC_LOAD_MAX_I8 0U, // ATOMIC_LOAD_MIN_I16 0U, // ATOMIC_LOAD_MIN_I32 0U, // ATOMIC_LOAD_MIN_I64 0U, // ATOMIC_LOAD_MIN_I8 0U, // ATOMIC_LOAD_NAND_I16 0U, // ATOMIC_LOAD_NAND_I32 0U, // ATOMIC_LOAD_NAND_I64 0U, // ATOMIC_LOAD_NAND_I8 0U, // ATOMIC_LOAD_OR_I16 0U, // ATOMIC_LOAD_OR_I32 0U, // ATOMIC_LOAD_OR_I64 0U, // ATOMIC_LOAD_OR_I8 0U, // ATOMIC_LOAD_SUB_I16 0U, // ATOMIC_LOAD_SUB_I32 0U, // ATOMIC_LOAD_SUB_I64 0U, // ATOMIC_LOAD_SUB_I8 0U, // ATOMIC_LOAD_UMAX_I16 0U, // ATOMIC_LOAD_UMAX_I32 0U, // ATOMIC_LOAD_UMAX_I64 0U, // ATOMIC_LOAD_UMAX_I8 0U, // ATOMIC_LOAD_UMIN_I16 0U, // ATOMIC_LOAD_UMIN_I32 0U, // ATOMIC_LOAD_UMIN_I64 0U, // ATOMIC_LOAD_UMIN_I8 0U, // ATOMIC_LOAD_XOR_I16 0U, // ATOMIC_LOAD_XOR_I32 0U, // ATOMIC_LOAD_XOR_I64 0U, // ATOMIC_LOAD_XOR_I8 0U, // ATOMIC_SWAP_I16 0U, // ATOMIC_SWAP_I32 0U, // ATOMIC_SWAP_I64 0U, // ATOMIC_SWAP_I8 0U, // ATTN 0U, // B 0U, // BA 0U, // BC 0U, // BCC 0U, // BCCA 0U, // BCCCTR 0U, // BCCCTR8 0U, // BCCCTRL 0U, // BCCCTRL8 0U, // BCCL 0U, // BCCLA 0U, // BCCLR 0U, // BCCLRL 0U, // BCCTR 0U, // BCCTR8 0U, // BCCTR8n 0U, // BCCTRL 0U, // BCCTRL8 0U, // BCCTRL8n 0U, // BCCTRLn 0U, // BCCTRn 42U, // BCDCFNo 42U, // BCDCFSQo 42U, // BCDCFZo 38U, // BCDCPSGNo 0U, // BCDCTNo 0U, // BCDCTSQo 42U, // BCDCTZo 42U, // BCDSETSGNo 198U, // BCDSRo 198U, // BCDSo 198U, // BCDTRUNCo 38U, // BCDUSo 38U, // BCDUTRUNCo 0U, // BCL 0U, // BCLR 0U, // BCLRL 0U, // BCLRLn 0U, // BCLRn 0U, // BCLalways 0U, // BCLn 0U, // BCTR 0U, // BCTR8 0U, // BCTRL 0U, // BCTRL8 0U, // BCTRL8_LDinto_toc 0U, // BCn 0U, // BDNZ 0U, // BDNZ8 0U, // BDNZA 0U, // BDNZAm 0U, // BDNZAp 0U, // BDNZL 0U, // BDNZLA 0U, // BDNZLAm 0U, // BDNZLAp 0U, // BDNZLR 0U, // BDNZLR8 0U, // BDNZLRL 0U, // BDNZLRLm 0U, // BDNZLRLp 0U, // BDNZLRm 0U, // BDNZLRp 0U, // BDNZLm 0U, // BDNZLp 0U, // BDNZm 0U, // BDNZp 0U, // BDZ 0U, // BDZ8 0U, // BDZA 0U, // BDZAm 0U, // BDZAp 0U, // BDZL 0U, // BDZLA 0U, // BDZLAm 0U, // BDZLAp 0U, // BDZLR 0U, // BDZLR8 0U, // BDZLRL 0U, // BDZLRLm 0U, // BDZLRLp 0U, // BDZLRm 0U, // BDZLRp 0U, // BDZLm 0U, // BDZLp 0U, // BDZm 0U, // BDZp 0U, // BL 0U, // BL8 0U, // BL8_NOP 0U, // BL8_NOP_TLS 0U, // BL8_TLS 0U, // BL8_TLS_ 0U, // BLA 0U, // BLA8 0U, // BLA8_NOP 0U, // BLR 0U, // BLR8 0U, // BLRL 0U, // BL_TLS 38U, // BPERMD 38U, // BRINC 0U, // CLRBHRB 38U, // CMPB 38U, // CMPB8 38U, // CMPD 4U, // CMPDI 38U, // CMPEQB 38U, // CMPLD 8U, // CMPLDI 38U, // CMPLW 8U, // CMPLWI 0U, // CMPRB 0U, // CMPRB8 38U, // CMPW 4U, // CMPWI 0U, // CNTLZD 0U, // CNTLZDo 0U, // CNTLZW 0U, // CNTLZW8 0U, // CNTLZW8o 0U, // CNTLZWo 0U, // CNTTZD 0U, // CNTTZDo 0U, // CNTTZW 0U, // CNTTZW8 0U, // CNTTZW8o 0U, // CNTTZWo 0U, // CP_ABORT 42U, // CP_COPY 42U, // CP_COPY8 42U, // CP_PASTE 42U, // CP_PASTE8 42U, // CP_PASTE8o 42U, // CP_PASTEo 0U, // CR6SET 0U, // CR6UNSET 38U, // CRAND 38U, // CRANDC 38U, // CREQV 38U, // CRNAND 38U, // CRNOR 38U, // CROR 38U, // CRORC 12U, // CRSET 12U, // CRUNSET 38U, // CRXOR 0U, // CTRL_DEP 0U, // DARN 0U, // DCBA 0U, // DCBF 0U, // DCBFEP 0U, // DCBI 0U, // DCBST 0U, // DCBSTEP 0U, // DCBT 0U, // DCBTEP 0U, // DCBTST 0U, // DCBTSTEP 0U, // DCBZ 0U, // DCBZEP 0U, // DCBZL 0U, // DCBZLEP 0U, // DCCCI 38U, // DIVD 38U, // DIVDE 38U, // DIVDEU 38U, // DIVDEUo 38U, // DIVDEo 38U, // DIVDU 38U, // DIVDUo 38U, // DIVDo 38U, // DIVW 38U, // DIVWE 38U, // DIVWEU 38U, // DIVWEUo 38U, // DIVWEo 38U, // DIVWU 38U, // DIVWUo 38U, // DIVWo 0U, // DSS 0U, // DSSALL 0U, // DST 0U, // DST64 0U, // DSTST 0U, // DSTST64 0U, // DSTSTT 0U, // DSTSTT64 0U, // DSTT 0U, // DSTT64 0U, // DYNALLOC 0U, // DYNALLOC8 0U, // DYNAREAOFFSET 0U, // DYNAREAOFFSET8 0U, // EFDABS 38U, // EFDADD 0U, // EFDCFS 0U, // EFDCFSF 0U, // EFDCFSI 0U, // EFDCFSID 0U, // EFDCFUF 0U, // EFDCFUI 0U, // EFDCFUID 38U, // EFDCMPEQ 38U, // EFDCMPGT 38U, // EFDCMPLT 0U, // EFDCTSF 0U, // EFDCTSI 0U, // EFDCTSIDZ 0U, // EFDCTSIZ 0U, // EFDCTUF 0U, // EFDCTUI 0U, // EFDCTUIDZ 0U, // EFDCTUIZ 38U, // EFDDIV 38U, // EFDMUL 0U, // EFDNABS 0U, // EFDNEG 38U, // EFDSUB 38U, // EFDTSTEQ 38U, // EFDTSTGT 38U, // EFDTSTLT 0U, // EFSABS 38U, // EFSADD 0U, // EFSCFD 0U, // EFSCFSF 0U, // EFSCFSI 0U, // EFSCFUF 0U, // EFSCFUI 38U, // EFSCMPEQ 38U, // EFSCMPGT 38U, // EFSCMPLT 0U, // EFSCTSF 0U, // EFSCTSI 0U, // EFSCTSIZ 0U, // EFSCTUF 0U, // EFSCTUI 0U, // EFSCTUIZ 38U, // EFSDIV 38U, // EFSMUL 0U, // EFSNABS 0U, // EFSNEG 38U, // EFSSUB 38U, // EFSTSTEQ 38U, // EFSTSTGT 38U, // EFSTSTLT 0U, // EH_SjLj_LongJmp32 0U, // EH_SjLj_LongJmp64 0U, // EH_SjLj_SetJmp32 0U, // EH_SjLj_SetJmp64 0U, // EH_SjLj_Setup 38U, // EQV 38U, // EQV8 38U, // EQV8o 38U, // EQVo 0U, // EVABS 46U, // EVADDIW 0U, // EVADDSMIAAW 0U, // EVADDSSIAAW 0U, // EVADDUMIAAW 0U, // EVADDUSIAAW 38U, // EVADDW 38U, // EVAND 38U, // EVANDC 38U, // EVCMPEQ 38U, // EVCMPGTS 38U, // EVCMPGTU 38U, // EVCMPLTS 38U, // EVCMPLTU 0U, // EVCNTLSW 0U, // EVCNTLZW 38U, // EVDIVWS 38U, // EVDIVWU 38U, // EVEQV 0U, // EVEXTSB 0U, // EVEXTSH 0U, // EVFSABS 38U, // EVFSADD 0U, // EVFSCFSF 0U, // EVFSCFSI 0U, // EVFSCFUF 0U, // EVFSCFUI 38U, // EVFSCMPEQ 38U, // EVFSCMPGT 38U, // EVFSCMPLT 0U, // EVFSCTSF 0U, // EVFSCTSI 0U, // EVFSCTSIZ 0U, // EVFSCTUF 0U, // EVFSCTUI 0U, // EVFSCTUIZ 38U, // EVFSDIV 38U, // EVFSMUL 0U, // EVFSNABS 0U, // EVFSNEG 38U, // EVFSSUB 38U, // EVFSTSTEQ 38U, // EVFSTSTGT 38U, // EVFSTSTLT 0U, // EVLDD 0U, // EVLDDX 0U, // EVLDH 0U, // EVLDHX 0U, // EVLDW 0U, // EVLDWX 0U, // EVLHHESPLAT 0U, // EVLHHESPLATX 0U, // EVLHHOSSPLAT 0U, // EVLHHOSSPLATX 0U, // EVLHHOUSPLAT 0U, // EVLHHOUSPLATX 0U, // EVLWHE 0U, // EVLWHEX 0U, // EVLWHOS 0U, // EVLWHOSX 0U, // EVLWHOU 0U, // EVLWHOUX 0U, // EVLWHSPLAT 0U, // EVLWHSPLATX 0U, // EVLWWSPLAT 0U, // EVLWWSPLATX 38U, // EVMERGEHI 38U, // EVMERGEHILO 38U, // EVMERGELO 38U, // EVMERGELOHI 38U, // EVMHEGSMFAA 38U, // EVMHEGSMFAN 38U, // EVMHEGSMIAA 38U, // EVMHEGSMIAN 38U, // EVMHEGUMIAA 38U, // EVMHEGUMIAN 38U, // EVMHESMF 38U, // EVMHESMFA 38U, // EVMHESMFAAW 38U, // EVMHESMFANW 38U, // EVMHESMI 38U, // EVMHESMIA 38U, // EVMHESMIAAW 38U, // EVMHESMIANW 38U, // EVMHESSF 38U, // EVMHESSFA 38U, // EVMHESSFAAW 38U, // EVMHESSFANW 38U, // EVMHESSIAAW 38U, // EVMHESSIANW 38U, // EVMHEUMI 38U, // EVMHEUMIA 38U, // EVMHEUMIAAW 38U, // EVMHEUMIANW 38U, // EVMHEUSIAAW 38U, // EVMHEUSIANW 38U, // EVMHOGSMFAA 38U, // EVMHOGSMFAN 38U, // EVMHOGSMIAA 38U, // EVMHOGSMIAN 38U, // EVMHOGUMIAA 38U, // EVMHOGUMIAN 38U, // EVMHOSMF 38U, // EVMHOSMFA 38U, // EVMHOSMFAAW 38U, // EVMHOSMFANW 38U, // EVMHOSMI 38U, // EVMHOSMIA 38U, // EVMHOSMIAAW 38U, // EVMHOSMIANW 38U, // EVMHOSSF 38U, // EVMHOSSFA 38U, // EVMHOSSFAAW 38U, // EVMHOSSFANW 38U, // EVMHOSSIAAW 38U, // EVMHOSSIANW 38U, // EVMHOUMI 38U, // EVMHOUMIA 38U, // EVMHOUMIAAW 38U, // EVMHOUMIANW 38U, // EVMHOUSIAAW 38U, // EVMHOUSIANW 0U, // EVMRA 38U, // EVMWHSMF 38U, // EVMWHSMFA 38U, // EVMWHSMI 38U, // EVMWHSMIA 38U, // EVMWHSSF 38U, // EVMWHSSFA 38U, // EVMWHUMI 38U, // EVMWHUMIA 38U, // EVMWLSMIAAW 38U, // EVMWLSMIANW 38U, // EVMWLSSIAAW 38U, // EVMWLSSIANW 38U, // EVMWLUMI 38U, // EVMWLUMIA 38U, // EVMWLUMIAAW 38U, // EVMWLUMIANW 38U, // EVMWLUSIAAW 38U, // EVMWLUSIANW 38U, // EVMWSMF 38U, // EVMWSMFA 38U, // EVMWSMFAA 38U, // EVMWSMFAN 38U, // EVMWSMI 38U, // EVMWSMIA 38U, // EVMWSMIAA 38U, // EVMWSMIAN 38U, // EVMWSSF 38U, // EVMWSSFA 38U, // EVMWSSFAA 38U, // EVMWSSFAN 38U, // EVMWUMI 38U, // EVMWUMIA 38U, // EVMWUMIAA 38U, // EVMWUMIAN 38U, // EVNAND 0U, // EVNEG 38U, // EVNOR 38U, // EVOR 38U, // EVORC 38U, // EVRLW 34U, // EVRLWI 0U, // EVRNDW 0U, // EVSEL 38U, // EVSLW 34U, // EVSLWI 0U, // EVSPLATFI 0U, // EVSPLATI 34U, // EVSRWIS 34U, // EVSRWIU 38U, // EVSRWS 38U, // EVSRWU 0U, // EVSTDD 0U, // EVSTDDX 0U, // EVSTDH 0U, // EVSTDHX 0U, // EVSTDW 0U, // EVSTDWX 0U, // EVSTWHE 0U, // EVSTWHEX 0U, // EVSTWHO 0U, // EVSTWHOX 0U, // EVSTWWE 0U, // EVSTWWEX 0U, // EVSTWWO 0U, // EVSTWWOX 0U, // EVSUBFSMIAAW 0U, // EVSUBFSSIAAW 0U, // EVSUBFUMIAAW 0U, // EVSUBFUSIAAW 38U, // EVSUBFW 0U, // EVSUBIFW 38U, // EVXOR 0U, // EXTSB 0U, // EXTSB8 0U, // EXTSB8_32_64 0U, // EXTSB8o 0U, // EXTSBo 0U, // EXTSH 0U, // EXTSH8 0U, // EXTSH8_32_64 0U, // EXTSH8o 0U, // EXTSHo 0U, // EXTSW 32U, // EXTSWSLI 32U, // EXTSWSLIo 0U, // EXTSW_32 0U, // EXTSW_32_64 0U, // EXTSW_32_64o 0U, // EXTSWo 0U, // EnforceIEIO 0U, // FABSD 0U, // FABSDo 0U, // FABSS 0U, // FABSSo 38U, // FADD 38U, // FADDS 38U, // FADDSo 38U, // FADDo 0U, // FADDrtz 0U, // FCFID 0U, // FCFIDS 0U, // FCFIDSo 0U, // FCFIDU 0U, // FCFIDUS 0U, // FCFIDUSo 0U, // FCFIDUo 0U, // FCFIDo 38U, // FCMPUD 38U, // FCMPUS 38U, // FCPSGND 38U, // FCPSGNDo 38U, // FCPSGNS 38U, // FCPSGNSo 0U, // FCTID 0U, // FCTIDU 0U, // FCTIDUZ 0U, // FCTIDUZo 0U, // FCTIDUo 0U, // FCTIDZ 0U, // FCTIDZo 0U, // FCTIDo 0U, // FCTIW 0U, // FCTIWU 0U, // FCTIWUZ 0U, // FCTIWUZo 0U, // FCTIWUo 0U, // FCTIWZ 0U, // FCTIWZo 0U, // FCTIWo 38U, // FDIV 38U, // FDIVS 38U, // FDIVSo 38U, // FDIVo 134U, // FMADD 134U, // FMADDS 134U, // FMADDSo 134U, // FMADDo 0U, // FMR 0U, // FMRo 134U, // FMSUB 134U, // FMSUBS 134U, // FMSUBSo 134U, // FMSUBo 38U, // FMUL 38U, // FMULS 38U, // FMULSo 38U, // FMULo 0U, // FNABSD 0U, // FNABSDo 0U, // FNABSS 0U, // FNABSSo 0U, // FNEGD 0U, // FNEGDo 0U, // FNEGS 0U, // FNEGSo 134U, // FNMADD 134U, // FNMADDS 134U, // FNMADDSo 134U, // FNMADDo 134U, // FNMSUB 134U, // FNMSUBS 134U, // FNMSUBSo 134U, // FNMSUBo 0U, // FRE 0U, // FRES 0U, // FRESo 0U, // FREo 0U, // FRIMD 0U, // FRIMDo 0U, // FRIMS 0U, // FRIMSo 0U, // FRIND 0U, // FRINDo 0U, // FRINS 0U, // FRINSo 0U, // FRIPD 0U, // FRIPDo 0U, // FRIPS 0U, // FRIPSo 0U, // FRIZD 0U, // FRIZDo 0U, // FRIZS 0U, // FRIZSo 0U, // FRSP 0U, // FRSPo 0U, // FRSQRTE 0U, // FRSQRTES 0U, // FRSQRTESo 0U, // FRSQRTEo 134U, // FSELD 134U, // FSELDo 134U, // FSELS 134U, // FSELSo 0U, // FSQRT 0U, // FSQRTS 0U, // FSQRTSo 0U, // FSQRTo 38U, // FSUB 38U, // FSUBS 38U, // FSUBSo 38U, // FSUBo 38U, // FTDIV 0U, // FTSQRT 0U, // GETtlsADDR 0U, // GETtlsADDR32 0U, // GETtlsldADDR 0U, // GETtlsldADDR32 0U, // HRFID 0U, // ICBI 0U, // ICBIEP 0U, // ICBLC 0U, // ICBLQ 0U, // ICBT 0U, // ICBTLS 0U, // ICCCI 134U, // ISEL 134U, // ISEL8 0U, // ISYNC 0U, // LA 0U, // LBARX 0U, // LBARXL 0U, // LBEPX 0U, // LBZ 0U, // LBZ8 38U, // LBZCIX 0U, // LBZU 0U, // LBZU8 0U, // LBZUX 0U, // LBZUX8 0U, // LBZX 0U, // LBZX8 38U, // LBZXTLS 38U, // LBZXTLS_ 38U, // LBZXTLS_32 0U, // LD 0U, // LDARX 0U, // LDARXL 34U, // LDAT 0U, // LDBRX 38U, // LDCIX 0U, // LDMX 0U, // LDU 0U, // LDUX 0U, // LDX 38U, // LDXTLS 38U, // LDXTLS_ 0U, // LDgotTprelL 0U, // LDgotTprelL32 0U, // LDtoc 0U, // LDtocBA 0U, // LDtocCPT 0U, // LDtocJTI 0U, // LDtocL 0U, // LFD 0U, // LFDEPX 0U, // LFDU 0U, // LFDUX 0U, // LFDX 0U, // LFIWAX 0U, // LFIWZX 0U, // LFS 0U, // LFSU 0U, // LFSUX 0U, // LFSX 0U, // LHA 0U, // LHA8 0U, // LHARX 0U, // LHARXL 0U, // LHAU 0U, // LHAU8 0U, // LHAUX 0U, // LHAUX8 0U, // LHAX 0U, // LHAX8 0U, // LHBRX 0U, // LHBRX8 0U, // LHEPX 0U, // LHZ 0U, // LHZ8 38U, // LHZCIX 0U, // LHZU 0U, // LHZU8 0U, // LHZUX 0U, // LHZUX8 0U, // LHZX 0U, // LHZX8 38U, // LHZXTLS 38U, // LHZXTLS_ 38U, // LHZXTLS_32 0U, // LI 0U, // LI8 0U, // LIS 0U, // LIS8 0U, // LMW 34U, // LSWI 0U, // LVEBX 0U, // LVEHX 0U, // LVEWX 0U, // LVSL 0U, // LVSR 0U, // LVX 0U, // LVXL 0U, // LWA 0U, // LWARX 0U, // LWARXL 34U, // LWAT 0U, // LWAUX 0U, // LWAX 0U, // LWAX_32 0U, // LWA_32 0U, // LWBRX 0U, // LWBRX8 0U, // LWEPX 0U, // LWZ 0U, // LWZ8 38U, // LWZCIX 0U, // LWZU 0U, // LWZU8 0U, // LWZUX 0U, // LWZUX8 0U, // LWZX 0U, // LWZX8 38U, // LWZXTLS 38U, // LWZXTLS_ 38U, // LWZXTLS_32 0U, // LWZtoc 0U, // LXSD 0U, // LXSDX 0U, // LXSIBZX 0U, // LXSIHZX 0U, // LXSIWAX 0U, // LXSIWZX 0U, // LXSSP 0U, // LXSSPX 0U, // LXV 0U, // LXVB16X 0U, // LXVD2X 0U, // LXVDSX 0U, // LXVH8X 38U, // LXVL 38U, // LXVLL 0U, // LXVW4X 0U, // LXVWSX 0U, // LXVX 134U, // MADDHD 134U, // MADDHDU 134U, // MADDLD 0U, // MBAR 0U, // MCRF 0U, // MCRFS 0U, // MCRXRX 0U, // MFBHRBE 0U, // MFCR 0U, // MFCR8 0U, // MFCTR 0U, // MFCTR8 0U, // MFDCR 0U, // MFFS 0U, // MFFSCDRN 0U, // MFFSCDRNI 0U, // MFFSCE 0U, // MFFSCRN 0U, // MFFSCRNI 0U, // MFFSL 0U, // MFFSo 0U, // MFLR 0U, // MFLR8 0U, // MFMSR 0U, // MFOCRF 0U, // MFOCRF8 0U, // MFPMR 0U, // MFSPR 0U, // MFSPR8 0U, // MFSR 0U, // MFSRIN 0U, // MFTB 0U, // MFTB8 0U, // MFVRD 0U, // MFVRSAVE 0U, // MFVRSAVEv 0U, // MFVSCR 0U, // MFVSRD 0U, // MFVSRLD 0U, // MFVSRWZ 38U, // MODSD 38U, // MODSW 38U, // MODUD 38U, // MODUW 0U, // MSGSYNC 0U, // MSYNC 0U, // MTCRF 0U, // MTCRF8 0U, // MTCTR 0U, // MTCTR8 0U, // MTCTR8loop 0U, // MTCTRloop 0U, // MTDCR 0U, // MTFSB0 0U, // MTFSB1 134U, // MTFSF 38U, // MTFSFI 38U, // MTFSFIo 0U, // MTFSFb 134U, // MTFSFo 0U, // MTLR 0U, // MTLR8 0U, // MTMSR 0U, // MTMSRD 0U, // MTOCRF 0U, // MTOCRF8 0U, // MTPMR 0U, // MTSPR 0U, // MTSPR8 0U, // MTSR 0U, // MTSRIN 0U, // MTVRSAVE 0U, // MTVRSAVEv 0U, // MTVSCR 0U, // MTVSRD 38U, // MTVSRDD 0U, // MTVSRWA 0U, // MTVSRWS 0U, // MTVSRWZ 38U, // MULHD 38U, // MULHDU 38U, // MULHDUo 38U, // MULHDo 38U, // MULHW 38U, // MULHWU 38U, // MULHWUo 38U, // MULHWo 38U, // MULLD 38U, // MULLDo 4U, // MULLI 4U, // MULLI8 38U, // MULLW 38U, // MULLWo 0U, // MoveGOTtoLR 0U, // MovePCtoLR 0U, // MovePCtoLR8 38U, // NAND 38U, // NAND8 38U, // NAND8o 38U, // NANDo 0U, // NAP 0U, // NEG 0U, // NEG8 0U, // NEG8o 0U, // NEGo 0U, // NOP 0U, // NOP_GT_PWR6 0U, // NOP_GT_PWR7 38U, // NOR 38U, // NOR8 38U, // NOR8o 38U, // NORo 38U, // OR 38U, // OR8 38U, // OR8o 38U, // ORC 38U, // ORC8 38U, // ORC8o 38U, // ORCo 8U, // ORI 8U, // ORI8 8U, // ORIS 8U, // ORIS8 38U, // ORo 0U, // POPCNTB 0U, // POPCNTD 0U, // POPCNTW 0U, // PPC32GOT 0U, // PPC32PICGOT 262U, // QVALIGNI 262U, // QVALIGNIb 262U, // QVALIGNIs 16U, // QVESPLATI 16U, // QVESPLATIb 16U, // QVESPLATIs 0U, // QVFABS 0U, // QVFABSs 38U, // QVFADD 38U, // QVFADDS 38U, // QVFADDSs 0U, // QVFCFID 0U, // QVFCFIDS 0U, // QVFCFIDU 0U, // QVFCFIDUS 0U, // QVFCFIDb 38U, // QVFCMPEQ 38U, // QVFCMPEQb 38U, // QVFCMPEQbs 38U, // QVFCMPGT 38U, // QVFCMPGTb 38U, // QVFCMPGTbs 38U, // QVFCMPLT 38U, // QVFCMPLTb 38U, // QVFCMPLTbs 38U, // QVFCPSGN 38U, // QVFCPSGNs 0U, // QVFCTID 0U, // QVFCTIDU 0U, // QVFCTIDUZ 0U, // QVFCTIDZ 0U, // QVFCTIDb 0U, // QVFCTIW 0U, // QVFCTIWU 0U, // QVFCTIWUZ 0U, // QVFCTIWZ 326U, // QVFLOGICAL 326U, // QVFLOGICALb 326U, // QVFLOGICALs 18U, // QVFMADD 18U, // QVFMADDS 18U, // QVFMADDSs 0U, // QVFMR 0U, // QVFMRb 0U, // QVFMRs 18U, // QVFMSUB 18U, // QVFMSUBS 18U, // QVFMSUBSs 38U, // QVFMUL 38U, // QVFMULS 38U, // QVFMULSs 0U, // QVFNABS 0U, // QVFNABSs 0U, // QVFNEG 0U, // QVFNEGs 18U, // QVFNMADD 18U, // QVFNMADDS 18U, // QVFNMADDSs 18U, // QVFNMSUB 18U, // QVFNMSUBS 18U, // QVFNMSUBSs 134U, // QVFPERM 134U, // QVFPERMs 0U, // QVFRE 0U, // QVFRES 0U, // QVFRESs 0U, // QVFRIM 0U, // QVFRIMs 0U, // QVFRIN 0U, // QVFRINs 0U, // QVFRIP 0U, // QVFRIPs 0U, // QVFRIZ 0U, // QVFRIZs 0U, // QVFRSP 0U, // QVFRSPs 0U, // QVFRSQRTE 0U, // QVFRSQRTES 0U, // QVFRSQRTESs 18U, // QVFSEL 18U, // QVFSELb 18U, // QVFSELbb 18U, // QVFSELbs 38U, // QVFSUB 38U, // QVFSUBS 38U, // QVFSUBSs 38U, // QVFTSTNAN 38U, // QVFTSTNANb 38U, // QVFTSTNANbs 18U, // QVFXMADD 18U, // QVFXMADDS 38U, // QVFXMUL 38U, // QVFXMULS 18U, // QVFXXCPNMADD 18U, // QVFXXCPNMADDS 18U, // QVFXXMADD 18U, // QVFXXMADDS 18U, // QVFXXNPMADD 18U, // QVFXXNPMADDS 0U, // QVGPCI 0U, // QVLFCDUX 0U, // QVLFCDUXA 0U, // QVLFCDX 0U, // QVLFCDXA 0U, // QVLFCSUX 0U, // QVLFCSUXA 0U, // QVLFCSX 0U, // QVLFCSXA 0U, // QVLFCSXs 0U, // QVLFDUX 0U, // QVLFDUXA 0U, // QVLFDX 0U, // QVLFDXA 0U, // QVLFDXb 0U, // QVLFIWAX 0U, // QVLFIWAXA 0U, // QVLFIWZX 0U, // QVLFIWZXA 0U, // QVLFSUX 0U, // QVLFSUXA 0U, // QVLFSX 0U, // QVLFSXA 0U, // QVLFSXb 0U, // QVLFSXs 0U, // QVLPCLDX 0U, // QVLPCLSX 0U, // QVLPCLSXint 0U, // QVLPCRDX 0U, // QVLPCRSX 0U, // QVSTFCDUX 0U, // QVSTFCDUXA 0U, // QVSTFCDUXI 0U, // QVSTFCDUXIA 0U, // QVSTFCDX 0U, // QVSTFCDXA 0U, // QVSTFCDXI 0U, // QVSTFCDXIA 0U, // QVSTFCSUX 0U, // QVSTFCSUXA 0U, // QVSTFCSUXI 0U, // QVSTFCSUXIA 0U, // QVSTFCSX 0U, // QVSTFCSXA 0U, // QVSTFCSXI 0U, // QVSTFCSXIA 0U, // QVSTFCSXs 0U, // QVSTFDUX 0U, // QVSTFDUXA 0U, // QVSTFDUXI 0U, // QVSTFDUXIA 0U, // QVSTFDX 0U, // QVSTFDXA 0U, // QVSTFDXI 0U, // QVSTFDXIA 0U, // QVSTFDXb 0U, // QVSTFIWX 0U, // QVSTFIWXA 0U, // QVSTFSUX 0U, // QVSTFSUXA 0U, // QVSTFSUXI 0U, // QVSTFSUXIA 0U, // QVSTFSUXs 0U, // QVSTFSX 0U, // QVSTFSXA 0U, // QVSTFSXI 0U, // QVSTFSXIA 0U, // QVSTFSXs 0U, // RESTORE_CR 0U, // RESTORE_CRBIT 0U, // RESTORE_VRSAVE 0U, // RFCI 0U, // RFDI 0U, // RFEBB 0U, // RFI 0U, // RFID 0U, // RFMCI 6U, // RLDCL 6U, // RLDCLo 6U, // RLDCR 6U, // RLDCRo 0U, // RLDIC 0U, // RLDICL 0U, // RLDICL_32 0U, // RLDICL_32_64 0U, // RLDICL_32o 0U, // RLDICLo 0U, // RLDICR 0U, // RLDICR_32 0U, // RLDICRo 0U, // RLDICo 0U, // RLDIMI 0U, // RLDIMIo 0U, // RLWIMI 0U, // RLWIMI8 0U, // RLWIMI8o 0U, // RLWIMIo 578U, // RLWINM 578U, // RLWINM8 578U, // RLWINM8o 578U, // RLWINMo 582U, // RLWNM 582U, // RLWNM8 582U, // RLWNM8o 582U, // RLWNMo 0U, // ReadTB 0U, // SC 0U, // SELECT_CC_F16 0U, // SELECT_CC_F4 0U, // SELECT_CC_F8 0U, // SELECT_CC_I4 0U, // SELECT_CC_I8 0U, // SELECT_CC_QBRC 0U, // SELECT_CC_QFRC 0U, // SELECT_CC_QSRC 0U, // SELECT_CC_SPE 0U, // SELECT_CC_SPE4 0U, // SELECT_CC_VRRC 0U, // SELECT_CC_VSFRC 0U, // SELECT_CC_VSRC 0U, // SELECT_CC_VSSRC 0U, // SELECT_F16 0U, // SELECT_F4 0U, // SELECT_F8 0U, // SELECT_I4 0U, // SELECT_I8 0U, // SELECT_QBRC 0U, // SELECT_QFRC 0U, // SELECT_QSRC 0U, // SELECT_SPE 0U, // SELECT_SPE4 0U, // SELECT_VRRC 0U, // SELECT_VSFRC 0U, // SELECT_VSRC 0U, // SELECT_VSSRC 0U, // SETB 0U, // SLBIA 0U, // SLBIE 0U, // SLBIEG 0U, // SLBMFEE 0U, // SLBMFEV 0U, // SLBMTE 0U, // SLBSYNC 38U, // SLD 38U, // SLDo 38U, // SLW 38U, // SLW8 38U, // SLW8o 38U, // SLWo 0U, // SPELWZ 0U, // SPELWZX 0U, // SPESTW 0U, // SPESTWX 0U, // SPILL_CR 0U, // SPILL_CRBIT 0U, // SPILL_VRSAVE 38U, // SRAD 32U, // SRADI 32U, // SRADI_32 32U, // SRADIo 38U, // SRADo 38U, // SRAW 34U, // SRAWI 34U, // SRAWIo 38U, // SRAWo 38U, // SRD 38U, // SRDo 38U, // SRW 38U, // SRW8 38U, // SRW8o 38U, // SRWo 0U, // STB 0U, // STB8 38U, // STBCIX 0U, // STBCX 0U, // STBEPX 0U, // STBU 0U, // STBU8 0U, // STBUX 0U, // STBUX8 0U, // STBX 0U, // STBX8 38U, // STBXTLS 38U, // STBXTLS_ 38U, // STBXTLS_32 0U, // STD 34U, // STDAT 0U, // STDBRX 38U, // STDCIX 0U, // STDCX 0U, // STDU 0U, // STDUX 0U, // STDX 38U, // STDXTLS 38U, // STDXTLS_ 0U, // STFD 0U, // STFDEPX 0U, // STFDU 0U, // STFDUX 0U, // STFDX 0U, // STFIWX 0U, // STFS 0U, // STFSU 0U, // STFSUX 0U, // STFSX 0U, // STH 0U, // STH8 0U, // STHBRX 38U, // STHCIX 0U, // STHCX 0U, // STHEPX 0U, // STHU 0U, // STHU8 0U, // STHUX 0U, // STHUX8 0U, // STHX 0U, // STHX8 38U, // STHXTLS 38U, // STHXTLS_ 38U, // STHXTLS_32 0U, // STMW 0U, // STOP 34U, // STSWI 0U, // STVEBX 0U, // STVEHX 0U, // STVEWX 0U, // STVX 0U, // STVXL 0U, // STW 0U, // STW8 34U, // STWAT 0U, // STWBRX 38U, // STWCIX 0U, // STWCX 0U, // STWEPX 0U, // STWU 0U, // STWU8 0U, // STWUX 0U, // STWUX8 0U, // STWX 0U, // STWX8 38U, // STWXTLS 38U, // STWXTLS_ 38U, // STWXTLS_32 0U, // STXSD 0U, // STXSDX 0U, // STXSIBX 0U, // STXSIBXv 0U, // STXSIHX 0U, // STXSIHXv 0U, // STXSIWX 0U, // STXSSP 0U, // STXSSPX 0U, // STXV 0U, // STXVB16X 0U, // STXVD2X 0U, // STXVH8X 38U, // STXVL 38U, // STXVLL 0U, // STXVW4X 0U, // STXVX 38U, // SUBF 38U, // SUBF8 38U, // SUBF8o 38U, // SUBFC 38U, // SUBFC8 38U, // SUBFC8o 38U, // SUBFCo 38U, // SUBFE 38U, // SUBFE8 38U, // SUBFE8o 38U, // SUBFEo 4U, // SUBFIC 4U, // SUBFIC8 0U, // SUBFME 0U, // SUBFME8 0U, // SUBFME8o 0U, // SUBFMEo 0U, // SUBFZE 0U, // SUBFZE8 0U, // SUBFZE8o 0U, // SUBFZEo 38U, // SUBFo 0U, // SYNC 0U, // TABORT 0U, // TABORTDC 0U, // TABORTDCI 0U, // TABORTWC 0U, // TABORTWCI 0U, // TAILB 0U, // TAILB8 0U, // TAILBA 0U, // TAILBA8 0U, // TAILBCTR 0U, // TAILBCTR8 0U, // TBEGIN 0U, // TCHECK 0U, // TCHECK_RET 0U, // TCRETURNai 0U, // TCRETURNai8 0U, // TCRETURNdi 0U, // TCRETURNdi8 0U, // TCRETURNri 0U, // TCRETURNri8 38U, // TD 4U, // TDI 0U, // TEND 0U, // TLBIA 0U, // TLBIE 0U, // TLBIEL 0U, // TLBIVAX 0U, // TLBLD 0U, // TLBLI 0U, // TLBRE 38U, // TLBRE2 0U, // TLBSX 38U, // TLBSX2 38U, // TLBSX2D 0U, // TLBSYNC 0U, // TLBWE 38U, // TLBWE2 0U, // TRAP 0U, // TRECHKPT 0U, // TRECLAIM 0U, // TSR 38U, // TW 4U, // TWI 0U, // UPDATE_VRSAVE 0U, // UpdateGBR 38U, // VABSDUB 38U, // VABSDUH 38U, // VABSDUW 38U, // VADDCUQ 38U, // VADDCUW 134U, // VADDECUQ 134U, // VADDEUQM 38U, // VADDFP 38U, // VADDSBS 38U, // VADDSHS 38U, // VADDSWS 38U, // VADDUBM 38U, // VADDUBS 38U, // VADDUDM 38U, // VADDUHM 38U, // VADDUHS 38U, // VADDUQM 38U, // VADDUWM 38U, // VADDUWS 38U, // VAND 38U, // VANDC 38U, // VAVGSB 38U, // VAVGSH 38U, // VAVGSW 38U, // VAVGUB 38U, // VAVGUH 38U, // VAVGUW 38U, // VBPERMD 38U, // VBPERMQ 1U, // VCFSX 1U, // VCFSX_0 1U, // VCFUX 1U, // VCFUX_0 38U, // VCIPHER 38U, // VCIPHERLAST 0U, // VCLZB 0U, // VCLZD 0U, // VCLZH 0U, // VCLZLSBB 0U, // VCLZW 38U, // VCMPBFP 38U, // VCMPBFPo 38U, // VCMPEQFP 38U, // VCMPEQFPo 38U, // VCMPEQUB 38U, // VCMPEQUBo 38U, // VCMPEQUD 38U, // VCMPEQUDo 38U, // VCMPEQUH 38U, // VCMPEQUHo 38U, // VCMPEQUW 38U, // VCMPEQUWo 38U, // VCMPGEFP 38U, // VCMPGEFPo 38U, // VCMPGTFP 38U, // VCMPGTFPo 38U, // VCMPGTSB 38U, // VCMPGTSBo 38U, // VCMPGTSD 38U, // VCMPGTSDo 38U, // VCMPGTSH 38U, // VCMPGTSHo 38U, // VCMPGTSW 38U, // VCMPGTSWo 38U, // VCMPGTUB 38U, // VCMPGTUBo 38U, // VCMPGTUD 38U, // VCMPGTUDo 38U, // VCMPGTUH 38U, // VCMPGTUHo 38U, // VCMPGTUW 38U, // VCMPGTUWo 38U, // VCMPNEB 38U, // VCMPNEBo 38U, // VCMPNEH 38U, // VCMPNEHo 38U, // VCMPNEW 38U, // VCMPNEWo 38U, // VCMPNEZB 38U, // VCMPNEZBo 38U, // VCMPNEZH 38U, // VCMPNEZHo 38U, // VCMPNEZW 38U, // VCMPNEZWo 1U, // VCTSXS 1U, // VCTSXS_0 1U, // VCTUXS 1U, // VCTUXS_0 0U, // VCTZB 0U, // VCTZD 0U, // VCTZH 0U, // VCTZLSBB 0U, // VCTZW 38U, // VEQV 0U, // VEXPTEFP 1U, // VEXTRACTD 1U, // VEXTRACTUB 1U, // VEXTRACTUH 1U, // VEXTRACTUW 0U, // VEXTSB2D 0U, // VEXTSB2Ds 0U, // VEXTSB2W 0U, // VEXTSB2Ws 0U, // VEXTSH2D 0U, // VEXTSH2Ds 0U, // VEXTSH2W 0U, // VEXTSH2Ws 0U, // VEXTSW2D 0U, // VEXTSW2Ds 38U, // VEXTUBLX 38U, // VEXTUBRX 38U, // VEXTUHLX 38U, // VEXTUHRX 38U, // VEXTUWLX 38U, // VEXTUWRX 0U, // VGBBD 0U, // VINSERTB 1U, // VINSERTD 0U, // VINSERTH 1U, // VINSERTW 0U, // VLOGEFP 134U, // VMADDFP 38U, // VMAXFP 38U, // VMAXSB 38U, // VMAXSD 38U, // VMAXSH 38U, // VMAXSW 38U, // VMAXUB 38U, // VMAXUD 38U, // VMAXUH 38U, // VMAXUW 134U, // VMHADDSHS 134U, // VMHRADDSHS 38U, // VMINFP 38U, // VMINSB 38U, // VMINSD 38U, // VMINSH 38U, // VMINSW 38U, // VMINUB 38U, // VMINUD 38U, // VMINUH 38U, // VMINUW 134U, // VMLADDUHM 38U, // VMRGEW 38U, // VMRGHB 38U, // VMRGHH 38U, // VMRGHW 38U, // VMRGLB 38U, // VMRGLH 38U, // VMRGLW 38U, // VMRGOW 134U, // VMSUMMBM 134U, // VMSUMSHM 134U, // VMSUMSHS 134U, // VMSUMUBM 134U, // VMSUMUHM 134U, // VMSUMUHS 0U, // VMUL10CUQ 38U, // VMUL10ECUQ 38U, // VMUL10EUQ 0U, // VMUL10UQ 38U, // VMULESB 38U, // VMULESH 38U, // VMULESW 38U, // VMULEUB 38U, // VMULEUH 38U, // VMULEUW 38U, // VMULOSB 38U, // VMULOSH 38U, // VMULOSW 38U, // VMULOUB 38U, // VMULOUH 38U, // VMULOUW 38U, // VMULUWM 38U, // VNAND 38U, // VNCIPHER 38U, // VNCIPHERLAST 0U, // VNEGD 0U, // VNEGW 134U, // VNMSUBFP 38U, // VNOR 38U, // VOR 38U, // VORC 134U, // VPERM 134U, // VPERMR 134U, // VPERMXOR 38U, // VPKPX 38U, // VPKSDSS 38U, // VPKSDUS 38U, // VPKSHSS 38U, // VPKSHUS 38U, // VPKSWSS 38U, // VPKSWUS 38U, // VPKUDUM 38U, // VPKUDUS 38U, // VPKUHUM 38U, // VPKUHUS 38U, // VPKUWUM 38U, // VPKUWUS 38U, // VPMSUMB 38U, // VPMSUMD 38U, // VPMSUMH 38U, // VPMSUMW 0U, // VPOPCNTB 0U, // VPOPCNTD 0U, // VPOPCNTH 0U, // VPOPCNTW 0U, // VPRTYBD 0U, // VPRTYBQ 0U, // VPRTYBW 0U, // VREFP 0U, // VRFIM 0U, // VRFIN 0U, // VRFIP 0U, // VRFIZ 38U, // VRLB 38U, // VRLD 38U, // VRLDMI 38U, // VRLDNM 38U, // VRLH 38U, // VRLW 38U, // VRLWMI 38U, // VRLWNM 0U, // VRSQRTEFP 0U, // VSBOX 134U, // VSEL 394U, // VSHASIGMAD 394U, // VSHASIGMAW 38U, // VSL 38U, // VSLB 38U, // VSLD 390U, // VSLDOI 38U, // VSLH 38U, // VSLO 38U, // VSLV 38U, // VSLW 1U, // VSPLTB 1U, // VSPLTBs 1U, // VSPLTH 1U, // VSPLTHs 0U, // VSPLTISB 0U, // VSPLTISH 0U, // VSPLTISW 1U, // VSPLTW 38U, // VSR 38U, // VSRAB 38U, // VSRAD 38U, // VSRAH 38U, // VSRAW 38U, // VSRB 38U, // VSRD 38U, // VSRH 38U, // VSRO 38U, // VSRV 38U, // VSRW 38U, // VSUBCUQ 38U, // VSUBCUW 134U, // VSUBECUQ 134U, // VSUBEUQM 38U, // VSUBFP 38U, // VSUBSBS 38U, // VSUBSHS 38U, // VSUBSWS 38U, // VSUBUBM 38U, // VSUBUBS 38U, // VSUBUDM 38U, // VSUBUHM 38U, // VSUBUHS 38U, // VSUBUQM 38U, // VSUBUWM 38U, // VSUBUWS 38U, // VSUM2SWS 38U, // VSUM4SBS 38U, // VSUM4SHS 38U, // VSUM4UBS 38U, // VSUMSWS 0U, // VUPKHPX 0U, // VUPKHSB 0U, // VUPKHSH 0U, // VUPKHSW 0U, // VUPKLPX 0U, // VUPKLSB 0U, // VUPKLSH 0U, // VUPKLSW 38U, // VXOR 12U, // V_SET0 12U, // V_SET0B 12U, // V_SET0H 0U, // V_SETALLONES 0U, // V_SETALLONESB 0U, // V_SETALLONESH 0U, // WAIT 0U, // WRTEE 0U, // WRTEEI 38U, // XOR 38U, // XOR8 38U, // XOR8o 8U, // XORI 8U, // XORI8 8U, // XORIS 8U, // XORIS8 38U, // XORo 0U, // XSABSDP 0U, // XSABSQP 38U, // XSADDDP 38U, // XSADDQP 38U, // XSADDQPO 38U, // XSADDSP 38U, // XSCMPEQDP 38U, // XSCMPEXPDP 38U, // XSCMPEXPQP 38U, // XSCMPGEDP 38U, // XSCMPGTDP 38U, // XSCMPODP 38U, // XSCMPOQP 38U, // XSCMPUDP 38U, // XSCMPUQP 38U, // XSCPSGNDP 38U, // XSCPSGNQP 0U, // XSCVDPHP 0U, // XSCVDPQP 0U, // XSCVDPSP 0U, // XSCVDPSPN 0U, // XSCVDPSXDS 0U, // XSCVDPSXDSs 0U, // XSCVDPSXWS 0U, // XSCVDPSXWSs 0U, // XSCVDPUXDS 0U, // XSCVDPUXDSs 0U, // XSCVDPUXWS 0U, // XSCVDPUXWSs 0U, // XSCVHPDP 0U, // XSCVQPDP 0U, // XSCVQPDPO 0U, // XSCVQPSDZ 0U, // XSCVQPSWZ 0U, // XSCVQPUDZ 0U, // XSCVQPUWZ 0U, // XSCVSDQP 0U, // XSCVSPDP 0U, // XSCVSPDPN 0U, // XSCVSXDDP 0U, // XSCVSXDSP 0U, // XSCVUDQP 0U, // XSCVUXDDP 0U, // XSCVUXDSP 38U, // XSDIVDP 38U, // XSDIVQP 38U, // XSDIVQPO 38U, // XSDIVSP 38U, // XSIEXPDP 38U, // XSIEXPQP 1U, // XSMADDADP 1U, // XSMADDASP 1U, // XSMADDMDP 1U, // XSMADDMSP 1U, // XSMADDQP 1U, // XSMADDQPO 38U, // XSMAXCDP 38U, // XSMAXDP 38U, // XSMAXJDP 38U, // XSMINCDP 38U, // XSMINDP 38U, // XSMINJDP 1U, // XSMSUBADP 1U, // XSMSUBASP 1U, // XSMSUBMDP 1U, // XSMSUBMSP 1U, // XSMSUBQP 1U, // XSMSUBQPO 38U, // XSMULDP 38U, // XSMULQP 38U, // XSMULQPO 38U, // XSMULSP 0U, // XSNABSDP 0U, // XSNABSQP 0U, // XSNEGDP 0U, // XSNEGQP 1U, // XSNMADDADP 1U, // XSNMADDASP 1U, // XSNMADDMDP 1U, // XSNMADDMSP 1U, // XSNMADDQP 1U, // XSNMADDQPO 1U, // XSNMSUBADP 1U, // XSNMSUBASP 1U, // XSNMSUBMDP 1U, // XSNMSUBMSP 1U, // XSNMSUBQP 1U, // XSNMSUBQPO 0U, // XSRDPI 0U, // XSRDPIC 0U, // XSRDPIM 0U, // XSRDPIP 0U, // XSRDPIZ 0U, // XSREDP 0U, // XSRESP 262U, // XSRQPI 262U, // XSRQPIX 262U, // XSRQPXP 0U, // XSRSP 0U, // XSRSQRTEDP 0U, // XSRSQRTESP 0U, // XSSQRTDP 0U, // XSSQRTQP 0U, // XSSQRTQPO 0U, // XSSQRTSP 38U, // XSSUBDP 38U, // XSSUBQP 38U, // XSSUBQPO 38U, // XSSUBSP 38U, // XSTDIVDP 0U, // XSTSQRTDP 1U, // XSTSTDCDP 1U, // XSTSTDCQP 1U, // XSTSTDCSP 0U, // XSXEXPDP 0U, // XSXEXPQP 0U, // XSXSIGDP 0U, // XSXSIGQP 0U, // XVABSDP 0U, // XVABSSP 38U, // XVADDDP 38U, // XVADDSP 38U, // XVCMPEQDP 38U, // XVCMPEQDPo 38U, // XVCMPEQSP 38U, // XVCMPEQSPo 38U, // XVCMPGEDP 38U, // XVCMPGEDPo 38U, // XVCMPGESP 38U, // XVCMPGESPo 38U, // XVCMPGTDP 38U, // XVCMPGTDPo 38U, // XVCMPGTSP 38U, // XVCMPGTSPo 38U, // XVCPSGNDP 38U, // XVCPSGNSP 0U, // XVCVDPSP 0U, // XVCVDPSXDS 0U, // XVCVDPSXWS 0U, // XVCVDPUXDS 0U, // XVCVDPUXWS 0U, // XVCVHPSP 0U, // XVCVSPDP 0U, // XVCVSPHP 0U, // XVCVSPSXDS 0U, // XVCVSPSXWS 0U, // XVCVSPUXDS 0U, // XVCVSPUXWS 0U, // XVCVSXDDP 0U, // XVCVSXDSP 0U, // XVCVSXWDP 0U, // XVCVSXWSP 0U, // XVCVUXDDP 0U, // XVCVUXDSP 0U, // XVCVUXWDP 0U, // XVCVUXWSP 38U, // XVDIVDP 38U, // XVDIVSP 38U, // XVIEXPDP 38U, // XVIEXPSP 1U, // XVMADDADP 1U, // XVMADDASP 1U, // XVMADDMDP 1U, // XVMADDMSP 38U, // XVMAXDP 38U, // XVMAXSP 38U, // XVMINDP 38U, // XVMINSP 1U, // XVMSUBADP 1U, // XVMSUBASP 1U, // XVMSUBMDP 1U, // XVMSUBMSP 38U, // XVMULDP 38U, // XVMULSP 0U, // XVNABSDP 0U, // XVNABSSP 0U, // XVNEGDP 0U, // XVNEGSP 1U, // XVNMADDADP 1U, // XVNMADDASP 1U, // XVNMADDMDP 1U, // XVNMADDMSP 1U, // XVNMSUBADP 1U, // XVNMSUBASP 1U, // XVNMSUBMDP 1U, // XVNMSUBMSP 0U, // XVRDPI 0U, // XVRDPIC 0U, // XVRDPIM 0U, // XVRDPIP 0U, // XVRDPIZ 0U, // XVREDP 0U, // XVRESP 0U, // XVRSPI 0U, // XVRSPIC 0U, // XVRSPIM 0U, // XVRSPIP 0U, // XVRSPIZ 0U, // XVRSQRTEDP 0U, // XVRSQRTESP 0U, // XVSQRTDP 0U, // XVSQRTSP 38U, // XVSUBDP 38U, // XVSUBSP 38U, // XVTDIVDP 38U, // XVTDIVSP 0U, // XVTSQRTDP 0U, // XVTSQRTSP 1U, // XVTSTDCDP 1U, // XVTSTDCSP 0U, // XVXEXPDP 0U, // XVXEXPSP 0U, // XVXSIGDP 0U, // XVXSIGSP 0U, // XXBRD 0U, // XXBRH 0U, // XXBRQ 0U, // XXBRW 20U, // XXEXTRACTUW 1U, // XXINSERTW 38U, // XXLAND 38U, // XXLANDC 38U, // XXLEQV 38U, // XXLNAND 38U, // XXLNOR 38U, // XXLOR 38U, // XXLORC 38U, // XXLORf 38U, // XXLXOR 12U, // XXLXORdpz 12U, // XXLXORspz 12U, // XXLXORz 38U, // XXMRGHW 38U, // XXMRGLW 38U, // XXPERM 262U, // XXPERMDI 462U, // XXPERMDIs 38U, // XXPERMR 134U, // XXSEL 262U, // XXSLDWI 462U, // XXSLDWIs 0U, // XXSPLTIB 16U, // XXSPLTW 16U, // XXSPLTWs 22U, // gBC 24U, // gBCA 0U, // gBCAat 38U, // gBCCTR 38U, // gBCCTRL 22U, // gBCL 24U, // gBCLA 0U, // gBCLAat 38U, // gBCLR 38U, // gBCLRL 0U, // gBCLat 0U, // gBCat }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint64_t Bits = 0; Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 16383)-1); #endif // Fragment 0 encoded into 5 bits for 20 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 31)); switch ((Bits >> 14) & 31) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR... printOperand(MI, 0, O); break; case 2: // DCBFL, DCBFLP, DCBFx, DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, DCBTSTT, DCB... printMemRegReg(MI, 0, O); break; case 3: // ADJCALLSTACKDOWN, ADJCALLSTACKUP printU16ImmOperand(MI, 0, O); SStream_concat0(O, " "); printU16ImmOperand(MI, 1, O); return; break; case 4: // B, BCLalways, BDNZ, BDNZ8, BDNZL, BDNZLm, BDNZLp, BDNZm, BDNZp, BDZ, B... printBranchOperand(MI, 0, O); break; case 5: // BA, BDNZA, BDNZAm, BDNZAp, BDNZLA, BDNZLAm, BDNZLAp, BDZA, BDZAm, BDZA... printAbsBranchOperand(MI, 0, O); break; case 6: // BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCC... printPredicateOperand(MI, 0, O, "cc"); break; case 7: // BCTRL8_LDinto_toc printMemRegImm(MI, 0, O); return; break; case 8: // BL8_NOP_TLS, BL8_TLS, BL8_TLS_, BL_TLS printTLSCall(MI, 0, O); break; case 9: // DCBF, DCBT, DCBTST printMemRegReg(MI, 1, O); SStream_concat0(O, ", "); printU5ImmOperand(MI, 0, O); return; break; case 10: // DCBTEP, DCBTSTEP printU5ImmOperand(MI, 2, O); SStream_concat0(O, ", "); printMemRegReg(MI, 0, O); return; break; case 11: // DSS, MBAR, MTFSB0, MTFSB1, TD, TDI, TW, TWI, gBC, gBCA, gBCCTR, gBCCTR... printU5ImmOperand(MI, 0, O); break; case 12: // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, MTDCR, MTV... printOperand(MI, 1, O); break; case 13: // ICBLC, ICBLQ, ICBT, ICBTLS printU4ImmOperand(MI, 0, O); SStream_concat0(O, ", "); printMemRegReg(MI, 1, O); return; break; case 14: // MTOCRF, MTOCRF8 printcrbitm(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 15: // MTSR printU4ImmOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 16: // RFEBB, TBEGIN printU1ImmOperand(MI, 0, O); return; break; case 17: // TABORTDC, TABORTDCI, TABORTWC, TABORTWCI printU5ImmOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 18: // TEND, TSR, XSRQPI, XSRQPIX, XSRQPXP printU1ImmOperand(MI, 1, O); break; case 19: // gBCAat, gBCLAat, gBCLat, gBCat printATBitsAsHint(MI, 1, O); SStream_concat0(O, " "); printU5ImmOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); break; } // Fragment 1 encoded into 5 bits for 22 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 31)); switch ((Bits >> 19) & 31) { default: // unreachable case 0: // CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR... SStream_concat0(O, ", "); break; case 1: // DCBFL, DCBFLP, DCBFx, DCBTSTT, DCBTSTx, DCBTT, DCBTx, B, BA, BCLalways... return; break; case 2: // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, TCRETURNai8, TCR... SStream_concat0(O, " "); break; case 3: // BCC, CTRL_DEP printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); SStream_concat0(O, ", "); printBranchOperand(MI, 2, O); return; break; case 4: // BCCA SStream_concat0(O, "a"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); SStream_concat0(O, ", "); printAbsBranchOperand(MI, 2, O); return; break; case 5: // BCCCTR, BCCCTR8 SStream_concat0(O, "ctr"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); return; break; case 6: // BCCCTRL, BCCCTRL8 SStream_concat0(O, "ctrl"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); return; break; case 7: // BCCL SStream_concat0(O, "l"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); SStream_concat0(O, ", "); printBranchOperand(MI, 2, O); return; break; case 8: // BCCLA SStream_concat0(O, "la"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); SStream_concat0(O, ", "); printAbsBranchOperand(MI, 2, O); return; break; case 9: // BCCLR SStream_concat0(O, "lr"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); return; break; case 10: // BCCLRL SStream_concat0(O, "lrl"); printPredicateOperand(MI, 0, O, "pm"); SStream_concat0(O, " "); printPredicateOperand(MI, 0, O, "reg"); return; break; case 11: // BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, BC... SStream_concat0(O, ", 0"); op_addImm(MI, 0); return; break; case 12: // BL8_NOP, BL8_NOP_TLS, BLA8_NOP SStream_concat0(O, "\n\tnop"); return; break; case 13: // EVSEL, TLBIE SStream_concat0(O, ","); break; case 14: // MFTB8 SStream_concat0(O, ", 268"); op_addImm(MI, 268); return; break; case 15: // MFVRSAVE, MFVRSAVEv SStream_concat0(O, ", 256"); op_addImm(MI, 256); return; break; case 16: // QVLPCLSXint SStream_concat0(O, ", 0, "); op_addImm(MI, 0); printOperand(MI, 1, O); return; break; case 17: // TABORTDC, TABORTWC printOperand(MI, 3, O); return; break; case 18: // TABORTDCI, TABORTWCI printU5ImmOperand(MI, 3, O); return; break; case 19: // V_SETALLONES, V_SETALLONESB, V_SETALLONESH SStream_concat0(O, ", -1"); op_addImm(MI, -1); return; break; case 20: // gBCAat, gBCLAat printAbsBranchOperand(MI, 3, O); return; break; case 21: // gBCLat, gBCat printBranchOperand(MI, 3, O); return; break; } // Fragment 2 encoded into 5 bits for 22 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 31)); switch ((Bits >> 24) & 31) { default: // unreachable case 0: // CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR... printOperand(MI, 1, O); break; case 1: // DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, EVADDIW printU5ImmOperand(MI, 2, O); break; case 2: // LAx, EVLDD, EVLDH, EVLDW, EVLHHESPLAT, EVLHHOSSPLAT, EVLHHOUSPLAT, EVL... printMemRegImm(MI, 1, O); return; break; case 3: // SUBPCIS, LI, LI8, LIS, LIS8 printS16ImmOperand(MI, 1, O); return; break; case 4: // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, EVLDDX, EVLDHX, EVLDWX, EVLH... printMemRegReg(MI, 1, O); break; case 5: // BC, BCL, BCLn, BCn printBranchOperand(MI, 1, O); return; break; case 6: // CMPRB, CMPRB8 printU1ImmOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 7: // CRSET, CRUNSET, MTDCR, TLBIE, V_SET0, V_SET0B, V_SET0H, XSRQPI, XSRQPI... printOperand(MI, 0, O); break; case 8: // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, RLDIMI, RL... printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 9: // EVSPLATFI, EVSPLATI, VSPLTISB, VSPLTISH, VSPLTISW printS5ImmOperand(MI, 1, O); return; break; case 10: // EVSUBIFW printU5ImmOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 11: // LA printS16ImmOperand(MI, 2, O); SStream_concat0(O, "("); printOperand(MI, 1, O); SStream_concat0(O, ")"); return; break; case 12: // LBZU, LBZU8, LDU, LFDU, LFSU, LHAU, LHAU8, LHZU, LHZU8, LWZU, LWZU8, S... printMemRegImm(MI, 2, O); return; break; case 13: // LBZUX, LBZUX8, LDUX, LFDUX, LFSUX, LHAUX, LHAUX8, LHZUX, LHZUX8, LWAUX... printMemRegReg(MI, 2, O); return; break; case 14: // MFBHRBE printU10ImmOperand(MI, 1, O); return; break; case 15: // MFFSCDRNI printU3ImmOperand(MI, 1, O); return; break; case 16: // MFFSCRNI printU2ImmOperand(MI, 1, O); return; break; case 17: // MFOCRF, MFOCRF8 printcrbitm(MI, 1, O); return; break; case 18: // MFSR printU4ImmOperand(MI, 1, O); return; break; case 19: // QVGPCI printU12ImmOperand(MI, 1, O); return; break; case 20: // VINSERTB, VINSERTH printOperand(MI, 3, O); SStream_concat0(O, ", "); printU4ImmOperand(MI, 2, O); return; break; case 21: // XXSPLTIB printU8ImmOperand(MI, 1, O); return; break; } // Fragment 3 encoded into 4 bits for 14 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 29) & 15)); switch ((Bits >> 29) & 15) { default: // unreachable case 0: // CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, CLRRDI, CLRRDIo, CLRRWI, CLR... SStream_concat0(O, ", "); break; case 1: // CP_COPY_FIRST, CP_COPYx, CP_PASTE_LAST, CP_PASTEx, DCBTCT, DCBTDS, DCB... return; break; case 2: // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32 SStream_concat0(O, " "); printOperand(MI, 3, O); SStream_concat0(O, " "); printOperand(MI, 4, O); return; break; case 3: // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64 printU5ImmOperand(MI, 0, O); return; break; case 4: // EVSEL SStream_concat0(O, ","); printOperand(MI, 2, O); return; break; case 5: // LBARXL, LDARXL, LHARXL, LWARXL SStream_concat0(O, ", 1"); op_addImm(MI, 1); return; break; case 6: // RLDIMI, RLDIMIo printU6ImmOperand(MI, 3, O); SStream_concat0(O, ", "); printU6ImmOperand(MI, 4, O); return; break; case 7: // RLWIMI, RLWIMI8, RLWIMI8o, RLWIMIo printU5ImmOperand(MI, 3, O); SStream_concat0(O, ", "); printU5ImmOperand(MI, 4, O); SStream_concat0(O, ", "); printU5ImmOperand(MI, 5, O); return; break; case 8: // VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTW printU5ImmOperand(MI, 1, O); return; break; case 9: // VCFSX_0, VCFUX_0, VCTSXS_0, VCTUXS_0 SStream_concat0(O, ", 0"); op_addImm(MI, 0); return; break; case 10: // VEXTRACTD, VEXTRACTUB, VEXTRACTUH, VEXTRACTUW, VINSERTD, VINSERTW printU4ImmOperand(MI, 1, O); return; break; case 11: // XSMADDADP, XSMADDASP, XSMADDMDP, XSMADDMSP, XSMADDQP, XSMADDQPO, XSMSU... printOperand(MI, 3, O); return; break; case 12: // XSTSTDCDP, XSTSTDCQP, XSTSTDCSP, XVTSTDCDP, XVTSTDCSP printU7ImmOperand(MI, 1, O); return; break; case 13: // XXINSERTW printU4ImmOperand(MI, 3, O); return; break; } // Fragment 4 encoded into 4 bits for 13 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 33) & 15)); switch ((Bits >> 33) & 15) { default: // unreachable case 0: // CLRLSLDI, CLRLSLDIo, CLRRDI, CLRRDIo, EXTLDI, EXTLDIo, EXTRDI, EXTRDIo... printU6ImmOperand(MI, 2, O); break; case 1: // CLRLSLWI, CLRLSLWIo, CLRRWI, CLRRWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo... printU5ImmOperand(MI, 2, O); break; case 2: // SUBI, SUBIC, SUBICo, SUBIS, ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, ADDIS,... printS16ImmOperand(MI, 2, O); return; break; case 3: // ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD... printOperand(MI, 2, O); break; case 4: // ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8... printU16ImmOperand(MI, 2, O); return; break; case 5: // BCDCFNo, BCDCFSQo, BCDCFZo, BCDCTZo, BCDSETSGNo, CP_COPY, CP_COPY8, CP... printU1ImmOperand(MI, 2, O); break; case 6: // CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H, XXLXORdpz, XXLXORspz, XXLXOR... printOperand(MI, 0, O); return; break; case 7: // EVADDIW, XXPERMDIs, XXSLDWIs printOperand(MI, 1, O); break; case 8: // QVESPLATI, QVESPLATIb, QVESPLATIs, XXSPLTW, XXSPLTWs printU2ImmOperand(MI, 2, O); return; break; case 9: // QVFMADD, QVFMADDS, QVFMADDSs, QVFMSUB, QVFMSUBS, QVFMSUBSs, QVFNMADD, ... printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 10: // XXEXTRACTUW printU4ImmOperand(MI, 2, O); return; break; case 11: // gBC, gBCL printBranchOperand(MI, 2, O); return; break; case 12: // gBCA, gBCLA printAbsBranchOperand(MI, 2, O); return; break; } // Fragment 5 encoded into 1 bits for 2 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 37) & 1)); if ((Bits >> 37) & 1) { // CLRRDI, CLRRDIo, CLRRWI, CLRRWIo, ROTRDI, ROTRDIo, ROTRWI, ROTRWIo, SL... return; } else { // CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, EXTLDI, EXTLDIo, EXTLWI, EXT... SStream_concat0(O, ", "); } // Fragment 6 encoded into 3 bits for 8 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 38) & 7)); switch ((Bits >> 38) & 7) { default: // unreachable case 0: // CLRLSLDI, CLRLSLDIo, EXTLDI, EXTLDIo, EXTRDI, EXTRDIo, INSRDI, INSRDIo... printU6ImmOperand(MI, 3, O); return; break; case 1: // CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo... printU5ImmOperand(MI, 3, O); break; case 2: // RLWIMIbm, RLWIMIobm, RLWINMbm, RLWINMobm, RLWNMbm, RLWNMobm, FMADD, FM... printOperand(MI, 3, O); return; break; case 3: // BCDSRo, BCDSo, BCDTRUNCo printU1ImmOperand(MI, 3, O); return; break; case 4: // QVALIGNI, QVALIGNIb, QVALIGNIs, XSRQPI, XSRQPIX, XSRQPXP, XXPERMDI, XX... printU2ImmOperand(MI, 3, O); return; break; case 5: // QVFLOGICAL, QVFLOGICALb, QVFLOGICALs printU12ImmOperand(MI, 3, O); return; break; case 6: // VSHASIGMAD, VSHASIGMAW, VSLDOI printU4ImmOperand(MI, 3, O); return; break; case 7: // XXPERMDIs, XXSLDWIs printU2ImmOperand(MI, 2, O); return; break; } // Fragment 7 encoded into 1 bits for 2 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 41) & 1)); if ((Bits >> 41) & 1) { // RLWINM, RLWINM8, RLWINM8o, RLWINMo, RLWNM, RLWNM8, RLWNM8o, RLWNMo SStream_concat0(O, ", "); printU5ImmOperand(MI, 4, O); return; } else { // CLRLSLWI, CLRLSLWIo, EXTLWI, EXTLWIo, EXTRWI, EXTRWIo, INSLWI, INSLWIo... return; } } #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) { #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) unsigned int I = 0, OpIdx, PrintMethodIdx; char *tmpString; const char *AsmString; switch (MCInst_getOpcode(MI)) { default: return false; case PPC_ADDPCIS: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (ADDPCIS g8rc:$RT, 0) AsmString = "lnia $\x01"; break; } return NULL; case PPC_BCC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 12, crrc:$cc, condbrtarget:$dst) AsmString = "blt $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 12, CR0, condbrtarget:$dst) AsmString = "blt $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 14, crrc:$cc, condbrtarget:$dst) AsmString = "blt- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 14, CR0, condbrtarget:$dst) AsmString = "blt- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 15, crrc:$cc, condbrtarget:$dst) AsmString = "blt+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 15, CR0, condbrtarget:$dst) AsmString = "blt+ $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 44, crrc:$cc, condbrtarget:$dst) AsmString = "bgt $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 44, CR0, condbrtarget:$dst) AsmString = "bgt $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 46, crrc:$cc, condbrtarget:$dst) AsmString = "bgt- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 46, CR0, condbrtarget:$dst) AsmString = "bgt- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 47, crrc:$cc, condbrtarget:$dst) AsmString = "bgt+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 47, CR0, condbrtarget:$dst) AsmString = "bgt+ $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 76, crrc:$cc, condbrtarget:$dst) AsmString = "beq $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 76, CR0, condbrtarget:$dst) AsmString = "beq $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 78, crrc:$cc, condbrtarget:$dst) AsmString = "beq- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 78, CR0, condbrtarget:$dst) AsmString = "beq- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 79, crrc:$cc, condbrtarget:$dst) AsmString = "beq+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 79, CR0, condbrtarget:$dst) AsmString = "beq+ $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 68, crrc:$cc, condbrtarget:$dst) AsmString = "bne $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 68, CR0, condbrtarget:$dst) AsmString = "bne $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 70, crrc:$cc, condbrtarget:$dst) AsmString = "bne- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 70, CR0, condbrtarget:$dst) AsmString = "bne- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCC 71, crrc:$cc, condbrtarget:$dst) AsmString = "bne+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCC 71, CR0, condbrtarget:$dst) AsmString = "bne+ $\xFF\x03\x01"; break; } return NULL; case PPC_BCCA: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 12, crrc:$cc, abscondbrtarget:$dst) AsmString = "blta $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 12, CR0, abscondbrtarget:$dst) AsmString = "blta $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 14, crrc:$cc, abscondbrtarget:$dst) AsmString = "blta- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 14, CR0, abscondbrtarget:$dst) AsmString = "blta- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 15, crrc:$cc, abscondbrtarget:$dst) AsmString = "blta+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 15, CR0, abscondbrtarget:$dst) AsmString = "blta+ $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 44, crrc:$cc, abscondbrtarget:$dst) AsmString = "bgta $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 44, CR0, abscondbrtarget:$dst) AsmString = "bgta $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 46, crrc:$cc, abscondbrtarget:$dst) AsmString = "bgta- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 46, CR0, abscondbrtarget:$dst) AsmString = "bgta- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 47, crrc:$cc, abscondbrtarget:$dst) AsmString = "bgta+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 47, CR0, abscondbrtarget:$dst) AsmString = "bgta+ $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 76, crrc:$cc, abscondbrtarget:$dst) AsmString = "beqa $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 76, CR0, abscondbrtarget:$dst) AsmString = "beqa $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 78, crrc:$cc, abscondbrtarget:$dst) AsmString = "beqa- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 78, CR0, abscondbrtarget:$dst) AsmString = "beqa- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 79, crrc:$cc, abscondbrtarget:$dst) AsmString = "beqa+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 79, CR0, abscondbrtarget:$dst) AsmString = "beqa+ $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 68, crrc:$cc, abscondbrtarget:$dst) AsmString = "bnea $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 68, CR0, abscondbrtarget:$dst) AsmString = "bnea $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 70, crrc:$cc, abscondbrtarget:$dst) AsmString = "bnea- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 70, CR0, abscondbrtarget:$dst) AsmString = "bnea- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCA 71, crrc:$cc, abscondbrtarget:$dst) AsmString = "bnea+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCA 71, CR0, abscondbrtarget:$dst) AsmString = "bnea+ $\xFF\x03\x02"; break; } return NULL; case PPC_BCCCTR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 12, crrc:$cc) AsmString = "bltctr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 12, CR0) AsmString = "bltctr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 14, crrc:$cc) AsmString = "bltctr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 14, CR0) AsmString = "bltctr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 15, crrc:$cc) AsmString = "bltctr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 15, CR0) AsmString = "bltctr+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 44, crrc:$cc) AsmString = "bgtctr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 44, CR0) AsmString = "bgtctr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 46, crrc:$cc) AsmString = "bgtctr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 46, CR0) AsmString = "bgtctr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 47, crrc:$cc) AsmString = "bgtctr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 47, CR0) AsmString = "bgtctr+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 76, crrc:$cc) AsmString = "beqctr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 76, CR0) AsmString = "beqctr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 78, crrc:$cc) AsmString = "beqctr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 78, CR0) AsmString = "beqctr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 79, crrc:$cc) AsmString = "beqctr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 79, CR0) AsmString = "beqctr+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 68, crrc:$cc) AsmString = "bnectr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 68, CR0) AsmString = "bnectr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 70, crrc:$cc) AsmString = "bnectr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 70, CR0) AsmString = "bnectr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTR 71, crrc:$cc) AsmString = "bnectr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTR 71, CR0) AsmString = "bnectr+"; break; } return NULL; case PPC_BCCCTRL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 12, crrc:$cc) AsmString = "bltctrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 12, CR0) AsmString = "bltctrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 14, crrc:$cc) AsmString = "bltctrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 14, CR0) AsmString = "bltctrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 15, crrc:$cc) AsmString = "bltctrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 15, CR0) AsmString = "bltctrl+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 44, crrc:$cc) AsmString = "bgtctrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 44, CR0) AsmString = "bgtctrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 46, crrc:$cc) AsmString = "bgtctrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 46, CR0) AsmString = "bgtctrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 47, crrc:$cc) AsmString = "bgtctrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 47, CR0) AsmString = "bgtctrl+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 76, crrc:$cc) AsmString = "beqctrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 76, CR0) AsmString = "beqctrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 78, crrc:$cc) AsmString = "beqctrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 78, CR0) AsmString = "beqctrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 79, crrc:$cc) AsmString = "beqctrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 79, CR0) AsmString = "beqctrl+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 68, crrc:$cc) AsmString = "bnectrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 68, CR0) AsmString = "bnectrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 70, crrc:$cc) AsmString = "bnectrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 70, CR0) AsmString = "bnectrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCCTRL 71, crrc:$cc) AsmString = "bnectrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCCTRL 71, CR0) AsmString = "bnectrl+"; break; } return NULL; case PPC_BCCL: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 12, crrc:$cc, condbrtarget:$dst) AsmString = "bltl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 12, CR0, condbrtarget:$dst) AsmString = "bltl $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 14, crrc:$cc, condbrtarget:$dst) AsmString = "bltl- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 14, CR0, condbrtarget:$dst) AsmString = "bltl- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 15, crrc:$cc, condbrtarget:$dst) AsmString = "bltl+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 15, CR0, condbrtarget:$dst) AsmString = "bltl+ $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 44, crrc:$cc, condbrtarget:$dst) AsmString = "bgtl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 44, CR0, condbrtarget:$dst) AsmString = "bgtl $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 46, crrc:$cc, condbrtarget:$dst) AsmString = "bgtl- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 46, CR0, condbrtarget:$dst) AsmString = "bgtl- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 47, crrc:$cc, condbrtarget:$dst) AsmString = "bgtl+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 47, CR0, condbrtarget:$dst) AsmString = "bgtl+ $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 76, crrc:$cc, condbrtarget:$dst) AsmString = "beql $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 76, CR0, condbrtarget:$dst) AsmString = "beql $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 78, crrc:$cc, condbrtarget:$dst) AsmString = "beql- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 78, CR0, condbrtarget:$dst) AsmString = "beql- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 79, crrc:$cc, condbrtarget:$dst) AsmString = "beql+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 79, CR0, condbrtarget:$dst) AsmString = "beql+ $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 68, crrc:$cc, condbrtarget:$dst) AsmString = "bnel $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 68, CR0, condbrtarget:$dst) AsmString = "bnel $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 70, crrc:$cc, condbrtarget:$dst) AsmString = "bnel- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 70, CR0, condbrtarget:$dst) AsmString = "bnel- $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCL 71, crrc:$cc, condbrtarget:$dst) AsmString = "bnel+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCL 71, CR0, condbrtarget:$dst) AsmString = "bnel+ $\xFF\x03\x01"; break; } return NULL; case PPC_BCCLA: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 12, crrc:$cc, abscondbrtarget:$dst) AsmString = "bltla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 12, CR0, abscondbrtarget:$dst) AsmString = "bltla $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 14, crrc:$cc, abscondbrtarget:$dst) AsmString = "bltla- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 14, CR0, abscondbrtarget:$dst) AsmString = "bltla- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 15, crrc:$cc, abscondbrtarget:$dst) AsmString = "bltla+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 15, CR0, abscondbrtarget:$dst) AsmString = "bltla+ $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 44, crrc:$cc, abscondbrtarget:$dst) AsmString = "bgtla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 44, CR0, abscondbrtarget:$dst) AsmString = "bgtla $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 46, crrc:$cc, abscondbrtarget:$dst) AsmString = "bgtla- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 46, CR0, abscondbrtarget:$dst) AsmString = "bgtla- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 47, crrc:$cc, abscondbrtarget:$dst) AsmString = "bgtla+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 47, CR0, abscondbrtarget:$dst) AsmString = "bgtla+ $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 76, crrc:$cc, abscondbrtarget:$dst) AsmString = "beqla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 76, CR0, abscondbrtarget:$dst) AsmString = "beqla $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 78, crrc:$cc, abscondbrtarget:$dst) AsmString = "beqla- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 78, CR0, abscondbrtarget:$dst) AsmString = "beqla- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 79, crrc:$cc, abscondbrtarget:$dst) AsmString = "beqla+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 79, CR0, abscondbrtarget:$dst) AsmString = "beqla+ $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 68, crrc:$cc, abscondbrtarget:$dst) AsmString = "bnela $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 68, CR0, abscondbrtarget:$dst) AsmString = "bnela $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 70, crrc:$cc, abscondbrtarget:$dst) AsmString = "bnela- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 70, CR0, abscondbrtarget:$dst) AsmString = "bnela- $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLA 71, crrc:$cc, abscondbrtarget:$dst) AsmString = "bnela+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLA 71, CR0, abscondbrtarget:$dst) AsmString = "bnela+ $\xFF\x03\x02"; break; } return NULL; case PPC_BCCLR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 12, crrc:$cc) AsmString = "bltlr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 12, CR0) AsmString = "bltlr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 14, crrc:$cc) AsmString = "bltlr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 14, CR0) AsmString = "bltlr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 15, crrc:$cc) AsmString = "bltlr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 15, CR0) AsmString = "bltlr+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 44, crrc:$cc) AsmString = "bgtlr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 44, CR0) AsmString = "bgtlr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 46, crrc:$cc) AsmString = "bgtlr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 46, CR0) AsmString = "bgtlr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 47, crrc:$cc) AsmString = "bgtlr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 47, CR0) AsmString = "bgtlr+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 76, crrc:$cc) AsmString = "beqlr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 76, CR0) AsmString = "beqlr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 78, crrc:$cc) AsmString = "beqlr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 78, CR0) AsmString = "beqlr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 79, crrc:$cc) AsmString = "beqlr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 79, CR0) AsmString = "beqlr+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 68, crrc:$cc) AsmString = "bnelr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 68, CR0) AsmString = "bnelr"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 70, crrc:$cc) AsmString = "bnelr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 70, CR0) AsmString = "bnelr-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLR 71, crrc:$cc) AsmString = "bnelr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLR 71, CR0) AsmString = "bnelr+"; break; } return NULL; case PPC_BCCLRL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 12, crrc:$cc) AsmString = "bltlrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 12, CR0) AsmString = "bltlrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 14, crrc:$cc) AsmString = "bltlrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 14, CR0) AsmString = "bltlrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 15, crrc:$cc) AsmString = "bltlrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 15, CR0) AsmString = "bltlrl+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 44, crrc:$cc) AsmString = "bgtlrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 44 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 44, CR0) AsmString = "bgtlrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 46, crrc:$cc) AsmString = "bgtlrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 46 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 46, CR0) AsmString = "bgtlrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 47, crrc:$cc) AsmString = "bgtlrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 47 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 47, CR0) AsmString = "bgtlrl+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 76, crrc:$cc) AsmString = "beqlrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 76 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 76, CR0) AsmString = "beqlrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 78, crrc:$cc) AsmString = "beqlrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 78 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 78, CR0) AsmString = "beqlrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 79, crrc:$cc) AsmString = "beqlrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 79 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 79, CR0) AsmString = "beqlrl+"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 68, crrc:$cc) AsmString = "bnelrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 68 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 68, CR0) AsmString = "bnelrl"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 70, crrc:$cc) AsmString = "bnelrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 70 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 70, CR0) AsmString = "bnelrl-"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 1)) { // (BCCLRL 71, crrc:$cc) AsmString = "bnelrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 71 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) { // (BCCLRL 71, CR0) AsmString = "bnelrl+"; break; } return NULL; case PPC_CMPD: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (CMPD CR0, g8rc:$rA, g8rc:$rB) AsmString = "cmpd $\x02, $\x03"; break; } return NULL; case PPC_CMPDI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (CMPDI CR0, g8rc:$rA, s16imm64:$imm) AsmString = "cmpdi $\x02, $\xFF\x03\x03"; break; } return NULL; case PPC_CMPLD: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (CMPLD CR0, g8rc:$rA, g8rc:$rB) AsmString = "cmpld $\x02, $\x03"; break; } return NULL; case PPC_CMPLDI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm) AsmString = "cmpldi $\x02, $\xFF\x03\x04"; break; } return NULL; case PPC_CMPLW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (CMPLW CR0, gprc:$rA, gprc:$rB) AsmString = "cmplw $\x02, $\x03"; break; } return NULL; case PPC_CMPLWI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (CMPLWI CR0, gprc:$rA, u16imm:$imm) AsmString = "cmplwi $\x02, $\xFF\x03\x04"; break; } return NULL; case PPC_CMPW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (CMPW CR0, gprc:$rA, gprc:$rB) AsmString = "cmpw $\x02, $\x03"; break; } return NULL; case PPC_CMPWI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_CR0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (CMPWI CR0, gprc:$rA, s16imm:$imm) AsmString = "cmpwi $\x02, $\xFF\x03\x03"; break; } return NULL; case PPC_CNTLZW: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (CNTLZW gprc:$rA, gprc:$rS) AsmString = "cntlzw $\x01, $\x02"; break; } return NULL; case PPC_CNTLZWo: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (CNTLZWo gprc:$rA, gprc:$rS) AsmString = "cntlzw. $\x01, $\x02"; break; } return NULL; case PPC_CREQV: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { // (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) AsmString = "crset $\x01"; break; } return NULL; case PPC_CRNOR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by) AsmString = "crnot $\x01, $\x02"; break; } return NULL; case PPC_CROR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by) AsmString = "crmove $\x01, $\x02"; break; } return NULL; case PPC_CRXOR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { // (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) AsmString = "crclr $\x01"; break; } return NULL; case PPC_MBAR: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (MBAR 0) AsmString = "mbar"; break; } return NULL; case PPC_MFDCR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 128) { // (MFDCR gprc:$Rx, 128) AsmString = "mfbr0 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 129) { // (MFDCR gprc:$Rx, 129) AsmString = "mfbr1 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 130) { // (MFDCR gprc:$Rx, 130) AsmString = "mfbr2 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 131) { // (MFDCR gprc:$Rx, 131) AsmString = "mfbr3 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 132) { // (MFDCR gprc:$Rx, 132) AsmString = "mfbr4 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 133) { // (MFDCR gprc:$Rx, 133) AsmString = "mfbr5 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 134) { // (MFDCR gprc:$Rx, 134) AsmString = "mfbr6 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 135) { // (MFDCR gprc:$Rx, 135) AsmString = "mfbr7 $\x01"; break; } return NULL; case PPC_MFSPR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (MFSPR gprc:$Rx, 1) AsmString = "mfxer $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (MFSPR gprc:$Rx, 4) AsmString = "mfrtcu $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (MFSPR gprc:$Rx, 5) AsmString = "mfrtcl $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 17) { // (MFSPR gprc:$Rx, 17) AsmString = "mfdscr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 18) { // (MFSPR gprc:$Rx, 18) AsmString = "mfdsisr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 19) { // (MFSPR gprc:$Rx, 19) AsmString = "mfdar $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 990) { // (MFSPR gprc:$Rx, 990) AsmString = "mfsrr2 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 991) { // (MFSPR gprc:$Rx, 991) AsmString = "mfsrr3 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 28) { // (MFSPR gprc:$Rx, 28) AsmString = "mfcfar $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 29) { // (MFSPR gprc:$Rx, 29) AsmString = "mfamr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 48) { // (MFSPR gprc:$Rx, 48) AsmString = "mfpid $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 989) { // (MFSPR gprc:$Rx, 989) AsmString = "mftblo $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 988) { // (MFSPR gprc:$Rx, 988) AsmString = "mftbhi $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 536) { // (MFSPR gprc:$Rx, 536) AsmString = "mfdbatu $\x01, 0"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 537) { // (MFSPR gprc:$Rx, 537) AsmString = "mfdbatl $\x01, 0"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 528) { // (MFSPR gprc:$Rx, 528) AsmString = "mfibatu $\x01, 0"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 529) { // (MFSPR gprc:$Rx, 529) AsmString = "mfibatl $\x01, 0"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 538) { // (MFSPR gprc:$Rx, 538) AsmString = "mfdbatu $\x01, 1"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 539) { // (MFSPR gprc:$Rx, 539) AsmString = "mfdbatl $\x01, 1"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 530) { // (MFSPR gprc:$Rx, 530) AsmString = "mfibatu $\x01, 1"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 531) { // (MFSPR gprc:$Rx, 531) AsmString = "mfibatl $\x01, 1"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 540) { // (MFSPR gprc:$Rx, 540) AsmString = "mfdbatu $\x01, 2"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 541) { // (MFSPR gprc:$Rx, 541) AsmString = "mfdbatl $\x01, 2"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 532) { // (MFSPR gprc:$Rx, 532) AsmString = "mfibatu $\x01, 2"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 533) { // (MFSPR gprc:$Rx, 533) AsmString = "mfibatl $\x01, 2"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 542) { // (MFSPR gprc:$Rx, 542) AsmString = "mfdbatu $\x01, 3"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 543) { // (MFSPR gprc:$Rx, 543) AsmString = "mfdbatl $\x01, 3"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 534) { // (MFSPR gprc:$Rx, 534) AsmString = "mfibatu $\x01, 3"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 535) { // (MFSPR gprc:$Rx, 535) AsmString = "mfibatl $\x01, 3"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1018) { // (MFSPR gprc:$Rx, 1018) AsmString = "mfdccr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1019) { // (MFSPR gprc:$Rx, 1019) AsmString = "mficcr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 981) { // (MFSPR gprc:$Rx, 981) AsmString = "mfdear $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 980) { // (MFSPR gprc:$Rx, 980) AsmString = "mfesr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 512) { // (MFSPR gprc:$Rx, 512) AsmString = "mfspefscr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 986) { // (MFSPR gprc:$Rx, 986) AsmString = "mftcr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 280) { // (MFSPR gprc:$RT, 280) AsmString = "mfasr $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 287) { // (MFSPR gprc:$RT, 287) AsmString = "mfpvr $\x01"; break; } return NULL; case PPC_MFTB: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 269) { // (MFTB gprc:$Rx, 269) AsmString = "mftbu $\x01"; break; } return NULL; case PPC_MFVRSAVE: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0)) { // (MFVRSAVE gprc:$rS) AsmString = "mfvrsave $\x01"; break; } return NULL; case PPC_MFVSRD: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1)) { // (MFVSRD g8rc:$rA, f8rc:$src) AsmString = "mffprd $\x01, $\x02"; break; } return NULL; case PPC_MTCRF8: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 255 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (MTCRF8 255, g8rc:$rA) AsmString = "mtcr $\x02"; break; } return NULL; case PPC_MTDCR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 128) { // (MTDCR gprc:$Rx, 128) AsmString = "mtbr0 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 129) { // (MTDCR gprc:$Rx, 129) AsmString = "mtbr1 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 130) { // (MTDCR gprc:$Rx, 130) AsmString = "mtbr2 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 131) { // (MTDCR gprc:$Rx, 131) AsmString = "mtbr3 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 132) { // (MTDCR gprc:$Rx, 132) AsmString = "mtbr4 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 133) { // (MTDCR gprc:$Rx, 133) AsmString = "mtbr5 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 134) { // (MTDCR gprc:$Rx, 134) AsmString = "mtbr6 $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 135) { // (MTDCR gprc:$Rx, 135) AsmString = "mtbr7 $\x01"; break; } return NULL; case PPC_MTFSF: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0) AsmString = "mtfsf $\x01, $\x02"; break; } return NULL; case PPC_MTFSFI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (MTFSFI crrc:$BF, i32imm:$U, 0) AsmString = "mtfsfi $\x01, $\x02"; break; } return NULL; case PPC_MTFSFIo: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_CRRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (MTFSFIo crrc:$BF, i32imm:$U, 0) AsmString = "mtfsfi. $\x01, $\x02"; break; } return NULL; case PPC_MTFSFo: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_F8RCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0) AsmString = "mtfsf. $\x01, $\x02"; break; } return NULL; case PPC_MTMSR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (MTMSR gprc:$RS, 0) AsmString = "mtmsr $\x01"; break; } return NULL; case PPC_MTMSRD: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (MTMSRD gprc:$RS, 0) AsmString = "mtmsrd $\x01"; break; } return NULL; case PPC_MTSPR: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 1, gprc:$Rx) AsmString = "mtxer $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 17 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 17, gprc:$Rx) AsmString = "mtdscr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 18 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 18, gprc:$Rx) AsmString = "mtdsisr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 19 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 19, gprc:$Rx) AsmString = "mtdar $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 990 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 990, gprc:$Rx) AsmString = "mtsrr2 $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 991 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 991, gprc:$Rx) AsmString = "mtsrr3 $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 28 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 28, gprc:$Rx) AsmString = "mtcfar $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 29 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 29, gprc:$Rx) AsmString = "mtamr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 48 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 48, gprc:$Rx) AsmString = "mtpid $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 284 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 284, gprc:$Rx) AsmString = "mttbl $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 285 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 285, gprc:$Rx) AsmString = "mttbu $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 989 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 989, gprc:$Rx) AsmString = "mttblo $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 988 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 988, gprc:$Rx) AsmString = "mttbhi $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 536 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 536, gprc:$Rx) AsmString = "mtdbatu 0, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 537 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 537, gprc:$Rx) AsmString = "mtdbatl 0, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 528 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 528, gprc:$Rx) AsmString = "mtibatu 0, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 529 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 529, gprc:$Rx) AsmString = "mtibatl 0, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 538 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 538, gprc:$Rx) AsmString = "mtdbatu 1, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 539 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 539, gprc:$Rx) AsmString = "mtdbatl 1, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 530 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 530, gprc:$Rx) AsmString = "mtibatu 1, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 531 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 531, gprc:$Rx) AsmString = "mtibatl 1, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 540 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 540, gprc:$Rx) AsmString = "mtdbatu 2, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 541 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 541, gprc:$Rx) AsmString = "mtdbatl 2, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 532 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 532, gprc:$Rx) AsmString = "mtibatu 2, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 533 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 533, gprc:$Rx) AsmString = "mtibatl 2, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 542 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 542, gprc:$Rx) AsmString = "mtdbatu 3, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 543 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 543, gprc:$Rx) AsmString = "mtdbatl 3, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 534 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 534, gprc:$Rx) AsmString = "mtibatu 3, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 535 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 535, gprc:$Rx) AsmString = "mtibatl 3, $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1018 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 1018, gprc:$Rx) AsmString = "mtdccr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1019 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 1019, gprc:$Rx) AsmString = "mticcr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 981 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 981, gprc:$Rx) AsmString = "mtdear $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 980 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 980, gprc:$Rx) AsmString = "mtesr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 512 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 512, gprc:$Rx) AsmString = "mtspefscr $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 986 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (MTSPR 986, gprc:$Rx) AsmString = "mttcr $\x02"; break; } return NULL; case PPC_MTVRSAVE: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0)) { // (MTVRSAVE gprc:$rS) AsmString = "mtvrsave $\x01"; break; } return NULL; case PPC_NOR8: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "not $\x01, $\x02"; break; } return NULL; case PPC_NOR8o: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "not. $\x01, $\x02"; break; } return NULL; case PPC_OR8: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "mr $\x01, $\x02"; break; } return NULL; case PPC_OR8o: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB) AsmString = "mr. $\x01, $\x02"; break; } return NULL; case PPC_QVFLOGICALb: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 0) AsmString = "qvfclr $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 1) AsmString = "qvfand $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 4) AsmString = "qvfandc $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 5) AsmString = "qvfctfb $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 6) AsmString = "qvfxor $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 7) AsmString = "qvfor $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 8) AsmString = "qvfnor $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 9) AsmString = "qvfequ $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRA, 10) AsmString = "qvfnot $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 13) AsmString = "qvforc $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRA, qbrc:$FRB, 14) AsmString = "qvfnand $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_QBRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (QVFLOGICALb qbrc:$FRT, qbrc:$FRT, qbrc:$FRT, 15) AsmString = "qvfset $\x01"; break; } return NULL; case PPC_RLDCL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0) AsmString = "rotld $\x01, $\x02, $\x03"; break; } return NULL; case PPC_RLDCLo: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0) AsmString = "rotld. $\x01, $\x02, $\x03"; break; } return NULL; case PPC_RLDICL: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0) AsmString = "rotldi $\x01, $\x02, $\xFF\x03\x05"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n) AsmString = "clrldi $\x01, $\x02, $\xFF\x04\x05"; break; } return NULL; case PPC_RLDICL_32_64: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n) AsmString = "clrldi $\x01, $\x02, $\xFF\x04\x05"; break; } return NULL; case PPC_RLDICLo: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0) AsmString = "rotldi. $\x01, $\x02, $\xFF\x03\x05"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n) AsmString = "clrldi. $\x01, $\x02, $\xFF\x04\x05"; break; } return NULL; case PPC_RLWINM: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { // (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) AsmString = "rotlwi $\x01, $\x02, $\xFF\x03\x06"; break; } if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { // (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) AsmString = "clrlwi $\x01, $\x02, $\xFF\x04\x06"; break; } return NULL; case PPC_RLWINMo: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { // (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) AsmString = "rotlwi. $\x01, $\x02, $\xFF\x03\x06"; break; } if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { // (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) AsmString = "clrlwi. $\x01, $\x02, $\xFF\x04\x06"; break; } return NULL; case PPC_RLWNM: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { // (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) AsmString = "rotlw $\x01, $\x02, $\x03"; break; } return NULL; case PPC_RLWNMo: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 31) { // (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) AsmString = "rotlw. $\x01, $\x02, $\x03"; break; } return NULL; case PPC_SC: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (SC 0) AsmString = "sc"; break; } return NULL; case PPC_SUBF8: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB) AsmString = "sub $\x01, $\x03, $\x02"; break; } return NULL; case PPC_SUBF8o: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB) AsmString = "sub. $\x01, $\x03, $\x02"; break; } return NULL; case PPC_SUBFC8: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB) AsmString = "subc $\x01, $\x03, $\x02"; break; } return NULL; case PPC_SUBFC8o: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB) AsmString = "subc. $\x01, $\x03, $\x02"; break; } return NULL; case PPC_SYNC: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (SYNC 0) AsmString = "sync"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { // (SYNC 1) AsmString = "lwsync"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { // (SYNC 2) AsmString = "ptesync"; break; } return NULL; case PPC_TD: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 16, g8rc:$rA, g8rc:$rB) AsmString = "tdlt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 4, g8rc:$rA, g8rc:$rB) AsmString = "tdeq $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 8, g8rc:$rA, g8rc:$rB) AsmString = "tdgt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 24, g8rc:$rA, g8rc:$rB) AsmString = "tdne $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 2, g8rc:$rA, g8rc:$rB) AsmString = "tdllt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 1, g8rc:$rA, g8rc:$rB) AsmString = "tdlgt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 2)) { // (TD 31, g8rc:$rA, g8rc:$rB) AsmString = "tdu $\x02, $\x03"; break; } return NULL; case PPC_TDI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 16, g8rc:$rA, s16imm:$imm) AsmString = "tdlti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 4, g8rc:$rA, s16imm:$imm) AsmString = "tdeqi $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 8, g8rc:$rA, s16imm:$imm) AsmString = "tdgti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 24, g8rc:$rA, s16imm:$imm) AsmString = "tdnei $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 2, g8rc:$rA, s16imm:$imm) AsmString = "tdllti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 1, g8rc:$rA, s16imm:$imm) AsmString = "tdlgti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_G8RCRegClassID, 1)) { // (TDI 31, g8rc:$rA, s16imm:$imm) AsmString = "tdui $\x02, $\xFF\x03\x03"; break; } return NULL; case PPC_TLBIE: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_R0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TLBIE R0, gprc:$RB) AsmString = "tlbie $\x02"; break; } return NULL; case PPC_TLBRE2: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TLBRE2 gprc:$RS, gprc:$A, 0) AsmString = "tlbrehi $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (TLBRE2 gprc:$RS, gprc:$A, 1) AsmString = "tlbrelo $\x01, $\x02"; break; } return NULL; case PPC_TLBWE2: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TLBWE2 gprc:$RS, gprc:$A, 0) AsmString = "tlbwehi $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (TLBWE2 gprc:$RS, gprc:$A, 1) AsmString = "tlbwelo $\x01, $\x02"; break; } return NULL; case PPC_TW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 16, gprc:$rA, gprc:$rB) AsmString = "twlt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 4, gprc:$rA, gprc:$rB) AsmString = "tweq $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 8, gprc:$rA, gprc:$rB) AsmString = "twgt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 24, gprc:$rA, gprc:$rB) AsmString = "twne $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 2, gprc:$rA, gprc:$rB) AsmString = "twllt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 1, gprc:$rA, gprc:$rB) AsmString = "twlgt $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 2)) { // (TW 31, gprc:$rA, gprc:$rB) AsmString = "twu $\x02, $\x03"; break; } return NULL; case PPC_TWI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 16, gprc:$rA, s16imm:$imm) AsmString = "twlti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 4, gprc:$rA, s16imm:$imm) AsmString = "tweqi $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 8, gprc:$rA, s16imm:$imm) AsmString = "twgti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 24, gprc:$rA, s16imm:$imm) AsmString = "twnei $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 2, gprc:$rA, s16imm:$imm) AsmString = "twllti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 1, gprc:$rA, s16imm:$imm) AsmString = "twlgti $\x02, $\xFF\x03\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 31 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_GPRCRegClassID, 1)) { // (TWI 31, gprc:$rA, s16imm:$imm) AsmString = "twui $\x02, $\xFF\x03\x03"; break; } return NULL; case PPC_VNOR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA) AsmString = "vnot $\x01, $\x02"; break; } return NULL; case PPC_VOR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VRRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA) AsmString = "vmr $\x01, $\x02"; break; } return NULL; case PPC_WAIT: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { // (WAIT 0) AsmString = "wait"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { // (WAIT 1) AsmString = "waitrsv"; break; } if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { // (WAIT 2) AsmString = "waitimpl"; break; } return NULL; case PPC_XORI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == PPC_R0 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_R0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (XORI R0, R0, 0) AsmString = "xnop"; break; } return NULL; case PPC_XVCPSGNDP: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB) AsmString = "xvmovdp $\x01, $\x02"; break; } return NULL; case PPC_XVCPSGNSP: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB) AsmString = "xvmovsp $\x01, $\x02"; break; } return NULL; case PPC_XXPERMDI: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0) AsmString = "xxspltd $\x01, $\x02, 0"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3) AsmString = "xxspltd $\x01, $\x02, 1"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0) AsmString = "xxmrghd $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3) AsmString = "xxmrgld $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2) AsmString = "xxswapd $\x01, $\x02"; break; } return NULL; case PPC_XXPERMDIs: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSFRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0) AsmString = "xxspltd $\x01, $\x02, 0"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSFRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3) AsmString = "xxspltd $\x01, $\x02, 1"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(PPC_VSRCRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_VSFRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2) AsmString = "xxswapd $\x01, $\x02"; break; } return NULL; case PPC_gBC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 12, crbitrc:$bi, condbrtarget:$dst) AsmString = "bt $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 4, crbitrc:$bi, condbrtarget:$dst) AsmString = "bf $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 14, crbitrc:$bi, condbrtarget:$dst) AsmString = "bt- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 6, crbitrc:$bi, condbrtarget:$dst) AsmString = "bf- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 15, crbitrc:$bi, condbrtarget:$dst) AsmString = "bt+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 7, crbitrc:$bi, condbrtarget:$dst) AsmString = "bf+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 8, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdnzt $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 0, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdnzf $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 10, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdzt $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBC 2, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdzf $\x02, $\xFF\x03\x01"; break; } return NULL; case PPC_gBCA: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 12, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bta $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 4, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bfa $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 14, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bta- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 6, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bfa- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 15, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bta+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 7, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bfa+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 8, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdnzta $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 0, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdnzfa $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 10, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdzta $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCA 2, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdzfa $\x02, $\xFF\x03\x02"; break; } return NULL; case PPC_gBCAat: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) AsmString = "bca+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) AsmString = "bca- $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } return NULL; case PPC_gBCCTR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR u5imm:$bo, crbitrc:$bi, 0) AsmString = "bcctr $\xFF\x01\x06, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR 12, crbitrc:$bi, 0) AsmString = "btctr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR 4, crbitrc:$bi, 0) AsmString = "bfctr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR 14, crbitrc:$bi, 0) AsmString = "btctr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR 6, crbitrc:$bi, 0) AsmString = "bfctr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR 15, crbitrc:$bi, 0) AsmString = "btctr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTR 7, crbitrc:$bi, 0) AsmString = "bfctr+ $\x02"; break; } return NULL; case PPC_gBCCTRL: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL u5imm:$bo, crbitrc:$bi, 0) AsmString = "bcctrl $\xFF\x01\x06, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL 12, crbitrc:$bi, 0) AsmString = "btctrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL 4, crbitrc:$bi, 0) AsmString = "bfctrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL 14, crbitrc:$bi, 0) AsmString = "btctrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL 6, crbitrc:$bi, 0) AsmString = "bfctrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL 15, crbitrc:$bi, 0) AsmString = "btctrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCCTRL 7, crbitrc:$bi, 0) AsmString = "bfctrl+ $\x02"; break; } return NULL; case PPC_gBCL: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 12, crbitrc:$bi, condbrtarget:$dst) AsmString = "btl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 4, crbitrc:$bi, condbrtarget:$dst) AsmString = "bfl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 14, crbitrc:$bi, condbrtarget:$dst) AsmString = "btl- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 6, crbitrc:$bi, condbrtarget:$dst) AsmString = "bfl- $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 15, crbitrc:$bi, condbrtarget:$dst) AsmString = "btl+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 7, crbitrc:$bi, condbrtarget:$dst) AsmString = "bfl+ $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 8, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdnztl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 0, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdnzfl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 10, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdztl $\x02, $\xFF\x03\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCL 2, crbitrc:$bi, condbrtarget:$dst) AsmString = "bdzfl $\x02, $\xFF\x03\x01"; break; } return NULL; case PPC_gBCLA: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 12, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "btla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 4, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bfla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 14, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "btla- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 6, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bfla- $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 15, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "btla+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 7, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bfla+ $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 8, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdnztla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 0, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdnzfla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 10, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdztla $\x02, $\xFF\x03\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { // (gBCLA 2, crbitrc:$bi, abscondbrtarget:$dst) AsmString = "bdzfla $\x02, $\xFF\x03\x02"; break; } return NULL; case PPC_gBCLAat: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCLAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) AsmString = "bcla+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCLAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) AsmString = "bcla- $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } return NULL; case PPC_gBCLR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR u5imm:$bo, crbitrc:$bi, 0) AsmString = "bclr $\xFF\x01\x06, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 12, crbitrc:$bi, 0) AsmString = "btlr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 4, crbitrc:$bi, 0) AsmString = "bflr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 14, crbitrc:$bi, 0) AsmString = "btlr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 6, crbitrc:$bi, 0) AsmString = "bflr- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 15, crbitrc:$bi, 0) AsmString = "btlr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 7, crbitrc:$bi, 0) AsmString = "bflr+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 8, crbitrc:$bi, 0) AsmString = "bdnztlr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 0, crbitrc:$bi, 0) AsmString = "bdnzflr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 10, crbitrc:$bi, 0) AsmString = "bdztlr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLR 2, crbitrc:$bi, 0) AsmString = "bdzflr $\x02"; break; } return NULL; case PPC_gBCLRL: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL u5imm:$bo, crbitrc:$bi, 0) AsmString = "bclrl $\xFF\x01\x06, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 12, crbitrc:$bi, 0) AsmString = "btlrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 4, crbitrc:$bi, 0) AsmString = "bflrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 14, crbitrc:$bi, 0) AsmString = "btlrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 6, crbitrc:$bi, 0) AsmString = "bflrl- $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 15, crbitrc:$bi, 0) AsmString = "btlrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 7, crbitrc:$bi, 0) AsmString = "bflrl+ $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 8, crbitrc:$bi, 0) AsmString = "bdnztlrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 0, crbitrc:$bi, 0) AsmString = "bdnzflrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 10, crbitrc:$bi, 0) AsmString = "bdztlrl $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (gBCLRL 2, crbitrc:$bi, 0) AsmString = "bdzflrl $\x02"; break; } return NULL; case PPC_gBCLat: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCLat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) AsmString = "bcl+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCLat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) AsmString = "bcl- $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } return NULL; case PPC_gBCat: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) AsmString = "bc+ $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 2)) { // (gBCat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) AsmString = "bc- $\xFF\x01\x06, $\x03, $\xFF\x04\x01"; break; } return NULL; } tmpString = cs_strdup(AsmString); while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && AsmString[I] != '\0') ++I; tmpString[I] = 0; SStream_concat0(OS, tmpString); if (AsmString[I] != '\0') { if (AsmString[I] == ' ' || AsmString[I] == '\t') { SStream_concat0(OS, " "); ++I; } do { if (AsmString[I] == '$') { ++I; if (AsmString[I] == (char)0xff) { ++I; OpIdx = AsmString[I++] - 1; PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } else { SStream_concat1(OS, AsmString[I++]); } } while (AsmString[I] != '\0'); } return tmpString; } static void printCustomAliasOperand( MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: break; case 0: printBranchOperand(MI, OpIdx, OS); break; case 1: printAbsBranchOperand(MI, OpIdx, OS); break; case 2: printS16ImmOperand(MI, OpIdx, OS); break; case 3: printU16ImmOperand(MI, OpIdx, OS); break; case 4: printU6ImmOperand(MI, OpIdx, OS); break; case 5: printU5ImmOperand(MI, OpIdx, OS); break; } } #endif // PRINT_ALIAS_INSTR capstone-sys-0.15.0/capstone/arch/PowerPC/PPCGenDisassemblerTables.inc000064400000000000000000014526610072674642500237160ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /* Automatically generated file, do not edit! */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. //#if defined(_MSC_VER) && !defined(__clang__) //__declspec(noinline) //#endif #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 3 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 20 /* 8 */ MCD_OPC_CheckField, 1, 10, 128, 2, 34, 64, 0, // Skip to: 16434 /* 16 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: ATTN /* 20 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 29 /* 25 */ MCD_OPC_Decode, 165, 12, 1, // Opcode: TDI /* 29 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 38 /* 34 */ MCD_OPC_Decode, 186, 12, 2, // Opcode: TWI /* 38 */ MCD_OPC_FilterValue, 4, 12, 12, 0, // Skip to: 3127 /* 43 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 46 */ MCD_OPC_FilterValue, 0, 237, 0, 0, // Skip to: 288 /* 51 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 54 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 63 /* 59 */ MCD_OPC_Decode, 200, 12, 3, // Opcode: VADDUBM /* 63 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 72 /* 68 */ MCD_OPC_Decode, 203, 12, 3, // Opcode: VADDUHM /* 72 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 81 /* 77 */ MCD_OPC_Decode, 206, 12, 3, // Opcode: VADDUWM /* 81 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 90 /* 86 */ MCD_OPC_Decode, 202, 12, 3, // Opcode: VADDUDM /* 90 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 99 /* 95 */ MCD_OPC_Decode, 205, 12, 3, // Opcode: VADDUQM /* 99 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 108 /* 104 */ MCD_OPC_Decode, 192, 12, 3, // Opcode: VADDCUQ /* 108 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 117 /* 113 */ MCD_OPC_Decode, 193, 12, 3, // Opcode: VADDCUW /* 117 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 126 /* 122 */ MCD_OPC_Decode, 201, 12, 3, // Opcode: VADDUBS /* 126 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 135 /* 131 */ MCD_OPC_Decode, 204, 12, 3, // Opcode: VADDUHS /* 135 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 144 /* 140 */ MCD_OPC_Decode, 207, 12, 3, // Opcode: VADDUWS /* 144 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 153 /* 149 */ MCD_OPC_Decode, 197, 12, 3, // Opcode: VADDSBS /* 153 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 162 /* 158 */ MCD_OPC_Decode, 198, 12, 3, // Opcode: VADDSHS /* 162 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 171 /* 167 */ MCD_OPC_Decode, 199, 12, 3, // Opcode: VADDSWS /* 171 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 180 /* 176 */ MCD_OPC_Decode, 196, 14, 3, // Opcode: VSUBUBM /* 180 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 189 /* 185 */ MCD_OPC_Decode, 199, 14, 3, // Opcode: VSUBUHM /* 189 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 198 /* 194 */ MCD_OPC_Decode, 202, 14, 3, // Opcode: VSUBUWM /* 198 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 207 /* 203 */ MCD_OPC_Decode, 198, 14, 3, // Opcode: VSUBUDM /* 207 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 216 /* 212 */ MCD_OPC_Decode, 201, 14, 3, // Opcode: VSUBUQM /* 216 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 225 /* 221 */ MCD_OPC_Decode, 188, 14, 3, // Opcode: VSUBCUQ /* 225 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 234 /* 230 */ MCD_OPC_Decode, 189, 14, 3, // Opcode: VSUBCUW /* 234 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 243 /* 239 */ MCD_OPC_Decode, 197, 14, 3, // Opcode: VSUBUBS /* 243 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 252 /* 248 */ MCD_OPC_Decode, 200, 14, 3, // Opcode: VSUBUHS /* 252 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 261 /* 257 */ MCD_OPC_Decode, 203, 14, 3, // Opcode: VSUBUWS /* 261 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 270 /* 266 */ MCD_OPC_Decode, 193, 14, 3, // Opcode: VSUBSBS /* 270 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 279 /* 275 */ MCD_OPC_Decode, 194, 14, 3, // Opcode: VSUBSHS /* 279 */ MCD_OPC_FilterValue, 30, 22, 63, 0, // Skip to: 16434 /* 284 */ MCD_OPC_Decode, 195, 14, 3, // Opcode: VSUBSWS /* 288 */ MCD_OPC_FilterValue, 1, 9, 1, 0, // Skip to: 558 /* 293 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... /* 296 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 322 /* 301 */ MCD_OPC_ExtractField, 9, 7, // Inst{15-9} ... /* 304 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 313 /* 309 */ MCD_OPC_Decode, 218, 13, 4, // Opcode: VMUL10CUQ /* 313 */ MCD_OPC_FilterValue, 1, 244, 62, 0, // Skip to: 16434 /* 318 */ MCD_OPC_Decode, 221, 13, 4, // Opcode: VMUL10UQ /* 322 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 348 /* 327 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 330 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 339 /* 335 */ MCD_OPC_Decode, 219, 13, 3, // Opcode: VMUL10ECUQ /* 339 */ MCD_OPC_FilterValue, 1, 218, 62, 0, // Skip to: 16434 /* 344 */ MCD_OPC_Decode, 220, 13, 3, // Opcode: VMUL10EUQ /* 348 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 364 /* 353 */ MCD_OPC_CheckField, 9, 2, 2, 202, 62, 0, // Skip to: 16434 /* 360 */ MCD_OPC_Decode, 222, 2, 3, // Opcode: BCDUSo /* 364 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 380 /* 369 */ MCD_OPC_CheckField, 10, 1, 1, 186, 62, 0, // Skip to: 16434 /* 376 */ MCD_OPC_Decode, 220, 2, 5, // Opcode: BCDSo /* 380 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 396 /* 385 */ MCD_OPC_CheckField, 10, 1, 1, 170, 62, 0, // Skip to: 16434 /* 392 */ MCD_OPC_Decode, 221, 2, 5, // Opcode: BCDTRUNCo /* 396 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 422 /* 401 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 404 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 413 /* 409 */ MCD_OPC_Decode, 214, 2, 3, // Opcode: BCDCPSGNo /* 413 */ MCD_OPC_FilterValue, 2, 144, 62, 0, // Skip to: 16434 /* 418 */ MCD_OPC_Decode, 223, 2, 3, // Opcode: BCDUTRUNCo /* 422 */ MCD_OPC_FilterValue, 6, 115, 0, 0, // Skip to: 542 /* 427 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 430 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 446 /* 435 */ MCD_OPC_CheckField, 9, 2, 2, 120, 62, 0, // Skip to: 16434 /* 442 */ MCD_OPC_Decode, 216, 2, 6, // Opcode: BCDCTSQo /* 446 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 462 /* 451 */ MCD_OPC_CheckField, 10, 1, 1, 104, 62, 0, // Skip to: 16434 /* 458 */ MCD_OPC_Decode, 212, 2, 7, // Opcode: BCDCFSQo /* 462 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 478 /* 467 */ MCD_OPC_CheckField, 10, 1, 1, 88, 62, 0, // Skip to: 16434 /* 474 */ MCD_OPC_Decode, 217, 2, 7, // Opcode: BCDCTZo /* 478 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 494 /* 483 */ MCD_OPC_CheckField, 9, 2, 2, 72, 62, 0, // Skip to: 16434 /* 490 */ MCD_OPC_Decode, 215, 2, 6, // Opcode: BCDCTNo /* 494 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 510 /* 499 */ MCD_OPC_CheckField, 10, 1, 1, 56, 62, 0, // Skip to: 16434 /* 506 */ MCD_OPC_Decode, 213, 2, 7, // Opcode: BCDCFZo /* 510 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 526 /* 515 */ MCD_OPC_CheckField, 10, 1, 1, 40, 62, 0, // Skip to: 16434 /* 522 */ MCD_OPC_Decode, 211, 2, 7, // Opcode: BCDCFNo /* 526 */ MCD_OPC_FilterValue, 31, 31, 62, 0, // Skip to: 16434 /* 531 */ MCD_OPC_CheckField, 10, 1, 1, 24, 62, 0, // Skip to: 16434 /* 538 */ MCD_OPC_Decode, 218, 2, 7, // Opcode: BCDSETSGNo /* 542 */ MCD_OPC_FilterValue, 7, 15, 62, 0, // Skip to: 16434 /* 547 */ MCD_OPC_CheckField, 10, 1, 1, 8, 62, 0, // Skip to: 16434 /* 554 */ MCD_OPC_Decode, 219, 2, 5, // Opcode: BCDSRo /* 558 */ MCD_OPC_FilterValue, 2, 179, 1, 0, // Skip to: 998 /* 563 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 566 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 575 /* 571 */ MCD_OPC_Decode, 188, 13, 3, // Opcode: VMAXUB /* 575 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 584 /* 580 */ MCD_OPC_Decode, 190, 13, 3, // Opcode: VMAXUH /* 584 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 593 /* 589 */ MCD_OPC_Decode, 191, 13, 3, // Opcode: VMAXUW /* 593 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 602 /* 598 */ MCD_OPC_Decode, 189, 13, 3, // Opcode: VMAXUD /* 602 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 611 /* 607 */ MCD_OPC_Decode, 184, 13, 3, // Opcode: VMAXSB /* 611 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 620 /* 616 */ MCD_OPC_Decode, 186, 13, 3, // Opcode: VMAXSH /* 620 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 629 /* 625 */ MCD_OPC_Decode, 187, 13, 3, // Opcode: VMAXSW /* 629 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 638 /* 634 */ MCD_OPC_Decode, 185, 13, 3, // Opcode: VMAXSD /* 638 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 647 /* 643 */ MCD_OPC_Decode, 199, 13, 3, // Opcode: VMINUB /* 647 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 656 /* 652 */ MCD_OPC_Decode, 201, 13, 3, // Opcode: VMINUH /* 656 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 665 /* 661 */ MCD_OPC_Decode, 202, 13, 3, // Opcode: VMINUW /* 665 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 674 /* 670 */ MCD_OPC_Decode, 200, 13, 3, // Opcode: VMINUD /* 674 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 683 /* 679 */ MCD_OPC_Decode, 195, 13, 3, // Opcode: VMINSB /* 683 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 692 /* 688 */ MCD_OPC_Decode, 197, 13, 3, // Opcode: VMINSH /* 692 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 701 /* 697 */ MCD_OPC_Decode, 198, 13, 3, // Opcode: VMINSW /* 701 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 710 /* 706 */ MCD_OPC_Decode, 196, 13, 3, // Opcode: VMINSD /* 710 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 719 /* 715 */ MCD_OPC_Decode, 213, 12, 3, // Opcode: VAVGUB /* 719 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 728 /* 724 */ MCD_OPC_Decode, 214, 12, 3, // Opcode: VAVGUH /* 728 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 737 /* 733 */ MCD_OPC_Decode, 215, 12, 3, // Opcode: VAVGUW /* 737 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 746 /* 742 */ MCD_OPC_Decode, 210, 12, 3, // Opcode: VAVGSB /* 746 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 755 /* 751 */ MCD_OPC_Decode, 211, 12, 3, // Opcode: VAVGSH /* 755 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 764 /* 760 */ MCD_OPC_Decode, 212, 12, 3, // Opcode: VAVGSW /* 764 */ MCD_OPC_FilterValue, 24, 147, 0, 0, // Skip to: 916 /* 769 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 772 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 781 /* 777 */ MCD_OPC_Decode, 227, 12, 8, // Opcode: VCLZLSBB /* 781 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 790 /* 786 */ MCD_OPC_Decode, 152, 13, 8, // Opcode: VCTZLSBB /* 790 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 799 /* 795 */ MCD_OPC_Decode, 239, 13, 6, // Opcode: VNEGW /* 799 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 808 /* 804 */ MCD_OPC_Decode, 238, 13, 6, // Opcode: VNEGD /* 808 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 817 /* 813 */ MCD_OPC_Decode, 142, 14, 6, // Opcode: VPRTYBW /* 817 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 826 /* 822 */ MCD_OPC_Decode, 140, 14, 6, // Opcode: VPRTYBD /* 826 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 835 /* 831 */ MCD_OPC_Decode, 141, 14, 6, // Opcode: VPRTYBQ /* 835 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 844 /* 840 */ MCD_OPC_Decode, 162, 13, 6, // Opcode: VEXTSB2W /* 844 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 853 /* 849 */ MCD_OPC_Decode, 166, 13, 6, // Opcode: VEXTSH2W /* 853 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 862 /* 858 */ MCD_OPC_Decode, 160, 13, 6, // Opcode: VEXTSB2D /* 862 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 871 /* 867 */ MCD_OPC_Decode, 164, 13, 6, // Opcode: VEXTSH2D /* 871 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 880 /* 876 */ MCD_OPC_Decode, 168, 13, 6, // Opcode: VEXTSW2D /* 880 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 889 /* 885 */ MCD_OPC_Decode, 149, 13, 6, // Opcode: VCTZB /* 889 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 898 /* 894 */ MCD_OPC_Decode, 151, 13, 6, // Opcode: VCTZH /* 898 */ MCD_OPC_FilterValue, 30, 4, 0, 0, // Skip to: 907 /* 903 */ MCD_OPC_Decode, 153, 13, 6, // Opcode: VCTZW /* 907 */ MCD_OPC_FilterValue, 31, 162, 60, 0, // Skip to: 16434 /* 912 */ MCD_OPC_Decode, 150, 13, 6, // Opcode: VCTZD /* 916 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 925 /* 921 */ MCD_OPC_Decode, 160, 14, 9, // Opcode: VSHASIGMAW /* 925 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 934 /* 930 */ MCD_OPC_Decode, 159, 14, 9, // Opcode: VSHASIGMAD /* 934 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 950 /* 939 */ MCD_OPC_CheckField, 16, 5, 0, 128, 60, 0, // Skip to: 16434 /* 946 */ MCD_OPC_Decode, 224, 12, 6, // Opcode: VCLZB /* 950 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 966 /* 955 */ MCD_OPC_CheckField, 16, 5, 0, 112, 60, 0, // Skip to: 16434 /* 962 */ MCD_OPC_Decode, 226, 12, 6, // Opcode: VCLZH /* 966 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 982 /* 971 */ MCD_OPC_CheckField, 16, 5, 0, 96, 60, 0, // Skip to: 16434 /* 978 */ MCD_OPC_Decode, 228, 12, 6, // Opcode: VCLZW /* 982 */ MCD_OPC_FilterValue, 31, 87, 60, 0, // Skip to: 16434 /* 987 */ MCD_OPC_CheckField, 16, 5, 0, 80, 60, 0, // Skip to: 16434 /* 994 */ MCD_OPC_Decode, 225, 12, 6, // Opcode: VCLZD /* 998 */ MCD_OPC_FilterValue, 3, 94, 0, 0, // Skip to: 1097 /* 1003 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1006 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1015 /* 1011 */ MCD_OPC_Decode, 189, 12, 3, // Opcode: VABSDUB /* 1015 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1024 /* 1020 */ MCD_OPC_Decode, 190, 12, 3, // Opcode: VABSDUH /* 1024 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1033 /* 1029 */ MCD_OPC_Decode, 191, 12, 3, // Opcode: VABSDUW /* 1033 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 1049 /* 1038 */ MCD_OPC_CheckField, 16, 5, 0, 29, 60, 0, // Skip to: 16434 /* 1045 */ MCD_OPC_Decode, 136, 14, 6, // Opcode: VPOPCNTB /* 1049 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 1065 /* 1054 */ MCD_OPC_CheckField, 16, 5, 0, 13, 60, 0, // Skip to: 16434 /* 1061 */ MCD_OPC_Decode, 138, 14, 6, // Opcode: VPOPCNTH /* 1065 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 1081 /* 1070 */ MCD_OPC_CheckField, 16, 5, 0, 253, 59, 0, // Skip to: 16434 /* 1077 */ MCD_OPC_Decode, 139, 14, 6, // Opcode: VPOPCNTW /* 1081 */ MCD_OPC_FilterValue, 31, 244, 59, 0, // Skip to: 16434 /* 1086 */ MCD_OPC_CheckField, 16, 5, 0, 237, 59, 0, // Skip to: 16434 /* 1093 */ MCD_OPC_Decode, 137, 14, 6, // Opcode: VPOPCNTD /* 1097 */ MCD_OPC_FilterValue, 4, 31, 1, 0, // Skip to: 1389 /* 1102 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1105 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1114 /* 1110 */ MCD_OPC_Decode, 148, 14, 3, // Opcode: VRLB /* 1114 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1123 /* 1119 */ MCD_OPC_Decode, 152, 14, 3, // Opcode: VRLH /* 1123 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1132 /* 1128 */ MCD_OPC_Decode, 153, 14, 3, // Opcode: VRLW /* 1132 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1141 /* 1137 */ MCD_OPC_Decode, 149, 14, 3, // Opcode: VRLD /* 1141 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1150 /* 1146 */ MCD_OPC_Decode, 162, 14, 3, // Opcode: VSLB /* 1150 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1159 /* 1155 */ MCD_OPC_Decode, 165, 14, 3, // Opcode: VSLH /* 1159 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1168 /* 1164 */ MCD_OPC_Decode, 168, 14, 3, // Opcode: VSLW /* 1168 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1177 /* 1173 */ MCD_OPC_Decode, 161, 14, 3, // Opcode: VSL /* 1177 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1186 /* 1182 */ MCD_OPC_Decode, 182, 14, 3, // Opcode: VSRB /* 1186 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1195 /* 1191 */ MCD_OPC_Decode, 184, 14, 3, // Opcode: VSRH /* 1195 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1204 /* 1200 */ MCD_OPC_Decode, 187, 14, 3, // Opcode: VSRW /* 1204 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1213 /* 1209 */ MCD_OPC_Decode, 177, 14, 3, // Opcode: VSR /* 1213 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1222 /* 1218 */ MCD_OPC_Decode, 178, 14, 3, // Opcode: VSRAB /* 1222 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1231 /* 1227 */ MCD_OPC_Decode, 180, 14, 3, // Opcode: VSRAH /* 1231 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1240 /* 1236 */ MCD_OPC_Decode, 181, 14, 3, // Opcode: VSRAW /* 1240 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1249 /* 1245 */ MCD_OPC_Decode, 179, 14, 3, // Opcode: VSRAD /* 1249 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1258 /* 1254 */ MCD_OPC_Decode, 208, 12, 3, // Opcode: VAND /* 1258 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1267 /* 1263 */ MCD_OPC_Decode, 209, 12, 3, // Opcode: VANDC /* 1267 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1276 /* 1272 */ MCD_OPC_Decode, 242, 13, 3, // Opcode: VOR /* 1276 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1285 /* 1281 */ MCD_OPC_Decode, 217, 14, 3, // Opcode: VXOR /* 1285 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 1294 /* 1290 */ MCD_OPC_Decode, 241, 13, 3, // Opcode: VNOR /* 1294 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 1303 /* 1299 */ MCD_OPC_Decode, 243, 13, 3, // Opcode: VORC /* 1303 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 1312 /* 1308 */ MCD_OPC_Decode, 235, 13, 3, // Opcode: VNAND /* 1312 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 1321 /* 1317 */ MCD_OPC_Decode, 163, 14, 3, // Opcode: VSLD /* 1321 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 1337 /* 1326 */ MCD_OPC_CheckField, 11, 10, 0, 253, 58, 0, // Skip to: 16434 /* 1333 */ MCD_OPC_Decode, 180, 8, 10, // Opcode: MFVSCR /* 1337 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 1353 /* 1342 */ MCD_OPC_CheckField, 16, 10, 0, 237, 58, 0, // Skip to: 16434 /* 1349 */ MCD_OPC_Decode, 217, 8, 11, // Opcode: MTVSCR /* 1353 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 1362 /* 1358 */ MCD_OPC_Decode, 154, 13, 3, // Opcode: VEQV /* 1362 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1371 /* 1367 */ MCD_OPC_Decode, 183, 14, 3, // Opcode: VSRD /* 1371 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 1380 /* 1376 */ MCD_OPC_Decode, 186, 14, 3, // Opcode: VSRV /* 1380 */ MCD_OPC_FilterValue, 29, 201, 58, 0, // Skip to: 16434 /* 1385 */ MCD_OPC_Decode, 167, 14, 3, // Opcode: VSLV /* 1389 */ MCD_OPC_FilterValue, 5, 39, 0, 0, // Skip to: 1433 /* 1394 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1397 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1406 /* 1402 */ MCD_OPC_Decode, 154, 14, 12, // Opcode: VRLWMI /* 1406 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1415 /* 1411 */ MCD_OPC_Decode, 150, 14, 12, // Opcode: VRLDMI /* 1415 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1424 /* 1420 */ MCD_OPC_Decode, 155, 14, 3, // Opcode: VRLWNM /* 1424 */ MCD_OPC_FilterValue, 7, 157, 58, 0, // Skip to: 16434 /* 1429 */ MCD_OPC_Decode, 151, 14, 3, // Opcode: VRLDNM /* 1433 */ MCD_OPC_FilterValue, 6, 237, 0, 0, // Skip to: 1675 /* 1438 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1441 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1450 /* 1446 */ MCD_OPC_Decode, 233, 12, 3, // Opcode: VCMPEQUB /* 1450 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1459 /* 1455 */ MCD_OPC_Decode, 237, 12, 3, // Opcode: VCMPEQUH /* 1459 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1468 /* 1464 */ MCD_OPC_Decode, 239, 12, 3, // Opcode: VCMPEQUW /* 1468 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1477 /* 1473 */ MCD_OPC_Decode, 231, 12, 3, // Opcode: VCMPEQFP /* 1477 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 1486 /* 1482 */ MCD_OPC_Decode, 241, 12, 3, // Opcode: VCMPGEFP /* 1486 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1495 /* 1491 */ MCD_OPC_Decode, 253, 12, 3, // Opcode: VCMPGTUB /* 1495 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1504 /* 1500 */ MCD_OPC_Decode, 129, 13, 3, // Opcode: VCMPGTUH /* 1504 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1513 /* 1509 */ MCD_OPC_Decode, 131, 13, 3, // Opcode: VCMPGTUW /* 1513 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1522 /* 1518 */ MCD_OPC_Decode, 243, 12, 3, // Opcode: VCMPGTFP /* 1522 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1531 /* 1527 */ MCD_OPC_Decode, 245, 12, 3, // Opcode: VCMPGTSB /* 1531 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1540 /* 1536 */ MCD_OPC_Decode, 249, 12, 3, // Opcode: VCMPGTSH /* 1540 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1549 /* 1545 */ MCD_OPC_Decode, 251, 12, 3, // Opcode: VCMPGTSW /* 1549 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1558 /* 1554 */ MCD_OPC_Decode, 229, 12, 3, // Opcode: VCMPBFP /* 1558 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1567 /* 1563 */ MCD_OPC_Decode, 234, 12, 3, // Opcode: VCMPEQUBo /* 1567 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1576 /* 1572 */ MCD_OPC_Decode, 238, 12, 3, // Opcode: VCMPEQUHo /* 1576 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1585 /* 1581 */ MCD_OPC_Decode, 240, 12, 3, // Opcode: VCMPEQUWo /* 1585 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1594 /* 1590 */ MCD_OPC_Decode, 232, 12, 3, // Opcode: VCMPEQFPo /* 1594 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 1603 /* 1599 */ MCD_OPC_Decode, 242, 12, 3, // Opcode: VCMPGEFPo /* 1603 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 1612 /* 1608 */ MCD_OPC_Decode, 254, 12, 3, // Opcode: VCMPGTUBo /* 1612 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 1621 /* 1617 */ MCD_OPC_Decode, 130, 13, 3, // Opcode: VCMPGTUHo /* 1621 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 1630 /* 1626 */ MCD_OPC_Decode, 132, 13, 3, // Opcode: VCMPGTUWo /* 1630 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1639 /* 1635 */ MCD_OPC_Decode, 244, 12, 3, // Opcode: VCMPGTFPo /* 1639 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 1648 /* 1644 */ MCD_OPC_Decode, 246, 12, 3, // Opcode: VCMPGTSBo /* 1648 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 1657 /* 1653 */ MCD_OPC_Decode, 250, 12, 3, // Opcode: VCMPGTSHo /* 1657 */ MCD_OPC_FilterValue, 30, 4, 0, 0, // Skip to: 1666 /* 1662 */ MCD_OPC_Decode, 252, 12, 3, // Opcode: VCMPGTSWo /* 1666 */ MCD_OPC_FilterValue, 31, 171, 57, 0, // Skip to: 16434 /* 1671 */ MCD_OPC_Decode, 230, 12, 3, // Opcode: VCMPBFPo /* 1675 */ MCD_OPC_FilterValue, 7, 165, 0, 0, // Skip to: 1845 /* 1680 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1683 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1692 /* 1688 */ MCD_OPC_Decode, 133, 13, 3, // Opcode: VCMPNEB /* 1692 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1701 /* 1697 */ MCD_OPC_Decode, 135, 13, 3, // Opcode: VCMPNEH /* 1701 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1710 /* 1706 */ MCD_OPC_Decode, 137, 13, 3, // Opcode: VCMPNEW /* 1710 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1719 /* 1715 */ MCD_OPC_Decode, 235, 12, 3, // Opcode: VCMPEQUD /* 1719 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1728 /* 1724 */ MCD_OPC_Decode, 139, 13, 3, // Opcode: VCMPNEZB /* 1728 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1737 /* 1733 */ MCD_OPC_Decode, 141, 13, 3, // Opcode: VCMPNEZH /* 1737 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1746 /* 1742 */ MCD_OPC_Decode, 143, 13, 3, // Opcode: VCMPNEZW /* 1746 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 1755 /* 1751 */ MCD_OPC_Decode, 255, 12, 3, // Opcode: VCMPGTUD /* 1755 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 1764 /* 1760 */ MCD_OPC_Decode, 247, 12, 3, // Opcode: VCMPGTSD /* 1764 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1773 /* 1769 */ MCD_OPC_Decode, 134, 13, 3, // Opcode: VCMPNEBo /* 1773 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1782 /* 1778 */ MCD_OPC_Decode, 136, 13, 3, // Opcode: VCMPNEHo /* 1782 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1791 /* 1787 */ MCD_OPC_Decode, 138, 13, 3, // Opcode: VCMPNEWo /* 1791 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1800 /* 1796 */ MCD_OPC_Decode, 236, 12, 3, // Opcode: VCMPEQUDo /* 1800 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 1809 /* 1805 */ MCD_OPC_Decode, 140, 13, 3, // Opcode: VCMPNEZBo /* 1809 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 1818 /* 1814 */ MCD_OPC_Decode, 142, 13, 3, // Opcode: VCMPNEZHo /* 1818 */ MCD_OPC_FilterValue, 22, 4, 0, 0, // Skip to: 1827 /* 1823 */ MCD_OPC_Decode, 144, 13, 3, // Opcode: VCMPNEZWo /* 1827 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 1836 /* 1832 */ MCD_OPC_Decode, 128, 13, 3, // Opcode: VCMPGTUDo /* 1836 */ MCD_OPC_FilterValue, 31, 1, 57, 0, // Skip to: 16434 /* 1841 */ MCD_OPC_Decode, 248, 12, 3, // Opcode: VCMPGTSDo /* 1845 */ MCD_OPC_FilterValue, 8, 226, 0, 0, // Skip to: 2076 /* 1850 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1853 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 1862 /* 1858 */ MCD_OPC_Decode, 231, 13, 3, // Opcode: VMULOUB /* 1862 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 1871 /* 1867 */ MCD_OPC_Decode, 232, 13, 3, // Opcode: VMULOUH /* 1871 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 1880 /* 1876 */ MCD_OPC_Decode, 233, 13, 3, // Opcode: VMULOUW /* 1880 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 1889 /* 1885 */ MCD_OPC_Decode, 228, 13, 3, // Opcode: VMULOSB /* 1889 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 1898 /* 1894 */ MCD_OPC_Decode, 229, 13, 3, // Opcode: VMULOSH /* 1898 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 1907 /* 1903 */ MCD_OPC_Decode, 230, 13, 3, // Opcode: VMULOSW /* 1907 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 1916 /* 1912 */ MCD_OPC_Decode, 225, 13, 3, // Opcode: VMULEUB /* 1916 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 1925 /* 1921 */ MCD_OPC_Decode, 226, 13, 3, // Opcode: VMULEUH /* 1925 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 1934 /* 1930 */ MCD_OPC_Decode, 227, 13, 3, // Opcode: VMULEUW /* 1934 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 1943 /* 1939 */ MCD_OPC_Decode, 222, 13, 3, // Opcode: VMULESB /* 1943 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 1952 /* 1948 */ MCD_OPC_Decode, 223, 13, 3, // Opcode: VMULESH /* 1952 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 1961 /* 1957 */ MCD_OPC_Decode, 224, 13, 3, // Opcode: VMULESW /* 1961 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 1970 /* 1966 */ MCD_OPC_Decode, 132, 14, 3, // Opcode: VPMSUMB /* 1970 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 1979 /* 1975 */ MCD_OPC_Decode, 134, 14, 3, // Opcode: VPMSUMH /* 1979 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 1988 /* 1984 */ MCD_OPC_Decode, 135, 14, 3, // Opcode: VPMSUMW /* 1988 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 1997 /* 1993 */ MCD_OPC_Decode, 133, 14, 3, // Opcode: VPMSUMD /* 1997 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 2006 /* 2002 */ MCD_OPC_Decode, 222, 12, 3, // Opcode: VCIPHER /* 2006 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 2015 /* 2011 */ MCD_OPC_Decode, 236, 13, 3, // Opcode: VNCIPHER /* 2015 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 2031 /* 2020 */ MCD_OPC_CheckField, 11, 5, 0, 71, 56, 0, // Skip to: 16434 /* 2027 */ MCD_OPC_Decode, 157, 14, 4, // Opcode: VSBOX /* 2031 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 2040 /* 2036 */ MCD_OPC_Decode, 207, 14, 3, // Opcode: VSUM4UBS /* 2040 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 2049 /* 2045 */ MCD_OPC_Decode, 206, 14, 3, // Opcode: VSUM4SHS /* 2049 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 2058 /* 2054 */ MCD_OPC_Decode, 204, 14, 3, // Opcode: VSUM2SWS /* 2058 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 2067 /* 2063 */ MCD_OPC_Decode, 205, 14, 3, // Opcode: VSUM4SBS /* 2067 */ MCD_OPC_FilterValue, 30, 26, 56, 0, // Skip to: 16434 /* 2072 */ MCD_OPC_Decode, 208, 14, 3, // Opcode: VSUMSWS /* 2076 */ MCD_OPC_FilterValue, 9, 30, 0, 0, // Skip to: 2111 /* 2081 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 2084 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2093 /* 2089 */ MCD_OPC_Decode, 234, 13, 3, // Opcode: VMULUWM /* 2093 */ MCD_OPC_FilterValue, 20, 4, 0, 0, // Skip to: 2102 /* 2098 */ MCD_OPC_Decode, 223, 12, 3, // Opcode: VCIPHERLAST /* 2102 */ MCD_OPC_FilterValue, 21, 247, 55, 0, // Skip to: 16434 /* 2107 */ MCD_OPC_Decode, 237, 13, 3, // Opcode: VNCIPHERLAST /* 2111 */ MCD_OPC_FilterValue, 10, 203, 0, 0, // Skip to: 2319 /* 2116 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 2119 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2128 /* 2124 */ MCD_OPC_Decode, 196, 12, 3, // Opcode: VADDFP /* 2128 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2137 /* 2133 */ MCD_OPC_Decode, 192, 14, 3, // Opcode: VSUBFP /* 2137 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 2153 /* 2142 */ MCD_OPC_CheckField, 16, 5, 0, 205, 55, 0, // Skip to: 16434 /* 2149 */ MCD_OPC_Decode, 143, 14, 6, // Opcode: VREFP /* 2153 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 2169 /* 2158 */ MCD_OPC_CheckField, 16, 5, 0, 189, 55, 0, // Skip to: 16434 /* 2165 */ MCD_OPC_Decode, 156, 14, 6, // Opcode: VRSQRTEFP /* 2169 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 2185 /* 2174 */ MCD_OPC_CheckField, 16, 5, 0, 173, 55, 0, // Skip to: 16434 /* 2181 */ MCD_OPC_Decode, 155, 13, 6, // Opcode: VEXPTEFP /* 2185 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 2201 /* 2190 */ MCD_OPC_CheckField, 16, 5, 0, 157, 55, 0, // Skip to: 16434 /* 2197 */ MCD_OPC_Decode, 181, 13, 6, // Opcode: VLOGEFP /* 2201 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 2217 /* 2206 */ MCD_OPC_CheckField, 16, 5, 0, 141, 55, 0, // Skip to: 16434 /* 2213 */ MCD_OPC_Decode, 145, 14, 6, // Opcode: VRFIN /* 2217 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2233 /* 2222 */ MCD_OPC_CheckField, 16, 5, 0, 125, 55, 0, // Skip to: 16434 /* 2229 */ MCD_OPC_Decode, 147, 14, 6, // Opcode: VRFIZ /* 2233 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 2249 /* 2238 */ MCD_OPC_CheckField, 16, 5, 0, 109, 55, 0, // Skip to: 16434 /* 2245 */ MCD_OPC_Decode, 146, 14, 6, // Opcode: VRFIP /* 2249 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2265 /* 2254 */ MCD_OPC_CheckField, 16, 5, 0, 93, 55, 0, // Skip to: 16434 /* 2261 */ MCD_OPC_Decode, 144, 14, 6, // Opcode: VRFIM /* 2265 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2274 /* 2270 */ MCD_OPC_Decode, 220, 12, 13, // Opcode: VCFUX /* 2274 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2283 /* 2279 */ MCD_OPC_Decode, 218, 12, 13, // Opcode: VCFSX /* 2283 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 2292 /* 2288 */ MCD_OPC_Decode, 147, 13, 13, // Opcode: VCTUXS /* 2292 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 2301 /* 2297 */ MCD_OPC_Decode, 145, 13, 13, // Opcode: VCTSXS /* 2301 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 2310 /* 2306 */ MCD_OPC_Decode, 183, 13, 3, // Opcode: VMAXFP /* 2310 */ MCD_OPC_FilterValue, 17, 39, 55, 0, // Skip to: 16434 /* 2315 */ MCD_OPC_Decode, 194, 13, 3, // Opcode: VMINFP /* 2319 */ MCD_OPC_FilterValue, 12, 202, 0, 0, // Skip to: 2526 /* 2324 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 2327 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2336 /* 2332 */ MCD_OPC_Decode, 205, 13, 3, // Opcode: VMRGHB /* 2336 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2345 /* 2341 */ MCD_OPC_Decode, 206, 13, 3, // Opcode: VMRGHH /* 2345 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2354 /* 2350 */ MCD_OPC_Decode, 207, 13, 3, // Opcode: VMRGHW /* 2354 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2363 /* 2359 */ MCD_OPC_Decode, 208, 13, 3, // Opcode: VMRGLB /* 2363 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2372 /* 2368 */ MCD_OPC_Decode, 209, 13, 3, // Opcode: VMRGLH /* 2372 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2381 /* 2377 */ MCD_OPC_Decode, 210, 13, 3, // Opcode: VMRGLW /* 2381 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2390 /* 2386 */ MCD_OPC_Decode, 169, 14, 13, // Opcode: VSPLTB /* 2390 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2399 /* 2395 */ MCD_OPC_Decode, 171, 14, 13, // Opcode: VSPLTH /* 2399 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2408 /* 2404 */ MCD_OPC_Decode, 176, 14, 13, // Opcode: VSPLTW /* 2408 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 2424 /* 2413 */ MCD_OPC_CheckField, 11, 5, 0, 190, 54, 0, // Skip to: 16434 /* 2420 */ MCD_OPC_Decode, 173, 14, 14, // Opcode: VSPLTISB /* 2424 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2440 /* 2429 */ MCD_OPC_CheckField, 11, 5, 0, 174, 54, 0, // Skip to: 16434 /* 2436 */ MCD_OPC_Decode, 174, 14, 14, // Opcode: VSPLTISH /* 2440 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 2456 /* 2445 */ MCD_OPC_CheckField, 11, 5, 0, 158, 54, 0, // Skip to: 16434 /* 2452 */ MCD_OPC_Decode, 175, 14, 14, // Opcode: VSPLTISW /* 2456 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 2465 /* 2461 */ MCD_OPC_Decode, 166, 14, 3, // Opcode: VSLO /* 2465 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 2474 /* 2470 */ MCD_OPC_Decode, 185, 14, 3, // Opcode: VSRO /* 2474 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 2490 /* 2479 */ MCD_OPC_CheckField, 16, 5, 0, 124, 54, 0, // Skip to: 16434 /* 2486 */ MCD_OPC_Decode, 176, 13, 6, // Opcode: VGBBD /* 2490 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 2499 /* 2495 */ MCD_OPC_Decode, 217, 12, 3, // Opcode: VBPERMQ /* 2499 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 2508 /* 2504 */ MCD_OPC_Decode, 216, 12, 3, // Opcode: VBPERMD /* 2508 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 2517 /* 2513 */ MCD_OPC_Decode, 211, 13, 3, // Opcode: VMRGOW /* 2517 */ MCD_OPC_FilterValue, 30, 88, 54, 0, // Skip to: 16434 /* 2522 */ MCD_OPC_Decode, 204, 13, 3, // Opcode: VMRGEW /* 2526 */ MCD_OPC_FilterValue, 13, 129, 0, 0, // Skip to: 2660 /* 2531 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 2534 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 2543 /* 2539 */ MCD_OPC_Decode, 157, 13, 15, // Opcode: VEXTRACTUB /* 2543 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 2552 /* 2548 */ MCD_OPC_Decode, 158, 13, 15, // Opcode: VEXTRACTUH /* 2552 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 2561 /* 2557 */ MCD_OPC_Decode, 159, 13, 15, // Opcode: VEXTRACTUW /* 2561 */ MCD_OPC_FilterValue, 11, 4, 0, 0, // Skip to: 2570 /* 2566 */ MCD_OPC_Decode, 156, 13, 15, // Opcode: VEXTRACTD /* 2570 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2579 /* 2575 */ MCD_OPC_Decode, 177, 13, 16, // Opcode: VINSERTB /* 2579 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 2588 /* 2584 */ MCD_OPC_Decode, 179, 13, 16, // Opcode: VINSERTH /* 2588 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 2597 /* 2593 */ MCD_OPC_Decode, 180, 13, 15, // Opcode: VINSERTW /* 2597 */ MCD_OPC_FilterValue, 15, 4, 0, 0, // Skip to: 2606 /* 2602 */ MCD_OPC_Decode, 178, 13, 15, // Opcode: VINSERTD /* 2606 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 2615 /* 2611 */ MCD_OPC_Decode, 170, 13, 17, // Opcode: VEXTUBLX /* 2615 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 2624 /* 2620 */ MCD_OPC_Decode, 172, 13, 17, // Opcode: VEXTUHLX /* 2624 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 2633 /* 2629 */ MCD_OPC_Decode, 174, 13, 17, // Opcode: VEXTUWLX /* 2633 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 2642 /* 2638 */ MCD_OPC_Decode, 171, 13, 17, // Opcode: VEXTUBRX /* 2642 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 2651 /* 2647 */ MCD_OPC_Decode, 173, 13, 17, // Opcode: VEXTUHRX /* 2651 */ MCD_OPC_FilterValue, 30, 210, 53, 0, // Skip to: 16434 /* 2656 */ MCD_OPC_Decode, 175, 13, 17, // Opcode: VEXTUWRX /* 2660 */ MCD_OPC_FilterValue, 14, 248, 0, 0, // Skip to: 2913 /* 2665 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 2668 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2677 /* 2673 */ MCD_OPC_Decode, 128, 14, 3, // Opcode: VPKUHUM /* 2677 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 2686 /* 2682 */ MCD_OPC_Decode, 130, 14, 3, // Opcode: VPKUWUM /* 2686 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 2695 /* 2691 */ MCD_OPC_Decode, 129, 14, 3, // Opcode: VPKUHUS /* 2695 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 2704 /* 2700 */ MCD_OPC_Decode, 131, 14, 3, // Opcode: VPKUWUS /* 2704 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 2713 /* 2709 */ MCD_OPC_Decode, 251, 13, 3, // Opcode: VPKSHUS /* 2713 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 2722 /* 2718 */ MCD_OPC_Decode, 253, 13, 3, // Opcode: VPKSWUS /* 2722 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 2731 /* 2727 */ MCD_OPC_Decode, 250, 13, 3, // Opcode: VPKSHSS /* 2731 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 2740 /* 2736 */ MCD_OPC_Decode, 252, 13, 3, // Opcode: VPKSWSS /* 2740 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 2756 /* 2745 */ MCD_OPC_CheckField, 16, 5, 0, 114, 53, 0, // Skip to: 16434 /* 2752 */ MCD_OPC_Decode, 210, 14, 6, // Opcode: VUPKHSB /* 2756 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 2772 /* 2761 */ MCD_OPC_CheckField, 16, 5, 0, 98, 53, 0, // Skip to: 16434 /* 2768 */ MCD_OPC_Decode, 211, 14, 6, // Opcode: VUPKHSH /* 2772 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 2788 /* 2777 */ MCD_OPC_CheckField, 16, 5, 0, 82, 53, 0, // Skip to: 16434 /* 2784 */ MCD_OPC_Decode, 214, 14, 6, // Opcode: VUPKLSB /* 2788 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 2804 /* 2793 */ MCD_OPC_CheckField, 16, 5, 0, 66, 53, 0, // Skip to: 16434 /* 2800 */ MCD_OPC_Decode, 215, 14, 6, // Opcode: VUPKLSH /* 2804 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 2813 /* 2809 */ MCD_OPC_Decode, 247, 13, 3, // Opcode: VPKPX /* 2813 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 2829 /* 2818 */ MCD_OPC_CheckField, 16, 5, 0, 41, 53, 0, // Skip to: 16434 /* 2825 */ MCD_OPC_Decode, 209, 14, 6, // Opcode: VUPKHPX /* 2829 */ MCD_OPC_FilterValue, 15, 11, 0, 0, // Skip to: 2845 /* 2834 */ MCD_OPC_CheckField, 16, 5, 0, 25, 53, 0, // Skip to: 16434 /* 2841 */ MCD_OPC_Decode, 213, 14, 6, // Opcode: VUPKLPX /* 2845 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 2854 /* 2850 */ MCD_OPC_Decode, 254, 13, 3, // Opcode: VPKUDUM /* 2854 */ MCD_OPC_FilterValue, 19, 4, 0, 0, // Skip to: 2863 /* 2859 */ MCD_OPC_Decode, 255, 13, 3, // Opcode: VPKUDUS /* 2863 */ MCD_OPC_FilterValue, 21, 4, 0, 0, // Skip to: 2872 /* 2868 */ MCD_OPC_Decode, 249, 13, 3, // Opcode: VPKSDUS /* 2872 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 2881 /* 2877 */ MCD_OPC_Decode, 248, 13, 3, // Opcode: VPKSDSS /* 2881 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 2897 /* 2886 */ MCD_OPC_CheckField, 16, 5, 0, 229, 52, 0, // Skip to: 16434 /* 2893 */ MCD_OPC_Decode, 212, 14, 6, // Opcode: VUPKHSW /* 2897 */ MCD_OPC_FilterValue, 27, 220, 52, 0, // Skip to: 16434 /* 2902 */ MCD_OPC_CheckField, 16, 5, 0, 213, 52, 0, // Skip to: 16434 /* 2909 */ MCD_OPC_Decode, 216, 14, 6, // Opcode: VUPKLSW /* 2913 */ MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 2922 /* 2918 */ MCD_OPC_Decode, 192, 13, 18, // Opcode: VMHADDSHS /* 2922 */ MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 2931 /* 2927 */ MCD_OPC_Decode, 193, 13, 18, // Opcode: VMHRADDSHS /* 2931 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 2940 /* 2936 */ MCD_OPC_Decode, 203, 13, 18, // Opcode: VMLADDUHM /* 2940 */ MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 2949 /* 2945 */ MCD_OPC_Decode, 215, 13, 18, // Opcode: VMSUMUBM /* 2949 */ MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 2958 /* 2954 */ MCD_OPC_Decode, 212, 13, 18, // Opcode: VMSUMMBM /* 2958 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 2967 /* 2963 */ MCD_OPC_Decode, 216, 13, 18, // Opcode: VMSUMUHM /* 2967 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 2976 /* 2972 */ MCD_OPC_Decode, 217, 13, 18, // Opcode: VMSUMUHS /* 2976 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 2985 /* 2981 */ MCD_OPC_Decode, 213, 13, 18, // Opcode: VMSUMSHM /* 2985 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 2994 /* 2990 */ MCD_OPC_Decode, 214, 13, 18, // Opcode: VMSUMSHS /* 2994 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 3003 /* 2999 */ MCD_OPC_Decode, 158, 14, 18, // Opcode: VSEL /* 3003 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 3012 /* 3008 */ MCD_OPC_Decode, 244, 13, 18, // Opcode: VPERM /* 3012 */ MCD_OPC_FilterValue, 44, 11, 0, 0, // Skip to: 3028 /* 3017 */ MCD_OPC_CheckField, 10, 1, 0, 98, 52, 0, // Skip to: 16434 /* 3024 */ MCD_OPC_Decode, 164, 14, 19, // Opcode: VSLDOI /* 3028 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 3037 /* 3033 */ MCD_OPC_Decode, 246, 13, 18, // Opcode: VPERMXOR /* 3037 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 3046 /* 3042 */ MCD_OPC_Decode, 182, 13, 20, // Opcode: VMADDFP /* 3046 */ MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 3055 /* 3051 */ MCD_OPC_Decode, 240, 13, 20, // Opcode: VNMSUBFP /* 3055 */ MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 3064 /* 3060 */ MCD_OPC_Decode, 144, 8, 21, // Opcode: MADDHD /* 3064 */ MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 3073 /* 3069 */ MCD_OPC_Decode, 145, 8, 21, // Opcode: MADDHDU /* 3073 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 3082 /* 3078 */ MCD_OPC_Decode, 146, 8, 21, // Opcode: MADDLD /* 3082 */ MCD_OPC_FilterValue, 59, 4, 0, 0, // Skip to: 3091 /* 3087 */ MCD_OPC_Decode, 245, 13, 18, // Opcode: VPERMR /* 3091 */ MCD_OPC_FilterValue, 60, 4, 0, 0, // Skip to: 3100 /* 3096 */ MCD_OPC_Decode, 195, 12, 18, // Opcode: VADDEUQM /* 3100 */ MCD_OPC_FilterValue, 61, 4, 0, 0, // Skip to: 3109 /* 3105 */ MCD_OPC_Decode, 194, 12, 18, // Opcode: VADDECUQ /* 3109 */ MCD_OPC_FilterValue, 62, 4, 0, 0, // Skip to: 3118 /* 3114 */ MCD_OPC_Decode, 191, 14, 18, // Opcode: VSUBEUQM /* 3118 */ MCD_OPC_FilterValue, 63, 255, 51, 0, // Skip to: 16434 /* 3123 */ MCD_OPC_Decode, 190, 14, 18, // Opcode: VSUBECUQ /* 3127 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 3136 /* 3132 */ MCD_OPC_Decode, 233, 8, 22, // Opcode: MULLI /* 3136 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 3145 /* 3141 */ MCD_OPC_Decode, 132, 12, 22, // Opcode: SUBFIC /* 3145 */ MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 3171 /* 3150 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 3153 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3162 /* 3158 */ MCD_OPC_Decode, 173, 3, 23, // Opcode: CMPLWI /* 3162 */ MCD_OPC_FilterValue, 1, 211, 51, 0, // Skip to: 16434 /* 3167 */ MCD_OPC_Decode, 171, 3, 24, // Opcode: CMPLDI /* 3171 */ MCD_OPC_FilterValue, 11, 21, 0, 0, // Skip to: 3197 /* 3176 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 3179 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3188 /* 3184 */ MCD_OPC_Decode, 177, 3, 25, // Opcode: CMPWI /* 3188 */ MCD_OPC_FilterValue, 1, 185, 51, 0, // Skip to: 16434 /* 3193 */ MCD_OPC_Decode, 168, 3, 26, // Opcode: CMPDI /* 3197 */ MCD_OPC_FilterValue, 12, 4, 0, 0, // Skip to: 3206 /* 3202 */ MCD_OPC_Decode, 220, 1, 22, // Opcode: ADDIC /* 3206 */ MCD_OPC_FilterValue, 13, 4, 0, 0, // Skip to: 3215 /* 3211 */ MCD_OPC_Decode, 222, 1, 22, // Opcode: ADDICo /* 3215 */ MCD_OPC_FilterValue, 14, 15, 0, 0, // Skip to: 3235 /* 3220 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, 0, // Skip to: 3231 /* 3227 */ MCD_OPC_Decode, 217, 7, 27, // Opcode: LI /* 3231 */ MCD_OPC_Decode, 218, 1, 28, // Opcode: ADDI /* 3235 */ MCD_OPC_FilterValue, 15, 15, 0, 0, // Skip to: 3255 /* 3240 */ MCD_OPC_CheckField, 16, 5, 0, 4, 0, 0, // Skip to: 3251 /* 3247 */ MCD_OPC_Decode, 219, 7, 27, // Opcode: LIS /* 3251 */ MCD_OPC_Decode, 223, 1, 28, // Opcode: ADDIS /* 3255 */ MCD_OPC_FilterValue, 16, 35, 1, 0, // Skip to: 3551 /* 3260 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 3263 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 3335 /* 3268 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 3271 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3281 /* 3277 */ MCD_OPC_Decode, 237, 2, 29, // Opcode: BDNZ /* 3281 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3291 /* 3287 */ MCD_OPC_Decode, 129, 3, 29, // Opcode: BDZ /* 3291 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3301 /* 3297 */ MCD_OPC_Decode, 255, 2, 29, // Opcode: BDNZm /* 3301 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3311 /* 3307 */ MCD_OPC_Decode, 128, 3, 29, // Opcode: BDNZp /* 3311 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3321 /* 3317 */ MCD_OPC_Decode, 147, 3, 29, // Opcode: BDZm /* 3321 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3331 /* 3327 */ MCD_OPC_Decode, 148, 3, 29, // Opcode: BDZp /* 3331 */ MCD_OPC_Decode, 223, 16, 30, // Opcode: gBC /* 3335 */ MCD_OPC_FilterValue, 1, 67, 0, 0, // Skip to: 3407 /* 3340 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 3343 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3353 /* 3349 */ MCD_OPC_Decode, 242, 2, 29, // Opcode: BDNZL /* 3353 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3363 /* 3359 */ MCD_OPC_Decode, 134, 3, 29, // Opcode: BDZL /* 3363 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3373 /* 3369 */ MCD_OPC_Decode, 253, 2, 29, // Opcode: BDNZLm /* 3373 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3383 /* 3379 */ MCD_OPC_Decode, 254, 2, 29, // Opcode: BDNZLp /* 3383 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3393 /* 3389 */ MCD_OPC_Decode, 145, 3, 29, // Opcode: BDZLm /* 3393 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3403 /* 3399 */ MCD_OPC_Decode, 146, 3, 29, // Opcode: BDZLp /* 3403 */ MCD_OPC_Decode, 228, 16, 30, // Opcode: gBCL /* 3407 */ MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 3479 /* 3412 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 3415 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3425 /* 3421 */ MCD_OPC_Decode, 239, 2, 29, // Opcode: BDNZA /* 3425 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3435 /* 3431 */ MCD_OPC_Decode, 131, 3, 29, // Opcode: BDZA /* 3435 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3445 /* 3441 */ MCD_OPC_Decode, 240, 2, 29, // Opcode: BDNZAm /* 3445 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3455 /* 3451 */ MCD_OPC_Decode, 241, 2, 29, // Opcode: BDNZAp /* 3455 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3465 /* 3461 */ MCD_OPC_Decode, 132, 3, 29, // Opcode: BDZAm /* 3465 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3475 /* 3471 */ MCD_OPC_Decode, 133, 3, 29, // Opcode: BDZAp /* 3475 */ MCD_OPC_Decode, 224, 16, 30, // Opcode: gBCA /* 3479 */ MCD_OPC_FilterValue, 3, 150, 50, 0, // Skip to: 16434 /* 3484 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 3487 */ MCD_OPC_FilterValue, 128, 4, 4, 0, 0, // Skip to: 3497 /* 3493 */ MCD_OPC_Decode, 243, 2, 29, // Opcode: BDNZLA /* 3497 */ MCD_OPC_FilterValue, 192, 4, 4, 0, 0, // Skip to: 3507 /* 3503 */ MCD_OPC_Decode, 135, 3, 29, // Opcode: BDZLA /* 3507 */ MCD_OPC_FilterValue, 128, 6, 4, 0, 0, // Skip to: 3517 /* 3513 */ MCD_OPC_Decode, 244, 2, 29, // Opcode: BDNZLAm /* 3517 */ MCD_OPC_FilterValue, 160, 6, 4, 0, 0, // Skip to: 3527 /* 3523 */ MCD_OPC_Decode, 245, 2, 29, // Opcode: BDNZLAp /* 3527 */ MCD_OPC_FilterValue, 192, 6, 4, 0, 0, // Skip to: 3537 /* 3533 */ MCD_OPC_Decode, 136, 3, 29, // Opcode: BDZLAm /* 3537 */ MCD_OPC_FilterValue, 224, 6, 4, 0, 0, // Skip to: 3547 /* 3543 */ MCD_OPC_Decode, 137, 3, 29, // Opcode: BDZLAp /* 3547 */ MCD_OPC_Decode, 229, 16, 30, // Opcode: gBCLA /* 3551 */ MCD_OPC_FilterValue, 17, 11, 0, 0, // Skip to: 3567 /* 3556 */ MCD_OPC_CheckField, 1, 1, 1, 71, 50, 0, // Skip to: 16434 /* 3563 */ MCD_OPC_Decode, 222, 10, 31, // Opcode: SC /* 3567 */ MCD_OPC_FilterValue, 18, 39, 0, 0, // Skip to: 3611 /* 3572 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 3575 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3584 /* 3580 */ MCD_OPC_Decode, 190, 2, 32, // Opcode: B /* 3584 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 3593 /* 3589 */ MCD_OPC_Decode, 149, 3, 32, // Opcode: BL /* 3593 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3602 /* 3598 */ MCD_OPC_Decode, 191, 2, 32, // Opcode: BA /* 3602 */ MCD_OPC_FilterValue, 3, 27, 50, 0, // Skip to: 16434 /* 3607 */ MCD_OPC_Decode, 155, 3, 32, // Opcode: BLA /* 3611 */ MCD_OPC_FilterValue, 19, 22, 3, 0, // Skip to: 4406 /* 3616 */ MCD_OPC_ExtractField, 1, 5, // Inst{5-1} ... /* 3619 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 3649 /* 3624 */ MCD_OPC_CheckField, 21, 2, 0, 3, 50, 0, // Skip to: 16434 /* 3631 */ MCD_OPC_CheckField, 6, 12, 0, 252, 49, 0, // Skip to: 16434 /* 3638 */ MCD_OPC_CheckField, 0, 1, 0, 245, 49, 0, // Skip to: 16434 /* 3645 */ MCD_OPC_Decode, 148, 8, 33, // Opcode: MCRF /* 3649 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 3785 /* 3654 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 3657 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 3673 /* 3662 */ MCD_OPC_CheckField, 0, 1, 0, 221, 49, 0, // Skip to: 16434 /* 3669 */ MCD_OPC_Decode, 203, 3, 34, // Opcode: CRNOR /* 3673 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 3689 /* 3678 */ MCD_OPC_CheckField, 0, 1, 0, 205, 49, 0, // Skip to: 16434 /* 3685 */ MCD_OPC_Decode, 200, 3, 34, // Opcode: CRANDC /* 3689 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 3705 /* 3694 */ MCD_OPC_CheckField, 0, 1, 0, 189, 49, 0, // Skip to: 16434 /* 3701 */ MCD_OPC_Decode, 208, 3, 34, // Opcode: CRXOR /* 3705 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 3721 /* 3710 */ MCD_OPC_CheckField, 0, 1, 0, 173, 49, 0, // Skip to: 16434 /* 3717 */ MCD_OPC_Decode, 202, 3, 34, // Opcode: CRNAND /* 3721 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 3737 /* 3726 */ MCD_OPC_CheckField, 0, 1, 0, 157, 49, 0, // Skip to: 16434 /* 3733 */ MCD_OPC_Decode, 199, 3, 34, // Opcode: CRAND /* 3737 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3753 /* 3742 */ MCD_OPC_CheckField, 0, 1, 0, 141, 49, 0, // Skip to: 16434 /* 3749 */ MCD_OPC_Decode, 201, 3, 34, // Opcode: CREQV /* 3753 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 3769 /* 3758 */ MCD_OPC_CheckField, 0, 1, 0, 125, 49, 0, // Skip to: 16434 /* 3765 */ MCD_OPC_Decode, 205, 3, 34, // Opcode: CRORC /* 3769 */ MCD_OPC_FilterValue, 14, 116, 49, 0, // Skip to: 16434 /* 3774 */ MCD_OPC_CheckField, 0, 1, 0, 109, 49, 0, // Skip to: 16434 /* 3781 */ MCD_OPC_Decode, 204, 3, 34, // Opcode: CROR /* 3785 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3794 /* 3790 */ MCD_OPC_Decode, 246, 1, 35, // Opcode: ADDPCIS /* 3794 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 3817 /* 3799 */ MCD_OPC_CheckField, 6, 20, 1, 84, 49, 0, // Skip to: 16434 /* 3806 */ MCD_OPC_CheckField, 0, 1, 0, 77, 49, 0, // Skip to: 16434 /* 3813 */ MCD_OPC_Decode, 192, 10, 0, // Opcode: RFMCI /* 3817 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 3840 /* 3822 */ MCD_OPC_CheckField, 6, 20, 1, 61, 49, 0, // Skip to: 16434 /* 3829 */ MCD_OPC_CheckField, 0, 1, 0, 54, 49, 0, // Skip to: 16434 /* 3836 */ MCD_OPC_Decode, 188, 10, 0, // Opcode: RFDI /* 3840 */ MCD_OPC_FilterValue, 16, 113, 1, 0, // Skip to: 4214 /* 3845 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 3848 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 4031 /* 3853 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 3856 */ MCD_OPC_FilterValue, 0, 134, 0, 0, // Skip to: 3995 /* 3861 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 3864 */ MCD_OPC_FilterValue, 0, 21, 49, 0, // Skip to: 16434 /* 3869 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 3872 */ MCD_OPC_FilterValue, 128, 4, 11, 0, 0, // Skip to: 3889 /* 3878 */ MCD_OPC_CheckField, 11, 2, 0, 106, 0, 0, // Skip to: 3991 /* 3885 */ MCD_OPC_Decode, 246, 2, 0, // Opcode: BDNZLR /* 3889 */ MCD_OPC_FilterValue, 192, 4, 11, 0, 0, // Skip to: 3906 /* 3895 */ MCD_OPC_CheckField, 11, 2, 0, 89, 0, 0, // Skip to: 3991 /* 3902 */ MCD_OPC_Decode, 138, 3, 0, // Opcode: BDZLR /* 3906 */ MCD_OPC_FilterValue, 128, 5, 11, 0, 0, // Skip to: 3923 /* 3912 */ MCD_OPC_CheckField, 11, 2, 0, 72, 0, 0, // Skip to: 3991 /* 3919 */ MCD_OPC_Decode, 158, 3, 0, // Opcode: BLR /* 3923 */ MCD_OPC_FilterValue, 128, 6, 11, 0, 0, // Skip to: 3940 /* 3929 */ MCD_OPC_CheckField, 11, 2, 0, 55, 0, 0, // Skip to: 3991 /* 3936 */ MCD_OPC_Decode, 251, 2, 0, // Opcode: BDNZLRm /* 3940 */ MCD_OPC_FilterValue, 160, 6, 11, 0, 0, // Skip to: 3957 /* 3946 */ MCD_OPC_CheckField, 11, 2, 0, 38, 0, 0, // Skip to: 3991 /* 3953 */ MCD_OPC_Decode, 252, 2, 0, // Opcode: BDNZLRp /* 3957 */ MCD_OPC_FilterValue, 192, 6, 11, 0, 0, // Skip to: 3974 /* 3963 */ MCD_OPC_CheckField, 11, 2, 0, 21, 0, 0, // Skip to: 3991 /* 3970 */ MCD_OPC_Decode, 143, 3, 0, // Opcode: BDZLRm /* 3974 */ MCD_OPC_FilterValue, 224, 6, 11, 0, 0, // Skip to: 3991 /* 3980 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 3991 /* 3987 */ MCD_OPC_Decode, 144, 3, 0, // Opcode: BDZLRp /* 3991 */ MCD_OPC_Decode, 231, 16, 36, // Opcode: gBCLR /* 3995 */ MCD_OPC_FilterValue, 16, 146, 48, 0, // Skip to: 16434 /* 4000 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 4003 */ MCD_OPC_FilterValue, 0, 138, 48, 0, // Skip to: 16434 /* 4008 */ MCD_OPC_CheckField, 16, 10, 128, 5, 11, 0, 0, // Skip to: 4027 /* 4016 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4027 /* 4023 */ MCD_OPC_Decode, 231, 2, 0, // Opcode: BCTR /* 4027 */ MCD_OPC_Decode, 226, 16, 36, // Opcode: gBCCTR /* 4031 */ MCD_OPC_FilterValue, 1, 110, 48, 0, // Skip to: 16434 /* 4036 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 4039 */ MCD_OPC_FilterValue, 0, 134, 0, 0, // Skip to: 4178 /* 4044 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 4047 */ MCD_OPC_FilterValue, 0, 94, 48, 0, // Skip to: 16434 /* 4052 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... /* 4055 */ MCD_OPC_FilterValue, 128, 4, 11, 0, 0, // Skip to: 4072 /* 4061 */ MCD_OPC_CheckField, 11, 2, 0, 106, 0, 0, // Skip to: 4174 /* 4068 */ MCD_OPC_Decode, 248, 2, 0, // Opcode: BDNZLRL /* 4072 */ MCD_OPC_FilterValue, 192, 4, 11, 0, 0, // Skip to: 4089 /* 4078 */ MCD_OPC_CheckField, 11, 2, 0, 89, 0, 0, // Skip to: 4174 /* 4085 */ MCD_OPC_Decode, 140, 3, 0, // Opcode: BDZLRL /* 4089 */ MCD_OPC_FilterValue, 128, 5, 11, 0, 0, // Skip to: 4106 /* 4095 */ MCD_OPC_CheckField, 11, 2, 0, 72, 0, 0, // Skip to: 4174 /* 4102 */ MCD_OPC_Decode, 160, 3, 0, // Opcode: BLRL /* 4106 */ MCD_OPC_FilterValue, 128, 6, 11, 0, 0, // Skip to: 4123 /* 4112 */ MCD_OPC_CheckField, 11, 2, 0, 55, 0, 0, // Skip to: 4174 /* 4119 */ MCD_OPC_Decode, 249, 2, 0, // Opcode: BDNZLRLm /* 4123 */ MCD_OPC_FilterValue, 160, 6, 11, 0, 0, // Skip to: 4140 /* 4129 */ MCD_OPC_CheckField, 11, 2, 0, 38, 0, 0, // Skip to: 4174 /* 4136 */ MCD_OPC_Decode, 250, 2, 0, // Opcode: BDNZLRLp /* 4140 */ MCD_OPC_FilterValue, 192, 6, 11, 0, 0, // Skip to: 4157 /* 4146 */ MCD_OPC_CheckField, 11, 2, 0, 21, 0, 0, // Skip to: 4174 /* 4153 */ MCD_OPC_Decode, 141, 3, 0, // Opcode: BDZLRLm /* 4157 */ MCD_OPC_FilterValue, 224, 6, 11, 0, 0, // Skip to: 4174 /* 4163 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4174 /* 4170 */ MCD_OPC_Decode, 142, 3, 0, // Opcode: BDZLRLp /* 4174 */ MCD_OPC_Decode, 232, 16, 36, // Opcode: gBCLRL /* 4178 */ MCD_OPC_FilterValue, 16, 219, 47, 0, // Skip to: 16434 /* 4183 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 4186 */ MCD_OPC_FilterValue, 0, 211, 47, 0, // Skip to: 16434 /* 4191 */ MCD_OPC_CheckField, 16, 10, 128, 5, 11, 0, 0, // Skip to: 4210 /* 4199 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4210 /* 4206 */ MCD_OPC_Decode, 233, 2, 0, // Opcode: BCTRL /* 4210 */ MCD_OPC_Decode, 227, 16, 36, // Opcode: gBCCTRL /* 4214 */ MCD_OPC_FilterValue, 18, 141, 0, 0, // Skip to: 4360 /* 4219 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 4222 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 4245 /* 4227 */ MCD_OPC_CheckField, 11, 15, 0, 168, 47, 0, // Skip to: 16434 /* 4234 */ MCD_OPC_CheckField, 0, 1, 0, 161, 47, 0, // Skip to: 16434 /* 4241 */ MCD_OPC_Decode, 191, 10, 0, // Opcode: RFID /* 4245 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 4268 /* 4250 */ MCD_OPC_CheckField, 11, 15, 0, 145, 47, 0, // Skip to: 16434 /* 4257 */ MCD_OPC_CheckField, 0, 1, 0, 138, 47, 0, // Skip to: 16434 /* 4264 */ MCD_OPC_Decode, 190, 10, 0, // Opcode: RFI /* 4268 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 4291 /* 4273 */ MCD_OPC_CheckField, 12, 14, 0, 122, 47, 0, // Skip to: 16434 /* 4280 */ MCD_OPC_CheckField, 0, 1, 0, 115, 47, 0, // Skip to: 16434 /* 4287 */ MCD_OPC_Decode, 189, 10, 37, // Opcode: RFEBB /* 4291 */ MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 4314 /* 4296 */ MCD_OPC_CheckField, 11, 15, 0, 99, 47, 0, // Skip to: 16434 /* 4303 */ MCD_OPC_CheckField, 0, 1, 0, 92, 47, 0, // Skip to: 16434 /* 4310 */ MCD_OPC_Decode, 135, 7, 0, // Opcode: HRFID /* 4314 */ MCD_OPC_FilterValue, 11, 18, 0, 0, // Skip to: 4337 /* 4319 */ MCD_OPC_CheckField, 11, 15, 0, 76, 47, 0, // Skip to: 16434 /* 4326 */ MCD_OPC_CheckField, 0, 1, 0, 69, 47, 0, // Skip to: 16434 /* 4333 */ MCD_OPC_Decode, 209, 11, 0, // Opcode: STOP /* 4337 */ MCD_OPC_FilterValue, 13, 60, 47, 0, // Skip to: 16434 /* 4342 */ MCD_OPC_CheckField, 11, 15, 0, 53, 47, 0, // Skip to: 16434 /* 4349 */ MCD_OPC_CheckField, 0, 1, 0, 46, 47, 0, // Skip to: 16434 /* 4356 */ MCD_OPC_Decode, 244, 8, 0, // Opcode: NAP /* 4360 */ MCD_OPC_FilterValue, 19, 18, 0, 0, // Skip to: 4383 /* 4365 */ MCD_OPC_CheckField, 6, 20, 1, 30, 47, 0, // Skip to: 16434 /* 4372 */ MCD_OPC_CheckField, 0, 1, 0, 23, 47, 0, // Skip to: 16434 /* 4379 */ MCD_OPC_Decode, 187, 10, 0, // Opcode: RFCI /* 4383 */ MCD_OPC_FilterValue, 22, 14, 47, 0, // Skip to: 16434 /* 4388 */ MCD_OPC_CheckField, 6, 20, 4, 7, 47, 0, // Skip to: 16434 /* 4395 */ MCD_OPC_CheckField, 0, 1, 0, 0, 47, 0, // Skip to: 16434 /* 4402 */ MCD_OPC_Decode, 145, 7, 0, // Opcode: ISYNC /* 4406 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 4432 /* 4411 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4414 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4423 /* 4419 */ MCD_OPC_Decode, 209, 10, 38, // Opcode: RLWIMI /* 4423 */ MCD_OPC_FilterValue, 1, 230, 46, 0, // Skip to: 16434 /* 4428 */ MCD_OPC_Decode, 212, 10, 38, // Opcode: RLWIMIo /* 4432 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 4458 /* 4437 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4440 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4449 /* 4445 */ MCD_OPC_Decode, 213, 10, 39, // Opcode: RLWINM /* 4449 */ MCD_OPC_FilterValue, 1, 204, 46, 0, // Skip to: 16434 /* 4454 */ MCD_OPC_Decode, 216, 10, 39, // Opcode: RLWINMo /* 4458 */ MCD_OPC_FilterValue, 23, 21, 0, 0, // Skip to: 4484 /* 4463 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4466 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4475 /* 4471 */ MCD_OPC_Decode, 217, 10, 40, // Opcode: RLWNM /* 4475 */ MCD_OPC_FilterValue, 1, 178, 46, 0, // Skip to: 16434 /* 4480 */ MCD_OPC_Decode, 220, 10, 40, // Opcode: RLWNMo /* 4484 */ MCD_OPC_FilterValue, 24, 15, 0, 0, // Skip to: 4504 /* 4489 */ MCD_OPC_CheckField, 0, 26, 0, 4, 0, 0, // Skip to: 4500 /* 4496 */ MCD_OPC_Decode, 249, 8, 0, // Opcode: NOP /* 4500 */ MCD_OPC_Decode, 135, 9, 41, // Opcode: ORI /* 4504 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 4513 /* 4509 */ MCD_OPC_Decode, 137, 9, 41, // Opcode: ORIS /* 4513 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 4522 /* 4518 */ MCD_OPC_Decode, 230, 14, 41, // Opcode: XORI /* 4522 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 4531 /* 4527 */ MCD_OPC_Decode, 232, 14, 41, // Opcode: XORIS /* 4531 */ MCD_OPC_FilterValue, 28, 4, 0, 0, // Skip to: 4540 /* 4536 */ MCD_OPC_Decode, 134, 2, 41, // Opcode: ANDIo /* 4540 */ MCD_OPC_FilterValue, 29, 4, 0, 0, // Skip to: 4549 /* 4545 */ MCD_OPC_Decode, 132, 2, 41, // Opcode: ANDISo /* 4549 */ MCD_OPC_FilterValue, 30, 151, 0, 0, // Skip to: 4705 /* 4554 */ MCD_OPC_ExtractField, 2, 3, // Inst{4-2} ... /* 4557 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4583 /* 4562 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4565 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4574 /* 4570 */ MCD_OPC_Decode, 198, 10, 42, // Opcode: RLDICL /* 4574 */ MCD_OPC_FilterValue, 1, 79, 46, 0, // Skip to: 16434 /* 4579 */ MCD_OPC_Decode, 202, 10, 42, // Opcode: RLDICLo /* 4583 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 4609 /* 4588 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4591 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4600 /* 4596 */ MCD_OPC_Decode, 203, 10, 42, // Opcode: RLDICR /* 4600 */ MCD_OPC_FilterValue, 1, 53, 46, 0, // Skip to: 16434 /* 4605 */ MCD_OPC_Decode, 205, 10, 42, // Opcode: RLDICRo /* 4609 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 4635 /* 4614 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4617 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4626 /* 4622 */ MCD_OPC_Decode, 197, 10, 42, // Opcode: RLDIC /* 4626 */ MCD_OPC_FilterValue, 1, 27, 46, 0, // Skip to: 16434 /* 4631 */ MCD_OPC_Decode, 206, 10, 42, // Opcode: RLDICo /* 4635 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 4661 /* 4640 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 4643 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4652 /* 4648 */ MCD_OPC_Decode, 207, 10, 43, // Opcode: RLDIMI /* 4652 */ MCD_OPC_FilterValue, 1, 1, 46, 0, // Skip to: 16434 /* 4657 */ MCD_OPC_Decode, 208, 10, 43, // Opcode: RLDIMIo /* 4661 */ MCD_OPC_FilterValue, 4, 248, 45, 0, // Skip to: 16434 /* 4666 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 4669 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 4678 /* 4674 */ MCD_OPC_Decode, 193, 10, 44, // Opcode: RLDCL /* 4678 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 4687 /* 4683 */ MCD_OPC_Decode, 194, 10, 44, // Opcode: RLDCLo /* 4687 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 4696 /* 4692 */ MCD_OPC_Decode, 195, 10, 44, // Opcode: RLDCR /* 4696 */ MCD_OPC_FilterValue, 3, 213, 45, 0, // Skip to: 16434 /* 4701 */ MCD_OPC_Decode, 196, 10, 44, // Opcode: RLDCRo /* 4705 */ MCD_OPC_FilterValue, 31, 64, 21, 0, // Skip to: 10150 /* 4710 */ MCD_OPC_ExtractField, 2, 4, // Inst{5-2} ... /* 4713 */ MCD_OPC_FilterValue, 0, 175, 0, 0, // Skip to: 4893 /* 4718 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 4721 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4761 /* 4726 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 4729 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4745 /* 4734 */ MCD_OPC_CheckField, 0, 2, 0, 173, 45, 0, // Skip to: 16434 /* 4741 */ MCD_OPC_Decode, 176, 3, 45, // Opcode: CMPW /* 4745 */ MCD_OPC_FilterValue, 1, 164, 45, 0, // Skip to: 16434 /* 4750 */ MCD_OPC_CheckField, 0, 2, 0, 157, 45, 0, // Skip to: 16434 /* 4757 */ MCD_OPC_Decode, 167, 3, 46, // Opcode: CMPD /* 4761 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 4801 /* 4766 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... /* 4769 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 4785 /* 4774 */ MCD_OPC_CheckField, 0, 2, 0, 133, 45, 0, // Skip to: 16434 /* 4781 */ MCD_OPC_Decode, 172, 3, 45, // Opcode: CMPLW /* 4785 */ MCD_OPC_FilterValue, 1, 124, 45, 0, // Skip to: 16434 /* 4790 */ MCD_OPC_CheckField, 0, 2, 0, 117, 45, 0, // Skip to: 16434 /* 4797 */ MCD_OPC_Decode, 170, 3, 46, // Opcode: CMPLD /* 4801 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 4824 /* 4806 */ MCD_OPC_CheckField, 11, 7, 0, 101, 45, 0, // Skip to: 16434 /* 4813 */ MCD_OPC_CheckField, 0, 2, 0, 94, 45, 0, // Skip to: 16434 /* 4820 */ MCD_OPC_Decode, 251, 10, 47, // Opcode: SETB /* 4824 */ MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 4847 /* 4829 */ MCD_OPC_CheckField, 22, 1, 0, 78, 45, 0, // Skip to: 16434 /* 4836 */ MCD_OPC_CheckField, 0, 2, 0, 71, 45, 0, // Skip to: 16434 /* 4843 */ MCD_OPC_Decode, 174, 3, 48, // Opcode: CMPRB /* 4847 */ MCD_OPC_FilterValue, 7, 18, 0, 0, // Skip to: 4870 /* 4852 */ MCD_OPC_CheckField, 21, 2, 0, 55, 45, 0, // Skip to: 16434 /* 4859 */ MCD_OPC_CheckField, 0, 2, 0, 48, 45, 0, // Skip to: 16434 /* 4866 */ MCD_OPC_Decode, 169, 3, 49, // Opcode: CMPEQB /* 4870 */ MCD_OPC_FilterValue, 18, 39, 45, 0, // Skip to: 16434 /* 4875 */ MCD_OPC_CheckField, 11, 12, 0, 32, 45, 0, // Skip to: 16434 /* 4882 */ MCD_OPC_CheckField, 0, 2, 0, 25, 45, 0, // Skip to: 16434 /* 4889 */ MCD_OPC_Decode, 150, 8, 50, // Opcode: MCRXRX /* 4893 */ MCD_OPC_FilterValue, 1, 74, 0, 0, // Skip to: 4972 /* 4898 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 4901 */ MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 4924 /* 4906 */ MCD_OPC_CheckField, 16, 1, 0, 1, 45, 0, // Skip to: 16434 /* 4913 */ MCD_OPC_CheckField, 1, 1, 1, 250, 44, 0, // Skip to: 16434 /* 4920 */ MCD_OPC_Decode, 225, 14, 51, // Opcode: WRTEE /* 4924 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 4940 /* 4929 */ MCD_OPC_CheckField, 1, 1, 1, 234, 44, 0, // Skip to: 16434 /* 4936 */ MCD_OPC_Decode, 226, 14, 52, // Opcode: WRTEEI /* 4940 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 4956 /* 4945 */ MCD_OPC_CheckField, 0, 2, 2, 218, 44, 0, // Skip to: 16434 /* 4952 */ MCD_OPC_Decode, 156, 8, 53, // Opcode: MFDCR /* 4956 */ MCD_OPC_FilterValue, 14, 209, 44, 0, // Skip to: 16434 /* 4961 */ MCD_OPC_CheckField, 0, 2, 2, 202, 44, 0, // Skip to: 16434 /* 4968 */ MCD_OPC_Decode, 196, 8, 53, // Opcode: MTDCR /* 4972 */ MCD_OPC_FilterValue, 2, 49, 0, 0, // Skip to: 5026 /* 4977 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 4980 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 5010 /* 4985 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 4988 */ MCD_OPC_FilterValue, 0, 177, 44, 0, // Skip to: 16434 /* 4993 */ MCD_OPC_CheckField, 11, 15, 128, 248, 1, 4, 0, 0, // Skip to: 5006 /* 5002 */ MCD_OPC_Decode, 181, 12, 0, // Opcode: TRAP /* 5006 */ MCD_OPC_Decode, 185, 12, 54, // Opcode: TW /* 5010 */ MCD_OPC_FilterValue, 2, 155, 44, 0, // Skip to: 16434 /* 5015 */ MCD_OPC_CheckField, 0, 2, 0, 148, 44, 0, // Skip to: 16434 /* 5022 */ MCD_OPC_Decode, 164, 12, 55, // Opcode: TD /* 5026 */ MCD_OPC_FilterValue, 3, 174, 1, 0, // Skip to: 5461 /* 5031 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 5034 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 5060 /* 5039 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5042 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5051 /* 5047 */ MCD_OPC_Decode, 226, 7, 56, // Opcode: LVSL /* 5051 */ MCD_OPC_FilterValue, 2, 114, 44, 0, // Skip to: 16434 /* 5056 */ MCD_OPC_Decode, 223, 7, 56, // Opcode: LVEBX /* 5060 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5086 /* 5065 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5068 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5077 /* 5073 */ MCD_OPC_Decode, 227, 7, 56, // Opcode: LVSR /* 5077 */ MCD_OPC_FilterValue, 2, 88, 44, 0, // Skip to: 16434 /* 5082 */ MCD_OPC_Decode, 224, 7, 56, // Opcode: LVEHX /* 5086 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 5102 /* 5091 */ MCD_OPC_CheckField, 0, 2, 2, 72, 44, 0, // Skip to: 16434 /* 5098 */ MCD_OPC_Decode, 225, 7, 56, // Opcode: LVEWX /* 5102 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 5118 /* 5107 */ MCD_OPC_CheckField, 0, 2, 2, 56, 44, 0, // Skip to: 16434 /* 5114 */ MCD_OPC_Decode, 228, 7, 56, // Opcode: LVX /* 5118 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 5134 /* 5123 */ MCD_OPC_CheckField, 0, 2, 2, 40, 44, 0, // Skip to: 16434 /* 5130 */ MCD_OPC_Decode, 211, 11, 56, // Opcode: STVEBX /* 5134 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 5150 /* 5139 */ MCD_OPC_CheckField, 0, 2, 2, 24, 44, 0, // Skip to: 16434 /* 5146 */ MCD_OPC_Decode, 212, 11, 56, // Opcode: STVEHX /* 5150 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 5183 /* 5155 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5158 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5174 /* 5163 */ MCD_OPC_CheckField, 25, 1, 0, 0, 44, 0, // Skip to: 16434 /* 5170 */ MCD_OPC_Decode, 139, 7, 57, // Opcode: ICBLQ /* 5174 */ MCD_OPC_FilterValue, 2, 247, 43, 0, // Skip to: 16434 /* 5179 */ MCD_OPC_Decode, 213, 11, 56, // Opcode: STVEWX /* 5183 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 5216 /* 5188 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5191 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5207 /* 5196 */ MCD_OPC_CheckField, 25, 1, 0, 223, 43, 0, // Skip to: 16434 /* 5203 */ MCD_OPC_Decode, 138, 7, 57, // Opcode: ICBLC /* 5207 */ MCD_OPC_FilterValue, 2, 214, 43, 0, // Skip to: 16434 /* 5212 */ MCD_OPC_Decode, 214, 11, 56, // Opcode: STVX /* 5216 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 5232 /* 5221 */ MCD_OPC_CheckField, 0, 2, 2, 198, 43, 0, // Skip to: 16434 /* 5228 */ MCD_OPC_Decode, 229, 7, 56, // Opcode: LVXL /* 5232 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 5255 /* 5237 */ MCD_OPC_CheckField, 21, 5, 0, 182, 43, 0, // Skip to: 16434 /* 5244 */ MCD_OPC_CheckField, 0, 2, 0, 175, 43, 0, // Skip to: 16434 /* 5251 */ MCD_OPC_Decode, 225, 3, 58, // Opcode: DCCCI /* 5255 */ MCD_OPC_FilterValue, 15, 28, 0, 0, // Skip to: 5288 /* 5260 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5263 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5279 /* 5268 */ MCD_OPC_CheckField, 25, 1, 0, 151, 43, 0, // Skip to: 16434 /* 5275 */ MCD_OPC_Decode, 141, 7, 57, // Opcode: ICBTLS /* 5279 */ MCD_OPC_FilterValue, 2, 142, 43, 0, // Skip to: 16434 /* 5284 */ MCD_OPC_Decode, 215, 11, 56, // Opcode: STVXL /* 5288 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 5304 /* 5293 */ MCD_OPC_CheckField, 0, 2, 0, 126, 43, 0, // Skip to: 16434 /* 5300 */ MCD_OPC_Decode, 233, 7, 59, // Opcode: LWAT /* 5304 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 5320 /* 5309 */ MCD_OPC_CheckField, 0, 2, 0, 110, 43, 0, // Skip to: 16434 /* 5316 */ MCD_OPC_Decode, 165, 7, 60, // Opcode: LDAT /* 5320 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 5336 /* 5325 */ MCD_OPC_CheckField, 0, 2, 0, 94, 43, 0, // Skip to: 16434 /* 5332 */ MCD_OPC_Decode, 218, 11, 59, // Opcode: STWAT /* 5336 */ MCD_OPC_FilterValue, 23, 11, 0, 0, // Skip to: 5352 /* 5341 */ MCD_OPC_CheckField, 0, 2, 0, 78, 43, 0, // Skip to: 16434 /* 5348 */ MCD_OPC_Decode, 174, 11, 60, // Opcode: STDAT /* 5352 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 5375 /* 5357 */ MCD_OPC_CheckField, 22, 4, 0, 62, 43, 0, // Skip to: 16434 /* 5364 */ MCD_OPC_CheckField, 0, 2, 0, 55, 43, 0, // Skip to: 16434 /* 5371 */ MCD_OPC_Decode, 191, 3, 61, // Opcode: CP_COPY /* 5375 */ MCD_OPC_FilterValue, 26, 18, 0, 0, // Skip to: 5398 /* 5380 */ MCD_OPC_CheckField, 11, 15, 0, 39, 43, 0, // Skip to: 16434 /* 5387 */ MCD_OPC_CheckField, 0, 2, 0, 32, 43, 0, // Skip to: 16434 /* 5394 */ MCD_OPC_Decode, 190, 3, 0, // Opcode: CP_ABORT /* 5398 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 5438 /* 5403 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5406 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5422 /* 5411 */ MCD_OPC_CheckField, 22, 4, 0, 8, 43, 0, // Skip to: 16434 /* 5418 */ MCD_OPC_Decode, 193, 3, 61, // Opcode: CP_PASTE /* 5422 */ MCD_OPC_FilterValue, 1, 255, 42, 0, // Skip to: 16434 /* 5427 */ MCD_OPC_CheckField, 22, 4, 0, 248, 42, 0, // Skip to: 16434 /* 5434 */ MCD_OPC_Decode, 196, 3, 61, // Opcode: CP_PASTEo /* 5438 */ MCD_OPC_FilterValue, 30, 239, 42, 0, // Skip to: 16434 /* 5443 */ MCD_OPC_CheckField, 21, 5, 0, 232, 42, 0, // Skip to: 16434 /* 5450 */ MCD_OPC_CheckField, 0, 2, 0, 225, 42, 0, // Skip to: 16434 /* 5457 */ MCD_OPC_Decode, 142, 7, 58, // Opcode: ICCCI /* 5461 */ MCD_OPC_FilterValue, 4, 143, 1, 0, // Skip to: 5865 /* 5466 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 5469 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5513 /* 5474 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5477 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5486 /* 5482 */ MCD_OPC_Decode, 252, 11, 62, // Opcode: SUBFC /* 5486 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 5495 /* 5491 */ MCD_OPC_Decode, 255, 11, 62, // Opcode: SUBFCo /* 5495 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5504 /* 5500 */ MCD_OPC_Decode, 224, 8, 63, // Opcode: MULHDU /* 5504 */ MCD_OPC_FilterValue, 3, 173, 42, 0, // Skip to: 16434 /* 5509 */ MCD_OPC_Decode, 225, 8, 63, // Opcode: MULHDUo /* 5513 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 5539 /* 5518 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5521 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5530 /* 5526 */ MCD_OPC_Decode, 249, 11, 62, // Opcode: SUBF /* 5530 */ MCD_OPC_FilterValue, 1, 147, 42, 0, // Skip to: 16434 /* 5535 */ MCD_OPC_Decode, 142, 12, 62, // Opcode: SUBFo /* 5539 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5565 /* 5544 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5547 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5556 /* 5552 */ MCD_OPC_Decode, 223, 8, 63, // Opcode: MULHD /* 5556 */ MCD_OPC_FilterValue, 3, 121, 42, 0, // Skip to: 16434 /* 5561 */ MCD_OPC_Decode, 226, 8, 63, // Opcode: MULHDo /* 5565 */ MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 5605 /* 5570 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5573 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5589 /* 5578 */ MCD_OPC_CheckField, 11, 5, 0, 97, 42, 0, // Skip to: 16434 /* 5585 */ MCD_OPC_Decode, 245, 8, 64, // Opcode: NEG /* 5589 */ MCD_OPC_FilterValue, 1, 88, 42, 0, // Skip to: 16434 /* 5594 */ MCD_OPC_CheckField, 11, 5, 0, 81, 42, 0, // Skip to: 16434 /* 5601 */ MCD_OPC_Decode, 248, 8, 64, // Opcode: NEGo /* 5605 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5631 /* 5610 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5613 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5622 /* 5618 */ MCD_OPC_Decode, 128, 12, 62, // Opcode: SUBFE /* 5622 */ MCD_OPC_FilterValue, 1, 55, 42, 0, // Skip to: 16434 /* 5627 */ MCD_OPC_Decode, 131, 12, 62, // Opcode: SUBFEo /* 5631 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 5671 /* 5636 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5639 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5655 /* 5644 */ MCD_OPC_CheckField, 11, 5, 0, 31, 42, 0, // Skip to: 16434 /* 5651 */ MCD_OPC_Decode, 138, 12, 64, // Opcode: SUBFZE /* 5655 */ MCD_OPC_FilterValue, 1, 22, 42, 0, // Skip to: 16434 /* 5660 */ MCD_OPC_CheckField, 11, 5, 0, 15, 42, 0, // Skip to: 16434 /* 5667 */ MCD_OPC_Decode, 141, 12, 64, // Opcode: SUBFZEo /* 5671 */ MCD_OPC_FilterValue, 7, 53, 0, 0, // Skip to: 5729 /* 5676 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5679 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5695 /* 5684 */ MCD_OPC_CheckField, 11, 5, 0, 247, 41, 0, // Skip to: 16434 /* 5691 */ MCD_OPC_Decode, 134, 12, 64, // Opcode: SUBFME /* 5695 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 5711 /* 5700 */ MCD_OPC_CheckField, 11, 5, 0, 231, 41, 0, // Skip to: 16434 /* 5707 */ MCD_OPC_Decode, 137, 12, 64, // Opcode: SUBFMEo /* 5711 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5720 /* 5716 */ MCD_OPC_Decode, 231, 8, 63, // Opcode: MULLD /* 5720 */ MCD_OPC_FilterValue, 3, 213, 41, 0, // Skip to: 16434 /* 5725 */ MCD_OPC_Decode, 232, 8, 63, // Opcode: MULLDo /* 5729 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 5745 /* 5734 */ MCD_OPC_CheckField, 0, 2, 2, 197, 41, 0, // Skip to: 16434 /* 5741 */ MCD_OPC_Decode, 186, 8, 63, // Opcode: MODUD /* 5745 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 5771 /* 5750 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5753 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5762 /* 5758 */ MCD_OPC_Decode, 228, 3, 63, // Opcode: DIVDEU /* 5762 */ MCD_OPC_FilterValue, 3, 171, 41, 0, // Skip to: 16434 /* 5767 */ MCD_OPC_Decode, 229, 3, 63, // Opcode: DIVDEUo /* 5771 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 5797 /* 5776 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5779 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5788 /* 5784 */ MCD_OPC_Decode, 227, 3, 63, // Opcode: DIVDE /* 5788 */ MCD_OPC_FilterValue, 3, 145, 41, 0, // Skip to: 16434 /* 5793 */ MCD_OPC_Decode, 230, 3, 63, // Opcode: DIVDEo /* 5797 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 5823 /* 5802 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5805 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5814 /* 5810 */ MCD_OPC_Decode, 231, 3, 63, // Opcode: DIVDU /* 5814 */ MCD_OPC_FilterValue, 3, 119, 41, 0, // Skip to: 16434 /* 5819 */ MCD_OPC_Decode, 232, 3, 63, // Opcode: DIVDUo /* 5823 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 5849 /* 5828 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5831 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5840 /* 5836 */ MCD_OPC_Decode, 226, 3, 63, // Opcode: DIVD /* 5840 */ MCD_OPC_FilterValue, 3, 93, 41, 0, // Skip to: 16434 /* 5845 */ MCD_OPC_Decode, 233, 3, 63, // Opcode: DIVDo /* 5849 */ MCD_OPC_FilterValue, 24, 84, 41, 0, // Skip to: 16434 /* 5854 */ MCD_OPC_CheckField, 0, 2, 2, 77, 41, 0, // Skip to: 16434 /* 5861 */ MCD_OPC_Decode, 184, 8, 63, // Opcode: MODSD /* 5865 */ MCD_OPC_FilterValue, 5, 96, 1, 0, // Skip to: 6222 /* 5870 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 5873 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5917 /* 5878 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5881 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5890 /* 5886 */ MCD_OPC_Decode, 210, 1, 62, // Opcode: ADDC /* 5890 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 5899 /* 5895 */ MCD_OPC_Decode, 213, 1, 62, // Opcode: ADDCo /* 5899 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5908 /* 5904 */ MCD_OPC_Decode, 228, 8, 62, // Opcode: MULHWU /* 5908 */ MCD_OPC_FilterValue, 3, 25, 41, 0, // Skip to: 16434 /* 5913 */ MCD_OPC_Decode, 229, 8, 62, // Opcode: MULHWUo /* 5917 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 5943 /* 5922 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5925 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 5934 /* 5930 */ MCD_OPC_Decode, 227, 8, 62, // Opcode: MULHW /* 5934 */ MCD_OPC_FilterValue, 3, 255, 40, 0, // Skip to: 16434 /* 5939 */ MCD_OPC_Decode, 230, 8, 62, // Opcode: MULHWo /* 5943 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 5969 /* 5948 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5951 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 5960 /* 5956 */ MCD_OPC_Decode, 214, 1, 62, // Opcode: ADDE /* 5960 */ MCD_OPC_FilterValue, 1, 229, 40, 0, // Skip to: 16434 /* 5965 */ MCD_OPC_Decode, 217, 1, 62, // Opcode: ADDEo /* 5969 */ MCD_OPC_FilterValue, 6, 35, 0, 0, // Skip to: 6009 /* 5974 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 5977 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 5993 /* 5982 */ MCD_OPC_CheckField, 11, 5, 0, 205, 40, 0, // Skip to: 16434 /* 5989 */ MCD_OPC_Decode, 247, 1, 64, // Opcode: ADDZE /* 5993 */ MCD_OPC_FilterValue, 1, 196, 40, 0, // Skip to: 16434 /* 5998 */ MCD_OPC_CheckField, 11, 5, 0, 189, 40, 0, // Skip to: 16434 /* 6005 */ MCD_OPC_Decode, 250, 1, 64, // Opcode: ADDZEo /* 6009 */ MCD_OPC_FilterValue, 7, 53, 0, 0, // Skip to: 6067 /* 6014 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6017 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6033 /* 6022 */ MCD_OPC_CheckField, 11, 5, 0, 165, 40, 0, // Skip to: 16434 /* 6029 */ MCD_OPC_Decode, 242, 1, 64, // Opcode: ADDME /* 6033 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 6049 /* 6038 */ MCD_OPC_CheckField, 11, 5, 0, 149, 40, 0, // Skip to: 16434 /* 6045 */ MCD_OPC_Decode, 245, 1, 64, // Opcode: ADDMEo /* 6049 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6058 /* 6054 */ MCD_OPC_Decode, 235, 8, 62, // Opcode: MULLW /* 6058 */ MCD_OPC_FilterValue, 3, 131, 40, 0, // Skip to: 16434 /* 6063 */ MCD_OPC_Decode, 236, 8, 62, // Opcode: MULLWo /* 6067 */ MCD_OPC_FilterValue, 8, 30, 0, 0, // Skip to: 6102 /* 6072 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6075 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6084 /* 6080 */ MCD_OPC_Decode, 203, 1, 62, // Opcode: ADD4 /* 6084 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 6093 /* 6089 */ MCD_OPC_Decode, 205, 1, 62, // Opcode: ADD4o /* 6093 */ MCD_OPC_FilterValue, 2, 96, 40, 0, // Skip to: 16434 /* 6098 */ MCD_OPC_Decode, 187, 8, 62, // Opcode: MODUW /* 6102 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 6128 /* 6107 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6110 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6119 /* 6115 */ MCD_OPC_Decode, 236, 3, 62, // Opcode: DIVWEU /* 6119 */ MCD_OPC_FilterValue, 3, 70, 40, 0, // Skip to: 16434 /* 6124 */ MCD_OPC_Decode, 237, 3, 62, // Opcode: DIVWEUo /* 6128 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 6154 /* 6133 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6136 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6145 /* 6141 */ MCD_OPC_Decode, 235, 3, 62, // Opcode: DIVWE /* 6145 */ MCD_OPC_FilterValue, 3, 44, 40, 0, // Skip to: 16434 /* 6150 */ MCD_OPC_Decode, 238, 3, 62, // Opcode: DIVWEo /* 6154 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 6180 /* 6159 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6162 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6171 /* 6167 */ MCD_OPC_Decode, 239, 3, 62, // Opcode: DIVWU /* 6171 */ MCD_OPC_FilterValue, 3, 18, 40, 0, // Skip to: 16434 /* 6176 */ MCD_OPC_Decode, 240, 3, 62, // Opcode: DIVWUo /* 6180 */ MCD_OPC_FilterValue, 15, 21, 0, 0, // Skip to: 6206 /* 6185 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6188 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 6197 /* 6193 */ MCD_OPC_Decode, 234, 3, 62, // Opcode: DIVW /* 6197 */ MCD_OPC_FilterValue, 3, 248, 39, 0, // Skip to: 16434 /* 6202 */ MCD_OPC_Decode, 241, 3, 62, // Opcode: DIVWo /* 6206 */ MCD_OPC_FilterValue, 24, 239, 39, 0, // Skip to: 16434 /* 6211 */ MCD_OPC_CheckField, 0, 2, 2, 232, 39, 0, // Skip to: 16434 /* 6218 */ MCD_OPC_Decode, 185, 8, 62, // Opcode: MODSW /* 6222 */ MCD_OPC_FilterValue, 6, 143, 1, 0, // Skip to: 6626 /* 6227 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 6230 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 6246 /* 6235 */ MCD_OPC_CheckField, 1, 1, 0, 208, 39, 0, // Skip to: 16434 /* 6242 */ MCD_OPC_Decode, 131, 8, 65, // Opcode: LXSIWZX /* 6246 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 6262 /* 6251 */ MCD_OPC_CheckField, 1, 1, 0, 192, 39, 0, // Skip to: 16434 /* 6258 */ MCD_OPC_Decode, 130, 8, 65, // Opcode: LXSIWAX /* 6262 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 6278 /* 6267 */ MCD_OPC_CheckField, 1, 1, 0, 176, 39, 0, // Skip to: 16434 /* 6274 */ MCD_OPC_Decode, 238, 11, 65, // Opcode: STXSIWX /* 6278 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 6304 /* 6283 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 6286 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6295 /* 6291 */ MCD_OPC_Decode, 143, 8, 66, // Opcode: LXVX /* 6295 */ MCD_OPC_FilterValue, 1, 150, 39, 0, // Skip to: 16434 /* 6300 */ MCD_OPC_Decode, 139, 8, 67, // Opcode: LXVL /* 6304 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 6320 /* 6309 */ MCD_OPC_CheckField, 1, 1, 1, 134, 39, 0, // Skip to: 16434 /* 6316 */ MCD_OPC_Decode, 140, 8, 67, // Opcode: LXVLL /* 6320 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 6336 /* 6325 */ MCD_OPC_CheckField, 1, 1, 0, 118, 39, 0, // Skip to: 16434 /* 6332 */ MCD_OPC_Decode, 137, 8, 66, // Opcode: LXVDSX /* 6336 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 6352 /* 6341 */ MCD_OPC_CheckField, 1, 1, 0, 102, 39, 0, // Skip to: 16434 /* 6348 */ MCD_OPC_Decode, 142, 8, 66, // Opcode: LXVWSX /* 6352 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 6378 /* 6357 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 6360 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6369 /* 6365 */ MCD_OPC_Decode, 248, 11, 66, // Opcode: STXVX /* 6369 */ MCD_OPC_FilterValue, 1, 76, 39, 0, // Skip to: 16434 /* 6374 */ MCD_OPC_Decode, 245, 11, 67, // Opcode: STXVL /* 6378 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 6394 /* 6383 */ MCD_OPC_CheckField, 1, 1, 1, 60, 39, 0, // Skip to: 16434 /* 6390 */ MCD_OPC_Decode, 246, 11, 67, // Opcode: STXVLL /* 6394 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 6410 /* 6399 */ MCD_OPC_CheckField, 1, 1, 0, 44, 39, 0, // Skip to: 16434 /* 6406 */ MCD_OPC_Decode, 133, 8, 68, // Opcode: LXSSPX /* 6410 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 6426 /* 6415 */ MCD_OPC_CheckField, 1, 1, 0, 28, 39, 0, // Skip to: 16434 /* 6422 */ MCD_OPC_Decode, 255, 7, 65, // Opcode: LXSDX /* 6426 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 6442 /* 6431 */ MCD_OPC_CheckField, 1, 1, 0, 12, 39, 0, // Skip to: 16434 /* 6438 */ MCD_OPC_Decode, 240, 11, 68, // Opcode: STXSSPX /* 6442 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 6458 /* 6447 */ MCD_OPC_CheckField, 1, 1, 0, 252, 38, 0, // Skip to: 16434 /* 6454 */ MCD_OPC_Decode, 233, 11, 65, // Opcode: STXSDX /* 6458 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 6484 /* 6463 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 6466 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6475 /* 6471 */ MCD_OPC_Decode, 141, 8, 66, // Opcode: LXVW4X /* 6475 */ MCD_OPC_FilterValue, 1, 226, 38, 0, // Skip to: 16434 /* 6480 */ MCD_OPC_Decode, 128, 8, 65, // Opcode: LXSIBZX /* 6484 */ MCD_OPC_FilterValue, 25, 21, 0, 0, // Skip to: 6510 /* 6489 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 6492 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6501 /* 6497 */ MCD_OPC_Decode, 138, 8, 66, // Opcode: LXVH8X /* 6501 */ MCD_OPC_FilterValue, 1, 200, 38, 0, // Skip to: 16434 /* 6506 */ MCD_OPC_Decode, 129, 8, 65, // Opcode: LXSIHZX /* 6510 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 6526 /* 6515 */ MCD_OPC_CheckField, 1, 1, 0, 184, 38, 0, // Skip to: 16434 /* 6522 */ MCD_OPC_Decode, 136, 8, 66, // Opcode: LXVD2X /* 6526 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 6542 /* 6531 */ MCD_OPC_CheckField, 1, 1, 0, 168, 38, 0, // Skip to: 16434 /* 6538 */ MCD_OPC_Decode, 135, 8, 66, // Opcode: LXVB16X /* 6542 */ MCD_OPC_FilterValue, 28, 21, 0, 0, // Skip to: 6568 /* 6547 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 6550 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6559 /* 6555 */ MCD_OPC_Decode, 247, 11, 66, // Opcode: STXVW4X /* 6559 */ MCD_OPC_FilterValue, 1, 142, 38, 0, // Skip to: 16434 /* 6564 */ MCD_OPC_Decode, 234, 11, 65, // Opcode: STXSIBX /* 6568 */ MCD_OPC_FilterValue, 29, 21, 0, 0, // Skip to: 6594 /* 6573 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 6576 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 6585 /* 6581 */ MCD_OPC_Decode, 244, 11, 66, // Opcode: STXVH8X /* 6585 */ MCD_OPC_FilterValue, 1, 116, 38, 0, // Skip to: 16434 /* 6590 */ MCD_OPC_Decode, 236, 11, 65, // Opcode: STXSIHX /* 6594 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 6610 /* 6599 */ MCD_OPC_CheckField, 1, 1, 0, 100, 38, 0, // Skip to: 16434 /* 6606 */ MCD_OPC_Decode, 243, 11, 66, // Opcode: STXVD2X /* 6610 */ MCD_OPC_FilterValue, 31, 91, 38, 0, // Skip to: 16434 /* 6615 */ MCD_OPC_CheckField, 1, 1, 0, 84, 38, 0, // Skip to: 16434 /* 6622 */ MCD_OPC_Decode, 242, 11, 66, // Opcode: STXVB16X /* 6626 */ MCD_OPC_FilterValue, 7, 247, 0, 0, // Skip to: 6878 /* 6631 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 6634 */ MCD_OPC_FilterValue, 0, 62, 0, 0, // Skip to: 6701 /* 6639 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 6642 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 6651 /* 6647 */ MCD_OPC_Decode, 151, 8, 69, // Opcode: MFBHRBE /* 6651 */ MCD_OPC_FilterValue, 10, 4, 0, 0, // Skip to: 6660 /* 6656 */ MCD_OPC_Decode, 170, 8, 53, // Opcode: MFPMR /* 6660 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 6676 /* 6665 */ MCD_OPC_CheckField, 11, 15, 0, 34, 38, 0, // Skip to: 16434 /* 6672 */ MCD_OPC_Decode, 164, 3, 0, // Opcode: CLRBHRB /* 6676 */ MCD_OPC_FilterValue, 14, 4, 0, 0, // Skip to: 6685 /* 6681 */ MCD_OPC_Decode, 210, 8, 70, // Opcode: MTPMR /* 6685 */ MCD_OPC_FilterValue, 22, 16, 38, 0, // Skip to: 16434 /* 6690 */ MCD_OPC_CheckField, 11, 12, 0, 9, 38, 0, // Skip to: 16434 /* 6697 */ MCD_OPC_Decode, 156, 12, 50, // Opcode: TCHECK /* 6701 */ MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 6869 /* 6706 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 6709 */ MCD_OPC_FilterValue, 20, 18, 0, 0, // Skip to: 6732 /* 6714 */ MCD_OPC_CheckField, 22, 4, 0, 241, 37, 0, // Skip to: 16434 /* 6721 */ MCD_OPC_CheckField, 11, 10, 0, 234, 37, 0, // Skip to: 16434 /* 6728 */ MCD_OPC_Decode, 155, 12, 71, // Opcode: TBEGIN /* 6732 */ MCD_OPC_FilterValue, 21, 11, 0, 0, // Skip to: 6748 /* 6737 */ MCD_OPC_CheckField, 11, 14, 0, 218, 37, 0, // Skip to: 16434 /* 6744 */ MCD_OPC_Decode, 166, 12, 72, // Opcode: TEND /* 6748 */ MCD_OPC_FilterValue, 23, 18, 0, 0, // Skip to: 6771 /* 6753 */ MCD_OPC_CheckField, 22, 3, 0, 202, 37, 0, // Skip to: 16434 /* 6760 */ MCD_OPC_CheckField, 11, 10, 0, 195, 37, 0, // Skip to: 16434 /* 6767 */ MCD_OPC_Decode, 184, 12, 71, // Opcode: TSR /* 6771 */ MCD_OPC_FilterValue, 24, 4, 0, 0, // Skip to: 6780 /* 6776 */ MCD_OPC_Decode, 147, 12, 73, // Opcode: TABORTWC /* 6780 */ MCD_OPC_FilterValue, 25, 4, 0, 0, // Skip to: 6789 /* 6785 */ MCD_OPC_Decode, 145, 12, 73, // Opcode: TABORTDC /* 6789 */ MCD_OPC_FilterValue, 26, 4, 0, 0, // Skip to: 6798 /* 6794 */ MCD_OPC_Decode, 148, 12, 74, // Opcode: TABORTWCI /* 6798 */ MCD_OPC_FilterValue, 27, 4, 0, 0, // Skip to: 6807 /* 6803 */ MCD_OPC_Decode, 146, 12, 74, // Opcode: TABORTDCI /* 6807 */ MCD_OPC_FilterValue, 28, 18, 0, 0, // Skip to: 6830 /* 6812 */ MCD_OPC_CheckField, 21, 5, 0, 143, 37, 0, // Skip to: 16434 /* 6819 */ MCD_OPC_CheckField, 11, 5, 0, 136, 37, 0, // Skip to: 16434 /* 6826 */ MCD_OPC_Decode, 144, 12, 75, // Opcode: TABORT /* 6830 */ MCD_OPC_FilterValue, 29, 18, 0, 0, // Skip to: 6853 /* 6835 */ MCD_OPC_CheckField, 21, 5, 0, 120, 37, 0, // Skip to: 16434 /* 6842 */ MCD_OPC_CheckField, 11, 5, 0, 113, 37, 0, // Skip to: 16434 /* 6849 */ MCD_OPC_Decode, 183, 12, 75, // Opcode: TRECLAIM /* 6853 */ MCD_OPC_FilterValue, 31, 104, 37, 0, // Skip to: 16434 /* 6858 */ MCD_OPC_CheckField, 11, 15, 0, 97, 37, 0, // Skip to: 16434 /* 6865 */ MCD_OPC_Decode, 182, 12, 0, // Opcode: TRECHKPT /* 6869 */ MCD_OPC_FilterValue, 2, 88, 37, 0, // Skip to: 16434 /* 6874 */ MCD_OPC_Decode, 143, 7, 76, // Opcode: ISEL /* 6878 */ MCD_OPC_FilterValue, 8, 49, 0, 0, // Skip to: 6932 /* 6883 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6886 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 6909 /* 6891 */ MCD_OPC_CheckField, 6, 6, 4, 64, 37, 0, // Skip to: 16434 /* 6898 */ MCD_OPC_CheckField, 0, 2, 0, 57, 37, 0, // Skip to: 16434 /* 6905 */ MCD_OPC_Decode, 190, 8, 77, // Opcode: MTCRF /* 6909 */ MCD_OPC_FilterValue, 1, 48, 37, 0, // Skip to: 16434 /* 6914 */ MCD_OPC_CheckField, 6, 6, 4, 41, 37, 0, // Skip to: 16434 /* 6921 */ MCD_OPC_CheckField, 0, 2, 0, 34, 37, 0, // Skip to: 16434 /* 6928 */ MCD_OPC_Decode, 208, 8, 78, // Opcode: MTOCRF /* 6932 */ MCD_OPC_FilterValue, 9, 49, 3, 0, // Skip to: 7754 /* 6937 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 6940 */ MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6994 /* 6945 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 6948 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 6971 /* 6953 */ MCD_OPC_CheckField, 11, 9, 0, 2, 37, 0, // Skip to: 16434 /* 6960 */ MCD_OPC_CheckField, 0, 2, 2, 251, 36, 0, // Skip to: 16434 /* 6967 */ MCD_OPC_Decode, 152, 8, 51, // Opcode: MFCR /* 6971 */ MCD_OPC_FilterValue, 1, 242, 36, 0, // Skip to: 16434 /* 6976 */ MCD_OPC_CheckField, 11, 1, 0, 235, 36, 0, // Skip to: 16434 /* 6983 */ MCD_OPC_CheckField, 0, 2, 2, 228, 36, 0, // Skip to: 16434 /* 6990 */ MCD_OPC_Decode, 168, 8, 79, // Opcode: MFOCRF /* 6994 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 7017 /* 6999 */ MCD_OPC_CheckField, 11, 5, 0, 212, 36, 0, // Skip to: 16434 /* 7006 */ MCD_OPC_CheckField, 1, 1, 1, 205, 36, 0, // Skip to: 16434 /* 7013 */ MCD_OPC_Decode, 181, 8, 80, // Opcode: MFVSRD /* 7017 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 7040 /* 7022 */ MCD_OPC_CheckField, 11, 10, 0, 189, 36, 0, // Skip to: 16434 /* 7029 */ MCD_OPC_CheckField, 0, 2, 2, 182, 36, 0, // Skip to: 16434 /* 7036 */ MCD_OPC_Decode, 167, 8, 51, // Opcode: MFMSR /* 7040 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 7063 /* 7045 */ MCD_OPC_CheckField, 11, 5, 0, 166, 36, 0, // Skip to: 16434 /* 7052 */ MCD_OPC_CheckField, 1, 1, 1, 159, 36, 0, // Skip to: 16434 /* 7059 */ MCD_OPC_Decode, 183, 8, 81, // Opcode: MFVSRWZ /* 7063 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 7079 /* 7068 */ MCD_OPC_CheckField, 1, 1, 0, 143, 36, 0, // Skip to: 16434 /* 7075 */ MCD_OPC_Decode, 206, 8, 82, // Opcode: MTMSR /* 7079 */ MCD_OPC_FilterValue, 5, 28, 0, 0, // Skip to: 7112 /* 7084 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 7087 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7096 /* 7092 */ MCD_OPC_Decode, 207, 8, 82, // Opcode: MTMSRD /* 7096 */ MCD_OPC_FilterValue, 1, 117, 36, 0, // Skip to: 16434 /* 7101 */ MCD_OPC_CheckField, 11, 5, 0, 110, 36, 0, // Skip to: 16434 /* 7108 */ MCD_OPC_Decode, 218, 8, 83, // Opcode: MTVSRD /* 7112 */ MCD_OPC_FilterValue, 6, 28, 0, 0, // Skip to: 7145 /* 7117 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 7120 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7129 /* 7125 */ MCD_OPC_Decode, 213, 8, 84, // Opcode: MTSR /* 7129 */ MCD_OPC_FilterValue, 1, 84, 36, 0, // Skip to: 16434 /* 7134 */ MCD_OPC_CheckField, 11, 5, 0, 77, 36, 0, // Skip to: 16434 /* 7141 */ MCD_OPC_Decode, 220, 8, 85, // Opcode: MTVSRWA /* 7145 */ MCD_OPC_FilterValue, 7, 28, 0, 0, // Skip to: 7178 /* 7150 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 7153 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7162 /* 7158 */ MCD_OPC_Decode, 214, 8, 86, // Opcode: MTSRIN /* 7162 */ MCD_OPC_FilterValue, 1, 51, 36, 0, // Skip to: 16434 /* 7167 */ MCD_OPC_CheckField, 11, 5, 0, 44, 36, 0, // Skip to: 16434 /* 7174 */ MCD_OPC_Decode, 222, 8, 85, // Opcode: MTVSRWZ /* 7178 */ MCD_OPC_FilterValue, 8, 18, 0, 0, // Skip to: 7201 /* 7183 */ MCD_OPC_CheckField, 16, 10, 0, 28, 36, 0, // Skip to: 16434 /* 7190 */ MCD_OPC_CheckField, 0, 2, 0, 21, 36, 0, // Skip to: 16434 /* 7197 */ MCD_OPC_Decode, 169, 12, 87, // Opcode: TLBIEL /* 7201 */ MCD_OPC_FilterValue, 9, 42, 0, 0, // Skip to: 7248 /* 7206 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 7209 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7232 /* 7214 */ MCD_OPC_CheckField, 16, 5, 0, 253, 35, 0, // Skip to: 16434 /* 7221 */ MCD_OPC_CheckField, 0, 1, 0, 246, 35, 0, // Skip to: 16434 /* 7228 */ MCD_OPC_Decode, 168, 12, 86, // Opcode: TLBIE /* 7232 */ MCD_OPC_FilterValue, 1, 237, 35, 0, // Skip to: 16434 /* 7237 */ MCD_OPC_CheckField, 11, 5, 0, 230, 35, 0, // Skip to: 16434 /* 7244 */ MCD_OPC_Decode, 182, 8, 88, // Opcode: MFVSRLD /* 7248 */ MCD_OPC_FilterValue, 10, 51, 0, 0, // Skip to: 7304 /* 7253 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7256 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7272 /* 7261 */ MCD_OPC_CheckField, 11, 15, 0, 206, 35, 0, // Skip to: 16434 /* 7268 */ MCD_OPC_Decode, 130, 11, 0, // Opcode: SLBSYNC /* 7272 */ MCD_OPC_FilterValue, 2, 197, 35, 0, // Skip to: 16434 /* 7277 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... /* 7280 */ MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 7290 /* 7286 */ MCD_OPC_Decode, 165, 8, 51, // Opcode: MFLR /* 7290 */ MCD_OPC_FilterValue, 160, 2, 4, 0, 0, // Skip to: 7300 /* 7296 */ MCD_OPC_Decode, 154, 8, 51, // Opcode: MFCTR /* 7300 */ MCD_OPC_Decode, 171, 8, 53, // Opcode: MFSPR /* 7304 */ MCD_OPC_FilterValue, 11, 28, 0, 0, // Skip to: 7337 /* 7309 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7312 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7328 /* 7317 */ MCD_OPC_CheckField, 11, 15, 0, 150, 35, 0, // Skip to: 16434 /* 7324 */ MCD_OPC_Decode, 167, 12, 0, // Opcode: TLBIA /* 7328 */ MCD_OPC_FilterValue, 2, 141, 35, 0, // Skip to: 16434 /* 7333 */ MCD_OPC_Decode, 175, 8, 53, // Opcode: MFTB /* 7337 */ MCD_OPC_FilterValue, 12, 42, 0, 0, // Skip to: 7384 /* 7342 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 7345 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7368 /* 7350 */ MCD_OPC_CheckField, 16, 5, 0, 117, 35, 0, // Skip to: 16434 /* 7357 */ MCD_OPC_CheckField, 0, 1, 0, 110, 35, 0, // Skip to: 16434 /* 7364 */ MCD_OPC_Decode, 129, 11, 86, // Opcode: SLBMTE /* 7368 */ MCD_OPC_FilterValue, 1, 101, 35, 0, // Skip to: 16434 /* 7373 */ MCD_OPC_CheckField, 11, 5, 0, 94, 35, 0, // Skip to: 16434 /* 7380 */ MCD_OPC_Decode, 221, 8, 89, // Opcode: MTVSRWS /* 7384 */ MCD_OPC_FilterValue, 13, 35, 0, 0, // Skip to: 7424 /* 7389 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 7392 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 7415 /* 7397 */ MCD_OPC_CheckField, 16, 10, 0, 70, 35, 0, // Skip to: 16434 /* 7404 */ MCD_OPC_CheckField, 0, 1, 0, 63, 35, 0, // Skip to: 16434 /* 7411 */ MCD_OPC_Decode, 253, 10, 87, // Opcode: SLBIE /* 7415 */ MCD_OPC_FilterValue, 1, 54, 35, 0, // Skip to: 16434 /* 7420 */ MCD_OPC_Decode, 219, 8, 90, // Opcode: MTVSRDD /* 7424 */ MCD_OPC_FilterValue, 14, 51, 0, 0, // Skip to: 7480 /* 7429 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7432 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 7448 /* 7437 */ MCD_OPC_CheckField, 16, 5, 0, 30, 35, 0, // Skip to: 16434 /* 7444 */ MCD_OPC_Decode, 254, 10, 86, // Opcode: SLBIEG /* 7448 */ MCD_OPC_FilterValue, 2, 21, 35, 0, // Skip to: 16434 /* 7453 */ MCD_OPC_ExtractField, 11, 10, // Inst{20-11} ... /* 7456 */ MCD_OPC_FilterValue, 128, 2, 4, 0, 0, // Skip to: 7466 /* 7462 */ MCD_OPC_Decode, 204, 8, 51, // Opcode: MTLR /* 7466 */ MCD_OPC_FilterValue, 160, 2, 4, 0, 0, // Skip to: 7476 /* 7472 */ MCD_OPC_Decode, 192, 8, 51, // Opcode: MTCTR /* 7476 */ MCD_OPC_Decode, 211, 8, 70, // Opcode: MTSPR /* 7480 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 7503 /* 7485 */ MCD_OPC_CheckField, 11, 15, 0, 238, 34, 0, // Skip to: 16434 /* 7492 */ MCD_OPC_CheckField, 0, 2, 0, 231, 34, 0, // Skip to: 16434 /* 7499 */ MCD_OPC_Decode, 252, 10, 0, // Opcode: SLBIA /* 7503 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 7519 /* 7508 */ MCD_OPC_CheckField, 1, 1, 1, 215, 34, 0, // Skip to: 16434 /* 7515 */ MCD_OPC_Decode, 173, 8, 84, // Opcode: MFSR /* 7519 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 7535 /* 7524 */ MCD_OPC_CheckField, 1, 1, 1, 199, 34, 0, // Skip to: 16434 /* 7531 */ MCD_OPC_Decode, 174, 8, 86, // Opcode: MFSRIN /* 7535 */ MCD_OPC_FilterValue, 23, 25, 0, 0, // Skip to: 7565 /* 7540 */ MCD_OPC_CheckField, 18, 3, 0, 183, 34, 0, // Skip to: 16434 /* 7547 */ MCD_OPC_CheckField, 11, 5, 0, 176, 34, 0, // Skip to: 16434 /* 7554 */ MCD_OPC_CheckField, 0, 2, 2, 169, 34, 0, // Skip to: 16434 /* 7561 */ MCD_OPC_Decode, 210, 3, 91, // Opcode: DARN /* 7565 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 7588 /* 7570 */ MCD_OPC_CheckField, 21, 5, 0, 153, 34, 0, // Skip to: 16434 /* 7577 */ MCD_OPC_CheckField, 0, 2, 0, 146, 34, 0, // Skip to: 16434 /* 7584 */ MCD_OPC_Decode, 170, 12, 58, // Opcode: TLBIVAX /* 7588 */ MCD_OPC_FilterValue, 26, 18, 0, 0, // Skip to: 7611 /* 7593 */ MCD_OPC_CheckField, 16, 5, 0, 130, 34, 0, // Skip to: 16434 /* 7600 */ MCD_OPC_CheckField, 0, 2, 2, 123, 34, 0, // Skip to: 16434 /* 7607 */ MCD_OPC_Decode, 128, 11, 86, // Opcode: SLBMFEV /* 7611 */ MCD_OPC_FilterValue, 28, 48, 0, 0, // Skip to: 7664 /* 7616 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7619 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 7639 /* 7624 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 7635 /* 7631 */ MCD_OPC_Decode, 175, 12, 58, // Opcode: TLBSX /* 7635 */ MCD_OPC_Decode, 176, 12, 62, // Opcode: TLBSX2 /* 7639 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7648 /* 7644 */ MCD_OPC_Decode, 177, 12, 62, // Opcode: TLBSX2D /* 7648 */ MCD_OPC_FilterValue, 2, 77, 34, 0, // Skip to: 16434 /* 7653 */ MCD_OPC_CheckField, 16, 5, 0, 70, 34, 0, // Skip to: 16434 /* 7660 */ MCD_OPC_Decode, 255, 10, 86, // Opcode: SLBMFEE /* 7664 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 7692 /* 7669 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7672 */ MCD_OPC_FilterValue, 0, 53, 34, 0, // Skip to: 16434 /* 7677 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, 0, // Skip to: 7688 /* 7684 */ MCD_OPC_Decode, 173, 12, 0, // Opcode: TLBRE /* 7688 */ MCD_OPC_Decode, 174, 12, 92, // Opcode: TLBRE2 /* 7692 */ MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 7731 /* 7697 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7700 */ MCD_OPC_FilterValue, 0, 25, 34, 0, // Skip to: 16434 /* 7705 */ MCD_OPC_CheckField, 11, 15, 0, 4, 0, 0, // Skip to: 7716 /* 7712 */ MCD_OPC_Decode, 179, 12, 0, // Opcode: TLBWE /* 7716 */ MCD_OPC_CheckField, 16, 10, 0, 4, 0, 0, // Skip to: 7727 /* 7723 */ MCD_OPC_Decode, 171, 12, 87, // Opcode: TLBLD /* 7727 */ MCD_OPC_Decode, 180, 12, 92, // Opcode: TLBWE2 /* 7731 */ MCD_OPC_FilterValue, 31, 250, 33, 0, // Skip to: 16434 /* 7736 */ MCD_OPC_CheckField, 16, 10, 0, 243, 33, 0, // Skip to: 16434 /* 7743 */ MCD_OPC_CheckField, 0, 2, 0, 236, 33, 0, // Skip to: 16434 /* 7750 */ MCD_OPC_Decode, 172, 12, 87, // Opcode: TLBLI /* 7754 */ MCD_OPC_FilterValue, 10, 141, 1, 0, // Skip to: 8156 /* 7759 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 7762 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 7797 /* 7767 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7770 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7779 /* 7775 */ MCD_OPC_Decode, 231, 7, 93, // Opcode: LWARX /* 7779 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7788 /* 7784 */ MCD_OPC_Decode, 232, 7, 93, // Opcode: LWARXL /* 7788 */ MCD_OPC_FilterValue, 2, 193, 33, 0, // Skip to: 16434 /* 7793 */ MCD_OPC_Decode, 171, 7, 94, // Opcode: LDX /* 7797 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 7832 /* 7802 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7805 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7814 /* 7810 */ MCD_OPC_Decode, 147, 7, 93, // Opcode: LBARX /* 7814 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 7823 /* 7819 */ MCD_OPC_Decode, 148, 7, 93, // Opcode: LBARXL /* 7823 */ MCD_OPC_FilterValue, 2, 158, 33, 0, // Skip to: 16434 /* 7828 */ MCD_OPC_Decode, 170, 7, 95, // Opcode: LDUX /* 7832 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 7858 /* 7837 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7840 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7849 /* 7845 */ MCD_OPC_Decode, 163, 7, 94, // Opcode: LDARX /* 7849 */ MCD_OPC_FilterValue, 1, 132, 33, 0, // Skip to: 16434 /* 7854 */ MCD_OPC_Decode, 164, 7, 94, // Opcode: LDARXL /* 7858 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 7884 /* 7863 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 7866 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 7875 /* 7871 */ MCD_OPC_Decode, 194, 7, 93, // Opcode: LHARX /* 7875 */ MCD_OPC_FilterValue, 1, 106, 33, 0, // Skip to: 16434 /* 7880 */ MCD_OPC_Decode, 195, 7, 93, // Opcode: LHARXL /* 7884 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 7900 /* 7889 */ MCD_OPC_CheckField, 0, 2, 2, 90, 33, 0, // Skip to: 16434 /* 7896 */ MCD_OPC_Decode, 180, 11, 94, // Opcode: STDX /* 7900 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 7916 /* 7905 */ MCD_OPC_CheckField, 0, 2, 2, 74, 33, 0, // Skip to: 16434 /* 7912 */ MCD_OPC_Decode, 179, 11, 96, // Opcode: STDUX /* 7916 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 7932 /* 7921 */ MCD_OPC_CheckField, 0, 2, 2, 58, 33, 0, // Skip to: 16434 /* 7928 */ MCD_OPC_Decode, 168, 7, 94, // Opcode: LDMX /* 7932 */ MCD_OPC_FilterValue, 10, 11, 0, 0, // Skip to: 7948 /* 7937 */ MCD_OPC_CheckField, 0, 2, 2, 42, 33, 0, // Skip to: 16434 /* 7944 */ MCD_OPC_Decode, 235, 7, 94, // Opcode: LWAX /* 7948 */ MCD_OPC_FilterValue, 11, 11, 0, 0, // Skip to: 7964 /* 7953 */ MCD_OPC_CheckField, 0, 2, 2, 26, 33, 0, // Skip to: 16434 /* 7960 */ MCD_OPC_Decode, 234, 7, 95, // Opcode: LWAUX /* 7964 */ MCD_OPC_FilterValue, 16, 11, 0, 0, // Skip to: 7980 /* 7969 */ MCD_OPC_CheckField, 0, 2, 0, 10, 33, 0, // Skip to: 16434 /* 7976 */ MCD_OPC_Decode, 166, 7, 94, // Opcode: LDBRX /* 7980 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 7996 /* 7985 */ MCD_OPC_CheckField, 0, 2, 2, 250, 32, 0, // Skip to: 16434 /* 7992 */ MCD_OPC_Decode, 222, 7, 59, // Opcode: LSWI /* 7996 */ MCD_OPC_FilterValue, 20, 11, 0, 0, // Skip to: 8012 /* 8001 */ MCD_OPC_CheckField, 0, 2, 0, 234, 32, 0, // Skip to: 16434 /* 8008 */ MCD_OPC_Decode, 175, 11, 94, // Opcode: STDBRX /* 8012 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 8028 /* 8017 */ MCD_OPC_CheckField, 0, 2, 2, 218, 32, 0, // Skip to: 16434 /* 8024 */ MCD_OPC_Decode, 210, 11, 59, // Opcode: STSWI /* 8028 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 8044 /* 8033 */ MCD_OPC_CheckField, 0, 2, 2, 202, 32, 0, // Skip to: 16434 /* 8040 */ MCD_OPC_Decode, 243, 7, 62, // Opcode: LWZCIX /* 8044 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 8060 /* 8049 */ MCD_OPC_CheckField, 0, 2, 2, 186, 32, 0, // Skip to: 16434 /* 8056 */ MCD_OPC_Decode, 207, 7, 62, // Opcode: LHZCIX /* 8060 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 8076 /* 8065 */ MCD_OPC_CheckField, 0, 2, 2, 170, 32, 0, // Skip to: 16434 /* 8072 */ MCD_OPC_Decode, 152, 7, 62, // Opcode: LBZCIX /* 8076 */ MCD_OPC_FilterValue, 27, 11, 0, 0, // Skip to: 8092 /* 8081 */ MCD_OPC_CheckField, 0, 2, 2, 154, 32, 0, // Skip to: 16434 /* 8088 */ MCD_OPC_Decode, 167, 7, 62, // Opcode: LDCIX /* 8092 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 8108 /* 8097 */ MCD_OPC_CheckField, 0, 2, 2, 138, 32, 0, // Skip to: 16434 /* 8104 */ MCD_OPC_Decode, 220, 11, 62, // Opcode: STWCIX /* 8108 */ MCD_OPC_FilterValue, 29, 11, 0, 0, // Skip to: 8124 /* 8113 */ MCD_OPC_CheckField, 0, 2, 2, 122, 32, 0, // Skip to: 16434 /* 8120 */ MCD_OPC_Decode, 196, 11, 62, // Opcode: STHCIX /* 8124 */ MCD_OPC_FilterValue, 30, 11, 0, 0, // Skip to: 8140 /* 8129 */ MCD_OPC_CheckField, 0, 2, 2, 106, 32, 0, // Skip to: 16434 /* 8136 */ MCD_OPC_Decode, 161, 11, 62, // Opcode: STBCIX /* 8140 */ MCD_OPC_FilterValue, 31, 97, 32, 0, // Skip to: 16434 /* 8145 */ MCD_OPC_CheckField, 0, 2, 2, 90, 32, 0, // Skip to: 16434 /* 8152 */ MCD_OPC_Decode, 176, 11, 62, // Opcode: STDCIX /* 8156 */ MCD_OPC_FilterValue, 11, 89, 3, 0, // Skip to: 9018 /* 8161 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 8164 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 8197 /* 8169 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8172 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8188 /* 8177 */ MCD_OPC_CheckField, 25, 1, 0, 58, 32, 0, // Skip to: 16434 /* 8184 */ MCD_OPC_Decode, 140, 7, 57, // Opcode: ICBT /* 8188 */ MCD_OPC_FilterValue, 2, 49, 32, 0, // Skip to: 16434 /* 8193 */ MCD_OPC_Decode, 248, 7, 93, // Opcode: LWZX /* 8197 */ MCD_OPC_FilterValue, 1, 28, 0, 0, // Skip to: 8230 /* 8202 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8205 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8221 /* 8210 */ MCD_OPC_CheckField, 21, 5, 0, 25, 32, 0, // Skip to: 16434 /* 8217 */ MCD_OPC_Decode, 215, 3, 97, // Opcode: DCBST /* 8221 */ MCD_OPC_FilterValue, 2, 16, 32, 0, // Skip to: 16434 /* 8226 */ MCD_OPC_Decode, 246, 7, 98, // Opcode: LWZUX /* 8230 */ MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 8256 /* 8235 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8238 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8247 /* 8243 */ MCD_OPC_Decode, 212, 3, 99, // Opcode: DCBF /* 8247 */ MCD_OPC_FilterValue, 2, 246, 31, 0, // Skip to: 16434 /* 8252 */ MCD_OPC_Decode, 157, 7, 93, // Opcode: LBZX /* 8256 */ MCD_OPC_FilterValue, 3, 11, 0, 0, // Skip to: 8272 /* 8261 */ MCD_OPC_CheckField, 0, 2, 2, 230, 31, 0, // Skip to: 16434 /* 8268 */ MCD_OPC_Decode, 155, 7, 98, // Opcode: LBZUX /* 8272 */ MCD_OPC_FilterValue, 4, 21, 0, 0, // Skip to: 8298 /* 8277 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8280 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8289 /* 8285 */ MCD_OPC_Decode, 221, 11, 93, // Opcode: STWCX /* 8289 */ MCD_OPC_FilterValue, 2, 204, 31, 0, // Skip to: 16434 /* 8294 */ MCD_OPC_Decode, 227, 11, 93, // Opcode: STWX /* 8298 */ MCD_OPC_FilterValue, 5, 11, 0, 0, // Skip to: 8314 /* 8303 */ MCD_OPC_CheckField, 0, 2, 2, 188, 31, 0, // Skip to: 16434 /* 8310 */ MCD_OPC_Decode, 225, 11, 100, // Opcode: STWUX /* 8314 */ MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 8340 /* 8319 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8322 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8331 /* 8327 */ MCD_OPC_Decode, 177, 11, 94, // Opcode: STDCX /* 8331 */ MCD_OPC_FilterValue, 2, 162, 31, 0, // Skip to: 16434 /* 8336 */ MCD_OPC_Decode, 168, 11, 93, // Opcode: STBX /* 8340 */ MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 8366 /* 8345 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8348 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8357 /* 8353 */ MCD_OPC_Decode, 219, 3, 99, // Opcode: DCBTST /* 8357 */ MCD_OPC_FilterValue, 2, 136, 31, 0, // Skip to: 16434 /* 8362 */ MCD_OPC_Decode, 166, 11, 100, // Opcode: STBUX /* 8366 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 8392 /* 8371 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8374 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8383 /* 8379 */ MCD_OPC_Decode, 217, 3, 99, // Opcode: DCBT /* 8383 */ MCD_OPC_FilterValue, 2, 110, 31, 0, // Skip to: 16434 /* 8388 */ MCD_OPC_Decode, 212, 7, 93, // Opcode: LHZX /* 8392 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 8408 /* 8397 */ MCD_OPC_CheckField, 0, 2, 2, 94, 31, 0, // Skip to: 16434 /* 8404 */ MCD_OPC_Decode, 210, 7, 98, // Opcode: LHZUX /* 8408 */ MCD_OPC_FilterValue, 10, 38, 0, 0, // Skip to: 8451 /* 8413 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8416 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8442 /* 8421 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 8424 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8433 /* 8429 */ MCD_OPC_Decode, 244, 3, 101, // Opcode: DST /* 8433 */ MCD_OPC_FilterValue, 4, 60, 31, 0, // Skip to: 16434 /* 8438 */ MCD_OPC_Decode, 250, 3, 101, // Opcode: DSTT /* 8442 */ MCD_OPC_FilterValue, 2, 51, 31, 0, // Skip to: 16434 /* 8447 */ MCD_OPC_Decode, 200, 7, 93, // Opcode: LHAX /* 8451 */ MCD_OPC_FilterValue, 11, 38, 0, 0, // Skip to: 8494 /* 8456 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8459 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 8485 /* 8464 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 8467 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8476 /* 8472 */ MCD_OPC_Decode, 246, 3, 101, // Opcode: DSTST /* 8476 */ MCD_OPC_FilterValue, 4, 17, 31, 0, // Skip to: 16434 /* 8481 */ MCD_OPC_Decode, 248, 3, 101, // Opcode: DSTSTT /* 8485 */ MCD_OPC_FilterValue, 2, 8, 31, 0, // Skip to: 16434 /* 8490 */ MCD_OPC_Decode, 198, 7, 98, // Opcode: LHAUX /* 8494 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 8510 /* 8499 */ MCD_OPC_CheckField, 0, 2, 2, 248, 30, 0, // Skip to: 16434 /* 8506 */ MCD_OPC_Decode, 203, 11, 93, // Opcode: STHX /* 8510 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 8526 /* 8515 */ MCD_OPC_CheckField, 0, 2, 2, 232, 30, 0, // Skip to: 16434 /* 8522 */ MCD_OPC_Decode, 201, 11, 100, // Opcode: STHUX /* 8526 */ MCD_OPC_FilterValue, 14, 18, 0, 0, // Skip to: 8549 /* 8531 */ MCD_OPC_CheckField, 21, 5, 0, 216, 30, 0, // Skip to: 16434 /* 8538 */ MCD_OPC_CheckField, 0, 2, 0, 209, 30, 0, // Skip to: 16434 /* 8545 */ MCD_OPC_Decode, 214, 3, 97, // Opcode: DCBI /* 8549 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 8575 /* 8554 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8557 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8566 /* 8562 */ MCD_OPC_Decode, 238, 7, 93, // Opcode: LWBRX /* 8566 */ MCD_OPC_FilterValue, 2, 183, 30, 0, // Skip to: 16434 /* 8571 */ MCD_OPC_Decode, 191, 7, 102, // Opcode: LFSX /* 8575 */ MCD_OPC_FilterValue, 17, 28, 0, 0, // Skip to: 8608 /* 8580 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8583 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8599 /* 8588 */ MCD_OPC_CheckField, 11, 15, 0, 159, 30, 0, // Skip to: 16434 /* 8595 */ MCD_OPC_Decode, 178, 12, 0, // Opcode: TLBSYNC /* 8599 */ MCD_OPC_FilterValue, 2, 150, 30, 0, // Skip to: 16434 /* 8604 */ MCD_OPC_Decode, 190, 7, 103, // Opcode: LFSUX /* 8608 */ MCD_OPC_FilterValue, 18, 35, 0, 0, // Skip to: 8648 /* 8613 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8616 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 8639 /* 8621 */ MCD_OPC_CheckField, 23, 3, 0, 126, 30, 0, // Skip to: 16434 /* 8628 */ MCD_OPC_CheckField, 11, 10, 0, 119, 30, 0, // Skip to: 16434 /* 8635 */ MCD_OPC_Decode, 143, 12, 104, // Opcode: SYNC /* 8639 */ MCD_OPC_FilterValue, 2, 110, 30, 0, // Skip to: 16434 /* 8644 */ MCD_OPC_Decode, 185, 7, 105, // Opcode: LFDX /* 8648 */ MCD_OPC_FilterValue, 19, 11, 0, 0, // Skip to: 8664 /* 8653 */ MCD_OPC_CheckField, 0, 2, 2, 94, 30, 0, // Skip to: 16434 /* 8660 */ MCD_OPC_Decode, 184, 7, 106, // Opcode: LFDUX /* 8664 */ MCD_OPC_FilterValue, 20, 21, 0, 0, // Skip to: 8690 /* 8669 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8672 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 8681 /* 8677 */ MCD_OPC_Decode, 219, 11, 93, // Opcode: STWBRX /* 8681 */ MCD_OPC_FilterValue, 2, 68, 30, 0, // Skip to: 16434 /* 8686 */ MCD_OPC_Decode, 192, 11, 102, // Opcode: STFSX /* 8690 */ MCD_OPC_FilterValue, 21, 21, 0, 0, // Skip to: 8716 /* 8695 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8698 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8707 /* 8703 */ MCD_OPC_Decode, 162, 11, 93, // Opcode: STBCX /* 8707 */ MCD_OPC_FilterValue, 2, 42, 30, 0, // Skip to: 16434 /* 8712 */ MCD_OPC_Decode, 191, 11, 107, // Opcode: STFSUX /* 8716 */ MCD_OPC_FilterValue, 22, 21, 0, 0, // Skip to: 8742 /* 8721 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8724 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 8733 /* 8729 */ MCD_OPC_Decode, 197, 11, 93, // Opcode: STHCX /* 8733 */ MCD_OPC_FilterValue, 2, 16, 30, 0, // Skip to: 16434 /* 8738 */ MCD_OPC_Decode, 187, 11, 105, // Opcode: STFDX /* 8742 */ MCD_OPC_FilterValue, 23, 28, 0, 0, // Skip to: 8775 /* 8747 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8750 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8766 /* 8755 */ MCD_OPC_CheckField, 21, 5, 0, 248, 29, 0, // Skip to: 16434 /* 8762 */ MCD_OPC_Decode, 211, 3, 97, // Opcode: DCBA /* 8766 */ MCD_OPC_FilterValue, 2, 239, 29, 0, // Skip to: 16434 /* 8771 */ MCD_OPC_Decode, 186, 11, 108, // Opcode: STFDUX /* 8775 */ MCD_OPC_FilterValue, 24, 11, 0, 0, // Skip to: 8791 /* 8780 */ MCD_OPC_CheckField, 0, 2, 0, 223, 29, 0, // Skip to: 16434 /* 8787 */ MCD_OPC_Decode, 202, 7, 93, // Opcode: LHBRX /* 8791 */ MCD_OPC_FilterValue, 25, 49, 0, 0, // Skip to: 8845 /* 8796 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... /* 8799 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 8822 /* 8804 */ MCD_OPC_CheckField, 11, 10, 0, 199, 29, 0, // Skip to: 16434 /* 8811 */ MCD_OPC_CheckField, 0, 2, 0, 192, 29, 0, // Skip to: 16434 /* 8818 */ MCD_OPC_Decode, 242, 3, 109, // Opcode: DSS /* 8822 */ MCD_OPC_FilterValue, 4, 183, 29, 0, // Skip to: 16434 /* 8827 */ MCD_OPC_CheckField, 11, 12, 0, 176, 29, 0, // Skip to: 16434 /* 8834 */ MCD_OPC_CheckField, 0, 2, 0, 169, 29, 0, // Skip to: 16434 /* 8841 */ MCD_OPC_Decode, 243, 3, 0, // Opcode: DSSALL /* 8845 */ MCD_OPC_FilterValue, 26, 46, 0, 0, // Skip to: 8896 /* 8850 */ MCD_OPC_ExtractField, 1, 1, // Inst{1} ... /* 8853 */ MCD_OPC_FilterValue, 0, 22, 0, 0, // Skip to: 8880 /* 8858 */ MCD_OPC_CheckField, 11, 15, 0, 11, 0, 0, // Skip to: 8876 /* 8865 */ MCD_OPC_CheckField, 0, 1, 0, 4, 0, 0, // Skip to: 8876 /* 8872 */ MCD_OPC_Decode, 145, 6, 0, // Opcode: EnforceIEIO /* 8876 */ MCD_OPC_Decode, 147, 8, 110, // Opcode: MBAR /* 8880 */ MCD_OPC_FilterValue, 1, 125, 29, 0, // Skip to: 16434 /* 8885 */ MCD_OPC_CheckField, 0, 1, 0, 118, 29, 0, // Skip to: 16434 /* 8892 */ MCD_OPC_Decode, 186, 7, 105, // Opcode: LFIWAX /* 8896 */ MCD_OPC_FilterValue, 27, 28, 0, 0, // Skip to: 8929 /* 8901 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8904 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8920 /* 8909 */ MCD_OPC_CheckField, 11, 15, 0, 94, 29, 0, // Skip to: 16434 /* 8916 */ MCD_OPC_Decode, 188, 8, 0, // Opcode: MSGSYNC /* 8920 */ MCD_OPC_FilterValue, 2, 85, 29, 0, // Skip to: 16434 /* 8925 */ MCD_OPC_Decode, 187, 7, 105, // Opcode: LFIWZX /* 8929 */ MCD_OPC_FilterValue, 28, 11, 0, 0, // Skip to: 8945 /* 8934 */ MCD_OPC_CheckField, 0, 2, 0, 69, 29, 0, // Skip to: 16434 /* 8941 */ MCD_OPC_Decode, 195, 11, 93, // Opcode: STHBRX /* 8945 */ MCD_OPC_FilterValue, 30, 28, 0, 0, // Skip to: 8978 /* 8950 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 8953 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 8969 /* 8958 */ MCD_OPC_CheckField, 21, 5, 0, 45, 29, 0, // Skip to: 16434 /* 8965 */ MCD_OPC_Decode, 136, 7, 97, // Opcode: ICBI /* 8969 */ MCD_OPC_FilterValue, 2, 36, 29, 0, // Skip to: 16434 /* 8974 */ MCD_OPC_Decode, 188, 11, 105, // Opcode: STFIWX /* 8978 */ MCD_OPC_FilterValue, 31, 27, 29, 0, // Skip to: 16434 /* 8983 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 8986 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9002 /* 8991 */ MCD_OPC_CheckField, 0, 2, 0, 12, 29, 0, // Skip to: 16434 /* 8998 */ MCD_OPC_Decode, 221, 3, 97, // Opcode: DCBZ /* 9002 */ MCD_OPC_FilterValue, 1, 3, 29, 0, // Skip to: 16434 /* 9007 */ MCD_OPC_CheckField, 0, 2, 0, 252, 28, 0, // Skip to: 16434 /* 9014 */ MCD_OPC_Decode, 223, 3, 97, // Opcode: DCBZL /* 9018 */ MCD_OPC_FilterValue, 12, 107, 0, 0, // Skip to: 9130 /* 9023 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 9026 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9052 /* 9031 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9034 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9043 /* 9039 */ MCD_OPC_Decode, 133, 11, 111, // Opcode: SLW /* 9043 */ MCD_OPC_FilterValue, 1, 218, 28, 0, // Skip to: 16434 /* 9048 */ MCD_OPC_Decode, 136, 11, 111, // Opcode: SLWo /* 9052 */ MCD_OPC_FilterValue, 16, 21, 0, 0, // Skip to: 9078 /* 9057 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9060 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9069 /* 9065 */ MCD_OPC_Decode, 155, 11, 111, // Opcode: SRW /* 9069 */ MCD_OPC_FilterValue, 1, 192, 28, 0, // Skip to: 16434 /* 9074 */ MCD_OPC_Decode, 158, 11, 111, // Opcode: SRWo /* 9078 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 9104 /* 9083 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9086 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9095 /* 9091 */ MCD_OPC_Decode, 149, 11, 111, // Opcode: SRAW /* 9095 */ MCD_OPC_FilterValue, 1, 166, 28, 0, // Skip to: 16434 /* 9100 */ MCD_OPC_Decode, 152, 11, 111, // Opcode: SRAWo /* 9104 */ MCD_OPC_FilterValue, 25, 157, 28, 0, // Skip to: 16434 /* 9109 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9112 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9121 /* 9117 */ MCD_OPC_Decode, 150, 11, 112, // Opcode: SRAWI /* 9121 */ MCD_OPC_FilterValue, 1, 140, 28, 0, // Skip to: 16434 /* 9126 */ MCD_OPC_Decode, 151, 11, 112, // Opcode: SRAWIo /* 9130 */ MCD_OPC_FilterValue, 13, 210, 1, 0, // Skip to: 9601 /* 9135 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 9138 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 9196 /* 9143 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9146 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9162 /* 9151 */ MCD_OPC_CheckField, 11, 5, 0, 108, 28, 0, // Skip to: 16434 /* 9158 */ MCD_OPC_Decode, 180, 3, 113, // Opcode: CNTLZW /* 9162 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 9178 /* 9167 */ MCD_OPC_CheckField, 11, 5, 0, 92, 28, 0, // Skip to: 16434 /* 9174 */ MCD_OPC_Decode, 183, 3, 113, // Opcode: CNTLZWo /* 9178 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9187 /* 9183 */ MCD_OPC_Decode, 131, 11, 114, // Opcode: SLD /* 9187 */ MCD_OPC_FilterValue, 3, 74, 28, 0, // Skip to: 16434 /* 9192 */ MCD_OPC_Decode, 132, 11, 114, // Opcode: SLDo /* 9196 */ MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 9236 /* 9201 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9204 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9220 /* 9209 */ MCD_OPC_CheckField, 11, 5, 0, 50, 28, 0, // Skip to: 16434 /* 9216 */ MCD_OPC_Decode, 178, 3, 115, // Opcode: CNTLZD /* 9220 */ MCD_OPC_FilterValue, 1, 41, 28, 0, // Skip to: 16434 /* 9225 */ MCD_OPC_CheckField, 11, 5, 0, 34, 28, 0, // Skip to: 16434 /* 9232 */ MCD_OPC_Decode, 179, 3, 115, // Opcode: CNTLZDo /* 9236 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 9259 /* 9241 */ MCD_OPC_CheckField, 11, 5, 0, 18, 28, 0, // Skip to: 16434 /* 9248 */ MCD_OPC_CheckField, 0, 2, 0, 11, 28, 0, // Skip to: 16434 /* 9255 */ MCD_OPC_Decode, 140, 9, 113, // Opcode: POPCNTB /* 9259 */ MCD_OPC_FilterValue, 11, 18, 0, 0, // Skip to: 9282 /* 9264 */ MCD_OPC_CheckField, 11, 5, 0, 251, 27, 0, // Skip to: 16434 /* 9271 */ MCD_OPC_CheckField, 0, 2, 0, 244, 27, 0, // Skip to: 16434 /* 9278 */ MCD_OPC_Decode, 142, 9, 113, // Opcode: POPCNTW /* 9282 */ MCD_OPC_FilterValue, 15, 18, 0, 0, // Skip to: 9305 /* 9287 */ MCD_OPC_CheckField, 11, 5, 0, 228, 27, 0, // Skip to: 16434 /* 9294 */ MCD_OPC_CheckField, 0, 2, 0, 221, 27, 0, // Skip to: 16434 /* 9301 */ MCD_OPC_Decode, 141, 9, 115, // Opcode: POPCNTD /* 9305 */ MCD_OPC_FilterValue, 16, 53, 0, 0, // Skip to: 9363 /* 9310 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9313 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9329 /* 9318 */ MCD_OPC_CheckField, 11, 5, 0, 197, 27, 0, // Skip to: 16434 /* 9325 */ MCD_OPC_Decode, 186, 3, 113, // Opcode: CNTTZW /* 9329 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 9345 /* 9334 */ MCD_OPC_CheckField, 11, 5, 0, 181, 27, 0, // Skip to: 16434 /* 9341 */ MCD_OPC_Decode, 189, 3, 113, // Opcode: CNTTZWo /* 9345 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 9354 /* 9350 */ MCD_OPC_Decode, 153, 11, 114, // Opcode: SRD /* 9354 */ MCD_OPC_FilterValue, 3, 163, 27, 0, // Skip to: 16434 /* 9359 */ MCD_OPC_Decode, 154, 11, 114, // Opcode: SRDo /* 9363 */ MCD_OPC_FilterValue, 17, 35, 0, 0, // Skip to: 9403 /* 9368 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9371 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9387 /* 9376 */ MCD_OPC_CheckField, 11, 5, 0, 139, 27, 0, // Skip to: 16434 /* 9383 */ MCD_OPC_Decode, 184, 3, 115, // Opcode: CNTTZD /* 9387 */ MCD_OPC_FilterValue, 1, 130, 27, 0, // Skip to: 16434 /* 9392 */ MCD_OPC_CheckField, 11, 5, 0, 123, 27, 0, // Skip to: 16434 /* 9399 */ MCD_OPC_Decode, 185, 3, 115, // Opcode: CNTTZDo /* 9403 */ MCD_OPC_FilterValue, 24, 21, 0, 0, // Skip to: 9429 /* 9408 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9411 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9420 /* 9416 */ MCD_OPC_Decode, 144, 11, 114, // Opcode: SRAD /* 9420 */ MCD_OPC_FilterValue, 1, 97, 27, 0, // Skip to: 16434 /* 9425 */ MCD_OPC_Decode, 148, 11, 114, // Opcode: SRADo /* 9429 */ MCD_OPC_FilterValue, 25, 21, 0, 0, // Skip to: 9455 /* 9434 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 9437 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9446 /* 9442 */ MCD_OPC_Decode, 145, 11, 116, // Opcode: SRADI /* 9446 */ MCD_OPC_FilterValue, 1, 71, 27, 0, // Skip to: 16434 /* 9451 */ MCD_OPC_Decode, 147, 11, 116, // Opcode: SRADIo /* 9455 */ MCD_OPC_FilterValue, 27, 21, 0, 0, // Skip to: 9481 /* 9460 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... /* 9463 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9472 /* 9468 */ MCD_OPC_Decode, 139, 6, 116, // Opcode: EXTSWSLI /* 9472 */ MCD_OPC_FilterValue, 1, 45, 27, 0, // Skip to: 16434 /* 9477 */ MCD_OPC_Decode, 140, 6, 116, // Opcode: EXTSWSLIo /* 9481 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 9521 /* 9486 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9489 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9505 /* 9494 */ MCD_OPC_CheckField, 11, 5, 0, 21, 27, 0, // Skip to: 16434 /* 9501 */ MCD_OPC_Decode, 133, 6, 113, // Opcode: EXTSH /* 9505 */ MCD_OPC_FilterValue, 1, 12, 27, 0, // Skip to: 16434 /* 9510 */ MCD_OPC_CheckField, 11, 5, 0, 5, 27, 0, // Skip to: 16434 /* 9517 */ MCD_OPC_Decode, 137, 6, 113, // Opcode: EXTSHo /* 9521 */ MCD_OPC_FilterValue, 29, 35, 0, 0, // Skip to: 9561 /* 9526 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9529 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9545 /* 9534 */ MCD_OPC_CheckField, 11, 5, 0, 237, 26, 0, // Skip to: 16434 /* 9541 */ MCD_OPC_Decode, 128, 6, 113, // Opcode: EXTSB /* 9545 */ MCD_OPC_FilterValue, 1, 228, 26, 0, // Skip to: 16434 /* 9550 */ MCD_OPC_CheckField, 11, 5, 0, 221, 26, 0, // Skip to: 16434 /* 9557 */ MCD_OPC_Decode, 132, 6, 113, // Opcode: EXTSBo /* 9561 */ MCD_OPC_FilterValue, 30, 212, 26, 0, // Skip to: 16434 /* 9566 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9569 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 9585 /* 9574 */ MCD_OPC_CheckField, 11, 5, 0, 197, 26, 0, // Skip to: 16434 /* 9581 */ MCD_OPC_Decode, 138, 6, 115, // Opcode: EXTSW /* 9585 */ MCD_OPC_FilterValue, 1, 188, 26, 0, // Skip to: 16434 /* 9590 */ MCD_OPC_CheckField, 11, 5, 0, 181, 26, 0, // Skip to: 16434 /* 9597 */ MCD_OPC_Decode, 144, 6, 115, // Opcode: EXTSWo /* 9601 */ MCD_OPC_FilterValue, 14, 243, 0, 0, // Skip to: 9849 /* 9606 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 9609 */ MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 9635 /* 9614 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9617 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9626 /* 9622 */ MCD_OPC_Decode, 253, 1, 111, // Opcode: AND /* 9626 */ MCD_OPC_FilterValue, 1, 147, 26, 0, // Skip to: 16434 /* 9631 */ MCD_OPC_Decode, 140, 2, 111, // Opcode: ANDo /* 9635 */ MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 9661 /* 9640 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9643 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9652 /* 9648 */ MCD_OPC_Decode, 128, 2, 111, // Opcode: ANDC /* 9652 */ MCD_OPC_FilterValue, 1, 121, 26, 0, // Skip to: 16434 /* 9657 */ MCD_OPC_Decode, 131, 2, 111, // Opcode: ANDCo /* 9661 */ MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 9687 /* 9666 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9669 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9678 /* 9674 */ MCD_OPC_Decode, 252, 8, 111, // Opcode: NOR /* 9678 */ MCD_OPC_FilterValue, 1, 95, 26, 0, // Skip to: 16434 /* 9683 */ MCD_OPC_Decode, 255, 8, 111, // Opcode: NORo /* 9687 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 9703 /* 9692 */ MCD_OPC_CheckField, 0, 2, 0, 79, 26, 0, // Skip to: 16434 /* 9699 */ MCD_OPC_Decode, 162, 3, 117, // Opcode: BPERMD /* 9703 */ MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 9729 /* 9708 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9711 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9720 /* 9716 */ MCD_OPC_Decode, 185, 4, 111, // Opcode: EQV /* 9720 */ MCD_OPC_FilterValue, 1, 53, 26, 0, // Skip to: 16434 /* 9725 */ MCD_OPC_Decode, 188, 4, 111, // Opcode: EQVo /* 9729 */ MCD_OPC_FilterValue, 9, 21, 0, 0, // Skip to: 9755 /* 9734 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9737 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9746 /* 9742 */ MCD_OPC_Decode, 227, 14, 111, // Opcode: XOR /* 9746 */ MCD_OPC_FilterValue, 1, 27, 26, 0, // Skip to: 16434 /* 9751 */ MCD_OPC_Decode, 234, 14, 111, // Opcode: XORo /* 9755 */ MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 9781 /* 9760 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9763 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9772 /* 9768 */ MCD_OPC_Decode, 131, 9, 111, // Opcode: ORC /* 9772 */ MCD_OPC_FilterValue, 1, 1, 26, 0, // Skip to: 16434 /* 9777 */ MCD_OPC_Decode, 134, 9, 111, // Opcode: ORCo /* 9781 */ MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 9807 /* 9786 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9789 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9798 /* 9794 */ MCD_OPC_Decode, 128, 9, 111, // Opcode: OR /* 9798 */ MCD_OPC_FilterValue, 1, 231, 25, 0, // Skip to: 16434 /* 9803 */ MCD_OPC_Decode, 139, 9, 111, // Opcode: ORo /* 9807 */ MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 9833 /* 9812 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9815 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 9824 /* 9820 */ MCD_OPC_Decode, 240, 8, 111, // Opcode: NAND /* 9824 */ MCD_OPC_FilterValue, 1, 205, 25, 0, // Skip to: 16434 /* 9829 */ MCD_OPC_Decode, 243, 8, 111, // Opcode: NANDo /* 9833 */ MCD_OPC_FilterValue, 15, 196, 25, 0, // Skip to: 16434 /* 9838 */ MCD_OPC_CheckField, 0, 2, 0, 189, 25, 0, // Skip to: 16434 /* 9845 */ MCD_OPC_Decode, 165, 3, 111, // Opcode: CMPB /* 9849 */ MCD_OPC_FilterValue, 15, 180, 25, 0, // Skip to: 16434 /* 9854 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 9857 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 9897 /* 9862 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 9865 */ MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 9888 /* 9870 */ MCD_OPC_CheckField, 23, 3, 0, 157, 25, 0, // Skip to: 16434 /* 9877 */ MCD_OPC_CheckField, 11, 10, 0, 150, 25, 0, // Skip to: 16434 /* 9884 */ MCD_OPC_Decode, 224, 14, 104, // Opcode: WAIT /* 9888 */ MCD_OPC_FilterValue, 2, 141, 25, 0, // Skip to: 16434 /* 9893 */ MCD_OPC_Decode, 240, 7, 93, // Opcode: LWEPX /* 9897 */ MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 9920 /* 9902 */ MCD_OPC_CheckField, 21, 5, 0, 125, 25, 0, // Skip to: 16434 /* 9909 */ MCD_OPC_CheckField, 0, 2, 2, 118, 25, 0, // Skip to: 16434 /* 9916 */ MCD_OPC_Decode, 216, 3, 97, // Opcode: DCBSTEP /* 9920 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 9936 /* 9925 */ MCD_OPC_CheckField, 0, 2, 2, 102, 25, 0, // Skip to: 16434 /* 9932 */ MCD_OPC_Decode, 149, 7, 93, // Opcode: LBEPX /* 9936 */ MCD_OPC_FilterValue, 3, 18, 0, 0, // Skip to: 9959 /* 9941 */ MCD_OPC_CheckField, 21, 5, 0, 86, 25, 0, // Skip to: 16434 /* 9948 */ MCD_OPC_CheckField, 0, 2, 2, 79, 25, 0, // Skip to: 16434 /* 9955 */ MCD_OPC_Decode, 213, 3, 97, // Opcode: DCBFEP /* 9959 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 9975 /* 9964 */ MCD_OPC_CheckField, 0, 2, 2, 63, 25, 0, // Skip to: 16434 /* 9971 */ MCD_OPC_Decode, 222, 11, 93, // Opcode: STWEPX /* 9975 */ MCD_OPC_FilterValue, 6, 11, 0, 0, // Skip to: 9991 /* 9980 */ MCD_OPC_CheckField, 0, 2, 2, 47, 25, 0, // Skip to: 16434 /* 9987 */ MCD_OPC_Decode, 163, 11, 93, // Opcode: STBEPX /* 9991 */ MCD_OPC_FilterValue, 7, 11, 0, 0, // Skip to: 10007 /* 9996 */ MCD_OPC_CheckField, 0, 2, 2, 31, 25, 0, // Skip to: 16434 /* 10003 */ MCD_OPC_Decode, 220, 3, 118, // Opcode: DCBTSTEP /* 10007 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 10023 /* 10012 */ MCD_OPC_CheckField, 0, 2, 2, 15, 25, 0, // Skip to: 16434 /* 10019 */ MCD_OPC_Decode, 204, 7, 93, // Opcode: LHEPX /* 10023 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 10039 /* 10028 */ MCD_OPC_CheckField, 0, 2, 2, 255, 24, 0, // Skip to: 16434 /* 10035 */ MCD_OPC_Decode, 218, 3, 118, // Opcode: DCBTEP /* 10039 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 10055 /* 10044 */ MCD_OPC_CheckField, 0, 2, 2, 239, 24, 0, // Skip to: 16434 /* 10051 */ MCD_OPC_Decode, 198, 11, 93, // Opcode: STHEPX /* 10055 */ MCD_OPC_FilterValue, 18, 11, 0, 0, // Skip to: 10071 /* 10060 */ MCD_OPC_CheckField, 0, 2, 2, 223, 24, 0, // Skip to: 16434 /* 10067 */ MCD_OPC_Decode, 182, 7, 105, // Opcode: LFDEPX /* 10071 */ MCD_OPC_FilterValue, 22, 11, 0, 0, // Skip to: 10087 /* 10076 */ MCD_OPC_CheckField, 0, 2, 2, 207, 24, 0, // Skip to: 16434 /* 10083 */ MCD_OPC_Decode, 184, 11, 105, // Opcode: STFDEPX /* 10087 */ MCD_OPC_FilterValue, 30, 18, 0, 0, // Skip to: 10110 /* 10092 */ MCD_OPC_CheckField, 21, 5, 0, 191, 24, 0, // Skip to: 16434 /* 10099 */ MCD_OPC_CheckField, 0, 2, 2, 184, 24, 0, // Skip to: 16434 /* 10106 */ MCD_OPC_Decode, 137, 7, 97, // Opcode: ICBIEP /* 10110 */ MCD_OPC_FilterValue, 31, 175, 24, 0, // Skip to: 16434 /* 10115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... /* 10118 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 10134 /* 10123 */ MCD_OPC_CheckField, 0, 2, 2, 160, 24, 0, // Skip to: 16434 /* 10130 */ MCD_OPC_Decode, 222, 3, 97, // Opcode: DCBZEP /* 10134 */ MCD_OPC_FilterValue, 1, 151, 24, 0, // Skip to: 16434 /* 10139 */ MCD_OPC_CheckField, 0, 2, 2, 144, 24, 0, // Skip to: 16434 /* 10146 */ MCD_OPC_Decode, 224, 3, 97, // Opcode: DCBZLEP /* 10150 */ MCD_OPC_FilterValue, 32, 4, 0, 0, // Skip to: 10159 /* 10155 */ MCD_OPC_Decode, 241, 7, 119, // Opcode: LWZ /* 10159 */ MCD_OPC_FilterValue, 33, 4, 0, 0, // Skip to: 10168 /* 10164 */ MCD_OPC_Decode, 244, 7, 119, // Opcode: LWZU /* 10168 */ MCD_OPC_FilterValue, 34, 4, 0, 0, // Skip to: 10177 /* 10173 */ MCD_OPC_Decode, 150, 7, 119, // Opcode: LBZ /* 10177 */ MCD_OPC_FilterValue, 35, 4, 0, 0, // Skip to: 10186 /* 10182 */ MCD_OPC_Decode, 153, 7, 119, // Opcode: LBZU /* 10186 */ MCD_OPC_FilterValue, 36, 4, 0, 0, // Skip to: 10195 /* 10191 */ MCD_OPC_Decode, 216, 11, 119, // Opcode: STW /* 10195 */ MCD_OPC_FilterValue, 37, 4, 0, 0, // Skip to: 10204 /* 10200 */ MCD_OPC_Decode, 223, 11, 119, // Opcode: STWU /* 10204 */ MCD_OPC_FilterValue, 38, 4, 0, 0, // Skip to: 10213 /* 10209 */ MCD_OPC_Decode, 159, 11, 119, // Opcode: STB /* 10213 */ MCD_OPC_FilterValue, 39, 4, 0, 0, // Skip to: 10222 /* 10218 */ MCD_OPC_Decode, 164, 11, 119, // Opcode: STBU /* 10222 */ MCD_OPC_FilterValue, 40, 4, 0, 0, // Skip to: 10231 /* 10227 */ MCD_OPC_Decode, 205, 7, 119, // Opcode: LHZ /* 10231 */ MCD_OPC_FilterValue, 41, 4, 0, 0, // Skip to: 10240 /* 10236 */ MCD_OPC_Decode, 208, 7, 119, // Opcode: LHZU /* 10240 */ MCD_OPC_FilterValue, 42, 4, 0, 0, // Skip to: 10249 /* 10245 */ MCD_OPC_Decode, 192, 7, 119, // Opcode: LHA /* 10249 */ MCD_OPC_FilterValue, 43, 4, 0, 0, // Skip to: 10258 /* 10254 */ MCD_OPC_Decode, 196, 7, 119, // Opcode: LHAU /* 10258 */ MCD_OPC_FilterValue, 44, 4, 0, 0, // Skip to: 10267 /* 10263 */ MCD_OPC_Decode, 193, 11, 119, // Opcode: STH /* 10267 */ MCD_OPC_FilterValue, 45, 4, 0, 0, // Skip to: 10276 /* 10272 */ MCD_OPC_Decode, 199, 11, 119, // Opcode: STHU /* 10276 */ MCD_OPC_FilterValue, 46, 4, 0, 0, // Skip to: 10285 /* 10281 */ MCD_OPC_Decode, 221, 7, 119, // Opcode: LMW /* 10285 */ MCD_OPC_FilterValue, 47, 4, 0, 0, // Skip to: 10294 /* 10290 */ MCD_OPC_Decode, 208, 11, 119, // Opcode: STMW /* 10294 */ MCD_OPC_FilterValue, 48, 4, 0, 0, // Skip to: 10303 /* 10299 */ MCD_OPC_Decode, 188, 7, 120, // Opcode: LFS /* 10303 */ MCD_OPC_FilterValue, 49, 4, 0, 0, // Skip to: 10312 /* 10308 */ MCD_OPC_Decode, 189, 7, 120, // Opcode: LFSU /* 10312 */ MCD_OPC_FilterValue, 50, 4, 0, 0, // Skip to: 10321 /* 10317 */ MCD_OPC_Decode, 181, 7, 121, // Opcode: LFD /* 10321 */ MCD_OPC_FilterValue, 51, 4, 0, 0, // Skip to: 10330 /* 10326 */ MCD_OPC_Decode, 183, 7, 121, // Opcode: LFDU /* 10330 */ MCD_OPC_FilterValue, 52, 4, 0, 0, // Skip to: 10339 /* 10335 */ MCD_OPC_Decode, 189, 11, 120, // Opcode: STFS /* 10339 */ MCD_OPC_FilterValue, 53, 4, 0, 0, // Skip to: 10348 /* 10344 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: STFSU /* 10348 */ MCD_OPC_FilterValue, 54, 4, 0, 0, // Skip to: 10357 /* 10353 */ MCD_OPC_Decode, 183, 11, 121, // Opcode: STFD /* 10357 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 10366 /* 10362 */ MCD_OPC_Decode, 185, 11, 121, // Opcode: STFDU /* 10366 */ MCD_OPC_FilterValue, 57, 21, 0, 0, // Skip to: 10392 /* 10371 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 10374 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 10383 /* 10379 */ MCD_OPC_Decode, 254, 7, 122, // Opcode: LXSD /* 10383 */ MCD_OPC_FilterValue, 3, 158, 23, 0, // Skip to: 16434 /* 10388 */ MCD_OPC_Decode, 132, 8, 122, // Opcode: LXSSP /* 10392 */ MCD_OPC_FilterValue, 58, 30, 0, 0, // Skip to: 10427 /* 10397 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 10400 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 10409 /* 10405 */ MCD_OPC_Decode, 162, 7, 123, // Opcode: LD /* 10409 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 10418 /* 10414 */ MCD_OPC_Decode, 169, 7, 123, // Opcode: LDU /* 10418 */ MCD_OPC_FilterValue, 2, 123, 23, 0, // Skip to: 16434 /* 10423 */ MCD_OPC_Decode, 230, 7, 123, // Opcode: LWA /* 10427 */ MCD_OPC_FilterValue, 59, 173, 1, 0, // Skip to: 10861 /* 10432 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 10435 */ MCD_OPC_FilterValue, 28, 35, 0, 0, // Skip to: 10475 /* 10440 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 10443 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 10459 /* 10448 */ MCD_OPC_CheckField, 16, 5, 0, 91, 23, 0, // Skip to: 16434 /* 10455 */ MCD_OPC_Decode, 156, 6, 124, // Opcode: FCFIDS /* 10459 */ MCD_OPC_FilterValue, 30, 82, 23, 0, // Skip to: 16434 /* 10464 */ MCD_OPC_CheckField, 16, 5, 0, 75, 23, 0, // Skip to: 16434 /* 10471 */ MCD_OPC_Decode, 159, 6, 124, // Opcode: FCFIDUS /* 10475 */ MCD_OPC_FilterValue, 29, 35, 0, 0, // Skip to: 10515 /* 10480 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 10483 */ MCD_OPC_FilterValue, 26, 11, 0, 0, // Skip to: 10499 /* 10488 */ MCD_OPC_CheckField, 16, 5, 0, 51, 23, 0, // Skip to: 16434 /* 10495 */ MCD_OPC_Decode, 157, 6, 124, // Opcode: FCFIDSo /* 10499 */ MCD_OPC_FilterValue, 30, 42, 23, 0, // Skip to: 16434 /* 10504 */ MCD_OPC_CheckField, 16, 5, 0, 35, 23, 0, // Skip to: 16434 /* 10511 */ MCD_OPC_Decode, 160, 6, 124, // Opcode: FCFIDUSo /* 10515 */ MCD_OPC_FilterValue, 36, 11, 0, 0, // Skip to: 10531 /* 10520 */ MCD_OPC_CheckField, 6, 5, 0, 19, 23, 0, // Skip to: 16434 /* 10527 */ MCD_OPC_Decode, 186, 6, 125, // Opcode: FDIVS /* 10531 */ MCD_OPC_FilterValue, 37, 11, 0, 0, // Skip to: 10547 /* 10536 */ MCD_OPC_CheckField, 6, 5, 0, 3, 23, 0, // Skip to: 16434 /* 10543 */ MCD_OPC_Decode, 187, 6, 125, // Opcode: FDIVSo /* 10547 */ MCD_OPC_FilterValue, 40, 11, 0, 0, // Skip to: 10563 /* 10552 */ MCD_OPC_CheckField, 6, 5, 0, 243, 22, 0, // Skip to: 16434 /* 10559 */ MCD_OPC_Decode, 254, 6, 125, // Opcode: FSUBS /* 10563 */ MCD_OPC_FilterValue, 41, 11, 0, 0, // Skip to: 10579 /* 10568 */ MCD_OPC_CheckField, 6, 5, 0, 227, 22, 0, // Skip to: 16434 /* 10575 */ MCD_OPC_Decode, 255, 6, 125, // Opcode: FSUBSo /* 10579 */ MCD_OPC_FilterValue, 42, 11, 0, 0, // Skip to: 10595 /* 10584 */ MCD_OPC_CheckField, 6, 5, 0, 211, 22, 0, // Skip to: 16434 /* 10591 */ MCD_OPC_Decode, 151, 6, 125, // Opcode: FADDS /* 10595 */ MCD_OPC_FilterValue, 43, 11, 0, 0, // Skip to: 10611 /* 10600 */ MCD_OPC_CheckField, 6, 5, 0, 195, 22, 0, // Skip to: 16434 /* 10607 */ MCD_OPC_Decode, 152, 6, 125, // Opcode: FADDSo /* 10611 */ MCD_OPC_FilterValue, 44, 18, 0, 0, // Skip to: 10634 /* 10616 */ MCD_OPC_CheckField, 16, 5, 0, 179, 22, 0, // Skip to: 16434 /* 10623 */ MCD_OPC_CheckField, 6, 5, 0, 172, 22, 0, // Skip to: 16434 /* 10630 */ MCD_OPC_Decode, 250, 6, 126, // Opcode: FSQRTS /* 10634 */ MCD_OPC_FilterValue, 45, 18, 0, 0, // Skip to: 10657 /* 10639 */ MCD_OPC_CheckField, 16, 5, 0, 156, 22, 0, // Skip to: 16434 /* 10646 */ MCD_OPC_CheckField, 6, 5, 0, 149, 22, 0, // Skip to: 16434 /* 10653 */ MCD_OPC_Decode, 251, 6, 126, // Opcode: FSQRTSo /* 10657 */ MCD_OPC_FilterValue, 48, 18, 0, 0, // Skip to: 10680 /* 10662 */ MCD_OPC_CheckField, 16, 5, 0, 133, 22, 0, // Skip to: 16434 /* 10669 */ MCD_OPC_CheckField, 6, 5, 0, 126, 22, 0, // Skip to: 16434 /* 10676 */ MCD_OPC_Decode, 220, 6, 126, // Opcode: FRES /* 10680 */ MCD_OPC_FilterValue, 49, 18, 0, 0, // Skip to: 10703 /* 10685 */ MCD_OPC_CheckField, 16, 5, 0, 110, 22, 0, // Skip to: 16434 /* 10692 */ MCD_OPC_CheckField, 6, 5, 0, 103, 22, 0, // Skip to: 16434 /* 10699 */ MCD_OPC_Decode, 221, 6, 126, // Opcode: FRESo /* 10703 */ MCD_OPC_FilterValue, 50, 11, 0, 0, // Skip to: 10719 /* 10708 */ MCD_OPC_CheckField, 11, 5, 0, 87, 22, 0, // Skip to: 16434 /* 10715 */ MCD_OPC_Decode, 200, 6, 127, // Opcode: FMULS /* 10719 */ MCD_OPC_FilterValue, 51, 11, 0, 0, // Skip to: 10735 /* 10724 */ MCD_OPC_CheckField, 11, 5, 0, 71, 22, 0, // Skip to: 16434 /* 10731 */ MCD_OPC_Decode, 201, 6, 127, // Opcode: FMULSo /* 10735 */ MCD_OPC_FilterValue, 52, 18, 0, 0, // Skip to: 10758 /* 10740 */ MCD_OPC_CheckField, 16, 5, 0, 55, 22, 0, // Skip to: 16434 /* 10747 */ MCD_OPC_CheckField, 6, 5, 0, 48, 22, 0, // Skip to: 16434 /* 10754 */ MCD_OPC_Decode, 242, 6, 126, // Opcode: FRSQRTES /* 10758 */ MCD_OPC_FilterValue, 53, 18, 0, 0, // Skip to: 10781 /* 10763 */ MCD_OPC_CheckField, 16, 5, 0, 32, 22, 0, // Skip to: 16434 /* 10770 */ MCD_OPC_CheckField, 6, 5, 0, 25, 22, 0, // Skip to: 16434 /* 10777 */ MCD_OPC_Decode, 243, 6, 126, // Opcode: FRSQRTESo /* 10781 */ MCD_OPC_FilterValue, 56, 5, 0, 0, // Skip to: 10791 /* 10786 */ MCD_OPC_Decode, 196, 6, 128, 1, // Opcode: FMSUBS /* 10791 */ MCD_OPC_FilterValue, 57, 5, 0, 0, // Skip to: 10801 /* 10796 */ MCD_OPC_Decode, 197, 6, 128, 1, // Opcode: FMSUBSo /* 10801 */ MCD_OPC_FilterValue, 58, 5, 0, 0, // Skip to: 10811 /* 10806 */ MCD_OPC_Decode, 190, 6, 128, 1, // Opcode: FMADDS /* 10811 */ MCD_OPC_FilterValue, 59, 5, 0, 0, // Skip to: 10821 /* 10816 */ MCD_OPC_Decode, 191, 6, 128, 1, // Opcode: FMADDSo /* 10821 */ MCD_OPC_FilterValue, 60, 5, 0, 0, // Skip to: 10831 /* 10826 */ MCD_OPC_Decode, 216, 6, 128, 1, // Opcode: FNMSUBS /* 10831 */ MCD_OPC_FilterValue, 61, 5, 0, 0, // Skip to: 10841 /* 10836 */ MCD_OPC_Decode, 217, 6, 128, 1, // Opcode: FNMSUBSo /* 10841 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 10851 /* 10846 */ MCD_OPC_Decode, 212, 6, 128, 1, // Opcode: FNMADDS /* 10851 */ MCD_OPC_FilterValue, 63, 202, 21, 0, // Skip to: 16434 /* 10856 */ MCD_OPC_Decode, 213, 6, 128, 1, // Opcode: FNMADDSo /* 10861 */ MCD_OPC_FilterValue, 60, 242, 13, 0, // Skip to: 14436 /* 10866 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... /* 10869 */ MCD_OPC_FilterValue, 0, 120, 3, 0, // Skip to: 11762 /* 10874 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 10877 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 10905 /* 10882 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 10885 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10895 /* 10890 */ MCD_OPC_Decode, 240, 14, 129, 1, // Opcode: XSADDSP /* 10895 */ MCD_OPC_FilterValue, 1, 158, 21, 0, // Skip to: 16434 /* 10900 */ MCD_OPC_Decode, 158, 15, 130, 1, // Opcode: XSMADDASP /* 10905 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 10933 /* 10910 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 10913 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10923 /* 10918 */ MCD_OPC_Decode, 215, 15, 129, 1, // Opcode: XSSUBSP /* 10923 */ MCD_OPC_FilterValue, 1, 130, 21, 0, // Skip to: 16434 /* 10928 */ MCD_OPC_Decode, 160, 15, 130, 1, // Opcode: XSMADDMSP /* 10933 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 10961 /* 10938 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 10941 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10951 /* 10946 */ MCD_OPC_Decode, 178, 15, 129, 1, // Opcode: XSMULSP /* 10951 */ MCD_OPC_FilterValue, 1, 102, 21, 0, // Skip to: 16434 /* 10956 */ MCD_OPC_Decode, 170, 15, 130, 1, // Opcode: XSMSUBASP /* 10961 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 10989 /* 10966 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 10969 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 10979 /* 10974 */ MCD_OPC_Decode, 154, 15, 129, 1, // Opcode: XSDIVSP /* 10979 */ MCD_OPC_FilterValue, 1, 74, 21, 0, // Skip to: 16434 /* 10984 */ MCD_OPC_Decode, 172, 15, 130, 1, // Opcode: XSMSUBMSP /* 10989 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 11017 /* 10994 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 10997 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11007 /* 11002 */ MCD_OPC_Decode, 237, 14, 131, 1, // Opcode: XSADDDP /* 11007 */ MCD_OPC_FilterValue, 1, 46, 21, 0, // Skip to: 16434 /* 11012 */ MCD_OPC_Decode, 157, 15, 132, 1, // Opcode: XSMADDADP /* 11017 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 11045 /* 11022 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11025 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11035 /* 11030 */ MCD_OPC_Decode, 212, 15, 131, 1, // Opcode: XSSUBDP /* 11035 */ MCD_OPC_FilterValue, 1, 18, 21, 0, // Skip to: 16434 /* 11040 */ MCD_OPC_Decode, 159, 15, 132, 1, // Opcode: XSMADDMDP /* 11045 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 11073 /* 11050 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11053 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11063 /* 11058 */ MCD_OPC_Decode, 175, 15, 131, 1, // Opcode: XSMULDP /* 11063 */ MCD_OPC_FilterValue, 1, 246, 20, 0, // Skip to: 16434 /* 11068 */ MCD_OPC_Decode, 169, 15, 132, 1, // Opcode: XSMSUBADP /* 11073 */ MCD_OPC_FilterValue, 7, 23, 0, 0, // Skip to: 11101 /* 11078 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11081 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11091 /* 11086 */ MCD_OPC_Decode, 151, 15, 131, 1, // Opcode: XSDIVDP /* 11091 */ MCD_OPC_FilterValue, 1, 218, 20, 0, // Skip to: 16434 /* 11096 */ MCD_OPC_Decode, 171, 15, 132, 1, // Opcode: XSMSUBMDP /* 11101 */ MCD_OPC_FilterValue, 8, 23, 0, 0, // Skip to: 11129 /* 11106 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11109 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11119 /* 11114 */ MCD_OPC_Decode, 228, 15, 133, 1, // Opcode: XVADDSP /* 11119 */ MCD_OPC_FilterValue, 1, 190, 20, 0, // Skip to: 16434 /* 11124 */ MCD_OPC_Decode, 140, 16, 134, 1, // Opcode: XVMADDASP /* 11129 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 11157 /* 11134 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11137 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11147 /* 11142 */ MCD_OPC_Decode, 182, 16, 133, 1, // Opcode: XVSUBSP /* 11147 */ MCD_OPC_FilterValue, 1, 162, 20, 0, // Skip to: 16434 /* 11152 */ MCD_OPC_Decode, 142, 16, 134, 1, // Opcode: XVMADDMSP /* 11157 */ MCD_OPC_FilterValue, 10, 23, 0, 0, // Skip to: 11185 /* 11162 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11165 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11175 /* 11170 */ MCD_OPC_Decode, 152, 16, 133, 1, // Opcode: XVMULSP /* 11175 */ MCD_OPC_FilterValue, 1, 134, 20, 0, // Skip to: 16434 /* 11180 */ MCD_OPC_Decode, 148, 16, 134, 1, // Opcode: XVMSUBASP /* 11185 */ MCD_OPC_FilterValue, 11, 23, 0, 0, // Skip to: 11213 /* 11190 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11193 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11203 /* 11198 */ MCD_OPC_Decode, 136, 16, 133, 1, // Opcode: XVDIVSP /* 11203 */ MCD_OPC_FilterValue, 1, 106, 20, 0, // Skip to: 16434 /* 11208 */ MCD_OPC_Decode, 150, 16, 134, 1, // Opcode: XVMSUBMSP /* 11213 */ MCD_OPC_FilterValue, 12, 23, 0, 0, // Skip to: 11241 /* 11218 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11221 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11231 /* 11226 */ MCD_OPC_Decode, 227, 15, 133, 1, // Opcode: XVADDDP /* 11231 */ MCD_OPC_FilterValue, 1, 78, 20, 0, // Skip to: 16434 /* 11236 */ MCD_OPC_Decode, 139, 16, 134, 1, // Opcode: XVMADDADP /* 11241 */ MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 11269 /* 11246 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11249 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11259 /* 11254 */ MCD_OPC_Decode, 181, 16, 133, 1, // Opcode: XVSUBDP /* 11259 */ MCD_OPC_FilterValue, 1, 50, 20, 0, // Skip to: 16434 /* 11264 */ MCD_OPC_Decode, 141, 16, 134, 1, // Opcode: XVMADDMDP /* 11269 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 11297 /* 11274 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11277 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11287 /* 11282 */ MCD_OPC_Decode, 151, 16, 133, 1, // Opcode: XVMULDP /* 11287 */ MCD_OPC_FilterValue, 1, 22, 20, 0, // Skip to: 16434 /* 11292 */ MCD_OPC_Decode, 147, 16, 134, 1, // Opcode: XVMSUBADP /* 11297 */ MCD_OPC_FilterValue, 15, 23, 0, 0, // Skip to: 11325 /* 11302 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11305 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11315 /* 11310 */ MCD_OPC_Decode, 135, 16, 133, 1, // Opcode: XVDIVDP /* 11315 */ MCD_OPC_FilterValue, 1, 250, 19, 0, // Skip to: 16434 /* 11320 */ MCD_OPC_Decode, 149, 16, 134, 1, // Opcode: XVMSUBMDP /* 11325 */ MCD_OPC_FilterValue, 16, 23, 0, 0, // Skip to: 11353 /* 11330 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11333 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11343 /* 11338 */ MCD_OPC_Decode, 163, 15, 135, 1, // Opcode: XSMAXCDP /* 11343 */ MCD_OPC_FilterValue, 1, 222, 19, 0, // Skip to: 16434 /* 11348 */ MCD_OPC_Decode, 184, 15, 130, 1, // Opcode: XSNMADDASP /* 11353 */ MCD_OPC_FilterValue, 17, 23, 0, 0, // Skip to: 11381 /* 11358 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11361 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11371 /* 11366 */ MCD_OPC_Decode, 166, 15, 135, 1, // Opcode: XSMINCDP /* 11371 */ MCD_OPC_FilterValue, 1, 194, 19, 0, // Skip to: 16434 /* 11376 */ MCD_OPC_Decode, 186, 15, 130, 1, // Opcode: XSNMADDMSP /* 11381 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 11409 /* 11386 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11389 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11399 /* 11394 */ MCD_OPC_Decode, 165, 15, 135, 1, // Opcode: XSMAXJDP /* 11399 */ MCD_OPC_FilterValue, 1, 166, 19, 0, // Skip to: 16434 /* 11404 */ MCD_OPC_Decode, 190, 15, 130, 1, // Opcode: XSNMSUBASP /* 11409 */ MCD_OPC_FilterValue, 19, 23, 0, 0, // Skip to: 11437 /* 11414 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11417 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11427 /* 11422 */ MCD_OPC_Decode, 168, 15, 135, 1, // Opcode: XSMINJDP /* 11427 */ MCD_OPC_FilterValue, 1, 138, 19, 0, // Skip to: 16434 /* 11432 */ MCD_OPC_Decode, 192, 15, 130, 1, // Opcode: XSNMSUBMSP /* 11437 */ MCD_OPC_FilterValue, 20, 23, 0, 0, // Skip to: 11465 /* 11442 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11445 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11455 /* 11450 */ MCD_OPC_Decode, 164, 15, 131, 1, // Opcode: XSMAXDP /* 11455 */ MCD_OPC_FilterValue, 1, 110, 19, 0, // Skip to: 16434 /* 11460 */ MCD_OPC_Decode, 183, 15, 132, 1, // Opcode: XSNMADDADP /* 11465 */ MCD_OPC_FilterValue, 21, 23, 0, 0, // Skip to: 11493 /* 11470 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11473 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11483 /* 11478 */ MCD_OPC_Decode, 167, 15, 131, 1, // Opcode: XSMINDP /* 11483 */ MCD_OPC_FilterValue, 1, 82, 19, 0, // Skip to: 16434 /* 11488 */ MCD_OPC_Decode, 185, 15, 132, 1, // Opcode: XSNMADDMDP /* 11493 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 11521 /* 11498 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11501 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11511 /* 11506 */ MCD_OPC_Decode, 250, 14, 131, 1, // Opcode: XSCPSGNDP /* 11511 */ MCD_OPC_FilterValue, 1, 54, 19, 0, // Skip to: 16434 /* 11516 */ MCD_OPC_Decode, 189, 15, 132, 1, // Opcode: XSNMSUBADP /* 11521 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 11538 /* 11526 */ MCD_OPC_CheckField, 3, 1, 1, 37, 19, 0, // Skip to: 16434 /* 11533 */ MCD_OPC_Decode, 191, 15, 132, 1, // Opcode: XSNMSUBMDP /* 11538 */ MCD_OPC_FilterValue, 24, 23, 0, 0, // Skip to: 11566 /* 11543 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11546 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11556 /* 11551 */ MCD_OPC_Decode, 144, 16, 133, 1, // Opcode: XVMAXSP /* 11556 */ MCD_OPC_FilterValue, 1, 9, 19, 0, // Skip to: 16434 /* 11561 */ MCD_OPC_Decode, 158, 16, 134, 1, // Opcode: XVNMADDASP /* 11566 */ MCD_OPC_FilterValue, 25, 23, 0, 0, // Skip to: 11594 /* 11571 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11574 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11584 /* 11579 */ MCD_OPC_Decode, 146, 16, 133, 1, // Opcode: XVMINSP /* 11584 */ MCD_OPC_FilterValue, 1, 237, 18, 0, // Skip to: 16434 /* 11589 */ MCD_OPC_Decode, 160, 16, 134, 1, // Opcode: XVNMADDMSP /* 11594 */ MCD_OPC_FilterValue, 26, 23, 0, 0, // Skip to: 11622 /* 11599 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11602 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11612 /* 11607 */ MCD_OPC_Decode, 242, 15, 133, 1, // Opcode: XVCPSGNSP /* 11612 */ MCD_OPC_FilterValue, 1, 209, 18, 0, // Skip to: 16434 /* 11617 */ MCD_OPC_Decode, 162, 16, 134, 1, // Opcode: XVNMSUBASP /* 11622 */ MCD_OPC_FilterValue, 27, 23, 0, 0, // Skip to: 11650 /* 11627 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11630 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11640 /* 11635 */ MCD_OPC_Decode, 138, 16, 133, 1, // Opcode: XVIEXPSP /* 11640 */ MCD_OPC_FilterValue, 1, 181, 18, 0, // Skip to: 16434 /* 11645 */ MCD_OPC_Decode, 164, 16, 134, 1, // Opcode: XVNMSUBMSP /* 11650 */ MCD_OPC_FilterValue, 28, 23, 0, 0, // Skip to: 11678 /* 11655 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11658 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11668 /* 11663 */ MCD_OPC_Decode, 143, 16, 133, 1, // Opcode: XVMAXDP /* 11668 */ MCD_OPC_FilterValue, 1, 153, 18, 0, // Skip to: 16434 /* 11673 */ MCD_OPC_Decode, 157, 16, 134, 1, // Opcode: XVNMADDADP /* 11678 */ MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 11706 /* 11683 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11686 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11696 /* 11691 */ MCD_OPC_Decode, 145, 16, 133, 1, // Opcode: XVMINDP /* 11696 */ MCD_OPC_FilterValue, 1, 125, 18, 0, // Skip to: 16434 /* 11701 */ MCD_OPC_Decode, 159, 16, 134, 1, // Opcode: XVNMADDMDP /* 11706 */ MCD_OPC_FilterValue, 30, 23, 0, 0, // Skip to: 11734 /* 11711 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11714 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11724 /* 11719 */ MCD_OPC_Decode, 241, 15, 133, 1, // Opcode: XVCPSGNDP /* 11724 */ MCD_OPC_FilterValue, 1, 97, 18, 0, // Skip to: 16434 /* 11729 */ MCD_OPC_Decode, 161, 16, 134, 1, // Opcode: XVNMSUBADP /* 11734 */ MCD_OPC_FilterValue, 31, 87, 18, 0, // Skip to: 16434 /* 11739 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11742 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11752 /* 11747 */ MCD_OPC_Decode, 137, 16, 133, 1, // Opcode: XVIEXPDP /* 11752 */ MCD_OPC_FilterValue, 1, 69, 18, 0, // Skip to: 16434 /* 11757 */ MCD_OPC_Decode, 163, 16, 134, 1, // Opcode: XVNMSUBMDP /* 11762 */ MCD_OPC_FilterValue, 1, 97, 2, 0, // Skip to: 12376 /* 11767 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... /* 11770 */ MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 11906 /* 11775 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11778 */ MCD_OPC_FilterValue, 0, 41, 0, 0, // Skip to: 11824 /* 11783 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 11786 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11796 /* 11791 */ MCD_OPC_Decode, 218, 16, 136, 1, // Opcode: XXSLDWI /* 11796 */ MCD_OPC_FilterValue, 1, 25, 18, 0, // Skip to: 16434 /* 11801 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 11804 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11814 /* 11809 */ MCD_OPC_Decode, 199, 16, 133, 1, // Opcode: XXLAND /* 11814 */ MCD_OPC_FilterValue, 1, 7, 18, 0, // Skip to: 16434 /* 11819 */ MCD_OPC_Decode, 203, 16, 133, 1, // Opcode: XXLNOR /* 11824 */ MCD_OPC_FilterValue, 1, 253, 17, 0, // Skip to: 16434 /* 11829 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 11832 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11842 /* 11837 */ MCD_OPC_Decode, 241, 14, 135, 1, // Opcode: XSCMPEQDP /* 11842 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 11866 /* 11847 */ MCD_OPC_CheckField, 21, 2, 0, 228, 17, 0, // Skip to: 16434 /* 11854 */ MCD_OPC_CheckField, 0, 1, 0, 221, 17, 0, // Skip to: 16434 /* 11861 */ MCD_OPC_Decode, 248, 14, 137, 1, // Opcode: XSCMPUDP /* 11866 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 11876 /* 11871 */ MCD_OPC_Decode, 231, 15, 133, 1, // Opcode: XVCMPEQSP /* 11876 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 11886 /* 11881 */ MCD_OPC_Decode, 229, 15, 133, 1, // Opcode: XVCMPEQDP /* 11886 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 11896 /* 11891 */ MCD_OPC_Decode, 232, 15, 133, 1, // Opcode: XVCMPEQSPo /* 11896 */ MCD_OPC_FilterValue, 7, 181, 17, 0, // Skip to: 16434 /* 11901 */ MCD_OPC_Decode, 230, 15, 133, 1, // Opcode: XVCMPEQDPo /* 11906 */ MCD_OPC_FilterValue, 1, 131, 0, 0, // Skip to: 12042 /* 11911 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 11914 */ MCD_OPC_FilterValue, 0, 41, 0, 0, // Skip to: 11960 /* 11919 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 11922 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11932 /* 11927 */ MCD_OPC_Decode, 214, 16, 136, 1, // Opcode: XXPERMDI /* 11932 */ MCD_OPC_FilterValue, 1, 145, 17, 0, // Skip to: 16434 /* 11937 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 11940 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11950 /* 11945 */ MCD_OPC_Decode, 200, 16, 133, 1, // Opcode: XXLANDC /* 11950 */ MCD_OPC_FilterValue, 1, 127, 17, 0, // Skip to: 16434 /* 11955 */ MCD_OPC_Decode, 205, 16, 133, 1, // Opcode: XXLORC /* 11960 */ MCD_OPC_FilterValue, 1, 117, 17, 0, // Skip to: 16434 /* 11965 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 11968 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 11978 /* 11973 */ MCD_OPC_Decode, 245, 14, 135, 1, // Opcode: XSCMPGTDP /* 11978 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 12002 /* 11983 */ MCD_OPC_CheckField, 21, 2, 0, 92, 17, 0, // Skip to: 16434 /* 11990 */ MCD_OPC_CheckField, 0, 1, 0, 85, 17, 0, // Skip to: 16434 /* 11997 */ MCD_OPC_Decode, 246, 14, 137, 1, // Opcode: XSCMPODP /* 12002 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 12012 /* 12007 */ MCD_OPC_Decode, 239, 15, 133, 1, // Opcode: XVCMPGTSP /* 12012 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 12022 /* 12017 */ MCD_OPC_Decode, 237, 15, 133, 1, // Opcode: XVCMPGTDP /* 12022 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 12032 /* 12027 */ MCD_OPC_Decode, 240, 15, 133, 1, // Opcode: XVCMPGTSPo /* 12032 */ MCD_OPC_FilterValue, 7, 45, 17, 0, // Skip to: 16434 /* 12037 */ MCD_OPC_Decode, 238, 15, 133, 1, // Opcode: XVCMPGTDPo /* 12042 */ MCD_OPC_FilterValue, 2, 186, 0, 0, // Skip to: 12233 /* 12047 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 12050 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 12078 /* 12055 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 12058 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 12068 /* 12063 */ MCD_OPC_Decode, 211, 16, 133, 1, // Opcode: XXMRGHW /* 12068 */ MCD_OPC_FilterValue, 1, 9, 17, 0, // Skip to: 16434 /* 12073 */ MCD_OPC_Decode, 244, 14, 135, 1, // Opcode: XSCMPGEDP /* 12078 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 12095 /* 12083 */ MCD_OPC_CheckField, 3, 1, 0, 248, 16, 0, // Skip to: 16434 /* 12090 */ MCD_OPC_Decode, 212, 16, 133, 1, // Opcode: XXMRGLW /* 12095 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 12148 /* 12100 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 12103 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 12138 /* 12108 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 12111 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12128 /* 12116 */ MCD_OPC_CheckField, 18, 3, 0, 215, 16, 0, // Skip to: 16434 /* 12123 */ MCD_OPC_Decode, 221, 16, 138, 1, // Opcode: XXSPLTW /* 12128 */ MCD_OPC_FilterValue, 1, 205, 16, 0, // Skip to: 16434 /* 12133 */ MCD_OPC_Decode, 197, 16, 139, 1, // Opcode: XXEXTRACTUW /* 12138 */ MCD_OPC_FilterValue, 1, 195, 16, 0, // Skip to: 16434 /* 12143 */ MCD_OPC_Decode, 235, 15, 133, 1, // Opcode: XVCMPGESP /* 12148 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 12165 /* 12153 */ MCD_OPC_CheckField, 3, 1, 1, 178, 16, 0, // Skip to: 16434 /* 12160 */ MCD_OPC_Decode, 233, 15, 133, 1, // Opcode: XVCMPGEDP /* 12165 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 12182 /* 12170 */ MCD_OPC_CheckField, 3, 1, 0, 161, 16, 0, // Skip to: 16434 /* 12177 */ MCD_OPC_Decode, 204, 16, 133, 1, // Opcode: XXLOR /* 12182 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 12199 /* 12187 */ MCD_OPC_CheckField, 3, 1, 0, 144, 16, 0, // Skip to: 16434 /* 12194 */ MCD_OPC_Decode, 202, 16, 133, 1, // Opcode: XXLNAND /* 12199 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 12216 /* 12204 */ MCD_OPC_CheckField, 3, 1, 1, 127, 16, 0, // Skip to: 16434 /* 12211 */ MCD_OPC_Decode, 236, 15, 133, 1, // Opcode: XVCMPGESPo /* 12216 */ MCD_OPC_FilterValue, 7, 117, 16, 0, // Skip to: 16434 /* 12221 */ MCD_OPC_CheckField, 3, 1, 1, 110, 16, 0, // Skip to: 16434 /* 12228 */ MCD_OPC_Decode, 234, 15, 133, 1, // Opcode: XVCMPGEDPo /* 12233 */ MCD_OPC_FilterValue, 3, 100, 16, 0, // Skip to: 16434 /* 12238 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 12241 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12258 /* 12246 */ MCD_OPC_CheckField, 3, 1, 0, 85, 16, 0, // Skip to: 16434 /* 12253 */ MCD_OPC_Decode, 213, 16, 133, 1, // Opcode: XXPERM /* 12258 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 12300 /* 12263 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 12266 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 12276 /* 12271 */ MCD_OPC_Decode, 216, 16, 133, 1, // Opcode: XXPERMR /* 12276 */ MCD_OPC_FilterValue, 1, 57, 16, 0, // Skip to: 16434 /* 12281 */ MCD_OPC_CheckField, 21, 2, 0, 50, 16, 0, // Skip to: 16434 /* 12288 */ MCD_OPC_CheckField, 0, 1, 0, 43, 16, 0, // Skip to: 16434 /* 12295 */ MCD_OPC_Decode, 242, 14, 137, 1, // Opcode: XSCMPEXPDP /* 12300 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12342 /* 12305 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 12308 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12332 /* 12313 */ MCD_OPC_CheckField, 19, 2, 0, 18, 16, 0, // Skip to: 16434 /* 12320 */ MCD_OPC_CheckField, 1, 1, 0, 11, 16, 0, // Skip to: 16434 /* 12327 */ MCD_OPC_Decode, 220, 16, 140, 1, // Opcode: XXSPLTIB /* 12332 */ MCD_OPC_FilterValue, 1, 1, 16, 0, // Skip to: 16434 /* 12337 */ MCD_OPC_Decode, 198, 16, 141, 1, // Opcode: XXINSERTW /* 12342 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 12359 /* 12347 */ MCD_OPC_CheckField, 3, 1, 0, 240, 15, 0, // Skip to: 16434 /* 12354 */ MCD_OPC_Decode, 207, 16, 133, 1, // Opcode: XXLXOR /* 12359 */ MCD_OPC_FilterValue, 5, 230, 15, 0, // Skip to: 16434 /* 12364 */ MCD_OPC_CheckField, 3, 1, 0, 223, 15, 0, // Skip to: 16434 /* 12371 */ MCD_OPC_Decode, 201, 16, 133, 1, // Opcode: XXLEQV /* 12376 */ MCD_OPC_FilterValue, 2, 253, 7, 0, // Skip to: 14426 /* 12381 */ MCD_OPC_ExtractField, 7, 4, // Inst{10-7} ... /* 12384 */ MCD_OPC_FilterValue, 0, 69, 0, 0, // Skip to: 12458 /* 12389 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 12392 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12434 /* 12397 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12400 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12417 /* 12405 */ MCD_OPC_CheckField, 16, 5, 0, 182, 15, 0, // Skip to: 16434 /* 12412 */ MCD_OPC_Decode, 207, 15, 142, 1, // Opcode: XSRSQRTESP /* 12417 */ MCD_OPC_FilterValue, 1, 172, 15, 0, // Skip to: 16434 /* 12422 */ MCD_OPC_CheckField, 16, 5, 0, 165, 15, 0, // Skip to: 16434 /* 12429 */ MCD_OPC_Decode, 201, 15, 142, 1, // Opcode: XSRESP /* 12434 */ MCD_OPC_FilterValue, 3, 155, 15, 0, // Skip to: 16434 /* 12439 */ MCD_OPC_CheckField, 16, 5, 0, 148, 15, 0, // Skip to: 16434 /* 12446 */ MCD_OPC_CheckField, 6, 1, 0, 141, 15, 0, // Skip to: 16434 /* 12453 */ MCD_OPC_Decode, 211, 15, 142, 1, // Opcode: XSSQRTSP /* 12458 */ MCD_OPC_FilterValue, 2, 153, 0, 0, // Skip to: 12616 /* 12463 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 12466 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 12508 /* 12471 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12474 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12491 /* 12479 */ MCD_OPC_CheckField, 16, 5, 0, 108, 15, 0, // Skip to: 16434 /* 12486 */ MCD_OPC_Decode, 134, 15, 143, 1, // Opcode: XSCVDPUXWS /* 12491 */ MCD_OPC_FilterValue, 1, 98, 15, 0, // Skip to: 16434 /* 12496 */ MCD_OPC_CheckField, 16, 5, 0, 91, 15, 0, // Skip to: 16434 /* 12503 */ MCD_OPC_Decode, 130, 15, 143, 1, // Opcode: XSCVDPSXWS /* 12508 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 12550 /* 12513 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12516 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12533 /* 12521 */ MCD_OPC_CheckField, 16, 5, 0, 66, 15, 0, // Skip to: 16434 /* 12528 */ MCD_OPC_Decode, 195, 15, 143, 1, // Opcode: XSRDPI /* 12533 */ MCD_OPC_FilterValue, 1, 56, 15, 0, // Skip to: 16434 /* 12538 */ MCD_OPC_CheckField, 16, 5, 0, 49, 15, 0, // Skip to: 16434 /* 12545 */ MCD_OPC_Decode, 199, 15, 143, 1, // Opcode: XSRDPIZ /* 12550 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12592 /* 12555 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12558 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12575 /* 12563 */ MCD_OPC_CheckField, 16, 5, 0, 24, 15, 0, // Skip to: 16434 /* 12570 */ MCD_OPC_Decode, 206, 15, 143, 1, // Opcode: XSRSQRTEDP /* 12575 */ MCD_OPC_FilterValue, 1, 14, 15, 0, // Skip to: 16434 /* 12580 */ MCD_OPC_CheckField, 16, 5, 0, 7, 15, 0, // Skip to: 16434 /* 12587 */ MCD_OPC_Decode, 200, 15, 143, 1, // Opcode: XSREDP /* 12592 */ MCD_OPC_FilterValue, 3, 253, 14, 0, // Skip to: 16434 /* 12597 */ MCD_OPC_CheckField, 16, 5, 0, 246, 14, 0, // Skip to: 16434 /* 12604 */ MCD_OPC_CheckField, 6, 1, 0, 239, 14, 0, // Skip to: 16434 /* 12611 */ MCD_OPC_Decode, 208, 15, 143, 1, // Opcode: XSSQRTDP /* 12616 */ MCD_OPC_FilterValue, 3, 140, 0, 0, // Skip to: 12761 /* 12621 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 12624 */ MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 12680 /* 12629 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12632 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12656 /* 12637 */ MCD_OPC_CheckField, 16, 5, 0, 206, 14, 0, // Skip to: 16434 /* 12644 */ MCD_OPC_CheckField, 2, 1, 1, 199, 14, 0, // Skip to: 16434 /* 12651 */ MCD_OPC_Decode, 198, 15, 143, 1, // Opcode: XSRDPIP /* 12656 */ MCD_OPC_FilterValue, 1, 189, 14, 0, // Skip to: 16434 /* 12661 */ MCD_OPC_CheckField, 16, 5, 0, 182, 14, 0, // Skip to: 16434 /* 12668 */ MCD_OPC_CheckField, 2, 1, 1, 175, 14, 0, // Skip to: 16434 /* 12675 */ MCD_OPC_Decode, 197, 15, 143, 1, // Opcode: XSRDPIM /* 12680 */ MCD_OPC_FilterValue, 1, 165, 14, 0, // Skip to: 16434 /* 12685 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12688 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 12737 /* 12693 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 12696 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 12720 /* 12701 */ MCD_OPC_CheckField, 16, 7, 0, 142, 14, 0, // Skip to: 16434 /* 12708 */ MCD_OPC_CheckField, 0, 1, 0, 135, 14, 0, // Skip to: 16434 /* 12715 */ MCD_OPC_Decode, 217, 15, 144, 1, // Opcode: XSTSQRTDP /* 12720 */ MCD_OPC_FilterValue, 1, 125, 14, 0, // Skip to: 16434 /* 12725 */ MCD_OPC_CheckField, 16, 5, 0, 118, 14, 0, // Skip to: 16434 /* 12732 */ MCD_OPC_Decode, 196, 15, 143, 1, // Opcode: XSRDPIC /* 12737 */ MCD_OPC_FilterValue, 1, 108, 14, 0, // Skip to: 16434 /* 12742 */ MCD_OPC_CheckField, 21, 2, 0, 101, 14, 0, // Skip to: 16434 /* 12749 */ MCD_OPC_CheckField, 0, 1, 0, 94, 14, 0, // Skip to: 16434 /* 12756 */ MCD_OPC_Decode, 216, 15, 137, 1, // Opcode: XSTDIVDP /* 12761 */ MCD_OPC_FilterValue, 4, 153, 0, 0, // Skip to: 12919 /* 12766 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 12769 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 12811 /* 12774 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12777 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12794 /* 12782 */ MCD_OPC_CheckField, 16, 5, 0, 61, 14, 0, // Skip to: 16434 /* 12789 */ MCD_OPC_Decode, 254, 15, 145, 1, // Opcode: XVCVSPUXWS /* 12794 */ MCD_OPC_FilterValue, 1, 51, 14, 0, // Skip to: 16434 /* 12799 */ MCD_OPC_CheckField, 16, 5, 0, 44, 14, 0, // Skip to: 16434 /* 12806 */ MCD_OPC_Decode, 252, 15, 145, 1, // Opcode: XVCVSPSXWS /* 12811 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 12853 /* 12816 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12819 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12836 /* 12824 */ MCD_OPC_CheckField, 16, 5, 0, 19, 14, 0, // Skip to: 16434 /* 12831 */ MCD_OPC_Decode, 172, 16, 145, 1, // Opcode: XVRSPI /* 12836 */ MCD_OPC_FilterValue, 1, 9, 14, 0, // Skip to: 16434 /* 12841 */ MCD_OPC_CheckField, 16, 5, 0, 2, 14, 0, // Skip to: 16434 /* 12848 */ MCD_OPC_Decode, 176, 16, 145, 1, // Opcode: XVRSPIZ /* 12853 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 12895 /* 12858 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12861 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12878 /* 12866 */ MCD_OPC_CheckField, 16, 5, 0, 233, 13, 0, // Skip to: 16434 /* 12873 */ MCD_OPC_Decode, 178, 16, 145, 1, // Opcode: XVRSQRTESP /* 12878 */ MCD_OPC_FilterValue, 1, 223, 13, 0, // Skip to: 16434 /* 12883 */ MCD_OPC_CheckField, 16, 5, 0, 216, 13, 0, // Skip to: 16434 /* 12890 */ MCD_OPC_Decode, 171, 16, 145, 1, // Opcode: XVRESP /* 12895 */ MCD_OPC_FilterValue, 3, 206, 13, 0, // Skip to: 16434 /* 12900 */ MCD_OPC_CheckField, 16, 5, 0, 199, 13, 0, // Skip to: 16434 /* 12907 */ MCD_OPC_CheckField, 6, 1, 0, 192, 13, 0, // Skip to: 16434 /* 12914 */ MCD_OPC_Decode, 180, 16, 145, 1, // Opcode: XVSQRTSP /* 12919 */ MCD_OPC_FilterValue, 5, 176, 0, 0, // Skip to: 13100 /* 12924 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 12927 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 13019 /* 12932 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 12935 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 12977 /* 12940 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12943 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 12960 /* 12948 */ MCD_OPC_CheckField, 16, 5, 0, 151, 13, 0, // Skip to: 16434 /* 12955 */ MCD_OPC_Decode, 134, 16, 145, 1, // Opcode: XVCVUXWSP /* 12960 */ MCD_OPC_FilterValue, 1, 141, 13, 0, // Skip to: 16434 /* 12965 */ MCD_OPC_CheckField, 16, 5, 0, 134, 13, 0, // Skip to: 16434 /* 12972 */ MCD_OPC_Decode, 130, 16, 145, 1, // Opcode: XVCVSXWSP /* 12977 */ MCD_OPC_FilterValue, 1, 124, 13, 0, // Skip to: 16434 /* 12982 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 12985 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13002 /* 12990 */ MCD_OPC_CheckField, 16, 5, 0, 109, 13, 0, // Skip to: 16434 /* 12997 */ MCD_OPC_Decode, 175, 16, 145, 1, // Opcode: XVRSPIP /* 13002 */ MCD_OPC_FilterValue, 1, 99, 13, 0, // Skip to: 16434 /* 13007 */ MCD_OPC_CheckField, 16, 5, 0, 92, 13, 0, // Skip to: 16434 /* 13014 */ MCD_OPC_Decode, 174, 16, 145, 1, // Opcode: XVRSPIM /* 13019 */ MCD_OPC_FilterValue, 1, 82, 13, 0, // Skip to: 16434 /* 13024 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13027 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 13076 /* 13032 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 13035 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 13059 /* 13040 */ MCD_OPC_CheckField, 16, 7, 0, 59, 13, 0, // Skip to: 16434 /* 13047 */ MCD_OPC_CheckField, 0, 1, 0, 52, 13, 0, // Skip to: 16434 /* 13054 */ MCD_OPC_Decode, 186, 16, 146, 1, // Opcode: XVTSQRTSP /* 13059 */ MCD_OPC_FilterValue, 1, 42, 13, 0, // Skip to: 16434 /* 13064 */ MCD_OPC_CheckField, 16, 5, 0, 35, 13, 0, // Skip to: 16434 /* 13071 */ MCD_OPC_Decode, 173, 16, 145, 1, // Opcode: XVRSPIC /* 13076 */ MCD_OPC_FilterValue, 1, 25, 13, 0, // Skip to: 16434 /* 13081 */ MCD_OPC_CheckField, 21, 2, 0, 18, 13, 0, // Skip to: 16434 /* 13088 */ MCD_OPC_CheckField, 0, 1, 0, 11, 13, 0, // Skip to: 16434 /* 13095 */ MCD_OPC_Decode, 184, 16, 147, 1, // Opcode: XVTDIVSP /* 13100 */ MCD_OPC_FilterValue, 6, 153, 0, 0, // Skip to: 13258 /* 13105 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 13108 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13150 /* 13113 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13116 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13133 /* 13121 */ MCD_OPC_CheckField, 16, 5, 0, 234, 12, 0, // Skip to: 16434 /* 13128 */ MCD_OPC_Decode, 247, 15, 145, 1, // Opcode: XVCVDPUXWS /* 13133 */ MCD_OPC_FilterValue, 1, 224, 12, 0, // Skip to: 16434 /* 13138 */ MCD_OPC_CheckField, 16, 5, 0, 217, 12, 0, // Skip to: 16434 /* 13145 */ MCD_OPC_Decode, 245, 15, 145, 1, // Opcode: XVCVDPSXWS /* 13150 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 13192 /* 13155 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13158 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13175 /* 13163 */ MCD_OPC_CheckField, 16, 5, 0, 192, 12, 0, // Skip to: 16434 /* 13170 */ MCD_OPC_Decode, 165, 16, 145, 1, // Opcode: XVRDPI /* 13175 */ MCD_OPC_FilterValue, 1, 182, 12, 0, // Skip to: 16434 /* 13180 */ MCD_OPC_CheckField, 16, 5, 0, 175, 12, 0, // Skip to: 16434 /* 13187 */ MCD_OPC_Decode, 169, 16, 145, 1, // Opcode: XVRDPIZ /* 13192 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 13234 /* 13197 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13200 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13217 /* 13205 */ MCD_OPC_CheckField, 16, 5, 0, 150, 12, 0, // Skip to: 16434 /* 13212 */ MCD_OPC_Decode, 177, 16, 145, 1, // Opcode: XVRSQRTEDP /* 13217 */ MCD_OPC_FilterValue, 1, 140, 12, 0, // Skip to: 16434 /* 13222 */ MCD_OPC_CheckField, 16, 5, 0, 133, 12, 0, // Skip to: 16434 /* 13229 */ MCD_OPC_Decode, 170, 16, 145, 1, // Opcode: XVREDP /* 13234 */ MCD_OPC_FilterValue, 3, 123, 12, 0, // Skip to: 16434 /* 13239 */ MCD_OPC_CheckField, 16, 5, 0, 116, 12, 0, // Skip to: 16434 /* 13246 */ MCD_OPC_CheckField, 6, 1, 0, 109, 12, 0, // Skip to: 16434 /* 13253 */ MCD_OPC_Decode, 179, 16, 145, 1, // Opcode: XVSQRTDP /* 13258 */ MCD_OPC_FilterValue, 7, 176, 0, 0, // Skip to: 13439 /* 13263 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 13266 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 13358 /* 13271 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 13274 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13316 /* 13279 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13282 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13299 /* 13287 */ MCD_OPC_CheckField, 16, 5, 0, 68, 12, 0, // Skip to: 16434 /* 13294 */ MCD_OPC_Decode, 133, 16, 145, 1, // Opcode: XVCVUXWDP /* 13299 */ MCD_OPC_FilterValue, 1, 58, 12, 0, // Skip to: 16434 /* 13304 */ MCD_OPC_CheckField, 16, 5, 0, 51, 12, 0, // Skip to: 16434 /* 13311 */ MCD_OPC_Decode, 129, 16, 145, 1, // Opcode: XVCVSXWDP /* 13316 */ MCD_OPC_FilterValue, 1, 41, 12, 0, // Skip to: 16434 /* 13321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13324 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13341 /* 13329 */ MCD_OPC_CheckField, 16, 5, 0, 26, 12, 0, // Skip to: 16434 /* 13336 */ MCD_OPC_Decode, 168, 16, 145, 1, // Opcode: XVRDPIP /* 13341 */ MCD_OPC_FilterValue, 1, 16, 12, 0, // Skip to: 16434 /* 13346 */ MCD_OPC_CheckField, 16, 5, 0, 9, 12, 0, // Skip to: 16434 /* 13353 */ MCD_OPC_Decode, 167, 16, 145, 1, // Opcode: XVRDPIM /* 13358 */ MCD_OPC_FilterValue, 1, 255, 11, 0, // Skip to: 16434 /* 13363 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13366 */ MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 13415 /* 13371 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 13374 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 13398 /* 13379 */ MCD_OPC_CheckField, 16, 7, 0, 232, 11, 0, // Skip to: 16434 /* 13386 */ MCD_OPC_CheckField, 0, 1, 0, 225, 11, 0, // Skip to: 16434 /* 13393 */ MCD_OPC_Decode, 185, 16, 146, 1, // Opcode: XVTSQRTDP /* 13398 */ MCD_OPC_FilterValue, 1, 215, 11, 0, // Skip to: 16434 /* 13403 */ MCD_OPC_CheckField, 16, 5, 0, 208, 11, 0, // Skip to: 16434 /* 13410 */ MCD_OPC_Decode, 166, 16, 145, 1, // Opcode: XVRDPIC /* 13415 */ MCD_OPC_FilterValue, 1, 198, 11, 0, // Skip to: 16434 /* 13420 */ MCD_OPC_CheckField, 21, 2, 0, 191, 11, 0, // Skip to: 16434 /* 13427 */ MCD_OPC_CheckField, 0, 1, 0, 184, 11, 0, // Skip to: 16434 /* 13434 */ MCD_OPC_Decode, 183, 16, 147, 1, // Opcode: XVTDIVDP /* 13439 */ MCD_OPC_FilterValue, 8, 69, 0, 0, // Skip to: 13513 /* 13444 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 13447 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 13489 /* 13452 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13455 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13472 /* 13460 */ MCD_OPC_CheckField, 16, 5, 0, 151, 11, 0, // Skip to: 16434 /* 13467 */ MCD_OPC_Decode, 254, 14, 143, 1, // Opcode: XSCVDPSP /* 13472 */ MCD_OPC_FilterValue, 1, 141, 11, 0, // Skip to: 16434 /* 13477 */ MCD_OPC_CheckField, 16, 5, 0, 134, 11, 0, // Skip to: 16434 /* 13484 */ MCD_OPC_Decode, 205, 15, 148, 1, // Opcode: XSRSP /* 13489 */ MCD_OPC_FilterValue, 3, 124, 11, 0, // Skip to: 16434 /* 13494 */ MCD_OPC_CheckField, 16, 5, 0, 117, 11, 0, // Skip to: 16434 /* 13501 */ MCD_OPC_CheckField, 6, 1, 0, 110, 11, 0, // Skip to: 16434 /* 13508 */ MCD_OPC_Decode, 255, 14, 149, 1, // Opcode: XSCVDPSPN /* 13513 */ MCD_OPC_FilterValue, 9, 69, 0, 0, // Skip to: 13587 /* 13518 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 13521 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13563 /* 13526 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13529 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13546 /* 13534 */ MCD_OPC_CheckField, 16, 5, 0, 77, 11, 0, // Skip to: 16434 /* 13541 */ MCD_OPC_Decode, 150, 15, 148, 1, // Opcode: XSCVUXDSP /* 13546 */ MCD_OPC_FilterValue, 1, 67, 11, 0, // Skip to: 16434 /* 13551 */ MCD_OPC_CheckField, 16, 5, 0, 60, 11, 0, // Skip to: 16434 /* 13558 */ MCD_OPC_Decode, 147, 15, 148, 1, // Opcode: XSCVSXDSP /* 13563 */ MCD_OPC_FilterValue, 2, 50, 11, 0, // Skip to: 16434 /* 13568 */ MCD_OPC_CheckField, 6, 1, 0, 43, 11, 0, // Skip to: 16434 /* 13575 */ MCD_OPC_CheckField, 0, 1, 0, 36, 11, 0, // Skip to: 16434 /* 13582 */ MCD_OPC_Decode, 220, 15, 150, 1, // Opcode: XSTSTDCSP /* 13587 */ MCD_OPC_FilterValue, 10, 181, 0, 0, // Skip to: 13773 /* 13592 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 13595 */ MCD_OPC_FilterValue, 0, 94, 0, 0, // Skip to: 13694 /* 13600 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 13603 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13631 /* 13608 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13611 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13621 /* 13616 */ MCD_OPC_Decode, 132, 15, 143, 1, // Opcode: XSCVDPUXDS /* 13621 */ MCD_OPC_FilterValue, 1, 248, 10, 0, // Skip to: 16434 /* 13626 */ MCD_OPC_Decode, 128, 15, 143, 1, // Opcode: XSCVDPSXDS /* 13631 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 13659 /* 13636 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13639 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13649 /* 13644 */ MCD_OPC_Decode, 144, 15, 143, 1, // Opcode: XSCVSPDP /* 13649 */ MCD_OPC_FilterValue, 1, 220, 10, 0, // Skip to: 16434 /* 13654 */ MCD_OPC_Decode, 235, 14, 143, 1, // Opcode: XSABSDP /* 13659 */ MCD_OPC_FilterValue, 3, 210, 10, 0, // Skip to: 16434 /* 13664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13667 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 13677 /* 13672 */ MCD_OPC_Decode, 145, 15, 151, 1, // Opcode: XSCVSPDPN /* 13677 */ MCD_OPC_FilterValue, 1, 192, 10, 0, // Skip to: 16434 /* 13682 */ MCD_OPC_CheckField, 0, 1, 0, 185, 10, 0, // Skip to: 16434 /* 13689 */ MCD_OPC_Decode, 221, 15, 152, 1, // Opcode: XSXEXPDP /* 13694 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 13725 /* 13699 */ MCD_OPC_CheckField, 6, 1, 1, 168, 10, 0, // Skip to: 16434 /* 13706 */ MCD_OPC_CheckField, 2, 2, 3, 161, 10, 0, // Skip to: 16434 /* 13713 */ MCD_OPC_CheckField, 0, 1, 0, 154, 10, 0, // Skip to: 16434 /* 13720 */ MCD_OPC_Decode, 223, 15, 152, 1, // Opcode: XSXSIGDP /* 13725 */ MCD_OPC_FilterValue, 16, 19, 0, 0, // Skip to: 13749 /* 13730 */ MCD_OPC_CheckField, 6, 1, 1, 137, 10, 0, // Skip to: 16434 /* 13737 */ MCD_OPC_CheckField, 2, 2, 3, 130, 10, 0, // Skip to: 16434 /* 13744 */ MCD_OPC_Decode, 136, 15, 143, 1, // Opcode: XSCVHPDP /* 13749 */ MCD_OPC_FilterValue, 17, 120, 10, 0, // Skip to: 16434 /* 13754 */ MCD_OPC_CheckField, 6, 1, 1, 113, 10, 0, // Skip to: 16434 /* 13761 */ MCD_OPC_CheckField, 2, 2, 3, 106, 10, 0, // Skip to: 16434 /* 13768 */ MCD_OPC_Decode, 252, 14, 143, 1, // Opcode: XSCVDPHP /* 13773 */ MCD_OPC_FilterValue, 11, 111, 0, 0, // Skip to: 13889 /* 13778 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 13781 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13823 /* 13786 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13789 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13806 /* 13794 */ MCD_OPC_CheckField, 16, 5, 0, 73, 10, 0, // Skip to: 16434 /* 13801 */ MCD_OPC_Decode, 149, 15, 143, 1, // Opcode: XSCVUXDDP /* 13806 */ MCD_OPC_FilterValue, 1, 63, 10, 0, // Skip to: 16434 /* 13811 */ MCD_OPC_CheckField, 16, 5, 0, 56, 10, 0, // Skip to: 16434 /* 13818 */ MCD_OPC_Decode, 146, 15, 143, 1, // Opcode: XSCVSXDDP /* 13823 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 13865 /* 13828 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13831 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13848 /* 13836 */ MCD_OPC_CheckField, 16, 5, 0, 31, 10, 0, // Skip to: 16434 /* 13843 */ MCD_OPC_Decode, 179, 15, 143, 1, // Opcode: XSNABSDP /* 13848 */ MCD_OPC_FilterValue, 1, 21, 10, 0, // Skip to: 16434 /* 13853 */ MCD_OPC_CheckField, 16, 5, 0, 14, 10, 0, // Skip to: 16434 /* 13860 */ MCD_OPC_Decode, 181, 15, 143, 1, // Opcode: XSNEGDP /* 13865 */ MCD_OPC_FilterValue, 2, 4, 10, 0, // Skip to: 16434 /* 13870 */ MCD_OPC_CheckField, 6, 1, 0, 253, 9, 0, // Skip to: 16434 /* 13877 */ MCD_OPC_CheckField, 0, 1, 0, 246, 9, 0, // Skip to: 16434 /* 13884 */ MCD_OPC_Decode, 218, 15, 150, 1, // Opcode: XSTSTDCDP /* 13889 */ MCD_OPC_FilterValue, 12, 87, 0, 0, // Skip to: 13981 /* 13894 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 13897 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 13939 /* 13902 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13905 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13922 /* 13910 */ MCD_OPC_CheckField, 16, 5, 0, 213, 9, 0, // Skip to: 16434 /* 13917 */ MCD_OPC_Decode, 253, 15, 145, 1, // Opcode: XVCVSPUXDS /* 13922 */ MCD_OPC_FilterValue, 1, 203, 9, 0, // Skip to: 16434 /* 13927 */ MCD_OPC_CheckField, 16, 5, 0, 196, 9, 0, // Skip to: 16434 /* 13934 */ MCD_OPC_Decode, 251, 15, 145, 1, // Opcode: XVCVSPSXDS /* 13939 */ MCD_OPC_FilterValue, 1, 186, 9, 0, // Skip to: 16434 /* 13944 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 13947 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 13964 /* 13952 */ MCD_OPC_CheckField, 16, 5, 0, 171, 9, 0, // Skip to: 16434 /* 13959 */ MCD_OPC_Decode, 243, 15, 145, 1, // Opcode: XVCVDPSP /* 13964 */ MCD_OPC_FilterValue, 1, 161, 9, 0, // Skip to: 16434 /* 13969 */ MCD_OPC_CheckField, 16, 5, 0, 154, 9, 0, // Skip to: 16434 /* 13976 */ MCD_OPC_Decode, 226, 15, 145, 1, // Opcode: XVABSSP /* 13981 */ MCD_OPC_FilterValue, 13, 105, 0, 0, // Skip to: 14091 /* 13986 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 13989 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 14081 /* 13994 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 13997 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 14039 /* 14002 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14005 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14022 /* 14010 */ MCD_OPC_CheckField, 16, 5, 0, 113, 9, 0, // Skip to: 16434 /* 14017 */ MCD_OPC_Decode, 132, 16, 145, 1, // Opcode: XVCVUXDSP /* 14022 */ MCD_OPC_FilterValue, 1, 103, 9, 0, // Skip to: 16434 /* 14027 */ MCD_OPC_CheckField, 16, 5, 0, 96, 9, 0, // Skip to: 16434 /* 14034 */ MCD_OPC_Decode, 128, 16, 145, 1, // Opcode: XVCVSXDSP /* 14039 */ MCD_OPC_FilterValue, 1, 86, 9, 0, // Skip to: 16434 /* 14044 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14047 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14064 /* 14052 */ MCD_OPC_CheckField, 16, 5, 0, 71, 9, 0, // Skip to: 16434 /* 14059 */ MCD_OPC_Decode, 154, 16, 145, 1, // Opcode: XVNABSSP /* 14064 */ MCD_OPC_FilterValue, 1, 61, 9, 0, // Skip to: 16434 /* 14069 */ MCD_OPC_CheckField, 16, 5, 0, 54, 9, 0, // Skip to: 16434 /* 14076 */ MCD_OPC_Decode, 156, 16, 145, 1, // Opcode: XVNEGSP /* 14081 */ MCD_OPC_FilterValue, 1, 44, 9, 0, // Skip to: 16434 /* 14086 */ MCD_OPC_Decode, 188, 16, 153, 1, // Opcode: XVTSTDCSP /* 14091 */ MCD_OPC_FilterValue, 14, 220, 0, 0, // Skip to: 14316 /* 14096 */ MCD_OPC_ExtractField, 2, 2, // Inst{3-2} ... /* 14099 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 14141 /* 14104 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14107 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14124 /* 14112 */ MCD_OPC_CheckField, 16, 5, 0, 11, 9, 0, // Skip to: 16434 /* 14119 */ MCD_OPC_Decode, 246, 15, 145, 1, // Opcode: XVCVDPUXDS /* 14124 */ MCD_OPC_FilterValue, 1, 1, 9, 0, // Skip to: 16434 /* 14129 */ MCD_OPC_CheckField, 16, 5, 0, 250, 8, 0, // Skip to: 16434 /* 14136 */ MCD_OPC_Decode, 244, 15, 145, 1, // Opcode: XVCVDPSXDS /* 14141 */ MCD_OPC_FilterValue, 1, 37, 0, 0, // Skip to: 14183 /* 14146 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14149 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14166 /* 14154 */ MCD_OPC_CheckField, 16, 5, 0, 225, 8, 0, // Skip to: 16434 /* 14161 */ MCD_OPC_Decode, 249, 15, 145, 1, // Opcode: XVCVSPDP /* 14166 */ MCD_OPC_FilterValue, 1, 215, 8, 0, // Skip to: 16434 /* 14171 */ MCD_OPC_CheckField, 16, 5, 0, 208, 8, 0, // Skip to: 16434 /* 14178 */ MCD_OPC_Decode, 225, 15, 145, 1, // Opcode: XVABSDP /* 14183 */ MCD_OPC_FilterValue, 3, 198, 8, 0, // Skip to: 16434 /* 14188 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14191 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14208 /* 14196 */ MCD_OPC_CheckField, 1, 1, 0, 183, 8, 0, // Skip to: 16434 /* 14203 */ MCD_OPC_Decode, 155, 15, 154, 1, // Opcode: XSIEXPDP /* 14208 */ MCD_OPC_FilterValue, 1, 173, 8, 0, // Skip to: 16434 /* 14213 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 14216 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 14226 /* 14221 */ MCD_OPC_Decode, 189, 16, 145, 1, // Opcode: XVXEXPDP /* 14226 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 14236 /* 14231 */ MCD_OPC_Decode, 191, 16, 145, 1, // Opcode: XVXSIGDP /* 14236 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 14246 /* 14241 */ MCD_OPC_Decode, 194, 16, 145, 1, // Opcode: XXBRH /* 14246 */ MCD_OPC_FilterValue, 8, 5, 0, 0, // Skip to: 14256 /* 14251 */ MCD_OPC_Decode, 190, 16, 145, 1, // Opcode: XVXEXPSP /* 14256 */ MCD_OPC_FilterValue, 9, 5, 0, 0, // Skip to: 14266 /* 14261 */ MCD_OPC_Decode, 192, 16, 145, 1, // Opcode: XVXSIGSP /* 14266 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 14276 /* 14271 */ MCD_OPC_Decode, 196, 16, 145, 1, // Opcode: XXBRW /* 14276 */ MCD_OPC_FilterValue, 23, 5, 0, 0, // Skip to: 14286 /* 14281 */ MCD_OPC_Decode, 193, 16, 145, 1, // Opcode: XXBRD /* 14286 */ MCD_OPC_FilterValue, 24, 5, 0, 0, // Skip to: 14296 /* 14291 */ MCD_OPC_Decode, 248, 15, 145, 1, // Opcode: XVCVHPSP /* 14296 */ MCD_OPC_FilterValue, 25, 5, 0, 0, // Skip to: 14306 /* 14301 */ MCD_OPC_Decode, 250, 15, 145, 1, // Opcode: XVCVSPHP /* 14306 */ MCD_OPC_FilterValue, 31, 75, 8, 0, // Skip to: 16434 /* 14311 */ MCD_OPC_Decode, 195, 16, 145, 1, // Opcode: XXBRQ /* 14316 */ MCD_OPC_FilterValue, 15, 65, 8, 0, // Skip to: 16434 /* 14321 */ MCD_OPC_ExtractField, 3, 1, // Inst{3} ... /* 14324 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 14416 /* 14329 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 14332 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 14374 /* 14337 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14340 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14357 /* 14345 */ MCD_OPC_CheckField, 16, 5, 0, 34, 8, 0, // Skip to: 16434 /* 14352 */ MCD_OPC_Decode, 131, 16, 145, 1, // Opcode: XVCVUXDDP /* 14357 */ MCD_OPC_FilterValue, 1, 24, 8, 0, // Skip to: 16434 /* 14362 */ MCD_OPC_CheckField, 16, 5, 0, 17, 8, 0, // Skip to: 16434 /* 14369 */ MCD_OPC_Decode, 255, 15, 145, 1, // Opcode: XVCVSXDDP /* 14374 */ MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 16434 /* 14379 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... /* 14382 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14399 /* 14387 */ MCD_OPC_CheckField, 16, 5, 0, 248, 7, 0, // Skip to: 16434 /* 14394 */ MCD_OPC_Decode, 153, 16, 145, 1, // Opcode: XVNABSDP /* 14399 */ MCD_OPC_FilterValue, 1, 238, 7, 0, // Skip to: 16434 /* 14404 */ MCD_OPC_CheckField, 16, 5, 0, 231, 7, 0, // Skip to: 16434 /* 14411 */ MCD_OPC_Decode, 155, 16, 145, 1, // Opcode: XVNEGDP /* 14416 */ MCD_OPC_FilterValue, 1, 221, 7, 0, // Skip to: 16434 /* 14421 */ MCD_OPC_Decode, 187, 16, 153, 1, // Opcode: XVTSTDCDP /* 14426 */ MCD_OPC_FilterValue, 3, 211, 7, 0, // Skip to: 16434 /* 14431 */ MCD_OPC_Decode, 217, 16, 155, 1, // Opcode: XXSEL /* 14436 */ MCD_OPC_FilterValue, 61, 49, 0, 0, // Skip to: 14490 /* 14441 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 14444 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 14472 /* 14449 */ MCD_OPC_ExtractField, 2, 1, // Inst{2} ... /* 14452 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 14462 /* 14457 */ MCD_OPC_Decode, 134, 8, 156, 1, // Opcode: LXV /* 14462 */ MCD_OPC_FilterValue, 1, 175, 7, 0, // Skip to: 16434 /* 14467 */ MCD_OPC_Decode, 241, 11, 156, 1, // Opcode: STXV /* 14472 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 14481 /* 14477 */ MCD_OPC_Decode, 232, 11, 122, // Opcode: STXSD /* 14481 */ MCD_OPC_FilterValue, 3, 156, 7, 0, // Skip to: 16434 /* 14486 */ MCD_OPC_Decode, 239, 11, 122, // Opcode: STXSSP /* 14490 */ MCD_OPC_FilterValue, 62, 21, 0, 0, // Skip to: 14516 /* 14495 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 14498 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14507 /* 14503 */ MCD_OPC_Decode, 173, 11, 123, // Opcode: STD /* 14507 */ MCD_OPC_FilterValue, 1, 130, 7, 0, // Skip to: 16434 /* 14512 */ MCD_OPC_Decode, 178, 11, 123, // Opcode: STDU /* 14516 */ MCD_OPC_FilterValue, 63, 121, 7, 0, // Skip to: 16434 /* 14521 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 14524 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 14606 /* 14529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 14532 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 14549 /* 14537 */ MCD_OPC_CheckField, 21, 2, 0, 98, 7, 0, // Skip to: 16434 /* 14544 */ MCD_OPC_Decode, 164, 6, 157, 1, // Opcode: FCMPUS /* 14549 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 14572 /* 14554 */ MCD_OPC_CheckField, 21, 2, 0, 81, 7, 0, // Skip to: 16434 /* 14561 */ MCD_OPC_CheckField, 11, 7, 0, 74, 7, 0, // Skip to: 16434 /* 14568 */ MCD_OPC_Decode, 149, 8, 33, // Opcode: MCRFS /* 14572 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 14589 /* 14577 */ MCD_OPC_CheckField, 21, 2, 0, 58, 7, 0, // Skip to: 16434 /* 14584 */ MCD_OPC_Decode, 129, 7, 158, 1, // Opcode: FTDIV /* 14589 */ MCD_OPC_FilterValue, 5, 48, 7, 0, // Skip to: 16434 /* 14594 */ MCD_OPC_CheckField, 16, 7, 0, 41, 7, 0, // Skip to: 16434 /* 14601 */ MCD_OPC_Decode, 130, 7, 159, 1, // Opcode: FTSQRT /* 14606 */ MCD_OPC_FilterValue, 8, 49, 1, 0, // Skip to: 14916 /* 14611 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 14614 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14623 /* 14619 */ MCD_OPC_Decode, 238, 14, 3, // Opcode: XSADDQP /* 14623 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 14632 /* 14628 */ MCD_OPC_Decode, 176, 15, 3, // Opcode: XSMULQP /* 14632 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 14641 /* 14637 */ MCD_OPC_Decode, 251, 14, 3, // Opcode: XSCPSGNQP /* 14641 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 14658 /* 14646 */ MCD_OPC_CheckField, 21, 2, 0, 245, 6, 0, // Skip to: 16434 /* 14653 */ MCD_OPC_Decode, 247, 14, 160, 1, // Opcode: XSCMPOQP /* 14658 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 14675 /* 14663 */ MCD_OPC_CheckField, 21, 2, 0, 228, 6, 0, // Skip to: 16434 /* 14670 */ MCD_OPC_Decode, 243, 14, 160, 1, // Opcode: XSCMPEXPQP /* 14675 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 14685 /* 14680 */ MCD_OPC_Decode, 161, 15, 161, 1, // Opcode: XSMADDQP /* 14685 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 14695 /* 14690 */ MCD_OPC_Decode, 173, 15, 161, 1, // Opcode: XSMSUBQP /* 14695 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 14705 /* 14700 */ MCD_OPC_Decode, 187, 15, 161, 1, // Opcode: XSNMADDQP /* 14705 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 14715 /* 14710 */ MCD_OPC_Decode, 193, 15, 161, 1, // Opcode: XSNMSUBQP /* 14715 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 14724 /* 14720 */ MCD_OPC_Decode, 213, 15, 3, // Opcode: XSSUBQP /* 14724 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 14733 /* 14729 */ MCD_OPC_Decode, 152, 15, 3, // Opcode: XSDIVQP /* 14733 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 14750 /* 14738 */ MCD_OPC_CheckField, 21, 2, 0, 153, 6, 0, // Skip to: 16434 /* 14745 */ MCD_OPC_Decode, 249, 14, 160, 1, // Opcode: XSCMPUQP /* 14750 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 14760 /* 14755 */ MCD_OPC_Decode, 219, 15, 162, 1, // Opcode: XSTSTDCQP /* 14760 */ MCD_OPC_FilterValue, 25, 57, 0, 0, // Skip to: 14822 /* 14765 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 14768 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14777 /* 14773 */ MCD_OPC_Decode, 236, 14, 6, // Opcode: XSABSQP /* 14777 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 14786 /* 14782 */ MCD_OPC_Decode, 222, 15, 6, // Opcode: XSXEXPQP /* 14786 */ MCD_OPC_FilterValue, 8, 4, 0, 0, // Skip to: 14795 /* 14791 */ MCD_OPC_Decode, 180, 15, 6, // Opcode: XSNABSQP /* 14795 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 14804 /* 14800 */ MCD_OPC_Decode, 182, 15, 6, // Opcode: XSNEGQP /* 14804 */ MCD_OPC_FilterValue, 18, 4, 0, 0, // Skip to: 14813 /* 14809 */ MCD_OPC_Decode, 224, 15, 6, // Opcode: XSXSIGQP /* 14813 */ MCD_OPC_FilterValue, 27, 80, 6, 0, // Skip to: 16434 /* 14818 */ MCD_OPC_Decode, 209, 15, 6, // Opcode: XSSQRTQP /* 14822 */ MCD_OPC_FilterValue, 26, 79, 0, 0, // Skip to: 14906 /* 14827 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 14830 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 14839 /* 14835 */ MCD_OPC_Decode, 142, 15, 6, // Opcode: XSCVQPUWZ /* 14839 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 14849 /* 14844 */ MCD_OPC_Decode, 148, 15, 163, 1, // Opcode: XSCVUDQP /* 14849 */ MCD_OPC_FilterValue, 9, 4, 0, 0, // Skip to: 14858 /* 14854 */ MCD_OPC_Decode, 140, 15, 6, // Opcode: XSCVQPSWZ /* 14858 */ MCD_OPC_FilterValue, 10, 5, 0, 0, // Skip to: 14868 /* 14863 */ MCD_OPC_Decode, 143, 15, 163, 1, // Opcode: XSCVSDQP /* 14868 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 14877 /* 14873 */ MCD_OPC_Decode, 141, 15, 6, // Opcode: XSCVQPUDZ /* 14877 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 14887 /* 14882 */ MCD_OPC_Decode, 137, 15, 164, 1, // Opcode: XSCVQPDP /* 14887 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 14897 /* 14892 */ MCD_OPC_Decode, 253, 14, 163, 1, // Opcode: XSCVDPQP /* 14897 */ MCD_OPC_FilterValue, 25, 252, 5, 0, // Skip to: 16434 /* 14902 */ MCD_OPC_Decode, 139, 15, 6, // Opcode: XSCVQPSDZ /* 14906 */ MCD_OPC_FilterValue, 27, 243, 5, 0, // Skip to: 16434 /* 14911 */ MCD_OPC_Decode, 156, 15, 165, 1, // Opcode: XSIEXPQP /* 14916 */ MCD_OPC_FilterValue, 9, 112, 0, 0, // Skip to: 15033 /* 14921 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 14924 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 14933 /* 14929 */ MCD_OPC_Decode, 239, 14, 3, // Opcode: XSADDQPO /* 14933 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 14942 /* 14938 */ MCD_OPC_Decode, 177, 15, 3, // Opcode: XSMULQPO /* 14942 */ MCD_OPC_FilterValue, 12, 5, 0, 0, // Skip to: 14952 /* 14947 */ MCD_OPC_Decode, 162, 15, 161, 1, // Opcode: XSMADDQPO /* 14952 */ MCD_OPC_FilterValue, 13, 5, 0, 0, // Skip to: 14962 /* 14957 */ MCD_OPC_Decode, 174, 15, 161, 1, // Opcode: XSMSUBQPO /* 14962 */ MCD_OPC_FilterValue, 14, 5, 0, 0, // Skip to: 14972 /* 14967 */ MCD_OPC_Decode, 188, 15, 161, 1, // Opcode: XSNMADDQPO /* 14972 */ MCD_OPC_FilterValue, 15, 5, 0, 0, // Skip to: 14982 /* 14977 */ MCD_OPC_Decode, 194, 15, 161, 1, // Opcode: XSNMSUBQPO /* 14982 */ MCD_OPC_FilterValue, 16, 4, 0, 0, // Skip to: 14991 /* 14987 */ MCD_OPC_Decode, 214, 15, 3, // Opcode: XSSUBQPO /* 14991 */ MCD_OPC_FilterValue, 17, 4, 0, 0, // Skip to: 15000 /* 14996 */ MCD_OPC_Decode, 153, 15, 3, // Opcode: XSDIVQPO /* 15000 */ MCD_OPC_FilterValue, 25, 11, 0, 0, // Skip to: 15016 /* 15005 */ MCD_OPC_CheckField, 16, 5, 27, 142, 5, 0, // Skip to: 16434 /* 15012 */ MCD_OPC_Decode, 210, 15, 6, // Opcode: XSSQRTQPO /* 15016 */ MCD_OPC_FilterValue, 26, 133, 5, 0, // Skip to: 16434 /* 15021 */ MCD_OPC_CheckField, 16, 5, 20, 126, 5, 0, // Skip to: 16434 /* 15028 */ MCD_OPC_Decode, 138, 15, 164, 1, // Opcode: XSCVQPDPO /* 15033 */ MCD_OPC_FilterValue, 10, 37, 0, 0, // Skip to: 15075 /* 15038 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... /* 15041 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15058 /* 15046 */ MCD_OPC_CheckField, 17, 4, 0, 101, 5, 0, // Skip to: 16434 /* 15053 */ MCD_OPC_Decode, 202, 15, 166, 1, // Opcode: XSRQPI /* 15058 */ MCD_OPC_FilterValue, 1, 91, 5, 0, // Skip to: 16434 /* 15063 */ MCD_OPC_CheckField, 17, 4, 0, 84, 5, 0, // Skip to: 16434 /* 15070 */ MCD_OPC_Decode, 204, 15, 166, 1, // Opcode: XSRQPXP /* 15075 */ MCD_OPC_FilterValue, 11, 19, 0, 0, // Skip to: 15099 /* 15080 */ MCD_OPC_CheckField, 17, 4, 0, 67, 5, 0, // Skip to: 16434 /* 15087 */ MCD_OPC_CheckField, 6, 3, 0, 60, 5, 0, // Skip to: 16434 /* 15094 */ MCD_OPC_Decode, 203, 15, 166, 1, // Opcode: XSRQPIX /* 15099 */ MCD_OPC_FilterValue, 12, 52, 0, 0, // Skip to: 15156 /* 15104 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... /* 15107 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 15123 /* 15112 */ MCD_OPC_CheckField, 12, 9, 0, 35, 5, 0, // Skip to: 16434 /* 15119 */ MCD_OPC_Decode, 198, 8, 110, // Opcode: MTFSB1 /* 15123 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 15139 /* 15128 */ MCD_OPC_CheckField, 12, 9, 0, 19, 5, 0, // Skip to: 16434 /* 15135 */ MCD_OPC_Decode, 197, 8, 110, // Opcode: MTFSB0 /* 15139 */ MCD_OPC_FilterValue, 4, 10, 5, 0, // Skip to: 16434 /* 15144 */ MCD_OPC_CheckField, 17, 6, 0, 3, 5, 0, // Skip to: 16434 /* 15151 */ MCD_OPC_Decode, 200, 8, 167, 1, // Opcode: MTFSFI /* 15156 */ MCD_OPC_FilterValue, 13, 19, 0, 0, // Skip to: 15180 /* 15161 */ MCD_OPC_CheckField, 17, 6, 0, 242, 4, 0, // Skip to: 16434 /* 15168 */ MCD_OPC_CheckField, 6, 6, 4, 235, 4, 0, // Skip to: 16434 /* 15175 */ MCD_OPC_Decode, 201, 8, 167, 1, // Opcode: MTFSFIo /* 15180 */ MCD_OPC_FilterValue, 14, 126, 0, 0, // Skip to: 15311 /* 15185 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15188 */ MCD_OPC_FilterValue, 18, 108, 0, 0, // Skip to: 15301 /* 15193 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... /* 15196 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15213 /* 15201 */ MCD_OPC_CheckField, 11, 5, 0, 202, 4, 0, // Skip to: 16434 /* 15208 */ MCD_OPC_Decode, 157, 8, 168, 1, // Opcode: MFFS /* 15213 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 15230 /* 15218 */ MCD_OPC_CheckField, 11, 5, 0, 185, 4, 0, // Skip to: 16434 /* 15225 */ MCD_OPC_Decode, 160, 8, 168, 1, // Opcode: MFFSCE /* 15230 */ MCD_OPC_FilterValue, 20, 5, 0, 0, // Skip to: 15240 /* 15235 */ MCD_OPC_Decode, 158, 8, 169, 1, // Opcode: MFFSCDRN /* 15240 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 15257 /* 15245 */ MCD_OPC_CheckField, 14, 2, 0, 158, 4, 0, // Skip to: 16434 /* 15252 */ MCD_OPC_Decode, 159, 8, 170, 1, // Opcode: MFFSCDRNI /* 15257 */ MCD_OPC_FilterValue, 22, 5, 0, 0, // Skip to: 15267 /* 15262 */ MCD_OPC_Decode, 161, 8, 169, 1, // Opcode: MFFSCRN /* 15267 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 15284 /* 15272 */ MCD_OPC_CheckField, 13, 3, 0, 131, 4, 0, // Skip to: 16434 /* 15279 */ MCD_OPC_Decode, 162, 8, 171, 1, // Opcode: MFFSCRNI /* 15284 */ MCD_OPC_FilterValue, 24, 121, 4, 0, // Skip to: 16434 /* 15289 */ MCD_OPC_CheckField, 11, 5, 0, 114, 4, 0, // Skip to: 16434 /* 15296 */ MCD_OPC_Decode, 163, 8, 168, 1, // Opcode: MFFSL /* 15301 */ MCD_OPC_FilterValue, 22, 104, 4, 0, // Skip to: 16434 /* 15306 */ MCD_OPC_Decode, 199, 8, 172, 1, // Opcode: MTFSF /* 15311 */ MCD_OPC_FilterValue, 15, 30, 0, 0, // Skip to: 15346 /* 15316 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15319 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 15336 /* 15324 */ MCD_OPC_CheckField, 11, 10, 0, 79, 4, 0, // Skip to: 16434 /* 15331 */ MCD_OPC_Decode, 164, 8, 168, 1, // Opcode: MFFSo /* 15336 */ MCD_OPC_FilterValue, 22, 69, 4, 0, // Skip to: 16434 /* 15341 */ MCD_OPC_Decode, 203, 8, 172, 1, // Opcode: MTFSFo /* 15346 */ MCD_OPC_FilterValue, 16, 140, 0, 0, // Skip to: 15491 /* 15351 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15354 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 15363 /* 15359 */ MCD_OPC_Decode, 167, 6, 125, // Opcode: FCPSGNS /* 15363 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 15379 /* 15368 */ MCD_OPC_CheckField, 16, 5, 0, 35, 4, 0, // Skip to: 16434 /* 15375 */ MCD_OPC_Decode, 209, 6, 126, // Opcode: FNEGS /* 15379 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 15395 /* 15384 */ MCD_OPC_CheckField, 16, 5, 0, 19, 4, 0, // Skip to: 16434 /* 15391 */ MCD_OPC_Decode, 193, 6, 126, // Opcode: FMR /* 15395 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 15411 /* 15400 */ MCD_OPC_CheckField, 16, 5, 0, 3, 4, 0, // Skip to: 16434 /* 15407 */ MCD_OPC_Decode, 205, 6, 126, // Opcode: FNABSS /* 15411 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 15427 /* 15416 */ MCD_OPC_CheckField, 16, 5, 0, 243, 3, 0, // Skip to: 16434 /* 15423 */ MCD_OPC_Decode, 148, 6, 126, // Opcode: FABSS /* 15427 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 15443 /* 15432 */ MCD_OPC_CheckField, 16, 5, 0, 227, 3, 0, // Skip to: 16434 /* 15439 */ MCD_OPC_Decode, 229, 6, 126, // Opcode: FRINS /* 15443 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 15459 /* 15448 */ MCD_OPC_CheckField, 16, 5, 0, 211, 3, 0, // Skip to: 16434 /* 15455 */ MCD_OPC_Decode, 237, 6, 126, // Opcode: FRIZS /* 15459 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 15475 /* 15464 */ MCD_OPC_CheckField, 16, 5, 0, 195, 3, 0, // Skip to: 16434 /* 15471 */ MCD_OPC_Decode, 233, 6, 126, // Opcode: FRIPS /* 15475 */ MCD_OPC_FilterValue, 15, 186, 3, 0, // Skip to: 16434 /* 15480 */ MCD_OPC_CheckField, 16, 5, 0, 179, 3, 0, // Skip to: 16434 /* 15487 */ MCD_OPC_Decode, 225, 6, 126, // Opcode: FRIMS /* 15491 */ MCD_OPC_FilterValue, 17, 140, 0, 0, // Skip to: 15636 /* 15496 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15499 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 15508 /* 15504 */ MCD_OPC_Decode, 168, 6, 125, // Opcode: FCPSGNSo /* 15508 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 15524 /* 15513 */ MCD_OPC_CheckField, 16, 5, 0, 146, 3, 0, // Skip to: 16434 /* 15520 */ MCD_OPC_Decode, 210, 6, 126, // Opcode: FNEGSo /* 15524 */ MCD_OPC_FilterValue, 2, 11, 0, 0, // Skip to: 15540 /* 15529 */ MCD_OPC_CheckField, 16, 5, 0, 130, 3, 0, // Skip to: 16434 /* 15536 */ MCD_OPC_Decode, 194, 6, 126, // Opcode: FMRo /* 15540 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 15556 /* 15545 */ MCD_OPC_CheckField, 16, 5, 0, 114, 3, 0, // Skip to: 16434 /* 15552 */ MCD_OPC_Decode, 206, 6, 126, // Opcode: FNABSSo /* 15556 */ MCD_OPC_FilterValue, 8, 11, 0, 0, // Skip to: 15572 /* 15561 */ MCD_OPC_CheckField, 16, 5, 0, 98, 3, 0, // Skip to: 16434 /* 15568 */ MCD_OPC_Decode, 149, 6, 126, // Opcode: FABSSo /* 15572 */ MCD_OPC_FilterValue, 12, 11, 0, 0, // Skip to: 15588 /* 15577 */ MCD_OPC_CheckField, 16, 5, 0, 82, 3, 0, // Skip to: 16434 /* 15584 */ MCD_OPC_Decode, 230, 6, 126, // Opcode: FRINSo /* 15588 */ MCD_OPC_FilterValue, 13, 11, 0, 0, // Skip to: 15604 /* 15593 */ MCD_OPC_CheckField, 16, 5, 0, 66, 3, 0, // Skip to: 16434 /* 15600 */ MCD_OPC_Decode, 238, 6, 126, // Opcode: FRIZSo /* 15604 */ MCD_OPC_FilterValue, 14, 11, 0, 0, // Skip to: 15620 /* 15609 */ MCD_OPC_CheckField, 16, 5, 0, 50, 3, 0, // Skip to: 16434 /* 15616 */ MCD_OPC_Decode, 234, 6, 126, // Opcode: FRIPSo /* 15620 */ MCD_OPC_FilterValue, 15, 41, 3, 0, // Skip to: 16434 /* 15625 */ MCD_OPC_CheckField, 16, 5, 0, 34, 3, 0, // Skip to: 16434 /* 15632 */ MCD_OPC_Decode, 226, 6, 126, // Opcode: FRIMSo /* 15636 */ MCD_OPC_FilterValue, 24, 18, 0, 0, // Skip to: 15659 /* 15641 */ MCD_OPC_CheckField, 16, 5, 0, 18, 3, 0, // Skip to: 16434 /* 15648 */ MCD_OPC_CheckField, 6, 5, 0, 11, 3, 0, // Skip to: 16434 /* 15655 */ MCD_OPC_Decode, 239, 6, 124, // Opcode: FRSP /* 15659 */ MCD_OPC_FilterValue, 25, 18, 0, 0, // Skip to: 15682 /* 15664 */ MCD_OPC_CheckField, 16, 5, 0, 251, 2, 0, // Skip to: 16434 /* 15671 */ MCD_OPC_CheckField, 6, 5, 0, 244, 2, 0, // Skip to: 16434 /* 15678 */ MCD_OPC_Decode, 240, 6, 124, // Opcode: FRSPo /* 15682 */ MCD_OPC_FilterValue, 28, 105, 0, 0, // Skip to: 15792 /* 15687 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15690 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15707 /* 15695 */ MCD_OPC_CheckField, 16, 5, 0, 220, 2, 0, // Skip to: 16434 /* 15702 */ MCD_OPC_Decode, 177, 6, 169, 1, // Opcode: FCTIW /* 15707 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15724 /* 15712 */ MCD_OPC_CheckField, 16, 5, 0, 203, 2, 0, // Skip to: 16434 /* 15719 */ MCD_OPC_Decode, 178, 6, 169, 1, // Opcode: FCTIWU /* 15724 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 15741 /* 15729 */ MCD_OPC_CheckField, 16, 5, 0, 186, 2, 0, // Skip to: 16434 /* 15736 */ MCD_OPC_Decode, 169, 6, 169, 1, // Opcode: FCTID /* 15741 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 15758 /* 15746 */ MCD_OPC_CheckField, 16, 5, 0, 169, 2, 0, // Skip to: 16434 /* 15753 */ MCD_OPC_Decode, 155, 6, 169, 1, // Opcode: FCFID /* 15758 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 15775 /* 15763 */ MCD_OPC_CheckField, 16, 5, 0, 152, 2, 0, // Skip to: 16434 /* 15770 */ MCD_OPC_Decode, 170, 6, 169, 1, // Opcode: FCTIDU /* 15775 */ MCD_OPC_FilterValue, 30, 142, 2, 0, // Skip to: 16434 /* 15780 */ MCD_OPC_CheckField, 16, 5, 0, 135, 2, 0, // Skip to: 16434 /* 15787 */ MCD_OPC_Decode, 158, 6, 169, 1, // Opcode: FCFIDU /* 15792 */ MCD_OPC_FilterValue, 29, 105, 0, 0, // Skip to: 15902 /* 15797 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15800 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15817 /* 15805 */ MCD_OPC_CheckField, 16, 5, 0, 110, 2, 0, // Skip to: 16434 /* 15812 */ MCD_OPC_Decode, 184, 6, 169, 1, // Opcode: FCTIWo /* 15817 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15834 /* 15822 */ MCD_OPC_CheckField, 16, 5, 0, 93, 2, 0, // Skip to: 16434 /* 15829 */ MCD_OPC_Decode, 181, 6, 169, 1, // Opcode: FCTIWUo /* 15834 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 15851 /* 15839 */ MCD_OPC_CheckField, 16, 5, 0, 76, 2, 0, // Skip to: 16434 /* 15846 */ MCD_OPC_Decode, 176, 6, 169, 1, // Opcode: FCTIDo /* 15851 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 15868 /* 15856 */ MCD_OPC_CheckField, 16, 5, 0, 59, 2, 0, // Skip to: 16434 /* 15863 */ MCD_OPC_Decode, 162, 6, 169, 1, // Opcode: FCFIDo /* 15868 */ MCD_OPC_FilterValue, 29, 12, 0, 0, // Skip to: 15885 /* 15873 */ MCD_OPC_CheckField, 16, 5, 0, 42, 2, 0, // Skip to: 16434 /* 15880 */ MCD_OPC_Decode, 173, 6, 169, 1, // Opcode: FCTIDUo /* 15885 */ MCD_OPC_FilterValue, 30, 32, 2, 0, // Skip to: 16434 /* 15890 */ MCD_OPC_CheckField, 16, 5, 0, 25, 2, 0, // Skip to: 16434 /* 15897 */ MCD_OPC_Decode, 161, 6, 169, 1, // Opcode: FCFIDUo /* 15902 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 15978 /* 15907 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15910 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 15927 /* 15915 */ MCD_OPC_CheckField, 16, 5, 0, 0, 2, 0, // Skip to: 16434 /* 15922 */ MCD_OPC_Decode, 182, 6, 169, 1, // Opcode: FCTIWZ /* 15927 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 15944 /* 15932 */ MCD_OPC_CheckField, 16, 5, 0, 239, 1, 0, // Skip to: 16434 /* 15939 */ MCD_OPC_Decode, 179, 6, 169, 1, // Opcode: FCTIWUZ /* 15944 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 15961 /* 15949 */ MCD_OPC_CheckField, 16, 5, 0, 222, 1, 0, // Skip to: 16434 /* 15956 */ MCD_OPC_Decode, 174, 6, 169, 1, // Opcode: FCTIDZ /* 15961 */ MCD_OPC_FilterValue, 29, 212, 1, 0, // Skip to: 16434 /* 15966 */ MCD_OPC_CheckField, 16, 5, 0, 205, 1, 0, // Skip to: 16434 /* 15973 */ MCD_OPC_Decode, 171, 6, 169, 1, // Opcode: FCTIDUZ /* 15978 */ MCD_OPC_FilterValue, 31, 71, 0, 0, // Skip to: 16054 /* 15983 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 15986 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 16003 /* 15991 */ MCD_OPC_CheckField, 16, 5, 0, 180, 1, 0, // Skip to: 16434 /* 15998 */ MCD_OPC_Decode, 183, 6, 169, 1, // Opcode: FCTIWZo /* 16003 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 16020 /* 16008 */ MCD_OPC_CheckField, 16, 5, 0, 163, 1, 0, // Skip to: 16434 /* 16015 */ MCD_OPC_Decode, 180, 6, 169, 1, // Opcode: FCTIWUZo /* 16020 */ MCD_OPC_FilterValue, 25, 12, 0, 0, // Skip to: 16037 /* 16025 */ MCD_OPC_CheckField, 16, 5, 0, 146, 1, 0, // Skip to: 16434 /* 16032 */ MCD_OPC_Decode, 175, 6, 169, 1, // Opcode: FCTIDZo /* 16037 */ MCD_OPC_FilterValue, 29, 136, 1, 0, // Skip to: 16434 /* 16042 */ MCD_OPC_CheckField, 16, 5, 0, 129, 1, 0, // Skip to: 16434 /* 16049 */ MCD_OPC_Decode, 172, 6, 169, 1, // Opcode: FCTIDUZo /* 16054 */ MCD_OPC_FilterValue, 36, 12, 0, 0, // Skip to: 16071 /* 16059 */ MCD_OPC_CheckField, 6, 5, 0, 112, 1, 0, // Skip to: 16434 /* 16066 */ MCD_OPC_Decode, 185, 6, 173, 1, // Opcode: FDIV /* 16071 */ MCD_OPC_FilterValue, 37, 12, 0, 0, // Skip to: 16088 /* 16076 */ MCD_OPC_CheckField, 6, 5, 0, 95, 1, 0, // Skip to: 16434 /* 16083 */ MCD_OPC_Decode, 188, 6, 173, 1, // Opcode: FDIVo /* 16088 */ MCD_OPC_FilterValue, 40, 12, 0, 0, // Skip to: 16105 /* 16093 */ MCD_OPC_CheckField, 6, 5, 0, 78, 1, 0, // Skip to: 16434 /* 16100 */ MCD_OPC_Decode, 253, 6, 173, 1, // Opcode: FSUB /* 16105 */ MCD_OPC_FilterValue, 41, 12, 0, 0, // Skip to: 16122 /* 16110 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, 0, // Skip to: 16434 /* 16117 */ MCD_OPC_Decode, 128, 7, 173, 1, // Opcode: FSUBo /* 16122 */ MCD_OPC_FilterValue, 42, 12, 0, 0, // Skip to: 16139 /* 16127 */ MCD_OPC_CheckField, 6, 5, 0, 44, 1, 0, // Skip to: 16434 /* 16134 */ MCD_OPC_Decode, 150, 6, 173, 1, // Opcode: FADD /* 16139 */ MCD_OPC_FilterValue, 43, 12, 0, 0, // Skip to: 16156 /* 16144 */ MCD_OPC_CheckField, 6, 5, 0, 27, 1, 0, // Skip to: 16434 /* 16151 */ MCD_OPC_Decode, 153, 6, 173, 1, // Opcode: FADDo /* 16156 */ MCD_OPC_FilterValue, 44, 19, 0, 0, // Skip to: 16180 /* 16161 */ MCD_OPC_CheckField, 16, 5, 0, 10, 1, 0, // Skip to: 16434 /* 16168 */ MCD_OPC_CheckField, 6, 5, 0, 3, 1, 0, // Skip to: 16434 /* 16175 */ MCD_OPC_Decode, 249, 6, 169, 1, // Opcode: FSQRT /* 16180 */ MCD_OPC_FilterValue, 45, 19, 0, 0, // Skip to: 16204 /* 16185 */ MCD_OPC_CheckField, 16, 5, 0, 242, 0, 0, // Skip to: 16434 /* 16192 */ MCD_OPC_CheckField, 6, 5, 0, 235, 0, 0, // Skip to: 16434 /* 16199 */ MCD_OPC_Decode, 252, 6, 169, 1, // Opcode: FSQRTo /* 16204 */ MCD_OPC_FilterValue, 46, 5, 0, 0, // Skip to: 16214 /* 16209 */ MCD_OPC_Decode, 247, 6, 174, 1, // Opcode: FSELS /* 16214 */ MCD_OPC_FilterValue, 47, 5, 0, 0, // Skip to: 16224 /* 16219 */ MCD_OPC_Decode, 248, 6, 174, 1, // Opcode: FSELSo /* 16224 */ MCD_OPC_FilterValue, 48, 19, 0, 0, // Skip to: 16248 /* 16229 */ MCD_OPC_CheckField, 16, 5, 0, 198, 0, 0, // Skip to: 16434 /* 16236 */ MCD_OPC_CheckField, 6, 5, 0, 191, 0, 0, // Skip to: 16434 /* 16243 */ MCD_OPC_Decode, 219, 6, 169, 1, // Opcode: FRE /* 16248 */ MCD_OPC_FilterValue, 49, 19, 0, 0, // Skip to: 16272 /* 16253 */ MCD_OPC_CheckField, 16, 5, 0, 174, 0, 0, // Skip to: 16434 /* 16260 */ MCD_OPC_CheckField, 6, 5, 0, 167, 0, 0, // Skip to: 16434 /* 16267 */ MCD_OPC_Decode, 222, 6, 169, 1, // Opcode: FREo /* 16272 */ MCD_OPC_FilterValue, 50, 12, 0, 0, // Skip to: 16289 /* 16277 */ MCD_OPC_CheckField, 11, 5, 0, 150, 0, 0, // Skip to: 16434 /* 16284 */ MCD_OPC_Decode, 199, 6, 175, 1, // Opcode: FMUL /* 16289 */ MCD_OPC_FilterValue, 51, 12, 0, 0, // Skip to: 16306 /* 16294 */ MCD_OPC_CheckField, 11, 5, 0, 133, 0, 0, // Skip to: 16434 /* 16301 */ MCD_OPC_Decode, 202, 6, 175, 1, // Opcode: FMULo /* 16306 */ MCD_OPC_FilterValue, 52, 19, 0, 0, // Skip to: 16330 /* 16311 */ MCD_OPC_CheckField, 16, 5, 0, 116, 0, 0, // Skip to: 16434 /* 16318 */ MCD_OPC_CheckField, 6, 5, 0, 109, 0, 0, // Skip to: 16434 /* 16325 */ MCD_OPC_Decode, 241, 6, 169, 1, // Opcode: FRSQRTE /* 16330 */ MCD_OPC_FilterValue, 53, 19, 0, 0, // Skip to: 16354 /* 16335 */ MCD_OPC_CheckField, 16, 5, 0, 92, 0, 0, // Skip to: 16434 /* 16342 */ MCD_OPC_CheckField, 6, 5, 0, 85, 0, 0, // Skip to: 16434 /* 16349 */ MCD_OPC_Decode, 244, 6, 169, 1, // Opcode: FRSQRTEo /* 16354 */ MCD_OPC_FilterValue, 56, 5, 0, 0, // Skip to: 16364 /* 16359 */ MCD_OPC_Decode, 195, 6, 176, 1, // Opcode: FMSUB /* 16364 */ MCD_OPC_FilterValue, 57, 5, 0, 0, // Skip to: 16374 /* 16369 */ MCD_OPC_Decode, 198, 6, 176, 1, // Opcode: FMSUBo /* 16374 */ MCD_OPC_FilterValue, 58, 5, 0, 0, // Skip to: 16384 /* 16379 */ MCD_OPC_Decode, 189, 6, 176, 1, // Opcode: FMADD /* 16384 */ MCD_OPC_FilterValue, 59, 5, 0, 0, // Skip to: 16394 /* 16389 */ MCD_OPC_Decode, 192, 6, 176, 1, // Opcode: FMADDo /* 16394 */ MCD_OPC_FilterValue, 60, 5, 0, 0, // Skip to: 16404 /* 16399 */ MCD_OPC_Decode, 215, 6, 176, 1, // Opcode: FNMSUB /* 16404 */ MCD_OPC_FilterValue, 61, 5, 0, 0, // Skip to: 16414 /* 16409 */ MCD_OPC_Decode, 218, 6, 176, 1, // Opcode: FNMSUBo /* 16414 */ MCD_OPC_FilterValue, 62, 5, 0, 0, // Skip to: 16424 /* 16419 */ MCD_OPC_Decode, 211, 6, 176, 1, // Opcode: FNMADD /* 16424 */ MCD_OPC_FilterValue, 63, 5, 0, 0, // Skip to: 16434 /* 16429 */ MCD_OPC_Decode, 214, 6, 176, 1, // Opcode: FNMADDo /* 16434 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableQPX32[] = { /* 0 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... /* 3 */ MCD_OPC_FilterValue, 0, 71, 0, 0, // Skip to: 79 /* 8 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 11 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 28 /* 16 */ MCD_OPC_CheckField, 26, 6, 4, 186, 8, 0, // Skip to: 2257 /* 23 */ MCD_OPC_Decode, 162, 9, 177, 1, // Opcode: QVFCMPEQb /* 28 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 45 /* 33 */ MCD_OPC_CheckField, 26, 6, 4, 169, 8, 0, // Skip to: 2257 /* 40 */ MCD_OPC_Decode, 165, 9, 177, 1, // Opcode: QVFCMPGTb /* 45 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 62 /* 50 */ MCD_OPC_CheckField, 26, 6, 4, 152, 8, 0, // Skip to: 2257 /* 57 */ MCD_OPC_Decode, 232, 9, 177, 1, // Opcode: QVFTSTNANb /* 62 */ MCD_OPC_FilterValue, 3, 142, 8, 0, // Skip to: 2257 /* 67 */ MCD_OPC_CheckField, 26, 6, 4, 135, 8, 0, // Skip to: 2257 /* 74 */ MCD_OPC_Decode, 168, 9, 177, 1, // Opcode: QVFCMPLTb /* 79 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 107 /* 84 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 87 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 97 /* 92 */ MCD_OPC_Decode, 241, 9, 178, 1, // Opcode: QVFXXMADDS /* 97 */ MCD_OPC_FilterValue, 4, 107, 8, 0, // Skip to: 2257 /* 102 */ MCD_OPC_Decode, 240, 9, 178, 1, // Opcode: QVFXXMADD /* 107 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 135 /* 112 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 115 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 125 /* 120 */ MCD_OPC_Decode, 239, 9, 178, 1, // Opcode: QVFXXCPNMADDS /* 125 */ MCD_OPC_FilterValue, 4, 79, 8, 0, // Skip to: 2257 /* 130 */ MCD_OPC_Decode, 238, 9, 178, 1, // Opcode: QVFXXCPNMADD /* 135 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 159 /* 140 */ MCD_OPC_CheckField, 26, 6, 4, 62, 8, 0, // Skip to: 2257 /* 147 */ MCD_OPC_CheckField, 6, 1, 0, 55, 8, 0, // Skip to: 2257 /* 154 */ MCD_OPC_Decode, 182, 9, 179, 1, // Opcode: QVFLOGICALb /* 159 */ MCD_OPC_FilterValue, 10, 216, 0, 0, // Skip to: 380 /* 164 */ MCD_OPC_ExtractField, 6, 3, // Inst{8-6} ... /* 167 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 184 /* 172 */ MCD_OPC_CheckField, 26, 6, 4, 30, 8, 0, // Skip to: 2257 /* 179 */ MCD_OPC_Decode, 145, 9, 180, 1, // Opcode: QVALIGNI /* 184 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 208 /* 189 */ MCD_OPC_CheckField, 26, 6, 4, 13, 8, 0, // Skip to: 2257 /* 196 */ MCD_OPC_CheckField, 11, 5, 0, 6, 8, 0, // Skip to: 2257 /* 203 */ MCD_OPC_Decode, 148, 9, 181, 1, // Opcode: QVESPLATI /* 208 */ MCD_OPC_FilterValue, 4, 41, 0, 0, // Skip to: 254 /* 213 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 216 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 226 /* 221 */ MCD_OPC_Decode, 244, 9, 182, 1, // Opcode: QVGPCI /* 226 */ MCD_OPC_FilterValue, 31, 234, 7, 0, // Skip to: 2257 /* 231 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 234 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 244 /* 239 */ MCD_OPC_Decode, 160, 10, 183, 1, // Opcode: QVSTFCSXI /* 244 */ MCD_OPC_FilterValue, 2, 216, 7, 0, // Skip to: 2257 /* 249 */ MCD_OPC_Decode, 181, 10, 183, 1, // Opcode: QVSTFSXI /* 254 */ MCD_OPC_FilterValue, 5, 37, 0, 0, // Skip to: 296 /* 259 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 262 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 279 /* 267 */ MCD_OPC_CheckField, 26, 6, 31, 191, 7, 0, // Skip to: 2257 /* 274 */ MCD_OPC_Decode, 156, 10, 183, 1, // Opcode: QVSTFCSUXI /* 279 */ MCD_OPC_FilterValue, 2, 181, 7, 0, // Skip to: 2257 /* 284 */ MCD_OPC_CheckField, 26, 6, 31, 174, 7, 0, // Skip to: 2257 /* 291 */ MCD_OPC_Decode, 176, 10, 183, 1, // Opcode: QVSTFSUXI /* 296 */ MCD_OPC_FilterValue, 6, 37, 0, 0, // Skip to: 338 /* 301 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 304 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 321 /* 309 */ MCD_OPC_CheckField, 26, 6, 31, 149, 7, 0, // Skip to: 2257 /* 316 */ MCD_OPC_Decode, 152, 10, 183, 1, // Opcode: QVSTFCDXI /* 321 */ MCD_OPC_FilterValue, 2, 139, 7, 0, // Skip to: 2257 /* 326 */ MCD_OPC_CheckField, 26, 6, 31, 132, 7, 0, // Skip to: 2257 /* 333 */ MCD_OPC_Decode, 169, 10, 183, 1, // Opcode: QVSTFDXI /* 338 */ MCD_OPC_FilterValue, 7, 122, 7, 0, // Skip to: 2257 /* 343 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... /* 346 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 363 /* 351 */ MCD_OPC_CheckField, 26, 6, 31, 107, 7, 0, // Skip to: 2257 /* 358 */ MCD_OPC_Decode, 148, 10, 183, 1, // Opcode: QVSTFCDUXI /* 363 */ MCD_OPC_FilterValue, 2, 97, 7, 0, // Skip to: 2257 /* 368 */ MCD_OPC_CheckField, 26, 6, 31, 90, 7, 0, // Skip to: 2257 /* 375 */ MCD_OPC_Decode, 165, 10, 183, 1, // Opcode: QVSTFDUXI /* 380 */ MCD_OPC_FilterValue, 11, 139, 0, 0, // Skip to: 524 /* 385 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 388 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 405 /* 393 */ MCD_OPC_CheckField, 26, 6, 31, 65, 7, 0, // Skip to: 2257 /* 400 */ MCD_OPC_Decode, 161, 10, 183, 1, // Opcode: QVSTFCSXIA /* 405 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 422 /* 410 */ MCD_OPC_CheckField, 26, 6, 31, 48, 7, 0, // Skip to: 2257 /* 417 */ MCD_OPC_Decode, 157, 10, 183, 1, // Opcode: QVSTFCSUXIA /* 422 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 439 /* 427 */ MCD_OPC_CheckField, 26, 6, 31, 31, 7, 0, // Skip to: 2257 /* 434 */ MCD_OPC_Decode, 153, 10, 183, 1, // Opcode: QVSTFCDXIA /* 439 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 456 /* 444 */ MCD_OPC_CheckField, 26, 6, 31, 14, 7, 0, // Skip to: 2257 /* 451 */ MCD_OPC_Decode, 149, 10, 183, 1, // Opcode: QVSTFCDUXIA /* 456 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 473 /* 461 */ MCD_OPC_CheckField, 26, 6, 31, 253, 6, 0, // Skip to: 2257 /* 468 */ MCD_OPC_Decode, 182, 10, 183, 1, // Opcode: QVSTFSXIA /* 473 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 490 /* 478 */ MCD_OPC_CheckField, 26, 6, 31, 236, 6, 0, // Skip to: 2257 /* 485 */ MCD_OPC_Decode, 177, 10, 183, 1, // Opcode: QVSTFSUXIA /* 490 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 507 /* 495 */ MCD_OPC_CheckField, 26, 6, 31, 219, 6, 0, // Skip to: 2257 /* 502 */ MCD_OPC_Decode, 170, 10, 183, 1, // Opcode: QVSTFDXIA /* 507 */ MCD_OPC_FilterValue, 23, 209, 6, 0, // Skip to: 2257 /* 512 */ MCD_OPC_CheckField, 26, 6, 31, 202, 6, 0, // Skip to: 2257 /* 519 */ MCD_OPC_Decode, 166, 10, 183, 1, // Opcode: QVSTFDUXIA /* 524 */ MCD_OPC_FilterValue, 12, 61, 0, 0, // Skip to: 590 /* 529 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 532 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 542 /* 537 */ MCD_OPC_Decode, 206, 9, 178, 1, // Opcode: QVFPERM /* 542 */ MCD_OPC_FilterValue, 31, 174, 6, 0, // Skip to: 2257 /* 547 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 550 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 560 /* 555 */ MCD_OPC_Decode, 145, 10, 183, 1, // Opcode: QVLPCRSX /* 560 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 570 /* 565 */ MCD_OPC_Decode, 144, 10, 183, 1, // Opcode: QVLPCRDX /* 570 */ MCD_OPC_FilterValue, 16, 5, 0, 0, // Skip to: 580 /* 575 */ MCD_OPC_Decode, 142, 10, 183, 1, // Opcode: QVLPCLSX /* 580 */ MCD_OPC_FilterValue, 18, 136, 6, 0, // Skip to: 2257 /* 585 */ MCD_OPC_Decode, 141, 10, 183, 1, // Opcode: QVLPCLDX /* 590 */ MCD_OPC_FilterValue, 14, 70, 1, 0, // Skip to: 921 /* 595 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 598 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 615 /* 603 */ MCD_OPC_CheckField, 26, 6, 31, 111, 6, 0, // Skip to: 2257 /* 610 */ MCD_OPC_Decode, 251, 9, 183, 1, // Opcode: QVLFCSX /* 615 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 632 /* 620 */ MCD_OPC_CheckField, 26, 6, 31, 94, 6, 0, // Skip to: 2257 /* 627 */ MCD_OPC_Decode, 249, 9, 183, 1, // Opcode: QVLFCSUX /* 632 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 649 /* 637 */ MCD_OPC_CheckField, 26, 6, 31, 77, 6, 0, // Skip to: 2257 /* 644 */ MCD_OPC_Decode, 247, 9, 183, 1, // Opcode: QVLFCDX /* 649 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 666 /* 654 */ MCD_OPC_CheckField, 26, 6, 31, 60, 6, 0, // Skip to: 2257 /* 661 */ MCD_OPC_Decode, 245, 9, 183, 1, // Opcode: QVLFCDUX /* 666 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 683 /* 671 */ MCD_OPC_CheckField, 26, 6, 31, 43, 6, 0, // Skip to: 2257 /* 678 */ MCD_OPC_Decode, 158, 10, 183, 1, // Opcode: QVSTFCSX /* 683 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 700 /* 688 */ MCD_OPC_CheckField, 26, 6, 31, 26, 6, 0, // Skip to: 2257 /* 695 */ MCD_OPC_Decode, 154, 10, 183, 1, // Opcode: QVSTFCSUX /* 700 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 717 /* 705 */ MCD_OPC_CheckField, 26, 6, 31, 9, 6, 0, // Skip to: 2257 /* 712 */ MCD_OPC_Decode, 150, 10, 183, 1, // Opcode: QVSTFCDX /* 717 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 734 /* 722 */ MCD_OPC_CheckField, 26, 6, 31, 248, 5, 0, // Skip to: 2257 /* 729 */ MCD_OPC_Decode, 146, 10, 183, 1, // Opcode: QVSTFCDUX /* 734 */ MCD_OPC_FilterValue, 16, 12, 0, 0, // Skip to: 751 /* 739 */ MCD_OPC_CheckField, 26, 6, 31, 231, 5, 0, // Skip to: 2257 /* 746 */ MCD_OPC_Decode, 137, 10, 183, 1, // Opcode: QVLFSX /* 751 */ MCD_OPC_FilterValue, 17, 12, 0, 0, // Skip to: 768 /* 756 */ MCD_OPC_CheckField, 26, 6, 31, 214, 5, 0, // Skip to: 2257 /* 763 */ MCD_OPC_Decode, 135, 10, 184, 1, // Opcode: QVLFSUX /* 768 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 785 /* 773 */ MCD_OPC_CheckField, 26, 6, 31, 197, 5, 0, // Skip to: 2257 /* 780 */ MCD_OPC_Decode, 128, 10, 183, 1, // Opcode: QVLFDX /* 785 */ MCD_OPC_FilterValue, 19, 12, 0, 0, // Skip to: 802 /* 790 */ MCD_OPC_CheckField, 26, 6, 31, 180, 5, 0, // Skip to: 2257 /* 797 */ MCD_OPC_Decode, 254, 9, 185, 1, // Opcode: QVLFDUX /* 802 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 819 /* 807 */ MCD_OPC_CheckField, 26, 6, 31, 163, 5, 0, // Skip to: 2257 /* 814 */ MCD_OPC_Decode, 179, 10, 183, 1, // Opcode: QVSTFSX /* 819 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 836 /* 824 */ MCD_OPC_CheckField, 26, 6, 31, 146, 5, 0, // Skip to: 2257 /* 831 */ MCD_OPC_Decode, 174, 10, 186, 1, // Opcode: QVSTFSUX /* 836 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 853 /* 841 */ MCD_OPC_CheckField, 26, 6, 31, 129, 5, 0, // Skip to: 2257 /* 848 */ MCD_OPC_Decode, 167, 10, 183, 1, // Opcode: QVSTFDX /* 853 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 870 /* 858 */ MCD_OPC_CheckField, 26, 6, 31, 112, 5, 0, // Skip to: 2257 /* 865 */ MCD_OPC_Decode, 163, 10, 187, 1, // Opcode: QVSTFDUX /* 870 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 887 /* 875 */ MCD_OPC_CheckField, 26, 6, 31, 95, 5, 0, // Skip to: 2257 /* 882 */ MCD_OPC_Decode, 133, 10, 183, 1, // Opcode: QVLFIWZX /* 887 */ MCD_OPC_FilterValue, 27, 12, 0, 0, // Skip to: 904 /* 892 */ MCD_OPC_CheckField, 26, 6, 31, 78, 5, 0, // Skip to: 2257 /* 899 */ MCD_OPC_Decode, 131, 10, 183, 1, // Opcode: QVLFIWAX /* 904 */ MCD_OPC_FilterValue, 30, 68, 5, 0, // Skip to: 2257 /* 909 */ MCD_OPC_CheckField, 26, 6, 31, 61, 5, 0, // Skip to: 2257 /* 916 */ MCD_OPC_Decode, 172, 10, 183, 1, // Opcode: QVSTFIWX /* 921 */ MCD_OPC_FilterValue, 15, 70, 1, 0, // Skip to: 1252 /* 926 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 929 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 946 /* 934 */ MCD_OPC_CheckField, 26, 6, 31, 36, 5, 0, // Skip to: 2257 /* 941 */ MCD_OPC_Decode, 252, 9, 183, 1, // Opcode: QVLFCSXA /* 946 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 963 /* 951 */ MCD_OPC_CheckField, 26, 6, 31, 19, 5, 0, // Skip to: 2257 /* 958 */ MCD_OPC_Decode, 250, 9, 183, 1, // Opcode: QVLFCSUXA /* 963 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 980 /* 968 */ MCD_OPC_CheckField, 26, 6, 31, 2, 5, 0, // Skip to: 2257 /* 975 */ MCD_OPC_Decode, 248, 9, 183, 1, // Opcode: QVLFCDXA /* 980 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 997 /* 985 */ MCD_OPC_CheckField, 26, 6, 31, 241, 4, 0, // Skip to: 2257 /* 992 */ MCD_OPC_Decode, 246, 9, 183, 1, // Opcode: QVLFCDUXA /* 997 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 1014 /* 1002 */ MCD_OPC_CheckField, 26, 6, 31, 224, 4, 0, // Skip to: 2257 /* 1009 */ MCD_OPC_Decode, 159, 10, 183, 1, // Opcode: QVSTFCSXA /* 1014 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 1031 /* 1019 */ MCD_OPC_CheckField, 26, 6, 31, 207, 4, 0, // Skip to: 2257 /* 1026 */ MCD_OPC_Decode, 155, 10, 183, 1, // Opcode: QVSTFCSUXA /* 1031 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 1048 /* 1036 */ MCD_OPC_CheckField, 26, 6, 31, 190, 4, 0, // Skip to: 2257 /* 1043 */ MCD_OPC_Decode, 151, 10, 183, 1, // Opcode: QVSTFCDXA /* 1048 */ MCD_OPC_FilterValue, 7, 12, 0, 0, // Skip to: 1065 /* 1053 */ MCD_OPC_CheckField, 26, 6, 31, 173, 4, 0, // Skip to: 2257 /* 1060 */ MCD_OPC_Decode, 147, 10, 183, 1, // Opcode: QVSTFCDUXA /* 1065 */ MCD_OPC_FilterValue, 16, 12, 0, 0, // Skip to: 1082 /* 1070 */ MCD_OPC_CheckField, 26, 6, 31, 156, 4, 0, // Skip to: 2257 /* 1077 */ MCD_OPC_Decode, 138, 10, 183, 1, // Opcode: QVLFSXA /* 1082 */ MCD_OPC_FilterValue, 17, 12, 0, 0, // Skip to: 1099 /* 1087 */ MCD_OPC_CheckField, 26, 6, 31, 139, 4, 0, // Skip to: 2257 /* 1094 */ MCD_OPC_Decode, 136, 10, 183, 1, // Opcode: QVLFSUXA /* 1099 */ MCD_OPC_FilterValue, 18, 12, 0, 0, // Skip to: 1116 /* 1104 */ MCD_OPC_CheckField, 26, 6, 31, 122, 4, 0, // Skip to: 2257 /* 1111 */ MCD_OPC_Decode, 129, 10, 183, 1, // Opcode: QVLFDXA /* 1116 */ MCD_OPC_FilterValue, 19, 12, 0, 0, // Skip to: 1133 /* 1121 */ MCD_OPC_CheckField, 26, 6, 31, 105, 4, 0, // Skip to: 2257 /* 1128 */ MCD_OPC_Decode, 255, 9, 183, 1, // Opcode: QVLFDUXA /* 1133 */ MCD_OPC_FilterValue, 20, 12, 0, 0, // Skip to: 1150 /* 1138 */ MCD_OPC_CheckField, 26, 6, 31, 88, 4, 0, // Skip to: 2257 /* 1145 */ MCD_OPC_Decode, 180, 10, 183, 1, // Opcode: QVSTFSXA /* 1150 */ MCD_OPC_FilterValue, 21, 12, 0, 0, // Skip to: 1167 /* 1155 */ MCD_OPC_CheckField, 26, 6, 31, 71, 4, 0, // Skip to: 2257 /* 1162 */ MCD_OPC_Decode, 175, 10, 183, 1, // Opcode: QVSTFSUXA /* 1167 */ MCD_OPC_FilterValue, 22, 12, 0, 0, // Skip to: 1184 /* 1172 */ MCD_OPC_CheckField, 26, 6, 31, 54, 4, 0, // Skip to: 2257 /* 1179 */ MCD_OPC_Decode, 168, 10, 183, 1, // Opcode: QVSTFDXA /* 1184 */ MCD_OPC_FilterValue, 23, 12, 0, 0, // Skip to: 1201 /* 1189 */ MCD_OPC_CheckField, 26, 6, 31, 37, 4, 0, // Skip to: 2257 /* 1196 */ MCD_OPC_Decode, 164, 10, 183, 1, // Opcode: QVSTFDUXA /* 1201 */ MCD_OPC_FilterValue, 26, 12, 0, 0, // Skip to: 1218 /* 1206 */ MCD_OPC_CheckField, 26, 6, 31, 20, 4, 0, // Skip to: 2257 /* 1213 */ MCD_OPC_Decode, 134, 10, 183, 1, // Opcode: QVLFIWZXA /* 1218 */ MCD_OPC_FilterValue, 27, 12, 0, 0, // Skip to: 1235 /* 1223 */ MCD_OPC_CheckField, 26, 6, 31, 3, 4, 0, // Skip to: 2257 /* 1230 */ MCD_OPC_Decode, 132, 10, 183, 1, // Opcode: QVLFIWAXA /* 1235 */ MCD_OPC_FilterValue, 30, 249, 3, 0, // Skip to: 2257 /* 1240 */ MCD_OPC_CheckField, 26, 6, 31, 242, 3, 0, // Skip to: 2257 /* 1247 */ MCD_OPC_Decode, 173, 10, 183, 1, // Opcode: QVSTFIWXA /* 1252 */ MCD_OPC_FilterValue, 16, 212, 0, 0, // Skip to: 1469 /* 1257 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1260 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1277 /* 1265 */ MCD_OPC_CheckField, 26, 6, 4, 217, 3, 0, // Skip to: 2257 /* 1272 */ MCD_OPC_Decode, 170, 9, 188, 1, // Opcode: QVFCPSGN /* 1277 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 1301 /* 1282 */ MCD_OPC_CheckField, 26, 6, 4, 200, 3, 0, // Skip to: 2257 /* 1289 */ MCD_OPC_CheckField, 16, 5, 0, 193, 3, 0, // Skip to: 2257 /* 1296 */ MCD_OPC_Decode, 198, 9, 189, 1, // Opcode: QVFNEG /* 1301 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1325 /* 1306 */ MCD_OPC_CheckField, 26, 6, 4, 176, 3, 0, // Skip to: 2257 /* 1313 */ MCD_OPC_CheckField, 16, 5, 0, 169, 3, 0, // Skip to: 2257 /* 1320 */ MCD_OPC_Decode, 187, 9, 189, 1, // Opcode: QVFMR /* 1325 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1349 /* 1330 */ MCD_OPC_CheckField, 26, 6, 4, 152, 3, 0, // Skip to: 2257 /* 1337 */ MCD_OPC_CheckField, 16, 5, 0, 145, 3, 0, // Skip to: 2257 /* 1344 */ MCD_OPC_Decode, 196, 9, 189, 1, // Opcode: QVFNABS /* 1349 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 1373 /* 1354 */ MCD_OPC_CheckField, 26, 6, 4, 128, 3, 0, // Skip to: 2257 /* 1361 */ MCD_OPC_CheckField, 16, 5, 0, 121, 3, 0, // Skip to: 2257 /* 1368 */ MCD_OPC_Decode, 151, 9, 189, 1, // Opcode: QVFABS /* 1373 */ MCD_OPC_FilterValue, 12, 19, 0, 0, // Skip to: 1397 /* 1378 */ MCD_OPC_CheckField, 26, 6, 4, 104, 3, 0, // Skip to: 2257 /* 1385 */ MCD_OPC_CheckField, 16, 5, 0, 97, 3, 0, // Skip to: 2257 /* 1392 */ MCD_OPC_Decode, 213, 9, 189, 1, // Opcode: QVFRIN /* 1397 */ MCD_OPC_FilterValue, 13, 19, 0, 0, // Skip to: 1421 /* 1402 */ MCD_OPC_CheckField, 26, 6, 4, 80, 3, 0, // Skip to: 2257 /* 1409 */ MCD_OPC_CheckField, 16, 5, 0, 73, 3, 0, // Skip to: 2257 /* 1416 */ MCD_OPC_Decode, 217, 9, 189, 1, // Opcode: QVFRIZ /* 1421 */ MCD_OPC_FilterValue, 14, 19, 0, 0, // Skip to: 1445 /* 1426 */ MCD_OPC_CheckField, 26, 6, 4, 56, 3, 0, // Skip to: 2257 /* 1433 */ MCD_OPC_CheckField, 16, 5, 0, 49, 3, 0, // Skip to: 2257 /* 1440 */ MCD_OPC_Decode, 215, 9, 189, 1, // Opcode: QVFRIP /* 1445 */ MCD_OPC_FilterValue, 15, 39, 3, 0, // Skip to: 2257 /* 1450 */ MCD_OPC_CheckField, 26, 6, 4, 32, 3, 0, // Skip to: 2257 /* 1457 */ MCD_OPC_CheckField, 16, 5, 0, 25, 3, 0, // Skip to: 2257 /* 1464 */ MCD_OPC_Decode, 211, 9, 189, 1, // Opcode: QVFRIM /* 1469 */ MCD_OPC_FilterValue, 18, 23, 0, 0, // Skip to: 1497 /* 1474 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1477 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 1487 /* 1482 */ MCD_OPC_Decode, 235, 9, 178, 1, // Opcode: QVFXMADDS /* 1487 */ MCD_OPC_FilterValue, 4, 253, 2, 0, // Skip to: 2257 /* 1492 */ MCD_OPC_Decode, 234, 9, 178, 1, // Opcode: QVFXMADD /* 1497 */ MCD_OPC_FilterValue, 22, 23, 0, 0, // Skip to: 1525 /* 1502 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1505 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 1515 /* 1510 */ MCD_OPC_Decode, 243, 9, 178, 1, // Opcode: QVFXXNPMADDS /* 1515 */ MCD_OPC_FilterValue, 4, 225, 2, 0, // Skip to: 2257 /* 1520 */ MCD_OPC_Decode, 242, 9, 178, 1, // Opcode: QVFXXNPMADD /* 1525 */ MCD_OPC_FilterValue, 24, 26, 0, 0, // Skip to: 1556 /* 1530 */ MCD_OPC_CheckField, 26, 6, 4, 208, 2, 0, // Skip to: 2257 /* 1537 */ MCD_OPC_CheckField, 16, 5, 0, 201, 2, 0, // Skip to: 2257 /* 1544 */ MCD_OPC_CheckField, 6, 5, 0, 194, 2, 0, // Skip to: 2257 /* 1551 */ MCD_OPC_Decode, 220, 9, 190, 1, // Opcode: QVFRSPs /* 1556 */ MCD_OPC_FilterValue, 28, 183, 0, 0, // Skip to: 1744 /* 1561 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1564 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1588 /* 1569 */ MCD_OPC_CheckField, 26, 6, 4, 169, 2, 0, // Skip to: 2257 /* 1576 */ MCD_OPC_CheckField, 16, 5, 0, 162, 2, 0, // Skip to: 2257 /* 1583 */ MCD_OPC_Decode, 177, 9, 189, 1, // Opcode: QVFCTIW /* 1588 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1612 /* 1593 */ MCD_OPC_CheckField, 26, 6, 4, 145, 2, 0, // Skip to: 2257 /* 1600 */ MCD_OPC_CheckField, 16, 5, 0, 138, 2, 0, // Skip to: 2257 /* 1607 */ MCD_OPC_Decode, 178, 9, 189, 1, // Opcode: QVFCTIWU /* 1612 */ MCD_OPC_FilterValue, 25, 19, 0, 0, // Skip to: 1636 /* 1617 */ MCD_OPC_CheckField, 26, 6, 4, 121, 2, 0, // Skip to: 2257 /* 1624 */ MCD_OPC_CheckField, 16, 5, 0, 114, 2, 0, // Skip to: 2257 /* 1631 */ MCD_OPC_Decode, 172, 9, 189, 1, // Opcode: QVFCTID /* 1636 */ MCD_OPC_FilterValue, 26, 37, 0, 0, // Skip to: 1678 /* 1641 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1644 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1661 /* 1649 */ MCD_OPC_CheckField, 16, 5, 0, 89, 2, 0, // Skip to: 2257 /* 1656 */ MCD_OPC_Decode, 157, 9, 189, 1, // Opcode: QVFCFIDS /* 1661 */ MCD_OPC_FilterValue, 4, 79, 2, 0, // Skip to: 2257 /* 1666 */ MCD_OPC_CheckField, 16, 5, 0, 72, 2, 0, // Skip to: 2257 /* 1673 */ MCD_OPC_Decode, 156, 9, 189, 1, // Opcode: QVFCFID /* 1678 */ MCD_OPC_FilterValue, 29, 19, 0, 0, // Skip to: 1702 /* 1683 */ MCD_OPC_CheckField, 26, 6, 4, 55, 2, 0, // Skip to: 2257 /* 1690 */ MCD_OPC_CheckField, 16, 5, 0, 48, 2, 0, // Skip to: 2257 /* 1697 */ MCD_OPC_Decode, 173, 9, 189, 1, // Opcode: QVFCTIDU /* 1702 */ MCD_OPC_FilterValue, 30, 38, 2, 0, // Skip to: 2257 /* 1707 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1710 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1727 /* 1715 */ MCD_OPC_CheckField, 16, 5, 0, 23, 2, 0, // Skip to: 2257 /* 1722 */ MCD_OPC_Decode, 159, 9, 189, 1, // Opcode: QVFCFIDUS /* 1727 */ MCD_OPC_FilterValue, 4, 13, 2, 0, // Skip to: 2257 /* 1732 */ MCD_OPC_CheckField, 16, 5, 0, 6, 2, 0, // Skip to: 2257 /* 1739 */ MCD_OPC_Decode, 158, 9, 189, 1, // Opcode: QVFCFIDU /* 1744 */ MCD_OPC_FilterValue, 30, 99, 0, 0, // Skip to: 1848 /* 1749 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... /* 1752 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1776 /* 1757 */ MCD_OPC_CheckField, 26, 6, 4, 237, 1, 0, // Skip to: 2257 /* 1764 */ MCD_OPC_CheckField, 16, 5, 0, 230, 1, 0, // Skip to: 2257 /* 1771 */ MCD_OPC_Decode, 180, 9, 189, 1, // Opcode: QVFCTIWZ /* 1776 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1800 /* 1781 */ MCD_OPC_CheckField, 26, 6, 4, 213, 1, 0, // Skip to: 2257 /* 1788 */ MCD_OPC_CheckField, 16, 5, 0, 206, 1, 0, // Skip to: 2257 /* 1795 */ MCD_OPC_Decode, 179, 9, 189, 1, // Opcode: QVFCTIWUZ /* 1800 */ MCD_OPC_FilterValue, 25, 19, 0, 0, // Skip to: 1824 /* 1805 */ MCD_OPC_CheckField, 26, 6, 4, 189, 1, 0, // Skip to: 2257 /* 1812 */ MCD_OPC_CheckField, 16, 5, 0, 182, 1, 0, // Skip to: 2257 /* 1819 */ MCD_OPC_Decode, 175, 9, 189, 1, // Opcode: QVFCTIDZ /* 1824 */ MCD_OPC_FilterValue, 29, 172, 1, 0, // Skip to: 2257 /* 1829 */ MCD_OPC_CheckField, 26, 6, 4, 165, 1, 0, // Skip to: 2257 /* 1836 */ MCD_OPC_CheckField, 16, 5, 0, 158, 1, 0, // Skip to: 2257 /* 1843 */ MCD_OPC_Decode, 174, 9, 189, 1, // Opcode: QVFCTIDUZ /* 1848 */ MCD_OPC_FilterValue, 34, 37, 0, 0, // Skip to: 1890 /* 1853 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1856 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1873 /* 1861 */ MCD_OPC_CheckField, 11, 5, 0, 133, 1, 0, // Skip to: 2257 /* 1868 */ MCD_OPC_Decode, 237, 9, 191, 1, // Opcode: QVFXMULS /* 1873 */ MCD_OPC_FilterValue, 4, 123, 1, 0, // Skip to: 2257 /* 1878 */ MCD_OPC_CheckField, 11, 5, 0, 116, 1, 0, // Skip to: 2257 /* 1885 */ MCD_OPC_Decode, 236, 9, 191, 1, // Opcode: QVFXMUL /* 1890 */ MCD_OPC_FilterValue, 40, 37, 0, 0, // Skip to: 1932 /* 1895 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1898 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1915 /* 1903 */ MCD_OPC_CheckField, 6, 5, 0, 91, 1, 0, // Skip to: 2257 /* 1910 */ MCD_OPC_Decode, 230, 9, 192, 1, // Opcode: QVFSUBSs /* 1915 */ MCD_OPC_FilterValue, 4, 81, 1, 0, // Skip to: 2257 /* 1920 */ MCD_OPC_CheckField, 6, 5, 0, 74, 1, 0, // Skip to: 2257 /* 1927 */ MCD_OPC_Decode, 228, 9, 188, 1, // Opcode: QVFSUB /* 1932 */ MCD_OPC_FilterValue, 42, 37, 0, 0, // Skip to: 1974 /* 1937 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1940 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1957 /* 1945 */ MCD_OPC_CheckField, 6, 5, 0, 49, 1, 0, // Skip to: 2257 /* 1952 */ MCD_OPC_Decode, 155, 9, 192, 1, // Opcode: QVFADDSs /* 1957 */ MCD_OPC_FilterValue, 4, 39, 1, 0, // Skip to: 2257 /* 1962 */ MCD_OPC_CheckField, 6, 5, 0, 32, 1, 0, // Skip to: 2257 /* 1969 */ MCD_OPC_Decode, 153, 9, 188, 1, // Opcode: QVFADD /* 1974 */ MCD_OPC_FilterValue, 46, 12, 0, 0, // Skip to: 1991 /* 1979 */ MCD_OPC_CheckField, 26, 6, 4, 15, 1, 0, // Skip to: 2257 /* 1986 */ MCD_OPC_Decode, 225, 9, 193, 1, // Opcode: QVFSELb /* 1991 */ MCD_OPC_FilterValue, 48, 51, 0, 0, // Skip to: 2047 /* 1996 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 1999 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2023 /* 2004 */ MCD_OPC_CheckField, 16, 5, 0, 246, 0, 0, // Skip to: 2257 /* 2011 */ MCD_OPC_CheckField, 6, 5, 0, 239, 0, 0, // Skip to: 2257 /* 2018 */ MCD_OPC_Decode, 209, 9, 189, 1, // Opcode: QVFRES /* 2023 */ MCD_OPC_FilterValue, 4, 229, 0, 0, // Skip to: 2257 /* 2028 */ MCD_OPC_CheckField, 16, 5, 0, 222, 0, 0, // Skip to: 2257 /* 2035 */ MCD_OPC_CheckField, 6, 5, 0, 215, 0, 0, // Skip to: 2257 /* 2042 */ MCD_OPC_Decode, 208, 9, 189, 1, // Opcode: QVFRE /* 2047 */ MCD_OPC_FilterValue, 50, 37, 0, 0, // Skip to: 2089 /* 2052 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 2055 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2072 /* 2060 */ MCD_OPC_CheckField, 11, 5, 0, 190, 0, 0, // Skip to: 2257 /* 2067 */ MCD_OPC_Decode, 195, 9, 194, 1, // Opcode: QVFMULSs /* 2072 */ MCD_OPC_FilterValue, 4, 180, 0, 0, // Skip to: 2257 /* 2077 */ MCD_OPC_CheckField, 11, 5, 0, 173, 0, 0, // Skip to: 2257 /* 2084 */ MCD_OPC_Decode, 193, 9, 191, 1, // Opcode: QVFMUL /* 2089 */ MCD_OPC_FilterValue, 52, 51, 0, 0, // Skip to: 2145 /* 2094 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 2097 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2121 /* 2102 */ MCD_OPC_CheckField, 16, 5, 0, 148, 0, 0, // Skip to: 2257 /* 2109 */ MCD_OPC_CheckField, 6, 5, 0, 141, 0, 0, // Skip to: 2257 /* 2116 */ MCD_OPC_Decode, 222, 9, 189, 1, // Opcode: QVFRSQRTES /* 2121 */ MCD_OPC_FilterValue, 4, 131, 0, 0, // Skip to: 2257 /* 2126 */ MCD_OPC_CheckField, 16, 5, 0, 124, 0, 0, // Skip to: 2257 /* 2133 */ MCD_OPC_CheckField, 6, 5, 0, 117, 0, 0, // Skip to: 2257 /* 2140 */ MCD_OPC_Decode, 221, 9, 189, 1, // Opcode: QVFRSQRTE /* 2145 */ MCD_OPC_FilterValue, 56, 23, 0, 0, // Skip to: 2173 /* 2150 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 2153 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2163 /* 2158 */ MCD_OPC_Decode, 192, 9, 195, 1, // Opcode: QVFMSUBSs /* 2163 */ MCD_OPC_FilterValue, 4, 89, 0, 0, // Skip to: 2257 /* 2168 */ MCD_OPC_Decode, 190, 9, 178, 1, // Opcode: QVFMSUB /* 2173 */ MCD_OPC_FilterValue, 58, 23, 0, 0, // Skip to: 2201 /* 2178 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 2181 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2191 /* 2186 */ MCD_OPC_Decode, 186, 9, 195, 1, // Opcode: QVFMADDSs /* 2191 */ MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 2257 /* 2196 */ MCD_OPC_Decode, 184, 9, 178, 1, // Opcode: QVFMADD /* 2201 */ MCD_OPC_FilterValue, 60, 23, 0, 0, // Skip to: 2229 /* 2206 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 2209 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2219 /* 2214 */ MCD_OPC_Decode, 205, 9, 195, 1, // Opcode: QVFNMSUBSs /* 2219 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 2257 /* 2224 */ MCD_OPC_Decode, 203, 9, 178, 1, // Opcode: QVFNMSUB /* 2229 */ MCD_OPC_FilterValue, 62, 23, 0, 0, // Skip to: 2257 /* 2234 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 2237 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 2247 /* 2242 */ MCD_OPC_Decode, 202, 9, 195, 1, // Opcode: QVFNMADDSs /* 2247 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 2257 /* 2252 */ MCD_OPC_Decode, 200, 9, 178, 1, // Opcode: QVFNMADD /* 2257 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableSPE32[] = { /* 0 */ MCD_OPC_ExtractField, 3, 8, // Inst{10-3} ... /* 3 */ MCD_OPC_FilterValue, 64, 71, 0, 0, // Skip to: 79 /* 8 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 11 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 28 /* 16 */ MCD_OPC_CheckField, 26, 6, 4, 131, 20, 0, // Skip to: 5274 /* 23 */ MCD_OPC_Decode, 195, 4, 196, 1, // Opcode: EVADDW /* 28 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 45 /* 33 */ MCD_OPC_CheckField, 26, 6, 4, 114, 20, 0, // Skip to: 5274 /* 40 */ MCD_OPC_Decode, 190, 4, 197, 1, // Opcode: EVADDIW /* 45 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 62 /* 50 */ MCD_OPC_CheckField, 26, 6, 4, 97, 20, 0, // Skip to: 5274 /* 57 */ MCD_OPC_Decode, 253, 5, 196, 1, // Opcode: EVSUBFW /* 62 */ MCD_OPC_FilterValue, 6, 87, 20, 0, // Skip to: 5274 /* 67 */ MCD_OPC_CheckField, 26, 6, 4, 80, 20, 0, // Skip to: 5274 /* 74 */ MCD_OPC_Decode, 254, 5, 198, 1, // Opcode: EVSUBIFW /* 79 */ MCD_OPC_FilterValue, 65, 187, 0, 0, // Skip to: 271 /* 84 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 87 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 111 /* 92 */ MCD_OPC_CheckField, 26, 6, 4, 55, 20, 0, // Skip to: 5274 /* 99 */ MCD_OPC_CheckField, 11, 5, 0, 48, 20, 0, // Skip to: 5274 /* 106 */ MCD_OPC_Decode, 189, 4, 199, 1, // Opcode: EVABS /* 111 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 135 /* 116 */ MCD_OPC_CheckField, 26, 6, 4, 31, 20, 0, // Skip to: 5274 /* 123 */ MCD_OPC_CheckField, 11, 5, 0, 24, 20, 0, // Skip to: 5274 /* 130 */ MCD_OPC_Decode, 219, 5, 199, 1, // Opcode: EVNEG /* 135 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 159 /* 140 */ MCD_OPC_CheckField, 26, 6, 4, 7, 20, 0, // Skip to: 5274 /* 147 */ MCD_OPC_CheckField, 11, 5, 0, 0, 20, 0, // Skip to: 5274 /* 154 */ MCD_OPC_Decode, 208, 4, 199, 1, // Opcode: EVEXTSB /* 159 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 183 /* 164 */ MCD_OPC_CheckField, 26, 6, 4, 239, 19, 0, // Skip to: 5274 /* 171 */ MCD_OPC_CheckField, 11, 5, 0, 232, 19, 0, // Skip to: 5274 /* 178 */ MCD_OPC_Decode, 209, 4, 199, 1, // Opcode: EVEXTSH /* 183 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 207 /* 188 */ MCD_OPC_CheckField, 26, 6, 4, 215, 19, 0, // Skip to: 5274 /* 195 */ MCD_OPC_CheckField, 11, 5, 0, 208, 19, 0, // Skip to: 5274 /* 202 */ MCD_OPC_Decode, 225, 5, 199, 1, // Opcode: EVRNDW /* 207 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 231 /* 212 */ MCD_OPC_CheckField, 26, 6, 4, 191, 19, 0, // Skip to: 5274 /* 219 */ MCD_OPC_CheckField, 11, 5, 0, 184, 19, 0, // Skip to: 5274 /* 226 */ MCD_OPC_Decode, 204, 4, 199, 1, // Opcode: EVCNTLZW /* 231 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 255 /* 236 */ MCD_OPC_CheckField, 26, 6, 4, 167, 19, 0, // Skip to: 5274 /* 243 */ MCD_OPC_CheckField, 11, 5, 0, 160, 19, 0, // Skip to: 5274 /* 250 */ MCD_OPC_Decode, 203, 4, 199, 1, // Opcode: EVCNTLSW /* 255 */ MCD_OPC_FilterValue, 7, 150, 19, 0, // Skip to: 5274 /* 260 */ MCD_OPC_CheckField, 26, 6, 4, 143, 19, 0, // Skip to: 5274 /* 267 */ MCD_OPC_Decode, 163, 3, 62, // Opcode: BRINC /* 271 */ MCD_OPC_FilterValue, 66, 71, 0, 0, // Skip to: 347 /* 276 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 279 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 296 /* 284 */ MCD_OPC_CheckField, 26, 6, 4, 119, 19, 0, // Skip to: 5274 /* 291 */ MCD_OPC_Decode, 196, 4, 196, 1, // Opcode: EVAND /* 296 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 313 /* 301 */ MCD_OPC_CheckField, 26, 6, 4, 102, 19, 0, // Skip to: 5274 /* 308 */ MCD_OPC_Decode, 197, 4, 196, 1, // Opcode: EVANDC /* 313 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 330 /* 318 */ MCD_OPC_CheckField, 26, 6, 4, 85, 19, 0, // Skip to: 5274 /* 325 */ MCD_OPC_Decode, 255, 5, 196, 1, // Opcode: EVXOR /* 330 */ MCD_OPC_FilterValue, 7, 75, 19, 0, // Skip to: 5274 /* 335 */ MCD_OPC_CheckField, 26, 6, 4, 68, 19, 0, // Skip to: 5274 /* 342 */ MCD_OPC_Decode, 221, 5, 196, 1, // Opcode: EVOR /* 347 */ MCD_OPC_FilterValue, 67, 71, 0, 0, // Skip to: 423 /* 352 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 355 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 372 /* 360 */ MCD_OPC_CheckField, 26, 6, 4, 43, 19, 0, // Skip to: 5274 /* 367 */ MCD_OPC_Decode, 220, 5, 196, 1, // Opcode: EVNOR /* 372 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 389 /* 377 */ MCD_OPC_CheckField, 26, 6, 4, 26, 19, 0, // Skip to: 5274 /* 384 */ MCD_OPC_Decode, 207, 4, 196, 1, // Opcode: EVEQV /* 389 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 406 /* 394 */ MCD_OPC_CheckField, 26, 6, 4, 9, 19, 0, // Skip to: 5274 /* 401 */ MCD_OPC_Decode, 222, 5, 196, 1, // Opcode: EVORC /* 406 */ MCD_OPC_FilterValue, 6, 255, 18, 0, // Skip to: 5274 /* 411 */ MCD_OPC_CheckField, 26, 6, 4, 248, 18, 0, // Skip to: 5274 /* 418 */ MCD_OPC_Decode, 218, 5, 196, 1, // Opcode: EVNAND /* 423 */ MCD_OPC_FilterValue, 68, 105, 0, 0, // Skip to: 533 /* 428 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 431 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 448 /* 436 */ MCD_OPC_CheckField, 26, 6, 4, 223, 18, 0, // Skip to: 5274 /* 443 */ MCD_OPC_Decode, 234, 5, 196, 1, // Opcode: EVSRWU /* 448 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 465 /* 453 */ MCD_OPC_CheckField, 26, 6, 4, 206, 18, 0, // Skip to: 5274 /* 460 */ MCD_OPC_Decode, 233, 5, 196, 1, // Opcode: EVSRWS /* 465 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 482 /* 470 */ MCD_OPC_CheckField, 26, 6, 4, 189, 18, 0, // Skip to: 5274 /* 477 */ MCD_OPC_Decode, 232, 5, 197, 1, // Opcode: EVSRWIU /* 482 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 499 /* 487 */ MCD_OPC_CheckField, 26, 6, 4, 172, 18, 0, // Skip to: 5274 /* 494 */ MCD_OPC_Decode, 231, 5, 197, 1, // Opcode: EVSRWIS /* 499 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 516 /* 504 */ MCD_OPC_CheckField, 26, 6, 4, 155, 18, 0, // Skip to: 5274 /* 511 */ MCD_OPC_Decode, 227, 5, 196, 1, // Opcode: EVSLW /* 516 */ MCD_OPC_FilterValue, 6, 145, 18, 0, // Skip to: 5274 /* 521 */ MCD_OPC_CheckField, 26, 6, 4, 138, 18, 0, // Skip to: 5274 /* 528 */ MCD_OPC_Decode, 228, 5, 197, 1, // Opcode: EVSLWI /* 533 */ MCD_OPC_FilterValue, 69, 153, 0, 0, // Skip to: 691 /* 538 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 541 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 558 /* 546 */ MCD_OPC_CheckField, 26, 6, 4, 113, 18, 0, // Skip to: 5274 /* 553 */ MCD_OPC_Decode, 223, 5, 196, 1, // Opcode: EVRLW /* 558 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 582 /* 563 */ MCD_OPC_CheckField, 26, 6, 4, 96, 18, 0, // Skip to: 5274 /* 570 */ MCD_OPC_CheckField, 11, 5, 0, 89, 18, 0, // Skip to: 5274 /* 577 */ MCD_OPC_Decode, 230, 5, 200, 1, // Opcode: EVSPLATI /* 582 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 599 /* 587 */ MCD_OPC_CheckField, 26, 6, 4, 72, 18, 0, // Skip to: 5274 /* 594 */ MCD_OPC_Decode, 224, 5, 197, 1, // Opcode: EVRLWI /* 599 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 623 /* 604 */ MCD_OPC_CheckField, 26, 6, 4, 55, 18, 0, // Skip to: 5274 /* 611 */ MCD_OPC_CheckField, 11, 5, 0, 48, 18, 0, // Skip to: 5274 /* 618 */ MCD_OPC_Decode, 229, 5, 200, 1, // Opcode: EVSPLATFI /* 623 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 640 /* 628 */ MCD_OPC_CheckField, 26, 6, 4, 31, 18, 0, // Skip to: 5274 /* 635 */ MCD_OPC_Decode, 255, 4, 196, 1, // Opcode: EVMERGEHI /* 640 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 657 /* 645 */ MCD_OPC_CheckField, 26, 6, 4, 14, 18, 0, // Skip to: 5274 /* 652 */ MCD_OPC_Decode, 129, 5, 196, 1, // Opcode: EVMERGELO /* 657 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 674 /* 662 */ MCD_OPC_CheckField, 26, 6, 4, 253, 17, 0, // Skip to: 5274 /* 669 */ MCD_OPC_Decode, 128, 5, 196, 1, // Opcode: EVMERGEHILO /* 674 */ MCD_OPC_FilterValue, 7, 243, 17, 0, // Skip to: 5274 /* 679 */ MCD_OPC_CheckField, 26, 6, 4, 236, 17, 0, // Skip to: 5274 /* 686 */ MCD_OPC_Decode, 130, 5, 196, 1, // Opcode: EVMERGELOHI /* 691 */ MCD_OPC_FilterValue, 70, 123, 0, 0, // Skip to: 819 /* 696 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 699 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 723 /* 704 */ MCD_OPC_CheckField, 26, 6, 4, 211, 17, 0, // Skip to: 5274 /* 711 */ MCD_OPC_CheckField, 21, 2, 0, 204, 17, 0, // Skip to: 5274 /* 718 */ MCD_OPC_Decode, 200, 4, 201, 1, // Opcode: EVCMPGTU /* 723 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 747 /* 728 */ MCD_OPC_CheckField, 26, 6, 4, 187, 17, 0, // Skip to: 5274 /* 735 */ MCD_OPC_CheckField, 21, 2, 0, 180, 17, 0, // Skip to: 5274 /* 742 */ MCD_OPC_Decode, 199, 4, 201, 1, // Opcode: EVCMPGTS /* 747 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 771 /* 752 */ MCD_OPC_CheckField, 26, 6, 4, 163, 17, 0, // Skip to: 5274 /* 759 */ MCD_OPC_CheckField, 21, 2, 0, 156, 17, 0, // Skip to: 5274 /* 766 */ MCD_OPC_Decode, 202, 4, 201, 1, // Opcode: EVCMPLTU /* 771 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 795 /* 776 */ MCD_OPC_CheckField, 26, 6, 4, 139, 17, 0, // Skip to: 5274 /* 783 */ MCD_OPC_CheckField, 21, 2, 0, 132, 17, 0, // Skip to: 5274 /* 790 */ MCD_OPC_Decode, 201, 4, 201, 1, // Opcode: EVCMPLTS /* 795 */ MCD_OPC_FilterValue, 4, 122, 17, 0, // Skip to: 5274 /* 800 */ MCD_OPC_CheckField, 26, 6, 4, 115, 17, 0, // Skip to: 5274 /* 807 */ MCD_OPC_CheckField, 21, 2, 0, 108, 17, 0, // Skip to: 5274 /* 814 */ MCD_OPC_Decode, 198, 4, 201, 1, // Opcode: EVCMPEQ /* 819 */ MCD_OPC_FilterValue, 79, 12, 0, 0, // Skip to: 836 /* 824 */ MCD_OPC_CheckField, 26, 6, 4, 91, 17, 0, // Skip to: 5274 /* 831 */ MCD_OPC_Decode, 226, 5, 202, 1, // Opcode: EVSEL /* 836 */ MCD_OPC_FilterValue, 80, 109, 0, 0, // Skip to: 950 /* 841 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 844 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 861 /* 849 */ MCD_OPC_CheckField, 26, 6, 4, 66, 17, 0, // Skip to: 5274 /* 856 */ MCD_OPC_Decode, 211, 4, 196, 1, // Opcode: EVFSADD /* 861 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 878 /* 866 */ MCD_OPC_CheckField, 26, 6, 4, 49, 17, 0, // Skip to: 5274 /* 873 */ MCD_OPC_Decode, 229, 4, 196, 1, // Opcode: EVFSSUB /* 878 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 902 /* 883 */ MCD_OPC_CheckField, 26, 6, 4, 32, 17, 0, // Skip to: 5274 /* 890 */ MCD_OPC_CheckField, 11, 5, 0, 25, 17, 0, // Skip to: 5274 /* 897 */ MCD_OPC_Decode, 210, 4, 199, 1, // Opcode: EVFSABS /* 902 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 926 /* 907 */ MCD_OPC_CheckField, 26, 6, 4, 8, 17, 0, // Skip to: 5274 /* 914 */ MCD_OPC_CheckField, 11, 5, 0, 1, 17, 0, // Skip to: 5274 /* 921 */ MCD_OPC_Decode, 227, 4, 199, 1, // Opcode: EVFSNABS /* 926 */ MCD_OPC_FilterValue, 6, 247, 16, 0, // Skip to: 5274 /* 931 */ MCD_OPC_CheckField, 26, 6, 4, 240, 16, 0, // Skip to: 5274 /* 938 */ MCD_OPC_CheckField, 11, 5, 0, 233, 16, 0, // Skip to: 5274 /* 945 */ MCD_OPC_Decode, 228, 4, 199, 1, // Opcode: EVFSNEG /* 950 */ MCD_OPC_FilterValue, 81, 133, 0, 0, // Skip to: 1088 /* 955 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 958 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 975 /* 963 */ MCD_OPC_CheckField, 26, 6, 4, 208, 16, 0, // Skip to: 5274 /* 970 */ MCD_OPC_Decode, 226, 4, 196, 1, // Opcode: EVFSMUL /* 975 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 992 /* 980 */ MCD_OPC_CheckField, 26, 6, 4, 191, 16, 0, // Skip to: 5274 /* 987 */ MCD_OPC_Decode, 225, 4, 196, 1, // Opcode: EVFSDIV /* 992 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1016 /* 997 */ MCD_OPC_CheckField, 26, 6, 4, 174, 16, 0, // Skip to: 5274 /* 1004 */ MCD_OPC_CheckField, 16, 5, 0, 167, 16, 0, // Skip to: 5274 /* 1011 */ MCD_OPC_Decode, 215, 4, 203, 1, // Opcode: EVFSCFUI /* 1016 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1040 /* 1021 */ MCD_OPC_CheckField, 26, 6, 4, 150, 16, 0, // Skip to: 5274 /* 1028 */ MCD_OPC_CheckField, 21, 2, 0, 143, 16, 0, // Skip to: 5274 /* 1035 */ MCD_OPC_Decode, 217, 4, 201, 1, // Opcode: EVFSCMPGT /* 1040 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1064 /* 1045 */ MCD_OPC_CheckField, 26, 6, 4, 126, 16, 0, // Skip to: 5274 /* 1052 */ MCD_OPC_CheckField, 21, 2, 0, 119, 16, 0, // Skip to: 5274 /* 1059 */ MCD_OPC_Decode, 218, 4, 201, 1, // Opcode: EVFSCMPLT /* 1064 */ MCD_OPC_FilterValue, 6, 109, 16, 0, // Skip to: 5274 /* 1069 */ MCD_OPC_CheckField, 26, 6, 4, 102, 16, 0, // Skip to: 5274 /* 1076 */ MCD_OPC_CheckField, 21, 2, 0, 95, 16, 0, // Skip to: 5274 /* 1083 */ MCD_OPC_Decode, 216, 4, 201, 1, // Opcode: EVFSCMPEQ /* 1088 */ MCD_OPC_FilterValue, 82, 171, 0, 0, // Skip to: 1264 /* 1093 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1096 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 1120 /* 1101 */ MCD_OPC_CheckField, 26, 6, 4, 70, 16, 0, // Skip to: 5274 /* 1108 */ MCD_OPC_CheckField, 16, 5, 0, 63, 16, 0, // Skip to: 5274 /* 1115 */ MCD_OPC_Decode, 213, 4, 203, 1, // Opcode: EVFSCFSI /* 1120 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1144 /* 1125 */ MCD_OPC_CheckField, 26, 6, 4, 46, 16, 0, // Skip to: 5274 /* 1132 */ MCD_OPC_CheckField, 16, 5, 0, 39, 16, 0, // Skip to: 5274 /* 1139 */ MCD_OPC_Decode, 214, 4, 203, 1, // Opcode: EVFSCFUF /* 1144 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 1168 /* 1149 */ MCD_OPC_CheckField, 26, 6, 4, 22, 16, 0, // Skip to: 5274 /* 1156 */ MCD_OPC_CheckField, 16, 5, 0, 15, 16, 0, // Skip to: 5274 /* 1163 */ MCD_OPC_Decode, 212, 4, 203, 1, // Opcode: EVFSCFSF /* 1168 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1192 /* 1173 */ MCD_OPC_CheckField, 26, 6, 4, 254, 15, 0, // Skip to: 5274 /* 1180 */ MCD_OPC_CheckField, 16, 5, 0, 247, 15, 0, // Skip to: 5274 /* 1187 */ MCD_OPC_Decode, 223, 4, 203, 1, // Opcode: EVFSCTUI /* 1192 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1216 /* 1197 */ MCD_OPC_CheckField, 26, 6, 4, 230, 15, 0, // Skip to: 5274 /* 1204 */ MCD_OPC_CheckField, 16, 5, 0, 223, 15, 0, // Skip to: 5274 /* 1211 */ MCD_OPC_Decode, 220, 4, 203, 1, // Opcode: EVFSCTSI /* 1216 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1240 /* 1221 */ MCD_OPC_CheckField, 26, 6, 4, 206, 15, 0, // Skip to: 5274 /* 1228 */ MCD_OPC_CheckField, 16, 5, 0, 199, 15, 0, // Skip to: 5274 /* 1235 */ MCD_OPC_Decode, 222, 4, 203, 1, // Opcode: EVFSCTUF /* 1240 */ MCD_OPC_FilterValue, 7, 189, 15, 0, // Skip to: 5274 /* 1245 */ MCD_OPC_CheckField, 26, 6, 4, 182, 15, 0, // Skip to: 5274 /* 1252 */ MCD_OPC_CheckField, 16, 5, 0, 175, 15, 0, // Skip to: 5274 /* 1259 */ MCD_OPC_Decode, 219, 4, 203, 1, // Opcode: EVFSCTSF /* 1264 */ MCD_OPC_FilterValue, 83, 123, 0, 0, // Skip to: 1392 /* 1269 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1272 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1296 /* 1277 */ MCD_OPC_CheckField, 26, 6, 4, 150, 15, 0, // Skip to: 5274 /* 1284 */ MCD_OPC_CheckField, 16, 5, 0, 143, 15, 0, // Skip to: 5274 /* 1291 */ MCD_OPC_Decode, 224, 4, 203, 1, // Opcode: EVFSCTUIZ /* 1296 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1320 /* 1301 */ MCD_OPC_CheckField, 26, 6, 4, 126, 15, 0, // Skip to: 5274 /* 1308 */ MCD_OPC_CheckField, 16, 5, 0, 119, 15, 0, // Skip to: 5274 /* 1315 */ MCD_OPC_Decode, 221, 4, 203, 1, // Opcode: EVFSCTSIZ /* 1320 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1344 /* 1325 */ MCD_OPC_CheckField, 26, 6, 4, 102, 15, 0, // Skip to: 5274 /* 1332 */ MCD_OPC_CheckField, 21, 2, 0, 95, 15, 0, // Skip to: 5274 /* 1339 */ MCD_OPC_Decode, 231, 4, 201, 1, // Opcode: EVFSTSTGT /* 1344 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1368 /* 1349 */ MCD_OPC_CheckField, 26, 6, 4, 78, 15, 0, // Skip to: 5274 /* 1356 */ MCD_OPC_CheckField, 21, 2, 0, 71, 15, 0, // Skip to: 5274 /* 1363 */ MCD_OPC_Decode, 232, 4, 201, 1, // Opcode: EVFSTSTLT /* 1368 */ MCD_OPC_FilterValue, 6, 61, 15, 0, // Skip to: 5274 /* 1373 */ MCD_OPC_CheckField, 26, 6, 4, 54, 15, 0, // Skip to: 5274 /* 1380 */ MCD_OPC_CheckField, 21, 2, 0, 47, 15, 0, // Skip to: 5274 /* 1387 */ MCD_OPC_Decode, 230, 4, 201, 1, // Opcode: EVFSTSTEQ /* 1392 */ MCD_OPC_FilterValue, 88, 109, 0, 0, // Skip to: 1506 /* 1397 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1400 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1417 /* 1405 */ MCD_OPC_CheckField, 26, 6, 4, 22, 15, 0, // Skip to: 5274 /* 1412 */ MCD_OPC_Decode, 157, 4, 204, 1, // Opcode: EFSADD /* 1417 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 1434 /* 1422 */ MCD_OPC_CheckField, 26, 6, 4, 5, 15, 0, // Skip to: 5274 /* 1429 */ MCD_OPC_Decode, 176, 4, 204, 1, // Opcode: EFSSUB /* 1434 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1458 /* 1439 */ MCD_OPC_CheckField, 26, 6, 4, 244, 14, 0, // Skip to: 5274 /* 1446 */ MCD_OPC_CheckField, 11, 5, 0, 237, 14, 0, // Skip to: 5274 /* 1453 */ MCD_OPC_Decode, 156, 4, 205, 1, // Opcode: EFSABS /* 1458 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1482 /* 1463 */ MCD_OPC_CheckField, 26, 6, 4, 220, 14, 0, // Skip to: 5274 /* 1470 */ MCD_OPC_CheckField, 11, 5, 0, 213, 14, 0, // Skip to: 5274 /* 1477 */ MCD_OPC_Decode, 174, 4, 205, 1, // Opcode: EFSNABS /* 1482 */ MCD_OPC_FilterValue, 6, 203, 14, 0, // Skip to: 5274 /* 1487 */ MCD_OPC_CheckField, 26, 6, 4, 196, 14, 0, // Skip to: 5274 /* 1494 */ MCD_OPC_CheckField, 11, 5, 0, 189, 14, 0, // Skip to: 5274 /* 1501 */ MCD_OPC_Decode, 175, 4, 205, 1, // Opcode: EFSNEG /* 1506 */ MCD_OPC_FilterValue, 89, 133, 0, 0, // Skip to: 1644 /* 1511 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1514 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1531 /* 1519 */ MCD_OPC_CheckField, 26, 6, 4, 164, 14, 0, // Skip to: 5274 /* 1526 */ MCD_OPC_Decode, 173, 4, 204, 1, // Opcode: EFSMUL /* 1531 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 1548 /* 1536 */ MCD_OPC_CheckField, 26, 6, 4, 147, 14, 0, // Skip to: 5274 /* 1543 */ MCD_OPC_Decode, 172, 4, 204, 1, // Opcode: EFSDIV /* 1548 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1572 /* 1553 */ MCD_OPC_CheckField, 26, 6, 4, 130, 14, 0, // Skip to: 5274 /* 1560 */ MCD_OPC_CheckField, 21, 2, 0, 123, 14, 0, // Skip to: 5274 /* 1567 */ MCD_OPC_Decode, 164, 4, 206, 1, // Opcode: EFSCMPGT /* 1572 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1596 /* 1577 */ MCD_OPC_CheckField, 26, 6, 4, 106, 14, 0, // Skip to: 5274 /* 1584 */ MCD_OPC_CheckField, 21, 2, 0, 99, 14, 0, // Skip to: 5274 /* 1591 */ MCD_OPC_Decode, 165, 4, 206, 1, // Opcode: EFSCMPLT /* 1596 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1620 /* 1601 */ MCD_OPC_CheckField, 26, 6, 4, 82, 14, 0, // Skip to: 5274 /* 1608 */ MCD_OPC_CheckField, 21, 2, 0, 75, 14, 0, // Skip to: 5274 /* 1615 */ MCD_OPC_Decode, 163, 4, 206, 1, // Opcode: EFSCMPEQ /* 1620 */ MCD_OPC_FilterValue, 7, 65, 14, 0, // Skip to: 5274 /* 1625 */ MCD_OPC_CheckField, 26, 6, 4, 58, 14, 0, // Skip to: 5274 /* 1632 */ MCD_OPC_CheckField, 16, 5, 0, 51, 14, 0, // Skip to: 5274 /* 1639 */ MCD_OPC_Decode, 158, 4, 207, 1, // Opcode: EFSCFD /* 1644 */ MCD_OPC_FilterValue, 90, 195, 0, 0, // Skip to: 1844 /* 1649 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1652 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1676 /* 1657 */ MCD_OPC_CheckField, 26, 6, 4, 26, 14, 0, // Skip to: 5274 /* 1664 */ MCD_OPC_CheckField, 16, 5, 0, 19, 14, 0, // Skip to: 5274 /* 1671 */ MCD_OPC_Decode, 162, 4, 208, 1, // Opcode: EFSCFUI /* 1676 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 1700 /* 1681 */ MCD_OPC_CheckField, 26, 6, 4, 2, 14, 0, // Skip to: 5274 /* 1688 */ MCD_OPC_CheckField, 16, 5, 0, 251, 13, 0, // Skip to: 5274 /* 1695 */ MCD_OPC_Decode, 160, 4, 208, 1, // Opcode: EFSCFSI /* 1700 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1724 /* 1705 */ MCD_OPC_CheckField, 26, 6, 4, 234, 13, 0, // Skip to: 5274 /* 1712 */ MCD_OPC_CheckField, 16, 5, 0, 227, 13, 0, // Skip to: 5274 /* 1719 */ MCD_OPC_Decode, 161, 4, 209, 1, // Opcode: EFSCFUF /* 1724 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 1748 /* 1729 */ MCD_OPC_CheckField, 26, 6, 4, 210, 13, 0, // Skip to: 5274 /* 1736 */ MCD_OPC_CheckField, 16, 5, 0, 203, 13, 0, // Skip to: 5274 /* 1743 */ MCD_OPC_Decode, 159, 4, 209, 1, // Opcode: EFSCFSF /* 1748 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1772 /* 1753 */ MCD_OPC_CheckField, 26, 6, 4, 186, 13, 0, // Skip to: 5274 /* 1760 */ MCD_OPC_CheckField, 16, 5, 0, 179, 13, 0, // Skip to: 5274 /* 1767 */ MCD_OPC_Decode, 170, 4, 210, 1, // Opcode: EFSCTUI /* 1772 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1796 /* 1777 */ MCD_OPC_CheckField, 26, 6, 4, 162, 13, 0, // Skip to: 5274 /* 1784 */ MCD_OPC_CheckField, 16, 5, 0, 155, 13, 0, // Skip to: 5274 /* 1791 */ MCD_OPC_Decode, 167, 4, 210, 1, // Opcode: EFSCTSI /* 1796 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 1820 /* 1801 */ MCD_OPC_CheckField, 26, 6, 4, 138, 13, 0, // Skip to: 5274 /* 1808 */ MCD_OPC_CheckField, 16, 5, 0, 131, 13, 0, // Skip to: 5274 /* 1815 */ MCD_OPC_Decode, 169, 4, 211, 1, // Opcode: EFSCTUF /* 1820 */ MCD_OPC_FilterValue, 7, 121, 13, 0, // Skip to: 5274 /* 1825 */ MCD_OPC_CheckField, 26, 6, 4, 114, 13, 0, // Skip to: 5274 /* 1832 */ MCD_OPC_CheckField, 16, 5, 0, 107, 13, 0, // Skip to: 5274 /* 1839 */ MCD_OPC_Decode, 166, 4, 209, 1, // Opcode: EFSCTSF /* 1844 */ MCD_OPC_FilterValue, 91, 123, 0, 0, // Skip to: 1972 /* 1849 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1852 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 1876 /* 1857 */ MCD_OPC_CheckField, 26, 6, 4, 82, 13, 0, // Skip to: 5274 /* 1864 */ MCD_OPC_CheckField, 16, 5, 0, 75, 13, 0, // Skip to: 5274 /* 1871 */ MCD_OPC_Decode, 171, 4, 210, 1, // Opcode: EFSCTUIZ /* 1876 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 1900 /* 1881 */ MCD_OPC_CheckField, 26, 6, 4, 58, 13, 0, // Skip to: 5274 /* 1888 */ MCD_OPC_CheckField, 16, 5, 0, 51, 13, 0, // Skip to: 5274 /* 1895 */ MCD_OPC_Decode, 168, 4, 210, 1, // Opcode: EFSCTSIZ /* 1900 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 1924 /* 1905 */ MCD_OPC_CheckField, 26, 6, 4, 34, 13, 0, // Skip to: 5274 /* 1912 */ MCD_OPC_CheckField, 21, 2, 0, 27, 13, 0, // Skip to: 5274 /* 1919 */ MCD_OPC_Decode, 178, 4, 201, 1, // Opcode: EFSTSTGT /* 1924 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 1948 /* 1929 */ MCD_OPC_CheckField, 26, 6, 4, 10, 13, 0, // Skip to: 5274 /* 1936 */ MCD_OPC_CheckField, 21, 2, 0, 3, 13, 0, // Skip to: 5274 /* 1943 */ MCD_OPC_Decode, 179, 4, 201, 1, // Opcode: EFSTSTLT /* 1948 */ MCD_OPC_FilterValue, 6, 249, 12, 0, // Skip to: 5274 /* 1953 */ MCD_OPC_CheckField, 26, 6, 4, 242, 12, 0, // Skip to: 5274 /* 1960 */ MCD_OPC_CheckField, 21, 2, 0, 235, 12, 0, // Skip to: 5274 /* 1967 */ MCD_OPC_Decode, 177, 4, 201, 1, // Opcode: EFSTSTEQ /* 1972 */ MCD_OPC_FilterValue, 92, 157, 0, 0, // Skip to: 2134 /* 1977 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 1980 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 1997 /* 1985 */ MCD_OPC_CheckField, 26, 6, 4, 210, 12, 0, // Skip to: 5274 /* 1992 */ MCD_OPC_Decode, 129, 4, 196, 1, // Opcode: EFDADD /* 1997 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2014 /* 2002 */ MCD_OPC_CheckField, 26, 6, 4, 193, 12, 0, // Skip to: 5274 /* 2009 */ MCD_OPC_Decode, 152, 4, 196, 1, // Opcode: EFDSUB /* 2014 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2038 /* 2019 */ MCD_OPC_CheckField, 26, 6, 4, 176, 12, 0, // Skip to: 5274 /* 2026 */ MCD_OPC_CheckField, 16, 5, 0, 169, 12, 0, // Skip to: 5274 /* 2033 */ MCD_OPC_Decode, 136, 4, 212, 1, // Opcode: EFDCFUID /* 2038 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2062 /* 2043 */ MCD_OPC_CheckField, 26, 6, 4, 152, 12, 0, // Skip to: 5274 /* 2050 */ MCD_OPC_CheckField, 16, 5, 0, 145, 12, 0, // Skip to: 5274 /* 2057 */ MCD_OPC_Decode, 133, 4, 212, 1, // Opcode: EFDCFSID /* 2062 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2086 /* 2067 */ MCD_OPC_CheckField, 26, 6, 4, 128, 12, 0, // Skip to: 5274 /* 2074 */ MCD_OPC_CheckField, 11, 5, 0, 121, 12, 0, // Skip to: 5274 /* 2081 */ MCD_OPC_Decode, 128, 4, 199, 1, // Opcode: EFDABS /* 2086 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2110 /* 2091 */ MCD_OPC_CheckField, 26, 6, 4, 104, 12, 0, // Skip to: 5274 /* 2098 */ MCD_OPC_CheckField, 11, 5, 0, 97, 12, 0, // Skip to: 5274 /* 2105 */ MCD_OPC_Decode, 150, 4, 199, 1, // Opcode: EFDNABS /* 2110 */ MCD_OPC_FilterValue, 6, 87, 12, 0, // Skip to: 5274 /* 2115 */ MCD_OPC_CheckField, 26, 6, 4, 80, 12, 0, // Skip to: 5274 /* 2122 */ MCD_OPC_CheckField, 11, 5, 0, 73, 12, 0, // Skip to: 5274 /* 2129 */ MCD_OPC_Decode, 151, 4, 199, 1, // Opcode: EFDNEG /* 2134 */ MCD_OPC_FilterValue, 93, 181, 0, 0, // Skip to: 2320 /* 2139 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2142 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2159 /* 2147 */ MCD_OPC_CheckField, 26, 6, 4, 48, 12, 0, // Skip to: 5274 /* 2154 */ MCD_OPC_Decode, 149, 4, 196, 1, // Opcode: EFDMUL /* 2159 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2176 /* 2164 */ MCD_OPC_CheckField, 26, 6, 4, 31, 12, 0, // Skip to: 5274 /* 2171 */ MCD_OPC_Decode, 148, 4, 196, 1, // Opcode: EFDDIV /* 2176 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2200 /* 2181 */ MCD_OPC_CheckField, 26, 6, 4, 14, 12, 0, // Skip to: 5274 /* 2188 */ MCD_OPC_CheckField, 16, 5, 0, 7, 12, 0, // Skip to: 5274 /* 2195 */ MCD_OPC_Decode, 146, 4, 213, 1, // Opcode: EFDCTUIDZ /* 2200 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2224 /* 2205 */ MCD_OPC_CheckField, 26, 6, 4, 246, 11, 0, // Skip to: 5274 /* 2212 */ MCD_OPC_CheckField, 16, 5, 0, 239, 11, 0, // Skip to: 5274 /* 2219 */ MCD_OPC_Decode, 142, 4, 213, 1, // Opcode: EFDCTSIDZ /* 2224 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2248 /* 2229 */ MCD_OPC_CheckField, 26, 6, 4, 222, 11, 0, // Skip to: 5274 /* 2236 */ MCD_OPC_CheckField, 21, 2, 0, 215, 11, 0, // Skip to: 5274 /* 2243 */ MCD_OPC_Decode, 138, 4, 201, 1, // Opcode: EFDCMPGT /* 2248 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2272 /* 2253 */ MCD_OPC_CheckField, 26, 6, 4, 198, 11, 0, // Skip to: 5274 /* 2260 */ MCD_OPC_CheckField, 21, 2, 0, 191, 11, 0, // Skip to: 5274 /* 2267 */ MCD_OPC_Decode, 139, 4, 201, 1, // Opcode: EFDCMPLT /* 2272 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2296 /* 2277 */ MCD_OPC_CheckField, 26, 6, 4, 174, 11, 0, // Skip to: 5274 /* 2284 */ MCD_OPC_CheckField, 21, 2, 0, 167, 11, 0, // Skip to: 5274 /* 2291 */ MCD_OPC_Decode, 137, 4, 201, 1, // Opcode: EFDCMPEQ /* 2296 */ MCD_OPC_FilterValue, 7, 157, 11, 0, // Skip to: 5274 /* 2301 */ MCD_OPC_CheckField, 26, 6, 4, 150, 11, 0, // Skip to: 5274 /* 2308 */ MCD_OPC_CheckField, 16, 5, 0, 143, 11, 0, // Skip to: 5274 /* 2315 */ MCD_OPC_Decode, 130, 4, 211, 1, // Opcode: EFDCFS /* 2320 */ MCD_OPC_FilterValue, 94, 195, 0, 0, // Skip to: 2520 /* 2325 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2328 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2352 /* 2333 */ MCD_OPC_CheckField, 26, 6, 4, 118, 11, 0, // Skip to: 5274 /* 2340 */ MCD_OPC_CheckField, 16, 5, 0, 111, 11, 0, // Skip to: 5274 /* 2347 */ MCD_OPC_Decode, 135, 4, 212, 1, // Opcode: EFDCFUI /* 2352 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 2376 /* 2357 */ MCD_OPC_CheckField, 26, 6, 4, 94, 11, 0, // Skip to: 5274 /* 2364 */ MCD_OPC_CheckField, 16, 5, 0, 87, 11, 0, // Skip to: 5274 /* 2371 */ MCD_OPC_Decode, 132, 4, 212, 1, // Opcode: EFDCFSI /* 2376 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2400 /* 2381 */ MCD_OPC_CheckField, 26, 6, 4, 70, 11, 0, // Skip to: 5274 /* 2388 */ MCD_OPC_CheckField, 16, 5, 0, 63, 11, 0, // Skip to: 5274 /* 2395 */ MCD_OPC_Decode, 134, 4, 211, 1, // Opcode: EFDCFUF /* 2400 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2424 /* 2405 */ MCD_OPC_CheckField, 26, 6, 4, 46, 11, 0, // Skip to: 5274 /* 2412 */ MCD_OPC_CheckField, 16, 5, 0, 39, 11, 0, // Skip to: 5274 /* 2419 */ MCD_OPC_Decode, 131, 4, 211, 1, // Opcode: EFDCFSF /* 2424 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2448 /* 2429 */ MCD_OPC_CheckField, 26, 6, 4, 22, 11, 0, // Skip to: 5274 /* 2436 */ MCD_OPC_CheckField, 16, 5, 0, 15, 11, 0, // Skip to: 5274 /* 2443 */ MCD_OPC_Decode, 145, 4, 213, 1, // Opcode: EFDCTUI /* 2448 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2472 /* 2453 */ MCD_OPC_CheckField, 26, 6, 4, 254, 10, 0, // Skip to: 5274 /* 2460 */ MCD_OPC_CheckField, 16, 5, 0, 247, 10, 0, // Skip to: 5274 /* 2467 */ MCD_OPC_Decode, 141, 4, 213, 1, // Opcode: EFDCTSI /* 2472 */ MCD_OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2496 /* 2477 */ MCD_OPC_CheckField, 26, 6, 4, 230, 10, 0, // Skip to: 5274 /* 2484 */ MCD_OPC_CheckField, 16, 5, 0, 223, 10, 0, // Skip to: 5274 /* 2491 */ MCD_OPC_Decode, 144, 4, 211, 1, // Opcode: EFDCTUF /* 2496 */ MCD_OPC_FilterValue, 7, 213, 10, 0, // Skip to: 5274 /* 2501 */ MCD_OPC_CheckField, 26, 6, 4, 206, 10, 0, // Skip to: 5274 /* 2508 */ MCD_OPC_CheckField, 16, 5, 0, 199, 10, 0, // Skip to: 5274 /* 2515 */ MCD_OPC_Decode, 140, 4, 211, 1, // Opcode: EFDCTSF /* 2520 */ MCD_OPC_FilterValue, 95, 123, 0, 0, // Skip to: 2648 /* 2525 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2528 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 2552 /* 2533 */ MCD_OPC_CheckField, 26, 6, 4, 174, 10, 0, // Skip to: 5274 /* 2540 */ MCD_OPC_CheckField, 16, 5, 0, 167, 10, 0, // Skip to: 5274 /* 2547 */ MCD_OPC_Decode, 147, 4, 213, 1, // Opcode: EFDCTUIZ /* 2552 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2576 /* 2557 */ MCD_OPC_CheckField, 26, 6, 4, 150, 10, 0, // Skip to: 5274 /* 2564 */ MCD_OPC_CheckField, 16, 5, 0, 143, 10, 0, // Skip to: 5274 /* 2571 */ MCD_OPC_Decode, 143, 4, 213, 1, // Opcode: EFDCTSIZ /* 2576 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2600 /* 2581 */ MCD_OPC_CheckField, 26, 6, 4, 126, 10, 0, // Skip to: 5274 /* 2588 */ MCD_OPC_CheckField, 21, 2, 0, 119, 10, 0, // Skip to: 5274 /* 2595 */ MCD_OPC_Decode, 154, 4, 201, 1, // Opcode: EFDTSTGT /* 2600 */ MCD_OPC_FilterValue, 5, 19, 0, 0, // Skip to: 2624 /* 2605 */ MCD_OPC_CheckField, 26, 6, 4, 102, 10, 0, // Skip to: 5274 /* 2612 */ MCD_OPC_CheckField, 21, 2, 0, 95, 10, 0, // Skip to: 5274 /* 2619 */ MCD_OPC_Decode, 155, 4, 201, 1, // Opcode: EFDTSTLT /* 2624 */ MCD_OPC_FilterValue, 6, 85, 10, 0, // Skip to: 5274 /* 2629 */ MCD_OPC_CheckField, 26, 6, 4, 78, 10, 0, // Skip to: 5274 /* 2636 */ MCD_OPC_CheckField, 21, 2, 0, 71, 10, 0, // Skip to: 5274 /* 2643 */ MCD_OPC_Decode, 153, 4, 201, 1, // Opcode: EFDTSTEQ /* 2648 */ MCD_OPC_FilterValue, 96, 105, 0, 0, // Skip to: 2758 /* 2653 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2656 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2673 /* 2661 */ MCD_OPC_CheckField, 26, 6, 4, 46, 10, 0, // Skip to: 5274 /* 2668 */ MCD_OPC_Decode, 234, 4, 214, 1, // Opcode: EVLDDX /* 2673 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2690 /* 2678 */ MCD_OPC_CheckField, 26, 6, 4, 29, 10, 0, // Skip to: 5274 /* 2685 */ MCD_OPC_Decode, 233, 4, 215, 1, // Opcode: EVLDD /* 2690 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 2707 /* 2695 */ MCD_OPC_CheckField, 26, 6, 4, 12, 10, 0, // Skip to: 5274 /* 2702 */ MCD_OPC_Decode, 238, 4, 214, 1, // Opcode: EVLDWX /* 2707 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 2724 /* 2712 */ MCD_OPC_CheckField, 26, 6, 4, 251, 9, 0, // Skip to: 5274 /* 2719 */ MCD_OPC_Decode, 237, 4, 215, 1, // Opcode: EVLDW /* 2724 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2741 /* 2729 */ MCD_OPC_CheckField, 26, 6, 4, 234, 9, 0, // Skip to: 5274 /* 2736 */ MCD_OPC_Decode, 236, 4, 214, 1, // Opcode: EVLDHX /* 2741 */ MCD_OPC_FilterValue, 5, 224, 9, 0, // Skip to: 5274 /* 2746 */ MCD_OPC_CheckField, 26, 6, 4, 217, 9, 0, // Skip to: 5274 /* 2753 */ MCD_OPC_Decode, 235, 4, 215, 1, // Opcode: EVLDH /* 2758 */ MCD_OPC_FilterValue, 97, 105, 0, 0, // Skip to: 2868 /* 2763 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2766 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2783 /* 2771 */ MCD_OPC_CheckField, 26, 6, 4, 192, 9, 0, // Skip to: 5274 /* 2778 */ MCD_OPC_Decode, 240, 4, 214, 1, // Opcode: EVLHHESPLATX /* 2783 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2800 /* 2788 */ MCD_OPC_CheckField, 26, 6, 4, 175, 9, 0, // Skip to: 5274 /* 2795 */ MCD_OPC_Decode, 239, 4, 216, 1, // Opcode: EVLHHESPLAT /* 2800 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2817 /* 2805 */ MCD_OPC_CheckField, 26, 6, 4, 158, 9, 0, // Skip to: 5274 /* 2812 */ MCD_OPC_Decode, 244, 4, 214, 1, // Opcode: EVLHHOUSPLATX /* 2817 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 2834 /* 2822 */ MCD_OPC_CheckField, 26, 6, 4, 141, 9, 0, // Skip to: 5274 /* 2829 */ MCD_OPC_Decode, 243, 4, 216, 1, // Opcode: EVLHHOUSPLAT /* 2834 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 2851 /* 2839 */ MCD_OPC_CheckField, 26, 6, 4, 124, 9, 0, // Skip to: 5274 /* 2846 */ MCD_OPC_Decode, 242, 4, 214, 1, // Opcode: EVLHHOSSPLATX /* 2851 */ MCD_OPC_FilterValue, 7, 114, 9, 0, // Skip to: 5274 /* 2856 */ MCD_OPC_CheckField, 26, 6, 4, 107, 9, 0, // Skip to: 5274 /* 2863 */ MCD_OPC_Decode, 241, 4, 216, 1, // Opcode: EVLHHOSSPLAT /* 2868 */ MCD_OPC_FilterValue, 98, 105, 0, 0, // Skip to: 2978 /* 2873 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2876 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 2893 /* 2881 */ MCD_OPC_CheckField, 26, 6, 4, 82, 9, 0, // Skip to: 5274 /* 2888 */ MCD_OPC_Decode, 246, 4, 214, 1, // Opcode: EVLWHEX /* 2893 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 2910 /* 2898 */ MCD_OPC_CheckField, 26, 6, 4, 65, 9, 0, // Skip to: 5274 /* 2905 */ MCD_OPC_Decode, 245, 4, 217, 1, // Opcode: EVLWHE /* 2910 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 2927 /* 2915 */ MCD_OPC_CheckField, 26, 6, 4, 48, 9, 0, // Skip to: 5274 /* 2922 */ MCD_OPC_Decode, 250, 4, 214, 1, // Opcode: EVLWHOUX /* 2927 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 2944 /* 2932 */ MCD_OPC_CheckField, 26, 6, 4, 31, 9, 0, // Skip to: 5274 /* 2939 */ MCD_OPC_Decode, 249, 4, 217, 1, // Opcode: EVLWHOU /* 2944 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 2961 /* 2949 */ MCD_OPC_CheckField, 26, 6, 4, 14, 9, 0, // Skip to: 5274 /* 2956 */ MCD_OPC_Decode, 248, 4, 214, 1, // Opcode: EVLWHOSX /* 2961 */ MCD_OPC_FilterValue, 7, 4, 9, 0, // Skip to: 5274 /* 2966 */ MCD_OPC_CheckField, 26, 6, 4, 253, 8, 0, // Skip to: 5274 /* 2973 */ MCD_OPC_Decode, 247, 4, 217, 1, // Opcode: EVLWHOS /* 2978 */ MCD_OPC_FilterValue, 99, 71, 0, 0, // Skip to: 3054 /* 2983 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 2986 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3003 /* 2991 */ MCD_OPC_CheckField, 26, 6, 4, 228, 8, 0, // Skip to: 5274 /* 2998 */ MCD_OPC_Decode, 254, 4, 214, 1, // Opcode: EVLWWSPLATX /* 3003 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3020 /* 3008 */ MCD_OPC_CheckField, 26, 6, 4, 211, 8, 0, // Skip to: 5274 /* 3015 */ MCD_OPC_Decode, 253, 4, 217, 1, // Opcode: EVLWWSPLAT /* 3020 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3037 /* 3025 */ MCD_OPC_CheckField, 26, 6, 4, 194, 8, 0, // Skip to: 5274 /* 3032 */ MCD_OPC_Decode, 252, 4, 214, 1, // Opcode: EVLWHSPLATX /* 3037 */ MCD_OPC_FilterValue, 5, 184, 8, 0, // Skip to: 5274 /* 3042 */ MCD_OPC_CheckField, 26, 6, 4, 177, 8, 0, // Skip to: 5274 /* 3049 */ MCD_OPC_Decode, 251, 4, 217, 1, // Opcode: EVLWHSPLAT /* 3054 */ MCD_OPC_FilterValue, 100, 105, 0, 0, // Skip to: 3164 /* 3059 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3062 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3079 /* 3067 */ MCD_OPC_CheckField, 26, 6, 4, 152, 8, 0, // Skip to: 5274 /* 3074 */ MCD_OPC_Decode, 236, 5, 214, 1, // Opcode: EVSTDDX /* 3079 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3096 /* 3084 */ MCD_OPC_CheckField, 26, 6, 4, 135, 8, 0, // Skip to: 5274 /* 3091 */ MCD_OPC_Decode, 235, 5, 215, 1, // Opcode: EVSTDD /* 3096 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 3113 /* 3101 */ MCD_OPC_CheckField, 26, 6, 4, 118, 8, 0, // Skip to: 5274 /* 3108 */ MCD_OPC_Decode, 240, 5, 214, 1, // Opcode: EVSTDWX /* 3113 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3130 /* 3118 */ MCD_OPC_CheckField, 26, 6, 4, 101, 8, 0, // Skip to: 5274 /* 3125 */ MCD_OPC_Decode, 239, 5, 215, 1, // Opcode: EVSTDW /* 3130 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3147 /* 3135 */ MCD_OPC_CheckField, 26, 6, 4, 84, 8, 0, // Skip to: 5274 /* 3142 */ MCD_OPC_Decode, 238, 5, 214, 1, // Opcode: EVSTDHX /* 3147 */ MCD_OPC_FilterValue, 5, 74, 8, 0, // Skip to: 5274 /* 3152 */ MCD_OPC_CheckField, 26, 6, 4, 67, 8, 0, // Skip to: 5274 /* 3159 */ MCD_OPC_Decode, 237, 5, 215, 1, // Opcode: EVSTDH /* 3164 */ MCD_OPC_FilterValue, 102, 71, 0, 0, // Skip to: 3240 /* 3169 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3172 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3189 /* 3177 */ MCD_OPC_CheckField, 26, 6, 4, 42, 8, 0, // Skip to: 5274 /* 3184 */ MCD_OPC_Decode, 242, 5, 214, 1, // Opcode: EVSTWHEX /* 3189 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3206 /* 3194 */ MCD_OPC_CheckField, 26, 6, 4, 25, 8, 0, // Skip to: 5274 /* 3201 */ MCD_OPC_Decode, 241, 5, 217, 1, // Opcode: EVSTWHE /* 3206 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3223 /* 3211 */ MCD_OPC_CheckField, 26, 6, 4, 8, 8, 0, // Skip to: 5274 /* 3218 */ MCD_OPC_Decode, 244, 5, 214, 1, // Opcode: EVSTWHOX /* 3223 */ MCD_OPC_FilterValue, 5, 254, 7, 0, // Skip to: 5274 /* 3228 */ MCD_OPC_CheckField, 26, 6, 4, 247, 7, 0, // Skip to: 5274 /* 3235 */ MCD_OPC_Decode, 243, 5, 217, 1, // Opcode: EVSTWHO /* 3240 */ MCD_OPC_FilterValue, 103, 71, 0, 0, // Skip to: 3316 /* 3245 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3248 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3265 /* 3253 */ MCD_OPC_CheckField, 26, 6, 4, 222, 7, 0, // Skip to: 5274 /* 3260 */ MCD_OPC_Decode, 246, 5, 214, 1, // Opcode: EVSTWWEX /* 3265 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3282 /* 3270 */ MCD_OPC_CheckField, 26, 6, 4, 205, 7, 0, // Skip to: 5274 /* 3277 */ MCD_OPC_Decode, 245, 5, 217, 1, // Opcode: EVSTWWE /* 3282 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3299 /* 3287 */ MCD_OPC_CheckField, 26, 6, 4, 188, 7, 0, // Skip to: 5274 /* 3294 */ MCD_OPC_Decode, 248, 5, 214, 1, // Opcode: EVSTWWOX /* 3299 */ MCD_OPC_FilterValue, 5, 178, 7, 0, // Skip to: 5274 /* 3304 */ MCD_OPC_CheckField, 26, 6, 4, 171, 7, 0, // Skip to: 5274 /* 3311 */ MCD_OPC_Decode, 247, 5, 217, 1, // Opcode: EVSTWWO /* 3316 */ MCD_OPC_FilterValue, 128, 1, 37, 0, 0, // Skip to: 3359 /* 3322 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3325 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3342 /* 3330 */ MCD_OPC_CheckField, 26, 6, 4, 145, 7, 0, // Skip to: 5274 /* 3337 */ MCD_OPC_Decode, 145, 5, 196, 1, // Opcode: EVMHESSF /* 3342 */ MCD_OPC_FilterValue, 7, 135, 7, 0, // Skip to: 5274 /* 3347 */ MCD_OPC_CheckField, 26, 6, 4, 128, 7, 0, // Skip to: 5274 /* 3354 */ MCD_OPC_Decode, 171, 5, 196, 1, // Opcode: EVMHOSSF /* 3359 */ MCD_OPC_FilterValue, 129, 1, 105, 0, 0, // Skip to: 3470 /* 3365 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3368 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3385 /* 3373 */ MCD_OPC_CheckField, 26, 6, 4, 102, 7, 0, // Skip to: 5274 /* 3380 */ MCD_OPC_Decode, 151, 5, 196, 1, // Opcode: EVMHEUMI /* 3385 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3402 /* 3390 */ MCD_OPC_CheckField, 26, 6, 4, 85, 7, 0, // Skip to: 5274 /* 3397 */ MCD_OPC_Decode, 141, 5, 196, 1, // Opcode: EVMHESMI /* 3402 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3419 /* 3407 */ MCD_OPC_CheckField, 26, 6, 4, 68, 7, 0, // Skip to: 5274 /* 3414 */ MCD_OPC_Decode, 137, 5, 196, 1, // Opcode: EVMHESMF /* 3419 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3436 /* 3424 */ MCD_OPC_CheckField, 26, 6, 4, 51, 7, 0, // Skip to: 5274 /* 3431 */ MCD_OPC_Decode, 177, 5, 196, 1, // Opcode: EVMHOUMI /* 3436 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3453 /* 3441 */ MCD_OPC_CheckField, 26, 6, 4, 34, 7, 0, // Skip to: 5274 /* 3448 */ MCD_OPC_Decode, 167, 5, 196, 1, // Opcode: EVMHOSMI /* 3453 */ MCD_OPC_FilterValue, 7, 24, 7, 0, // Skip to: 5274 /* 3458 */ MCD_OPC_CheckField, 26, 6, 4, 17, 7, 0, // Skip to: 5274 /* 3465 */ MCD_OPC_Decode, 163, 5, 196, 1, // Opcode: EVMHOSMF /* 3470 */ MCD_OPC_FilterValue, 132, 1, 37, 0, 0, // Skip to: 3513 /* 3476 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3479 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3496 /* 3484 */ MCD_OPC_CheckField, 26, 6, 4, 247, 6, 0, // Skip to: 5274 /* 3491 */ MCD_OPC_Decode, 146, 5, 196, 1, // Opcode: EVMHESSFA /* 3496 */ MCD_OPC_FilterValue, 7, 237, 6, 0, // Skip to: 5274 /* 3501 */ MCD_OPC_CheckField, 26, 6, 4, 230, 6, 0, // Skip to: 5274 /* 3508 */ MCD_OPC_Decode, 172, 5, 196, 1, // Opcode: EVMHOSSFA /* 3513 */ MCD_OPC_FilterValue, 133, 1, 105, 0, 0, // Skip to: 3624 /* 3519 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3522 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3539 /* 3527 */ MCD_OPC_CheckField, 26, 6, 4, 204, 6, 0, // Skip to: 5274 /* 3534 */ MCD_OPC_Decode, 152, 5, 196, 1, // Opcode: EVMHEUMIA /* 3539 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3556 /* 3544 */ MCD_OPC_CheckField, 26, 6, 4, 187, 6, 0, // Skip to: 5274 /* 3551 */ MCD_OPC_Decode, 142, 5, 196, 1, // Opcode: EVMHESMIA /* 3556 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 3573 /* 3561 */ MCD_OPC_CheckField, 26, 6, 4, 170, 6, 0, // Skip to: 5274 /* 3568 */ MCD_OPC_Decode, 138, 5, 196, 1, // Opcode: EVMHESMFA /* 3573 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3590 /* 3578 */ MCD_OPC_CheckField, 26, 6, 4, 153, 6, 0, // Skip to: 5274 /* 3585 */ MCD_OPC_Decode, 178, 5, 196, 1, // Opcode: EVMHOUMIA /* 3590 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3607 /* 3595 */ MCD_OPC_CheckField, 26, 6, 4, 136, 6, 0, // Skip to: 5274 /* 3602 */ MCD_OPC_Decode, 168, 5, 196, 1, // Opcode: EVMHOSMIA /* 3607 */ MCD_OPC_FilterValue, 7, 126, 6, 0, // Skip to: 5274 /* 3612 */ MCD_OPC_CheckField, 26, 6, 4, 119, 6, 0, // Skip to: 5274 /* 3619 */ MCD_OPC_Decode, 164, 5, 196, 1, // Opcode: EVMHOSMFA /* 3624 */ MCD_OPC_FilterValue, 136, 1, 19, 0, 0, // Skip to: 3649 /* 3630 */ MCD_OPC_CheckField, 26, 6, 4, 101, 6, 0, // Skip to: 5274 /* 3637 */ MCD_OPC_CheckField, 0, 3, 7, 94, 6, 0, // Skip to: 5274 /* 3644 */ MCD_OPC_Decode, 188, 5, 196, 1, // Opcode: EVMWHSSF /* 3649 */ MCD_OPC_FilterValue, 137, 1, 71, 0, 0, // Skip to: 3726 /* 3655 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3658 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3675 /* 3663 */ MCD_OPC_CheckField, 26, 6, 4, 68, 6, 0, // Skip to: 5274 /* 3670 */ MCD_OPC_Decode, 196, 5, 196, 1, // Opcode: EVMWLUMI /* 3675 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3692 /* 3680 */ MCD_OPC_CheckField, 26, 6, 4, 51, 6, 0, // Skip to: 5274 /* 3687 */ MCD_OPC_Decode, 190, 5, 196, 1, // Opcode: EVMWHUMI /* 3692 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3709 /* 3697 */ MCD_OPC_CheckField, 26, 6, 4, 34, 6, 0, // Skip to: 5274 /* 3704 */ MCD_OPC_Decode, 186, 5, 196, 1, // Opcode: EVMWHSMI /* 3709 */ MCD_OPC_FilterValue, 7, 24, 6, 0, // Skip to: 5274 /* 3714 */ MCD_OPC_CheckField, 26, 6, 4, 17, 6, 0, // Skip to: 5274 /* 3721 */ MCD_OPC_Decode, 184, 5, 196, 1, // Opcode: EVMWHSMF /* 3726 */ MCD_OPC_FilterValue, 138, 1, 19, 0, 0, // Skip to: 3751 /* 3732 */ MCD_OPC_CheckField, 26, 6, 4, 255, 5, 0, // Skip to: 5274 /* 3739 */ MCD_OPC_CheckField, 0, 3, 3, 248, 5, 0, // Skip to: 5274 /* 3746 */ MCD_OPC_Decode, 210, 5, 196, 1, // Opcode: EVMWSSF /* 3751 */ MCD_OPC_FilterValue, 139, 1, 54, 0, 0, // Skip to: 3811 /* 3757 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3760 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3777 /* 3765 */ MCD_OPC_CheckField, 26, 6, 4, 222, 5, 0, // Skip to: 5274 /* 3772 */ MCD_OPC_Decode, 214, 5, 196, 1, // Opcode: EVMWUMI /* 3777 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3794 /* 3782 */ MCD_OPC_CheckField, 26, 6, 4, 205, 5, 0, // Skip to: 5274 /* 3789 */ MCD_OPC_Decode, 206, 5, 196, 1, // Opcode: EVMWSMI /* 3794 */ MCD_OPC_FilterValue, 3, 195, 5, 0, // Skip to: 5274 /* 3799 */ MCD_OPC_CheckField, 26, 6, 4, 188, 5, 0, // Skip to: 5274 /* 3806 */ MCD_OPC_Decode, 202, 5, 196, 1, // Opcode: EVMWSMF /* 3811 */ MCD_OPC_FilterValue, 140, 1, 19, 0, 0, // Skip to: 3836 /* 3817 */ MCD_OPC_CheckField, 26, 6, 4, 170, 5, 0, // Skip to: 5274 /* 3824 */ MCD_OPC_CheckField, 0, 3, 7, 163, 5, 0, // Skip to: 5274 /* 3831 */ MCD_OPC_Decode, 189, 5, 196, 1, // Opcode: EVMWHSSFA /* 3836 */ MCD_OPC_FilterValue, 141, 1, 71, 0, 0, // Skip to: 3913 /* 3842 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3845 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3862 /* 3850 */ MCD_OPC_CheckField, 26, 6, 4, 137, 5, 0, // Skip to: 5274 /* 3857 */ MCD_OPC_Decode, 197, 5, 196, 1, // Opcode: EVMWLUMIA /* 3862 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 3879 /* 3867 */ MCD_OPC_CheckField, 26, 6, 4, 120, 5, 0, // Skip to: 5274 /* 3874 */ MCD_OPC_Decode, 191, 5, 196, 1, // Opcode: EVMWHUMIA /* 3879 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 3896 /* 3884 */ MCD_OPC_CheckField, 26, 6, 4, 103, 5, 0, // Skip to: 5274 /* 3891 */ MCD_OPC_Decode, 187, 5, 196, 1, // Opcode: EVMWHSMIA /* 3896 */ MCD_OPC_FilterValue, 7, 93, 5, 0, // Skip to: 5274 /* 3901 */ MCD_OPC_CheckField, 26, 6, 4, 86, 5, 0, // Skip to: 5274 /* 3908 */ MCD_OPC_Decode, 185, 5, 196, 1, // Opcode: EVMWHSMFA /* 3913 */ MCD_OPC_FilterValue, 142, 1, 19, 0, 0, // Skip to: 3938 /* 3919 */ MCD_OPC_CheckField, 26, 6, 4, 68, 5, 0, // Skip to: 5274 /* 3926 */ MCD_OPC_CheckField, 0, 3, 3, 61, 5, 0, // Skip to: 5274 /* 3933 */ MCD_OPC_Decode, 211, 5, 196, 1, // Opcode: EVMWSSFA /* 3938 */ MCD_OPC_FilterValue, 143, 1, 54, 0, 0, // Skip to: 3998 /* 3944 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 3947 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 3964 /* 3952 */ MCD_OPC_CheckField, 26, 6, 4, 35, 5, 0, // Skip to: 5274 /* 3959 */ MCD_OPC_Decode, 215, 5, 196, 1, // Opcode: EVMWUMIA /* 3964 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 3981 /* 3969 */ MCD_OPC_CheckField, 26, 6, 4, 18, 5, 0, // Skip to: 5274 /* 3976 */ MCD_OPC_Decode, 207, 5, 196, 1, // Opcode: EVMWSMIA /* 3981 */ MCD_OPC_FilterValue, 3, 8, 5, 0, // Skip to: 5274 /* 3986 */ MCD_OPC_CheckField, 26, 6, 4, 1, 5, 0, // Skip to: 5274 /* 3993 */ MCD_OPC_Decode, 203, 5, 196, 1, // Opcode: EVMWSMFA /* 3998 */ MCD_OPC_FilterValue, 152, 1, 157, 0, 0, // Skip to: 4161 /* 4004 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4007 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 4031 /* 4012 */ MCD_OPC_CheckField, 26, 6, 4, 231, 4, 0, // Skip to: 5274 /* 4019 */ MCD_OPC_CheckField, 11, 5, 0, 224, 4, 0, // Skip to: 5274 /* 4026 */ MCD_OPC_Decode, 194, 4, 199, 1, // Opcode: EVADDUSIAAW /* 4031 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 4055 /* 4036 */ MCD_OPC_CheckField, 26, 6, 4, 207, 4, 0, // Skip to: 5274 /* 4043 */ MCD_OPC_CheckField, 11, 5, 0, 200, 4, 0, // Skip to: 5274 /* 4050 */ MCD_OPC_Decode, 192, 4, 199, 1, // Opcode: EVADDSSIAAW /* 4055 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 4079 /* 4060 */ MCD_OPC_CheckField, 26, 6, 4, 183, 4, 0, // Skip to: 5274 /* 4067 */ MCD_OPC_CheckField, 11, 5, 0, 176, 4, 0, // Skip to: 5274 /* 4074 */ MCD_OPC_Decode, 252, 5, 199, 1, // Opcode: EVSUBFUSIAAW /* 4079 */ MCD_OPC_FilterValue, 3, 19, 0, 0, // Skip to: 4103 /* 4084 */ MCD_OPC_CheckField, 26, 6, 4, 159, 4, 0, // Skip to: 5274 /* 4091 */ MCD_OPC_CheckField, 11, 5, 0, 152, 4, 0, // Skip to: 5274 /* 4098 */ MCD_OPC_Decode, 250, 5, 199, 1, // Opcode: EVSUBFSSIAAW /* 4103 */ MCD_OPC_FilterValue, 4, 19, 0, 0, // Skip to: 4127 /* 4108 */ MCD_OPC_CheckField, 26, 6, 4, 135, 4, 0, // Skip to: 5274 /* 4115 */ MCD_OPC_CheckField, 11, 5, 0, 128, 4, 0, // Skip to: 5274 /* 4122 */ MCD_OPC_Decode, 183, 5, 199, 1, // Opcode: EVMRA /* 4127 */ MCD_OPC_FilterValue, 6, 12, 0, 0, // Skip to: 4144 /* 4132 */ MCD_OPC_CheckField, 26, 6, 4, 111, 4, 0, // Skip to: 5274 /* 4139 */ MCD_OPC_Decode, 205, 4, 196, 1, // Opcode: EVDIVWS /* 4144 */ MCD_OPC_FilterValue, 7, 101, 4, 0, // Skip to: 5274 /* 4149 */ MCD_OPC_CheckField, 26, 6, 4, 94, 4, 0, // Skip to: 5274 /* 4156 */ MCD_OPC_Decode, 206, 4, 196, 1, // Opcode: EVDIVWU /* 4161 */ MCD_OPC_FilterValue, 153, 1, 99, 0, 0, // Skip to: 4266 /* 4167 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4170 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 4194 /* 4175 */ MCD_OPC_CheckField, 26, 6, 4, 68, 4, 0, // Skip to: 5274 /* 4182 */ MCD_OPC_CheckField, 11, 5, 0, 61, 4, 0, // Skip to: 5274 /* 4189 */ MCD_OPC_Decode, 193, 4, 199, 1, // Opcode: EVADDUMIAAW /* 4194 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 4218 /* 4199 */ MCD_OPC_CheckField, 26, 6, 4, 44, 4, 0, // Skip to: 5274 /* 4206 */ MCD_OPC_CheckField, 11, 5, 0, 37, 4, 0, // Skip to: 5274 /* 4213 */ MCD_OPC_Decode, 191, 4, 199, 1, // Opcode: EVADDSMIAAW /* 4218 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 4242 /* 4223 */ MCD_OPC_CheckField, 26, 6, 4, 20, 4, 0, // Skip to: 5274 /* 4230 */ MCD_OPC_CheckField, 11, 5, 0, 13, 4, 0, // Skip to: 5274 /* 4237 */ MCD_OPC_Decode, 251, 5, 199, 1, // Opcode: EVSUBFUMIAAW /* 4242 */ MCD_OPC_FilterValue, 3, 3, 4, 0, // Skip to: 5274 /* 4247 */ MCD_OPC_CheckField, 26, 6, 4, 252, 3, 0, // Skip to: 5274 /* 4254 */ MCD_OPC_CheckField, 11, 5, 0, 245, 3, 0, // Skip to: 5274 /* 4261 */ MCD_OPC_Decode, 249, 5, 199, 1, // Opcode: EVSUBFSMIAAW /* 4266 */ MCD_OPC_FilterValue, 160, 1, 105, 0, 0, // Skip to: 4377 /* 4272 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4275 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4292 /* 4280 */ MCD_OPC_CheckField, 26, 6, 4, 219, 3, 0, // Skip to: 5274 /* 4287 */ MCD_OPC_Decode, 155, 5, 196, 1, // Opcode: EVMHEUSIAAW /* 4292 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4309 /* 4297 */ MCD_OPC_CheckField, 26, 6, 4, 202, 3, 0, // Skip to: 5274 /* 4304 */ MCD_OPC_Decode, 149, 5, 196, 1, // Opcode: EVMHESSIAAW /* 4309 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4326 /* 4314 */ MCD_OPC_CheckField, 26, 6, 4, 185, 3, 0, // Skip to: 5274 /* 4321 */ MCD_OPC_Decode, 147, 5, 196, 1, // Opcode: EVMHESSFAAW /* 4326 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4343 /* 4331 */ MCD_OPC_CheckField, 26, 6, 4, 168, 3, 0, // Skip to: 5274 /* 4338 */ MCD_OPC_Decode, 181, 5, 196, 1, // Opcode: EVMHOUSIAAW /* 4343 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4360 /* 4348 */ MCD_OPC_CheckField, 26, 6, 4, 151, 3, 0, // Skip to: 5274 /* 4355 */ MCD_OPC_Decode, 175, 5, 196, 1, // Opcode: EVMHOSSIAAW /* 4360 */ MCD_OPC_FilterValue, 7, 141, 3, 0, // Skip to: 5274 /* 4365 */ MCD_OPC_CheckField, 26, 6, 4, 134, 3, 0, // Skip to: 5274 /* 4372 */ MCD_OPC_Decode, 173, 5, 196, 1, // Opcode: EVMHOSSFAAW /* 4377 */ MCD_OPC_FilterValue, 161, 1, 105, 0, 0, // Skip to: 4488 /* 4383 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4386 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4403 /* 4391 */ MCD_OPC_CheckField, 26, 6, 4, 108, 3, 0, // Skip to: 5274 /* 4398 */ MCD_OPC_Decode, 153, 5, 196, 1, // Opcode: EVMHEUMIAAW /* 4403 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4420 /* 4408 */ MCD_OPC_CheckField, 26, 6, 4, 91, 3, 0, // Skip to: 5274 /* 4415 */ MCD_OPC_Decode, 143, 5, 196, 1, // Opcode: EVMHESMIAAW /* 4420 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4437 /* 4425 */ MCD_OPC_CheckField, 26, 6, 4, 74, 3, 0, // Skip to: 5274 /* 4432 */ MCD_OPC_Decode, 139, 5, 196, 1, // Opcode: EVMHESMFAAW /* 4437 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4454 /* 4442 */ MCD_OPC_CheckField, 26, 6, 4, 57, 3, 0, // Skip to: 5274 /* 4449 */ MCD_OPC_Decode, 179, 5, 196, 1, // Opcode: EVMHOUMIAAW /* 4454 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4471 /* 4459 */ MCD_OPC_CheckField, 26, 6, 4, 40, 3, 0, // Skip to: 5274 /* 4466 */ MCD_OPC_Decode, 169, 5, 196, 1, // Opcode: EVMHOSMIAAW /* 4471 */ MCD_OPC_FilterValue, 7, 30, 3, 0, // Skip to: 5274 /* 4476 */ MCD_OPC_CheckField, 26, 6, 4, 23, 3, 0, // Skip to: 5274 /* 4483 */ MCD_OPC_Decode, 165, 5, 196, 1, // Opcode: EVMHOSMFAAW /* 4488 */ MCD_OPC_FilterValue, 165, 1, 105, 0, 0, // Skip to: 4599 /* 4494 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4497 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4514 /* 4502 */ MCD_OPC_CheckField, 26, 6, 4, 253, 2, 0, // Skip to: 5274 /* 4509 */ MCD_OPC_Decode, 135, 5, 196, 1, // Opcode: EVMHEGUMIAA /* 4514 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4531 /* 4519 */ MCD_OPC_CheckField, 26, 6, 4, 236, 2, 0, // Skip to: 5274 /* 4526 */ MCD_OPC_Decode, 133, 5, 196, 1, // Opcode: EVMHEGSMIAA /* 4531 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4548 /* 4536 */ MCD_OPC_CheckField, 26, 6, 4, 219, 2, 0, // Skip to: 5274 /* 4543 */ MCD_OPC_Decode, 131, 5, 196, 1, // Opcode: EVMHEGSMFAA /* 4548 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4565 /* 4553 */ MCD_OPC_CheckField, 26, 6, 4, 202, 2, 0, // Skip to: 5274 /* 4560 */ MCD_OPC_Decode, 161, 5, 196, 1, // Opcode: EVMHOGUMIAA /* 4565 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4582 /* 4570 */ MCD_OPC_CheckField, 26, 6, 4, 185, 2, 0, // Skip to: 5274 /* 4577 */ MCD_OPC_Decode, 159, 5, 196, 1, // Opcode: EVMHOGSMIAA /* 4582 */ MCD_OPC_FilterValue, 7, 175, 2, 0, // Skip to: 5274 /* 4587 */ MCD_OPC_CheckField, 26, 6, 4, 168, 2, 0, // Skip to: 5274 /* 4594 */ MCD_OPC_Decode, 157, 5, 196, 1, // Opcode: EVMHOGSMFAA /* 4599 */ MCD_OPC_FilterValue, 168, 1, 37, 0, 0, // Skip to: 4642 /* 4605 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4608 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4625 /* 4613 */ MCD_OPC_CheckField, 26, 6, 4, 142, 2, 0, // Skip to: 5274 /* 4620 */ MCD_OPC_Decode, 200, 5, 196, 1, // Opcode: EVMWLUSIAAW /* 4625 */ MCD_OPC_FilterValue, 1, 132, 2, 0, // Skip to: 5274 /* 4630 */ MCD_OPC_CheckField, 26, 6, 4, 125, 2, 0, // Skip to: 5274 /* 4637 */ MCD_OPC_Decode, 194, 5, 196, 1, // Opcode: EVMWLSSIAAW /* 4642 */ MCD_OPC_FilterValue, 169, 1, 37, 0, 0, // Skip to: 4685 /* 4648 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4651 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4668 /* 4656 */ MCD_OPC_CheckField, 26, 6, 4, 99, 2, 0, // Skip to: 5274 /* 4663 */ MCD_OPC_Decode, 198, 5, 196, 1, // Opcode: EVMWLUMIAAW /* 4668 */ MCD_OPC_FilterValue, 1, 89, 2, 0, // Skip to: 5274 /* 4673 */ MCD_OPC_CheckField, 26, 6, 4, 82, 2, 0, // Skip to: 5274 /* 4680 */ MCD_OPC_Decode, 192, 5, 196, 1, // Opcode: EVMWLSMIAAW /* 4685 */ MCD_OPC_FilterValue, 170, 1, 19, 0, 0, // Skip to: 4710 /* 4691 */ MCD_OPC_CheckField, 26, 6, 4, 64, 2, 0, // Skip to: 5274 /* 4698 */ MCD_OPC_CheckField, 0, 3, 3, 57, 2, 0, // Skip to: 5274 /* 4705 */ MCD_OPC_Decode, 212, 5, 196, 1, // Opcode: EVMWSSFAA /* 4710 */ MCD_OPC_FilterValue, 171, 1, 54, 0, 0, // Skip to: 4770 /* 4716 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4719 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4736 /* 4724 */ MCD_OPC_CheckField, 26, 6, 4, 31, 2, 0, // Skip to: 5274 /* 4731 */ MCD_OPC_Decode, 216, 5, 196, 1, // Opcode: EVMWUMIAA /* 4736 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4753 /* 4741 */ MCD_OPC_CheckField, 26, 6, 4, 14, 2, 0, // Skip to: 5274 /* 4748 */ MCD_OPC_Decode, 208, 5, 196, 1, // Opcode: EVMWSMIAA /* 4753 */ MCD_OPC_FilterValue, 3, 4, 2, 0, // Skip to: 5274 /* 4758 */ MCD_OPC_CheckField, 26, 6, 4, 253, 1, 0, // Skip to: 5274 /* 4765 */ MCD_OPC_Decode, 204, 5, 196, 1, // Opcode: EVMWSMFAA /* 4770 */ MCD_OPC_FilterValue, 176, 1, 105, 0, 0, // Skip to: 4881 /* 4776 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4779 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4796 /* 4784 */ MCD_OPC_CheckField, 26, 6, 4, 227, 1, 0, // Skip to: 5274 /* 4791 */ MCD_OPC_Decode, 156, 5, 196, 1, // Opcode: EVMHEUSIANW /* 4796 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4813 /* 4801 */ MCD_OPC_CheckField, 26, 6, 4, 210, 1, 0, // Skip to: 5274 /* 4808 */ MCD_OPC_Decode, 150, 5, 196, 1, // Opcode: EVMHESSIANW /* 4813 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4830 /* 4818 */ MCD_OPC_CheckField, 26, 6, 4, 193, 1, 0, // Skip to: 5274 /* 4825 */ MCD_OPC_Decode, 148, 5, 196, 1, // Opcode: EVMHESSFANW /* 4830 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4847 /* 4835 */ MCD_OPC_CheckField, 26, 6, 4, 176, 1, 0, // Skip to: 5274 /* 4842 */ MCD_OPC_Decode, 182, 5, 196, 1, // Opcode: EVMHOUSIANW /* 4847 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4864 /* 4852 */ MCD_OPC_CheckField, 26, 6, 4, 159, 1, 0, // Skip to: 5274 /* 4859 */ MCD_OPC_Decode, 176, 5, 196, 1, // Opcode: EVMHOSSIANW /* 4864 */ MCD_OPC_FilterValue, 7, 149, 1, 0, // Skip to: 5274 /* 4869 */ MCD_OPC_CheckField, 26, 6, 4, 142, 1, 0, // Skip to: 5274 /* 4876 */ MCD_OPC_Decode, 174, 5, 196, 1, // Opcode: EVMHOSSFANW /* 4881 */ MCD_OPC_FilterValue, 177, 1, 105, 0, 0, // Skip to: 4992 /* 4887 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 4890 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 4907 /* 4895 */ MCD_OPC_CheckField, 26, 6, 4, 116, 1, 0, // Skip to: 5274 /* 4902 */ MCD_OPC_Decode, 154, 5, 196, 1, // Opcode: EVMHEUMIANW /* 4907 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 4924 /* 4912 */ MCD_OPC_CheckField, 26, 6, 4, 99, 1, 0, // Skip to: 5274 /* 4919 */ MCD_OPC_Decode, 144, 5, 196, 1, // Opcode: EVMHESMIANW /* 4924 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 4941 /* 4929 */ MCD_OPC_CheckField, 26, 6, 4, 82, 1, 0, // Skip to: 5274 /* 4936 */ MCD_OPC_Decode, 140, 5, 196, 1, // Opcode: EVMHESMFANW /* 4941 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 4958 /* 4946 */ MCD_OPC_CheckField, 26, 6, 4, 65, 1, 0, // Skip to: 5274 /* 4953 */ MCD_OPC_Decode, 180, 5, 196, 1, // Opcode: EVMHOUMIANW /* 4958 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 4975 /* 4963 */ MCD_OPC_CheckField, 26, 6, 4, 48, 1, 0, // Skip to: 5274 /* 4970 */ MCD_OPC_Decode, 170, 5, 196, 1, // Opcode: EVMHOSMIANW /* 4975 */ MCD_OPC_FilterValue, 7, 38, 1, 0, // Skip to: 5274 /* 4980 */ MCD_OPC_CheckField, 26, 6, 4, 31, 1, 0, // Skip to: 5274 /* 4987 */ MCD_OPC_Decode, 166, 5, 196, 1, // Opcode: EVMHOSMFANW /* 4992 */ MCD_OPC_FilterValue, 181, 1, 105, 0, 0, // Skip to: 5103 /* 4998 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 5001 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5018 /* 5006 */ MCD_OPC_CheckField, 26, 6, 4, 5, 1, 0, // Skip to: 5274 /* 5013 */ MCD_OPC_Decode, 136, 5, 196, 1, // Opcode: EVMHEGUMIAN /* 5018 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 5035 /* 5023 */ MCD_OPC_CheckField, 26, 6, 4, 244, 0, 0, // Skip to: 5274 /* 5030 */ MCD_OPC_Decode, 134, 5, 196, 1, // Opcode: EVMHEGSMIAN /* 5035 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 5052 /* 5040 */ MCD_OPC_CheckField, 26, 6, 4, 227, 0, 0, // Skip to: 5274 /* 5047 */ MCD_OPC_Decode, 132, 5, 196, 1, // Opcode: EVMHEGSMFAN /* 5052 */ MCD_OPC_FilterValue, 4, 12, 0, 0, // Skip to: 5069 /* 5057 */ MCD_OPC_CheckField, 26, 6, 4, 210, 0, 0, // Skip to: 5274 /* 5064 */ MCD_OPC_Decode, 162, 5, 196, 1, // Opcode: EVMHOGUMIAN /* 5069 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 5086 /* 5074 */ MCD_OPC_CheckField, 26, 6, 4, 193, 0, 0, // Skip to: 5274 /* 5081 */ MCD_OPC_Decode, 160, 5, 196, 1, // Opcode: EVMHOGSMIAN /* 5086 */ MCD_OPC_FilterValue, 7, 183, 0, 0, // Skip to: 5274 /* 5091 */ MCD_OPC_CheckField, 26, 6, 4, 176, 0, 0, // Skip to: 5274 /* 5098 */ MCD_OPC_Decode, 158, 5, 196, 1, // Opcode: EVMHOGSMFAN /* 5103 */ MCD_OPC_FilterValue, 184, 1, 37, 0, 0, // Skip to: 5146 /* 5109 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 5112 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5129 /* 5117 */ MCD_OPC_CheckField, 26, 6, 4, 150, 0, 0, // Skip to: 5274 /* 5124 */ MCD_OPC_Decode, 201, 5, 196, 1, // Opcode: EVMWLUSIANW /* 5129 */ MCD_OPC_FilterValue, 1, 140, 0, 0, // Skip to: 5274 /* 5134 */ MCD_OPC_CheckField, 26, 6, 4, 133, 0, 0, // Skip to: 5274 /* 5141 */ MCD_OPC_Decode, 195, 5, 196, 1, // Opcode: EVMWLSSIANW /* 5146 */ MCD_OPC_FilterValue, 185, 1, 37, 0, 0, // Skip to: 5189 /* 5152 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 5155 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5172 /* 5160 */ MCD_OPC_CheckField, 26, 6, 4, 107, 0, 0, // Skip to: 5274 /* 5167 */ MCD_OPC_Decode, 199, 5, 196, 1, // Opcode: EVMWLUMIANW /* 5172 */ MCD_OPC_FilterValue, 1, 97, 0, 0, // Skip to: 5274 /* 5177 */ MCD_OPC_CheckField, 26, 6, 4, 90, 0, 0, // Skip to: 5274 /* 5184 */ MCD_OPC_Decode, 193, 5, 196, 1, // Opcode: EVMWLSMIANW /* 5189 */ MCD_OPC_FilterValue, 186, 1, 19, 0, 0, // Skip to: 5214 /* 5195 */ MCD_OPC_CheckField, 26, 6, 4, 72, 0, 0, // Skip to: 5274 /* 5202 */ MCD_OPC_CheckField, 0, 3, 3, 65, 0, 0, // Skip to: 5274 /* 5209 */ MCD_OPC_Decode, 213, 5, 196, 1, // Opcode: EVMWSSFAN /* 5214 */ MCD_OPC_FilterValue, 187, 1, 54, 0, 0, // Skip to: 5274 /* 5220 */ MCD_OPC_ExtractField, 0, 3, // Inst{2-0} ... /* 5223 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 5240 /* 5228 */ MCD_OPC_CheckField, 26, 6, 4, 39, 0, 0, // Skip to: 5274 /* 5235 */ MCD_OPC_Decode, 217, 5, 196, 1, // Opcode: EVMWUMIAN /* 5240 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 5257 /* 5245 */ MCD_OPC_CheckField, 26, 6, 4, 22, 0, 0, // Skip to: 5274 /* 5252 */ MCD_OPC_Decode, 209, 5, 196, 1, // Opcode: EVMWSMIAN /* 5257 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 5274 /* 5262 */ MCD_OPC_CheckField, 26, 6, 4, 5, 0, 0, // Skip to: 5274 /* 5269 */ MCD_OPC_Decode, 205, 5, 196, 1, // Opcode: EVMWSMFAN /* 5274 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) { /* llvm_unreachable("Invalid index!");*/ return true; } #define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, bool *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ default: /* llvm_unreachable("Invalid index!");*/ \ case 0: \ return S; \ case 1: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 2: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 3: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 4: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 5: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 6: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 7: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 8: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 9: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 15, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 10: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 11: \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 12: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 13: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 14: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 15: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 16: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 17: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 18: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 19: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 20: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 21: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 22: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 23: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 24: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 25: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 26: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 27: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 28: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 29: \ tmp = fieldname(insn, 2, 14); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 30: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 2, 14); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 31: \ tmp = fieldname(insn, 5, 7); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 32: \ tmp = fieldname(insn, 2, 24); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 33: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 34: \ tmp = fieldname(insn, 21, 5); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 35: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 0; \ tmp |= fieldname(insn, 6, 10) << 6; \ tmp |= fieldname(insn, 16, 5) << 1; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 36: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 37: \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 38: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 39: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 40: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 1, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 41: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 16); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 16) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 42: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 1) << 5; \ tmp |= fieldname(insn, 6, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 43: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 1) << 5; \ tmp |= fieldname(insn, 6, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 44: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 5, 1) << 5; \ tmp |= fieldname(insn, 6, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 45: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 46: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 47: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 18, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 48: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 49: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 50: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 51: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 52: \ tmp = fieldname(insn, 15, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 53: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 5) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 54: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 55: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 56: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 57: \ tmp = fieldname(insn, 21, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 58: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 59: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 60: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 61: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 62: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 63: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 64: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 65: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 66: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 67: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 68: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 69: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 10); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 70: \ tmp = 0; \ tmp |= fieldname(insn, 11, 5) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 71: \ tmp = fieldname(insn, 21, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 72: \ tmp = fieldname(insn, 25, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 73: \ tmp = fieldname(insn, 21, 5); \ if (DecodeCRRC0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 74: \ tmp = fieldname(insn, 21, 5); \ if (DecodeCRRC0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 75: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 76: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRC_NOR0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeCRBITRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 77: \ tmp = fieldname(insn, 12, 8); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 78: \ tmp = fieldname(insn, 12, 8); \ if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 79: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 8); \ if (decodeCRBitMOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 80: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 81: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 82: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 83: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 84: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 85: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 86: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 87: \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 88: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 89: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 90: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RC_NOX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 91: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 92: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 93: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 94: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 95: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 96: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 97: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 98: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 99: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 100: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 101: \ tmp = fieldname(insn, 21, 2); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 102: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 103: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 104: \ tmp = fieldname(insn, 21, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 105: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 106: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 107: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 108: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 109: \ tmp = fieldname(insn, 21, 2); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 110: \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 111: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 112: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 113: \ tmp = fieldname(insn, 16, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 114: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 115: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 116: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 117: \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 118: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 119: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 21); \ if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 120: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 21); \ if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 121: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 21); \ if (decodeMemRIOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 122: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 2, 19); \ if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 123: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 2, 19); \ if (decodeMemRIXOperands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 124: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 125: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 126: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 127: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 128: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 129: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 130: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 131: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 132: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 133: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 134: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 135: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 136: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 8, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 137: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 138: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 139: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 140: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 8); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 141: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 142: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 143: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 144: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 145: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 146: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 147: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 148: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 149: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 150: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 7); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 151: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 152: \ tmp = fieldname(insn, 21, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 153: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 6; \ tmp |= fieldname(insn, 6, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 154: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeG8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 155: \ tmp = 0; \ tmp |= fieldname(insn, 0, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 16, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 1, 1) << 5; \ tmp |= fieldname(insn, 11, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 5; \ tmp |= fieldname(insn, 6, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 156: \ tmp = 0; \ tmp |= fieldname(insn, 3, 1) << 5; \ tmp |= fieldname(insn, 21, 5) << 0; \ if (DecodeVSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 4, 17); \ if (decodeMemRIX16Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 157: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 158: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 159: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 160: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 161: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 162: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 7); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 163: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 164: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 165: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeVSFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 166: \ tmp = fieldname(insn, 21, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeVRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 167: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 12, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 168: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 169: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 170: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 171: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 172: \ tmp = fieldname(insn, 17, 8); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 25, 1); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 16, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 173: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 174: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 175: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 176: \ tmp = fieldname(insn, 21, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeF8RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 177: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 178: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 179: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 7, 4); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 180: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 181: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 182: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 9, 12); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 183: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 184: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 185: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 186: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 187: \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 188: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 189: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 190: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 191: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 192: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 193: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQBRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeQFRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 194: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 195: \ tmp = fieldname(insn, 21, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 6, 5); \ if (DecodeQSRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 196: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 197: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 198: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 199: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 200: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 201: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 202: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 203: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 204: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 205: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 206: \ tmp = fieldname(insn, 23, 3); \ if (DecodeCRRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 207: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 208: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 209: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 210: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 211: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPE4RCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 212: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 213: \ tmp = fieldname(insn, 21, 5); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 214: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ if (DecodePointerLikeRegClass1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 5); \ if (DecodePointerLikeRegClass0(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 215: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 10); \ if (decodeSPE8Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 216: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 10); \ if (decodeSPE2Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ case 217: \ tmp = fieldname(insn, 21, 5); \ if (DecodeSPERCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 11, 10); \ if (decodeSPE4Operands(MI, tmp, Address, Decoder) == MCDisassembler_Fail) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address) \ { \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail, DecodeComplete = true; \ uint32_t ExpectedValue; \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ /* Decode the field value. */ \ Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ /* Decode the field value. */ \ ExpectedValue = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ /* Decode the Predicate Index value. */ \ PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Check the predicate. */ \ if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ /* Decode the Opcode value. */ \ Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_clear(MI); \ MCInst_setOpcode(MI, Opc); \ S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ /* assert(DecodeComplete); */ \ return S; \ } \ case MCD_OPC_TryDecode: { \ /* Decode the Opcode value. */ \ Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ NumToSkip |= (*Ptr++) << 16; \ /* Perform the decode operation. */ \ MCInst_setOpcode(MI, Opc); \ S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ if (DecodeComplete) { \ /* Decoding complete. */ \ return S; \ } else { \ /* assert(S == MCDisassembler_Fail); */ \ /* If the decoding was incomplete, skip. */ \ Ptr += NumToSkip; \ /* Reset decode status. This also drops a SoftFail status that could be */ \ /* set before the decode attempt. */ \ S = MCDisassembler_Success; \ } \ break; \ } \ case MCD_OPC_SoftFail: { \ /* Decode the mask values. */ \ PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ } FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) capstone-sys-0.15.0/capstone/arch/PowerPC/PPCGenInstrInfo.inc000064400000000000000000004757770072674642500220750ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { PPC_PHI = 0, PPC_INLINEASM = 1, PPC_CFI_INSTRUCTION = 2, PPC_EH_LABEL = 3, PPC_GC_LABEL = 4, PPC_ANNOTATION_LABEL = 5, PPC_KILL = 6, PPC_EXTRACT_SUBREG = 7, PPC_INSERT_SUBREG = 8, PPC_IMPLICIT_DEF = 9, PPC_SUBREG_TO_REG = 10, PPC_COPY_TO_REGCLASS = 11, PPC_DBG_VALUE = 12, PPC_DBG_LABEL = 13, PPC_REG_SEQUENCE = 14, PPC_COPY = 15, PPC_BUNDLE = 16, PPC_LIFETIME_START = 17, PPC_LIFETIME_END = 18, PPC_STACKMAP = 19, PPC_FENTRY_CALL = 20, PPC_PATCHPOINT = 21, PPC_LOAD_STACK_GUARD = 22, PPC_STATEPOINT = 23, PPC_LOCAL_ESCAPE = 24, PPC_FAULTING_OP = 25, PPC_PATCHABLE_OP = 26, PPC_PATCHABLE_FUNCTION_ENTER = 27, PPC_PATCHABLE_RET = 28, PPC_PATCHABLE_FUNCTION_EXIT = 29, PPC_PATCHABLE_TAIL_CALL = 30, PPC_PATCHABLE_EVENT_CALL = 31, PPC_PATCHABLE_TYPED_EVENT_CALL = 32, PPC_ICALL_BRANCH_FUNNEL = 33, PPC_G_ADD = 34, PPC_G_SUB = 35, PPC_G_MUL = 36, PPC_G_SDIV = 37, PPC_G_UDIV = 38, PPC_G_SREM = 39, PPC_G_UREM = 40, PPC_G_AND = 41, PPC_G_OR = 42, PPC_G_XOR = 43, PPC_G_IMPLICIT_DEF = 44, PPC_G_PHI = 45, PPC_G_FRAME_INDEX = 46, PPC_G_GLOBAL_VALUE = 47, PPC_G_EXTRACT = 48, PPC_G_UNMERGE_VALUES = 49, PPC_G_INSERT = 50, PPC_G_MERGE_VALUES = 51, PPC_G_PTRTOINT = 52, PPC_G_INTTOPTR = 53, PPC_G_BITCAST = 54, PPC_G_LOAD = 55, PPC_G_SEXTLOAD = 56, PPC_G_ZEXTLOAD = 57, PPC_G_STORE = 58, PPC_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, PPC_G_ATOMIC_CMPXCHG = 60, PPC_G_ATOMICRMW_XCHG = 61, PPC_G_ATOMICRMW_ADD = 62, PPC_G_ATOMICRMW_SUB = 63, PPC_G_ATOMICRMW_AND = 64, PPC_G_ATOMICRMW_NAND = 65, PPC_G_ATOMICRMW_OR = 66, PPC_G_ATOMICRMW_XOR = 67, PPC_G_ATOMICRMW_MAX = 68, PPC_G_ATOMICRMW_MIN = 69, PPC_G_ATOMICRMW_UMAX = 70, PPC_G_ATOMICRMW_UMIN = 71, PPC_G_BRCOND = 72, PPC_G_BRINDIRECT = 73, PPC_G_INTRINSIC = 74, PPC_G_INTRINSIC_W_SIDE_EFFECTS = 75, PPC_G_ANYEXT = 76, PPC_G_TRUNC = 77, PPC_G_CONSTANT = 78, PPC_G_FCONSTANT = 79, PPC_G_VASTART = 80, PPC_G_VAARG = 81, PPC_G_SEXT = 82, PPC_G_ZEXT = 83, PPC_G_SHL = 84, PPC_G_LSHR = 85, PPC_G_ASHR = 86, PPC_G_ICMP = 87, PPC_G_FCMP = 88, PPC_G_SELECT = 89, PPC_G_UADDE = 90, PPC_G_USUBE = 91, PPC_G_SADDO = 92, PPC_G_SSUBO = 93, PPC_G_UMULO = 94, PPC_G_SMULO = 95, PPC_G_UMULH = 96, PPC_G_SMULH = 97, PPC_G_FADD = 98, PPC_G_FSUB = 99, PPC_G_FMUL = 100, PPC_G_FMA = 101, PPC_G_FDIV = 102, PPC_G_FREM = 103, PPC_G_FPOW = 104, PPC_G_FEXP = 105, PPC_G_FEXP2 = 106, PPC_G_FLOG = 107, PPC_G_FLOG2 = 108, PPC_G_FNEG = 109, PPC_G_FPEXT = 110, PPC_G_FPTRUNC = 111, PPC_G_FPTOSI = 112, PPC_G_FPTOUI = 113, PPC_G_SITOFP = 114, PPC_G_UITOFP = 115, PPC_G_FABS = 116, PPC_G_GEP = 117, PPC_G_PTR_MASK = 118, PPC_G_BR = 119, PPC_G_INSERT_VECTOR_ELT = 120, PPC_G_EXTRACT_VECTOR_ELT = 121, PPC_G_SHUFFLE_VECTOR = 122, PPC_G_BSWAP = 123, PPC_G_ADDRSPACE_CAST = 124, PPC_G_BLOCK_ADDR = 125, PPC_CFENCE8 = 126, PPC_CLRLSLDI = 127, PPC_CLRLSLDIo = 128, PPC_CLRLSLWI = 129, PPC_CLRLSLWIo = 130, PPC_CLRRDI = 131, PPC_CLRRDIo = 132, PPC_CLRRWI = 133, PPC_CLRRWIo = 134, PPC_CP_COPY_FIRST = 135, PPC_CP_COPYx = 136, PPC_CP_PASTE_LAST = 137, PPC_CP_PASTEx = 138, PPC_DCBFL = 139, PPC_DCBFLP = 140, PPC_DCBFx = 141, PPC_DCBTCT = 142, PPC_DCBTDS = 143, PPC_DCBTSTCT = 144, PPC_DCBTSTDS = 145, PPC_DCBTSTT = 146, PPC_DCBTSTx = 147, PPC_DCBTT = 148, PPC_DCBTx = 149, PPC_DFLOADf32 = 150, PPC_DFLOADf64 = 151, PPC_DFSTOREf32 = 152, PPC_DFSTOREf64 = 153, PPC_EXTLDI = 154, PPC_EXTLDIo = 155, PPC_EXTLWI = 156, PPC_EXTLWIo = 157, PPC_EXTRDI = 158, PPC_EXTRDIo = 159, PPC_EXTRWI = 160, PPC_EXTRWIo = 161, PPC_INSLWI = 162, PPC_INSLWIo = 163, PPC_INSRDI = 164, PPC_INSRDIo = 165, PPC_INSRWI = 166, PPC_INSRWIo = 167, PPC_LAx = 168, PPC_LIWAX = 169, PPC_LIWZX = 170, PPC_RLWIMIbm = 171, PPC_RLWIMIobm = 172, PPC_RLWINMbm = 173, PPC_RLWINMobm = 174, PPC_RLWNMbm = 175, PPC_RLWNMobm = 176, PPC_ROTRDI = 177, PPC_ROTRDIo = 178, PPC_ROTRWI = 179, PPC_ROTRWIo = 180, PPC_SLDI = 181, PPC_SLDIo = 182, PPC_SLWI = 183, PPC_SLWIo = 184, PPC_SPILLTOVSR_LD = 185, PPC_SPILLTOVSR_LDX = 186, PPC_SPILLTOVSR_ST = 187, PPC_SPILLTOVSR_STX = 188, PPC_SRDI = 189, PPC_SRDIo = 190, PPC_SRWI = 191, PPC_SRWIo = 192, PPC_STIWX = 193, PPC_SUBI = 194, PPC_SUBIC = 195, PPC_SUBICo = 196, PPC_SUBIS = 197, PPC_SUBPCIS = 198, PPC_XFLOADf32 = 199, PPC_XFLOADf64 = 200, PPC_XFSTOREf32 = 201, PPC_XFSTOREf64 = 202, PPC_ADD4 = 203, PPC_ADD4TLS = 204, PPC_ADD4o = 205, PPC_ADD8 = 206, PPC_ADD8TLS = 207, PPC_ADD8TLS_ = 208, PPC_ADD8o = 209, PPC_ADDC = 210, PPC_ADDC8 = 211, PPC_ADDC8o = 212, PPC_ADDCo = 213, PPC_ADDE = 214, PPC_ADDE8 = 215, PPC_ADDE8o = 216, PPC_ADDEo = 217, PPC_ADDI = 218, PPC_ADDI8 = 219, PPC_ADDIC = 220, PPC_ADDIC8 = 221, PPC_ADDICo = 222, PPC_ADDIS = 223, PPC_ADDIS8 = 224, PPC_ADDISdtprelHA = 225, PPC_ADDISdtprelHA32 = 226, PPC_ADDISgotTprelHA = 227, PPC_ADDIStlsgdHA = 228, PPC_ADDIStlsldHA = 229, PPC_ADDIStocHA = 230, PPC_ADDIdtprelL = 231, PPC_ADDIdtprelL32 = 232, PPC_ADDItlsgdL = 233, PPC_ADDItlsgdL32 = 234, PPC_ADDItlsgdLADDR = 235, PPC_ADDItlsgdLADDR32 = 236, PPC_ADDItlsldL = 237, PPC_ADDItlsldL32 = 238, PPC_ADDItlsldLADDR = 239, PPC_ADDItlsldLADDR32 = 240, PPC_ADDItocL = 241, PPC_ADDME = 242, PPC_ADDME8 = 243, PPC_ADDME8o = 244, PPC_ADDMEo = 245, PPC_ADDPCIS = 246, PPC_ADDZE = 247, PPC_ADDZE8 = 248, PPC_ADDZE8o = 249, PPC_ADDZEo = 250, PPC_ADJCALLSTACKDOWN = 251, PPC_ADJCALLSTACKUP = 252, PPC_AND = 253, PPC_AND8 = 254, PPC_AND8o = 255, PPC_ANDC = 256, PPC_ANDC8 = 257, PPC_ANDC8o = 258, PPC_ANDCo = 259, PPC_ANDISo = 260, PPC_ANDISo8 = 261, PPC_ANDIo = 262, PPC_ANDIo8 = 263, PPC_ANDIo_1_EQ_BIT = 264, PPC_ANDIo_1_EQ_BIT8 = 265, PPC_ANDIo_1_GT_BIT = 266, PPC_ANDIo_1_GT_BIT8 = 267, PPC_ANDo = 268, PPC_ATOMIC_CMP_SWAP_I16 = 269, PPC_ATOMIC_CMP_SWAP_I32 = 270, PPC_ATOMIC_CMP_SWAP_I64 = 271, PPC_ATOMIC_CMP_SWAP_I8 = 272, PPC_ATOMIC_LOAD_ADD_I16 = 273, PPC_ATOMIC_LOAD_ADD_I32 = 274, PPC_ATOMIC_LOAD_ADD_I64 = 275, PPC_ATOMIC_LOAD_ADD_I8 = 276, PPC_ATOMIC_LOAD_AND_I16 = 277, PPC_ATOMIC_LOAD_AND_I32 = 278, PPC_ATOMIC_LOAD_AND_I64 = 279, PPC_ATOMIC_LOAD_AND_I8 = 280, PPC_ATOMIC_LOAD_MAX_I16 = 281, PPC_ATOMIC_LOAD_MAX_I32 = 282, PPC_ATOMIC_LOAD_MAX_I64 = 283, PPC_ATOMIC_LOAD_MAX_I8 = 284, PPC_ATOMIC_LOAD_MIN_I16 = 285, PPC_ATOMIC_LOAD_MIN_I32 = 286, PPC_ATOMIC_LOAD_MIN_I64 = 287, PPC_ATOMIC_LOAD_MIN_I8 = 288, PPC_ATOMIC_LOAD_NAND_I16 = 289, PPC_ATOMIC_LOAD_NAND_I32 = 290, PPC_ATOMIC_LOAD_NAND_I64 = 291, PPC_ATOMIC_LOAD_NAND_I8 = 292, PPC_ATOMIC_LOAD_OR_I16 = 293, PPC_ATOMIC_LOAD_OR_I32 = 294, PPC_ATOMIC_LOAD_OR_I64 = 295, PPC_ATOMIC_LOAD_OR_I8 = 296, PPC_ATOMIC_LOAD_SUB_I16 = 297, PPC_ATOMIC_LOAD_SUB_I32 = 298, PPC_ATOMIC_LOAD_SUB_I64 = 299, PPC_ATOMIC_LOAD_SUB_I8 = 300, PPC_ATOMIC_LOAD_UMAX_I16 = 301, PPC_ATOMIC_LOAD_UMAX_I32 = 302, PPC_ATOMIC_LOAD_UMAX_I64 = 303, PPC_ATOMIC_LOAD_UMAX_I8 = 304, PPC_ATOMIC_LOAD_UMIN_I16 = 305, PPC_ATOMIC_LOAD_UMIN_I32 = 306, PPC_ATOMIC_LOAD_UMIN_I64 = 307, PPC_ATOMIC_LOAD_UMIN_I8 = 308, PPC_ATOMIC_LOAD_XOR_I16 = 309, PPC_ATOMIC_LOAD_XOR_I32 = 310, PPC_ATOMIC_LOAD_XOR_I64 = 311, PPC_ATOMIC_LOAD_XOR_I8 = 312, PPC_ATOMIC_SWAP_I16 = 313, PPC_ATOMIC_SWAP_I32 = 314, PPC_ATOMIC_SWAP_I64 = 315, PPC_ATOMIC_SWAP_I8 = 316, PPC_ATTN = 317, PPC_B = 318, PPC_BA = 319, PPC_BC = 320, PPC_BCC = 321, PPC_BCCA = 322, PPC_BCCCTR = 323, PPC_BCCCTR8 = 324, PPC_BCCCTRL = 325, PPC_BCCCTRL8 = 326, PPC_BCCL = 327, PPC_BCCLA = 328, PPC_BCCLR = 329, PPC_BCCLRL = 330, PPC_BCCTR = 331, PPC_BCCTR8 = 332, PPC_BCCTR8n = 333, PPC_BCCTRL = 334, PPC_BCCTRL8 = 335, PPC_BCCTRL8n = 336, PPC_BCCTRLn = 337, PPC_BCCTRn = 338, PPC_BCDCFNo = 339, PPC_BCDCFSQo = 340, PPC_BCDCFZo = 341, PPC_BCDCPSGNo = 342, PPC_BCDCTNo = 343, PPC_BCDCTSQo = 344, PPC_BCDCTZo = 345, PPC_BCDSETSGNo = 346, PPC_BCDSRo = 347, PPC_BCDSo = 348, PPC_BCDTRUNCo = 349, PPC_BCDUSo = 350, PPC_BCDUTRUNCo = 351, PPC_BCL = 352, PPC_BCLR = 353, PPC_BCLRL = 354, PPC_BCLRLn = 355, PPC_BCLRn = 356, PPC_BCLalways = 357, PPC_BCLn = 358, PPC_BCTR = 359, PPC_BCTR8 = 360, PPC_BCTRL = 361, PPC_BCTRL8 = 362, PPC_BCTRL8_LDinto_toc = 363, PPC_BCn = 364, PPC_BDNZ = 365, PPC_BDNZ8 = 366, PPC_BDNZA = 367, PPC_BDNZAm = 368, PPC_BDNZAp = 369, PPC_BDNZL = 370, PPC_BDNZLA = 371, PPC_BDNZLAm = 372, PPC_BDNZLAp = 373, PPC_BDNZLR = 374, PPC_BDNZLR8 = 375, PPC_BDNZLRL = 376, PPC_BDNZLRLm = 377, PPC_BDNZLRLp = 378, PPC_BDNZLRm = 379, PPC_BDNZLRp = 380, PPC_BDNZLm = 381, PPC_BDNZLp = 382, PPC_BDNZm = 383, PPC_BDNZp = 384, PPC_BDZ = 385, PPC_BDZ8 = 386, PPC_BDZA = 387, PPC_BDZAm = 388, PPC_BDZAp = 389, PPC_BDZL = 390, PPC_BDZLA = 391, PPC_BDZLAm = 392, PPC_BDZLAp = 393, PPC_BDZLR = 394, PPC_BDZLR8 = 395, PPC_BDZLRL = 396, PPC_BDZLRLm = 397, PPC_BDZLRLp = 398, PPC_BDZLRm = 399, PPC_BDZLRp = 400, PPC_BDZLm = 401, PPC_BDZLp = 402, PPC_BDZm = 403, PPC_BDZp = 404, PPC_BL = 405, PPC_BL8 = 406, PPC_BL8_NOP = 407, PPC_BL8_NOP_TLS = 408, PPC_BL8_TLS = 409, PPC_BL8_TLS_ = 410, PPC_BLA = 411, PPC_BLA8 = 412, PPC_BLA8_NOP = 413, PPC_BLR = 414, PPC_BLR8 = 415, PPC_BLRL = 416, PPC_BL_TLS = 417, PPC_BPERMD = 418, PPC_BRINC = 419, PPC_CLRBHRB = 420, PPC_CMPB = 421, PPC_CMPB8 = 422, PPC_CMPD = 423, PPC_CMPDI = 424, PPC_CMPEQB = 425, PPC_CMPLD = 426, PPC_CMPLDI = 427, PPC_CMPLW = 428, PPC_CMPLWI = 429, PPC_CMPRB = 430, PPC_CMPRB8 = 431, PPC_CMPW = 432, PPC_CMPWI = 433, PPC_CNTLZD = 434, PPC_CNTLZDo = 435, PPC_CNTLZW = 436, PPC_CNTLZW8 = 437, PPC_CNTLZW8o = 438, PPC_CNTLZWo = 439, PPC_CNTTZD = 440, PPC_CNTTZDo = 441, PPC_CNTTZW = 442, PPC_CNTTZW8 = 443, PPC_CNTTZW8o = 444, PPC_CNTTZWo = 445, PPC_CP_ABORT = 446, PPC_CP_COPY = 447, PPC_CP_COPY8 = 448, PPC_CP_PASTE = 449, PPC_CP_PASTE8 = 450, PPC_CP_PASTE8o = 451, PPC_CP_PASTEo = 452, PPC_CR6SET = 453, PPC_CR6UNSET = 454, PPC_CRAND = 455, PPC_CRANDC = 456, PPC_CREQV = 457, PPC_CRNAND = 458, PPC_CRNOR = 459, PPC_CROR = 460, PPC_CRORC = 461, PPC_CRSET = 462, PPC_CRUNSET = 463, PPC_CRXOR = 464, PPC_CTRL_DEP = 465, PPC_DARN = 466, PPC_DCBA = 467, PPC_DCBF = 468, PPC_DCBFEP = 469, PPC_DCBI = 470, PPC_DCBST = 471, PPC_DCBSTEP = 472, PPC_DCBT = 473, PPC_DCBTEP = 474, PPC_DCBTST = 475, PPC_DCBTSTEP = 476, PPC_DCBZ = 477, PPC_DCBZEP = 478, PPC_DCBZL = 479, PPC_DCBZLEP = 480, PPC_DCCCI = 481, PPC_DIVD = 482, PPC_DIVDE = 483, PPC_DIVDEU = 484, PPC_DIVDEUo = 485, PPC_DIVDEo = 486, PPC_DIVDU = 487, PPC_DIVDUo = 488, PPC_DIVDo = 489, PPC_DIVW = 490, PPC_DIVWE = 491, PPC_DIVWEU = 492, PPC_DIVWEUo = 493, PPC_DIVWEo = 494, PPC_DIVWU = 495, PPC_DIVWUo = 496, PPC_DIVWo = 497, PPC_DSS = 498, PPC_DSSALL = 499, PPC_DST = 500, PPC_DST64 = 501, PPC_DSTST = 502, PPC_DSTST64 = 503, PPC_DSTSTT = 504, PPC_DSTSTT64 = 505, PPC_DSTT = 506, PPC_DSTT64 = 507, PPC_DYNALLOC = 508, PPC_DYNALLOC8 = 509, PPC_DYNAREAOFFSET = 510, PPC_DYNAREAOFFSET8 = 511, PPC_EFDABS = 512, PPC_EFDADD = 513, PPC_EFDCFS = 514, PPC_EFDCFSF = 515, PPC_EFDCFSI = 516, PPC_EFDCFSID = 517, PPC_EFDCFUF = 518, PPC_EFDCFUI = 519, PPC_EFDCFUID = 520, PPC_EFDCMPEQ = 521, PPC_EFDCMPGT = 522, PPC_EFDCMPLT = 523, PPC_EFDCTSF = 524, PPC_EFDCTSI = 525, PPC_EFDCTSIDZ = 526, PPC_EFDCTSIZ = 527, PPC_EFDCTUF = 528, PPC_EFDCTUI = 529, PPC_EFDCTUIDZ = 530, PPC_EFDCTUIZ = 531, PPC_EFDDIV = 532, PPC_EFDMUL = 533, PPC_EFDNABS = 534, PPC_EFDNEG = 535, PPC_EFDSUB = 536, PPC_EFDTSTEQ = 537, PPC_EFDTSTGT = 538, PPC_EFDTSTLT = 539, PPC_EFSABS = 540, PPC_EFSADD = 541, PPC_EFSCFD = 542, PPC_EFSCFSF = 543, PPC_EFSCFSI = 544, PPC_EFSCFUF = 545, PPC_EFSCFUI = 546, PPC_EFSCMPEQ = 547, PPC_EFSCMPGT = 548, PPC_EFSCMPLT = 549, PPC_EFSCTSF = 550, PPC_EFSCTSI = 551, PPC_EFSCTSIZ = 552, PPC_EFSCTUF = 553, PPC_EFSCTUI = 554, PPC_EFSCTUIZ = 555, PPC_EFSDIV = 556, PPC_EFSMUL = 557, PPC_EFSNABS = 558, PPC_EFSNEG = 559, PPC_EFSSUB = 560, PPC_EFSTSTEQ = 561, PPC_EFSTSTGT = 562, PPC_EFSTSTLT = 563, PPC_EH_SjLj_LongJmp32 = 564, PPC_EH_SjLj_LongJmp64 = 565, PPC_EH_SjLj_SetJmp32 = 566, PPC_EH_SjLj_SetJmp64 = 567, PPC_EH_SjLj_Setup = 568, PPC_EQV = 569, PPC_EQV8 = 570, PPC_EQV8o = 571, PPC_EQVo = 572, PPC_EVABS = 573, PPC_EVADDIW = 574, PPC_EVADDSMIAAW = 575, PPC_EVADDSSIAAW = 576, PPC_EVADDUMIAAW = 577, PPC_EVADDUSIAAW = 578, PPC_EVADDW = 579, PPC_EVAND = 580, PPC_EVANDC = 581, PPC_EVCMPEQ = 582, PPC_EVCMPGTS = 583, PPC_EVCMPGTU = 584, PPC_EVCMPLTS = 585, PPC_EVCMPLTU = 586, PPC_EVCNTLSW = 587, PPC_EVCNTLZW = 588, PPC_EVDIVWS = 589, PPC_EVDIVWU = 590, PPC_EVEQV = 591, PPC_EVEXTSB = 592, PPC_EVEXTSH = 593, PPC_EVFSABS = 594, PPC_EVFSADD = 595, PPC_EVFSCFSF = 596, PPC_EVFSCFSI = 597, PPC_EVFSCFUF = 598, PPC_EVFSCFUI = 599, PPC_EVFSCMPEQ = 600, PPC_EVFSCMPGT = 601, PPC_EVFSCMPLT = 602, PPC_EVFSCTSF = 603, PPC_EVFSCTSI = 604, PPC_EVFSCTSIZ = 605, PPC_EVFSCTUF = 606, PPC_EVFSCTUI = 607, PPC_EVFSCTUIZ = 608, PPC_EVFSDIV = 609, PPC_EVFSMUL = 610, PPC_EVFSNABS = 611, PPC_EVFSNEG = 612, PPC_EVFSSUB = 613, PPC_EVFSTSTEQ = 614, PPC_EVFSTSTGT = 615, PPC_EVFSTSTLT = 616, PPC_EVLDD = 617, PPC_EVLDDX = 618, PPC_EVLDH = 619, PPC_EVLDHX = 620, PPC_EVLDW = 621, PPC_EVLDWX = 622, PPC_EVLHHESPLAT = 623, PPC_EVLHHESPLATX = 624, PPC_EVLHHOSSPLAT = 625, PPC_EVLHHOSSPLATX = 626, PPC_EVLHHOUSPLAT = 627, PPC_EVLHHOUSPLATX = 628, PPC_EVLWHE = 629, PPC_EVLWHEX = 630, PPC_EVLWHOS = 631, PPC_EVLWHOSX = 632, PPC_EVLWHOU = 633, PPC_EVLWHOUX = 634, PPC_EVLWHSPLAT = 635, PPC_EVLWHSPLATX = 636, PPC_EVLWWSPLAT = 637, PPC_EVLWWSPLATX = 638, PPC_EVMERGEHI = 639, PPC_EVMERGEHILO = 640, PPC_EVMERGELO = 641, PPC_EVMERGELOHI = 642, PPC_EVMHEGSMFAA = 643, PPC_EVMHEGSMFAN = 644, PPC_EVMHEGSMIAA = 645, PPC_EVMHEGSMIAN = 646, PPC_EVMHEGUMIAA = 647, PPC_EVMHEGUMIAN = 648, PPC_EVMHESMF = 649, PPC_EVMHESMFA = 650, PPC_EVMHESMFAAW = 651, PPC_EVMHESMFANW = 652, PPC_EVMHESMI = 653, PPC_EVMHESMIA = 654, PPC_EVMHESMIAAW = 655, PPC_EVMHESMIANW = 656, PPC_EVMHESSF = 657, PPC_EVMHESSFA = 658, PPC_EVMHESSFAAW = 659, PPC_EVMHESSFANW = 660, PPC_EVMHESSIAAW = 661, PPC_EVMHESSIANW = 662, PPC_EVMHEUMI = 663, PPC_EVMHEUMIA = 664, PPC_EVMHEUMIAAW = 665, PPC_EVMHEUMIANW = 666, PPC_EVMHEUSIAAW = 667, PPC_EVMHEUSIANW = 668, PPC_EVMHOGSMFAA = 669, PPC_EVMHOGSMFAN = 670, PPC_EVMHOGSMIAA = 671, PPC_EVMHOGSMIAN = 672, PPC_EVMHOGUMIAA = 673, PPC_EVMHOGUMIAN = 674, PPC_EVMHOSMF = 675, PPC_EVMHOSMFA = 676, PPC_EVMHOSMFAAW = 677, PPC_EVMHOSMFANW = 678, PPC_EVMHOSMI = 679, PPC_EVMHOSMIA = 680, PPC_EVMHOSMIAAW = 681, PPC_EVMHOSMIANW = 682, PPC_EVMHOSSF = 683, PPC_EVMHOSSFA = 684, PPC_EVMHOSSFAAW = 685, PPC_EVMHOSSFANW = 686, PPC_EVMHOSSIAAW = 687, PPC_EVMHOSSIANW = 688, PPC_EVMHOUMI = 689, PPC_EVMHOUMIA = 690, PPC_EVMHOUMIAAW = 691, PPC_EVMHOUMIANW = 692, PPC_EVMHOUSIAAW = 693, PPC_EVMHOUSIANW = 694, PPC_EVMRA = 695, PPC_EVMWHSMF = 696, PPC_EVMWHSMFA = 697, PPC_EVMWHSMI = 698, PPC_EVMWHSMIA = 699, PPC_EVMWHSSF = 700, PPC_EVMWHSSFA = 701, PPC_EVMWHUMI = 702, PPC_EVMWHUMIA = 703, PPC_EVMWLSMIAAW = 704, PPC_EVMWLSMIANW = 705, PPC_EVMWLSSIAAW = 706, PPC_EVMWLSSIANW = 707, PPC_EVMWLUMI = 708, PPC_EVMWLUMIA = 709, PPC_EVMWLUMIAAW = 710, PPC_EVMWLUMIANW = 711, PPC_EVMWLUSIAAW = 712, PPC_EVMWLUSIANW = 713, PPC_EVMWSMF = 714, PPC_EVMWSMFA = 715, PPC_EVMWSMFAA = 716, PPC_EVMWSMFAN = 717, PPC_EVMWSMI = 718, PPC_EVMWSMIA = 719, PPC_EVMWSMIAA = 720, PPC_EVMWSMIAN = 721, PPC_EVMWSSF = 722, PPC_EVMWSSFA = 723, PPC_EVMWSSFAA = 724, PPC_EVMWSSFAN = 725, PPC_EVMWUMI = 726, PPC_EVMWUMIA = 727, PPC_EVMWUMIAA = 728, PPC_EVMWUMIAN = 729, PPC_EVNAND = 730, PPC_EVNEG = 731, PPC_EVNOR = 732, PPC_EVOR = 733, PPC_EVORC = 734, PPC_EVRLW = 735, PPC_EVRLWI = 736, PPC_EVRNDW = 737, PPC_EVSEL = 738, PPC_EVSLW = 739, PPC_EVSLWI = 740, PPC_EVSPLATFI = 741, PPC_EVSPLATI = 742, PPC_EVSRWIS = 743, PPC_EVSRWIU = 744, PPC_EVSRWS = 745, PPC_EVSRWU = 746, PPC_EVSTDD = 747, PPC_EVSTDDX = 748, PPC_EVSTDH = 749, PPC_EVSTDHX = 750, PPC_EVSTDW = 751, PPC_EVSTDWX = 752, PPC_EVSTWHE = 753, PPC_EVSTWHEX = 754, PPC_EVSTWHO = 755, PPC_EVSTWHOX = 756, PPC_EVSTWWE = 757, PPC_EVSTWWEX = 758, PPC_EVSTWWO = 759, PPC_EVSTWWOX = 760, PPC_EVSUBFSMIAAW = 761, PPC_EVSUBFSSIAAW = 762, PPC_EVSUBFUMIAAW = 763, PPC_EVSUBFUSIAAW = 764, PPC_EVSUBFW = 765, PPC_EVSUBIFW = 766, PPC_EVXOR = 767, PPC_EXTSB = 768, PPC_EXTSB8 = 769, PPC_EXTSB8_32_64 = 770, PPC_EXTSB8o = 771, PPC_EXTSBo = 772, PPC_EXTSH = 773, PPC_EXTSH8 = 774, PPC_EXTSH8_32_64 = 775, PPC_EXTSH8o = 776, PPC_EXTSHo = 777, PPC_EXTSW = 778, PPC_EXTSWSLI = 779, PPC_EXTSWSLIo = 780, PPC_EXTSW_32 = 781, PPC_EXTSW_32_64 = 782, PPC_EXTSW_32_64o = 783, PPC_EXTSWo = 784, PPC_EnforceIEIO = 785, PPC_FABSD = 786, PPC_FABSDo = 787, PPC_FABSS = 788, PPC_FABSSo = 789, PPC_FADD = 790, PPC_FADDS = 791, PPC_FADDSo = 792, PPC_FADDo = 793, PPC_FADDrtz = 794, PPC_FCFID = 795, PPC_FCFIDS = 796, PPC_FCFIDSo = 797, PPC_FCFIDU = 798, PPC_FCFIDUS = 799, PPC_FCFIDUSo = 800, PPC_FCFIDUo = 801, PPC_FCFIDo = 802, PPC_FCMPUD = 803, PPC_FCMPUS = 804, PPC_FCPSGND = 805, PPC_FCPSGNDo = 806, PPC_FCPSGNS = 807, PPC_FCPSGNSo = 808, PPC_FCTID = 809, PPC_FCTIDU = 810, PPC_FCTIDUZ = 811, PPC_FCTIDUZo = 812, PPC_FCTIDUo = 813, PPC_FCTIDZ = 814, PPC_FCTIDZo = 815, PPC_FCTIDo = 816, PPC_FCTIW = 817, PPC_FCTIWU = 818, PPC_FCTIWUZ = 819, PPC_FCTIWUZo = 820, PPC_FCTIWUo = 821, PPC_FCTIWZ = 822, PPC_FCTIWZo = 823, PPC_FCTIWo = 824, PPC_FDIV = 825, PPC_FDIVS = 826, PPC_FDIVSo = 827, PPC_FDIVo = 828, PPC_FMADD = 829, PPC_FMADDS = 830, PPC_FMADDSo = 831, PPC_FMADDo = 832, PPC_FMR = 833, PPC_FMRo = 834, PPC_FMSUB = 835, PPC_FMSUBS = 836, PPC_FMSUBSo = 837, PPC_FMSUBo = 838, PPC_FMUL = 839, PPC_FMULS = 840, PPC_FMULSo = 841, PPC_FMULo = 842, PPC_FNABSD = 843, PPC_FNABSDo = 844, PPC_FNABSS = 845, PPC_FNABSSo = 846, PPC_FNEGD = 847, PPC_FNEGDo = 848, PPC_FNEGS = 849, PPC_FNEGSo = 850, PPC_FNMADD = 851, PPC_FNMADDS = 852, PPC_FNMADDSo = 853, PPC_FNMADDo = 854, PPC_FNMSUB = 855, PPC_FNMSUBS = 856, PPC_FNMSUBSo = 857, PPC_FNMSUBo = 858, PPC_FRE = 859, PPC_FRES = 860, PPC_FRESo = 861, PPC_FREo = 862, PPC_FRIMD = 863, PPC_FRIMDo = 864, PPC_FRIMS = 865, PPC_FRIMSo = 866, PPC_FRIND = 867, PPC_FRINDo = 868, PPC_FRINS = 869, PPC_FRINSo = 870, PPC_FRIPD = 871, PPC_FRIPDo = 872, PPC_FRIPS = 873, PPC_FRIPSo = 874, PPC_FRIZD = 875, PPC_FRIZDo = 876, PPC_FRIZS = 877, PPC_FRIZSo = 878, PPC_FRSP = 879, PPC_FRSPo = 880, PPC_FRSQRTE = 881, PPC_FRSQRTES = 882, PPC_FRSQRTESo = 883, PPC_FRSQRTEo = 884, PPC_FSELD = 885, PPC_FSELDo = 886, PPC_FSELS = 887, PPC_FSELSo = 888, PPC_FSQRT = 889, PPC_FSQRTS = 890, PPC_FSQRTSo = 891, PPC_FSQRTo = 892, PPC_FSUB = 893, PPC_FSUBS = 894, PPC_FSUBSo = 895, PPC_FSUBo = 896, PPC_FTDIV = 897, PPC_FTSQRT = 898, PPC_GETtlsADDR = 899, PPC_GETtlsADDR32 = 900, PPC_GETtlsldADDR = 901, PPC_GETtlsldADDR32 = 902, PPC_HRFID = 903, PPC_ICBI = 904, PPC_ICBIEP = 905, PPC_ICBLC = 906, PPC_ICBLQ = 907, PPC_ICBT = 908, PPC_ICBTLS = 909, PPC_ICCCI = 910, PPC_ISEL = 911, PPC_ISEL8 = 912, PPC_ISYNC = 913, PPC_LA = 914, PPC_LBARX = 915, PPC_LBARXL = 916, PPC_LBEPX = 917, PPC_LBZ = 918, PPC_LBZ8 = 919, PPC_LBZCIX = 920, PPC_LBZU = 921, PPC_LBZU8 = 922, PPC_LBZUX = 923, PPC_LBZUX8 = 924, PPC_LBZX = 925, PPC_LBZX8 = 926, PPC_LBZXTLS = 927, PPC_LBZXTLS_ = 928, PPC_LBZXTLS_32 = 929, PPC_LD = 930, PPC_LDARX = 931, PPC_LDARXL = 932, PPC_LDAT = 933, PPC_LDBRX = 934, PPC_LDCIX = 935, PPC_LDMX = 936, PPC_LDU = 937, PPC_LDUX = 938, PPC_LDX = 939, PPC_LDXTLS = 940, PPC_LDXTLS_ = 941, PPC_LDgotTprelL = 942, PPC_LDgotTprelL32 = 943, PPC_LDtoc = 944, PPC_LDtocBA = 945, PPC_LDtocCPT = 946, PPC_LDtocJTI = 947, PPC_LDtocL = 948, PPC_LFD = 949, PPC_LFDEPX = 950, PPC_LFDU = 951, PPC_LFDUX = 952, PPC_LFDX = 953, PPC_LFIWAX = 954, PPC_LFIWZX = 955, PPC_LFS = 956, PPC_LFSU = 957, PPC_LFSUX = 958, PPC_LFSX = 959, PPC_LHA = 960, PPC_LHA8 = 961, PPC_LHARX = 962, PPC_LHARXL = 963, PPC_LHAU = 964, PPC_LHAU8 = 965, PPC_LHAUX = 966, PPC_LHAUX8 = 967, PPC_LHAX = 968, PPC_LHAX8 = 969, PPC_LHBRX = 970, PPC_LHBRX8 = 971, PPC_LHEPX = 972, PPC_LHZ = 973, PPC_LHZ8 = 974, PPC_LHZCIX = 975, PPC_LHZU = 976, PPC_LHZU8 = 977, PPC_LHZUX = 978, PPC_LHZUX8 = 979, PPC_LHZX = 980, PPC_LHZX8 = 981, PPC_LHZXTLS = 982, PPC_LHZXTLS_ = 983, PPC_LHZXTLS_32 = 984, PPC_LI = 985, PPC_LI8 = 986, PPC_LIS = 987, PPC_LIS8 = 988, PPC_LMW = 989, PPC_LSWI = 990, PPC_LVEBX = 991, PPC_LVEHX = 992, PPC_LVEWX = 993, PPC_LVSL = 994, PPC_LVSR = 995, PPC_LVX = 996, PPC_LVXL = 997, PPC_LWA = 998, PPC_LWARX = 999, PPC_LWARXL = 1000, PPC_LWAT = 1001, PPC_LWAUX = 1002, PPC_LWAX = 1003, PPC_LWAX_32 = 1004, PPC_LWA_32 = 1005, PPC_LWBRX = 1006, PPC_LWBRX8 = 1007, PPC_LWEPX = 1008, PPC_LWZ = 1009, PPC_LWZ8 = 1010, PPC_LWZCIX = 1011, PPC_LWZU = 1012, PPC_LWZU8 = 1013, PPC_LWZUX = 1014, PPC_LWZUX8 = 1015, PPC_LWZX = 1016, PPC_LWZX8 = 1017, PPC_LWZXTLS = 1018, PPC_LWZXTLS_ = 1019, PPC_LWZXTLS_32 = 1020, PPC_LWZtoc = 1021, PPC_LXSD = 1022, PPC_LXSDX = 1023, PPC_LXSIBZX = 1024, PPC_LXSIHZX = 1025, PPC_LXSIWAX = 1026, PPC_LXSIWZX = 1027, PPC_LXSSP = 1028, PPC_LXSSPX = 1029, PPC_LXV = 1030, PPC_LXVB16X = 1031, PPC_LXVD2X = 1032, PPC_LXVDSX = 1033, PPC_LXVH8X = 1034, PPC_LXVL = 1035, PPC_LXVLL = 1036, PPC_LXVW4X = 1037, PPC_LXVWSX = 1038, PPC_LXVX = 1039, PPC_MADDHD = 1040, PPC_MADDHDU = 1041, PPC_MADDLD = 1042, PPC_MBAR = 1043, PPC_MCRF = 1044, PPC_MCRFS = 1045, PPC_MCRXRX = 1046, PPC_MFBHRBE = 1047, PPC_MFCR = 1048, PPC_MFCR8 = 1049, PPC_MFCTR = 1050, PPC_MFCTR8 = 1051, PPC_MFDCR = 1052, PPC_MFFS = 1053, PPC_MFFSCDRN = 1054, PPC_MFFSCDRNI = 1055, PPC_MFFSCE = 1056, PPC_MFFSCRN = 1057, PPC_MFFSCRNI = 1058, PPC_MFFSL = 1059, PPC_MFFSo = 1060, PPC_MFLR = 1061, PPC_MFLR8 = 1062, PPC_MFMSR = 1063, PPC_MFOCRF = 1064, PPC_MFOCRF8 = 1065, PPC_MFPMR = 1066, PPC_MFSPR = 1067, PPC_MFSPR8 = 1068, PPC_MFSR = 1069, PPC_MFSRIN = 1070, PPC_MFTB = 1071, PPC_MFTB8 = 1072, PPC_MFVRD = 1073, PPC_MFVRSAVE = 1074, PPC_MFVRSAVEv = 1075, PPC_MFVSCR = 1076, PPC_MFVSRD = 1077, PPC_MFVSRLD = 1078, PPC_MFVSRWZ = 1079, PPC_MODSD = 1080, PPC_MODSW = 1081, PPC_MODUD = 1082, PPC_MODUW = 1083, PPC_MSGSYNC = 1084, PPC_MSYNC = 1085, PPC_MTCRF = 1086, PPC_MTCRF8 = 1087, PPC_MTCTR = 1088, PPC_MTCTR8 = 1089, PPC_MTCTR8loop = 1090, PPC_MTCTRloop = 1091, PPC_MTDCR = 1092, PPC_MTFSB0 = 1093, PPC_MTFSB1 = 1094, PPC_MTFSF = 1095, PPC_MTFSFI = 1096, PPC_MTFSFIo = 1097, PPC_MTFSFb = 1098, PPC_MTFSFo = 1099, PPC_MTLR = 1100, PPC_MTLR8 = 1101, PPC_MTMSR = 1102, PPC_MTMSRD = 1103, PPC_MTOCRF = 1104, PPC_MTOCRF8 = 1105, PPC_MTPMR = 1106, PPC_MTSPR = 1107, PPC_MTSPR8 = 1108, PPC_MTSR = 1109, PPC_MTSRIN = 1110, PPC_MTVRSAVE = 1111, PPC_MTVRSAVEv = 1112, PPC_MTVSCR = 1113, PPC_MTVSRD = 1114, PPC_MTVSRDD = 1115, PPC_MTVSRWA = 1116, PPC_MTVSRWS = 1117, PPC_MTVSRWZ = 1118, PPC_MULHD = 1119, PPC_MULHDU = 1120, PPC_MULHDUo = 1121, PPC_MULHDo = 1122, PPC_MULHW = 1123, PPC_MULHWU = 1124, PPC_MULHWUo = 1125, PPC_MULHWo = 1126, PPC_MULLD = 1127, PPC_MULLDo = 1128, PPC_MULLI = 1129, PPC_MULLI8 = 1130, PPC_MULLW = 1131, PPC_MULLWo = 1132, PPC_MoveGOTtoLR = 1133, PPC_MovePCtoLR = 1134, PPC_MovePCtoLR8 = 1135, PPC_NAND = 1136, PPC_NAND8 = 1137, PPC_NAND8o = 1138, PPC_NANDo = 1139, PPC_NAP = 1140, PPC_NEG = 1141, PPC_NEG8 = 1142, PPC_NEG8o = 1143, PPC_NEGo = 1144, PPC_NOP = 1145, PPC_NOP_GT_PWR6 = 1146, PPC_NOP_GT_PWR7 = 1147, PPC_NOR = 1148, PPC_NOR8 = 1149, PPC_NOR8o = 1150, PPC_NORo = 1151, PPC_OR = 1152, PPC_OR8 = 1153, PPC_OR8o = 1154, PPC_ORC = 1155, PPC_ORC8 = 1156, PPC_ORC8o = 1157, PPC_ORCo = 1158, PPC_ORI = 1159, PPC_ORI8 = 1160, PPC_ORIS = 1161, PPC_ORIS8 = 1162, PPC_ORo = 1163, PPC_POPCNTB = 1164, PPC_POPCNTD = 1165, PPC_POPCNTW = 1166, PPC_PPC32GOT = 1167, PPC_PPC32PICGOT = 1168, PPC_QVALIGNI = 1169, PPC_QVALIGNIb = 1170, PPC_QVALIGNIs = 1171, PPC_QVESPLATI = 1172, PPC_QVESPLATIb = 1173, PPC_QVESPLATIs = 1174, PPC_QVFABS = 1175, PPC_QVFABSs = 1176, PPC_QVFADD = 1177, PPC_QVFADDS = 1178, PPC_QVFADDSs = 1179, PPC_QVFCFID = 1180, PPC_QVFCFIDS = 1181, PPC_QVFCFIDU = 1182, PPC_QVFCFIDUS = 1183, PPC_QVFCFIDb = 1184, PPC_QVFCMPEQ = 1185, PPC_QVFCMPEQb = 1186, PPC_QVFCMPEQbs = 1187, PPC_QVFCMPGT = 1188, PPC_QVFCMPGTb = 1189, PPC_QVFCMPGTbs = 1190, PPC_QVFCMPLT = 1191, PPC_QVFCMPLTb = 1192, PPC_QVFCMPLTbs = 1193, PPC_QVFCPSGN = 1194, PPC_QVFCPSGNs = 1195, PPC_QVFCTID = 1196, PPC_QVFCTIDU = 1197, PPC_QVFCTIDUZ = 1198, PPC_QVFCTIDZ = 1199, PPC_QVFCTIDb = 1200, PPC_QVFCTIW = 1201, PPC_QVFCTIWU = 1202, PPC_QVFCTIWUZ = 1203, PPC_QVFCTIWZ = 1204, PPC_QVFLOGICAL = 1205, PPC_QVFLOGICALb = 1206, PPC_QVFLOGICALs = 1207, PPC_QVFMADD = 1208, PPC_QVFMADDS = 1209, PPC_QVFMADDSs = 1210, PPC_QVFMR = 1211, PPC_QVFMRb = 1212, PPC_QVFMRs = 1213, PPC_QVFMSUB = 1214, PPC_QVFMSUBS = 1215, PPC_QVFMSUBSs = 1216, PPC_QVFMUL = 1217, PPC_QVFMULS = 1218, PPC_QVFMULSs = 1219, PPC_QVFNABS = 1220, PPC_QVFNABSs = 1221, PPC_QVFNEG = 1222, PPC_QVFNEGs = 1223, PPC_QVFNMADD = 1224, PPC_QVFNMADDS = 1225, PPC_QVFNMADDSs = 1226, PPC_QVFNMSUB = 1227, PPC_QVFNMSUBS = 1228, PPC_QVFNMSUBSs = 1229, PPC_QVFPERM = 1230, PPC_QVFPERMs = 1231, PPC_QVFRE = 1232, PPC_QVFRES = 1233, PPC_QVFRESs = 1234, PPC_QVFRIM = 1235, PPC_QVFRIMs = 1236, PPC_QVFRIN = 1237, PPC_QVFRINs = 1238, PPC_QVFRIP = 1239, PPC_QVFRIPs = 1240, PPC_QVFRIZ = 1241, PPC_QVFRIZs = 1242, PPC_QVFRSP = 1243, PPC_QVFRSPs = 1244, PPC_QVFRSQRTE = 1245, PPC_QVFRSQRTES = 1246, PPC_QVFRSQRTESs = 1247, PPC_QVFSEL = 1248, PPC_QVFSELb = 1249, PPC_QVFSELbb = 1250, PPC_QVFSELbs = 1251, PPC_QVFSUB = 1252, PPC_QVFSUBS = 1253, PPC_QVFSUBSs = 1254, PPC_QVFTSTNAN = 1255, PPC_QVFTSTNANb = 1256, PPC_QVFTSTNANbs = 1257, PPC_QVFXMADD = 1258, PPC_QVFXMADDS = 1259, PPC_QVFXMUL = 1260, PPC_QVFXMULS = 1261, PPC_QVFXXCPNMADD = 1262, PPC_QVFXXCPNMADDS = 1263, PPC_QVFXXMADD = 1264, PPC_QVFXXMADDS = 1265, PPC_QVFXXNPMADD = 1266, PPC_QVFXXNPMADDS = 1267, PPC_QVGPCI = 1268, PPC_QVLFCDUX = 1269, PPC_QVLFCDUXA = 1270, PPC_QVLFCDX = 1271, PPC_QVLFCDXA = 1272, PPC_QVLFCSUX = 1273, PPC_QVLFCSUXA = 1274, PPC_QVLFCSX = 1275, PPC_QVLFCSXA = 1276, PPC_QVLFCSXs = 1277, PPC_QVLFDUX = 1278, PPC_QVLFDUXA = 1279, PPC_QVLFDX = 1280, PPC_QVLFDXA = 1281, PPC_QVLFDXb = 1282, PPC_QVLFIWAX = 1283, PPC_QVLFIWAXA = 1284, PPC_QVLFIWZX = 1285, PPC_QVLFIWZXA = 1286, PPC_QVLFSUX = 1287, PPC_QVLFSUXA = 1288, PPC_QVLFSX = 1289, PPC_QVLFSXA = 1290, PPC_QVLFSXb = 1291, PPC_QVLFSXs = 1292, PPC_QVLPCLDX = 1293, PPC_QVLPCLSX = 1294, PPC_QVLPCLSXint = 1295, PPC_QVLPCRDX = 1296, PPC_QVLPCRSX = 1297, PPC_QVSTFCDUX = 1298, PPC_QVSTFCDUXA = 1299, PPC_QVSTFCDUXI = 1300, PPC_QVSTFCDUXIA = 1301, PPC_QVSTFCDX = 1302, PPC_QVSTFCDXA = 1303, PPC_QVSTFCDXI = 1304, PPC_QVSTFCDXIA = 1305, PPC_QVSTFCSUX = 1306, PPC_QVSTFCSUXA = 1307, PPC_QVSTFCSUXI = 1308, PPC_QVSTFCSUXIA = 1309, PPC_QVSTFCSX = 1310, PPC_QVSTFCSXA = 1311, PPC_QVSTFCSXI = 1312, PPC_QVSTFCSXIA = 1313, PPC_QVSTFCSXs = 1314, PPC_QVSTFDUX = 1315, PPC_QVSTFDUXA = 1316, PPC_QVSTFDUXI = 1317, PPC_QVSTFDUXIA = 1318, PPC_QVSTFDX = 1319, PPC_QVSTFDXA = 1320, PPC_QVSTFDXI = 1321, PPC_QVSTFDXIA = 1322, PPC_QVSTFDXb = 1323, PPC_QVSTFIWX = 1324, PPC_QVSTFIWXA = 1325, PPC_QVSTFSUX = 1326, PPC_QVSTFSUXA = 1327, PPC_QVSTFSUXI = 1328, PPC_QVSTFSUXIA = 1329, PPC_QVSTFSUXs = 1330, PPC_QVSTFSX = 1331, PPC_QVSTFSXA = 1332, PPC_QVSTFSXI = 1333, PPC_QVSTFSXIA = 1334, PPC_QVSTFSXs = 1335, PPC_RESTORE_CR = 1336, PPC_RESTORE_CRBIT = 1337, PPC_RESTORE_VRSAVE = 1338, PPC_RFCI = 1339, PPC_RFDI = 1340, PPC_RFEBB = 1341, PPC_RFI = 1342, PPC_RFID = 1343, PPC_RFMCI = 1344, PPC_RLDCL = 1345, PPC_RLDCLo = 1346, PPC_RLDCR = 1347, PPC_RLDCRo = 1348, PPC_RLDIC = 1349, PPC_RLDICL = 1350, PPC_RLDICL_32 = 1351, PPC_RLDICL_32_64 = 1352, PPC_RLDICL_32o = 1353, PPC_RLDICLo = 1354, PPC_RLDICR = 1355, PPC_RLDICR_32 = 1356, PPC_RLDICRo = 1357, PPC_RLDICo = 1358, PPC_RLDIMI = 1359, PPC_RLDIMIo = 1360, PPC_RLWIMI = 1361, PPC_RLWIMI8 = 1362, PPC_RLWIMI8o = 1363, PPC_RLWIMIo = 1364, PPC_RLWINM = 1365, PPC_RLWINM8 = 1366, PPC_RLWINM8o = 1367, PPC_RLWINMo = 1368, PPC_RLWNM = 1369, PPC_RLWNM8 = 1370, PPC_RLWNM8o = 1371, PPC_RLWNMo = 1372, PPC_ReadTB = 1373, PPC_SC = 1374, PPC_SELECT_CC_F16 = 1375, PPC_SELECT_CC_F4 = 1376, PPC_SELECT_CC_F8 = 1377, PPC_SELECT_CC_I4 = 1378, PPC_SELECT_CC_I8 = 1379, PPC_SELECT_CC_QBRC = 1380, PPC_SELECT_CC_QFRC = 1381, PPC_SELECT_CC_QSRC = 1382, PPC_SELECT_CC_SPE = 1383, PPC_SELECT_CC_SPE4 = 1384, PPC_SELECT_CC_VRRC = 1385, PPC_SELECT_CC_VSFRC = 1386, PPC_SELECT_CC_VSRC = 1387, PPC_SELECT_CC_VSSRC = 1388, PPC_SELECT_F16 = 1389, PPC_SELECT_F4 = 1390, PPC_SELECT_F8 = 1391, PPC_SELECT_I4 = 1392, PPC_SELECT_I8 = 1393, PPC_SELECT_QBRC = 1394, PPC_SELECT_QFRC = 1395, PPC_SELECT_QSRC = 1396, PPC_SELECT_SPE = 1397, PPC_SELECT_SPE4 = 1398, PPC_SELECT_VRRC = 1399, PPC_SELECT_VSFRC = 1400, PPC_SELECT_VSRC = 1401, PPC_SELECT_VSSRC = 1402, PPC_SETB = 1403, PPC_SLBIA = 1404, PPC_SLBIE = 1405, PPC_SLBIEG = 1406, PPC_SLBMFEE = 1407, PPC_SLBMFEV = 1408, PPC_SLBMTE = 1409, PPC_SLBSYNC = 1410, PPC_SLD = 1411, PPC_SLDo = 1412, PPC_SLW = 1413, PPC_SLW8 = 1414, PPC_SLW8o = 1415, PPC_SLWo = 1416, PPC_SPELWZ = 1417, PPC_SPELWZX = 1418, PPC_SPESTW = 1419, PPC_SPESTWX = 1420, PPC_SPILL_CR = 1421, PPC_SPILL_CRBIT = 1422, PPC_SPILL_VRSAVE = 1423, PPC_SRAD = 1424, PPC_SRADI = 1425, PPC_SRADI_32 = 1426, PPC_SRADIo = 1427, PPC_SRADo = 1428, PPC_SRAW = 1429, PPC_SRAWI = 1430, PPC_SRAWIo = 1431, PPC_SRAWo = 1432, PPC_SRD = 1433, PPC_SRDo = 1434, PPC_SRW = 1435, PPC_SRW8 = 1436, PPC_SRW8o = 1437, PPC_SRWo = 1438, PPC_STB = 1439, PPC_STB8 = 1440, PPC_STBCIX = 1441, PPC_STBCX = 1442, PPC_STBEPX = 1443, PPC_STBU = 1444, PPC_STBU8 = 1445, PPC_STBUX = 1446, PPC_STBUX8 = 1447, PPC_STBX = 1448, PPC_STBX8 = 1449, PPC_STBXTLS = 1450, PPC_STBXTLS_ = 1451, PPC_STBXTLS_32 = 1452, PPC_STD = 1453, PPC_STDAT = 1454, PPC_STDBRX = 1455, PPC_STDCIX = 1456, PPC_STDCX = 1457, PPC_STDU = 1458, PPC_STDUX = 1459, PPC_STDX = 1460, PPC_STDXTLS = 1461, PPC_STDXTLS_ = 1462, PPC_STFD = 1463, PPC_STFDEPX = 1464, PPC_STFDU = 1465, PPC_STFDUX = 1466, PPC_STFDX = 1467, PPC_STFIWX = 1468, PPC_STFS = 1469, PPC_STFSU = 1470, PPC_STFSUX = 1471, PPC_STFSX = 1472, PPC_STH = 1473, PPC_STH8 = 1474, PPC_STHBRX = 1475, PPC_STHCIX = 1476, PPC_STHCX = 1477, PPC_STHEPX = 1478, PPC_STHU = 1479, PPC_STHU8 = 1480, PPC_STHUX = 1481, PPC_STHUX8 = 1482, PPC_STHX = 1483, PPC_STHX8 = 1484, PPC_STHXTLS = 1485, PPC_STHXTLS_ = 1486, PPC_STHXTLS_32 = 1487, PPC_STMW = 1488, PPC_STOP = 1489, PPC_STSWI = 1490, PPC_STVEBX = 1491, PPC_STVEHX = 1492, PPC_STVEWX = 1493, PPC_STVX = 1494, PPC_STVXL = 1495, PPC_STW = 1496, PPC_STW8 = 1497, PPC_STWAT = 1498, PPC_STWBRX = 1499, PPC_STWCIX = 1500, PPC_STWCX = 1501, PPC_STWEPX = 1502, PPC_STWU = 1503, PPC_STWU8 = 1504, PPC_STWUX = 1505, PPC_STWUX8 = 1506, PPC_STWX = 1507, PPC_STWX8 = 1508, PPC_STWXTLS = 1509, PPC_STWXTLS_ = 1510, PPC_STWXTLS_32 = 1511, PPC_STXSD = 1512, PPC_STXSDX = 1513, PPC_STXSIBX = 1514, PPC_STXSIBXv = 1515, PPC_STXSIHX = 1516, PPC_STXSIHXv = 1517, PPC_STXSIWX = 1518, PPC_STXSSP = 1519, PPC_STXSSPX = 1520, PPC_STXV = 1521, PPC_STXVB16X = 1522, PPC_STXVD2X = 1523, PPC_STXVH8X = 1524, PPC_STXVL = 1525, PPC_STXVLL = 1526, PPC_STXVW4X = 1527, PPC_STXVX = 1528, PPC_SUBF = 1529, PPC_SUBF8 = 1530, PPC_SUBF8o = 1531, PPC_SUBFC = 1532, PPC_SUBFC8 = 1533, PPC_SUBFC8o = 1534, PPC_SUBFCo = 1535, PPC_SUBFE = 1536, PPC_SUBFE8 = 1537, PPC_SUBFE8o = 1538, PPC_SUBFEo = 1539, PPC_SUBFIC = 1540, PPC_SUBFIC8 = 1541, PPC_SUBFME = 1542, PPC_SUBFME8 = 1543, PPC_SUBFME8o = 1544, PPC_SUBFMEo = 1545, PPC_SUBFZE = 1546, PPC_SUBFZE8 = 1547, PPC_SUBFZE8o = 1548, PPC_SUBFZEo = 1549, PPC_SUBFo = 1550, PPC_SYNC = 1551, PPC_TABORT = 1552, PPC_TABORTDC = 1553, PPC_TABORTDCI = 1554, PPC_TABORTWC = 1555, PPC_TABORTWCI = 1556, PPC_TAILB = 1557, PPC_TAILB8 = 1558, PPC_TAILBA = 1559, PPC_TAILBA8 = 1560, PPC_TAILBCTR = 1561, PPC_TAILBCTR8 = 1562, PPC_TBEGIN = 1563, PPC_TCHECK = 1564, PPC_TCHECK_RET = 1565, PPC_TCRETURNai = 1566, PPC_TCRETURNai8 = 1567, PPC_TCRETURNdi = 1568, PPC_TCRETURNdi8 = 1569, PPC_TCRETURNri = 1570, PPC_TCRETURNri8 = 1571, PPC_TD = 1572, PPC_TDI = 1573, PPC_TEND = 1574, PPC_TLBIA = 1575, PPC_TLBIE = 1576, PPC_TLBIEL = 1577, PPC_TLBIVAX = 1578, PPC_TLBLD = 1579, PPC_TLBLI = 1580, PPC_TLBRE = 1581, PPC_TLBRE2 = 1582, PPC_TLBSX = 1583, PPC_TLBSX2 = 1584, PPC_TLBSX2D = 1585, PPC_TLBSYNC = 1586, PPC_TLBWE = 1587, PPC_TLBWE2 = 1588, PPC_TRAP = 1589, PPC_TRECHKPT = 1590, PPC_TRECLAIM = 1591, PPC_TSR = 1592, PPC_TW = 1593, PPC_TWI = 1594, PPC_UPDATE_VRSAVE = 1595, PPC_UpdateGBR = 1596, PPC_VABSDUB = 1597, PPC_VABSDUH = 1598, PPC_VABSDUW = 1599, PPC_VADDCUQ = 1600, PPC_VADDCUW = 1601, PPC_VADDECUQ = 1602, PPC_VADDEUQM = 1603, PPC_VADDFP = 1604, PPC_VADDSBS = 1605, PPC_VADDSHS = 1606, PPC_VADDSWS = 1607, PPC_VADDUBM = 1608, PPC_VADDUBS = 1609, PPC_VADDUDM = 1610, PPC_VADDUHM = 1611, PPC_VADDUHS = 1612, PPC_VADDUQM = 1613, PPC_VADDUWM = 1614, PPC_VADDUWS = 1615, PPC_VAND = 1616, PPC_VANDC = 1617, PPC_VAVGSB = 1618, PPC_VAVGSH = 1619, PPC_VAVGSW = 1620, PPC_VAVGUB = 1621, PPC_VAVGUH = 1622, PPC_VAVGUW = 1623, PPC_VBPERMD = 1624, PPC_VBPERMQ = 1625, PPC_VCFSX = 1626, PPC_VCFSX_0 = 1627, PPC_VCFUX = 1628, PPC_VCFUX_0 = 1629, PPC_VCIPHER = 1630, PPC_VCIPHERLAST = 1631, PPC_VCLZB = 1632, PPC_VCLZD = 1633, PPC_VCLZH = 1634, PPC_VCLZLSBB = 1635, PPC_VCLZW = 1636, PPC_VCMPBFP = 1637, PPC_VCMPBFPo = 1638, PPC_VCMPEQFP = 1639, PPC_VCMPEQFPo = 1640, PPC_VCMPEQUB = 1641, PPC_VCMPEQUBo = 1642, PPC_VCMPEQUD = 1643, PPC_VCMPEQUDo = 1644, PPC_VCMPEQUH = 1645, PPC_VCMPEQUHo = 1646, PPC_VCMPEQUW = 1647, PPC_VCMPEQUWo = 1648, PPC_VCMPGEFP = 1649, PPC_VCMPGEFPo = 1650, PPC_VCMPGTFP = 1651, PPC_VCMPGTFPo = 1652, PPC_VCMPGTSB = 1653, PPC_VCMPGTSBo = 1654, PPC_VCMPGTSD = 1655, PPC_VCMPGTSDo = 1656, PPC_VCMPGTSH = 1657, PPC_VCMPGTSHo = 1658, PPC_VCMPGTSW = 1659, PPC_VCMPGTSWo = 1660, PPC_VCMPGTUB = 1661, PPC_VCMPGTUBo = 1662, PPC_VCMPGTUD = 1663, PPC_VCMPGTUDo = 1664, PPC_VCMPGTUH = 1665, PPC_VCMPGTUHo = 1666, PPC_VCMPGTUW = 1667, PPC_VCMPGTUWo = 1668, PPC_VCMPNEB = 1669, PPC_VCMPNEBo = 1670, PPC_VCMPNEH = 1671, PPC_VCMPNEHo = 1672, PPC_VCMPNEW = 1673, PPC_VCMPNEWo = 1674, PPC_VCMPNEZB = 1675, PPC_VCMPNEZBo = 1676, PPC_VCMPNEZH = 1677, PPC_VCMPNEZHo = 1678, PPC_VCMPNEZW = 1679, PPC_VCMPNEZWo = 1680, PPC_VCTSXS = 1681, PPC_VCTSXS_0 = 1682, PPC_VCTUXS = 1683, PPC_VCTUXS_0 = 1684, PPC_VCTZB = 1685, PPC_VCTZD = 1686, PPC_VCTZH = 1687, PPC_VCTZLSBB = 1688, PPC_VCTZW = 1689, PPC_VEQV = 1690, PPC_VEXPTEFP = 1691, PPC_VEXTRACTD = 1692, PPC_VEXTRACTUB = 1693, PPC_VEXTRACTUH = 1694, PPC_VEXTRACTUW = 1695, PPC_VEXTSB2D = 1696, PPC_VEXTSB2Ds = 1697, PPC_VEXTSB2W = 1698, PPC_VEXTSB2Ws = 1699, PPC_VEXTSH2D = 1700, PPC_VEXTSH2Ds = 1701, PPC_VEXTSH2W = 1702, PPC_VEXTSH2Ws = 1703, PPC_VEXTSW2D = 1704, PPC_VEXTSW2Ds = 1705, PPC_VEXTUBLX = 1706, PPC_VEXTUBRX = 1707, PPC_VEXTUHLX = 1708, PPC_VEXTUHRX = 1709, PPC_VEXTUWLX = 1710, PPC_VEXTUWRX = 1711, PPC_VGBBD = 1712, PPC_VINSERTB = 1713, PPC_VINSERTD = 1714, PPC_VINSERTH = 1715, PPC_VINSERTW = 1716, PPC_VLOGEFP = 1717, PPC_VMADDFP = 1718, PPC_VMAXFP = 1719, PPC_VMAXSB = 1720, PPC_VMAXSD = 1721, PPC_VMAXSH = 1722, PPC_VMAXSW = 1723, PPC_VMAXUB = 1724, PPC_VMAXUD = 1725, PPC_VMAXUH = 1726, PPC_VMAXUW = 1727, PPC_VMHADDSHS = 1728, PPC_VMHRADDSHS = 1729, PPC_VMINFP = 1730, PPC_VMINSB = 1731, PPC_VMINSD = 1732, PPC_VMINSH = 1733, PPC_VMINSW = 1734, PPC_VMINUB = 1735, PPC_VMINUD = 1736, PPC_VMINUH = 1737, PPC_VMINUW = 1738, PPC_VMLADDUHM = 1739, PPC_VMRGEW = 1740, PPC_VMRGHB = 1741, PPC_VMRGHH = 1742, PPC_VMRGHW = 1743, PPC_VMRGLB = 1744, PPC_VMRGLH = 1745, PPC_VMRGLW = 1746, PPC_VMRGOW = 1747, PPC_VMSUMMBM = 1748, PPC_VMSUMSHM = 1749, PPC_VMSUMSHS = 1750, PPC_VMSUMUBM = 1751, PPC_VMSUMUHM = 1752, PPC_VMSUMUHS = 1753, PPC_VMUL10CUQ = 1754, PPC_VMUL10ECUQ = 1755, PPC_VMUL10EUQ = 1756, PPC_VMUL10UQ = 1757, PPC_VMULESB = 1758, PPC_VMULESH = 1759, PPC_VMULESW = 1760, PPC_VMULEUB = 1761, PPC_VMULEUH = 1762, PPC_VMULEUW = 1763, PPC_VMULOSB = 1764, PPC_VMULOSH = 1765, PPC_VMULOSW = 1766, PPC_VMULOUB = 1767, PPC_VMULOUH = 1768, PPC_VMULOUW = 1769, PPC_VMULUWM = 1770, PPC_VNAND = 1771, PPC_VNCIPHER = 1772, PPC_VNCIPHERLAST = 1773, PPC_VNEGD = 1774, PPC_VNEGW = 1775, PPC_VNMSUBFP = 1776, PPC_VNOR = 1777, PPC_VOR = 1778, PPC_VORC = 1779, PPC_VPERM = 1780, PPC_VPERMR = 1781, PPC_VPERMXOR = 1782, PPC_VPKPX = 1783, PPC_VPKSDSS = 1784, PPC_VPKSDUS = 1785, PPC_VPKSHSS = 1786, PPC_VPKSHUS = 1787, PPC_VPKSWSS = 1788, PPC_VPKSWUS = 1789, PPC_VPKUDUM = 1790, PPC_VPKUDUS = 1791, PPC_VPKUHUM = 1792, PPC_VPKUHUS = 1793, PPC_VPKUWUM = 1794, PPC_VPKUWUS = 1795, PPC_VPMSUMB = 1796, PPC_VPMSUMD = 1797, PPC_VPMSUMH = 1798, PPC_VPMSUMW = 1799, PPC_VPOPCNTB = 1800, PPC_VPOPCNTD = 1801, PPC_VPOPCNTH = 1802, PPC_VPOPCNTW = 1803, PPC_VPRTYBD = 1804, PPC_VPRTYBQ = 1805, PPC_VPRTYBW = 1806, PPC_VREFP = 1807, PPC_VRFIM = 1808, PPC_VRFIN = 1809, PPC_VRFIP = 1810, PPC_VRFIZ = 1811, PPC_VRLB = 1812, PPC_VRLD = 1813, PPC_VRLDMI = 1814, PPC_VRLDNM = 1815, PPC_VRLH = 1816, PPC_VRLW = 1817, PPC_VRLWMI = 1818, PPC_VRLWNM = 1819, PPC_VRSQRTEFP = 1820, PPC_VSBOX = 1821, PPC_VSEL = 1822, PPC_VSHASIGMAD = 1823, PPC_VSHASIGMAW = 1824, PPC_VSL = 1825, PPC_VSLB = 1826, PPC_VSLD = 1827, PPC_VSLDOI = 1828, PPC_VSLH = 1829, PPC_VSLO = 1830, PPC_VSLV = 1831, PPC_VSLW = 1832, PPC_VSPLTB = 1833, PPC_VSPLTBs = 1834, PPC_VSPLTH = 1835, PPC_VSPLTHs = 1836, PPC_VSPLTISB = 1837, PPC_VSPLTISH = 1838, PPC_VSPLTISW = 1839, PPC_VSPLTW = 1840, PPC_VSR = 1841, PPC_VSRAB = 1842, PPC_VSRAD = 1843, PPC_VSRAH = 1844, PPC_VSRAW = 1845, PPC_VSRB = 1846, PPC_VSRD = 1847, PPC_VSRH = 1848, PPC_VSRO = 1849, PPC_VSRV = 1850, PPC_VSRW = 1851, PPC_VSUBCUQ = 1852, PPC_VSUBCUW = 1853, PPC_VSUBECUQ = 1854, PPC_VSUBEUQM = 1855, PPC_VSUBFP = 1856, PPC_VSUBSBS = 1857, PPC_VSUBSHS = 1858, PPC_VSUBSWS = 1859, PPC_VSUBUBM = 1860, PPC_VSUBUBS = 1861, PPC_VSUBUDM = 1862, PPC_VSUBUHM = 1863, PPC_VSUBUHS = 1864, PPC_VSUBUQM = 1865, PPC_VSUBUWM = 1866, PPC_VSUBUWS = 1867, PPC_VSUM2SWS = 1868, PPC_VSUM4SBS = 1869, PPC_VSUM4SHS = 1870, PPC_VSUM4UBS = 1871, PPC_VSUMSWS = 1872, PPC_VUPKHPX = 1873, PPC_VUPKHSB = 1874, PPC_VUPKHSH = 1875, PPC_VUPKHSW = 1876, PPC_VUPKLPX = 1877, PPC_VUPKLSB = 1878, PPC_VUPKLSH = 1879, PPC_VUPKLSW = 1880, PPC_VXOR = 1881, PPC_V_SET0 = 1882, PPC_V_SET0B = 1883, PPC_V_SET0H = 1884, PPC_V_SETALLONES = 1885, PPC_V_SETALLONESB = 1886, PPC_V_SETALLONESH = 1887, PPC_WAIT = 1888, PPC_WRTEE = 1889, PPC_WRTEEI = 1890, PPC_XOR = 1891, PPC_XOR8 = 1892, PPC_XOR8o = 1893, PPC_XORI = 1894, PPC_XORI8 = 1895, PPC_XORIS = 1896, PPC_XORIS8 = 1897, PPC_XORo = 1898, PPC_XSABSDP = 1899, PPC_XSABSQP = 1900, PPC_XSADDDP = 1901, PPC_XSADDQP = 1902, PPC_XSADDQPO = 1903, PPC_XSADDSP = 1904, PPC_XSCMPEQDP = 1905, PPC_XSCMPEXPDP = 1906, PPC_XSCMPEXPQP = 1907, PPC_XSCMPGEDP = 1908, PPC_XSCMPGTDP = 1909, PPC_XSCMPODP = 1910, PPC_XSCMPOQP = 1911, PPC_XSCMPUDP = 1912, PPC_XSCMPUQP = 1913, PPC_XSCPSGNDP = 1914, PPC_XSCPSGNQP = 1915, PPC_XSCVDPHP = 1916, PPC_XSCVDPQP = 1917, PPC_XSCVDPSP = 1918, PPC_XSCVDPSPN = 1919, PPC_XSCVDPSXDS = 1920, PPC_XSCVDPSXDSs = 1921, PPC_XSCVDPSXWS = 1922, PPC_XSCVDPSXWSs = 1923, PPC_XSCVDPUXDS = 1924, PPC_XSCVDPUXDSs = 1925, PPC_XSCVDPUXWS = 1926, PPC_XSCVDPUXWSs = 1927, PPC_XSCVHPDP = 1928, PPC_XSCVQPDP = 1929, PPC_XSCVQPDPO = 1930, PPC_XSCVQPSDZ = 1931, PPC_XSCVQPSWZ = 1932, PPC_XSCVQPUDZ = 1933, PPC_XSCVQPUWZ = 1934, PPC_XSCVSDQP = 1935, PPC_XSCVSPDP = 1936, PPC_XSCVSPDPN = 1937, PPC_XSCVSXDDP = 1938, PPC_XSCVSXDSP = 1939, PPC_XSCVUDQP = 1940, PPC_XSCVUXDDP = 1941, PPC_XSCVUXDSP = 1942, PPC_XSDIVDP = 1943, PPC_XSDIVQP = 1944, PPC_XSDIVQPO = 1945, PPC_XSDIVSP = 1946, PPC_XSIEXPDP = 1947, PPC_XSIEXPQP = 1948, PPC_XSMADDADP = 1949, PPC_XSMADDASP = 1950, PPC_XSMADDMDP = 1951, PPC_XSMADDMSP = 1952, PPC_XSMADDQP = 1953, PPC_XSMADDQPO = 1954, PPC_XSMAXCDP = 1955, PPC_XSMAXDP = 1956, PPC_XSMAXJDP = 1957, PPC_XSMINCDP = 1958, PPC_XSMINDP = 1959, PPC_XSMINJDP = 1960, PPC_XSMSUBADP = 1961, PPC_XSMSUBASP = 1962, PPC_XSMSUBMDP = 1963, PPC_XSMSUBMSP = 1964, PPC_XSMSUBQP = 1965, PPC_XSMSUBQPO = 1966, PPC_XSMULDP = 1967, PPC_XSMULQP = 1968, PPC_XSMULQPO = 1969, PPC_XSMULSP = 1970, PPC_XSNABSDP = 1971, PPC_XSNABSQP = 1972, PPC_XSNEGDP = 1973, PPC_XSNEGQP = 1974, PPC_XSNMADDADP = 1975, PPC_XSNMADDASP = 1976, PPC_XSNMADDMDP = 1977, PPC_XSNMADDMSP = 1978, PPC_XSNMADDQP = 1979, PPC_XSNMADDQPO = 1980, PPC_XSNMSUBADP = 1981, PPC_XSNMSUBASP = 1982, PPC_XSNMSUBMDP = 1983, PPC_XSNMSUBMSP = 1984, PPC_XSNMSUBQP = 1985, PPC_XSNMSUBQPO = 1986, PPC_XSRDPI = 1987, PPC_XSRDPIC = 1988, PPC_XSRDPIM = 1989, PPC_XSRDPIP = 1990, PPC_XSRDPIZ = 1991, PPC_XSREDP = 1992, PPC_XSRESP = 1993, PPC_XSRQPI = 1994, PPC_XSRQPIX = 1995, PPC_XSRQPXP = 1996, PPC_XSRSP = 1997, PPC_XSRSQRTEDP = 1998, PPC_XSRSQRTESP = 1999, PPC_XSSQRTDP = 2000, PPC_XSSQRTQP = 2001, PPC_XSSQRTQPO = 2002, PPC_XSSQRTSP = 2003, PPC_XSSUBDP = 2004, PPC_XSSUBQP = 2005, PPC_XSSUBQPO = 2006, PPC_XSSUBSP = 2007, PPC_XSTDIVDP = 2008, PPC_XSTSQRTDP = 2009, PPC_XSTSTDCDP = 2010, PPC_XSTSTDCQP = 2011, PPC_XSTSTDCSP = 2012, PPC_XSXEXPDP = 2013, PPC_XSXEXPQP = 2014, PPC_XSXSIGDP = 2015, PPC_XSXSIGQP = 2016, PPC_XVABSDP = 2017, PPC_XVABSSP = 2018, PPC_XVADDDP = 2019, PPC_XVADDSP = 2020, PPC_XVCMPEQDP = 2021, PPC_XVCMPEQDPo = 2022, PPC_XVCMPEQSP = 2023, PPC_XVCMPEQSPo = 2024, PPC_XVCMPGEDP = 2025, PPC_XVCMPGEDPo = 2026, PPC_XVCMPGESP = 2027, PPC_XVCMPGESPo = 2028, PPC_XVCMPGTDP = 2029, PPC_XVCMPGTDPo = 2030, PPC_XVCMPGTSP = 2031, PPC_XVCMPGTSPo = 2032, PPC_XVCPSGNDP = 2033, PPC_XVCPSGNSP = 2034, PPC_XVCVDPSP = 2035, PPC_XVCVDPSXDS = 2036, PPC_XVCVDPSXWS = 2037, PPC_XVCVDPUXDS = 2038, PPC_XVCVDPUXWS = 2039, PPC_XVCVHPSP = 2040, PPC_XVCVSPDP = 2041, PPC_XVCVSPHP = 2042, PPC_XVCVSPSXDS = 2043, PPC_XVCVSPSXWS = 2044, PPC_XVCVSPUXDS = 2045, PPC_XVCVSPUXWS = 2046, PPC_XVCVSXDDP = 2047, PPC_XVCVSXDSP = 2048, PPC_XVCVSXWDP = 2049, PPC_XVCVSXWSP = 2050, PPC_XVCVUXDDP = 2051, PPC_XVCVUXDSP = 2052, PPC_XVCVUXWDP = 2053, PPC_XVCVUXWSP = 2054, PPC_XVDIVDP = 2055, PPC_XVDIVSP = 2056, PPC_XVIEXPDP = 2057, PPC_XVIEXPSP = 2058, PPC_XVMADDADP = 2059, PPC_XVMADDASP = 2060, PPC_XVMADDMDP = 2061, PPC_XVMADDMSP = 2062, PPC_XVMAXDP = 2063, PPC_XVMAXSP = 2064, PPC_XVMINDP = 2065, PPC_XVMINSP = 2066, PPC_XVMSUBADP = 2067, PPC_XVMSUBASP = 2068, PPC_XVMSUBMDP = 2069, PPC_XVMSUBMSP = 2070, PPC_XVMULDP = 2071, PPC_XVMULSP = 2072, PPC_XVNABSDP = 2073, PPC_XVNABSSP = 2074, PPC_XVNEGDP = 2075, PPC_XVNEGSP = 2076, PPC_XVNMADDADP = 2077, PPC_XVNMADDASP = 2078, PPC_XVNMADDMDP = 2079, PPC_XVNMADDMSP = 2080, PPC_XVNMSUBADP = 2081, PPC_XVNMSUBASP = 2082, PPC_XVNMSUBMDP = 2083, PPC_XVNMSUBMSP = 2084, PPC_XVRDPI = 2085, PPC_XVRDPIC = 2086, PPC_XVRDPIM = 2087, PPC_XVRDPIP = 2088, PPC_XVRDPIZ = 2089, PPC_XVREDP = 2090, PPC_XVRESP = 2091, PPC_XVRSPI = 2092, PPC_XVRSPIC = 2093, PPC_XVRSPIM = 2094, PPC_XVRSPIP = 2095, PPC_XVRSPIZ = 2096, PPC_XVRSQRTEDP = 2097, PPC_XVRSQRTESP = 2098, PPC_XVSQRTDP = 2099, PPC_XVSQRTSP = 2100, PPC_XVSUBDP = 2101, PPC_XVSUBSP = 2102, PPC_XVTDIVDP = 2103, PPC_XVTDIVSP = 2104, PPC_XVTSQRTDP = 2105, PPC_XVTSQRTSP = 2106, PPC_XVTSTDCDP = 2107, PPC_XVTSTDCSP = 2108, PPC_XVXEXPDP = 2109, PPC_XVXEXPSP = 2110, PPC_XVXSIGDP = 2111, PPC_XVXSIGSP = 2112, PPC_XXBRD = 2113, PPC_XXBRH = 2114, PPC_XXBRQ = 2115, PPC_XXBRW = 2116, PPC_XXEXTRACTUW = 2117, PPC_XXINSERTW = 2118, PPC_XXLAND = 2119, PPC_XXLANDC = 2120, PPC_XXLEQV = 2121, PPC_XXLNAND = 2122, PPC_XXLNOR = 2123, PPC_XXLOR = 2124, PPC_XXLORC = 2125, PPC_XXLORf = 2126, PPC_XXLXOR = 2127, PPC_XXLXORdpz = 2128, PPC_XXLXORspz = 2129, PPC_XXLXORz = 2130, PPC_XXMRGHW = 2131, PPC_XXMRGLW = 2132, PPC_XXPERM = 2133, PPC_XXPERMDI = 2134, PPC_XXPERMDIs = 2135, PPC_XXPERMR = 2136, PPC_XXSEL = 2137, PPC_XXSLDWI = 2138, PPC_XXSLDWIs = 2139, PPC_XXSPLTIB = 2140, PPC_XXSPLTW = 2141, PPC_XXSPLTWs = 2142, PPC_gBC = 2143, PPC_gBCA = 2144, PPC_gBCAat = 2145, PPC_gBCCTR = 2146, PPC_gBCCTRL = 2147, PPC_gBCL = 2148, PPC_gBCLA = 2149, PPC_gBCLAat = 2150, PPC_gBCLR = 2151, PPC_gBCLRL = 2152, PPC_gBCLat = 2153, PPC_gBCat = 2154, PPC_INSTRUCTION_LIST_END = 2155 }; #endif // GET_INSTRINFO_ENUM #ifdef GET_INSTRINFO_MC_DESC #undef GET_INSTRINFO_MC_DESC #define nullptr 0 static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { PPC_NoRegister, PPC_BP = 1, PPC_CARRY = 2, PPC_CTR = 3, PPC_FP = 4, PPC_LR = 5, PPC_RM = 6, PPC_SPEFSCR = 7, PPC_VRSAVE = 8, PPC_XER = 9, PPC_ZERO = 10, PPC_BP8 = 11, PPC_CR0 = 12, PPC_CR1 = 13, PPC_CR2 = 14, PPC_CR3 = 15, PPC_CR4 = 16, PPC_CR5 = 17, PPC_CR6 = 18, PPC_CR7 = 19, PPC_CTR8 = 20, PPC_F0 = 21, PPC_F1 = 22, PPC_F2 = 23, PPC_F3 = 24, PPC_F4 = 25, PPC_F5 = 26, PPC_F6 = 27, PPC_F7 = 28, PPC_F8 = 29, PPC_F9 = 30, PPC_F10 = 31, PPC_F11 = 32, PPC_F12 = 33, PPC_F13 = 34, PPC_F14 = 35, PPC_F15 = 36, PPC_F16 = 37, PPC_F17 = 38, PPC_F18 = 39, PPC_F19 = 40, PPC_F20 = 41, PPC_F21 = 42, PPC_F22 = 43, PPC_F23 = 44, PPC_F24 = 45, PPC_F25 = 46, PPC_F26 = 47, PPC_F27 = 48, PPC_F28 = 49, PPC_F29 = 50, PPC_F30 = 51, PPC_F31 = 52, PPC_FP8 = 53, PPC_LR8 = 54, PPC_QF0 = 55, PPC_QF1 = 56, PPC_QF2 = 57, PPC_QF3 = 58, PPC_QF4 = 59, PPC_QF5 = 60, PPC_QF6 = 61, PPC_QF7 = 62, PPC_QF8 = 63, PPC_QF9 = 64, PPC_QF10 = 65, PPC_QF11 = 66, PPC_QF12 = 67, PPC_QF13 = 68, PPC_QF14 = 69, PPC_QF15 = 70, PPC_QF16 = 71, PPC_QF17 = 72, PPC_QF18 = 73, PPC_QF19 = 74, PPC_QF20 = 75, PPC_QF21 = 76, PPC_QF22 = 77, PPC_QF23 = 78, PPC_QF24 = 79, PPC_QF25 = 80, PPC_QF26 = 81, PPC_QF27 = 82, PPC_QF28 = 83, PPC_QF29 = 84, PPC_QF30 = 85, PPC_QF31 = 86, PPC_R0 = 87, PPC_R1 = 88, PPC_R2 = 89, PPC_R3 = 90, PPC_R4 = 91, PPC_R5 = 92, PPC_R6 = 93, PPC_R7 = 94, PPC_R8 = 95, PPC_R9 = 96, PPC_R10 = 97, PPC_R11 = 98, PPC_R12 = 99, PPC_R13 = 100, PPC_R14 = 101, PPC_R15 = 102, PPC_R16 = 103, PPC_R17 = 104, PPC_R18 = 105, PPC_R19 = 106, PPC_R20 = 107, PPC_R21 = 108, PPC_R22 = 109, PPC_R23 = 110, PPC_R24 = 111, PPC_R25 = 112, PPC_R26 = 113, PPC_R27 = 114, PPC_R28 = 115, PPC_R29 = 116, PPC_R30 = 117, PPC_R31 = 118, PPC_S0 = 119, PPC_S1 = 120, PPC_S2 = 121, PPC_S3 = 122, PPC_S4 = 123, PPC_S5 = 124, PPC_S6 = 125, PPC_S7 = 126, PPC_S8 = 127, PPC_S9 = 128, PPC_S10 = 129, PPC_S11 = 130, PPC_S12 = 131, PPC_S13 = 132, PPC_S14 = 133, PPC_S15 = 134, PPC_S16 = 135, PPC_S17 = 136, PPC_S18 = 137, PPC_S19 = 138, PPC_S20 = 139, PPC_S21 = 140, PPC_S22 = 141, PPC_S23 = 142, PPC_S24 = 143, PPC_S25 = 144, PPC_S26 = 145, PPC_S27 = 146, PPC_S28 = 147, PPC_S29 = 148, PPC_S30 = 149, PPC_S31 = 150, PPC_V0 = 151, PPC_V1 = 152, PPC_V2 = 153, PPC_V3 = 154, PPC_V4 = 155, PPC_V5 = 156, PPC_V6 = 157, PPC_V7 = 158, PPC_V8 = 159, PPC_V9 = 160, PPC_V10 = 161, PPC_V11 = 162, PPC_V12 = 163, PPC_V13 = 164, PPC_V14 = 165, PPC_V15 = 166, PPC_V16 = 167, PPC_V17 = 168, PPC_V18 = 169, PPC_V19 = 170, PPC_V20 = 171, PPC_V21 = 172, PPC_V22 = 173, PPC_V23 = 174, PPC_V24 = 175, PPC_V25 = 176, PPC_V26 = 177, PPC_V27 = 178, PPC_V28 = 179, PPC_V29 = 180, PPC_V30 = 181, PPC_V31 = 182, PPC_VF0 = 183, PPC_VF1 = 184, PPC_VF2 = 185, PPC_VF3 = 186, PPC_VF4 = 187, PPC_VF5 = 188, PPC_VF6 = 189, PPC_VF7 = 190, PPC_VF8 = 191, PPC_VF9 = 192, PPC_VF10 = 193, PPC_VF11 = 194, PPC_VF12 = 195, PPC_VF13 = 196, PPC_VF14 = 197, PPC_VF15 = 198, PPC_VF16 = 199, PPC_VF17 = 200, PPC_VF18 = 201, PPC_VF19 = 202, PPC_VF20 = 203, PPC_VF21 = 204, PPC_VF22 = 205, PPC_VF23 = 206, PPC_VF24 = 207, PPC_VF25 = 208, PPC_VF26 = 209, PPC_VF27 = 210, PPC_VF28 = 211, PPC_VF29 = 212, PPC_VF30 = 213, PPC_VF31 = 214, PPC_VSL0 = 215, PPC_VSL1 = 216, PPC_VSL2 = 217, PPC_VSL3 = 218, PPC_VSL4 = 219, PPC_VSL5 = 220, PPC_VSL6 = 221, PPC_VSL7 = 222, PPC_VSL8 = 223, PPC_VSL9 = 224, PPC_VSL10 = 225, PPC_VSL11 = 226, PPC_VSL12 = 227, PPC_VSL13 = 228, PPC_VSL14 = 229, PPC_VSL15 = 230, PPC_VSL16 = 231, PPC_VSL17 = 232, PPC_VSL18 = 233, PPC_VSL19 = 234, PPC_VSL20 = 235, PPC_VSL21 = 236, PPC_VSL22 = 237, PPC_VSL23 = 238, PPC_VSL24 = 239, PPC_VSL25 = 240, PPC_VSL26 = 241, PPC_VSL27 = 242, PPC_VSL28 = 243, PPC_VSL29 = 244, PPC_VSL30 = 245, PPC_VSL31 = 246, PPC_VSX32 = 247, PPC_VSX33 = 248, PPC_VSX34 = 249, PPC_VSX35 = 250, PPC_VSX36 = 251, PPC_VSX37 = 252, PPC_VSX38 = 253, PPC_VSX39 = 254, PPC_VSX40 = 255, PPC_VSX41 = 256, PPC_VSX42 = 257, PPC_VSX43 = 258, PPC_VSX44 = 259, PPC_VSX45 = 260, PPC_VSX46 = 261, PPC_VSX47 = 262, PPC_VSX48 = 263, PPC_VSX49 = 264, PPC_VSX50 = 265, PPC_VSX51 = 266, PPC_VSX52 = 267, PPC_VSX53 = 268, PPC_VSX54 = 269, PPC_VSX55 = 270, PPC_VSX56 = 271, PPC_VSX57 = 272, PPC_VSX58 = 273, PPC_VSX59 = 274, PPC_VSX60 = 275, PPC_VSX61 = 276, PPC_VSX62 = 277, PPC_VSX63 = 278, PPC_X0 = 279, PPC_X1 = 280, PPC_X2 = 281, PPC_X3 = 282, PPC_X4 = 283, PPC_X5 = 284, PPC_X6 = 285, PPC_X7 = 286, PPC_X8 = 287, PPC_X9 = 288, PPC_X10 = 289, PPC_X11 = 290, PPC_X12 = 291, PPC_X13 = 292, PPC_X14 = 293, PPC_X15 = 294, PPC_X16 = 295, PPC_X17 = 296, PPC_X18 = 297, PPC_X19 = 298, PPC_X20 = 299, PPC_X21 = 300, PPC_X22 = 301, PPC_X23 = 302, PPC_X24 = 303, PPC_X25 = 304, PPC_X26 = 305, PPC_X27 = 306, PPC_X28 = 307, PPC_X29 = 308, PPC_X30 = 309, PPC_X31 = 310, PPC_ZERO8 = 311, PPC_CR0EQ = 312, PPC_CR1EQ = 313, PPC_CR2EQ = 314, PPC_CR3EQ = 315, PPC_CR4EQ = 316, PPC_CR5EQ = 317, PPC_CR6EQ = 318, PPC_CR7EQ = 319, PPC_CR0GT = 320, PPC_CR1GT = 321, PPC_CR2GT = 322, PPC_CR3GT = 323, PPC_CR4GT = 324, PPC_CR5GT = 325, PPC_CR6GT = 326, PPC_CR7GT = 327, PPC_CR0LT = 328, PPC_CR1LT = 329, PPC_CR2LT = 330, PPC_CR3LT = 331, PPC_CR4LT = 332, PPC_CR5LT = 333, PPC_CR6LT = 334, PPC_CR7LT = 335, PPC_CR0UN = 336, PPC_CR1UN = 337, PPC_CR2UN = 338, PPC_CR3UN = 339, PPC_CR4UN = 340, PPC_CR5UN = 341, PPC_CR6UN = 342, PPC_CR7UN = 343, PPC_NUM_TARGET_REGS // 344 }; // Register classes enum { PPC_VSSRCRegClassID = 0, PPC_GPRCRegClassID = 1, PPC_GPRC_NOR0RegClassID = 2, PPC_SPE4RCRegClassID = 3, PPC_GPRC_and_GPRC_NOR0RegClassID = 4, PPC_CRBITRCRegClassID = 5, PPC_F4RCRegClassID = 6, PPC_CRRCRegClassID = 7, PPC_CARRYRCRegClassID = 8, PPC_CRRC0RegClassID = 9, PPC_CTRRCRegClassID = 10, PPC_VRSAVERCRegClassID = 11, PPC_SPILLTOVSRRCRegClassID = 12, PPC_VSFRCRegClassID = 13, PPC_G8RCRegClassID = 14, PPC_G8RC_NOX0RegClassID = 15, PPC_SPILLTOVSRRC_and_VSFRCRegClassID = 16, PPC_G8RC_and_G8RC_NOX0RegClassID = 17, PPC_F8RCRegClassID = 18, PPC_SPERCRegClassID = 19, PPC_VFRCRegClassID = 20, PPC_SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 21, PPC_SPILLTOVSRRC_and_VFRCRegClassID = 22, PPC_SPILLTOVSRRC_and_F4RCRegClassID = 23, PPC_CTRRC8RegClassID = 24, PPC_VSRCRegClassID = 25, PPC_VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 26, PPC_QSRCRegClassID = 27, PPC_VRRCRegClassID = 28, PPC_VSLRCRegClassID = 29, PPC_VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 30, PPC_QSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 31, PPC_VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 32, PPC_QBRCRegClassID = 33, PPC_QFRCRegClassID = 34, PPC_QBRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 35, }; #endif // GET_REGINFO_ENUM #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg PPCRegDiffLists[] = { /* 0 */ 0, 0, /* 2 */ 65497, 1, 1, 1, 0, /* 7 */ 3, 0, /* 9 */ 10, 0, /* 11 */ 21, 0, /* 13 */ 316, 65528, 65528, 24, 0, /* 18 */ 32, 0, /* 20 */ 49, 0, /* 22 */ 74, 0, /* 24 */ 32, 160, 0, /* 27 */ 34, 160, 0, /* 30 */ 301, 0, /* 32 */ 64204, 0, /* 34 */ 64233, 0, /* 36 */ 64266, 0, /* 38 */ 64299, 0, /* 40 */ 64611, 0, /* 42 */ 65212, 0, /* 44 */ 65220, 0, /* 46 */ 65228, 0, /* 48 */ 65235, 0, /* 50 */ 65236, 0, /* 52 */ 65332, 0, /* 54 */ 65342, 0, /* 56 */ 65344, 0, /* 58 */ 65363, 0, /* 60 */ 65428, 0, /* 62 */ 65460, 0, /* 64 */ 65474, 0, /* 66 */ 65487, 0, /* 68 */ 65492, 0, /* 70 */ 65502, 0, /* 72 */ 65504, 0, /* 74 */ 65523, 0, /* 76 */ 65524, 0, /* 78 */ 65526, 0, /* 80 */ 65535, 0, }; static const uint16_t PPCSubRegIdxLists[] = { /* 0 */ 1, 0, /* 2 */ 2, 0, /* 4 */ 5, 4, 3, 6, 0, }; static const MCRegisterDesc PPCRegDesc[] = { { 4, 0, 0, 0, 0, 0 }, { 1237, 1, 9, 1, 1281, 0 }, { 1406, 1, 1, 1, 1281, 0 }, { 1306, 1, 1, 1, 1281, 0 }, { 1240, 1, 20, 1, 1281, 0 }, { 1303, 1, 1, 1, 1281, 0 }, { 1181, 1, 1, 1, 1281, 0 }, { 1291, 1, 1, 1, 1281, 0 }, { 1174, 1, 1, 1, 1281, 0 }, { 1299, 1, 1, 1, 1031, 0 }, { 1232, 1, 30, 1, 1031, 0 }, { 1041, 78, 1, 0, 0, 2 }, { 127, 13, 1, 4, 36, 6 }, { 267, 13, 1, 4, 36, 6 }, { 381, 13, 1, 4, 36, 6 }, { 495, 13, 1, 4, 36, 6 }, { 603, 13, 1, 4, 36, 6 }, { 711, 13, 1, 4, 36, 6 }, { 819, 13, 1, 4, 36, 6 }, { 927, 13, 1, 4, 36, 6 }, { 1053, 1, 1, 1, 177, 0 }, { 115, 1, 27, 1, 177, 0 }, { 255, 1, 27, 1, 177, 0 }, { 369, 1, 27, 1, 177, 0 }, { 483, 1, 27, 1, 177, 0 }, { 591, 1, 27, 1, 177, 0 }, { 699, 1, 27, 1, 177, 0 }, { 807, 1, 27, 1, 177, 0 }, { 915, 1, 27, 1, 177, 0 }, { 1023, 1, 27, 1, 177, 0 }, { 1150, 1, 27, 1, 177, 0 }, { 1, 1, 27, 1, 177, 0 }, { 141, 1, 27, 1, 177, 0 }, { 281, 1, 27, 1, 177, 0 }, { 395, 1, 27, 1, 177, 0 }, { 509, 1, 27, 1, 177, 0 }, { 617, 1, 27, 1, 177, 0 }, { 725, 1, 27, 1, 177, 0 }, { 833, 1, 27, 1, 177, 0 }, { 941, 1, 27, 1, 177, 0 }, { 1068, 1, 27, 1, 177, 0 }, { 33, 1, 27, 1, 177, 0 }, { 173, 1, 27, 1, 177, 0 }, { 313, 1, 27, 1, 177, 0 }, { 427, 1, 27, 1, 177, 0 }, { 541, 1, 27, 1, 177, 0 }, { 649, 1, 27, 1, 177, 0 }, { 757, 1, 27, 1, 177, 0 }, { 865, 1, 27, 1, 177, 0 }, { 973, 1, 27, 1, 177, 0 }, { 1100, 1, 27, 1, 177, 0 }, { 65, 1, 27, 1, 177, 0 }, { 205, 1, 27, 1, 177, 0 }, { 1045, 66, 1, 0, 112, 2 }, { 1049, 1, 1, 1, 352, 0 }, { 114, 70, 1, 2, 1185, 4 }, { 254, 70, 1, 2, 1185, 4 }, { 368, 70, 1, 2, 1185, 4 }, { 482, 70, 1, 2, 1185, 4 }, { 590, 70, 1, 2, 1185, 4 }, { 698, 70, 1, 2, 1185, 4 }, { 806, 70, 1, 2, 1185, 4 }, { 914, 70, 1, 2, 1185, 4 }, { 1022, 70, 1, 2, 1185, 4 }, { 1149, 70, 1, 2, 1185, 4 }, { 0, 70, 1, 2, 1185, 4 }, { 140, 70, 1, 2, 1185, 4 }, { 280, 70, 1, 2, 1185, 4 }, { 394, 70, 1, 2, 1185, 4 }, { 508, 70, 1, 2, 1185, 4 }, { 616, 70, 1, 2, 1185, 4 }, { 724, 70, 1, 2, 1185, 4 }, { 832, 70, 1, 2, 1185, 4 }, { 940, 70, 1, 2, 1185, 4 }, { 1067, 70, 1, 2, 1185, 4 }, { 32, 70, 1, 2, 1185, 4 }, { 172, 70, 1, 2, 1185, 4 }, { 312, 70, 1, 2, 1185, 4 }, { 426, 70, 1, 2, 1185, 4 }, { 540, 70, 1, 2, 1185, 4 }, { 648, 70, 1, 2, 1185, 4 }, { 756, 70, 1, 2, 1185, 4 }, { 864, 70, 1, 2, 1185, 4 }, { 972, 70, 1, 2, 1185, 4 }, { 1099, 70, 1, 2, 1185, 4 }, { 64, 70, 1, 2, 1185, 4 }, { 204, 70, 1, 2, 1185, 4 }, { 128, 1, 24, 1, 1217, 0 }, { 268, 1, 24, 1, 1217, 0 }, { 382, 1, 24, 1, 1217, 0 }, { 496, 1, 24, 1, 1217, 0 }, { 604, 1, 24, 1, 1217, 0 }, { 712, 1, 24, 1, 1217, 0 }, { 820, 1, 24, 1, 1217, 0 }, { 928, 1, 24, 1, 1217, 0 }, { 1050, 1, 24, 1, 1217, 0 }, { 1162, 1, 24, 1, 1217, 0 }, { 16, 1, 24, 1, 1217, 0 }, { 156, 1, 24, 1, 1217, 0 }, { 296, 1, 24, 1, 1217, 0 }, { 410, 1, 24, 1, 1217, 0 }, { 524, 1, 24, 1, 1217, 0 }, { 632, 1, 24, 1, 1217, 0 }, { 740, 1, 24, 1, 1217, 0 }, { 848, 1, 24, 1, 1217, 0 }, { 956, 1, 24, 1, 1217, 0 }, { 1083, 1, 24, 1, 1217, 0 }, { 48, 1, 24, 1, 1217, 0 }, { 188, 1, 24, 1, 1217, 0 }, { 328, 1, 24, 1, 1217, 0 }, { 442, 1, 24, 1, 1217, 0 }, { 556, 1, 24, 1, 1217, 0 }, { 664, 1, 24, 1, 1217, 0 }, { 772, 1, 24, 1, 1217, 0 }, { 880, 1, 24, 1, 1217, 0 }, { 988, 1, 24, 1, 1217, 0 }, { 1115, 1, 24, 1, 1217, 0 }, { 80, 1, 24, 1, 1217, 0 }, { 220, 1, 24, 1, 1217, 0 }, { 131, 72, 1, 0, 1089, 2 }, { 271, 72, 1, 0, 1089, 2 }, { 385, 72, 1, 0, 1089, 2 }, { 499, 72, 1, 0, 1089, 2 }, { 607, 72, 1, 0, 1089, 2 }, { 715, 72, 1, 0, 1089, 2 }, { 823, 72, 1, 0, 1089, 2 }, { 931, 72, 1, 0, 1089, 2 }, { 1058, 72, 1, 0, 1089, 2 }, { 1165, 72, 1, 0, 1089, 2 }, { 20, 72, 1, 0, 1089, 2 }, { 160, 72, 1, 0, 1089, 2 }, { 300, 72, 1, 0, 1089, 2 }, { 414, 72, 1, 0, 1089, 2 }, { 528, 72, 1, 0, 1089, 2 }, { 636, 72, 1, 0, 1089, 2 }, { 744, 72, 1, 0, 1089, 2 }, { 852, 72, 1, 0, 1089, 2 }, { 960, 72, 1, 0, 1089, 2 }, { 1087, 72, 1, 0, 1089, 2 }, { 52, 72, 1, 0, 1089, 2 }, { 192, 72, 1, 0, 1089, 2 }, { 332, 72, 1, 0, 1089, 2 }, { 446, 72, 1, 0, 1089, 2 }, { 560, 72, 1, 0, 1089, 2 }, { 668, 72, 1, 0, 1089, 2 }, { 776, 72, 1, 0, 1089, 2 }, { 884, 72, 1, 0, 1089, 2 }, { 992, 72, 1, 0, 1089, 2 }, { 1119, 72, 1, 0, 1089, 2 }, { 84, 72, 1, 0, 1089, 2 }, { 224, 72, 1, 0, 1089, 2 }, { 134, 18, 1, 2, 1089, 4 }, { 274, 18, 1, 2, 1089, 4 }, { 388, 18, 1, 2, 1089, 4 }, { 502, 18, 1, 2, 1089, 4 }, { 610, 18, 1, 2, 1089, 4 }, { 718, 18, 1, 2, 1089, 4 }, { 826, 18, 1, 2, 1089, 4 }, { 934, 18, 1, 2, 1089, 4 }, { 1061, 18, 1, 2, 1089, 4 }, { 1168, 18, 1, 2, 1089, 4 }, { 24, 18, 1, 2, 1089, 4 }, { 164, 18, 1, 2, 1089, 4 }, { 304, 18, 1, 2, 1089, 4 }, { 418, 18, 1, 2, 1089, 4 }, { 532, 18, 1, 2, 1089, 4 }, { 640, 18, 1, 2, 1089, 4 }, { 748, 18, 1, 2, 1089, 4 }, { 856, 18, 1, 2, 1089, 4 }, { 964, 18, 1, 2, 1089, 4 }, { 1091, 18, 1, 2, 1089, 4 }, { 56, 18, 1, 2, 1089, 4 }, { 196, 18, 1, 2, 1089, 4 }, { 336, 18, 1, 2, 1089, 4 }, { 450, 18, 1, 2, 1089, 4 }, { 564, 18, 1, 2, 1089, 4 }, { 672, 18, 1, 2, 1089, 4 }, { 780, 18, 1, 2, 1089, 4 }, { 888, 18, 1, 2, 1089, 4 }, { 996, 18, 1, 2, 1089, 4 }, { 1123, 18, 1, 2, 1089, 4 }, { 88, 18, 1, 2, 1089, 4 }, { 228, 18, 1, 2, 1089, 4 }, { 118, 1, 72, 1, 993, 0 }, { 258, 1, 72, 1, 993, 0 }, { 372, 1, 72, 1, 993, 0 }, { 486, 1, 72, 1, 993, 0 }, { 594, 1, 72, 1, 993, 0 }, { 702, 1, 72, 1, 993, 0 }, { 810, 1, 72, 1, 993, 0 }, { 918, 1, 72, 1, 993, 0 }, { 1026, 1, 72, 1, 993, 0 }, { 1153, 1, 72, 1, 993, 0 }, { 5, 1, 72, 1, 993, 0 }, { 145, 1, 72, 1, 993, 0 }, { 285, 1, 72, 1, 993, 0 }, { 399, 1, 72, 1, 993, 0 }, { 513, 1, 72, 1, 993, 0 }, { 621, 1, 72, 1, 993, 0 }, { 729, 1, 72, 1, 993, 0 }, { 837, 1, 72, 1, 993, 0 }, { 945, 1, 72, 1, 993, 0 }, { 1072, 1, 72, 1, 993, 0 }, { 37, 1, 72, 1, 993, 0 }, { 177, 1, 72, 1, 993, 0 }, { 317, 1, 72, 1, 993, 0 }, { 431, 1, 72, 1, 993, 0 }, { 545, 1, 72, 1, 993, 0 }, { 653, 1, 72, 1, 993, 0 }, { 761, 1, 72, 1, 993, 0 }, { 869, 1, 72, 1, 993, 0 }, { 977, 1, 72, 1, 993, 0 }, { 1104, 1, 72, 1, 993, 0 }, { 69, 1, 72, 1, 993, 0 }, { 209, 1, 72, 1, 993, 0 }, { 122, 54, 1, 2, 929, 4 }, { 262, 54, 1, 2, 929, 4 }, { 376, 54, 1, 2, 929, 4 }, { 490, 54, 1, 2, 929, 4 }, { 598, 54, 1, 2, 929, 4 }, { 706, 54, 1, 2, 929, 4 }, { 814, 54, 1, 2, 929, 4 }, { 922, 54, 1, 2, 929, 4 }, { 1030, 54, 1, 2, 929, 4 }, { 1157, 54, 1, 2, 929, 4 }, { 10, 54, 1, 2, 929, 4 }, { 150, 54, 1, 2, 929, 4 }, { 290, 54, 1, 2, 929, 4 }, { 404, 54, 1, 2, 929, 4 }, { 518, 54, 1, 2, 929, 4 }, { 626, 54, 1, 2, 929, 4 }, { 734, 54, 1, 2, 929, 4 }, { 842, 54, 1, 2, 929, 4 }, { 950, 54, 1, 2, 929, 4 }, { 1077, 54, 1, 2, 929, 4 }, { 42, 54, 1, 2, 929, 4 }, { 182, 54, 1, 2, 929, 4 }, { 322, 54, 1, 2, 929, 4 }, { 436, 54, 1, 2, 929, 4 }, { 550, 54, 1, 2, 929, 4 }, { 658, 54, 1, 2, 929, 4 }, { 766, 54, 1, 2, 929, 4 }, { 874, 54, 1, 2, 929, 4 }, { 982, 54, 1, 2, 929, 4 }, { 1109, 54, 1, 2, 929, 4 }, { 74, 54, 1, 2, 929, 4 }, { 214, 54, 1, 2, 929, 4 }, { 344, 1, 1, 1, 961, 0 }, { 458, 1, 1, 1, 961, 0 }, { 572, 1, 1, 1, 961, 0 }, { 680, 1, 1, 1, 961, 0 }, { 788, 1, 1, 1, 961, 0 }, { 896, 1, 1, 1, 961, 0 }, { 1004, 1, 1, 1, 961, 0 }, { 1131, 1, 1, 1, 961, 0 }, { 96, 1, 1, 1, 961, 0 }, { 236, 1, 1, 1, 961, 0 }, { 350, 1, 1, 1, 961, 0 }, { 464, 1, 1, 1, 961, 0 }, { 578, 1, 1, 1, 961, 0 }, { 686, 1, 1, 1, 961, 0 }, { 794, 1, 1, 1, 961, 0 }, { 902, 1, 1, 1, 961, 0 }, { 1010, 1, 1, 1, 961, 0 }, { 1137, 1, 1, 1, 961, 0 }, { 102, 1, 1, 1, 961, 0 }, { 242, 1, 1, 1, 961, 0 }, { 356, 1, 1, 1, 961, 0 }, { 470, 1, 1, 1, 961, 0 }, { 584, 1, 1, 1, 961, 0 }, { 692, 1, 1, 1, 961, 0 }, { 800, 1, 1, 1, 961, 0 }, { 908, 1, 1, 1, 961, 0 }, { 1016, 1, 1, 1, 961, 0 }, { 1143, 1, 1, 1, 961, 0 }, { 108, 1, 1, 1, 961, 0 }, { 248, 1, 1, 1, 961, 0 }, { 362, 1, 1, 1, 961, 0 }, { 476, 1, 1, 1, 961, 0 }, { 137, 56, 1, 0, 833, 2 }, { 277, 56, 1, 0, 833, 2 }, { 391, 56, 1, 0, 833, 2 }, { 505, 56, 1, 0, 833, 2 }, { 613, 56, 1, 0, 833, 2 }, { 721, 56, 1, 0, 833, 2 }, { 829, 56, 1, 0, 833, 2 }, { 937, 56, 1, 0, 833, 2 }, { 1064, 56, 1, 0, 833, 2 }, { 1171, 56, 1, 0, 833, 2 }, { 28, 56, 1, 0, 833, 2 }, { 168, 56, 1, 0, 833, 2 }, { 308, 56, 1, 0, 833, 2 }, { 422, 56, 1, 0, 833, 2 }, { 536, 56, 1, 0, 833, 2 }, { 644, 56, 1, 0, 833, 2 }, { 752, 56, 1, 0, 833, 2 }, { 860, 56, 1, 0, 833, 2 }, { 968, 56, 1, 0, 833, 2 }, { 1095, 56, 1, 0, 833, 2 }, { 60, 56, 1, 0, 833, 2 }, { 200, 56, 1, 0, 833, 2 }, { 340, 56, 1, 0, 833, 2 }, { 454, 56, 1, 0, 833, 2 }, { 568, 56, 1, 0, 833, 2 }, { 676, 56, 1, 0, 833, 2 }, { 784, 56, 1, 0, 833, 2 }, { 892, 56, 1, 0, 833, 2 }, { 1000, 56, 1, 0, 833, 2 }, { 1127, 56, 1, 0, 833, 2 }, { 92, 56, 1, 0, 833, 2 }, { 232, 56, 1, 0, 833, 2 }, { 1035, 48, 1, 0, 643, 2 }, { 1243, 1, 50, 1, 643, 0 }, { 1249, 1, 50, 1, 612, 0 }, { 1255, 1, 50, 1, 612, 0 }, { 1261, 1, 50, 1, 612, 0 }, { 1267, 1, 50, 1, 612, 0 }, { 1273, 1, 50, 1, 612, 0 }, { 1279, 1, 50, 1, 612, 0 }, { 1285, 1, 50, 1, 612, 0 }, { 1310, 1, 46, 1, 580, 0 }, { 1316, 1, 46, 1, 580, 0 }, { 1322, 1, 46, 1, 580, 0 }, { 1328, 1, 46, 1, 580, 0 }, { 1334, 1, 46, 1, 580, 0 }, { 1340, 1, 46, 1, 580, 0 }, { 1346, 1, 46, 1, 580, 0 }, { 1352, 1, 46, 1, 580, 0 }, { 1358, 1, 44, 1, 548, 0 }, { 1364, 1, 44, 1, 548, 0 }, { 1370, 1, 44, 1, 548, 0 }, { 1376, 1, 44, 1, 548, 0 }, { 1382, 1, 44, 1, 548, 0 }, { 1388, 1, 44, 1, 548, 0 }, { 1394, 1, 44, 1, 548, 0 }, { 1400, 1, 44, 1, 548, 0 }, { 1184, 1, 42, 1, 516, 0 }, { 1190, 1, 42, 1, 516, 0 }, { 1196, 1, 42, 1, 516, 0 }, { 1202, 1, 42, 1, 516, 0 }, { 1208, 1, 42, 1, 516, 0 }, { 1214, 1, 42, 1, 516, 0 }, { 1220, 1, 42, 1, 516, 0 }, { 1226, 1, 42, 1, 516, 0 }, }; // VSSRC Register Class... static const MCPhysReg VSSRC[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, }; // VSSRC Bit set. static const uint8_t VSSRCBits[] = { 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // GPRC Register Class... static const MCPhysReg GPRC[] = { PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP, }; // GPRC Bit set. static const uint8_t GPRCBits[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // GPRC_NOR0 Register Class... static const MCPhysReg GPRC_NOR0[] = { PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO, }; // GPRC_NOR0 Bit set. static const uint8_t GPRC_NOR0Bits[] = { 0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, }; // SPE4RC Register Class... static const MCPhysReg SPE4RC[] = { PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP, }; // SPE4RC Bit set. static const uint8_t SPE4RCBits[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // GPRC_and_GPRC_NOR0 Register Class... static const MCPhysReg GPRC_and_GPRC_NOR0[] = { PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, }; // GPRC_and_GPRC_NOR0 Bit set. static const uint8_t GPRC_and_GPRC_NOR0Bits[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, }; // CRBITRC Register Class... static const MCPhysReg CRBITRC[] = { PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, }; // CRBITRC Bit set. static const uint8_t CRBITRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, }; // F4RC Register Class... static const MCPhysReg F4RC[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, }; // F4RC Bit set. static const uint8_t F4RCBits[] = { 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // CRRC Register Class... static const MCPhysReg CRRC[] = { PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4, }; // CRRC Bit set. static const uint8_t CRRCBits[] = { 0x00, 0xf0, 0x0f, }; // CARRYRC Register Class... static const MCPhysReg CARRYRC[] = { PPC_CARRY, PPC_XER, }; // CARRYRC Bit set. static const uint8_t CARRYRCBits[] = { 0x04, 0x02, }; // CRRC0 Register Class... static const MCPhysReg CRRC0[] = { PPC_CR0, }; // CRRC0 Bit set. static const uint8_t CRRC0Bits[] = { 0x00, 0x10, }; // CTRRC Register Class... static const MCPhysReg CTRRC[] = { PPC_CTR, }; // CTRRC Bit set. static const uint8_t CTRRCBits[] = { 0x08, }; // VRSAVERC Register Class... static const MCPhysReg VRSAVERC[] = { PPC_VRSAVE, }; // VRSAVERC Bit set. static const uint8_t VRSAVERCBits[] = { 0x00, 0x01, }; // SPILLTOVSRRC Register Class... static const MCPhysReg SPILLTOVSRRC[] = { PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, }; // SPILLTOVSRRC Bit set. static const uint8_t SPILLTOVSRRCBits[] = { 0x00, 0x08, 0xe0, 0xff, 0x07, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // VSFRC Register Class... static const MCPhysReg VSFRC[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, }; // VSFRC Bit set. static const uint8_t VSFRCBits[] = { 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // G8RC Register Class... static const MCPhysReg G8RC[] = { PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, }; // G8RC Bit set. static const uint8_t G8RCBits[] = { 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // G8RC_NOX0 Register Class... static const MCPhysReg G8RC_NOX0[] = { PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8, }; // G8RC_NOX0 Bit set. static const uint8_t G8RC_NOX0Bits[] = { 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, }; // SPILLTOVSRRC_and_VSFRC Register Class... static const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, }; // SPILLTOVSRRC_and_VSFRC Bit set. static const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = { 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, }; // G8RC_and_G8RC_NOX0 Register Class... static const MCPhysReg G8RC_and_G8RC_NOX0[] = { PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, }; // G8RC_and_G8RC_NOX0 Bit set. static const uint8_t G8RC_and_G8RC_NOX0Bits[] = { 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, }; // F8RC Register Class... static const MCPhysReg F8RC[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, }; // F8RC Bit set. static const uint8_t F8RCBits[] = { 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // SPERC Register Class... static const MCPhysReg SPERC[] = { PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S30, PPC_S29, PPC_S28, PPC_S27, PPC_S26, PPC_S25, PPC_S24, PPC_S23, PPC_S22, PPC_S21, PPC_S20, PPC_S19, PPC_S18, PPC_S17, PPC_S16, PPC_S15, PPC_S14, PPC_S13, PPC_S31, PPC_S0, PPC_S1, }; // SPERC Bit set. static const uint8_t SPERCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // VFRC Register Class... static const MCPhysReg VFRC[] = { PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20, }; // VFRC Bit set. static const uint8_t VFRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // SPERC_with_sub_32_in_GPRC_NOR0 Register Class... static const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = { PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S30, PPC_S29, PPC_S28, PPC_S27, PPC_S26, PPC_S25, PPC_S24, PPC_S23, PPC_S22, PPC_S21, PPC_S20, PPC_S19, PPC_S18, PPC_S17, PPC_S16, PPC_S15, PPC_S14, PPC_S13, PPC_S31, PPC_S1, }; // SPERC_with_sub_32_in_GPRC_NOR0 Bit set. static const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, }; // SPILLTOVSRRC_and_VFRC Register Class... static const MCPhysReg SPILLTOVSRRC_and_VFRC[] = { PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, }; // SPILLTOVSRRC_and_VFRC Bit set. static const uint8_t SPILLTOVSRRC_and_VFRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, }; // SPILLTOVSRRC_and_F4RC Register Class... static const MCPhysReg SPILLTOVSRRC_and_F4RC[] = { PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, }; // SPILLTOVSRRC_and_F4RC Bit set. static const uint8_t SPILLTOVSRRC_and_F4RCBits[] = { 0x00, 0x00, 0xe0, 0xff, 0x07, }; // CTRRC8 Register Class... static const MCPhysReg CTRRC8[] = { PPC_CTR8, }; // CTRRC8 Bit set. static const uint8_t CTRRC8Bits[] = { 0x00, 0x00, 0x10, }; // VSRC Register Class... static const MCPhysReg VSRC[] = { PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20, }; // VSRC Bit set. static const uint8_t VSRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class... static const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = { PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, }; // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set. static const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, }; // QSRC Register Class... static const MCPhysReg QSRC[] = { PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14, }; // QSRC Bit set. static const uint8_t QSRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // VRRC Register Class... static const MCPhysReg VRRC[] = { PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20, }; // VRRC Bit set. static const uint8_t VRRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // VSLRC Register Class... static const MCPhysReg VSLRC[] = { PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, }; // VSLRC Bit set. static const uint8_t VSLRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class... static const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = { PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, }; // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set. static const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, }; // QSRC_with_sub_64_in_SPILLTOVSRRC Register Class... static const MCPhysReg QSRC_with_sub_64_in_SPILLTOVSRRC[] = { PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, }; // QSRC_with_sub_64_in_SPILLTOVSRRC Bit set. static const uint8_t QSRC_with_sub_64_in_SPILLTOVSRRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, }; // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class... static const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = { PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, }; // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set. static const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, }; // QBRC Register Class... static const MCPhysReg QBRC[] = { PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14, }; // QBRC Bit set. static const uint8_t QBRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // QFRC Register Class... static const MCPhysReg QFRC[] = { PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14, }; // QFRC Bit set. static const uint8_t QFRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // QBRC_with_sub_64_in_SPILLTOVSRRC Register Class... static const MCPhysReg QBRC_with_sub_64_in_SPILLTOVSRRC[] = { PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, }; // QBRC_with_sub_64_in_SPILLTOVSRRC Bit set. static const uint8_t QBRC_with_sub_64_in_SPILLTOVSRRCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, }; static const MCRegisterClass PPCMCRegisterClasses[] = { { VSSRC, VSSRCBits, sizeof(VSSRCBits) }, { GPRC, GPRCBits, sizeof(GPRCBits) }, { GPRC_NOR0, GPRC_NOR0Bits, sizeof(GPRC_NOR0Bits) }, { SPE4RC, SPE4RCBits, sizeof(SPE4RCBits) }, { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, sizeof(GPRC_and_GPRC_NOR0Bits) }, { CRBITRC, CRBITRCBits, sizeof(CRBITRCBits) }, { F4RC, F4RCBits, sizeof(F4RCBits) }, { CRRC, CRRCBits, sizeof(CRRCBits) }, { CARRYRC, CARRYRCBits, sizeof(CARRYRCBits) }, { CRRC0, CRRC0Bits, sizeof(CRRC0Bits) }, { CTRRC, CTRRCBits, sizeof(CTRRCBits) }, { VRSAVERC, VRSAVERCBits, sizeof(VRSAVERCBits) }, { SPILLTOVSRRC, SPILLTOVSRRCBits, sizeof(SPILLTOVSRRCBits) }, { VSFRC, VSFRCBits, sizeof(VSFRCBits) }, { G8RC, G8RCBits, sizeof(G8RCBits) }, { G8RC_NOX0, G8RC_NOX0Bits, sizeof(G8RC_NOX0Bits) }, { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, sizeof(SPILLTOVSRRC_and_VSFRCBits) }, { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, sizeof(G8RC_and_G8RC_NOX0Bits) }, { F8RC, F8RCBits, sizeof(F8RCBits) }, { SPERC, SPERCBits, sizeof(SPERCBits) }, { VFRC, VFRCBits, sizeof(VFRCBits) }, { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits) }, { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, sizeof(SPILLTOVSRRC_and_VFRCBits) }, { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, sizeof(SPILLTOVSRRC_and_F4RCBits) }, { CTRRC8, CTRRC8Bits, sizeof(CTRRC8Bits) }, { VSRC, VSRCBits, sizeof(VSRCBits) }, { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits) }, { QSRC, QSRCBits, sizeof(QSRCBits) }, { VRRC, VRRCBits, sizeof(VRRCBits) }, { VSLRC, VSLRCBits, sizeof(VSLRCBits) }, { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits) }, { QSRC_with_sub_64_in_SPILLTOVSRRC, QSRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(QSRC_with_sub_64_in_SPILLTOVSRRCBits) }, { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits) }, { QBRC, QBRCBits, sizeof(QBRCBits) }, { QFRC, QFRCBits, sizeof(QFRCBits) }, { QBRC_with_sub_64_in_SPILLTOVSRRC, QBRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(QBRC_with_sub_64_in_SPILLTOVSRRCBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/PowerPC/PPCGenRegisterName.inc000064400000000000000000000233340072674642500225210ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0, /* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0, /* 36 */ '*', '*', 'B', 'A', 'S', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0, /* 53 */ 'f', '1', '0', 0, /* 57 */ 'q', '1', '0', 0, /* 61 */ 'r', '1', '0', 0, /* 65 */ 'v', 's', '1', '0', 0, /* 70 */ 'v', '1', '0', 0, /* 74 */ 'f', '2', '0', 0, /* 78 */ 'q', '2', '0', 0, /* 82 */ 'r', '2', '0', 0, /* 86 */ 'v', 's', '2', '0', 0, /* 91 */ 'v', '2', '0', 0, /* 95 */ 'f', '3', '0', 0, /* 99 */ 'q', '3', '0', 0, /* 103 */ 'r', '3', '0', 0, /* 107 */ 'v', 's', '3', '0', 0, /* 112 */ 'v', '3', '0', 0, /* 116 */ 'v', 's', '4', '0', 0, /* 121 */ 'v', 's', '5', '0', 0, /* 126 */ 'v', 's', '6', '0', 0, /* 131 */ 'f', '0', 0, /* 134 */ 'q', '0', 0, /* 137 */ 'c', 'r', '0', 0, /* 141 */ 'v', 's', '0', 0, /* 145 */ 'v', '0', 0, /* 148 */ 'f', '1', '1', 0, /* 152 */ 'q', '1', '1', 0, /* 156 */ 'r', '1', '1', 0, /* 160 */ 'v', 's', '1', '1', 0, /* 165 */ 'v', '1', '1', 0, /* 169 */ 'f', '2', '1', 0, /* 173 */ 'q', '2', '1', 0, /* 177 */ 'r', '2', '1', 0, /* 181 */ 'v', 's', '2', '1', 0, /* 186 */ 'v', '2', '1', 0, /* 190 */ 'f', '3', '1', 0, /* 194 */ 'q', '3', '1', 0, /* 198 */ 'r', '3', '1', 0, /* 202 */ 'v', 's', '3', '1', 0, /* 207 */ 'v', '3', '1', 0, /* 211 */ 'v', 's', '4', '1', 0, /* 216 */ 'v', 's', '5', '1', 0, /* 221 */ 'v', 's', '6', '1', 0, /* 226 */ 'f', '1', 0, /* 229 */ 'q', '1', 0, /* 232 */ 'c', 'r', '1', 0, /* 236 */ 'v', 's', '1', 0, /* 240 */ 'v', '1', 0, /* 243 */ 'f', '1', '2', 0, /* 247 */ 'q', '1', '2', 0, /* 251 */ 'r', '1', '2', 0, /* 255 */ 'v', 's', '1', '2', 0, /* 260 */ 'v', '1', '2', 0, /* 264 */ 'f', '2', '2', 0, /* 268 */ 'q', '2', '2', 0, /* 272 */ 'r', '2', '2', 0, /* 276 */ 'v', 's', '2', '2', 0, /* 281 */ 'v', '2', '2', 0, /* 285 */ 'v', 's', '3', '2', 0, /* 290 */ 'v', 's', '4', '2', 0, /* 295 */ 'v', 's', '5', '2', 0, /* 300 */ 'v', 's', '6', '2', 0, /* 305 */ 'f', '2', 0, /* 308 */ 'q', '2', 0, /* 311 */ 'c', 'r', '2', 0, /* 315 */ 'v', 's', '2', 0, /* 319 */ 'v', '2', 0, /* 322 */ 'f', '1', '3', 0, /* 326 */ 'q', '1', '3', 0, /* 330 */ 'r', '1', '3', 0, /* 334 */ 'v', 's', '1', '3', 0, /* 339 */ 'v', '1', '3', 0, /* 343 */ 'f', '2', '3', 0, /* 347 */ 'q', '2', '3', 0, /* 351 */ 'r', '2', '3', 0, /* 355 */ 'v', 's', '2', '3', 0, /* 360 */ 'v', '2', '3', 0, /* 364 */ 'v', 's', '3', '3', 0, /* 369 */ 'v', 's', '4', '3', 0, /* 374 */ 'v', 's', '5', '3', 0, /* 379 */ 'v', 's', '6', '3', 0, /* 384 */ 'f', '3', 0, /* 387 */ 'q', '3', 0, /* 390 */ 'c', 'r', '3', 0, /* 394 */ 'v', 's', '3', 0, /* 398 */ 'v', '3', 0, /* 401 */ 'f', '1', '4', 0, /* 405 */ 'q', '1', '4', 0, /* 409 */ 'r', '1', '4', 0, /* 413 */ 'v', 's', '1', '4', 0, /* 418 */ 'v', '1', '4', 0, /* 422 */ 'f', '2', '4', 0, /* 426 */ 'q', '2', '4', 0, /* 430 */ 'r', '2', '4', 0, /* 434 */ 'v', 's', '2', '4', 0, /* 439 */ 'v', '2', '4', 0, /* 443 */ 'v', 's', '3', '4', 0, /* 448 */ 'v', 's', '4', '4', 0, /* 453 */ 'v', 's', '5', '4', 0, /* 458 */ 'f', '4', 0, /* 461 */ 'q', '4', 0, /* 464 */ 'c', 'r', '4', 0, /* 468 */ 'v', 's', '4', 0, /* 472 */ 'v', '4', 0, /* 475 */ 'f', '1', '5', 0, /* 479 */ 'q', '1', '5', 0, /* 483 */ 'r', '1', '5', 0, /* 487 */ 'v', 's', '1', '5', 0, /* 492 */ 'v', '1', '5', 0, /* 496 */ 'f', '2', '5', 0, /* 500 */ 'q', '2', '5', 0, /* 504 */ 'r', '2', '5', 0, /* 508 */ 'v', 's', '2', '5', 0, /* 513 */ 'v', '2', '5', 0, /* 517 */ 'v', 's', '3', '5', 0, /* 522 */ 'v', 's', '4', '5', 0, /* 527 */ 'v', 's', '5', '5', 0, /* 532 */ 'f', '5', 0, /* 535 */ 'q', '5', 0, /* 538 */ 'c', 'r', '5', 0, /* 542 */ 'v', 's', '5', 0, /* 546 */ 'v', '5', 0, /* 549 */ 'f', '1', '6', 0, /* 553 */ 'q', '1', '6', 0, /* 557 */ 'r', '1', '6', 0, /* 561 */ 'v', 's', '1', '6', 0, /* 566 */ 'v', '1', '6', 0, /* 570 */ 'f', '2', '6', 0, /* 574 */ 'q', '2', '6', 0, /* 578 */ 'r', '2', '6', 0, /* 582 */ 'v', 's', '2', '6', 0, /* 587 */ 'v', '2', '6', 0, /* 591 */ 'v', 's', '3', '6', 0, /* 596 */ 'v', 's', '4', '6', 0, /* 601 */ 'v', 's', '5', '6', 0, /* 606 */ 'f', '6', 0, /* 609 */ 'q', '6', 0, /* 612 */ 'c', 'r', '6', 0, /* 616 */ 'v', 's', '6', 0, /* 620 */ 'v', '6', 0, /* 623 */ 'f', '1', '7', 0, /* 627 */ 'q', '1', '7', 0, /* 631 */ 'r', '1', '7', 0, /* 635 */ 'v', 's', '1', '7', 0, /* 640 */ 'v', '1', '7', 0, /* 644 */ 'f', '2', '7', 0, /* 648 */ 'q', '2', '7', 0, /* 652 */ 'r', '2', '7', 0, /* 656 */ 'v', 's', '2', '7', 0, /* 661 */ 'v', '2', '7', 0, /* 665 */ 'v', 's', '3', '7', 0, /* 670 */ 'v', 's', '4', '7', 0, /* 675 */ 'v', 's', '5', '7', 0, /* 680 */ 'f', '7', 0, /* 683 */ 'q', '7', 0, /* 686 */ 'c', 'r', '7', 0, /* 690 */ 'v', 's', '7', 0, /* 694 */ 'v', '7', 0, /* 697 */ 'f', '1', '8', 0, /* 701 */ 'q', '1', '8', 0, /* 705 */ 'r', '1', '8', 0, /* 709 */ 'v', 's', '1', '8', 0, /* 714 */ 'v', '1', '8', 0, /* 718 */ 'f', '2', '8', 0, /* 722 */ 'q', '2', '8', 0, /* 726 */ 'r', '2', '8', 0, /* 730 */ 'v', 's', '2', '8', 0, /* 735 */ 'v', '2', '8', 0, /* 739 */ 'v', 's', '3', '8', 0, /* 744 */ 'v', 's', '4', '8', 0, /* 749 */ 'v', 's', '5', '8', 0, /* 754 */ 'f', '8', 0, /* 757 */ 'q', '8', 0, /* 760 */ 'r', '8', 0, /* 763 */ 'v', 's', '8', 0, /* 767 */ 'v', '8', 0, /* 770 */ 'f', '1', '9', 0, /* 774 */ 'q', '1', '9', 0, /* 778 */ 'r', '1', '9', 0, /* 782 */ 'v', 's', '1', '9', 0, /* 787 */ 'v', '1', '9', 0, /* 791 */ 'f', '2', '9', 0, /* 795 */ 'q', '2', '9', 0, /* 799 */ 'r', '2', '9', 0, /* 803 */ 'v', 's', '2', '9', 0, /* 808 */ 'v', '2', '9', 0, /* 812 */ 'v', 's', '3', '9', 0, /* 817 */ 'v', 's', '4', '9', 0, /* 822 */ 'v', 's', '5', '9', 0, /* 827 */ 'f', '9', 0, /* 830 */ 'q', '9', 0, /* 833 */ 'r', '9', 0, /* 836 */ 'v', 's', '9', 0, /* 840 */ 'v', '9', 0, /* 843 */ 'v', 'r', 's', 'a', 'v', 'e', 0, /* 850 */ 'c', 'r', '0', 'u', 'n', 0, /* 856 */ 'c', 'r', '1', 'u', 'n', 0, /* 862 */ 'c', 'r', '2', 'u', 'n', 0, /* 868 */ 'c', 'r', '3', 'u', 'n', 0, /* 874 */ 'c', 'r', '4', 'u', 'n', 0, /* 880 */ 'c', 'r', '5', 'u', 'n', 0, /* 886 */ 'c', 'r', '6', 'u', 'n', 0, /* 892 */ 'c', 'r', '7', 'u', 'n', 0, /* 898 */ 'c', 'r', '0', 'e', 'q', 0, /* 904 */ 'c', 'r', '1', 'e', 'q', 0, /* 910 */ 'c', 'r', '2', 'e', 'q', 0, /* 916 */ 'c', 'r', '3', 'e', 'q', 0, /* 922 */ 'c', 'r', '4', 'e', 'q', 0, /* 928 */ 'c', 'r', '5', 'e', 'q', 0, /* 934 */ 'c', 'r', '6', 'e', 'q', 0, /* 940 */ 'c', 'r', '7', 'e', 'q', 0, /* 946 */ 's', 'p', 'e', 'f', 's', 'c', 'r', 0, /* 954 */ 'x', 'e', 'r', 0, /* 958 */ 'l', 'r', 0, /* 961 */ 'c', 't', 'r', 0, /* 965 */ 'c', 'r', '0', 'g', 't', 0, /* 971 */ 'c', 'r', '1', 'g', 't', 0, /* 977 */ 'c', 'r', '2', 'g', 't', 0, /* 983 */ 'c', 'r', '3', 'g', 't', 0, /* 989 */ 'c', 'r', '4', 'g', 't', 0, /* 995 */ 'c', 'r', '5', 'g', 't', 0, /* 1001 */ 'c', 'r', '6', 'g', 't', 0, /* 1007 */ 'c', 'r', '7', 'g', 't', 0, /* 1013 */ 'c', 'r', '0', 'l', 't', 0, /* 1019 */ 'c', 'r', '1', 'l', 't', 0, /* 1025 */ 'c', 'r', '2', 'l', 't', 0, /* 1031 */ 'c', 'r', '3', 'l', 't', 0, /* 1037 */ 'c', 'r', '4', 'l', 't', 0, /* 1043 */ 'c', 'r', '5', 'l', 't', 0, /* 1049 */ 'c', 'r', '6', 'l', 't', 0, /* 1055 */ 'c', 'r', '7', 'l', 't', 0, }; static const uint16_t RegAsmOffset[] = { 36, 954, 961, 18, 958, 0, 946, 843, 954, 55, 36, 137, 232, 311, 390, 464, 538, 612, 686, 961, 131, 226, 305, 384, 458, 532, 606, 680, 754, 827, 53, 148, 243, 322, 401, 475, 549, 623, 697, 770, 74, 169, 264, 343, 422, 496, 570, 644, 718, 791, 95, 190, 18, 958, 134, 229, 308, 387, 461, 535, 609, 683, 757, 830, 57, 152, 247, 326, 405, 479, 553, 627, 701, 774, 78, 173, 268, 347, 426, 500, 574, 648, 722, 795, 99, 194, 138, 233, 312, 391, 465, 539, 613, 687, 760, 833, 61, 156, 251, 330, 409, 483, 557, 631, 705, 778, 82, 177, 272, 351, 430, 504, 578, 652, 726, 799, 103, 198, 138, 233, 312, 391, 465, 539, 613, 687, 760, 833, 61, 156, 251, 330, 409, 483, 557, 631, 705, 778, 82, 177, 272, 351, 430, 504, 578, 652, 726, 799, 103, 198, 145, 240, 319, 398, 472, 546, 620, 694, 767, 840, 70, 165, 260, 339, 418, 492, 566, 640, 714, 787, 91, 186, 281, 360, 439, 513, 587, 661, 735, 808, 112, 207, 145, 240, 319, 398, 472, 546, 620, 694, 767, 840, 70, 165, 260, 339, 418, 492, 566, 640, 714, 787, 91, 186, 281, 360, 439, 513, 587, 661, 735, 808, 112, 207, 141, 236, 315, 394, 468, 542, 616, 690, 763, 836, 65, 160, 255, 334, 413, 487, 561, 635, 709, 782, 86, 181, 276, 355, 434, 508, 582, 656, 730, 803, 107, 202, 285, 364, 443, 517, 591, 665, 739, 812, 116, 211, 290, 369, 448, 522, 596, 670, 744, 817, 121, 216, 295, 374, 453, 527, 601, 675, 749, 822, 126, 221, 300, 379, 138, 233, 312, 391, 465, 539, 613, 687, 760, 833, 61, 156, 251, 330, 409, 483, 557, 631, 705, 778, 82, 177, 272, 351, 430, 504, 578, 652, 726, 799, 103, 198, 55, 898, 904, 910, 916, 922, 928, 934, 940, 965, 971, 977, 983, 989, 995, 1001, 1007, 1013, 1019, 1025, 1031, 1037, 1043, 1049, 1055, 850, 856, 862, 868, 874, 880, 886, 892, }; return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc000064400000000000000000000051220072674642500227030ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ enum { PPC_DeprecatedDST = 0, PPC_Directive32 = 1, PPC_Directive64 = 2, PPC_Directive440 = 3, PPC_Directive601 = 4, PPC_Directive602 = 5, PPC_Directive603 = 6, PPC_Directive604 = 7, PPC_Directive620 = 8, PPC_Directive750 = 9, PPC_Directive970 = 10, PPC_Directive7400 = 11, PPC_DirectiveA2 = 12, PPC_DirectiveE500 = 13, PPC_DirectiveE500mc = 14, PPC_DirectiveE5500 = 15, PPC_DirectivePwr3 = 16, PPC_DirectivePwr4 = 17, PPC_DirectivePwr5 = 18, PPC_DirectivePwr5x = 19, PPC_DirectivePwr6 = 20, PPC_DirectivePwr6x = 21, PPC_DirectivePwr7 = 22, PPC_DirectivePwr8 = 23, PPC_DirectivePwr9 = 24, PPC_Feature64Bit = 25, PPC_Feature64BitRegs = 26, PPC_FeatureAltivec = 27, PPC_FeatureBPERMD = 28, PPC_FeatureBookE = 29, PPC_FeatureCMPB = 30, PPC_FeatureCRBits = 31, PPC_FeatureDirectMove = 32, PPC_FeatureE500 = 33, PPC_FeatureExtDiv = 34, PPC_FeatureFCPSGN = 35, PPC_FeatureFPCVT = 36, PPC_FeatureFPRND = 37, PPC_FeatureFPU = 38, PPC_FeatureFRE = 39, PPC_FeatureFRES = 40, PPC_FeatureFRSQRTE = 41, PPC_FeatureFRSQRTES = 42, PPC_FeatureFSqrt = 43, PPC_FeatureFloat128 = 44, PPC_FeatureFusion = 45, PPC_FeatureHTM = 46, PPC_FeatureHardFloat = 47, PPC_FeatureICBT = 48, PPC_FeatureISA3_0 = 49, PPC_FeatureISEL = 50, PPC_FeatureInvariantFunctionDescriptors = 51, PPC_FeatureLDBRX = 52, PPC_FeatureLFIWAX = 53, PPC_FeatureLongCall = 54, PPC_FeatureMFOCRF = 55, PPC_FeatureMFTB = 56, PPC_FeatureMSYNC = 57, PPC_FeatureP8Altivec = 58, PPC_FeatureP8Crypto = 59, PPC_FeatureP8Vector = 60, PPC_FeatureP9Altivec = 61, PPC_FeatureP9Vector = 62, PPC_FeaturePOPCNTD = 63, PPC_FeaturePPC4xx = 64, PPC_FeaturePPC6xx = 65, PPC_FeaturePartwordAtomic = 66, PPC_FeatureQPX = 67, PPC_FeatureRecipPrec = 68, PPC_FeatureSPE = 69, PPC_FeatureSTFIWX = 70, PPC_FeatureSecurePlt = 71, PPC_FeatureSlowPOPCNTD = 72, PPC_FeatureVSX = 73, }; capstone-sys-0.15.0/capstone/arch/PowerPC/PPCInstPrinter.c000064400000000000000000001003700072674642500214300ustar 00000000000000//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an PPC MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_POWERPC #include #include #include #include "PPCInstPrinter.h" #include "PPCPredicates.h" #include "../../MCInst.h" #include "../../utils.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" #include "PPCMapping.h" #ifndef CAPSTONE_DIET static const char *getRegisterName(unsigned RegNo); #endif static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printInstruction(MCInst *MI, SStream *O); static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O); static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI); static char *printAliasBcc(MCInst *MI, SStream *OS, void *info); static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS); #if 0 static void printRegName(SStream *OS, unsigned RegNo) { char *RegName = getRegisterName(RegNo); if (RegName[0] == 'q' /* QPX */) { // The system toolchain on the BG/Q does not understand QPX register names // in .cfi_* directives, so print the name of the floating-point // subregister instead. RegName[0] = 'f'; } SStream_concat0(OS, RegName); } #endif static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (status) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0; } else { // done, create the next operand slot MI->flat_insn->detail->ppc.op_count++; } } void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { if (((cs_struct *)ud)->detail != CS_OPT_ON) return; // check if this insn has branch hint if (strrchr(insn_asm, '+') != NULL && !strstr(insn_asm, ".+")) { insn->detail->ppc.bh = PPC_BH_PLUS; } else if (strrchr(insn_asm, '-') != NULL) { insn->detail->ppc.bh = PPC_BH_MINUS; } if (strrchr(insn_asm, '.') != NULL) { insn->detail->ppc.update_cr0 = true; } } #define GET_INSTRINFO_ENUM #include "PPCGenInstrInfo.inc" #define GET_REGINFO_ENUM #include "PPCGenRegisterInfo.inc" static void op_addBC(MCInst *MI, unsigned int bc) { if (MI->csh->detail) { MI->flat_insn->detail->ppc.bc = (ppc_bc)bc; } } #define CREQ (0) #define CRGT (1) #define CRLT (2) #define CRUN (3) static int getBICRCond(int bi) { return (bi - PPC_CR0EQ) >> 3; } static int getBICR(int bi) { return ((bi - PPC_CR0EQ) & 7) + PPC_CR0; } static void op_addReg(MCInst *MI, unsigned int reg) { if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; MI->flat_insn->detail->ppc.op_count++; } } static void add_CRxx(MCInst *MI, ppc_reg reg) { if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; MI->flat_insn->detail->ppc.op_count++; } } static char *printAliasBcc(MCInst *MI, SStream *OS, void *info) { #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) SStream ss; const char *opCode; char *tmp, *AsmMnem, *AsmOps, *c; int OpIdx, PrintMethodIdx; int decCtr = false, needComma = false; MCRegisterInfo *MRI = (MCRegisterInfo *)info; SStream_Init(&ss); switch (MCInst_getOpcode(MI)) { default: return NULL; case PPC_gBC: opCode = "b%s"; break; case PPC_gBCA: opCode = "b%sa"; break; case PPC_gBCCTR: opCode = "b%sctr"; break; case PPC_gBCCTRL: opCode = "b%sctrl"; break; case PPC_gBCL: opCode = "b%sl"; break; case PPC_gBCLA: opCode = "b%sla"; break; case PPC_gBCLR: opCode = "b%slr"; break; case PPC_gBCLRL: opCode = "b%slrl"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) { SStream_concat(&ss, opCode, "dnzf"); decCtr = true; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) { SStream_concat(&ss, opCode, "dzf"); decCtr = true; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); switch(cr) { case CREQ: SStream_concat(&ss, opCode, "ne"); break; case CRGT: SStream_concat(&ss, opCode, "le"); break; case CRLT: SStream_concat(&ss, opCode, "ge"); break; case CRUN: SStream_concat(&ss, opCode, "ns"); break; } if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6) SStream_concat0(&ss, "-"); if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7) SStream_concat0(&ss, "+"); decCtr = false; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) { SStream_concat(&ss, opCode, "dnzt"); decCtr = true; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) { SStream_concat(&ss, opCode, "dzt"); decCtr = true; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) { int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); switch(cr) { case CREQ: SStream_concat(&ss, opCode, "eq"); break; case CRGT: SStream_concat(&ss, opCode, "gt"); break; case CRLT: SStream_concat(&ss, opCode, "lt"); break; case CRUN: SStream_concat(&ss, opCode, "so"); break; } if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14) SStream_concat0(&ss, "-"); if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) SStream_concat0(&ss, "+"); decCtr = false; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) { SStream_concat(&ss, opCode, "dnz"); if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24) SStream_concat0(&ss, "-"); if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25) SStream_concat0(&ss, "+"); needComma = false; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) { SStream_concat(&ss, opCode, "dz"); if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26) SStream_concat0(&ss, "-"); if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27) SStream_concat0(&ss, "+"); needComma = false; } if (MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) { int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1))); if (decCtr) { int cd; needComma = true; SStream_concat0(&ss, " "); if (cr > PPC_CR0) { SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0); } cd = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1))); switch(cd) { case CREQ: SStream_concat0(&ss, "eq"); if (cr <= PPC_CR0) add_CRxx(MI, PPC_REG_CR0EQ); op_addBC(MI, PPC_BC_EQ); break; case CRGT: SStream_concat0(&ss, "gt"); if (cr <= PPC_CR0) add_CRxx(MI, PPC_REG_CR0GT); op_addBC(MI, PPC_BC_GT); break; case CRLT: SStream_concat0(&ss, "lt"); if (cr <= PPC_CR0) add_CRxx(MI, PPC_REG_CR0LT); op_addBC(MI, PPC_BC_LT); break; case CRUN: SStream_concat0(&ss, "so"); if (cr <= PPC_CR0) add_CRxx(MI, PPC_REG_CR0UN); op_addBC(MI, PPC_BC_SO); break; } if (cr > PPC_CR0) { if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); MI->flat_insn->detail->ppc.op_count++; } } } else { if (cr > PPC_CR0) { needComma = true; SStream_concat(&ss, " cr%d", cr - PPC_CR0); op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0); } } } if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) { if (needComma) SStream_concat0(&ss, ","); SStream_concat0(&ss, " $\xFF\x03\x01"); } tmp = cs_strdup(ss.buffer); AsmMnem = tmp; for(AsmOps = tmp; *AsmOps; AsmOps++) { if (*AsmOps == ' ' || *AsmOps == '\t') { *AsmOps = '\0'; AsmOps++; break; } } SStream_concat0(OS, AsmMnem); if (*AsmOps) { SStream_concat0(OS, "\t"); for (c = AsmOps; *c; c++) { if (*c == '$') { c += 1; if (*c == (char)0xff) { c += 1; OpIdx = *c - 1; c += 1; PrintMethodIdx = *c - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, *c - 1, OS); } else { SStream_concat1(OS, *c); } } } return tmp; } static bool isBOCTRBranch(unsigned int op) { return ((op >= PPC_BDNZ) && (op <= PPC_BDZp)); } void PPC_printInst(MCInst *MI, SStream *O, void *Info) { char *mnem; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Check for slwi/srwi mnemonics. if (opcode == PPC_RLWINM) { unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4)); bool useSubstituteMnemonic = false; if (SH <= 31 && MB == 0 && ME == (31 - SH)) { SStream_concat0(O, "slwi\t"); MCInst_setOpcodePub(MI, PPC_INS_SLWI); useSubstituteMnemonic = true; } if (SH <= 31 && MB == (32 - SH) && ME == 31) { SStream_concat0(O, "srwi\t"); MCInst_setOpcodePub(MI, PPC_INS_SRWI); useSubstituteMnemonic = true; SH = 32 - SH; } if (useSubstituteMnemonic) { printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); if (SH > HEX_THRESHOLD) SStream_concat(O, ", 0x%x", (unsigned int)SH); else SStream_concat(O, ", %u", (unsigned int)SH); if (MI->csh->detail) { cs_ppc *ppc = &MI->flat_insn->detail->ppc; ppc->operands[ppc->op_count].type = PPC_OP_IMM; ppc->operands[ppc->op_count].imm = SH; ++ppc->op_count; } return; } } if ((opcode == PPC_OR || opcode == PPC_OR8) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) { SStream_concat0(O, "mr\t"); MCInst_setOpcodePub(MI, PPC_INS_MR); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; } if (opcode == PPC_RLDICR || opcode == PPC_RLDICR_32) { unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2)); unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3)); // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH if (63 - SH == ME) { SStream_concat0(O, "sldi\t"); MCInst_setOpcodePub(MI, PPC_INS_SLDI); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); if (SH > HEX_THRESHOLD) SStream_concat(O, ", 0x%x", (unsigned int)SH); else SStream_concat(O, ", %u", (unsigned int)SH); if (MI->csh->detail) { cs_ppc *ppc = &MI->flat_insn->detail->ppc; ppc->operands[ppc->op_count].type = PPC_OP_IMM; ppc->operands[ppc->op_count].imm = SH; ++ppc->op_count; } return; } } // dcbt[st] is printed manually here because: // 1. The assembly syntax is different between embedded and server targets // 2. We must print the short mnemonics for TH == 0 because the // embedded/server syntax default will not be stable across assemblers // The syntax for dcbt is: // dcbt ra, rb, th [server] // dcbt th, ra, rb [embedded] // where th can be omitted when it is 0. dcbtst is the same. if (opcode == PPC_DCBT || opcode == PPC_DCBTST) { unsigned char TH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0)); SStream_concat0(O, "dcbt"); MCInst_setOpcodePub(MI, PPC_INS_DCBT); if (opcode == PPC_DCBTST) { SStream_concat0(O, "st"); MCInst_setOpcodePub(MI, PPC_INS_DCBTST); } if (TH == 16) { SStream_concat0(O, "t"); MCInst_setOpcodePub(MI, PPC_INS_DCBTSTT); } SStream_concat0(O, "\t"); if (MI->csh->mode & CS_MODE_BOOKE && TH != 0 && TH != 16) { if (TH > HEX_THRESHOLD) SStream_concat(O, "0x%x, ", (unsigned int)TH); else SStream_concat(O, "%u, ", (unsigned int)TH); if (MI->csh->detail) { cs_ppc *ppc = &MI->flat_insn->detail->ppc; ppc->operands[ppc->op_count].type = PPC_OP_IMM; ppc->operands[ppc->op_count].imm = TH; ++ppc->op_count; } } printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); if (!(MI->csh->mode & CS_MODE_BOOKE) && TH != 0 && TH != 16) { if (TH > HEX_THRESHOLD) SStream_concat(O, ", 0x%x", (unsigned int)TH); else SStream_concat(O, ", %u", (unsigned int)TH); if (MI->csh->detail) { cs_ppc *ppc = &MI->flat_insn->detail->ppc; ppc->operands[ppc->op_count].type = PPC_OP_IMM; ppc->operands[ppc->op_count].imm = TH; ++ppc->op_count; } } return; } if (opcode == PPC_DCBF) { unsigned char L = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0)); if (!L || L == 1 || L == 3) { SStream_concat0(O, "dcbf"); MCInst_setOpcodePub(MI, PPC_INS_DCBF); if (L == 1 || L == 3) { SStream_concat0(O, "l"); MCInst_setOpcodePub(MI, PPC_INS_DCBFL); } if (L == 3) { SStream_concat0(O, "p"); MCInst_setOpcodePub(MI, PPC_INS_DCBFLP); } SStream_concat0(O, "\t"); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; } } if (opcode == PPC_B || opcode == PPC_BA || opcode == PPC_BL || opcode == PPC_BLA) { int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); bd = SignExtend64(bd, 24); MCOperand_setImm(MCInst_getOperand(MI, 0), bd); } if (opcode == PPC_gBC || opcode == PPC_gBCA || opcode == PPC_gBCL || opcode == PPC_gBCLA) { int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2)); bd = SignExtend64(bd, 14); MCOperand_setImm(MCInst_getOperand(MI, 2), bd); } if (isBOCTRBranch(MCInst_getOpcode(MI))) { if (MCOperand_isImm(MCInst_getOperand(MI,0))) { int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0)); bd = SignExtend64(bd, 14); MCOperand_setImm(MCInst_getOperand(MI, 0), bd); } } mnem = printAliasBcc(MI, O, Info); if (!mnem) mnem = printAliasInstr(MI, O, Info); if (mnem != NULL) { if (strlen(mnem) > 0) { // check to remove the last letter of ('.', '-', '+') if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.') mnem[strlen(mnem) - 1] = '\0'; MCInst_setOpcodePub(MI, PPC_map_insn(mnem)); if (MI->csh->detail) { struct ppc_alias alias; if (PPC_alias_insn(mnem, &alias)) { MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc; } } } cs_mem_free(mnem); } else printInstruction(MI, O); } // FIXME enum ppc_bc_hint { PPC_BC_LT_MINUS = (0 << 5) | 14, PPC_BC_LE_MINUS = (1 << 5) | 6, PPC_BC_EQ_MINUS = (2 << 5) | 14, PPC_BC_GE_MINUS = (0 << 5) | 6, PPC_BC_GT_MINUS = (1 << 5) | 14, PPC_BC_NE_MINUS = (2 << 5) | 6, PPC_BC_UN_MINUS = (3 << 5) | 14, PPC_BC_NU_MINUS = (3 << 5) | 6, PPC_BC_LT_PLUS = (0 << 5) | 15, PPC_BC_LE_PLUS = (1 << 5) | 7, PPC_BC_EQ_PLUS = (2 << 5) | 15, PPC_BC_GE_PLUS = (0 << 5) | 7, PPC_BC_GT_PLUS = (1 << 5) | 15, PPC_BC_NE_PLUS = (2 << 5) | 7, PPC_BC_UN_PLUS = (3 << 5) | 15, PPC_BC_NU_PLUS = (3 << 5) | 7, }; // FIXME // normalize CC to remove _MINUS & _PLUS static int cc_normalize(int cc) { switch(cc) { default: return cc; case PPC_BC_LT_MINUS: return PPC_BC_LT; case PPC_BC_LE_MINUS: return PPC_BC_LE; case PPC_BC_EQ_MINUS: return PPC_BC_EQ; case PPC_BC_GE_MINUS: return PPC_BC_GE; case PPC_BC_GT_MINUS: return PPC_BC_GT; case PPC_BC_NE_MINUS: return PPC_BC_NE; case PPC_BC_UN_MINUS: return PPC_BC_UN; case PPC_BC_NU_MINUS: return PPC_BC_NU; case PPC_BC_LT_PLUS : return PPC_BC_LT; case PPC_BC_LE_PLUS : return PPC_BC_LE; case PPC_BC_EQ_PLUS : return PPC_BC_EQ; case PPC_BC_GE_PLUS : return PPC_BC_GE; case PPC_BC_GT_PLUS : return PPC_BC_GT; case PPC_BC_NE_PLUS : return PPC_BC_NE; case PPC_BC_UN_PLUS : return PPC_BC_UN; case PPC_BC_NU_PLUS : return PPC_BC_NU; } } static void printPredicateOperand(MCInst *MI, unsigned OpNo, SStream *O, const char *Modifier) { unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code); if (!strcmp(Modifier, "cc")) { switch ((ppc_predicate)Code) { default: // unreachable case PPC_PRED_LT_MINUS: case PPC_PRED_LT_PLUS: case PPC_PRED_LT: SStream_concat0(O, "lt"); return; case PPC_PRED_LE_MINUS: case PPC_PRED_LE_PLUS: case PPC_PRED_LE: SStream_concat0(O, "le"); return; case PPC_PRED_EQ_MINUS: case PPC_PRED_EQ_PLUS: case PPC_PRED_EQ: SStream_concat0(O, "eq"); return; case PPC_PRED_GE_MINUS: case PPC_PRED_GE_PLUS: case PPC_PRED_GE: SStream_concat0(O, "ge"); return; case PPC_PRED_GT_MINUS: case PPC_PRED_GT_PLUS: case PPC_PRED_GT: SStream_concat0(O, "gt"); return; case PPC_PRED_NE_MINUS: case PPC_PRED_NE_PLUS: case PPC_PRED_NE: SStream_concat0(O, "ne"); return; case PPC_PRED_UN_MINUS: case PPC_PRED_UN_PLUS: case PPC_PRED_UN: SStream_concat0(O, "un"); return; case PPC_PRED_NU_MINUS: case PPC_PRED_NU_PLUS: case PPC_PRED_NU: SStream_concat0(O, "nu"); return; case PPC_PRED_BIT_SET: case PPC_PRED_BIT_UNSET: // llvm_unreachable("Invalid use of bit predicate code"); SStream_concat0(O, "invalid-predicate"); return; } } if (!strcmp(Modifier, "pm")) { switch ((ppc_predicate)Code) { case PPC_PRED_LT: case PPC_PRED_LE: case PPC_PRED_EQ: case PPC_PRED_GE: case PPC_PRED_GT: case PPC_PRED_NE: case PPC_PRED_UN: case PPC_PRED_NU: return; case PPC_PRED_LT_MINUS: case PPC_PRED_LE_MINUS: case PPC_PRED_EQ_MINUS: case PPC_PRED_GE_MINUS: case PPC_PRED_GT_MINUS: case PPC_PRED_NE_MINUS: case PPC_PRED_UN_MINUS: case PPC_PRED_NU_MINUS: SStream_concat0(O, "-"); return; case PPC_PRED_LT_PLUS: case PPC_PRED_LE_PLUS: case PPC_PRED_EQ_PLUS: case PPC_PRED_GE_PLUS: case PPC_PRED_GT_PLUS: case PPC_PRED_NE_PLUS: case PPC_PRED_UN_PLUS: case PPC_PRED_NU_PLUS: SStream_concat0(O, "+"); return; case PPC_PRED_BIT_SET: case PPC_PRED_BIT_UNSET: // llvm_unreachable("Invalid use of bit predicate code"); SStream_concat0(O, "invalid-predicate"); return; default: // unreachable return; } // llvm_unreachable("Invalid predicate code"); } //assert(StringRef(Modifier) == "reg" && // "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!"); printOperand(MI, OpNo + 1, O); } static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O) { unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); if (Code == 2) { SStream_concat0(O, "-"); } else if (Code == 3) { SStream_concat0(O, "+"); } } static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); // assert(Value <= 1 && "Invalid u1imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 3 && "Invalid u2imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 8 && "Invalid u3imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 15 && "Invalid u4imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); Value = SignExtend32(Value, 5); printInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 31 && "Invalid u5imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 63 && "Invalid u6imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 127 && "Invalid u7imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } // Operands of BUILD_VECTOR are signed and we use this to print operands // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and // print as unsigned. static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //assert(Value <= 1023 && "Invalid u10imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); // assert(Value <= 4095 && "Invalid u12imm argument!"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value; MI->flat_insn->detail->ppc.op_count++; } } static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); printInt32(O, Imm); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm; } else { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; MI->flat_insn->detail->ppc.op_count++; } } } else printOperand(MI, OpNo, O); } static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O) { if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); printUInt32(O, Imm); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm; MI->flat_insn->detail->ppc.op_count++; } } else printOperand(MI, OpNo, O); } static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) { if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { printOperand(MI, OpNo, O); return; } // Branches can take an immediate operand. This is used by the branch // selection pass to print .+8, an eight byte displacement from the PC. // O << ".+"; printAbsBranchOperand(MI, OpNo, O); } static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O) { int64_t imm; if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) { printOperand(MI, OpNo, O); return; } imm = SignExtend32(MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4, 32); //imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4; if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) { imm += MI->address; } printUInt64(O, imm); if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm; MI->flat_insn->detail->ppc.op_count++; } } static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O) { unsigned RegNo; unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo)); switch (CCReg) { default: // llvm_unreachable("Unknown CR register"); case PPC_CR0: RegNo = 0; break; case PPC_CR1: RegNo = 1; break; case PPC_CR2: RegNo = 2; break; case PPC_CR3: RegNo = 3; break; case PPC_CR4: RegNo = 4; break; case PPC_CR5: RegNo = 5; break; case PPC_CR6: RegNo = 6; break; case PPC_CR7: RegNo = 7; break; } printUInt32(O, 0x80 >> RegNo); } static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O) { set_mem_access(MI, true); printS16ImmOperand(MI, OpNo, O); SStream_concat0(O, "("); if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0) SStream_concat0(O, "0"); else printOperand(MI, OpNo + 1, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin // assembler requires that we print r0 as 0 (no r) when used as the base. if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0) SStream_concat0(O, "0"); else printOperand(MI, OpNo, O); SStream_concat0(O, ", "); printOperand(MI, OpNo + 1, O); } static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O) { set_mem_access(MI, true); //printBranchOperand(MI, OpNo, O); // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must // come at the _end_ of the expression. SStream_concat0(O, "("); printOperand(MI, OpNo + 1, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } /// stripRegisterPrefix - This method strips the character prefix from a /// register name so that only the number is left. Used by for linux asm. static char *stripRegisterPrefix(const char *RegName) { switch (RegName[0]) { case 'r': case 'f': case 'q': // for QPX case 'v': if (RegName[1] == 's') return cs_strdup(RegName + 2); return cs_strdup(RegName + 1); case 'c': if (RegName[1] == 'r') { // skip the first 2 letters "cr" char *name = cs_strdup(RegName + 2); // also strip the last 2 letters name[strlen(name) - 2] = '\0'; return name; } } return cs_strdup(RegName); } static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { unsigned reg = MCOperand_getReg(Op); #ifndef CAPSTONE_DIET const char *RegName = getRegisterName(reg); // printf("reg = %u (%s)\n", reg, RegName); // convert internal register ID to public register ID reg = PPC_name_reg(RegName); // The linux and AIX assembler does not take register prefixes. if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) { char *name = stripRegisterPrefix(RegName); SStream_concat0(O, name); cs_mem_free(name); } else SStream_concat0(O, RegName); #endif if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg; } else { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg; MI->flat_insn->detail->ppc.op_count++; } } return; } if (MCOperand_isImm(Op)) { int32_t imm = (int32_t)MCOperand_getImm(Op); printInt32(O, imm); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm; } else { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm; MI->flat_insn->detail->ppc.op_count++; } } } } static void op_addImm(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM; MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v; MI->flat_insn->detail->ppc.op_count++; } } #define PRINT_ALIAS_INSTR #include "PPCGenRegisterName.inc" #include "PPCGenAsmWriter.inc" #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCInstPrinter.h000064400000000000000000000005700072674642500214360ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_PPCINSTPRINTER_H #define CS_PPCINSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void PPC_printInst(MCInst *MI, SStream *O, void *Info); void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCMapping.c000064400000000000000000000337770072674642500205620ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_POWERPC #include // debug #include #include "../../utils.h" #include "PPCMapping.h" #define GET_INSTRINFO_ENUM #include "PPCGenInstrInfo.inc" // NOTE: this reg_name_maps[] reflects the order of registers in ppc_reg static const name_map reg_name_maps[] = { { PPC_REG_INVALID, NULL }, { PPC_REG_CARRY, "ca" }, { PPC_REG_CTR, "ctr" }, { PPC_REG_LR, "lr" }, { PPC_REG_RM, "rm" }, { PPC_REG_VRSAVE, "vrsave" }, { PPC_REG_XER, "xer" }, { PPC_REG_ZERO, "zero" }, { PPC_REG_CR0, "cr0" }, { PPC_REG_CR1, "cr1" }, { PPC_REG_CR2, "cr2" }, { PPC_REG_CR3, "cr3" }, { PPC_REG_CR4, "cr4" }, { PPC_REG_CR5, "cr5" }, { PPC_REG_CR6, "cr6" }, { PPC_REG_CR7, "cr7" }, { PPC_REG_CTR8, "ctr8" }, { PPC_REG_F0, "f0" }, { PPC_REG_F1, "f1" }, { PPC_REG_F2, "f2" }, { PPC_REG_F3, "f3" }, { PPC_REG_F4, "f4" }, { PPC_REG_F5, "f5" }, { PPC_REG_F6, "f6" }, { PPC_REG_F7, "f7" }, { PPC_REG_F8, "f8" }, { PPC_REG_F9, "f9" }, { PPC_REG_F10, "f10" }, { PPC_REG_F11, "f11" }, { PPC_REG_F12, "f12" }, { PPC_REG_F13, "f13" }, { PPC_REG_F14, "f14" }, { PPC_REG_F15, "f15" }, { PPC_REG_F16, "f16" }, { PPC_REG_F17, "f17" }, { PPC_REG_F18, "f18" }, { PPC_REG_F19, "f19" }, { PPC_REG_F20, "f20" }, { PPC_REG_F21, "f21" }, { PPC_REG_F22, "f22" }, { PPC_REG_F23, "f23" }, { PPC_REG_F24, "f24" }, { PPC_REG_F25, "f25" }, { PPC_REG_F26, "f26" }, { PPC_REG_F27, "f27" }, { PPC_REG_F28, "f28" }, { PPC_REG_F29, "f29" }, { PPC_REG_F30, "f30" }, { PPC_REG_F31, "f31" }, { PPC_REG_LR8, "lr8" }, { PPC_REG_Q0, "q0" }, { PPC_REG_Q1, "q1" }, { PPC_REG_Q2, "q2" }, { PPC_REG_Q3, "q3" }, { PPC_REG_Q4, "q4" }, { PPC_REG_Q5, "q5" }, { PPC_REG_Q6, "q6" }, { PPC_REG_Q7, "q7" }, { PPC_REG_Q8, "q8" }, { PPC_REG_Q9, "q9" }, { PPC_REG_Q10, "q10" }, { PPC_REG_Q11, "q11" }, { PPC_REG_Q12, "q12" }, { PPC_REG_Q13, "q13" }, { PPC_REG_Q14, "q14" }, { PPC_REG_Q15, "q15" }, { PPC_REG_Q16, "q16" }, { PPC_REG_Q17, "q17" }, { PPC_REG_Q18, "q18" }, { PPC_REG_Q19, "q19" }, { PPC_REG_Q20, "q20" }, { PPC_REG_Q21, "q21" }, { PPC_REG_Q22, "q22" }, { PPC_REG_Q23, "q23" }, { PPC_REG_Q24, "q24" }, { PPC_REG_Q25, "q25" }, { PPC_REG_Q26, "q26" }, { PPC_REG_Q27, "q27" }, { PPC_REG_Q28, "q28" }, { PPC_REG_Q29, "q29" }, { PPC_REG_Q30, "q30" }, { PPC_REG_Q31, "q31" }, { PPC_REG_R0, "r0" }, { PPC_REG_R1, "r1" }, { PPC_REG_R2, "r2" }, { PPC_REG_R3, "r3" }, { PPC_REG_R4, "r4" }, { PPC_REG_R5, "r5" }, { PPC_REG_R6, "r6" }, { PPC_REG_R7, "r7" }, { PPC_REG_R8, "r8" }, { PPC_REG_R9, "r9" }, { PPC_REG_R10, "r10" }, { PPC_REG_R11, "r11" }, { PPC_REG_R12, "r12" }, { PPC_REG_R13, "r13" }, { PPC_REG_R14, "r14" }, { PPC_REG_R15, "r15" }, { PPC_REG_R16, "r16" }, { PPC_REG_R17, "r17" }, { PPC_REG_R18, "r18" }, { PPC_REG_R19, "r19" }, { PPC_REG_R20, "r20" }, { PPC_REG_R21, "r21" }, { PPC_REG_R22, "r22" }, { PPC_REG_R23, "r23" }, { PPC_REG_R24, "r24" }, { PPC_REG_R25, "r25" }, { PPC_REG_R26, "r26" }, { PPC_REG_R27, "r27" }, { PPC_REG_R28, "r28" }, { PPC_REG_R29, "r29" }, { PPC_REG_R30, "r30" }, { PPC_REG_R31, "r31" }, { PPC_REG_V0, "v0" }, { PPC_REG_V1, "v1" }, { PPC_REG_V2, "v2" }, { PPC_REG_V3, "v3" }, { PPC_REG_V4, "v4" }, { PPC_REG_V5, "v5" }, { PPC_REG_V6, "v6" }, { PPC_REG_V7, "v7" }, { PPC_REG_V8, "v8" }, { PPC_REG_V9, "v9" }, { PPC_REG_V10, "v10" }, { PPC_REG_V11, "v11" }, { PPC_REG_V12, "v12" }, { PPC_REG_V13, "v13" }, { PPC_REG_V14, "v14" }, { PPC_REG_V15, "v15" }, { PPC_REG_V16, "v16" }, { PPC_REG_V17, "v17" }, { PPC_REG_V18, "v18" }, { PPC_REG_V19, "v19" }, { PPC_REG_V20, "v20" }, { PPC_REG_V21, "v21" }, { PPC_REG_V22, "v22" }, { PPC_REG_V23, "v23" }, { PPC_REG_V24, "v24" }, { PPC_REG_V25, "v25" }, { PPC_REG_V26, "v26" }, { PPC_REG_V27, "v27" }, { PPC_REG_V28, "v28" }, { PPC_REG_V29, "v29" }, { PPC_REG_V30, "v30" }, { PPC_REG_V31, "v31" }, { PPC_REG_VS0, "vs0" }, { PPC_REG_VS1, "vs1" }, { PPC_REG_VS2, "vs2" }, { PPC_REG_VS3, "vs3" }, { PPC_REG_VS4, "vs4" }, { PPC_REG_VS5, "vs5" }, { PPC_REG_VS6, "vs6" }, { PPC_REG_VS7, "vs7" }, { PPC_REG_VS8, "vs8" }, { PPC_REG_VS9, "vs9" }, { PPC_REG_VS10, "vs10" }, { PPC_REG_VS11, "vs11" }, { PPC_REG_VS12, "vs12" }, { PPC_REG_VS13, "vs13" }, { PPC_REG_VS14, "vs14" }, { PPC_REG_VS15, "vs15" }, { PPC_REG_VS16, "vs16" }, { PPC_REG_VS17, "vs17" }, { PPC_REG_VS18, "vs18" }, { PPC_REG_VS19, "vs19" }, { PPC_REG_VS20, "vs20" }, { PPC_REG_VS21, "vs21" }, { PPC_REG_VS22, "vs22" }, { PPC_REG_VS23, "vs23" }, { PPC_REG_VS24, "vs24" }, { PPC_REG_VS25, "vs25" }, { PPC_REG_VS26, "vs26" }, { PPC_REG_VS27, "vs27" }, { PPC_REG_VS28, "vs28" }, { PPC_REG_VS29, "vs29" }, { PPC_REG_VS30, "vs30" }, { PPC_REG_VS31, "vs31" }, { PPC_REG_VS32, "vs32" }, { PPC_REG_VS33, "vs33" }, { PPC_REG_VS34, "vs34" }, { PPC_REG_VS35, "vs35" }, { PPC_REG_VS36, "vs36" }, { PPC_REG_VS37, "vs37" }, { PPC_REG_VS38, "vs38" }, { PPC_REG_VS39, "vs39" }, { PPC_REG_VS40, "vs40" }, { PPC_REG_VS41, "vs41" }, { PPC_REG_VS42, "vs42" }, { PPC_REG_VS43, "vs43" }, { PPC_REG_VS44, "vs44" }, { PPC_REG_VS45, "vs45" }, { PPC_REG_VS46, "vs46" }, { PPC_REG_VS47, "vs47" }, { PPC_REG_VS48, "vs48" }, { PPC_REG_VS49, "vs49" }, { PPC_REG_VS50, "vs50" }, { PPC_REG_VS51, "vs51" }, { PPC_REG_VS52, "vs52" }, { PPC_REG_VS53, "vs53" }, { PPC_REG_VS54, "vs54" }, { PPC_REG_VS55, "vs55" }, { PPC_REG_VS56, "vs56" }, { PPC_REG_VS57, "vs57" }, { PPC_REG_VS58, "vs58" }, { PPC_REG_VS59, "vs59" }, { PPC_REG_VS60, "vs60" }, { PPC_REG_VS61, "vs61" }, { PPC_REG_VS62, "vs62" }, { PPC_REG_VS63, "vs63" }, { PPC_REG_CR0EQ, "cr0eq" }, { PPC_REG_CR1EQ, "cr1eq" }, { PPC_REG_CR2EQ, "cr2eq" }, { PPC_REG_CR3EQ, "cr3eq" }, { PPC_REG_CR4EQ, "cr4eq" }, { PPC_REG_CR5EQ, "cr5eq" }, { PPC_REG_CR6EQ, "cr6eq" }, { PPC_REG_CR7EQ, "cr7eq" }, { PPC_REG_CR0GT, "cr0gt" }, { PPC_REG_CR1GT, "cr1gt" }, { PPC_REG_CR2GT, "cr2gt" }, { PPC_REG_CR3GT, "cr3gt" }, { PPC_REG_CR4GT, "cr4gt" }, { PPC_REG_CR5GT, "cr5gt" }, { PPC_REG_CR6GT, "cr6gt" }, { PPC_REG_CR7GT, "cr7gt" }, { PPC_REG_CR0LT, "cr0lt" }, { PPC_REG_CR1LT, "cr1lt" }, { PPC_REG_CR2LT, "cr2lt" }, { PPC_REG_CR3LT, "cr3lt" }, { PPC_REG_CR4LT, "cr4lt" }, { PPC_REG_CR5LT, "cr5lt" }, { PPC_REG_CR6LT, "cr6lt" }, { PPC_REG_CR7LT, "cr7lt" }, { PPC_REG_CR0UN, "cr0un" }, { PPC_REG_CR1UN, "cr1un" }, { PPC_REG_CR2UN, "cr2un" }, { PPC_REG_CR3UN, "cr3un" }, { PPC_REG_CR4UN, "cr4un" }, { PPC_REG_CR5UN, "cr5un" }, { PPC_REG_CR6UN, "cr6un" }, { PPC_REG_CR7UN, "cr7un" }, }; const char *PPC_reg_name(csh handle, unsigned int reg) { // binary searching since the IDs are sorted in order unsigned int left, right, m; unsigned int max = ARR_SIZE(reg_name_maps); right = max - 1; if (reg < reg_name_maps[0].id || reg > reg_name_maps[right].id) // not found return NULL; left = 0; while(left <= right) { m = (left + right) / 2; if (reg == reg_name_maps[m].id) { return reg_name_maps[m].name; } if (reg < reg_name_maps[m].id) right = m - 1; else left = m + 1; } // not found return NULL; } ppc_reg PPC_name_reg(const char *name) { unsigned int i; for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { if (!strcmp(name, reg_name_maps[i].name)) return reg_name_maps[i].id; } // not found return 0; } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "PPCMappingInsn.inc" }; // given internal insn id, return public instruction info void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { int i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET cs_struct handle; handle.detail = h->detail; memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = PPC_GRP_JUMP; insn->detail->groups_count++; } insn->detail->ppc.update_cr0 = cs_reg_write((csh)&handle, insn, PPC_REG_CR0); #endif } } } static const char * const insn_name_maps[] = { NULL, // PPC_INS_BCT #include "PPCMappingInsnName.inc" }; const char *PPC_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= PPC_INS_ENDING) return NULL; return insn_name_maps[id]; #else return NULL; #endif } // map instruction name to public instruction ID ppc_insn PPC_map_insn(const char *name) { unsigned int i; for(i = 1; i < ARR_SIZE(insn_name_maps); i++) { if (!strcmp(name, insn_name_maps[i])) return i; } // not found return PPC_INS_INVALID; } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { PPC_GRP_INVALID, NULL }, { PPC_GRP_JUMP, "jump" }, // architecture-specific groups { PPC_GRP_ALTIVEC, "altivec" }, { PPC_GRP_MODE32, "mode32" }, { PPC_GRP_MODE64, "mode64" }, { PPC_GRP_BOOKE, "booke" }, { PPC_GRP_NOTBOOKE, "notbooke" }, { PPC_GRP_SPE, "spe" }, { PPC_GRP_VSX, "vsx" }, { PPC_GRP_E500, "e500" }, { PPC_GRP_PPC4XX, "ppc4xx" }, { PPC_GRP_PPC6XX, "ppc6xx" }, { PPC_GRP_ICBT, "icbt" }, { PPC_GRP_P8ALTIVEC, "p8altivec" }, { PPC_GRP_P8VECTOR, "p8vector" }, { PPC_GRP_QPX, "qpx" }, }; #endif const char *PPC_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } static const struct ppc_alias alias_insn_name_maps[] = { //{ PPC_INS_BTA, "bta" }, { PPC_INS_B, PPC_BC_LT, "blt" }, { PPC_INS_B, PPC_BC_LE, "ble" }, { PPC_INS_B, PPC_BC_EQ, "beq" }, { PPC_INS_B, PPC_BC_GE, "bge" }, { PPC_INS_B, PPC_BC_GT, "bgt" }, { PPC_INS_B, PPC_BC_NE, "bne" }, { PPC_INS_B, PPC_BC_UN, "bun" }, { PPC_INS_B, PPC_BC_NU, "bnu" }, { PPC_INS_B, PPC_BC_SO, "bso" }, { PPC_INS_B, PPC_BC_NS, "bns" }, { PPC_INS_BA, PPC_BC_LT, "blta" }, { PPC_INS_BA, PPC_BC_LE, "blea" }, { PPC_INS_BA, PPC_BC_EQ, "beqa" }, { PPC_INS_BA, PPC_BC_GE, "bgea" }, { PPC_INS_BA, PPC_BC_GT, "bgta" }, { PPC_INS_BA, PPC_BC_NE, "bnea" }, { PPC_INS_BA, PPC_BC_UN, "buna" }, { PPC_INS_BA, PPC_BC_NU, "bnua" }, { PPC_INS_BA, PPC_BC_SO, "bsoa" }, { PPC_INS_BA, PPC_BC_NS, "bnsa" }, { PPC_INS_BCTR, PPC_BC_LT, "bltctr" }, { PPC_INS_BCTR, PPC_BC_LE, "blectr" }, { PPC_INS_BCTR, PPC_BC_EQ, "beqctr" }, { PPC_INS_BCTR, PPC_BC_GE, "bgectr" }, { PPC_INS_BCTR, PPC_BC_GT, "bgtctr" }, { PPC_INS_BCTR, PPC_BC_NE, "bnectr" }, { PPC_INS_BCTR, PPC_BC_UN, "bunctr" }, { PPC_INS_BCTR, PPC_BC_NU, "bnuctr" }, { PPC_INS_BCTR, PPC_BC_SO, "bsoctr" }, { PPC_INS_BCTR, PPC_BC_NS, "bnsctr" }, { PPC_INS_BCTRL, PPC_BC_LT, "bltctrl" }, { PPC_INS_BCTRL, PPC_BC_LE, "blectrl" }, { PPC_INS_BCTRL, PPC_BC_EQ, "beqctrl" }, { PPC_INS_BCTRL, PPC_BC_GE, "bgectrl" }, { PPC_INS_BCTRL, PPC_BC_GT, "bgtctrl" }, { PPC_INS_BCTRL, PPC_BC_NE, "bnectrl" }, { PPC_INS_BCTRL, PPC_BC_UN, "bunctrl" }, { PPC_INS_BCTRL, PPC_BC_NU, "bnuctrl" }, { PPC_INS_BCTRL, PPC_BC_SO, "bsoctrl" }, { PPC_INS_BCTRL, PPC_BC_NS, "bnsctrl" }, { PPC_INS_BL, PPC_BC_LT, "bltl" }, { PPC_INS_BL, PPC_BC_LE, "blel" }, { PPC_INS_BL, PPC_BC_EQ, "beql" }, { PPC_INS_BL, PPC_BC_GE, "bgel" }, { PPC_INS_BL, PPC_BC_GT, "bgtl" }, { PPC_INS_BL, PPC_BC_NE, "bnel" }, { PPC_INS_BL, PPC_BC_UN, "bunl" }, { PPC_INS_BL, PPC_BC_NU, "bnul" }, { PPC_INS_BL, PPC_BC_SO, "bsol" }, { PPC_INS_BL, PPC_BC_NS, "bnsl" }, { PPC_INS_BLA, PPC_BC_LT, "bltla" }, { PPC_INS_BLA, PPC_BC_LE, "blela" }, { PPC_INS_BLA, PPC_BC_EQ, "beqla" }, { PPC_INS_BLA, PPC_BC_GE, "bgela" }, { PPC_INS_BLA, PPC_BC_GT, "bgtla" }, { PPC_INS_BLA, PPC_BC_NE, "bnela" }, { PPC_INS_BLA, PPC_BC_UN, "bunla" }, { PPC_INS_BLA, PPC_BC_NU, "bnula" }, { PPC_INS_BLA, PPC_BC_SO, "bsola" }, { PPC_INS_BLA, PPC_BC_NS, "bnsla" }, { PPC_INS_BLR, PPC_BC_LT, "bltlr" }, { PPC_INS_BLR, PPC_BC_LE, "blelr" }, { PPC_INS_BLR, PPC_BC_EQ, "beqlr" }, { PPC_INS_BLR, PPC_BC_GE, "bgelr" }, { PPC_INS_BLR, PPC_BC_GT, "bgtlr" }, { PPC_INS_BLR, PPC_BC_NE, "bnelr" }, { PPC_INS_BLR, PPC_BC_UN, "bunlr" }, { PPC_INS_BLR, PPC_BC_NU, "bnulr" }, { PPC_INS_BLR, PPC_BC_SO, "bsolr" }, { PPC_INS_BLR, PPC_BC_NS, "bnslr" }, { PPC_INS_BLRL, PPC_BC_LT, "bltlrl" }, { PPC_INS_BLRL, PPC_BC_LE, "blelrl" }, { PPC_INS_BLRL, PPC_BC_EQ, "beqlrl" }, { PPC_INS_BLRL, PPC_BC_GE, "bgelrl" }, { PPC_INS_BLRL, PPC_BC_GT, "bgtlrl" }, { PPC_INS_BLRL, PPC_BC_NE, "bnelrl" }, { PPC_INS_BLRL, PPC_BC_UN, "bunlrl" }, { PPC_INS_BLRL, PPC_BC_NU, "bnulrl" }, { PPC_INS_BLRL, PPC_BC_SO, "bsolrl" }, { PPC_INS_BLRL, PPC_BC_NS, "bnslrl" }, }; // given alias mnemonic, return instruction ID & CC bool PPC_alias_insn(const char *name, struct ppc_alias *alias) { size_t i; alias->cc = PPC_BC_INVALID; for(i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { if (!strcmp(name, alias_insn_name_maps[i].mnem)) { // alias->id = alias_insn_name_maps[i].id; alias->cc = alias_insn_name_maps[i].cc; return true; } } // not found return false; } // check if this insn is relative branch bool PPC_abs_branch(cs_struct *h, unsigned int id) { unsigned int i; // list all absolute branch instructions static const unsigned int insn_abs[] = { PPC_BA, PPC_BCCA, PPC_BCCLA, PPC_BDNZA, PPC_BDNZAm, PPC_BDNZAp, PPC_BDNZLA, PPC_BDNZLAm, PPC_BDNZLAp, PPC_BDZA, PPC_BDZAm, PPC_BDZAp, PPC_BDZLAm, PPC_BDZLAp, PPC_BLA, PPC_gBCA, PPC_gBCLA, PPC_BDZLA, 0 }; // printf("opcode: %u\n", id); for (i = 0; insn_abs[i]; i++) { if (id == insn_abs[i]) { return true; } } // not found return false; } #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCMapping.h000064400000000000000000000021150072674642500205450ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_PPC_MAP_H #define CS_PPC_MAP_H #include "capstone/capstone.h" // return name of regiser in friendly string const char *PPC_reg_name(csh handle, unsigned int reg); // return register id, given register name ppc_reg PPC_name_reg(const char *name); // given internal insn id, return public instruction info void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *PPC_insn_name(csh handle, unsigned int id); const char *PPC_group_name(csh handle, unsigned int id); struct ppc_alias { unsigned int id; // instruction id int cc; // code condition const char *mnem; }; // map instruction name to public instruction ID ppc_insn PPC_map_insn(const char *name); // check if this insn is relative branch bool PPC_abs_branch(cs_struct *h, unsigned int id); // map internal raw register to 'public' register ppc_reg PPC_map_register(unsigned int r); // given alias mnemonic, return instruction ID & CC bool PPC_alias_insn(const char *name, struct ppc_alias *alias); #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCMappingInsn.inc000064400000000000000000005627150072674642500217400ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { PPC_CLRLSLDI, PPC_INS_CLRLSLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRLSLDIo, PPC_INS_CLRLSLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRLSLWI, PPC_INS_CLRLSLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRLSLWIo, PPC_INS_CLRLSLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRRDI, PPC_INS_CLRRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRRDIo, PPC_INS_CLRRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRRWI, PPC_INS_CLRRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CLRRWIo, PPC_INS_CLRRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_COPY_FIRST, PPC_INS_COPY_FIRST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_COPYx, PPC_INS_COPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_PASTE_LAST, PPC_INS_PASTE_LAST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_PASTEx, PPC_INS_PASTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBFL, PPC_INS_DCBFL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBFLP, PPC_INS_DCBFLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBFx, PPC_INS_DCBF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTCT, PPC_INS_DCBTCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTDS, PPC_INS_DCBTDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTSTCT, PPC_INS_DCBTSTCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTSTDS, PPC_INS_DCBTSTDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTSTT, PPC_INS_DCBTSTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTSTx, PPC_INS_DCBTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTT, PPC_INS_DCBTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTx, PPC_INS_DCBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTLDI, PPC_INS_EXTLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTLDIo, PPC_INS_EXTLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTLWI, PPC_INS_EXTLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTLWIo, PPC_INS_EXTLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTRDI, PPC_INS_EXTRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTRDIo, PPC_INS_EXTRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTRWI, PPC_INS_EXTRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTRWIo, PPC_INS_EXTRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_INSLWI, PPC_INS_INSLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_INSLWIo, PPC_INS_INSLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_INSRDI, PPC_INS_INSRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_INSRDIo, PPC_INS_INSRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_INSRWI, PPC_INS_INSRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_INSRWIo, PPC_INS_INSRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LAx, PPC_INS_LA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWIMIbm, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWIMIobm, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWINMbm, PPC_INS_RLWINM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWINMobm, PPC_INS_RLWINM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWNMbm, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWNMobm, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ROTRDI, PPC_INS_ROTRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ROTRDIo, PPC_INS_ROTRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ROTRWI, PPC_INS_ROTRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ROTRWIo, PPC_INS_ROTRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLDI, PPC_INS_SLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLDIo, PPC_INS_SLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLWI, PPC_INS_SLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLWIo, PPC_INS_SLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRDI, PPC_INS_SRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRDIo, PPC_INS_SRDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRWI, PPC_INS_SRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRWIo, PPC_INS_SRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBI, PPC_INS_SUBI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBIC, PPC_INS_SUBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBICo, PPC_INS_SUBIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBIS, PPC_INS_SUBIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBPCIS, PPC_INS_SUBPCIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD4, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD4TLS, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD4o, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD8, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD8TLS, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD8TLS_, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADD8o, PPC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDC, PPC_INS_ADDC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDC8, PPC_INS_ADDC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDC8o, PPC_INS_ADDC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDCo, PPC_INS_ADDC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDE, PPC_INS_ADDE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDE8, PPC_INS_ADDE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDE8o, PPC_INS_ADDE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDEo, PPC_INS_ADDE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDI, PPC_INS_ADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDI8, PPC_INS_ADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDIC, PPC_INS_ADDIC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDIC8, PPC_INS_ADDIC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDICo, PPC_INS_ADDIC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDIS, PPC_INS_ADDIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDIS8, PPC_INS_ADDIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDME, PPC_INS_ADDME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDME8, PPC_INS_ADDME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDME8o, PPC_INS_ADDME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDMEo, PPC_INS_ADDME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDPCIS, PPC_INS_ADDPCIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDZE, PPC_INS_ADDZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDZE8, PPC_INS_ADDZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDZE8o, PPC_INS_ADDZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ADDZEo, PPC_INS_ADDZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_AND, PPC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_AND8, PPC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_AND8o, PPC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDC, PPC_INS_ANDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDC8, PPC_INS_ANDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDC8o, PPC_INS_ANDC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDCo, PPC_INS_ANDC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDISo, PPC_INS_ANDIS, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDISo8, PPC_INS_ANDIS, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDIo, PPC_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDIo8, PPC_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ANDo, PPC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ATTN, PPC_INS_ATTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_B, PPC_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BA, PPC_INS_BA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BC, PPC_INS_BC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BCC, PPC_INS_BEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCA, PPC_INS_BEQA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCCTR, PPC_INS_BEQCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { PPC_BCCCTR8, PPC_INS_BCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 #endif }, { PPC_BCCCTRL, PPC_INS_BEQCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCCTRL8, PPC_INS_BCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 #endif }, { PPC_BCCL, PPC_INS_BEQL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCLA, PPC_INS_BEQLA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCLR, PPC_INS_BEQLR, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCLRL, PPC_INS_BEQLRL, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCTR, PPC_INS_BCCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { PPC_BCCTR8, PPC_INS_BCCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 #endif }, { PPC_BCCTR8n, PPC_INS_BCCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 #endif }, { PPC_BCCTRL, PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCTRL8, PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 #endif }, { PPC_BCCTRL8n, PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 #endif }, { PPC_BCCTRLn, PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCCTRn, PPC_INS_BCCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { PPC_BCDCFNo, PPC_INS_BCDCFN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDCFSQo, PPC_INS_BCDCFSQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDCFZo, PPC_INS_BCDCFZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDCPSGNo, PPC_INS_BCDCPSGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDCTNo, PPC_INS_BCDCTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDCTSQo, PPC_INS_BCDCTSQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDCTZo, PPC_INS_BCDCTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDSETSGNo, PPC_INS_BCDSETSGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDSRo, PPC_INS_BCDSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDSo, PPC_INS_BCDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDTRUNCo, PPC_INS_BCDTRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDUSo, PPC_INS_BCDUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCDUTRUNCo, PPC_INS_BCDUTRUNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BCL, PPC_INS_BCL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { PPC_BCLR, PPC_INS_BCLR, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BCLRL, PPC_INS_BCLRL, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCLRLn, PPC_INS_BCLRL, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCLRn, PPC_INS_BCLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BCLalways, PPC_INS_BCL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCLn, PPC_INS_BCL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BCTR, PPC_INS_BCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { PPC_BCTR8, PPC_INS_BCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 #endif }, { PPC_BCTRL, PPC_INS_BCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { PPC_GRP_MODE32, 0 }, 1, 0 #endif }, { PPC_BCTRL8, PPC_INS_BCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 #endif }, { PPC_BCTRL8_LDinto_toc, PPC_INS_BCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 #endif }, { PPC_BCn, PPC_INS_BC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZ, PPC_INS_BDNZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZ8, PPC_INS_BDNZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZA, PPC_INS_BDNZA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZAm, PPC_INS_BDNZA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZAp, PPC_INS_BDNZA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZL, PPC_INS_BDNZL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLA, PPC_INS_BDNZLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLAm, PPC_INS_BDNZLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLAp, PPC_INS_BDNZLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLR, PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLR8, PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLRL, PPC_INS_BDNZLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLRLm, PPC_INS_BDNZLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLRLp, PPC_INS_BDNZLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLRm, PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLRp, PPC_INS_BDNZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLm, PPC_INS_BDNZL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZLp, PPC_INS_BDNZL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZm, PPC_INS_BDNZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDNZp, PPC_INS_BDNZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZ, PPC_INS_BDZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZ8, PPC_INS_BDZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZA, PPC_INS_BDZA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZAm, PPC_INS_BDZA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZAp, PPC_INS_BDZA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZL, PPC_INS_BDZL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLA, PPC_INS_BDZLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLAm, PPC_INS_BDZLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLAp, PPC_INS_BDZLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLR, PPC_INS_BDZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLR8, PPC_INS_BDZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_LR8, PPC_REG_RM, 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLRL, PPC_INS_BDZLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLRLm, PPC_INS_BDZLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLRLp, PPC_INS_BDZLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLRm, PPC_INS_BDZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLRp, PPC_INS_BDZLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLm, PPC_INS_BDZL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZLp, PPC_INS_BDZL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZm, PPC_INS_BDZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BDZp, PPC_INS_BDZ, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL8, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL8_NOP, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL8_NOP_TLS, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL8_TLS, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL8_TLS_, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BLA, PPC_INS_BLA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BLA8, PPC_INS_BLA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BLA8_NOP, PPC_INS_BLA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { 0 }, 1, 0 #endif }, { PPC_BLR, PPC_INS_BLR, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 0 #endif }, { PPC_BLR8, PPC_INS_BLR, #ifndef CAPSTONE_DIET { PPC_REG_LR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 0 #endif }, { PPC_BLRL, PPC_INS_BLRL, #ifndef CAPSTONE_DIET { PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BL_TLS, PPC_INS_BL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 1, 0 #endif }, { PPC_BPERMD, PPC_INS_BPERMD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_BRINC, PPC_INS_BRINC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_CLRBHRB, PPC_INS_CLRBHRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPB, PPC_INS_CMPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPB8, PPC_INS_CMPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPD, PPC_INS_CMPD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPDI, PPC_INS_CMPDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPEQB, PPC_INS_CMPEQB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPLD, PPC_INS_CMPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPLDI, PPC_INS_CMPLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPLW, PPC_INS_CMPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPLWI, PPC_INS_CMPLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPRB, PPC_INS_CMPRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPW, PPC_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CMPWI, PPC_INS_CMPWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTLZD, PPC_INS_CNTLZD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTLZDo, PPC_INS_CNTLZD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTLZW, PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTLZW8, PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTLZW8o, PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTLZWo, PPC_INS_CNTLZW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTTZD, PPC_INS_CNTTZD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTTZDo, PPC_INS_CNTTZD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTTZW, PPC_INS_CNTTZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CNTTZWo, PPC_INS_CNTTZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_ABORT, PPC_INS_CP_ABORT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_COPY, PPC_INS_COPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_PASTE, PPC_INS_PASTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CP_PASTEo, PPC_INS_PASTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CR6SET, PPC_INS_CREQV, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 #endif }, { PPC_CR6UNSET, PPC_INS_CRXOR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1EQ, 0 }, { 0 }, 0, 0 #endif }, { PPC_CRAND, PPC_INS_CRAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRANDC, PPC_INS_CRANDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CREQV, PPC_INS_CREQV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRNAND, PPC_INS_CRNAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRNOR, PPC_INS_CRNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CROR, PPC_INS_CROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRORC, PPC_INS_CRORC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRSET, PPC_INS_CRSET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRUNSET, PPC_INS_CRXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_CRXOR, PPC_INS_CRXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DARN, PPC_INS_DARN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBA, PPC_INS_DCBA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBF, PPC_INS_DCBF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBFEP, PPC_INS_DCBFEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBI, PPC_INS_DCBI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBST, PPC_INS_DCBST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBSTEP, PPC_INS_DCBSTEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBT, PPC_INS_DCBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTEP, PPC_INS_DCBTEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTST, PPC_INS_DCBTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBTSTEP, PPC_INS_DCBTSTEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBZ, PPC_INS_DCBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBZEP, PPC_INS_DCBZEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBZL, PPC_INS_DCBZL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCBZLEP, PPC_INS_DCBZLEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DCCCI, PPC_INS_DCCCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_DIVD, PPC_INS_DIVD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDE, PPC_INS_DIVDE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDEU, PPC_INS_DIVDEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDEUo, PPC_INS_DIVDEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDEo, PPC_INS_DIVDE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDU, PPC_INS_DIVDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDUo, PPC_INS_DIVDU, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVDo, PPC_INS_DIVD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVW, PPC_INS_DIVW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWE, PPC_INS_DIVWE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWEU, PPC_INS_DIVWEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWEUo, PPC_INS_DIVWEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWEo, PPC_INS_DIVWE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWU, PPC_INS_DIVWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWUo, PPC_INS_DIVWU, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_DIVWo, PPC_INS_DIVW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_DSS, PPC_INS_DSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSSALL, PPC_INS_DSSALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DST, PPC_INS_DST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DST64, PPC_INS_DST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSTST, PPC_INS_DSTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSTST64, PPC_INS_DSTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSTSTT, PPC_INS_DSTSTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSTSTT64, PPC_INS_DSTSTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSTT, PPC_INS_DSTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_DSTT64, PPC_INS_DSTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_EFDABS, PPC_INS_EFDABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDADD, PPC_INS_EFDADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFS, PPC_INS_EFDCFS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFSF, PPC_INS_EFDCFSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFSI, PPC_INS_EFDCFSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFSID, PPC_INS_EFDCFSID, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFUF, PPC_INS_EFDCFUF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFUI, PPC_INS_EFDCFUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCFUID, PPC_INS_EFDCFUID, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCMPEQ, PPC_INS_EFDCMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCMPGT, PPC_INS_EFDCMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCMPLT, PPC_INS_EFDCMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTSF, PPC_INS_EFDCTSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTSI, PPC_INS_EFDCTSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTSIDZ, PPC_INS_EFDCTSIDZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTSIZ, PPC_INS_EFDCTSIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTUF, PPC_INS_EFDCTUF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTUI, PPC_INS_EFDCTUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTUIDZ, PPC_INS_EFDCTUIDZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDCTUIZ, PPC_INS_EFDCTUIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDDIV, PPC_INS_EFDDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDMUL, PPC_INS_EFDMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDNABS, PPC_INS_EFDNABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDNEG, PPC_INS_EFDNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDSUB, PPC_INS_EFDSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDTSTEQ, PPC_INS_EFDTSTEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDTSTGT, PPC_INS_EFDTSTGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFDTSTLT, PPC_INS_EFDTSTLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSABS, PPC_INS_EFSABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSADD, PPC_INS_EFSADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCFD, PPC_INS_EFSCFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCFSF, PPC_INS_EFSCFSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCFSI, PPC_INS_EFSCFSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCFUF, PPC_INS_EFSCFUF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCFUI, PPC_INS_EFSCFUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCMPEQ, PPC_INS_EFSCMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCMPGT, PPC_INS_EFSCMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCMPLT, PPC_INS_EFSCMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCTSF, PPC_INS_EFSCTSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCTSI, PPC_INS_EFSCTSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCTSIZ, PPC_INS_EFSCTSIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCTUF, PPC_INS_EFSCTUF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCTUI, PPC_INS_EFSCTUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSCTUIZ, PPC_INS_EFSCTUIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSDIV, PPC_INS_EFSDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSMUL, PPC_INS_EFSMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSNABS, PPC_INS_EFSNABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSNEG, PPC_INS_EFSNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSSUB, PPC_INS_EFSSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSTSTEQ, PPC_INS_EFSTSTEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSTSTGT, PPC_INS_EFSTSTGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EFSTSTLT, PPC_INS_EFSTSTLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EQV, PPC_INS_EQV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EQV8, PPC_INS_EQV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EQV8o, PPC_INS_EQV, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EQVo, PPC_INS_EQV, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EVABS, PPC_INS_EVABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVADDIW, PPC_INS_EVADDIW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVADDSMIAAW, PPC_INS_EVADDSMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVADDSSIAAW, PPC_INS_EVADDSSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVADDUMIAAW, PPC_INS_EVADDUMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVADDUSIAAW, PPC_INS_EVADDUSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVADDW, PPC_INS_EVADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVAND, PPC_INS_EVAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVANDC, PPC_INS_EVANDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCMPEQ, PPC_INS_EVCMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCMPGTS, PPC_INS_EVCMPGTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCMPGTU, PPC_INS_EVCMPGTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCMPLTS, PPC_INS_EVCMPLTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCMPLTU, PPC_INS_EVCMPLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCNTLSW, PPC_INS_EVCNTLSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVCNTLZW, PPC_INS_EVCNTLZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVDIVWS, PPC_INS_EVDIVWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVDIVWU, PPC_INS_EVDIVWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVEQV, PPC_INS_EVEQV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVEXTSB, PPC_INS_EVEXTSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVEXTSH, PPC_INS_EVEXTSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVFSABS, PPC_INS_EVFSABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSADD, PPC_INS_EVFSADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCFSF, PPC_INS_EVFSCFSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCFSI, PPC_INS_EVFSCFSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCFUF, PPC_INS_EVFSCFUF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCFUI, PPC_INS_EVFSCFUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCMPEQ, PPC_INS_EVFSCMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCMPGT, PPC_INS_EVFSCMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCMPLT, PPC_INS_EVFSCMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCTSF, PPC_INS_EVFSCTSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCTSI, PPC_INS_EVFSCTSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCTSIZ, PPC_INS_EVFSCTSIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCTUF, PPC_INS_EVFSCTSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCTUI, PPC_INS_EVFSCTUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSCTUIZ, PPC_INS_EVFSCTSIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSDIV, PPC_INS_EVFSDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSMUL, PPC_INS_EVFSMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSNABS, PPC_INS_EVFSNABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSNEG, PPC_INS_EVFSNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSSUB, PPC_INS_EVFSSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSTSTEQ, PPC_INS_EVFSTSTEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSTSTGT, PPC_INS_EVFSTSTGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVFSTSTLT, PPC_INS_EVFSTSTLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVLDD, PPC_INS_EVLDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLDDX, PPC_INS_EVLDDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLDH, PPC_INS_EVLDH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLDHX, PPC_INS_EVLDHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLDW, PPC_INS_EVLDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLDWX, PPC_INS_EVLDWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLHHESPLAT, PPC_INS_EVLHHESPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLHHESPLATX, PPC_INS_EVLHHESPLATX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLHHOSSPLAT, PPC_INS_EVLHHOSSPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLHHOSSPLATX, PPC_INS_EVLHHOSSPLATX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLHHOUSPLAT, PPC_INS_EVLHHOUSPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLHHOUSPLATX, PPC_INS_EVLHHOUSPLATX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHE, PPC_INS_EVLWHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHEX, PPC_INS_EVLWHEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHOS, PPC_INS_EVLWHOS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHOSX, PPC_INS_EVLWHOSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHOU, PPC_INS_EVLWHOU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHOUX, PPC_INS_EVLWHOUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHSPLAT, PPC_INS_EVLWHSPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWHSPLATX, PPC_INS_EVLWHSPLATX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWWSPLAT, PPC_INS_EVLWWSPLAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVLWWSPLATX, PPC_INS_EVLWWSPLATX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMERGEHI, PPC_INS_EVMERGEHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMERGEHILO, PPC_INS_EVMERGEHILO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMERGELO, PPC_INS_EVMERGELO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMERGELOHI, PPC_INS_EVMERGELOHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEGSMFAA, PPC_INS_EVMHEGSMFAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEGSMFAN, PPC_INS_EVMHEGSMFAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEGSMIAA, PPC_INS_EVMHEGSMIAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEGSMIAN, PPC_INS_EVMHEGSMIAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEGUMIAA, PPC_INS_EVMHEGUMIAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEGUMIAN, PPC_INS_EVMHEGUMIAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMF, PPC_INS_EVMHESMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMFA, PPC_INS_EVMHESMFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMFAAW, PPC_INS_EVMHESMFAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMFANW, PPC_INS_EVMHESMFANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMI, PPC_INS_EVMHESMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMIA, PPC_INS_EVMHESMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMIAAW, PPC_INS_EVMHESMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESMIANW, PPC_INS_EVMHESMIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESSF, PPC_INS_EVMHESSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESSFA, PPC_INS_EVMHESSFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESSFAAW, PPC_INS_EVMHESSFAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESSFANW, PPC_INS_EVMHESSFANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESSIAAW, PPC_INS_EVMHESSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHESSIANW, PPC_INS_EVMHESSIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEUMI, PPC_INS_EVMHEUMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEUMIA, PPC_INS_EVMHEUMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEUMIAAW, PPC_INS_EVMHEUMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEUMIANW, PPC_INS_EVMHEUMIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEUSIAAW, PPC_INS_EVMHEUSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHEUSIANW, PPC_INS_EVMHEUSIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOGSMFAA, PPC_INS_EVMHOGSMFAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOGSMFAN, PPC_INS_EVMHOGSMFAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOGSMIAA, PPC_INS_EVMHOGSMIAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOGSMIAN, PPC_INS_EVMHOGSMIAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOGUMIAA, PPC_INS_EVMHOGUMIAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOGUMIAN, PPC_INS_EVMHOGUMIAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMF, PPC_INS_EVMHOSMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMFA, PPC_INS_EVMHOSMFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMFAAW, PPC_INS_EVMHOSMFAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMFANW, PPC_INS_EVMHOSMFANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMI, PPC_INS_EVMHOSMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMIA, PPC_INS_EVMHOSMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMIAAW, PPC_INS_EVMHOSMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSMIANW, PPC_INS_EVMHOSMIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSSF, PPC_INS_EVMHOSSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSSFA, PPC_INS_EVMHOSSFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSSFAAW, PPC_INS_EVMHOSSFAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSSFANW, PPC_INS_EVMHOSSFANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSSIAAW, PPC_INS_EVMHOSSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOSSIANW, PPC_INS_EVMHOSSIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOUMI, PPC_INS_EVMHOUMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOUMIA, PPC_INS_EVMHOUMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOUMIAAW, PPC_INS_EVMHOUMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOUMIANW, PPC_INS_EVMHOUMIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOUSIAAW, PPC_INS_EVMHOUSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMHOUSIANW, PPC_INS_EVMHOUSIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMRA, PPC_INS_EVMRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHSMF, PPC_INS_EVMWHSMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHSMFA, PPC_INS_EVMWHSMFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHSMI, PPC_INS_EVMWHSMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHSMIA, PPC_INS_EVMWHSMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHSSF, PPC_INS_EVMWHSSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHSSFA, PPC_INS_EVMWHSSFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHUMI, PPC_INS_EVMWHUMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWHUMIA, PPC_INS_EVMWHUMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLSMIAAW, PPC_INS_EVMWLSMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLSMIANW, PPC_INS_EVMWLSMIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLSSIAAW, PPC_INS_EVMWLSSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLSSIANW, PPC_INS_EVMWLSSIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLUMI, PPC_INS_EVMWLUMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLUMIA, PPC_INS_EVMWLUMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLUMIAAW, PPC_INS_EVMWLUMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLUMIANW, PPC_INS_EVMWLUMIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLUSIAAW, PPC_INS_EVMWLUSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWLUSIANW, PPC_INS_EVMWLUSIANW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMF, PPC_INS_EVMWSMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMFA, PPC_INS_EVMWSMFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMFAA, PPC_INS_EVMWSMFAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMFAN, PPC_INS_EVMWSMFAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMI, PPC_INS_EVMWSMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMIA, PPC_INS_EVMWSMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMIAA, PPC_INS_EVMWSMIAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSMIAN, PPC_INS_EVMWSMIAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSSF, PPC_INS_EVMWSSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSSFA, PPC_INS_EVMWSSFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSSFAA, PPC_INS_EVMWSSFAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWSSFAN, PPC_INS_EVMWSSFAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWUMI, PPC_INS_EVMWUMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWUMIA, PPC_INS_EVMWUMIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWUMIAA, PPC_INS_EVMWUMIAA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVMWUMIAN, PPC_INS_EVMWUMIAN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVNAND, PPC_INS_EVNAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVNEG, PPC_INS_EVNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVNOR, PPC_INS_EVNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVOR, PPC_INS_EVOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVORC, PPC_INS_EVORC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVRLW, PPC_INS_EVRLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVRLWI, PPC_INS_EVRLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVRNDW, PPC_INS_EVRNDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSEL, PPC_INS_EVSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EVSLW, PPC_INS_EVSLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSLWI, PPC_INS_EVSLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSPLATFI, PPC_INS_EVSPLATFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSPLATI, PPC_INS_EVSPLATI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSRWIS, PPC_INS_EVSRWIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSRWIU, PPC_INS_EVSRWIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSRWS, PPC_INS_EVSRWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSRWU, PPC_INS_EVSRWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTDD, PPC_INS_EVSTDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTDDX, PPC_INS_EVSTDDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTDH, PPC_INS_EVSTDH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTDHX, PPC_INS_EVSTDHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTDW, PPC_INS_EVSTDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTDWX, PPC_INS_EVSTDWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWHE, PPC_INS_EVSTWHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWHEX, PPC_INS_EVSTWHEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWHO, PPC_INS_EVSTWHO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWHOX, PPC_INS_EVSTWHOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWWE, PPC_INS_EVSTWWE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWWEX, PPC_INS_EVSTWWEX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWWO, PPC_INS_EVSTWWO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSTWWOX, PPC_INS_EVSTWWOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSUBFSMIAAW, PPC_INS_EVSUBFSMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSUBFSSIAAW, PPC_INS_EVSUBFSSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSUBFUMIAAW, PPC_INS_EVSUBFUMIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSUBFUSIAAW, PPC_INS_EVSUBFUSIAAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSUBFW, PPC_INS_EVSUBFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVSUBIFW, PPC_INS_EVSUBIFW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EVXOR, PPC_INS_EVXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_SPE, 0 }, 0, 0 #endif }, { PPC_EXTSB, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSB8, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSB8_32_64, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSB8o, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSBo, PPC_INS_EXTSB, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSH, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSH8, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSH8_32_64, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSH8o, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSHo, PPC_INS_EXTSH, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSW, PPC_INS_EXTSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSWSLI, PPC_INS_EXTSWSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSWSLIo, PPC_INS_EXTSWSLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSW_32_64, PPC_INS_EXTSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSW_32_64o, PPC_INS_EXTSW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EXTSWo, PPC_INS_EXTSW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_EnforceIEIO, PPC_INS_EIEIO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FABSD, PPC_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FABSDo, PPC_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FABSS, PPC_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FABSSo, PPC_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FADD, PPC_INS_FADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FADDS, PPC_INS_FADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FADDSo, PPC_INS_FADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FADDo, PPC_INS_FADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFID, PPC_INS_FCFID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDS, PPC_INS_FCFIDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDSo, PPC_INS_FCFIDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDU, PPC_INS_FCFIDU, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDUS, PPC_INS_FCFIDUS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDUSo, PPC_INS_FCFIDUS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDUo, PPC_INS_FCFIDU, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCFIDo, PPC_INS_FCFID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCMPUD, PPC_INS_FCMPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCMPUS, PPC_INS_FCMPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCPSGND, PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCPSGNDo, PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCPSGNS, PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCPSGNSo, PPC_INS_FCPSGN, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTID, PPC_INS_FCTID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDU, PPC_INS_FCTIDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDUZ, PPC_INS_FCTIDUZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDUZo, PPC_INS_FCTIDUZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDUo, PPC_INS_FCTIDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDZ, PPC_INS_FCTIDZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDZo, PPC_INS_FCTIDZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIDo, PPC_INS_FCTID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIW, PPC_INS_FCTIW, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWU, PPC_INS_FCTIWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWUZ, PPC_INS_FCTIWUZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWUZo, PPC_INS_FCTIWUZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWUo, PPC_INS_FCTIWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWZ, PPC_INS_FCTIWZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWZo, PPC_INS_FCTIWZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FCTIWo, PPC_INS_FCTIW, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FDIV, PPC_INS_FDIV, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FDIVS, PPC_INS_FDIVS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FDIVSo, PPC_INS_FDIVS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FDIVo, PPC_INS_FDIV, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMADD, PPC_INS_FMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMADDS, PPC_INS_FMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMADDSo, PPC_INS_FMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMADDo, PPC_INS_FMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMR, PPC_INS_FMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMRo, PPC_INS_FMR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMSUB, PPC_INS_FMSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMSUBS, PPC_INS_FMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMSUBSo, PPC_INS_FMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMSUBo, PPC_INS_FMSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMUL, PPC_INS_FMUL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMULS, PPC_INS_FMULS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FMULSo, PPC_INS_FMULS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FMULo, PPC_INS_FMUL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNABSD, PPC_INS_FNABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNABSDo, PPC_INS_FNABS, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNABSS, PPC_INS_FNABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNABSSo, PPC_INS_FNABS, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNEGD, PPC_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNEGDo, PPC_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNEGS, PPC_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNEGSo, PPC_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMADD, PPC_INS_FNMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMADDS, PPC_INS_FNMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMADDSo, PPC_INS_FNMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMADDo, PPC_INS_FNMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMSUB, PPC_INS_FNMSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMSUBS, PPC_INS_FNMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMSUBSo, PPC_INS_FNMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FNMSUBo, PPC_INS_FNMSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRE, PPC_INS_FRE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRES, PPC_INS_FRES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRESo, PPC_INS_FRES, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FREo, PPC_INS_FRE, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIMD, PPC_INS_FRIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIMDo, PPC_INS_FRIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIMS, PPC_INS_FRIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIMSo, PPC_INS_FRIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIND, PPC_INS_FRIN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRINDo, PPC_INS_FRIN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRINS, PPC_INS_FRIN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRINSo, PPC_INS_FRIN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIPD, PPC_INS_FRIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIPDo, PPC_INS_FRIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIPS, PPC_INS_FRIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIPSo, PPC_INS_FRIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIZD, PPC_INS_FRIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIZDo, PPC_INS_FRIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIZS, PPC_INS_FRIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRIZSo, PPC_INS_FRIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRSP, PPC_INS_FRSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRSPo, PPC_INS_FRSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRSQRTE, PPC_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRSQRTES, PPC_INS_FRSQRTES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FRSQRTESo, PPC_INS_FRSQRTES, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FRSQRTEo, PPC_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FSELD, PPC_INS_FSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FSELDo, PPC_INS_FSEL, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FSELS, PPC_INS_FSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FSELSo, PPC_INS_FSEL, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FSQRT, PPC_INS_FSQRT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FSQRTS, PPC_INS_FSQRTS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FSQRTSo, PPC_INS_FSQRTS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FSQRTo, PPC_INS_FSQRT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FSUB, PPC_INS_FSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FSUBS, PPC_INS_FSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FSUBSo, PPC_INS_FSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FSUBo, PPC_INS_FSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_FTDIV, PPC_INS_FTDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_FTSQRT, PPC_INS_FTSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_HRFID, PPC_INS_HRFID, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ICBI, PPC_INS_ICBI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ICBIEP, PPC_INS_ICBIEP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ICBLC, PPC_INS_ICBLC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ICBLQ, PPC_INS_ICBLQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ICBT, PPC_INS_ICBT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ICBT, 0 }, 0, 0 #endif }, { PPC_ICBTLS, PPC_INS_ICBTLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ICCCI, PPC_INS_ICCCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_ISEL, PPC_INS_ISEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ISEL8, PPC_INS_ISEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ISYNC, PPC_INS_ISYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LA, PPC_INS_LA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBARX, PPC_INS_LBARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBARXL, PPC_INS_LBARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBEPX, PPC_INS_LBEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZ, PPC_INS_LBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZ8, PPC_INS_LBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZCIX, PPC_INS_LBZCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZU, PPC_INS_LBZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZU8, PPC_INS_LBZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZUX, PPC_INS_LBZUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZUX8, PPC_INS_LBZUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZX, PPC_INS_LBZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZX8, PPC_INS_LBZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LBZXTLS_, PPC_INS_LBZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LD, PPC_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDARX, PPC_INS_LDARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDARXL, PPC_INS_LDARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDAT, PPC_INS_LDAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDBRX, PPC_INS_LDBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDCIX, PPC_INS_LDCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDMX, PPC_INS_LDMX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDU, PPC_INS_LDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDUX, PPC_INS_LDUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDX, PPC_INS_LDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LDXTLS_, PPC_INS_LDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFD, PPC_INS_LFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFDEPX, PPC_INS_LFDEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFDU, PPC_INS_LFDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFDUX, PPC_INS_LFDUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFDX, PPC_INS_LFDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFIWAX, PPC_INS_LFIWAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFIWZX, PPC_INS_LFIWZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFS, PPC_INS_LFS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFSU, PPC_INS_LFSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFSUX, PPC_INS_LFSUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LFSX, PPC_INS_LFSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHA, PPC_INS_LHA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHA8, PPC_INS_LHA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHARX, PPC_INS_LHARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHARXL, PPC_INS_LHARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHAU, PPC_INS_LHAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHAU8, PPC_INS_LHAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHAUX, PPC_INS_LHAUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHAUX8, PPC_INS_LHAUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHAX, PPC_INS_LHAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHAX8, PPC_INS_LHAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHBRX, PPC_INS_LHBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHBRX8, PPC_INS_LHBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHEPX, PPC_INS_LHEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZ, PPC_INS_LHZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZ8, PPC_INS_LHZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZCIX, PPC_INS_LHZCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZU, PPC_INS_LHZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZU8, PPC_INS_LHZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZUX, PPC_INS_LHZUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZUX8, PPC_INS_LHZUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZX, PPC_INS_LHZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZX8, PPC_INS_LHZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LHZXTLS_, PPC_INS_LHZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LI, PPC_INS_LI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LI8, PPC_INS_LI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LIS, PPC_INS_LIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LIS8, PPC_INS_LIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LMW, PPC_INS_LMW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LSWI, PPC_INS_LSWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LVEBX, PPC_INS_LVEBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LVEHX, PPC_INS_LVEHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LVEWX, PPC_INS_LVEWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LVSL, PPC_INS_LVSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LVSR, PPC_INS_LVSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LVX, PPC_INS_LVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LVXL, PPC_INS_LVXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_LWA, PPC_INS_LWA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWARX, PPC_INS_LWARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWARXL, PPC_INS_LWARX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWAT, PPC_INS_LWAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWAUX, PPC_INS_LWAUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWAX, PPC_INS_LWAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWAX_32, PPC_INS_LWAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWA_32, PPC_INS_LWA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWBRX, PPC_INS_LWBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWBRX8, PPC_INS_LWBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWEPX, PPC_INS_LWEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZ, PPC_INS_LWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZ8, PPC_INS_LWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZCIX, PPC_INS_LWZCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZU, PPC_INS_LWZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZU8, PPC_INS_LWZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZUX, PPC_INS_LWZUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZUX8, PPC_INS_LWZUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZX, PPC_INS_LWZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZX8, PPC_INS_LWZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LWZXTLS_, PPC_INS_LWZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSD, PPC_INS_LXSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSDX, PPC_INS_LXSDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_LXSIBZX, PPC_INS_LXSIBZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSIHZX, PPC_INS_LXSIHZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSIWAX, PPC_INS_LXSIWAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSIWZX, PPC_INS_LXSIWZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSSP, PPC_INS_LXSSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXSSPX, PPC_INS_LXSSPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXV, PPC_INS_LXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXVB16X, PPC_INS_LXVB16X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXVD2X, PPC_INS_LXVD2X, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_LXVDSX, PPC_INS_LXVDSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_LXVH8X, PPC_INS_LXVH8X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXVL, PPC_INS_LXVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXVLL, PPC_INS_LXVLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXVW4X, PPC_INS_LXVW4X, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_LXVWSX, PPC_INS_LXVWSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_LXVX, PPC_INS_LXVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MADDHD, PPC_INS_MADDHD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MADDHDU, PPC_INS_MADDHDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MADDLD, PPC_INS_MADDLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MBAR, PPC_INS_MBAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_MCRF, PPC_INS_MCRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MCRFS, PPC_INS_MCRFS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MCRXRX, PPC_INS_MCRXRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFBHRBE, PPC_INS_MFBHRBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFCR, PPC_INS_MFCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFCR8, PPC_INS_MFCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFCTR, PPC_INS_MFCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFCTR8, PPC_INS_MFCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFDCR, PPC_INS_MFBR0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_MFFS, PPC_INS_MFFS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSCDRN, PPC_INS_MFFSCDRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSCDRNI, PPC_INS_MFFSCDRNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSCE, PPC_INS_MFFSCE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSCRN, PPC_INS_MFFSCRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSCRNI, PPC_INS_MFFSCRNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSL, PPC_INS_MFFSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFFSo, PPC_INS_MFFS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR1, 0 }, { 0 }, 0, 0 #endif }, { PPC_MFLR, PPC_INS_MFLR, #ifndef CAPSTONE_DIET { PPC_REG_LR, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFLR8, PPC_INS_MFLR, #ifndef CAPSTONE_DIET { PPC_REG_LR8, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFMSR, PPC_INS_MFMSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFOCRF, PPC_INS_MFOCRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFOCRF8, PPC_INS_MFOCRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFPMR, PPC_INS_MFPMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFSPR, PPC_INS_MFAMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFSR, PPC_INS_MFSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFSRIN, PPC_INS_MFSRIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFTB, PPC_INS_MFTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFTB8, PPC_INS_MFSPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFVRD, PPC_INS_MFVRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFVRSAVE, PPC_INS_MFVRSAVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFVRSAVEv, PPC_INS_MFSPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFVSCR, PPC_INS_MFVSCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_MFVSRD, PPC_INS_MFFPRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFVSRLD, PPC_INS_MFVSRLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MFVSRWZ, PPC_INS_MFVSRWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MODSD, PPC_INS_MODSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MODSW, PPC_INS_MODSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MODUD, PPC_INS_MODUD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MODUW, PPC_INS_MODUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MSGSYNC, PPC_INS_MSGSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MSYNC, PPC_INS_MSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTCRF, PPC_INS_MTCRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTCRF8, PPC_INS_MTCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTCTR, PPC_INS_MTCTR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTCTR8, PPC_INS_MTCTR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTCTR8loop, PPC_INS_MTCTR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CTR8, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTCTRloop, PPC_INS_MTCTR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CTR, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTDCR, PPC_INS_MTBR0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_MTFSB0, PPC_INS_MTFSB0, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTFSB1, PPC_INS_MTFSB1, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTFSF, PPC_INS_MTFSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTFSFI, PPC_INS_MTFSFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTFSFIo, PPC_INS_MTFSFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTFSFb, PPC_INS_MTFSF, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_RM, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTFSFo, PPC_INS_MTFSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTLR, PPC_INS_MTLR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTLR8, PPC_INS_MTLR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_LR8, 0 }, { 0 }, 0, 0 #endif }, { PPC_MTMSR, PPC_INS_MTMSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTMSRD, PPC_INS_MTMSRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTOCRF, PPC_INS_MTOCRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTOCRF8, PPC_INS_MTOCRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTPMR, PPC_INS_MTPMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTSPR, PPC_INS_MTAMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTSR, PPC_INS_MTSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTSRIN, PPC_INS_MTSRIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVRSAVE, PPC_INS_MTVRSAVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVRSAVEv, PPC_INS_MTSPR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVSCR, PPC_INS_MTVSCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_MTVSRD, PPC_INS_MTVSRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVSRDD, PPC_INS_MTVSRDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVSRWA, PPC_INS_MTVSRWA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVSRWS, PPC_INS_MTVSRWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MTVSRWZ, PPC_INS_MTVSRWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHD, PPC_INS_MULHD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHDU, PPC_INS_MULHDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHDUo, PPC_INS_MULHDU, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHDo, PPC_INS_MULHD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHW, PPC_INS_MULHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHWU, PPC_INS_MULHWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHWUo, PPC_INS_MULHWU, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_MULHWo, PPC_INS_MULHW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_MULLD, PPC_INS_MULLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULLDo, PPC_INS_MULLD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_MULLI, PPC_INS_MULLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULLI8, PPC_INS_MULLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULLW, PPC_INS_MULLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_MULLWo, PPC_INS_MULLW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_NAND, PPC_INS_NAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NAND8, PPC_INS_NAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NAND8o, PPC_INS_NAND, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_NANDo, PPC_INS_NAND, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_NAP, PPC_INS_NAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NEG, PPC_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NEG8, PPC_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NEG8o, PPC_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_NEGo, PPC_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_NOP, PPC_INS_NOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NOP_GT_PWR6, PPC_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NOP_GT_PWR7, PPC_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NOR, PPC_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NOR8, PPC_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_NOR8o, PPC_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_NORo, PPC_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_OR, PPC_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_OR8, PPC_INS_MR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_OR8o, PPC_INS_MR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ORC, PPC_INS_ORC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ORC8, PPC_INS_ORC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ORC8o, PPC_INS_ORC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ORCo, PPC_INS_ORC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_ORI, PPC_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ORI8, PPC_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ORIS, PPC_INS_ORIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ORIS8, PPC_INS_ORIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_ORo, PPC_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_POPCNTB, PPC_INS_POPCNTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_POPCNTD, PPC_INS_POPCNTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_POPCNTW, PPC_INS_POPCNTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_QVALIGNI, PPC_INS_QVALIGNI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVALIGNIb, PPC_INS_QVALIGNI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVALIGNIs, PPC_INS_QVALIGNI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVESPLATI, PPC_INS_QVESPLATI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVESPLATIb, PPC_INS_QVESPLATI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVESPLATIs, PPC_INS_QVESPLATI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFABS, PPC_INS_QVFABS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFABSs, PPC_INS_QVFABS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFADD, PPC_INS_QVFADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFADDS, PPC_INS_QVFADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFADDSs, PPC_INS_QVFADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCFID, PPC_INS_QVFCFID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCFIDS, PPC_INS_QVFCFIDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCFIDU, PPC_INS_QVFCFIDU, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCFIDUS, PPC_INS_QVFCFIDUS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCFIDb, PPC_INS_QVFCFID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPEQ, PPC_INS_QVFCMPEQ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPEQb, PPC_INS_QVFCMPEQ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPEQbs, PPC_INS_QVFCMPEQ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPGT, PPC_INS_QVFCMPGT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPGTb, PPC_INS_QVFCMPGT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPGTbs, PPC_INS_QVFCMPGT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPLT, PPC_INS_QVFCMPLT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPLTb, PPC_INS_QVFCMPLT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCMPLTbs, PPC_INS_QVFCMPLT, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCPSGN, PPC_INS_QVFCPSGN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCPSGNs, PPC_INS_QVFCPSGN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTID, PPC_INS_QVFCTID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIDU, PPC_INS_QVFCTIDU, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIDUZ, PPC_INS_QVFCTIDUZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIDZ, PPC_INS_QVFCTIDZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIDb, PPC_INS_QVFCTID, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIW, PPC_INS_QVFCTIW, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIWU, PPC_INS_QVFCTIWU, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIWUZ, PPC_INS_QVFCTIWUZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFCTIWZ, PPC_INS_QVFCTIWZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFLOGICAL, PPC_INS_QVFLOGICAL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFLOGICALb, PPC_INS_QVFAND, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFLOGICALs, PPC_INS_QVFLOGICAL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMADD, PPC_INS_QVFMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMADDS, PPC_INS_QVFMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMADDSs, PPC_INS_QVFMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMR, PPC_INS_QVFMR, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMRb, PPC_INS_QVFMR, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMRs, PPC_INS_QVFMR, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMSUB, PPC_INS_QVFMSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMSUBS, PPC_INS_QVFMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMSUBSs, PPC_INS_QVFMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMUL, PPC_INS_QVFMUL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMULS, PPC_INS_QVFMULS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFMULSs, PPC_INS_QVFMULS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNABS, PPC_INS_QVFNABS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNABSs, PPC_INS_QVFNABS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNEG, PPC_INS_QVFNEG, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNEGs, PPC_INS_QVFNEG, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNMADD, PPC_INS_QVFNMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNMADDS, PPC_INS_QVFNMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNMADDSs, PPC_INS_QVFNMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNMSUB, PPC_INS_QVFNMSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNMSUBS, PPC_INS_QVFNMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFNMSUBSs, PPC_INS_QVFNMSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFPERM, PPC_INS_QVFPERM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFPERMs, PPC_INS_QVFPERM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRE, PPC_INS_QVFRE, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRES, PPC_INS_QVFRES, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRESs, PPC_INS_QVFRES, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIM, PPC_INS_QVFRIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIMs, PPC_INS_QVFRIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIN, PPC_INS_QVFRIN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRINs, PPC_INS_QVFRIN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIP, PPC_INS_QVFRIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIPs, PPC_INS_QVFRIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIZ, PPC_INS_QVFRIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRIZs, PPC_INS_QVFRIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRSP, PPC_INS_QVFRSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRSPs, PPC_INS_QVFRSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRSQRTE, PPC_INS_QVFRSQRTE, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRSQRTES, PPC_INS_QVFRSQRTES, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFRSQRTESs, PPC_INS_QVFRSQRTES, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSEL, PPC_INS_QVFSEL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSELb, PPC_INS_QVFSEL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSELbb, PPC_INS_QVFSEL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSELbs, PPC_INS_QVFSEL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSUB, PPC_INS_QVFSUB, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSUBS, PPC_INS_QVFSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFSUBSs, PPC_INS_QVFSUBS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFTSTNAN, PPC_INS_QVFTSTNAN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFTSTNANb, PPC_INS_QVFTSTNAN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFTSTNANbs, PPC_INS_QVFTSTNAN, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXMADD, PPC_INS_QVFXMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXMADDS, PPC_INS_QVFXMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXMUL, PPC_INS_QVFXMUL, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXMULS, PPC_INS_QVFXMULS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXXCPNMADD, PPC_INS_QVFXXCPNMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXXCPNMADDS, PPC_INS_QVFXXCPNMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXXMADD, PPC_INS_QVFXXMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXXMADDS, PPC_INS_QVFXXMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXXNPMADD, PPC_INS_QVFXXNPMADD, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVFXXNPMADDS, PPC_INS_QVFXXNPMADDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVGPCI, PPC_INS_QVGPCI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCDUX, PPC_INS_QVLFCDUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCDUXA, PPC_INS_QVLFCDUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCDX, PPC_INS_QVLFCDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCDXA, PPC_INS_QVLFCDXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCSUX, PPC_INS_QVLFCSUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCSUXA, PPC_INS_QVLFCSUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCSX, PPC_INS_QVLFCSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCSXA, PPC_INS_QVLFCSXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFCSXs, PPC_INS_QVLFCSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFDUX, PPC_INS_QVLFDUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFDUXA, PPC_INS_QVLFDUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFDX, PPC_INS_QVLFDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFDXA, PPC_INS_QVLFDXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFDXb, PPC_INS_QVLFDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFIWAX, PPC_INS_QVLFIWAX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFIWAXA, PPC_INS_QVLFIWAXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFIWZX, PPC_INS_QVLFIWZX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFIWZXA, PPC_INS_QVLFIWZXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFSUX, PPC_INS_QVLFSUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFSUXA, PPC_INS_QVLFSUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFSX, PPC_INS_QVLFSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFSXA, PPC_INS_QVLFSXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFSXb, PPC_INS_QVLFSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLFSXs, PPC_INS_QVLFSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLPCLDX, PPC_INS_QVLPCLDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLPCLSX, PPC_INS_QVLPCLSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLPCLSXint, PPC_INS_QVLPCLSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLPCRDX, PPC_INS_QVLPCRDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVLPCRSX, PPC_INS_QVLPCRSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDUX, PPC_INS_QVSTFCDUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDUXA, PPC_INS_QVSTFCDUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDUXI, PPC_INS_QVSTFCDUXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDUXIA, PPC_INS_QVSTFCDUXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDX, PPC_INS_QVSTFCDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDXA, PPC_INS_QVSTFCDXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDXI, PPC_INS_QVSTFCDXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCDXIA, PPC_INS_QVSTFCDXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSUX, PPC_INS_QVSTFCSUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSUXA, PPC_INS_QVSTFCSUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSUXI, PPC_INS_QVSTFCSUXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSUXIA, PPC_INS_QVSTFCSUXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSX, PPC_INS_QVSTFCSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSXA, PPC_INS_QVSTFCSXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSXI, PPC_INS_QVSTFCSXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSXIA, PPC_INS_QVSTFCSXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFCSXs, PPC_INS_QVSTFCSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDUX, PPC_INS_QVSTFDUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDUXA, PPC_INS_QVSTFDUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDUXI, PPC_INS_QVSTFDUXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDUXIA, PPC_INS_QVSTFDUXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDX, PPC_INS_QVSTFDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDXA, PPC_INS_QVSTFDXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDXI, PPC_INS_QVSTFDXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDXIA, PPC_INS_QVSTFDXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFDXb, PPC_INS_QVSTFDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFIWX, PPC_INS_QVSTFIWX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFIWXA, PPC_INS_QVSTFIWXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSUX, PPC_INS_QVSTFSUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSUXA, PPC_INS_QVSTFSUXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSUXI, PPC_INS_QVSTFSUXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSUXIA, PPC_INS_QVSTFSUXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSUXs, PPC_INS_QVSTFSUX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSX, PPC_INS_QVSTFSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSXA, PPC_INS_QVSTFSXA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSXI, PPC_INS_QVSTFSXI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSXIA, PPC_INS_QVSTFSXIA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_QVSTFSXs, PPC_INS_QVSTFSX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_QPX, 0 }, 0, 0 #endif }, { PPC_RFCI, PPC_INS_RFCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_RFDI, PPC_INS_RFDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_E500, 0 }, 0, 0 #endif }, { PPC_RFEBB, PPC_INS_RFEBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RFI, PPC_INS_RFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_RFID, PPC_INS_RFID, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RFMCI, PPC_INS_RFMCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_E500, 0 }, 0, 0 #endif }, { PPC_RLDCL, PPC_INS_RLDCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDCLo, PPC_INS_RLDCL, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDCR, PPC_INS_RLDCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDCRo, PPC_INS_RLDCR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDIC, PPC_INS_RLDIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDICL, PPC_INS_CLRLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDICL_32_64, PPC_INS_CLRLDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDICLo, PPC_INS_CLRLDI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDICR, PPC_INS_RLDICR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDICRo, PPC_INS_RLDICR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDICo, PPC_INS_RLDIC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDIMI, PPC_INS_RLDIMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLDIMIo, PPC_INS_RLDIMI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWIMI, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWIMI8, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWIMI8o, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWIMIo, PPC_INS_RLWIMI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWINM, PPC_INS_CLRLWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWINM8, PPC_INS_RLWINM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWINM8o, PPC_INS_RLWINM, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWINMo, PPC_INS_CLRLWI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWNM, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWNM8, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWNM8o, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_RLWNMo, PPC_INS_RLWNM, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SC, PPC_INS_SC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SETB, PPC_INS_SETB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBIA, PPC_INS_SLBIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBIE, PPC_INS_SLBIE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBIEG, PPC_INS_SLBIEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBMFEE, PPC_INS_SLBMFEE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBMFEV, PPC_INS_SLBMFEV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBMTE, PPC_INS_SLBMTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLBSYNC, PPC_INS_SLBSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLD, PPC_INS_SLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLDo, PPC_INS_SLD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SLW, PPC_INS_SLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLW8, PPC_INS_SLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SLW8o, PPC_INS_SLW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SLWo, PPC_INS_SLW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SPELWZ, PPC_INS_LWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SPELWZX, PPC_INS_LWZX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SPESTW, PPC_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SPESTWX, PPC_INS_STWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRAD, PPC_INS_SRAD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRADI, PPC_INS_SRADI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRADIo, PPC_INS_SRADI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRADo, PPC_INS_SRAD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRAW, PPC_INS_SRAW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRAWI, PPC_INS_SRAWI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRAWIo, PPC_INS_SRAWI, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRAWo, PPC_INS_SRAW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRD, PPC_INS_SRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRDo, PPC_INS_SRD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRW, PPC_INS_SRW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRW8, PPC_INS_SRW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SRW8o, PPC_INS_SRW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SRWo, PPC_INS_SRW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_STB, PPC_INS_STB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STB8, PPC_INS_STB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBCIX, PPC_INS_STBCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBCX, PPC_INS_STBCX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBEPX, PPC_INS_STBEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBU, PPC_INS_STBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBU8, PPC_INS_STBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBUX, PPC_INS_STBUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBUX8, PPC_INS_STBUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBX, PPC_INS_STBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBX8, PPC_INS_STBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STBXTLS_, PPC_INS_STBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STD, PPC_INS_STD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDAT, PPC_INS_STDAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDBRX, PPC_INS_STDBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDCIX, PPC_INS_STDCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDCX, PPC_INS_STDCX, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_STDU, PPC_INS_STDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDUX, PPC_INS_STDUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDX, PPC_INS_STDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STDXTLS_, PPC_INS_STDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFD, PPC_INS_STFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFDEPX, PPC_INS_STFDEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFDU, PPC_INS_STFDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFDUX, PPC_INS_STFDUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFDX, PPC_INS_STFDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFIWX, PPC_INS_STFIWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFS, PPC_INS_STFS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFSU, PPC_INS_STFSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFSUX, PPC_INS_STFSUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STFSX, PPC_INS_STFSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STH, PPC_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STH8, PPC_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHBRX, PPC_INS_STHBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHCIX, PPC_INS_STHCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHCX, PPC_INS_STHCX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHEPX, PPC_INS_STHEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHU, PPC_INS_STHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHU8, PPC_INS_STHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHUX, PPC_INS_STHUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHUX8, PPC_INS_STHUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHX, PPC_INS_STHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHX8, PPC_INS_STHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STHXTLS_, PPC_INS_STHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STMW, PPC_INS_STMW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STOP, PPC_INS_STOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STSWI, PPC_INS_STSWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STVEBX, PPC_INS_STVEBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_STVEHX, PPC_INS_STVEHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_STVEWX, PPC_INS_STVEWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_STVX, PPC_INS_STVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_STVXL, PPC_INS_STVXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_STW, PPC_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STW8, PPC_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWAT, PPC_INS_STWAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWBRX, PPC_INS_STWBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWCIX, PPC_INS_STWCIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWCX, PPC_INS_STWCX, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_STWEPX, PPC_INS_STWEPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWU, PPC_INS_STWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWU8, PPC_INS_STWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWUX, PPC_INS_STWUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWUX8, PPC_INS_STWUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWX, PPC_INS_STWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWX8, PPC_INS_STWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STWXTLS_, PPC_INS_STWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXSD, PPC_INS_STXSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXSDX, PPC_INS_STXSDX, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_STXSIBX, PPC_INS_STXSIBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXSIHX, PPC_INS_STXSIHX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXSIWX, PPC_INS_STXSIWX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXSSP, PPC_INS_STXSSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXSSPX, PPC_INS_STXSSPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXV, PPC_INS_STXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXVB16X, PPC_INS_STXVB16X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXVD2X, PPC_INS_STXVD2X, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_STXVH8X, PPC_INS_STXVH8X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXVL, PPC_INS_STXVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXVLL, PPC_INS_STXVLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_STXVW4X, PPC_INS_STXVW4X, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_STXVX, PPC_INS_STXVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBF, PPC_INS_SUBF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBF8, PPC_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBF8o, PPC_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFC, PPC_INS_SUBFC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFC8, PPC_INS_SUBC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFC8o, PPC_INS_SUBC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFCo, PPC_INS_SUBFC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFE, PPC_INS_SUBFE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFE8, PPC_INS_SUBFE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFE8o, PPC_INS_SUBFE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFEo, PPC_INS_SUBFE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFIC, PPC_INS_SUBFIC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFIC8, PPC_INS_SUBFIC, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFME, PPC_INS_SUBFME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFME8, PPC_INS_SUBFME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFME8o, PPC_INS_SUBFME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFMEo, PPC_INS_SUBFME, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFZE, PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFZE8, PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFZE8o, PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFZEo, PPC_INS_SUBFZE, #ifndef CAPSTONE_DIET { PPC_REG_CARRY, 0 }, { PPC_REG_CARRY, PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SUBFo, PPC_INS_SUBF, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_SYNC, PPC_INS_LWSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TABORT, PPC_INS_TABORT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TABORTDC, PPC_INS_TABORTDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TABORTDCI, PPC_INS_TABORTDCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TABORTWC, PPC_INS_TABORTWC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TABORTWCI, PPC_INS_TABORTWCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TAILB, PPC_INS_B, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_TAILB8, PPC_INS_B, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_TAILBA, PPC_INS_BA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_TAILBA8, PPC_INS_BA, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_TAILBCTR, PPC_INS_BCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE32, 0 }, 1, 1 #endif }, { PPC_TAILBCTR8, PPC_INS_BCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR8, PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1 #endif }, { PPC_TBEGIN, PPC_INS_TBEGIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TCHECK, PPC_INS_TCHECK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TD, PPC_INS_TD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TDI, PPC_INS_TDEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TEND, PPC_INS_TEND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TLBIA, PPC_INS_TLBIA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TLBIE, PPC_INS_TLBIE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TLBIEL, PPC_INS_TLBIEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TLBIVAX, PPC_INS_TLBIVAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_TLBLD, PPC_INS_TLBLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC6XX, 0 }, 0, 0 #endif }, { PPC_TLBLI, PPC_INS_TLBLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC6XX, 0 }, 0, 0 #endif }, { PPC_TLBRE, PPC_INS_TLBRE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_TLBRE2, PPC_INS_TLBRE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_TLBSX, PPC_INS_TLBSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_TLBSX2, PPC_INS_TLBSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_TLBSX2D, PPC_INS_TLBSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_TLBSYNC, PPC_INS_TLBSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TLBWE, PPC_INS_TLBWE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_TLBWE2, PPC_INS_TLBWE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_PPC4XX, 0 }, 0, 0 #endif }, { PPC_TRAP, PPC_INS_TRAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TRECHKPT, PPC_INS_TRECHKPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TRECLAIM, PPC_INS_TRECLAIM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TSR, PPC_INS_TSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TW, PPC_INS_TW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_TWI, PPC_INS_TWEQI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VABSDUB, PPC_INS_VABSDUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VABSDUH, PPC_INS_VABSDUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VABSDUW, PPC_INS_VABSDUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VADDCUQ, PPC_INS_VADDCUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VADDCUW, PPC_INS_VADDCUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDECUQ, PPC_INS_VADDECUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VADDEUQM, PPC_INS_VADDEUQM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VADDFP, PPC_INS_VADDFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDSBS, PPC_INS_VADDSBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDSHS, PPC_INS_VADDSHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDSWS, PPC_INS_VADDSWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUBM, PPC_INS_VADDUBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUBS, PPC_INS_VADDUBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUDM, PPC_INS_VADDUDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUHM, PPC_INS_VADDUHM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUHS, PPC_INS_VADDUHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUQM, PPC_INS_VADDUQM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VADDUWM, PPC_INS_VADDUWM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VADDUWS, PPC_INS_VADDUWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAND, PPC_INS_VAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VANDC, PPC_INS_VANDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAVGSB, PPC_INS_VAVGSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAVGSH, PPC_INS_VAVGSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAVGSW, PPC_INS_VAVGSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAVGUB, PPC_INS_VAVGUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAVGUH, PPC_INS_VAVGUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VAVGUW, PPC_INS_VAVGUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VBPERMD, PPC_INS_VBPERMD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VBPERMQ, PPC_INS_VBPERMQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCFSX, PPC_INS_VCFSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCFSX_0, PPC_INS_VCFSX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCFUX, PPC_INS_VCFUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCFUX_0, PPC_INS_VCFUX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCIPHER, PPC_INS_VCIPHER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCIPHERLAST, PPC_INS_VCIPHERLAST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCLZB, PPC_INS_VCLZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCLZD, PPC_INS_VCLZD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCLZH, PPC_INS_VCLZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCLZLSBB, PPC_INS_VCLZLSBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCLZW, PPC_INS_VCLZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPBFP, PPC_INS_VCMPBFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPBFPo, PPC_INS_VCMPBFP, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQFP, PPC_INS_VCMPEQFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQFPo, PPC_INS_VCMPEQFP, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUB, PPC_INS_VCMPEQUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUBo, PPC_INS_VCMPEQUB, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUD, PPC_INS_VCMPEQUD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUDo, PPC_INS_VCMPEQUD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUH, PPC_INS_VCMPEQUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUHo, PPC_INS_VCMPEQUH, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUW, PPC_INS_VCMPEQUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPEQUWo, PPC_INS_VCMPEQUW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGEFP, PPC_INS_VCMPGEFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGEFPo, PPC_INS_VCMPGEFP, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTFP, PPC_INS_VCMPGTFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTFPo, PPC_INS_VCMPGTFP, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSB, PPC_INS_VCMPGTSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSBo, PPC_INS_VCMPGTSB, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSD, PPC_INS_VCMPGTSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSDo, PPC_INS_VCMPGTSD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSH, PPC_INS_VCMPGTSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSHo, PPC_INS_VCMPGTSH, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSW, PPC_INS_VCMPGTSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTSWo, PPC_INS_VCMPGTSW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUB, PPC_INS_VCMPGTUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUBo, PPC_INS_VCMPGTUB, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUD, PPC_INS_VCMPGTUD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUDo, PPC_INS_VCMPGTUD, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUH, PPC_INS_VCMPGTUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUHo, PPC_INS_VCMPGTUH, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUW, PPC_INS_VCMPGTUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPGTUWo, PPC_INS_VCMPGTUW, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCMPNEB, PPC_INS_VCMPNEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEBo, PPC_INS_VCMPNEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEH, PPC_INS_VCMPNEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEHo, PPC_INS_VCMPNEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEW, PPC_INS_VCMPNEW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEWo, PPC_INS_VCMPNEW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEZB, PPC_INS_VCMPNEZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEZBo, PPC_INS_VCMPNEZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEZH, PPC_INS_VCMPNEZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEZHo, PPC_INS_VCMPNEZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEZW, PPC_INS_VCMPNEZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCMPNEZWo, PPC_INS_VCMPNEZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCTSXS, PPC_INS_VCTSXS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCTSXS_0, PPC_INS_VCTSXS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCTUXS, PPC_INS_VCTUXS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCTUXS_0, PPC_INS_VCTUXS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VCTZB, PPC_INS_VCTZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCTZD, PPC_INS_VCTZD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCTZH, PPC_INS_VCTZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCTZLSBB, PPC_INS_VCTZLSBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VCTZW, PPC_INS_VCTZW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEQV, PPC_INS_VEQV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VEXPTEFP, PPC_INS_VEXPTEFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VEXTRACTD, PPC_INS_VEXTRACTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTRACTUB, PPC_INS_VEXTRACTUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTRACTUH, PPC_INS_VEXTRACTUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTRACTUW, PPC_INS_VEXTRACTUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTSB2D, PPC_INS_VEXTSB2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTSB2W, PPC_INS_VEXTSB2W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTSH2D, PPC_INS_VEXTSH2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTSH2W, PPC_INS_VEXTSH2W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTSW2D, PPC_INS_VEXTSW2D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTUBLX, PPC_INS_VEXTUBLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTUBRX, PPC_INS_VEXTUBRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTUHLX, PPC_INS_VEXTUHLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTUHRX, PPC_INS_VEXTUHRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTUWLX, PPC_INS_VEXTUWLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VEXTUWRX, PPC_INS_VEXTUWRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VGBBD, PPC_INS_VGBBD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VINSERTB, PPC_INS_VINSERTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VINSERTD, PPC_INS_VINSERTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VINSERTH, PPC_INS_VINSERTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VINSERTW, PPC_INS_VINSERTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VLOGEFP, PPC_INS_VLOGEFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMADDFP, PPC_INS_VMADDFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXFP, PPC_INS_VMAXFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXSB, PPC_INS_VMAXSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXSD, PPC_INS_VMAXSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXSH, PPC_INS_VMAXSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXSW, PPC_INS_VMAXSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXUB, PPC_INS_VMAXUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXUD, PPC_INS_VMAXUD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXUH, PPC_INS_VMAXUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMAXUW, PPC_INS_VMAXUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMHADDSHS, PPC_INS_VMHADDSHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMHRADDSHS, PPC_INS_VMHRADDSHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINFP, PPC_INS_VMINFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINSB, PPC_INS_VMINSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINSD, PPC_INS_VMINSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINSH, PPC_INS_VMINSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINSW, PPC_INS_VMINSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINUB, PPC_INS_VMINUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINUD, PPC_INS_VMINUD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMINUH, PPC_INS_VMINUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMINUW, PPC_INS_VMINUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMLADDUHM, PPC_INS_VMLADDUHM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGEW, PPC_INS_VMRGEW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMRGHB, PPC_INS_VMRGHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGHH, PPC_INS_VMRGHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGHW, PPC_INS_VMRGHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGLB, PPC_INS_VMRGLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGLH, PPC_INS_VMRGLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGLW, PPC_INS_VMRGLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMRGOW, PPC_INS_VMRGOW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMSUMMBM, PPC_INS_VMSUMMBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMSUMSHM, PPC_INS_VMSUMSHM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMSUMSHS, PPC_INS_VMSUMSHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMSUMUBM, PPC_INS_VMSUMUBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMSUMUHM, PPC_INS_VMSUMUHM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMSUMUHS, PPC_INS_VMSUMUHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMUL10CUQ, PPC_INS_VMUL10CUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMUL10ECUQ, PPC_INS_VMUL10ECUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMUL10EUQ, PPC_INS_VMUL10EUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMUL10UQ, PPC_INS_VMUL10UQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VMULESB, PPC_INS_VMULESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULESH, PPC_INS_VMULESH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULESW, PPC_INS_VMULESW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULEUB, PPC_INS_VMULEUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULEUH, PPC_INS_VMULEUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULEUW, PPC_INS_VMULEUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULOSB, PPC_INS_VMULOSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULOSH, PPC_INS_VMULOSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULOSW, PPC_INS_VMULOSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULOUB, PPC_INS_VMULOUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULOUH, PPC_INS_VMULOUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULOUW, PPC_INS_VMULOUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VMULUWM, PPC_INS_VMULUWM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VNAND, PPC_INS_VNAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VNCIPHER, PPC_INS_VNCIPHER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VNCIPHERLAST, PPC_INS_VNCIPHERLAST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VNEGD, PPC_INS_VNEGD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VNEGW, PPC_INS_VNEGW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VNMSUBFP, PPC_INS_VNMSUBFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VNOR, PPC_INS_VNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VOR, PPC_INS_VOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VORC, PPC_INS_VORC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPERM, PPC_INS_VPERM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPERMR, PPC_INS_VPERMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPERMXOR, PPC_INS_VPERMXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPKPX, PPC_INS_VPKPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKSDSS, PPC_INS_VPKSDSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPKSDUS, PPC_INS_VPKSDUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPKSHSS, PPC_INS_VPKSHSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKSHUS, PPC_INS_VPKSHUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKSWSS, PPC_INS_VPKSWSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKSWUS, PPC_INS_VPKSWUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKUDUM, PPC_INS_VPKUDUM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPKUDUS, PPC_INS_VPKUDUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPKUHUM, PPC_INS_VPKUHUM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKUHUS, PPC_INS_VPKUHUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKUWUM, PPC_INS_VPKUWUM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPKUWUS, PPC_INS_VPKUWUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPMSUMB, PPC_INS_VPMSUMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPMSUMD, PPC_INS_VPMSUMD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPMSUMH, PPC_INS_VPMSUMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPMSUMW, PPC_INS_VPMSUMW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPOPCNTB, PPC_INS_VPOPCNTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPOPCNTD, PPC_INS_VPOPCNTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPOPCNTH, PPC_INS_VPOPCNTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPOPCNTW, PPC_INS_VPOPCNTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VPRTYBD, PPC_INS_VPRTYBD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPRTYBQ, PPC_INS_VPRTYBQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VPRTYBW, PPC_INS_VPRTYBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VREFP, PPC_INS_VREFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRFIM, PPC_INS_VRFIM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRFIN, PPC_INS_VRFIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRFIP, PPC_INS_VRFIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRFIZ, PPC_INS_VRFIZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRLB, PPC_INS_VRLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRLD, PPC_INS_VRLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRLDMI, PPC_INS_VRLDMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VRLDNM, PPC_INS_VRLDNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VRLH, PPC_INS_VRLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRLW, PPC_INS_VRLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VRLWMI, PPC_INS_VRLWMI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VRLWNM, PPC_INS_VRLWNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VRSQRTEFP, PPC_INS_VRSQRTEFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSBOX, PPC_INS_VSBOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSEL, PPC_INS_VSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSHASIGMAD, PPC_INS_VSHASIGMAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSHASIGMAW, PPC_INS_VSHASIGMAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSL, PPC_INS_VSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSLB, PPC_INS_VSLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSLD, PPC_INS_VSLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSLDOI, PPC_INS_VSLDOI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSLH, PPC_INS_VSLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSLO, PPC_INS_VSLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSLV, PPC_INS_VSLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSLW, PPC_INS_VSLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSPLTB, PPC_INS_VSPLTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSPLTH, PPC_INS_VSPLTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSPLTISB, PPC_INS_VSPLTISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSPLTISH, PPC_INS_VSPLTISH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSPLTISW, PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSPLTW, PPC_INS_VSPLTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSR, PPC_INS_VSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRAB, PPC_INS_VSRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRAD, PPC_INS_VSRAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRAH, PPC_INS_VSRAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRAW, PPC_INS_VSRAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRB, PPC_INS_VSRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRD, PPC_INS_VSRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRH, PPC_INS_VSRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRO, PPC_INS_VSRO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSRV, PPC_INS_VSRV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSRW, PPC_INS_VSRW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBCUQ, PPC_INS_VSUBCUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSUBCUW, PPC_INS_VSUBCUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBECUQ, PPC_INS_VSUBECUQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSUBEUQM, PPC_INS_VSUBEUQM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSUBFP, PPC_INS_VSUBFP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBSBS, PPC_INS_VSUBSBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBSHS, PPC_INS_VSUBSHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBSWS, PPC_INS_VSUBSWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUBM, PPC_INS_VSUBUBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUBS, PPC_INS_VSUBUBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUDM, PPC_INS_VSUBUDM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUHM, PPC_INS_VSUBUHM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUHS, PPC_INS_VSUBUHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUQM, PPC_INS_VSUBUQM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VSUBUWM, PPC_INS_VSUBUWM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUBUWS, PPC_INS_VSUBUWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUM2SWS, PPC_INS_VSUM2SWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUM4SBS, PPC_INS_VSUM4SBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUM4SHS, PPC_INS_VSUM4SHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUM4UBS, PPC_INS_VSUM4UBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VSUMSWS, PPC_INS_VSUMSWS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKHPX, PPC_INS_VUPKHPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKHSB, PPC_INS_VUPKHSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKHSH, PPC_INS_VUPKHSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKHSW, PPC_INS_VUPKHSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VUPKLPX, PPC_INS_VUPKLPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKLSB, PPC_INS_VUPKLSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKLSH, PPC_INS_VUPKLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_VUPKLSW, PPC_INS_VUPKLSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_VXOR, PPC_INS_VXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_V_SET0, PPC_INS_VXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_V_SET0B, PPC_INS_VXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_V_SET0H, PPC_INS_VXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_V_SETALLONES, PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_V_SETALLONESB, PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_V_SETALLONESH, PPC_INS_VSPLTISW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_ALTIVEC, 0 }, 0, 0 #endif }, { PPC_WAIT, PPC_INS_WAIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_WRTEE, PPC_INS_WRTEE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_WRTEEI, PPC_INS_WRTEEI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_BOOKE, 0 }, 0, 0 #endif }, { PPC_XOR, PPC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XOR8, PPC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XOR8o, PPC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_XORI, PPC_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XORI8, PPC_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XORIS, PPC_INS_XORIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XORIS8, PPC_INS_XORIS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XORo, PPC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { PPC_REG_CR0, 0 }, { 0 }, 0, 0 #endif }, { PPC_XSABSDP, PPC_INS_XSABSDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSABSQP, PPC_INS_XSABSQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSADDDP, PPC_INS_XSADDDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSADDQP, PPC_INS_XSADDQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSADDQPO, PPC_INS_XSADDQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSADDSP, PPC_INS_XSADDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPEQDP, PPC_INS_XSCMPEQDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPEXPDP, PPC_INS_XSCMPEXPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPEXPQP, PPC_INS_XSCMPEXPQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPGEDP, PPC_INS_XSCMPGEDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPGTDP, PPC_INS_XSCMPGTDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPODP, PPC_INS_XSCMPODP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCMPOQP, PPC_INS_XSCMPOQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCMPUDP, PPC_INS_XSCMPUDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCMPUQP, PPC_INS_XSCMPUQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCPSGNDP, PPC_INS_XSCPSGNDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCPSGNQP, PPC_INS_XSCPSGNQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVDPHP, PPC_INS_XSCVDPHP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVDPQP, PPC_INS_XSCVDPQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVDPSP, PPC_INS_XSCVDPSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVDPSPN, PPC_INS_XSCVDPSPN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVDPSXDS, PPC_INS_XSCVDPSXDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVDPSXWS, PPC_INS_XSCVDPSXWS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVDPUXDS, PPC_INS_XSCVDPUXDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVDPUXWS, PPC_INS_XSCVDPUXWS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVHPDP, PPC_INS_XSCVHPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVQPDP, PPC_INS_XSCVQPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVQPDPO, PPC_INS_XSCVQPDPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVQPSDZ, PPC_INS_XSCVQPSDZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVQPSWZ, PPC_INS_XSCVQPSWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVQPUDZ, PPC_INS_XSCVQPUDZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVQPUWZ, PPC_INS_XSCVQPUWZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVSDQP, PPC_INS_XSCVSDQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVSPDP, PPC_INS_XSCVSPDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVSPDPN, PPC_INS_XSCVSPDPN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVSXDDP, PPC_INS_XSCVSXDDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVSXDSP, PPC_INS_XSCVSXDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVUDQP, PPC_INS_XSCVUDQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSCVUXDDP, PPC_INS_XSCVUXDDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSCVUXDSP, PPC_INS_XSCVUXDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSDIVDP, PPC_INS_XSDIVDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSDIVQP, PPC_INS_XSDIVQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSDIVQPO, PPC_INS_XSDIVQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSDIVSP, PPC_INS_XSDIVSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSIEXPDP, PPC_INS_XSIEXPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSIEXPQP, PPC_INS_XSIEXPQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMADDADP, PPC_INS_XSMADDADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMADDASP, PPC_INS_XSMADDASP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMADDMDP, PPC_INS_XSMADDMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMADDMSP, PPC_INS_XSMADDMSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMADDQP, PPC_INS_XSMADDQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMADDQPO, PPC_INS_XSMADDQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMAXCDP, PPC_INS_XSMAXCDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMAXDP, PPC_INS_XSMAXDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMAXJDP, PPC_INS_XSMAXJDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMINCDP, PPC_INS_XSMINCDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMINDP, PPC_INS_XSMINDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMINJDP, PPC_INS_XSMINJDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMSUBADP, PPC_INS_XSMSUBADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMSUBASP, PPC_INS_XSMSUBASP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMSUBMDP, PPC_INS_XSMSUBMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMSUBMSP, PPC_INS_XSMSUBMSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMSUBQP, PPC_INS_XSMSUBQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMSUBQPO, PPC_INS_XSMSUBQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMULDP, PPC_INS_XSMULDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSMULQP, PPC_INS_XSMULQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMULQPO, PPC_INS_XSMULQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSMULSP, PPC_INS_XSMULSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNABSDP, PPC_INS_XSNABSDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSNABSQP, PPC_INS_XSNABSQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNEGDP, PPC_INS_XSNEGDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSNEGQP, PPC_INS_XSNEGQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMADDADP, PPC_INS_XSNMADDADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSNMADDASP, PPC_INS_XSNMADDASP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMADDMDP, PPC_INS_XSNMADDMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSNMADDMSP, PPC_INS_XSNMADDMSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMADDQP, PPC_INS_XSNMADDQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMADDQPO, PPC_INS_XSNMADDQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMSUBADP, PPC_INS_XSNMSUBADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSNMSUBASP, PPC_INS_XSNMSUBASP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMSUBMDP, PPC_INS_XSNMSUBMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSNMSUBMSP, PPC_INS_XSNMSUBMSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMSUBQP, PPC_INS_XSNMSUBQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSNMSUBQPO, PPC_INS_XSNMSUBQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSRDPI, PPC_INS_XSRDPI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSRDPIC, PPC_INS_XSRDPIC, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSRDPIM, PPC_INS_XSRDPIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSRDPIP, PPC_INS_XSRDPIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSRDPIZ, PPC_INS_XSRDPIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSREDP, PPC_INS_XSREDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSRESP, PPC_INS_XSRESP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSRQPI, PPC_INS_XSRQPI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSRQPIX, PPC_INS_XSRQPIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSRQPXP, PPC_INS_XSRQPXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSRSP, PPC_INS_XSRSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSRSQRTEDP, PPC_INS_XSRSQRTEDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSRSQRTESP, PPC_INS_XSRSQRTESP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSSQRTDP, PPC_INS_XSSQRTDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSSQRTQP, PPC_INS_XSSQRTQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSSQRTQPO, PPC_INS_XSSQRTQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSSQRTSP, PPC_INS_XSSQRTSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSSUBDP, PPC_INS_XSSUBDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSSUBQP, PPC_INS_XSSUBQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSSUBQPO, PPC_INS_XSSUBQPO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSSUBSP, PPC_INS_XSSUBSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSTDIVDP, PPC_INS_XSTDIVDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSTSQRTDP, PPC_INS_XSTSQRTDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XSTSTDCDP, PPC_INS_XSTSTDCDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSTSTDCQP, PPC_INS_XSTSTDCQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSTSTDCSP, PPC_INS_XSTSTDCSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSXEXPDP, PPC_INS_XSXEXPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSXEXPQP, PPC_INS_XSXEXPQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSXSIGDP, PPC_INS_XSXSIGDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XSXSIGQP, PPC_INS_XSXSIGQP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVABSDP, PPC_INS_XVABSDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVABSSP, PPC_INS_XVABSSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVADDDP, PPC_INS_XVADDDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVADDSP, PPC_INS_XVADDSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPEQDP, PPC_INS_XVCMPEQDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPEQDPo, PPC_INS_XVCMPEQDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPEQSP, PPC_INS_XVCMPEQSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPEQSPo, PPC_INS_XVCMPEQSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGEDP, PPC_INS_XVCMPGEDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGEDPo, PPC_INS_XVCMPGEDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGESP, PPC_INS_XVCMPGESP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGESPo, PPC_INS_XVCMPGESP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGTDP, PPC_INS_XVCMPGTDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGTDPo, PPC_INS_XVCMPGTDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGTSP, PPC_INS_XVCMPGTSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCMPGTSPo, PPC_INS_XVCMPGTSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { PPC_REG_CR6, 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCPSGNDP, PPC_INS_XVCPSGNDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCPSGNSP, PPC_INS_XVCPSGNSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVDPSP, PPC_INS_XVCVDPSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVDPSXDS, PPC_INS_XVCVDPSXDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVDPSXWS, PPC_INS_XVCVDPSXWS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVDPUXDS, PPC_INS_XVCVDPUXDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVDPUXWS, PPC_INS_XVCVDPUXWS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVHPSP, PPC_INS_XVCVHPSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVCVSPDP, PPC_INS_XVCVSPDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSPHP, PPC_INS_XVCVSPHP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVCVSPSXDS, PPC_INS_XVCVSPSXDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSPSXWS, PPC_INS_XVCVSPSXWS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSPUXDS, PPC_INS_XVCVSPUXDS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSPUXWS, PPC_INS_XVCVSPUXWS, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSXDDP, PPC_INS_XVCVSXDDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSXDSP, PPC_INS_XVCVSXDSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSXWDP, PPC_INS_XVCVSXWDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVSXWSP, PPC_INS_XVCVSXWSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVUXDDP, PPC_INS_XVCVUXDDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVUXDSP, PPC_INS_XVCVUXDSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVUXWDP, PPC_INS_XVCVUXWDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVCVUXWSP, PPC_INS_XVCVUXWSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVDIVDP, PPC_INS_XVDIVDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVDIVSP, PPC_INS_XVDIVSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVIEXPDP, PPC_INS_XVIEXPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVIEXPSP, PPC_INS_XVIEXPSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVMADDADP, PPC_INS_XVMADDADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMADDASP, PPC_INS_XVMADDASP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMADDMDP, PPC_INS_XVMADDMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMADDMSP, PPC_INS_XVMADDMSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMAXDP, PPC_INS_XVMAXDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMAXSP, PPC_INS_XVMAXSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMINDP, PPC_INS_XVMINDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMINSP, PPC_INS_XVMINSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMSUBADP, PPC_INS_XVMSUBADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMSUBASP, PPC_INS_XVMSUBASP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMSUBMDP, PPC_INS_XVMSUBMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMSUBMSP, PPC_INS_XVMSUBMSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMULDP, PPC_INS_XVMULDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVMULSP, PPC_INS_XVMULSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNABSDP, PPC_INS_XVNABSDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNABSSP, PPC_INS_XVNABSSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNEGDP, PPC_INS_XVNEGDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNEGSP, PPC_INS_XVNEGSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMADDADP, PPC_INS_XVNMADDADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMADDASP, PPC_INS_XVNMADDASP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMADDMDP, PPC_INS_XVNMADDMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMADDMSP, PPC_INS_XVNMADDMSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMSUBADP, PPC_INS_XVNMSUBADP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMSUBASP, PPC_INS_XVNMSUBASP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMSUBMDP, PPC_INS_XVNMSUBMDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVNMSUBMSP, PPC_INS_XVNMSUBMSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRDPI, PPC_INS_XVRDPI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRDPIC, PPC_INS_XVRDPIC, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRDPIM, PPC_INS_XVRDPIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRDPIP, PPC_INS_XVRDPIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRDPIZ, PPC_INS_XVRDPIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVREDP, PPC_INS_XVREDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRESP, PPC_INS_XVRESP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSPI, PPC_INS_XVRSPI, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSPIC, PPC_INS_XVRSPIC, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSPIM, PPC_INS_XVRSPIM, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSPIP, PPC_INS_XVRSPIP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSPIZ, PPC_INS_XVRSPIZ, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSQRTEDP, PPC_INS_XVRSQRTEDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVRSQRTESP, PPC_INS_XVRSQRTESP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVSQRTDP, PPC_INS_XVSQRTDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVSQRTSP, PPC_INS_XVSQRTSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVSUBDP, PPC_INS_XVSUBDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVSUBSP, PPC_INS_XVSUBSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVTDIVDP, PPC_INS_XVTDIVDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVTDIVSP, PPC_INS_XVTDIVSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVTSQRTDP, PPC_INS_XVTSQRTDP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVTSQRTSP, PPC_INS_XVTSQRTSP, #ifndef CAPSTONE_DIET { PPC_REG_RM, 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XVTSTDCDP, PPC_INS_XVTSTDCDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVTSTDCSP, PPC_INS_XVTSTDCSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVXEXPDP, PPC_INS_XVXEXPDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVXEXPSP, PPC_INS_XVXEXPSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVXSIGDP, PPC_INS_XVXSIGDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XVXSIGSP, PPC_INS_XVXSIGSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXBRD, PPC_INS_XXBRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXBRH, PPC_INS_XXBRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXBRQ, PPC_INS_XXBRQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXBRW, PPC_INS_XXBRW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXEXTRACTUW, PPC_INS_XXEXTRACTUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXINSERTW, PPC_INS_XXINSERTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXLAND, PPC_INS_XXLAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXLANDC, PPC_INS_XXLANDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXLEQV, PPC_INS_XXLEQV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 #endif }, { PPC_XXLNAND, PPC_INS_XXLNAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 #endif }, { PPC_XXLNOR, PPC_INS_XXLNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXLOR, PPC_INS_XXLOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXLORC, PPC_INS_XXLORC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_P8VECTOR, 0 }, 0, 0 #endif }, { PPC_XXLORf, PPC_INS_XXLOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXLXOR, PPC_INS_XXLXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXMRGHW, PPC_INS_XXMRGHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXMRGLW, PPC_INS_XXMRGLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXPERM, PPC_INS_XXPERM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXPERMDI, PPC_INS_XXMRGHD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXPERMDIs, PPC_INS_XXSPLTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXPERMR, PPC_INS_XXPERMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXSEL, PPC_INS_XXSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXSLDWI, PPC_INS_XXSLDWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_XXSPLTIB, PPC_INS_XXSPLTIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { PPC_XXSPLTW, PPC_INS_XXSPLTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { PPC_GRP_VSX, 0 }, 0, 0 #endif }, { PPC_gBC, PPC_INS_BC, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCA, PPC_INS_BCA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCAat, PPC_INS_BCA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCCTR, PPC_INS_BCCTR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCCTRL, PPC_INS_BCCTRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCL, PPC_INS_BCL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCLA, PPC_INS_BCLA, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCLAat, PPC_INS_BCLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCLR, PPC_INS_BCLR, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCLRL, PPC_INS_BCLRL, #ifndef CAPSTONE_DIET { PPC_REG_CTR, PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, PPC_REG_CTR, 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCLat, PPC_INS_BCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { PPC_gBCat, PPC_INS_BC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, capstone-sys-0.15.0/capstone/arch/PowerPC/PPCMappingInsnName.inc000064400000000000000000001464150072674642500225340ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ "add", // PPC_INS_ADD, "addc", // PPC_INS_ADDC, "adde", // PPC_INS_ADDE, "addi", // PPC_INS_ADDI, "addic", // PPC_INS_ADDIC, "addis", // PPC_INS_ADDIS, "addme", // PPC_INS_ADDME, "addpcis", // PPC_INS_ADDPCIS, "addze", // PPC_INS_ADDZE, "and", // PPC_INS_AND, "andc", // PPC_INS_ANDC, "andi", // PPC_INS_ANDI, "andis", // PPC_INS_ANDIS, "attn", // PPC_INS_ATTN, "b", // PPC_INS_B, "ba", // PPC_INS_BA, "bc", // PPC_INS_BC, "bca", // PPC_INS_BCA, "bcctr", // PPC_INS_BCCTR, "bcctrl", // PPC_INS_BCCTRL, "bcdcfn", // PPC_INS_BCDCFN, "bcdcfsq", // PPC_INS_BCDCFSQ, "bcdcfz", // PPC_INS_BCDCFZ, "bcdcpsgn", // PPC_INS_BCDCPSGN, "bcdctn", // PPC_INS_BCDCTN, "bcdctsq", // PPC_INS_BCDCTSQ, "bcdctz", // PPC_INS_BCDCTZ, "bcds", // PPC_INS_BCDS, "bcdsetsgn", // PPC_INS_BCDSETSGN, "bcdsr", // PPC_INS_BCDSR, "bcdtrunc", // PPC_INS_BCDTRUNC, "bcdus", // PPC_INS_BCDUS, "bcdutrunc", // PPC_INS_BCDUTRUNC, "bcl", // PPC_INS_BCL, "bcla", // PPC_INS_BCLA, "bclr", // PPC_INS_BCLR, "bclrl", // PPC_INS_BCLRL, "bctr", // PPC_INS_BCTR, "bctrl", // PPC_INS_BCTRL, "bdnz", // PPC_INS_BDNZ, "bdnza", // PPC_INS_BDNZA, "bdnzf", // PPC_INS_BDNZF, "bdnzfa", // PPC_INS_BDNZFA, "bdnzfl", // PPC_INS_BDNZFL, "bdnzfla", // PPC_INS_BDNZFLA, "bdnzflr", // PPC_INS_BDNZFLR, "bdnzflrl", // PPC_INS_BDNZFLRL, "bdnzl", // PPC_INS_BDNZL, "bdnzla", // PPC_INS_BDNZLA, "bdnzlr", // PPC_INS_BDNZLR, "bdnzlrl", // PPC_INS_BDNZLRL, "bdnzt", // PPC_INS_BDNZT, "bdnzta", // PPC_INS_BDNZTA, "bdnztl", // PPC_INS_BDNZTL, "bdnztla", // PPC_INS_BDNZTLA, "bdnztlr", // PPC_INS_BDNZTLR, "bdnztlrl", // PPC_INS_BDNZTLRL, "bdz", // PPC_INS_BDZ, "bdza", // PPC_INS_BDZA, "bdzf", // PPC_INS_BDZF, "bdzfa", // PPC_INS_BDZFA, "bdzfl", // PPC_INS_BDZFL, "bdzfla", // PPC_INS_BDZFLA, "bdzflr", // PPC_INS_BDZFLR, "bdzflrl", // PPC_INS_BDZFLRL, "bdzl", // PPC_INS_BDZL, "bdzla", // PPC_INS_BDZLA, "bdzlr", // PPC_INS_BDZLR, "bdzlrl", // PPC_INS_BDZLRL, "bdzt", // PPC_INS_BDZT, "bdzta", // PPC_INS_BDZTA, "bdztl", // PPC_INS_BDZTL, "bdztla", // PPC_INS_BDZTLA, "bdztlr", // PPC_INS_BDZTLR, "bdztlrl", // PPC_INS_BDZTLRL, "beq", // PPC_INS_BEQ, "beqa", // PPC_INS_BEQA, "beqctr", // PPC_INS_BEQCTR, "beqctrl", // PPC_INS_BEQCTRL, "beql", // PPC_INS_BEQL, "beqla", // PPC_INS_BEQLA, "beqlr", // PPC_INS_BEQLR, "beqlrl", // PPC_INS_BEQLRL, "bf", // PPC_INS_BF, "bfa", // PPC_INS_BFA, "bfctr", // PPC_INS_BFCTR, "bfctrl", // PPC_INS_BFCTRL, "bfl", // PPC_INS_BFL, "bfla", // PPC_INS_BFLA, "bflr", // PPC_INS_BFLR, "bflrl", // PPC_INS_BFLRL, "bge", // PPC_INS_BGE, "bgea", // PPC_INS_BGEA, "bgectr", // PPC_INS_BGECTR, "bgectrl", // PPC_INS_BGECTRL, "bgel", // PPC_INS_BGEL, "bgela", // PPC_INS_BGELA, "bgelr", // PPC_INS_BGELR, "bgelrl", // PPC_INS_BGELRL, "bgt", // PPC_INS_BGT, "bgta", // PPC_INS_BGTA, "bgtctr", // PPC_INS_BGTCTR, "bgtctrl", // PPC_INS_BGTCTRL, "bgtl", // PPC_INS_BGTL, "bgtla", // PPC_INS_BGTLA, "bgtlr", // PPC_INS_BGTLR, "bgtlrl", // PPC_INS_BGTLRL, "bl", // PPC_INS_BL, "bla", // PPC_INS_BLA, "ble", // PPC_INS_BLE, "blea", // PPC_INS_BLEA, "blectr", // PPC_INS_BLECTR, "blectrl", // PPC_INS_BLECTRL, "blel", // PPC_INS_BLEL, "blela", // PPC_INS_BLELA, "blelr", // PPC_INS_BLELR, "blelrl", // PPC_INS_BLELRL, "blr", // PPC_INS_BLR, "blrl", // PPC_INS_BLRL, "blt", // PPC_INS_BLT, "blta", // PPC_INS_BLTA, "bltctr", // PPC_INS_BLTCTR, "bltctrl", // PPC_INS_BLTCTRL, "bltl", // PPC_INS_BLTL, "bltla", // PPC_INS_BLTLA, "bltlr", // PPC_INS_BLTLR, "bltlrl", // PPC_INS_BLTLRL, "bne", // PPC_INS_BNE, "bnea", // PPC_INS_BNEA, "bnectr", // PPC_INS_BNECTR, "bnectrl", // PPC_INS_BNECTRL, "bnel", // PPC_INS_BNEL, "bnela", // PPC_INS_BNELA, "bnelr", // PPC_INS_BNELR, "bnelrl", // PPC_INS_BNELRL, "bng", // PPC_INS_BNG, "bnga", // PPC_INS_BNGA, "bngctr", // PPC_INS_BNGCTR, "bngctrl", // PPC_INS_BNGCTRL, "bngl", // PPC_INS_BNGL, "bngla", // PPC_INS_BNGLA, "bnglr", // PPC_INS_BNGLR, "bnglrl", // PPC_INS_BNGLRL, "bnl", // PPC_INS_BNL, "bnla", // PPC_INS_BNLA, "bnlctr", // PPC_INS_BNLCTR, "bnlctrl", // PPC_INS_BNLCTRL, "bnll", // PPC_INS_BNLL, "bnlla", // PPC_INS_BNLLA, "bnllr", // PPC_INS_BNLLR, "bnllrl", // PPC_INS_BNLLRL, "bns", // PPC_INS_BNS, "bnsa", // PPC_INS_BNSA, "bnsctr", // PPC_INS_BNSCTR, "bnsctrl", // PPC_INS_BNSCTRL, "bnsl", // PPC_INS_BNSL, "bnsla", // PPC_INS_BNSLA, "bnslr", // PPC_INS_BNSLR, "bnslrl", // PPC_INS_BNSLRL, "bnu", // PPC_INS_BNU, "bnua", // PPC_INS_BNUA, "bnuctr", // PPC_INS_BNUCTR, "bnuctrl", // PPC_INS_BNUCTRL, "bnul", // PPC_INS_BNUL, "bnula", // PPC_INS_BNULA, "bnulr", // PPC_INS_BNULR, "bnulrl", // PPC_INS_BNULRL, "bpermd", // PPC_INS_BPERMD, "brinc", // PPC_INS_BRINC, "bso", // PPC_INS_BSO, "bsoa", // PPC_INS_BSOA, "bsoctr", // PPC_INS_BSOCTR, "bsoctrl", // PPC_INS_BSOCTRL, "bsol", // PPC_INS_BSOL, "bsola", // PPC_INS_BSOLA, "bsolr", // PPC_INS_BSOLR, "bsolrl", // PPC_INS_BSOLRL, "bt", // PPC_INS_BT, "bta", // PPC_INS_BTA, "btctr", // PPC_INS_BTCTR, "btctrl", // PPC_INS_BTCTRL, "btl", // PPC_INS_BTL, "btla", // PPC_INS_BTLA, "btlr", // PPC_INS_BTLR, "btlrl", // PPC_INS_BTLRL, "bun", // PPC_INS_BUN, "buna", // PPC_INS_BUNA, "bunctr", // PPC_INS_BUNCTR, "bunctrl", // PPC_INS_BUNCTRL, "bunl", // PPC_INS_BUNL, "bunla", // PPC_INS_BUNLA, "bunlr", // PPC_INS_BUNLR, "bunlrl", // PPC_INS_BUNLRL, "clrbhrb", // PPC_INS_CLRBHRB, "clrldi", // PPC_INS_CLRLDI, "clrlsldi", // PPC_INS_CLRLSLDI, "clrlslwi", // PPC_INS_CLRLSLWI, "clrlwi", // PPC_INS_CLRLWI, "clrrdi", // PPC_INS_CLRRDI, "clrrwi", // PPC_INS_CLRRWI, "cmp", // PPC_INS_CMP, "cmpb", // PPC_INS_CMPB, "cmpd", // PPC_INS_CMPD, "cmpdi", // PPC_INS_CMPDI, "cmpeqb", // PPC_INS_CMPEQB, "cmpi", // PPC_INS_CMPI, "cmpl", // PPC_INS_CMPL, "cmpld", // PPC_INS_CMPLD, "cmpldi", // PPC_INS_CMPLDI, "cmpli", // PPC_INS_CMPLI, "cmplw", // PPC_INS_CMPLW, "cmplwi", // PPC_INS_CMPLWI, "cmprb", // PPC_INS_CMPRB, "cmpw", // PPC_INS_CMPW, "cmpwi", // PPC_INS_CMPWI, "cntlzd", // PPC_INS_CNTLZD, "cntlzw", // PPC_INS_CNTLZW, "cnttzd", // PPC_INS_CNTTZD, "cnttzw", // PPC_INS_CNTTZW, "copy", // PPC_INS_COPY, "copy_first", // PPC_INS_COPY_FIRST, "cp_abort", // PPC_INS_CP_ABORT, "crand", // PPC_INS_CRAND, "crandc", // PPC_INS_CRANDC, "crclr", // PPC_INS_CRCLR, "creqv", // PPC_INS_CREQV, "crmove", // PPC_INS_CRMOVE, "crnand", // PPC_INS_CRNAND, "crnor", // PPC_INS_CRNOR, "crnot", // PPC_INS_CRNOT, "cror", // PPC_INS_CROR, "crorc", // PPC_INS_CRORC, "crset", // PPC_INS_CRSET, "crxor", // PPC_INS_CRXOR, "darn", // PPC_INS_DARN, "dcba", // PPC_INS_DCBA, "dcbf", // PPC_INS_DCBF, "dcbfep", // PPC_INS_DCBFEP, "dcbfl", // PPC_INS_DCBFL, "dcbflp", // PPC_INS_DCBFLP, "dcbi", // PPC_INS_DCBI, "dcbst", // PPC_INS_DCBST, "dcbstep", // PPC_INS_DCBSTEP, "dcbt", // PPC_INS_DCBT, "dcbtct", // PPC_INS_DCBTCT, "dcbtds", // PPC_INS_DCBTDS, "dcbtep", // PPC_INS_DCBTEP, "dcbtst", // PPC_INS_DCBTST, "dcbtstct", // PPC_INS_DCBTSTCT, "dcbtstds", // PPC_INS_DCBTSTDS, "dcbtstep", // PPC_INS_DCBTSTEP, "dcbtstt", // PPC_INS_DCBTSTT, "dcbtt", // PPC_INS_DCBTT, "dcbz", // PPC_INS_DCBZ, "dcbzep", // PPC_INS_DCBZEP, "dcbzl", // PPC_INS_DCBZL, "dcbzlep", // PPC_INS_DCBZLEP, "dccci", // PPC_INS_DCCCI, "dci", // PPC_INS_DCI, "divd", // PPC_INS_DIVD, "divde", // PPC_INS_DIVDE, "divdeu", // PPC_INS_DIVDEU, "divdu", // PPC_INS_DIVDU, "divw", // PPC_INS_DIVW, "divwe", // PPC_INS_DIVWE, "divweu", // PPC_INS_DIVWEU, "divwu", // PPC_INS_DIVWU, "dss", // PPC_INS_DSS, "dssall", // PPC_INS_DSSALL, "dst", // PPC_INS_DST, "dstst", // PPC_INS_DSTST, "dststt", // PPC_INS_DSTSTT, "dstt", // PPC_INS_DSTT, "efdabs", // PPC_INS_EFDABS, "efdadd", // PPC_INS_EFDADD, "efdcfs", // PPC_INS_EFDCFS, "efdcfsf", // PPC_INS_EFDCFSF, "efdcfsi", // PPC_INS_EFDCFSI, "efdcfsid", // PPC_INS_EFDCFSID, "efdcfuf", // PPC_INS_EFDCFUF, "efdcfui", // PPC_INS_EFDCFUI, "efdcfuid", // PPC_INS_EFDCFUID, "efdcmpeq", // PPC_INS_EFDCMPEQ, "efdcmpgt", // PPC_INS_EFDCMPGT, "efdcmplt", // PPC_INS_EFDCMPLT, "efdctsf", // PPC_INS_EFDCTSF, "efdctsi", // PPC_INS_EFDCTSI, "efdctsidz", // PPC_INS_EFDCTSIDZ, "efdctsiz", // PPC_INS_EFDCTSIZ, "efdctuf", // PPC_INS_EFDCTUF, "efdctui", // PPC_INS_EFDCTUI, "efdctuidz", // PPC_INS_EFDCTUIDZ, "efdctuiz", // PPC_INS_EFDCTUIZ, "efddiv", // PPC_INS_EFDDIV, "efdmul", // PPC_INS_EFDMUL, "efdnabs", // PPC_INS_EFDNABS, "efdneg", // PPC_INS_EFDNEG, "efdsub", // PPC_INS_EFDSUB, "efdtsteq", // PPC_INS_EFDTSTEQ, "efdtstgt", // PPC_INS_EFDTSTGT, "efdtstlt", // PPC_INS_EFDTSTLT, "efsabs", // PPC_INS_EFSABS, "efsadd", // PPC_INS_EFSADD, "efscfd", // PPC_INS_EFSCFD, "efscfsf", // PPC_INS_EFSCFSF, "efscfsi", // PPC_INS_EFSCFSI, "efscfuf", // PPC_INS_EFSCFUF, "efscfui", // PPC_INS_EFSCFUI, "efscmpeq", // PPC_INS_EFSCMPEQ, "efscmpgt", // PPC_INS_EFSCMPGT, "efscmplt", // PPC_INS_EFSCMPLT, "efsctsf", // PPC_INS_EFSCTSF, "efsctsi", // PPC_INS_EFSCTSI, "efsctsiz", // PPC_INS_EFSCTSIZ, "efsctuf", // PPC_INS_EFSCTUF, "efsctui", // PPC_INS_EFSCTUI, "efsctuiz", // PPC_INS_EFSCTUIZ, "efsdiv", // PPC_INS_EFSDIV, "efsmul", // PPC_INS_EFSMUL, "efsnabs", // PPC_INS_EFSNABS, "efsneg", // PPC_INS_EFSNEG, "efssub", // PPC_INS_EFSSUB, "efststeq", // PPC_INS_EFSTSTEQ, "efststgt", // PPC_INS_EFSTSTGT, "efststlt", // PPC_INS_EFSTSTLT, "eieio", // PPC_INS_EIEIO, "eqv", // PPC_INS_EQV, "evabs", // PPC_INS_EVABS, "evaddiw", // PPC_INS_EVADDIW, "evaddsmiaaw", // PPC_INS_EVADDSMIAAW, "evaddssiaaw", // PPC_INS_EVADDSSIAAW, "evaddumiaaw", // PPC_INS_EVADDUMIAAW, "evaddusiaaw", // PPC_INS_EVADDUSIAAW, "evaddw", // PPC_INS_EVADDW, "evand", // PPC_INS_EVAND, "evandc", // PPC_INS_EVANDC, "evcmpeq", // PPC_INS_EVCMPEQ, "evcmpgts", // PPC_INS_EVCMPGTS, "evcmpgtu", // PPC_INS_EVCMPGTU, "evcmplts", // PPC_INS_EVCMPLTS, "evcmpltu", // PPC_INS_EVCMPLTU, "evcntlsw", // PPC_INS_EVCNTLSW, "evcntlzw", // PPC_INS_EVCNTLZW, "evdivws", // PPC_INS_EVDIVWS, "evdivwu", // PPC_INS_EVDIVWU, "eveqv", // PPC_INS_EVEQV, "evextsb", // PPC_INS_EVEXTSB, "evextsh", // PPC_INS_EVEXTSH, "evfsabs", // PPC_INS_EVFSABS, "evfsadd", // PPC_INS_EVFSADD, "evfscfsf", // PPC_INS_EVFSCFSF, "evfscfsi", // PPC_INS_EVFSCFSI, "evfscfuf", // PPC_INS_EVFSCFUF, "evfscfui", // PPC_INS_EVFSCFUI, "evfscmpeq", // PPC_INS_EVFSCMPEQ, "evfscmpgt", // PPC_INS_EVFSCMPGT, "evfscmplt", // PPC_INS_EVFSCMPLT, "evfsctsf", // PPC_INS_EVFSCTSF, "evfsctsi", // PPC_INS_EVFSCTSI, "evfsctsiz", // PPC_INS_EVFSCTSIZ, "evfsctui", // PPC_INS_EVFSCTUI, "evfsdiv", // PPC_INS_EVFSDIV, "evfsmul", // PPC_INS_EVFSMUL, "evfsnabs", // PPC_INS_EVFSNABS, "evfsneg", // PPC_INS_EVFSNEG, "evfssub", // PPC_INS_EVFSSUB, "evfststeq", // PPC_INS_EVFSTSTEQ, "evfststgt", // PPC_INS_EVFSTSTGT, "evfststlt", // PPC_INS_EVFSTSTLT, "evldd", // PPC_INS_EVLDD, "evlddx", // PPC_INS_EVLDDX, "evldh", // PPC_INS_EVLDH, "evldhx", // PPC_INS_EVLDHX, "evldw", // PPC_INS_EVLDW, "evldwx", // PPC_INS_EVLDWX, "evlhhesplat", // PPC_INS_EVLHHESPLAT, "evlhhesplatx", // PPC_INS_EVLHHESPLATX, "evlhhossplat", // PPC_INS_EVLHHOSSPLAT, "evlhhossplatx", // PPC_INS_EVLHHOSSPLATX, "evlhhousplat", // PPC_INS_EVLHHOUSPLAT, "evlhhousplatx", // PPC_INS_EVLHHOUSPLATX, "evlwhe", // PPC_INS_EVLWHE, "evlwhex", // PPC_INS_EVLWHEX, "evlwhos", // PPC_INS_EVLWHOS, "evlwhosx", // PPC_INS_EVLWHOSX, "evlwhou", // PPC_INS_EVLWHOU, "evlwhoux", // PPC_INS_EVLWHOUX, "evlwhsplat", // PPC_INS_EVLWHSPLAT, "evlwhsplatx", // PPC_INS_EVLWHSPLATX, "evlwwsplat", // PPC_INS_EVLWWSPLAT, "evlwwsplatx", // PPC_INS_EVLWWSPLATX, "evmergehi", // PPC_INS_EVMERGEHI, "evmergehilo", // PPC_INS_EVMERGEHILO, "evmergelo", // PPC_INS_EVMERGELO, "evmergelohi", // PPC_INS_EVMERGELOHI, "evmhegsmfaa", // PPC_INS_EVMHEGSMFAA, "evmhegsmfan", // PPC_INS_EVMHEGSMFAN, "evmhegsmiaa", // PPC_INS_EVMHEGSMIAA, "evmhegsmian", // PPC_INS_EVMHEGSMIAN, "evmhegumiaa", // PPC_INS_EVMHEGUMIAA, "evmhegumian", // PPC_INS_EVMHEGUMIAN, "evmhesmf", // PPC_INS_EVMHESMF, "evmhesmfa", // PPC_INS_EVMHESMFA, "evmhesmfaaw", // PPC_INS_EVMHESMFAAW, "evmhesmfanw", // PPC_INS_EVMHESMFANW, "evmhesmi", // PPC_INS_EVMHESMI, "evmhesmia", // PPC_INS_EVMHESMIA, "evmhesmiaaw", // PPC_INS_EVMHESMIAAW, "evmhesmianw", // PPC_INS_EVMHESMIANW, "evmhessf", // PPC_INS_EVMHESSF, "evmhessfa", // PPC_INS_EVMHESSFA, "evmhessfaaw", // PPC_INS_EVMHESSFAAW, "evmhessfanw", // PPC_INS_EVMHESSFANW, "evmhessiaaw", // PPC_INS_EVMHESSIAAW, "evmhessianw", // PPC_INS_EVMHESSIANW, "evmheumi", // PPC_INS_EVMHEUMI, "evmheumia", // PPC_INS_EVMHEUMIA, "evmheumiaaw", // PPC_INS_EVMHEUMIAAW, "evmheumianw", // PPC_INS_EVMHEUMIANW, "evmheusiaaw", // PPC_INS_EVMHEUSIAAW, "evmheusianw", // PPC_INS_EVMHEUSIANW, "evmhogsmfaa", // PPC_INS_EVMHOGSMFAA, "evmhogsmfan", // PPC_INS_EVMHOGSMFAN, "evmhogsmiaa", // PPC_INS_EVMHOGSMIAA, "evmhogsmian", // PPC_INS_EVMHOGSMIAN, "evmhogumiaa", // PPC_INS_EVMHOGUMIAA, "evmhogumian", // PPC_INS_EVMHOGUMIAN, "evmhosmf", // PPC_INS_EVMHOSMF, "evmhosmfa", // PPC_INS_EVMHOSMFA, "evmhosmfaaw", // PPC_INS_EVMHOSMFAAW, "evmhosmfanw", // PPC_INS_EVMHOSMFANW, "evmhosmi", // PPC_INS_EVMHOSMI, "evmhosmia", // PPC_INS_EVMHOSMIA, "evmhosmiaaw", // PPC_INS_EVMHOSMIAAW, "evmhosmianw", // PPC_INS_EVMHOSMIANW, "evmhossf", // PPC_INS_EVMHOSSF, "evmhossfa", // PPC_INS_EVMHOSSFA, "evmhossfaaw", // PPC_INS_EVMHOSSFAAW, "evmhossfanw", // PPC_INS_EVMHOSSFANW, "evmhossiaaw", // PPC_INS_EVMHOSSIAAW, "evmhossianw", // PPC_INS_EVMHOSSIANW, "evmhoumi", // PPC_INS_EVMHOUMI, "evmhoumia", // PPC_INS_EVMHOUMIA, "evmhoumiaaw", // PPC_INS_EVMHOUMIAAW, "evmhoumianw", // PPC_INS_EVMHOUMIANW, "evmhousiaaw", // PPC_INS_EVMHOUSIAAW, "evmhousianw", // PPC_INS_EVMHOUSIANW, "evmra", // PPC_INS_EVMRA, "evmwhsmf", // PPC_INS_EVMWHSMF, "evmwhsmfa", // PPC_INS_EVMWHSMFA, "evmwhsmi", // PPC_INS_EVMWHSMI, "evmwhsmia", // PPC_INS_EVMWHSMIA, "evmwhssf", // PPC_INS_EVMWHSSF, "evmwhssfa", // PPC_INS_EVMWHSSFA, "evmwhumi", // PPC_INS_EVMWHUMI, "evmwhumia", // PPC_INS_EVMWHUMIA, "evmwlsmiaaw", // PPC_INS_EVMWLSMIAAW, "evmwlsmianw", // PPC_INS_EVMWLSMIANW, "evmwlssiaaw", // PPC_INS_EVMWLSSIAAW, "evmwlssianw", // PPC_INS_EVMWLSSIANW, "evmwlumi", // PPC_INS_EVMWLUMI, "evmwlumia", // PPC_INS_EVMWLUMIA, "evmwlumiaaw", // PPC_INS_EVMWLUMIAAW, "evmwlumianw", // PPC_INS_EVMWLUMIANW, "evmwlusiaaw", // PPC_INS_EVMWLUSIAAW, "evmwlusianw", // PPC_INS_EVMWLUSIANW, "evmwsmf", // PPC_INS_EVMWSMF, "evmwsmfa", // PPC_INS_EVMWSMFA, "evmwsmfaa", // PPC_INS_EVMWSMFAA, "evmwsmfan", // PPC_INS_EVMWSMFAN, "evmwsmi", // PPC_INS_EVMWSMI, "evmwsmia", // PPC_INS_EVMWSMIA, "evmwsmiaa", // PPC_INS_EVMWSMIAA, "evmwsmian", // PPC_INS_EVMWSMIAN, "evmwssf", // PPC_INS_EVMWSSF, "evmwssfa", // PPC_INS_EVMWSSFA, "evmwssfaa", // PPC_INS_EVMWSSFAA, "evmwssfan", // PPC_INS_EVMWSSFAN, "evmwumi", // PPC_INS_EVMWUMI, "evmwumia", // PPC_INS_EVMWUMIA, "evmwumiaa", // PPC_INS_EVMWUMIAA, "evmwumian", // PPC_INS_EVMWUMIAN, "evnand", // PPC_INS_EVNAND, "evneg", // PPC_INS_EVNEG, "evnor", // PPC_INS_EVNOR, "evor", // PPC_INS_EVOR, "evorc", // PPC_INS_EVORC, "evrlw", // PPC_INS_EVRLW, "evrlwi", // PPC_INS_EVRLWI, "evrndw", // PPC_INS_EVRNDW, "evsel", // PPC_INS_EVSEL, "evslw", // PPC_INS_EVSLW, "evslwi", // PPC_INS_EVSLWI, "evsplatfi", // PPC_INS_EVSPLATFI, "evsplati", // PPC_INS_EVSPLATI, "evsrwis", // PPC_INS_EVSRWIS, "evsrwiu", // PPC_INS_EVSRWIU, "evsrws", // PPC_INS_EVSRWS, "evsrwu", // PPC_INS_EVSRWU, "evstdd", // PPC_INS_EVSTDD, "evstddx", // PPC_INS_EVSTDDX, "evstdh", // PPC_INS_EVSTDH, "evstdhx", // PPC_INS_EVSTDHX, "evstdw", // PPC_INS_EVSTDW, "evstdwx", // PPC_INS_EVSTDWX, "evstwhe", // PPC_INS_EVSTWHE, "evstwhex", // PPC_INS_EVSTWHEX, "evstwho", // PPC_INS_EVSTWHO, "evstwhox", // PPC_INS_EVSTWHOX, "evstwwe", // PPC_INS_EVSTWWE, "evstwwex", // PPC_INS_EVSTWWEX, "evstwwo", // PPC_INS_EVSTWWO, "evstwwox", // PPC_INS_EVSTWWOX, "evsubfsmiaaw", // PPC_INS_EVSUBFSMIAAW, "evsubfssiaaw", // PPC_INS_EVSUBFSSIAAW, "evsubfumiaaw", // PPC_INS_EVSUBFUMIAAW, "evsubfusiaaw", // PPC_INS_EVSUBFUSIAAW, "evsubfw", // PPC_INS_EVSUBFW, "evsubifw", // PPC_INS_EVSUBIFW, "evxor", // PPC_INS_EVXOR, "extldi", // PPC_INS_EXTLDI, "extlwi", // PPC_INS_EXTLWI, "extrdi", // PPC_INS_EXTRDI, "extrwi", // PPC_INS_EXTRWI, "extsb", // PPC_INS_EXTSB, "extsh", // PPC_INS_EXTSH, "extsw", // PPC_INS_EXTSW, "extswsli", // PPC_INS_EXTSWSLI, "fabs", // PPC_INS_FABS, "fadd", // PPC_INS_FADD, "fadds", // PPC_INS_FADDS, "fcfid", // PPC_INS_FCFID, "fcfids", // PPC_INS_FCFIDS, "fcfidu", // PPC_INS_FCFIDU, "fcfidus", // PPC_INS_FCFIDUS, "fcmpu", // PPC_INS_FCMPU, "fcpsgn", // PPC_INS_FCPSGN, "fctid", // PPC_INS_FCTID, "fctidu", // PPC_INS_FCTIDU, "fctiduz", // PPC_INS_FCTIDUZ, "fctidz", // PPC_INS_FCTIDZ, "fctiw", // PPC_INS_FCTIW, "fctiwu", // PPC_INS_FCTIWU, "fctiwuz", // PPC_INS_FCTIWUZ, "fctiwz", // PPC_INS_FCTIWZ, "fdiv", // PPC_INS_FDIV, "fdivs", // PPC_INS_FDIVS, "fmadd", // PPC_INS_FMADD, "fmadds", // PPC_INS_FMADDS, "fmr", // PPC_INS_FMR, "fmsub", // PPC_INS_FMSUB, "fmsubs", // PPC_INS_FMSUBS, "fmul", // PPC_INS_FMUL, "fmuls", // PPC_INS_FMULS, "fnabs", // PPC_INS_FNABS, "fneg", // PPC_INS_FNEG, "fnmadd", // PPC_INS_FNMADD, "fnmadds", // PPC_INS_FNMADDS, "fnmsub", // PPC_INS_FNMSUB, "fnmsubs", // PPC_INS_FNMSUBS, "fre", // PPC_INS_FRE, "fres", // PPC_INS_FRES, "frim", // PPC_INS_FRIM, "frin", // PPC_INS_FRIN, "frip", // PPC_INS_FRIP, "friz", // PPC_INS_FRIZ, "frsp", // PPC_INS_FRSP, "frsqrte", // PPC_INS_FRSQRTE, "frsqrtes", // PPC_INS_FRSQRTES, "fsel", // PPC_INS_FSEL, "fsqrt", // PPC_INS_FSQRT, "fsqrts", // PPC_INS_FSQRTS, "fsub", // PPC_INS_FSUB, "fsubs", // PPC_INS_FSUBS, "ftdiv", // PPC_INS_FTDIV, "ftsqrt", // PPC_INS_FTSQRT, "hrfid", // PPC_INS_HRFID, "icbi", // PPC_INS_ICBI, "icbiep", // PPC_INS_ICBIEP, "icblc", // PPC_INS_ICBLC, "icblq", // PPC_INS_ICBLQ, "icbt", // PPC_INS_ICBT, "icbtls", // PPC_INS_ICBTLS, "iccci", // PPC_INS_ICCCI, "ici", // PPC_INS_ICI, "inslwi", // PPC_INS_INSLWI, "insrdi", // PPC_INS_INSRDI, "insrwi", // PPC_INS_INSRWI, "isel", // PPC_INS_ISEL, "isync", // PPC_INS_ISYNC, "la", // PPC_INS_LA, "lbarx", // PPC_INS_LBARX, "lbepx", // PPC_INS_LBEPX, "lbz", // PPC_INS_LBZ, "lbzcix", // PPC_INS_LBZCIX, "lbzu", // PPC_INS_LBZU, "lbzux", // PPC_INS_LBZUX, "lbzx", // PPC_INS_LBZX, "ld", // PPC_INS_LD, "ldarx", // PPC_INS_LDARX, "ldat", // PPC_INS_LDAT, "ldbrx", // PPC_INS_LDBRX, "ldcix", // PPC_INS_LDCIX, "ldmx", // PPC_INS_LDMX, "ldu", // PPC_INS_LDU, "ldux", // PPC_INS_LDUX, "ldx", // PPC_INS_LDX, "lfd", // PPC_INS_LFD, "lfdepx", // PPC_INS_LFDEPX, "lfdu", // PPC_INS_LFDU, "lfdux", // PPC_INS_LFDUX, "lfdx", // PPC_INS_LFDX, "lfiwax", // PPC_INS_LFIWAX, "lfiwzx", // PPC_INS_LFIWZX, "lfs", // PPC_INS_LFS, "lfsu", // PPC_INS_LFSU, "lfsux", // PPC_INS_LFSUX, "lfsx", // PPC_INS_LFSX, "lha", // PPC_INS_LHA, "lharx", // PPC_INS_LHARX, "lhau", // PPC_INS_LHAU, "lhaux", // PPC_INS_LHAUX, "lhax", // PPC_INS_LHAX, "lhbrx", // PPC_INS_LHBRX, "lhepx", // PPC_INS_LHEPX, "lhz", // PPC_INS_LHZ, "lhzcix", // PPC_INS_LHZCIX, "lhzu", // PPC_INS_LHZU, "lhzux", // PPC_INS_LHZUX, "lhzx", // PPC_INS_LHZX, "li", // PPC_INS_LI, "lis", // PPC_INS_LIS, "lmw", // PPC_INS_LMW, "lnia", // PPC_INS_LNIA, "lswi", // PPC_INS_LSWI, "lvebx", // PPC_INS_LVEBX, "lvehx", // PPC_INS_LVEHX, "lvewx", // PPC_INS_LVEWX, "lvsl", // PPC_INS_LVSL, "lvsr", // PPC_INS_LVSR, "lvx", // PPC_INS_LVX, "lvxl", // PPC_INS_LVXL, "lwa", // PPC_INS_LWA, "lwarx", // PPC_INS_LWARX, "lwat", // PPC_INS_LWAT, "lwaux", // PPC_INS_LWAUX, "lwax", // PPC_INS_LWAX, "lwbrx", // PPC_INS_LWBRX, "lwepx", // PPC_INS_LWEPX, "lwsync", // PPC_INS_LWSYNC, "lwz", // PPC_INS_LWZ, "lwzcix", // PPC_INS_LWZCIX, "lwzu", // PPC_INS_LWZU, "lwzux", // PPC_INS_LWZUX, "lwzx", // PPC_INS_LWZX, "lxsd", // PPC_INS_LXSD, "lxsdx", // PPC_INS_LXSDX, "lxsibzx", // PPC_INS_LXSIBZX, "lxsihzx", // PPC_INS_LXSIHZX, "lxsiwax", // PPC_INS_LXSIWAX, "lxsiwzx", // PPC_INS_LXSIWZX, "lxssp", // PPC_INS_LXSSP, "lxsspx", // PPC_INS_LXSSPX, "lxv", // PPC_INS_LXV, "lxvb16x", // PPC_INS_LXVB16X, "lxvd2x", // PPC_INS_LXVD2X, "lxvdsx", // PPC_INS_LXVDSX, "lxvh8x", // PPC_INS_LXVH8X, "lxvl", // PPC_INS_LXVL, "lxvll", // PPC_INS_LXVLL, "lxvw4x", // PPC_INS_LXVW4X, "lxvwsx", // PPC_INS_LXVWSX, "lxvx", // PPC_INS_LXVX, "maddhd", // PPC_INS_MADDHD, "maddhdu", // PPC_INS_MADDHDU, "maddld", // PPC_INS_MADDLD, "mbar", // PPC_INS_MBAR, "mcrf", // PPC_INS_MCRF, "mcrfs", // PPC_INS_MCRFS, "mcrxrx", // PPC_INS_MCRXRX, "mfamr", // PPC_INS_MFAMR, "mfasr", // PPC_INS_MFASR, "mfbhrbe", // PPC_INS_MFBHRBE, "mfbr0", // PPC_INS_MFBR0, "mfbr1", // PPC_INS_MFBR1, "mfbr2", // PPC_INS_MFBR2, "mfbr3", // PPC_INS_MFBR3, "mfbr4", // PPC_INS_MFBR4, "mfbr5", // PPC_INS_MFBR5, "mfbr6", // PPC_INS_MFBR6, "mfbr7", // PPC_INS_MFBR7, "mfcfar", // PPC_INS_MFCFAR, "mfcr", // PPC_INS_MFCR, "mfctr", // PPC_INS_MFCTR, "mfdar", // PPC_INS_MFDAR, "mfdbatl", // PPC_INS_MFDBATL, "mfdbatu", // PPC_INS_MFDBATU, "mfdccr", // PPC_INS_MFDCCR, "mfdcr", // PPC_INS_MFDCR, "mfdear", // PPC_INS_MFDEAR, "mfdec", // PPC_INS_MFDEC, "mfdscr", // PPC_INS_MFDSCR, "mfdsisr", // PPC_INS_MFDSISR, "mfesr", // PPC_INS_MFESR, "mffprd", // PPC_INS_MFFPRD, "mffs", // PPC_INS_MFFS, "mffscdrn", // PPC_INS_MFFSCDRN, "mffscdrni", // PPC_INS_MFFSCDRNI, "mffsce", // PPC_INS_MFFSCE, "mffscrn", // PPC_INS_MFFSCRN, "mffscrni", // PPC_INS_MFFSCRNI, "mffsl", // PPC_INS_MFFSL, "mfibatl", // PPC_INS_MFIBATL, "mfibatu", // PPC_INS_MFIBATU, "mficcr", // PPC_INS_MFICCR, "mflr", // PPC_INS_MFLR, "mfmsr", // PPC_INS_MFMSR, "mfocrf", // PPC_INS_MFOCRF, "mfpid", // PPC_INS_MFPID, "mfpmr", // PPC_INS_MFPMR, "mfpvr", // PPC_INS_MFPVR, "mfrtcl", // PPC_INS_MFRTCL, "mfrtcu", // PPC_INS_MFRTCU, "mfsdr1", // PPC_INS_MFSDR1, "mfspefscr", // PPC_INS_MFSPEFSCR, "mfspr", // PPC_INS_MFSPR, "mfsprg", // PPC_INS_MFSPRG, "mfsprg0", // PPC_INS_MFSPRG0, "mfsprg1", // PPC_INS_MFSPRG1, "mfsprg2", // PPC_INS_MFSPRG2, "mfsprg3", // PPC_INS_MFSPRG3, "mfsprg4", // PPC_INS_MFSPRG4, "mfsprg5", // PPC_INS_MFSPRG5, "mfsprg6", // PPC_INS_MFSPRG6, "mfsprg7", // PPC_INS_MFSPRG7, "mfsr", // PPC_INS_MFSR, "mfsrin", // PPC_INS_MFSRIN, "mfsrr0", // PPC_INS_MFSRR0, "mfsrr1", // PPC_INS_MFSRR1, "mfsrr2", // PPC_INS_MFSRR2, "mfsrr3", // PPC_INS_MFSRR3, "mftb", // PPC_INS_MFTB, "mftbhi", // PPC_INS_MFTBHI, "mftbl", // PPC_INS_MFTBL, "mftblo", // PPC_INS_MFTBLO, "mftbu", // PPC_INS_MFTBU, "mftcr", // PPC_INS_MFTCR, "mfvrd", // PPC_INS_MFVRD, "mfvrsave", // PPC_INS_MFVRSAVE, "mfvscr", // PPC_INS_MFVSCR, "mfvsrd", // PPC_INS_MFVSRD, "mfvsrld", // PPC_INS_MFVSRLD, "mfvsrwz", // PPC_INS_MFVSRWZ, "mfxer", // PPC_INS_MFXER, "modsd", // PPC_INS_MODSD, "modsw", // PPC_INS_MODSW, "modud", // PPC_INS_MODUD, "moduw", // PPC_INS_MODUW, "mr", // PPC_INS_MR, "msgsync", // PPC_INS_MSGSYNC, "msync", // PPC_INS_MSYNC, "mtamr", // PPC_INS_MTAMR, "mtasr", // PPC_INS_MTASR, "mtbr0", // PPC_INS_MTBR0, "mtbr1", // PPC_INS_MTBR1, "mtbr2", // PPC_INS_MTBR2, "mtbr3", // PPC_INS_MTBR3, "mtbr4", // PPC_INS_MTBR4, "mtbr5", // PPC_INS_MTBR5, "mtbr6", // PPC_INS_MTBR6, "mtbr7", // PPC_INS_MTBR7, "mtcfar", // PPC_INS_MTCFAR, "mtcr", // PPC_INS_MTCR, "mtcrf", // PPC_INS_MTCRF, "mtctr", // PPC_INS_MTCTR, "mtdar", // PPC_INS_MTDAR, "mtdbatl", // PPC_INS_MTDBATL, "mtdbatu", // PPC_INS_MTDBATU, "mtdccr", // PPC_INS_MTDCCR, "mtdcr", // PPC_INS_MTDCR, "mtdear", // PPC_INS_MTDEAR, "mtdec", // PPC_INS_MTDEC, "mtdscr", // PPC_INS_MTDSCR, "mtdsisr", // PPC_INS_MTDSISR, "mtesr", // PPC_INS_MTESR, "mtfsb0", // PPC_INS_MTFSB0, "mtfsb1", // PPC_INS_MTFSB1, "mtfsf", // PPC_INS_MTFSF, "mtfsfi", // PPC_INS_MTFSFI, "mtibatl", // PPC_INS_MTIBATL, "mtibatu", // PPC_INS_MTIBATU, "mticcr", // PPC_INS_MTICCR, "mtlr", // PPC_INS_MTLR, "mtmsr", // PPC_INS_MTMSR, "mtmsrd", // PPC_INS_MTMSRD, "mtocrf", // PPC_INS_MTOCRF, "mtpid", // PPC_INS_MTPID, "mtpmr", // PPC_INS_MTPMR, "mtsdr1", // PPC_INS_MTSDR1, "mtspefscr", // PPC_INS_MTSPEFSCR, "mtspr", // PPC_INS_MTSPR, "mtsprg", // PPC_INS_MTSPRG, "mtsprg0", // PPC_INS_MTSPRG0, "mtsprg1", // PPC_INS_MTSPRG1, "mtsprg2", // PPC_INS_MTSPRG2, "mtsprg3", // PPC_INS_MTSPRG3, "mtsprg4", // PPC_INS_MTSPRG4, "mtsprg5", // PPC_INS_MTSPRG5, "mtsprg6", // PPC_INS_MTSPRG6, "mtsprg7", // PPC_INS_MTSPRG7, "mtsr", // PPC_INS_MTSR, "mtsrin", // PPC_INS_MTSRIN, "mtsrr0", // PPC_INS_MTSRR0, "mtsrr1", // PPC_INS_MTSRR1, "mtsrr2", // PPC_INS_MTSRR2, "mtsrr3", // PPC_INS_MTSRR3, "mttbhi", // PPC_INS_MTTBHI, "mttbl", // PPC_INS_MTTBL, "mttblo", // PPC_INS_MTTBLO, "mttbu", // PPC_INS_MTTBU, "mttcr", // PPC_INS_MTTCR, "mtvrsave", // PPC_INS_MTVRSAVE, "mtvscr", // PPC_INS_MTVSCR, "mtvsrd", // PPC_INS_MTVSRD, "mtvsrdd", // PPC_INS_MTVSRDD, "mtvsrwa", // PPC_INS_MTVSRWA, "mtvsrws", // PPC_INS_MTVSRWS, "mtvsrwz", // PPC_INS_MTVSRWZ, "mtxer", // PPC_INS_MTXER, "mulhd", // PPC_INS_MULHD, "mulhdu", // PPC_INS_MULHDU, "mulhw", // PPC_INS_MULHW, "mulhwu", // PPC_INS_MULHWU, "mulld", // PPC_INS_MULLD, "mulli", // PPC_INS_MULLI, "mullw", // PPC_INS_MULLW, "nand", // PPC_INS_NAND, "nap", // PPC_INS_NAP, "neg", // PPC_INS_NEG, "nop", // PPC_INS_NOP, "nor", // PPC_INS_NOR, "not", // PPC_INS_NOT, "or", // PPC_INS_OR, "orc", // PPC_INS_ORC, "ori", // PPC_INS_ORI, "oris", // PPC_INS_ORIS, "paste", // PPC_INS_PASTE, "paste_last", // PPC_INS_PASTE_LAST, "popcntb", // PPC_INS_POPCNTB, "popcntd", // PPC_INS_POPCNTD, "popcntw", // PPC_INS_POPCNTW, "ptesync", // PPC_INS_PTESYNC, "qvaligni", // PPC_INS_QVALIGNI, "qvesplati", // PPC_INS_QVESPLATI, "qvfabs", // PPC_INS_QVFABS, "qvfadd", // PPC_INS_QVFADD, "qvfadds", // PPC_INS_QVFADDS, "qvfand", // PPC_INS_QVFAND, "qvfandc", // PPC_INS_QVFANDC, "qvfcfid", // PPC_INS_QVFCFID, "qvfcfids", // PPC_INS_QVFCFIDS, "qvfcfidu", // PPC_INS_QVFCFIDU, "qvfcfidus", // PPC_INS_QVFCFIDUS, "qvfclr", // PPC_INS_QVFCLR, "qvfcmpeq", // PPC_INS_QVFCMPEQ, "qvfcmpgt", // PPC_INS_QVFCMPGT, "qvfcmplt", // PPC_INS_QVFCMPLT, "qvfcpsgn", // PPC_INS_QVFCPSGN, "qvfctfb", // PPC_INS_QVFCTFB, "qvfctid", // PPC_INS_QVFCTID, "qvfctidu", // PPC_INS_QVFCTIDU, "qvfctiduz", // PPC_INS_QVFCTIDUZ, "qvfctidz", // PPC_INS_QVFCTIDZ, "qvfctiw", // PPC_INS_QVFCTIW, "qvfctiwu", // PPC_INS_QVFCTIWU, "qvfctiwuz", // PPC_INS_QVFCTIWUZ, "qvfctiwz", // PPC_INS_QVFCTIWZ, "qvfequ", // PPC_INS_QVFEQU, "qvflogical", // PPC_INS_QVFLOGICAL, "qvfmadd", // PPC_INS_QVFMADD, "qvfmadds", // PPC_INS_QVFMADDS, "qvfmr", // PPC_INS_QVFMR, "qvfmsub", // PPC_INS_QVFMSUB, "qvfmsubs", // PPC_INS_QVFMSUBS, "qvfmul", // PPC_INS_QVFMUL, "qvfmuls", // PPC_INS_QVFMULS, "qvfnabs", // PPC_INS_QVFNABS, "qvfnand", // PPC_INS_QVFNAND, "qvfneg", // PPC_INS_QVFNEG, "qvfnmadd", // PPC_INS_QVFNMADD, "qvfnmadds", // PPC_INS_QVFNMADDS, "qvfnmsub", // PPC_INS_QVFNMSUB, "qvfnmsubs", // PPC_INS_QVFNMSUBS, "qvfnor", // PPC_INS_QVFNOR, "qvfnot", // PPC_INS_QVFNOT, "qvfor", // PPC_INS_QVFOR, "qvforc", // PPC_INS_QVFORC, "qvfperm", // PPC_INS_QVFPERM, "qvfre", // PPC_INS_QVFRE, "qvfres", // PPC_INS_QVFRES, "qvfrim", // PPC_INS_QVFRIM, "qvfrin", // PPC_INS_QVFRIN, "qvfrip", // PPC_INS_QVFRIP, "qvfriz", // PPC_INS_QVFRIZ, "qvfrsp", // PPC_INS_QVFRSP, "qvfrsqrte", // PPC_INS_QVFRSQRTE, "qvfrsqrtes", // PPC_INS_QVFRSQRTES, "qvfsel", // PPC_INS_QVFSEL, "qvfset", // PPC_INS_QVFSET, "qvfsub", // PPC_INS_QVFSUB, "qvfsubs", // PPC_INS_QVFSUBS, "qvftstnan", // PPC_INS_QVFTSTNAN, "qvfxmadd", // PPC_INS_QVFXMADD, "qvfxmadds", // PPC_INS_QVFXMADDS, "qvfxmul", // PPC_INS_QVFXMUL, "qvfxmuls", // PPC_INS_QVFXMULS, "qvfxor", // PPC_INS_QVFXOR, "qvfxxcpnmadd", // PPC_INS_QVFXXCPNMADD, "qvfxxcpnmadds", // PPC_INS_QVFXXCPNMADDS, "qvfxxmadd", // PPC_INS_QVFXXMADD, "qvfxxmadds", // PPC_INS_QVFXXMADDS, "qvfxxnpmadd", // PPC_INS_QVFXXNPMADD, "qvfxxnpmadds", // PPC_INS_QVFXXNPMADDS, "qvgpci", // PPC_INS_QVGPCI, "qvlfcdux", // PPC_INS_QVLFCDUX, "qvlfcduxa", // PPC_INS_QVLFCDUXA, "qvlfcdx", // PPC_INS_QVLFCDX, "qvlfcdxa", // PPC_INS_QVLFCDXA, "qvlfcsux", // PPC_INS_QVLFCSUX, "qvlfcsuxa", // PPC_INS_QVLFCSUXA, "qvlfcsx", // PPC_INS_QVLFCSX, "qvlfcsxa", // PPC_INS_QVLFCSXA, "qvlfdux", // PPC_INS_QVLFDUX, "qvlfduxa", // PPC_INS_QVLFDUXA, "qvlfdx", // PPC_INS_QVLFDX, "qvlfdxa", // PPC_INS_QVLFDXA, "qvlfiwax", // PPC_INS_QVLFIWAX, "qvlfiwaxa", // PPC_INS_QVLFIWAXA, "qvlfiwzx", // PPC_INS_QVLFIWZX, "qvlfiwzxa", // PPC_INS_QVLFIWZXA, "qvlfsux", // PPC_INS_QVLFSUX, "qvlfsuxa", // PPC_INS_QVLFSUXA, "qvlfsx", // PPC_INS_QVLFSX, "qvlfsxa", // PPC_INS_QVLFSXA, "qvlpcldx", // PPC_INS_QVLPCLDX, "qvlpclsx", // PPC_INS_QVLPCLSX, "qvlpcrdx", // PPC_INS_QVLPCRDX, "qvlpcrsx", // PPC_INS_QVLPCRSX, "qvstfcdux", // PPC_INS_QVSTFCDUX, "qvstfcduxa", // PPC_INS_QVSTFCDUXA, "qvstfcduxi", // PPC_INS_QVSTFCDUXI, "qvstfcduxia", // PPC_INS_QVSTFCDUXIA, "qvstfcdx", // PPC_INS_QVSTFCDX, "qvstfcdxa", // PPC_INS_QVSTFCDXA, "qvstfcdxi", // PPC_INS_QVSTFCDXI, "qvstfcdxia", // PPC_INS_QVSTFCDXIA, "qvstfcsux", // PPC_INS_QVSTFCSUX, "qvstfcsuxa", // PPC_INS_QVSTFCSUXA, "qvstfcsuxi", // PPC_INS_QVSTFCSUXI, "qvstfcsuxia", // PPC_INS_QVSTFCSUXIA, "qvstfcsx", // PPC_INS_QVSTFCSX, "qvstfcsxa", // PPC_INS_QVSTFCSXA, "qvstfcsxi", // PPC_INS_QVSTFCSXI, "qvstfcsxia", // PPC_INS_QVSTFCSXIA, "qvstfdux", // PPC_INS_QVSTFDUX, "qvstfduxa", // PPC_INS_QVSTFDUXA, "qvstfduxi", // PPC_INS_QVSTFDUXI, "qvstfduxia", // PPC_INS_QVSTFDUXIA, "qvstfdx", // PPC_INS_QVSTFDX, "qvstfdxa", // PPC_INS_QVSTFDXA, "qvstfdxi", // PPC_INS_QVSTFDXI, "qvstfdxia", // PPC_INS_QVSTFDXIA, "qvstfiwx", // PPC_INS_QVSTFIWX, "qvstfiwxa", // PPC_INS_QVSTFIWXA, "qvstfsux", // PPC_INS_QVSTFSUX, "qvstfsuxa", // PPC_INS_QVSTFSUXA, "qvstfsuxi", // PPC_INS_QVSTFSUXI, "qvstfsuxia", // PPC_INS_QVSTFSUXIA, "qvstfsx", // PPC_INS_QVSTFSX, "qvstfsxa", // PPC_INS_QVSTFSXA, "qvstfsxi", // PPC_INS_QVSTFSXI, "qvstfsxia", // PPC_INS_QVSTFSXIA, "rfci", // PPC_INS_RFCI, "rfdi", // PPC_INS_RFDI, "rfebb", // PPC_INS_RFEBB, "rfi", // PPC_INS_RFI, "rfid", // PPC_INS_RFID, "rfmci", // PPC_INS_RFMCI, "rldcl", // PPC_INS_RLDCL, "rldcr", // PPC_INS_RLDCR, "rldic", // PPC_INS_RLDIC, "rldicl", // PPC_INS_RLDICL, "rldicr", // PPC_INS_RLDICR, "rldimi", // PPC_INS_RLDIMI, "rlwimi", // PPC_INS_RLWIMI, "rlwinm", // PPC_INS_RLWINM, "rlwnm", // PPC_INS_RLWNM, "rotld", // PPC_INS_ROTLD, "rotldi", // PPC_INS_ROTLDI, "rotlw", // PPC_INS_ROTLW, "rotlwi", // PPC_INS_ROTLWI, "rotrdi", // PPC_INS_ROTRDI, "rotrwi", // PPC_INS_ROTRWI, "sc", // PPC_INS_SC, "setb", // PPC_INS_SETB, "slbia", // PPC_INS_SLBIA, "slbie", // PPC_INS_SLBIE, "slbieg", // PPC_INS_SLBIEG, "slbmfee", // PPC_INS_SLBMFEE, "slbmfev", // PPC_INS_SLBMFEV, "slbmte", // PPC_INS_SLBMTE, "slbsync", // PPC_INS_SLBSYNC, "sld", // PPC_INS_SLD, "sldi", // PPC_INS_SLDI, "slw", // PPC_INS_SLW, "slwi", // PPC_INS_SLWI, "srad", // PPC_INS_SRAD, "sradi", // PPC_INS_SRADI, "sraw", // PPC_INS_SRAW, "srawi", // PPC_INS_SRAWI, "srd", // PPC_INS_SRD, "srdi", // PPC_INS_SRDI, "srw", // PPC_INS_SRW, "srwi", // PPC_INS_SRWI, "stb", // PPC_INS_STB, "stbcix", // PPC_INS_STBCIX, "stbcx", // PPC_INS_STBCX, "stbepx", // PPC_INS_STBEPX, "stbu", // PPC_INS_STBU, "stbux", // PPC_INS_STBUX, "stbx", // PPC_INS_STBX, "std", // PPC_INS_STD, "stdat", // PPC_INS_STDAT, "stdbrx", // PPC_INS_STDBRX, "stdcix", // PPC_INS_STDCIX, "stdcx", // PPC_INS_STDCX, "stdu", // PPC_INS_STDU, "stdux", // PPC_INS_STDUX, "stdx", // PPC_INS_STDX, "stfd", // PPC_INS_STFD, "stfdepx", // PPC_INS_STFDEPX, "stfdu", // PPC_INS_STFDU, "stfdux", // PPC_INS_STFDUX, "stfdx", // PPC_INS_STFDX, "stfiwx", // PPC_INS_STFIWX, "stfs", // PPC_INS_STFS, "stfsu", // PPC_INS_STFSU, "stfsux", // PPC_INS_STFSUX, "stfsx", // PPC_INS_STFSX, "sth", // PPC_INS_STH, "sthbrx", // PPC_INS_STHBRX, "sthcix", // PPC_INS_STHCIX, "sthcx", // PPC_INS_STHCX, "sthepx", // PPC_INS_STHEPX, "sthu", // PPC_INS_STHU, "sthux", // PPC_INS_STHUX, "sthx", // PPC_INS_STHX, "stmw", // PPC_INS_STMW, "stop", // PPC_INS_STOP, "stswi", // PPC_INS_STSWI, "stvebx", // PPC_INS_STVEBX, "stvehx", // PPC_INS_STVEHX, "stvewx", // PPC_INS_STVEWX, "stvx", // PPC_INS_STVX, "stvxl", // PPC_INS_STVXL, "stw", // PPC_INS_STW, "stwat", // PPC_INS_STWAT, "stwbrx", // PPC_INS_STWBRX, "stwcix", // PPC_INS_STWCIX, "stwcx", // PPC_INS_STWCX, "stwepx", // PPC_INS_STWEPX, "stwu", // PPC_INS_STWU, "stwux", // PPC_INS_STWUX, "stwx", // PPC_INS_STWX, "stxsd", // PPC_INS_STXSD, "stxsdx", // PPC_INS_STXSDX, "stxsibx", // PPC_INS_STXSIBX, "stxsihx", // PPC_INS_STXSIHX, "stxsiwx", // PPC_INS_STXSIWX, "stxssp", // PPC_INS_STXSSP, "stxsspx", // PPC_INS_STXSSPX, "stxv", // PPC_INS_STXV, "stxvb16x", // PPC_INS_STXVB16X, "stxvd2x", // PPC_INS_STXVD2X, "stxvh8x", // PPC_INS_STXVH8X, "stxvl", // PPC_INS_STXVL, "stxvll", // PPC_INS_STXVLL, "stxvw4x", // PPC_INS_STXVW4X, "stxvx", // PPC_INS_STXVX, "sub", // PPC_INS_SUB, "subc", // PPC_INS_SUBC, "subf", // PPC_INS_SUBF, "subfc", // PPC_INS_SUBFC, "subfe", // PPC_INS_SUBFE, "subfic", // PPC_INS_SUBFIC, "subfme", // PPC_INS_SUBFME, "subfze", // PPC_INS_SUBFZE, "subi", // PPC_INS_SUBI, "subic", // PPC_INS_SUBIC, "subis", // PPC_INS_SUBIS, "subpcis", // PPC_INS_SUBPCIS, "sync", // PPC_INS_SYNC, "tabort", // PPC_INS_TABORT, "tabortdc", // PPC_INS_TABORTDC, "tabortdci", // PPC_INS_TABORTDCI, "tabortwc", // PPC_INS_TABORTWC, "tabortwci", // PPC_INS_TABORTWCI, "tbegin", // PPC_INS_TBEGIN, "tcheck", // PPC_INS_TCHECK, "td", // PPC_INS_TD, "tdeq", // PPC_INS_TDEQ, "tdeqi", // PPC_INS_TDEQI, "tdge", // PPC_INS_TDGE, "tdgei", // PPC_INS_TDGEI, "tdgt", // PPC_INS_TDGT, "tdgti", // PPC_INS_TDGTI, "tdi", // PPC_INS_TDI, "tdle", // PPC_INS_TDLE, "tdlei", // PPC_INS_TDLEI, "tdlge", // PPC_INS_TDLGE, "tdlgei", // PPC_INS_TDLGEI, "tdlgt", // PPC_INS_TDLGT, "tdlgti", // PPC_INS_TDLGTI, "tdlle", // PPC_INS_TDLLE, "tdllei", // PPC_INS_TDLLEI, "tdllt", // PPC_INS_TDLLT, "tdllti", // PPC_INS_TDLLTI, "tdlng", // PPC_INS_TDLNG, "tdlngi", // PPC_INS_TDLNGI, "tdlnl", // PPC_INS_TDLNL, "tdlnli", // PPC_INS_TDLNLI, "tdlt", // PPC_INS_TDLT, "tdlti", // PPC_INS_TDLTI, "tdne", // PPC_INS_TDNE, "tdnei", // PPC_INS_TDNEI, "tdng", // PPC_INS_TDNG, "tdngi", // PPC_INS_TDNGI, "tdnl", // PPC_INS_TDNL, "tdnli", // PPC_INS_TDNLI, "tdu", // PPC_INS_TDU, "tdui", // PPC_INS_TDUI, "tend", // PPC_INS_TEND, "tlbia", // PPC_INS_TLBIA, "tlbie", // PPC_INS_TLBIE, "tlbiel", // PPC_INS_TLBIEL, "tlbivax", // PPC_INS_TLBIVAX, "tlbld", // PPC_INS_TLBLD, "tlbli", // PPC_INS_TLBLI, "tlbre", // PPC_INS_TLBRE, "tlbrehi", // PPC_INS_TLBREHI, "tlbrelo", // PPC_INS_TLBRELO, "tlbsx", // PPC_INS_TLBSX, "tlbsync", // PPC_INS_TLBSYNC, "tlbwe", // PPC_INS_TLBWE, "tlbwehi", // PPC_INS_TLBWEHI, "tlbwelo", // PPC_INS_TLBWELO, "trap", // PPC_INS_TRAP, "trechkpt", // PPC_INS_TRECHKPT, "treclaim", // PPC_INS_TRECLAIM, "tsr", // PPC_INS_TSR, "tw", // PPC_INS_TW, "tweq", // PPC_INS_TWEQ, "tweqi", // PPC_INS_TWEQI, "twge", // PPC_INS_TWGE, "twgei", // PPC_INS_TWGEI, "twgt", // PPC_INS_TWGT, "twgti", // PPC_INS_TWGTI, "twi", // PPC_INS_TWI, "twle", // PPC_INS_TWLE, "twlei", // PPC_INS_TWLEI, "twlge", // PPC_INS_TWLGE, "twlgei", // PPC_INS_TWLGEI, "twlgt", // PPC_INS_TWLGT, "twlgti", // PPC_INS_TWLGTI, "twlle", // PPC_INS_TWLLE, "twllei", // PPC_INS_TWLLEI, "twllt", // PPC_INS_TWLLT, "twllti", // PPC_INS_TWLLTI, "twlng", // PPC_INS_TWLNG, "twlngi", // PPC_INS_TWLNGI, "twlnl", // PPC_INS_TWLNL, "twlnli", // PPC_INS_TWLNLI, "twlt", // PPC_INS_TWLT, "twlti", // PPC_INS_TWLTI, "twne", // PPC_INS_TWNE, "twnei", // PPC_INS_TWNEI, "twng", // PPC_INS_TWNG, "twngi", // PPC_INS_TWNGI, "twnl", // PPC_INS_TWNL, "twnli", // PPC_INS_TWNLI, "twu", // PPC_INS_TWU, "twui", // PPC_INS_TWUI, "vabsdub", // PPC_INS_VABSDUB, "vabsduh", // PPC_INS_VABSDUH, "vabsduw", // PPC_INS_VABSDUW, "vaddcuq", // PPC_INS_VADDCUQ, "vaddcuw", // PPC_INS_VADDCUW, "vaddecuq", // PPC_INS_VADDECUQ, "vaddeuqm", // PPC_INS_VADDEUQM, "vaddfp", // PPC_INS_VADDFP, "vaddsbs", // PPC_INS_VADDSBS, "vaddshs", // PPC_INS_VADDSHS, "vaddsws", // PPC_INS_VADDSWS, "vaddubm", // PPC_INS_VADDUBM, "vaddubs", // PPC_INS_VADDUBS, "vaddudm", // PPC_INS_VADDUDM, "vadduhm", // PPC_INS_VADDUHM, "vadduhs", // PPC_INS_VADDUHS, "vadduqm", // PPC_INS_VADDUQM, "vadduwm", // PPC_INS_VADDUWM, "vadduws", // PPC_INS_VADDUWS, "vand", // PPC_INS_VAND, "vandc", // PPC_INS_VANDC, "vavgsb", // PPC_INS_VAVGSB, "vavgsh", // PPC_INS_VAVGSH, "vavgsw", // PPC_INS_VAVGSW, "vavgub", // PPC_INS_VAVGUB, "vavguh", // PPC_INS_VAVGUH, "vavguw", // PPC_INS_VAVGUW, "vbpermd", // PPC_INS_VBPERMD, "vbpermq", // PPC_INS_VBPERMQ, "vcfsx", // PPC_INS_VCFSX, "vcfux", // PPC_INS_VCFUX, "vcipher", // PPC_INS_VCIPHER, "vcipherlast", // PPC_INS_VCIPHERLAST, "vclzb", // PPC_INS_VCLZB, "vclzd", // PPC_INS_VCLZD, "vclzh", // PPC_INS_VCLZH, "vclzlsbb", // PPC_INS_VCLZLSBB, "vclzw", // PPC_INS_VCLZW, "vcmpbfp", // PPC_INS_VCMPBFP, "vcmpeqfp", // PPC_INS_VCMPEQFP, "vcmpequb", // PPC_INS_VCMPEQUB, "vcmpequd", // PPC_INS_VCMPEQUD, "vcmpequh", // PPC_INS_VCMPEQUH, "vcmpequw", // PPC_INS_VCMPEQUW, "vcmpgefp", // PPC_INS_VCMPGEFP, "vcmpgtfp", // PPC_INS_VCMPGTFP, "vcmpgtsb", // PPC_INS_VCMPGTSB, "vcmpgtsd", // PPC_INS_VCMPGTSD, "vcmpgtsh", // PPC_INS_VCMPGTSH, "vcmpgtsw", // PPC_INS_VCMPGTSW, "vcmpgtub", // PPC_INS_VCMPGTUB, "vcmpgtud", // PPC_INS_VCMPGTUD, "vcmpgtuh", // PPC_INS_VCMPGTUH, "vcmpgtuw", // PPC_INS_VCMPGTUW, "vcmpneb", // PPC_INS_VCMPNEB, "vcmpneh", // PPC_INS_VCMPNEH, "vcmpnew", // PPC_INS_VCMPNEW, "vcmpnezb", // PPC_INS_VCMPNEZB, "vcmpnezh", // PPC_INS_VCMPNEZH, "vcmpnezw", // PPC_INS_VCMPNEZW, "vctsxs", // PPC_INS_VCTSXS, "vctuxs", // PPC_INS_VCTUXS, "vctzb", // PPC_INS_VCTZB, "vctzd", // PPC_INS_VCTZD, "vctzh", // PPC_INS_VCTZH, "vctzlsbb", // PPC_INS_VCTZLSBB, "vctzw", // PPC_INS_VCTZW, "veqv", // PPC_INS_VEQV, "vexptefp", // PPC_INS_VEXPTEFP, "vextractd", // PPC_INS_VEXTRACTD, "vextractub", // PPC_INS_VEXTRACTUB, "vextractuh", // PPC_INS_VEXTRACTUH, "vextractuw", // PPC_INS_VEXTRACTUW, "vextsb2d", // PPC_INS_VEXTSB2D, "vextsb2w", // PPC_INS_VEXTSB2W, "vextsh2d", // PPC_INS_VEXTSH2D, "vextsh2w", // PPC_INS_VEXTSH2W, "vextsw2d", // PPC_INS_VEXTSW2D, "vextublx", // PPC_INS_VEXTUBLX, "vextubrx", // PPC_INS_VEXTUBRX, "vextuhlx", // PPC_INS_VEXTUHLX, "vextuhrx", // PPC_INS_VEXTUHRX, "vextuwlx", // PPC_INS_VEXTUWLX, "vextuwrx", // PPC_INS_VEXTUWRX, "vgbbd", // PPC_INS_VGBBD, "vinsertb", // PPC_INS_VINSERTB, "vinsertd", // PPC_INS_VINSERTD, "vinserth", // PPC_INS_VINSERTH, "vinsertw", // PPC_INS_VINSERTW, "vlogefp", // PPC_INS_VLOGEFP, "vmaddfp", // PPC_INS_VMADDFP, "vmaxfp", // PPC_INS_VMAXFP, "vmaxsb", // PPC_INS_VMAXSB, "vmaxsd", // PPC_INS_VMAXSD, "vmaxsh", // PPC_INS_VMAXSH, "vmaxsw", // PPC_INS_VMAXSW, "vmaxub", // PPC_INS_VMAXUB, "vmaxud", // PPC_INS_VMAXUD, "vmaxuh", // PPC_INS_VMAXUH, "vmaxuw", // PPC_INS_VMAXUW, "vmhaddshs", // PPC_INS_VMHADDSHS, "vmhraddshs", // PPC_INS_VMHRADDSHS, "vminfp", // PPC_INS_VMINFP, "vminsb", // PPC_INS_VMINSB, "vminsd", // PPC_INS_VMINSD, "vminsh", // PPC_INS_VMINSH, "vminsw", // PPC_INS_VMINSW, "vminub", // PPC_INS_VMINUB, "vminud", // PPC_INS_VMINUD, "vminuh", // PPC_INS_VMINUH, "vminuw", // PPC_INS_VMINUW, "vmladduhm", // PPC_INS_VMLADDUHM, "vmr", // PPC_INS_VMR, "vmrgew", // PPC_INS_VMRGEW, "vmrghb", // PPC_INS_VMRGHB, "vmrghh", // PPC_INS_VMRGHH, "vmrghw", // PPC_INS_VMRGHW, "vmrglb", // PPC_INS_VMRGLB, "vmrglh", // PPC_INS_VMRGLH, "vmrglw", // PPC_INS_VMRGLW, "vmrgow", // PPC_INS_VMRGOW, "vmsummbm", // PPC_INS_VMSUMMBM, "vmsumshm", // PPC_INS_VMSUMSHM, "vmsumshs", // PPC_INS_VMSUMSHS, "vmsumubm", // PPC_INS_VMSUMUBM, "vmsumuhm", // PPC_INS_VMSUMUHM, "vmsumuhs", // PPC_INS_VMSUMUHS, "vmul10cuq", // PPC_INS_VMUL10CUQ, "vmul10ecuq", // PPC_INS_VMUL10ECUQ, "vmul10euq", // PPC_INS_VMUL10EUQ, "vmul10uq", // PPC_INS_VMUL10UQ, "vmulesb", // PPC_INS_VMULESB, "vmulesh", // PPC_INS_VMULESH, "vmulesw", // PPC_INS_VMULESW, "vmuleub", // PPC_INS_VMULEUB, "vmuleuh", // PPC_INS_VMULEUH, "vmuleuw", // PPC_INS_VMULEUW, "vmulosb", // PPC_INS_VMULOSB, "vmulosh", // PPC_INS_VMULOSH, "vmulosw", // PPC_INS_VMULOSW, "vmuloub", // PPC_INS_VMULOUB, "vmulouh", // PPC_INS_VMULOUH, "vmulouw", // PPC_INS_VMULOUW, "vmuluwm", // PPC_INS_VMULUWM, "vnand", // PPC_INS_VNAND, "vncipher", // PPC_INS_VNCIPHER, "vncipherlast", // PPC_INS_VNCIPHERLAST, "vnegd", // PPC_INS_VNEGD, "vnegw", // PPC_INS_VNEGW, "vnmsubfp", // PPC_INS_VNMSUBFP, "vnor", // PPC_INS_VNOR, "vnot", // PPC_INS_VNOT, "vor", // PPC_INS_VOR, "vorc", // PPC_INS_VORC, "vperm", // PPC_INS_VPERM, "vpermr", // PPC_INS_VPERMR, "vpermxor", // PPC_INS_VPERMXOR, "vpkpx", // PPC_INS_VPKPX, "vpksdss", // PPC_INS_VPKSDSS, "vpksdus", // PPC_INS_VPKSDUS, "vpkshss", // PPC_INS_VPKSHSS, "vpkshus", // PPC_INS_VPKSHUS, "vpkswss", // PPC_INS_VPKSWSS, "vpkswus", // PPC_INS_VPKSWUS, "vpkudum", // PPC_INS_VPKUDUM, "vpkudus", // PPC_INS_VPKUDUS, "vpkuhum", // PPC_INS_VPKUHUM, "vpkuhus", // PPC_INS_VPKUHUS, "vpkuwum", // PPC_INS_VPKUWUM, "vpkuwus", // PPC_INS_VPKUWUS, "vpmsumb", // PPC_INS_VPMSUMB, "vpmsumd", // PPC_INS_VPMSUMD, "vpmsumh", // PPC_INS_VPMSUMH, "vpmsumw", // PPC_INS_VPMSUMW, "vpopcntb", // PPC_INS_VPOPCNTB, "vpopcntd", // PPC_INS_VPOPCNTD, "vpopcnth", // PPC_INS_VPOPCNTH, "vpopcntw", // PPC_INS_VPOPCNTW, "vprtybd", // PPC_INS_VPRTYBD, "vprtybq", // PPC_INS_VPRTYBQ, "vprtybw", // PPC_INS_VPRTYBW, "vrefp", // PPC_INS_VREFP, "vrfim", // PPC_INS_VRFIM, "vrfin", // PPC_INS_VRFIN, "vrfip", // PPC_INS_VRFIP, "vrfiz", // PPC_INS_VRFIZ, "vrlb", // PPC_INS_VRLB, "vrld", // PPC_INS_VRLD, "vrldmi", // PPC_INS_VRLDMI, "vrldnm", // PPC_INS_VRLDNM, "vrlh", // PPC_INS_VRLH, "vrlw", // PPC_INS_VRLW, "vrlwmi", // PPC_INS_VRLWMI, "vrlwnm", // PPC_INS_VRLWNM, "vrsqrtefp", // PPC_INS_VRSQRTEFP, "vsbox", // PPC_INS_VSBOX, "vsel", // PPC_INS_VSEL, "vshasigmad", // PPC_INS_VSHASIGMAD, "vshasigmaw", // PPC_INS_VSHASIGMAW, "vsl", // PPC_INS_VSL, "vslb", // PPC_INS_VSLB, "vsld", // PPC_INS_VSLD, "vsldoi", // PPC_INS_VSLDOI, "vslh", // PPC_INS_VSLH, "vslo", // PPC_INS_VSLO, "vslv", // PPC_INS_VSLV, "vslw", // PPC_INS_VSLW, "vspltb", // PPC_INS_VSPLTB, "vsplth", // PPC_INS_VSPLTH, "vspltisb", // PPC_INS_VSPLTISB, "vspltish", // PPC_INS_VSPLTISH, "vspltisw", // PPC_INS_VSPLTISW, "vspltw", // PPC_INS_VSPLTW, "vsr", // PPC_INS_VSR, "vsrab", // PPC_INS_VSRAB, "vsrad", // PPC_INS_VSRAD, "vsrah", // PPC_INS_VSRAH, "vsraw", // PPC_INS_VSRAW, "vsrb", // PPC_INS_VSRB, "vsrd", // PPC_INS_VSRD, "vsrh", // PPC_INS_VSRH, "vsro", // PPC_INS_VSRO, "vsrv", // PPC_INS_VSRV, "vsrw", // PPC_INS_VSRW, "vsubcuq", // PPC_INS_VSUBCUQ, "vsubcuw", // PPC_INS_VSUBCUW, "vsubecuq", // PPC_INS_VSUBECUQ, "vsubeuqm", // PPC_INS_VSUBEUQM, "vsubfp", // PPC_INS_VSUBFP, "vsubsbs", // PPC_INS_VSUBSBS, "vsubshs", // PPC_INS_VSUBSHS, "vsubsws", // PPC_INS_VSUBSWS, "vsububm", // PPC_INS_VSUBUBM, "vsububs", // PPC_INS_VSUBUBS, "vsubudm", // PPC_INS_VSUBUDM, "vsubuhm", // PPC_INS_VSUBUHM, "vsubuhs", // PPC_INS_VSUBUHS, "vsubuqm", // PPC_INS_VSUBUQM, "vsubuwm", // PPC_INS_VSUBUWM, "vsubuws", // PPC_INS_VSUBUWS, "vsum2sws", // PPC_INS_VSUM2SWS, "vsum4sbs", // PPC_INS_VSUM4SBS, "vsum4shs", // PPC_INS_VSUM4SHS, "vsum4ubs", // PPC_INS_VSUM4UBS, "vsumsws", // PPC_INS_VSUMSWS, "vupkhpx", // PPC_INS_VUPKHPX, "vupkhsb", // PPC_INS_VUPKHSB, "vupkhsh", // PPC_INS_VUPKHSH, "vupkhsw", // PPC_INS_VUPKHSW, "vupklpx", // PPC_INS_VUPKLPX, "vupklsb", // PPC_INS_VUPKLSB, "vupklsh", // PPC_INS_VUPKLSH, "vupklsw", // PPC_INS_VUPKLSW, "vxor", // PPC_INS_VXOR, "wait", // PPC_INS_WAIT, "waitimpl", // PPC_INS_WAITIMPL, "waitrsv", // PPC_INS_WAITRSV, "wrtee", // PPC_INS_WRTEE, "wrteei", // PPC_INS_WRTEEI, "xnop", // PPC_INS_XNOP, "xor", // PPC_INS_XOR, "xori", // PPC_INS_XORI, "xoris", // PPC_INS_XORIS, "xsabsdp", // PPC_INS_XSABSDP, "xsabsqp", // PPC_INS_XSABSQP, "xsadddp", // PPC_INS_XSADDDP, "xsaddqp", // PPC_INS_XSADDQP, "xsaddqpo", // PPC_INS_XSADDQPO, "xsaddsp", // PPC_INS_XSADDSP, "xscmpeqdp", // PPC_INS_XSCMPEQDP, "xscmpexpdp", // PPC_INS_XSCMPEXPDP, "xscmpexpqp", // PPC_INS_XSCMPEXPQP, "xscmpgedp", // PPC_INS_XSCMPGEDP, "xscmpgtdp", // PPC_INS_XSCMPGTDP, "xscmpodp", // PPC_INS_XSCMPODP, "xscmpoqp", // PPC_INS_XSCMPOQP, "xscmpudp", // PPC_INS_XSCMPUDP, "xscmpuqp", // PPC_INS_XSCMPUQP, "xscpsgndp", // PPC_INS_XSCPSGNDP, "xscpsgnqp", // PPC_INS_XSCPSGNQP, "xscvdphp", // PPC_INS_XSCVDPHP, "xscvdpqp", // PPC_INS_XSCVDPQP, "xscvdpsp", // PPC_INS_XSCVDPSP, "xscvdpspn", // PPC_INS_XSCVDPSPN, "xscvdpsxds", // PPC_INS_XSCVDPSXDS, "xscvdpsxws", // PPC_INS_XSCVDPSXWS, "xscvdpuxds", // PPC_INS_XSCVDPUXDS, "xscvdpuxws", // PPC_INS_XSCVDPUXWS, "xscvhpdp", // PPC_INS_XSCVHPDP, "xscvqpdp", // PPC_INS_XSCVQPDP, "xscvqpdpo", // PPC_INS_XSCVQPDPO, "xscvqpsdz", // PPC_INS_XSCVQPSDZ, "xscvqpswz", // PPC_INS_XSCVQPSWZ, "xscvqpudz", // PPC_INS_XSCVQPUDZ, "xscvqpuwz", // PPC_INS_XSCVQPUWZ, "xscvsdqp", // PPC_INS_XSCVSDQP, "xscvspdp", // PPC_INS_XSCVSPDP, "xscvspdpn", // PPC_INS_XSCVSPDPN, "xscvsxddp", // PPC_INS_XSCVSXDDP, "xscvsxdsp", // PPC_INS_XSCVSXDSP, "xscvudqp", // PPC_INS_XSCVUDQP, "xscvuxddp", // PPC_INS_XSCVUXDDP, "xscvuxdsp", // PPC_INS_XSCVUXDSP, "xsdivdp", // PPC_INS_XSDIVDP, "xsdivqp", // PPC_INS_XSDIVQP, "xsdivqpo", // PPC_INS_XSDIVQPO, "xsdivsp", // PPC_INS_XSDIVSP, "xsiexpdp", // PPC_INS_XSIEXPDP, "xsiexpqp", // PPC_INS_XSIEXPQP, "xsmaddadp", // PPC_INS_XSMADDADP, "xsmaddasp", // PPC_INS_XSMADDASP, "xsmaddmdp", // PPC_INS_XSMADDMDP, "xsmaddmsp", // PPC_INS_XSMADDMSP, "xsmaddqp", // PPC_INS_XSMADDQP, "xsmaddqpo", // PPC_INS_XSMADDQPO, "xsmaxcdp", // PPC_INS_XSMAXCDP, "xsmaxdp", // PPC_INS_XSMAXDP, "xsmaxjdp", // PPC_INS_XSMAXJDP, "xsmincdp", // PPC_INS_XSMINCDP, "xsmindp", // PPC_INS_XSMINDP, "xsminjdp", // PPC_INS_XSMINJDP, "xsmsubadp", // PPC_INS_XSMSUBADP, "xsmsubasp", // PPC_INS_XSMSUBASP, "xsmsubmdp", // PPC_INS_XSMSUBMDP, "xsmsubmsp", // PPC_INS_XSMSUBMSP, "xsmsubqp", // PPC_INS_XSMSUBQP, "xsmsubqpo", // PPC_INS_XSMSUBQPO, "xsmuldp", // PPC_INS_XSMULDP, "xsmulqp", // PPC_INS_XSMULQP, "xsmulqpo", // PPC_INS_XSMULQPO, "xsmulsp", // PPC_INS_XSMULSP, "xsnabsdp", // PPC_INS_XSNABSDP, "xsnabsqp", // PPC_INS_XSNABSQP, "xsnegdp", // PPC_INS_XSNEGDP, "xsnegqp", // PPC_INS_XSNEGQP, "xsnmaddadp", // PPC_INS_XSNMADDADP, "xsnmaddasp", // PPC_INS_XSNMADDASP, "xsnmaddmdp", // PPC_INS_XSNMADDMDP, "xsnmaddmsp", // PPC_INS_XSNMADDMSP, "xsnmaddqp", // PPC_INS_XSNMADDQP, "xsnmaddqpo", // PPC_INS_XSNMADDQPO, "xsnmsubadp", // PPC_INS_XSNMSUBADP, "xsnmsubasp", // PPC_INS_XSNMSUBASP, "xsnmsubmdp", // PPC_INS_XSNMSUBMDP, "xsnmsubmsp", // PPC_INS_XSNMSUBMSP, "xsnmsubqp", // PPC_INS_XSNMSUBQP, "xsnmsubqpo", // PPC_INS_XSNMSUBQPO, "xsrdpi", // PPC_INS_XSRDPI, "xsrdpic", // PPC_INS_XSRDPIC, "xsrdpim", // PPC_INS_XSRDPIM, "xsrdpip", // PPC_INS_XSRDPIP, "xsrdpiz", // PPC_INS_XSRDPIZ, "xsredp", // PPC_INS_XSREDP, "xsresp", // PPC_INS_XSRESP, "xsrqpi", // PPC_INS_XSRQPI, "xsrqpix", // PPC_INS_XSRQPIX, "xsrqpxp", // PPC_INS_XSRQPXP, "xsrsp", // PPC_INS_XSRSP, "xsrsqrtedp", // PPC_INS_XSRSQRTEDP, "xsrsqrtesp", // PPC_INS_XSRSQRTESP, "xssqrtdp", // PPC_INS_XSSQRTDP, "xssqrtqp", // PPC_INS_XSSQRTQP, "xssqrtqpo", // PPC_INS_XSSQRTQPO, "xssqrtsp", // PPC_INS_XSSQRTSP, "xssubdp", // PPC_INS_XSSUBDP, "xssubqp", // PPC_INS_XSSUBQP, "xssubqpo", // PPC_INS_XSSUBQPO, "xssubsp", // PPC_INS_XSSUBSP, "xstdivdp", // PPC_INS_XSTDIVDP, "xstsqrtdp", // PPC_INS_XSTSQRTDP, "xststdcdp", // PPC_INS_XSTSTDCDP, "xststdcqp", // PPC_INS_XSTSTDCQP, "xststdcsp", // PPC_INS_XSTSTDCSP, "xsxexpdp", // PPC_INS_XSXEXPDP, "xsxexpqp", // PPC_INS_XSXEXPQP, "xsxsigdp", // PPC_INS_XSXSIGDP, "xsxsigqp", // PPC_INS_XSXSIGQP, "xvabsdp", // PPC_INS_XVABSDP, "xvabssp", // PPC_INS_XVABSSP, "xvadddp", // PPC_INS_XVADDDP, "xvaddsp", // PPC_INS_XVADDSP, "xvcmpeqdp", // PPC_INS_XVCMPEQDP, "xvcmpeqsp", // PPC_INS_XVCMPEQSP, "xvcmpgedp", // PPC_INS_XVCMPGEDP, "xvcmpgesp", // PPC_INS_XVCMPGESP, "xvcmpgtdp", // PPC_INS_XVCMPGTDP, "xvcmpgtsp", // PPC_INS_XVCMPGTSP, "xvcpsgndp", // PPC_INS_XVCPSGNDP, "xvcpsgnsp", // PPC_INS_XVCPSGNSP, "xvcvdpsp", // PPC_INS_XVCVDPSP, "xvcvdpsxds", // PPC_INS_XVCVDPSXDS, "xvcvdpsxws", // PPC_INS_XVCVDPSXWS, "xvcvdpuxds", // PPC_INS_XVCVDPUXDS, "xvcvdpuxws", // PPC_INS_XVCVDPUXWS, "xvcvhpsp", // PPC_INS_XVCVHPSP, "xvcvspdp", // PPC_INS_XVCVSPDP, "xvcvsphp", // PPC_INS_XVCVSPHP, "xvcvspsxds", // PPC_INS_XVCVSPSXDS, "xvcvspsxws", // PPC_INS_XVCVSPSXWS, "xvcvspuxds", // PPC_INS_XVCVSPUXDS, "xvcvspuxws", // PPC_INS_XVCVSPUXWS, "xvcvsxddp", // PPC_INS_XVCVSXDDP, "xvcvsxdsp", // PPC_INS_XVCVSXDSP, "xvcvsxwdp", // PPC_INS_XVCVSXWDP, "xvcvsxwsp", // PPC_INS_XVCVSXWSP, "xvcvuxddp", // PPC_INS_XVCVUXDDP, "xvcvuxdsp", // PPC_INS_XVCVUXDSP, "xvcvuxwdp", // PPC_INS_XVCVUXWDP, "xvcvuxwsp", // PPC_INS_XVCVUXWSP, "xvdivdp", // PPC_INS_XVDIVDP, "xvdivsp", // PPC_INS_XVDIVSP, "xviexpdp", // PPC_INS_XVIEXPDP, "xviexpsp", // PPC_INS_XVIEXPSP, "xvmaddadp", // PPC_INS_XVMADDADP, "xvmaddasp", // PPC_INS_XVMADDASP, "xvmaddmdp", // PPC_INS_XVMADDMDP, "xvmaddmsp", // PPC_INS_XVMADDMSP, "xvmaxdp", // PPC_INS_XVMAXDP, "xvmaxsp", // PPC_INS_XVMAXSP, "xvmindp", // PPC_INS_XVMINDP, "xvminsp", // PPC_INS_XVMINSP, "xvmovdp", // PPC_INS_XVMOVDP, "xvmovsp", // PPC_INS_XVMOVSP, "xvmsubadp", // PPC_INS_XVMSUBADP, "xvmsubasp", // PPC_INS_XVMSUBASP, "xvmsubmdp", // PPC_INS_XVMSUBMDP, "xvmsubmsp", // PPC_INS_XVMSUBMSP, "xvmuldp", // PPC_INS_XVMULDP, "xvmulsp", // PPC_INS_XVMULSP, "xvnabsdp", // PPC_INS_XVNABSDP, "xvnabssp", // PPC_INS_XVNABSSP, "xvnegdp", // PPC_INS_XVNEGDP, "xvnegsp", // PPC_INS_XVNEGSP, "xvnmaddadp", // PPC_INS_XVNMADDADP, "xvnmaddasp", // PPC_INS_XVNMADDASP, "xvnmaddmdp", // PPC_INS_XVNMADDMDP, "xvnmaddmsp", // PPC_INS_XVNMADDMSP, "xvnmsubadp", // PPC_INS_XVNMSUBADP, "xvnmsubasp", // PPC_INS_XVNMSUBASP, "xvnmsubmdp", // PPC_INS_XVNMSUBMDP, "xvnmsubmsp", // PPC_INS_XVNMSUBMSP, "xvrdpi", // PPC_INS_XVRDPI, "xvrdpic", // PPC_INS_XVRDPIC, "xvrdpim", // PPC_INS_XVRDPIM, "xvrdpip", // PPC_INS_XVRDPIP, "xvrdpiz", // PPC_INS_XVRDPIZ, "xvredp", // PPC_INS_XVREDP, "xvresp", // PPC_INS_XVRESP, "xvrspi", // PPC_INS_XVRSPI, "xvrspic", // PPC_INS_XVRSPIC, "xvrspim", // PPC_INS_XVRSPIM, "xvrspip", // PPC_INS_XVRSPIP, "xvrspiz", // PPC_INS_XVRSPIZ, "xvrsqrtedp", // PPC_INS_XVRSQRTEDP, "xvrsqrtesp", // PPC_INS_XVRSQRTESP, "xvsqrtdp", // PPC_INS_XVSQRTDP, "xvsqrtsp", // PPC_INS_XVSQRTSP, "xvsubdp", // PPC_INS_XVSUBDP, "xvsubsp", // PPC_INS_XVSUBSP, "xvtdivdp", // PPC_INS_XVTDIVDP, "xvtdivsp", // PPC_INS_XVTDIVSP, "xvtsqrtdp", // PPC_INS_XVTSQRTDP, "xvtsqrtsp", // PPC_INS_XVTSQRTSP, "xvtstdcdp", // PPC_INS_XVTSTDCDP, "xvtstdcsp", // PPC_INS_XVTSTDCSP, "xvxexpdp", // PPC_INS_XVXEXPDP, "xvxexpsp", // PPC_INS_XVXEXPSP, "xvxsigdp", // PPC_INS_XVXSIGDP, "xvxsigsp", // PPC_INS_XVXSIGSP, "xxbrd", // PPC_INS_XXBRD, "xxbrh", // PPC_INS_XXBRH, "xxbrq", // PPC_INS_XXBRQ, "xxbrw", // PPC_INS_XXBRW, "xxextractuw", // PPC_INS_XXEXTRACTUW, "xxinsertw", // PPC_INS_XXINSERTW, "xxland", // PPC_INS_XXLAND, "xxlandc", // PPC_INS_XXLANDC, "xxleqv", // PPC_INS_XXLEQV, "xxlnand", // PPC_INS_XXLNAND, "xxlnor", // PPC_INS_XXLNOR, "xxlor", // PPC_INS_XXLOR, "xxlorc", // PPC_INS_XXLORC, "xxlxor", // PPC_INS_XXLXOR, "xxmrghd", // PPC_INS_XXMRGHD, "xxmrghw", // PPC_INS_XXMRGHW, "xxmrgld", // PPC_INS_XXMRGLD, "xxmrglw", // PPC_INS_XXMRGLW, "xxperm", // PPC_INS_XXPERM, "xxpermdi", // PPC_INS_XXPERMDI, "xxpermr", // PPC_INS_XXPERMR, "xxsel", // PPC_INS_XXSEL, "xxsldwi", // PPC_INS_XXSLDWI, "xxspltd", // PPC_INS_XXSPLTD, "xxspltib", // PPC_INS_XXSPLTIB, "xxspltw", // PPC_INS_XXSPLTW, "xxswapd", // PPC_INS_XXSWAPD, capstone-sys-0.15.0/capstone/arch/PowerPC/PPCModule.c000064400000000000000000000016640072674642500204020ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_POWERPC #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "PPCDisassembler.h" #include "PPCInstPrinter.h" #include "PPCMapping.h" #include "PPCModule.h" cs_err PPC_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri)); PPC_init(mri); ud->printer = PPC_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = PPC_getInstruction; ud->post_printer = PPC_post_printer; ud->reg_name = PPC_reg_name; ud->insn_id = PPC_get_insn_id; ud->insn_name = PPC_insn_name; ud->group_name = PPC_group_name; return CS_ERR_OK; } cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_SYNTAX) handle->syntax = (int) value; if (type == CS_OPT_MODE) { handle->mode = (cs_mode)value; } return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCModule.h000064400000000000000000000004410072674642500203770ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_POWERPC_MODULE_H #define CS_POWERPC_MODULE_H #include "../../utils.h" cs_err PPC_global_init(cs_struct *ud); cs_err PPC_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/PowerPC/PPCPredicates.h000064400000000000000000000042030072674642500212350ustar 00000000000000//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file describes the PowerPC branch predicates. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_POWERPC_PPCPREDICATES_H #define CS_POWERPC_PPCPREDICATES_H #include "capstone/ppc.h" // NOTE: duplicate of ppc_bc in ppc.h to maitain code compatibility with LLVM typedef enum ppc_predicate { PPC_PRED_LT = (0 << 5) | 12, PPC_PRED_LE = (1 << 5) | 4, PPC_PRED_EQ = (2 << 5) | 12, PPC_PRED_GE = (0 << 5) | 4, PPC_PRED_GT = (1 << 5) | 12, PPC_PRED_NE = (2 << 5) | 4, PPC_PRED_UN = (3 << 5) | 12, PPC_PRED_NU = (3 << 5) | 4, PPC_PRED_LT_MINUS = (0 << 5) | 14, PPC_PRED_LE_MINUS = (1 << 5) | 6, PPC_PRED_EQ_MINUS = (2 << 5) | 14, PPC_PRED_GE_MINUS = (0 << 5) | 6, PPC_PRED_GT_MINUS = (1 << 5) | 14, PPC_PRED_NE_MINUS = (2 << 5) | 6, PPC_PRED_UN_MINUS = (3 << 5) | 14, PPC_PRED_NU_MINUS = (3 << 5) | 6, PPC_PRED_LT_PLUS = (0 << 5) | 15, PPC_PRED_LE_PLUS = (1 << 5) | 7, PPC_PRED_EQ_PLUS = (2 << 5) | 15, PPC_PRED_GE_PLUS = (0 << 5) | 7, PPC_PRED_GT_PLUS = (1 << 5) | 15, PPC_PRED_NE_PLUS = (2 << 5) | 7, PPC_PRED_UN_PLUS = (3 << 5) | 15, PPC_PRED_NU_PLUS = (3 << 5) | 7, // When dealing with individual condition-register bits, we have simple set // and unset predicates. PPC_PRED_BIT_SET = 1024, PPC_PRED_BIT_UNSET = 1025 } ppc_predicate; /// Invert the specified predicate. != -> ==, < -> >=. ppc_predicate InvertPredicate(ppc_predicate Opcode); /// Assume the condition register is set by MI(a,b), return the predicate if /// we modify the instructions such that condition register is set by MI(b,a). ppc_predicate getSwappedPredicate(ppc_predicate Opcode); #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVBaseInfo.h000064400000000000000000000053300072674642500204550ustar 00000000000000//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains small standalone enum definitions for the RISCV target // useful for the compiler back-end and the MC libraries. // //===----------------------------------------------------------------------===// #ifndef CS_RISCVBASEINFO_H #define CS_RISCVBASEINFO_H #include "../../cs_priv.h" //#include "RISCVMCTargetDesc.h" // RISCVII - This namespace holds all of the target specific flags that // instruction info tracks. All definitions must match RISCVInstrFormats.td. enum { IRISCVII_InstFormatPseudo = 0, IRISCVII_InstFormatR = 1, IRISCVII_InstFormatR4 = 2, IRISCVII_InstFormatI = 3, IRISCVII_InstFormatS = 4, IRISCVII_InstFormatB = 5, IRISCVII_InstFormatU = 6, IRISCVII_InstFormatJ = 7, IRISCVII_InstFormatCR = 8, IRISCVII_InstFormatCI = 9, IRISCVII_InstFormatCSS = 10, IRISCVII_InstFormatCIW = 11, IRISCVII_InstFormatCL = 12, IRISCVII_InstFormatCS = 13, IRISCVII_InstFormatCA = 14, IRISCVII_InstFormatCB = 15, IRISCVII_InstFormatCJ = 16, IRISCVII_InstFormatOther = 17, IRISCVII_InstFormatMask = 31 }; enum { RISCVII_MO_None, RISCVII_MO_LO, RISCVII_MO_HI, RISCVII_MO_PCREL_HI, }; // Describes the predecessor/successor bits used in the FENCE instruction. enum FenceField { RISCVFenceField_I = 8, RISCVFenceField_O = 4, RISCVFenceField_R = 2, RISCVFenceField_W = 1 }; // Describes the supported floating point rounding mode encodings. enum RoundingMode { RISCVFPRndMode_RNE = 0, RISCVFPRndMode_RTZ = 1, RISCVFPRndMode_RDN = 2, RISCVFPRndMode_RUP = 3, RISCVFPRndMode_RMM = 4, RISCVFPRndMode_DYN = 7, RISCVFPRndMode_Invalid }; inline static const char *roundingModeToString(enum RoundingMode RndMode) { switch (RndMode) { default: CS_ASSERT(0 && "Unknown floating point rounding mode"); case RISCVFPRndMode_RNE: return "rne"; case RISCVFPRndMode_RTZ: return "rtz"; case RISCVFPRndMode_RDN: return "rdn"; case RISCVFPRndMode_RUP: return "rup"; case RISCVFPRndMode_RMM: return "rmm"; case RISCVFPRndMode_DYN: return "dyn"; } } inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) { switch (Mode) { default: return false; case RISCVFPRndMode_RNE: case RISCVFPRndMode_RTZ: case RISCVFPRndMode_RDN: case RISCVFPRndMode_RUP: case RISCVFPRndMode_RMM: case RISCVFPRndMode_DYN: return true; } } #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVDisassembler.c000064400000000000000000000340320072674642500214000ustar 00000000000000//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ #ifdef CAPSTONE_HAS_RISCV #include // DEBUG #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" #include "RISCVBaseInfo.h" #include "RISCVDisassembler.h" /* Need the feature infos define in RISCVGenSubtargetInfo.inc. */ #define GET_SUBTARGETINFO_ENUM #include "RISCVGenSubtargetInfo.inc" /* When we specify the RISCV64 mode, It means It is RV64IMAFD. Similar, RISCV32 means RV32IMAFD. */ static uint64_t getFeatureBits(int mode) { uint64_t ret = RISCV_FeatureStdExtM | RISCV_FeatureStdExtA | RISCV_FeatureStdExtF | RISCV_FeatureStdExtD ; if (mode & CS_MODE_RISCV64) ret |= RISCV_Feature64Bit; if (mode & CS_MODE_RISCVC) ret |= RISCV_FeatureStdExtC; return ret; } #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "RISCVGenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "RISCVGenInstrInfo.inc" static const unsigned GPRDecoderTable[] = { RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X8, RISCV_X9, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31 }; static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = 0; if (RegNo > sizeof(GPRDecoderTable)) return MCDisassembler_Fail; // We must define our own mapping from RegNo to register identifier. // Accessing index RegNo in the register class will work in the case that // registers were added in ascending order, but not in general. Reg = GPRDecoderTable[RegNo]; //Inst.addOperand(MCOperand::createReg(Reg)); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static const unsigned FPR32DecoderTable[] = { RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F8_32, RISCV_F9_32, RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, RISCV_F17_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32 }; static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = 0; if (RegNo > sizeof(FPR32DecoderTable)) return MCDisassembler_Fail; // We must define our own mapping from RegNo to register identifier. // Accessing index RegNo in the register class will work in the case that // registers were added in ascending order, but not in general. Reg = FPR32DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = 0; if (RegNo > 8) return MCDisassembler_Fail; Reg = FPR32DecoderTable[RegNo + 8]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static const unsigned FPR64DecoderTable[] = { RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F8_64, RISCV_F9_64, RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, RISCV_F17_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64 }; static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = 0; if (RegNo > sizeof(FPR64DecoderTable)) return MCDisassembler_Fail; // We must define our own mapping from RegNo to register identifier. // Accessing index RegNo in the register class will work in the case that // registers were added in ascending order, but not in general. Reg = FPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = 0; if (RegNo > 8) return MCDisassembler_Fail; Reg = FPR64DecoderTable[RegNo + 8]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo == 0) return MCDisassembler_Fail; return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo == 2) return MCDisassembler_Fail; return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { unsigned Reg = 0; if (RegNo > 8) return MCDisassembler_Fail; Reg = GPRDecoderTable[RegNo + 8]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } // Add implied SP operand for instructions *SP compressed instructions. The SP // operand isn't explicitly encoded in the instruction. static void addImplySP(MCInst *Inst, int64_t Address, const void *Decoder) { if (MCInst_getOpcode(Inst) == RISCV_C_LWSP || MCInst_getOpcode(Inst) == RISCV_C_SWSP || MCInst_getOpcode(Inst) == RISCV_C_LDSP || MCInst_getOpcode(Inst) == RISCV_C_SDSP || MCInst_getOpcode(Inst) == RISCV_C_FLWSP || MCInst_getOpcode(Inst) == RISCV_C_FSWSP || MCInst_getOpcode(Inst) == RISCV_C_FLDSP || MCInst_getOpcode(Inst) == RISCV_C_FSDSP || MCInst_getOpcode(Inst) == RISCV_C_ADDI4SPN) { DecodeGPRRegisterClass(Inst, 2, Address, Decoder); } if (MCInst_getOpcode(Inst) == RISCV_C_ADDI16SP) { DecodeGPRRegisterClass(Inst, 2, Address, Decoder); DecodeGPRRegisterClass(Inst, 2, Address, Decoder); } } static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); addImplySP(Inst, Address, Decoder); //Inst.addOperand(MCOperand::createImm(Imm)); MCOperand_CreateImm0(Inst, Imm); return MCDisassembler_Success; } static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { if (Imm == 0) return MCDisassembler_Fail; return decodeUImmOperand(Inst, Imm, Address, Decoder, N); } static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); addImplySP(Inst, Address, Decoder); // Sign-extend the number in the bottom N bits of Imm //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); return MCDisassembler_Success; } static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { if (Imm == 0) return MCDisassembler_Fail; return decodeSImmOperand(Inst, Imm, Address, Decoder, N); } static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); // Sign-extend the number in the bottom N bits of Imm after accounting for // the fact that the N bit immediate is stored in N-1 bits (the LSB is // always zero) //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << 1))); MCOperand_CreateImm0(Inst, SignExtend64(Imm << 1, N)); return MCDisassembler_Success; } static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { //CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate"); if (Imm > 31) { Imm = (SignExtend64(Imm, 6) & 0xfffff); } //Inst.addOperand(MCOperand::createImm(Imm)); MCOperand_CreateImm0(Inst, Imm); return MCDisassembler_Success; } static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { //CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate"); if (!RISCVFPRndMode_isValidRoundingMode(Imm)) return MCDisassembler_Fail; //Inst.addOperand(MCOperand::createImm(Imm)); MCOperand_CreateImm0(Inst, Imm); return MCDisassembler_Success; } #include "RISCVGenDisassemblerTables.inc" static void init_MI_insn_detail(MCInst *MI) { if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, sizeof(cs_detail)); } return; } // mark the load/store instructions through the opcode. static void markLSInsn(MCInst *MI, uint32_t in) { /* I ld 0000011 = 0x03 st 0100011 = 0x23 F/D ld 0000111 = 0x07 st 0100111 = 0x27 */ #define MASK_LS_INSN 0x0000007f uint32_t opcode = in & MASK_LS_INSN; if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) || 0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27)) MI->flat_insn->detail->riscv.need_effective_addr = true; #undef MASK_LS_INSN return; } static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI, const uint8_t *code, size_t code_len, uint16_t *Size, uint64_t Address, MCRegisterInfo *MRI) { // TODO: This will need modification when supporting instruction set // extensions with instructions > 32-bits (up to 176 bits wide). uint32_t Inst = 0; DecodeStatus Result; // It's a 32 bit instruction if bit 0 and 1 are 1. if ((code[0] & 0x3) == 0x3) { if (code_len < 4) { *Size = 0; return MCDisassembler_Fail; } *Size = 4; // Get the four bytes of the instruction. //Encoded as little endian 32 bits. Inst = code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24); init_MI_insn_detail(MI); // Now we need mark what instruction need fix effective address output. if (MI->csh->detail) markLSInsn(MI, Inst); Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode); } else { if (code_len < 2) { *Size = 0; return MCDisassembler_Fail; } // If not b4bit. if (! (getFeatureBits(mode) & ((uint64_t)RISCV_Feature64Bit))) { // Trying RISCV32Only_16 table (16-bit Instruction) Inst = code[0] | (code[1] << 8); init_MI_insn_detail(MI); Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Inst, Address, MRI, mode); if (Result != MCDisassembler_Fail) { *Size = 2; return Result; } } // Trying RISCV_C table (16-bit Instruction) Inst = code[0] | (code[1] << 8); init_MI_insn_detail(MI); // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode); *Size = 2; } return Result; } bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info) { cs_struct *handle = (cs_struct *)(uintptr_t)ud; return MCDisassembler_Success == RISCVDisassembler_getInstruction(handle->mode, instr, code, code_len, size, address, (MCRegisterInfo *)info); } void RISCV_init(MCRegisterInfo * MRI) { /* InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, RISCVMCRegisterClasses, 11, RISCVRegUnitRoots, 64, RISCVRegDiffLists, RISCVLaneMaskLists, RISCVRegStrings, RISCVRegClassStrings, RISCVSubRegIdxLists, 2, RISCVSubRegIdxRanges, RISCVRegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, 97, 0, 0, RISCVMCRegisterClasses, 11, 0, 0, RISCVRegDiffLists, 0, RISCVSubRegIdxLists, 2, 0); } #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVDisassembler.h000064400000000000000000000010300072674642500213750ustar 00000000000000/* Capstone Disassembly Engine */ /* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ #ifndef CS_RISCVDISASSEMBLER_H #define CS_RISCVDISASSEMBLER_H #include "../../include/capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void RISCV_init(MCRegisterInfo *MRI); bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVGenAsmWriter.inc000064400000000000000000003115550072674642500216710ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include // debug #include #include /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'l', 'l', 'a', 9, 0, /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, /* 17 */ 's', 'r', 'a', 9, 0, /* 22 */ 'l', 'b', 9, 0, /* 26 */ 's', 'b', 9, 0, /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0, /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0, /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0, /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, /* 78 */ 's', 'c', '.', 'd', 9, 0, /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0, /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0, /* 211 */ 'l', 'r', '.', 'd', 9, 0, /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0, /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0, /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0, /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0, /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0, /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0, /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0, /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0, /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0, /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0, /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0, /* 378 */ 'c', '.', 'l', 'd', 9, 0, /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0, /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0, /* 398 */ 'c', '.', 's', 'd', 9, 0, /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0, /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0, /* 418 */ 'b', 'g', 'e', 9, 0, /* 423 */ 'b', 'n', 'e', 9, 0, /* 428 */ 'm', 'u', 'l', 'h', 9, 0, /* 434 */ 's', 'h', 9, 0, /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, /* 479 */ 'w', 'f', 'i', 9, 0, /* 484 */ 'c', '.', 'l', 'i', 9, 0, /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, /* 506 */ 'x', 'o', 'r', 'i', 9, 0, /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, /* 520 */ 's', 'l', 't', 'i', 9, 0, /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0, /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, /* 541 */ 'c', '.', 'j', 9, 0, /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0, /* 583 */ 't', 'a', 'i', 'l', 9, 0, /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0, /* 596 */ 's', 'l', 'l', 9, 0, /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0, /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0, /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0, /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0, /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0, /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0, /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0, /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0, /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0, /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0, /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0, /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0, /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, /* 1193 */ 's', 'r', 'l', 9, 0, /* 1198 */ 'm', 'u', 'l', 9, 0, /* 1203 */ 'r', 'e', 'm', 9, 0, /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0, /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0, /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0, /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0, /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0, /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0, /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0, /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0, /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0, /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0, /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0, /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0, /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0, /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0, /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0, /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0, /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0, /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0, /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0, /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0, /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0, /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0, /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0, /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0, /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0, /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0, /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0, /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0, /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0, /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0, /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0, /* 1601 */ 'b', 'e', 'q', 9, 0, /* 1606 */ 'c', '.', 'j', 'r', 9, 0, /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0, /* 1620 */ 'c', '.', 'o', 'r', 9, 0, /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0, /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0, /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0, /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0, /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0, /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0, /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0, /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0, /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0, /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0, /* 1847 */ 'm', 'r', 'e', 't', 9, 0, /* 1853 */ 's', 'r', 'e', 't', 9, 0, /* 1859 */ 'u', 'r', 'e', 't', 9, 0, /* 1865 */ 'b', 'l', 't', 9, 0, /* 1870 */ 's', 'l', 't', 9, 0, /* 1875 */ 'l', 'b', 'u', 9, 0, /* 1880 */ 'b', 'g', 'e', 'u', 9, 0, /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0, /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0, /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, /* 1922 */ 'r', 'e', 'm', 'u', 9, 0, /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, /* 1936 */ 'b', 'l', 't', 'u', 9, 0, /* 1942 */ 's', 'l', 't', 'u', 9, 0, /* 1948 */ 'd', 'i', 'v', 'u', 9, 0, /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, /* 1976 */ 'l', 'w', 'u', 9, 0, /* 1981 */ 'd', 'i', 'v', 9, 0, /* 1986 */ 'c', '.', 'm', 'v', 9, 0, /* 1992 */ 's', 'c', '.', 'w', 9, 0, /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, /* 2049 */ 'l', 'r', '.', 'w', 9, 0, /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, /* 2125 */ 's', 'r', 'a', 'w', 9, 0, /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0, /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0, /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0, /* 2177 */ 'c', '.', 'l', 'w', 9, 0, /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0, /* 2190 */ 's', 'l', 'l', 'w', 9, 0, /* 2196 */ 's', 'r', 'l', 'w', 9, 0, /* 2202 */ 'm', 'u', 'l', 'w', 9, 0, /* 2208 */ 'r', 'e', 'm', 'w', 9, 0, /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0, /* 2221 */ 'c', '.', 's', 'w', 9, 0, /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0, /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0, /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0, /* 2248 */ 'd', 'i', 'v', 'w', 9, 0, /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, }; #endif static const uint16_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 2457U, // DBG_VALUE 2467U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 2450U, // BUNDLE 2477U, // LIFETIME_START 2437U, // LIFETIME_END 0U, // STACKMAP 2492U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 2369U, // PATCHABLE_FUNCTION_ENTER 2289U, // PATCHABLE_RET 2415U, // PATCHABLE_FUNCTION_EXIT 2392U, // PATCHABLE_TAIL_CALL 2344U, // PATCHABLE_EVENT_CALL 2320U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_BUILD_VECTOR 0U, // G_BUILD_VECTOR_TRUNC 0U, // G_CONCAT_VECTORS 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_INTRINSIC_TRUNC 0U, // G_INTRINSIC_ROUND 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDO 0U, // G_UADDE 0U, // G_USUBO 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SADDE 0U, // G_SSUBO 0U, // G_SSUBE 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FLOG10 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_FCANONICALIZE 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_CTTZ 0U, // G_CTTZ_ZERO_UNDEF 0U, // G_CTLZ 0U, // G_CTLZ_ZERO_UNDEF 0U, // G_CTPOP 0U, // G_BSWAP 0U, // G_FCEIL 0U, // G_FCOS 0U, // G_FSIN 0U, // G_FSQRT 0U, // G_FFLOOR 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 4U, // ADJCALLSTACKDOWN 4U, // ADJCALLSTACKUP 4U, // BuildPairF64Pseudo 4U, // PseudoAtomicLoadNand32 4U, // PseudoAtomicLoadNand64 4U, // PseudoBR 4U, // PseudoBRIND 4687U, // PseudoCALL 4U, // PseudoCALLIndirect 4U, // PseudoCmpXchg32 4U, // PseudoCmpXchg64 20482U, // PseudoLA 20967U, // PseudoLI 20481U, // PseudoLLA 4U, // PseudoMaskedAtomicLoadAdd32 4U, // PseudoMaskedAtomicLoadMax32 4U, // PseudoMaskedAtomicLoadMin32 4U, // PseudoMaskedAtomicLoadNand32 4U, // PseudoMaskedAtomicLoadSub32 4U, // PseudoMaskedAtomicLoadUMax32 4U, // PseudoMaskedAtomicLoadUMin32 4U, // PseudoMaskedAtomicSwap32 4U, // PseudoMaskedCmpXchg32 4U, // PseudoRET 4680U, // PseudoTAIL 4U, // PseudoTAILIndirect 4U, // Select_FPR32_Using_CC_GPR 4U, // Select_FPR64_Using_CC_GPR 4U, // Select_GPR_Using_CC_GPR 4U, // SplitF64Pseudo 20854U, // ADD 20946U, // ADDI 22637U, // ADDIW 22622U, // ADDW 20592U, // AMOADD_D 21817U, // AMOADD_D_AQ 21367U, // AMOADD_D_AQ_RL 21091U, // AMOADD_D_RL 22489U, // AMOADD_W 21954U, // AMOADD_W_AQ 21526U, // AMOADD_W_AQ_RL 21228U, // AMOADD_W_RL 20602U, // AMOAND_D 21830U, // AMOAND_D_AQ 21382U, // AMOAND_D_AQ_RL 21104U, // AMOAND_D_RL 22499U, // AMOAND_W 21967U, // AMOAND_W_AQ 21541U, // AMOAND_W_AQ_RL 21241U, // AMOAND_W_RL 20786U, // AMOMAXU_D 21918U, // AMOMAXU_D_AQ 21484U, // AMOMAXU_D_AQ_RL 21192U, // AMOMAXU_D_RL 22576U, // AMOMAXU_W 22055U, // AMOMAXU_W_AQ 21643U, // AMOMAXU_W_AQ_RL 21329U, // AMOMAXU_W_RL 20832U, // AMOMAX_D 21932U, // AMOMAX_D_AQ 21500U, // AMOMAX_D_AQ_RL 21206U, // AMOMAX_D_RL 22596U, // AMOMAX_W 22069U, // AMOMAX_W_AQ 21659U, // AMOMAX_W_AQ_RL 21343U, // AMOMAX_W_RL 20764U, // AMOMINU_D 21904U, // AMOMINU_D_AQ 21468U, // AMOMINU_D_AQ_RL 21178U, // AMOMINU_D_RL 22565U, // AMOMINU_W 22041U, // AMOMINU_W_AQ 21627U, // AMOMINU_W_AQ_RL 21315U, // AMOMINU_W_RL 20654U, // AMOMIN_D 21843U, // AMOMIN_D_AQ 21397U, // AMOMIN_D_AQ_RL 21117U, // AMOMIN_D_RL 22509U, // AMOMIN_W 21980U, // AMOMIN_W_AQ 21556U, // AMOMIN_W_AQ_RL 21254U, // AMOMIN_W_RL 20698U, // AMOOR_D 21879U, // AMOOR_D_AQ 21439U, // AMOOR_D_AQ_RL 21153U, // AMOOR_D_RL 22536U, // AMOOR_W 22016U, // AMOOR_W_AQ 21598U, // AMOOR_W_AQ_RL 21290U, // AMOOR_W_RL 20674U, // AMOSWAP_D 21856U, // AMOSWAP_D_AQ 21412U, // AMOSWAP_D_AQ_RL 21130U, // AMOSWAP_D_RL 22519U, // AMOSWAP_W 21993U, // AMOSWAP_W_AQ 21571U, // AMOSWAP_W_AQ_RL 21267U, // AMOSWAP_W_RL 20707U, // AMOXOR_D 21891U, // AMOXOR_D_AQ 21453U, // AMOXOR_D_AQ_RL 21165U, // AMOXOR_D_RL 22545U, // AMOXOR_W 22028U, // AMOXOR_W_AQ 21612U, // AMOXOR_W_AQ_RL 21302U, // AMOXOR_W_RL 20874U, // AND 20954U, // ANDI 20518U, // AUIPC 22082U, // BEQ 20899U, // BGE 22361U, // BGEU 22346U, // BLT 22417U, // BLTU 20904U, // BNE 20525U, // CSRRC 20936U, // CSRRCI 22321U, // CSRRS 20993U, // CSRRSI 22695U, // CSRRW 21014U, // CSRRWI 8564U, // C_ADD 8656U, // C_ADDI 9440U, // C_ADDI16SP 21689U, // C_ADDI4SPN 10347U, // C_ADDIW 10332U, // C_ADDW 8584U, // C_AND 8664U, // C_ANDI 22761U, // C_BEQZ 22753U, // C_BNEZ 547U, // C_EBREAK 20865U, // C_FLD 21748U, // C_FLDSP 22664U, // C_FLW 21782U, // C_FLWSP 20885U, // C_FSD 21765U, // C_FSDSP 22708U, // C_FSW 21799U, // C_FSWSP 4638U, // C_J 4673U, // C_JAL 5709U, // C_JALR 5703U, // C_JR 20859U, // C_LD 21740U, // C_LDSP 20965U, // C_LI 21007U, // C_LUI 22658U, // C_LW 21774U, // C_LWSP 22467U, // C_MV 1241U, // C_NOP 9813U, // C_OR 20879U, // C_SD 21757U, // C_SDSP 8683U, // C_SLLI 8640U, // C_SRAI 8691U, // C_SRLI 8223U, // C_SUB 10324U, // C_SUBW 22702U, // C_SW 21791U, // C_SWSP 1232U, // C_UNIMP 9819U, // C_XOR 22462U, // DIV 22429U, // DIVU 22722U, // DIVUW 22729U, // DIVW 549U, // EBREAK 590U, // ECALL 20565U, // FADD_D 22151U, // FADD_S 20727U, // FCLASS_D 22237U, // FCLASS_S 21037U, // FCVT_D_L 22381U, // FCVT_D_LU 22141U, // FCVT_D_S 22479U, // FCVT_D_W 22435U, // FCVT_D_WU 20753U, // FCVT_LU_D 22263U, // FCVT_LU_S 20628U, // FCVT_L_D 22194U, // FCVT_L_S 20717U, // FCVT_S_D 21047U, // FCVT_S_L 22392U, // FCVT_S_LU 22555U, // FCVT_S_W 22446U, // FCVT_S_WU 20775U, // FCVT_WU_D 22274U, // FCVT_WU_S 20805U, // FCVT_W_D 22293U, // FCVT_W_S 20797U, // FDIV_D 22285U, // FDIV_S 12700U, // FENCE 439U, // FENCE_I 1221U, // FENCE_TSO 20685U, // FEQ_D 22230U, // FEQ_S 20867U, // FLD 20612U, // FLE_D 22178U, // FLE_S 20737U, // FLT_D 22247U, // FLT_S 22666U, // FLW 20573U, // FMADD_D 22159U, // FMADD_S 20824U, // FMAX_D 22303U, // FMAX_S 20646U, // FMIN_D 22212U, // FMIN_S 20540U, // FMSUB_D 22122U, // FMSUB_S 20638U, // FMUL_D 22204U, // FMUL_S 22735U, // FMV_D_X 22744U, // FMV_W_X 20815U, // FMV_X_D 22587U, // FMV_X_W 20582U, // FNMADD_D 22168U, // FNMADD_S 20549U, // FNMSUB_D 22131U, // FNMSUB_S 20887U, // FSD 20664U, // FSGNJN_D 22220U, // FSGNJN_S 20842U, // FSGNJX_D 22311U, // FSGNJX_S 20619U, // FSGNJ_D 22185U, // FSGNJ_S 20744U, // FSQRT_D 22254U, // FSQRT_S 20532U, // FSUB_D 22114U, // FSUB_S 22710U, // FSW 21059U, // JAL 22095U, // JALR 20503U, // LB 22356U, // LBU 20861U, // LD 20911U, // LH 22369U, // LHU 37076U, // LR_D 38254U, // LR_D_AQ 37812U, // LR_D_AQ_RL 37528U, // LR_D_RL 38914U, // LR_W 38391U, // LR_W_AQ 37971U, // LR_W_AQ_RL 37665U, // LR_W_RL 21009U, // LUI 22660U, // LW 22457U, // LWU 1848U, // MRET 21679U, // MUL 20909U, // MULH 22409U, // MULHSU 22367U, // MULHU 22683U, // MULW 22103U, // OR 20988U, // ORI 21684U, // REM 22403U, // REMU 22715U, // REMUW 22689U, // REMW 20507U, // SB 20559U, // SC_D 21808U, // SC_D_AQ 21356U, // SC_D_AQ_RL 21082U, // SC_D_RL 22473U, // SC_W 21945U, // SC_W_AQ 21515U, // SC_W_AQ_RL 21219U, // SC_W_RL 20881U, // SD 20486U, // SFENCE_VMA 20915U, // SH 21077U, // SLL 20973U, // SLLI 22644U, // SLLIW 22671U, // SLLW 22351U, // SLT 21001U, // SLTI 22374U, // SLTIU 22423U, // SLTU 20498U, // SRA 20930U, // SRAI 22628U, // SRAIW 22606U, // SRAW 1854U, // SRET 21674U, // SRL 20981U, // SRLI 22651U, // SRLIW 22677U, // SRLW 20513U, // SUB 22614U, // SUBW 22704U, // SW 1234U, // UNIMP 1860U, // URET 480U, // WFI 22109U, // XOR 20987U, // XORI }; static const uint8_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // INLINEASM_BR 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_BUILD_VECTOR 0U, // G_BUILD_VECTOR_TRUNC 0U, // G_CONCAT_VECTORS 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_INTRINSIC_TRUNC 0U, // G_INTRINSIC_ROUND 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDO 0U, // G_UADDE 0U, // G_USUBO 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SADDE 0U, // G_SSUBO 0U, // G_SSUBE 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FLOG10 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_FCANONICALIZE 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_CTTZ 0U, // G_CTTZ_ZERO_UNDEF 0U, // G_CTLZ 0U, // G_CTLZ_ZERO_UNDEF 0U, // G_CTPOP 0U, // G_BSWAP 0U, // G_FCEIL 0U, // G_FCOS 0U, // G_FSIN 0U, // G_FSQRT 0U, // G_FFLOOR 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // BuildPairF64Pseudo 0U, // PseudoAtomicLoadNand32 0U, // PseudoAtomicLoadNand64 0U, // PseudoBR 0U, // PseudoBRIND 0U, // PseudoCALL 0U, // PseudoCALLIndirect 0U, // PseudoCmpXchg32 0U, // PseudoCmpXchg64 0U, // PseudoLA 0U, // PseudoLI 0U, // PseudoLLA 0U, // PseudoMaskedAtomicLoadAdd32 0U, // PseudoMaskedAtomicLoadMax32 0U, // PseudoMaskedAtomicLoadMin32 0U, // PseudoMaskedAtomicLoadNand32 0U, // PseudoMaskedAtomicLoadSub32 0U, // PseudoMaskedAtomicLoadUMax32 0U, // PseudoMaskedAtomicLoadUMin32 0U, // PseudoMaskedAtomicSwap32 0U, // PseudoMaskedCmpXchg32 0U, // PseudoRET 0U, // PseudoTAIL 0U, // PseudoTAILIndirect 0U, // Select_FPR32_Using_CC_GPR 0U, // Select_FPR64_Using_CC_GPR 0U, // Select_GPR_Using_CC_GPR 0U, // SplitF64Pseudo 4U, // ADD 4U, // ADDI 4U, // ADDIW 4U, // ADDW 9U, // AMOADD_D 9U, // AMOADD_D_AQ 9U, // AMOADD_D_AQ_RL 9U, // AMOADD_D_RL 9U, // AMOADD_W 9U, // AMOADD_W_AQ 9U, // AMOADD_W_AQ_RL 9U, // AMOADD_W_RL 9U, // AMOAND_D 9U, // AMOAND_D_AQ 9U, // AMOAND_D_AQ_RL 9U, // AMOAND_D_RL 9U, // AMOAND_W 9U, // AMOAND_W_AQ 9U, // AMOAND_W_AQ_RL 9U, // AMOAND_W_RL 9U, // AMOMAXU_D 9U, // AMOMAXU_D_AQ 9U, // AMOMAXU_D_AQ_RL 9U, // AMOMAXU_D_RL 9U, // AMOMAXU_W 9U, // AMOMAXU_W_AQ 9U, // AMOMAXU_W_AQ_RL 9U, // AMOMAXU_W_RL 9U, // AMOMAX_D 9U, // AMOMAX_D_AQ 9U, // AMOMAX_D_AQ_RL 9U, // AMOMAX_D_RL 9U, // AMOMAX_W 9U, // AMOMAX_W_AQ 9U, // AMOMAX_W_AQ_RL 9U, // AMOMAX_W_RL 9U, // AMOMINU_D 9U, // AMOMINU_D_AQ 9U, // AMOMINU_D_AQ_RL 9U, // AMOMINU_D_RL 9U, // AMOMINU_W 9U, // AMOMINU_W_AQ 9U, // AMOMINU_W_AQ_RL 9U, // AMOMINU_W_RL 9U, // AMOMIN_D 9U, // AMOMIN_D_AQ 9U, // AMOMIN_D_AQ_RL 9U, // AMOMIN_D_RL 9U, // AMOMIN_W 9U, // AMOMIN_W_AQ 9U, // AMOMIN_W_AQ_RL 9U, // AMOMIN_W_RL 9U, // AMOOR_D 9U, // AMOOR_D_AQ 9U, // AMOOR_D_AQ_RL 9U, // AMOOR_D_RL 9U, // AMOOR_W 9U, // AMOOR_W_AQ 9U, // AMOOR_W_AQ_RL 9U, // AMOOR_W_RL 9U, // AMOSWAP_D 9U, // AMOSWAP_D_AQ 9U, // AMOSWAP_D_AQ_RL 9U, // AMOSWAP_D_RL 9U, // AMOSWAP_W 9U, // AMOSWAP_W_AQ 9U, // AMOSWAP_W_AQ_RL 9U, // AMOSWAP_W_RL 9U, // AMOXOR_D 9U, // AMOXOR_D_AQ 9U, // AMOXOR_D_AQ_RL 9U, // AMOXOR_D_RL 9U, // AMOXOR_W 9U, // AMOXOR_W_AQ 9U, // AMOXOR_W_AQ_RL 9U, // AMOXOR_W_RL 4U, // AND 4U, // ANDI 0U, // AUIPC 4U, // BEQ 4U, // BGE 4U, // BGEU 4U, // BLT 4U, // BLTU 4U, // BNE 2U, // CSRRC 2U, // CSRRCI 2U, // CSRRS 2U, // CSRRSI 2U, // CSRRW 2U, // CSRRWI 0U, // C_ADD 0U, // C_ADDI 0U, // C_ADDI16SP 4U, // C_ADDI4SPN 0U, // C_ADDIW 0U, // C_ADDW 0U, // C_AND 0U, // C_ANDI 0U, // C_BEQZ 0U, // C_BNEZ 0U, // C_EBREAK 13U, // C_FLD 13U, // C_FLDSP 13U, // C_FLW 13U, // C_FLWSP 13U, // C_FSD 13U, // C_FSDSP 13U, // C_FSW 13U, // C_FSWSP 0U, // C_J 0U, // C_JAL 0U, // C_JALR 0U, // C_JR 13U, // C_LD 13U, // C_LDSP 0U, // C_LI 0U, // C_LUI 13U, // C_LW 13U, // C_LWSP 0U, // C_MV 0U, // C_NOP 0U, // C_OR 13U, // C_SD 13U, // C_SDSP 0U, // C_SLLI 0U, // C_SRAI 0U, // C_SRLI 0U, // C_SUB 0U, // C_SUBW 13U, // C_SW 13U, // C_SWSP 0U, // C_UNIMP 0U, // C_XOR 4U, // DIV 4U, // DIVU 4U, // DIVUW 4U, // DIVW 0U, // EBREAK 0U, // ECALL 36U, // FADD_D 36U, // FADD_S 0U, // FCLASS_D 0U, // FCLASS_S 20U, // FCVT_D_L 20U, // FCVT_D_LU 0U, // FCVT_D_S 0U, // FCVT_D_W 0U, // FCVT_D_WU 20U, // FCVT_LU_D 20U, // FCVT_LU_S 20U, // FCVT_L_D 20U, // FCVT_L_S 20U, // FCVT_S_D 20U, // FCVT_S_L 20U, // FCVT_S_LU 20U, // FCVT_S_W 20U, // FCVT_S_WU 20U, // FCVT_WU_D 20U, // FCVT_WU_S 20U, // FCVT_W_D 20U, // FCVT_W_S 36U, // FDIV_D 36U, // FDIV_S 0U, // FENCE 0U, // FENCE_I 0U, // FENCE_TSO 4U, // FEQ_D 4U, // FEQ_S 13U, // FLD 4U, // FLE_D 4U, // FLE_S 4U, // FLT_D 4U, // FLT_S 13U, // FLW 100U, // FMADD_D 100U, // FMADD_S 4U, // FMAX_D 4U, // FMAX_S 4U, // FMIN_D 4U, // FMIN_S 100U, // FMSUB_D 100U, // FMSUB_S 36U, // FMUL_D 36U, // FMUL_S 0U, // FMV_D_X 0U, // FMV_W_X 0U, // FMV_X_D 0U, // FMV_X_W 100U, // FNMADD_D 100U, // FNMADD_S 100U, // FNMSUB_D 100U, // FNMSUB_S 13U, // FSD 4U, // FSGNJN_D 4U, // FSGNJN_S 4U, // FSGNJX_D 4U, // FSGNJX_S 4U, // FSGNJ_D 4U, // FSGNJ_S 20U, // FSQRT_D 20U, // FSQRT_S 36U, // FSUB_D 36U, // FSUB_S 13U, // FSW 0U, // JAL 4U, // JALR 13U, // LB 13U, // LBU 13U, // LD 13U, // LH 13U, // LHU 0U, // LR_D 0U, // LR_D_AQ 0U, // LR_D_AQ_RL 0U, // LR_D_RL 0U, // LR_W 0U, // LR_W_AQ 0U, // LR_W_AQ_RL 0U, // LR_W_RL 0U, // LUI 13U, // LW 13U, // LWU 0U, // MRET 4U, // MUL 4U, // MULH 4U, // MULHSU 4U, // MULHU 4U, // MULW 4U, // OR 4U, // ORI 4U, // REM 4U, // REMU 4U, // REMUW 4U, // REMW 13U, // SB 9U, // SC_D 9U, // SC_D_AQ 9U, // SC_D_AQ_RL 9U, // SC_D_RL 9U, // SC_W 9U, // SC_W_AQ 9U, // SC_W_AQ_RL 9U, // SC_W_RL 13U, // SD 0U, // SFENCE_VMA 13U, // SH 4U, // SLL 4U, // SLLI 4U, // SLLIW 4U, // SLLW 4U, // SLT 4U, // SLTI 4U, // SLTIU 4U, // SLTU 4U, // SRA 4U, // SRAI 4U, // SRAIW 4U, // SRAW 0U, // SRET 4U, // SRL 4U, // SRLI 4U, // SRLIW 4U, // SRLW 4U, // SUB 4U, // SUBW 13U, // SW 0U, // UNIMP 0U, // URET 0U, // WFI 4U, // XOR 4U, // XORI }; // Emit the opcode for the instruction. uint32_t Bits = 0; Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; CS_ASSERT(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 4095)-1); #endif // Fragment 0 encoded into 2 bits for 4 unique commands. switch ((Bits >> 12) & 3) { default: CS_ASSERT(0 && "Invalid command number."); case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI... printOperand(MI, 0, O); break; case 2: // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL... printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 3: // FENCE printFenceArg(MI, 0, O); SStream_concat0(O, ", "); printFenceArg(MI, 1, O); return; break; } // Fragment 1 encoded into 2 bits for 3 unique commands. switch ((Bits >> 14) & 3) { default: CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR return; break; case 1: // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD... SStream_concat0(O, ", "); break; case 2: // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL SStream_concat0(O, ", ("); printOperand(MI, 1, O); SStream_concat0(O, ")"); return; break; } // Fragment 2 encoded into 2 bits for 3 unique commands. switch ((Bits >> 16) & 3) { default: CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... printOperand(MI, 1, O); break; case 1: // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... printOperand(MI, 2, O); break; case 2: // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI printCSRSystemRegister(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; } // Fragment 3 encoded into 2 bits for 4 unique commands. switch ((Bits >> 18) & 3) { default: CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... return; break; case 1: // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... SStream_concat0(O, ", "); break; case 2: // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... SStream_concat0(O, ", ("); printOperand(MI, 1, O); SStream_concat0(O, ")"); return; break; case 3: // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... SStream_concat0(O, "("); printOperand(MI, 1, O); SStream_concat0(O, ")"); return; break; } // Fragment 4 encoded into 1 bits for 2 unique commands. if ((Bits >> 20) & 1) { // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... printFRMArg(MI, 2, O); return; } else { // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... printOperand(MI, 2, O); } // Fragment 5 encoded into 1 bits for 2 unique commands. if ((Bits >> 21) & 1) { // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM... SStream_concat0(O, ", "); } else { // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... return; } // Fragment 6 encoded into 1 bits for 2 unique commands. if ((Bits >> 22) & 1) { // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... printOperand(MI, 3, O); SStream_concat0(O, ", "); printFRMArg(MI, 4, O); return; } else { // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S printFRMArg(MI, 3, O); return; } } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char * getRegisterName(unsigned RegNo, unsigned AltIdx) { CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrsABIRegAltName[] = { /* 0 */ 'f', 's', '1', '0', 0, /* 5 */ 'f', 't', '1', '0', 0, /* 10 */ 'f', 'a', '0', 0, /* 14 */ 'f', 's', '0', 0, /* 18 */ 'f', 't', '0', 0, /* 22 */ 'f', 's', '1', '1', 0, /* 27 */ 'f', 't', '1', '1', 0, /* 32 */ 'f', 'a', '1', 0, /* 36 */ 'f', 's', '1', 0, /* 40 */ 'f', 't', '1', 0, /* 44 */ 'f', 'a', '2', 0, /* 48 */ 'f', 's', '2', 0, /* 52 */ 'f', 't', '2', 0, /* 56 */ 'f', 'a', '3', 0, /* 60 */ 'f', 's', '3', 0, /* 64 */ 'f', 't', '3', 0, /* 68 */ 'f', 'a', '4', 0, /* 72 */ 'f', 's', '4', 0, /* 76 */ 'f', 't', '4', 0, /* 80 */ 'f', 'a', '5', 0, /* 84 */ 'f', 's', '5', 0, /* 88 */ 'f', 't', '5', 0, /* 92 */ 'f', 'a', '6', 0, /* 96 */ 'f', 's', '6', 0, /* 100 */ 'f', 't', '6', 0, /* 104 */ 'f', 'a', '7', 0, /* 108 */ 'f', 's', '7', 0, /* 112 */ 'f', 't', '7', 0, /* 116 */ 'f', 's', '8', 0, /* 120 */ 'f', 't', '8', 0, /* 124 */ 'f', 's', '9', 0, /* 128 */ 'f', 't', '9', 0, /* 132 */ 'r', 'a', 0, /* 135 */ 'z', 'e', 'r', 'o', 0, /* 140 */ 'g', 'p', 0, /* 143 */ 's', 'p', 0, /* 146 */ 't', 'p', 0, }; static const uint8_t RegAsmOffsetABIRegAltName[] = { 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, }; static const char AsmStrsNoRegAltName[] = { /* 0 */ 'f', '1', '0', 0, /* 4 */ 'x', '1', '0', 0, /* 8 */ 'f', '2', '0', 0, /* 12 */ 'x', '2', '0', 0, /* 16 */ 'f', '3', '0', 0, /* 20 */ 'x', '3', '0', 0, /* 24 */ 'f', '0', 0, /* 27 */ 'x', '0', 0, /* 30 */ 'f', '1', '1', 0, /* 34 */ 'x', '1', '1', 0, /* 38 */ 'f', '2', '1', 0, /* 42 */ 'x', '2', '1', 0, /* 46 */ 'f', '3', '1', 0, /* 50 */ 'x', '3', '1', 0, /* 54 */ 'f', '1', 0, /* 57 */ 'x', '1', 0, /* 60 */ 'f', '1', '2', 0, /* 64 */ 'x', '1', '2', 0, /* 68 */ 'f', '2', '2', 0, /* 72 */ 'x', '2', '2', 0, /* 76 */ 'f', '2', 0, /* 79 */ 'x', '2', 0, /* 82 */ 'f', '1', '3', 0, /* 86 */ 'x', '1', '3', 0, /* 90 */ 'f', '2', '3', 0, /* 94 */ 'x', '2', '3', 0, /* 98 */ 'f', '3', 0, /* 101 */ 'x', '3', 0, /* 104 */ 'f', '1', '4', 0, /* 108 */ 'x', '1', '4', 0, /* 112 */ 'f', '2', '4', 0, /* 116 */ 'x', '2', '4', 0, /* 120 */ 'f', '4', 0, /* 123 */ 'x', '4', 0, /* 126 */ 'f', '1', '5', 0, /* 130 */ 'x', '1', '5', 0, /* 134 */ 'f', '2', '5', 0, /* 138 */ 'x', '2', '5', 0, /* 142 */ 'f', '5', 0, /* 145 */ 'x', '5', 0, /* 148 */ 'f', '1', '6', 0, /* 152 */ 'x', '1', '6', 0, /* 156 */ 'f', '2', '6', 0, /* 160 */ 'x', '2', '6', 0, /* 164 */ 'f', '6', 0, /* 167 */ 'x', '6', 0, /* 170 */ 'f', '1', '7', 0, /* 174 */ 'x', '1', '7', 0, /* 178 */ 'f', '2', '7', 0, /* 182 */ 'x', '2', '7', 0, /* 186 */ 'f', '7', 0, /* 189 */ 'x', '7', 0, /* 192 */ 'f', '1', '8', 0, /* 196 */ 'x', '1', '8', 0, /* 200 */ 'f', '2', '8', 0, /* 204 */ 'x', '2', '8', 0, /* 208 */ 'f', '8', 0, /* 211 */ 'x', '8', 0, /* 214 */ 'f', '1', '9', 0, /* 218 */ 'x', '1', '9', 0, /* 222 */ 'f', '2', '9', 0, /* 226 */ 'x', '2', '9', 0, /* 230 */ 'f', '9', 0, /* 233 */ 'x', '9', 0, }; static const uint8_t RegAsmOffsetNoRegAltName[] = { 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, }; switch(AltIdx) { default: CS_ASSERT(0 && "Invalid register alt name index!"); case RISCV_ABIRegAltName: CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && "Invalid alt name index for register!"); return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; case RISCV_NoRegAltName: CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && "Invalid alt name index for register!"); return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; } #else return NULL; #endif } #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, unsigned PredicateIndex); static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) { MCRegisterInfo *MRI = (MCRegisterInfo *) info; const char *AsmString; unsigned I = 0; #define ASMSTRING_CONTAIN_SIZE 64 unsigned AsmStringLen = 0; char tmpString_[ASMSTRING_CONTAIN_SIZE]; char *tmpString = tmpString_; switch (MCInst_getOpcode(MI)) { default: return false; case RISCV_ADDI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (ADDI X0, X0, 0) AsmString = "nop"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (ADDI GPR:$rd, GPR:$rs, 0) AsmString = "mv $\x01, $\x02"; break; } return false; case RISCV_ADDIW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (ADDIW GPR:$rd, GPR:$rs, 0) AsmString = "sext.w $\x01, $\x02"; break; } return false; case RISCV_BEQ: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) AsmString = "beqz $\x01, $\x03"; break; } return false; case RISCV_BGE: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BGE X0, GPR:$rs, simm13_lsb0:$offset) AsmString = "blez $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BGE GPR:$rs, X0, simm13_lsb0:$offset) AsmString = "bgez $\x01, $\x03"; break; } return false; case RISCV_BLT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BLT GPR:$rs, X0, simm13_lsb0:$offset) AsmString = "bltz $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BLT X0, GPR:$rs, simm13_lsb0:$offset) AsmString = "bgtz $\x02, $\x03"; break; } return false; case RISCV_BNE: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { // (BNE GPR:$rs, X0, simm13_lsb0:$offset) AsmString = "bnez $\x01, $\x03"; break; } return false; case RISCV_CSRRC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) AsmString = "csrc $\xFF\x02\x01, $\x03"; break; } return false; case RISCV_CSRRCI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) AsmString = "csrci $\xFF\x02\x01, $\x03"; break; } return false; case RISCV_CSRRS: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3, X0) AsmString = "frcsr $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 2, X0) AsmString = "frrm $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 1, X0) AsmString = "frflags $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3074, X0) AsmString = "rdinstret $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3072, X0) AsmString = "rdcycle $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3073, X0) AsmString = "rdtime $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3202, X0) AsmString = "rdinstreth $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3200, X0) AsmString = "rdcycleh $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, 3201, X0) AsmString = "rdtimeh $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) AsmString = "csrr $\x01, $\xFF\x02\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) AsmString = "csrs $\xFF\x02\x01, $\x03"; break; } return false; case RISCV_CSRRSI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) AsmString = "csrsi $\xFF\x02\x01, $\x03"; break; } return false; case RISCV_CSRRW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, 3, GPR:$rs) AsmString = "fscsr $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, 2, GPR:$rs) AsmString = "fsrm $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, 1, GPR:$rs) AsmString = "fsflags $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) AsmString = "csrw $\xFF\x02\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW GPR:$rd, 3, GPR:$rs) AsmString = "fscsr $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW GPR:$rd, 2, GPR:$rs) AsmString = "fsrm $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (CSRRW GPR:$rd, 1, GPR:$rs) AsmString = "fsflags $\x01, $\x03"; break; } return false; case RISCV_CSRRWI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (CSRRWI X0, 2, uimm5:$imm) AsmString = "fsrmi $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (CSRRWI X0, 1, uimm5:$imm) AsmString = "fsflagsi $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) AsmString = "csrwi $\xFF\x02\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (CSRRWI GPR:$rd, 2, uimm5:$imm) AsmString = "fsrmi $\x01, $\x03"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (CSRRWI GPR:$rd, 1, uimm5:$imm) AsmString = "fsflagsi $\x01, $\x03"; break; } return false; case RISCV_FADD_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) AsmString = "fadd.d $\x01, $\x02, $\x03"; break; } return false; case RISCV_FADD_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) AsmString = "fadd.s $\x01, $\x02, $\x03"; break; } return false; case RISCV_FCVT_D_L: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) AsmString = "fcvt.d.l $\x01, $\x02"; break; } return false; case RISCV_FCVT_D_LU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) AsmString = "fcvt.d.lu $\x01, $\x02"; break; } return false; case RISCV_FCVT_LU_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) AsmString = "fcvt.lu.d $\x01, $\x02"; break; } return false; case RISCV_FCVT_LU_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) AsmString = "fcvt.lu.s $\x01, $\x02"; break; } return false; case RISCV_FCVT_L_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) AsmString = "fcvt.l.d $\x01, $\x02"; break; } return false; case RISCV_FCVT_L_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) AsmString = "fcvt.l.s $\x01, $\x02"; break; } return false; case RISCV_FCVT_S_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) AsmString = "fcvt.s.d $\x01, $\x02"; break; } return false; case RISCV_FCVT_S_L: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) AsmString = "fcvt.s.l $\x01, $\x02"; break; } return false; case RISCV_FCVT_S_LU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) AsmString = "fcvt.s.lu $\x01, $\x02"; break; } return false; case RISCV_FCVT_S_W: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) AsmString = "fcvt.s.w $\x01, $\x02"; break; } return false; case RISCV_FCVT_S_WU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) AsmString = "fcvt.s.wu $\x01, $\x02"; break; } return false; case RISCV_FCVT_WU_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) AsmString = "fcvt.wu.d $\x01, $\x02"; break; } return false; case RISCV_FCVT_WU_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) AsmString = "fcvt.wu.s $\x01, $\x02"; break; } return false; case RISCV_FCVT_W_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) AsmString = "fcvt.w.d $\x01, $\x02"; break; } return false; case RISCV_FCVT_W_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) AsmString = "fcvt.w.s $\x01, $\x02"; break; } return false; case RISCV_FDIV_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) AsmString = "fdiv.d $\x01, $\x02, $\x03"; break; } return false; case RISCV_FDIV_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) AsmString = "fdiv.s $\x01, $\x02, $\x03"; break; } return false; case RISCV_FENCE: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (FENCE 15, 15) AsmString = "fence"; break; } return false; case RISCV_FMADD_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FMADD_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FMSUB_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FMSUB_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FMUL_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) AsmString = "fmul.d $\x01, $\x02, $\x03"; break; } return false; case RISCV_FMUL_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) AsmString = "fmul.s $\x01, $\x02, $\x03"; break; } return false; case RISCV_FNMADD_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FNMADD_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FNMSUB_D: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FNMSUB_S: if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isReg(MCInst_getOperand(MI, 3)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04"; break; } return false; case RISCV_FSGNJN_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) AsmString = "fneg.d $\x01, $\x02"; break; } return false; case RISCV_FSGNJN_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) AsmString = "fneg.s $\x01, $\x02"; break; } return false; case RISCV_FSGNJX_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) AsmString = "fabs.d $\x01, $\x02"; break; } return false; case RISCV_FSGNJX_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) AsmString = "fabs.s $\x01, $\x02"; break; } return false; case RISCV_FSGNJ_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) AsmString = "fmv.d $\x01, $\x02"; break; } return false; case RISCV_FSGNJ_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) AsmString = "fmv.s $\x01, $\x02"; break; } return false; case RISCV_FSQRT_D: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) AsmString = "fsqrt.d $\x01, $\x02"; break; } return false; case RISCV_FSQRT_S: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) AsmString = "fsqrt.s $\x01, $\x02"; break; } return false; case RISCV_FSUB_D: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) AsmString = "fsub.d $\x01, $\x02, $\x03"; break; } return false; case RISCV_FSUB_S: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) AsmString = "fsub.s $\x01, $\x02, $\x03"; break; } return false; case RISCV_JAL: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { // (JAL X0, simm21_lsb0_jal:$offset) AsmString = "j $\x02"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { // (JAL X1, simm21_lsb0_jal:$offset) AsmString = "jal $\x02"; break; } return false; case RISCV_JALR: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (JALR X0, X1, 0) AsmString = "ret"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (JALR X0, GPR:$rs, 0) AsmString = "jr $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (JALR X1, GPR:$rs, 0) AsmString = "jalr $\x02"; break; } return false; case RISCV_SFENCE_VMA: if (MCInst_getNumOperands(MI) == 2 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { // (SFENCE_VMA X0, X0) AsmString = "sfence.vma"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { // (SFENCE_VMA GPR:$rs, X0) AsmString = "sfence.vma $\x01"; break; } return false; case RISCV_SLT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { // (SLT GPR:$rd, GPR:$rs, X0) AsmString = "sltz $\x01, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SLT GPR:$rd, X0, GPR:$rs) AsmString = "sgtz $\x01, $\x03"; break; } return false; case RISCV_SLTIU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (SLTIU GPR:$rd, GPR:$rs, 1) AsmString = "seqz $\x01, $\x02"; break; } return false; case RISCV_SLTU: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SLTU GPR:$rd, X0, GPR:$rs) AsmString = "snez $\x01, $\x03"; break; } return false; case RISCV_SUB: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SUB GPR:$rd, X0, GPR:$rs) AsmString = "neg $\x01, $\x03"; break; } return false; case RISCV_SUBW: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { // (SUBW GPR:$rd, X0, GPR:$rs) AsmString = "negw $\x01, $\x03"; break; } return false; case RISCV_XORI: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) { // (XORI GPR:$rd, GPR:$rs, -1) AsmString = "not $\x01, $\x02"; break; } return false; } AsmStringLen = strlen(AsmString); if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) tmpString = cs_strdup(AsmString); else tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen); while (AsmString[I] != ' ' && AsmString[I] != '\t' && AsmString[I] != '$' && AsmString[I] != '\0') ++I; tmpString[I] = 0; SStream_concat0(OS, tmpString); if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) /* Free the possible cs_strdup() memory. PR#1424. */ cs_mem_free(tmpString); #undef ASMSTRING_CONTAIN_SIZE if (AsmString[I] != '\0') { if (AsmString[I] == ' ' || AsmString[I] == '\t') { SStream_concat0(OS, " "); ++I; } do { if (AsmString[I] == '$') { ++I; if (AsmString[I] == (char)0xff) { ++I; int OpIdx = AsmString[I++] - 1; int PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } else { SStream_concat1(OS, AsmString[I++]); } } while (AsmString[I] != '\0'); } return true; } static void printCustomAliasOperand( MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS) { switch (PrintMethodIdx) { default: CS_ASSERT(0 && "Unknown PrintMethod kind"); break; case 0: printCSRSystemRegister(MI, OpIdx, OS); break; } } static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, unsigned PredicateIndex) { // TODO: need some constant untils operate the MCOperand, // but current CAPSTONE does't have. // So, We just return true return true; #if 0 switch (PredicateIndex) { default: llvm_unreachable("Unknown MCOperandPredicate kind"); break; case 1: { int64_t Imm; if (MCOp.evaluateAsConstantImm(Imm)) return isShiftedInt<12, 1>(Imm); return MCOp.isBareSymbolRef(); } case 2: { int64_t Imm; if (MCOp.evaluateAsConstantImm(Imm)) return isShiftedInt<20, 1>(Imm); return MCOp.isBareSymbolRef(); } } #endif } #endif // PRINT_ALIAS_INSTR capstone-sys-0.15.0/capstone/arch/RISCV/RISCVGenDisassemblerTables.inc000064400000000000000000003071760072674642500235300ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * RISCV Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include "../../MCInst.h" #include "../../LEB128.h" #include "../../cs_priv.h" // Helper functions for extracting fields from encoded instructions. // InsnType must either be integral or an APInt-like object that must: // * Have a static const max_size_in_bits equal to the number of bits in the // encoding. // * be default-constructible and copy-constructible // * be constructible from a uint64_t // * be constructible from an APInt (this can be private) // * Support getBitsSet(loBit, hiBit) // * be convertible to uint64_t // * Support the ~, &, ==, !=, and |= operators with other objects of the same type // * Support shift (<<, >>) with signed and unsigned integers on the RHS // * Support put (<<) to raw_ostream& #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTable16[] = { /* 0 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 3 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 85 /* 8 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 11 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 41 /* 16 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 32 /* 21 */ MCD_OPC_CheckField, 2, 11, 0, 4, 0, 0, // Skip to: 32 /* 28 */ MCD_OPC_Decode, 182, 2, 0, // Opcode: C_UNIMP /* 32 */ MCD_OPC_CheckPredicate, 0, 116, 2, 0, // Skip to: 665 /* 37 */ MCD_OPC_Decode, 144, 2, 1, // Opcode: C_ADDI4SPN /* 41 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 71 /* 46 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 62 /* 51 */ MCD_OPC_CheckField, 7, 6, 0, 4, 0, 0, // Skip to: 62 /* 58 */ MCD_OPC_Decode, 171, 2, 0, // Opcode: C_NOP /* 62 */ MCD_OPC_CheckPredicate, 0, 86, 2, 0, // Skip to: 665 /* 67 */ MCD_OPC_Decode, 142, 2, 2, // Opcode: C_ADDI /* 71 */ MCD_OPC_FilterValue, 2, 77, 2, 0, // Skip to: 665 /* 76 */ MCD_OPC_CheckPredicate, 0, 72, 2, 0, // Skip to: 665 /* 81 */ MCD_OPC_Decode, 175, 2, 3, // Opcode: C_SLLI /* 85 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 135 /* 90 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 93 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 107 /* 98 */ MCD_OPC_CheckPredicate, 1, 50, 2, 0, // Skip to: 665 /* 103 */ MCD_OPC_Decode, 152, 2, 4, // Opcode: C_FLD /* 107 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 121 /* 112 */ MCD_OPC_CheckPredicate, 2, 36, 2, 0, // Skip to: 665 /* 117 */ MCD_OPC_Decode, 145, 2, 2, // Opcode: C_ADDIW /* 121 */ MCD_OPC_FilterValue, 2, 27, 2, 0, // Skip to: 665 /* 126 */ MCD_OPC_CheckPredicate, 1, 22, 2, 0, // Skip to: 665 /* 131 */ MCD_OPC_Decode, 153, 2, 5, // Opcode: C_FLDSP /* 135 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 185 /* 140 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 143 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 157 /* 148 */ MCD_OPC_CheckPredicate, 0, 0, 2, 0, // Skip to: 665 /* 153 */ MCD_OPC_Decode, 168, 2, 6, // Opcode: C_LW /* 157 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 171 /* 162 */ MCD_OPC_CheckPredicate, 0, 242, 1, 0, // Skip to: 665 /* 167 */ MCD_OPC_Decode, 166, 2, 7, // Opcode: C_LI /* 171 */ MCD_OPC_FilterValue, 2, 233, 1, 0, // Skip to: 665 /* 176 */ MCD_OPC_CheckPredicate, 0, 228, 1, 0, // Skip to: 665 /* 181 */ MCD_OPC_Decode, 169, 2, 8, // Opcode: C_LWSP /* 185 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 251 /* 190 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 193 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207 /* 198 */ MCD_OPC_CheckPredicate, 2, 206, 1, 0, // Skip to: 665 /* 203 */ MCD_OPC_Decode, 164, 2, 9, // Opcode: C_LD /* 207 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 237 /* 212 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 228 /* 217 */ MCD_OPC_CheckField, 7, 5, 2, 4, 0, 0, // Skip to: 228 /* 224 */ MCD_OPC_Decode, 143, 2, 10, // Opcode: C_ADDI16SP /* 228 */ MCD_OPC_CheckPredicate, 0, 176, 1, 0, // Skip to: 665 /* 233 */ MCD_OPC_Decode, 167, 2, 11, // Opcode: C_LUI /* 237 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 665 /* 242 */ MCD_OPC_CheckPredicate, 2, 162, 1, 0, // Skip to: 665 /* 247 */ MCD_OPC_Decode, 165, 2, 12, // Opcode: C_LDSP /* 251 */ MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 515 /* 256 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 259 */ MCD_OPC_FilterValue, 1, 167, 0, 0, // Skip to: 431 /* 264 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... /* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 /* 272 */ MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 665 /* 277 */ MCD_OPC_Decode, 177, 2, 13, // Opcode: C_SRLI /* 281 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 295 /* 286 */ MCD_OPC_CheckPredicate, 0, 118, 1, 0, // Skip to: 665 /* 291 */ MCD_OPC_Decode, 176, 2, 13, // Opcode: C_SRAI /* 295 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 309 /* 300 */ MCD_OPC_CheckPredicate, 0, 104, 1, 0, // Skip to: 665 /* 305 */ MCD_OPC_Decode, 148, 2, 14, // Opcode: C_ANDI /* 309 */ MCD_OPC_FilterValue, 3, 95, 1, 0, // Skip to: 665 /* 314 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... /* 317 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 353 /* 322 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 325 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 339 /* 330 */ MCD_OPC_CheckPredicate, 0, 74, 1, 0, // Skip to: 665 /* 335 */ MCD_OPC_Decode, 178, 2, 15, // Opcode: C_SUB /* 339 */ MCD_OPC_FilterValue, 1, 65, 1, 0, // Skip to: 665 /* 344 */ MCD_OPC_CheckPredicate, 2, 60, 1, 0, // Skip to: 665 /* 349 */ MCD_OPC_Decode, 179, 2, 15, // Opcode: C_SUBW /* 353 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 389 /* 358 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 361 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 375 /* 366 */ MCD_OPC_CheckPredicate, 0, 38, 1, 0, // Skip to: 665 /* 371 */ MCD_OPC_Decode, 183, 2, 15, // Opcode: C_XOR /* 375 */ MCD_OPC_FilterValue, 1, 29, 1, 0, // Skip to: 665 /* 380 */ MCD_OPC_CheckPredicate, 2, 24, 1, 0, // Skip to: 665 /* 385 */ MCD_OPC_Decode, 146, 2, 15, // Opcode: C_ADDW /* 389 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 410 /* 394 */ MCD_OPC_CheckPredicate, 0, 10, 1, 0, // Skip to: 665 /* 399 */ MCD_OPC_CheckField, 12, 1, 0, 3, 1, 0, // Skip to: 665 /* 406 */ MCD_OPC_Decode, 172, 2, 15, // Opcode: C_OR /* 410 */ MCD_OPC_FilterValue, 3, 250, 0, 0, // Skip to: 665 /* 415 */ MCD_OPC_CheckPredicate, 0, 245, 0, 0, // Skip to: 665 /* 420 */ MCD_OPC_CheckField, 12, 1, 0, 238, 0, 0, // Skip to: 665 /* 427 */ MCD_OPC_Decode, 147, 2, 15, // Opcode: C_AND /* 431 */ MCD_OPC_FilterValue, 2, 229, 0, 0, // Skip to: 665 /* 436 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 439 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 469 /* 444 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 460 /* 449 */ MCD_OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 460 /* 456 */ MCD_OPC_Decode, 163, 2, 16, // Opcode: C_JR /* 460 */ MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 665 /* 465 */ MCD_OPC_Decode, 170, 2, 17, // Opcode: C_MV /* 469 */ MCD_OPC_FilterValue, 1, 191, 0, 0, // Skip to: 665 /* 474 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 490 /* 479 */ MCD_OPC_CheckField, 2, 10, 0, 4, 0, 0, // Skip to: 490 /* 486 */ MCD_OPC_Decode, 151, 2, 0, // Opcode: C_EBREAK /* 490 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 506 /* 495 */ MCD_OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 506 /* 502 */ MCD_OPC_Decode, 162, 2, 16, // Opcode: C_JALR /* 506 */ MCD_OPC_CheckPredicate, 0, 154, 0, 0, // Skip to: 665 /* 511 */ MCD_OPC_Decode, 141, 2, 18, // Opcode: C_ADD /* 515 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 565 /* 520 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 537 /* 528 */ MCD_OPC_CheckPredicate, 1, 132, 0, 0, // Skip to: 665 /* 533 */ MCD_OPC_Decode, 156, 2, 4, // Opcode: C_FSD /* 537 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 551 /* 542 */ MCD_OPC_CheckPredicate, 0, 118, 0, 0, // Skip to: 665 /* 547 */ MCD_OPC_Decode, 160, 2, 19, // Opcode: C_J /* 551 */ MCD_OPC_FilterValue, 2, 109, 0, 0, // Skip to: 665 /* 556 */ MCD_OPC_CheckPredicate, 1, 104, 0, 0, // Skip to: 665 /* 561 */ MCD_OPC_Decode, 157, 2, 20, // Opcode: C_FSDSP /* 565 */ MCD_OPC_FilterValue, 6, 45, 0, 0, // Skip to: 615 /* 570 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 573 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 587 /* 578 */ MCD_OPC_CheckPredicate, 0, 82, 0, 0, // Skip to: 665 /* 583 */ MCD_OPC_Decode, 180, 2, 6, // Opcode: C_SW /* 587 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 601 /* 592 */ MCD_OPC_CheckPredicate, 0, 68, 0, 0, // Skip to: 665 /* 597 */ MCD_OPC_Decode, 149, 2, 21, // Opcode: C_BEQZ /* 601 */ MCD_OPC_FilterValue, 2, 59, 0, 0, // Skip to: 665 /* 606 */ MCD_OPC_CheckPredicate, 0, 54, 0, 0, // Skip to: 665 /* 611 */ MCD_OPC_Decode, 181, 2, 22, // Opcode: C_SWSP /* 615 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 665 /* 620 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 623 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 637 /* 628 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 665 /* 633 */ MCD_OPC_Decode, 173, 2, 9, // Opcode: C_SD /* 637 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 651 /* 642 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 665 /* 647 */ MCD_OPC_Decode, 150, 2, 21, // Opcode: C_BNEZ /* 651 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 665 /* 656 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 665 /* 661 */ MCD_OPC_Decode, 174, 2, 23, // Opcode: C_SDSP /* 665 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 0, 7, // Inst{6-0} ... /* 3 */ MCD_OPC_FilterValue, 3, 76, 0, 0, // Skip to: 84 /* 8 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 11 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20 /* 16 */ MCD_OPC_Decode, 129, 3, 24, // Opcode: LB /* 20 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 29 /* 25 */ MCD_OPC_Decode, 132, 3, 24, // Opcode: LH /* 29 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 38 /* 34 */ MCD_OPC_Decode, 143, 3, 24, // Opcode: LW /* 38 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 52 /* 43 */ MCD_OPC_CheckPredicate, 3, 55, 15, 0, // Skip to: 3943 /* 48 */ MCD_OPC_Decode, 131, 3, 24, // Opcode: LD /* 52 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 61 /* 57 */ MCD_OPC_Decode, 130, 3, 24, // Opcode: LBU /* 61 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 70 /* 66 */ MCD_OPC_Decode, 133, 3, 24, // Opcode: LHU /* 70 */ MCD_OPC_FilterValue, 6, 28, 15, 0, // Skip to: 3943 /* 75 */ MCD_OPC_CheckPredicate, 3, 23, 15, 0, // Skip to: 3943 /* 80 */ MCD_OPC_Decode, 144, 3, 24, // Opcode: LWU /* 84 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 120 /* 89 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 92 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106 /* 97 */ MCD_OPC_CheckPredicate, 4, 1, 15, 0, // Skip to: 3943 /* 102 */ MCD_OPC_Decode, 224, 2, 25, // Opcode: FLW /* 106 */ MCD_OPC_FilterValue, 3, 248, 14, 0, // Skip to: 3943 /* 111 */ MCD_OPC_CheckPredicate, 5, 243, 14, 0, // Skip to: 3943 /* 116 */ MCD_OPC_Decode, 219, 2, 26, // Opcode: FLD /* 120 */ MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 177 /* 125 */ MCD_OPC_ExtractField, 7, 13, // Inst{19-7} ... /* 128 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 161 /* 133 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... /* 136 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 145 /* 141 */ MCD_OPC_Decode, 214, 2, 27, // Opcode: FENCE /* 145 */ MCD_OPC_FilterValue, 8, 209, 14, 0, // Skip to: 3943 /* 150 */ MCD_OPC_CheckField, 20, 8, 51, 202, 14, 0, // Skip to: 3943 /* 157 */ MCD_OPC_Decode, 216, 2, 0, // Opcode: FENCE_TSO /* 161 */ MCD_OPC_FilterValue, 32, 193, 14, 0, // Skip to: 3943 /* 166 */ MCD_OPC_CheckField, 20, 12, 0, 186, 14, 0, // Skip to: 3943 /* 173 */ MCD_OPC_Decode, 215, 2, 0, // Opcode: FENCE_I /* 177 */ MCD_OPC_FilterValue, 19, 99, 0, 0, // Skip to: 281 /* 182 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 185 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 194 /* 190 */ MCD_OPC_Decode, 179, 1, 24, // Opcode: ADDI /* 194 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 210 /* 199 */ MCD_OPC_CheckField, 26, 6, 0, 153, 14, 0, // Skip to: 3943 /* 206 */ MCD_OPC_Decode, 170, 3, 28, // Opcode: SLLI /* 210 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 219 /* 215 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: SLTI /* 219 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 228 /* 224 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: SLTIU /* 228 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 237 /* 233 */ MCD_OPC_Decode, 193, 3, 24, // Opcode: XORI /* 237 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 263 /* 242 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... /* 245 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 254 /* 250 */ MCD_OPC_Decode, 183, 3, 28, // Opcode: SRLI /* 254 */ MCD_OPC_FilterValue, 16, 100, 14, 0, // Skip to: 3943 /* 259 */ MCD_OPC_Decode, 178, 3, 28, // Opcode: SRAI /* 263 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 272 /* 268 */ MCD_OPC_Decode, 152, 3, 24, // Opcode: ORI /* 272 */ MCD_OPC_FilterValue, 7, 82, 14, 0, // Skip to: 3943 /* 277 */ MCD_OPC_Decode, 255, 1, 24, // Opcode: ANDI /* 281 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 290 /* 286 */ MCD_OPC_Decode, 128, 2, 29, // Opcode: AUIPC /* 290 */ MCD_OPC_FilterValue, 27, 74, 0, 0, // Skip to: 369 /* 295 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 298 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 312 /* 303 */ MCD_OPC_CheckPredicate, 3, 51, 14, 0, // Skip to: 3943 /* 308 */ MCD_OPC_Decode, 180, 1, 24, // Opcode: ADDIW /* 312 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 333 /* 317 */ MCD_OPC_CheckPredicate, 3, 37, 14, 0, // Skip to: 3943 /* 322 */ MCD_OPC_CheckField, 25, 7, 0, 30, 14, 0, // Skip to: 3943 /* 329 */ MCD_OPC_Decode, 171, 3, 30, // Opcode: SLLIW /* 333 */ MCD_OPC_FilterValue, 5, 21, 14, 0, // Skip to: 3943 /* 338 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 341 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 355 /* 346 */ MCD_OPC_CheckPredicate, 3, 8, 14, 0, // Skip to: 3943 /* 351 */ MCD_OPC_Decode, 184, 3, 30, // Opcode: SRLIW /* 355 */ MCD_OPC_FilterValue, 32, 255, 13, 0, // Skip to: 3943 /* 360 */ MCD_OPC_CheckPredicate, 3, 250, 13, 0, // Skip to: 3943 /* 365 */ MCD_OPC_Decode, 179, 3, 30, // Opcode: SRAIW /* 369 */ MCD_OPC_FilterValue, 35, 44, 0, 0, // Skip to: 418 /* 374 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 377 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 386 /* 382 */ MCD_OPC_Decode, 157, 3, 31, // Opcode: SB /* 386 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 395 /* 391 */ MCD_OPC_Decode, 168, 3, 31, // Opcode: SH /* 395 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 404 /* 400 */ MCD_OPC_Decode, 188, 3, 31, // Opcode: SW /* 404 */ MCD_OPC_FilterValue, 3, 206, 13, 0, // Skip to: 3943 /* 409 */ MCD_OPC_CheckPredicate, 3, 201, 13, 0, // Skip to: 3943 /* 414 */ MCD_OPC_Decode, 166, 3, 31, // Opcode: SD /* 418 */ MCD_OPC_FilterValue, 39, 31, 0, 0, // Skip to: 454 /* 423 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 426 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 440 /* 431 */ MCD_OPC_CheckPredicate, 4, 179, 13, 0, // Skip to: 3943 /* 436 */ MCD_OPC_Decode, 254, 2, 32, // Opcode: FSW /* 440 */ MCD_OPC_FilterValue, 3, 170, 13, 0, // Skip to: 3943 /* 445 */ MCD_OPC_CheckPredicate, 5, 165, 13, 0, // Skip to: 3943 /* 450 */ MCD_OPC_Decode, 243, 2, 33, // Opcode: FSD /* 454 */ MCD_OPC_FilterValue, 47, 107, 6, 0, // Skip to: 2102 /* 459 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 462 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 498 /* 467 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 470 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 484 /* 475 */ MCD_OPC_CheckPredicate, 6, 135, 13, 0, // Skip to: 3943 /* 480 */ MCD_OPC_Decode, 186, 1, 34, // Opcode: AMOADD_W /* 484 */ MCD_OPC_FilterValue, 3, 126, 13, 0, // Skip to: 3943 /* 489 */ MCD_OPC_CheckPredicate, 7, 121, 13, 0, // Skip to: 3943 /* 494 */ MCD_OPC_Decode, 182, 1, 34, // Opcode: AMOADD_D /* 498 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 534 /* 503 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 506 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 520 /* 511 */ MCD_OPC_CheckPredicate, 6, 99, 13, 0, // Skip to: 3943 /* 516 */ MCD_OPC_Decode, 189, 1, 34, // Opcode: AMOADD_W_RL /* 520 */ MCD_OPC_FilterValue, 3, 90, 13, 0, // Skip to: 3943 /* 525 */ MCD_OPC_CheckPredicate, 7, 85, 13, 0, // Skip to: 3943 /* 530 */ MCD_OPC_Decode, 185, 1, 34, // Opcode: AMOADD_D_RL /* 534 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 570 /* 539 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 542 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 556 /* 547 */ MCD_OPC_CheckPredicate, 6, 63, 13, 0, // Skip to: 3943 /* 552 */ MCD_OPC_Decode, 187, 1, 34, // Opcode: AMOADD_W_AQ /* 556 */ MCD_OPC_FilterValue, 3, 54, 13, 0, // Skip to: 3943 /* 561 */ MCD_OPC_CheckPredicate, 7, 49, 13, 0, // Skip to: 3943 /* 566 */ MCD_OPC_Decode, 183, 1, 34, // Opcode: AMOADD_D_AQ /* 570 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 606 /* 575 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 578 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 592 /* 583 */ MCD_OPC_CheckPredicate, 6, 27, 13, 0, // Skip to: 3943 /* 588 */ MCD_OPC_Decode, 188, 1, 34, // Opcode: AMOADD_W_AQ_RL /* 592 */ MCD_OPC_FilterValue, 3, 18, 13, 0, // Skip to: 3943 /* 597 */ MCD_OPC_CheckPredicate, 7, 13, 13, 0, // Skip to: 3943 /* 602 */ MCD_OPC_Decode, 184, 1, 34, // Opcode: AMOADD_D_AQ_RL /* 606 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 642 /* 611 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 614 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 628 /* 619 */ MCD_OPC_CheckPredicate, 6, 247, 12, 0, // Skip to: 3943 /* 624 */ MCD_OPC_Decode, 242, 1, 34, // Opcode: AMOSWAP_W /* 628 */ MCD_OPC_FilterValue, 3, 238, 12, 0, // Skip to: 3943 /* 633 */ MCD_OPC_CheckPredicate, 7, 233, 12, 0, // Skip to: 3943 /* 638 */ MCD_OPC_Decode, 238, 1, 34, // Opcode: AMOSWAP_D /* 642 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 678 /* 647 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 650 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 664 /* 655 */ MCD_OPC_CheckPredicate, 6, 211, 12, 0, // Skip to: 3943 /* 660 */ MCD_OPC_Decode, 245, 1, 34, // Opcode: AMOSWAP_W_RL /* 664 */ MCD_OPC_FilterValue, 3, 202, 12, 0, // Skip to: 3943 /* 669 */ MCD_OPC_CheckPredicate, 7, 197, 12, 0, // Skip to: 3943 /* 674 */ MCD_OPC_Decode, 241, 1, 34, // Opcode: AMOSWAP_D_RL /* 678 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 714 /* 683 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 686 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 700 /* 691 */ MCD_OPC_CheckPredicate, 6, 175, 12, 0, // Skip to: 3943 /* 696 */ MCD_OPC_Decode, 243, 1, 34, // Opcode: AMOSWAP_W_AQ /* 700 */ MCD_OPC_FilterValue, 3, 166, 12, 0, // Skip to: 3943 /* 705 */ MCD_OPC_CheckPredicate, 7, 161, 12, 0, // Skip to: 3943 /* 710 */ MCD_OPC_Decode, 239, 1, 34, // Opcode: AMOSWAP_D_AQ /* 714 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 750 /* 719 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 722 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 736 /* 727 */ MCD_OPC_CheckPredicate, 6, 139, 12, 0, // Skip to: 3943 /* 732 */ MCD_OPC_Decode, 244, 1, 34, // Opcode: AMOSWAP_W_AQ_RL /* 736 */ MCD_OPC_FilterValue, 3, 130, 12, 0, // Skip to: 3943 /* 741 */ MCD_OPC_CheckPredicate, 7, 125, 12, 0, // Skip to: 3943 /* 746 */ MCD_OPC_Decode, 240, 1, 34, // Opcode: AMOSWAP_D_AQ_RL /* 750 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 800 /* 755 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 758 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 779 /* 763 */ MCD_OPC_CheckPredicate, 6, 103, 12, 0, // Skip to: 3943 /* 768 */ MCD_OPC_CheckField, 20, 5, 0, 96, 12, 0, // Skip to: 3943 /* 775 */ MCD_OPC_Decode, 138, 3, 35, // Opcode: LR_W /* 779 */ MCD_OPC_FilterValue, 3, 87, 12, 0, // Skip to: 3943 /* 784 */ MCD_OPC_CheckPredicate, 7, 82, 12, 0, // Skip to: 3943 /* 789 */ MCD_OPC_CheckField, 20, 5, 0, 75, 12, 0, // Skip to: 3943 /* 796 */ MCD_OPC_Decode, 134, 3, 35, // Opcode: LR_D /* 800 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 850 /* 805 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 808 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 829 /* 813 */ MCD_OPC_CheckPredicate, 6, 53, 12, 0, // Skip to: 3943 /* 818 */ MCD_OPC_CheckField, 20, 5, 0, 46, 12, 0, // Skip to: 3943 /* 825 */ MCD_OPC_Decode, 141, 3, 35, // Opcode: LR_W_RL /* 829 */ MCD_OPC_FilterValue, 3, 37, 12, 0, // Skip to: 3943 /* 834 */ MCD_OPC_CheckPredicate, 7, 32, 12, 0, // Skip to: 3943 /* 839 */ MCD_OPC_CheckField, 20, 5, 0, 25, 12, 0, // Skip to: 3943 /* 846 */ MCD_OPC_Decode, 137, 3, 35, // Opcode: LR_D_RL /* 850 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 900 /* 855 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 858 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 879 /* 863 */ MCD_OPC_CheckPredicate, 6, 3, 12, 0, // Skip to: 3943 /* 868 */ MCD_OPC_CheckField, 20, 5, 0, 252, 11, 0, // Skip to: 3943 /* 875 */ MCD_OPC_Decode, 139, 3, 35, // Opcode: LR_W_AQ /* 879 */ MCD_OPC_FilterValue, 3, 243, 11, 0, // Skip to: 3943 /* 884 */ MCD_OPC_CheckPredicate, 7, 238, 11, 0, // Skip to: 3943 /* 889 */ MCD_OPC_CheckField, 20, 5, 0, 231, 11, 0, // Skip to: 3943 /* 896 */ MCD_OPC_Decode, 135, 3, 35, // Opcode: LR_D_AQ /* 900 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 950 /* 905 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 908 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 929 /* 913 */ MCD_OPC_CheckPredicate, 6, 209, 11, 0, // Skip to: 3943 /* 918 */ MCD_OPC_CheckField, 20, 5, 0, 202, 11, 0, // Skip to: 3943 /* 925 */ MCD_OPC_Decode, 140, 3, 35, // Opcode: LR_W_AQ_RL /* 929 */ MCD_OPC_FilterValue, 3, 193, 11, 0, // Skip to: 3943 /* 934 */ MCD_OPC_CheckPredicate, 7, 188, 11, 0, // Skip to: 3943 /* 939 */ MCD_OPC_CheckField, 20, 5, 0, 181, 11, 0, // Skip to: 3943 /* 946 */ MCD_OPC_Decode, 136, 3, 35, // Opcode: LR_D_AQ_RL /* 950 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 986 /* 955 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 958 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 972 /* 963 */ MCD_OPC_CheckPredicate, 6, 159, 11, 0, // Skip to: 3943 /* 968 */ MCD_OPC_Decode, 162, 3, 34, // Opcode: SC_W /* 972 */ MCD_OPC_FilterValue, 3, 150, 11, 0, // Skip to: 3943 /* 977 */ MCD_OPC_CheckPredicate, 7, 145, 11, 0, // Skip to: 3943 /* 982 */ MCD_OPC_Decode, 158, 3, 34, // Opcode: SC_D /* 986 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1022 /* 991 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 994 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1008 /* 999 */ MCD_OPC_CheckPredicate, 6, 123, 11, 0, // Skip to: 3943 /* 1004 */ MCD_OPC_Decode, 165, 3, 34, // Opcode: SC_W_RL /* 1008 */ MCD_OPC_FilterValue, 3, 114, 11, 0, // Skip to: 3943 /* 1013 */ MCD_OPC_CheckPredicate, 7, 109, 11, 0, // Skip to: 3943 /* 1018 */ MCD_OPC_Decode, 161, 3, 34, // Opcode: SC_D_RL /* 1022 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1058 /* 1027 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1030 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1044 /* 1035 */ MCD_OPC_CheckPredicate, 6, 87, 11, 0, // Skip to: 3943 /* 1040 */ MCD_OPC_Decode, 163, 3, 34, // Opcode: SC_W_AQ /* 1044 */ MCD_OPC_FilterValue, 3, 78, 11, 0, // Skip to: 3943 /* 1049 */ MCD_OPC_CheckPredicate, 7, 73, 11, 0, // Skip to: 3943 /* 1054 */ MCD_OPC_Decode, 159, 3, 34, // Opcode: SC_D_AQ /* 1058 */ MCD_OPC_FilterValue, 15, 31, 0, 0, // Skip to: 1094 /* 1063 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1066 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1080 /* 1071 */ MCD_OPC_CheckPredicate, 6, 51, 11, 0, // Skip to: 3943 /* 1076 */ MCD_OPC_Decode, 164, 3, 34, // Opcode: SC_W_AQ_RL /* 1080 */ MCD_OPC_FilterValue, 3, 42, 11, 0, // Skip to: 3943 /* 1085 */ MCD_OPC_CheckPredicate, 7, 37, 11, 0, // Skip to: 3943 /* 1090 */ MCD_OPC_Decode, 160, 3, 34, // Opcode: SC_D_AQ_RL /* 1094 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1130 /* 1099 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1102 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1116 /* 1107 */ MCD_OPC_CheckPredicate, 6, 15, 11, 0, // Skip to: 3943 /* 1112 */ MCD_OPC_Decode, 250, 1, 34, // Opcode: AMOXOR_W /* 1116 */ MCD_OPC_FilterValue, 3, 6, 11, 0, // Skip to: 3943 /* 1121 */ MCD_OPC_CheckPredicate, 7, 1, 11, 0, // Skip to: 3943 /* 1126 */ MCD_OPC_Decode, 246, 1, 34, // Opcode: AMOXOR_D /* 1130 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1166 /* 1135 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1138 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1152 /* 1143 */ MCD_OPC_CheckPredicate, 6, 235, 10, 0, // Skip to: 3943 /* 1148 */ MCD_OPC_Decode, 253, 1, 34, // Opcode: AMOXOR_W_RL /* 1152 */ MCD_OPC_FilterValue, 3, 226, 10, 0, // Skip to: 3943 /* 1157 */ MCD_OPC_CheckPredicate, 7, 221, 10, 0, // Skip to: 3943 /* 1162 */ MCD_OPC_Decode, 249, 1, 34, // Opcode: AMOXOR_D_RL /* 1166 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 1202 /* 1171 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1174 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1188 /* 1179 */ MCD_OPC_CheckPredicate, 6, 199, 10, 0, // Skip to: 3943 /* 1184 */ MCD_OPC_Decode, 251, 1, 34, // Opcode: AMOXOR_W_AQ /* 1188 */ MCD_OPC_FilterValue, 3, 190, 10, 0, // Skip to: 3943 /* 1193 */ MCD_OPC_CheckPredicate, 7, 185, 10, 0, // Skip to: 3943 /* 1198 */ MCD_OPC_Decode, 247, 1, 34, // Opcode: AMOXOR_D_AQ /* 1202 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1238 /* 1207 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1210 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1224 /* 1215 */ MCD_OPC_CheckPredicate, 6, 163, 10, 0, // Skip to: 3943 /* 1220 */ MCD_OPC_Decode, 252, 1, 34, // Opcode: AMOXOR_W_AQ_RL /* 1224 */ MCD_OPC_FilterValue, 3, 154, 10, 0, // Skip to: 3943 /* 1229 */ MCD_OPC_CheckPredicate, 7, 149, 10, 0, // Skip to: 3943 /* 1234 */ MCD_OPC_Decode, 248, 1, 34, // Opcode: AMOXOR_D_AQ_RL /* 1238 */ MCD_OPC_FilterValue, 32, 31, 0, 0, // Skip to: 1274 /* 1243 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1246 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1260 /* 1251 */ MCD_OPC_CheckPredicate, 6, 127, 10, 0, // Skip to: 3943 /* 1256 */ MCD_OPC_Decode, 234, 1, 34, // Opcode: AMOOR_W /* 1260 */ MCD_OPC_FilterValue, 3, 118, 10, 0, // Skip to: 3943 /* 1265 */ MCD_OPC_CheckPredicate, 7, 113, 10, 0, // Skip to: 3943 /* 1270 */ MCD_OPC_Decode, 230, 1, 34, // Opcode: AMOOR_D /* 1274 */ MCD_OPC_FilterValue, 33, 31, 0, 0, // Skip to: 1310 /* 1279 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1282 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1296 /* 1287 */ MCD_OPC_CheckPredicate, 6, 91, 10, 0, // Skip to: 3943 /* 1292 */ MCD_OPC_Decode, 237, 1, 34, // Opcode: AMOOR_W_RL /* 1296 */ MCD_OPC_FilterValue, 3, 82, 10, 0, // Skip to: 3943 /* 1301 */ MCD_OPC_CheckPredicate, 7, 77, 10, 0, // Skip to: 3943 /* 1306 */ MCD_OPC_Decode, 233, 1, 34, // Opcode: AMOOR_D_RL /* 1310 */ MCD_OPC_FilterValue, 34, 31, 0, 0, // Skip to: 1346 /* 1315 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1318 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1332 /* 1323 */ MCD_OPC_CheckPredicate, 6, 55, 10, 0, // Skip to: 3943 /* 1328 */ MCD_OPC_Decode, 235, 1, 34, // Opcode: AMOOR_W_AQ /* 1332 */ MCD_OPC_FilterValue, 3, 46, 10, 0, // Skip to: 3943 /* 1337 */ MCD_OPC_CheckPredicate, 7, 41, 10, 0, // Skip to: 3943 /* 1342 */ MCD_OPC_Decode, 231, 1, 34, // Opcode: AMOOR_D_AQ /* 1346 */ MCD_OPC_FilterValue, 35, 31, 0, 0, // Skip to: 1382 /* 1351 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1354 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1368 /* 1359 */ MCD_OPC_CheckPredicate, 6, 19, 10, 0, // Skip to: 3943 /* 1364 */ MCD_OPC_Decode, 236, 1, 34, // Opcode: AMOOR_W_AQ_RL /* 1368 */ MCD_OPC_FilterValue, 3, 10, 10, 0, // Skip to: 3943 /* 1373 */ MCD_OPC_CheckPredicate, 7, 5, 10, 0, // Skip to: 3943 /* 1378 */ MCD_OPC_Decode, 232, 1, 34, // Opcode: AMOOR_D_AQ_RL /* 1382 */ MCD_OPC_FilterValue, 48, 31, 0, 0, // Skip to: 1418 /* 1387 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1390 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1404 /* 1395 */ MCD_OPC_CheckPredicate, 6, 239, 9, 0, // Skip to: 3943 /* 1400 */ MCD_OPC_Decode, 194, 1, 34, // Opcode: AMOAND_W /* 1404 */ MCD_OPC_FilterValue, 3, 230, 9, 0, // Skip to: 3943 /* 1409 */ MCD_OPC_CheckPredicate, 7, 225, 9, 0, // Skip to: 3943 /* 1414 */ MCD_OPC_Decode, 190, 1, 34, // Opcode: AMOAND_D /* 1418 */ MCD_OPC_FilterValue, 49, 31, 0, 0, // Skip to: 1454 /* 1423 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1426 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1440 /* 1431 */ MCD_OPC_CheckPredicate, 6, 203, 9, 0, // Skip to: 3943 /* 1436 */ MCD_OPC_Decode, 197, 1, 34, // Opcode: AMOAND_W_RL /* 1440 */ MCD_OPC_FilterValue, 3, 194, 9, 0, // Skip to: 3943 /* 1445 */ MCD_OPC_CheckPredicate, 7, 189, 9, 0, // Skip to: 3943 /* 1450 */ MCD_OPC_Decode, 193, 1, 34, // Opcode: AMOAND_D_RL /* 1454 */ MCD_OPC_FilterValue, 50, 31, 0, 0, // Skip to: 1490 /* 1459 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1462 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1476 /* 1467 */ MCD_OPC_CheckPredicate, 6, 167, 9, 0, // Skip to: 3943 /* 1472 */ MCD_OPC_Decode, 195, 1, 34, // Opcode: AMOAND_W_AQ /* 1476 */ MCD_OPC_FilterValue, 3, 158, 9, 0, // Skip to: 3943 /* 1481 */ MCD_OPC_CheckPredicate, 7, 153, 9, 0, // Skip to: 3943 /* 1486 */ MCD_OPC_Decode, 191, 1, 34, // Opcode: AMOAND_D_AQ /* 1490 */ MCD_OPC_FilterValue, 51, 31, 0, 0, // Skip to: 1526 /* 1495 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1498 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1512 /* 1503 */ MCD_OPC_CheckPredicate, 6, 131, 9, 0, // Skip to: 3943 /* 1508 */ MCD_OPC_Decode, 196, 1, 34, // Opcode: AMOAND_W_AQ_RL /* 1512 */ MCD_OPC_FilterValue, 3, 122, 9, 0, // Skip to: 3943 /* 1517 */ MCD_OPC_CheckPredicate, 7, 117, 9, 0, // Skip to: 3943 /* 1522 */ MCD_OPC_Decode, 192, 1, 34, // Opcode: AMOAND_D_AQ_RL /* 1526 */ MCD_OPC_FilterValue, 64, 31, 0, 0, // Skip to: 1562 /* 1531 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1534 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1548 /* 1539 */ MCD_OPC_CheckPredicate, 6, 95, 9, 0, // Skip to: 3943 /* 1544 */ MCD_OPC_Decode, 226, 1, 34, // Opcode: AMOMIN_W /* 1548 */ MCD_OPC_FilterValue, 3, 86, 9, 0, // Skip to: 3943 /* 1553 */ MCD_OPC_CheckPredicate, 7, 81, 9, 0, // Skip to: 3943 /* 1558 */ MCD_OPC_Decode, 222, 1, 34, // Opcode: AMOMIN_D /* 1562 */ MCD_OPC_FilterValue, 65, 31, 0, 0, // Skip to: 1598 /* 1567 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1570 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1584 /* 1575 */ MCD_OPC_CheckPredicate, 6, 59, 9, 0, // Skip to: 3943 /* 1580 */ MCD_OPC_Decode, 229, 1, 34, // Opcode: AMOMIN_W_RL /* 1584 */ MCD_OPC_FilterValue, 3, 50, 9, 0, // Skip to: 3943 /* 1589 */ MCD_OPC_CheckPredicate, 7, 45, 9, 0, // Skip to: 3943 /* 1594 */ MCD_OPC_Decode, 225, 1, 34, // Opcode: AMOMIN_D_RL /* 1598 */ MCD_OPC_FilterValue, 66, 31, 0, 0, // Skip to: 1634 /* 1603 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1606 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1620 /* 1611 */ MCD_OPC_CheckPredicate, 6, 23, 9, 0, // Skip to: 3943 /* 1616 */ MCD_OPC_Decode, 227, 1, 34, // Opcode: AMOMIN_W_AQ /* 1620 */ MCD_OPC_FilterValue, 3, 14, 9, 0, // Skip to: 3943 /* 1625 */ MCD_OPC_CheckPredicate, 7, 9, 9, 0, // Skip to: 3943 /* 1630 */ MCD_OPC_Decode, 223, 1, 34, // Opcode: AMOMIN_D_AQ /* 1634 */ MCD_OPC_FilterValue, 67, 31, 0, 0, // Skip to: 1670 /* 1639 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1642 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1656 /* 1647 */ MCD_OPC_CheckPredicate, 6, 243, 8, 0, // Skip to: 3943 /* 1652 */ MCD_OPC_Decode, 228, 1, 34, // Opcode: AMOMIN_W_AQ_RL /* 1656 */ MCD_OPC_FilterValue, 3, 234, 8, 0, // Skip to: 3943 /* 1661 */ MCD_OPC_CheckPredicate, 7, 229, 8, 0, // Skip to: 3943 /* 1666 */ MCD_OPC_Decode, 224, 1, 34, // Opcode: AMOMIN_D_AQ_RL /* 1670 */ MCD_OPC_FilterValue, 80, 31, 0, 0, // Skip to: 1706 /* 1675 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1678 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1692 /* 1683 */ MCD_OPC_CheckPredicate, 6, 207, 8, 0, // Skip to: 3943 /* 1688 */ MCD_OPC_Decode, 210, 1, 34, // Opcode: AMOMAX_W /* 1692 */ MCD_OPC_FilterValue, 3, 198, 8, 0, // Skip to: 3943 /* 1697 */ MCD_OPC_CheckPredicate, 7, 193, 8, 0, // Skip to: 3943 /* 1702 */ MCD_OPC_Decode, 206, 1, 34, // Opcode: AMOMAX_D /* 1706 */ MCD_OPC_FilterValue, 81, 31, 0, 0, // Skip to: 1742 /* 1711 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1714 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1728 /* 1719 */ MCD_OPC_CheckPredicate, 6, 171, 8, 0, // Skip to: 3943 /* 1724 */ MCD_OPC_Decode, 213, 1, 34, // Opcode: AMOMAX_W_RL /* 1728 */ MCD_OPC_FilterValue, 3, 162, 8, 0, // Skip to: 3943 /* 1733 */ MCD_OPC_CheckPredicate, 7, 157, 8, 0, // Skip to: 3943 /* 1738 */ MCD_OPC_Decode, 209, 1, 34, // Opcode: AMOMAX_D_RL /* 1742 */ MCD_OPC_FilterValue, 82, 31, 0, 0, // Skip to: 1778 /* 1747 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1750 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1764 /* 1755 */ MCD_OPC_CheckPredicate, 6, 135, 8, 0, // Skip to: 3943 /* 1760 */ MCD_OPC_Decode, 211, 1, 34, // Opcode: AMOMAX_W_AQ /* 1764 */ MCD_OPC_FilterValue, 3, 126, 8, 0, // Skip to: 3943 /* 1769 */ MCD_OPC_CheckPredicate, 7, 121, 8, 0, // Skip to: 3943 /* 1774 */ MCD_OPC_Decode, 207, 1, 34, // Opcode: AMOMAX_D_AQ /* 1778 */ MCD_OPC_FilterValue, 83, 31, 0, 0, // Skip to: 1814 /* 1783 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1786 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1800 /* 1791 */ MCD_OPC_CheckPredicate, 6, 99, 8, 0, // Skip to: 3943 /* 1796 */ MCD_OPC_Decode, 212, 1, 34, // Opcode: AMOMAX_W_AQ_RL /* 1800 */ MCD_OPC_FilterValue, 3, 90, 8, 0, // Skip to: 3943 /* 1805 */ MCD_OPC_CheckPredicate, 7, 85, 8, 0, // Skip to: 3943 /* 1810 */ MCD_OPC_Decode, 208, 1, 34, // Opcode: AMOMAX_D_AQ_RL /* 1814 */ MCD_OPC_FilterValue, 96, 31, 0, 0, // Skip to: 1850 /* 1819 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1822 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1836 /* 1827 */ MCD_OPC_CheckPredicate, 6, 63, 8, 0, // Skip to: 3943 /* 1832 */ MCD_OPC_Decode, 218, 1, 34, // Opcode: AMOMINU_W /* 1836 */ MCD_OPC_FilterValue, 3, 54, 8, 0, // Skip to: 3943 /* 1841 */ MCD_OPC_CheckPredicate, 7, 49, 8, 0, // Skip to: 3943 /* 1846 */ MCD_OPC_Decode, 214, 1, 34, // Opcode: AMOMINU_D /* 1850 */ MCD_OPC_FilterValue, 97, 31, 0, 0, // Skip to: 1886 /* 1855 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1858 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1872 /* 1863 */ MCD_OPC_CheckPredicate, 6, 27, 8, 0, // Skip to: 3943 /* 1868 */ MCD_OPC_Decode, 221, 1, 34, // Opcode: AMOMINU_W_RL /* 1872 */ MCD_OPC_FilterValue, 3, 18, 8, 0, // Skip to: 3943 /* 1877 */ MCD_OPC_CheckPredicate, 7, 13, 8, 0, // Skip to: 3943 /* 1882 */ MCD_OPC_Decode, 217, 1, 34, // Opcode: AMOMINU_D_RL /* 1886 */ MCD_OPC_FilterValue, 98, 31, 0, 0, // Skip to: 1922 /* 1891 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1894 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1908 /* 1899 */ MCD_OPC_CheckPredicate, 6, 247, 7, 0, // Skip to: 3943 /* 1904 */ MCD_OPC_Decode, 219, 1, 34, // Opcode: AMOMINU_W_AQ /* 1908 */ MCD_OPC_FilterValue, 3, 238, 7, 0, // Skip to: 3943 /* 1913 */ MCD_OPC_CheckPredicate, 7, 233, 7, 0, // Skip to: 3943 /* 1918 */ MCD_OPC_Decode, 215, 1, 34, // Opcode: AMOMINU_D_AQ /* 1922 */ MCD_OPC_FilterValue, 99, 31, 0, 0, // Skip to: 1958 /* 1927 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1930 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1944 /* 1935 */ MCD_OPC_CheckPredicate, 6, 211, 7, 0, // Skip to: 3943 /* 1940 */ MCD_OPC_Decode, 220, 1, 34, // Opcode: AMOMINU_W_AQ_RL /* 1944 */ MCD_OPC_FilterValue, 3, 202, 7, 0, // Skip to: 3943 /* 1949 */ MCD_OPC_CheckPredicate, 7, 197, 7, 0, // Skip to: 3943 /* 1954 */ MCD_OPC_Decode, 216, 1, 34, // Opcode: AMOMINU_D_AQ_RL /* 1958 */ MCD_OPC_FilterValue, 112, 31, 0, 0, // Skip to: 1994 /* 1963 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 1966 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1980 /* 1971 */ MCD_OPC_CheckPredicate, 6, 175, 7, 0, // Skip to: 3943 /* 1976 */ MCD_OPC_Decode, 202, 1, 34, // Opcode: AMOMAXU_W /* 1980 */ MCD_OPC_FilterValue, 3, 166, 7, 0, // Skip to: 3943 /* 1985 */ MCD_OPC_CheckPredicate, 7, 161, 7, 0, // Skip to: 3943 /* 1990 */ MCD_OPC_Decode, 198, 1, 34, // Opcode: AMOMAXU_D /* 1994 */ MCD_OPC_FilterValue, 113, 31, 0, 0, // Skip to: 2030 /* 1999 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2002 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2016 /* 2007 */ MCD_OPC_CheckPredicate, 6, 139, 7, 0, // Skip to: 3943 /* 2012 */ MCD_OPC_Decode, 205, 1, 34, // Opcode: AMOMAXU_W_RL /* 2016 */ MCD_OPC_FilterValue, 3, 130, 7, 0, // Skip to: 3943 /* 2021 */ MCD_OPC_CheckPredicate, 7, 125, 7, 0, // Skip to: 3943 /* 2026 */ MCD_OPC_Decode, 201, 1, 34, // Opcode: AMOMAXU_D_RL /* 2030 */ MCD_OPC_FilterValue, 114, 31, 0, 0, // Skip to: 2066 /* 2035 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2038 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2052 /* 2043 */ MCD_OPC_CheckPredicate, 6, 103, 7, 0, // Skip to: 3943 /* 2048 */ MCD_OPC_Decode, 203, 1, 34, // Opcode: AMOMAXU_W_AQ /* 2052 */ MCD_OPC_FilterValue, 3, 94, 7, 0, // Skip to: 3943 /* 2057 */ MCD_OPC_CheckPredicate, 7, 89, 7, 0, // Skip to: 3943 /* 2062 */ MCD_OPC_Decode, 199, 1, 34, // Opcode: AMOMAXU_D_AQ /* 2066 */ MCD_OPC_FilterValue, 115, 80, 7, 0, // Skip to: 3943 /* 2071 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2074 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2088 /* 2079 */ MCD_OPC_CheckPredicate, 6, 67, 7, 0, // Skip to: 3943 /* 2084 */ MCD_OPC_Decode, 204, 1, 34, // Opcode: AMOMAXU_W_AQ_RL /* 2088 */ MCD_OPC_FilterValue, 3, 58, 7, 0, // Skip to: 3943 /* 2093 */ MCD_OPC_CheckPredicate, 7, 53, 7, 0, // Skip to: 3943 /* 2098 */ MCD_OPC_Decode, 200, 1, 34, // Opcode: AMOMAXU_D_AQ_RL /* 2102 */ MCD_OPC_FilterValue, 51, 13, 1, 0, // Skip to: 2376 /* 2107 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2110 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2150 /* 2115 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2118 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2127 /* 2123 */ MCD_OPC_Decode, 178, 1, 34, // Opcode: ADD /* 2127 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2141 /* 2132 */ MCD_OPC_CheckPredicate, 8, 14, 7, 0, // Skip to: 3943 /* 2137 */ MCD_OPC_Decode, 146, 3, 34, // Opcode: MUL /* 2141 */ MCD_OPC_FilterValue, 32, 5, 7, 0, // Skip to: 3943 /* 2146 */ MCD_OPC_Decode, 186, 3, 34, // Opcode: SUB /* 2150 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 2181 /* 2155 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2158 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2167 /* 2163 */ MCD_OPC_Decode, 169, 3, 34, // Opcode: SLL /* 2167 */ MCD_OPC_FilterValue, 1, 235, 6, 0, // Skip to: 3943 /* 2172 */ MCD_OPC_CheckPredicate, 8, 230, 6, 0, // Skip to: 3943 /* 2177 */ MCD_OPC_Decode, 147, 3, 34, // Opcode: MULH /* 2181 */ MCD_OPC_FilterValue, 2, 26, 0, 0, // Skip to: 2212 /* 2186 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2189 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2198 /* 2194 */ MCD_OPC_Decode, 173, 3, 34, // Opcode: SLT /* 2198 */ MCD_OPC_FilterValue, 1, 204, 6, 0, // Skip to: 3943 /* 2203 */ MCD_OPC_CheckPredicate, 8, 199, 6, 0, // Skip to: 3943 /* 2208 */ MCD_OPC_Decode, 148, 3, 34, // Opcode: MULHSU /* 2212 */ MCD_OPC_FilterValue, 3, 26, 0, 0, // Skip to: 2243 /* 2217 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2220 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2229 /* 2225 */ MCD_OPC_Decode, 176, 3, 34, // Opcode: SLTU /* 2229 */ MCD_OPC_FilterValue, 1, 173, 6, 0, // Skip to: 3943 /* 2234 */ MCD_OPC_CheckPredicate, 8, 168, 6, 0, // Skip to: 3943 /* 2239 */ MCD_OPC_Decode, 149, 3, 34, // Opcode: MULHU /* 2243 */ MCD_OPC_FilterValue, 4, 26, 0, 0, // Skip to: 2274 /* 2248 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2251 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2260 /* 2256 */ MCD_OPC_Decode, 192, 3, 34, // Opcode: XOR /* 2260 */ MCD_OPC_FilterValue, 1, 142, 6, 0, // Skip to: 3943 /* 2265 */ MCD_OPC_CheckPredicate, 8, 137, 6, 0, // Skip to: 3943 /* 2270 */ MCD_OPC_Decode, 184, 2, 34, // Opcode: DIV /* 2274 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 2314 /* 2279 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2282 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2291 /* 2287 */ MCD_OPC_Decode, 182, 3, 34, // Opcode: SRL /* 2291 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2305 /* 2296 */ MCD_OPC_CheckPredicate, 8, 106, 6, 0, // Skip to: 3943 /* 2301 */ MCD_OPC_Decode, 185, 2, 34, // Opcode: DIVU /* 2305 */ MCD_OPC_FilterValue, 32, 97, 6, 0, // Skip to: 3943 /* 2310 */ MCD_OPC_Decode, 177, 3, 34, // Opcode: SRA /* 2314 */ MCD_OPC_FilterValue, 6, 26, 0, 0, // Skip to: 2345 /* 2319 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2322 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2331 /* 2327 */ MCD_OPC_Decode, 151, 3, 34, // Opcode: OR /* 2331 */ MCD_OPC_FilterValue, 1, 71, 6, 0, // Skip to: 3943 /* 2336 */ MCD_OPC_CheckPredicate, 8, 66, 6, 0, // Skip to: 3943 /* 2341 */ MCD_OPC_Decode, 153, 3, 34, // Opcode: REM /* 2345 */ MCD_OPC_FilterValue, 7, 57, 6, 0, // Skip to: 3943 /* 2350 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2353 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2362 /* 2358 */ MCD_OPC_Decode, 254, 1, 34, // Opcode: AND /* 2362 */ MCD_OPC_FilterValue, 1, 40, 6, 0, // Skip to: 3943 /* 2367 */ MCD_OPC_CheckPredicate, 8, 35, 6, 0, // Skip to: 3943 /* 2372 */ MCD_OPC_Decode, 154, 3, 34, // Opcode: REMU /* 2376 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 2385 /* 2381 */ MCD_OPC_Decode, 142, 3, 29, // Opcode: LUI /* 2385 */ MCD_OPC_FilterValue, 59, 187, 0, 0, // Skip to: 2577 /* 2390 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2393 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2443 /* 2398 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2401 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2415 /* 2406 */ MCD_OPC_CheckPredicate, 3, 252, 5, 0, // Skip to: 3943 /* 2411 */ MCD_OPC_Decode, 181, 1, 34, // Opcode: ADDW /* 2415 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2429 /* 2420 */ MCD_OPC_CheckPredicate, 9, 238, 5, 0, // Skip to: 3943 /* 2425 */ MCD_OPC_Decode, 150, 3, 34, // Opcode: MULW /* 2429 */ MCD_OPC_FilterValue, 32, 229, 5, 0, // Skip to: 3943 /* 2434 */ MCD_OPC_CheckPredicate, 3, 224, 5, 0, // Skip to: 3943 /* 2439 */ MCD_OPC_Decode, 187, 3, 34, // Opcode: SUBW /* 2443 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2464 /* 2448 */ MCD_OPC_CheckPredicate, 3, 210, 5, 0, // Skip to: 3943 /* 2453 */ MCD_OPC_CheckField, 25, 7, 0, 203, 5, 0, // Skip to: 3943 /* 2460 */ MCD_OPC_Decode, 172, 3, 34, // Opcode: SLLW /* 2464 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2485 /* 2469 */ MCD_OPC_CheckPredicate, 9, 189, 5, 0, // Skip to: 3943 /* 2474 */ MCD_OPC_CheckField, 25, 7, 1, 182, 5, 0, // Skip to: 3943 /* 2481 */ MCD_OPC_Decode, 187, 2, 34, // Opcode: DIVW /* 2485 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 2535 /* 2490 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2507 /* 2498 */ MCD_OPC_CheckPredicate, 3, 160, 5, 0, // Skip to: 3943 /* 2503 */ MCD_OPC_Decode, 185, 3, 34, // Opcode: SRLW /* 2507 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2521 /* 2512 */ MCD_OPC_CheckPredicate, 9, 146, 5, 0, // Skip to: 3943 /* 2517 */ MCD_OPC_Decode, 186, 2, 34, // Opcode: DIVUW /* 2521 */ MCD_OPC_FilterValue, 32, 137, 5, 0, // Skip to: 3943 /* 2526 */ MCD_OPC_CheckPredicate, 3, 132, 5, 0, // Skip to: 3943 /* 2531 */ MCD_OPC_Decode, 180, 3, 34, // Opcode: SRAW /* 2535 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2556 /* 2540 */ MCD_OPC_CheckPredicate, 9, 118, 5, 0, // Skip to: 3943 /* 2545 */ MCD_OPC_CheckField, 25, 7, 1, 111, 5, 0, // Skip to: 3943 /* 2552 */ MCD_OPC_Decode, 156, 3, 34, // Opcode: REMW /* 2556 */ MCD_OPC_FilterValue, 7, 102, 5, 0, // Skip to: 3943 /* 2561 */ MCD_OPC_CheckPredicate, 9, 97, 5, 0, // Skip to: 3943 /* 2566 */ MCD_OPC_CheckField, 25, 7, 1, 90, 5, 0, // Skip to: 3943 /* 2573 */ MCD_OPC_Decode, 155, 3, 34, // Opcode: REMUW /* 2577 */ MCD_OPC_FilterValue, 67, 31, 0, 0, // Skip to: 2613 /* 2582 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... /* 2585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2599 /* 2590 */ MCD_OPC_CheckPredicate, 4, 68, 5, 0, // Skip to: 3943 /* 2595 */ MCD_OPC_Decode, 226, 2, 36, // Opcode: FMADD_S /* 2599 */ MCD_OPC_FilterValue, 1, 59, 5, 0, // Skip to: 3943 /* 2604 */ MCD_OPC_CheckPredicate, 5, 54, 5, 0, // Skip to: 3943 /* 2609 */ MCD_OPC_Decode, 225, 2, 37, // Opcode: FMADD_D /* 2613 */ MCD_OPC_FilterValue, 71, 31, 0, 0, // Skip to: 2649 /* 2618 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... /* 2621 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2635 /* 2626 */ MCD_OPC_CheckPredicate, 4, 32, 5, 0, // Skip to: 3943 /* 2631 */ MCD_OPC_Decode, 232, 2, 36, // Opcode: FMSUB_S /* 2635 */ MCD_OPC_FilterValue, 1, 23, 5, 0, // Skip to: 3943 /* 2640 */ MCD_OPC_CheckPredicate, 5, 18, 5, 0, // Skip to: 3943 /* 2645 */ MCD_OPC_Decode, 231, 2, 37, // Opcode: FMSUB_D /* 2649 */ MCD_OPC_FilterValue, 75, 31, 0, 0, // Skip to: 2685 /* 2654 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... /* 2657 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2671 /* 2662 */ MCD_OPC_CheckPredicate, 4, 252, 4, 0, // Skip to: 3943 /* 2667 */ MCD_OPC_Decode, 242, 2, 36, // Opcode: FNMSUB_S /* 2671 */ MCD_OPC_FilterValue, 1, 243, 4, 0, // Skip to: 3943 /* 2676 */ MCD_OPC_CheckPredicate, 5, 238, 4, 0, // Skip to: 3943 /* 2681 */ MCD_OPC_Decode, 241, 2, 37, // Opcode: FNMSUB_D /* 2685 */ MCD_OPC_FilterValue, 79, 31, 0, 0, // Skip to: 2721 /* 2690 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... /* 2693 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2707 /* 2698 */ MCD_OPC_CheckPredicate, 4, 216, 4, 0, // Skip to: 3943 /* 2703 */ MCD_OPC_Decode, 240, 2, 36, // Opcode: FNMADD_S /* 2707 */ MCD_OPC_FilterValue, 1, 207, 4, 0, // Skip to: 3943 /* 2712 */ MCD_OPC_CheckPredicate, 5, 202, 4, 0, // Skip to: 3943 /* 2717 */ MCD_OPC_Decode, 239, 2, 37, // Opcode: FNMADD_D /* 2721 */ MCD_OPC_FilterValue, 83, 136, 3, 0, // Skip to: 3630 /* 2726 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 2729 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2743 /* 2734 */ MCD_OPC_CheckPredicate, 4, 180, 4, 0, // Skip to: 3943 /* 2739 */ MCD_OPC_Decode, 191, 2, 38, // Opcode: FADD_S /* 2743 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2757 /* 2748 */ MCD_OPC_CheckPredicate, 5, 166, 4, 0, // Skip to: 3943 /* 2753 */ MCD_OPC_Decode, 190, 2, 39, // Opcode: FADD_D /* 2757 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2771 /* 2762 */ MCD_OPC_CheckPredicate, 4, 152, 4, 0, // Skip to: 3943 /* 2767 */ MCD_OPC_Decode, 253, 2, 38, // Opcode: FSUB_S /* 2771 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2785 /* 2776 */ MCD_OPC_CheckPredicate, 5, 138, 4, 0, // Skip to: 3943 /* 2781 */ MCD_OPC_Decode, 252, 2, 39, // Opcode: FSUB_D /* 2785 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2799 /* 2790 */ MCD_OPC_CheckPredicate, 4, 124, 4, 0, // Skip to: 3943 /* 2795 */ MCD_OPC_Decode, 234, 2, 38, // Opcode: FMUL_S /* 2799 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2813 /* 2804 */ MCD_OPC_CheckPredicate, 5, 110, 4, 0, // Skip to: 3943 /* 2809 */ MCD_OPC_Decode, 233, 2, 39, // Opcode: FMUL_D /* 2813 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2827 /* 2818 */ MCD_OPC_CheckPredicate, 4, 96, 4, 0, // Skip to: 3943 /* 2823 */ MCD_OPC_Decode, 213, 2, 38, // Opcode: FDIV_S /* 2827 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2841 /* 2832 */ MCD_OPC_CheckPredicate, 5, 82, 4, 0, // Skip to: 3943 /* 2837 */ MCD_OPC_Decode, 212, 2, 39, // Opcode: FDIV_D /* 2841 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 2891 /* 2846 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2849 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2863 /* 2854 */ MCD_OPC_CheckPredicate, 4, 60, 4, 0, // Skip to: 3943 /* 2859 */ MCD_OPC_Decode, 249, 2, 40, // Opcode: FSGNJ_S /* 2863 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2877 /* 2868 */ MCD_OPC_CheckPredicate, 4, 46, 4, 0, // Skip to: 3943 /* 2873 */ MCD_OPC_Decode, 245, 2, 40, // Opcode: FSGNJN_S /* 2877 */ MCD_OPC_FilterValue, 2, 37, 4, 0, // Skip to: 3943 /* 2882 */ MCD_OPC_CheckPredicate, 4, 32, 4, 0, // Skip to: 3943 /* 2887 */ MCD_OPC_Decode, 247, 2, 40, // Opcode: FSGNJX_S /* 2891 */ MCD_OPC_FilterValue, 17, 45, 0, 0, // Skip to: 2941 /* 2896 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2899 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2913 /* 2904 */ MCD_OPC_CheckPredicate, 5, 10, 4, 0, // Skip to: 3943 /* 2909 */ MCD_OPC_Decode, 248, 2, 41, // Opcode: FSGNJ_D /* 2913 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2927 /* 2918 */ MCD_OPC_CheckPredicate, 5, 252, 3, 0, // Skip to: 3943 /* 2923 */ MCD_OPC_Decode, 244, 2, 41, // Opcode: FSGNJN_D /* 2927 */ MCD_OPC_FilterValue, 2, 243, 3, 0, // Skip to: 3943 /* 2932 */ MCD_OPC_CheckPredicate, 5, 238, 3, 0, // Skip to: 3943 /* 2937 */ MCD_OPC_Decode, 246, 2, 41, // Opcode: FSGNJX_D /* 2941 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2977 /* 2946 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2949 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2963 /* 2954 */ MCD_OPC_CheckPredicate, 4, 216, 3, 0, // Skip to: 3943 /* 2959 */ MCD_OPC_Decode, 230, 2, 40, // Opcode: FMIN_S /* 2963 */ MCD_OPC_FilterValue, 1, 207, 3, 0, // Skip to: 3943 /* 2968 */ MCD_OPC_CheckPredicate, 4, 202, 3, 0, // Skip to: 3943 /* 2973 */ MCD_OPC_Decode, 228, 2, 40, // Opcode: FMAX_S /* 2977 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3013 /* 2982 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 2985 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2999 /* 2990 */ MCD_OPC_CheckPredicate, 5, 180, 3, 0, // Skip to: 3943 /* 2995 */ MCD_OPC_Decode, 229, 2, 41, // Opcode: FMIN_D /* 2999 */ MCD_OPC_FilterValue, 1, 171, 3, 0, // Skip to: 3943 /* 3004 */ MCD_OPC_CheckPredicate, 5, 166, 3, 0, // Skip to: 3943 /* 3009 */ MCD_OPC_Decode, 227, 2, 41, // Opcode: FMAX_D /* 3013 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 3034 /* 3018 */ MCD_OPC_CheckPredicate, 5, 152, 3, 0, // Skip to: 3943 /* 3023 */ MCD_OPC_CheckField, 20, 5, 1, 145, 3, 0, // Skip to: 3943 /* 3030 */ MCD_OPC_Decode, 203, 2, 42, // Opcode: FCVT_S_D /* 3034 */ MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3062 /* 3039 */ MCD_OPC_CheckPredicate, 5, 131, 3, 0, // Skip to: 3943 /* 3044 */ MCD_OPC_CheckField, 20, 5, 0, 124, 3, 0, // Skip to: 3943 /* 3051 */ MCD_OPC_CheckField, 12, 3, 0, 117, 3, 0, // Skip to: 3943 /* 3058 */ MCD_OPC_Decode, 196, 2, 43, // Opcode: FCVT_D_S /* 3062 */ MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 3083 /* 3067 */ MCD_OPC_CheckPredicate, 4, 103, 3, 0, // Skip to: 3943 /* 3072 */ MCD_OPC_CheckField, 20, 5, 0, 96, 3, 0, // Skip to: 3943 /* 3079 */ MCD_OPC_Decode, 251, 2, 44, // Opcode: FSQRT_S /* 3083 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 3104 /* 3088 */ MCD_OPC_CheckPredicate, 5, 82, 3, 0, // Skip to: 3943 /* 3093 */ MCD_OPC_CheckField, 20, 5, 0, 75, 3, 0, // Skip to: 3943 /* 3100 */ MCD_OPC_Decode, 250, 2, 45, // Opcode: FSQRT_D /* 3104 */ MCD_OPC_FilterValue, 80, 45, 0, 0, // Skip to: 3154 /* 3109 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 3112 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3126 /* 3117 */ MCD_OPC_CheckPredicate, 4, 53, 3, 0, // Skip to: 3943 /* 3122 */ MCD_OPC_Decode, 221, 2, 46, // Opcode: FLE_S /* 3126 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3140 /* 3131 */ MCD_OPC_CheckPredicate, 4, 39, 3, 0, // Skip to: 3943 /* 3136 */ MCD_OPC_Decode, 223, 2, 46, // Opcode: FLT_S /* 3140 */ MCD_OPC_FilterValue, 2, 30, 3, 0, // Skip to: 3943 /* 3145 */ MCD_OPC_CheckPredicate, 4, 25, 3, 0, // Skip to: 3943 /* 3150 */ MCD_OPC_Decode, 218, 2, 46, // Opcode: FEQ_S /* 3154 */ MCD_OPC_FilterValue, 81, 45, 0, 0, // Skip to: 3204 /* 3159 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 3162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3176 /* 3167 */ MCD_OPC_CheckPredicate, 5, 3, 3, 0, // Skip to: 3943 /* 3172 */ MCD_OPC_Decode, 220, 2, 47, // Opcode: FLE_D /* 3176 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3190 /* 3181 */ MCD_OPC_CheckPredicate, 5, 245, 2, 0, // Skip to: 3943 /* 3186 */ MCD_OPC_Decode, 222, 2, 47, // Opcode: FLT_D /* 3190 */ MCD_OPC_FilterValue, 2, 236, 2, 0, // Skip to: 3943 /* 3195 */ MCD_OPC_CheckPredicate, 5, 231, 2, 0, // Skip to: 3943 /* 3200 */ MCD_OPC_Decode, 217, 2, 47, // Opcode: FEQ_D /* 3204 */ MCD_OPC_FilterValue, 96, 59, 0, 0, // Skip to: 3268 /* 3209 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... /* 3212 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3226 /* 3217 */ MCD_OPC_CheckPredicate, 4, 209, 2, 0, // Skip to: 3943 /* 3222 */ MCD_OPC_Decode, 211, 2, 48, // Opcode: FCVT_W_S /* 3226 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3240 /* 3231 */ MCD_OPC_CheckPredicate, 4, 195, 2, 0, // Skip to: 3943 /* 3236 */ MCD_OPC_Decode, 209, 2, 48, // Opcode: FCVT_WU_S /* 3240 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3254 /* 3245 */ MCD_OPC_CheckPredicate, 10, 181, 2, 0, // Skip to: 3943 /* 3250 */ MCD_OPC_Decode, 202, 2, 48, // Opcode: FCVT_L_S /* 3254 */ MCD_OPC_FilterValue, 3, 172, 2, 0, // Skip to: 3943 /* 3259 */ MCD_OPC_CheckPredicate, 10, 167, 2, 0, // Skip to: 3943 /* 3264 */ MCD_OPC_Decode, 200, 2, 48, // Opcode: FCVT_LU_S /* 3268 */ MCD_OPC_FilterValue, 97, 59, 0, 0, // Skip to: 3332 /* 3273 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... /* 3276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3290 /* 3281 */ MCD_OPC_CheckPredicate, 5, 145, 2, 0, // Skip to: 3943 /* 3286 */ MCD_OPC_Decode, 210, 2, 49, // Opcode: FCVT_W_D /* 3290 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3304 /* 3295 */ MCD_OPC_CheckPredicate, 5, 131, 2, 0, // Skip to: 3943 /* 3300 */ MCD_OPC_Decode, 208, 2, 49, // Opcode: FCVT_WU_D /* 3304 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3318 /* 3309 */ MCD_OPC_CheckPredicate, 11, 117, 2, 0, // Skip to: 3943 /* 3314 */ MCD_OPC_Decode, 201, 2, 49, // Opcode: FCVT_L_D /* 3318 */ MCD_OPC_FilterValue, 3, 108, 2, 0, // Skip to: 3943 /* 3323 */ MCD_OPC_CheckPredicate, 11, 103, 2, 0, // Skip to: 3943 /* 3328 */ MCD_OPC_Decode, 199, 2, 49, // Opcode: FCVT_LU_D /* 3332 */ MCD_OPC_FilterValue, 104, 59, 0, 0, // Skip to: 3396 /* 3337 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... /* 3340 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3354 /* 3345 */ MCD_OPC_CheckPredicate, 4, 81, 2, 0, // Skip to: 3943 /* 3350 */ MCD_OPC_Decode, 206, 2, 50, // Opcode: FCVT_S_W /* 3354 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3368 /* 3359 */ MCD_OPC_CheckPredicate, 4, 67, 2, 0, // Skip to: 3943 /* 3364 */ MCD_OPC_Decode, 207, 2, 50, // Opcode: FCVT_S_WU /* 3368 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3382 /* 3373 */ MCD_OPC_CheckPredicate, 10, 53, 2, 0, // Skip to: 3943 /* 3378 */ MCD_OPC_Decode, 204, 2, 50, // Opcode: FCVT_S_L /* 3382 */ MCD_OPC_FilterValue, 3, 44, 2, 0, // Skip to: 3943 /* 3387 */ MCD_OPC_CheckPredicate, 10, 39, 2, 0, // Skip to: 3943 /* 3392 */ MCD_OPC_Decode, 205, 2, 50, // Opcode: FCVT_S_LU /* 3396 */ MCD_OPC_FilterValue, 105, 73, 0, 0, // Skip to: 3474 /* 3401 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... /* 3404 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3425 /* 3409 */ MCD_OPC_CheckPredicate, 5, 17, 2, 0, // Skip to: 3943 /* 3414 */ MCD_OPC_CheckField, 12, 3, 0, 10, 2, 0, // Skip to: 3943 /* 3421 */ MCD_OPC_Decode, 197, 2, 51, // Opcode: FCVT_D_W /* 3425 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3446 /* 3430 */ MCD_OPC_CheckPredicate, 5, 252, 1, 0, // Skip to: 3943 /* 3435 */ MCD_OPC_CheckField, 12, 3, 0, 245, 1, 0, // Skip to: 3943 /* 3442 */ MCD_OPC_Decode, 198, 2, 51, // Opcode: FCVT_D_WU /* 3446 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3460 /* 3451 */ MCD_OPC_CheckPredicate, 11, 231, 1, 0, // Skip to: 3943 /* 3456 */ MCD_OPC_Decode, 194, 2, 52, // Opcode: FCVT_D_L /* 3460 */ MCD_OPC_FilterValue, 3, 222, 1, 0, // Skip to: 3943 /* 3465 */ MCD_OPC_CheckPredicate, 11, 217, 1, 0, // Skip to: 3943 /* 3470 */ MCD_OPC_Decode, 195, 2, 52, // Opcode: FCVT_D_LU /* 3474 */ MCD_OPC_FilterValue, 112, 45, 0, 0, // Skip to: 3524 /* 3479 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 3482 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3503 /* 3487 */ MCD_OPC_CheckPredicate, 4, 195, 1, 0, // Skip to: 3943 /* 3492 */ MCD_OPC_CheckField, 20, 5, 0, 188, 1, 0, // Skip to: 3943 /* 3499 */ MCD_OPC_Decode, 238, 2, 53, // Opcode: FMV_X_W /* 3503 */ MCD_OPC_FilterValue, 1, 179, 1, 0, // Skip to: 3943 /* 3508 */ MCD_OPC_CheckPredicate, 4, 174, 1, 0, // Skip to: 3943 /* 3513 */ MCD_OPC_CheckField, 20, 5, 0, 167, 1, 0, // Skip to: 3943 /* 3520 */ MCD_OPC_Decode, 193, 2, 53, // Opcode: FCLASS_S /* 3524 */ MCD_OPC_FilterValue, 113, 45, 0, 0, // Skip to: 3574 /* 3529 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 3532 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3553 /* 3537 */ MCD_OPC_CheckPredicate, 11, 145, 1, 0, // Skip to: 3943 /* 3542 */ MCD_OPC_CheckField, 20, 5, 0, 138, 1, 0, // Skip to: 3943 /* 3549 */ MCD_OPC_Decode, 237, 2, 54, // Opcode: FMV_X_D /* 3553 */ MCD_OPC_FilterValue, 1, 129, 1, 0, // Skip to: 3943 /* 3558 */ MCD_OPC_CheckPredicate, 5, 124, 1, 0, // Skip to: 3943 /* 3563 */ MCD_OPC_CheckField, 20, 5, 0, 117, 1, 0, // Skip to: 3943 /* 3570 */ MCD_OPC_Decode, 192, 2, 54, // Opcode: FCLASS_D /* 3574 */ MCD_OPC_FilterValue, 120, 23, 0, 0, // Skip to: 3602 /* 3579 */ MCD_OPC_CheckPredicate, 4, 103, 1, 0, // Skip to: 3943 /* 3584 */ MCD_OPC_CheckField, 20, 5, 0, 96, 1, 0, // Skip to: 3943 /* 3591 */ MCD_OPC_CheckField, 12, 3, 0, 89, 1, 0, // Skip to: 3943 /* 3598 */ MCD_OPC_Decode, 236, 2, 55, // Opcode: FMV_W_X /* 3602 */ MCD_OPC_FilterValue, 121, 80, 1, 0, // Skip to: 3943 /* 3607 */ MCD_OPC_CheckPredicate, 11, 75, 1, 0, // Skip to: 3943 /* 3612 */ MCD_OPC_CheckField, 20, 5, 0, 68, 1, 0, // Skip to: 3943 /* 3619 */ MCD_OPC_CheckField, 12, 3, 0, 61, 1, 0, // Skip to: 3943 /* 3626 */ MCD_OPC_Decode, 235, 2, 51, // Opcode: FMV_D_X /* 3630 */ MCD_OPC_FilterValue, 99, 57, 0, 0, // Skip to: 3692 /* 3635 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 3638 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3647 /* 3643 */ MCD_OPC_Decode, 129, 2, 56, // Opcode: BEQ /* 3647 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 3656 /* 3652 */ MCD_OPC_Decode, 134, 2, 56, // Opcode: BNE /* 3656 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 3665 /* 3661 */ MCD_OPC_Decode, 132, 2, 56, // Opcode: BLT /* 3665 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3674 /* 3670 */ MCD_OPC_Decode, 130, 2, 56, // Opcode: BGE /* 3674 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3683 /* 3679 */ MCD_OPC_Decode, 133, 2, 56, // Opcode: BLTU /* 3683 */ MCD_OPC_FilterValue, 7, 255, 0, 0, // Skip to: 3943 /* 3688 */ MCD_OPC_Decode, 131, 2, 56, // Opcode: BGEU /* 3692 */ MCD_OPC_FilterValue, 103, 11, 0, 0, // Skip to: 3708 /* 3697 */ MCD_OPC_CheckField, 12, 3, 0, 239, 0, 0, // Skip to: 3943 /* 3704 */ MCD_OPC_Decode, 128, 3, 24, // Opcode: JALR /* 3708 */ MCD_OPC_FilterValue, 111, 4, 0, 0, // Skip to: 3717 /* 3713 */ MCD_OPC_Decode, 255, 2, 57, // Opcode: JAL /* 3717 */ MCD_OPC_FilterValue, 115, 221, 0, 0, // Skip to: 3943 /* 3722 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... /* 3725 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 3869 /* 3730 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... /* 3733 */ MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 3789 /* 3738 */ MCD_OPC_ExtractField, 15, 10, // Inst{24-15} ... /* 3741 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3757 /* 3746 */ MCD_OPC_CheckField, 7, 5, 0, 190, 0, 0, // Skip to: 3943 /* 3753 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: ECALL /* 3757 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 3773 /* 3762 */ MCD_OPC_CheckField, 7, 5, 0, 174, 0, 0, // Skip to: 3943 /* 3769 */ MCD_OPC_Decode, 188, 2, 0, // Opcode: EBREAK /* 3773 */ MCD_OPC_FilterValue, 64, 165, 0, 0, // Skip to: 3943 /* 3778 */ MCD_OPC_CheckField, 7, 5, 0, 158, 0, 0, // Skip to: 3943 /* 3785 */ MCD_OPC_Decode, 190, 3, 0, // Opcode: URET /* 3789 */ MCD_OPC_FilterValue, 8, 36, 0, 0, // Skip to: 3830 /* 3794 */ MCD_OPC_ExtractField, 15, 10, // Inst{24-15} ... /* 3797 */ MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 3813 /* 3802 */ MCD_OPC_CheckField, 7, 5, 0, 134, 0, 0, // Skip to: 3943 /* 3809 */ MCD_OPC_Decode, 181, 3, 0, // Opcode: SRET /* 3813 */ MCD_OPC_FilterValue, 160, 1, 124, 0, 0, // Skip to: 3943 /* 3819 */ MCD_OPC_CheckField, 7, 5, 0, 117, 0, 0, // Skip to: 3943 /* 3826 */ MCD_OPC_Decode, 191, 3, 0, // Opcode: WFI /* 3830 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3846 /* 3835 */ MCD_OPC_CheckField, 7, 5, 0, 101, 0, 0, // Skip to: 3943 /* 3842 */ MCD_OPC_Decode, 167, 3, 58, // Opcode: SFENCE_VMA /* 3846 */ MCD_OPC_FilterValue, 24, 92, 0, 0, // Skip to: 3943 /* 3851 */ MCD_OPC_CheckField, 15, 10, 64, 85, 0, 0, // Skip to: 3943 /* 3858 */ MCD_OPC_CheckField, 7, 5, 0, 78, 0, 0, // Skip to: 3943 /* 3865 */ MCD_OPC_Decode, 145, 3, 0, // Opcode: MRET /* 3869 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3898 /* 3874 */ MCD_OPC_CheckField, 15, 17, 128, 128, 6, 11, 0, 0, // Skip to: 3894 /* 3883 */ MCD_OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 3894 /* 3890 */ MCD_OPC_Decode, 189, 3, 0, // Opcode: UNIMP /* 3894 */ MCD_OPC_Decode, 139, 2, 59, // Opcode: CSRRW /* 3898 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3907 /* 3903 */ MCD_OPC_Decode, 137, 2, 59, // Opcode: CSRRS /* 3907 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 3916 /* 3912 */ MCD_OPC_Decode, 135, 2, 59, // Opcode: CSRRC /* 3916 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3925 /* 3921 */ MCD_OPC_Decode, 140, 2, 60, // Opcode: CSRRWI /* 3925 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3934 /* 3930 */ MCD_OPC_Decode, 138, 2, 60, // Opcode: CSRRSI /* 3934 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 3943 /* 3939 */ MCD_OPC_Decode, 136, 2, 60, // Opcode: CSRRCI /* 3943 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTableRISCV32Only_16[] = { /* 0 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... /* 3 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39 /* 8 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 11 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25 /* 16 */ MCD_OPC_CheckPredicate, 12, 75, 0, 0, // Skip to: 96 /* 21 */ MCD_OPC_Decode, 154, 2, 61, // Opcode: C_FLW /* 25 */ MCD_OPC_FilterValue, 7, 66, 0, 0, // Skip to: 96 /* 30 */ MCD_OPC_CheckPredicate, 12, 61, 0, 0, // Skip to: 96 /* 35 */ MCD_OPC_Decode, 158, 2, 61, // Opcode: C_FSW /* 39 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 60 /* 44 */ MCD_OPC_CheckPredicate, 13, 47, 0, 0, // Skip to: 96 /* 49 */ MCD_OPC_CheckField, 13, 3, 1, 40, 0, 0, // Skip to: 96 /* 56 */ MCD_OPC_Decode, 161, 2, 19, // Opcode: C_JAL /* 60 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 96 /* 65 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... /* 68 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82 /* 73 */ MCD_OPC_CheckPredicate, 12, 18, 0, 0, // Skip to: 96 /* 78 */ MCD_OPC_Decode, 155, 2, 62, // Opcode: C_FLWSP /* 82 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 96 /* 87 */ MCD_OPC_CheckPredicate, 12, 4, 0, 0, // Skip to: 96 /* 92 */ MCD_OPC_Decode, 159, 2, 63, // Opcode: C_FSWSP /* 96 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { default: CS_ASSERT(0 && "Invalid index!"); case 0: return (Bits & RISCV_FeatureStdExtC); case 1: return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_FeatureStdExtD); case 2: return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_Feature64Bit); case 3: return (Bits & RISCV_Feature64Bit); case 4: return (Bits & RISCV_FeatureStdExtF); case 5: return (Bits & RISCV_FeatureStdExtD); case 6: return (Bits & RISCV_FeatureStdExtA); case 7: return (Bits & RISCV_FeatureStdExtA) && (Bits & RISCV_Feature64Bit); case 8: return (Bits & RISCV_FeatureStdExtM); case 9: return (Bits & RISCV_FeatureStdExtM) && (Bits & RISCV_Feature64Bit); case 10: return (Bits & RISCV_FeatureStdExtF) && (Bits & RISCV_Feature64Bit); case 11: return (Bits & RISCV_FeatureStdExtD) && (Bits & RISCV_Feature64Bit); case 12: return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_FeatureStdExtF) && !(Bits & RISCV_Feature64Bit); case 13: return (Bits & RISCV_FeatureStdExtC) && !(Bits & RISCV_Feature64Bit); } } #define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, const void *Decoder,\ bool *DecodeComplete) {\ *DecodeComplete = true;\ InsnType tmp; \ switch (Idx) { \ default: CS_ASSERT(0 && "Invalid index!");\ case 0: \ return S; \ case 1: \ tmp = fieldname(insn, 2, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 5, 1) << 3; \ tmp |= fieldname(insn, 6, 1) << 2; \ tmp |= fieldname(insn, 7, 4) << 6; \ tmp |= fieldname(insn, 11, 2) << 4; \ if (decodeUImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 2: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 5) << 0; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 3: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 5) << 0; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 4: \ tmp = fieldname(insn, 2, 3); \ if (DecodeFPR64CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 5, 2) << 6; \ tmp |= fieldname(insn, 10, 3) << 3; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 5: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 3) << 6; \ tmp |= fieldname(insn, 5, 2) << 3; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 6: \ tmp = fieldname(insn, 2, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 5, 1) << 6; \ tmp |= fieldname(insn, 6, 1) << 2; \ tmp |= fieldname(insn, 10, 3) << 3; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 7: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 5) << 0; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 8: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 2) << 6; \ tmp |= fieldname(insn, 4, 3) << 2; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 9: \ tmp = fieldname(insn, 2, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 5, 2) << 6; \ tmp |= fieldname(insn, 10, 3) << 3; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 10: \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 5; \ tmp |= fieldname(insn, 3, 2) << 7; \ tmp |= fieldname(insn, 5, 1) << 6; \ tmp |= fieldname(insn, 6, 1) << 4; \ tmp |= fieldname(insn, 12, 1) << 9; \ if (decodeSImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 11: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0X2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 5) << 0; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeCLUIImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 12: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 3) << 6; \ tmp |= fieldname(insn, 5, 2) << 3; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 13: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 5) << 0; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 14: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 5) << 0; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 15: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 2, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 16: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 17: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 2, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 18: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 2, 5); \ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 19: \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 4; \ tmp |= fieldname(insn, 3, 3) << 0; \ tmp |= fieldname(insn, 6, 1) << 6; \ tmp |= fieldname(insn, 7, 1) << 5; \ tmp |= fieldname(insn, 8, 1) << 9; \ tmp |= fieldname(insn, 9, 2) << 7; \ tmp |= fieldname(insn, 11, 1) << 3; \ tmp |= fieldname(insn, 12, 1) << 10; \ if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 20: \ tmp = fieldname(insn, 2, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 3) << 6; \ tmp |= fieldname(insn, 10, 3) << 3; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 21: \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 1) << 4; \ tmp |= fieldname(insn, 3, 2) << 0; \ tmp |= fieldname(insn, 5, 2) << 5; \ tmp |= fieldname(insn, 10, 2) << 2; \ tmp |= fieldname(insn, 12, 1) << 7; \ if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 22: \ tmp = fieldname(insn, 2, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 2) << 6; \ tmp |= fieldname(insn, 9, 4) << 2; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 23: \ tmp = fieldname(insn, 2, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 3) << 6; \ tmp |= fieldname(insn, 10, 3) << 3; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 24: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 25: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 26: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 27: \ tmp = fieldname(insn, 24, 4); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 28: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 6); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 29: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 20); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 20) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 30: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 31: \ tmp = fieldname(insn, 20, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 5) << 0; \ tmp |= fieldname(insn, 25, 7) << 5; \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 32: \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 5) << 0; \ tmp |= fieldname(insn, 25, 7) << 5; \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 33: \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 5) << 0; \ tmp |= fieldname(insn, 25, 7) << 5; \ if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 34: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 35: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 36: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 27, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 37: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 27, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 38: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 39: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 40: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 41: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 42: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 43: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 44: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 45: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 46: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 47: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 48: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 49: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 50: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 51: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 52: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 3); \ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 53: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 54: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 55: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 56: \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 10; \ tmp |= fieldname(insn, 8, 4) << 0; \ tmp |= fieldname(insn, 25, 6) << 4; \ tmp |= fieldname(insn, 31, 1) << 11; \ if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 13) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 57: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 12, 8) << 11; \ tmp |= fieldname(insn, 20, 1) << 10; \ tmp |= fieldname(insn, 21, 10) << 0; \ tmp |= fieldname(insn, 31, 1) << 19; \ if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 21) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 58: \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 59: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 60: \ tmp = fieldname(insn, 7, 5); \ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 15, 5); \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 61: \ tmp = fieldname(insn, 2, 3); \ if (DecodeFPR32CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 3); \ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 5, 1) << 6; \ tmp |= fieldname(insn, 6, 1) << 2; \ tmp |= fieldname(insn, 10, 3) << 3; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 62: \ tmp = fieldname(insn, 7, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 2, 2) << 6; \ tmp |= fieldname(insn, 4, 3) << 2; \ tmp |= fieldname(insn, 12, 1) << 5; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 63: \ tmp = fieldname(insn, 2, 5); \ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 2) << 6; \ tmp |= fieldname(insn, 9, 4) << 2; \ if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ InsnType insn, uint64_t Address,\ const void *DisAsm, int feature) {\ uint64_t Bits = getFeatureBits(feature);\ \ const uint8_t *Ptr = DecodeTable;\ uint32_t CurFieldValue = 0;\ DecodeStatus S = MCDisassembler_Success;\ while (true) {\ switch (*Ptr) {\ default:\ return MCDisassembler_Fail;\ case MCD_OPC_ExtractField: {\ unsigned Start = *++Ptr;\ unsigned Len = *++Ptr;\ ++Ptr;\ CurFieldValue = fieldname(insn, Start, Len);\ break;\ }\ case MCD_OPC_FilterValue: {\ unsigned Len;\ InsnType Val = decodeULEB128(++Ptr, &Len);\ Ptr += Len;\ unsigned NumToSkip = *Ptr++;\ NumToSkip |= (*Ptr++) << 8;\ NumToSkip |= (*Ptr++) << 16;\ \ if (Val != CurFieldValue)\ Ptr += NumToSkip;\ break;\ }\ case MCD_OPC_CheckField: {\ unsigned Start = *++Ptr;\ unsigned Len = *++Ptr;\ InsnType FieldValue = fieldname(insn, Start, Len);\ uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);\ Ptr += Len;\ unsigned NumToSkip = *Ptr++;\ NumToSkip |= (*Ptr++) << 8;\ NumToSkip |= (*Ptr++) << 16;\ \ if (ExpectedValue != FieldValue)\ Ptr += NumToSkip;\ break;\ }\ case MCD_OPC_CheckPredicate: {\ unsigned Len;\ unsigned PIdx = decodeULEB128(++Ptr, &Len);\ Ptr += Len;\ unsigned NumToSkip = *Ptr++;\ NumToSkip |= (*Ptr++) << 8;\ NumToSkip |= (*Ptr++) << 16;\ bool Pred;\ if (!(Pred = checkDecoderPredicate(PIdx, Bits)))\ Ptr += NumToSkip;\ (void)Pred;\ break;\ }\ case MCD_OPC_Decode: {\ unsigned Len;\ unsigned Opc = decodeULEB128(++Ptr, &Len);\ Ptr += Len;\ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\ Ptr += Len;\ \ MCInst_clear(MI);\ MCInst_setOpcode(MI, Opc);\ bool DecodeComplete;\ S = decoder(S, DecodeIdx, insn, MI, Address, DisAsm, &DecodeComplete);\ CS_ASSERT(DecodeComplete);\ \ return S;\ }\ case MCD_OPC_TryDecode: {\ unsigned Len;\ unsigned Opc = decodeULEB128(++Ptr, &Len);\ Ptr += Len;\ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\ Ptr += Len;\ unsigned NumToSkip = *Ptr++;\ NumToSkip |= (*Ptr++) << 8;\ NumToSkip |= (*Ptr++) << 16;\ \ MCInst TmpMI;\ MCInst_setOpcode(&TmpMI, Opc);\ bool DecodeComplete;\ S = decoder(S, DecodeIdx, insn, &TmpMI, Address, DisAsm, &DecodeComplete);\ \ if (DecodeComplete) {\ *MI = TmpMI;\ return S;\ } else {\ CS_ASSERT(S == MCDisassembler_Fail);\ Ptr += NumToSkip;\ S = MCDisassembler_Success;\ }\ break;\ }\ case MCD_OPC_SoftFail: {\ unsigned Len;\ InsnType PositiveMask = decodeULEB128(++Ptr, &Len);\ Ptr += Len;\ InsnType NegativeMask = decodeULEB128(Ptr, &Len);\ Ptr += Len;\ bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);\ if (Fail)\ S = MCDisassembler_SoftFail;\ break;\ }\ case MCD_OPC_Fail: {\ return MCDisassembler_Fail;\ }\ }\ }\ CS_ASSERT(0 && "bogosity detected in disassembler state machine!");\ } // For RISCV instruction is 32 bits. FieldFromInstruction(fieldFromInstruction, uint32_t) DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) capstone-sys-0.15.0/capstone/arch/RISCV/RISCVGenInsnNameMaps.inc000064400000000000000000000226260072674642500223030ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { RISCV_INS_ADD, "add" }, { RISCV_INS_ADDI, "addi" }, { RISCV_INS_ADDIW, "addiw" }, { RISCV_INS_ADDW, "addw" }, { RISCV_INS_AMOADD_D, "amoadd.d" }, { RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq" }, { RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl" }, { RISCV_INS_AMOADD_D_RL, "amoadd.d.rl" }, { RISCV_INS_AMOADD_W, "amoadd.w" }, { RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq" }, { RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl" }, { RISCV_INS_AMOADD_W_RL, "amoadd.w.rl" }, { RISCV_INS_AMOAND_D, "amoand.d" }, { RISCV_INS_AMOAND_D_AQ, "amoand.d.aq" }, { RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl" }, { RISCV_INS_AMOAND_D_RL, "amoand.d.rl" }, { RISCV_INS_AMOAND_W, "amoand.w" }, { RISCV_INS_AMOAND_W_AQ, "amoand.w.aq" }, { RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl" }, { RISCV_INS_AMOAND_W_RL, "amoand.w.rl" }, { RISCV_INS_AMOMAXU_D, "amomaxu.d" }, { RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq" }, { RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl" }, { RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl" }, { RISCV_INS_AMOMAXU_W, "amomaxu.w" }, { RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq" }, { RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl" }, { RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl" }, { RISCV_INS_AMOMAX_D, "amomax.d" }, { RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq" }, { RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl" }, { RISCV_INS_AMOMAX_D_RL, "amomax.d.rl" }, { RISCV_INS_AMOMAX_W, "amomax.w" }, { RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq" }, { RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl" }, { RISCV_INS_AMOMAX_W_RL, "amomax.w.rl" }, { RISCV_INS_AMOMINU_D, "amominu.d" }, { RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq" }, { RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl" }, { RISCV_INS_AMOMINU_D_RL, "amominu.d.rl" }, { RISCV_INS_AMOMINU_W, "amominu.w" }, { RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq" }, { RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl" }, { RISCV_INS_AMOMINU_W_RL, "amominu.w.rl" }, { RISCV_INS_AMOMIN_D, "amomin.d" }, { RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq" }, { RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl" }, { RISCV_INS_AMOMIN_D_RL, "amomin.d.rl" }, { RISCV_INS_AMOMIN_W, "amomin.w" }, { RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq" }, { RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl" }, { RISCV_INS_AMOMIN_W_RL, "amomin.w.rl" }, { RISCV_INS_AMOOR_D, "amoor.d" }, { RISCV_INS_AMOOR_D_AQ, "amoor.d.aq" }, { RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl" }, { RISCV_INS_AMOOR_D_RL, "amoor.d.rl" }, { RISCV_INS_AMOOR_W, "amoor.w" }, { RISCV_INS_AMOOR_W_AQ, "amoor.w.aq" }, { RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl" }, { RISCV_INS_AMOOR_W_RL, "amoor.w.rl" }, { RISCV_INS_AMOSWAP_D, "amoswap.d" }, { RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq" }, { RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl" }, { RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl" }, { RISCV_INS_AMOSWAP_W, "amoswap.w" }, { RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq" }, { RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl" }, { RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl" }, { RISCV_INS_AMOXOR_D, "amoxor.d" }, { RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq" }, { RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl" }, { RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl" }, { RISCV_INS_AMOXOR_W, "amoxor.w" }, { RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq" }, { RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl" }, { RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl" }, { RISCV_INS_AND, "and" }, { RISCV_INS_ANDI, "andi" }, { RISCV_INS_AUIPC, "auipc" }, { RISCV_INS_BEQ, "beq" }, { RISCV_INS_BGE, "bge" }, { RISCV_INS_BGEU, "bgeu" }, { RISCV_INS_BLT, "blt" }, { RISCV_INS_BLTU, "bltu" }, { RISCV_INS_BNE, "bne" }, { RISCV_INS_CSRRC, "csrrc" }, { RISCV_INS_CSRRCI, "csrrci" }, { RISCV_INS_CSRRS, "csrrs" }, { RISCV_INS_CSRRSI, "csrrsi" }, { RISCV_INS_CSRRW, "csrrw" }, { RISCV_INS_CSRRWI, "csrrwi" }, { RISCV_INS_C_ADD, "c.add" }, { RISCV_INS_C_ADDI, "c.addi" }, { RISCV_INS_C_ADDI16SP, "c.addi16sp" }, { RISCV_INS_C_ADDI4SPN, "c.addi4spn" }, { RISCV_INS_C_ADDIW, "c.addiw" }, { RISCV_INS_C_ADDW, "c.addw" }, { RISCV_INS_C_AND, "c.and" }, { RISCV_INS_C_ANDI, "c.andi" }, { RISCV_INS_C_BEQZ, "c.beqz" }, { RISCV_INS_C_BNEZ, "c.bnez" }, { RISCV_INS_C_EBREAK, "c.ebreak" }, { RISCV_INS_C_FLD, "c.fld" }, { RISCV_INS_C_FLDSP, "c.fldsp" }, { RISCV_INS_C_FLW, "c.flw" }, { RISCV_INS_C_FLWSP, "c.flwsp" }, { RISCV_INS_C_FSD, "c.fsd" }, { RISCV_INS_C_FSDSP, "c.fsdsp" }, { RISCV_INS_C_FSW, "c.fsw" }, { RISCV_INS_C_FSWSP, "c.fswsp" }, { RISCV_INS_C_J, "c.j" }, { RISCV_INS_C_JAL, "c.jal" }, { RISCV_INS_C_JALR, "c.jalr" }, { RISCV_INS_C_JR, "c.jr" }, { RISCV_INS_C_LD, "c.ld" }, { RISCV_INS_C_LDSP, "c.ldsp" }, { RISCV_INS_C_LI, "c.li" }, { RISCV_INS_C_LUI, "c.lui" }, { RISCV_INS_C_LW, "c.lw" }, { RISCV_INS_C_LWSP, "c.lwsp" }, { RISCV_INS_C_MV, "c.mv" }, { RISCV_INS_C_NOP, "c.nop" }, { RISCV_INS_C_OR, "c.or" }, { RISCV_INS_C_SD, "c.sd" }, { RISCV_INS_C_SDSP, "c.sdsp" }, { RISCV_INS_C_SLLI, "c.slli" }, { RISCV_INS_C_SRAI, "c.srai" }, { RISCV_INS_C_SRLI, "c.srli" }, { RISCV_INS_C_SUB, "c.sub" }, { RISCV_INS_C_SUBW, "c.subw" }, { RISCV_INS_C_SW, "c.sw" }, { RISCV_INS_C_SWSP, "c.swsp" }, { RISCV_INS_C_UNIMP, "c.unimp" }, { RISCV_INS_C_XOR, "c.xor" }, { RISCV_INS_DIV, "div" }, { RISCV_INS_DIVU, "divu" }, { RISCV_INS_DIVUW, "divuw" }, { RISCV_INS_DIVW, "divw" }, { RISCV_INS_EBREAK, "ebreak" }, { RISCV_INS_ECALL, "ecall" }, { RISCV_INS_FADD_D, "fadd.d" }, { RISCV_INS_FADD_S, "fadd.s" }, { RISCV_INS_FCLASS_D, "fclass.d" }, { RISCV_INS_FCLASS_S, "fclass.s" }, { RISCV_INS_FCVT_D_L, "fcvt.d.l" }, { RISCV_INS_FCVT_D_LU, "fcvt.d.lu" }, { RISCV_INS_FCVT_D_S, "fcvt.d.s" }, { RISCV_INS_FCVT_D_W, "fcvt.d.w" }, { RISCV_INS_FCVT_D_WU, "fcvt.d.wu" }, { RISCV_INS_FCVT_LU_D, "fcvt.lu.d" }, { RISCV_INS_FCVT_LU_S, "fcvt.lu.s" }, { RISCV_INS_FCVT_L_D, "fcvt.l.d" }, { RISCV_INS_FCVT_L_S, "fcvt.l.s" }, { RISCV_INS_FCVT_S_D, "fcvt.s.d" }, { RISCV_INS_FCVT_S_L, "fcvt.s.l" }, { RISCV_INS_FCVT_S_LU, "fcvt.s.lu" }, { RISCV_INS_FCVT_S_W, "fcvt.s.w" }, { RISCV_INS_FCVT_S_WU, "fcvt.s.wu" }, { RISCV_INS_FCVT_WU_D, "fcvt.wu.d" }, { RISCV_INS_FCVT_WU_S, "fcvt.wu.s" }, { RISCV_INS_FCVT_W_D, "fcvt.w.d" }, { RISCV_INS_FCVT_W_S, "fcvt.w.s" }, { RISCV_INS_FDIV_D, "fdiv.d" }, { RISCV_INS_FDIV_S, "fdiv.s" }, { RISCV_INS_FENCE, "fence" }, { RISCV_INS_FENCE_I, "fence.i" }, { RISCV_INS_FENCE_TSO, "fence.tso" }, { RISCV_INS_FEQ_D, "feq.d" }, { RISCV_INS_FEQ_S, "feq.s" }, { RISCV_INS_FLD, "fld" }, { RISCV_INS_FLE_D, "fle.d" }, { RISCV_INS_FLE_S, "fle.s" }, { RISCV_INS_FLT_D, "flt.d" }, { RISCV_INS_FLT_S, "flt.s" }, { RISCV_INS_FLW, "flw" }, { RISCV_INS_FMADD_D, "fmadd.d" }, { RISCV_INS_FMADD_S, "fmadd.s" }, { RISCV_INS_FMAX_D, "fmax.d" }, { RISCV_INS_FMAX_S, "fmax.s" }, { RISCV_INS_FMIN_D, "fmin.d" }, { RISCV_INS_FMIN_S, "fmin.s" }, { RISCV_INS_FMSUB_D, "fmsub.d" }, { RISCV_INS_FMSUB_S, "fmsub.s" }, { RISCV_INS_FMUL_D, "fmul.d" }, { RISCV_INS_FMUL_S, "fmul.s" }, { RISCV_INS_FMV_D_X, "fmv.d.x" }, { RISCV_INS_FMV_W_X, "fmv.w.x" }, { RISCV_INS_FMV_X_D, "fmv.x.d" }, { RISCV_INS_FMV_X_W, "fmv.x.w" }, { RISCV_INS_FNMADD_D, "fnmadd.d" }, { RISCV_INS_FNMADD_S, "fnmadd.s" }, { RISCV_INS_FNMSUB_D, "fnmsub.d" }, { RISCV_INS_FNMSUB_S, "fnmsub.s" }, { RISCV_INS_FSD, "fsd" }, { RISCV_INS_FSGNJN_D, "fsgnjn.d" }, { RISCV_INS_FSGNJN_S, "fsgnjn.s" }, { RISCV_INS_FSGNJX_D, "fsgnjx.d" }, { RISCV_INS_FSGNJX_S, "fsgnjx.s" }, { RISCV_INS_FSGNJ_D, "fsgnj.d" }, { RISCV_INS_FSGNJ_S, "fsgnj.s" }, { RISCV_INS_FSQRT_D, "fsqrt.d" }, { RISCV_INS_FSQRT_S, "fsqrt.s" }, { RISCV_INS_FSUB_D, "fsub.d" }, { RISCV_INS_FSUB_S, "fsub.s" }, { RISCV_INS_FSW, "fsw" }, { RISCV_INS_JAL, "jal" }, { RISCV_INS_JALR, "jalr" }, { RISCV_INS_LB, "lb" }, { RISCV_INS_LBU, "lbu" }, { RISCV_INS_LD, "ld" }, { RISCV_INS_LH, "lh" }, { RISCV_INS_LHU, "lhu" }, { RISCV_INS_LR_D, "lr.d" }, { RISCV_INS_LR_D_AQ, "lr.d.aq" }, { RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl" }, { RISCV_INS_LR_D_RL, "lr.d.rl" }, { RISCV_INS_LR_W, "lr.w" }, { RISCV_INS_LR_W_AQ, "lr.w.aq" }, { RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl" }, { RISCV_INS_LR_W_RL, "lr.w.rl" }, { RISCV_INS_LUI, "lui" }, { RISCV_INS_LW, "lw" }, { RISCV_INS_LWU, "lwu" }, { RISCV_INS_MRET, "mret" }, { RISCV_INS_MUL, "mul" }, { RISCV_INS_MULH, "mulh" }, { RISCV_INS_MULHSU, "mulhsu" }, { RISCV_INS_MULHU, "mulhu" }, { RISCV_INS_MULW, "mulw" }, { RISCV_INS_OR, "or" }, { RISCV_INS_ORI, "ori" }, { RISCV_INS_REM, "rem" }, { RISCV_INS_REMU, "remu" }, { RISCV_INS_REMUW, "remuw" }, { RISCV_INS_REMW, "remw" }, { RISCV_INS_SB, "sb" }, { RISCV_INS_SC_D, "sc.d" }, { RISCV_INS_SC_D_AQ, "sc.d.aq" }, { RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl" }, { RISCV_INS_SC_D_RL, "sc.d.rl" }, { RISCV_INS_SC_W, "sc.w" }, { RISCV_INS_SC_W_AQ, "sc.w.aq" }, { RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl" }, { RISCV_INS_SC_W_RL, "sc.w.rl" }, { RISCV_INS_SD, "sd" }, { RISCV_INS_SFENCE_VMA, "sfence.vma" }, { RISCV_INS_SH, "sh" }, { RISCV_INS_SLL, "sll" }, { RISCV_INS_SLLI, "slli" }, { RISCV_INS_SLLIW, "slliw" }, { RISCV_INS_SLLW, "sllw" }, { RISCV_INS_SLT, "slt" }, { RISCV_INS_SLTI, "slti" }, { RISCV_INS_SLTIU, "sltiu" }, { RISCV_INS_SLTU, "sltu" }, { RISCV_INS_SRA, "sra" }, { RISCV_INS_SRAI, "srai" }, { RISCV_INS_SRAIW, "sraiw" }, { RISCV_INS_SRAW, "sraw" }, { RISCV_INS_SRET, "sret" }, { RISCV_INS_SRL, "srl" }, { RISCV_INS_SRLI, "srli" }, { RISCV_INS_SRLIW, "srliw" }, { RISCV_INS_SRLW, "srlw" }, { RISCV_INS_SUB, "sub" }, { RISCV_INS_SUBW, "subw" }, { RISCV_INS_SW, "sw" }, { RISCV_INS_UNIMP, "unimp" }, { RISCV_INS_URET, "uret" }, { RISCV_INS_WFI, "wfi" }, { RISCV_INS_XOR, "xor" }, { RISCV_INS_XORI, "xori" }, capstone-sys-0.15.0/capstone/arch/RISCV/RISCVGenInstrInfo.inc000064400000000000000000000307560072674642500216700ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { RISCV_PHI = 0, RISCV_INLINEASM = 1, RISCV_INLINEASM_BR = 2, RISCV_CFI_INSTRUCTION = 3, RISCV_EH_LABEL = 4, RISCV_GC_LABEL = 5, RISCV_ANNOTATION_LABEL = 6, RISCV_KILL = 7, RISCV_EXTRACT_SUBREG = 8, RISCV_INSERT_SUBREG = 9, RISCV_IMPLICIT_DEF = 10, RISCV_SUBREG_TO_REG = 11, RISCV_COPY_TO_REGCLASS = 12, RISCV_DBG_VALUE = 13, RISCV_DBG_LABEL = 14, RISCV_REG_SEQUENCE = 15, RISCV_COPY = 16, RISCV_BUNDLE = 17, RISCV_LIFETIME_START = 18, RISCV_LIFETIME_END = 19, RISCV_STACKMAP = 20, RISCV_FENTRY_CALL = 21, RISCV_PATCHPOINT = 22, RISCV_LOAD_STACK_GUARD = 23, RISCV_STATEPOINT = 24, RISCV_LOCAL_ESCAPE = 25, RISCV_FAULTING_OP = 26, RISCV_PATCHABLE_OP = 27, RISCV_PATCHABLE_FUNCTION_ENTER = 28, RISCV_PATCHABLE_RET = 29, RISCV_PATCHABLE_FUNCTION_EXIT = 30, RISCV_PATCHABLE_TAIL_CALL = 31, RISCV_PATCHABLE_EVENT_CALL = 32, RISCV_PATCHABLE_TYPED_EVENT_CALL = 33, RISCV_ICALL_BRANCH_FUNNEL = 34, RISCV_G_ADD = 35, RISCV_G_SUB = 36, RISCV_G_MUL = 37, RISCV_G_SDIV = 38, RISCV_G_UDIV = 39, RISCV_G_SREM = 40, RISCV_G_UREM = 41, RISCV_G_AND = 42, RISCV_G_OR = 43, RISCV_G_XOR = 44, RISCV_G_IMPLICIT_DEF = 45, RISCV_G_PHI = 46, RISCV_G_FRAME_INDEX = 47, RISCV_G_GLOBAL_VALUE = 48, RISCV_G_EXTRACT = 49, RISCV_G_UNMERGE_VALUES = 50, RISCV_G_INSERT = 51, RISCV_G_MERGE_VALUES = 52, RISCV_G_BUILD_VECTOR = 53, RISCV_G_BUILD_VECTOR_TRUNC = 54, RISCV_G_CONCAT_VECTORS = 55, RISCV_G_PTRTOINT = 56, RISCV_G_INTTOPTR = 57, RISCV_G_BITCAST = 58, RISCV_G_INTRINSIC_TRUNC = 59, RISCV_G_INTRINSIC_ROUND = 60, RISCV_G_LOAD = 61, RISCV_G_SEXTLOAD = 62, RISCV_G_ZEXTLOAD = 63, RISCV_G_STORE = 64, RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65, RISCV_G_ATOMIC_CMPXCHG = 66, RISCV_G_ATOMICRMW_XCHG = 67, RISCV_G_ATOMICRMW_ADD = 68, RISCV_G_ATOMICRMW_SUB = 69, RISCV_G_ATOMICRMW_AND = 70, RISCV_G_ATOMICRMW_NAND = 71, RISCV_G_ATOMICRMW_OR = 72, RISCV_G_ATOMICRMW_XOR = 73, RISCV_G_ATOMICRMW_MAX = 74, RISCV_G_ATOMICRMW_MIN = 75, RISCV_G_ATOMICRMW_UMAX = 76, RISCV_G_ATOMICRMW_UMIN = 77, RISCV_G_BRCOND = 78, RISCV_G_BRINDIRECT = 79, RISCV_G_INTRINSIC = 80, RISCV_G_INTRINSIC_W_SIDE_EFFECTS = 81, RISCV_G_ANYEXT = 82, RISCV_G_TRUNC = 83, RISCV_G_CONSTANT = 84, RISCV_G_FCONSTANT = 85, RISCV_G_VASTART = 86, RISCV_G_VAARG = 87, RISCV_G_SEXT = 88, RISCV_G_ZEXT = 89, RISCV_G_SHL = 90, RISCV_G_LSHR = 91, RISCV_G_ASHR = 92, RISCV_G_ICMP = 93, RISCV_G_FCMP = 94, RISCV_G_SELECT = 95, RISCV_G_UADDO = 96, RISCV_G_UADDE = 97, RISCV_G_USUBO = 98, RISCV_G_USUBE = 99, RISCV_G_SADDO = 100, RISCV_G_SADDE = 101, RISCV_G_SSUBO = 102, RISCV_G_SSUBE = 103, RISCV_G_UMULO = 104, RISCV_G_SMULO = 105, RISCV_G_UMULH = 106, RISCV_G_SMULH = 107, RISCV_G_FADD = 108, RISCV_G_FSUB = 109, RISCV_G_FMUL = 110, RISCV_G_FMA = 111, RISCV_G_FDIV = 112, RISCV_G_FREM = 113, RISCV_G_FPOW = 114, RISCV_G_FEXP = 115, RISCV_G_FEXP2 = 116, RISCV_G_FLOG = 117, RISCV_G_FLOG2 = 118, RISCV_G_FLOG10 = 119, RISCV_G_FNEG = 120, RISCV_G_FPEXT = 121, RISCV_G_FPTRUNC = 122, RISCV_G_FPTOSI = 123, RISCV_G_FPTOUI = 124, RISCV_G_SITOFP = 125, RISCV_G_UITOFP = 126, RISCV_G_FABS = 127, RISCV_G_FCANONICALIZE = 128, RISCV_G_GEP = 129, RISCV_G_PTR_MASK = 130, RISCV_G_BR = 131, RISCV_G_INSERT_VECTOR_ELT = 132, RISCV_G_EXTRACT_VECTOR_ELT = 133, RISCV_G_SHUFFLE_VECTOR = 134, RISCV_G_CTTZ = 135, RISCV_G_CTTZ_ZERO_UNDEF = 136, RISCV_G_CTLZ = 137, RISCV_G_CTLZ_ZERO_UNDEF = 138, RISCV_G_CTPOP = 139, RISCV_G_BSWAP = 140, RISCV_G_FCEIL = 141, RISCV_G_FCOS = 142, RISCV_G_FSIN = 143, RISCV_G_FSQRT = 144, RISCV_G_FFLOOR = 145, RISCV_G_ADDRSPACE_CAST = 146, RISCV_G_BLOCK_ADDR = 147, RISCV_ADJCALLSTACKDOWN = 148, RISCV_ADJCALLSTACKUP = 149, RISCV_BuildPairF64Pseudo = 150, RISCV_PseudoAtomicLoadNand32 = 151, RISCV_PseudoAtomicLoadNand64 = 152, RISCV_PseudoBR = 153, RISCV_PseudoBRIND = 154, RISCV_PseudoCALL = 155, RISCV_PseudoCALLIndirect = 156, RISCV_PseudoCmpXchg32 = 157, RISCV_PseudoCmpXchg64 = 158, RISCV_PseudoLA = 159, RISCV_PseudoLI = 160, RISCV_PseudoLLA = 161, RISCV_PseudoMaskedAtomicLoadAdd32 = 162, RISCV_PseudoMaskedAtomicLoadMax32 = 163, RISCV_PseudoMaskedAtomicLoadMin32 = 164, RISCV_PseudoMaskedAtomicLoadNand32 = 165, RISCV_PseudoMaskedAtomicLoadSub32 = 166, RISCV_PseudoMaskedAtomicLoadUMax32 = 167, RISCV_PseudoMaskedAtomicLoadUMin32 = 168, RISCV_PseudoMaskedAtomicSwap32 = 169, RISCV_PseudoMaskedCmpXchg32 = 170, RISCV_PseudoRET = 171, RISCV_PseudoTAIL = 172, RISCV_PseudoTAILIndirect = 173, RISCV_Select_FPR32_Using_CC_GPR = 174, RISCV_Select_FPR64_Using_CC_GPR = 175, RISCV_Select_GPR_Using_CC_GPR = 176, RISCV_SplitF64Pseudo = 177, RISCV_ADD = 178, RISCV_ADDI = 179, RISCV_ADDIW = 180, RISCV_ADDW = 181, RISCV_AMOADD_D = 182, RISCV_AMOADD_D_AQ = 183, RISCV_AMOADD_D_AQ_RL = 184, RISCV_AMOADD_D_RL = 185, RISCV_AMOADD_W = 186, RISCV_AMOADD_W_AQ = 187, RISCV_AMOADD_W_AQ_RL = 188, RISCV_AMOADD_W_RL = 189, RISCV_AMOAND_D = 190, RISCV_AMOAND_D_AQ = 191, RISCV_AMOAND_D_AQ_RL = 192, RISCV_AMOAND_D_RL = 193, RISCV_AMOAND_W = 194, RISCV_AMOAND_W_AQ = 195, RISCV_AMOAND_W_AQ_RL = 196, RISCV_AMOAND_W_RL = 197, RISCV_AMOMAXU_D = 198, RISCV_AMOMAXU_D_AQ = 199, RISCV_AMOMAXU_D_AQ_RL = 200, RISCV_AMOMAXU_D_RL = 201, RISCV_AMOMAXU_W = 202, RISCV_AMOMAXU_W_AQ = 203, RISCV_AMOMAXU_W_AQ_RL = 204, RISCV_AMOMAXU_W_RL = 205, RISCV_AMOMAX_D = 206, RISCV_AMOMAX_D_AQ = 207, RISCV_AMOMAX_D_AQ_RL = 208, RISCV_AMOMAX_D_RL = 209, RISCV_AMOMAX_W = 210, RISCV_AMOMAX_W_AQ = 211, RISCV_AMOMAX_W_AQ_RL = 212, RISCV_AMOMAX_W_RL = 213, RISCV_AMOMINU_D = 214, RISCV_AMOMINU_D_AQ = 215, RISCV_AMOMINU_D_AQ_RL = 216, RISCV_AMOMINU_D_RL = 217, RISCV_AMOMINU_W = 218, RISCV_AMOMINU_W_AQ = 219, RISCV_AMOMINU_W_AQ_RL = 220, RISCV_AMOMINU_W_RL = 221, RISCV_AMOMIN_D = 222, RISCV_AMOMIN_D_AQ = 223, RISCV_AMOMIN_D_AQ_RL = 224, RISCV_AMOMIN_D_RL = 225, RISCV_AMOMIN_W = 226, RISCV_AMOMIN_W_AQ = 227, RISCV_AMOMIN_W_AQ_RL = 228, RISCV_AMOMIN_W_RL = 229, RISCV_AMOOR_D = 230, RISCV_AMOOR_D_AQ = 231, RISCV_AMOOR_D_AQ_RL = 232, RISCV_AMOOR_D_RL = 233, RISCV_AMOOR_W = 234, RISCV_AMOOR_W_AQ = 235, RISCV_AMOOR_W_AQ_RL = 236, RISCV_AMOOR_W_RL = 237, RISCV_AMOSWAP_D = 238, RISCV_AMOSWAP_D_AQ = 239, RISCV_AMOSWAP_D_AQ_RL = 240, RISCV_AMOSWAP_D_RL = 241, RISCV_AMOSWAP_W = 242, RISCV_AMOSWAP_W_AQ = 243, RISCV_AMOSWAP_W_AQ_RL = 244, RISCV_AMOSWAP_W_RL = 245, RISCV_AMOXOR_D = 246, RISCV_AMOXOR_D_AQ = 247, RISCV_AMOXOR_D_AQ_RL = 248, RISCV_AMOXOR_D_RL = 249, RISCV_AMOXOR_W = 250, RISCV_AMOXOR_W_AQ = 251, RISCV_AMOXOR_W_AQ_RL = 252, RISCV_AMOXOR_W_RL = 253, RISCV_AND = 254, RISCV_ANDI = 255, RISCV_AUIPC = 256, RISCV_BEQ = 257, RISCV_BGE = 258, RISCV_BGEU = 259, RISCV_BLT = 260, RISCV_BLTU = 261, RISCV_BNE = 262, RISCV_CSRRC = 263, RISCV_CSRRCI = 264, RISCV_CSRRS = 265, RISCV_CSRRSI = 266, RISCV_CSRRW = 267, RISCV_CSRRWI = 268, RISCV_C_ADD = 269, RISCV_C_ADDI = 270, RISCV_C_ADDI16SP = 271, RISCV_C_ADDI4SPN = 272, RISCV_C_ADDIW = 273, RISCV_C_ADDW = 274, RISCV_C_AND = 275, RISCV_C_ANDI = 276, RISCV_C_BEQZ = 277, RISCV_C_BNEZ = 278, RISCV_C_EBREAK = 279, RISCV_C_FLD = 280, RISCV_C_FLDSP = 281, RISCV_C_FLW = 282, RISCV_C_FLWSP = 283, RISCV_C_FSD = 284, RISCV_C_FSDSP = 285, RISCV_C_FSW = 286, RISCV_C_FSWSP = 287, RISCV_C_J = 288, RISCV_C_JAL = 289, RISCV_C_JALR = 290, RISCV_C_JR = 291, RISCV_C_LD = 292, RISCV_C_LDSP = 293, RISCV_C_LI = 294, RISCV_C_LUI = 295, RISCV_C_LW = 296, RISCV_C_LWSP = 297, RISCV_C_MV = 298, RISCV_C_NOP = 299, RISCV_C_OR = 300, RISCV_C_SD = 301, RISCV_C_SDSP = 302, RISCV_C_SLLI = 303, RISCV_C_SRAI = 304, RISCV_C_SRLI = 305, RISCV_C_SUB = 306, RISCV_C_SUBW = 307, RISCV_C_SW = 308, RISCV_C_SWSP = 309, RISCV_C_UNIMP = 310, RISCV_C_XOR = 311, RISCV_DIV = 312, RISCV_DIVU = 313, RISCV_DIVUW = 314, RISCV_DIVW = 315, RISCV_EBREAK = 316, RISCV_ECALL = 317, RISCV_FADD_D = 318, RISCV_FADD_S = 319, RISCV_FCLASS_D = 320, RISCV_FCLASS_S = 321, RISCV_FCVT_D_L = 322, RISCV_FCVT_D_LU = 323, RISCV_FCVT_D_S = 324, RISCV_FCVT_D_W = 325, RISCV_FCVT_D_WU = 326, RISCV_FCVT_LU_D = 327, RISCV_FCVT_LU_S = 328, RISCV_FCVT_L_D = 329, RISCV_FCVT_L_S = 330, RISCV_FCVT_S_D = 331, RISCV_FCVT_S_L = 332, RISCV_FCVT_S_LU = 333, RISCV_FCVT_S_W = 334, RISCV_FCVT_S_WU = 335, RISCV_FCVT_WU_D = 336, RISCV_FCVT_WU_S = 337, RISCV_FCVT_W_D = 338, RISCV_FCVT_W_S = 339, RISCV_FDIV_D = 340, RISCV_FDIV_S = 341, RISCV_FENCE = 342, RISCV_FENCE_I = 343, RISCV_FENCE_TSO = 344, RISCV_FEQ_D = 345, RISCV_FEQ_S = 346, RISCV_FLD = 347, RISCV_FLE_D = 348, RISCV_FLE_S = 349, RISCV_FLT_D = 350, RISCV_FLT_S = 351, RISCV_FLW = 352, RISCV_FMADD_D = 353, RISCV_FMADD_S = 354, RISCV_FMAX_D = 355, RISCV_FMAX_S = 356, RISCV_FMIN_D = 357, RISCV_FMIN_S = 358, RISCV_FMSUB_D = 359, RISCV_FMSUB_S = 360, RISCV_FMUL_D = 361, RISCV_FMUL_S = 362, RISCV_FMV_D_X = 363, RISCV_FMV_W_X = 364, RISCV_FMV_X_D = 365, RISCV_FMV_X_W = 366, RISCV_FNMADD_D = 367, RISCV_FNMADD_S = 368, RISCV_FNMSUB_D = 369, RISCV_FNMSUB_S = 370, RISCV_FSD = 371, RISCV_FSGNJN_D = 372, RISCV_FSGNJN_S = 373, RISCV_FSGNJX_D = 374, RISCV_FSGNJX_S = 375, RISCV_FSGNJ_D = 376, RISCV_FSGNJ_S = 377, RISCV_FSQRT_D = 378, RISCV_FSQRT_S = 379, RISCV_FSUB_D = 380, RISCV_FSUB_S = 381, RISCV_FSW = 382, RISCV_JAL = 383, RISCV_JALR = 384, RISCV_LB = 385, RISCV_LBU = 386, RISCV_LD = 387, RISCV_LH = 388, RISCV_LHU = 389, RISCV_LR_D = 390, RISCV_LR_D_AQ = 391, RISCV_LR_D_AQ_RL = 392, RISCV_LR_D_RL = 393, RISCV_LR_W = 394, RISCV_LR_W_AQ = 395, RISCV_LR_W_AQ_RL = 396, RISCV_LR_W_RL = 397, RISCV_LUI = 398, RISCV_LW = 399, RISCV_LWU = 400, RISCV_MRET = 401, RISCV_MUL = 402, RISCV_MULH = 403, RISCV_MULHSU = 404, RISCV_MULHU = 405, RISCV_MULW = 406, RISCV_OR = 407, RISCV_ORI = 408, RISCV_REM = 409, RISCV_REMU = 410, RISCV_REMUW = 411, RISCV_REMW = 412, RISCV_SB = 413, RISCV_SC_D = 414, RISCV_SC_D_AQ = 415, RISCV_SC_D_AQ_RL = 416, RISCV_SC_D_RL = 417, RISCV_SC_W = 418, RISCV_SC_W_AQ = 419, RISCV_SC_W_AQ_RL = 420, RISCV_SC_W_RL = 421, RISCV_SD = 422, RISCV_SFENCE_VMA = 423, RISCV_SH = 424, RISCV_SLL = 425, RISCV_SLLI = 426, RISCV_SLLIW = 427, RISCV_SLLW = 428, RISCV_SLT = 429, RISCV_SLTI = 430, RISCV_SLTIU = 431, RISCV_SLTU = 432, RISCV_SRA = 433, RISCV_SRAI = 434, RISCV_SRAIW = 435, RISCV_SRAW = 436, RISCV_SRET = 437, RISCV_SRL = 438, RISCV_SRLI = 439, RISCV_SRLIW = 440, RISCV_SRLW = 441, RISCV_SUB = 442, RISCV_SUBW = 443, RISCV_SW = 444, RISCV_UNIMP = 445, RISCV_URET = 446, RISCV_WFI = 447, RISCV_XOR = 448, RISCV_XORI = 449, RISCV_INSTRUCTION_LIST_END = 450 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/RISCV/RISCVGenRegisterInfo.inc000064400000000000000000000303760072674642500223530ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { RISCV_NoRegister, RISCV_X0 = 1, RISCV_X1 = 2, RISCV_X2 = 3, RISCV_X3 = 4, RISCV_X4 = 5, RISCV_X5 = 6, RISCV_X6 = 7, RISCV_X7 = 8, RISCV_X8 = 9, RISCV_X9 = 10, RISCV_X10 = 11, RISCV_X11 = 12, RISCV_X12 = 13, RISCV_X13 = 14, RISCV_X14 = 15, RISCV_X15 = 16, RISCV_X16 = 17, RISCV_X17 = 18, RISCV_X18 = 19, RISCV_X19 = 20, RISCV_X20 = 21, RISCV_X21 = 22, RISCV_X22 = 23, RISCV_X23 = 24, RISCV_X24 = 25, RISCV_X25 = 26, RISCV_X26 = 27, RISCV_X27 = 28, RISCV_X28 = 29, RISCV_X29 = 30, RISCV_X30 = 31, RISCV_X31 = 32, RISCV_F0_32 = 33, RISCV_F0_64 = 34, RISCV_F1_32 = 35, RISCV_F1_64 = 36, RISCV_F2_32 = 37, RISCV_F2_64 = 38, RISCV_F3_32 = 39, RISCV_F3_64 = 40, RISCV_F4_32 = 41, RISCV_F4_64 = 42, RISCV_F5_32 = 43, RISCV_F5_64 = 44, RISCV_F6_32 = 45, RISCV_F6_64 = 46, RISCV_F7_32 = 47, RISCV_F7_64 = 48, RISCV_F8_32 = 49, RISCV_F8_64 = 50, RISCV_F9_32 = 51, RISCV_F9_64 = 52, RISCV_F10_32 = 53, RISCV_F10_64 = 54, RISCV_F11_32 = 55, RISCV_F11_64 = 56, RISCV_F12_32 = 57, RISCV_F12_64 = 58, RISCV_F13_32 = 59, RISCV_F13_64 = 60, RISCV_F14_32 = 61, RISCV_F14_64 = 62, RISCV_F15_32 = 63, RISCV_F15_64 = 64, RISCV_F16_32 = 65, RISCV_F16_64 = 66, RISCV_F17_32 = 67, RISCV_F17_64 = 68, RISCV_F18_32 = 69, RISCV_F18_64 = 70, RISCV_F19_32 = 71, RISCV_F19_64 = 72, RISCV_F20_32 = 73, RISCV_F20_64 = 74, RISCV_F21_32 = 75, RISCV_F21_64 = 76, RISCV_F22_32 = 77, RISCV_F22_64 = 78, RISCV_F23_32 = 79, RISCV_F23_64 = 80, RISCV_F24_32 = 81, RISCV_F24_64 = 82, RISCV_F25_32 = 83, RISCV_F25_64 = 84, RISCV_F26_32 = 85, RISCV_F26_64 = 86, RISCV_F27_32 = 87, RISCV_F27_64 = 88, RISCV_F28_32 = 89, RISCV_F28_64 = 90, RISCV_F29_32 = 91, RISCV_F29_64 = 92, RISCV_F30_32 = 93, RISCV_F30_64 = 94, RISCV_F31_32 = 95, RISCV_F31_64 = 96, RISCV_NUM_TARGET_REGS // 97 }; // Register classes enum { RISCV_FPR32RegClassID = 0, RISCV_GPRRegClassID = 1, RISCV_GPRNoX0RegClassID = 2, RISCV_GPRNoX0X2RegClassID = 3, RISCV_GPRTCRegClassID = 4, RISCV_FPR32CRegClassID = 5, RISCV_GPRCRegClassID = 6, RISCV_GPRC_and_GPRTCRegClassID = 7, RISCV_SPRegClassID = 8, RISCV_FPR64RegClassID = 9, RISCV_FPR64CRegClassID = 10, }; // Register alternate name indices enum { RISCV_ABIRegAltName, // 0 RISCV_NoRegAltName, // 1 RISCV_NUM_TARGET_REG_ALT_NAMES = 2 }; // Subregister indices enum { RISCV_NoSubRegister, RISCV_sub_32, // 1 RISCV_NUM_TARGET_SUBREGS }; #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg RISCVRegDiffLists[] = { /* 0 */ 1, 0, /* 2 */ 32, 0, /* 4 */ 33, 0, /* 6 */ 34, 0, /* 8 */ 35, 0, /* 10 */ 36, 0, /* 12 */ 37, 0, /* 14 */ 38, 0, /* 16 */ 39, 0, /* 18 */ 40, 0, /* 20 */ 41, 0, /* 22 */ 42, 0, /* 24 */ 43, 0, /* 26 */ 44, 0, /* 28 */ 45, 0, /* 30 */ 46, 0, /* 32 */ 47, 0, /* 34 */ 48, 0, /* 36 */ 49, 0, /* 38 */ 50, 0, /* 40 */ 51, 0, /* 42 */ 52, 0, /* 44 */ 53, 0, /* 46 */ 54, 0, /* 48 */ 55, 0, /* 50 */ 56, 0, /* 52 */ 57, 0, /* 54 */ 58, 0, /* 56 */ 59, 0, /* 58 */ 60, 0, /* 60 */ 61, 0, /* 62 */ 62, 0, /* 64 */ 63, 0, /* 66 */ 65535, 0, }; static const uint16_t RISCVSubRegIdxLists[] = { /* 0 */ 1, 0, }; static const MCRegisterDesc RISCVRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, { 12, 1, 1, 1, 1057, 0 }, { 27, 1, 1, 1, 1057, 0 }, { 252, 1, 1, 1, 1057, 0 }, { 263, 1, 1, 1, 1057, 0 }, { 488, 1, 1, 1, 1057, 0 }, { 499, 1, 1, 1, 1057, 0 }, { 510, 1, 1, 1, 1057, 0 }, { 521, 1, 1, 1, 1057, 0 }, { 532, 1, 1, 1, 1057, 0 }, { 543, 1, 1, 1, 1057, 0 }, { 0, 1, 1, 1, 1057, 0 }, { 15, 1, 1, 1, 1057, 0 }, { 30, 1, 1, 1, 1057, 0 }, { 255, 1, 1, 1, 1057, 0 }, { 266, 1, 1, 1, 1057, 0 }, { 491, 1, 1, 1, 1057, 0 }, { 502, 1, 1, 1, 1057, 0 }, { 513, 1, 1, 1, 1057, 0 }, { 524, 1, 1, 1, 1057, 0 }, { 535, 1, 1, 1, 1057, 0 }, { 4, 1, 1, 1, 1057, 0 }, { 19, 1, 1, 1, 1057, 0 }, { 34, 1, 1, 1, 1057, 0 }, { 259, 1, 1, 1, 1057, 0 }, { 270, 1, 1, 1, 1057, 0 }, { 495, 1, 1, 1, 1057, 0 }, { 506, 1, 1, 1, 1057, 0 }, { 517, 1, 1, 1, 1057, 0 }, { 528, 1, 1, 1, 1057, 0 }, { 539, 1, 1, 1, 1057, 0 }, { 8, 1, 1, 1, 1057, 0 }, { 23, 1, 1, 1, 1057, 0 }, { 59, 1, 0, 1, 32, 0 }, { 295, 66, 1, 0, 32, 2 }, { 86, 1, 0, 1, 64, 0 }, { 322, 66, 1, 0, 64, 2 }, { 106, 1, 0, 1, 96, 0 }, { 342, 66, 1, 0, 96, 2 }, { 126, 1, 0, 1, 128, 0 }, { 362, 66, 1, 0, 128, 2 }, { 146, 1, 0, 1, 160, 0 }, { 382, 66, 1, 0, 160, 2 }, { 166, 1, 0, 1, 192, 0 }, { 402, 66, 1, 0, 192, 2 }, { 186, 1, 0, 1, 224, 0 }, { 422, 66, 1, 0, 224, 2 }, { 206, 1, 0, 1, 256, 0 }, { 442, 66, 1, 0, 256, 2 }, { 226, 1, 0, 1, 288, 0 }, { 462, 66, 1, 0, 288, 2 }, { 246, 1, 0, 1, 320, 0 }, { 482, 66, 1, 0, 320, 2 }, { 38, 1, 0, 1, 352, 0 }, { 274, 66, 1, 0, 352, 2 }, { 65, 1, 0, 1, 384, 0 }, { 301, 66, 1, 0, 384, 2 }, { 92, 1, 0, 1, 416, 0 }, { 328, 66, 1, 0, 416, 2 }, { 112, 1, 0, 1, 448, 0 }, { 348, 66, 1, 0, 448, 2 }, { 132, 1, 0, 1, 480, 0 }, { 368, 66, 1, 0, 480, 2 }, { 152, 1, 0, 1, 512, 0 }, { 388, 66, 1, 0, 512, 2 }, { 172, 1, 0, 1, 544, 0 }, { 408, 66, 1, 0, 544, 2 }, { 192, 1, 0, 1, 576, 0 }, { 428, 66, 1, 0, 576, 2 }, { 212, 1, 0, 1, 608, 0 }, { 448, 66, 1, 0, 608, 2 }, { 232, 1, 0, 1, 640, 0 }, { 468, 66, 1, 0, 640, 2 }, { 45, 1, 0, 1, 672, 0 }, { 281, 66, 1, 0, 672, 2 }, { 72, 1, 0, 1, 704, 0 }, { 308, 66, 1, 0, 704, 2 }, { 99, 1, 0, 1, 736, 0 }, { 335, 66, 1, 0, 736, 2 }, { 119, 1, 0, 1, 768, 0 }, { 355, 66, 1, 0, 768, 2 }, { 139, 1, 0, 1, 800, 0 }, { 375, 66, 1, 0, 800, 2 }, { 159, 1, 0, 1, 832, 0 }, { 395, 66, 1, 0, 832, 2 }, { 179, 1, 0, 1, 864, 0 }, { 415, 66, 1, 0, 864, 2 }, { 199, 1, 0, 1, 896, 0 }, { 435, 66, 1, 0, 896, 2 }, { 219, 1, 0, 1, 928, 0 }, { 455, 66, 1, 0, 928, 2 }, { 239, 1, 0, 1, 960, 0 }, { 475, 66, 1, 0, 960, 2 }, { 52, 1, 0, 1, 992, 0 }, { 288, 66, 1, 0, 992, 2 }, { 79, 1, 0, 1, 1024, 0 }, { 315, 66, 1, 0, 1024, 2 }, }; // FPR32 Register Class... static const MCPhysReg FPR32[] = { RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, RISCV_F17_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32, RISCV_F8_32, RISCV_F9_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32, }; // FPR32 Bit set. static const uint8_t FPR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, }; // GPR Register Class... static const MCPhysReg GPR[] = { RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, }; // GPR Bit set. static const uint8_t GPRBits[] = { 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPRNoX0 Register Class... static const MCPhysReg GPRNoX0[] = { RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, }; // GPRNoX0 Bit set. static const uint8_t GPRNoX0Bits[] = { 0xfc, 0xff, 0xff, 0xff, 0x01, }; // GPRNoX0X2 Register Class... static const MCPhysReg GPRNoX0X2[] = { RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4, }; // GPRNoX0X2 Bit set. static const uint8_t GPRNoX0X2Bits[] = { 0xf4, 0xff, 0xff, 0xff, 0x01, }; // GPRTC Register Class... static const MCPhysReg GPRTC[] = { RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, }; // GPRTC Bit set. static const uint8_t GPRTCBits[] = { 0xc0, 0xf9, 0x07, 0xe0, 0x01, }; // FPR32C Register Class... static const MCPhysReg FPR32C[] = { RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F8_32, RISCV_F9_32, }; // FPR32C Bit set. static const uint8_t FPR32CBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, }; // GPRC Register Class... static const MCPhysReg GPRC[] = { RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9, }; // GPRC Bit set. static const uint8_t GPRCBits[] = { 0x00, 0xfe, 0x01, }; // GPRC_and_GPRTC Register Class... static const MCPhysReg GPRC_and_GPRTC[] = { RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, }; // GPRC_and_GPRTC Bit set. static const uint8_t GPRC_and_GPRTCBits[] = { 0x00, 0xf8, 0x01, }; // SP Register Class... static const MCPhysReg SP[] = { RISCV_X2, }; // SP Bit set. static const uint8_t SPBits[] = { 0x08, }; // FPR64 Register Class... static const MCPhysReg FPR64[] = { RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, RISCV_F17_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64, RISCV_F8_64, RISCV_F9_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64, }; // FPR64 Bit set. static const uint8_t FPR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x01, }; // FPR64C Register Class... static const MCPhysReg FPR64C[] = { RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F8_64, RISCV_F9_64, }; // FPR64C Bit set. static const uint8_t FPR64CBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, }; static const MCRegisterClass RISCVMCRegisterClasses[] = { { FPR32, FPR32Bits, sizeof(FPR32Bits) }, { GPR, GPRBits, sizeof(GPRBits) }, { GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits) }, { GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits) }, { GPRTC, GPRTCBits, sizeof(GPRTCBits) }, { FPR32C, FPR32CBits, sizeof(FPR32CBits) }, { GPRC, GPRCBits, sizeof(GPRCBits) }, { GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits) }, { SP, SPBits, sizeof(SPBits) }, { FPR64, FPR64Bits, sizeof(FPR64Bits) }, { FPR64C, FPR64CBits, sizeof(FPR64CBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc000064400000000000000000000021470072674642500225220ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM /* Make sure: CS_MODE_RISCV64 = 0b11111 CS_MODE_RISCV32 = 0b11110 */ enum { RISCV_Feature64Bit = 1ULL << 0, RISCV_FeatureStdExtA = 1ULL << 1, RISCV_FeatureStdExtC = 1ULL << 2, RISCV_FeatureStdExtD = 1ULL << 3, RISCV_FeatureStdExtF = 1ULL << 4, RISCV_FeatureStdExtM = 1ULL << 5, RISCV_FeatureRelax = 1ULL << 6, }; #endif // GET_SUBTARGETINFO_ENUM capstone-sys-0.15.0/capstone/arch/RISCV/RISCVInstPrinter.c000064400000000000000000000346220072674642500212510ustar 00000000000000//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an RISCV MCInst to a .s file. // //===----------------------------------------------------------------------===// #ifdef CAPSTONE_HAS_RISCV #include // DEBUG #include #include #include #include "RISCVInstPrinter.h" #include "RISCVBaseInfo.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../utils.h" #include "RISCVMapping.h" //#include "RISCVDisassembler.h" #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "RISCVGenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "RISCVGenInstrInfo.inc" // Autogenerated by tblgen. static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); static bool printAliasInstr(MCInst *MI, SStream *OS, void *info); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O); static void printCSRSystemRegister(MCInst*, unsigned, SStream *); static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O); static void printCustomAliasOperand( MCInst *, unsigned, unsigned, SStream *); /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); // Include the auto-generated portion of the assembly writer. #define PRINT_ALIAS_INSTR #include "RISCVGenAsmWriter.inc" static void fixDetailOfEffectiveAddr(MCInst *MI) { unsigned reg = 0; int64_t imm = 0; CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[0].type); if (RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[1].type) { CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[2].type); imm = MI->flat_insn->detail->riscv.operands[1].imm; reg = MI->flat_insn->detail->riscv.operands[2].reg; } else if (RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[1].type) { CS_ASSERT(RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[2].type); reg = MI->flat_insn->detail->riscv.operands[1].reg; imm = MI->flat_insn->detail->riscv.operands[2].imm; } // set up effective address. MI->flat_insn->detail->riscv.operands[1].type = RISCV_OP_MEM; MI->flat_insn->detail->riscv.op_count--; MI->flat_insn->detail->riscv.operands[1].mem.base = reg; MI->flat_insn->detail->riscv.operands[1].mem.disp = imm; return; } //void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, // StringRef Annot, const MCSubtargetInfo &STI) void RISCV_printInst(MCInst *MI, SStream *O, void *info) { MCRegisterInfo *MRI = (MCRegisterInfo *) info; //bool Res = false; //MCInst *NewMI = MI; // TODO: RISCV compressd instructions. //MCInst UncompressedMI; //if (!NoAliases) //Res = uncompressInst(UncompressedMI, *MI, MRI, STI); //if (Res) //NewMI = const_cast(&UncompressedMI); if (/*NoAliases ||*/ !printAliasInstr(MI, O, info)) printInstruction(MI, O, MRI); //printAnnotation(O, Annot); // fix load/store type insttuction if (MI->csh->detail && MI->flat_insn->detail->riscv.need_effective_addr) fixDetailOfEffectiveAddr(MI); return; } static void printRegName(SStream *OS, unsigned RegNo) { SStream_concat0(OS, getRegisterName(RegNo, RISCV_ABIRegAltName)); } /** void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier) */ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { unsigned reg; int64_t Imm = 0; MCOperand *MO = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(MO)) { reg = MCOperand_getReg(MO); printRegName(O, reg); if (MI->csh->detail) { MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_REG; MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].reg = reg; MI->flat_insn->detail->riscv.op_count++; } } else { CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); Imm = MCOperand_getImm(MO); if (Imm >= 0) { if (Imm > HEX_THRESHOLD) SStream_concat(O, "0x%" PRIx64, Imm); else SStream_concat(O, "%" PRIu64, Imm); } else { if (Imm < -HEX_THRESHOLD) SStream_concat(O, "-0x%" PRIx64, -Imm); else SStream_concat(O, "-%" PRIu64, -Imm); } if (MI->csh->detail) { MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].type = RISCV_OP_IMM; MI->flat_insn->detail->riscv.operands[MI->flat_insn->detail->riscv.op_count].imm = Imm; MI->flat_insn->detail->riscv.op_count++; } } //CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); return; } static const char *getCSRSystemRegisterName(unsigned CsrNo) { switch (CsrNo) { /* * From RISC-V Privileged Architecture Version 1.10. * In the same order as Table 2.5. */ case 0x0000: return "ustatus"; case 0x0004: return "uie"; case 0x0005: return "utvec"; case 0x0040: return "uscratch"; case 0x0041: return "uepc"; case 0x0042: return "ucause"; case 0x0043: return "utval"; case 0x0044: return "uip"; case 0x0001: return "fflags"; case 0x0002: return "frm"; case 0x0003: return "fcsr"; case 0x0c00: return "cycle"; case 0x0c01: return "time"; case 0x0c02: return "instret"; case 0x0c03: return "hpmcounter3"; case 0x0c04: return "hpmcounter4"; case 0x0c05: return "hpmcounter5"; case 0x0c06: return "hpmcounter6"; case 0x0c07: return "hpmcounter7"; case 0x0c08: return "hpmcounter8"; case 0x0c09: return "hpmcounter9"; case 0x0c0a: return "hpmcounter10"; case 0x0c0b: return "hpmcounter11"; case 0x0c0c: return "hpmcounter12"; case 0x0c0d: return "hpmcounter13"; case 0x0c0e: return "hpmcounter14"; case 0x0c0f: return "hpmcounter15"; case 0x0c10: return "hpmcounter16"; case 0x0c11: return "hpmcounter17"; case 0x0c12: return "hpmcounter18"; case 0x0c13: return "hpmcounter19"; case 0x0c14: return "hpmcounter20"; case 0x0c15: return "hpmcounter21"; case 0x0c16: return "hpmcounter22"; case 0x0c17: return "hpmcounter23"; case 0x0c18: return "hpmcounter24"; case 0x0c19: return "hpmcounter25"; case 0x0c1a: return "hpmcounter26"; case 0x0c1b: return "hpmcounter27"; case 0x0c1c: return "hpmcounter28"; case 0x0c1d: return "hpmcounter29"; case 0x0c1e: return "hpmcounter30"; case 0x0c1f: return "hpmcounter31"; case 0x0c80: return "cycleh"; case 0x0c81: return "timeh"; case 0x0c82: return "instreth"; case 0x0c83: return "hpmcounter3h"; case 0x0c84: return "hpmcounter4h"; case 0x0c85: return "hpmcounter5h"; case 0x0c86: return "hpmcounter6h"; case 0x0c87: return "hpmcounter7h"; case 0x0c88: return "hpmcounter8h"; case 0x0c89: return "hpmcounter9h"; case 0x0c8a: return "hpmcounter10h"; case 0x0c8b: return "hpmcounter11h"; case 0x0c8c: return "hpmcounter12h"; case 0x0c8d: return "hpmcounter13h"; case 0x0c8e: return "hpmcounter14h"; case 0x0c8f: return "hpmcounter15h"; case 0x0c90: return "hpmcounter16h"; case 0x0c91: return "hpmcounter17h"; case 0x0c92: return "hpmcounter18h"; case 0x0c93: return "hpmcounter19h"; case 0x0c94: return "hpmcounter20h"; case 0x0c95: return "hpmcounter21h"; case 0x0c96: return "hpmcounter22h"; case 0x0c97: return "hpmcounter23h"; case 0x0c98: return "hpmcounter24h"; case 0x0c99: return "hpmcounter25h"; case 0x0c9a: return "hpmcounter26h"; case 0x0c9b: return "hpmcounter27h"; case 0x0c9c: return "hpmcounter28h"; case 0x0c9d: return "hpmcounter29h"; case 0x0c9e: return "hpmcounter30h"; case 0x0c9f: return "hpmcounter31h"; case 0x0100: return "sstatus"; case 0x0102: return "sedeleg"; case 0x0103: return "sideleg"; case 0x0104: return "sie"; case 0x0105: return "stvec"; case 0x0106: return "scounteren"; case 0x0140: return "sscratch"; case 0x0141: return "sepc"; case 0x0142: return "scause"; case 0x0143: return "stval"; case 0x0144: return "sip"; case 0x0180: return "satp"; case 0x0f11: return "mvendorid"; case 0x0f12: return "marchid"; case 0x0f13: return "mimpid"; case 0x0f14: return "mhartid"; case 0x0300: return "mstatus"; case 0x0301: return "misa"; case 0x0302: return "medeleg"; case 0x0303: return "mideleg"; case 0x0304: return "mie"; case 0x0305: return "mtvec"; case 0x0306: return "mcounteren"; case 0x0340: return "mscratch"; case 0x0341: return "mepc"; case 0x0342: return "mcause"; case 0x0343: return "mtval"; case 0x0344: return "mip"; case 0x03a0: return "pmpcfg0"; case 0x03a1: return "pmpcfg1"; case 0x03a2: return "pmpcfg2"; case 0x03a3: return "pmpcfg3"; case 0x03b0: return "pmpaddr0"; case 0x03b1: return "pmpaddr1"; case 0x03b2: return "pmpaddr2"; case 0x03b3: return "pmpaddr3"; case 0x03b4: return "pmpaddr4"; case 0x03b5: return "pmpaddr5"; case 0x03b6: return "pmpaddr6"; case 0x03b7: return "pmpaddr7"; case 0x03b8: return "pmpaddr8"; case 0x03b9: return "pmpaddr9"; case 0x03ba: return "pmpaddr10"; case 0x03bb: return "pmpaddr11"; case 0x03bc: return "pmpaddr12"; case 0x03bd: return "pmpaddr14"; case 0x03be: return "pmpaddr13"; case 0x03bf: return "pmpaddr15"; case 0x0b00: return "mcycle"; case 0x0b02: return "minstret"; case 0x0b03: return "mhpmcounter3"; case 0x0b04: return "mhpmcounter4"; case 0x0b05: return "mhpmcounter5"; case 0x0b06: return "mhpmcounter6"; case 0x0b07: return "mhpmcounter7"; case 0x0b08: return "mhpmcounter8"; case 0x0b09: return "mhpmcounter9"; case 0x0b0a: return "mhpmcounter10"; case 0x0b0b: return "mhpmcounter11"; case 0x0b0c: return "mhpmcounter12"; case 0x0b0d: return "mhpmcounter13"; case 0x0b0e: return "mhpmcounter14"; case 0x0b0f: return "mhpmcounter15"; case 0x0b10: return "mhpmcounter16"; case 0x0b11: return "mhpmcounter17"; case 0x0b12: return "mhpmcounter18"; case 0x0b13: return "mhpmcounter19"; case 0x0b14: return "mhpmcounter20"; case 0x0b15: return "mhpmcounter21"; case 0x0b16: return "mhpmcounter22"; case 0x0b17: return "mhpmcounter23"; case 0x0b18: return "mhpmcounter24"; case 0x0b19: return "mhpmcounter25"; case 0x0b1a: return "mhpmcounter26"; case 0x0b1b: return "mhpmcounter27"; case 0x0b1c: return "mhpmcounter28"; case 0x0b1d: return "mhpmcounter29"; case 0x0b1e: return "mhpmcounter30"; case 0x0b1f: return "mhpmcounter31"; case 0x0b80: return "mcycleh"; case 0x0b82: return "minstreth"; case 0x0b83: return "mhpmcounter3h"; case 0x0b84: return "mhpmcounter4h"; case 0x0b85: return "mhpmcounter5h"; case 0x0b86: return "mhpmcounter6h"; case 0x0b87: return "mhpmcounter7h"; case 0x0b88: return "mhpmcounter8h"; case 0x0b89: return "mhpmcounter9h"; case 0x0b8a: return "mhpmcounter10h"; case 0x0b8b: return "mhpmcounter11h"; case 0x0b8c: return "mhpmcounter12h"; case 0x0b8d: return "mhpmcounter13h"; case 0x0b8e: return "mhpmcounter14h"; case 0x0b8f: return "mhpmcounter15h"; case 0x0b90: return "mhpmcounter16h"; case 0x0b91: return "mhpmcounter17h"; case 0x0b92: return "mhpmcounter18h"; case 0x0b93: return "mhpmcounter19h"; case 0x0b94: return "mhpmcounter20h"; case 0x0b95: return "mhpmcounter21h"; case 0x0b96: return "mhpmcounter22h"; case 0x0b97: return "mhpmcounter23h"; case 0x0b98: return "mhpmcounter24h"; case 0x0b99: return "mhpmcounter25h"; case 0x0b9a: return "mhpmcounter26h"; case 0x0b9b: return "mhpmcounter27h"; case 0x0b9c: return "mhpmcounter28h"; case 0x0b9d: return "mhpmcounter29h"; case 0x0b9e: return "mhpmcounter30h"; case 0x0b9f: return "mhpmcounter31h"; case 0x0323: return "mhpmevent3"; case 0x0324: return "mhpmevent4"; case 0x0325: return "mhpmevent5"; case 0x0326: return "mhpmevent6"; case 0x0327: return "mhpmevent7"; case 0x0328: return "mhpmevent8"; case 0x0329: return "mhpmevent9"; case 0x032a: return "mhpmevent10"; case 0x032b: return "mhpmevent11"; case 0x032c: return "mhpmevent12"; case 0x032d: return "mhpmevent13"; case 0x032e: return "mhpmevent14"; case 0x032f: return "mhpmevent15"; case 0x0330: return "mhpmevent16"; case 0x0331: return "mhpmevent17"; case 0x0332: return "mhpmevent18"; case 0x0333: return "mhpmevent19"; case 0x0334: return "mhpmevent20"; case 0x0335: return "mhpmevent21"; case 0x0336: return "mhpmevent22"; case 0x0337: return "mhpmevent23"; case 0x0338: return "mhpmevent24"; case 0x0339: return "mhpmevent25"; case 0x033a: return "mhpmevent26"; case 0x033b: return "mhpmevent27"; case 0x033c: return "mhpmevent28"; case 0x033d: return "mhpmevent29"; case 0x033e: return "mhpmevent30"; case 0x033f: return "mhpmevent31"; case 0x07a0: return "tselect"; case 0x07a1: return "tdata1"; case 0x07a2: return "tdata2"; case 0x07a3: return "tdata3"; case 0x07b0: return "dcsr"; case 0x07b1: return "dpc"; case 0x07b2: return "dscratch"; } return NULL; } static void printCSRSystemRegister(MCInst *MI, unsigned OpNo, //const MCSubtargetInfo &STI, SStream *O) { unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); const char *Name = getCSRSystemRegisterName(Imm); if (Name) { SStream_concat0(O, Name); } else { SStream_concat(O, "%u", Imm); } } static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O) { unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); //CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); if ((FenceArg & RISCVFenceField_I) != 0) SStream_concat0(O, "i"); if ((FenceArg & RISCVFenceField_O) != 0) SStream_concat0(O, "o"); if ((FenceArg & RISCVFenceField_R) != 0) SStream_concat0(O, "r"); if ((FenceArg & RISCVFenceField_W) != 0) SStream_concat0(O, "w"); if (FenceArg == 0) SStream_concat0(O, "unknown"); } static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O) { enum RoundingMode FRMArg = (enum RoundingMode)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); #if 0 auto FRMArg = static_cast(MI->getOperand(OpNo).getImm()); O << RISCVFPRndMode::roundingModeToString(FRMArg); #endif SStream_concat0(O, roundingModeToString(FRMArg)); } #endif // CAPSTONE_HAS_RISCV capstone-sys-0.15.0/capstone/arch/RISCV/RISCVInstPrinter.h000064400000000000000000000013460072674642500212530ustar 00000000000000//===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints a RISCV MCInst to a .s file. // //===----------------------------------------------------------------------===// #ifndef CS_RISCVINSTPRINTER_H #define CS_RISCVINSTPRINTER_H #include "../../MCInst.h" #include "../../SStream.h" void RISCV_printInst(MCInst * MI, SStream * O, void *info); void RISCV_post_printer(csh ud, cs_insn * insn, char *insn_asm, MCInst * mci); #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVMapping.c000064400000000000000000000204700072674642500203570ustar 00000000000000 #ifdef CAPSTONE_HAS_RISCV #include // debug #include #include "../../utils.h" #include "RISCVMapping.h" #include "RISCVInstPrinter.h" #define GET_INSTRINFO_ENUM #include "RISCVGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { { RISCV_REG_INVALID, NULL }, { RISCV_REG_X0, "zero" }, { RISCV_REG_X1, "ra" }, { RISCV_REG_X2, "sp" }, { RISCV_REG_X3, "gp" }, { RISCV_REG_X4, "tp" }, { RISCV_REG_X5, "t0" }, { RISCV_REG_X6, "t1" }, { RISCV_REG_X7, "t2" }, { RISCV_REG_X8, "s0" }, { RISCV_REG_X9, "s1" }, { RISCV_REG_X10, "a0" }, { RISCV_REG_X11, "a1" }, { RISCV_REG_X12, "a2" }, { RISCV_REG_X13, "a3" }, { RISCV_REG_X14, "a4" }, { RISCV_REG_X15, "a5" }, { RISCV_REG_X16, "a6" }, { RISCV_REG_X17, "a7" }, { RISCV_REG_X18, "s2" }, { RISCV_REG_X19, "s3" }, { RISCV_REG_X20, "s4" }, { RISCV_REG_X21, "s5" }, { RISCV_REG_X22, "s6" }, { RISCV_REG_X23, "s7" }, { RISCV_REG_X24, "s8" }, { RISCV_REG_X25, "s9" }, { RISCV_REG_X26, "s10" }, { RISCV_REG_X27, "s11" }, { RISCV_REG_X28, "t3" }, { RISCV_REG_X29, "t4" }, { RISCV_REG_X30, "t5" }, { RISCV_REG_X31, "t6" }, { RISCV_REG_F0_32, "ft0" }, { RISCV_REG_F0_64, "ft0" }, { RISCV_REG_F1_32, "ft1" }, { RISCV_REG_F1_64, "ft1" }, { RISCV_REG_F2_32, "ft2" }, { RISCV_REG_F2_64, "ft2" }, { RISCV_REG_F3_32, "ft3" }, { RISCV_REG_F3_64, "ft3" }, { RISCV_REG_F4_32, "ft4" }, { RISCV_REG_F4_64, "ft4" }, { RISCV_REG_F5_32, "ft5" }, { RISCV_REG_F5_64, "ft5" }, { RISCV_REG_F6_32, "ft6" }, { RISCV_REG_F6_64, "ft6" }, { RISCV_REG_F7_32, "ft7" }, { RISCV_REG_F7_64, "ft7" }, { RISCV_REG_F8_32, "fs0" }, { RISCV_REG_F8_64, "fs0" }, { RISCV_REG_F9_32, "fs1" }, { RISCV_REG_F9_64, "fs1" }, { RISCV_REG_F10_32, "fa0" }, { RISCV_REG_F10_64, "fa0" }, { RISCV_REG_F11_32, "fa1" }, { RISCV_REG_F11_64, "fa1" }, { RISCV_REG_F12_32, "fa2" }, { RISCV_REG_F12_64, "fa2" }, { RISCV_REG_F13_32, "fa3" }, { RISCV_REG_F13_64, "fa3" }, { RISCV_REG_F14_32, "fa4" }, { RISCV_REG_F14_64, "fa4" }, { RISCV_REG_F15_32, "fa5" }, { RISCV_REG_F15_64, "fa5" }, { RISCV_REG_F16_32, "fa6" }, { RISCV_REG_F16_64, "fa6" }, { RISCV_REG_F17_32, "fa7" }, { RISCV_REG_F17_64, "fa7" }, { RISCV_REG_F18_32, "fs2" }, { RISCV_REG_F18_64, "fs2" }, { RISCV_REG_F19_32, "fs3" }, { RISCV_REG_F19_64, "fs3" }, { RISCV_REG_F20_32, "fs4" }, { RISCV_REG_F20_64, "fs4" }, { RISCV_REG_F21_32, "fs5" }, { RISCV_REG_F21_64, "fs5" }, { RISCV_REG_F22_32, "fs6" }, { RISCV_REG_F22_64, "fs6" }, { RISCV_REG_F23_32, "fs7" }, { RISCV_REG_F23_64, "fs7" }, { RISCV_REG_F24_32, "fs8" }, { RISCV_REG_F24_64, "fs8" }, { RISCV_REG_F25_32, "fs9" }, { RISCV_REG_F25_64, "fs9" }, { RISCV_REG_F26_32, "fs10" }, { RISCV_REG_F26_64, "fs10" }, { RISCV_REG_F27_32, "fs11" }, { RISCV_REG_F27_64, "fs11" }, { RISCV_REG_F28_32, "ft8" }, { RISCV_REG_F28_64, "ft8" }, { RISCV_REG_F29_32, "ft9" }, { RISCV_REG_F29_64, "ft9" }, { RISCV_REG_F30_32, "ft10" }, { RISCV_REG_F30_64, "ft10" }, { RISCV_REG_F31_32, "ft11" }, { RISCV_REG_F31_64, "ft11" }, }; #endif const char *RISCV_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= RISCV_REG_ENDING) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET {0}, {0}, {0}, 0, 0 #endif }, #include "RISCVMappingInsn.inc" }; // given internal insn id, return public instruction info void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id) { unsigned int i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = RISCV_GRP_JUMP; insn->detail->groups_count++; } #endif } } } static const name_map insn_name_maps[] = { {RISCV_INS_INVALID, NULL}, #include "RISCVGenInsnNameMaps.inc" }; const char *RISCV_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= RISCV_INS_ENDING) return NULL; return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { { RISCV_GRP_INVALID, NULL }, { RISCV_GRP_JUMP, "jump" }, // architecture specific { RISCV_GRP_ISRV32, "isrv32" }, { RISCV_GRP_ISRV64, "isrv64" }, { RISCV_GRP_HASSTDEXTA, "hasStdExtA" }, { RISCV_GRP_HASSTDEXTC, "hasStdExtC" }, { RISCV_GRP_HASSTDEXTD, "hasStdExtD" }, { RISCV_GRP_HASSTDEXTF, "hasStdExtF" }, { RISCV_GRP_HASSTDEXTM, "hasStdExtM" }, /* { RISCV_GRP_ISRVA, "isrva" }, { RISCV_GRP_ISRVC, "isrvc" }, { RISCV_GRP_ISRVD, "isrvd" }, { RISCV_GRP_ISRVCD, "isrvcd" }, { RISCV_GRP_ISRVF, "isrvf" }, { RISCV_GRP_ISRV32C, "isrv32c" }, { RISCV_GRP_ISRV32CF, "isrv32cf" }, { RISCV_GRP_ISRVM, "isrvm" }, { RISCV_GRP_ISRV64A, "isrv64a" }, { RISCV_GRP_ISRV64C, "isrv64c" }, { RISCV_GRP_ISRV64D, "isrv64d" }, { RISCV_GRP_ISRV64F, "isrv64f" }, { RISCV_GRP_ISRV64M, "isrv64m" } */ { RISCV_GRP_ENDING, NULL } }; #endif const char *RISCV_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET // verify group id if (id >= RISCV_GRP_ENDING || (id > RISCV_GRP_JUMP && id < RISCV_GRP_ISRV32)) return NULL; return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // map instruction name to public instruction ID riscv_reg RISCV_map_insn(const char *name) { // handle special alias first unsigned int i; // NOTE: skip first NULL name in insn_name_maps i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); return (i != -1) ? i : RISCV_REG_INVALID; } // map internal raw register to 'public' register riscv_reg RISCV_map_register(unsigned int r) { static const unsigned int map[] = { 0, RISCV_REG_X0, RISCV_REG_X1, RISCV_REG_X2, RISCV_REG_X3, RISCV_REG_X4, RISCV_REG_X5, RISCV_REG_X6, RISCV_REG_X7, RISCV_REG_X8, RISCV_REG_X9, RISCV_REG_X10, RISCV_REG_X11, RISCV_REG_X12, RISCV_REG_X13, RISCV_REG_X14, RISCV_REG_X15, RISCV_REG_X16, RISCV_REG_X17, RISCV_REG_X18, RISCV_REG_X19, RISCV_REG_X20, RISCV_REG_X21, RISCV_REG_X22, RISCV_REG_X23, RISCV_REG_X24, RISCV_REG_X25, RISCV_REG_X26, RISCV_REG_X27, RISCV_REG_X28, RISCV_REG_X29, RISCV_REG_X30, RISCV_REG_X31, RISCV_REG_F0_32, RISCV_REG_F0_64, RISCV_REG_F1_32, RISCV_REG_F1_64, RISCV_REG_F2_32, RISCV_REG_F2_64, RISCV_REG_F3_32, RISCV_REG_F3_64, RISCV_REG_F4_32, RISCV_REG_F4_64, RISCV_REG_F5_32, RISCV_REG_F5_64, RISCV_REG_F6_32, RISCV_REG_F6_64, RISCV_REG_F7_32, RISCV_REG_F7_64, RISCV_REG_F8_32, RISCV_REG_F8_64, RISCV_REG_F9_32, RISCV_REG_F9_64, RISCV_REG_F10_32, RISCV_REG_F10_64, RISCV_REG_F11_32, RISCV_REG_F11_64, RISCV_REG_F12_32, RISCV_REG_F12_64, RISCV_REG_F13_32, RISCV_REG_F13_64, RISCV_REG_F14_32, RISCV_REG_F14_64, RISCV_REG_F15_32, RISCV_REG_F15_64, RISCV_REG_F16_32, RISCV_REG_F16_64, RISCV_REG_F17_32, RISCV_REG_F17_64, RISCV_REG_F18_32, RISCV_REG_F18_64, RISCV_REG_F19_32, RISCV_REG_F19_64, RISCV_REG_F20_32, RISCV_REG_F20_64, RISCV_REG_F21_32, RISCV_REG_F21_64, RISCV_REG_F22_32, RISCV_REG_F22_64, RISCV_REG_F23_32, RISCV_REG_F23_64, RISCV_REG_F24_32, RISCV_REG_F24_64, RISCV_REG_F25_32, RISCV_REG_F25_64, RISCV_REG_F26_32, RISCV_REG_F26_64, RISCV_REG_F27_32, RISCV_REG_F27_64, RISCV_REG_F28_32, RISCV_REG_F28_64, RISCV_REG_F29_32, RISCV_REG_F29_64, RISCV_REG_F30_32, RISCV_REG_F30_64, RISCV_REG_F31_32, RISCV_REG_F31_64, }; if (r < ARR_SIZE(map)) return map[r]; // cannot find this register return 0; } #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVMapping.h000064400000000000000000000011220072674642500203550ustar 00000000000000 #ifndef CS_RISCV_MAP_H #define CS_RISCV_MAP_H #include "../../include/capstone/capstone.h" // given internal insn id, return public instruction info void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id); const char *RISCV_insn_name(csh handle, unsigned int id); const char *RISCV_group_name(csh handle, unsigned int id); const char *RISCV_reg_name(csh handle, unsigned int reg); // map instruction name to instruction ID riscv_reg RISCV_map_insn(const char *name); // map internal raw register to 'public' register riscv_reg RISCV_map_register(unsigned int r); #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVMappingInsn.inc000064400000000000000000000773400072674642500215460ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { RISCV_ADD, RISCV_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_ADDI, RISCV_INS_ADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_ADDIW, RISCV_INS_ADDIW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_ADDW, RISCV_INS_ADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOADD_D, RISCV_INS_AMOADD_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOADD_D_AQ, RISCV_INS_AMOADD_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOADD_D_AQ_RL, RISCV_INS_AMOADD_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOADD_D_RL, RISCV_INS_AMOADD_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOADD_W, RISCV_INS_AMOADD_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOADD_W_AQ, RISCV_INS_AMOADD_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOADD_W_AQ_RL, RISCV_INS_AMOADD_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOADD_W_RL, RISCV_INS_AMOADD_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOAND_D, RISCV_INS_AMOAND_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOAND_D_AQ, RISCV_INS_AMOAND_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOAND_D_AQ_RL, RISCV_INS_AMOAND_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOAND_D_RL, RISCV_INS_AMOAND_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOAND_W, RISCV_INS_AMOAND_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOAND_W_AQ, RISCV_INS_AMOAND_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOAND_W_AQ_RL, RISCV_INS_AMOAND_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOAND_W_RL, RISCV_INS_AMOAND_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_D, RISCV_INS_AMOMAXU_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_D_AQ, RISCV_INS_AMOMAXU_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_D_AQ_RL, RISCV_INS_AMOMAXU_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_D_RL, RISCV_INS_AMOMAXU_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_W, RISCV_INS_AMOMAXU_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_W_AQ, RISCV_INS_AMOMAXU_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_W_AQ_RL, RISCV_INS_AMOMAXU_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAXU_W_RL, RISCV_INS_AMOMAXU_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_D, RISCV_INS_AMOMAX_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_D_AQ, RISCV_INS_AMOMAX_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_D_AQ_RL, RISCV_INS_AMOMAX_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_D_RL, RISCV_INS_AMOMAX_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_W, RISCV_INS_AMOMAX_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_W_AQ, RISCV_INS_AMOMAX_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_W_AQ_RL, RISCV_INS_AMOMAX_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMAX_W_RL, RISCV_INS_AMOMAX_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_D, RISCV_INS_AMOMINU_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_D_AQ, RISCV_INS_AMOMINU_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_D_AQ_RL, RISCV_INS_AMOMINU_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_D_RL, RISCV_INS_AMOMINU_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_W, RISCV_INS_AMOMINU_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_W_AQ, RISCV_INS_AMOMINU_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_W_AQ_RL, RISCV_INS_AMOMINU_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMINU_W_RL, RISCV_INS_AMOMINU_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_D, RISCV_INS_AMOMIN_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_D_AQ, RISCV_INS_AMOMIN_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_D_AQ_RL, RISCV_INS_AMOMIN_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_D_RL, RISCV_INS_AMOMIN_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_W, RISCV_INS_AMOMIN_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_W_AQ, RISCV_INS_AMOMIN_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_W_AQ_RL, RISCV_INS_AMOMIN_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOMIN_W_RL, RISCV_INS_AMOMIN_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOOR_D, RISCV_INS_AMOOR_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOOR_D_AQ, RISCV_INS_AMOOR_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOOR_D_AQ_RL, RISCV_INS_AMOOR_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOOR_D_RL, RISCV_INS_AMOOR_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOOR_W, RISCV_INS_AMOOR_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOOR_W_AQ, RISCV_INS_AMOOR_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOOR_W_AQ_RL, RISCV_INS_AMOOR_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOOR_W_RL, RISCV_INS_AMOOR_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_D, RISCV_INS_AMOSWAP_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_D_AQ, RISCV_INS_AMOSWAP_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_D_AQ_RL, RISCV_INS_AMOSWAP_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_D_RL, RISCV_INS_AMOSWAP_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_W, RISCV_INS_AMOSWAP_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_W_AQ, RISCV_INS_AMOSWAP_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_W_AQ_RL, RISCV_INS_AMOSWAP_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOSWAP_W_RL, RISCV_INS_AMOSWAP_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_D, RISCV_INS_AMOXOR_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_D_AQ, RISCV_INS_AMOXOR_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_D_AQ_RL, RISCV_INS_AMOXOR_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_D_RL, RISCV_INS_AMOXOR_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_W, RISCV_INS_AMOXOR_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_W_AQ, RISCV_INS_AMOXOR_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_W_AQ_RL, RISCV_INS_AMOXOR_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AMOXOR_W_RL, RISCV_INS_AMOXOR_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_AND, RISCV_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_ANDI, RISCV_INS_ANDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_AUIPC, RISCV_INS_AUIPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_BEQ, RISCV_INS_BEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { RISCV_BGE, RISCV_INS_BGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { RISCV_BGEU, RISCV_INS_BGEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { RISCV_BLT, RISCV_INS_BLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { RISCV_BLTU, RISCV_INS_BLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { RISCV_BNE, RISCV_INS_BNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { RISCV_CSRRC, RISCV_INS_CSRRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_CSRRCI, RISCV_INS_CSRRCI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_CSRRS, RISCV_INS_CSRRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_CSRRSI, RISCV_INS_CSRRSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_CSRRW, RISCV_INS_CSRRW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_CSRRWI, RISCV_INS_CSRRWI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_C_ADD, RISCV_INS_C_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_ADDI, RISCV_INS_C_ADDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_ADDI16SP, RISCV_INS_C_ADDI16SP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_ADDI4SPN, RISCV_INS_C_ADDI4SPN, #ifndef CAPSTONE_DIET { RISCV_REG_X2, 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_ADDIW, RISCV_INS_C_ADDIW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_ADDW, RISCV_INS_C_ADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_AND, RISCV_INS_C_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_ANDI, RISCV_INS_C_ANDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_BEQZ, RISCV_INS_C_BEQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 #endif }, { RISCV_C_BNEZ, RISCV_INS_C_BNEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 #endif }, { RISCV_C_EBREAK, RISCV_INS_C_EBREAK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_FLD, RISCV_INS_C_FLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_C_FLDSP, RISCV_INS_C_FLDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_C_FLW, RISCV_INS_C_FLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 #endif }, { RISCV_C_FLWSP, RISCV_INS_C_FLWSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 #endif }, { RISCV_C_FSD, RISCV_INS_C_FSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_C_FSDSP, RISCV_INS_C_FSDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_C_FSW, RISCV_INS_C_FSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 #endif }, { RISCV_C_FSWSP, RISCV_INS_C_FSWSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 #endif }, { RISCV_C_J, RISCV_INS_C_J, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 #endif }, { RISCV_C_JAL, RISCV_INS_C_JAL, #ifndef CAPSTONE_DIET { 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, 0 }, 0, 0 #endif }, { RISCV_C_JALR, RISCV_INS_C_JALR, #ifndef CAPSTONE_DIET { 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_JR, RISCV_INS_C_JR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 1 #endif }, { RISCV_C_LD, RISCV_INS_C_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_LDSP, RISCV_INS_C_LDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_LI, RISCV_INS_C_LI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_LUI, RISCV_INS_C_LUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_LW, RISCV_INS_C_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_LWSP, RISCV_INS_C_LWSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_MV, RISCV_INS_C_MV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_NOP, RISCV_INS_C_NOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_OR, RISCV_INS_C_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_SD, RISCV_INS_C_SD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_SDSP, RISCV_INS_C_SDSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_SLLI, RISCV_INS_C_SLLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_SRAI, RISCV_INS_C_SRAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_SRLI, RISCV_INS_C_SRLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_SUB, RISCV_INS_C_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_SUBW, RISCV_INS_C_SUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_C_SW, RISCV_INS_C_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_SWSP, RISCV_INS_C_SWSP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_UNIMP, RISCV_INS_C_UNIMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_C_XOR, RISCV_INS_C_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 #endif }, { RISCV_DIV, RISCV_INS_DIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_DIVU, RISCV_INS_DIVU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_DIVUW, RISCV_INS_DIVUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_DIVW, RISCV_INS_DIVW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_EBREAK, RISCV_INS_EBREAK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_ECALL, RISCV_INS_ECALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_FADD_D, RISCV_INS_FADD_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FADD_S, RISCV_INS_FADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FCLASS_D, RISCV_INS_FCLASS_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCLASS_S, RISCV_INS_FCLASS_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FCVT_D_L, RISCV_INS_FCVT_D_L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_D_LU, RISCV_INS_FCVT_D_LU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_D_S, RISCV_INS_FCVT_D_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCVT_D_W, RISCV_INS_FCVT_D_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCVT_D_WU, RISCV_INS_FCVT_D_WU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCVT_LU_D, RISCV_INS_FCVT_LU_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_LU_S, RISCV_INS_FCVT_LU_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_L_D, RISCV_INS_FCVT_L_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_L_S, RISCV_INS_FCVT_L_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_S_D, RISCV_INS_FCVT_S_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCVT_S_L, RISCV_INS_FCVT_S_L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_S_LU, RISCV_INS_FCVT_S_LU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FCVT_S_W, RISCV_INS_FCVT_S_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FCVT_S_WU, RISCV_INS_FCVT_S_WU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FCVT_WU_D, RISCV_INS_FCVT_WU_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCVT_WU_S, RISCV_INS_FCVT_WU_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FCVT_W_D, RISCV_INS_FCVT_W_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FCVT_W_S, RISCV_INS_FCVT_W_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FDIV_D, RISCV_INS_FDIV_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FDIV_S, RISCV_INS_FDIV_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FENCE, RISCV_INS_FENCE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_FENCE_I, RISCV_INS_FENCE_I, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_FENCE_TSO, RISCV_INS_FENCE_TSO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_FEQ_D, RISCV_INS_FEQ_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FEQ_S, RISCV_INS_FEQ_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FLD, RISCV_INS_FLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FLE_D, RISCV_INS_FLE_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FLE_S, RISCV_INS_FLE_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FLT_D, RISCV_INS_FLT_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FLT_S, RISCV_INS_FLT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FLW, RISCV_INS_FLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMADD_D, RISCV_INS_FMADD_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FMADD_S, RISCV_INS_FMADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMAX_D, RISCV_INS_FMAX_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FMAX_S, RISCV_INS_FMAX_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMIN_D, RISCV_INS_FMIN_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FMIN_S, RISCV_INS_FMIN_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMSUB_D, RISCV_INS_FMSUB_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FMSUB_S, RISCV_INS_FMSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMUL_D, RISCV_INS_FMUL_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FMUL_S, RISCV_INS_FMUL_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMV_D_X, RISCV_INS_FMV_D_X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FMV_W_X, RISCV_INS_FMV_W_X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FMV_X_D, RISCV_INS_FMV_X_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_FMV_X_W, RISCV_INS_FMV_X_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FNMADD_D, RISCV_INS_FNMADD_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FNMADD_S, RISCV_INS_FNMADD_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FNMSUB_D, RISCV_INS_FNMSUB_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FNMSUB_S, RISCV_INS_FNMSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FSD, RISCV_INS_FSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FSGNJN_D, RISCV_INS_FSGNJN_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FSGNJN_S, RISCV_INS_FSGNJN_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FSGNJX_D, RISCV_INS_FSGNJX_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FSGNJX_S, RISCV_INS_FSGNJX_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FSGNJ_D, RISCV_INS_FSGNJ_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FSGNJ_S, RISCV_INS_FSGNJ_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FSQRT_D, RISCV_INS_FSQRT_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FSQRT_S, RISCV_INS_FSQRT_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FSUB_D, RISCV_INS_FSUB_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 #endif }, { RISCV_FSUB_S, RISCV_INS_FSUB_S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_FSW, RISCV_INS_FSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 #endif }, { RISCV_JAL, RISCV_INS_JAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_JALR, RISCV_INS_JALR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LB, RISCV_INS_LB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LBU, RISCV_INS_LBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LD, RISCV_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_LH, RISCV_INS_LH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LHU, RISCV_INS_LHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LR_D, RISCV_INS_LR_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_LR_D_AQ, RISCV_INS_LR_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_LR_D_AQ_RL, RISCV_INS_LR_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_LR_D_RL, RISCV_INS_LR_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_LR_W, RISCV_INS_LR_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_LR_W_AQ, RISCV_INS_LR_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_LR_W_AQ_RL, RISCV_INS_LR_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_LR_W_RL, RISCV_INS_LR_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_LUI, RISCV_INS_LUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LW, RISCV_INS_LW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_LWU, RISCV_INS_LWU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_MRET, RISCV_INS_MRET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_MUL, RISCV_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_MULH, RISCV_INS_MULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_MULHSU, RISCV_INS_MULHSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_MULHU, RISCV_INS_MULHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_MULW, RISCV_INS_MULW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_OR, RISCV_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_ORI, RISCV_INS_ORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_REM, RISCV_INS_REM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_REMU, RISCV_INS_REMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 #endif }, { RISCV_REMUW, RISCV_INS_REMUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_REMW, RISCV_INS_REMW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SB, RISCV_INS_SB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SC_D, RISCV_INS_SC_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SC_D_AQ, RISCV_INS_SC_D_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SC_D_AQ_RL, RISCV_INS_SC_D_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SC_D_RL, RISCV_INS_SC_D_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SC_W, RISCV_INS_SC_W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_SC_W_AQ, RISCV_INS_SC_W_AQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_SC_W_AQ_RL, RISCV_INS_SC_W_AQ_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_SC_W_RL, RISCV_INS_SC_W_RL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 #endif }, { RISCV_SD, RISCV_INS_SD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SFENCE_VMA, RISCV_INS_SFENCE_VMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SH, RISCV_INS_SH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SLL, RISCV_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SLLI, RISCV_INS_SLLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SLLIW, RISCV_INS_SLLIW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SLLW, RISCV_INS_SLLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SLT, RISCV_INS_SLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SLTI, RISCV_INS_SLTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SLTIU, RISCV_INS_SLTIU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SLTU, RISCV_INS_SLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SRA, RISCV_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SRAI, RISCV_INS_SRAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SRAIW, RISCV_INS_SRAIW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SRAW, RISCV_INS_SRAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SRET, RISCV_INS_SRET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SRL, RISCV_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SRLI, RISCV_INS_SRLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SRLIW, RISCV_INS_SRLIW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SRLW, RISCV_INS_SRLW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SUB, RISCV_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_SUBW, RISCV_INS_SUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 #endif }, { RISCV_SW, RISCV_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_UNIMP, RISCV_INS_UNIMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_URET, RISCV_INS_URET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_WFI, RISCV_INS_WFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_XOR, RISCV_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { RISCV_XORI, RISCV_INS_XORI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/RISCV/RISCVModule.c000064400000000000000000000016600072674642500202110ustar 00000000000000/* Capstone Disassembly Engine */ /* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ #ifdef CAPSTONE_HAS_RISCV #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "RISCVDisassembler.h" #include "RISCVInstPrinter.h" #include "RISCVMapping.h" #include "RISCVModule.h" cs_err RISCV_global_init(cs_struct * ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); RISCV_init(mri); ud->printer = RISCV_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = RISCV_getInstruction; ud->post_printer = NULL; ud->reg_name = RISCV_reg_name; ud->insn_id = RISCV_get_insn_id; ud->insn_name = RISCV_insn_name; ud->group_name = RISCV_group_name; return CS_ERR_OK; } cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value) { if (type == CS_OPT_SYNTAX) handle->syntax = (int)value; return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/RISCV/RISCVModule.h000064400000000000000000000004510072674642500202130ustar 00000000000000/* Capstone Disassembly Engine */ /* By Shawn Chang , HardenedLinux@2018 */ #ifndef CS_RISCV_MODULE_H #define CS_RISCV_MODULE_H #include "../../utils.h" cs_err RISCV_global_init(cs_struct * ud); cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/Sparc/Sparc.h000064400000000000000000000040040072674642500174070ustar 00000000000000//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains the entry points for global functions defined in the LLVM // Sparc back-end. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SPARC_TARGET_SPARC_H #define CS_SPARC_TARGET_SPARC_H #include "capstone/sparc.h" inline static const char *SPARCCondCodeToString(sparc_cc CC) { switch (CC) { default: return NULL; // unreachable case SPARC_CC_ICC_A: return "a"; case SPARC_CC_ICC_N: return "n"; case SPARC_CC_ICC_NE: return "ne"; case SPARC_CC_ICC_E: return "e"; case SPARC_CC_ICC_G: return "g"; case SPARC_CC_ICC_LE: return "le"; case SPARC_CC_ICC_GE: return "ge"; case SPARC_CC_ICC_L: return "l"; case SPARC_CC_ICC_GU: return "gu"; case SPARC_CC_ICC_LEU: return "leu"; case SPARC_CC_ICC_CC: return "cc"; case SPARC_CC_ICC_CS: return "cs"; case SPARC_CC_ICC_POS: return "pos"; case SPARC_CC_ICC_NEG: return "neg"; case SPARC_CC_ICC_VC: return "vc"; case SPARC_CC_ICC_VS: return "vs"; case SPARC_CC_FCC_A: return "a"; case SPARC_CC_FCC_N: return "n"; case SPARC_CC_FCC_U: return "u"; case SPARC_CC_FCC_G: return "g"; case SPARC_CC_FCC_UG: return "ug"; case SPARC_CC_FCC_L: return "l"; case SPARC_CC_FCC_UL: return "ul"; case SPARC_CC_FCC_LG: return "lg"; case SPARC_CC_FCC_NE: return "ne"; case SPARC_CC_FCC_E: return "e"; case SPARC_CC_FCC_UE: return "ue"; case SPARC_CC_FCC_GE: return "ge"; case SPARC_CC_FCC_UGE: return "uge"; case SPARC_CC_FCC_LE: return "le"; case SPARC_CC_FCC_ULE: return "ule"; case SPARC_CC_FCC_O: return "o"; } } #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcDisassembler.c000064400000000000000000000313010072674642500217400ustar 00000000000000//===------ SparcDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SPARC #include // DEBUG #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "SparcDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" #define GET_REGINFO_MC_DESC #define GET_REGINFO_ENUM #include "SparcGenRegisterInfo.inc" static const unsigned IntRegDecoderTable[] = { SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7 }; static const unsigned FPRegDecoderTable[] = { SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31 }; static const unsigned DFPRegDecoderTable[] = { SP_D0, SP_D16, SP_D1, SP_D17, SP_D2, SP_D18, SP_D3, SP_D19, SP_D4, SP_D20, SP_D5, SP_D21, SP_D6, SP_D22, SP_D7, SP_D23, SP_D8, SP_D24, SP_D9, SP_D25, SP_D10, SP_D26, SP_D11, SP_D27, SP_D12, SP_D28, SP_D13, SP_D29, SP_D14, SP_D30, SP_D15, SP_D31 }; static const unsigned QFPRegDecoderTable[] = { SP_Q0, SP_Q8, ~0U, ~0U, SP_Q1, SP_Q9, ~0U, ~0U, SP_Q2, SP_Q10, ~0U, ~0U, SP_Q3, SP_Q11, ~0U, ~0U, SP_Q4, SP_Q12, ~0U, ~0U, SP_Q5, SP_Q13, ~0U, ~0U, SP_Q6, SP_Q14, ~0U, ~0U, SP_Q7, SP_Q15, ~0U, ~0U }; static const unsigned FCCRegDecoderTable[] = { SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3 }; static uint64_t getFeatureBits(int mode) { // support everything return (uint64_t)-1; } static DecodeStatus DecodeIntRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = IntRegDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeI64RegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = IntRegDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = FPRegDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeDFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = DFPRegDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeQFPRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 31) return MCDisassembler_Fail; Reg = QFPRegDecoderTable[RegNo]; if (Reg == ~0U) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeFCCRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { if (RegNo > 3) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, FCCRegDecoderTable[RegNo]); return MCDisassembler_Success; } static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCall(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSIMM13(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeJMPL(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSWAP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder); #define GET_SUBTARGETINFO_ENUM #include "SparcGenSubtargetInfo.inc" #include "SparcGenDisassemblerTables.inc" /// readInstruction - read four bytes and return 32 bit word. static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn) { if (len < 4) // not enough data return MCDisassembler_Fail; // Encoded as a big-endian 32-bit word in the stream. *Insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); return MCDisassembler_Success; } bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *info) { uint32_t Insn; DecodeStatus Result; Result = readInstruction32(code, code_len, &Insn); if (Result == MCDisassembler_Fail) return false; if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sparc)+sizeof(cs_sparc)); } Result = decodeInstruction_4(DecoderTableSparc32, MI, Insn, address, (MCRegisterInfo *)info, 0); if (Result != MCDisassembler_Fail) { *size = 4; return true; } return false; } typedef DecodeStatus (*DecodeFunc)(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder, bool isLoad, DecodeFunc DecodeRD) { DecodeStatus status; unsigned rd = fieldFromInstruction_4(insn, 25, 5); unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0; unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); else rs2 = fieldFromInstruction_4(insn, 0, 5); if (isLoad) { status = DecodeRD(MI, rd, Address, Decoder); if (status != MCDisassembler_Success) return status; } // Decode rs1. status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler_Success) return status; // Decode imm|rs2. if (isImm) MCOperand_CreateImm0(MI, simm13); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler_Success) return status; } if (!isLoad) { status = DecodeRD(MI, rd, Address, Decoder); if (status != MCDisassembler_Success) return status; } return MCDisassembler_Success; } static DecodeStatus DecodeLoadInt(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeIntRegsRegisterClass); } static DecodeStatus DecodeLoadFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeFPRegsRegisterClass); } static DecodeStatus DecodeLoadDFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeDFPRegsRegisterClass); } static DecodeStatus DecodeLoadQFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, true, DecodeQFPRegsRegisterClass); } static DecodeStatus DecodeStoreInt(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeIntRegsRegisterClass); } static DecodeStatus DecodeStoreFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeFPRegsRegisterClass); } static DecodeStatus DecodeStoreDFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeDFPRegsRegisterClass); } static DecodeStatus DecodeStoreQFP(MCInst *Inst, unsigned insn, uint64_t Address, const void *Decoder) { return DecodeMem(Inst, insn, Address, Decoder, false, DecodeQFPRegsRegisterClass); } static DecodeStatus DecodeCall(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { unsigned tgt = fieldFromInstruction_4(insn, 0, 30); tgt <<= 2; MCOperand_CreateImm0(MI, tgt); return MCDisassembler_Success; } static DecodeStatus DecodeSIMM13(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { unsigned tgt = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); MCOperand_CreateImm0(MI, tgt); return MCDisassembler_Success; } static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { DecodeStatus status; unsigned rd = fieldFromInstruction_4(insn, 25, 5); unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); unsigned isImm = fieldFromInstruction_4(insn, 13, 1); unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); else rs2 = fieldFromInstruction_4(insn, 0, 5); // Decode RD. status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); if (status != MCDisassembler_Success) return status; // Decode RS1. status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler_Success) return status; // Decode RS1 | SIMM13. if (isImm) MCOperand_CreateImm0(MI, simm13); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler_Success) return status; } return MCDisassembler_Success; } static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { DecodeStatus status; unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); unsigned isImm = fieldFromInstruction_4(insn, 13, 1); unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); else rs2 = fieldFromInstruction_4(insn, 0, 5); // Decode RS1. status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler_Success) return status; // Decode RS2 | SIMM13. if (isImm) MCOperand_CreateImm0(MI, simm13); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler_Success) return status; } return MCDisassembler_Success; } static DecodeStatus DecodeSWAP(MCInst *MI, unsigned insn, uint64_t Address, const void *Decoder) { DecodeStatus status; unsigned rd = fieldFromInstruction_4(insn, 25, 5); unsigned rs1 = fieldFromInstruction_4(insn, 14, 5); unsigned isImm = fieldFromInstruction_4(insn, 13, 1); unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13); else rs2 = fieldFromInstruction_4(insn, 0, 5); // Decode RD. status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); if (status != MCDisassembler_Success) return status; // Decode RS1. status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); if (status != MCDisassembler_Success) return status; // Decode RS1 | SIMM13. if (isImm) MCOperand_CreateImm0(MI, simm13); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler_Success) return status; } return MCDisassembler_Success; } void Sparc_init(MCRegisterInfo *MRI) { /* InitMCRegisterInfo(SparcRegDesc, 119, RA, PC, SparcMCRegisterClasses, 8, SparcRegUnitRoots, 86, SparcRegDiffLists, SparcRegStrings, SparcSubRegIdxLists, 7, SparcSubRegIdxRanges, SparcRegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, SparcRegDesc, 119, 0, 0, SparcMCRegisterClasses, 8, 0, 0, SparcRegDiffLists, 0, SparcSubRegIdxLists, 7, 0); } #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcDisassembler.h000064400000000000000000000006560072674642500217560ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SPARCDISASSEMBLER_H #define CS_SPARCDISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void Sparc_init(MCRegisterInfo *MRI); bool Sparc_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcGenAsmWriter.inc000064400000000000000000006772340072674642500222460ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include // debug #include /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) { static const uint32_t OpInfo[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 2452U, // DBG_VALUE 0U, // REG_SEQUENCE 0U, // COPY 2445U, // BUNDLE 2462U, // LIFETIME_START 2432U, // LIFETIME_END 0U, // STACKMAP 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // FRAME_ALLOC 4688U, // ADDCCri 4688U, // ADDCCrr 5925U, // ADDCri 5925U, // ADDCrr 4772U, // ADDEri 4772U, // ADDErr 4786U, // ADDXC 4678U, // ADDXCCC 4808U, // ADDXri 4808U, // ADDXrr 4808U, // ADDri 4808U, // ADDrr 74166U, // ADJCALLSTACKDOWN 74185U, // ADJCALLSTACKUP 5497U, // ALIGNADDR 5127U, // ALIGNADDRL 4695U, // ANDCCri 4695U, // ANDCCrr 4718U, // ANDNCCri 4718U, // ANDNCCrr 5182U, // ANDNri 5182U, // ANDNrr 5182U, // ANDXNrr 4876U, // ANDXri 4876U, // ANDXrr 4876U, // ANDri 4876U, // ANDrr 4502U, // ARRAY16 4255U, // ARRAY32 4526U, // ARRAY8 0U, // ATOMIC_LOAD_ADD_32 0U, // ATOMIC_LOAD_ADD_64 0U, // ATOMIC_LOAD_AND_32 0U, // ATOMIC_LOAD_AND_64 0U, // ATOMIC_LOAD_MAX_32 0U, // ATOMIC_LOAD_MAX_64 0U, // ATOMIC_LOAD_MIN_32 0U, // ATOMIC_LOAD_MIN_64 0U, // ATOMIC_LOAD_NAND_32 0U, // ATOMIC_LOAD_NAND_64 0U, // ATOMIC_LOAD_OR_32 0U, // ATOMIC_LOAD_OR_64 0U, // ATOMIC_LOAD_SUB_32 0U, // ATOMIC_LOAD_SUB_64 0U, // ATOMIC_LOAD_UMAX_32 0U, // ATOMIC_LOAD_UMAX_64 0U, // ATOMIC_LOAD_UMIN_32 0U, // ATOMIC_LOAD_UMIN_64 0U, // ATOMIC_LOAD_XOR_32 0U, // ATOMIC_LOAD_XOR_64 0U, // ATOMIC_SWAP_64 74271U, // BA 1194492U, // BCOND 1260028U, // BCONDA 17659U, // BINDri 17659U, // BINDrr 5065U, // BMASK 145915U, // BPFCC 211451U, // BPFCCA 276987U, // BPFCCANT 342523U, // BPFCCNT 2106465U, // BPGEZapn 2105838U, // BPGEZapt 2106532U, // BPGEZnapn 2107288U, // BPGEZnapt 2106489U, // BPGZapn 2105856U, // BPGZapt 2106552U, // BPGZnapn 2107384U, // BPGZnapt 1456636U, // BPICC 473596U, // BPICCA 539132U, // BPICCANT 604668U, // BPICCNT 2106477U, // BPLEZapn 2105847U, // BPLEZapt 2106542U, // BPLEZnapn 2107337U, // BPLEZnapt 2106500U, // BPLZapn 2105864U, // BPLZapt 2106561U, // BPLZnapn 2107428U, // BPLZnapt 2106511U, // BPNZapn 2105872U, // BPNZapt 2106570U, // BPNZnapn 2107472U, // BPNZnapt 1718780U, // BPXCC 735740U, // BPXCCA 801276U, // BPXCCANT 866812U, // BPXCCNT 2106522U, // BPZapn 2105880U, // BPZapt 2106579U, // BPZnapn 2107505U, // BPZnapt 4983U, // BSHUFFLE 74742U, // CALL 17398U, // CALLri 17398U, // CALLrr 924148U, // CASXrr 924129U, // CASrr 74001U, // CMASK16 73833U, // CMASK32 74150U, // CMASK8 2106607U, // CMPri 2106607U, // CMPrr 4332U, // EDGE16 5081U, // EDGE16L 5198U, // EDGE16LN 5165U, // EDGE16N 4164U, // EDGE32 5072U, // EDGE32L 5188U, // EDGE32LN 5156U, // EDGE32N 4511U, // EDGE8 5090U, // EDGE8L 5208U, // EDGE8LN 5174U, // EDGE8N 1053516U, // FABSD 1054031U, // FABSQ 1054376U, // FABSS 4813U, // FADDD 5383U, // FADDQ 5645U, // FADDS 4648U, // FALIGNADATA 4875U, // FAND 4112U, // FANDNOT1 5544U, // FANDNOT1S 4271U, // FANDNOT2 5591U, // FANDNOT2S 5677U, // FANDS 1194491U, // FBCOND 1260027U, // FBCONDA 4394U, // FCHKSM16 2106173U, // FCMPD 4413U, // FCMPEQ16 4226U, // FCMPEQ32 4432U, // FCMPGT16 4245U, // FCMPGT32 4340U, // FCMPLE16 4172U, // FCMPLE32 4350U, // FCMPNE16 4182U, // FCMPNE32 2106696U, // FCMPQ 2107005U, // FCMPS 4960U, // FDIVD 5475U, // FDIVQ 5815U, // FDIVS 5405U, // FDMULQ 1053620U, // FDTOI 1053996U, // FDTOQ 1054305U, // FDTOS 1054536U, // FDTOX 1053464U, // FEXPAND 4820U, // FHADDD 5652U, // FHADDS 4800U, // FHSUBD 5637U, // FHSUBS 1053473U, // FITOD 1054003U, // FITOQ 1054312U, // FITOS 6300484U, // FLCMPD 6301316U, // FLCMPS 2606U, // FLUSHW 4404U, // FMEAN16 1053543U, // FMOVD 1006078U, // FMOVD_FCC 23484926U, // FMOVD_ICC 23747070U, // FMOVD_XCC 1054058U, // FMOVQ 1006102U, // FMOVQ_FCC 23484950U, // FMOVQ_ICC 23747094U, // FMOVQ_XCC 6018U, // FMOVRGEZD 6029U, // FMOVRGEZQ 6056U, // FMOVRGEZS 6116U, // FMOVRGZD 6126U, // FMOVRGZQ 6150U, // FMOVRGZS 6067U, // FMOVRLEZD 6078U, // FMOVRLEZQ 6105U, // FMOVRLEZS 6160U, // FMOVRLZD 6170U, // FMOVRLZQ 6194U, // FMOVRLZS 6204U, // FMOVRNZD 6214U, // FMOVRNZQ 6238U, // FMOVRNZS 6009U, // FMOVRZD 6248U, // FMOVRZQ 6269U, // FMOVRZS 1054398U, // FMOVS 1006114U, // FMOVS_FCC 23484962U, // FMOVS_ICC 23747106U, // FMOVS_XCC 4490U, // FMUL8SUX16 4465U, // FMUL8ULX16 4442U, // FMUL8X16 5098U, // FMUL8X16AL 5849U, // FMUL8X16AU 4860U, // FMULD 4477U, // FMULD8SUX16 4452U, // FMULD8ULX16 5413U, // FMULQ 5714U, // FMULS 4837U, // FNADDD 5669U, // FNADDS 4881U, // FNAND 5684U, // FNANDS 1053429U, // FNEGD 1053974U, // FNEGQ 1054283U, // FNEGS 4828U, // FNHADDD 5660U, // FNHADDS 4828U, // FNMULD 5660U, // FNMULS 5513U, // FNOR 5778U, // FNORS 1052698U, // FNOT1 1054131U, // FNOT1S 1052857U, // FNOT2 1054178U, // FNOT2S 5660U, // FNSMULD 74625U, // FONE 75324U, // FONES 5508U, // FOR 4129U, // FORNOT1 5563U, // FORNOT1S 4288U, // FORNOT2 5610U, // FORNOT2S 5772U, // FORS 1052936U, // FPACK16 4192U, // FPACK32 1054507U, // FPACKFIX 4323U, // FPADD16 5620U, // FPADD16S 4155U, // FPADD32 5573U, // FPADD32S 4297U, // FPADD64 4974U, // FPMERGE 4314U, // FPSUB16 4580U, // FPSUB16S 4146U, // FPSUB32 4570U, // FPSUB32S 1053480U, // FQTOD 1053627U, // FQTOI 1054319U, // FQTOS 1054552U, // FQTOX 4423U, // FSLAS16 4236U, // FSLAS32 4378U, // FSLL16 4210U, // FSLL32 4867U, // FSMULD 1053523U, // FSQRTD 1054038U, // FSQRTQ 1054383U, // FSQRTS 4306U, // FSRA16 4138U, // FSRA32 1052681U, // FSRC1 1054112U, // FSRC1S 1052840U, // FSRC2 1054159U, // FSRC2S 4386U, // FSRL16 4218U, // FSRL32 1053487U, // FSTOD 1053634U, // FSTOI 1054010U, // FSTOQ 1054559U, // FSTOX 4793U, // FSUBD 5376U, // FSUBQ 5630U, // FSUBS 5519U, // FXNOR 5785U, // FXNORS 5526U, // FXOR 5793U, // FXORS 1053494U, // FXTOD 1054017U, // FXTOQ 1054326U, // FXTOS 74984U, // FZERO 75353U, // FZEROS 24584U, // GETPCX 1078273U, // JMPLri 1078273U, // JMPLrr 1997243U, // LDDFri 1997243U, // LDDFrr 1997249U, // LDFri 1997249U, // LDFrr 1997275U, // LDQFri 1997275U, // LDQFrr 1997229U, // LDSBri 1997229U, // LDSBrr 1997254U, // LDSHri 1997254U, // LDSHrr 1997287U, // LDSWri 1997287U, // LDSWrr 1997236U, // LDUBri 1997236U, // LDUBrr 1997261U, // LDUHri 1997261U, // LDUHrr 1997294U, // LDXri 1997294U, // LDXrr 1997249U, // LDri 1997249U, // LDrr 33480U, // LEAX_ADDri 33480U, // LEA_ADDri 1054405U, // LZCNT 75121U, // MEMBARi 1054543U, // MOVDTOX 1006122U, // MOVFCCri 1006122U, // MOVFCCrr 23484970U, // MOVICCri 23484970U, // MOVICCrr 6047U, // MOVRGEZri 6047U, // MOVRGEZrr 6142U, // MOVRGZri 6142U, // MOVRGZrr 6096U, // MOVRLEZri 6096U, // MOVRLEZrr 6186U, // MOVRLZri 6186U, // MOVRLZrr 6230U, // MOVRNZri 6230U, // MOVRNZrr 6262U, // MOVRRZri 6262U, // MOVRRZrr 1054469U, // MOVSTOSW 1054479U, // MOVSTOUW 1054543U, // MOVWTOS 23747114U, // MOVXCCri 23747114U, // MOVXCCrr 1054543U, // MOVXTOD 5954U, // MULXri 5954U, // MULXrr 2578U, // NOP 4735U, // ORCCri 4735U, // ORCCrr 4726U, // ORNCCri 4726U, // ORNCCrr 5339U, // ORNri 5339U, // ORNrr 5339U, // ORXNrr 5509U, // ORXri 5509U, // ORXrr 5509U, // ORri 5509U, // ORrr 5836U, // PDIST 5344U, // PDISTN 1053356U, // POPCrr 73729U, // RDY 4999U, // RESTOREri 4999U, // RESTORErr 76132U, // RET 76141U, // RETL 18131U, // RETTri 18131U, // RETTrr 5008U, // SAVEri 5008U, // SAVErr 4748U, // SDIVCCri 4748U, // SDIVCCrr 5995U, // SDIVXri 5995U, // SDIVXrr 5861U, // SDIVri 5861U, // SDIVrr 2182U, // SELECT_CC_DFP_FCC 2293U, // SELECT_CC_DFP_ICC 2238U, // SELECT_CC_FP_FCC 2349U, // SELECT_CC_FP_ICC 2265U, // SELECT_CC_Int_FCC 2376U, // SELECT_CC_Int_ICC 2210U, // SELECT_CC_QFP_FCC 2321U, // SELECT_CC_QFP_ICC 1053595U, // SETHIXi 1053595U, // SETHIi 2569U, // SHUTDOWN 2564U, // SIAM 5941U, // SLLXri 5941U, // SLLXrr 5116U, // SLLri 5116U, // SLLrr 4702U, // SMULCCri 4702U, // SMULCCrr 5144U, // SMULri 5144U, // SMULrr 5913U, // SRAXri 5913U, // SRAXrr 4643U, // SRAri 4643U, // SRArr 5947U, // SRLXri 5947U, // SRLXrr 5139U, // SRLri 5139U, // SRLrr 2588U, // STBAR 37428U, // STBri 37428U, // STBrr 37723U, // STDFri 37723U, // STDFrr 38607U, // STFri 38607U, // STFrr 37782U, // STHri 37782U, // STHrr 38238U, // STQFri 38238U, // STQFrr 38758U, // STXri 38758U, // STXrr 38607U, // STri 38607U, // STrr 4671U, // SUBCCri 4671U, // SUBCCrr 5919U, // SUBCri 5919U, // SUBCrr 4764U, // SUBEri 4764U, // SUBErr 4665U, // SUBXri 4665U, // SUBXrr 4665U, // SUBri 4665U, // SUBrr 1997268U, // SWAPri 1997268U, // SWAPrr 2422U, // TA3 2427U, // TA5 5883U, // TADDCCTVri 5883U, // TADDCCTVrr 4687U, // TADDCCri 4687U, // TADDCCrr 9873960U, // TICCri 9873960U, // TICCrr 37753544U, // TLS_ADDXrr 37753544U, // TLS_ADDrr 2106358U, // TLS_CALL 39746030U, // TLS_LDXrr 39745985U, // TLS_LDrr 5873U, // TSUBCCTVri 5873U, // TSUBCCTVrr 4670U, // TSUBCCri 4670U, // TSUBCCrr 10136104U, // TXCCri 10136104U, // TXCCrr 4756U, // UDIVCCri 4756U, // UDIVCCrr 6002U, // UDIVXri 6002U, // UDIVXrr 5867U, // UDIVri 5867U, // UDIVrr 4710U, // UMULCCri 4710U, // UMULCCrr 5026U, // UMULXHI 5150U, // UMULri 5150U, // UMULrr 74996U, // UNIMP 6300477U, // V9FCMPD 6300397U, // V9FCMPED 6300942U, // V9FCMPEQ 6301251U, // V9FCMPES 6301000U, // V9FCMPQ 6301309U, // V9FCMPS 47614U, // V9FMOVD_FCC 47638U, // V9FMOVQ_FCC 47650U, // V9FMOVS_FCC 47658U, // V9MOVFCCri 47658U, // V9MOVFCCrr 14689692U, // WRYri 14689692U, // WRYrr 5953U, // XMULX 5035U, // XMULXHI 4733U, // XNORCCri 4733U, // XNORCCrr 5520U, // XNORXrr 5520U, // XNORri 5520U, // XNORrr 4741U, // XORCCri 4741U, // XORCCrr 5527U, // XORXri 5527U, // XORXrr 5527U, // XORri 5527U, // XORrr 0U }; #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0, /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0, /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0, /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0, /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0, /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0, /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0, /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0, /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0, /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0, /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0, /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0, /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0, /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0, /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0, /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0, /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0, /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0, /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0, /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0, /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0, /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0, /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0, /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0, /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0, /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0, /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0, /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0, /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0, /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0, /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0, /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0, /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0, /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0, /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0, /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0, /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0, /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0, /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0, /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0, /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0, /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0, /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0, /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0, /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0, /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0, /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0, /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0, /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0, /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0, /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0, /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0, /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0, /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0, /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0, /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0, /* 542 */ 'b', 'a', 32, 0, /* 546 */ 's', 'r', 'a', 32, 0, /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0, /* 563 */ 's', 't', 'b', 32, 0, /* 568 */ 's', 'u', 'b', 32, 0, /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0, /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0, /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0, /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0, /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0, /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0, /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0, /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0, /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0, /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0, /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0, /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0, /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0, /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0, /* 683 */ 'p', 'o', 'p', 'c', 32, 0, /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0, /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0, /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0, /* 711 */ 'a', 'd', 'd', 32, 0, /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0, /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0, /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0, /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0, /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0, /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0, /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0, /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0, /* 778 */ 'f', 'a', 'n', 'd', 32, 0, /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0, /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0, /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0, /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0, /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0, /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0, /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0, /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0, /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0, /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0, /* 858 */ 's', 't', 'd', 32, 0, /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0, /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0, /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0, /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0, /* 896 */ 'f', 'o', 'n', 'e', 32, 0, /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0, /* 911 */ 's', 'a', 'v', 'e', 32, 0, /* 917 */ 's', 't', 'h', 32, 0, /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0, /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0, /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0, /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0, /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0, /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0, /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0, /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0, /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0, /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0, /* 1013 */ 'c', 'a', 'l', 'l', 32, 0, /* 1019 */ 's', 'l', 'l', 32, 0, /* 1024 */ 'j', 'm', 'p', 'l', 32, 0, /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0, /* 1042 */ 's', 'r', 'l', 32, 0, /* 1047 */ 's', 'm', 'u', 'l', 32, 0, /* 1053 */ 'u', 'm', 'u', 'l', 32, 0, /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0, /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0, /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0, /* 1085 */ 'a', 'n', 'd', 'n', 32, 0, /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0, /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0, /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0, /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0, /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0, /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0, /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0, /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0, /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0, /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0, /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0, /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0, /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0, /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0, /* 1242 */ 'o', 'r', 'n', 32, 0, /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0, /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0, /* 1262 */ 'c', 'm', 'p', 32, 0, /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0, /* 1274 */ 'j', 'm', 'p', 32, 0, /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0, /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0, /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0, /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0, /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0, /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0, /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0, /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0, /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0, /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0, /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0, /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0, /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0, /* 1373 */ 's', 't', 'q', 32, 0, /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0, /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0, /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0, /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0, /* 1411 */ 'f', 'o', 'r', 32, 0, /* 1416 */ 'f', 'n', 'o', 'r', 32, 0, /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0, /* 1429 */ 'f', 'x', 'o', 'r', 32, 0, /* 1435 */ 'w', 'r', 32, 0, /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0, /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0, /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0, /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0, /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0, /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0, /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0, /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0, /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0, /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0, /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0, /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0, /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0, /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0, /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0, /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0, /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0, /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0, /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0, /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0, /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0, /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0, /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0, /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0, /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0, /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0, /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0, /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0, /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0, /* 1675 */ 'f', 'o', 'r', 's', 32, 0, /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0, /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0, /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0, /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0, /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0, /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0, /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0, /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0, /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0, /* 1746 */ 'r', 'e', 't', 't', 32, 0, /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0, /* 1764 */ 's', 'd', 'i', 'v', 32, 0, /* 1770 */ 'u', 'd', 'i', 'v', 32, 0, /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0, /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0, /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0, /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0, /* 1816 */ 's', 'r', 'a', 'x', 32, 0, /* 1822 */ 's', 'u', 'b', 'x', 32, 0, /* 1828 */ 'a', 'd', 'd', 'x', 32, 0, /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0, /* 1844 */ 's', 'l', 'l', 'x', 32, 0, /* 1850 */ 's', 'r', 'l', 'x', 32, 0, /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0, /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0, /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0, /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0, /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0, /* 1893 */ 's', 't', 'x', 32, 0, /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0, /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0, /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0, /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0, /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0, /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0, /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0, /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0, /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0, /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0, /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0, /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0, /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0, /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0, /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0, /* 2039 */ 'b', 'r', 'g', 'z', 32, 0, /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0, /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0, /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0, /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0, /* 2083 */ 'b', 'r', 'l', 'z', 32, 0, /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0, /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0, /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0, /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0, /* 2127 */ 'b', 'r', 'n', 'z', 32, 0, /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0, /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0, /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0, /* 2160 */ 'b', 'r', 'z', 32, 0, /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0, /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0, /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0, /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0, /* 2421 */ 't', 'a', 32, '3', 0, /* 2426 */ 't', 'a', 32, '5', 0, /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0, /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0, /* 2490 */ 'l', 'd', 'd', 32, '[', 0, /* 2496 */ 'l', 'd', 32, '[', 0, /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0, /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0, /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0, /* 2522 */ 'l', 'd', 'q', 32, '[', 0, /* 2528 */ 'c', 'a', 's', 32, '[', 0, /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0, /* 2541 */ 'l', 'd', 'x', 32, '[', 0, /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0, /* 2554 */ 'f', 'b', 0, /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0, /* 2563 */ 's', 'i', 'a', 'm', 0, /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0, /* 2577 */ 'n', 'o', 'p', 0, /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0, /* 2587 */ 's', 't', 'b', 'a', 'r', 0, /* 2593 */ 'f', 'm', 'o', 'v', 's', 0, /* 2599 */ 't', 0, /* 2601 */ 'm', 'o', 'v', 0, /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0, }; #endif // Emit the opcode for the instruction. uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; #ifndef CAPSTONE_DIET // assert(Bits != 0 && "Cannot print this instruction."); SStream_concat0(O, AsmStrs+(Bits & 4095)-1); #endif // Fragment 0 encoded into 4 bits for 12 unique commands. // printf("Frag-0: %u\n", (Bits >> 12) & 15); switch ((Bits >> 12) & 15) { default: // unreachable. case 0: // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C... return; break; case 1: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... printOperand(MI, 1, O); break; case 2: // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B... printOperand(MI, 0, O); break; case 3: // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA... printCCOperand(MI, 1, O); break; case 4: // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr printMemOperand(MI, 0, O, NULL); return; break; case 5: // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV... printCCOperand(MI, 3, O); break; case 6: // GETPCX printGetPCX(MI, 0, O); return; break; case 7: // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ... printMemOperand(MI, 1, O, NULL); break; case 8: // LEAX_ADDri, LEA_ADDri printMemOperand(MI, 1, O, "arith"); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 9: // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF... printOperand(MI, 2, O); SStream_concat0(O, ", ["); printMemOperand(MI, 0, O, NULL); SStream_concat0(O, "]"); return; break; case 10: // TICCri, TICCrr, TXCCri, TXCCrr printCCOperand(MI, 2, O); break; case 11: // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr printCCOperand(MI, 4, O); SStream_concat0(O, " "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; } // Fragment 1 encoded into 4 bits for 16 unique commands. // printf("Frag-1: %u\n", (Bits >> 16) & 15); switch ((Bits >> 16) & 15) { default: // unreachable. case 0: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... SStream_concat0(O, ", "); break; case 1: // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ... return; break; case 2: // BCOND, BPFCC, FBCOND SStream_concat0(O, " "); break; case 3: // BCONDA, BPFCCA, FBCONDA SStream_concat0(O, ",a "); Sparc_add_hint(MI, SPARC_HINT_A); break; case 4: // BPFCCANT SStream_concat0(O, ",a,pn "); Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 5: // BPFCCNT SStream_concat0(O, ",pn "); Sparc_add_hint(MI, SPARC_HINT_PN); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 6: // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI... SStream_concat0(O, " %icc, "); Sparc_add_reg(MI, SPARC_REG_ICC); break; case 7: // BPICCA SStream_concat0(O, ",a %icc, "); Sparc_add_hint(MI, SPARC_HINT_A); Sparc_add_reg(MI, SPARC_REG_ICC); printOperand(MI, 0, O); return; break; case 8: // BPICCANT SStream_concat0(O, ",a,pn %icc, "); Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); Sparc_add_reg(MI, SPARC_REG_ICC); printOperand(MI, 0, O); return; break; case 9: // BPICCNT SStream_concat0(O, ",pn %icc, "); Sparc_add_hint(MI, SPARC_HINT_PN); Sparc_add_reg(MI, SPARC_REG_ICC); printOperand(MI, 0, O); return; break; case 10: // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX... SStream_concat0(O, " %xcc, "); Sparc_add_reg(MI, SPARC_REG_XCC); break; case 11: // BPXCCA SStream_concat0(O, ",a %xcc, "); Sparc_add_hint(MI, SPARC_HINT_A); Sparc_add_reg(MI, SPARC_REG_XCC); printOperand(MI, 0, O); return; break; case 12: // BPXCCANT SStream_concat0(O, ",a,pn %xcc, "); Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN); Sparc_add_reg(MI, SPARC_REG_XCC); printOperand(MI, 0, O); return; break; case 13: // BPXCCNT SStream_concat0(O, ",pn %xcc, "); Sparc_add_hint(MI, SPARC_HINT_PN); Sparc_add_reg(MI, SPARC_REG_XCC); printOperand(MI, 0, O); return; break; case 14: // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L... SStream_concat0(O, "], "); break; case 15: // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr SStream_concat0(O, " %fcc0, "); Sparc_add_reg(MI, SPARC_REG_FCC0); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; } // Fragment 2 encoded into 2 bits for 3 unique commands. // printf("Frag-2: %u\n", (Bits >> 20) & 3); switch ((Bits >> 20) & 3) { default: // unreachable. case 0: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); break; case 1: // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT... printOperand(MI, 0, O); break; case 2: // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ... printOperand(MI, 1, O); break; } // Fragment 3 encoded into 2 bits for 4 unique commands. // printf("Frag-3: %u\n", (Bits >> 22) & 3); switch ((Bits >> 22) & 3) { default: // unreachable. case 0: // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX... return; break; case 1: // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,... SStream_concat0(O, ", "); break; case 2: // TICCri, TICCrr, TXCCri, TXCCrr SStream_concat0(O, " + "); // qq printOperand(MI, 1, O); return; break; case 3: // WRYri, WRYrr SStream_concat0(O, ", %y"); Sparc_add_reg(MI, SPARC_REG_Y); return; break; } // Fragment 4 encoded into 2 bits for 3 unique commands. // printf("Frag-4: %u\n", (Bits >> 24) & 3); switch ((Bits >> 24) & 3) { default: // unreachable. case 0: // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP... printOperand(MI, 2, O); return; break; case 1: // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI... printOperand(MI, 0, O); return; break; case 2: // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr printOperand(MI, 3, O); return; break; } } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 119 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'f', '1', '0', 0, /* 4 */ 'f', '2', '0', 0, /* 8 */ 'f', '3', '0', 0, /* 12 */ 'f', '4', '0', 0, /* 16 */ 'f', '5', '0', 0, /* 20 */ 'f', '6', '0', 0, /* 24 */ 'f', 'c', 'c', '0', 0, /* 29 */ 'f', '0', 0, /* 32 */ 'g', '0', 0, /* 35 */ 'i', '0', 0, /* 38 */ 'l', '0', 0, /* 41 */ 'o', '0', 0, /* 44 */ 'f', '1', '1', 0, /* 48 */ 'f', '2', '1', 0, /* 52 */ 'f', '3', '1', 0, /* 56 */ 'f', 'c', 'c', '1', 0, /* 61 */ 'f', '1', 0, /* 64 */ 'g', '1', 0, /* 67 */ 'i', '1', 0, /* 70 */ 'l', '1', 0, /* 73 */ 'o', '1', 0, /* 76 */ 'f', '1', '2', 0, /* 80 */ 'f', '2', '2', 0, /* 84 */ 'f', '3', '2', 0, /* 88 */ 'f', '4', '2', 0, /* 92 */ 'f', '5', '2', 0, /* 96 */ 'f', '6', '2', 0, /* 100 */ 'f', 'c', 'c', '2', 0, /* 105 */ 'f', '2', 0, /* 108 */ 'g', '2', 0, /* 111 */ 'i', '2', 0, /* 114 */ 'l', '2', 0, /* 117 */ 'o', '2', 0, /* 120 */ 'f', '1', '3', 0, /* 124 */ 'f', '2', '3', 0, /* 128 */ 'f', 'c', 'c', '3', 0, /* 133 */ 'f', '3', 0, /* 136 */ 'g', '3', 0, /* 139 */ 'i', '3', 0, /* 142 */ 'l', '3', 0, /* 145 */ 'o', '3', 0, /* 148 */ 'f', '1', '4', 0, /* 152 */ 'f', '2', '4', 0, /* 156 */ 'f', '3', '4', 0, /* 160 */ 'f', '4', '4', 0, /* 164 */ 'f', '5', '4', 0, /* 168 */ 'f', '4', 0, /* 171 */ 'g', '4', 0, /* 174 */ 'i', '4', 0, /* 177 */ 'l', '4', 0, /* 180 */ 'o', '4', 0, /* 183 */ 'f', '1', '5', 0, /* 187 */ 'f', '2', '5', 0, /* 191 */ 'f', '5', 0, /* 194 */ 'g', '5', 0, /* 197 */ 'i', '5', 0, /* 200 */ 'l', '5', 0, /* 203 */ 'o', '5', 0, /* 206 */ 'f', '1', '6', 0, /* 210 */ 'f', '2', '6', 0, /* 214 */ 'f', '3', '6', 0, /* 218 */ 'f', '4', '6', 0, /* 222 */ 'f', '5', '6', 0, /* 226 */ 'f', '6', 0, /* 229 */ 'g', '6', 0, /* 232 */ 'l', '6', 0, /* 235 */ 'f', '1', '7', 0, /* 239 */ 'f', '2', '7', 0, /* 243 */ 'f', '7', 0, /* 246 */ 'g', '7', 0, /* 249 */ 'i', '7', 0, /* 252 */ 'l', '7', 0, /* 255 */ 'o', '7', 0, /* 258 */ 'f', '1', '8', 0, /* 262 */ 'f', '2', '8', 0, /* 266 */ 'f', '3', '8', 0, /* 270 */ 'f', '4', '8', 0, /* 274 */ 'f', '5', '8', 0, /* 278 */ 'f', '8', 0, /* 281 */ 'f', '1', '9', 0, /* 285 */ 'f', '2', '9', 0, /* 289 */ 'f', '9', 0, /* 292 */ 'i', 'c', 'c', 0, /* 296 */ 'f', 'p', 0, /* 299 */ 's', 'p', 0, /* 302 */ 'y', 0, }; static const uint16_t RegAsmOffset[] = { 292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80, 152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16, 92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243, 278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48, 80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128, 32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197, 296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145, 180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214, 12, 160, 270, 92, 222, 20, }; //int i; //for (i = 0; i < sizeof(RegAsmOffset)/2; i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); //printf("*************************\n"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS) { } static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) { #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) const char *AsmString; char *tmp, *AsmMnem, *AsmOps, *c; int OpIdx, PrintMethodIdx; MCRegisterInfo *MRI = (MCRegisterInfo *)info; switch (MCInst_getOpcode(MI)) { default: return NULL; case SP_BCOND: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { // (BCOND brtarget:$imm, 8) AsmString = "ba $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BCOND brtarget:$imm, 0) AsmString = "bn $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { // (BCOND brtarget:$imm, 9) AsmString = "bne $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (BCOND brtarget:$imm, 1) AsmString = "be $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { // (BCOND brtarget:$imm, 10) AsmString = "bg $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (BCOND brtarget:$imm, 2) AsmString = "ble $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { // (BCOND brtarget:$imm, 11) AsmString = "bge $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { // (BCOND brtarget:$imm, 3) AsmString = "bl $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { // (BCOND brtarget:$imm, 12) AsmString = "bgu $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (BCOND brtarget:$imm, 4) AsmString = "bleu $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { // (BCOND brtarget:$imm, 13) AsmString = "bcc $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (BCOND brtarget:$imm, 5) AsmString = "bcs $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { // (BCOND brtarget:$imm, 14) AsmString = "bpos $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { // (BCOND brtarget:$imm, 6) AsmString = "bneg $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (BCOND brtarget:$imm, 15) AsmString = "bvc $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { // (BCOND brtarget:$imm, 7) AsmString = "bvs $\x01"; break; } return NULL; case SP_BCONDA: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { // (BCONDA brtarget:$imm, 8) AsmString = "ba,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BCONDA brtarget:$imm, 0) AsmString = "bn,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { // (BCONDA brtarget:$imm, 9) AsmString = "bne,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (BCONDA brtarget:$imm, 1) AsmString = "be,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { // (BCONDA brtarget:$imm, 10) AsmString = "bg,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (BCONDA brtarget:$imm, 2) AsmString = "ble,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { // (BCONDA brtarget:$imm, 11) AsmString = "bge,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { // (BCONDA brtarget:$imm, 3) AsmString = "bl,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { // (BCONDA brtarget:$imm, 12) AsmString = "bgu,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (BCONDA brtarget:$imm, 4) AsmString = "bleu,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { // (BCONDA brtarget:$imm, 13) AsmString = "bcc,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (BCONDA brtarget:$imm, 5) AsmString = "bcs,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { // (BCONDA brtarget:$imm, 14) AsmString = "bpos,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { // (BCONDA brtarget:$imm, 6) AsmString = "bneg,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (BCONDA brtarget:$imm, 15) AsmString = "bvc,a $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { // (BCONDA brtarget:$imm, 7) AsmString = "bvs,a $\x01"; break; } return NULL; case SP_BPFCCANT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) AsmString = "fba,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) AsmString = "fbn,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) AsmString = "fbu,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) AsmString = "fbg,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) AsmString = "fbug,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) AsmString = "fbl,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) AsmString = "fbul,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) AsmString = "fblg,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) AsmString = "fbne,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) AsmString = "fbe,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) AsmString = "fbue,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) AsmString = "fbge,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) AsmString = "fbuge,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) AsmString = "fble,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) AsmString = "fbule,a,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) AsmString = "fbo,a,pn $\x03, $\x01"; break; } return NULL; case SP_BPFCCNT: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) AsmString = "fba,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) AsmString = "fbn,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) AsmString = "fbu,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) AsmString = "fbg,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) AsmString = "fbug,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) AsmString = "fbl,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) AsmString = "fbul,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) AsmString = "fblg,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) AsmString = "fbne,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) AsmString = "fbe,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) AsmString = "fbue,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) AsmString = "fbge,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) AsmString = "fbuge,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) AsmString = "fble,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) AsmString = "fbule,pn $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) { // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) AsmString = "fbo,pn $\x03, $\x01"; break; } return NULL; case SP_BPICCANT: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { // (BPICCANT brtarget:$imm, 8) AsmString = "ba,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BPICCANT brtarget:$imm, 0) AsmString = "bn,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { // (BPICCANT brtarget:$imm, 9) AsmString = "bne,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (BPICCANT brtarget:$imm, 1) AsmString = "be,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { // (BPICCANT brtarget:$imm, 10) AsmString = "bg,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (BPICCANT brtarget:$imm, 2) AsmString = "ble,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { // (BPICCANT brtarget:$imm, 11) AsmString = "bge,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { // (BPICCANT brtarget:$imm, 3) AsmString = "bl,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { // (BPICCANT brtarget:$imm, 12) AsmString = "bgu,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (BPICCANT brtarget:$imm, 4) AsmString = "bleu,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { // (BPICCANT brtarget:$imm, 13) AsmString = "bcc,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (BPICCANT brtarget:$imm, 5) AsmString = "bcs,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { // (BPICCANT brtarget:$imm, 14) AsmString = "bpos,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { // (BPICCANT brtarget:$imm, 6) AsmString = "bneg,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (BPICCANT brtarget:$imm, 15) AsmString = "bvc,a,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { // (BPICCANT brtarget:$imm, 7) AsmString = "bvs,a,pn %icc, $\x01"; break; } return NULL; case SP_BPICCNT: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { // (BPICCNT brtarget:$imm, 8) AsmString = "ba,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BPICCNT brtarget:$imm, 0) AsmString = "bn,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { // (BPICCNT brtarget:$imm, 9) AsmString = "bne,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (BPICCNT brtarget:$imm, 1) AsmString = "be,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { // (BPICCNT brtarget:$imm, 10) AsmString = "bg,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (BPICCNT brtarget:$imm, 2) AsmString = "ble,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { // (BPICCNT brtarget:$imm, 11) AsmString = "bge,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { // (BPICCNT brtarget:$imm, 3) AsmString = "bl,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { // (BPICCNT brtarget:$imm, 12) AsmString = "bgu,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (BPICCNT brtarget:$imm, 4) AsmString = "bleu,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { // (BPICCNT brtarget:$imm, 13) AsmString = "bcc,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (BPICCNT brtarget:$imm, 5) AsmString = "bcs,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { // (BPICCNT brtarget:$imm, 14) AsmString = "bpos,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { // (BPICCNT brtarget:$imm, 6) AsmString = "bneg,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (BPICCNT brtarget:$imm, 15) AsmString = "bvc,pn %icc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { // (BPICCNT brtarget:$imm, 7) AsmString = "bvs,pn %icc, $\x01"; break; } return NULL; case SP_BPXCCANT: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { // (BPXCCANT brtarget:$imm, 8) AsmString = "ba,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BPXCCANT brtarget:$imm, 0) AsmString = "bn,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { // (BPXCCANT brtarget:$imm, 9) AsmString = "bne,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (BPXCCANT brtarget:$imm, 1) AsmString = "be,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { // (BPXCCANT brtarget:$imm, 10) AsmString = "bg,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (BPXCCANT brtarget:$imm, 2) AsmString = "ble,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { // (BPXCCANT brtarget:$imm, 11) AsmString = "bge,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { // (BPXCCANT brtarget:$imm, 3) AsmString = "bl,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { // (BPXCCANT brtarget:$imm, 12) AsmString = "bgu,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (BPXCCANT brtarget:$imm, 4) AsmString = "bleu,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { // (BPXCCANT brtarget:$imm, 13) AsmString = "bcc,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (BPXCCANT brtarget:$imm, 5) AsmString = "bcs,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { // (BPXCCANT brtarget:$imm, 14) AsmString = "bpos,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { // (BPXCCANT brtarget:$imm, 6) AsmString = "bneg,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (BPXCCANT brtarget:$imm, 15) AsmString = "bvc,a,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { // (BPXCCANT brtarget:$imm, 7) AsmString = "bvs,a,pn %xcc, $\x01"; break; } return NULL; case SP_BPXCCNT: if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) { // (BPXCCNT brtarget:$imm, 8) AsmString = "ba,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { // (BPXCCNT brtarget:$imm, 0) AsmString = "bn,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) { // (BPXCCNT brtarget:$imm, 9) AsmString = "bne,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { // (BPXCCNT brtarget:$imm, 1) AsmString = "be,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) { // (BPXCCNT brtarget:$imm, 10) AsmString = "bg,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { // (BPXCCNT brtarget:$imm, 2) AsmString = "ble,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) { // (BPXCCNT brtarget:$imm, 11) AsmString = "bge,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) { // (BPXCCNT brtarget:$imm, 3) AsmString = "bl,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) { // (BPXCCNT brtarget:$imm, 12) AsmString = "bgu,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) { // (BPXCCNT brtarget:$imm, 4) AsmString = "bleu,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) { // (BPXCCNT brtarget:$imm, 13) AsmString = "bcc,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) { // (BPXCCNT brtarget:$imm, 5) AsmString = "bcs,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) { // (BPXCCNT brtarget:$imm, 14) AsmString = "bpos,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) { // (BPXCCNT brtarget:$imm, 6) AsmString = "bneg,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { // (BPXCCNT brtarget:$imm, 15) AsmString = "bvc,pn %xcc, $\x01"; break; } if (MCInst_getNumOperands(MI) == 2 && MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) { // (BPXCCNT brtarget:$imm, 7) AsmString = "bvs,pn %xcc, $\x01"; break; } return NULL; case SP_FMOVD_ICC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) AsmString = "fmovda %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) AsmString = "fmovdn %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) AsmString = "fmovdne %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) AsmString = "fmovde %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) AsmString = "fmovdg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) AsmString = "fmovdle %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) AsmString = "fmovdge %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) AsmString = "fmovdl %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) AsmString = "fmovdgu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) AsmString = "fmovdleu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) AsmString = "fmovdcc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) AsmString = "fmovdcs %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) AsmString = "fmovdpos %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) AsmString = "fmovdneg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) AsmString = "fmovdvc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) AsmString = "fmovdvs %icc, $\x02, $\x01"; break; } return NULL; case SP_FMOVD_XCC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) AsmString = "fmovda %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) AsmString = "fmovdn %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) AsmString = "fmovdne %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) AsmString = "fmovde %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) AsmString = "fmovdg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) AsmString = "fmovdle %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) AsmString = "fmovdge %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) AsmString = "fmovdl %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) AsmString = "fmovdgu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) AsmString = "fmovdleu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) AsmString = "fmovdcc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) AsmString = "fmovdcs %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) AsmString = "fmovdpos %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) AsmString = "fmovdneg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) AsmString = "fmovdvc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) AsmString = "fmovdvs %xcc, $\x02, $\x01"; break; } return NULL; case SP_FMOVQ_ICC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) AsmString = "fmovqa %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) AsmString = "fmovqn %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) AsmString = "fmovqne %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) AsmString = "fmovqe %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) AsmString = "fmovqg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) AsmString = "fmovqle %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) AsmString = "fmovqge %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) AsmString = "fmovql %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) AsmString = "fmovqgu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) AsmString = "fmovqleu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) AsmString = "fmovqcc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) AsmString = "fmovqcs %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) AsmString = "fmovqpos %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) AsmString = "fmovqneg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) AsmString = "fmovqvc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) AsmString = "fmovqvs %icc, $\x02, $\x01"; break; } return NULL; case SP_FMOVQ_XCC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) AsmString = "fmovqa %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) AsmString = "fmovqn %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) AsmString = "fmovqne %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) AsmString = "fmovqe %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) AsmString = "fmovqg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) AsmString = "fmovqle %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) AsmString = "fmovqge %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) AsmString = "fmovql %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) AsmString = "fmovqgu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) AsmString = "fmovqleu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) AsmString = "fmovqcc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) AsmString = "fmovqcs %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) AsmString = "fmovqpos %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) AsmString = "fmovqneg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) AsmString = "fmovqvc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) AsmString = "fmovqvs %xcc, $\x02, $\x01"; break; } return NULL; case SP_FMOVS_ICC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) AsmString = "fmovsa %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) AsmString = "fmovsn %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) AsmString = "fmovsne %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) AsmString = "fmovse %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) AsmString = "fmovsg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) AsmString = "fmovsle %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) AsmString = "fmovsge %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) AsmString = "fmovsl %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) AsmString = "fmovsgu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) AsmString = "fmovsleu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) AsmString = "fmovscc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) AsmString = "fmovscs %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) AsmString = "fmovspos %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) AsmString = "fmovsneg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) AsmString = "fmovsvc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) AsmString = "fmovsvs %icc, $\x02, $\x01"; break; } return NULL; case SP_FMOVS_XCC: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) AsmString = "fmovsa %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) AsmString = "fmovsn %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) AsmString = "fmovsne %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) AsmString = "fmovse %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) AsmString = "fmovsg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) AsmString = "fmovsle %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) AsmString = "fmovsge %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) AsmString = "fmovsl %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) AsmString = "fmovsgu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) AsmString = "fmovsleu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) AsmString = "fmovscc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) AsmString = "fmovscs %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) AsmString = "fmovspos %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) AsmString = "fmovsneg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) AsmString = "fmovsvc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) AsmString = "fmovsvs %xcc, $\x02, $\x01"; break; } return NULL; case SP_MOVICCri: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) AsmString = "mova %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) AsmString = "movn %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) AsmString = "movne %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) AsmString = "move %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) AsmString = "movg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) AsmString = "movle %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) AsmString = "movge %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) AsmString = "movl %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) AsmString = "movgu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) AsmString = "movleu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) AsmString = "movcc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) AsmString = "movcs %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) AsmString = "movpos %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) AsmString = "movneg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) AsmString = "movvc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) AsmString = "movvs %icc, $\x02, $\x01"; break; } return NULL; case SP_MOVICCrr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) AsmString = "mova %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) AsmString = "movn %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) AsmString = "movne %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) AsmString = "move %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) AsmString = "movg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) AsmString = "movle %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) AsmString = "movge %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) AsmString = "movl %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) AsmString = "movgu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) AsmString = "movleu %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) AsmString = "movcc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) AsmString = "movcs %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) AsmString = "movpos %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) AsmString = "movneg %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) AsmString = "movvc %icc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) AsmString = "movvs %icc, $\x02, $\x01"; break; } return NULL; case SP_MOVXCCri: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) AsmString = "mova %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) AsmString = "movn %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) AsmString = "movne %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) AsmString = "move %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) AsmString = "movg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) AsmString = "movle %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) AsmString = "movge %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) AsmString = "movl %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) AsmString = "movgu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) AsmString = "movleu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) AsmString = "movcc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) AsmString = "movcs %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) AsmString = "movpos %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) AsmString = "movneg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) AsmString = "movvc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) AsmString = "movvs %xcc, $\x02, $\x01"; break; } return NULL; case SP_MOVXCCrr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) AsmString = "mova %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) AsmString = "movn %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) AsmString = "movne %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) AsmString = "move %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) AsmString = "movg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) AsmString = "movle %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) AsmString = "movge %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) AsmString = "movl %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) AsmString = "movgu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) AsmString = "movleu %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) AsmString = "movcc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) AsmString = "movcs %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) AsmString = "movpos %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) AsmString = "movneg %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) AsmString = "movvc %xcc, $\x02, $\x01"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) AsmString = "movvs %xcc, $\x02, $\x01"; break; } return NULL; case SP_ORri: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) { // (ORri IntRegs:$rd, G0, i32imm:$simm13) AsmString = "mov $\x03, $\x01"; break; } return NULL; case SP_ORrr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) { // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) AsmString = "mov $\x03, $\x01"; break; } return NULL; case SP_RESTORErr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 && MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) { // (RESTORErr G0, G0, G0) AsmString = "restore"; break; } return NULL; case SP_RET: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { // (RET 8) AsmString = "ret"; break; } return NULL; case SP_RETL: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) { // (RETL 8) AsmString = "retl"; break; } return NULL; case SP_TXCCri: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) AsmString = "ta %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (TXCCri G0, i32imm:$imm, 8) AsmString = "ta %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) AsmString = "tn %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TXCCri G0, i32imm:$imm, 0) AsmString = "tn %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) AsmString = "tne %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (TXCCri G0, i32imm:$imm, 9) AsmString = "tne %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) AsmString = "te %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (TXCCri G0, i32imm:$imm, 1) AsmString = "te %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) AsmString = "tg %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (TXCCri G0, i32imm:$imm, 10) AsmString = "tg %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) AsmString = "tle %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (TXCCri G0, i32imm:$imm, 2) AsmString = "tle %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) AsmString = "tge %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (TXCCri G0, i32imm:$imm, 11) AsmString = "tge %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) AsmString = "tl %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (TXCCri G0, i32imm:$imm, 3) AsmString = "tl %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) AsmString = "tgu %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (TXCCri G0, i32imm:$imm, 12) AsmString = "tgu %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) AsmString = "tleu %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (TXCCri G0, i32imm:$imm, 4) AsmString = "tleu %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) AsmString = "tcc %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (TXCCri G0, i32imm:$imm, 13) AsmString = "tcc %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) AsmString = "tcs %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (TXCCri G0, i32imm:$imm, 5) AsmString = "tcs %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) AsmString = "tpos %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (TXCCri G0, i32imm:$imm, 14) AsmString = "tpos %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) AsmString = "tneg %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (TXCCri G0, i32imm:$imm, 6) AsmString = "tneg %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) AsmString = "tvc %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (TXCCri G0, i32imm:$imm, 15) AsmString = "tvc %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) AsmString = "tvs %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (TXCCri G0, i32imm:$imm, 7) AsmString = "tvs %xcc, $\x02"; break; } return NULL; case SP_TXCCrr: if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) AsmString = "ta %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { // (TXCCrr G0, IntRegs:$rs2, 8) AsmString = "ta %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) AsmString = "tn %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (TXCCrr G0, IntRegs:$rs2, 0) AsmString = "tn %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) AsmString = "tne %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) { // (TXCCrr G0, IntRegs:$rs2, 9) AsmString = "tne %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) AsmString = "te %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { // (TXCCrr G0, IntRegs:$rs2, 1) AsmString = "te %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) AsmString = "tg %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) { // (TXCCrr G0, IntRegs:$rs2, 10) AsmString = "tg %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) AsmString = "tle %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) { // (TXCCrr G0, IntRegs:$rs2, 2) AsmString = "tle %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) AsmString = "tge %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) { // (TXCCrr G0, IntRegs:$rs2, 11) AsmString = "tge %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) AsmString = "tl %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) { // (TXCCrr G0, IntRegs:$rs2, 3) AsmString = "tl %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) AsmString = "tgu %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) { // (TXCCrr G0, IntRegs:$rs2, 12) AsmString = "tgu %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) AsmString = "tleu %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) { // (TXCCrr G0, IntRegs:$rs2, 4) AsmString = "tleu %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) AsmString = "tcc %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) { // (TXCCrr G0, IntRegs:$rs2, 13) AsmString = "tcc %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) AsmString = "tcs %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) { // (TXCCrr G0, IntRegs:$rs2, 5) AsmString = "tcs %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) AsmString = "tpos %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) { // (TXCCrr G0, IntRegs:$rs2, 14) AsmString = "tpos %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) AsmString = "tneg %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) { // (TXCCrr G0, IntRegs:$rs2, 6) AsmString = "tneg %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) AsmString = "tvc %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) { // (TXCCrr G0, IntRegs:$rs2, 15) AsmString = "tvc %xcc, $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) AsmString = "tvs %xcc, $\x01 + $\x02"; break; } if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { // (TXCCrr G0, IntRegs:$rs2, 7) AsmString = "tvs %xcc, $\x02"; break; } return NULL; case SP_V9FCMPD: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) { // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) AsmString = "fcmpd $\x02, $\x03"; break; } return NULL; case SP_V9FCMPED: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) { // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) AsmString = "fcmped $\x02, $\x03"; break; } return NULL; case SP_V9FCMPEQ: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) { // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) AsmString = "fcmpeq $\x02, $\x03"; break; } return NULL; case SP_V9FCMPES: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) { // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) AsmString = "fcmpes $\x02, $\x03"; break; } return NULL; case SP_V9FCMPQ: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) { // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) AsmString = "fcmpq $\x02, $\x03"; break; } return NULL; case SP_V9FCMPS: if (MCInst_getNumOperands(MI) == 3 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) { // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) AsmString = "fcmps $\x02, $\x03"; break; } return NULL; case SP_V9FMOVD_FCC: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) AsmString = "fmovda $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) AsmString = "fmovdn $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) AsmString = "fmovdu $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) AsmString = "fmovdg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) AsmString = "fmovdug $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) AsmString = "fmovdl $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) AsmString = "fmovdul $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) AsmString = "fmovdlg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) AsmString = "fmovdne $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) AsmString = "fmovde $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) AsmString = "fmovdue $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) AsmString = "fmovdge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) AsmString = "fmovduge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) AsmString = "fmovdle $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) AsmString = "fmovdule $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) AsmString = "fmovdo $\x02, $\x03, $\x01"; break; } return NULL; case SP_V9FMOVQ_FCC: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) AsmString = "fmovqa $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) AsmString = "fmovqn $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) AsmString = "fmovqu $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) AsmString = "fmovqg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) AsmString = "fmovqug $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) AsmString = "fmovql $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) AsmString = "fmovqul $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) AsmString = "fmovqlg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) AsmString = "fmovqne $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) AsmString = "fmovqe $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) AsmString = "fmovque $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) AsmString = "fmovqge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) AsmString = "fmovquge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) AsmString = "fmovqle $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) AsmString = "fmovqule $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) AsmString = "fmovqo $\x02, $\x03, $\x01"; break; } return NULL; case SP_V9FMOVS_FCC: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) AsmString = "fmovsa $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) AsmString = "fmovsn $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) AsmString = "fmovsu $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) AsmString = "fmovsg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) AsmString = "fmovsug $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) AsmString = "fmovsl $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) AsmString = "fmovsul $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) AsmString = "fmovslg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) AsmString = "fmovsne $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) AsmString = "fmovse $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) AsmString = "fmovsue $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) AsmString = "fmovsge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) AsmString = "fmovsuge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) AsmString = "fmovsle $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) AsmString = "fmovsule $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) AsmString = "fmovso $\x02, $\x03, $\x01"; break; } return NULL; case SP_V9MOVFCCri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) AsmString = "mova $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) AsmString = "movn $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) AsmString = "movu $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) AsmString = "movg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) AsmString = "movug $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) AsmString = "movl $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) AsmString = "movul $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) AsmString = "movlg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) AsmString = "movne $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) AsmString = "move $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) AsmString = "movue $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) AsmString = "movge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) AsmString = "movuge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) AsmString = "movle $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) AsmString = "movule $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) AsmString = "movo $\x02, $\x03, $\x01"; break; } return NULL; case SP_V9MOVFCCrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) AsmString = "mova $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) AsmString = "movn $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) AsmString = "movu $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) AsmString = "movg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) AsmString = "movug $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) AsmString = "movl $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) AsmString = "movul $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) AsmString = "movlg $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) AsmString = "movne $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) AsmString = "move $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) AsmString = "movue $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) AsmString = "movge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) AsmString = "movuge $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) AsmString = "movle $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) AsmString = "movule $\x02, $\x03, $\x01"; break; } if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) AsmString = "movo $\x02, $\x03, $\x01"; break; } return NULL; } tmp = cs_strdup(AsmString); AsmMnem = tmp; for(AsmOps = tmp; *AsmOps; AsmOps++) { if (*AsmOps == ' ' || *AsmOps == '\t') { *AsmOps = '\0'; AsmOps++; break; } } SStream_concat0(OS, AsmMnem); if (*AsmOps) { SStream_concat0(OS, "\t"); if (strstr(AsmOps, "icc")) Sparc_addReg(MI, SPARC_REG_ICC); if (strstr(AsmOps, "xcc")) Sparc_addReg(MI, SPARC_REG_XCC); for (c = AsmOps; *c; c++) { if (*c == '$') { c += 1; if (*c == (char)0xff) { c += 1; OpIdx = *c - 1; c += 1; PrintMethodIdx = *c - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, *c - 1, OS); } else { SStream_concat(OS, "%c", *c); } } } return tmp; } #endif // PRINT_ALIAS_INSTR capstone-sys-0.15.0/capstone/arch/Sparc/SparcGenDisassemblerTables.inc000064400000000000000000003471430072674642500240720ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * Sparc Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTableSparc32[] = { /* 0 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... /* 3 */ MCD_OPC_FilterValue, 0, 13, 2, // Skip to: 532 /* 7 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... /* 10 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 24 /* 14 */ MCD_OPC_CheckField, 25, 5, 0, 163, 22, // Skip to: 5815 /* 20 */ MCD_OPC_Decode, 211, 3, 0, // Opcode: UNIMP /* 24 */ MCD_OPC_FilterValue, 1, 103, 0, // Skip to: 131 /* 28 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... /* 31 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 60 /* 35 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 38 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 49 /* 42 */ MCD_OPC_CheckPredicate, 0, 137, 22, // Skip to: 5815 /* 46 */ MCD_OPC_Decode, 94, 1, // Opcode: BPICCNT /* 49 */ MCD_OPC_FilterValue, 1, 130, 22, // Skip to: 5815 /* 53 */ MCD_OPC_CheckPredicate, 0, 126, 22, // Skip to: 5815 /* 57 */ MCD_OPC_Decode, 93, 1, // Opcode: BPICCANT /* 60 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 89 /* 64 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 67 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 78 /* 71 */ MCD_OPC_CheckPredicate, 0, 108, 22, // Skip to: 5815 /* 75 */ MCD_OPC_Decode, 91, 1, // Opcode: BPICC /* 78 */ MCD_OPC_FilterValue, 1, 101, 22, // Skip to: 5815 /* 82 */ MCD_OPC_CheckPredicate, 0, 97, 22, // Skip to: 5815 /* 86 */ MCD_OPC_Decode, 92, 1, // Opcode: BPICCA /* 89 */ MCD_OPC_FilterValue, 4, 17, 0, // Skip to: 110 /* 93 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 96 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 103 /* 100 */ MCD_OPC_Decode, 110, 1, // Opcode: BPXCCNT /* 103 */ MCD_OPC_FilterValue, 1, 76, 22, // Skip to: 5815 /* 107 */ MCD_OPC_Decode, 109, 1, // Opcode: BPXCCANT /* 110 */ MCD_OPC_FilterValue, 5, 69, 22, // Skip to: 5815 /* 114 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 117 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 124 /* 121 */ MCD_OPC_Decode, 107, 1, // Opcode: BPXCC /* 124 */ MCD_OPC_FilterValue, 1, 55, 22, // Skip to: 5815 /* 128 */ MCD_OPC_Decode, 108, 1, // Opcode: BPXCCA /* 131 */ MCD_OPC_FilterValue, 2, 26, 0, // Skip to: 161 /* 135 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 138 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 154 /* 142 */ MCD_OPC_CheckField, 25, 4, 8, 3, 0, // Skip to: 151 /* 148 */ MCD_OPC_Decode, 73, 0, // Opcode: BA /* 151 */ MCD_OPC_Decode, 74, 2, // Opcode: BCOND /* 154 */ MCD_OPC_FilterValue, 1, 25, 22, // Skip to: 5815 /* 158 */ MCD_OPC_Decode, 75, 2, // Opcode: BCONDA /* 161 */ MCD_OPC_FilterValue, 3, 255, 0, // Skip to: 420 /* 165 */ MCD_OPC_ExtractField, 25, 5, // Inst{29-25} ... /* 168 */ MCD_OPC_FilterValue, 1, 17, 0, // Skip to: 189 /* 172 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 175 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 182 /* 179 */ MCD_OPC_Decode, 113, 3, // Opcode: BPZnapn /* 182 */ MCD_OPC_FilterValue, 1, 253, 21, // Skip to: 5815 /* 186 */ MCD_OPC_Decode, 114, 3, // Opcode: BPZnapt /* 189 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 210 /* 193 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 196 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 203 /* 200 */ MCD_OPC_Decode, 97, 3, // Opcode: BPLEZnapn /* 203 */ MCD_OPC_FilterValue, 1, 232, 21, // Skip to: 5815 /* 207 */ MCD_OPC_Decode, 98, 3, // Opcode: BPLEZnapt /* 210 */ MCD_OPC_FilterValue, 3, 17, 0, // Skip to: 231 /* 214 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 217 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 224 /* 221 */ MCD_OPC_Decode, 101, 3, // Opcode: BPLZnapn /* 224 */ MCD_OPC_FilterValue, 1, 211, 21, // Skip to: 5815 /* 228 */ MCD_OPC_Decode, 102, 3, // Opcode: BPLZnapt /* 231 */ MCD_OPC_FilterValue, 5, 17, 0, // Skip to: 252 /* 235 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 238 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 245 /* 242 */ MCD_OPC_Decode, 105, 3, // Opcode: BPNZnapn /* 245 */ MCD_OPC_FilterValue, 1, 190, 21, // Skip to: 5815 /* 249 */ MCD_OPC_Decode, 106, 3, // Opcode: BPNZnapt /* 252 */ MCD_OPC_FilterValue, 6, 17, 0, // Skip to: 273 /* 256 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 259 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 266 /* 263 */ MCD_OPC_Decode, 89, 3, // Opcode: BPGZnapn /* 266 */ MCD_OPC_FilterValue, 1, 169, 21, // Skip to: 5815 /* 270 */ MCD_OPC_Decode, 90, 3, // Opcode: BPGZnapt /* 273 */ MCD_OPC_FilterValue, 7, 17, 0, // Skip to: 294 /* 277 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 280 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 287 /* 284 */ MCD_OPC_Decode, 85, 3, // Opcode: BPGEZnapn /* 287 */ MCD_OPC_FilterValue, 1, 148, 21, // Skip to: 5815 /* 291 */ MCD_OPC_Decode, 86, 3, // Opcode: BPGEZnapt /* 294 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 315 /* 298 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 301 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 308 /* 305 */ MCD_OPC_Decode, 111, 3, // Opcode: BPZapn /* 308 */ MCD_OPC_FilterValue, 1, 127, 21, // Skip to: 5815 /* 312 */ MCD_OPC_Decode, 112, 3, // Opcode: BPZapt /* 315 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 336 /* 319 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 322 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 329 /* 326 */ MCD_OPC_Decode, 95, 3, // Opcode: BPLEZapn /* 329 */ MCD_OPC_FilterValue, 1, 106, 21, // Skip to: 5815 /* 333 */ MCD_OPC_Decode, 96, 3, // Opcode: BPLEZapt /* 336 */ MCD_OPC_FilterValue, 19, 17, 0, // Skip to: 357 /* 340 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 343 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 350 /* 347 */ MCD_OPC_Decode, 99, 3, // Opcode: BPLZapn /* 350 */ MCD_OPC_FilterValue, 1, 85, 21, // Skip to: 5815 /* 354 */ MCD_OPC_Decode, 100, 3, // Opcode: BPLZapt /* 357 */ MCD_OPC_FilterValue, 21, 17, 0, // Skip to: 378 /* 361 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 364 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 371 /* 368 */ MCD_OPC_Decode, 103, 3, // Opcode: BPNZapn /* 371 */ MCD_OPC_FilterValue, 1, 64, 21, // Skip to: 5815 /* 375 */ MCD_OPC_Decode, 104, 3, // Opcode: BPNZapt /* 378 */ MCD_OPC_FilterValue, 22, 17, 0, // Skip to: 399 /* 382 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 385 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 392 /* 389 */ MCD_OPC_Decode, 87, 3, // Opcode: BPGZapn /* 392 */ MCD_OPC_FilterValue, 1, 43, 21, // Skip to: 5815 /* 396 */ MCD_OPC_Decode, 88, 3, // Opcode: BPGZapt /* 399 */ MCD_OPC_FilterValue, 23, 36, 21, // Skip to: 5815 /* 403 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 406 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 413 /* 410 */ MCD_OPC_Decode, 83, 3, // Opcode: BPGEZapn /* 413 */ MCD_OPC_FilterValue, 1, 22, 21, // Skip to: 5815 /* 417 */ MCD_OPC_Decode, 84, 3, // Opcode: BPGEZapt /* 420 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 444 /* 424 */ MCD_OPC_CheckField, 25, 5, 0, 10, 0, // Skip to: 440 /* 430 */ MCD_OPC_CheckField, 0, 22, 0, 4, 0, // Skip to: 440 /* 436 */ MCD_OPC_Decode, 224, 2, 4, // Opcode: NOP /* 440 */ MCD_OPC_Decode, 135, 3, 5, // Opcode: SETHIi /* 444 */ MCD_OPC_FilterValue, 5, 61, 0, // Skip to: 509 /* 448 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... /* 451 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 480 /* 455 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 458 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 469 /* 462 */ MCD_OPC_CheckPredicate, 0, 229, 20, // Skip to: 5815 /* 466 */ MCD_OPC_Decode, 82, 6, // Opcode: BPFCCNT /* 469 */ MCD_OPC_FilterValue, 1, 222, 20, // Skip to: 5815 /* 473 */ MCD_OPC_CheckPredicate, 0, 218, 20, // Skip to: 5815 /* 477 */ MCD_OPC_Decode, 81, 6, // Opcode: BPFCCANT /* 480 */ MCD_OPC_FilterValue, 1, 211, 20, // Skip to: 5815 /* 484 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 487 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 498 /* 491 */ MCD_OPC_CheckPredicate, 0, 200, 20, // Skip to: 5815 /* 495 */ MCD_OPC_Decode, 79, 6, // Opcode: BPFCC /* 498 */ MCD_OPC_FilterValue, 1, 193, 20, // Skip to: 5815 /* 502 */ MCD_OPC_CheckPredicate, 0, 189, 20, // Skip to: 5815 /* 506 */ MCD_OPC_Decode, 80, 6, // Opcode: BPFCCA /* 509 */ MCD_OPC_FilterValue, 6, 182, 20, // Skip to: 5815 /* 513 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 516 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 524 /* 520 */ MCD_OPC_Decode, 151, 1, 2, // Opcode: FBCOND /* 524 */ MCD_OPC_FilterValue, 1, 167, 20, // Skip to: 5815 /* 528 */ MCD_OPC_Decode, 152, 1, 2, // Opcode: FBCONDA /* 532 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 539 /* 536 */ MCD_OPC_Decode, 116, 7, // Opcode: CALL /* 539 */ MCD_OPC_FilterValue, 2, 87, 18, // Skip to: 5238 /* 543 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... /* 546 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 573 /* 550 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 553 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 566 /* 557 */ MCD_OPC_CheckField, 5, 8, 0, 132, 20, // Skip to: 5815 /* 563 */ MCD_OPC_Decode, 33, 8, // Opcode: ADDrr /* 566 */ MCD_OPC_FilterValue, 1, 125, 20, // Skip to: 5815 /* 570 */ MCD_OPC_Decode, 32, 9, // Opcode: ADDri /* 573 */ MCD_OPC_FilterValue, 1, 23, 0, // Skip to: 600 /* 577 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 580 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 593 /* 584 */ MCD_OPC_CheckField, 5, 8, 0, 105, 20, // Skip to: 5815 /* 590 */ MCD_OPC_Decode, 48, 8, // Opcode: ANDrr /* 593 */ MCD_OPC_FilterValue, 1, 98, 20, // Skip to: 5815 /* 597 */ MCD_OPC_Decode, 47, 9, // Opcode: ANDri /* 600 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 629 /* 604 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 607 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 621 /* 611 */ MCD_OPC_CheckField, 5, 8, 0, 78, 20, // Skip to: 5815 /* 617 */ MCD_OPC_Decode, 235, 2, 8, // Opcode: ORrr /* 621 */ MCD_OPC_FilterValue, 1, 70, 20, // Skip to: 5815 /* 625 */ MCD_OPC_Decode, 234, 2, 9, // Opcode: ORri /* 629 */ MCD_OPC_FilterValue, 3, 25, 0, // Skip to: 658 /* 633 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 650 /* 640 */ MCD_OPC_CheckField, 5, 8, 0, 49, 20, // Skip to: 5815 /* 646 */ MCD_OPC_Decode, 237, 3, 8, // Opcode: XORrr /* 650 */ MCD_OPC_FilterValue, 1, 41, 20, // Skip to: 5815 /* 654 */ MCD_OPC_Decode, 236, 3, 9, // Opcode: XORri /* 658 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 687 /* 662 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 665 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 679 /* 669 */ MCD_OPC_CheckField, 5, 8, 0, 20, 20, // Skip to: 5815 /* 675 */ MCD_OPC_Decode, 178, 3, 8, // Opcode: SUBrr /* 679 */ MCD_OPC_FilterValue, 1, 12, 20, // Skip to: 5815 /* 683 */ MCD_OPC_Decode, 177, 3, 9, // Opcode: SUBri /* 687 */ MCD_OPC_FilterValue, 5, 23, 0, // Skip to: 714 /* 691 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 694 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 707 /* 698 */ MCD_OPC_CheckField, 5, 8, 0, 247, 19, // Skip to: 5815 /* 704 */ MCD_OPC_Decode, 43, 8, // Opcode: ANDNrr /* 707 */ MCD_OPC_FilterValue, 1, 240, 19, // Skip to: 5815 /* 711 */ MCD_OPC_Decode, 42, 9, // Opcode: ANDNri /* 714 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 743 /* 718 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 721 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 735 /* 725 */ MCD_OPC_CheckField, 5, 8, 0, 220, 19, // Skip to: 5815 /* 731 */ MCD_OPC_Decode, 230, 2, 8, // Opcode: ORNrr /* 735 */ MCD_OPC_FilterValue, 1, 212, 19, // Skip to: 5815 /* 739 */ MCD_OPC_Decode, 229, 2, 9, // Opcode: ORNri /* 743 */ MCD_OPC_FilterValue, 7, 25, 0, // Skip to: 772 /* 747 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 750 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 764 /* 754 */ MCD_OPC_CheckField, 5, 8, 0, 191, 19, // Skip to: 5815 /* 760 */ MCD_OPC_Decode, 231, 3, 8, // Opcode: XNORrr /* 764 */ MCD_OPC_FilterValue, 1, 183, 19, // Skip to: 5815 /* 768 */ MCD_OPC_Decode, 230, 3, 9, // Opcode: XNORri /* 772 */ MCD_OPC_FilterValue, 8, 23, 0, // Skip to: 799 /* 776 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 779 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 792 /* 783 */ MCD_OPC_CheckField, 5, 8, 0, 162, 19, // Skip to: 5815 /* 789 */ MCD_OPC_Decode, 25, 8, // Opcode: ADDCrr /* 792 */ MCD_OPC_FilterValue, 1, 155, 19, // Skip to: 5815 /* 796 */ MCD_OPC_Decode, 24, 9, // Opcode: ADDCri /* 799 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 828 /* 803 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 806 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 820 /* 810 */ MCD_OPC_CheckField, 5, 8, 0, 135, 19, // Skip to: 5815 /* 816 */ MCD_OPC_Decode, 223, 2, 10, // Opcode: MULXrr /* 820 */ MCD_OPC_FilterValue, 1, 127, 19, // Skip to: 5815 /* 824 */ MCD_OPC_Decode, 222, 2, 11, // Opcode: MULXri /* 828 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 857 /* 832 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 835 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 849 /* 839 */ MCD_OPC_CheckField, 5, 8, 0, 106, 19, // Skip to: 5815 /* 845 */ MCD_OPC_Decode, 210, 3, 8, // Opcode: UMULrr /* 849 */ MCD_OPC_FilterValue, 1, 98, 19, // Skip to: 5815 /* 853 */ MCD_OPC_Decode, 209, 3, 9, // Opcode: UMULri /* 857 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 886 /* 861 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 864 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 878 /* 868 */ MCD_OPC_CheckField, 5, 8, 0, 77, 19, // Skip to: 5815 /* 874 */ MCD_OPC_Decode, 145, 3, 8, // Opcode: SMULrr /* 878 */ MCD_OPC_FilterValue, 1, 69, 19, // Skip to: 5815 /* 882 */ MCD_OPC_Decode, 144, 3, 9, // Opcode: SMULri /* 886 */ MCD_OPC_FilterValue, 12, 25, 0, // Skip to: 915 /* 890 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 893 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 907 /* 897 */ MCD_OPC_CheckField, 5, 8, 0, 48, 19, // Skip to: 5815 /* 903 */ MCD_OPC_Decode, 172, 3, 8, // Opcode: SUBCrr /* 907 */ MCD_OPC_FilterValue, 1, 40, 19, // Skip to: 5815 /* 911 */ MCD_OPC_Decode, 171, 3, 9, // Opcode: SUBCri /* 915 */ MCD_OPC_FilterValue, 13, 25, 0, // Skip to: 944 /* 919 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 922 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 936 /* 926 */ MCD_OPC_CheckField, 5, 8, 0, 19, 19, // Skip to: 5815 /* 932 */ MCD_OPC_Decode, 203, 3, 10, // Opcode: UDIVXrr /* 936 */ MCD_OPC_FilterValue, 1, 11, 19, // Skip to: 5815 /* 940 */ MCD_OPC_Decode, 202, 3, 11, // Opcode: UDIVXri /* 944 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 973 /* 948 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 951 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 965 /* 955 */ MCD_OPC_CheckField, 5, 8, 0, 246, 18, // Skip to: 5815 /* 961 */ MCD_OPC_Decode, 205, 3, 8, // Opcode: UDIVrr /* 965 */ MCD_OPC_FilterValue, 1, 238, 18, // Skip to: 5815 /* 969 */ MCD_OPC_Decode, 204, 3, 9, // Opcode: UDIVri /* 973 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 1002 /* 977 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 980 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 994 /* 984 */ MCD_OPC_CheckField, 5, 8, 0, 217, 18, // Skip to: 5815 /* 990 */ MCD_OPC_Decode, 253, 2, 8, // Opcode: SDIVrr /* 994 */ MCD_OPC_FilterValue, 1, 209, 18, // Skip to: 5815 /* 998 */ MCD_OPC_Decode, 252, 2, 9, // Opcode: SDIVri /* 1002 */ MCD_OPC_FilterValue, 16, 23, 0, // Skip to: 1029 /* 1006 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1009 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1022 /* 1013 */ MCD_OPC_CheckField, 5, 8, 0, 188, 18, // Skip to: 5815 /* 1019 */ MCD_OPC_Decode, 23, 8, // Opcode: ADDCCrr /* 1022 */ MCD_OPC_FilterValue, 1, 181, 18, // Skip to: 5815 /* 1026 */ MCD_OPC_Decode, 22, 9, // Opcode: ADDCCri /* 1029 */ MCD_OPC_FilterValue, 17, 23, 0, // Skip to: 1056 /* 1033 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1036 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1049 /* 1040 */ MCD_OPC_CheckField, 5, 8, 0, 161, 18, // Skip to: 5815 /* 1046 */ MCD_OPC_Decode, 39, 8, // Opcode: ANDCCrr /* 1049 */ MCD_OPC_FilterValue, 1, 154, 18, // Skip to: 5815 /* 1053 */ MCD_OPC_Decode, 38, 9, // Opcode: ANDCCri /* 1056 */ MCD_OPC_FilterValue, 18, 25, 0, // Skip to: 1085 /* 1060 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1063 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1077 /* 1067 */ MCD_OPC_CheckField, 5, 8, 0, 134, 18, // Skip to: 5815 /* 1073 */ MCD_OPC_Decode, 226, 2, 8, // Opcode: ORCCrr /* 1077 */ MCD_OPC_FilterValue, 1, 126, 18, // Skip to: 5815 /* 1081 */ MCD_OPC_Decode, 225, 2, 9, // Opcode: ORCCri /* 1085 */ MCD_OPC_FilterValue, 19, 25, 0, // Skip to: 1114 /* 1089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1092 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1106 /* 1096 */ MCD_OPC_CheckField, 5, 8, 0, 105, 18, // Skip to: 5815 /* 1102 */ MCD_OPC_Decode, 233, 3, 8, // Opcode: XORCCrr /* 1106 */ MCD_OPC_FilterValue, 1, 97, 18, // Skip to: 5815 /* 1110 */ MCD_OPC_Decode, 232, 3, 9, // Opcode: XORCCri /* 1114 */ MCD_OPC_FilterValue, 20, 44, 0, // Skip to: 1162 /* 1118 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1121 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1145 /* 1125 */ MCD_OPC_ExtractField, 5, 8, // Inst{12-5} ... /* 1128 */ MCD_OPC_FilterValue, 0, 75, 18, // Skip to: 5815 /* 1132 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1141 /* 1138 */ MCD_OPC_Decode, 125, 12, // Opcode: CMPrr /* 1141 */ MCD_OPC_Decode, 170, 3, 8, // Opcode: SUBCCrr /* 1145 */ MCD_OPC_FilterValue, 1, 58, 18, // Skip to: 5815 /* 1149 */ MCD_OPC_CheckField, 25, 5, 0, 3, 0, // Skip to: 1158 /* 1155 */ MCD_OPC_Decode, 124, 13, // Opcode: CMPri /* 1158 */ MCD_OPC_Decode, 169, 3, 9, // Opcode: SUBCCri /* 1162 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1189 /* 1166 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1169 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1182 /* 1173 */ MCD_OPC_CheckField, 5, 8, 0, 28, 18, // Skip to: 5815 /* 1179 */ MCD_OPC_Decode, 41, 8, // Opcode: ANDNCCrr /* 1182 */ MCD_OPC_FilterValue, 1, 21, 18, // Skip to: 5815 /* 1186 */ MCD_OPC_Decode, 40, 9, // Opcode: ANDNCCri /* 1189 */ MCD_OPC_FilterValue, 22, 25, 0, // Skip to: 1218 /* 1193 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1196 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1210 /* 1200 */ MCD_OPC_CheckField, 5, 8, 0, 1, 18, // Skip to: 5815 /* 1206 */ MCD_OPC_Decode, 228, 2, 8, // Opcode: ORNCCrr /* 1210 */ MCD_OPC_FilterValue, 1, 249, 17, // Skip to: 5815 /* 1214 */ MCD_OPC_Decode, 227, 2, 9, // Opcode: ORNCCri /* 1218 */ MCD_OPC_FilterValue, 23, 25, 0, // Skip to: 1247 /* 1222 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1225 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1239 /* 1229 */ MCD_OPC_CheckField, 5, 8, 0, 228, 17, // Skip to: 5815 /* 1235 */ MCD_OPC_Decode, 228, 3, 8, // Opcode: XNORCCrr /* 1239 */ MCD_OPC_FilterValue, 1, 220, 17, // Skip to: 5815 /* 1243 */ MCD_OPC_Decode, 227, 3, 9, // Opcode: XNORCCri /* 1247 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1274 /* 1251 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1254 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1267 /* 1258 */ MCD_OPC_CheckField, 5, 8, 0, 199, 17, // Skip to: 5815 /* 1264 */ MCD_OPC_Decode, 27, 8, // Opcode: ADDErr /* 1267 */ MCD_OPC_FilterValue, 1, 192, 17, // Skip to: 5815 /* 1271 */ MCD_OPC_Decode, 26, 9, // Opcode: ADDEri /* 1274 */ MCD_OPC_FilterValue, 26, 25, 0, // Skip to: 1303 /* 1278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1295 /* 1285 */ MCD_OPC_CheckField, 5, 8, 0, 172, 17, // Skip to: 5815 /* 1291 */ MCD_OPC_Decode, 207, 3, 8, // Opcode: UMULCCrr /* 1295 */ MCD_OPC_FilterValue, 1, 164, 17, // Skip to: 5815 /* 1299 */ MCD_OPC_Decode, 206, 3, 9, // Opcode: UMULCCri /* 1303 */ MCD_OPC_FilterValue, 27, 25, 0, // Skip to: 1332 /* 1307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1324 /* 1314 */ MCD_OPC_CheckField, 5, 8, 0, 143, 17, // Skip to: 5815 /* 1320 */ MCD_OPC_Decode, 143, 3, 8, // Opcode: SMULCCrr /* 1324 */ MCD_OPC_FilterValue, 1, 135, 17, // Skip to: 5815 /* 1328 */ MCD_OPC_Decode, 142, 3, 9, // Opcode: SMULCCri /* 1332 */ MCD_OPC_FilterValue, 28, 25, 0, // Skip to: 1361 /* 1336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1353 /* 1343 */ MCD_OPC_CheckField, 5, 8, 0, 114, 17, // Skip to: 5815 /* 1349 */ MCD_OPC_Decode, 174, 3, 8, // Opcode: SUBErr /* 1353 */ MCD_OPC_FilterValue, 1, 106, 17, // Skip to: 5815 /* 1357 */ MCD_OPC_Decode, 173, 3, 9, // Opcode: SUBEri /* 1361 */ MCD_OPC_FilterValue, 30, 25, 0, // Skip to: 1390 /* 1365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1382 /* 1372 */ MCD_OPC_CheckField, 5, 8, 0, 85, 17, // Skip to: 5815 /* 1378 */ MCD_OPC_Decode, 201, 3, 8, // Opcode: UDIVCCrr /* 1382 */ MCD_OPC_FilterValue, 1, 77, 17, // Skip to: 5815 /* 1386 */ MCD_OPC_Decode, 200, 3, 9, // Opcode: UDIVCCri /* 1390 */ MCD_OPC_FilterValue, 31, 25, 0, // Skip to: 1419 /* 1394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1411 /* 1401 */ MCD_OPC_CheckField, 5, 8, 0, 56, 17, // Skip to: 5815 /* 1407 */ MCD_OPC_Decode, 249, 2, 8, // Opcode: SDIVCCrr /* 1411 */ MCD_OPC_FilterValue, 1, 48, 17, // Skip to: 5815 /* 1415 */ MCD_OPC_Decode, 248, 2, 9, // Opcode: SDIVCCri /* 1419 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 1448 /* 1423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1440 /* 1430 */ MCD_OPC_CheckField, 5, 8, 0, 27, 17, // Skip to: 5815 /* 1436 */ MCD_OPC_Decode, 186, 3, 8, // Opcode: TADDCCrr /* 1440 */ MCD_OPC_FilterValue, 1, 19, 17, // Skip to: 5815 /* 1444 */ MCD_OPC_Decode, 185, 3, 9, // Opcode: TADDCCri /* 1448 */ MCD_OPC_FilterValue, 33, 25, 0, // Skip to: 1477 /* 1452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1469 /* 1459 */ MCD_OPC_CheckField, 5, 8, 0, 254, 16, // Skip to: 5815 /* 1465 */ MCD_OPC_Decode, 197, 3, 8, // Opcode: TSUBCCrr /* 1469 */ MCD_OPC_FilterValue, 1, 246, 16, // Skip to: 5815 /* 1473 */ MCD_OPC_Decode, 196, 3, 9, // Opcode: TSUBCCri /* 1477 */ MCD_OPC_FilterValue, 34, 25, 0, // Skip to: 1506 /* 1481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1498 /* 1488 */ MCD_OPC_CheckField, 5, 8, 0, 225, 16, // Skip to: 5815 /* 1494 */ MCD_OPC_Decode, 184, 3, 8, // Opcode: TADDCCTVrr /* 1498 */ MCD_OPC_FilterValue, 1, 217, 16, // Skip to: 5815 /* 1502 */ MCD_OPC_Decode, 183, 3, 9, // Opcode: TADDCCTVri /* 1506 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 1535 /* 1510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1527 /* 1517 */ MCD_OPC_CheckField, 5, 8, 0, 196, 16, // Skip to: 5815 /* 1523 */ MCD_OPC_Decode, 195, 3, 8, // Opcode: TSUBCCTVrr /* 1527 */ MCD_OPC_FilterValue, 1, 188, 16, // Skip to: 5815 /* 1531 */ MCD_OPC_Decode, 194, 3, 9, // Opcode: TSUBCCTVri /* 1535 */ MCD_OPC_FilterValue, 37, 50, 0, // Skip to: 1589 /* 1539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1542 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1571 /* 1546 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 1549 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1563 /* 1553 */ MCD_OPC_CheckField, 5, 7, 0, 160, 16, // Skip to: 5815 /* 1559 */ MCD_OPC_Decode, 141, 3, 8, // Opcode: SLLrr /* 1563 */ MCD_OPC_FilterValue, 1, 152, 16, // Skip to: 5815 /* 1567 */ MCD_OPC_Decode, 139, 3, 14, // Opcode: SLLXrr /* 1571 */ MCD_OPC_FilterValue, 1, 144, 16, // Skip to: 5815 /* 1575 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1585 /* 1581 */ MCD_OPC_Decode, 138, 3, 15, // Opcode: SLLXri /* 1585 */ MCD_OPC_Decode, 140, 3, 9, // Opcode: SLLri /* 1589 */ MCD_OPC_FilterValue, 38, 50, 0, // Skip to: 1643 /* 1593 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1596 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1625 /* 1600 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 1603 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1617 /* 1607 */ MCD_OPC_CheckField, 5, 7, 0, 106, 16, // Skip to: 5815 /* 1613 */ MCD_OPC_Decode, 153, 3, 8, // Opcode: SRLrr /* 1617 */ MCD_OPC_FilterValue, 1, 98, 16, // Skip to: 5815 /* 1621 */ MCD_OPC_Decode, 151, 3, 14, // Opcode: SRLXrr /* 1625 */ MCD_OPC_FilterValue, 1, 90, 16, // Skip to: 5815 /* 1629 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1639 /* 1635 */ MCD_OPC_Decode, 150, 3, 15, // Opcode: SRLXri /* 1639 */ MCD_OPC_Decode, 152, 3, 9, // Opcode: SRLri /* 1643 */ MCD_OPC_FilterValue, 39, 50, 0, // Skip to: 1697 /* 1647 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1650 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 1679 /* 1654 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 1657 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1671 /* 1661 */ MCD_OPC_CheckField, 5, 7, 0, 52, 16, // Skip to: 5815 /* 1667 */ MCD_OPC_Decode, 149, 3, 8, // Opcode: SRArr /* 1671 */ MCD_OPC_FilterValue, 1, 44, 16, // Skip to: 5815 /* 1675 */ MCD_OPC_Decode, 147, 3, 14, // Opcode: SRAXrr /* 1679 */ MCD_OPC_FilterValue, 1, 36, 16, // Skip to: 5815 /* 1683 */ MCD_OPC_CheckField, 12, 1, 1, 4, 0, // Skip to: 1693 /* 1689 */ MCD_OPC_Decode, 146, 3, 15, // Opcode: SRAXri /* 1693 */ MCD_OPC_Decode, 148, 3, 9, // Opcode: SRAri /* 1697 */ MCD_OPC_FilterValue, 40, 55, 0, // Skip to: 1756 /* 1701 */ MCD_OPC_ExtractField, 13, 6, // Inst{18-13} ... /* 1704 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1718 /* 1708 */ MCD_OPC_CheckField, 0, 13, 0, 5, 16, // Skip to: 5815 /* 1714 */ MCD_OPC_Decode, 239, 2, 4, // Opcode: RDY /* 1718 */ MCD_OPC_FilterValue, 30, 16, 0, // Skip to: 1738 /* 1722 */ MCD_OPC_CheckField, 25, 5, 0, 247, 15, // Skip to: 5815 /* 1728 */ MCD_OPC_CheckField, 0, 13, 0, 241, 15, // Skip to: 5815 /* 1734 */ MCD_OPC_Decode, 154, 3, 4, // Opcode: STBAR /* 1738 */ MCD_OPC_FilterValue, 31, 233, 15, // Skip to: 5815 /* 1742 */ MCD_OPC_CheckPredicate, 0, 229, 15, // Skip to: 5815 /* 1746 */ MCD_OPC_CheckField, 25, 5, 0, 223, 15, // Skip to: 5815 /* 1752 */ MCD_OPC_Decode, 198, 2, 16, // Opcode: MEMBARi /* 1756 */ MCD_OPC_FilterValue, 43, 20, 0, // Skip to: 1780 /* 1760 */ MCD_OPC_CheckPredicate, 0, 211, 15, // Skip to: 5815 /* 1764 */ MCD_OPC_CheckField, 25, 5, 0, 205, 15, // Skip to: 5815 /* 1770 */ MCD_OPC_CheckField, 0, 19, 0, 199, 15, // Skip to: 5815 /* 1776 */ MCD_OPC_Decode, 183, 1, 4, // Opcode: FLUSHW /* 1780 */ MCD_OPC_FilterValue, 44, 123, 0, // Skip to: 1907 /* 1784 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1787 */ MCD_OPC_FilterValue, 0, 56, 0, // Skip to: 1847 /* 1791 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 1794 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1820 /* 1798 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1812 /* 1802 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1812 /* 1808 */ MCD_OPC_Decode, 201, 2, 17, // Opcode: MOVFCCrr /* 1812 */ MCD_OPC_CheckPredicate, 0, 159, 15, // Skip to: 5815 /* 1816 */ MCD_OPC_Decode, 222, 3, 18, // Opcode: V9MOVFCCrr /* 1820 */ MCD_OPC_FilterValue, 1, 151, 15, // Skip to: 5815 /* 1824 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 1827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1839 /* 1831 */ MCD_OPC_CheckPredicate, 0, 140, 15, // Skip to: 5815 /* 1835 */ MCD_OPC_Decode, 203, 2, 17, // Opcode: MOVICCrr /* 1839 */ MCD_OPC_FilterValue, 2, 132, 15, // Skip to: 5815 /* 1843 */ MCD_OPC_Decode, 220, 2, 17, // Opcode: MOVXCCrr /* 1847 */ MCD_OPC_FilterValue, 1, 124, 15, // Skip to: 5815 /* 1851 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 1854 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1880 /* 1858 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1872 /* 1862 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 1872 /* 1868 */ MCD_OPC_Decode, 200, 2, 19, // Opcode: MOVFCCri /* 1872 */ MCD_OPC_CheckPredicate, 0, 99, 15, // Skip to: 5815 /* 1876 */ MCD_OPC_Decode, 221, 3, 20, // Opcode: V9MOVFCCri /* 1880 */ MCD_OPC_FilterValue, 1, 91, 15, // Skip to: 5815 /* 1884 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 1887 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1899 /* 1891 */ MCD_OPC_CheckPredicate, 0, 80, 15, // Skip to: 5815 /* 1895 */ MCD_OPC_Decode, 202, 2, 19, // Opcode: MOVICCri /* 1899 */ MCD_OPC_FilterValue, 2, 72, 15, // Skip to: 5815 /* 1903 */ MCD_OPC_Decode, 219, 2, 19, // Opcode: MOVXCCri /* 1907 */ MCD_OPC_FilterValue, 45, 25, 0, // Skip to: 1936 /* 1911 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 1914 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1928 /* 1918 */ MCD_OPC_CheckField, 5, 8, 0, 51, 15, // Skip to: 5815 /* 1924 */ MCD_OPC_Decode, 251, 2, 10, // Opcode: SDIVXrr /* 1928 */ MCD_OPC_FilterValue, 1, 43, 15, // Skip to: 5815 /* 1932 */ MCD_OPC_Decode, 250, 2, 11, // Opcode: SDIVXri /* 1936 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 1954 /* 1940 */ MCD_OPC_CheckPredicate, 0, 31, 15, // Skip to: 5815 /* 1944 */ MCD_OPC_CheckField, 5, 14, 0, 25, 15, // Skip to: 5815 /* 1950 */ MCD_OPC_Decode, 238, 2, 21, // Opcode: POPCrr /* 1954 */ MCD_OPC_FilterValue, 47, 135, 0, // Skip to: 2093 /* 1958 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... /* 1961 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 1975 /* 1965 */ MCD_OPC_CheckField, 5, 5, 0, 4, 15, // Skip to: 5815 /* 1971 */ MCD_OPC_Decode, 215, 2, 14, // Opcode: MOVRRZrr /* 1975 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 1989 /* 1979 */ MCD_OPC_CheckField, 5, 5, 0, 246, 14, // Skip to: 5815 /* 1985 */ MCD_OPC_Decode, 209, 2, 14, // Opcode: MOVRLEZrr /* 1989 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2003 /* 1993 */ MCD_OPC_CheckField, 5, 5, 0, 232, 14, // Skip to: 5815 /* 1999 */ MCD_OPC_Decode, 211, 2, 14, // Opcode: MOVRLZrr /* 2003 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2017 /* 2007 */ MCD_OPC_CheckField, 5, 5, 0, 218, 14, // Skip to: 5815 /* 2013 */ MCD_OPC_Decode, 213, 2, 14, // Opcode: MOVRNZrr /* 2017 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2031 /* 2021 */ MCD_OPC_CheckField, 5, 5, 0, 204, 14, // Skip to: 5815 /* 2027 */ MCD_OPC_Decode, 207, 2, 14, // Opcode: MOVRGZrr /* 2031 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2045 /* 2035 */ MCD_OPC_CheckField, 5, 5, 0, 190, 14, // Skip to: 5815 /* 2041 */ MCD_OPC_Decode, 205, 2, 14, // Opcode: MOVRGEZrr /* 2045 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2053 /* 2049 */ MCD_OPC_Decode, 214, 2, 22, // Opcode: MOVRRZri /* 2053 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 2061 /* 2057 */ MCD_OPC_Decode, 208, 2, 22, // Opcode: MOVRLEZri /* 2061 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2069 /* 2065 */ MCD_OPC_Decode, 210, 2, 22, // Opcode: MOVRLZri /* 2069 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2077 /* 2073 */ MCD_OPC_Decode, 212, 2, 22, // Opcode: MOVRNZri /* 2077 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 2085 /* 2081 */ MCD_OPC_Decode, 206, 2, 22, // Opcode: MOVRGZri /* 2085 */ MCD_OPC_FilterValue, 15, 142, 14, // Skip to: 5815 /* 2089 */ MCD_OPC_Decode, 204, 2, 22, // Opcode: MOVRGEZri /* 2093 */ MCD_OPC_FilterValue, 48, 37, 0, // Skip to: 2134 /* 2097 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 2100 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 2120 /* 2104 */ MCD_OPC_CheckField, 25, 5, 0, 121, 14, // Skip to: 5815 /* 2110 */ MCD_OPC_CheckField, 5, 8, 0, 115, 14, // Skip to: 5815 /* 2116 */ MCD_OPC_Decode, 224, 3, 12, // Opcode: WRYrr /* 2120 */ MCD_OPC_FilterValue, 1, 107, 14, // Skip to: 5815 /* 2124 */ MCD_OPC_CheckField, 25, 5, 0, 101, 14, // Skip to: 5815 /* 2130 */ MCD_OPC_Decode, 223, 3, 13, // Opcode: WRYri /* 2134 */ MCD_OPC_FilterValue, 52, 197, 2, // Skip to: 2847 /* 2138 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... /* 2141 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2155 /* 2145 */ MCD_OPC_CheckField, 14, 5, 0, 80, 14, // Skip to: 5815 /* 2151 */ MCD_OPC_Decode, 211, 1, 23, // Opcode: FMOVS /* 2155 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2173 /* 2159 */ MCD_OPC_CheckPredicate, 0, 68, 14, // Skip to: 5815 /* 2163 */ MCD_OPC_CheckField, 14, 5, 0, 62, 14, // Skip to: 5815 /* 2169 */ MCD_OPC_Decode, 185, 1, 24, // Opcode: FMOVD /* 2173 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 2191 /* 2177 */ MCD_OPC_CheckPredicate, 0, 50, 14, // Skip to: 5815 /* 2181 */ MCD_OPC_CheckField, 14, 5, 0, 44, 14, // Skip to: 5815 /* 2187 */ MCD_OPC_Decode, 189, 1, 25, // Opcode: FMOVQ /* 2191 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2205 /* 2195 */ MCD_OPC_CheckField, 14, 5, 0, 30, 14, // Skip to: 5815 /* 2201 */ MCD_OPC_Decode, 231, 1, 23, // Opcode: FNEGS /* 2205 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2223 /* 2209 */ MCD_OPC_CheckPredicate, 0, 18, 14, // Skip to: 5815 /* 2213 */ MCD_OPC_CheckField, 14, 5, 0, 12, 14, // Skip to: 5815 /* 2219 */ MCD_OPC_Decode, 229, 1, 24, // Opcode: FNEGD /* 2223 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2241 /* 2227 */ MCD_OPC_CheckPredicate, 0, 0, 14, // Skip to: 5815 /* 2231 */ MCD_OPC_CheckField, 14, 5, 0, 250, 13, // Skip to: 5815 /* 2237 */ MCD_OPC_Decode, 230, 1, 25, // Opcode: FNEGQ /* 2241 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2255 /* 2245 */ MCD_OPC_CheckField, 14, 5, 0, 236, 13, // Skip to: 5815 /* 2251 */ MCD_OPC_Decode, 140, 1, 23, // Opcode: FABSS /* 2255 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2273 /* 2259 */ MCD_OPC_CheckPredicate, 0, 224, 13, // Skip to: 5815 /* 2263 */ MCD_OPC_CheckField, 14, 5, 0, 218, 13, // Skip to: 5815 /* 2269 */ MCD_OPC_Decode, 138, 1, 24, // Opcode: FABSD /* 2273 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2291 /* 2277 */ MCD_OPC_CheckPredicate, 0, 206, 13, // Skip to: 5815 /* 2281 */ MCD_OPC_CheckField, 14, 5, 0, 200, 13, // Skip to: 5815 /* 2287 */ MCD_OPC_Decode, 139, 1, 25, // Opcode: FABSQ /* 2291 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 2305 /* 2295 */ MCD_OPC_CheckField, 14, 5, 0, 186, 13, // Skip to: 5815 /* 2301 */ MCD_OPC_Decode, 147, 2, 23, // Opcode: FSQRTS /* 2305 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 2319 /* 2309 */ MCD_OPC_CheckField, 14, 5, 0, 172, 13, // Skip to: 5815 /* 2315 */ MCD_OPC_Decode, 145, 2, 24, // Opcode: FSQRTD /* 2319 */ MCD_OPC_FilterValue, 43, 10, 0, // Skip to: 2333 /* 2323 */ MCD_OPC_CheckField, 14, 5, 0, 158, 13, // Skip to: 5815 /* 2329 */ MCD_OPC_Decode, 146, 2, 25, // Opcode: FSQRTQ /* 2333 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 2341 /* 2337 */ MCD_OPC_Decode, 143, 1, 26, // Opcode: FADDS /* 2341 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 2349 /* 2345 */ MCD_OPC_Decode, 141, 1, 27, // Opcode: FADDD /* 2349 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 2357 /* 2353 */ MCD_OPC_Decode, 142, 1, 28, // Opcode: FADDQ /* 2357 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 2365 /* 2361 */ MCD_OPC_Decode, 162, 2, 26, // Opcode: FSUBS /* 2365 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 2373 /* 2369 */ MCD_OPC_Decode, 160, 2, 27, // Opcode: FSUBD /* 2373 */ MCD_OPC_FilterValue, 71, 4, 0, // Skip to: 2381 /* 2377 */ MCD_OPC_Decode, 161, 2, 28, // Opcode: FSUBQ /* 2381 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 2389 /* 2385 */ MCD_OPC_Decode, 224, 1, 26, // Opcode: FMULS /* 2389 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 2397 /* 2393 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: FMULD /* 2397 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 2405 /* 2401 */ MCD_OPC_Decode, 223, 1, 28, // Opcode: FMULQ /* 2405 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 2413 /* 2409 */ MCD_OPC_Decode, 167, 1, 26, // Opcode: FDIVS /* 2413 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 2421 /* 2417 */ MCD_OPC_Decode, 165, 1, 27, // Opcode: FDIVD /* 2421 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 2429 /* 2425 */ MCD_OPC_Decode, 166, 1, 28, // Opcode: FDIVQ /* 2429 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 2441 /* 2433 */ MCD_OPC_CheckPredicate, 1, 50, 13, // Skip to: 5815 /* 2437 */ MCD_OPC_Decode, 226, 1, 27, // Opcode: FNADDS /* 2441 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 2453 /* 2445 */ MCD_OPC_CheckPredicate, 1, 38, 13, // Skip to: 5815 /* 2449 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: FNADDD /* 2453 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 2465 /* 2457 */ MCD_OPC_CheckPredicate, 1, 26, 13, // Skip to: 5815 /* 2461 */ MCD_OPC_Decode, 235, 1, 27, // Opcode: FNMULS /* 2465 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 2477 /* 2469 */ MCD_OPC_CheckPredicate, 1, 14, 13, // Skip to: 5815 /* 2473 */ MCD_OPC_Decode, 234, 1, 27, // Opcode: FNMULD /* 2477 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 2489 /* 2481 */ MCD_OPC_CheckPredicate, 1, 2, 13, // Skip to: 5815 /* 2485 */ MCD_OPC_Decode, 175, 1, 27, // Opcode: FHADDS /* 2489 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 2501 /* 2493 */ MCD_OPC_CheckPredicate, 1, 246, 12, // Skip to: 5815 /* 2497 */ MCD_OPC_Decode, 174, 1, 27, // Opcode: FHADDD /* 2501 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 2513 /* 2505 */ MCD_OPC_CheckPredicate, 1, 234, 12, // Skip to: 5815 /* 2509 */ MCD_OPC_Decode, 177, 1, 27, // Opcode: FHSUBS /* 2513 */ MCD_OPC_FilterValue, 102, 8, 0, // Skip to: 2525 /* 2517 */ MCD_OPC_CheckPredicate, 1, 222, 12, // Skip to: 5815 /* 2521 */ MCD_OPC_Decode, 176, 1, 27, // Opcode: FHSUBD /* 2525 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 2533 /* 2529 */ MCD_OPC_Decode, 144, 2, 29, // Opcode: FSMULD /* 2533 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 2541 /* 2537 */ MCD_OPC_Decode, 168, 1, 30, // Opcode: FDMULQ /* 2541 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 2553 /* 2545 */ MCD_OPC_CheckPredicate, 1, 194, 12, // Skip to: 5815 /* 2549 */ MCD_OPC_Decode, 233, 1, 27, // Opcode: FNHADDS /* 2553 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 2565 /* 2557 */ MCD_OPC_CheckPredicate, 1, 182, 12, // Skip to: 5815 /* 2561 */ MCD_OPC_Decode, 232, 1, 27, // Opcode: FNHADDD /* 2565 */ MCD_OPC_FilterValue, 121, 8, 0, // Skip to: 2577 /* 2569 */ MCD_OPC_CheckPredicate, 1, 170, 12, // Skip to: 5815 /* 2573 */ MCD_OPC_Decode, 242, 1, 27, // Opcode: FNSMULD /* 2577 */ MCD_OPC_FilterValue, 129, 1, 10, 0, // Skip to: 2592 /* 2582 */ MCD_OPC_CheckField, 14, 5, 0, 155, 12, // Skip to: 5815 /* 2588 */ MCD_OPC_Decode, 159, 2, 31, // Opcode: FSTOX /* 2592 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 2607 /* 2597 */ MCD_OPC_CheckField, 14, 5, 0, 140, 12, // Skip to: 5815 /* 2603 */ MCD_OPC_Decode, 172, 1, 24, // Opcode: FDTOX /* 2607 */ MCD_OPC_FilterValue, 131, 1, 10, 0, // Skip to: 2622 /* 2612 */ MCD_OPC_CheckField, 14, 5, 0, 125, 12, // Skip to: 5815 /* 2618 */ MCD_OPC_Decode, 139, 2, 32, // Opcode: FQTOX /* 2622 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 2637 /* 2627 */ MCD_OPC_CheckField, 14, 5, 0, 110, 12, // Skip to: 5815 /* 2633 */ MCD_OPC_Decode, 169, 2, 33, // Opcode: FXTOS /* 2637 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 2652 /* 2642 */ MCD_OPC_CheckField, 14, 5, 0, 95, 12, // Skip to: 5815 /* 2648 */ MCD_OPC_Decode, 167, 2, 24, // Opcode: FXTOD /* 2652 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 2667 /* 2657 */ MCD_OPC_CheckField, 14, 5, 0, 80, 12, // Skip to: 5815 /* 2663 */ MCD_OPC_Decode, 168, 2, 34, // Opcode: FXTOQ /* 2667 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 2682 /* 2672 */ MCD_OPC_CheckField, 14, 5, 0, 65, 12, // Skip to: 5815 /* 2678 */ MCD_OPC_Decode, 180, 1, 23, // Opcode: FITOS /* 2682 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 2697 /* 2687 */ MCD_OPC_CheckField, 14, 5, 0, 50, 12, // Skip to: 5815 /* 2693 */ MCD_OPC_Decode, 171, 1, 33, // Opcode: FDTOS /* 2697 */ MCD_OPC_FilterValue, 199, 1, 10, 0, // Skip to: 2712 /* 2702 */ MCD_OPC_CheckField, 14, 5, 0, 35, 12, // Skip to: 5815 /* 2708 */ MCD_OPC_Decode, 138, 2, 35, // Opcode: FQTOS /* 2712 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 2727 /* 2717 */ MCD_OPC_CheckField, 14, 5, 0, 20, 12, // Skip to: 5815 /* 2723 */ MCD_OPC_Decode, 178, 1, 31, // Opcode: FITOD /* 2727 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 2742 /* 2732 */ MCD_OPC_CheckField, 14, 5, 0, 5, 12, // Skip to: 5815 /* 2738 */ MCD_OPC_Decode, 156, 2, 31, // Opcode: FSTOD /* 2742 */ MCD_OPC_FilterValue, 203, 1, 10, 0, // Skip to: 2757 /* 2747 */ MCD_OPC_CheckField, 14, 5, 0, 246, 11, // Skip to: 5815 /* 2753 */ MCD_OPC_Decode, 136, 2, 32, // Opcode: FQTOD /* 2757 */ MCD_OPC_FilterValue, 204, 1, 10, 0, // Skip to: 2772 /* 2762 */ MCD_OPC_CheckField, 14, 5, 0, 231, 11, // Skip to: 5815 /* 2768 */ MCD_OPC_Decode, 179, 1, 36, // Opcode: FITOQ /* 2772 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 2787 /* 2777 */ MCD_OPC_CheckField, 14, 5, 0, 216, 11, // Skip to: 5815 /* 2783 */ MCD_OPC_Decode, 158, 2, 36, // Opcode: FSTOQ /* 2787 */ MCD_OPC_FilterValue, 206, 1, 10, 0, // Skip to: 2802 /* 2792 */ MCD_OPC_CheckField, 14, 5, 0, 201, 11, // Skip to: 5815 /* 2798 */ MCD_OPC_Decode, 170, 1, 34, // Opcode: FDTOQ /* 2802 */ MCD_OPC_FilterValue, 209, 1, 10, 0, // Skip to: 2817 /* 2807 */ MCD_OPC_CheckField, 14, 5, 0, 186, 11, // Skip to: 5815 /* 2813 */ MCD_OPC_Decode, 157, 2, 23, // Opcode: FSTOI /* 2817 */ MCD_OPC_FilterValue, 210, 1, 10, 0, // Skip to: 2832 /* 2822 */ MCD_OPC_CheckField, 14, 5, 0, 171, 11, // Skip to: 5815 /* 2828 */ MCD_OPC_Decode, 169, 1, 33, // Opcode: FDTOI /* 2832 */ MCD_OPC_FilterValue, 211, 1, 162, 11, // Skip to: 5815 /* 2837 */ MCD_OPC_CheckField, 14, 5, 0, 156, 11, // Skip to: 5815 /* 2843 */ MCD_OPC_Decode, 137, 2, 35, // Opcode: FQTOI /* 2847 */ MCD_OPC_FilterValue, 53, 70, 2, // Skip to: 3433 /* 2851 */ MCD_OPC_ExtractField, 5, 6, // Inst{10-5} ... /* 2854 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 2933 /* 2858 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 2861 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2894 /* 2865 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 2868 */ MCD_OPC_FilterValue, 0, 127, 11, // Skip to: 5815 /* 2872 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2886 /* 2876 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2886 /* 2882 */ MCD_OPC_Decode, 212, 1, 37, // Opcode: FMOVS_FCC /* 2886 */ MCD_OPC_CheckPredicate, 0, 109, 11, // Skip to: 5815 /* 2890 */ MCD_OPC_Decode, 220, 3, 38, // Opcode: V9FMOVS_FCC /* 2894 */ MCD_OPC_FilterValue, 1, 101, 11, // Skip to: 5815 /* 2898 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 2901 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2919 /* 2905 */ MCD_OPC_CheckPredicate, 0, 90, 11, // Skip to: 5815 /* 2909 */ MCD_OPC_CheckField, 18, 1, 0, 84, 11, // Skip to: 5815 /* 2915 */ MCD_OPC_Decode, 213, 1, 37, // Opcode: FMOVS_ICC /* 2919 */ MCD_OPC_FilterValue, 2, 76, 11, // Skip to: 5815 /* 2923 */ MCD_OPC_CheckField, 18, 1, 0, 70, 11, // Skip to: 5815 /* 2929 */ MCD_OPC_Decode, 214, 1, 37, // Opcode: FMOVS_XCC /* 2933 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 3012 /* 2937 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 2940 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2973 /* 2944 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 2947 */ MCD_OPC_FilterValue, 0, 48, 11, // Skip to: 5815 /* 2951 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2965 /* 2955 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 2965 /* 2961 */ MCD_OPC_Decode, 186, 1, 39, // Opcode: FMOVD_FCC /* 2965 */ MCD_OPC_CheckPredicate, 0, 30, 11, // Skip to: 5815 /* 2969 */ MCD_OPC_Decode, 218, 3, 40, // Opcode: V9FMOVD_FCC /* 2973 */ MCD_OPC_FilterValue, 1, 22, 11, // Skip to: 5815 /* 2977 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 2980 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2998 /* 2984 */ MCD_OPC_CheckPredicate, 0, 11, 11, // Skip to: 5815 /* 2988 */ MCD_OPC_CheckField, 18, 1, 0, 5, 11, // Skip to: 5815 /* 2994 */ MCD_OPC_Decode, 187, 1, 39, // Opcode: FMOVD_ICC /* 2998 */ MCD_OPC_FilterValue, 2, 253, 10, // Skip to: 5815 /* 3002 */ MCD_OPC_CheckField, 18, 1, 0, 247, 10, // Skip to: 5815 /* 3008 */ MCD_OPC_Decode, 188, 1, 39, // Opcode: FMOVD_XCC /* 3012 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 3091 /* 3016 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 3019 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 3052 /* 3023 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... /* 3026 */ MCD_OPC_FilterValue, 0, 225, 10, // Skip to: 5815 /* 3030 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 3044 /* 3034 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3044 /* 3040 */ MCD_OPC_Decode, 190, 1, 41, // Opcode: FMOVQ_FCC /* 3044 */ MCD_OPC_CheckPredicate, 0, 207, 10, // Skip to: 5815 /* 3048 */ MCD_OPC_Decode, 219, 3, 42, // Opcode: V9FMOVQ_FCC /* 3052 */ MCD_OPC_FilterValue, 1, 199, 10, // Skip to: 5815 /* 3056 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... /* 3059 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3077 /* 3063 */ MCD_OPC_CheckPredicate, 0, 188, 10, // Skip to: 5815 /* 3067 */ MCD_OPC_CheckField, 18, 1, 0, 182, 10, // Skip to: 5815 /* 3073 */ MCD_OPC_Decode, 191, 1, 41, // Opcode: FMOVQ_ICC /* 3077 */ MCD_OPC_FilterValue, 2, 174, 10, // Skip to: 5815 /* 3081 */ MCD_OPC_CheckField, 18, 1, 0, 168, 10, // Skip to: 5815 /* 3087 */ MCD_OPC_Decode, 192, 1, 41, // Opcode: FMOVQ_XCC /* 3091 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 3122 /* 3095 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 3098 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3110 /* 3102 */ MCD_OPC_CheckPredicate, 0, 149, 10, // Skip to: 5815 /* 3106 */ MCD_OPC_Decode, 201, 1, 43, // Opcode: FMOVRLEZS /* 3110 */ MCD_OPC_FilterValue, 3, 141, 10, // Skip to: 5815 /* 3114 */ MCD_OPC_CheckPredicate, 0, 137, 10, // Skip to: 5815 /* 3118 */ MCD_OPC_Decode, 198, 1, 43, // Opcode: FMOVRGZS /* 3122 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3153 /* 3126 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 3129 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3141 /* 3133 */ MCD_OPC_CheckPredicate, 0, 118, 10, // Skip to: 5815 /* 3137 */ MCD_OPC_Decode, 199, 1, 43, // Opcode: FMOVRLEZD /* 3141 */ MCD_OPC_FilterValue, 3, 110, 10, // Skip to: 5815 /* 3145 */ MCD_OPC_CheckPredicate, 0, 106, 10, // Skip to: 5815 /* 3149 */ MCD_OPC_Decode, 196, 1, 43, // Opcode: FMOVRGZD /* 3153 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 3184 /* 3157 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 3160 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3172 /* 3164 */ MCD_OPC_CheckPredicate, 0, 87, 10, // Skip to: 5815 /* 3168 */ MCD_OPC_Decode, 200, 1, 43, // Opcode: FMOVRLEZQ /* 3172 */ MCD_OPC_FilterValue, 3, 79, 10, // Skip to: 5815 /* 3176 */ MCD_OPC_CheckPredicate, 0, 75, 10, // Skip to: 5815 /* 3180 */ MCD_OPC_Decode, 197, 1, 43, // Opcode: FMOVRGZQ /* 3184 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 3198 /* 3188 */ MCD_OPC_CheckField, 11, 3, 1, 61, 10, // Skip to: 5815 /* 3194 */ MCD_OPC_Decode, 217, 3, 44, // Opcode: V9FCMPS /* 3198 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 3212 /* 3202 */ MCD_OPC_CheckField, 11, 3, 1, 47, 10, // Skip to: 5815 /* 3208 */ MCD_OPC_Decode, 212, 3, 45, // Opcode: V9FCMPD /* 3212 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 3226 /* 3216 */ MCD_OPC_CheckField, 11, 3, 1, 33, 10, // Skip to: 5815 /* 3222 */ MCD_OPC_Decode, 216, 3, 46, // Opcode: V9FCMPQ /* 3226 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 3240 /* 3230 */ MCD_OPC_CheckField, 11, 3, 1, 19, 10, // Skip to: 5815 /* 3236 */ MCD_OPC_Decode, 215, 3, 44, // Opcode: V9FCMPES /* 3240 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 3254 /* 3244 */ MCD_OPC_CheckField, 11, 3, 1, 5, 10, // Skip to: 5815 /* 3250 */ MCD_OPC_Decode, 213, 3, 45, // Opcode: V9FCMPED /* 3254 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 3268 /* 3258 */ MCD_OPC_CheckField, 11, 3, 1, 247, 9, // Skip to: 5815 /* 3264 */ MCD_OPC_Decode, 214, 3, 46, // Opcode: V9FCMPEQ /* 3268 */ MCD_OPC_FilterValue, 37, 51, 0, // Skip to: 3323 /* 3272 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 3275 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3287 /* 3279 */ MCD_OPC_CheckPredicate, 0, 228, 9, // Skip to: 5815 /* 3283 */ MCD_OPC_Decode, 210, 1, 43, // Opcode: FMOVRZS /* 3287 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3299 /* 3291 */ MCD_OPC_CheckPredicate, 0, 216, 9, // Skip to: 5815 /* 3295 */ MCD_OPC_Decode, 204, 1, 43, // Opcode: FMOVRLZS /* 3299 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3311 /* 3303 */ MCD_OPC_CheckPredicate, 0, 204, 9, // Skip to: 5815 /* 3307 */ MCD_OPC_Decode, 207, 1, 43, // Opcode: FMOVRNZS /* 3311 */ MCD_OPC_FilterValue, 3, 196, 9, // Skip to: 5815 /* 3315 */ MCD_OPC_CheckPredicate, 0, 192, 9, // Skip to: 5815 /* 3319 */ MCD_OPC_Decode, 195, 1, 43, // Opcode: FMOVRGEZS /* 3323 */ MCD_OPC_FilterValue, 38, 51, 0, // Skip to: 3378 /* 3327 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 3330 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3342 /* 3334 */ MCD_OPC_CheckPredicate, 0, 173, 9, // Skip to: 5815 /* 3338 */ MCD_OPC_Decode, 208, 1, 43, // Opcode: FMOVRZD /* 3342 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3354 /* 3346 */ MCD_OPC_CheckPredicate, 0, 161, 9, // Skip to: 5815 /* 3350 */ MCD_OPC_Decode, 202, 1, 43, // Opcode: FMOVRLZD /* 3354 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3366 /* 3358 */ MCD_OPC_CheckPredicate, 0, 149, 9, // Skip to: 5815 /* 3362 */ MCD_OPC_Decode, 205, 1, 43, // Opcode: FMOVRNZD /* 3366 */ MCD_OPC_FilterValue, 3, 141, 9, // Skip to: 5815 /* 3370 */ MCD_OPC_CheckPredicate, 0, 137, 9, // Skip to: 5815 /* 3374 */ MCD_OPC_Decode, 193, 1, 43, // Opcode: FMOVRGEZD /* 3378 */ MCD_OPC_FilterValue, 39, 129, 9, // Skip to: 5815 /* 3382 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... /* 3385 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3397 /* 3389 */ MCD_OPC_CheckPredicate, 0, 118, 9, // Skip to: 5815 /* 3393 */ MCD_OPC_Decode, 209, 1, 43, // Opcode: FMOVRZQ /* 3397 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3409 /* 3401 */ MCD_OPC_CheckPredicate, 0, 106, 9, // Skip to: 5815 /* 3405 */ MCD_OPC_Decode, 203, 1, 43, // Opcode: FMOVRLZQ /* 3409 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3421 /* 3413 */ MCD_OPC_CheckPredicate, 0, 94, 9, // Skip to: 5815 /* 3417 */ MCD_OPC_Decode, 206, 1, 43, // Opcode: FMOVRNZQ /* 3421 */ MCD_OPC_FilterValue, 3, 86, 9, // Skip to: 5815 /* 3425 */ MCD_OPC_CheckPredicate, 0, 82, 9, // Skip to: 5815 /* 3429 */ MCD_OPC_Decode, 194, 1, 43, // Opcode: FMOVRGEZQ /* 3433 */ MCD_OPC_FilterValue, 54, 18, 6, // Skip to: 4991 /* 3437 */ MCD_OPC_ExtractField, 5, 9, // Inst{13-5} ... /* 3440 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3452 /* 3444 */ MCD_OPC_CheckPredicate, 2, 63, 9, // Skip to: 5815 /* 3448 */ MCD_OPC_Decode, 134, 1, 10, // Opcode: EDGE8 /* 3452 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3464 /* 3456 */ MCD_OPC_CheckPredicate, 3, 51, 9, // Skip to: 5815 /* 3460 */ MCD_OPC_Decode, 137, 1, 10, // Opcode: EDGE8N /* 3464 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3476 /* 3468 */ MCD_OPC_CheckPredicate, 2, 39, 9, // Skip to: 5815 /* 3472 */ MCD_OPC_Decode, 135, 1, 10, // Opcode: EDGE8L /* 3476 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3488 /* 3480 */ MCD_OPC_CheckPredicate, 3, 27, 9, // Skip to: 5815 /* 3484 */ MCD_OPC_Decode, 136, 1, 10, // Opcode: EDGE8LN /* 3488 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 3499 /* 3492 */ MCD_OPC_CheckPredicate, 2, 15, 9, // Skip to: 5815 /* 3496 */ MCD_OPC_Decode, 126, 10, // Opcode: EDGE16 /* 3499 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 3511 /* 3503 */ MCD_OPC_CheckPredicate, 3, 4, 9, // Skip to: 5815 /* 3507 */ MCD_OPC_Decode, 129, 1, 10, // Opcode: EDGE16N /* 3511 */ MCD_OPC_FilterValue, 6, 7, 0, // Skip to: 3522 /* 3515 */ MCD_OPC_CheckPredicate, 2, 248, 8, // Skip to: 5815 /* 3519 */ MCD_OPC_Decode, 127, 10, // Opcode: EDGE16L /* 3522 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 3534 /* 3526 */ MCD_OPC_CheckPredicate, 3, 237, 8, // Skip to: 5815 /* 3530 */ MCD_OPC_Decode, 128, 1, 10, // Opcode: EDGE16LN /* 3534 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 3546 /* 3538 */ MCD_OPC_CheckPredicate, 2, 225, 8, // Skip to: 5815 /* 3542 */ MCD_OPC_Decode, 130, 1, 10, // Opcode: EDGE32 /* 3546 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 3558 /* 3550 */ MCD_OPC_CheckPredicate, 3, 213, 8, // Skip to: 5815 /* 3554 */ MCD_OPC_Decode, 133, 1, 10, // Opcode: EDGE32N /* 3558 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 3570 /* 3562 */ MCD_OPC_CheckPredicate, 2, 201, 8, // Skip to: 5815 /* 3566 */ MCD_OPC_Decode, 131, 1, 10, // Opcode: EDGE32L /* 3570 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 3582 /* 3574 */ MCD_OPC_CheckPredicate, 3, 189, 8, // Skip to: 5815 /* 3578 */ MCD_OPC_Decode, 132, 1, 10, // Opcode: EDGE32LN /* 3582 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 3593 /* 3586 */ MCD_OPC_CheckPredicate, 2, 177, 8, // Skip to: 5815 /* 3590 */ MCD_OPC_Decode, 51, 10, // Opcode: ARRAY8 /* 3593 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 3604 /* 3597 */ MCD_OPC_CheckPredicate, 1, 166, 8, // Skip to: 5815 /* 3601 */ MCD_OPC_Decode, 28, 10, // Opcode: ADDXC /* 3604 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 3615 /* 3608 */ MCD_OPC_CheckPredicate, 2, 155, 8, // Skip to: 5815 /* 3612 */ MCD_OPC_Decode, 49, 10, // Opcode: ARRAY16 /* 3615 */ MCD_OPC_FilterValue, 19, 7, 0, // Skip to: 3626 /* 3619 */ MCD_OPC_CheckPredicate, 1, 144, 8, // Skip to: 5815 /* 3623 */ MCD_OPC_Decode, 29, 10, // Opcode: ADDXCCC /* 3626 */ MCD_OPC_FilterValue, 20, 7, 0, // Skip to: 3637 /* 3630 */ MCD_OPC_CheckPredicate, 2, 133, 8, // Skip to: 5815 /* 3634 */ MCD_OPC_Decode, 50, 10, // Opcode: ARRAY32 /* 3637 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 3649 /* 3641 */ MCD_OPC_CheckPredicate, 1, 122, 8, // Skip to: 5815 /* 3645 */ MCD_OPC_Decode, 208, 3, 10, // Opcode: UMULXHI /* 3649 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3667 /* 3653 */ MCD_OPC_CheckPredicate, 1, 110, 8, // Skip to: 5815 /* 3657 */ MCD_OPC_CheckField, 14, 5, 0, 104, 8, // Skip to: 5815 /* 3663 */ MCD_OPC_Decode, 197, 2, 47, // Opcode: LZCNT /* 3667 */ MCD_OPC_FilterValue, 24, 7, 0, // Skip to: 3678 /* 3671 */ MCD_OPC_CheckPredicate, 2, 92, 8, // Skip to: 5815 /* 3675 */ MCD_OPC_Decode, 36, 10, // Opcode: ALIGNADDR /* 3678 */ MCD_OPC_FilterValue, 25, 7, 0, // Skip to: 3689 /* 3682 */ MCD_OPC_CheckPredicate, 3, 81, 8, // Skip to: 5815 /* 3686 */ MCD_OPC_Decode, 78, 10, // Opcode: BMASK /* 3689 */ MCD_OPC_FilterValue, 26, 7, 0, // Skip to: 3700 /* 3693 */ MCD_OPC_CheckPredicate, 2, 70, 8, // Skip to: 5815 /* 3697 */ MCD_OPC_Decode, 37, 10, // Opcode: ALIGNADDRL /* 3700 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 3723 /* 3704 */ MCD_OPC_CheckPredicate, 1, 59, 8, // Skip to: 5815 /* 3708 */ MCD_OPC_CheckField, 25, 5, 0, 53, 8, // Skip to: 5815 /* 3714 */ MCD_OPC_CheckField, 14, 5, 0, 47, 8, // Skip to: 5815 /* 3720 */ MCD_OPC_Decode, 123, 48, // Opcode: CMASK8 /* 3723 */ MCD_OPC_FilterValue, 28, 7, 0, // Skip to: 3734 /* 3727 */ MCD_OPC_CheckPredicate, 3, 36, 8, // Skip to: 5815 /* 3731 */ MCD_OPC_Decode, 115, 27, // Opcode: BSHUFFLE /* 3734 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 3757 /* 3738 */ MCD_OPC_CheckPredicate, 1, 25, 8, // Skip to: 5815 /* 3742 */ MCD_OPC_CheckField, 25, 5, 0, 19, 8, // Skip to: 5815 /* 3748 */ MCD_OPC_CheckField, 14, 5, 0, 13, 8, // Skip to: 5815 /* 3754 */ MCD_OPC_Decode, 121, 48, // Opcode: CMASK16 /* 3757 */ MCD_OPC_FilterValue, 31, 19, 0, // Skip to: 3780 /* 3761 */ MCD_OPC_CheckPredicate, 1, 2, 8, // Skip to: 5815 /* 3765 */ MCD_OPC_CheckField, 25, 5, 0, 252, 7, // Skip to: 5815 /* 3771 */ MCD_OPC_CheckField, 14, 5, 0, 246, 7, // Skip to: 5815 /* 3777 */ MCD_OPC_Decode, 122, 48, // Opcode: CMASK32 /* 3780 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3792 /* 3784 */ MCD_OPC_CheckPredicate, 2, 235, 7, // Skip to: 5815 /* 3788 */ MCD_OPC_Decode, 159, 1, 49, // Opcode: FCMPLE16 /* 3792 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3804 /* 3796 */ MCD_OPC_CheckPredicate, 1, 223, 7, // Skip to: 5815 /* 3800 */ MCD_OPC_Decode, 142, 2, 27, // Opcode: FSLL16 /* 3804 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 3816 /* 3808 */ MCD_OPC_CheckPredicate, 2, 211, 7, // Skip to: 5815 /* 3812 */ MCD_OPC_Decode, 161, 1, 49, // Opcode: FCMPNE16 /* 3816 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 3828 /* 3820 */ MCD_OPC_CheckPredicate, 1, 199, 7, // Skip to: 5815 /* 3824 */ MCD_OPC_Decode, 154, 2, 27, // Opcode: FSRL16 /* 3828 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 3840 /* 3832 */ MCD_OPC_CheckPredicate, 2, 187, 7, // Skip to: 5815 /* 3836 */ MCD_OPC_Decode, 160, 1, 49, // Opcode: FCMPLE32 /* 3840 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 3852 /* 3844 */ MCD_OPC_CheckPredicate, 1, 175, 7, // Skip to: 5815 /* 3848 */ MCD_OPC_Decode, 143, 2, 27, // Opcode: FSLL32 /* 3852 */ MCD_OPC_FilterValue, 38, 8, 0, // Skip to: 3864 /* 3856 */ MCD_OPC_CheckPredicate, 2, 163, 7, // Skip to: 5815 /* 3860 */ MCD_OPC_Decode, 162, 1, 49, // Opcode: FCMPNE32 /* 3864 */ MCD_OPC_FilterValue, 39, 8, 0, // Skip to: 3876 /* 3868 */ MCD_OPC_CheckPredicate, 1, 151, 7, // Skip to: 5815 /* 3872 */ MCD_OPC_Decode, 155, 2, 27, // Opcode: FSRL32 /* 3876 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3888 /* 3880 */ MCD_OPC_CheckPredicate, 2, 139, 7, // Skip to: 5815 /* 3884 */ MCD_OPC_Decode, 157, 1, 49, // Opcode: FCMPGT16 /* 3888 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3900 /* 3892 */ MCD_OPC_CheckPredicate, 1, 127, 7, // Skip to: 5815 /* 3896 */ MCD_OPC_Decode, 140, 2, 27, // Opcode: FSLAS16 /* 3900 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 3912 /* 3904 */ MCD_OPC_CheckPredicate, 2, 115, 7, // Skip to: 5815 /* 3908 */ MCD_OPC_Decode, 155, 1, 49, // Opcode: FCMPEQ16 /* 3912 */ MCD_OPC_FilterValue, 43, 8, 0, // Skip to: 3924 /* 3916 */ MCD_OPC_CheckPredicate, 1, 103, 7, // Skip to: 5815 /* 3920 */ MCD_OPC_Decode, 148, 2, 27, // Opcode: FSRA16 /* 3924 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 3936 /* 3928 */ MCD_OPC_CheckPredicate, 2, 91, 7, // Skip to: 5815 /* 3932 */ MCD_OPC_Decode, 158, 1, 49, // Opcode: FCMPGT32 /* 3936 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 3948 /* 3940 */ MCD_OPC_CheckPredicate, 1, 79, 7, // Skip to: 5815 /* 3944 */ MCD_OPC_Decode, 141, 2, 27, // Opcode: FSLAS32 /* 3948 */ MCD_OPC_FilterValue, 46, 8, 0, // Skip to: 3960 /* 3952 */ MCD_OPC_CheckPredicate, 2, 67, 7, // Skip to: 5815 /* 3956 */ MCD_OPC_Decode, 156, 1, 49, // Opcode: FCMPEQ32 /* 3960 */ MCD_OPC_FilterValue, 47, 8, 0, // Skip to: 3972 /* 3964 */ MCD_OPC_CheckPredicate, 1, 55, 7, // Skip to: 5815 /* 3968 */ MCD_OPC_Decode, 149, 2, 27, // Opcode: FSRA32 /* 3972 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3984 /* 3976 */ MCD_OPC_CheckPredicate, 2, 43, 7, // Skip to: 5815 /* 3980 */ MCD_OPC_Decode, 217, 1, 27, // Opcode: FMUL8X16 /* 3984 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 3996 /* 3988 */ MCD_OPC_CheckPredicate, 2, 31, 7, // Skip to: 5815 /* 3992 */ MCD_OPC_Decode, 219, 1, 27, // Opcode: FMUL8X16AU /* 3996 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 4008 /* 4000 */ MCD_OPC_CheckPredicate, 2, 19, 7, // Skip to: 5815 /* 4004 */ MCD_OPC_Decode, 218, 1, 27, // Opcode: FMUL8X16AL /* 4008 */ MCD_OPC_FilterValue, 54, 8, 0, // Skip to: 4020 /* 4012 */ MCD_OPC_CheckPredicate, 2, 7, 7, // Skip to: 5815 /* 4016 */ MCD_OPC_Decode, 215, 1, 27, // Opcode: FMUL8SUX16 /* 4020 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 4032 /* 4024 */ MCD_OPC_CheckPredicate, 2, 251, 6, // Skip to: 5815 /* 4028 */ MCD_OPC_Decode, 216, 1, 27, // Opcode: FMUL8ULX16 /* 4032 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 4044 /* 4036 */ MCD_OPC_CheckPredicate, 2, 239, 6, // Skip to: 5815 /* 4040 */ MCD_OPC_Decode, 221, 1, 27, // Opcode: FMULD8SUX16 /* 4044 */ MCD_OPC_FilterValue, 57, 8, 0, // Skip to: 4056 /* 4048 */ MCD_OPC_CheckPredicate, 2, 227, 6, // Skip to: 5815 /* 4052 */ MCD_OPC_Decode, 222, 1, 27, // Opcode: FMULD8ULX16 /* 4056 */ MCD_OPC_FilterValue, 58, 8, 0, // Skip to: 4068 /* 4060 */ MCD_OPC_CheckPredicate, 2, 215, 6, // Skip to: 5815 /* 4064 */ MCD_OPC_Decode, 252, 1, 27, // Opcode: FPACK32 /* 4068 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 4086 /* 4072 */ MCD_OPC_CheckPredicate, 2, 203, 6, // Skip to: 5815 /* 4076 */ MCD_OPC_CheckField, 14, 5, 0, 197, 6, // Skip to: 5815 /* 4082 */ MCD_OPC_Decode, 251, 1, 24, // Opcode: FPACK16 /* 4086 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 4104 /* 4090 */ MCD_OPC_CheckPredicate, 2, 185, 6, // Skip to: 5815 /* 4094 */ MCD_OPC_CheckField, 14, 5, 0, 179, 6, // Skip to: 5815 /* 4100 */ MCD_OPC_Decode, 253, 1, 24, // Opcode: FPACKFIX /* 4104 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 4116 /* 4108 */ MCD_OPC_CheckPredicate, 2, 167, 6, // Skip to: 5815 /* 4112 */ MCD_OPC_Decode, 236, 2, 27, // Opcode: PDIST /* 4116 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 4128 /* 4120 */ MCD_OPC_CheckPredicate, 1, 155, 6, // Skip to: 5815 /* 4124 */ MCD_OPC_Decode, 237, 2, 27, // Opcode: PDISTN /* 4128 */ MCD_OPC_FilterValue, 64, 8, 0, // Skip to: 4140 /* 4132 */ MCD_OPC_CheckPredicate, 1, 143, 6, // Skip to: 5815 /* 4136 */ MCD_OPC_Decode, 184, 1, 27, // Opcode: FMEAN16 /* 4140 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 4152 /* 4144 */ MCD_OPC_CheckPredicate, 1, 131, 6, // Skip to: 5815 /* 4148 */ MCD_OPC_Decode, 130, 2, 27, // Opcode: FPADD64 /* 4152 */ MCD_OPC_FilterValue, 68, 8, 0, // Skip to: 4164 /* 4156 */ MCD_OPC_CheckPredicate, 1, 119, 6, // Skip to: 5815 /* 4160 */ MCD_OPC_Decode, 153, 1, 27, // Opcode: FCHKSM16 /* 4164 */ MCD_OPC_FilterValue, 72, 8, 0, // Skip to: 4176 /* 4168 */ MCD_OPC_CheckPredicate, 2, 107, 6, // Skip to: 5815 /* 4172 */ MCD_OPC_Decode, 144, 1, 27, // Opcode: FALIGNADATA /* 4176 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 4188 /* 4180 */ MCD_OPC_CheckPredicate, 2, 95, 6, // Skip to: 5815 /* 4184 */ MCD_OPC_Decode, 131, 2, 27, // Opcode: FPMERGE /* 4188 */ MCD_OPC_FilterValue, 77, 14, 0, // Skip to: 4206 /* 4192 */ MCD_OPC_CheckPredicate, 2, 83, 6, // Skip to: 5815 /* 4196 */ MCD_OPC_CheckField, 14, 5, 0, 77, 6, // Skip to: 5815 /* 4202 */ MCD_OPC_Decode, 173, 1, 24, // Opcode: FEXPAND /* 4206 */ MCD_OPC_FilterValue, 80, 8, 0, // Skip to: 4218 /* 4210 */ MCD_OPC_CheckPredicate, 2, 65, 6, // Skip to: 5815 /* 4214 */ MCD_OPC_Decode, 254, 1, 27, // Opcode: FPADD16 /* 4218 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 4230 /* 4222 */ MCD_OPC_CheckPredicate, 2, 53, 6, // Skip to: 5815 /* 4226 */ MCD_OPC_Decode, 255, 1, 27, // Opcode: FPADD16S /* 4230 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 4242 /* 4234 */ MCD_OPC_CheckPredicate, 2, 41, 6, // Skip to: 5815 /* 4238 */ MCD_OPC_Decode, 128, 2, 27, // Opcode: FPADD32 /* 4242 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 4254 /* 4246 */ MCD_OPC_CheckPredicate, 2, 29, 6, // Skip to: 5815 /* 4250 */ MCD_OPC_Decode, 129, 2, 27, // Opcode: FPADD32S /* 4254 */ MCD_OPC_FilterValue, 84, 8, 0, // Skip to: 4266 /* 4258 */ MCD_OPC_CheckPredicate, 2, 17, 6, // Skip to: 5815 /* 4262 */ MCD_OPC_Decode, 132, 2, 27, // Opcode: FPSUB16 /* 4266 */ MCD_OPC_FilterValue, 85, 8, 0, // Skip to: 4278 /* 4270 */ MCD_OPC_CheckPredicate, 2, 5, 6, // Skip to: 5815 /* 4274 */ MCD_OPC_Decode, 133, 2, 27, // Opcode: FPSUB16S /* 4278 */ MCD_OPC_FilterValue, 86, 8, 0, // Skip to: 4290 /* 4282 */ MCD_OPC_CheckPredicate, 2, 249, 5, // Skip to: 5815 /* 4286 */ MCD_OPC_Decode, 134, 2, 27, // Opcode: FPSUB32 /* 4290 */ MCD_OPC_FilterValue, 87, 8, 0, // Skip to: 4302 /* 4294 */ MCD_OPC_CheckPredicate, 2, 237, 5, // Skip to: 5815 /* 4298 */ MCD_OPC_Decode, 135, 2, 27, // Opcode: FPSUB32S /* 4302 */ MCD_OPC_FilterValue, 96, 20, 0, // Skip to: 4326 /* 4306 */ MCD_OPC_CheckPredicate, 2, 225, 5, // Skip to: 5815 /* 4310 */ MCD_OPC_CheckField, 14, 5, 0, 219, 5, // Skip to: 5815 /* 4316 */ MCD_OPC_CheckField, 0, 5, 0, 213, 5, // Skip to: 5815 /* 4322 */ MCD_OPC_Decode, 170, 2, 50, // Opcode: FZERO /* 4326 */ MCD_OPC_FilterValue, 97, 20, 0, // Skip to: 4350 /* 4330 */ MCD_OPC_CheckPredicate, 2, 201, 5, // Skip to: 5815 /* 4334 */ MCD_OPC_CheckField, 14, 5, 0, 195, 5, // Skip to: 5815 /* 4340 */ MCD_OPC_CheckField, 0, 5, 0, 189, 5, // Skip to: 5815 /* 4346 */ MCD_OPC_Decode, 171, 2, 51, // Opcode: FZEROS /* 4350 */ MCD_OPC_FilterValue, 98, 8, 0, // Skip to: 4362 /* 4354 */ MCD_OPC_CheckPredicate, 2, 177, 5, // Skip to: 5815 /* 4358 */ MCD_OPC_Decode, 236, 1, 27, // Opcode: FNOR /* 4362 */ MCD_OPC_FilterValue, 99, 8, 0, // Skip to: 4374 /* 4366 */ MCD_OPC_CheckPredicate, 2, 165, 5, // Skip to: 5815 /* 4370 */ MCD_OPC_Decode, 237, 1, 26, // Opcode: FNORS /* 4374 */ MCD_OPC_FilterValue, 100, 8, 0, // Skip to: 4386 /* 4378 */ MCD_OPC_CheckPredicate, 2, 153, 5, // Skip to: 5815 /* 4382 */ MCD_OPC_Decode, 148, 1, 27, // Opcode: FANDNOT2 /* 4386 */ MCD_OPC_FilterValue, 101, 8, 0, // Skip to: 4398 /* 4390 */ MCD_OPC_CheckPredicate, 2, 141, 5, // Skip to: 5815 /* 4394 */ MCD_OPC_Decode, 149, 1, 26, // Opcode: FANDNOT2S /* 4398 */ MCD_OPC_FilterValue, 102, 14, 0, // Skip to: 4416 /* 4402 */ MCD_OPC_CheckPredicate, 2, 129, 5, // Skip to: 5815 /* 4406 */ MCD_OPC_CheckField, 14, 5, 0, 123, 5, // Skip to: 5815 /* 4412 */ MCD_OPC_Decode, 240, 1, 24, // Opcode: FNOT2 /* 4416 */ MCD_OPC_FilterValue, 103, 14, 0, // Skip to: 4434 /* 4420 */ MCD_OPC_CheckPredicate, 2, 111, 5, // Skip to: 5815 /* 4424 */ MCD_OPC_CheckField, 14, 5, 0, 105, 5, // Skip to: 5815 /* 4430 */ MCD_OPC_Decode, 241, 1, 23, // Opcode: FNOT2S /* 4434 */ MCD_OPC_FilterValue, 104, 8, 0, // Skip to: 4446 /* 4438 */ MCD_OPC_CheckPredicate, 2, 93, 5, // Skip to: 5815 /* 4442 */ MCD_OPC_Decode, 146, 1, 27, // Opcode: FANDNOT1 /* 4446 */ MCD_OPC_FilterValue, 105, 8, 0, // Skip to: 4458 /* 4450 */ MCD_OPC_CheckPredicate, 2, 81, 5, // Skip to: 5815 /* 4454 */ MCD_OPC_Decode, 147, 1, 26, // Opcode: FANDNOT1S /* 4458 */ MCD_OPC_FilterValue, 106, 14, 0, // Skip to: 4476 /* 4462 */ MCD_OPC_CheckPredicate, 2, 69, 5, // Skip to: 5815 /* 4466 */ MCD_OPC_CheckField, 0, 5, 0, 63, 5, // Skip to: 5815 /* 4472 */ MCD_OPC_Decode, 238, 1, 52, // Opcode: FNOT1 /* 4476 */ MCD_OPC_FilterValue, 107, 14, 0, // Skip to: 4494 /* 4480 */ MCD_OPC_CheckPredicate, 2, 51, 5, // Skip to: 5815 /* 4484 */ MCD_OPC_CheckField, 0, 5, 0, 45, 5, // Skip to: 5815 /* 4490 */ MCD_OPC_Decode, 239, 1, 53, // Opcode: FNOT1S /* 4494 */ MCD_OPC_FilterValue, 108, 8, 0, // Skip to: 4506 /* 4498 */ MCD_OPC_CheckPredicate, 2, 33, 5, // Skip to: 5815 /* 4502 */ MCD_OPC_Decode, 165, 2, 27, // Opcode: FXOR /* 4506 */ MCD_OPC_FilterValue, 109, 8, 0, // Skip to: 4518 /* 4510 */ MCD_OPC_CheckPredicate, 2, 21, 5, // Skip to: 5815 /* 4514 */ MCD_OPC_Decode, 166, 2, 26, // Opcode: FXORS /* 4518 */ MCD_OPC_FilterValue, 110, 8, 0, // Skip to: 4530 /* 4522 */ MCD_OPC_CheckPredicate, 2, 9, 5, // Skip to: 5815 /* 4526 */ MCD_OPC_Decode, 227, 1, 27, // Opcode: FNAND /* 4530 */ MCD_OPC_FilterValue, 111, 8, 0, // Skip to: 4542 /* 4534 */ MCD_OPC_CheckPredicate, 2, 253, 4, // Skip to: 5815 /* 4538 */ MCD_OPC_Decode, 228, 1, 26, // Opcode: FNANDS /* 4542 */ MCD_OPC_FilterValue, 112, 8, 0, // Skip to: 4554 /* 4546 */ MCD_OPC_CheckPredicate, 2, 241, 4, // Skip to: 5815 /* 4550 */ MCD_OPC_Decode, 145, 1, 27, // Opcode: FAND /* 4554 */ MCD_OPC_FilterValue, 113, 8, 0, // Skip to: 4566 /* 4558 */ MCD_OPC_CheckPredicate, 2, 229, 4, // Skip to: 5815 /* 4562 */ MCD_OPC_Decode, 150, 1, 26, // Opcode: FANDS /* 4566 */ MCD_OPC_FilterValue, 114, 8, 0, // Skip to: 4578 /* 4570 */ MCD_OPC_CheckPredicate, 2, 217, 4, // Skip to: 5815 /* 4574 */ MCD_OPC_Decode, 163, 2, 27, // Opcode: FXNOR /* 4578 */ MCD_OPC_FilterValue, 115, 8, 0, // Skip to: 4590 /* 4582 */ MCD_OPC_CheckPredicate, 2, 205, 4, // Skip to: 5815 /* 4586 */ MCD_OPC_Decode, 164, 2, 26, // Opcode: FXNORS /* 4590 */ MCD_OPC_FilterValue, 116, 14, 0, // Skip to: 4608 /* 4594 */ MCD_OPC_CheckPredicate, 2, 193, 4, // Skip to: 5815 /* 4598 */ MCD_OPC_CheckField, 0, 5, 0, 187, 4, // Skip to: 5815 /* 4604 */ MCD_OPC_Decode, 150, 2, 52, // Opcode: FSRC1 /* 4608 */ MCD_OPC_FilterValue, 117, 14, 0, // Skip to: 4626 /* 4612 */ MCD_OPC_CheckPredicate, 2, 175, 4, // Skip to: 5815 /* 4616 */ MCD_OPC_CheckField, 0, 5, 0, 169, 4, // Skip to: 5815 /* 4622 */ MCD_OPC_Decode, 151, 2, 53, // Opcode: FSRC1S /* 4626 */ MCD_OPC_FilterValue, 118, 8, 0, // Skip to: 4638 /* 4630 */ MCD_OPC_CheckPredicate, 2, 157, 4, // Skip to: 5815 /* 4634 */ MCD_OPC_Decode, 248, 1, 27, // Opcode: FORNOT2 /* 4638 */ MCD_OPC_FilterValue, 119, 8, 0, // Skip to: 4650 /* 4642 */ MCD_OPC_CheckPredicate, 2, 145, 4, // Skip to: 5815 /* 4646 */ MCD_OPC_Decode, 249, 1, 26, // Opcode: FORNOT2S /* 4650 */ MCD_OPC_FilterValue, 120, 14, 0, // Skip to: 4668 /* 4654 */ MCD_OPC_CheckPredicate, 2, 133, 4, // Skip to: 5815 /* 4658 */ MCD_OPC_CheckField, 14, 5, 0, 127, 4, // Skip to: 5815 /* 4664 */ MCD_OPC_Decode, 152, 2, 24, // Opcode: FSRC2 /* 4668 */ MCD_OPC_FilterValue, 121, 14, 0, // Skip to: 4686 /* 4672 */ MCD_OPC_CheckPredicate, 2, 115, 4, // Skip to: 5815 /* 4676 */ MCD_OPC_CheckField, 14, 5, 0, 109, 4, // Skip to: 5815 /* 4682 */ MCD_OPC_Decode, 153, 2, 23, // Opcode: FSRC2S /* 4686 */ MCD_OPC_FilterValue, 122, 8, 0, // Skip to: 4698 /* 4690 */ MCD_OPC_CheckPredicate, 2, 97, 4, // Skip to: 5815 /* 4694 */ MCD_OPC_Decode, 246, 1, 27, // Opcode: FORNOT1 /* 4698 */ MCD_OPC_FilterValue, 123, 8, 0, // Skip to: 4710 /* 4702 */ MCD_OPC_CheckPredicate, 2, 85, 4, // Skip to: 5815 /* 4706 */ MCD_OPC_Decode, 247, 1, 26, // Opcode: FORNOT1S /* 4710 */ MCD_OPC_FilterValue, 124, 8, 0, // Skip to: 4722 /* 4714 */ MCD_OPC_CheckPredicate, 2, 73, 4, // Skip to: 5815 /* 4718 */ MCD_OPC_Decode, 245, 1, 27, // Opcode: FOR /* 4722 */ MCD_OPC_FilterValue, 125, 8, 0, // Skip to: 4734 /* 4726 */ MCD_OPC_CheckPredicate, 2, 61, 4, // Skip to: 5815 /* 4730 */ MCD_OPC_Decode, 250, 1, 26, // Opcode: FORS /* 4734 */ MCD_OPC_FilterValue, 126, 20, 0, // Skip to: 4758 /* 4738 */ MCD_OPC_CheckPredicate, 2, 49, 4, // Skip to: 5815 /* 4742 */ MCD_OPC_CheckField, 14, 5, 0, 43, 4, // Skip to: 5815 /* 4748 */ MCD_OPC_CheckField, 0, 5, 0, 37, 4, // Skip to: 5815 /* 4754 */ MCD_OPC_Decode, 243, 1, 50, // Opcode: FONE /* 4758 */ MCD_OPC_FilterValue, 127, 20, 0, // Skip to: 4782 /* 4762 */ MCD_OPC_CheckPredicate, 2, 25, 4, // Skip to: 5815 /* 4766 */ MCD_OPC_CheckField, 14, 5, 0, 19, 4, // Skip to: 5815 /* 4772 */ MCD_OPC_CheckField, 0, 5, 0, 13, 4, // Skip to: 5815 /* 4778 */ MCD_OPC_Decode, 244, 1, 51, // Opcode: FONES /* 4782 */ MCD_OPC_FilterValue, 128, 1, 26, 0, // Skip to: 4813 /* 4787 */ MCD_OPC_CheckPredicate, 2, 0, 4, // Skip to: 5815 /* 4791 */ MCD_OPC_CheckField, 25, 5, 0, 250, 3, // Skip to: 5815 /* 4797 */ MCD_OPC_CheckField, 14, 5, 0, 244, 3, // Skip to: 5815 /* 4803 */ MCD_OPC_CheckField, 0, 5, 0, 238, 3, // Skip to: 5815 /* 4809 */ MCD_OPC_Decode, 136, 3, 4, // Opcode: SHUTDOWN /* 4813 */ MCD_OPC_FilterValue, 129, 1, 26, 0, // Skip to: 4844 /* 4818 */ MCD_OPC_CheckPredicate, 3, 225, 3, // Skip to: 5815 /* 4822 */ MCD_OPC_CheckField, 25, 5, 0, 219, 3, // Skip to: 5815 /* 4828 */ MCD_OPC_CheckField, 14, 5, 0, 213, 3, // Skip to: 5815 /* 4834 */ MCD_OPC_CheckField, 0, 5, 0, 207, 3, // Skip to: 5815 /* 4840 */ MCD_OPC_Decode, 137, 3, 4, // Opcode: SIAM /* 4844 */ MCD_OPC_FilterValue, 144, 2, 14, 0, // Skip to: 4863 /* 4849 */ MCD_OPC_CheckPredicate, 1, 194, 3, // Skip to: 5815 /* 4853 */ MCD_OPC_CheckField, 14, 5, 0, 188, 3, // Skip to: 5815 /* 4859 */ MCD_OPC_Decode, 199, 2, 54, // Opcode: MOVDTOX /* 4863 */ MCD_OPC_FilterValue, 145, 2, 14, 0, // Skip to: 4882 /* 4868 */ MCD_OPC_CheckPredicate, 1, 175, 3, // Skip to: 5815 /* 4872 */ MCD_OPC_CheckField, 14, 5, 0, 169, 3, // Skip to: 5815 /* 4878 */ MCD_OPC_Decode, 217, 2, 54, // Opcode: MOVSTOUW /* 4882 */ MCD_OPC_FilterValue, 147, 2, 14, 0, // Skip to: 4901 /* 4887 */ MCD_OPC_CheckPredicate, 1, 156, 3, // Skip to: 5815 /* 4891 */ MCD_OPC_CheckField, 14, 5, 0, 150, 3, // Skip to: 5815 /* 4897 */ MCD_OPC_Decode, 216, 2, 54, // Opcode: MOVSTOSW /* 4901 */ MCD_OPC_FilterValue, 149, 2, 8, 0, // Skip to: 4914 /* 4906 */ MCD_OPC_CheckPredicate, 1, 137, 3, // Skip to: 5815 /* 4910 */ MCD_OPC_Decode, 225, 3, 10, // Opcode: XMULX /* 4914 */ MCD_OPC_FilterValue, 151, 2, 8, 0, // Skip to: 4927 /* 4919 */ MCD_OPC_CheckPredicate, 1, 124, 3, // Skip to: 5815 /* 4923 */ MCD_OPC_Decode, 226, 3, 10, // Opcode: XMULXHI /* 4927 */ MCD_OPC_FilterValue, 152, 2, 14, 0, // Skip to: 4946 /* 4932 */ MCD_OPC_CheckPredicate, 1, 111, 3, // Skip to: 5815 /* 4936 */ MCD_OPC_CheckField, 14, 5, 0, 105, 3, // Skip to: 5815 /* 4942 */ MCD_OPC_Decode, 221, 2, 55, // Opcode: MOVXTOD /* 4946 */ MCD_OPC_FilterValue, 153, 2, 14, 0, // Skip to: 4965 /* 4951 */ MCD_OPC_CheckPredicate, 1, 92, 3, // Skip to: 5815 /* 4955 */ MCD_OPC_CheckField, 14, 5, 0, 86, 3, // Skip to: 5815 /* 4961 */ MCD_OPC_Decode, 218, 2, 55, // Opcode: MOVWTOS /* 4965 */ MCD_OPC_FilterValue, 209, 2, 8, 0, // Skip to: 4978 /* 4970 */ MCD_OPC_CheckPredicate, 1, 73, 3, // Skip to: 5815 /* 4974 */ MCD_OPC_Decode, 182, 1, 45, // Opcode: FLCMPS /* 4978 */ MCD_OPC_FilterValue, 210, 2, 64, 3, // Skip to: 5815 /* 4983 */ MCD_OPC_CheckPredicate, 1, 60, 3, // Skip to: 5815 /* 4987 */ MCD_OPC_Decode, 181, 1, 45, // Opcode: FLCMPD /* 4991 */ MCD_OPC_FilterValue, 56, 25, 0, // Skip to: 5020 /* 4995 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 4998 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5012 /* 5002 */ MCD_OPC_CheckField, 5, 8, 0, 39, 3, // Skip to: 5815 /* 5008 */ MCD_OPC_Decode, 174, 2, 56, // Opcode: JMPLrr /* 5012 */ MCD_OPC_FilterValue, 1, 31, 3, // Skip to: 5815 /* 5016 */ MCD_OPC_Decode, 173, 2, 56, // Opcode: JMPLri /* 5020 */ MCD_OPC_FilterValue, 57, 37, 0, // Skip to: 5061 /* 5024 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5027 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5047 /* 5031 */ MCD_OPC_CheckField, 25, 5, 0, 10, 3, // Skip to: 5815 /* 5037 */ MCD_OPC_CheckField, 5, 8, 0, 4, 3, // Skip to: 5815 /* 5043 */ MCD_OPC_Decode, 245, 2, 57, // Opcode: RETTrr /* 5047 */ MCD_OPC_FilterValue, 1, 252, 2, // Skip to: 5815 /* 5051 */ MCD_OPC_CheckField, 25, 5, 0, 246, 2, // Skip to: 5815 /* 5057 */ MCD_OPC_Decode, 244, 2, 57, // Opcode: RETTri /* 5061 */ MCD_OPC_FilterValue, 58, 115, 0, // Skip to: 5180 /* 5065 */ MCD_OPC_ExtractField, 8, 6, // Inst{13-8} ... /* 5068 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 5088 /* 5072 */ MCD_OPC_CheckField, 29, 1, 0, 225, 2, // Skip to: 5815 /* 5078 */ MCD_OPC_CheckField, 5, 3, 0, 219, 2, // Skip to: 5815 /* 5084 */ MCD_OPC_Decode, 188, 3, 58, // Opcode: TICCrr /* 5088 */ MCD_OPC_FilterValue, 16, 16, 0, // Skip to: 5108 /* 5092 */ MCD_OPC_CheckField, 29, 1, 0, 205, 2, // Skip to: 5815 /* 5098 */ MCD_OPC_CheckField, 5, 3, 0, 199, 2, // Skip to: 5815 /* 5104 */ MCD_OPC_Decode, 199, 3, 58, // Opcode: TXCCrr /* 5108 */ MCD_OPC_FilterValue, 32, 54, 0, // Skip to: 5166 /* 5112 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... /* 5115 */ MCD_OPC_FilterValue, 0, 184, 2, // Skip to: 5815 /* 5119 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 5122 */ MCD_OPC_FilterValue, 3, 16, 0, // Skip to: 5142 /* 5126 */ MCD_OPC_CheckField, 25, 4, 0, 30, 0, // Skip to: 5162 /* 5132 */ MCD_OPC_CheckField, 14, 5, 1, 24, 0, // Skip to: 5162 /* 5138 */ MCD_OPC_Decode, 181, 3, 4, // Opcode: TA3 /* 5142 */ MCD_OPC_FilterValue, 5, 16, 0, // Skip to: 5162 /* 5146 */ MCD_OPC_CheckField, 25, 4, 8, 10, 0, // Skip to: 5162 /* 5152 */ MCD_OPC_CheckField, 14, 5, 0, 4, 0, // Skip to: 5162 /* 5158 */ MCD_OPC_Decode, 182, 3, 4, // Opcode: TA5 /* 5162 */ MCD_OPC_Decode, 187, 3, 59, // Opcode: TICCri /* 5166 */ MCD_OPC_FilterValue, 48, 133, 2, // Skip to: 5815 /* 5170 */ MCD_OPC_CheckField, 29, 1, 0, 127, 2, // Skip to: 5815 /* 5176 */ MCD_OPC_Decode, 198, 3, 59, // Opcode: TXCCri /* 5180 */ MCD_OPC_FilterValue, 60, 25, 0, // Skip to: 5209 /* 5184 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5187 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5201 /* 5191 */ MCD_OPC_CheckField, 5, 8, 0, 106, 2, // Skip to: 5815 /* 5197 */ MCD_OPC_Decode, 247, 2, 8, // Opcode: SAVErr /* 5201 */ MCD_OPC_FilterValue, 1, 98, 2, // Skip to: 5815 /* 5205 */ MCD_OPC_Decode, 246, 2, 9, // Opcode: SAVEri /* 5209 */ MCD_OPC_FilterValue, 61, 90, 2, // Skip to: 5815 /* 5213 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5216 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5230 /* 5220 */ MCD_OPC_CheckField, 5, 8, 0, 77, 2, // Skip to: 5815 /* 5226 */ MCD_OPC_Decode, 241, 2, 8, // Opcode: RESTORErr /* 5230 */ MCD_OPC_FilterValue, 1, 69, 2, // Skip to: 5815 /* 5234 */ MCD_OPC_Decode, 240, 2, 9, // Opcode: RESTOREri /* 5238 */ MCD_OPC_FilterValue, 3, 61, 2, // Skip to: 5815 /* 5242 */ MCD_OPC_ExtractField, 19, 6, // Inst{24-19} ... /* 5245 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 5274 /* 5249 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5252 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5266 /* 5256 */ MCD_OPC_CheckField, 5, 8, 0, 41, 2, // Skip to: 5815 /* 5262 */ MCD_OPC_Decode, 194, 2, 60, // Opcode: LDrr /* 5266 */ MCD_OPC_FilterValue, 1, 33, 2, // Skip to: 5815 /* 5270 */ MCD_OPC_Decode, 193, 2, 60, // Opcode: LDri /* 5274 */ MCD_OPC_FilterValue, 1, 25, 0, // Skip to: 5303 /* 5278 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5281 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5295 /* 5285 */ MCD_OPC_CheckField, 5, 8, 0, 12, 2, // Skip to: 5815 /* 5291 */ MCD_OPC_Decode, 188, 2, 60, // Opcode: LDUBrr /* 5295 */ MCD_OPC_FilterValue, 1, 4, 2, // Skip to: 5815 /* 5299 */ MCD_OPC_Decode, 187, 2, 60, // Opcode: LDUBri /* 5303 */ MCD_OPC_FilterValue, 2, 25, 0, // Skip to: 5332 /* 5307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5310 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5324 /* 5314 */ MCD_OPC_CheckField, 5, 8, 0, 239, 1, // Skip to: 5815 /* 5320 */ MCD_OPC_Decode, 190, 2, 60, // Opcode: LDUHrr /* 5324 */ MCD_OPC_FilterValue, 1, 231, 1, // Skip to: 5815 /* 5328 */ MCD_OPC_Decode, 189, 2, 60, // Opcode: LDUHri /* 5332 */ MCD_OPC_FilterValue, 4, 25, 0, // Skip to: 5361 /* 5336 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5339 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5353 /* 5343 */ MCD_OPC_CheckField, 5, 8, 0, 210, 1, // Skip to: 5815 /* 5349 */ MCD_OPC_Decode, 168, 3, 61, // Opcode: STrr /* 5353 */ MCD_OPC_FilterValue, 1, 202, 1, // Skip to: 5815 /* 5357 */ MCD_OPC_Decode, 167, 3, 61, // Opcode: STri /* 5361 */ MCD_OPC_FilterValue, 5, 25, 0, // Skip to: 5390 /* 5365 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5368 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5382 /* 5372 */ MCD_OPC_CheckField, 5, 8, 0, 181, 1, // Skip to: 5815 /* 5378 */ MCD_OPC_Decode, 156, 3, 61, // Opcode: STBrr /* 5382 */ MCD_OPC_FilterValue, 1, 173, 1, // Skip to: 5815 /* 5386 */ MCD_OPC_Decode, 155, 3, 61, // Opcode: STBri /* 5390 */ MCD_OPC_FilterValue, 6, 25, 0, // Skip to: 5419 /* 5394 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5397 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5411 /* 5401 */ MCD_OPC_CheckField, 5, 8, 0, 152, 1, // Skip to: 5815 /* 5407 */ MCD_OPC_Decode, 162, 3, 61, // Opcode: STHrr /* 5411 */ MCD_OPC_FilterValue, 1, 144, 1, // Skip to: 5815 /* 5415 */ MCD_OPC_Decode, 161, 3, 61, // Opcode: STHri /* 5419 */ MCD_OPC_FilterValue, 8, 25, 0, // Skip to: 5448 /* 5423 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5426 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5440 /* 5430 */ MCD_OPC_CheckField, 5, 8, 0, 123, 1, // Skip to: 5815 /* 5436 */ MCD_OPC_Decode, 186, 2, 60, // Opcode: LDSWrr /* 5440 */ MCD_OPC_FilterValue, 1, 115, 1, // Skip to: 5815 /* 5444 */ MCD_OPC_Decode, 185, 2, 60, // Opcode: LDSWri /* 5448 */ MCD_OPC_FilterValue, 9, 25, 0, // Skip to: 5477 /* 5452 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5455 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5469 /* 5459 */ MCD_OPC_CheckField, 5, 8, 0, 94, 1, // Skip to: 5815 /* 5465 */ MCD_OPC_Decode, 182, 2, 60, // Opcode: LDSBrr /* 5469 */ MCD_OPC_FilterValue, 1, 86, 1, // Skip to: 5815 /* 5473 */ MCD_OPC_Decode, 181, 2, 60, // Opcode: LDSBri /* 5477 */ MCD_OPC_FilterValue, 10, 25, 0, // Skip to: 5506 /* 5481 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5498 /* 5488 */ MCD_OPC_CheckField, 5, 8, 0, 65, 1, // Skip to: 5815 /* 5494 */ MCD_OPC_Decode, 184, 2, 60, // Opcode: LDSHrr /* 5498 */ MCD_OPC_FilterValue, 1, 57, 1, // Skip to: 5815 /* 5502 */ MCD_OPC_Decode, 183, 2, 60, // Opcode: LDSHri /* 5506 */ MCD_OPC_FilterValue, 11, 25, 0, // Skip to: 5535 /* 5510 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5513 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5527 /* 5517 */ MCD_OPC_CheckField, 5, 8, 0, 36, 1, // Skip to: 5815 /* 5523 */ MCD_OPC_Decode, 192, 2, 60, // Opcode: LDXrr /* 5527 */ MCD_OPC_FilterValue, 1, 28, 1, // Skip to: 5815 /* 5531 */ MCD_OPC_Decode, 191, 2, 60, // Opcode: LDXri /* 5535 */ MCD_OPC_FilterValue, 14, 25, 0, // Skip to: 5564 /* 5539 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5542 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5556 /* 5546 */ MCD_OPC_CheckField, 5, 8, 0, 7, 1, // Skip to: 5815 /* 5552 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: STXrr /* 5556 */ MCD_OPC_FilterValue, 1, 255, 0, // Skip to: 5815 /* 5560 */ MCD_OPC_Decode, 165, 3, 61, // Opcode: STXri /* 5564 */ MCD_OPC_FilterValue, 15, 25, 0, // Skip to: 5593 /* 5568 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5571 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5585 /* 5575 */ MCD_OPC_CheckField, 5, 8, 0, 234, 0, // Skip to: 5815 /* 5581 */ MCD_OPC_Decode, 180, 3, 62, // Opcode: SWAPrr /* 5585 */ MCD_OPC_FilterValue, 1, 226, 0, // Skip to: 5815 /* 5589 */ MCD_OPC_Decode, 179, 3, 62, // Opcode: SWAPri /* 5593 */ MCD_OPC_FilterValue, 32, 25, 0, // Skip to: 5622 /* 5597 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5600 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5614 /* 5604 */ MCD_OPC_CheckField, 5, 8, 0, 205, 0, // Skip to: 5815 /* 5610 */ MCD_OPC_Decode, 178, 2, 63, // Opcode: LDFrr /* 5614 */ MCD_OPC_FilterValue, 1, 197, 0, // Skip to: 5815 /* 5618 */ MCD_OPC_Decode, 177, 2, 63, // Opcode: LDFri /* 5622 */ MCD_OPC_FilterValue, 34, 33, 0, // Skip to: 5659 /* 5626 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5629 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5647 /* 5633 */ MCD_OPC_CheckPredicate, 0, 178, 0, // Skip to: 5815 /* 5637 */ MCD_OPC_CheckField, 5, 8, 0, 172, 0, // Skip to: 5815 /* 5643 */ MCD_OPC_Decode, 180, 2, 64, // Opcode: LDQFrr /* 5647 */ MCD_OPC_FilterValue, 1, 164, 0, // Skip to: 5815 /* 5651 */ MCD_OPC_CheckPredicate, 0, 160, 0, // Skip to: 5815 /* 5655 */ MCD_OPC_Decode, 179, 2, 64, // Opcode: LDQFri /* 5659 */ MCD_OPC_FilterValue, 35, 25, 0, // Skip to: 5688 /* 5663 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5666 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5680 /* 5670 */ MCD_OPC_CheckField, 5, 8, 0, 139, 0, // Skip to: 5815 /* 5676 */ MCD_OPC_Decode, 176, 2, 65, // Opcode: LDDFrr /* 5680 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 5815 /* 5684 */ MCD_OPC_Decode, 175, 2, 65, // Opcode: LDDFri /* 5688 */ MCD_OPC_FilterValue, 36, 25, 0, // Skip to: 5717 /* 5692 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5695 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5709 /* 5699 */ MCD_OPC_CheckField, 5, 8, 0, 110, 0, // Skip to: 5815 /* 5705 */ MCD_OPC_Decode, 160, 3, 66, // Opcode: STFrr /* 5709 */ MCD_OPC_FilterValue, 1, 102, 0, // Skip to: 5815 /* 5713 */ MCD_OPC_Decode, 159, 3, 66, // Opcode: STFri /* 5717 */ MCD_OPC_FilterValue, 38, 33, 0, // Skip to: 5754 /* 5721 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5742 /* 5728 */ MCD_OPC_CheckPredicate, 0, 83, 0, // Skip to: 5815 /* 5732 */ MCD_OPC_CheckField, 5, 8, 0, 77, 0, // Skip to: 5815 /* 5738 */ MCD_OPC_Decode, 164, 3, 67, // Opcode: STQFrr /* 5742 */ MCD_OPC_FilterValue, 1, 69, 0, // Skip to: 5815 /* 5746 */ MCD_OPC_CheckPredicate, 0, 65, 0, // Skip to: 5815 /* 5750 */ MCD_OPC_Decode, 163, 3, 67, // Opcode: STQFri /* 5754 */ MCD_OPC_FilterValue, 39, 25, 0, // Skip to: 5783 /* 5758 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... /* 5761 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5775 /* 5765 */ MCD_OPC_CheckField, 5, 8, 0, 44, 0, // Skip to: 5815 /* 5771 */ MCD_OPC_Decode, 158, 3, 68, // Opcode: STDFrr /* 5775 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 5815 /* 5779 */ MCD_OPC_Decode, 157, 3, 68, // Opcode: STDFri /* 5783 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 5801 /* 5787 */ MCD_OPC_CheckPredicate, 0, 24, 0, // Skip to: 5815 /* 5791 */ MCD_OPC_CheckField, 5, 9, 128, 1, 17, 0, // Skip to: 5815 /* 5798 */ MCD_OPC_Decode, 120, 69, // Opcode: CASrr /* 5801 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 5815 /* 5805 */ MCD_OPC_CheckField, 5, 9, 128, 1, 3, 0, // Skip to: 5815 /* 5812 */ MCD_OPC_Decode, 119, 70, // Opcode: CASXrr /* 5815 */ MCD_OPC_Fail, 0 }; static bool getbool(uint64_t b) { return b != 0; } static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { default: // llvm_unreachable("Invalid index!"); case 0: return getbool(Bits & Sparc_FeatureV9); case 1: return getbool(Bits & Sparc_FeatureVIS3); case 2: return getbool(Bits & Sparc_FeatureVIS); case 3: return getbool(Bits & Sparc_FeatureVIS2); } } #define DecodeToMCInst(fname,fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, const void *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ default: \ case 0: \ tmp = fieldname(insn, 0, 22); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 1: \ tmp = fieldname(insn, 0, 19); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 25, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 2: \ tmp = fieldname(insn, 0, 22); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 25, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 3: \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 0, 14) << 0; \ tmp |= fieldname(insn, 20, 2) << 14; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 4: \ return S; \ case 5: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 22); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 6: \ tmp = fieldname(insn, 0, 19); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 25, 4); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 20, 2); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 7: \ tmp = fieldname(insn, 0, 30); \ if (DecodeCall(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 8: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 9: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 13); \ if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 10: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 11: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 13); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 12: \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 13: \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 13); \ if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 14: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 15: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 16: \ tmp = fieldname(insn, 0, 13); \ if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 17: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 18: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 19: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 11); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 20: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 11); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 21: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 22: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 23: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 24: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 25: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 26: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 27: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 28: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 29: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 30: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 31: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 32: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 33: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 34: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 35: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 36: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 37: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 38: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 39: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 40: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 41: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 42: \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 11, 2); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 43: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 44: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 45: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 46: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 47: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 48: \ tmp = fieldname(insn, 0, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 49: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 50: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 51: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 52: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 53: \ tmp = fieldname(insn, 25, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 54: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 55: \ tmp = fieldname(insn, 25, 5); \ if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 56: \ if (DecodeJMPL(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 57: \ if (DecodeReturn(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 58: \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 59: \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 8); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 25, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 60: \ if (DecodeLoadInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 61: \ if (DecodeStoreInt(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 62: \ if (DecodeSWAP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 63: \ if (DecodeLoadFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 64: \ if (DecodeLoadQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 65: \ if (DecodeLoadDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 66: \ if (DecodeStoreFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 67: \ if (DecodeStoreQFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 68: \ if (DecodeStoreDFP(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 69: \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 70: \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 14, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 25, 5); \ if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ { \ uint64_t Bits = getFeatureBits(feature); \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0, ExpectedValue; \ DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail; \ for (;;) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ Pred = checkDecoderPredicate(PIdx, Bits); \ if (!Pred) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_setOpcode(MI, Opc); \ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ } \ case MCD_OPC_SoftFail: { \ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ } FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) capstone-sys-0.15.0/capstone/arch/Sparc/SparcGenInstrInfo.inc000064400000000000000000000267570072674642500222420ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Instruction Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { SP_PHI = 0, SP_INLINEASM = 1, SP_CFI_INSTRUCTION = 2, SP_EH_LABEL = 3, SP_GC_LABEL = 4, SP_KILL = 5, SP_EXTRACT_SUBREG = 6, SP_INSERT_SUBREG = 7, SP_IMPLICIT_DEF = 8, SP_SUBREG_TO_REG = 9, SP_COPY_TO_REGCLASS = 10, SP_DBG_VALUE = 11, SP_REG_SEQUENCE = 12, SP_COPY = 13, SP_BUNDLE = 14, SP_LIFETIME_START = 15, SP_LIFETIME_END = 16, SP_STACKMAP = 17, SP_PATCHPOINT = 18, SP_LOAD_STACK_GUARD = 19, SP_STATEPOINT = 20, SP_FRAME_ALLOC = 21, SP_ADDCCri = 22, SP_ADDCCrr = 23, SP_ADDCri = 24, SP_ADDCrr = 25, SP_ADDEri = 26, SP_ADDErr = 27, SP_ADDXC = 28, SP_ADDXCCC = 29, SP_ADDXri = 30, SP_ADDXrr = 31, SP_ADDri = 32, SP_ADDrr = 33, SP_ADJCALLSTACKDOWN = 34, SP_ADJCALLSTACKUP = 35, SP_ALIGNADDR = 36, SP_ALIGNADDRL = 37, SP_ANDCCri = 38, SP_ANDCCrr = 39, SP_ANDNCCri = 40, SP_ANDNCCrr = 41, SP_ANDNri = 42, SP_ANDNrr = 43, SP_ANDXNrr = 44, SP_ANDXri = 45, SP_ANDXrr = 46, SP_ANDri = 47, SP_ANDrr = 48, SP_ARRAY16 = 49, SP_ARRAY32 = 50, SP_ARRAY8 = 51, SP_ATOMIC_LOAD_ADD_32 = 52, SP_ATOMIC_LOAD_ADD_64 = 53, SP_ATOMIC_LOAD_AND_32 = 54, SP_ATOMIC_LOAD_AND_64 = 55, SP_ATOMIC_LOAD_MAX_32 = 56, SP_ATOMIC_LOAD_MAX_64 = 57, SP_ATOMIC_LOAD_MIN_32 = 58, SP_ATOMIC_LOAD_MIN_64 = 59, SP_ATOMIC_LOAD_NAND_32 = 60, SP_ATOMIC_LOAD_NAND_64 = 61, SP_ATOMIC_LOAD_OR_32 = 62, SP_ATOMIC_LOAD_OR_64 = 63, SP_ATOMIC_LOAD_SUB_32 = 64, SP_ATOMIC_LOAD_SUB_64 = 65, SP_ATOMIC_LOAD_UMAX_32 = 66, SP_ATOMIC_LOAD_UMAX_64 = 67, SP_ATOMIC_LOAD_UMIN_32 = 68, SP_ATOMIC_LOAD_UMIN_64 = 69, SP_ATOMIC_LOAD_XOR_32 = 70, SP_ATOMIC_LOAD_XOR_64 = 71, SP_ATOMIC_SWAP_64 = 72, SP_BA = 73, SP_BCOND = 74, SP_BCONDA = 75, SP_BINDri = 76, SP_BINDrr = 77, SP_BMASK = 78, SP_BPFCC = 79, SP_BPFCCA = 80, SP_BPFCCANT = 81, SP_BPFCCNT = 82, SP_BPGEZapn = 83, SP_BPGEZapt = 84, SP_BPGEZnapn = 85, SP_BPGEZnapt = 86, SP_BPGZapn = 87, SP_BPGZapt = 88, SP_BPGZnapn = 89, SP_BPGZnapt = 90, SP_BPICC = 91, SP_BPICCA = 92, SP_BPICCANT = 93, SP_BPICCNT = 94, SP_BPLEZapn = 95, SP_BPLEZapt = 96, SP_BPLEZnapn = 97, SP_BPLEZnapt = 98, SP_BPLZapn = 99, SP_BPLZapt = 100, SP_BPLZnapn = 101, SP_BPLZnapt = 102, SP_BPNZapn = 103, SP_BPNZapt = 104, SP_BPNZnapn = 105, SP_BPNZnapt = 106, SP_BPXCC = 107, SP_BPXCCA = 108, SP_BPXCCANT = 109, SP_BPXCCNT = 110, SP_BPZapn = 111, SP_BPZapt = 112, SP_BPZnapn = 113, SP_BPZnapt = 114, SP_BSHUFFLE = 115, SP_CALL = 116, SP_CALLri = 117, SP_CALLrr = 118, SP_CASXrr = 119, SP_CASrr = 120, SP_CMASK16 = 121, SP_CMASK32 = 122, SP_CMASK8 = 123, SP_CMPri = 124, SP_CMPrr = 125, SP_EDGE16 = 126, SP_EDGE16L = 127, SP_EDGE16LN = 128, SP_EDGE16N = 129, SP_EDGE32 = 130, SP_EDGE32L = 131, SP_EDGE32LN = 132, SP_EDGE32N = 133, SP_EDGE8 = 134, SP_EDGE8L = 135, SP_EDGE8LN = 136, SP_EDGE8N = 137, SP_FABSD = 138, SP_FABSQ = 139, SP_FABSS = 140, SP_FADDD = 141, SP_FADDQ = 142, SP_FADDS = 143, SP_FALIGNADATA = 144, SP_FAND = 145, SP_FANDNOT1 = 146, SP_FANDNOT1S = 147, SP_FANDNOT2 = 148, SP_FANDNOT2S = 149, SP_FANDS = 150, SP_FBCOND = 151, SP_FBCONDA = 152, SP_FCHKSM16 = 153, SP_FCMPD = 154, SP_FCMPEQ16 = 155, SP_FCMPEQ32 = 156, SP_FCMPGT16 = 157, SP_FCMPGT32 = 158, SP_FCMPLE16 = 159, SP_FCMPLE32 = 160, SP_FCMPNE16 = 161, SP_FCMPNE32 = 162, SP_FCMPQ = 163, SP_FCMPS = 164, SP_FDIVD = 165, SP_FDIVQ = 166, SP_FDIVS = 167, SP_FDMULQ = 168, SP_FDTOI = 169, SP_FDTOQ = 170, SP_FDTOS = 171, SP_FDTOX = 172, SP_FEXPAND = 173, SP_FHADDD = 174, SP_FHADDS = 175, SP_FHSUBD = 176, SP_FHSUBS = 177, SP_FITOD = 178, SP_FITOQ = 179, SP_FITOS = 180, SP_FLCMPD = 181, SP_FLCMPS = 182, SP_FLUSHW = 183, SP_FMEAN16 = 184, SP_FMOVD = 185, SP_FMOVD_FCC = 186, SP_FMOVD_ICC = 187, SP_FMOVD_XCC = 188, SP_FMOVQ = 189, SP_FMOVQ_FCC = 190, SP_FMOVQ_ICC = 191, SP_FMOVQ_XCC = 192, SP_FMOVRGEZD = 193, SP_FMOVRGEZQ = 194, SP_FMOVRGEZS = 195, SP_FMOVRGZD = 196, SP_FMOVRGZQ = 197, SP_FMOVRGZS = 198, SP_FMOVRLEZD = 199, SP_FMOVRLEZQ = 200, SP_FMOVRLEZS = 201, SP_FMOVRLZD = 202, SP_FMOVRLZQ = 203, SP_FMOVRLZS = 204, SP_FMOVRNZD = 205, SP_FMOVRNZQ = 206, SP_FMOVRNZS = 207, SP_FMOVRZD = 208, SP_FMOVRZQ = 209, SP_FMOVRZS = 210, SP_FMOVS = 211, SP_FMOVS_FCC = 212, SP_FMOVS_ICC = 213, SP_FMOVS_XCC = 214, SP_FMUL8SUX16 = 215, SP_FMUL8ULX16 = 216, SP_FMUL8X16 = 217, SP_FMUL8X16AL = 218, SP_FMUL8X16AU = 219, SP_FMULD = 220, SP_FMULD8SUX16 = 221, SP_FMULD8ULX16 = 222, SP_FMULQ = 223, SP_FMULS = 224, SP_FNADDD = 225, SP_FNADDS = 226, SP_FNAND = 227, SP_FNANDS = 228, SP_FNEGD = 229, SP_FNEGQ = 230, SP_FNEGS = 231, SP_FNHADDD = 232, SP_FNHADDS = 233, SP_FNMULD = 234, SP_FNMULS = 235, SP_FNOR = 236, SP_FNORS = 237, SP_FNOT1 = 238, SP_FNOT1S = 239, SP_FNOT2 = 240, SP_FNOT2S = 241, SP_FNSMULD = 242, SP_FONE = 243, SP_FONES = 244, SP_FOR = 245, SP_FORNOT1 = 246, SP_FORNOT1S = 247, SP_FORNOT2 = 248, SP_FORNOT2S = 249, SP_FORS = 250, SP_FPACK16 = 251, SP_FPACK32 = 252, SP_FPACKFIX = 253, SP_FPADD16 = 254, SP_FPADD16S = 255, SP_FPADD32 = 256, SP_FPADD32S = 257, SP_FPADD64 = 258, SP_FPMERGE = 259, SP_FPSUB16 = 260, SP_FPSUB16S = 261, SP_FPSUB32 = 262, SP_FPSUB32S = 263, SP_FQTOD = 264, SP_FQTOI = 265, SP_FQTOS = 266, SP_FQTOX = 267, SP_FSLAS16 = 268, SP_FSLAS32 = 269, SP_FSLL16 = 270, SP_FSLL32 = 271, SP_FSMULD = 272, SP_FSQRTD = 273, SP_FSQRTQ = 274, SP_FSQRTS = 275, SP_FSRA16 = 276, SP_FSRA32 = 277, SP_FSRC1 = 278, SP_FSRC1S = 279, SP_FSRC2 = 280, SP_FSRC2S = 281, SP_FSRL16 = 282, SP_FSRL32 = 283, SP_FSTOD = 284, SP_FSTOI = 285, SP_FSTOQ = 286, SP_FSTOX = 287, SP_FSUBD = 288, SP_FSUBQ = 289, SP_FSUBS = 290, SP_FXNOR = 291, SP_FXNORS = 292, SP_FXOR = 293, SP_FXORS = 294, SP_FXTOD = 295, SP_FXTOQ = 296, SP_FXTOS = 297, SP_FZERO = 298, SP_FZEROS = 299, SP_GETPCX = 300, SP_JMPLri = 301, SP_JMPLrr = 302, SP_LDDFri = 303, SP_LDDFrr = 304, SP_LDFri = 305, SP_LDFrr = 306, SP_LDQFri = 307, SP_LDQFrr = 308, SP_LDSBri = 309, SP_LDSBrr = 310, SP_LDSHri = 311, SP_LDSHrr = 312, SP_LDSWri = 313, SP_LDSWrr = 314, SP_LDUBri = 315, SP_LDUBrr = 316, SP_LDUHri = 317, SP_LDUHrr = 318, SP_LDXri = 319, SP_LDXrr = 320, SP_LDri = 321, SP_LDrr = 322, SP_LEAX_ADDri = 323, SP_LEA_ADDri = 324, SP_LZCNT = 325, SP_MEMBARi = 326, SP_MOVDTOX = 327, SP_MOVFCCri = 328, SP_MOVFCCrr = 329, SP_MOVICCri = 330, SP_MOVICCrr = 331, SP_MOVRGEZri = 332, SP_MOVRGEZrr = 333, SP_MOVRGZri = 334, SP_MOVRGZrr = 335, SP_MOVRLEZri = 336, SP_MOVRLEZrr = 337, SP_MOVRLZri = 338, SP_MOVRLZrr = 339, SP_MOVRNZri = 340, SP_MOVRNZrr = 341, SP_MOVRRZri = 342, SP_MOVRRZrr = 343, SP_MOVSTOSW = 344, SP_MOVSTOUW = 345, SP_MOVWTOS = 346, SP_MOVXCCri = 347, SP_MOVXCCrr = 348, SP_MOVXTOD = 349, SP_MULXri = 350, SP_MULXrr = 351, SP_NOP = 352, SP_ORCCri = 353, SP_ORCCrr = 354, SP_ORNCCri = 355, SP_ORNCCrr = 356, SP_ORNri = 357, SP_ORNrr = 358, SP_ORXNrr = 359, SP_ORXri = 360, SP_ORXrr = 361, SP_ORri = 362, SP_ORrr = 363, SP_PDIST = 364, SP_PDISTN = 365, SP_POPCrr = 366, SP_RDY = 367, SP_RESTOREri = 368, SP_RESTORErr = 369, SP_RET = 370, SP_RETL = 371, SP_RETTri = 372, SP_RETTrr = 373, SP_SAVEri = 374, SP_SAVErr = 375, SP_SDIVCCri = 376, SP_SDIVCCrr = 377, SP_SDIVXri = 378, SP_SDIVXrr = 379, SP_SDIVri = 380, SP_SDIVrr = 381, SP_SELECT_CC_DFP_FCC = 382, SP_SELECT_CC_DFP_ICC = 383, SP_SELECT_CC_FP_FCC = 384, SP_SELECT_CC_FP_ICC = 385, SP_SELECT_CC_Int_FCC = 386, SP_SELECT_CC_Int_ICC = 387, SP_SELECT_CC_QFP_FCC = 388, SP_SELECT_CC_QFP_ICC = 389, SP_SETHIXi = 390, SP_SETHIi = 391, SP_SHUTDOWN = 392, SP_SIAM = 393, SP_SLLXri = 394, SP_SLLXrr = 395, SP_SLLri = 396, SP_SLLrr = 397, SP_SMULCCri = 398, SP_SMULCCrr = 399, SP_SMULri = 400, SP_SMULrr = 401, SP_SRAXri = 402, SP_SRAXrr = 403, SP_SRAri = 404, SP_SRArr = 405, SP_SRLXri = 406, SP_SRLXrr = 407, SP_SRLri = 408, SP_SRLrr = 409, SP_STBAR = 410, SP_STBri = 411, SP_STBrr = 412, SP_STDFri = 413, SP_STDFrr = 414, SP_STFri = 415, SP_STFrr = 416, SP_STHri = 417, SP_STHrr = 418, SP_STQFri = 419, SP_STQFrr = 420, SP_STXri = 421, SP_STXrr = 422, SP_STri = 423, SP_STrr = 424, SP_SUBCCri = 425, SP_SUBCCrr = 426, SP_SUBCri = 427, SP_SUBCrr = 428, SP_SUBEri = 429, SP_SUBErr = 430, SP_SUBXri = 431, SP_SUBXrr = 432, SP_SUBri = 433, SP_SUBrr = 434, SP_SWAPri = 435, SP_SWAPrr = 436, SP_TA3 = 437, SP_TA5 = 438, SP_TADDCCTVri = 439, SP_TADDCCTVrr = 440, SP_TADDCCri = 441, SP_TADDCCrr = 442, SP_TICCri = 443, SP_TICCrr = 444, SP_TLS_ADDXrr = 445, SP_TLS_ADDrr = 446, SP_TLS_CALL = 447, SP_TLS_LDXrr = 448, SP_TLS_LDrr = 449, SP_TSUBCCTVri = 450, SP_TSUBCCTVrr = 451, SP_TSUBCCri = 452, SP_TSUBCCrr = 453, SP_TXCCri = 454, SP_TXCCrr = 455, SP_UDIVCCri = 456, SP_UDIVCCrr = 457, SP_UDIVXri = 458, SP_UDIVXrr = 459, SP_UDIVri = 460, SP_UDIVrr = 461, SP_UMULCCri = 462, SP_UMULCCrr = 463, SP_UMULXHI = 464, SP_UMULri = 465, SP_UMULrr = 466, SP_UNIMP = 467, SP_V9FCMPD = 468, SP_V9FCMPED = 469, SP_V9FCMPEQ = 470, SP_V9FCMPES = 471, SP_V9FCMPQ = 472, SP_V9FCMPS = 473, SP_V9FMOVD_FCC = 474, SP_V9FMOVQ_FCC = 475, SP_V9FMOVS_FCC = 476, SP_V9MOVFCCri = 477, SP_V9MOVFCCrr = 478, SP_WRYri = 479, SP_WRYrr = 480, SP_XMULX = 481, SP_XMULXHI = 482, SP_XNORCCri = 483, SP_XNORCCrr = 484, SP_XNORXrr = 485, SP_XNORri = 486, SP_XNORrr = 487, SP_XORCCri = 488, SP_XORCCrr = 489, SP_XORXri = 490, SP_XORXrr = 491, SP_XORri = 492, SP_XORrr = 493, SP_INSTRUCTION_LIST_END = 494 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/Sparc/SparcGenRegisterInfo.inc000064400000000000000000000303660072674642500227160ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { SP_NoRegister, SP_ICC = 1, SP_Y = 2, SP_D0 = 3, SP_D1 = 4, SP_D2 = 5, SP_D3 = 6, SP_D4 = 7, SP_D5 = 8, SP_D6 = 9, SP_D7 = 10, SP_D8 = 11, SP_D9 = 12, SP_D10 = 13, SP_D11 = 14, SP_D12 = 15, SP_D13 = 16, SP_D14 = 17, SP_D15 = 18, SP_D16 = 19, SP_D17 = 20, SP_D18 = 21, SP_D19 = 22, SP_D20 = 23, SP_D21 = 24, SP_D22 = 25, SP_D23 = 26, SP_D24 = 27, SP_D25 = 28, SP_D26 = 29, SP_D27 = 30, SP_D28 = 31, SP_D29 = 32, SP_D30 = 33, SP_D31 = 34, SP_F0 = 35, SP_F1 = 36, SP_F2 = 37, SP_F3 = 38, SP_F4 = 39, SP_F5 = 40, SP_F6 = 41, SP_F7 = 42, SP_F8 = 43, SP_F9 = 44, SP_F10 = 45, SP_F11 = 46, SP_F12 = 47, SP_F13 = 48, SP_F14 = 49, SP_F15 = 50, SP_F16 = 51, SP_F17 = 52, SP_F18 = 53, SP_F19 = 54, SP_F20 = 55, SP_F21 = 56, SP_F22 = 57, SP_F23 = 58, SP_F24 = 59, SP_F25 = 60, SP_F26 = 61, SP_F27 = 62, SP_F28 = 63, SP_F29 = 64, SP_F30 = 65, SP_F31 = 66, SP_FCC0 = 67, SP_FCC1 = 68, SP_FCC2 = 69, SP_FCC3 = 70, SP_G0 = 71, SP_G1 = 72, SP_G2 = 73, SP_G3 = 74, SP_G4 = 75, SP_G5 = 76, SP_G6 = 77, SP_G7 = 78, SP_I0 = 79, SP_I1 = 80, SP_I2 = 81, SP_I3 = 82, SP_I4 = 83, SP_I5 = 84, SP_I6 = 85, SP_I7 = 86, SP_L0 = 87, SP_L1 = 88, SP_L2 = 89, SP_L3 = 90, SP_L4 = 91, SP_L5 = 92, SP_L6 = 93, SP_L7 = 94, SP_O0 = 95, SP_O1 = 96, SP_O2 = 97, SP_O3 = 98, SP_O4 = 99, SP_O5 = 100, SP_O6 = 101, SP_O7 = 102, SP_Q0 = 103, SP_Q1 = 104, SP_Q2 = 105, SP_Q3 = 106, SP_Q4 = 107, SP_Q5 = 108, SP_Q6 = 109, SP_Q7 = 110, SP_Q8 = 111, SP_Q9 = 112, SP_Q10 = 113, SP_Q11 = 114, SP_Q12 = 115, SP_Q13 = 116, SP_Q14 = 117, SP_Q15 = 118, SP_NUM_TARGET_REGS // 119 }; // Register classes enum { SP_FCCRegsRegClassID = 0, SP_FPRegsRegClassID = 1, SP_IntRegsRegClassID = 2, SP_DFPRegsRegClassID = 3, SP_I64RegsRegClassID = 4, SP_DFPRegs_with_sub_evenRegClassID = 5, SP_QFPRegsRegClassID = 6, SP_QFPRegs_with_sub_evenRegClassID = 7 }; #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg SparcRegDiffLists[] = { /* 0 */ 65126, 1, 1, 1, 0, /* 5 */ 32, 1, 0, /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, /* 15 */ 34, 1, 0, /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, /* 25 */ 36, 1, 0, /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, /* 35 */ 38, 1, 0, /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, /* 45 */ 40, 1, 0, /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, /* 55 */ 42, 1, 0, /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, /* 65 */ 44, 1, 0, /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, /* 75 */ 46, 1, 0, /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, /* 85 */ 65348, 1, 0, /* 88 */ 65444, 1, 0, /* 91 */ 65445, 1, 0, /* 94 */ 65446, 1, 0, /* 97 */ 65447, 1, 0, /* 100 */ 65448, 1, 0, /* 103 */ 65449, 1, 0, /* 106 */ 65450, 1, 0, /* 109 */ 65451, 1, 0, /* 112 */ 65532, 1, 0, /* 115 */ 15, 0, /* 117 */ 84, 0, /* 119 */ 85, 0, /* 121 */ 86, 0, /* 123 */ 87, 0, /* 125 */ 88, 0, /* 127 */ 89, 0, /* 129 */ 90, 0, /* 131 */ 91, 0, /* 133 */ 65488, 92, 0, /* 136 */ 65489, 92, 0, /* 139 */ 65489, 93, 0, /* 142 */ 65490, 93, 0, /* 145 */ 65491, 93, 0, /* 148 */ 65491, 94, 0, /* 151 */ 65492, 94, 0, /* 154 */ 65493, 94, 0, /* 157 */ 65493, 95, 0, /* 160 */ 65494, 95, 0, /* 163 */ 65495, 95, 0, /* 166 */ 65495, 96, 0, /* 169 */ 65496, 96, 0, /* 172 */ 65497, 96, 0, /* 175 */ 65497, 97, 0, /* 178 */ 65498, 97, 0, /* 181 */ 65499, 97, 0, /* 184 */ 65499, 98, 0, /* 187 */ 65500, 98, 0, /* 190 */ 65501, 98, 0, /* 193 */ 65501, 99, 0, /* 196 */ 65502, 99, 0, /* 199 */ 65503, 99, 0, /* 202 */ 65503, 100, 0, /* 205 */ 65504, 100, 0, /* 208 */ 65503, 0, /* 210 */ 65519, 0, /* 212 */ 65535, 0, }; static const uint16_t SparcSubRegIdxLists[] = { /* 0 */ 1, 3, 0, /* 3 */ 2, 4, 0, /* 6 */ 2, 1, 3, 4, 5, 6, 0, }; static const MCRegisterDesc SparcRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, { 406, 4, 4, 2, 3393, 0 }, { 410, 4, 4, 2, 3393, 0 }, { 33, 5, 203, 0, 1794, 2 }, { 87, 12, 194, 0, 1794, 2 }, { 133, 15, 194, 0, 1794, 2 }, { 179, 22, 185, 0, 1794, 2 }, { 220, 25, 185, 0, 1794, 2 }, { 261, 32, 176, 0, 1794, 2 }, { 298, 35, 176, 0, 1794, 2 }, { 335, 42, 167, 0, 1794, 2 }, { 372, 45, 167, 0, 1794, 2 }, { 397, 52, 158, 0, 1794, 2 }, { 0, 55, 158, 0, 1794, 2 }, { 54, 62, 149, 0, 1794, 2 }, { 108, 65, 149, 0, 1794, 2 }, { 154, 72, 140, 0, 1794, 2 }, { 200, 75, 140, 0, 1794, 2 }, { 241, 82, 134, 0, 1794, 2 }, { 282, 4, 134, 2, 1841, 0 }, { 319, 4, 131, 2, 1841, 0 }, { 356, 4, 131, 2, 1841, 0 }, { 381, 4, 129, 2, 1841, 0 }, { 12, 4, 129, 2, 1841, 0 }, { 66, 4, 127, 2, 1841, 0 }, { 120, 4, 127, 2, 1841, 0 }, { 166, 4, 125, 2, 1841, 0 }, { 212, 4, 125, 2, 1841, 0 }, { 253, 4, 123, 2, 1841, 0 }, { 290, 4, 123, 2, 1841, 0 }, { 327, 4, 121, 2, 1841, 0 }, { 364, 4, 121, 2, 1841, 0 }, { 389, 4, 119, 2, 1841, 0 }, { 20, 4, 119, 2, 1841, 0 }, { 74, 4, 117, 2, 1841, 0 }, { 36, 4, 205, 2, 3329, 0 }, { 90, 4, 202, 2, 3329, 0 }, { 136, 4, 199, 2, 3329, 0 }, { 182, 4, 196, 2, 3329, 0 }, { 223, 4, 196, 2, 3329, 0 }, { 264, 4, 193, 2, 3329, 0 }, { 301, 4, 190, 2, 3329, 0 }, { 338, 4, 187, 2, 3329, 0 }, { 375, 4, 187, 2, 3329, 0 }, { 400, 4, 184, 2, 3329, 0 }, { 4, 4, 181, 2, 3329, 0 }, { 58, 4, 178, 2, 3329, 0 }, { 112, 4, 178, 2, 3329, 0 }, { 158, 4, 175, 2, 3329, 0 }, { 204, 4, 172, 2, 3329, 0 }, { 245, 4, 169, 2, 3329, 0 }, { 286, 4, 169, 2, 3329, 0 }, { 323, 4, 166, 2, 3329, 0 }, { 360, 4, 163, 2, 3329, 0 }, { 385, 4, 160, 2, 3329, 0 }, { 16, 4, 160, 2, 3329, 0 }, { 70, 4, 157, 2, 3329, 0 }, { 124, 4, 154, 2, 3329, 0 }, { 170, 4, 151, 2, 3329, 0 }, { 216, 4, 151, 2, 3329, 0 }, { 257, 4, 148, 2, 3329, 0 }, { 294, 4, 145, 2, 3329, 0 }, { 331, 4, 142, 2, 3329, 0 }, { 368, 4, 142, 2, 3329, 0 }, { 393, 4, 139, 2, 3329, 0 }, { 24, 4, 136, 2, 3329, 0 }, { 78, 4, 133, 2, 3329, 0 }, { 28, 4, 4, 2, 3361, 0 }, { 82, 4, 4, 2, 3361, 0 }, { 128, 4, 4, 2, 3361, 0 }, { 174, 4, 4, 2, 3361, 0 }, { 39, 4, 4, 2, 3361, 0 }, { 93, 4, 4, 2, 3361, 0 }, { 139, 4, 4, 2, 3361, 0 }, { 185, 4, 4, 2, 3361, 0 }, { 226, 4, 4, 2, 3361, 0 }, { 267, 4, 4, 2, 3361, 0 }, { 304, 4, 4, 2, 3361, 0 }, { 341, 4, 4, 2, 3361, 0 }, { 42, 4, 4, 2, 3361, 0 }, { 96, 4, 4, 2, 3361, 0 }, { 142, 4, 4, 2, 3361, 0 }, { 188, 4, 4, 2, 3361, 0 }, { 229, 4, 4, 2, 3361, 0 }, { 270, 4, 4, 2, 3361, 0 }, { 307, 4, 4, 2, 3361, 0 }, { 344, 4, 4, 2, 3361, 0 }, { 45, 4, 4, 2, 3361, 0 }, { 99, 4, 4, 2, 3361, 0 }, { 145, 4, 4, 2, 3361, 0 }, { 191, 4, 4, 2, 3361, 0 }, { 232, 4, 4, 2, 3361, 0 }, { 273, 4, 4, 2, 3361, 0 }, { 310, 4, 4, 2, 3361, 0 }, { 347, 4, 4, 2, 3361, 0 }, { 48, 4, 4, 2, 3361, 0 }, { 102, 4, 4, 2, 3361, 0 }, { 148, 4, 4, 2, 3361, 0 }, { 194, 4, 4, 2, 3361, 0 }, { 235, 4, 4, 2, 3361, 0 }, { 276, 4, 4, 2, 3361, 0 }, { 313, 4, 4, 2, 3361, 0 }, { 350, 4, 4, 2, 3361, 0 }, { 51, 8, 4, 6, 4, 5 }, { 105, 18, 4, 6, 4, 5 }, { 151, 28, 4, 6, 4, 5 }, { 197, 38, 4, 6, 4, 5 }, { 238, 48, 4, 6, 4, 5 }, { 279, 58, 4, 6, 4, 5 }, { 316, 68, 4, 6, 4, 5 }, { 353, 78, 4, 6, 4, 5 }, { 378, 88, 4, 3, 1362, 10 }, { 403, 91, 4, 3, 1362, 10 }, { 8, 94, 4, 3, 1362, 10 }, { 62, 97, 4, 3, 1362, 10 }, { 116, 100, 4, 3, 1362, 10 }, { 162, 103, 4, 3, 1362, 10 }, { 208, 106, 4, 3, 1362, 10 }, { 249, 109, 4, 3, 1362, 10 }, }; // FCCRegs Register Class... static const MCPhysReg FCCRegs[] = { SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3, }; // FCCRegs Bit set. static const uint8_t FCCRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // FPRegs Register Class... static const MCPhysReg FPRegs[] = { SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, }; // FPRegs Bit set. static const uint8_t FPRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // IntRegs Register Class... static const MCPhysReg IntRegs[] = { SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, }; // IntRegs Bit set. static const uint8_t IntRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // DFPRegs Register Class... static const MCPhysReg DFPRegs[] = { SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, }; // DFPRegs Bit set. static const uint8_t DFPRegsBits[] = { 0xf8, 0xff, 0xff, 0xff, 0x07, }; // I64Regs Register Class... static const MCPhysReg I64Regs[] = { SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, }; // I64Regs Bit set. static const uint8_t I64RegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, }; // DFPRegs_with_sub_even Register Class... static const MCPhysReg DFPRegs_with_sub_even[] = { SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, }; // DFPRegs_with_sub_even Bit set. static const uint8_t DFPRegs_with_sub_evenBits[] = { 0xf8, 0xff, 0x07, }; // QFPRegs Register Class... static const MCPhysReg QFPRegs[] = { SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, }; // QFPRegs Bit set. static const uint8_t QFPRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, }; // QFPRegs_with_sub_even Register Class... static const MCPhysReg QFPRegs_with_sub_even[] = { SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, }; // QFPRegs_with_sub_even Bit set. static const uint8_t QFPRegs_with_sub_evenBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, }; static const MCRegisterClass SparcMCRegisterClasses[] = { { FCCRegs, FCCRegsBits, sizeof(FCCRegsBits) }, { FPRegs, FPRegsBits, sizeof(FPRegsBits) }, { IntRegs, IntRegsBits, sizeof(IntRegsBits) }, { DFPRegs, DFPRegsBits, sizeof(DFPRegsBits) }, { I64Regs, I64RegsBits, sizeof(I64RegsBits) }, { DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, sizeof(DFPRegs_with_sub_evenBits) }, { QFPRegs, QFPRegsBits, sizeof(QFPRegsBits) }, { QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, sizeof(QFPRegs_with_sub_evenBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/Sparc/SparcGenSubtargetInfo.inc000064400000000000000000000020200072674642500230540ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM enum { Sparc_FeatureHardQuad = 1ULL << 0, Sparc_FeatureV8Deprecated = 1ULL << 1, Sparc_FeatureV9 = 1ULL << 2, Sparc_FeatureVIS = 1ULL << 3, Sparc_FeatureVIS2 = 1ULL << 4, Sparc_FeatureVIS3 = 1ULL << 5, Sparc_UsePopc = 1ULL << 6 }; #endif // GET_SUBTARGETINFO_ENUM capstone-sys-0.15.0/capstone/arch/Sparc/SparcInstPrinter.c000064400000000000000000000311600072674642500216070ustar 00000000000000//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an Sparc MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SPARC #ifdef _MSC_VER #define _CRT_SECURE_NO_WARNINGS #endif #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:28719) // disable MSVC's warning on strncpy() #endif #include #include #include #include #include "SparcInstPrinter.h" #include "../../MCInst.h" #include "../../utils.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" #include "SparcMapping.h" #include "Sparc.h" static const char *getRegisterName(unsigned RegNo); static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier); static void printOperand(MCInst *MI, int opNum, SStream *O); static void Sparc_add_hint(MCInst *MI, unsigned int hint) { if (MI->csh->detail) { MI->flat_insn->detail->sparc.hint = hint; } } static void Sparc_add_reg(MCInst *MI, unsigned int reg) { if (MI->csh->detail) { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; MI->flat_insn->detail->sparc.op_count++; } } static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (status) { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0; } else { // done, create the next operand slot MI->flat_insn->detail->sparc.op_count++; } } void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { if (((cs_struct *)ud)->detail != CS_OPT_ON) return; // fix up some instructions if (insn->id == SPARC_INS_CASX) { // first op is actually a memop, not regop insn->detail->sparc.operands[0].type = SPARC_OP_MEM; insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg; insn->detail->sparc.operands[0].mem.disp = 0; } } static void printRegName(SStream *OS, unsigned RegNo) { SStream_concat0(OS, "%"); SStream_concat0(OS, getRegisterName(RegNo)); } #define GET_INSTRINFO_ENUM #include "SparcGenInstrInfo.inc" #define GET_REGINFO_ENUM #include "SparcGenRegisterInfo.inc" static bool printSparcAliasInstr(MCInst *MI, SStream *O) { switch (MCInst_getOpcode(MI)) { default: return false; case SP_JMPLrr: case SP_JMPLri: if (MCInst_getNumOperands(MI) != 3) return false; if (!MCOperand_isReg(MCInst_getOperand(MI, 0))) return false; switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) { default: return false; case SP_G0: // jmp $addr | ret | retl if (MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) { switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) { default: break; case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true; case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true; } } SStream_concat0(O, "jmp\t"); MCInst_setOpcodePub(MI, SPARC_INS_JMP); printMemOperand(MI, 1, O, NULL); return true; case SP_O7: // call $addr SStream_concat0(O, "call "); MCInst_setOpcodePub(MI, SPARC_INS_CALL); printMemOperand(MI, 1, O, NULL); return true; } case SP_V9FCMPS: case SP_V9FCMPD: case SP_V9FCMPQ: case SP_V9FCMPES: case SP_V9FCMPED: case SP_V9FCMPEQ: if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) || (!MCOperand_isReg(MCInst_getOperand(MI, 0))) || (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0)) return false; // if V8, skip printing %fcc0. switch(MCInst_getOpcode(MI)) { default: case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break; case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break; case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break; case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break; case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break; case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break; } printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return true; } } static void printOperand(MCInst *MI, int opNum, SStream *O) { int64_t Imm; unsigned reg; MCOperand *MO = MCInst_getOperand(MI, opNum); if (MCOperand_isReg(MO)) { reg = MCOperand_getReg(MO); printRegName(O, reg); reg = Sparc_map_register(reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base) MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg; else MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg; } else { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; MI->flat_insn->detail->sparc.op_count++; } } return; } if (MCOperand_isImm(MO)) { Imm = (int)MCOperand_getImm(MO); // Conditional branches displacements needs to be signextended to be // able to jump backwards. // // Displacements are measured as the number of instructions forward or // backward, so they need to be multiplied by 4 switch (MI->Opcode) { case SP_CALL: // Imm = SignExtend32(Imm, 30); Imm += MI->address; break; // Branch on integer condition with prediction (BPcc) // Branch on floating point condition with prediction (FBPfcc) case SP_BPICC: case SP_BPICCA: case SP_BPICCANT: case SP_BPICCNT: case SP_BPXCC: case SP_BPXCCA: case SP_BPXCCANT: case SP_BPXCCNT: case SP_BPFCC: case SP_BPFCCA: case SP_BPFCCANT: case SP_BPFCCNT: Imm = SignExtend32(Imm, 19); Imm = MI->address + Imm * 4; break; // Branch on integer condition (Bicc) // Branch on floating point condition (FBfcc) case SP_BA: case SP_BCOND: case SP_BCONDA: case SP_FBCOND: case SP_FBCONDA: Imm = SignExtend32(Imm, 22); Imm = MI->address + Imm * 4; break; // Branch on integer register with prediction (BPr) case SP_BPGEZapn: case SP_BPGEZapt: case SP_BPGEZnapn: case SP_BPGEZnapt: case SP_BPGZapn: case SP_BPGZapt: case SP_BPGZnapn: case SP_BPGZnapt: case SP_BPLEZapn: case SP_BPLEZapt: case SP_BPLEZnapn: case SP_BPLEZnapt: case SP_BPLZapn: case SP_BPLZapt: case SP_BPLZnapn: case SP_BPLZnapt: case SP_BPNZapn: case SP_BPNZapt: case SP_BPNZnapn: case SP_BPNZnapt: case SP_BPZapn: case SP_BPZapt: case SP_BPZnapn: case SP_BPZnapt: Imm = SignExtend32(Imm, 16); Imm = MI->address + Imm * 4; break; } printInt64(O, Imm); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm; } else { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm; MI->flat_insn->detail->sparc.op_count++; } } } return; } static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier) { MCOperand *MO; set_mem_access(MI, true); printOperand(MI, opNum, O); // If this is an ADD operand, emit it like normal operands. if (Modifier && !strcmp(Modifier, "arith")) { SStream_concat0(O, ", "); printOperand(MI, opNum + 1, O); set_mem_access(MI, false); return; } MO = MCInst_getOperand(MI, opNum + 1); if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) { set_mem_access(MI, false); return; // don't print "+%g0" } if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) { set_mem_access(MI, false); return; // don't print "+0" } SStream_concat0(O, "+"); // qq printOperand(MI, opNum + 1, O); set_mem_access(MI, false); } static void printCCOperand(MCInst *MI, int opNum, SStream *O) { int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256; switch (MCInst_getOpcode(MI)) { default: break; case SP_FBCOND: case SP_FBCONDA: case SP_BPFCC: case SP_BPFCCA: case SP_BPFCCNT: case SP_BPFCCANT: case SP_MOVFCCrr: case SP_V9MOVFCCrr: case SP_MOVFCCri: case SP_V9MOVFCCri: case SP_FMOVS_FCC: case SP_V9FMOVS_FCC: case SP_FMOVD_FCC: case SP_V9FMOVD_FCC: case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC: // Make sure CC is a fp conditional flag. CC = (CC < 16+256) ? (CC + 16) : CC; break; } SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC)); if (MI->csh->detail) MI->flat_insn->detail->sparc.cc = (sparc_cc)CC; } static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O) { return true; } #define PRINT_ALIAS_INSTR #include "SparcGenAsmWriter.inc" void Sparc_printInst(MCInst *MI, SStream *O, void *Info) { char *mnem, *p; char instr[64]; // Sparc has no instruction this long mnem = printAliasInstr(MI, O, Info); if (mnem) { // fixup instruction id due to the change in alias instruction strncpy(instr, mnem, sizeof(instr)); instr[sizeof(instr) - 1] = '\0'; // does this contains hint with a coma? p = strchr(instr, ','); if (p) *p = '\0'; // now instr only has instruction mnemonic MCInst_setOpcodePub(MI, Sparc_map_insn(instr)); switch(MCInst_getOpcode(MI)) { case SP_BCOND: case SP_BCONDA: case SP_BPICCANT: case SP_BPICCNT: case SP_BPXCCANT: case SP_BPXCCNT: case SP_TXCCri: case SP_TXCCrr: if (MI->csh->detail) { // skip 'b', 't' MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1); MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); } break; case SP_BPFCCANT: case SP_BPFCCNT: if (MI->csh->detail) { // skip 'fb' MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2); MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); } break; case SP_FMOVD_ICC: case SP_FMOVD_XCC: case SP_FMOVQ_ICC: case SP_FMOVQ_XCC: case SP_FMOVS_ICC: case SP_FMOVS_XCC: if (MI->csh->detail) { // skip 'fmovd', 'fmovq', 'fmovs' MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5); MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); } break; case SP_MOVICCri: case SP_MOVICCrr: case SP_MOVXCCri: case SP_MOVXCCrr: if (MI->csh->detail) { // skip 'mov' MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3); MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); } break; case SP_V9FMOVD_FCC: case SP_V9FMOVQ_FCC: case SP_V9FMOVS_FCC: if (MI->csh->detail) { // skip 'fmovd', 'fmovq', 'fmovs' MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5); MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); } break; case SP_V9MOVFCCri: case SP_V9MOVFCCrr: if (MI->csh->detail) { // skip 'mov' MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3); MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem); } break; default: break; } cs_mem_free(mnem); } else { if (!printSparcAliasInstr(MI, O)) printInstruction(MI, O, NULL); } } void Sparc_addReg(MCInst *MI, int reg) { if (MI->csh->detail) { MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; MI->flat_insn->detail->sparc.op_count++; } } #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcInstPrinter.h000064400000000000000000000006510072674642500216150ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SPARCINSTPRINTER_H #define CS_SPARCINSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void Sparc_printInst(MCInst *MI, SStream *O, void *Info); void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); void Sparc_addReg(MCInst *MI, int reg); #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcMapping.c000064400000000000000000000456770072674642500207430ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SPARC #include // debug #include #include "../../utils.h" #include "SparcMapping.h" #define GET_INSTRINFO_ENUM #include "SparcGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { { SPARC_REG_INVALID, NULL }, { SPARC_REG_F0, "f0"}, { SPARC_REG_F1, "f1"}, { SPARC_REG_F2, "f2"}, { SPARC_REG_F3, "f3"}, { SPARC_REG_F4, "f4"}, { SPARC_REG_F5, "f5"}, { SPARC_REG_F6, "f6"}, { SPARC_REG_F7, "f7"}, { SPARC_REG_F8, "f8"}, { SPARC_REG_F9, "f9"}, { SPARC_REG_F10, "f10"}, { SPARC_REG_F11, "f11"}, { SPARC_REG_F12, "f12"}, { SPARC_REG_F13, "f13"}, { SPARC_REG_F14, "f14"}, { SPARC_REG_F15, "f15"}, { SPARC_REG_F16, "f16"}, { SPARC_REG_F17, "f17"}, { SPARC_REG_F18, "f18"}, { SPARC_REG_F19, "f19"}, { SPARC_REG_F20, "f20"}, { SPARC_REG_F21, "f21"}, { SPARC_REG_F22, "f22"}, { SPARC_REG_F23, "f23"}, { SPARC_REG_F24, "f24"}, { SPARC_REG_F25, "f25"}, { SPARC_REG_F26, "f26"}, { SPARC_REG_F27, "f27"}, { SPARC_REG_F28, "f28"}, { SPARC_REG_F29, "f29"}, { SPARC_REG_F30, "f30"}, { SPARC_REG_F31, "f31"}, { SPARC_REG_F32, "f32"}, { SPARC_REG_F34, "f34"}, { SPARC_REG_F36, "f36"}, { SPARC_REG_F38, "f38"}, { SPARC_REG_F40, "f40"}, { SPARC_REG_F42, "f42"}, { SPARC_REG_F44, "f44"}, { SPARC_REG_F46, "f46"}, { SPARC_REG_F48, "f48"}, { SPARC_REG_F50, "f50"}, { SPARC_REG_F52, "f52"}, { SPARC_REG_F54, "f54"}, { SPARC_REG_F56, "f56"}, { SPARC_REG_F58, "f58"}, { SPARC_REG_F60, "f60"}, { SPARC_REG_F62, "f62"}, { SPARC_REG_FCC0, "fcc0"}, { SPARC_REG_FCC1, "fcc1"}, { SPARC_REG_FCC2, "fcc2"}, { SPARC_REG_FCC3, "fcc3"}, { SPARC_REG_FP, "fp"}, { SPARC_REG_G0, "g0"}, { SPARC_REG_G1, "g1"}, { SPARC_REG_G2, "g2"}, { SPARC_REG_G3, "g3"}, { SPARC_REG_G4, "g4"}, { SPARC_REG_G5, "g5"}, { SPARC_REG_G6, "g6"}, { SPARC_REG_G7, "g7"}, { SPARC_REG_I0, "i0"}, { SPARC_REG_I1, "i1"}, { SPARC_REG_I2, "i2"}, { SPARC_REG_I3, "i3"}, { SPARC_REG_I4, "i4"}, { SPARC_REG_I5, "i5"}, { SPARC_REG_I7, "i7"}, { SPARC_REG_ICC, "icc"}, { SPARC_REG_L0, "l0"}, { SPARC_REG_L1, "l1"}, { SPARC_REG_L2, "l2"}, { SPARC_REG_L3, "l3"}, { SPARC_REG_L4, "l4"}, { SPARC_REG_L5, "l5"}, { SPARC_REG_L6, "l6"}, { SPARC_REG_L7, "l7"}, { SPARC_REG_O0, "o0"}, { SPARC_REG_O1, "o1"}, { SPARC_REG_O2, "o2"}, { SPARC_REG_O3, "o3"}, { SPARC_REG_O4, "o4"}, { SPARC_REG_O5, "o5"}, { SPARC_REG_O7, "o7"}, { SPARC_REG_SP, "sp"}, { SPARC_REG_Y, "y"}, // special registers { SPARC_REG_XCC, "xcc"}, }; #endif const char *Sparc_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "SparcMappingInsn.inc" }; static struct hint_map { unsigned int id; uint8_t hints; } const insn_hints[] = { { SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN }, { SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT }, { SP_BPGEZnapn, SPARC_HINT_PN }, { SP_BPGZapn, SPARC_HINT_A | SPARC_HINT_PN }, { SP_BPGZapt, SPARC_HINT_A | SPARC_HINT_PT }, { SP_BPGZnapn, SPARC_HINT_PN }, { SP_BPLEZapn, SPARC_HINT_A | SPARC_HINT_PN }, { SP_BPLEZapt, SPARC_HINT_A | SPARC_HINT_PT }, { SP_BPLEZnapn, SPARC_HINT_PN }, { SP_BPLZapn, SPARC_HINT_A | SPARC_HINT_PN }, { SP_BPLZapt, SPARC_HINT_A | SPARC_HINT_PT }, { SP_BPLZnapn, SPARC_HINT_PN }, { SP_BPNZapn, SPARC_HINT_A | SPARC_HINT_PN }, { SP_BPNZapt, SPARC_HINT_A | SPARC_HINT_PT }, { SP_BPNZnapn, SPARC_HINT_PN }, { SP_BPZapn, SPARC_HINT_A | SPARC_HINT_PN }, { SP_BPZapt, SPARC_HINT_A | SPARC_HINT_PT }, { SP_BPZnapn, SPARC_HINT_PN }, }; // given internal insn id, return public instruction info void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned short i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP; insn->detail->groups_count++; } #endif // hint code for (i = 0; i < ARR_SIZE(insn_hints); i++) { if (id == insn_hints[i].id) { insn->detail->sparc.hint = insn_hints[i].hints; break; } } } } } static const name_map insn_name_maps[] = { { SPARC_INS_INVALID, NULL }, { SPARC_INS_ADDCC, "addcc" }, { SPARC_INS_ADDX, "addx" }, { SPARC_INS_ADDXCC, "addxcc" }, { SPARC_INS_ADDXC, "addxc" }, { SPARC_INS_ADDXCCC, "addxccc" }, { SPARC_INS_ADD, "add" }, { SPARC_INS_ALIGNADDR, "alignaddr" }, { SPARC_INS_ALIGNADDRL, "alignaddrl" }, { SPARC_INS_ANDCC, "andcc" }, { SPARC_INS_ANDNCC, "andncc" }, { SPARC_INS_ANDN, "andn" }, { SPARC_INS_AND, "and" }, { SPARC_INS_ARRAY16, "array16" }, { SPARC_INS_ARRAY32, "array32" }, { SPARC_INS_ARRAY8, "array8" }, { SPARC_INS_B, "b" }, { SPARC_INS_JMP, "jmp" }, { SPARC_INS_BMASK, "bmask" }, { SPARC_INS_FB, "fb" }, { SPARC_INS_BRGEZ, "brgez" }, { SPARC_INS_BRGZ, "brgz" }, { SPARC_INS_BRLEZ, "brlez" }, { SPARC_INS_BRLZ, "brlz" }, { SPARC_INS_BRNZ, "brnz" }, { SPARC_INS_BRZ, "brz" }, { SPARC_INS_BSHUFFLE, "bshuffle" }, { SPARC_INS_CALL, "call" }, { SPARC_INS_CASX, "casx" }, { SPARC_INS_CAS, "cas" }, { SPARC_INS_CMASK16, "cmask16" }, { SPARC_INS_CMASK32, "cmask32" }, { SPARC_INS_CMASK8, "cmask8" }, { SPARC_INS_CMP, "cmp" }, { SPARC_INS_EDGE16, "edge16" }, { SPARC_INS_EDGE16L, "edge16l" }, { SPARC_INS_EDGE16LN, "edge16ln" }, { SPARC_INS_EDGE16N, "edge16n" }, { SPARC_INS_EDGE32, "edge32" }, { SPARC_INS_EDGE32L, "edge32l" }, { SPARC_INS_EDGE32LN, "edge32ln" }, { SPARC_INS_EDGE32N, "edge32n" }, { SPARC_INS_EDGE8, "edge8" }, { SPARC_INS_EDGE8L, "edge8l" }, { SPARC_INS_EDGE8LN, "edge8ln" }, { SPARC_INS_EDGE8N, "edge8n" }, { SPARC_INS_FABSD, "fabsd" }, { SPARC_INS_FABSQ, "fabsq" }, { SPARC_INS_FABSS, "fabss" }, { SPARC_INS_FADDD, "faddd" }, { SPARC_INS_FADDQ, "faddq" }, { SPARC_INS_FADDS, "fadds" }, { SPARC_INS_FALIGNDATA, "faligndata" }, { SPARC_INS_FAND, "fand" }, { SPARC_INS_FANDNOT1, "fandnot1" }, { SPARC_INS_FANDNOT1S, "fandnot1s" }, { SPARC_INS_FANDNOT2, "fandnot2" }, { SPARC_INS_FANDNOT2S, "fandnot2s" }, { SPARC_INS_FANDS, "fands" }, { SPARC_INS_FCHKSM16, "fchksm16" }, { SPARC_INS_FCMPD, "fcmpd" }, { SPARC_INS_FCMPEQ16, "fcmpeq16" }, { SPARC_INS_FCMPEQ32, "fcmpeq32" }, { SPARC_INS_FCMPGT16, "fcmpgt16" }, { SPARC_INS_FCMPGT32, "fcmpgt32" }, { SPARC_INS_FCMPLE16, "fcmple16" }, { SPARC_INS_FCMPLE32, "fcmple32" }, { SPARC_INS_FCMPNE16, "fcmpne16" }, { SPARC_INS_FCMPNE32, "fcmpne32" }, { SPARC_INS_FCMPQ, "fcmpq" }, { SPARC_INS_FCMPS, "fcmps" }, { SPARC_INS_FDIVD, "fdivd" }, { SPARC_INS_FDIVQ, "fdivq" }, { SPARC_INS_FDIVS, "fdivs" }, { SPARC_INS_FDMULQ, "fdmulq" }, { SPARC_INS_FDTOI, "fdtoi" }, { SPARC_INS_FDTOQ, "fdtoq" }, { SPARC_INS_FDTOS, "fdtos" }, { SPARC_INS_FDTOX, "fdtox" }, { SPARC_INS_FEXPAND, "fexpand" }, { SPARC_INS_FHADDD, "fhaddd" }, { SPARC_INS_FHADDS, "fhadds" }, { SPARC_INS_FHSUBD, "fhsubd" }, { SPARC_INS_FHSUBS, "fhsubs" }, { SPARC_INS_FITOD, "fitod" }, { SPARC_INS_FITOQ, "fitoq" }, { SPARC_INS_FITOS, "fitos" }, { SPARC_INS_FLCMPD, "flcmpd" }, { SPARC_INS_FLCMPS, "flcmps" }, { SPARC_INS_FLUSHW, "flushw" }, { SPARC_INS_FMEAN16, "fmean16" }, { SPARC_INS_FMOVD, "fmovd" }, { SPARC_INS_FMOVQ, "fmovq" }, { SPARC_INS_FMOVRDGEZ, "fmovrdgez" }, { SPARC_INS_FMOVRQGEZ, "fmovrqgez" }, { SPARC_INS_FMOVRSGEZ, "fmovrsgez" }, { SPARC_INS_FMOVRDGZ, "fmovrdgz" }, { SPARC_INS_FMOVRQGZ, "fmovrqgz" }, { SPARC_INS_FMOVRSGZ, "fmovrsgz" }, { SPARC_INS_FMOVRDLEZ, "fmovrdlez" }, { SPARC_INS_FMOVRQLEZ, "fmovrqlez" }, { SPARC_INS_FMOVRSLEZ, "fmovrslez" }, { SPARC_INS_FMOVRDLZ, "fmovrdlz" }, { SPARC_INS_FMOVRQLZ, "fmovrqlz" }, { SPARC_INS_FMOVRSLZ, "fmovrslz" }, { SPARC_INS_FMOVRDNZ, "fmovrdnz" }, { SPARC_INS_FMOVRQNZ, "fmovrqnz" }, { SPARC_INS_FMOVRSNZ, "fmovrsnz" }, { SPARC_INS_FMOVRDZ, "fmovrdz" }, { SPARC_INS_FMOVRQZ, "fmovrqz" }, { SPARC_INS_FMOVRSZ, "fmovrsz" }, { SPARC_INS_FMOVS, "fmovs" }, { SPARC_INS_FMUL8SUX16, "fmul8sux16" }, { SPARC_INS_FMUL8ULX16, "fmul8ulx16" }, { SPARC_INS_FMUL8X16, "fmul8x16" }, { SPARC_INS_FMUL8X16AL, "fmul8x16al" }, { SPARC_INS_FMUL8X16AU, "fmul8x16au" }, { SPARC_INS_FMULD, "fmuld" }, { SPARC_INS_FMULD8SUX16, "fmuld8sux16" }, { SPARC_INS_FMULD8ULX16, "fmuld8ulx16" }, { SPARC_INS_FMULQ, "fmulq" }, { SPARC_INS_FMULS, "fmuls" }, { SPARC_INS_FNADDD, "fnaddd" }, { SPARC_INS_FNADDS, "fnadds" }, { SPARC_INS_FNAND, "fnand" }, { SPARC_INS_FNANDS, "fnands" }, { SPARC_INS_FNEGD, "fnegd" }, { SPARC_INS_FNEGQ, "fnegq" }, { SPARC_INS_FNEGS, "fnegs" }, { SPARC_INS_FNHADDD, "fnhaddd" }, { SPARC_INS_FNHADDS, "fnhadds" }, { SPARC_INS_FNOR, "fnor" }, { SPARC_INS_FNORS, "fnors" }, { SPARC_INS_FNOT1, "fnot1" }, { SPARC_INS_FNOT1S, "fnot1s" }, { SPARC_INS_FNOT2, "fnot2" }, { SPARC_INS_FNOT2S, "fnot2s" }, { SPARC_INS_FONE, "fone" }, { SPARC_INS_FONES, "fones" }, { SPARC_INS_FOR, "for" }, { SPARC_INS_FORNOT1, "fornot1" }, { SPARC_INS_FORNOT1S, "fornot1s" }, { SPARC_INS_FORNOT2, "fornot2" }, { SPARC_INS_FORNOT2S, "fornot2s" }, { SPARC_INS_FORS, "fors" }, { SPARC_INS_FPACK16, "fpack16" }, { SPARC_INS_FPACK32, "fpack32" }, { SPARC_INS_FPACKFIX, "fpackfix" }, { SPARC_INS_FPADD16, "fpadd16" }, { SPARC_INS_FPADD16S, "fpadd16s" }, { SPARC_INS_FPADD32, "fpadd32" }, { SPARC_INS_FPADD32S, "fpadd32s" }, { SPARC_INS_FPADD64, "fpadd64" }, { SPARC_INS_FPMERGE, "fpmerge" }, { SPARC_INS_FPSUB16, "fpsub16" }, { SPARC_INS_FPSUB16S, "fpsub16s" }, { SPARC_INS_FPSUB32, "fpsub32" }, { SPARC_INS_FPSUB32S, "fpsub32s" }, { SPARC_INS_FQTOD, "fqtod" }, { SPARC_INS_FQTOI, "fqtoi" }, { SPARC_INS_FQTOS, "fqtos" }, { SPARC_INS_FQTOX, "fqtox" }, { SPARC_INS_FSLAS16, "fslas16" }, { SPARC_INS_FSLAS32, "fslas32" }, { SPARC_INS_FSLL16, "fsll16" }, { SPARC_INS_FSLL32, "fsll32" }, { SPARC_INS_FSMULD, "fsmuld" }, { SPARC_INS_FSQRTD, "fsqrtd" }, { SPARC_INS_FSQRTQ, "fsqrtq" }, { SPARC_INS_FSQRTS, "fsqrts" }, { SPARC_INS_FSRA16, "fsra16" }, { SPARC_INS_FSRA32, "fsra32" }, { SPARC_INS_FSRC1, "fsrc1" }, { SPARC_INS_FSRC1S, "fsrc1s" }, { SPARC_INS_FSRC2, "fsrc2" }, { SPARC_INS_FSRC2S, "fsrc2s" }, { SPARC_INS_FSRL16, "fsrl16" }, { SPARC_INS_FSRL32, "fsrl32" }, { SPARC_INS_FSTOD, "fstod" }, { SPARC_INS_FSTOI, "fstoi" }, { SPARC_INS_FSTOQ, "fstoq" }, { SPARC_INS_FSTOX, "fstox" }, { SPARC_INS_FSUBD, "fsubd" }, { SPARC_INS_FSUBQ, "fsubq" }, { SPARC_INS_FSUBS, "fsubs" }, { SPARC_INS_FXNOR, "fxnor" }, { SPARC_INS_FXNORS, "fxnors" }, { SPARC_INS_FXOR, "fxor" }, { SPARC_INS_FXORS, "fxors" }, { SPARC_INS_FXTOD, "fxtod" }, { SPARC_INS_FXTOQ, "fxtoq" }, { SPARC_INS_FXTOS, "fxtos" }, { SPARC_INS_FZERO, "fzero" }, { SPARC_INS_FZEROS, "fzeros" }, { SPARC_INS_JMPL, "jmpl" }, { SPARC_INS_LDD, "ldd" }, { SPARC_INS_LD, "ld" }, { SPARC_INS_LDQ, "ldq" }, { SPARC_INS_LDSB, "ldsb" }, { SPARC_INS_LDSH, "ldsh" }, { SPARC_INS_LDSW, "ldsw" }, { SPARC_INS_LDUB, "ldub" }, { SPARC_INS_LDUH, "lduh" }, { SPARC_INS_LDX, "ldx" }, { SPARC_INS_LZCNT, "lzcnt" }, { SPARC_INS_MEMBAR, "membar" }, { SPARC_INS_MOVDTOX, "movdtox" }, { SPARC_INS_MOV, "mov" }, { SPARC_INS_MOVRGEZ, "movrgez" }, { SPARC_INS_MOVRGZ, "movrgz" }, { SPARC_INS_MOVRLEZ, "movrlez" }, { SPARC_INS_MOVRLZ, "movrlz" }, { SPARC_INS_MOVRNZ, "movrnz" }, { SPARC_INS_MOVRZ, "movrz" }, { SPARC_INS_MOVSTOSW, "movstosw" }, { SPARC_INS_MOVSTOUW, "movstouw" }, { SPARC_INS_MULX, "mulx" }, { SPARC_INS_NOP, "nop" }, { SPARC_INS_ORCC, "orcc" }, { SPARC_INS_ORNCC, "orncc" }, { SPARC_INS_ORN, "orn" }, { SPARC_INS_OR, "or" }, { SPARC_INS_PDIST, "pdist" }, { SPARC_INS_PDISTN, "pdistn" }, { SPARC_INS_POPC, "popc" }, { SPARC_INS_RD, "rd" }, { SPARC_INS_RESTORE, "restore" }, { SPARC_INS_RETT, "rett" }, { SPARC_INS_SAVE, "save" }, { SPARC_INS_SDIVCC, "sdivcc" }, { SPARC_INS_SDIVX, "sdivx" }, { SPARC_INS_SDIV, "sdiv" }, { SPARC_INS_SETHI, "sethi" }, { SPARC_INS_SHUTDOWN, "shutdown" }, { SPARC_INS_SIAM, "siam" }, { SPARC_INS_SLLX, "sllx" }, { SPARC_INS_SLL, "sll" }, { SPARC_INS_SMULCC, "smulcc" }, { SPARC_INS_SMUL, "smul" }, { SPARC_INS_SRAX, "srax" }, { SPARC_INS_SRA, "sra" }, { SPARC_INS_SRLX, "srlx" }, { SPARC_INS_SRL, "srl" }, { SPARC_INS_STBAR, "stbar" }, { SPARC_INS_STB, "stb" }, { SPARC_INS_STD, "std" }, { SPARC_INS_ST, "st" }, { SPARC_INS_STH, "sth" }, { SPARC_INS_STQ, "stq" }, { SPARC_INS_STX, "stx" }, { SPARC_INS_SUBCC, "subcc" }, { SPARC_INS_SUBX, "subx" }, { SPARC_INS_SUBXCC, "subxcc" }, { SPARC_INS_SUB, "sub" }, { SPARC_INS_SWAP, "swap" }, { SPARC_INS_TADDCCTV, "taddcctv" }, { SPARC_INS_TADDCC, "taddcc" }, { SPARC_INS_T, "t" }, { SPARC_INS_TSUBCCTV, "tsubcctv" }, { SPARC_INS_TSUBCC, "tsubcc" }, { SPARC_INS_UDIVCC, "udivcc" }, { SPARC_INS_UDIVX, "udivx" }, { SPARC_INS_UDIV, "udiv" }, { SPARC_INS_UMULCC, "umulcc" }, { SPARC_INS_UMULXHI, "umulxhi" }, { SPARC_INS_UMUL, "umul" }, { SPARC_INS_UNIMP, "unimp" }, { SPARC_INS_FCMPED, "fcmped" }, { SPARC_INS_FCMPEQ, "fcmpeq" }, { SPARC_INS_FCMPES, "fcmpes" }, { SPARC_INS_WR, "wr" }, { SPARC_INS_XMULX, "xmulx" }, { SPARC_INS_XMULXHI, "xmulxhi" }, { SPARC_INS_XNORCC, "xnorcc" }, { SPARC_INS_XNOR, "xnor" }, { SPARC_INS_XORCC, "xorcc" }, { SPARC_INS_XOR, "xor" }, // alias instructions { SPARC_INS_RET, "ret" }, { SPARC_INS_RETL, "retl" }, }; #ifndef CAPSTONE_DIET // special alias insn static const name_map alias_insn_names[] = { { 0, NULL } }; #endif const char *Sparc_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET unsigned int i; if (id >= SPARC_INS_ENDING) return NULL; // handle special alias first for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { if (alias_insn_names[i].id == id) return alias_insn_names[i].name; } return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { SPARC_GRP_INVALID, NULL }, { SPARC_GRP_JUMP, "jump" }, // architecture-specific groups { SPARC_GRP_HARDQUAD, "hardquad" }, { SPARC_GRP_V9, "v9" }, { SPARC_GRP_VIS, "vis" }, { SPARC_GRP_VIS2, "vis2" }, { SPARC_GRP_VIS3, "vis3" }, { SPARC_GRP_32BIT, "32bit" }, { SPARC_GRP_64BIT, "64bit" }, }; #endif const char *Sparc_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // map internal raw register to 'public' register sparc_reg Sparc_map_register(unsigned int r) { static const unsigned int map[] = { 0, SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4, SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14, SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24, SPARC_REG_F26, SPARC_REG_F28, SPARC_REG_F30, SPARC_REG_F32, SPARC_REG_F34, SPARC_REG_F36, SPARC_REG_F38, SPARC_REG_F40, SPARC_REG_F42, SPARC_REG_F44, SPARC_REG_F46, SPARC_REG_F48, SPARC_REG_F50, SPARC_REG_F52, SPARC_REG_F54, SPARC_REG_F56, SPARC_REG_F58, SPARC_REG_F60, SPARC_REG_F62, SPARC_REG_F0, SPARC_REG_F1, SPARC_REG_F2, SPARC_REG_F3, SPARC_REG_F4, SPARC_REG_F5, SPARC_REG_F6, SPARC_REG_F7, SPARC_REG_F8, SPARC_REG_F9, SPARC_REG_F10, SPARC_REG_F11, SPARC_REG_F12, SPARC_REG_F13, SPARC_REG_F14, SPARC_REG_F15, SPARC_REG_F16, SPARC_REG_F17, SPARC_REG_F18, SPARC_REG_F19, SPARC_REG_F20, SPARC_REG_F21, SPARC_REG_F22, SPARC_REG_F23, SPARC_REG_F24, SPARC_REG_F25, SPARC_REG_F26, SPARC_REG_F27, SPARC_REG_F28, SPARC_REG_F29, SPARC_REG_F30, SPARC_REG_F31, SPARC_REG_FCC0, SPARC_REG_FCC1, SPARC_REG_FCC2, SPARC_REG_FCC3, SPARC_REG_G0, SPARC_REG_G1, SPARC_REG_G2, SPARC_REG_G3, SPARC_REG_G4, SPARC_REG_G5, SPARC_REG_G6, SPARC_REG_G7, SPARC_REG_I0, SPARC_REG_I1, SPARC_REG_I2, SPARC_REG_I3, SPARC_REG_I4, SPARC_REG_I5, SPARC_REG_FP, SPARC_REG_I7, SPARC_REG_L0, SPARC_REG_L1, SPARC_REG_L2, SPARC_REG_L3, SPARC_REG_L4, SPARC_REG_L5, SPARC_REG_L6, SPARC_REG_L7, SPARC_REG_O0, SPARC_REG_O1, SPARC_REG_O2, SPARC_REG_O3, SPARC_REG_O4, SPARC_REG_O5, SPARC_REG_SP, SPARC_REG_O7, SPARC_REG_F0, SPARC_REG_F4, SPARC_REG_F8, SPARC_REG_F12, SPARC_REG_F16, SPARC_REG_F20, SPARC_REG_F24, SPARC_REG_F28, SPARC_REG_F32, SPARC_REG_F36, SPARC_REG_F40, SPARC_REG_F44, SPARC_REG_F48, SPARC_REG_F52, SPARC_REG_F56, SPARC_REG_F60, }; if (r < ARR_SIZE(map)) return map[r]; // cannot find this register return 0; } // map instruction name to instruction ID (public) sparc_reg Sparc_map_insn(const char *name) { unsigned int i; // NOTE: skip first NULL name in insn_name_maps i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); return (i != -1)? i : SPARC_REG_INVALID; } // NOTE: put strings in the order of string length since // we are going to compare with mnemonic to find out CC static const name_map alias_icc_maps[] = { { SPARC_CC_ICC_LEU, "leu" }, { SPARC_CC_ICC_POS, "pos" }, { SPARC_CC_ICC_NEG, "neg" }, { SPARC_CC_ICC_NE, "ne" }, { SPARC_CC_ICC_LE, "le" }, { SPARC_CC_ICC_GE, "ge" }, { SPARC_CC_ICC_GU, "gu" }, { SPARC_CC_ICC_CC, "cc" }, { SPARC_CC_ICC_CS, "cs" }, { SPARC_CC_ICC_VC, "vc" }, { SPARC_CC_ICC_VS, "vs" }, { SPARC_CC_ICC_A, "a" }, { SPARC_CC_ICC_N, "n" }, { SPARC_CC_ICC_E, "e" }, { SPARC_CC_ICC_G, "g" }, { SPARC_CC_ICC_L, "l" }, }; static const name_map alias_fcc_maps[] = { { SPARC_CC_FCC_UGE, "uge" }, { SPARC_CC_FCC_ULE, "ule" }, { SPARC_CC_FCC_UG, "ug" }, { SPARC_CC_FCC_UL, "ul" }, { SPARC_CC_FCC_LG, "lg" }, { SPARC_CC_FCC_NE, "ne" }, { SPARC_CC_FCC_UE, "ue" }, { SPARC_CC_FCC_GE, "ge" }, { SPARC_CC_FCC_LE, "le" }, { SPARC_CC_FCC_A, "a" }, { SPARC_CC_FCC_N, "n" }, { SPARC_CC_FCC_U, "u" }, { SPARC_CC_FCC_G, "g" }, { SPARC_CC_FCC_L, "l" }, { SPARC_CC_FCC_E, "e" }, { SPARC_CC_FCC_O, "o" }, }; // map CC string to CC id sparc_cc Sparc_map_ICC(const char *name) { unsigned int i; i = name2id(alias_icc_maps, ARR_SIZE(alias_icc_maps), name); return (i != -1)? i : SPARC_CC_INVALID; } sparc_cc Sparc_map_FCC(const char *name) { unsigned int i; i = name2id(alias_fcc_maps, ARR_SIZE(alias_fcc_maps), name); return (i != -1)? i : SPARC_CC_INVALID; } static const name_map hint_maps[] = { { SPARC_HINT_A, ",a" }, { SPARC_HINT_A | SPARC_HINT_PN, ",a,pn" }, { SPARC_HINT_PN, ",pn" }, }; sparc_hint Sparc_map_hint(const char *name) { size_t i, l1, l2; l1 = strlen(name); for(i = 0; i < ARR_SIZE(hint_maps); i++) { l2 = strlen(hint_maps[i].name); if (l1 > l2) { // compare the last part of @name with this hint string if (!strcmp(hint_maps[i].name, name + (l1 - l2))) return hint_maps[i].id; } } return SPARC_HINT_INVALID; } #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcMapping.h000064400000000000000000000016300072674642500207250ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SPARC_MAP_H #define CS_SPARC_MAP_H #include "capstone/capstone.h" // return name of regiser in friendly string const char *Sparc_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *Sparc_insn_name(csh handle, unsigned int id); const char *Sparc_group_name(csh handle, unsigned int id); // map internal raw register to 'public' register sparc_reg Sparc_map_register(unsigned int r); // map instruction name to instruction ID (public) // this is for alias instructions only sparc_reg Sparc_map_insn(const char *name); // map CC string to CC id sparc_cc Sparc_map_ICC(const char *name); sparc_cc Sparc_map_FCC(const char *name); sparc_hint Sparc_map_hint(const char *name); #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcMappingInsn.inc000064400000000000000000001320130072674642500220770ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { SP_ADDCCri, SPARC_INS_ADDCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ADDCCrr, SPARC_INS_ADDCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ADDCri, SPARC_INS_ADDX, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ADDCrr, SPARC_INS_ADDX, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ADDEri, SPARC_INS_ADDXCC, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ADDErr, SPARC_INS_ADDXCC, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ADDXC, SPARC_INS_ADDXC, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_ADDXCCC, SPARC_INS_ADDXCCC, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_ADDXri, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ADDXrr, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ADDri, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ADDrr, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ALIGNADDR, SPARC_INS_ALIGNADDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_ALIGNADDRL, SPARC_INS_ALIGNADDRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_ANDCCri, SPARC_INS_ANDCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ANDCCrr, SPARC_INS_ANDCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ANDNCCri, SPARC_INS_ANDNCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ANDNCCrr, SPARC_INS_ANDNCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ANDNri, SPARC_INS_ANDN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ANDNrr, SPARC_INS_ANDN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ANDXNrr, SPARC_INS_ANDN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ANDXri, SPARC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ANDXrr, SPARC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ANDri, SPARC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ANDrr, SPARC_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ARRAY16, SPARC_INS_ARRAY16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_ARRAY32, SPARC_INS_ARRAY32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_ARRAY8, SPARC_INS_ARRAY8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_BA, SPARC_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SP_BCOND, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SP_BCONDA, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SP_BINDri, SPARC_INS_JMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SP_BINDrr, SPARC_INS_JMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SP_BMASK, SPARC_INS_BMASK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_BPFCC, SPARC_INS_FB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPFCCA, SPARC_INS_FB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPFCCANT, SPARC_INS_FB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPFCCNT, SPARC_INS_FB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPGEZapn, SPARC_INS_BRGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGEZapt, SPARC_INS_BRGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGEZnapn, SPARC_INS_BRGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGEZnapt, SPARC_INS_BRGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGZapn, SPARC_INS_BRGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGZapt, SPARC_INS_BRGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGZnapn, SPARC_INS_BRGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPGZnapt, SPARC_INS_BRGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPICC, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPICCA, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPICCANT, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPICCNT, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0 #endif }, { SP_BPLEZapn, SPARC_INS_BRLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLEZapt, SPARC_INS_BRLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLEZnapn, SPARC_INS_BRLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLEZnapt, SPARC_INS_BRLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLZapn, SPARC_INS_BRLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLZapt, SPARC_INS_BRLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLZnapn, SPARC_INS_BRLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPLZnapt, SPARC_INS_BRLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPNZapn, SPARC_INS_BRNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPNZapt, SPARC_INS_BRNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPNZnapn, SPARC_INS_BRNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPNZnapt, SPARC_INS_BRNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPXCC, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPXCCA, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPXCCANT, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPXCCNT, SPARC_INS_B, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPZapn, SPARC_INS_BRZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPZapt, SPARC_INS_BRZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPZnapn, SPARC_INS_BRZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BPZnapt, SPARC_INS_BRZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0 #endif }, { SP_BSHUFFLE, SPARC_INS_BSHUFFLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_CALL, SPARC_INS_CALL, #ifndef CAPSTONE_DIET { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_CALLri, SPARC_INS_CALL, #ifndef CAPSTONE_DIET { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_CALLrr, SPARC_INS_CALL, #ifndef CAPSTONE_DIET { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_CASXrr, SPARC_INS_CASX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_CASrr, SPARC_INS_CAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_CMASK16, SPARC_INS_CMASK16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_CMASK32, SPARC_INS_CMASK32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_CMASK8, SPARC_INS_CMASK8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_CMPri, SPARC_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_CMPrr, SPARC_INS_CMP, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_EDGE16, SPARC_INS_EDGE16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_EDGE16L, SPARC_INS_EDGE16L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_EDGE16LN, SPARC_INS_EDGE16LN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_EDGE16N, SPARC_INS_EDGE16N, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_EDGE32, SPARC_INS_EDGE32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_EDGE32L, SPARC_INS_EDGE32L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_EDGE32LN, SPARC_INS_EDGE32LN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_EDGE32N, SPARC_INS_EDGE32N, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_EDGE8, SPARC_INS_EDGE8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_EDGE8L, SPARC_INS_EDGE8L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_EDGE8LN, SPARC_INS_EDGE8LN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_EDGE8N, SPARC_INS_EDGE8N, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_FABSD, SPARC_INS_FABSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FABSQ, SPARC_INS_FABSQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FABSS, SPARC_INS_FABSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FADDD, SPARC_INS_FADDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FADDQ, SPARC_INS_FADDQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FADDS, SPARC_INS_FADDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FALIGNADATA, SPARC_INS_FALIGNDATA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FAND, SPARC_INS_FAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FANDNOT1, SPARC_INS_FANDNOT1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FANDNOT1S, SPARC_INS_FANDNOT1S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FANDNOT2, SPARC_INS_FANDNOT2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FANDNOT2S, SPARC_INS_FANDNOT2S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FANDS, SPARC_INS_FANDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FBCOND, SPARC_INS_FB, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SP_FBCONDA, SPARC_INS_FB, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SP_FCHKSM16, SPARC_INS_FCHKSM16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FCMPD, SPARC_INS_FCMPD, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 #endif }, { SP_FCMPEQ16, SPARC_INS_FCMPEQ16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPEQ32, SPARC_INS_FCMPEQ32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPGT16, SPARC_INS_FCMPGT16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPGT32, SPARC_INS_FCMPGT32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPLE16, SPARC_INS_FCMPLE16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPLE32, SPARC_INS_FCMPLE32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPNE16, SPARC_INS_FCMPNE16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPNE32, SPARC_INS_FCMPNE32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FCMPQ, SPARC_INS_FCMPQ, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_FCC0, 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FCMPS, SPARC_INS_FCMPS, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0 #endif }, { SP_FDIVD, SPARC_INS_FDIVD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FDIVQ, SPARC_INS_FDIVQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FDIVS, SPARC_INS_FDIVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FDMULQ, SPARC_INS_FDMULQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FDTOI, SPARC_INS_FDTOI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FDTOQ, SPARC_INS_FDTOQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FDTOS, SPARC_INS_FDTOS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FDTOX, SPARC_INS_FDTOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FEXPAND, SPARC_INS_FEXPAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FHADDD, SPARC_INS_FHADDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FHADDS, SPARC_INS_FHADDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FHSUBD, SPARC_INS_FHSUBD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FHSUBS, SPARC_INS_FHSUBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FITOD, SPARC_INS_FITOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FITOQ, SPARC_INS_FITOQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FITOS, SPARC_INS_FITOS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FLCMPD, SPARC_INS_FLCMPD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FLCMPS, SPARC_INS_FLCMPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FLUSHW, SPARC_INS_FLUSHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMEAN16, SPARC_INS_FMEAN16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FMOVD, SPARC_INS_FMOVD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVD_FCC, SPARC_INS_FMOVD, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVD_ICC, SPARC_INS_FMOVD, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVD_XCC, SPARC_INS_FMOVD, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FMOVQ, SPARC_INS_FMOVQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVQ_FCC, SPARC_INS_FMOVQ, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVQ_ICC, SPARC_INS_FMOVQ, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVQ_XCC, SPARC_INS_FMOVQ, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FMOVRGEZD, SPARC_INS_FMOVRDGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRGEZQ, SPARC_INS_FMOVRQGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRGEZS, SPARC_INS_FMOVRSGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRGZD, SPARC_INS_FMOVRDGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRGZQ, SPARC_INS_FMOVRQGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRGZS, SPARC_INS_FMOVRSGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRLEZD, SPARC_INS_FMOVRDLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRLEZQ, SPARC_INS_FMOVRQLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRLEZS, SPARC_INS_FMOVRSLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRLZD, SPARC_INS_FMOVRDLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRLZQ, SPARC_INS_FMOVRQLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRLZS, SPARC_INS_FMOVRSLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRNZD, SPARC_INS_FMOVRDNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRNZQ, SPARC_INS_FMOVRQNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRNZS, SPARC_INS_FMOVRSNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRZD, SPARC_INS_FMOVRDZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRZQ, SPARC_INS_FMOVRQZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVRZS, SPARC_INS_FMOVRSZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVS, SPARC_INS_FMOVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FMOVS_FCC, SPARC_INS_FMOVS, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVS_ICC, SPARC_INS_FMOVS, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FMOVS_XCC, SPARC_INS_FMOVS, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FMUL8SUX16, SPARC_INS_FMUL8SUX16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMUL8ULX16, SPARC_INS_FMUL8ULX16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMUL8X16, SPARC_INS_FMUL8X16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMUL8X16AL, SPARC_INS_FMUL8X16AL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMUL8X16AU, SPARC_INS_FMUL8X16AU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMULD, SPARC_INS_FMULD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FMULD8SUX16, SPARC_INS_FMULD8SUX16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMULD8ULX16, SPARC_INS_FMULD8ULX16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FMULQ, SPARC_INS_FMULQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FMULS, SPARC_INS_FMULS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FNADDD, SPARC_INS_FNADDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FNADDS, SPARC_INS_FNADDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FNAND, SPARC_INS_FNAND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNANDS, SPARC_INS_FNANDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNEGD, SPARC_INS_FNEGD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FNEGQ, SPARC_INS_FNEGQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_FNEGS, SPARC_INS_FNEGS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FNHADDD, SPARC_INS_FNHADDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FNHADDS, SPARC_INS_FNHADDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FNMULD, SPARC_INS_FNHADDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FNMULS, SPARC_INS_FNHADDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FNOR, SPARC_INS_FNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNORS, SPARC_INS_FNORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNOT1, SPARC_INS_FNOT1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNOT1S, SPARC_INS_FNOT1S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNOT2, SPARC_INS_FNOT2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNOT2S, SPARC_INS_FNOT2S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FNSMULD, SPARC_INS_FNHADDS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FONE, SPARC_INS_FONE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FONES, SPARC_INS_FONES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FOR, SPARC_INS_FOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FORNOT1, SPARC_INS_FORNOT1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FORNOT1S, SPARC_INS_FORNOT1S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FORNOT2, SPARC_INS_FORNOT2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FORNOT2S, SPARC_INS_FORNOT2S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FORS, SPARC_INS_FORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPACK16, SPARC_INS_FPACK16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPACK32, SPARC_INS_FPACK32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPACKFIX, SPARC_INS_FPACKFIX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPADD16, SPARC_INS_FPADD16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPADD16S, SPARC_INS_FPADD16S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPADD32, SPARC_INS_FPADD32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPADD32S, SPARC_INS_FPADD32S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPADD64, SPARC_INS_FPADD64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FPMERGE, SPARC_INS_FPMERGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPSUB16, SPARC_INS_FPSUB16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPSUB16S, SPARC_INS_FPSUB16S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPSUB32, SPARC_INS_FPSUB32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FPSUB32S, SPARC_INS_FPSUB32S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FQTOD, SPARC_INS_FQTOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FQTOI, SPARC_INS_FQTOI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FQTOS, SPARC_INS_FQTOS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FQTOX, SPARC_INS_FQTOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FSLAS16, SPARC_INS_FSLAS16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSLAS32, SPARC_INS_FSLAS32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSLL16, SPARC_INS_FSLL16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSLL32, SPARC_INS_FSLL32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSMULD, SPARC_INS_FSMULD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FSQRTD, SPARC_INS_FSQRTD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FSQRTQ, SPARC_INS_FSQRTQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FSQRTS, SPARC_INS_FSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FSRA16, SPARC_INS_FSRA16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSRA32, SPARC_INS_FSRA32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSRC1, SPARC_INS_FSRC1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FSRC1S, SPARC_INS_FSRC1S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FSRC2, SPARC_INS_FSRC2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FSRC2S, SPARC_INS_FSRC2S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FSRL16, SPARC_INS_FSRL16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSRL32, SPARC_INS_FSRL32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_FSTOD, SPARC_INS_FSTOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FSTOI, SPARC_INS_FSTOI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FSTOQ, SPARC_INS_FSTOQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FSTOX, SPARC_INS_FSTOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FSUBD, SPARC_INS_FSUBD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FSUBQ, SPARC_INS_FSUBQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_FSUBS, SPARC_INS_FSUBS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_FXNOR, SPARC_INS_FXNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FXNORS, SPARC_INS_FXNORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FXOR, SPARC_INS_FXOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FXORS, SPARC_INS_FXORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FXTOD, SPARC_INS_FXTOD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FXTOQ, SPARC_INS_FXTOQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FXTOS, SPARC_INS_FXTOS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_FZERO, SPARC_INS_FZERO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_FZEROS, SPARC_INS_FZEROS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_JMPLri, SPARC_INS_JMPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_JMPLrr, SPARC_INS_JMPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDDFri, SPARC_INS_LDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDDFrr, SPARC_INS_LDD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDFri, SPARC_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDFrr, SPARC_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDQFri, SPARC_INS_LDQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_LDQFrr, SPARC_INS_LDQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_LDSBri, SPARC_INS_LDSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDSBrr, SPARC_INS_LDSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDSHri, SPARC_INS_LDSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDSHrr, SPARC_INS_LDSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDSWri, SPARC_INS_LDSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_LDSWrr, SPARC_INS_LDSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_LDUBri, SPARC_INS_LDUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDUBrr, SPARC_INS_LDUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDUHri, SPARC_INS_LDUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDUHrr, SPARC_INS_LDUH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDXri, SPARC_INS_LDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_LDXrr, SPARC_INS_LDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_LDri, SPARC_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LDrr, SPARC_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_LEAX_ADDri, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_LEA_ADDri, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_32BIT, 0 }, 0, 0 #endif }, { SP_LZCNT, SPARC_INS_LZCNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_MEMBARi, SPARC_INS_MEMBAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_MOVDTOX, SPARC_INS_MOVDTOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_MOVFCCri, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_MOVFCCrr, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_MOVICCri, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_MOVICCrr, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_MOVRGEZri, SPARC_INS_MOVRGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRGEZrr, SPARC_INS_MOVRGEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRGZri, SPARC_INS_MOVRGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRGZrr, SPARC_INS_MOVRGZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRLEZri, SPARC_INS_MOVRLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRLEZrr, SPARC_INS_MOVRLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRLZri, SPARC_INS_MOVRLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRLZrr, SPARC_INS_MOVRLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRNZri, SPARC_INS_MOVRNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRNZrr, SPARC_INS_MOVRNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRRZri, SPARC_INS_MOVRZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVRRZrr, SPARC_INS_MOVRZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVSTOSW, SPARC_INS_MOVSTOSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_MOVSTOUW, SPARC_INS_MOVSTOUW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_MOVWTOS, SPARC_INS_MOVDTOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_MOVXCCri, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVXCCrr, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MOVXTOD, SPARC_INS_MOVDTOX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_MULXri, SPARC_INS_MULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_MULXrr, SPARC_INS_MULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_NOP, SPARC_INS_NOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ORCCri, SPARC_INS_ORCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ORCCrr, SPARC_INS_ORCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ORNCCri, SPARC_INS_ORNCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ORNCCrr, SPARC_INS_ORNCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_ORNri, SPARC_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ORNrr, SPARC_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ORXNrr, SPARC_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ORXri, SPARC_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ORXrr, SPARC_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_ORri, SPARC_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_ORrr, SPARC_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_PDIST, SPARC_INS_PDIST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_PDISTN, SPARC_INS_PDISTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_POPCrr, SPARC_INS_POPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_RDY, SPARC_INS_RD, #ifndef CAPSTONE_DIET { SPARC_REG_Y, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_RESTOREri, SPARC_INS_RESTORE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_RESTORErr, SPARC_INS_RESTORE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_RET, SPARC_INS_JMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_RETL, SPARC_INS_JMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_RETTri, SPARC_INS_RETT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_RETTrr, SPARC_INS_RETT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SAVEri, SPARC_INS_SAVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SAVErr, SPARC_INS_SAVE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SDIVCCri, SPARC_INS_SDIVCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SDIVCCrr, SPARC_INS_SDIVCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SDIVXri, SPARC_INS_SDIVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SDIVXrr, SPARC_INS_SDIVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SDIVri, SPARC_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_SDIVrr, SPARC_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_SETHIXi, SPARC_INS_SETHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SETHIi, SPARC_INS_SETHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SHUTDOWN, SPARC_INS_SHUTDOWN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0 #endif }, { SP_SIAM, SPARC_INS_SIAM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0 #endif }, { SP_SLLXri, SPARC_INS_SLLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SLLXrr, SPARC_INS_SLLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SLLri, SPARC_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SLLrr, SPARC_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SMULCCri, SPARC_INS_SMULCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SMULCCrr, SPARC_INS_SMULCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SMULri, SPARC_INS_SMUL, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_SMULrr, SPARC_INS_SMUL, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_SRAXri, SPARC_INS_SRAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SRAXrr, SPARC_INS_SRAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SRAri, SPARC_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SRArr, SPARC_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SRLXri, SPARC_INS_SRLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SRLXrr, SPARC_INS_SRLX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SRLri, SPARC_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SRLrr, SPARC_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STBAR, SPARC_INS_STBAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STBri, SPARC_INS_STB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STBrr, SPARC_INS_STB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STDFri, SPARC_INS_STD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STDFrr, SPARC_INS_STD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STFri, SPARC_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STFrr, SPARC_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STHri, SPARC_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STHrr, SPARC_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STQFri, SPARC_INS_STQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_STQFrr, SPARC_INS_STQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_STXri, SPARC_INS_STX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_STXrr, SPARC_INS_STX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_STri, SPARC_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_STrr, SPARC_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SUBCCri, SPARC_INS_SUBCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SUBCCrr, SPARC_INS_SUBCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SUBCri, SPARC_INS_SUBX, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SUBCrr, SPARC_INS_SUBX, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SUBEri, SPARC_INS_SUBXCC, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SUBErr, SPARC_INS_SUBXCC, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_SUBXri, SPARC_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SUBXrr, SPARC_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_SUBri, SPARC_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SUBrr, SPARC_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SWAPri, SPARC_INS_SWAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_SWAPrr, SPARC_INS_SWAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TA3, SPARC_INS_T, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TA5, SPARC_INS_T, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TADDCCTVri, SPARC_INS_TADDCCTV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TADDCCTVrr, SPARC_INS_TADDCCTV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TADDCCri, SPARC_INS_TADDCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TADDCCrr, SPARC_INS_TADDCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TICCri, SPARC_INS_T, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TICCrr, SPARC_INS_T, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TLS_ADDXrr, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_TLS_ADDrr, SPARC_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TLS_CALL, SPARC_INS_CALL, #ifndef CAPSTONE_DIET { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TLS_LDXrr, SPARC_INS_LDX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_TLS_LDrr, SPARC_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_TSUBCCTVri, SPARC_INS_TSUBCCTV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TSUBCCTVrr, SPARC_INS_TSUBCCTV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TSUBCCri, SPARC_INS_TSUBCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TSUBCCrr, SPARC_INS_TSUBCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_TXCCri, SPARC_INS_T, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_TXCCrr, SPARC_INS_T, #ifndef CAPSTONE_DIET { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_UDIVCCri, SPARC_INS_UDIVCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_UDIVCCrr, SPARC_INS_UDIVCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_UDIVXri, SPARC_INS_UDIVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_UDIVXrr, SPARC_INS_UDIVX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_UDIVri, SPARC_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_UDIVrr, SPARC_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_UMULCCri, SPARC_INS_UMULCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_UMULCCrr, SPARC_INS_UMULCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_UMULXHI, SPARC_INS_UMULXHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_UMULri, SPARC_INS_UMUL, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_UMULrr, SPARC_INS_UMUL, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_UNIMP, SPARC_INS_UNIMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_V9FCMPD, SPARC_INS_FCMPD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_V9FCMPED, SPARC_INS_FCMPED, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_V9FCMPEQ, SPARC_INS_FCMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_V9FCMPES, SPARC_INS_FCMPES, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_V9FCMPQ, SPARC_INS_FCMPQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0 #endif }, { SP_V9FCMPS, SPARC_INS_FCMPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_V9FMOVD_FCC, SPARC_INS_FMOVD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_V9FMOVQ_FCC, SPARC_INS_FMOVQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_V9FMOVS_FCC, SPARC_INS_FMOVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_V9MOVFCCri, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_V9MOVFCCrr, SPARC_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0 #endif }, { SP_WRYri, SPARC_INS_WR, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_WRYrr, SPARC_INS_WR, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0 #endif }, { SP_XMULX, SPARC_INS_XMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_XMULXHI, SPARC_INS_XMULXHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0 #endif }, { SP_XNORCCri, SPARC_INS_XNORCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_XNORCCrr, SPARC_INS_XNORCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_XNORXrr, SPARC_INS_XNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_XNORri, SPARC_INS_XNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_XNORrr, SPARC_INS_XNOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_XORCCri, SPARC_INS_XORCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_XORCCrr, SPARC_INS_XORCC, #ifndef CAPSTONE_DIET { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 #endif }, { SP_XORXri, SPARC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_XORXrr, SPARC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0 #endif }, { SP_XORri, SPARC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SP_XORrr, SPARC_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/Sparc/SparcModule.c000064400000000000000000000016730072674642500205610ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SPARC #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "SparcDisassembler.h" #include "SparcInstPrinter.h" #include "SparcMapping.h" #include "SparcModule.h" cs_err Sparc_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); Sparc_init(mri); ud->printer = Sparc_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = Sparc_getInstruction; ud->post_printer = Sparc_post_printer; ud->reg_name = Sparc_reg_name; ud->insn_id = Sparc_get_insn_id; ud->insn_name = Sparc_insn_name; ud->group_name = Sparc_group_name; return CS_ERR_OK; } cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_SYNTAX) handle->syntax = (int) value; if (type == CS_OPT_MODE) { handle->mode = (cs_mode)value; } return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/Sparc/SparcModule.h000064400000000000000000000004410072674642500205560ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_SPARC_MODULE_H #define CS_SPARC_MODULE_H #include "../../utils.h" cs_err Sparc_global_init(cs_struct *ud); cs_err Sparc_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZDisassembler.c000064400000000000000000000317640072674642500226710ustar 00000000000000//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SYSZ #include // DEBUG #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "SystemZDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" #include "SystemZMCTargetDesc.h" static uint64_t getFeatureBits(int mode) { // support everything return (uint64_t)-1; } static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) { //assert(RegNo < 16 && "Invalid register"); RegNo = Regs[RegNo]; if (RegNo == 0) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, (unsigned)RegNo); return MCDisassembler_Success; } static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs); } static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs); } static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); } static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs); } static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs); } static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs); } static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs); } static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs); } static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs); } static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs); } static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs); } static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs); } static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs); } static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm) { //assert(isUInt(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, Imm); return MCDisassembler_Success; } static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N) { //assert(isUInt(Imm) && "Invalid immediate"); MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); return MCDisassembler_Success; } static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand(Inst, Imm); } static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeSImmOperand(Inst, Imm, 8); } static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeSImmOperand(Inst, Imm, 16); } static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeSImmOperand(Inst, Imm, 32); } static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, unsigned N) { //assert(isUInt(Imm) && "Invalid PC-relative offset"); MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address); return MCDisassembler_Success; } static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodePCDBLOperand(Inst, Imm, Address, 12); } static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodePCDBLOperand(Inst, Imm, Address, 16); } static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodePCDBLOperand(Inst, Imm, Address, 24); } static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodePCDBLOperand(Inst, Imm, Address, 32); } static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodePCDBLOperand(Inst, Imm, Address, 32); } static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Base = Field >> 12; uint64_t Disp = Field & 0xfff; //assert(Base < 16 && "Invalid BDAddr12"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, Disp); return MCDisassembler_Success; } static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Base = Field >> 20; uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); //assert(Base < 16 && "Invalid BDAddr20"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); return MCDisassembler_Success; } static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Index = Field >> 16; uint64_t Base = (Field >> 12) & 0xf; uint64_t Disp = Field & 0xfff; //assert(Index < 16 && "Invalid BDXAddr12"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, Disp); MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); return MCDisassembler_Success; } static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Index = Field >> 24; uint64_t Base = (Field >> 20) & 0xf; uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); //assert(Index < 16 && "Invalid BDXAddr20"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20)); MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]); return MCDisassembler_Success; } static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Length = Field >> 16; uint64_t Base = (Field >> 12) & 0xf; uint64_t Disp = Field & 0xfff; //assert(Length < 256 && "Invalid BDLAddr12Len8"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, Disp); MCOperand_CreateImm0(Inst, Length + 1); return MCDisassembler_Success; } static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Length = Field >> 16; uint64_t Base = (Field >> 12) & 0xf; uint64_t Disp = Field & 0xfff; //assert(Length < 16 && "Invalid BDRAddr12"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, Disp); MCOperand_CreateReg0(Inst, Regs[Length]); return MCDisassembler_Success; } static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field, const unsigned *Regs) { uint64_t Index = Field >> 16; uint64_t Base = (Field >> 12) & 0xf; uint64_t Disp = Field & 0xfff; //assert(Index < 32 && "Invalid BDVAddr12"); MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]); MCOperand_CreateImm0(Inst, Disp); MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]); return MCDisassembler_Success; } static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs); } static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs); } static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs); } static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field, uint64_t Address, const void *Decoder) { return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs); } #define GET_SUBTARGETINFO_ENUM #include "SystemZGenSubtargetInfo.inc" #include "SystemZGenDisassemblerTables.inc" bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *info) { uint64_t Inst; const uint8_t *Table; uint16_t I; // The top 2 bits of the first byte specify the size. if (*code < 0x40) { *size = 2; Table = DecoderTable16; } else if (*code < 0xc0) { *size = 4; Table = DecoderTable32; } else { *size = 6; Table = DecoderTable48; } if (code_len < *size) // short of input data return false; if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz)); } // Construct the instruction. Inst = 0; for (I = 0; I < *size; ++I) Inst = (Inst << 8) | code[I]; return decodeInstruction(Table, MI, Inst, address, info, 0); } #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "SystemZGenRegisterInfo.inc" void SystemZ_init(MCRegisterInfo *MRI) { /* InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC, SystemZMCRegisterClasses, 12, SystemZRegUnitRoots, 49, SystemZRegDiffLists, SystemZRegStrings, SystemZSubRegIdxLists, 7, SystemZSubRegIdxRanges, SystemZRegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194, 0, 0, SystemZMCRegisterClasses, 21, 0, 0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists, 7, 0); } #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZDisassembler.h000064400000000000000000000006600072674642500226650ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SYSZDISASSEMBLER_H #define CS_SYSZDISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void SystemZ_init(MCRegisterInfo *MRI); bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZGenAsmWriter.inc000064400000000000000000011107330072674642500231450ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include // debug #include /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'c', 'u', '2', '1', 9, 0, /* 6 */ 'c', 'u', '4', '1', 9, 0, /* 12 */ 'c', 'u', '1', '2', 9, 0, /* 18 */ 'c', 'u', '4', '2', 9, 0, /* 24 */ 'c', 'u', '1', '4', 9, 0, /* 30 */ 'c', 'u', '2', '4', 9, 0, /* 36 */ 't', 'r', 'a', 'p', '4', 9, 0, /* 43 */ 'l', 'a', 'a', 9, 0, /* 48 */ 's', 'l', 'd', 'a', 9, 0, /* 54 */ 's', 'r', 'd', 'a', 9, 0, /* 60 */ 'e', 's', 'e', 'a', 9, 0, /* 66 */ 'l', 'p', 't', 'e', 'a', 9, 0, /* 73 */ 'v', 'f', 'a', 9, 0, /* 78 */ 's', 'i', 'g', 'a', 9, 0, /* 84 */ 'e', 'c', 'p', 'g', 'a', 9, 0, /* 91 */ 'u', 'n', 'p', 'k', 'a', 9, 0, /* 98 */ 's', 'p', 'k', 'a', 9, 0, /* 104 */ 's', 'l', 'a', 9, 0, /* 109 */ 'v', 'g', 'f', 'm', 'a', 9, 0, /* 116 */ 'v', 'f', 'm', 'a', 9, 0, /* 122 */ 'k', 'm', 'a', 9, 0, /* 127 */ 'v', 'f', 'n', 'm', 'a', 9, 0, /* 134 */ 'p', 'p', 'a', 9, 0, /* 139 */ 'l', 'e', 'd', 'b', 'r', 'a', 9, 0, /* 147 */ 'c', 'f', 'd', 'b', 'r', 'a', 9, 0, /* 155 */ 'c', 'g', 'd', 'b', 'r', 'a', 9, 0, /* 163 */ 'f', 'i', 'd', 'b', 'r', 'a', 9, 0, /* 171 */ 'c', 'f', 'e', 'b', 'r', 'a', 9, 0, /* 179 */ 'c', 'g', 'e', 'b', 'r', 'a', 9, 0, /* 187 */ 'f', 'i', 'e', 'b', 'r', 'a', 9, 0, /* 195 */ 'c', 'd', 'f', 'b', 'r', 'a', 9, 0, /* 203 */ 'c', 'e', 'f', 'b', 'r', 'a', 9, 0, /* 211 */ 'c', 'x', 'f', 'b', 'r', 'a', 9, 0, /* 219 */ 'c', 'd', 'g', 'b', 'r', 'a', 9, 0, /* 227 */ 'c', 'e', 'g', 'b', 'r', 'a', 9, 0, /* 235 */ 'c', 'x', 'g', 'b', 'r', 'a', 9, 0, /* 243 */ 'l', 'd', 'x', 'b', 'r', 'a', 9, 0, /* 251 */ 'l', 'e', 'x', 'b', 'r', 'a', 9, 0, /* 259 */ 'c', 'f', 'x', 'b', 'r', 'a', 9, 0, /* 267 */ 'c', 'g', 'x', 'b', 'r', 'a', 9, 0, /* 275 */ 'f', 'i', 'x', 'b', 'r', 'a', 9, 0, /* 283 */ 'l', 'r', 'a', 9, 0, /* 288 */ 'v', 'e', 's', 'r', 'a', 9, 0, /* 295 */ 'v', 's', 'r', 'a', 9, 0, /* 301 */ 'a', 'd', 't', 'r', 'a', 9, 0, /* 308 */ 'd', 'd', 't', 'r', 'a', 9, 0, /* 315 */ 'c', 'g', 'd', 't', 'r', 'a', 9, 0, /* 323 */ 'm', 'd', 't', 'r', 'a', 9, 0, /* 330 */ 's', 'd', 't', 'r', 'a', 9, 0, /* 337 */ 'c', 'd', 'g', 't', 'r', 'a', 9, 0, /* 345 */ 'c', 'x', 'g', 't', 'r', 'a', 9, 0, /* 353 */ 'a', 'x', 't', 'r', 'a', 9, 0, /* 360 */ 'd', 'x', 't', 'r', 'a', 9, 0, /* 367 */ 'c', 'g', 'x', 't', 'r', 'a', 9, 0, /* 375 */ 'm', 'x', 't', 'r', 'a', 9, 0, /* 382 */ 's', 'x', 't', 'r', 'a', 9, 0, /* 389 */ 'l', 'u', 'r', 'a', 9, 0, /* 395 */ 's', 't', 'u', 'r', 'a', 9, 0, /* 402 */ 'b', 's', 'a', 9, 0, /* 407 */ 'e', 's', 't', 'a', 9, 0, /* 413 */ 'm', 's', 't', 'a', 9, 0, /* 419 */ 'v', 'a', 9, 0, /* 423 */ 'c', 'p', 'y', 'a', 9, 0, /* 429 */ 'v', 'g', 'f', 'm', 'a', 'b', 9, 0, /* 437 */ 'v', 'e', 's', 'r', 'a', 'b', 9, 0, /* 445 */ 'v', 's', 'r', 'a', 'b', 9, 0, /* 452 */ 'v', 'a', 'b', 9, 0, /* 457 */ 'l', 'c', 'b', 'b', 9, 0, /* 463 */ 'v', 'l', 'b', 'b', 9, 0, /* 469 */ 'v', 'a', 'c', 'c', 'b', 9, 0, /* 476 */ 'v', 'e', 'c', 'b', 9, 0, /* 482 */ 'v', 'l', 'c', 'b', 9, 0, /* 488 */ 'v', 's', 't', 'r', 'c', 'b', 9, 0, /* 496 */ 'v', 'f', 'a', 'd', 'b', 9, 0, /* 503 */ 'w', 'f', 'a', 'd', 'b', 9, 0, /* 510 */ 'v', 'f', 'm', 'a', 'd', 'b', 9, 0, /* 518 */ 'w', 'f', 'm', 'a', 'd', 'b', 9, 0, /* 526 */ 'v', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, /* 535 */ 'w', 'f', 'n', 'm', 'a', 'd', 'b', 9, 0, /* 544 */ 'w', 'f', 'c', 'd', 'b', 9, 0, /* 551 */ 'v', 'f', 'l', 'c', 'd', 'b', 9, 0, /* 559 */ 'w', 'f', 'l', 'c', 'd', 'b', 9, 0, /* 567 */ 't', 'c', 'd', 'b', 9, 0, /* 573 */ 'v', 'f', 'd', 'd', 'b', 9, 0, /* 580 */ 'w', 'f', 'd', 'd', 'b', 9, 0, /* 587 */ 'v', 'f', 'c', 'e', 'd', 'b', 9, 0, /* 595 */ 'w', 'f', 'c', 'e', 'd', 'b', 9, 0, /* 603 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, /* 612 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 9, 0, /* 621 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, /* 630 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 9, 0, /* 639 */ 'v', 'f', 'k', 'e', 'd', 'b', 9, 0, /* 647 */ 'w', 'f', 'k', 'e', 'd', 'b', 9, 0, /* 655 */ 'v', 'l', 'e', 'd', 'b', 9, 0, /* 662 */ 'w', 'l', 'e', 'd', 'b', 9, 0, /* 669 */ 'v', 'c', 'g', 'd', 'b', 9, 0, /* 676 */ 'w', 'c', 'g', 'd', 'b', 9, 0, /* 683 */ 'v', 'c', 'l', 'g', 'd', 'b', 9, 0, /* 691 */ 'w', 'c', 'l', 'g', 'd', 'b', 9, 0, /* 699 */ 'v', 'f', 'c', 'h', 'd', 'b', 9, 0, /* 707 */ 'w', 'f', 'c', 'h', 'd', 'b', 9, 0, /* 715 */ 'v', 'f', 'k', 'h', 'd', 'b', 9, 0, /* 723 */ 'w', 'f', 'k', 'h', 'd', 'b', 9, 0, /* 731 */ 'v', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, /* 740 */ 'w', 'f', 't', 'c', 'i', 'd', 'b', 9, 0, /* 749 */ 'v', 'f', 'i', 'd', 'b', 9, 0, /* 756 */ 'w', 'f', 'i', 'd', 'b', 9, 0, /* 763 */ 'w', 'f', 'k', 'd', 'b', 9, 0, /* 770 */ 'v', 's', 'l', 'd', 'b', 9, 0, /* 777 */ 'v', 'f', 'm', 'd', 'b', 9, 0, /* 784 */ 'w', 'f', 'm', 'd', 'b', 9, 0, /* 791 */ 'v', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, /* 800 */ 'w', 'f', 'm', 'i', 'n', 'd', 'b', 9, 0, /* 809 */ 'v', 'f', 'l', 'n', 'd', 'b', 9, 0, /* 817 */ 'w', 'f', 'l', 'n', 'd', 'b', 9, 0, /* 825 */ 'v', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, /* 834 */ 'w', 'f', 'p', 's', 'o', 'd', 'b', 9, 0, /* 843 */ 'v', 'f', 'l', 'p', 'd', 'b', 9, 0, /* 851 */ 'w', 'f', 'l', 'p', 'd', 'b', 9, 0, /* 859 */ 'v', 'f', 's', 'q', 'd', 'b', 9, 0, /* 867 */ 'w', 'f', 's', 'q', 'd', 'b', 9, 0, /* 875 */ 'v', 'f', 's', 'd', 'b', 9, 0, /* 882 */ 'w', 'f', 's', 'd', 'b', 9, 0, /* 889 */ 'v', 'f', 'm', 's', 'd', 'b', 9, 0, /* 897 */ 'w', 'f', 'm', 's', 'd', 'b', 9, 0, /* 905 */ 'v', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, /* 914 */ 'w', 'f', 'n', 'm', 's', 'd', 'b', 9, 0, /* 923 */ 'v', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, /* 932 */ 'w', 'f', 'm', 'a', 'x', 'd', 'b', 9, 0, /* 941 */ 'l', 'x', 'd', 'b', 9, 0, /* 947 */ 'm', 'x', 'd', 'b', 9, 0, /* 953 */ 'v', 'f', 'a', 'e', 'b', 9, 0, /* 960 */ 'v', 'm', 'a', 'e', 'b', 9, 0, /* 967 */ 't', 'c', 'e', 'b', 9, 0, /* 973 */ 'v', 'l', 'd', 'e', 'b', 9, 0, /* 980 */ 'w', 'l', 'd', 'e', 'b', 9, 0, /* 987 */ 'm', 'd', 'e', 'b', 9, 0, /* 993 */ 'v', 'f', 'e', 'e', 'b', 9, 0, /* 1000 */ 'm', 'e', 'e', 'b', 9, 0, /* 1006 */ 'k', 'e', 'b', 9, 0, /* 1011 */ 'v', 'm', 'a', 'l', 'e', 'b', 9, 0, /* 1019 */ 'v', 'm', 'l', 'e', 'b', 9, 0, /* 1026 */ 'v', 'l', 'e', 'b', 9, 0, /* 1032 */ 'v', 'm', 'e', 'b', 9, 0, /* 1038 */ 'v', 'f', 'e', 'n', 'e', 'b', 9, 0, /* 1046 */ 's', 'q', 'e', 'b', 9, 0, /* 1052 */ 'm', 's', 'e', 'b', 9, 0, /* 1058 */ 'v', 's', 't', 'e', 'b', 9, 0, /* 1065 */ 'l', 'x', 'e', 'b', 9, 0, /* 1071 */ 'v', 'c', 'd', 'g', 'b', 9, 0, /* 1078 */ 'w', 'c', 'd', 'g', 'b', 9, 0, /* 1085 */ 'v', 's', 'e', 'g', 'b', 9, 0, /* 1092 */ 'v', 'c', 'd', 'l', 'g', 'b', 9, 0, /* 1100 */ 'w', 'c', 'd', 'l', 'g', 'b', 9, 0, /* 1108 */ 'v', 'a', 'v', 'g', 'b', 9, 0, /* 1115 */ 'v', 'l', 'v', 'g', 'b', 9, 0, /* 1122 */ 'v', 'm', 'a', 'h', 'b', 9, 0, /* 1129 */ 'v', 'c', 'h', 'b', 9, 0, /* 1135 */ 'v', 'm', 'a', 'l', 'h', 'b', 9, 0, /* 1143 */ 'v', 'm', 'l', 'h', 'b', 9, 0, /* 1150 */ 'v', 'u', 'p', 'l', 'h', 'b', 9, 0, /* 1158 */ 'v', 'm', 'h', 'b', 9, 0, /* 1164 */ 'v', 'u', 'p', 'h', 'b', 9, 0, /* 1171 */ 'v', 'm', 'r', 'h', 'b', 9, 0, /* 1178 */ 'v', 's', 'c', 'b', 'i', 'b', 9, 0, /* 1186 */ 'c', 'i', 'b', 9, 0, /* 1191 */ 'v', 'l', 'e', 'i', 'b', 9, 0, /* 1198 */ 'c', 'g', 'i', 'b', 9, 0, /* 1204 */ 'c', 'l', 'g', 'i', 'b', 9, 0, /* 1211 */ 'c', 'l', 'i', 'b', 9, 0, /* 1217 */ 'v', 'r', 'e', 'p', 'i', 'b', 9, 0, /* 1225 */ 'v', 'm', 'a', 'l', 'b', 9, 0, /* 1232 */ 'v', 'e', 'c', 'l', 'b', 9, 0, /* 1239 */ 'v', 'a', 'v', 'g', 'l', 'b', 9, 0, /* 1247 */ 'v', 'c', 'h', 'l', 'b', 9, 0, /* 1254 */ 'v', 'u', 'p', 'l', 'l', 'b', 9, 0, /* 1262 */ 'v', 'e', 'r', 'l', 'l', 'b', 9, 0, /* 1270 */ 'v', 'm', 'l', 'b', 9, 0, /* 1276 */ 'v', 'm', 'n', 'l', 'b', 9, 0, /* 1283 */ 'v', 'u', 'p', 'l', 'b', 9, 0, /* 1290 */ 'v', 'm', 'r', 'l', 'b', 9, 0, /* 1297 */ 'v', 'e', 's', 'r', 'l', 'b', 9, 0, /* 1305 */ 'v', 's', 'r', 'l', 'b', 9, 0, /* 1312 */ 'v', 'e', 's', 'l', 'b', 9, 0, /* 1319 */ 'v', 's', 'l', 'b', 9, 0, /* 1325 */ 'v', 'm', 'x', 'l', 'b', 9, 0, /* 1332 */ 'v', 'g', 'f', 'm', 'b', 9, 0, /* 1339 */ 'v', 'g', 'm', 'b', 9, 0, /* 1345 */ 'v', 'e', 'r', 'i', 'm', 'b', 9, 0, /* 1353 */ 's', 'r', 'n', 'm', 'b', 9, 0, /* 1360 */ 'v', 's', 'u', 'm', 'b', 9, 0, /* 1367 */ 'v', 'm', 'n', 'b', 9, 0, /* 1373 */ 'v', 'm', 'a', 'o', 'b', 9, 0, /* 1380 */ 'v', 'm', 'a', 'l', 'o', 'b', 9, 0, /* 1388 */ 'v', 'm', 'l', 'o', 'b', 9, 0, /* 1395 */ 'v', 'm', 'o', 'b', 9, 0, /* 1401 */ 'v', 'l', 'r', 'e', 'p', 'b', 9, 0, /* 1409 */ 'v', 'r', 'e', 'p', 'b', 9, 0, /* 1416 */ 'v', 'l', 'p', 'b', 9, 0, /* 1422 */ 'v', 'c', 'e', 'q', 'b', 9, 0, /* 1429 */ 'c', 'r', 'b', 9, 0, /* 1434 */ 'c', 'g', 'r', 'b', 9, 0, /* 1440 */ 'c', 'l', 'g', 'r', 'b', 9, 0, /* 1447 */ 'c', 'l', 'r', 'b', 9, 0, /* 1453 */ 'v', 'i', 's', 't', 'r', 'b', 9, 0, /* 1461 */ 'v', 'f', 'a', 's', 'b', 9, 0, /* 1468 */ 'w', 'f', 'a', 's', 'b', 9, 0, /* 1475 */ 'v', 'f', 'm', 'a', 's', 'b', 9, 0, /* 1483 */ 'w', 'f', 'm', 'a', 's', 'b', 9, 0, /* 1491 */ 'v', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, /* 1500 */ 'w', 'f', 'n', 'm', 'a', 's', 'b', 9, 0, /* 1509 */ 'w', 'f', 'c', 's', 'b', 9, 0, /* 1516 */ 'v', 'f', 'l', 'c', 's', 'b', 9, 0, /* 1524 */ 'w', 'f', 'l', 'c', 's', 'b', 9, 0, /* 1532 */ 'v', 'f', 'd', 's', 'b', 9, 0, /* 1539 */ 'w', 'f', 'd', 's', 'b', 9, 0, /* 1546 */ 'v', 'f', 'c', 'e', 's', 'b', 9, 0, /* 1554 */ 'w', 'f', 'c', 'e', 's', 'b', 9, 0, /* 1562 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, /* 1571 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 9, 0, /* 1580 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, /* 1589 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 9, 0, /* 1598 */ 'v', 'f', 'k', 'e', 's', 'b', 9, 0, /* 1606 */ 'w', 'f', 'k', 'e', 's', 'b', 9, 0, /* 1614 */ 'v', 'f', 'c', 'h', 's', 'b', 9, 0, /* 1622 */ 'w', 'f', 'c', 'h', 's', 'b', 9, 0, /* 1630 */ 'v', 'f', 'k', 'h', 's', 'b', 9, 0, /* 1638 */ 'w', 'f', 'k', 'h', 's', 'b', 9, 0, /* 1646 */ 'v', 'f', 't', 'c', 'i', 's', 'b', 9, 0, /* 1655 */ 'w', 'f', 't', 'c', 'i', 's', 'b', 9, 0, /* 1664 */ 'v', 'f', 'i', 's', 'b', 9, 0, /* 1671 */ 'w', 'f', 'i', 's', 'b', 9, 0, /* 1678 */ 'w', 'f', 'k', 's', 'b', 9, 0, /* 1685 */ 'v', 'f', 'm', 's', 'b', 9, 0, /* 1692 */ 'w', 'f', 'm', 's', 'b', 9, 0, /* 1699 */ 'v', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, /* 1708 */ 'w', 'f', 'm', 'i', 'n', 's', 'b', 9, 0, /* 1717 */ 'v', 'f', 'l', 'n', 's', 'b', 9, 0, /* 1725 */ 'w', 'f', 'l', 'n', 's', 'b', 9, 0, /* 1733 */ 'v', 'f', 'p', 's', 'o', 's', 'b', 9, 0, /* 1742 */ 'w', 'f', 'p', 's', 'o', 's', 'b', 9, 0, /* 1751 */ 'v', 'f', 'l', 'p', 's', 'b', 9, 0, /* 1759 */ 'w', 'f', 'l', 'p', 's', 'b', 9, 0, /* 1767 */ 'v', 'f', 's', 'q', 's', 'b', 9, 0, /* 1775 */ 'w', 'f', 's', 'q', 's', 'b', 9, 0, /* 1783 */ 'v', 'f', 's', 's', 'b', 9, 0, /* 1790 */ 'w', 'f', 's', 's', 'b', 9, 0, /* 1797 */ 'v', 'f', 'm', 's', 's', 'b', 9, 0, /* 1805 */ 'w', 'f', 'm', 's', 's', 'b', 9, 0, /* 1813 */ 'v', 'f', 'n', 'm', 's', 's', 'b', 9, 0, /* 1822 */ 'w', 'f', 'n', 'm', 's', 's', 'b', 9, 0, /* 1831 */ 'v', 's', 'b', 9, 0, /* 1836 */ 'v', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, /* 1845 */ 'w', 'f', 'm', 'a', 'x', 's', 'b', 9, 0, /* 1854 */ 'v', 'p', 'o', 'p', 'c', 't', 'b', 9, 0, /* 1863 */ 'v', 'e', 's', 'r', 'a', 'v', 'b', 9, 0, /* 1872 */ 'v', 'c', 'v', 'b', 9, 0, /* 1878 */ 'v', 'l', 'g', 'v', 'b', 9, 0, /* 1885 */ 'v', 'e', 'r', 'l', 'l', 'v', 'b', 9, 0, /* 1894 */ 'v', 'e', 's', 'r', 'l', 'v', 'b', 9, 0, /* 1903 */ 'v', 'e', 's', 'l', 'v', 'b', 9, 0, /* 1911 */ 'w', 'f', 'a', 'x', 'b', 9, 0, /* 1918 */ 'w', 'f', 'm', 'a', 'x', 'b', 9, 0, /* 1926 */ 'w', 'f', 'n', 'm', 'a', 'x', 'b', 9, 0, /* 1935 */ 'w', 'f', 'c', 'x', 'b', 9, 0, /* 1942 */ 'w', 'f', 'l', 'c', 'x', 'b', 9, 0, /* 1950 */ 't', 'c', 'x', 'b', 9, 0, /* 1956 */ 'w', 'f', 'd', 'x', 'b', 9, 0, /* 1963 */ 'w', 'f', 'c', 'e', 'x', 'b', 9, 0, /* 1971 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 9, 0, /* 1980 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 9, 0, /* 1989 */ 'w', 'f', 'k', 'e', 'x', 'b', 9, 0, /* 1997 */ 'w', 'f', 'c', 'h', 'x', 'b', 9, 0, /* 2005 */ 'w', 'f', 'k', 'h', 'x', 'b', 9, 0, /* 2013 */ 'w', 'f', 't', 'c', 'i', 'x', 'b', 9, 0, /* 2022 */ 'w', 'f', 'i', 'x', 'b', 9, 0, /* 2029 */ 'w', 'f', 'k', 'x', 'b', 9, 0, /* 2036 */ 'w', 'f', 'm', 'x', 'b', 9, 0, /* 2043 */ 'v', 'm', 'x', 'b', 9, 0, /* 2049 */ 'w', 'f', 'm', 'i', 'n', 'x', 'b', 9, 0, /* 2058 */ 'w', 'f', 'l', 'n', 'x', 'b', 9, 0, /* 2066 */ 'w', 'f', 'p', 's', 'o', 'x', 'b', 9, 0, /* 2075 */ 'w', 'f', 'l', 'p', 'x', 'b', 9, 0, /* 2083 */ 'w', 'f', 's', 'q', 'x', 'b', 9, 0, /* 2091 */ 'w', 'f', 's', 'x', 'b', 9, 0, /* 2098 */ 'w', 'f', 'm', 's', 'x', 'b', 9, 0, /* 2106 */ 'w', 'f', 'n', 'm', 's', 'x', 'b', 9, 0, /* 2115 */ 'w', 'f', 'm', 'a', 'x', 'x', 'b', 9, 0, /* 2124 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 9, 0, /* 2133 */ 'v', 'f', 'a', 'e', 'z', 'b', 9, 0, /* 2141 */ 'v', 'f', 'e', 'e', 'z', 'b', 9, 0, /* 2149 */ 'v', 'l', 'l', 'e', 'z', 'b', 9, 0, /* 2157 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 9, 0, /* 2166 */ 'v', 'c', 'l', 'z', 'b', 9, 0, /* 2173 */ 'v', 'c', 't', 'z', 'b', 9, 0, /* 2180 */ 'i', 'a', 'c', 9, 0, /* 2185 */ 'k', 'm', 'a', 'c', 9, 0, /* 2191 */ 's', 'a', 'c', 9, 0, /* 2196 */ 'v', 'a', 'c', 9, 0, /* 2201 */ 'b', 'c', 9, 0, /* 2205 */ 'v', 'a', 'c', 'c', 9, 0, /* 2211 */ 'v', 'a', 'c', 'c', 'c', 9, 0, /* 2218 */ 'v', 'e', 'c', 9, 0, /* 2223 */ 'c', 'f', 'c', 9, 0, /* 2228 */ 'w', 'f', 'c', 9, 0, /* 2233 */ 'l', 'l', 'g', 'c', 9, 0, /* 2239 */ 'm', 's', 'g', 'c', 9, 0, /* 2245 */ 'b', 'i', 'c', 9, 0, /* 2250 */ 's', 'c', 'k', 'c', 9, 0, /* 2256 */ 's', 't', 'c', 'k', 'c', 9, 0, /* 2263 */ 'm', 's', 'g', 'r', 'k', 'c', 9, 0, /* 2271 */ 'm', 's', 'r', 'k', 'c', 9, 0, /* 2278 */ 'a', 'l', 'c', 9, 0, /* 2283 */ 'c', 'l', 'c', 9, 0, /* 2288 */ 'l', 'l', 'c', 9, 0, /* 2293 */ 'v', 'l', 'c', 9, 0, /* 2298 */ 'k', 'm', 'c', 9, 0, /* 2303 */ 't', 'b', 'e', 'g', 'i', 'n', 'c', 9, 0, /* 2312 */ 'v', 'n', 'c', 9, 0, /* 2317 */ 'l', 'o', 'c', 9, 0, /* 2322 */ 's', 't', 'o', 'c', 9, 0, /* 2328 */ 'v', 'o', 'c', 9, 0, /* 2333 */ 'e', 'f', 'p', 'c', 9, 0, /* 2339 */ 'l', 'f', 'p', 'c', 9, 0, /* 2345 */ 's', 'f', 'p', 'c', 9, 0, /* 2351 */ 's', 't', 'f', 'p', 'c', 9, 0, /* 2358 */ 'b', 'r', 'c', 9, 0, /* 2363 */ 'v', 's', 't', 'r', 'c', 9, 0, /* 2370 */ 'l', 'g', 's', 'c', 9, 0, /* 2376 */ 's', 't', 'g', 's', 'c', 9, 0, /* 2383 */ 'm', 's', 'c', 9, 0, /* 2388 */ 'c', 'm', 'p', 's', 'c', 9, 0, /* 2395 */ 's', 't', 'c', 9, 0, /* 2400 */ 'm', 'v', 'c', 9, 0, /* 2405 */ 's', 'v', 'c', 9, 0, /* 2410 */ 'x', 'c', 9, 0, /* 2414 */ 'm', 'a', 'd', 9, 0, /* 2419 */ 'c', 'd', 9, 0, /* 2423 */ 'd', 'd', 9, 0, /* 2427 */ 'v', 'l', 'e', 'd', 9, 0, /* 2433 */ 'p', 'f', 'd', 9, 0, /* 2438 */ 'v', 'f', 'd', 9, 0, /* 2443 */ 'v', 'c', 'g', 'd', 9, 0, /* 2449 */ 'v', 'c', 'l', 'g', 'd', 9, 0, /* 2456 */ 'w', 'f', 'l', 'l', 'd', 9, 0, /* 2463 */ 'k', 'i', 'm', 'd', 9, 0, /* 2469 */ 'k', 'l', 'm', 'd', 9, 0, /* 2475 */ 'e', 't', 'n', 'd', 9, 0, /* 2481 */ 'l', 'p', 'd', 9, 0, /* 2486 */ 's', 'q', 'd', 9, 0, /* 2491 */ 'v', 'f', 'l', 'r', 'd', 9, 0, /* 2498 */ 'w', 'f', 'l', 'r', 'd', 9, 0, /* 2505 */ 'm', 's', 'd', 9, 0, /* 2510 */ 's', 't', 'd', 9, 0, /* 2515 */ 'v', 'c', 'v', 'd', 9, 0, /* 2521 */ 'l', 'x', 'd', 9, 0, /* 2526 */ 'm', 'x', 'd', 9, 0, /* 2531 */ 'v', 'f', 'a', 'e', 9, 0, /* 2537 */ 'l', 'a', 'e', 9, 0, /* 2542 */ 'v', 'm', 'a', 'e', 9, 0, /* 2548 */ 'c', 'i', 'b', 'e', 9, 0, /* 2554 */ 'c', 'g', 'i', 'b', 'e', 9, 0, /* 2561 */ 'c', 'l', 'g', 'i', 'b', 'e', 9, 0, /* 2569 */ 'c', 'l', 'i', 'b', 'e', 9, 0, /* 2576 */ 'c', 'r', 'b', 'e', 9, 0, /* 2582 */ 'c', 'g', 'r', 'b', 'e', 9, 0, /* 2589 */ 'c', 'l', 'g', 'r', 'b', 'e', 9, 0, /* 2597 */ 'c', 'l', 'r', 'b', 'e', 9, 0, /* 2604 */ 'r', 'r', 'b', 'e', 9, 0, /* 2610 */ 't', 'r', 'a', 'c', 'e', 9, 0, /* 2617 */ 'v', 'f', 'c', 'e', 9, 0, /* 2623 */ 'l', 'o', 'c', 'e', 9, 0, /* 2629 */ 's', 't', 'o', 'c', 'e', 9, 0, /* 2636 */ 'v', 'l', 'd', 'e', 9, 0, /* 2642 */ 'm', 'd', 'e', 9, 0, /* 2647 */ 'v', 'f', 'e', 'e', 9, 0, /* 2653 */ 'm', 'e', 'e', 9, 0, /* 2658 */ 'l', 'o', 'c', 'g', 'e', 9, 0, /* 2665 */ 's', 't', 'o', 'c', 'g', 'e', 9, 0, /* 2673 */ 'j', 'g', 'e', 9, 0, /* 2678 */ 'c', 'i', 'b', 'h', 'e', 9, 0, /* 2685 */ 'c', 'g', 'i', 'b', 'h', 'e', 9, 0, /* 2693 */ 'c', 'l', 'g', 'i', 'b', 'h', 'e', 9, 0, /* 2702 */ 'c', 'l', 'i', 'b', 'h', 'e', 9, 0, /* 2710 */ 'c', 'r', 'b', 'h', 'e', 9, 0, /* 2717 */ 'c', 'g', 'r', 'b', 'h', 'e', 9, 0, /* 2725 */ 'c', 'l', 'g', 'r', 'b', 'h', 'e', 9, 0, /* 2734 */ 'c', 'l', 'r', 'b', 'h', 'e', 9, 0, /* 2742 */ 'v', 'f', 'c', 'h', 'e', 9, 0, /* 2749 */ 'l', 'o', 'c', 'h', 'e', 9, 0, /* 2756 */ 's', 't', 'o', 'c', 'h', 'e', 9, 0, /* 2764 */ 'l', 'o', 'c', 'f', 'h', 'e', 9, 0, /* 2772 */ 's', 't', 'o', 'c', 'f', 'h', 'e', 9, 0, /* 2781 */ 'l', 'o', 'c', 'g', 'h', 'e', 9, 0, /* 2789 */ 's', 't', 'o', 'c', 'g', 'h', 'e', 9, 0, /* 2798 */ 'j', 'g', 'h', 'e', 9, 0, /* 2804 */ 'l', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, /* 2813 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 'e', 9, 0, /* 2823 */ 'b', 'i', 'h', 'e', 9, 0, /* 2829 */ 'l', 'o', 'c', 'h', 'i', 'h', 'e', 9, 0, /* 2838 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 'e', 9, 0, /* 2848 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 'e', 9, 0, /* 2858 */ 'c', 'i', 'j', 'h', 'e', 9, 0, /* 2865 */ 'c', 'g', 'i', 'j', 'h', 'e', 9, 0, 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'e', 9, 0, /* 3047 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'h', 'e', 9, 0, /* 3058 */ 'b', 'i', 'n', 'h', 'e', 9, 0, /* 3065 */ 'l', 'o', 'c', 'h', 'i', 'n', 'h', 'e', 9, 0, /* 3075 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'h', 'e', 9, 0, /* 3086 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'h', 'e', 9, 0, /* 3097 */ 'c', 'i', 'j', 'n', 'h', 'e', 9, 0, /* 3105 */ 'c', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, /* 3114 */ 'c', 'l', 'g', 'i', 'j', 'n', 'h', 'e', 9, 0, /* 3124 */ 'c', 'l', 'i', 'j', 'n', 'h', 'e', 9, 0, /* 3133 */ 'c', 'r', 'j', 'n', 'h', 'e', 9, 0, /* 3141 */ 'c', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, /* 3150 */ 'c', 'l', 'g', 'r', 'j', 'n', 'h', 'e', 9, 0, /* 3160 */ 'c', 'l', 'r', 'j', 'n', 'h', 'e', 9, 0, /* 3169 */ 'l', 'o', 'c', 'r', 'n', 'h', 'e', 9, 0, /* 3178 */ 'l', 'o', 'c', 'g', 'r', 'n', 'h', 'e', 9, 0, /* 3188 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 'e', 9, 0, /* 3199 */ 'c', 'l', 'g', 't', 'n', 'h', 'e', 9, 0, /* 3208 */ 'c', 'i', 't', 'n', 'h', 'e', 9, 0, /* 3216 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 'e', 9, 0, /* 3226 */ 'c', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, /* 3235 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 'e', 9, 0, /* 3245 */ 'c', 'l', 't', 'n', 'h', 'e', 9, 0, /* 3253 */ 'c', 'r', 't', 'n', 'h', 'e', 9, 0, /* 3261 */ 'c', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, /* 3270 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 'e', 9, 0, /* 3280 */ 'c', 'l', 'r', 't', 'n', 'h', 'e', 9, 0, /* 3289 */ 'l', 'o', 'c', 'r', 'h', 'e', 9, 0, /* 3297 */ 'l', 'o', 'c', 'g', 'r', 'h', 'e', 9, 0, /* 3306 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 'e', 9, 0, /* 3316 */ 'c', 'l', 'g', 't', 'h', 'e', 9, 0, /* 3324 */ 'c', 'i', 't', 'h', 'e', 9, 0, /* 3331 */ 'c', 'l', 'f', 'i', 't', 'h', 'e', 9, 0, /* 3340 */ 'c', 'g', 'i', 't', 'h', 'e', 9, 0, /* 3348 */ 'c', 'l', 'g', 'i', 't', 'h', 'e', 9, 0, /* 3357 */ 'c', 'l', 't', 'h', 'e', 9, 0, /* 3364 */ 'c', 'r', 't', 'h', 'e', 9, 0, /* 3371 */ 'c', 'g', 'r', 't', 'h', 'e', 9, 0, /* 3379 */ 'c', 'l', 'g', 'r', 't', 'h', 'e', 9, 0, /* 3388 */ 'c', 'l', 'r', 't', 'h', 'e', 9, 0, /* 3396 */ 'b', 'i', 'e', 9, 0, /* 3401 */ 'l', 'o', 'c', 'h', 'i', 'e', 9, 0, /* 3409 */ 'l', 'o', 'c', 'g', 'h', 'i', 'e', 9, 0, /* 3418 */ 'l', 'o', 'c', 'h', 'h', 'i', 'e', 9, 0, /* 3427 */ 's', 'i', 'e', 9, 0, /* 3432 */ 'c', 'i', 'j', 'e', 9, 0, /* 3438 */ 'c', 'g', 'i', 'j', 'e', 9, 0, /* 3445 */ 'c', 'l', 'g', 'i', 'j', 'e', 9, 0, /* 3453 */ 'c', 'l', 'i', 'j', 'e', 9, 0, /* 3460 */ 'c', 'r', 'j', 'e', 9, 0, /* 3466 */ 'c', 'g', 'r', 'j', 'e', 9, 0, /* 3473 */ 'c', 'l', 'g', 'r', 'j', 'e', 9, 0, /* 3481 */ 'c', 'l', 'r', 'j', 'e', 9, 0, /* 3488 */ 's', 't', 'c', 'k', 'e', 9, 0, /* 3495 */ 'i', 's', 'k', 'e', 9, 0, /* 3501 */ 's', 's', 'k', 'e', 9, 0, /* 3507 */ 'v', 'm', 'a', 'l', 'e', 9, 0, /* 3514 */ 'c', 'i', 'b', 'l', 'e', 9, 0, /* 3521 */ 'c', 'g', 'i', 'b', 'l', 'e', 9, 0, /* 3529 */ 'c', 'l', 'g', 'i', 'b', 'l', 'e', 9, 0, /* 3538 */ 'c', 'l', 'i', 'b', 'l', 'e', 9, 0, /* 3546 */ 'c', 'r', 'b', 'l', 'e', 9, 0, /* 3553 */ 'c', 'g', 'r', 'b', 'l', 'e', 9, 0, /* 3561 */ 'c', 'l', 'g', 'r', 'b', 'l', 'e', 9, 0, /* 3570 */ 'c', 'l', 'r', 'b', 'l', 'e', 9, 0, /* 3578 */ 'c', 'l', 'c', 'l', 'e', 9, 0, /* 3585 */ 'l', 'o', 'c', 'l', 'e', 9, 0, /* 3592 */ 's', 't', 'o', 'c', 'l', 'e', 9, 0, /* 3600 */ 'm', 'v', 'c', 'l', 'e', 9, 0, /* 3607 */ 's', 't', 'f', 'l', 'e', 9, 0, /* 3614 */ 'l', 'o', 'c', 'g', 'l', 'e', 9, 0, /* 3622 */ 's', 't', 'o', 'c', 'g', 'l', 'e', 9, 0, /* 3631 */ 'j', 'g', 'l', 'e', 9, 0, /* 3637 */ 'l', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, /* 3646 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 'e', 9, 0, /* 3656 */ 'b', 'i', 'l', 'e', 9, 0, /* 3662 */ 'l', 'o', 'c', 'h', 'i', 'l', 'e', 9, 0, /* 3671 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 'e', 9, 0, /* 3681 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 'e', 9, 0, /* 3691 */ 'c', 'i', 'j', 'l', 'e', 9, 0, /* 3698 */ 'c', 'g', 'i', 'j', 'l', 'e', 9, 0, /* 3706 */ 'c', 'l', 'g', 'i', 'j', 'l', 'e', 9, 0, /* 3715 */ 'c', 'l', 'i', 'j', 'l', 'e', 9, 0, /* 3723 */ 'c', 'r', 'j', 'l', 'e', 9, 0, /* 3730 */ 'c', 'g', 'r', 'j', 'l', 'e', 9, 0, /* 3738 */ 'c', 'l', 'g', 'r', 'j', 'l', 'e', 9, 0, /* 3747 */ 'c', 'l', 'r', 'j', 'l', 'e', 9, 0, /* 3755 */ 'v', 'm', 'l', 'e', 9, 0, /* 3761 */ 'c', 'i', 'b', 'n', 'l', 'e', 9, 0, /* 3769 */ 'c', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, /* 3778 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 'e', 9, 0, /* 3788 */ 'c', 'l', 'i', 'b', 'n', 'l', 'e', 9, 0, /* 3797 */ 'c', 'r', 'b', 'n', 'l', 'e', 9, 0, /* 3805 */ 'c', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, /* 3814 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 'e', 9, 0, /* 3824 */ 'c', 'l', 'r', 'b', 'n', 'l', 'e', 9, 0, /* 3833 */ 'l', 'o', 'c', 'n', 'l', 'e', 9, 0, /* 3841 */ 's', 't', 'o', 'c', 'n', 'l', 'e', 9, 0, /* 3850 */ 'l', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, /* 3859 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 'e', 9, 0, /* 3869 */ 'j', 'g', 'n', 'l', 'e', 9, 0, /* 3876 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, /* 3886 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 'e', 9, 0, /* 3897 */ 'b', 'i', 'n', 'l', 'e', 9, 0, /* 3904 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'e', 9, 0, /* 3914 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'e', 9, 0, /* 3925 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'e', 9, 0, /* 3936 */ 'c', 'i', 'j', 'n', 'l', 'e', 9, 0, /* 3944 */ 'c', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, /* 3953 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'e', 9, 0, /* 3963 */ 'c', 'l', 'i', 'j', 'n', 'l', 'e', 9, 0, /* 3972 */ 'c', 'r', 'j', 'n', 'l', 'e', 9, 0, /* 3980 */ 'c', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, /* 3989 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'e', 9, 0, /* 3999 */ 'c', 'l', 'r', 'j', 'n', 'l', 'e', 9, 0, /* 4008 */ 'l', 'o', 'c', 'r', 'n', 'l', 'e', 9, 0, /* 4017 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'e', 9, 0, /* 4027 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'e', 9, 0, /* 4038 */ 'c', 'l', 'g', 't', 'n', 'l', 'e', 9, 0, /* 4047 */ 'c', 'i', 't', 'n', 'l', 'e', 9, 0, /* 4055 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'e', 9, 0, /* 4065 */ 'c', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, /* 4074 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'e', 9, 0, /* 4084 */ 'c', 'l', 't', 'n', 'l', 'e', 9, 0, /* 4092 */ 'c', 'r', 't', 'n', 'l', 'e', 9, 0, /* 4100 */ 'c', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, /* 4109 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'e', 9, 0, /* 4119 */ 'c', 'l', 'r', 't', 'n', 'l', 'e', 9, 0, /* 4128 */ 'l', 'o', 'c', 'r', 'l', 'e', 9, 0, /* 4136 */ 'l', 'o', 'c', 'g', 'r', 'l', 'e', 9, 0, /* 4145 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'e', 9, 0, /* 4155 */ 'c', 'l', 'g', 't', 'l', 'e', 9, 0, /* 4163 */ 'c', 'i', 't', 'l', 'e', 9, 0, /* 4170 */ 'c', 'l', 'f', 'i', 't', 'l', 'e', 9, 0, /* 4179 */ 'c', 'g', 'i', 't', 'l', 'e', 9, 0, /* 4187 */ 'c', 'l', 'g', 'i', 't', 'l', 'e', 9, 0, /* 4196 */ 'c', 'l', 't', 'l', 'e', 9, 0, /* 4203 */ 'c', 'r', 't', 'l', 'e', 9, 0, /* 4210 */ 'c', 'g', 'r', 't', 'l', 'e', 9, 0, /* 4218 */ 'c', 'l', 'g', 'r', 't', 'l', 'e', 9, 0, /* 4227 */ 'c', 'l', 'r', 't', 'l', 'e', 9, 0, /* 4235 */ 'b', 'x', 'l', 'e', 9, 0, /* 4241 */ 'b', 'r', 'x', 'l', 'e', 9, 0, /* 4248 */ 'v', 'm', 'e', 9, 0, /* 4253 */ 'c', 'i', 'b', 'n', 'e', 9, 0, /* 4260 */ 'c', 'g', 'i', 'b', 'n', 'e', 9, 0, /* 4268 */ 'c', 'l', 'g', 'i', 'b', 'n', 'e', 9, 0, /* 4277 */ 'c', 'l', 'i', 'b', 'n', 'e', 9, 0, /* 4285 */ 'c', 'r', 'b', 'n', 'e', 9, 0, /* 4292 */ 'c', 'g', 'r', 'b', 'n', 'e', 9, 0, /* 4300 */ 'c', 'l', 'g', 'r', 'b', 'n', 'e', 9, 0, /* 4309 */ 'c', 'l', 'r', 'b', 'n', 'e', 9, 0, /* 4317 */ 'l', 'o', 'c', 'n', 'e', 9, 0, /* 4324 */ 's', 't', 'o', 'c', 'n', 'e', 9, 0, /* 4332 */ 'v', 'f', 'e', 'n', 'e', 9, 0, /* 4339 */ 'l', 'o', 'c', 'g', 'n', 'e', 9, 0, /* 4347 */ 's', 't', 'o', 'c', 'g', 'n', 'e', 9, 0, /* 4356 */ 'j', 'g', 'n', 'e', 9, 0, /* 4362 */ 'l', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, /* 4371 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'e', 9, 0, /* 4381 */ 'b', 'i', 'n', 'e', 9, 0, /* 4387 */ 'l', 'o', 'c', 'h', 'i', 'n', 'e', 9, 0, /* 4396 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'e', 9, 0, /* 4406 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'e', 9, 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4585 */ 'c', 'l', 'r', 't', 'n', 'e', 9, 0, /* 4593 */ 's', 'q', 'e', 9, 0, /* 4598 */ 'l', 'o', 'c', 'r', 'e', 9, 0, /* 4605 */ 'l', 'o', 'c', 'g', 'r', 'e', 9, 0, /* 4613 */ 'l', 'o', 'c', 'f', 'h', 'r', 'e', 9, 0, /* 4622 */ 't', 'r', 't', 'r', 'e', 9, 0, /* 4629 */ 'm', 's', 'e', 9, 0, /* 4634 */ 'c', 'u', 's', 'e', 9, 0, /* 4640 */ 'i', 'd', 't', 'e', 9, 0, /* 4646 */ 'c', 'r', 'd', 't', 'e', 9, 0, /* 4653 */ 'c', 'l', 'g', 't', 'e', 9, 0, /* 4660 */ 'c', 'i', 't', 'e', 9, 0, /* 4666 */ 'c', 'l', 'f', 'i', 't', 'e', 9, 0, /* 4674 */ 'c', 'g', 'i', 't', 'e', 9, 0, /* 4681 */ 'c', 'l', 'g', 'i', 't', 'e', 9, 0, /* 4689 */ 'c', 'l', 't', 'e', 9, 0, /* 4695 */ 'i', 'p', 't', 'e', 9, 0, /* 4701 */ 'c', 'r', 't', 'e', 9, 0, /* 4707 */ 'c', 'g', 'r', 't', 'e', 9, 0, /* 4714 */ 'c', 'l', 'g', 'r', 't', 'e', 9, 0, /* 4722 */ 'c', 'l', 'r', 't', 'e', 9, 0, /* 4729 */ 't', 'r', 't', 'e', 9, 0, /* 4735 */ 's', 't', 'e', 9, 0, /* 4740 */ 'l', 'p', 's', 'w', 'e', 9, 0, /* 4747 */ 'l', 'x', 'e', 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*/ 'v', 'g', 'm', 'f', 9, 0, /* 5253 */ 'v', 'e', 'r', 'i', 'm', 'f', 9, 0, /* 5261 */ 'k', 'm', 'f', 9, 0, /* 5266 */ 'v', 'm', 'n', 'f', 9, 0, /* 5272 */ 'v', 'm', 'a', 'o', 'f', 9, 0, /* 5279 */ 'v', 'm', 'a', 'l', 'o', 'f', 9, 0, /* 5287 */ 'v', 'm', 'l', 'o', 'f', 9, 0, /* 5294 */ 'v', 'm', 'o', 'f', 9, 0, /* 5300 */ 'v', 'l', 'r', 'e', 'p', 'f', 9, 0, /* 5308 */ 'v', 'r', 'e', 'p', 'f', 9, 0, /* 5315 */ 'v', 'l', 'p', 'f', 9, 0, /* 5321 */ 'v', 'c', 'e', 'q', 'f', 9, 0, /* 5328 */ 'v', 's', 'u', 'm', 'q', 'f', 9, 0, /* 5336 */ 'v', 'i', 's', 't', 'r', 'f', 9, 0, /* 5344 */ 'l', 'z', 'r', 'f', 9, 0, /* 5350 */ 'v', 'p', 'k', 's', 'f', 9, 0, /* 5357 */ 'v', 'p', 'k', 'l', 's', 'f', 9, 0, /* 5365 */ 'v', 's', 'f', 9, 0, /* 5370 */ 'v', 'p', 'o', 'p', 'c', 't', 'f', 9, 0, /* 5379 */ 'p', 't', 'f', 9, 0, /* 5384 */ 'c', 'u', 'u', 't', 'f', 9, 0, /* 5391 */ 'v', 'e', 's', 'r', 'a', 'v', 'f', 9, 0, /* 5400 */ 'v', 'l', 'g', 'v', 'f', 9, 0, /* 5407 */ 'v', 'e', 'r', 'l', 'l', 'v', 'f', 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'r', 'o', 's', 'b', 'g', 9, 0, /* 5587 */ 'r', 'x', 's', 'b', 'g', 9, 0, /* 5594 */ 'v', 'c', 'v', 'b', 'g', 9, 0, /* 5601 */ 't', 'r', 'a', 'c', 'g', 9, 0, /* 5608 */ 'v', 'a', 'c', 'c', 'g', 9, 0, /* 5615 */ 'v', 'e', 'c', 'g', 9, 0, /* 5621 */ 'a', 'l', 'c', 'g', 9, 0, /* 5627 */ 'v', 'l', 'c', 'g', 9, 0, /* 5633 */ 'l', 'o', 'c', 'g', 9, 0, /* 5639 */ 's', 't', 'o', 'c', 'g', 9, 0, /* 5646 */ 'v', 'c', 'd', 'g', 9, 0, /* 5652 */ 'l', 'p', 'd', 'g', 9, 0, /* 5658 */ 'v', 'c', 'v', 'd', 'g', 9, 0, /* 5665 */ 'v', 's', 'c', 'e', 'g', 9, 0, /* 5672 */ 'v', 'g', 'e', 'g', 9, 0, /* 5678 */ 'v', 'l', 'e', 'g', 9, 0, /* 5684 */ 'b', 'x', 'l', 'e', 'g', 9, 0, /* 5691 */ 'e', 'r', 'e', 'g', 9, 0, /* 5697 */ 'v', 's', 'e', 'g', 9, 0, /* 5703 */ 'v', 's', 't', 'e', 'g', 9, 0, /* 5710 */ 'e', 'r', 'e', 'g', 'g', 9, 0, /* 5717 */ 'l', 'g', 'g', 9, 0, /* 5722 */ 'v', 'a', 'v', 'g', 'g', 9, 0, /* 5729 */ 'v', 'l', 'v', 'g', 'g', 9, 0, /* 5736 */ 'r', 'i', 's', 'b', 'h', 'g', 9, 0, /* 5744 */ 'v', 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'h', 9, 0, /* 6575 */ 'l', 'o', 'c', 'f', 'h', 'h', 9, 0, /* 6583 */ 's', 't', 'o', 'c', 'f', 'h', 'h', 9, 0, /* 6592 */ 'i', 'i', 'h', 'h', 9, 0, /* 6598 */ 'l', 'l', 'i', 'h', 'h', 9, 0, /* 6605 */ 'n', 'i', 'h', 'h', 9, 0, /* 6611 */ 'o', 'i', 'h', 'h', 9, 0, /* 6617 */ 'v', 'm', 'a', 'l', 'h', 'h', 9, 0, /* 6625 */ 'l', 'l', 'h', 'h', 9, 0, /* 6631 */ 'v', 'm', 'l', 'h', 'h', 9, 0, /* 6638 */ 'v', 'u', 'p', 'l', 'h', 'h', 9, 0, /* 6646 */ 't', 'm', 'h', 'h', 9, 0, /* 6652 */ 'v', 'm', 'h', 'h', 9, 0, /* 6658 */ 'v', 'u', 'p', 'h', 'h', 9, 0, /* 6665 */ 'v', 'm', 'r', 'h', 'h', 9, 0, /* 6672 */ 's', 't', 'h', 'h', 9, 0, /* 6678 */ 'a', 'i', 'h', 9, 0, /* 6683 */ 'v', 's', 'c', 'b', 'i', 'h', 9, 0, /* 6691 */ 'c', 'i', 'h', 9, 0, /* 6696 */ 'v', 'l', 'e', 'i', 'h', 9, 0, /* 6703 */ 'l', 'o', 'c', 'h', 'i', 'h', 9, 0, /* 6711 */ 'l', 'o', 'c', 'g', 'h', 'i', 'h', 9, 0, /* 6720 */ 'l', 'o', 'c', 'h', 'h', 'i', 'h', 9, 0, /* 6729 */ 'c', 'l', 'i', 'h', 9, 0, /* 6735 */ 'v', 'r', 'e', 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0, /* 7250 */ 'b', 'i', 'n', 'l', 'h', 9, 0, /* 7257 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 'h', 9, 0, /* 7267 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 'h', 9, 0, /* 7278 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 'h', 9, 0, /* 7289 */ 'c', 'i', 'j', 'n', 'l', 'h', 9, 0, /* 7297 */ 'c', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, /* 7306 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 'h', 9, 0, /* 7316 */ 'c', 'l', 'i', 'j', 'n', 'l', 'h', 9, 0, /* 7325 */ 'c', 'r', 'j', 'n', 'l', 'h', 9, 0, /* 7333 */ 'c', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, /* 7342 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 'h', 9, 0, /* 7352 */ 'c', 'l', 'r', 'j', 'n', 'l', 'h', 9, 0, /* 7361 */ 'v', 'm', 'n', 'l', 'h', 9, 0, /* 7368 */ 'l', 'o', 'c', 'r', 'n', 'l', 'h', 9, 0, /* 7377 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 'h', 9, 0, /* 7387 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 'h', 9, 0, /* 7398 */ 'c', 'l', 'g', 't', 'n', 'l', 'h', 9, 0, /* 7407 */ 'c', 'i', 't', 'n', 'l', 'h', 9, 0, /* 7415 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 'h', 9, 0, /* 7425 */ 'c', 'g', 'i', 't', 'n', 'l', 'h', 9, 0, /* 7434 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 'h', 9, 0, /* 7444 */ 'c', 'l', 't', 'n', 'l', 'h', 9, 0, /* 7452 */ 'c', 'r', 't', 'n', 'l', 'h', 9, 0, /* 7460 */ 'c', 'g', 'r', 't', 'n', 'l', 'h', 9, 0, /* 7469 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 'h', 9, 0, /* 7479 */ 'c', 'l', 'r', 't', 'n', 'l', 'h', 9, 0, /* 7488 */ 'v', 'u', 'p', 'l', 'h', 9, 0, /* 7495 */ 'l', 'o', 'c', 'r', 'l', 'h', 9, 0, /* 7503 */ 'l', 'o', 'c', 'g', 'r', 'l', 'h', 9, 0, /* 7512 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 'h', 9, 0, /* 7522 */ 'v', 'm', 'r', 'l', 'h', 9, 0, /* 7529 */ 'v', 'e', 's', 'r', 'l', 'h', 9, 0, /* 7537 */ 'v', 'e', 's', 'l', 'h', 9, 0, /* 7544 */ 'c', 'l', 'g', 't', 'l', 'h', 9, 0, /* 7552 */ 'c', 'i', 't', 'l', 'h', 9, 0, /* 7559 */ 'c', 'l', 'f', 'i', 't', 'l', 'h', 9, 0, /* 7568 */ 'c', 'g', 'i', 't', 'l', 'h', 9, 0, /* 7576 */ 'c', 'l', 'g', 'i', 't', 'l', 'h', 9, 0, /* 7585 */ 'c', 'l', 't', 'l', 'h', 9, 0, /* 7592 */ 'c', 'r', 't', 'l', 'h', 9, 0, /* 7599 */ 'c', 'g', 'r', 't', 'l', 'h', 9, 0, /* 7607 */ 'c', 'l', 'g', 'r', 't', 'l', 'h', 9, 0, /* 7616 */ 'c', 'l', 'r', 't', 'l', 'h', 9, 0, /* 7624 */ 'v', 'm', 'x', 'l', 'h', 9, 0, /* 7631 */ 'i', 'c', 'm', 'h', 9, 0, /* 7637 */ 's', 't', 'c', 'm', 'h', 9, 0, /* 7644 */ 'v', 'g', 'f', 'm', 'h', 9, 0, /* 7651 */ 'v', 'g', 'm', 'h', 9, 0, /* 7657 */ 'v', 'e', 'r', 'i', 'm', 'h', 9, 0, /* 7665 */ 'c', 'l', 'm', 'h', 9, 0, /* 7671 */ 's', 't', 'm', 'h', 9, 0, /* 7677 */ 'v', 's', 'u', 'm', 'h', 9, 0, /* 7684 */ 'v', 'm', 'h', 9, 0, /* 7689 */ 'c', 'i', 'b', 'n', 'h', 9, 0, /* 7696 */ 'c', 'g', 'i', 'b', 'n', 'h', 9, 0, /* 7704 */ 'c', 'l', 'g', 'i', 'b', 'n', 'h', 9, 0, /* 7713 */ 'c', 'l', 'i', 'b', 'n', 'h', 9, 0, /* 7721 */ 'c', 'r', 'b', 'n', 'h', 9, 0, /* 7728 */ 'c', 'g', 'r', 'b', 'n', 'h', 9, 0, /* 7736 */ 'c', 'l', 'g', 'r', 'b', 'n', 'h', 9, 0, /* 7745 */ 'c', 'l', 'r', 'b', 'n', 'h', 9, 0, /* 7753 */ 'l', 'o', 'c', 'n', 'h', 9, 0, /* 7760 */ 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7932 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'h', 9, 0, /* 7942 */ 'c', 'l', 'g', 't', 'n', 'h', 9, 0, /* 7950 */ 'c', 'i', 't', 'n', 'h', 9, 0, /* 7957 */ 'c', 'l', 'f', 'i', 't', 'n', 'h', 9, 0, /* 7966 */ 'c', 'g', 'i', 't', 'n', 'h', 9, 0, /* 7974 */ 'c', 'l', 'g', 'i', 't', 'n', 'h', 9, 0, /* 7983 */ 'c', 'l', 't', 'n', 'h', 9, 0, /* 7990 */ 'c', 'r', 't', 'n', 'h', 9, 0, /* 7997 */ 'c', 'g', 'r', 't', 'n', 'h', 9, 0, /* 8005 */ 'c', 'l', 'g', 'r', 't', 'n', 'h', 9, 0, /* 8014 */ 'c', 'l', 'r', 't', 'n', 'h', 9, 0, /* 8022 */ 'v', 'm', 'a', 'o', 'h', 9, 0, /* 8029 */ 'v', 'm', 'a', 'l', 'o', 'h', 9, 0, /* 8037 */ 'v', 'm', 'l', 'o', 'h', 9, 0, /* 8044 */ 'v', 'm', 'o', 'h', 9, 0, /* 8050 */ 'v', 'l', 'r', 'e', 'p', 'h', 9, 0, /* 8058 */ 'v', 'r', 'e', 'p', 'h', 9, 0, /* 8065 */ 'v', 'l', 'p', 'h', 9, 0, /* 8071 */ 'v', 'u', 'p', 'h', 9, 0, /* 8077 */ 'v', 'c', 'e', 'q', 'h', 9, 0, /* 8084 */ 'l', 'o', 'c', 'r', 'h', 9, 0, /* 8091 */ 'l', 'o', 'c', 'g', 'r', 'h', 9, 0, /* 8099 */ 'l', 'o', 'c', 'f', 'h', 'r', 'h', 9, 0, /* 8108 */ 'v', 'm', 'r', 'h', 9, 0, /* 8114 */ 'v', 'i', 's', 't', 'r', 'h', 9, 0, /* 8122 */ 'v', 'p', 'k', 's', 'h', 9, 0, /* 8129 */ 'v', 'p', 'k', 'l', 's', 'h', 9, 0, /* 8137 */ 'v', 's', 'h', 9, 0, /* 8142 */ 'v', 'p', 'o', 'p', 'c', 't', 'h', 9, 0, /* 8151 */ 'b', 'r', 'c', 't', 'h', 9, 0, /* 8158 */ 'c', 'l', 'g', 't', 'h', 9, 0, /* 8165 */ 'c', 'i', 't', 'h', 9, 0, /* 8171 */ 'c', 'l', 'f', 'i', 't', 'h', 9, 0, /* 8179 */ 'c', 'g', 'i', 't', 'h', 9, 0, /* 8186 */ 'c', 'l', 'g', 'i', 't', 'h', 9, 0, /* 8194 */ 'c', 'l', 't', 'h', 9, 0, /* 8200 */ 'c', 'r', 't', 'h', 9, 0, /* 8206 */ 'c', 'g', 'r', 't', 'h', 9, 0, /* 8213 */ 'c', 'l', 'g', 'r', 't', 'h', 9, 0, /* 8221 */ 'c', 'l', 'r', 't', 'h', 9, 0, /* 8228 */ 's', 't', 'h', 9, 0, /* 8233 */ 'v', 'e', 's', 'r', 'a', 'v', 'h', 9, 0, /* 8242 */ 'v', 'l', 'g', 'v', 'h', 9, 0, /* 8249 */ 'v', 'e', 'r', 'l', 'l', 'v', 'h', 9, 0, /* 8258 */ 'v', 'e', 's', 'r', 'l', 'v', 'h', 9, 0, /* 8267 */ 'v', 'e', 's', 'l', 'v', 'h', 9, 0, /* 8275 */ 'l', 'r', 'v', 'h', 9, 0, /* 8281 */ 's', 't', 'r', 'v', 'h', 9, 0, /* 8288 */ 'b', 'x', 'h', 9, 0, /* 8293 */ 'v', 'm', 'x', 'h', 9, 0, /* 8299 */ 'b', 'r', 'x', 'h', 9, 0, /* 8305 */ 'm', 'a', 'y', 'h', 9, 0, /* 8311 */ 'm', 'y', 'h', 9, 0, /* 8316 */ 'v', 's', 't', 'r', 'c', 'z', 'h', 9, 0, /* 8325 */ 'v', 'f', 'a', 'e', 'z', 'h', 9, 0, /* 8333 */ 'v', 'f', 'e', 'e', 'z', 'h', 9, 0, /* 8341 */ 'v', 'l', 'l', 'e', 'z', 'h', 9, 0, /* 8349 */ 'v', 'f', 'e', 'n', 'e', 'z', 'h', 9, 0, /* 8358 */ 'v', 'c', 'l', 'z', 'h', 9, 0, /* 8365 */ 'v', 'c', 't', 'z', 'h', 9, 0, /* 8372 */ 'n', 'i', 'a', 'i', 9, 0, /* 8378 */ 'v', 's', 'b', 'c', 'b', 'i', 9, 0, /* 8386 */ 'v', 's', 'c', 'b', 'i', 9, 0, /* 8393 */ 'v', 's', 'b', 'i', 9, 0, /* 8399 */ 'v', 'f', 't', 'c', 'i', 9, 0, /* 8406 */ 'v', 'p', 'd', 'i', 9, 0, /* 8412 */ 'a', 'f', 'i', 9, 0, /* 8417 */ 'c', 'f', 'i', 9, 0, /* 8422 */ 'a', 'g', 'f', 'i', 9, 0, /* 8428 */ 'c', 'g', 'f', 'i', 9, 0, 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9, 0, /* 8923 */ 's', 'r', 'k', 9, 0, /* 8928 */ 'x', 'r', 'k', 9, 0, /* 8933 */ 'm', 'v', 'c', 's', 'k', 9, 0, /* 8940 */ 'i', 'v', 's', 'k', 9, 0, /* 8946 */ 'l', 'a', 'a', 'l', 9, 0, /* 8952 */ 'b', 'a', 'l', 9, 0, /* 8957 */ 'v', 'm', 'a', 'l', 9, 0, /* 8963 */ 'c', 'i', 'b', 'l', 9, 0, /* 8969 */ 'c', 'g', 'i', 'b', 'l', 9, 0, /* 8976 */ 'c', 'l', 'g', 'i', 'b', 'l', 9, 0, /* 8984 */ 'c', 'l', 'i', 'b', 'l', 9, 0, /* 8991 */ 'c', 'r', 'b', 'l', 9, 0, /* 8997 */ 'c', 'g', 'r', 'b', 'l', 9, 0, /* 9004 */ 'c', 'l', 'g', 'r', 'b', 'l', 9, 0, /* 9012 */ 'c', 'l', 'r', 'b', 'l', 9, 0, /* 9019 */ 'v', 'e', 'c', 'l', 9, 0, /* 9025 */ 'c', 'l', 'c', 'l', 9, 0, /* 9031 */ 'l', 'o', 'c', 'l', 9, 0, /* 9037 */ 's', 't', 'o', 'c', 'l', 9, 0, /* 9044 */ 'b', 'r', 'c', 'l', 9, 0, /* 9050 */ 'm', 'v', 'c', 'l', 9, 0, /* 9056 */ 's', 'l', 'd', 'l', 9, 0, /* 9062 */ 's', 'r', 'd', 'l', 9, 0, /* 9068 */ 'v', 's', 'e', 'l', 9, 0, /* 9074 */ 's', 't', 'f', 'l', 9, 0, /* 9080 */ 'l', 'o', 'c', 'g', 'l', 9, 0, /* 9087 */ 's', 't', 'o', 'c', 'g', 'l', 9, 0, /* 9095 */ 'j', 'g', 'l', 9, 0, /* 9100 */ 'v', 'a', 'v', 'g', 'l', 9, 0, /* 9107 */ 'v', 'c', 'h', 'l', 9, 0, /* 9113 */ 'l', 'o', 'c', 'f', 'h', 'l', 9, 0, /* 9121 */ 's', 't', 'o', 'c', 'f', 'h', 'l', 9, 0, /* 9130 */ 'i', 'i', 'h', 'l', 9, 0, /* 9136 */ 'l', 'l', 'i', 'h', 'l', 9, 0, /* 9143 */ 'n', 'i', 'h', 'l', 9, 0, /* 9149 */ 'o', 'i', 'h', 'l', 9, 0, /* 9155 */ 't', 'm', 'h', 'l', 9, 0, /* 9161 */ 'b', 'i', 'l', 9, 0, /* 9166 */ 'l', 'o', 'c', 'h', 'i', 'l', 9, 0, /* 9174 */ 'l', 'o', 'c', 'g', 'h', 'i', 'l', 9, 0, /* 9183 */ 'l', 'o', 'c', 'h', 'h', 'i', 'l', 9, 0, /* 9192 */ 'c', 'i', 'j', 'l', 9, 0, /* 9198 */ 'c', 'g', 'i', 'j', 'l', 9, 0, /* 9205 */ 'c', 'l', 'g', 'i', 'j', 'l', 9, 0, /* 9213 */ 'c', 'l', 'i', 'j', 'l', 9, 0, /* 9220 */ 'c', 'r', 'j', 'l', 9, 0, /* 9226 */ 'c', 'g', 'r', 'j', 'l', 9, 0, /* 9233 */ 'c', 'l', 'g', 'r', 'j', 'l', 9, 0, /* 9241 */ 'c', 'l', 'r', 'j', 'l', 9, 0, /* 9248 */ 'v', 'f', 'l', 'l', 9, 0, /* 9254 */ 'i', 'i', 'l', 'l', 9, 0, /* 9260 */ 'l', 'l', 'i', 'l', 'l', 9, 0, /* 9267 */ 'n', 'i', 'l', 'l', 9, 0, /* 9273 */ 'o', 'i', 'l', 'l', 9, 0, /* 9279 */ 't', 'm', 'l', 'l', 9, 0, /* 9285 */ 'v', 'u', 'p', 'l', 'l', 9, 0, /* 9292 */ 'v', 'e', 'r', 'l', 'l', 9, 0, /* 9299 */ 's', 'l', 'l', 9, 0, /* 9304 */ 'v', 'l', 'l', 9, 0, /* 9309 */ 'v', 'm', 'l', 9, 0, /* 9314 */ 'c', 'i', 'b', 'n', 'l', 9, 0, /* 9321 */ 'c', 'g', 'i', 'b', 'n', 'l', 9, 0, /* 9329 */ 'c', 'l', 'g', 'i', 'b', 'n', 'l', 9, 0, /* 9338 */ 'c', 'l', 'i', 'b', 'n', 'l', 9, 0, /* 9346 */ 'c', 'r', 'b', 'n', 'l', 9, 0, /* 9353 */ 'c', 'g', 'r', 'b', 'n', 'l', 9, 0, /* 9361 */ 'c', 'l', 'g', 'r', 'b', 'n', 'l', 9, 0, /* 9370 */ 'c', 'l', 'r', 'b', 'n', 'l', 9, 0, /* 9378 */ 'l', 'o', 'c', 'n', 'l', 9, 0, /* 9385 */ 's', 't', 'o', 'c', 'n', 'l', 9, 0, /* 9393 */ 'l', 'o', 'c', 'g', 'n', 'l', 9, 0, /* 9401 */ 's', 't', 'o', 'c', 'g', 'n', 'l', 9, 0, /* 9410 */ 'j', 'g', 'n', 'l', 9, 0, /* 9416 */ 'l', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, /* 9425 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'l', 9, 0, /* 9435 */ 'b', 'i', 'n', 'l', 9, 0, /* 9441 */ 'l', 'o', 'c', 'h', 'i', 'n', 'l', 9, 0, /* 9450 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'l', 9, 0, /* 9460 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'l', 9, 0, /* 9470 */ 'c', 'i', 'j', 'n', 'l', 9, 0, /* 9477 */ 'c', 'g', 'i', 'j', 'n', 'l', 9, 0, /* 9485 */ 'c', 'l', 'g', 'i', 'j', 'n', 'l', 9, 0, /* 9494 */ 'c', 'l', 'i', 'j', 'n', 'l', 9, 0, /* 9502 */ 'c', 'r', 'j', 'n', 'l', 9, 0, /* 9509 */ 'c', 'g', 'r', 'j', 'n', 'l', 9, 0, /* 9517 */ 'c', 'l', 'g', 'r', 'j', 'n', 'l', 9, 0, /* 9526 */ 'c', 'l', 'r', 'j', 'n', 'l', 9, 0, /* 9534 */ 'v', 'm', 'n', 'l', 9, 0, /* 9540 */ 'l', 'o', 'c', 'r', 'n', 'l', 9, 0, /* 9548 */ 'l', 'o', 'c', 'g', 'r', 'n', 'l', 9, 0, /* 9557 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'l', 9, 0, /* 9567 */ 'c', 'l', 'g', 't', 'n', 'l', 9, 0, /* 9575 */ 'c', 'i', 't', 'n', 'l', 9, 0, /* 9582 */ 'c', 'l', 'f', 'i', 't', 'n', 'l', 9, 0, /* 9591 */ 'c', 'g', 'i', 't', 'n', 'l', 9, 0, /* 9599 */ 'c', 'l', 'g', 'i', 't', 'n', 'l', 9, 0, /* 9608 */ 'c', 'l', 't', 'n', 'l', 9, 0, /* 9615 */ 'c', 'r', 't', 'n', 'l', 9, 0, /* 9622 */ 'c', 'g', 'r', 't', 'n', 'l', 9, 0, /* 9630 */ 'c', 'l', 'g', 'r', 't', 'n', 'l', 9, 0, /* 9639 */ 'c', 'l', 'r', 't', 'n', 'l', 9, 0, /* 9647 */ 'v', 'u', 'p', 'l', 9, 0, /* 9653 */ 'l', 'a', 'r', 'l', 9, 0, /* 9659 */ 'l', 'o', 'c', 'r', 'l', 9, 0, /* 9666 */ 'p', 'f', 'd', 'r', 'l', 9, 0, /* 9673 */ 'c', 'g', 'f', 'r', 'l', 9, 0, /* 9680 */ 'c', 'l', 'g', 'f', 'r', 'l', 9, 0, /* 9688 */ 'l', 'l', 'g', 'f', 'r', 'l', 9, 0, /* 9696 */ 'l', 'o', 'c', 'g', 'r', 'l', 9, 0, /* 9704 */ 'c', 'l', 'g', 'r', 'l', 9, 0, /* 9711 */ 's', 't', 'g', 'r', 'l', 9, 0, /* 9718 */ 'c', 'h', 'r', 'l', 9, 0, /* 9724 */ 'l', 'o', 'c', 'f', 'h', 'r', 'l', 9, 0, /* 9733 */ 'c', 'g', 'h', 'r', 'l', 9, 0, /* 9740 */ 'c', 'l', 'g', 'h', 'r', 'l', 9, 0, /* 9748 */ 'l', 'l', 'g', 'h', 'r', 'l', 9, 0, /* 9756 */ 'c', 'l', 'h', 'r', 'l', 9, 0, /* 9763 */ 'l', 'l', 'h', 'r', 'l', 9, 0, /* 9770 */ 's', 't', 'h', 'r', 'l', 9, 0, /* 9777 */ 'c', 'l', 'r', 'l', 9, 0, /* 9783 */ 'v', 'l', 'r', 'l', 9, 0, /* 9789 */ 'v', 'm', 'r', 'l', 9, 0, /* 9795 */ 'v', 'e', 's', 'r', 'l', 9, 0, /* 9802 */ 'v', 's', 'r', 'l', 9, 0, /* 9808 */ 'v', 's', 't', 'r', 'l', 9, 0, /* 9815 */ 'e', 'x', 'r', 'l', 9, 0, /* 9821 */ 'b', 'r', 'a', 's', 'l', 9, 0, /* 9828 */ 'v', 'e', 's', 'l', 9, 0, /* 9834 */ 'v', 'm', 's', 'l', 9, 0, /* 9840 */ 'v', 's', 'l', 9, 0, /* 9845 */ 'l', 'c', 'c', 't', 'l', 9, 0, /* 9852 */ 'l', 'c', 't', 'l', 9, 0, /* 9858 */ 'l', 'p', 'c', 't', 'l', 9, 0, /* 9865 */ 'l', 's', 'c', 't', 'l', 9, 0, /* 9872 */ 's', 't', 'c', 't', 'l', 9, 0, /* 9879 */ 'c', 'l', 'g', 't', 'l', 9, 0, /* 9886 */ 'c', 'i', 't', 'l', 9, 0, /* 9892 */ 'c', 'l', 'f', 'i', 't', 'l', 9, 0, /* 9900 */ 'c', 'g', 'i', 't', 'l', 9, 0, /* 9907 */ 'c', 'l', 'g', 'i', 't', 'l', 9, 0, /* 9915 */ 'c', 'l', 't', 'l', 9, 0, /* 9921 */ 'c', 'r', 't', 'l', 9, 0, /* 9927 */ 'c', 'g', 'r', 't', 'l', 9, 0, /* 9934 */ 'c', 'l', 'g', 'r', 't', 'l', 9, 0, /* 9942 */ 'c', 'l', 'r', 't', 'l', 9, 0, /* 9949 */ 'v', 's', 't', 'l', 9, 0, /* 9955 */ 'v', 'l', 9, 0, /* 9959 */ 'v', 'm', 'x', 'l', 9, 0, /* 9965 */ 'm', 'a', 'y', 'l', 9, 0, /* 9971 */ 'm', 'y', 'l', 9, 0, /* 9976 */ 'l', 'a', 'm', 9, 0, /* 9981 */ 's', 't', 'a', 'm', 9, 0, /* 9987 */ 'v', 'g', 'b', 'm', 9, 0, /* 9993 */ 'i', 'r', 'b', 'm', 9, 0, /* 9999 */ 'r', 'r', 'b', 'm', 9, 0, /* 10005 */ 'i', 'c', 'm', 9, 0, /* 10010 */ 'l', 'o', 'c', 'm', 9, 0, /* 10016 */ 's', 't', 'o', 'c', 'm', 9, 0, /* 10023 */ 's', 't', 'c', 'm', 9, 0, /* 10029 */ 'v', 'g', 'f', 'm', 9, 0, /* 10035 */ 'v', 'f', 'm', 9, 0, /* 10040 */ 'l', 'o', 'c', 'g', 'm', 9, 0, /* 10047 */ 's', 't', 'o', 'c', 'g', 'm', 9, 0, /* 10055 */ 'j', 'g', 'm', 9, 0, /* 10060 */ 'v', 'g', 'm', 9, 0, /* 10065 */ 'l', 'o', 'c', 'f', 'h', 'm', 9, 0, /* 10073 */ 's', 't', 'o', 'c', 'f', 'h', 'm', 9, 0, /* 10082 */ 'b', 'i', 'm', 9, 0, /* 10087 */ 'l', 'o', 'c', 'h', 'i', 'm', 9, 0, /* 10095 */ 'l', 'o', 'c', 'g', 'h', 'i', 'm', 9, 0, /* 10104 */ 'l', 'o', 'c', 'h', 'h', 'i', 'm', 9, 0, /* 10113 */ 'v', 'e', 'r', 'i', 'm', 9, 0, /* 10120 */ 'j', 'm', 9, 0, /* 10124 */ 'k', 'm', 9, 0, /* 10128 */ 'c', 'l', 'm', 9, 0, /* 10133 */ 'v', 'l', 'm', 9, 0, /* 10138 */ 'b', 'n', 'm', 9, 0, /* 10143 */ 'l', 'o', 'c', 'n', 'm', 9, 0, /* 10150 */ 's', 't', 'o', 'c', 'n', 'm', 9, 0, /* 10158 */ 'l', 'o', 'c', 'g', 'n', 'm', 9, 0, /* 10166 */ 's', 't', 'o', 'c', 'g', 'n', 'm', 9, 0, /* 10175 */ 'j', 'g', 'n', 'm', 9, 0, /* 10181 */ 'l', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, /* 10190 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'm', 9, 0, /* 10200 */ 'b', 'i', 'n', 'm', 9, 0, /* 10206 */ 'l', 'o', 'c', 'h', 'i', 'n', 'm', 9, 0, /* 10215 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'm', 9, 0, /* 10225 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'm', 9, 0, /* 10235 */ 'j', 'n', 'm', 9, 0, /* 10240 */ 'l', 'o', 'c', 'r', 'n', 'm', 9, 0, /* 10248 */ 'l', 'o', 'c', 'g', 'r', 'n', 'm', 9, 0, /* 10257 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'm', 9, 0, /* 10267 */ 's', 'r', 'n', 'm', 9, 0, /* 10273 */ 'i', 'p', 'm', 9, 0, /* 10278 */ 's', 'p', 'm', 9, 0, /* 10283 */ 'l', 'o', 'c', 'r', 'm', 9, 0, /* 10290 */ 'v', 'b', 'p', 'e', 'r', 'm', 9, 0, /* 10298 */ 'v', 'p', 'e', 'r', 'm', 9, 0, /* 10305 */ 'l', 'o', 'c', 'g', 'r', 'm', 9, 0, /* 10313 */ 'l', 'o', 'c', 'f', 'h', 'r', 'm', 9, 0, /* 10322 */ 'b', 's', 'm', 9, 0, /* 10327 */ 'v', 'c', 'k', 's', 'm', 9, 0, /* 10334 */ 's', 't', 'n', 's', 'm', 9, 0, /* 10341 */ 's', 't', 'o', 's', 'm', 9, 0, /* 10348 */ 'b', 'a', 's', 's', 'm', 9, 0, /* 10355 */ 'v', 's', 't', 'm', 9, 0, /* 10361 */ 'v', 't', 'm', 9, 0, /* 10366 */ 'v', 's', 'u', 'm', 9, 0, /* 10372 */ 'l', 'a', 'n', 9, 0, /* 10377 */ 'r', 'i', 's', 'b', 'g', 'n', 9, 0, /* 10385 */ 'a', 'l', 's', 'i', 'h', 'n', 9, 0, /* 10393 */ 'm', 'v', 'c', 'i', 'n', 9, 0, /* 10400 */ 't', 'b', 'e', 'g', 'i', 'n', 9, 0, /* 10408 */ 'p', 'g', 'i', 'n', 9, 0, /* 10414 */ 'v', 'f', 'm', 'i', 'n', 9, 0, /* 10421 */ 'v', 'm', 'n', 9, 0, /* 10426 */ 'v', 'n', 'n', 9, 0, /* 10431 */ 'm', 'v', 'n', 9, 0, /* 10436 */ 'l', 'a', 'o', 9, 0, /* 10441 */ 'v', 'm', 'a', 'o', 9, 0, /* 10447 */ 'b', 'o', 9, 0, /* 10451 */ 'l', 'o', 'c', 'o', 9, 0, /* 10457 */ 's', 't', 'o', 'c', 'o', 9, 0, /* 10464 */ 'l', 'o', 'c', 'g', 'o', 9, 0, /* 10471 */ 's', 't', 'o', 'c', 'g', 'o', 9, 0, /* 10479 */ 'j', 'g', 'o', 9, 0, /* 10484 */ 'l', 'o', 'c', 'f', 'h', 'o', 9, 0, /* 10492 */ 's', 't', 'o', 'c', 'f', 'h', 'o', 9, 0, /* 10501 */ 'b', 'i', 'o', 9, 0, /* 10506 */ 'l', 'o', 'c', 'h', 'i', 'o', 9, 0, /* 10514 */ 'l', 'o', 'c', 'g', 'h', 'i', 'o', 9, 0, /* 10523 */ 'l', 'o', 'c', 'h', 'h', 'i', 'o', 9, 0, /* 10532 */ 'j', 'o', 9, 0, /* 10536 */ 'v', 'm', 'a', 'l', 'o', 9, 0, /* 10543 */ 'v', 'm', 'l', 'o', 9, 0, /* 10549 */ 'p', 'l', 'o', 9, 0, /* 10554 */ 'k', 'm', 'o', 9, 0, /* 10559 */ 'v', 'm', 'o', 9, 0, /* 10564 */ 'b', 'n', 'o', 9, 0, /* 10569 */ 'l', 'o', 'c', 'n', 'o', 9, 0, /* 10576 */ 's', 't', 'o', 'c', 'n', 'o', 9, 0, /* 10584 */ 'l', 'o', 'c', 'g', 'n', 'o', 9, 0, /* 10592 */ 's', 't', 'o', 'c', 'g', 'n', 'o', 9, 0, /* 10601 */ 'j', 'g', 'n', 'o', 9, 0, /* 10607 */ 'l', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, /* 10616 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'o', 9, 0, /* 10626 */ 'b', 'i', 'n', 'o', 9, 0, /* 10632 */ 'l', 'o', 'c', 'h', 'i', 'n', 'o', 9, 0, /* 10641 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'o', 9, 0, /* 10651 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'o', 9, 0, /* 10661 */ 'j', 'n', 'o', 9, 0, /* 10666 */ 'p', 'p', 'n', 'o', 9, 0, /* 10672 */ 'l', 'o', 'c', 'r', 'n', 'o', 9, 0, /* 10680 */ 'l', 'o', 'c', 'g', 'r', 'n', 'o', 9, 0, /* 10689 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'o', 9, 0, /* 10699 */ 'p', 'r', 'n', 'o', 9, 0, /* 10705 */ 'v', 'n', 'o', 9, 0, /* 10710 */ 't', 'r', 'o', 'o', 9, 0, /* 10716 */ 'l', 'o', 'c', 'r', 'o', 9, 0, /* 10723 */ 'v', 'z', 'e', 'r', 'o', 9, 0, /* 10730 */ 'l', 'o', 'c', 'g', 'r', 'o', 9, 0, /* 10738 */ 'l', 'o', 'c', 'f', 'h', 'r', 'o', 9, 0, /* 10747 */ 'v', 'f', 'p', 's', 'o', 9, 0, /* 10754 */ 't', 'r', 't', 'o', 9, 0, /* 10760 */ 'm', 'v', 'o', 9, 0, /* 10765 */ 's', 't', 'a', 'p', 9, 0, /* 10771 */ 'v', 'a', 'p', 9, 0, /* 10776 */ 'z', 'a', 'p', 9, 0, /* 10781 */ 'b', 'p', 9, 0, /* 10785 */ 'l', 'o', 'c', 'p', 9, 0, /* 10791 */ 's', 't', 'o', 'c', 'p', 9, 0, /* 10798 */ 'm', 'v', 'c', 'p', 9, 0, /* 10804 */ 's', 't', 'i', 'd', 'p', 9, 0, /* 10811 */ 'v', 's', 'd', 'p', 9, 0, /* 10817 */ 'v', 'd', 'p', 9, 0, /* 10822 */ 'v', 'l', 'r', 'e', 'p', 9, 0, /* 10829 */ 'v', 'r', 'e', 'p', 9, 0, /* 10835 */ 'l', 'o', 'c', 'g', 'p', 9, 0, /* 10842 */ 's', 't', 'o', 'c', 'g', 'p', 9, 0, /* 10850 */ 's', 'i', 'g', 'p', 9, 0, /* 10856 */ 'j', 'g', 'p', 9, 0, /* 10861 */ 'v', 'l', 'v', 'g', 'p', 9, 0, /* 10868 */ 'l', 'o', 'c', 'f', 'h', 'p', 9, 0, /* 10876 */ 's', 't', 'o', 'c', 'f', 'h', 'p', 9, 0, /* 10885 */ 'b', 'i', 'p', 9, 0, /* 10890 */ 'l', 'o', 'c', 'h', 'i', 'p', 9, 0, /* 10898 */ 'l', 'o', 'c', 'g', 'h', 'i', 'p', 9, 0, /* 10907 */ 'l', 'o', 'c', 'h', 'h', 'i', 'p', 9, 0, /* 10916 */ 'v', 'l', 'i', 'p', 9, 0, /* 10922 */ 'j', 'p', 9, 0, /* 10926 */ 'v', 'l', 'p', 9, 0, /* 10931 */ 'v', 'm', 'p', 9, 0, /* 10936 */ 'b', 'n', 'p', 9, 0, /* 10941 */ 'l', 'o', 'c', 'n', 'p', 9, 0, /* 10948 */ 's', 't', 'o', 'c', 'n', 'p', 9, 0, /* 10956 */ 'l', 'o', 'c', 'g', 'n', 'p', 9, 0, /* 10964 */ 's', 't', 'o', 'c', 'g', 'n', 'p', 9, 0, /* 10973 */ 'j', 'g', 'n', 'p', 9, 0, /* 10979 */ 'l', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, /* 10988 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'p', 9, 0, /* 10998 */ 'b', 'i', 'n', 'p', 9, 0, /* 11004 */ 'l', 'o', 'c', 'h', 'i', 'n', 'p', 9, 0, /* 11013 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'p', 9, 0, /* 11023 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'p', 9, 0, /* 11033 */ 'j', 'n', 'p', 9, 0, /* 11038 */ 'l', 'o', 'c', 'r', 'n', 'p', 9, 0, /* 11046 */ 'l', 'o', 'c', 'g', 'r', 'n', 'p', 9, 0, /* 11055 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'p', 9, 0, /* 11065 */ 'v', 'p', 's', 'o', 'p', 9, 0, /* 11072 */ 'b', 'p', 'p', 9, 0, /* 11077 */ 'l', 'p', 'p', 9, 0, /* 11082 */ 'l', 'o', 'c', 'r', 'p', 9, 0, /* 11089 */ 'l', 'o', 'c', 'g', 'r', 'p', 9, 0, /* 11097 */ 'l', 'o', 'c', 'f', 'h', 'r', 'p', 9, 0, /* 11106 */ 'b', 'p', 'r', 'p', 9, 0, /* 11112 */ 'v', 's', 'r', 'p', 9, 0, /* 11118 */ 'v', 'r', 'p', 9, 0, /* 11123 */ 'l', 'a', 's', 'p', 9, 0, /* 11129 */ 'c', 's', 'p', 9, 0, /* 11134 */ 'v', 'm', 's', 'p', 9, 0, /* 11140 */ 'v', 's', 'p', 9, 0, /* 11145 */ 'v', 't', 'p', 9, 0, /* 11150 */ 'v', 'a', 'q', 9, 0, /* 11155 */ 'v', 'a', 'c', 'q', 9, 0, /* 11161 */ 'v', 'a', 'c', 'c', 'q', 9, 0, /* 11168 */ 'v', 'a', 'c', 'c', 'c', 'q', 9, 0, /* 11176 */ 'v', 'c', 'e', 'q', 9, 0, /* 11182 */ 'v', 's', 'b', 'c', 'b', 'i', 'q', 9, 0, /* 11191 */ 'v', 's', 'c', 'b', 'i', 'q', 9, 0, /* 11199 */ 'v', 's', 'b', 'i', 'q', 9, 0, /* 11206 */ 'v', 's', 'u', 'm', 'q', 9, 0, /* 11213 */ 'l', 'p', 'q', 9, 0, /* 11218 */ 's', 't', 'p', 'q', 9, 0, /* 11224 */ 'v', 'f', 's', 'q', 9, 0, /* 11230 */ 'v', 's', 'q', 9, 0, /* 11235 */ 'e', 'a', 'r', 9, 0, /* 11240 */ 'e', 'p', 'a', 'r', 9, 0, /* 11246 */ 'e', 's', 'a', 'r', 9, 0, /* 11252 */ 's', 's', 'a', 'r', 9, 0, /* 11258 */ 't', 'a', 'r', 9, 0, /* 11263 */ 'm', 'a', 'd', 'b', 'r', 9, 0, /* 11270 */ 'l', 'c', 'd', 'b', 'r', 9, 0, /* 11277 */ 'd', 'd', 'b', 'r', 9, 0, /* 11283 */ 'l', 'e', 'd', 'b', 'r', 9, 0, /* 11290 */ 'c', 'f', 'd', 'b', 'r', 9, 0, /* 11297 */ 'c', 'l', 'f', 'd', 'b', 'r', 9, 0, /* 11305 */ 'c', 'g', 'd', 'b', 'r', 9, 0, /* 11312 */ 'c', 'l', 'g', 'd', 'b', 'r', 9, 0, /* 11320 */ 'd', 'i', 'd', 'b', 'r', 9, 0, /* 11327 */ 'f', 'i', 'd', 'b', 'r', 9, 0, /* 11334 */ 'k', 'd', 'b', 'r', 9, 0, /* 11340 */ 'm', 'd', 'b', 'r', 9, 0, /* 11346 */ 'l', 'n', 'd', 'b', 'r', 9, 0, /* 11353 */ 'l', 'p', 'd', 'b', 'r', 9, 0, /* 11360 */ 's', 'q', 'd', 'b', 'r', 9, 0, /* 11367 */ 'm', 's', 'd', 'b', 'r', 9, 0, /* 11374 */ 'l', 't', 'd', 'b', 'r', 9, 0, /* 11381 */ 'l', 'x', 'd', 'b', 'r', 9, 0, /* 11388 */ 'm', 'x', 'd', 'b', 'r', 9, 0, /* 11395 */ 'm', 'a', 'e', 'b', 'r', 9, 0, /* 11402 */ 'l', 'c', 'e', 'b', 'r', 9, 0, /* 11409 */ 'l', 'd', 'e', 'b', 'r', 9, 0, /* 11416 */ 'm', 'd', 'e', 'b', 'r', 9, 0, /* 11423 */ 'm', 'e', 'e', 'b', 'r', 9, 0, /* 11430 */ 'c', 'f', 'e', 'b', 'r', 9, 0, /* 11437 */ 'c', 'l', 'f', 'e', 'b', 'r', 9, 0, /* 11445 */ 'c', 'g', 'e', 'b', 'r', 9, 0, /* 11452 */ 'c', 'l', 'g', 'e', 'b', 'r', 9, 0, /* 11460 */ 'd', 'i', 'e', 'b', 'r', 9, 0, /* 11467 */ 'f', 'i', 'e', 'b', 'r', 9, 0, /* 11474 */ 'k', 'e', 'b', 'r', 9, 0, /* 11480 */ 'l', 'n', 'e', 'b', 'r', 9, 0, /* 11487 */ 'l', 'p', 'e', 'b', 'r', 9, 0, /* 11494 */ 's', 'q', 'e', 'b', 'r', 9, 0, /* 11501 */ 'm', 's', 'e', 'b', 'r', 9, 0, /* 11508 */ 'l', 't', 'e', 'b', 'r', 9, 0, /* 11515 */ 'l', 'x', 'e', 'b', 'r', 9, 0, /* 11522 */ 'c', 'd', 'f', 'b', 'r', 9, 0, /* 11529 */ 'c', 'e', 'f', 'b', 'r', 9, 0, /* 11536 */ 'c', 'd', 'l', 'f', 'b', 'r', 9, 0, /* 11544 */ 'c', 'e', 'l', 'f', 'b', 'r', 9, 0, /* 11552 */ 'c', 'x', 'l', 'f', 'b', 'r', 9, 0, /* 11560 */ 'c', 'x', 'f', 'b', 'r', 9, 0, /* 11567 */ 'c', 'd', 'g', 'b', 'r', 9, 0, /* 11574 */ 'c', 'e', 'g', 'b', 'r', 9, 0, /* 11581 */ 'c', 'd', 'l', 'g', 'b', 'r', 9, 0, /* 11589 */ 'c', 'e', 'l', 'g', 'b', 'r', 9, 0, /* 11597 */ 'c', 'x', 'l', 'g', 'b', 'r', 9, 0, /* 11605 */ 'c', 'x', 'g', 'b', 'r', 9, 0, /* 11612 */ 's', 'l', 'b', 'r', 9, 0, /* 11618 */ 'a', 'x', 'b', 'r', 9, 0, /* 11624 */ 'l', 'c', 'x', 'b', 'r', 9, 0, /* 11631 */ 'l', 'd', 'x', 'b', 'r', 9, 0, /* 11638 */ 'l', 'e', 'x', 'b', 'r', 9, 0, /* 11645 */ 'c', 'f', 'x', 'b', 'r', 9, 0, /* 11652 */ 'c', 'l', 'f', 'x', 'b', 'r', 9, 0, /* 11660 */ 'c', 'g', 'x', 'b', 'r', 9, 0, /* 11667 */ 'c', 'l', 'g', 'x', 'b', 'r', 9, 0, /* 11675 */ 'f', 'i', 'x', 'b', 'r', 9, 0, /* 11682 */ 'k', 'x', 'b', 'r', 9, 0, /* 11688 */ 'm', 'x', 'b', 'r', 9, 0, /* 11694 */ 'l', 'n', 'x', 'b', 'r', 9, 0, /* 11701 */ 'l', 'p', 'x', 'b', 'r', 9, 0, /* 11708 */ 's', 'q', 'x', 'b', 'r', 9, 0, /* 11715 */ 's', 'x', 'b', 'r', 9, 0, /* 11721 */ 'l', 't', 'x', 'b', 'r', 9, 0, /* 11728 */ 'b', 'c', 'r', 9, 0, /* 11733 */ 'l', 'l', 'g', 'c', 'r', 9, 0, /* 11740 */ 'a', 'l', 'c', 'r', 9, 0, /* 11746 */ 'l', 'l', 'c', 'r', 9, 0, /* 11752 */ 'l', 'o', 'c', 'r', 9, 0, /* 11758 */ 'm', 'a', 'd', 'r', 9, 0, /* 11764 */ 't', 'b', 'd', 'r', 9, 0, /* 11770 */ 'l', 'c', 'd', 'r', 9, 0, /* 11776 */ 'd', 'd', 'r', 9, 0, /* 11781 */ 't', 'b', 'e', 'd', 'r', 9, 0, /* 11788 */ 'l', 'e', 'd', 'r', 9, 0, /* 11794 */ 'c', 'f', 'd', 'r', 9, 0, /* 11800 */ 'c', 'g', 'd', 'r', 9, 0, /* 11806 */ 'l', 'g', 'd', 'r', 9, 0, /* 11812 */ 't', 'h', 'd', 'r', 9, 0, /* 11818 */ 'f', 'i', 'd', 'r', 9, 0, /* 11824 */ 'l', 'd', 'r', 9, 0, /* 11829 */ 'm', 'd', 'r', 9, 0, /* 11834 */ 'l', 'n', 'd', 'r', 9, 0, /* 11840 */ 'l', 'p', 'd', 'r', 9, 0, /* 11846 */ 's', 'q', 'd', 'r', 9, 0, /* 11852 */ 'l', 'r', 'd', 'r', 9, 0, /* 11858 */ 'm', 's', 'd', 'r', 9, 0, /* 11864 */ 'c', 'p', 's', 'd', 'r', 9, 0, /* 11871 */ 'l', 't', 'd', 'r', 9, 0, /* 11877 */ 'l', 'x', 'd', 'r', 9, 0, /* 11883 */ 'm', 'x', 'd', 'r', 9, 0, /* 11889 */ 'l', 'z', 'd', 'r', 9, 0, /* 11895 */ 'm', 'a', 'e', 'r', 9, 0, /* 11901 */ 'b', 'e', 'r', 9, 0, /* 11906 */ 'l', 'c', 'e', 'r', 9, 0, /* 11912 */ 't', 'h', 'd', 'e', 'r', 9, 0, /* 11919 */ 'l', 'd', 'e', 'r', 9, 0, /* 11925 */ 'm', 'd', 'e', 'r', 9, 0, /* 11931 */ 'm', 'e', 'e', 'r', 9, 0, /* 11937 */ 'c', 'f', 'e', 'r', 9, 0, /* 11943 */ 'c', 'g', 'e', 'r', 9, 0, /* 11949 */ 'b', 'h', 'e', 'r', 9, 0, /* 11955 */ 'b', 'n', 'h', 'e', 'r', 9, 0, /* 11962 */ 'f', 'i', 'e', 'r', 9, 0, /* 11968 */ 'b', 'l', 'e', 'r', 9, 0, /* 11974 */ 'b', 'n', 'l', 'e', 'r', 9, 0, /* 11981 */ 'm', 'e', 'r', 9, 0, /* 11986 */ 'b', 'n', 'e', 'r', 9, 0, /* 11992 */ 'l', 'n', 'e', 'r', 9, 0, /* 11998 */ 'l', 'p', 'e', 'r', 9, 0, /* 12004 */ 's', 'q', 'e', 'r', 9, 0, /* 12010 */ 'l', 'r', 'e', 'r', 9, 0, /* 12016 */ 'm', 's', 'e', 'r', 9, 0, /* 12022 */ 'l', 't', 'e', 'r', 9, 0, /* 12028 */ 'l', 'x', 'e', 'r', 9, 0, /* 12034 */ 'l', 'z', 'e', 'r', 9, 0, /* 12040 */ 'l', 'c', 'd', 'f', 'r', 9, 0, /* 12047 */ 'l', 'n', 'd', 'f', 'r', 9, 0, /* 12054 */ 'l', 'p', 'd', 'f', 'r', 9, 0, /* 12061 */ 'c', 'e', 'f', 'r', 9, 0, /* 12067 */ 'a', 'g', 'f', 'r', 9, 0, /* 12073 */ 'l', 'c', 'g', 'f', 'r', 9, 0, /* 12080 */ 'a', 'l', 'g', 'f', 'r', 9, 0, /* 12087 */ 'c', 'l', 'g', 'f', 'r', 9, 0, /* 12094 */ 'l', 'l', 'g', 'f', 'r', 9, 0, /* 12101 */ 's', 'l', 'g', 'f', 'r', 9, 0, /* 12108 */ 'l', 'n', 'g', 'f', 'r', 9, 0, /* 12115 */ 'l', 'p', 'g', 'f', 'r', 9, 0, /* 12122 */ 'd', 's', 'g', 'f', 'r', 9, 0, /* 12129 */ 'm', 's', 'g', 'f', 'r', 9, 0, /* 12136 */ 'l', 't', 'g', 'f', 'r', 9, 0, /* 12143 */ 'c', 'x', 'f', 'r', 9, 0, /* 12149 */ 'a', 'g', 'r', 9, 0, /* 12154 */ 's', 'l', 'b', 'g', 'r', 9, 0, /* 12161 */ 'a', 'l', 'c', 'g', 'r', 9, 0, /* 12168 */ 'l', 'o', 'c', 'g', 'r', 9, 0, /* 12175 */ 'c', 'd', 'g', 'r', 9, 0, /* 12181 */ 'l', 'd', 'g', 'r', 9, 0, /* 12187 */ 'c', 'e', 'g', 'r', 9, 0, /* 12193 */ 'a', 'l', 'g', 'r', 9, 0, /* 12199 */ 'c', 'l', 'g', 'r', 9, 0, /* 12205 */ 'd', 'l', 'g', 'r', 9, 0, /* 12211 */ 'm', 'l', 'g', 'r', 9, 0, /* 12217 */ 's', 'l', 'g', 'r', 9, 0, /* 12223 */ 'l', 'n', 'g', 'r', 9, 0, /* 12229 */ 'f', 'l', 'o', 'g', 'r', 9, 0, /* 12236 */ 'l', 'p', 'g', 'r', 9, 0, /* 12242 */ 'd', 's', 'g', 'r', 9, 0, /* 12248 */ 'm', 's', 'g', 'r', 9, 0, /* 12254 */ 'b', 'c', 't', 'g', 'r', 9, 0, /* 12261 */ 'l', 't', 'g', 'r', 9, 0, /* 12267 */ 'l', 'r', 'v', 'g', 'r', 9, 0, /* 12274 */ 'c', 'x', 'g', 'r', 9, 0, /* 12280 */ 'b', 'h', 'r', 9, 0, /* 12285 */ 'l', 'o', 'c', 'f', 'h', 'r', 9, 0, /* 12293 */ 'l', 'l', 'g', 'h', 'r', 9, 0, /* 12300 */ 'c', 'h', 'h', 'r', 9, 0, /* 12306 */ 'a', 'h', 'h', 'h', 'r', 9, 0, /* 12313 */ 'a', 'l', 'h', 'h', 'h', 'r', 9, 0, /* 12321 */ 's', 'l', 'h', 'h', 'h', 'r', 9, 0, /* 12329 */ 's', 'h', 'h', 'h', 'r', 9, 0, /* 12336 */ 'c', 'l', 'h', 'h', 'r', 9, 0, /* 12343 */ 'b', 'l', 'h', 'r', 9, 0, /* 12349 */ 'l', 'l', 'h', 'r', 9, 0, /* 12355 */ 'b', 'n', 'l', 'h', 'r', 9, 0, /* 12362 */ 'b', 'n', 'h', 'r', 9, 0, /* 12368 */ 'm', 'a', 'y', 'h', 'r', 9, 0, /* 12375 */ 'm', 'y', 'h', 'r', 9, 0, /* 12381 */ 'e', 'p', 'a', 'i', 'r', 9, 0, /* 12388 */ 'e', 's', 'a', 'i', 'r', 9, 0, /* 12395 */ 's', 's', 'a', 'i', 'r', 9, 0, /* 12402 */ 'b', 'a', 'k', 'r', 9, 0, /* 12408 */ 'b', 'a', 'l', 'r', 9, 0, /* 12414 */ 'b', 'l', 'r', 9, 0, /* 12419 */ 'c', 'l', 'r', 9, 0, /* 12424 */ 'd', 'l', 'r', 9, 0, /* 12429 */ 'v', 'f', 'l', 'r', 9, 0, /* 12435 */ 'c', 'h', 'l', 'r', 9, 0, /* 12441 */ 'a', 'h', 'h', 'l', 'r', 9, 0, /* 12448 */ 'a', 'l', 'h', 'h', 'l', 'r', 9, 0, /* 12456 */ 's', 'l', 'h', 'h', 'l', 'r', 9, 0, /* 12464 */ 's', 'h', 'h', 'l', 'r', 9, 0, /* 12471 */ 'c', 'l', 'h', 'l', 'r', 9, 0, /* 12478 */ 'm', 'l', 'r', 9, 0, /* 12483 */ 'b', 'n', 'l', 'r', 9, 0, /* 12489 */ 'v', 'l', 'r', 'l', 'r', 9, 0, /* 12496 */ 'v', 's', 't', 'r', 'l', 'r', 9, 0, /* 12504 */ 's', 'l', 'r', 9, 0, /* 12509 */ 'v', 'l', 'r', 9, 0, /* 12514 */ 'm', 'a', 'y', 'l', 'r', 9, 0, /* 12521 */ 'm', 'y', 'l', 'r', 9, 0, /* 12527 */ 'b', 'm', 'r', 9, 0, /* 12532 */ 'b', 'n', 'm', 'r', 9, 0, /* 12538 */ 'l', 'n', 'r', 9, 0, /* 12543 */ 'b', 'o', 'r', 9, 0, /* 12548 */ 'b', 'n', 'o', 'r', 9, 0, /* 12554 */ 'b', 'p', 'r', 9, 0, /* 12559 */ 'l', 'p', 'r', 9, 0, /* 12564 */ 'b', 'n', 'p', 'r', 9, 0, /* 12570 */ 'b', 'a', 's', 'r', 9, 0, /* 12576 */ 's', 'f', 'a', 's', 'r', 9, 0, /* 12583 */ 'm', 's', 'r', 9, 0, /* 12588 */ 'b', 'c', 't', 'r', 9, 0, /* 12594 */ 'e', 'c', 'c', 't', 'r', 9, 0, /* 12601 */ 's', 'c', 'c', 't', 'r', 9, 0, /* 12608 */ 'k', 'm', 'c', 't', 'r', 9, 0, /* 12615 */ 'e', 'p', 'c', 't', 'r', 9, 0, /* 12622 */ 's', 'p', 'c', 't', 'r', 9, 0, /* 12629 */ 'q', 'a', 'd', 't', 'r', 9, 0, /* 12636 */ 'c', 'd', 't', 'r', 9, 0, /* 12642 */ 'd', 'd', 't', 'r', 9, 0, /* 12648 */ 'c', 'e', 'd', 't', 'r', 9, 0, /* 12655 */ 'e', 'e', 'd', 't', 'r', 9, 0, /* 12662 */ 'i', 'e', 'd', 't', 'r', 9, 0, /* 12669 */ 'l', 'e', 'd', 't', 'r', 9, 0, /* 12676 */ 'c', 'f', 'd', 't', 'r', 9, 0, /* 12683 */ 'c', 'l', 'f', 'd', 't', 'r', 9, 0, /* 12691 */ 'c', 'g', 'd', 't', 'r', 9, 0, /* 12698 */ 'c', 'l', 'g', 'd', 't', 'r', 9, 0, /* 12706 */ 'f', 'i', 'd', 't', 'r', 9, 0, /* 12713 */ 'k', 'd', 't', 'r', 9, 0, /* 12719 */ 'm', 'd', 't', 'r', 9, 0, /* 12725 */ 'r', 'r', 'd', 't', 'r', 9, 0, /* 12732 */ 'c', 's', 'd', 't', 'r', 9, 0, /* 12739 */ 'e', 's', 'd', 't', 'r', 9, 0, /* 12746 */ 'l', 't', 'd', 't', 'r', 9, 0, /* 12753 */ 'c', 'u', 'd', 't', 'r', 9, 0, /* 12760 */ 'l', 'x', 'd', 't', 'r', 9, 0, /* 12767 */ 'l', 'd', 'e', 't', 'r', 9, 0, /* 12774 */ 'c', 'd', 'f', 't', 'r', 9, 0, /* 12781 */ 'c', 'd', 'l', 'f', 't', 'r', 9, 0, /* 12789 */ 'c', 'x', 'l', 'f', 't', 'r', 9, 0, /* 12797 */ 'c', 'x', 'f', 't', 'r', 9, 0, /* 12804 */ 'c', 'd', 'g', 't', 'r', 9, 0, /* 12811 */ 'c', 'd', 'l', 'g', 't', 'r', 9, 0, /* 12819 */ 'l', 'l', 'g', 't', 'r', 9, 0, /* 12826 */ 'c', 'x', 'l', 'g', 't', 'r', 9, 0, /* 12834 */ 'c', 'x', 'g', 't', 'r', 9, 0, /* 12841 */ 'l', 't', 'r', 9, 0, /* 12846 */ 't', 'r', 't', 'r', 9, 0, /* 12852 */ 'c', 'd', 's', 't', 'r', 9, 0, /* 12859 */ 'v', 'i', 's', 't', 'r', 9, 0, /* 12866 */ 'c', 'x', 's', 't', 'r', 9, 0, /* 12873 */ 'c', 'd', 'u', 't', 'r', 9, 0, /* 12880 */ 'c', 'x', 'u', 't', 'r', 9, 0, /* 12887 */ 'q', 'a', 'x', 't', 'r', 9, 0, /* 12894 */ 'c', 'x', 't', 'r', 9, 0, /* 12900 */ 'l', 'd', 'x', 't', 'r', 9, 0, /* 12907 */ 'c', 'e', 'x', 't', 'r', 9, 0, /* 12914 */ 'e', 'e', 'x', 't', 'r', 9, 0, /* 12921 */ 'i', 'e', 'x', 't', 'r', 9, 0, /* 12928 */ 'c', 'f', 'x', 't', 'r', 9, 0, /* 12935 */ 'c', 'l', 'f', 'x', 't', 'r', 9, 0, /* 12943 */ 'c', 'g', 'x', 't', 'r', 9, 0, /* 12950 */ 'c', 'l', 'g', 'x', 't', 'r', 9, 0, /* 12958 */ 'f', 'i', 'x', 't', 'r', 9, 0, /* 12965 */ 'k', 'x', 't', 'r', 9, 0, /* 12971 */ 'm', 'x', 't', 'r', 9, 0, /* 12977 */ 'r', 'r', 'x', 't', 'r', 9, 0, /* 12984 */ 'c', 's', 'x', 't', 'r', 9, 0, /* 12991 */ 'e', 's', 'x', 't', 'r', 9, 0, /* 12998 */ 'l', 't', 'x', 't', 'r', 9, 0, /* 13005 */ 'c', 'u', 'x', 't', 'r', 9, 0, /* 13012 */ 'a', 'u', 'r', 9, 0, /* 13017 */ 's', 'u', 'r', 9, 0, /* 13022 */ 'l', 'r', 'v', 'r', 9, 0, /* 13028 */ 'a', 'w', 'r', 9, 0, /* 13033 */ 's', 'w', 'r', 9, 0, /* 13038 */ 'a', 'x', 'r', 9, 0, /* 13043 */ 'l', 'c', 'x', 'r', 9, 0, /* 13049 */ 'l', 'd', 'x', 'r', 9, 0, /* 13055 */ 'l', 'e', 'x', 'r', 9, 0, /* 13061 */ 'c', 'f', 'x', 'r', 9, 0, /* 13067 */ 'c', 'g', 'x', 'r', 9, 0, /* 13073 */ 'f', 'i', 'x', 'r', 9, 0, /* 13079 */ 'l', 'x', 'r', 9, 0, /* 13084 */ 'm', 'x', 'r', 9, 0, /* 13089 */ 'l', 'n', 'x', 'r', 9, 0, /* 13095 */ 'l', 'p', 'x', 'r', 9, 0, /* 13101 */ 's', 'q', 'x', 'r', 9, 0, /* 13107 */ 's', 'x', 'r', 9, 0, /* 13112 */ 'l', 't', 'x', 'r', 9, 0, /* 13118 */ 'l', 'z', 'x', 'r', 9, 0, /* 13124 */ 'm', 'a', 'y', 'r', 9, 0, /* 13130 */ 'm', 'y', 'r', 9, 0, /* 13135 */ 'b', 'z', 'r', 9, 0, /* 13140 */ 'b', 'n', 'z', 'r', 9, 0, /* 13146 */ 'b', 'a', 's', 9, 0, /* 13151 */ 'l', 'f', 'a', 's', 9, 0, /* 13157 */ 'b', 'r', 'a', 's', 9, 0, /* 13163 */ 'v', 's', 't', 'r', 'c', 'b', 's', 9, 0, /* 13172 */ 'v', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, /* 13181 */ 'w', 'f', 'c', 'e', 'd', 'b', 's', 9, 0, /* 13190 */ 'v', 'f', 'c', 'h', 'e', 'd', 'b', 's', 9, 0, /* 13200 */ 'w', 'f', 'c', 'h', 'e', 'd', 'b', 's', 9, 0, /* 13210 */ 'v', 'f', 'k', 'h', 'e', 'd', 'b', 's', 9, 0, /* 13220 */ 'w', 'f', 'k', 'h', 'e', 'd', 'b', 's', 9, 0, /* 13230 */ 'v', 'f', 'k', 'e', 'd', 'b', 's', 9, 0, /* 13239 */ 'w', 'f', 'k', 'e', 'd', 'b', 's', 9, 0, /* 13248 */ 'v', 'f', 'c', 'h', 'd', 'b', 's', 9, 0, /* 13257 */ 'w', 'f', 'c', 'h', 'd', 'b', 's', 9, 0, /* 13266 */ 'v', 'f', 'k', 'h', 'd', 'b', 's', 9, 0, /* 13275 */ 'w', 'f', 'k', 'h', 'd', 'b', 's', 9, 0, /* 13284 */ 'v', 'f', 'a', 'e', 'b', 's', 9, 0, /* 13292 */ 'v', 'f', 'e', 'e', 'b', 's', 9, 0, /* 13300 */ 'v', 'f', 'e', 'n', 'e', 'b', 's', 9, 0, /* 13309 */ 'v', 'c', 'h', 'b', 's', 9, 0, /* 13316 */ 'v', 'c', 'h', 'l', 'b', 's', 9, 0, /* 13324 */ 'v', 'c', 'e', 'q', 'b', 's', 9, 0, /* 13332 */ 'v', 'i', 's', 't', 'r', 'b', 's', 9, 0, /* 13341 */ 'v', 'f', 'c', 'e', 's', 'b', 's', 9, 0, /* 13350 */ 'w', 'f', 'c', 'e', 's', 'b', 's', 9, 0, /* 13359 */ 'v', 'f', 'c', 'h', 'e', 's', 'b', 's', 9, 0, /* 13369 */ 'w', 'f', 'c', 'h', 'e', 's', 'b', 's', 9, 0, /* 13379 */ 'v', 'f', 'k', 'h', 'e', 's', 'b', 's', 9, 0, /* 13389 */ 'w', 'f', 'k', 'h', 'e', 's', 'b', 's', 9, 0, /* 13399 */ 'v', 'f', 'k', 'e', 's', 'b', 's', 9, 0, /* 13408 */ 'w', 'f', 'k', 'e', 's', 'b', 's', 9, 0, /* 13417 */ 'v', 'f', 'c', 'h', 's', 'b', 's', 9, 0, /* 13426 */ 'w', 'f', 'c', 'h', 's', 'b', 's', 9, 0, /* 13435 */ 'v', 'f', 'k', 'h', 's', 'b', 's', 9, 0, /* 13444 */ 'w', 'f', 'k', 'h', 's', 'b', 's', 9, 0, /* 13453 */ 'w', 'f', 'c', 'e', 'x', 'b', 's', 9, 0, /* 13462 */ 'w', 'f', 'c', 'h', 'e', 'x', 'b', 's', 9, 0, /* 13472 */ 'w', 'f', 'k', 'h', 'e', 'x', 'b', 's', 9, 0, /* 13482 */ 'w', 'f', 'k', 'e', 'x', 'b', 's', 9, 0, /* 13491 */ 'w', 'f', 'c', 'h', 'x', 'b', 's', 9, 0, /* 13500 */ 'w', 'f', 'k', 'h', 'x', 'b', 's', 9, 0, /* 13509 */ 'v', 's', 't', 'r', 'c', 'z', 'b', 's', 9, 0, /* 13519 */ 'v', 'f', 'a', 'e', 'z', 'b', 's', 9, 0, /* 13528 */ 'v', 'f', 'e', 'e', 'z', 'b', 's', 9, 0, /* 13537 */ 'v', 'f', 'e', 'n', 'e', 'z', 'b', 's', 9, 0, /* 13547 */ 'm', 'v', 'c', 's', 9, 0, /* 13553 */ 'c', 'd', 's', 9, 0, /* 13558 */ 'v', 's', 't', 'r', 'c', 'f', 's', 9, 0, /* 13567 */ 'v', 'f', 'a', 'e', 'f', 's', 9, 0, /* 13575 */ 'v', 'f', 'e', 'e', 'f', 's', 9, 0, /* 13583 */ 'v', 'f', 'e', 'n', 'e', 'f', 's', 9, 0, /* 13592 */ 'v', 'c', 'h', 'f', 's', 9, 0, /* 13599 */ 'v', 'c', 'h', 'l', 'f', 's', 9, 0, /* 13607 */ 'v', 'c', 'e', 'q', 'f', 's', 9, 0, /* 13615 */ 'v', 'i', 's', 't', 'r', 'f', 's', 9, 0, /* 13624 */ 'v', 'p', 'k', 's', 'f', 's', 9, 0, /* 13632 */ 'v', 'p', 'k', 'l', 's', 'f', 's', 9, 0, /* 13641 */ 'v', 'f', 's', 9, 0, /* 13646 */ 'v', 's', 't', 'r', 'c', 'z', 'f', 's', 9, 0, /* 13656 */ 'v', 'f', 'a', 'e', 'z', 'f', 's', 9, 0, /* 13665 */ 'v', 'f', 'e', 'e', 'z', 'f', 's', 9, 0, /* 13674 */ 'v', 'f', 'e', 'n', 'e', 'z', 'f', 's', 9, 0, /* 13684 */ 'v', 'c', 'h', 'g', 's', 9, 0, /* 13691 */ 'v', 'c', 'h', 'l', 'g', 's', 9, 0, /* 13699 */ 'v', 'c', 'e', 'q', 'g', 's', 9, 0, /* 13707 */ 'v', 'p', 'k', 's', 'g', 's', 9, 0, /* 13715 */ 'v', 'p', 'k', 'l', 's', 'g', 's', 9, 0, /* 13724 */ 'v', 's', 't', 'r', 'c', 'h', 's', 9, 0, /* 13733 */ 'v', 'f', 'a', 'e', 'h', 's', 9, 0, /* 13741 */ 'v', 'f', 'e', 'e', 'h', 's', 9, 0, /* 13749 */ 'v', 'f', 'e', 'n', 'e', 'h', 's', 9, 0, /* 13758 */ 'v', 'c', 'h', 'h', 's', 9, 0, /* 13765 */ 'v', 'c', 'h', 'l', 'h', 's', 9, 0, /* 13773 */ 'v', 'c', 'e', 'q', 'h', 's', 9, 0, /* 13781 */ 'v', 'i', 's', 't', 'r', 'h', 's', 9, 0, /* 13790 */ 'v', 'p', 'k', 's', 'h', 's', 9, 0, /* 13798 */ 'v', 'p', 'k', 'l', 's', 'h', 's', 9, 0, /* 13807 */ 'v', 's', 't', 'r', 'c', 'z', 'h', 's', 9, 0, /* 13817 */ 'v', 'f', 'a', 'e', 'z', 'h', 's', 9, 0, /* 13826 */ 'v', 'f', 'e', 'e', 'z', 'h', 's', 9, 0, /* 13835 */ 'v', 'f', 'e', 'n', 'e', 'z', 'h', 's', 9, 0, /* 13845 */ 'v', 'p', 'k', 's', 9, 0, /* 13851 */ 'v', 'p', 'k', 'l', 's', 9, 0, /* 13858 */ 'v', 'f', 'l', 'l', 's', 9, 0, /* 13865 */ 'w', 'f', 'l', 'l', 's', 9, 0, /* 13872 */ 'v', 'f', 'm', 's', 9, 0, /* 13878 */ 'v', 'f', 'n', 'm', 's', 9, 0, /* 13885 */ 'm', 'v', 'c', 'o', 's', 9, 0, /* 13892 */ 's', 't', 'c', 'p', 's', 9, 0, /* 13899 */ 't', 's', 9, 0, /* 13903 */ 'v', 's', 9, 0, /* 13907 */ 'l', 'l', 'g', 'f', 'a', 't', 9, 0, /* 13915 */ 'l', 'g', 'a', 't', 9, 0, /* 13921 */ 'l', 'f', 'h', 'a', 't', 9, 0, /* 13928 */ 'l', 'a', 't', 9, 0, /* 13933 */ 'l', 'l', 'g', 't', 'a', 't', 9, 0, /* 13941 */ 'b', 'c', 't', 9, 0, /* 13946 */ 'v', 'p', 'o', 'p', 'c', 't', 9, 0, /* 13954 */ 'b', 'r', 'c', 't', 9, 0, /* 13960 */ 't', 'd', 'c', 'd', 't', 9, 0, /* 13967 */ 't', 'd', 'g', 'd', 't', 9, 0, /* 13974 */ 's', 'l', 'd', 't', 9, 0, /* 13980 */ 'c', 'p', 'd', 't', 9, 0, /* 13986 */ 's', 'r', 'd', 't', 9, 0, /* 13992 */ 'c', 'z', 'd', 't', 9, 0, /* 13998 */ 't', 'd', 'c', 'e', 't', 9, 0, /* 14005 */ 't', 'd', 'g', 'e', 't', 9, 0, /* 14012 */ 'c', 'l', 'g', 't', 9, 0, /* 14018 */ 'l', 'l', 'g', 't', 9, 0, /* 14024 */ 'c', 'i', 't', 9, 0, /* 14029 */ 'c', 'l', 'f', 'i', 't', 9, 0, /* 14036 */ 'c', 'g', 'i', 't', 9, 0, /* 14042 */ 'c', 'l', 'g', 'i', 't', 9, 0, /* 14049 */ 'c', 'l', 't', 9, 0, /* 14054 */ 's', 'r', 'n', 'm', 't', 9, 0, /* 14061 */ 'p', 'o', 'p', 'c', 'n', 't', 9, 0, /* 14069 */ 't', 'p', 'r', 'o', 't', 9, 0, /* 14076 */ 't', 'r', 'o', 't', 9, 0, /* 14082 */ 'c', 'd', 'p', 't', 9, 0, /* 14088 */ 's', 'p', 't', 9, 0, /* 14093 */ 's', 't', 'p', 't', 9, 0, /* 14099 */ 'c', 'x', 'p', 't', 9, 0, /* 14105 */ 'c', 'r', 't', 9, 0, /* 14110 */ 'c', 'g', 'r', 't', 9, 0, /* 14116 */ 'c', 'l', 'g', 'r', 't', 9, 0, /* 14123 */ 'c', 'l', 'r', 't', 9, 0, /* 14129 */ 't', 'a', 'b', 'o', 'r', 't', 9, 0, /* 14137 */ 't', 'r', 't', 9, 0, /* 14142 */ 'c', 'l', 's', 't', 9, 0, /* 14148 */ 's', 'r', 's', 't', 9, 0, /* 14154 */ 'c', 's', 's', 't', 9, 0, /* 14160 */ 'm', 'v', 's', 't', 9, 0, /* 14166 */ 't', 'r', 't', 't', 9, 0, /* 14172 */ 'p', 'g', 'o', 'u', 't', 9, 0, /* 14179 */ 't', 'd', 'c', 'x', 't', 9, 0, /* 14186 */ 't', 'd', 'g', 'x', 't', 9, 0, /* 14193 */ 's', 'l', 'x', 't', 9, 0, /* 14199 */ 'c', 'p', 'x', 't', 9, 0, /* 14205 */ 's', 'r', 'x', 't', 9, 0, /* 14211 */ 'c', 'z', 'x', 't', 9, 0, /* 14217 */ 'c', 'd', 'z', 't', 9, 0, /* 14223 */ 'c', 'x', 'z', 't', 9, 0, /* 14229 */ 'a', 'u', 9, 0, /* 14233 */ 'c', 'u', 't', 'f', 'u', 9, 0, /* 14240 */ 'u', 'n', 'p', 'k', 'u', 9, 0, /* 14247 */ 'c', 'l', 'c', 'l', 'u', 9, 0, /* 14254 */ 'm', 'v', 'c', 'l', 'u', 9, 0, /* 14261 */ 's', 'u', 9, 0, /* 14265 */ 's', 'r', 's', 't', 'u', 9, 0, /* 14272 */ 'v', 'e', 's', 'r', 'a', 'v', 9, 0, /* 14280 */ 'v', 'l', 'g', 'v', 9, 0, /* 14286 */ 'v', 'e', 'r', 'l', 'l', 'v', 9, 0, /* 14294 */ 'v', 'e', 's', 'r', 'l', 'v', 9, 0, /* 14302 */ 'v', 'e', 's', 'l', 'v', 9, 0, /* 14309 */ 'l', 'r', 'v', 9, 0, /* 14314 */ 's', 't', 'r', 'v', 9, 0, /* 14320 */ 'a', 'w', 9, 0, /* 14324 */ 'v', 'm', 'a', 'l', 'h', 'w', 9, 0, /* 14332 */ 'v', 'm', 'l', 'h', 'w', 9, 0, /* 14339 */ 'v', 'u', 'p', 'l', 'h', 'w', 9, 0, /* 14347 */ 's', 't', 'c', 'r', 'w', 9, 0, /* 14354 */ 'e', 'p', 's', 'w', 9, 0, /* 14360 */ 'l', 'p', 's', 'w', 9, 0, /* 14366 */ 'l', 'a', 'x', 9, 0, /* 14371 */ 'v', 'f', 'm', 'a', 'x', 9, 0, /* 14378 */ 'e', 'x', 9, 0, /* 14382 */ 'v', 'm', 'x', 9, 0, /* 14387 */ 'v', 'n', 'x', 9, 0, /* 14392 */ 's', 'p', 'x', 9, 0, /* 14397 */ 's', 't', 'p', 'x', 9, 0, /* 14403 */ 'w', 'f', 'l', 'r', 'x', 9, 0, /* 14410 */ 'v', 'x', 9, 0, /* 14414 */ 'l', 'a', 'y', 9, 0, /* 14419 */ 'm', 'a', 'y', 9, 0, /* 14424 */ 'l', 'r', 'a', 'y', 9, 0, /* 14430 */ 'c', 'v', 'b', 'y', 9, 0, /* 14436 */ 'i', 'c', 'y', 9, 0, /* 14441 */ 's', 't', 'c', 'y', 9, 0, /* 14447 */ 'l', 'd', 'y', 9, 0, /* 14452 */ 's', 't', 'd', 'y', 9, 0, /* 14458 */ 'c', 'v', 'd', 'y', 9, 0, /* 14464 */ 'l', 'a', 'e', 'y', 9, 0, /* 14470 */ 'l', 'e', 'y', 9, 0, /* 14475 */ 's', 't', 'e', 'y', 9, 0, /* 14481 */ 'm', 'f', 'y', 9, 0, /* 14486 */ 'a', 'h', 'y', 9, 0, /* 14491 */ 'c', 'h', 'y', 9, 0, /* 14496 */ 'l', 'h', 'y', 9, 0, /* 14501 */ 'm', 'h', 'y', 9, 0, /* 14506 */ 's', 'h', 'y', 9, 0, /* 14511 */ 's', 't', 'h', 'y', 9, 0, /* 14517 */ 'c', 'l', 'i', 'y', 9, 0, /* 14523 */ 'n', 'i', 'y', 9, 0, /* 14528 */ 'o', 'i', 'y', 9, 0, /* 14533 */ 'm', 'v', 'i', 'y', 9, 0, /* 14539 */ 'x', 'i', 'y', 9, 0, /* 14544 */ 'a', 'l', 'y', 9, 0, /* 14549 */ 'c', 'l', 'y', 9, 0, /* 14554 */ 's', 'l', 'y', 9, 0, /* 14559 */ 'l', 'a', 'm', 'y', 9, 0, /* 14565 */ 's', 't', 'a', 'm', 'y', 9, 0, /* 14572 */ 'i', 'c', 'm', 'y', 9, 0, /* 14578 */ 's', 't', 'c', 'm', 'y', 9, 0, /* 14585 */ 'c', 'l', 'm', 'y', 9, 0, /* 14591 */ 's', 't', 'm', 'y', 9, 0, /* 14597 */ 'n', 'y', 9, 0, /* 14601 */ 'o', 'y', 9, 0, /* 14605 */ 'c', 's', 'y', 9, 0, /* 14610 */ 'c', 'd', 's', 'y', 9, 0, /* 14616 */ 'm', 's', 'y', 9, 0, /* 14621 */ 's', 't', 'y', 9, 0, /* 14626 */ 'x', 'y', 9, 0, /* 14630 */ 'b', 'z', 9, 0, /* 14634 */ 'l', 'o', 'c', 'z', 9, 0, /* 14640 */ 's', 't', 'o', 'c', 'z', 9, 0, /* 14647 */ 'v', 'l', 'l', 'e', 'z', 9, 0, /* 14654 */ 'l', 'o', 'c', 'g', 'z', 9, 0, /* 14661 */ 's', 't', 'o', 'c', 'g', 'z', 9, 0, /* 14669 */ 'j', 'g', 'z', 9, 0, /* 14674 */ 'l', 'o', 'c', 'f', 'h', 'z', 9, 0, /* 14682 */ 's', 't', 'o', 'c', 'f', 'h', 'z', 9, 0, /* 14691 */ 'b', 'i', 'z', 9, 0, /* 14696 */ 'l', 'o', 'c', 'h', 'i', 'z', 9, 0, /* 14704 */ 'l', 'o', 'c', 'g', 'h', 'i', 'z', 9, 0, /* 14713 */ 'l', 'o', 'c', 'h', 'h', 'i', 'z', 9, 0, /* 14722 */ 'j', 'z', 9, 0, /* 14726 */ 'v', 'u', 'p', 'k', 'z', 9, 0, /* 14733 */ 'v', 'p', 'k', 'z', 9, 0, /* 14739 */ 'v', 'c', 'l', 'z', 9, 0, /* 14745 */ 'b', 'n', 'z', 9, 0, /* 14750 */ 'l', 'o', 'c', 'n', 'z', 9, 0, /* 14757 */ 's', 't', 'o', 'c', 'n', 'z', 9, 0, /* 14765 */ 'l', 'o', 'c', 'g', 'n', 'z', 9, 0, /* 14773 */ 's', 't', 'o', 'c', 'g', 'n', 'z', 9, 0, /* 14782 */ 'j', 'g', 'n', 'z', 9, 0, /* 14788 */ 'l', 'o', 'c', 'f', 'h', 'n', 'z', 9, 0, /* 14797 */ 's', 't', 'o', 'c', 'f', 'h', 'n', 'z', 9, 0, /* 14807 */ 'b', 'i', 'n', 'z', 9, 0, /* 14813 */ 'l', 'o', 'c', 'h', 'i', 'n', 'z', 9, 0, /* 14822 */ 'l', 'o', 'c', 'g', 'h', 'i', 'n', 'z', 9, 0, /* 14832 */ 'l', 'o', 'c', 'h', 'h', 'i', 'n', 'z', 9, 0, /* 14842 */ 'j', 'n', 'z', 9, 0, /* 14847 */ 'l', 'o', 'c', 'r', 'n', 'z', 9, 0, /* 14855 */ 'l', 'o', 'c', 'g', 'r', 'n', 'z', 9, 0, /* 14864 */ 'l', 'o', 'c', 'f', 'h', 'r', 'n', 'z', 9, 0, /* 14874 */ 'l', 'o', 'c', 'r', 'z', 9, 0, /* 14881 */ 'l', 'o', 'c', 'g', 'r', 'z', 9, 0, /* 14889 */ 'l', 'o', 'c', 'f', 'h', 'r', 'z', 9, 0, /* 14898 */ 'v', 'c', 't', 'z', 9, 0, /* 14904 */ 'm', 'v', 'z', 9, 0, /* 14909 */ '.', 'i', 'n', 's', 'n', 32, 'e', ',', 0, /* 14918 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'e', ',', 0, /* 14929 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 'e', ',', 0, /* 14940 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'e', ',', 0, /* 14951 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', 'e', ',', 0, /* 14962 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'e', ',', 0, /* 14973 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 'f', ',', 0, /* 14984 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', 'f', ',', 0, /* 14995 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'f', ',', 0, /* 15006 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', ',', 0, /* 15016 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', ',', 0, /* 15026 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'i', ',', 0, /* 15037 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'l', ',', 0, /* 15048 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', 'l', ',', 0, /* 15059 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', ',', 0, /* 15069 */ '.', 'i', 'n', 's', 'n', 32, 's', ',', 0, /* 15078 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 's', ',', 0, /* 15089 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', ',', 0, /* 15099 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'r', 's', ',', 0, /* 15110 */ '.', 'i', 'n', 's', 'n', 32, 's', 's', ',', 0, /* 15120 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'i', 'l', 'u', ',', 0, /* 15132 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', ',', 0, /* 15142 */ '.', 'i', 'n', 's', 'n', 32, 's', 'i', 'y', ',', 0, /* 15153 */ '.', 'i', 'n', 's', 'n', 32, 'r', 's', 'y', ',', 0, /* 15164 */ '.', 'i', 'n', 's', 'n', 32, 'r', 'x', 'y', ',', 0, /* 15175 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, /* 15206 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 15230 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 15255 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, /* 15278 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, /* 15301 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, /* 15323 */ 's', 'a', 'm', '3', '1', 0, /* 15329 */ 't', 'r', 'a', 'p', '2', 0, /* 15335 */ 's', 'a', 'm', '2', '4', 0, /* 15341 */ 's', 'a', 'm', '6', '4', 0, /* 15347 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 15360 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 15367 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 15377 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, /* 15387 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 15402 */ 'c', 'i', 'b', 0, /* 15406 */ 'c', 'g', 'i', 'b', 0, /* 15411 */ 'c', 'l', 'g', 'i', 'b', 0, /* 15417 */ 'c', 'l', 'i', 'b', 0, /* 15422 */ 'p', 'a', 'l', 'b', 0, /* 15427 */ 'p', 't', 'l', 'b', 0, /* 15432 */ 'c', 'r', 'b', 0, /* 15436 */ 'c', 'g', 'r', 'b', 0, /* 15441 */ 'c', 'l', 'g', 'r', 'b', 0, /* 15447 */ 'c', 'l', 'r', 'b', 0, /* 15452 */ 'p', 'c', 'c', 0, /* 15456 */ 'l', 'o', 'c', 0, /* 15460 */ 's', 't', 'o', 'c', 0, /* 15465 */ 't', 'e', 'n', 'd', 0, /* 15470 */ 'p', 't', 'f', 'f', 0, /* 15475 */ 's', 'c', 'k', 'p', 'f', 0, /* 15481 */ 'l', 'o', 'c', 'g', 0, /* 15486 */ 's', 't', 'o', 'c', 'g', 0, /* 15492 */ 'j', 'g', 0, /* 15495 */ 'c', 's', 'c', 'h', 0, /* 15500 */ 'h', 's', 'c', 'h', 0, /* 15505 */ 'r', 's', 'c', 'h', 0, /* 15510 */ 'x', 's', 'c', 'h', 0, /* 15515 */ 'l', 'o', 'c', 'f', 'h', 0, /* 15521 */ 's', 't', 'o', 'c', 'f', 'h', 0, /* 15528 */ 'b', 'i', 0, /* 15531 */ 'l', 'o', 'c', 'h', 'i', 0, /* 15537 */ 'l', 'o', 'c', 'g', 'h', 'i', 0, /* 15544 */ 'l', 'o', 'c', 'h', 'h', 'i', 0, /* 15551 */ 'c', 'i', 'j', 0, /* 15555 */ 'c', 'g', 'i', 'j', 0, /* 15560 */ 'c', 'l', 'g', 'i', 'j', 0, /* 15566 */ 'c', 'l', 'i', 'j', 0, /* 15571 */ 'c', 'r', 'j', 0, /* 15575 */ 'c', 'g', 'r', 'j', 0, /* 15580 */ 'c', 'l', 'g', 'r', 'j', 0, /* 15586 */ 'c', 'l', 'r', 'j', 0, /* 15591 */ 'i', 'p', 'k', 0, /* 15595 */ 's', 'a', 'l', 0, /* 15599 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 15613 */ 't', 'a', 'm', 0, /* 15617 */ 's', 'c', 'h', 'm', 0, /* 15622 */ 'p', 'c', 'k', 'm', 'o', 0, /* 15628 */ 'p', 'f', 'p', 'o', 0, /* 15633 */ 'r', 'c', 'h', 'p', 0, /* 15638 */ 'l', 'o', 'c', 'r', 0, /* 15643 */ 'l', 'o', 'c', 'g', 'r', 0, /* 15649 */ 'l', 'o', 'c', 'f', 'h', 'r', 0, /* 15656 */ 'p', 'r', 0, /* 15659 */ 'c', 'l', 'g', 't', 0, /* 15664 */ 'c', 'i', 't', 0, /* 15668 */ 'c', 'l', 'f', 'i', 't', 0, /* 15674 */ 'c', 'g', 'i', 't', 0, /* 15679 */ 'c', 'l', 'g', 'i', 't', 0, /* 15685 */ 'c', 'l', 't', 0, /* 15689 */ 'u', 'p', 't', 0, /* 15693 */ 'c', 'r', 't', 0, /* 15697 */ 'c', 'g', 'r', 't', 0, /* 15702 */ 'c', 'l', 'g', 'r', 't', 0, /* 15708 */ 'c', 'l', 'r', 't', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 15368U, // DBG_VALUE 15378U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 15361U, // BUNDLE 15388U, // LIFETIME_START 15348U, // LIFETIME_END 0U, // STACKMAP 15600U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 15256U, // PATCHABLE_FUNCTION_ENTER 15176U, // PATCHABLE_RET 15302U, // PATCHABLE_FUNCTION_EXIT 15279U, // PATCHABLE_TAIL_CALL 15231U, // PATCHABLE_EVENT_CALL 15207U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ADJDYNALLOC 0U, // AEXT128 0U, // AFIMux 0U, // AHIMux 0U, // AHIMuxK 0U, // ATOMIC_CMP_SWAPW 0U, // ATOMIC_LOADW_AFI 0U, // ATOMIC_LOADW_AR 0U, // ATOMIC_LOADW_MAX 0U, // ATOMIC_LOADW_MIN 0U, // ATOMIC_LOADW_NILH 0U, // ATOMIC_LOADW_NILHi 0U, // ATOMIC_LOADW_NR 0U, // ATOMIC_LOADW_NRi 0U, // ATOMIC_LOADW_OILH 0U, // ATOMIC_LOADW_OR 0U, // ATOMIC_LOADW_SR 0U, // ATOMIC_LOADW_UMAX 0U, // ATOMIC_LOADW_UMIN 0U, // ATOMIC_LOADW_XILF 0U, // ATOMIC_LOADW_XR 0U, // ATOMIC_LOAD_AFI 0U, // ATOMIC_LOAD_AGFI 0U, // ATOMIC_LOAD_AGHI 0U, // ATOMIC_LOAD_AGR 0U, // ATOMIC_LOAD_AHI 0U, // ATOMIC_LOAD_AR 0U, // ATOMIC_LOAD_MAX_32 0U, // ATOMIC_LOAD_MAX_64 0U, // ATOMIC_LOAD_MIN_32 0U, // ATOMIC_LOAD_MIN_64 0U, // ATOMIC_LOAD_NGR 0U, // ATOMIC_LOAD_NGRi 0U, // ATOMIC_LOAD_NIHF64 0U, // ATOMIC_LOAD_NIHF64i 0U, // ATOMIC_LOAD_NIHH64 0U, // ATOMIC_LOAD_NIHH64i 0U, // ATOMIC_LOAD_NIHL64 0U, // ATOMIC_LOAD_NIHL64i 0U, // ATOMIC_LOAD_NILF 0U, // ATOMIC_LOAD_NILF64 0U, // ATOMIC_LOAD_NILF64i 0U, // ATOMIC_LOAD_NILFi 0U, // ATOMIC_LOAD_NILH 0U, // ATOMIC_LOAD_NILH64 0U, // ATOMIC_LOAD_NILH64i 0U, // ATOMIC_LOAD_NILHi 0U, // ATOMIC_LOAD_NILL 0U, // ATOMIC_LOAD_NILL64 0U, // ATOMIC_LOAD_NILL64i 0U, // ATOMIC_LOAD_NILLi 0U, // ATOMIC_LOAD_NR 0U, // ATOMIC_LOAD_NRi 0U, // ATOMIC_LOAD_OGR 0U, // ATOMIC_LOAD_OIHF64 0U, // ATOMIC_LOAD_OIHH64 0U, // ATOMIC_LOAD_OIHL64 0U, // ATOMIC_LOAD_OILF 0U, // ATOMIC_LOAD_OILF64 0U, // ATOMIC_LOAD_OILH 0U, // ATOMIC_LOAD_OILH64 0U, // ATOMIC_LOAD_OILL 0U, // ATOMIC_LOAD_OILL64 0U, // ATOMIC_LOAD_OR 0U, // ATOMIC_LOAD_SGR 0U, // ATOMIC_LOAD_SR 0U, // ATOMIC_LOAD_UMAX_32 0U, // ATOMIC_LOAD_UMAX_64 0U, // ATOMIC_LOAD_UMIN_32 0U, // ATOMIC_LOAD_UMIN_64 0U, // ATOMIC_LOAD_XGR 0U, // ATOMIC_LOAD_XIHF64 0U, // ATOMIC_LOAD_XILF 0U, // ATOMIC_LOAD_XILF64 0U, // ATOMIC_LOAD_XR 0U, // ATOMIC_SWAPW 0U, // ATOMIC_SWAP_32 0U, // ATOMIC_SWAP_64 0U, // CFIMux 0U, // CGIBCall 0U, // CGIBReturn 0U, // CGRBCall 0U, // CGRBReturn 0U, // CHIMux 0U, // CIBCall 0U, // CIBReturn 0U, // CLCLoop 0U, // CLCSequence 0U, // CLFIMux 0U, // CLGIBCall 0U, // CLGIBReturn 0U, // CLGRBCall 0U, // CLGRBReturn 0U, // CLIBCall 0U, // CLIBReturn 0U, // CLMux 0U, // CLRBCall 0U, // CLRBReturn 0U, // CLSTLoop 0U, // CMux 0U, // CRBCall 0U, // CRBReturn 0U, // CallBASR 0U, // CallBCR 0U, // CallBR 0U, // CallBRASL 0U, // CallBRCL 0U, // CallJG 0U, // CondReturn 0U, // CondStore16 0U, // CondStore16Inv 0U, // CondStore16Mux 0U, // CondStore16MuxInv 0U, // CondStore32 0U, // CondStore32Inv 0U, // CondStore32Mux 0U, // CondStore32MuxInv 0U, // CondStore64 0U, // CondStore64Inv 0U, // CondStore8 0U, // CondStore8Inv 0U, // CondStore8Mux 0U, // CondStore8MuxInv 0U, // CondStoreF32 0U, // CondStoreF32Inv 0U, // CondStoreF64 0U, // CondStoreF64Inv 0U, // CondTrap 0U, // GOT 0U, // IIFMux 0U, // IIHF64 0U, // IIHH64 0U, // IIHL64 0U, // IIHMux 0U, // IILF64 0U, // IILH64 0U, // IILL64 0U, // IILMux 0U, // L128 0U, // LBMux 0U, // LEFR 0U, // LFER 0U, // LHIMux 0U, // LHMux 0U, // LLCMux 0U, // LLCRMux 0U, // LLHMux 0U, // LLHRMux 0U, // LMux 0U, // LOCHIMux 0U, // LOCMux 0U, // LOCRMux 0U, // LRMux 0U, // LTDBRCompare_VecPseudo 0U, // LTEBRCompare_VecPseudo 0U, // LTXBRCompare_VecPseudo 0U, // LX 0U, // MVCLoop 0U, // MVCSequence 0U, // MVSTLoop 0U, // MemBarrier 0U, // NCLoop 0U, // NCSequence 0U, // NIFMux 0U, // NIHF64 0U, // NIHH64 0U, // NIHL64 0U, // NIHMux 0U, // NILF64 0U, // NILH64 0U, // NILL64 0U, // NILMux 0U, // OCLoop 0U, // OCSequence 0U, // OIFMux 0U, // OIHF64 0U, // OIHH64 0U, // OIHL64 0U, // OIHMux 0U, // OILF64 0U, // OILH64 0U, // OILL64 0U, // OILMux 0U, // PAIR128 0U, // RISBHH 0U, // RISBHL 0U, // RISBLH 0U, // RISBLL 0U, // RISBMux 0U, // Return 0U, // SRSTLoop 0U, // ST128 0U, // STCMux 0U, // STHMux 0U, // STMux 0U, // STOCMux 0U, // STX 0U, // Select32 0U, // Select64 0U, // SelectF128 0U, // SelectF32 0U, // SelectF64 0U, // SelectVR128 0U, // SelectVR32 0U, // SelectVR64 0U, // Serialize 0U, // TBEGIN_nofloat 0U, // TLS_GDCALL 0U, // TLS_LDCALL 0U, // TMHH64 0U, // TMHL64 0U, // TMHMux 0U, // TMLH64 0U, // TMLL64 0U, // TMLMux 0U, // Trap 0U, // VL32 0U, // VL64 0U, // VLR32 0U, // VLR64 0U, // VLVGP32 0U, // VST32 0U, // VST64 0U, // XCLoop 0U, // XCSequence 0U, // XIFMux 0U, // XIHF64 0U, // XILF64 0U, // ZEXT128 16430U, // A 18800U, // AD 16883U, // ADB 16804865U, // ADBR 16805360U, // ADR 1107325271U, // ADTR 1107312942U, // ADTRA 18918U, // AE 17340U, // AEB 16804997U, // AEBR 16805497U, // AER 50356445U, // AFI 21882U, // AG 21267U, // AGF 50356455U, // AGFI 16805668U, // AGFR 22882U, // AGH 67133752U, // AGHI 1107321434U, // AGHIK 16805750U, // AGR 1107321492U, // AGRK 83927453U, // AGSI 22627U, // AH 1107324947U, // AHHHR 1107325082U, // AHHLR 67133740U, // AHI 1107321428U, // AHIK 30871U, // AHY 50354711U, // AIH 25333U, // AL 18663U, // ALC 22006U, // ALCG 16805762U, // ALCGR 16805341U, // ALCR 100688143U, // ALFI 22190U, // ALG 21284U, // ALGF 100688115U, // ALGFI 16805681U, // ALGFR 1107321441U, // ALGHSIK 16805794U, // ALGR 1107321498U, // ALGRK 83927459U, // ALGSI 1107324954U, // ALHHHR 1107325089U, // ALHHLR 1107321450U, // ALHSIK 16806010U, // ALR 1107321542U, // ALRK 83927510U, // ALSI 50354776U, // ALSIH 50358418U, // ALSIHN 30929U, // ALY 117500432U, // AP 16804837U, // AR 1107321487U, // ARK 83927448U, // ASI 30614U, // AU 16806613U, // AUR 30705U, // AW 16806629U, // AWR 16805219U, // AXBR 16806639U, // AXR 1107325529U, // AXTR 1107312994U, // AXTRA 30800U, // AY 65971U, // B 33583219U, // BAKR 134243065U, // BAL 33583225U, // BALR 134247259U, // BAS 33583387U, // BASR 33581165U, // BASSM 68087U, // BAsmE 71804U, // BAsmH 68217U, // BAsmHE 74502U, // BAsmL 69053U, // BAsmLE 72358U, // BAsmLH 75526U, // BAsmM 69792U, // BAsmNE 73228U, // BAsmNH 68461U, // BAsmNHE 74853U, // BAsmNL 69300U, // BAsmNLE 72653U, // BAsmNLH 75675U, // BAsmNM 76101U, // BAsmNO 76473U, // BAsmNP 80282U, // BAsmNZ 75984U, // BAsmO 76318U, // BAsmP 80167U, // BAsmZ 621613U, // BC 1149082U, // BCAsm 1670189U, // BCR 153202129U, // BCRAsm 30326U, // BCT 22475U, // BCTG 16805855U, // BCTGR 16806189U, // BCTR 73919U, // BI 68933U, // BIAsmE 72223U, // BIAsmH 68360U, // BIAsmHE 74698U, // BIAsmL 69193U, // BIAsmLE 72499U, // BIAsmLH 75619U, // BIAsmM 69918U, // BIAsmNE 73347U, // BIAsmNH 68595U, // BIAsmNHE 74972U, // BIAsmNL 69434U, // BIAsmNLE 72787U, // BIAsmNLH 75737U, // BIAsmNM 76163U, // BIAsmNO 76535U, // BIAsmNP 80344U, // BIAsmNZ 76038U, // BIAsmO 76422U, // BIAsmP 80228U, // BIAsmZ 621737U, // BIC 1149126U, // BICAsm 2317986625U, // BPP 3391728483U, // BPRP 3173379U, // BR 184578918U, // BRAS 184575582U, // BRASL 3174014U, // BRAsmE 3174393U, // BRAsmH 3174062U, // BRAsmHE 3174527U, // BRAsmL 3174081U, // BRAsmLE 3174456U, // BRAsmLH 3174640U, // BRAsmM 3174099U, // BRAsmNE 3174475U, // BRAsmNH 3174068U, // BRAsmNHE 3174596U, // BRAsmNL 3174087U, // BRAsmNLE 3174468U, // BRAsmNLH 3174645U, // BRAsmNM 3174661U, // BRAsmNO 3174677U, // BRAsmNP 3175253U, // BRAsmNZ 3174656U, // BRAsmO 3174667U, // BRAsmP 3175248U, // BRAsmZ 201948354U, // BRC 153717047U, // BRCAsm 201948293U, // BRCL 153723733U, // BRCLAsm 201356931U, // BRCT 201349088U, // BRCTG 201351128U, // BRCTH 1090543724U, // BRXH 1090541188U, // BRXHG 1090539666U, // BRXLE 1090541341U, // BRXLG 33571219U, // BSA 33576858U, // BSG 33581139U, // BSM 1090543713U, // BXH 1090541182U, // BXHG 1090539660U, // BXLE 1090541109U, // BXLEG 134236295U, // C 134236532U, // CD 134234659U, // CDB 33582088U, // CDBR 33582339U, // CDFBR 218120388U, // CDFBRA 33582858U, // CDFR 218132967U, // CDFTR 33582384U, // CDGBR 218120412U, // CDGBRA 33582992U, // CDGR 33583621U, // CDGTR 218120530U, // CDGTRA 218131729U, // CDLFBR 218132974U, // CDLFTR 218131774U, // CDLGBR 218133004U, // CDLGTR 234911491U, // CDPT 33582588U, // CDR 1090548978U, // CDS 1090541476U, // CDSG 33583669U, // CDSTR 1090550035U, // CDSY 33583453U, // CDTR 33583690U, // CDUTR 234911626U, // CDZT 134236726U, // CE 134235081U, // CEB 33582220U, // CEBR 33583465U, // CEDTR 33582346U, // CEFBR 218120396U, // CEFBRA 33582878U, // CEFR 33582391U, // CEGBR 218120420U, // CEGBRA 33583004U, // CEGR 218131737U, // CELFBR 218131782U, // CELGBR 33582724U, // CER 33583724U, // CEXTR 3180720U, // CFC 218131483U, // CFDBR 218120340U, // CFDBRA 218131987U, // CFDR 218132869U, // CFDTR 218131623U, // CFEBR 218120364U, // CFEBRA 218132130U, // CFER 251683042U, // CFI 218131838U, // CFXBR 218120452U, // CFXBRA 218133254U, // CFXR 218133121U, // CFXTR 134239717U, // CG 218131498U, // CGDBR 218120348U, // CGDBRA 218131993U, // CGDR 218132884U, // CGDTR 218120508U, // CGDTRA 218131638U, // CGEBR 218120372U, // CGEBRA 218132136U, // CGER 134239000U, // CGF 251683053U, // CGFI 33582891U, // CGFR 268461514U, // CGFRL 134240617U, // CGH 285237568U, // CGHI 268461574U, // CGHRL 67150264U, // CGHSI 305789999U, // CGIB 1392526511U, // CGIBAsm 2466269691U, // CGIBAsmE 2466273408U, // CGIBAsmH 2466269822U, // CGIBAsmHE 2466276106U, // CGIBAsmL 2466270658U, // CGIBAsmLE 2466273963U, // CGIBAsmLH 2466271397U, // CGIBAsmNE 2466274833U, // CGIBAsmNH 2466270067U, // CGIBAsmNHE 2466276458U, // CGIBAsmNL 2466270906U, // CGIBAsmNLE 2466274259U, // CGIBAsmNLH 339344580U, // CGIJ 1392534010U, // CGIJAsm 3540012399U, // CGIJAsmE 3540015717U, // CGIJAsmH 3540011826U, // CGIJAsmHE 3540018159U, // CGIJAsmL 3540012659U, // CGIJAsmLE 3540015990U, // CGIJAsmLH 3540013384U, // CGIJAsmNE 3540016813U, // CGIJAsmNH 3540012066U, // CGIJAsmNHE 3540018438U, // CGIJAsmNL 3540012905U, // CGIJAsmNLE 3540016258U, // CGIJAsmNLH 4324667U, // CGIT 1358984917U, // CGITAsm 285233731U, // CGITAsmE 285237236U, // CGITAsmH 285232397U, // CGITAsmHE 285238957U, // CGITAsmL 285233236U, // CGITAsmLE 285236625U, // CGITAsmLH 285233594U, // CGITAsmNE 285237023U, // CGITAsmNH 285232283U, // CGITAsmNHE 285238648U, // CGITAsmNL 285233122U, // CGITAsmNLE 285236482U, // CGITAsmNLH 33582980U, // CGR 3391224909U, // CGRB 1107314075U, // CGRBAsm 1107315223U, // CGRBAsmE 1107318945U, // CGRBAsmH 1107315358U, // CGRBAsmHE 1107321638U, // CGRBAsmL 1107316194U, // CGRBAsmLE 1107319499U, // CGRBAsmLH 1107316933U, // CGRBAsmNE 1107320369U, // CGRBAsmNH 1107315607U, // CGRBAsmNHE 1107321994U, // CGRBAsmNL 1107316446U, // CGRBAsmNLE 1107319799U, // CGRBAsmNLH 169999576U, // CGRJ 1107321362U, // CGRJAsm 1107316107U, // CGRJAsmE 1107319425U, // CGRJAsmH 1107315538U, // CGRJAsmHE 1107321867U, // CGRJAsmL 1107316371U, // CGRJAsmLE 1107319702U, // CGRJAsmLH 1107317096U, // CGRJAsmNE 1107320525U, // CGRJAsmNH 1107315782U, // CGRJAsmNHE 1107322150U, // CGRJAsmNL 1107316621U, // CGRJAsmNLE 1107319974U, // CGRJAsmNLH 268461539U, // CGRL 153222482U, // CGRT 1107326751U, // CGRTAsm 33575524U, // CGRTAsmE 33579023U, // CGRTAsmH 33574188U, // CGRTAsmHE 33580744U, // CGRTAsmL 33575027U, // CGRTAsmLE 33578416U, // CGRTAsmLH 33575385U, // CGRTAsmNE 33578814U, // CGRTAsmNH 33574078U, // CGRTAsmNHE 33580439U, // CGRTAsmNL 33574917U, // CGRTAsmNLE 33578277U, // CGRTAsmNLH 218131853U, // CGXBR 218120460U, // CGXBRA 218133260U, // CGXR 218133136U, // CGXTR 218120560U, // CGXTRA 134240442U, // CH 134239092U, // CHF 33583117U, // CHHR 67150279U, // CHHSI 285237555U, // CHI 33583252U, // CHLR 268461559U, // CHRL 67150250U, // CHSI 134248604U, // CHY 305789995U, // CIB 1392526499U, // CIBAsm 2466269685U, // CIBAsmE 2466273402U, // CIBAsmH 2466269815U, // CIBAsmHE 2466276100U, // CIBAsmL 2466270651U, // CIBAsmLE 2466273956U, // CIBAsmLH 2466271390U, // CIBAsmNE 2466274826U, // CIBAsmNH 2466270059U, // CIBAsmNHE 2466276451U, // CIBAsmNL 2466270898U, // CIBAsmNLE 2466274251U, // CIBAsmNLH 251681316U, // CIH 339344576U, // CIJ 1392534005U, // CIJAsm 3540012393U, // CIJAsmE 3540015711U, // CIJAsmH 3540011819U, // CIJAsmHE 3540018153U, // CIJAsmL 3540012652U, // CIJAsmLE 3540015983U, // CIJAsmLH 3540013377U, // CIJAsmNE 3540016806U, // CIJAsmNH 3540012058U, // CIJAsmNHE 3540018431U, // CIJAsmNL 3540012897U, // CIJAsmNLE 3540016250U, // CIJAsmNLH 4324657U, // CIT 1358984905U, // CITAsm 285233717U, // CITAsmE 285237222U, // CITAsmH 285232381U, // CITAsmHE 285238943U, // CITAsmL 285233220U, // CITAsmLE 285236609U, // CITAsmLH 285233578U, // CITAsmNE 285237007U, // CITAsmNH 285232265U, // CITAsmNHE 285238632U, // CITAsmNL 285233104U, // CITAsmNLE 285236464U, // CITAsmNLH 33581145U, // CKSM 134243134U, // CL 302041324U, // CLC 33579842U, // CLCL 1107316219U, // CLCLE 1107326888U, // CLCLU 218131490U, // CLFDBR 218132876U, // CLFDTR 218131630U, // CLFEBR 352362928U, // CLFHSI 369123605U, // CLFI 4848949U, // CLFIT 1459648206U, // CLFITAsm 385897019U, // CLFITAsmE 385900524U, // CLFITAsmH 385895684U, // CLFITAsmHE 385902245U, // CLFITAsmL 385896523U, // CLFITAsmLE 385899912U, // CLFITAsmLH 385896881U, // CLFITAsmNE 385900310U, // CLFITAsmNH 385895569U, // CLFITAsmNHE 385901935U, // CLFITAsmNL 385896408U, // CLFITAsmNLE 385899768U, // CLFITAsmNLH 218131845U, // CLFXBR 218133128U, // CLFXTR 134239933U, // CLG 218131505U, // CLGDBR 218132891U, // CLGDTR 218131645U, // CLGEBR 134239018U, // CLGF 369123578U, // CLGFI 33582904U, // CLGFR 268461521U, // CLGFRL 268461581U, // CLGHRL 352362943U, // CLGHSI 307362868U, // CLGIB 1476412597U, // CLGIBAsm 2550155778U, // CLGIBAsmE 2550159495U, // CLGIBAsmH 2550155910U, // CLGIBAsmHE 2550162193U, // CLGIBAsmL 2550156746U, // CLGIBAsmLE 2550160051U, // CLGIBAsmLH 2550157485U, // CLGIBAsmNE 2550160921U, // CLGIBAsmNH 2550156156U, // CLGIBAsmNHE 2550162546U, // CLGIBAsmNL 2550156995U, // CLGIBAsmNLE 2550160348U, // CLGIBAsmNLH 340917449U, // CLGIJ 1476420096U, // CLGIJAsm 3623898486U, // CLGIJAsmE 3623901804U, // CLGIJAsmH 3623897914U, // CLGIJAsmHE 3623904246U, // CLGIJAsmL 3623898747U, // CLGIJAsmLE 3623902078U, // CLGIJAsmLH 3623899472U, // CLGIJAsmNE 3623902901U, // CLGIJAsmNH 3623898155U, // CLGIJAsmNHE 3623904526U, // CLGIJAsmNL 3623898994U, // CLGIJAsmNLE 3623902347U, // CLGIJAsmNLH 4848960U, // CLGIT 1459648219U, // CLGITAsm 385897034U, // CLGITAsmE 385900539U, // CLGITAsmH 385895701U, // CLGITAsmHE 385902260U, // CLGITAsmL 385896540U, // CLGITAsmLE 385899929U, // CLGITAsmLH 385896898U, // CLGITAsmNE 385900327U, // CLGITAsmNH 385895588U, // CLGITAsmNHE 385901952U, // CLGITAsmNL 385896427U, // CLGITAsmNLE 385899787U, // CLGITAsmNLH 33583016U, // CLGR 3391224914U, // CLGRB 1107314081U, // CLGRBAsm 1107315230U, // CLGRBAsmE 1107318952U, // CLGRBAsmH 1107315366U, // CLGRBAsmHE 1107321645U, // CLGRBAsmL 1107316202U, // CLGRBAsmLE 1107319507U, // CLGRBAsmLH 1107316941U, // CLGRBAsmNE 1107320377U, // CLGRBAsmNH 1107315616U, // CLGRBAsmNHE 1107322002U, // CLGRBAsmNL 1107316455U, // CLGRBAsmNLE 1107319808U, // CLGRBAsmNLH 169999581U, // CLGRJ 1107321368U, // CLGRJAsm 1107316114U, // CLGRJAsmE 1107319432U, // CLGRJAsmH 1107315546U, // CLGRJAsmHE 1107321874U, // CLGRJAsmL 1107316379U, // CLGRJAsmLE 1107319710U, // CLGRJAsmLH 1107317104U, // CLGRJAsmNE 1107320533U, // CLGRJAsmNH 1107315791U, // CLGRJAsmNHE 1107322158U, // CLGRJAsmNL 1107316630U, // CLGRJAsmNLE 1107319983U, // CLGRJAsmNLH 268461545U, // CLGRL 153222487U, // CLGRT 1107326757U, // CLGRTAsm 33575531U, // CLGRTAsmE 33579030U, // CLGRTAsmH 33574196U, // CLGRTAsmHE 33580751U, // CLGRTAsmL 33575035U, // CLGRTAsmLE 33578424U, // CLGRTAsmLH 33575393U, // CLGRTAsmNE 33578822U, // CLGRTAsmNH 33574087U, // CLGRTAsmNHE 33580447U, // CLGRTAsmNL 33574926U, // CLGRTAsmNLE 33578286U, // CLGRTAsmNLH 146732U, // CLGT 1493202621U, // CLGTAsm 436228654U, // CLGTAsmE 436232159U, // CLGTAsmH 436227317U, // CLGTAsmHE 436233880U, // CLGTAsmL 436228156U, // CLGTAsmLE 436231545U, // CLGTAsmLH 436228514U, // CLGTAsmNE 436231943U, // CLGTAsmNH 436227200U, // CLGTAsmNHE 436233568U, // CLGTAsmNL 436228039U, // CLGTAsmNLE 436231399U, // CLGTAsmNLH 218131860U, // CLGXBR 218133143U, // CLGXTR 134239136U, // CLHF 33583153U, // CLHHR 352362958U, // CLHHSI 33583288U, // CLHLR 268461597U, // CLHRL 453026168U, // CLI 307362874U, // CLIB 1476412604U, // CLIBAsm 2550155786U, // CLIBAsmE 2550159503U, // CLIBAsmH 2550155919U, // CLIBAsmHE 2550162201U, // CLIBAsmL 2550156755U, // CLIBAsmLE 2550160060U, // CLIBAsmLH 2550157494U, // CLIBAsmNE 2550160930U, // CLIBAsmNH 2550156166U, // CLIBAsmNHE 2550162555U, // CLIBAsmNL 2550157005U, // CLIBAsmNLE 2550160358U, // CLIBAsmNLH 369121866U, // CLIH 340917455U, // CLIJ 1476420103U, // CLIJAsm 3623898494U, // CLIJAsmE 3623901812U, // CLIJAsmH 3623897923U, // CLIJAsmHE 3623904254U, // CLIJAsmL 3623898756U, // CLIJAsmLE 3623902087U, // CLIJAsmLH 3623899481U, // CLIJAsmNE 3623902910U, // CLIJAsmNH 3623898165U, // CLIJAsmNHE 3623904535U, // CLIJAsmNL 3623899004U, // CLIJAsmNLE 3623902357U, // CLIJAsmNLH 453032118U, // CLIY 2365613969U, // CLM 2365611506U, // CLMH 2365618426U, // CLMY 33583236U, // CLR 3391224920U, // CLRB 1107314088U, // CLRBAsm 1107315238U, // CLRBAsmE 1107318960U, // CLRBAsmH 1107315375U, // CLRBAsmHE 1107321653U, // CLRBAsmL 1107316211U, // CLRBAsmLE 1107319516U, // CLRBAsmLH 1107316950U, // CLRBAsmNE 1107320386U, // CLRBAsmNH 1107315626U, // CLRBAsmNHE 1107322011U, // CLRBAsmNL 1107316465U, // CLRBAsmNLE 1107319818U, // CLRBAsmNLH 169999587U, // CLRJ 1107321375U, // CLRJAsm 1107316122U, // CLRJAsmE 1107319440U, // CLRJAsmH 1107315555U, // CLRJAsmHE 1107321882U, // CLRJAsmL 1107316388U, // CLRJAsmLE 1107319719U, // CLRJAsmLH 1107317113U, // CLRJAsmNE 1107320542U, // CLRJAsmNH 1107315801U, // CLRJAsmNHE 1107322167U, // CLRJAsmNL 1107316640U, // CLRJAsmNLE 1107319993U, // CLRJAsmNLH 268461618U, // CLRL 153222493U, // CLRT 1107326764U, // CLRTAsm 33575539U, // CLRTAsmE 33579038U, // CLRTAsmH 33574205U, // CLRTAsmHE 33580759U, // CLRTAsmL 33575044U, // CLRTAsmLE 33578433U, // CLRTAsmLH 33575402U, // CLRTAsmNE 33578831U, // CLRTAsmNH 33574097U, // CLRTAsmNHE 33580456U, // CLRTAsmNL 33574936U, // CLRTAsmNLE 33578296U, // CLRTAsmNLH 33584959U, // CLST 146758U, // CLT 1493202658U, // CLTAsm 436228690U, // CLTAsmE 436232195U, // CLTAsmH 436227358U, // CLTAsmHE 436233916U, // CLTAsmL 436228197U, // CLTAsmLE 436231586U, // CLTAsmLH 436228555U, // CLTAsmNE 436231984U, // CLTAsmNH 436227246U, // CLTAsmNHE 436233609U, // CLTAsmNL 436228085U, // CLTAsmNLE 436231445U, // CLTAsmNLH 134248662U, // CLY 33573205U, // CMPSC 117500452U, // CP 234911389U, // CPDT 1090547289U, // CPSDRdd 1090547289U, // CPSDRds 1090547289U, // CPSDRsd 1090547289U, // CPSDRss 234911608U, // CPXT 33571240U, // CPYA 33582546U, // CR 3391224905U, // CRB 1107314070U, // CRBAsm 1107315217U, // CRBAsmE 1107318939U, // CRBAsmH 1107315351U, // CRBAsmHE 1107321632U, // CRBAsmL 1107316187U, // CRBAsmLE 1107319492U, // CRBAsmLH 1107316926U, // CRBAsmNE 1107320362U, // CRBAsmNH 1107315599U, // CRBAsmNHE 1107321987U, // CRBAsmNL 1107316438U, // CRBAsmNLE 1107319791U, // CRBAsmNLH 1090540071U, // CRDTE 1090540071U, // CRDTEOpt 169999572U, // CRJ 1107321357U, // CRJAsm 1107316101U, // CRJAsmE 1107319419U, // CRJAsmH 1107315531U, // CRJAsmHE 1107321861U, // CRJAsmL 1107316364U, // CRJAsmLE 1107319695U, // CRJAsmLH 1107317089U, // CRJAsmNE 1107320518U, // CRJAsmNH 1107315774U, // CRJAsmNHE 1107322143U, // CRJAsmNL 1107316613U, // CRJAsmNLE 1107319966U, // CRJAsmNLH 268461502U, // CRL 153222478U, // CRT 1107326746U, // CRTAsm 33575518U, // CRTAsmE 33579017U, // CRTAsmH 33574181U, // CRTAsmHE 33580738U, // CRTAsmL 33575020U, // CRTAsmLE 33578409U, // CRTAsmLH 33575378U, // CRTAsmNE 33578807U, // CRTAsmNH 33574070U, // CRTAsmNHE 33580432U, // CRTAsmNL 33574909U, // CRTAsmNLE 33578269U, // CRTAsmNLH 1090548974U, // CS 15496U, // CSCH 1107325373U, // CSDTR 1090541471U, // CSG 16804730U, // CSP 16799602U, // CSPG 1543550795U, // CSST 1107325625U, // CSXTR 1090550030U, // CSY 1107312653U, // CU12 33570829U, // CU12Opt 1107312665U, // CU14 33570841U, // CU14Opt 1107312641U, // CU21 33570817U, // CU21Opt 1107312671U, // CU24 33570847U, // CU24Opt 33570823U, // CU41 33570835U, // CU42 33583570U, // CUDTR 33575451U, // CUSE 1107326874U, // CUTFU 33585050U, // CUTFUOpt 1107318025U, // CUUTF 33576201U, // CUUTFOpt 33583822U, // CUXTR 18258U, // CVB 21980U, // CVBG 30815U, // CVBY 134236629U, // CVD 134239772U, // CVDG 134248571U, // CVDY 33582442U, // CXBR 33582377U, // CXFBR 218120404U, // CXFBRA 33582960U, // CXFR 218132990U, // CXFTR 33582422U, // CXGBR 218120428U, // CXGBRA 33583091U, // CXGR 33583651U, // CXGTR 218120538U, // CXGTRA 218131745U, // CXLFBR 218132982U, // CXLFTR 218131790U, // CXLGBR 218133019U, // CXLGTR 234911508U, // CXPT 33583861U, // CXR 33583683U, // CXSTR 33583711U, // CXTR 33583697U, // CXUTR 234911632U, // CXZT 134248550U, // CY 234911401U, // CZDT 234911620U, // CZXT 18801U, // D 18808U, // DD 16960U, // DDB 16804878U, // DDBR 16805377U, // DDR 1107325283U, // DDTR 1107312949U, // DDTRA 19023U, // DE 17360U, // DEB 16805011U, // DEBR 16805515U, // DER 1107318148U, // DIAG 1107323961U, // DIDBR 1107324101U, // DIEBR 25443U, // DL 22212U, // DLG 16805806U, // DLGR 16806025U, // DLR 117500472U, // DP 16805361U, // DR 22437U, // DSG 21324U, // DSGF 16805723U, // DSGFR 16805843U, // DSGR 16805233U, // DXBR 16806651U, // DXR 1107325542U, // DXTR 1107313001U, // DXTRA 33582052U, // EAR 1107318142U, // ECAG 33583411U, // ECCTR 33570901U, // ECPGA 1543542737U, // ECTG 302041470U, // ED 302047870U, // EDMK 33583472U, // EEDTR 33583731U, // EEXTR 3164446U, // EFPC 3174494U, // EPAIR 3173353U, // EPAR 33583432U, // EPCTR 33585171U, // EPSW 33576508U, // EREG 33576527U, // EREGG 3174501U, // ESAIR 3173359U, // ESAR 33583556U, // ESDTR 3162173U, // ESEA 33571224U, // ESTA 33583808U, // ESXTR 3164588U, // ETND 134248491U, // EX 268461656U, // EXRL 218131520U, // FIDBR 218120356U, // FIDBRA 33582635U, // FIDR 218132899U, // FIDTR 218131660U, // FIEBR 218120380U, // FIEBRA 33582779U, // FIER 218131868U, // FIXBR 218120468U, // FIXBRA 33583890U, // FIXR 218133151U, // FIXTR 33583046U, // FLOGR 33582630U, // HDR 33582767U, // HER 15501U, // HSCH 3164293U, // IAC 18631U, // IC 18631U, // IC32 30821U, // IC32Y 486565654U, // ICM 486563280U, // ICMH 486570221U, // ICMY 30821U, // ICY 1090540065U, // IDTE 1090540065U, // IDTEOpt 1090548087U, // IEDTR 1090548346U, // IEXTR 369120121U, // IIHF 352344513U, // IIHH 352347051U, // IIHL 369120266U, // IILF 352344918U, // IILH 352347175U, // IILL 15592U, // IPK 3172386U, // IPM 1107317336U, // IPTE 1107317336U, // IPTEOpt 33575512U, // IPTEOptOpt 33580810U, // IRBM 16797096U, // ISKE 16802541U, // IVSK 3308094U, // InsnE 1579334303U, // InsnRI 505608775U, // InsnRIE 3726834366U, // InsnRIL 2653092625U, // InsnRILU 3726834407U, // InsnRIS 5929684U, // InsnRR 505592402U, // InsnRRE 505592446U, // InsnRRF 505608956U, // InsnRRS 505592562U, // InsnRS 505608797U, // InsnRSE 505608883U, // InsnRSI 505609010U, // InsnRSY 2653076253U, // InsnRX 2653092467U, // InsnRXE 505608852U, // InsnRXF 2653092669U, // InsnRXY 157465310U, // InsnS 509786793U, // InsnSI 1583545033U, // InsnSIL 2657286951U, // InsnSIY 7011079U, // InsnSS 3731028584U, // InsnSSE 3731028617U, // InsnSSF 205303U, // J 200043U, // JAsmE 203361U, // JAsmH 199469U, // JAsmHE 205803U, // JAsmL 200302U, // JAsmLE 203633U, // JAsmLH 206729U, // JAsmM 201027U, // JAsmNE 204456U, // JAsmNH 199708U, // JAsmNHE 206081U, // JAsmNL 200547U, // JAsmNLE 203900U, // JAsmNLH 206844U, // JAsmNM 207270U, // JAsmNO 207642U, // JAsmNP 211451U, // JAsmNZ 207141U, // JAsmO 207531U, // JAsmP 211331U, // JAsmZ 202402U, // JG 199282U, // JGAsmE 203133U, // JGAsmH 199407U, // JGAsmHE 205704U, // JGAsmL 200240U, // JGAsmLE 203531U, // JGAsmLH 206664U, // JGAsmM 200965U, // JGAsmNE 204394U, // JGAsmNH 199639U, // JGAsmNHE 206019U, // JGAsmNL 200478U, // JGAsmNLE 203831U, // JGAsmNLH 206784U, // JGAsmNM 207210U, // JGAsmNO 207582U, // JGAsmNP 211391U, // JGAsmNZ 207088U, // JGAsmO 207465U, // JGAsmP 211278U, // JGAsmZ 134234878U, // KDB 33582151U, // KDBR 33583530U, // KDTR 134235119U, // KEB 33582291U, // KEBR 3361184U, // KIMD 3361190U, // KLMD 33580941U, // KM 1090535547U, // KMA 3360906U, // KMAC 33573115U, // KMC 1090548033U, // KMCTR 33576078U, // KMF 33581371U, // KMO 33582499U, // KXBR 33583782U, // KXTR 134243062U, // L 134234218U, // LA 1107312684U, // LAA 1107318136U, // LAAG 1107321587U, // LAAL 1107318444U, // LAALG 134236650U, // LAE 134248577U, // LAEY 1107322617U, // LAM 1107327200U, // LAMY 1107323013U, // LAN 1107318603U, // LANG 1107323077U, // LAO 1107318615U, // LAOG 268461494U, // LARL 469805940U, // LASP 134248041U, // LAT 1107327007U, // LAX 1107318845U, // LAXG 134248527U, // LAY 134235341U, // LB 134240406U, // LBH 33582430U, // LBR 1207976394U, // LCBB 3188342U, // LCCTL 33582087U, // LCDBR 33582857U, // LCDFR 33582857U, // LCDFR_32 33582587U, // LCDR 33582219U, // LCEBR 33582723U, // LCER 33582890U, // LCGFR 33582979U, // LCGR 33582558U, // LCR 1107322493U, // LCTL 1107318543U, // LCTLG 33582441U, // LCXBR 33583860U, // LCXR 134236572U, // LD 134236750U, // LDE 134236750U, // LDE32 134235087U, // LDEB 33582226U, // LDEBR 33582736U, // LDER 1107325408U, // LDETR 33582998U, // LDGR 33582641U, // LDR 33582641U, // LDR32 33582448U, // LDXBR 218120436U, // LDXBRA 33583866U, // LDXR 218133093U, // LDXTR 134248560U, // LDY 134237623U, // LE 33582100U, // LEDBR 218120332U, // LEDBRA 33582605U, // LEDR 218132862U, // LEDTR 33582786U, // LER 33582455U, // LEXBR 218120444U, // LEXBRA 33583872U, // LEXR 134248583U, // LEY 3191648U, // LFAS 134240599U, // LFH 134248034U, // LFHAT 3180836U, // LFPC 134239919U, // LG 134248028U, // LGAT 134235208U, // LGB 33582400U, // LGBR 33582623U, // LGDR 134239013U, // LGF 251683060U, // LGFI 33582898U, // LGFR 268461522U, // LGFRL 134239830U, // LGG 134240643U, // LGH 285237574U, // LGHI 33583111U, // LGHR 268461582U, // LGHRL 33583011U, // LGR 268461546U, // LGRL 134236483U, // LGSC 134240928U, // LH 134240733U, // LHH 285237608U, // LHI 33583161U, // LHR 268461598U, // LHRL 134248609U, // LHY 134236401U, // LLC 134240458U, // LLCH 33582563U, // LLCR 134236346U, // LLGC 33582550U, // LLGCR 134239024U, // LLGF 134248020U, // LLGFAT 33582911U, // LLGFR 268461529U, // LLGFRL 134240170U, // LLGFSG 134240642U, // LLGH 33583110U, // LLGHR 268461589U, // LLGHRL 134248131U, // LLGT 134248046U, // LLGTAT 33583636U, // LLGTR 134241202U, // LLH 134240738U, // LLHH 33583166U, // LLHR 268461604U, // LLHRL 369120127U, // LLIHF 385898951U, // LLIHH 385901489U, // LLIHL 369120272U, // LLILF 385899356U, // LLILH 385901613U, // LLILL 134239044U, // LLZRGF 1107322770U, // LM 1107315111U, // LMD 1107318585U, // LMG 1107320307U, // LMH 1107327227U, // LMY 33582163U, // LNDBR 33582864U, // LNDFR 33582864U, // LNDFR_32 33582651U, // LNDR 33582297U, // LNEBR 33582809U, // LNER 33582925U, // LNGFR 33583040U, // LNGR 33583355U, // LNR 33582511U, // LNXBR 33583906U, // LNXR 244833U, // LOC 1543522574U, // LOCAsm 469781056U, // LOCAsmE 469784790U, // LOCAsmH 469781182U, // LOCAsmHE 469787464U, // LOCAsmL 469782018U, // LOCAsmLE 469785323U, // LOCAsmLH 469788443U, // LOCAsmM 469782750U, // LOCAsmNE 469786186U, // LOCAsmNH 469781427U, // LOCAsmNHE 469787811U, // LOCAsmNL 469782266U, // LOCAsmNLE 469785619U, // LOCAsmNLH 469788576U, // LOCAsmNM 469789002U, // LOCAsmNO 469789374U, // LOCAsmNP 469793183U, // LOCAsmNZ 469788884U, // LOCAsmO 469789218U, // LOCAsmP 469793067U, // LOCAsmZ 244892U, // LOCFH 1543526728U, // LOCFHAsm 469781197U, // LOCFHAsmE 469785008U, // LOCFHAsmH 469781237U, // LOCFHAsmHE 469787546U, // LOCFHAsmL 469782070U, // LOCFHAsmLE 469785376U, // LOCFHAsmLH 469788498U, // LOCFHAsmM 469782795U, // LOCFHAsmNE 469786224U, // LOCFHAsmNH 469781470U, // LOCFHAsmNHE 469787849U, // LOCFHAsmNL 469782309U, // LOCFHAsmNLE 469785662U, // LOCFHAsmNLH 469788614U, // LOCFHAsmNM 469789040U, // LOCFHAsmNO 469789412U, // LOCFHAsmNP 469793221U, // LOCFHAsmNZ 469788917U, // LOCFHAsmO 469789301U, // LOCFHAsmP 469793107U, // LOCFHAsmZ 7601442U, // LOCFHR 1090547710U, // LOCFHRAsm 16798214U, // LOCFHRAsmE 16801700U, // LOCFHRAsmH 16796907U, // LOCFHRAsmHE 16803325U, // LOCFHRAsmL 16797746U, // LOCFHRAsmLE 16801113U, // LOCFHRAsmLH 16803914U, // LOCFHRAsmM 16798104U, // LOCFHRAsmNE 16801533U, // LOCFHRAsmNH 16796789U, // LOCFHRAsmNHE 16803158U, // LOCFHRAsmNL 16797628U, // LOCFHRAsmNLE 16800988U, // LOCFHRAsmNLH 16803858U, // LOCFHRAsmNM 16804290U, // LOCFHRAsmNO 16804656U, // LOCFHRAsmNP 16808465U, // LOCFHRAsmNZ 16804339U, // LOCFHRAsmO 16804698U, // LOCFHRAsmP 16808490U, // LOCFHRAsmZ 244858U, // LOCG 1543525890U, // LOCGAsm 469781091U, // LOCGAsmE 469784935U, // LOCGAsmH 469781214U, // LOCGAsmHE 469787513U, // LOCGAsmL 469782047U, // LOCGAsmLE 469785338U, // LOCGAsmLH 469788473U, // LOCGAsmM 469782772U, // LOCGAsmNE 469786201U, // LOCGAsmNH 469781444U, // LOCGAsmNHE 469787826U, // LOCGAsmNL 469782283U, // LOCGAsmNLE 469785636U, // LOCGAsmNLH 469788591U, // LOCGAsmNM 469789017U, // LOCGAsmNO 469789389U, // LOCGAsmNP 469793198U, // LOCGAsmNZ 469788897U, // LOCGAsmO 469789268U, // LOCGAsmP 469793087U, // LOCGAsmZ 8125618U, // LOCGHI 1140875582U, // LOCGHIAsm 67128658U, // LOCGHIAsmE 67131960U, // LOCGHIAsmH 67128087U, // LOCGHIAsmHE 67134423U, // LOCGHIAsmL 67128920U, // LOCGHIAsmLE 67132226U, // LOCGHIAsmLH 67135344U, // LOCGHIAsmM 67129645U, // LOCGHIAsmNE 67133074U, // LOCGHIAsmNH 67128324U, // LOCGHIAsmNHE 67134699U, // LOCGHIAsmNL 67129163U, // LOCGHIAsmNLE 67132516U, // LOCGHIAsmNLH 67135464U, // LOCGHIAsmNM 67135890U, // LOCGHIAsmNO 67136262U, // LOCGHIAsmNP 67140071U, // LOCGHIAsmNZ 67135763U, // LOCGHIAsmO 67136147U, // LOCGHIAsmP 67139953U, // LOCGHIAsmZ 7601436U, // LOCGR 1090547593U, // LOCGRAsm 16798206U, // LOCGRAsmE 16801692U, // LOCGRAsmH 16796898U, // LOCGRAsmHE 16803297U, // LOCGRAsmL 16797737U, // LOCGRAsmLE 16801104U, // LOCGRAsmLH 16803906U, // LOCGRAsmM 16798095U, // LOCGRAsmNE 16801524U, // LOCGRAsmNH 16796779U, // LOCGRAsmNHE 16803149U, // LOCGRAsmNL 16797618U, // LOCGRAsmNLE 16800978U, // LOCGRAsmNLH 16803849U, // LOCGRAsmNM 16804281U, // LOCGRAsmNO 16804647U, // LOCGRAsmNP 16808456U, // LOCGRAsmNZ 16804331U, // LOCGRAsmO 16804690U, // LOCGRAsmP 16808482U, // LOCGRAsmZ 8125625U, // LOCHHI 1140875609U, // LOCHHIAsm 67128667U, // LOCHHIAsmE 67131969U, // LOCHHIAsmH 67128097U, // LOCHHIAsmHE 67134432U, // LOCHHIAsmL 67128930U, // LOCHHIAsmLE 67132236U, // LOCHHIAsmLH 67135353U, // LOCHHIAsmM 67129655U, // LOCHHIAsmNE 67133084U, // LOCHHIAsmNH 67128335U, // LOCHHIAsmNHE 67134709U, // LOCHHIAsmNL 67129174U, // LOCHHIAsmNLE 67132527U, // LOCHHIAsmNLH 67135474U, // LOCHHIAsmNM 67135900U, // LOCHHIAsmNO 67136272U, // LOCHHIAsmNP 67140081U, // LOCHHIAsmNZ 67135772U, // LOCHHIAsmO 67136156U, // LOCHHIAsmP 67139962U, // LOCHHIAsmZ 8125612U, // LOCHI 1140875569U, // LOCHIAsm 67128650U, // LOCHIAsmE 67131952U, // LOCHIAsmH 67128078U, // LOCHIAsmHE 67134415U, // LOCHIAsmL 67128911U, // LOCHIAsmLE 67132217U, // LOCHIAsmLH 67135336U, // LOCHIAsmM 67129636U, // LOCHIAsmNE 67133065U, // LOCHIAsmNH 67128314U, // LOCHIAsmNHE 67134690U, // LOCHIAsmNL 67129153U, // LOCHIAsmNLE 67132506U, // LOCHIAsmNLH 67135455U, // LOCHIAsmNM 67135881U, // LOCHIAsmNO 67136253U, // LOCHIAsmNP 67140062U, // LOCHIAsmNZ 67135755U, // LOCHIAsmO 67136139U, // LOCHIAsmP 67139945U, // LOCHIAsmZ 7601431U, // LOCR 1090547177U, // LOCRAsm 16798199U, // LOCRAsmE 16801685U, // LOCRAsmH 16796890U, // LOCRAsmHE 16803260U, // LOCRAsmL 16797729U, // LOCRAsmLE 16801096U, // LOCRAsmLH 16803884U, // LOCRAsmM 16798087U, // LOCRAsmNE 16801516U, // LOCRAsmNH 16796770U, // LOCRAsmNHE 16803141U, // LOCRAsmNL 16797609U, // LOCRAsmNLE 16800969U, // LOCRAsmNLH 16803841U, // LOCRAsmNM 16804273U, // LOCRAsmNO 16804639U, // LOCRAsmNP 16808448U, // LOCRAsmNZ 16804317U, // LOCRAsmO 16804683U, // LOCRAsmP 16808475U, // LOCRAsmZ 3188355U, // LPCTL 1509968306U, // LPD 33582170U, // LPDBR 33582871U, // LPDFR 33582871U, // LPDFR_32 1509971477U, // LPDG 33582657U, // LPDR 33582304U, // LPEBR 33582815U, // LPER 33582932U, // LPGFR 33583053U, // LPGR 3189574U, // LPP 134245326U, // LPQ 33583376U, // LPR 3192857U, // LPSW 3183237U, // LPSWE 1107312707U, // LPTEA 33582518U, // LPXBR 33583912U, // LPXR 33583227U, // LR 134234396U, // LRA 134239640U, // LRAG 134248537U, // LRAY 33582669U, // LRDR 33582827U, // LRER 268461619U, // LRL 134248422U, // LRV 134240304U, // LRVG 33583084U, // LRVGR 134242388U, // LRVH 33583839U, // LRVR 3188362U, // LSCTL 134248163U, // LT 33582191U, // LTDBR 33582191U, // LTDBRCompare 33582688U, // LTDR 33583563U, // LTDTR 33582325U, // LTEBR 33582325U, // LTEBRCompare 33582839U, // LTER 134240238U, // LTG 134239064U, // LTGF 33582953U, // LTGFR 33583078U, // LTGR 33583658U, // LTR 33582538U, // LTXBR 33582538U, // LTXBRCompare 33583929U, // LTXR 33583815U, // LTXTR 33571206U, // LURA 33576365U, // LURAG 134236634U, // LXD 134235054U, // LXDB 33582198U, // LXDBR 33582694U, // LXDR 1107325401U, // LXDTR 134238860U, // LXE 134235178U, // LXEB 33582332U, // LXEBR 33582845U, // LXER 33583896U, // LXR 134248658U, // LY 3174002U, // LZDR 3174147U, // LZER 134239457U, // LZRF 134240148U, // LZRG 3175231U, // LZXR 26363U, // M 1090537839U, // MAD 1090535937U, // MADB 1090546688U, // MADBR 1090547183U, // MADR 1090537968U, // MAE 1090536386U, // MAEB 1090546820U, // MAEBR 1090547320U, // MAER 1090549844U, // MAY 1090543730U, // MAYH 1090547793U, // MAYHR 1090545390U, // MAYL 1090547939U, // MAYLR 1090548549U, // MAYR 453019900U, // MC 18850U, // MD 17164U, // MDB 16804941U, // MDBR 19027U, // MDE 17372U, // MDEB 16805017U, // MDEBR 16805526U, // MDER 16805430U, // MDR 1107325360U, // MDTR 1107312964U, // MDTRA 20634U, // ME 19038U, // MEE 17385U, // MEEB 16805024U, // MEEBR 16805532U, // MEER 16805582U, // MER 30866U, // MFY 22311U, // MG 22923U, // MGH 67133772U, // MGHI 1107321512U, // MGRK 24018U, // MH 67133805U, // MHI 30886U, // MHY 25695U, // ML 22246U, // MLG 16805812U, // MLGR 16806079U, // MLR 117500597U, // MP 16806129U, // MR 30259U, // MS 18768U, // MSC 3184875U, // MSCH 1090537930U, // MSD 1090536316U, // MSDB 1090546792U, // MSDBR 1090547283U, // MSDR 1090540054U, // MSE 1090536477U, // MSEB 1090546926U, // MSEBR 1090547441U, // MSER 50356513U, // MSFI 22465U, // MSG 18624U, // MSGC 21330U, // MSGF 50356488U, // MSGFI 16805730U, // MSGFR 16805849U, // MSGR 1107314904U, // MSGRKC 16806184U, // MSR 1107314912U, // MSRKC 3162526U, // MSTA 31001U, // MSY 302041441U, // MVC 469803592U, // MVCDK 302049434U, // MVCIN 270914U, // MVCK 33579867U, // MVCL 1107316241U, // MVCLE 1107326895U, // MVCLU 1543550526U, // MVCOS 272943U, // MVCP 275692U, // MVCS 469803750U, // MVCSK 67150162U, // MVGHI 67150177U, // MVHHI 67150194U, // MVHI 453026284U, // MVI 453032134U, // MVIY 302049472U, // MVN 117500425U, // MVO 33576824U, // MVPG 33584977U, // MVST 302053945U, // MVZ 16805289U, // MXBR 18911U, // MXD 17332U, // MXDB 16804989U, // MXDBR 16805484U, // MXDR 16806685U, // MXR 1107325612U, // MXTR 1107313016U, // MXTRA 1107327202U, // MY 1107320952U, // MYH 1107325016U, // MYHR 1107322612U, // MYL 1107325162U, // MYLR 1107325771U, // MYR 26759U, // N 302041349U, // NC 22349U, // NG 16805825U, // NGR 1107321518U, // NGRK 453026173U, // NI 8495285U, // NIAI 100684678U, // NIHF 352344526U, // NIHH 352347064U, // NIHL 100684823U, // NILF 352344931U, // NILH 352347188U, // NILL 453032124U, // NIY 16806140U, // NR 1107321554U, // NRK 134240243U, // NTSTG 30982U, // NY 26823U, // O 302041359U, // OC 22361U, // OG 16805832U, // OGR 1107321524U, // OGRK 453026177U, // OI 100684684U, // OIHF 352344532U, // OIHH 352347070U, // OIHL 100684829U, // OILF 352344937U, // OILH 352347194U, // OILL 453032129U, // OIY 16806145U, // OR 1107321559U, // ORK 30986U, // OY 117498417U, // PACK 15423U, // PALB 3180832U, // PC 15453U, // PCC 15623U, // PCKMO 1149314U, // PFD 153724355U, // PFDRL 3363962U, // PFMF 15629U, // PFPO 33581225U, // PGIN 33584989U, // PGOUT 520126558U, // PKA 520140707U, // PKU 1509976374U, // PLO 33584878U, // POPCNT 1107312775U, // PPA 33581483U, // PPNO 15657U, // PR 33581516U, // PRNO 33584901U, // PT 3167492U, // PTF 15471U, // PTFF 33579495U, // PTI 15428U, // PTLB 1107325270U, // QADTR 1107325528U, // QAXTR 3187089U, // QCTRI 3187164U, // QSI 15634U, // RCHP 1090540991U, // RISBG 1090540991U, // RISBG32 1090545802U, // RISBGN 1090541161U, // RISBHG 1090541235U, // RISBLG 1107321935U, // RLL 1107318490U, // RLLG 1090540998U, // RNSBG 1090541005U, // ROSBG 3189582U, // RP 33573421U, // RRBE 33580816U, // RRBM 1107325366U, // RRDTR 1107325618U, // RRXTR 15506U, // RSCH 1090541012U, // RXSBG 29533U, // S 3180688U, // SAC 3183270U, // SACF 15596U, // SAL 15336U, // SAM24 15324U, // SAM31 15342U, // SAM64 33582064U, // SAR 33583418U, // SCCTR 15618U, // SCHM 3187255U, // SCK 3180747U, // SCKC 15476U, // SCKPF 18891U, // SD 17262U, // SDB 16804969U, // SDBR 16805460U, // SDR 1107325374U, // SDTR 1107312971U, // SDTRA 21015U, // SE 17438U, // SEB 16805103U, // SEBR 16805618U, // SER 3174689U, // SFASR 3164458U, // SFPC 22427U, // SG 21325U, // SGF 16805724U, // SGFR 22928U, // SGH 16805844U, // SGR 1107321530U, // SGRK 24510U, // SH 1107324970U, // SHHHR 1107325105U, // SHHLR 30891U, // SHY 3181924U, // SIE 3178575U, // SIGA 1107323491U, // SIGP 26209U, // SL 469778537U, // SLA 1107318154U, // SLAG 1107321381U, // SLAK 17699U, // SLB 21945U, // SLBG 16805755U, // SLBGR 16805213U, // SLBR 469778481U, // SLDA 469787489U, // SLDL 1107326615U, // SLDT 100688155U, // SLFI 22275U, // SLG 21302U, // SLGF 100688129U, // SLGFI 16805702U, // SLGFR 16805818U, // SLGR 1107321505U, // SLGRK 1107324962U, // SLHHHR 1107325097U, // SLHHLR 469787732U, // SLL 1107318496U, // SLLG 1107321458U, // SLLK 16806105U, // SLR 1107321548U, // SLRK 1107326834U, // SLXT 30939U, // SLY 117500790U, // SP 33583439U, // SPCTR 3178595U, // SPKA 3172391U, // SPM 3192585U, // SPT 3192889U, // SPX 134236599U, // SQD 134234974U, // SQDB 33582177U, // SQDBR 33582663U, // SQDR 134238706U, // SQE 134235159U, // SQEB 33582311U, // SQEBR 33582821U, // SQER 33582525U, // SQXBR 33583918U, // SQXR 16806173U, // SR 469778723U, // SRA 1107318176U, // SRAG 1107321387U, // SRAK 469778487U, // SRDA 469787495U, // SRDL 1107326627U, // SRDT 1107321564U, // SRK 469788230U, // SRL 1107318523U, // SRLG 1107321464U, // SRLK 3188764U, // SRNM 3179850U, // SRNMB 3192551U, // SRNMT 1375791978U, // SRP 33584965U, // SRST 33585082U, // SRSTU 1107326846U, // SRXT 3174508U, // SSAIR 3173365U, // SSAR 3184881U, // SSCH 1107316142U, // SSKE 33574318U, // SSKEOpt 3188847U, // SSM 134248257U, // ST 1107322622U, // STAM 1107327206U, // STAMY 3189262U, // STAP 134236508U, // STC 134240510U, // STCH 3187260U, // STCK 3180753U, // STCKC 3181985U, // STCKE 3183584U, // STCKF 2365613864U, // STCM 2365611478U, // STCMH 2365618419U, // STCMY 3192389U, // STCPS 3192844U, // STCRW 1107318759U, // STCTG 1107322513U, // STCTL 134248554U, // STCY 134236623U, // STD 134248565U, // STDY 134238848U, // STE 134248588U, // STEY 134240604U, // STFH 3187571U, // STFL 3182104U, // STFLE 3180848U, // STFPC 134240245U, // STG 268461552U, // STGRL 134236489U, // STGSC 134242341U, // STH 134240785U, // STHH 268461611U, // STHRL 134248624U, // STHY 3189301U, // STIDP 1107322997U, // STM 1107318590U, // STMG 1107320312U, // STMH 1107327232U, // STMY 453027935U, // STNSM 157547621U, // STOC 1509968147U, // STOCAsm 436226630U, // STOCAsmE 436230364U, // STOCAsmH 436226757U, // STOCAsmHE 436233038U, // STOCAsmL 436227593U, // STOCAsmLE 436230898U, // STOCAsmLH 436234017U, // STOCAsmM 436228325U, // STOCAsmNE 436231761U, // STOCAsmNH 436227003U, // STOCAsmNHE 436233386U, // STOCAsmNL 436227842U, // STOCAsmNLE 436231195U, // STOCAsmNLH 436234151U, // STOCAsmNM 436234577U, // STOCAsmNO 436234949U, // STOCAsmNP 436238758U, // STOCAsmNZ 436234458U, // STOCAsmO 436234792U, // STOCAsmP 436238641U, // STOCAsmZ 157547682U, // STOCFH 1509972303U, // STOCFHAsm 436226773U, // STOCFHAsmE 436230584U, // STOCFHAsmH 436226814U, // STOCFHAsmHE 436233122U, // STOCFHAsmL 436227647U, // STOCFHAsmLE 436230953U, // STOCFHAsmLH 436234074U, // STOCFHAsmM 436228372U, // STOCFHAsmNE 436231801U, // STOCFHAsmNH 436227048U, // STOCFHAsmNHE 436233426U, // STOCFHAsmNL 436227887U, // STOCFHAsmNLE 436231240U, // STOCFHAsmNLH 436234191U, // STOCFHAsmNM 436234617U, // STOCFHAsmNO 436234989U, // STOCFHAsmNP 436238798U, // STOCFHAsmNZ 436234493U, // STOCFHAsmO 436234877U, // STOCFHAsmP 436238683U, // STOCFHAsmZ 157547647U, // STOCG 1509971464U, // STOCGAsm 436226666U, // STOCGAsmE 436230510U, // STOCGAsmH 436226790U, // STOCGAsmHE 436233088U, // STOCGAsmL 436227623U, // STOCGAsmLE 436230914U, // STOCGAsmLH 436234048U, // STOCGAsmM 436228348U, // STOCGAsmNE 436231777U, // STOCGAsmNH 436227021U, // STOCGAsmNHE 436233402U, // STOCGAsmNL 436227860U, // STOCGAsmNLE 436231213U, // STOCGAsmNLH 436234167U, // STOCGAsmNM 436234593U, // STOCGAsmNO 436234965U, // STOCGAsmNP 436238774U, // STOCGAsmNZ 436234472U, // STOCGAsmO 436234843U, // STOCGAsmP 436238662U, // STOCGAsmZ 453027942U, // STOSM 134245331U, // STPQ 3192590U, // STPT 3192894U, // STPX 469800358U, // STRAG 268461650U, // STRL 134248427U, // STRV 134240310U, // STRVG 134242394U, // STRVH 3184887U, // STSCH 3187169U, // STSI 33571212U, // STURA 33576845U, // STURG 134248734U, // STY 30646U, // SU 16806618U, // SUR 280934U, // SVC 30741U, // SW 16806634U, // SWR 16805316U, // SXBR 16806708U, // SXR 1107325626U, // SXTR 1107313023U, // SXTRA 30991U, // SY 3192626U, // TABORT 15614U, // TAM 33582075U, // TAR 33572676U, // TB 218131957U, // TBDR 218131974U, // TBEDR 352364705U, // TBEGIN 352356608U, // TBEGINC 134234680U, // TCDB 134235080U, // TCEB 134236063U, // TCXB 134248073U, // TDCDT 134248111U, // TDCET 134248292U, // TDCXT 134248080U, // TDGDT 134248118U, // TDGET 134248299U, // TDGXT 15466U, // TEND 33582729U, // THDER 33582629U, // THDR 453027958U, // TM 385898999U, // TMHH 385901508U, // TMHL 385899455U, // TMLH 385901632U, // TMLL 453032193U, // TMY 3206027U, // TP 3187084U, // TPI 469808886U, // TPROT 302051631U, // TR 1107315251U, // TRACE 1107318242U, // TRACG 15330U, // TRAP2 3178533U, // TRAP4 33575441U, // TRE 1107323351U, // TROO 33581527U, // TROOOpt 1107326717U, // TROT 33584893U, // TROTOpt 302053178U, // TRT 419648122U, // TRTE 3363450U, // TRTEOpt 1107323395U, // TRTO 33581571U, // TRTOOpt 302051887U, // TRTR 419648015U, // TRTRE 3363343U, // TRTREOpt 1107326807U, // TRTT 33584983U, // TRTTOpt 3192396U, // TS 3184888U, // TSCH 117498500U, // UNPK 302039132U, // UNPKA 302053281U, // UNPKU 15690U, // UPT 1107313060U, // VA 1107313093U, // VAB 1107314837U, // VAC 1107314846U, // VACC 1107313110U, // VACCB 1107314852U, // VACCC 1107323809U, // VACCCQ 1107317420U, // VACCF 1107318249U, // VACCG 1107318967U, // VACCH 1107323802U, // VACCQ 1107323796U, // VACQ 1107317409U, // VAF 1107318196U, // VAG 1107318901U, // VAH 1107323412U, // VAP 1107323791U, // VAQ 1107318787U, // VAVG 1107313749U, // VAVGB 1107317598U, // VAVGF 1107318363U, // VAVGG 1107319189U, // VAVGH 1107321741U, // VAVGL 1107313880U, // VAVGLB 1107317755U, // VAVGLF 1107318473U, // VAVGLG 1107319569U, // VAVGLH 1107322931U, // VBPERM 1107318287U, // VCDG 1107313712U, // VCDGB 1107318466U, // VCDLG 1107313733U, // VCDLGB 1107323817U, // VCEQ 1107314063U, // VCEQB 1107325965U, // VCEQBS 1107317962U, // VCEQF 1107326248U, // VCEQFS 1107318654U, // VCEQG 1107326340U, // VCEQGS 1107320718U, // VCEQH 1107326414U, // VCEQHS 1107315084U, // VCGD 1107313310U, // VCGDB 1107319044U, // VCH 1107313770U, // VCHB 1107325950U, // VCHBS 1107317619U, // VCHF 1107326233U, // VCHFS 1107318385U, // VCHG 1107326325U, // VCHGS 1107319210U, // VCHH 1107326399U, // VCHHS 1107321748U, // VCHL 1107313888U, // VCHLB 1107325957U, // VCHLBS 1107317763U, // VCHLF 1107326240U, // VCHLFS 1107318481U, // VCHLG 1107326332U, // VCHLGS 1107319577U, // VCHLH 1107326406U, // VCHLHS 1107322968U, // VCKSM 1107315090U, // VCLGD 1107313324U, // VCLGDB 1107327380U, // VCLZ 33572983U, // VCLZB 33576298U, // VCLZF 33577041U, // VCLZG 33579175U, // VCLZH 1107323440U, // VCP 1107327539U, // VCTZ 33572990U, // VCTZB 33576305U, // VCTZF 33577048U, // VCTZG 33579182U, // VCTZH 1107314513U, // VCVB 1107318235U, // VCVBG 1107315156U, // VCVD 1107318299U, // VCVDG 1107323458U, // VDP 1107314859U, // VEC 33571293U, // VECB 33575603U, // VECF 33576432U, // VECG 33577150U, // VECH 1107321660U, // VECL 33572049U, // VECLB 33575924U, // VECLF 33576635U, // VECLG 33577700U, // VECLH 1090545538U, // VERIM 1090536770U, // VERIMB 1090540678U, // VERIMF 1090541361U, // VERIMG 1090543082U, // VERIMH 1107321933U, // VERLL 1107313903U, // VERLLB 1107317809U, // VERLLF 1107318488U, // VERLLG 1107319735U, // VERLLH 1107326927U, // VERLLV 1107314526U, // VERLLVB 1107318048U, // VERLLVF 1107318800U, // VERLLVG 1107320890U, // VERLLVH 1107322469U, // VESL 1107313953U, // VESLB 1107317852U, // VESLF 1107318529U, // VESLG 1107320178U, // VESLH 1107326943U, // VESLV 1107314544U, // VESLVB 1107318066U, // VESLVF 1107318818U, // VESLVG 1107320908U, // VESLVH 1107312929U, // VESRA 1107313078U, // VESRAB 1107317401U, // VESRAF 1107318174U, // VESRAG 1107318893U, // VESRAH 1107326913U, // VESRAV 1107314504U, // VESRAVB 1107318032U, // VESRAVF 1107318778U, // VESRAVG 1107320874U, // VESRAVH 1107322436U, // VESRL 1107313938U, // VESRLB 1107317844U, // VESRLF 1107318521U, // VESRLG 1107320170U, // VESRLH 1107326935U, // VESRLV 1107314535U, // VESRLVB 1107318057U, // VESRLVF 1107318809U, // VESRLVG 1107320899U, // VESRLVH 1107312714U, // VFA 1107313137U, // VFADB 1107315172U, // VFAE 1107313594U, // VFAEB 1107325925U, // VFAEBS 1107317447U, // VFAEF 1107326208U, // VFAEFS 1107319049U, // VFAEH 1107326374U, // VFAEHS 1107314774U, // VFAEZB 1107326160U, // VFAEZBS 1107318089U, // VFAEZF 1107326297U, // VFAEZFS 1107320966U, // VFAEZH 1107326458U, // VFAEZHS 1107314102U, // VFASB 1107315258U, // VFCE 1107313228U, // VFCEDB 1107325813U, // VFCEDBS 1107314187U, // VFCESB 1107325982U, // VFCESBS 1107318980U, // VFCH 1107313340U, // VFCHDB 1107325889U, // VFCHDBS 1107315383U, // VFCHE 1107313244U, // VFCHEDB 1107325831U, // VFCHEDBS 1107314203U, // VFCHESB 1107326000U, // VFCHESBS 1107314255U, // VFCHSB 1107326058U, // VFCHSBS 1107315079U, // VFD 1107313214U, // VFDDB 1107314173U, // VFDSB 1107315288U, // VFEE 1107313634U, // VFEEB 1107325933U, // VFEEBS 1107317468U, // VFEEF 1107326216U, // VFEEFS 1107319063U, // VFEEH 1107326382U, // VFEEHS 1107314782U, // VFEEZB 1107326169U, // VFEEZBS 1107318097U, // VFEEZF 1107326306U, // VFEEZFS 1107320974U, // VFEEZH 1107326467U, // VFEEZHS 1107316973U, // VFENE 1107313679U, // VFENEB 1107325941U, // VFENEBS 1107317508U, // VFENEF 1107326224U, // VFENEFS 1107319097U, // VFENEH 1107326390U, // VFENEHS 1107314798U, // VFENEZB 1107326178U, // VFENEZBS 1107318113U, // VFENEZF 1107326315U, // VFENEZFS 1107320990U, // VFENEZH 1107326476U, // VFENEZHS 1107321127U, // VFI 1107313390U, // VFIDB 1107314305U, // VFISB 1107313280U, // VFKEDB 1107325871U, // VFKEDBS 1107314239U, // VFKESB 1107326040U, // VFKESBS 1107313356U, // VFKHDB 1107325907U, // VFKHDBS 1107313262U, // VFKHEDB 1107325851U, // VFKHEDBS 1107314221U, // VFKHESB 1107326020U, // VFKHESBS 1107314271U, // VFKHSB 1107326076U, // VFKHSBS 33571368U, // VFLCDB 33572333U, // VFLCSB 1107321889U, // VFLL 33584675U, // VFLLS 33571626U, // VFLNDB 33572534U, // VFLNSB 33571660U, // VFLPDB 33572568U, // VFLPSB 1107325070U, // VFLR 1107315132U, // VFLRD 1107322676U, // VFM 1107312757U, // VFMA 1107313151U, // VFMADB 1107314116U, // VFMASB 1107327012U, // VFMAX 1107313564U, // VFMAXDB 1107314477U, // VFMAXSB 1107313418U, // VFMDB 1107323055U, // VFMIN 1107313432U, // VFMINDB 1107314340U, // VFMINSB 1107326513U, // VFMS 1107314326U, // VFMSB 1107313530U, // VFMSDB 1107314438U, // VFMSSB 1107312768U, // VFNMA 1107313167U, // VFNMADB 1107314132U, // VFNMASB 1107326519U, // VFNMS 1107313546U, // VFNMSDB 1107314454U, // VFNMSSB 1107323388U, // VFPSO 1107313466U, // VFPSODB 1107314374U, // VFPSOSB 1107326282U, // VFS 1107313516U, // VFSDB 1107323865U, // VFSQ 33571676U, // VFSQDB 33572584U, // VFSQSB 1107314424U, // VFSSB 1107321040U, // VFTCI 1107313372U, // VFTCIDB 1107314287U, // VFTCISB 385902340U, // VGBM 3758117603U, // VGEF 536892969U, // VGEG 1107322670U, // VGFM 1107312750U, // VGFMA 1107313070U, // VGFMAB 1107317393U, // VGFMAF 1107318160U, // VGFMAG 1107318879U, // VGFMAH 1107313973U, // VGFMB 1107317875U, // VGFMF 1107318564U, // VGFMG 1107320285U, // VGFMH 1476421453U, // VGM 1476412732U, // VGMB 1476416640U, // VGMF 1476417323U, // VGMG 1476419044U, // VGMH 1107325500U, // VISTR 1107314094U, // VISTRB 33584149U, // VISTRBS 1107317977U, // VISTRF 33584432U, // VISTRFS 1107320755U, // VISTRH 33584598U, // VISTRHS 134244068U, // VL 1207976400U, // VLBB 1107314934U, // VLC 33571299U, // VLCB 33575609U, // VLCF 33576444U, // VLCG 33577168U, // VLCH 1107315277U, // VLDE 33571790U, // VLDEB 1073759235U, // VLEB 1107315068U, // VLED 1107313296U, // VLEDB 1073763064U, // VLEF 1073763887U, // VLEG 1073764653U, // VLEH 1140868264U, // VLEIB 1140872145U, // VLEIF 1140872851U, // VLEIG 1140873769U, // VLEIH 1107326921U, // VLGV 1107314519U, // VLGVB 1107318041U, // VLGVF 1107318793U, // VLGVG 1107320883U, // VLGVH 1459645093U, // VLIP 1107321945U, // VLL 1207990584U, // VLLEZ 134236262U, // VLLEZB 134239577U, // VLLEZF 134240329U, // VLLEZG 134242454U, // VLLEZH 134239338U, // VLLEZLF 1107322774U, // VLM 1107323567U, // VLP 33572233U, // VLPB 33576132U, // VLPF 33576812U, // VLPG 33578882U, // VLPH 33583326U, // VLR 1207986759U, // VLREP 134235514U, // VLREPB 134239413U, // VLREPF 134240093U, // VLREPG 134242163U, // VLREPH 1509975608U, // VLRL 1107325130U, // VLRLR 1090541610U, // VLVG 1090536540U, // VLVGB 1090540389U, // VLVGF 1090541154U, // VLVGG 1090541980U, // VLVGH 1107323502U, // VLVGP 1107315183U, // VMAE 1107313601U, // VMAEB 1107317454U, // VMAEF 1107319056U, // VMAEH 1107318887U, // VMAH 1107313763U, // VMAHB 1107317612U, // VMAHF 1107319203U, // VMAHH 1107321598U, // VMAL 1107313866U, // VMALB 1107316148U, // VMALE 1107313652U, // VMALEB 1107317481U, // VMALEF 1107319070U, // VMALEH 1107317741U, // VMALF 1107319453U, // VMALH 1107313776U, // VMALHB 1107317656U, // VMALHF 1107319258U, // VMALHH 1107326965U, // VMALHW 1107323177U, // VMALO 1107314021U, // VMALOB 1107317920U, // VMALOF 1107320670U, // VMALOH 1107323082U, // VMAO 1107314014U, // VMAOB 1107317913U, // VMAOF 1107320663U, // VMAOH 1107316889U, // VME 1107313673U, // VMEB 1107317502U, // VMEF 1107319091U, // VMEH 1107320325U, // VMH 1107313799U, // VMHB 1107317685U, // VMHF 1107319293U, // VMHH 1107321950U, // VML 1107313911U, // VMLB 1107316396U, // VMLE 1107313660U, // VMLEB 1107317489U, // VMLEF 1107319078U, // VMLEH 1107317817U, // VMLF 1107319749U, // VMLH 1107313784U, // VMLHB 1107317670U, // VMLHF 1107319272U, // VMLHH 1107326973U, // VMLHW 1107323184U, // VMLO 1107314029U, // VMLOB 1107317928U, // VMLOF 1107320678U, // VMLOH 1107323062U, // VMN 1107314008U, // VMNB 1107317907U, // VMNF 1107318609U, // VMNG 1107320550U, // VMNH 1107322175U, // VMNL 1107313917U, // VMNLB 1107317823U, // VMNLF 1107318507U, // VMNLG 1107320002U, // VMNLH 1107323200U, // VMO 1107314036U, // VMOB 1107317935U, // VMOF 1107320685U, // VMOH 1107323572U, // VMP 1107320749U, // VMRH 1107313812U, // VMRHB 1107317698U, // VMRHF 1107318391U, // VMRHG 1107319306U, // VMRHH 1107322430U, // VMRL 1107313931U, // VMRLB 1107317837U, // VMRLF 1107318514U, // VMRLG 1107320163U, // VMRLH 1107322475U, // VMSL 1107318536U, // VMSLG 1107323775U, // VMSP 1107327023U, // VMX 1107314684U, // VMXB 1107318074U, // VMXF 1107318851U, // VMXG 1107320934U, // VMXH 1107322600U, // VMXL 1107313966U, // VMXLB 1107317859U, // VMXLF 1107318550U, // VMXLG 1107320265U, // VMXLH 1107323073U, // VN 1107314953U, // VNC 1107323067U, // VNN 1107323346U, // VNO 1107327028U, // VNX 1107323402U, // VO 1107314969U, // VOC 3166593U, // VONE 1107321047U, // VPDI 1107322939U, // VPERM 1107321482U, // VPK 1107317735U, // VPKF 1107318438U, // VPKG 1107319447U, // VPKH 1107326492U, // VPKLS 1107317998U, // VPKLSF 1107326273U, // VPKLSFS 1107318713U, // VPKLSG 1107326356U, // VPKLSGS 1107320770U, // VPKLSH 1107326439U, // VPKLSHS 1107326486U, // VPKS 1107317991U, // VPKSF 1107326265U, // VPKSFS 1107318706U, // VPKSG 1107326348U, // VPKSGS 1107320763U, // VPKSH 1107326431U, // VPKSHS 1509980558U, // VPKZ 1107326587U, // VPOPCT 33572671U, // VPOPCTB 33576187U, // VPOPCTF 33576919U, // VPOPCTG 33578959U, // VPOPCTH 1107323706U, // VPSOP 1107323470U, // VREP 1107314050U, // VREPB 1107317949U, // VREPF 1107318629U, // VREPG 1107320699U, // VREPH 1358979461U, // VREPI 285230274U, // VREPIB 285234136U, // VREPIF 285234842U, // VREPIG 285235792U, // VREPIH 1107323759U, // VRP 1107326544U, // VS 1107314472U, // VSB 1107321019U, // VSBCBI 1107323823U, // VSBCBIQ 1107321034U, // VSBI 1107323840U, // VSBIQ 1107321027U, // VSCBI 1107313819U, // VSCBIB 1107317705U, // VSCBIF 1107318411U, // VSCBIG 1107319324U, // VSCBIH 1107323832U, // VSCBIQ 2701152981U, // VSCEF 3774895650U, // VSCEG 1107323452U, // VSDP 1107318338U, // VSEG 33571902U, // VSEGB 33575709U, // VSEGF 33577334U, // VSEGH 1107321709U, // VSEL 1107318006U, // VSF 1107318726U, // VSG 1107320778U, // VSH 1107322481U, // VSL 1107313960U, // VSLB 1107313411U, // VSLDB 1107323781U, // VSP 1107323871U, // VSQ 1107312936U, // VSRA 1107313086U, // VSRAB 1107322443U, // VSRL 1107313946U, // VSRLB 1107323753U, // VSRP 134248274U, // VST 1207976995U, // VSTEB 1207980812U, // VSTEF 1207981640U, // VSTEG 1207982401U, // VSTEH 1107322590U, // VSTL 1107322996U, // VSTM 1107315004U, // VSTRC 1107313129U, // VSTRCB 1107325804U, // VSTRCBS 1107317439U, // VSTRCF 1107326199U, // VSTRCFS 1107319011U, // VSTRCH 1107326365U, // VSTRCHS 1107314765U, // VSTRCZB 1107326150U, // VSTRCZBS 1107318080U, // VSTRCZF 1107326287U, // VSTRCZFS 1107320957U, // VSTRCZH 1107326448U, // VSTRCZHS 1509975633U, // VSTRL 1107325137U, // VSTRLR 1107323007U, // VSUM 1107314001U, // VSUMB 1107318596U, // VSUMG 1107317564U, // VSUMGF 1107319176U, // VSUMGH 1107320318U, // VSUMH 1107323847U, // VSUMQ 1107317969U, // VSUMQF 1107318661U, // VSUMQG 33581178U, // VTM 3173258U, // VTP 1107320712U, // VUPH 33571981U, // VUPHB 33575867U, // VUPHF 33577475U, // VUPHH 1509980551U, // VUPKZ 1107322288U, // VUPL 33572100U, // VUPLB 33576006U, // VUPLF 1107320129U, // VUPLH 33571967U, // VUPLHB 33575853U, // VUPLHF 33577455U, // VUPLHH 33585156U, // VUPLHW 1107321926U, // VUPLL 33572071U, // VUPLLB 33575977U, // VUPLLF 33577903U, // VUPLLH 1107327051U, // VX 3172836U, // VZERO 1107313719U, // WCDGB 1107313741U, // WCDLGB 1107313317U, // WCGDB 1107313332U, // WCLGDB 1107313144U, // WFADB 1107314109U, // WFASB 1107314552U, // WFAXB 1107314869U, // WFC 33571361U, // WFCDB 1107313236U, // WFCEDB 1107325822U, // WFCEDBS 1107314195U, // WFCESB 1107325991U, // WFCESBS 1107314604U, // WFCEXB 1107326094U, // WFCEXBS 1107313348U, // WFCHDB 1107325898U, // WFCHDBS 1107313253U, // WFCHEDB 1107325841U, // WFCHEDBS 1107314212U, // WFCHESB 1107326010U, // WFCHESBS 1107314612U, // WFCHEXB 1107326103U, // WFCHEXBS 1107314263U, // WFCHSB 1107326067U, // WFCHSBS 1107314638U, // WFCHXB 1107326132U, // WFCHXBS 33572326U, // WFCSB 33572752U, // WFCXB 1107313221U, // WFDDB 1107314180U, // WFDSB 1107314597U, // WFDXB 1107313397U, // WFIDB 1107314312U, // WFISB 1107314663U, // WFIXB 1107321423U, // WFK 33571580U, // WFKDB 1107313288U, // WFKEDB 1107325880U, // WFKEDBS 1107314247U, // WFKESB 1107326049U, // WFKESBS 1107314630U, // WFKEXB 1107326123U, // WFKEXBS 1107313364U, // WFKHDB 1107325916U, // WFKHDBS 1107313271U, // WFKHEDB 1107325861U, // WFKHEDBS 1107314230U, // WFKHESB 1107326030U, // WFKHESBS 1107314621U, // WFKHEXB 1107326113U, // WFKHEXBS 1107314279U, // WFKHSB 1107326085U, // WFKHSBS 1107314646U, // WFKHXB 1107326141U, // WFKHXBS 33572495U, // WFKSB 33572846U, // WFKXB 33571376U, // WFLCDB 33572341U, // WFLCSB 33572759U, // WFLCXB 33573273U, // WFLLD 33584682U, // WFLLS 33571634U, // WFLNDB 33572542U, // WFLNSB 33572875U, // WFLNXB 33571668U, // WFLPDB 33572576U, // WFLPSB 33572892U, // WFLPXB 1107315139U, // WFLRD 1107327044U, // WFLRX 1107313159U, // WFMADB 1107314124U, // WFMASB 1107314559U, // WFMAXB 1107313573U, // WFMAXDB 1107314486U, // WFMAXSB 1107314756U, // WFMAXXB 1107313425U, // WFMDB 1107313441U, // WFMINDB 1107314349U, // WFMINSB 1107314690U, // WFMINXB 1107314333U, // WFMSB 1107313538U, // WFMSDB 1107314446U, // WFMSSB 1107314739U, // WFMSXB 1107314677U, // WFMXB 1107313176U, // WFNMADB 1107314141U, // WFNMASB 1107314567U, // WFNMAXB 1107313555U, // WFNMSDB 1107314463U, // WFNMSSB 1107314747U, // WFNMSXB 1107313475U, // WFPSODB 1107314383U, // WFPSOSB 1107314707U, // WFPSOXB 1107313523U, // WFSDB 33571684U, // WFSQDB 33572592U, // WFSQSB 33572900U, // WFSQXB 1107314431U, // WFSSB 1107314732U, // WFSXB 1107313381U, // WFTCIDB 1107314296U, // WFTCISB 1107314654U, // WFTCIXB 33571797U, // WLDEB 1107313303U, // WLEDB 30753U, // X 302041451U, // XC 22591U, // XG 16805876U, // XGR 1107321536U, // XGRK 453026289U, // XI 100684690U, // XIHF 100684835U, // XILF 453032140U, // XIY 16806640U, // XR 1107321569U, // XRK 15511U, // XSCH 31011U, // XY 117500441U, // ZAP }; static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ADJDYNALLOC 0U, // AEXT128 0U, // AFIMux 0U, // AHIMux 0U, // AHIMuxK 0U, // ATOMIC_CMP_SWAPW 0U, // ATOMIC_LOADW_AFI 0U, // ATOMIC_LOADW_AR 0U, // ATOMIC_LOADW_MAX 0U, // ATOMIC_LOADW_MIN 0U, // ATOMIC_LOADW_NILH 0U, // ATOMIC_LOADW_NILHi 0U, // ATOMIC_LOADW_NR 0U, // ATOMIC_LOADW_NRi 0U, // ATOMIC_LOADW_OILH 0U, // ATOMIC_LOADW_OR 0U, // ATOMIC_LOADW_SR 0U, // ATOMIC_LOADW_UMAX 0U, // ATOMIC_LOADW_UMIN 0U, // ATOMIC_LOADW_XILF 0U, // ATOMIC_LOADW_XR 0U, // ATOMIC_LOAD_AFI 0U, // ATOMIC_LOAD_AGFI 0U, // ATOMIC_LOAD_AGHI 0U, // ATOMIC_LOAD_AGR 0U, // ATOMIC_LOAD_AHI 0U, // ATOMIC_LOAD_AR 0U, // ATOMIC_LOAD_MAX_32 0U, // ATOMIC_LOAD_MAX_64 0U, // ATOMIC_LOAD_MIN_32 0U, // ATOMIC_LOAD_MIN_64 0U, // ATOMIC_LOAD_NGR 0U, // ATOMIC_LOAD_NGRi 0U, // ATOMIC_LOAD_NIHF64 0U, // ATOMIC_LOAD_NIHF64i 0U, // ATOMIC_LOAD_NIHH64 0U, // ATOMIC_LOAD_NIHH64i 0U, // ATOMIC_LOAD_NIHL64 0U, // ATOMIC_LOAD_NIHL64i 0U, // ATOMIC_LOAD_NILF 0U, // ATOMIC_LOAD_NILF64 0U, // ATOMIC_LOAD_NILF64i 0U, // ATOMIC_LOAD_NILFi 0U, // ATOMIC_LOAD_NILH 0U, // ATOMIC_LOAD_NILH64 0U, // ATOMIC_LOAD_NILH64i 0U, // ATOMIC_LOAD_NILHi 0U, // ATOMIC_LOAD_NILL 0U, // ATOMIC_LOAD_NILL64 0U, // ATOMIC_LOAD_NILL64i 0U, // ATOMIC_LOAD_NILLi 0U, // ATOMIC_LOAD_NR 0U, // ATOMIC_LOAD_NRi 0U, // ATOMIC_LOAD_OGR 0U, // ATOMIC_LOAD_OIHF64 0U, // ATOMIC_LOAD_OIHH64 0U, // ATOMIC_LOAD_OIHL64 0U, // ATOMIC_LOAD_OILF 0U, // ATOMIC_LOAD_OILF64 0U, // ATOMIC_LOAD_OILH 0U, // ATOMIC_LOAD_OILH64 0U, // ATOMIC_LOAD_OILL 0U, // ATOMIC_LOAD_OILL64 0U, // ATOMIC_LOAD_OR 0U, // ATOMIC_LOAD_SGR 0U, // ATOMIC_LOAD_SR 0U, // ATOMIC_LOAD_UMAX_32 0U, // ATOMIC_LOAD_UMAX_64 0U, // ATOMIC_LOAD_UMIN_32 0U, // ATOMIC_LOAD_UMIN_64 0U, // ATOMIC_LOAD_XGR 0U, // ATOMIC_LOAD_XIHF64 0U, // ATOMIC_LOAD_XILF 0U, // ATOMIC_LOAD_XILF64 0U, // ATOMIC_LOAD_XR 0U, // ATOMIC_SWAPW 0U, // ATOMIC_SWAP_32 0U, // ATOMIC_SWAP_64 0U, // CFIMux 0U, // CGIBCall 0U, // CGIBReturn 0U, // CGRBCall 0U, // CGRBReturn 0U, // CHIMux 0U, // CIBCall 0U, // CIBReturn 0U, // CLCLoop 0U, // CLCSequence 0U, // CLFIMux 0U, // CLGIBCall 0U, // CLGIBReturn 0U, // CLGRBCall 0U, // CLGRBReturn 0U, // CLIBCall 0U, // CLIBReturn 0U, // CLMux 0U, // CLRBCall 0U, // CLRBReturn 0U, // CLSTLoop 0U, // CMux 0U, // CRBCall 0U, // CRBReturn 0U, // CallBASR 0U, // CallBCR 0U, // CallBR 0U, // CallBRASL 0U, // CallBRCL 0U, // CallJG 0U, // CondReturn 0U, // CondStore16 0U, // CondStore16Inv 0U, // CondStore16Mux 0U, // CondStore16MuxInv 0U, // CondStore32 0U, // CondStore32Inv 0U, // CondStore32Mux 0U, // CondStore32MuxInv 0U, // CondStore64 0U, // CondStore64Inv 0U, // CondStore8 0U, // CondStore8Inv 0U, // CondStore8Mux 0U, // CondStore8MuxInv 0U, // CondStoreF32 0U, // CondStoreF32Inv 0U, // CondStoreF64 0U, // CondStoreF64Inv 0U, // CondTrap 0U, // GOT 0U, // IIFMux 0U, // IIHF64 0U, // IIHH64 0U, // IIHL64 0U, // IIHMux 0U, // IILF64 0U, // IILH64 0U, // IILL64 0U, // IILMux 0U, // L128 0U, // LBMux 0U, // LEFR 0U, // LFER 0U, // LHIMux 0U, // LHMux 0U, // LLCMux 0U, // LLCRMux 0U, // LLHMux 0U, // LLHRMux 0U, // LMux 0U, // LOCHIMux 0U, // LOCMux 0U, // LOCRMux 0U, // LRMux 0U, // LTDBRCompare_VecPseudo 0U, // LTEBRCompare_VecPseudo 0U, // LTXBRCompare_VecPseudo 0U, // LX 0U, // MVCLoop 0U, // MVCSequence 0U, // MVSTLoop 0U, // MemBarrier 0U, // NCLoop 0U, // NCSequence 0U, // NIFMux 0U, // NIHF64 0U, // NIHH64 0U, // NIHL64 0U, // NIHMux 0U, // NILF64 0U, // NILH64 0U, // NILL64 0U, // NILMux 0U, // OCLoop 0U, // OCSequence 0U, // OIFMux 0U, // OIHF64 0U, // OIHH64 0U, // OIHL64 0U, // OIHMux 0U, // OILF64 0U, // OILH64 0U, // OILL64 0U, // OILMux 0U, // PAIR128 0U, // RISBHH 0U, // RISBHL 0U, // RISBLH 0U, // RISBLL 0U, // RISBMux 0U, // Return 0U, // SRSTLoop 0U, // ST128 0U, // STCMux 0U, // STHMux 0U, // STMux 0U, // STOCMux 0U, // STX 0U, // Select32 0U, // Select64 0U, // SelectF128 0U, // SelectF32 0U, // SelectF64 0U, // SelectVR128 0U, // SelectVR32 0U, // SelectVR64 0U, // Serialize 0U, // TBEGIN_nofloat 0U, // TLS_GDCALL 0U, // TLS_LDCALL 0U, // TMHH64 0U, // TMHL64 0U, // TMHMux 0U, // TMLH64 0U, // TMLL64 0U, // TMLMux 0U, // Trap 0U, // VL32 0U, // VL64 0U, // VLR32 0U, // VLR64 0U, // VLVGP32 0U, // VST32 0U, // VST64 0U, // XCLoop 0U, // XCSequence 0U, // XIFMux 0U, // XIHF64 0U, // XILF64 0U, // ZEXT128 0U, // A 0U, // AD 0U, // ADB 0U, // ADBR 0U, // ADR 0U, // ADTR 512U, // ADTRA 0U, // AE 0U, // AEB 0U, // AEBR 0U, // AER 0U, // AFI 0U, // AG 0U, // AGF 0U, // AGFI 0U, // AGFR 0U, // AGH 0U, // AGHI 8U, // AGHIK 0U, // AGR 0U, // AGRK 0U, // AGSI 0U, // AH 0U, // AHHHR 0U, // AHHLR 0U, // AHI 8U, // AHIK 0U, // AHY 0U, // AIH 0U, // AL 0U, // ALC 0U, // ALCG 0U, // ALCGR 0U, // ALCR 0U, // ALFI 0U, // ALG 0U, // ALGF 0U, // ALGFI 0U, // ALGFR 8U, // ALGHSIK 0U, // ALGR 0U, // ALGRK 0U, // ALGSI 0U, // ALHHHR 0U, // ALHHLR 8U, // ALHSIK 0U, // ALR 0U, // ALRK 0U, // ALSI 0U, // ALSIH 0U, // ALSIHN 0U, // ALY 0U, // AP 0U, // AR 0U, // ARK 0U, // ASI 0U, // AU 0U, // AUR 0U, // AW 0U, // AWR 0U, // AXBR 0U, // AXR 0U, // AXTR 512U, // AXTRA 0U, // AY 0U, // B 0U, // BAKR 0U, // BAL 0U, // BALR 0U, // BAS 0U, // BASR 0U, // BASSM 0U, // BAsmE 0U, // BAsmH 0U, // BAsmHE 0U, // BAsmL 0U, // BAsmLE 0U, // BAsmLH 0U, // BAsmM 0U, // BAsmNE 0U, // BAsmNH 0U, // BAsmNHE 0U, // BAsmNL 0U, // BAsmNLE 0U, // BAsmNLH 0U, // BAsmNM 0U, // BAsmNO 0U, // BAsmNP 0U, // BAsmNZ 0U, // BAsmO 0U, // BAsmP 0U, // BAsmZ 0U, // BC 0U, // BCAsm 0U, // BCR 0U, // BCRAsm 0U, // BCT 0U, // BCTG 0U, // BCTGR 0U, // BCTR 0U, // BI 0U, // BIAsmE 0U, // BIAsmH 0U, // BIAsmHE 0U, // BIAsmL 0U, // BIAsmLE 0U, // BIAsmLH 0U, // BIAsmM 0U, // BIAsmNE 0U, // BIAsmNH 0U, // BIAsmNHE 0U, // BIAsmNL 0U, // BIAsmNLE 0U, // BIAsmNLH 0U, // BIAsmNM 0U, // BIAsmNO 0U, // BIAsmNP 0U, // BIAsmNZ 0U, // BIAsmO 0U, // BIAsmP 0U, // BIAsmZ 0U, // BIC 0U, // BICAsm 0U, // BPP 0U, // BPRP 0U, // BR 0U, // BRAS 0U, // BRASL 0U, // BRAsmE 0U, // BRAsmH 0U, // BRAsmHE 0U, // BRAsmL 0U, // BRAsmLE 0U, // BRAsmLH 0U, // BRAsmM 0U, // BRAsmNE 0U, // BRAsmNH 0U, // BRAsmNHE 0U, // BRAsmNL 0U, // BRAsmNLE 0U, // BRAsmNLH 0U, // BRAsmNM 0U, // BRAsmNO 0U, // BRAsmNP 0U, // BRAsmNZ 0U, // BRAsmO 0U, // BRAsmP 0U, // BRAsmZ 0U, // BRC 0U, // BRCAsm 0U, // BRCL 0U, // BRCLAsm 0U, // BRCT 0U, // BRCTG 0U, // BRCTH 16U, // BRXH 16U, // BRXHG 16U, // BRXLE 16U, // BRXLG 0U, // BSA 0U, // BSG 0U, // BSM 24U, // BXH 24U, // BXHG 24U, // BXLE 24U, // BXLEG 0U, // C 0U, // CD 0U, // CDB 0U, // CDBR 0U, // CDFBR 33U, // CDFBRA 0U, // CDFR 33U, // CDFTR 0U, // CDGBR 33U, // CDGBRA 0U, // CDGR 0U, // CDGTR 33U, // CDGTRA 33U, // CDLFBR 33U, // CDLFTR 33U, // CDLGBR 33U, // CDLGTR 0U, // CDPT 0U, // CDR 24U, // CDS 24U, // CDSG 0U, // CDSTR 24U, // CDSY 0U, // CDTR 0U, // CDUTR 0U, // CDZT 0U, // CE 0U, // CEB 0U, // CEBR 0U, // CEDTR 0U, // CEFBR 33U, // CEFBRA 0U, // CEFR 0U, // CEGBR 33U, // CEGBRA 0U, // CEGR 33U, // CELFBR 33U, // CELGBR 0U, // CER 0U, // CEXTR 0U, // CFC 41U, // CFDBR 33U, // CFDBRA 41U, // CFDR 33U, // CFDTR 41U, // CFEBR 33U, // CFEBRA 41U, // CFER 0U, // CFI 41U, // CFXBR 33U, // CFXBRA 41U, // CFXR 33U, // CFXTR 0U, // CG 41U, // CGDBR 33U, // CGDBRA 41U, // CGDR 41U, // CGDTR 33U, // CGDTRA 41U, // CGEBR 33U, // CGEBRA 41U, // CGER 0U, // CGF 0U, // CGFI 0U, // CGFR 0U, // CGFRL 0U, // CGH 0U, // CGHI 0U, // CGHRL 0U, // CGHSI 0U, // CGIB 25U, // CGIBAsm 1U, // CGIBAsmE 1U, // CGIBAsmH 1U, // CGIBAsmHE 1U, // CGIBAsmL 1U, // CGIBAsmLE 1U, // CGIBAsmLH 1U, // CGIBAsmNE 1U, // CGIBAsmNH 1U, // CGIBAsmNHE 1U, // CGIBAsmNL 1U, // CGIBAsmNLE 1U, // CGIBAsmNLH 0U, // CGIJ 17U, // CGIJAsm 0U, // CGIJAsmE 0U, // CGIJAsmH 0U, // CGIJAsmHE 0U, // CGIJAsmL 0U, // CGIJAsmLE 0U, // CGIJAsmLH 0U, // CGIJAsmNE 0U, // CGIJAsmNH 0U, // CGIJAsmNHE 0U, // CGIJAsmNL 0U, // CGIJAsmNLE 0U, // CGIJAsmNLH 0U, // CGIT 48U, // CGITAsm 0U, // CGITAsmE 0U, // CGITAsmH 0U, // CGITAsmHE 0U, // CGITAsmL 0U, // CGITAsmLE 0U, // CGITAsmLH 0U, // CGITAsmNE 0U, // CGITAsmNH 0U, // CGITAsmNHE 0U, // CGITAsmNL 0U, // CGITAsmNLE 0U, // CGITAsmNLH 0U, // CGR 41U, // CGRB 8752U, // CGRBAsm 56U, // CGRBAsmE 56U, // CGRBAsmH 56U, // CGRBAsmHE 56U, // CGRBAsmL 56U, // CGRBAsmLE 56U, // CGRBAsmLH 56U, // CGRBAsmNE 56U, // CGRBAsmNH 56U, // CGRBAsmNHE 56U, // CGRBAsmNL 56U, // CGRBAsmNLE 56U, // CGRBAsmNLH 2U, // CGRJ 16944U, // CGRJAsm 64U, // CGRJAsmE 64U, // CGRJAsmH 64U, // CGRJAsmHE 64U, // CGRJAsmL 64U, // CGRJAsmLE 64U, // CGRJAsmLH 64U, // CGRJAsmNE 64U, // CGRJAsmNH 64U, // CGRJAsmNHE 64U, // CGRJAsmNL 64U, // CGRJAsmNLE 64U, // CGRJAsmNLH 0U, // CGRL 0U, // CGRT 48U, // CGRTAsm 0U, // CGRTAsmE 0U, // CGRTAsmH 0U, // CGRTAsmHE 0U, // CGRTAsmL 0U, // CGRTAsmLE 0U, // CGRTAsmLH 0U, // CGRTAsmNE 0U, // CGRTAsmNH 0U, // CGRTAsmNHE 0U, // CGRTAsmNL 0U, // CGRTAsmNLE 0U, // CGRTAsmNLH 41U, // CGXBR 33U, // CGXBRA 41U, // CGXR 41U, // CGXTR 33U, // CGXTRA 0U, // CH 0U, // CHF 0U, // CHHR 0U, // CHHSI 0U, // CHI 0U, // CHLR 0U, // CHRL 0U, // CHSI 0U, // CHY 0U, // CIB 25U, // CIBAsm 1U, // CIBAsmE 1U, // CIBAsmH 1U, // CIBAsmHE 1U, // CIBAsmL 1U, // CIBAsmLE 1U, // CIBAsmLH 1U, // CIBAsmNE 1U, // CIBAsmNH 1U, // CIBAsmNHE 1U, // CIBAsmNL 1U, // CIBAsmNLE 1U, // CIBAsmNLH 0U, // CIH 0U, // CIJ 17U, // CIJAsm 0U, // CIJAsmE 0U, // CIJAsmH 0U, // CIJAsmHE 0U, // CIJAsmL 0U, // CIJAsmLE 0U, // CIJAsmLH 0U, // CIJAsmNE 0U, // CIJAsmNH 0U, // CIJAsmNHE 0U, // CIJAsmNL 0U, // CIJAsmNLE 0U, // CIJAsmNLH 0U, // CIT 48U, // CITAsm 0U, // CITAsmE 0U, // CITAsmH 0U, // CITAsmHE 0U, // CITAsmL 0U, // CITAsmLE 0U, // CITAsmLH 0U, // CITAsmNE 0U, // CITAsmNH 0U, // CITAsmNHE 0U, // CITAsmNL 0U, // CITAsmNLE 0U, // CITAsmNLH 0U, // CKSM 0U, // CL 0U, // CLC 0U, // CLCL 72U, // CLCLE 72U, // CLCLU 33U, // CLFDBR 33U, // CLFDTR 33U, // CLFEBR 0U, // CLFHSI 0U, // CLFI 0U, // CLFIT 48U, // CLFITAsm 0U, // CLFITAsmE 0U, // CLFITAsmH 0U, // CLFITAsmHE 0U, // CLFITAsmL 0U, // CLFITAsmLE 0U, // CLFITAsmLH 0U, // CLFITAsmNE 0U, // CLFITAsmNH 0U, // CLFITAsmNHE 0U, // CLFITAsmNL 0U, // CLFITAsmNLE 0U, // CLFITAsmNLH 33U, // CLFXBR 33U, // CLFXTR 0U, // CLG 33U, // CLGDBR 33U, // CLGDTR 33U, // CLGEBR 0U, // CLGF 0U, // CLGFI 0U, // CLGFR 0U, // CLGFRL 0U, // CLGHRL 0U, // CLGHSI 0U, // CLGIB 25U, // CLGIBAsm 1U, // CLGIBAsmE 1U, // CLGIBAsmH 1U, // CLGIBAsmHE 1U, // CLGIBAsmL 1U, // CLGIBAsmLE 1U, // CLGIBAsmLH 1U, // CLGIBAsmNE 1U, // CLGIBAsmNH 1U, // CLGIBAsmNHE 1U, // CLGIBAsmNL 1U, // CLGIBAsmNLE 1U, // CLGIBAsmNLH 0U, // CLGIJ 17U, // CLGIJAsm 0U, // CLGIJAsmE 0U, // CLGIJAsmH 0U, // CLGIJAsmHE 0U, // CLGIJAsmL 0U, // CLGIJAsmLE 0U, // CLGIJAsmLH 0U, // CLGIJAsmNE 0U, // CLGIJAsmNH 0U, // CLGIJAsmNHE 0U, // CLGIJAsmNL 0U, // CLGIJAsmNLE 0U, // CLGIJAsmNLH 0U, // CLGIT 48U, // CLGITAsm 0U, // CLGITAsmE 0U, // CLGITAsmH 0U, // CLGITAsmHE 0U, // CLGITAsmL 0U, // CLGITAsmLE 0U, // CLGITAsmLH 0U, // CLGITAsmNE 0U, // CLGITAsmNH 0U, // CLGITAsmNHE 0U, // CLGITAsmNL 0U, // CLGITAsmNLE 0U, // CLGITAsmNLH 0U, // CLGR 41U, // CLGRB 8752U, // CLGRBAsm 56U, // CLGRBAsmE 56U, // CLGRBAsmH 56U, // CLGRBAsmHE 56U, // CLGRBAsmL 56U, // CLGRBAsmLE 56U, // CLGRBAsmLH 56U, // CLGRBAsmNE 56U, // CLGRBAsmNH 56U, // CLGRBAsmNHE 56U, // CLGRBAsmNL 56U, // CLGRBAsmNLE 56U, // CLGRBAsmNLH 2U, // CLGRJ 16944U, // CLGRJAsm 64U, // CLGRJAsmE 64U, // CLGRJAsmH 64U, // CLGRJAsmHE 64U, // CLGRJAsmL 64U, // CLGRJAsmLE 64U, // CLGRJAsmLH 64U, // CLGRJAsmNE 64U, // CLGRJAsmNH 64U, // CLGRJAsmNHE 64U, // CLGRJAsmNL 64U, // CLGRJAsmNLE 64U, // CLGRJAsmNLH 0U, // CLGRL 0U, // CLGRT 48U, // CLGRTAsm 0U, // CLGRTAsmE 0U, // CLGRTAsmH 0U, // CLGRTAsmHE 0U, // CLGRTAsmL 0U, // CLGRTAsmLE 0U, // CLGRTAsmLH 0U, // CLGRTAsmNE 0U, // CLGRTAsmNH 0U, // CLGRTAsmNHE 0U, // CLGRTAsmNL 0U, // CLGRTAsmNLE 0U, // CLGRTAsmNLH 0U, // CLGT 80U, // CLGTAsm 0U, // CLGTAsmE 0U, // CLGTAsmH 0U, // CLGTAsmHE 0U, // CLGTAsmL 0U, // CLGTAsmLE 0U, // CLGTAsmLH 0U, // CLGTAsmNE 0U, // CLGTAsmNH 0U, // CLGTAsmNHE 0U, // CLGTAsmNL 0U, // CLGTAsmNLE 0U, // CLGTAsmNLH 33U, // CLGXBR 33U, // CLGXTR 0U, // CLHF 0U, // CLHHR 0U, // CLHHSI 0U, // CLHLR 0U, // CLHRL 0U, // CLI 0U, // CLIB 25U, // CLIBAsm 1U, // CLIBAsmE 1U, // CLIBAsmH 1U, // CLIBAsmHE 1U, // CLIBAsmL 1U, // CLIBAsmLE 1U, // CLIBAsmLH 1U, // CLIBAsmNE 1U, // CLIBAsmNH 1U, // CLIBAsmNHE 1U, // CLIBAsmNL 1U, // CLIBAsmNLE 1U, // CLIBAsmNLH 0U, // CLIH 0U, // CLIJ 17U, // CLIJAsm 0U, // CLIJAsmE 0U, // CLIJAsmH 0U, // CLIJAsmHE 0U, // CLIJAsmL 0U, // CLIJAsmLE 0U, // CLIJAsmLH 0U, // CLIJAsmNE 0U, // CLIJAsmNH 0U, // CLIJAsmNHE 0U, // CLIJAsmNL 0U, // CLIJAsmNLE 0U, // CLIJAsmNLH 0U, // CLIY 1U, // CLM 1U, // CLMH 1U, // CLMY 0U, // CLR 41U, // CLRB 8752U, // CLRBAsm 56U, // CLRBAsmE 56U, // CLRBAsmH 56U, // CLRBAsmHE 56U, // CLRBAsmL 56U, // CLRBAsmLE 56U, // CLRBAsmLH 56U, // CLRBAsmNE 56U, // CLRBAsmNH 56U, // CLRBAsmNHE 56U, // CLRBAsmNL 56U, // CLRBAsmNLE 56U, // CLRBAsmNLH 2U, // CLRJ 16944U, // CLRJAsm 64U, // CLRJAsmE 64U, // CLRJAsmH 64U, // CLRJAsmHE 64U, // CLRJAsmL 64U, // CLRJAsmLE 64U, // CLRJAsmLH 64U, // CLRJAsmNE 64U, // CLRJAsmNH 64U, // CLRJAsmNHE 64U, // CLRJAsmNL 64U, // CLRJAsmNLE 64U, // CLRJAsmNLH 0U, // CLRL 0U, // CLRT 48U, // CLRTAsm 0U, // CLRTAsmE 0U, // CLRTAsmH 0U, // CLRTAsmHE 0U, // CLRTAsmL 0U, // CLRTAsmLE 0U, // CLRTAsmLH 0U, // CLRTAsmNE 0U, // CLRTAsmNH 0U, // CLRTAsmNHE 0U, // CLRTAsmNL 0U, // CLRTAsmNLE 0U, // CLRTAsmNLH 0U, // CLST 0U, // CLT 80U, // CLTAsm 0U, // CLTAsmE 0U, // CLTAsmH 0U, // CLTAsmHE 0U, // CLTAsmL 0U, // CLTAsmLE 0U, // CLTAsmLH 0U, // CLTAsmNE 0U, // CLTAsmNH 0U, // CLTAsmNHE 0U, // CLTAsmNL 0U, // CLTAsmNLE 0U, // CLTAsmNLH 0U, // CLY 0U, // CMPSC 0U, // CP 0U, // CPDT 88U, // CPSDRdd 88U, // CPSDRds 88U, // CPSDRsd 88U, // CPSDRss 0U, // CPXT 0U, // CPYA 0U, // CR 41U, // CRB 8752U, // CRBAsm 56U, // CRBAsmE 56U, // CRBAsmH 56U, // CRBAsmHE 56U, // CRBAsmL 56U, // CRBAsmLE 56U, // CRBAsmLH 56U, // CRBAsmNE 56U, // CRBAsmNH 56U, // CRBAsmNHE 56U, // CRBAsmNL 56U, // CRBAsmNLE 56U, // CRBAsmNLH 600U, // CRDTE 88U, // CRDTEOpt 2U, // CRJ 16944U, // CRJAsm 64U, // CRJAsmE 64U, // CRJAsmH 64U, // CRJAsmHE 64U, // CRJAsmL 64U, // CRJAsmLE 64U, // CRJAsmLH 64U, // CRJAsmNE 64U, // CRJAsmNH 64U, // CRJAsmNHE 64U, // CRJAsmNL 64U, // CRJAsmNLE 64U, // CRJAsmNLH 0U, // CRL 0U, // CRT 48U, // CRTAsm 0U, // CRTAsmE 0U, // CRTAsmH 0U, // CRTAsmHE 0U, // CRTAsmL 0U, // CRTAsmLE 0U, // CRTAsmLH 0U, // CRTAsmNE 0U, // CRTAsmNH 0U, // CRTAsmNHE 0U, // CRTAsmNL 0U, // CRTAsmNLE 0U, // CRTAsmNLH 24U, // CS 0U, // CSCH 48U, // CSDTR 24U, // CSG 0U, // CSP 0U, // CSPG 96U, // CSST 48U, // CSXTR 24U, // CSY 104U, // CU12 0U, // CU12Opt 104U, // CU14 0U, // CU14Opt 104U, // CU21 0U, // CU21Opt 104U, // CU24 0U, // CU24Opt 0U, // CU41 0U, // CU42 0U, // CUDTR 0U, // CUSE 104U, // CUTFU 0U, // CUTFUOpt 104U, // CUUTF 0U, // CUUTFOpt 0U, // CUXTR 0U, // CVB 0U, // CVBG 0U, // CVBY 0U, // CVD 0U, // CVDG 0U, // CVDY 0U, // CXBR 0U, // CXFBR 33U, // CXFBRA 0U, // CXFR 33U, // CXFTR 0U, // CXGBR 33U, // CXGBRA 0U, // CXGR 0U, // CXGTR 33U, // CXGTRA 33U, // CXLFBR 33U, // CXLFTR 33U, // CXLGBR 33U, // CXLGTR 0U, // CXPT 0U, // CXR 0U, // CXSTR 0U, // CXTR 0U, // CXUTR 0U, // CXZT 0U, // CY 0U, // CZDT 0U, // CZXT 0U, // D 0U, // DD 0U, // DDB 0U, // DDBR 0U, // DDR 0U, // DDTR 512U, // DDTRA 0U, // DE 0U, // DEB 0U, // DEBR 0U, // DER 56U, // DIAG 25200U, // DIDBR 25200U, // DIEBR 0U, // DL 0U, // DLG 0U, // DLGR 0U, // DLR 0U, // DP 0U, // DR 0U, // DSG 0U, // DSGF 0U, // DSGFR 0U, // DSGR 0U, // DXBR 0U, // DXR 0U, // DXTR 512U, // DXTRA 0U, // EAR 56U, // ECAG 0U, // ECCTR 0U, // ECPGA 96U, // ECTG 0U, // ED 0U, // EDMK 0U, // EEDTR 0U, // EEXTR 0U, // EFPC 0U, // EPAIR 0U, // EPAR 0U, // EPCTR 0U, // EPSW 0U, // EREG 0U, // EREGG 0U, // ESAIR 0U, // ESAR 0U, // ESDTR 0U, // ESEA 0U, // ESTA 0U, // ESXTR 0U, // ETND 0U, // EX 0U, // EXRL 41U, // FIDBR 33U, // FIDBRA 0U, // FIDR 33U, // FIDTR 41U, // FIEBR 33U, // FIEBRA 0U, // FIER 41U, // FIXBR 33U, // FIXBRA 0U, // FIXR 33U, // FIXTR 0U, // FLOGR 0U, // HDR 0U, // HER 0U, // HSCH 0U, // IAC 0U, // IC 0U, // IC32 0U, // IC32Y 0U, // ICM 0U, // ICMH 0U, // ICMY 0U, // ICY 600U, // IDTE 88U, // IDTEOpt 88U, // IEDTR 88U, // IEXTR 0U, // IIHF 0U, // IIHH 0U, // IIHL 0U, // IILF 0U, // IILH 0U, // IILL 0U, // IPK 0U, // IPM 512U, // IPTE 0U, // IPTEOpt 0U, // IPTEOptOpt 0U, // IRBM 0U, // ISKE 0U, // IVSK 0U, // InsnE 2U, // InsnRI 1145U, // InsnRIE 0U, // InsnRIL 2U, // InsnRILU 2U, // InsnRIS 0U, // InsnRR 41U, // InsnRRE 1657U, // InsnRRF 34937U, // InsnRRS 2681U, // InsnRS 2681U, // InsnRSE 1145U, // InsnRSI 2681U, // InsnRSY 0U, // InsnRX 0U, // InsnRXE 3193U, // InsnRXF 0U, // InsnRXY 0U, // InsnS 3U, // InsnSI 3U, // InsnSIL 3U, // InsnSIY 0U, // InsnSS 41U, // InsnSSE 3705U, // InsnSSF 0U, // J 0U, // JAsmE 0U, // JAsmH 0U, // JAsmHE 0U, // JAsmL 0U, // JAsmLE 0U, // JAsmLH 0U, // JAsmM 0U, // JAsmNE 0U, // JAsmNH 0U, // JAsmNHE 0U, // JAsmNL 0U, // JAsmNLE 0U, // JAsmNLH 0U, // JAsmNM 0U, // JAsmNO 0U, // JAsmNP 0U, // JAsmNZ 0U, // JAsmO 0U, // JAsmP 0U, // JAsmZ 0U, // JG 0U, // JGAsmE 0U, // JGAsmH 0U, // JGAsmHE 0U, // JGAsmL 0U, // JGAsmLE 0U, // JGAsmLH 0U, // JGAsmM 0U, // JGAsmNE 0U, // JGAsmNH 0U, // JGAsmNHE 0U, // JGAsmNL 0U, // JGAsmNLE 0U, // JGAsmNLH 0U, // JGAsmNM 0U, // JGAsmNO 0U, // JGAsmNP 0U, // JGAsmNZ 0U, // JGAsmO 0U, // JGAsmP 0U, // JGAsmZ 0U, // KDB 0U, // KDBR 0U, // KDTR 0U, // KEB 0U, // KEBR 0U, // KIMD 0U, // KLMD 0U, // KM 88U, // KMA 0U, // KMAC 0U, // KMC 88U, // KMCTR 0U, // KMF 0U, // KMO 0U, // KXBR 0U, // KXTR 0U, // L 0U, // LA 56U, // LAA 56U, // LAAG 56U, // LAAL 56U, // LAALG 0U, // LAE 0U, // LAEY 56U, // LAM 56U, // LAMY 56U, // LAN 56U, // LANG 56U, // LAO 56U, // LAOG 0U, // LARL 0U, // LASP 0U, // LAT 56U, // LAX 56U, // LAXG 0U, // LAY 0U, // LB 0U, // LBH 0U, // LBR 104U, // LCBB 0U, // LCCTL 0U, // LCDBR 0U, // LCDFR 0U, // LCDFR_32 0U, // LCDR 0U, // LCEBR 0U, // LCER 0U, // LCGFR 0U, // LCGR 0U, // LCR 56U, // LCTL 56U, // LCTLG 0U, // LCXBR 0U, // LCXR 0U, // LD 0U, // LDE 0U, // LDE32 0U, // LDEB 0U, // LDEBR 0U, // LDER 48U, // LDETR 0U, // LDGR 0U, // LDR 0U, // LDR32 0U, // LDXBR 33U, // LDXBRA 0U, // LDXR 33U, // LDXTR 0U, // LDY 0U, // LE 0U, // LEDBR 33U, // LEDBRA 0U, // LEDR 33U, // LEDTR 0U, // LER 0U, // LEXBR 33U, // LEXBRA 0U, // LEXR 0U, // LEY 0U, // LFAS 0U, // LFH 0U, // LFHAT 0U, // LFPC 0U, // LG 0U, // LGAT 0U, // LGB 0U, // LGBR 0U, // LGDR 0U, // LGF 0U, // LGFI 0U, // LGFR 0U, // LGFRL 0U, // LGG 0U, // LGH 0U, // LGHI 0U, // LGHR 0U, // LGHRL 0U, // LGR 0U, // LGRL 0U, // LGSC 0U, // LH 0U, // LHH 0U, // LHI 0U, // LHR 0U, // LHRL 0U, // LHY 0U, // LLC 0U, // LLCH 0U, // LLCR 0U, // LLGC 0U, // LLGCR 0U, // LLGF 0U, // LLGFAT 0U, // LLGFR 0U, // LLGFRL 0U, // LLGFSG 0U, // LLGH 0U, // LLGHR 0U, // LLGHRL 0U, // LLGT 0U, // LLGTAT 0U, // LLGTR 0U, // LLH 0U, // LLHH 0U, // LLHR 0U, // LLHRL 0U, // LLIHF 0U, // LLIHH 0U, // LLIHL 0U, // LLILF 0U, // LLILH 0U, // LLILL 0U, // LLZRGF 56U, // LM 41528U, // LMD 56U, // LMG 56U, // LMH 56U, // LMY 0U, // LNDBR 0U, // LNDFR 0U, // LNDFR_32 0U, // LNDR 0U, // LNEBR 0U, // LNER 0U, // LNGFR 0U, // LNGR 0U, // LNR 0U, // LNXBR 0U, // LNXR 0U, // LOC 104U, // LOCAsm 0U, // LOCAsmE 0U, // LOCAsmH 0U, // LOCAsmHE 0U, // LOCAsmL 0U, // LOCAsmLE 0U, // LOCAsmLH 0U, // LOCAsmM 0U, // LOCAsmNE 0U, // LOCAsmNH 0U, // LOCAsmNHE 0U, // LOCAsmNL 0U, // LOCAsmNLE 0U, // LOCAsmNLH 0U, // LOCAsmNM 0U, // LOCAsmNO 0U, // LOCAsmNP 0U, // LOCAsmNZ 0U, // LOCAsmO 0U, // LOCAsmP 0U, // LOCAsmZ 0U, // LOCFH 104U, // LOCFHAsm 0U, // LOCFHAsmE 0U, // LOCFHAsmH 0U, // LOCFHAsmHE 0U, // LOCFHAsmL 0U, // LOCFHAsmLE 0U, // LOCFHAsmLH 0U, // LOCFHAsmM 0U, // LOCFHAsmNE 0U, // LOCFHAsmNH 0U, // LOCFHAsmNHE 0U, // LOCFHAsmNL 0U, // LOCFHAsmNLE 0U, // LOCFHAsmNLH 0U, // LOCFHAsmNM 0U, // LOCFHAsmNO 0U, // LOCFHAsmNP 0U, // LOCFHAsmNZ 0U, // LOCFHAsmO 0U, // LOCFHAsmP 0U, // LOCFHAsmZ 0U, // LOCFHR 128U, // LOCFHRAsm 0U, // LOCFHRAsmE 0U, // LOCFHRAsmH 0U, // LOCFHRAsmHE 0U, // LOCFHRAsmL 0U, // LOCFHRAsmLE 0U, // LOCFHRAsmLH 0U, // LOCFHRAsmM 0U, // LOCFHRAsmNE 0U, // LOCFHRAsmNH 0U, // LOCFHRAsmNHE 0U, // LOCFHRAsmNL 0U, // LOCFHRAsmNLE 0U, // LOCFHRAsmNLH 0U, // LOCFHRAsmNM 0U, // LOCFHRAsmNO 0U, // LOCFHRAsmNP 0U, // LOCFHRAsmNZ 0U, // LOCFHRAsmO 0U, // LOCFHRAsmP 0U, // LOCFHRAsmZ 0U, // LOCG 104U, // LOCGAsm 0U, // LOCGAsmE 0U, // LOCGAsmH 0U, // LOCGAsmHE 0U, // LOCGAsmL 0U, // LOCGAsmLE 0U, // LOCGAsmLH 0U, // LOCGAsmM 0U, // LOCGAsmNE 0U, // LOCGAsmNH 0U, // LOCGAsmNHE 0U, // LOCGAsmNL 0U, // LOCGAsmNLE 0U, // LOCGAsmNLH 0U, // LOCGAsmNM 0U, // LOCGAsmNO 0U, // LOCGAsmNP 0U, // LOCGAsmNZ 0U, // LOCGAsmO 0U, // LOCGAsmP 0U, // LOCGAsmZ 0U, // LOCGHI 128U, // LOCGHIAsm 0U, // LOCGHIAsmE 0U, // LOCGHIAsmH 0U, // LOCGHIAsmHE 0U, // LOCGHIAsmL 0U, // LOCGHIAsmLE 0U, // LOCGHIAsmLH 0U, // LOCGHIAsmM 0U, // LOCGHIAsmNE 0U, // LOCGHIAsmNH 0U, // LOCGHIAsmNHE 0U, // LOCGHIAsmNL 0U, // LOCGHIAsmNLE 0U, // LOCGHIAsmNLH 0U, // LOCGHIAsmNM 0U, // LOCGHIAsmNO 0U, // LOCGHIAsmNP 0U, // LOCGHIAsmNZ 0U, // LOCGHIAsmO 0U, // LOCGHIAsmP 0U, // LOCGHIAsmZ 0U, // LOCGR 128U, // LOCGRAsm 0U, // LOCGRAsmE 0U, // LOCGRAsmH 0U, // LOCGRAsmHE 0U, // LOCGRAsmL 0U, // LOCGRAsmLE 0U, // LOCGRAsmLH 0U, // LOCGRAsmM 0U, // LOCGRAsmNE 0U, // LOCGRAsmNH 0U, // LOCGRAsmNHE 0U, // LOCGRAsmNL 0U, // LOCGRAsmNLE 0U, // LOCGRAsmNLH 0U, // LOCGRAsmNM 0U, // LOCGRAsmNO 0U, // LOCGRAsmNP 0U, // LOCGRAsmNZ 0U, // LOCGRAsmO 0U, // LOCGRAsmP 0U, // LOCGRAsmZ 0U, // LOCHHI 128U, // LOCHHIAsm 0U, // LOCHHIAsmE 0U, // LOCHHIAsmH 0U, // LOCHHIAsmHE 0U, // LOCHHIAsmL 0U, // LOCHHIAsmLE 0U, // LOCHHIAsmLH 0U, // LOCHHIAsmM 0U, // LOCHHIAsmNE 0U, // LOCHHIAsmNH 0U, // LOCHHIAsmNHE 0U, // LOCHHIAsmNL 0U, // LOCHHIAsmNLE 0U, // LOCHHIAsmNLH 0U, // LOCHHIAsmNM 0U, // LOCHHIAsmNO 0U, // LOCHHIAsmNP 0U, // LOCHHIAsmNZ 0U, // LOCHHIAsmO 0U, // LOCHHIAsmP 0U, // LOCHHIAsmZ 0U, // LOCHI 128U, // LOCHIAsm 0U, // LOCHIAsmE 0U, // LOCHIAsmH 0U, // LOCHIAsmHE 0U, // LOCHIAsmL 0U, // LOCHIAsmLE 0U, // LOCHIAsmLH 0U, // LOCHIAsmM 0U, // LOCHIAsmNE 0U, // LOCHIAsmNH 0U, // LOCHIAsmNHE 0U, // LOCHIAsmNL 0U, // LOCHIAsmNLE 0U, // LOCHIAsmNLH 0U, // LOCHIAsmNM 0U, // LOCHIAsmNO 0U, // LOCHIAsmNP 0U, // LOCHIAsmNZ 0U, // LOCHIAsmO 0U, // LOCHIAsmP 0U, // LOCHIAsmZ 0U, // LOCR 128U, // LOCRAsm 0U, // LOCRAsmE 0U, // LOCRAsmH 0U, // LOCRAsmHE 0U, // LOCRAsmL 0U, // LOCRAsmLE 0U, // LOCRAsmLH 0U, // LOCRAsmM 0U, // LOCRAsmNE 0U, // LOCRAsmNH 0U, // LOCRAsmNHE 0U, // LOCRAsmNL 0U, // LOCRAsmNLE 0U, // LOCRAsmNLH 0U, // LOCRAsmNM 0U, // LOCRAsmNO 0U, // LOCRAsmNP 0U, // LOCRAsmNZ 0U, // LOCRAsmO 0U, // LOCRAsmP 0U, // LOCRAsmZ 0U, // LPCTL 24U, // LPD 0U, // LPDBR 0U, // LPDFR 0U, // LPDFR_32 24U, // LPDG 0U, // LPDR 0U, // LPEBR 0U, // LPER 0U, // LPGFR 0U, // LPGR 0U, // LPP 0U, // LPQ 0U, // LPR 0U, // LPSW 0U, // LPSWE 25200U, // LPTEA 0U, // LPXBR 0U, // LPXR 0U, // LR 0U, // LRA 0U, // LRAG 0U, // LRAY 0U, // LRDR 0U, // LRER 0U, // LRL 0U, // LRV 0U, // LRVG 0U, // LRVGR 0U, // LRVH 0U, // LRVR 0U, // LSCTL 0U, // LT 0U, // LTDBR 0U, // LTDBRCompare 0U, // LTDR 0U, // LTDTR 0U, // LTEBR 0U, // LTEBRCompare 0U, // LTER 0U, // LTG 0U, // LTGF 0U, // LTGFR 0U, // LTGR 0U, // LTR 0U, // LTXBR 0U, // LTXBRCompare 0U, // LTXR 0U, // LTXTR 0U, // LURA 0U, // LURAG 0U, // LXD 0U, // LXDB 0U, // LXDBR 0U, // LXDR 48U, // LXDTR 0U, // LXE 0U, // LXEB 0U, // LXEBR 0U, // LXER 0U, // LXR 0U, // LY 0U, // LZDR 0U, // LZER 0U, // LZRF 0U, // LZRG 0U, // LZXR 0U, // M 136U, // MAD 136U, // MADB 112U, // MADBR 112U, // MADR 136U, // MAE 136U, // MAEB 112U, // MAEBR 112U, // MAER 136U, // MAY 136U, // MAYH 112U, // MAYHR 136U, // MAYL 112U, // MAYLR 112U, // MAYR 0U, // MC 0U, // MD 0U, // MDB 0U, // MDBR 0U, // MDE 0U, // MDEB 0U, // MDEBR 0U, // MDER 0U, // MDR 0U, // MDTR 512U, // MDTRA 0U, // ME 0U, // MEE 0U, // MEEB 0U, // MEEBR 0U, // MEER 0U, // MER 0U, // MFY 0U, // MG 0U, // MGH 0U, // MGHI 0U, // MGRK 0U, // MH 0U, // MHI 0U, // MHY 0U, // ML 0U, // MLG 0U, // MLGR 0U, // MLR 0U, // MP 0U, // MR 0U, // MS 0U, // MSC 0U, // MSCH 136U, // MSD 136U, // MSDB 112U, // MSDBR 112U, // MSDR 136U, // MSE 136U, // MSEB 112U, // MSEBR 112U, // MSER 0U, // MSFI 0U, // MSG 0U, // MSGC 0U, // MSGF 0U, // MSGFI 0U, // MSGFR 0U, // MSGR 0U, // MSGRKC 0U, // MSR 0U, // MSRKC 0U, // MSTA 0U, // MSY 0U, // MVC 0U, // MVCDK 0U, // MVCIN 0U, // MVCK 0U, // MVCL 72U, // MVCLE 72U, // MVCLU 96U, // MVCOS 0U, // MVCP 0U, // MVCS 0U, // MVCSK 0U, // MVGHI 0U, // MVHHI 0U, // MVHI 0U, // MVI 0U, // MVIY 0U, // MVN 0U, // MVO 0U, // MVPG 0U, // MVST 0U, // MVZ 0U, // MXBR 0U, // MXD 0U, // MXDB 0U, // MXDBR 0U, // MXDR 0U, // MXR 0U, // MXTR 512U, // MXTRA 144U, // MY 144U, // MYH 0U, // MYHR 144U, // MYL 0U, // MYLR 0U, // MYR 0U, // N 0U, // NC 0U, // NG 0U, // NGR 0U, // NGRK 0U, // NI 0U, // NIAI 0U, // NIHF 0U, // NIHH 0U, // NIHL 0U, // NILF 0U, // NILH 0U, // NILL 0U, // NIY 0U, // NR 0U, // NRK 0U, // NTSTG 0U, // NY 0U, // O 0U, // OC 0U, // OG 0U, // OGR 0U, // OGRK 0U, // OI 0U, // OIHF 0U, // OIHH 0U, // OIHL 0U, // OILF 0U, // OILH 0U, // OILL 0U, // OIY 0U, // OR 0U, // ORK 0U, // OY 0U, // PACK 0U, // PALB 0U, // PC 0U, // PCC 0U, // PCKMO 0U, // PFD 0U, // PFDRL 0U, // PFMF 0U, // PFPO 0U, // PGIN 0U, // PGOUT 0U, // PKA 0U, // PKU 41584U, // PLO 0U, // POPCNT 48U, // PPA 0U, // PPNO 0U, // PR 0U, // PRNO 0U, // PT 0U, // PTF 0U, // PTFF 0U, // PTI 0U, // PTLB 25200U, // QADTR 25200U, // QAXTR 0U, // QCTRI 0U, // QSI 0U, // RCHP 49816U, // RISBG 49816U, // RISBG32 49816U, // RISBGN 49816U, // RISBHG 49816U, // RISBLG 56U, // RLL 56U, // RLLG 49816U, // RNSBG 49816U, // ROSBG 0U, // RP 0U, // RRBE 0U, // RRBM 25200U, // RRDTR 25200U, // RRXTR 0U, // RSCH 49816U, // RXSBG 0U, // S 0U, // SAC 0U, // SACF 0U, // SAL 0U, // SAM24 0U, // SAM31 0U, // SAM64 0U, // SAR 0U, // SCCTR 0U, // SCHM 0U, // SCK 0U, // SCKC 0U, // SCKPF 0U, // SD 0U, // SDB 0U, // SDBR 0U, // SDR 0U, // SDTR 512U, // SDTRA 0U, // SE 0U, // SEB 0U, // SEBR 0U, // SER 0U, // SFASR 0U, // SFPC 0U, // SG 0U, // SGF 0U, // SGFR 0U, // SGH 0U, // SGR 0U, // SGRK 0U, // SH 0U, // SHHHR 0U, // SHHLR 0U, // SHY 0U, // SIE 0U, // SIGA 56U, // SIGP 0U, // SL 0U, // SLA 56U, // SLAG 56U, // SLAK 0U, // SLB 0U, // SLBG 0U, // SLBGR 0U, // SLBR 0U, // SLDA 0U, // SLDL 144U, // SLDT 0U, // SLFI 0U, // SLG 0U, // SLGF 0U, // SLGFI 0U, // SLGFR 0U, // SLGR 0U, // SLGRK 0U, // SLHHHR 0U, // SLHHLR 0U, // SLL 56U, // SLLG 56U, // SLLK 0U, // SLR 0U, // SLRK 144U, // SLXT 0U, // SLY 0U, // SP 0U, // SPCTR 0U, // SPKA 0U, // SPM 0U, // SPT 0U, // SPX 0U, // SQD 0U, // SQDB 0U, // SQDBR 0U, // SQDR 0U, // SQE 0U, // SQEB 0U, // SQEBR 0U, // SQER 0U, // SQXBR 0U, // SQXR 0U, // SR 0U, // SRA 56U, // SRAG 56U, // SRAK 0U, // SRDA 0U, // SRDL 144U, // SRDT 0U, // SRK 0U, // SRL 56U, // SRLG 56U, // SRLK 0U, // SRNM 0U, // SRNMB 0U, // SRNMT 160U, // SRP 0U, // SRST 0U, // SRSTU 144U, // SRXT 0U, // SSAIR 0U, // SSAR 0U, // SSCH 48U, // SSKE 0U, // SSKEOpt 0U, // SSM 0U, // ST 56U, // STAM 56U, // STAMY 0U, // STAP 0U, // STC 0U, // STCH 0U, // STCK 0U, // STCKC 0U, // STCKE 0U, // STCKF 1U, // STCM 1U, // STCMH 1U, // STCMY 0U, // STCPS 0U, // STCRW 56U, // STCTG 56U, // STCTL 0U, // STCY 0U, // STD 0U, // STDY 0U, // STE 0U, // STEY 0U, // STFH 0U, // STFL 0U, // STFLE 0U, // STFPC 0U, // STG 0U, // STGRL 0U, // STGSC 0U, // STH 0U, // STHH 0U, // STHRL 0U, // STHY 0U, // STIDP 56U, // STM 56U, // STMG 56U, // STMH 56U, // STMY 0U, // STNSM 0U, // STOC 128U, // STOCAsm 0U, // STOCAsmE 0U, // STOCAsmH 0U, // STOCAsmHE 0U, // STOCAsmL 0U, // STOCAsmLE 0U, // STOCAsmLH 0U, // STOCAsmM 0U, // STOCAsmNE 0U, // STOCAsmNH 0U, // STOCAsmNHE 0U, // STOCAsmNL 0U, // STOCAsmNLE 0U, // STOCAsmNLH 0U, // STOCAsmNM 0U, // STOCAsmNO 0U, // STOCAsmNP 0U, // STOCAsmNZ 0U, // STOCAsmO 0U, // STOCAsmP 0U, // STOCAsmZ 0U, // STOCFH 128U, // STOCFHAsm 0U, // STOCFHAsmE 0U, // STOCFHAsmH 0U, // STOCFHAsmHE 0U, // STOCFHAsmL 0U, // STOCFHAsmLE 0U, // STOCFHAsmLH 0U, // STOCFHAsmM 0U, // STOCFHAsmNE 0U, // STOCFHAsmNH 0U, // STOCFHAsmNHE 0U, // STOCFHAsmNL 0U, // STOCFHAsmNLE 0U, // STOCFHAsmNLH 0U, // STOCFHAsmNM 0U, // STOCFHAsmNO 0U, // STOCFHAsmNP 0U, // STOCFHAsmNZ 0U, // STOCFHAsmO 0U, // STOCFHAsmP 0U, // STOCFHAsmZ 0U, // STOCG 128U, // STOCGAsm 0U, // STOCGAsmE 0U, // STOCGAsmH 0U, // STOCGAsmHE 0U, // STOCGAsmL 0U, // STOCGAsmLE 0U, // STOCGAsmLH 0U, // STOCGAsmM 0U, // STOCGAsmNE 0U, // STOCGAsmNH 0U, // STOCGAsmNHE 0U, // STOCGAsmNL 0U, // STOCGAsmNLE 0U, // STOCGAsmNLH 0U, // STOCGAsmNM 0U, // STOCGAsmNO 0U, // STOCGAsmNP 0U, // STOCGAsmNZ 0U, // STOCGAsmO 0U, // STOCGAsmP 0U, // STOCGAsmZ 0U, // STOSM 0U, // STPQ 0U, // STPT 0U, // STPX 0U, // STRAG 0U, // STRL 0U, // STRV 0U, // STRVG 0U, // STRVH 0U, // STSCH 0U, // STSI 0U, // STURA 0U, // STURG 0U, // STY 0U, // SU 0U, // SUR 0U, // SVC 0U, // SW 0U, // SWR 0U, // SXBR 0U, // SXR 0U, // SXTR 512U, // SXTRA 0U, // SY 0U, // TABORT 0U, // TAM 0U, // TAR 0U, // TB 41U, // TBDR 41U, // TBEDR 0U, // TBEGIN 0U, // TBEGINC 0U, // TCDB 0U, // TCEB 0U, // TCXB 0U, // TDCDT 0U, // TDCET 0U, // TDCXT 0U, // TDGDT 0U, // TDGET 0U, // TDGXT 0U, // TEND 0U, // THDER 0U, // THDR 0U, // TM 0U, // TMHH 0U, // TMHL 0U, // TMLH 0U, // TMLL 0U, // TMY 0U, // TP 0U, // TPI 0U, // TPROT 0U, // TR 56U, // TRACE 56U, // TRACG 0U, // TRAP2 0U, // TRAP4 0U, // TRE 104U, // TROO 0U, // TROOOpt 104U, // TROT 0U, // TROTOpt 0U, // TRT 0U, // TRTE 0U, // TRTEOpt 104U, // TRTO 0U, // TRTOOpt 0U, // TRTR 0U, // TRTRE 0U, // TRTREOpt 104U, // TRTT 0U, // TRTTOpt 0U, // TS 0U, // TSCH 0U, // UNPK 0U, // UNPKA 0U, // UNPKU 0U, // UPT 512U, // VA 0U, // VAB 57856U, // VAC 512U, // VACC 0U, // VACCB 57856U, // VACCC 57856U, // VACCCQ 0U, // VACCF 0U, // VACCG 0U, // VACCH 0U, // VACCQ 57856U, // VACQ 0U, // VAF 0U, // VAG 0U, // VAH 512U, // VAP 0U, // VAQ 512U, // VAVG 0U, // VAVGB 0U, // VAVGF 0U, // VAVGG 0U, // VAVGH 512U, // VAVGL 0U, // VAVGLB 0U, // VAVGLF 0U, // VAVGLG 0U, // VAVGLH 0U, // VBPERM 560U, // VCDG 560U, // VCDGB 560U, // VCDLG 560U, // VCDLGB 512U, // VCEQ 0U, // VCEQB 0U, // VCEQBS 0U, // VCEQF 0U, // VCEQFS 0U, // VCEQG 0U, // VCEQGS 0U, // VCEQH 0U, // VCEQHS 560U, // VCGD 560U, // VCGDB 512U, // VCH 0U, // VCHB 0U, // VCHBS 0U, // VCHF 0U, // VCHFS 0U, // VCHG 0U, // VCHGS 0U, // VCHH 0U, // VCHHS 512U, // VCHL 0U, // VCHLB 0U, // VCHLBS 0U, // VCHLF 0U, // VCHLFS 0U, // VCHLG 0U, // VCHLGS 0U, // VCHLH 0U, // VCHLHS 0U, // VCKSM 560U, // VCLGD 560U, // VCLGDB 48U, // VCLZ 0U, // VCLZB 0U, // VCLZF 0U, // VCLZG 0U, // VCLZH 48U, // VCP 48U, // VCTZ 0U, // VCTZB 0U, // VCTZF 0U, // VCTZG 0U, // VCTZH 48U, // VCVB 48U, // VCVBG 10408U, // VCVD 10408U, // VCVDG 512U, // VDP 48U, // VEC 0U, // VECB 0U, // VECF 0U, // VECG 0U, // VECH 48U, // VECL 0U, // VECLB 0U, // VECLF 0U, // VECLG 0U, // VECLH 49776U, // VERIM 49776U, // VERIMB 49776U, // VERIMF 49776U, // VERIMG 49776U, // VERIMH 25144U, // VERLL 56U, // VERLLB 56U, // VERLLF 56U, // VERLLG 56U, // VERLLH 512U, // VERLLV 0U, // VERLLVB 0U, // VERLLVF 0U, // VERLLVG 0U, // VERLLVH 25144U, // VESL 56U, // VESLB 56U, // VESLF 56U, // VESLG 56U, // VESLH 512U, // VESLV 0U, // VESLVB 0U, // VESLVF 0U, // VESLVG 0U, // VESLVH 25144U, // VESRA 56U, // VESRAB 56U, // VESRAF 56U, // VESRAG 56U, // VESRAH 512U, // VESRAV 0U, // VESRAVB 0U, // VESRAVF 0U, // VESRAVG 0U, // VESRAVH 25144U, // VESRL 56U, // VESRLB 56U, // VESRLF 56U, // VESRLG 56U, // VESRLH 512U, // VESRLV 0U, // VESRLVB 0U, // VESRLVF 0U, // VESRLVG 0U, // VESRLVH 512U, // VFA 0U, // VFADB 512U, // VFAE 512U, // VFAEB 512U, // VFAEBS 512U, // VFAEF 512U, // VFAEFS 512U, // VFAEH 512U, // VFAEHS 512U, // VFAEZB 512U, // VFAEZBS 512U, // VFAEZF 512U, // VFAEZFS 512U, // VFAEZH 512U, // VFAEZHS 0U, // VFASB 512U, // VFCE 0U, // VFCEDB 0U, // VFCEDBS 0U, // VFCESB 0U, // VFCESBS 512U, // VFCH 0U, // VFCHDB 0U, // VFCHDBS 512U, // VFCHE 0U, // VFCHEDB 0U, // VFCHEDBS 0U, // VFCHESB 0U, // VFCHESBS 0U, // VFCHSB 0U, // VFCHSBS 512U, // VFD 0U, // VFDDB 0U, // VFDSB 512U, // VFEE 512U, // VFEEB 0U, // VFEEBS 512U, // VFEEF 0U, // VFEEFS 512U, // VFEEH 0U, // VFEEHS 0U, // VFEEZB 0U, // VFEEZBS 0U, // VFEEZF 0U, // VFEEZFS 0U, // VFEEZH 0U, // VFEEZHS 512U, // VFENE 512U, // VFENEB 0U, // VFENEBS 512U, // VFENEF 0U, // VFENEFS 512U, // VFENEH 0U, // VFENEHS 0U, // VFENEZB 0U, // VFENEZBS 0U, // VFENEZF 0U, // VFENEZFS 0U, // VFENEZH 0U, // VFENEZHS 560U, // VFI 560U, // VFIDB 560U, // VFISB 0U, // VFKEDB 0U, // VFKEDBS 0U, // VFKESB 0U, // VFKESBS 0U, // VFKHDB 0U, // VFKHDBS 0U, // VFKHEDB 0U, // VFKHEDBS 0U, // VFKHESB 0U, // VFKHESBS 0U, // VFKHSB 0U, // VFKHSBS 0U, // VFLCDB 0U, // VFLCSB 560U, // VFLL 0U, // VFLLS 0U, // VFLNDB 0U, // VFLNSB 0U, // VFLPDB 0U, // VFLPSB 560U, // VFLR 560U, // VFLRD 512U, // VFM 57856U, // VFMA 57856U, // VFMADB 57856U, // VFMASB 512U, // VFMAX 512U, // VFMAXDB 512U, // VFMAXSB 0U, // VFMDB 512U, // VFMIN 512U, // VFMINDB 512U, // VFMINSB 57856U, // VFMS 0U, // VFMSB 57856U, // VFMSDB 57856U, // VFMSSB 57856U, // VFNMA 57856U, // VFNMADB 57856U, // VFNMASB 57856U, // VFNMS 57856U, // VFNMSDB 57856U, // VFNMSSB 560U, // VFPSO 48U, // VFPSODB 48U, // VFPSOSB 512U, // VFS 0U, // VFSDB 560U, // VFSQ 0U, // VFSQDB 0U, // VFSQSB 0U, // VFSSB 688U, // VFTCI 176U, // VFTCIDB 176U, // VFTCISB 0U, // VGBM 3U, // VGEF 4U, // VGEG 512U, // VGFM 57856U, // VGFMA 57856U, // VGFMAB 57856U, // VGFMAF 57856U, // VGFMAG 57856U, // VGFMAH 0U, // VGFMB 0U, // VGFMF 0U, // VGFMG 0U, // VGFMH 36U, // VGM 44U, // VGMB 44U, // VGMF 44U, // VGMG 44U, // VGMH 560U, // VISTR 48U, // VISTRB 0U, // VISTRBS 48U, // VISTRF 0U, // VISTRFS 48U, // VISTRH 0U, // VISTRHS 0U, // VL 104U, // VLBB 48U, // VLC 0U, // VLCB 0U, // VLCF 0U, // VLCG 0U, // VLCH 560U, // VLDE 0U, // VLDEB 160U, // VLEB 560U, // VLED 560U, // VLEDB 184U, // VLEF 192U, // VLEG 200U, // VLEH 128U, // VLEIB 208U, // VLEIF 216U, // VLEIG 224U, // VLEIH 25144U, // VLGV 56U, // VLGVB 56U, // VLGVF 56U, // VLGVG 56U, // VLGVH 48U, // VLIP 56U, // VLL 104U, // VLLEZ 0U, // VLLEZB 0U, // VLLEZF 0U, // VLLEZG 0U, // VLLEZH 0U, // VLLEZLF 56U, // VLM 48U, // VLP 0U, // VLPB 0U, // VLPF 0U, // VLPG 0U, // VLPH 0U, // VLR 104U, // VLREP 0U, // VLREPB 0U, // VLREPF 0U, // VLREPG 0U, // VLREPH 152U, // VLRL 56U, // VLRLR 16920U, // VLVG 24U, // VLVGB 24U, // VLVGF 24U, // VLVGG 24U, // VLVGH 0U, // VLVGP 57856U, // VMAE 57856U, // VMAEB 57856U, // VMAEF 57856U, // VMAEH 57856U, // VMAH 57856U, // VMAHB 57856U, // VMAHF 57856U, // VMAHH 57856U, // VMAL 57856U, // VMALB 57856U, // VMALE 57856U, // VMALEB 57856U, // VMALEF 57856U, // VMALEH 57856U, // VMALF 57856U, // VMALH 57856U, // VMALHB 57856U, // VMALHF 57856U, // VMALHH 57856U, // VMALHW 57856U, // VMALO 57856U, // VMALOB 57856U, // VMALOF 57856U, // VMALOH 57856U, // VMAO 57856U, // VMAOB 57856U, // VMAOF 57856U, // VMAOH 512U, // VME 0U, // VMEB 0U, // VMEF 0U, // VMEH 512U, // VMH 0U, // VMHB 0U, // VMHF 0U, // VMHH 512U, // VML 0U, // VMLB 512U, // VMLE 0U, // VMLEB 0U, // VMLEF 0U, // VMLEH 0U, // VMLF 512U, // VMLH 0U, // VMLHB 0U, // VMLHF 0U, // VMLHH 0U, // VMLHW 512U, // VMLO 0U, // VMLOB 0U, // VMLOF 0U, // VMLOH 512U, // VMN 0U, // VMNB 0U, // VMNF 0U, // VMNG 0U, // VMNH 512U, // VMNL 0U, // VMNLB 0U, // VMNLF 0U, // VMNLG 0U, // VMNLH 512U, // VMO 0U, // VMOB 0U, // VMOF 0U, // VMOH 512U, // VMP 512U, // VMRH 0U, // VMRHB 0U, // VMRHF 0U, // VMRHG 0U, // VMRHH 512U, // VMRL 0U, // VMRLB 0U, // VMRLF 0U, // VMRLG 0U, // VMRLH 57856U, // VMSL 57856U, // VMSLG 512U, // VMSP 512U, // VMX 0U, // VMXB 0U, // VMXF 0U, // VMXG 0U, // VMXH 512U, // VMXL 0U, // VMXLB 0U, // VMXLF 0U, // VMXLG 0U, // VMXLH 0U, // VN 0U, // VNC 0U, // VNN 0U, // VNO 0U, // VNX 0U, // VO 0U, // VOC 0U, // VONE 512U, // VPDI 57856U, // VPERM 512U, // VPK 0U, // VPKF 0U, // VPKG 0U, // VPKH 512U, // VPKLS 0U, // VPKLSF 0U, // VPKLSFS 0U, // VPKLSG 0U, // VPKLSGS 0U, // VPKLSH 0U, // VPKLSHS 512U, // VPKS 0U, // VPKSF 0U, // VPKSFS 0U, // VPKSG 0U, // VPKSGS 0U, // VPKSH 0U, // VPKSHS 152U, // VPKZ 48U, // VPOPCT 0U, // VPOPCTB 0U, // VPOPCTF 0U, // VPOPCTG 0U, // VPOPCTH 4264U, // VPSOP 744U, // VREP 232U, // VREPB 232U, // VREPF 232U, // VREPG 232U, // VREPH 48U, // VREPI 0U, // VREPIB 0U, // VREPIF 0U, // VREPIG 0U, // VREPIH 512U, // VRP 512U, // VS 0U, // VSB 57856U, // VSBCBI 57856U, // VSBCBIQ 57856U, // VSBI 57856U, // VSBIQ 512U, // VSCBI 0U, // VSCBIB 0U, // VSCBIF 0U, // VSCBIG 0U, // VSCBIH 0U, // VSCBIQ 4U, // VSCEF 4U, // VSCEG 512U, // VSDP 48U, // VSEG 0U, // VSEGB 0U, // VSEGF 0U, // VSEGH 57856U, // VSEL 0U, // VSF 0U, // VSG 0U, // VSH 0U, // VSL 0U, // VSLB 512U, // VSLDB 512U, // VSP 0U, // VSQ 0U, // VSRA 0U, // VSRAB 0U, // VSRL 0U, // VSRLB 4264U, // VSRP 0U, // VST 104U, // VSTEB 240U, // VSTEF 248U, // VSTEG 256U, // VSTEH 56U, // VSTL 56U, // VSTM 57856U, // VSTRC 57856U, // VSTRCB 57856U, // VSTRCBS 57856U, // VSTRCF 57856U, // VSTRCFS 57856U, // VSTRCH 57856U, // VSTRCHS 57856U, // VSTRCZB 57856U, // VSTRCZBS 57856U, // VSTRCZF 57856U, // VSTRCZFS 57856U, // VSTRCZH 57856U, // VSTRCZHS 152U, // VSTRL 56U, // VSTRLR 512U, // VSUM 0U, // VSUMB 512U, // VSUMG 0U, // VSUMGF 0U, // VSUMGH 0U, // VSUMH 512U, // VSUMQ 0U, // VSUMQF 0U, // VSUMQG 0U, // VTM 0U, // VTP 48U, // VUPH 0U, // VUPHB 0U, // VUPHF 0U, // VUPHH 152U, // VUPKZ 48U, // VUPL 0U, // VUPLB 0U, // VUPLF 48U, // VUPLH 0U, // VUPLHB 0U, // VUPLHF 0U, // VUPLHH 0U, // VUPLHW 48U, // VUPLL 0U, // VUPLLB 0U, // VUPLLF 0U, // VUPLLH 0U, // VX 0U, // VZERO 560U, // WCDGB 560U, // WCDLGB 560U, // WCGDB 560U, // WCLGDB 0U, // WFADB 0U, // WFASB 0U, // WFAXB 560U, // WFC 0U, // WFCDB 0U, // WFCEDB 0U, // WFCEDBS 0U, // WFCESB 0U, // WFCESBS 0U, // WFCEXB 0U, // WFCEXBS 0U, // WFCHDB 0U, // WFCHDBS 0U, // WFCHEDB 0U, // WFCHEDBS 0U, // WFCHESB 0U, // WFCHESBS 0U, // WFCHEXB 0U, // WFCHEXBS 0U, // WFCHSB 0U, // WFCHSBS 0U, // WFCHXB 0U, // WFCHXBS 0U, // WFCSB 0U, // WFCXB 0U, // WFDDB 0U, // WFDSB 0U, // WFDXB 560U, // WFIDB 560U, // WFISB 560U, // WFIXB 560U, // WFK 0U, // WFKDB 0U, // WFKEDB 0U, // WFKEDBS 0U, // WFKESB 0U, // WFKESBS 0U, // WFKEXB 0U, // WFKEXBS 0U, // WFKHDB 0U, // WFKHDBS 0U, // WFKHEDB 0U, // WFKHEDBS 0U, // WFKHESB 0U, // WFKHESBS 0U, // WFKHEXB 0U, // WFKHEXBS 0U, // WFKHSB 0U, // WFKHSBS 0U, // WFKHXB 0U, // WFKHXBS 0U, // WFKSB 0U, // WFKXB 0U, // WFLCDB 0U, // WFLCSB 0U, // WFLCXB 0U, // WFLLD 0U, // WFLLS 0U, // WFLNDB 0U, // WFLNSB 0U, // WFLNXB 0U, // WFLPDB 0U, // WFLPSB 0U, // WFLPXB 560U, // WFLRD 560U, // WFLRX 57856U, // WFMADB 57856U, // WFMASB 57856U, // WFMAXB 512U, // WFMAXDB 512U, // WFMAXSB 512U, // WFMAXXB 0U, // WFMDB 512U, // WFMINDB 512U, // WFMINSB 512U, // WFMINXB 0U, // WFMSB 57856U, // WFMSDB 57856U, // WFMSSB 57856U, // WFMSXB 0U, // WFMXB 57856U, // WFNMADB 57856U, // WFNMASB 57856U, // WFNMAXB 57856U, // WFNMSDB 57856U, // WFNMSSB 57856U, // WFNMSXB 48U, // WFPSODB 48U, // WFPSOSB 48U, // WFPSOXB 0U, // WFSDB 0U, // WFSQDB 0U, // WFSQSB 0U, // WFSQXB 0U, // WFSSB 0U, // WFSXB 176U, // WFTCIDB 176U, // WFTCISB 176U, // WFTCIXB 0U, // WLDEB 560U, // WLEDB 0U, // X 0U, // XC 0U, // XG 0U, // XGR 0U, // XGRK 0U, // XI 0U, // XIHF 0U, // XILF 0U, // XIY 0U, // XR 0U, // XRK 0U, // XSCH 0U, // XY 0U, // ZAP }; static const uint8_t OpInfo2[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP 0U, // ADJDYNALLOC 0U, // AEXT128 0U, // AFIMux 0U, // AHIMux 0U, // AHIMuxK 0U, // ATOMIC_CMP_SWAPW 0U, // ATOMIC_LOADW_AFI 0U, // ATOMIC_LOADW_AR 0U, // ATOMIC_LOADW_MAX 0U, // ATOMIC_LOADW_MIN 0U, // ATOMIC_LOADW_NILH 0U, // ATOMIC_LOADW_NILHi 0U, // ATOMIC_LOADW_NR 0U, // ATOMIC_LOADW_NRi 0U, // ATOMIC_LOADW_OILH 0U, // ATOMIC_LOADW_OR 0U, // ATOMIC_LOADW_SR 0U, // ATOMIC_LOADW_UMAX 0U, // ATOMIC_LOADW_UMIN 0U, // ATOMIC_LOADW_XILF 0U, // ATOMIC_LOADW_XR 0U, // ATOMIC_LOAD_AFI 0U, // ATOMIC_LOAD_AGFI 0U, // ATOMIC_LOAD_AGHI 0U, // ATOMIC_LOAD_AGR 0U, // ATOMIC_LOAD_AHI 0U, // ATOMIC_LOAD_AR 0U, // ATOMIC_LOAD_MAX_32 0U, // ATOMIC_LOAD_MAX_64 0U, // ATOMIC_LOAD_MIN_32 0U, // ATOMIC_LOAD_MIN_64 0U, // ATOMIC_LOAD_NGR 0U, // ATOMIC_LOAD_NGRi 0U, // ATOMIC_LOAD_NIHF64 0U, // ATOMIC_LOAD_NIHF64i 0U, // ATOMIC_LOAD_NIHH64 0U, // ATOMIC_LOAD_NIHH64i 0U, // ATOMIC_LOAD_NIHL64 0U, // ATOMIC_LOAD_NIHL64i 0U, // ATOMIC_LOAD_NILF 0U, // ATOMIC_LOAD_NILF64 0U, // ATOMIC_LOAD_NILF64i 0U, // ATOMIC_LOAD_NILFi 0U, // ATOMIC_LOAD_NILH 0U, // ATOMIC_LOAD_NILH64 0U, // ATOMIC_LOAD_NILH64i 0U, // ATOMIC_LOAD_NILHi 0U, // ATOMIC_LOAD_NILL 0U, // ATOMIC_LOAD_NILL64 0U, // ATOMIC_LOAD_NILL64i 0U, // ATOMIC_LOAD_NILLi 0U, // ATOMIC_LOAD_NR 0U, // ATOMIC_LOAD_NRi 0U, // ATOMIC_LOAD_OGR 0U, // ATOMIC_LOAD_OIHF64 0U, // ATOMIC_LOAD_OIHH64 0U, // ATOMIC_LOAD_OIHL64 0U, // ATOMIC_LOAD_OILF 0U, // ATOMIC_LOAD_OILF64 0U, // ATOMIC_LOAD_OILH 0U, // ATOMIC_LOAD_OILH64 0U, // ATOMIC_LOAD_OILL 0U, // ATOMIC_LOAD_OILL64 0U, // ATOMIC_LOAD_OR 0U, // ATOMIC_LOAD_SGR 0U, // ATOMIC_LOAD_SR 0U, // ATOMIC_LOAD_UMAX_32 0U, // ATOMIC_LOAD_UMAX_64 0U, // ATOMIC_LOAD_UMIN_32 0U, // ATOMIC_LOAD_UMIN_64 0U, // ATOMIC_LOAD_XGR 0U, // ATOMIC_LOAD_XIHF64 0U, // ATOMIC_LOAD_XILF 0U, // ATOMIC_LOAD_XILF64 0U, // ATOMIC_LOAD_XR 0U, // ATOMIC_SWAPW 0U, // ATOMIC_SWAP_32 0U, // ATOMIC_SWAP_64 0U, // CFIMux 0U, // CGIBCall 0U, // CGIBReturn 0U, // CGRBCall 0U, // CGRBReturn 0U, // CHIMux 0U, // CIBCall 0U, // CIBReturn 0U, // CLCLoop 0U, // CLCSequence 0U, // CLFIMux 0U, // CLGIBCall 0U, // CLGIBReturn 0U, // CLGRBCall 0U, // CLGRBReturn 0U, // CLIBCall 0U, // CLIBReturn 0U, // CLMux 0U, // CLRBCall 0U, // CLRBReturn 0U, // CLSTLoop 0U, // CMux 0U, // CRBCall 0U, // CRBReturn 0U, // CallBASR 0U, // CallBCR 0U, // CallBR 0U, // CallBRASL 0U, // CallBRCL 0U, // CallJG 0U, // CondReturn 0U, // CondStore16 0U, // CondStore16Inv 0U, // CondStore16Mux 0U, // CondStore16MuxInv 0U, // CondStore32 0U, // CondStore32Inv 0U, // CondStore32Mux 0U, // CondStore32MuxInv 0U, // CondStore64 0U, // CondStore64Inv 0U, // CondStore8 0U, // CondStore8Inv 0U, // CondStore8Mux 0U, // CondStore8MuxInv 0U, // CondStoreF32 0U, // CondStoreF32Inv 0U, // CondStoreF64 0U, // CondStoreF64Inv 0U, // CondTrap 0U, // GOT 0U, // IIFMux 0U, // IIHF64 0U, // IIHH64 0U, // IIHL64 0U, // IIHMux 0U, // IILF64 0U, // IILH64 0U, // IILL64 0U, // IILMux 0U, // L128 0U, // LBMux 0U, // LEFR 0U, // LFER 0U, // LHIMux 0U, // LHMux 0U, // LLCMux 0U, // LLCRMux 0U, // LLHMux 0U, // LLHRMux 0U, // LMux 0U, // LOCHIMux 0U, // LOCMux 0U, // LOCRMux 0U, // LRMux 0U, // LTDBRCompare_VecPseudo 0U, // LTEBRCompare_VecPseudo 0U, // LTXBRCompare_VecPseudo 0U, // LX 0U, // MVCLoop 0U, // MVCSequence 0U, // MVSTLoop 0U, // MemBarrier 0U, // NCLoop 0U, // NCSequence 0U, // NIFMux 0U, // NIHF64 0U, // NIHH64 0U, // NIHL64 0U, // NIHMux 0U, // NILF64 0U, // NILH64 0U, // NILL64 0U, // NILMux 0U, // OCLoop 0U, // OCSequence 0U, // OIFMux 0U, // OIHF64 0U, // OIHH64 0U, // OIHL64 0U, // OIHMux 0U, // OILF64 0U, // OILH64 0U, // OILL64 0U, // OILMux 0U, // PAIR128 0U, // RISBHH 0U, // RISBHL 0U, // RISBLH 0U, // RISBLL 0U, // RISBMux 0U, // Return 0U, // SRSTLoop 0U, // ST128 0U, // STCMux 0U, // STHMux 0U, // STMux 0U, // STOCMux 0U, // STX 0U, // Select32 0U, // Select64 0U, // SelectF128 0U, // SelectF32 0U, // SelectF64 0U, // SelectVR128 0U, // SelectVR32 0U, // SelectVR64 0U, // Serialize 0U, // TBEGIN_nofloat 0U, // TLS_GDCALL 0U, // TLS_LDCALL 0U, // TMHH64 0U, // TMHL64 0U, // TMHMux 0U, // TMLH64 0U, // TMLL64 0U, // TMLMux 0U, // Trap 0U, // VL32 0U, // VL64 0U, // VLR32 0U, // VLR64 0U, // VLVGP32 0U, // VST32 0U, // VST64 0U, // XCLoop 0U, // XCSequence 0U, // XIFMux 0U, // XIHF64 0U, // XILF64 0U, // ZEXT128 0U, // A 0U, // AD 0U, // ADB 0U, // ADBR 0U, // ADR 0U, // ADTR 0U, // ADTRA 0U, // AE 0U, // AEB 0U, // AEBR 0U, // AER 0U, // AFI 0U, // AG 0U, // AGF 0U, // AGFI 0U, // AGFR 0U, // AGH 0U, // AGHI 0U, // AGHIK 0U, // AGR 0U, // AGRK 0U, // AGSI 0U, // AH 0U, // AHHHR 0U, // AHHLR 0U, // AHI 0U, // AHIK 0U, // AHY 0U, // AIH 0U, // AL 0U, // ALC 0U, // ALCG 0U, // ALCGR 0U, // ALCR 0U, // ALFI 0U, // ALG 0U, // ALGF 0U, // ALGFI 0U, // ALGFR 0U, // ALGHSIK 0U, // ALGR 0U, // ALGRK 0U, // ALGSI 0U, // ALHHHR 0U, // ALHHLR 0U, // ALHSIK 0U, // ALR 0U, // ALRK 0U, // ALSI 0U, // ALSIH 0U, // ALSIHN 0U, // ALY 0U, // AP 0U, // AR 0U, // ARK 0U, // ASI 0U, // AU 0U, // AUR 0U, // AW 0U, // AWR 0U, // AXBR 0U, // AXR 0U, // AXTR 0U, // AXTRA 0U, // AY 0U, // B 0U, // BAKR 0U, // BAL 0U, // BALR 0U, // BAS 0U, // BASR 0U, // BASSM 0U, // BAsmE 0U, // BAsmH 0U, // BAsmHE 0U, // BAsmL 0U, // BAsmLE 0U, // BAsmLH 0U, // BAsmM 0U, // BAsmNE 0U, // BAsmNH 0U, // BAsmNHE 0U, // BAsmNL 0U, // BAsmNLE 0U, // BAsmNLH 0U, // BAsmNM 0U, // BAsmNO 0U, // BAsmNP 0U, // BAsmNZ 0U, // BAsmO 0U, // BAsmP 0U, // BAsmZ 0U, // BC 0U, // BCAsm 0U, // BCR 0U, // BCRAsm 0U, // BCT 0U, // BCTG 0U, // BCTGR 0U, // BCTR 0U, // BI 0U, // BIAsmE 0U, // BIAsmH 0U, // BIAsmHE 0U, // BIAsmL 0U, // BIAsmLE 0U, // BIAsmLH 0U, // BIAsmM 0U, // BIAsmNE 0U, // BIAsmNH 0U, // BIAsmNHE 0U, // BIAsmNL 0U, // BIAsmNLE 0U, // BIAsmNLH 0U, // BIAsmNM 0U, // BIAsmNO 0U, // BIAsmNP 0U, // BIAsmNZ 0U, // BIAsmO 0U, // BIAsmP 0U, // BIAsmZ 0U, // BIC 0U, // BICAsm 0U, // BPP 0U, // BPRP 0U, // BR 0U, // BRAS 0U, // BRASL 0U, // BRAsmE 0U, // BRAsmH 0U, // BRAsmHE 0U, // BRAsmL 0U, // BRAsmLE 0U, // BRAsmLH 0U, // BRAsmM 0U, // BRAsmNE 0U, // BRAsmNH 0U, // BRAsmNHE 0U, // BRAsmNL 0U, // BRAsmNLE 0U, // BRAsmNLH 0U, // BRAsmNM 0U, // BRAsmNO 0U, // BRAsmNP 0U, // BRAsmNZ 0U, // BRAsmO 0U, // BRAsmP 0U, // BRAsmZ 0U, // BRC 0U, // BRCAsm 0U, // BRCL 0U, // BRCLAsm 0U, // BRCT 0U, // BRCTG 0U, // BRCTH 0U, // BRXH 0U, // BRXHG 0U, // BRXLE 0U, // BRXLG 0U, // BSA 0U, // BSG 0U, // BSM 0U, // BXH 0U, // BXHG 0U, // BXLE 0U, // BXLEG 0U, // C 0U, // CD 0U, // CDB 0U, // CDBR 0U, // CDFBR 0U, // CDFBRA 0U, // CDFR 0U, // CDFTR 0U, // CDGBR 0U, // CDGBRA 0U, // CDGR 0U, // CDGTR 0U, // CDGTRA 0U, // CDLFBR 0U, // CDLFTR 0U, // CDLGBR 0U, // CDLGTR 0U, // CDPT 0U, // CDR 0U, // CDS 0U, // CDSG 0U, // CDSTR 0U, // CDSY 0U, // CDTR 0U, // CDUTR 0U, // CDZT 0U, // CE 0U, // CEB 0U, // CEBR 0U, // CEDTR 0U, // CEFBR 0U, // CEFBRA 0U, // CEFR 0U, // CEGBR 0U, // CEGBRA 0U, // CEGR 0U, // CELFBR 0U, // CELGBR 0U, // CER 0U, // CEXTR 0U, // CFC 0U, // CFDBR 0U, // CFDBRA 0U, // CFDR 0U, // CFDTR 0U, // CFEBR 0U, // CFEBRA 0U, // CFER 0U, // CFI 0U, // CFXBR 0U, // CFXBRA 0U, // CFXR 0U, // CFXTR 0U, // CG 0U, // CGDBR 0U, // CGDBRA 0U, // CGDR 0U, // CGDTR 0U, // CGDTRA 0U, // CGEBR 0U, // CGEBRA 0U, // CGER 0U, // CGF 0U, // CGFI 0U, // CGFR 0U, // CGFRL 0U, // CGH 0U, // CGHI 0U, // CGHRL 0U, // CGHSI 0U, // CGIB 0U, // CGIBAsm 0U, // CGIBAsmE 0U, // CGIBAsmH 0U, // CGIBAsmHE 0U, // CGIBAsmL 0U, // CGIBAsmLE 0U, // CGIBAsmLH 0U, // CGIBAsmNE 0U, // CGIBAsmNH 0U, // CGIBAsmNHE 0U, // CGIBAsmNL 0U, // CGIBAsmNLE 0U, // CGIBAsmNLH 0U, // CGIJ 0U, // CGIJAsm 0U, // CGIJAsmE 0U, // CGIJAsmH 0U, // CGIJAsmHE 0U, // CGIJAsmL 0U, // CGIJAsmLE 0U, // CGIJAsmLH 0U, // CGIJAsmNE 0U, // CGIJAsmNH 0U, // CGIJAsmNHE 0U, // CGIJAsmNL 0U, // CGIJAsmNLE 0U, // CGIJAsmNLH 0U, // CGIT 0U, // CGITAsm 0U, // CGITAsmE 0U, // CGITAsmH 0U, // CGITAsmHE 0U, // CGITAsmL 0U, // CGITAsmLE 0U, // CGITAsmLH 0U, // CGITAsmNE 0U, // CGITAsmNH 0U, // CGITAsmNHE 0U, // CGITAsmNL 0U, // CGITAsmNLE 0U, // CGITAsmNLH 0U, // CGR 0U, // CGRB 0U, // CGRBAsm 0U, // CGRBAsmE 0U, // CGRBAsmH 0U, // CGRBAsmHE 0U, // CGRBAsmL 0U, // CGRBAsmLE 0U, // CGRBAsmLH 0U, // CGRBAsmNE 0U, // CGRBAsmNH 0U, // CGRBAsmNHE 0U, // CGRBAsmNL 0U, // CGRBAsmNLE 0U, // CGRBAsmNLH 0U, // CGRJ 0U, // CGRJAsm 0U, // CGRJAsmE 0U, // CGRJAsmH 0U, // CGRJAsmHE 0U, // CGRJAsmL 0U, // CGRJAsmLE 0U, // CGRJAsmLH 0U, // CGRJAsmNE 0U, // CGRJAsmNH 0U, // CGRJAsmNHE 0U, // CGRJAsmNL 0U, // CGRJAsmNLE 0U, // CGRJAsmNLH 0U, // CGRL 0U, // CGRT 0U, // CGRTAsm 0U, // CGRTAsmE 0U, // CGRTAsmH 0U, // CGRTAsmHE 0U, // CGRTAsmL 0U, // CGRTAsmLE 0U, // CGRTAsmLH 0U, // CGRTAsmNE 0U, // CGRTAsmNH 0U, // CGRTAsmNHE 0U, // CGRTAsmNL 0U, // CGRTAsmNLE 0U, // CGRTAsmNLH 0U, // CGXBR 0U, // CGXBRA 0U, // CGXR 0U, // CGXTR 0U, // CGXTRA 0U, // CH 0U, // CHF 0U, // CHHR 0U, // CHHSI 0U, // CHI 0U, // CHLR 0U, // CHRL 0U, // CHSI 0U, // CHY 0U, // CIB 0U, // CIBAsm 0U, // CIBAsmE 0U, // CIBAsmH 0U, // CIBAsmHE 0U, // CIBAsmL 0U, // CIBAsmLE 0U, // CIBAsmLH 0U, // CIBAsmNE 0U, // CIBAsmNH 0U, // CIBAsmNHE 0U, // CIBAsmNL 0U, // CIBAsmNLE 0U, // CIBAsmNLH 0U, // CIH 0U, // CIJ 0U, // CIJAsm 0U, // CIJAsmE 0U, // CIJAsmH 0U, // CIJAsmHE 0U, // CIJAsmL 0U, // CIJAsmLE 0U, // CIJAsmLH 0U, // CIJAsmNE 0U, // CIJAsmNH 0U, // CIJAsmNHE 0U, // CIJAsmNL 0U, // CIJAsmNLE 0U, // CIJAsmNLH 0U, // CIT 0U, // CITAsm 0U, // CITAsmE 0U, // CITAsmH 0U, // CITAsmHE 0U, // CITAsmL 0U, // CITAsmLE 0U, // CITAsmLH 0U, // CITAsmNE 0U, // CITAsmNH 0U, // CITAsmNHE 0U, // CITAsmNL 0U, // CITAsmNLE 0U, // CITAsmNLH 0U, // CKSM 0U, // CL 0U, // CLC 0U, // CLCL 0U, // CLCLE 0U, // CLCLU 0U, // CLFDBR 0U, // CLFDTR 0U, // CLFEBR 0U, // CLFHSI 0U, // CLFI 0U, // CLFIT 0U, // CLFITAsm 0U, // CLFITAsmE 0U, // CLFITAsmH 0U, // CLFITAsmHE 0U, // CLFITAsmL 0U, // CLFITAsmLE 0U, // CLFITAsmLH 0U, // CLFITAsmNE 0U, // CLFITAsmNH 0U, // CLFITAsmNHE 0U, // CLFITAsmNL 0U, // CLFITAsmNLE 0U, // CLFITAsmNLH 0U, // CLFXBR 0U, // CLFXTR 0U, // CLG 0U, // CLGDBR 0U, // CLGDTR 0U, // CLGEBR 0U, // CLGF 0U, // CLGFI 0U, // CLGFR 0U, // CLGFRL 0U, // CLGHRL 0U, // CLGHSI 0U, // CLGIB 0U, // CLGIBAsm 0U, // CLGIBAsmE 0U, // CLGIBAsmH 0U, // CLGIBAsmHE 0U, // CLGIBAsmL 0U, // CLGIBAsmLE 0U, // CLGIBAsmLH 0U, // CLGIBAsmNE 0U, // CLGIBAsmNH 0U, // CLGIBAsmNHE 0U, // CLGIBAsmNL 0U, // CLGIBAsmNLE 0U, // CLGIBAsmNLH 0U, // CLGIJ 0U, // CLGIJAsm 0U, // CLGIJAsmE 0U, // CLGIJAsmH 0U, // CLGIJAsmHE 0U, // CLGIJAsmL 0U, // CLGIJAsmLE 0U, // CLGIJAsmLH 0U, // CLGIJAsmNE 0U, // CLGIJAsmNH 0U, // CLGIJAsmNHE 0U, // CLGIJAsmNL 0U, // CLGIJAsmNLE 0U, // CLGIJAsmNLH 0U, // CLGIT 0U, // CLGITAsm 0U, // CLGITAsmE 0U, // CLGITAsmH 0U, // CLGITAsmHE 0U, // CLGITAsmL 0U, // CLGITAsmLE 0U, // CLGITAsmLH 0U, // CLGITAsmNE 0U, // CLGITAsmNH 0U, // CLGITAsmNHE 0U, // CLGITAsmNL 0U, // CLGITAsmNLE 0U, // CLGITAsmNLH 0U, // CLGR 0U, // CLGRB 0U, // CLGRBAsm 0U, // CLGRBAsmE 0U, // CLGRBAsmH 0U, // CLGRBAsmHE 0U, // CLGRBAsmL 0U, // CLGRBAsmLE 0U, // CLGRBAsmLH 0U, // CLGRBAsmNE 0U, // CLGRBAsmNH 0U, // CLGRBAsmNHE 0U, // CLGRBAsmNL 0U, // CLGRBAsmNLE 0U, // CLGRBAsmNLH 0U, // CLGRJ 0U, // CLGRJAsm 0U, // CLGRJAsmE 0U, // CLGRJAsmH 0U, // CLGRJAsmHE 0U, // CLGRJAsmL 0U, // CLGRJAsmLE 0U, // CLGRJAsmLH 0U, // CLGRJAsmNE 0U, // CLGRJAsmNH 0U, // CLGRJAsmNHE 0U, // CLGRJAsmNL 0U, // CLGRJAsmNLE 0U, // CLGRJAsmNLH 0U, // CLGRL 0U, // CLGRT 0U, // CLGRTAsm 0U, // CLGRTAsmE 0U, // CLGRTAsmH 0U, // CLGRTAsmHE 0U, // CLGRTAsmL 0U, // CLGRTAsmLE 0U, // CLGRTAsmLH 0U, // CLGRTAsmNE 0U, // CLGRTAsmNH 0U, // CLGRTAsmNHE 0U, // CLGRTAsmNL 0U, // CLGRTAsmNLE 0U, // CLGRTAsmNLH 0U, // CLGT 0U, // CLGTAsm 0U, // CLGTAsmE 0U, // CLGTAsmH 0U, // CLGTAsmHE 0U, // CLGTAsmL 0U, // CLGTAsmLE 0U, // CLGTAsmLH 0U, // CLGTAsmNE 0U, // CLGTAsmNH 0U, // CLGTAsmNHE 0U, // CLGTAsmNL 0U, // CLGTAsmNLE 0U, // CLGTAsmNLH 0U, // CLGXBR 0U, // CLGXTR 0U, // CLHF 0U, // CLHHR 0U, // CLHHSI 0U, // CLHLR 0U, // CLHRL 0U, // CLI 0U, // CLIB 0U, // CLIBAsm 0U, // CLIBAsmE 0U, // CLIBAsmH 0U, // CLIBAsmHE 0U, // CLIBAsmL 0U, // CLIBAsmLE 0U, // CLIBAsmLH 0U, // CLIBAsmNE 0U, // CLIBAsmNH 0U, // CLIBAsmNHE 0U, // CLIBAsmNL 0U, // CLIBAsmNLE 0U, // CLIBAsmNLH 0U, // CLIH 0U, // CLIJ 0U, // CLIJAsm 0U, // CLIJAsmE 0U, // CLIJAsmH 0U, // CLIJAsmHE 0U, // CLIJAsmL 0U, // CLIJAsmLE 0U, // CLIJAsmLH 0U, // CLIJAsmNE 0U, // CLIJAsmNH 0U, // CLIJAsmNHE 0U, // CLIJAsmNL 0U, // CLIJAsmNLE 0U, // CLIJAsmNLH 0U, // CLIY 0U, // CLM 0U, // CLMH 0U, // CLMY 0U, // CLR 0U, // CLRB 0U, // CLRBAsm 0U, // CLRBAsmE 0U, // CLRBAsmH 0U, // CLRBAsmHE 0U, // CLRBAsmL 0U, // CLRBAsmLE 0U, // CLRBAsmLH 0U, // CLRBAsmNE 0U, // CLRBAsmNH 0U, // CLRBAsmNHE 0U, // CLRBAsmNL 0U, // CLRBAsmNLE 0U, // CLRBAsmNLH 0U, // CLRJ 0U, // CLRJAsm 0U, // CLRJAsmE 0U, // CLRJAsmH 0U, // CLRJAsmHE 0U, // CLRJAsmL 0U, // CLRJAsmLE 0U, // CLRJAsmLH 0U, // CLRJAsmNE 0U, // CLRJAsmNH 0U, // CLRJAsmNHE 0U, // CLRJAsmNL 0U, // CLRJAsmNLE 0U, // CLRJAsmNLH 0U, // CLRL 0U, // CLRT 0U, // CLRTAsm 0U, // CLRTAsmE 0U, // CLRTAsmH 0U, // CLRTAsmHE 0U, // CLRTAsmL 0U, // CLRTAsmLE 0U, // CLRTAsmLH 0U, // CLRTAsmNE 0U, // CLRTAsmNH 0U, // CLRTAsmNHE 0U, // CLRTAsmNL 0U, // CLRTAsmNLE 0U, // CLRTAsmNLH 0U, // CLST 0U, // CLT 0U, // CLTAsm 0U, // CLTAsmE 0U, // CLTAsmH 0U, // CLTAsmHE 0U, // CLTAsmL 0U, // CLTAsmLE 0U, // CLTAsmLH 0U, // CLTAsmNE 0U, // CLTAsmNH 0U, // CLTAsmNHE 0U, // CLTAsmNL 0U, // CLTAsmNLE 0U, // CLTAsmNLH 0U, // CLY 0U, // CMPSC 0U, // CP 0U, // CPDT 0U, // CPSDRdd 0U, // CPSDRds 0U, // CPSDRsd 0U, // CPSDRss 0U, // CPXT 0U, // CPYA 0U, // CR 0U, // CRB 0U, // CRBAsm 0U, // CRBAsmE 0U, // CRBAsmH 0U, // CRBAsmHE 0U, // CRBAsmL 0U, // CRBAsmLE 0U, // CRBAsmLH 0U, // CRBAsmNE 0U, // CRBAsmNH 0U, // CRBAsmNHE 0U, // CRBAsmNL 0U, // CRBAsmNLE 0U, // CRBAsmNLH 0U, // CRDTE 0U, // CRDTEOpt 0U, // CRJ 0U, // CRJAsm 0U, // CRJAsmE 0U, // CRJAsmH 0U, // CRJAsmHE 0U, // CRJAsmL 0U, // CRJAsmLE 0U, // CRJAsmLH 0U, // CRJAsmNE 0U, // CRJAsmNH 0U, // CRJAsmNHE 0U, // CRJAsmNL 0U, // CRJAsmNLE 0U, // CRJAsmNLH 0U, // CRL 0U, // CRT 0U, // CRTAsm 0U, // CRTAsmE 0U, // CRTAsmH 0U, // CRTAsmHE 0U, // CRTAsmL 0U, // CRTAsmLE 0U, // CRTAsmLH 0U, // CRTAsmNE 0U, // CRTAsmNH 0U, // CRTAsmNHE 0U, // CRTAsmNL 0U, // CRTAsmNLE 0U, // CRTAsmNLH 0U, // CS 0U, // CSCH 0U, // CSDTR 0U, // CSG 0U, // CSP 0U, // CSPG 0U, // CSST 0U, // CSXTR 0U, // CSY 0U, // CU12 0U, // CU12Opt 0U, // CU14 0U, // CU14Opt 0U, // CU21 0U, // CU21Opt 0U, // CU24 0U, // CU24Opt 0U, // CU41 0U, // CU42 0U, // CUDTR 0U, // CUSE 0U, // CUTFU 0U, // CUTFUOpt 0U, // CUUTF 0U, // CUUTFOpt 0U, // CUXTR 0U, // CVB 0U, // CVBG 0U, // CVBY 0U, // CVD 0U, // CVDG 0U, // CVDY 0U, // CXBR 0U, // CXFBR 0U, // CXFBRA 0U, // CXFR 0U, // CXFTR 0U, // CXGBR 0U, // CXGBRA 0U, // CXGR 0U, // CXGTR 0U, // CXGTRA 0U, // CXLFBR 0U, // CXLFTR 0U, // CXLGBR 0U, // CXLGTR 0U, // CXPT 0U, // CXR 0U, // CXSTR 0U, // CXTR 0U, // CXUTR 0U, // CXZT 0U, // CY 0U, // CZDT 0U, // CZXT 0U, // D 0U, // DD 0U, // DDB 0U, // DDBR 0U, // DDR 0U, // DDTR 0U, // DDTRA 0U, // DE 0U, // DEB 0U, // DEBR 0U, // DER 0U, // DIAG 0U, // DIDBR 0U, // DIEBR 0U, // DL 0U, // DLG 0U, // DLGR 0U, // DLR 0U, // DP 0U, // DR 0U, // DSG 0U, // DSGF 0U, // DSGFR 0U, // DSGR 0U, // DXBR 0U, // DXR 0U, // DXTR 0U, // DXTRA 0U, // EAR 0U, // ECAG 0U, // ECCTR 0U, // ECPGA 0U, // ECTG 0U, // ED 0U, // EDMK 0U, // EEDTR 0U, // EEXTR 0U, // EFPC 0U, // EPAIR 0U, // EPAR 0U, // EPCTR 0U, // EPSW 0U, // EREG 0U, // EREGG 0U, // ESAIR 0U, // ESAR 0U, // ESDTR 0U, // ESEA 0U, // ESTA 0U, // ESXTR 0U, // ETND 0U, // EX 0U, // EXRL 0U, // FIDBR 0U, // FIDBRA 0U, // FIDR 0U, // FIDTR 0U, // FIEBR 0U, // FIEBRA 0U, // FIER 0U, // FIXBR 0U, // FIXBRA 0U, // FIXR 0U, // FIXTR 0U, // FLOGR 0U, // HDR 0U, // HER 0U, // HSCH 0U, // IAC 0U, // IC 0U, // IC32 0U, // IC32Y 0U, // ICM 0U, // ICMH 0U, // ICMY 0U, // ICY 0U, // IDTE 0U, // IDTEOpt 0U, // IEDTR 0U, // IEXTR 0U, // IIHF 0U, // IIHH 0U, // IIHL 0U, // IILF 0U, // IILH 0U, // IILL 0U, // IPK 0U, // IPM 0U, // IPTE 0U, // IPTEOpt 0U, // IPTEOptOpt 0U, // IRBM 0U, // ISKE 0U, // IVSK 0U, // InsnE 0U, // InsnRI 0U, // InsnRIE 0U, // InsnRIL 0U, // InsnRILU 0U, // InsnRIS 0U, // InsnRR 0U, // InsnRRE 0U, // InsnRRF 0U, // InsnRRS 0U, // InsnRS 0U, // InsnRSE 0U, // InsnRSI 0U, // InsnRSY 0U, // InsnRX 0U, // InsnRXE 0U, // InsnRXF 0U, // InsnRXY 0U, // InsnS 0U, // InsnSI 0U, // InsnSIL 0U, // InsnSIY 0U, // InsnSS 0U, // InsnSSE 0U, // InsnSSF 0U, // J 0U, // JAsmE 0U, // JAsmH 0U, // JAsmHE 0U, // JAsmL 0U, // JAsmLE 0U, // JAsmLH 0U, // JAsmM 0U, // JAsmNE 0U, // JAsmNH 0U, // JAsmNHE 0U, // JAsmNL 0U, // JAsmNLE 0U, // JAsmNLH 0U, // JAsmNM 0U, // JAsmNO 0U, // JAsmNP 0U, // JAsmNZ 0U, // JAsmO 0U, // JAsmP 0U, // JAsmZ 0U, // JG 0U, // JGAsmE 0U, // JGAsmH 0U, // JGAsmHE 0U, // JGAsmL 0U, // JGAsmLE 0U, // JGAsmLH 0U, // JGAsmM 0U, // JGAsmNE 0U, // JGAsmNH 0U, // JGAsmNHE 0U, // JGAsmNL 0U, // JGAsmNLE 0U, // JGAsmNLH 0U, // JGAsmNM 0U, // JGAsmNO 0U, // JGAsmNP 0U, // JGAsmNZ 0U, // JGAsmO 0U, // JGAsmP 0U, // JGAsmZ 0U, // KDB 0U, // KDBR 0U, // KDTR 0U, // KEB 0U, // KEBR 0U, // KIMD 0U, // KLMD 0U, // KM 0U, // KMA 0U, // KMAC 0U, // KMC 0U, // KMCTR 0U, // KMF 0U, // KMO 0U, // KXBR 0U, // KXTR 0U, // L 0U, // LA 0U, // LAA 0U, // LAAG 0U, // LAAL 0U, // LAALG 0U, // LAE 0U, // LAEY 0U, // LAM 0U, // LAMY 0U, // LAN 0U, // LANG 0U, // LAO 0U, // LAOG 0U, // LARL 0U, // LASP 0U, // LAT 0U, // LAX 0U, // LAXG 0U, // LAY 0U, // LB 0U, // LBH 0U, // LBR 0U, // LCBB 0U, // LCCTL 0U, // LCDBR 0U, // LCDFR 0U, // LCDFR_32 0U, // LCDR 0U, // LCEBR 0U, // LCER 0U, // LCGFR 0U, // LCGR 0U, // LCR 0U, // LCTL 0U, // LCTLG 0U, // LCXBR 0U, // LCXR 0U, // LD 0U, // LDE 0U, // LDE32 0U, // LDEB 0U, // LDEBR 0U, // LDER 0U, // LDETR 0U, // LDGR 0U, // LDR 0U, // LDR32 0U, // LDXBR 0U, // LDXBRA 0U, // LDXR 0U, // LDXTR 0U, // LDY 0U, // LE 0U, // LEDBR 0U, // LEDBRA 0U, // LEDR 0U, // LEDTR 0U, // LER 0U, // LEXBR 0U, // LEXBRA 0U, // LEXR 0U, // LEY 0U, // LFAS 0U, // LFH 0U, // LFHAT 0U, // LFPC 0U, // LG 0U, // LGAT 0U, // LGB 0U, // LGBR 0U, // LGDR 0U, // LGF 0U, // LGFI 0U, // LGFR 0U, // LGFRL 0U, // LGG 0U, // LGH 0U, // LGHI 0U, // LGHR 0U, // LGHRL 0U, // LGR 0U, // LGRL 0U, // LGSC 0U, // LH 0U, // LHH 0U, // LHI 0U, // LHR 0U, // LHRL 0U, // LHY 0U, // LLC 0U, // LLCH 0U, // LLCR 0U, // LLGC 0U, // LLGCR 0U, // LLGF 0U, // LLGFAT 0U, // LLGFR 0U, // LLGFRL 0U, // LLGFSG 0U, // LLGH 0U, // LLGHR 0U, // LLGHRL 0U, // LLGT 0U, // LLGTAT 0U, // LLGTR 0U, // LLH 0U, // LLHH 0U, // LLHR 0U, // LLHRL 0U, // LLIHF 0U, // LLIHH 0U, // LLIHL 0U, // LLILF 0U, // LLILH 0U, // LLILL 0U, // LLZRGF 0U, // LM 0U, // LMD 0U, // LMG 0U, // LMH 0U, // LMY 0U, // LNDBR 0U, // LNDFR 0U, // LNDFR_32 0U, // LNDR 0U, // LNEBR 0U, // LNER 0U, // LNGFR 0U, // LNGR 0U, // LNR 0U, // LNXBR 0U, // LNXR 0U, // LOC 0U, // LOCAsm 0U, // LOCAsmE 0U, // LOCAsmH 0U, // LOCAsmHE 0U, // LOCAsmL 0U, // LOCAsmLE 0U, // LOCAsmLH 0U, // LOCAsmM 0U, // LOCAsmNE 0U, // LOCAsmNH 0U, // LOCAsmNHE 0U, // LOCAsmNL 0U, // LOCAsmNLE 0U, // LOCAsmNLH 0U, // LOCAsmNM 0U, // LOCAsmNO 0U, // LOCAsmNP 0U, // LOCAsmNZ 0U, // LOCAsmO 0U, // LOCAsmP 0U, // LOCAsmZ 0U, // LOCFH 0U, // LOCFHAsm 0U, // LOCFHAsmE 0U, // LOCFHAsmH 0U, // LOCFHAsmHE 0U, // LOCFHAsmL 0U, // LOCFHAsmLE 0U, // LOCFHAsmLH 0U, // LOCFHAsmM 0U, // LOCFHAsmNE 0U, // LOCFHAsmNH 0U, // LOCFHAsmNHE 0U, // LOCFHAsmNL 0U, // LOCFHAsmNLE 0U, // LOCFHAsmNLH 0U, // LOCFHAsmNM 0U, // LOCFHAsmNO 0U, // LOCFHAsmNP 0U, // LOCFHAsmNZ 0U, // LOCFHAsmO 0U, // LOCFHAsmP 0U, // LOCFHAsmZ 0U, // LOCFHR 0U, // LOCFHRAsm 0U, // LOCFHRAsmE 0U, // LOCFHRAsmH 0U, // LOCFHRAsmHE 0U, // LOCFHRAsmL 0U, // LOCFHRAsmLE 0U, // LOCFHRAsmLH 0U, // LOCFHRAsmM 0U, // LOCFHRAsmNE 0U, // LOCFHRAsmNH 0U, // LOCFHRAsmNHE 0U, // LOCFHRAsmNL 0U, // LOCFHRAsmNLE 0U, // LOCFHRAsmNLH 0U, // LOCFHRAsmNM 0U, // LOCFHRAsmNO 0U, // LOCFHRAsmNP 0U, // LOCFHRAsmNZ 0U, // LOCFHRAsmO 0U, // LOCFHRAsmP 0U, // LOCFHRAsmZ 0U, // LOCG 0U, // LOCGAsm 0U, // LOCGAsmE 0U, // LOCGAsmH 0U, // LOCGAsmHE 0U, // LOCGAsmL 0U, // LOCGAsmLE 0U, // LOCGAsmLH 0U, // LOCGAsmM 0U, // LOCGAsmNE 0U, // LOCGAsmNH 0U, // LOCGAsmNHE 0U, // LOCGAsmNL 0U, // LOCGAsmNLE 0U, // LOCGAsmNLH 0U, // LOCGAsmNM 0U, // LOCGAsmNO 0U, // LOCGAsmNP 0U, // LOCGAsmNZ 0U, // LOCGAsmO 0U, // LOCGAsmP 0U, // LOCGAsmZ 0U, // LOCGHI 0U, // LOCGHIAsm 0U, // LOCGHIAsmE 0U, // LOCGHIAsmH 0U, // LOCGHIAsmHE 0U, // LOCGHIAsmL 0U, // LOCGHIAsmLE 0U, // LOCGHIAsmLH 0U, // LOCGHIAsmM 0U, // LOCGHIAsmNE 0U, // LOCGHIAsmNH 0U, // LOCGHIAsmNHE 0U, // LOCGHIAsmNL 0U, // LOCGHIAsmNLE 0U, // LOCGHIAsmNLH 0U, // LOCGHIAsmNM 0U, // LOCGHIAsmNO 0U, // LOCGHIAsmNP 0U, // LOCGHIAsmNZ 0U, // LOCGHIAsmO 0U, // LOCGHIAsmP 0U, // LOCGHIAsmZ 0U, // LOCGR 0U, // LOCGRAsm 0U, // LOCGRAsmE 0U, // LOCGRAsmH 0U, // LOCGRAsmHE 0U, // LOCGRAsmL 0U, // LOCGRAsmLE 0U, // LOCGRAsmLH 0U, // LOCGRAsmM 0U, // LOCGRAsmNE 0U, // LOCGRAsmNH 0U, // LOCGRAsmNHE 0U, // LOCGRAsmNL 0U, // LOCGRAsmNLE 0U, // LOCGRAsmNLH 0U, // LOCGRAsmNM 0U, // LOCGRAsmNO 0U, // LOCGRAsmNP 0U, // LOCGRAsmNZ 0U, // LOCGRAsmO 0U, // LOCGRAsmP 0U, // LOCGRAsmZ 0U, // LOCHHI 0U, // LOCHHIAsm 0U, // LOCHHIAsmE 0U, // LOCHHIAsmH 0U, // LOCHHIAsmHE 0U, // LOCHHIAsmL 0U, // LOCHHIAsmLE 0U, // LOCHHIAsmLH 0U, // LOCHHIAsmM 0U, // LOCHHIAsmNE 0U, // LOCHHIAsmNH 0U, // LOCHHIAsmNHE 0U, // LOCHHIAsmNL 0U, // LOCHHIAsmNLE 0U, // LOCHHIAsmNLH 0U, // LOCHHIAsmNM 0U, // LOCHHIAsmNO 0U, // LOCHHIAsmNP 0U, // LOCHHIAsmNZ 0U, // LOCHHIAsmO 0U, // LOCHHIAsmP 0U, // LOCHHIAsmZ 0U, // LOCHI 0U, // LOCHIAsm 0U, // LOCHIAsmE 0U, // LOCHIAsmH 0U, // LOCHIAsmHE 0U, // LOCHIAsmL 0U, // LOCHIAsmLE 0U, // LOCHIAsmLH 0U, // LOCHIAsmM 0U, // LOCHIAsmNE 0U, // LOCHIAsmNH 0U, // LOCHIAsmNHE 0U, // LOCHIAsmNL 0U, // LOCHIAsmNLE 0U, // LOCHIAsmNLH 0U, // LOCHIAsmNM 0U, // LOCHIAsmNO 0U, // LOCHIAsmNP 0U, // LOCHIAsmNZ 0U, // LOCHIAsmO 0U, // LOCHIAsmP 0U, // LOCHIAsmZ 0U, // LOCR 0U, // LOCRAsm 0U, // LOCRAsmE 0U, // LOCRAsmH 0U, // LOCRAsmHE 0U, // LOCRAsmL 0U, // LOCRAsmLE 0U, // LOCRAsmLH 0U, // LOCRAsmM 0U, // LOCRAsmNE 0U, // LOCRAsmNH 0U, // LOCRAsmNHE 0U, // LOCRAsmNL 0U, // LOCRAsmNLE 0U, // LOCRAsmNLH 0U, // LOCRAsmNM 0U, // LOCRAsmNO 0U, // LOCRAsmNP 0U, // LOCRAsmNZ 0U, // LOCRAsmO 0U, // LOCRAsmP 0U, // LOCRAsmZ 0U, // LPCTL 0U, // LPD 0U, // LPDBR 0U, // LPDFR 0U, // LPDFR_32 0U, // LPDG 0U, // LPDR 0U, // LPEBR 0U, // LPER 0U, // LPGFR 0U, // LPGR 0U, // LPP 0U, // LPQ 0U, // LPR 0U, // LPSW 0U, // LPSWE 0U, // LPTEA 0U, // LPXBR 0U, // LPXR 0U, // LR 0U, // LRA 0U, // LRAG 0U, // LRAY 0U, // LRDR 0U, // LRER 0U, // LRL 0U, // LRV 0U, // LRVG 0U, // LRVGR 0U, // LRVH 0U, // LRVR 0U, // LSCTL 0U, // LT 0U, // LTDBR 0U, // LTDBRCompare 0U, // LTDR 0U, // LTDTR 0U, // LTEBR 0U, // LTEBRCompare 0U, // LTER 0U, // LTG 0U, // LTGF 0U, // LTGFR 0U, // LTGR 0U, // LTR 0U, // LTXBR 0U, // LTXBRCompare 0U, // LTXR 0U, // LTXTR 0U, // LURA 0U, // LURAG 0U, // LXD 0U, // LXDB 0U, // LXDBR 0U, // LXDR 0U, // LXDTR 0U, // LXE 0U, // LXEB 0U, // LXEBR 0U, // LXER 0U, // LXR 0U, // LY 0U, // LZDR 0U, // LZER 0U, // LZRF 0U, // LZRG 0U, // LZXR 0U, // M 0U, // MAD 0U, // MADB 0U, // MADBR 0U, // MADR 0U, // MAE 0U, // MAEB 0U, // MAEBR 0U, // MAER 0U, // MAY 0U, // MAYH 0U, // MAYHR 0U, // MAYL 0U, // MAYLR 0U, // MAYR 0U, // MC 0U, // MD 0U, // MDB 0U, // MDBR 0U, // MDE 0U, // MDEB 0U, // MDEBR 0U, // MDER 0U, // MDR 0U, // MDTR 0U, // MDTRA 0U, // ME 0U, // MEE 0U, // MEEB 0U, // MEEBR 0U, // MEER 0U, // MER 0U, // MFY 0U, // MG 0U, // MGH 0U, // MGHI 0U, // MGRK 0U, // MH 0U, // MHI 0U, // MHY 0U, // ML 0U, // MLG 0U, // MLGR 0U, // MLR 0U, // MP 0U, // MR 0U, // MS 0U, // MSC 0U, // MSCH 0U, // MSD 0U, // MSDB 0U, // MSDBR 0U, // MSDR 0U, // MSE 0U, // MSEB 0U, // MSEBR 0U, // MSER 0U, // MSFI 0U, // MSG 0U, // MSGC 0U, // MSGF 0U, // MSGFI 0U, // MSGFR 0U, // MSGR 0U, // MSGRKC 0U, // MSR 0U, // MSRKC 0U, // MSTA 0U, // MSY 0U, // MVC 0U, // MVCDK 0U, // MVCIN 0U, // MVCK 0U, // MVCL 0U, // MVCLE 0U, // MVCLU 0U, // MVCOS 0U, // MVCP 0U, // MVCS 0U, // MVCSK 0U, // MVGHI 0U, // MVHHI 0U, // MVHI 0U, // MVI 0U, // MVIY 0U, // MVN 0U, // MVO 0U, // MVPG 0U, // MVST 0U, // MVZ 0U, // MXBR 0U, // MXD 0U, // MXDB 0U, // MXDBR 0U, // MXDR 0U, // MXR 0U, // MXTR 0U, // MXTRA 0U, // MY 0U, // MYH 0U, // MYHR 0U, // MYL 0U, // MYLR 0U, // MYR 0U, // N 0U, // NC 0U, // NG 0U, // NGR 0U, // NGRK 0U, // NI 0U, // NIAI 0U, // NIHF 0U, // NIHH 0U, // NIHL 0U, // NILF 0U, // NILH 0U, // NILL 0U, // NIY 0U, // NR 0U, // NRK 0U, // NTSTG 0U, // NY 0U, // O 0U, // OC 0U, // OG 0U, // OGR 0U, // OGRK 0U, // OI 0U, // OIHF 0U, // OIHH 0U, // OIHL 0U, // OILF 0U, // OILH 0U, // OILL 0U, // OIY 0U, // OR 0U, // ORK 0U, // OY 0U, // PACK 0U, // PALB 0U, // PC 0U, // PCC 0U, // PCKMO 0U, // PFD 0U, // PFDRL 0U, // PFMF 0U, // PFPO 0U, // PGIN 0U, // PGOUT 0U, // PKA 0U, // PKU 0U, // PLO 0U, // POPCNT 0U, // PPA 0U, // PPNO 0U, // PR 0U, // PRNO 0U, // PT 0U, // PTF 0U, // PTFF 0U, // PTI 0U, // PTLB 0U, // QADTR 0U, // QAXTR 0U, // QCTRI 0U, // QSI 0U, // RCHP 2U, // RISBG 2U, // RISBG32 2U, // RISBGN 2U, // RISBHG 2U, // RISBLG 0U, // RLL 0U, // RLLG 2U, // RNSBG 2U, // ROSBG 0U, // RP 0U, // RRBE 0U, // RRBM 0U, // RRDTR 0U, // RRXTR 0U, // RSCH 2U, // RXSBG 0U, // S 0U, // SAC 0U, // SACF 0U, // SAL 0U, // SAM24 0U, // SAM31 0U, // SAM64 0U, // SAR 0U, // SCCTR 0U, // SCHM 0U, // SCK 0U, // SCKC 0U, // SCKPF 0U, // SD 0U, // SDB 0U, // SDBR 0U, // SDR 0U, // SDTR 0U, // SDTRA 0U, // SE 0U, // SEB 0U, // SEBR 0U, // SER 0U, // SFASR 0U, // SFPC 0U, // SG 0U, // SGF 0U, // SGFR 0U, // SGH 0U, // SGR 0U, // SGRK 0U, // SH 0U, // SHHHR 0U, // SHHLR 0U, // SHY 0U, // SIE 0U, // SIGA 0U, // SIGP 0U, // SL 0U, // SLA 0U, // SLAG 0U, // SLAK 0U, // SLB 0U, // SLBG 0U, // SLBGR 0U, // SLBR 0U, // SLDA 0U, // SLDL 0U, // SLDT 0U, // SLFI 0U, // SLG 0U, // SLGF 0U, // SLGFI 0U, // SLGFR 0U, // SLGR 0U, // SLGRK 0U, // SLHHHR 0U, // SLHHLR 0U, // SLL 0U, // SLLG 0U, // SLLK 0U, // SLR 0U, // SLRK 0U, // SLXT 0U, // SLY 0U, // SP 0U, // SPCTR 0U, // SPKA 0U, // SPM 0U, // SPT 0U, // SPX 0U, // SQD 0U, // SQDB 0U, // SQDBR 0U, // SQDR 0U, // SQE 0U, // SQEB 0U, // SQEBR 0U, // SQER 0U, // SQXBR 0U, // SQXR 0U, // SR 0U, // SRA 0U, // SRAG 0U, // SRAK 0U, // SRDA 0U, // SRDL 0U, // SRDT 0U, // SRK 0U, // SRL 0U, // SRLG 0U, // SRLK 0U, // SRNM 0U, // SRNMB 0U, // SRNMT 0U, // SRP 0U, // SRST 0U, // SRSTU 0U, // SRXT 0U, // SSAIR 0U, // SSAR 0U, // SSCH 0U, // SSKE 0U, // SSKEOpt 0U, // SSM 0U, // ST 0U, // STAM 0U, // STAMY 0U, // STAP 0U, // STC 0U, // STCH 0U, // STCK 0U, // STCKC 0U, // STCKE 0U, // STCKF 0U, // STCM 0U, // STCMH 0U, // STCMY 0U, // STCPS 0U, // STCRW 0U, // STCTG 0U, // STCTL 0U, // STCY 0U, // STD 0U, // STDY 0U, // STE 0U, // STEY 0U, // STFH 0U, // STFL 0U, // STFLE 0U, // STFPC 0U, // STG 0U, // STGRL 0U, // STGSC 0U, // STH 0U, // STHH 0U, // STHRL 0U, // STHY 0U, // STIDP 0U, // STM 0U, // STMG 0U, // STMH 0U, // STMY 0U, // STNSM 0U, // STOC 0U, // STOCAsm 0U, // STOCAsmE 0U, // STOCAsmH 0U, // STOCAsmHE 0U, // STOCAsmL 0U, // STOCAsmLE 0U, // STOCAsmLH 0U, // STOCAsmM 0U, // STOCAsmNE 0U, // STOCAsmNH 0U, // STOCAsmNHE 0U, // STOCAsmNL 0U, // STOCAsmNLE 0U, // STOCAsmNLH 0U, // STOCAsmNM 0U, // STOCAsmNO 0U, // STOCAsmNP 0U, // STOCAsmNZ 0U, // STOCAsmO 0U, // STOCAsmP 0U, // STOCAsmZ 0U, // STOCFH 0U, // STOCFHAsm 0U, // STOCFHAsmE 0U, // STOCFHAsmH 0U, // STOCFHAsmHE 0U, // STOCFHAsmL 0U, // STOCFHAsmLE 0U, // STOCFHAsmLH 0U, // STOCFHAsmM 0U, // STOCFHAsmNE 0U, // STOCFHAsmNH 0U, // STOCFHAsmNHE 0U, // STOCFHAsmNL 0U, // STOCFHAsmNLE 0U, // STOCFHAsmNLH 0U, // STOCFHAsmNM 0U, // STOCFHAsmNO 0U, // STOCFHAsmNP 0U, // STOCFHAsmNZ 0U, // STOCFHAsmO 0U, // STOCFHAsmP 0U, // STOCFHAsmZ 0U, // STOCG 0U, // STOCGAsm 0U, // STOCGAsmE 0U, // STOCGAsmH 0U, // STOCGAsmHE 0U, // STOCGAsmL 0U, // STOCGAsmLE 0U, // STOCGAsmLH 0U, // STOCGAsmM 0U, // STOCGAsmNE 0U, // STOCGAsmNH 0U, // STOCGAsmNHE 0U, // STOCGAsmNL 0U, // STOCGAsmNLE 0U, // STOCGAsmNLH 0U, // STOCGAsmNM 0U, // STOCGAsmNO 0U, // STOCGAsmNP 0U, // STOCGAsmNZ 0U, // STOCGAsmO 0U, // STOCGAsmP 0U, // STOCGAsmZ 0U, // STOSM 0U, // STPQ 0U, // STPT 0U, // STPX 0U, // STRAG 0U, // STRL 0U, // STRV 0U, // STRVG 0U, // STRVH 0U, // STSCH 0U, // STSI 0U, // STURA 0U, // STURG 0U, // STY 0U, // SU 0U, // SUR 0U, // SVC 0U, // SW 0U, // SWR 0U, // SXBR 0U, // SXR 0U, // SXTR 0U, // SXTRA 0U, // SY 0U, // TABORT 0U, // TAM 0U, // TAR 0U, // TB 0U, // TBDR 0U, // TBEDR 0U, // TBEGIN 0U, // TBEGINC 0U, // TCDB 0U, // TCEB 0U, // TCXB 0U, // TDCDT 0U, // TDCET 0U, // TDCXT 0U, // TDGDT 0U, // TDGET 0U, // TDGXT 0U, // TEND 0U, // THDER 0U, // THDR 0U, // TM 0U, // TMHH 0U, // TMHL 0U, // TMLH 0U, // TMLL 0U, // TMY 0U, // TP 0U, // TPI 0U, // TPROT 0U, // TR 0U, // TRACE 0U, // TRACG 0U, // TRAP2 0U, // TRAP4 0U, // TRE 0U, // TROO 0U, // TROOOpt 0U, // TROT 0U, // TROTOpt 0U, // TRT 0U, // TRTE 0U, // TRTEOpt 0U, // TRTO 0U, // TRTOOpt 0U, // TRTR 0U, // TRTRE 0U, // TRTREOpt 0U, // TRTT 0U, // TRTTOpt 0U, // TS 0U, // TSCH 0U, // UNPK 0U, // UNPKA 0U, // UNPKU 0U, // UPT 0U, // VA 0U, // VAB 6U, // VAC 0U, // VACC 0U, // VACCB 6U, // VACCC 0U, // VACCCQ 0U, // VACCF 0U, // VACCG 0U, // VACCH 0U, // VACCQ 0U, // VACQ 0U, // VAF 0U, // VAG 0U, // VAH 7U, // VAP 0U, // VAQ 0U, // VAVG 0U, // VAVGB 0U, // VAVGF 0U, // VAVGG 0U, // VAVGH 0U, // VAVGL 0U, // VAVGLB 0U, // VAVGLF 0U, // VAVGLG 0U, // VAVGLH 0U, // VBPERM 6U, // VCDG 0U, // VCDGB 6U, // VCDLG 0U, // VCDLGB 6U, // VCEQ 0U, // VCEQB 0U, // VCEQBS 0U, // VCEQF 0U, // VCEQFS 0U, // VCEQG 0U, // VCEQGS 0U, // VCEQH 0U, // VCEQHS 6U, // VCGD 0U, // VCGDB 6U, // VCH 0U, // VCHB 0U, // VCHBS 0U, // VCHF 0U, // VCHFS 0U, // VCHG 0U, // VCHGS 0U, // VCHH 0U, // VCHHS 6U, // VCHL 0U, // VCHLB 0U, // VCHLBS 0U, // VCHLF 0U, // VCHLFS 0U, // VCHLG 0U, // VCHLGS 0U, // VCHLH 0U, // VCHLHS 0U, // VCKSM 6U, // VCLGD 0U, // VCLGDB 0U, // VCLZ 0U, // VCLZB 0U, // VCLZF 0U, // VCLZG 0U, // VCLZH 0U, // VCP 0U, // VCTZ 0U, // VCTZB 0U, // VCTZF 0U, // VCTZG 0U, // VCTZH 0U, // VCVB 0U, // VCVBG 1U, // VCVD 1U, // VCVDG 7U, // VDP 0U, // VEC 0U, // VECB 0U, // VECF 0U, // VECG 0U, // VECH 0U, // VECL 0U, // VECLB 0U, // VECLF 0U, // VECLG 0U, // VECLH 10U, // VERIM 0U, // VERIMB 0U, // VERIMF 0U, // VERIMG 0U, // VERIMH 0U, // VERLL 0U, // VERLLB 0U, // VERLLF 0U, // VERLLG 0U, // VERLLH 0U, // VERLLV 0U, // VERLLVB 0U, // VERLLVF 0U, // VERLLVG 0U, // VERLLVH 0U, // VESL 0U, // VESLB 0U, // VESLF 0U, // VESLG 0U, // VESLH 0U, // VESLV 0U, // VESLVB 0U, // VESLVF 0U, // VESLVG 0U, // VESLVH 0U, // VESRA 0U, // VESRAB 0U, // VESRAF 0U, // VESRAG 0U, // VESRAH 0U, // VESRAV 0U, // VESRAVB 0U, // VESRAVF 0U, // VESRAVG 0U, // VESRAVH 0U, // VESRL 0U, // VESRLB 0U, // VESRLF 0U, // VESRLG 0U, // VESRLH 0U, // VESRLV 0U, // VESRLVB 0U, // VESRLVF 0U, // VESRLVG 0U, // VESRLVH 6U, // VFA 0U, // VFADB 6U, // VFAE 0U, // VFAEB 0U, // VFAEBS 0U, // VFAEF 0U, // VFAEFS 0U, // VFAEH 0U, // VFAEHS 0U, // VFAEZB 0U, // VFAEZBS 0U, // VFAEZF 0U, // VFAEZFS 0U, // VFAEZH 0U, // VFAEZHS 0U, // VFASB 22U, // VFCE 0U, // VFCEDB 0U, // VFCEDBS 0U, // VFCESB 0U, // VFCESBS 22U, // VFCH 0U, // VFCHDB 0U, // VFCHDBS 22U, // VFCHE 0U, // VFCHEDB 0U, // VFCHEDBS 0U, // VFCHESB 0U, // VFCHESBS 0U, // VFCHSB 0U, // VFCHSBS 6U, // VFD 0U, // VFDDB 0U, // VFDSB 6U, // VFEE 0U, // VFEEB 0U, // VFEEBS 0U, // VFEEF 0U, // VFEEFS 0U, // VFEEH 0U, // VFEEHS 0U, // VFEEZB 0U, // VFEEZBS 0U, // VFEEZF 0U, // VFEEZFS 0U, // VFEEZH 0U, // VFEEZHS 6U, // VFENE 0U, // VFENEB 0U, // VFENEBS 0U, // VFENEF 0U, // VFENEFS 0U, // VFENEH 0U, // VFENEHS 0U, // VFENEZB 0U, // VFENEZBS 0U, // VFENEZF 0U, // VFENEZFS 0U, // VFENEZH 0U, // VFENEZHS 6U, // VFI 0U, // VFIDB 0U, // VFISB 0U, // VFKEDB 0U, // VFKEDBS 0U, // VFKESB 0U, // VFKESBS 0U, // VFKHDB 0U, // VFKHDBS 0U, // VFKHEDB 0U, // VFKHEDBS 0U, // VFKHESB 0U, // VFKHESBS 0U, // VFKHSB 0U, // VFKHSBS 0U, // VFLCDB 0U, // VFLCSB 0U, // VFLL 0U, // VFLLS 0U, // VFLNDB 0U, // VFLNSB 0U, // VFLPDB 0U, // VFLPSB 6U, // VFLR 0U, // VFLRD 6U, // VFM 22U, // VFMA 0U, // VFMADB 0U, // VFMASB 22U, // VFMAX 0U, // VFMAXDB 0U, // VFMAXSB 0U, // VFMDB 22U, // VFMIN 0U, // VFMINDB 0U, // VFMINSB 22U, // VFMS 0U, // VFMSB 0U, // VFMSDB 0U, // VFMSSB 22U, // VFNMA 0U, // VFNMADB 0U, // VFNMASB 22U, // VFNMS 0U, // VFNMSDB 0U, // VFNMSSB 6U, // VFPSO 0U, // VFPSODB 0U, // VFPSOSB 6U, // VFS 0U, // VFSDB 0U, // VFSQ 0U, // VFSQDB 0U, // VFSQSB 0U, // VFSSB 6U, // VFTCI 0U, // VFTCIDB 0U, // VFTCISB 0U, // VGBM 0U, // VGEF 0U, // VGEG 0U, // VGFM 6U, // VGFMA 0U, // VGFMAB 0U, // VGFMAF 0U, // VGFMAG 0U, // VGFMAH 0U, // VGFMB 0U, // VGFMF 0U, // VGFMG 0U, // VGFMH 0U, // VGM 0U, // VGMB 0U, // VGMF 0U, // VGMG 0U, // VGMH 0U, // VISTR 0U, // VISTRB 0U, // VISTRBS 0U, // VISTRF 0U, // VISTRFS 0U, // VISTRH 0U, // VISTRHS 0U, // VL 0U, // VLBB 0U, // VLC 0U, // VLCB 0U, // VLCF 0U, // VLCG 0U, // VLCH 0U, // VLDE 0U, // VLDEB 0U, // VLEB 6U, // VLED 0U, // VLEDB 0U, // VLEF 0U, // VLEG 0U, // VLEH 0U, // VLEIB 0U, // VLEIF 0U, // VLEIG 0U, // VLEIH 0U, // VLGV 0U, // VLGVB 0U, // VLGVF 0U, // VLGVG 0U, // VLGVH 0U, // VLIP 0U, // VLL 0U, // VLLEZ 0U, // VLLEZB 0U, // VLLEZF 0U, // VLLEZG 0U, // VLLEZH 0U, // VLLEZLF 0U, // VLM 0U, // VLP 0U, // VLPB 0U, // VLPF 0U, // VLPG 0U, // VLPH 0U, // VLR 0U, // VLREP 0U, // VLREPB 0U, // VLREPF 0U, // VLREPG 0U, // VLREPH 0U, // VLRL 0U, // VLRLR 1U, // VLVG 0U, // VLVGB 0U, // VLVGF 0U, // VLVGG 0U, // VLVGH 0U, // VLVGP 6U, // VMAE 0U, // VMAEB 0U, // VMAEF 0U, // VMAEH 6U, // VMAH 0U, // VMAHB 0U, // VMAHF 0U, // VMAHH 6U, // VMAL 0U, // VMALB 6U, // VMALE 0U, // VMALEB 0U, // VMALEF 0U, // VMALEH 0U, // VMALF 6U, // VMALH 0U, // VMALHB 0U, // VMALHF 0U, // VMALHH 0U, // VMALHW 6U, // VMALO 0U, // VMALOB 0U, // VMALOF 0U, // VMALOH 6U, // VMAO 0U, // VMAOB 0U, // VMAOF 0U, // VMAOH 0U, // VME 0U, // VMEB 0U, // VMEF 0U, // VMEH 0U, // VMH 0U, // VMHB 0U, // VMHF 0U, // VMHH 0U, // VML 0U, // VMLB 0U, // VMLE 0U, // VMLEB 0U, // VMLEF 0U, // VMLEH 0U, // VMLF 0U, // VMLH 0U, // VMLHB 0U, // VMLHF 0U, // VMLHH 0U, // VMLHW 0U, // VMLO 0U, // VMLOB 0U, // VMLOF 0U, // VMLOH 0U, // VMN 0U, // VMNB 0U, // VMNF 0U, // VMNG 0U, // VMNH 0U, // VMNL 0U, // VMNLB 0U, // VMNLF 0U, // VMNLG 0U, // VMNLH 0U, // VMO 0U, // VMOB 0U, // VMOF 0U, // VMOH 7U, // VMP 0U, // VMRH 0U, // VMRHB 0U, // VMRHF 0U, // VMRHG 0U, // VMRHH 0U, // VMRL 0U, // VMRLB 0U, // VMRLF 0U, // VMRLG 0U, // VMRLH 22U, // VMSL 6U, // VMSLG 7U, // VMSP 0U, // VMX 0U, // VMXB 0U, // VMXF 0U, // VMXG 0U, // VMXH 0U, // VMXL 0U, // VMXLB 0U, // VMXLF 0U, // VMXLG 0U, // VMXLH 0U, // VN 0U, // VNC 0U, // VNN 0U, // VNO 0U, // VNX 0U, // VO 0U, // VOC 0U, // VONE 0U, // VPDI 0U, // VPERM 0U, // VPK 0U, // VPKF 0U, // VPKG 0U, // VPKH 6U, // VPKLS 0U, // VPKLSF 0U, // VPKLSFS 0U, // VPKLSG 0U, // VPKLSGS 0U, // VPKLSH 0U, // VPKLSHS 6U, // VPKS 0U, // VPKSF 0U, // VPKSFS 0U, // VPKSG 0U, // VPKSGS 0U, // VPKSH 0U, // VPKSHS 0U, // VPKZ 0U, // VPOPCT 0U, // VPOPCTB 0U, // VPOPCTF 0U, // VPOPCTG 0U, // VPOPCTH 0U, // VPSOP 0U, // VREP 0U, // VREPB 0U, // VREPF 0U, // VREPG 0U, // VREPH 0U, // VREPI 0U, // VREPIB 0U, // VREPIF 0U, // VREPIG 0U, // VREPIH 7U, // VRP 0U, // VS 0U, // VSB 6U, // VSBCBI 0U, // VSBCBIQ 6U, // VSBI 0U, // VSBIQ 0U, // VSCBI 0U, // VSCBIB 0U, // VSCBIF 0U, // VSCBIG 0U, // VSCBIH 0U, // VSCBIQ 0U, // VSCEF 0U, // VSCEG 7U, // VSDP 0U, // VSEG 0U, // VSEGB 0U, // VSEGF 0U, // VSEGH 0U, // VSEL 0U, // VSF 0U, // VSG 0U, // VSH 0U, // VSL 0U, // VSLB 1U, // VSLDB 7U, // VSP 0U, // VSQ 0U, // VSRA 0U, // VSRAB 0U, // VSRL 0U, // VSRLB 0U, // VSRP 0U, // VST 0U, // VSTEB 0U, // VSTEF 0U, // VSTEG 0U, // VSTEH 0U, // VSTL 0U, // VSTM 22U, // VSTRC 6U, // VSTRCB 6U, // VSTRCBS 6U, // VSTRCF 6U, // VSTRCFS 6U, // VSTRCH 6U, // VSTRCHS 6U, // VSTRCZB 6U, // VSTRCZBS 6U, // VSTRCZF 6U, // VSTRCZFS 6U, // VSTRCZH 6U, // VSTRCZHS 0U, // VSTRL 0U, // VSTRLR 0U, // VSUM 0U, // VSUMB 0U, // VSUMG 0U, // VSUMGF 0U, // VSUMGH 0U, // VSUMH 0U, // VSUMQ 0U, // VSUMQF 0U, // VSUMQG 0U, // VTM 0U, // VTP 0U, // VUPH 0U, // VUPHB 0U, // VUPHF 0U, // VUPHH 0U, // VUPKZ 0U, // VUPL 0U, // VUPLB 0U, // VUPLF 0U, // VUPLH 0U, // VUPLHB 0U, // VUPLHF 0U, // VUPLHH 0U, // VUPLHW 0U, // VUPLL 0U, // VUPLLB 0U, // VUPLLF 0U, // VUPLLH 0U, // VX 0U, // VZERO 0U, // WCDGB 0U, // WCDLGB 0U, // WCGDB 0U, // WCLGDB 0U, // WFADB 0U, // WFASB 0U, // WFAXB 0U, // WFC 0U, // WFCDB 0U, // WFCEDB 0U, // WFCEDBS 0U, // WFCESB 0U, // WFCESBS 0U, // WFCEXB 0U, // WFCEXBS 0U, // WFCHDB 0U, // WFCHDBS 0U, // WFCHEDB 0U, // WFCHEDBS 0U, // WFCHESB 0U, // WFCHESBS 0U, // WFCHEXB 0U, // WFCHEXBS 0U, // WFCHSB 0U, // WFCHSBS 0U, // WFCHXB 0U, // WFCHXBS 0U, // WFCSB 0U, // WFCXB 0U, // WFDDB 0U, // WFDSB 0U, // WFDXB 0U, // WFIDB 0U, // WFISB 0U, // WFIXB 0U, // WFK 0U, // WFKDB 0U, // WFKEDB 0U, // WFKEDBS 0U, // WFKESB 0U, // WFKESBS 0U, // WFKEXB 0U, // WFKEXBS 0U, // WFKHDB 0U, // WFKHDBS 0U, // WFKHEDB 0U, // WFKHEDBS 0U, // WFKHESB 0U, // WFKHESBS 0U, // WFKHEXB 0U, // WFKHEXBS 0U, // WFKHSB 0U, // WFKHSBS 0U, // WFKHXB 0U, // WFKHXBS 0U, // WFKSB 0U, // WFKXB 0U, // WFLCDB 0U, // WFLCSB 0U, // WFLCXB 0U, // WFLLD 0U, // WFLLS 0U, // WFLNDB 0U, // WFLNSB 0U, // WFLNXB 0U, // WFLPDB 0U, // WFLPSB 0U, // WFLPXB 0U, // WFLRD 0U, // WFLRX 0U, // WFMADB 0U, // WFMASB 0U, // WFMAXB 0U, // WFMAXDB 0U, // WFMAXSB 0U, // WFMAXXB 0U, // WFMDB 0U, // WFMINDB 0U, // WFMINSB 0U, // WFMINXB 0U, // WFMSB 0U, // WFMSDB 0U, // WFMSSB 0U, // WFMSXB 0U, // WFMXB 0U, // WFNMADB 0U, // WFNMASB 0U, // WFNMAXB 0U, // WFNMSDB 0U, // WFNMSSB 0U, // WFNMSXB 0U, // WFPSODB 0U, // WFPSOSB 0U, // WFPSOXB 0U, // WFSDB 0U, // WFSQDB 0U, // WFSQSB 0U, // WFSQXB 0U, // WFSSB 0U, // WFSXB 0U, // WFTCIDB 0U, // WFTCISB 0U, // WFTCIXB 0U, // WLDEB 0U, // WLEDB 0U, // X 0U, // XC 0U, // XG 0U, // XGR 0U, // XGRK 0U, // XI 0U, // XIHF 0U, // XILF 0U, // XIY 0U, // XR 0U, // XRK 0U, // XSCH 0U, // XY 0U, // ZAP }; // Emit the opcode for the instruction. uint64_t Bits = 0; Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0; Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32; Bits |= (uint64_t)OpInfo2[MCInst_getOpcode(MI)] << 48; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 16383)-1); #endif // Fragment 0 encoded into 5 bits for 18 unique commands. // printf("Fragment 0 = %" PRIu64 "\n", (Bits >> 14) & 31); switch ((Bits >> 14) & 31) { default: // llvm_unreachable("Invalid command number."); case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... printOperand(MI, 0, O); break; case 2: // AGSI, ALGSI, ALSI, ASI, CFC, CGHSI, CHHSI, CHSI, CLFHSI, CLGHSI, CLHHS... printBDAddrOperand(MI, 0, O); break; case 3: // AP, CLC, CP, DP, ED, EDMK, MP, MVC, MVCIN, MVN, MVO, MVZ, NC, OC, PACK... printBDLAddrOperand(MI, 0, O); break; case 4: // B, BAsmE, BAsmH, BAsmHE, BAsmL, BAsmLE, BAsmLH, BAsmM, BAsmNE, BAsmNH,... printBDXAddrOperand(MI, 0, O); return; break; case 5: // BC, BCR, BIC, BRC, BRCL printCond4Operand(MI, 1, O); break; case 6: // BCAsm, BCRAsm, BICAsm, BPP, BPRP, BRCAsm, BRCLAsm, NIAI, PFD, PFDRL printU4ImmOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 7: // CGIB, CGIJ, CGIT, CGRB, CGRJ, CGRT, CIB, CIJ, CIT, CLFIT, CLGIB, CLGIJ... printCond4Operand(MI, 2, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 8: // CLGT, CLT printCond4Operand(MI, 3, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printBDAddrOperand(MI, 1, O); return; break; case 9: // InsnE, InsnRR printU16ImmOperand(MI, 0, O); break; case 10: // InsnRI, InsnRRE, InsnRRF, InsnRS, InsnRX, InsnS, InsnSI printU32ImmOperand(MI, 0, O); SStream_concat0(O, ","); break; case 11: // InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRS, InsnRSE, InsnRSI, InsnRS... printU48ImmOperand(MI, 0, O); SStream_concat0(O, ","); break; case 12: // J, JAsmE, JAsmH, JAsmHE, JAsmL, JAsmLE, JAsmLH, JAsmM, JAsmNE, JAsmNH,... printPCRelOperand(MI, 0, O); return; break; case 13: // KIMD, KLMD, KMAC, PFMF, TRTE, TRTEOpt, TRTRE, TRTREOpt printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); break; case 14: // LOC, LOCFH, LOCG printCond4Operand(MI, 5, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); printBDAddrOperand(MI, 2, O); return; break; case 15: // LOCFHR, LOCGHI, LOCGR, LOCHHI, LOCHI, LOCR, STOC, STOCFH, STOCG printCond4Operand(MI, 4, O); SStream_concat0(O, "\t"); printOperand(MI, 0, O); SStream_concat0(O, ", "); break; case 16: // MVCK, MVCP, MVCS printBDRAddrOperand(MI, 0, O); SStream_concat0(O, ", "); printBDAddrOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 17: // SVC printU8ImmOperand(MI, 0, O); return; break; } // Fragment 1 encoded into 5 bits for 17 unique commands. // printf("Fragment 1 = %" PRIu64 "\n", (Bits >> 19) & 31); switch ((Bits >> 19) & 31) { default: // llvm_unreachable("Invalid command number."); case 0: // A, AD, ADB, ADBR, ADR, ADTR, ADTRA, AE, AEB, AEBR, AER, AFI, AG, AGF, ... SStream_concat0(O, ", "); break; case 1: // BC, BIC, BRC, BRCL SStream_concat0(O, "\t"); break; case 2: // BCAsm, BICAsm, PFD printBDXAddrOperand(MI, 1, O); return; break; case 3: // BCR SStream_concat0(O, "r\t"); printOperand(MI, 2, O); return; break; case 4: // BCRAsm, CGRB, CGRJ, CGRT, CLGRB, CLGRJ, CLGRT, CLRB, CLRJ, CLRT, CRB, ... printOperand(MI, 1, O); break; case 5: // BPP, BPRP, BRCAsm, BRCLAsm, PFDRL printPCRelOperand(MI, 1, O); break; case 6: // BR, BRAsmE, BRAsmH, BRAsmHE, BRAsmL, BRAsmLE, BRAsmLH, BRAsmM, BRAsmNE... return; break; case 7: // CGIB, CGIJ, CIB, CIJ printS8ImmOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 8: // CGIT, CIT printS16ImmOperand(MI, 1, O); return; break; case 9: // CLFIT, CLGIT printU16ImmOperand(MI, 1, O); return; break; case 10: // CLGIB, CLGIJ, CLIB, CLIJ printU8ImmOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 11: // InsnRR SStream_concat0(O, ","); printOperand(MI, 1, O); SStream_concat0(O, ","); printOperand(MI, 2, O); return; break; case 12: // InsnS, InsnSI, InsnSIL, InsnSIY, InsnSSE, InsnSSF, STOC, STOCFH, STOCG printBDAddrOperand(MI, 1, O); break; case 13: // InsnSS printBDRAddrOperand(MI, 1, O); SStream_concat0(O, ","); printBDAddrOperand(MI, 4, O); SStream_concat0(O, ","); printOperand(MI, 6, O); return; break; case 14: // LOCFHR, LOCGR, LOCR printOperand(MI, 2, O); return; break; case 15: // LOCGHI, LOCHHI, LOCHI printS16ImmOperand(MI, 2, O); return; break; case 16: // NIAI printU4ImmOperand(MI, 1, O); return; break; } // Fragment 2 encoded into 6 bits for 34 unique commands. // printf("Fragment 2 = %" PRIu64 "\n", (Bits >> 24) & 63); switch ((Bits >> 24) & 63) { default: // llvm_unreachable("Invalid command number."); case 0: // A, AD, ADB, AE, AEB, AG, AGF, AGH, AH, AHY, AL, ALC, ALCG, ALG, ALGF, ... printBDXAddrOperand(MI, 2, O); break; case 1: // ADBR, ADR, AEBR, AER, AGFR, AGR, ALCGR, ALCR, ALGFR, ALGR, ALR, AR, AU... printOperand(MI, 2, O); break; case 2: // ADTR, ADTRA, AGHIK, AGRK, AHHHR, AHHLR, AHIK, ALGHSIK, ALGRK, ALHHHR, ... printOperand(MI, 1, O); break; case 3: // AFI, AGFI, AIH, ALSIH, ALSIHN, MSFI, MSGFI printS32ImmOperand(MI, 2, O); return; break; case 4: // AGHI, AHI, CGHSI, CHHSI, CHSI, LOCGHIAsm, LOCGHIAsmE, LOCGHIAsmH, LOCG... printS16ImmOperand(MI, 2, O); break; case 5: // AGSI, ALGSI, ALSI, ASI printS8ImmOperand(MI, 2, O); return; break; case 6: // ALFI, ALGFI, NIHF, NILF, OIHF, OILF, SLFI, SLGFI, XIHF, XILF printU32ImmOperand(MI, 2, O); return; break; case 7: // AP, CP, DP, MP, MVO, PACK, SP, UNPK, ZAP printBDLAddrOperand(MI, 3, O); return; break; case 8: // BAL, BAS, C, CD, CDB, CE, CEB, CG, CGF, CGH, CH, CHF, CHY, CL, CLG, CL... printBDXAddrOperand(MI, 1, O); break; case 9: // BCRAsm, BRCAsm, BRCLAsm, CGRT, CLGRT, CLRT, CRT, InsnS, PFDRL, STOC, S... return; break; case 10: // BPP, BPRP, CGRB, CGRJ, CLGRB, CLGRJ, CLRB, CLRJ, CRB, CRJ SStream_concat0(O, ", "); break; case 11: // BRAS, BRASL printPCRelTLSOperand(MI, 1, O); return; break; case 12: // BRC, BRCL, BRCT, BRCTG, BRCTH printPCRelOperand(MI, 2, O); return; break; case 13: // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... printU4ImmOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 14: // CDPT, CDZT, CPDT, CPXT, CXPT, CXZT, CZDT, CZXT printBDLAddrOperand(MI, 1, O); SStream_concat0(O, ", "); printU4ImmOperand(MI, 4, O); return; break; case 15: // CFI, CGFI, CIH, LGFI printS32ImmOperand(MI, 1, O); return; break; case 16: // CGFRL, CGHRL, CGRL, CHRL, CLGFRL, CLGHRL, CLGRL, CLHRL, CLRL, CRL, EXR... printPCRelOperand(MI, 1, O); return; break; case 17: // CGHI, CGITAsm, CGITAsmE, CGITAsmH, CGITAsmHE, CGITAsmL, CGITAsmLE, CGI... printS16ImmOperand(MI, 1, O); break; case 18: // CGIB, CIB, CLC, CLGIB, CLIB, ED, EDMK, MVC, MVCIN, MVN, MVZ, NC, OC, S... printBDAddrOperand(MI, 3, O); break; case 19: // CGIBAsm, CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH... printS8ImmOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 20: // CGIJ, CIJ, CLGIJ, CLIJ printPCRelOperand(MI, 3, O); return; break; case 21: // CLFHSI, CLGHSI, CLHHSI, IIHH, IIHL, IILH, IILL, NIHH, NIHL, NILH, NILL... printU16ImmOperand(MI, 2, O); return; break; case 22: // CLFI, CLGFI, CLIH, IIHF, IILF, LLIHF, LLILF printU32ImmOperand(MI, 1, O); return; break; case 23: // CLFITAsm, CLFITAsmE, CLFITAsmH, CLFITAsmHE, CLFITAsmL, CLFITAsmLE, CLF... printU16ImmOperand(MI, 1, O); break; case 24: // CLGIBAsm, CLGIBAsmE, CLGIBAsmH, CLGIBAsmHE, CLGIBAsmL, CLGIBAsmLE, CLG... printU8ImmOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 25: // CLGTAsm, CLTAsm, TRTE, TRTRE printU4ImmOperand(MI, 3, O); break; case 26: // CLGTAsmE, CLGTAsmH, CLGTAsmHE, CLGTAsmL, CLGTAsmLE, CLGTAsmLH, CLGTAsm... printBDAddrOperand(MI, 1, O); break; case 27: // CLI, CLIY, MC, MVI, MVIY, NI, NIY, OI, OIY, STNSM, STOSM, TM, TMY, XI,... printU8ImmOperand(MI, 2, O); return; break; case 28: // CSST, ECTG, LASP, LOCAsm, LOCAsmE, LOCAsmH, LOCAsmHE, LOCAsmL, LOCAsmL... printBDAddrOperand(MI, 2, O); break; case 29: // ICM, ICMH, ICMY printU4ImmOperand(MI, 2, O); SStream_concat0(O, ", "); printBDAddrOperand(MI, 3, O); return; break; case 30: // InsnRI, InsnRIE, InsnRIL, InsnRILU, InsnRIS, InsnRRE, InsnRRF, InsnRRS... SStream_concat0(O, ","); break; case 31: // PKA, PKU printBDLAddrOperand(MI, 2, O); return; break; case 32: // VGEF, VGEG printBDVAddrOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 33: // VSCEF, VSCEG printBDVAddrOperand(MI, 1, O); SStream_concat0(O, ", "); break; } // Fragment 3 encoded into 5 bits for 20 unique commands. // printf("Fragment 3 = %" PRIu64 "\n", (Bits >> 30) & 31); switch ((Bits >> 30) & 31) { default: // llvm_unreachable("Invalid command number."); case 0: // A, AD, ADB, ADBR, ADR, AE, AEB, AEBR, AER, AG, AGF, AGFR, AGH, AGHI, A... return; break; case 1: // ADTR, ADTRA, AGHIK, AGRK, AHHHR, AHHLR, AHIK, ALGHSIK, ALGRK, ALHHHR, ... SStream_concat0(O, ", "); break; case 2: // BPP, InsnRX, InsnRXE, InsnRXY printBDXAddrOperand(MI, 2, O); return; break; case 3: // BPRP, CGIJAsmE, CGIJAsmH, CGIJAsmHE, CGIJAsmL, CGIJAsmLE, CGIJAsmLH, C... printPCRelOperand(MI, 2, O); return; break; case 4: // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... printOperand(MI, 2, O); break; case 5: // CGIBAsm, CGIJAsm, CIBAsm, CIJAsm, CLGIBAsm, CLGIJAsm, CLIBAsm, CLIJAsm printU4ImmOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 6: // CGIBAsmE, CGIBAsmH, CGIBAsmHE, CGIBAsmL, CGIBAsmLE, CGIBAsmLH, CGIBAsm... printBDAddrOperand(MI, 2, O); return; break; case 7: // CGRB, CLGRB, CLRB, CRB, InsnSSE, InsnSSF printBDAddrOperand(MI, 3, O); break; case 8: // CGRJ, CLGRJ, CLRJ, CRJ printPCRelOperand(MI, 3, O); return; break; case 9: // InsnRI printS16ImmOperand(MI, 2, O); return; break; case 10: // InsnRILU printU32ImmOperand(MI, 2, O); return; break; case 11: // InsnRIS printS8ImmOperand(MI, 2, O); SStream_concat0(O, ","); printU4ImmOperand(MI, 3, O); SStream_concat0(O, ","); printBDAddrOperand(MI, 4, O); return; break; case 12: // InsnSI printS8ImmOperand(MI, 3, O); return; break; case 13: // InsnSIL printU16ImmOperand(MI, 3, O); return; break; case 14: // InsnSIY printU8ImmOperand(MI, 3, O); return; break; case 15: // VGEF printU2ImmOperand(MI, 5, O); return; break; case 16: // VGEG printU1ImmOperand(MI, 5, O); return; break; case 17: // VGM, VGMB, VGMF, VGMG, VGMH printU8ImmOperand(MI, 2, O); break; case 18: // VSCEF printU2ImmOperand(MI, 4, O); return; break; case 19: // VSCEG printU1ImmOperand(MI, 4, O); return; break; } // Fragment 4 encoded into 6 bits for 33 unique commands. // printf("Fragment 4 = %" PRIu64 "\n", (Bits >> 35) & 63); switch ((Bits >> 35) & 63) { default: // llvm_unreachable("Invalid command number."); case 0: // ADTR, ADTRA, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXT... printOperand(MI, 2, O); break; case 1: // AGHIK, AHIK, ALGHSIK, ALHSIK printS16ImmOperand(MI, 2, O); return; break; case 2: // BRXH, BRXHG, BRXLE, BRXLG, CGIJAsm, CIJAsm, CLGIJAsm, CLIJAsm printPCRelOperand(MI, 3, O); return; break; case 3: // BXH, BXHG, BXLE, BXLEG, CDS, CDSG, CDSY, CGIBAsm, CIBAsm, CLGIBAsm, CL... printBDAddrOperand(MI, 3, O); break; case 4: // CDFBRA, CDFTR, CDGBRA, CDGTRA, CDLFBR, CDLFTR, CDLGBR, CDLGTR, CEFBRA,... SStream_concat0(O, ", "); printU4ImmOperand(MI, 3, O); return; break; case 5: // CFDBR, CFDR, CFEBR, CFER, CFXBR, CFXR, CGDBR, CGDR, CGDTR, CGEBR, CGER... return; break; case 6: // CGITAsm, CGRBAsm, CGRJAsm, CGRTAsm, CITAsm, CLFITAsm, CLGITAsm, CLGRBA... printU4ImmOperand(MI, 2, O); break; case 7: // CGRBAsmE, CGRBAsmH, CGRBAsmHE, CGRBAsmL, CGRBAsmLE, CGRBAsmLH, CGRBAsm... printBDAddrOperand(MI, 2, O); break; case 8: // CGRJAsmE, CGRJAsmH, CGRJAsmHE, CGRJAsmL, CGRJAsmLE, CGRJAsmLH, CGRJAsm... printPCRelOperand(MI, 2, O); return; break; case 9: // CLCLE, CLCLU, MVCLE, MVCLU printBDAddrOperand(MI, 4, O); return; break; case 10: // CLGTAsm, CLTAsm printBDAddrOperand(MI, 1, O); return; break; case 11: // CPSDRdd, CPSDRds, CPSDRsd, CPSDRss, CRDTE, CRDTEOpt, IDTE, IDTEOpt, IE... printOperand(MI, 1, O); break; case 12: // CSST, ECTG, MVCOS printOperand(MI, 4, O); return; break; case 13: // CU12, CU14, CU21, CU24, CUTFU, CUUTF, LCBB, LOCAsm, LOCFHAsm, LOCGAsm,... printU4ImmOperand(MI, 4, O); return; break; case 14: // DIDBR, DIEBR, LPTEA, MADBR, MADR, MAEBR, MAER, MAYHR, MAYLR, MAYR, MSD... printOperand(MI, 3, O); break; case 15: // InsnRIE, InsnRRF, InsnRRS, InsnRS, InsnRSE, InsnRSI, InsnRSY, InsnRXF,... SStream_concat0(O, ","); break; case 16: // LOCFHRAsm, LOCGHIAsm, LOCGRAsm, LOCHHIAsm, LOCHIAsm, LOCRAsm, STOCAsm,... printU4ImmOperand(MI, 3, O); return; break; case 17: // MAD, MADB, MAE, MAEB, MAY, MAYH, MAYL, MSD, MSDB, MSE, MSEB printBDXAddrOperand(MI, 3, O); return; break; case 18: // MY, MYH, MYL, SLDT, SLXT, SRDT, SRXT printBDXAddrOperand(MI, 2, O); return; break; case 19: // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VLRL, VPK... printU8ImmOperand(MI, 3, O); break; case 20: // SRP, VLEB printU4ImmOperand(MI, 5, O); return; break; case 21: // VCVD, VCVDG, VPSOP, VSRP printU8ImmOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 22: // VFTCI, VFTCIDB, VFTCISB, WFTCIDB, WFTCISB, WFTCIXB printU12ImmOperand(MI, 2, O); break; case 23: // VLEF printU2ImmOperand(MI, 5, O); return; break; case 24: // VLEG printU1ImmOperand(MI, 5, O); return; break; case 25: // VLEH printU3ImmOperand(MI, 5, O); return; break; case 26: // VLEIF printU2ImmOperand(MI, 3, O); return; break; case 27: // VLEIG printU1ImmOperand(MI, 3, O); return; break; case 28: // VLEIH printU3ImmOperand(MI, 3, O); return; break; case 29: // VREP, VREPB, VREPF, VREPG, VREPH printU16ImmOperand(MI, 2, O); break; case 30: // VSTEF printU2ImmOperand(MI, 4, O); return; break; case 31: // VSTEG printU1ImmOperand(MI, 4, O); return; break; case 32: // VSTEH printU3ImmOperand(MI, 4, O); return; break; } // Fragment 5 encoded into 4 bits for 9 unique commands. // printf("Fragment 5 = %" PRIu64 "\n", (Bits >> 41) & 15); switch ((Bits >> 41) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // ADTR, AGRK, AHHHR, AHHLR, ALGRK, ALHHHR, ALHHLR, ALRK, ARK, AXTR, BXH,... return; break; case 1: // ADTRA, AXTRA, CGRBAsm, CGRJAsm, CLGRBAsm, CLGRJAsm, CLRBAsm, CLRJAsm, ... SStream_concat0(O, ", "); break; case 2: // InsnRIE, InsnRSI printPCRelOperand(MI, 3, O); return; break; case 3: // InsnRRF printOperand(MI, 3, O); SStream_concat0(O, ","); printU4ImmOperand(MI, 4, O); return; break; case 4: // InsnRRS, VCVD, VCVDG printU4ImmOperand(MI, 3, O); break; case 5: // InsnRS, InsnRSE, InsnRSY printBDAddrOperand(MI, 3, O); return; break; case 6: // InsnRXF printBDXAddrOperand(MI, 3, O); return; break; case 7: // InsnSSF printOperand(MI, 5, O); return; break; case 8: // VPSOP, VSRP printU8ImmOperand(MI, 3, O); SStream_concat0(O, ", "); printU4ImmOperand(MI, 4, O); return; break; } // Fragment 6 encoded into 4 bits for 11 unique commands. // printf("Fragment 6 = %" PRIu64 "\n", (Bits >> 45) & 15); switch ((Bits >> 45) & 15) { default: // llvm_unreachable("Invalid command number."); case 0: // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, SDTRA, SX... printU4ImmOperand(MI, 3, O); break; case 1: // CGRBAsm, CLGRBAsm, CLRBAsm, CRBAsm printBDAddrOperand(MI, 3, O); return; break; case 2: // CGRJAsm, CLGRJAsm, CLRJAsm, CRJAsm printPCRelOperand(MI, 3, O); return; break; case 3: // DIDBR, DIEBR, LPTEA, QADTR, QAXTR, RRDTR, RRXTR, VERLL, VESL, VESRA, V... printU4ImmOperand(MI, 4, O); return; break; case 4: // InsnRRS SStream_concat0(O, ","); printBDAddrOperand(MI, 4, O); return; break; case 5: // LMD, PLO printBDAddrOperand(MI, 4, O); return; break; case 6: // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VERIM, VE... printU8ImmOperand(MI, 4, O); break; case 7: // VAC, VACCC, VACCCQ, VACQ, VFMA, VFMADB, VFMASB, VFMS, VFMSDB, VFMSSB, ... printOperand(MI, 3, O); break; case 8: // VAP, VDP, VMP, VMSP, VRP, VSDP, VSLDB, VSP printU8ImmOperand(MI, 3, O); break; case 9: // VCVD, VCVDG return; break; case 10: // VLVG printU4ImmOperand(MI, 5, O); return; break; } // Fragment 7 encoded into 1 bits for 2 unique commands. // printf("Fragment 7 = %" PRIu64 "\n", (Bits >> 49) & 1); if ((Bits >> 49) & 1) { // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG, VAC, VACC... SStream_concat0(O, ", "); } else { // ADTRA, AXTRA, CRDTE, DDTRA, DXTRA, IDTE, IPTE, MDTRA, MXTRA, SDTRA, SX... return; } // Fragment 8 encoded into 2 bits for 3 unique commands. // printf("Fragment 8 = %" PRIu64 "\n", (Bits >> 50) & 3); switch ((Bits >> 50) & 3) { default: // llvm_unreachable("Invalid command number."); case 0: // RISBG, RISBG32, RISBGN, RISBHG, RISBLG, RNSBG, ROSBG, RXSBG printU6ImmOperand(MI, 5, O); return; break; case 1: // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... printU4ImmOperand(MI, 4, O); break; case 2: // VERIM printU4ImmOperand(MI, 5, O); return; break; } // Fragment 9 encoded into 1 bits for 2 unique commands. // printf("Fragment 9 = %" PRIu64 "\n", (Bits >> 52) & 1); if ((Bits >> 52) & 1) { // VFCE, VFCH, VFCHE, VFMA, VFMAX, VFMIN, VFMS, VFNMA, VFNMS, VMSL, VSTRC SStream_concat0(O, ", "); printU4ImmOperand(MI, 5, O); return; } else { // VAC, VACCC, VAP, VCDG, VCDLG, VCEQ, VCGD, VCH, VCHL, VCLGD, VDP, VFA, ... return; } } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 194 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'a', '1', '0', 0, /* 4 */ 'c', '1', '0', 0, /* 8 */ 'f', '1', '0', 0, /* 12 */ 'r', '1', '0', 0, /* 16 */ 'v', '1', '0', 0, /* 20 */ 'v', '2', '0', 0, /* 24 */ 'v', '3', '0', 0, /* 28 */ 'a', '0', 0, /* 31 */ 'c', '0', 0, /* 34 */ 'f', '0', 0, /* 37 */ 'r', '0', 0, /* 40 */ 'v', '0', 0, /* 43 */ 'a', '1', '1', 0, /* 47 */ 'c', '1', '1', 0, /* 51 */ 'f', '1', '1', 0, /* 55 */ 'r', '1', '1', 0, /* 59 */ 'v', '1', '1', 0, /* 63 */ 'v', '2', '1', 0, /* 67 */ 'v', '3', '1', 0, /* 71 */ 'a', '1', 0, /* 74 */ 'c', '1', 0, /* 77 */ 'f', '1', 0, /* 80 */ 'r', '1', 0, /* 83 */ 'v', '1', 0, /* 86 */ 'a', '1', '2', 0, /* 90 */ 'c', '1', '2', 0, /* 94 */ 'f', '1', '2', 0, /* 98 */ 'r', '1', '2', 0, /* 102 */ 'v', '1', '2', 0, /* 106 */ 'v', '2', '2', 0, /* 110 */ 'a', '2', 0, /* 113 */ 'c', '2', 0, /* 116 */ 'f', '2', 0, /* 119 */ 'r', '2', 0, /* 122 */ 'v', '2', 0, /* 125 */ 'a', '1', '3', 0, /* 129 */ 'c', '1', '3', 0, /* 133 */ 'f', '1', '3', 0, /* 137 */ 'r', '1', '3', 0, /* 141 */ 'v', '1', '3', 0, /* 145 */ 'v', '2', '3', 0, /* 149 */ 'a', '3', 0, /* 152 */ 'c', '3', 0, /* 155 */ 'f', '3', 0, /* 158 */ 'r', '3', 0, /* 161 */ 'v', '3', 0, /* 164 */ 'a', '1', '4', 0, /* 168 */ 'c', '1', '4', 0, /* 172 */ 'f', '1', '4', 0, /* 176 */ 'r', '1', '4', 0, /* 180 */ 'v', '1', '4', 0, /* 184 */ 'v', '2', '4', 0, /* 188 */ 'a', '4', 0, /* 191 */ 'c', '4', 0, /* 194 */ 'f', '4', 0, /* 197 */ 'r', '4', 0, /* 200 */ 'v', '4', 0, /* 203 */ 'a', '1', '5', 0, /* 207 */ 'c', '1', '5', 0, /* 211 */ 'f', '1', '5', 0, /* 215 */ 'r', '1', '5', 0, /* 219 */ 'v', '1', '5', 0, /* 223 */ 'v', '2', '5', 0, /* 227 */ 'a', '5', 0, /* 230 */ 'c', '5', 0, /* 233 */ 'f', '5', 0, /* 236 */ 'r', '5', 0, /* 239 */ 'v', '5', 0, /* 242 */ 'v', '1', '6', 0, /* 246 */ 'v', '2', '6', 0, /* 250 */ 'a', '6', 0, /* 253 */ 'c', '6', 0, /* 256 */ 'f', '6', 0, /* 259 */ 'r', '6', 0, /* 262 */ 'v', '6', 0, /* 265 */ 'v', '1', '7', 0, /* 269 */ 'v', '2', '7', 0, /* 273 */ 'a', '7', 0, /* 276 */ 'c', '7', 0, /* 279 */ 'f', '7', 0, /* 282 */ 'r', '7', 0, /* 285 */ 'v', '7', 0, /* 288 */ 'v', '1', '8', 0, /* 292 */ 'v', '2', '8', 0, /* 296 */ 'a', '8', 0, /* 299 */ 'c', '8', 0, /* 302 */ 'f', '8', 0, /* 305 */ 'r', '8', 0, /* 308 */ 'v', '8', 0, /* 311 */ 'v', '1', '9', 0, /* 315 */ 'v', '2', '9', 0, /* 319 */ 'a', '9', 0, /* 322 */ 'c', '9', 0, /* 325 */ 'f', '9', 0, /* 328 */ 'r', '9', 0, /* 331 */ 'v', '9', 0, /* 334 */ 'c', 'c', 0, }; static const uint16_t RegAsmOffset[] = { 334, 28, 71, 110, 149, 188, 227, 250, 273, 296, 319, 0, 43, 86, 125, 164, 203, 31, 74, 113, 152, 191, 230, 253, 276, 299, 322, 4, 47, 90, 129, 168, 207, 40, 83, 122, 161, 200, 239, 262, 285, 308, 331, 16, 59, 102, 141, 180, 219, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 116, 155, 194, 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 34, 77, 194, 233, 302, 325, 94, 133, 34, 77, 116, 155, 194, 233, 256, 279, 302, 325, 8, 51, 94, 133, 172, 211, 242, 265, 288, 311, 20, 63, 106, 145, 184, 223, 246, 269, 292, 315, 24, 67, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, 37, 80, 119, 158, 197, 236, 259, 282, 305, 328, 12, 55, 98, 137, 176, 215, 37, 119, 197, 259, 305, 12, 98, 176, }; //int i; //for (i = 0; i < sizeof(RegAsmOffset); i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); //printf("*************************\n"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc000064400000000000000000023070760072674642500250110ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * SystemZ Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTable16[] = { /* 0 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... /* 3 */ MCD_OPC_FilterValue, 1, 84, 0, // Skip to: 91 /* 7 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 10 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 18 /* 14 */ MCD_OPC_Decode, 149, 14, 0, // Opcode: PR /* 18 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 26 /* 22 */ MCD_OPC_Decode, 209, 16, 0, // Opcode: UPT /* 26 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 34 /* 30 */ MCD_OPC_Decode, 153, 14, 0, // Opcode: PTFF /* 34 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 42 /* 38 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: SCKPF /* 42 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 50 /* 46 */ MCD_OPC_Decode, 140, 14, 0, // Opcode: PFPO /* 50 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 58 /* 54 */ MCD_OPC_Decode, 156, 16, 0, // Opcode: TAM /* 58 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 66 /* 62 */ MCD_OPC_Decode, 181, 14, 0, // Opcode: SAM24 /* 66 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 74 /* 70 */ MCD_OPC_Decode, 182, 14, 0, // Opcode: SAM31 /* 74 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 82 /* 78 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: SAM64 /* 82 */ MCD_OPC_FilterValue, 255, 1, 85, 2, // Skip to: 684 /* 87 */ MCD_OPC_Decode, 187, 16, 0, // Opcode: TRAP2 /* 91 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 105 /* 95 */ MCD_OPC_CheckField, 0, 4, 0, 71, 2, // Skip to: 684 /* 101 */ MCD_OPC_Decode, 245, 14, 1, // Opcode: SPM /* 105 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 113 /* 109 */ MCD_OPC_Decode, 168, 3, 2, // Opcode: BALR /* 113 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 121 /* 117 */ MCD_OPC_Decode, 199, 3, 3, // Opcode: BCTR /* 121 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 252 /* 125 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... /* 128 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 136 /* 132 */ MCD_OPC_Decode, 245, 3, 4, // Opcode: BRAsmO /* 136 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 144 /* 140 */ MCD_OPC_Decode, 229, 3, 4, // Opcode: BRAsmH /* 144 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 152 /* 148 */ MCD_OPC_Decode, 239, 3, 4, // Opcode: BRAsmNLE /* 152 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 160 /* 156 */ MCD_OPC_Decode, 231, 3, 4, // Opcode: BRAsmL /* 160 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 168 /* 164 */ MCD_OPC_Decode, 237, 3, 4, // Opcode: BRAsmNHE /* 168 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 176 /* 172 */ MCD_OPC_Decode, 233, 3, 4, // Opcode: BRAsmLH /* 176 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 184 /* 180 */ MCD_OPC_Decode, 235, 3, 4, // Opcode: BRAsmNE /* 184 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 192 /* 188 */ MCD_OPC_Decode, 228, 3, 4, // Opcode: BRAsmE /* 192 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 200 /* 196 */ MCD_OPC_Decode, 240, 3, 4, // Opcode: BRAsmNLH /* 200 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 208 /* 204 */ MCD_OPC_Decode, 230, 3, 4, // Opcode: BRAsmHE /* 208 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 216 /* 212 */ MCD_OPC_Decode, 238, 3, 4, // Opcode: BRAsmNL /* 216 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 224 /* 220 */ MCD_OPC_Decode, 232, 3, 4, // Opcode: BRAsmLE /* 224 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 232 /* 228 */ MCD_OPC_Decode, 236, 3, 4, // Opcode: BRAsmNH /* 232 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 240 /* 236 */ MCD_OPC_Decode, 242, 3, 4, // Opcode: BRAsmNO /* 240 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 248 /* 244 */ MCD_OPC_Decode, 225, 3, 4, // Opcode: BR /* 248 */ MCD_OPC_Decode, 195, 3, 5, // Opcode: BCRAsm /* 252 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 260 /* 256 */ MCD_OPC_Decode, 147, 16, 6, // Opcode: SVC /* 260 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 268 /* 264 */ MCD_OPC_Decode, 133, 4, 2, // Opcode: BSM /* 268 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 276 /* 272 */ MCD_OPC_Decode, 171, 3, 2, // Opcode: BASSM /* 276 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 284 /* 280 */ MCD_OPC_Decode, 170, 3, 2, // Opcode: BASR /* 284 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 292 /* 288 */ MCD_OPC_Decode, 195, 13, 7, // Opcode: MVCL /* 292 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 300 /* 296 */ MCD_OPC_Decode, 226, 5, 7, // Opcode: CLCL /* 300 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 308 /* 304 */ MCD_OPC_Decode, 196, 12, 8, // Opcode: LPR /* 308 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 316 /* 312 */ MCD_OPC_Decode, 238, 10, 8, // Opcode: LNR /* 316 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 324 /* 320 */ MCD_OPC_Decode, 227, 12, 8, // Opcode: LTR /* 324 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 332 /* 328 */ MCD_OPC_Decode, 141, 10, 8, // Opcode: LCR /* 332 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 340 /* 336 */ MCD_OPC_Decode, 240, 13, 9, // Opcode: NR /* 340 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 348 /* 344 */ MCD_OPC_Decode, 145, 7, 8, // Opcode: CLR /* 348 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 356 /* 352 */ MCD_OPC_Decode, 129, 14, 9, // Opcode: OR /* 356 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 364 /* 360 */ MCD_OPC_Decode, 235, 21, 9, // Opcode: XR /* 364 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 372 /* 368 */ MCD_OPC_Decode, 202, 12, 8, // Opcode: LR /* 372 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 380 /* 376 */ MCD_OPC_Decode, 214, 7, 8, // Opcode: CR /* 380 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 388 /* 384 */ MCD_OPC_Decode, 153, 3, 9, // Opcode: AR /* 388 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 396 /* 392 */ MCD_OPC_Decode, 130, 15, 9, // Opcode: SR /* 396 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 404 /* 400 */ MCD_OPC_Decode, 167, 13, 10, // Opcode: MR /* 404 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 412 /* 408 */ MCD_OPC_Decode, 206, 8, 10, // Opcode: DR /* 412 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 420 /* 416 */ MCD_OPC_Decode, 146, 3, 9, // Opcode: ALR /* 420 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 428 /* 424 */ MCD_OPC_Decode, 238, 14, 9, // Opcode: SLR /* 428 */ MCD_OPC_FilterValue, 32, 4, 0, // Skip to: 436 /* 432 */ MCD_OPC_Decode, 189, 12, 11, // Opcode: LPDR /* 436 */ MCD_OPC_FilterValue, 33, 4, 0, // Skip to: 444 /* 440 */ MCD_OPC_Decode, 233, 10, 11, // Opcode: LNDR /* 444 */ MCD_OPC_FilterValue, 34, 4, 0, // Skip to: 452 /* 448 */ MCD_OPC_Decode, 218, 12, 11, // Opcode: LTDR /* 452 */ MCD_OPC_FilterValue, 35, 4, 0, // Skip to: 460 /* 456 */ MCD_OPC_Decode, 136, 10, 11, // Opcode: LCDR /* 460 */ MCD_OPC_FilterValue, 36, 4, 0, // Skip to: 468 /* 464 */ MCD_OPC_Decode, 252, 8, 11, // Opcode: HDR /* 468 */ MCD_OPC_FilterValue, 37, 4, 0, // Skip to: 476 /* 472 */ MCD_OPC_Decode, 158, 10, 12, // Opcode: LDXR /* 476 */ MCD_OPC_FilterValue, 38, 4, 0, // Skip to: 484 /* 480 */ MCD_OPC_Decode, 217, 13, 13, // Opcode: MXR /* 484 */ MCD_OPC_FilterValue, 39, 4, 0, // Skip to: 492 /* 488 */ MCD_OPC_Decode, 216, 13, 14, // Opcode: MXDR /* 492 */ MCD_OPC_FilterValue, 40, 4, 0, // Skip to: 500 /* 496 */ MCD_OPC_Decode, 154, 10, 11, // Opcode: LDR /* 500 */ MCD_OPC_FilterValue, 41, 4, 0, // Skip to: 508 /* 504 */ MCD_OPC_Decode, 156, 4, 11, // Opcode: CDR /* 508 */ MCD_OPC_FilterValue, 42, 4, 0, // Skip to: 516 /* 512 */ MCD_OPC_Decode, 232, 2, 15, // Opcode: ADR /* 516 */ MCD_OPC_FilterValue, 43, 4, 0, // Skip to: 524 /* 520 */ MCD_OPC_Decode, 193, 14, 15, // Opcode: SDR /* 524 */ MCD_OPC_FilterValue, 44, 4, 0, // Skip to: 532 /* 528 */ MCD_OPC_Decode, 145, 13, 15, // Opcode: MDR /* 532 */ MCD_OPC_FilterValue, 45, 4, 0, // Skip to: 540 /* 536 */ MCD_OPC_Decode, 191, 8, 15, // Opcode: DDR /* 540 */ MCD_OPC_FilterValue, 46, 4, 0, // Skip to: 548 /* 544 */ MCD_OPC_Decode, 159, 3, 15, // Opcode: AWR /* 548 */ MCD_OPC_FilterValue, 47, 4, 0, // Skip to: 556 /* 552 */ MCD_OPC_Decode, 149, 16, 15, // Opcode: SWR /* 556 */ MCD_OPC_FilterValue, 48, 4, 0, // Skip to: 564 /* 560 */ MCD_OPC_Decode, 191, 12, 16, // Opcode: LPER /* 564 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 572 /* 568 */ MCD_OPC_Decode, 235, 10, 16, // Opcode: LNER /* 572 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 580 /* 576 */ MCD_OPC_Decode, 222, 12, 16, // Opcode: LTER /* 580 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 588 /* 584 */ MCD_OPC_Decode, 138, 10, 16, // Opcode: LCER /* 588 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 596 /* 592 */ MCD_OPC_Decode, 253, 8, 16, // Opcode: HER /* 596 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 604 /* 600 */ MCD_OPC_Decode, 164, 10, 17, // Opcode: LEDR /* 604 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 612 /* 608 */ MCD_OPC_Decode, 161, 3, 13, // Opcode: AXR /* 612 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 620 /* 616 */ MCD_OPC_Decode, 151, 16, 13, // Opcode: SXR /* 620 */ MCD_OPC_FilterValue, 56, 4, 0, // Skip to: 628 /* 624 */ MCD_OPC_Decode, 166, 10, 16, // Opcode: LER /* 628 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 636 /* 632 */ MCD_OPC_Decode, 176, 4, 16, // Opcode: CER /* 636 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 644 /* 640 */ MCD_OPC_Decode, 238, 2, 18, // Opcode: AER /* 644 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 652 /* 648 */ MCD_OPC_Decode, 199, 14, 18, // Opcode: SER /* 652 */ MCD_OPC_FilterValue, 60, 4, 0, // Skip to: 660 /* 656 */ MCD_OPC_Decode, 144, 13, 19, // Opcode: MDER /* 660 */ MCD_OPC_FilterValue, 61, 4, 0, // Skip to: 668 /* 664 */ MCD_OPC_Decode, 197, 8, 18, // Opcode: DER /* 668 */ MCD_OPC_FilterValue, 62, 4, 0, // Skip to: 676 /* 672 */ MCD_OPC_Decode, 157, 3, 18, // Opcode: AUR /* 676 */ MCD_OPC_FilterValue, 63, 4, 0, // Skip to: 684 /* 680 */ MCD_OPC_Decode, 146, 16, 18, // Opcode: SUR /* 684 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 3 */ MCD_OPC_FilterValue, 64, 4, 0, // Skip to: 11 /* 7 */ MCD_OPC_Decode, 183, 15, 20, // Opcode: STH /* 11 */ MCD_OPC_FilterValue, 65, 4, 0, // Skip to: 19 /* 15 */ MCD_OPC_Decode, 237, 9, 21, // Opcode: LA /* 19 */ MCD_OPC_FilterValue, 66, 4, 0, // Skip to: 27 /* 23 */ MCD_OPC_Decode, 158, 15, 20, // Opcode: STC /* 27 */ MCD_OPC_FilterValue, 67, 4, 0, // Skip to: 35 /* 31 */ MCD_OPC_Decode, 128, 9, 22, // Opcode: IC /* 35 */ MCD_OPC_FilterValue, 68, 4, 0, // Skip to: 43 /* 39 */ MCD_OPC_Decode, 238, 8, 21, // Opcode: EX /* 43 */ MCD_OPC_FilterValue, 69, 4, 0, // Skip to: 51 /* 47 */ MCD_OPC_Decode, 167, 3, 21, // Opcode: BAL /* 51 */ MCD_OPC_FilterValue, 70, 4, 0, // Skip to: 59 /* 55 */ MCD_OPC_Decode, 196, 3, 23, // Opcode: BCT /* 59 */ MCD_OPC_FilterValue, 71, 127, 0, // Skip to: 190 /* 63 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 66 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 74 /* 70 */ MCD_OPC_Decode, 189, 3, 24, // Opcode: BAsmO /* 74 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 82 /* 78 */ MCD_OPC_Decode, 173, 3, 24, // Opcode: BAsmH /* 82 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 90 /* 86 */ MCD_OPC_Decode, 183, 3, 24, // Opcode: BAsmNLE /* 90 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 98 /* 94 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: BAsmL /* 98 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 106 /* 102 */ MCD_OPC_Decode, 181, 3, 24, // Opcode: BAsmNHE /* 106 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 114 /* 110 */ MCD_OPC_Decode, 177, 3, 24, // Opcode: BAsmLH /* 114 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 122 /* 118 */ MCD_OPC_Decode, 179, 3, 24, // Opcode: BAsmNE /* 122 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 130 /* 126 */ MCD_OPC_Decode, 172, 3, 24, // Opcode: BAsmE /* 130 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 138 /* 134 */ MCD_OPC_Decode, 184, 3, 24, // Opcode: BAsmNLH /* 138 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 146 /* 142 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: BAsmHE /* 146 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 154 /* 150 */ MCD_OPC_Decode, 182, 3, 24, // Opcode: BAsmNL /* 154 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 162 /* 158 */ MCD_OPC_Decode, 176, 3, 24, // Opcode: BAsmLE /* 162 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 170 /* 166 */ MCD_OPC_Decode, 180, 3, 24, // Opcode: BAsmNH /* 170 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 178 /* 174 */ MCD_OPC_Decode, 186, 3, 24, // Opcode: BAsmNO /* 178 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 186 /* 182 */ MCD_OPC_Decode, 165, 3, 24, // Opcode: B /* 186 */ MCD_OPC_Decode, 193, 3, 25, // Opcode: BCAsm /* 190 */ MCD_OPC_FilterValue, 72, 4, 0, // Skip to: 198 /* 194 */ MCD_OPC_Decode, 192, 10, 20, // Opcode: LH /* 198 */ MCD_OPC_FilterValue, 73, 4, 0, // Skip to: 206 /* 202 */ MCD_OPC_Decode, 171, 5, 20, // Opcode: CH /* 206 */ MCD_OPC_FilterValue, 74, 4, 0, // Skip to: 214 /* 210 */ MCD_OPC_Decode, 250, 2, 23, // Opcode: AH /* 214 */ MCD_OPC_FilterValue, 75, 4, 0, // Skip to: 222 /* 218 */ MCD_OPC_Decode, 208, 14, 23, // Opcode: SH /* 222 */ MCD_OPC_FilterValue, 76, 4, 0, // Skip to: 230 /* 226 */ MCD_OPC_Decode, 159, 13, 23, // Opcode: MH /* 230 */ MCD_OPC_FilterValue, 77, 4, 0, // Skip to: 238 /* 234 */ MCD_OPC_Decode, 169, 3, 21, // Opcode: BAS /* 238 */ MCD_OPC_FilterValue, 78, 4, 0, // Skip to: 246 /* 242 */ MCD_OPC_Decode, 161, 8, 20, // Opcode: CVD /* 246 */ MCD_OPC_FilterValue, 79, 4, 0, // Skip to: 254 /* 250 */ MCD_OPC_Decode, 158, 8, 23, // Opcode: CVB /* 254 */ MCD_OPC_FilterValue, 80, 4, 0, // Skip to: 262 /* 258 */ MCD_OPC_Decode, 154, 15, 20, // Opcode: ST /* 262 */ MCD_OPC_FilterValue, 81, 4, 0, // Skip to: 270 /* 266 */ MCD_OPC_Decode, 242, 9, 21, // Opcode: LAE /* 270 */ MCD_OPC_FilterValue, 84, 4, 0, // Skip to: 278 /* 274 */ MCD_OPC_Decode, 226, 13, 23, // Opcode: N /* 278 */ MCD_OPC_FilterValue, 85, 4, 0, // Skip to: 286 /* 282 */ MCD_OPC_Decode, 224, 5, 20, // Opcode: CL /* 286 */ MCD_OPC_FilterValue, 86, 4, 0, // Skip to: 294 /* 290 */ MCD_OPC_Decode, 244, 13, 23, // Opcode: O /* 294 */ MCD_OPC_FilterValue, 87, 4, 0, // Skip to: 302 /* 298 */ MCD_OPC_Decode, 226, 21, 23, // Opcode: X /* 302 */ MCD_OPC_FilterValue, 88, 4, 0, // Skip to: 310 /* 306 */ MCD_OPC_Decode, 236, 9, 20, // Opcode: L /* 310 */ MCD_OPC_FilterValue, 89, 4, 0, // Skip to: 318 /* 314 */ MCD_OPC_Decode, 138, 4, 20, // Opcode: C /* 318 */ MCD_OPC_FilterValue, 90, 4, 0, // Skip to: 326 /* 322 */ MCD_OPC_Decode, 228, 2, 23, // Opcode: A /* 326 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 334 /* 330 */ MCD_OPC_Decode, 177, 14, 23, // Opcode: S /* 334 */ MCD_OPC_FilterValue, 92, 4, 0, // Skip to: 342 /* 338 */ MCD_OPC_Decode, 250, 12, 26, // Opcode: M /* 342 */ MCD_OPC_FilterValue, 93, 4, 0, // Skip to: 350 /* 346 */ MCD_OPC_Decode, 187, 8, 26, // Opcode: D /* 350 */ MCD_OPC_FilterValue, 94, 4, 0, // Skip to: 358 /* 354 */ MCD_OPC_Decode, 129, 3, 23, // Opcode: AL /* 358 */ MCD_OPC_FilterValue, 95, 4, 0, // Skip to: 366 /* 362 */ MCD_OPC_Decode, 215, 14, 23, // Opcode: SL /* 366 */ MCD_OPC_FilterValue, 96, 4, 0, // Skip to: 374 /* 370 */ MCD_OPC_Decode, 172, 15, 27, // Opcode: STD /* 374 */ MCD_OPC_FilterValue, 103, 4, 0, // Skip to: 382 /* 378 */ MCD_OPC_Decode, 213, 13, 28, // Opcode: MXD /* 382 */ MCD_OPC_FilterValue, 104, 4, 0, // Skip to: 390 /* 386 */ MCD_OPC_Decode, 146, 10, 27, // Opcode: LD /* 390 */ MCD_OPC_FilterValue, 105, 4, 0, // Skip to: 398 /* 394 */ MCD_OPC_Decode, 139, 4, 27, // Opcode: CD /* 398 */ MCD_OPC_FilterValue, 106, 4, 0, // Skip to: 406 /* 402 */ MCD_OPC_Decode, 229, 2, 29, // Opcode: AD /* 406 */ MCD_OPC_FilterValue, 107, 4, 0, // Skip to: 414 /* 410 */ MCD_OPC_Decode, 190, 14, 29, // Opcode: SD /* 414 */ MCD_OPC_FilterValue, 108, 4, 0, // Skip to: 422 /* 418 */ MCD_OPC_Decode, 138, 13, 29, // Opcode: MD /* 422 */ MCD_OPC_FilterValue, 109, 4, 0, // Skip to: 430 /* 426 */ MCD_OPC_Decode, 188, 8, 29, // Opcode: DD /* 430 */ MCD_OPC_FilterValue, 110, 4, 0, // Skip to: 438 /* 434 */ MCD_OPC_Decode, 158, 3, 29, // Opcode: AW /* 438 */ MCD_OPC_FilterValue, 111, 4, 0, // Skip to: 446 /* 442 */ MCD_OPC_Decode, 148, 16, 29, // Opcode: SW /* 446 */ MCD_OPC_FilterValue, 112, 4, 0, // Skip to: 454 /* 450 */ MCD_OPC_Decode, 174, 15, 30, // Opcode: STE /* 454 */ MCD_OPC_FilterValue, 113, 4, 0, // Skip to: 462 /* 458 */ MCD_OPC_Decode, 168, 13, 23, // Opcode: MS /* 462 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 470 /* 466 */ MCD_OPC_Decode, 161, 10, 30, // Opcode: LE /* 470 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 478 /* 474 */ MCD_OPC_Decode, 164, 4, 30, // Opcode: CE /* 478 */ MCD_OPC_FilterValue, 122, 4, 0, // Skip to: 486 /* 482 */ MCD_OPC_Decode, 235, 2, 31, // Opcode: AE /* 486 */ MCD_OPC_FilterValue, 123, 4, 0, // Skip to: 494 /* 490 */ MCD_OPC_Decode, 196, 14, 31, // Opcode: SE /* 494 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 502 /* 498 */ MCD_OPC_Decode, 141, 13, 29, // Opcode: MDE /* 502 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 510 /* 506 */ MCD_OPC_Decode, 194, 8, 31, // Opcode: DE /* 510 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 518 /* 514 */ MCD_OPC_Decode, 156, 3, 31, // Opcode: AU /* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 /* 522 */ MCD_OPC_Decode, 145, 16, 31, // Opcode: SU /* 526 */ MCD_OPC_FilterValue, 128, 1, 10, 0, // Skip to: 541 /* 531 */ MCD_OPC_CheckField, 16, 8, 0, 67, 31, // Skip to: 8540 /* 537 */ MCD_OPC_Decode, 153, 15, 32, // Opcode: SSM /* 541 */ MCD_OPC_FilterValue, 130, 1, 10, 0, // Skip to: 556 /* 546 */ MCD_OPC_CheckField, 16, 8, 0, 52, 31, // Skip to: 8540 /* 552 */ MCD_OPC_Decode, 197, 12, 32, // Opcode: LPSW /* 556 */ MCD_OPC_FilterValue, 131, 1, 4, 0, // Skip to: 565 /* 561 */ MCD_OPC_Decode, 198, 8, 33, // Opcode: DIAG /* 565 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 574 /* 570 */ MCD_OPC_Decode, 255, 3, 34, // Opcode: BRXH /* 574 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 583 /* 579 */ MCD_OPC_Decode, 129, 4, 34, // Opcode: BRXLE /* 583 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 592 /* 588 */ MCD_OPC_Decode, 134, 4, 35, // Opcode: BXH /* 592 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 601 /* 597 */ MCD_OPC_Decode, 136, 4, 35, // Opcode: BXLE /* 601 */ MCD_OPC_FilterValue, 136, 1, 10, 0, // Skip to: 616 /* 606 */ MCD_OPC_CheckField, 16, 4, 0, 248, 30, // Skip to: 8540 /* 612 */ MCD_OPC_Decode, 138, 15, 36, // Opcode: SRL /* 616 */ MCD_OPC_FilterValue, 137, 1, 10, 0, // Skip to: 631 /* 621 */ MCD_OPC_CheckField, 16, 4, 0, 233, 30, // Skip to: 8540 /* 627 */ MCD_OPC_Decode, 235, 14, 36, // Opcode: SLL /* 631 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 646 /* 636 */ MCD_OPC_CheckField, 16, 4, 0, 218, 30, // Skip to: 8540 /* 642 */ MCD_OPC_Decode, 131, 15, 36, // Opcode: SRA /* 646 */ MCD_OPC_FilterValue, 139, 1, 10, 0, // Skip to: 661 /* 651 */ MCD_OPC_CheckField, 16, 4, 0, 203, 30, // Skip to: 8540 /* 657 */ MCD_OPC_Decode, 216, 14, 36, // Opcode: SLA /* 661 */ MCD_OPC_FilterValue, 140, 1, 10, 0, // Skip to: 676 /* 666 */ MCD_OPC_CheckField, 16, 4, 0, 188, 30, // Skip to: 8540 /* 672 */ MCD_OPC_Decode, 135, 15, 37, // Opcode: SRDL /* 676 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 691 /* 681 */ MCD_OPC_CheckField, 16, 4, 0, 173, 30, // Skip to: 8540 /* 687 */ MCD_OPC_Decode, 224, 14, 37, // Opcode: SLDL /* 691 */ MCD_OPC_FilterValue, 142, 1, 10, 0, // Skip to: 706 /* 696 */ MCD_OPC_CheckField, 16, 4, 0, 158, 30, // Skip to: 8540 /* 702 */ MCD_OPC_Decode, 134, 15, 37, // Opcode: SRDA /* 706 */ MCD_OPC_FilterValue, 143, 1, 10, 0, // Skip to: 721 /* 711 */ MCD_OPC_CheckField, 16, 4, 0, 143, 30, // Skip to: 8540 /* 717 */ MCD_OPC_Decode, 223, 14, 37, // Opcode: SLDA /* 721 */ MCD_OPC_FilterValue, 144, 1, 4, 0, // Skip to: 730 /* 726 */ MCD_OPC_Decode, 188, 15, 33, // Opcode: STM /* 730 */ MCD_OPC_FilterValue, 145, 1, 4, 0, // Skip to: 739 /* 735 */ MCD_OPC_Decode, 175, 16, 38, // Opcode: TM /* 739 */ MCD_OPC_FilterValue, 146, 1, 4, 0, // Skip to: 748 /* 744 */ MCD_OPC_Decode, 205, 13, 38, // Opcode: MVI /* 748 */ MCD_OPC_FilterValue, 147, 1, 10, 0, // Skip to: 763 /* 753 */ MCD_OPC_CheckField, 16, 8, 0, 101, 30, // Skip to: 8540 /* 759 */ MCD_OPC_Decode, 204, 16, 32, // Opcode: TS /* 763 */ MCD_OPC_FilterValue, 148, 1, 4, 0, // Skip to: 772 /* 768 */ MCD_OPC_Decode, 231, 13, 38, // Opcode: NI /* 772 */ MCD_OPC_FilterValue, 149, 1, 4, 0, // Skip to: 781 /* 777 */ MCD_OPC_Decode, 239, 6, 38, // Opcode: CLI /* 781 */ MCD_OPC_FilterValue, 150, 1, 4, 0, // Skip to: 790 /* 786 */ MCD_OPC_Decode, 249, 13, 38, // Opcode: OI /* 790 */ MCD_OPC_FilterValue, 151, 1, 4, 0, // Skip to: 799 /* 795 */ MCD_OPC_Decode, 231, 21, 38, // Opcode: XI /* 799 */ MCD_OPC_FilterValue, 152, 1, 4, 0, // Skip to: 808 /* 804 */ MCD_OPC_Decode, 225, 10, 33, // Opcode: LM /* 808 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 817 /* 813 */ MCD_OPC_Decode, 185, 16, 33, // Opcode: TRACE /* 817 */ MCD_OPC_FilterValue, 154, 1, 4, 0, // Skip to: 826 /* 822 */ MCD_OPC_Decode, 244, 9, 39, // Opcode: LAM /* 826 */ MCD_OPC_FilterValue, 155, 1, 4, 0, // Skip to: 835 /* 831 */ MCD_OPC_Decode, 155, 15, 39, // Opcode: STAM /* 835 */ MCD_OPC_FilterValue, 165, 1, 131, 0, // Skip to: 971 /* 840 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 843 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 851 /* 847 */ MCD_OPC_Decode, 140, 9, 40, // Opcode: IIHH /* 851 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 859 /* 855 */ MCD_OPC_Decode, 141, 9, 40, // Opcode: IIHL /* 859 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 867 /* 863 */ MCD_OPC_Decode, 143, 9, 41, // Opcode: IILH /* 867 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 875 /* 871 */ MCD_OPC_Decode, 144, 9, 41, // Opcode: IILL /* 875 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 883 /* 879 */ MCD_OPC_Decode, 234, 13, 40, // Opcode: NIHH /* 883 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 891 /* 887 */ MCD_OPC_Decode, 235, 13, 40, // Opcode: NIHL /* 891 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 899 /* 895 */ MCD_OPC_Decode, 237, 13, 41, // Opcode: NILH /* 899 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 907 /* 903 */ MCD_OPC_Decode, 238, 13, 41, // Opcode: NILL /* 907 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 915 /* 911 */ MCD_OPC_Decode, 251, 13, 40, // Opcode: OIHH /* 915 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 923 /* 919 */ MCD_OPC_Decode, 252, 13, 40, // Opcode: OIHL /* 923 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 931 /* 927 */ MCD_OPC_Decode, 254, 13, 41, // Opcode: OILH /* 931 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 939 /* 935 */ MCD_OPC_Decode, 255, 13, 41, // Opcode: OILL /* 939 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 947 /* 943 */ MCD_OPC_Decode, 219, 10, 42, // Opcode: LLIHH /* 947 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 955 /* 951 */ MCD_OPC_Decode, 220, 10, 42, // Opcode: LLIHL /* 955 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 963 /* 959 */ MCD_OPC_Decode, 222, 10, 42, // Opcode: LLILH /* 963 */ MCD_OPC_FilterValue, 15, 149, 29, // Skip to: 8540 /* 967 */ MCD_OPC_Decode, 223, 10, 42, // Opcode: LLILL /* 971 */ MCD_OPC_FilterValue, 167, 1, 254, 0, // Skip to: 1230 /* 976 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 979 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 987 /* 983 */ MCD_OPC_Decode, 178, 16, 43, // Opcode: TMLH /* 987 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 995 /* 991 */ MCD_OPC_Decode, 179, 16, 43, // Opcode: TMLL /* 995 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1003 /* 999 */ MCD_OPC_Decode, 176, 16, 44, // Opcode: TMHH /* 1003 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1011 /* 1007 */ MCD_OPC_Decode, 177, 16, 44, // Opcode: TMHL /* 1011 */ MCD_OPC_FilterValue, 4, 127, 0, // Skip to: 1142 /* 1015 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 1018 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1026 /* 1022 */ MCD_OPC_Decode, 196, 9, 45, // Opcode: JAsmO /* 1026 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1034 /* 1030 */ MCD_OPC_Decode, 180, 9, 45, // Opcode: JAsmH /* 1034 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1042 /* 1038 */ MCD_OPC_Decode, 190, 9, 45, // Opcode: JAsmNLE /* 1042 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1050 /* 1046 */ MCD_OPC_Decode, 182, 9, 45, // Opcode: JAsmL /* 1050 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1058 /* 1054 */ MCD_OPC_Decode, 188, 9, 45, // Opcode: JAsmNHE /* 1058 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1066 /* 1062 */ MCD_OPC_Decode, 184, 9, 45, // Opcode: JAsmLH /* 1066 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1074 /* 1070 */ MCD_OPC_Decode, 186, 9, 45, // Opcode: JAsmNE /* 1074 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1082 /* 1078 */ MCD_OPC_Decode, 179, 9, 45, // Opcode: JAsmE /* 1082 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1090 /* 1086 */ MCD_OPC_Decode, 191, 9, 45, // Opcode: JAsmNLH /* 1090 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1098 /* 1094 */ MCD_OPC_Decode, 181, 9, 45, // Opcode: JAsmHE /* 1098 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1106 /* 1102 */ MCD_OPC_Decode, 189, 9, 45, // Opcode: JAsmNL /* 1106 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1114 /* 1110 */ MCD_OPC_Decode, 183, 9, 45, // Opcode: JAsmLE /* 1114 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1122 /* 1118 */ MCD_OPC_Decode, 187, 9, 45, // Opcode: JAsmNH /* 1122 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1130 /* 1126 */ MCD_OPC_Decode, 193, 9, 45, // Opcode: JAsmNO /* 1130 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1138 /* 1134 */ MCD_OPC_Decode, 178, 9, 45, // Opcode: J /* 1138 */ MCD_OPC_Decode, 249, 3, 46, // Opcode: BRCAsm /* 1142 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1150 /* 1146 */ MCD_OPC_Decode, 226, 3, 47, // Opcode: BRAS /* 1150 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1158 /* 1154 */ MCD_OPC_Decode, 252, 3, 48, // Opcode: BRCT /* 1158 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1166 /* 1162 */ MCD_OPC_Decode, 253, 3, 49, // Opcode: BRCTG /* 1166 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1174 /* 1170 */ MCD_OPC_Decode, 194, 10, 50, // Opcode: LHI /* 1174 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1182 /* 1178 */ MCD_OPC_Decode, 186, 10, 51, // Opcode: LGHI /* 1182 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1190 /* 1186 */ MCD_OPC_Decode, 253, 2, 52, // Opcode: AHI /* 1190 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1198 /* 1194 */ MCD_OPC_Decode, 245, 2, 53, // Opcode: AGHI /* 1198 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1206 /* 1202 */ MCD_OPC_Decode, 160, 13, 52, // Opcode: MHI /* 1206 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1214 /* 1210 */ MCD_OPC_Decode, 157, 13, 53, // Opcode: MGHI /* 1214 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1222 /* 1218 */ MCD_OPC_Decode, 175, 5, 50, // Opcode: CHI /* 1222 */ MCD_OPC_FilterValue, 15, 146, 28, // Skip to: 8540 /* 1226 */ MCD_OPC_Decode, 205, 4, 51, // Opcode: CGHI /* 1230 */ MCD_OPC_FilterValue, 168, 1, 4, 0, // Skip to: 1239 /* 1235 */ MCD_OPC_Decode, 196, 13, 54, // Opcode: MVCLE /* 1239 */ MCD_OPC_FilterValue, 169, 1, 4, 0, // Skip to: 1248 /* 1244 */ MCD_OPC_Decode, 227, 5, 54, // Opcode: CLCLE /* 1248 */ MCD_OPC_FilterValue, 172, 1, 4, 0, // Skip to: 1257 /* 1253 */ MCD_OPC_Decode, 192, 15, 38, // Opcode: STNSM /* 1257 */ MCD_OPC_FilterValue, 173, 1, 4, 0, // Skip to: 1266 /* 1262 */ MCD_OPC_Decode, 131, 16, 38, // Opcode: STOSM /* 1266 */ MCD_OPC_FilterValue, 174, 1, 4, 0, // Skip to: 1275 /* 1271 */ MCD_OPC_Decode, 214, 14, 55, // Opcode: SIGP /* 1275 */ MCD_OPC_FilterValue, 175, 1, 4, 0, // Skip to: 1284 /* 1280 */ MCD_OPC_Decode, 137, 13, 38, // Opcode: MC /* 1284 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 1293 /* 1289 */ MCD_OPC_Decode, 203, 12, 21, // Opcode: LRA /* 1293 */ MCD_OPC_FilterValue, 178, 1, 65, 5, // Skip to: 2643 /* 1298 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 1301 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1309 /* 1305 */ MCD_OPC_Decode, 187, 15, 32, // Opcode: STIDP /* 1309 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1317 /* 1313 */ MCD_OPC_Decode, 187, 14, 32, // Opcode: SCK /* 1317 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1325 /* 1321 */ MCD_OPC_Decode, 160, 15, 32, // Opcode: STCK /* 1325 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 1333 /* 1329 */ MCD_OPC_Decode, 188, 14, 32, // Opcode: SCKC /* 1333 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1341 /* 1337 */ MCD_OPC_Decode, 161, 15, 32, // Opcode: STCKC /* 1341 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1349 /* 1345 */ MCD_OPC_Decode, 246, 14, 32, // Opcode: SPT /* 1349 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1357 /* 1353 */ MCD_OPC_Decode, 133, 16, 32, // Opcode: STPT /* 1357 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1365 /* 1361 */ MCD_OPC_Decode, 244, 14, 32, // Opcode: SPKA /* 1365 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 1379 /* 1369 */ MCD_OPC_CheckField, 0, 16, 0, 253, 27, // Skip to: 8540 /* 1375 */ MCD_OPC_Decode, 145, 9, 0, // Opcode: IPK /* 1379 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 1393 /* 1383 */ MCD_OPC_CheckField, 0, 16, 0, 239, 27, // Skip to: 8540 /* 1389 */ MCD_OPC_Decode, 155, 14, 0, // Opcode: PTLB /* 1393 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 1401 /* 1397 */ MCD_OPC_Decode, 247, 14, 32, // Opcode: SPX /* 1401 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1409 /* 1405 */ MCD_OPC_Decode, 134, 16, 32, // Opcode: STPX /* 1409 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1417 /* 1413 */ MCD_OPC_Decode, 157, 15, 32, // Opcode: STAP /* 1417 */ MCD_OPC_FilterValue, 20, 4, 0, // Skip to: 1425 /* 1421 */ MCD_OPC_Decode, 212, 14, 32, // Opcode: SIE /* 1425 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1433 /* 1429 */ MCD_OPC_Decode, 134, 14, 32, // Opcode: PC /* 1433 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1441 /* 1437 */ MCD_OPC_Decode, 178, 14, 32, // Opcode: SAC /* 1441 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1449 /* 1445 */ MCD_OPC_Decode, 178, 4, 32, // Opcode: CFC /* 1449 */ MCD_OPC_FilterValue, 33, 24, 0, // Skip to: 1477 /* 1453 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 1463 /* 1459 */ MCD_OPC_Decode, 149, 9, 56, // Opcode: IPTEOptOpt /* 1463 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 1473 /* 1469 */ MCD_OPC_Decode, 148, 9, 57, // Opcode: IPTEOpt /* 1473 */ MCD_OPC_Decode, 147, 9, 58, // Opcode: IPTE /* 1477 */ MCD_OPC_FilterValue, 34, 16, 0, // Skip to: 1497 /* 1481 */ MCD_OPC_CheckField, 8, 8, 0, 141, 27, // Skip to: 8540 /* 1487 */ MCD_OPC_CheckField, 0, 4, 0, 135, 27, // Skip to: 8540 /* 1493 */ MCD_OPC_Decode, 146, 9, 1, // Opcode: IPM /* 1497 */ MCD_OPC_FilterValue, 35, 10, 0, // Skip to: 1511 /* 1501 */ MCD_OPC_CheckField, 8, 8, 0, 121, 27, // Skip to: 8540 /* 1507 */ MCD_OPC_Decode, 152, 9, 3, // Opcode: IVSK /* 1511 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1531 /* 1515 */ MCD_OPC_CheckField, 8, 8, 0, 107, 27, // Skip to: 8540 /* 1521 */ MCD_OPC_CheckField, 0, 4, 0, 101, 27, // Skip to: 8540 /* 1527 */ MCD_OPC_Decode, 255, 8, 1, // Opcode: IAC /* 1531 */ MCD_OPC_FilterValue, 37, 16, 0, // Skip to: 1551 /* 1535 */ MCD_OPC_CheckField, 8, 8, 0, 87, 27, // Skip to: 8540 /* 1541 */ MCD_OPC_CheckField, 0, 4, 0, 81, 27, // Skip to: 8540 /* 1547 */ MCD_OPC_Decode, 149, 15, 1, // Opcode: SSAR /* 1551 */ MCD_OPC_FilterValue, 38, 16, 0, // Skip to: 1571 /* 1555 */ MCD_OPC_CheckField, 8, 8, 0, 67, 27, // Skip to: 8540 /* 1561 */ MCD_OPC_CheckField, 0, 4, 0, 61, 27, // Skip to: 8540 /* 1567 */ MCD_OPC_Decode, 226, 8, 1, // Opcode: EPAR /* 1571 */ MCD_OPC_FilterValue, 39, 16, 0, // Skip to: 1591 /* 1575 */ MCD_OPC_CheckField, 8, 8, 0, 47, 27, // Skip to: 8540 /* 1581 */ MCD_OPC_CheckField, 0, 4, 0, 41, 27, // Skip to: 8540 /* 1587 */ MCD_OPC_Decode, 232, 8, 1, // Opcode: ESAR /* 1591 */ MCD_OPC_FilterValue, 40, 10, 0, // Skip to: 1605 /* 1595 */ MCD_OPC_CheckField, 8, 8, 0, 27, 27, // Skip to: 8540 /* 1601 */ MCD_OPC_Decode, 151, 14, 59, // Opcode: PT /* 1605 */ MCD_OPC_FilterValue, 41, 10, 0, // Skip to: 1619 /* 1609 */ MCD_OPC_CheckField, 8, 8, 0, 13, 27, // Skip to: 8540 /* 1615 */ MCD_OPC_Decode, 151, 9, 3, // Opcode: ISKE /* 1619 */ MCD_OPC_FilterValue, 42, 10, 0, // Skip to: 1633 /* 1623 */ MCD_OPC_CheckField, 8, 8, 0, 255, 26, // Skip to: 8540 /* 1629 */ MCD_OPC_Decode, 171, 14, 59, // Opcode: RRBE /* 1633 */ MCD_OPC_FilterValue, 43, 21, 0, // Skip to: 1658 /* 1637 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 1640 */ MCD_OPC_FilterValue, 0, 240, 26, // Skip to: 8540 /* 1644 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 1654 /* 1650 */ MCD_OPC_Decode, 152, 15, 59, // Opcode: SSKEOpt /* 1654 */ MCD_OPC_Decode, 151, 15, 60, // Opcode: SSKE /* 1658 */ MCD_OPC_FilterValue, 44, 10, 0, // Skip to: 1672 /* 1662 */ MCD_OPC_CheckField, 8, 8, 0, 216, 26, // Skip to: 8540 /* 1668 */ MCD_OPC_Decode, 158, 16, 61, // Opcode: TB /* 1672 */ MCD_OPC_FilterValue, 45, 10, 0, // Skip to: 1686 /* 1676 */ MCD_OPC_CheckField, 8, 8, 0, 202, 26, // Skip to: 8540 /* 1682 */ MCD_OPC_Decode, 212, 8, 13, // Opcode: DXR /* 1686 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 1700 /* 1690 */ MCD_OPC_CheckField, 8, 8, 0, 188, 26, // Skip to: 8540 /* 1696 */ MCD_OPC_Decode, 141, 14, 61, // Opcode: PGIN /* 1700 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 1714 /* 1704 */ MCD_OPC_CheckField, 8, 8, 0, 174, 26, // Skip to: 8540 /* 1710 */ MCD_OPC_Decode, 142, 14, 61, // Opcode: PGOUT /* 1714 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 1728 /* 1718 */ MCD_OPC_CheckField, 0, 16, 0, 160, 26, // Skip to: 8540 /* 1724 */ MCD_OPC_Decode, 133, 8, 0, // Opcode: CSCH /* 1728 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 1742 /* 1732 */ MCD_OPC_CheckField, 0, 16, 0, 146, 26, // Skip to: 8540 /* 1738 */ MCD_OPC_Decode, 254, 8, 0, // Opcode: HSCH /* 1742 */ MCD_OPC_FilterValue, 50, 4, 0, // Skip to: 1750 /* 1746 */ MCD_OPC_Decode, 170, 13, 32, // Opcode: MSCH /* 1750 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1758 /* 1754 */ MCD_OPC_Decode, 150, 15, 32, // Opcode: SSCH /* 1758 */ MCD_OPC_FilterValue, 52, 4, 0, // Skip to: 1766 /* 1762 */ MCD_OPC_Decode, 140, 16, 32, // Opcode: STSCH /* 1766 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1774 /* 1770 */ MCD_OPC_Decode, 205, 16, 32, // Opcode: TSCH /* 1774 */ MCD_OPC_FilterValue, 54, 4, 0, // Skip to: 1782 /* 1778 */ MCD_OPC_Decode, 182, 16, 32, // Opcode: TPI /* 1782 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 1796 /* 1786 */ MCD_OPC_CheckField, 0, 16, 0, 92, 26, // Skip to: 8540 /* 1792 */ MCD_OPC_Decode, 180, 14, 0, // Opcode: SAL /* 1796 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 1810 /* 1800 */ MCD_OPC_CheckField, 0, 16, 0, 78, 26, // Skip to: 8540 /* 1806 */ MCD_OPC_Decode, 175, 14, 0, // Opcode: RSCH /* 1810 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1818 /* 1814 */ MCD_OPC_Decode, 168, 15, 32, // Opcode: STCRW /* 1818 */ MCD_OPC_FilterValue, 58, 4, 0, // Skip to: 1826 /* 1822 */ MCD_OPC_Decode, 167, 15, 32, // Opcode: STCPS /* 1826 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 1840 /* 1830 */ MCD_OPC_CheckField, 0, 16, 0, 48, 26, // Skip to: 8540 /* 1836 */ MCD_OPC_Decode, 160, 14, 0, // Opcode: RCHP /* 1840 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 1854 /* 1844 */ MCD_OPC_CheckField, 0, 16, 0, 34, 26, // Skip to: 8540 /* 1850 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: SCHM /* 1854 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 1868 /* 1858 */ MCD_OPC_CheckField, 8, 8, 0, 20, 26, // Skip to: 8540 /* 1864 */ MCD_OPC_Decode, 166, 3, 61, // Opcode: BAKR /* 1868 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 1882 /* 1872 */ MCD_OPC_CheckField, 8, 8, 0, 6, 26, // Skip to: 8540 /* 1878 */ MCD_OPC_Decode, 223, 5, 62, // Opcode: CKSM /* 1882 */ MCD_OPC_FilterValue, 68, 10, 0, // Skip to: 1896 /* 1886 */ MCD_OPC_CheckField, 8, 8, 0, 248, 25, // Skip to: 8540 /* 1892 */ MCD_OPC_Decode, 251, 14, 11, // Opcode: SQDR /* 1896 */ MCD_OPC_FilterValue, 69, 10, 0, // Skip to: 1910 /* 1900 */ MCD_OPC_CheckField, 8, 8, 0, 234, 25, // Skip to: 8540 /* 1906 */ MCD_OPC_Decode, 255, 14, 16, // Opcode: SQER /* 1910 */ MCD_OPC_FilterValue, 70, 10, 0, // Skip to: 1924 /* 1914 */ MCD_OPC_CheckField, 8, 8, 0, 220, 25, // Skip to: 8540 /* 1920 */ MCD_OPC_Decode, 142, 16, 59, // Opcode: STURA /* 1924 */ MCD_OPC_FilterValue, 71, 16, 0, // Skip to: 1944 /* 1928 */ MCD_OPC_CheckField, 8, 8, 0, 206, 25, // Skip to: 8540 /* 1934 */ MCD_OPC_CheckField, 0, 4, 0, 200, 25, // Skip to: 8540 /* 1940 */ MCD_OPC_Decode, 189, 13, 63, // Opcode: MSTA /* 1944 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 1958 /* 1948 */ MCD_OPC_CheckField, 0, 16, 0, 186, 25, // Skip to: 8540 /* 1954 */ MCD_OPC_Decode, 133, 14, 0, // Opcode: PALB /* 1958 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 1972 /* 1962 */ MCD_OPC_CheckField, 8, 8, 0, 172, 25, // Skip to: 8540 /* 1968 */ MCD_OPC_Decode, 229, 8, 8, // Opcode: EREG /* 1972 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 1986 /* 1976 */ MCD_OPC_CheckField, 8, 8, 0, 158, 25, // Skip to: 8540 /* 1982 */ MCD_OPC_Decode, 235, 8, 64, // Opcode: ESTA /* 1986 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 2000 /* 1990 */ MCD_OPC_CheckField, 8, 8, 0, 144, 25, // Skip to: 8540 /* 1996 */ MCD_OPC_Decode, 232, 12, 59, // Opcode: LURA /* 2000 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 2014 /* 2004 */ MCD_OPC_CheckField, 8, 8, 0, 130, 25, // Skip to: 8540 /* 2010 */ MCD_OPC_Decode, 157, 16, 65, // Opcode: TAR /* 2014 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 2028 /* 2018 */ MCD_OPC_CheckField, 8, 8, 0, 116, 25, // Skip to: 8540 /* 2024 */ MCD_OPC_Decode, 213, 7, 66, // Opcode: CPYA /* 2028 */ MCD_OPC_FilterValue, 78, 10, 0, // Skip to: 2042 /* 2032 */ MCD_OPC_CheckField, 8, 8, 0, 102, 25, // Skip to: 8540 /* 2038 */ MCD_OPC_Decode, 184, 14, 65, // Opcode: SAR /* 2042 */ MCD_OPC_FilterValue, 79, 10, 0, // Skip to: 2056 /* 2046 */ MCD_OPC_CheckField, 8, 8, 0, 88, 25, // Skip to: 8540 /* 2052 */ MCD_OPC_Decode, 215, 8, 67, // Opcode: EAR /* 2056 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 2070 /* 2060 */ MCD_OPC_CheckField, 8, 8, 0, 74, 25, // Skip to: 8540 /* 2066 */ MCD_OPC_Decode, 136, 8, 68, // Opcode: CSP /* 2070 */ MCD_OPC_FilterValue, 82, 10, 0, // Skip to: 2084 /* 2074 */ MCD_OPC_CheckField, 8, 8, 0, 60, 25, // Skip to: 8540 /* 2080 */ MCD_OPC_Decode, 187, 13, 9, // Opcode: MSR /* 2084 */ MCD_OPC_FilterValue, 84, 10, 0, // Skip to: 2098 /* 2088 */ MCD_OPC_CheckField, 8, 8, 0, 46, 25, // Skip to: 8540 /* 2094 */ MCD_OPC_Decode, 209, 13, 61, // Opcode: MVPG /* 2098 */ MCD_OPC_FilterValue, 85, 10, 0, // Skip to: 2112 /* 2102 */ MCD_OPC_CheckField, 8, 8, 0, 32, 25, // Skip to: 8540 /* 2108 */ MCD_OPC_Decode, 210, 13, 69, // Opcode: MVST /* 2112 */ MCD_OPC_FilterValue, 87, 10, 0, // Skip to: 2126 /* 2116 */ MCD_OPC_CheckField, 8, 8, 0, 18, 25, // Skip to: 8540 /* 2122 */ MCD_OPC_Decode, 152, 8, 7, // Opcode: CUSE /* 2126 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 2140 /* 2130 */ MCD_OPC_CheckField, 8, 8, 0, 4, 25, // Skip to: 8540 /* 2136 */ MCD_OPC_Decode, 132, 4, 61, // Opcode: BSG /* 2140 */ MCD_OPC_FilterValue, 90, 10, 0, // Skip to: 2154 /* 2144 */ MCD_OPC_CheckField, 8, 8, 0, 246, 24, // Skip to: 8540 /* 2150 */ MCD_OPC_Decode, 131, 4, 61, // Opcode: BSA /* 2154 */ MCD_OPC_FilterValue, 93, 10, 0, // Skip to: 2168 /* 2158 */ MCD_OPC_CheckField, 8, 8, 0, 232, 24, // Skip to: 8540 /* 2164 */ MCD_OPC_Decode, 189, 7, 69, // Opcode: CLST /* 2168 */ MCD_OPC_FilterValue, 94, 10, 0, // Skip to: 2182 /* 2172 */ MCD_OPC_CheckField, 8, 8, 0, 218, 24, // Skip to: 8540 /* 2178 */ MCD_OPC_Decode, 145, 15, 69, // Opcode: SRST /* 2182 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 2196 /* 2186 */ MCD_OPC_CheckField, 8, 8, 0, 204, 24, // Skip to: 8540 /* 2192 */ MCD_OPC_Decode, 205, 7, 7, // Opcode: CMPSC /* 2196 */ MCD_OPC_FilterValue, 116, 4, 0, // Skip to: 2204 /* 2200 */ MCD_OPC_Decode, 213, 14, 32, // Opcode: SIGA /* 2204 */ MCD_OPC_FilterValue, 118, 10, 0, // Skip to: 2218 /* 2208 */ MCD_OPC_CheckField, 0, 16, 0, 182, 24, // Skip to: 8540 /* 2214 */ MCD_OPC_Decode, 237, 21, 0, // Opcode: XSCH /* 2218 */ MCD_OPC_FilterValue, 119, 4, 0, // Skip to: 2226 /* 2222 */ MCD_OPC_Decode, 170, 14, 32, // Opcode: RP /* 2226 */ MCD_OPC_FilterValue, 120, 4, 0, // Skip to: 2234 /* 2230 */ MCD_OPC_Decode, 162, 15, 32, // Opcode: STCKE /* 2234 */ MCD_OPC_FilterValue, 121, 4, 0, // Skip to: 2242 /* 2238 */ MCD_OPC_Decode, 179, 14, 32, // Opcode: SACF /* 2242 */ MCD_OPC_FilterValue, 124, 4, 0, // Skip to: 2250 /* 2246 */ MCD_OPC_Decode, 163, 15, 32, // Opcode: STCKF /* 2250 */ MCD_OPC_FilterValue, 125, 4, 0, // Skip to: 2258 /* 2254 */ MCD_OPC_Decode, 141, 16, 32, // Opcode: STSI /* 2258 */ MCD_OPC_FilterValue, 128, 1, 4, 0, // Skip to: 2267 /* 2263 */ MCD_OPC_Decode, 194, 12, 32, // Opcode: LPP /* 2267 */ MCD_OPC_FilterValue, 132, 1, 4, 0, // Skip to: 2276 /* 2272 */ MCD_OPC_Decode, 132, 10, 32, // Opcode: LCCTL /* 2276 */ MCD_OPC_FilterValue, 133, 1, 4, 0, // Skip to: 2285 /* 2281 */ MCD_OPC_Decode, 183, 12, 32, // Opcode: LPCTL /* 2285 */ MCD_OPC_FilterValue, 134, 1, 4, 0, // Skip to: 2294 /* 2290 */ MCD_OPC_Decode, 159, 14, 32, // Opcode: QSI /* 2294 */ MCD_OPC_FilterValue, 135, 1, 4, 0, // Skip to: 2303 /* 2299 */ MCD_OPC_Decode, 214, 12, 32, // Opcode: LSCTL /* 2303 */ MCD_OPC_FilterValue, 142, 1, 4, 0, // Skip to: 2312 /* 2308 */ MCD_OPC_Decode, 158, 14, 32, // Opcode: QCTRI /* 2312 */ MCD_OPC_FilterValue, 153, 1, 4, 0, // Skip to: 2321 /* 2317 */ MCD_OPC_Decode, 141, 15, 70, // Opcode: SRNM /* 2321 */ MCD_OPC_FilterValue, 156, 1, 4, 0, // Skip to: 2330 /* 2326 */ MCD_OPC_Decode, 179, 15, 32, // Opcode: STFPC /* 2330 */ MCD_OPC_FilterValue, 157, 1, 4, 0, // Skip to: 2339 /* 2335 */ MCD_OPC_Decode, 174, 10, 32, // Opcode: LFPC /* 2339 */ MCD_OPC_FilterValue, 165, 1, 10, 0, // Skip to: 2354 /* 2344 */ MCD_OPC_CheckField, 8, 8, 0, 46, 24, // Skip to: 8540 /* 2350 */ MCD_OPC_Decode, 189, 16, 71, // Opcode: TRE /* 2354 */ MCD_OPC_FilterValue, 166, 1, 21, 0, // Skip to: 2380 /* 2359 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 2362 */ MCD_OPC_FilterValue, 0, 30, 24, // Skip to: 8540 /* 2366 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2376 /* 2372 */ MCD_OPC_Decode, 146, 8, 7, // Opcode: CU21Opt /* 2376 */ MCD_OPC_Decode, 145, 8, 72, // Opcode: CU21 /* 2380 */ MCD_OPC_FilterValue, 167, 1, 21, 0, // Skip to: 2406 /* 2385 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 2388 */ MCD_OPC_FilterValue, 0, 4, 24, // Skip to: 8540 /* 2392 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 2402 /* 2398 */ MCD_OPC_Decode, 142, 8, 7, // Opcode: CU12Opt /* 2402 */ MCD_OPC_Decode, 141, 8, 72, // Opcode: CU12 /* 2406 */ MCD_OPC_FilterValue, 176, 1, 4, 0, // Skip to: 2415 /* 2411 */ MCD_OPC_Decode, 178, 15, 32, // Opcode: STFLE /* 2415 */ MCD_OPC_FilterValue, 177, 1, 4, 0, // Skip to: 2424 /* 2420 */ MCD_OPC_Decode, 177, 15, 32, // Opcode: STFL /* 2424 */ MCD_OPC_FilterValue, 178, 1, 4, 0, // Skip to: 2433 /* 2429 */ MCD_OPC_Decode, 198, 12, 32, // Opcode: LPSWE /* 2433 */ MCD_OPC_FilterValue, 184, 1, 8, 0, // Skip to: 2446 /* 2438 */ MCD_OPC_CheckPredicate, 0, 210, 23, // Skip to: 8540 /* 2442 */ MCD_OPC_Decode, 142, 15, 70, // Opcode: SRNMB /* 2446 */ MCD_OPC_FilterValue, 185, 1, 4, 0, // Skip to: 2455 /* 2451 */ MCD_OPC_Decode, 143, 15, 70, // Opcode: SRNMT /* 2455 */ MCD_OPC_FilterValue, 189, 1, 4, 0, // Skip to: 2464 /* 2460 */ MCD_OPC_Decode, 171, 10, 32, // Opcode: LFAS /* 2464 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 2479 /* 2469 */ MCD_OPC_CheckField, 8, 8, 0, 177, 23, // Skip to: 8540 /* 2475 */ MCD_OPC_Decode, 185, 14, 61, // Opcode: SCCTR /* 2479 */ MCD_OPC_FilterValue, 225, 1, 10, 0, // Skip to: 2494 /* 2484 */ MCD_OPC_CheckField, 8, 8, 0, 162, 23, // Skip to: 8540 /* 2490 */ MCD_OPC_Decode, 243, 14, 61, // Opcode: SPCTR /* 2494 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 2509 /* 2499 */ MCD_OPC_CheckField, 8, 8, 0, 147, 23, // Skip to: 8540 /* 2505 */ MCD_OPC_Decode, 217, 8, 61, // Opcode: ECCTR /* 2509 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 2524 /* 2514 */ MCD_OPC_CheckField, 8, 8, 0, 132, 23, // Skip to: 8540 /* 2520 */ MCD_OPC_Decode, 227, 8, 61, // Opcode: EPCTR /* 2524 */ MCD_OPC_FilterValue, 232, 1, 14, 0, // Skip to: 2543 /* 2529 */ MCD_OPC_CheckPredicate, 1, 119, 23, // Skip to: 8540 /* 2533 */ MCD_OPC_CheckField, 8, 4, 0, 113, 23, // Skip to: 8540 /* 2539 */ MCD_OPC_Decode, 147, 14, 73, // Opcode: PPA /* 2543 */ MCD_OPC_FilterValue, 236, 1, 20, 0, // Skip to: 2568 /* 2548 */ MCD_OPC_CheckPredicate, 2, 100, 23, // Skip to: 8540 /* 2552 */ MCD_OPC_CheckField, 8, 8, 0, 94, 23, // Skip to: 8540 /* 2558 */ MCD_OPC_CheckField, 0, 4, 0, 88, 23, // Skip to: 8540 /* 2564 */ MCD_OPC_Decode, 237, 8, 1, // Opcode: ETND /* 2568 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 2583 /* 2573 */ MCD_OPC_CheckField, 8, 8, 0, 73, 23, // Skip to: 8540 /* 2579 */ MCD_OPC_Decode, 218, 8, 59, // Opcode: ECPGA /* 2583 */ MCD_OPC_FilterValue, 248, 1, 14, 0, // Skip to: 2602 /* 2588 */ MCD_OPC_CheckPredicate, 2, 60, 23, // Skip to: 8540 /* 2592 */ MCD_OPC_CheckField, 0, 16, 0, 54, 23, // Skip to: 8540 /* 2598 */ MCD_OPC_Decode, 172, 16, 0, // Opcode: TEND /* 2602 */ MCD_OPC_FilterValue, 250, 1, 14, 0, // Skip to: 2621 /* 2607 */ MCD_OPC_CheckPredicate, 3, 41, 23, // Skip to: 8540 /* 2611 */ MCD_OPC_CheckField, 8, 8, 0, 35, 23, // Skip to: 8540 /* 2617 */ MCD_OPC_Decode, 232, 13, 74, // Opcode: NIAI /* 2621 */ MCD_OPC_FilterValue, 252, 1, 8, 0, // Skip to: 2634 /* 2626 */ MCD_OPC_CheckPredicate, 2, 22, 23, // Skip to: 8540 /* 2630 */ MCD_OPC_Decode, 155, 16, 32, // Opcode: TABORT /* 2634 */ MCD_OPC_FilterValue, 255, 1, 13, 23, // Skip to: 8540 /* 2639 */ MCD_OPC_Decode, 188, 16, 32, // Opcode: TRAP4 /* 2643 */ MCD_OPC_FilterValue, 179, 1, 122, 10, // Skip to: 5330 /* 2648 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 2651 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 2665 /* 2655 */ MCD_OPC_CheckField, 8, 8, 0, 247, 22, // Skip to: 8540 /* 2661 */ MCD_OPC_Decode, 190, 12, 16, // Opcode: LPEBR /* 2665 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 2679 /* 2669 */ MCD_OPC_CheckField, 8, 8, 0, 233, 22, // Skip to: 8540 /* 2675 */ MCD_OPC_Decode, 234, 10, 16, // Opcode: LNEBR /* 2679 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 2693 /* 2683 */ MCD_OPC_CheckField, 8, 8, 0, 219, 22, // Skip to: 8540 /* 2689 */ MCD_OPC_Decode, 220, 12, 16, // Opcode: LTEBR /* 2693 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 2707 /* 2697 */ MCD_OPC_CheckField, 8, 8, 0, 205, 22, // Skip to: 8540 /* 2703 */ MCD_OPC_Decode, 137, 10, 16, // Opcode: LCEBR /* 2707 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 2721 /* 2711 */ MCD_OPC_CheckField, 8, 8, 0, 191, 22, // Skip to: 8540 /* 2717 */ MCD_OPC_Decode, 150, 10, 75, // Opcode: LDEBR /* 2721 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 2735 /* 2725 */ MCD_OPC_CheckField, 8, 8, 0, 177, 22, // Skip to: 8540 /* 2731 */ MCD_OPC_Decode, 236, 12, 76, // Opcode: LXDBR /* 2735 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 2749 /* 2739 */ MCD_OPC_CheckField, 8, 8, 0, 163, 22, // Skip to: 8540 /* 2745 */ MCD_OPC_Decode, 241, 12, 77, // Opcode: LXEBR /* 2749 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 2763 /* 2753 */ MCD_OPC_CheckField, 8, 8, 0, 149, 22, // Skip to: 8540 /* 2759 */ MCD_OPC_Decode, 215, 13, 14, // Opcode: MXDBR /* 2763 */ MCD_OPC_FilterValue, 8, 10, 0, // Skip to: 2777 /* 2767 */ MCD_OPC_CheckField, 8, 8, 0, 135, 22, // Skip to: 8540 /* 2773 */ MCD_OPC_Decode, 224, 9, 16, // Opcode: KEBR /* 2777 */ MCD_OPC_FilterValue, 9, 10, 0, // Skip to: 2791 /* 2781 */ MCD_OPC_CheckField, 8, 8, 0, 121, 22, // Skip to: 8540 /* 2787 */ MCD_OPC_Decode, 166, 4, 16, // Opcode: CEBR /* 2791 */ MCD_OPC_FilterValue, 10, 10, 0, // Skip to: 2805 /* 2795 */ MCD_OPC_CheckField, 8, 8, 0, 107, 22, // Skip to: 8540 /* 2801 */ MCD_OPC_Decode, 237, 2, 18, // Opcode: AEBR /* 2805 */ MCD_OPC_FilterValue, 11, 10, 0, // Skip to: 2819 /* 2809 */ MCD_OPC_CheckField, 8, 8, 0, 93, 22, // Skip to: 8540 /* 2815 */ MCD_OPC_Decode, 198, 14, 18, // Opcode: SEBR /* 2819 */ MCD_OPC_FilterValue, 12, 10, 0, // Skip to: 2833 /* 2823 */ MCD_OPC_CheckField, 8, 8, 0, 79, 22, // Skip to: 8540 /* 2829 */ MCD_OPC_Decode, 143, 13, 19, // Opcode: MDEBR /* 2833 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 2847 /* 2837 */ MCD_OPC_CheckField, 8, 8, 0, 65, 22, // Skip to: 8540 /* 2843 */ MCD_OPC_Decode, 196, 8, 18, // Opcode: DEBR /* 2847 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 2861 /* 2851 */ MCD_OPC_CheckField, 8, 4, 0, 51, 22, // Skip to: 8540 /* 2857 */ MCD_OPC_Decode, 129, 13, 78, // Opcode: MAEBR /* 2861 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 2875 /* 2865 */ MCD_OPC_CheckField, 8, 4, 0, 37, 22, // Skip to: 8540 /* 2871 */ MCD_OPC_Decode, 177, 13, 78, // Opcode: MSEBR /* 2875 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 2889 /* 2879 */ MCD_OPC_CheckField, 8, 8, 0, 23, 22, // Skip to: 8540 /* 2885 */ MCD_OPC_Decode, 185, 12, 11, // Opcode: LPDBR /* 2889 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 2903 /* 2893 */ MCD_OPC_CheckField, 8, 8, 0, 9, 22, // Skip to: 8540 /* 2899 */ MCD_OPC_Decode, 230, 10, 11, // Opcode: LNDBR /* 2903 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 2917 /* 2907 */ MCD_OPC_CheckField, 8, 8, 0, 251, 21, // Skip to: 8540 /* 2913 */ MCD_OPC_Decode, 216, 12, 11, // Opcode: LTDBR /* 2917 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 2931 /* 2921 */ MCD_OPC_CheckField, 8, 8, 0, 237, 21, // Skip to: 8540 /* 2927 */ MCD_OPC_Decode, 133, 10, 11, // Opcode: LCDBR /* 2931 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 2945 /* 2935 */ MCD_OPC_CheckField, 8, 8, 0, 223, 21, // Skip to: 8540 /* 2941 */ MCD_OPC_Decode, 254, 14, 16, // Opcode: SQEBR /* 2945 */ MCD_OPC_FilterValue, 21, 10, 0, // Skip to: 2959 /* 2949 */ MCD_OPC_CheckField, 8, 8, 0, 209, 21, // Skip to: 8540 /* 2955 */ MCD_OPC_Decode, 250, 14, 11, // Opcode: SQDBR /* 2959 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 2973 /* 2963 */ MCD_OPC_CheckField, 8, 8, 0, 195, 21, // Skip to: 8540 /* 2969 */ MCD_OPC_Decode, 128, 15, 79, // Opcode: SQXBR /* 2973 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 2987 /* 2977 */ MCD_OPC_CheckField, 8, 8, 0, 181, 21, // Skip to: 8540 /* 2983 */ MCD_OPC_Decode, 151, 13, 18, // Opcode: MEEBR /* 2987 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 3001 /* 2991 */ MCD_OPC_CheckField, 8, 8, 0, 167, 21, // Skip to: 8540 /* 2997 */ MCD_OPC_Decode, 221, 9, 11, // Opcode: KDBR /* 3001 */ MCD_OPC_FilterValue, 25, 10, 0, // Skip to: 3015 /* 3005 */ MCD_OPC_CheckField, 8, 8, 0, 153, 21, // Skip to: 8540 /* 3011 */ MCD_OPC_Decode, 141, 4, 11, // Opcode: CDBR /* 3015 */ MCD_OPC_FilterValue, 26, 10, 0, // Skip to: 3029 /* 3019 */ MCD_OPC_CheckField, 8, 8, 0, 139, 21, // Skip to: 8540 /* 3025 */ MCD_OPC_Decode, 231, 2, 15, // Opcode: ADBR /* 3029 */ MCD_OPC_FilterValue, 27, 10, 0, // Skip to: 3043 /* 3033 */ MCD_OPC_CheckField, 8, 8, 0, 125, 21, // Skip to: 8540 /* 3039 */ MCD_OPC_Decode, 192, 14, 15, // Opcode: SDBR /* 3043 */ MCD_OPC_FilterValue, 28, 10, 0, // Skip to: 3057 /* 3047 */ MCD_OPC_CheckField, 8, 8, 0, 111, 21, // Skip to: 8540 /* 3053 */ MCD_OPC_Decode, 140, 13, 15, // Opcode: MDBR /* 3057 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 3071 /* 3061 */ MCD_OPC_CheckField, 8, 8, 0, 97, 21, // Skip to: 8540 /* 3067 */ MCD_OPC_Decode, 190, 8, 15, // Opcode: DDBR /* 3071 */ MCD_OPC_FilterValue, 30, 10, 0, // Skip to: 3085 /* 3075 */ MCD_OPC_CheckField, 8, 4, 0, 83, 21, // Skip to: 8540 /* 3081 */ MCD_OPC_Decode, 253, 12, 80, // Opcode: MADBR /* 3085 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 3099 /* 3089 */ MCD_OPC_CheckField, 8, 4, 0, 69, 21, // Skip to: 8540 /* 3095 */ MCD_OPC_Decode, 173, 13, 80, // Opcode: MSDBR /* 3099 */ MCD_OPC_FilterValue, 36, 10, 0, // Skip to: 3113 /* 3103 */ MCD_OPC_CheckField, 8, 8, 0, 55, 21, // Skip to: 8540 /* 3109 */ MCD_OPC_Decode, 151, 10, 75, // Opcode: LDER /* 3113 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 3127 /* 3117 */ MCD_OPC_CheckField, 8, 8, 0, 41, 21, // Skip to: 8540 /* 3123 */ MCD_OPC_Decode, 237, 12, 76, // Opcode: LXDR /* 3127 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 3141 /* 3131 */ MCD_OPC_CheckField, 8, 8, 0, 27, 21, // Skip to: 8540 /* 3137 */ MCD_OPC_Decode, 242, 12, 77, // Opcode: LXER /* 3141 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 3155 /* 3145 */ MCD_OPC_CheckField, 8, 4, 0, 13, 21, // Skip to: 8540 /* 3151 */ MCD_OPC_Decode, 130, 13, 78, // Opcode: MAER /* 3155 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 3169 /* 3159 */ MCD_OPC_CheckField, 8, 4, 0, 255, 20, // Skip to: 8540 /* 3165 */ MCD_OPC_Decode, 178, 13, 78, // Opcode: MSER /* 3169 */ MCD_OPC_FilterValue, 54, 10, 0, // Skip to: 3183 /* 3173 */ MCD_OPC_CheckField, 8, 8, 0, 241, 20, // Skip to: 8540 /* 3179 */ MCD_OPC_Decode, 129, 15, 79, // Opcode: SQXR /* 3183 */ MCD_OPC_FilterValue, 55, 10, 0, // Skip to: 3197 /* 3187 */ MCD_OPC_CheckField, 8, 8, 0, 227, 20, // Skip to: 8540 /* 3193 */ MCD_OPC_Decode, 152, 13, 18, // Opcode: MEER /* 3197 */ MCD_OPC_FilterValue, 56, 10, 0, // Skip to: 3211 /* 3201 */ MCD_OPC_CheckField, 8, 4, 0, 213, 20, // Skip to: 8540 /* 3207 */ MCD_OPC_Decode, 135, 13, 80, // Opcode: MAYLR /* 3211 */ MCD_OPC_FilterValue, 57, 10, 0, // Skip to: 3225 /* 3215 */ MCD_OPC_CheckField, 8, 4, 0, 199, 20, // Skip to: 8540 /* 3221 */ MCD_OPC_Decode, 224, 13, 81, // Opcode: MYLR /* 3225 */ MCD_OPC_FilterValue, 58, 10, 0, // Skip to: 3239 /* 3229 */ MCD_OPC_CheckField, 8, 4, 0, 185, 20, // Skip to: 8540 /* 3235 */ MCD_OPC_Decode, 136, 13, 82, // Opcode: MAYR /* 3239 */ MCD_OPC_FilterValue, 59, 10, 0, // Skip to: 3253 /* 3243 */ MCD_OPC_CheckField, 8, 4, 0, 171, 20, // Skip to: 8540 /* 3249 */ MCD_OPC_Decode, 225, 13, 83, // Opcode: MYR /* 3253 */ MCD_OPC_FilterValue, 60, 10, 0, // Skip to: 3267 /* 3257 */ MCD_OPC_CheckField, 8, 4, 0, 157, 20, // Skip to: 8540 /* 3263 */ MCD_OPC_Decode, 133, 13, 80, // Opcode: MAYHR /* 3267 */ MCD_OPC_FilterValue, 61, 10, 0, // Skip to: 3281 /* 3271 */ MCD_OPC_CheckField, 8, 4, 0, 143, 20, // Skip to: 8540 /* 3277 */ MCD_OPC_Decode, 222, 13, 81, // Opcode: MYHR /* 3281 */ MCD_OPC_FilterValue, 62, 10, 0, // Skip to: 3295 /* 3285 */ MCD_OPC_CheckField, 8, 4, 0, 129, 20, // Skip to: 8540 /* 3291 */ MCD_OPC_Decode, 254, 12, 80, // Opcode: MADR /* 3295 */ MCD_OPC_FilterValue, 63, 10, 0, // Skip to: 3309 /* 3299 */ MCD_OPC_CheckField, 8, 4, 0, 115, 20, // Skip to: 8540 /* 3305 */ MCD_OPC_Decode, 174, 13, 80, // Opcode: MSDR /* 3309 */ MCD_OPC_FilterValue, 64, 10, 0, // Skip to: 3323 /* 3313 */ MCD_OPC_CheckField, 8, 8, 0, 101, 20, // Skip to: 8540 /* 3319 */ MCD_OPC_Decode, 200, 12, 79, // Opcode: LPXBR /* 3323 */ MCD_OPC_FilterValue, 65, 10, 0, // Skip to: 3337 /* 3327 */ MCD_OPC_CheckField, 8, 8, 0, 87, 20, // Skip to: 8540 /* 3333 */ MCD_OPC_Decode, 239, 10, 79, // Opcode: LNXBR /* 3337 */ MCD_OPC_FilterValue, 66, 10, 0, // Skip to: 3351 /* 3341 */ MCD_OPC_CheckField, 8, 8, 0, 73, 20, // Skip to: 8540 /* 3347 */ MCD_OPC_Decode, 228, 12, 79, // Opcode: LTXBR /* 3351 */ MCD_OPC_FilterValue, 67, 10, 0, // Skip to: 3365 /* 3355 */ MCD_OPC_CheckField, 8, 8, 0, 59, 20, // Skip to: 8540 /* 3361 */ MCD_OPC_Decode, 144, 10, 79, // Opcode: LCXBR /* 3365 */ MCD_OPC_FilterValue, 68, 18, 0, // Skip to: 3387 /* 3369 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3379 /* 3375 */ MCD_OPC_Decode, 162, 10, 17, // Opcode: LEDBR /* 3379 */ MCD_OPC_CheckPredicate, 0, 37, 20, // Skip to: 8540 /* 3383 */ MCD_OPC_Decode, 163, 10, 84, // Opcode: LEDBRA /* 3387 */ MCD_OPC_FilterValue, 69, 18, 0, // Skip to: 3409 /* 3391 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3401 /* 3397 */ MCD_OPC_Decode, 156, 10, 79, // Opcode: LDXBR /* 3401 */ MCD_OPC_CheckPredicate, 0, 15, 20, // Skip to: 8540 /* 3405 */ MCD_OPC_Decode, 157, 10, 85, // Opcode: LDXBRA /* 3409 */ MCD_OPC_FilterValue, 70, 18, 0, // Skip to: 3431 /* 3413 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 3423 /* 3419 */ MCD_OPC_Decode, 167, 10, 79, // Opcode: LEXBR /* 3423 */ MCD_OPC_CheckPredicate, 0, 249, 19, // Skip to: 8540 /* 3427 */ MCD_OPC_Decode, 168, 10, 85, // Opcode: LEXBRA /* 3431 */ MCD_OPC_FilterValue, 71, 18, 0, // Skip to: 3453 /* 3435 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3445 /* 3441 */ MCD_OPC_Decode, 247, 8, 86, // Opcode: FIXBR /* 3445 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 8540 /* 3449 */ MCD_OPC_Decode, 248, 8, 85, // Opcode: FIXBRA /* 3453 */ MCD_OPC_FilterValue, 72, 10, 0, // Skip to: 3467 /* 3457 */ MCD_OPC_CheckField, 8, 8, 0, 213, 19, // Skip to: 8540 /* 3463 */ MCD_OPC_Decode, 234, 9, 79, // Opcode: KXBR /* 3467 */ MCD_OPC_FilterValue, 73, 10, 0, // Skip to: 3481 /* 3471 */ MCD_OPC_CheckField, 8, 8, 0, 199, 19, // Skip to: 8540 /* 3477 */ MCD_OPC_Decode, 164, 8, 79, // Opcode: CXBR /* 3481 */ MCD_OPC_FilterValue, 74, 10, 0, // Skip to: 3495 /* 3485 */ MCD_OPC_CheckField, 8, 8, 0, 185, 19, // Skip to: 8540 /* 3491 */ MCD_OPC_Decode, 160, 3, 13, // Opcode: AXBR /* 3495 */ MCD_OPC_FilterValue, 75, 10, 0, // Skip to: 3509 /* 3499 */ MCD_OPC_CheckField, 8, 8, 0, 171, 19, // Skip to: 8540 /* 3505 */ MCD_OPC_Decode, 150, 16, 13, // Opcode: SXBR /* 3509 */ MCD_OPC_FilterValue, 76, 10, 0, // Skip to: 3523 /* 3513 */ MCD_OPC_CheckField, 8, 8, 0, 157, 19, // Skip to: 8540 /* 3519 */ MCD_OPC_Decode, 212, 13, 13, // Opcode: MXBR /* 3523 */ MCD_OPC_FilterValue, 77, 10, 0, // Skip to: 3537 /* 3527 */ MCD_OPC_CheckField, 8, 8, 0, 143, 19, // Skip to: 8540 /* 3533 */ MCD_OPC_Decode, 211, 8, 13, // Opcode: DXBR /* 3537 */ MCD_OPC_FilterValue, 80, 10, 0, // Skip to: 3551 /* 3541 */ MCD_OPC_CheckField, 8, 4, 0, 129, 19, // Skip to: 8540 /* 3547 */ MCD_OPC_Decode, 160, 16, 87, // Opcode: TBEDR /* 3551 */ MCD_OPC_FilterValue, 81, 10, 0, // Skip to: 3565 /* 3555 */ MCD_OPC_CheckField, 8, 4, 0, 115, 19, // Skip to: 8540 /* 3561 */ MCD_OPC_Decode, 159, 16, 88, // Opcode: TBDR /* 3565 */ MCD_OPC_FilterValue, 83, 4, 0, // Skip to: 3573 /* 3569 */ MCD_OPC_Decode, 200, 8, 89, // Opcode: DIEBR /* 3573 */ MCD_OPC_FilterValue, 87, 18, 0, // Skip to: 3595 /* 3577 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3587 /* 3583 */ MCD_OPC_Decode, 244, 8, 90, // Opcode: FIEBR /* 3587 */ MCD_OPC_CheckPredicate, 0, 85, 19, // Skip to: 8540 /* 3591 */ MCD_OPC_Decode, 245, 8, 91, // Opcode: FIEBRA /* 3595 */ MCD_OPC_FilterValue, 88, 10, 0, // Skip to: 3609 /* 3599 */ MCD_OPC_CheckField, 8, 8, 0, 71, 19, // Skip to: 8540 /* 3605 */ MCD_OPC_Decode, 173, 16, 75, // Opcode: THDER /* 3609 */ MCD_OPC_FilterValue, 89, 10, 0, // Skip to: 3623 /* 3613 */ MCD_OPC_CheckField, 8, 8, 0, 57, 19, // Skip to: 8540 /* 3619 */ MCD_OPC_Decode, 174, 16, 11, // Opcode: THDR /* 3623 */ MCD_OPC_FilterValue, 91, 4, 0, // Skip to: 3631 /* 3627 */ MCD_OPC_Decode, 199, 8, 92, // Opcode: DIDBR /* 3631 */ MCD_OPC_FilterValue, 95, 18, 0, // Skip to: 3653 /* 3635 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 3645 /* 3641 */ MCD_OPC_Decode, 240, 8, 88, // Opcode: FIDBR /* 3645 */ MCD_OPC_CheckPredicate, 0, 27, 19, // Skip to: 8540 /* 3649 */ MCD_OPC_Decode, 241, 8, 93, // Opcode: FIDBRA /* 3653 */ MCD_OPC_FilterValue, 96, 10, 0, // Skip to: 3667 /* 3657 */ MCD_OPC_CheckField, 8, 8, 0, 13, 19, // Skip to: 8540 /* 3663 */ MCD_OPC_Decode, 201, 12, 79, // Opcode: LPXR /* 3667 */ MCD_OPC_FilterValue, 97, 10, 0, // Skip to: 3681 /* 3671 */ MCD_OPC_CheckField, 8, 8, 0, 255, 18, // Skip to: 8540 /* 3677 */ MCD_OPC_Decode, 240, 10, 79, // Opcode: LNXR /* 3681 */ MCD_OPC_FilterValue, 98, 10, 0, // Skip to: 3695 /* 3685 */ MCD_OPC_CheckField, 8, 8, 0, 241, 18, // Skip to: 8540 /* 3691 */ MCD_OPC_Decode, 230, 12, 79, // Opcode: LTXR /* 3695 */ MCD_OPC_FilterValue, 99, 10, 0, // Skip to: 3709 /* 3699 */ MCD_OPC_CheckField, 8, 8, 0, 227, 18, // Skip to: 8540 /* 3705 */ MCD_OPC_Decode, 145, 10, 79, // Opcode: LCXR /* 3709 */ MCD_OPC_FilterValue, 101, 10, 0, // Skip to: 3723 /* 3713 */ MCD_OPC_CheckField, 8, 8, 0, 213, 18, // Skip to: 8540 /* 3719 */ MCD_OPC_Decode, 243, 12, 79, // Opcode: LXR /* 3723 */ MCD_OPC_FilterValue, 102, 10, 0, // Skip to: 3737 /* 3727 */ MCD_OPC_CheckField, 8, 8, 0, 199, 18, // Skip to: 8540 /* 3733 */ MCD_OPC_Decode, 169, 10, 94, // Opcode: LEXR /* 3737 */ MCD_OPC_FilterValue, 103, 10, 0, // Skip to: 3751 /* 3741 */ MCD_OPC_CheckField, 8, 8, 0, 185, 18, // Skip to: 8540 /* 3747 */ MCD_OPC_Decode, 249, 8, 79, // Opcode: FIXR /* 3751 */ MCD_OPC_FilterValue, 105, 10, 0, // Skip to: 3765 /* 3755 */ MCD_OPC_CheckField, 8, 8, 0, 171, 18, // Skip to: 8540 /* 3761 */ MCD_OPC_Decode, 179, 8, 79, // Opcode: CXR /* 3765 */ MCD_OPC_FilterValue, 112, 10, 0, // Skip to: 3779 /* 3769 */ MCD_OPC_CheckField, 8, 8, 0, 157, 18, // Skip to: 8540 /* 3775 */ MCD_OPC_Decode, 186, 12, 11, // Opcode: LPDFR /* 3779 */ MCD_OPC_FilterValue, 113, 10, 0, // Skip to: 3793 /* 3783 */ MCD_OPC_CheckField, 8, 8, 0, 143, 18, // Skip to: 8540 /* 3789 */ MCD_OPC_Decode, 231, 10, 11, // Opcode: LNDFR /* 3793 */ MCD_OPC_FilterValue, 114, 10, 0, // Skip to: 3807 /* 3797 */ MCD_OPC_CheckField, 8, 4, 0, 129, 18, // Skip to: 8540 /* 3803 */ MCD_OPC_Decode, 208, 7, 95, // Opcode: CPSDRdd /* 3807 */ MCD_OPC_FilterValue, 115, 10, 0, // Skip to: 3821 /* 3811 */ MCD_OPC_CheckField, 8, 8, 0, 115, 18, // Skip to: 8540 /* 3817 */ MCD_OPC_Decode, 134, 10, 11, // Opcode: LCDFR /* 3821 */ MCD_OPC_FilterValue, 116, 16, 0, // Skip to: 3841 /* 3825 */ MCD_OPC_CheckField, 8, 8, 0, 101, 18, // Skip to: 8540 /* 3831 */ MCD_OPC_CheckField, 0, 4, 0, 95, 18, // Skip to: 8540 /* 3837 */ MCD_OPC_Decode, 246, 12, 96, // Opcode: LZER /* 3841 */ MCD_OPC_FilterValue, 117, 16, 0, // Skip to: 3861 /* 3845 */ MCD_OPC_CheckField, 8, 8, 0, 81, 18, // Skip to: 8540 /* 3851 */ MCD_OPC_CheckField, 0, 4, 0, 75, 18, // Skip to: 8540 /* 3857 */ MCD_OPC_Decode, 245, 12, 97, // Opcode: LZDR /* 3861 */ MCD_OPC_FilterValue, 118, 16, 0, // Skip to: 3881 /* 3865 */ MCD_OPC_CheckField, 8, 8, 0, 61, 18, // Skip to: 8540 /* 3871 */ MCD_OPC_CheckField, 0, 4, 0, 55, 18, // Skip to: 8540 /* 3877 */ MCD_OPC_Decode, 249, 12, 98, // Opcode: LZXR /* 3881 */ MCD_OPC_FilterValue, 119, 10, 0, // Skip to: 3895 /* 3885 */ MCD_OPC_CheckField, 8, 8, 0, 41, 18, // Skip to: 8540 /* 3891 */ MCD_OPC_Decode, 246, 8, 16, // Opcode: FIER /* 3895 */ MCD_OPC_FilterValue, 127, 10, 0, // Skip to: 3909 /* 3899 */ MCD_OPC_CheckField, 8, 8, 0, 27, 18, // Skip to: 8540 /* 3905 */ MCD_OPC_Decode, 242, 8, 11, // Opcode: FIDR /* 3909 */ MCD_OPC_FilterValue, 132, 1, 16, 0, // Skip to: 3930 /* 3914 */ MCD_OPC_CheckField, 8, 8, 0, 12, 18, // Skip to: 8540 /* 3920 */ MCD_OPC_CheckField, 0, 4, 0, 6, 18, // Skip to: 8540 /* 3926 */ MCD_OPC_Decode, 201, 14, 1, // Opcode: SFPC /* 3930 */ MCD_OPC_FilterValue, 133, 1, 16, 0, // Skip to: 3951 /* 3935 */ MCD_OPC_CheckField, 8, 8, 0, 247, 17, // Skip to: 8540 /* 3941 */ MCD_OPC_CheckField, 0, 4, 0, 241, 17, // Skip to: 8540 /* 3947 */ MCD_OPC_Decode, 200, 14, 1, // Opcode: SFASR /* 3951 */ MCD_OPC_FilterValue, 140, 1, 16, 0, // Skip to: 3972 /* 3956 */ MCD_OPC_CheckField, 8, 8, 0, 226, 17, // Skip to: 8540 /* 3962 */ MCD_OPC_CheckField, 0, 4, 0, 220, 17, // Skip to: 8540 /* 3968 */ MCD_OPC_Decode, 224, 8, 1, // Opcode: EFPC /* 3972 */ MCD_OPC_FilterValue, 144, 1, 8, 0, // Skip to: 3985 /* 3977 */ MCD_OPC_CheckPredicate, 0, 207, 17, // Skip to: 8540 /* 3981 */ MCD_OPC_Decode, 174, 4, 99, // Opcode: CELFBR /* 3985 */ MCD_OPC_FilterValue, 145, 1, 8, 0, // Skip to: 3998 /* 3990 */ MCD_OPC_CheckPredicate, 0, 194, 17, // Skip to: 8540 /* 3994 */ MCD_OPC_Decode, 151, 4, 100, // Opcode: CDLFBR /* 3998 */ MCD_OPC_FilterValue, 146, 1, 8, 0, // Skip to: 4011 /* 4003 */ MCD_OPC_CheckPredicate, 0, 181, 17, // Skip to: 8540 /* 4007 */ MCD_OPC_Decode, 174, 8, 101, // Opcode: CXLFBR /* 4011 */ MCD_OPC_FilterValue, 148, 1, 18, 0, // Skip to: 4034 /* 4016 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4026 /* 4022 */ MCD_OPC_Decode, 168, 4, 102, // Opcode: CEFBR /* 4026 */ MCD_OPC_CheckPredicate, 0, 158, 17, // Skip to: 8540 /* 4030 */ MCD_OPC_Decode, 169, 4, 99, // Opcode: CEFBRA /* 4034 */ MCD_OPC_FilterValue, 149, 1, 18, 0, // Skip to: 4057 /* 4039 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4049 /* 4045 */ MCD_OPC_Decode, 142, 4, 103, // Opcode: CDFBR /* 4049 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 8540 /* 4053 */ MCD_OPC_Decode, 143, 4, 100, // Opcode: CDFBRA /* 4057 */ MCD_OPC_FilterValue, 150, 1, 18, 0, // Skip to: 4080 /* 4062 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4072 /* 4068 */ MCD_OPC_Decode, 165, 8, 104, // Opcode: CXFBR /* 4072 */ MCD_OPC_CheckPredicate, 0, 112, 17, // Skip to: 8540 /* 4076 */ MCD_OPC_Decode, 166, 8, 101, // Opcode: CXFBRA /* 4080 */ MCD_OPC_FilterValue, 152, 1, 18, 0, // Skip to: 4103 /* 4085 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4095 /* 4091 */ MCD_OPC_Decode, 183, 4, 105, // Opcode: CFEBR /* 4095 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 8540 /* 4099 */ MCD_OPC_Decode, 184, 4, 106, // Opcode: CFEBRA /* 4103 */ MCD_OPC_FilterValue, 153, 1, 18, 0, // Skip to: 4126 /* 4108 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4118 /* 4114 */ MCD_OPC_Decode, 179, 4, 107, // Opcode: CFDBR /* 4118 */ MCD_OPC_CheckPredicate, 0, 66, 17, // Skip to: 8540 /* 4122 */ MCD_OPC_Decode, 180, 4, 108, // Opcode: CFDBRA /* 4126 */ MCD_OPC_FilterValue, 154, 1, 18, 0, // Skip to: 4149 /* 4131 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4141 /* 4137 */ MCD_OPC_Decode, 187, 4, 109, // Opcode: CFXBR /* 4141 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 8540 /* 4145 */ MCD_OPC_Decode, 188, 4, 110, // Opcode: CFXBRA /* 4149 */ MCD_OPC_FilterValue, 156, 1, 8, 0, // Skip to: 4162 /* 4154 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 8540 /* 4158 */ MCD_OPC_Decode, 231, 5, 106, // Opcode: CLFEBR /* 4162 */ MCD_OPC_FilterValue, 157, 1, 8, 0, // Skip to: 4175 /* 4167 */ MCD_OPC_CheckPredicate, 0, 17, 17, // Skip to: 8540 /* 4171 */ MCD_OPC_Decode, 229, 5, 108, // Opcode: CLFDBR /* 4175 */ MCD_OPC_FilterValue, 158, 1, 8, 0, // Skip to: 4188 /* 4180 */ MCD_OPC_CheckPredicate, 0, 4, 17, // Skip to: 8540 /* 4184 */ MCD_OPC_Decode, 248, 5, 110, // Opcode: CLFXBR /* 4188 */ MCD_OPC_FilterValue, 160, 1, 8, 0, // Skip to: 4201 /* 4193 */ MCD_OPC_CheckPredicate, 0, 247, 16, // Skip to: 8540 /* 4197 */ MCD_OPC_Decode, 175, 4, 111, // Opcode: CELGBR /* 4201 */ MCD_OPC_FilterValue, 161, 1, 8, 0, // Skip to: 4214 /* 4206 */ MCD_OPC_CheckPredicate, 0, 234, 16, // Skip to: 8540 /* 4210 */ MCD_OPC_Decode, 153, 4, 112, // Opcode: CDLGBR /* 4214 */ MCD_OPC_FilterValue, 162, 1, 8, 0, // Skip to: 4227 /* 4219 */ MCD_OPC_CheckPredicate, 0, 221, 16, // Skip to: 8540 /* 4223 */ MCD_OPC_Decode, 176, 8, 113, // Opcode: CXLGBR /* 4227 */ MCD_OPC_FilterValue, 164, 1, 18, 0, // Skip to: 4250 /* 4232 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4242 /* 4238 */ MCD_OPC_Decode, 171, 4, 114, // Opcode: CEGBR /* 4242 */ MCD_OPC_CheckPredicate, 0, 198, 16, // Skip to: 8540 /* 4246 */ MCD_OPC_Decode, 172, 4, 111, // Opcode: CEGBRA /* 4250 */ MCD_OPC_FilterValue, 165, 1, 18, 0, // Skip to: 4273 /* 4255 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4265 /* 4261 */ MCD_OPC_Decode, 146, 4, 115, // Opcode: CDGBR /* 4265 */ MCD_OPC_CheckPredicate, 0, 175, 16, // Skip to: 8540 /* 4269 */ MCD_OPC_Decode, 147, 4, 112, // Opcode: CDGBRA /* 4273 */ MCD_OPC_FilterValue, 166, 1, 18, 0, // Skip to: 4296 /* 4278 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 4288 /* 4284 */ MCD_OPC_Decode, 169, 8, 116, // Opcode: CXGBR /* 4288 */ MCD_OPC_CheckPredicate, 0, 152, 16, // Skip to: 8540 /* 4292 */ MCD_OPC_Decode, 170, 8, 113, // Opcode: CXGBRA /* 4296 */ MCD_OPC_FilterValue, 168, 1, 18, 0, // Skip to: 4319 /* 4301 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4311 /* 4307 */ MCD_OPC_Decode, 197, 4, 117, // Opcode: CGEBR /* 4311 */ MCD_OPC_CheckPredicate, 0, 129, 16, // Skip to: 8540 /* 4315 */ MCD_OPC_Decode, 198, 4, 118, // Opcode: CGEBRA /* 4319 */ MCD_OPC_FilterValue, 169, 1, 18, 0, // Skip to: 4342 /* 4324 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4334 /* 4330 */ MCD_OPC_Decode, 192, 4, 119, // Opcode: CGDBR /* 4334 */ MCD_OPC_CheckPredicate, 0, 106, 16, // Skip to: 8540 /* 4338 */ MCD_OPC_Decode, 193, 4, 120, // Opcode: CGDBRA /* 4342 */ MCD_OPC_FilterValue, 170, 1, 18, 0, // Skip to: 4365 /* 4347 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4357 /* 4353 */ MCD_OPC_Decode, 166, 5, 121, // Opcode: CGXBR /* 4357 */ MCD_OPC_CheckPredicate, 0, 83, 16, // Skip to: 8540 /* 4361 */ MCD_OPC_Decode, 167, 5, 122, // Opcode: CGXBRA /* 4365 */ MCD_OPC_FilterValue, 172, 1, 8, 0, // Skip to: 4378 /* 4370 */ MCD_OPC_CheckPredicate, 0, 70, 16, // Skip to: 8540 /* 4374 */ MCD_OPC_Decode, 253, 5, 118, // Opcode: CLGEBR /* 4378 */ MCD_OPC_FilterValue, 173, 1, 8, 0, // Skip to: 4391 /* 4383 */ MCD_OPC_CheckPredicate, 0, 57, 16, // Skip to: 8540 /* 4387 */ MCD_OPC_Decode, 251, 5, 120, // Opcode: CLGDBR /* 4391 */ MCD_OPC_FilterValue, 174, 1, 8, 0, // Skip to: 4404 /* 4396 */ MCD_OPC_CheckPredicate, 0, 44, 16, // Skip to: 8540 /* 4400 */ MCD_OPC_Decode, 232, 6, 122, // Opcode: CLGXBR /* 4404 */ MCD_OPC_FilterValue, 180, 1, 10, 0, // Skip to: 4419 /* 4409 */ MCD_OPC_CheckField, 8, 8, 0, 29, 16, // Skip to: 8540 /* 4415 */ MCD_OPC_Decode, 170, 4, 102, // Opcode: CEFR /* 4419 */ MCD_OPC_FilterValue, 181, 1, 10, 0, // Skip to: 4434 /* 4424 */ MCD_OPC_CheckField, 8, 8, 0, 14, 16, // Skip to: 8540 /* 4430 */ MCD_OPC_Decode, 144, 4, 103, // Opcode: CDFR /* 4434 */ MCD_OPC_FilterValue, 182, 1, 10, 0, // Skip to: 4449 /* 4439 */ MCD_OPC_CheckField, 8, 8, 0, 255, 15, // Skip to: 8540 /* 4445 */ MCD_OPC_Decode, 167, 8, 104, // Opcode: CXFR /* 4449 */ MCD_OPC_FilterValue, 184, 1, 10, 0, // Skip to: 4464 /* 4454 */ MCD_OPC_CheckField, 8, 4, 0, 240, 15, // Skip to: 8540 /* 4460 */ MCD_OPC_Decode, 185, 4, 105, // Opcode: CFER /* 4464 */ MCD_OPC_FilterValue, 185, 1, 10, 0, // Skip to: 4479 /* 4469 */ MCD_OPC_CheckField, 8, 4, 0, 225, 15, // Skip to: 8540 /* 4475 */ MCD_OPC_Decode, 181, 4, 107, // Opcode: CFDR /* 4479 */ MCD_OPC_FilterValue, 186, 1, 10, 0, // Skip to: 4494 /* 4484 */ MCD_OPC_CheckField, 8, 4, 0, 210, 15, // Skip to: 8540 /* 4490 */ MCD_OPC_Decode, 189, 4, 109, // Opcode: CFXR /* 4494 */ MCD_OPC_FilterValue, 193, 1, 10, 0, // Skip to: 4509 /* 4499 */ MCD_OPC_CheckField, 8, 8, 0, 195, 15, // Skip to: 8540 /* 4505 */ MCD_OPC_Decode, 153, 10, 115, // Opcode: LDGR /* 4509 */ MCD_OPC_FilterValue, 196, 1, 10, 0, // Skip to: 4524 /* 4514 */ MCD_OPC_CheckField, 8, 8, 0, 180, 15, // Skip to: 8540 /* 4520 */ MCD_OPC_Decode, 173, 4, 114, // Opcode: CEGR /* 4524 */ MCD_OPC_FilterValue, 197, 1, 10, 0, // Skip to: 4539 /* 4529 */ MCD_OPC_CheckField, 8, 8, 0, 165, 15, // Skip to: 8540 /* 4535 */ MCD_OPC_Decode, 148, 4, 115, // Opcode: CDGR /* 4539 */ MCD_OPC_FilterValue, 198, 1, 10, 0, // Skip to: 4554 /* 4544 */ MCD_OPC_CheckField, 8, 8, 0, 150, 15, // Skip to: 8540 /* 4550 */ MCD_OPC_Decode, 171, 8, 116, // Opcode: CXGR /* 4554 */ MCD_OPC_FilterValue, 200, 1, 10, 0, // Skip to: 4569 /* 4559 */ MCD_OPC_CheckField, 8, 4, 0, 135, 15, // Skip to: 8540 /* 4565 */ MCD_OPC_Decode, 199, 4, 117, // Opcode: CGER /* 4569 */ MCD_OPC_FilterValue, 201, 1, 10, 0, // Skip to: 4584 /* 4574 */ MCD_OPC_CheckField, 8, 4, 0, 120, 15, // Skip to: 8540 /* 4580 */ MCD_OPC_Decode, 194, 4, 119, // Opcode: CGDR /* 4584 */ MCD_OPC_FilterValue, 202, 1, 10, 0, // Skip to: 4599 /* 4589 */ MCD_OPC_CheckField, 8, 4, 0, 105, 15, // Skip to: 8540 /* 4595 */ MCD_OPC_Decode, 168, 5, 121, // Opcode: CGXR /* 4599 */ MCD_OPC_FilterValue, 205, 1, 10, 0, // Skip to: 4614 /* 4604 */ MCD_OPC_CheckField, 8, 8, 0, 90, 15, // Skip to: 8540 /* 4610 */ MCD_OPC_Decode, 179, 10, 123, // Opcode: LGDR /* 4614 */ MCD_OPC_FilterValue, 208, 1, 18, 0, // Skip to: 4637 /* 4619 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4629 /* 4625 */ MCD_OPC_Decode, 146, 13, 95, // Opcode: MDTR /* 4629 */ MCD_OPC_CheckPredicate, 0, 67, 15, // Skip to: 8540 /* 4633 */ MCD_OPC_Decode, 147, 13, 124, // Opcode: MDTRA /* 4637 */ MCD_OPC_FilterValue, 209, 1, 18, 0, // Skip to: 4660 /* 4642 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4652 /* 4648 */ MCD_OPC_Decode, 192, 8, 95, // Opcode: DDTR /* 4652 */ MCD_OPC_CheckPredicate, 0, 44, 15, // Skip to: 8540 /* 4656 */ MCD_OPC_Decode, 193, 8, 124, // Opcode: DDTRA /* 4660 */ MCD_OPC_FilterValue, 210, 1, 18, 0, // Skip to: 4683 /* 4665 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4675 /* 4671 */ MCD_OPC_Decode, 233, 2, 95, // Opcode: ADTR /* 4675 */ MCD_OPC_CheckPredicate, 0, 21, 15, // Skip to: 8540 /* 4679 */ MCD_OPC_Decode, 234, 2, 124, // Opcode: ADTRA /* 4683 */ MCD_OPC_FilterValue, 211, 1, 18, 0, // Skip to: 4706 /* 4688 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4698 /* 4694 */ MCD_OPC_Decode, 194, 14, 95, // Opcode: SDTR /* 4698 */ MCD_OPC_CheckPredicate, 0, 254, 14, // Skip to: 8540 /* 4702 */ MCD_OPC_Decode, 195, 14, 124, // Opcode: SDTRA /* 4706 */ MCD_OPC_FilterValue, 212, 1, 10, 0, // Skip to: 4721 /* 4711 */ MCD_OPC_CheckField, 12, 4, 0, 239, 14, // Skip to: 8540 /* 4717 */ MCD_OPC_Decode, 152, 10, 125, // Opcode: LDETR /* 4721 */ MCD_OPC_FilterValue, 213, 1, 4, 0, // Skip to: 4730 /* 4726 */ MCD_OPC_Decode, 165, 10, 84, // Opcode: LEDTR /* 4730 */ MCD_OPC_FilterValue, 214, 1, 10, 0, // Skip to: 4745 /* 4735 */ MCD_OPC_CheckField, 8, 8, 0, 215, 14, // Skip to: 8540 /* 4741 */ MCD_OPC_Decode, 219, 12, 11, // Opcode: LTDTR /* 4745 */ MCD_OPC_FilterValue, 215, 1, 4, 0, // Skip to: 4754 /* 4750 */ MCD_OPC_Decode, 243, 8, 93, // Opcode: FIDTR /* 4754 */ MCD_OPC_FilterValue, 216, 1, 18, 0, // Skip to: 4777 /* 4759 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4769 /* 4765 */ MCD_OPC_Decode, 218, 13, 126, // Opcode: MXTR /* 4769 */ MCD_OPC_CheckPredicate, 0, 183, 14, // Skip to: 8540 /* 4773 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: MXTRA /* 4777 */ MCD_OPC_FilterValue, 217, 1, 18, 0, // Skip to: 4800 /* 4782 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4792 /* 4788 */ MCD_OPC_Decode, 213, 8, 126, // Opcode: DXTR /* 4792 */ MCD_OPC_CheckPredicate, 0, 160, 14, // Skip to: 8540 /* 4796 */ MCD_OPC_Decode, 214, 8, 127, // Opcode: DXTRA /* 4800 */ MCD_OPC_FilterValue, 218, 1, 18, 0, // Skip to: 4823 /* 4805 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4815 /* 4811 */ MCD_OPC_Decode, 162, 3, 126, // Opcode: AXTR /* 4815 */ MCD_OPC_CheckPredicate, 0, 137, 14, // Skip to: 8540 /* 4819 */ MCD_OPC_Decode, 163, 3, 127, // Opcode: AXTRA /* 4823 */ MCD_OPC_FilterValue, 219, 1, 18, 0, // Skip to: 4846 /* 4828 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4838 /* 4834 */ MCD_OPC_Decode, 152, 16, 126, // Opcode: SXTR /* 4838 */ MCD_OPC_CheckPredicate, 0, 114, 14, // Skip to: 8540 /* 4842 */ MCD_OPC_Decode, 153, 16, 127, // Opcode: SXTRA /* 4846 */ MCD_OPC_FilterValue, 220, 1, 11, 0, // Skip to: 4862 /* 4851 */ MCD_OPC_CheckField, 12, 4, 0, 99, 14, // Skip to: 8540 /* 4857 */ MCD_OPC_Decode, 238, 12, 128, 1, // Opcode: LXDTR /* 4862 */ MCD_OPC_FilterValue, 221, 1, 4, 0, // Skip to: 4871 /* 4867 */ MCD_OPC_Decode, 159, 10, 85, // Opcode: LDXTR /* 4871 */ MCD_OPC_FilterValue, 222, 1, 10, 0, // Skip to: 4886 /* 4876 */ MCD_OPC_CheckField, 8, 8, 0, 74, 14, // Skip to: 8540 /* 4882 */ MCD_OPC_Decode, 231, 12, 79, // Opcode: LTXTR /* 4886 */ MCD_OPC_FilterValue, 223, 1, 4, 0, // Skip to: 4895 /* 4891 */ MCD_OPC_Decode, 250, 8, 85, // Opcode: FIXTR /* 4895 */ MCD_OPC_FilterValue, 224, 1, 10, 0, // Skip to: 4910 /* 4900 */ MCD_OPC_CheckField, 8, 8, 0, 50, 14, // Skip to: 8540 /* 4906 */ MCD_OPC_Decode, 222, 9, 11, // Opcode: KDTR /* 4910 */ MCD_OPC_FilterValue, 225, 1, 18, 0, // Skip to: 4933 /* 4915 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 4925 /* 4921 */ MCD_OPC_Decode, 195, 4, 119, // Opcode: CGDTR /* 4925 */ MCD_OPC_CheckPredicate, 0, 27, 14, // Skip to: 8540 /* 4929 */ MCD_OPC_Decode, 196, 4, 120, // Opcode: CGDTRA /* 4933 */ MCD_OPC_FilterValue, 226, 1, 10, 0, // Skip to: 4948 /* 4938 */ MCD_OPC_CheckField, 8, 8, 0, 12, 14, // Skip to: 8540 /* 4944 */ MCD_OPC_Decode, 151, 8, 123, // Opcode: CUDTR /* 4948 */ MCD_OPC_FilterValue, 227, 1, 11, 0, // Skip to: 4964 /* 4953 */ MCD_OPC_CheckField, 12, 4, 0, 253, 13, // Skip to: 8540 /* 4959 */ MCD_OPC_Decode, 134, 8, 129, 1, // Opcode: CSDTR /* 4964 */ MCD_OPC_FilterValue, 228, 1, 10, 0, // Skip to: 4979 /* 4969 */ MCD_OPC_CheckField, 8, 8, 0, 237, 13, // Skip to: 8540 /* 4975 */ MCD_OPC_Decode, 161, 4, 11, // Opcode: CDTR /* 4979 */ MCD_OPC_FilterValue, 229, 1, 10, 0, // Skip to: 4994 /* 4984 */ MCD_OPC_CheckField, 8, 8, 0, 222, 13, // Skip to: 8540 /* 4990 */ MCD_OPC_Decode, 222, 8, 11, // Opcode: EEDTR /* 4994 */ MCD_OPC_FilterValue, 231, 1, 10, 0, // Skip to: 5009 /* 4999 */ MCD_OPC_CheckField, 8, 8, 0, 207, 13, // Skip to: 8540 /* 5005 */ MCD_OPC_Decode, 233, 8, 11, // Opcode: ESDTR /* 5009 */ MCD_OPC_FilterValue, 232, 1, 10, 0, // Skip to: 5024 /* 5014 */ MCD_OPC_CheckField, 8, 8, 0, 192, 13, // Skip to: 8540 /* 5020 */ MCD_OPC_Decode, 235, 9, 79, // Opcode: KXTR /* 5024 */ MCD_OPC_FilterValue, 233, 1, 18, 0, // Skip to: 5047 /* 5029 */ MCD_OPC_CheckField, 8, 4, 0, 4, 0, // Skip to: 5039 /* 5035 */ MCD_OPC_Decode, 169, 5, 121, // Opcode: CGXTR /* 5039 */ MCD_OPC_CheckPredicate, 0, 169, 13, // Skip to: 8540 /* 5043 */ MCD_OPC_Decode, 170, 5, 122, // Opcode: CGXTRA /* 5047 */ MCD_OPC_FilterValue, 234, 1, 11, 0, // Skip to: 5063 /* 5052 */ MCD_OPC_CheckField, 8, 8, 0, 154, 13, // Skip to: 8540 /* 5058 */ MCD_OPC_Decode, 157, 8, 130, 1, // Opcode: CUXTR /* 5063 */ MCD_OPC_FilterValue, 235, 1, 11, 0, // Skip to: 5079 /* 5068 */ MCD_OPC_CheckField, 12, 4, 0, 138, 13, // Skip to: 8540 /* 5074 */ MCD_OPC_Decode, 139, 8, 131, 1, // Opcode: CSXTR /* 5079 */ MCD_OPC_FilterValue, 236, 1, 10, 0, // Skip to: 5094 /* 5084 */ MCD_OPC_CheckField, 8, 8, 0, 122, 13, // Skip to: 8540 /* 5090 */ MCD_OPC_Decode, 181, 8, 79, // Opcode: CXTR /* 5094 */ MCD_OPC_FilterValue, 237, 1, 10, 0, // Skip to: 5109 /* 5099 */ MCD_OPC_CheckField, 8, 8, 0, 107, 13, // Skip to: 8540 /* 5105 */ MCD_OPC_Decode, 223, 8, 79, // Opcode: EEXTR /* 5109 */ MCD_OPC_FilterValue, 239, 1, 10, 0, // Skip to: 5124 /* 5114 */ MCD_OPC_CheckField, 8, 8, 0, 92, 13, // Skip to: 8540 /* 5120 */ MCD_OPC_Decode, 236, 8, 79, // Opcode: ESXTR /* 5124 */ MCD_OPC_FilterValue, 241, 1, 18, 0, // Skip to: 5147 /* 5129 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5139 /* 5135 */ MCD_OPC_Decode, 149, 4, 115, // Opcode: CDGTR /* 5139 */ MCD_OPC_CheckPredicate, 0, 69, 13, // Skip to: 8540 /* 5143 */ MCD_OPC_Decode, 150, 4, 112, // Opcode: CDGTRA /* 5147 */ MCD_OPC_FilterValue, 242, 1, 10, 0, // Skip to: 5162 /* 5152 */ MCD_OPC_CheckField, 8, 8, 0, 54, 13, // Skip to: 8540 /* 5158 */ MCD_OPC_Decode, 162, 4, 115, // Opcode: CDUTR /* 5162 */ MCD_OPC_FilterValue, 243, 1, 10, 0, // Skip to: 5177 /* 5167 */ MCD_OPC_CheckField, 8, 8, 0, 39, 13, // Skip to: 8540 /* 5173 */ MCD_OPC_Decode, 159, 4, 115, // Opcode: CDSTR /* 5177 */ MCD_OPC_FilterValue, 244, 1, 10, 0, // Skip to: 5192 /* 5182 */ MCD_OPC_CheckField, 8, 8, 0, 24, 13, // Skip to: 8540 /* 5188 */ MCD_OPC_Decode, 167, 4, 11, // Opcode: CEDTR /* 5192 */ MCD_OPC_FilterValue, 245, 1, 4, 0, // Skip to: 5201 /* 5197 */ MCD_OPC_Decode, 156, 14, 92, // Opcode: QADTR /* 5201 */ MCD_OPC_FilterValue, 246, 1, 10, 0, // Skip to: 5216 /* 5206 */ MCD_OPC_CheckField, 8, 4, 0, 0, 13, // Skip to: 8540 /* 5212 */ MCD_OPC_Decode, 137, 9, 95, // Opcode: IEDTR /* 5216 */ MCD_OPC_FilterValue, 247, 1, 4, 0, // Skip to: 5225 /* 5221 */ MCD_OPC_Decode, 173, 14, 92, // Opcode: RRDTR /* 5225 */ MCD_OPC_FilterValue, 249, 1, 18, 0, // Skip to: 5248 /* 5230 */ MCD_OPC_CheckField, 8, 8, 0, 4, 0, // Skip to: 5240 /* 5236 */ MCD_OPC_Decode, 172, 8, 116, // Opcode: CXGTR /* 5240 */ MCD_OPC_CheckPredicate, 0, 224, 12, // Skip to: 8540 /* 5244 */ MCD_OPC_Decode, 173, 8, 113, // Opcode: CXGTRA /* 5248 */ MCD_OPC_FilterValue, 250, 1, 11, 0, // Skip to: 5264 /* 5253 */ MCD_OPC_CheckField, 8, 8, 0, 209, 12, // Skip to: 8540 /* 5259 */ MCD_OPC_Decode, 182, 8, 132, 1, // Opcode: CXUTR /* 5264 */ MCD_OPC_FilterValue, 251, 1, 11, 0, // Skip to: 5280 /* 5269 */ MCD_OPC_CheckField, 8, 8, 0, 193, 12, // Skip to: 8540 /* 5275 */ MCD_OPC_Decode, 180, 8, 132, 1, // Opcode: CXSTR /* 5280 */ MCD_OPC_FilterValue, 252, 1, 10, 0, // Skip to: 5295 /* 5285 */ MCD_OPC_CheckField, 8, 8, 0, 177, 12, // Skip to: 8540 /* 5291 */ MCD_OPC_Decode, 177, 4, 79, // Opcode: CEXTR /* 5295 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 5305 /* 5300 */ MCD_OPC_Decode, 157, 14, 133, 1, // Opcode: QAXTR /* 5305 */ MCD_OPC_FilterValue, 254, 1, 10, 0, // Skip to: 5320 /* 5310 */ MCD_OPC_CheckField, 8, 4, 0, 152, 12, // Skip to: 8540 /* 5316 */ MCD_OPC_Decode, 138, 9, 126, // Opcode: IEXTR /* 5320 */ MCD_OPC_FilterValue, 255, 1, 143, 12, // Skip to: 8540 /* 5325 */ MCD_OPC_Decode, 174, 14, 133, 1, // Opcode: RRXTR /* 5330 */ MCD_OPC_FilterValue, 182, 1, 5, 0, // Skip to: 5340 /* 5335 */ MCD_OPC_Decode, 170, 15, 134, 1, // Opcode: STCTL /* 5340 */ MCD_OPC_FilterValue, 183, 1, 5, 0, // Skip to: 5350 /* 5345 */ MCD_OPC_Decode, 142, 10, 134, 1, // Opcode: LCTL /* 5350 */ MCD_OPC_FilterValue, 185, 1, 64, 12, // Skip to: 8491 /* 5355 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 5358 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 5372 /* 5362 */ MCD_OPC_CheckField, 8, 8, 0, 100, 12, // Skip to: 8540 /* 5368 */ MCD_OPC_Decode, 193, 12, 61, // Opcode: LPGR /* 5372 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 5386 /* 5376 */ MCD_OPC_CheckField, 8, 8, 0, 86, 12, // Skip to: 8540 /* 5382 */ MCD_OPC_Decode, 237, 10, 61, // Opcode: LNGR /* 5386 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 5400 /* 5390 */ MCD_OPC_CheckField, 8, 8, 0, 72, 12, // Skip to: 8540 /* 5396 */ MCD_OPC_Decode, 226, 12, 61, // Opcode: LTGR /* 5400 */ MCD_OPC_FilterValue, 3, 10, 0, // Skip to: 5414 /* 5404 */ MCD_OPC_CheckField, 8, 8, 0, 58, 12, // Skip to: 8540 /* 5410 */ MCD_OPC_Decode, 140, 10, 61, // Opcode: LCGR /* 5414 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 5428 /* 5418 */ MCD_OPC_CheckField, 8, 8, 0, 44, 12, // Skip to: 8540 /* 5424 */ MCD_OPC_Decode, 189, 10, 61, // Opcode: LGR /* 5428 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 5442 /* 5432 */ MCD_OPC_CheckField, 8, 8, 0, 30, 12, // Skip to: 8540 /* 5438 */ MCD_OPC_Decode, 233, 12, 61, // Opcode: LURAG /* 5442 */ MCD_OPC_FilterValue, 6, 10, 0, // Skip to: 5456 /* 5446 */ MCD_OPC_CheckField, 8, 8, 0, 16, 12, // Skip to: 8540 /* 5452 */ MCD_OPC_Decode, 178, 10, 61, // Opcode: LGBR /* 5456 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 5470 /* 5460 */ MCD_OPC_CheckField, 8, 8, 0, 2, 12, // Skip to: 8540 /* 5466 */ MCD_OPC_Decode, 187, 10, 61, // Opcode: LGHR /* 5470 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 5485 /* 5474 */ MCD_OPC_CheckField, 8, 8, 0, 244, 11, // Skip to: 8540 /* 5480 */ MCD_OPC_Decode, 247, 2, 135, 1, // Opcode: AGR /* 5485 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 5500 /* 5489 */ MCD_OPC_CheckField, 8, 8, 0, 229, 11, // Skip to: 8540 /* 5495 */ MCD_OPC_Decode, 206, 14, 135, 1, // Opcode: SGR /* 5500 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 5515 /* 5504 */ MCD_OPC_CheckField, 8, 8, 0, 214, 11, // Skip to: 8540 /* 5510 */ MCD_OPC_Decode, 140, 3, 135, 1, // Opcode: ALGR /* 5515 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 5530 /* 5519 */ MCD_OPC_CheckField, 8, 8, 0, 199, 11, // Skip to: 8540 /* 5525 */ MCD_OPC_Decode, 231, 14, 135, 1, // Opcode: SLGR /* 5530 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 5545 /* 5534 */ MCD_OPC_CheckField, 8, 8, 0, 184, 11, // Skip to: 8540 /* 5540 */ MCD_OPC_Decode, 185, 13, 135, 1, // Opcode: MSGR /* 5545 */ MCD_OPC_FilterValue, 13, 10, 0, // Skip to: 5559 /* 5549 */ MCD_OPC_CheckField, 8, 8, 0, 169, 11, // Skip to: 8540 /* 5555 */ MCD_OPC_Decode, 210, 8, 68, // Opcode: DSGR /* 5559 */ MCD_OPC_FilterValue, 14, 10, 0, // Skip to: 5573 /* 5563 */ MCD_OPC_CheckField, 8, 8, 0, 155, 11, // Skip to: 8540 /* 5569 */ MCD_OPC_Decode, 230, 8, 61, // Opcode: EREGG /* 5573 */ MCD_OPC_FilterValue, 15, 10, 0, // Skip to: 5587 /* 5577 */ MCD_OPC_CheckField, 8, 8, 0, 141, 11, // Skip to: 8540 /* 5583 */ MCD_OPC_Decode, 211, 12, 61, // Opcode: LRVGR /* 5587 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 5601 /* 5591 */ MCD_OPC_CheckField, 8, 8, 0, 127, 11, // Skip to: 8540 /* 5597 */ MCD_OPC_Decode, 192, 12, 56, // Opcode: LPGFR /* 5601 */ MCD_OPC_FilterValue, 17, 10, 0, // Skip to: 5615 /* 5605 */ MCD_OPC_CheckField, 8, 8, 0, 113, 11, // Skip to: 8540 /* 5611 */ MCD_OPC_Decode, 236, 10, 56, // Opcode: LNGFR /* 5615 */ MCD_OPC_FilterValue, 18, 10, 0, // Skip to: 5629 /* 5619 */ MCD_OPC_CheckField, 8, 8, 0, 99, 11, // Skip to: 8540 /* 5625 */ MCD_OPC_Decode, 225, 12, 56, // Opcode: LTGFR /* 5629 */ MCD_OPC_FilterValue, 19, 10, 0, // Skip to: 5643 /* 5633 */ MCD_OPC_CheckField, 8, 8, 0, 85, 11, // Skip to: 8540 /* 5639 */ MCD_OPC_Decode, 139, 10, 56, // Opcode: LCGFR /* 5643 */ MCD_OPC_FilterValue, 20, 10, 0, // Skip to: 5657 /* 5647 */ MCD_OPC_CheckField, 8, 8, 0, 71, 11, // Skip to: 8540 /* 5653 */ MCD_OPC_Decode, 182, 10, 56, // Opcode: LGFR /* 5657 */ MCD_OPC_FilterValue, 22, 10, 0, // Skip to: 5671 /* 5661 */ MCD_OPC_CheckField, 8, 8, 0, 57, 11, // Skip to: 8540 /* 5667 */ MCD_OPC_Decode, 205, 10, 56, // Opcode: LLGFR /* 5671 */ MCD_OPC_FilterValue, 23, 10, 0, // Skip to: 5685 /* 5675 */ MCD_OPC_CheckField, 8, 8, 0, 43, 11, // Skip to: 8540 /* 5681 */ MCD_OPC_Decode, 213, 10, 61, // Opcode: LLGTR /* 5685 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 5700 /* 5689 */ MCD_OPC_CheckField, 8, 8, 0, 29, 11, // Skip to: 8540 /* 5695 */ MCD_OPC_Decode, 243, 2, 136, 1, // Opcode: AGFR /* 5700 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 5715 /* 5704 */ MCD_OPC_CheckField, 8, 8, 0, 14, 11, // Skip to: 8540 /* 5710 */ MCD_OPC_Decode, 204, 14, 136, 1, // Opcode: SGFR /* 5715 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 5730 /* 5719 */ MCD_OPC_CheckField, 8, 8, 0, 255, 10, // Skip to: 8540 /* 5725 */ MCD_OPC_Decode, 138, 3, 136, 1, // Opcode: ALGFR /* 5730 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 5745 /* 5734 */ MCD_OPC_CheckField, 8, 8, 0, 240, 10, // Skip to: 8540 /* 5740 */ MCD_OPC_Decode, 230, 14, 136, 1, // Opcode: SLGFR /* 5745 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 5760 /* 5749 */ MCD_OPC_CheckField, 8, 8, 0, 225, 10, // Skip to: 8540 /* 5755 */ MCD_OPC_Decode, 184, 13, 136, 1, // Opcode: MSGFR /* 5760 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 5774 /* 5764 */ MCD_OPC_CheckField, 8, 8, 0, 210, 10, // Skip to: 8540 /* 5770 */ MCD_OPC_Decode, 209, 8, 10, // Opcode: DSGFR /* 5774 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 5789 /* 5778 */ MCD_OPC_CheckField, 8, 8, 0, 196, 10, // Skip to: 8540 /* 5784 */ MCD_OPC_Decode, 229, 9, 137, 1, // Opcode: KMAC /* 5789 */ MCD_OPC_FilterValue, 31, 10, 0, // Skip to: 5803 /* 5793 */ MCD_OPC_CheckField, 8, 8, 0, 181, 10, // Skip to: 8540 /* 5799 */ MCD_OPC_Decode, 213, 12, 8, // Opcode: LRVR /* 5803 */ MCD_OPC_FilterValue, 32, 10, 0, // Skip to: 5817 /* 5807 */ MCD_OPC_CheckField, 8, 8, 0, 167, 10, // Skip to: 8540 /* 5813 */ MCD_OPC_Decode, 250, 4, 61, // Opcode: CGR /* 5817 */ MCD_OPC_FilterValue, 33, 10, 0, // Skip to: 5831 /* 5821 */ MCD_OPC_CheckField, 8, 8, 0, 153, 10, // Skip to: 8540 /* 5827 */ MCD_OPC_Decode, 174, 6, 61, // Opcode: CLGR /* 5831 */ MCD_OPC_FilterValue, 37, 10, 0, // Skip to: 5845 /* 5835 */ MCD_OPC_CheckField, 8, 8, 0, 139, 10, // Skip to: 8540 /* 5841 */ MCD_OPC_Decode, 143, 16, 61, // Opcode: STURG /* 5845 */ MCD_OPC_FilterValue, 38, 10, 0, // Skip to: 5859 /* 5849 */ MCD_OPC_CheckField, 8, 8, 0, 125, 10, // Skip to: 8540 /* 5855 */ MCD_OPC_Decode, 130, 10, 8, // Opcode: LBR /* 5859 */ MCD_OPC_FilterValue, 39, 10, 0, // Skip to: 5873 /* 5863 */ MCD_OPC_CheckField, 8, 8, 0, 111, 10, // Skip to: 8540 /* 5869 */ MCD_OPC_Decode, 195, 10, 8, // Opcode: LHR /* 5873 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 5891 /* 5877 */ MCD_OPC_CheckPredicate, 4, 99, 10, // Skip to: 8540 /* 5881 */ MCD_OPC_CheckField, 0, 16, 0, 93, 10, // Skip to: 8540 /* 5887 */ MCD_OPC_Decode, 136, 14, 0, // Opcode: PCKMO /* 5891 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 5910 /* 5895 */ MCD_OPC_CheckPredicate, 5, 81, 10, // Skip to: 8540 /* 5899 */ MCD_OPC_CheckField, 8, 4, 0, 75, 10, // Skip to: 8540 /* 5905 */ MCD_OPC_Decode, 228, 9, 138, 1, // Opcode: KMA /* 5910 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 5928 /* 5914 */ MCD_OPC_CheckPredicate, 6, 62, 10, // Skip to: 8540 /* 5918 */ MCD_OPC_CheckField, 8, 8, 0, 56, 10, // Skip to: 8540 /* 5924 */ MCD_OPC_Decode, 232, 9, 7, // Opcode: KMF /* 5928 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 5946 /* 5932 */ MCD_OPC_CheckPredicate, 6, 44, 10, // Skip to: 8540 /* 5936 */ MCD_OPC_CheckField, 8, 8, 0, 38, 10, // Skip to: 8540 /* 5942 */ MCD_OPC_Decode, 233, 9, 7, // Opcode: KMO /* 5946 */ MCD_OPC_FilterValue, 44, 14, 0, // Skip to: 5964 /* 5950 */ MCD_OPC_CheckPredicate, 6, 26, 10, // Skip to: 8540 /* 5954 */ MCD_OPC_CheckField, 0, 16, 0, 20, 10, // Skip to: 8540 /* 5960 */ MCD_OPC_Decode, 135, 14, 0, // Opcode: PCC /* 5964 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 5983 /* 5968 */ MCD_OPC_CheckPredicate, 6, 8, 10, // Skip to: 8540 /* 5972 */ MCD_OPC_CheckField, 8, 4, 0, 2, 10, // Skip to: 8540 /* 5978 */ MCD_OPC_Decode, 231, 9, 138, 1, // Opcode: KMCTR /* 5983 */ MCD_OPC_FilterValue, 46, 10, 0, // Skip to: 5997 /* 5987 */ MCD_OPC_CheckField, 8, 8, 0, 243, 9, // Skip to: 8540 /* 5993 */ MCD_OPC_Decode, 227, 9, 7, // Opcode: KM /* 5997 */ MCD_OPC_FilterValue, 47, 10, 0, // Skip to: 6011 /* 6001 */ MCD_OPC_CheckField, 8, 8, 0, 229, 9, // Skip to: 8540 /* 6007 */ MCD_OPC_Decode, 230, 9, 7, // Opcode: KMC /* 6011 */ MCD_OPC_FilterValue, 48, 10, 0, // Skip to: 6025 /* 6015 */ MCD_OPC_CheckField, 8, 8, 0, 215, 9, // Skip to: 8540 /* 6021 */ MCD_OPC_Decode, 202, 4, 56, // Opcode: CGFR /* 6025 */ MCD_OPC_FilterValue, 49, 10, 0, // Skip to: 6039 /* 6029 */ MCD_OPC_CheckField, 8, 8, 0, 201, 9, // Skip to: 8540 /* 6035 */ MCD_OPC_Decode, 128, 6, 56, // Opcode: CLGFR /* 6039 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 6057 /* 6043 */ MCD_OPC_CheckPredicate, 7, 189, 9, // Skip to: 8540 /* 6047 */ MCD_OPC_CheckField, 8, 8, 0, 183, 9, // Skip to: 8540 /* 6053 */ MCD_OPC_Decode, 148, 14, 7, // Opcode: PPNO /* 6057 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 6072 /* 6061 */ MCD_OPC_CheckField, 8, 8, 0, 169, 9, // Skip to: 8540 /* 6067 */ MCD_OPC_Decode, 225, 9, 137, 1, // Opcode: KIMD /* 6072 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 6087 /* 6076 */ MCD_OPC_CheckField, 8, 8, 0, 154, 9, // Skip to: 8540 /* 6082 */ MCD_OPC_Decode, 226, 9, 137, 1, // Opcode: KLMD /* 6087 */ MCD_OPC_FilterValue, 65, 8, 0, // Skip to: 6099 /* 6091 */ MCD_OPC_CheckPredicate, 0, 141, 9, // Skip to: 8540 /* 6095 */ MCD_OPC_Decode, 182, 4, 108, // Opcode: CFDTR /* 6099 */ MCD_OPC_FilterValue, 66, 8, 0, // Skip to: 6111 /* 6103 */ MCD_OPC_CheckPredicate, 0, 129, 9, // Skip to: 8540 /* 6107 */ MCD_OPC_Decode, 252, 5, 120, // Opcode: CLGDTR /* 6111 */ MCD_OPC_FilterValue, 67, 8, 0, // Skip to: 6123 /* 6115 */ MCD_OPC_CheckPredicate, 0, 117, 9, // Skip to: 8540 /* 6119 */ MCD_OPC_Decode, 230, 5, 108, // Opcode: CLFDTR /* 6123 */ MCD_OPC_FilterValue, 70, 11, 0, // Skip to: 6138 /* 6127 */ MCD_OPC_CheckField, 8, 8, 0, 103, 9, // Skip to: 8540 /* 6133 */ MCD_OPC_Decode, 198, 3, 135, 1, // Opcode: BCTGR /* 6138 */ MCD_OPC_FilterValue, 73, 8, 0, // Skip to: 6150 /* 6142 */ MCD_OPC_CheckPredicate, 0, 90, 9, // Skip to: 8540 /* 6146 */ MCD_OPC_Decode, 190, 4, 110, // Opcode: CFXTR /* 6150 */ MCD_OPC_FilterValue, 74, 8, 0, // Skip to: 6162 /* 6154 */ MCD_OPC_CheckPredicate, 0, 78, 9, // Skip to: 8540 /* 6158 */ MCD_OPC_Decode, 233, 6, 122, // Opcode: CLGXTR /* 6162 */ MCD_OPC_FilterValue, 75, 8, 0, // Skip to: 6174 /* 6166 */ MCD_OPC_CheckPredicate, 0, 66, 9, // Skip to: 8540 /* 6170 */ MCD_OPC_Decode, 249, 5, 110, // Opcode: CLFXTR /* 6174 */ MCD_OPC_FilterValue, 81, 8, 0, // Skip to: 6186 /* 6178 */ MCD_OPC_CheckPredicate, 0, 54, 9, // Skip to: 8540 /* 6182 */ MCD_OPC_Decode, 145, 4, 100, // Opcode: CDFTR /* 6186 */ MCD_OPC_FilterValue, 82, 8, 0, // Skip to: 6198 /* 6190 */ MCD_OPC_CheckPredicate, 0, 42, 9, // Skip to: 8540 /* 6194 */ MCD_OPC_Decode, 154, 4, 112, // Opcode: CDLGTR /* 6198 */ MCD_OPC_FilterValue, 83, 8, 0, // Skip to: 6210 /* 6202 */ MCD_OPC_CheckPredicate, 0, 30, 9, // Skip to: 8540 /* 6206 */ MCD_OPC_Decode, 152, 4, 100, // Opcode: CDLFTR /* 6210 */ MCD_OPC_FilterValue, 89, 8, 0, // Skip to: 6222 /* 6214 */ MCD_OPC_CheckPredicate, 0, 18, 9, // Skip to: 8540 /* 6218 */ MCD_OPC_Decode, 168, 8, 101, // Opcode: CXFTR /* 6222 */ MCD_OPC_FilterValue, 90, 8, 0, // Skip to: 6234 /* 6226 */ MCD_OPC_CheckPredicate, 0, 6, 9, // Skip to: 8540 /* 6230 */ MCD_OPC_Decode, 177, 8, 113, // Opcode: CXLGTR /* 6234 */ MCD_OPC_FilterValue, 91, 8, 0, // Skip to: 6246 /* 6238 */ MCD_OPC_CheckPredicate, 0, 250, 8, // Skip to: 8540 /* 6242 */ MCD_OPC_Decode, 175, 8, 101, // Opcode: CXLFTR /* 6246 */ MCD_OPC_FilterValue, 96, 62, 0, // Skip to: 6312 /* 6250 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6253 */ MCD_OPC_FilterValue, 0, 235, 8, // Skip to: 8540 /* 6257 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6260 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6268 /* 6264 */ MCD_OPC_Decode, 155, 5, 61, // Opcode: CGRTAsmH /* 6268 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6276 /* 6272 */ MCD_OPC_Decode, 157, 5, 61, // Opcode: CGRTAsmL /* 6276 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6284 /* 6280 */ MCD_OPC_Decode, 159, 5, 61, // Opcode: CGRTAsmLH /* 6284 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6292 /* 6288 */ MCD_OPC_Decode, 154, 5, 61, // Opcode: CGRTAsmE /* 6292 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6300 /* 6296 */ MCD_OPC_Decode, 156, 5, 61, // Opcode: CGRTAsmHE /* 6300 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6308 /* 6304 */ MCD_OPC_Decode, 158, 5, 61, // Opcode: CGRTAsmLE /* 6308 */ MCD_OPC_Decode, 153, 5, 73, // Opcode: CGRTAsm /* 6312 */ MCD_OPC_FilterValue, 97, 62, 0, // Skip to: 6378 /* 6316 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6319 */ MCD_OPC_FilterValue, 0, 169, 8, // Skip to: 8540 /* 6323 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6326 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6334 /* 6330 */ MCD_OPC_Decode, 207, 6, 61, // Opcode: CLGRTAsmH /* 6334 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6342 /* 6338 */ MCD_OPC_Decode, 209, 6, 61, // Opcode: CLGRTAsmL /* 6342 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6350 /* 6346 */ MCD_OPC_Decode, 211, 6, 61, // Opcode: CLGRTAsmLH /* 6350 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6358 /* 6354 */ MCD_OPC_Decode, 206, 6, 61, // Opcode: CLGRTAsmE /* 6358 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6366 /* 6362 */ MCD_OPC_Decode, 208, 6, 61, // Opcode: CLGRTAsmHE /* 6366 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6374 /* 6370 */ MCD_OPC_Decode, 210, 6, 61, // Opcode: CLGRTAsmLE /* 6374 */ MCD_OPC_Decode, 205, 6, 73, // Opcode: CLGRTAsm /* 6378 */ MCD_OPC_FilterValue, 114, 63, 0, // Skip to: 6445 /* 6382 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6385 */ MCD_OPC_FilterValue, 0, 103, 8, // Skip to: 8540 /* 6389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6392 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6400 /* 6396 */ MCD_OPC_Decode, 249, 7, 8, // Opcode: CRTAsmH /* 6400 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6408 /* 6404 */ MCD_OPC_Decode, 251, 7, 8, // Opcode: CRTAsmL /* 6408 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6416 /* 6412 */ MCD_OPC_Decode, 253, 7, 8, // Opcode: CRTAsmLH /* 6416 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6424 /* 6420 */ MCD_OPC_Decode, 248, 7, 8, // Opcode: CRTAsmE /* 6424 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6432 /* 6428 */ MCD_OPC_Decode, 250, 7, 8, // Opcode: CRTAsmHE /* 6432 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6440 /* 6436 */ MCD_OPC_Decode, 252, 7, 8, // Opcode: CRTAsmLE /* 6440 */ MCD_OPC_Decode, 247, 7, 139, 1, // Opcode: CRTAsm /* 6445 */ MCD_OPC_FilterValue, 115, 63, 0, // Skip to: 6512 /* 6449 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6452 */ MCD_OPC_FilterValue, 0, 36, 8, // Skip to: 8540 /* 6456 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6459 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 6467 /* 6463 */ MCD_OPC_Decode, 178, 7, 8, // Opcode: CLRTAsmH /* 6467 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 6475 /* 6471 */ MCD_OPC_Decode, 180, 7, 8, // Opcode: CLRTAsmL /* 6475 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 6483 /* 6479 */ MCD_OPC_Decode, 182, 7, 8, // Opcode: CLRTAsmLH /* 6483 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 6491 /* 6487 */ MCD_OPC_Decode, 177, 7, 8, // Opcode: CLRTAsmE /* 6491 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 6499 /* 6495 */ MCD_OPC_Decode, 179, 7, 8, // Opcode: CLRTAsmHE /* 6499 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 6507 /* 6503 */ MCD_OPC_Decode, 181, 7, 8, // Opcode: CLRTAsmLE /* 6507 */ MCD_OPC_Decode, 176, 7, 139, 1, // Opcode: CLRTAsm /* 6512 */ MCD_OPC_FilterValue, 128, 1, 11, 0, // Skip to: 6528 /* 6517 */ MCD_OPC_CheckField, 8, 8, 0, 225, 7, // Skip to: 8540 /* 6523 */ MCD_OPC_Decode, 229, 13, 135, 1, // Opcode: NGR /* 6528 */ MCD_OPC_FilterValue, 129, 1, 11, 0, // Skip to: 6544 /* 6533 */ MCD_OPC_CheckField, 8, 8, 0, 209, 7, // Skip to: 8540 /* 6539 */ MCD_OPC_Decode, 247, 13, 135, 1, // Opcode: OGR /* 6544 */ MCD_OPC_FilterValue, 130, 1, 11, 0, // Skip to: 6560 /* 6549 */ MCD_OPC_CheckField, 8, 8, 0, 193, 7, // Skip to: 8540 /* 6555 */ MCD_OPC_Decode, 229, 21, 135, 1, // Opcode: XGR /* 6560 */ MCD_OPC_FilterValue, 131, 1, 11, 0, // Skip to: 6576 /* 6565 */ MCD_OPC_CheckField, 8, 8, 0, 177, 7, // Skip to: 8540 /* 6571 */ MCD_OPC_Decode, 251, 8, 140, 1, // Opcode: FLOGR /* 6576 */ MCD_OPC_FilterValue, 132, 1, 10, 0, // Skip to: 6591 /* 6581 */ MCD_OPC_CheckField, 8, 8, 0, 161, 7, // Skip to: 8540 /* 6587 */ MCD_OPC_Decode, 202, 10, 61, // Opcode: LLGCR /* 6591 */ MCD_OPC_FilterValue, 133, 1, 10, 0, // Skip to: 6606 /* 6596 */ MCD_OPC_CheckField, 8, 8, 0, 146, 7, // Skip to: 8540 /* 6602 */ MCD_OPC_Decode, 209, 10, 61, // Opcode: LLGHR /* 6606 */ MCD_OPC_FilterValue, 134, 1, 10, 0, // Skip to: 6621 /* 6611 */ MCD_OPC_CheckField, 8, 8, 0, 131, 7, // Skip to: 8540 /* 6617 */ MCD_OPC_Decode, 164, 13, 68, // Opcode: MLGR /* 6621 */ MCD_OPC_FilterValue, 135, 1, 10, 0, // Skip to: 6636 /* 6626 */ MCD_OPC_CheckField, 8, 8, 0, 116, 7, // Skip to: 8540 /* 6632 */ MCD_OPC_Decode, 203, 8, 68, // Opcode: DLGR /* 6636 */ MCD_OPC_FilterValue, 136, 1, 11, 0, // Skip to: 6652 /* 6641 */ MCD_OPC_CheckField, 8, 8, 0, 101, 7, // Skip to: 8540 /* 6647 */ MCD_OPC_Decode, 132, 3, 135, 1, // Opcode: ALCGR /* 6652 */ MCD_OPC_FilterValue, 137, 1, 11, 0, // Skip to: 6668 /* 6657 */ MCD_OPC_CheckField, 8, 8, 0, 85, 7, // Skip to: 8540 /* 6663 */ MCD_OPC_Decode, 221, 14, 135, 1, // Opcode: SLBGR /* 6668 */ MCD_OPC_FilterValue, 138, 1, 10, 0, // Skip to: 6683 /* 6673 */ MCD_OPC_CheckField, 8, 8, 0, 69, 7, // Skip to: 8540 /* 6679 */ MCD_OPC_Decode, 137, 8, 68, // Opcode: CSPG /* 6683 */ MCD_OPC_FilterValue, 141, 1, 10, 0, // Skip to: 6698 /* 6688 */ MCD_OPC_CheckField, 8, 8, 0, 54, 7, // Skip to: 8540 /* 6694 */ MCD_OPC_Decode, 228, 8, 8, // Opcode: EPSW /* 6698 */ MCD_OPC_FilterValue, 142, 1, 16, 0, // Skip to: 6719 /* 6703 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6714 /* 6709 */ MCD_OPC_Decode, 136, 9, 141, 1, // Opcode: IDTEOpt /* 6714 */ MCD_OPC_Decode, 135, 9, 142, 1, // Opcode: IDTE /* 6719 */ MCD_OPC_FilterValue, 143, 1, 24, 0, // Skip to: 6748 /* 6724 */ MCD_OPC_CheckPredicate, 8, 11, 0, // Skip to: 6739 /* 6728 */ MCD_OPC_CheckField, 8, 4, 0, 5, 0, // Skip to: 6739 /* 6734 */ MCD_OPC_Decode, 230, 7, 143, 1, // Opcode: CRDTEOpt /* 6739 */ MCD_OPC_CheckPredicate, 8, 5, 7, // Skip to: 8540 /* 6743 */ MCD_OPC_Decode, 229, 7, 144, 1, // Opcode: CRDTE /* 6748 */ MCD_OPC_FilterValue, 144, 1, 22, 0, // Skip to: 6775 /* 6753 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6756 */ MCD_OPC_FilterValue, 0, 244, 6, // Skip to: 8540 /* 6760 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6770 /* 6766 */ MCD_OPC_Decode, 203, 16, 71, // Opcode: TRTTOpt /* 6770 */ MCD_OPC_Decode, 202, 16, 145, 1, // Opcode: TRTT /* 6775 */ MCD_OPC_FilterValue, 145, 1, 22, 0, // Skip to: 6802 /* 6780 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6783 */ MCD_OPC_FilterValue, 0, 217, 6, // Skip to: 8540 /* 6787 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6797 /* 6793 */ MCD_OPC_Decode, 198, 16, 71, // Opcode: TRTOOpt /* 6797 */ MCD_OPC_Decode, 197, 16, 145, 1, // Opcode: TRTO /* 6802 */ MCD_OPC_FilterValue, 146, 1, 22, 0, // Skip to: 6829 /* 6807 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6810 */ MCD_OPC_FilterValue, 0, 190, 6, // Skip to: 8540 /* 6814 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6824 /* 6820 */ MCD_OPC_Decode, 193, 16, 71, // Opcode: TROTOpt /* 6824 */ MCD_OPC_Decode, 192, 16, 145, 1, // Opcode: TROT /* 6829 */ MCD_OPC_FilterValue, 147, 1, 22, 0, // Skip to: 6856 /* 6834 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 6837 */ MCD_OPC_FilterValue, 0, 163, 6, // Skip to: 8540 /* 6841 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 6851 /* 6847 */ MCD_OPC_Decode, 191, 16, 71, // Opcode: TROOOpt /* 6851 */ MCD_OPC_Decode, 190, 16, 145, 1, // Opcode: TROO /* 6856 */ MCD_OPC_FilterValue, 148, 1, 10, 0, // Skip to: 6871 /* 6861 */ MCD_OPC_CheckField, 8, 8, 0, 137, 6, // Skip to: 8540 /* 6867 */ MCD_OPC_Decode, 200, 10, 8, // Opcode: LLCR /* 6871 */ MCD_OPC_FilterValue, 149, 1, 10, 0, // Skip to: 6886 /* 6876 */ MCD_OPC_CheckField, 8, 8, 0, 122, 6, // Skip to: 8540 /* 6882 */ MCD_OPC_Decode, 216, 10, 8, // Opcode: LLHR /* 6886 */ MCD_OPC_FilterValue, 150, 1, 10, 0, // Skip to: 6901 /* 6891 */ MCD_OPC_CheckField, 8, 8, 0, 107, 6, // Skip to: 8540 /* 6897 */ MCD_OPC_Decode, 165, 13, 10, // Opcode: MLR /* 6901 */ MCD_OPC_FilterValue, 151, 1, 10, 0, // Skip to: 6916 /* 6906 */ MCD_OPC_CheckField, 8, 8, 0, 92, 6, // Skip to: 8540 /* 6912 */ MCD_OPC_Decode, 204, 8, 10, // Opcode: DLR /* 6916 */ MCD_OPC_FilterValue, 152, 1, 10, 0, // Skip to: 6931 /* 6921 */ MCD_OPC_CheckField, 8, 8, 0, 77, 6, // Skip to: 8540 /* 6927 */ MCD_OPC_Decode, 133, 3, 9, // Opcode: ALCR /* 6931 */ MCD_OPC_FilterValue, 153, 1, 10, 0, // Skip to: 6946 /* 6936 */ MCD_OPC_CheckField, 8, 8, 0, 62, 6, // Skip to: 8540 /* 6942 */ MCD_OPC_Decode, 222, 14, 9, // Opcode: SLBR /* 6946 */ MCD_OPC_FilterValue, 154, 1, 17, 0, // Skip to: 6968 /* 6951 */ MCD_OPC_CheckField, 8, 8, 0, 47, 6, // Skip to: 8540 /* 6957 */ MCD_OPC_CheckField, 0, 4, 0, 41, 6, // Skip to: 8540 /* 6963 */ MCD_OPC_Decode, 225, 8, 146, 1, // Opcode: EPAIR /* 6968 */ MCD_OPC_FilterValue, 155, 1, 17, 0, // Skip to: 6990 /* 6973 */ MCD_OPC_CheckField, 8, 8, 0, 25, 6, // Skip to: 8540 /* 6979 */ MCD_OPC_CheckField, 0, 4, 0, 19, 6, // Skip to: 8540 /* 6985 */ MCD_OPC_Decode, 231, 8, 146, 1, // Opcode: ESAIR /* 6990 */ MCD_OPC_FilterValue, 157, 1, 17, 0, // Skip to: 7012 /* 6995 */ MCD_OPC_CheckField, 8, 8, 0, 3, 6, // Skip to: 8540 /* 7001 */ MCD_OPC_CheckField, 0, 4, 0, 253, 5, // Skip to: 8540 /* 7007 */ MCD_OPC_Decode, 234, 8, 147, 1, // Opcode: ESEA /* 7012 */ MCD_OPC_FilterValue, 158, 1, 10, 0, // Skip to: 7027 /* 7017 */ MCD_OPC_CheckField, 8, 8, 0, 237, 5, // Skip to: 8540 /* 7023 */ MCD_OPC_Decode, 154, 14, 61, // Opcode: PTI /* 7027 */ MCD_OPC_FilterValue, 159, 1, 17, 0, // Skip to: 7049 /* 7032 */ MCD_OPC_CheckField, 8, 8, 0, 222, 5, // Skip to: 8540 /* 7038 */ MCD_OPC_CheckField, 0, 4, 0, 216, 5, // Skip to: 8540 /* 7044 */ MCD_OPC_Decode, 148, 15, 146, 1, // Opcode: SSAIR /* 7049 */ MCD_OPC_FilterValue, 162, 1, 17, 0, // Skip to: 7071 /* 7054 */ MCD_OPC_CheckField, 8, 8, 0, 200, 5, // Skip to: 8540 /* 7060 */ MCD_OPC_CheckField, 0, 4, 0, 194, 5, // Skip to: 8540 /* 7066 */ MCD_OPC_Decode, 152, 14, 148, 1, // Opcode: PTF /* 7071 */ MCD_OPC_FilterValue, 170, 1, 5, 0, // Skip to: 7081 /* 7076 */ MCD_OPC_Decode, 199, 12, 149, 1, // Opcode: LPTEA /* 7081 */ MCD_OPC_FilterValue, 172, 1, 14, 0, // Skip to: 7100 /* 7086 */ MCD_OPC_CheckPredicate, 9, 170, 5, // Skip to: 8540 /* 7090 */ MCD_OPC_CheckField, 8, 8, 0, 164, 5, // Skip to: 8540 /* 7096 */ MCD_OPC_Decode, 150, 9, 61, // Opcode: IRBM /* 7100 */ MCD_OPC_FilterValue, 174, 1, 14, 0, // Skip to: 7119 /* 7105 */ MCD_OPC_CheckPredicate, 10, 151, 5, // Skip to: 8540 /* 7109 */ MCD_OPC_CheckField, 8, 8, 0, 145, 5, // Skip to: 8540 /* 7115 */ MCD_OPC_Decode, 172, 14, 61, // Opcode: RRBM /* 7119 */ MCD_OPC_FilterValue, 175, 1, 11, 0, // Skip to: 7135 /* 7124 */ MCD_OPC_CheckField, 8, 8, 0, 130, 5, // Skip to: 8540 /* 7130 */ MCD_OPC_Decode, 139, 14, 150, 1, // Opcode: PFMF /* 7135 */ MCD_OPC_FilterValue, 176, 1, 21, 0, // Skip to: 7161 /* 7140 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 7143 */ MCD_OPC_FilterValue, 0, 113, 5, // Skip to: 8540 /* 7147 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7157 /* 7153 */ MCD_OPC_Decode, 144, 8, 7, // Opcode: CU14Opt /* 7157 */ MCD_OPC_Decode, 143, 8, 72, // Opcode: CU14 /* 7161 */ MCD_OPC_FilterValue, 177, 1, 21, 0, // Skip to: 7187 /* 7166 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 7169 */ MCD_OPC_FilterValue, 0, 87, 5, // Skip to: 8540 /* 7173 */ MCD_OPC_CheckField, 12, 4, 0, 4, 0, // Skip to: 7183 /* 7179 */ MCD_OPC_Decode, 148, 8, 7, // Opcode: CU24Opt /* 7183 */ MCD_OPC_Decode, 147, 8, 72, // Opcode: CU24 /* 7187 */ MCD_OPC_FilterValue, 178, 1, 10, 0, // Skip to: 7202 /* 7192 */ MCD_OPC_CheckField, 8, 8, 0, 62, 5, // Skip to: 8540 /* 7198 */ MCD_OPC_Decode, 149, 8, 7, // Opcode: CU41 /* 7202 */ MCD_OPC_FilterValue, 179, 1, 10, 0, // Skip to: 7217 /* 7207 */ MCD_OPC_CheckField, 8, 8, 0, 47, 5, // Skip to: 8540 /* 7213 */ MCD_OPC_Decode, 150, 8, 7, // Opcode: CU42 /* 7217 */ MCD_OPC_FilterValue, 189, 1, 23, 0, // Skip to: 7245 /* 7222 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 7225 */ MCD_OPC_FilterValue, 0, 31, 5, // Skip to: 8540 /* 7229 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7240 /* 7235 */ MCD_OPC_Decode, 201, 16, 151, 1, // Opcode: TRTREOpt /* 7240 */ MCD_OPC_Decode, 200, 16, 152, 1, // Opcode: TRTRE /* 7245 */ MCD_OPC_FilterValue, 190, 1, 10, 0, // Skip to: 7260 /* 7250 */ MCD_OPC_CheckField, 8, 8, 0, 4, 5, // Skip to: 8540 /* 7256 */ MCD_OPC_Decode, 146, 15, 69, // Opcode: SRSTU /* 7260 */ MCD_OPC_FilterValue, 191, 1, 23, 0, // Skip to: 7288 /* 7265 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 7268 */ MCD_OPC_FilterValue, 0, 244, 4, // Skip to: 8540 /* 7272 */ MCD_OPC_CheckField, 12, 4, 0, 5, 0, // Skip to: 7283 /* 7278 */ MCD_OPC_Decode, 196, 16, 151, 1, // Opcode: TRTEOpt /* 7283 */ MCD_OPC_Decode, 195, 16, 152, 1, // Opcode: TRTE /* 7288 */ MCD_OPC_FilterValue, 200, 1, 15, 0, // Skip to: 7308 /* 7293 */ MCD_OPC_CheckPredicate, 11, 219, 4, // Skip to: 8540 /* 7297 */ MCD_OPC_CheckField, 8, 4, 0, 213, 4, // Skip to: 8540 /* 7303 */ MCD_OPC_Decode, 251, 2, 153, 1, // Opcode: AHHHR /* 7308 */ MCD_OPC_FilterValue, 201, 1, 15, 0, // Skip to: 7328 /* 7313 */ MCD_OPC_CheckPredicate, 11, 199, 4, // Skip to: 8540 /* 7317 */ MCD_OPC_CheckField, 8, 4, 0, 193, 4, // Skip to: 8540 /* 7323 */ MCD_OPC_Decode, 209, 14, 153, 1, // Opcode: SHHHR /* 7328 */ MCD_OPC_FilterValue, 202, 1, 15, 0, // Skip to: 7348 /* 7333 */ MCD_OPC_CheckPredicate, 11, 179, 4, // Skip to: 8540 /* 7337 */ MCD_OPC_CheckField, 8, 4, 0, 173, 4, // Skip to: 8540 /* 7343 */ MCD_OPC_Decode, 143, 3, 153, 1, // Opcode: ALHHHR /* 7348 */ MCD_OPC_FilterValue, 203, 1, 15, 0, // Skip to: 7368 /* 7353 */ MCD_OPC_CheckPredicate, 11, 159, 4, // Skip to: 8540 /* 7357 */ MCD_OPC_CheckField, 8, 4, 0, 153, 4, // Skip to: 8540 /* 7363 */ MCD_OPC_Decode, 233, 14, 153, 1, // Opcode: SLHHHR /* 7368 */ MCD_OPC_FilterValue, 205, 1, 15, 0, // Skip to: 7388 /* 7373 */ MCD_OPC_CheckPredicate, 11, 139, 4, // Skip to: 8540 /* 7377 */ MCD_OPC_CheckField, 8, 8, 0, 133, 4, // Skip to: 8540 /* 7383 */ MCD_OPC_Decode, 173, 5, 154, 1, // Opcode: CHHR /* 7388 */ MCD_OPC_FilterValue, 207, 1, 15, 0, // Skip to: 7408 /* 7393 */ MCD_OPC_CheckPredicate, 11, 119, 4, // Skip to: 8540 /* 7397 */ MCD_OPC_CheckField, 8, 8, 0, 113, 4, // Skip to: 8540 /* 7403 */ MCD_OPC_Decode, 235, 6, 154, 1, // Opcode: CLHHR /* 7408 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 7428 /* 7413 */ MCD_OPC_CheckPredicate, 11, 99, 4, // Skip to: 8540 /* 7417 */ MCD_OPC_CheckField, 8, 4, 0, 93, 4, // Skip to: 8540 /* 7423 */ MCD_OPC_Decode, 252, 2, 155, 1, // Opcode: AHHLR /* 7428 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 7448 /* 7433 */ MCD_OPC_CheckPredicate, 11, 79, 4, // Skip to: 8540 /* 7437 */ MCD_OPC_CheckField, 8, 4, 0, 73, 4, // Skip to: 8540 /* 7443 */ MCD_OPC_Decode, 210, 14, 155, 1, // Opcode: SHHLR /* 7448 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 7468 /* 7453 */ MCD_OPC_CheckPredicate, 11, 59, 4, // Skip to: 8540 /* 7457 */ MCD_OPC_CheckField, 8, 4, 0, 53, 4, // Skip to: 8540 /* 7463 */ MCD_OPC_Decode, 144, 3, 155, 1, // Opcode: ALHHLR /* 7468 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 7488 /* 7473 */ MCD_OPC_CheckPredicate, 11, 39, 4, // Skip to: 8540 /* 7477 */ MCD_OPC_CheckField, 8, 4, 0, 33, 4, // Skip to: 8540 /* 7483 */ MCD_OPC_Decode, 234, 14, 155, 1, // Opcode: SLHHLR /* 7488 */ MCD_OPC_FilterValue, 221, 1, 15, 0, // Skip to: 7508 /* 7493 */ MCD_OPC_CheckPredicate, 11, 19, 4, // Skip to: 8540 /* 7497 */ MCD_OPC_CheckField, 8, 8, 0, 13, 4, // Skip to: 8540 /* 7503 */ MCD_OPC_Decode, 176, 5, 156, 1, // Opcode: CHLR /* 7508 */ MCD_OPC_FilterValue, 223, 1, 15, 0, // Skip to: 7528 /* 7513 */ MCD_OPC_CheckPredicate, 11, 255, 3, // Skip to: 8540 /* 7517 */ MCD_OPC_CheckField, 8, 8, 0, 249, 3, // Skip to: 8540 /* 7523 */ MCD_OPC_Decode, 237, 6, 156, 1, // Opcode: CLHLR /* 7528 */ MCD_OPC_FilterValue, 224, 1, 201, 0, // Skip to: 7734 /* 7533 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 7536 */ MCD_OPC_FilterValue, 0, 232, 3, // Skip to: 8540 /* 7540 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7543 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7556 /* 7547 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 7725 /* 7551 */ MCD_OPC_Decode, 176, 11, 157, 1, // Opcode: LOCFHRAsmO /* 7556 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7569 /* 7560 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 7725 /* 7564 */ MCD_OPC_Decode, 160, 11, 157, 1, // Opcode: LOCFHRAsmH /* 7569 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7582 /* 7573 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 7725 /* 7577 */ MCD_OPC_Decode, 170, 11, 157, 1, // Opcode: LOCFHRAsmNLE /* 7582 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7595 /* 7586 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 7725 /* 7590 */ MCD_OPC_Decode, 162, 11, 157, 1, // Opcode: LOCFHRAsmL /* 7595 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7608 /* 7599 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 7725 /* 7603 */ MCD_OPC_Decode, 168, 11, 157, 1, // Opcode: LOCFHRAsmNHE /* 7608 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7621 /* 7612 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 7725 /* 7616 */ MCD_OPC_Decode, 164, 11, 157, 1, // Opcode: LOCFHRAsmLH /* 7621 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7634 /* 7625 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 7725 /* 7629 */ MCD_OPC_Decode, 166, 11, 157, 1, // Opcode: LOCFHRAsmNE /* 7634 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7647 /* 7638 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 7725 /* 7642 */ MCD_OPC_Decode, 159, 11, 157, 1, // Opcode: LOCFHRAsmE /* 7647 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7660 /* 7651 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 7725 /* 7655 */ MCD_OPC_Decode, 171, 11, 157, 1, // Opcode: LOCFHRAsmNLH /* 7660 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7673 /* 7664 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 7725 /* 7668 */ MCD_OPC_Decode, 161, 11, 157, 1, // Opcode: LOCFHRAsmHE /* 7673 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7686 /* 7677 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 7725 /* 7681 */ MCD_OPC_Decode, 169, 11, 157, 1, // Opcode: LOCFHRAsmNL /* 7686 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7699 /* 7690 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 7725 /* 7694 */ MCD_OPC_Decode, 163, 11, 157, 1, // Opcode: LOCFHRAsmLE /* 7699 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7712 /* 7703 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 7725 /* 7707 */ MCD_OPC_Decode, 167, 11, 157, 1, // Opcode: LOCFHRAsmNH /* 7712 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7725 /* 7716 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 7725 /* 7720 */ MCD_OPC_Decode, 173, 11, 157, 1, // Opcode: LOCFHRAsmNO /* 7725 */ MCD_OPC_CheckPredicate, 12, 43, 3, // Skip to: 8540 /* 7729 */ MCD_OPC_Decode, 158, 11, 158, 1, // Opcode: LOCFHRAsm /* 7734 */ MCD_OPC_FilterValue, 225, 1, 14, 0, // Skip to: 7753 /* 7739 */ MCD_OPC_CheckPredicate, 13, 29, 3, // Skip to: 8540 /* 7743 */ MCD_OPC_CheckField, 8, 8, 0, 23, 3, // Skip to: 8540 /* 7749 */ MCD_OPC_Decode, 146, 14, 61, // Opcode: POPCNT /* 7753 */ MCD_OPC_FilterValue, 226, 1, 201, 0, // Skip to: 7959 /* 7758 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 7761 */ MCD_OPC_FilterValue, 0, 7, 3, // Skip to: 8540 /* 7765 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7768 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7781 /* 7772 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 7950 /* 7776 */ MCD_OPC_Decode, 242, 11, 135, 1, // Opcode: LOCGRAsmO /* 7781 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7794 /* 7785 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 7950 /* 7789 */ MCD_OPC_Decode, 226, 11, 135, 1, // Opcode: LOCGRAsmH /* 7794 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7807 /* 7798 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 7950 /* 7802 */ MCD_OPC_Decode, 236, 11, 135, 1, // Opcode: LOCGRAsmNLE /* 7807 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7820 /* 7811 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 7950 /* 7815 */ MCD_OPC_Decode, 228, 11, 135, 1, // Opcode: LOCGRAsmL /* 7820 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7833 /* 7824 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 7950 /* 7828 */ MCD_OPC_Decode, 234, 11, 135, 1, // Opcode: LOCGRAsmNHE /* 7833 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7846 /* 7837 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 7950 /* 7841 */ MCD_OPC_Decode, 230, 11, 135, 1, // Opcode: LOCGRAsmLH /* 7846 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7859 /* 7850 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 7950 /* 7854 */ MCD_OPC_Decode, 232, 11, 135, 1, // Opcode: LOCGRAsmNE /* 7859 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 7872 /* 7863 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 7950 /* 7867 */ MCD_OPC_Decode, 225, 11, 135, 1, // Opcode: LOCGRAsmE /* 7872 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 7885 /* 7876 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 7950 /* 7880 */ MCD_OPC_Decode, 237, 11, 135, 1, // Opcode: LOCGRAsmNLH /* 7885 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 7898 /* 7889 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 7950 /* 7893 */ MCD_OPC_Decode, 227, 11, 135, 1, // Opcode: LOCGRAsmHE /* 7898 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 7911 /* 7902 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 7950 /* 7906 */ MCD_OPC_Decode, 235, 11, 135, 1, // Opcode: LOCGRAsmNL /* 7911 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 7924 /* 7915 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 7950 /* 7919 */ MCD_OPC_Decode, 229, 11, 135, 1, // Opcode: LOCGRAsmLE /* 7924 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 7937 /* 7928 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 7950 /* 7932 */ MCD_OPC_Decode, 233, 11, 135, 1, // Opcode: LOCGRAsmNH /* 7937 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 7950 /* 7941 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 7950 /* 7945 */ MCD_OPC_Decode, 239, 11, 135, 1, // Opcode: LOCGRAsmNO /* 7950 */ MCD_OPC_CheckPredicate, 14, 74, 2, // Skip to: 8540 /* 7954 */ MCD_OPC_Decode, 224, 11, 159, 1, // Opcode: LOCGRAsm /* 7959 */ MCD_OPC_FilterValue, 228, 1, 15, 0, // Skip to: 7979 /* 7964 */ MCD_OPC_CheckPredicate, 15, 60, 2, // Skip to: 8540 /* 7968 */ MCD_OPC_CheckField, 8, 4, 0, 54, 2, // Skip to: 8540 /* 7974 */ MCD_OPC_Decode, 230, 13, 141, 1, // Opcode: NGRK /* 7979 */ MCD_OPC_FilterValue, 230, 1, 15, 0, // Skip to: 7999 /* 7984 */ MCD_OPC_CheckPredicate, 15, 40, 2, // Skip to: 8540 /* 7988 */ MCD_OPC_CheckField, 8, 4, 0, 34, 2, // Skip to: 8540 /* 7994 */ MCD_OPC_Decode, 248, 13, 141, 1, // Opcode: OGRK /* 7999 */ MCD_OPC_FilterValue, 231, 1, 15, 0, // Skip to: 8019 /* 8004 */ MCD_OPC_CheckPredicate, 15, 20, 2, // Skip to: 8540 /* 8008 */ MCD_OPC_CheckField, 8, 4, 0, 14, 2, // Skip to: 8540 /* 8014 */ MCD_OPC_Decode, 230, 21, 141, 1, // Opcode: XGRK /* 8019 */ MCD_OPC_FilterValue, 232, 1, 15, 0, // Skip to: 8039 /* 8024 */ MCD_OPC_CheckPredicate, 15, 0, 2, // Skip to: 8540 /* 8028 */ MCD_OPC_CheckField, 8, 4, 0, 250, 1, // Skip to: 8540 /* 8034 */ MCD_OPC_Decode, 248, 2, 141, 1, // Opcode: AGRK /* 8039 */ MCD_OPC_FilterValue, 233, 1, 15, 0, // Skip to: 8059 /* 8044 */ MCD_OPC_CheckPredicate, 15, 236, 1, // Skip to: 8540 /* 8048 */ MCD_OPC_CheckField, 8, 4, 0, 230, 1, // Skip to: 8540 /* 8054 */ MCD_OPC_Decode, 207, 14, 141, 1, // Opcode: SGRK /* 8059 */ MCD_OPC_FilterValue, 234, 1, 15, 0, // Skip to: 8079 /* 8064 */ MCD_OPC_CheckPredicate, 15, 216, 1, // Skip to: 8540 /* 8068 */ MCD_OPC_CheckField, 8, 4, 0, 210, 1, // Skip to: 8540 /* 8074 */ MCD_OPC_Decode, 141, 3, 141, 1, // Opcode: ALGRK /* 8079 */ MCD_OPC_FilterValue, 235, 1, 15, 0, // Skip to: 8099 /* 8084 */ MCD_OPC_CheckPredicate, 15, 196, 1, // Skip to: 8540 /* 8088 */ MCD_OPC_CheckField, 8, 4, 0, 190, 1, // Skip to: 8540 /* 8094 */ MCD_OPC_Decode, 232, 14, 141, 1, // Opcode: SLGRK /* 8099 */ MCD_OPC_FilterValue, 236, 1, 15, 0, // Skip to: 8119 /* 8104 */ MCD_OPC_CheckPredicate, 16, 176, 1, // Skip to: 8540 /* 8108 */ MCD_OPC_CheckField, 8, 4, 0, 170, 1, // Skip to: 8540 /* 8114 */ MCD_OPC_Decode, 158, 13, 160, 1, // Opcode: MGRK /* 8119 */ MCD_OPC_FilterValue, 237, 1, 15, 0, // Skip to: 8139 /* 8124 */ MCD_OPC_CheckPredicate, 16, 156, 1, // Skip to: 8540 /* 8128 */ MCD_OPC_CheckField, 8, 4, 0, 150, 1, // Skip to: 8540 /* 8134 */ MCD_OPC_Decode, 186, 13, 141, 1, // Opcode: MSGRKC /* 8139 */ MCD_OPC_FilterValue, 242, 1, 187, 0, // Skip to: 8331 /* 8144 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 8147 */ MCD_OPC_FilterValue, 0, 133, 1, // Skip to: 8540 /* 8151 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8154 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 8166 /* 8158 */ MCD_OPC_CheckPredicate, 14, 160, 0, // Skip to: 8322 /* 8162 */ MCD_OPC_Decode, 180, 12, 9, // Opcode: LOCRAsmO /* 8166 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8178 /* 8170 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 8322 /* 8174 */ MCD_OPC_Decode, 164, 12, 9, // Opcode: LOCRAsmH /* 8178 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 8190 /* 8182 */ MCD_OPC_CheckPredicate, 14, 136, 0, // Skip to: 8322 /* 8186 */ MCD_OPC_Decode, 174, 12, 9, // Opcode: LOCRAsmNLE /* 8190 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8202 /* 8194 */ MCD_OPC_CheckPredicate, 14, 124, 0, // Skip to: 8322 /* 8198 */ MCD_OPC_Decode, 166, 12, 9, // Opcode: LOCRAsmL /* 8202 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 8214 /* 8206 */ MCD_OPC_CheckPredicate, 14, 112, 0, // Skip to: 8322 /* 8210 */ MCD_OPC_Decode, 172, 12, 9, // Opcode: LOCRAsmNHE /* 8214 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 8226 /* 8218 */ MCD_OPC_CheckPredicate, 14, 100, 0, // Skip to: 8322 /* 8222 */ MCD_OPC_Decode, 168, 12, 9, // Opcode: LOCRAsmLH /* 8226 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 8238 /* 8230 */ MCD_OPC_CheckPredicate, 14, 88, 0, // Skip to: 8322 /* 8234 */ MCD_OPC_Decode, 170, 12, 9, // Opcode: LOCRAsmNE /* 8238 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 8250 /* 8242 */ MCD_OPC_CheckPredicate, 14, 76, 0, // Skip to: 8322 /* 8246 */ MCD_OPC_Decode, 163, 12, 9, // Opcode: LOCRAsmE /* 8250 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 8262 /* 8254 */ MCD_OPC_CheckPredicate, 14, 64, 0, // Skip to: 8322 /* 8258 */ MCD_OPC_Decode, 175, 12, 9, // Opcode: LOCRAsmNLH /* 8262 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 8274 /* 8266 */ MCD_OPC_CheckPredicate, 14, 52, 0, // Skip to: 8322 /* 8270 */ MCD_OPC_Decode, 165, 12, 9, // Opcode: LOCRAsmHE /* 8274 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 8286 /* 8278 */ MCD_OPC_CheckPredicate, 14, 40, 0, // Skip to: 8322 /* 8282 */ MCD_OPC_Decode, 173, 12, 9, // Opcode: LOCRAsmNL /* 8286 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 8298 /* 8290 */ MCD_OPC_CheckPredicate, 14, 28, 0, // Skip to: 8322 /* 8294 */ MCD_OPC_Decode, 167, 12, 9, // Opcode: LOCRAsmLE /* 8298 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 8310 /* 8302 */ MCD_OPC_CheckPredicate, 14, 16, 0, // Skip to: 8322 /* 8306 */ MCD_OPC_Decode, 171, 12, 9, // Opcode: LOCRAsmNH /* 8310 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 8322 /* 8314 */ MCD_OPC_CheckPredicate, 14, 4, 0, // Skip to: 8322 /* 8318 */ MCD_OPC_Decode, 177, 12, 9, // Opcode: LOCRAsmNO /* 8322 */ MCD_OPC_CheckPredicate, 14, 214, 0, // Skip to: 8540 /* 8326 */ MCD_OPC_Decode, 162, 12, 161, 1, // Opcode: LOCRAsm /* 8331 */ MCD_OPC_FilterValue, 244, 1, 15, 0, // Skip to: 8351 /* 8336 */ MCD_OPC_CheckPredicate, 15, 200, 0, // Skip to: 8540 /* 8340 */ MCD_OPC_CheckField, 8, 4, 0, 194, 0, // Skip to: 8540 /* 8346 */ MCD_OPC_Decode, 241, 13, 162, 1, // Opcode: NRK /* 8351 */ MCD_OPC_FilterValue, 246, 1, 15, 0, // Skip to: 8371 /* 8356 */ MCD_OPC_CheckPredicate, 15, 180, 0, // Skip to: 8540 /* 8360 */ MCD_OPC_CheckField, 8, 4, 0, 174, 0, // Skip to: 8540 /* 8366 */ MCD_OPC_Decode, 130, 14, 162, 1, // Opcode: ORK /* 8371 */ MCD_OPC_FilterValue, 247, 1, 15, 0, // Skip to: 8391 /* 8376 */ MCD_OPC_CheckPredicate, 15, 160, 0, // Skip to: 8540 /* 8380 */ MCD_OPC_CheckField, 8, 4, 0, 154, 0, // Skip to: 8540 /* 8386 */ MCD_OPC_Decode, 236, 21, 162, 1, // Opcode: XRK /* 8391 */ MCD_OPC_FilterValue, 248, 1, 15, 0, // Skip to: 8411 /* 8396 */ MCD_OPC_CheckPredicate, 15, 140, 0, // Skip to: 8540 /* 8400 */ MCD_OPC_CheckField, 8, 4, 0, 134, 0, // Skip to: 8540 /* 8406 */ MCD_OPC_Decode, 154, 3, 162, 1, // Opcode: ARK /* 8411 */ MCD_OPC_FilterValue, 249, 1, 15, 0, // Skip to: 8431 /* 8416 */ MCD_OPC_CheckPredicate, 15, 120, 0, // Skip to: 8540 /* 8420 */ MCD_OPC_CheckField, 8, 4, 0, 114, 0, // Skip to: 8540 /* 8426 */ MCD_OPC_Decode, 137, 15, 162, 1, // Opcode: SRK /* 8431 */ MCD_OPC_FilterValue, 250, 1, 15, 0, // Skip to: 8451 /* 8436 */ MCD_OPC_CheckPredicate, 15, 100, 0, // Skip to: 8540 /* 8440 */ MCD_OPC_CheckField, 8, 4, 0, 94, 0, // Skip to: 8540 /* 8446 */ MCD_OPC_Decode, 147, 3, 162, 1, // Opcode: ALRK /* 8451 */ MCD_OPC_FilterValue, 251, 1, 15, 0, // Skip to: 8471 /* 8456 */ MCD_OPC_CheckPredicate, 15, 80, 0, // Skip to: 8540 /* 8460 */ MCD_OPC_CheckField, 8, 4, 0, 74, 0, // Skip to: 8540 /* 8466 */ MCD_OPC_Decode, 239, 14, 162, 1, // Opcode: SLRK /* 8471 */ MCD_OPC_FilterValue, 253, 1, 64, 0, // Skip to: 8540 /* 8476 */ MCD_OPC_CheckPredicate, 16, 60, 0, // Skip to: 8540 /* 8480 */ MCD_OPC_CheckField, 8, 4, 0, 54, 0, // Skip to: 8540 /* 8486 */ MCD_OPC_Decode, 188, 13, 162, 1, // Opcode: MSRKC /* 8491 */ MCD_OPC_FilterValue, 186, 1, 4, 0, // Skip to: 8500 /* 8496 */ MCD_OPC_Decode, 132, 8, 35, // Opcode: CS /* 8500 */ MCD_OPC_FilterValue, 187, 1, 5, 0, // Skip to: 8510 /* 8505 */ MCD_OPC_Decode, 157, 4, 163, 1, // Opcode: CDS /* 8510 */ MCD_OPC_FilterValue, 189, 1, 5, 0, // Skip to: 8520 /* 8515 */ MCD_OPC_Decode, 142, 7, 164, 1, // Opcode: CLM /* 8520 */ MCD_OPC_FilterValue, 190, 1, 5, 0, // Skip to: 8530 /* 8525 */ MCD_OPC_Decode, 164, 15, 164, 1, // Opcode: STCM /* 8530 */ MCD_OPC_FilterValue, 191, 1, 5, 0, // Skip to: 8540 /* 8535 */ MCD_OPC_Decode, 131, 9, 165, 1, // Opcode: ICM /* 8540 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTable48[] = { /* 0 */ MCD_OPC_ExtractField, 40, 8, // Inst{47-40} ... /* 3 */ MCD_OPC_FilterValue, 192, 1, 11, 1, // Skip to: 275 /* 8 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 11 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 20 /* 15 */ MCD_OPC_Decode, 250, 9, 166, 1, // Opcode: LARL /* 20 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29 /* 24 */ MCD_OPC_Decode, 181, 10, 167, 1, // Opcode: LGFI /* 29 */ MCD_OPC_FilterValue, 4, 143, 0, // Skip to: 176 /* 33 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... /* 36 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 45 /* 40 */ MCD_OPC_Decode, 217, 9, 168, 1, // Opcode: JGAsmO /* 45 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 54 /* 49 */ MCD_OPC_Decode, 201, 9, 168, 1, // Opcode: JGAsmH /* 54 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 63 /* 58 */ MCD_OPC_Decode, 211, 9, 168, 1, // Opcode: JGAsmNLE /* 63 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 72 /* 67 */ MCD_OPC_Decode, 203, 9, 168, 1, // Opcode: JGAsmL /* 72 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 81 /* 76 */ MCD_OPC_Decode, 209, 9, 168, 1, // Opcode: JGAsmNHE /* 81 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 90 /* 85 */ MCD_OPC_Decode, 205, 9, 168, 1, // Opcode: JGAsmLH /* 90 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 99 /* 94 */ MCD_OPC_Decode, 207, 9, 168, 1, // Opcode: JGAsmNE /* 99 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 108 /* 103 */ MCD_OPC_Decode, 200, 9, 168, 1, // Opcode: JGAsmE /* 108 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 117 /* 112 */ MCD_OPC_Decode, 212, 9, 168, 1, // Opcode: JGAsmNLH /* 117 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 126 /* 121 */ MCD_OPC_Decode, 202, 9, 168, 1, // Opcode: JGAsmHE /* 126 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 135 /* 130 */ MCD_OPC_Decode, 210, 9, 168, 1, // Opcode: JGAsmNL /* 135 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 144 /* 139 */ MCD_OPC_Decode, 204, 9, 168, 1, // Opcode: JGAsmLE /* 144 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 153 /* 148 */ MCD_OPC_Decode, 208, 9, 168, 1, // Opcode: JGAsmNH /* 153 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 162 /* 157 */ MCD_OPC_Decode, 214, 9, 168, 1, // Opcode: JGAsmNO /* 162 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 171 /* 166 */ MCD_OPC_Decode, 199, 9, 168, 1, // Opcode: JG /* 171 */ MCD_OPC_Decode, 251, 3, 169, 1, // Opcode: BRCLAsm /* 176 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 185 /* 180 */ MCD_OPC_Decode, 227, 3, 170, 1, // Opcode: BRASL /* 185 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 194 /* 189 */ MCD_OPC_Decode, 232, 21, 171, 1, // Opcode: XIHF /* 194 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 203 /* 198 */ MCD_OPC_Decode, 233, 21, 172, 1, // Opcode: XILF /* 203 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 212 /* 207 */ MCD_OPC_Decode, 139, 9, 173, 1, // Opcode: IIHF /* 212 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 221 /* 216 */ MCD_OPC_Decode, 142, 9, 174, 1, // Opcode: IILF /* 221 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 230 /* 225 */ MCD_OPC_Decode, 233, 13, 171, 1, // Opcode: NIHF /* 230 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 239 /* 234 */ MCD_OPC_Decode, 236, 13, 172, 1, // Opcode: NILF /* 239 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 248 /* 243 */ MCD_OPC_Decode, 250, 13, 171, 1, // Opcode: OIHF /* 248 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 257 /* 252 */ MCD_OPC_Decode, 253, 13, 172, 1, // Opcode: OILF /* 257 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 266 /* 261 */ MCD_OPC_Decode, 218, 10, 175, 1, // Opcode: LLIHF /* 266 */ MCD_OPC_FilterValue, 15, 133, 73, // Skip to: 19091 /* 270 */ MCD_OPC_Decode, 221, 10, 175, 1, // Opcode: LLILF /* 275 */ MCD_OPC_FilterValue, 194, 1, 111, 0, // Skip to: 391 /* 280 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 283 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 292 /* 287 */ MCD_OPC_Decode, 183, 13, 176, 1, // Opcode: MSGFI /* 292 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 301 /* 296 */ MCD_OPC_Decode, 179, 13, 177, 1, // Opcode: MSFI /* 301 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 310 /* 305 */ MCD_OPC_Decode, 229, 14, 178, 1, // Opcode: SLGFI /* 310 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 319 /* 314 */ MCD_OPC_Decode, 226, 14, 172, 1, // Opcode: SLFI /* 319 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 328 /* 323 */ MCD_OPC_Decode, 242, 2, 176, 1, // Opcode: AGFI /* 328 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 337 /* 332 */ MCD_OPC_Decode, 239, 2, 177, 1, // Opcode: AFI /* 337 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 346 /* 341 */ MCD_OPC_Decode, 137, 3, 178, 1, // Opcode: ALGFI /* 346 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 355 /* 350 */ MCD_OPC_Decode, 134, 3, 172, 1, // Opcode: ALFI /* 355 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 364 /* 359 */ MCD_OPC_Decode, 201, 4, 167, 1, // Opcode: CGFI /* 364 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 373 /* 368 */ MCD_OPC_Decode, 186, 4, 179, 1, // Opcode: CFI /* 373 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 382 /* 377 */ MCD_OPC_Decode, 255, 5, 175, 1, // Opcode: CLGFI /* 382 */ MCD_OPC_FilterValue, 15, 17, 73, // Skip to: 19091 /* 386 */ MCD_OPC_Decode, 233, 5, 174, 1, // Opcode: CLFI /* 391 */ MCD_OPC_FilterValue, 196, 1, 102, 0, // Skip to: 498 /* 396 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 399 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 408 /* 403 */ MCD_OPC_Decode, 217, 10, 180, 1, // Opcode: LLHRL /* 408 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 417 /* 412 */ MCD_OPC_Decode, 188, 10, 166, 1, // Opcode: LGHRL /* 417 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 426 /* 421 */ MCD_OPC_Decode, 196, 10, 180, 1, // Opcode: LHRL /* 426 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 435 /* 430 */ MCD_OPC_Decode, 210, 10, 166, 1, // Opcode: LLGHRL /* 435 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 444 /* 439 */ MCD_OPC_Decode, 185, 15, 180, 1, // Opcode: STHRL /* 444 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 453 /* 448 */ MCD_OPC_Decode, 190, 10, 166, 1, // Opcode: LGRL /* 453 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 462 /* 457 */ MCD_OPC_Decode, 181, 15, 166, 1, // Opcode: STGRL /* 462 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 471 /* 466 */ MCD_OPC_Decode, 183, 10, 166, 1, // Opcode: LGFRL /* 471 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 480 /* 475 */ MCD_OPC_Decode, 208, 12, 180, 1, // Opcode: LRL /* 480 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 489 /* 484 */ MCD_OPC_Decode, 206, 10, 166, 1, // Opcode: LLGFRL /* 489 */ MCD_OPC_FilterValue, 15, 166, 72, // Skip to: 19091 /* 493 */ MCD_OPC_Decode, 136, 16, 180, 1, // Opcode: STRL /* 498 */ MCD_OPC_FilterValue, 197, 1, 9, 0, // Skip to: 512 /* 503 */ MCD_OPC_CheckPredicate, 3, 152, 72, // Skip to: 19091 /* 507 */ MCD_OPC_Decode, 224, 3, 181, 1, // Opcode: BPRP /* 512 */ MCD_OPC_FilterValue, 198, 1, 111, 0, // Skip to: 628 /* 517 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 520 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 529 /* 524 */ MCD_OPC_Decode, 239, 8, 166, 1, // Opcode: EXRL /* 529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 538 /* 533 */ MCD_OPC_Decode, 138, 14, 182, 1, // Opcode: PFDRL /* 538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 547 /* 542 */ MCD_OPC_Decode, 206, 4, 166, 1, // Opcode: CGHRL /* 547 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 556 /* 551 */ MCD_OPC_Decode, 177, 5, 180, 1, // Opcode: CHRL /* 556 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 565 /* 560 */ MCD_OPC_Decode, 130, 6, 166, 1, // Opcode: CLGHRL /* 565 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 574 /* 569 */ MCD_OPC_Decode, 238, 6, 180, 1, // Opcode: CLHRL /* 574 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 583 /* 578 */ MCD_OPC_Decode, 151, 5, 166, 1, // Opcode: CGRL /* 583 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 592 /* 587 */ MCD_OPC_Decode, 203, 6, 166, 1, // Opcode: CLGRL /* 592 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 601 /* 596 */ MCD_OPC_Decode, 203, 4, 166, 1, // Opcode: CGFRL /* 601 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 610 /* 605 */ MCD_OPC_Decode, 245, 7, 180, 1, // Opcode: CRL /* 610 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 619 /* 614 */ MCD_OPC_Decode, 129, 6, 166, 1, // Opcode: CLGFRL /* 619 */ MCD_OPC_FilterValue, 15, 36, 72, // Skip to: 19091 /* 623 */ MCD_OPC_Decode, 174, 7, 180, 1, // Opcode: CLRL /* 628 */ MCD_OPC_FilterValue, 199, 1, 15, 0, // Skip to: 648 /* 633 */ MCD_OPC_CheckPredicate, 3, 22, 72, // Skip to: 19091 /* 637 */ MCD_OPC_CheckField, 32, 4, 0, 16, 72, // Skip to: 19091 /* 643 */ MCD_OPC_Decode, 223, 3, 183, 1, // Opcode: BPP /* 648 */ MCD_OPC_FilterValue, 200, 1, 56, 0, // Skip to: 709 /* 653 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 656 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 665 /* 660 */ MCD_OPC_Decode, 198, 13, 184, 1, // Opcode: MVCOS /* 665 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 674 /* 669 */ MCD_OPC_Decode, 219, 8, 184, 1, // Opcode: ECTG /* 674 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 683 /* 678 */ MCD_OPC_Decode, 138, 8, 184, 1, // Opcode: CSST /* 683 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 696 /* 687 */ MCD_OPC_CheckPredicate, 17, 224, 71, // Skip to: 19091 /* 691 */ MCD_OPC_Decode, 184, 12, 185, 1, // Opcode: LPD /* 696 */ MCD_OPC_FilterValue, 5, 215, 71, // Skip to: 19091 /* 700 */ MCD_OPC_CheckPredicate, 17, 211, 71, // Skip to: 19091 /* 704 */ MCD_OPC_Decode, 188, 12, 185, 1, // Opcode: LPDG /* 709 */ MCD_OPC_FilterValue, 204, 1, 81, 0, // Skip to: 795 /* 714 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 717 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 730 /* 721 */ MCD_OPC_CheckPredicate, 11, 190, 71, // Skip to: 19091 /* 725 */ MCD_OPC_Decode, 254, 3, 186, 1, // Opcode: BRCTH /* 730 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 743 /* 734 */ MCD_OPC_CheckPredicate, 11, 177, 71, // Skip to: 19091 /* 738 */ MCD_OPC_Decode, 128, 3, 187, 1, // Opcode: AIH /* 743 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 756 /* 747 */ MCD_OPC_CheckPredicate, 11, 164, 71, // Skip to: 19091 /* 751 */ MCD_OPC_Decode, 149, 3, 187, 1, // Opcode: ALSIH /* 756 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 769 /* 760 */ MCD_OPC_CheckPredicate, 11, 151, 71, // Skip to: 19091 /* 764 */ MCD_OPC_Decode, 150, 3, 187, 1, // Opcode: ALSIHN /* 769 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 782 /* 773 */ MCD_OPC_CheckPredicate, 11, 138, 71, // Skip to: 19091 /* 777 */ MCD_OPC_Decode, 194, 5, 188, 1, // Opcode: CIH /* 782 */ MCD_OPC_FilterValue, 15, 129, 71, // Skip to: 19091 /* 786 */ MCD_OPC_CheckPredicate, 11, 125, 71, // Skip to: 19091 /* 790 */ MCD_OPC_Decode, 254, 6, 173, 1, // Opcode: CLIH /* 795 */ MCD_OPC_FilterValue, 208, 1, 5, 0, // Skip to: 805 /* 800 */ MCD_OPC_Decode, 199, 16, 189, 1, // Opcode: TRTR /* 805 */ MCD_OPC_FilterValue, 209, 1, 5, 0, // Skip to: 815 /* 810 */ MCD_OPC_Decode, 207, 13, 189, 1, // Opcode: MVN /* 815 */ MCD_OPC_FilterValue, 210, 1, 5, 0, // Skip to: 825 /* 820 */ MCD_OPC_Decode, 191, 13, 189, 1, // Opcode: MVC /* 825 */ MCD_OPC_FilterValue, 211, 1, 5, 0, // Skip to: 835 /* 830 */ MCD_OPC_Decode, 211, 13, 189, 1, // Opcode: MVZ /* 835 */ MCD_OPC_FilterValue, 212, 1, 5, 0, // Skip to: 845 /* 840 */ MCD_OPC_Decode, 227, 13, 189, 1, // Opcode: NC /* 845 */ MCD_OPC_FilterValue, 213, 1, 5, 0, // Skip to: 855 /* 850 */ MCD_OPC_Decode, 225, 5, 189, 1, // Opcode: CLC /* 855 */ MCD_OPC_FilterValue, 214, 1, 5, 0, // Skip to: 865 /* 860 */ MCD_OPC_Decode, 245, 13, 189, 1, // Opcode: OC /* 865 */ MCD_OPC_FilterValue, 215, 1, 5, 0, // Skip to: 875 /* 870 */ MCD_OPC_Decode, 227, 21, 189, 1, // Opcode: XC /* 875 */ MCD_OPC_FilterValue, 217, 1, 5, 0, // Skip to: 885 /* 880 */ MCD_OPC_Decode, 194, 13, 190, 1, // Opcode: MVCK /* 885 */ MCD_OPC_FilterValue, 218, 1, 5, 0, // Skip to: 895 /* 890 */ MCD_OPC_Decode, 199, 13, 190, 1, // Opcode: MVCP /* 895 */ MCD_OPC_FilterValue, 219, 1, 5, 0, // Skip to: 905 /* 900 */ MCD_OPC_Decode, 200, 13, 190, 1, // Opcode: MVCS /* 905 */ MCD_OPC_FilterValue, 220, 1, 5, 0, // Skip to: 915 /* 910 */ MCD_OPC_Decode, 184, 16, 189, 1, // Opcode: TR /* 915 */ MCD_OPC_FilterValue, 221, 1, 5, 0, // Skip to: 925 /* 920 */ MCD_OPC_Decode, 194, 16, 189, 1, // Opcode: TRT /* 925 */ MCD_OPC_FilterValue, 222, 1, 5, 0, // Skip to: 935 /* 930 */ MCD_OPC_Decode, 220, 8, 189, 1, // Opcode: ED /* 935 */ MCD_OPC_FilterValue, 223, 1, 5, 0, // Skip to: 945 /* 940 */ MCD_OPC_Decode, 221, 8, 189, 1, // Opcode: EDMK /* 945 */ MCD_OPC_FilterValue, 225, 1, 5, 0, // Skip to: 955 /* 950 */ MCD_OPC_Decode, 144, 14, 191, 1, // Opcode: PKU /* 955 */ MCD_OPC_FilterValue, 226, 1, 5, 0, // Skip to: 965 /* 960 */ MCD_OPC_Decode, 208, 16, 189, 1, // Opcode: UNPKU /* 965 */ MCD_OPC_FilterValue, 227, 1, 83, 5, // Skip to: 2333 /* 970 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 973 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 982 /* 977 */ MCD_OPC_Decode, 223, 12, 192, 1, // Opcode: LTG /* 982 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 991 /* 986 */ MCD_OPC_Decode, 204, 12, 192, 1, // Opcode: LRAG /* 991 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 1000 /* 995 */ MCD_OPC_Decode, 175, 10, 192, 1, // Opcode: LG /* 1000 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 1009 /* 1004 */ MCD_OPC_Decode, 160, 8, 193, 1, // Opcode: CVBY /* 1009 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 1018 /* 1013 */ MCD_OPC_Decode, 240, 2, 194, 1, // Opcode: AG /* 1018 */ MCD_OPC_FilterValue, 9, 5, 0, // Skip to: 1027 /* 1022 */ MCD_OPC_Decode, 202, 14, 194, 1, // Opcode: SG /* 1027 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 1036 /* 1031 */ MCD_OPC_Decode, 135, 3, 194, 1, // Opcode: ALG /* 1036 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 1045 /* 1040 */ MCD_OPC_Decode, 227, 14, 194, 1, // Opcode: SLG /* 1045 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 1054 /* 1049 */ MCD_OPC_Decode, 180, 13, 194, 1, // Opcode: MSG /* 1054 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 1063 /* 1058 */ MCD_OPC_Decode, 207, 8, 195, 1, // Opcode: DSG /* 1063 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 1072 /* 1067 */ MCD_OPC_Decode, 159, 8, 194, 1, // Opcode: CVBG /* 1072 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 1081 /* 1076 */ MCD_OPC_Decode, 210, 12, 192, 1, // Opcode: LRVG /* 1081 */ MCD_OPC_FilterValue, 18, 5, 0, // Skip to: 1090 /* 1085 */ MCD_OPC_Decode, 215, 12, 196, 1, // Opcode: LT /* 1090 */ MCD_OPC_FilterValue, 19, 5, 0, // Skip to: 1099 /* 1094 */ MCD_OPC_Decode, 205, 12, 192, 1, // Opcode: LRAY /* 1099 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 1108 /* 1103 */ MCD_OPC_Decode, 180, 10, 192, 1, // Opcode: LGF /* 1108 */ MCD_OPC_FilterValue, 21, 5, 0, // Skip to: 1117 /* 1112 */ MCD_OPC_Decode, 185, 10, 192, 1, // Opcode: LGH /* 1117 */ MCD_OPC_FilterValue, 22, 5, 0, // Skip to: 1126 /* 1121 */ MCD_OPC_Decode, 203, 10, 192, 1, // Opcode: LLGF /* 1126 */ MCD_OPC_FilterValue, 23, 5, 0, // Skip to: 1135 /* 1130 */ MCD_OPC_Decode, 211, 10, 192, 1, // Opcode: LLGT /* 1135 */ MCD_OPC_FilterValue, 24, 5, 0, // Skip to: 1144 /* 1139 */ MCD_OPC_Decode, 241, 2, 194, 1, // Opcode: AGF /* 1144 */ MCD_OPC_FilterValue, 25, 5, 0, // Skip to: 1153 /* 1148 */ MCD_OPC_Decode, 203, 14, 194, 1, // Opcode: SGF /* 1153 */ MCD_OPC_FilterValue, 26, 5, 0, // Skip to: 1162 /* 1157 */ MCD_OPC_Decode, 136, 3, 194, 1, // Opcode: ALGF /* 1162 */ MCD_OPC_FilterValue, 27, 5, 0, // Skip to: 1171 /* 1166 */ MCD_OPC_Decode, 228, 14, 194, 1, // Opcode: SLGF /* 1171 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 1180 /* 1175 */ MCD_OPC_Decode, 182, 13, 194, 1, // Opcode: MSGF /* 1180 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 1189 /* 1184 */ MCD_OPC_Decode, 208, 8, 195, 1, // Opcode: DSGF /* 1189 */ MCD_OPC_FilterValue, 30, 5, 0, // Skip to: 1198 /* 1193 */ MCD_OPC_Decode, 209, 12, 196, 1, // Opcode: LRV /* 1198 */ MCD_OPC_FilterValue, 31, 5, 0, // Skip to: 1207 /* 1202 */ MCD_OPC_Decode, 212, 12, 196, 1, // Opcode: LRVH /* 1207 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 1216 /* 1211 */ MCD_OPC_Decode, 191, 4, 192, 1, // Opcode: CG /* 1216 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 1225 /* 1220 */ MCD_OPC_Decode, 250, 5, 192, 1, // Opcode: CLG /* 1225 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 1234 /* 1229 */ MCD_OPC_Decode, 180, 15, 192, 1, // Opcode: STG /* 1234 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 1247 /* 1238 */ MCD_OPC_CheckPredicate, 2, 185, 69, // Skip to: 19091 /* 1242 */ MCD_OPC_Decode, 242, 13, 192, 1, // Opcode: NTSTG /* 1247 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 1256 /* 1251 */ MCD_OPC_Decode, 163, 8, 196, 1, // Opcode: CVDY /* 1256 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 1269 /* 1260 */ MCD_OPC_CheckPredicate, 18, 163, 69, // Skip to: 19091 /* 1264 */ MCD_OPC_Decode, 248, 12, 192, 1, // Opcode: LZRG /* 1269 */ MCD_OPC_FilterValue, 46, 5, 0, // Skip to: 1278 /* 1273 */ MCD_OPC_Decode, 162, 8, 192, 1, // Opcode: CVDG /* 1278 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 1287 /* 1282 */ MCD_OPC_Decode, 138, 16, 192, 1, // Opcode: STRVG /* 1287 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 1296 /* 1291 */ MCD_OPC_Decode, 200, 4, 192, 1, // Opcode: CGF /* 1296 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 1305 /* 1300 */ MCD_OPC_Decode, 254, 5, 192, 1, // Opcode: CLGF /* 1305 */ MCD_OPC_FilterValue, 50, 5, 0, // Skip to: 1314 /* 1309 */ MCD_OPC_Decode, 224, 12, 192, 1, // Opcode: LTGF /* 1314 */ MCD_OPC_FilterValue, 52, 5, 0, // Skip to: 1323 /* 1318 */ MCD_OPC_Decode, 204, 4, 192, 1, // Opcode: CGH /* 1323 */ MCD_OPC_FilterValue, 54, 5, 0, // Skip to: 1332 /* 1327 */ MCD_OPC_Decode, 137, 14, 197, 1, // Opcode: PFD /* 1332 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 1345 /* 1336 */ MCD_OPC_CheckPredicate, 16, 87, 69, // Skip to: 19091 /* 1340 */ MCD_OPC_Decode, 244, 2, 194, 1, // Opcode: AGH /* 1345 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 1358 /* 1349 */ MCD_OPC_CheckPredicate, 16, 74, 69, // Skip to: 19091 /* 1353 */ MCD_OPC_Decode, 205, 14, 194, 1, // Opcode: SGH /* 1358 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1371 /* 1362 */ MCD_OPC_CheckPredicate, 18, 61, 69, // Skip to: 19091 /* 1366 */ MCD_OPC_Decode, 224, 10, 192, 1, // Opcode: LLZRGF /* 1371 */ MCD_OPC_FilterValue, 59, 9, 0, // Skip to: 1384 /* 1375 */ MCD_OPC_CheckPredicate, 18, 48, 69, // Skip to: 19091 /* 1379 */ MCD_OPC_Decode, 247, 12, 196, 1, // Opcode: LZRF /* 1384 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 1397 /* 1388 */ MCD_OPC_CheckPredicate, 16, 35, 69, // Skip to: 19091 /* 1392 */ MCD_OPC_Decode, 156, 13, 194, 1, // Opcode: MGH /* 1397 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 1406 /* 1401 */ MCD_OPC_Decode, 137, 16, 196, 1, // Opcode: STRV /* 1406 */ MCD_OPC_FilterValue, 63, 5, 0, // Skip to: 1415 /* 1410 */ MCD_OPC_Decode, 139, 16, 196, 1, // Opcode: STRVH /* 1415 */ MCD_OPC_FilterValue, 70, 5, 0, // Skip to: 1424 /* 1419 */ MCD_OPC_Decode, 197, 3, 194, 1, // Opcode: BCTG /* 1424 */ MCD_OPC_FilterValue, 71, 207, 0, // Skip to: 1635 /* 1428 */ MCD_OPC_ExtractField, 36, 4, // Inst{39-36} ... /* 1431 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1444 /* 1435 */ MCD_OPC_CheckPredicate, 16, 187, 0, // Skip to: 1626 /* 1439 */ MCD_OPC_Decode, 218, 3, 198, 1, // Opcode: BIAsmO /* 1444 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1457 /* 1448 */ MCD_OPC_CheckPredicate, 16, 174, 0, // Skip to: 1626 /* 1452 */ MCD_OPC_Decode, 202, 3, 198, 1, // Opcode: BIAsmH /* 1457 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1470 /* 1461 */ MCD_OPC_CheckPredicate, 16, 161, 0, // Skip to: 1626 /* 1465 */ MCD_OPC_Decode, 212, 3, 198, 1, // Opcode: BIAsmNLE /* 1470 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1483 /* 1474 */ MCD_OPC_CheckPredicate, 16, 148, 0, // Skip to: 1626 /* 1478 */ MCD_OPC_Decode, 204, 3, 198, 1, // Opcode: BIAsmL /* 1483 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1496 /* 1487 */ MCD_OPC_CheckPredicate, 16, 135, 0, // Skip to: 1626 /* 1491 */ MCD_OPC_Decode, 210, 3, 198, 1, // Opcode: BIAsmNHE /* 1496 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1509 /* 1500 */ MCD_OPC_CheckPredicate, 16, 122, 0, // Skip to: 1626 /* 1504 */ MCD_OPC_Decode, 206, 3, 198, 1, // Opcode: BIAsmLH /* 1509 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1522 /* 1513 */ MCD_OPC_CheckPredicate, 16, 109, 0, // Skip to: 1626 /* 1517 */ MCD_OPC_Decode, 208, 3, 198, 1, // Opcode: BIAsmNE /* 1522 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1535 /* 1526 */ MCD_OPC_CheckPredicate, 16, 96, 0, // Skip to: 1626 /* 1530 */ MCD_OPC_Decode, 201, 3, 198, 1, // Opcode: BIAsmE /* 1535 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1548 /* 1539 */ MCD_OPC_CheckPredicate, 16, 83, 0, // Skip to: 1626 /* 1543 */ MCD_OPC_Decode, 213, 3, 198, 1, // Opcode: BIAsmNLH /* 1548 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1561 /* 1552 */ MCD_OPC_CheckPredicate, 16, 70, 0, // Skip to: 1626 /* 1556 */ MCD_OPC_Decode, 203, 3, 198, 1, // Opcode: BIAsmHE /* 1561 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1574 /* 1565 */ MCD_OPC_CheckPredicate, 16, 57, 0, // Skip to: 1626 /* 1569 */ MCD_OPC_Decode, 211, 3, 198, 1, // Opcode: BIAsmNL /* 1574 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1587 /* 1578 */ MCD_OPC_CheckPredicate, 16, 44, 0, // Skip to: 1626 /* 1582 */ MCD_OPC_Decode, 205, 3, 198, 1, // Opcode: BIAsmLE /* 1587 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1600 /* 1591 */ MCD_OPC_CheckPredicate, 16, 31, 0, // Skip to: 1626 /* 1595 */ MCD_OPC_Decode, 209, 3, 198, 1, // Opcode: BIAsmNH /* 1600 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1613 /* 1604 */ MCD_OPC_CheckPredicate, 16, 18, 0, // Skip to: 1626 /* 1608 */ MCD_OPC_Decode, 215, 3, 198, 1, // Opcode: BIAsmNO /* 1613 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1626 /* 1617 */ MCD_OPC_CheckPredicate, 16, 5, 0, // Skip to: 1626 /* 1621 */ MCD_OPC_Decode, 200, 3, 198, 1, // Opcode: BI /* 1626 */ MCD_OPC_CheckPredicate, 16, 53, 68, // Skip to: 19091 /* 1630 */ MCD_OPC_Decode, 222, 3, 197, 1, // Opcode: BICAsm /* 1635 */ MCD_OPC_FilterValue, 72, 9, 0, // Skip to: 1648 /* 1639 */ MCD_OPC_CheckPredicate, 19, 40, 68, // Skip to: 19091 /* 1643 */ MCD_OPC_Decode, 207, 10, 192, 1, // Opcode: LLGFSG /* 1648 */ MCD_OPC_FilterValue, 73, 9, 0, // Skip to: 1661 /* 1652 */ MCD_OPC_CheckPredicate, 19, 27, 68, // Skip to: 19091 /* 1656 */ MCD_OPC_Decode, 182, 15, 192, 1, // Opcode: STGSC /* 1661 */ MCD_OPC_FilterValue, 76, 9, 0, // Skip to: 1674 /* 1665 */ MCD_OPC_CheckPredicate, 19, 14, 68, // Skip to: 19091 /* 1669 */ MCD_OPC_Decode, 184, 10, 192, 1, // Opcode: LGG /* 1674 */ MCD_OPC_FilterValue, 77, 9, 0, // Skip to: 1687 /* 1678 */ MCD_OPC_CheckPredicate, 19, 1, 68, // Skip to: 19091 /* 1682 */ MCD_OPC_Decode, 191, 10, 192, 1, // Opcode: LGSC /* 1687 */ MCD_OPC_FilterValue, 80, 5, 0, // Skip to: 1696 /* 1691 */ MCD_OPC_Decode, 144, 16, 196, 1, // Opcode: STY /* 1696 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 1705 /* 1700 */ MCD_OPC_Decode, 190, 13, 193, 1, // Opcode: MSY /* 1705 */ MCD_OPC_FilterValue, 83, 9, 0, // Skip to: 1718 /* 1709 */ MCD_OPC_CheckPredicate, 16, 226, 67, // Skip to: 19091 /* 1713 */ MCD_OPC_Decode, 169, 13, 193, 1, // Opcode: MSC /* 1718 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 1727 /* 1722 */ MCD_OPC_Decode, 243, 13, 193, 1, // Opcode: NY /* 1727 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 1736 /* 1731 */ MCD_OPC_Decode, 204, 7, 196, 1, // Opcode: CLY /* 1736 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 1745 /* 1740 */ MCD_OPC_Decode, 131, 14, 193, 1, // Opcode: OY /* 1745 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 1754 /* 1749 */ MCD_OPC_Decode, 238, 21, 193, 1, // Opcode: XY /* 1754 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 1763 /* 1758 */ MCD_OPC_Decode, 244, 12, 196, 1, // Opcode: LY /* 1763 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 1772 /* 1767 */ MCD_OPC_Decode, 184, 8, 196, 1, // Opcode: CY /* 1772 */ MCD_OPC_FilterValue, 90, 5, 0, // Skip to: 1781 /* 1776 */ MCD_OPC_Decode, 164, 3, 193, 1, // Opcode: AY /* 1781 */ MCD_OPC_FilterValue, 91, 5, 0, // Skip to: 1790 /* 1785 */ MCD_OPC_Decode, 154, 16, 193, 1, // Opcode: SY /* 1790 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 1799 /* 1794 */ MCD_OPC_Decode, 154, 13, 195, 1, // Opcode: MFY /* 1799 */ MCD_OPC_FilterValue, 94, 5, 0, // Skip to: 1808 /* 1803 */ MCD_OPC_Decode, 151, 3, 193, 1, // Opcode: ALY /* 1808 */ MCD_OPC_FilterValue, 95, 5, 0, // Skip to: 1817 /* 1812 */ MCD_OPC_Decode, 241, 14, 193, 1, // Opcode: SLY /* 1817 */ MCD_OPC_FilterValue, 112, 5, 0, // Skip to: 1826 /* 1821 */ MCD_OPC_Decode, 186, 15, 196, 1, // Opcode: STHY /* 1826 */ MCD_OPC_FilterValue, 113, 5, 0, // Skip to: 1835 /* 1830 */ MCD_OPC_Decode, 255, 9, 192, 1, // Opcode: LAY /* 1835 */ MCD_OPC_FilterValue, 114, 5, 0, // Skip to: 1844 /* 1839 */ MCD_OPC_Decode, 171, 15, 196, 1, // Opcode: STCY /* 1844 */ MCD_OPC_FilterValue, 115, 5, 0, // Skip to: 1853 /* 1848 */ MCD_OPC_Decode, 134, 9, 194, 1, // Opcode: ICY /* 1853 */ MCD_OPC_FilterValue, 117, 5, 0, // Skip to: 1862 /* 1857 */ MCD_OPC_Decode, 243, 9, 192, 1, // Opcode: LAEY /* 1862 */ MCD_OPC_FilterValue, 118, 5, 0, // Skip to: 1871 /* 1866 */ MCD_OPC_Decode, 128, 10, 196, 1, // Opcode: LB /* 1871 */ MCD_OPC_FilterValue, 119, 5, 0, // Skip to: 1880 /* 1875 */ MCD_OPC_Decode, 177, 10, 192, 1, // Opcode: LGB /* 1880 */ MCD_OPC_FilterValue, 120, 5, 0, // Skip to: 1889 /* 1884 */ MCD_OPC_Decode, 197, 10, 196, 1, // Opcode: LHY /* 1889 */ MCD_OPC_FilterValue, 121, 5, 0, // Skip to: 1898 /* 1893 */ MCD_OPC_Decode, 179, 5, 196, 1, // Opcode: CHY /* 1898 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 1907 /* 1902 */ MCD_OPC_Decode, 255, 2, 193, 1, // Opcode: AHY /* 1907 */ MCD_OPC_FilterValue, 123, 5, 0, // Skip to: 1916 /* 1911 */ MCD_OPC_Decode, 211, 14, 193, 1, // Opcode: SHY /* 1916 */ MCD_OPC_FilterValue, 124, 5, 0, // Skip to: 1925 /* 1920 */ MCD_OPC_Decode, 161, 13, 193, 1, // Opcode: MHY /* 1925 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 1935 /* 1930 */ MCD_OPC_Decode, 228, 13, 194, 1, // Opcode: NG /* 1935 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 1945 /* 1940 */ MCD_OPC_Decode, 246, 13, 194, 1, // Opcode: OG /* 1945 */ MCD_OPC_FilterValue, 130, 1, 5, 0, // Skip to: 1955 /* 1950 */ MCD_OPC_Decode, 228, 21, 194, 1, // Opcode: XG /* 1955 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 1969 /* 1960 */ MCD_OPC_CheckPredicate, 16, 231, 66, // Skip to: 19091 /* 1964 */ MCD_OPC_Decode, 181, 13, 194, 1, // Opcode: MSGC /* 1969 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 1983 /* 1974 */ MCD_OPC_CheckPredicate, 16, 217, 66, // Skip to: 19091 /* 1978 */ MCD_OPC_Decode, 155, 13, 195, 1, // Opcode: MG /* 1983 */ MCD_OPC_FilterValue, 133, 1, 9, 0, // Skip to: 1997 /* 1988 */ MCD_OPC_CheckPredicate, 20, 203, 66, // Skip to: 19091 /* 1992 */ MCD_OPC_Decode, 176, 10, 192, 1, // Opcode: LGAT /* 1997 */ MCD_OPC_FilterValue, 134, 1, 5, 0, // Skip to: 2007 /* 2002 */ MCD_OPC_Decode, 163, 13, 195, 1, // Opcode: MLG /* 2007 */ MCD_OPC_FilterValue, 135, 1, 5, 0, // Skip to: 2017 /* 2012 */ MCD_OPC_Decode, 202, 8, 195, 1, // Opcode: DLG /* 2017 */ MCD_OPC_FilterValue, 136, 1, 5, 0, // Skip to: 2027 /* 2022 */ MCD_OPC_Decode, 131, 3, 194, 1, // Opcode: ALCG /* 2027 */ MCD_OPC_FilterValue, 137, 1, 5, 0, // Skip to: 2037 /* 2032 */ MCD_OPC_Decode, 220, 14, 194, 1, // Opcode: SLBG /* 2037 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 2047 /* 2042 */ MCD_OPC_Decode, 132, 16, 199, 1, // Opcode: STPQ /* 2047 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 2057 /* 2052 */ MCD_OPC_Decode, 195, 12, 199, 1, // Opcode: LPQ /* 2057 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 2067 /* 2062 */ MCD_OPC_Decode, 201, 10, 192, 1, // Opcode: LLGC /* 2067 */ MCD_OPC_FilterValue, 145, 1, 5, 0, // Skip to: 2077 /* 2072 */ MCD_OPC_Decode, 208, 10, 192, 1, // Opcode: LLGH /* 2077 */ MCD_OPC_FilterValue, 148, 1, 5, 0, // Skip to: 2087 /* 2082 */ MCD_OPC_Decode, 198, 10, 196, 1, // Opcode: LLC /* 2087 */ MCD_OPC_FilterValue, 149, 1, 5, 0, // Skip to: 2097 /* 2092 */ MCD_OPC_Decode, 214, 10, 196, 1, // Opcode: LLH /* 2097 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 2107 /* 2102 */ MCD_OPC_Decode, 162, 13, 195, 1, // Opcode: ML /* 2107 */ MCD_OPC_FilterValue, 151, 1, 5, 0, // Skip to: 2117 /* 2112 */ MCD_OPC_Decode, 201, 8, 195, 1, // Opcode: DL /* 2117 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 2127 /* 2122 */ MCD_OPC_Decode, 130, 3, 193, 1, // Opcode: ALC /* 2127 */ MCD_OPC_FilterValue, 153, 1, 5, 0, // Skip to: 2137 /* 2132 */ MCD_OPC_Decode, 219, 14, 193, 1, // Opcode: SLB /* 2137 */ MCD_OPC_FilterValue, 156, 1, 9, 0, // Skip to: 2151 /* 2142 */ MCD_OPC_CheckPredicate, 20, 49, 66, // Skip to: 19091 /* 2146 */ MCD_OPC_Decode, 212, 10, 192, 1, // Opcode: LLGTAT /* 2151 */ MCD_OPC_FilterValue, 157, 1, 9, 0, // Skip to: 2165 /* 2156 */ MCD_OPC_CheckPredicate, 20, 35, 66, // Skip to: 19091 /* 2160 */ MCD_OPC_Decode, 204, 10, 192, 1, // Opcode: LLGFAT /* 2165 */ MCD_OPC_FilterValue, 159, 1, 9, 0, // Skip to: 2179 /* 2170 */ MCD_OPC_CheckPredicate, 20, 21, 66, // Skip to: 19091 /* 2174 */ MCD_OPC_Decode, 252, 9, 196, 1, // Opcode: LAT /* 2179 */ MCD_OPC_FilterValue, 192, 1, 9, 0, // Skip to: 2193 /* 2184 */ MCD_OPC_CheckPredicate, 11, 7, 66, // Skip to: 19091 /* 2188 */ MCD_OPC_Decode, 129, 10, 200, 1, // Opcode: LBH /* 2193 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 2207 /* 2198 */ MCD_OPC_CheckPredicate, 11, 249, 65, // Skip to: 19091 /* 2202 */ MCD_OPC_Decode, 199, 10, 200, 1, // Opcode: LLCH /* 2207 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 2221 /* 2212 */ MCD_OPC_CheckPredicate, 11, 235, 65, // Skip to: 19091 /* 2216 */ MCD_OPC_Decode, 159, 15, 200, 1, // Opcode: STCH /* 2221 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 2235 /* 2226 */ MCD_OPC_CheckPredicate, 11, 221, 65, // Skip to: 19091 /* 2230 */ MCD_OPC_Decode, 193, 10, 200, 1, // Opcode: LHH /* 2235 */ MCD_OPC_FilterValue, 198, 1, 9, 0, // Skip to: 2249 /* 2240 */ MCD_OPC_CheckPredicate, 11, 207, 65, // Skip to: 19091 /* 2244 */ MCD_OPC_Decode, 215, 10, 200, 1, // Opcode: LLHH /* 2249 */ MCD_OPC_FilterValue, 199, 1, 9, 0, // Skip to: 2263 /* 2254 */ MCD_OPC_CheckPredicate, 11, 193, 65, // Skip to: 19091 /* 2258 */ MCD_OPC_Decode, 184, 15, 200, 1, // Opcode: STHH /* 2263 */ MCD_OPC_FilterValue, 200, 1, 9, 0, // Skip to: 2277 /* 2268 */ MCD_OPC_CheckPredicate, 20, 179, 65, // Skip to: 19091 /* 2272 */ MCD_OPC_Decode, 173, 10, 200, 1, // Opcode: LFHAT /* 2277 */ MCD_OPC_FilterValue, 202, 1, 9, 0, // Skip to: 2291 /* 2282 */ MCD_OPC_CheckPredicate, 11, 165, 65, // Skip to: 19091 /* 2286 */ MCD_OPC_Decode, 172, 10, 200, 1, // Opcode: LFH /* 2291 */ MCD_OPC_FilterValue, 203, 1, 9, 0, // Skip to: 2305 /* 2296 */ MCD_OPC_CheckPredicate, 11, 151, 65, // Skip to: 19091 /* 2300 */ MCD_OPC_Decode, 176, 15, 200, 1, // Opcode: STFH /* 2305 */ MCD_OPC_FilterValue, 205, 1, 9, 0, // Skip to: 2319 /* 2310 */ MCD_OPC_CheckPredicate, 11, 137, 65, // Skip to: 19091 /* 2314 */ MCD_OPC_Decode, 172, 5, 200, 1, // Opcode: CHF /* 2319 */ MCD_OPC_FilterValue, 207, 1, 127, 65, // Skip to: 19091 /* 2324 */ MCD_OPC_CheckPredicate, 11, 123, 65, // Skip to: 19091 /* 2328 */ MCD_OPC_Decode, 234, 6, 200, 1, // Opcode: CLHF /* 2333 */ MCD_OPC_FilterValue, 229, 1, 155, 0, // Skip to: 2493 /* 2338 */ MCD_OPC_ExtractField, 32, 8, // Inst{39-32} ... /* 2341 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 2350 /* 2345 */ MCD_OPC_Decode, 251, 9, 201, 1, // Opcode: LASP /* 2350 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 2359 /* 2354 */ MCD_OPC_Decode, 183, 16, 201, 1, // Opcode: TPROT /* 2359 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 2368 /* 2363 */ MCD_OPC_Decode, 135, 16, 201, 1, // Opcode: STRAG /* 2368 */ MCD_OPC_FilterValue, 14, 5, 0, // Skip to: 2377 /* 2372 */ MCD_OPC_Decode, 201, 13, 201, 1, // Opcode: MVCSK /* 2377 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 2386 /* 2381 */ MCD_OPC_Decode, 192, 13, 201, 1, // Opcode: MVCDK /* 2386 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 2395 /* 2390 */ MCD_OPC_Decode, 203, 13, 202, 1, // Opcode: MVHHI /* 2395 */ MCD_OPC_FilterValue, 72, 5, 0, // Skip to: 2404 /* 2399 */ MCD_OPC_Decode, 202, 13, 202, 1, // Opcode: MVGHI /* 2404 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 2413 /* 2408 */ MCD_OPC_Decode, 204, 13, 202, 1, // Opcode: MVHI /* 2413 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 2422 /* 2417 */ MCD_OPC_Decode, 174, 5, 202, 1, // Opcode: CHHSI /* 2422 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 2431 /* 2426 */ MCD_OPC_Decode, 236, 6, 203, 1, // Opcode: CLHHSI /* 2431 */ MCD_OPC_FilterValue, 88, 5, 0, // Skip to: 2440 /* 2435 */ MCD_OPC_Decode, 207, 4, 202, 1, // Opcode: CGHSI /* 2440 */ MCD_OPC_FilterValue, 89, 5, 0, // Skip to: 2449 /* 2444 */ MCD_OPC_Decode, 131, 6, 203, 1, // Opcode: CLGHSI /* 2449 */ MCD_OPC_FilterValue, 92, 5, 0, // Skip to: 2458 /* 2453 */ MCD_OPC_Decode, 178, 5, 202, 1, // Opcode: CHSI /* 2458 */ MCD_OPC_FilterValue, 93, 5, 0, // Skip to: 2467 /* 2462 */ MCD_OPC_Decode, 232, 5, 203, 1, // Opcode: CLFHSI /* 2467 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 2480 /* 2471 */ MCD_OPC_CheckPredicate, 2, 232, 64, // Skip to: 19091 /* 2475 */ MCD_OPC_Decode, 161, 16, 203, 1, // Opcode: TBEGIN /* 2480 */ MCD_OPC_FilterValue, 97, 223, 64, // Skip to: 19091 /* 2484 */ MCD_OPC_CheckPredicate, 2, 219, 64, // Skip to: 19091 /* 2488 */ MCD_OPC_Decode, 162, 16, 203, 1, // Opcode: TBEGINC /* 2493 */ MCD_OPC_FilterValue, 230, 1, 35, 2, // Skip to: 3045 /* 2498 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 2501 */ MCD_OPC_FilterValue, 52, 15, 0, // Skip to: 2520 /* 2505 */ MCD_OPC_CheckPredicate, 21, 198, 64, // Skip to: 19091 /* 2509 */ MCD_OPC_CheckField, 9, 3, 0, 192, 64, // Skip to: 19091 /* 2515 */ MCD_OPC_Decode, 146, 20, 204, 1, // Opcode: VPKZ /* 2520 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 2539 /* 2524 */ MCD_OPC_CheckPredicate, 21, 179, 64, // Skip to: 19091 /* 2528 */ MCD_OPC_CheckField, 9, 3, 0, 173, 64, // Skip to: 19091 /* 2534 */ MCD_OPC_Decode, 148, 19, 204, 1, // Opcode: VLRL /* 2539 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 2564 /* 2543 */ MCD_OPC_CheckPredicate, 21, 160, 64, // Skip to: 19091 /* 2547 */ MCD_OPC_CheckField, 36, 4, 0, 154, 64, // Skip to: 19091 /* 2553 */ MCD_OPC_CheckField, 9, 3, 0, 148, 64, // Skip to: 19091 /* 2559 */ MCD_OPC_Decode, 149, 19, 205, 1, // Opcode: VLRLR /* 2564 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 2583 /* 2568 */ MCD_OPC_CheckPredicate, 21, 135, 64, // Skip to: 19091 /* 2572 */ MCD_OPC_CheckField, 9, 3, 0, 129, 64, // Skip to: 19091 /* 2578 */ MCD_OPC_Decode, 234, 20, 204, 1, // Opcode: VUPKZ /* 2583 */ MCD_OPC_FilterValue, 61, 15, 0, // Skip to: 2602 /* 2587 */ MCD_OPC_CheckPredicate, 21, 116, 64, // Skip to: 19091 /* 2591 */ MCD_OPC_CheckField, 9, 3, 0, 110, 64, // Skip to: 19091 /* 2597 */ MCD_OPC_Decode, 217, 20, 204, 1, // Opcode: VSTRL /* 2602 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 2627 /* 2606 */ MCD_OPC_CheckPredicate, 21, 97, 64, // Skip to: 19091 /* 2610 */ MCD_OPC_CheckField, 36, 4, 0, 91, 64, // Skip to: 19091 /* 2616 */ MCD_OPC_CheckField, 9, 3, 0, 85, 64, // Skip to: 19091 /* 2622 */ MCD_OPC_Decode, 218, 20, 205, 1, // Opcode: VSTRLR /* 2627 */ MCD_OPC_FilterValue, 73, 21, 0, // Skip to: 2652 /* 2631 */ MCD_OPC_CheckPredicate, 21, 72, 64, // Skip to: 19091 /* 2635 */ MCD_OPC_CheckField, 32, 4, 0, 66, 64, // Skip to: 19091 /* 2641 */ MCD_OPC_CheckField, 8, 3, 0, 60, 64, // Skip to: 19091 /* 2647 */ MCD_OPC_Decode, 128, 19, 206, 1, // Opcode: VLIP /* 2652 */ MCD_OPC_FilterValue, 80, 27, 0, // Skip to: 2683 /* 2656 */ MCD_OPC_CheckPredicate, 21, 47, 64, // Skip to: 19091 /* 2660 */ MCD_OPC_CheckField, 24, 8, 0, 41, 64, // Skip to: 19091 /* 2666 */ MCD_OPC_CheckField, 11, 9, 0, 35, 64, // Skip to: 19091 /* 2672 */ MCD_OPC_CheckField, 8, 2, 0, 29, 64, // Skip to: 19091 /* 2678 */ MCD_OPC_Decode, 157, 17, 207, 1, // Opcode: VCVB /* 2683 */ MCD_OPC_FilterValue, 82, 27, 0, // Skip to: 2714 /* 2687 */ MCD_OPC_CheckPredicate, 21, 16, 64, // Skip to: 19091 /* 2691 */ MCD_OPC_CheckField, 24, 8, 0, 10, 64, // Skip to: 19091 /* 2697 */ MCD_OPC_CheckField, 11, 9, 0, 4, 64, // Skip to: 19091 /* 2703 */ MCD_OPC_CheckField, 8, 2, 0, 254, 63, // Skip to: 19091 /* 2709 */ MCD_OPC_Decode, 158, 17, 208, 1, // Opcode: VCVBG /* 2714 */ MCD_OPC_FilterValue, 88, 21, 0, // Skip to: 2739 /* 2718 */ MCD_OPC_CheckPredicate, 21, 241, 63, // Skip to: 19091 /* 2722 */ MCD_OPC_CheckField, 24, 8, 0, 235, 63, // Skip to: 19091 /* 2728 */ MCD_OPC_CheckField, 8, 3, 0, 229, 63, // Skip to: 19091 /* 2734 */ MCD_OPC_Decode, 159, 17, 209, 1, // Opcode: VCVD /* 2739 */ MCD_OPC_FilterValue, 89, 15, 0, // Skip to: 2758 /* 2743 */ MCD_OPC_CheckPredicate, 21, 216, 63, // Skip to: 19091 /* 2747 */ MCD_OPC_CheckField, 8, 2, 0, 210, 63, // Skip to: 19091 /* 2753 */ MCD_OPC_Decode, 196, 20, 210, 1, // Opcode: VSRP /* 2758 */ MCD_OPC_FilterValue, 90, 21, 0, // Skip to: 2783 /* 2762 */ MCD_OPC_CheckPredicate, 21, 197, 63, // Skip to: 19091 /* 2766 */ MCD_OPC_CheckField, 24, 8, 0, 191, 63, // Skip to: 19091 /* 2772 */ MCD_OPC_CheckField, 8, 3, 0, 185, 63, // Skip to: 19091 /* 2778 */ MCD_OPC_Decode, 160, 17, 211, 1, // Opcode: VCVDG /* 2783 */ MCD_OPC_FilterValue, 91, 15, 0, // Skip to: 2802 /* 2787 */ MCD_OPC_CheckPredicate, 21, 172, 63, // Skip to: 19091 /* 2791 */ MCD_OPC_CheckField, 8, 2, 0, 166, 63, // Skip to: 19091 /* 2797 */ MCD_OPC_Decode, 152, 20, 210, 1, // Opcode: VPSOP /* 2802 */ MCD_OPC_FilterValue, 95, 27, 0, // Skip to: 2833 /* 2806 */ MCD_OPC_CheckPredicate, 21, 153, 63, // Skip to: 19091 /* 2810 */ MCD_OPC_CheckField, 36, 4, 0, 147, 63, // Skip to: 19091 /* 2816 */ MCD_OPC_CheckField, 11, 21, 0, 141, 63, // Skip to: 19091 /* 2822 */ MCD_OPC_CheckField, 8, 2, 0, 135, 63, // Skip to: 19091 /* 2828 */ MCD_OPC_Decode, 229, 20, 212, 1, // Opcode: VTP /* 2833 */ MCD_OPC_FilterValue, 113, 21, 0, // Skip to: 2858 /* 2837 */ MCD_OPC_CheckPredicate, 21, 122, 63, // Skip to: 19091 /* 2841 */ MCD_OPC_CheckField, 24, 4, 0, 116, 63, // Skip to: 19091 /* 2847 */ MCD_OPC_CheckField, 8, 1, 0, 110, 63, // Skip to: 19091 /* 2853 */ MCD_OPC_Decode, 225, 16, 213, 1, // Opcode: VAP /* 2858 */ MCD_OPC_FilterValue, 115, 21, 0, // Skip to: 2883 /* 2862 */ MCD_OPC_CheckPredicate, 21, 97, 63, // Skip to: 19091 /* 2866 */ MCD_OPC_CheckField, 24, 4, 0, 91, 63, // Skip to: 19091 /* 2872 */ MCD_OPC_CheckField, 8, 1, 0, 85, 63, // Skip to: 19091 /* 2878 */ MCD_OPC_Decode, 190, 20, 213, 1, // Opcode: VSP /* 2883 */ MCD_OPC_FilterValue, 119, 33, 0, // Skip to: 2920 /* 2887 */ MCD_OPC_CheckPredicate, 21, 72, 63, // Skip to: 19091 /* 2891 */ MCD_OPC_CheckField, 36, 4, 0, 66, 63, // Skip to: 19091 /* 2897 */ MCD_OPC_CheckField, 24, 4, 0, 60, 63, // Skip to: 19091 /* 2903 */ MCD_OPC_CheckField, 11, 9, 0, 54, 63, // Skip to: 19091 /* 2909 */ MCD_OPC_CheckField, 8, 1, 0, 48, 63, // Skip to: 19091 /* 2915 */ MCD_OPC_Decode, 151, 17, 214, 1, // Opcode: VCP /* 2920 */ MCD_OPC_FilterValue, 120, 21, 0, // Skip to: 2945 /* 2924 */ MCD_OPC_CheckPredicate, 21, 35, 63, // Skip to: 19091 /* 2928 */ MCD_OPC_CheckField, 24, 4, 0, 29, 63, // Skip to: 19091 /* 2934 */ MCD_OPC_CheckField, 8, 1, 0, 23, 63, // Skip to: 19091 /* 2940 */ MCD_OPC_Decode, 222, 19, 213, 1, // Opcode: VMP /* 2945 */ MCD_OPC_FilterValue, 121, 21, 0, // Skip to: 2970 /* 2949 */ MCD_OPC_CheckPredicate, 21, 10, 63, // Skip to: 19091 /* 2953 */ MCD_OPC_CheckField, 24, 4, 0, 4, 63, // Skip to: 19091 /* 2959 */ MCD_OPC_CheckField, 8, 1, 0, 254, 62, // Skip to: 19091 /* 2965 */ MCD_OPC_Decode, 235, 19, 213, 1, // Opcode: VMSP /* 2970 */ MCD_OPC_FilterValue, 122, 21, 0, // Skip to: 2995 /* 2974 */ MCD_OPC_CheckPredicate, 21, 241, 62, // Skip to: 19091 /* 2978 */ MCD_OPC_CheckField, 24, 4, 0, 235, 62, // Skip to: 19091 /* 2984 */ MCD_OPC_CheckField, 8, 1, 0, 229, 62, // Skip to: 19091 /* 2990 */ MCD_OPC_Decode, 161, 17, 213, 1, // Opcode: VDP /* 2995 */ MCD_OPC_FilterValue, 123, 21, 0, // Skip to: 3020 /* 2999 */ MCD_OPC_CheckPredicate, 21, 216, 62, // Skip to: 19091 /* 3003 */ MCD_OPC_CheckField, 24, 4, 0, 210, 62, // Skip to: 19091 /* 3009 */ MCD_OPC_CheckField, 8, 1, 0, 204, 62, // Skip to: 19091 /* 3015 */ MCD_OPC_Decode, 163, 20, 213, 1, // Opcode: VRP /* 3020 */ MCD_OPC_FilterValue, 126, 195, 62, // Skip to: 19091 /* 3024 */ MCD_OPC_CheckPredicate, 21, 191, 62, // Skip to: 19091 /* 3028 */ MCD_OPC_CheckField, 24, 4, 0, 185, 62, // Skip to: 19091 /* 3034 */ MCD_OPC_CheckField, 8, 1, 0, 179, 62, // Skip to: 19091 /* 3040 */ MCD_OPC_Decode, 178, 20, 213, 1, // Opcode: VSDP /* 3045 */ MCD_OPC_FilterValue, 231, 1, 216, 41, // Skip to: 13762 /* 3050 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 3053 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3072 /* 3057 */ MCD_OPC_CheckPredicate, 22, 158, 62, // Skip to: 19091 /* 3061 */ MCD_OPC_CheckField, 8, 3, 0, 152, 62, // Skip to: 19091 /* 3067 */ MCD_OPC_Decode, 241, 18, 215, 1, // Opcode: VLEB /* 3072 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 3091 /* 3076 */ MCD_OPC_CheckPredicate, 22, 139, 62, // Skip to: 19091 /* 3080 */ MCD_OPC_CheckField, 8, 3, 0, 133, 62, // Skip to: 19091 /* 3086 */ MCD_OPC_Decode, 246, 18, 216, 1, // Opcode: VLEH /* 3091 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3110 /* 3095 */ MCD_OPC_CheckPredicate, 22, 120, 62, // Skip to: 19091 /* 3099 */ MCD_OPC_CheckField, 8, 3, 0, 114, 62, // Skip to: 19091 /* 3105 */ MCD_OPC_Decode, 245, 18, 217, 1, // Opcode: VLEG /* 3110 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 3129 /* 3114 */ MCD_OPC_CheckPredicate, 22, 101, 62, // Skip to: 19091 /* 3118 */ MCD_OPC_CheckField, 8, 3, 0, 95, 62, // Skip to: 19091 /* 3124 */ MCD_OPC_Decode, 244, 18, 218, 1, // Opcode: VLEF /* 3129 */ MCD_OPC_FilterValue, 4, 84, 0, // Skip to: 3217 /* 3133 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 3136 */ MCD_OPC_FilterValue, 0, 79, 62, // Skip to: 19091 /* 3140 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3143 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3156 /* 3147 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 3208 /* 3151 */ MCD_OPC_Decode, 131, 19, 219, 1, // Opcode: VLLEZB /* 3156 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3169 /* 3160 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3208 /* 3164 */ MCD_OPC_Decode, 134, 19, 219, 1, // Opcode: VLLEZH /* 3169 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3182 /* 3173 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3208 /* 3177 */ MCD_OPC_Decode, 132, 19, 219, 1, // Opcode: VLLEZF /* 3182 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3195 /* 3186 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3208 /* 3190 */ MCD_OPC_Decode, 133, 19, 219, 1, // Opcode: VLLEZG /* 3195 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 3208 /* 3199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 3208 /* 3203 */ MCD_OPC_Decode, 135, 19, 219, 1, // Opcode: VLLEZLF /* 3208 */ MCD_OPC_CheckPredicate, 22, 7, 62, // Skip to: 19091 /* 3212 */ MCD_OPC_Decode, 130, 19, 220, 1, // Opcode: VLLEZ /* 3217 */ MCD_OPC_FilterValue, 5, 71, 0, // Skip to: 3292 /* 3221 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 3224 */ MCD_OPC_FilterValue, 0, 247, 61, // Skip to: 19091 /* 3228 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3231 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3244 /* 3235 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3283 /* 3239 */ MCD_OPC_Decode, 144, 19, 219, 1, // Opcode: VLREPB /* 3244 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3257 /* 3248 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3283 /* 3252 */ MCD_OPC_Decode, 147, 19, 219, 1, // Opcode: VLREPH /* 3257 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3270 /* 3261 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3283 /* 3265 */ MCD_OPC_Decode, 145, 19, 219, 1, // Opcode: VLREPF /* 3270 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3283 /* 3274 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3283 /* 3278 */ MCD_OPC_Decode, 146, 19, 219, 1, // Opcode: VLREPG /* 3283 */ MCD_OPC_CheckPredicate, 22, 188, 61, // Skip to: 19091 /* 3287 */ MCD_OPC_Decode, 143, 19, 220, 1, // Opcode: VLREP /* 3292 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 3317 /* 3296 */ MCD_OPC_CheckPredicate, 22, 175, 61, // Skip to: 19091 /* 3300 */ MCD_OPC_CheckField, 12, 4, 0, 169, 61, // Skip to: 19091 /* 3306 */ MCD_OPC_CheckField, 8, 3, 0, 163, 61, // Skip to: 19091 /* 3312 */ MCD_OPC_Decode, 232, 18, 219, 1, // Opcode: VL /* 3317 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 3336 /* 3321 */ MCD_OPC_CheckPredicate, 22, 150, 61, // Skip to: 19091 /* 3325 */ MCD_OPC_CheckField, 8, 3, 0, 144, 61, // Skip to: 19091 /* 3331 */ MCD_OPC_Decode, 233, 18, 220, 1, // Opcode: VLBB /* 3336 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 3355 /* 3340 */ MCD_OPC_CheckPredicate, 22, 131, 61, // Skip to: 19091 /* 3344 */ MCD_OPC_CheckField, 8, 3, 0, 125, 61, // Skip to: 19091 /* 3350 */ MCD_OPC_Decode, 198, 20, 220, 1, // Opcode: VSTEB /* 3355 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 3374 /* 3359 */ MCD_OPC_CheckPredicate, 22, 112, 61, // Skip to: 19091 /* 3363 */ MCD_OPC_CheckField, 8, 3, 0, 106, 61, // Skip to: 19091 /* 3369 */ MCD_OPC_Decode, 201, 20, 221, 1, // Opcode: VSTEH /* 3374 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 3393 /* 3378 */ MCD_OPC_CheckPredicate, 22, 93, 61, // Skip to: 19091 /* 3382 */ MCD_OPC_CheckField, 8, 3, 0, 87, 61, // Skip to: 19091 /* 3388 */ MCD_OPC_Decode, 200, 20, 222, 1, // Opcode: VSTEG /* 3393 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 3412 /* 3397 */ MCD_OPC_CheckPredicate, 22, 74, 61, // Skip to: 19091 /* 3401 */ MCD_OPC_CheckField, 8, 3, 0, 68, 61, // Skip to: 19091 /* 3407 */ MCD_OPC_Decode, 199, 20, 223, 1, // Opcode: VSTEF /* 3412 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 3437 /* 3416 */ MCD_OPC_CheckPredicate, 22, 55, 61, // Skip to: 19091 /* 3420 */ MCD_OPC_CheckField, 12, 4, 0, 49, 61, // Skip to: 19091 /* 3426 */ MCD_OPC_CheckField, 8, 3, 0, 43, 61, // Skip to: 19091 /* 3432 */ MCD_OPC_Decode, 197, 20, 219, 1, // Opcode: VST /* 3437 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 3456 /* 3441 */ MCD_OPC_CheckPredicate, 22, 30, 61, // Skip to: 19091 /* 3445 */ MCD_OPC_CheckField, 8, 2, 0, 24, 61, // Skip to: 19091 /* 3451 */ MCD_OPC_Decode, 209, 18, 224, 1, // Opcode: VGEG /* 3456 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 3475 /* 3460 */ MCD_OPC_CheckPredicate, 22, 11, 61, // Skip to: 19091 /* 3464 */ MCD_OPC_CheckField, 8, 2, 0, 5, 61, // Skip to: 19091 /* 3470 */ MCD_OPC_Decode, 208, 18, 225, 1, // Opcode: VGEF /* 3475 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 3494 /* 3479 */ MCD_OPC_CheckPredicate, 22, 248, 60, // Skip to: 19091 /* 3483 */ MCD_OPC_CheckField, 8, 2, 0, 242, 60, // Skip to: 19091 /* 3489 */ MCD_OPC_Decode, 177, 20, 226, 1, // Opcode: VSCEG /* 3494 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 3513 /* 3498 */ MCD_OPC_CheckPredicate, 22, 229, 60, // Skip to: 19091 /* 3502 */ MCD_OPC_CheckField, 8, 2, 0, 223, 60, // Skip to: 19091 /* 3508 */ MCD_OPC_Decode, 176, 20, 227, 1, // Opcode: VSCEF /* 3513 */ MCD_OPC_FilterValue, 33, 78, 0, // Skip to: 3595 /* 3517 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 3520 */ MCD_OPC_FilterValue, 0, 207, 60, // Skip to: 19091 /* 3524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... /* 3527 */ MCD_OPC_FilterValue, 0, 200, 60, // Skip to: 19091 /* 3531 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3534 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3547 /* 3538 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3586 /* 3542 */ MCD_OPC_Decode, 252, 18, 228, 1, // Opcode: VLGVB /* 3547 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3560 /* 3551 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3586 /* 3555 */ MCD_OPC_Decode, 255, 18, 228, 1, // Opcode: VLGVH /* 3560 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3573 /* 3564 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3586 /* 3568 */ MCD_OPC_Decode, 253, 18, 228, 1, // Opcode: VLGVF /* 3573 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3586 /* 3577 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3586 /* 3581 */ MCD_OPC_Decode, 254, 18, 228, 1, // Opcode: VLGVG /* 3586 */ MCD_OPC_CheckPredicate, 22, 141, 60, // Skip to: 19091 /* 3590 */ MCD_OPC_Decode, 251, 18, 229, 1, // Opcode: VLGV /* 3595 */ MCD_OPC_FilterValue, 34, 71, 0, // Skip to: 3670 /* 3599 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 3602 */ MCD_OPC_FilterValue, 0, 125, 60, // Skip to: 19091 /* 3606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3609 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3622 /* 3613 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3661 /* 3617 */ MCD_OPC_Decode, 151, 19, 230, 1, // Opcode: VLVGB /* 3622 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3635 /* 3626 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3661 /* 3630 */ MCD_OPC_Decode, 154, 19, 230, 1, // Opcode: VLVGH /* 3635 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3648 /* 3639 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3661 /* 3643 */ MCD_OPC_Decode, 152, 19, 230, 1, // Opcode: VLVGF /* 3648 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3661 /* 3652 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3661 /* 3656 */ MCD_OPC_Decode, 153, 19, 231, 1, // Opcode: VLVGG /* 3661 */ MCD_OPC_CheckPredicate, 22, 66, 60, // Skip to: 19091 /* 3665 */ MCD_OPC_Decode, 150, 19, 232, 1, // Opcode: VLVG /* 3670 */ MCD_OPC_FilterValue, 39, 15, 0, // Skip to: 3689 /* 3674 */ MCD_OPC_CheckPredicate, 22, 53, 60, // Skip to: 19091 /* 3678 */ MCD_OPC_CheckField, 8, 4, 0, 47, 60, // Skip to: 19091 /* 3684 */ MCD_OPC_Decode, 131, 10, 233, 1, // Opcode: LCBB /* 3689 */ MCD_OPC_FilterValue, 48, 71, 0, // Skip to: 3764 /* 3693 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 3696 */ MCD_OPC_FilterValue, 0, 31, 60, // Skip to: 19091 /* 3700 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3703 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3716 /* 3707 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3755 /* 3711 */ MCD_OPC_Decode, 188, 17, 234, 1, // Opcode: VESLB /* 3716 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3729 /* 3720 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3755 /* 3724 */ MCD_OPC_Decode, 191, 17, 234, 1, // Opcode: VESLH /* 3729 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3742 /* 3733 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3755 /* 3737 */ MCD_OPC_Decode, 189, 17, 234, 1, // Opcode: VESLF /* 3742 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3755 /* 3746 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3755 /* 3750 */ MCD_OPC_Decode, 190, 17, 234, 1, // Opcode: VESLG /* 3755 */ MCD_OPC_CheckPredicate, 22, 228, 59, // Skip to: 19091 /* 3759 */ MCD_OPC_Decode, 187, 17, 235, 1, // Opcode: VESL /* 3764 */ MCD_OPC_FilterValue, 51, 71, 0, // Skip to: 3839 /* 3768 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 3771 */ MCD_OPC_FilterValue, 0, 212, 59, // Skip to: 19091 /* 3775 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3778 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3791 /* 3782 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3830 /* 3786 */ MCD_OPC_Decode, 178, 17, 234, 1, // Opcode: VERLLB /* 3791 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3804 /* 3795 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3830 /* 3799 */ MCD_OPC_Decode, 181, 17, 234, 1, // Opcode: VERLLH /* 3804 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3817 /* 3808 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3830 /* 3812 */ MCD_OPC_Decode, 179, 17, 234, 1, // Opcode: VERLLF /* 3817 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3830 /* 3821 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3830 /* 3825 */ MCD_OPC_Decode, 180, 17, 234, 1, // Opcode: VERLLG /* 3830 */ MCD_OPC_CheckPredicate, 22, 153, 59, // Skip to: 19091 /* 3834 */ MCD_OPC_Decode, 177, 17, 235, 1, // Opcode: VERLL /* 3839 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 3864 /* 3843 */ MCD_OPC_CheckPredicate, 22, 140, 59, // Skip to: 19091 /* 3847 */ MCD_OPC_CheckField, 12, 4, 0, 134, 59, // Skip to: 19091 /* 3853 */ MCD_OPC_CheckField, 8, 2, 0, 128, 59, // Skip to: 19091 /* 3859 */ MCD_OPC_Decode, 136, 19, 236, 1, // Opcode: VLM /* 3864 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 3889 /* 3868 */ MCD_OPC_CheckPredicate, 22, 115, 59, // Skip to: 19091 /* 3872 */ MCD_OPC_CheckField, 12, 4, 0, 109, 59, // Skip to: 19091 /* 3878 */ MCD_OPC_CheckField, 8, 3, 0, 103, 59, // Skip to: 19091 /* 3884 */ MCD_OPC_Decode, 129, 19, 237, 1, // Opcode: VLL /* 3889 */ MCD_OPC_FilterValue, 56, 71, 0, // Skip to: 3964 /* 3893 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 3896 */ MCD_OPC_FilterValue, 0, 87, 59, // Skip to: 19091 /* 3900 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3903 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3916 /* 3907 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 3955 /* 3911 */ MCD_OPC_Decode, 208, 17, 234, 1, // Opcode: VESRLB /* 3916 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3929 /* 3920 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 3955 /* 3924 */ MCD_OPC_Decode, 211, 17, 234, 1, // Opcode: VESRLH /* 3929 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 3942 /* 3933 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 3955 /* 3937 */ MCD_OPC_Decode, 209, 17, 234, 1, // Opcode: VESRLF /* 3942 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 3955 /* 3946 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3955 /* 3950 */ MCD_OPC_Decode, 210, 17, 234, 1, // Opcode: VESRLG /* 3955 */ MCD_OPC_CheckPredicate, 22, 28, 59, // Skip to: 19091 /* 3959 */ MCD_OPC_Decode, 207, 17, 235, 1, // Opcode: VESRL /* 3964 */ MCD_OPC_FilterValue, 58, 71, 0, // Skip to: 4039 /* 3968 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 3971 */ MCD_OPC_FilterValue, 0, 12, 59, // Skip to: 19091 /* 3975 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 3978 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3991 /* 3982 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4030 /* 3986 */ MCD_OPC_Decode, 198, 17, 234, 1, // Opcode: VESRAB /* 3991 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4004 /* 3995 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4030 /* 3999 */ MCD_OPC_Decode, 201, 17, 234, 1, // Opcode: VESRAH /* 4004 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4017 /* 4008 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4030 /* 4012 */ MCD_OPC_Decode, 199, 17, 234, 1, // Opcode: VESRAF /* 4017 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4030 /* 4021 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4030 /* 4025 */ MCD_OPC_Decode, 200, 17, 234, 1, // Opcode: VESRAG /* 4030 */ MCD_OPC_CheckPredicate, 22, 209, 58, // Skip to: 19091 /* 4034 */ MCD_OPC_Decode, 197, 17, 235, 1, // Opcode: VESRA /* 4039 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 4064 /* 4043 */ MCD_OPC_CheckPredicate, 22, 196, 58, // Skip to: 19091 /* 4047 */ MCD_OPC_CheckField, 12, 4, 0, 190, 58, // Skip to: 19091 /* 4053 */ MCD_OPC_CheckField, 8, 2, 0, 184, 58, // Skip to: 19091 /* 4059 */ MCD_OPC_Decode, 203, 20, 236, 1, // Opcode: VSTM /* 4064 */ MCD_OPC_FilterValue, 63, 21, 0, // Skip to: 4089 /* 4068 */ MCD_OPC_CheckPredicate, 22, 171, 58, // Skip to: 19091 /* 4072 */ MCD_OPC_CheckField, 12, 4, 0, 165, 58, // Skip to: 19091 /* 4078 */ MCD_OPC_CheckField, 8, 3, 0, 159, 58, // Skip to: 19091 /* 4084 */ MCD_OPC_Decode, 202, 20, 237, 1, // Opcode: VSTL /* 4089 */ MCD_OPC_FilterValue, 64, 21, 0, // Skip to: 4114 /* 4093 */ MCD_OPC_CheckPredicate, 22, 146, 58, // Skip to: 19091 /* 4097 */ MCD_OPC_CheckField, 32, 4, 0, 140, 58, // Skip to: 19091 /* 4103 */ MCD_OPC_CheckField, 8, 3, 0, 134, 58, // Skip to: 19091 /* 4109 */ MCD_OPC_Decode, 247, 18, 238, 1, // Opcode: VLEIB /* 4114 */ MCD_OPC_FilterValue, 65, 21, 0, // Skip to: 4139 /* 4118 */ MCD_OPC_CheckPredicate, 22, 121, 58, // Skip to: 19091 /* 4122 */ MCD_OPC_CheckField, 32, 4, 0, 115, 58, // Skip to: 19091 /* 4128 */ MCD_OPC_CheckField, 8, 3, 0, 109, 58, // Skip to: 19091 /* 4134 */ MCD_OPC_Decode, 250, 18, 239, 1, // Opcode: VLEIH /* 4139 */ MCD_OPC_FilterValue, 66, 21, 0, // Skip to: 4164 /* 4143 */ MCD_OPC_CheckPredicate, 22, 96, 58, // Skip to: 19091 /* 4147 */ MCD_OPC_CheckField, 32, 4, 0, 90, 58, // Skip to: 19091 /* 4153 */ MCD_OPC_CheckField, 8, 3, 0, 84, 58, // Skip to: 19091 /* 4159 */ MCD_OPC_Decode, 249, 18, 240, 1, // Opcode: VLEIG /* 4164 */ MCD_OPC_FilterValue, 67, 21, 0, // Skip to: 4189 /* 4168 */ MCD_OPC_CheckPredicate, 22, 71, 58, // Skip to: 19091 /* 4172 */ MCD_OPC_CheckField, 32, 4, 0, 65, 58, // Skip to: 19091 /* 4178 */ MCD_OPC_CheckField, 8, 3, 0, 59, 58, // Skip to: 19091 /* 4184 */ MCD_OPC_Decode, 248, 18, 241, 1, // Opcode: VLEIF /* 4189 */ MCD_OPC_FilterValue, 68, 61, 0, // Skip to: 4254 /* 4193 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 4196 */ MCD_OPC_FilterValue, 0, 43, 58, // Skip to: 19091 /* 4200 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4203 */ MCD_OPC_FilterValue, 0, 36, 58, // Skip to: 19091 /* 4207 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 4210 */ MCD_OPC_FilterValue, 0, 29, 58, // Skip to: 19091 /* 4214 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 4217 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4230 /* 4221 */ MCD_OPC_CheckPredicate, 22, 20, 0, // Skip to: 4245 /* 4225 */ MCD_OPC_Decode, 248, 20, 242, 1, // Opcode: VZERO /* 4230 */ MCD_OPC_FilterValue, 255, 255, 3, 9, 0, // Skip to: 4245 /* 4236 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4245 /* 4240 */ MCD_OPC_Decode, 253, 19, 242, 1, // Opcode: VONE /* 4245 */ MCD_OPC_CheckPredicate, 22, 250, 57, // Skip to: 19091 /* 4249 */ MCD_OPC_Decode, 207, 18, 243, 1, // Opcode: VGBM /* 4254 */ MCD_OPC_FilterValue, 69, 78, 0, // Skip to: 4336 /* 4258 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 4261 */ MCD_OPC_FilterValue, 0, 234, 57, // Skip to: 19091 /* 4265 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 4268 */ MCD_OPC_FilterValue, 0, 227, 57, // Skip to: 19091 /* 4272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4275 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4288 /* 4279 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4327 /* 4283 */ MCD_OPC_Decode, 159, 20, 244, 1, // Opcode: VREPIB /* 4288 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4301 /* 4292 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4327 /* 4296 */ MCD_OPC_Decode, 162, 20, 244, 1, // Opcode: VREPIH /* 4301 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4314 /* 4305 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4327 /* 4309 */ MCD_OPC_Decode, 160, 20, 244, 1, // Opcode: VREPIF /* 4314 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4327 /* 4318 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4327 /* 4322 */ MCD_OPC_Decode, 161, 20, 244, 1, // Opcode: VREPIG /* 4327 */ MCD_OPC_CheckPredicate, 22, 168, 57, // Skip to: 19091 /* 4331 */ MCD_OPC_Decode, 158, 20, 245, 1, // Opcode: VREPI /* 4336 */ MCD_OPC_FilterValue, 70, 78, 0, // Skip to: 4418 /* 4340 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... /* 4343 */ MCD_OPC_FilterValue, 0, 152, 57, // Skip to: 19091 /* 4347 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 4350 */ MCD_OPC_FilterValue, 0, 145, 57, // Skip to: 19091 /* 4354 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4357 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4370 /* 4361 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4409 /* 4365 */ MCD_OPC_Decode, 221, 18, 246, 1, // Opcode: VGMB /* 4370 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4383 /* 4374 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4409 /* 4378 */ MCD_OPC_Decode, 224, 18, 246, 1, // Opcode: VGMH /* 4383 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4396 /* 4387 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4409 /* 4391 */ MCD_OPC_Decode, 222, 18, 246, 1, // Opcode: VGMF /* 4396 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4409 /* 4400 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4409 /* 4404 */ MCD_OPC_Decode, 223, 18, 246, 1, // Opcode: VGMG /* 4409 */ MCD_OPC_CheckPredicate, 22, 86, 57, // Skip to: 19091 /* 4413 */ MCD_OPC_Decode, 220, 18, 247, 1, // Opcode: VGM /* 4418 */ MCD_OPC_FilterValue, 74, 87, 0, // Skip to: 4509 /* 4422 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4425 */ MCD_OPC_FilterValue, 0, 70, 57, // Skip to: 19091 /* 4429 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 4432 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4445 /* 4436 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 4500 /* 4440 */ MCD_OPC_Decode, 206, 18, 248, 1, // Opcode: VFTCISB /* 4445 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4458 /* 4449 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 4500 /* 4453 */ MCD_OPC_Decode, 205, 18, 248, 1, // Opcode: VFTCIDB /* 4458 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 4472 /* 4463 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 4500 /* 4467 */ MCD_OPC_Decode, 222, 21, 249, 1, // Opcode: WFTCISB /* 4472 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 4486 /* 4477 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 4500 /* 4481 */ MCD_OPC_Decode, 221, 21, 250, 1, // Opcode: WFTCIDB /* 4486 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 4500 /* 4491 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4500 /* 4495 */ MCD_OPC_Decode, 223, 21, 248, 1, // Opcode: WFTCIXB /* 4500 */ MCD_OPC_CheckPredicate, 22, 251, 56, // Skip to: 19091 /* 4504 */ MCD_OPC_Decode, 204, 18, 251, 1, // Opcode: VFTCI /* 4509 */ MCD_OPC_FilterValue, 77, 71, 0, // Skip to: 4584 /* 4513 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4516 */ MCD_OPC_FilterValue, 0, 235, 56, // Skip to: 19091 /* 4520 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4523 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4536 /* 4527 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4575 /* 4531 */ MCD_OPC_Decode, 154, 20, 252, 1, // Opcode: VREPB /* 4536 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4549 /* 4540 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4575 /* 4544 */ MCD_OPC_Decode, 157, 20, 252, 1, // Opcode: VREPH /* 4549 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4562 /* 4553 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4575 /* 4557 */ MCD_OPC_Decode, 155, 20, 252, 1, // Opcode: VREPF /* 4562 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4575 /* 4566 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4575 /* 4570 */ MCD_OPC_Decode, 156, 20, 252, 1, // Opcode: VREPG /* 4575 */ MCD_OPC_CheckPredicate, 22, 176, 56, // Skip to: 19091 /* 4579 */ MCD_OPC_Decode, 153, 20, 253, 1, // Opcode: VREP /* 4584 */ MCD_OPC_FilterValue, 80, 78, 0, // Skip to: 4666 /* 4588 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4591 */ MCD_OPC_FilterValue, 0, 160, 56, // Skip to: 19091 /* 4595 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 4598 */ MCD_OPC_FilterValue, 0, 153, 56, // Skip to: 19091 /* 4602 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4605 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4618 /* 4609 */ MCD_OPC_CheckPredicate, 23, 44, 0, // Skip to: 4657 /* 4613 */ MCD_OPC_Decode, 148, 20, 254, 1, // Opcode: VPOPCTB /* 4618 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4631 /* 4622 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 4657 /* 4626 */ MCD_OPC_Decode, 151, 20, 254, 1, // Opcode: VPOPCTH /* 4631 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4644 /* 4635 */ MCD_OPC_CheckPredicate, 23, 18, 0, // Skip to: 4657 /* 4639 */ MCD_OPC_Decode, 149, 20, 254, 1, // Opcode: VPOPCTF /* 4644 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4657 /* 4648 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 4657 /* 4652 */ MCD_OPC_Decode, 150, 20, 254, 1, // Opcode: VPOPCTG /* 4657 */ MCD_OPC_CheckPredicate, 22, 94, 56, // Skip to: 19091 /* 4661 */ MCD_OPC_Decode, 147, 20, 255, 1, // Opcode: VPOPCT /* 4666 */ MCD_OPC_FilterValue, 82, 78, 0, // Skip to: 4748 /* 4670 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4673 */ MCD_OPC_FilterValue, 0, 78, 56, // Skip to: 19091 /* 4677 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 4680 */ MCD_OPC_FilterValue, 0, 71, 56, // Skip to: 19091 /* 4684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4687 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4700 /* 4691 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4739 /* 4695 */ MCD_OPC_Decode, 153, 17, 254, 1, // Opcode: VCTZB /* 4700 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4713 /* 4704 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4739 /* 4708 */ MCD_OPC_Decode, 156, 17, 254, 1, // Opcode: VCTZH /* 4713 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4726 /* 4717 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4739 /* 4721 */ MCD_OPC_Decode, 154, 17, 254, 1, // Opcode: VCTZF /* 4726 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4739 /* 4730 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4739 /* 4734 */ MCD_OPC_Decode, 155, 17, 254, 1, // Opcode: VCTZG /* 4739 */ MCD_OPC_CheckPredicate, 22, 12, 56, // Skip to: 19091 /* 4743 */ MCD_OPC_Decode, 152, 17, 255, 1, // Opcode: VCTZ /* 4748 */ MCD_OPC_FilterValue, 83, 78, 0, // Skip to: 4830 /* 4752 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4755 */ MCD_OPC_FilterValue, 0, 252, 55, // Skip to: 19091 /* 4759 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 4762 */ MCD_OPC_FilterValue, 0, 245, 55, // Skip to: 19091 /* 4766 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4769 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 4782 /* 4773 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 4821 /* 4777 */ MCD_OPC_Decode, 147, 17, 254, 1, // Opcode: VCLZB /* 4782 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4795 /* 4786 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4821 /* 4790 */ MCD_OPC_Decode, 150, 17, 254, 1, // Opcode: VCLZH /* 4795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 4808 /* 4799 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4821 /* 4803 */ MCD_OPC_Decode, 148, 17, 254, 1, // Opcode: VCLZF /* 4808 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 4821 /* 4812 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4821 /* 4816 */ MCD_OPC_Decode, 149, 17, 254, 1, // Opcode: VCLZG /* 4821 */ MCD_OPC_CheckPredicate, 22, 186, 55, // Skip to: 19091 /* 4825 */ MCD_OPC_Decode, 146, 17, 255, 1, // Opcode: VCLZ /* 4830 */ MCD_OPC_FilterValue, 86, 21, 0, // Skip to: 4855 /* 4834 */ MCD_OPC_CheckPredicate, 22, 173, 55, // Skip to: 19091 /* 4838 */ MCD_OPC_CheckField, 12, 20, 0, 167, 55, // Skip to: 19091 /* 4844 */ MCD_OPC_CheckField, 8, 2, 0, 161, 55, // Skip to: 19091 /* 4850 */ MCD_OPC_Decode, 142, 19, 254, 1, // Opcode: VLR /* 4855 */ MCD_OPC_FilterValue, 92, 117, 0, // Skip to: 4976 /* 4859 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4862 */ MCD_OPC_FilterValue, 0, 145, 55, // Skip to: 19091 /* 4866 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 4869 */ MCD_OPC_FilterValue, 0, 138, 55, // Skip to: 19091 /* 4873 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 4876 */ MCD_OPC_FilterValue, 0, 131, 55, // Skip to: 19091 /* 4880 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4883 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4911 /* 4887 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4902 /* 4891 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4902 /* 4897 */ MCD_OPC_Decode, 227, 18, 254, 1, // Opcode: VISTRBS /* 4902 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 4967 /* 4906 */ MCD_OPC_Decode, 226, 18, 128, 2, // Opcode: VISTRB /* 4911 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4939 /* 4915 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4930 /* 4919 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4930 /* 4925 */ MCD_OPC_Decode, 231, 18, 254, 1, // Opcode: VISTRHS /* 4930 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 4967 /* 4934 */ MCD_OPC_Decode, 230, 18, 128, 2, // Opcode: VISTRH /* 4939 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 4967 /* 4943 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4958 /* 4947 */ MCD_OPC_CheckField, 20, 4, 1, 5, 0, // Skip to: 4958 /* 4953 */ MCD_OPC_Decode, 229, 18, 254, 1, // Opcode: VISTRFS /* 4958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4967 /* 4962 */ MCD_OPC_Decode, 228, 18, 128, 2, // Opcode: VISTRF /* 4967 */ MCD_OPC_CheckPredicate, 22, 40, 55, // Skip to: 19091 /* 4971 */ MCD_OPC_Decode, 225, 18, 129, 2, // Opcode: VISTR /* 4976 */ MCD_OPC_FilterValue, 95, 65, 0, // Skip to: 5045 /* 4980 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 4983 */ MCD_OPC_FilterValue, 0, 24, 55, // Skip to: 19091 /* 4987 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 4990 */ MCD_OPC_FilterValue, 0, 17, 55, // Skip to: 19091 /* 4994 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 4997 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5010 /* 5001 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5036 /* 5005 */ MCD_OPC_Decode, 180, 20, 254, 1, // Opcode: VSEGB /* 5010 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5023 /* 5014 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5036 /* 5018 */ MCD_OPC_Decode, 182, 20, 254, 1, // Opcode: VSEGH /* 5023 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5036 /* 5027 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5036 /* 5031 */ MCD_OPC_Decode, 181, 20, 254, 1, // Opcode: VSEGF /* 5036 */ MCD_OPC_CheckPredicate, 22, 227, 54, // Skip to: 19091 /* 5040 */ MCD_OPC_Decode, 179, 20, 255, 1, // Opcode: VSEG /* 5045 */ MCD_OPC_FilterValue, 96, 78, 0, // Skip to: 5127 /* 5049 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5052 */ MCD_OPC_FilterValue, 0, 211, 54, // Skip to: 19091 /* 5056 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5059 */ MCD_OPC_FilterValue, 0, 204, 54, // Skip to: 19091 /* 5063 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5066 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5079 /* 5070 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5118 /* 5074 */ MCD_OPC_Decode, 229, 19, 130, 2, // Opcode: VMRLB /* 5079 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5092 /* 5083 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5118 /* 5087 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: VMRLH /* 5092 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5105 /* 5096 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5118 /* 5100 */ MCD_OPC_Decode, 230, 19, 130, 2, // Opcode: VMRLF /* 5105 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5118 /* 5109 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5118 /* 5113 */ MCD_OPC_Decode, 231, 19, 130, 2, // Opcode: VMRLG /* 5118 */ MCD_OPC_CheckPredicate, 22, 145, 54, // Skip to: 19091 /* 5122 */ MCD_OPC_Decode, 228, 19, 131, 2, // Opcode: VMRL /* 5127 */ MCD_OPC_FilterValue, 97, 78, 0, // Skip to: 5209 /* 5131 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5134 */ MCD_OPC_FilterValue, 0, 129, 54, // Skip to: 19091 /* 5138 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5141 */ MCD_OPC_FilterValue, 0, 122, 54, // Skip to: 19091 /* 5145 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5161 /* 5152 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5200 /* 5156 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: VMRHB /* 5161 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5174 /* 5165 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5200 /* 5169 */ MCD_OPC_Decode, 227, 19, 130, 2, // Opcode: VMRHH /* 5174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5187 /* 5178 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5200 /* 5182 */ MCD_OPC_Decode, 225, 19, 130, 2, // Opcode: VMRHF /* 5187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5200 /* 5191 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5200 /* 5195 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: VMRHG /* 5200 */ MCD_OPC_CheckPredicate, 22, 63, 54, // Skip to: 19091 /* 5204 */ MCD_OPC_Decode, 223, 19, 131, 2, // Opcode: VMRH /* 5209 */ MCD_OPC_FilterValue, 98, 21, 0, // Skip to: 5234 /* 5213 */ MCD_OPC_CheckPredicate, 22, 50, 54, // Skip to: 19091 /* 5217 */ MCD_OPC_CheckField, 12, 16, 0, 44, 54, // Skip to: 19091 /* 5223 */ MCD_OPC_CheckField, 8, 3, 0, 38, 54, // Skip to: 19091 /* 5229 */ MCD_OPC_Decode, 155, 19, 132, 2, // Opcode: VLVGP /* 5234 */ MCD_OPC_FilterValue, 100, 52, 0, // Skip to: 5290 /* 5238 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5241 */ MCD_OPC_FilterValue, 0, 22, 54, // Skip to: 19091 /* 5245 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5248 */ MCD_OPC_FilterValue, 0, 15, 54, // Skip to: 19091 /* 5252 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5255 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5268 /* 5259 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5281 /* 5263 */ MCD_OPC_Decode, 220, 20, 130, 2, // Opcode: VSUMB /* 5268 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5281 /* 5272 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5281 /* 5276 */ MCD_OPC_Decode, 224, 20, 130, 2, // Opcode: VSUMH /* 5281 */ MCD_OPC_CheckPredicate, 22, 238, 53, // Skip to: 19091 /* 5285 */ MCD_OPC_Decode, 219, 20, 131, 2, // Opcode: VSUM /* 5290 */ MCD_OPC_FilterValue, 101, 52, 0, // Skip to: 5346 /* 5294 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5297 */ MCD_OPC_FilterValue, 0, 222, 53, // Skip to: 19091 /* 5301 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5304 */ MCD_OPC_FilterValue, 0, 215, 53, // Skip to: 19091 /* 5308 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5311 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5324 /* 5315 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5337 /* 5319 */ MCD_OPC_Decode, 223, 20, 130, 2, // Opcode: VSUMGH /* 5324 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5337 /* 5328 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5337 /* 5332 */ MCD_OPC_Decode, 222, 20, 130, 2, // Opcode: VSUMGF /* 5337 */ MCD_OPC_CheckPredicate, 22, 182, 53, // Skip to: 19091 /* 5341 */ MCD_OPC_Decode, 221, 20, 131, 2, // Opcode: VSUMG /* 5346 */ MCD_OPC_FilterValue, 102, 21, 0, // Skip to: 5371 /* 5350 */ MCD_OPC_CheckPredicate, 22, 169, 53, // Skip to: 19091 /* 5354 */ MCD_OPC_CheckField, 12, 16, 0, 163, 53, // Skip to: 19091 /* 5360 */ MCD_OPC_CheckField, 8, 1, 0, 157, 53, // Skip to: 19091 /* 5366 */ MCD_OPC_Decode, 143, 17, 130, 2, // Opcode: VCKSM /* 5371 */ MCD_OPC_FilterValue, 103, 52, 0, // Skip to: 5427 /* 5375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5378 */ MCD_OPC_FilterValue, 0, 141, 53, // Skip to: 19091 /* 5382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5385 */ MCD_OPC_FilterValue, 0, 134, 53, // Skip to: 19091 /* 5389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5392 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5405 /* 5396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5418 /* 5400 */ MCD_OPC_Decode, 226, 20, 130, 2, // Opcode: VSUMQF /* 5405 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5418 /* 5409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5418 /* 5413 */ MCD_OPC_Decode, 227, 20, 130, 2, // Opcode: VSUMQG /* 5418 */ MCD_OPC_CheckPredicate, 22, 101, 53, // Skip to: 19091 /* 5422 */ MCD_OPC_Decode, 225, 20, 131, 2, // Opcode: VSUMQ /* 5427 */ MCD_OPC_FilterValue, 104, 21, 0, // Skip to: 5452 /* 5431 */ MCD_OPC_CheckPredicate, 22, 88, 53, // Skip to: 19091 /* 5435 */ MCD_OPC_CheckField, 12, 16, 0, 82, 53, // Skip to: 19091 /* 5441 */ MCD_OPC_CheckField, 8, 1, 0, 76, 53, // Skip to: 19091 /* 5447 */ MCD_OPC_Decode, 246, 19, 130, 2, // Opcode: VN /* 5452 */ MCD_OPC_FilterValue, 105, 21, 0, // Skip to: 5477 /* 5456 */ MCD_OPC_CheckPredicate, 22, 63, 53, // Skip to: 19091 /* 5460 */ MCD_OPC_CheckField, 12, 16, 0, 57, 53, // Skip to: 19091 /* 5466 */ MCD_OPC_CheckField, 8, 1, 0, 51, 53, // Skip to: 19091 /* 5472 */ MCD_OPC_Decode, 247, 19, 130, 2, // Opcode: VNC /* 5477 */ MCD_OPC_FilterValue, 106, 21, 0, // Skip to: 5502 /* 5481 */ MCD_OPC_CheckPredicate, 22, 38, 53, // Skip to: 19091 /* 5485 */ MCD_OPC_CheckField, 12, 16, 0, 32, 53, // Skip to: 19091 /* 5491 */ MCD_OPC_CheckField, 8, 1, 0, 26, 53, // Skip to: 19091 /* 5497 */ MCD_OPC_Decode, 251, 19, 130, 2, // Opcode: VO /* 5502 */ MCD_OPC_FilterValue, 107, 21, 0, // Skip to: 5527 /* 5506 */ MCD_OPC_CheckPredicate, 22, 13, 53, // Skip to: 19091 /* 5510 */ MCD_OPC_CheckField, 12, 16, 0, 7, 53, // Skip to: 19091 /* 5516 */ MCD_OPC_CheckField, 8, 1, 0, 1, 53, // Skip to: 19091 /* 5522 */ MCD_OPC_Decode, 249, 19, 130, 2, // Opcode: VNO /* 5527 */ MCD_OPC_FilterValue, 108, 21, 0, // Skip to: 5552 /* 5531 */ MCD_OPC_CheckPredicate, 23, 244, 52, // Skip to: 19091 /* 5535 */ MCD_OPC_CheckField, 12, 16, 0, 238, 52, // Skip to: 19091 /* 5541 */ MCD_OPC_CheckField, 8, 1, 0, 232, 52, // Skip to: 19091 /* 5547 */ MCD_OPC_Decode, 250, 19, 130, 2, // Opcode: VNX /* 5552 */ MCD_OPC_FilterValue, 109, 21, 0, // Skip to: 5577 /* 5556 */ MCD_OPC_CheckPredicate, 22, 219, 52, // Skip to: 19091 /* 5560 */ MCD_OPC_CheckField, 12, 16, 0, 213, 52, // Skip to: 19091 /* 5566 */ MCD_OPC_CheckField, 8, 1, 0, 207, 52, // Skip to: 19091 /* 5572 */ MCD_OPC_Decode, 247, 20, 130, 2, // Opcode: VX /* 5577 */ MCD_OPC_FilterValue, 110, 21, 0, // Skip to: 5602 /* 5581 */ MCD_OPC_CheckPredicate, 23, 194, 52, // Skip to: 19091 /* 5585 */ MCD_OPC_CheckField, 12, 16, 0, 188, 52, // Skip to: 19091 /* 5591 */ MCD_OPC_CheckField, 8, 1, 0, 182, 52, // Skip to: 19091 /* 5597 */ MCD_OPC_Decode, 248, 19, 130, 2, // Opcode: VNN /* 5602 */ MCD_OPC_FilterValue, 111, 21, 0, // Skip to: 5627 /* 5606 */ MCD_OPC_CheckPredicate, 23, 169, 52, // Skip to: 19091 /* 5610 */ MCD_OPC_CheckField, 12, 16, 0, 163, 52, // Skip to: 19091 /* 5616 */ MCD_OPC_CheckField, 8, 1, 0, 157, 52, // Skip to: 19091 /* 5622 */ MCD_OPC_Decode, 252, 19, 130, 2, // Opcode: VOC /* 5627 */ MCD_OPC_FilterValue, 112, 78, 0, // Skip to: 5709 /* 5631 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5634 */ MCD_OPC_FilterValue, 0, 141, 52, // Skip to: 19091 /* 5638 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5641 */ MCD_OPC_FilterValue, 0, 134, 52, // Skip to: 19091 /* 5645 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5648 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5661 /* 5652 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5700 /* 5656 */ MCD_OPC_Decode, 193, 17, 130, 2, // Opcode: VESLVB /* 5661 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5674 /* 5665 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5700 /* 5669 */ MCD_OPC_Decode, 196, 17, 130, 2, // Opcode: VESLVH /* 5674 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5687 /* 5678 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5700 /* 5682 */ MCD_OPC_Decode, 194, 17, 130, 2, // Opcode: VESLVF /* 5687 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5700 /* 5691 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5700 /* 5695 */ MCD_OPC_Decode, 195, 17, 130, 2, // Opcode: VESLVG /* 5700 */ MCD_OPC_CheckPredicate, 22, 75, 52, // Skip to: 19091 /* 5704 */ MCD_OPC_Decode, 192, 17, 131, 2, // Opcode: VESLV /* 5709 */ MCD_OPC_FilterValue, 114, 78, 0, // Skip to: 5791 /* 5713 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5716 */ MCD_OPC_FilterValue, 0, 59, 52, // Skip to: 19091 /* 5720 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 5723 */ MCD_OPC_FilterValue, 0, 52, 52, // Skip to: 19091 /* 5727 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5730 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5743 /* 5734 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5782 /* 5738 */ MCD_OPC_Decode, 173, 17, 133, 2, // Opcode: VERIMB /* 5743 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5756 /* 5747 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5782 /* 5751 */ MCD_OPC_Decode, 176, 17, 133, 2, // Opcode: VERIMH /* 5756 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5769 /* 5760 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5782 /* 5764 */ MCD_OPC_Decode, 174, 17, 133, 2, // Opcode: VERIMF /* 5769 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5782 /* 5773 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5782 /* 5777 */ MCD_OPC_Decode, 175, 17, 133, 2, // Opcode: VERIMG /* 5782 */ MCD_OPC_CheckPredicate, 22, 249, 51, // Skip to: 19091 /* 5786 */ MCD_OPC_Decode, 172, 17, 134, 2, // Opcode: VERIM /* 5791 */ MCD_OPC_FilterValue, 115, 78, 0, // Skip to: 5873 /* 5795 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5798 */ MCD_OPC_FilterValue, 0, 233, 51, // Skip to: 19091 /* 5802 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5805 */ MCD_OPC_FilterValue, 0, 226, 51, // Skip to: 19091 /* 5809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5812 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5825 /* 5816 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 5864 /* 5820 */ MCD_OPC_Decode, 183, 17, 130, 2, // Opcode: VERLLVB /* 5825 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 5838 /* 5829 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 5864 /* 5833 */ MCD_OPC_Decode, 186, 17, 130, 2, // Opcode: VERLLVH /* 5838 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 5851 /* 5842 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 5864 /* 5846 */ MCD_OPC_Decode, 184, 17, 130, 2, // Opcode: VERLLVF /* 5851 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 5864 /* 5855 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 5864 /* 5859 */ MCD_OPC_Decode, 185, 17, 130, 2, // Opcode: VERLLVG /* 5864 */ MCD_OPC_CheckPredicate, 22, 167, 51, // Skip to: 19091 /* 5868 */ MCD_OPC_Decode, 182, 17, 131, 2, // Opcode: VERLLV /* 5873 */ MCD_OPC_FilterValue, 116, 21, 0, // Skip to: 5898 /* 5877 */ MCD_OPC_CheckPredicate, 22, 154, 51, // Skip to: 19091 /* 5881 */ MCD_OPC_CheckField, 12, 16, 0, 148, 51, // Skip to: 19091 /* 5887 */ MCD_OPC_CheckField, 8, 1, 0, 142, 51, // Skip to: 19091 /* 5893 */ MCD_OPC_Decode, 187, 20, 130, 2, // Opcode: VSL /* 5898 */ MCD_OPC_FilterValue, 117, 21, 0, // Skip to: 5923 /* 5902 */ MCD_OPC_CheckPredicate, 22, 129, 51, // Skip to: 19091 /* 5906 */ MCD_OPC_CheckField, 12, 16, 0, 123, 51, // Skip to: 19091 /* 5912 */ MCD_OPC_CheckField, 8, 1, 0, 117, 51, // Skip to: 19091 /* 5918 */ MCD_OPC_Decode, 188, 20, 130, 2, // Opcode: VSLB /* 5923 */ MCD_OPC_FilterValue, 119, 27, 0, // Skip to: 5954 /* 5927 */ MCD_OPC_CheckPredicate, 22, 104, 51, // Skip to: 19091 /* 5931 */ MCD_OPC_CheckField, 24, 4, 0, 98, 51, // Skip to: 19091 /* 5937 */ MCD_OPC_CheckField, 12, 4, 0, 92, 51, // Skip to: 19091 /* 5943 */ MCD_OPC_CheckField, 8, 1, 0, 86, 51, // Skip to: 19091 /* 5949 */ MCD_OPC_Decode, 189, 20, 135, 2, // Opcode: VSLDB /* 5954 */ MCD_OPC_FilterValue, 120, 78, 0, // Skip to: 6036 /* 5958 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 5961 */ MCD_OPC_FilterValue, 0, 70, 51, // Skip to: 19091 /* 5965 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 5968 */ MCD_OPC_FilterValue, 0, 63, 51, // Skip to: 19091 /* 5972 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 5988 /* 5979 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6027 /* 5983 */ MCD_OPC_Decode, 213, 17, 130, 2, // Opcode: VESRLVB /* 5988 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6001 /* 5992 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6027 /* 5996 */ MCD_OPC_Decode, 216, 17, 130, 2, // Opcode: VESRLVH /* 6001 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6014 /* 6005 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6027 /* 6009 */ MCD_OPC_Decode, 214, 17, 130, 2, // Opcode: VESRLVF /* 6014 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6027 /* 6018 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6027 /* 6022 */ MCD_OPC_Decode, 215, 17, 130, 2, // Opcode: VESRLVG /* 6027 */ MCD_OPC_CheckPredicate, 22, 4, 51, // Skip to: 19091 /* 6031 */ MCD_OPC_Decode, 212, 17, 131, 2, // Opcode: VESRLV /* 6036 */ MCD_OPC_FilterValue, 122, 78, 0, // Skip to: 6118 /* 6040 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 6043 */ MCD_OPC_FilterValue, 0, 244, 50, // Skip to: 19091 /* 6047 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 6050 */ MCD_OPC_FilterValue, 0, 237, 50, // Skip to: 19091 /* 6054 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6057 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6070 /* 6061 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 6109 /* 6065 */ MCD_OPC_Decode, 203, 17, 130, 2, // Opcode: VESRAVB /* 6070 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6083 /* 6074 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6109 /* 6078 */ MCD_OPC_Decode, 206, 17, 130, 2, // Opcode: VESRAVH /* 6083 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6096 /* 6087 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6109 /* 6091 */ MCD_OPC_Decode, 204, 17, 130, 2, // Opcode: VESRAVF /* 6096 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6109 /* 6100 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6109 /* 6104 */ MCD_OPC_Decode, 205, 17, 130, 2, // Opcode: VESRAVG /* 6109 */ MCD_OPC_CheckPredicate, 22, 178, 50, // Skip to: 19091 /* 6113 */ MCD_OPC_Decode, 202, 17, 131, 2, // Opcode: VESRAV /* 6118 */ MCD_OPC_FilterValue, 124, 21, 0, // Skip to: 6143 /* 6122 */ MCD_OPC_CheckPredicate, 22, 165, 50, // Skip to: 19091 /* 6126 */ MCD_OPC_CheckField, 12, 16, 0, 159, 50, // Skip to: 19091 /* 6132 */ MCD_OPC_CheckField, 8, 1, 0, 153, 50, // Skip to: 19091 /* 6138 */ MCD_OPC_Decode, 194, 20, 130, 2, // Opcode: VSRL /* 6143 */ MCD_OPC_FilterValue, 125, 21, 0, // Skip to: 6168 /* 6147 */ MCD_OPC_CheckPredicate, 22, 140, 50, // Skip to: 19091 /* 6151 */ MCD_OPC_CheckField, 12, 16, 0, 134, 50, // Skip to: 19091 /* 6157 */ MCD_OPC_CheckField, 8, 1, 0, 128, 50, // Skip to: 19091 /* 6163 */ MCD_OPC_Decode, 195, 20, 130, 2, // Opcode: VSRLB /* 6168 */ MCD_OPC_FilterValue, 126, 21, 0, // Skip to: 6193 /* 6172 */ MCD_OPC_CheckPredicate, 22, 115, 50, // Skip to: 19091 /* 6176 */ MCD_OPC_CheckField, 12, 16, 0, 109, 50, // Skip to: 19091 /* 6182 */ MCD_OPC_CheckField, 8, 1, 0, 103, 50, // Skip to: 19091 /* 6188 */ MCD_OPC_Decode, 192, 20, 130, 2, // Opcode: VSRA /* 6193 */ MCD_OPC_FilterValue, 127, 21, 0, // Skip to: 6218 /* 6197 */ MCD_OPC_CheckPredicate, 22, 90, 50, // Skip to: 19091 /* 6201 */ MCD_OPC_CheckField, 12, 16, 0, 84, 50, // Skip to: 19091 /* 6207 */ MCD_OPC_CheckField, 8, 1, 0, 78, 50, // Skip to: 19091 /* 6213 */ MCD_OPC_Decode, 193, 20, 130, 2, // Opcode: VSRAB /* 6218 */ MCD_OPC_FilterValue, 128, 1, 198, 0, // Skip to: 6421 /* 6223 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 6226 */ MCD_OPC_FilterValue, 0, 61, 50, // Skip to: 19091 /* 6230 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 6233 */ MCD_OPC_FilterValue, 0, 54, 50, // Skip to: 19091 /* 6237 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 6240 */ MCD_OPC_FilterValue, 0, 47, 50, // Skip to: 19091 /* 6244 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6247 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6302 /* 6251 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 6254 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6267 /* 6258 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6293 /* 6262 */ MCD_OPC_Decode, 253, 17, 130, 2, // Opcode: VFEEBS /* 6267 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6280 /* 6271 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6293 /* 6275 */ MCD_OPC_Decode, 130, 18, 130, 2, // Opcode: VFEEZB /* 6280 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6293 /* 6284 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6293 /* 6288 */ MCD_OPC_Decode, 131, 18, 130, 2, // Opcode: VFEEZBS /* 6293 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6412 /* 6297 */ MCD_OPC_Decode, 252, 17, 136, 2, // Opcode: VFEEB /* 6302 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6357 /* 6306 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 6309 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6322 /* 6313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6348 /* 6317 */ MCD_OPC_Decode, 129, 18, 130, 2, // Opcode: VFEEHS /* 6322 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6335 /* 6326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6348 /* 6330 */ MCD_OPC_Decode, 134, 18, 130, 2, // Opcode: VFEEZH /* 6335 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6348 /* 6339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6348 /* 6343 */ MCD_OPC_Decode, 135, 18, 130, 2, // Opcode: VFEEZHS /* 6348 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6412 /* 6352 */ MCD_OPC_Decode, 128, 18, 136, 2, // Opcode: VFEEH /* 6357 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6412 /* 6361 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 6364 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6377 /* 6368 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6403 /* 6372 */ MCD_OPC_Decode, 255, 17, 130, 2, // Opcode: VFEEFS /* 6377 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6390 /* 6381 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6403 /* 6385 */ MCD_OPC_Decode, 132, 18, 130, 2, // Opcode: VFEEZF /* 6390 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6403 /* 6394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6403 /* 6398 */ MCD_OPC_Decode, 133, 18, 130, 2, // Opcode: VFEEZFS /* 6403 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6412 /* 6407 */ MCD_OPC_Decode, 254, 17, 136, 2, // Opcode: VFEEF /* 6412 */ MCD_OPC_CheckPredicate, 22, 131, 49, // Skip to: 19091 /* 6416 */ MCD_OPC_Decode, 251, 17, 137, 2, // Opcode: VFEE /* 6421 */ MCD_OPC_FilterValue, 129, 1, 198, 0, // Skip to: 6624 /* 6426 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 6429 */ MCD_OPC_FilterValue, 0, 114, 49, // Skip to: 19091 /* 6433 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 6436 */ MCD_OPC_FilterValue, 0, 107, 49, // Skip to: 19091 /* 6440 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 6443 */ MCD_OPC_FilterValue, 0, 100, 49, // Skip to: 19091 /* 6447 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6450 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6505 /* 6454 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 6457 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6470 /* 6461 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6496 /* 6465 */ MCD_OPC_Decode, 138, 18, 130, 2, // Opcode: VFENEBS /* 6470 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6483 /* 6474 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6496 /* 6478 */ MCD_OPC_Decode, 143, 18, 130, 2, // Opcode: VFENEZB /* 6483 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6496 /* 6487 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6496 /* 6491 */ MCD_OPC_Decode, 144, 18, 130, 2, // Opcode: VFENEZBS /* 6496 */ MCD_OPC_CheckPredicate, 22, 115, 0, // Skip to: 6615 /* 6500 */ MCD_OPC_Decode, 137, 18, 136, 2, // Opcode: VFENEB /* 6505 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6560 /* 6509 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 6512 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6525 /* 6516 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6551 /* 6520 */ MCD_OPC_Decode, 142, 18, 130, 2, // Opcode: VFENEHS /* 6525 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6538 /* 6529 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6551 /* 6533 */ MCD_OPC_Decode, 147, 18, 130, 2, // Opcode: VFENEZH /* 6538 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6551 /* 6542 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6551 /* 6546 */ MCD_OPC_Decode, 148, 18, 130, 2, // Opcode: VFENEZHS /* 6551 */ MCD_OPC_CheckPredicate, 22, 60, 0, // Skip to: 6615 /* 6555 */ MCD_OPC_Decode, 141, 18, 136, 2, // Opcode: VFENEH /* 6560 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6615 /* 6564 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 6567 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 6580 /* 6571 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 6606 /* 6575 */ MCD_OPC_Decode, 140, 18, 130, 2, // Opcode: VFENEFS /* 6580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 6593 /* 6584 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 6606 /* 6588 */ MCD_OPC_Decode, 145, 18, 130, 2, // Opcode: VFENEZF /* 6593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 6606 /* 6597 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6606 /* 6601 */ MCD_OPC_Decode, 146, 18, 130, 2, // Opcode: VFENEZFS /* 6606 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6615 /* 6610 */ MCD_OPC_Decode, 139, 18, 136, 2, // Opcode: VFENEF /* 6615 */ MCD_OPC_CheckPredicate, 22, 184, 48, // Skip to: 19091 /* 6619 */ MCD_OPC_Decode, 136, 18, 137, 2, // Opcode: VFENE /* 6624 */ MCD_OPC_FilterValue, 130, 1, 207, 0, // Skip to: 6836 /* 6629 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 6632 */ MCD_OPC_FilterValue, 0, 167, 48, // Skip to: 19091 /* 6636 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 6639 */ MCD_OPC_FilterValue, 0, 160, 48, // Skip to: 19091 /* 6643 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 6646 */ MCD_OPC_FilterValue, 0, 153, 48, // Skip to: 19091 /* 6650 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 6653 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6711 /* 6657 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6672 /* 6661 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6672 /* 6667 */ MCD_OPC_Decode, 227, 17, 138, 2, // Opcode: VFAEZBS /* 6672 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6687 /* 6676 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6687 /* 6682 */ MCD_OPC_Decode, 221, 17, 139, 2, // Opcode: VFAEBS /* 6687 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6702 /* 6691 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6702 /* 6697 */ MCD_OPC_Decode, 226, 17, 140, 2, // Opcode: VFAEZB /* 6702 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 6827 /* 6706 */ MCD_OPC_Decode, 220, 17, 136, 2, // Opcode: VFAEB /* 6711 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 6769 /* 6715 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6730 /* 6719 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6730 /* 6725 */ MCD_OPC_Decode, 231, 17, 138, 2, // Opcode: VFAEZHS /* 6730 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6745 /* 6734 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6745 /* 6740 */ MCD_OPC_Decode, 225, 17, 139, 2, // Opcode: VFAEHS /* 6745 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6760 /* 6749 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6760 /* 6755 */ MCD_OPC_Decode, 230, 17, 140, 2, // Opcode: VFAEZH /* 6760 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 6827 /* 6764 */ MCD_OPC_Decode, 224, 17, 136, 2, // Opcode: VFAEH /* 6769 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 6827 /* 6773 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6788 /* 6777 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6788 /* 6783 */ MCD_OPC_Decode, 229, 17, 138, 2, // Opcode: VFAEZFS /* 6788 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6803 /* 6792 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6803 /* 6798 */ MCD_OPC_Decode, 223, 17, 139, 2, // Opcode: VFAEFS /* 6803 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6818 /* 6807 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6818 /* 6813 */ MCD_OPC_Decode, 228, 17, 140, 2, // Opcode: VFAEZF /* 6818 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 6827 /* 6822 */ MCD_OPC_Decode, 222, 17, 136, 2, // Opcode: VFAEF /* 6827 */ MCD_OPC_CheckPredicate, 22, 228, 47, // Skip to: 19091 /* 6831 */ MCD_OPC_Decode, 219, 17, 137, 2, // Opcode: VFAE /* 6836 */ MCD_OPC_FilterValue, 132, 1, 21, 0, // Skip to: 6862 /* 6841 */ MCD_OPC_CheckPredicate, 22, 214, 47, // Skip to: 19091 /* 6845 */ MCD_OPC_CheckField, 16, 12, 0, 208, 47, // Skip to: 19091 /* 6851 */ MCD_OPC_CheckField, 8, 1, 0, 202, 47, // Skip to: 19091 /* 6857 */ MCD_OPC_Decode, 254, 19, 131, 2, // Opcode: VPDI /* 6862 */ MCD_OPC_FilterValue, 133, 1, 21, 0, // Skip to: 6888 /* 6867 */ MCD_OPC_CheckPredicate, 23, 188, 47, // Skip to: 19091 /* 6871 */ MCD_OPC_CheckField, 12, 16, 0, 182, 47, // Skip to: 19091 /* 6877 */ MCD_OPC_CheckField, 8, 1, 0, 176, 47, // Skip to: 19091 /* 6883 */ MCD_OPC_Decode, 237, 16, 130, 2, // Opcode: VBPERM /* 6888 */ MCD_OPC_FilterValue, 138, 1, 193, 0, // Skip to: 7086 /* 6893 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 6896 */ MCD_OPC_FilterValue, 0, 159, 47, // Skip to: 19091 /* 6900 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 6903 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 6961 /* 6907 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6922 /* 6911 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6922 /* 6917 */ MCD_OPC_Decode, 212, 20, 141, 2, // Opcode: VSTRCZBS /* 6922 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6937 /* 6926 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6937 /* 6932 */ MCD_OPC_Decode, 206, 20, 142, 2, // Opcode: VSTRCBS /* 6937 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6952 /* 6941 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 6952 /* 6947 */ MCD_OPC_Decode, 211, 20, 143, 2, // Opcode: VSTRCZB /* 6952 */ MCD_OPC_CheckPredicate, 22, 121, 0, // Skip to: 7077 /* 6956 */ MCD_OPC_Decode, 205, 20, 144, 2, // Opcode: VSTRCB /* 6961 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 7019 /* 6965 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6980 /* 6969 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 6980 /* 6975 */ MCD_OPC_Decode, 216, 20, 141, 2, // Opcode: VSTRCZHS /* 6980 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 6995 /* 6984 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 6995 /* 6990 */ MCD_OPC_Decode, 210, 20, 142, 2, // Opcode: VSTRCHS /* 6995 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7010 /* 6999 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7010 /* 7005 */ MCD_OPC_Decode, 215, 20, 143, 2, // Opcode: VSTRCZH /* 7010 */ MCD_OPC_CheckPredicate, 22, 63, 0, // Skip to: 7077 /* 7014 */ MCD_OPC_Decode, 209, 20, 144, 2, // Opcode: VSTRCH /* 7019 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 7077 /* 7023 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7038 /* 7027 */ MCD_OPC_CheckField, 20, 2, 3, 5, 0, // Skip to: 7038 /* 7033 */ MCD_OPC_Decode, 214, 20, 141, 2, // Opcode: VSTRCZFS /* 7038 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7053 /* 7042 */ MCD_OPC_CheckField, 20, 1, 1, 5, 0, // Skip to: 7053 /* 7048 */ MCD_OPC_Decode, 208, 20, 142, 2, // Opcode: VSTRCFS /* 7053 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 7068 /* 7057 */ MCD_OPC_CheckField, 21, 1, 1, 5, 0, // Skip to: 7068 /* 7063 */ MCD_OPC_Decode, 213, 20, 143, 2, // Opcode: VSTRCZF /* 7068 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7077 /* 7072 */ MCD_OPC_Decode, 207, 20, 144, 2, // Opcode: VSTRCF /* 7077 */ MCD_OPC_CheckPredicate, 22, 234, 46, // Skip to: 19091 /* 7081 */ MCD_OPC_Decode, 204, 20, 145, 2, // Opcode: VSTRC /* 7086 */ MCD_OPC_FilterValue, 140, 1, 15, 0, // Skip to: 7106 /* 7091 */ MCD_OPC_CheckPredicate, 22, 220, 46, // Skip to: 19091 /* 7095 */ MCD_OPC_CheckField, 16, 12, 0, 214, 46, // Skip to: 19091 /* 7101 */ MCD_OPC_Decode, 255, 19, 146, 2, // Opcode: VPERM /* 7106 */ MCD_OPC_FilterValue, 141, 1, 15, 0, // Skip to: 7126 /* 7111 */ MCD_OPC_CheckPredicate, 22, 200, 46, // Skip to: 19091 /* 7115 */ MCD_OPC_CheckField, 16, 12, 0, 194, 46, // Skip to: 19091 /* 7121 */ MCD_OPC_Decode, 183, 20, 146, 2, // Opcode: VSEL /* 7126 */ MCD_OPC_FilterValue, 142, 1, 104, 0, // Skip to: 7235 /* 7131 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7134 */ MCD_OPC_FilterValue, 0, 177, 46, // Skip to: 19091 /* 7138 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 7141 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7174 /* 7145 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7148 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7161 /* 7152 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7226 /* 7156 */ MCD_OPC_Decode, 188, 18, 146, 2, // Opcode: VFMSSB /* 7161 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7226 /* 7165 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7226 /* 7169 */ MCD_OPC_Decode, 203, 21, 147, 2, // Opcode: WFMSSB /* 7174 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7207 /* 7178 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7194 /* 7185 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7226 /* 7189 */ MCD_OPC_Decode, 187, 18, 146, 2, // Opcode: VFMSDB /* 7194 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7226 /* 7198 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7226 /* 7202 */ MCD_OPC_Decode, 202, 21, 148, 2, // Opcode: WFMSDB /* 7207 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7226 /* 7211 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7226 /* 7215 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7226 /* 7221 */ MCD_OPC_Decode, 204, 21, 146, 2, // Opcode: WFMSXB /* 7226 */ MCD_OPC_CheckPredicate, 22, 85, 46, // Skip to: 19091 /* 7230 */ MCD_OPC_Decode, 185, 18, 149, 2, // Opcode: VFMS /* 7235 */ MCD_OPC_FilterValue, 143, 1, 104, 0, // Skip to: 7344 /* 7240 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7243 */ MCD_OPC_FilterValue, 0, 68, 46, // Skip to: 19091 /* 7247 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 7250 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7283 /* 7254 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7257 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7270 /* 7261 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7335 /* 7265 */ MCD_OPC_Decode, 177, 18, 146, 2, // Opcode: VFMASB /* 7270 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7335 /* 7274 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7335 /* 7278 */ MCD_OPC_Decode, 192, 21, 147, 2, // Opcode: WFMASB /* 7283 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7316 /* 7287 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7290 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7303 /* 7294 */ MCD_OPC_CheckPredicate, 22, 37, 0, // Skip to: 7335 /* 7298 */ MCD_OPC_Decode, 176, 18, 146, 2, // Opcode: VFMADB /* 7303 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7335 /* 7307 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 7335 /* 7311 */ MCD_OPC_Decode, 191, 21, 148, 2, // Opcode: WFMADB /* 7316 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7335 /* 7320 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7335 /* 7324 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7335 /* 7330 */ MCD_OPC_Decode, 193, 21, 146, 2, // Opcode: WFMAXB /* 7335 */ MCD_OPC_CheckPredicate, 22, 232, 45, // Skip to: 19091 /* 7339 */ MCD_OPC_Decode, 175, 18, 149, 2, // Opcode: VFMA /* 7344 */ MCD_OPC_FilterValue, 148, 1, 65, 0, // Skip to: 7414 /* 7349 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 7352 */ MCD_OPC_FilterValue, 0, 215, 45, // Skip to: 19091 /* 7356 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 7359 */ MCD_OPC_FilterValue, 0, 208, 45, // Skip to: 19091 /* 7363 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7366 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7379 /* 7370 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7405 /* 7374 */ MCD_OPC_Decode, 131, 20, 130, 2, // Opcode: VPKH /* 7379 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7392 /* 7383 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7405 /* 7387 */ MCD_OPC_Decode, 129, 20, 130, 2, // Opcode: VPKF /* 7392 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7405 /* 7396 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7405 /* 7400 */ MCD_OPC_Decode, 130, 20, 130, 2, // Opcode: VPKG /* 7405 */ MCD_OPC_CheckPredicate, 22, 162, 45, // Skip to: 19091 /* 7409 */ MCD_OPC_Decode, 128, 20, 131, 2, // Opcode: VPK /* 7414 */ MCD_OPC_FilterValue, 149, 1, 132, 0, // Skip to: 7551 /* 7419 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 7422 */ MCD_OPC_FilterValue, 0, 145, 45, // Skip to: 19091 /* 7426 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7429 */ MCD_OPC_FilterValue, 0, 138, 45, // Skip to: 19091 /* 7433 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 7436 */ MCD_OPC_FilterValue, 0, 131, 45, // Skip to: 19091 /* 7440 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7443 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7476 /* 7447 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7450 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7463 /* 7454 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7542 /* 7458 */ MCD_OPC_Decode, 137, 20, 130, 2, // Opcode: VPKLSH /* 7463 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7542 /* 7467 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7542 /* 7471 */ MCD_OPC_Decode, 138, 20, 130, 2, // Opcode: VPKLSHS /* 7476 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7509 /* 7480 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7483 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7496 /* 7487 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7542 /* 7491 */ MCD_OPC_Decode, 133, 20, 130, 2, // Opcode: VPKLSF /* 7496 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7542 /* 7500 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7542 /* 7504 */ MCD_OPC_Decode, 134, 20, 130, 2, // Opcode: VPKLSFS /* 7509 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7542 /* 7513 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7516 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7529 /* 7520 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7542 /* 7524 */ MCD_OPC_Decode, 135, 20, 130, 2, // Opcode: VPKLSG /* 7529 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7542 /* 7533 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7542 /* 7537 */ MCD_OPC_Decode, 136, 20, 130, 2, // Opcode: VPKLSGS /* 7542 */ MCD_OPC_CheckPredicate, 22, 25, 45, // Skip to: 19091 /* 7546 */ MCD_OPC_Decode, 132, 20, 137, 2, // Opcode: VPKLS /* 7551 */ MCD_OPC_FilterValue, 151, 1, 132, 0, // Skip to: 7688 /* 7556 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 7559 */ MCD_OPC_FilterValue, 0, 8, 45, // Skip to: 19091 /* 7563 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7566 */ MCD_OPC_FilterValue, 0, 1, 45, // Skip to: 19091 /* 7570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 7573 */ MCD_OPC_FilterValue, 0, 250, 44, // Skip to: 19091 /* 7577 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7580 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7613 /* 7584 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7587 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7600 /* 7591 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 7679 /* 7595 */ MCD_OPC_Decode, 144, 20, 130, 2, // Opcode: VPKSH /* 7600 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 7679 /* 7604 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 7679 /* 7608 */ MCD_OPC_Decode, 145, 20, 130, 2, // Opcode: VPKSHS /* 7613 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7646 /* 7617 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7620 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7633 /* 7624 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 7679 /* 7628 */ MCD_OPC_Decode, 140, 20, 130, 2, // Opcode: VPKSF /* 7633 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 7679 /* 7637 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 7679 /* 7641 */ MCD_OPC_Decode, 141, 20, 130, 2, // Opcode: VPKSFS /* 7646 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7679 /* 7650 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7653 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7666 /* 7657 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7679 /* 7661 */ MCD_OPC_Decode, 142, 20, 130, 2, // Opcode: VPKSG /* 7666 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7679 /* 7670 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7679 /* 7674 */ MCD_OPC_Decode, 143, 20, 130, 2, // Opcode: VPKSGS /* 7679 */ MCD_OPC_CheckPredicate, 22, 144, 44, // Skip to: 19091 /* 7683 */ MCD_OPC_Decode, 139, 20, 137, 2, // Opcode: VPKS /* 7688 */ MCD_OPC_FilterValue, 158, 1, 104, 0, // Skip to: 7797 /* 7693 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7696 */ MCD_OPC_FilterValue, 0, 127, 44, // Skip to: 19091 /* 7700 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 7703 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7736 /* 7707 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7710 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7723 /* 7714 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7788 /* 7718 */ MCD_OPC_Decode, 194, 18, 146, 2, // Opcode: VFNMSSB /* 7723 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7788 /* 7727 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7788 /* 7731 */ MCD_OPC_Decode, 210, 21, 147, 2, // Opcode: WFNMSSB /* 7736 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7769 /* 7740 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7743 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7756 /* 7747 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7788 /* 7751 */ MCD_OPC_Decode, 193, 18, 146, 2, // Opcode: VFNMSDB /* 7756 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7788 /* 7760 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7788 /* 7764 */ MCD_OPC_Decode, 209, 21, 148, 2, // Opcode: WFNMSDB /* 7769 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7788 /* 7773 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7788 /* 7777 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7788 /* 7783 */ MCD_OPC_Decode, 211, 21, 146, 2, // Opcode: WFNMSXB /* 7788 */ MCD_OPC_CheckPredicate, 23, 35, 44, // Skip to: 19091 /* 7792 */ MCD_OPC_Decode, 192, 18, 149, 2, // Opcode: VFNMS /* 7797 */ MCD_OPC_FilterValue, 159, 1, 104, 0, // Skip to: 7906 /* 7802 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 7805 */ MCD_OPC_FilterValue, 0, 18, 44, // Skip to: 19091 /* 7809 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 7812 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 7845 /* 7816 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7819 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7832 /* 7823 */ MCD_OPC_CheckPredicate, 23, 70, 0, // Skip to: 7897 /* 7827 */ MCD_OPC_Decode, 191, 18, 146, 2, // Opcode: VFNMASB /* 7832 */ MCD_OPC_FilterValue, 8, 61, 0, // Skip to: 7897 /* 7836 */ MCD_OPC_CheckPredicate, 23, 57, 0, // Skip to: 7897 /* 7840 */ MCD_OPC_Decode, 207, 21, 147, 2, // Opcode: WFNMASB /* 7845 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 7878 /* 7849 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 7852 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7865 /* 7856 */ MCD_OPC_CheckPredicate, 23, 37, 0, // Skip to: 7897 /* 7860 */ MCD_OPC_Decode, 190, 18, 146, 2, // Opcode: VFNMADB /* 7865 */ MCD_OPC_FilterValue, 8, 28, 0, // Skip to: 7897 /* 7869 */ MCD_OPC_CheckPredicate, 23, 24, 0, // Skip to: 7897 /* 7873 */ MCD_OPC_Decode, 206, 21, 148, 2, // Opcode: WFNMADB /* 7878 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 7897 /* 7882 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 7897 /* 7886 */ MCD_OPC_CheckField, 16, 4, 8, 5, 0, // Skip to: 7897 /* 7892 */ MCD_OPC_Decode, 208, 21, 146, 2, // Opcode: WFNMAXB /* 7897 */ MCD_OPC_CheckPredicate, 23, 182, 43, // Skip to: 19091 /* 7901 */ MCD_OPC_Decode, 189, 18, 149, 2, // Opcode: VFNMA /* 7906 */ MCD_OPC_FilterValue, 161, 1, 65, 0, // Skip to: 7976 /* 7911 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 7914 */ MCD_OPC_FilterValue, 0, 165, 43, // Skip to: 19091 /* 7918 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 7921 */ MCD_OPC_FilterValue, 0, 158, 43, // Skip to: 19091 /* 7925 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7928 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7941 /* 7932 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 7967 /* 7936 */ MCD_OPC_Decode, 200, 19, 130, 2, // Opcode: VMLHB /* 7941 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7954 /* 7945 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 7967 /* 7949 */ MCD_OPC_Decode, 202, 19, 130, 2, // Opcode: VMLHH /* 7954 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7967 /* 7958 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 7967 /* 7962 */ MCD_OPC_Decode, 201, 19, 130, 2, // Opcode: VMLHF /* 7967 */ MCD_OPC_CheckPredicate, 22, 112, 43, // Skip to: 19091 /* 7971 */ MCD_OPC_Decode, 199, 19, 131, 2, // Opcode: VMLH /* 7976 */ MCD_OPC_FilterValue, 162, 1, 65, 0, // Skip to: 8046 /* 7981 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 7984 */ MCD_OPC_FilterValue, 0, 95, 43, // Skip to: 19091 /* 7988 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 7991 */ MCD_OPC_FilterValue, 0, 88, 43, // Skip to: 19091 /* 7995 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 7998 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8011 /* 8002 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8037 /* 8006 */ MCD_OPC_Decode, 193, 19, 130, 2, // Opcode: VMLB /* 8011 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8024 /* 8015 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8037 /* 8019 */ MCD_OPC_Decode, 203, 19, 130, 2, // Opcode: VMLHW /* 8024 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8037 /* 8028 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8037 /* 8032 */ MCD_OPC_Decode, 198, 19, 130, 2, // Opcode: VMLF /* 8037 */ MCD_OPC_CheckPredicate, 22, 42, 43, // Skip to: 19091 /* 8041 */ MCD_OPC_Decode, 192, 19, 131, 2, // Opcode: VML /* 8046 */ MCD_OPC_FilterValue, 163, 1, 65, 0, // Skip to: 8116 /* 8051 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 8054 */ MCD_OPC_FilterValue, 0, 25, 43, // Skip to: 19091 /* 8058 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 8061 */ MCD_OPC_FilterValue, 0, 18, 43, // Skip to: 19091 /* 8065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8068 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8081 /* 8072 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8107 /* 8076 */ MCD_OPC_Decode, 189, 19, 130, 2, // Opcode: VMHB /* 8081 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8094 /* 8085 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8107 /* 8089 */ MCD_OPC_Decode, 191, 19, 130, 2, // Opcode: VMHH /* 8094 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8107 /* 8098 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8107 /* 8102 */ MCD_OPC_Decode, 190, 19, 130, 2, // Opcode: VMHF /* 8107 */ MCD_OPC_CheckPredicate, 22, 228, 42, // Skip to: 19091 /* 8111 */ MCD_OPC_Decode, 188, 19, 131, 2, // Opcode: VMH /* 8116 */ MCD_OPC_FilterValue, 164, 1, 65, 0, // Skip to: 8186 /* 8121 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 8124 */ MCD_OPC_FilterValue, 0, 211, 42, // Skip to: 19091 /* 8128 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 8131 */ MCD_OPC_FilterValue, 0, 204, 42, // Skip to: 19091 /* 8135 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8138 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8151 /* 8142 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8177 /* 8146 */ MCD_OPC_Decode, 195, 19, 130, 2, // Opcode: VMLEB /* 8151 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8164 /* 8155 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8177 /* 8159 */ MCD_OPC_Decode, 197, 19, 130, 2, // Opcode: VMLEH /* 8164 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8177 /* 8168 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8177 /* 8172 */ MCD_OPC_Decode, 196, 19, 130, 2, // Opcode: VMLEF /* 8177 */ MCD_OPC_CheckPredicate, 22, 158, 42, // Skip to: 19091 /* 8181 */ MCD_OPC_Decode, 194, 19, 131, 2, // Opcode: VMLE /* 8186 */ MCD_OPC_FilterValue, 165, 1, 65, 0, // Skip to: 8256 /* 8191 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 8194 */ MCD_OPC_FilterValue, 0, 141, 42, // Skip to: 19091 /* 8198 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 8201 */ MCD_OPC_FilterValue, 0, 134, 42, // Skip to: 19091 /* 8205 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8208 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8221 /* 8212 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8247 /* 8216 */ MCD_OPC_Decode, 205, 19, 130, 2, // Opcode: VMLOB /* 8221 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8234 /* 8225 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8247 /* 8229 */ MCD_OPC_Decode, 207, 19, 130, 2, // Opcode: VMLOH /* 8234 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8247 /* 8238 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8247 /* 8242 */ MCD_OPC_Decode, 206, 19, 130, 2, // Opcode: VMLOF /* 8247 */ MCD_OPC_CheckPredicate, 22, 88, 42, // Skip to: 19091 /* 8251 */ MCD_OPC_Decode, 204, 19, 131, 2, // Opcode: VMLO /* 8256 */ MCD_OPC_FilterValue, 166, 1, 65, 0, // Skip to: 8326 /* 8261 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 8264 */ MCD_OPC_FilterValue, 0, 71, 42, // Skip to: 19091 /* 8268 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 8271 */ MCD_OPC_FilterValue, 0, 64, 42, // Skip to: 19091 /* 8275 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8278 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8291 /* 8282 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8317 /* 8286 */ MCD_OPC_Decode, 185, 19, 130, 2, // Opcode: VMEB /* 8291 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8304 /* 8295 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8317 /* 8299 */ MCD_OPC_Decode, 187, 19, 130, 2, // Opcode: VMEH /* 8304 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8317 /* 8308 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8317 /* 8312 */ MCD_OPC_Decode, 186, 19, 130, 2, // Opcode: VMEF /* 8317 */ MCD_OPC_CheckPredicate, 22, 18, 42, // Skip to: 19091 /* 8321 */ MCD_OPC_Decode, 184, 19, 131, 2, // Opcode: VME /* 8326 */ MCD_OPC_FilterValue, 167, 1, 65, 0, // Skip to: 8396 /* 8331 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 8334 */ MCD_OPC_FilterValue, 0, 1, 42, // Skip to: 19091 /* 8338 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 8341 */ MCD_OPC_FilterValue, 0, 250, 41, // Skip to: 19091 /* 8345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8348 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8361 /* 8352 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8387 /* 8356 */ MCD_OPC_Decode, 219, 19, 130, 2, // Opcode: VMOB /* 8361 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8374 /* 8365 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8387 /* 8369 */ MCD_OPC_Decode, 221, 19, 130, 2, // Opcode: VMOH /* 8374 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8387 /* 8378 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8387 /* 8382 */ MCD_OPC_Decode, 220, 19, 130, 2, // Opcode: VMOF /* 8387 */ MCD_OPC_CheckPredicate, 22, 204, 41, // Skip to: 19091 /* 8391 */ MCD_OPC_Decode, 218, 19, 131, 2, // Opcode: VMO /* 8396 */ MCD_OPC_FilterValue, 169, 1, 58, 0, // Skip to: 8459 /* 8401 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8404 */ MCD_OPC_FilterValue, 0, 187, 41, // Skip to: 19091 /* 8408 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8411 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8424 /* 8415 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8450 /* 8419 */ MCD_OPC_Decode, 172, 19, 146, 2, // Opcode: VMALHB /* 8424 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8437 /* 8428 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8450 /* 8432 */ MCD_OPC_Decode, 174, 19, 146, 2, // Opcode: VMALHH /* 8437 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8450 /* 8441 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8450 /* 8445 */ MCD_OPC_Decode, 173, 19, 146, 2, // Opcode: VMALHF /* 8450 */ MCD_OPC_CheckPredicate, 22, 141, 41, // Skip to: 19091 /* 8454 */ MCD_OPC_Decode, 171, 19, 150, 2, // Opcode: VMALH /* 8459 */ MCD_OPC_FilterValue, 170, 1, 58, 0, // Skip to: 8522 /* 8464 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8467 */ MCD_OPC_FilterValue, 0, 124, 41, // Skip to: 19091 /* 8471 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8474 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8487 /* 8478 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8513 /* 8482 */ MCD_OPC_Decode, 165, 19, 146, 2, // Opcode: VMALB /* 8487 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8500 /* 8491 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8513 /* 8495 */ MCD_OPC_Decode, 175, 19, 146, 2, // Opcode: VMALHW /* 8500 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8513 /* 8504 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8513 /* 8508 */ MCD_OPC_Decode, 170, 19, 146, 2, // Opcode: VMALF /* 8513 */ MCD_OPC_CheckPredicate, 22, 78, 41, // Skip to: 19091 /* 8517 */ MCD_OPC_Decode, 164, 19, 150, 2, // Opcode: VMAL /* 8522 */ MCD_OPC_FilterValue, 171, 1, 58, 0, // Skip to: 8585 /* 8527 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8530 */ MCD_OPC_FilterValue, 0, 61, 41, // Skip to: 19091 /* 8534 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8537 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8550 /* 8541 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8576 /* 8545 */ MCD_OPC_Decode, 161, 19, 146, 2, // Opcode: VMAHB /* 8550 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8563 /* 8554 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8576 /* 8558 */ MCD_OPC_Decode, 163, 19, 146, 2, // Opcode: VMAHH /* 8563 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8576 /* 8567 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8576 /* 8571 */ MCD_OPC_Decode, 162, 19, 146, 2, // Opcode: VMAHF /* 8576 */ MCD_OPC_CheckPredicate, 22, 15, 41, // Skip to: 19091 /* 8580 */ MCD_OPC_Decode, 160, 19, 150, 2, // Opcode: VMAH /* 8585 */ MCD_OPC_FilterValue, 172, 1, 58, 0, // Skip to: 8648 /* 8590 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8593 */ MCD_OPC_FilterValue, 0, 254, 40, // Skip to: 19091 /* 8597 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8600 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8613 /* 8604 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8639 /* 8608 */ MCD_OPC_Decode, 167, 19, 146, 2, // Opcode: VMALEB /* 8613 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8626 /* 8617 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8639 /* 8621 */ MCD_OPC_Decode, 169, 19, 146, 2, // Opcode: VMALEH /* 8626 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8639 /* 8630 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8639 /* 8634 */ MCD_OPC_Decode, 168, 19, 146, 2, // Opcode: VMALEF /* 8639 */ MCD_OPC_CheckPredicate, 22, 208, 40, // Skip to: 19091 /* 8643 */ MCD_OPC_Decode, 166, 19, 150, 2, // Opcode: VMALE /* 8648 */ MCD_OPC_FilterValue, 173, 1, 58, 0, // Skip to: 8711 /* 8653 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8656 */ MCD_OPC_FilterValue, 0, 191, 40, // Skip to: 19091 /* 8660 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8663 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8676 /* 8667 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8702 /* 8671 */ MCD_OPC_Decode, 177, 19, 146, 2, // Opcode: VMALOB /* 8676 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8689 /* 8680 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8702 /* 8684 */ MCD_OPC_Decode, 179, 19, 146, 2, // Opcode: VMALOH /* 8689 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8702 /* 8693 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8702 /* 8697 */ MCD_OPC_Decode, 178, 19, 146, 2, // Opcode: VMALOF /* 8702 */ MCD_OPC_CheckPredicate, 22, 145, 40, // Skip to: 19091 /* 8706 */ MCD_OPC_Decode, 176, 19, 150, 2, // Opcode: VMALO /* 8711 */ MCD_OPC_FilterValue, 174, 1, 58, 0, // Skip to: 8774 /* 8716 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8719 */ MCD_OPC_FilterValue, 0, 128, 40, // Skip to: 19091 /* 8723 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8726 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8739 /* 8730 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8765 /* 8734 */ MCD_OPC_Decode, 157, 19, 146, 2, // Opcode: VMAEB /* 8739 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8752 /* 8743 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8765 /* 8747 */ MCD_OPC_Decode, 159, 19, 146, 2, // Opcode: VMAEH /* 8752 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8765 /* 8756 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8765 /* 8760 */ MCD_OPC_Decode, 158, 19, 146, 2, // Opcode: VMAEF /* 8765 */ MCD_OPC_CheckPredicate, 22, 82, 40, // Skip to: 19091 /* 8769 */ MCD_OPC_Decode, 156, 19, 150, 2, // Opcode: VMAE /* 8774 */ MCD_OPC_FilterValue, 175, 1, 58, 0, // Skip to: 8837 /* 8779 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8782 */ MCD_OPC_FilterValue, 0, 65, 40, // Skip to: 19091 /* 8786 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 8789 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8802 /* 8793 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8828 /* 8797 */ MCD_OPC_Decode, 181, 19, 146, 2, // Opcode: VMAOB /* 8802 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8815 /* 8806 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8828 /* 8810 */ MCD_OPC_Decode, 183, 19, 146, 2, // Opcode: VMAOH /* 8815 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8828 /* 8819 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8828 /* 8823 */ MCD_OPC_Decode, 182, 19, 146, 2, // Opcode: VMAOF /* 8828 */ MCD_OPC_CheckPredicate, 22, 19, 40, // Skip to: 19091 /* 8832 */ MCD_OPC_Decode, 180, 19, 150, 2, // Opcode: VMAO /* 8837 */ MCD_OPC_FilterValue, 180, 1, 78, 0, // Skip to: 8920 /* 8842 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 8845 */ MCD_OPC_FilterValue, 0, 2, 40, // Skip to: 19091 /* 8849 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 8852 */ MCD_OPC_FilterValue, 0, 251, 39, // Skip to: 19091 /* 8856 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 8859 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8872 /* 8863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 8911 /* 8867 */ MCD_OPC_Decode, 216, 18, 130, 2, // Opcode: VGFMB /* 8872 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 8885 /* 8876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 8911 /* 8880 */ MCD_OPC_Decode, 219, 18, 130, 2, // Opcode: VGFMH /* 8885 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 8898 /* 8889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 8911 /* 8893 */ MCD_OPC_Decode, 217, 18, 130, 2, // Opcode: VGFMF /* 8898 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 8911 /* 8902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 8911 /* 8906 */ MCD_OPC_Decode, 218, 18, 130, 2, // Opcode: VGFMG /* 8911 */ MCD_OPC_CheckPredicate, 22, 192, 39, // Skip to: 19091 /* 8915 */ MCD_OPC_Decode, 210, 18, 131, 2, // Opcode: VGFM /* 8920 */ MCD_OPC_FilterValue, 184, 1, 31, 0, // Skip to: 8956 /* 8925 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 8928 */ MCD_OPC_FilterValue, 0, 175, 39, // Skip to: 19091 /* 8932 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 8947 /* 8936 */ MCD_OPC_CheckField, 24, 4, 3, 5, 0, // Skip to: 8947 /* 8942 */ MCD_OPC_Decode, 234, 19, 144, 2, // Opcode: VMSLG /* 8947 */ MCD_OPC_CheckPredicate, 23, 156, 39, // Skip to: 19091 /* 8951 */ MCD_OPC_Decode, 233, 19, 145, 2, // Opcode: VMSL /* 8956 */ MCD_OPC_FilterValue, 185, 1, 31, 0, // Skip to: 8992 /* 8961 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 8964 */ MCD_OPC_FilterValue, 0, 139, 39, // Skip to: 19091 /* 8968 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 8983 /* 8972 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 8983 /* 8978 */ MCD_OPC_Decode, 216, 16, 146, 2, // Opcode: VACCCQ /* 8983 */ MCD_OPC_CheckPredicate, 22, 120, 39, // Skip to: 19091 /* 8987 */ MCD_OPC_Decode, 215, 16, 150, 2, // Opcode: VACCC /* 8992 */ MCD_OPC_FilterValue, 187, 1, 31, 0, // Skip to: 9028 /* 8997 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 9000 */ MCD_OPC_FilterValue, 0, 103, 39, // Skip to: 19091 /* 9004 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9019 /* 9008 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9019 /* 9014 */ MCD_OPC_Decode, 221, 16, 146, 2, // Opcode: VACQ /* 9019 */ MCD_OPC_CheckPredicate, 22, 84, 39, // Skip to: 19091 /* 9023 */ MCD_OPC_Decode, 212, 16, 150, 2, // Opcode: VAC /* 9028 */ MCD_OPC_FilterValue, 188, 1, 71, 0, // Skip to: 9104 /* 9033 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 9036 */ MCD_OPC_FilterValue, 0, 67, 39, // Skip to: 19091 /* 9040 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 9043 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9056 /* 9047 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 9095 /* 9051 */ MCD_OPC_Decode, 212, 18, 146, 2, // Opcode: VGFMAB /* 9056 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9069 /* 9060 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 9095 /* 9064 */ MCD_OPC_Decode, 215, 18, 146, 2, // Opcode: VGFMAH /* 9069 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9082 /* 9073 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9095 /* 9077 */ MCD_OPC_Decode, 213, 18, 146, 2, // Opcode: VGFMAF /* 9082 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9095 /* 9086 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9095 /* 9090 */ MCD_OPC_Decode, 214, 18, 146, 2, // Opcode: VGFMAG /* 9095 */ MCD_OPC_CheckPredicate, 22, 8, 39, // Skip to: 19091 /* 9099 */ MCD_OPC_Decode, 211, 18, 150, 2, // Opcode: VGFMA /* 9104 */ MCD_OPC_FilterValue, 189, 1, 31, 0, // Skip to: 9140 /* 9109 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 9112 */ MCD_OPC_FilterValue, 0, 247, 38, // Skip to: 19091 /* 9116 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9131 /* 9120 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9131 /* 9126 */ MCD_OPC_Decode, 167, 20, 146, 2, // Opcode: VSBCBIQ /* 9131 */ MCD_OPC_CheckPredicate, 22, 228, 38, // Skip to: 19091 /* 9135 */ MCD_OPC_Decode, 166, 20, 150, 2, // Opcode: VSBCBI /* 9140 */ MCD_OPC_FilterValue, 191, 1, 31, 0, // Skip to: 9176 /* 9145 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... /* 9148 */ MCD_OPC_FilterValue, 0, 211, 38, // Skip to: 19091 /* 9152 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9167 /* 9156 */ MCD_OPC_CheckField, 24, 4, 4, 5, 0, // Skip to: 9167 /* 9162 */ MCD_OPC_Decode, 169, 20, 146, 2, // Opcode: VSBIQ /* 9167 */ MCD_OPC_CheckPredicate, 22, 192, 38, // Skip to: 19091 /* 9171 */ MCD_OPC_Decode, 168, 20, 150, 2, // Opcode: VSBI /* 9176 */ MCD_OPC_FilterValue, 192, 1, 54, 0, // Skip to: 9235 /* 9181 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9184 */ MCD_OPC_FilterValue, 0, 175, 38, // Skip to: 19091 /* 9188 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9191 */ MCD_OPC_FilterValue, 0, 168, 38, // Skip to: 19091 /* 9195 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 9198 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9226 /* 9202 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9217 /* 9206 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9217 /* 9212 */ MCD_OPC_Decode, 252, 20, 151, 2, // Opcode: WCLGDB /* 9217 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9226 /* 9221 */ MCD_OPC_Decode, 145, 17, 152, 2, // Opcode: VCLGDB /* 9226 */ MCD_OPC_CheckPredicate, 22, 133, 38, // Skip to: 19091 /* 9230 */ MCD_OPC_Decode, 144, 17, 153, 2, // Opcode: VCLGD /* 9235 */ MCD_OPC_FilterValue, 193, 1, 54, 0, // Skip to: 9294 /* 9240 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9243 */ MCD_OPC_FilterValue, 0, 116, 38, // Skip to: 19091 /* 9247 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9250 */ MCD_OPC_FilterValue, 0, 109, 38, // Skip to: 19091 /* 9254 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 9257 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9285 /* 9261 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9276 /* 9265 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9276 /* 9271 */ MCD_OPC_Decode, 250, 20, 151, 2, // Opcode: WCDLGB /* 9276 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9285 /* 9280 */ MCD_OPC_Decode, 241, 16, 152, 2, // Opcode: VCDLGB /* 9285 */ MCD_OPC_CheckPredicate, 22, 74, 38, // Skip to: 19091 /* 9289 */ MCD_OPC_Decode, 240, 16, 153, 2, // Opcode: VCDLG /* 9294 */ MCD_OPC_FilterValue, 194, 1, 54, 0, // Skip to: 9353 /* 9299 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9302 */ MCD_OPC_FilterValue, 0, 57, 38, // Skip to: 19091 /* 9306 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9309 */ MCD_OPC_FilterValue, 0, 50, 38, // Skip to: 19091 /* 9313 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 9316 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9344 /* 9320 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9335 /* 9324 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9335 /* 9330 */ MCD_OPC_Decode, 251, 20, 151, 2, // Opcode: WCGDB /* 9335 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9344 /* 9339 */ MCD_OPC_Decode, 252, 16, 152, 2, // Opcode: VCGDB /* 9344 */ MCD_OPC_CheckPredicate, 22, 15, 38, // Skip to: 19091 /* 9348 */ MCD_OPC_Decode, 251, 16, 153, 2, // Opcode: VCGD /* 9353 */ MCD_OPC_FilterValue, 195, 1, 54, 0, // Skip to: 9412 /* 9358 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9361 */ MCD_OPC_FilterValue, 0, 254, 37, // Skip to: 19091 /* 9365 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9368 */ MCD_OPC_FilterValue, 0, 247, 37, // Skip to: 19091 /* 9372 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 9375 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9403 /* 9379 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9394 /* 9383 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9394 /* 9389 */ MCD_OPC_Decode, 249, 20, 151, 2, // Opcode: WCDGB /* 9394 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 9403 /* 9398 */ MCD_OPC_Decode, 239, 16, 152, 2, // Opcode: VCDGB /* 9403 */ MCD_OPC_CheckPredicate, 22, 212, 37, // Skip to: 19091 /* 9407 */ MCD_OPC_Decode, 238, 16, 153, 2, // Opcode: VCDG /* 9412 */ MCD_OPC_FilterValue, 196, 1, 67, 0, // Skip to: 9484 /* 9417 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9420 */ MCD_OPC_FilterValue, 0, 195, 37, // Skip to: 19091 /* 9424 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... /* 9427 */ MCD_OPC_FilterValue, 0, 188, 37, // Skip to: 19091 /* 9431 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 9434 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9447 /* 9438 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 9475 /* 9442 */ MCD_OPC_Decode, 240, 18, 254, 1, // Opcode: VLDEB /* 9447 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9461 /* 9452 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 9475 /* 9456 */ MCD_OPC_Decode, 224, 21, 154, 2, // Opcode: WLDEB /* 9461 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9475 /* 9466 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9475 /* 9470 */ MCD_OPC_Decode, 181, 21, 155, 2, // Opcode: WFLLD /* 9475 */ MCD_OPC_CheckPredicate, 22, 140, 37, // Skip to: 19091 /* 9479 */ MCD_OPC_Decode, 239, 18, 156, 2, // Opcode: VLDE /* 9484 */ MCD_OPC_FilterValue, 197, 1, 73, 0, // Skip to: 9562 /* 9489 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9492 */ MCD_OPC_FilterValue, 0, 123, 37, // Skip to: 19091 /* 9496 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9499 */ MCD_OPC_FilterValue, 0, 116, 37, // Skip to: 19091 /* 9503 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 9506 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9534 /* 9510 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9525 /* 9514 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9525 /* 9520 */ MCD_OPC_Decode, 225, 21, 157, 2, // Opcode: WLEDB /* 9525 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9553 /* 9529 */ MCD_OPC_Decode, 243, 18, 152, 2, // Opcode: VLEDB /* 9534 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9553 /* 9538 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9553 /* 9542 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9553 /* 9548 */ MCD_OPC_Decode, 190, 21, 158, 2, // Opcode: WFLRX /* 9553 */ MCD_OPC_CheckPredicate, 22, 62, 37, // Skip to: 19091 /* 9557 */ MCD_OPC_Decode, 242, 18, 153, 2, // Opcode: VLED /* 9562 */ MCD_OPC_FilterValue, 199, 1, 101, 0, // Skip to: 9668 /* 9567 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9570 */ MCD_OPC_FilterValue, 0, 45, 37, // Skip to: 19091 /* 9574 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9577 */ MCD_OPC_FilterValue, 0, 38, 37, // Skip to: 19091 /* 9581 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 9584 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 9612 /* 9588 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9603 /* 9592 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9603 /* 9598 */ MCD_OPC_Decode, 154, 21, 159, 2, // Opcode: WFISB /* 9603 */ MCD_OPC_CheckPredicate, 23, 52, 0, // Skip to: 9659 /* 9607 */ MCD_OPC_Decode, 151, 18, 152, 2, // Opcode: VFISB /* 9612 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 9640 /* 9616 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 9631 /* 9620 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9631 /* 9626 */ MCD_OPC_Decode, 153, 21, 151, 2, // Opcode: WFIDB /* 9631 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 9659 /* 9635 */ MCD_OPC_Decode, 150, 18, 152, 2, // Opcode: VFIDB /* 9640 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 9659 /* 9644 */ MCD_OPC_CheckPredicate, 23, 11, 0, // Skip to: 9659 /* 9648 */ MCD_OPC_CheckField, 19, 1, 1, 5, 0, // Skip to: 9659 /* 9654 */ MCD_OPC_Decode, 155, 21, 160, 2, // Opcode: WFIXB /* 9659 */ MCD_OPC_CheckPredicate, 22, 212, 36, // Skip to: 19091 /* 9663 */ MCD_OPC_Decode, 149, 18, 153, 2, // Opcode: VFI /* 9668 */ MCD_OPC_FilterValue, 202, 1, 65, 0, // Skip to: 9738 /* 9673 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9676 */ MCD_OPC_FilterValue, 0, 195, 36, // Skip to: 19091 /* 9680 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... /* 9683 */ MCD_OPC_FilterValue, 0, 188, 36, // Skip to: 19091 /* 9687 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 9690 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9703 /* 9694 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9729 /* 9698 */ MCD_OPC_Decode, 176, 21, 161, 2, // Opcode: WFKSB /* 9703 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9716 /* 9707 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9729 /* 9711 */ MCD_OPC_Decode, 157, 21, 162, 2, // Opcode: WFKDB /* 9716 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9729 /* 9720 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9729 /* 9724 */ MCD_OPC_Decode, 177, 21, 254, 1, // Opcode: WFKXB /* 9729 */ MCD_OPC_CheckPredicate, 22, 142, 36, // Skip to: 19091 /* 9733 */ MCD_OPC_Decode, 156, 21, 163, 2, // Opcode: WFK /* 9738 */ MCD_OPC_FilterValue, 203, 1, 65, 0, // Skip to: 9808 /* 9743 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9746 */ MCD_OPC_FilterValue, 0, 125, 36, // Skip to: 19091 /* 9750 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... /* 9753 */ MCD_OPC_FilterValue, 0, 118, 36, // Skip to: 19091 /* 9757 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 9760 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9773 /* 9764 */ MCD_OPC_CheckPredicate, 23, 31, 0, // Skip to: 9799 /* 9768 */ MCD_OPC_Decode, 148, 21, 161, 2, // Opcode: WFCSB /* 9773 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9786 /* 9777 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 9799 /* 9781 */ MCD_OPC_Decode, 129, 21, 162, 2, // Opcode: WFCDB /* 9786 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9799 /* 9790 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 9799 /* 9794 */ MCD_OPC_Decode, 149, 21, 254, 1, // Opcode: WFCXB /* 9799 */ MCD_OPC_CheckPredicate, 22, 72, 36, // Skip to: 19091 /* 9803 */ MCD_OPC_Decode, 128, 21, 163, 2, // Opcode: WFC /* 9808 */ MCD_OPC_FilterValue, 204, 1, 49, 1, // Skip to: 10118 /* 9813 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 9816 */ MCD_OPC_FilterValue, 0, 55, 36, // Skip to: 19091 /* 9820 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... /* 9823 */ MCD_OPC_FilterValue, 0, 48, 36, // Skip to: 19091 /* 9827 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... /* 9830 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9843 /* 9834 */ MCD_OPC_CheckPredicate, 23, 200, 0, // Skip to: 10038 /* 9838 */ MCD_OPC_Decode, 165, 18, 254, 1, // Opcode: VFLCSB /* 9843 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9856 /* 9847 */ MCD_OPC_CheckPredicate, 22, 187, 0, // Skip to: 10038 /* 9851 */ MCD_OPC_Decode, 164, 18, 254, 1, // Opcode: VFLCDB /* 9856 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 9870 /* 9861 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 10038 /* 9865 */ MCD_OPC_Decode, 179, 21, 161, 2, // Opcode: WFLCSB /* 9870 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 9884 /* 9875 */ MCD_OPC_CheckPredicate, 22, 159, 0, // Skip to: 10038 /* 9879 */ MCD_OPC_Decode, 178, 21, 162, 2, // Opcode: WFLCDB /* 9884 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 9898 /* 9889 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 10038 /* 9893 */ MCD_OPC_Decode, 180, 21, 254, 1, // Opcode: WFLCXB /* 9898 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 9912 /* 9903 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 10038 /* 9907 */ MCD_OPC_Decode, 169, 18, 254, 1, // Opcode: VFLNSB /* 9912 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 9926 /* 9917 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 10038 /* 9921 */ MCD_OPC_Decode, 168, 18, 254, 1, // Opcode: VFLNDB /* 9926 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 9940 /* 9931 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 10038 /* 9935 */ MCD_OPC_Decode, 184, 21, 161, 2, // Opcode: WFLNSB /* 9940 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 9954 /* 9945 */ MCD_OPC_CheckPredicate, 22, 89, 0, // Skip to: 10038 /* 9949 */ MCD_OPC_Decode, 183, 21, 162, 2, // Opcode: WFLNDB /* 9954 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 9968 /* 9959 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 10038 /* 9963 */ MCD_OPC_Decode, 185, 21, 254, 1, // Opcode: WFLNXB /* 9968 */ MCD_OPC_FilterValue, 130, 4, 9, 0, // Skip to: 9982 /* 9973 */ MCD_OPC_CheckPredicate, 23, 61, 0, // Skip to: 10038 /* 9977 */ MCD_OPC_Decode, 171, 18, 254, 1, // Opcode: VFLPSB /* 9982 */ MCD_OPC_FilterValue, 131, 4, 9, 0, // Skip to: 9996 /* 9987 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10038 /* 9991 */ MCD_OPC_Decode, 170, 18, 254, 1, // Opcode: VFLPDB /* 9996 */ MCD_OPC_FilterValue, 130, 5, 9, 0, // Skip to: 10010 /* 10001 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10038 /* 10005 */ MCD_OPC_Decode, 187, 21, 161, 2, // Opcode: WFLPSB /* 10010 */ MCD_OPC_FilterValue, 131, 5, 9, 0, // Skip to: 10024 /* 10015 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10038 /* 10019 */ MCD_OPC_Decode, 186, 21, 162, 2, // Opcode: WFLPDB /* 10024 */ MCD_OPC_FilterValue, 132, 5, 9, 0, // Skip to: 10038 /* 10029 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10038 /* 10033 */ MCD_OPC_Decode, 188, 21, 254, 1, // Opcode: WFLPXB /* 10038 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 10041 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10054 /* 10045 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10109 /* 10049 */ MCD_OPC_Decode, 197, 18, 128, 2, // Opcode: VFPSOSB /* 10054 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10067 /* 10058 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10109 /* 10062 */ MCD_OPC_Decode, 196, 18, 128, 2, // Opcode: VFPSODB /* 10067 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10081 /* 10072 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10109 /* 10076 */ MCD_OPC_Decode, 213, 21, 164, 2, // Opcode: WFPSOSB /* 10081 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10095 /* 10086 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10109 /* 10090 */ MCD_OPC_Decode, 212, 21, 165, 2, // Opcode: WFPSODB /* 10095 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10109 /* 10100 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10109 /* 10104 */ MCD_OPC_Decode, 214, 21, 128, 2, // Opcode: WFPSOXB /* 10109 */ MCD_OPC_CheckPredicate, 22, 18, 35, // Skip to: 19091 /* 10113 */ MCD_OPC_Decode, 195, 18, 153, 2, // Opcode: VFPSO /* 10118 */ MCD_OPC_FilterValue, 206, 1, 94, 0, // Skip to: 10217 /* 10123 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10126 */ MCD_OPC_FilterValue, 0, 1, 35, // Skip to: 19091 /* 10130 */ MCD_OPC_ExtractField, 20, 12, // Inst{31-20} ... /* 10133 */ MCD_OPC_FilterValue, 0, 250, 34, // Skip to: 19091 /* 10137 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 10140 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10153 /* 10144 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10208 /* 10148 */ MCD_OPC_Decode, 202, 18, 254, 1, // Opcode: VFSQSB /* 10153 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10166 /* 10157 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10208 /* 10161 */ MCD_OPC_Decode, 201, 18, 254, 1, // Opcode: VFSQDB /* 10166 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10180 /* 10171 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10208 /* 10175 */ MCD_OPC_Decode, 217, 21, 161, 2, // Opcode: WFSQSB /* 10180 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10194 /* 10185 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10208 /* 10189 */ MCD_OPC_Decode, 216, 21, 162, 2, // Opcode: WFSQDB /* 10194 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10208 /* 10199 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10208 /* 10203 */ MCD_OPC_Decode, 218, 21, 254, 1, // Opcode: WFSQXB /* 10208 */ MCD_OPC_CheckPredicate, 22, 175, 34, // Skip to: 19091 /* 10212 */ MCD_OPC_Decode, 200, 18, 156, 2, // Opcode: VFSQ /* 10217 */ MCD_OPC_FilterValue, 212, 1, 65, 0, // Skip to: 10287 /* 10222 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10225 */ MCD_OPC_FilterValue, 0, 158, 34, // Skip to: 19091 /* 10229 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10232 */ MCD_OPC_FilterValue, 0, 151, 34, // Skip to: 19091 /* 10236 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10239 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10252 /* 10243 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10278 /* 10247 */ MCD_OPC_Decode, 244, 20, 254, 1, // Opcode: VUPLLB /* 10252 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10265 /* 10256 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10278 /* 10260 */ MCD_OPC_Decode, 246, 20, 254, 1, // Opcode: VUPLLH /* 10265 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10278 /* 10269 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10278 /* 10273 */ MCD_OPC_Decode, 245, 20, 254, 1, // Opcode: VUPLLF /* 10278 */ MCD_OPC_CheckPredicate, 22, 105, 34, // Skip to: 19091 /* 10282 */ MCD_OPC_Decode, 243, 20, 255, 1, // Opcode: VUPLL /* 10287 */ MCD_OPC_FilterValue, 213, 1, 65, 0, // Skip to: 10357 /* 10292 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10295 */ MCD_OPC_FilterValue, 0, 88, 34, // Skip to: 19091 /* 10299 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10302 */ MCD_OPC_FilterValue, 0, 81, 34, // Skip to: 19091 /* 10306 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10309 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10322 /* 10313 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10348 /* 10317 */ MCD_OPC_Decode, 239, 20, 254, 1, // Opcode: VUPLHB /* 10322 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10335 /* 10326 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10348 /* 10330 */ MCD_OPC_Decode, 241, 20, 254, 1, // Opcode: VUPLHH /* 10335 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10348 /* 10339 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10348 /* 10343 */ MCD_OPC_Decode, 240, 20, 254, 1, // Opcode: VUPLHF /* 10348 */ MCD_OPC_CheckPredicate, 22, 35, 34, // Skip to: 19091 /* 10352 */ MCD_OPC_Decode, 238, 20, 255, 1, // Opcode: VUPLH /* 10357 */ MCD_OPC_FilterValue, 214, 1, 65, 0, // Skip to: 10427 /* 10362 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10365 */ MCD_OPC_FilterValue, 0, 18, 34, // Skip to: 19091 /* 10369 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10372 */ MCD_OPC_FilterValue, 0, 11, 34, // Skip to: 19091 /* 10376 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10379 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10392 /* 10383 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10418 /* 10387 */ MCD_OPC_Decode, 236, 20, 254, 1, // Opcode: VUPLB /* 10392 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10405 /* 10396 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10418 /* 10400 */ MCD_OPC_Decode, 242, 20, 254, 1, // Opcode: VUPLHW /* 10405 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10418 /* 10409 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10418 /* 10413 */ MCD_OPC_Decode, 237, 20, 254, 1, // Opcode: VUPLF /* 10418 */ MCD_OPC_CheckPredicate, 22, 221, 33, // Skip to: 19091 /* 10422 */ MCD_OPC_Decode, 235, 20, 255, 1, // Opcode: VUPL /* 10427 */ MCD_OPC_FilterValue, 215, 1, 65, 0, // Skip to: 10497 /* 10432 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10435 */ MCD_OPC_FilterValue, 0, 204, 33, // Skip to: 19091 /* 10439 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10442 */ MCD_OPC_FilterValue, 0, 197, 33, // Skip to: 19091 /* 10446 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10449 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10462 /* 10453 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10488 /* 10457 */ MCD_OPC_Decode, 231, 20, 254, 1, // Opcode: VUPHB /* 10462 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10475 /* 10466 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10488 /* 10470 */ MCD_OPC_Decode, 233, 20, 254, 1, // Opcode: VUPHH /* 10475 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10488 /* 10479 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10488 /* 10483 */ MCD_OPC_Decode, 232, 20, 254, 1, // Opcode: VUPHF /* 10488 */ MCD_OPC_CheckPredicate, 22, 151, 33, // Skip to: 19091 /* 10492 */ MCD_OPC_Decode, 230, 20, 255, 1, // Opcode: VUPH /* 10497 */ MCD_OPC_FilterValue, 216, 1, 21, 0, // Skip to: 10523 /* 10502 */ MCD_OPC_CheckPredicate, 22, 137, 33, // Skip to: 19091 /* 10506 */ MCD_OPC_CheckField, 12, 20, 0, 131, 33, // Skip to: 19091 /* 10512 */ MCD_OPC_CheckField, 8, 2, 0, 125, 33, // Skip to: 19091 /* 10518 */ MCD_OPC_Decode, 228, 20, 254, 1, // Opcode: VTM /* 10523 */ MCD_OPC_FilterValue, 217, 1, 78, 0, // Skip to: 10606 /* 10528 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10531 */ MCD_OPC_FilterValue, 0, 108, 33, // Skip to: 19091 /* 10535 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10538 */ MCD_OPC_FilterValue, 0, 101, 33, // Skip to: 19091 /* 10542 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10545 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10558 /* 10549 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10597 /* 10553 */ MCD_OPC_Decode, 168, 17, 254, 1, // Opcode: VECLB /* 10558 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10571 /* 10562 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10597 /* 10566 */ MCD_OPC_Decode, 171, 17, 254, 1, // Opcode: VECLH /* 10571 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10584 /* 10575 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10597 /* 10579 */ MCD_OPC_Decode, 169, 17, 254, 1, // Opcode: VECLF /* 10584 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10597 /* 10588 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10597 /* 10592 */ MCD_OPC_Decode, 170, 17, 254, 1, // Opcode: VECLG /* 10597 */ MCD_OPC_CheckPredicate, 22, 42, 33, // Skip to: 19091 /* 10601 */ MCD_OPC_Decode, 167, 17, 255, 1, // Opcode: VECL /* 10606 */ MCD_OPC_FilterValue, 219, 1, 78, 0, // Skip to: 10689 /* 10611 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10614 */ MCD_OPC_FilterValue, 0, 25, 33, // Skip to: 19091 /* 10618 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10621 */ MCD_OPC_FilterValue, 0, 18, 33, // Skip to: 19091 /* 10625 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10628 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10641 /* 10632 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10680 /* 10636 */ MCD_OPC_Decode, 163, 17, 254, 1, // Opcode: VECB /* 10641 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10654 /* 10645 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10680 /* 10649 */ MCD_OPC_Decode, 166, 17, 254, 1, // Opcode: VECH /* 10654 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10667 /* 10658 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10680 /* 10662 */ MCD_OPC_Decode, 164, 17, 254, 1, // Opcode: VECF /* 10667 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10680 /* 10671 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10680 /* 10675 */ MCD_OPC_Decode, 165, 17, 254, 1, // Opcode: VECG /* 10680 */ MCD_OPC_CheckPredicate, 22, 215, 32, // Skip to: 19091 /* 10684 */ MCD_OPC_Decode, 162, 17, 255, 1, // Opcode: VEC /* 10689 */ MCD_OPC_FilterValue, 222, 1, 78, 0, // Skip to: 10772 /* 10694 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10697 */ MCD_OPC_FilterValue, 0, 198, 32, // Skip to: 19091 /* 10701 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10704 */ MCD_OPC_FilterValue, 0, 191, 32, // Skip to: 19091 /* 10708 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10711 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10724 /* 10715 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10763 /* 10719 */ MCD_OPC_Decode, 235, 18, 254, 1, // Opcode: VLCB /* 10724 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10737 /* 10728 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10763 /* 10732 */ MCD_OPC_Decode, 238, 18, 254, 1, // Opcode: VLCH /* 10737 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10750 /* 10741 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10763 /* 10745 */ MCD_OPC_Decode, 236, 18, 254, 1, // Opcode: VLCF /* 10750 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10763 /* 10754 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10763 /* 10758 */ MCD_OPC_Decode, 237, 18, 254, 1, // Opcode: VLCG /* 10763 */ MCD_OPC_CheckPredicate, 22, 132, 32, // Skip to: 19091 /* 10767 */ MCD_OPC_Decode, 234, 18, 255, 1, // Opcode: VLC /* 10772 */ MCD_OPC_FilterValue, 223, 1, 78, 0, // Skip to: 10855 /* 10777 */ MCD_OPC_ExtractField, 8, 2, // Inst{9-8} ... /* 10780 */ MCD_OPC_FilterValue, 0, 115, 32, // Skip to: 19091 /* 10784 */ MCD_OPC_ExtractField, 16, 16, // Inst{31-16} ... /* 10787 */ MCD_OPC_FilterValue, 0, 108, 32, // Skip to: 19091 /* 10791 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 10794 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10807 /* 10798 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 10846 /* 10802 */ MCD_OPC_Decode, 138, 19, 254, 1, // Opcode: VLPB /* 10807 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10820 /* 10811 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 10846 /* 10815 */ MCD_OPC_Decode, 141, 19, 254, 1, // Opcode: VLPH /* 10820 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10833 /* 10824 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 10846 /* 10828 */ MCD_OPC_Decode, 139, 19, 254, 1, // Opcode: VLPF /* 10833 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10846 /* 10837 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 10846 /* 10841 */ MCD_OPC_Decode, 140, 19, 254, 1, // Opcode: VLPG /* 10846 */ MCD_OPC_CheckPredicate, 22, 49, 32, // Skip to: 19091 /* 10850 */ MCD_OPC_Decode, 137, 19, 255, 1, // Opcode: VLP /* 10855 */ MCD_OPC_FilterValue, 226, 1, 94, 0, // Skip to: 10954 /* 10860 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 10863 */ MCD_OPC_FilterValue, 0, 32, 32, // Skip to: 19091 /* 10867 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... /* 10870 */ MCD_OPC_FilterValue, 0, 25, 32, // Skip to: 19091 /* 10874 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 10877 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10890 /* 10881 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 10945 /* 10885 */ MCD_OPC_Decode, 203, 18, 130, 2, // Opcode: VFSSB /* 10890 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10903 /* 10894 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 10945 /* 10898 */ MCD_OPC_Decode, 199, 18, 130, 2, // Opcode: VFSDB /* 10903 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 10917 /* 10908 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 10945 /* 10912 */ MCD_OPC_Decode, 219, 21, 166, 2, // Opcode: WFSSB /* 10917 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 10931 /* 10922 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 10945 /* 10926 */ MCD_OPC_Decode, 215, 21, 167, 2, // Opcode: WFSDB /* 10931 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 10945 /* 10936 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 10945 /* 10940 */ MCD_OPC_Decode, 220, 21, 130, 2, // Opcode: WFSXB /* 10945 */ MCD_OPC_CheckPredicate, 22, 206, 31, // Skip to: 19091 /* 10949 */ MCD_OPC_Decode, 198, 18, 168, 2, // Opcode: VFS /* 10954 */ MCD_OPC_FilterValue, 227, 1, 94, 0, // Skip to: 11053 /* 10959 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 10962 */ MCD_OPC_FilterValue, 0, 189, 31, // Skip to: 19091 /* 10966 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... /* 10969 */ MCD_OPC_FilterValue, 0, 182, 31, // Skip to: 19091 /* 10973 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 10976 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10989 /* 10980 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11044 /* 10984 */ MCD_OPC_Decode, 232, 17, 130, 2, // Opcode: VFASB /* 10989 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11002 /* 10993 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11044 /* 10997 */ MCD_OPC_Decode, 218, 17, 130, 2, // Opcode: VFADB /* 11002 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11016 /* 11007 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11044 /* 11011 */ MCD_OPC_Decode, 254, 20, 166, 2, // Opcode: WFASB /* 11016 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11030 /* 11021 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11044 /* 11025 */ MCD_OPC_Decode, 253, 20, 167, 2, // Opcode: WFADB /* 11030 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11044 /* 11035 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11044 /* 11039 */ MCD_OPC_Decode, 255, 20, 130, 2, // Opcode: WFAXB /* 11044 */ MCD_OPC_CheckPredicate, 22, 107, 31, // Skip to: 19091 /* 11048 */ MCD_OPC_Decode, 217, 17, 168, 2, // Opcode: VFA /* 11053 */ MCD_OPC_FilterValue, 229, 1, 94, 0, // Skip to: 11152 /* 11058 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 11061 */ MCD_OPC_FilterValue, 0, 90, 31, // Skip to: 19091 /* 11065 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... /* 11068 */ MCD_OPC_FilterValue, 0, 83, 31, // Skip to: 19091 /* 11072 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 11075 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11088 /* 11079 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11143 /* 11083 */ MCD_OPC_Decode, 250, 17, 130, 2, // Opcode: VFDSB /* 11088 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11101 /* 11092 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11143 /* 11096 */ MCD_OPC_Decode, 249, 17, 130, 2, // Opcode: VFDDB /* 11101 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11115 /* 11106 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11143 /* 11110 */ MCD_OPC_Decode, 151, 21, 166, 2, // Opcode: WFDSB /* 11115 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11129 /* 11120 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11143 /* 11124 */ MCD_OPC_Decode, 150, 21, 167, 2, // Opcode: WFDDB /* 11129 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11143 /* 11134 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11143 /* 11138 */ MCD_OPC_Decode, 152, 21, 130, 2, // Opcode: WFDXB /* 11143 */ MCD_OPC_CheckPredicate, 22, 8, 31, // Skip to: 19091 /* 11147 */ MCD_OPC_Decode, 248, 17, 168, 2, // Opcode: VFD /* 11152 */ MCD_OPC_FilterValue, 231, 1, 94, 0, // Skip to: 11251 /* 11157 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 11160 */ MCD_OPC_FilterValue, 0, 247, 30, // Skip to: 19091 /* 11164 */ MCD_OPC_ExtractField, 20, 8, // Inst{27-20} ... /* 11167 */ MCD_OPC_FilterValue, 0, 240, 30, // Skip to: 19091 /* 11171 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 11174 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11187 /* 11178 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 11242 /* 11182 */ MCD_OPC_Decode, 186, 18, 130, 2, // Opcode: VFMSB /* 11187 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11200 /* 11191 */ MCD_OPC_CheckPredicate, 22, 47, 0, // Skip to: 11242 /* 11195 */ MCD_OPC_Decode, 181, 18, 130, 2, // Opcode: VFMDB /* 11200 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11214 /* 11205 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11242 /* 11209 */ MCD_OPC_Decode, 201, 21, 166, 2, // Opcode: WFMSB /* 11214 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11228 /* 11219 */ MCD_OPC_CheckPredicate, 22, 19, 0, // Skip to: 11242 /* 11223 */ MCD_OPC_Decode, 197, 21, 167, 2, // Opcode: WFMDB /* 11228 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11242 /* 11233 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11242 /* 11237 */ MCD_OPC_Decode, 205, 21, 130, 2, // Opcode: WFMXB /* 11242 */ MCD_OPC_CheckPredicate, 22, 165, 30, // Skip to: 19091 /* 11246 */ MCD_OPC_Decode, 174, 18, 168, 2, // Opcode: VFM /* 11251 */ MCD_OPC_FilterValue, 232, 1, 46, 1, // Skip to: 11558 /* 11256 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 11259 */ MCD_OPC_FilterValue, 0, 148, 30, // Skip to: 19091 /* 11263 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 11266 */ MCD_OPC_FilterValue, 0, 141, 30, // Skip to: 19091 /* 11270 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... /* 11273 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11286 /* 11277 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11549 /* 11281 */ MCD_OPC_Decode, 236, 17, 130, 2, // Opcode: VFCESB /* 11286 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11299 /* 11290 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11549 /* 11294 */ MCD_OPC_Decode, 234, 17, 130, 2, // Opcode: VFCEDB /* 11299 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11312 /* 11303 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11549 /* 11307 */ MCD_OPC_Decode, 154, 18, 130, 2, // Opcode: VFKESB /* 11312 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11325 /* 11316 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11549 /* 11320 */ MCD_OPC_Decode, 152, 18, 130, 2, // Opcode: VFKEDB /* 11325 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11339 /* 11330 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11549 /* 11334 */ MCD_OPC_Decode, 132, 21, 166, 2, // Opcode: WFCESB /* 11339 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11353 /* 11344 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11549 /* 11348 */ MCD_OPC_Decode, 130, 21, 167, 2, // Opcode: WFCEDB /* 11353 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11367 /* 11358 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11549 /* 11362 */ MCD_OPC_Decode, 134, 21, 130, 2, // Opcode: WFCEXB /* 11367 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11381 /* 11372 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11549 /* 11376 */ MCD_OPC_Decode, 160, 21, 166, 2, // Opcode: WFKESB /* 11381 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11395 /* 11386 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11549 /* 11390 */ MCD_OPC_Decode, 158, 21, 167, 2, // Opcode: WFKEDB /* 11395 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11409 /* 11400 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11549 /* 11404 */ MCD_OPC_Decode, 162, 21, 130, 2, // Opcode: WFKEXB /* 11409 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11423 /* 11414 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11549 /* 11418 */ MCD_OPC_Decode, 237, 17, 130, 2, // Opcode: VFCESBS /* 11423 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11437 /* 11428 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11549 /* 11432 */ MCD_OPC_Decode, 235, 17, 130, 2, // Opcode: VFCEDBS /* 11437 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11451 /* 11442 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11549 /* 11446 */ MCD_OPC_Decode, 155, 18, 130, 2, // Opcode: VFKESBS /* 11451 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11465 /* 11456 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11549 /* 11460 */ MCD_OPC_Decode, 153, 18, 130, 2, // Opcode: VFKEDBS /* 11465 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11479 /* 11470 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11549 /* 11474 */ MCD_OPC_Decode, 133, 21, 166, 2, // Opcode: WFCESBS /* 11479 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11493 /* 11484 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11549 /* 11488 */ MCD_OPC_Decode, 131, 21, 167, 2, // Opcode: WFCEDBS /* 11493 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11507 /* 11498 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11549 /* 11502 */ MCD_OPC_Decode, 135, 21, 130, 2, // Opcode: WFCEXBS /* 11507 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11521 /* 11512 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11549 /* 11516 */ MCD_OPC_Decode, 161, 21, 166, 2, // Opcode: WFKESBS /* 11521 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11535 /* 11526 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11549 /* 11530 */ MCD_OPC_Decode, 159, 21, 167, 2, // Opcode: WFKEDBS /* 11535 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11549 /* 11540 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11549 /* 11544 */ MCD_OPC_Decode, 163, 21, 130, 2, // Opcode: WFKEXBS /* 11549 */ MCD_OPC_CheckPredicate, 22, 114, 29, // Skip to: 19091 /* 11553 */ MCD_OPC_Decode, 233, 17, 169, 2, // Opcode: VFCE /* 11558 */ MCD_OPC_FilterValue, 234, 1, 46, 1, // Skip to: 11865 /* 11563 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 11566 */ MCD_OPC_FilterValue, 0, 97, 29, // Skip to: 19091 /* 11570 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 11573 */ MCD_OPC_FilterValue, 0, 90, 29, // Skip to: 19091 /* 11577 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... /* 11580 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11593 /* 11584 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 11856 /* 11588 */ MCD_OPC_Decode, 244, 17, 130, 2, // Opcode: VFCHESB /* 11593 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11606 /* 11597 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 11856 /* 11601 */ MCD_OPC_Decode, 242, 17, 130, 2, // Opcode: VFCHEDB /* 11606 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11619 /* 11610 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 11856 /* 11614 */ MCD_OPC_Decode, 160, 18, 130, 2, // Opcode: VFKHESB /* 11619 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11632 /* 11623 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 11856 /* 11627 */ MCD_OPC_Decode, 158, 18, 130, 2, // Opcode: VFKHEDB /* 11632 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11646 /* 11637 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 11856 /* 11641 */ MCD_OPC_Decode, 140, 21, 166, 2, // Opcode: WFCHESB /* 11646 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11660 /* 11651 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 11856 /* 11655 */ MCD_OPC_Decode, 138, 21, 167, 2, // Opcode: WFCHEDB /* 11660 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11674 /* 11665 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 11856 /* 11669 */ MCD_OPC_Decode, 142, 21, 130, 2, // Opcode: WFCHEXB /* 11674 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11688 /* 11679 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 11856 /* 11683 */ MCD_OPC_Decode, 168, 21, 166, 2, // Opcode: WFKHESB /* 11688 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 11702 /* 11693 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 11856 /* 11697 */ MCD_OPC_Decode, 166, 21, 167, 2, // Opcode: WFKHEDB /* 11702 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 11716 /* 11707 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 11856 /* 11711 */ MCD_OPC_Decode, 170, 21, 130, 2, // Opcode: WFKHEXB /* 11716 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 11730 /* 11721 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 11856 /* 11725 */ MCD_OPC_Decode, 245, 17, 130, 2, // Opcode: VFCHESBS /* 11730 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 11744 /* 11735 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 11856 /* 11739 */ MCD_OPC_Decode, 243, 17, 130, 2, // Opcode: VFCHEDBS /* 11744 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 11758 /* 11749 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 11856 /* 11753 */ MCD_OPC_Decode, 161, 18, 130, 2, // Opcode: VFKHESBS /* 11758 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 11772 /* 11763 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 11856 /* 11767 */ MCD_OPC_Decode, 159, 18, 130, 2, // Opcode: VFKHEDBS /* 11772 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 11786 /* 11777 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 11856 /* 11781 */ MCD_OPC_Decode, 141, 21, 166, 2, // Opcode: WFCHESBS /* 11786 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 11800 /* 11791 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 11856 /* 11795 */ MCD_OPC_Decode, 139, 21, 167, 2, // Opcode: WFCHEDBS /* 11800 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 11814 /* 11805 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 11856 /* 11809 */ MCD_OPC_Decode, 143, 21, 130, 2, // Opcode: WFCHEXBS /* 11814 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 11828 /* 11819 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 11856 /* 11823 */ MCD_OPC_Decode, 169, 21, 166, 2, // Opcode: WFKHESBS /* 11828 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 11842 /* 11833 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 11856 /* 11837 */ MCD_OPC_Decode, 167, 21, 167, 2, // Opcode: WFKHEDBS /* 11842 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 11856 /* 11847 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 11856 /* 11851 */ MCD_OPC_Decode, 171, 21, 130, 2, // Opcode: WFKHEXBS /* 11856 */ MCD_OPC_CheckPredicate, 22, 63, 28, // Skip to: 19091 /* 11860 */ MCD_OPC_Decode, 241, 17, 169, 2, // Opcode: VFCHE /* 11865 */ MCD_OPC_FilterValue, 235, 1, 46, 1, // Skip to: 12172 /* 11870 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 11873 */ MCD_OPC_FilterValue, 0, 46, 28, // Skip to: 19091 /* 11877 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 11880 */ MCD_OPC_FilterValue, 0, 39, 28, // Skip to: 19091 /* 11884 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... /* 11887 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11900 /* 11891 */ MCD_OPC_CheckPredicate, 23, 12, 1, // Skip to: 12163 /* 11895 */ MCD_OPC_Decode, 246, 17, 130, 2, // Opcode: VFCHSB /* 11900 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11913 /* 11904 */ MCD_OPC_CheckPredicate, 22, 255, 0, // Skip to: 12163 /* 11908 */ MCD_OPC_Decode, 239, 17, 130, 2, // Opcode: VFCHDB /* 11913 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 11926 /* 11917 */ MCD_OPC_CheckPredicate, 23, 242, 0, // Skip to: 12163 /* 11921 */ MCD_OPC_Decode, 162, 18, 130, 2, // Opcode: VFKHSB /* 11926 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 11939 /* 11930 */ MCD_OPC_CheckPredicate, 23, 229, 0, // Skip to: 12163 /* 11934 */ MCD_OPC_Decode, 156, 18, 130, 2, // Opcode: VFKHDB /* 11939 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 11953 /* 11944 */ MCD_OPC_CheckPredicate, 23, 215, 0, // Skip to: 12163 /* 11948 */ MCD_OPC_Decode, 144, 21, 166, 2, // Opcode: WFCHSB /* 11953 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 11967 /* 11958 */ MCD_OPC_CheckPredicate, 22, 201, 0, // Skip to: 12163 /* 11962 */ MCD_OPC_Decode, 136, 21, 167, 2, // Opcode: WFCHDB /* 11967 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 11981 /* 11972 */ MCD_OPC_CheckPredicate, 23, 187, 0, // Skip to: 12163 /* 11976 */ MCD_OPC_Decode, 146, 21, 130, 2, // Opcode: WFCHXB /* 11981 */ MCD_OPC_FilterValue, 194, 1, 9, 0, // Skip to: 11995 /* 11986 */ MCD_OPC_CheckPredicate, 23, 173, 0, // Skip to: 12163 /* 11990 */ MCD_OPC_Decode, 172, 21, 166, 2, // Opcode: WFKHSB /* 11995 */ MCD_OPC_FilterValue, 195, 1, 9, 0, // Skip to: 12009 /* 12000 */ MCD_OPC_CheckPredicate, 23, 159, 0, // Skip to: 12163 /* 12004 */ MCD_OPC_Decode, 164, 21, 167, 2, // Opcode: WFKHDB /* 12009 */ MCD_OPC_FilterValue, 196, 1, 9, 0, // Skip to: 12023 /* 12014 */ MCD_OPC_CheckPredicate, 23, 145, 0, // Skip to: 12163 /* 12018 */ MCD_OPC_Decode, 174, 21, 130, 2, // Opcode: WFKHXB /* 12023 */ MCD_OPC_FilterValue, 130, 2, 9, 0, // Skip to: 12037 /* 12028 */ MCD_OPC_CheckPredicate, 23, 131, 0, // Skip to: 12163 /* 12032 */ MCD_OPC_Decode, 247, 17, 130, 2, // Opcode: VFCHSBS /* 12037 */ MCD_OPC_FilterValue, 131, 2, 9, 0, // Skip to: 12051 /* 12042 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 12163 /* 12046 */ MCD_OPC_Decode, 240, 17, 130, 2, // Opcode: VFCHDBS /* 12051 */ MCD_OPC_FilterValue, 194, 2, 9, 0, // Skip to: 12065 /* 12056 */ MCD_OPC_CheckPredicate, 23, 103, 0, // Skip to: 12163 /* 12060 */ MCD_OPC_Decode, 163, 18, 130, 2, // Opcode: VFKHSBS /* 12065 */ MCD_OPC_FilterValue, 195, 2, 9, 0, // Skip to: 12079 /* 12070 */ MCD_OPC_CheckPredicate, 23, 89, 0, // Skip to: 12163 /* 12074 */ MCD_OPC_Decode, 157, 18, 130, 2, // Opcode: VFKHDBS /* 12079 */ MCD_OPC_FilterValue, 130, 3, 9, 0, // Skip to: 12093 /* 12084 */ MCD_OPC_CheckPredicate, 23, 75, 0, // Skip to: 12163 /* 12088 */ MCD_OPC_Decode, 145, 21, 166, 2, // Opcode: WFCHSBS /* 12093 */ MCD_OPC_FilterValue, 131, 3, 9, 0, // Skip to: 12107 /* 12098 */ MCD_OPC_CheckPredicate, 22, 61, 0, // Skip to: 12163 /* 12102 */ MCD_OPC_Decode, 137, 21, 167, 2, // Opcode: WFCHDBS /* 12107 */ MCD_OPC_FilterValue, 132, 3, 9, 0, // Skip to: 12121 /* 12112 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12163 /* 12116 */ MCD_OPC_Decode, 147, 21, 130, 2, // Opcode: WFCHXBS /* 12121 */ MCD_OPC_FilterValue, 194, 3, 9, 0, // Skip to: 12135 /* 12126 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12163 /* 12130 */ MCD_OPC_Decode, 173, 21, 166, 2, // Opcode: WFKHSBS /* 12135 */ MCD_OPC_FilterValue, 195, 3, 9, 0, // Skip to: 12149 /* 12140 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12163 /* 12144 */ MCD_OPC_Decode, 165, 21, 167, 2, // Opcode: WFKHDBS /* 12149 */ MCD_OPC_FilterValue, 196, 3, 9, 0, // Skip to: 12163 /* 12154 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12163 /* 12158 */ MCD_OPC_Decode, 175, 21, 130, 2, // Opcode: WFKHXBS /* 12163 */ MCD_OPC_CheckPredicate, 22, 12, 27, // Skip to: 19091 /* 12167 */ MCD_OPC_Decode, 238, 17, 169, 2, // Opcode: VFCH /* 12172 */ MCD_OPC_FilterValue, 238, 1, 94, 0, // Skip to: 12271 /* 12177 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12180 */ MCD_OPC_FilterValue, 0, 251, 26, // Skip to: 19091 /* 12184 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 12187 */ MCD_OPC_FilterValue, 0, 244, 26, // Skip to: 19091 /* 12191 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 12194 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12207 /* 12198 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12262 /* 12202 */ MCD_OPC_Decode, 184, 18, 136, 2, // Opcode: VFMINSB /* 12207 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12220 /* 12211 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12262 /* 12215 */ MCD_OPC_Decode, 183, 18, 136, 2, // Opcode: VFMINDB /* 12220 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12234 /* 12225 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12262 /* 12229 */ MCD_OPC_Decode, 199, 21, 170, 2, // Opcode: WFMINSB /* 12234 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12248 /* 12239 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12262 /* 12243 */ MCD_OPC_Decode, 198, 21, 171, 2, // Opcode: WFMINDB /* 12248 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12262 /* 12253 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12262 /* 12257 */ MCD_OPC_Decode, 200, 21, 136, 2, // Opcode: WFMINXB /* 12262 */ MCD_OPC_CheckPredicate, 23, 169, 26, // Skip to: 19091 /* 12266 */ MCD_OPC_Decode, 182, 18, 169, 2, // Opcode: VFMIN /* 12271 */ MCD_OPC_FilterValue, 239, 1, 94, 0, // Skip to: 12370 /* 12276 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12279 */ MCD_OPC_FilterValue, 0, 152, 26, // Skip to: 19091 /* 12283 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 12286 */ MCD_OPC_FilterValue, 0, 145, 26, // Skip to: 19091 /* 12290 */ MCD_OPC_ExtractField, 12, 8, // Inst{19-12} ... /* 12293 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12306 /* 12297 */ MCD_OPC_CheckPredicate, 23, 60, 0, // Skip to: 12361 /* 12301 */ MCD_OPC_Decode, 180, 18, 136, 2, // Opcode: VFMAXSB /* 12306 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12319 /* 12310 */ MCD_OPC_CheckPredicate, 23, 47, 0, // Skip to: 12361 /* 12314 */ MCD_OPC_Decode, 179, 18, 136, 2, // Opcode: VFMAXDB /* 12319 */ MCD_OPC_FilterValue, 130, 1, 9, 0, // Skip to: 12333 /* 12324 */ MCD_OPC_CheckPredicate, 23, 33, 0, // Skip to: 12361 /* 12328 */ MCD_OPC_Decode, 195, 21, 170, 2, // Opcode: WFMAXSB /* 12333 */ MCD_OPC_FilterValue, 131, 1, 9, 0, // Skip to: 12347 /* 12338 */ MCD_OPC_CheckPredicate, 23, 19, 0, // Skip to: 12361 /* 12342 */ MCD_OPC_Decode, 194, 21, 171, 2, // Opcode: WFMAXDB /* 12347 */ MCD_OPC_FilterValue, 132, 1, 9, 0, // Skip to: 12361 /* 12352 */ MCD_OPC_CheckPredicate, 23, 5, 0, // Skip to: 12361 /* 12356 */ MCD_OPC_Decode, 196, 21, 136, 2, // Opcode: WFMAXXB /* 12361 */ MCD_OPC_CheckPredicate, 23, 70, 26, // Skip to: 19091 /* 12365 */ MCD_OPC_Decode, 178, 18, 169, 2, // Opcode: VFMAX /* 12370 */ MCD_OPC_FilterValue, 240, 1, 78, 0, // Skip to: 12453 /* 12375 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12378 */ MCD_OPC_FilterValue, 0, 53, 26, // Skip to: 19091 /* 12382 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 12385 */ MCD_OPC_FilterValue, 0, 46, 26, // Skip to: 19091 /* 12389 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12392 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12405 /* 12396 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12444 /* 12400 */ MCD_OPC_Decode, 233, 16, 130, 2, // Opcode: VAVGLB /* 12405 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12418 /* 12409 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12444 /* 12413 */ MCD_OPC_Decode, 236, 16, 130, 2, // Opcode: VAVGLH /* 12418 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12431 /* 12422 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12444 /* 12426 */ MCD_OPC_Decode, 234, 16, 130, 2, // Opcode: VAVGLF /* 12431 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12444 /* 12435 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12444 /* 12439 */ MCD_OPC_Decode, 235, 16, 130, 2, // Opcode: VAVGLG /* 12444 */ MCD_OPC_CheckPredicate, 22, 243, 25, // Skip to: 19091 /* 12448 */ MCD_OPC_Decode, 232, 16, 131, 2, // Opcode: VAVGL /* 12453 */ MCD_OPC_FilterValue, 241, 1, 91, 0, // Skip to: 12549 /* 12458 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12461 */ MCD_OPC_FilterValue, 0, 226, 25, // Skip to: 19091 /* 12465 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 12468 */ MCD_OPC_FilterValue, 0, 219, 25, // Skip to: 19091 /* 12472 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12475 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12488 /* 12479 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12540 /* 12483 */ MCD_OPC_Decode, 214, 16, 130, 2, // Opcode: VACCB /* 12488 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12501 /* 12492 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12540 /* 12496 */ MCD_OPC_Decode, 219, 16, 130, 2, // Opcode: VACCH /* 12501 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12514 /* 12505 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12540 /* 12509 */ MCD_OPC_Decode, 217, 16, 130, 2, // Opcode: VACCF /* 12514 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12527 /* 12518 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12540 /* 12522 */ MCD_OPC_Decode, 218, 16, 130, 2, // Opcode: VACCG /* 12527 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12540 /* 12531 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12540 /* 12535 */ MCD_OPC_Decode, 220, 16, 130, 2, // Opcode: VACCQ /* 12540 */ MCD_OPC_CheckPredicate, 22, 147, 25, // Skip to: 19091 /* 12544 */ MCD_OPC_Decode, 213, 16, 131, 2, // Opcode: VACC /* 12549 */ MCD_OPC_FilterValue, 242, 1, 78, 0, // Skip to: 12632 /* 12554 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12557 */ MCD_OPC_FilterValue, 0, 130, 25, // Skip to: 19091 /* 12561 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 12564 */ MCD_OPC_FilterValue, 0, 123, 25, // Skip to: 19091 /* 12568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12571 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12584 /* 12575 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12623 /* 12579 */ MCD_OPC_Decode, 228, 16, 130, 2, // Opcode: VAVGB /* 12584 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12597 /* 12588 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12623 /* 12592 */ MCD_OPC_Decode, 231, 16, 130, 2, // Opcode: VAVGH /* 12597 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12610 /* 12601 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12623 /* 12605 */ MCD_OPC_Decode, 229, 16, 130, 2, // Opcode: VAVGF /* 12610 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12623 /* 12614 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12623 /* 12618 */ MCD_OPC_Decode, 230, 16, 130, 2, // Opcode: VAVGG /* 12623 */ MCD_OPC_CheckPredicate, 22, 64, 25, // Skip to: 19091 /* 12627 */ MCD_OPC_Decode, 227, 16, 131, 2, // Opcode: VAVG /* 12632 */ MCD_OPC_FilterValue, 243, 1, 91, 0, // Skip to: 12728 /* 12637 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12640 */ MCD_OPC_FilterValue, 0, 47, 25, // Skip to: 19091 /* 12644 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 12647 */ MCD_OPC_FilterValue, 0, 40, 25, // Skip to: 19091 /* 12651 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12667 /* 12658 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12719 /* 12662 */ MCD_OPC_Decode, 211, 16, 130, 2, // Opcode: VAB /* 12667 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12680 /* 12671 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12719 /* 12675 */ MCD_OPC_Decode, 224, 16, 130, 2, // Opcode: VAH /* 12680 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12693 /* 12684 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12719 /* 12688 */ MCD_OPC_Decode, 222, 16, 130, 2, // Opcode: VAF /* 12693 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12706 /* 12697 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12719 /* 12701 */ MCD_OPC_Decode, 223, 16, 130, 2, // Opcode: VAG /* 12706 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12719 /* 12710 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12719 /* 12714 */ MCD_OPC_Decode, 226, 16, 130, 2, // Opcode: VAQ /* 12719 */ MCD_OPC_CheckPredicate, 22, 224, 24, // Skip to: 19091 /* 12723 */ MCD_OPC_Decode, 210, 16, 131, 2, // Opcode: VA /* 12728 */ MCD_OPC_FilterValue, 245, 1, 91, 0, // Skip to: 12824 /* 12733 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12736 */ MCD_OPC_FilterValue, 0, 207, 24, // Skip to: 19091 /* 12740 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 12743 */ MCD_OPC_FilterValue, 0, 200, 24, // Skip to: 19091 /* 12747 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12750 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12763 /* 12754 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12815 /* 12758 */ MCD_OPC_Decode, 171, 20, 130, 2, // Opcode: VSCBIB /* 12763 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12776 /* 12767 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12815 /* 12771 */ MCD_OPC_Decode, 174, 20, 130, 2, // Opcode: VSCBIH /* 12776 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12789 /* 12780 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12815 /* 12784 */ MCD_OPC_Decode, 172, 20, 130, 2, // Opcode: VSCBIF /* 12789 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12802 /* 12793 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12815 /* 12797 */ MCD_OPC_Decode, 173, 20, 130, 2, // Opcode: VSCBIG /* 12802 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12815 /* 12806 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12815 /* 12810 */ MCD_OPC_Decode, 175, 20, 130, 2, // Opcode: VSCBIQ /* 12815 */ MCD_OPC_CheckPredicate, 22, 128, 24, // Skip to: 19091 /* 12819 */ MCD_OPC_Decode, 170, 20, 131, 2, // Opcode: VSCBI /* 12824 */ MCD_OPC_FilterValue, 247, 1, 91, 0, // Skip to: 12920 /* 12829 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12832 */ MCD_OPC_FilterValue, 0, 111, 24, // Skip to: 19091 /* 12836 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 12839 */ MCD_OPC_FilterValue, 0, 104, 24, // Skip to: 19091 /* 12843 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12859 /* 12850 */ MCD_OPC_CheckPredicate, 22, 57, 0, // Skip to: 12911 /* 12854 */ MCD_OPC_Decode, 165, 20, 130, 2, // Opcode: VSB /* 12859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12872 /* 12863 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 12911 /* 12867 */ MCD_OPC_Decode, 186, 20, 130, 2, // Opcode: VSH /* 12872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 12885 /* 12876 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 12911 /* 12880 */ MCD_OPC_Decode, 184, 20, 130, 2, // Opcode: VSF /* 12885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12898 /* 12889 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 12911 /* 12893 */ MCD_OPC_Decode, 185, 20, 130, 2, // Opcode: VSG /* 12898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 12911 /* 12902 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 12911 /* 12906 */ MCD_OPC_Decode, 191, 20, 130, 2, // Opcode: VSQ /* 12911 */ MCD_OPC_CheckPredicate, 22, 32, 24, // Skip to: 19091 /* 12915 */ MCD_OPC_Decode, 164, 20, 131, 2, // Opcode: VS /* 12920 */ MCD_OPC_FilterValue, 248, 1, 165, 0, // Skip to: 13090 /* 12925 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 12928 */ MCD_OPC_FilterValue, 0, 15, 24, // Skip to: 19091 /* 12932 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 12935 */ MCD_OPC_FilterValue, 0, 8, 24, // Skip to: 19091 /* 12939 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 12942 */ MCD_OPC_FilterValue, 0, 1, 24, // Skip to: 19091 /* 12946 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 12949 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12982 /* 12953 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 12956 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12969 /* 12960 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13081 /* 12964 */ MCD_OPC_Decode, 243, 16, 130, 2, // Opcode: VCEQB /* 12969 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13081 /* 12973 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13081 /* 12977 */ MCD_OPC_Decode, 244, 16, 130, 2, // Opcode: VCEQBS /* 12982 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13015 /* 12986 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 12989 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13002 /* 12993 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13081 /* 12997 */ MCD_OPC_Decode, 249, 16, 130, 2, // Opcode: VCEQH /* 13002 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13081 /* 13006 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13081 /* 13010 */ MCD_OPC_Decode, 250, 16, 130, 2, // Opcode: VCEQHS /* 13015 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13048 /* 13019 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13022 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13035 /* 13026 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13081 /* 13030 */ MCD_OPC_Decode, 245, 16, 130, 2, // Opcode: VCEQF /* 13035 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13081 /* 13039 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13081 /* 13043 */ MCD_OPC_Decode, 246, 16, 130, 2, // Opcode: VCEQFS /* 13048 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13081 /* 13052 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13055 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13068 /* 13059 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13081 /* 13063 */ MCD_OPC_Decode, 247, 16, 130, 2, // Opcode: VCEQG /* 13068 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13081 /* 13072 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13081 /* 13076 */ MCD_OPC_Decode, 248, 16, 130, 2, // Opcode: VCEQGS /* 13081 */ MCD_OPC_CheckPredicate, 22, 118, 23, // Skip to: 19091 /* 13085 */ MCD_OPC_Decode, 242, 16, 137, 2, // Opcode: VCEQ /* 13090 */ MCD_OPC_FilterValue, 249, 1, 165, 0, // Skip to: 13260 /* 13095 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 13098 */ MCD_OPC_FilterValue, 0, 101, 23, // Skip to: 19091 /* 13102 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 13105 */ MCD_OPC_FilterValue, 0, 94, 23, // Skip to: 19091 /* 13109 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 13112 */ MCD_OPC_FilterValue, 0, 87, 23, // Skip to: 19091 /* 13116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 13119 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13152 /* 13123 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13126 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13139 /* 13130 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13251 /* 13134 */ MCD_OPC_Decode, 135, 17, 130, 2, // Opcode: VCHLB /* 13139 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13251 /* 13143 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13251 /* 13147 */ MCD_OPC_Decode, 136, 17, 130, 2, // Opcode: VCHLBS /* 13152 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13185 /* 13156 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13159 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13172 /* 13163 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13251 /* 13167 */ MCD_OPC_Decode, 141, 17, 130, 2, // Opcode: VCHLH /* 13172 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13251 /* 13176 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13251 /* 13180 */ MCD_OPC_Decode, 142, 17, 130, 2, // Opcode: VCHLHS /* 13185 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13218 /* 13189 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13205 /* 13196 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13251 /* 13200 */ MCD_OPC_Decode, 137, 17, 130, 2, // Opcode: VCHLF /* 13205 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13251 /* 13209 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13251 /* 13213 */ MCD_OPC_Decode, 138, 17, 130, 2, // Opcode: VCHLFS /* 13218 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13251 /* 13222 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13225 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13238 /* 13229 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13251 /* 13233 */ MCD_OPC_Decode, 139, 17, 130, 2, // Opcode: VCHLG /* 13238 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13251 /* 13242 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13251 /* 13246 */ MCD_OPC_Decode, 140, 17, 130, 2, // Opcode: VCHLGS /* 13251 */ MCD_OPC_CheckPredicate, 22, 204, 22, // Skip to: 19091 /* 13255 */ MCD_OPC_Decode, 134, 17, 137, 2, // Opcode: VCHL /* 13260 */ MCD_OPC_FilterValue, 251, 1, 165, 0, // Skip to: 13430 /* 13265 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 13268 */ MCD_OPC_FilterValue, 0, 187, 22, // Skip to: 19091 /* 13272 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... /* 13275 */ MCD_OPC_FilterValue, 0, 180, 22, // Skip to: 19091 /* 13279 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... /* 13282 */ MCD_OPC_FilterValue, 0, 173, 22, // Skip to: 19091 /* 13286 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 13289 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 13322 /* 13293 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13296 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13309 /* 13300 */ MCD_OPC_CheckPredicate, 22, 117, 0, // Skip to: 13421 /* 13304 */ MCD_OPC_Decode, 254, 16, 130, 2, // Opcode: VCHB /* 13309 */ MCD_OPC_FilterValue, 1, 108, 0, // Skip to: 13421 /* 13313 */ MCD_OPC_CheckPredicate, 22, 104, 0, // Skip to: 13421 /* 13317 */ MCD_OPC_Decode, 255, 16, 130, 2, // Opcode: VCHBS /* 13322 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 13355 /* 13326 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13329 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13342 /* 13333 */ MCD_OPC_CheckPredicate, 22, 84, 0, // Skip to: 13421 /* 13337 */ MCD_OPC_Decode, 132, 17, 130, 2, // Opcode: VCHH /* 13342 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13421 /* 13346 */ MCD_OPC_CheckPredicate, 22, 71, 0, // Skip to: 13421 /* 13350 */ MCD_OPC_Decode, 133, 17, 130, 2, // Opcode: VCHHS /* 13355 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 13388 /* 13359 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13362 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13375 /* 13366 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 13421 /* 13370 */ MCD_OPC_Decode, 128, 17, 130, 2, // Opcode: VCHF /* 13375 */ MCD_OPC_FilterValue, 1, 42, 0, // Skip to: 13421 /* 13379 */ MCD_OPC_CheckPredicate, 22, 38, 0, // Skip to: 13421 /* 13383 */ MCD_OPC_Decode, 129, 17, 130, 2, // Opcode: VCHFS /* 13388 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 13421 /* 13392 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... /* 13395 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13408 /* 13399 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13421 /* 13403 */ MCD_OPC_Decode, 130, 17, 130, 2, // Opcode: VCHG /* 13408 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13421 /* 13412 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13421 /* 13416 */ MCD_OPC_Decode, 131, 17, 130, 2, // Opcode: VCHGS /* 13421 */ MCD_OPC_CheckPredicate, 22, 34, 22, // Skip to: 19091 /* 13425 */ MCD_OPC_Decode, 253, 16, 137, 2, // Opcode: VCH /* 13430 */ MCD_OPC_FilterValue, 252, 1, 78, 0, // Skip to: 13513 /* 13435 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 13438 */ MCD_OPC_FilterValue, 0, 17, 22, // Skip to: 19091 /* 13442 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 13445 */ MCD_OPC_FilterValue, 0, 10, 22, // Skip to: 19091 /* 13449 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 13452 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13465 /* 13456 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13504 /* 13460 */ MCD_OPC_Decode, 214, 19, 130, 2, // Opcode: VMNLB /* 13465 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13478 /* 13469 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13504 /* 13473 */ MCD_OPC_Decode, 217, 19, 130, 2, // Opcode: VMNLH /* 13478 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13491 /* 13482 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13504 /* 13486 */ MCD_OPC_Decode, 215, 19, 130, 2, // Opcode: VMNLF /* 13491 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13504 /* 13495 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13504 /* 13499 */ MCD_OPC_Decode, 216, 19, 130, 2, // Opcode: VMNLG /* 13504 */ MCD_OPC_CheckPredicate, 22, 207, 21, // Skip to: 19091 /* 13508 */ MCD_OPC_Decode, 213, 19, 131, 2, // Opcode: VMNL /* 13513 */ MCD_OPC_FilterValue, 253, 1, 78, 0, // Skip to: 13596 /* 13518 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 13521 */ MCD_OPC_FilterValue, 0, 190, 21, // Skip to: 19091 /* 13525 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 13528 */ MCD_OPC_FilterValue, 0, 183, 21, // Skip to: 19091 /* 13532 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 13535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13548 /* 13539 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13587 /* 13543 */ MCD_OPC_Decode, 242, 19, 130, 2, // Opcode: VMXLB /* 13548 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13561 /* 13552 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13587 /* 13556 */ MCD_OPC_Decode, 245, 19, 130, 2, // Opcode: VMXLH /* 13561 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13574 /* 13565 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13587 /* 13569 */ MCD_OPC_Decode, 243, 19, 130, 2, // Opcode: VMXLF /* 13574 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13587 /* 13578 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13587 /* 13582 */ MCD_OPC_Decode, 244, 19, 130, 2, // Opcode: VMXLG /* 13587 */ MCD_OPC_CheckPredicate, 22, 124, 21, // Skip to: 19091 /* 13591 */ MCD_OPC_Decode, 241, 19, 131, 2, // Opcode: VMXL /* 13596 */ MCD_OPC_FilterValue, 254, 1, 78, 0, // Skip to: 13679 /* 13601 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 13604 */ MCD_OPC_FilterValue, 0, 107, 21, // Skip to: 19091 /* 13608 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 13611 */ MCD_OPC_FilterValue, 0, 100, 21, // Skip to: 19091 /* 13615 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 13618 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13631 /* 13622 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13670 /* 13626 */ MCD_OPC_Decode, 209, 19, 130, 2, // Opcode: VMNB /* 13631 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13644 /* 13635 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13670 /* 13639 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: VMNH /* 13644 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13657 /* 13648 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13670 /* 13652 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: VMNF /* 13657 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13670 /* 13661 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13670 /* 13665 */ MCD_OPC_Decode, 211, 19, 130, 2, // Opcode: VMNG /* 13670 */ MCD_OPC_CheckPredicate, 22, 41, 21, // Skip to: 19091 /* 13674 */ MCD_OPC_Decode, 208, 19, 131, 2, // Opcode: VMN /* 13679 */ MCD_OPC_FilterValue, 255, 1, 31, 21, // Skip to: 19091 /* 13684 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 13687 */ MCD_OPC_FilterValue, 0, 24, 21, // Skip to: 19091 /* 13691 */ MCD_OPC_ExtractField, 16, 12, // Inst{27-16} ... /* 13694 */ MCD_OPC_FilterValue, 0, 17, 21, // Skip to: 19091 /* 13698 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 13701 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13714 /* 13705 */ MCD_OPC_CheckPredicate, 22, 44, 0, // Skip to: 13753 /* 13709 */ MCD_OPC_Decode, 237, 19, 130, 2, // Opcode: VMXB /* 13714 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 13727 /* 13718 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 13753 /* 13722 */ MCD_OPC_Decode, 240, 19, 130, 2, // Opcode: VMXH /* 13727 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13740 /* 13731 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 13753 /* 13735 */ MCD_OPC_Decode, 238, 19, 130, 2, // Opcode: VMXF /* 13740 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 13753 /* 13744 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 13753 /* 13748 */ MCD_OPC_Decode, 239, 19, 130, 2, // Opcode: VMXG /* 13753 */ MCD_OPC_CheckPredicate, 22, 214, 20, // Skip to: 19091 /* 13757 */ MCD_OPC_Decode, 236, 19, 131, 2, // Opcode: VMX /* 13762 */ MCD_OPC_FilterValue, 232, 1, 5, 0, // Skip to: 13772 /* 13767 */ MCD_OPC_Decode, 193, 13, 189, 1, // Opcode: MVCIN /* 13772 */ MCD_OPC_FilterValue, 233, 1, 5, 0, // Skip to: 13782 /* 13777 */ MCD_OPC_Decode, 143, 14, 191, 1, // Opcode: PKA /* 13782 */ MCD_OPC_FilterValue, 234, 1, 5, 0, // Skip to: 13792 /* 13787 */ MCD_OPC_Decode, 207, 16, 189, 1, // Opcode: UNPKA /* 13792 */ MCD_OPC_FilterValue, 235, 1, 198, 7, // Skip to: 15787 /* 13797 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 13800 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 13809 /* 13804 */ MCD_OPC_Decode, 227, 10, 172, 2, // Opcode: LMG /* 13809 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 13818 /* 13813 */ MCD_OPC_Decode, 132, 15, 173, 2, // Opcode: SRAG /* 13818 */ MCD_OPC_FilterValue, 11, 5, 0, // Skip to: 13827 /* 13822 */ MCD_OPC_Decode, 217, 14, 173, 2, // Opcode: SLAG /* 13827 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 13836 /* 13831 */ MCD_OPC_Decode, 139, 15, 173, 2, // Opcode: SRLG /* 13836 */ MCD_OPC_FilterValue, 13, 5, 0, // Skip to: 13845 /* 13840 */ MCD_OPC_Decode, 236, 14, 173, 2, // Opcode: SLLG /* 13845 */ MCD_OPC_FilterValue, 15, 5, 0, // Skip to: 13854 /* 13849 */ MCD_OPC_Decode, 186, 16, 172, 2, // Opcode: TRACG /* 13854 */ MCD_OPC_FilterValue, 20, 5, 0, // Skip to: 13863 /* 13858 */ MCD_OPC_Decode, 140, 8, 174, 2, // Opcode: CSY /* 13863 */ MCD_OPC_FilterValue, 28, 5, 0, // Skip to: 13872 /* 13867 */ MCD_OPC_Decode, 167, 14, 173, 2, // Opcode: RLLG /* 13872 */ MCD_OPC_FilterValue, 29, 5, 0, // Skip to: 13881 /* 13876 */ MCD_OPC_Decode, 166, 14, 175, 2, // Opcode: RLL /* 13881 */ MCD_OPC_FilterValue, 32, 5, 0, // Skip to: 13890 /* 13885 */ MCD_OPC_Decode, 143, 7, 176, 2, // Opcode: CLMH /* 13890 */ MCD_OPC_FilterValue, 33, 5, 0, // Skip to: 13899 /* 13894 */ MCD_OPC_Decode, 144, 7, 177, 2, // Opcode: CLMY /* 13899 */ MCD_OPC_FilterValue, 35, 90, 0, // Skip to: 13993 /* 13903 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 13906 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 13919 /* 13910 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 13984 /* 13914 */ MCD_OPC_Decode, 193, 7, 178, 2, // Opcode: CLTAsmH /* 13919 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 13932 /* 13923 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 13984 /* 13927 */ MCD_OPC_Decode, 195, 7, 178, 2, // Opcode: CLTAsmL /* 13932 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 13945 /* 13936 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 13984 /* 13940 */ MCD_OPC_Decode, 197, 7, 178, 2, // Opcode: CLTAsmLH /* 13945 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 13958 /* 13949 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 13984 /* 13953 */ MCD_OPC_Decode, 192, 7, 178, 2, // Opcode: CLTAsmE /* 13958 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 13971 /* 13962 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 13984 /* 13966 */ MCD_OPC_Decode, 194, 7, 178, 2, // Opcode: CLTAsmHE /* 13971 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 13984 /* 13975 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 13984 /* 13979 */ MCD_OPC_Decode, 196, 7, 178, 2, // Opcode: CLTAsmLE /* 13984 */ MCD_OPC_CheckPredicate, 24, 239, 19, // Skip to: 19091 /* 13988 */ MCD_OPC_Decode, 191, 7, 179, 2, // Opcode: CLTAsm /* 13993 */ MCD_OPC_FilterValue, 36, 5, 0, // Skip to: 14002 /* 13997 */ MCD_OPC_Decode, 189, 15, 172, 2, // Opcode: STMG /* 14002 */ MCD_OPC_FilterValue, 37, 5, 0, // Skip to: 14011 /* 14006 */ MCD_OPC_Decode, 169, 15, 180, 2, // Opcode: STCTG /* 14011 */ MCD_OPC_FilterValue, 38, 5, 0, // Skip to: 14020 /* 14015 */ MCD_OPC_Decode, 190, 15, 181, 2, // Opcode: STMH /* 14020 */ MCD_OPC_FilterValue, 43, 90, 0, // Skip to: 14114 /* 14024 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 14027 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14040 /* 14031 */ MCD_OPC_CheckPredicate, 24, 70, 0, // Skip to: 14105 /* 14035 */ MCD_OPC_Decode, 221, 6, 182, 2, // Opcode: CLGTAsmH /* 14040 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14053 /* 14044 */ MCD_OPC_CheckPredicate, 24, 57, 0, // Skip to: 14105 /* 14048 */ MCD_OPC_Decode, 223, 6, 182, 2, // Opcode: CLGTAsmL /* 14053 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14066 /* 14057 */ MCD_OPC_CheckPredicate, 24, 44, 0, // Skip to: 14105 /* 14061 */ MCD_OPC_Decode, 225, 6, 182, 2, // Opcode: CLGTAsmLH /* 14066 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14079 /* 14070 */ MCD_OPC_CheckPredicate, 24, 31, 0, // Skip to: 14105 /* 14074 */ MCD_OPC_Decode, 220, 6, 182, 2, // Opcode: CLGTAsmE /* 14079 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14092 /* 14083 */ MCD_OPC_CheckPredicate, 24, 18, 0, // Skip to: 14105 /* 14087 */ MCD_OPC_Decode, 222, 6, 182, 2, // Opcode: CLGTAsmHE /* 14092 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14105 /* 14096 */ MCD_OPC_CheckPredicate, 24, 5, 0, // Skip to: 14105 /* 14100 */ MCD_OPC_Decode, 224, 6, 182, 2, // Opcode: CLGTAsmLE /* 14105 */ MCD_OPC_CheckPredicate, 24, 118, 19, // Skip to: 19091 /* 14109 */ MCD_OPC_Decode, 219, 6, 183, 2, // Opcode: CLGTAsm /* 14114 */ MCD_OPC_FilterValue, 44, 5, 0, // Skip to: 14123 /* 14118 */ MCD_OPC_Decode, 165, 15, 176, 2, // Opcode: STCMH /* 14123 */ MCD_OPC_FilterValue, 45, 5, 0, // Skip to: 14132 /* 14127 */ MCD_OPC_Decode, 166, 15, 177, 2, // Opcode: STCMY /* 14132 */ MCD_OPC_FilterValue, 47, 5, 0, // Skip to: 14141 /* 14136 */ MCD_OPC_Decode, 143, 10, 180, 2, // Opcode: LCTLG /* 14141 */ MCD_OPC_FilterValue, 48, 5, 0, // Skip to: 14150 /* 14145 */ MCD_OPC_Decode, 135, 8, 184, 2, // Opcode: CSG /* 14150 */ MCD_OPC_FilterValue, 49, 5, 0, // Skip to: 14159 /* 14154 */ MCD_OPC_Decode, 160, 4, 185, 2, // Opcode: CDSY /* 14159 */ MCD_OPC_FilterValue, 62, 5, 0, // Skip to: 14168 /* 14163 */ MCD_OPC_Decode, 158, 4, 185, 2, // Opcode: CDSG /* 14168 */ MCD_OPC_FilterValue, 68, 5, 0, // Skip to: 14177 /* 14172 */ MCD_OPC_Decode, 135, 4, 184, 2, // Opcode: BXHG /* 14177 */ MCD_OPC_FilterValue, 69, 5, 0, // Skip to: 14186 /* 14181 */ MCD_OPC_Decode, 137, 4, 184, 2, // Opcode: BXLEG /* 14186 */ MCD_OPC_FilterValue, 76, 5, 0, // Skip to: 14195 /* 14190 */ MCD_OPC_Decode, 216, 8, 173, 2, // Opcode: ECAG /* 14195 */ MCD_OPC_FilterValue, 81, 5, 0, // Skip to: 14204 /* 14199 */ MCD_OPC_Decode, 180, 16, 186, 2, // Opcode: TMY /* 14204 */ MCD_OPC_FilterValue, 82, 5, 0, // Skip to: 14213 /* 14208 */ MCD_OPC_Decode, 206, 13, 186, 2, // Opcode: MVIY /* 14213 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 14222 /* 14217 */ MCD_OPC_Decode, 239, 13, 186, 2, // Opcode: NIY /* 14222 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 14231 /* 14226 */ MCD_OPC_Decode, 141, 7, 186, 2, // Opcode: CLIY /* 14231 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 14240 /* 14235 */ MCD_OPC_Decode, 128, 14, 186, 2, // Opcode: OIY /* 14240 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 14249 /* 14244 */ MCD_OPC_Decode, 234, 21, 186, 2, // Opcode: XIY /* 14249 */ MCD_OPC_FilterValue, 106, 5, 0, // Skip to: 14258 /* 14253 */ MCD_OPC_Decode, 155, 3, 187, 2, // Opcode: ASI /* 14258 */ MCD_OPC_FilterValue, 110, 5, 0, // Skip to: 14267 /* 14262 */ MCD_OPC_Decode, 148, 3, 187, 2, // Opcode: ALSI /* 14267 */ MCD_OPC_FilterValue, 122, 5, 0, // Skip to: 14276 /* 14271 */ MCD_OPC_Decode, 249, 2, 187, 2, // Opcode: AGSI /* 14276 */ MCD_OPC_FilterValue, 126, 5, 0, // Skip to: 14285 /* 14280 */ MCD_OPC_Decode, 142, 3, 187, 2, // Opcode: ALGSI /* 14285 */ MCD_OPC_FilterValue, 128, 1, 5, 0, // Skip to: 14295 /* 14290 */ MCD_OPC_Decode, 132, 9, 188, 2, // Opcode: ICMH /* 14295 */ MCD_OPC_FilterValue, 129, 1, 5, 0, // Skip to: 14305 /* 14300 */ MCD_OPC_Decode, 133, 9, 189, 2, // Opcode: ICMY /* 14305 */ MCD_OPC_FilterValue, 142, 1, 5, 0, // Skip to: 14315 /* 14310 */ MCD_OPC_Decode, 197, 13, 190, 2, // Opcode: MVCLU /* 14315 */ MCD_OPC_FilterValue, 143, 1, 5, 0, // Skip to: 14325 /* 14320 */ MCD_OPC_Decode, 228, 5, 190, 2, // Opcode: CLCLU /* 14325 */ MCD_OPC_FilterValue, 144, 1, 5, 0, // Skip to: 14335 /* 14330 */ MCD_OPC_Decode, 191, 15, 191, 2, // Opcode: STMY /* 14335 */ MCD_OPC_FilterValue, 150, 1, 5, 0, // Skip to: 14345 /* 14340 */ MCD_OPC_Decode, 228, 10, 181, 2, // Opcode: LMH /* 14345 */ MCD_OPC_FilterValue, 152, 1, 5, 0, // Skip to: 14355 /* 14350 */ MCD_OPC_Decode, 229, 10, 191, 2, // Opcode: LMY /* 14355 */ MCD_OPC_FilterValue, 154, 1, 5, 0, // Skip to: 14365 /* 14360 */ MCD_OPC_Decode, 245, 9, 192, 2, // Opcode: LAMY /* 14365 */ MCD_OPC_FilterValue, 155, 1, 5, 0, // Skip to: 14375 /* 14370 */ MCD_OPC_Decode, 156, 15, 192, 2, // Opcode: STAMY /* 14375 */ MCD_OPC_FilterValue, 192, 1, 17, 0, // Skip to: 14397 /* 14380 */ MCD_OPC_CheckField, 32, 4, 0, 97, 18, // Skip to: 19091 /* 14386 */ MCD_OPC_CheckField, 8, 8, 0, 91, 18, // Skip to: 19091 /* 14392 */ MCD_OPC_Decode, 181, 16, 193, 2, // Opcode: TP /* 14397 */ MCD_OPC_FilterValue, 220, 1, 9, 0, // Skip to: 14411 /* 14402 */ MCD_OPC_CheckPredicate, 15, 77, 18, // Skip to: 19091 /* 14406 */ MCD_OPC_Decode, 133, 15, 175, 2, // Opcode: SRAK /* 14411 */ MCD_OPC_FilterValue, 221, 1, 9, 0, // Skip to: 14425 /* 14416 */ MCD_OPC_CheckPredicate, 15, 63, 18, // Skip to: 19091 /* 14420 */ MCD_OPC_Decode, 218, 14, 175, 2, // Opcode: SLAK /* 14425 */ MCD_OPC_FilterValue, 222, 1, 9, 0, // Skip to: 14439 /* 14430 */ MCD_OPC_CheckPredicate, 15, 49, 18, // Skip to: 19091 /* 14434 */ MCD_OPC_Decode, 140, 15, 175, 2, // Opcode: SRLK /* 14439 */ MCD_OPC_FilterValue, 223, 1, 9, 0, // Skip to: 14453 /* 14444 */ MCD_OPC_CheckPredicate, 15, 35, 18, // Skip to: 19091 /* 14448 */ MCD_OPC_Decode, 237, 14, 175, 2, // Opcode: SLLK /* 14453 */ MCD_OPC_FilterValue, 224, 1, 194, 0, // Skip to: 14652 /* 14458 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 14461 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14474 /* 14465 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14643 /* 14469 */ MCD_OPC_Decode, 154, 11, 194, 2, // Opcode: LOCFHAsmO /* 14474 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14487 /* 14478 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14643 /* 14482 */ MCD_OPC_Decode, 138, 11, 194, 2, // Opcode: LOCFHAsmH /* 14487 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14500 /* 14491 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14643 /* 14495 */ MCD_OPC_Decode, 148, 11, 194, 2, // Opcode: LOCFHAsmNLE /* 14500 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14513 /* 14504 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14643 /* 14508 */ MCD_OPC_Decode, 140, 11, 194, 2, // Opcode: LOCFHAsmL /* 14513 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14526 /* 14517 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14643 /* 14521 */ MCD_OPC_Decode, 146, 11, 194, 2, // Opcode: LOCFHAsmNHE /* 14526 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14539 /* 14530 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14643 /* 14534 */ MCD_OPC_Decode, 142, 11, 194, 2, // Opcode: LOCFHAsmLH /* 14539 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14552 /* 14543 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14643 /* 14547 */ MCD_OPC_Decode, 144, 11, 194, 2, // Opcode: LOCFHAsmNE /* 14552 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14565 /* 14556 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14643 /* 14560 */ MCD_OPC_Decode, 137, 11, 194, 2, // Opcode: LOCFHAsmE /* 14565 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14578 /* 14569 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14643 /* 14573 */ MCD_OPC_Decode, 149, 11, 194, 2, // Opcode: LOCFHAsmNLH /* 14578 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14591 /* 14582 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14643 /* 14586 */ MCD_OPC_Decode, 139, 11, 194, 2, // Opcode: LOCFHAsmHE /* 14591 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14604 /* 14595 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14643 /* 14599 */ MCD_OPC_Decode, 147, 11, 194, 2, // Opcode: LOCFHAsmNL /* 14604 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14617 /* 14608 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14643 /* 14612 */ MCD_OPC_Decode, 141, 11, 194, 2, // Opcode: LOCFHAsmLE /* 14617 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14630 /* 14621 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14643 /* 14625 */ MCD_OPC_Decode, 145, 11, 194, 2, // Opcode: LOCFHAsmNH /* 14630 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14643 /* 14634 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14643 /* 14638 */ MCD_OPC_Decode, 151, 11, 194, 2, // Opcode: LOCFHAsmNO /* 14643 */ MCD_OPC_CheckPredicate, 12, 92, 17, // Skip to: 19091 /* 14647 */ MCD_OPC_Decode, 136, 11, 195, 2, // Opcode: LOCFHAsm /* 14652 */ MCD_OPC_FilterValue, 225, 1, 194, 0, // Skip to: 14851 /* 14657 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 14660 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14673 /* 14664 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 14842 /* 14668 */ MCD_OPC_Decode, 234, 15, 196, 2, // Opcode: STOCFHAsmO /* 14673 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14686 /* 14677 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 14842 /* 14681 */ MCD_OPC_Decode, 218, 15, 196, 2, // Opcode: STOCFHAsmH /* 14686 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14699 /* 14690 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 14842 /* 14694 */ MCD_OPC_Decode, 228, 15, 196, 2, // Opcode: STOCFHAsmNLE /* 14699 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14712 /* 14703 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 14842 /* 14707 */ MCD_OPC_Decode, 220, 15, 196, 2, // Opcode: STOCFHAsmL /* 14712 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14725 /* 14716 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 14842 /* 14720 */ MCD_OPC_Decode, 226, 15, 196, 2, // Opcode: STOCFHAsmNHE /* 14725 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14738 /* 14729 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 14842 /* 14733 */ MCD_OPC_Decode, 222, 15, 196, 2, // Opcode: STOCFHAsmLH /* 14738 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14751 /* 14742 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 14842 /* 14746 */ MCD_OPC_Decode, 224, 15, 196, 2, // Opcode: STOCFHAsmNE /* 14751 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14764 /* 14755 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 14842 /* 14759 */ MCD_OPC_Decode, 217, 15, 196, 2, // Opcode: STOCFHAsmE /* 14764 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14777 /* 14768 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 14842 /* 14772 */ MCD_OPC_Decode, 229, 15, 196, 2, // Opcode: STOCFHAsmNLH /* 14777 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14790 /* 14781 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 14842 /* 14785 */ MCD_OPC_Decode, 219, 15, 196, 2, // Opcode: STOCFHAsmHE /* 14790 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 14803 /* 14794 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 14842 /* 14798 */ MCD_OPC_Decode, 227, 15, 196, 2, // Opcode: STOCFHAsmNL /* 14803 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 14816 /* 14807 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 14842 /* 14811 */ MCD_OPC_Decode, 221, 15, 196, 2, // Opcode: STOCFHAsmLE /* 14816 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 14829 /* 14820 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 14842 /* 14824 */ MCD_OPC_Decode, 225, 15, 196, 2, // Opcode: STOCFHAsmNH /* 14829 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 14842 /* 14833 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 14842 /* 14837 */ MCD_OPC_Decode, 231, 15, 196, 2, // Opcode: STOCFHAsmNO /* 14842 */ MCD_OPC_CheckPredicate, 12, 149, 16, // Skip to: 19091 /* 14846 */ MCD_OPC_Decode, 216, 15, 197, 2, // Opcode: STOCFHAsm /* 14851 */ MCD_OPC_FilterValue, 226, 1, 194, 0, // Skip to: 15050 /* 14856 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 14859 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14872 /* 14863 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15041 /* 14867 */ MCD_OPC_Decode, 198, 11, 198, 2, // Opcode: LOCGAsmO /* 14872 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 14885 /* 14876 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15041 /* 14880 */ MCD_OPC_Decode, 182, 11, 198, 2, // Opcode: LOCGAsmH /* 14885 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 14898 /* 14889 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15041 /* 14893 */ MCD_OPC_Decode, 192, 11, 198, 2, // Opcode: LOCGAsmNLE /* 14898 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 14911 /* 14902 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15041 /* 14906 */ MCD_OPC_Decode, 184, 11, 198, 2, // Opcode: LOCGAsmL /* 14911 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 14924 /* 14915 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15041 /* 14919 */ MCD_OPC_Decode, 190, 11, 198, 2, // Opcode: LOCGAsmNHE /* 14924 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 14937 /* 14928 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15041 /* 14932 */ MCD_OPC_Decode, 186, 11, 198, 2, // Opcode: LOCGAsmLH /* 14937 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 14950 /* 14941 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15041 /* 14945 */ MCD_OPC_Decode, 188, 11, 198, 2, // Opcode: LOCGAsmNE /* 14950 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 14963 /* 14954 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15041 /* 14958 */ MCD_OPC_Decode, 181, 11, 198, 2, // Opcode: LOCGAsmE /* 14963 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 14976 /* 14967 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15041 /* 14971 */ MCD_OPC_Decode, 193, 11, 198, 2, // Opcode: LOCGAsmNLH /* 14976 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 14989 /* 14980 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15041 /* 14984 */ MCD_OPC_Decode, 183, 11, 198, 2, // Opcode: LOCGAsmHE /* 14989 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15002 /* 14993 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15041 /* 14997 */ MCD_OPC_Decode, 191, 11, 198, 2, // Opcode: LOCGAsmNL /* 15002 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15015 /* 15006 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15041 /* 15010 */ MCD_OPC_Decode, 185, 11, 198, 2, // Opcode: LOCGAsmLE /* 15015 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15028 /* 15019 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15041 /* 15023 */ MCD_OPC_Decode, 189, 11, 198, 2, // Opcode: LOCGAsmNH /* 15028 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15041 /* 15032 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15041 /* 15036 */ MCD_OPC_Decode, 195, 11, 198, 2, // Opcode: LOCGAsmNO /* 15041 */ MCD_OPC_CheckPredicate, 14, 206, 15, // Skip to: 19091 /* 15045 */ MCD_OPC_Decode, 180, 11, 199, 2, // Opcode: LOCGAsm /* 15050 */ MCD_OPC_FilterValue, 227, 1, 194, 0, // Skip to: 15249 /* 15055 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 15058 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15071 /* 15062 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15240 /* 15066 */ MCD_OPC_Decode, 128, 16, 182, 2, // Opcode: STOCGAsmO /* 15071 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15084 /* 15075 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15240 /* 15079 */ MCD_OPC_Decode, 240, 15, 182, 2, // Opcode: STOCGAsmH /* 15084 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15097 /* 15088 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15240 /* 15092 */ MCD_OPC_Decode, 250, 15, 182, 2, // Opcode: STOCGAsmNLE /* 15097 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15110 /* 15101 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15240 /* 15105 */ MCD_OPC_Decode, 242, 15, 182, 2, // Opcode: STOCGAsmL /* 15110 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15123 /* 15114 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15240 /* 15118 */ MCD_OPC_Decode, 248, 15, 182, 2, // Opcode: STOCGAsmNHE /* 15123 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15136 /* 15127 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15240 /* 15131 */ MCD_OPC_Decode, 244, 15, 182, 2, // Opcode: STOCGAsmLH /* 15136 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15149 /* 15140 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15240 /* 15144 */ MCD_OPC_Decode, 246, 15, 182, 2, // Opcode: STOCGAsmNE /* 15149 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15162 /* 15153 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15240 /* 15157 */ MCD_OPC_Decode, 239, 15, 182, 2, // Opcode: STOCGAsmE /* 15162 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15175 /* 15166 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15240 /* 15170 */ MCD_OPC_Decode, 251, 15, 182, 2, // Opcode: STOCGAsmNLH /* 15175 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15188 /* 15179 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15240 /* 15183 */ MCD_OPC_Decode, 241, 15, 182, 2, // Opcode: STOCGAsmHE /* 15188 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15201 /* 15192 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15240 /* 15196 */ MCD_OPC_Decode, 249, 15, 182, 2, // Opcode: STOCGAsmNL /* 15201 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15214 /* 15205 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15240 /* 15209 */ MCD_OPC_Decode, 243, 15, 182, 2, // Opcode: STOCGAsmLE /* 15214 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15227 /* 15218 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15240 /* 15222 */ MCD_OPC_Decode, 247, 15, 182, 2, // Opcode: STOCGAsmNH /* 15227 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15240 /* 15231 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15240 /* 15235 */ MCD_OPC_Decode, 253, 15, 182, 2, // Opcode: STOCGAsmNO /* 15240 */ MCD_OPC_CheckPredicate, 14, 7, 15, // Skip to: 19091 /* 15244 */ MCD_OPC_Decode, 238, 15, 183, 2, // Opcode: STOCGAsm /* 15249 */ MCD_OPC_FilterValue, 228, 1, 9, 0, // Skip to: 15263 /* 15254 */ MCD_OPC_CheckPredicate, 17, 249, 14, // Skip to: 19091 /* 15258 */ MCD_OPC_Decode, 247, 9, 172, 2, // Opcode: LANG /* 15263 */ MCD_OPC_FilterValue, 230, 1, 9, 0, // Skip to: 15277 /* 15268 */ MCD_OPC_CheckPredicate, 17, 235, 14, // Skip to: 19091 /* 15272 */ MCD_OPC_Decode, 249, 9, 172, 2, // Opcode: LAOG /* 15277 */ MCD_OPC_FilterValue, 231, 1, 9, 0, // Skip to: 15291 /* 15282 */ MCD_OPC_CheckPredicate, 17, 221, 14, // Skip to: 19091 /* 15286 */ MCD_OPC_Decode, 254, 9, 172, 2, // Opcode: LAXG /* 15291 */ MCD_OPC_FilterValue, 232, 1, 9, 0, // Skip to: 15305 /* 15296 */ MCD_OPC_CheckPredicate, 17, 207, 14, // Skip to: 19091 /* 15300 */ MCD_OPC_Decode, 239, 9, 172, 2, // Opcode: LAAG /* 15305 */ MCD_OPC_FilterValue, 234, 1, 9, 0, // Skip to: 15319 /* 15310 */ MCD_OPC_CheckPredicate, 17, 193, 14, // Skip to: 19091 /* 15314 */ MCD_OPC_Decode, 241, 9, 172, 2, // Opcode: LAALG /* 15319 */ MCD_OPC_FilterValue, 242, 1, 194, 0, // Skip to: 15518 /* 15324 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 15327 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15340 /* 15331 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15509 /* 15335 */ MCD_OPC_Decode, 132, 11, 200, 2, // Opcode: LOCAsmO /* 15340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15353 /* 15344 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15509 /* 15348 */ MCD_OPC_Decode, 244, 10, 200, 2, // Opcode: LOCAsmH /* 15353 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15366 /* 15357 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15509 /* 15361 */ MCD_OPC_Decode, 254, 10, 200, 2, // Opcode: LOCAsmNLE /* 15366 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15379 /* 15370 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15509 /* 15374 */ MCD_OPC_Decode, 246, 10, 200, 2, // Opcode: LOCAsmL /* 15379 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15392 /* 15383 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15509 /* 15387 */ MCD_OPC_Decode, 252, 10, 200, 2, // Opcode: LOCAsmNHE /* 15392 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15405 /* 15396 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15509 /* 15400 */ MCD_OPC_Decode, 248, 10, 200, 2, // Opcode: LOCAsmLH /* 15405 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15418 /* 15409 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15509 /* 15413 */ MCD_OPC_Decode, 250, 10, 200, 2, // Opcode: LOCAsmNE /* 15418 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15431 /* 15422 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15509 /* 15426 */ MCD_OPC_Decode, 243, 10, 200, 2, // Opcode: LOCAsmE /* 15431 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15444 /* 15435 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15509 /* 15439 */ MCD_OPC_Decode, 255, 10, 200, 2, // Opcode: LOCAsmNLH /* 15444 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15457 /* 15448 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15509 /* 15452 */ MCD_OPC_Decode, 245, 10, 200, 2, // Opcode: LOCAsmHE /* 15457 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15470 /* 15461 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15509 /* 15465 */ MCD_OPC_Decode, 253, 10, 200, 2, // Opcode: LOCAsmNL /* 15470 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15483 /* 15474 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15509 /* 15478 */ MCD_OPC_Decode, 247, 10, 200, 2, // Opcode: LOCAsmLE /* 15483 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15496 /* 15487 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15509 /* 15491 */ MCD_OPC_Decode, 251, 10, 200, 2, // Opcode: LOCAsmNH /* 15496 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15509 /* 15500 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15509 /* 15504 */ MCD_OPC_Decode, 129, 11, 200, 2, // Opcode: LOCAsmNO /* 15509 */ MCD_OPC_CheckPredicate, 14, 250, 13, // Skip to: 19091 /* 15513 */ MCD_OPC_Decode, 242, 10, 201, 2, // Opcode: LOCAsm /* 15518 */ MCD_OPC_FilterValue, 243, 1, 194, 0, // Skip to: 15717 /* 15523 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 15526 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15539 /* 15530 */ MCD_OPC_CheckPredicate, 14, 174, 0, // Skip to: 15708 /* 15534 */ MCD_OPC_Decode, 212, 15, 178, 2, // Opcode: STOCAsmO /* 15539 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15552 /* 15543 */ MCD_OPC_CheckPredicate, 14, 161, 0, // Skip to: 15708 /* 15547 */ MCD_OPC_Decode, 196, 15, 178, 2, // Opcode: STOCAsmH /* 15552 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15565 /* 15556 */ MCD_OPC_CheckPredicate, 14, 148, 0, // Skip to: 15708 /* 15560 */ MCD_OPC_Decode, 206, 15, 178, 2, // Opcode: STOCAsmNLE /* 15565 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15578 /* 15569 */ MCD_OPC_CheckPredicate, 14, 135, 0, // Skip to: 15708 /* 15573 */ MCD_OPC_Decode, 198, 15, 178, 2, // Opcode: STOCAsmL /* 15578 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15591 /* 15582 */ MCD_OPC_CheckPredicate, 14, 122, 0, // Skip to: 15708 /* 15586 */ MCD_OPC_Decode, 204, 15, 178, 2, // Opcode: STOCAsmNHE /* 15591 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15604 /* 15595 */ MCD_OPC_CheckPredicate, 14, 109, 0, // Skip to: 15708 /* 15599 */ MCD_OPC_Decode, 200, 15, 178, 2, // Opcode: STOCAsmLH /* 15604 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15617 /* 15608 */ MCD_OPC_CheckPredicate, 14, 96, 0, // Skip to: 15708 /* 15612 */ MCD_OPC_Decode, 202, 15, 178, 2, // Opcode: STOCAsmNE /* 15617 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15630 /* 15621 */ MCD_OPC_CheckPredicate, 14, 83, 0, // Skip to: 15708 /* 15625 */ MCD_OPC_Decode, 195, 15, 178, 2, // Opcode: STOCAsmE /* 15630 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15643 /* 15634 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 15708 /* 15638 */ MCD_OPC_Decode, 207, 15, 178, 2, // Opcode: STOCAsmNLH /* 15643 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15656 /* 15647 */ MCD_OPC_CheckPredicate, 14, 57, 0, // Skip to: 15708 /* 15651 */ MCD_OPC_Decode, 197, 15, 178, 2, // Opcode: STOCAsmHE /* 15656 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15669 /* 15660 */ MCD_OPC_CheckPredicate, 14, 44, 0, // Skip to: 15708 /* 15664 */ MCD_OPC_Decode, 205, 15, 178, 2, // Opcode: STOCAsmNL /* 15669 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15682 /* 15673 */ MCD_OPC_CheckPredicate, 14, 31, 0, // Skip to: 15708 /* 15677 */ MCD_OPC_Decode, 199, 15, 178, 2, // Opcode: STOCAsmLE /* 15682 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15695 /* 15686 */ MCD_OPC_CheckPredicate, 14, 18, 0, // Skip to: 15708 /* 15690 */ MCD_OPC_Decode, 203, 15, 178, 2, // Opcode: STOCAsmNH /* 15695 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15708 /* 15699 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 15708 /* 15703 */ MCD_OPC_Decode, 209, 15, 178, 2, // Opcode: STOCAsmNO /* 15708 */ MCD_OPC_CheckPredicate, 14, 51, 13, // Skip to: 19091 /* 15712 */ MCD_OPC_Decode, 194, 15, 179, 2, // Opcode: STOCAsm /* 15717 */ MCD_OPC_FilterValue, 244, 1, 9, 0, // Skip to: 15731 /* 15722 */ MCD_OPC_CheckPredicate, 17, 37, 13, // Skip to: 19091 /* 15726 */ MCD_OPC_Decode, 246, 9, 191, 2, // Opcode: LAN /* 15731 */ MCD_OPC_FilterValue, 246, 1, 9, 0, // Skip to: 15745 /* 15736 */ MCD_OPC_CheckPredicate, 17, 23, 13, // Skip to: 19091 /* 15740 */ MCD_OPC_Decode, 248, 9, 191, 2, // Opcode: LAO /* 15745 */ MCD_OPC_FilterValue, 247, 1, 9, 0, // Skip to: 15759 /* 15750 */ MCD_OPC_CheckPredicate, 17, 9, 13, // Skip to: 19091 /* 15754 */ MCD_OPC_Decode, 253, 9, 191, 2, // Opcode: LAX /* 15759 */ MCD_OPC_FilterValue, 248, 1, 9, 0, // Skip to: 15773 /* 15764 */ MCD_OPC_CheckPredicate, 17, 251, 12, // Skip to: 19091 /* 15768 */ MCD_OPC_Decode, 238, 9, 191, 2, // Opcode: LAA /* 15773 */ MCD_OPC_FilterValue, 250, 1, 241, 12, // Skip to: 19091 /* 15778 */ MCD_OPC_CheckPredicate, 17, 237, 12, // Skip to: 19091 /* 15782 */ MCD_OPC_Decode, 240, 9, 191, 2, // Opcode: LAAL /* 15787 */ MCD_OPC_FilterValue, 236, 1, 195, 8, // Skip to: 18035 /* 15792 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 15795 */ MCD_OPC_FilterValue, 66, 201, 0, // Skip to: 16000 /* 15799 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... /* 15802 */ MCD_OPC_FilterValue, 0, 213, 12, // Skip to: 19091 /* 15806 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 15809 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 15822 /* 15813 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 15991 /* 15817 */ MCD_OPC_Decode, 158, 12, 202, 2, // Opcode: LOCHIAsmO /* 15822 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 15835 /* 15826 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 15991 /* 15830 */ MCD_OPC_Decode, 142, 12, 202, 2, // Opcode: LOCHIAsmH /* 15835 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 15848 /* 15839 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 15991 /* 15843 */ MCD_OPC_Decode, 152, 12, 202, 2, // Opcode: LOCHIAsmNLE /* 15848 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 15861 /* 15852 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 15991 /* 15856 */ MCD_OPC_Decode, 144, 12, 202, 2, // Opcode: LOCHIAsmL /* 15861 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 15874 /* 15865 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 15991 /* 15869 */ MCD_OPC_Decode, 150, 12, 202, 2, // Opcode: LOCHIAsmNHE /* 15874 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 15887 /* 15878 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 15991 /* 15882 */ MCD_OPC_Decode, 146, 12, 202, 2, // Opcode: LOCHIAsmLH /* 15887 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 15900 /* 15891 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 15991 /* 15895 */ MCD_OPC_Decode, 148, 12, 202, 2, // Opcode: LOCHIAsmNE /* 15900 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 15913 /* 15904 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 15991 /* 15908 */ MCD_OPC_Decode, 141, 12, 202, 2, // Opcode: LOCHIAsmE /* 15913 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 15926 /* 15917 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 15991 /* 15921 */ MCD_OPC_Decode, 153, 12, 202, 2, // Opcode: LOCHIAsmNLH /* 15926 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 15939 /* 15930 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 15991 /* 15934 */ MCD_OPC_Decode, 143, 12, 202, 2, // Opcode: LOCHIAsmHE /* 15939 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 15952 /* 15943 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 15991 /* 15947 */ MCD_OPC_Decode, 151, 12, 202, 2, // Opcode: LOCHIAsmNL /* 15952 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 15965 /* 15956 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 15991 /* 15960 */ MCD_OPC_Decode, 145, 12, 202, 2, // Opcode: LOCHIAsmLE /* 15965 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 15978 /* 15969 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 15991 /* 15973 */ MCD_OPC_Decode, 149, 12, 202, 2, // Opcode: LOCHIAsmNH /* 15978 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 15991 /* 15982 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 15991 /* 15986 */ MCD_OPC_Decode, 155, 12, 202, 2, // Opcode: LOCHIAsmNO /* 15991 */ MCD_OPC_CheckPredicate, 12, 24, 12, // Skip to: 19091 /* 15995 */ MCD_OPC_Decode, 140, 12, 203, 2, // Opcode: LOCHIAsm /* 16000 */ MCD_OPC_FilterValue, 68, 11, 0, // Skip to: 16015 /* 16004 */ MCD_OPC_CheckField, 8, 8, 0, 9, 12, // Skip to: 19091 /* 16010 */ MCD_OPC_Decode, 128, 4, 204, 2, // Opcode: BRXHG /* 16015 */ MCD_OPC_FilterValue, 69, 11, 0, // Skip to: 16030 /* 16019 */ MCD_OPC_CheckField, 8, 8, 0, 250, 11, // Skip to: 19091 /* 16025 */ MCD_OPC_Decode, 130, 4, 204, 2, // Opcode: BRXLG /* 16030 */ MCD_OPC_FilterValue, 70, 201, 0, // Skip to: 16235 /* 16034 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... /* 16037 */ MCD_OPC_FilterValue, 0, 234, 11, // Skip to: 19091 /* 16041 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 16044 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16057 /* 16048 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16226 /* 16052 */ MCD_OPC_Decode, 220, 11, 205, 2, // Opcode: LOCGHIAsmO /* 16057 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16070 /* 16061 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16226 /* 16065 */ MCD_OPC_Decode, 204, 11, 205, 2, // Opcode: LOCGHIAsmH /* 16070 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16083 /* 16074 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16226 /* 16078 */ MCD_OPC_Decode, 214, 11, 205, 2, // Opcode: LOCGHIAsmNLE /* 16083 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16096 /* 16087 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16226 /* 16091 */ MCD_OPC_Decode, 206, 11, 205, 2, // Opcode: LOCGHIAsmL /* 16096 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16109 /* 16100 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16226 /* 16104 */ MCD_OPC_Decode, 212, 11, 205, 2, // Opcode: LOCGHIAsmNHE /* 16109 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16122 /* 16113 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16226 /* 16117 */ MCD_OPC_Decode, 208, 11, 205, 2, // Opcode: LOCGHIAsmLH /* 16122 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16135 /* 16126 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16226 /* 16130 */ MCD_OPC_Decode, 210, 11, 205, 2, // Opcode: LOCGHIAsmNE /* 16135 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16148 /* 16139 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16226 /* 16143 */ MCD_OPC_Decode, 203, 11, 205, 2, // Opcode: LOCGHIAsmE /* 16148 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16161 /* 16152 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16226 /* 16156 */ MCD_OPC_Decode, 215, 11, 205, 2, // Opcode: LOCGHIAsmNLH /* 16161 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16174 /* 16165 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16226 /* 16169 */ MCD_OPC_Decode, 205, 11, 205, 2, // Opcode: LOCGHIAsmHE /* 16174 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16187 /* 16178 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16226 /* 16182 */ MCD_OPC_Decode, 213, 11, 205, 2, // Opcode: LOCGHIAsmNL /* 16187 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16200 /* 16191 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16226 /* 16195 */ MCD_OPC_Decode, 207, 11, 205, 2, // Opcode: LOCGHIAsmLE /* 16200 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16213 /* 16204 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16226 /* 16208 */ MCD_OPC_Decode, 211, 11, 205, 2, // Opcode: LOCGHIAsmNH /* 16213 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16226 /* 16217 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16226 /* 16221 */ MCD_OPC_Decode, 217, 11, 205, 2, // Opcode: LOCGHIAsmNO /* 16226 */ MCD_OPC_CheckPredicate, 12, 45, 11, // Skip to: 19091 /* 16230 */ MCD_OPC_Decode, 202, 11, 206, 2, // Opcode: LOCGHIAsm /* 16235 */ MCD_OPC_FilterValue, 78, 201, 0, // Skip to: 16440 /* 16239 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ... /* 16242 */ MCD_OPC_FilterValue, 0, 29, 11, // Skip to: 19091 /* 16246 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 16249 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 16262 /* 16253 */ MCD_OPC_CheckPredicate, 12, 174, 0, // Skip to: 16431 /* 16257 */ MCD_OPC_Decode, 136, 12, 207, 2, // Opcode: LOCHHIAsmO /* 16262 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16275 /* 16266 */ MCD_OPC_CheckPredicate, 12, 161, 0, // Skip to: 16431 /* 16270 */ MCD_OPC_Decode, 248, 11, 207, 2, // Opcode: LOCHHIAsmH /* 16275 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 16288 /* 16279 */ MCD_OPC_CheckPredicate, 12, 148, 0, // Skip to: 16431 /* 16283 */ MCD_OPC_Decode, 130, 12, 207, 2, // Opcode: LOCHHIAsmNLE /* 16288 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 16301 /* 16292 */ MCD_OPC_CheckPredicate, 12, 135, 0, // Skip to: 16431 /* 16296 */ MCD_OPC_Decode, 250, 11, 207, 2, // Opcode: LOCHHIAsmL /* 16301 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 16314 /* 16305 */ MCD_OPC_CheckPredicate, 12, 122, 0, // Skip to: 16431 /* 16309 */ MCD_OPC_Decode, 128, 12, 207, 2, // Opcode: LOCHHIAsmNHE /* 16314 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 16327 /* 16318 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 16431 /* 16322 */ MCD_OPC_Decode, 252, 11, 207, 2, // Opcode: LOCHHIAsmLH /* 16327 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 16340 /* 16331 */ MCD_OPC_CheckPredicate, 12, 96, 0, // Skip to: 16431 /* 16335 */ MCD_OPC_Decode, 254, 11, 207, 2, // Opcode: LOCHHIAsmNE /* 16340 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 16353 /* 16344 */ MCD_OPC_CheckPredicate, 12, 83, 0, // Skip to: 16431 /* 16348 */ MCD_OPC_Decode, 247, 11, 207, 2, // Opcode: LOCHHIAsmE /* 16353 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 16366 /* 16357 */ MCD_OPC_CheckPredicate, 12, 70, 0, // Skip to: 16431 /* 16361 */ MCD_OPC_Decode, 131, 12, 207, 2, // Opcode: LOCHHIAsmNLH /* 16366 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 16379 /* 16370 */ MCD_OPC_CheckPredicate, 12, 57, 0, // Skip to: 16431 /* 16374 */ MCD_OPC_Decode, 249, 11, 207, 2, // Opcode: LOCHHIAsmHE /* 16379 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 16392 /* 16383 */ MCD_OPC_CheckPredicate, 12, 44, 0, // Skip to: 16431 /* 16387 */ MCD_OPC_Decode, 129, 12, 207, 2, // Opcode: LOCHHIAsmNL /* 16392 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 16405 /* 16396 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 16431 /* 16400 */ MCD_OPC_Decode, 251, 11, 207, 2, // Opcode: LOCHHIAsmLE /* 16405 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 16418 /* 16409 */ MCD_OPC_CheckPredicate, 12, 18, 0, // Skip to: 16431 /* 16413 */ MCD_OPC_Decode, 255, 11, 207, 2, // Opcode: LOCHHIAsmNH /* 16418 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 16431 /* 16422 */ MCD_OPC_CheckPredicate, 12, 5, 0, // Skip to: 16431 /* 16426 */ MCD_OPC_Decode, 133, 12, 207, 2, // Opcode: LOCHHIAsmNO /* 16431 */ MCD_OPC_CheckPredicate, 12, 96, 10, // Skip to: 19091 /* 16435 */ MCD_OPC_Decode, 246, 11, 208, 2, // Opcode: LOCHHIAsm /* 16440 */ MCD_OPC_FilterValue, 81, 9, 0, // Skip to: 16453 /* 16444 */ MCD_OPC_CheckPredicate, 11, 83, 10, // Skip to: 19091 /* 16448 */ MCD_OPC_Decode, 165, 14, 209, 2, // Opcode: RISBLG /* 16453 */ MCD_OPC_FilterValue, 84, 5, 0, // Skip to: 16462 /* 16457 */ MCD_OPC_Decode, 168, 14, 210, 2, // Opcode: RNSBG /* 16462 */ MCD_OPC_FilterValue, 85, 5, 0, // Skip to: 16471 /* 16466 */ MCD_OPC_Decode, 161, 14, 210, 2, // Opcode: RISBG /* 16471 */ MCD_OPC_FilterValue, 86, 5, 0, // Skip to: 16480 /* 16475 */ MCD_OPC_Decode, 169, 14, 210, 2, // Opcode: ROSBG /* 16480 */ MCD_OPC_FilterValue, 87, 5, 0, // Skip to: 16489 /* 16484 */ MCD_OPC_Decode, 176, 14, 210, 2, // Opcode: RXSBG /* 16489 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 16502 /* 16493 */ MCD_OPC_CheckPredicate, 24, 34, 10, // Skip to: 19091 /* 16497 */ MCD_OPC_Decode, 163, 14, 210, 2, // Opcode: RISBGN /* 16502 */ MCD_OPC_FilterValue, 93, 9, 0, // Skip to: 16515 /* 16506 */ MCD_OPC_CheckPredicate, 11, 21, 10, // Skip to: 19091 /* 16510 */ MCD_OPC_Decode, 164, 14, 211, 2, // Opcode: RISBHG /* 16515 */ MCD_OPC_FilterValue, 100, 69, 0, // Skip to: 16588 /* 16519 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16522 */ MCD_OPC_FilterValue, 0, 5, 10, // Skip to: 19091 /* 16526 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16529 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16538 /* 16533 */ MCD_OPC_Decode, 140, 5, 212, 2, // Opcode: CGRJAsmH /* 16538 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16547 /* 16542 */ MCD_OPC_Decode, 142, 5, 212, 2, // Opcode: CGRJAsmL /* 16547 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16556 /* 16551 */ MCD_OPC_Decode, 144, 5, 212, 2, // Opcode: CGRJAsmLH /* 16556 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16565 /* 16560 */ MCD_OPC_Decode, 139, 5, 212, 2, // Opcode: CGRJAsmE /* 16565 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16574 /* 16569 */ MCD_OPC_Decode, 141, 5, 212, 2, // Opcode: CGRJAsmHE /* 16574 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16583 /* 16578 */ MCD_OPC_Decode, 143, 5, 212, 2, // Opcode: CGRJAsmLE /* 16583 */ MCD_OPC_Decode, 138, 5, 213, 2, // Opcode: CGRJAsm /* 16588 */ MCD_OPC_FilterValue, 101, 69, 0, // Skip to: 16661 /* 16592 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16595 */ MCD_OPC_FilterValue, 0, 188, 9, // Skip to: 19091 /* 16599 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16602 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16611 /* 16606 */ MCD_OPC_Decode, 192, 6, 212, 2, // Opcode: CLGRJAsmH /* 16611 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16620 /* 16615 */ MCD_OPC_Decode, 194, 6, 212, 2, // Opcode: CLGRJAsmL /* 16620 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16629 /* 16624 */ MCD_OPC_Decode, 196, 6, 212, 2, // Opcode: CLGRJAsmLH /* 16629 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16638 /* 16633 */ MCD_OPC_Decode, 191, 6, 212, 2, // Opcode: CLGRJAsmE /* 16638 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16647 /* 16642 */ MCD_OPC_Decode, 193, 6, 212, 2, // Opcode: CLGRJAsmHE /* 16647 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16656 /* 16651 */ MCD_OPC_Decode, 195, 6, 212, 2, // Opcode: CLGRJAsmLE /* 16656 */ MCD_OPC_Decode, 190, 6, 213, 2, // Opcode: CLGRJAsm /* 16661 */ MCD_OPC_FilterValue, 112, 76, 0, // Skip to: 16741 /* 16665 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16668 */ MCD_OPC_FilterValue, 0, 115, 9, // Skip to: 19091 /* 16672 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 16675 */ MCD_OPC_FilterValue, 0, 108, 9, // Skip to: 19091 /* 16679 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16682 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16691 /* 16686 */ MCD_OPC_Decode, 239, 4, 214, 2, // Opcode: CGITAsmH /* 16691 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16700 /* 16695 */ MCD_OPC_Decode, 241, 4, 214, 2, // Opcode: CGITAsmL /* 16700 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16709 /* 16704 */ MCD_OPC_Decode, 243, 4, 214, 2, // Opcode: CGITAsmLH /* 16709 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16718 /* 16713 */ MCD_OPC_Decode, 238, 4, 214, 2, // Opcode: CGITAsmE /* 16718 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16727 /* 16722 */ MCD_OPC_Decode, 240, 4, 214, 2, // Opcode: CGITAsmHE /* 16727 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16736 /* 16731 */ MCD_OPC_Decode, 242, 4, 214, 2, // Opcode: CGITAsmLE /* 16736 */ MCD_OPC_Decode, 237, 4, 215, 2, // Opcode: CGITAsm /* 16741 */ MCD_OPC_FilterValue, 113, 76, 0, // Skip to: 16821 /* 16745 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16748 */ MCD_OPC_FilterValue, 0, 35, 9, // Skip to: 19091 /* 16752 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 16755 */ MCD_OPC_FilterValue, 0, 28, 9, // Skip to: 19091 /* 16759 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16762 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16771 /* 16766 */ MCD_OPC_Decode, 163, 6, 216, 2, // Opcode: CLGITAsmH /* 16771 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16780 /* 16775 */ MCD_OPC_Decode, 165, 6, 216, 2, // Opcode: CLGITAsmL /* 16780 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16789 /* 16784 */ MCD_OPC_Decode, 167, 6, 216, 2, // Opcode: CLGITAsmLH /* 16789 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16798 /* 16793 */ MCD_OPC_Decode, 162, 6, 216, 2, // Opcode: CLGITAsmE /* 16798 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16807 /* 16802 */ MCD_OPC_Decode, 164, 6, 216, 2, // Opcode: CLGITAsmHE /* 16807 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16816 /* 16811 */ MCD_OPC_Decode, 166, 6, 216, 2, // Opcode: CLGITAsmLE /* 16816 */ MCD_OPC_Decode, 161, 6, 217, 2, // Opcode: CLGITAsm /* 16821 */ MCD_OPC_FilterValue, 114, 76, 0, // Skip to: 16901 /* 16825 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16828 */ MCD_OPC_FilterValue, 0, 211, 8, // Skip to: 19091 /* 16832 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 16835 */ MCD_OPC_FilterValue, 0, 204, 8, // Skip to: 19091 /* 16839 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16851 /* 16846 */ MCD_OPC_Decode, 212, 5, 218, 2, // Opcode: CITAsmH /* 16851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16860 /* 16855 */ MCD_OPC_Decode, 214, 5, 218, 2, // Opcode: CITAsmL /* 16860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16869 /* 16864 */ MCD_OPC_Decode, 216, 5, 218, 2, // Opcode: CITAsmLH /* 16869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16878 /* 16873 */ MCD_OPC_Decode, 211, 5, 218, 2, // Opcode: CITAsmE /* 16878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16887 /* 16882 */ MCD_OPC_Decode, 213, 5, 218, 2, // Opcode: CITAsmHE /* 16887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16896 /* 16891 */ MCD_OPC_Decode, 215, 5, 218, 2, // Opcode: CITAsmLE /* 16896 */ MCD_OPC_Decode, 210, 5, 219, 2, // Opcode: CITAsm /* 16901 */ MCD_OPC_FilterValue, 115, 76, 0, // Skip to: 16981 /* 16905 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16908 */ MCD_OPC_FilterValue, 0, 131, 8, // Skip to: 19091 /* 16912 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 16915 */ MCD_OPC_FilterValue, 0, 124, 8, // Skip to: 19091 /* 16919 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16922 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 16931 /* 16926 */ MCD_OPC_Decode, 237, 5, 220, 2, // Opcode: CLFITAsmH /* 16931 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 16940 /* 16935 */ MCD_OPC_Decode, 239, 5, 220, 2, // Opcode: CLFITAsmL /* 16940 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 16949 /* 16944 */ MCD_OPC_Decode, 241, 5, 220, 2, // Opcode: CLFITAsmLH /* 16949 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 16958 /* 16953 */ MCD_OPC_Decode, 236, 5, 220, 2, // Opcode: CLFITAsmE /* 16958 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 16967 /* 16962 */ MCD_OPC_Decode, 238, 5, 220, 2, // Opcode: CLFITAsmHE /* 16967 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 16976 /* 16971 */ MCD_OPC_Decode, 240, 5, 220, 2, // Opcode: CLFITAsmLE /* 16976 */ MCD_OPC_Decode, 235, 5, 221, 2, // Opcode: CLFITAsm /* 16981 */ MCD_OPC_FilterValue, 118, 69, 0, // Skip to: 17054 /* 16985 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 16988 */ MCD_OPC_FilterValue, 0, 51, 8, // Skip to: 19091 /* 16992 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 16995 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17004 /* 16999 */ MCD_OPC_Decode, 234, 7, 222, 2, // Opcode: CRJAsmH /* 17004 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17013 /* 17008 */ MCD_OPC_Decode, 236, 7, 222, 2, // Opcode: CRJAsmL /* 17013 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17022 /* 17017 */ MCD_OPC_Decode, 238, 7, 222, 2, // Opcode: CRJAsmLH /* 17022 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17031 /* 17026 */ MCD_OPC_Decode, 233, 7, 222, 2, // Opcode: CRJAsmE /* 17031 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17040 /* 17035 */ MCD_OPC_Decode, 235, 7, 222, 2, // Opcode: CRJAsmHE /* 17040 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17049 /* 17044 */ MCD_OPC_Decode, 237, 7, 222, 2, // Opcode: CRJAsmLE /* 17049 */ MCD_OPC_Decode, 232, 7, 223, 2, // Opcode: CRJAsm /* 17054 */ MCD_OPC_FilterValue, 119, 69, 0, // Skip to: 17127 /* 17058 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 17061 */ MCD_OPC_FilterValue, 0, 234, 7, // Skip to: 19091 /* 17065 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17068 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17077 /* 17072 */ MCD_OPC_Decode, 163, 7, 222, 2, // Opcode: CLRJAsmH /* 17077 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17086 /* 17081 */ MCD_OPC_Decode, 165, 7, 222, 2, // Opcode: CLRJAsmL /* 17086 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17095 /* 17090 */ MCD_OPC_Decode, 167, 7, 222, 2, // Opcode: CLRJAsmLH /* 17095 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17104 /* 17099 */ MCD_OPC_Decode, 162, 7, 222, 2, // Opcode: CLRJAsmE /* 17104 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17113 /* 17108 */ MCD_OPC_Decode, 164, 7, 222, 2, // Opcode: CLRJAsmHE /* 17113 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17122 /* 17117 */ MCD_OPC_Decode, 166, 7, 222, 2, // Opcode: CLRJAsmLE /* 17122 */ MCD_OPC_Decode, 161, 7, 223, 2, // Opcode: CLRJAsm /* 17127 */ MCD_OPC_FilterValue, 124, 62, 0, // Skip to: 17193 /* 17131 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17134 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17143 /* 17138 */ MCD_OPC_Decode, 225, 4, 224, 2, // Opcode: CGIJAsmH /* 17143 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17152 /* 17147 */ MCD_OPC_Decode, 227, 4, 224, 2, // Opcode: CGIJAsmL /* 17152 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17161 /* 17156 */ MCD_OPC_Decode, 229, 4, 224, 2, // Opcode: CGIJAsmLH /* 17161 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17170 /* 17165 */ MCD_OPC_Decode, 224, 4, 224, 2, // Opcode: CGIJAsmE /* 17170 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17179 /* 17174 */ MCD_OPC_Decode, 226, 4, 224, 2, // Opcode: CGIJAsmHE /* 17179 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17188 /* 17183 */ MCD_OPC_Decode, 228, 4, 224, 2, // Opcode: CGIJAsmLE /* 17188 */ MCD_OPC_Decode, 223, 4, 225, 2, // Opcode: CGIJAsm /* 17193 */ MCD_OPC_FilterValue, 125, 62, 0, // Skip to: 17259 /* 17197 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17200 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17209 /* 17204 */ MCD_OPC_Decode, 149, 6, 226, 2, // Opcode: CLGIJAsmH /* 17209 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17218 /* 17213 */ MCD_OPC_Decode, 151, 6, 226, 2, // Opcode: CLGIJAsmL /* 17218 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17227 /* 17222 */ MCD_OPC_Decode, 153, 6, 226, 2, // Opcode: CLGIJAsmLH /* 17227 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17236 /* 17231 */ MCD_OPC_Decode, 148, 6, 226, 2, // Opcode: CLGIJAsmE /* 17236 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17245 /* 17240 */ MCD_OPC_Decode, 150, 6, 226, 2, // Opcode: CLGIJAsmHE /* 17245 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17254 /* 17249 */ MCD_OPC_Decode, 152, 6, 226, 2, // Opcode: CLGIJAsmLE /* 17254 */ MCD_OPC_Decode, 147, 6, 227, 2, // Opcode: CLGIJAsm /* 17259 */ MCD_OPC_FilterValue, 126, 62, 0, // Skip to: 17325 /* 17263 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17266 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17275 /* 17270 */ MCD_OPC_Decode, 198, 5, 228, 2, // Opcode: CIJAsmH /* 17275 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17284 /* 17279 */ MCD_OPC_Decode, 200, 5, 228, 2, // Opcode: CIJAsmL /* 17284 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17293 /* 17288 */ MCD_OPC_Decode, 202, 5, 228, 2, // Opcode: CIJAsmLH /* 17293 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17302 /* 17297 */ MCD_OPC_Decode, 197, 5, 228, 2, // Opcode: CIJAsmE /* 17302 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17311 /* 17306 */ MCD_OPC_Decode, 199, 5, 228, 2, // Opcode: CIJAsmHE /* 17311 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17320 /* 17315 */ MCD_OPC_Decode, 201, 5, 228, 2, // Opcode: CIJAsmLE /* 17320 */ MCD_OPC_Decode, 196, 5, 229, 2, // Opcode: CIJAsm /* 17325 */ MCD_OPC_FilterValue, 127, 62, 0, // Skip to: 17391 /* 17329 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17332 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17341 /* 17336 */ MCD_OPC_Decode, 130, 7, 230, 2, // Opcode: CLIJAsmH /* 17341 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17350 /* 17345 */ MCD_OPC_Decode, 132, 7, 230, 2, // Opcode: CLIJAsmL /* 17350 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17359 /* 17354 */ MCD_OPC_Decode, 134, 7, 230, 2, // Opcode: CLIJAsmLH /* 17359 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17368 /* 17363 */ MCD_OPC_Decode, 129, 7, 230, 2, // Opcode: CLIJAsmE /* 17368 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17377 /* 17372 */ MCD_OPC_Decode, 131, 7, 230, 2, // Opcode: CLIJAsmHE /* 17377 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17386 /* 17381 */ MCD_OPC_Decode, 133, 7, 230, 2, // Opcode: CLIJAsmLE /* 17386 */ MCD_OPC_Decode, 128, 7, 231, 2, // Opcode: CLIJAsm /* 17391 */ MCD_OPC_FilterValue, 216, 1, 15, 0, // Skip to: 17411 /* 17396 */ MCD_OPC_CheckPredicate, 15, 155, 6, // Skip to: 19091 /* 17400 */ MCD_OPC_CheckField, 8, 8, 0, 149, 6, // Skip to: 19091 /* 17406 */ MCD_OPC_Decode, 254, 2, 232, 2, // Opcode: AHIK /* 17411 */ MCD_OPC_FilterValue, 217, 1, 15, 0, // Skip to: 17431 /* 17416 */ MCD_OPC_CheckPredicate, 15, 135, 6, // Skip to: 19091 /* 17420 */ MCD_OPC_CheckField, 8, 8, 0, 129, 6, // Skip to: 19091 /* 17426 */ MCD_OPC_Decode, 246, 2, 233, 2, // Opcode: AGHIK /* 17431 */ MCD_OPC_FilterValue, 218, 1, 15, 0, // Skip to: 17451 /* 17436 */ MCD_OPC_CheckPredicate, 15, 115, 6, // Skip to: 19091 /* 17440 */ MCD_OPC_CheckField, 8, 8, 0, 109, 6, // Skip to: 19091 /* 17446 */ MCD_OPC_Decode, 145, 3, 232, 2, // Opcode: ALHSIK /* 17451 */ MCD_OPC_FilterValue, 219, 1, 15, 0, // Skip to: 17471 /* 17456 */ MCD_OPC_CheckPredicate, 15, 95, 6, // Skip to: 19091 /* 17460 */ MCD_OPC_CheckField, 8, 8, 0, 89, 6, // Skip to: 19091 /* 17466 */ MCD_OPC_Decode, 139, 3, 233, 2, // Opcode: ALGHSIK /* 17471 */ MCD_OPC_FilterValue, 228, 1, 69, 0, // Skip to: 17545 /* 17476 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 17479 */ MCD_OPC_FilterValue, 0, 72, 6, // Skip to: 19091 /* 17483 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17486 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17495 /* 17490 */ MCD_OPC_Decode, 254, 4, 234, 2, // Opcode: CGRBAsmH /* 17495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17504 /* 17499 */ MCD_OPC_Decode, 128, 5, 234, 2, // Opcode: CGRBAsmL /* 17504 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17513 /* 17508 */ MCD_OPC_Decode, 130, 5, 234, 2, // Opcode: CGRBAsmLH /* 17513 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17522 /* 17517 */ MCD_OPC_Decode, 253, 4, 234, 2, // Opcode: CGRBAsmE /* 17522 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17531 /* 17526 */ MCD_OPC_Decode, 255, 4, 234, 2, // Opcode: CGRBAsmHE /* 17531 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17540 /* 17535 */ MCD_OPC_Decode, 129, 5, 234, 2, // Opcode: CGRBAsmLE /* 17540 */ MCD_OPC_Decode, 252, 4, 235, 2, // Opcode: CGRBAsm /* 17545 */ MCD_OPC_FilterValue, 229, 1, 69, 0, // Skip to: 17619 /* 17550 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 17553 */ MCD_OPC_FilterValue, 0, 254, 5, // Skip to: 19091 /* 17557 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17560 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17569 /* 17564 */ MCD_OPC_Decode, 178, 6, 234, 2, // Opcode: CLGRBAsmH /* 17569 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17578 /* 17573 */ MCD_OPC_Decode, 180, 6, 234, 2, // Opcode: CLGRBAsmL /* 17578 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17587 /* 17582 */ MCD_OPC_Decode, 182, 6, 234, 2, // Opcode: CLGRBAsmLH /* 17587 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17596 /* 17591 */ MCD_OPC_Decode, 177, 6, 234, 2, // Opcode: CLGRBAsmE /* 17596 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17605 /* 17600 */ MCD_OPC_Decode, 179, 6, 234, 2, // Opcode: CLGRBAsmHE /* 17605 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17614 /* 17609 */ MCD_OPC_Decode, 181, 6, 234, 2, // Opcode: CLGRBAsmLE /* 17614 */ MCD_OPC_Decode, 176, 6, 235, 2, // Opcode: CLGRBAsm /* 17619 */ MCD_OPC_FilterValue, 246, 1, 69, 0, // Skip to: 17693 /* 17624 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 17627 */ MCD_OPC_FilterValue, 0, 180, 5, // Skip to: 19091 /* 17631 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17634 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17643 /* 17638 */ MCD_OPC_Decode, 218, 7, 236, 2, // Opcode: CRBAsmH /* 17643 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17652 /* 17647 */ MCD_OPC_Decode, 220, 7, 236, 2, // Opcode: CRBAsmL /* 17652 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17661 /* 17656 */ MCD_OPC_Decode, 222, 7, 236, 2, // Opcode: CRBAsmLH /* 17661 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17670 /* 17665 */ MCD_OPC_Decode, 217, 7, 236, 2, // Opcode: CRBAsmE /* 17670 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17679 /* 17674 */ MCD_OPC_Decode, 219, 7, 236, 2, // Opcode: CRBAsmHE /* 17679 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17688 /* 17683 */ MCD_OPC_Decode, 221, 7, 236, 2, // Opcode: CRBAsmLE /* 17688 */ MCD_OPC_Decode, 216, 7, 237, 2, // Opcode: CRBAsm /* 17693 */ MCD_OPC_FilterValue, 247, 1, 69, 0, // Skip to: 17767 /* 17698 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... /* 17701 */ MCD_OPC_FilterValue, 0, 106, 5, // Skip to: 19091 /* 17705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... /* 17708 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17717 /* 17712 */ MCD_OPC_Decode, 149, 7, 236, 2, // Opcode: CLRBAsmH /* 17717 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17726 /* 17721 */ MCD_OPC_Decode, 151, 7, 236, 2, // Opcode: CLRBAsmL /* 17726 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17735 /* 17730 */ MCD_OPC_Decode, 153, 7, 236, 2, // Opcode: CLRBAsmLH /* 17735 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17744 /* 17739 */ MCD_OPC_Decode, 148, 7, 236, 2, // Opcode: CLRBAsmE /* 17744 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17753 /* 17748 */ MCD_OPC_Decode, 150, 7, 236, 2, // Opcode: CLRBAsmHE /* 17753 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17762 /* 17757 */ MCD_OPC_Decode, 152, 7, 236, 2, // Opcode: CLRBAsmLE /* 17762 */ MCD_OPC_Decode, 147, 7, 237, 2, // Opcode: CLRBAsm /* 17767 */ MCD_OPC_FilterValue, 252, 1, 62, 0, // Skip to: 17834 /* 17772 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17775 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17784 /* 17779 */ MCD_OPC_Decode, 211, 4, 238, 2, // Opcode: CGIBAsmH /* 17784 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17793 /* 17788 */ MCD_OPC_Decode, 213, 4, 238, 2, // Opcode: CGIBAsmL /* 17793 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17802 /* 17797 */ MCD_OPC_Decode, 215, 4, 238, 2, // Opcode: CGIBAsmLH /* 17802 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17811 /* 17806 */ MCD_OPC_Decode, 210, 4, 238, 2, // Opcode: CGIBAsmE /* 17811 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17820 /* 17815 */ MCD_OPC_Decode, 212, 4, 238, 2, // Opcode: CGIBAsmHE /* 17820 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17829 /* 17824 */ MCD_OPC_Decode, 214, 4, 238, 2, // Opcode: CGIBAsmLE /* 17829 */ MCD_OPC_Decode, 209, 4, 239, 2, // Opcode: CGIBAsm /* 17834 */ MCD_OPC_FilterValue, 253, 1, 62, 0, // Skip to: 17901 /* 17839 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17842 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17851 /* 17846 */ MCD_OPC_Decode, 135, 6, 240, 2, // Opcode: CLGIBAsmH /* 17851 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17860 /* 17855 */ MCD_OPC_Decode, 137, 6, 240, 2, // Opcode: CLGIBAsmL /* 17860 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17869 /* 17864 */ MCD_OPC_Decode, 139, 6, 240, 2, // Opcode: CLGIBAsmLH /* 17869 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17878 /* 17873 */ MCD_OPC_Decode, 134, 6, 240, 2, // Opcode: CLGIBAsmE /* 17878 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17887 /* 17882 */ MCD_OPC_Decode, 136, 6, 240, 2, // Opcode: CLGIBAsmHE /* 17887 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17896 /* 17891 */ MCD_OPC_Decode, 138, 6, 240, 2, // Opcode: CLGIBAsmLE /* 17896 */ MCD_OPC_Decode, 133, 6, 241, 2, // Opcode: CLGIBAsm /* 17901 */ MCD_OPC_FilterValue, 254, 1, 62, 0, // Skip to: 17968 /* 17906 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17909 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17918 /* 17913 */ MCD_OPC_Decode, 183, 5, 242, 2, // Opcode: CIBAsmH /* 17918 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17927 /* 17922 */ MCD_OPC_Decode, 185, 5, 242, 2, // Opcode: CIBAsmL /* 17927 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 17936 /* 17931 */ MCD_OPC_Decode, 187, 5, 242, 2, // Opcode: CIBAsmLH /* 17936 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 17945 /* 17940 */ MCD_OPC_Decode, 182, 5, 242, 2, // Opcode: CIBAsmE /* 17945 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 17954 /* 17949 */ MCD_OPC_Decode, 184, 5, 242, 2, // Opcode: CIBAsmHE /* 17954 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 17963 /* 17958 */ MCD_OPC_Decode, 186, 5, 242, 2, // Opcode: CIBAsmLE /* 17963 */ MCD_OPC_Decode, 181, 5, 243, 2, // Opcode: CIBAsm /* 17968 */ MCD_OPC_FilterValue, 255, 1, 94, 4, // Skip to: 19091 /* 17973 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ... /* 17976 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 17985 /* 17980 */ MCD_OPC_Decode, 243, 6, 244, 2, // Opcode: CLIBAsmH /* 17985 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 17994 /* 17989 */ MCD_OPC_Decode, 245, 6, 244, 2, // Opcode: CLIBAsmL /* 17994 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 18003 /* 17998 */ MCD_OPC_Decode, 247, 6, 244, 2, // Opcode: CLIBAsmLH /* 18003 */ MCD_OPC_FilterValue, 8, 5, 0, // Skip to: 18012 /* 18007 */ MCD_OPC_Decode, 242, 6, 244, 2, // Opcode: CLIBAsmE /* 18012 */ MCD_OPC_FilterValue, 10, 5, 0, // Skip to: 18021 /* 18016 */ MCD_OPC_Decode, 244, 6, 244, 2, // Opcode: CLIBAsmHE /* 18021 */ MCD_OPC_FilterValue, 12, 5, 0, // Skip to: 18030 /* 18025 */ MCD_OPC_Decode, 246, 6, 244, 2, // Opcode: CLIBAsmLE /* 18030 */ MCD_OPC_Decode, 241, 6, 245, 2, // Opcode: CLIBAsm /* 18035 */ MCD_OPC_FilterValue, 237, 1, 163, 3, // Skip to: 18971 /* 18040 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... /* 18043 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 18058 /* 18047 */ MCD_OPC_CheckField, 8, 8, 0, 14, 4, // Skip to: 19091 /* 18053 */ MCD_OPC_Decode, 149, 10, 246, 2, // Opcode: LDEB /* 18058 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 18073 /* 18062 */ MCD_OPC_CheckField, 8, 8, 0, 255, 3, // Skip to: 19091 /* 18068 */ MCD_OPC_Decode, 235, 12, 247, 2, // Opcode: LXDB /* 18073 */ MCD_OPC_FilterValue, 6, 11, 0, // Skip to: 18088 /* 18077 */ MCD_OPC_CheckField, 8, 8, 0, 240, 3, // Skip to: 19091 /* 18083 */ MCD_OPC_Decode, 240, 12, 247, 2, // Opcode: LXEB /* 18088 */ MCD_OPC_FilterValue, 7, 11, 0, // Skip to: 18103 /* 18092 */ MCD_OPC_CheckField, 8, 8, 0, 225, 3, // Skip to: 19091 /* 18098 */ MCD_OPC_Decode, 214, 13, 248, 2, // Opcode: MXDB /* 18103 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 18118 /* 18107 */ MCD_OPC_CheckField, 8, 8, 0, 210, 3, // Skip to: 19091 /* 18113 */ MCD_OPC_Decode, 223, 9, 249, 2, // Opcode: KEB /* 18118 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 18133 /* 18122 */ MCD_OPC_CheckField, 8, 8, 0, 195, 3, // Skip to: 19091 /* 18128 */ MCD_OPC_Decode, 165, 4, 249, 2, // Opcode: CEB /* 18133 */ MCD_OPC_FilterValue, 10, 11, 0, // Skip to: 18148 /* 18137 */ MCD_OPC_CheckField, 8, 8, 0, 180, 3, // Skip to: 19091 /* 18143 */ MCD_OPC_Decode, 236, 2, 250, 2, // Opcode: AEB /* 18148 */ MCD_OPC_FilterValue, 11, 11, 0, // Skip to: 18163 /* 18152 */ MCD_OPC_CheckField, 8, 8, 0, 165, 3, // Skip to: 19091 /* 18158 */ MCD_OPC_Decode, 197, 14, 250, 2, // Opcode: SEB /* 18163 */ MCD_OPC_FilterValue, 12, 11, 0, // Skip to: 18178 /* 18167 */ MCD_OPC_CheckField, 8, 8, 0, 150, 3, // Skip to: 19091 /* 18173 */ MCD_OPC_Decode, 142, 13, 251, 2, // Opcode: MDEB /* 18178 */ MCD_OPC_FilterValue, 13, 11, 0, // Skip to: 18193 /* 18182 */ MCD_OPC_CheckField, 8, 8, 0, 135, 3, // Skip to: 19091 /* 18188 */ MCD_OPC_Decode, 195, 8, 250, 2, // Opcode: DEB /* 18193 */ MCD_OPC_FilterValue, 14, 11, 0, // Skip to: 18208 /* 18197 */ MCD_OPC_CheckField, 8, 4, 0, 120, 3, // Skip to: 19091 /* 18203 */ MCD_OPC_Decode, 128, 13, 252, 2, // Opcode: MAEB /* 18208 */ MCD_OPC_FilterValue, 15, 11, 0, // Skip to: 18223 /* 18212 */ MCD_OPC_CheckField, 8, 4, 0, 105, 3, // Skip to: 19091 /* 18218 */ MCD_OPC_Decode, 176, 13, 252, 2, // Opcode: MSEB /* 18223 */ MCD_OPC_FilterValue, 16, 11, 0, // Skip to: 18238 /* 18227 */ MCD_OPC_CheckField, 8, 8, 0, 90, 3, // Skip to: 19091 /* 18233 */ MCD_OPC_Decode, 164, 16, 249, 2, // Opcode: TCEB /* 18238 */ MCD_OPC_FilterValue, 17, 11, 0, // Skip to: 18253 /* 18242 */ MCD_OPC_CheckField, 8, 8, 0, 75, 3, // Skip to: 19091 /* 18248 */ MCD_OPC_Decode, 163, 16, 246, 2, // Opcode: TCDB /* 18253 */ MCD_OPC_FilterValue, 18, 11, 0, // Skip to: 18268 /* 18257 */ MCD_OPC_CheckField, 8, 8, 0, 60, 3, // Skip to: 19091 /* 18263 */ MCD_OPC_Decode, 165, 16, 247, 2, // Opcode: TCXB /* 18268 */ MCD_OPC_FilterValue, 20, 11, 0, // Skip to: 18283 /* 18272 */ MCD_OPC_CheckField, 8, 8, 0, 45, 3, // Skip to: 19091 /* 18278 */ MCD_OPC_Decode, 253, 14, 249, 2, // Opcode: SQEB /* 18283 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 18298 /* 18287 */ MCD_OPC_CheckField, 8, 8, 0, 30, 3, // Skip to: 19091 /* 18293 */ MCD_OPC_Decode, 249, 14, 246, 2, // Opcode: SQDB /* 18298 */ MCD_OPC_FilterValue, 23, 11, 0, // Skip to: 18313 /* 18302 */ MCD_OPC_CheckField, 8, 8, 0, 15, 3, // Skip to: 19091 /* 18308 */ MCD_OPC_Decode, 150, 13, 250, 2, // Opcode: MEEB /* 18313 */ MCD_OPC_FilterValue, 24, 11, 0, // Skip to: 18328 /* 18317 */ MCD_OPC_CheckField, 8, 8, 0, 0, 3, // Skip to: 19091 /* 18323 */ MCD_OPC_Decode, 220, 9, 246, 2, // Opcode: KDB /* 18328 */ MCD_OPC_FilterValue, 25, 11, 0, // Skip to: 18343 /* 18332 */ MCD_OPC_CheckField, 8, 8, 0, 241, 2, // Skip to: 19091 /* 18338 */ MCD_OPC_Decode, 140, 4, 246, 2, // Opcode: CDB /* 18343 */ MCD_OPC_FilterValue, 26, 11, 0, // Skip to: 18358 /* 18347 */ MCD_OPC_CheckField, 8, 8, 0, 226, 2, // Skip to: 19091 /* 18353 */ MCD_OPC_Decode, 230, 2, 251, 2, // Opcode: ADB /* 18358 */ MCD_OPC_FilterValue, 27, 11, 0, // Skip to: 18373 /* 18362 */ MCD_OPC_CheckField, 8, 8, 0, 211, 2, // Skip to: 19091 /* 18368 */ MCD_OPC_Decode, 191, 14, 251, 2, // Opcode: SDB /* 18373 */ MCD_OPC_FilterValue, 28, 11, 0, // Skip to: 18388 /* 18377 */ MCD_OPC_CheckField, 8, 8, 0, 196, 2, // Skip to: 19091 /* 18383 */ MCD_OPC_Decode, 139, 13, 251, 2, // Opcode: MDB /* 18388 */ MCD_OPC_FilterValue, 29, 11, 0, // Skip to: 18403 /* 18392 */ MCD_OPC_CheckField, 8, 8, 0, 181, 2, // Skip to: 19091 /* 18398 */ MCD_OPC_Decode, 189, 8, 251, 2, // Opcode: DDB /* 18403 */ MCD_OPC_FilterValue, 30, 11, 0, // Skip to: 18418 /* 18407 */ MCD_OPC_CheckField, 8, 4, 0, 166, 2, // Skip to: 19091 /* 18413 */ MCD_OPC_Decode, 252, 12, 253, 2, // Opcode: MADB /* 18418 */ MCD_OPC_FilterValue, 31, 11, 0, // Skip to: 18433 /* 18422 */ MCD_OPC_CheckField, 8, 4, 0, 151, 2, // Skip to: 19091 /* 18428 */ MCD_OPC_Decode, 172, 13, 253, 2, // Opcode: MSDB /* 18433 */ MCD_OPC_FilterValue, 36, 11, 0, // Skip to: 18448 /* 18437 */ MCD_OPC_CheckField, 8, 8, 0, 136, 2, // Skip to: 19091 /* 18443 */ MCD_OPC_Decode, 147, 10, 246, 2, // Opcode: LDE /* 18448 */ MCD_OPC_FilterValue, 37, 11, 0, // Skip to: 18463 /* 18452 */ MCD_OPC_CheckField, 8, 8, 0, 121, 2, // Skip to: 19091 /* 18458 */ MCD_OPC_Decode, 234, 12, 247, 2, // Opcode: LXD /* 18463 */ MCD_OPC_FilterValue, 38, 11, 0, // Skip to: 18478 /* 18467 */ MCD_OPC_CheckField, 8, 8, 0, 106, 2, // Skip to: 19091 /* 18473 */ MCD_OPC_Decode, 239, 12, 247, 2, // Opcode: LXE /* 18478 */ MCD_OPC_FilterValue, 46, 11, 0, // Skip to: 18493 /* 18482 */ MCD_OPC_CheckField, 8, 4, 0, 91, 2, // Skip to: 19091 /* 18488 */ MCD_OPC_Decode, 255, 12, 252, 2, // Opcode: MAE /* 18493 */ MCD_OPC_FilterValue, 47, 11, 0, // Skip to: 18508 /* 18497 */ MCD_OPC_CheckField, 8, 4, 0, 76, 2, // Skip to: 19091 /* 18503 */ MCD_OPC_Decode, 175, 13, 252, 2, // Opcode: MSE /* 18508 */ MCD_OPC_FilterValue, 52, 11, 0, // Skip to: 18523 /* 18512 */ MCD_OPC_CheckField, 8, 8, 0, 61, 2, // Skip to: 19091 /* 18518 */ MCD_OPC_Decode, 252, 14, 249, 2, // Opcode: SQE /* 18523 */ MCD_OPC_FilterValue, 53, 11, 0, // Skip to: 18538 /* 18527 */ MCD_OPC_CheckField, 8, 8, 0, 46, 2, // Skip to: 19091 /* 18533 */ MCD_OPC_Decode, 248, 14, 246, 2, // Opcode: SQD /* 18538 */ MCD_OPC_FilterValue, 55, 11, 0, // Skip to: 18553 /* 18542 */ MCD_OPC_CheckField, 8, 8, 0, 31, 2, // Skip to: 19091 /* 18548 */ MCD_OPC_Decode, 149, 13, 250, 2, // Opcode: MEE /* 18553 */ MCD_OPC_FilterValue, 56, 11, 0, // Skip to: 18568 /* 18557 */ MCD_OPC_CheckField, 8, 4, 0, 16, 2, // Skip to: 19091 /* 18563 */ MCD_OPC_Decode, 134, 13, 253, 2, // Opcode: MAYL /* 18568 */ MCD_OPC_FilterValue, 57, 11, 0, // Skip to: 18583 /* 18572 */ MCD_OPC_CheckField, 8, 4, 0, 1, 2, // Skip to: 19091 /* 18578 */ MCD_OPC_Decode, 223, 13, 254, 2, // Opcode: MYL /* 18583 */ MCD_OPC_FilterValue, 58, 11, 0, // Skip to: 18598 /* 18587 */ MCD_OPC_CheckField, 8, 4, 0, 242, 1, // Skip to: 19091 /* 18593 */ MCD_OPC_Decode, 131, 13, 255, 2, // Opcode: MAY /* 18598 */ MCD_OPC_FilterValue, 59, 11, 0, // Skip to: 18613 /* 18602 */ MCD_OPC_CheckField, 8, 4, 0, 227, 1, // Skip to: 19091 /* 18608 */ MCD_OPC_Decode, 220, 13, 128, 3, // Opcode: MY /* 18613 */ MCD_OPC_FilterValue, 60, 11, 0, // Skip to: 18628 /* 18617 */ MCD_OPC_CheckField, 8, 4, 0, 212, 1, // Skip to: 19091 /* 18623 */ MCD_OPC_Decode, 132, 13, 253, 2, // Opcode: MAYH /* 18628 */ MCD_OPC_FilterValue, 61, 11, 0, // Skip to: 18643 /* 18632 */ MCD_OPC_CheckField, 8, 4, 0, 197, 1, // Skip to: 19091 /* 18638 */ MCD_OPC_Decode, 221, 13, 254, 2, // Opcode: MYH /* 18643 */ MCD_OPC_FilterValue, 62, 11, 0, // Skip to: 18658 /* 18647 */ MCD_OPC_CheckField, 8, 4, 0, 182, 1, // Skip to: 19091 /* 18653 */ MCD_OPC_Decode, 251, 12, 253, 2, // Opcode: MAD /* 18658 */ MCD_OPC_FilterValue, 63, 11, 0, // Skip to: 18673 /* 18662 */ MCD_OPC_CheckField, 8, 4, 0, 167, 1, // Skip to: 19091 /* 18668 */ MCD_OPC_Decode, 171, 13, 253, 2, // Opcode: MSD /* 18673 */ MCD_OPC_FilterValue, 64, 11, 0, // Skip to: 18688 /* 18677 */ MCD_OPC_CheckField, 8, 4, 0, 152, 1, // Skip to: 19091 /* 18683 */ MCD_OPC_Decode, 225, 14, 254, 2, // Opcode: SLDT /* 18688 */ MCD_OPC_FilterValue, 65, 11, 0, // Skip to: 18703 /* 18692 */ MCD_OPC_CheckField, 8, 4, 0, 137, 1, // Skip to: 19091 /* 18698 */ MCD_OPC_Decode, 136, 15, 254, 2, // Opcode: SRDT /* 18703 */ MCD_OPC_FilterValue, 72, 11, 0, // Skip to: 18718 /* 18707 */ MCD_OPC_CheckField, 8, 4, 0, 122, 1, // Skip to: 19091 /* 18713 */ MCD_OPC_Decode, 240, 14, 129, 3, // Opcode: SLXT /* 18718 */ MCD_OPC_FilterValue, 73, 11, 0, // Skip to: 18733 /* 18722 */ MCD_OPC_CheckField, 8, 4, 0, 107, 1, // Skip to: 19091 /* 18728 */ MCD_OPC_Decode, 147, 15, 129, 3, // Opcode: SRXT /* 18733 */ MCD_OPC_FilterValue, 80, 11, 0, // Skip to: 18748 /* 18737 */ MCD_OPC_CheckField, 8, 8, 0, 92, 1, // Skip to: 19091 /* 18743 */ MCD_OPC_Decode, 167, 16, 249, 2, // Opcode: TDCET /* 18748 */ MCD_OPC_FilterValue, 81, 11, 0, // Skip to: 18763 /* 18752 */ MCD_OPC_CheckField, 8, 8, 0, 77, 1, // Skip to: 19091 /* 18758 */ MCD_OPC_Decode, 170, 16, 249, 2, // Opcode: TDGET /* 18763 */ MCD_OPC_FilterValue, 84, 11, 0, // Skip to: 18778 /* 18767 */ MCD_OPC_CheckField, 8, 8, 0, 62, 1, // Skip to: 19091 /* 18773 */ MCD_OPC_Decode, 166, 16, 246, 2, // Opcode: TDCDT /* 18778 */ MCD_OPC_FilterValue, 85, 11, 0, // Skip to: 18793 /* 18782 */ MCD_OPC_CheckField, 8, 8, 0, 47, 1, // Skip to: 19091 /* 18788 */ MCD_OPC_Decode, 169, 16, 246, 2, // Opcode: TDGDT /* 18793 */ MCD_OPC_FilterValue, 88, 11, 0, // Skip to: 18808 /* 18797 */ MCD_OPC_CheckField, 8, 8, 0, 32, 1, // Skip to: 19091 /* 18803 */ MCD_OPC_Decode, 168, 16, 247, 2, // Opcode: TDCXT /* 18808 */ MCD_OPC_FilterValue, 89, 11, 0, // Skip to: 18823 /* 18812 */ MCD_OPC_CheckField, 8, 8, 0, 17, 1, // Skip to: 19091 /* 18818 */ MCD_OPC_Decode, 171, 16, 247, 2, // Opcode: TDGXT /* 18823 */ MCD_OPC_FilterValue, 100, 5, 0, // Skip to: 18832 /* 18827 */ MCD_OPC_Decode, 170, 10, 130, 3, // Opcode: LEY /* 18832 */ MCD_OPC_FilterValue, 101, 5, 0, // Skip to: 18841 /* 18836 */ MCD_OPC_Decode, 160, 10, 131, 3, // Opcode: LDY /* 18841 */ MCD_OPC_FilterValue, 102, 5, 0, // Skip to: 18850 /* 18845 */ MCD_OPC_Decode, 175, 15, 130, 3, // Opcode: STEY /* 18850 */ MCD_OPC_FilterValue, 103, 5, 0, // Skip to: 18859 /* 18854 */ MCD_OPC_Decode, 173, 15, 131, 3, // Opcode: STDY /* 18859 */ MCD_OPC_FilterValue, 168, 1, 9, 0, // Skip to: 18873 /* 18864 */ MCD_OPC_CheckPredicate, 25, 223, 0, // Skip to: 19091 /* 18868 */ MCD_OPC_Decode, 185, 8, 132, 3, // Opcode: CZDT /* 18873 */ MCD_OPC_FilterValue, 169, 1, 9, 0, // Skip to: 18887 /* 18878 */ MCD_OPC_CheckPredicate, 25, 209, 0, // Skip to: 19091 /* 18882 */ MCD_OPC_Decode, 186, 8, 133, 3, // Opcode: CZXT /* 18887 */ MCD_OPC_FilterValue, 170, 1, 9, 0, // Skip to: 18901 /* 18892 */ MCD_OPC_CheckPredicate, 25, 195, 0, // Skip to: 19091 /* 18896 */ MCD_OPC_Decode, 163, 4, 132, 3, // Opcode: CDZT /* 18901 */ MCD_OPC_FilterValue, 171, 1, 9, 0, // Skip to: 18915 /* 18906 */ MCD_OPC_CheckPredicate, 25, 181, 0, // Skip to: 19091 /* 18910 */ MCD_OPC_Decode, 183, 8, 133, 3, // Opcode: CXZT /* 18915 */ MCD_OPC_FilterValue, 172, 1, 9, 0, // Skip to: 18929 /* 18920 */ MCD_OPC_CheckPredicate, 26, 167, 0, // Skip to: 19091 /* 18924 */ MCD_OPC_Decode, 207, 7, 132, 3, // Opcode: CPDT /* 18929 */ MCD_OPC_FilterValue, 173, 1, 9, 0, // Skip to: 18943 /* 18934 */ MCD_OPC_CheckPredicate, 26, 153, 0, // Skip to: 19091 /* 18938 */ MCD_OPC_Decode, 212, 7, 133, 3, // Opcode: CPXT /* 18943 */ MCD_OPC_FilterValue, 174, 1, 9, 0, // Skip to: 18957 /* 18948 */ MCD_OPC_CheckPredicate, 26, 139, 0, // Skip to: 19091 /* 18952 */ MCD_OPC_Decode, 155, 4, 132, 3, // Opcode: CDPT /* 18957 */ MCD_OPC_FilterValue, 175, 1, 129, 0, // Skip to: 19091 /* 18962 */ MCD_OPC_CheckPredicate, 26, 125, 0, // Skip to: 19091 /* 18966 */ MCD_OPC_Decode, 178, 8, 133, 3, // Opcode: CXPT /* 18971 */ MCD_OPC_FilterValue, 238, 1, 5, 0, // Skip to: 18981 /* 18976 */ MCD_OPC_Decode, 145, 14, 134, 3, // Opcode: PLO /* 18981 */ MCD_OPC_FilterValue, 239, 1, 5, 0, // Skip to: 18991 /* 18986 */ MCD_OPC_Decode, 226, 10, 135, 3, // Opcode: LMD /* 18991 */ MCD_OPC_FilterValue, 240, 1, 5, 0, // Skip to: 19001 /* 18996 */ MCD_OPC_Decode, 144, 15, 136, 3, // Opcode: SRP /* 19001 */ MCD_OPC_FilterValue, 241, 1, 5, 0, // Skip to: 19011 /* 19006 */ MCD_OPC_Decode, 208, 13, 137, 3, // Opcode: MVO /* 19011 */ MCD_OPC_FilterValue, 242, 1, 5, 0, // Skip to: 19021 /* 19016 */ MCD_OPC_Decode, 132, 14, 137, 3, // Opcode: PACK /* 19021 */ MCD_OPC_FilterValue, 243, 1, 5, 0, // Skip to: 19031 /* 19026 */ MCD_OPC_Decode, 206, 16, 137, 3, // Opcode: UNPK /* 19031 */ MCD_OPC_FilterValue, 248, 1, 5, 0, // Skip to: 19041 /* 19036 */ MCD_OPC_Decode, 239, 21, 137, 3, // Opcode: ZAP /* 19041 */ MCD_OPC_FilterValue, 249, 1, 5, 0, // Skip to: 19051 /* 19046 */ MCD_OPC_Decode, 206, 7, 137, 3, // Opcode: CP /* 19051 */ MCD_OPC_FilterValue, 250, 1, 5, 0, // Skip to: 19061 /* 19056 */ MCD_OPC_Decode, 152, 3, 137, 3, // Opcode: AP /* 19061 */ MCD_OPC_FilterValue, 251, 1, 5, 0, // Skip to: 19071 /* 19066 */ MCD_OPC_Decode, 242, 14, 137, 3, // Opcode: SP /* 19071 */ MCD_OPC_FilterValue, 252, 1, 5, 0, // Skip to: 19081 /* 19076 */ MCD_OPC_Decode, 166, 13, 137, 3, // Opcode: MP /* 19081 */ MCD_OPC_FilterValue, 253, 1, 5, 0, // Skip to: 19091 /* 19086 */ MCD_OPC_Decode, 205, 8, 137, 3, // Opcode: DP /* 19091 */ MCD_OPC_Fail, 0 }; static bool getbool(uint64_t b) { return b != 0; } static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { default: // llvm_unreachable("Invalid index!"); case 0: return getbool((Bits & SystemZ_FeatureFPExtension)); case 1: return getbool((Bits & SystemZ_FeatureProcessorAssist)); case 2: return getbool((Bits & SystemZ_FeatureTransactionalExecution)); case 3: return getbool((Bits & SystemZ_FeatureExecutionHint)); case 4: return getbool((Bits & SystemZ_FeatureMessageSecurityAssist3)); case 5: return getbool((Bits & SystemZ_FeatureMessageSecurityAssist8)); case 6: return getbool((Bits & SystemZ_FeatureMessageSecurityAssist4)); case 7: return getbool((Bits & SystemZ_FeatureMessageSecurityAssist5)); case 8: return getbool((Bits & SystemZ_FeatureEnhancedDAT2)); case 9: return getbool((Bits & SystemZ_FeatureInsertReferenceBitsMultiple)); case 10: return getbool((Bits & SystemZ_FeatureResetReferenceBitsMultiple)); case 11: return getbool((Bits & SystemZ_FeatureHighWord)); case 12: return getbool((Bits & SystemZ_FeatureLoadStoreOnCond2)); case 13: return getbool((Bits & SystemZ_FeaturePopulationCount)); case 14: return getbool((Bits & SystemZ_FeatureLoadStoreOnCond)); case 15: return getbool((Bits & SystemZ_FeatureDistinctOps)); case 16: return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions2)); case 17: return getbool((Bits & SystemZ_FeatureInterlockedAccess1)); case 18: return getbool((Bits & SystemZ_FeatureLoadAndZeroRightmostByte)); case 19: return getbool((Bits & SystemZ_FeatureGuardedStorage)); case 20: return getbool((Bits & SystemZ_FeatureLoadAndTrap)); case 21: return getbool((Bits & SystemZ_FeatureVectorPackedDecimal)); case 22: return getbool((Bits & SystemZ_FeatureVector)); case 23: return getbool((Bits & SystemZ_FeatureVectorEnhancements1)); case 24: return getbool((Bits & SystemZ_FeatureMiscellaneousExtensions)); case 25: return getbool((Bits & SystemZ_FeatureDFPZonedConversion)); case 26: return getbool((Bits & SystemZ_FeatureDFPPackedConversion)); } } #define DecodeToMCInst(fname,fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, const void *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ default: \ case 0: \ return S; \ case 1: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 2: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 3: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 4: \ tmp = fieldname(insn, 0, 4); \ if (DecodeADDR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 5: \ tmp = fieldname(insn, 4, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 6: \ tmp = fieldname(insn, 0, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 7: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 8: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 9: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 10: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 11: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 12: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 13: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 14: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 15: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 16: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 17: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 18: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 19: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 20: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 21: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 22: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 23: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 24: \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 25: \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 26: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 27: \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 28: \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 29: \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 30: \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 31: \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 32: \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 33: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 34: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 35: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 36: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 37: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 38: \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 39: \ tmp = fieldname(insn, 20, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 40: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 41: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 42: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 43: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 44: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 45: \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 46: \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 47: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 48: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 49: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 50: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 51: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 52: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 53: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 54: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 55: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 56: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 57: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 58: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 59: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 60: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 61: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 62: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 63: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 64: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 65: \ tmp = fieldname(insn, 4, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 66: \ tmp = fieldname(insn, 4, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 67: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 68: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 69: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 70: \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 71: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 72: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 73: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 74: \ tmp = fieldname(insn, 4, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 75: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 76: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 77: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 78: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 79: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 80: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 81: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 82: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 83: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 84: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 85: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 86: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 87: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 88: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 89: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 90: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 91: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 92: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 93: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 94: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 95: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 96: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 97: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 98: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 99: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 100: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 101: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 102: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 103: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 104: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 105: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 106: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 107: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 108: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 109: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 110: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 111: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 112: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 113: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 114: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 115: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 116: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 117: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 118: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 119: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 120: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 121: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 122: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 123: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 124: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 125: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 126: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 127: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 128: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 129: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 130: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 131: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 132: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 133: \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 134: \ tmp = fieldname(insn, 20, 4); \ if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 135: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 136: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 137: \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 138: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 139: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 140: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 141: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 142: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 143: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 144: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 145: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 146: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 147: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 148: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 149: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 150: \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 151: \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 152: \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 153: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 154: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 155: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 156: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 157: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 158: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 159: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 160: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 161: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 162: \ tmp = fieldname(insn, 4, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 163: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 164: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 165: \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 166: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 167: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 168: \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 169: \ tmp = fieldname(insn, 36, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 170: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 171: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 172: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 173: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 174: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 175: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 176: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 177: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 178: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeU32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 179: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 180: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 181: \ tmp = fieldname(insn, 36, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 12); \ if (decodePC12DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 24); \ if (decodePC24DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 182: \ tmp = fieldname(insn, 36, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 183: \ tmp = fieldname(insn, 36, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 184: \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 185: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 186: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodePC32DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 187: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 188: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 32); \ if (decodeS32ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 189: \ tmp = fieldname(insn, 16, 24); \ if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 190: \ tmp = 0; \ tmp |= fieldname(insn, 16, 16) << 0; \ tmp |= fieldname(insn, 36, 4) << 16; \ if (decodeBDRAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 191: \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 0, 16) << 0; \ tmp |= fieldname(insn, 32, 8) << 16; \ if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 192: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 193: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 194: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 195: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 196: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 197: \ tmp = fieldname(insn, 36, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 198: \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 199: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 200: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 201: \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 202: \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 203: \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 204: \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 205: \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 206: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 207: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 208: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 209: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 210: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 211: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 212: \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 213: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 214: \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 215: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 216: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 217: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 218: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 219: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 220: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 221: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 222: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 223: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 224: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 20; \ tmp |= fieldname(insn, 16, 20) << 0; \ if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 225: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 20; \ tmp |= fieldname(insn, 16, 20) << 0; \ if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 226: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 20; \ tmp |= fieldname(insn, 16, 20) << 0; \ if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 227: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 20; \ tmp |= fieldname(insn, 16, 20) << 0; \ if (decodeBDVAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 228: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 229: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 230: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 231: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 232: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 233: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 234: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 235: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 236: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 237: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 238: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 239: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU3ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 240: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU1ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 241: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU2ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 242: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 243: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 244: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 245: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 246: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 247: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 248: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 249: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 250: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 251: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 12); \ if (decodeU12ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 252: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 253: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 254: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 255: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 256: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 257: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 258: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 259: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 260: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 261: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 262: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 263: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 264: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 265: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 266: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 22, 2) << 2; \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 267: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 3) << 1; \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 268: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 20, 1) << 0; \ tmp |= fieldname(insn, 22, 2) << 2; \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 269: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 22, 2) << 2; \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 270: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 21, 3) << 1; \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 271: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 20, 1) << 0; \ tmp |= fieldname(insn, 22, 2) << 2; \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 272: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 273: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 274: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 275: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 276: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 277: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 278: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 8, 1) << 4; \ tmp |= fieldname(insn, 12, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 279: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 280: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 281: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 282: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 283: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 284: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 285: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 286: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 287: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 288: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 3); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 289: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 290: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 291: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 292: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 293: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 294: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 295: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 296: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 297: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 298: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 299: \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 4; \ tmp |= fieldname(insn, 36, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 10, 1) << 4; \ tmp |= fieldname(insn, 32, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 9, 1) << 4; \ tmp |= fieldname(insn, 28, 4) << 0; \ if (DecodeVR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 20, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 300: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 301: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 302: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 303: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 304: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 305: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 306: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 307: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 308: \ tmp = fieldname(insn, 36, 4); \ if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeCR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 309: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 310: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 311: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 312: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 313: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 314: \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 315: \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 316: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 317: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 318: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr32Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 319: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 320: \ tmp = fieldname(insn, 36, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeAR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 321: \ tmp = 0; \ tmp |= fieldname(insn, 16, 16) << 0; \ tmp |= fieldname(insn, 36, 4) << 16; \ if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 322: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 323: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 324: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 325: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 326: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 327: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 328: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 329: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 24); \ if (decodeBDAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 330: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 331: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 332: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 333: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 334: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 335: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 336: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 337: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 338: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 339: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeGRH32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 24, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU6ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 340: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 341: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 342: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 343: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 344: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 345: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 346: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 347: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 348: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 349: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeU16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 350: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 351: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 352: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 353: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 354: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 355: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 356: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 357: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 358: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 359: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodePC16DBLBranchOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 360: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 361: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeS16ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 362: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 363: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 364: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 365: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 366: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 367: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 368: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 369: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 370: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 371: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeS8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 372: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 373: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 8); \ if (decodeU8ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 374: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 375: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 376: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 377: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 378: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 379: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 380: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 381: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 382: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 383: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 384: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 385: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 20); \ if (decodeBDXAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 386: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP32BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 387: \ tmp = fieldname(insn, 36, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 28); \ if (decodeBDXAddr64Disp20Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 388: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 24); \ if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 389: \ tmp = fieldname(insn, 12, 4); \ if (DecodeFP128BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 24); \ if (decodeBDLAddr64Disp12Len8Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 8, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 390: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 391: \ tmp = fieldname(insn, 36, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (DecodeGR64BitRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr64Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 392: \ tmp = 0; \ tmp |= fieldname(insn, 16, 16) << 0; \ tmp |= fieldname(insn, 36, 4) << 16; \ if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 16); \ if (decodeBDAddr32Disp12Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 32, 4); \ if (decodeU4ImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 393: \ tmp = 0; \ tmp |= fieldname(insn, 16, 16) << 0; \ tmp |= fieldname(insn, 36, 4) << 16; \ if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 0, 16) << 0; \ tmp |= fieldname(insn, 32, 4) << 16; \ if (decodeBDLAddr64Disp12Len4Operand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ { \ uint64_t Bits = getFeatureBits(feature); \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0, ExpectedValue; \ DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail; \ for (;;) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ Pred = checkDecoderPredicate(PIdx, Bits); \ if (!Pred) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_setOpcode(MI, Opc); \ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ } \ case MCD_OPC_SoftFail: { \ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ } FieldFromInstruction(fieldFromInstruction, uint64_t) DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint64_t) DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint64_t) capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc000064400000000000000000002103000072674642500235470ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { SYSZ_INS_A, "a" }, { SYSZ_INS_ADB, "adb" }, { SYSZ_INS_ADBR, "adbr" }, { SYSZ_INS_AEB, "aeb" }, { SYSZ_INS_AEBR, "aebr" }, { SYSZ_INS_AFI, "afi" }, { SYSZ_INS_AG, "ag" }, { SYSZ_INS_AGF, "agf" }, { SYSZ_INS_AGFI, "agfi" }, { SYSZ_INS_AGFR, "agfr" }, { SYSZ_INS_AGHI, "aghi" }, { SYSZ_INS_AGHIK, "aghik" }, { SYSZ_INS_AGR, "agr" }, { SYSZ_INS_AGRK, "agrk" }, { SYSZ_INS_AGSI, "agsi" }, { SYSZ_INS_AH, "ah" }, { SYSZ_INS_AHI, "ahi" }, { SYSZ_INS_AHIK, "ahik" }, { SYSZ_INS_AHY, "ahy" }, { SYSZ_INS_AIH, "aih" }, { SYSZ_INS_AL, "al" }, { SYSZ_INS_ALC, "alc" }, { SYSZ_INS_ALCG, "alcg" }, { SYSZ_INS_ALCGR, "alcgr" }, { SYSZ_INS_ALCR, "alcr" }, { SYSZ_INS_ALFI, "alfi" }, { SYSZ_INS_ALG, "alg" }, { SYSZ_INS_ALGF, "algf" }, { SYSZ_INS_ALGFI, "algfi" }, { SYSZ_INS_ALGFR, "algfr" }, { SYSZ_INS_ALGHSIK, "alghsik" }, { SYSZ_INS_ALGR, "algr" }, { SYSZ_INS_ALGRK, "algrk" }, { SYSZ_INS_ALHSIK, "alhsik" }, { SYSZ_INS_ALR, "alr" }, { SYSZ_INS_ALRK, "alrk" }, { SYSZ_INS_ALY, "aly" }, { SYSZ_INS_AR, "ar" }, { SYSZ_INS_ARK, "ark" }, { SYSZ_INS_ASI, "asi" }, { SYSZ_INS_AXBR, "axbr" }, { SYSZ_INS_AY, "ay" }, { SYSZ_INS_BCR, "bcr" }, { SYSZ_INS_BRC, "brc" }, { SYSZ_INS_BRCL, "brcl" }, { SYSZ_INS_CGIJ, "cgij" }, { SYSZ_INS_CGRJ, "cgrj" }, { SYSZ_INS_CIJ, "cij" }, { SYSZ_INS_CLGIJ, "clgij" }, { SYSZ_INS_CLGRJ, "clgrj" }, { SYSZ_INS_CLIJ, "clij" }, { SYSZ_INS_CLRJ, "clrj" }, { SYSZ_INS_CRJ, "crj" }, { SYSZ_INS_BER, "ber" }, { SYSZ_INS_JE, "je" }, { SYSZ_INS_JGE, "jge" }, { SYSZ_INS_LOCE, "loce" }, { SYSZ_INS_LOCGE, "locge" }, { SYSZ_INS_LOCGRE, "locgre" }, { SYSZ_INS_LOCRE, "locre" }, { SYSZ_INS_STOCE, "stoce" }, { SYSZ_INS_STOCGE, "stocge" }, { SYSZ_INS_BHR, "bhr" }, { SYSZ_INS_BHER, "bher" }, { SYSZ_INS_JHE, "jhe" }, { SYSZ_INS_JGHE, "jghe" }, { SYSZ_INS_LOCHE, "loche" }, { SYSZ_INS_LOCGHE, "locghe" }, { SYSZ_INS_LOCGRHE, "locgrhe" }, { SYSZ_INS_LOCRHE, "locrhe" }, { SYSZ_INS_STOCHE, "stoche" }, { SYSZ_INS_STOCGHE, "stocghe" }, { SYSZ_INS_JH, "jh" }, { SYSZ_INS_JGH, "jgh" }, { SYSZ_INS_LOCH, "loch" }, { SYSZ_INS_LOCGH, "locgh" }, { SYSZ_INS_LOCGRH, "locgrh" }, { SYSZ_INS_LOCRH, "locrh" }, { SYSZ_INS_STOCH, "stoch" }, { SYSZ_INS_STOCGH, "stocgh" }, { SYSZ_INS_CGIJNLH, "cgijnlh" }, { SYSZ_INS_CGRJNLH, "cgrjnlh" }, { SYSZ_INS_CIJNLH, "cijnlh" }, { SYSZ_INS_CLGIJNLH, "clgijnlh" }, { SYSZ_INS_CLGRJNLH, "clgrjnlh" }, { SYSZ_INS_CLIJNLH, "clijnlh" }, { SYSZ_INS_CLRJNLH, "clrjnlh" }, { SYSZ_INS_CRJNLH, "crjnlh" }, { SYSZ_INS_CGIJE, "cgije" }, { SYSZ_INS_CGRJE, "cgrje" }, { SYSZ_INS_CIJE, "cije" }, { SYSZ_INS_CLGIJE, "clgije" }, { SYSZ_INS_CLGRJE, "clgrje" }, { SYSZ_INS_CLIJE, "clije" }, { SYSZ_INS_CLRJE, "clrje" }, { SYSZ_INS_CRJE, "crje" }, { SYSZ_INS_CGIJNLE, "cgijnle" }, { SYSZ_INS_CGRJNLE, "cgrjnle" }, { SYSZ_INS_CIJNLE, "cijnle" }, { SYSZ_INS_CLGIJNLE, "clgijnle" }, { SYSZ_INS_CLGRJNLE, "clgrjnle" }, { SYSZ_INS_CLIJNLE, "clijnle" }, { SYSZ_INS_CLRJNLE, "clrjnle" }, { SYSZ_INS_CRJNLE, "crjnle" }, { SYSZ_INS_CGIJH, "cgijh" }, { SYSZ_INS_CGRJH, "cgrjh" }, { SYSZ_INS_CIJH, "cijh" }, { SYSZ_INS_CLGIJH, "clgijh" }, { SYSZ_INS_CLGRJH, "clgrjh" }, { SYSZ_INS_CLIJH, "clijh" }, { SYSZ_INS_CLRJH, "clrjh" }, { SYSZ_INS_CRJH, "crjh" }, { SYSZ_INS_CGIJNL, "cgijnl" }, { SYSZ_INS_CGRJNL, "cgrjnl" }, { SYSZ_INS_CIJNL, "cijnl" }, { SYSZ_INS_CLGIJNL, "clgijnl" }, { SYSZ_INS_CLGRJNL, "clgrjnl" }, { SYSZ_INS_CLIJNL, "clijnl" }, { SYSZ_INS_CLRJNL, "clrjnl" }, { SYSZ_INS_CRJNL, "crjnl" }, { SYSZ_INS_CGIJHE, "cgijhe" }, { SYSZ_INS_CGRJHE, "cgrjhe" }, { SYSZ_INS_CIJHE, "cijhe" }, { SYSZ_INS_CLGIJHE, "clgijhe" }, { SYSZ_INS_CLGRJHE, "clgrjhe" }, { SYSZ_INS_CLIJHE, "clijhe" }, { SYSZ_INS_CLRJHE, "clrjhe" }, { SYSZ_INS_CRJHE, "crjhe" }, { SYSZ_INS_CGIJNHE, "cgijnhe" }, { SYSZ_INS_CGRJNHE, "cgrjnhe" }, { SYSZ_INS_CIJNHE, "cijnhe" }, { SYSZ_INS_CLGIJNHE, "clgijnhe" }, { SYSZ_INS_CLGRJNHE, "clgrjnhe" }, { SYSZ_INS_CLIJNHE, "clijnhe" }, { SYSZ_INS_CLRJNHE, "clrjnhe" }, { SYSZ_INS_CRJNHE, "crjnhe" }, { SYSZ_INS_CGIJL, "cgijl" }, { SYSZ_INS_CGRJL, "cgrjl" }, { SYSZ_INS_CIJL, "cijl" }, { SYSZ_INS_CLGIJL, "clgijl" }, { SYSZ_INS_CLGRJL, "clgrjl" }, { SYSZ_INS_CLIJL, "clijl" }, { SYSZ_INS_CLRJL, "clrjl" }, { SYSZ_INS_CRJL, "crjl" }, { SYSZ_INS_CGIJNH, "cgijnh" }, { SYSZ_INS_CGRJNH, "cgrjnh" }, { SYSZ_INS_CIJNH, "cijnh" }, { SYSZ_INS_CLGIJNH, "clgijnh" }, { SYSZ_INS_CLGRJNH, "clgrjnh" }, { SYSZ_INS_CLIJNH, "clijnh" }, { SYSZ_INS_CLRJNH, "clrjnh" }, { SYSZ_INS_CRJNH, "crjnh" }, { SYSZ_INS_CGIJLE, "cgijle" }, { SYSZ_INS_CGRJLE, "cgrjle" }, { SYSZ_INS_CIJLE, "cijle" }, { SYSZ_INS_CLGIJLE, "clgijle" }, { SYSZ_INS_CLGRJLE, "clgrjle" }, { SYSZ_INS_CLIJLE, "clijle" }, { SYSZ_INS_CLRJLE, "clrjle" }, { SYSZ_INS_CRJLE, "crjle" }, { SYSZ_INS_CGIJNE, "cgijne" }, { SYSZ_INS_CGRJNE, "cgrjne" }, { SYSZ_INS_CIJNE, "cijne" }, { SYSZ_INS_CLGIJNE, "clgijne" }, { SYSZ_INS_CLGRJNE, "clgrjne" }, { SYSZ_INS_CLIJNE, "clijne" }, { SYSZ_INS_CLRJNE, "clrjne" }, { SYSZ_INS_CRJNE, "crjne" }, { SYSZ_INS_CGIJLH, "cgijlh" }, { SYSZ_INS_CGRJLH, "cgrjlh" }, { SYSZ_INS_CIJLH, "cijlh" }, { SYSZ_INS_CLGIJLH, "clgijlh" }, { SYSZ_INS_CLGRJLH, "clgrjlh" }, { SYSZ_INS_CLIJLH, "clijlh" }, { SYSZ_INS_CLRJLH, "clrjlh" }, { SYSZ_INS_CRJLH, "crjlh" }, { SYSZ_INS_BLR, "blr" }, { SYSZ_INS_BLER, "bler" }, { SYSZ_INS_JLE, "jle" }, { SYSZ_INS_JGLE, "jgle" }, { SYSZ_INS_LOCLE, "locle" }, { SYSZ_INS_LOCGLE, "locgle" }, { SYSZ_INS_LOCGRLE, "locgrle" }, { SYSZ_INS_LOCRLE, "locrle" }, { SYSZ_INS_STOCLE, "stocle" }, { SYSZ_INS_STOCGLE, "stocgle" }, { SYSZ_INS_BLHR, "blhr" }, { SYSZ_INS_JLH, "jlh" }, { SYSZ_INS_JGLH, "jglh" }, { SYSZ_INS_LOCLH, "loclh" }, { SYSZ_INS_LOCGLH, "locglh" }, { SYSZ_INS_LOCGRLH, "locgrlh" }, { SYSZ_INS_LOCRLH, "locrlh" }, { SYSZ_INS_STOCLH, "stoclh" }, { SYSZ_INS_STOCGLH, "stocglh" }, { SYSZ_INS_JL, "jl" }, { SYSZ_INS_JGL, "jgl" }, { SYSZ_INS_LOCL, "locl" }, { SYSZ_INS_LOCGL, "locgl" }, { SYSZ_INS_LOCGRL, "locgrl" }, { SYSZ_INS_LOCRL, "locrl" }, { SYSZ_INS_LOC, "loc" }, { SYSZ_INS_LOCG, "locg" }, { SYSZ_INS_LOCGR, "locgr" }, { SYSZ_INS_LOCR, "locr" }, { SYSZ_INS_STOCL, "stocl" }, { SYSZ_INS_STOCGL, "stocgl" }, { SYSZ_INS_BNER, "bner" }, { SYSZ_INS_JNE, "jne" }, { SYSZ_INS_JGNE, "jgne" }, { SYSZ_INS_LOCNE, "locne" }, { SYSZ_INS_LOCGNE, "locgne" }, { SYSZ_INS_LOCGRNE, "locgrne" }, { SYSZ_INS_LOCRNE, "locrne" }, { SYSZ_INS_STOCNE, "stocne" }, { SYSZ_INS_STOCGNE, "stocgne" }, { SYSZ_INS_BNHR, "bnhr" }, { SYSZ_INS_BNHER, "bnher" }, { SYSZ_INS_JNHE, "jnhe" }, { SYSZ_INS_JGNHE, "jgnhe" }, { SYSZ_INS_LOCNHE, "locnhe" }, { SYSZ_INS_LOCGNHE, "locgnhe" }, { SYSZ_INS_LOCGRNHE, "locgrnhe" }, { SYSZ_INS_LOCRNHE, "locrnhe" }, { SYSZ_INS_STOCNHE, "stocnhe" }, { SYSZ_INS_STOCGNHE, "stocgnhe" }, { SYSZ_INS_JNH, "jnh" }, { SYSZ_INS_JGNH, "jgnh" }, { SYSZ_INS_LOCNH, "locnh" }, { SYSZ_INS_LOCGNH, "locgnh" }, { SYSZ_INS_LOCGRNH, "locgrnh" }, { SYSZ_INS_LOCRNH, "locrnh" }, { SYSZ_INS_STOCNH, "stocnh" }, { SYSZ_INS_STOCGNH, "stocgnh" }, { SYSZ_INS_BNLR, "bnlr" }, { SYSZ_INS_BNLER, "bnler" }, { SYSZ_INS_JNLE, "jnle" }, { SYSZ_INS_JGNLE, "jgnle" }, { SYSZ_INS_LOCNLE, "locnle" }, { SYSZ_INS_LOCGNLE, "locgnle" }, { SYSZ_INS_LOCGRNLE, "locgrnle" }, { SYSZ_INS_LOCRNLE, "locrnle" }, { SYSZ_INS_STOCNLE, "stocnle" }, { SYSZ_INS_STOCGNLE, "stocgnle" }, { SYSZ_INS_BNLHR, "bnlhr" }, { SYSZ_INS_JNLH, "jnlh" }, { SYSZ_INS_JGNLH, "jgnlh" }, { SYSZ_INS_LOCNLH, "locnlh" }, { SYSZ_INS_LOCGNLH, "locgnlh" }, { SYSZ_INS_LOCGRNLH, "locgrnlh" }, { SYSZ_INS_LOCRNLH, "locrnlh" }, { SYSZ_INS_STOCNLH, "stocnlh" }, { SYSZ_INS_STOCGNLH, "stocgnlh" }, { SYSZ_INS_JNL, "jnl" }, { SYSZ_INS_JGNL, "jgnl" }, { SYSZ_INS_LOCNL, "locnl" }, { SYSZ_INS_LOCGNL, "locgnl" }, { SYSZ_INS_LOCGRNL, "locgrnl" }, { SYSZ_INS_LOCRNL, "locrnl" }, { SYSZ_INS_STOCNL, "stocnl" }, { SYSZ_INS_STOCGNL, "stocgnl" }, { SYSZ_INS_BNOR, "bnor" }, { SYSZ_INS_JNO, "jno" }, { SYSZ_INS_JGNO, "jgno" }, { SYSZ_INS_LOCNO, "locno" }, { SYSZ_INS_LOCGNO, "locgno" }, { SYSZ_INS_LOCGRNO, "locgrno" }, { SYSZ_INS_LOCRNO, "locrno" }, { SYSZ_INS_STOCNO, "stocno" }, { SYSZ_INS_STOCGNO, "stocgno" }, { SYSZ_INS_BOR, "bor" }, { SYSZ_INS_JO, "jo" }, { SYSZ_INS_JGO, "jgo" }, { SYSZ_INS_LOCO, "loco" }, { SYSZ_INS_LOCGO, "locgo" }, { SYSZ_INS_LOCGRO, "locgro" }, { SYSZ_INS_LOCRO, "locro" }, { SYSZ_INS_STOCO, "stoco" }, { SYSZ_INS_STOCGO, "stocgo" }, { SYSZ_INS_STOC, "stoc" }, { SYSZ_INS_STOCG, "stocg" }, { SYSZ_INS_BASR, "basr" }, { SYSZ_INS_BR, "br" }, { SYSZ_INS_BRAS, "bras" }, { SYSZ_INS_BRASL, "brasl" }, { SYSZ_INS_J, "j" }, { SYSZ_INS_JG, "jg" }, { SYSZ_INS_BRCT, "brct" }, { SYSZ_INS_BRCTG, "brctg" }, { SYSZ_INS_C, "c" }, { SYSZ_INS_CDB, "cdb" }, { SYSZ_INS_CDBR, "cdbr" }, { SYSZ_INS_CDFBR, "cdfbr" }, { SYSZ_INS_CDGBR, "cdgbr" }, { SYSZ_INS_CDLFBR, "cdlfbr" }, { SYSZ_INS_CDLGBR, "cdlgbr" }, { SYSZ_INS_CEB, "ceb" }, { SYSZ_INS_CEBR, "cebr" }, { SYSZ_INS_CEFBR, "cefbr" }, { SYSZ_INS_CEGBR, "cegbr" }, { SYSZ_INS_CELFBR, "celfbr" }, { SYSZ_INS_CELGBR, "celgbr" }, { SYSZ_INS_CFDBR, "cfdbr" }, { SYSZ_INS_CFEBR, "cfebr" }, { SYSZ_INS_CFI, "cfi" }, { SYSZ_INS_CFXBR, "cfxbr" }, { SYSZ_INS_CG, "cg" }, { SYSZ_INS_CGDBR, "cgdbr" }, { SYSZ_INS_CGEBR, "cgebr" }, { SYSZ_INS_CGF, "cgf" }, { SYSZ_INS_CGFI, "cgfi" }, { SYSZ_INS_CGFR, "cgfr" }, { SYSZ_INS_CGFRL, "cgfrl" }, { SYSZ_INS_CGH, "cgh" }, { SYSZ_INS_CGHI, "cghi" }, { SYSZ_INS_CGHRL, "cghrl" }, { SYSZ_INS_CGHSI, "cghsi" }, { SYSZ_INS_CGR, "cgr" }, { SYSZ_INS_CGRL, "cgrl" }, { SYSZ_INS_CGXBR, "cgxbr" }, { SYSZ_INS_CH, "ch" }, { SYSZ_INS_CHF, "chf" }, { SYSZ_INS_CHHSI, "chhsi" }, { SYSZ_INS_CHI, "chi" }, { SYSZ_INS_CHRL, "chrl" }, { SYSZ_INS_CHSI, "chsi" }, { SYSZ_INS_CHY, "chy" }, { SYSZ_INS_CIH, "cih" }, { SYSZ_INS_CL, "cl" }, { SYSZ_INS_CLC, "clc" }, { SYSZ_INS_CLFDBR, "clfdbr" }, { SYSZ_INS_CLFEBR, "clfebr" }, { SYSZ_INS_CLFHSI, "clfhsi" }, { SYSZ_INS_CLFI, "clfi" }, { SYSZ_INS_CLFXBR, "clfxbr" }, { SYSZ_INS_CLG, "clg" }, { SYSZ_INS_CLGDBR, "clgdbr" }, { SYSZ_INS_CLGEBR, "clgebr" }, { SYSZ_INS_CLGF, "clgf" }, { SYSZ_INS_CLGFI, "clgfi" }, { SYSZ_INS_CLGFR, "clgfr" }, { SYSZ_INS_CLGFRL, "clgfrl" }, { SYSZ_INS_CLGHRL, "clghrl" }, { SYSZ_INS_CLGHSI, "clghsi" }, { SYSZ_INS_CLGR, "clgr" }, { SYSZ_INS_CLGRL, "clgrl" }, { SYSZ_INS_CLGXBR, "clgxbr" }, { SYSZ_INS_CLHF, "clhf" }, { SYSZ_INS_CLHHSI, "clhhsi" }, { SYSZ_INS_CLHRL, "clhrl" }, { SYSZ_INS_CLI, "cli" }, { SYSZ_INS_CLIH, "clih" }, { SYSZ_INS_CLIY, "cliy" }, { SYSZ_INS_CLR, "clr" }, { SYSZ_INS_CLRL, "clrl" }, { SYSZ_INS_CLST, "clst" }, { SYSZ_INS_CLY, "cly" }, { SYSZ_INS_CPSDR, "cpsdr" }, { SYSZ_INS_CR, "cr" }, { SYSZ_INS_CRL, "crl" }, { SYSZ_INS_CS, "cs" }, { SYSZ_INS_CSG, "csg" }, { SYSZ_INS_CSY, "csy" }, { SYSZ_INS_CXBR, "cxbr" }, { SYSZ_INS_CXFBR, "cxfbr" }, { SYSZ_INS_CXGBR, "cxgbr" }, { SYSZ_INS_CXLFBR, "cxlfbr" }, { SYSZ_INS_CXLGBR, "cxlgbr" }, { SYSZ_INS_CY, "cy" }, { SYSZ_INS_DDB, "ddb" }, { SYSZ_INS_DDBR, "ddbr" }, { SYSZ_INS_DEB, "deb" }, { SYSZ_INS_DEBR, "debr" }, { SYSZ_INS_DL, "dl" }, { SYSZ_INS_DLG, "dlg" }, { SYSZ_INS_DLGR, "dlgr" }, { SYSZ_INS_DLR, "dlr" }, { SYSZ_INS_DSG, "dsg" }, { SYSZ_INS_DSGF, "dsgf" }, { SYSZ_INS_DSGFR, "dsgfr" }, { SYSZ_INS_DSGR, "dsgr" }, { SYSZ_INS_DXBR, "dxbr" }, { SYSZ_INS_EAR, "ear" }, { SYSZ_INS_FIDBR, "fidbr" }, { SYSZ_INS_FIDBRA, "fidbra" }, { SYSZ_INS_FIEBR, "fiebr" }, { SYSZ_INS_FIEBRA, "fiebra" }, { SYSZ_INS_FIXBR, "fixbr" }, { SYSZ_INS_FIXBRA, "fixbra" }, { SYSZ_INS_FLOGR, "flogr" }, { SYSZ_INS_IC, "ic" }, { SYSZ_INS_ICY, "icy" }, { SYSZ_INS_IIHF, "iihf" }, { SYSZ_INS_IIHH, "iihh" }, { SYSZ_INS_IIHL, "iihl" }, { SYSZ_INS_IILF, "iilf" }, { SYSZ_INS_IILH, "iilh" }, { SYSZ_INS_IILL, "iill" }, { SYSZ_INS_IPM, "ipm" }, { SYSZ_INS_L, "l" }, { SYSZ_INS_LA, "la" }, { SYSZ_INS_LAA, "laa" }, { SYSZ_INS_LAAG, "laag" }, { SYSZ_INS_LAAL, "laal" }, { SYSZ_INS_LAALG, "laalg" }, { SYSZ_INS_LAN, "lan" }, { SYSZ_INS_LANG, "lang" }, { SYSZ_INS_LAO, "lao" }, { SYSZ_INS_LAOG, "laog" }, { SYSZ_INS_LARL, "larl" }, { SYSZ_INS_LAX, "lax" }, { SYSZ_INS_LAXG, "laxg" }, { SYSZ_INS_LAY, "lay" }, { SYSZ_INS_LB, "lb" }, { SYSZ_INS_LBH, "lbh" }, { SYSZ_INS_LBR, "lbr" }, { SYSZ_INS_LCDBR, "lcdbr" }, { SYSZ_INS_LCEBR, "lcebr" }, { SYSZ_INS_LCGFR, "lcgfr" }, { SYSZ_INS_LCGR, "lcgr" }, { SYSZ_INS_LCR, "lcr" }, { SYSZ_INS_LCXBR, "lcxbr" }, { SYSZ_INS_LD, "ld" }, { SYSZ_INS_LDEB, "ldeb" }, { SYSZ_INS_LDEBR, "ldebr" }, { SYSZ_INS_LDGR, "ldgr" }, { SYSZ_INS_LDR, "ldr" }, { SYSZ_INS_LDXBR, "ldxbr" }, { SYSZ_INS_LDXBRA, "ldxbra" }, { SYSZ_INS_LDY, "ldy" }, { SYSZ_INS_LE, "le" }, { SYSZ_INS_LEDBR, "ledbr" }, { SYSZ_INS_LEDBRA, "ledbra" }, { SYSZ_INS_LER, "ler" }, { SYSZ_INS_LEXBR, "lexbr" }, { SYSZ_INS_LEXBRA, "lexbra" }, { SYSZ_INS_LEY, "ley" }, { SYSZ_INS_LFH, "lfh" }, { SYSZ_INS_LG, "lg" }, { SYSZ_INS_LGB, "lgb" }, { SYSZ_INS_LGBR, "lgbr" }, { SYSZ_INS_LGDR, "lgdr" }, { SYSZ_INS_LGF, "lgf" }, { SYSZ_INS_LGFI, "lgfi" }, { SYSZ_INS_LGFR, "lgfr" }, { SYSZ_INS_LGFRL, "lgfrl" }, { SYSZ_INS_LGH, "lgh" }, { SYSZ_INS_LGHI, "lghi" }, { SYSZ_INS_LGHR, "lghr" }, { SYSZ_INS_LGHRL, "lghrl" }, { SYSZ_INS_LGR, "lgr" }, { SYSZ_INS_LGRL, "lgrl" }, { SYSZ_INS_LH, "lh" }, { SYSZ_INS_LHH, "lhh" }, { SYSZ_INS_LHI, "lhi" }, { SYSZ_INS_LHR, "lhr" }, { SYSZ_INS_LHRL, "lhrl" }, { SYSZ_INS_LHY, "lhy" }, { SYSZ_INS_LLC, "llc" }, { SYSZ_INS_LLCH, "llch" }, { SYSZ_INS_LLCR, "llcr" }, { SYSZ_INS_LLGC, "llgc" }, { SYSZ_INS_LLGCR, "llgcr" }, { SYSZ_INS_LLGF, "llgf" }, { SYSZ_INS_LLGFR, "llgfr" }, { SYSZ_INS_LLGFRL, "llgfrl" }, { SYSZ_INS_LLGH, "llgh" }, { SYSZ_INS_LLGHR, "llghr" }, { SYSZ_INS_LLGHRL, "llghrl" }, { SYSZ_INS_LLH, "llh" }, { SYSZ_INS_LLHH, "llhh" }, { SYSZ_INS_LLHR, "llhr" }, { SYSZ_INS_LLHRL, "llhrl" }, { SYSZ_INS_LLIHF, "llihf" }, { SYSZ_INS_LLIHH, "llihh" }, { SYSZ_INS_LLIHL, "llihl" }, { SYSZ_INS_LLILF, "llilf" }, { SYSZ_INS_LLILH, "llilh" }, { SYSZ_INS_LLILL, "llill" }, { SYSZ_INS_LMG, "lmg" }, { SYSZ_INS_LNDBR, "lndbr" }, { SYSZ_INS_LNEBR, "lnebr" }, { SYSZ_INS_LNGFR, "lngfr" }, { SYSZ_INS_LNGR, "lngr" }, { SYSZ_INS_LNR, "lnr" }, { SYSZ_INS_LNXBR, "lnxbr" }, { SYSZ_INS_LPDBR, "lpdbr" }, { SYSZ_INS_LPEBR, "lpebr" }, { SYSZ_INS_LPGFR, "lpgfr" }, { SYSZ_INS_LPGR, "lpgr" }, { SYSZ_INS_LPR, "lpr" }, { SYSZ_INS_LPXBR, "lpxbr" }, { SYSZ_INS_LR, "lr" }, { SYSZ_INS_LRL, "lrl" }, { SYSZ_INS_LRV, "lrv" }, { SYSZ_INS_LRVG, "lrvg" }, { SYSZ_INS_LRVGR, "lrvgr" }, { SYSZ_INS_LRVR, "lrvr" }, { SYSZ_INS_LT, "lt" }, { SYSZ_INS_LTDBR, "ltdbr" }, { SYSZ_INS_LTEBR, "ltebr" }, { SYSZ_INS_LTG, "ltg" }, { SYSZ_INS_LTGF, "ltgf" }, { SYSZ_INS_LTGFR, "ltgfr" }, { SYSZ_INS_LTGR, "ltgr" }, { SYSZ_INS_LTR, "ltr" }, { SYSZ_INS_LTXBR, "ltxbr" }, { SYSZ_INS_LXDB, "lxdb" }, { SYSZ_INS_LXDBR, "lxdbr" }, { SYSZ_INS_LXEB, "lxeb" }, { SYSZ_INS_LXEBR, "lxebr" }, { SYSZ_INS_LXR, "lxr" }, { SYSZ_INS_LY, "ly" }, { SYSZ_INS_LZDR, "lzdr" }, { SYSZ_INS_LZER, "lzer" }, { SYSZ_INS_LZXR, "lzxr" }, { SYSZ_INS_MADB, "madb" }, { SYSZ_INS_MADBR, "madbr" }, { SYSZ_INS_MAEB, "maeb" }, { SYSZ_INS_MAEBR, "maebr" }, { SYSZ_INS_MDB, "mdb" }, { SYSZ_INS_MDBR, "mdbr" }, { SYSZ_INS_MDEB, "mdeb" }, { SYSZ_INS_MDEBR, "mdebr" }, { SYSZ_INS_MEEB, "meeb" }, { SYSZ_INS_MEEBR, "meebr" }, { SYSZ_INS_MGHI, "mghi" }, { SYSZ_INS_MH, "mh" }, { SYSZ_INS_MHI, "mhi" }, { SYSZ_INS_MHY, "mhy" }, { SYSZ_INS_MLG, "mlg" }, { SYSZ_INS_MLGR, "mlgr" }, { SYSZ_INS_MS, "ms" }, { SYSZ_INS_MSDB, "msdb" }, { SYSZ_INS_MSDBR, "msdbr" }, { SYSZ_INS_MSEB, "mseb" }, { SYSZ_INS_MSEBR, "msebr" }, { SYSZ_INS_MSFI, "msfi" }, { SYSZ_INS_MSG, "msg" }, { SYSZ_INS_MSGF, "msgf" }, { SYSZ_INS_MSGFI, "msgfi" }, { SYSZ_INS_MSGFR, "msgfr" }, { SYSZ_INS_MSGR, "msgr" }, { SYSZ_INS_MSR, "msr" }, { SYSZ_INS_MSY, "msy" }, { SYSZ_INS_MVC, "mvc" }, { SYSZ_INS_MVGHI, "mvghi" }, { SYSZ_INS_MVHHI, "mvhhi" }, { SYSZ_INS_MVHI, "mvhi" }, { SYSZ_INS_MVI, "mvi" }, { SYSZ_INS_MVIY, "mviy" }, { SYSZ_INS_MVST, "mvst" }, { SYSZ_INS_MXBR, "mxbr" }, { SYSZ_INS_MXDB, "mxdb" }, { SYSZ_INS_MXDBR, "mxdbr" }, { SYSZ_INS_N, "n" }, { SYSZ_INS_NC, "nc" }, { SYSZ_INS_NG, "ng" }, { SYSZ_INS_NGR, "ngr" }, { SYSZ_INS_NGRK, "ngrk" }, { SYSZ_INS_NI, "ni" }, { SYSZ_INS_NIHF, "nihf" }, { SYSZ_INS_NIHH, "nihh" }, { SYSZ_INS_NIHL, "nihl" }, { SYSZ_INS_NILF, "nilf" }, { SYSZ_INS_NILH, "nilh" }, { SYSZ_INS_NILL, "nill" }, { SYSZ_INS_NIY, "niy" }, { SYSZ_INS_NR, "nr" }, { SYSZ_INS_NRK, "nrk" }, { SYSZ_INS_NY, "ny" }, { SYSZ_INS_O, "o" }, { SYSZ_INS_OC, "oc" }, { SYSZ_INS_OG, "og" }, { SYSZ_INS_OGR, "ogr" }, { SYSZ_INS_OGRK, "ogrk" }, { SYSZ_INS_OI, "oi" }, { SYSZ_INS_OIHF, "oihf" }, { SYSZ_INS_OIHH, "oihh" }, { SYSZ_INS_OIHL, "oihl" }, { SYSZ_INS_OILF, "oilf" }, { SYSZ_INS_OILH, "oilh" }, { SYSZ_INS_OILL, "oill" }, { SYSZ_INS_OIY, "oiy" }, { SYSZ_INS_OR, "or" }, { SYSZ_INS_ORK, "ork" }, { SYSZ_INS_OY, "oy" }, { SYSZ_INS_PFD, "pfd" }, { SYSZ_INS_PFDRL, "pfdrl" }, { SYSZ_INS_RISBG, "risbg" }, { SYSZ_INS_RISBHG, "risbhg" }, { SYSZ_INS_RISBLG, "risblg" }, { SYSZ_INS_RLL, "rll" }, { SYSZ_INS_RLLG, "rllg" }, { SYSZ_INS_RNSBG, "rnsbg" }, { SYSZ_INS_ROSBG, "rosbg" }, { SYSZ_INS_RXSBG, "rxsbg" }, { SYSZ_INS_S, "s" }, { SYSZ_INS_SDB, "sdb" }, { SYSZ_INS_SDBR, "sdbr" }, { SYSZ_INS_SEB, "seb" }, { SYSZ_INS_SEBR, "sebr" }, { SYSZ_INS_SG, "sg" }, { SYSZ_INS_SGF, "sgf" }, { SYSZ_INS_SGFR, "sgfr" }, { SYSZ_INS_SGR, "sgr" }, { SYSZ_INS_SGRK, "sgrk" }, { SYSZ_INS_SH, "sh" }, { SYSZ_INS_SHY, "shy" }, { SYSZ_INS_SL, "sl" }, { SYSZ_INS_SLB, "slb" }, { SYSZ_INS_SLBG, "slbg" }, { SYSZ_INS_SLBR, "slbr" }, { SYSZ_INS_SLFI, "slfi" }, { SYSZ_INS_SLG, "slg" }, { SYSZ_INS_SLBGR, "slbgr" }, { SYSZ_INS_SLGF, "slgf" }, { SYSZ_INS_SLGFI, "slgfi" }, { SYSZ_INS_SLGFR, "slgfr" }, { SYSZ_INS_SLGR, "slgr" }, { SYSZ_INS_SLGRK, "slgrk" }, { SYSZ_INS_SLL, "sll" }, { SYSZ_INS_SLLG, "sllg" }, { SYSZ_INS_SLLK, "sllk" }, { SYSZ_INS_SLR, "slr" }, { SYSZ_INS_SLRK, "slrk" }, { SYSZ_INS_SLY, "sly" }, { SYSZ_INS_SQDB, "sqdb" }, { SYSZ_INS_SQDBR, "sqdbr" }, { SYSZ_INS_SQEB, "sqeb" }, { SYSZ_INS_SQEBR, "sqebr" }, { SYSZ_INS_SQXBR, "sqxbr" }, { SYSZ_INS_SR, "sr" }, { SYSZ_INS_SRA, "sra" }, { SYSZ_INS_SRAG, "srag" }, { SYSZ_INS_SRAK, "srak" }, { SYSZ_INS_SRK, "srk" }, { SYSZ_INS_SRL, "srl" }, { SYSZ_INS_SRLG, "srlg" }, { SYSZ_INS_SRLK, "srlk" }, { SYSZ_INS_SRST, "srst" }, { SYSZ_INS_ST, "st" }, { SYSZ_INS_STC, "stc" }, { SYSZ_INS_STCH, "stch" }, { SYSZ_INS_STCY, "stcy" }, { SYSZ_INS_STD, "std" }, { SYSZ_INS_STDY, "stdy" }, { SYSZ_INS_STE, "ste" }, { SYSZ_INS_STEY, "stey" }, { SYSZ_INS_STFH, "stfh" }, { SYSZ_INS_STG, "stg" }, { SYSZ_INS_STGRL, "stgrl" }, { SYSZ_INS_STH, "sth" }, { SYSZ_INS_STHH, "sthh" }, { SYSZ_INS_STHRL, "sthrl" }, { SYSZ_INS_STHY, "sthy" }, { SYSZ_INS_STMG, "stmg" }, { SYSZ_INS_STRL, "strl" }, { SYSZ_INS_STRV, "strv" }, { SYSZ_INS_STRVG, "strvg" }, { SYSZ_INS_STY, "sty" }, { SYSZ_INS_SXBR, "sxbr" }, { SYSZ_INS_SY, "sy" }, { SYSZ_INS_TM, "tm" }, { SYSZ_INS_TMHH, "tmhh" }, { SYSZ_INS_TMHL, "tmhl" }, { SYSZ_INS_TMLH, "tmlh" }, { SYSZ_INS_TMLL, "tmll" }, { SYSZ_INS_TMY, "tmy" }, { SYSZ_INS_X, "x" }, { SYSZ_INS_XC, "xc" }, { SYSZ_INS_XG, "xg" }, { SYSZ_INS_XGR, "xgr" }, { SYSZ_INS_XGRK, "xgrk" }, { SYSZ_INS_XI, "xi" }, { SYSZ_INS_XIHF, "xihf" }, { SYSZ_INS_XILF, "xilf" }, { SYSZ_INS_XIY, "xiy" }, { SYSZ_INS_XR, "xr" }, { SYSZ_INS_XRK, "xrk" }, { SYSZ_INS_XY, "xy" }, { SYSZ_INS_AD, "ad" }, { SYSZ_INS_ADR, "adr" }, { SYSZ_INS_ADTR, "adtr" }, { SYSZ_INS_ADTRA, "adtra" }, { SYSZ_INS_AE, "ae" }, { SYSZ_INS_AER, "aer" }, { SYSZ_INS_AGH, "agh" }, { SYSZ_INS_AHHHR, "ahhhr" }, { SYSZ_INS_AHHLR, "ahhlr" }, { SYSZ_INS_ALGSI, "algsi" }, { SYSZ_INS_ALHHHR, "alhhhr" }, { SYSZ_INS_ALHHLR, "alhhlr" }, { SYSZ_INS_ALSI, "alsi" }, { SYSZ_INS_ALSIH, "alsih" }, { SYSZ_INS_ALSIHN, "alsihn" }, { SYSZ_INS_AP, "ap" }, { SYSZ_INS_AU, "au" }, { SYSZ_INS_AUR, "aur" }, { SYSZ_INS_AW, "aw" }, { SYSZ_INS_AWR, "awr" }, { SYSZ_INS_AXR, "axr" }, { SYSZ_INS_AXTR, "axtr" }, { SYSZ_INS_AXTRA, "axtra" }, { SYSZ_INS_B, "b" }, { SYSZ_INS_BAKR, "bakr" }, { SYSZ_INS_BAL, "bal" }, { SYSZ_INS_BALR, "balr" }, { SYSZ_INS_BAS, "bas" }, { SYSZ_INS_BASSM, "bassm" }, { SYSZ_INS_BC, "bc" }, { SYSZ_INS_BCT, "bct" }, { SYSZ_INS_BCTG, "bctg" }, { SYSZ_INS_BCTGR, "bctgr" }, { SYSZ_INS_BCTR, "bctr" }, { SYSZ_INS_BE, "be" }, { SYSZ_INS_BH, "bh" }, { SYSZ_INS_BHE, "bhe" }, { SYSZ_INS_BI, "bi" }, { SYSZ_INS_BIC, "bic" }, { SYSZ_INS_BIE, "bie" }, { SYSZ_INS_BIH, "bih" }, { SYSZ_INS_BIHE, "bihe" }, { SYSZ_INS_BIL, "bil" }, { SYSZ_INS_BILE, "bile" }, { SYSZ_INS_BILH, "bilh" }, { SYSZ_INS_BIM, "bim" }, { SYSZ_INS_BINE, "bine" }, { SYSZ_INS_BINH, "binh" }, { SYSZ_INS_BINHE, "binhe" }, { SYSZ_INS_BINL, "binl" }, { SYSZ_INS_BINLE, "binle" }, { SYSZ_INS_BINLH, "binlh" }, { SYSZ_INS_BINM, "binm" }, { SYSZ_INS_BINO, "bino" }, { SYSZ_INS_BINP, "binp" }, { SYSZ_INS_BINZ, "binz" }, { SYSZ_INS_BIO, "bio" }, { SYSZ_INS_BIP, "bip" }, { SYSZ_INS_BIZ, "biz" }, { SYSZ_INS_BL, "bl" }, { SYSZ_INS_BLE, "ble" }, { SYSZ_INS_BLH, "blh" }, { SYSZ_INS_BM, "bm" }, { SYSZ_INS_BMR, "bmr" }, { SYSZ_INS_BNE, "bne" }, { SYSZ_INS_BNH, "bnh" }, { SYSZ_INS_BNHE, "bnhe" }, { SYSZ_INS_BNL, "bnl" }, { SYSZ_INS_BNLE, "bnle" }, { SYSZ_INS_BNLH, "bnlh" }, { SYSZ_INS_BNM, "bnm" }, { SYSZ_INS_BNMR, "bnmr" }, { SYSZ_INS_BNO, "bno" }, { SYSZ_INS_BNP, "bnp" }, { SYSZ_INS_BNPR, "bnpr" }, { SYSZ_INS_BNZ, "bnz" }, { SYSZ_INS_BNZR, "bnzr" }, { SYSZ_INS_BO, "bo" }, { SYSZ_INS_BP, "bp" }, { SYSZ_INS_BPP, "bpp" }, { SYSZ_INS_BPR, "bpr" }, { SYSZ_INS_BPRP, "bprp" }, { SYSZ_INS_BRCTH, "brcth" }, { SYSZ_INS_BRXH, "brxh" }, { SYSZ_INS_BRXHG, "brxhg" }, { SYSZ_INS_BRXLE, "brxle" }, { SYSZ_INS_BRXLG, "brxlg" }, { SYSZ_INS_BSA, "bsa" }, { SYSZ_INS_BSG, "bsg" }, { SYSZ_INS_BSM, "bsm" }, { SYSZ_INS_BXH, "bxh" }, { SYSZ_INS_BXHG, "bxhg" }, { SYSZ_INS_BXLE, "bxle" }, { SYSZ_INS_BXLEG, "bxleg" }, { SYSZ_INS_BZ, "bz" }, { SYSZ_INS_BZR, "bzr" }, { SYSZ_INS_CD, "cd" }, { SYSZ_INS_CDFBRA, "cdfbra" }, { SYSZ_INS_CDFR, "cdfr" }, { SYSZ_INS_CDFTR, "cdftr" }, { SYSZ_INS_CDGBRA, "cdgbra" }, { SYSZ_INS_CDGR, "cdgr" }, { SYSZ_INS_CDGTR, "cdgtr" }, { SYSZ_INS_CDGTRA, "cdgtra" }, { SYSZ_INS_CDLFTR, "cdlftr" }, { SYSZ_INS_CDLGTR, "cdlgtr" }, { SYSZ_INS_CDPT, "cdpt" }, { SYSZ_INS_CDR, "cdr" }, { SYSZ_INS_CDS, "cds" }, { SYSZ_INS_CDSG, "cdsg" }, { SYSZ_INS_CDSTR, "cdstr" }, { SYSZ_INS_CDSY, "cdsy" }, { SYSZ_INS_CDTR, "cdtr" }, { SYSZ_INS_CDUTR, "cdutr" }, { SYSZ_INS_CDZT, "cdzt" }, { SYSZ_INS_CE, "ce" }, { SYSZ_INS_CEDTR, "cedtr" }, { SYSZ_INS_CEFBRA, "cefbra" }, { SYSZ_INS_CEFR, "cefr" }, { SYSZ_INS_CEGBRA, "cegbra" }, { SYSZ_INS_CEGR, "cegr" }, { SYSZ_INS_CER, "cer" }, { SYSZ_INS_CEXTR, "cextr" }, { SYSZ_INS_CFC, "cfc" }, { SYSZ_INS_CFDBRA, "cfdbra" }, { SYSZ_INS_CFDR, "cfdr" }, { SYSZ_INS_CFDTR, "cfdtr" }, { SYSZ_INS_CFEBRA, "cfebra" }, { SYSZ_INS_CFER, "cfer" }, { SYSZ_INS_CFXBRA, "cfxbra" }, { SYSZ_INS_CFXR, "cfxr" }, { SYSZ_INS_CFXTR, "cfxtr" }, { SYSZ_INS_CGDBRA, "cgdbra" }, { SYSZ_INS_CGDR, "cgdr" }, { SYSZ_INS_CGDTR, "cgdtr" }, { SYSZ_INS_CGDTRA, "cgdtra" }, { SYSZ_INS_CGEBRA, "cgebra" }, { SYSZ_INS_CGER, "cger" }, { SYSZ_INS_CGIB, "cgib" }, { SYSZ_INS_CGIBE, "cgibe" }, { SYSZ_INS_CGIBH, "cgibh" }, { SYSZ_INS_CGIBHE, "cgibhe" }, { SYSZ_INS_CGIBL, "cgibl" }, { SYSZ_INS_CGIBLE, "cgible" }, { SYSZ_INS_CGIBLH, "cgiblh" }, { SYSZ_INS_CGIBNE, "cgibne" }, { SYSZ_INS_CGIBNH, "cgibnh" }, { SYSZ_INS_CGIBNHE, "cgibnhe" }, { SYSZ_INS_CGIBNL, "cgibnl" }, { SYSZ_INS_CGIBNLE, "cgibnle" }, { SYSZ_INS_CGIBNLH, "cgibnlh" }, { SYSZ_INS_CGIT, "cgit" }, { SYSZ_INS_CGITE, "cgite" }, { SYSZ_INS_CGITH, "cgith" }, { SYSZ_INS_CGITHE, "cgithe" }, { SYSZ_INS_CGITL, "cgitl" }, { SYSZ_INS_CGITLE, "cgitle" }, { SYSZ_INS_CGITLH, "cgitlh" }, { SYSZ_INS_CGITNE, "cgitne" }, { SYSZ_INS_CGITNH, "cgitnh" }, { SYSZ_INS_CGITNHE, "cgitnhe" }, { SYSZ_INS_CGITNL, "cgitnl" }, { SYSZ_INS_CGITNLE, "cgitnle" }, { SYSZ_INS_CGITNLH, "cgitnlh" }, { SYSZ_INS_CGRB, "cgrb" }, { SYSZ_INS_CGRBE, "cgrbe" }, { SYSZ_INS_CGRBH, "cgrbh" }, { SYSZ_INS_CGRBHE, "cgrbhe" }, { SYSZ_INS_CGRBL, "cgrbl" }, { SYSZ_INS_CGRBLE, "cgrble" }, { SYSZ_INS_CGRBLH, "cgrblh" }, { SYSZ_INS_CGRBNE, "cgrbne" }, { SYSZ_INS_CGRBNH, "cgrbnh" }, { SYSZ_INS_CGRBNHE, "cgrbnhe" }, { SYSZ_INS_CGRBNL, "cgrbnl" }, { SYSZ_INS_CGRBNLE, "cgrbnle" }, { SYSZ_INS_CGRBNLH, "cgrbnlh" }, { SYSZ_INS_CGRT, "cgrt" }, { SYSZ_INS_CGRTE, "cgrte" }, { SYSZ_INS_CGRTH, "cgrth" }, { SYSZ_INS_CGRTHE, "cgrthe" }, { SYSZ_INS_CGRTL, "cgrtl" }, { SYSZ_INS_CGRTLE, "cgrtle" }, { SYSZ_INS_CGRTLH, "cgrtlh" }, { SYSZ_INS_CGRTNE, "cgrtne" }, { SYSZ_INS_CGRTNH, "cgrtnh" }, { SYSZ_INS_CGRTNHE, "cgrtnhe" }, { SYSZ_INS_CGRTNL, "cgrtnl" }, { SYSZ_INS_CGRTNLE, "cgrtnle" }, { SYSZ_INS_CGRTNLH, "cgrtnlh" }, { SYSZ_INS_CGXBRA, "cgxbra" }, { SYSZ_INS_CGXR, "cgxr" }, { SYSZ_INS_CGXTR, "cgxtr" }, { SYSZ_INS_CGXTRA, "cgxtra" }, { SYSZ_INS_CHHR, "chhr" }, { SYSZ_INS_CHLR, "chlr" }, { SYSZ_INS_CIB, "cib" }, { SYSZ_INS_CIBE, "cibe" }, { SYSZ_INS_CIBH, "cibh" }, { SYSZ_INS_CIBHE, "cibhe" }, { SYSZ_INS_CIBL, "cibl" }, { SYSZ_INS_CIBLE, "cible" }, { SYSZ_INS_CIBLH, "ciblh" }, { SYSZ_INS_CIBNE, "cibne" }, { SYSZ_INS_CIBNH, "cibnh" }, { SYSZ_INS_CIBNHE, "cibnhe" }, { SYSZ_INS_CIBNL, "cibnl" }, { SYSZ_INS_CIBNLE, "cibnle" }, { SYSZ_INS_CIBNLH, "cibnlh" }, { SYSZ_INS_CIT, "cit" }, { SYSZ_INS_CITE, "cite" }, { SYSZ_INS_CITH, "cith" }, { SYSZ_INS_CITHE, "cithe" }, { SYSZ_INS_CITL, "citl" }, { SYSZ_INS_CITLE, "citle" }, { SYSZ_INS_CITLH, "citlh" }, { SYSZ_INS_CITNE, "citne" }, { SYSZ_INS_CITNH, "citnh" }, { SYSZ_INS_CITNHE, "citnhe" }, { SYSZ_INS_CITNL, "citnl" }, { SYSZ_INS_CITNLE, "citnle" }, { SYSZ_INS_CITNLH, "citnlh" }, { SYSZ_INS_CKSM, "cksm" }, { SYSZ_INS_CLCL, "clcl" }, { SYSZ_INS_CLCLE, "clcle" }, { SYSZ_INS_CLCLU, "clclu" }, { SYSZ_INS_CLFDTR, "clfdtr" }, { SYSZ_INS_CLFIT, "clfit" }, { SYSZ_INS_CLFITE, "clfite" }, { SYSZ_INS_CLFITH, "clfith" }, { SYSZ_INS_CLFITHE, "clfithe" }, { SYSZ_INS_CLFITL, "clfitl" }, { SYSZ_INS_CLFITLE, "clfitle" }, { SYSZ_INS_CLFITLH, "clfitlh" }, { SYSZ_INS_CLFITNE, "clfitne" }, { SYSZ_INS_CLFITNH, "clfitnh" }, { SYSZ_INS_CLFITNHE, "clfitnhe" }, { SYSZ_INS_CLFITNL, "clfitnl" }, { SYSZ_INS_CLFITNLE, "clfitnle" }, { SYSZ_INS_CLFITNLH, "clfitnlh" }, { SYSZ_INS_CLFXTR, "clfxtr" }, { SYSZ_INS_CLGDTR, "clgdtr" }, { SYSZ_INS_CLGIB, "clgib" }, { SYSZ_INS_CLGIBE, "clgibe" }, { SYSZ_INS_CLGIBH, "clgibh" }, { SYSZ_INS_CLGIBHE, "clgibhe" }, { SYSZ_INS_CLGIBL, "clgibl" }, { SYSZ_INS_CLGIBLE, "clgible" }, { SYSZ_INS_CLGIBLH, "clgiblh" }, { SYSZ_INS_CLGIBNE, "clgibne" }, { SYSZ_INS_CLGIBNH, "clgibnh" }, { SYSZ_INS_CLGIBNHE, "clgibnhe" }, { SYSZ_INS_CLGIBNL, "clgibnl" }, { SYSZ_INS_CLGIBNLE, "clgibnle" }, { SYSZ_INS_CLGIBNLH, "clgibnlh" }, { SYSZ_INS_CLGIT, "clgit" }, { SYSZ_INS_CLGITE, "clgite" }, { SYSZ_INS_CLGITH, "clgith" }, { SYSZ_INS_CLGITHE, "clgithe" }, { SYSZ_INS_CLGITL, "clgitl" }, { SYSZ_INS_CLGITLE, "clgitle" }, { SYSZ_INS_CLGITLH, "clgitlh" }, { SYSZ_INS_CLGITNE, "clgitne" }, { SYSZ_INS_CLGITNH, "clgitnh" }, { SYSZ_INS_CLGITNHE, "clgitnhe" }, { SYSZ_INS_CLGITNL, "clgitnl" }, { SYSZ_INS_CLGITNLE, "clgitnle" }, { SYSZ_INS_CLGITNLH, "clgitnlh" }, { SYSZ_INS_CLGRB, "clgrb" }, { SYSZ_INS_CLGRBE, "clgrbe" }, { SYSZ_INS_CLGRBH, "clgrbh" }, { SYSZ_INS_CLGRBHE, "clgrbhe" }, { SYSZ_INS_CLGRBL, "clgrbl" }, { SYSZ_INS_CLGRBLE, "clgrble" }, { SYSZ_INS_CLGRBLH, "clgrblh" }, { SYSZ_INS_CLGRBNE, "clgrbne" }, { SYSZ_INS_CLGRBNH, "clgrbnh" }, { SYSZ_INS_CLGRBNHE, "clgrbnhe" }, { SYSZ_INS_CLGRBNL, "clgrbnl" }, { SYSZ_INS_CLGRBNLE, "clgrbnle" }, { SYSZ_INS_CLGRBNLH, "clgrbnlh" }, { SYSZ_INS_CLGRT, "clgrt" }, { SYSZ_INS_CLGRTE, "clgrte" }, { SYSZ_INS_CLGRTH, "clgrth" }, { SYSZ_INS_CLGRTHE, "clgrthe" }, { SYSZ_INS_CLGRTL, "clgrtl" }, { SYSZ_INS_CLGRTLE, "clgrtle" }, { SYSZ_INS_CLGRTLH, "clgrtlh" }, { SYSZ_INS_CLGRTNE, "clgrtne" }, { SYSZ_INS_CLGRTNH, "clgrtnh" }, { SYSZ_INS_CLGRTNHE, "clgrtnhe" }, { SYSZ_INS_CLGRTNL, "clgrtnl" }, { SYSZ_INS_CLGRTNLE, "clgrtnle" }, { SYSZ_INS_CLGRTNLH, "clgrtnlh" }, { SYSZ_INS_CLGT, "clgt" }, { SYSZ_INS_CLGTE, "clgte" }, { SYSZ_INS_CLGTH, "clgth" }, { SYSZ_INS_CLGTHE, "clgthe" }, { SYSZ_INS_CLGTL, "clgtl" }, { SYSZ_INS_CLGTLE, "clgtle" }, { SYSZ_INS_CLGTLH, "clgtlh" }, { SYSZ_INS_CLGTNE, "clgtne" }, { SYSZ_INS_CLGTNH, "clgtnh" }, { SYSZ_INS_CLGTNHE, "clgtnhe" }, { SYSZ_INS_CLGTNL, "clgtnl" }, { SYSZ_INS_CLGTNLE, "clgtnle" }, { SYSZ_INS_CLGTNLH, "clgtnlh" }, { SYSZ_INS_CLGXTR, "clgxtr" }, { SYSZ_INS_CLHHR, "clhhr" }, { SYSZ_INS_CLHLR, "clhlr" }, { SYSZ_INS_CLIB, "clib" }, { SYSZ_INS_CLIBE, "clibe" }, { SYSZ_INS_CLIBH, "clibh" }, { SYSZ_INS_CLIBHE, "clibhe" }, { SYSZ_INS_CLIBL, "clibl" }, { SYSZ_INS_CLIBLE, "clible" }, { SYSZ_INS_CLIBLH, "cliblh" }, { SYSZ_INS_CLIBNE, "clibne" }, { SYSZ_INS_CLIBNH, "clibnh" }, { SYSZ_INS_CLIBNHE, "clibnhe" }, { SYSZ_INS_CLIBNL, "clibnl" }, { SYSZ_INS_CLIBNLE, "clibnle" }, { SYSZ_INS_CLIBNLH, "clibnlh" }, { SYSZ_INS_CLM, "clm" }, { SYSZ_INS_CLMH, "clmh" }, { SYSZ_INS_CLMY, "clmy" }, { SYSZ_INS_CLRB, "clrb" }, { SYSZ_INS_CLRBE, "clrbe" }, { SYSZ_INS_CLRBH, "clrbh" }, { SYSZ_INS_CLRBHE, "clrbhe" }, { SYSZ_INS_CLRBL, "clrbl" }, { SYSZ_INS_CLRBLE, "clrble" }, { SYSZ_INS_CLRBLH, "clrblh" }, { SYSZ_INS_CLRBNE, "clrbne" }, { SYSZ_INS_CLRBNH, "clrbnh" }, { SYSZ_INS_CLRBNHE, "clrbnhe" }, { SYSZ_INS_CLRBNL, "clrbnl" }, { SYSZ_INS_CLRBNLE, "clrbnle" }, { SYSZ_INS_CLRBNLH, "clrbnlh" }, { SYSZ_INS_CLRT, "clrt" }, { SYSZ_INS_CLRTE, "clrte" }, { SYSZ_INS_CLRTH, "clrth" }, { SYSZ_INS_CLRTHE, "clrthe" }, { SYSZ_INS_CLRTL, "clrtl" }, { SYSZ_INS_CLRTLE, "clrtle" }, { SYSZ_INS_CLRTLH, "clrtlh" }, { SYSZ_INS_CLRTNE, "clrtne" }, { SYSZ_INS_CLRTNH, "clrtnh" }, { SYSZ_INS_CLRTNHE, "clrtnhe" }, { SYSZ_INS_CLRTNL, "clrtnl" }, { SYSZ_INS_CLRTNLE, "clrtnle" }, { SYSZ_INS_CLRTNLH, "clrtnlh" }, { SYSZ_INS_CLT, "clt" }, { SYSZ_INS_CLTE, "clte" }, { SYSZ_INS_CLTH, "clth" }, { SYSZ_INS_CLTHE, "clthe" }, { SYSZ_INS_CLTL, "cltl" }, { SYSZ_INS_CLTLE, "cltle" }, { SYSZ_INS_CLTLH, "cltlh" }, { SYSZ_INS_CLTNE, "cltne" }, { SYSZ_INS_CLTNH, "cltnh" }, { SYSZ_INS_CLTNHE, "cltnhe" }, { SYSZ_INS_CLTNL, "cltnl" }, { SYSZ_INS_CLTNLE, "cltnle" }, { SYSZ_INS_CLTNLH, "cltnlh" }, { SYSZ_INS_CMPSC, "cmpsc" }, { SYSZ_INS_CP, "cp" }, { SYSZ_INS_CPDT, "cpdt" }, { SYSZ_INS_CPXT, "cpxt" }, { SYSZ_INS_CPYA, "cpya" }, { SYSZ_INS_CRB, "crb" }, { SYSZ_INS_CRBE, "crbe" }, { SYSZ_INS_CRBH, "crbh" }, { SYSZ_INS_CRBHE, "crbhe" }, { SYSZ_INS_CRBL, "crbl" }, { SYSZ_INS_CRBLE, "crble" }, { SYSZ_INS_CRBLH, "crblh" }, { SYSZ_INS_CRBNE, "crbne" }, { SYSZ_INS_CRBNH, "crbnh" }, { SYSZ_INS_CRBNHE, "crbnhe" }, { SYSZ_INS_CRBNL, "crbnl" }, { SYSZ_INS_CRBNLE, "crbnle" }, { SYSZ_INS_CRBNLH, "crbnlh" }, { SYSZ_INS_CRDTE, "crdte" }, { SYSZ_INS_CRT, "crt" }, { SYSZ_INS_CRTE, "crte" }, { SYSZ_INS_CRTH, "crth" }, { SYSZ_INS_CRTHE, "crthe" }, { SYSZ_INS_CRTL, "crtl" }, { SYSZ_INS_CRTLE, "crtle" }, { SYSZ_INS_CRTLH, "crtlh" }, { SYSZ_INS_CRTNE, "crtne" }, { SYSZ_INS_CRTNH, "crtnh" }, { SYSZ_INS_CRTNHE, "crtnhe" }, { SYSZ_INS_CRTNL, "crtnl" }, { SYSZ_INS_CRTNLE, "crtnle" }, { SYSZ_INS_CRTNLH, "crtnlh" }, { SYSZ_INS_CSCH, "csch" }, { SYSZ_INS_CSDTR, "csdtr" }, { SYSZ_INS_CSP, "csp" }, { SYSZ_INS_CSPG, "cspg" }, { SYSZ_INS_CSST, "csst" }, { SYSZ_INS_CSXTR, "csxtr" }, { SYSZ_INS_CU12, "cu12" }, { SYSZ_INS_CU14, "cu14" }, { SYSZ_INS_CU21, "cu21" }, { SYSZ_INS_CU24, "cu24" }, { SYSZ_INS_CU41, "cu41" }, { SYSZ_INS_CU42, "cu42" }, { SYSZ_INS_CUDTR, "cudtr" }, { SYSZ_INS_CUSE, "cuse" }, { SYSZ_INS_CUTFU, "cutfu" }, { SYSZ_INS_CUUTF, "cuutf" }, { SYSZ_INS_CUXTR, "cuxtr" }, { SYSZ_INS_CVB, "cvb" }, { SYSZ_INS_CVBG, "cvbg" }, { SYSZ_INS_CVBY, "cvby" }, { SYSZ_INS_CVD, "cvd" }, { SYSZ_INS_CVDG, "cvdg" }, { SYSZ_INS_CVDY, "cvdy" }, { SYSZ_INS_CXFBRA, "cxfbra" }, { SYSZ_INS_CXFR, "cxfr" }, { SYSZ_INS_CXFTR, "cxftr" }, { SYSZ_INS_CXGBRA, "cxgbra" }, { SYSZ_INS_CXGR, "cxgr" }, { SYSZ_INS_CXGTR, "cxgtr" }, { SYSZ_INS_CXGTRA, "cxgtra" }, { SYSZ_INS_CXLFTR, "cxlftr" }, { SYSZ_INS_CXLGTR, "cxlgtr" }, { SYSZ_INS_CXPT, "cxpt" }, { SYSZ_INS_CXR, "cxr" }, { SYSZ_INS_CXSTR, "cxstr" }, { SYSZ_INS_CXTR, "cxtr" }, { SYSZ_INS_CXUTR, "cxutr" }, { SYSZ_INS_CXZT, "cxzt" }, { SYSZ_INS_CZDT, "czdt" }, { SYSZ_INS_CZXT, "czxt" }, { SYSZ_INS_D, "d" }, { SYSZ_INS_DD, "dd" }, { SYSZ_INS_DDR, "ddr" }, { SYSZ_INS_DDTR, "ddtr" }, { SYSZ_INS_DDTRA, "ddtra" }, { SYSZ_INS_DE, "de" }, { SYSZ_INS_DER, "der" }, { SYSZ_INS_DIAG, "diag" }, { SYSZ_INS_DIDBR, "didbr" }, { SYSZ_INS_DIEBR, "diebr" }, { SYSZ_INS_DP, "dp" }, { SYSZ_INS_DR, "dr" }, { SYSZ_INS_DXR, "dxr" }, { SYSZ_INS_DXTR, "dxtr" }, { SYSZ_INS_DXTRA, "dxtra" }, { SYSZ_INS_ECAG, "ecag" }, { SYSZ_INS_ECCTR, "ecctr" }, { SYSZ_INS_ECPGA, "ecpga" }, { SYSZ_INS_ECTG, "ectg" }, { SYSZ_INS_ED, "ed" }, { SYSZ_INS_EDMK, "edmk" }, { SYSZ_INS_EEDTR, "eedtr" }, { SYSZ_INS_EEXTR, "eextr" }, { SYSZ_INS_EFPC, "efpc" }, { SYSZ_INS_EPAIR, "epair" }, { SYSZ_INS_EPAR, "epar" }, { SYSZ_INS_EPCTR, "epctr" }, { SYSZ_INS_EPSW, "epsw" }, { SYSZ_INS_EREG, "ereg" }, { SYSZ_INS_EREGG, "eregg" }, { SYSZ_INS_ESAIR, "esair" }, { SYSZ_INS_ESAR, "esar" }, { SYSZ_INS_ESDTR, "esdtr" }, { SYSZ_INS_ESEA, "esea" }, { SYSZ_INS_ESTA, "esta" }, { SYSZ_INS_ESXTR, "esxtr" }, { SYSZ_INS_ETND, "etnd" }, { SYSZ_INS_EX, "ex" }, { SYSZ_INS_EXRL, "exrl" }, { SYSZ_INS_FIDR, "fidr" }, { SYSZ_INS_FIDTR, "fidtr" }, { SYSZ_INS_FIER, "fier" }, { SYSZ_INS_FIXR, "fixr" }, { SYSZ_INS_FIXTR, "fixtr" }, { SYSZ_INS_HDR, "hdr" }, { SYSZ_INS_HER, "her" }, { SYSZ_INS_HSCH, "hsch" }, { SYSZ_INS_IAC, "iac" }, { SYSZ_INS_ICM, "icm" }, { SYSZ_INS_ICMH, "icmh" }, { SYSZ_INS_ICMY, "icmy" }, { SYSZ_INS_IDTE, "idte" }, { SYSZ_INS_IEDTR, "iedtr" }, { SYSZ_INS_IEXTR, "iextr" }, { SYSZ_INS_IPK, "ipk" }, { SYSZ_INS_IPTE, "ipte" }, { SYSZ_INS_IRBM, "irbm" }, { SYSZ_INS_ISKE, "iske" }, { SYSZ_INS_IVSK, "ivsk" }, { SYSZ_INS_JGM, "jgm" }, { SYSZ_INS_JGNM, "jgnm" }, { SYSZ_INS_JGNP, "jgnp" }, { SYSZ_INS_JGNZ, "jgnz" }, { SYSZ_INS_JGP, "jgp" }, { SYSZ_INS_JGZ, "jgz" }, { SYSZ_INS_JM, "jm" }, { SYSZ_INS_JNM, "jnm" }, { SYSZ_INS_JNP, "jnp" }, { SYSZ_INS_JNZ, "jnz" }, { SYSZ_INS_JP, "jp" }, { SYSZ_INS_JZ, "jz" }, { SYSZ_INS_KDB, "kdb" }, { SYSZ_INS_KDBR, "kdbr" }, { SYSZ_INS_KDTR, "kdtr" }, { SYSZ_INS_KEB, "keb" }, { SYSZ_INS_KEBR, "kebr" }, { SYSZ_INS_KIMD, "kimd" }, { SYSZ_INS_KLMD, "klmd" }, { SYSZ_INS_KM, "km" }, { SYSZ_INS_KMA, "kma" }, { SYSZ_INS_KMAC, "kmac" }, { SYSZ_INS_KMC, "kmc" }, { SYSZ_INS_KMCTR, "kmctr" }, { SYSZ_INS_KMF, "kmf" }, { SYSZ_INS_KMO, "kmo" }, { SYSZ_INS_KXBR, "kxbr" }, { SYSZ_INS_KXTR, "kxtr" }, { SYSZ_INS_LAE, "lae" }, { SYSZ_INS_LAEY, "laey" }, { SYSZ_INS_LAM, "lam" }, { SYSZ_INS_LAMY, "lamy" }, { SYSZ_INS_LASP, "lasp" }, { SYSZ_INS_LAT, "lat" }, { SYSZ_INS_LCBB, "lcbb" }, { SYSZ_INS_LCCTL, "lcctl" }, { SYSZ_INS_LCDFR, "lcdfr" }, { SYSZ_INS_LCDR, "lcdr" }, { SYSZ_INS_LCER, "lcer" }, { SYSZ_INS_LCTL, "lctl" }, { SYSZ_INS_LCTLG, "lctlg" }, { SYSZ_INS_LCXR, "lcxr" }, { SYSZ_INS_LDE, "lde" }, { SYSZ_INS_LDER, "lder" }, { SYSZ_INS_LDETR, "ldetr" }, { SYSZ_INS_LDXR, "ldxr" }, { SYSZ_INS_LDXTR, "ldxtr" }, { SYSZ_INS_LEDR, "ledr" }, { SYSZ_INS_LEDTR, "ledtr" }, { SYSZ_INS_LEXR, "lexr" }, { SYSZ_INS_LFAS, "lfas" }, { SYSZ_INS_LFHAT, "lfhat" }, { SYSZ_INS_LFPC, "lfpc" }, { SYSZ_INS_LGAT, "lgat" }, { SYSZ_INS_LGG, "lgg" }, { SYSZ_INS_LGSC, "lgsc" }, { SYSZ_INS_LLGFAT, "llgfat" }, { SYSZ_INS_LLGFSG, "llgfsg" }, { SYSZ_INS_LLGT, "llgt" }, { SYSZ_INS_LLGTAT, "llgtat" }, { SYSZ_INS_LLGTR, "llgtr" }, { SYSZ_INS_LLZRGF, "llzrgf" }, { SYSZ_INS_LM, "lm" }, { SYSZ_INS_LMD, "lmd" }, { SYSZ_INS_LMH, "lmh" }, { SYSZ_INS_LMY, "lmy" }, { SYSZ_INS_LNDFR, "lndfr" }, { SYSZ_INS_LNDR, "lndr" }, { SYSZ_INS_LNER, "lner" }, { SYSZ_INS_LNXR, "lnxr" }, { SYSZ_INS_LOCFH, "locfh" }, { SYSZ_INS_LOCFHE, "locfhe" }, { SYSZ_INS_LOCFHH, "locfhh" }, { SYSZ_INS_LOCFHHE, "locfhhe" }, { SYSZ_INS_LOCFHL, "locfhl" }, { SYSZ_INS_LOCFHLE, "locfhle" }, { SYSZ_INS_LOCFHLH, "locfhlh" }, { SYSZ_INS_LOCFHM, "locfhm" }, { SYSZ_INS_LOCFHNE, "locfhne" }, { SYSZ_INS_LOCFHNH, "locfhnh" }, { SYSZ_INS_LOCFHNHE, "locfhnhe" }, { SYSZ_INS_LOCFHNL, "locfhnl" }, { SYSZ_INS_LOCFHNLE, "locfhnle" }, { SYSZ_INS_LOCFHNLH, "locfhnlh" }, { SYSZ_INS_LOCFHNM, "locfhnm" }, { SYSZ_INS_LOCFHNO, "locfhno" }, { SYSZ_INS_LOCFHNP, "locfhnp" }, { SYSZ_INS_LOCFHNZ, "locfhnz" }, { SYSZ_INS_LOCFHO, "locfho" }, { SYSZ_INS_LOCFHP, "locfhp" }, { SYSZ_INS_LOCFHR, "locfhr" }, { SYSZ_INS_LOCFHRE, "locfhre" }, { SYSZ_INS_LOCFHRH, "locfhrh" }, { SYSZ_INS_LOCFHRHE, "locfhrhe" }, { SYSZ_INS_LOCFHRL, "locfhrl" }, { SYSZ_INS_LOCFHRLE, "locfhrle" }, { SYSZ_INS_LOCFHRLH, "locfhrlh" }, { SYSZ_INS_LOCFHRM, "locfhrm" }, { SYSZ_INS_LOCFHRNE, "locfhrne" }, { SYSZ_INS_LOCFHRNH, "locfhrnh" }, { SYSZ_INS_LOCFHRNHE, "locfhrnhe" }, { SYSZ_INS_LOCFHRNL, "locfhrnl" }, { SYSZ_INS_LOCFHRNLE, "locfhrnle" }, { SYSZ_INS_LOCFHRNLH, "locfhrnlh" }, { SYSZ_INS_LOCFHRNM, "locfhrnm" }, { SYSZ_INS_LOCFHRNO, "locfhrno" }, { SYSZ_INS_LOCFHRNP, "locfhrnp" }, { SYSZ_INS_LOCFHRNZ, "locfhrnz" }, { SYSZ_INS_LOCFHRO, "locfhro" }, { SYSZ_INS_LOCFHRP, "locfhrp" }, { SYSZ_INS_LOCFHRZ, "locfhrz" }, { SYSZ_INS_LOCFHZ, "locfhz" }, { SYSZ_INS_LOCGHI, "locghi" }, { SYSZ_INS_LOCGHIE, "locghie" }, { SYSZ_INS_LOCGHIH, "locghih" }, { SYSZ_INS_LOCGHIHE, "locghihe" }, { SYSZ_INS_LOCGHIL, "locghil" }, { SYSZ_INS_LOCGHILE, "locghile" }, { SYSZ_INS_LOCGHILH, "locghilh" }, { SYSZ_INS_LOCGHIM, "locghim" }, { SYSZ_INS_LOCGHINE, "locghine" }, { SYSZ_INS_LOCGHINH, "locghinh" }, { SYSZ_INS_LOCGHINHE, "locghinhe" }, { SYSZ_INS_LOCGHINL, "locghinl" }, { SYSZ_INS_LOCGHINLE, "locghinle" }, { SYSZ_INS_LOCGHINLH, "locghinlh" }, { SYSZ_INS_LOCGHINM, "locghinm" }, { SYSZ_INS_LOCGHINO, "locghino" }, { SYSZ_INS_LOCGHINP, "locghinp" }, { SYSZ_INS_LOCGHINZ, "locghinz" }, { SYSZ_INS_LOCGHIO, "locghio" }, { SYSZ_INS_LOCGHIP, "locghip" }, { SYSZ_INS_LOCGHIZ, "locghiz" }, { SYSZ_INS_LOCGM, "locgm" }, { SYSZ_INS_LOCGNM, "locgnm" }, { SYSZ_INS_LOCGNP, "locgnp" }, { SYSZ_INS_LOCGNZ, "locgnz" }, { SYSZ_INS_LOCGP, "locgp" }, { SYSZ_INS_LOCGRM, "locgrm" }, { SYSZ_INS_LOCGRNM, "locgrnm" }, { SYSZ_INS_LOCGRNP, "locgrnp" }, { SYSZ_INS_LOCGRNZ, "locgrnz" }, { SYSZ_INS_LOCGRP, "locgrp" }, { SYSZ_INS_LOCGRZ, "locgrz" }, { SYSZ_INS_LOCGZ, "locgz" }, { SYSZ_INS_LOCHHI, "lochhi" }, { SYSZ_INS_LOCHHIE, "lochhie" }, { SYSZ_INS_LOCHHIH, "lochhih" }, { SYSZ_INS_LOCHHIHE, "lochhihe" }, { SYSZ_INS_LOCHHIL, "lochhil" }, { SYSZ_INS_LOCHHILE, "lochhile" }, { SYSZ_INS_LOCHHILH, "lochhilh" }, { SYSZ_INS_LOCHHIM, "lochhim" }, { SYSZ_INS_LOCHHINE, "lochhine" }, { SYSZ_INS_LOCHHINH, "lochhinh" }, { SYSZ_INS_LOCHHINHE, "lochhinhe" }, { SYSZ_INS_LOCHHINL, "lochhinl" }, { SYSZ_INS_LOCHHINLE, "lochhinle" }, { SYSZ_INS_LOCHHINLH, "lochhinlh" }, { SYSZ_INS_LOCHHINM, "lochhinm" }, { SYSZ_INS_LOCHHINO, "lochhino" }, { SYSZ_INS_LOCHHINP, "lochhinp" }, { SYSZ_INS_LOCHHINZ, "lochhinz" }, { SYSZ_INS_LOCHHIO, "lochhio" }, { SYSZ_INS_LOCHHIP, "lochhip" }, { SYSZ_INS_LOCHHIZ, "lochhiz" }, { SYSZ_INS_LOCHI, "lochi" }, { SYSZ_INS_LOCHIE, "lochie" }, { SYSZ_INS_LOCHIH, "lochih" }, { SYSZ_INS_LOCHIHE, "lochihe" }, { SYSZ_INS_LOCHIL, "lochil" }, { SYSZ_INS_LOCHILE, "lochile" }, { SYSZ_INS_LOCHILH, "lochilh" }, { SYSZ_INS_LOCHIM, "lochim" }, { SYSZ_INS_LOCHINE, "lochine" }, { SYSZ_INS_LOCHINH, "lochinh" }, { SYSZ_INS_LOCHINHE, "lochinhe" }, { SYSZ_INS_LOCHINL, "lochinl" }, { SYSZ_INS_LOCHINLE, "lochinle" }, { SYSZ_INS_LOCHINLH, "lochinlh" }, { SYSZ_INS_LOCHINM, "lochinm" }, { SYSZ_INS_LOCHINO, "lochino" }, { SYSZ_INS_LOCHINP, "lochinp" }, { SYSZ_INS_LOCHINZ, "lochinz" }, { SYSZ_INS_LOCHIO, "lochio" }, { SYSZ_INS_LOCHIP, "lochip" }, { SYSZ_INS_LOCHIZ, "lochiz" }, { SYSZ_INS_LOCM, "locm" }, { SYSZ_INS_LOCNM, "locnm" }, { SYSZ_INS_LOCNP, "locnp" }, { SYSZ_INS_LOCNZ, "locnz" }, { SYSZ_INS_LOCP, "locp" }, { SYSZ_INS_LOCRM, "locrm" }, { SYSZ_INS_LOCRNM, "locrnm" }, { SYSZ_INS_LOCRNP, "locrnp" }, { SYSZ_INS_LOCRNZ, "locrnz" }, { SYSZ_INS_LOCRP, "locrp" }, { SYSZ_INS_LOCRZ, "locrz" }, { SYSZ_INS_LOCZ, "locz" }, { SYSZ_INS_LPCTL, "lpctl" }, { SYSZ_INS_LPD, "lpd" }, { SYSZ_INS_LPDFR, "lpdfr" }, { SYSZ_INS_LPDG, "lpdg" }, { SYSZ_INS_LPDR, "lpdr" }, { SYSZ_INS_LPER, "lper" }, { SYSZ_INS_LPP, "lpp" }, { SYSZ_INS_LPQ, "lpq" }, { SYSZ_INS_LPSW, "lpsw" }, { SYSZ_INS_LPSWE, "lpswe" }, { SYSZ_INS_LPTEA, "lptea" }, { SYSZ_INS_LPXR, "lpxr" }, { SYSZ_INS_LRA, "lra" }, { SYSZ_INS_LRAG, "lrag" }, { SYSZ_INS_LRAY, "lray" }, { SYSZ_INS_LRDR, "lrdr" }, { SYSZ_INS_LRER, "lrer" }, { SYSZ_INS_LRVH, "lrvh" }, { SYSZ_INS_LSCTL, "lsctl" }, { SYSZ_INS_LTDR, "ltdr" }, { SYSZ_INS_LTDTR, "ltdtr" }, { SYSZ_INS_LTER, "lter" }, { SYSZ_INS_LTXR, "ltxr" }, { SYSZ_INS_LTXTR, "ltxtr" }, { SYSZ_INS_LURA, "lura" }, { SYSZ_INS_LURAG, "lurag" }, { SYSZ_INS_LXD, "lxd" }, { SYSZ_INS_LXDR, "lxdr" }, { SYSZ_INS_LXDTR, "lxdtr" }, { SYSZ_INS_LXE, "lxe" }, { SYSZ_INS_LXER, "lxer" }, { SYSZ_INS_LZRF, "lzrf" }, { SYSZ_INS_LZRG, "lzrg" }, { SYSZ_INS_M, "m" }, { SYSZ_INS_MAD, "mad" }, { SYSZ_INS_MADR, "madr" }, { SYSZ_INS_MAE, "mae" }, { SYSZ_INS_MAER, "maer" }, { SYSZ_INS_MAY, "may" }, { SYSZ_INS_MAYH, "mayh" }, { SYSZ_INS_MAYHR, "mayhr" }, { SYSZ_INS_MAYL, "mayl" }, { SYSZ_INS_MAYLR, "maylr" }, { SYSZ_INS_MAYR, "mayr" }, { SYSZ_INS_MC, "mc" }, { SYSZ_INS_MD, "md" }, { SYSZ_INS_MDE, "mde" }, { SYSZ_INS_MDER, "mder" }, { SYSZ_INS_MDR, "mdr" }, { SYSZ_INS_MDTR, "mdtr" }, { SYSZ_INS_MDTRA, "mdtra" }, { SYSZ_INS_ME, "me" }, { SYSZ_INS_MEE, "mee" }, { SYSZ_INS_MEER, "meer" }, { SYSZ_INS_MER, "mer" }, { SYSZ_INS_MFY, "mfy" }, { SYSZ_INS_MG, "mg" }, { SYSZ_INS_MGH, "mgh" }, { SYSZ_INS_MGRK, "mgrk" }, { SYSZ_INS_ML, "ml" }, { SYSZ_INS_MLR, "mlr" }, { SYSZ_INS_MP, "mp" }, { SYSZ_INS_MR, "mr" }, { SYSZ_INS_MSC, "msc" }, { SYSZ_INS_MSCH, "msch" }, { SYSZ_INS_MSD, "msd" }, { SYSZ_INS_MSDR, "msdr" }, { SYSZ_INS_MSE, "mse" }, { SYSZ_INS_MSER, "mser" }, { SYSZ_INS_MSGC, "msgc" }, { SYSZ_INS_MSGRKC, "msgrkc" }, { SYSZ_INS_MSRKC, "msrkc" }, { SYSZ_INS_MSTA, "msta" }, { SYSZ_INS_MVCDK, "mvcdk" }, { SYSZ_INS_MVCIN, "mvcin" }, { SYSZ_INS_MVCK, "mvck" }, { SYSZ_INS_MVCL, "mvcl" }, { SYSZ_INS_MVCLE, "mvcle" }, { SYSZ_INS_MVCLU, "mvclu" }, { SYSZ_INS_MVCOS, "mvcos" }, { SYSZ_INS_MVCP, "mvcp" }, { SYSZ_INS_MVCS, "mvcs" }, { SYSZ_INS_MVCSK, "mvcsk" }, { SYSZ_INS_MVN, "mvn" }, { SYSZ_INS_MVO, "mvo" }, { SYSZ_INS_MVPG, "mvpg" }, { SYSZ_INS_MVZ, "mvz" }, { SYSZ_INS_MXD, "mxd" }, { SYSZ_INS_MXDR, "mxdr" }, { SYSZ_INS_MXR, "mxr" }, { SYSZ_INS_MXTR, "mxtr" }, { SYSZ_INS_MXTRA, "mxtra" }, { SYSZ_INS_MY, "my" }, { SYSZ_INS_MYH, "myh" }, { SYSZ_INS_MYHR, "myhr" }, { SYSZ_INS_MYL, "myl" }, { SYSZ_INS_MYLR, "mylr" }, { SYSZ_INS_MYR, "myr" }, { SYSZ_INS_NIAI, "niai" }, { SYSZ_INS_NTSTG, "ntstg" }, { SYSZ_INS_PACK, "pack" }, { SYSZ_INS_PALB, "palb" }, { SYSZ_INS_PC, "pc" }, { SYSZ_INS_PCC, "pcc" }, { SYSZ_INS_PCKMO, "pckmo" }, { SYSZ_INS_PFMF, "pfmf" }, { SYSZ_INS_PFPO, "pfpo" }, { SYSZ_INS_PGIN, "pgin" }, { SYSZ_INS_PGOUT, "pgout" }, { SYSZ_INS_PKA, "pka" }, { SYSZ_INS_PKU, "pku" }, { SYSZ_INS_PLO, "plo" }, { SYSZ_INS_POPCNT, "popcnt" }, { SYSZ_INS_PPA, "ppa" }, { SYSZ_INS_PPNO, "ppno" }, { SYSZ_INS_PR, "pr" }, { SYSZ_INS_PRNO, "prno" }, { SYSZ_INS_PT, "pt" }, { SYSZ_INS_PTF, "ptf" }, { SYSZ_INS_PTFF, "ptff" }, { SYSZ_INS_PTI, "pti" }, { SYSZ_INS_PTLB, "ptlb" }, { SYSZ_INS_QADTR, "qadtr" }, { SYSZ_INS_QAXTR, "qaxtr" }, { SYSZ_INS_QCTRI, "qctri" }, { SYSZ_INS_QSI, "qsi" }, { SYSZ_INS_RCHP, "rchp" }, { SYSZ_INS_RISBGN, "risbgn" }, { SYSZ_INS_RP, "rp" }, { SYSZ_INS_RRBE, "rrbe" }, { SYSZ_INS_RRBM, "rrbm" }, { SYSZ_INS_RRDTR, "rrdtr" }, { SYSZ_INS_RRXTR, "rrxtr" }, { SYSZ_INS_RSCH, "rsch" }, { SYSZ_INS_SAC, "sac" }, { SYSZ_INS_SACF, "sacf" }, { SYSZ_INS_SAL, "sal" }, { SYSZ_INS_SAM24, "sam24" }, { SYSZ_INS_SAM31, "sam31" }, { SYSZ_INS_SAM64, "sam64" }, { SYSZ_INS_SAR, "sar" }, { SYSZ_INS_SCCTR, "scctr" }, { SYSZ_INS_SCHM, "schm" }, { SYSZ_INS_SCK, "sck" }, { SYSZ_INS_SCKC, "sckc" }, { SYSZ_INS_SCKPF, "sckpf" }, { SYSZ_INS_SD, "sd" }, { SYSZ_INS_SDR, "sdr" }, { SYSZ_INS_SDTR, "sdtr" }, { SYSZ_INS_SDTRA, "sdtra" }, { SYSZ_INS_SE, "se" }, { SYSZ_INS_SER, "ser" }, { SYSZ_INS_SFASR, "sfasr" }, { SYSZ_INS_SFPC, "sfpc" }, { SYSZ_INS_SGH, "sgh" }, { SYSZ_INS_SHHHR, "shhhr" }, { SYSZ_INS_SHHLR, "shhlr" }, { SYSZ_INS_SIE, "sie" }, { SYSZ_INS_SIGA, "siga" }, { SYSZ_INS_SIGP, "sigp" }, { SYSZ_INS_SLA, "sla" }, { SYSZ_INS_SLAG, "slag" }, { SYSZ_INS_SLAK, "slak" }, { SYSZ_INS_SLDA, "slda" }, { SYSZ_INS_SLDL, "sldl" }, { SYSZ_INS_SLDT, "sldt" }, { SYSZ_INS_SLHHHR, "slhhhr" }, { SYSZ_INS_SLHHLR, "slhhlr" }, { SYSZ_INS_SLXT, "slxt" }, { SYSZ_INS_SP, "sp" }, { SYSZ_INS_SPCTR, "spctr" }, { SYSZ_INS_SPKA, "spka" }, { SYSZ_INS_SPM, "spm" }, { SYSZ_INS_SPT, "spt" }, { SYSZ_INS_SPX, "spx" }, { SYSZ_INS_SQD, "sqd" }, { SYSZ_INS_SQDR, "sqdr" }, { SYSZ_INS_SQE, "sqe" }, { SYSZ_INS_SQER, "sqer" }, { SYSZ_INS_SQXR, "sqxr" }, { SYSZ_INS_SRDA, "srda" }, { SYSZ_INS_SRDL, "srdl" }, { SYSZ_INS_SRDT, "srdt" }, { SYSZ_INS_SRNM, "srnm" }, { SYSZ_INS_SRNMB, "srnmb" }, { SYSZ_INS_SRNMT, "srnmt" }, { SYSZ_INS_SRP, "srp" }, { SYSZ_INS_SRSTU, "srstu" }, { SYSZ_INS_SRXT, "srxt" }, { SYSZ_INS_SSAIR, "ssair" }, { SYSZ_INS_SSAR, "ssar" }, { SYSZ_INS_SSCH, "ssch" }, { SYSZ_INS_SSKE, "sske" }, { SYSZ_INS_SSM, "ssm" }, { SYSZ_INS_STAM, "stam" }, { SYSZ_INS_STAMY, "stamy" }, { SYSZ_INS_STAP, "stap" }, { SYSZ_INS_STCK, "stck" }, { SYSZ_INS_STCKC, "stckc" }, { SYSZ_INS_STCKE, "stcke" }, { SYSZ_INS_STCKF, "stckf" }, { SYSZ_INS_STCM, "stcm" }, { SYSZ_INS_STCMH, "stcmh" }, { SYSZ_INS_STCMY, "stcmy" }, { SYSZ_INS_STCPS, "stcps" }, { SYSZ_INS_STCRW, "stcrw" }, { SYSZ_INS_STCTG, "stctg" }, { SYSZ_INS_STCTL, "stctl" }, { SYSZ_INS_STFL, "stfl" }, { SYSZ_INS_STFLE, "stfle" }, { SYSZ_INS_STFPC, "stfpc" }, { SYSZ_INS_STGSC, "stgsc" }, { SYSZ_INS_STIDP, "stidp" }, { SYSZ_INS_STM, "stm" }, { SYSZ_INS_STMH, "stmh" }, { SYSZ_INS_STMY, "stmy" }, { SYSZ_INS_STNSM, "stnsm" }, { SYSZ_INS_STOCFH, "stocfh" }, { SYSZ_INS_STOCFHE, "stocfhe" }, { SYSZ_INS_STOCFHH, "stocfhh" }, { SYSZ_INS_STOCFHHE, "stocfhhe" }, { SYSZ_INS_STOCFHL, "stocfhl" }, { SYSZ_INS_STOCFHLE, "stocfhle" }, { SYSZ_INS_STOCFHLH, "stocfhlh" }, { SYSZ_INS_STOCFHM, "stocfhm" }, { SYSZ_INS_STOCFHNE, "stocfhne" }, { SYSZ_INS_STOCFHNH, "stocfhnh" }, { SYSZ_INS_STOCFHNHE, "stocfhnhe" }, { SYSZ_INS_STOCFHNL, "stocfhnl" }, { SYSZ_INS_STOCFHNLE, "stocfhnle" }, { SYSZ_INS_STOCFHNLH, "stocfhnlh" }, { SYSZ_INS_STOCFHNM, "stocfhnm" }, { SYSZ_INS_STOCFHNO, "stocfhno" }, { SYSZ_INS_STOCFHNP, "stocfhnp" }, { SYSZ_INS_STOCFHNZ, "stocfhnz" }, { SYSZ_INS_STOCFHO, "stocfho" }, { SYSZ_INS_STOCFHP, "stocfhp" }, { SYSZ_INS_STOCFHZ, "stocfhz" }, { SYSZ_INS_STOCGM, "stocgm" }, { SYSZ_INS_STOCGNM, "stocgnm" }, { SYSZ_INS_STOCGNP, "stocgnp" }, { SYSZ_INS_STOCGNZ, "stocgnz" }, { SYSZ_INS_STOCGP, "stocgp" }, { SYSZ_INS_STOCGZ, "stocgz" }, { SYSZ_INS_STOCM, "stocm" }, { SYSZ_INS_STOCNM, "stocnm" }, { SYSZ_INS_STOCNP, "stocnp" }, { SYSZ_INS_STOCNZ, "stocnz" }, { SYSZ_INS_STOCP, "stocp" }, { SYSZ_INS_STOCZ, "stocz" }, { SYSZ_INS_STOSM, "stosm" }, { SYSZ_INS_STPQ, "stpq" }, { SYSZ_INS_STPT, "stpt" }, { SYSZ_INS_STPX, "stpx" }, { SYSZ_INS_STRAG, "strag" }, { SYSZ_INS_STRVH, "strvh" }, { SYSZ_INS_STSCH, "stsch" }, { SYSZ_INS_STSI, "stsi" }, { SYSZ_INS_STURA, "stura" }, { SYSZ_INS_STURG, "sturg" }, { SYSZ_INS_SU, "su" }, { SYSZ_INS_SUR, "sur" }, { SYSZ_INS_SVC, "svc" }, { SYSZ_INS_SW, "sw" }, { SYSZ_INS_SWR, "swr" }, { SYSZ_INS_SXR, "sxr" }, { SYSZ_INS_SXTR, "sxtr" }, { SYSZ_INS_SXTRA, "sxtra" }, { SYSZ_INS_TABORT, "tabort" }, { SYSZ_INS_TAM, "tam" }, { SYSZ_INS_TAR, "tar" }, { SYSZ_INS_TB, "tb" }, { SYSZ_INS_TBDR, "tbdr" }, { SYSZ_INS_TBEDR, "tbedr" }, { SYSZ_INS_TBEGIN, "tbegin" }, { SYSZ_INS_TBEGINC, "tbeginc" }, { SYSZ_INS_TCDB, "tcdb" }, { SYSZ_INS_TCEB, "tceb" }, { SYSZ_INS_TCXB, "tcxb" }, { SYSZ_INS_TDCDT, "tdcdt" }, { SYSZ_INS_TDCET, "tdcet" }, { SYSZ_INS_TDCXT, "tdcxt" }, { SYSZ_INS_TDGDT, "tdgdt" }, { SYSZ_INS_TDGET, "tdget" }, { SYSZ_INS_TDGXT, "tdgxt" }, { SYSZ_INS_TEND, "tend" }, { SYSZ_INS_THDER, "thder" }, { SYSZ_INS_THDR, "thdr" }, { SYSZ_INS_TP, "tp" }, { SYSZ_INS_TPI, "tpi" }, { SYSZ_INS_TPROT, "tprot" }, { SYSZ_INS_TR, "tr" }, { SYSZ_INS_TRACE, "trace" }, { SYSZ_INS_TRACG, "tracg" }, { SYSZ_INS_TRAP2, "trap2" }, { SYSZ_INS_TRAP4, "trap4" }, { SYSZ_INS_TRE, "tre" }, { SYSZ_INS_TROO, "troo" }, { SYSZ_INS_TROT, "trot" }, { SYSZ_INS_TRT, "trt" }, { SYSZ_INS_TRTE, "trte" }, { SYSZ_INS_TRTO, "trto" }, { SYSZ_INS_TRTR, "trtr" }, { SYSZ_INS_TRTRE, "trtre" }, { SYSZ_INS_TRTT, "trtt" }, { SYSZ_INS_TS, "ts" }, { SYSZ_INS_TSCH, "tsch" }, { SYSZ_INS_UNPK, "unpk" }, { SYSZ_INS_UNPKA, "unpka" }, { SYSZ_INS_UNPKU, "unpku" }, { SYSZ_INS_UPT, "upt" }, { SYSZ_INS_VA, "va" }, { SYSZ_INS_VAB, "vab" }, { SYSZ_INS_VAC, "vac" }, { SYSZ_INS_VACC, "vacc" }, { SYSZ_INS_VACCB, "vaccb" }, { SYSZ_INS_VACCC, "vaccc" }, { SYSZ_INS_VACCCQ, "vacccq" }, { SYSZ_INS_VACCF, "vaccf" }, { SYSZ_INS_VACCG, "vaccg" }, { SYSZ_INS_VACCH, "vacch" }, { SYSZ_INS_VACCQ, "vaccq" }, { SYSZ_INS_VACQ, "vacq" }, { SYSZ_INS_VAF, "vaf" }, { SYSZ_INS_VAG, "vag" }, { SYSZ_INS_VAH, "vah" }, { SYSZ_INS_VAP, "vap" }, { SYSZ_INS_VAQ, "vaq" }, { SYSZ_INS_VAVG, "vavg" }, { SYSZ_INS_VAVGB, "vavgb" }, { SYSZ_INS_VAVGF, "vavgf" }, { SYSZ_INS_VAVGG, "vavgg" }, { SYSZ_INS_VAVGH, "vavgh" }, { SYSZ_INS_VAVGL, "vavgl" }, { SYSZ_INS_VAVGLB, "vavglb" }, { SYSZ_INS_VAVGLF, "vavglf" }, { SYSZ_INS_VAVGLG, "vavglg" }, { SYSZ_INS_VAVGLH, "vavglh" }, { SYSZ_INS_VBPERM, "vbperm" }, { SYSZ_INS_VCDG, "vcdg" }, { SYSZ_INS_VCDGB, "vcdgb" }, { SYSZ_INS_VCDLG, "vcdlg" }, { SYSZ_INS_VCDLGB, "vcdlgb" }, { SYSZ_INS_VCEQ, "vceq" }, { SYSZ_INS_VCEQB, "vceqb" }, { SYSZ_INS_VCEQBS, "vceqbs" }, { SYSZ_INS_VCEQF, "vceqf" }, { SYSZ_INS_VCEQFS, "vceqfs" }, { SYSZ_INS_VCEQG, "vceqg" }, { SYSZ_INS_VCEQGS, "vceqgs" }, { SYSZ_INS_VCEQH, "vceqh" }, { SYSZ_INS_VCEQHS, "vceqhs" }, { SYSZ_INS_VCGD, "vcgd" }, { SYSZ_INS_VCGDB, "vcgdb" }, { SYSZ_INS_VCH, "vch" }, { SYSZ_INS_VCHB, "vchb" }, { SYSZ_INS_VCHBS, "vchbs" }, { SYSZ_INS_VCHF, "vchf" }, { SYSZ_INS_VCHFS, "vchfs" }, { SYSZ_INS_VCHG, "vchg" }, { SYSZ_INS_VCHGS, "vchgs" }, { SYSZ_INS_VCHH, "vchh" }, { SYSZ_INS_VCHHS, "vchhs" }, { SYSZ_INS_VCHL, "vchl" }, { SYSZ_INS_VCHLB, "vchlb" }, { SYSZ_INS_VCHLBS, "vchlbs" }, { SYSZ_INS_VCHLF, "vchlf" }, { SYSZ_INS_VCHLFS, "vchlfs" }, { SYSZ_INS_VCHLG, "vchlg" }, { SYSZ_INS_VCHLGS, "vchlgs" }, { SYSZ_INS_VCHLH, "vchlh" }, { SYSZ_INS_VCHLHS, "vchlhs" }, { SYSZ_INS_VCKSM, "vcksm" }, { SYSZ_INS_VCLGD, "vclgd" }, { SYSZ_INS_VCLGDB, "vclgdb" }, { SYSZ_INS_VCLZ, "vclz" }, { SYSZ_INS_VCLZB, "vclzb" }, { SYSZ_INS_VCLZF, "vclzf" }, { SYSZ_INS_VCLZG, "vclzg" }, { SYSZ_INS_VCLZH, "vclzh" }, { SYSZ_INS_VCP, "vcp" }, { SYSZ_INS_VCTZ, "vctz" }, { SYSZ_INS_VCTZB, "vctzb" }, { SYSZ_INS_VCTZF, "vctzf" }, { SYSZ_INS_VCTZG, "vctzg" }, { SYSZ_INS_VCTZH, "vctzh" }, { SYSZ_INS_VCVB, "vcvb" }, { SYSZ_INS_VCVBG, "vcvbg" }, { SYSZ_INS_VCVD, "vcvd" }, { SYSZ_INS_VCVDG, "vcvdg" }, { SYSZ_INS_VDP, "vdp" }, { SYSZ_INS_VEC, "vec" }, { SYSZ_INS_VECB, "vecb" }, { SYSZ_INS_VECF, "vecf" }, { SYSZ_INS_VECG, "vecg" }, { SYSZ_INS_VECH, "vech" }, { SYSZ_INS_VECL, "vecl" }, { SYSZ_INS_VECLB, "veclb" }, { SYSZ_INS_VECLF, "veclf" }, { SYSZ_INS_VECLG, "veclg" }, { SYSZ_INS_VECLH, "veclh" }, { SYSZ_INS_VERIM, "verim" }, { SYSZ_INS_VERIMB, "verimb" }, { SYSZ_INS_VERIMF, "verimf" }, { SYSZ_INS_VERIMG, "verimg" }, { SYSZ_INS_VERIMH, "verimh" }, { SYSZ_INS_VERLL, "verll" }, { SYSZ_INS_VERLLB, "verllb" }, { SYSZ_INS_VERLLF, "verllf" }, { SYSZ_INS_VERLLG, "verllg" }, { SYSZ_INS_VERLLH, "verllh" }, { SYSZ_INS_VERLLV, "verllv" }, { SYSZ_INS_VERLLVB, "verllvb" }, { SYSZ_INS_VERLLVF, "verllvf" }, { SYSZ_INS_VERLLVG, "verllvg" }, { SYSZ_INS_VERLLVH, "verllvh" }, { SYSZ_INS_VESL, "vesl" }, { SYSZ_INS_VESLB, "veslb" }, { SYSZ_INS_VESLF, "veslf" }, { SYSZ_INS_VESLG, "veslg" }, { SYSZ_INS_VESLH, "veslh" }, { SYSZ_INS_VESLV, "veslv" }, { SYSZ_INS_VESLVB, "veslvb" }, { SYSZ_INS_VESLVF, "veslvf" }, { SYSZ_INS_VESLVG, "veslvg" }, { SYSZ_INS_VESLVH, "veslvh" }, { SYSZ_INS_VESRA, "vesra" }, { SYSZ_INS_VESRAB, "vesrab" }, { SYSZ_INS_VESRAF, "vesraf" }, { SYSZ_INS_VESRAG, "vesrag" }, { SYSZ_INS_VESRAH, "vesrah" }, { SYSZ_INS_VESRAV, "vesrav" }, { SYSZ_INS_VESRAVB, "vesravb" }, { SYSZ_INS_VESRAVF, "vesravf" }, { SYSZ_INS_VESRAVG, "vesravg" }, { SYSZ_INS_VESRAVH, "vesravh" }, { SYSZ_INS_VESRL, "vesrl" }, { SYSZ_INS_VESRLB, "vesrlb" }, { SYSZ_INS_VESRLF, "vesrlf" }, { SYSZ_INS_VESRLG, "vesrlg" }, { SYSZ_INS_VESRLH, "vesrlh" }, { SYSZ_INS_VESRLV, "vesrlv" }, { SYSZ_INS_VESRLVB, "vesrlvb" }, { SYSZ_INS_VESRLVF, "vesrlvf" }, { SYSZ_INS_VESRLVG, "vesrlvg" }, { SYSZ_INS_VESRLVH, "vesrlvh" }, { SYSZ_INS_VFA, "vfa" }, { SYSZ_INS_VFADB, "vfadb" }, { SYSZ_INS_VFAE, "vfae" }, { SYSZ_INS_VFAEB, "vfaeb" }, { SYSZ_INS_VFAEBS, "vfaebs" }, { SYSZ_INS_VFAEF, "vfaef" }, { SYSZ_INS_VFAEFS, "vfaefs" }, { SYSZ_INS_VFAEH, "vfaeh" }, { SYSZ_INS_VFAEHS, "vfaehs" }, { SYSZ_INS_VFAEZB, "vfaezb" }, { SYSZ_INS_VFAEZBS, "vfaezbs" }, { SYSZ_INS_VFAEZF, "vfaezf" }, { SYSZ_INS_VFAEZFS, "vfaezfs" }, { SYSZ_INS_VFAEZH, "vfaezh" }, { SYSZ_INS_VFAEZHS, "vfaezhs" }, { SYSZ_INS_VFASB, "vfasb" }, { SYSZ_INS_VFCE, "vfce" }, { SYSZ_INS_VFCEDB, "vfcedb" }, { SYSZ_INS_VFCEDBS, "vfcedbs" }, { SYSZ_INS_VFCESB, "vfcesb" }, { SYSZ_INS_VFCESBS, "vfcesbs" }, { SYSZ_INS_VFCH, "vfch" }, { SYSZ_INS_VFCHDB, "vfchdb" }, { SYSZ_INS_VFCHDBS, "vfchdbs" }, { SYSZ_INS_VFCHE, "vfche" }, { SYSZ_INS_VFCHEDB, "vfchedb" }, { SYSZ_INS_VFCHEDBS, "vfchedbs" }, { SYSZ_INS_VFCHESB, "vfchesb" }, { SYSZ_INS_VFCHESBS, "vfchesbs" }, { SYSZ_INS_VFCHSB, "vfchsb" }, { SYSZ_INS_VFCHSBS, "vfchsbs" }, { SYSZ_INS_VFD, "vfd" }, { SYSZ_INS_VFDDB, "vfddb" }, { SYSZ_INS_VFDSB, "vfdsb" }, { SYSZ_INS_VFEE, "vfee" }, { SYSZ_INS_VFEEB, "vfeeb" }, { SYSZ_INS_VFEEBS, "vfeebs" }, { SYSZ_INS_VFEEF, "vfeef" }, { SYSZ_INS_VFEEFS, "vfeefs" }, { SYSZ_INS_VFEEH, "vfeeh" }, { SYSZ_INS_VFEEHS, "vfeehs" }, { SYSZ_INS_VFEEZB, "vfeezb" }, { SYSZ_INS_VFEEZBS, "vfeezbs" }, { SYSZ_INS_VFEEZF, "vfeezf" }, { SYSZ_INS_VFEEZFS, "vfeezfs" }, { SYSZ_INS_VFEEZH, "vfeezh" }, { SYSZ_INS_VFEEZHS, "vfeezhs" }, { SYSZ_INS_VFENE, "vfene" }, { SYSZ_INS_VFENEB, "vfeneb" }, { SYSZ_INS_VFENEBS, "vfenebs" }, { SYSZ_INS_VFENEF, "vfenef" }, { SYSZ_INS_VFENEFS, "vfenefs" }, { SYSZ_INS_VFENEH, "vfeneh" }, { SYSZ_INS_VFENEHS, "vfenehs" }, { SYSZ_INS_VFENEZB, "vfenezb" }, { SYSZ_INS_VFENEZBS, "vfenezbs" }, { SYSZ_INS_VFENEZF, "vfenezf" }, { SYSZ_INS_VFENEZFS, "vfenezfs" }, { SYSZ_INS_VFENEZH, "vfenezh" }, { SYSZ_INS_VFENEZHS, "vfenezhs" }, { SYSZ_INS_VFI, "vfi" }, { SYSZ_INS_VFIDB, "vfidb" }, { SYSZ_INS_VFISB, "vfisb" }, { SYSZ_INS_VFKEDB, "vfkedb" }, { SYSZ_INS_VFKEDBS, "vfkedbs" }, { SYSZ_INS_VFKESB, "vfkesb" }, { SYSZ_INS_VFKESBS, "vfkesbs" }, { SYSZ_INS_VFKHDB, "vfkhdb" }, { SYSZ_INS_VFKHDBS, "vfkhdbs" }, { SYSZ_INS_VFKHEDB, "vfkhedb" }, { SYSZ_INS_VFKHEDBS, "vfkhedbs" }, { SYSZ_INS_VFKHESB, "vfkhesb" }, { SYSZ_INS_VFKHESBS, "vfkhesbs" }, { SYSZ_INS_VFKHSB, "vfkhsb" }, { SYSZ_INS_VFKHSBS, "vfkhsbs" }, { SYSZ_INS_VFLCDB, "vflcdb" }, { SYSZ_INS_VFLCSB, "vflcsb" }, { SYSZ_INS_VFLL, "vfll" }, { SYSZ_INS_VFLLS, "vflls" }, { SYSZ_INS_VFLNDB, "vflndb" }, { SYSZ_INS_VFLNSB, "vflnsb" }, { SYSZ_INS_VFLPDB, "vflpdb" }, { SYSZ_INS_VFLPSB, "vflpsb" }, { SYSZ_INS_VFLR, "vflr" }, { SYSZ_INS_VFLRD, "vflrd" }, { SYSZ_INS_VFM, "vfm" }, { SYSZ_INS_VFMA, "vfma" }, { SYSZ_INS_VFMADB, "vfmadb" }, { SYSZ_INS_VFMASB, "vfmasb" }, { SYSZ_INS_VFMAX, "vfmax" }, { SYSZ_INS_VFMAXDB, "vfmaxdb" }, { SYSZ_INS_VFMAXSB, "vfmaxsb" }, { SYSZ_INS_VFMDB, "vfmdb" }, { SYSZ_INS_VFMIN, "vfmin" }, { SYSZ_INS_VFMINDB, "vfmindb" }, { SYSZ_INS_VFMINSB, "vfminsb" }, { SYSZ_INS_VFMS, "vfms" }, { SYSZ_INS_VFMSB, "vfmsb" }, { SYSZ_INS_VFMSDB, "vfmsdb" }, { SYSZ_INS_VFMSSB, "vfmssb" }, { SYSZ_INS_VFNMA, "vfnma" }, { SYSZ_INS_VFNMADB, "vfnmadb" }, { SYSZ_INS_VFNMASB, "vfnmasb" }, { SYSZ_INS_VFNMS, "vfnms" }, { SYSZ_INS_VFNMSDB, "vfnmsdb" }, { SYSZ_INS_VFNMSSB, "vfnmssb" }, { SYSZ_INS_VFPSO, "vfpso" }, { SYSZ_INS_VFPSODB, "vfpsodb" }, { SYSZ_INS_VFPSOSB, "vfpsosb" }, { SYSZ_INS_VFS, "vfs" }, { SYSZ_INS_VFSDB, "vfsdb" }, { SYSZ_INS_VFSQ, "vfsq" }, { SYSZ_INS_VFSQDB, "vfsqdb" }, { SYSZ_INS_VFSQSB, "vfsqsb" }, { SYSZ_INS_VFSSB, "vfssb" }, { SYSZ_INS_VFTCI, "vftci" }, { SYSZ_INS_VFTCIDB, "vftcidb" }, { SYSZ_INS_VFTCISB, "vftcisb" }, { SYSZ_INS_VGBM, "vgbm" }, { SYSZ_INS_VGEF, "vgef" }, { SYSZ_INS_VGEG, "vgeg" }, { SYSZ_INS_VGFM, "vgfm" }, { SYSZ_INS_VGFMA, "vgfma" }, { SYSZ_INS_VGFMAB, "vgfmab" }, { SYSZ_INS_VGFMAF, "vgfmaf" }, { SYSZ_INS_VGFMAG, "vgfmag" }, { SYSZ_INS_VGFMAH, "vgfmah" }, { SYSZ_INS_VGFMB, "vgfmb" }, { SYSZ_INS_VGFMF, "vgfmf" }, { SYSZ_INS_VGFMG, "vgfmg" }, { SYSZ_INS_VGFMH, "vgfmh" }, { SYSZ_INS_VGM, "vgm" }, { SYSZ_INS_VGMB, "vgmb" }, { SYSZ_INS_VGMF, "vgmf" }, { SYSZ_INS_VGMG, "vgmg" }, { SYSZ_INS_VGMH, "vgmh" }, { SYSZ_INS_VISTR, "vistr" }, { SYSZ_INS_VISTRB, "vistrb" }, { SYSZ_INS_VISTRBS, "vistrbs" }, { SYSZ_INS_VISTRF, "vistrf" }, { SYSZ_INS_VISTRFS, "vistrfs" }, { SYSZ_INS_VISTRH, "vistrh" }, { SYSZ_INS_VISTRHS, "vistrhs" }, { SYSZ_INS_VL, "vl" }, { SYSZ_INS_VLBB, "vlbb" }, { SYSZ_INS_VLC, "vlc" }, { SYSZ_INS_VLCB, "vlcb" }, { SYSZ_INS_VLCF, "vlcf" }, { SYSZ_INS_VLCG, "vlcg" }, { SYSZ_INS_VLCH, "vlch" }, { SYSZ_INS_VLDE, "vlde" }, { SYSZ_INS_VLDEB, "vldeb" }, { SYSZ_INS_VLEB, "vleb" }, { SYSZ_INS_VLED, "vled" }, { SYSZ_INS_VLEDB, "vledb" }, { SYSZ_INS_VLEF, "vlef" }, { SYSZ_INS_VLEG, "vleg" }, { SYSZ_INS_VLEH, "vleh" }, { SYSZ_INS_VLEIB, "vleib" }, { SYSZ_INS_VLEIF, "vleif" }, { SYSZ_INS_VLEIG, "vleig" }, { SYSZ_INS_VLEIH, "vleih" }, { SYSZ_INS_VLGV, "vlgv" }, { SYSZ_INS_VLGVB, "vlgvb" }, { SYSZ_INS_VLGVF, "vlgvf" }, { SYSZ_INS_VLGVG, "vlgvg" }, { SYSZ_INS_VLGVH, "vlgvh" }, { SYSZ_INS_VLIP, "vlip" }, { SYSZ_INS_VLL, "vll" }, { SYSZ_INS_VLLEZ, "vllez" }, { SYSZ_INS_VLLEZB, "vllezb" }, { SYSZ_INS_VLLEZF, "vllezf" }, { SYSZ_INS_VLLEZG, "vllezg" }, { SYSZ_INS_VLLEZH, "vllezh" }, { SYSZ_INS_VLLEZLF, "vllezlf" }, { SYSZ_INS_VLM, "vlm" }, { SYSZ_INS_VLP, "vlp" }, { SYSZ_INS_VLPB, "vlpb" }, { SYSZ_INS_VLPF, "vlpf" }, { SYSZ_INS_VLPG, "vlpg" }, { SYSZ_INS_VLPH, "vlph" }, { SYSZ_INS_VLR, "vlr" }, { SYSZ_INS_VLREP, "vlrep" }, { SYSZ_INS_VLREPB, "vlrepb" }, { SYSZ_INS_VLREPF, "vlrepf" }, { SYSZ_INS_VLREPG, "vlrepg" }, { SYSZ_INS_VLREPH, "vlreph" }, { SYSZ_INS_VLRL, "vlrl" }, { SYSZ_INS_VLRLR, "vlrlr" }, { SYSZ_INS_VLVG, "vlvg" }, { SYSZ_INS_VLVGB, "vlvgb" }, { SYSZ_INS_VLVGF, "vlvgf" }, { SYSZ_INS_VLVGG, "vlvgg" }, { SYSZ_INS_VLVGH, "vlvgh" }, { SYSZ_INS_VLVGP, "vlvgp" }, { SYSZ_INS_VMAE, "vmae" }, { SYSZ_INS_VMAEB, "vmaeb" }, { SYSZ_INS_VMAEF, "vmaef" }, { SYSZ_INS_VMAEH, "vmaeh" }, { SYSZ_INS_VMAH, "vmah" }, { SYSZ_INS_VMAHB, "vmahb" }, { SYSZ_INS_VMAHF, "vmahf" }, { SYSZ_INS_VMAHH, "vmahh" }, { SYSZ_INS_VMAL, "vmal" }, { SYSZ_INS_VMALB, "vmalb" }, { SYSZ_INS_VMALE, "vmale" }, { SYSZ_INS_VMALEB, "vmaleb" }, { SYSZ_INS_VMALEF, "vmalef" }, { SYSZ_INS_VMALEH, "vmaleh" }, { SYSZ_INS_VMALF, "vmalf" }, { SYSZ_INS_VMALH, "vmalh" }, { SYSZ_INS_VMALHB, "vmalhb" }, { SYSZ_INS_VMALHF, "vmalhf" }, { SYSZ_INS_VMALHH, "vmalhh" }, { SYSZ_INS_VMALHW, "vmalhw" }, { SYSZ_INS_VMALO, "vmalo" }, { SYSZ_INS_VMALOB, "vmalob" }, { SYSZ_INS_VMALOF, "vmalof" }, { SYSZ_INS_VMALOH, "vmaloh" }, { SYSZ_INS_VMAO, "vmao" }, { SYSZ_INS_VMAOB, "vmaob" }, { SYSZ_INS_VMAOF, "vmaof" }, { SYSZ_INS_VMAOH, "vmaoh" }, { SYSZ_INS_VME, "vme" }, { SYSZ_INS_VMEB, "vmeb" }, { SYSZ_INS_VMEF, "vmef" }, { SYSZ_INS_VMEH, "vmeh" }, { SYSZ_INS_VMH, "vmh" }, { SYSZ_INS_VMHB, "vmhb" }, { SYSZ_INS_VMHF, "vmhf" }, { SYSZ_INS_VMHH, "vmhh" }, { SYSZ_INS_VML, "vml" }, { SYSZ_INS_VMLB, "vmlb" }, { SYSZ_INS_VMLE, "vmle" }, { SYSZ_INS_VMLEB, "vmleb" }, { SYSZ_INS_VMLEF, "vmlef" }, { SYSZ_INS_VMLEH, "vmleh" }, { SYSZ_INS_VMLF, "vmlf" }, { SYSZ_INS_VMLH, "vmlh" }, { SYSZ_INS_VMLHB, "vmlhb" }, { SYSZ_INS_VMLHF, "vmlhf" }, { SYSZ_INS_VMLHH, "vmlhh" }, { SYSZ_INS_VMLHW, "vmlhw" }, { SYSZ_INS_VMLO, "vmlo" }, { SYSZ_INS_VMLOB, "vmlob" }, { SYSZ_INS_VMLOF, "vmlof" }, { SYSZ_INS_VMLOH, "vmloh" }, { SYSZ_INS_VMN, "vmn" }, { SYSZ_INS_VMNB, "vmnb" }, { SYSZ_INS_VMNF, "vmnf" }, { SYSZ_INS_VMNG, "vmng" }, { SYSZ_INS_VMNH, "vmnh" }, { SYSZ_INS_VMNL, "vmnl" }, { SYSZ_INS_VMNLB, "vmnlb" }, { SYSZ_INS_VMNLF, "vmnlf" }, { SYSZ_INS_VMNLG, "vmnlg" }, { SYSZ_INS_VMNLH, "vmnlh" }, { SYSZ_INS_VMO, "vmo" }, { SYSZ_INS_VMOB, "vmob" }, { SYSZ_INS_VMOF, "vmof" }, { SYSZ_INS_VMOH, "vmoh" }, { SYSZ_INS_VMP, "vmp" }, { SYSZ_INS_VMRH, "vmrh" }, { SYSZ_INS_VMRHB, "vmrhb" }, { SYSZ_INS_VMRHF, "vmrhf" }, { SYSZ_INS_VMRHG, "vmrhg" }, { SYSZ_INS_VMRHH, "vmrhh" }, { SYSZ_INS_VMRL, "vmrl" }, { SYSZ_INS_VMRLB, "vmrlb" }, { SYSZ_INS_VMRLF, "vmrlf" }, { SYSZ_INS_VMRLG, "vmrlg" }, { SYSZ_INS_VMRLH, "vmrlh" }, { SYSZ_INS_VMSL, "vmsl" }, { SYSZ_INS_VMSLG, "vmslg" }, { SYSZ_INS_VMSP, "vmsp" }, { SYSZ_INS_VMX, "vmx" }, { SYSZ_INS_VMXB, "vmxb" }, { SYSZ_INS_VMXF, "vmxf" }, { SYSZ_INS_VMXG, "vmxg" }, { SYSZ_INS_VMXH, "vmxh" }, { SYSZ_INS_VMXL, "vmxl" }, { SYSZ_INS_VMXLB, "vmxlb" }, { SYSZ_INS_VMXLF, "vmxlf" }, { SYSZ_INS_VMXLG, "vmxlg" }, { SYSZ_INS_VMXLH, "vmxlh" }, { SYSZ_INS_VN, "vn" }, { SYSZ_INS_VNC, "vnc" }, { SYSZ_INS_VNN, "vnn" }, { SYSZ_INS_VNO, "vno" }, { SYSZ_INS_VNX, "vnx" }, { SYSZ_INS_VO, "vo" }, { SYSZ_INS_VOC, "voc" }, { SYSZ_INS_VONE, "vone" }, { SYSZ_INS_VPDI, "vpdi" }, { SYSZ_INS_VPERM, "vperm" }, { SYSZ_INS_VPK, "vpk" }, { SYSZ_INS_VPKF, "vpkf" }, { SYSZ_INS_VPKG, "vpkg" }, { SYSZ_INS_VPKH, "vpkh" }, { SYSZ_INS_VPKLS, "vpkls" }, { SYSZ_INS_VPKLSF, "vpklsf" }, { SYSZ_INS_VPKLSFS, "vpklsfs" }, { SYSZ_INS_VPKLSG, "vpklsg" }, { SYSZ_INS_VPKLSGS, "vpklsgs" }, { SYSZ_INS_VPKLSH, "vpklsh" }, { SYSZ_INS_VPKLSHS, "vpklshs" }, { SYSZ_INS_VPKS, "vpks" }, { SYSZ_INS_VPKSF, "vpksf" }, { SYSZ_INS_VPKSFS, "vpksfs" }, { SYSZ_INS_VPKSG, "vpksg" }, { SYSZ_INS_VPKSGS, "vpksgs" }, { SYSZ_INS_VPKSH, "vpksh" }, { SYSZ_INS_VPKSHS, "vpkshs" }, { SYSZ_INS_VPKZ, "vpkz" }, { SYSZ_INS_VPOPCT, "vpopct" }, { SYSZ_INS_VPOPCTB, "vpopctb" }, { SYSZ_INS_VPOPCTF, "vpopctf" }, { SYSZ_INS_VPOPCTG, "vpopctg" }, { SYSZ_INS_VPOPCTH, "vpopcth" }, { SYSZ_INS_VPSOP, "vpsop" }, { SYSZ_INS_VREP, "vrep" }, { SYSZ_INS_VREPB, "vrepb" }, { SYSZ_INS_VREPF, "vrepf" }, { SYSZ_INS_VREPG, "vrepg" }, { SYSZ_INS_VREPH, "vreph" }, { SYSZ_INS_VREPI, "vrepi" }, { SYSZ_INS_VREPIB, "vrepib" }, { SYSZ_INS_VREPIF, "vrepif" }, { SYSZ_INS_VREPIG, "vrepig" }, { SYSZ_INS_VREPIH, "vrepih" }, { SYSZ_INS_VRP, "vrp" }, { SYSZ_INS_VS, "vs" }, { SYSZ_INS_VSB, "vsb" }, { SYSZ_INS_VSBCBI, "vsbcbi" }, { SYSZ_INS_VSBCBIQ, "vsbcbiq" }, { SYSZ_INS_VSBI, "vsbi" }, { SYSZ_INS_VSBIQ, "vsbiq" }, { SYSZ_INS_VSCBI, "vscbi" }, { SYSZ_INS_VSCBIB, "vscbib" }, { SYSZ_INS_VSCBIF, "vscbif" }, { SYSZ_INS_VSCBIG, "vscbig" }, { SYSZ_INS_VSCBIH, "vscbih" }, { SYSZ_INS_VSCBIQ, "vscbiq" }, { SYSZ_INS_VSCEF, "vscef" }, { SYSZ_INS_VSCEG, "vsceg" }, { SYSZ_INS_VSDP, "vsdp" }, { SYSZ_INS_VSEG, "vseg" }, { SYSZ_INS_VSEGB, "vsegb" }, { SYSZ_INS_VSEGF, "vsegf" }, { SYSZ_INS_VSEGH, "vsegh" }, { SYSZ_INS_VSEL, "vsel" }, { SYSZ_INS_VSF, "vsf" }, { SYSZ_INS_VSG, "vsg" }, { SYSZ_INS_VSH, "vsh" }, { SYSZ_INS_VSL, "vsl" }, { SYSZ_INS_VSLB, "vslb" }, { SYSZ_INS_VSLDB, "vsldb" }, { SYSZ_INS_VSP, "vsp" }, { SYSZ_INS_VSQ, "vsq" }, { SYSZ_INS_VSRA, "vsra" }, { SYSZ_INS_VSRAB, "vsrab" }, { SYSZ_INS_VSRL, "vsrl" }, { SYSZ_INS_VSRLB, "vsrlb" }, { SYSZ_INS_VSRP, "vsrp" }, { SYSZ_INS_VST, "vst" }, { SYSZ_INS_VSTEB, "vsteb" }, { SYSZ_INS_VSTEF, "vstef" }, { SYSZ_INS_VSTEG, "vsteg" }, { SYSZ_INS_VSTEH, "vsteh" }, { SYSZ_INS_VSTL, "vstl" }, { SYSZ_INS_VSTM, "vstm" }, { SYSZ_INS_VSTRC, "vstrc" }, { SYSZ_INS_VSTRCB, "vstrcb" }, { SYSZ_INS_VSTRCBS, "vstrcbs" }, { SYSZ_INS_VSTRCF, "vstrcf" }, { SYSZ_INS_VSTRCFS, "vstrcfs" }, { SYSZ_INS_VSTRCH, "vstrch" }, { SYSZ_INS_VSTRCHS, "vstrchs" }, { SYSZ_INS_VSTRCZB, "vstrczb" }, { SYSZ_INS_VSTRCZBS, "vstrczbs" }, { SYSZ_INS_VSTRCZF, "vstrczf" }, { SYSZ_INS_VSTRCZFS, "vstrczfs" }, { SYSZ_INS_VSTRCZH, "vstrczh" }, { SYSZ_INS_VSTRCZHS, "vstrczhs" }, { SYSZ_INS_VSTRL, "vstrl" }, { SYSZ_INS_VSTRLR, "vstrlr" }, { SYSZ_INS_VSUM, "vsum" }, { SYSZ_INS_VSUMB, "vsumb" }, { SYSZ_INS_VSUMG, "vsumg" }, { SYSZ_INS_VSUMGF, "vsumgf" }, { SYSZ_INS_VSUMGH, "vsumgh" }, { SYSZ_INS_VSUMH, "vsumh" }, { SYSZ_INS_VSUMQ, "vsumq" }, { SYSZ_INS_VSUMQF, "vsumqf" }, { SYSZ_INS_VSUMQG, "vsumqg" }, { SYSZ_INS_VTM, "vtm" }, { SYSZ_INS_VTP, "vtp" }, { SYSZ_INS_VUPH, "vuph" }, { SYSZ_INS_VUPHB, "vuphb" }, { SYSZ_INS_VUPHF, "vuphf" }, { SYSZ_INS_VUPHH, "vuphh" }, { SYSZ_INS_VUPKZ, "vupkz" }, { SYSZ_INS_VUPL, "vupl" }, { SYSZ_INS_VUPLB, "vuplb" }, { SYSZ_INS_VUPLF, "vuplf" }, { SYSZ_INS_VUPLH, "vuplh" }, { SYSZ_INS_VUPLHB, "vuplhb" }, { SYSZ_INS_VUPLHF, "vuplhf" }, { SYSZ_INS_VUPLHH, "vuplhh" }, { SYSZ_INS_VUPLHW, "vuplhw" }, { SYSZ_INS_VUPLL, "vupll" }, { SYSZ_INS_VUPLLB, "vupllb" }, { SYSZ_INS_VUPLLF, "vupllf" }, { SYSZ_INS_VUPLLH, "vupllh" }, { SYSZ_INS_VX, "vx" }, { SYSZ_INS_VZERO, "vzero" }, { SYSZ_INS_WCDGB, "wcdgb" }, { SYSZ_INS_WCDLGB, "wcdlgb" }, { SYSZ_INS_WCGDB, "wcgdb" }, { SYSZ_INS_WCLGDB, "wclgdb" }, { SYSZ_INS_WFADB, "wfadb" }, { SYSZ_INS_WFASB, "wfasb" }, { SYSZ_INS_WFAXB, "wfaxb" }, { SYSZ_INS_WFC, "wfc" }, { SYSZ_INS_WFCDB, "wfcdb" }, { SYSZ_INS_WFCEDB, "wfcedb" }, { SYSZ_INS_WFCEDBS, "wfcedbs" }, { SYSZ_INS_WFCESB, "wfcesb" }, { SYSZ_INS_WFCESBS, "wfcesbs" }, { SYSZ_INS_WFCEXB, "wfcexb" }, { SYSZ_INS_WFCEXBS, "wfcexbs" }, { SYSZ_INS_WFCHDB, "wfchdb" }, { SYSZ_INS_WFCHDBS, "wfchdbs" }, { SYSZ_INS_WFCHEDB, "wfchedb" }, { SYSZ_INS_WFCHEDBS, "wfchedbs" }, { SYSZ_INS_WFCHESB, "wfchesb" }, { SYSZ_INS_WFCHESBS, "wfchesbs" }, { SYSZ_INS_WFCHEXB, "wfchexb" }, { SYSZ_INS_WFCHEXBS, "wfchexbs" }, { SYSZ_INS_WFCHSB, "wfchsb" }, { SYSZ_INS_WFCHSBS, "wfchsbs" }, { SYSZ_INS_WFCHXB, "wfchxb" }, { SYSZ_INS_WFCHXBS, "wfchxbs" }, { SYSZ_INS_WFCSB, "wfcsb" }, { SYSZ_INS_WFCXB, "wfcxb" }, { SYSZ_INS_WFDDB, "wfddb" }, { SYSZ_INS_WFDSB, "wfdsb" }, { SYSZ_INS_WFDXB, "wfdxb" }, { SYSZ_INS_WFIDB, "wfidb" }, { SYSZ_INS_WFISB, "wfisb" }, { SYSZ_INS_WFIXB, "wfixb" }, { SYSZ_INS_WFK, "wfk" }, { SYSZ_INS_WFKDB, "wfkdb" }, { SYSZ_INS_WFKEDB, "wfkedb" }, { SYSZ_INS_WFKEDBS, "wfkedbs" }, { SYSZ_INS_WFKESB, "wfkesb" }, { SYSZ_INS_WFKESBS, "wfkesbs" }, { SYSZ_INS_WFKEXB, "wfkexb" }, { SYSZ_INS_WFKEXBS, "wfkexbs" }, { SYSZ_INS_WFKHDB, "wfkhdb" }, { SYSZ_INS_WFKHDBS, "wfkhdbs" }, { SYSZ_INS_WFKHEDB, "wfkhedb" }, { SYSZ_INS_WFKHEDBS, "wfkhedbs" }, { SYSZ_INS_WFKHESB, "wfkhesb" }, { SYSZ_INS_WFKHESBS, "wfkhesbs" }, { SYSZ_INS_WFKHEXB, "wfkhexb" }, { SYSZ_INS_WFKHEXBS, "wfkhexbs" }, { SYSZ_INS_WFKHSB, "wfkhsb" }, { SYSZ_INS_WFKHSBS, "wfkhsbs" }, { SYSZ_INS_WFKHXB, "wfkhxb" }, { SYSZ_INS_WFKHXBS, "wfkhxbs" }, { SYSZ_INS_WFKSB, "wfksb" }, { SYSZ_INS_WFKXB, "wfkxb" }, { SYSZ_INS_WFLCDB, "wflcdb" }, { SYSZ_INS_WFLCSB, "wflcsb" }, { SYSZ_INS_WFLCXB, "wflcxb" }, { SYSZ_INS_WFLLD, "wflld" }, { SYSZ_INS_WFLLS, "wflls" }, { SYSZ_INS_WFLNDB, "wflndb" }, { SYSZ_INS_WFLNSB, "wflnsb" }, { SYSZ_INS_WFLNXB, "wflnxb" }, { SYSZ_INS_WFLPDB, "wflpdb" }, { SYSZ_INS_WFLPSB, "wflpsb" }, { SYSZ_INS_WFLPXB, "wflpxb" }, { SYSZ_INS_WFLRD, "wflrd" }, { SYSZ_INS_WFLRX, "wflrx" }, { SYSZ_INS_WFMADB, "wfmadb" }, { SYSZ_INS_WFMASB, "wfmasb" }, { SYSZ_INS_WFMAXB, "wfmaxb" }, { SYSZ_INS_WFMAXDB, "wfmaxdb" }, { SYSZ_INS_WFMAXSB, "wfmaxsb" }, { SYSZ_INS_WFMAXXB, "wfmaxxb" }, { SYSZ_INS_WFMDB, "wfmdb" }, { SYSZ_INS_WFMINDB, "wfmindb" }, { SYSZ_INS_WFMINSB, "wfminsb" }, { SYSZ_INS_WFMINXB, "wfminxb" }, { SYSZ_INS_WFMSB, "wfmsb" }, { SYSZ_INS_WFMSDB, "wfmsdb" }, { SYSZ_INS_WFMSSB, "wfmssb" }, { SYSZ_INS_WFMSXB, "wfmsxb" }, { SYSZ_INS_WFMXB, "wfmxb" }, { SYSZ_INS_WFNMADB, "wfnmadb" }, { SYSZ_INS_WFNMASB, "wfnmasb" }, { SYSZ_INS_WFNMAXB, "wfnmaxb" }, { SYSZ_INS_WFNMSDB, "wfnmsdb" }, { SYSZ_INS_WFNMSSB, "wfnmssb" }, { SYSZ_INS_WFNMSXB, "wfnmsxb" }, { SYSZ_INS_WFPSODB, "wfpsodb" }, { SYSZ_INS_WFPSOSB, "wfpsosb" }, { SYSZ_INS_WFPSOXB, "wfpsoxb" }, { SYSZ_INS_WFSDB, "wfsdb" }, { SYSZ_INS_WFSQDB, "wfsqdb" }, { SYSZ_INS_WFSQSB, "wfsqsb" }, { SYSZ_INS_WFSQXB, "wfsqxb" }, { SYSZ_INS_WFSSB, "wfssb" }, { SYSZ_INS_WFSXB, "wfsxb" }, { SYSZ_INS_WFTCIDB, "wftcidb" }, { SYSZ_INS_WFTCISB, "wftcisb" }, { SYSZ_INS_WFTCIXB, "wftcixb" }, { SYSZ_INS_WLDEB, "wldeb" }, { SYSZ_INS_WLEDB, "wledb" }, { SYSZ_INS_XSCH, "xsch" }, { SYSZ_INS_ZAP, "zap" }, capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZGenInstrInfo.inc000064400000000000000000002250520072674642500231430ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { SystemZ_PHI = 0, SystemZ_INLINEASM = 1, SystemZ_CFI_INSTRUCTION = 2, SystemZ_EH_LABEL = 3, SystemZ_GC_LABEL = 4, SystemZ_ANNOTATION_LABEL = 5, SystemZ_KILL = 6, SystemZ_EXTRACT_SUBREG = 7, SystemZ_INSERT_SUBREG = 8, SystemZ_IMPLICIT_DEF = 9, SystemZ_SUBREG_TO_REG = 10, SystemZ_COPY_TO_REGCLASS = 11, SystemZ_DBG_VALUE = 12, SystemZ_DBG_LABEL = 13, SystemZ_REG_SEQUENCE = 14, SystemZ_COPY = 15, SystemZ_BUNDLE = 16, SystemZ_LIFETIME_START = 17, SystemZ_LIFETIME_END = 18, SystemZ_STACKMAP = 19, SystemZ_FENTRY_CALL = 20, SystemZ_PATCHPOINT = 21, SystemZ_LOAD_STACK_GUARD = 22, SystemZ_STATEPOINT = 23, SystemZ_LOCAL_ESCAPE = 24, SystemZ_FAULTING_OP = 25, SystemZ_PATCHABLE_OP = 26, SystemZ_PATCHABLE_FUNCTION_ENTER = 27, SystemZ_PATCHABLE_RET = 28, SystemZ_PATCHABLE_FUNCTION_EXIT = 29, SystemZ_PATCHABLE_TAIL_CALL = 30, SystemZ_PATCHABLE_EVENT_CALL = 31, SystemZ_PATCHABLE_TYPED_EVENT_CALL = 32, SystemZ_ICALL_BRANCH_FUNNEL = 33, SystemZ_G_ADD = 34, SystemZ_G_SUB = 35, SystemZ_G_MUL = 36, SystemZ_G_SDIV = 37, SystemZ_G_UDIV = 38, SystemZ_G_SREM = 39, SystemZ_G_UREM = 40, SystemZ_G_AND = 41, SystemZ_G_OR = 42, SystemZ_G_XOR = 43, SystemZ_G_IMPLICIT_DEF = 44, SystemZ_G_PHI = 45, SystemZ_G_FRAME_INDEX = 46, SystemZ_G_GLOBAL_VALUE = 47, SystemZ_G_EXTRACT = 48, SystemZ_G_UNMERGE_VALUES = 49, SystemZ_G_INSERT = 50, SystemZ_G_MERGE_VALUES = 51, SystemZ_G_PTRTOINT = 52, SystemZ_G_INTTOPTR = 53, SystemZ_G_BITCAST = 54, SystemZ_G_LOAD = 55, SystemZ_G_SEXTLOAD = 56, SystemZ_G_ZEXTLOAD = 57, SystemZ_G_STORE = 58, SystemZ_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, SystemZ_G_ATOMIC_CMPXCHG = 60, SystemZ_G_ATOMICRMW_XCHG = 61, SystemZ_G_ATOMICRMW_ADD = 62, SystemZ_G_ATOMICRMW_SUB = 63, SystemZ_G_ATOMICRMW_AND = 64, SystemZ_G_ATOMICRMW_NAND = 65, SystemZ_G_ATOMICRMW_OR = 66, SystemZ_G_ATOMICRMW_XOR = 67, SystemZ_G_ATOMICRMW_MAX = 68, SystemZ_G_ATOMICRMW_MIN = 69, SystemZ_G_ATOMICRMW_UMAX = 70, SystemZ_G_ATOMICRMW_UMIN = 71, SystemZ_G_BRCOND = 72, SystemZ_G_BRINDIRECT = 73, SystemZ_G_INTRINSIC = 74, SystemZ_G_INTRINSIC_W_SIDE_EFFECTS = 75, SystemZ_G_ANYEXT = 76, SystemZ_G_TRUNC = 77, SystemZ_G_CONSTANT = 78, SystemZ_G_FCONSTANT = 79, SystemZ_G_VASTART = 80, SystemZ_G_VAARG = 81, SystemZ_G_SEXT = 82, SystemZ_G_ZEXT = 83, SystemZ_G_SHL = 84, SystemZ_G_LSHR = 85, SystemZ_G_ASHR = 86, SystemZ_G_ICMP = 87, SystemZ_G_FCMP = 88, SystemZ_G_SELECT = 89, SystemZ_G_UADDE = 90, SystemZ_G_USUBE = 91, SystemZ_G_SADDO = 92, SystemZ_G_SSUBO = 93, SystemZ_G_UMULO = 94, SystemZ_G_SMULO = 95, SystemZ_G_UMULH = 96, SystemZ_G_SMULH = 97, SystemZ_G_FADD = 98, SystemZ_G_FSUB = 99, SystemZ_G_FMUL = 100, SystemZ_G_FMA = 101, SystemZ_G_FDIV = 102, SystemZ_G_FREM = 103, SystemZ_G_FPOW = 104, SystemZ_G_FEXP = 105, SystemZ_G_FEXP2 = 106, SystemZ_G_FLOG = 107, SystemZ_G_FLOG2 = 108, SystemZ_G_FNEG = 109, SystemZ_G_FPEXT = 110, SystemZ_G_FPTRUNC = 111, SystemZ_G_FPTOSI = 112, SystemZ_G_FPTOUI = 113, SystemZ_G_SITOFP = 114, SystemZ_G_UITOFP = 115, SystemZ_G_FABS = 116, SystemZ_G_GEP = 117, SystemZ_G_PTR_MASK = 118, SystemZ_G_BR = 119, SystemZ_G_INSERT_VECTOR_ELT = 120, SystemZ_G_EXTRACT_VECTOR_ELT = 121, SystemZ_G_SHUFFLE_VECTOR = 122, SystemZ_G_BSWAP = 123, SystemZ_G_ADDRSPACE_CAST = 124, SystemZ_ADJCALLSTACKDOWN = 125, SystemZ_ADJCALLSTACKUP = 126, SystemZ_ADJDYNALLOC = 127, SystemZ_AEXT128 = 128, SystemZ_AFIMux = 129, SystemZ_AHIMux = 130, SystemZ_AHIMuxK = 131, SystemZ_ATOMIC_CMP_SWAPW = 132, SystemZ_ATOMIC_LOADW_AFI = 133, SystemZ_ATOMIC_LOADW_AR = 134, SystemZ_ATOMIC_LOADW_MAX = 135, SystemZ_ATOMIC_LOADW_MIN = 136, SystemZ_ATOMIC_LOADW_NILH = 137, SystemZ_ATOMIC_LOADW_NILHi = 138, SystemZ_ATOMIC_LOADW_NR = 139, SystemZ_ATOMIC_LOADW_NRi = 140, SystemZ_ATOMIC_LOADW_OILH = 141, SystemZ_ATOMIC_LOADW_OR = 142, SystemZ_ATOMIC_LOADW_SR = 143, SystemZ_ATOMIC_LOADW_UMAX = 144, SystemZ_ATOMIC_LOADW_UMIN = 145, SystemZ_ATOMIC_LOADW_XILF = 146, SystemZ_ATOMIC_LOADW_XR = 147, SystemZ_ATOMIC_LOAD_AFI = 148, SystemZ_ATOMIC_LOAD_AGFI = 149, SystemZ_ATOMIC_LOAD_AGHI = 150, SystemZ_ATOMIC_LOAD_AGR = 151, SystemZ_ATOMIC_LOAD_AHI = 152, SystemZ_ATOMIC_LOAD_AR = 153, SystemZ_ATOMIC_LOAD_MAX_32 = 154, SystemZ_ATOMIC_LOAD_MAX_64 = 155, SystemZ_ATOMIC_LOAD_MIN_32 = 156, SystemZ_ATOMIC_LOAD_MIN_64 = 157, SystemZ_ATOMIC_LOAD_NGR = 158, SystemZ_ATOMIC_LOAD_NGRi = 159, SystemZ_ATOMIC_LOAD_NIHF64 = 160, SystemZ_ATOMIC_LOAD_NIHF64i = 161, SystemZ_ATOMIC_LOAD_NIHH64 = 162, SystemZ_ATOMIC_LOAD_NIHH64i = 163, SystemZ_ATOMIC_LOAD_NIHL64 = 164, SystemZ_ATOMIC_LOAD_NIHL64i = 165, SystemZ_ATOMIC_LOAD_NILF = 166, SystemZ_ATOMIC_LOAD_NILF64 = 167, SystemZ_ATOMIC_LOAD_NILF64i = 168, SystemZ_ATOMIC_LOAD_NILFi = 169, SystemZ_ATOMIC_LOAD_NILH = 170, SystemZ_ATOMIC_LOAD_NILH64 = 171, SystemZ_ATOMIC_LOAD_NILH64i = 172, SystemZ_ATOMIC_LOAD_NILHi = 173, SystemZ_ATOMIC_LOAD_NILL = 174, SystemZ_ATOMIC_LOAD_NILL64 = 175, SystemZ_ATOMIC_LOAD_NILL64i = 176, SystemZ_ATOMIC_LOAD_NILLi = 177, SystemZ_ATOMIC_LOAD_NR = 178, SystemZ_ATOMIC_LOAD_NRi = 179, SystemZ_ATOMIC_LOAD_OGR = 180, SystemZ_ATOMIC_LOAD_OIHF64 = 181, SystemZ_ATOMIC_LOAD_OIHH64 = 182, SystemZ_ATOMIC_LOAD_OIHL64 = 183, SystemZ_ATOMIC_LOAD_OILF = 184, SystemZ_ATOMIC_LOAD_OILF64 = 185, SystemZ_ATOMIC_LOAD_OILH = 186, SystemZ_ATOMIC_LOAD_OILH64 = 187, SystemZ_ATOMIC_LOAD_OILL = 188, SystemZ_ATOMIC_LOAD_OILL64 = 189, SystemZ_ATOMIC_LOAD_OR = 190, SystemZ_ATOMIC_LOAD_SGR = 191, SystemZ_ATOMIC_LOAD_SR = 192, SystemZ_ATOMIC_LOAD_UMAX_32 = 193, SystemZ_ATOMIC_LOAD_UMAX_64 = 194, SystemZ_ATOMIC_LOAD_UMIN_32 = 195, SystemZ_ATOMIC_LOAD_UMIN_64 = 196, SystemZ_ATOMIC_LOAD_XGR = 197, SystemZ_ATOMIC_LOAD_XIHF64 = 198, SystemZ_ATOMIC_LOAD_XILF = 199, SystemZ_ATOMIC_LOAD_XILF64 = 200, SystemZ_ATOMIC_LOAD_XR = 201, SystemZ_ATOMIC_SWAPW = 202, SystemZ_ATOMIC_SWAP_32 = 203, SystemZ_ATOMIC_SWAP_64 = 204, SystemZ_CFIMux = 205, SystemZ_CGIBCall = 206, SystemZ_CGIBReturn = 207, SystemZ_CGRBCall = 208, SystemZ_CGRBReturn = 209, SystemZ_CHIMux = 210, SystemZ_CIBCall = 211, SystemZ_CIBReturn = 212, SystemZ_CLCLoop = 213, SystemZ_CLCSequence = 214, SystemZ_CLFIMux = 215, SystemZ_CLGIBCall = 216, SystemZ_CLGIBReturn = 217, SystemZ_CLGRBCall = 218, SystemZ_CLGRBReturn = 219, SystemZ_CLIBCall = 220, SystemZ_CLIBReturn = 221, SystemZ_CLMux = 222, SystemZ_CLRBCall = 223, SystemZ_CLRBReturn = 224, SystemZ_CLSTLoop = 225, SystemZ_CMux = 226, SystemZ_CRBCall = 227, SystemZ_CRBReturn = 228, SystemZ_CallBASR = 229, SystemZ_CallBCR = 230, SystemZ_CallBR = 231, SystemZ_CallBRASL = 232, SystemZ_CallBRCL = 233, SystemZ_CallJG = 234, SystemZ_CondReturn = 235, SystemZ_CondStore16 = 236, SystemZ_CondStore16Inv = 237, SystemZ_CondStore16Mux = 238, SystemZ_CondStore16MuxInv = 239, SystemZ_CondStore32 = 240, SystemZ_CondStore32Inv = 241, SystemZ_CondStore32Mux = 242, SystemZ_CondStore32MuxInv = 243, SystemZ_CondStore64 = 244, SystemZ_CondStore64Inv = 245, SystemZ_CondStore8 = 246, SystemZ_CondStore8Inv = 247, SystemZ_CondStore8Mux = 248, SystemZ_CondStore8MuxInv = 249, SystemZ_CondStoreF32 = 250, SystemZ_CondStoreF32Inv = 251, SystemZ_CondStoreF64 = 252, SystemZ_CondStoreF64Inv = 253, SystemZ_CondTrap = 254, SystemZ_GOT = 255, SystemZ_IIFMux = 256, SystemZ_IIHF64 = 257, SystemZ_IIHH64 = 258, SystemZ_IIHL64 = 259, SystemZ_IIHMux = 260, SystemZ_IILF64 = 261, SystemZ_IILH64 = 262, SystemZ_IILL64 = 263, SystemZ_IILMux = 264, SystemZ_L128 = 265, SystemZ_LBMux = 266, SystemZ_LEFR = 267, SystemZ_LFER = 268, SystemZ_LHIMux = 269, SystemZ_LHMux = 270, SystemZ_LLCMux = 271, SystemZ_LLCRMux = 272, SystemZ_LLHMux = 273, SystemZ_LLHRMux = 274, SystemZ_LMux = 275, SystemZ_LOCHIMux = 276, SystemZ_LOCMux = 277, SystemZ_LOCRMux = 278, SystemZ_LRMux = 279, SystemZ_LTDBRCompare_VecPseudo = 280, SystemZ_LTEBRCompare_VecPseudo = 281, SystemZ_LTXBRCompare_VecPseudo = 282, SystemZ_LX = 283, SystemZ_MVCLoop = 284, SystemZ_MVCSequence = 285, SystemZ_MVSTLoop = 286, SystemZ_MemBarrier = 287, SystemZ_NCLoop = 288, SystemZ_NCSequence = 289, SystemZ_NIFMux = 290, SystemZ_NIHF64 = 291, SystemZ_NIHH64 = 292, SystemZ_NIHL64 = 293, SystemZ_NIHMux = 294, SystemZ_NILF64 = 295, SystemZ_NILH64 = 296, SystemZ_NILL64 = 297, SystemZ_NILMux = 298, SystemZ_OCLoop = 299, SystemZ_OCSequence = 300, SystemZ_OIFMux = 301, SystemZ_OIHF64 = 302, SystemZ_OIHH64 = 303, SystemZ_OIHL64 = 304, SystemZ_OIHMux = 305, SystemZ_OILF64 = 306, SystemZ_OILH64 = 307, SystemZ_OILL64 = 308, SystemZ_OILMux = 309, SystemZ_PAIR128 = 310, SystemZ_RISBHH = 311, SystemZ_RISBHL = 312, SystemZ_RISBLH = 313, SystemZ_RISBLL = 314, SystemZ_RISBMux = 315, SystemZ_Return = 316, SystemZ_SRSTLoop = 317, SystemZ_ST128 = 318, SystemZ_STCMux = 319, SystemZ_STHMux = 320, SystemZ_STMux = 321, SystemZ_STOCMux = 322, SystemZ_STX = 323, SystemZ_Select32 = 324, SystemZ_Select64 = 325, SystemZ_SelectF128 = 326, SystemZ_SelectF32 = 327, SystemZ_SelectF64 = 328, SystemZ_SelectVR128 = 329, SystemZ_SelectVR32 = 330, SystemZ_SelectVR64 = 331, SystemZ_Serialize = 332, SystemZ_TBEGIN_nofloat = 333, SystemZ_TLS_GDCALL = 334, SystemZ_TLS_LDCALL = 335, SystemZ_TMHH64 = 336, SystemZ_TMHL64 = 337, SystemZ_TMHMux = 338, SystemZ_TMLH64 = 339, SystemZ_TMLL64 = 340, SystemZ_TMLMux = 341, SystemZ_Trap = 342, SystemZ_VL32 = 343, SystemZ_VL64 = 344, SystemZ_VLR32 = 345, SystemZ_VLR64 = 346, SystemZ_VLVGP32 = 347, SystemZ_VST32 = 348, SystemZ_VST64 = 349, SystemZ_XCLoop = 350, SystemZ_XCSequence = 351, SystemZ_XIFMux = 352, SystemZ_XIHF64 = 353, SystemZ_XILF64 = 354, SystemZ_ZEXT128 = 355, SystemZ_A = 356, SystemZ_AD = 357, SystemZ_ADB = 358, SystemZ_ADBR = 359, SystemZ_ADR = 360, SystemZ_ADTR = 361, SystemZ_ADTRA = 362, SystemZ_AE = 363, SystemZ_AEB = 364, SystemZ_AEBR = 365, SystemZ_AER = 366, SystemZ_AFI = 367, SystemZ_AG = 368, SystemZ_AGF = 369, SystemZ_AGFI = 370, SystemZ_AGFR = 371, SystemZ_AGH = 372, SystemZ_AGHI = 373, SystemZ_AGHIK = 374, SystemZ_AGR = 375, SystemZ_AGRK = 376, SystemZ_AGSI = 377, SystemZ_AH = 378, SystemZ_AHHHR = 379, SystemZ_AHHLR = 380, SystemZ_AHI = 381, SystemZ_AHIK = 382, SystemZ_AHY = 383, SystemZ_AIH = 384, SystemZ_AL = 385, SystemZ_ALC = 386, SystemZ_ALCG = 387, SystemZ_ALCGR = 388, SystemZ_ALCR = 389, SystemZ_ALFI = 390, SystemZ_ALG = 391, SystemZ_ALGF = 392, SystemZ_ALGFI = 393, SystemZ_ALGFR = 394, SystemZ_ALGHSIK = 395, SystemZ_ALGR = 396, SystemZ_ALGRK = 397, SystemZ_ALGSI = 398, SystemZ_ALHHHR = 399, SystemZ_ALHHLR = 400, SystemZ_ALHSIK = 401, SystemZ_ALR = 402, SystemZ_ALRK = 403, SystemZ_ALSI = 404, SystemZ_ALSIH = 405, SystemZ_ALSIHN = 406, SystemZ_ALY = 407, SystemZ_AP = 408, SystemZ_AR = 409, SystemZ_ARK = 410, SystemZ_ASI = 411, SystemZ_AU = 412, SystemZ_AUR = 413, SystemZ_AW = 414, SystemZ_AWR = 415, SystemZ_AXBR = 416, SystemZ_AXR = 417, SystemZ_AXTR = 418, SystemZ_AXTRA = 419, SystemZ_AY = 420, SystemZ_B = 421, SystemZ_BAKR = 422, SystemZ_BAL = 423, SystemZ_BALR = 424, SystemZ_BAS = 425, SystemZ_BASR = 426, SystemZ_BASSM = 427, SystemZ_BAsmE = 428, SystemZ_BAsmH = 429, SystemZ_BAsmHE = 430, SystemZ_BAsmL = 431, SystemZ_BAsmLE = 432, SystemZ_BAsmLH = 433, SystemZ_BAsmM = 434, SystemZ_BAsmNE = 435, SystemZ_BAsmNH = 436, SystemZ_BAsmNHE = 437, SystemZ_BAsmNL = 438, SystemZ_BAsmNLE = 439, SystemZ_BAsmNLH = 440, SystemZ_BAsmNM = 441, SystemZ_BAsmNO = 442, SystemZ_BAsmNP = 443, SystemZ_BAsmNZ = 444, SystemZ_BAsmO = 445, SystemZ_BAsmP = 446, SystemZ_BAsmZ = 447, SystemZ_BC = 448, SystemZ_BCAsm = 449, SystemZ_BCR = 450, SystemZ_BCRAsm = 451, SystemZ_BCT = 452, SystemZ_BCTG = 453, SystemZ_BCTGR = 454, SystemZ_BCTR = 455, SystemZ_BI = 456, SystemZ_BIAsmE = 457, SystemZ_BIAsmH = 458, SystemZ_BIAsmHE = 459, SystemZ_BIAsmL = 460, SystemZ_BIAsmLE = 461, SystemZ_BIAsmLH = 462, SystemZ_BIAsmM = 463, SystemZ_BIAsmNE = 464, SystemZ_BIAsmNH = 465, SystemZ_BIAsmNHE = 466, SystemZ_BIAsmNL = 467, SystemZ_BIAsmNLE = 468, SystemZ_BIAsmNLH = 469, SystemZ_BIAsmNM = 470, SystemZ_BIAsmNO = 471, SystemZ_BIAsmNP = 472, SystemZ_BIAsmNZ = 473, SystemZ_BIAsmO = 474, SystemZ_BIAsmP = 475, SystemZ_BIAsmZ = 476, SystemZ_BIC = 477, SystemZ_BICAsm = 478, SystemZ_BPP = 479, SystemZ_BPRP = 480, SystemZ_BR = 481, SystemZ_BRAS = 482, SystemZ_BRASL = 483, SystemZ_BRAsmE = 484, SystemZ_BRAsmH = 485, SystemZ_BRAsmHE = 486, SystemZ_BRAsmL = 487, SystemZ_BRAsmLE = 488, SystemZ_BRAsmLH = 489, SystemZ_BRAsmM = 490, SystemZ_BRAsmNE = 491, SystemZ_BRAsmNH = 492, SystemZ_BRAsmNHE = 493, SystemZ_BRAsmNL = 494, SystemZ_BRAsmNLE = 495, SystemZ_BRAsmNLH = 496, SystemZ_BRAsmNM = 497, SystemZ_BRAsmNO = 498, SystemZ_BRAsmNP = 499, SystemZ_BRAsmNZ = 500, SystemZ_BRAsmO = 501, SystemZ_BRAsmP = 502, SystemZ_BRAsmZ = 503, SystemZ_BRC = 504, SystemZ_BRCAsm = 505, SystemZ_BRCL = 506, SystemZ_BRCLAsm = 507, SystemZ_BRCT = 508, SystemZ_BRCTG = 509, SystemZ_BRCTH = 510, SystemZ_BRXH = 511, SystemZ_BRXHG = 512, SystemZ_BRXLE = 513, SystemZ_BRXLG = 514, SystemZ_BSA = 515, SystemZ_BSG = 516, SystemZ_BSM = 517, SystemZ_BXH = 518, SystemZ_BXHG = 519, SystemZ_BXLE = 520, SystemZ_BXLEG = 521, SystemZ_C = 522, SystemZ_CD = 523, SystemZ_CDB = 524, SystemZ_CDBR = 525, SystemZ_CDFBR = 526, SystemZ_CDFBRA = 527, SystemZ_CDFR = 528, SystemZ_CDFTR = 529, SystemZ_CDGBR = 530, SystemZ_CDGBRA = 531, SystemZ_CDGR = 532, SystemZ_CDGTR = 533, SystemZ_CDGTRA = 534, SystemZ_CDLFBR = 535, SystemZ_CDLFTR = 536, SystemZ_CDLGBR = 537, SystemZ_CDLGTR = 538, SystemZ_CDPT = 539, SystemZ_CDR = 540, SystemZ_CDS = 541, SystemZ_CDSG = 542, SystemZ_CDSTR = 543, SystemZ_CDSY = 544, SystemZ_CDTR = 545, SystemZ_CDUTR = 546, SystemZ_CDZT = 547, SystemZ_CE = 548, SystemZ_CEB = 549, SystemZ_CEBR = 550, SystemZ_CEDTR = 551, SystemZ_CEFBR = 552, SystemZ_CEFBRA = 553, SystemZ_CEFR = 554, SystemZ_CEGBR = 555, SystemZ_CEGBRA = 556, SystemZ_CEGR = 557, SystemZ_CELFBR = 558, SystemZ_CELGBR = 559, SystemZ_CER = 560, SystemZ_CEXTR = 561, SystemZ_CFC = 562, SystemZ_CFDBR = 563, SystemZ_CFDBRA = 564, SystemZ_CFDR = 565, SystemZ_CFDTR = 566, SystemZ_CFEBR = 567, SystemZ_CFEBRA = 568, SystemZ_CFER = 569, SystemZ_CFI = 570, SystemZ_CFXBR = 571, SystemZ_CFXBRA = 572, SystemZ_CFXR = 573, SystemZ_CFXTR = 574, SystemZ_CG = 575, SystemZ_CGDBR = 576, SystemZ_CGDBRA = 577, SystemZ_CGDR = 578, SystemZ_CGDTR = 579, SystemZ_CGDTRA = 580, SystemZ_CGEBR = 581, SystemZ_CGEBRA = 582, SystemZ_CGER = 583, SystemZ_CGF = 584, SystemZ_CGFI = 585, SystemZ_CGFR = 586, SystemZ_CGFRL = 587, SystemZ_CGH = 588, SystemZ_CGHI = 589, SystemZ_CGHRL = 590, SystemZ_CGHSI = 591, SystemZ_CGIB = 592, SystemZ_CGIBAsm = 593, SystemZ_CGIBAsmE = 594, SystemZ_CGIBAsmH = 595, SystemZ_CGIBAsmHE = 596, SystemZ_CGIBAsmL = 597, SystemZ_CGIBAsmLE = 598, SystemZ_CGIBAsmLH = 599, SystemZ_CGIBAsmNE = 600, SystemZ_CGIBAsmNH = 601, SystemZ_CGIBAsmNHE = 602, SystemZ_CGIBAsmNL = 603, SystemZ_CGIBAsmNLE = 604, SystemZ_CGIBAsmNLH = 605, SystemZ_CGIJ = 606, SystemZ_CGIJAsm = 607, SystemZ_CGIJAsmE = 608, SystemZ_CGIJAsmH = 609, SystemZ_CGIJAsmHE = 610, SystemZ_CGIJAsmL = 611, SystemZ_CGIJAsmLE = 612, SystemZ_CGIJAsmLH = 613, SystemZ_CGIJAsmNE = 614, SystemZ_CGIJAsmNH = 615, SystemZ_CGIJAsmNHE = 616, SystemZ_CGIJAsmNL = 617, SystemZ_CGIJAsmNLE = 618, SystemZ_CGIJAsmNLH = 619, SystemZ_CGIT = 620, SystemZ_CGITAsm = 621, SystemZ_CGITAsmE = 622, SystemZ_CGITAsmH = 623, SystemZ_CGITAsmHE = 624, SystemZ_CGITAsmL = 625, SystemZ_CGITAsmLE = 626, SystemZ_CGITAsmLH = 627, SystemZ_CGITAsmNE = 628, SystemZ_CGITAsmNH = 629, SystemZ_CGITAsmNHE = 630, SystemZ_CGITAsmNL = 631, SystemZ_CGITAsmNLE = 632, SystemZ_CGITAsmNLH = 633, SystemZ_CGR = 634, SystemZ_CGRB = 635, SystemZ_CGRBAsm = 636, SystemZ_CGRBAsmE = 637, SystemZ_CGRBAsmH = 638, SystemZ_CGRBAsmHE = 639, SystemZ_CGRBAsmL = 640, SystemZ_CGRBAsmLE = 641, SystemZ_CGRBAsmLH = 642, SystemZ_CGRBAsmNE = 643, SystemZ_CGRBAsmNH = 644, SystemZ_CGRBAsmNHE = 645, SystemZ_CGRBAsmNL = 646, SystemZ_CGRBAsmNLE = 647, SystemZ_CGRBAsmNLH = 648, SystemZ_CGRJ = 649, SystemZ_CGRJAsm = 650, SystemZ_CGRJAsmE = 651, SystemZ_CGRJAsmH = 652, SystemZ_CGRJAsmHE = 653, SystemZ_CGRJAsmL = 654, SystemZ_CGRJAsmLE = 655, SystemZ_CGRJAsmLH = 656, SystemZ_CGRJAsmNE = 657, SystemZ_CGRJAsmNH = 658, SystemZ_CGRJAsmNHE = 659, SystemZ_CGRJAsmNL = 660, SystemZ_CGRJAsmNLE = 661, SystemZ_CGRJAsmNLH = 662, SystemZ_CGRL = 663, SystemZ_CGRT = 664, SystemZ_CGRTAsm = 665, SystemZ_CGRTAsmE = 666, SystemZ_CGRTAsmH = 667, SystemZ_CGRTAsmHE = 668, SystemZ_CGRTAsmL = 669, SystemZ_CGRTAsmLE = 670, SystemZ_CGRTAsmLH = 671, SystemZ_CGRTAsmNE = 672, SystemZ_CGRTAsmNH = 673, SystemZ_CGRTAsmNHE = 674, SystemZ_CGRTAsmNL = 675, SystemZ_CGRTAsmNLE = 676, SystemZ_CGRTAsmNLH = 677, SystemZ_CGXBR = 678, SystemZ_CGXBRA = 679, SystemZ_CGXR = 680, SystemZ_CGXTR = 681, SystemZ_CGXTRA = 682, SystemZ_CH = 683, SystemZ_CHF = 684, SystemZ_CHHR = 685, SystemZ_CHHSI = 686, SystemZ_CHI = 687, SystemZ_CHLR = 688, SystemZ_CHRL = 689, SystemZ_CHSI = 690, SystemZ_CHY = 691, SystemZ_CIB = 692, SystemZ_CIBAsm = 693, SystemZ_CIBAsmE = 694, SystemZ_CIBAsmH = 695, SystemZ_CIBAsmHE = 696, SystemZ_CIBAsmL = 697, SystemZ_CIBAsmLE = 698, SystemZ_CIBAsmLH = 699, SystemZ_CIBAsmNE = 700, SystemZ_CIBAsmNH = 701, SystemZ_CIBAsmNHE = 702, SystemZ_CIBAsmNL = 703, SystemZ_CIBAsmNLE = 704, SystemZ_CIBAsmNLH = 705, SystemZ_CIH = 706, SystemZ_CIJ = 707, SystemZ_CIJAsm = 708, SystemZ_CIJAsmE = 709, SystemZ_CIJAsmH = 710, SystemZ_CIJAsmHE = 711, SystemZ_CIJAsmL = 712, SystemZ_CIJAsmLE = 713, SystemZ_CIJAsmLH = 714, SystemZ_CIJAsmNE = 715, SystemZ_CIJAsmNH = 716, SystemZ_CIJAsmNHE = 717, SystemZ_CIJAsmNL = 718, SystemZ_CIJAsmNLE = 719, SystemZ_CIJAsmNLH = 720, SystemZ_CIT = 721, SystemZ_CITAsm = 722, SystemZ_CITAsmE = 723, SystemZ_CITAsmH = 724, SystemZ_CITAsmHE = 725, SystemZ_CITAsmL = 726, SystemZ_CITAsmLE = 727, SystemZ_CITAsmLH = 728, SystemZ_CITAsmNE = 729, SystemZ_CITAsmNH = 730, SystemZ_CITAsmNHE = 731, SystemZ_CITAsmNL = 732, SystemZ_CITAsmNLE = 733, SystemZ_CITAsmNLH = 734, SystemZ_CKSM = 735, SystemZ_CL = 736, SystemZ_CLC = 737, SystemZ_CLCL = 738, SystemZ_CLCLE = 739, SystemZ_CLCLU = 740, SystemZ_CLFDBR = 741, SystemZ_CLFDTR = 742, SystemZ_CLFEBR = 743, SystemZ_CLFHSI = 744, SystemZ_CLFI = 745, SystemZ_CLFIT = 746, SystemZ_CLFITAsm = 747, SystemZ_CLFITAsmE = 748, SystemZ_CLFITAsmH = 749, SystemZ_CLFITAsmHE = 750, SystemZ_CLFITAsmL = 751, SystemZ_CLFITAsmLE = 752, SystemZ_CLFITAsmLH = 753, SystemZ_CLFITAsmNE = 754, SystemZ_CLFITAsmNH = 755, SystemZ_CLFITAsmNHE = 756, SystemZ_CLFITAsmNL = 757, SystemZ_CLFITAsmNLE = 758, SystemZ_CLFITAsmNLH = 759, SystemZ_CLFXBR = 760, SystemZ_CLFXTR = 761, SystemZ_CLG = 762, SystemZ_CLGDBR = 763, SystemZ_CLGDTR = 764, SystemZ_CLGEBR = 765, SystemZ_CLGF = 766, SystemZ_CLGFI = 767, SystemZ_CLGFR = 768, SystemZ_CLGFRL = 769, SystemZ_CLGHRL = 770, SystemZ_CLGHSI = 771, SystemZ_CLGIB = 772, SystemZ_CLGIBAsm = 773, SystemZ_CLGIBAsmE = 774, SystemZ_CLGIBAsmH = 775, SystemZ_CLGIBAsmHE = 776, SystemZ_CLGIBAsmL = 777, SystemZ_CLGIBAsmLE = 778, SystemZ_CLGIBAsmLH = 779, SystemZ_CLGIBAsmNE = 780, SystemZ_CLGIBAsmNH = 781, SystemZ_CLGIBAsmNHE = 782, SystemZ_CLGIBAsmNL = 783, SystemZ_CLGIBAsmNLE = 784, SystemZ_CLGIBAsmNLH = 785, SystemZ_CLGIJ = 786, SystemZ_CLGIJAsm = 787, SystemZ_CLGIJAsmE = 788, SystemZ_CLGIJAsmH = 789, SystemZ_CLGIJAsmHE = 790, SystemZ_CLGIJAsmL = 791, SystemZ_CLGIJAsmLE = 792, SystemZ_CLGIJAsmLH = 793, SystemZ_CLGIJAsmNE = 794, SystemZ_CLGIJAsmNH = 795, SystemZ_CLGIJAsmNHE = 796, SystemZ_CLGIJAsmNL = 797, SystemZ_CLGIJAsmNLE = 798, SystemZ_CLGIJAsmNLH = 799, SystemZ_CLGIT = 800, SystemZ_CLGITAsm = 801, SystemZ_CLGITAsmE = 802, SystemZ_CLGITAsmH = 803, SystemZ_CLGITAsmHE = 804, SystemZ_CLGITAsmL = 805, SystemZ_CLGITAsmLE = 806, SystemZ_CLGITAsmLH = 807, SystemZ_CLGITAsmNE = 808, SystemZ_CLGITAsmNH = 809, SystemZ_CLGITAsmNHE = 810, SystemZ_CLGITAsmNL = 811, SystemZ_CLGITAsmNLE = 812, SystemZ_CLGITAsmNLH = 813, SystemZ_CLGR = 814, SystemZ_CLGRB = 815, SystemZ_CLGRBAsm = 816, SystemZ_CLGRBAsmE = 817, SystemZ_CLGRBAsmH = 818, SystemZ_CLGRBAsmHE = 819, SystemZ_CLGRBAsmL = 820, SystemZ_CLGRBAsmLE = 821, SystemZ_CLGRBAsmLH = 822, SystemZ_CLGRBAsmNE = 823, SystemZ_CLGRBAsmNH = 824, SystemZ_CLGRBAsmNHE = 825, SystemZ_CLGRBAsmNL = 826, SystemZ_CLGRBAsmNLE = 827, SystemZ_CLGRBAsmNLH = 828, SystemZ_CLGRJ = 829, SystemZ_CLGRJAsm = 830, SystemZ_CLGRJAsmE = 831, SystemZ_CLGRJAsmH = 832, SystemZ_CLGRJAsmHE = 833, SystemZ_CLGRJAsmL = 834, SystemZ_CLGRJAsmLE = 835, SystemZ_CLGRJAsmLH = 836, SystemZ_CLGRJAsmNE = 837, SystemZ_CLGRJAsmNH = 838, SystemZ_CLGRJAsmNHE = 839, SystemZ_CLGRJAsmNL = 840, SystemZ_CLGRJAsmNLE = 841, SystemZ_CLGRJAsmNLH = 842, SystemZ_CLGRL = 843, SystemZ_CLGRT = 844, SystemZ_CLGRTAsm = 845, SystemZ_CLGRTAsmE = 846, SystemZ_CLGRTAsmH = 847, SystemZ_CLGRTAsmHE = 848, SystemZ_CLGRTAsmL = 849, SystemZ_CLGRTAsmLE = 850, SystemZ_CLGRTAsmLH = 851, SystemZ_CLGRTAsmNE = 852, SystemZ_CLGRTAsmNH = 853, SystemZ_CLGRTAsmNHE = 854, SystemZ_CLGRTAsmNL = 855, SystemZ_CLGRTAsmNLE = 856, SystemZ_CLGRTAsmNLH = 857, SystemZ_CLGT = 858, SystemZ_CLGTAsm = 859, SystemZ_CLGTAsmE = 860, SystemZ_CLGTAsmH = 861, SystemZ_CLGTAsmHE = 862, SystemZ_CLGTAsmL = 863, SystemZ_CLGTAsmLE = 864, SystemZ_CLGTAsmLH = 865, SystemZ_CLGTAsmNE = 866, SystemZ_CLGTAsmNH = 867, SystemZ_CLGTAsmNHE = 868, SystemZ_CLGTAsmNL = 869, SystemZ_CLGTAsmNLE = 870, SystemZ_CLGTAsmNLH = 871, SystemZ_CLGXBR = 872, SystemZ_CLGXTR = 873, SystemZ_CLHF = 874, SystemZ_CLHHR = 875, SystemZ_CLHHSI = 876, SystemZ_CLHLR = 877, SystemZ_CLHRL = 878, SystemZ_CLI = 879, SystemZ_CLIB = 880, SystemZ_CLIBAsm = 881, SystemZ_CLIBAsmE = 882, SystemZ_CLIBAsmH = 883, SystemZ_CLIBAsmHE = 884, SystemZ_CLIBAsmL = 885, SystemZ_CLIBAsmLE = 886, SystemZ_CLIBAsmLH = 887, SystemZ_CLIBAsmNE = 888, SystemZ_CLIBAsmNH = 889, SystemZ_CLIBAsmNHE = 890, SystemZ_CLIBAsmNL = 891, SystemZ_CLIBAsmNLE = 892, SystemZ_CLIBAsmNLH = 893, SystemZ_CLIH = 894, SystemZ_CLIJ = 895, SystemZ_CLIJAsm = 896, SystemZ_CLIJAsmE = 897, SystemZ_CLIJAsmH = 898, SystemZ_CLIJAsmHE = 899, SystemZ_CLIJAsmL = 900, SystemZ_CLIJAsmLE = 901, SystemZ_CLIJAsmLH = 902, SystemZ_CLIJAsmNE = 903, SystemZ_CLIJAsmNH = 904, SystemZ_CLIJAsmNHE = 905, SystemZ_CLIJAsmNL = 906, SystemZ_CLIJAsmNLE = 907, SystemZ_CLIJAsmNLH = 908, SystemZ_CLIY = 909, SystemZ_CLM = 910, SystemZ_CLMH = 911, SystemZ_CLMY = 912, SystemZ_CLR = 913, SystemZ_CLRB = 914, SystemZ_CLRBAsm = 915, SystemZ_CLRBAsmE = 916, SystemZ_CLRBAsmH = 917, SystemZ_CLRBAsmHE = 918, SystemZ_CLRBAsmL = 919, SystemZ_CLRBAsmLE = 920, SystemZ_CLRBAsmLH = 921, SystemZ_CLRBAsmNE = 922, SystemZ_CLRBAsmNH = 923, SystemZ_CLRBAsmNHE = 924, SystemZ_CLRBAsmNL = 925, SystemZ_CLRBAsmNLE = 926, SystemZ_CLRBAsmNLH = 927, SystemZ_CLRJ = 928, SystemZ_CLRJAsm = 929, SystemZ_CLRJAsmE = 930, SystemZ_CLRJAsmH = 931, SystemZ_CLRJAsmHE = 932, SystemZ_CLRJAsmL = 933, SystemZ_CLRJAsmLE = 934, SystemZ_CLRJAsmLH = 935, SystemZ_CLRJAsmNE = 936, SystemZ_CLRJAsmNH = 937, SystemZ_CLRJAsmNHE = 938, SystemZ_CLRJAsmNL = 939, SystemZ_CLRJAsmNLE = 940, SystemZ_CLRJAsmNLH = 941, SystemZ_CLRL = 942, SystemZ_CLRT = 943, SystemZ_CLRTAsm = 944, SystemZ_CLRTAsmE = 945, SystemZ_CLRTAsmH = 946, SystemZ_CLRTAsmHE = 947, SystemZ_CLRTAsmL = 948, SystemZ_CLRTAsmLE = 949, SystemZ_CLRTAsmLH = 950, SystemZ_CLRTAsmNE = 951, SystemZ_CLRTAsmNH = 952, SystemZ_CLRTAsmNHE = 953, SystemZ_CLRTAsmNL = 954, SystemZ_CLRTAsmNLE = 955, SystemZ_CLRTAsmNLH = 956, SystemZ_CLST = 957, SystemZ_CLT = 958, SystemZ_CLTAsm = 959, SystemZ_CLTAsmE = 960, SystemZ_CLTAsmH = 961, SystemZ_CLTAsmHE = 962, SystemZ_CLTAsmL = 963, SystemZ_CLTAsmLE = 964, SystemZ_CLTAsmLH = 965, SystemZ_CLTAsmNE = 966, SystemZ_CLTAsmNH = 967, SystemZ_CLTAsmNHE = 968, SystemZ_CLTAsmNL = 969, SystemZ_CLTAsmNLE = 970, SystemZ_CLTAsmNLH = 971, SystemZ_CLY = 972, SystemZ_CMPSC = 973, SystemZ_CP = 974, SystemZ_CPDT = 975, SystemZ_CPSDRdd = 976, SystemZ_CPSDRds = 977, SystemZ_CPSDRsd = 978, SystemZ_CPSDRss = 979, SystemZ_CPXT = 980, SystemZ_CPYA = 981, SystemZ_CR = 982, SystemZ_CRB = 983, SystemZ_CRBAsm = 984, SystemZ_CRBAsmE = 985, SystemZ_CRBAsmH = 986, SystemZ_CRBAsmHE = 987, SystemZ_CRBAsmL = 988, SystemZ_CRBAsmLE = 989, SystemZ_CRBAsmLH = 990, SystemZ_CRBAsmNE = 991, SystemZ_CRBAsmNH = 992, SystemZ_CRBAsmNHE = 993, SystemZ_CRBAsmNL = 994, SystemZ_CRBAsmNLE = 995, SystemZ_CRBAsmNLH = 996, SystemZ_CRDTE = 997, SystemZ_CRDTEOpt = 998, SystemZ_CRJ = 999, SystemZ_CRJAsm = 1000, SystemZ_CRJAsmE = 1001, SystemZ_CRJAsmH = 1002, SystemZ_CRJAsmHE = 1003, SystemZ_CRJAsmL = 1004, SystemZ_CRJAsmLE = 1005, SystemZ_CRJAsmLH = 1006, SystemZ_CRJAsmNE = 1007, SystemZ_CRJAsmNH = 1008, SystemZ_CRJAsmNHE = 1009, SystemZ_CRJAsmNL = 1010, SystemZ_CRJAsmNLE = 1011, SystemZ_CRJAsmNLH = 1012, SystemZ_CRL = 1013, SystemZ_CRT = 1014, SystemZ_CRTAsm = 1015, SystemZ_CRTAsmE = 1016, SystemZ_CRTAsmH = 1017, SystemZ_CRTAsmHE = 1018, SystemZ_CRTAsmL = 1019, SystemZ_CRTAsmLE = 1020, SystemZ_CRTAsmLH = 1021, SystemZ_CRTAsmNE = 1022, SystemZ_CRTAsmNH = 1023, SystemZ_CRTAsmNHE = 1024, SystemZ_CRTAsmNL = 1025, SystemZ_CRTAsmNLE = 1026, SystemZ_CRTAsmNLH = 1027, SystemZ_CS = 1028, SystemZ_CSCH = 1029, SystemZ_CSDTR = 1030, SystemZ_CSG = 1031, SystemZ_CSP = 1032, SystemZ_CSPG = 1033, SystemZ_CSST = 1034, SystemZ_CSXTR = 1035, SystemZ_CSY = 1036, SystemZ_CU12 = 1037, SystemZ_CU12Opt = 1038, SystemZ_CU14 = 1039, SystemZ_CU14Opt = 1040, SystemZ_CU21 = 1041, SystemZ_CU21Opt = 1042, SystemZ_CU24 = 1043, SystemZ_CU24Opt = 1044, SystemZ_CU41 = 1045, SystemZ_CU42 = 1046, SystemZ_CUDTR = 1047, SystemZ_CUSE = 1048, SystemZ_CUTFU = 1049, SystemZ_CUTFUOpt = 1050, SystemZ_CUUTF = 1051, SystemZ_CUUTFOpt = 1052, SystemZ_CUXTR = 1053, SystemZ_CVB = 1054, SystemZ_CVBG = 1055, SystemZ_CVBY = 1056, SystemZ_CVD = 1057, SystemZ_CVDG = 1058, SystemZ_CVDY = 1059, SystemZ_CXBR = 1060, SystemZ_CXFBR = 1061, SystemZ_CXFBRA = 1062, SystemZ_CXFR = 1063, SystemZ_CXFTR = 1064, SystemZ_CXGBR = 1065, SystemZ_CXGBRA = 1066, SystemZ_CXGR = 1067, SystemZ_CXGTR = 1068, SystemZ_CXGTRA = 1069, SystemZ_CXLFBR = 1070, SystemZ_CXLFTR = 1071, SystemZ_CXLGBR = 1072, SystemZ_CXLGTR = 1073, SystemZ_CXPT = 1074, SystemZ_CXR = 1075, SystemZ_CXSTR = 1076, SystemZ_CXTR = 1077, SystemZ_CXUTR = 1078, SystemZ_CXZT = 1079, SystemZ_CY = 1080, SystemZ_CZDT = 1081, SystemZ_CZXT = 1082, SystemZ_D = 1083, SystemZ_DD = 1084, SystemZ_DDB = 1085, SystemZ_DDBR = 1086, SystemZ_DDR = 1087, SystemZ_DDTR = 1088, SystemZ_DDTRA = 1089, SystemZ_DE = 1090, SystemZ_DEB = 1091, SystemZ_DEBR = 1092, SystemZ_DER = 1093, SystemZ_DIAG = 1094, SystemZ_DIDBR = 1095, SystemZ_DIEBR = 1096, SystemZ_DL = 1097, SystemZ_DLG = 1098, SystemZ_DLGR = 1099, SystemZ_DLR = 1100, SystemZ_DP = 1101, SystemZ_DR = 1102, SystemZ_DSG = 1103, SystemZ_DSGF = 1104, SystemZ_DSGFR = 1105, SystemZ_DSGR = 1106, SystemZ_DXBR = 1107, SystemZ_DXR = 1108, SystemZ_DXTR = 1109, SystemZ_DXTRA = 1110, SystemZ_EAR = 1111, SystemZ_ECAG = 1112, SystemZ_ECCTR = 1113, SystemZ_ECPGA = 1114, SystemZ_ECTG = 1115, SystemZ_ED = 1116, SystemZ_EDMK = 1117, SystemZ_EEDTR = 1118, SystemZ_EEXTR = 1119, SystemZ_EFPC = 1120, SystemZ_EPAIR = 1121, SystemZ_EPAR = 1122, SystemZ_EPCTR = 1123, SystemZ_EPSW = 1124, SystemZ_EREG = 1125, SystemZ_EREGG = 1126, SystemZ_ESAIR = 1127, SystemZ_ESAR = 1128, SystemZ_ESDTR = 1129, SystemZ_ESEA = 1130, SystemZ_ESTA = 1131, SystemZ_ESXTR = 1132, SystemZ_ETND = 1133, SystemZ_EX = 1134, SystemZ_EXRL = 1135, SystemZ_FIDBR = 1136, SystemZ_FIDBRA = 1137, SystemZ_FIDR = 1138, SystemZ_FIDTR = 1139, SystemZ_FIEBR = 1140, SystemZ_FIEBRA = 1141, SystemZ_FIER = 1142, SystemZ_FIXBR = 1143, SystemZ_FIXBRA = 1144, SystemZ_FIXR = 1145, SystemZ_FIXTR = 1146, SystemZ_FLOGR = 1147, SystemZ_HDR = 1148, SystemZ_HER = 1149, SystemZ_HSCH = 1150, SystemZ_IAC = 1151, SystemZ_IC = 1152, SystemZ_IC32 = 1153, SystemZ_IC32Y = 1154, SystemZ_ICM = 1155, SystemZ_ICMH = 1156, SystemZ_ICMY = 1157, SystemZ_ICY = 1158, SystemZ_IDTE = 1159, SystemZ_IDTEOpt = 1160, SystemZ_IEDTR = 1161, SystemZ_IEXTR = 1162, SystemZ_IIHF = 1163, SystemZ_IIHH = 1164, SystemZ_IIHL = 1165, SystemZ_IILF = 1166, SystemZ_IILH = 1167, SystemZ_IILL = 1168, SystemZ_IPK = 1169, SystemZ_IPM = 1170, SystemZ_IPTE = 1171, SystemZ_IPTEOpt = 1172, SystemZ_IPTEOptOpt = 1173, SystemZ_IRBM = 1174, SystemZ_ISKE = 1175, SystemZ_IVSK = 1176, SystemZ_InsnE = 1177, SystemZ_InsnRI = 1178, SystemZ_InsnRIE = 1179, SystemZ_InsnRIL = 1180, SystemZ_InsnRILU = 1181, SystemZ_InsnRIS = 1182, SystemZ_InsnRR = 1183, SystemZ_InsnRRE = 1184, SystemZ_InsnRRF = 1185, SystemZ_InsnRRS = 1186, SystemZ_InsnRS = 1187, SystemZ_InsnRSE = 1188, SystemZ_InsnRSI = 1189, SystemZ_InsnRSY = 1190, SystemZ_InsnRX = 1191, SystemZ_InsnRXE = 1192, SystemZ_InsnRXF = 1193, SystemZ_InsnRXY = 1194, SystemZ_InsnS = 1195, SystemZ_InsnSI = 1196, SystemZ_InsnSIL = 1197, SystemZ_InsnSIY = 1198, SystemZ_InsnSS = 1199, SystemZ_InsnSSE = 1200, SystemZ_InsnSSF = 1201, SystemZ_J = 1202, SystemZ_JAsmE = 1203, SystemZ_JAsmH = 1204, SystemZ_JAsmHE = 1205, SystemZ_JAsmL = 1206, SystemZ_JAsmLE = 1207, SystemZ_JAsmLH = 1208, SystemZ_JAsmM = 1209, SystemZ_JAsmNE = 1210, SystemZ_JAsmNH = 1211, SystemZ_JAsmNHE = 1212, SystemZ_JAsmNL = 1213, SystemZ_JAsmNLE = 1214, SystemZ_JAsmNLH = 1215, SystemZ_JAsmNM = 1216, SystemZ_JAsmNO = 1217, SystemZ_JAsmNP = 1218, SystemZ_JAsmNZ = 1219, SystemZ_JAsmO = 1220, SystemZ_JAsmP = 1221, SystemZ_JAsmZ = 1222, SystemZ_JG = 1223, SystemZ_JGAsmE = 1224, SystemZ_JGAsmH = 1225, SystemZ_JGAsmHE = 1226, SystemZ_JGAsmL = 1227, SystemZ_JGAsmLE = 1228, SystemZ_JGAsmLH = 1229, SystemZ_JGAsmM = 1230, SystemZ_JGAsmNE = 1231, SystemZ_JGAsmNH = 1232, SystemZ_JGAsmNHE = 1233, SystemZ_JGAsmNL = 1234, SystemZ_JGAsmNLE = 1235, SystemZ_JGAsmNLH = 1236, SystemZ_JGAsmNM = 1237, SystemZ_JGAsmNO = 1238, SystemZ_JGAsmNP = 1239, SystemZ_JGAsmNZ = 1240, SystemZ_JGAsmO = 1241, SystemZ_JGAsmP = 1242, SystemZ_JGAsmZ = 1243, SystemZ_KDB = 1244, SystemZ_KDBR = 1245, SystemZ_KDTR = 1246, SystemZ_KEB = 1247, SystemZ_KEBR = 1248, SystemZ_KIMD = 1249, SystemZ_KLMD = 1250, SystemZ_KM = 1251, SystemZ_KMA = 1252, SystemZ_KMAC = 1253, SystemZ_KMC = 1254, SystemZ_KMCTR = 1255, SystemZ_KMF = 1256, SystemZ_KMO = 1257, SystemZ_KXBR = 1258, SystemZ_KXTR = 1259, SystemZ_L = 1260, SystemZ_LA = 1261, SystemZ_LAA = 1262, SystemZ_LAAG = 1263, SystemZ_LAAL = 1264, SystemZ_LAALG = 1265, SystemZ_LAE = 1266, SystemZ_LAEY = 1267, SystemZ_LAM = 1268, SystemZ_LAMY = 1269, SystemZ_LAN = 1270, SystemZ_LANG = 1271, SystemZ_LAO = 1272, SystemZ_LAOG = 1273, SystemZ_LARL = 1274, SystemZ_LASP = 1275, SystemZ_LAT = 1276, SystemZ_LAX = 1277, SystemZ_LAXG = 1278, SystemZ_LAY = 1279, SystemZ_LB = 1280, SystemZ_LBH = 1281, SystemZ_LBR = 1282, SystemZ_LCBB = 1283, SystemZ_LCCTL = 1284, SystemZ_LCDBR = 1285, SystemZ_LCDFR = 1286, SystemZ_LCDFR_32 = 1287, SystemZ_LCDR = 1288, SystemZ_LCEBR = 1289, SystemZ_LCER = 1290, SystemZ_LCGFR = 1291, SystemZ_LCGR = 1292, SystemZ_LCR = 1293, SystemZ_LCTL = 1294, SystemZ_LCTLG = 1295, SystemZ_LCXBR = 1296, SystemZ_LCXR = 1297, SystemZ_LD = 1298, SystemZ_LDE = 1299, SystemZ_LDE32 = 1300, SystemZ_LDEB = 1301, SystemZ_LDEBR = 1302, SystemZ_LDER = 1303, SystemZ_LDETR = 1304, SystemZ_LDGR = 1305, SystemZ_LDR = 1306, SystemZ_LDR32 = 1307, SystemZ_LDXBR = 1308, SystemZ_LDXBRA = 1309, SystemZ_LDXR = 1310, SystemZ_LDXTR = 1311, SystemZ_LDY = 1312, SystemZ_LE = 1313, SystemZ_LEDBR = 1314, SystemZ_LEDBRA = 1315, SystemZ_LEDR = 1316, SystemZ_LEDTR = 1317, SystemZ_LER = 1318, SystemZ_LEXBR = 1319, SystemZ_LEXBRA = 1320, SystemZ_LEXR = 1321, SystemZ_LEY = 1322, SystemZ_LFAS = 1323, SystemZ_LFH = 1324, SystemZ_LFHAT = 1325, SystemZ_LFPC = 1326, SystemZ_LG = 1327, SystemZ_LGAT = 1328, SystemZ_LGB = 1329, SystemZ_LGBR = 1330, SystemZ_LGDR = 1331, SystemZ_LGF = 1332, SystemZ_LGFI = 1333, SystemZ_LGFR = 1334, SystemZ_LGFRL = 1335, SystemZ_LGG = 1336, SystemZ_LGH = 1337, SystemZ_LGHI = 1338, SystemZ_LGHR = 1339, SystemZ_LGHRL = 1340, SystemZ_LGR = 1341, SystemZ_LGRL = 1342, SystemZ_LGSC = 1343, SystemZ_LH = 1344, SystemZ_LHH = 1345, SystemZ_LHI = 1346, SystemZ_LHR = 1347, SystemZ_LHRL = 1348, SystemZ_LHY = 1349, SystemZ_LLC = 1350, SystemZ_LLCH = 1351, SystemZ_LLCR = 1352, SystemZ_LLGC = 1353, SystemZ_LLGCR = 1354, SystemZ_LLGF = 1355, SystemZ_LLGFAT = 1356, SystemZ_LLGFR = 1357, SystemZ_LLGFRL = 1358, SystemZ_LLGFSG = 1359, SystemZ_LLGH = 1360, SystemZ_LLGHR = 1361, SystemZ_LLGHRL = 1362, SystemZ_LLGT = 1363, SystemZ_LLGTAT = 1364, SystemZ_LLGTR = 1365, SystemZ_LLH = 1366, SystemZ_LLHH = 1367, SystemZ_LLHR = 1368, SystemZ_LLHRL = 1369, SystemZ_LLIHF = 1370, SystemZ_LLIHH = 1371, SystemZ_LLIHL = 1372, SystemZ_LLILF = 1373, SystemZ_LLILH = 1374, SystemZ_LLILL = 1375, SystemZ_LLZRGF = 1376, SystemZ_LM = 1377, SystemZ_LMD = 1378, SystemZ_LMG = 1379, SystemZ_LMH = 1380, SystemZ_LMY = 1381, SystemZ_LNDBR = 1382, SystemZ_LNDFR = 1383, SystemZ_LNDFR_32 = 1384, SystemZ_LNDR = 1385, SystemZ_LNEBR = 1386, SystemZ_LNER = 1387, SystemZ_LNGFR = 1388, SystemZ_LNGR = 1389, SystemZ_LNR = 1390, SystemZ_LNXBR = 1391, SystemZ_LNXR = 1392, SystemZ_LOC = 1393, SystemZ_LOCAsm = 1394, SystemZ_LOCAsmE = 1395, SystemZ_LOCAsmH = 1396, SystemZ_LOCAsmHE = 1397, SystemZ_LOCAsmL = 1398, SystemZ_LOCAsmLE = 1399, SystemZ_LOCAsmLH = 1400, SystemZ_LOCAsmM = 1401, SystemZ_LOCAsmNE = 1402, SystemZ_LOCAsmNH = 1403, SystemZ_LOCAsmNHE = 1404, SystemZ_LOCAsmNL = 1405, SystemZ_LOCAsmNLE = 1406, SystemZ_LOCAsmNLH = 1407, SystemZ_LOCAsmNM = 1408, SystemZ_LOCAsmNO = 1409, SystemZ_LOCAsmNP = 1410, SystemZ_LOCAsmNZ = 1411, SystemZ_LOCAsmO = 1412, SystemZ_LOCAsmP = 1413, SystemZ_LOCAsmZ = 1414, SystemZ_LOCFH = 1415, SystemZ_LOCFHAsm = 1416, SystemZ_LOCFHAsmE = 1417, SystemZ_LOCFHAsmH = 1418, SystemZ_LOCFHAsmHE = 1419, SystemZ_LOCFHAsmL = 1420, SystemZ_LOCFHAsmLE = 1421, SystemZ_LOCFHAsmLH = 1422, SystemZ_LOCFHAsmM = 1423, SystemZ_LOCFHAsmNE = 1424, SystemZ_LOCFHAsmNH = 1425, SystemZ_LOCFHAsmNHE = 1426, SystemZ_LOCFHAsmNL = 1427, SystemZ_LOCFHAsmNLE = 1428, SystemZ_LOCFHAsmNLH = 1429, SystemZ_LOCFHAsmNM = 1430, SystemZ_LOCFHAsmNO = 1431, SystemZ_LOCFHAsmNP = 1432, SystemZ_LOCFHAsmNZ = 1433, SystemZ_LOCFHAsmO = 1434, SystemZ_LOCFHAsmP = 1435, SystemZ_LOCFHAsmZ = 1436, SystemZ_LOCFHR = 1437, SystemZ_LOCFHRAsm = 1438, SystemZ_LOCFHRAsmE = 1439, SystemZ_LOCFHRAsmH = 1440, SystemZ_LOCFHRAsmHE = 1441, SystemZ_LOCFHRAsmL = 1442, SystemZ_LOCFHRAsmLE = 1443, SystemZ_LOCFHRAsmLH = 1444, SystemZ_LOCFHRAsmM = 1445, SystemZ_LOCFHRAsmNE = 1446, SystemZ_LOCFHRAsmNH = 1447, SystemZ_LOCFHRAsmNHE = 1448, SystemZ_LOCFHRAsmNL = 1449, SystemZ_LOCFHRAsmNLE = 1450, SystemZ_LOCFHRAsmNLH = 1451, SystemZ_LOCFHRAsmNM = 1452, SystemZ_LOCFHRAsmNO = 1453, SystemZ_LOCFHRAsmNP = 1454, SystemZ_LOCFHRAsmNZ = 1455, SystemZ_LOCFHRAsmO = 1456, SystemZ_LOCFHRAsmP = 1457, SystemZ_LOCFHRAsmZ = 1458, SystemZ_LOCG = 1459, SystemZ_LOCGAsm = 1460, SystemZ_LOCGAsmE = 1461, SystemZ_LOCGAsmH = 1462, SystemZ_LOCGAsmHE = 1463, SystemZ_LOCGAsmL = 1464, SystemZ_LOCGAsmLE = 1465, SystemZ_LOCGAsmLH = 1466, SystemZ_LOCGAsmM = 1467, SystemZ_LOCGAsmNE = 1468, SystemZ_LOCGAsmNH = 1469, SystemZ_LOCGAsmNHE = 1470, SystemZ_LOCGAsmNL = 1471, SystemZ_LOCGAsmNLE = 1472, SystemZ_LOCGAsmNLH = 1473, SystemZ_LOCGAsmNM = 1474, SystemZ_LOCGAsmNO = 1475, SystemZ_LOCGAsmNP = 1476, SystemZ_LOCGAsmNZ = 1477, SystemZ_LOCGAsmO = 1478, SystemZ_LOCGAsmP = 1479, SystemZ_LOCGAsmZ = 1480, SystemZ_LOCGHI = 1481, SystemZ_LOCGHIAsm = 1482, SystemZ_LOCGHIAsmE = 1483, SystemZ_LOCGHIAsmH = 1484, SystemZ_LOCGHIAsmHE = 1485, SystemZ_LOCGHIAsmL = 1486, SystemZ_LOCGHIAsmLE = 1487, SystemZ_LOCGHIAsmLH = 1488, SystemZ_LOCGHIAsmM = 1489, SystemZ_LOCGHIAsmNE = 1490, SystemZ_LOCGHIAsmNH = 1491, SystemZ_LOCGHIAsmNHE = 1492, SystemZ_LOCGHIAsmNL = 1493, SystemZ_LOCGHIAsmNLE = 1494, SystemZ_LOCGHIAsmNLH = 1495, SystemZ_LOCGHIAsmNM = 1496, SystemZ_LOCGHIAsmNO = 1497, SystemZ_LOCGHIAsmNP = 1498, SystemZ_LOCGHIAsmNZ = 1499, SystemZ_LOCGHIAsmO = 1500, SystemZ_LOCGHIAsmP = 1501, SystemZ_LOCGHIAsmZ = 1502, SystemZ_LOCGR = 1503, SystemZ_LOCGRAsm = 1504, SystemZ_LOCGRAsmE = 1505, SystemZ_LOCGRAsmH = 1506, SystemZ_LOCGRAsmHE = 1507, SystemZ_LOCGRAsmL = 1508, SystemZ_LOCGRAsmLE = 1509, SystemZ_LOCGRAsmLH = 1510, SystemZ_LOCGRAsmM = 1511, SystemZ_LOCGRAsmNE = 1512, SystemZ_LOCGRAsmNH = 1513, SystemZ_LOCGRAsmNHE = 1514, SystemZ_LOCGRAsmNL = 1515, SystemZ_LOCGRAsmNLE = 1516, SystemZ_LOCGRAsmNLH = 1517, SystemZ_LOCGRAsmNM = 1518, SystemZ_LOCGRAsmNO = 1519, SystemZ_LOCGRAsmNP = 1520, SystemZ_LOCGRAsmNZ = 1521, SystemZ_LOCGRAsmO = 1522, SystemZ_LOCGRAsmP = 1523, SystemZ_LOCGRAsmZ = 1524, SystemZ_LOCHHI = 1525, SystemZ_LOCHHIAsm = 1526, SystemZ_LOCHHIAsmE = 1527, SystemZ_LOCHHIAsmH = 1528, SystemZ_LOCHHIAsmHE = 1529, SystemZ_LOCHHIAsmL = 1530, SystemZ_LOCHHIAsmLE = 1531, SystemZ_LOCHHIAsmLH = 1532, SystemZ_LOCHHIAsmM = 1533, SystemZ_LOCHHIAsmNE = 1534, SystemZ_LOCHHIAsmNH = 1535, SystemZ_LOCHHIAsmNHE = 1536, SystemZ_LOCHHIAsmNL = 1537, SystemZ_LOCHHIAsmNLE = 1538, SystemZ_LOCHHIAsmNLH = 1539, SystemZ_LOCHHIAsmNM = 1540, SystemZ_LOCHHIAsmNO = 1541, SystemZ_LOCHHIAsmNP = 1542, SystemZ_LOCHHIAsmNZ = 1543, SystemZ_LOCHHIAsmO = 1544, SystemZ_LOCHHIAsmP = 1545, SystemZ_LOCHHIAsmZ = 1546, SystemZ_LOCHI = 1547, SystemZ_LOCHIAsm = 1548, SystemZ_LOCHIAsmE = 1549, SystemZ_LOCHIAsmH = 1550, SystemZ_LOCHIAsmHE = 1551, SystemZ_LOCHIAsmL = 1552, SystemZ_LOCHIAsmLE = 1553, SystemZ_LOCHIAsmLH = 1554, SystemZ_LOCHIAsmM = 1555, SystemZ_LOCHIAsmNE = 1556, SystemZ_LOCHIAsmNH = 1557, SystemZ_LOCHIAsmNHE = 1558, SystemZ_LOCHIAsmNL = 1559, SystemZ_LOCHIAsmNLE = 1560, SystemZ_LOCHIAsmNLH = 1561, SystemZ_LOCHIAsmNM = 1562, SystemZ_LOCHIAsmNO = 1563, SystemZ_LOCHIAsmNP = 1564, SystemZ_LOCHIAsmNZ = 1565, SystemZ_LOCHIAsmO = 1566, SystemZ_LOCHIAsmP = 1567, SystemZ_LOCHIAsmZ = 1568, SystemZ_LOCR = 1569, SystemZ_LOCRAsm = 1570, SystemZ_LOCRAsmE = 1571, SystemZ_LOCRAsmH = 1572, SystemZ_LOCRAsmHE = 1573, SystemZ_LOCRAsmL = 1574, SystemZ_LOCRAsmLE = 1575, SystemZ_LOCRAsmLH = 1576, SystemZ_LOCRAsmM = 1577, SystemZ_LOCRAsmNE = 1578, SystemZ_LOCRAsmNH = 1579, SystemZ_LOCRAsmNHE = 1580, SystemZ_LOCRAsmNL = 1581, SystemZ_LOCRAsmNLE = 1582, SystemZ_LOCRAsmNLH = 1583, SystemZ_LOCRAsmNM = 1584, SystemZ_LOCRAsmNO = 1585, SystemZ_LOCRAsmNP = 1586, SystemZ_LOCRAsmNZ = 1587, SystemZ_LOCRAsmO = 1588, SystemZ_LOCRAsmP = 1589, SystemZ_LOCRAsmZ = 1590, SystemZ_LPCTL = 1591, SystemZ_LPD = 1592, SystemZ_LPDBR = 1593, SystemZ_LPDFR = 1594, SystemZ_LPDFR_32 = 1595, SystemZ_LPDG = 1596, SystemZ_LPDR = 1597, SystemZ_LPEBR = 1598, SystemZ_LPER = 1599, SystemZ_LPGFR = 1600, SystemZ_LPGR = 1601, SystemZ_LPP = 1602, SystemZ_LPQ = 1603, SystemZ_LPR = 1604, SystemZ_LPSW = 1605, SystemZ_LPSWE = 1606, SystemZ_LPTEA = 1607, SystemZ_LPXBR = 1608, SystemZ_LPXR = 1609, SystemZ_LR = 1610, SystemZ_LRA = 1611, SystemZ_LRAG = 1612, SystemZ_LRAY = 1613, SystemZ_LRDR = 1614, SystemZ_LRER = 1615, SystemZ_LRL = 1616, SystemZ_LRV = 1617, SystemZ_LRVG = 1618, SystemZ_LRVGR = 1619, SystemZ_LRVH = 1620, SystemZ_LRVR = 1621, SystemZ_LSCTL = 1622, SystemZ_LT = 1623, SystemZ_LTDBR = 1624, SystemZ_LTDBRCompare = 1625, SystemZ_LTDR = 1626, SystemZ_LTDTR = 1627, SystemZ_LTEBR = 1628, SystemZ_LTEBRCompare = 1629, SystemZ_LTER = 1630, SystemZ_LTG = 1631, SystemZ_LTGF = 1632, SystemZ_LTGFR = 1633, SystemZ_LTGR = 1634, SystemZ_LTR = 1635, SystemZ_LTXBR = 1636, SystemZ_LTXBRCompare = 1637, SystemZ_LTXR = 1638, SystemZ_LTXTR = 1639, SystemZ_LURA = 1640, SystemZ_LURAG = 1641, SystemZ_LXD = 1642, SystemZ_LXDB = 1643, SystemZ_LXDBR = 1644, SystemZ_LXDR = 1645, SystemZ_LXDTR = 1646, SystemZ_LXE = 1647, SystemZ_LXEB = 1648, SystemZ_LXEBR = 1649, SystemZ_LXER = 1650, SystemZ_LXR = 1651, SystemZ_LY = 1652, SystemZ_LZDR = 1653, SystemZ_LZER = 1654, SystemZ_LZRF = 1655, SystemZ_LZRG = 1656, SystemZ_LZXR = 1657, SystemZ_M = 1658, SystemZ_MAD = 1659, SystemZ_MADB = 1660, SystemZ_MADBR = 1661, SystemZ_MADR = 1662, SystemZ_MAE = 1663, SystemZ_MAEB = 1664, SystemZ_MAEBR = 1665, SystemZ_MAER = 1666, SystemZ_MAY = 1667, SystemZ_MAYH = 1668, SystemZ_MAYHR = 1669, SystemZ_MAYL = 1670, SystemZ_MAYLR = 1671, SystemZ_MAYR = 1672, SystemZ_MC = 1673, SystemZ_MD = 1674, SystemZ_MDB = 1675, SystemZ_MDBR = 1676, SystemZ_MDE = 1677, SystemZ_MDEB = 1678, SystemZ_MDEBR = 1679, SystemZ_MDER = 1680, SystemZ_MDR = 1681, SystemZ_MDTR = 1682, SystemZ_MDTRA = 1683, SystemZ_ME = 1684, SystemZ_MEE = 1685, SystemZ_MEEB = 1686, SystemZ_MEEBR = 1687, SystemZ_MEER = 1688, SystemZ_MER = 1689, SystemZ_MFY = 1690, SystemZ_MG = 1691, SystemZ_MGH = 1692, SystemZ_MGHI = 1693, SystemZ_MGRK = 1694, SystemZ_MH = 1695, SystemZ_MHI = 1696, SystemZ_MHY = 1697, SystemZ_ML = 1698, SystemZ_MLG = 1699, SystemZ_MLGR = 1700, SystemZ_MLR = 1701, SystemZ_MP = 1702, SystemZ_MR = 1703, SystemZ_MS = 1704, SystemZ_MSC = 1705, SystemZ_MSCH = 1706, SystemZ_MSD = 1707, SystemZ_MSDB = 1708, SystemZ_MSDBR = 1709, SystemZ_MSDR = 1710, SystemZ_MSE = 1711, SystemZ_MSEB = 1712, SystemZ_MSEBR = 1713, SystemZ_MSER = 1714, SystemZ_MSFI = 1715, SystemZ_MSG = 1716, SystemZ_MSGC = 1717, SystemZ_MSGF = 1718, SystemZ_MSGFI = 1719, SystemZ_MSGFR = 1720, SystemZ_MSGR = 1721, SystemZ_MSGRKC = 1722, SystemZ_MSR = 1723, SystemZ_MSRKC = 1724, SystemZ_MSTA = 1725, SystemZ_MSY = 1726, SystemZ_MVC = 1727, SystemZ_MVCDK = 1728, SystemZ_MVCIN = 1729, SystemZ_MVCK = 1730, SystemZ_MVCL = 1731, SystemZ_MVCLE = 1732, SystemZ_MVCLU = 1733, SystemZ_MVCOS = 1734, SystemZ_MVCP = 1735, SystemZ_MVCS = 1736, SystemZ_MVCSK = 1737, SystemZ_MVGHI = 1738, SystemZ_MVHHI = 1739, SystemZ_MVHI = 1740, SystemZ_MVI = 1741, SystemZ_MVIY = 1742, SystemZ_MVN = 1743, SystemZ_MVO = 1744, SystemZ_MVPG = 1745, SystemZ_MVST = 1746, SystemZ_MVZ = 1747, SystemZ_MXBR = 1748, SystemZ_MXD = 1749, SystemZ_MXDB = 1750, SystemZ_MXDBR = 1751, SystemZ_MXDR = 1752, SystemZ_MXR = 1753, SystemZ_MXTR = 1754, SystemZ_MXTRA = 1755, SystemZ_MY = 1756, SystemZ_MYH = 1757, SystemZ_MYHR = 1758, SystemZ_MYL = 1759, SystemZ_MYLR = 1760, SystemZ_MYR = 1761, SystemZ_N = 1762, SystemZ_NC = 1763, SystemZ_NG = 1764, SystemZ_NGR = 1765, SystemZ_NGRK = 1766, SystemZ_NI = 1767, SystemZ_NIAI = 1768, SystemZ_NIHF = 1769, SystemZ_NIHH = 1770, SystemZ_NIHL = 1771, SystemZ_NILF = 1772, SystemZ_NILH = 1773, SystemZ_NILL = 1774, SystemZ_NIY = 1775, SystemZ_NR = 1776, SystemZ_NRK = 1777, SystemZ_NTSTG = 1778, SystemZ_NY = 1779, SystemZ_O = 1780, SystemZ_OC = 1781, SystemZ_OG = 1782, SystemZ_OGR = 1783, SystemZ_OGRK = 1784, SystemZ_OI = 1785, SystemZ_OIHF = 1786, SystemZ_OIHH = 1787, SystemZ_OIHL = 1788, SystemZ_OILF = 1789, SystemZ_OILH = 1790, SystemZ_OILL = 1791, SystemZ_OIY = 1792, SystemZ_OR = 1793, SystemZ_ORK = 1794, SystemZ_OY = 1795, SystemZ_PACK = 1796, SystemZ_PALB = 1797, SystemZ_PC = 1798, SystemZ_PCC = 1799, SystemZ_PCKMO = 1800, SystemZ_PFD = 1801, SystemZ_PFDRL = 1802, SystemZ_PFMF = 1803, SystemZ_PFPO = 1804, SystemZ_PGIN = 1805, SystemZ_PGOUT = 1806, SystemZ_PKA = 1807, SystemZ_PKU = 1808, SystemZ_PLO = 1809, SystemZ_POPCNT = 1810, SystemZ_PPA = 1811, SystemZ_PPNO = 1812, SystemZ_PR = 1813, SystemZ_PRNO = 1814, SystemZ_PT = 1815, SystemZ_PTF = 1816, SystemZ_PTFF = 1817, SystemZ_PTI = 1818, SystemZ_PTLB = 1819, SystemZ_QADTR = 1820, SystemZ_QAXTR = 1821, SystemZ_QCTRI = 1822, SystemZ_QSI = 1823, SystemZ_RCHP = 1824, SystemZ_RISBG = 1825, SystemZ_RISBG32 = 1826, SystemZ_RISBGN = 1827, SystemZ_RISBHG = 1828, SystemZ_RISBLG = 1829, SystemZ_RLL = 1830, SystemZ_RLLG = 1831, SystemZ_RNSBG = 1832, SystemZ_ROSBG = 1833, SystemZ_RP = 1834, SystemZ_RRBE = 1835, SystemZ_RRBM = 1836, SystemZ_RRDTR = 1837, SystemZ_RRXTR = 1838, SystemZ_RSCH = 1839, SystemZ_RXSBG = 1840, SystemZ_S = 1841, SystemZ_SAC = 1842, SystemZ_SACF = 1843, SystemZ_SAL = 1844, SystemZ_SAM24 = 1845, SystemZ_SAM31 = 1846, SystemZ_SAM64 = 1847, SystemZ_SAR = 1848, SystemZ_SCCTR = 1849, SystemZ_SCHM = 1850, SystemZ_SCK = 1851, SystemZ_SCKC = 1852, SystemZ_SCKPF = 1853, SystemZ_SD = 1854, SystemZ_SDB = 1855, SystemZ_SDBR = 1856, SystemZ_SDR = 1857, SystemZ_SDTR = 1858, SystemZ_SDTRA = 1859, SystemZ_SE = 1860, SystemZ_SEB = 1861, SystemZ_SEBR = 1862, SystemZ_SER = 1863, SystemZ_SFASR = 1864, SystemZ_SFPC = 1865, SystemZ_SG = 1866, SystemZ_SGF = 1867, SystemZ_SGFR = 1868, SystemZ_SGH = 1869, SystemZ_SGR = 1870, SystemZ_SGRK = 1871, SystemZ_SH = 1872, SystemZ_SHHHR = 1873, SystemZ_SHHLR = 1874, SystemZ_SHY = 1875, SystemZ_SIE = 1876, SystemZ_SIGA = 1877, SystemZ_SIGP = 1878, SystemZ_SL = 1879, SystemZ_SLA = 1880, SystemZ_SLAG = 1881, SystemZ_SLAK = 1882, SystemZ_SLB = 1883, SystemZ_SLBG = 1884, SystemZ_SLBGR = 1885, SystemZ_SLBR = 1886, SystemZ_SLDA = 1887, SystemZ_SLDL = 1888, SystemZ_SLDT = 1889, SystemZ_SLFI = 1890, SystemZ_SLG = 1891, SystemZ_SLGF = 1892, SystemZ_SLGFI = 1893, SystemZ_SLGFR = 1894, SystemZ_SLGR = 1895, SystemZ_SLGRK = 1896, SystemZ_SLHHHR = 1897, SystemZ_SLHHLR = 1898, SystemZ_SLL = 1899, SystemZ_SLLG = 1900, SystemZ_SLLK = 1901, SystemZ_SLR = 1902, SystemZ_SLRK = 1903, SystemZ_SLXT = 1904, SystemZ_SLY = 1905, SystemZ_SP = 1906, SystemZ_SPCTR = 1907, SystemZ_SPKA = 1908, SystemZ_SPM = 1909, SystemZ_SPT = 1910, SystemZ_SPX = 1911, SystemZ_SQD = 1912, SystemZ_SQDB = 1913, SystemZ_SQDBR = 1914, SystemZ_SQDR = 1915, SystemZ_SQE = 1916, SystemZ_SQEB = 1917, SystemZ_SQEBR = 1918, SystemZ_SQER = 1919, SystemZ_SQXBR = 1920, SystemZ_SQXR = 1921, SystemZ_SR = 1922, SystemZ_SRA = 1923, SystemZ_SRAG = 1924, SystemZ_SRAK = 1925, SystemZ_SRDA = 1926, SystemZ_SRDL = 1927, SystemZ_SRDT = 1928, SystemZ_SRK = 1929, SystemZ_SRL = 1930, SystemZ_SRLG = 1931, SystemZ_SRLK = 1932, SystemZ_SRNM = 1933, SystemZ_SRNMB = 1934, SystemZ_SRNMT = 1935, SystemZ_SRP = 1936, SystemZ_SRST = 1937, SystemZ_SRSTU = 1938, SystemZ_SRXT = 1939, SystemZ_SSAIR = 1940, SystemZ_SSAR = 1941, SystemZ_SSCH = 1942, SystemZ_SSKE = 1943, SystemZ_SSKEOpt = 1944, SystemZ_SSM = 1945, SystemZ_ST = 1946, SystemZ_STAM = 1947, SystemZ_STAMY = 1948, SystemZ_STAP = 1949, SystemZ_STC = 1950, SystemZ_STCH = 1951, SystemZ_STCK = 1952, SystemZ_STCKC = 1953, SystemZ_STCKE = 1954, SystemZ_STCKF = 1955, SystemZ_STCM = 1956, SystemZ_STCMH = 1957, SystemZ_STCMY = 1958, SystemZ_STCPS = 1959, SystemZ_STCRW = 1960, SystemZ_STCTG = 1961, SystemZ_STCTL = 1962, SystemZ_STCY = 1963, SystemZ_STD = 1964, SystemZ_STDY = 1965, SystemZ_STE = 1966, SystemZ_STEY = 1967, SystemZ_STFH = 1968, SystemZ_STFL = 1969, SystemZ_STFLE = 1970, SystemZ_STFPC = 1971, SystemZ_STG = 1972, SystemZ_STGRL = 1973, SystemZ_STGSC = 1974, SystemZ_STH = 1975, SystemZ_STHH = 1976, SystemZ_STHRL = 1977, SystemZ_STHY = 1978, SystemZ_STIDP = 1979, SystemZ_STM = 1980, SystemZ_STMG = 1981, SystemZ_STMH = 1982, SystemZ_STMY = 1983, SystemZ_STNSM = 1984, SystemZ_STOC = 1985, SystemZ_STOCAsm = 1986, SystemZ_STOCAsmE = 1987, SystemZ_STOCAsmH = 1988, SystemZ_STOCAsmHE = 1989, SystemZ_STOCAsmL = 1990, SystemZ_STOCAsmLE = 1991, SystemZ_STOCAsmLH = 1992, SystemZ_STOCAsmM = 1993, SystemZ_STOCAsmNE = 1994, SystemZ_STOCAsmNH = 1995, SystemZ_STOCAsmNHE = 1996, SystemZ_STOCAsmNL = 1997, SystemZ_STOCAsmNLE = 1998, SystemZ_STOCAsmNLH = 1999, SystemZ_STOCAsmNM = 2000, SystemZ_STOCAsmNO = 2001, SystemZ_STOCAsmNP = 2002, SystemZ_STOCAsmNZ = 2003, SystemZ_STOCAsmO = 2004, SystemZ_STOCAsmP = 2005, SystemZ_STOCAsmZ = 2006, SystemZ_STOCFH = 2007, SystemZ_STOCFHAsm = 2008, SystemZ_STOCFHAsmE = 2009, SystemZ_STOCFHAsmH = 2010, SystemZ_STOCFHAsmHE = 2011, SystemZ_STOCFHAsmL = 2012, SystemZ_STOCFHAsmLE = 2013, SystemZ_STOCFHAsmLH = 2014, SystemZ_STOCFHAsmM = 2015, SystemZ_STOCFHAsmNE = 2016, SystemZ_STOCFHAsmNH = 2017, SystemZ_STOCFHAsmNHE = 2018, SystemZ_STOCFHAsmNL = 2019, SystemZ_STOCFHAsmNLE = 2020, SystemZ_STOCFHAsmNLH = 2021, SystemZ_STOCFHAsmNM = 2022, SystemZ_STOCFHAsmNO = 2023, SystemZ_STOCFHAsmNP = 2024, SystemZ_STOCFHAsmNZ = 2025, SystemZ_STOCFHAsmO = 2026, SystemZ_STOCFHAsmP = 2027, SystemZ_STOCFHAsmZ = 2028, SystemZ_STOCG = 2029, SystemZ_STOCGAsm = 2030, SystemZ_STOCGAsmE = 2031, SystemZ_STOCGAsmH = 2032, SystemZ_STOCGAsmHE = 2033, SystemZ_STOCGAsmL = 2034, SystemZ_STOCGAsmLE = 2035, SystemZ_STOCGAsmLH = 2036, SystemZ_STOCGAsmM = 2037, SystemZ_STOCGAsmNE = 2038, SystemZ_STOCGAsmNH = 2039, SystemZ_STOCGAsmNHE = 2040, SystemZ_STOCGAsmNL = 2041, SystemZ_STOCGAsmNLE = 2042, SystemZ_STOCGAsmNLH = 2043, SystemZ_STOCGAsmNM = 2044, SystemZ_STOCGAsmNO = 2045, SystemZ_STOCGAsmNP = 2046, SystemZ_STOCGAsmNZ = 2047, SystemZ_STOCGAsmO = 2048, SystemZ_STOCGAsmP = 2049, SystemZ_STOCGAsmZ = 2050, SystemZ_STOSM = 2051, SystemZ_STPQ = 2052, SystemZ_STPT = 2053, SystemZ_STPX = 2054, SystemZ_STRAG = 2055, SystemZ_STRL = 2056, SystemZ_STRV = 2057, SystemZ_STRVG = 2058, SystemZ_STRVH = 2059, SystemZ_STSCH = 2060, SystemZ_STSI = 2061, SystemZ_STURA = 2062, SystemZ_STURG = 2063, SystemZ_STY = 2064, SystemZ_SU = 2065, SystemZ_SUR = 2066, SystemZ_SVC = 2067, SystemZ_SW = 2068, SystemZ_SWR = 2069, SystemZ_SXBR = 2070, SystemZ_SXR = 2071, SystemZ_SXTR = 2072, SystemZ_SXTRA = 2073, SystemZ_SY = 2074, SystemZ_TABORT = 2075, SystemZ_TAM = 2076, SystemZ_TAR = 2077, SystemZ_TB = 2078, SystemZ_TBDR = 2079, SystemZ_TBEDR = 2080, SystemZ_TBEGIN = 2081, SystemZ_TBEGINC = 2082, SystemZ_TCDB = 2083, SystemZ_TCEB = 2084, SystemZ_TCXB = 2085, SystemZ_TDCDT = 2086, SystemZ_TDCET = 2087, SystemZ_TDCXT = 2088, SystemZ_TDGDT = 2089, SystemZ_TDGET = 2090, SystemZ_TDGXT = 2091, SystemZ_TEND = 2092, SystemZ_THDER = 2093, SystemZ_THDR = 2094, SystemZ_TM = 2095, SystemZ_TMHH = 2096, SystemZ_TMHL = 2097, SystemZ_TMLH = 2098, SystemZ_TMLL = 2099, SystemZ_TMY = 2100, SystemZ_TP = 2101, SystemZ_TPI = 2102, SystemZ_TPROT = 2103, SystemZ_TR = 2104, SystemZ_TRACE = 2105, SystemZ_TRACG = 2106, SystemZ_TRAP2 = 2107, SystemZ_TRAP4 = 2108, SystemZ_TRE = 2109, SystemZ_TROO = 2110, SystemZ_TROOOpt = 2111, SystemZ_TROT = 2112, SystemZ_TROTOpt = 2113, SystemZ_TRT = 2114, SystemZ_TRTE = 2115, SystemZ_TRTEOpt = 2116, SystemZ_TRTO = 2117, SystemZ_TRTOOpt = 2118, SystemZ_TRTR = 2119, SystemZ_TRTRE = 2120, SystemZ_TRTREOpt = 2121, SystemZ_TRTT = 2122, SystemZ_TRTTOpt = 2123, SystemZ_TS = 2124, SystemZ_TSCH = 2125, SystemZ_UNPK = 2126, SystemZ_UNPKA = 2127, SystemZ_UNPKU = 2128, SystemZ_UPT = 2129, SystemZ_VA = 2130, SystemZ_VAB = 2131, SystemZ_VAC = 2132, SystemZ_VACC = 2133, SystemZ_VACCB = 2134, SystemZ_VACCC = 2135, SystemZ_VACCCQ = 2136, SystemZ_VACCF = 2137, SystemZ_VACCG = 2138, SystemZ_VACCH = 2139, SystemZ_VACCQ = 2140, SystemZ_VACQ = 2141, SystemZ_VAF = 2142, SystemZ_VAG = 2143, SystemZ_VAH = 2144, SystemZ_VAP = 2145, SystemZ_VAQ = 2146, SystemZ_VAVG = 2147, SystemZ_VAVGB = 2148, SystemZ_VAVGF = 2149, SystemZ_VAVGG = 2150, SystemZ_VAVGH = 2151, SystemZ_VAVGL = 2152, SystemZ_VAVGLB = 2153, SystemZ_VAVGLF = 2154, SystemZ_VAVGLG = 2155, SystemZ_VAVGLH = 2156, SystemZ_VBPERM = 2157, SystemZ_VCDG = 2158, SystemZ_VCDGB = 2159, SystemZ_VCDLG = 2160, SystemZ_VCDLGB = 2161, SystemZ_VCEQ = 2162, SystemZ_VCEQB = 2163, SystemZ_VCEQBS = 2164, SystemZ_VCEQF = 2165, SystemZ_VCEQFS = 2166, SystemZ_VCEQG = 2167, SystemZ_VCEQGS = 2168, SystemZ_VCEQH = 2169, SystemZ_VCEQHS = 2170, SystemZ_VCGD = 2171, SystemZ_VCGDB = 2172, SystemZ_VCH = 2173, SystemZ_VCHB = 2174, SystemZ_VCHBS = 2175, SystemZ_VCHF = 2176, SystemZ_VCHFS = 2177, SystemZ_VCHG = 2178, SystemZ_VCHGS = 2179, SystemZ_VCHH = 2180, SystemZ_VCHHS = 2181, SystemZ_VCHL = 2182, SystemZ_VCHLB = 2183, SystemZ_VCHLBS = 2184, SystemZ_VCHLF = 2185, SystemZ_VCHLFS = 2186, SystemZ_VCHLG = 2187, SystemZ_VCHLGS = 2188, SystemZ_VCHLH = 2189, SystemZ_VCHLHS = 2190, SystemZ_VCKSM = 2191, SystemZ_VCLGD = 2192, SystemZ_VCLGDB = 2193, SystemZ_VCLZ = 2194, SystemZ_VCLZB = 2195, SystemZ_VCLZF = 2196, SystemZ_VCLZG = 2197, SystemZ_VCLZH = 2198, SystemZ_VCP = 2199, SystemZ_VCTZ = 2200, SystemZ_VCTZB = 2201, SystemZ_VCTZF = 2202, SystemZ_VCTZG = 2203, SystemZ_VCTZH = 2204, SystemZ_VCVB = 2205, SystemZ_VCVBG = 2206, SystemZ_VCVD = 2207, SystemZ_VCVDG = 2208, SystemZ_VDP = 2209, SystemZ_VEC = 2210, SystemZ_VECB = 2211, SystemZ_VECF = 2212, SystemZ_VECG = 2213, SystemZ_VECH = 2214, SystemZ_VECL = 2215, SystemZ_VECLB = 2216, SystemZ_VECLF = 2217, SystemZ_VECLG = 2218, SystemZ_VECLH = 2219, SystemZ_VERIM = 2220, SystemZ_VERIMB = 2221, SystemZ_VERIMF = 2222, SystemZ_VERIMG = 2223, SystemZ_VERIMH = 2224, SystemZ_VERLL = 2225, SystemZ_VERLLB = 2226, SystemZ_VERLLF = 2227, SystemZ_VERLLG = 2228, SystemZ_VERLLH = 2229, SystemZ_VERLLV = 2230, SystemZ_VERLLVB = 2231, SystemZ_VERLLVF = 2232, SystemZ_VERLLVG = 2233, SystemZ_VERLLVH = 2234, SystemZ_VESL = 2235, SystemZ_VESLB = 2236, SystemZ_VESLF = 2237, SystemZ_VESLG = 2238, SystemZ_VESLH = 2239, SystemZ_VESLV = 2240, SystemZ_VESLVB = 2241, SystemZ_VESLVF = 2242, SystemZ_VESLVG = 2243, SystemZ_VESLVH = 2244, SystemZ_VESRA = 2245, SystemZ_VESRAB = 2246, SystemZ_VESRAF = 2247, SystemZ_VESRAG = 2248, SystemZ_VESRAH = 2249, SystemZ_VESRAV = 2250, SystemZ_VESRAVB = 2251, SystemZ_VESRAVF = 2252, SystemZ_VESRAVG = 2253, SystemZ_VESRAVH = 2254, SystemZ_VESRL = 2255, SystemZ_VESRLB = 2256, SystemZ_VESRLF = 2257, SystemZ_VESRLG = 2258, SystemZ_VESRLH = 2259, SystemZ_VESRLV = 2260, SystemZ_VESRLVB = 2261, SystemZ_VESRLVF = 2262, SystemZ_VESRLVG = 2263, SystemZ_VESRLVH = 2264, SystemZ_VFA = 2265, SystemZ_VFADB = 2266, SystemZ_VFAE = 2267, SystemZ_VFAEB = 2268, SystemZ_VFAEBS = 2269, SystemZ_VFAEF = 2270, SystemZ_VFAEFS = 2271, SystemZ_VFAEH = 2272, SystemZ_VFAEHS = 2273, SystemZ_VFAEZB = 2274, SystemZ_VFAEZBS = 2275, SystemZ_VFAEZF = 2276, SystemZ_VFAEZFS = 2277, SystemZ_VFAEZH = 2278, SystemZ_VFAEZHS = 2279, SystemZ_VFASB = 2280, SystemZ_VFCE = 2281, SystemZ_VFCEDB = 2282, SystemZ_VFCEDBS = 2283, SystemZ_VFCESB = 2284, SystemZ_VFCESBS = 2285, SystemZ_VFCH = 2286, SystemZ_VFCHDB = 2287, SystemZ_VFCHDBS = 2288, SystemZ_VFCHE = 2289, SystemZ_VFCHEDB = 2290, SystemZ_VFCHEDBS = 2291, SystemZ_VFCHESB = 2292, SystemZ_VFCHESBS = 2293, SystemZ_VFCHSB = 2294, SystemZ_VFCHSBS = 2295, SystemZ_VFD = 2296, SystemZ_VFDDB = 2297, SystemZ_VFDSB = 2298, SystemZ_VFEE = 2299, SystemZ_VFEEB = 2300, SystemZ_VFEEBS = 2301, SystemZ_VFEEF = 2302, SystemZ_VFEEFS = 2303, SystemZ_VFEEH = 2304, SystemZ_VFEEHS = 2305, SystemZ_VFEEZB = 2306, SystemZ_VFEEZBS = 2307, SystemZ_VFEEZF = 2308, SystemZ_VFEEZFS = 2309, SystemZ_VFEEZH = 2310, SystemZ_VFEEZHS = 2311, SystemZ_VFENE = 2312, SystemZ_VFENEB = 2313, SystemZ_VFENEBS = 2314, SystemZ_VFENEF = 2315, SystemZ_VFENEFS = 2316, SystemZ_VFENEH = 2317, SystemZ_VFENEHS = 2318, SystemZ_VFENEZB = 2319, SystemZ_VFENEZBS = 2320, SystemZ_VFENEZF = 2321, SystemZ_VFENEZFS = 2322, SystemZ_VFENEZH = 2323, SystemZ_VFENEZHS = 2324, SystemZ_VFI = 2325, SystemZ_VFIDB = 2326, SystemZ_VFISB = 2327, SystemZ_VFKEDB = 2328, SystemZ_VFKEDBS = 2329, SystemZ_VFKESB = 2330, SystemZ_VFKESBS = 2331, SystemZ_VFKHDB = 2332, SystemZ_VFKHDBS = 2333, SystemZ_VFKHEDB = 2334, SystemZ_VFKHEDBS = 2335, SystemZ_VFKHESB = 2336, SystemZ_VFKHESBS = 2337, SystemZ_VFKHSB = 2338, SystemZ_VFKHSBS = 2339, SystemZ_VFLCDB = 2340, SystemZ_VFLCSB = 2341, SystemZ_VFLL = 2342, SystemZ_VFLLS = 2343, SystemZ_VFLNDB = 2344, SystemZ_VFLNSB = 2345, SystemZ_VFLPDB = 2346, SystemZ_VFLPSB = 2347, SystemZ_VFLR = 2348, SystemZ_VFLRD = 2349, SystemZ_VFM = 2350, SystemZ_VFMA = 2351, SystemZ_VFMADB = 2352, SystemZ_VFMASB = 2353, SystemZ_VFMAX = 2354, SystemZ_VFMAXDB = 2355, SystemZ_VFMAXSB = 2356, SystemZ_VFMDB = 2357, SystemZ_VFMIN = 2358, SystemZ_VFMINDB = 2359, SystemZ_VFMINSB = 2360, SystemZ_VFMS = 2361, SystemZ_VFMSB = 2362, SystemZ_VFMSDB = 2363, SystemZ_VFMSSB = 2364, SystemZ_VFNMA = 2365, SystemZ_VFNMADB = 2366, SystemZ_VFNMASB = 2367, SystemZ_VFNMS = 2368, SystemZ_VFNMSDB = 2369, SystemZ_VFNMSSB = 2370, SystemZ_VFPSO = 2371, SystemZ_VFPSODB = 2372, SystemZ_VFPSOSB = 2373, SystemZ_VFS = 2374, SystemZ_VFSDB = 2375, SystemZ_VFSQ = 2376, SystemZ_VFSQDB = 2377, SystemZ_VFSQSB = 2378, SystemZ_VFSSB = 2379, SystemZ_VFTCI = 2380, SystemZ_VFTCIDB = 2381, SystemZ_VFTCISB = 2382, SystemZ_VGBM = 2383, SystemZ_VGEF = 2384, SystemZ_VGEG = 2385, SystemZ_VGFM = 2386, SystemZ_VGFMA = 2387, SystemZ_VGFMAB = 2388, SystemZ_VGFMAF = 2389, SystemZ_VGFMAG = 2390, SystemZ_VGFMAH = 2391, SystemZ_VGFMB = 2392, SystemZ_VGFMF = 2393, SystemZ_VGFMG = 2394, SystemZ_VGFMH = 2395, SystemZ_VGM = 2396, SystemZ_VGMB = 2397, SystemZ_VGMF = 2398, SystemZ_VGMG = 2399, SystemZ_VGMH = 2400, SystemZ_VISTR = 2401, SystemZ_VISTRB = 2402, SystemZ_VISTRBS = 2403, SystemZ_VISTRF = 2404, SystemZ_VISTRFS = 2405, SystemZ_VISTRH = 2406, SystemZ_VISTRHS = 2407, SystemZ_VL = 2408, SystemZ_VLBB = 2409, SystemZ_VLC = 2410, SystemZ_VLCB = 2411, SystemZ_VLCF = 2412, SystemZ_VLCG = 2413, SystemZ_VLCH = 2414, SystemZ_VLDE = 2415, SystemZ_VLDEB = 2416, SystemZ_VLEB = 2417, SystemZ_VLED = 2418, SystemZ_VLEDB = 2419, SystemZ_VLEF = 2420, SystemZ_VLEG = 2421, SystemZ_VLEH = 2422, SystemZ_VLEIB = 2423, SystemZ_VLEIF = 2424, SystemZ_VLEIG = 2425, SystemZ_VLEIH = 2426, SystemZ_VLGV = 2427, SystemZ_VLGVB = 2428, SystemZ_VLGVF = 2429, SystemZ_VLGVG = 2430, SystemZ_VLGVH = 2431, SystemZ_VLIP = 2432, SystemZ_VLL = 2433, SystemZ_VLLEZ = 2434, SystemZ_VLLEZB = 2435, SystemZ_VLLEZF = 2436, SystemZ_VLLEZG = 2437, SystemZ_VLLEZH = 2438, SystemZ_VLLEZLF = 2439, SystemZ_VLM = 2440, SystemZ_VLP = 2441, SystemZ_VLPB = 2442, SystemZ_VLPF = 2443, SystemZ_VLPG = 2444, SystemZ_VLPH = 2445, SystemZ_VLR = 2446, SystemZ_VLREP = 2447, SystemZ_VLREPB = 2448, SystemZ_VLREPF = 2449, SystemZ_VLREPG = 2450, SystemZ_VLREPH = 2451, SystemZ_VLRL = 2452, SystemZ_VLRLR = 2453, SystemZ_VLVG = 2454, SystemZ_VLVGB = 2455, SystemZ_VLVGF = 2456, SystemZ_VLVGG = 2457, SystemZ_VLVGH = 2458, SystemZ_VLVGP = 2459, SystemZ_VMAE = 2460, SystemZ_VMAEB = 2461, SystemZ_VMAEF = 2462, SystemZ_VMAEH = 2463, SystemZ_VMAH = 2464, SystemZ_VMAHB = 2465, SystemZ_VMAHF = 2466, SystemZ_VMAHH = 2467, SystemZ_VMAL = 2468, SystemZ_VMALB = 2469, SystemZ_VMALE = 2470, SystemZ_VMALEB = 2471, SystemZ_VMALEF = 2472, SystemZ_VMALEH = 2473, SystemZ_VMALF = 2474, SystemZ_VMALH = 2475, SystemZ_VMALHB = 2476, SystemZ_VMALHF = 2477, SystemZ_VMALHH = 2478, SystemZ_VMALHW = 2479, SystemZ_VMALO = 2480, SystemZ_VMALOB = 2481, SystemZ_VMALOF = 2482, SystemZ_VMALOH = 2483, SystemZ_VMAO = 2484, SystemZ_VMAOB = 2485, SystemZ_VMAOF = 2486, SystemZ_VMAOH = 2487, SystemZ_VME = 2488, SystemZ_VMEB = 2489, SystemZ_VMEF = 2490, SystemZ_VMEH = 2491, SystemZ_VMH = 2492, SystemZ_VMHB = 2493, SystemZ_VMHF = 2494, SystemZ_VMHH = 2495, SystemZ_VML = 2496, SystemZ_VMLB = 2497, SystemZ_VMLE = 2498, SystemZ_VMLEB = 2499, SystemZ_VMLEF = 2500, SystemZ_VMLEH = 2501, SystemZ_VMLF = 2502, SystemZ_VMLH = 2503, SystemZ_VMLHB = 2504, SystemZ_VMLHF = 2505, SystemZ_VMLHH = 2506, SystemZ_VMLHW = 2507, SystemZ_VMLO = 2508, SystemZ_VMLOB = 2509, SystemZ_VMLOF = 2510, SystemZ_VMLOH = 2511, SystemZ_VMN = 2512, SystemZ_VMNB = 2513, SystemZ_VMNF = 2514, SystemZ_VMNG = 2515, SystemZ_VMNH = 2516, SystemZ_VMNL = 2517, SystemZ_VMNLB = 2518, SystemZ_VMNLF = 2519, SystemZ_VMNLG = 2520, SystemZ_VMNLH = 2521, SystemZ_VMO = 2522, SystemZ_VMOB = 2523, SystemZ_VMOF = 2524, SystemZ_VMOH = 2525, SystemZ_VMP = 2526, SystemZ_VMRH = 2527, SystemZ_VMRHB = 2528, SystemZ_VMRHF = 2529, SystemZ_VMRHG = 2530, SystemZ_VMRHH = 2531, SystemZ_VMRL = 2532, SystemZ_VMRLB = 2533, SystemZ_VMRLF = 2534, SystemZ_VMRLG = 2535, SystemZ_VMRLH = 2536, SystemZ_VMSL = 2537, SystemZ_VMSLG = 2538, SystemZ_VMSP = 2539, SystemZ_VMX = 2540, SystemZ_VMXB = 2541, SystemZ_VMXF = 2542, SystemZ_VMXG = 2543, SystemZ_VMXH = 2544, SystemZ_VMXL = 2545, SystemZ_VMXLB = 2546, SystemZ_VMXLF = 2547, SystemZ_VMXLG = 2548, SystemZ_VMXLH = 2549, SystemZ_VN = 2550, SystemZ_VNC = 2551, SystemZ_VNN = 2552, SystemZ_VNO = 2553, SystemZ_VNX = 2554, SystemZ_VO = 2555, SystemZ_VOC = 2556, SystemZ_VONE = 2557, SystemZ_VPDI = 2558, SystemZ_VPERM = 2559, SystemZ_VPK = 2560, SystemZ_VPKF = 2561, SystemZ_VPKG = 2562, SystemZ_VPKH = 2563, SystemZ_VPKLS = 2564, SystemZ_VPKLSF = 2565, SystemZ_VPKLSFS = 2566, SystemZ_VPKLSG = 2567, SystemZ_VPKLSGS = 2568, SystemZ_VPKLSH = 2569, SystemZ_VPKLSHS = 2570, SystemZ_VPKS = 2571, SystemZ_VPKSF = 2572, SystemZ_VPKSFS = 2573, SystemZ_VPKSG = 2574, SystemZ_VPKSGS = 2575, SystemZ_VPKSH = 2576, SystemZ_VPKSHS = 2577, SystemZ_VPKZ = 2578, SystemZ_VPOPCT = 2579, SystemZ_VPOPCTB = 2580, SystemZ_VPOPCTF = 2581, SystemZ_VPOPCTG = 2582, SystemZ_VPOPCTH = 2583, SystemZ_VPSOP = 2584, SystemZ_VREP = 2585, SystemZ_VREPB = 2586, SystemZ_VREPF = 2587, SystemZ_VREPG = 2588, SystemZ_VREPH = 2589, SystemZ_VREPI = 2590, SystemZ_VREPIB = 2591, SystemZ_VREPIF = 2592, SystemZ_VREPIG = 2593, SystemZ_VREPIH = 2594, SystemZ_VRP = 2595, SystemZ_VS = 2596, SystemZ_VSB = 2597, SystemZ_VSBCBI = 2598, SystemZ_VSBCBIQ = 2599, SystemZ_VSBI = 2600, SystemZ_VSBIQ = 2601, SystemZ_VSCBI = 2602, SystemZ_VSCBIB = 2603, SystemZ_VSCBIF = 2604, SystemZ_VSCBIG = 2605, SystemZ_VSCBIH = 2606, SystemZ_VSCBIQ = 2607, SystemZ_VSCEF = 2608, SystemZ_VSCEG = 2609, SystemZ_VSDP = 2610, SystemZ_VSEG = 2611, SystemZ_VSEGB = 2612, SystemZ_VSEGF = 2613, SystemZ_VSEGH = 2614, SystemZ_VSEL = 2615, SystemZ_VSF = 2616, SystemZ_VSG = 2617, SystemZ_VSH = 2618, SystemZ_VSL = 2619, SystemZ_VSLB = 2620, SystemZ_VSLDB = 2621, SystemZ_VSP = 2622, SystemZ_VSQ = 2623, SystemZ_VSRA = 2624, SystemZ_VSRAB = 2625, SystemZ_VSRL = 2626, SystemZ_VSRLB = 2627, SystemZ_VSRP = 2628, SystemZ_VST = 2629, SystemZ_VSTEB = 2630, SystemZ_VSTEF = 2631, SystemZ_VSTEG = 2632, SystemZ_VSTEH = 2633, SystemZ_VSTL = 2634, SystemZ_VSTM = 2635, SystemZ_VSTRC = 2636, SystemZ_VSTRCB = 2637, SystemZ_VSTRCBS = 2638, SystemZ_VSTRCF = 2639, SystemZ_VSTRCFS = 2640, SystemZ_VSTRCH = 2641, SystemZ_VSTRCHS = 2642, SystemZ_VSTRCZB = 2643, SystemZ_VSTRCZBS = 2644, SystemZ_VSTRCZF = 2645, SystemZ_VSTRCZFS = 2646, SystemZ_VSTRCZH = 2647, SystemZ_VSTRCZHS = 2648, SystemZ_VSTRL = 2649, SystemZ_VSTRLR = 2650, SystemZ_VSUM = 2651, SystemZ_VSUMB = 2652, SystemZ_VSUMG = 2653, SystemZ_VSUMGF = 2654, SystemZ_VSUMGH = 2655, SystemZ_VSUMH = 2656, SystemZ_VSUMQ = 2657, SystemZ_VSUMQF = 2658, SystemZ_VSUMQG = 2659, SystemZ_VTM = 2660, SystemZ_VTP = 2661, SystemZ_VUPH = 2662, SystemZ_VUPHB = 2663, SystemZ_VUPHF = 2664, SystemZ_VUPHH = 2665, SystemZ_VUPKZ = 2666, SystemZ_VUPL = 2667, SystemZ_VUPLB = 2668, SystemZ_VUPLF = 2669, SystemZ_VUPLH = 2670, SystemZ_VUPLHB = 2671, SystemZ_VUPLHF = 2672, SystemZ_VUPLHH = 2673, SystemZ_VUPLHW = 2674, SystemZ_VUPLL = 2675, SystemZ_VUPLLB = 2676, SystemZ_VUPLLF = 2677, SystemZ_VUPLLH = 2678, SystemZ_VX = 2679, SystemZ_VZERO = 2680, SystemZ_WCDGB = 2681, SystemZ_WCDLGB = 2682, SystemZ_WCGDB = 2683, SystemZ_WCLGDB = 2684, SystemZ_WFADB = 2685, SystemZ_WFASB = 2686, SystemZ_WFAXB = 2687, SystemZ_WFC = 2688, SystemZ_WFCDB = 2689, SystemZ_WFCEDB = 2690, SystemZ_WFCEDBS = 2691, SystemZ_WFCESB = 2692, SystemZ_WFCESBS = 2693, SystemZ_WFCEXB = 2694, SystemZ_WFCEXBS = 2695, SystemZ_WFCHDB = 2696, SystemZ_WFCHDBS = 2697, SystemZ_WFCHEDB = 2698, SystemZ_WFCHEDBS = 2699, SystemZ_WFCHESB = 2700, SystemZ_WFCHESBS = 2701, SystemZ_WFCHEXB = 2702, SystemZ_WFCHEXBS = 2703, SystemZ_WFCHSB = 2704, SystemZ_WFCHSBS = 2705, SystemZ_WFCHXB = 2706, SystemZ_WFCHXBS = 2707, SystemZ_WFCSB = 2708, SystemZ_WFCXB = 2709, SystemZ_WFDDB = 2710, SystemZ_WFDSB = 2711, SystemZ_WFDXB = 2712, SystemZ_WFIDB = 2713, SystemZ_WFISB = 2714, SystemZ_WFIXB = 2715, SystemZ_WFK = 2716, SystemZ_WFKDB = 2717, SystemZ_WFKEDB = 2718, SystemZ_WFKEDBS = 2719, SystemZ_WFKESB = 2720, SystemZ_WFKESBS = 2721, SystemZ_WFKEXB = 2722, SystemZ_WFKEXBS = 2723, SystemZ_WFKHDB = 2724, SystemZ_WFKHDBS = 2725, SystemZ_WFKHEDB = 2726, SystemZ_WFKHEDBS = 2727, SystemZ_WFKHESB = 2728, SystemZ_WFKHESBS = 2729, SystemZ_WFKHEXB = 2730, SystemZ_WFKHEXBS = 2731, SystemZ_WFKHSB = 2732, SystemZ_WFKHSBS = 2733, SystemZ_WFKHXB = 2734, SystemZ_WFKHXBS = 2735, SystemZ_WFKSB = 2736, SystemZ_WFKXB = 2737, SystemZ_WFLCDB = 2738, SystemZ_WFLCSB = 2739, SystemZ_WFLCXB = 2740, SystemZ_WFLLD = 2741, SystemZ_WFLLS = 2742, SystemZ_WFLNDB = 2743, SystemZ_WFLNSB = 2744, SystemZ_WFLNXB = 2745, SystemZ_WFLPDB = 2746, SystemZ_WFLPSB = 2747, SystemZ_WFLPXB = 2748, SystemZ_WFLRD = 2749, SystemZ_WFLRX = 2750, SystemZ_WFMADB = 2751, SystemZ_WFMASB = 2752, SystemZ_WFMAXB = 2753, SystemZ_WFMAXDB = 2754, SystemZ_WFMAXSB = 2755, SystemZ_WFMAXXB = 2756, SystemZ_WFMDB = 2757, SystemZ_WFMINDB = 2758, SystemZ_WFMINSB = 2759, SystemZ_WFMINXB = 2760, SystemZ_WFMSB = 2761, SystemZ_WFMSDB = 2762, SystemZ_WFMSSB = 2763, SystemZ_WFMSXB = 2764, SystemZ_WFMXB = 2765, SystemZ_WFNMADB = 2766, SystemZ_WFNMASB = 2767, SystemZ_WFNMAXB = 2768, SystemZ_WFNMSDB = 2769, SystemZ_WFNMSSB = 2770, SystemZ_WFNMSXB = 2771, SystemZ_WFPSODB = 2772, SystemZ_WFPSOSB = 2773, SystemZ_WFPSOXB = 2774, SystemZ_WFSDB = 2775, SystemZ_WFSQDB = 2776, SystemZ_WFSQSB = 2777, SystemZ_WFSQXB = 2778, SystemZ_WFSSB = 2779, SystemZ_WFSXB = 2780, SystemZ_WFTCIDB = 2781, SystemZ_WFTCISB = 2782, SystemZ_WFTCIXB = 2783, SystemZ_WLDEB = 2784, SystemZ_WLEDB = 2785, SystemZ_X = 2786, SystemZ_XC = 2787, SystemZ_XG = 2788, SystemZ_XGR = 2789, SystemZ_XGRK = 2790, SystemZ_XI = 2791, SystemZ_XIHF = 2792, SystemZ_XILF = 2793, SystemZ_XIY = 2794, SystemZ_XR = 2795, SystemZ_XRK = 2796, SystemZ_XSCH = 2797, SystemZ_XY = 2798, SystemZ_ZAP = 2799, SystemZ_INSTRUCTION_LIST_END = 2800 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc000064400000000000000000000622070072674642500236310ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { SystemZ_NoRegister, SystemZ_CC = 1, SystemZ_A0 = 2, SystemZ_A1 = 3, SystemZ_A2 = 4, SystemZ_A3 = 5, SystemZ_A4 = 6, SystemZ_A5 = 7, SystemZ_A6 = 8, SystemZ_A7 = 9, SystemZ_A8 = 10, SystemZ_A9 = 11, SystemZ_A10 = 12, SystemZ_A11 = 13, SystemZ_A12 = 14, SystemZ_A13 = 15, SystemZ_A14 = 16, SystemZ_A15 = 17, SystemZ_C0 = 18, SystemZ_C1 = 19, SystemZ_C2 = 20, SystemZ_C3 = 21, SystemZ_C4 = 22, SystemZ_C5 = 23, SystemZ_C6 = 24, SystemZ_C7 = 25, SystemZ_C8 = 26, SystemZ_C9 = 27, SystemZ_C10 = 28, SystemZ_C11 = 29, SystemZ_C12 = 30, SystemZ_C13 = 31, SystemZ_C14 = 32, SystemZ_C15 = 33, SystemZ_V0 = 34, SystemZ_V1 = 35, SystemZ_V2 = 36, SystemZ_V3 = 37, SystemZ_V4 = 38, SystemZ_V5 = 39, SystemZ_V6 = 40, SystemZ_V7 = 41, SystemZ_V8 = 42, SystemZ_V9 = 43, SystemZ_V10 = 44, SystemZ_V11 = 45, SystemZ_V12 = 46, SystemZ_V13 = 47, SystemZ_V14 = 48, SystemZ_V15 = 49, SystemZ_V16 = 50, SystemZ_V17 = 51, SystemZ_V18 = 52, SystemZ_V19 = 53, SystemZ_V20 = 54, SystemZ_V21 = 55, SystemZ_V22 = 56, SystemZ_V23 = 57, SystemZ_V24 = 58, SystemZ_V25 = 59, SystemZ_V26 = 60, SystemZ_V27 = 61, SystemZ_V28 = 62, SystemZ_V29 = 63, SystemZ_V30 = 64, SystemZ_V31 = 65, SystemZ_F0D = 66, SystemZ_F1D = 67, SystemZ_F2D = 68, SystemZ_F3D = 69, SystemZ_F4D = 70, SystemZ_F5D = 71, SystemZ_F6D = 72, SystemZ_F7D = 73, SystemZ_F8D = 74, SystemZ_F9D = 75, SystemZ_F10D = 76, SystemZ_F11D = 77, SystemZ_F12D = 78, SystemZ_F13D = 79, SystemZ_F14D = 80, SystemZ_F15D = 81, SystemZ_F16D = 82, SystemZ_F17D = 83, SystemZ_F18D = 84, SystemZ_F19D = 85, SystemZ_F20D = 86, SystemZ_F21D = 87, SystemZ_F22D = 88, SystemZ_F23D = 89, SystemZ_F24D = 90, SystemZ_F25D = 91, SystemZ_F26D = 92, SystemZ_F27D = 93, SystemZ_F28D = 94, SystemZ_F29D = 95, SystemZ_F30D = 96, SystemZ_F31D = 97, SystemZ_F0Q = 98, SystemZ_F1Q = 99, SystemZ_F4Q = 100, SystemZ_F5Q = 101, SystemZ_F8Q = 102, SystemZ_F9Q = 103, SystemZ_F12Q = 104, SystemZ_F13Q = 105, SystemZ_F0S = 106, SystemZ_F1S = 107, SystemZ_F2S = 108, SystemZ_F3S = 109, SystemZ_F4S = 110, SystemZ_F5S = 111, SystemZ_F6S = 112, SystemZ_F7S = 113, SystemZ_F8S = 114, SystemZ_F9S = 115, SystemZ_F10S = 116, SystemZ_F11S = 117, SystemZ_F12S = 118, SystemZ_F13S = 119, SystemZ_F14S = 120, SystemZ_F15S = 121, SystemZ_F16S = 122, SystemZ_F17S = 123, SystemZ_F18S = 124, SystemZ_F19S = 125, SystemZ_F20S = 126, SystemZ_F21S = 127, SystemZ_F22S = 128, SystemZ_F23S = 129, SystemZ_F24S = 130, SystemZ_F25S = 131, SystemZ_F26S = 132, SystemZ_F27S = 133, SystemZ_F28S = 134, SystemZ_F29S = 135, SystemZ_F30S = 136, SystemZ_F31S = 137, SystemZ_R0D = 138, SystemZ_R1D = 139, SystemZ_R2D = 140, SystemZ_R3D = 141, SystemZ_R4D = 142, SystemZ_R5D = 143, SystemZ_R6D = 144, SystemZ_R7D = 145, SystemZ_R8D = 146, SystemZ_R9D = 147, SystemZ_R10D = 148, SystemZ_R11D = 149, SystemZ_R12D = 150, SystemZ_R13D = 151, SystemZ_R14D = 152, SystemZ_R15D = 153, SystemZ_R0H = 154, SystemZ_R1H = 155, SystemZ_R2H = 156, SystemZ_R3H = 157, SystemZ_R4H = 158, SystemZ_R5H = 159, SystemZ_R6H = 160, SystemZ_R7H = 161, SystemZ_R8H = 162, SystemZ_R9H = 163, SystemZ_R10H = 164, SystemZ_R11H = 165, SystemZ_R12H = 166, SystemZ_R13H = 167, SystemZ_R14H = 168, SystemZ_R15H = 169, SystemZ_R0L = 170, SystemZ_R1L = 171, SystemZ_R2L = 172, SystemZ_R3L = 173, SystemZ_R4L = 174, SystemZ_R5L = 175, SystemZ_R6L = 176, SystemZ_R7L = 177, SystemZ_R8L = 178, SystemZ_R9L = 179, SystemZ_R10L = 180, SystemZ_R11L = 181, SystemZ_R12L = 182, SystemZ_R13L = 183, SystemZ_R14L = 184, SystemZ_R15L = 185, SystemZ_R0Q = 186, SystemZ_R2Q = 187, SystemZ_R4Q = 188, SystemZ_R6Q = 189, SystemZ_R8Q = 190, SystemZ_R10Q = 191, SystemZ_R12Q = 192, SystemZ_R14Q = 193, SystemZ_NUM_TARGET_REGS // 194 }; // Register classes enum { SystemZ_GRX32BitRegClassID = 0, SystemZ_VR32BitRegClassID = 1, SystemZ_AR32BitRegClassID = 2, SystemZ_FP32BitRegClassID = 3, SystemZ_GR32BitRegClassID = 4, SystemZ_GRH32BitRegClassID = 5, SystemZ_ADDR32BitRegClassID = 6, SystemZ_CCRRegClassID = 7, SystemZ_AnyRegBitRegClassID = 8, SystemZ_AnyRegBit_with_subreg_r32RegClassID = 9, SystemZ_VR64BitRegClassID = 10, SystemZ_AnyRegBit_with_subreg_r64RegClassID = 11, SystemZ_CR64BitRegClassID = 12, SystemZ_FP64BitRegClassID = 13, SystemZ_GR64BitRegClassID = 14, SystemZ_ADDR64BitRegClassID = 15, SystemZ_VR128BitRegClassID = 16, SystemZ_VF128BitRegClassID = 17, SystemZ_FP128BitRegClassID = 18, SystemZ_GR128BitRegClassID = 19, SystemZ_ADDR128BitRegClassID = 20, }; #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg SystemZRegDiffLists[] = { /* 0 */ 64857, 1, 1, 1, 0, /* 5 */ 65325, 1, 0, /* 8 */ 65471, 2, 0, /* 11 */ 65473, 2, 0, /* 14 */ 65475, 2, 0, /* 17 */ 65477, 2, 0, /* 20 */ 32, 40, 0, /* 23 */ 65506, 40, 65494, 40, 0, /* 28 */ 65508, 40, 65494, 40, 0, /* 33 */ 65510, 40, 65494, 40, 0, /* 38 */ 65512, 40, 65494, 40, 0, /* 43 */ 65504, 40, 0, /* 46 */ 65520, 40, 0, /* 49 */ 65504, 41, 0, /* 52 */ 65520, 41, 0, /* 55 */ 65504, 42, 0, /* 58 */ 65520, 42, 0, /* 61 */ 65504, 43, 0, /* 64 */ 65520, 43, 0, /* 67 */ 65504, 44, 0, /* 70 */ 65520, 44, 0, /* 73 */ 65504, 45, 0, /* 76 */ 65520, 45, 0, /* 79 */ 65504, 46, 0, /* 82 */ 65520, 46, 0, /* 85 */ 65504, 47, 0, /* 88 */ 65520, 47, 0, /* 91 */ 65504, 48, 0, /* 94 */ 65520, 48, 0, /* 97 */ 65496, 65504, 56, 0, /* 101 */ 65496, 65504, 58, 0, /* 105 */ 65496, 65504, 60, 0, /* 109 */ 65496, 65504, 62, 0, /* 113 */ 65496, 65504, 64, 0, /* 117 */ 65261, 0, /* 119 */ 65294, 0, /* 121 */ 65463, 0, /* 123 */ 65503, 0, /* 125 */ 65496, 65504, 0, /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0, /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0, /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0, /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0, /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0, /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0, /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0, /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0, /* 184 */ 65535, 0, }; static const uint16_t SystemZSubRegIdxLists[] = { /* 0 */ 6, 1, 0, /* 3 */ 7, 6, 1, 2, 4, 3, 0, /* 10 */ 7, 8, 2, 5, 0, /* 15 */ 9, 8, 0, }; static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, { 226, 4, 4, 2, 2945, 0 }, { 20, 4, 4, 2, 2945, 0 }, { 49, 4, 4, 2, 2945, 0 }, { 74, 4, 4, 2, 2945, 0 }, { 99, 4, 4, 2, 2945, 0 }, { 124, 4, 4, 2, 2945, 0 }, { 149, 4, 4, 2, 2945, 0 }, { 166, 4, 4, 2, 2945, 0 }, { 183, 4, 4, 2, 2945, 0 }, { 200, 4, 4, 2, 2945, 0 }, { 217, 4, 4, 2, 2945, 0 }, { 0, 4, 4, 2, 2945, 0 }, { 29, 4, 4, 2, 2945, 0 }, { 58, 4, 4, 2, 2945, 0 }, { 83, 4, 4, 2, 2945, 0 }, { 108, 4, 4, 2, 2945, 0 }, { 133, 4, 4, 2, 2945, 0 }, { 23, 4, 4, 2, 2945, 0 }, { 52, 4, 4, 2, 2945, 0 }, { 77, 4, 4, 2, 2945, 0 }, { 102, 4, 4, 2, 2945, 0 }, { 127, 4, 4, 2, 2945, 0 }, { 152, 4, 4, 2, 2945, 0 }, { 169, 4, 4, 2, 2945, 0 }, { 186, 4, 4, 2, 2945, 0 }, { 203, 4, 4, 2, 2945, 0 }, { 220, 4, 4, 2, 2945, 0 }, { 4, 4, 4, 2, 2945, 0 }, { 33, 4, 4, 2, 2945, 0 }, { 62, 4, 4, 2, 2945, 0 }, { 87, 4, 4, 2, 2945, 0 }, { 112, 4, 4, 2, 2945, 0 }, { 137, 4, 4, 2, 2945, 0 }, { 26, 20, 4, 15, 2945, 8 }, { 55, 20, 4, 15, 2945, 8 }, { 80, 20, 4, 15, 2945, 8 }, { 105, 20, 4, 15, 2945, 8 }, { 130, 20, 4, 15, 2945, 8 }, { 155, 20, 4, 15, 2945, 8 }, { 172, 20, 4, 15, 2945, 8 }, { 189, 20, 4, 15, 2945, 8 }, { 206, 20, 4, 15, 2945, 8 }, { 223, 20, 4, 15, 2945, 8 }, { 8, 20, 4, 15, 2945, 8 }, { 37, 20, 4, 15, 2945, 8 }, { 66, 20, 4, 15, 2945, 8 }, { 91, 20, 4, 15, 2945, 8 }, { 116, 20, 4, 15, 2945, 8 }, { 141, 20, 4, 15, 2945, 8 }, { 158, 20, 4, 15, 2945, 8 }, { 175, 20, 4, 15, 2945, 8 }, { 192, 20, 4, 15, 2945, 8 }, { 209, 20, 4, 15, 2945, 8 }, { 12, 20, 4, 15, 2945, 8 }, { 41, 20, 4, 15, 2945, 8 }, { 70, 20, 4, 15, 2945, 8 }, { 95, 20, 4, 15, 2945, 8 }, { 120, 20, 4, 15, 2945, 8 }, { 145, 20, 4, 15, 2945, 8 }, { 162, 20, 4, 15, 2945, 8 }, { 179, 20, 4, 15, 2945, 8 }, { 196, 20, 4, 15, 2945, 8 }, { 213, 20, 4, 15, 2945, 8 }, { 16, 20, 4, 15, 2945, 8 }, { 45, 20, 4, 15, 2945, 8 }, { 249, 21, 114, 16, 1969, 8 }, { 277, 21, 114, 16, 1969, 8 }, { 300, 21, 110, 16, 1969, 8 }, { 323, 21, 110, 16, 1969, 8 }, { 346, 21, 110, 16, 1969, 8 }, { 369, 21, 110, 16, 1969, 8 }, { 387, 21, 106, 16, 1969, 8 }, { 405, 21, 106, 16, 1969, 8 }, { 423, 21, 106, 16, 1969, 8 }, { 441, 21, 106, 16, 1969, 8 }, { 229, 21, 102, 16, 1969, 8 }, { 257, 21, 102, 16, 1969, 8 }, { 285, 21, 102, 16, 1969, 8 }, { 308, 21, 102, 16, 1969, 8 }, { 331, 21, 98, 16, 1969, 8 }, { 354, 21, 98, 16, 1969, 8 }, { 377, 21, 126, 16, 1969, 8 }, { 395, 21, 126, 16, 1969, 8 }, { 413, 21, 126, 16, 1969, 8 }, { 431, 21, 126, 16, 1969, 8 }, { 239, 21, 126, 16, 1969, 8 }, { 267, 21, 126, 16, 1969, 8 }, { 295, 21, 126, 16, 1969, 8 }, { 318, 21, 126, 16, 1969, 8 }, { 341, 21, 126, 16, 1969, 8 }, { 364, 21, 126, 16, 1969, 8 }, { 382, 21, 126, 16, 1969, 8 }, { 400, 21, 126, 16, 1969, 8 }, { 418, 21, 126, 16, 1969, 8 }, { 436, 21, 126, 16, 1969, 8 }, { 244, 21, 126, 16, 1969, 8 }, { 272, 21, 126, 16, 1969, 8 }, { 594, 23, 4, 10, 129, 7 }, { 602, 23, 4, 10, 129, 7 }, { 630, 28, 4, 10, 177, 7 }, { 638, 28, 4, 10, 177, 7 }, { 646, 33, 4, 10, 225, 7 }, { 654, 33, 4, 10, 225, 7 }, { 606, 38, 4, 10, 273, 7 }, { 620, 38, 4, 10, 273, 7 }, { 673, 4, 113, 2, 1937, 0 }, { 692, 4, 113, 2, 1937, 0 }, { 706, 4, 109, 2, 1937, 0 }, { 720, 4, 109, 2, 1937, 0 }, { 734, 4, 109, 2, 1937, 0 }, { 748, 4, 109, 2, 1937, 0 }, { 762, 4, 105, 2, 1937, 0 }, { 776, 4, 105, 2, 1937, 0 }, { 790, 4, 105, 2, 1937, 0 }, { 804, 4, 105, 2, 1937, 0 }, { 658, 4, 101, 2, 1937, 0 }, { 677, 4, 101, 2, 1937, 0 }, { 696, 4, 101, 2, 1937, 0 }, { 710, 4, 101, 2, 1937, 0 }, { 724, 4, 97, 2, 1937, 0 }, { 738, 4, 97, 2, 1937, 0 }, { 752, 4, 125, 2, 1937, 0 }, { 766, 4, 125, 2, 1937, 0 }, { 780, 4, 125, 2, 1937, 0 }, { 794, 4, 125, 2, 1937, 0 }, { 663, 4, 125, 2, 1937, 0 }, { 682, 4, 125, 2, 1937, 0 }, { 701, 4, 125, 2, 1937, 0 }, { 715, 4, 125, 2, 1937, 0 }, { 729, 4, 125, 2, 1937, 0 }, { 743, 4, 125, 2, 1937, 0 }, { 757, 4, 125, 2, 1937, 0 }, { 771, 4, 125, 2, 1937, 0 }, { 785, 4, 125, 2, 1937, 0 }, { 799, 4, 125, 2, 1937, 0 }, { 668, 4, 125, 2, 1937, 0 }, { 687, 4, 125, 2, 1937, 0 }, { 253, 132, 92, 0, 82, 4 }, { 281, 132, 86, 0, 82, 4 }, { 304, 132, 86, 0, 82, 4 }, { 327, 132, 80, 0, 82, 4 }, { 350, 132, 80, 0, 82, 4 }, { 373, 132, 74, 0, 82, 4 }, { 391, 132, 74, 0, 82, 4 }, { 409, 132, 68, 0, 82, 4 }, { 427, 132, 68, 0, 82, 4 }, { 445, 132, 62, 0, 82, 4 }, { 234, 132, 62, 0, 82, 4 }, { 262, 132, 56, 0, 82, 4 }, { 290, 132, 56, 0, 82, 4 }, { 313, 132, 50, 0, 82, 4 }, { 336, 132, 50, 0, 82, 4 }, { 359, 132, 21, 0, 82, 4 }, { 454, 4, 94, 2, 1906, 0 }, { 463, 4, 88, 2, 1906, 0 }, { 472, 4, 88, 2, 1906, 0 }, { 481, 4, 82, 2, 1906, 0 }, { 490, 4, 82, 2, 1906, 0 }, { 499, 4, 76, 2, 1906, 0 }, { 503, 4, 76, 2, 1906, 0 }, { 507, 4, 70, 2, 1906, 0 }, { 511, 4, 70, 2, 1906, 0 }, { 515, 4, 64, 2, 1906, 0 }, { 449, 4, 64, 2, 1906, 0 }, { 458, 4, 58, 2, 1906, 0 }, { 467, 4, 58, 2, 1906, 0 }, { 476, 4, 52, 2, 1906, 0 }, { 485, 4, 52, 2, 1906, 0 }, { 494, 4, 46, 2, 1906, 0 }, { 524, 4, 91, 2, 1874, 0 }, { 533, 4, 85, 2, 1874, 0 }, { 542, 4, 85, 2, 1874, 0 }, { 551, 4, 79, 2, 1874, 0 }, { 560, 4, 79, 2, 1874, 0 }, { 569, 4, 73, 2, 1874, 0 }, { 573, 4, 73, 2, 1874, 0 }, { 577, 4, 67, 2, 1874, 0 }, { 581, 4, 67, 2, 1874, 0 }, { 585, 4, 61, 2, 1874, 0 }, { 519, 4, 61, 2, 1874, 0 }, { 528, 4, 55, 2, 1874, 0 }, { 537, 4, 55, 2, 1874, 0 }, { 546, 4, 49, 2, 1874, 0 }, { 555, 4, 49, 2, 1874, 0 }, { 564, 4, 43, 2, 1874, 0 }, { 598, 128, 4, 3, 4, 2 }, { 616, 135, 4, 3, 4, 2 }, { 634, 142, 4, 3, 4, 2 }, { 642, 149, 4, 3, 4, 2 }, { 650, 156, 4, 3, 4, 2 }, { 589, 163, 4, 3, 4, 2 }, { 611, 170, 4, 3, 4, 2 }, { 625, 177, 4, 3, 4, 2 }, }; // GRX32Bit Register Class... static const MCPhysReg GRX32Bit[] = { SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H, }; // GRX32Bit Bit set. static const uint8_t GRX32BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, }; // VR32Bit Register Class... static const MCPhysReg VR32Bit[] = { SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, }; // VR32Bit Bit set. static const uint8_t VR32BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, }; // AR32Bit Register Class... static const MCPhysReg AR32Bit[] = { SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15, }; // AR32Bit Bit set. static const uint8_t AR32BitBits[] = { 0xfc, 0xff, 0x03, }; // FP32Bit Register Class... static const MCPhysReg FP32Bit[] = { SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, }; // FP32Bit Bit set. static const uint8_t FP32BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // GR32Bit Register Class... static const MCPhysReg GR32Bit[] = { SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, }; // GR32Bit Bit set. static const uint8_t GR32BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // GRH32Bit Register Class... static const MCPhysReg GRH32Bit[] = { SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H, }; // GRH32Bit Bit set. static const uint8_t GRH32BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // ADDR32Bit Register Class... static const MCPhysReg ADDR32Bit[] = { SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L, }; // ADDR32Bit Bit set. static const uint8_t ADDR32BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, }; // CCR Register Class... static const MCPhysReg CCR[] = { SystemZ_CC, }; // CCR Bit set. static const uint8_t CCRBits[] = { 0x02, }; // AnyRegBit Register Class... static const MCPhysReg AnyRegBit[] = { SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // AnyRegBit Bit set. static const uint8_t AnyRegBitBits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // AnyRegBit_with_subreg_r32 Register Class... static const MCPhysReg AnyRegBit_with_subreg_r32[] = { SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // AnyRegBit_with_subreg_r32 Bit set. static const uint8_t AnyRegBit_with_subreg_r32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0xfc, 0xff, 0x03, }; // VR64Bit Register Class... static const MCPhysReg VR64Bit[] = { SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, }; // VR64Bit Bit set. static const uint8_t VR64BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, }; // AnyRegBit_with_subreg_r64 Register Class... static const MCPhysReg AnyRegBit_with_subreg_r64[] = { SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // AnyRegBit_with_subreg_r64 Bit set. static const uint8_t AnyRegBit_with_subreg_r64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // CR64Bit Register Class... static const MCPhysReg CR64Bit[] = { SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15, }; // CR64Bit Bit set. static const uint8_t CR64BitBits[] = { 0x00, 0x00, 0xfc, 0xff, 0x03, }; // FP64Bit Register Class... static const MCPhysReg FP64Bit[] = { SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, }; // FP64Bit Bit set. static const uint8_t FP64BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // GR64Bit Register Class... static const MCPhysReg GR64Bit[] = { SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, }; // GR64Bit Bit set. static const uint8_t GR64BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // ADDR64Bit Register Class... static const MCPhysReg ADDR64Bit[] = { SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D, }; // ADDR64Bit Bit set. static const uint8_t ADDR64BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, }; // VR128Bit Register Class... static const MCPhysReg VR128Bit[] = { SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // VR128Bit Bit set. static const uint8_t VR128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, }; // VF128Bit Register Class... static const MCPhysReg VF128Bit[] = { SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, }; // VF128Bit Bit set. static const uint8_t VF128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, }; // FP128Bit Register Class... static const MCPhysReg FP128Bit[] = { SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q, }; // FP128Bit Bit set. static const uint8_t FP128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // GR128Bit Register Class... static const MCPhysReg GR128Bit[] = { SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, }; // GR128Bit Bit set. static const uint8_t GR128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, }; // ADDR128Bit Register Class... static const MCPhysReg ADDR128Bit[] = { SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q, }; // ADDR128Bit Bit set. static const uint8_t ADDR128BitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, }; static const MCRegisterClass SystemZMCRegisterClasses[] = { { GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits) }, { VR32Bit, VR32BitBits, sizeof(VR32BitBits) }, { AR32Bit, AR32BitBits, sizeof(AR32BitBits) }, { FP32Bit, FP32BitBits, sizeof(FP32BitBits) }, { GR32Bit, GR32BitBits, sizeof(GR32BitBits) }, { GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits) }, { ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits) }, { AnyRegBit_with_subreg_r32, AnyRegBit_with_subreg_r32Bits, sizeof(AnyRegBit_with_subreg_r32Bits) }, { VR64Bit, VR64BitBits, sizeof(VR64BitBits) }, { AnyRegBit_with_subreg_r64, AnyRegBit_with_subreg_r64Bits, sizeof(AnyRegBit_with_subreg_r64Bits) }, { CR64Bit, CR64BitBits, sizeof(CR64BitBits) }, { FP64Bit, FP64BitBits, sizeof(FP64BitBits) }, { GR64Bit, GR64BitBits, sizeof(GR64BitBits) }, { ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits) }, { VR128Bit, VR128BitBits, sizeof(VR128BitBits) }, { VF128Bit, VF128BitBits, sizeof(VF128BitBits) }, { FP128Bit, FP128BitBits, sizeof(FP128BitBits) }, { GR128Bit, GR128BitBits, sizeof(GR128BitBits) }, { ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc000064400000000000000000000042650072674642500240050ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_SUBTARGETINFO_ENUM #undef GET_SUBTARGETINFO_ENUM enum { SystemZ_FeatureDFPPackedConversion = 1ULL << 0, SystemZ_FeatureDFPZonedConversion = 1ULL << 1, SystemZ_FeatureDistinctOps = 1ULL << 2, SystemZ_FeatureEnhancedDAT2 = 1ULL << 3, SystemZ_FeatureExecutionHint = 1ULL << 4, SystemZ_FeatureFPExtension = 1ULL << 5, SystemZ_FeatureFastSerialization = 1ULL << 6, SystemZ_FeatureGuardedStorage = 1ULL << 7, SystemZ_FeatureHighWord = 1ULL << 8, SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9, SystemZ_FeatureInterlockedAccess1 = 1ULL << 10, SystemZ_FeatureLoadAndTrap = 1ULL << 11, SystemZ_FeatureLoadAndZeroRightmostByte = 1ULL << 12, SystemZ_FeatureLoadStoreOnCond = 1ULL << 13, SystemZ_FeatureLoadStoreOnCond2 = 1ULL << 14, SystemZ_FeatureMessageSecurityAssist3 = 1ULL << 15, SystemZ_FeatureMessageSecurityAssist4 = 1ULL << 16, SystemZ_FeatureMessageSecurityAssist5 = 1ULL << 17, SystemZ_FeatureMessageSecurityAssist7 = 1ULL << 18, SystemZ_FeatureMessageSecurityAssist8 = 1ULL << 19, SystemZ_FeatureMiscellaneousExtensions = 1ULL << 20, SystemZ_FeatureMiscellaneousExtensions2 = 1ULL << 21, SystemZ_FeaturePopulationCount = 1ULL << 22, SystemZ_FeatureProcessorAssist = 1ULL << 23, SystemZ_FeatureResetReferenceBitsMultiple = 1ULL << 24, SystemZ_FeatureTransactionalExecution = 1ULL << 25, SystemZ_FeatureVector = 1ULL << 26, SystemZ_FeatureVectorEnhancements1 = 1ULL << 27, SystemZ_FeatureVectorPackedDecimal = 1ULL << 28, }; #endif // GET_SUBTARGETINFO_ENUM capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZInstPrinter.c000064400000000000000000000347270072674642500225370ustar 00000000000000//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax --------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an SystemZ MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SYSZ #include #include #include #include #include "SystemZInstPrinter.h" #include "../../MCInst.h" #include "../../utils.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" #include "SystemZMapping.h" static const char *getRegisterName(unsigned RegNo); void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { /* if (((cs_struct *)ud)->detail != CS_OPT_ON) return; */ } static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O) { printInt64(O, Disp); if (Base) { SStream_concat0(O, "("); if (Index) SStream_concat(O, "%%%s, ", getRegisterName(Index)); SStream_concat(O, "%%%s)", getRegisterName(Base)); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; MI->flat_insn->detail->sysz.op_count++; } } else if (!Index) { if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; MI->flat_insn->detail->sysz.op_count++; } } else { SStream_concat(O, "(%%%s)", getRegisterName(Index)); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; MI->flat_insn->detail->sysz.op_count++; } } } static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) { if (MCOperand_isReg(MO)) { unsigned reg; reg = MCOperand_getReg(MO); SStream_concat(O, "%%%s", getRegisterName(reg)); reg = SystemZ_map_register(reg); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg; MI->flat_insn->detail->sysz.op_count++; } } else if (MCOperand_isImm(MO)) { int64_t Imm = MCOperand_getImm(MO); printInt64(O, Imm); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm; MI->flat_insn->detail->sysz.op_count++; } } } static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<1>(Value) && "Invalid u1imm argument"); printInt64(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<2>(Value) && "Invalid u2imm argument"); printInt64(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<3>(Value) && "Invalid u4imm argument"); printInt64(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<4>(Value) && "Invalid u4imm argument"); printInt64(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O) { uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<6>(Value) && "Invalid u6imm argument"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O) { int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isInt<8>(Value) && "Invalid s8imm argument"); if (Value >= 0) { if (Value > HEX_THRESHOLD) SStream_concat(O, "0x%x", Value); else SStream_concat(O, "%u", Value); } else { if (Value < -HEX_THRESHOLD) SStream_concat(O, "-0x%x", -Value); else SStream_concat(O, "-%u", -Value); } if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O) { uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<8>(Value) && "Invalid u8imm argument"); if (Value > HEX_THRESHOLD) SStream_concat(O, "0x%x", Value); else SStream_concat(O, "%u", Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<12>(Value) && "Invalid u12imm argument"); printInt64(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; MI->flat_insn->detail->sysz.op_count++; } } static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O) { int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isInt<16>(Value) && "Invalid s16imm argument"); if (Value >= 0) { if (Value > HEX_THRESHOLD) SStream_concat(O, "0x%x", Value); else SStream_concat(O, "%u", Value); } else { if (Value < -HEX_THRESHOLD) SStream_concat(O, "-0x%x", -Value); else SStream_concat(O, "-%u", -Value); } if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O) { uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<16>(Value) && "Invalid u16imm argument"); if (Value > HEX_THRESHOLD) SStream_concat(O, "0x%x", Value); else SStream_concat(O, "%u", Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O) { int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isInt<32>(Value) && "Invalid s32imm argument"); printInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O) { uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<32>(Value) && "Invalid u32imm argument"); printUInt32(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value; MI->flat_insn->detail->sysz.op_count++; } } static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O) { int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(isUInt<48>(Value) && "Invalid u48imm argument"); printInt64(O, Value); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value; MI->flat_insn->detail->sysz.op_count++; } } static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { int64_t imm = (int64_t)MCOperand_getImm(MO); printInt64(O, imm); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = imm; MI->flat_insn->detail->sysz.op_count++; } } } static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O) { // Output the PC-relative operand. printPCRelOperand(MI, OpNum, O); } static void printOperand(MCInst *MI, int OpNum, SStream *O) { _printOperand(MI, MCInst_getOperand(MI, OpNum), O); } static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O) { printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O); } static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) { printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); } static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) { unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)); if (Disp > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, Disp); else SStream_concat(O, "%"PRIu64, Disp); if (Length > HEX_THRESHOLD) SStream_concat(O, "(0x%"PRIx64, Length); else SStream_concat(O, "(%"PRIu64, Length); if (Base) SStream_concat(O, ", %%%s", getRegisterName(Base)); SStream_concat0(O, ")"); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; MI->flat_insn->detail->sysz.op_count++; } } static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) { unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)); if (Disp > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, Disp); else SStream_concat(O, "%"PRIu64, Disp); SStream_concat0(O, "("); SStream_concat(O, "%%%s", getRegisterName(Length)); if (Base) SStream_concat(O, ", %%%s", getRegisterName(Base)); SStream_concat0(O, ")"); if (MI->csh->detail) { MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register(Length); MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp; MI->flat_insn->detail->sysz.op_count++; } } static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) { printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)), MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O); } static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) { static const char *const CondNames[] = { "o", "h", "nle", "l", "nhe", "lh", "ne", "e", "nlh", "he", "nl", "le", "nh", "no" }; uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); // assert(Imm > 0 && Imm < 15 && "Invalid condition"); SStream_concat0(O, CondNames[Imm - 1]); if (MI->csh->detail) MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm; } #define PRINT_ALIAS_INSTR #include "SystemZGenAsmWriter.inc" void SystemZ_printInst(MCInst *MI, SStream *O, void *Info) { printInstruction(MI, O, Info); } #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZInstPrinter.h000064400000000000000000000006020072674642500225250ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SYSZINSTPRINTER_H #define CS_SYSZINSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void SystemZ_printInst(MCInst *MI, SStream *O, void *Info); void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZMCTargetDesc.c000064400000000000000000000135010072674642500225060ustar 00000000000000//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SYSZ #include #include "SystemZMCTargetDesc.h" #define GET_REGINFO_ENUM #include "SystemZGenRegisterInfo.inc" const unsigned SystemZMC_GR32Regs[16] = { SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L, SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L, SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L }; const unsigned SystemZMC_GRH32Regs[16] = { SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H, SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H, SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H }; const unsigned SystemZMC_GR64Regs[16] = { SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D }; const unsigned SystemZMC_GR128Regs[16] = { SystemZ_R0Q, 0, SystemZ_R2Q, 0, SystemZ_R4Q, 0, SystemZ_R6Q, 0, SystemZ_R8Q, 0, SystemZ_R10Q, 0, SystemZ_R12Q, 0, SystemZ_R14Q, 0 }; const unsigned SystemZMC_FP32Regs[16] = { SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S }; const unsigned SystemZMC_FP64Regs[16] = { SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D }; const unsigned SystemZMC_FP128Regs[16] = { SystemZ_F0Q, SystemZ_F1Q, 0, 0, SystemZ_F4Q, SystemZ_F5Q, 0, 0, SystemZ_F8Q, SystemZ_F9Q, 0, 0, SystemZ_F12Q, SystemZ_F13Q, 0, 0 }; const unsigned SystemZMC_VR32Regs[32] = { SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S }; const unsigned SystemZMC_VR64Regs[32] = { SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D }; const unsigned SystemZMC_VR128Regs[32] = { SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31 }; const unsigned SystemZMC_AR32Regs[16] = { SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15 }; const unsigned SystemZMC_CR64Regs[16] = { SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15 }; /* All register classes that have 0-15. */ #define DEF_REG16(N) \ [SystemZ_R ## N ## L] = N, \ [SystemZ_R ## N ## H] = N, \ [SystemZ_R ## N ## D] = N, \ [SystemZ_F ## N ## S] = N, \ [SystemZ_F ## N ## D] = N, \ [SystemZ_V ## N] = N, \ [SystemZ_A ## N] = N, \ [SystemZ_C ## N] = N /* All register classes that (also) have 16-31. */ #define DEF_REG32(N) \ [SystemZ_F ## N ## S] = N, \ [SystemZ_F ## N ## D] = N, \ [SystemZ_V ## N] = N static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = { DEF_REG16(0), DEF_REG16(1), DEF_REG16(2), DEF_REG16(3), DEF_REG16(4), DEF_REG16(5), DEF_REG16(6), DEF_REG16(8), DEF_REG16(9), DEF_REG16(10), DEF_REG16(11), DEF_REG16(12), DEF_REG16(13), DEF_REG16(14), DEF_REG16(15), DEF_REG32(16), DEF_REG32(17), DEF_REG32(18), DEF_REG32(19), DEF_REG32(20), DEF_REG32(21), DEF_REG32(22), DEF_REG32(23), DEF_REG32(24), DEF_REG32(25), DEF_REG32(26), DEF_REG32(27), DEF_REG32(28), DEF_REG32(29), DEF_REG32(30), DEF_REG32(31), /* The float Q registers are non-sequential. */ [SystemZ_F0Q] = 0, [SystemZ_F1Q] = 1, [SystemZ_F4Q] = 4, [SystemZ_F5Q] = 5, [SystemZ_F8Q] = 8, [SystemZ_F9Q] = 9, [SystemZ_F12Q] = 12, [SystemZ_F13Q] = 13, /* The integer Q registers are all even. */ [SystemZ_R0Q] = 0, [SystemZ_R2Q] = 2, [SystemZ_R4Q] = 4, [SystemZ_R6Q] = 6, [SystemZ_R8Q] = 8, [SystemZ_R10Q] = 10, [SystemZ_R12Q] = 12, [SystemZ_R14Q] = 14, }; unsigned SystemZMC_getFirstReg(unsigned Reg) { // assert(Reg < SystemZ_NUM_TARGET_REGS); return Map[Reg]; } #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZMCTargetDesc.h000064400000000000000000000037230072674642500225200ustar 00000000000000//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SYSTEMZMCTARGETDESC_H #define CS_SYSTEMZMCTARGETDESC_H // Maps of asm register numbers to LLVM register numbers, with 0 indicating // an invalid register. In principle we could use 32-bit and 64-bit register // classes directly, provided that we relegated the GPR allocation order // in SystemZRegisterInfo.td to an AltOrder and left the default order // as %r0-%r15. It seems better to provide the same interface for // all classes though. extern const unsigned SystemZMC_GR32Regs[16]; extern const unsigned SystemZMC_GRH32Regs[16]; extern const unsigned SystemZMC_GR64Regs[16]; extern const unsigned SystemZMC_GR128Regs[16]; extern const unsigned SystemZMC_FP32Regs[16]; extern const unsigned SystemZMC_FP64Regs[16]; extern const unsigned SystemZMC_FP128Regs[16]; extern const unsigned SystemZMC_VR32Regs[32]; extern const unsigned SystemZMC_VR64Regs[32]; extern const unsigned SystemZMC_VR128Regs[32]; extern const unsigned SystemZMC_AR32Regs[16]; extern const unsigned SystemZMC_CR64Regs[16]; // Return the 0-based number of the first architectural register that // contains the given LLVM register. E.g. R1D -> 1. unsigned SystemZMC_getFirstReg(unsigned Reg); // Defines symbolic names for SystemZ registers. // This defines a mapping from register name to register number. //#define GET_REGINFO_ENUM //#include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. //#define GET_INSTRINFO_ENUM //#include "SystemZGenInstrInfo.inc" //#define GET_SUBTARGETINFO_ENUM //#include "SystemZGenSubtargetInfo.inc" #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZMapping.c000064400000000000000000000350540072674642500216430ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SYSZ #include // debug #include #include "../../utils.h" #include "SystemZMapping.h" #define GET_INSTRINFO_ENUM #include "SystemZGenInstrInfo.inc" #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { { SYSZ_REG_INVALID, NULL }, { SYSZ_REG_0, "0" }, { SYSZ_REG_1, "1" }, { SYSZ_REG_2, "2" }, { SYSZ_REG_3, "3" }, { SYSZ_REG_4, "4" }, { SYSZ_REG_5, "5" }, { SYSZ_REG_6, "6" }, { SYSZ_REG_7, "7" }, { SYSZ_REG_8, "8" }, { SYSZ_REG_9, "9" }, { SYSZ_REG_10, "10" }, { SYSZ_REG_11, "11" }, { SYSZ_REG_12, "12" }, { SYSZ_REG_13, "13" }, { SYSZ_REG_14, "14" }, { SYSZ_REG_15, "15" }, { SYSZ_REG_CC, "cc"}, { SYSZ_REG_F0, "f0" }, { SYSZ_REG_F1, "f1" }, { SYSZ_REG_F2, "f2" }, { SYSZ_REG_F3, "f3" }, { SYSZ_REG_F4, "f4" }, { SYSZ_REG_F5, "f5" }, { SYSZ_REG_F6, "f6" }, { SYSZ_REG_F7, "f7" }, { SYSZ_REG_F8, "f8" }, { SYSZ_REG_F9, "f9" }, { SYSZ_REG_F10, "f10" }, { SYSZ_REG_F11, "f11" }, { SYSZ_REG_F12, "f12" }, { SYSZ_REG_F13, "f13" }, { SYSZ_REG_F14, "f14" }, { SYSZ_REG_F15, "f15" }, { SYSZ_REG_R0L, "r0l" }, { SYSZ_REG_A0, "a0" }, { SYSZ_REG_A1, "a1" }, { SYSZ_REG_A2, "a2" }, { SYSZ_REG_A3, "a3" }, { SYSZ_REG_A4, "a4" }, { SYSZ_REG_A5, "a5" }, { SYSZ_REG_A6, "a6" }, { SYSZ_REG_A7, "a7" }, { SYSZ_REG_A8, "a8" }, { SYSZ_REG_A9, "a9" }, { SYSZ_REG_A10, "a10" }, { SYSZ_REG_A11, "a11" }, { SYSZ_REG_A12, "a12" }, { SYSZ_REG_A13, "a13" }, { SYSZ_REG_A14, "a14" }, { SYSZ_REG_A15, "a15" }, { SYSZ_REG_C0, "c0" }, { SYSZ_REG_C1, "c1" }, { SYSZ_REG_C2, "c2" }, { SYSZ_REG_C3, "c3" }, { SYSZ_REG_C4, "c4" }, { SYSZ_REG_C5, "c5" }, { SYSZ_REG_C6, "c6" }, { SYSZ_REG_C7, "c7" }, { SYSZ_REG_C8, "c8" }, { SYSZ_REG_C9, "c9" }, { SYSZ_REG_C10, "c10" }, { SYSZ_REG_C11, "c11" }, { SYSZ_REG_C12, "c12" }, { SYSZ_REG_C13, "c13" }, { SYSZ_REG_C14, "c14" }, { SYSZ_REG_C15, "c15" }, { SYSZ_REG_V0, "v0" }, { SYSZ_REG_V1, "v1" }, { SYSZ_REG_V2, "v2" }, { SYSZ_REG_V3, "v3" }, { SYSZ_REG_V4, "v4" }, { SYSZ_REG_V5, "v5" }, { SYSZ_REG_V6, "v6" }, { SYSZ_REG_V7, "v7" }, { SYSZ_REG_V8, "v8" }, { SYSZ_REG_V9, "v9" }, { SYSZ_REG_V10, "v10" }, { SYSZ_REG_V11, "v11" }, { SYSZ_REG_V12, "v12" }, { SYSZ_REG_V13, "v13" }, { SYSZ_REG_V14, "v14" }, { SYSZ_REG_V15, "v15" }, { SYSZ_REG_V16, "v16" }, { SYSZ_REG_V17, "v17" }, { SYSZ_REG_V18, "v18" }, { SYSZ_REG_V19, "v19" }, { SYSZ_REG_V20, "v20" }, { SYSZ_REG_V21, "v21" }, { SYSZ_REG_V22, "v22" }, { SYSZ_REG_V23, "v23" }, { SYSZ_REG_V24, "v24" }, { SYSZ_REG_V25, "v25" }, { SYSZ_REG_V26, "v26" }, { SYSZ_REG_V27, "v27" }, { SYSZ_REG_V28, "v28" }, { SYSZ_REG_V29, "v29" }, { SYSZ_REG_V30, "v30" }, { SYSZ_REG_V31, "v31" }, { SYSZ_REG_F16, "f16" }, { SYSZ_REG_F17, "f17" }, { SYSZ_REG_F18, "f18" }, { SYSZ_REG_F19, "f19" }, { SYSZ_REG_F20, "f20" }, { SYSZ_REG_F21, "f21" }, { SYSZ_REG_F22, "f22" }, { SYSZ_REG_F23, "f23" }, { SYSZ_REG_F24, "f24" }, { SYSZ_REG_F25, "f25" }, { SYSZ_REG_F26, "f26" }, { SYSZ_REG_F27, "f27" }, { SYSZ_REG_F28, "f28" }, { SYSZ_REG_F29, "f29" }, { SYSZ_REG_F30, "f30" }, { SYSZ_REG_F31, "f31" }, { SYSZ_REG_F0Q, "f0q" }, { SYSZ_REG_F4Q, "f4q" }, }; #endif const char *SystemZ_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "SystemZMappingInsn.inc" }; // given internal insn id, return public instruction info void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned short i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = SYSZ_GRP_JUMP; insn->detail->groups_count++; } #endif } } } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[] = { { SYSZ_INS_INVALID, NULL }, #include "SystemZGenInsnNameMaps.inc" }; // special alias insn static const name_map alias_insn_names[] = { { 0, NULL } }; #endif const char *SystemZ_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET unsigned int i; if (id >= SYSZ_INS_ENDING) return NULL; // handle special alias first for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { if (alias_insn_names[i].id == id) return alias_insn_names[i].name; } return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { SYSZ_GRP_INVALID, NULL }, { SYSZ_GRP_JUMP, "jump" }, // architecture-specific groups { SYSZ_GRP_DFPPACKEDCONVERSION, "dfppackedconversion" }, { SYSZ_GRP_DFPZONEDCONVERSION, "dfpzonedconversion" }, { SYSZ_GRP_DISTINCTOPS, "distinctops" }, { SYSZ_GRP_ENHANCEDDAT2, "enhanceddat2" }, { SYSZ_GRP_EXECUTIONHINT, "executionhint" }, { SYSZ_GRP_FPEXTENSION, "fpextension" }, { SYSZ_GRP_GUARDEDSTORAGE, "guardedstorage" }, { SYSZ_GRP_HIGHWORD, "highword" }, { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, "insertreferencebitsmultiple" }, { SYSZ_GRP_INTERLOCKEDACCESS1, "interlockedaccess1" }, { SYSZ_GRP_LOADANDTRAP, "loadandtrap" }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, "loadandzerorightmostbyte" }, { SYSZ_GRP_LOADSTOREONCOND, "loadstoreoncond" }, { SYSZ_GRP_LOADSTOREONCOND2, "loadstoreoncond2" }, { SYSZ_GRP_MESSAGESECURITYASSIST3, "messagesecurityassist3" }, { SYSZ_GRP_MESSAGESECURITYASSIST4, "messagesecurityassist4" }, { SYSZ_GRP_MESSAGESECURITYASSIST5, "messagesecurityassist5" }, { SYSZ_GRP_MESSAGESECURITYASSIST7, "messagesecurityassist7" }, { SYSZ_GRP_MESSAGESECURITYASSIST8, "messagesecurityassist8" }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, "miscellaneousextensions" }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, "miscellaneousextensions2" }, { SYSZ_GRP_POPULATIONCOUNT, "populationcount" }, { SYSZ_GRP_PROCESSORASSIST, "processorassist" }, { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, "resetreferencebitsmultiple" }, { SYSZ_GRP_TRANSACTIONALEXECUTION, "transactionalexecution" }, { SYSZ_GRP_VECTOR, "vector" }, { SYSZ_GRP_VECTORENHANCEMENTS1, "vectorenhancements1" }, { SYSZ_GRP_VECTORPACKEDDECIMAL, "vectorpackeddecimal" }, }; #endif const char *SystemZ_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // map internal raw register to 'public' register sysz_reg SystemZ_map_register(unsigned int r) { static const unsigned int map[] = { 0, /* SystemZ_CC = 1 */ SYSZ_REG_CC, /* SystemZ_A0 = 2 */ SYSZ_REG_A0, /* SystemZ_A1 = 3 */ SYSZ_REG_A1, /* SystemZ_A2 = 4 */ SYSZ_REG_A2, /* SystemZ_A3 = 5 */ SYSZ_REG_A3, /* SystemZ_A4 = 6 */ SYSZ_REG_A4, /* SystemZ_A5 = 7 */ SYSZ_REG_A5, /* SystemZ_A6 = 8 */ SYSZ_REG_A6, /* SystemZ_A7 = 9 */ SYSZ_REG_A7, /* SystemZ_A8 = 10 */ SYSZ_REG_A8, /* SystemZ_A9 = 11 */ SYSZ_REG_A9, /* SystemZ_A10 = 12 */ SYSZ_REG_A10, /* SystemZ_A11 = 13 */ SYSZ_REG_A11, /* SystemZ_A12 = 14 */ SYSZ_REG_A12, /* SystemZ_A13 = 15 */ SYSZ_REG_A13, /* SystemZ_A14 = 16 */ SYSZ_REG_A14, /* SystemZ_A15 = 17 */ SYSZ_REG_A15, /* SystemZ_C0 = 18 */ SYSZ_REG_C0, /* SystemZ_C1 = 19 */ SYSZ_REG_C1, /* SystemZ_C2 = 20 */ SYSZ_REG_C2, /* SystemZ_C3 = 21 */ SYSZ_REG_C3, /* SystemZ_C4 = 22 */ SYSZ_REG_C4, /* SystemZ_C5 = 23 */ SYSZ_REG_C5, /* SystemZ_C6 = 24 */ SYSZ_REG_C6, /* SystemZ_C7 = 25 */ SYSZ_REG_C7, /* SystemZ_C8 = 26 */ SYSZ_REG_C8, /* SystemZ_C9 = 27 */ SYSZ_REG_C9, /* SystemZ_C10 = 28 */ SYSZ_REG_C10, /* SystemZ_C11 = 29 */ SYSZ_REG_C11, /* SystemZ_C12 = 30 */ SYSZ_REG_C12, /* SystemZ_C13 = 31 */ SYSZ_REG_C13, /* SystemZ_C14 = 32 */ SYSZ_REG_C14, /* SystemZ_C15 = 33 */ SYSZ_REG_C15, /* SystemZ_V0 = 34 */ SYSZ_REG_V0, /* SystemZ_V1 = 35 */ SYSZ_REG_V1, /* SystemZ_V2 = 36 */ SYSZ_REG_V2, /* SystemZ_V3 = 37 */ SYSZ_REG_V3, /* SystemZ_V4 = 38 */ SYSZ_REG_V4, /* SystemZ_V5 = 39 */ SYSZ_REG_V5, /* SystemZ_V6 = 40 */ SYSZ_REG_V6, /* SystemZ_V7 = 41 */ SYSZ_REG_V7, /* SystemZ_V8 = 42 */ SYSZ_REG_V8, /* SystemZ_V9 = 43 */ SYSZ_REG_V9, /* SystemZ_V10 = 44 */ SYSZ_REG_V10, /* SystemZ_V11 = 45 */ SYSZ_REG_V11, /* SystemZ_V12 = 46 */ SYSZ_REG_V12, /* SystemZ_V13 = 47 */ SYSZ_REG_V13, /* SystemZ_V14 = 48 */ SYSZ_REG_V14, /* SystemZ_V15 = 49 */ SYSZ_REG_V15, /* SystemZ_V16 = 50 */ SYSZ_REG_V16, /* SystemZ_V17 = 51 */ SYSZ_REG_V17, /* SystemZ_V18 = 52 */ SYSZ_REG_V18, /* SystemZ_V19 = 53 */ SYSZ_REG_V19, /* SystemZ_V20 = 54 */ SYSZ_REG_V20, /* SystemZ_V21 = 55 */ SYSZ_REG_V21, /* SystemZ_V22 = 56 */ SYSZ_REG_V22, /* SystemZ_V23 = 57 */ SYSZ_REG_V23, /* SystemZ_V24 = 58 */ SYSZ_REG_V24, /* SystemZ_V25 = 59 */ SYSZ_REG_V25, /* SystemZ_V26 = 60 */ SYSZ_REG_V26, /* SystemZ_V27 = 61 */ SYSZ_REG_V27, /* SystemZ_V28 = 62 */ SYSZ_REG_V28, /* SystemZ_V29 = 63 */ SYSZ_REG_V29, /* SystemZ_V30 = 64 */ SYSZ_REG_V30, /* SystemZ_V31 = 65 */ SYSZ_REG_V31, /* SystemZ_F0D = 66 */ SYSZ_REG_F0, /* SystemZ_F1D = 67 */ SYSZ_REG_F1, /* SystemZ_F2D = 68 */ SYSZ_REG_F2, /* SystemZ_F3D = 69 */ SYSZ_REG_F3, /* SystemZ_F4D = 70 */ SYSZ_REG_F4, /* SystemZ_F5D = 71 */ SYSZ_REG_F5, /* SystemZ_F6D = 72 */ SYSZ_REG_F6, /* SystemZ_F7D = 73 */ SYSZ_REG_F7, /* SystemZ_F8D = 74 */ SYSZ_REG_F8, /* SystemZ_F9D = 75 */ SYSZ_REG_F9, /* SystemZ_F10D = 76 */ SYSZ_REG_F10, /* SystemZ_F11D = 77 */ SYSZ_REG_F11, /* SystemZ_F12D = 78 */ SYSZ_REG_F12, /* SystemZ_F13D = 79 */ SYSZ_REG_F13, /* SystemZ_F14D = 80 */ SYSZ_REG_F14, /* SystemZ_F15D = 81 */ SYSZ_REG_F15, /* SystemZ_F16D = 82 */ SYSZ_REG_F16, /* SystemZ_F17D = 83 */ SYSZ_REG_F17, /* SystemZ_F18D = 84 */ SYSZ_REG_F18, /* SystemZ_F19D = 85 */ SYSZ_REG_F19, /* SystemZ_F20D = 86 */ SYSZ_REG_F20, /* SystemZ_F21D = 87 */ SYSZ_REG_F21, /* SystemZ_F22D = 88 */ SYSZ_REG_F22, /* SystemZ_F23D = 89 */ SYSZ_REG_F23, /* SystemZ_F24D = 90 */ SYSZ_REG_F24, /* SystemZ_F25D = 91 */ SYSZ_REG_F25, /* SystemZ_F26D = 92 */ SYSZ_REG_F26, /* SystemZ_F27D = 93 */ SYSZ_REG_F27, /* SystemZ_F28D = 94 */ SYSZ_REG_F28, /* SystemZ_F29D = 95 */ SYSZ_REG_F29, /* SystemZ_F30D = 96 */ SYSZ_REG_F30, /* SystemZ_F31D = 97 */ SYSZ_REG_F31, /* SystemZ_F0Q = 98 */ SYSZ_REG_F0, /* SystemZ_F1Q = 99 */ SYSZ_REG_F1, /* SystemZ_F4Q = 100 */ SYSZ_REG_F4, /* SystemZ_F5Q = 101 */ SYSZ_REG_F5, /* SystemZ_F8Q = 102 */ SYSZ_REG_F8, /* SystemZ_F9Q = 103 */ SYSZ_REG_F9, /* SystemZ_F12Q = 104 */ SYSZ_REG_F12, /* SystemZ_F13Q = 105 */ SYSZ_REG_F13, /* SystemZ_F0S = 106 */ SYSZ_REG_F0, /* SystemZ_F1S = 107 */ SYSZ_REG_F1, /* SystemZ_F2S = 108 */ SYSZ_REG_F2, /* SystemZ_F3S = 109 */ SYSZ_REG_F3, /* SystemZ_F4S = 110 */ SYSZ_REG_F4, /* SystemZ_F5S = 111 */ SYSZ_REG_F5, /* SystemZ_F6S = 112 */ SYSZ_REG_F6, /* SystemZ_F7S = 113 */ SYSZ_REG_F7, /* SystemZ_F8S = 114 */ SYSZ_REG_F8, /* SystemZ_F9S = 115 */ SYSZ_REG_F9, /* SystemZ_F10S = 116 */ SYSZ_REG_F10, /* SystemZ_F11S = 117 */ SYSZ_REG_F11, /* SystemZ_F12S = 118 */ SYSZ_REG_F12, /* SystemZ_F13S = 119 */ SYSZ_REG_F13, /* SystemZ_F14S = 120 */ SYSZ_REG_F14, /* SystemZ_F15S = 121 */ SYSZ_REG_F15, /* SystemZ_F16S = 122 */ SYSZ_REG_F16, /* SystemZ_F17S = 123 */ SYSZ_REG_F17, /* SystemZ_F18S = 124 */ SYSZ_REG_F18, /* SystemZ_F19S = 125 */ SYSZ_REG_F19, /* SystemZ_F20S = 126 */ SYSZ_REG_F20, /* SystemZ_F21S = 127 */ SYSZ_REG_F21, /* SystemZ_F22S = 128 */ SYSZ_REG_F22, /* SystemZ_F23S = 129 */ SYSZ_REG_F23, /* SystemZ_F24S = 130 */ SYSZ_REG_F24, /* SystemZ_F25S = 131 */ SYSZ_REG_F25, /* SystemZ_F26S = 132 */ SYSZ_REG_F26, /* SystemZ_F27S = 133 */ SYSZ_REG_F27, /* SystemZ_F28S = 134 */ SYSZ_REG_F28, /* SystemZ_F29S = 135 */ SYSZ_REG_F29, /* SystemZ_F30S = 136 */ SYSZ_REG_F30, /* SystemZ_F31S = 137 */ SYSZ_REG_F31, /* SystemZ_R0D = 138 */ SYSZ_REG_0, /* SystemZ_R1D = 139 */ SYSZ_REG_1, /* SystemZ_R2D = 140 */ SYSZ_REG_2, /* SystemZ_R3D = 141 */ SYSZ_REG_3, /* SystemZ_R4D = 142 */ SYSZ_REG_4, /* SystemZ_R5D = 143 */ SYSZ_REG_5, /* SystemZ_R6D = 144 */ SYSZ_REG_6, /* SystemZ_R7D = 145 */ SYSZ_REG_7, /* SystemZ_R8D = 146 */ SYSZ_REG_8, /* SystemZ_R9D = 147 */ SYSZ_REG_9, /* SystemZ_R10D = 148 */ SYSZ_REG_10, /* SystemZ_R11D = 149 */ SYSZ_REG_11, /* SystemZ_R12D = 150 */ SYSZ_REG_12, /* SystemZ_R13D = 151 */ SYSZ_REG_13, /* SystemZ_R14D = 152 */ SYSZ_REG_14, /* SystemZ_R15D = 153 */ SYSZ_REG_15, /* SystemZ_R0H = 154 */ SYSZ_REG_0, /* SystemZ_R1H = 155 */ SYSZ_REG_1, /* SystemZ_R2H = 156 */ SYSZ_REG_2, /* SystemZ_R3H = 157 */ SYSZ_REG_3, /* SystemZ_R4H = 158 */ SYSZ_REG_4, /* SystemZ_R5H = 159 */ SYSZ_REG_5, /* SystemZ_R6H = 160 */ SYSZ_REG_6, /* SystemZ_R7H = 161 */ SYSZ_REG_7, /* SystemZ_R8H = 162 */ SYSZ_REG_8, /* SystemZ_R9H = 163 */ SYSZ_REG_9, /* SystemZ_R10H = 164 */ SYSZ_REG_10, /* SystemZ_R11H = 165 */ SYSZ_REG_11, /* SystemZ_R12H = 166 */ SYSZ_REG_12, /* SystemZ_R13H = 167 */ SYSZ_REG_13, /* SystemZ_R14H = 168 */ SYSZ_REG_14, /* SystemZ_R15H = 169 */ SYSZ_REG_15, /* SystemZ_R0L = 170 */ SYSZ_REG_0, /* SystemZ_R1L = 171 */ SYSZ_REG_1, /* SystemZ_R2L = 172 */ SYSZ_REG_2, /* SystemZ_R3L = 173 */ SYSZ_REG_3, /* SystemZ_R4L = 174 */ SYSZ_REG_4, /* SystemZ_R5L = 175 */ SYSZ_REG_5, /* SystemZ_R6L = 176 */ SYSZ_REG_6, /* SystemZ_R7L = 177 */ SYSZ_REG_7, /* SystemZ_R8L = 178 */ SYSZ_REG_8, /* SystemZ_R9L = 179 */ SYSZ_REG_9, /* SystemZ_R10L = 180 */ SYSZ_REG_10, /* SystemZ_R11L = 181 */ SYSZ_REG_11, /* SystemZ_R12L = 182 */ SYSZ_REG_12, /* SystemZ_R13L = 183 */ SYSZ_REG_13, /* SystemZ_R14L = 184 */ SYSZ_REG_14, /* SystemZ_R15L = 185 */ SYSZ_REG_15, /* SystemZ_R0Q = 186 */ SYSZ_REG_0, /* SystemZ_R2Q = 187 */ SYSZ_REG_2, /* SystemZ_R4Q = 188 */ SYSZ_REG_4, /* SystemZ_R6Q = 189 */ SYSZ_REG_6, /* SystemZ_R8Q = 190 */ SYSZ_REG_8, /* SystemZ_R10Q = 191 */ SYSZ_REG_10, /* SystemZ_R12Q = 192 */ SYSZ_REG_12, /* SystemZ_R14Q = 193 */ SYSZ_REG_14, }; if (r < ARR_SIZE(map)) return map[r]; // cannot find this register return 0; } #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZMapping.h000064400000000000000000000011720072674642500216420ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_SYSZ_MAP_H #define CS_SYSZ_MAP_H #include "capstone/capstone.h" // return name of regiser in friendly string const char *SystemZ_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *SystemZ_insn_name(csh handle, unsigned int id); const char *SystemZ_group_name(csh handle, unsigned int id); // map internal raw register to 'public' register sysz_reg SystemZ_map_register(unsigned int r); #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZMappingInsn.inc000064400000000000000000010011000072674642500230040ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { SystemZ_A, SYSZ_INS_A, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AD, SYSZ_INS_AD, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ADB, SYSZ_INS_ADB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ADBR, SYSZ_INS_ADBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ADR, SYSZ_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ADTR, SYSZ_INS_ADTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ADTRA, SYSZ_INS_ADTRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_AE, SYSZ_INS_AE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AEB, SYSZ_INS_AEB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AEBR, SYSZ_INS_AEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AER, SYSZ_INS_AER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AFI, SYSZ_INS_AFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AG, SYSZ_INS_AG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AGF, SYSZ_INS_AGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AGFI, SYSZ_INS_AGFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AGFR, SYSZ_INS_AGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AGH, SYSZ_INS_AGH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_AGHI, SYSZ_INS_AGHI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AGHIK, SYSZ_INS_AGHIK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_AGR, SYSZ_INS_AGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AGRK, SYSZ_INS_AGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_AGSI, SYSZ_INS_AGSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AH, SYSZ_INS_AH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AHHHR, SYSZ_INS_AHHHR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_AHHLR, SYSZ_INS_AHHLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_AHI, SYSZ_INS_AHI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AHIK, SYSZ_INS_AHIK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_AHY, SYSZ_INS_AHY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AIH, SYSZ_INS_AIH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_AL, SYSZ_INS_AL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALC, SYSZ_INS_ALC, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALCG, SYSZ_INS_ALCG, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALCGR, SYSZ_INS_ALCGR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALCR, SYSZ_INS_ALCR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALFI, SYSZ_INS_ALFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALG, SYSZ_INS_ALG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALGF, SYSZ_INS_ALGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALGFI, SYSZ_INS_ALGFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALGFR, SYSZ_INS_ALGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALGHSIK, SYSZ_INS_ALGHSIK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_ALGR, SYSZ_INS_ALGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALGRK, SYSZ_INS_ALGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_ALGSI, SYSZ_INS_ALGSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALHHHR, SYSZ_INS_ALHHHR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_ALHHLR, SYSZ_INS_ALHHLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_ALHSIK, SYSZ_INS_ALHSIK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_ALR, SYSZ_INS_ALR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALRK, SYSZ_INS_ALRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_ALSI, SYSZ_INS_ALSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ALSIH, SYSZ_INS_ALSIH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_ALSIHN, SYSZ_INS_ALSIHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_ALY, SYSZ_INS_ALY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AP, SYSZ_INS_AP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AR, SYSZ_INS_AR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ARK, SYSZ_INS_ARK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_ASI, SYSZ_INS_ASI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AU, SYSZ_INS_AU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AUR, SYSZ_INS_AUR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AW, SYSZ_INS_AW, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AWR, SYSZ_INS_AWR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AXBR, SYSZ_INS_AXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AXR, SYSZ_INS_AXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AXTR, SYSZ_INS_AXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_AXTRA, SYSZ_INS_AXTRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_AY, SYSZ_INS_AY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_B, SYSZ_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAKR, SYSZ_INS_BAKR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BAL, SYSZ_INS_BAL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BALR, SYSZ_INS_BALR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BAS, SYSZ_INS_BAS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BASR, SYSZ_INS_BASR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BASSM, SYSZ_INS_BASSM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BAsmE, SYSZ_INS_BE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmH, SYSZ_INS_BH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmHE, SYSZ_INS_BHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmL, SYSZ_INS_BL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmLE, SYSZ_INS_BLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmLH, SYSZ_INS_BLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmM, SYSZ_INS_BM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNE, SYSZ_INS_BNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNH, SYSZ_INS_BNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNHE, SYSZ_INS_BNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNL, SYSZ_INS_BNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNLE, SYSZ_INS_BNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNLH, SYSZ_INS_BNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNM, SYSZ_INS_BNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNO, SYSZ_INS_BNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNP, SYSZ_INS_BNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmNZ, SYSZ_INS_BNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmO, SYSZ_INS_BO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmP, SYSZ_INS_BP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BAsmZ, SYSZ_INS_BZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BCAsm, SYSZ_INS_BC, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BCRAsm, SYSZ_INS_BCR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BCT, SYSZ_INS_BCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BCTG, SYSZ_INS_BCTG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BCTGR, SYSZ_INS_BCTGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BCTR, SYSZ_INS_BCTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BI, SYSZ_INS_BI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmE, SYSZ_INS_BIE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmH, SYSZ_INS_BIH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmHE, SYSZ_INS_BIHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmL, SYSZ_INS_BIL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmLE, SYSZ_INS_BILE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmLH, SYSZ_INS_BILH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmM, SYSZ_INS_BIM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNE, SYSZ_INS_BINE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNH, SYSZ_INS_BINH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNHE, SYSZ_INS_BINHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNL, SYSZ_INS_BINL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNLE, SYSZ_INS_BINLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNLH, SYSZ_INS_BINLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNM, SYSZ_INS_BINM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNO, SYSZ_INS_BINO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNP, SYSZ_INS_BINP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmNZ, SYSZ_INS_BINZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmO, SYSZ_INS_BIO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmP, SYSZ_INS_BIP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BIAsmZ, SYSZ_INS_BIZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BICAsm, SYSZ_INS_BIC, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 1, 1 #endif }, { SystemZ_BPP, SYSZ_INS_BPP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 #endif }, { SystemZ_BPRP, SYSZ_INS_BPRP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 #endif }, { SystemZ_BR, SYSZ_INS_BR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAS, SYSZ_INS_BRAS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BRASL, SYSZ_INS_BRASL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BRAsmE, SYSZ_INS_BER, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmH, SYSZ_INS_BHR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmHE, SYSZ_INS_BHER, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmL, SYSZ_INS_BLR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmLE, SYSZ_INS_BLER, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmLH, SYSZ_INS_BLHR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmM, SYSZ_INS_BMR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNE, SYSZ_INS_BNER, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNH, SYSZ_INS_BNHR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNHE, SYSZ_INS_BNHER, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNL, SYSZ_INS_BNLR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNLE, SYSZ_INS_BNLER, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNLH, SYSZ_INS_BNLHR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNM, SYSZ_INS_BNMR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNO, SYSZ_INS_BNOR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNP, SYSZ_INS_BNPR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmNZ, SYSZ_INS_BNZR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmO, SYSZ_INS_BOR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmP, SYSZ_INS_BPR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRAsmZ, SYSZ_INS_BZR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_BRCAsm, SYSZ_INS_BRC, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRCLAsm, SYSZ_INS_BRCL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRCT, SYSZ_INS_BRCT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRCTG, SYSZ_INS_BRCTG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRCTH, SYSZ_INS_BRCTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 1, 0 #endif }, { SystemZ_BRXH, SYSZ_INS_BRXH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRXHG, SYSZ_INS_BRXHG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRXLE, SYSZ_INS_BRXLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BRXLG, SYSZ_INS_BRXLG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BSA, SYSZ_INS_BSA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BSG, SYSZ_INS_BSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_BSM, SYSZ_INS_BSM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BXH, SYSZ_INS_BXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BXHG, SYSZ_INS_BXHG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BXLE, SYSZ_INS_BXLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_BXLEG, SYSZ_INS_BXLEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_C, SYSZ_INS_C, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CD, SYSZ_INS_CD, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDB, SYSZ_INS_CDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDBR, SYSZ_INS_CDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDFBR, SYSZ_INS_CDFBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDFBRA, SYSZ_INS_CDFBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDFR, SYSZ_INS_CDFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDFTR, SYSZ_INS_CDFTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDGBR, SYSZ_INS_CDGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDGBRA, SYSZ_INS_CDGBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDGR, SYSZ_INS_CDGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDGTR, SYSZ_INS_CDGTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDGTRA, SYSZ_INS_CDGTRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDLFBR, SYSZ_INS_CDLFBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDLFTR, SYSZ_INS_CDLFTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDLGBR, SYSZ_INS_CDLGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDLGTR, SYSZ_INS_CDLGTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CDPT, SYSZ_INS_CDPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CDR, SYSZ_INS_CDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDS, SYSZ_INS_CDS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDSG, SYSZ_INS_CDSG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDSTR, SYSZ_INS_CDSTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDSY, SYSZ_INS_CDSY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDTR, SYSZ_INS_CDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDUTR, SYSZ_INS_CDUTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CDZT, SYSZ_INS_CDZT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CE, SYSZ_INS_CE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEB, SYSZ_INS_CEB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEBR, SYSZ_INS_CEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEDTR, SYSZ_INS_CEDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEFBR, SYSZ_INS_CEFBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEFBRA, SYSZ_INS_CEFBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CEFR, SYSZ_INS_CEFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEGBR, SYSZ_INS_CEGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEGBRA, SYSZ_INS_CEGBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CEGR, SYSZ_INS_CEGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CELFBR, SYSZ_INS_CELFBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CELGBR, SYSZ_INS_CELGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CER, SYSZ_INS_CER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CEXTR, SYSZ_INS_CEXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFC, SYSZ_INS_CFC, #ifndef CAPSTONE_DIET { SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFDBR, SYSZ_INS_CFDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFDBRA, SYSZ_INS_CFDBRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CFDR, SYSZ_INS_CFDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFDTR, SYSZ_INS_CFDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CFEBR, SYSZ_INS_CFEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFEBRA, SYSZ_INS_CFEBRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CFER, SYSZ_INS_CFER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFI, SYSZ_INS_CFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFXBR, SYSZ_INS_CFXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFXBRA, SYSZ_INS_CFXBRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CFXR, SYSZ_INS_CFXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CFXTR, SYSZ_INS_CFXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CG, SYSZ_INS_CG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGDBR, SYSZ_INS_CGDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGDBRA, SYSZ_INS_CGDBRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CGDR, SYSZ_INS_CGDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGDTR, SYSZ_INS_CGDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGDTRA, SYSZ_INS_CGDTRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CGEBR, SYSZ_INS_CGEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGEBRA, SYSZ_INS_CGEBRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CGER, SYSZ_INS_CGER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGF, SYSZ_INS_CGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGFI, SYSZ_INS_CGFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGFR, SYSZ_INS_CGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGFRL, SYSZ_INS_CGFRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGH, SYSZ_INS_CGH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGHI, SYSZ_INS_CGHI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGHRL, SYSZ_INS_CGHRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGHSI, SYSZ_INS_CGHSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGIBAsm, SYSZ_INS_CGIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmE, SYSZ_INS_CGIBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmH, SYSZ_INS_CGIBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmHE, SYSZ_INS_CGIBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmL, SYSZ_INS_CGIBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmLE, SYSZ_INS_CGIBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmLH, SYSZ_INS_CGIBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmNE, SYSZ_INS_CGIBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmNH, SYSZ_INS_CGIBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmNHE, SYSZ_INS_CGIBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmNL, SYSZ_INS_CGIBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmNLE, SYSZ_INS_CGIBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIBAsmNLH, SYSZ_INS_CGIBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGIJAsm, SYSZ_INS_CGIJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmE, SYSZ_INS_CGIJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmH, SYSZ_INS_CGIJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmHE, SYSZ_INS_CGIJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmL, SYSZ_INS_CGIJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmLE, SYSZ_INS_CGIJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmLH, SYSZ_INS_CGIJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmNE, SYSZ_INS_CGIJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmNH, SYSZ_INS_CGIJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmNHE, SYSZ_INS_CGIJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmNL, SYSZ_INS_CGIJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmNLE, SYSZ_INS_CGIJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGIJAsmNLH, SYSZ_INS_CGIJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGITAsm, SYSZ_INS_CGIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmE, SYSZ_INS_CGITE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmH, SYSZ_INS_CGITH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmHE, SYSZ_INS_CGITHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmL, SYSZ_INS_CGITL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmLE, SYSZ_INS_CGITLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmLH, SYSZ_INS_CGITLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmNE, SYSZ_INS_CGITNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmNH, SYSZ_INS_CGITNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmNHE, SYSZ_INS_CGITNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmNL, SYSZ_INS_CGITNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmNLE, SYSZ_INS_CGITNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGITAsmNLH, SYSZ_INS_CGITNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGR, SYSZ_INS_CGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRBAsm, SYSZ_INS_CGRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmE, SYSZ_INS_CGRBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmH, SYSZ_INS_CGRBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmHE, SYSZ_INS_CGRBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmL, SYSZ_INS_CGRBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmLE, SYSZ_INS_CGRBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmLH, SYSZ_INS_CGRBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmNE, SYSZ_INS_CGRBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmNH, SYSZ_INS_CGRBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmNHE, SYSZ_INS_CGRBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmNL, SYSZ_INS_CGRBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmNLE, SYSZ_INS_CGRBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRBAsmNLH, SYSZ_INS_CGRBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CGRJAsm, SYSZ_INS_CGRJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmE, SYSZ_INS_CGRJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmH, SYSZ_INS_CGRJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmHE, SYSZ_INS_CGRJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmL, SYSZ_INS_CGRJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmLE, SYSZ_INS_CGRJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmLH, SYSZ_INS_CGRJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmNE, SYSZ_INS_CGRJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmNH, SYSZ_INS_CGRJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmNHE, SYSZ_INS_CGRJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmNL, SYSZ_INS_CGRJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmNLE, SYSZ_INS_CGRJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRJAsmNLH, SYSZ_INS_CGRJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CGRL, SYSZ_INS_CGRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsm, SYSZ_INS_CGRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmE, SYSZ_INS_CGRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmH, SYSZ_INS_CGRTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmHE, SYSZ_INS_CGRTHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmL, SYSZ_INS_CGRTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmLE, SYSZ_INS_CGRTLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmLH, SYSZ_INS_CGRTLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmNE, SYSZ_INS_CGRTNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmNH, SYSZ_INS_CGRTNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmNHE, SYSZ_INS_CGRTNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmNL, SYSZ_INS_CGRTNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmNLE, SYSZ_INS_CGRTNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGRTAsmNLH, SYSZ_INS_CGRTNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGXBR, SYSZ_INS_CGXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGXBRA, SYSZ_INS_CGXBRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CGXR, SYSZ_INS_CGXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGXTR, SYSZ_INS_CGXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CGXTRA, SYSZ_INS_CGXTRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CH, SYSZ_INS_CH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CHF, SYSZ_INS_CHF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CHHR, SYSZ_INS_CHHR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CHHSI, SYSZ_INS_CHHSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CHI, SYSZ_INS_CHI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CHLR, SYSZ_INS_CHLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CHRL, SYSZ_INS_CHRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CHSI, SYSZ_INS_CHSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CHY, SYSZ_INS_CHY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CIBAsm, SYSZ_INS_CIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmE, SYSZ_INS_CIBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmH, SYSZ_INS_CIBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmHE, SYSZ_INS_CIBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmL, SYSZ_INS_CIBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmLE, SYSZ_INS_CIBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmLH, SYSZ_INS_CIBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmNE, SYSZ_INS_CIBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmNH, SYSZ_INS_CIBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmNHE, SYSZ_INS_CIBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmNL, SYSZ_INS_CIBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmNLE, SYSZ_INS_CIBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIBAsmNLH, SYSZ_INS_CIBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CIH, SYSZ_INS_CIH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CIJAsm, SYSZ_INS_CIJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmE, SYSZ_INS_CIJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmH, SYSZ_INS_CIJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmHE, SYSZ_INS_CIJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmL, SYSZ_INS_CIJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmLE, SYSZ_INS_CIJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmLH, SYSZ_INS_CIJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmNE, SYSZ_INS_CIJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmNH, SYSZ_INS_CIJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmNHE, SYSZ_INS_CIJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmNL, SYSZ_INS_CIJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmNLE, SYSZ_INS_CIJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CIJAsmNLH, SYSZ_INS_CIJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CITAsm, SYSZ_INS_CIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmE, SYSZ_INS_CITE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmH, SYSZ_INS_CITH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmHE, SYSZ_INS_CITHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmL, SYSZ_INS_CITL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmLE, SYSZ_INS_CITLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmLH, SYSZ_INS_CITLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmNE, SYSZ_INS_CITNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmNH, SYSZ_INS_CITNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmNHE, SYSZ_INS_CITNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmNL, SYSZ_INS_CITNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmNLE, SYSZ_INS_CITNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CITAsmNLH, SYSZ_INS_CITNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CKSM, SYSZ_INS_CKSM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CL, SYSZ_INS_CL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLC, SYSZ_INS_CLC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLCL, SYSZ_INS_CLCL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLCLE, SYSZ_INS_CLCLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLCLU, SYSZ_INS_CLCLU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFDBR, SYSZ_INS_CLFDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLFDTR, SYSZ_INS_CLFDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLFEBR, SYSZ_INS_CLFEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLFHSI, SYSZ_INS_CLFHSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFI, SYSZ_INS_CLFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsm, SYSZ_INS_CLFIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmE, SYSZ_INS_CLFITE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmH, SYSZ_INS_CLFITH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmHE, SYSZ_INS_CLFITHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmL, SYSZ_INS_CLFITL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmLE, SYSZ_INS_CLFITLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmLH, SYSZ_INS_CLFITLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmNE, SYSZ_INS_CLFITNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmNH, SYSZ_INS_CLFITNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmNHE, SYSZ_INS_CLFITNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmNL, SYSZ_INS_CLFITNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmNLE, SYSZ_INS_CLFITNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFITAsmNLH, SYSZ_INS_CLFITNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLFXBR, SYSZ_INS_CLFXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLFXTR, SYSZ_INS_CLFXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLG, SYSZ_INS_CLG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGDBR, SYSZ_INS_CLGDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLGDTR, SYSZ_INS_CLGDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLGEBR, SYSZ_INS_CLGEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLGF, SYSZ_INS_CLGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGFI, SYSZ_INS_CLGFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGFR, SYSZ_INS_CLGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGFRL, SYSZ_INS_CLGFRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGHRL, SYSZ_INS_CLGHRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGHSI, SYSZ_INS_CLGHSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGIBAsm, SYSZ_INS_CLGIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmE, SYSZ_INS_CLGIBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmH, SYSZ_INS_CLGIBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmHE, SYSZ_INS_CLGIBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmL, SYSZ_INS_CLGIBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmLE, SYSZ_INS_CLGIBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmLH, SYSZ_INS_CLGIBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmNE, SYSZ_INS_CLGIBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmNH, SYSZ_INS_CLGIBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmNHE, SYSZ_INS_CLGIBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmNL, SYSZ_INS_CLGIBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmNLE, SYSZ_INS_CLGIBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIBAsmNLH, SYSZ_INS_CLGIBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGIJAsm, SYSZ_INS_CLGIJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmE, SYSZ_INS_CLGIJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmH, SYSZ_INS_CLGIJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmHE, SYSZ_INS_CLGIJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmL, SYSZ_INS_CLGIJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmLE, SYSZ_INS_CLGIJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmLH, SYSZ_INS_CLGIJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmNE, SYSZ_INS_CLGIJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmNH, SYSZ_INS_CLGIJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmNHE, SYSZ_INS_CLGIJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmNL, SYSZ_INS_CLGIJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmNLE, SYSZ_INS_CLGIJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGIJAsmNLH, SYSZ_INS_CLGIJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGITAsm, SYSZ_INS_CLGIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmE, SYSZ_INS_CLGITE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmH, SYSZ_INS_CLGITH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmHE, SYSZ_INS_CLGITHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmL, SYSZ_INS_CLGITL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmLE, SYSZ_INS_CLGITLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmLH, SYSZ_INS_CLGITLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmNE, SYSZ_INS_CLGITNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmNH, SYSZ_INS_CLGITNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmNHE, SYSZ_INS_CLGITNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmNL, SYSZ_INS_CLGITNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmNLE, SYSZ_INS_CLGITNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGITAsmNLH, SYSZ_INS_CLGITNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGR, SYSZ_INS_CLGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRBAsm, SYSZ_INS_CLGRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmE, SYSZ_INS_CLGRBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmH, SYSZ_INS_CLGRBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmHE, SYSZ_INS_CLGRBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmL, SYSZ_INS_CLGRBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmLE, SYSZ_INS_CLGRBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmLH, SYSZ_INS_CLGRBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmNE, SYSZ_INS_CLGRBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmNH, SYSZ_INS_CLGRBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmNHE, SYSZ_INS_CLGRBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmNL, SYSZ_INS_CLGRBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmNLE, SYSZ_INS_CLGRBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRBAsmNLH, SYSZ_INS_CLGRBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLGRJAsm, SYSZ_INS_CLGRJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmE, SYSZ_INS_CLGRJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmH, SYSZ_INS_CLGRJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmHE, SYSZ_INS_CLGRJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmL, SYSZ_INS_CLGRJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmLE, SYSZ_INS_CLGRJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmLH, SYSZ_INS_CLGRJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmNE, SYSZ_INS_CLGRJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmNH, SYSZ_INS_CLGRJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmNHE, SYSZ_INS_CLGRJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmNL, SYSZ_INS_CLGRJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmNLE, SYSZ_INS_CLGRJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRJAsmNLH, SYSZ_INS_CLGRJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLGRL, SYSZ_INS_CLGRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsm, SYSZ_INS_CLGRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmE, SYSZ_INS_CLGRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmH, SYSZ_INS_CLGRTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmHE, SYSZ_INS_CLGRTHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmL, SYSZ_INS_CLGRTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmLE, SYSZ_INS_CLGRTLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmLH, SYSZ_INS_CLGRTLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmNE, SYSZ_INS_CLGRTNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmNH, SYSZ_INS_CLGRTNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmNHE, SYSZ_INS_CLGRTNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmNL, SYSZ_INS_CLGRTNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmNLE, SYSZ_INS_CLGRTNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGRTAsmNLH, SYSZ_INS_CLGRTNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLGTAsm, SYSZ_INS_CLGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmE, SYSZ_INS_CLGTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmH, SYSZ_INS_CLGTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmHE, SYSZ_INS_CLGTHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmL, SYSZ_INS_CLGTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmLE, SYSZ_INS_CLGTLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmLH, SYSZ_INS_CLGTLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmNE, SYSZ_INS_CLGTNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmNH, SYSZ_INS_CLGTNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmNHE, SYSZ_INS_CLGTNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmNL, SYSZ_INS_CLGTNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmNLE, SYSZ_INS_CLGTNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGTAsmNLH, SYSZ_INS_CLGTNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLGXBR, SYSZ_INS_CLGXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLGXTR, SYSZ_INS_CLGXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CLHF, SYSZ_INS_CLHF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CLHHR, SYSZ_INS_CLHHR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CLHHSI, SYSZ_INS_CLHHSI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLHLR, SYSZ_INS_CLHLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CLHRL, SYSZ_INS_CLHRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLI, SYSZ_INS_CLI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLIBAsm, SYSZ_INS_CLIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmE, SYSZ_INS_CLIBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmH, SYSZ_INS_CLIBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmHE, SYSZ_INS_CLIBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmL, SYSZ_INS_CLIBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmLE, SYSZ_INS_CLIBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmLH, SYSZ_INS_CLIBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmNE, SYSZ_INS_CLIBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmNH, SYSZ_INS_CLIBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmNHE, SYSZ_INS_CLIBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmNL, SYSZ_INS_CLIBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmNLE, SYSZ_INS_CLIBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIBAsmNLH, SYSZ_INS_CLIBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLIH, SYSZ_INS_CLIH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_CLIJAsm, SYSZ_INS_CLIJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmE, SYSZ_INS_CLIJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmH, SYSZ_INS_CLIJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmHE, SYSZ_INS_CLIJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmL, SYSZ_INS_CLIJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmLE, SYSZ_INS_CLIJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmLH, SYSZ_INS_CLIJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmNE, SYSZ_INS_CLIJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmNH, SYSZ_INS_CLIJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmNHE, SYSZ_INS_CLIJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmNL, SYSZ_INS_CLIJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmNLE, SYSZ_INS_CLIJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIJAsmNLH, SYSZ_INS_CLIJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLIY, SYSZ_INS_CLIY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLM, SYSZ_INS_CLM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLMH, SYSZ_INS_CLMH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLMY, SYSZ_INS_CLMY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLR, SYSZ_INS_CLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRBAsm, SYSZ_INS_CLRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmE, SYSZ_INS_CLRBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmH, SYSZ_INS_CLRBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmHE, SYSZ_INS_CLRBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmL, SYSZ_INS_CLRBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmLE, SYSZ_INS_CLRBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmLH, SYSZ_INS_CLRBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmNE, SYSZ_INS_CLRBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmNH, SYSZ_INS_CLRBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmNHE, SYSZ_INS_CLRBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmNL, SYSZ_INS_CLRBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmNLE, SYSZ_INS_CLRBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRBAsmNLH, SYSZ_INS_CLRBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CLRJAsm, SYSZ_INS_CLRJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmE, SYSZ_INS_CLRJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmH, SYSZ_INS_CLRJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmHE, SYSZ_INS_CLRJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmL, SYSZ_INS_CLRJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmLE, SYSZ_INS_CLRJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmLH, SYSZ_INS_CLRJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmNE, SYSZ_INS_CLRJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmNH, SYSZ_INS_CLRJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmNHE, SYSZ_INS_CLRJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmNL, SYSZ_INS_CLRJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmNLE, SYSZ_INS_CLRJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRJAsmNLH, SYSZ_INS_CLRJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CLRL, SYSZ_INS_CLRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsm, SYSZ_INS_CLRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmE, SYSZ_INS_CLRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmH, SYSZ_INS_CLRTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmHE, SYSZ_INS_CLRTHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmL, SYSZ_INS_CLRTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmLE, SYSZ_INS_CLRTLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmLH, SYSZ_INS_CLRTLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmNE, SYSZ_INS_CLRTNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmNH, SYSZ_INS_CLRTNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmNHE, SYSZ_INS_CLRTNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmNL, SYSZ_INS_CLRTNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmNLE, SYSZ_INS_CLRTNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLRTAsmNLH, SYSZ_INS_CLRTNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLST, SYSZ_INS_CLST, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CLTAsm, SYSZ_INS_CLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmE, SYSZ_INS_CLTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmH, SYSZ_INS_CLTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmHE, SYSZ_INS_CLTHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmL, SYSZ_INS_CLTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmLE, SYSZ_INS_CLTLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmLH, SYSZ_INS_CLTLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmNE, SYSZ_INS_CLTNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmNH, SYSZ_INS_CLTNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmNHE, SYSZ_INS_CLTNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmNL, SYSZ_INS_CLTNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmNLE, SYSZ_INS_CLTNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLTAsmNLH, SYSZ_INS_CLTNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_CLY, SYSZ_INS_CLY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CMPSC, SYSZ_INS_CMPSC, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CP, SYSZ_INS_CP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CPDT, SYSZ_INS_CPDT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CPSDRdd, SYSZ_INS_CPSDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CPXT, SYSZ_INS_CPXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CPYA, SYSZ_INS_CPYA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CR, SYSZ_INS_CR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRBAsm, SYSZ_INS_CRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmE, SYSZ_INS_CRBE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmH, SYSZ_INS_CRBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmHE, SYSZ_INS_CRBHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmL, SYSZ_INS_CRBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmLE, SYSZ_INS_CRBLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmLH, SYSZ_INS_CRBLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmNE, SYSZ_INS_CRBNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmNH, SYSZ_INS_CRBNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmNHE, SYSZ_INS_CRBNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmNL, SYSZ_INS_CRBNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmNLE, SYSZ_INS_CRBNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRBAsmNLH, SYSZ_INS_CRBNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { SystemZ_CRDTE, SYSZ_INS_CRDTE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 #endif }, { SystemZ_CRDTEOpt, SYSZ_INS_CRDTE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_ENHANCEDDAT2, 0 }, 0, 0 #endif }, { SystemZ_CRJAsm, SYSZ_INS_CRJ, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmE, SYSZ_INS_CRJE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmH, SYSZ_INS_CRJH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmHE, SYSZ_INS_CRJHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmL, SYSZ_INS_CRJL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmLE, SYSZ_INS_CRJLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmLH, SYSZ_INS_CRJLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmNE, SYSZ_INS_CRJNE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmNH, SYSZ_INS_CRJNH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmNHE, SYSZ_INS_CRJNHE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmNL, SYSZ_INS_CRJNL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmNLE, SYSZ_INS_CRJNLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRJAsmNLH, SYSZ_INS_CRJNLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 1, 0 #endif }, { SystemZ_CRL, SYSZ_INS_CRL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsm, SYSZ_INS_CRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmE, SYSZ_INS_CRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmH, SYSZ_INS_CRTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmHE, SYSZ_INS_CRTHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmL, SYSZ_INS_CRTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmLE, SYSZ_INS_CRTLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmLH, SYSZ_INS_CRTLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmNE, SYSZ_INS_CRTNE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmNH, SYSZ_INS_CRTNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmNHE, SYSZ_INS_CRTNHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmNL, SYSZ_INS_CRTNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmNLE, SYSZ_INS_CRTNLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CRTAsmNLH, SYSZ_INS_CRTNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CS, SYSZ_INS_CS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSCH, SYSZ_INS_CSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSDTR, SYSZ_INS_CSDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSG, SYSZ_INS_CSG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSP, SYSZ_INS_CSP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSPG, SYSZ_INS_CSPG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSST, SYSZ_INS_CSST, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSXTR, SYSZ_INS_CSXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CSY, SYSZ_INS_CSY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU12, SYSZ_INS_CU12, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU12Opt, SYSZ_INS_CU12, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU14, SYSZ_INS_CU14, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU14Opt, SYSZ_INS_CU14, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU21, SYSZ_INS_CU21, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU21Opt, SYSZ_INS_CU21, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU24, SYSZ_INS_CU24, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU24Opt, SYSZ_INS_CU24, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU41, SYSZ_INS_CU41, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CU42, SYSZ_INS_CU42, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUDTR, SYSZ_INS_CUDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUSE, SYSZ_INS_CUSE, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUTFU, SYSZ_INS_CUTFU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUTFUOpt, SYSZ_INS_CUTFU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUUTF, SYSZ_INS_CUUTF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUUTFOpt, SYSZ_INS_CUUTF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CUXTR, SYSZ_INS_CUXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CVB, SYSZ_INS_CVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CVBG, SYSZ_INS_CVBG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CVBY, SYSZ_INS_CVBY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CVD, SYSZ_INS_CVD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CVDG, SYSZ_INS_CVDG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CVDY, SYSZ_INS_CVDY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXBR, SYSZ_INS_CXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXFBR, SYSZ_INS_CXFBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXFBRA, SYSZ_INS_CXFBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXFR, SYSZ_INS_CXFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXFTR, SYSZ_INS_CXFTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXGBR, SYSZ_INS_CXGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXGBRA, SYSZ_INS_CXGBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXGR, SYSZ_INS_CXGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXGTR, SYSZ_INS_CXGTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXGTRA, SYSZ_INS_CXGTRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXLFBR, SYSZ_INS_CXLFBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXLFTR, SYSZ_INS_CXLFTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXLGBR, SYSZ_INS_CXLGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXLGTR, SYSZ_INS_CXLGTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_CXPT, SYSZ_INS_CXPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPPACKEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CXR, SYSZ_INS_CXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXSTR, SYSZ_INS_CXSTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXTR, SYSZ_INS_CXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXUTR, SYSZ_INS_CXUTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CXZT, SYSZ_INS_CXZT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CY, SYSZ_INS_CY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_CZDT, SYSZ_INS_CZDT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_CZXT, SYSZ_INS_CZXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DFPZONEDCONVERSION, 0 }, 0, 0 #endif }, { SystemZ_D, SYSZ_INS_D, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DD, SYSZ_INS_DD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DDB, SYSZ_INS_DDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DDBR, SYSZ_INS_DDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DDR, SYSZ_INS_DDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DDTR, SYSZ_INS_DDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DDTRA, SYSZ_INS_DDTRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_DE, SYSZ_INS_DE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DEB, SYSZ_INS_DEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DEBR, SYSZ_INS_DEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DER, SYSZ_INS_DER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DIAG, SYSZ_INS_DIAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DIDBR, SYSZ_INS_DIDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DIEBR, SYSZ_INS_DIEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DL, SYSZ_INS_DL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DLG, SYSZ_INS_DLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DLGR, SYSZ_INS_DLGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DLR, SYSZ_INS_DLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DP, SYSZ_INS_DP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DR, SYSZ_INS_DR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DSG, SYSZ_INS_DSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DSGF, SYSZ_INS_DSGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DSGFR, SYSZ_INS_DSGFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DSGR, SYSZ_INS_DSGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DXBR, SYSZ_INS_DXBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DXR, SYSZ_INS_DXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DXTR, SYSZ_INS_DXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_DXTRA, SYSZ_INS_DXTRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_EAR, SYSZ_INS_EAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ECAG, SYSZ_INS_ECAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ECCTR, SYSZ_INS_ECCTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ECPGA, SYSZ_INS_ECPGA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ECTG, SYSZ_INS_ECTG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ED, SYSZ_INS_ED, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EDMK, SYSZ_INS_EDMK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EEDTR, SYSZ_INS_EEDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EEXTR, SYSZ_INS_EEXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EFPC, SYSZ_INS_EFPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EPAIR, SYSZ_INS_EPAIR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EPAR, SYSZ_INS_EPAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EPCTR, SYSZ_INS_EPCTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EPSW, SYSZ_INS_EPSW, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EREG, SYSZ_INS_EREG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EREGG, SYSZ_INS_EREGG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ESAIR, SYSZ_INS_ESAIR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ESAR, SYSZ_INS_ESAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ESDTR, SYSZ_INS_ESDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ESEA, SYSZ_INS_ESEA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ESTA, SYSZ_INS_ESTA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ESXTR, SYSZ_INS_ESXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ETND, SYSZ_INS_ETND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 #endif }, { SystemZ_EX, SYSZ_INS_EX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_EXRL, SYSZ_INS_EXRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIDBR, SYSZ_INS_FIDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIDBRA, SYSZ_INS_FIDBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_FIDR, SYSZ_INS_FIDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIDTR, SYSZ_INS_FIDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIEBR, SYSZ_INS_FIEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIEBRA, SYSZ_INS_FIEBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_FIER, SYSZ_INS_FIER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIXBR, SYSZ_INS_FIXBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIXBRA, SYSZ_INS_FIXBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_FIXR, SYSZ_INS_FIXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FIXTR, SYSZ_INS_FIXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_FLOGR, SYSZ_INS_FLOGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_HDR, SYSZ_INS_HDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_HER, SYSZ_INS_HER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_HSCH, SYSZ_INS_HSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IAC, SYSZ_INS_IAC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IC, SYSZ_INS_IC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ICM, SYSZ_INS_ICM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ICMH, SYSZ_INS_ICMH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ICMY, SYSZ_INS_ICMY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ICY, SYSZ_INS_ICY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IDTE, SYSZ_INS_IDTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IDTEOpt, SYSZ_INS_IDTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IEDTR, SYSZ_INS_IEDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IEXTR, SYSZ_INS_IEXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IIHF, SYSZ_INS_IIHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IIHH, SYSZ_INS_IIHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IIHL, SYSZ_INS_IIHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IILF, SYSZ_INS_IILF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IILH, SYSZ_INS_IILH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IILL, SYSZ_INS_IILL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IPK, SYSZ_INS_IPK, #ifndef CAPSTONE_DIET { SYSZ_REG_2, 0 }, { SYSZ_REG_2, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IPM, SYSZ_INS_IPM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IPTE, SYSZ_INS_IPTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IPTEOpt, SYSZ_INS_IPTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IPTEOptOpt, SYSZ_INS_IPTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IRBM, SYSZ_INS_IRBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, 0 }, 0, 0 #endif }, { SystemZ_ISKE, SYSZ_INS_ISKE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_IVSK, SYSZ_INS_IVSK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_J, SYSZ_INS_J, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmE, SYSZ_INS_JE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmH, SYSZ_INS_JH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmHE, SYSZ_INS_JHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmL, SYSZ_INS_JL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmLE, SYSZ_INS_JLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmLH, SYSZ_INS_JLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmM, SYSZ_INS_JM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNE, SYSZ_INS_JNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNH, SYSZ_INS_JNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNHE, SYSZ_INS_JNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNL, SYSZ_INS_JNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNLE, SYSZ_INS_JNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNLH, SYSZ_INS_JNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNM, SYSZ_INS_JNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNO, SYSZ_INS_JNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNP, SYSZ_INS_JNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmNZ, SYSZ_INS_JNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmO, SYSZ_INS_JO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmP, SYSZ_INS_JP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JAsmZ, SYSZ_INS_JZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JG, SYSZ_INS_JG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmE, SYSZ_INS_JGE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmH, SYSZ_INS_JGH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmHE, SYSZ_INS_JGHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmL, SYSZ_INS_JGL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmLE, SYSZ_INS_JGLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmLH, SYSZ_INS_JGLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmM, SYSZ_INS_JGM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNE, SYSZ_INS_JGNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNH, SYSZ_INS_JGNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNHE, SYSZ_INS_JGNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNL, SYSZ_INS_JGNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNLE, SYSZ_INS_JGNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNLH, SYSZ_INS_JGNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNM, SYSZ_INS_JGNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNO, SYSZ_INS_JGNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNP, SYSZ_INS_JGNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmNZ, SYSZ_INS_JGNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmO, SYSZ_INS_JGO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmP, SYSZ_INS_JGP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_JGAsmZ, SYSZ_INS_JGZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { SystemZ_KDB, SYSZ_INS_KDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KDBR, SYSZ_INS_KDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KDTR, SYSZ_INS_KDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KEB, SYSZ_INS_KEB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KEBR, SYSZ_INS_KEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KIMD, SYSZ_INS_KIMD, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KLMD, SYSZ_INS_KLMD, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KM, SYSZ_INS_KM, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KMA, SYSZ_INS_KMA, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST8, 0 }, 0, 0 #endif }, { SystemZ_KMAC, SYSZ_INS_KMAC, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KMC, SYSZ_INS_KMC, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KMCTR, SYSZ_INS_KMCTR, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 #endif }, { SystemZ_KMF, SYSZ_INS_KMF, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 #endif }, { SystemZ_KMO, SYSZ_INS_KMO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 #endif }, { SystemZ_KXBR, SYSZ_INS_KXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_KXTR, SYSZ_INS_KXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_L, SYSZ_INS_L, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LA, SYSZ_INS_LA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LAA, SYSZ_INS_LAA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAAG, SYSZ_INS_LAAG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAAL, SYSZ_INS_LAAL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAALG, SYSZ_INS_LAALG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAE, SYSZ_INS_LAE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LAEY, SYSZ_INS_LAEY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LAM, SYSZ_INS_LAM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LAMY, SYSZ_INS_LAMY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LAN, SYSZ_INS_LAN, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LANG, SYSZ_INS_LANG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAO, SYSZ_INS_LAO, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAOG, SYSZ_INS_LAOG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LARL, SYSZ_INS_LARL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LASP, SYSZ_INS_LASP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LAT, SYSZ_INS_LAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 #endif }, { SystemZ_LAX, SYSZ_INS_LAX, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAXG, SYSZ_INS_LAXG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LAY, SYSZ_INS_LAY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LB, SYSZ_INS_LB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LBH, SYSZ_INS_LBH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_LBR, SYSZ_INS_LBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCBB, SYSZ_INS_LCBB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_LCCTL, SYSZ_INS_LCCTL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCDBR, SYSZ_INS_LCDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCDFR, SYSZ_INS_LCDFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCDR, SYSZ_INS_LCDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCEBR, SYSZ_INS_LCEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCER, SYSZ_INS_LCER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCGFR, SYSZ_INS_LCGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCGR, SYSZ_INS_LCGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCR, SYSZ_INS_LCR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCTL, SYSZ_INS_LCTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCTLG, SYSZ_INS_LCTLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCXBR, SYSZ_INS_LCXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LCXR, SYSZ_INS_LCXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LD, SYSZ_INS_LD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDE, SYSZ_INS_LDE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDEB, SYSZ_INS_LDEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDEBR, SYSZ_INS_LDEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDER, SYSZ_INS_LDER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDETR, SYSZ_INS_LDETR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDGR, SYSZ_INS_LDGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDR, SYSZ_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDXBR, SYSZ_INS_LDXBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDXBRA, SYSZ_INS_LDXBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_LDXR, SYSZ_INS_LDXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDXTR, SYSZ_INS_LDXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LDY, SYSZ_INS_LDY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LE, SYSZ_INS_LE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LEDBR, SYSZ_INS_LEDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LEDBRA, SYSZ_INS_LEDBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_LEDR, SYSZ_INS_LEDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LEDTR, SYSZ_INS_LEDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LER, SYSZ_INS_LER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LEXBR, SYSZ_INS_LEXBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LEXBRA, SYSZ_INS_LEXBRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_LEXR, SYSZ_INS_LEXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LEY, SYSZ_INS_LEY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LFAS, SYSZ_INS_LFAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LFH, SYSZ_INS_LFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_LFHAT, SYSZ_INS_LFHAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 #endif }, { SystemZ_LFPC, SYSZ_INS_LFPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LG, SYSZ_INS_LG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGAT, SYSZ_INS_LGAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 #endif }, { SystemZ_LGB, SYSZ_INS_LGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGBR, SYSZ_INS_LGBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGDR, SYSZ_INS_LGDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGF, SYSZ_INS_LGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGFI, SYSZ_INS_LGFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGFR, SYSZ_INS_LGFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGFRL, SYSZ_INS_LGFRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGG, SYSZ_INS_LGG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 #endif }, { SystemZ_LGH, SYSZ_INS_LGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGHI, SYSZ_INS_LGHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGHR, SYSZ_INS_LGHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGHRL, SYSZ_INS_LGHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGR, SYSZ_INS_LGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGRL, SYSZ_INS_LGRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LGSC, SYSZ_INS_LGSC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 #endif }, { SystemZ_LH, SYSZ_INS_LH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LHH, SYSZ_INS_LHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_LHI, SYSZ_INS_LHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LHR, SYSZ_INS_LHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LHRL, SYSZ_INS_LHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LHY, SYSZ_INS_LHY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLC, SYSZ_INS_LLC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLCH, SYSZ_INS_LLCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_LLCR, SYSZ_INS_LLCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGC, SYSZ_INS_LLGC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGCR, SYSZ_INS_LLGCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGF, SYSZ_INS_LLGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGFAT, SYSZ_INS_LLGFAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 #endif }, { SystemZ_LLGFR, SYSZ_INS_LLGFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGFRL, SYSZ_INS_LLGFRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGFSG, SYSZ_INS_LLGFSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 #endif }, { SystemZ_LLGH, SYSZ_INS_LLGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGHR, SYSZ_INS_LLGHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGHRL, SYSZ_INS_LLGHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGT, SYSZ_INS_LLGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLGTAT, SYSZ_INS_LLGTAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDTRAP, 0 }, 0, 0 #endif }, { SystemZ_LLGTR, SYSZ_INS_LLGTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLH, SYSZ_INS_LLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLHH, SYSZ_INS_LLHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_LLHR, SYSZ_INS_LLHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLHRL, SYSZ_INS_LLHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLIHF, SYSZ_INS_LLIHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLIHH, SYSZ_INS_LLIHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLIHL, SYSZ_INS_LLIHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLILF, SYSZ_INS_LLILF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLILH, SYSZ_INS_LLILH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLILL, SYSZ_INS_LLILL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LLZRGF, SYSZ_INS_LLZRGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 #endif }, { SystemZ_LM, SYSZ_INS_LM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LMD, SYSZ_INS_LMD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LMG, SYSZ_INS_LMG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LMH, SYSZ_INS_LMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LMY, SYSZ_INS_LMY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNDBR, SYSZ_INS_LNDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNDFR, SYSZ_INS_LNDFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNDR, SYSZ_INS_LNDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNEBR, SYSZ_INS_LNEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNER, SYSZ_INS_LNER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNGFR, SYSZ_INS_LNGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNGR, SYSZ_INS_LNGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNR, SYSZ_INS_LNR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNXBR, SYSZ_INS_LNXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LNXR, SYSZ_INS_LNXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LOCAsm, SYSZ_INS_LOC, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmE, SYSZ_INS_LOCE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmH, SYSZ_INS_LOCH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmHE, SYSZ_INS_LOCHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmL, SYSZ_INS_LOCL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmLE, SYSZ_INS_LOCLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmLH, SYSZ_INS_LOCLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmM, SYSZ_INS_LOCM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNE, SYSZ_INS_LOCNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNH, SYSZ_INS_LOCNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNHE, SYSZ_INS_LOCNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNL, SYSZ_INS_LOCNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNLE, SYSZ_INS_LOCNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNLH, SYSZ_INS_LOCNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNM, SYSZ_INS_LOCNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNO, SYSZ_INS_LOCNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNP, SYSZ_INS_LOCNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmNZ, SYSZ_INS_LOCNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmO, SYSZ_INS_LOCO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmP, SYSZ_INS_LOCP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCAsmZ, SYSZ_INS_LOCZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsm, SYSZ_INS_LOCFH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmE, SYSZ_INS_LOCFHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmH, SYSZ_INS_LOCFHH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmHE, SYSZ_INS_LOCFHHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmL, SYSZ_INS_LOCFHL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmLE, SYSZ_INS_LOCFHLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmLH, SYSZ_INS_LOCFHLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmM, SYSZ_INS_LOCFHM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNE, SYSZ_INS_LOCFHNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNH, SYSZ_INS_LOCFHNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNHE, SYSZ_INS_LOCFHNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNL, SYSZ_INS_LOCFHNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNLE, SYSZ_INS_LOCFHNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNLH, SYSZ_INS_LOCFHNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNM, SYSZ_INS_LOCFHNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNO, SYSZ_INS_LOCFHNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNP, SYSZ_INS_LOCFHNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmNZ, SYSZ_INS_LOCFHNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmO, SYSZ_INS_LOCFHO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmP, SYSZ_INS_LOCFHP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHAsmZ, SYSZ_INS_LOCFHZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsm, SYSZ_INS_LOCFHR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmE, SYSZ_INS_LOCFHRE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmH, SYSZ_INS_LOCFHRH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmHE, SYSZ_INS_LOCFHRHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmL, SYSZ_INS_LOCFHRL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmLE, SYSZ_INS_LOCFHRLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmLH, SYSZ_INS_LOCFHRLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmM, SYSZ_INS_LOCFHRM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNE, SYSZ_INS_LOCFHRNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNH, SYSZ_INS_LOCFHRNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNHE, SYSZ_INS_LOCFHRNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNL, SYSZ_INS_LOCFHRNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNLE, SYSZ_INS_LOCFHRNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNLH, SYSZ_INS_LOCFHRNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNM, SYSZ_INS_LOCFHRNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNO, SYSZ_INS_LOCFHRNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNP, SYSZ_INS_LOCFHRNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmNZ, SYSZ_INS_LOCFHRNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmO, SYSZ_INS_LOCFHRO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmP, SYSZ_INS_LOCFHRP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCFHRAsmZ, SYSZ_INS_LOCFHRZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsm, SYSZ_INS_LOCG, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmE, SYSZ_INS_LOCGE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmH, SYSZ_INS_LOCGH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmHE, SYSZ_INS_LOCGHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmL, SYSZ_INS_LOCGL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmLE, SYSZ_INS_LOCGLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmLH, SYSZ_INS_LOCGLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmM, SYSZ_INS_LOCGM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNE, SYSZ_INS_LOCGNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNH, SYSZ_INS_LOCGNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNHE, SYSZ_INS_LOCGNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNL, SYSZ_INS_LOCGNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNLE, SYSZ_INS_LOCGNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNLH, SYSZ_INS_LOCGNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNM, SYSZ_INS_LOCGNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNO, SYSZ_INS_LOCGNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNP, SYSZ_INS_LOCGNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmNZ, SYSZ_INS_LOCGNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmO, SYSZ_INS_LOCGO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmP, SYSZ_INS_LOCGP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGAsmZ, SYSZ_INS_LOCGZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsm, SYSZ_INS_LOCGHI, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmE, SYSZ_INS_LOCGHIE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmH, SYSZ_INS_LOCGHIH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmHE, SYSZ_INS_LOCGHIHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmL, SYSZ_INS_LOCGHIL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmLE, SYSZ_INS_LOCGHILE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmLH, SYSZ_INS_LOCGHILH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmM, SYSZ_INS_LOCGHIM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNE, SYSZ_INS_LOCGHINE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNH, SYSZ_INS_LOCGHINH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNHE, SYSZ_INS_LOCGHINHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNL, SYSZ_INS_LOCGHINL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNLE, SYSZ_INS_LOCGHINLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNLH, SYSZ_INS_LOCGHINLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNM, SYSZ_INS_LOCGHINM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNO, SYSZ_INS_LOCGHINO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNP, SYSZ_INS_LOCGHINP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmNZ, SYSZ_INS_LOCGHINZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmO, SYSZ_INS_LOCGHIO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmP, SYSZ_INS_LOCGHIP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGHIAsmZ, SYSZ_INS_LOCGHIZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsm, SYSZ_INS_LOCGR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmE, SYSZ_INS_LOCGRE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmH, SYSZ_INS_LOCGRH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmHE, SYSZ_INS_LOCGRHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmL, SYSZ_INS_LOCGRL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmLE, SYSZ_INS_LOCGRLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmLH, SYSZ_INS_LOCGRLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmM, SYSZ_INS_LOCGRM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNE, SYSZ_INS_LOCGRNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNH, SYSZ_INS_LOCGRNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNHE, SYSZ_INS_LOCGRNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNL, SYSZ_INS_LOCGRNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNLE, SYSZ_INS_LOCGRNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNLH, SYSZ_INS_LOCGRNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNM, SYSZ_INS_LOCGRNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNO, SYSZ_INS_LOCGRNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNP, SYSZ_INS_LOCGRNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmNZ, SYSZ_INS_LOCGRNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmO, SYSZ_INS_LOCGRO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmP, SYSZ_INS_LOCGRP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCGRAsmZ, SYSZ_INS_LOCGRZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsm, SYSZ_INS_LOCHHI, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmE, SYSZ_INS_LOCHHIE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmH, SYSZ_INS_LOCHHIH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmHE, SYSZ_INS_LOCHHIHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmL, SYSZ_INS_LOCHHIL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmLE, SYSZ_INS_LOCHHILE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmLH, SYSZ_INS_LOCHHILH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmM, SYSZ_INS_LOCHHIM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNE, SYSZ_INS_LOCHHINE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNH, SYSZ_INS_LOCHHINH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNHE, SYSZ_INS_LOCHHINHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNL, SYSZ_INS_LOCHHINL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNLE, SYSZ_INS_LOCHHINLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNLH, SYSZ_INS_LOCHHINLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNM, SYSZ_INS_LOCHHINM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNO, SYSZ_INS_LOCHHINO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNP, SYSZ_INS_LOCHHINP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmNZ, SYSZ_INS_LOCHHINZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmO, SYSZ_INS_LOCHHIO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmP, SYSZ_INS_LOCHHIP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHHIAsmZ, SYSZ_INS_LOCHHIZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsm, SYSZ_INS_LOCHI, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmE, SYSZ_INS_LOCHIE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmH, SYSZ_INS_LOCHIH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmHE, SYSZ_INS_LOCHIHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmL, SYSZ_INS_LOCHIL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmLE, SYSZ_INS_LOCHILE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmLH, SYSZ_INS_LOCHILH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmM, SYSZ_INS_LOCHIM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNE, SYSZ_INS_LOCHINE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNH, SYSZ_INS_LOCHINH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNHE, SYSZ_INS_LOCHINHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNL, SYSZ_INS_LOCHINL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNLE, SYSZ_INS_LOCHINLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNLH, SYSZ_INS_LOCHINLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNM, SYSZ_INS_LOCHINM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNO, SYSZ_INS_LOCHINO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNP, SYSZ_INS_LOCHINP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmNZ, SYSZ_INS_LOCHINZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmO, SYSZ_INS_LOCHIO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmP, SYSZ_INS_LOCHIP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCHIAsmZ, SYSZ_INS_LOCHIZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsm, SYSZ_INS_LOCR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmE, SYSZ_INS_LOCRE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmH, SYSZ_INS_LOCRH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmHE, SYSZ_INS_LOCRHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmL, SYSZ_INS_LOCRL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmLE, SYSZ_INS_LOCRLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmLH, SYSZ_INS_LOCRLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmM, SYSZ_INS_LOCRM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNE, SYSZ_INS_LOCRNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNH, SYSZ_INS_LOCRNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNHE, SYSZ_INS_LOCRNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNL, SYSZ_INS_LOCRNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNLE, SYSZ_INS_LOCRNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNLH, SYSZ_INS_LOCRNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNM, SYSZ_INS_LOCRNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNO, SYSZ_INS_LOCRNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNP, SYSZ_INS_LOCRNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmNZ, SYSZ_INS_LOCRNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmO, SYSZ_INS_LOCRO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmP, SYSZ_INS_LOCRP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LOCRAsmZ, SYSZ_INS_LOCRZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_LPCTL, SYSZ_INS_LPCTL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPD, SYSZ_INS_LPD, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LPDBR, SYSZ_INS_LPDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPDFR, SYSZ_INS_LPDFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPDG, SYSZ_INS_LPDG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_INTERLOCKEDACCESS1, 0 }, 0, 0 #endif }, { SystemZ_LPDR, SYSZ_INS_LPDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPEBR, SYSZ_INS_LPEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPER, SYSZ_INS_LPER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPGFR, SYSZ_INS_LPGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPGR, SYSZ_INS_LPGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPP, SYSZ_INS_LPP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPQ, SYSZ_INS_LPQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPR, SYSZ_INS_LPR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPSW, SYSZ_INS_LPSW, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPSWE, SYSZ_INS_LPSWE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPTEA, SYSZ_INS_LPTEA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPXBR, SYSZ_INS_LPXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LPXR, SYSZ_INS_LPXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LR, SYSZ_INS_LR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRA, SYSZ_INS_LRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRAG, SYSZ_INS_LRAG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRAY, SYSZ_INS_LRAY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRDR, SYSZ_INS_LRDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRER, SYSZ_INS_LRER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRL, SYSZ_INS_LRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRV, SYSZ_INS_LRV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRVG, SYSZ_INS_LRVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRVGR, SYSZ_INS_LRVGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRVH, SYSZ_INS_LRVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LRVR, SYSZ_INS_LRVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LSCTL, SYSZ_INS_LSCTL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LT, SYSZ_INS_LT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTDBR, SYSZ_INS_LTDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTDR, SYSZ_INS_LTDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTDTR, SYSZ_INS_LTDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTEBR, SYSZ_INS_LTEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTER, SYSZ_INS_LTER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTG, SYSZ_INS_LTG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTGF, SYSZ_INS_LTGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTGFR, SYSZ_INS_LTGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTGR, SYSZ_INS_LTGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTR, SYSZ_INS_LTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTXBR, SYSZ_INS_LTXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTXR, SYSZ_INS_LTXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LTXTR, SYSZ_INS_LTXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LURA, SYSZ_INS_LURA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LURAG, SYSZ_INS_LURAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXD, SYSZ_INS_LXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXDB, SYSZ_INS_LXDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXDBR, SYSZ_INS_LXDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXDR, SYSZ_INS_LXDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXDTR, SYSZ_INS_LXDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXE, SYSZ_INS_LXE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXEB, SYSZ_INS_LXEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXEBR, SYSZ_INS_LXEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXER, SYSZ_INS_LXER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LXR, SYSZ_INS_LXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LY, SYSZ_INS_LY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LZDR, SYSZ_INS_LZDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LZER, SYSZ_INS_LZER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_LZRF, SYSZ_INS_LZRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 #endif }, { SystemZ_LZRG, SYSZ_INS_LZRG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, 0 }, 0, 0 #endif }, { SystemZ_LZXR, SYSZ_INS_LZXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_M, SYSZ_INS_M, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAD, SYSZ_INS_MAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MADB, SYSZ_INS_MADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MADBR, SYSZ_INS_MADBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MADR, SYSZ_INS_MADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAE, SYSZ_INS_MAE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAEB, SYSZ_INS_MAEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAEBR, SYSZ_INS_MAEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAER, SYSZ_INS_MAER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAY, SYSZ_INS_MAY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAYH, SYSZ_INS_MAYH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAYHR, SYSZ_INS_MAYHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAYL, SYSZ_INS_MAYL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAYLR, SYSZ_INS_MAYLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MAYR, SYSZ_INS_MAYR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MC, SYSZ_INS_MC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MD, SYSZ_INS_MD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDB, SYSZ_INS_MDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDBR, SYSZ_INS_MDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDE, SYSZ_INS_MDE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDEB, SYSZ_INS_MDEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDEBR, SYSZ_INS_MDEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDER, SYSZ_INS_MDER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDR, SYSZ_INS_MDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDTR, SYSZ_INS_MDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MDTRA, SYSZ_INS_MDTRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_ME, SYSZ_INS_ME, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MEE, SYSZ_INS_MEE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MEEB, SYSZ_INS_MEEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MEEBR, SYSZ_INS_MEEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MEER, SYSZ_INS_MEER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MER, SYSZ_INS_MER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MFY, SYSZ_INS_MFY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MG, SYSZ_INS_MG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MGH, SYSZ_INS_MGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MGHI, SYSZ_INS_MGHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MGRK, SYSZ_INS_MGRK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MH, SYSZ_INS_MH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MHI, SYSZ_INS_MHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MHY, SYSZ_INS_MHY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ML, SYSZ_INS_ML, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MLG, SYSZ_INS_MLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MLGR, SYSZ_INS_MLGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MLR, SYSZ_INS_MLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MP, SYSZ_INS_MP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MR, SYSZ_INS_MR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MS, SYSZ_INS_MS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSC, SYSZ_INS_MSC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MSCH, SYSZ_INS_MSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSD, SYSZ_INS_MSD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSDB, SYSZ_INS_MSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSDBR, SYSZ_INS_MSDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSDR, SYSZ_INS_MSDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSE, SYSZ_INS_MSE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSEB, SYSZ_INS_MSEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSEBR, SYSZ_INS_MSEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSER, SYSZ_INS_MSER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSFI, SYSZ_INS_MSFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSG, SYSZ_INS_MSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSGC, SYSZ_INS_MSGC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MSGF, SYSZ_INS_MSGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSGFI, SYSZ_INS_MSGFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSGFR, SYSZ_INS_MSGFR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSGR, SYSZ_INS_MSGR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSGRKC, SYSZ_INS_MSGRKC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MSR, SYSZ_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSRKC, SYSZ_INS_MSRKC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_MSTA, SYSZ_INS_MSTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MSY, SYSZ_INS_MSY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVC, SYSZ_INS_MVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCDK, SYSZ_INS_MVCDK, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCIN, SYSZ_INS_MVCIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCK, SYSZ_INS_MVCK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCL, SYSZ_INS_MVCL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCLE, SYSZ_INS_MVCLE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCLU, SYSZ_INS_MVCLU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCOS, SYSZ_INS_MVCOS, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCP, SYSZ_INS_MVCP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCS, SYSZ_INS_MVCS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVCSK, SYSZ_INS_MVCSK, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVGHI, SYSZ_INS_MVGHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVHHI, SYSZ_INS_MVHHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVHI, SYSZ_INS_MVHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVI, SYSZ_INS_MVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVIY, SYSZ_INS_MVIY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVN, SYSZ_INS_MVN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVO, SYSZ_INS_MVO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVPG, SYSZ_INS_MVPG, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVST, SYSZ_INS_MVST, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MVZ, SYSZ_INS_MVZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXBR, SYSZ_INS_MXBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXD, SYSZ_INS_MXD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXDB, SYSZ_INS_MXDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXDBR, SYSZ_INS_MXDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXDR, SYSZ_INS_MXDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXR, SYSZ_INS_MXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXTR, SYSZ_INS_MXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MXTRA, SYSZ_INS_MXTRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_MY, SYSZ_INS_MY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MYH, SYSZ_INS_MYH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MYHR, SYSZ_INS_MYHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MYL, SYSZ_INS_MYL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MYLR, SYSZ_INS_MYLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_MYR, SYSZ_INS_MYR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_N, SYSZ_INS_N, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NC, SYSZ_INS_NC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NG, SYSZ_INS_NG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NGR, SYSZ_INS_NGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NGRK, SYSZ_INS_NGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_NI, SYSZ_INS_NI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NIAI, SYSZ_INS_NIAI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_EXECUTIONHINT, 0 }, 0, 0 #endif }, { SystemZ_NIHF, SYSZ_INS_NIHF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NIHH, SYSZ_INS_NIHH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NIHL, SYSZ_INS_NIHL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NILF, SYSZ_INS_NILF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NILH, SYSZ_INS_NILH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NILL, SYSZ_INS_NILL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NIY, SYSZ_INS_NIY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NR, SYSZ_INS_NR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_NRK, SYSZ_INS_NRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_NTSTG, SYSZ_INS_NTSTG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 #endif }, { SystemZ_NY, SYSZ_INS_NY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_O, SYSZ_INS_O, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OC, SYSZ_INS_OC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OG, SYSZ_INS_OG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OGR, SYSZ_INS_OGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OGRK, SYSZ_INS_OGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_OI, SYSZ_INS_OI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OIHF, SYSZ_INS_OIHF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OIHH, SYSZ_INS_OIHH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OIHL, SYSZ_INS_OIHL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OILF, SYSZ_INS_OILF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OILH, SYSZ_INS_OILH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OILL, SYSZ_INS_OILL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OIY, SYSZ_INS_OIY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_OR, SYSZ_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ORK, SYSZ_INS_ORK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_OY, SYSZ_INS_OY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PACK, SYSZ_INS_PACK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PALB, SYSZ_INS_PALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PC, SYSZ_INS_PC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PCC, SYSZ_INS_PCC, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST4, 0 }, 0, 0 #endif }, { SystemZ_PCKMO, SYSZ_INS_PCKMO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST3, 0 }, 0, 0 #endif }, { SystemZ_PFD, SYSZ_INS_PFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PFDRL, SYSZ_INS_PFDRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PFMF, SYSZ_INS_PFMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PFPO, SYSZ_INS_PFPO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_F4Q, 0 }, { SYSZ_REG_CC, SYSZ_REG_1, SYSZ_REG_F0Q, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PGIN, SYSZ_INS_PGIN, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PGOUT, SYSZ_INS_PGOUT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PKA, SYSZ_INS_PKA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PKU, SYSZ_INS_PKU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PLO, SYSZ_INS_PLO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_POPCNT, SYSZ_INS_POPCNT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_POPULATIONCOUNT, 0 }, 0, 0 #endif }, { SystemZ_PPA, SYSZ_INS_PPA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_PROCESSORASSIST, 0 }, 0, 0 #endif }, { SystemZ_PPNO, SYSZ_INS_PPNO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST5, 0 }, 0, 0 #endif }, { SystemZ_PR, SYSZ_INS_PR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PRNO, SYSZ_INS_PRNO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MESSAGESECURITYASSIST7, 0 }, 0, 0 #endif }, { SystemZ_PT, SYSZ_INS_PT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PTF, SYSZ_INS_PTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PTFF, SYSZ_INS_PTFF, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PTI, SYSZ_INS_PTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_PTLB, SYSZ_INS_PTLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_QADTR, SYSZ_INS_QADTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_QAXTR, SYSZ_INS_QAXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_QCTRI, SYSZ_INS_QCTRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_QSI, SYSZ_INS_QSI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RCHP, SYSZ_INS_RCHP, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RISBG, SYSZ_INS_RISBG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RISBGN, SYSZ_INS_RISBGN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS, 0 }, 0, 0 #endif }, { SystemZ_RISBHG, SYSZ_INS_RISBHG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_RISBLG, SYSZ_INS_RISBLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_RLL, SYSZ_INS_RLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RLLG, SYSZ_INS_RLLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RNSBG, SYSZ_INS_RNSBG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ROSBG, SYSZ_INS_ROSBG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RP, SYSZ_INS_RP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RRBE, SYSZ_INS_RRBE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RRBM, SYSZ_INS_RRBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, 0 }, 0, 0 #endif }, { SystemZ_RRDTR, SYSZ_INS_RRDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RRXTR, SYSZ_INS_RRXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RSCH, SYSZ_INS_RSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_RXSBG, SYSZ_INS_RXSBG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_S, SYSZ_INS_S, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SAC, SYSZ_INS_SAC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SACF, SYSZ_INS_SACF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SAL, SYSZ_INS_SAL, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SAM24, SYSZ_INS_SAM24, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SAM31, SYSZ_INS_SAM31, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SAM64, SYSZ_INS_SAM64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SAR, SYSZ_INS_SAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SCCTR, SYSZ_INS_SCCTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SCHM, SYSZ_INS_SCHM, #ifndef CAPSTONE_DIET { SYSZ_REG_1, SYSZ_REG_2, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SCK, SYSZ_INS_SCK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SCKC, SYSZ_INS_SCKC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SCKPF, SYSZ_INS_SCKPF, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SD, SYSZ_INS_SD, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SDB, SYSZ_INS_SDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SDBR, SYSZ_INS_SDBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SDR, SYSZ_INS_SDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SDTR, SYSZ_INS_SDTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SDTRA, SYSZ_INS_SDTRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_SE, SYSZ_INS_SE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SEB, SYSZ_INS_SEB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SEBR, SYSZ_INS_SEBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SER, SYSZ_INS_SER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SFASR, SYSZ_INS_SFASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SFPC, SYSZ_INS_SFPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SG, SYSZ_INS_SG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SGF, SYSZ_INS_SGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SGFR, SYSZ_INS_SGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SGH, SYSZ_INS_SGH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, 0 }, 0, 0 #endif }, { SystemZ_SGR, SYSZ_INS_SGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SGRK, SYSZ_INS_SGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SH, SYSZ_INS_SH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SHHHR, SYSZ_INS_SHHHR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_SHHLR, SYSZ_INS_SHHLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_SHY, SYSZ_INS_SHY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SIE, SYSZ_INS_SIE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SIGA, SYSZ_INS_SIGA, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SIGP, SYSZ_INS_SIGP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SL, SYSZ_INS_SL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLA, SYSZ_INS_SLA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLAG, SYSZ_INS_SLAG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLAK, SYSZ_INS_SLAK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SLB, SYSZ_INS_SLB, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLBG, SYSZ_INS_SLBG, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLBGR, SYSZ_INS_SLBGR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLBR, SYSZ_INS_SLBR, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLDA, SYSZ_INS_SLDA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLDL, SYSZ_INS_SLDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLDT, SYSZ_INS_SLDT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLFI, SYSZ_INS_SLFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLG, SYSZ_INS_SLG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLGF, SYSZ_INS_SLGF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLGFI, SYSZ_INS_SLGFI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLGFR, SYSZ_INS_SLGFR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLGR, SYSZ_INS_SLGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLGRK, SYSZ_INS_SLGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SLHHHR, SYSZ_INS_SLHHHR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_SLHHLR, SYSZ_INS_SLHHLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_SLL, SYSZ_INS_SLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLLG, SYSZ_INS_SLLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLLK, SYSZ_INS_SLLK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SLR, SYSZ_INS_SLR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLRK, SYSZ_INS_SLRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SLXT, SYSZ_INS_SLXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SLY, SYSZ_INS_SLY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SP, SYSZ_INS_SP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SPCTR, SYSZ_INS_SPCTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SPKA, SYSZ_INS_SPKA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SPM, SYSZ_INS_SPM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SPT, SYSZ_INS_SPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SPX, SYSZ_INS_SPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQD, SYSZ_INS_SQD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQDB, SYSZ_INS_SQDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQDBR, SYSZ_INS_SQDBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQDR, SYSZ_INS_SQDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQE, SYSZ_INS_SQE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQEB, SYSZ_INS_SQEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQEBR, SYSZ_INS_SQEBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQER, SYSZ_INS_SQER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQXBR, SYSZ_INS_SQXBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SQXR, SYSZ_INS_SQXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SR, SYSZ_INS_SR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRA, SYSZ_INS_SRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRAG, SYSZ_INS_SRAG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRAK, SYSZ_INS_SRAK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SRDA, SYSZ_INS_SRDA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRDL, SYSZ_INS_SRDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRDT, SYSZ_INS_SRDT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRK, SYSZ_INS_SRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SRL, SYSZ_INS_SRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRLG, SYSZ_INS_SRLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRLK, SYSZ_INS_SRLK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_SRNM, SYSZ_INS_SRNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRNMB, SYSZ_INS_SRNMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_SRNMT, SYSZ_INS_SRNMT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRP, SYSZ_INS_SRP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRST, SYSZ_INS_SRST, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRSTU, SYSZ_INS_SRSTU, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SRXT, SYSZ_INS_SRXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SSAIR, SYSZ_INS_SSAIR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SSAR, SYSZ_INS_SSAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SSCH, SYSZ_INS_SSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SSKE, SYSZ_INS_SSKE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SSKEOpt, SYSZ_INS_SSKE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SSM, SYSZ_INS_SSM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ST, SYSZ_INS_ST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STAM, SYSZ_INS_STAM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STAMY, SYSZ_INS_STAMY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STAP, SYSZ_INS_STAP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STC, SYSZ_INS_STC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCH, SYSZ_INS_STCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_STCK, SYSZ_INS_STCK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCKC, SYSZ_INS_STCKC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCKE, SYSZ_INS_STCKE, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCKF, SYSZ_INS_STCKF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCM, SYSZ_INS_STCM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCMH, SYSZ_INS_STCMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCMY, SYSZ_INS_STCMY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCPS, SYSZ_INS_STCPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCRW, SYSZ_INS_STCRW, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCTG, SYSZ_INS_STCTG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCTL, SYSZ_INS_STCTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STCY, SYSZ_INS_STCY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STD, SYSZ_INS_STD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STDY, SYSZ_INS_STDY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STE, SYSZ_INS_STE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STEY, SYSZ_INS_STEY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STFH, SYSZ_INS_STFH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_STFL, SYSZ_INS_STFL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STFLE, SYSZ_INS_STFLE, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STFPC, SYSZ_INS_STFPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STG, SYSZ_INS_STG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STGRL, SYSZ_INS_STGRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STGSC, SYSZ_INS_STGSC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_GUARDEDSTORAGE, 0 }, 0, 0 #endif }, { SystemZ_STH, SYSZ_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STHH, SYSZ_INS_STHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_HIGHWORD, 0 }, 0, 0 #endif }, { SystemZ_STHRL, SYSZ_INS_STHRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STHY, SYSZ_INS_STHY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STIDP, SYSZ_INS_STIDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STM, SYSZ_INS_STM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STMG, SYSZ_INS_STMG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STMH, SYSZ_INS_STMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STMY, SYSZ_INS_STMY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STNSM, SYSZ_INS_STNSM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STOCAsm, SYSZ_INS_STOC, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmE, SYSZ_INS_STOCE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmH, SYSZ_INS_STOCH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmHE, SYSZ_INS_STOCHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmL, SYSZ_INS_STOCL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmLE, SYSZ_INS_STOCLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmLH, SYSZ_INS_STOCLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmM, SYSZ_INS_STOCM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNE, SYSZ_INS_STOCNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNH, SYSZ_INS_STOCNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNHE, SYSZ_INS_STOCNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNL, SYSZ_INS_STOCNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNLE, SYSZ_INS_STOCNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNLH, SYSZ_INS_STOCNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNM, SYSZ_INS_STOCNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNO, SYSZ_INS_STOCNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNP, SYSZ_INS_STOCNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmNZ, SYSZ_INS_STOCNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmO, SYSZ_INS_STOCO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmP, SYSZ_INS_STOCP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCAsmZ, SYSZ_INS_STOCZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsm, SYSZ_INS_STOCFH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmE, SYSZ_INS_STOCFHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmH, SYSZ_INS_STOCFHH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmHE, SYSZ_INS_STOCFHHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmL, SYSZ_INS_STOCFHL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmLE, SYSZ_INS_STOCFHLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmLH, SYSZ_INS_STOCFHLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmM, SYSZ_INS_STOCFHM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNE, SYSZ_INS_STOCFHNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNH, SYSZ_INS_STOCFHNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNHE, SYSZ_INS_STOCFHNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNL, SYSZ_INS_STOCFHNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNLE, SYSZ_INS_STOCFHNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNLH, SYSZ_INS_STOCFHNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNM, SYSZ_INS_STOCFHNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNO, SYSZ_INS_STOCFHNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNP, SYSZ_INS_STOCFHNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmNZ, SYSZ_INS_STOCFHNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmO, SYSZ_INS_STOCFHO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmP, SYSZ_INS_STOCFHP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCFHAsmZ, SYSZ_INS_STOCFHZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND2, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsm, SYSZ_INS_STOCG, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmE, SYSZ_INS_STOCGE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmH, SYSZ_INS_STOCGH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmHE, SYSZ_INS_STOCGHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmL, SYSZ_INS_STOCGL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmLE, SYSZ_INS_STOCGLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmLH, SYSZ_INS_STOCGLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmM, SYSZ_INS_STOCGM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNE, SYSZ_INS_STOCGNE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNH, SYSZ_INS_STOCGNH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNHE, SYSZ_INS_STOCGNHE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNL, SYSZ_INS_STOCGNL, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNLE, SYSZ_INS_STOCGNLE, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNLH, SYSZ_INS_STOCGNLH, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNM, SYSZ_INS_STOCGNM, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNO, SYSZ_INS_STOCGNO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNP, SYSZ_INS_STOCGNP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmNZ, SYSZ_INS_STOCGNZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmO, SYSZ_INS_STOCGO, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmP, SYSZ_INS_STOCGP, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOCGAsmZ, SYSZ_INS_STOCGZ, #ifndef CAPSTONE_DIET { SYSZ_REG_CC, 0 }, { 0 }, { SYSZ_GRP_LOADSTOREONCOND, 0 }, 0, 0 #endif }, { SystemZ_STOSM, SYSZ_INS_STOSM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STPQ, SYSZ_INS_STPQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STPT, SYSZ_INS_STPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STPX, SYSZ_INS_STPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STRAG, SYSZ_INS_STRAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STRL, SYSZ_INS_STRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STRV, SYSZ_INS_STRV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STRVG, SYSZ_INS_STRVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STRVH, SYSZ_INS_STRVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STSCH, SYSZ_INS_STSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STSI, SYSZ_INS_STSI, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STURA, SYSZ_INS_STURA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STURG, SYSZ_INS_STURG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_STY, SYSZ_INS_STY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SU, SYSZ_INS_SU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SUR, SYSZ_INS_SUR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SVC, SYSZ_INS_SVC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SW, SYSZ_INS_SW, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SWR, SYSZ_INS_SWR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SXBR, SYSZ_INS_SXBR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SXR, SYSZ_INS_SXR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SXTR, SYSZ_INS_SXTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_SXTRA, SYSZ_INS_SXTRA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_FPEXTENSION, 0 }, 0, 0 #endif }, { SystemZ_SY, SYSZ_INS_SY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TABORT, SYSZ_INS_TABORT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 #endif }, { SystemZ_TAM, SYSZ_INS_TAM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TAR, SYSZ_INS_TAR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TB, SYSZ_INS_TB, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { SYSZ_REG_0, SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TBDR, SYSZ_INS_TBDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TBEDR, SYSZ_INS_TBEDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TBEGIN, SYSZ_INS_TBEGIN, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 #endif }, { SystemZ_TBEGINC, SYSZ_INS_TBEGINC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 #endif }, { SystemZ_TCDB, SYSZ_INS_TCDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TCEB, SYSZ_INS_TCEB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TCXB, SYSZ_INS_TCXB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TDCDT, SYSZ_INS_TDCDT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TDCET, SYSZ_INS_TDCET, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TDCXT, SYSZ_INS_TDCXT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TDGDT, SYSZ_INS_TDGDT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TDGET, SYSZ_INS_TDGET, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TDGXT, SYSZ_INS_TDGXT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TEND, SYSZ_INS_TEND, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_TRANSACTIONALEXECUTION, 0 }, 0, 0 #endif }, { SystemZ_THDER, SYSZ_INS_THDER, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_THDR, SYSZ_INS_THDR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TM, SYSZ_INS_TM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TMHH, SYSZ_INS_TMHH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TMHL, SYSZ_INS_TMHL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TMLH, SYSZ_INS_TMLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TMLL, SYSZ_INS_TMLL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TMY, SYSZ_INS_TMY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TP, SYSZ_INS_TP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TPI, SYSZ_INS_TPI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TPROT, SYSZ_INS_TPROT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TR, SYSZ_INS_TR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRACE, SYSZ_INS_TRACE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRACG, SYSZ_INS_TRACG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRAP2, SYSZ_INS_TRAP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRAP4, SYSZ_INS_TRAP4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRE, SYSZ_INS_TRE, #ifndef CAPSTONE_DIET { SYSZ_REG_0, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TROO, SYSZ_INS_TROO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TROOOpt, SYSZ_INS_TROO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TROT, SYSZ_INS_TROT, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TROTOpt, SYSZ_INS_TROT, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRT, SYSZ_INS_TRT, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTE, SYSZ_INS_TRTE, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTEOpt, SYSZ_INS_TRTE, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTO, SYSZ_INS_TRTO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTOOpt, SYSZ_INS_TRTO, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTR, SYSZ_INS_TRTR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTRE, SYSZ_INS_TRTRE, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTREOpt, SYSZ_INS_TRTRE, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTT, SYSZ_INS_TRTT, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TRTTOpt, SYSZ_INS_TRTT, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TS, SYSZ_INS_TS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_TSCH, SYSZ_INS_TSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_UNPK, SYSZ_INS_UNPK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { SystemZ_UNPKA, SYSZ_INS_UNPKA, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_UNPKU, SYSZ_INS_UNPKU, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_UPT, SYSZ_INS_UPT, #ifndef CAPSTONE_DIET { SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, 0 }, { SYSZ_REG_CC, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_5, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_VA, SYSZ_INS_VA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAB, SYSZ_INS_VAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAC, SYSZ_INS_VAC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACC, SYSZ_INS_VACC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCB, SYSZ_INS_VACCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCC, SYSZ_INS_VACCC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCCQ, SYSZ_INS_VACCCQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCF, SYSZ_INS_VACCF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCG, SYSZ_INS_VACCG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCH, SYSZ_INS_VACCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACCQ, SYSZ_INS_VACCQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VACQ, SYSZ_INS_VACQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAF, SYSZ_INS_VAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAG, SYSZ_INS_VAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAH, SYSZ_INS_VAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAP, SYSZ_INS_VAP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VAQ, SYSZ_INS_VAQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVG, SYSZ_INS_VAVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGB, SYSZ_INS_VAVGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGF, SYSZ_INS_VAVGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGG, SYSZ_INS_VAVGG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGH, SYSZ_INS_VAVGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGL, SYSZ_INS_VAVGL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGLB, SYSZ_INS_VAVGLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGLF, SYSZ_INS_VAVGLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGLG, SYSZ_INS_VAVGLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VAVGLH, SYSZ_INS_VAVGLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VBPERM, SYSZ_INS_VBPERM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VCDG, SYSZ_INS_VCDG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCDGB, SYSZ_INS_VCDGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCDLG, SYSZ_INS_VCDLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCDLGB, SYSZ_INS_VCDLGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQ, SYSZ_INS_VCEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQB, SYSZ_INS_VCEQB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQBS, SYSZ_INS_VCEQBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQF, SYSZ_INS_VCEQF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQFS, SYSZ_INS_VCEQFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQG, SYSZ_INS_VCEQG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQGS, SYSZ_INS_VCEQGS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQH, SYSZ_INS_VCEQH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCEQHS, SYSZ_INS_VCEQHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCGD, SYSZ_INS_VCGD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCGDB, SYSZ_INS_VCGDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCH, SYSZ_INS_VCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHB, SYSZ_INS_VCHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHBS, SYSZ_INS_VCHBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHF, SYSZ_INS_VCHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHFS, SYSZ_INS_VCHFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHG, SYSZ_INS_VCHG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHGS, SYSZ_INS_VCHGS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHH, SYSZ_INS_VCHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHHS, SYSZ_INS_VCHHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHL, SYSZ_INS_VCHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLB, SYSZ_INS_VCHLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLBS, SYSZ_INS_VCHLBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLF, SYSZ_INS_VCHLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLFS, SYSZ_INS_VCHLFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLG, SYSZ_INS_VCHLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLGS, SYSZ_INS_VCHLGS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLH, SYSZ_INS_VCHLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCHLHS, SYSZ_INS_VCHLHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCKSM, SYSZ_INS_VCKSM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLGD, SYSZ_INS_VCLGD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLGDB, SYSZ_INS_VCLGDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLZ, SYSZ_INS_VCLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLZB, SYSZ_INS_VCLZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLZF, SYSZ_INS_VCLZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLZG, SYSZ_INS_VCLZG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCLZH, SYSZ_INS_VCLZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCP, SYSZ_INS_VCP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VCTZ, SYSZ_INS_VCTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCTZB, SYSZ_INS_VCTZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCTZF, SYSZ_INS_VCTZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCTZG, SYSZ_INS_VCTZG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCTZH, SYSZ_INS_VCTZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VCVB, SYSZ_INS_VCVB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VCVBG, SYSZ_INS_VCVBG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VCVD, SYSZ_INS_VCVD, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VCVDG, SYSZ_INS_VCVDG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VDP, SYSZ_INS_VDP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VEC, SYSZ_INS_VEC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECB, SYSZ_INS_VECB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECF, SYSZ_INS_VECF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECG, SYSZ_INS_VECG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECH, SYSZ_INS_VECH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECL, SYSZ_INS_VECL, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECLB, SYSZ_INS_VECLB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECLF, SYSZ_INS_VECLF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECLG, SYSZ_INS_VECLG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VECLH, SYSZ_INS_VECLH, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERIM, SYSZ_INS_VERIM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERIMB, SYSZ_INS_VERIMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERIMF, SYSZ_INS_VERIMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERIMG, SYSZ_INS_VERIMG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERIMH, SYSZ_INS_VERIMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLL, SYSZ_INS_VERLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLB, SYSZ_INS_VERLLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLF, SYSZ_INS_VERLLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLG, SYSZ_INS_VERLLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLH, SYSZ_INS_VERLLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLV, SYSZ_INS_VERLLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLVB, SYSZ_INS_VERLLVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLVF, SYSZ_INS_VERLLVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLVG, SYSZ_INS_VERLLVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VERLLVH, SYSZ_INS_VERLLVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESL, SYSZ_INS_VESL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLB, SYSZ_INS_VESLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLF, SYSZ_INS_VESLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLG, SYSZ_INS_VESLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLH, SYSZ_INS_VESLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLV, SYSZ_INS_VESLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLVB, SYSZ_INS_VESLVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLVF, SYSZ_INS_VESLVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLVG, SYSZ_INS_VESLVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESLVH, SYSZ_INS_VESLVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRA, SYSZ_INS_VESRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAB, SYSZ_INS_VESRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAF, SYSZ_INS_VESRAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAG, SYSZ_INS_VESRAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAH, SYSZ_INS_VESRAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAV, SYSZ_INS_VESRAV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAVB, SYSZ_INS_VESRAVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAVF, SYSZ_INS_VESRAVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAVG, SYSZ_INS_VESRAVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRAVH, SYSZ_INS_VESRAVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRL, SYSZ_INS_VESRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLB, SYSZ_INS_VESRLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLF, SYSZ_INS_VESRLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLG, SYSZ_INS_VESRLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLH, SYSZ_INS_VESRLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLV, SYSZ_INS_VESRLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLVB, SYSZ_INS_VESRLVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLVF, SYSZ_INS_VESRLVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLVG, SYSZ_INS_VESRLVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VESRLVH, SYSZ_INS_VESRLVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFA, SYSZ_INS_VFA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFADB, SYSZ_INS_VFADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAE, SYSZ_INS_VFAE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEB, SYSZ_INS_VFAEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEBS, SYSZ_INS_VFAEBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEF, SYSZ_INS_VFAEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEFS, SYSZ_INS_VFAEFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEH, SYSZ_INS_VFAEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEHS, SYSZ_INS_VFAEHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEZB, SYSZ_INS_VFAEZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEZBS, SYSZ_INS_VFAEZBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEZF, SYSZ_INS_VFAEZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEZFS, SYSZ_INS_VFAEZFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEZH, SYSZ_INS_VFAEZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFAEZHS, SYSZ_INS_VFAEZHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFASB, SYSZ_INS_VFASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFCE, SYSZ_INS_VFCE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCEDB, SYSZ_INS_VFCEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCEDBS, SYSZ_INS_VFCEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCESB, SYSZ_INS_VFCESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFCESBS, SYSZ_INS_VFCESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFCH, SYSZ_INS_VFCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCHDB, SYSZ_INS_VFCHDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCHDBS, SYSZ_INS_VFCHDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCHE, SYSZ_INS_VFCHE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCHEDB, SYSZ_INS_VFCHEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCHEDBS, SYSZ_INS_VFCHEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFCHESB, SYSZ_INS_VFCHESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFCHESBS, SYSZ_INS_VFCHESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFCHSB, SYSZ_INS_VFCHSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFCHSBS, SYSZ_INS_VFCHSBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFD, SYSZ_INS_VFD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFDDB, SYSZ_INS_VFDDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFDSB, SYSZ_INS_VFDSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFEE, SYSZ_INS_VFEE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEB, SYSZ_INS_VFEEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEBS, SYSZ_INS_VFEEBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEF, SYSZ_INS_VFEEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEFS, SYSZ_INS_VFEEFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEH, SYSZ_INS_VFEEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEHS, SYSZ_INS_VFEEHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEZB, SYSZ_INS_VFEEZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEZBS, SYSZ_INS_VFEEZBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEZF, SYSZ_INS_VFEEZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEZFS, SYSZ_INS_VFEEZFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEZH, SYSZ_INS_VFEEZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFEEZHS, SYSZ_INS_VFEEZHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENE, SYSZ_INS_VFENE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEB, SYSZ_INS_VFENEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEBS, SYSZ_INS_VFENEBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEF, SYSZ_INS_VFENEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEFS, SYSZ_INS_VFENEFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEH, SYSZ_INS_VFENEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEHS, SYSZ_INS_VFENEHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEZB, SYSZ_INS_VFENEZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEZBS, SYSZ_INS_VFENEZBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEZF, SYSZ_INS_VFENEZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEZFS, SYSZ_INS_VFENEZFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEZH, SYSZ_INS_VFENEZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFENEZHS, SYSZ_INS_VFENEZHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFI, SYSZ_INS_VFI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFIDB, SYSZ_INS_VFIDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFISB, SYSZ_INS_VFISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKEDB, SYSZ_INS_VFKEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKEDBS, SYSZ_INS_VFKEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKESB, SYSZ_INS_VFKESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKESBS, SYSZ_INS_VFKESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHDB, SYSZ_INS_VFKHDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHDBS, SYSZ_INS_VFKHDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHEDB, SYSZ_INS_VFKHEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHEDBS, SYSZ_INS_VFKHEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHESB, SYSZ_INS_VFKHESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHESBS, SYSZ_INS_VFKHESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHSB, SYSZ_INS_VFKHSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFKHSBS, SYSZ_INS_VFKHSBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLCDB, SYSZ_INS_VFLCDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFLCSB, SYSZ_INS_VFLCSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLL, SYSZ_INS_VFLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLLS, SYSZ_INS_VFLLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLNDB, SYSZ_INS_VFLNDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFLNSB, SYSZ_INS_VFLNSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLPDB, SYSZ_INS_VFLPDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFLPSB, SYSZ_INS_VFLPSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLR, SYSZ_INS_VFLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFLRD, SYSZ_INS_VFLRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFM, SYSZ_INS_VFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFMA, SYSZ_INS_VFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFMADB, SYSZ_INS_VFMADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFMASB, SYSZ_INS_VFMASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMAX, SYSZ_INS_VFMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMAXDB, SYSZ_INS_VFMAXDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMAXSB, SYSZ_INS_VFMAXSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMDB, SYSZ_INS_VFMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFMIN, SYSZ_INS_VFMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMINDB, SYSZ_INS_VFMINDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMINSB, SYSZ_INS_VFMINSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMS, SYSZ_INS_VFMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFMSB, SYSZ_INS_VFMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFMSDB, SYSZ_INS_VFMSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFMSSB, SYSZ_INS_VFMSSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFNMA, SYSZ_INS_VFNMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFNMADB, SYSZ_INS_VFNMADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFNMASB, SYSZ_INS_VFNMASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFNMS, SYSZ_INS_VFNMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFNMSDB, SYSZ_INS_VFNMSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFNMSSB, SYSZ_INS_VFNMSSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFPSO, SYSZ_INS_VFPSO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFPSODB, SYSZ_INS_VFPSODB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFPSOSB, SYSZ_INS_VFPSOSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFS, SYSZ_INS_VFS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFSDB, SYSZ_INS_VFSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFSQ, SYSZ_INS_VFSQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFSQDB, SYSZ_INS_VFSQDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFSQSB, SYSZ_INS_VFSQSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFSSB, SYSZ_INS_VFSSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VFTCI, SYSZ_INS_VFTCI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFTCIDB, SYSZ_INS_VFTCIDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VFTCISB, SYSZ_INS_VFTCISB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VGBM, SYSZ_INS_VGBM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGEF, SYSZ_INS_VGEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGEG, SYSZ_INS_VGEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFM, SYSZ_INS_VGFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMA, SYSZ_INS_VGFMA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMAB, SYSZ_INS_VGFMAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMAF, SYSZ_INS_VGFMAF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMAG, SYSZ_INS_VGFMAG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMAH, SYSZ_INS_VGFMAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMB, SYSZ_INS_VGFMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMF, SYSZ_INS_VGFMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMG, SYSZ_INS_VGFMG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGFMH, SYSZ_INS_VGFMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGM, SYSZ_INS_VGM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGMB, SYSZ_INS_VGMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGMF, SYSZ_INS_VGMF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGMG, SYSZ_INS_VGMG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VGMH, SYSZ_INS_VGMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTR, SYSZ_INS_VISTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTRB, SYSZ_INS_VISTRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTRBS, SYSZ_INS_VISTRBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTRF, SYSZ_INS_VISTRF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTRFS, SYSZ_INS_VISTRFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTRH, SYSZ_INS_VISTRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VISTRHS, SYSZ_INS_VISTRHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VL, SYSZ_INS_VL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLBB, SYSZ_INS_VLBB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLC, SYSZ_INS_VLC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLCB, SYSZ_INS_VLCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLCF, SYSZ_INS_VLCF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLCG, SYSZ_INS_VLCG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLCH, SYSZ_INS_VLCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLDE, SYSZ_INS_VLDE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLDEB, SYSZ_INS_VLDEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEB, SYSZ_INS_VLEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLED, SYSZ_INS_VLED, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEDB, SYSZ_INS_VLEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEF, SYSZ_INS_VLEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEG, SYSZ_INS_VLEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEH, SYSZ_INS_VLEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEIB, SYSZ_INS_VLEIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEIF, SYSZ_INS_VLEIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEIG, SYSZ_INS_VLEIG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLEIH, SYSZ_INS_VLEIH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLGV, SYSZ_INS_VLGV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLGVB, SYSZ_INS_VLGVB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLGVF, SYSZ_INS_VLGVF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLGVG, SYSZ_INS_VLGVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLGVH, SYSZ_INS_VLGVH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLIP, SYSZ_INS_VLIP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VLL, SYSZ_INS_VLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLLEZ, SYSZ_INS_VLLEZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLLEZB, SYSZ_INS_VLLEZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLLEZF, SYSZ_INS_VLLEZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLLEZG, SYSZ_INS_VLLEZG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLLEZH, SYSZ_INS_VLLEZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLLEZLF, SYSZ_INS_VLLEZLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VLM, SYSZ_INS_VLM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLP, SYSZ_INS_VLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLPB, SYSZ_INS_VLPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLPF, SYSZ_INS_VLPF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLPG, SYSZ_INS_VLPG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLPH, SYSZ_INS_VLPH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLR, SYSZ_INS_VLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLREP, SYSZ_INS_VLREP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLREPB, SYSZ_INS_VLREPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLREPF, SYSZ_INS_VLREPF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLREPG, SYSZ_INS_VLREPG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLREPH, SYSZ_INS_VLREPH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLRL, SYSZ_INS_VLRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VLRLR, SYSZ_INS_VLRLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VLVG, SYSZ_INS_VLVG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLVGB, SYSZ_INS_VLVGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLVGF, SYSZ_INS_VLVGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLVGG, SYSZ_INS_VLVGG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLVGH, SYSZ_INS_VLVGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VLVGP, SYSZ_INS_VLVGP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAE, SYSZ_INS_VMAE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAEB, SYSZ_INS_VMAEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAEF, SYSZ_INS_VMAEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAEH, SYSZ_INS_VMAEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAH, SYSZ_INS_VMAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAHB, SYSZ_INS_VMAHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAHF, SYSZ_INS_VMAHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAHH, SYSZ_INS_VMAHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAL, SYSZ_INS_VMAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALB, SYSZ_INS_VMALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALE, SYSZ_INS_VMALE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALEB, SYSZ_INS_VMALEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALEF, SYSZ_INS_VMALEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALEH, SYSZ_INS_VMALEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALF, SYSZ_INS_VMALF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALH, SYSZ_INS_VMALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALHB, SYSZ_INS_VMALHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALHF, SYSZ_INS_VMALHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALHH, SYSZ_INS_VMALHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALHW, SYSZ_INS_VMALHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALO, SYSZ_INS_VMALO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALOB, SYSZ_INS_VMALOB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALOF, SYSZ_INS_VMALOF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMALOH, SYSZ_INS_VMALOH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAO, SYSZ_INS_VMAO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAOB, SYSZ_INS_VMAOB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAOF, SYSZ_INS_VMAOF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMAOH, SYSZ_INS_VMAOH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VME, SYSZ_INS_VME, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMEB, SYSZ_INS_VMEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMEF, SYSZ_INS_VMEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMEH, SYSZ_INS_VMEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMH, SYSZ_INS_VMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMHB, SYSZ_INS_VMHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMHF, SYSZ_INS_VMHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMHH, SYSZ_INS_VMHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VML, SYSZ_INS_VML, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLB, SYSZ_INS_VMLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLE, SYSZ_INS_VMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLEB, SYSZ_INS_VMLEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLEF, SYSZ_INS_VMLEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLEH, SYSZ_INS_VMLEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLF, SYSZ_INS_VMLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLH, SYSZ_INS_VMLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLHB, SYSZ_INS_VMLHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLHF, SYSZ_INS_VMLHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLHH, SYSZ_INS_VMLHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLHW, SYSZ_INS_VMLHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLO, SYSZ_INS_VMLO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLOB, SYSZ_INS_VMLOB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLOF, SYSZ_INS_VMLOF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMLOH, SYSZ_INS_VMLOH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMN, SYSZ_INS_VMN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNB, SYSZ_INS_VMNB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNF, SYSZ_INS_VMNF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNG, SYSZ_INS_VMNG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNH, SYSZ_INS_VMNH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNL, SYSZ_INS_VMNL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNLB, SYSZ_INS_VMNLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNLF, SYSZ_INS_VMNLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNLG, SYSZ_INS_VMNLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMNLH, SYSZ_INS_VMNLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMO, SYSZ_INS_VMO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMOB, SYSZ_INS_VMOB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMOF, SYSZ_INS_VMOF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMOH, SYSZ_INS_VMOH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMP, SYSZ_INS_VMP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VMRH, SYSZ_INS_VMRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRHB, SYSZ_INS_VMRHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRHF, SYSZ_INS_VMRHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRHG, SYSZ_INS_VMRHG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRHH, SYSZ_INS_VMRHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRL, SYSZ_INS_VMRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRLB, SYSZ_INS_VMRLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRLF, SYSZ_INS_VMRLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRLG, SYSZ_INS_VMRLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMRLH, SYSZ_INS_VMRLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMSL, SYSZ_INS_VMSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VMSLG, SYSZ_INS_VMSLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VMSP, SYSZ_INS_VMSP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VMX, SYSZ_INS_VMX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXB, SYSZ_INS_VMXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXF, SYSZ_INS_VMXF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXG, SYSZ_INS_VMXG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXH, SYSZ_INS_VMXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXL, SYSZ_INS_VMXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXLB, SYSZ_INS_VMXLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXLF, SYSZ_INS_VMXLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXLG, SYSZ_INS_VMXLG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VMXLH, SYSZ_INS_VMXLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VN, SYSZ_INS_VN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VNC, SYSZ_INS_VNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VNN, SYSZ_INS_VNN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VNO, SYSZ_INS_VNO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VNX, SYSZ_INS_VNX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VO, SYSZ_INS_VO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VOC, SYSZ_INS_VOC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VONE, SYSZ_INS_VONE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPDI, SYSZ_INS_VPDI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPERM, SYSZ_INS_VPERM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPK, SYSZ_INS_VPK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKF, SYSZ_INS_VPKF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKG, SYSZ_INS_VPKG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKH, SYSZ_INS_VPKH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLS, SYSZ_INS_VPKLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLSF, SYSZ_INS_VPKLSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLSFS, SYSZ_INS_VPKLSFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLSG, SYSZ_INS_VPKLSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLSGS, SYSZ_INS_VPKLSGS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLSH, SYSZ_INS_VPKLSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKLSHS, SYSZ_INS_VPKLSHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKS, SYSZ_INS_VPKS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKSF, SYSZ_INS_VPKSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKSFS, SYSZ_INS_VPKSFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKSG, SYSZ_INS_VPKSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKSGS, SYSZ_INS_VPKSGS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKSH, SYSZ_INS_VPKSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKSHS, SYSZ_INS_VPKSHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPKZ, SYSZ_INS_VPKZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VPOPCT, SYSZ_INS_VPOPCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VPOPCTB, SYSZ_INS_VPOPCTB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VPOPCTF, SYSZ_INS_VPOPCTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VPOPCTG, SYSZ_INS_VPOPCTG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VPOPCTH, SYSZ_INS_VPOPCTH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_VPSOP, SYSZ_INS_VPSOP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VREP, SYSZ_INS_VREP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPB, SYSZ_INS_VREPB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPF, SYSZ_INS_VREPF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPG, SYSZ_INS_VREPG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPH, SYSZ_INS_VREPH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPI, SYSZ_INS_VREPI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPIB, SYSZ_INS_VREPIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPIF, SYSZ_INS_VREPIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPIG, SYSZ_INS_VREPIG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VREPIH, SYSZ_INS_VREPIH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VRP, SYSZ_INS_VRP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VS, SYSZ_INS_VS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSB, SYSZ_INS_VSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSBCBI, SYSZ_INS_VSBCBI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSBCBIQ, SYSZ_INS_VSBCBIQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSBI, SYSZ_INS_VSBI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSBIQ, SYSZ_INS_VSBIQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCBI, SYSZ_INS_VSCBI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCBIB, SYSZ_INS_VSCBIB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCBIF, SYSZ_INS_VSCBIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCBIG, SYSZ_INS_VSCBIG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCBIH, SYSZ_INS_VSCBIH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCBIQ, SYSZ_INS_VSCBIQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCEF, SYSZ_INS_VSCEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSCEG, SYSZ_INS_VSCEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSDP, SYSZ_INS_VSDP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VSEG, SYSZ_INS_VSEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSEGB, SYSZ_INS_VSEGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSEGF, SYSZ_INS_VSEGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSEGH, SYSZ_INS_VSEGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSEL, SYSZ_INS_VSEL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSF, SYSZ_INS_VSF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSG, SYSZ_INS_VSG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSH, SYSZ_INS_VSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSL, SYSZ_INS_VSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSLB, SYSZ_INS_VSLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSLDB, SYSZ_INS_VSLDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSP, SYSZ_INS_VSP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VSQ, SYSZ_INS_VSQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSRA, SYSZ_INS_VSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSRAB, SYSZ_INS_VSRAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSRL, SYSZ_INS_VSRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSRLB, SYSZ_INS_VSRLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSRP, SYSZ_INS_VSRP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VST, SYSZ_INS_VST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTEB, SYSZ_INS_VSTEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTEF, SYSZ_INS_VSTEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTEG, SYSZ_INS_VSTEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTEH, SYSZ_INS_VSTEH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTL, SYSZ_INS_VSTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTM, SYSZ_INS_VSTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRC, SYSZ_INS_VSTRC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCB, SYSZ_INS_VSTRCB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCBS, SYSZ_INS_VSTRCBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCF, SYSZ_INS_VSTRCF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCFS, SYSZ_INS_VSTRCFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCH, SYSZ_INS_VSTRCH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCHS, SYSZ_INS_VSTRCHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCZB, SYSZ_INS_VSTRCZB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCZBS, SYSZ_INS_VSTRCZBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCZF, SYSZ_INS_VSTRCZF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCZFS, SYSZ_INS_VSTRCZFS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCZH, SYSZ_INS_VSTRCZH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRCZHS, SYSZ_INS_VSTRCZHS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSTRL, SYSZ_INS_VSTRL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VSTRLR, SYSZ_INS_VSTRLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VSUM, SYSZ_INS_VSUM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMB, SYSZ_INS_VSUMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMG, SYSZ_INS_VSUMG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMGF, SYSZ_INS_VSUMGF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMGH, SYSZ_INS_VSUMGH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMH, SYSZ_INS_VSUMH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMQ, SYSZ_INS_VSUMQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMQF, SYSZ_INS_VSUMQF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VSUMQG, SYSZ_INS_VSUMQG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VTM, SYSZ_INS_VTM, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VTP, SYSZ_INS_VTP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VUPH, SYSZ_INS_VUPH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPHB, SYSZ_INS_VUPHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPHF, SYSZ_INS_VUPHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPHH, SYSZ_INS_VUPHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPKZ, SYSZ_INS_VUPKZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORPACKEDDECIMAL, 0 }, 0, 0 #endif }, { SystemZ_VUPL, SYSZ_INS_VUPL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLB, SYSZ_INS_VUPLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLF, SYSZ_INS_VUPLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLH, SYSZ_INS_VUPLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLHB, SYSZ_INS_VUPLHB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLHF, SYSZ_INS_VUPLHF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLHH, SYSZ_INS_VUPLHH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLHW, SYSZ_INS_VUPLHW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLL, SYSZ_INS_VUPLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLLB, SYSZ_INS_VUPLLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLLF, SYSZ_INS_VUPLLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VUPLLH, SYSZ_INS_VUPLLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VX, SYSZ_INS_VX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_VZERO, SYSZ_INS_VZERO, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WCDGB, SYSZ_INS_WCDGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WCDLGB, SYSZ_INS_WCDLGB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WCGDB, SYSZ_INS_WCGDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WCLGDB, SYSZ_INS_WCLGDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFADB, SYSZ_INS_WFADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFASB, SYSZ_INS_WFASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFAXB, SYSZ_INS_WFAXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFC, SYSZ_INS_WFC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCDB, SYSZ_INS_WFCDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCEDB, SYSZ_INS_WFCEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCEDBS, SYSZ_INS_WFCEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCESB, SYSZ_INS_WFCESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCESBS, SYSZ_INS_WFCESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCEXB, SYSZ_INS_WFCEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCEXBS, SYSZ_INS_WFCEXBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHDB, SYSZ_INS_WFCHDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCHDBS, SYSZ_INS_WFCHDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCHEDB, SYSZ_INS_WFCHEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCHEDBS, SYSZ_INS_WFCHEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFCHESB, SYSZ_INS_WFCHESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHESBS, SYSZ_INS_WFCHESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHEXB, SYSZ_INS_WFCHEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHEXBS, SYSZ_INS_WFCHEXBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHSB, SYSZ_INS_WFCHSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHSBS, SYSZ_INS_WFCHSBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHXB, SYSZ_INS_WFCHXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCHXBS, SYSZ_INS_WFCHXBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCSB, SYSZ_INS_WFCSB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFCXB, SYSZ_INS_WFCXB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFDDB, SYSZ_INS_WFDDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFDSB, SYSZ_INS_WFDSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFDXB, SYSZ_INS_WFDXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFIDB, SYSZ_INS_WFIDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFISB, SYSZ_INS_WFISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFIXB, SYSZ_INS_WFIXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFK, SYSZ_INS_WFK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFKDB, SYSZ_INS_WFKDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFKEDB, SYSZ_INS_WFKEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKEDBS, SYSZ_INS_WFKEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKESB, SYSZ_INS_WFKESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKESBS, SYSZ_INS_WFKESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKEXB, SYSZ_INS_WFKEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKEXBS, SYSZ_INS_WFKEXBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHDB, SYSZ_INS_WFKHDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHDBS, SYSZ_INS_WFKHDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHEDB, SYSZ_INS_WFKHEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHEDBS, SYSZ_INS_WFKHEDBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHESB, SYSZ_INS_WFKHESB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHESBS, SYSZ_INS_WFKHESBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHEXB, SYSZ_INS_WFKHEXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHEXBS, SYSZ_INS_WFKHEXBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHSB, SYSZ_INS_WFKHSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHSBS, SYSZ_INS_WFKHSBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHXB, SYSZ_INS_WFKHXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKHXBS, SYSZ_INS_WFKHXBS, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKSB, SYSZ_INS_WFKSB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFKXB, SYSZ_INS_WFKXB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLCDB, SYSZ_INS_WFLCDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFLCSB, SYSZ_INS_WFLCSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLCXB, SYSZ_INS_WFLCXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLLD, SYSZ_INS_WFLLD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLLS, SYSZ_INS_WFLLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLNDB, SYSZ_INS_WFLNDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFLNSB, SYSZ_INS_WFLNSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLNXB, SYSZ_INS_WFLNXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLPDB, SYSZ_INS_WFLPDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFLPSB, SYSZ_INS_WFLPSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLPXB, SYSZ_INS_WFLPXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLRD, SYSZ_INS_WFLRD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFLRX, SYSZ_INS_WFLRX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMADB, SYSZ_INS_WFMADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFMASB, SYSZ_INS_WFMASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMAXB, SYSZ_INS_WFMAXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMAXDB, SYSZ_INS_WFMAXDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMAXSB, SYSZ_INS_WFMAXSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMAXXB, SYSZ_INS_WFMAXXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMDB, SYSZ_INS_WFMDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFMINDB, SYSZ_INS_WFMINDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMINSB, SYSZ_INS_WFMINSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMINXB, SYSZ_INS_WFMINXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMSB, SYSZ_INS_WFMSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMSDB, SYSZ_INS_WFMSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFMSSB, SYSZ_INS_WFMSSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMSXB, SYSZ_INS_WFMSXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFMXB, SYSZ_INS_WFMXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFNMADB, SYSZ_INS_WFNMADB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFNMASB, SYSZ_INS_WFNMASB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFNMAXB, SYSZ_INS_WFNMAXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFNMSDB, SYSZ_INS_WFNMSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFNMSSB, SYSZ_INS_WFNMSSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFNMSXB, SYSZ_INS_WFNMSXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFPSODB, SYSZ_INS_WFPSODB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFPSOSB, SYSZ_INS_WFPSOSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFPSOXB, SYSZ_INS_WFPSOXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFSDB, SYSZ_INS_WFSDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFSQDB, SYSZ_INS_WFSQDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFSQSB, SYSZ_INS_WFSQSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFSQXB, SYSZ_INS_WFSQXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFSSB, SYSZ_INS_WFSSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFSXB, SYSZ_INS_WFSXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFTCIDB, SYSZ_INS_WFTCIDB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WFTCISB, SYSZ_INS_WFTCISB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WFTCIXB, SYSZ_INS_WFTCIXB, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_VECTORENHANCEMENTS1, 0 }, 0, 0 #endif }, { SystemZ_WLDEB, SYSZ_INS_WLDEB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_WLEDB, SYSZ_INS_WLEDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { SYSZ_GRP_VECTOR, 0 }, 0, 0 #endif }, { SystemZ_X, SYSZ_INS_X, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XC, SYSZ_INS_XC, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XG, SYSZ_INS_XG, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XGR, SYSZ_INS_XGR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XGRK, SYSZ_INS_XGRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_XI, SYSZ_INS_XI, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XIHF, SYSZ_INS_XIHF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XILF, SYSZ_INS_XILF, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XIY, SYSZ_INS_XIY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XR, SYSZ_INS_XR, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XRK, SYSZ_INS_XRK, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { SYSZ_GRP_DISTINCTOPS, 0 }, 0, 0 #endif }, { SystemZ_XSCH, SYSZ_INS_XSCH, #ifndef CAPSTONE_DIET { SYSZ_REG_1, 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_XY, SYSZ_INS_XY, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, { SystemZ_ZAP, SYSZ_INS_ZAP, #ifndef CAPSTONE_DIET { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZModule.c000064400000000000000000000020210072674642500214610ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_SYSZ #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "SystemZDisassembler.h" #include "SystemZInstPrinter.h" #include "SystemZMapping.h" #include "SystemZModule.h" cs_err SystemZ_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); SystemZ_init(mri); ud->printer = SystemZ_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = SystemZ_getInstruction; ud->post_printer = SystemZ_post_printer; ud->reg_name = SystemZ_reg_name; ud->insn_id = SystemZ_get_insn_id; ud->insn_name = SystemZ_insn_name; ud->group_name = SystemZ_group_name; return CS_ERR_OK; } cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_SYNTAX) handle->syntax = (int) value; // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot // test for CS_MODE_LITTLE_ENDIAN because it is 0 return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/SystemZ/SystemZModule.h000064400000000000000000000004510072674642500214730ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_SYSTEMZ_MODULE_H #define CS_SYSTEMZ_MODULE_H #include "../../utils.h" cs_err SystemZ_global_init(cs_struct *ud); cs_err SystemZ_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c000064400000000000000000000402010072674642500225110ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifdef CAPSTONE_HAS_TMS320C64X #include #include "../../cs_priv.h" #include "../../utils.h" #include "TMS320C64xDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" static uint64_t getFeatureBits(int mode); static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder); static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder); static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder); static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder); static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder); #include "TMS320C64xGenDisassemblerTables.inc" #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "TMS320C64xGenRegisterInfo.inc" static const unsigned GPRegsDecoderTable[] = { TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31 }; static const unsigned ControlRegsDecoderTable[] = { TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_ISR, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_ISTP, TMS320C64x_IRP, TMS320C64x_NRP, ~0U, ~0U, TMS320C64x_TSCL, TMS320C64x_TSCH, ~0U, TMS320C64x_ILC, TMS320C64x_RILC, TMS320C64x_REP, TMS320C64x_PCE1, TMS320C64x_DNUM, ~0U, ~0U, ~0U, TMS320C64x_SSR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_GFPGFR, TMS320C64x_DIER, TMS320C64x_TSR, TMS320C64x_ITSR, TMS320C64x_NTSR, TMS320C64x_ECR, ~0U, TMS320C64x_IERR }; static uint64_t getFeatureBits(int mode) { // support everything return (uint64_t)-1; } static unsigned getReg(const unsigned *RegTable, unsigned RegNo) { if(RegNo > 31) return ~0U; return RegTable[RegNo]; } static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder) { unsigned Reg; if(RegNo > 31) return MCDisassembler_Fail; Reg = getReg(GPRegsDecoderTable, RegNo); if(Reg == ~0U) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder) { unsigned Reg; if(RegNo > 31) return MCDisassembler_Fail; Reg = getReg(ControlRegsDecoderTable, RegNo); if(Reg == ~0U) return MCDisassembler_Fail; MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { int32_t imm; imm = Val; /* Sign extend 5 bit value */ if(imm & (1 << (5 - 1))) imm |= ~((1 << 5) - 1); MCOperand_CreateImm0(Inst, imm); return MCDisassembler_Success; } static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { int32_t imm; imm = Val; /* Sign extend 16 bit value */ if(imm & (1 << (16 - 1))) imm |= ~((1 << 16) - 1); MCOperand_CreateImm0(Inst, imm); return MCDisassembler_Success; } static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { int32_t imm; imm = Val; /* Sign extend 7 bit value */ if(imm & (1 << (7 - 1))) imm |= ~((1 << 7) - 1); /* Address is relative to the address of the first instruction in the fetch packet */ MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); return MCDisassembler_Success; } static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { int32_t imm; imm = Val; /* Sign extend 10 bit value */ if(imm & (1 << (10 - 1))) imm |= ~((1 << 10) - 1); /* Address is relative to the address of the first instruction in the fetch packet */ MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); return MCDisassembler_Success; } static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { int32_t imm; imm = Val; /* Sign extend 12 bit value */ if(imm & (1 << (12 - 1))) imm |= ~((1 << 12) - 1); /* Address is relative to the address of the first instruction in the fetch packet */ MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); return MCDisassembler_Success; } static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { int32_t imm; imm = Val; /* Sign extend 21 bit value */ if(imm & (1 << (21 - 1))) imm |= ~((1 << 21) - 1); /* Address is relative to the address of the first instruction in the fetch packet */ MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4)); return MCDisassembler_Success; } static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder); } static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { uint8_t scaled, base, offset, mode, unit; unsigned basereg, offsetreg; scaled = (Val >> 15) & 1; base = (Val >> 10) & 0x1f; offset = (Val >> 5) & 0x1f; mode = (Val >> 1) & 0xf; unit = Val & 1; if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31)) base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); else if((base >= TMS320C64X_REG_B0) && (base <= TMS320C64X_REG_B31)) base = (base - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); basereg = getReg(GPRegsDecoderTable, base); if (basereg == ~0U) return MCDisassembler_Fail; switch(mode) { case 0: case 1: case 8: case 9: case 10: case 11: MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offset << 5) | (mode << 1) | unit); break; case 4: case 5: case 12: case 13: case 14: case 15: if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31)) offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); else if((offset >= TMS320C64X_REG_B0) && (offset <= TMS320C64X_REG_B31)) offset = (offset - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); offsetreg = getReg(GPRegsDecoderTable, offset); if (offsetreg == ~0U) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit); break; default: return MCDisassembler_Fail; } return MCDisassembler_Success; } static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { uint16_t offset; unsigned basereg; if(Val & 1) basereg = TMS320C64X_REG_B15; else basereg = TMS320C64X_REG_B14; offset = (Val >> 1) & 0x7fff; MCOperand_CreateImm0(Inst, (offset << 7) | basereg); return MCDisassembler_Success; } static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder) { unsigned Reg; if(RegNo > 31) return MCDisassembler_Fail; Reg = getReg(GPRegsDecoderTable, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo, uint64_t Address, void *Decoder) { unsigned Reg; if(RegNo > 15) return MCDisassembler_Fail; Reg = getReg(GPRegsDecoderTable, RegNo << 1); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: case 7: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID; break; case 1: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B0; break; case 2: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B1; break; case 3: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B2; break; case 4: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A1; break; case 5: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A2; break; case 6: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A0; break; default: Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: Inst->flat_insn->detail->tms320c64x.condition.zero = 0; break; case 1: Inst->flat_insn->detail->tms320c64x.condition.zero = 1; break; default: Inst->flat_insn->detail->tms320c64x.condition.zero = 0; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; MCOperand *op; int i; /* This is pretty messy, probably we should find a better way */ if(Val == 1) { for(i = 0; i < Inst->size; i++) { op = &Inst->Operands[i]; if(op->Kind == kRegister) { if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); } } } if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: Inst->flat_insn->detail->tms320c64x.funit.side = 1; break; case 1: Inst->flat_insn->detail->tms320c64x.funit.side = 2; break; default: Inst->flat_insn->detail->tms320c64x.funit.side = 0; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: Inst->flat_insn->detail->tms320c64x.parallel = 0; break; case 1: Inst->flat_insn->detail->tms320c64x.parallel = 1; break; default: Inst->flat_insn->detail->tms320c64x.parallel = -1; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; MCOperand *op; if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; break; case 1: Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; op = &Inst->Operands[0]; if(op->Kind == kRegister) { if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); } break; default: Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; MCOperand *op; if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; break; case 1: Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1; op = &Inst->Operands[1]; if(op->Kind == kRegister) { if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); } break; default: Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { DecodeStatus ret = MCDisassembler_Success; MCOperand *op; if(!Inst->flat_insn->detail) return MCDisassembler_Success; switch(Val) { case 0: Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0; break; case 1: Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2; op = &Inst->Operands[2]; if(op->Kind == kRegister) { if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31)) op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0); else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31)) op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0); } break; default: Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1; ret = MCDisassembler_Fail; break; } return ret; } static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address, void *Decoder) { MCOperand_CreateImm0(Inst, Val + 1); return MCDisassembler_Success; } #define GET_INSTRINFO_ENUM #include "TMS320C64xGenInstrInfo.inc" bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *info) { uint32_t insn; DecodeStatus result; if(code_len < 4) { *size = 0; return MCDisassembler_Fail; } if(MI->flat_insn->detail) memset(MI->flat_insn->detail, 0, offsetof(cs_detail, tms320c64x)+sizeof(cs_tms320c64x)); insn = (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24); result = decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0); if(result == MCDisassembler_Success) { *size = 4; return true; } MCInst_clear(MI); *size = 0; return false; } void TMS320C64x_init(MCRegisterInfo *MRI) { MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, 0, 0, TMS320C64xMCRegisterClasses, 7, 0, 0, TMS320C64xRegDiffLists, 0, TMS320C64xSubRegIdxLists, 1, 0); } #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h000064400000000000000000000007350072674642500225260ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifndef CS_TMS320C64XDISASSEMBLER_H #define CS_TMS320C64XDISASSEMBLER_H #include #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void TMS320C64x_init(MCRegisterInfo *MRI); bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc000064400000000000000000000513500072674642500230010ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #include /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { static const uint32_t OpInfo[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 882U, // DBG_VALUE 0U, // REG_SEQUENCE 0U, // COPY 875U, // BUNDLE 904U, // LIFETIME_START 862U, // LIFETIME_END 0U, // STACKMAP 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // FRAME_ALLOC 1126U, // ABS2_l2_rr 10847U, // ABS_l1_pp 1631U, // ABS_l1_rr 85006U, // ADD2_d2_rrr 85006U, // ADD2_l1_rrr_x2 85006U, // ADD2_s1_rrr 85171U, // ADD4_l1_rrr_x2 91479U, // ADDAB_d1_rir 91479U, // ADDAB_d1_rrr 91541U, // ADDAD_d1_rir 91541U, // ADDAD_d1_rrr 91577U, // ADDAH_d1_rir 91577U, // ADDAH_d1_rrr 91937U, // ADDAW_d1_rir 91937U, // ADDAW_d1_rrr 132488U, // ADDKPC_s3_iir 1518U, // ADDK_s2_ir 233140U, // ADDU_l1_rpp 216756U, // ADDU_l1_rrp_x2 91555U, // ADD_d1_rir 91555U, // ADD_d1_rrr 91555U, // ADD_d2_rir 85411U, // ADD_d2_rrr 232867U, // ADD_l1_ipp 85411U, // ADD_l1_irr 232867U, // ADD_l1_rpp 216483U, // ADD_l1_rrp_x2 85411U, // ADD_l1_rrr_x2 85411U, // ADD_s1_irr 85411U, // ADD_s1_rrr 85542U, // ANDN_d2_rrr 85542U, // ANDN_l1_rrr_x2 85542U, // ANDN_s4_rrr 85416U, // AND_d2_rir 85416U, // AND_d2_rrr 85416U, // AND_l1_irr 85416U, // AND_l1_rrr_x2 85416U, // AND_s1_irr 85416U, // AND_s1_rrr 85019U, // AVG2_m1_rrr 85232U, // AVGU4_m1_rrr 1410U, // BDEC_s8_ir 1196U, // BITC4_m2_rr 307756U, // BNOP_s10_ri 307756U, // BNOP_s9_ii 1654U, // BPOS_s8_ir 53588U, // B_s5_i 53588U, // B_s6_r 892U, // B_s7_irp 898U, // B_s7_nrp 353870U, // CLR_s15_riir 91726U, // CLR_s1_rrr 85080U, // CMPEQ2_s1_rrr 85207U, // CMPEQ4_s1_rrr 101938U, // CMPEQ_l1_ipr 85554U, // CMPEQ_l1_irr 101938U, // CMPEQ_l1_rpr 85554U, // CMPEQ_l1_rrr_x2 85109U, // CMPGT2_s1_rrr 85298U, // CMPGTU4_s1_rrr 102037U, // CMPGT_l1_ipr 85653U, // CMPGT_l1_irr 102037U, // CMPGT_l1_rpr 85653U, // CMPGT_l1_rrr_x2 102150U, // CMPLTU_l1_ipr 85766U, // CMPLTU_l1_irr 102150U, // CMPLTU_l1_rpr 85766U, // CMPLTU_l1_rrr_x2 102044U, // CMPLT_l1_ipr 85660U, // CMPLT_l1_irr 102044U, // CMPLT_l1_rpr 85660U, // CMPLT_l1_rrr_x2 1529U, // DEAL_m2_rr 216145U, // DOTP2_m1_rrp 85073U, // DOTP2_m1_rrr 85065U, // DOTPN2_m1_rrr 85124U, // DOTPNRSU2_m1_rrr 85135U, // DOTPRSU2_m1_rrr 85281U, // DOTPSU4_m1_rrr 85273U, // DOTPU4_m1_rrr 354062U, // EXTU_s15_riir 91918U, // EXTU_s1_rrr 353955U, // EXT_s15_riir 91811U, // EXT_s1_rrr 102142U, // GMPGTU_l1_ipr 85758U, // GMPGTU_l1_irr 102142U, // GMPGTU_l1_rpr 85758U, // GMPGTU_l1_rrr_x2 85321U, // GMPY4_m1_rrr 5800U, // LDBU_d5_mr 6824U, // LDBU_d6_mr 5470U, // LDB_d5_mr 6494U, // LDB_d6_mr 14120U, // LDDW_d7_mp 5818U, // LDHU_d5_mr 6842U, // LDHU_d6_mr 5568U, // LDH_d5_mr 6592U, // LDH_d6_mr 14131U, // LDNDW_d8_mp 5959U, // LDNW_d5_mr 5934U, // LDW_d5_mr 6958U, // LDW_d6_mr 85404U, // LMBD_l1_irr 85404U, // LMBD_l1_rrr_x2 85145U, // MAX2_l1_rrr_x2 85307U, // MAXU4_l1_rrr_x2 85059U, // MIN2_l1_rrr_x2 85266U, // MINU4_l1_rrr_x2 216224U, // MPY2_m1_rrp 85566U, // MPYHIR_m1_rrr 216544U, // MPYHI_m1_rrp 85720U, // MPYHLU_m4_rrr 85516U, // MPYHL_m4_rrr 85728U, // MPYHSLU_m4_rrr 85743U, // MPYHSU_m4_rrr 85613U, // MPYHULS_m4_rrr 85628U, // MPYHUS_m4_rrr 85713U, // MPYHU_m4_rrr 85466U, // MPYH_m4_rrr 85696U, // MPYLHU_m4_rrr 85453U, // MPYLH_m4_rrr 85574U, // MPYLIR_m1_rrr 216551U, // MPYLI_m1_rrp 85704U, // MPYLSHU_m4_rrr 85604U, // MPYLUHS_m4_rrr 216362U, // MPYSU4_m1_rrp 85751U, // MPYSU_m4_irr 85751U, // MPYSU_m4_rrr 216386U, // MPYU4_m1_rrp 85636U, // MPYUS_m4_rrr 85780U, // MPYU_m4_rrr 85849U, // MPY_m4_irr 85849U, // MPY_m4_rrr 1424U, // MVC_s1_rr 1424U, // MVC_s1_rr2 1453U, // MVD_m2_rr 1477U, // MVKLH_s12_ir 1524U, // MVKL_s12_ir 1524U, // MVK_d1_rr 1524U, // MVK_l2_ir 53249U, // NOP_n 2592U, // NORM_l1_pr 1568U, // NORM_l1_rr 85588U, // OR_d2_rir 85588U, // OR_d2_rrr 85588U, // OR_l1_irr 85588U, // OR_l1_rrr_x2 85588U, // OR_s1_irr 85588U, // OR_s1_rrr 85043U, // PACK2_l1_rrr_x2 85043U, // PACK2_s4_rrr 85025U, // PACKH2_l1_rrr_x2 85025U, // PACKH2_s1_rrr 85184U, // PACKH4_l1_rrr_x2 85050U, // PACKHL2_l1_rrr_x2 85050U, // PACKHL2_s1_rrr 85192U, // PACKL4_l1_rrr_x2 85033U, // PACKLH2_l1_rrr_x2 85033U, // PACKLH2_s1_rrr 91667U, // ROTL_m1_rir 91667U, // ROTL_m1_rrr 85005U, // SADD2_s4_rrr 85224U, // SADDU4_s4_rrr 85100U, // SADDUS2_s4_rrr 232866U, // SADD_l1_ipp 85410U, // SADD_l1_irr 232866U, // SADD_l1_rpp 85410U, // SADD_l1_rrr_x2 85410U, // SADD_s1_rrr 2699U, // SAT_l1_pr 353936U, // SET_s15_riir 91792U, // SET_s1_rrr 1535U, // SHFL_m2_rr 85347U, // SHLMB_l1_rrr_x2 85347U, // SHLMB_s4_rrr 223750U, // SHL_s1_pip 223750U, // SHL_s1_prp 222726U, // SHL_s1_rip 91654U, // SHL_s1_rir 222726U, // SHL_s1_rrp 91654U, // SHL_s1_rrr 91232U, // SHR2_s1_rir 91232U, // SHR2_s4_rrr 85354U, // SHRMB_l1_rrr_x2 85354U, // SHRMB_s4_rrr 91261U, // SHRU2_s1_rir 91261U, // SHRU2_s4_rrr 223977U, // SHRU_s1_pip 223977U, // SHRU_s1_prp 91881U, // SHRU_s1_rir 91881U, // SHRU_s1_rrr 223801U, // SHR_s1_pip 223801U, // SHR_s1_prp 91705U, // SHR_s1_rir 91705U, // SHR_s1_rrr 216223U, // SMPY2_m1_rrp 85515U, // SMPYHL_m4_rrr 85465U, // SMPYH_m4_rrr 85452U, // SMPYLH_m4_rrr 85848U, // SMPY_m4_rrr 85042U, // SPACK2_s4_rrr 85248U, // SPACKU4_s4_rrr 91653U, // SSHL_s1_rir 91653U, // SSHL_s1_rrr 85529U, // SSHVL_m1_rrr 85592U, // SSHVR_m1_rrr 232822U, // SSUB_l1_ipp 85366U, // SSUB_l1_irr 85366U, // SSUB_l1_rrr_x1 85366U, // SSUB_l1_rrr_x2 438641U, // STB_d5_rm 504177U, // STB_d6_rm 8001U, // STDW_d7_pm 438740U, // STH_d5_rm 504276U, // STH_d6_rm 7994U, // STNDW_d8_pm 439117U, // STNW_d5_rm 439123U, // STW_d5_rm 504659U, // STW_d6_rm 84999U, // SUB2_d2_rrr 84999U, // SUB2_l1_rrr_x2 84999U, // SUB2_s1_rrr 85158U, // SUB4_l1_rrr_x2 85215U, // SUBABS4_l1_rrr_x2 91472U, // SUBAB_d1_rir 91472U, // SUBAB_d1_rrr 91472U, // SUBAH_d1_rir 91570U, // SUBAH_d1_rrr 91472U, // SUBAW_d1_rir 91930U, // SUBAW_d1_rrr 85372U, // SUBC_l1_rrr_x2 216750U, // SUBU_l1_rrp_x1 216750U, // SUBU_l1_rrp_x2 91511U, // SUB_d1_rir 91511U, // SUB_d1_rrr 85367U, // SUB_d2_rrr 232823U, // SUB_l1_ipp 85367U, // SUB_l1_irr 216439U, // SUB_l1_rrp_x1 216439U, // SUB_l1_rrp_x2 85367U, // SUB_l1_rrr_x1 85367U, // SUB_l1_rrr_x2 85367U, // SUB_s1_irr 85367U, // SUB_s1_rrr 91511U, // SUB_s4_rrr 1232U, // SWAP4_l2_rr 1271U, // UNPKHU4_l2_rr 1271U, // UNPKHU4_s14_rr 1289U, // UNPKLU4_l2_rr 1289U, // UNPKLU4_s14_rr 85587U, // XOR_d2_rir 85587U, // XOR_d2_rrr 85587U, // XOR_l1_irr 85587U, // XOR_l1_rrr_x2 85587U, // XOR_s1_irr 85587U, // XOR_s1_rrr 1044U, // XPND2_m2_rr 1209U, // XPND4_m2_rr 0U }; static const char AsmStrs[] = { /* 0 */ 'n', 'o', 'p', 9, 9, 0, /* 6 */ 's', 'u', 'b', '2', 9, 0, /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0, /* 19 */ 'x', 'p', 'n', 'd', '2', 9, 0, /* 26 */ 'a', 'v', 'g', '2', 9, 0, /* 32 */ 'p', 'a', 'c', 'k', 'h', '2', 9, 0, /* 40 */ 'p', 'a', 'c', 'k', 'l', 'h', '2', 9, 0, /* 49 */ 's', 'p', 'a', 'c', 'k', '2', 9, 0, /* 57 */ 'p', 'a', 'c', 'k', 'h', 'l', '2', 9, 0, /* 66 */ 'm', 'i', 'n', '2', 9, 0, /* 72 */ 'd', 'o', 't', 'p', 'n', '2', 9, 0, /* 80 */ 'd', 'o', 't', 'p', '2', 9, 0, /* 87 */ 'c', 'm', 'p', 'e', 'q', '2', 9, 0, /* 95 */ 's', 'h', 'r', '2', 9, 0, /* 101 */ 'a', 'b', 's', '2', 9, 0, /* 107 */ 's', 'a', 'd', 'd', 'u', 's', '2', 9, 0, /* 116 */ 'c', 'm', 'p', 'g', 't', '2', 9, 0, /* 124 */ 's', 'h', 'r', 'u', '2', 9, 0, /* 131 */ 'd', 'o', 't', 'p', 'n', 'r', 's', 'u', '2', 9, 0, /* 142 */ 'd', 'o', 't', 'p', 'r', 's', 'u', '2', 9, 0, /* 152 */ 'm', 'a', 'x', '2', 9, 0, /* 158 */ 's', 'm', 'p', 'y', '2', 9, 0, /* 165 */ 's', 'u', 'b', '4', 9, 0, /* 171 */ 'b', 'i', 't', 'c', '4', 9, 0, /* 178 */ 'a', 'd', 'd', '4', 9, 0, /* 184 */ 'x', 'p', 'n', 'd', '4', 9, 0, /* 191 */ 'p', 'a', 'c', 'k', 'h', '4', 9, 0, /* 199 */ 'p', 'a', 'c', 'k', 'l', '4', 9, 0, /* 207 */ 's', 'w', 'a', 'p', '4', 9, 0, /* 214 */ 'c', 'm', 'p', 'e', 'q', '4', 9, 0, /* 222 */ 's', 'u', 'b', 'a', 'b', 's', '4', 9, 0, /* 231 */ 's', 'a', 'd', 'd', 'u', '4', 9, 0, /* 239 */ 'a', 'v', 'g', 'u', '4', 9, 0, /* 246 */ 'u', 'n', 'p', 'k', 'h', 'u', '4', 9, 0, /* 255 */ 's', 'p', 'a', 'c', 'k', 'u', '4', 9, 0, /* 264 */ 'u', 'n', 'p', 'k', 'l', 'u', '4', 9, 0, /* 273 */ 'm', 'i', 'n', 'u', '4', 9, 0, /* 280 */ 'd', 'o', 't', 'p', 'u', '4', 9, 0, /* 288 */ 'd', 'o', 't', 'p', 's', 'u', '4', 9, 0, /* 297 */ 'm', 'p', 'y', 's', 'u', '4', 9, 0, /* 305 */ 'c', 'm', 'p', 'g', 't', 'u', '4', 9, 0, /* 314 */ 'm', 'a', 'x', 'u', '4', 9, 0, /* 321 */ 'm', 'p', 'y', 'u', '4', 9, 0, /* 328 */ 'g', 'm', 'p', 'y', '4', 9, 0, /* 335 */ 's', 'u', 'b', 'a', 'b', 9, 0, /* 342 */ 'a', 'd', 'd', 'a', 'b', 9, 0, /* 349 */ 'l', 'd', 'b', 9, 0, /* 354 */ 's', 'h', 'l', 'm', 'b', 9, 0, /* 361 */ 's', 'h', 'r', 'm', 'b', 9, 0, /* 368 */ 's', 't', 'b', 9, 0, /* 373 */ 's', 's', 'u', 'b', 9, 0, /* 379 */ 's', 'u', 'b', 'c', 9, 0, /* 385 */ 'b', 'd', 'e', 'c', 9, 0, /* 391 */ 'a', 'd', 'd', 'k', 'p', 'c', 9, 0, /* 399 */ 'm', 'v', 'c', 9, 0, /* 404 */ 'a', 'd', 'd', 'a', 'd', 9, 0, /* 411 */ 'l', 'm', 'b', 'd', 9, 0, /* 417 */ 's', 'a', 'd', 'd', 9, 0, /* 423 */ 'a', 'n', 'd', 9, 0, /* 428 */ 'm', 'v', 'd', 9, 0, /* 433 */ 's', 'u', 'b', 'a', 'h', 9, 0, /* 440 */ 'a', 'd', 'd', 'a', 'h', 9, 0, /* 447 */ 'l', 'd', 'h', 9, 0, /* 452 */ 'm', 'v', 'k', 'l', 'h', 9, 0, /* 459 */ 's', 'm', 'p', 'y', 'l', 'h', 9, 0, /* 467 */ 's', 't', 'h', 9, 0, /* 472 */ 's', 'm', 'p', 'y', 'h', 9, 0, /* 479 */ 'm', 'p', 'y', 'h', 'i', 9, 0, /* 486 */ 'm', 'p', 'y', 'l', 'i', 9, 0, /* 493 */ 'a', 'd', 'd', 'k', 9, 0, /* 499 */ 'm', 'v', 'k', 9, 0, /* 504 */ 'd', 'e', 'a', 'l', 9, 0, /* 510 */ 's', 'h', 'f', 'l', 9, 0, /* 516 */ 's', 's', 'h', 'l', 9, 0, /* 522 */ 's', 'm', 'p', 'y', 'h', 'l', 9, 0, /* 530 */ 'r', 'o', 't', 'l', 9, 0, /* 536 */ 's', 's', 'h', 'v', 'l', 9, 0, /* 543 */ 'n', 'o', 'r', 'm', 9, 0, /* 549 */ 'a', 'n', 'd', 'n', 9, 0, /* 555 */ 'b', 'n', 'o', 'p', 9, 0, /* 561 */ 'c', 'm', 'p', 'e', 'q', 9, 0, /* 568 */ 's', 'h', 'r', 9, 0, /* 573 */ 'm', 'p', 'y', 'h', 'i', 'r', 9, 0, /* 581 */ 'm', 'p', 'y', 'l', 'i', 'r', 9, 0, /* 589 */ 'c', 'l', 'r', 9, 0, /* 594 */ 'x', 'o', 'r', 9, 0, /* 599 */ 's', 's', 'h', 'v', 'r', 9, 0, /* 606 */ 'a', 'b', 's', 9, 0, /* 611 */ 'm', 'p', 'y', 'l', 'u', 'h', 's', 9, 0, /* 620 */ 'm', 'p', 'y', 'h', 'u', 'l', 's', 9, 0, /* 629 */ 'b', 'p', 'o', 's', 9, 0, /* 635 */ 'm', 'p', 'y', 'h', 'u', 's', 9, 0, /* 643 */ 'm', 'p', 'y', 'u', 's', 9, 0, /* 650 */ 's', 'a', 't', 9, 0, /* 655 */ 's', 'e', 't', 9, 0, /* 660 */ 'c', 'm', 'p', 'g', 't', 9, 0, /* 667 */ 'c', 'm', 'p', 'l', 't', 9, 0, /* 674 */ 'e', 'x', 't', 9, 0, /* 679 */ 'l', 'd', 'b', 'u', 9, 0, /* 685 */ 's', 'u', 'b', 'u', 9, 0, /* 691 */ 'a', 'd', 'd', 'u', 9, 0, /* 697 */ 'l', 'd', 'h', 'u', 9, 0, /* 703 */ 'm', 'p', 'y', 'l', 'h', 'u', 9, 0, /* 711 */ 'm', 'p', 'y', 'l', 's', 'h', 'u', 9, 0, /* 720 */ 'm', 'p', 'y', 'h', 'u', 9, 0, /* 727 */ 'm', 'p', 'y', 'h', 'l', 'u', 9, 0, /* 735 */ 'm', 'p', 'y', 'h', 's', 'l', 'u', 9, 0, /* 744 */ 's', 'h', 'r', 'u', 9, 0, /* 750 */ 'm', 'p', 'y', 'h', 's', 'u', 9, 0, /* 758 */ 'm', 'p', 'y', 's', 'u', 9, 0, /* 765 */ 'c', 'm', 'p', 'g', 't', 'u', 9, 0, /* 773 */ 'c', 'm', 'p', 'l', 't', 'u', 9, 0, /* 781 */ 'e', 'x', 't', 'u', 9, 0, /* 787 */ 'm', 'p', 'y', 'u', 9, 0, /* 793 */ 's', 'u', 'b', 'a', 'w', 9, 0, /* 800 */ 'a', 'd', 'd', 'a', 'w', 9, 0, /* 807 */ 'l', 'd', 'd', 'w', 9, 0, /* 813 */ 'l', 'd', 'w', 9, 0, /* 818 */ 'l', 'd', 'n', 'd', 'w', 9, 0, /* 825 */ 's', 't', 'n', 'd', 'w', 9, 0, /* 832 */ 's', 't', 'd', 'w', 9, 0, /* 838 */ 'l', 'd', 'n', 'w', 9, 0, /* 844 */ 's', 't', 'n', 'w', 9, 0, /* 850 */ 's', 't', 'w', 9, 0, /* 855 */ 's', 'm', 'p', 'y', 9, 0, /* 861 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 'e', 'n', 'd', 0, /* 874 */ 'b', 'u', 'n', 'd', 'l', 'e', 0, /* 881 */ 'd', 'b', 'g', '_', 'v', 'a', 'l', 'u', 'e', 0, /* 891 */ 'b', 9, 'i', 'r', 'p', 0, /* 897 */ 'b', 9, 'n', 'r', 'p', 0, /* 903 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 's', 't', 'a', 'r', 't', 0, }; // Emit the opcode for the instruction. uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 1023)-1); #endif // Fragment 0 encoded into 3 bits for 8 unique commands. switch ((Bits >> 10) & 7) { default: case 0: // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, B_s7_irp, B_s7_nrp return; break; case 1: // ABS2_l2_rr, ABS_l1_rr, ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD... printOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 2: // ABS_l1_pp, NORM_l1_pr, SAT_l1_pr, SHL_s1_pip, SHL_s1_prp, SHRU_s1_pip,... printRegPair(MI, 1, O); SStream_concat0(O, ", "); break; case 3: // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rpp,... printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 4: // BNOP_s10_ri, BNOP_s9_ii, B_s5_i, B_s6_r, NOP_n, STB_d5_rm, STB_d6_rm, ... printOperand(MI, 0, O); break; case 5: // LDBU_d5_mr, LDB_d5_mr, LDDW_d7_mp, LDHU_d5_mr, LDH_d5_mr, LDNDW_d8_mp,... printMemOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 6: // LDBU_d6_mr, LDB_d6_mr, LDHU_d6_mr, LDH_d6_mr, LDW_d6_mr printMemOperand2(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 7: // STDW_d7_pm, STNDW_d8_pm printRegPair(MI, 0, O); SStream_concat0(O, ", "); printMemOperand(MI, 1, O); return; break; } // Fragment 1 encoded into 3 bits for 7 unique commands. switch ((Bits >> 13) & 7) { default: case 0: // ABS2_l2_rr, ABS_l1_rr, ADDKPC_s3_iir, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2... printOperand(MI, 0, O); break; case 1: // ABS_l1_pp, LDDW_d7_mp, LDNDW_d8_mp printRegPair(MI, 0, O); return; break; case 2: // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDU_l1_rrp_... printOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 3: // ADDAB_d1_rir, ADDAB_d1_rrr, ADDAD_d1_rir, ADDAD_d1_rrr, ADDAH_d1_rir, ... printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 4: // ADDU_l1_rpp, ADD_l1_ipp, ADD_l1_rpp, CMPEQ_l1_ipr, CMPEQ_l1_rpr, CMPGT... printRegPair(MI, 1, O); SStream_concat0(O, ", "); break; case 5: // BNOP_s10_ri, BNOP_s9_ii, STB_d5_rm, STB_d6_rm, STH_d5_rm, STH_d6_rm, S... SStream_concat0(O, ", "); break; case 6: // B_s5_i, B_s6_r, NOP_n return; break; } // Fragment 2 encoded into 3 bits for 8 unique commands. switch ((Bits >> 16) & 7) { default: case 0: // ABS2_l2_rr, ABS_l1_rr, ADDK_s2_ir, BDEC_s8_ir, BITC4_m2_rr, BPOS_s8_ir... return; break; case 1: // ADD2_d2_rrr, ADD2_l1_rrr_x2, ADD2_s1_rrr, ADD4_l1_rrr_x2, ADDAB_d1_rir... printOperand(MI, 0, O); return; break; case 2: // ADDKPC_s3_iir SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 3: // ADDU_l1_rpp, ADDU_l1_rrp_x2, ADD_l1_ipp, ADD_l1_rpp, ADD_l1_rrp_x2, DO... printRegPair(MI, 0, O); return; break; case 4: // BNOP_s10_ri, BNOP_s9_ii printOperand(MI, 1, O); return; break; case 5: // CLR_s15_riir, EXTU_s15_riir, EXT_s15_riir, SET_s15_riir printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 6: // STB_d5_rm, STH_d5_rm, STNW_d5_rm, STW_d5_rm printMemOperand(MI, 1, O); return; break; case 7: // STB_d6_rm, STH_d6_rm, STW_d6_rm printMemOperand2(MI, 1, O); return; break; } } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'a', '1', '0', 0, /* 4 */ 'b', '1', '0', 0, /* 8 */ 'a', '2', '0', 0, /* 12 */ 'b', '2', '0', 0, /* 16 */ 'a', '3', '0', 0, /* 20 */ 'b', '3', '0', 0, /* 24 */ 'a', '0', 0, /* 27 */ 'b', '0', 0, /* 30 */ 'a', '1', '1', 0, /* 34 */ 'b', '1', '1', 0, /* 38 */ 'a', '2', '1', 0, /* 42 */ 'b', '2', '1', 0, /* 46 */ 'a', '3', '1', 0, /* 50 */ 'b', '3', '1', 0, /* 54 */ 'a', '1', 0, /* 57 */ 'b', '1', 0, /* 60 */ 'p', 'c', 'e', '1', 0, /* 65 */ 'a', '1', '2', 0, /* 69 */ 'b', '1', '2', 0, /* 73 */ 'a', '2', '2', 0, /* 77 */ 'b', '2', '2', 0, /* 81 */ 'a', '2', 0, /* 84 */ 'b', '2', 0, /* 87 */ 'a', '1', '3', 0, /* 91 */ 'b', '1', '3', 0, /* 95 */ 'a', '2', '3', 0, /* 99 */ 'b', '2', '3', 0, /* 103 */ 'a', '3', 0, /* 106 */ 'b', '3', 0, /* 109 */ 'a', '1', '4', 0, /* 113 */ 'b', '1', '4', 0, /* 117 */ 'a', '2', '4', 0, /* 121 */ 'b', '2', '4', 0, /* 125 */ 'a', '4', 0, /* 128 */ 'b', '4', 0, /* 131 */ 'a', '1', '5', 0, /* 135 */ 'b', '1', '5', 0, /* 139 */ 'a', '2', '5', 0, /* 143 */ 'b', '2', '5', 0, /* 147 */ 'a', '5', 0, /* 150 */ 'b', '5', 0, /* 153 */ 'a', '1', '6', 0, /* 157 */ 'b', '1', '6', 0, /* 161 */ 'a', '2', '6', 0, /* 165 */ 'b', '2', '6', 0, /* 169 */ 'a', '6', 0, /* 172 */ 'b', '6', 0, /* 175 */ 'a', '1', '7', 0, /* 179 */ 'b', '1', '7', 0, /* 183 */ 'a', '2', '7', 0, /* 187 */ 'b', '2', '7', 0, /* 191 */ 'a', '7', 0, /* 194 */ 'b', '7', 0, /* 197 */ 'a', '1', '8', 0, /* 201 */ 'b', '1', '8', 0, /* 205 */ 'a', '2', '8', 0, /* 209 */ 'b', '2', '8', 0, /* 213 */ 'a', '8', 0, /* 216 */ 'b', '8', 0, /* 219 */ 'a', '1', '9', 0, /* 223 */ 'b', '1', '9', 0, /* 227 */ 'a', '2', '9', 0, /* 231 */ 'b', '2', '9', 0, /* 235 */ 'a', '9', 0, /* 238 */ 'b', '9', 0, /* 241 */ 'g', 'p', 'l', 'y', 'a', 0, /* 247 */ 'g', 'p', 'l', 'y', 'b', 0, /* 253 */ 'r', 'i', 'l', 'c', 0, /* 258 */ 't', 's', 'c', 'h', 0, /* 263 */ 't', 's', 'c', 'l', 0, /* 268 */ 'd', 'n', 'u', 'm', 0, /* 273 */ 'r', 'e', 'p', 0, /* 277 */ 'i', 'r', 'p', 0, /* 281 */ 'n', 'r', 'p', 0, /* 285 */ 'i', 's', 't', 'p', 0, /* 290 */ 'e', 'c', 'r', 0, /* 294 */ 'i', 'c', 'r', 0, /* 298 */ 'd', 'i', 'e', 'r', 0, /* 303 */ 'g', 'f', 'p', 'g', 'f', 'r', 0, /* 310 */ 'a', 'm', 'r', 0, /* 314 */ 'i', 'e', 'r', 'r', 0, /* 319 */ 'c', 's', 'r', 0, /* 323 */ 'i', 's', 'r', 0, /* 327 */ 's', 's', 'r', 0, /* 331 */ 'i', 't', 's', 'r', 0, /* 336 */ 'n', 't', 's', 'r', 0, }; static const uint16_t RegAsmOffset[] = { 310, 319, 298, 268, 290, 303, 241, 247, 294, 299, 314, 254, 277, 323, 285, 331, 281, 336, 273, 253, 327, 258, 263, 332, 24, 54, 81, 103, 125, 147, 169, 191, 213, 235, 0, 30, 65, 87, 109, 131, 153, 175, 197, 219, 8, 38, 73, 95, 117, 139, 161, 183, 205, 227, 16, 46, 27, 57, 84, 106, 128, 150, 172, 194, 216, 238, 4, 34, 69, 91, 113, 135, 157, 179, 201, 223, 12, 42, 77, 99, 121, 143, 165, 187, 209, 231, 20, 50, 60, }; return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc000064400000000000000000002365340072674642500246450ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * TMS320C64x Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, \ unsigned numBits) { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 2, 5, // Inst{6-2} ... /* 3 */ MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206 /* 7 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 10 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 30 /* 14 */ MCD_OPC_CheckField, 17, 11, 0, 153, 8, // Skip to: 2221 /* 20 */ MCD_OPC_CheckField, 12, 1, 0, 147, 8, // Skip to: 2221 /* 26 */ MCD_OPC_Decode, 162, 1, 0, // Opcode: NOP_n /* 30 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 38 /* 34 */ MCD_OPC_Decode, 140, 1, 1, // Opcode: MPYH_m4_rrr /* 38 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 46 /* 42 */ MCD_OPC_Decode, 219, 1, 1, // Opcode: SMPYH_m4_rrr /* 46 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 54 /* 50 */ MCD_OPC_Decode, 136, 1, 1, // Opcode: MPYHSU_m4_rrr /* 54 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 62 /* 58 */ MCD_OPC_Decode, 138, 1, 1, // Opcode: MPYHUS_m4_rrr /* 62 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 70 /* 66 */ MCD_OPC_Decode, 139, 1, 1, // Opcode: MPYHU_m4_rrr /* 70 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 78 /* 74 */ MCD_OPC_Decode, 134, 1, 1, // Opcode: MPYHL_m4_rrr /* 78 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 86 /* 82 */ MCD_OPC_Decode, 218, 1, 1, // Opcode: SMPYHL_m4_rrr /* 86 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 94 /* 90 */ MCD_OPC_Decode, 135, 1, 1, // Opcode: MPYHSLU_m4_rrr /* 94 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 102 /* 98 */ MCD_OPC_Decode, 137, 1, 1, // Opcode: MPYHULS_m4_rrr /* 102 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 110 /* 106 */ MCD_OPC_Decode, 133, 1, 1, // Opcode: MPYHLU_m4_rrr /* 110 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 118 /* 114 */ MCD_OPC_Decode, 142, 1, 1, // Opcode: MPYLH_m4_rrr /* 118 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 126 /* 122 */ MCD_OPC_Decode, 220, 1, 1, // Opcode: SMPYLH_m4_rrr /* 126 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 134 /* 130 */ MCD_OPC_Decode, 145, 1, 1, // Opcode: MPYLSHU_m4_rrr /* 134 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 142 /* 138 */ MCD_OPC_Decode, 146, 1, 1, // Opcode: MPYLUHS_m4_rrr /* 142 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 150 /* 146 */ MCD_OPC_Decode, 141, 1, 1, // Opcode: MPYLHU_m4_rrr /* 150 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 158 /* 154 */ MCD_OPC_Decode, 153, 1, 2, // Opcode: MPY_m4_irr /* 158 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 166 /* 162 */ MCD_OPC_Decode, 154, 1, 1, // Opcode: MPY_m4_rrr /* 166 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 174 /* 170 */ MCD_OPC_Decode, 221, 1, 1, // Opcode: SMPY_m4_rrr /* 174 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 182 /* 178 */ MCD_OPC_Decode, 149, 1, 1, // Opcode: MPYSU_m4_rrr /* 182 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 190 /* 186 */ MCD_OPC_Decode, 151, 1, 1, // Opcode: MPYUS_m4_rrr /* 190 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 198 /* 194 */ MCD_OPC_Decode, 148, 1, 2, // Opcode: MPYSU_m4_irr /* 198 */ MCD_OPC_FilterValue, 31, 227, 7, // Skip to: 2221 /* 202 */ MCD_OPC_Decode, 152, 1, 1, // Opcode: MPYU_m4_rrr /* 206 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 219 /* 210 */ MCD_OPC_CheckField, 8, 1, 0, 213, 7, // Skip to: 2221 /* 216 */ MCD_OPC_Decode, 116, 3, // Opcode: LDHU_d5_mr /* 219 */ MCD_OPC_FilterValue, 2, 18, 0, // Skip to: 241 /* 223 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 226 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 233 /* 230 */ MCD_OPC_Decode, 102, 4, // Opcode: EXTU_s15_riir /* 233 */ MCD_OPC_FilterValue, 1, 192, 7, // Skip to: 2221 /* 237 */ MCD_OPC_Decode, 192, 1, 4, // Opcode: SET_s15_riir /* 241 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 248 /* 245 */ MCD_OPC_Decode, 117, 5, // Opcode: LDHU_d6_mr /* 248 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 255 /* 252 */ MCD_OPC_Decode, 68, 6, // Opcode: B_s5_i /* 255 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 268 /* 259 */ MCD_OPC_CheckField, 8, 1, 0, 164, 7, // Skip to: 2221 /* 265 */ MCD_OPC_Decode, 111, 3, // Opcode: LDBU_d5_mr /* 268 */ MCD_OPC_FilterValue, 6, 157, 0, // Skip to: 429 /* 272 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 275 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 283 /* 279 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: PACK2_l1_rrr_x2 /* 283 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 291 /* 287 */ MCD_OPC_Decode, 242, 1, 1, // Opcode: SUB2_l1_rrr_x2 /* 291 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 299 /* 295 */ MCD_OPC_Decode, 176, 1, 1, // Opcode: PACKHL2_l1_rrr_x2 /* 299 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 306 /* 303 */ MCD_OPC_Decode, 45, 7, // Opcode: ADD_l1_ipp /* 306 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 314 /* 310 */ MCD_OPC_Decode, 130, 2, 7, // Opcode: SUB_l1_ipp /* 314 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 322 /* 318 */ MCD_OPC_Decode, 228, 1, 7, // Opcode: SSUB_l1_ipp /* 322 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 330 /* 326 */ MCD_OPC_Decode, 186, 1, 7, // Opcode: SADD_l1_ipp /* 330 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 343 /* 334 */ MCD_OPC_CheckField, 13, 5, 0, 89, 7, // Skip to: 2221 /* 340 */ MCD_OPC_Decode, 23, 8, // Opcode: ABS_l1_pp /* 343 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 357 /* 347 */ MCD_OPC_CheckField, 13, 5, 0, 76, 7, // Skip to: 2221 /* 353 */ MCD_OPC_Decode, 191, 1, 9, // Opcode: SAT_l1_pr /* 357 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 364 /* 361 */ MCD_OPC_Decode, 82, 10, // Opcode: CMPGT_l1_ipr /* 364 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 372 /* 368 */ MCD_OPC_Decode, 129, 1, 1, // Opcode: MINU4_l1_rrr_x2 /* 372 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 379 /* 376 */ MCD_OPC_Decode, 106, 11, // Opcode: GMPGTU_l1_ipr /* 379 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 386 /* 383 */ MCD_OPC_Decode, 76, 10, // Opcode: CMPEQ_l1_ipr /* 386 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 393 /* 390 */ MCD_OPC_Decode, 90, 10, // Opcode: CMPLT_l1_ipr /* 393 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 400 /* 397 */ MCD_OPC_Decode, 86, 11, // Opcode: CMPLTU_l1_ipr /* 400 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 414 /* 404 */ MCD_OPC_CheckField, 13, 5, 0, 19, 7, // Skip to: 2221 /* 410 */ MCD_OPC_Decode, 163, 1, 12, // Opcode: NORM_l1_pr /* 414 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 422 /* 418 */ MCD_OPC_Decode, 178, 1, 1, // Opcode: PACKL4_l1_rrr_x2 /* 422 */ MCD_OPC_FilterValue, 31, 3, 7, // Skip to: 2221 /* 426 */ MCD_OPC_Decode, 53, 1, // Opcode: ANDN_l1_rrr_x2 /* 429 */ MCD_OPC_FilterValue, 7, 3, 0, // Skip to: 436 /* 433 */ MCD_OPC_Decode, 112, 5, // Opcode: LDBU_d6_mr /* 436 */ MCD_OPC_FilterValue, 8, 222, 0, // Skip to: 662 /* 440 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 443 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 464 /* 447 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... /* 450 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 457 /* 454 */ MCD_OPC_Decode, 67, 13, // Opcode: BPOS_s8_ir /* 457 */ MCD_OPC_FilterValue, 1, 224, 6, // Skip to: 2221 /* 461 */ MCD_OPC_Decode, 63, 13, // Opcode: BDEC_s8_ir /* 464 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 477 /* 468 */ MCD_OPC_CheckField, 12, 1, 0, 211, 6, // Skip to: 2221 /* 474 */ MCD_OPC_Decode, 66, 14, // Opcode: BNOP_s9_ii /* 477 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 484 /* 481 */ MCD_OPC_Decode, 50, 2, // Opcode: ADD_s1_irr /* 484 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 492 /* 488 */ MCD_OPC_Decode, 177, 1, 1, // Opcode: PACKHL2_s1_rrr /* 492 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 500 /* 496 */ MCD_OPC_Decode, 148, 2, 2, // Opcode: XOR_s1_irr /* 500 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 514 /* 504 */ MCD_OPC_CheckField, 13, 5, 0, 175, 6, // Skip to: 2221 /* 510 */ MCD_OPC_Decode, 156, 1, 15, // Opcode: MVC_s1_rr2 /* 514 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 522 /* 518 */ MCD_OPC_Decode, 180, 1, 1, // Opcode: PACKLH2_s1_rrr /* 522 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 530 /* 526 */ MCD_OPC_Decode, 199, 1, 16, // Opcode: SHL_s1_rip /* 530 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 537 /* 534 */ MCD_OPC_Decode, 80, 1, // Opcode: CMPGT2_s1_rrr /* 537 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 545 /* 541 */ MCD_OPC_Decode, 136, 2, 2, // Opcode: SUB_s1_irr /* 545 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 553 /* 549 */ MCD_OPC_Decode, 203, 1, 17, // Opcode: SHR2_s1_rir /* 553 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 561 /* 557 */ MCD_OPC_Decode, 169, 1, 2, // Opcode: OR_s1_irr /* 561 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 568 /* 565 */ MCD_OPC_Decode, 75, 1, // Opcode: CMPEQ4_s1_rrr /* 568 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 575 /* 572 */ MCD_OPC_Decode, 59, 2, // Opcode: AND_s1_irr /* 575 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 583 /* 579 */ MCD_OPC_Decode, 190, 1, 1, // Opcode: SADD_s1_rrr /* 583 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 591 /* 587 */ MCD_OPC_Decode, 224, 1, 17, // Opcode: SSHL_s1_rir /* 591 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 599 /* 595 */ MCD_OPC_Decode, 209, 1, 18, // Opcode: SHRU_s1_pip /* 599 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 607 /* 603 */ MCD_OPC_Decode, 211, 1, 17, // Opcode: SHRU_s1_rir /* 607 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 615 /* 611 */ MCD_OPC_Decode, 197, 1, 19, // Opcode: SHL_s1_pip /* 615 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 623 /* 619 */ MCD_OPC_Decode, 200, 1, 20, // Opcode: SHL_s1_rir /* 623 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 631 /* 627 */ MCD_OPC_Decode, 213, 1, 18, // Opcode: SHR_s1_pip /* 631 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 639 /* 635 */ MCD_OPC_Decode, 215, 1, 17, // Opcode: SHR_s1_rir /* 639 */ MCD_OPC_FilterValue, 30, 42, 6, // Skip to: 2221 /* 643 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ... /* 646 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 654 /* 650 */ MCD_OPC_Decode, 143, 2, 21, // Opcode: UNPKLU4_s14_rr /* 654 */ MCD_OPC_FilterValue, 3, 27, 6, // Skip to: 2221 /* 658 */ MCD_OPC_Decode, 141, 2, 21, // Opcode: UNPKHU4_s14_rr /* 662 */ MCD_OPC_FilterValue, 9, 17, 0, // Skip to: 683 /* 666 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 669 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 676 /* 673 */ MCD_OPC_Decode, 113, 3, // Opcode: LDB_d5_mr /* 676 */ MCD_OPC_FilterValue, 1, 5, 6, // Skip to: 2221 /* 680 */ MCD_OPC_Decode, 120, 22, // Opcode: LDNDW_d8_mp /* 683 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 691 /* 687 */ MCD_OPC_Decode, 159, 1, 23, // Opcode: MVKL_s12_ir /* 691 */ MCD_OPC_FilterValue, 11, 3, 0, // Skip to: 698 /* 695 */ MCD_OPC_Decode, 114, 5, // Opcode: LDB_d6_mr /* 698 */ MCD_OPC_FilterValue, 12, 194, 0, // Skip to: 896 /* 702 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 705 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 713 /* 709 */ MCD_OPC_Decode, 130, 1, 24, // Opcode: MPY2_m1_rrp /* 713 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 720 /* 717 */ MCD_OPC_Decode, 100, 1, // Opcode: DOTPSU4_m1_rrr /* 720 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 728 /* 724 */ MCD_OPC_Decode, 150, 1, 24, // Opcode: MPYU4_m1_rrp /* 728 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 735 /* 732 */ MCD_OPC_Decode, 101, 1, // Opcode: DOTPU4_m1_rrr /* 735 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 742 /* 739 */ MCD_OPC_Decode, 96, 1, // Opcode: DOTP2_m1_rrr /* 742 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 750 /* 746 */ MCD_OPC_Decode, 143, 1, 1, // Opcode: MPYLIR_m1_rrr /* 750 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 758 /* 754 */ MCD_OPC_Decode, 131, 1, 1, // Opcode: MPYHIR_m1_rrr /* 758 */ MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 765 /* 762 */ MCD_OPC_Decode, 62, 1, // Opcode: AVGU4_m1_rrr /* 765 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 773 /* 769 */ MCD_OPC_Decode, 132, 1, 24, // Opcode: MPYHI_m1_rrp /* 773 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 781 /* 777 */ MCD_OPC_Decode, 227, 1, 1, // Opcode: SSHVR_m1_rrr /* 781 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 789 /* 785 */ MCD_OPC_Decode, 226, 1, 1, // Opcode: SSHVL_m1_rrr /* 789 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 797 /* 793 */ MCD_OPC_Decode, 181, 1, 17, // Opcode: ROTL_m1_rir /* 797 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 804 /* 801 */ MCD_OPC_Decode, 52, 1, // Opcode: ANDN_d2_rrr /* 804 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 812 /* 808 */ MCD_OPC_Decode, 166, 1, 1, // Opcode: OR_d2_rrr /* 812 */ MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 819 /* 816 */ MCD_OPC_Decode, 25, 1, // Opcode: ADD2_d2_rrr /* 819 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 826 /* 823 */ MCD_OPC_Decode, 56, 1, // Opcode: AND_d2_rrr /* 826 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 833 /* 830 */ MCD_OPC_Decode, 44, 1, // Opcode: ADD_d2_rrr /* 833 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 841 /* 837 */ MCD_OPC_Decode, 129, 2, 1, // Opcode: SUB_d2_rrr /* 841 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 849 /* 845 */ MCD_OPC_Decode, 145, 2, 1, // Opcode: XOR_d2_rrr /* 849 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 857 /* 853 */ MCD_OPC_Decode, 183, 1, 1, // Opcode: SADD2_s4_rrr /* 857 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 865 /* 861 */ MCD_OPC_Decode, 222, 1, 1, // Opcode: SPACK2_s4_rrr /* 865 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 873 /* 869 */ MCD_OPC_Decode, 223, 1, 1, // Opcode: SPACKU4_s4_rrr /* 873 */ MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 880 /* 877 */ MCD_OPC_Decode, 54, 1, // Opcode: ANDN_s4_rrr /* 880 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 888 /* 884 */ MCD_OPC_Decode, 208, 1, 1, // Opcode: SHRU2_s4_rrr /* 888 */ MCD_OPC_FilterValue, 29, 49, 5, // Skip to: 2221 /* 892 */ MCD_OPC_Decode, 206, 1, 1, // Opcode: SHRMB_s4_rrr /* 896 */ MCD_OPC_FilterValue, 13, 18, 0, // Skip to: 918 /* 900 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 903 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 911 /* 907 */ MCD_OPC_Decode, 232, 1, 3, // Opcode: STB_d5_rm /* 911 */ MCD_OPC_FilterValue, 1, 26, 5, // Skip to: 2221 /* 915 */ MCD_OPC_Decode, 121, 3, // Opcode: LDNW_d5_mr /* 918 */ MCD_OPC_FilterValue, 14, 98, 0, // Skip to: 1020 /* 922 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 925 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 932 /* 929 */ MCD_OPC_Decode, 26, 1, // Opcode: ADD2_l1_rrr_x2 /* 932 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 939 /* 936 */ MCD_OPC_Decode, 47, 25, // Opcode: ADD_l1_rpp /* 939 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 946 /* 943 */ MCD_OPC_Decode, 39, 25, // Opcode: ADDU_l1_rpp /* 946 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 954 /* 950 */ MCD_OPC_Decode, 188, 1, 25, // Opcode: SADD_l1_rpp /* 954 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 962 /* 958 */ MCD_OPC_Decode, 128, 1, 1, // Opcode: MIN2_l1_rrr_x2 /* 962 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 969 /* 966 */ MCD_OPC_Decode, 84, 26, // Opcode: CMPGT_l1_rpr /* 969 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 976 /* 973 */ MCD_OPC_Decode, 108, 26, // Opcode: GMPGTU_l1_rpr /* 976 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 983 /* 980 */ MCD_OPC_Decode, 78, 26, // Opcode: CMPEQ_l1_rpr /* 983 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 990 /* 987 */ MCD_OPC_Decode, 92, 26, // Opcode: CMPLT_l1_rpr /* 990 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 997 /* 994 */ MCD_OPC_Decode, 88, 26, // Opcode: CMPLTU_l1_rpr /* 997 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1005 /* 1001 */ MCD_OPC_Decode, 195, 1, 1, // Opcode: SHLMB_l1_rrr_x2 /* 1005 */ MCD_OPC_FilterValue, 25, 3, 0, // Skip to: 1012 /* 1009 */ MCD_OPC_Decode, 28, 1, // Opcode: ADD4_l1_rrr_x2 /* 1012 */ MCD_OPC_FilterValue, 26, 181, 4, // Skip to: 2221 /* 1016 */ MCD_OPC_Decode, 175, 1, 1, // Opcode: PACKH4_l1_rrr_x2 /* 1020 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1028 /* 1024 */ MCD_OPC_Decode, 233, 1, 5, // Opcode: STB_d6_rm /* 1028 */ MCD_OPC_FilterValue, 16, 151, 0, // Skip to: 1183 /* 1032 */ MCD_OPC_ExtractField, 7, 6, // Inst{12-7} ... /* 1035 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1049 /* 1039 */ MCD_OPC_CheckField, 18, 5, 0, 152, 4, // Skip to: 2221 /* 1045 */ MCD_OPC_Decode, 160, 1, 27, // Opcode: MVK_d1_rr /* 1049 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1056 /* 1053 */ MCD_OPC_Decode, 42, 28, // Opcode: ADD_d1_rrr /* 1056 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1064 /* 1060 */ MCD_OPC_Decode, 128, 2, 28, // Opcode: SUB_d1_rrr /* 1064 */ MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 1071 /* 1068 */ MCD_OPC_Decode, 41, 29, // Opcode: ADD_d1_rir /* 1071 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1079 /* 1075 */ MCD_OPC_Decode, 255, 1, 29, // Opcode: SUB_d1_rir /* 1079 */ MCD_OPC_FilterValue, 48, 3, 0, // Skip to: 1086 /* 1083 */ MCD_OPC_Decode, 30, 28, // Opcode: ADDAB_d1_rrr /* 1086 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 1094 /* 1090 */ MCD_OPC_Decode, 247, 1, 28, // Opcode: SUBAB_d1_rrr /* 1094 */ MCD_OPC_FilterValue, 50, 3, 0, // Skip to: 1101 /* 1098 */ MCD_OPC_Decode, 29, 29, // Opcode: ADDAB_d1_rir /* 1101 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1109 /* 1105 */ MCD_OPC_Decode, 246, 1, 29, // Opcode: SUBAB_d1_rir /* 1109 */ MCD_OPC_FilterValue, 52, 3, 0, // Skip to: 1116 /* 1113 */ MCD_OPC_Decode, 34, 28, // Opcode: ADDAH_d1_rrr /* 1116 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1124 /* 1120 */ MCD_OPC_Decode, 249, 1, 28, // Opcode: SUBAH_d1_rrr /* 1124 */ MCD_OPC_FilterValue, 54, 3, 0, // Skip to: 1131 /* 1128 */ MCD_OPC_Decode, 33, 29, // Opcode: ADDAH_d1_rir /* 1131 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 1139 /* 1135 */ MCD_OPC_Decode, 248, 1, 29, // Opcode: SUBAH_d1_rir /* 1139 */ MCD_OPC_FilterValue, 56, 3, 0, // Skip to: 1146 /* 1143 */ MCD_OPC_Decode, 36, 28, // Opcode: ADDAW_d1_rrr /* 1146 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1154 /* 1150 */ MCD_OPC_Decode, 251, 1, 28, // Opcode: SUBAW_d1_rrr /* 1154 */ MCD_OPC_FilterValue, 58, 3, 0, // Skip to: 1161 /* 1158 */ MCD_OPC_Decode, 35, 29, // Opcode: ADDAW_d1_rir /* 1161 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 1169 /* 1165 */ MCD_OPC_Decode, 250, 1, 29, // Opcode: SUBAW_d1_rir /* 1169 */ MCD_OPC_FilterValue, 60, 3, 0, // Skip to: 1176 /* 1173 */ MCD_OPC_Decode, 32, 28, // Opcode: ADDAD_d1_rrr /* 1176 */ MCD_OPC_FilterValue, 61, 17, 4, // Skip to: 2221 /* 1180 */ MCD_OPC_Decode, 31, 29, // Opcode: ADDAD_d1_rir /* 1183 */ MCD_OPC_FilterValue, 17, 18, 0, // Skip to: 1205 /* 1187 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 1190 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1197 /* 1194 */ MCD_OPC_Decode, 118, 3, // Opcode: LDH_d5_mr /* 1197 */ MCD_OPC_FilterValue, 1, 252, 3, // Skip to: 2221 /* 1201 */ MCD_OPC_Decode, 234, 1, 30, // Opcode: STDW_d7_pm /* 1205 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 1226 /* 1209 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... /* 1212 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1219 /* 1216 */ MCD_OPC_Decode, 104, 4, // Opcode: EXT_s15_riir /* 1219 */ MCD_OPC_FilterValue, 1, 230, 3, // Skip to: 2221 /* 1223 */ MCD_OPC_Decode, 72, 4, // Opcode: CLR_s15_riir /* 1226 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1233 /* 1230 */ MCD_OPC_Decode, 119, 5, // Opcode: LDH_d6_mr /* 1233 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1240 /* 1237 */ MCD_OPC_Decode, 38, 23, // Opcode: ADDK_s2_ir /* 1240 */ MCD_OPC_FilterValue, 21, 19, 0, // Skip to: 1263 /* 1244 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 1247 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1255 /* 1251 */ MCD_OPC_Decode, 235, 1, 3, // Opcode: STH_d5_rm /* 1255 */ MCD_OPC_FilterValue, 1, 194, 3, // Skip to: 2221 /* 1259 */ MCD_OPC_Decode, 238, 1, 3, // Opcode: STNW_d5_rm /* 1263 */ MCD_OPC_FilterValue, 22, 191, 0, // Skip to: 1458 /* 1267 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 1270 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1277 /* 1274 */ MCD_OPC_Decode, 46, 2, // Opcode: ADD_l1_irr /* 1277 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1285 /* 1281 */ MCD_OPC_Decode, 131, 2, 2, // Opcode: SUB_l1_irr /* 1285 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1293 /* 1289 */ MCD_OPC_Decode, 229, 1, 2, // Opcode: SSUB_l1_irr /* 1293 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1301 /* 1297 */ MCD_OPC_Decode, 187, 1, 2, // Opcode: SADD_l1_irr /* 1301 */ MCD_OPC_FilterValue, 6, 49, 0, // Skip to: 1354 /* 1305 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ... /* 1308 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1315 /* 1312 */ MCD_OPC_Decode, 24, 21, // Opcode: ABS_l1_rr /* 1315 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1323 /* 1319 */ MCD_OPC_Decode, 139, 2, 21, // Opcode: SWAP4_l2_rr /* 1323 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1331 /* 1327 */ MCD_OPC_Decode, 142, 2, 21, // Opcode: UNPKLU4_l2_rr /* 1331 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1339 /* 1335 */ MCD_OPC_Decode, 140, 2, 21, // Opcode: UNPKHU4_l2_rr /* 1339 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1346 /* 1343 */ MCD_OPC_Decode, 22, 21, // Opcode: ABS2_l2_rr /* 1346 */ MCD_OPC_FilterValue, 5, 103, 3, // Skip to: 2221 /* 1350 */ MCD_OPC_Decode, 161, 1, 31, // Opcode: MVK_l2_ir /* 1354 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1362 /* 1358 */ MCD_OPC_Decode, 173, 1, 1, // Opcode: PACKH2_l1_rrr_x2 /* 1362 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1369 /* 1366 */ MCD_OPC_Decode, 126, 1, // Opcode: MAX2_l1_rrr_x2 /* 1369 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 1376 /* 1373 */ MCD_OPC_Decode, 83, 2, // Opcode: CMPGT_l1_irr /* 1376 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1383 /* 1380 */ MCD_OPC_Decode, 107, 17, // Opcode: GMPGTU_l1_irr /* 1383 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1390 /* 1387 */ MCD_OPC_Decode, 77, 2, // Opcode: CMPEQ_l1_irr /* 1390 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1397 /* 1394 */ MCD_OPC_Decode, 91, 2, // Opcode: CMPLT_l1_irr /* 1397 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 1405 /* 1401 */ MCD_OPC_Decode, 245, 1, 1, // Opcode: SUBABS4_l1_rrr_x2 /* 1405 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1412 /* 1409 */ MCD_OPC_Decode, 87, 17, // Opcode: CMPLTU_l1_irr /* 1412 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1420 /* 1416 */ MCD_OPC_Decode, 205, 1, 1, // Opcode: SHRMB_l1_rrr_x2 /* 1420 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1428 /* 1424 */ MCD_OPC_Decode, 244, 1, 1, // Opcode: SUB4_l1_rrr_x2 /* 1428 */ MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 1435 /* 1432 */ MCD_OPC_Decode, 124, 2, // Opcode: LMBD_l1_irr /* 1435 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1443 /* 1439 */ MCD_OPC_Decode, 146, 2, 2, // Opcode: XOR_l1_irr /* 1443 */ MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 1450 /* 1447 */ MCD_OPC_Decode, 57, 2, // Opcode: AND_l1_irr /* 1450 */ MCD_OPC_FilterValue, 31, 255, 2, // Skip to: 2221 /* 1454 */ MCD_OPC_Decode, 167, 1, 2, // Opcode: OR_l1_irr /* 1458 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1466 /* 1462 */ MCD_OPC_Decode, 236, 1, 5, // Opcode: STH_d6_rm /* 1466 */ MCD_OPC_FilterValue, 24, 6, 1, // Skip to: 1732 /* 1470 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 1473 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1480 /* 1477 */ MCD_OPC_Decode, 27, 1, // Opcode: ADD2_s1_rrr /* 1480 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 1503 /* 1484 */ MCD_OPC_ExtractField, 12, 16, // Inst{27-12} ... /* 1487 */ MCD_OPC_FilterValue, 128, 3, 3, 0, // Skip to: 1495 /* 1492 */ MCD_OPC_Decode, 70, 32, // Opcode: B_s7_irp /* 1495 */ MCD_OPC_FilterValue, 192, 3, 209, 2, // Skip to: 2221 /* 1500 */ MCD_OPC_Decode, 71, 32, // Opcode: B_s7_nrp /* 1503 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1516 /* 1507 */ MCD_OPC_CheckField, 12, 1, 0, 196, 2, // Skip to: 2221 /* 1513 */ MCD_OPC_Decode, 37, 33, // Opcode: ADDKPC_s3_iir /* 1516 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1523 /* 1520 */ MCD_OPC_Decode, 51, 1, // Opcode: ADD_s1_rrr /* 1523 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1531 /* 1527 */ MCD_OPC_Decode, 174, 1, 1, // Opcode: PACKH2_s1_rrr /* 1531 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1539 /* 1535 */ MCD_OPC_Decode, 149, 2, 1, // Opcode: XOR_s1_rrr /* 1539 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 1572 /* 1543 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... /* 1546 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1559 /* 1550 */ MCD_OPC_CheckField, 13, 5, 0, 153, 2, // Skip to: 2221 /* 1556 */ MCD_OPC_Decode, 69, 34, // Opcode: B_s6_r /* 1559 */ MCD_OPC_FilterValue, 1, 146, 2, // Skip to: 2221 /* 1563 */ MCD_OPC_CheckField, 16, 2, 0, 140, 2, // Skip to: 2221 /* 1569 */ MCD_OPC_Decode, 65, 35, // Opcode: BNOP_s10_ri /* 1572 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 1586 /* 1576 */ MCD_OPC_CheckField, 13, 5, 0, 127, 2, // Skip to: 2221 /* 1582 */ MCD_OPC_Decode, 155, 1, 36, // Opcode: MVC_s1_rr /* 1586 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1594 /* 1590 */ MCD_OPC_Decode, 243, 1, 1, // Opcode: SUB2_s1_rrr /* 1594 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1602 /* 1598 */ MCD_OPC_Decode, 201, 1, 37, // Opcode: SHL_s1_rrp /* 1602 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 1609 /* 1606 */ MCD_OPC_Decode, 81, 1, // Opcode: CMPGTU4_s1_rrr /* 1609 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1617 /* 1613 */ MCD_OPC_Decode, 137, 2, 1, // Opcode: SUB_s1_rrr /* 1617 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1625 /* 1621 */ MCD_OPC_Decode, 207, 1, 17, // Opcode: SHRU2_s1_rir /* 1625 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1633 /* 1629 */ MCD_OPC_Decode, 170, 1, 1, // Opcode: OR_s1_rrr /* 1633 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 1640 /* 1637 */ MCD_OPC_Decode, 74, 1, // Opcode: CMPEQ2_s1_rrr /* 1640 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 1647 /* 1644 */ MCD_OPC_Decode, 60, 1, // Opcode: AND_s1_rrr /* 1647 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1655 /* 1651 */ MCD_OPC_Decode, 225, 1, 1, // Opcode: SSHL_s1_rrr /* 1655 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1663 /* 1659 */ MCD_OPC_Decode, 210, 1, 38, // Opcode: SHRU_s1_prp /* 1663 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1671 /* 1667 */ MCD_OPC_Decode, 212, 1, 1, // Opcode: SHRU_s1_rrr /* 1671 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1678 /* 1675 */ MCD_OPC_Decode, 103, 1, // Opcode: EXTU_s1_rrr /* 1678 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1685 /* 1682 */ MCD_OPC_Decode, 105, 1, // Opcode: EXT_s1_rrr /* 1685 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1693 /* 1689 */ MCD_OPC_Decode, 198, 1, 25, // Opcode: SHL_s1_prp /* 1693 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1701 /* 1697 */ MCD_OPC_Decode, 202, 1, 39, // Opcode: SHL_s1_rrr /* 1701 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1709 /* 1705 */ MCD_OPC_Decode, 214, 1, 38, // Opcode: SHR_s1_prp /* 1709 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1717 /* 1713 */ MCD_OPC_Decode, 216, 1, 1, // Opcode: SHR_s1_rrr /* 1717 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 1725 /* 1721 */ MCD_OPC_Decode, 193, 1, 1, // Opcode: SET_s1_rrr /* 1725 */ MCD_OPC_FilterValue, 31, 236, 1, // Skip to: 2221 /* 1729 */ MCD_OPC_Decode, 73, 1, // Opcode: CLR_s1_rrr /* 1732 */ MCD_OPC_FilterValue, 25, 17, 0, // Skip to: 1753 /* 1736 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 1739 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1746 /* 1743 */ MCD_OPC_Decode, 122, 3, // Opcode: LDW_d5_mr /* 1746 */ MCD_OPC_FilterValue, 1, 215, 1, // Skip to: 2221 /* 1750 */ MCD_OPC_Decode, 115, 30, // Opcode: LDDW_d7_mp /* 1753 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1761 /* 1757 */ MCD_OPC_Decode, 158, 1, 23, // Opcode: MVKLH_s12_ir /* 1761 */ MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 1768 /* 1765 */ MCD_OPC_Decode, 123, 5, // Opcode: LDW_d6_mr /* 1768 */ MCD_OPC_FilterValue, 28, 216, 0, // Skip to: 1988 /* 1772 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 1775 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1783 /* 1779 */ MCD_OPC_Decode, 217, 1, 24, // Opcode: SMPY2_m1_rrp /* 1783 */ MCD_OPC_FilterValue, 1, 49, 0, // Skip to: 1836 /* 1787 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ... /* 1790 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1798 /* 1794 */ MCD_OPC_Decode, 151, 2, 21, // Opcode: XPND4_m2_rr /* 1798 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1806 /* 1802 */ MCD_OPC_Decode, 150, 2, 21, // Opcode: XPND2_m2_rr /* 1806 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1814 /* 1810 */ MCD_OPC_Decode, 157, 1, 21, // Opcode: MVD_m2_rr /* 1814 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1822 /* 1818 */ MCD_OPC_Decode, 194, 1, 21, // Opcode: SHFL_m2_rr /* 1822 */ MCD_OPC_FilterValue, 29, 3, 0, // Skip to: 1829 /* 1826 */ MCD_OPC_Decode, 94, 21, // Opcode: DEAL_m2_rr /* 1829 */ MCD_OPC_FilterValue, 30, 132, 1, // Skip to: 2221 /* 1833 */ MCD_OPC_Decode, 64, 21, // Opcode: BITC4_m2_rr /* 1836 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1844 /* 1840 */ MCD_OPC_Decode, 147, 1, 24, // Opcode: MPYSU4_m1_rrp /* 1844 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1851 /* 1848 */ MCD_OPC_Decode, 98, 1, // Opcode: DOTPNRSU2_m1_rrr /* 1851 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1858 /* 1855 */ MCD_OPC_Decode, 97, 1, // Opcode: DOTPN2_m1_rrr /* 1858 */ MCD_OPC_FilterValue, 5, 3, 0, // Skip to: 1865 /* 1862 */ MCD_OPC_Decode, 95, 24, // Opcode: DOTP2_m1_rrp /* 1865 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 1872 /* 1869 */ MCD_OPC_Decode, 99, 1, // Opcode: DOTPRSU2_m1_rrr /* 1872 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 1879 /* 1876 */ MCD_OPC_Decode, 110, 1, // Opcode: GMPY4_m1_rrr /* 1879 */ MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 1886 /* 1883 */ MCD_OPC_Decode, 61, 1, // Opcode: AVG2_m1_rrr /* 1886 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1894 /* 1890 */ MCD_OPC_Decode, 144, 1, 24, // Opcode: MPYLI_m1_rrp /* 1894 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1902 /* 1898 */ MCD_OPC_Decode, 182, 1, 1, // Opcode: ROTL_m1_rrr /* 1902 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1910 /* 1906 */ MCD_OPC_Decode, 165, 1, 2, // Opcode: OR_d2_rir /* 1910 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1918 /* 1914 */ MCD_OPC_Decode, 241, 1, 1, // Opcode: SUB2_d2_rrr /* 1918 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1925 /* 1922 */ MCD_OPC_Decode, 55, 2, // Opcode: AND_d2_rir /* 1925 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1932 /* 1929 */ MCD_OPC_Decode, 43, 2, // Opcode: ADD_d2_rir /* 1932 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1940 /* 1936 */ MCD_OPC_Decode, 144, 2, 2, // Opcode: XOR_d2_rir /* 1940 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1948 /* 1944 */ MCD_OPC_Decode, 185, 1, 1, // Opcode: SADDUS2_s4_rrr /* 1948 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1956 /* 1952 */ MCD_OPC_Decode, 184, 1, 1, // Opcode: SADDU4_s4_rrr /* 1956 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1964 /* 1960 */ MCD_OPC_Decode, 138, 2, 1, // Opcode: SUB_s4_rrr /* 1964 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1972 /* 1968 */ MCD_OPC_Decode, 204, 1, 1, // Opcode: SHR2_s4_rrr /* 1972 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1980 /* 1976 */ MCD_OPC_Decode, 196, 1, 1, // Opcode: SHLMB_s4_rrr /* 1980 */ MCD_OPC_FilterValue, 31, 237, 0, // Skip to: 2221 /* 1984 */ MCD_OPC_Decode, 172, 1, 1, // Opcode: PACK2_s4_rrr /* 1988 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 2011 /* 1992 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... /* 1995 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2003 /* 1999 */ MCD_OPC_Decode, 239, 1, 3, // Opcode: STW_d5_rm /* 2003 */ MCD_OPC_FilterValue, 1, 214, 0, // Skip to: 2221 /* 2007 */ MCD_OPC_Decode, 237, 1, 22, // Opcode: STNDW_d8_pm /* 2011 */ MCD_OPC_FilterValue, 30, 198, 0, // Skip to: 2213 /* 2015 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... /* 2018 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2025 /* 2022 */ MCD_OPC_Decode, 49, 1, // Opcode: ADD_l1_rrr_x2 /* 2025 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2033 /* 2029 */ MCD_OPC_Decode, 135, 2, 1, // Opcode: SUB_l1_rrr_x2 /* 2033 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2041 /* 2037 */ MCD_OPC_Decode, 231, 1, 1, // Opcode: SSUB_l1_rrr_x2 /* 2041 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 2049 /* 2045 */ MCD_OPC_Decode, 189, 1, 1, // Opcode: SADD_l1_rrr_x2 /* 2049 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 2057 /* 2053 */ MCD_OPC_Decode, 134, 2, 39, // Opcode: SUB_l1_rrr_x1 /* 2057 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 2065 /* 2061 */ MCD_OPC_Decode, 179, 1, 1, // Opcode: PACKLH2_l1_rrr_x2 /* 2065 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 2073 /* 2069 */ MCD_OPC_Decode, 230, 1, 39, // Opcode: SSUB_l1_rrr_x1 /* 2073 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 2080 /* 2077 */ MCD_OPC_Decode, 48, 24, // Opcode: ADD_l1_rrp_x2 /* 2080 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2088 /* 2084 */ MCD_OPC_Decode, 133, 2, 24, // Opcode: SUB_l1_rrp_x2 /* 2088 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 2095 /* 2092 */ MCD_OPC_Decode, 40, 24, // Opcode: ADDU_l1_rrp_x2 /* 2095 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2103 /* 2099 */ MCD_OPC_Decode, 254, 1, 24, // Opcode: SUBU_l1_rrp_x2 /* 2103 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2111 /* 2107 */ MCD_OPC_Decode, 132, 2, 37, // Opcode: SUB_l1_rrp_x1 /* 2111 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 2119 /* 2115 */ MCD_OPC_Decode, 253, 1, 37, // Opcode: SUBU_l1_rrp_x1 /* 2119 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 2126 /* 2123 */ MCD_OPC_Decode, 127, 1, // Opcode: MAXU4_l1_rrr_x2 /* 2126 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 2133 /* 2130 */ MCD_OPC_Decode, 85, 1, // Opcode: CMPGT_l1_rrr_x2 /* 2133 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 2141 /* 2137 */ MCD_OPC_Decode, 252, 1, 1, // Opcode: SUBC_l1_rrr_x2 /* 2141 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 2148 /* 2145 */ MCD_OPC_Decode, 109, 1, // Opcode: GMPGTU_l1_rrr_x2 /* 2148 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 2155 /* 2152 */ MCD_OPC_Decode, 79, 1, // Opcode: CMPEQ_l1_rrr_x2 /* 2155 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 2162 /* 2159 */ MCD_OPC_Decode, 93, 1, // Opcode: CMPLT_l1_rrr_x2 /* 2162 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 2169 /* 2166 */ MCD_OPC_Decode, 89, 1, // Opcode: CMPLTU_l1_rrr_x2 /* 2169 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 2183 /* 2173 */ MCD_OPC_CheckField, 13, 5, 0, 42, 0, // Skip to: 2221 /* 2179 */ MCD_OPC_Decode, 164, 1, 21, // Opcode: NORM_l1_rr /* 2183 */ MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 2190 /* 2187 */ MCD_OPC_Decode, 125, 1, // Opcode: LMBD_l1_rrr_x2 /* 2190 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 2198 /* 2194 */ MCD_OPC_Decode, 147, 2, 1, // Opcode: XOR_l1_rrr_x2 /* 2198 */ MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 2205 /* 2202 */ MCD_OPC_Decode, 58, 1, // Opcode: AND_l1_rrr_x2 /* 2205 */ MCD_OPC_FilterValue, 31, 12, 0, // Skip to: 2221 /* 2209 */ MCD_OPC_Decode, 168, 1, 1, // Opcode: OR_l1_rrr_x2 /* 2213 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 2221 /* 2217 */ MCD_OPC_Decode, 240, 1, 5, // Opcode: STW_d6_rm /* 2221 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { return true; } #define DecodeToMCInst(fname,fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, void *Decoder) { \ InsnType tmp; \ switch (Idx) { \ default: \ case 0: \ tmp = fieldname(insn, 13, 4); \ if (DecodeNop(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 1: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 2: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 3: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 9, 14) << 1; \ if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 4: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 8, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 5: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 16); \ if (DecodeMemOperand2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 6: \ tmp = fieldname(insn, 7, 21); \ if (DecodePCRelScst21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 7: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 8: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 9: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 10: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 11: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 12: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 13: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 10); \ if (DecodePCRelScst10(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 14: \ tmp = fieldname(insn, 16, 12); \ if (DecodePCRelScst12(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 15: \ tmp = fieldname(insn, 23, 5); \ if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 16: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 17: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 18: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 19: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 20: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 21: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 22: \ tmp = fieldname(insn, 24, 4); \ if (DecodeRegPair4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 9, 15) << 1; \ if (DecodeMemOperandSc(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 23: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 7, 16); \ if (DecodeScst16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 24: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 25: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 26: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 27: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 28: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 29: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 30: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= fieldname(insn, 7, 1) << 0; \ tmp |= fieldname(insn, 9, 14) << 1; \ if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 31: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 32: \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 33: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 16, 7); \ if (DecodePCRelScst7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 34: \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 35: \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 3); \ MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 36: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 37: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 38: \ tmp = fieldname(insn, 23, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 39: \ tmp = fieldname(insn, 23, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 18, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 13, 5); \ if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 12, 1); \ if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 29, 3); \ if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 28, 1); \ if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 1, 1); \ if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 1); \ if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address, \ MCRegisterInfo *MRI, \ int feature) { \ uint64_t Bits = getFeatureBits(feature); \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0, ExpectedValue; \ DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail; \ for (;;) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = (uint32_t) fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ Val = (InsnType) decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ ExpectedValue = (uint32_t) decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ PIdx = (uint32_t) decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ Pred = checkDecoderPredicate(PIdx, Bits); \ if (!Pred) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ Opc = (unsigned) decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = (unsigned) decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_setOpcode(MI, Opc); \ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ } \ case MCD_OPC_SoftFail: { \ PositiveMask = (InsnType) decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = (InsnType) decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ } FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc000064400000000000000000000227360072674642500230050ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Instruction Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { TMS320C64x_PHI = 0, TMS320C64x_INLINEASM = 1, TMS320C64x_CFI_INSTRUCTION = 2, TMS320C64x_EH_LABEL = 3, TMS320C64x_GC_LABEL = 4, TMS320C64x_KILL = 5, TMS320C64x_EXTRACT_SUBREG = 6, TMS320C64x_INSERT_SUBREG = 7, TMS320C64x_IMPLICIT_DEF = 8, TMS320C64x_SUBREG_TO_REG = 9, TMS320C64x_COPY_TO_REGCLASS = 10, TMS320C64x_DBG_VALUE = 11, TMS320C64x_REG_SEQUENCE = 12, TMS320C64x_COPY = 13, TMS320C64x_BUNDLE = 14, TMS320C64x_LIFETIME_START = 15, TMS320C64x_LIFETIME_END = 16, TMS320C64x_STACKMAP = 17, TMS320C64x_PATCHPOINT = 18, TMS320C64x_LOAD_STACK_GUARD = 19, TMS320C64x_STATEPOINT = 20, TMS320C64x_FRAME_ALLOC = 21, TMS320C64x_ABS2_l2_rr = 22, TMS320C64x_ABS_l1_pp = 23, TMS320C64x_ABS_l1_rr = 24, TMS320C64x_ADD2_d2_rrr = 25, TMS320C64x_ADD2_l1_rrr_x2 = 26, TMS320C64x_ADD2_s1_rrr = 27, TMS320C64x_ADD4_l1_rrr_x2 = 28, TMS320C64x_ADDAB_d1_rir = 29, TMS320C64x_ADDAB_d1_rrr = 30, TMS320C64x_ADDAD_d1_rir = 31, TMS320C64x_ADDAD_d1_rrr = 32, TMS320C64x_ADDAH_d1_rir = 33, TMS320C64x_ADDAH_d1_rrr = 34, TMS320C64x_ADDAW_d1_rir = 35, TMS320C64x_ADDAW_d1_rrr = 36, TMS320C64x_ADDKPC_s3_iir = 37, TMS320C64x_ADDK_s2_ir = 38, TMS320C64x_ADDU_l1_rpp = 39, TMS320C64x_ADDU_l1_rrp_x2 = 40, TMS320C64x_ADD_d1_rir = 41, TMS320C64x_ADD_d1_rrr = 42, TMS320C64x_ADD_d2_rir = 43, TMS320C64x_ADD_d2_rrr = 44, TMS320C64x_ADD_l1_ipp = 45, TMS320C64x_ADD_l1_irr = 46, TMS320C64x_ADD_l1_rpp = 47, TMS320C64x_ADD_l1_rrp_x2 = 48, TMS320C64x_ADD_l1_rrr_x2 = 49, TMS320C64x_ADD_s1_irr = 50, TMS320C64x_ADD_s1_rrr = 51, TMS320C64x_ANDN_d2_rrr = 52, TMS320C64x_ANDN_l1_rrr_x2 = 53, TMS320C64x_ANDN_s4_rrr = 54, TMS320C64x_AND_d2_rir = 55, TMS320C64x_AND_d2_rrr = 56, TMS320C64x_AND_l1_irr = 57, TMS320C64x_AND_l1_rrr_x2 = 58, TMS320C64x_AND_s1_irr = 59, TMS320C64x_AND_s1_rrr = 60, TMS320C64x_AVG2_m1_rrr = 61, TMS320C64x_AVGU4_m1_rrr = 62, TMS320C64x_BDEC_s8_ir = 63, TMS320C64x_BITC4_m2_rr = 64, TMS320C64x_BNOP_s10_ri = 65, TMS320C64x_BNOP_s9_ii = 66, TMS320C64x_BPOS_s8_ir = 67, TMS320C64x_B_s5_i = 68, TMS320C64x_B_s6_r = 69, TMS320C64x_B_s7_irp = 70, TMS320C64x_B_s7_nrp = 71, TMS320C64x_CLR_s15_riir = 72, TMS320C64x_CLR_s1_rrr = 73, TMS320C64x_CMPEQ2_s1_rrr = 74, TMS320C64x_CMPEQ4_s1_rrr = 75, TMS320C64x_CMPEQ_l1_ipr = 76, TMS320C64x_CMPEQ_l1_irr = 77, TMS320C64x_CMPEQ_l1_rpr = 78, TMS320C64x_CMPEQ_l1_rrr_x2 = 79, TMS320C64x_CMPGT2_s1_rrr = 80, TMS320C64x_CMPGTU4_s1_rrr = 81, TMS320C64x_CMPGT_l1_ipr = 82, TMS320C64x_CMPGT_l1_irr = 83, TMS320C64x_CMPGT_l1_rpr = 84, TMS320C64x_CMPGT_l1_rrr_x2 = 85, TMS320C64x_CMPLTU_l1_ipr = 86, TMS320C64x_CMPLTU_l1_irr = 87, TMS320C64x_CMPLTU_l1_rpr = 88, TMS320C64x_CMPLTU_l1_rrr_x2 = 89, TMS320C64x_CMPLT_l1_ipr = 90, TMS320C64x_CMPLT_l1_irr = 91, TMS320C64x_CMPLT_l1_rpr = 92, TMS320C64x_CMPLT_l1_rrr_x2 = 93, TMS320C64x_DEAL_m2_rr = 94, TMS320C64x_DOTP2_m1_rrp = 95, TMS320C64x_DOTP2_m1_rrr = 96, TMS320C64x_DOTPN2_m1_rrr = 97, TMS320C64x_DOTPNRSU2_m1_rrr = 98, TMS320C64x_DOTPRSU2_m1_rrr = 99, TMS320C64x_DOTPSU4_m1_rrr = 100, TMS320C64x_DOTPU4_m1_rrr = 101, TMS320C64x_EXTU_s15_riir = 102, TMS320C64x_EXTU_s1_rrr = 103, TMS320C64x_EXT_s15_riir = 104, TMS320C64x_EXT_s1_rrr = 105, TMS320C64x_GMPGTU_l1_ipr = 106, TMS320C64x_GMPGTU_l1_irr = 107, TMS320C64x_GMPGTU_l1_rpr = 108, TMS320C64x_GMPGTU_l1_rrr_x2 = 109, TMS320C64x_GMPY4_m1_rrr = 110, TMS320C64x_LDBU_d5_mr = 111, TMS320C64x_LDBU_d6_mr = 112, TMS320C64x_LDB_d5_mr = 113, TMS320C64x_LDB_d6_mr = 114, TMS320C64x_LDDW_d7_mp = 115, TMS320C64x_LDHU_d5_mr = 116, TMS320C64x_LDHU_d6_mr = 117, TMS320C64x_LDH_d5_mr = 118, TMS320C64x_LDH_d6_mr = 119, TMS320C64x_LDNDW_d8_mp = 120, TMS320C64x_LDNW_d5_mr = 121, TMS320C64x_LDW_d5_mr = 122, TMS320C64x_LDW_d6_mr = 123, TMS320C64x_LMBD_l1_irr = 124, TMS320C64x_LMBD_l1_rrr_x2 = 125, TMS320C64x_MAX2_l1_rrr_x2 = 126, TMS320C64x_MAXU4_l1_rrr_x2 = 127, TMS320C64x_MIN2_l1_rrr_x2 = 128, TMS320C64x_MINU4_l1_rrr_x2 = 129, TMS320C64x_MPY2_m1_rrp = 130, TMS320C64x_MPYHIR_m1_rrr = 131, TMS320C64x_MPYHI_m1_rrp = 132, TMS320C64x_MPYHLU_m4_rrr = 133, TMS320C64x_MPYHL_m4_rrr = 134, TMS320C64x_MPYHSLU_m4_rrr = 135, TMS320C64x_MPYHSU_m4_rrr = 136, TMS320C64x_MPYHULS_m4_rrr = 137, TMS320C64x_MPYHUS_m4_rrr = 138, TMS320C64x_MPYHU_m4_rrr = 139, TMS320C64x_MPYH_m4_rrr = 140, TMS320C64x_MPYLHU_m4_rrr = 141, TMS320C64x_MPYLH_m4_rrr = 142, TMS320C64x_MPYLIR_m1_rrr = 143, TMS320C64x_MPYLI_m1_rrp = 144, TMS320C64x_MPYLSHU_m4_rrr = 145, TMS320C64x_MPYLUHS_m4_rrr = 146, TMS320C64x_MPYSU4_m1_rrp = 147, TMS320C64x_MPYSU_m4_irr = 148, TMS320C64x_MPYSU_m4_rrr = 149, TMS320C64x_MPYU4_m1_rrp = 150, TMS320C64x_MPYUS_m4_rrr = 151, TMS320C64x_MPYU_m4_rrr = 152, TMS320C64x_MPY_m4_irr = 153, TMS320C64x_MPY_m4_rrr = 154, TMS320C64x_MVC_s1_rr = 155, TMS320C64x_MVC_s1_rr2 = 156, TMS320C64x_MVD_m2_rr = 157, TMS320C64x_MVKLH_s12_ir = 158, TMS320C64x_MVKL_s12_ir = 159, TMS320C64x_MVK_d1_rr = 160, TMS320C64x_MVK_l2_ir = 161, TMS320C64x_NOP_n = 162, TMS320C64x_NORM_l1_pr = 163, TMS320C64x_NORM_l1_rr = 164, TMS320C64x_OR_d2_rir = 165, TMS320C64x_OR_d2_rrr = 166, TMS320C64x_OR_l1_irr = 167, TMS320C64x_OR_l1_rrr_x2 = 168, TMS320C64x_OR_s1_irr = 169, TMS320C64x_OR_s1_rrr = 170, TMS320C64x_PACK2_l1_rrr_x2 = 171, TMS320C64x_PACK2_s4_rrr = 172, TMS320C64x_PACKH2_l1_rrr_x2 = 173, TMS320C64x_PACKH2_s1_rrr = 174, TMS320C64x_PACKH4_l1_rrr_x2 = 175, TMS320C64x_PACKHL2_l1_rrr_x2 = 176, TMS320C64x_PACKHL2_s1_rrr = 177, TMS320C64x_PACKL4_l1_rrr_x2 = 178, TMS320C64x_PACKLH2_l1_rrr_x2 = 179, TMS320C64x_PACKLH2_s1_rrr = 180, TMS320C64x_ROTL_m1_rir = 181, TMS320C64x_ROTL_m1_rrr = 182, TMS320C64x_SADD2_s4_rrr = 183, TMS320C64x_SADDU4_s4_rrr = 184, TMS320C64x_SADDUS2_s4_rrr = 185, TMS320C64x_SADD_l1_ipp = 186, TMS320C64x_SADD_l1_irr = 187, TMS320C64x_SADD_l1_rpp = 188, TMS320C64x_SADD_l1_rrr_x2 = 189, TMS320C64x_SADD_s1_rrr = 190, TMS320C64x_SAT_l1_pr = 191, TMS320C64x_SET_s15_riir = 192, TMS320C64x_SET_s1_rrr = 193, TMS320C64x_SHFL_m2_rr = 194, TMS320C64x_SHLMB_l1_rrr_x2 = 195, TMS320C64x_SHLMB_s4_rrr = 196, TMS320C64x_SHL_s1_pip = 197, TMS320C64x_SHL_s1_prp = 198, TMS320C64x_SHL_s1_rip = 199, TMS320C64x_SHL_s1_rir = 200, TMS320C64x_SHL_s1_rrp = 201, TMS320C64x_SHL_s1_rrr = 202, TMS320C64x_SHR2_s1_rir = 203, TMS320C64x_SHR2_s4_rrr = 204, TMS320C64x_SHRMB_l1_rrr_x2 = 205, TMS320C64x_SHRMB_s4_rrr = 206, TMS320C64x_SHRU2_s1_rir = 207, TMS320C64x_SHRU2_s4_rrr = 208, TMS320C64x_SHRU_s1_pip = 209, TMS320C64x_SHRU_s1_prp = 210, TMS320C64x_SHRU_s1_rir = 211, TMS320C64x_SHRU_s1_rrr = 212, TMS320C64x_SHR_s1_pip = 213, TMS320C64x_SHR_s1_prp = 214, TMS320C64x_SHR_s1_rir = 215, TMS320C64x_SHR_s1_rrr = 216, TMS320C64x_SMPY2_m1_rrp = 217, TMS320C64x_SMPYHL_m4_rrr = 218, TMS320C64x_SMPYH_m4_rrr = 219, TMS320C64x_SMPYLH_m4_rrr = 220, TMS320C64x_SMPY_m4_rrr = 221, TMS320C64x_SPACK2_s4_rrr = 222, TMS320C64x_SPACKU4_s4_rrr = 223, TMS320C64x_SSHL_s1_rir = 224, TMS320C64x_SSHL_s1_rrr = 225, TMS320C64x_SSHVL_m1_rrr = 226, TMS320C64x_SSHVR_m1_rrr = 227, TMS320C64x_SSUB_l1_ipp = 228, TMS320C64x_SSUB_l1_irr = 229, TMS320C64x_SSUB_l1_rrr_x1 = 230, TMS320C64x_SSUB_l1_rrr_x2 = 231, TMS320C64x_STB_d5_rm = 232, TMS320C64x_STB_d6_rm = 233, TMS320C64x_STDW_d7_pm = 234, TMS320C64x_STH_d5_rm = 235, TMS320C64x_STH_d6_rm = 236, TMS320C64x_STNDW_d8_pm = 237, TMS320C64x_STNW_d5_rm = 238, TMS320C64x_STW_d5_rm = 239, TMS320C64x_STW_d6_rm = 240, TMS320C64x_SUB2_d2_rrr = 241, TMS320C64x_SUB2_l1_rrr_x2 = 242, TMS320C64x_SUB2_s1_rrr = 243, TMS320C64x_SUB4_l1_rrr_x2 = 244, TMS320C64x_SUBABS4_l1_rrr_x2 = 245, TMS320C64x_SUBAB_d1_rir = 246, TMS320C64x_SUBAB_d1_rrr = 247, TMS320C64x_SUBAH_d1_rir = 248, TMS320C64x_SUBAH_d1_rrr = 249, TMS320C64x_SUBAW_d1_rir = 250, TMS320C64x_SUBAW_d1_rrr = 251, TMS320C64x_SUBC_l1_rrr_x2 = 252, TMS320C64x_SUBU_l1_rrp_x1 = 253, TMS320C64x_SUBU_l1_rrp_x2 = 254, TMS320C64x_SUB_d1_rir = 255, TMS320C64x_SUB_d1_rrr = 256, TMS320C64x_SUB_d2_rrr = 257, TMS320C64x_SUB_l1_ipp = 258, TMS320C64x_SUB_l1_irr = 259, TMS320C64x_SUB_l1_rrp_x1 = 260, TMS320C64x_SUB_l1_rrp_x2 = 261, TMS320C64x_SUB_l1_rrr_x1 = 262, TMS320C64x_SUB_l1_rrr_x2 = 263, TMS320C64x_SUB_s1_irr = 264, TMS320C64x_SUB_s1_rrr = 265, TMS320C64x_SUB_s4_rrr = 266, TMS320C64x_SWAP4_l2_rr = 267, TMS320C64x_UNPKHU4_l2_rr = 268, TMS320C64x_UNPKHU4_s14_rr = 269, TMS320C64x_UNPKLU4_l2_rr = 270, TMS320C64x_UNPKLU4_s14_rr = 271, TMS320C64x_XOR_d2_rir = 272, TMS320C64x_XOR_d2_rrr = 273, TMS320C64x_XOR_l1_irr = 274, TMS320C64x_XOR_l1_rrr_x2 = 275, TMS320C64x_XOR_s1_irr = 276, TMS320C64x_XOR_s1_rrr = 277, TMS320C64x_XPND2_m2_rr = 278, TMS320C64x_XPND4_m2_rr = 279, TMS320C64x_INSTRUCTION_LIST_END = 280 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc000064400000000000000000000222470072674642500234670ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { TMS320C64x_NoRegister, TMS320C64x_AMR = 1, TMS320C64x_CSR = 2, TMS320C64x_DIER = 3, TMS320C64x_DNUM = 4, TMS320C64x_ECR = 5, TMS320C64x_GFPGFR = 6, TMS320C64x_GPLYA = 7, TMS320C64x_GPLYB = 8, TMS320C64x_ICR = 9, TMS320C64x_IER = 10, TMS320C64x_IERR = 11, TMS320C64x_ILC = 12, TMS320C64x_IRP = 13, TMS320C64x_ISR = 14, TMS320C64x_ISTP = 15, TMS320C64x_ITSR = 16, TMS320C64x_NRP = 17, TMS320C64x_NTSR = 18, TMS320C64x_REP = 19, TMS320C64x_RILC = 20, TMS320C64x_SSR = 21, TMS320C64x_TSCH = 22, TMS320C64x_TSCL = 23, TMS320C64x_TSR = 24, TMS320C64x_A0 = 25, TMS320C64x_A1 = 26, TMS320C64x_A2 = 27, TMS320C64x_A3 = 28, TMS320C64x_A4 = 29, TMS320C64x_A5 = 30, TMS320C64x_A6 = 31, TMS320C64x_A7 = 32, TMS320C64x_A8 = 33, TMS320C64x_A9 = 34, TMS320C64x_A10 = 35, TMS320C64x_A11 = 36, TMS320C64x_A12 = 37, TMS320C64x_A13 = 38, TMS320C64x_A14 = 39, TMS320C64x_A15 = 40, TMS320C64x_A16 = 41, TMS320C64x_A17 = 42, TMS320C64x_A18 = 43, TMS320C64x_A19 = 44, TMS320C64x_A20 = 45, TMS320C64x_A21 = 46, TMS320C64x_A22 = 47, TMS320C64x_A23 = 48, TMS320C64x_A24 = 49, TMS320C64x_A25 = 50, TMS320C64x_A26 = 51, TMS320C64x_A27 = 52, TMS320C64x_A28 = 53, TMS320C64x_A29 = 54, TMS320C64x_A30 = 55, TMS320C64x_A31 = 56, TMS320C64x_B0 = 57, TMS320C64x_B1 = 58, TMS320C64x_B2 = 59, TMS320C64x_B3 = 60, TMS320C64x_B4 = 61, TMS320C64x_B5 = 62, TMS320C64x_B6 = 63, TMS320C64x_B7 = 64, TMS320C64x_B8 = 65, TMS320C64x_B9 = 66, TMS320C64x_B10 = 67, TMS320C64x_B11 = 68, TMS320C64x_B12 = 69, TMS320C64x_B13 = 70, TMS320C64x_B14 = 71, TMS320C64x_B15 = 72, TMS320C64x_B16 = 73, TMS320C64x_B17 = 74, TMS320C64x_B18 = 75, TMS320C64x_B19 = 76, TMS320C64x_B20 = 77, TMS320C64x_B21 = 78, TMS320C64x_B22 = 79, TMS320C64x_B23 = 80, TMS320C64x_B24 = 81, TMS320C64x_B25 = 82, TMS320C64x_B26 = 83, TMS320C64x_B27 = 84, TMS320C64x_B28 = 85, TMS320C64x_B29 = 86, TMS320C64x_B30 = 87, TMS320C64x_B31 = 88, TMS320C64x_PCE1 = 89, TMS320C64x_NUM_TARGET_REGS // 90 }; // Register classes enum { TMS320C64x_GPRegsRegClassID = 0, TMS320C64x_AFRegsRegClassID = 1, TMS320C64x_BFRegsRegClassID = 2, TMS320C64x_ControlRegsRegClassID = 3, }; #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg TMS320C64xRegDiffLists[] = { /* 0 */ 65535, 0, }; static const uint16_t TMS320C64xSubRegIdxLists[] = { /* 0 */ 0, }; static const MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0 }, { 310, 1, 1, 0, 1 }, { 319, 1, 1, 0, 1 }, { 298, 1, 1, 0, 1 }, { 268, 1, 1, 0, 1 }, { 290, 1, 1, 0, 1 }, { 303, 1, 1, 0, 1 }, { 241, 1, 1, 0, 1 }, { 247, 1, 1, 0, 1 }, { 294, 1, 1, 0, 1 }, { 299, 1, 1, 0, 1 }, { 314, 1, 1, 0, 1 }, { 254, 1, 1, 0, 1 }, { 277, 1, 1, 0, 1 }, { 323, 1, 1, 0, 1 }, { 285, 1, 1, 0, 1 }, { 331, 1, 1, 0, 1 }, { 281, 1, 1, 0, 1 }, { 336, 1, 1, 0, 1 }, { 273, 1, 1, 0, 1 }, { 253, 1, 1, 0, 1 }, { 327, 1, 1, 0, 1 }, { 258, 1, 1, 0, 1 }, { 263, 1, 1, 0, 1 }, { 332, 1, 1, 0, 1 }, { 24, 1, 1, 0, 1 }, { 54, 1, 1, 0, 1 }, { 81, 1, 1, 0, 1 }, { 103, 1, 1, 0, 1 }, { 125, 1, 1, 0, 1 }, { 147, 1, 1, 0, 1 }, { 169, 1, 1, 0, 1 }, { 191, 1, 1, 0, 1 }, { 213, 1, 1, 0, 1 }, { 235, 1, 1, 0, 1 }, { 0, 1, 1, 0, 1 }, { 30, 1, 1, 0, 1 }, { 65, 1, 1, 0, 1 }, { 87, 1, 1, 0, 1 }, { 109, 1, 1, 0, 1 }, { 131, 1, 1, 0, 1 }, { 153, 1, 1, 0, 1 }, { 175, 1, 1, 0, 1 }, { 197, 1, 1, 0, 1 }, { 219, 1, 1, 0, 1 }, { 8, 1, 1, 0, 1 }, { 38, 1, 1, 0, 1 }, { 73, 1, 1, 0, 1 }, { 95, 1, 1, 0, 1 }, { 117, 1, 1, 0, 1 }, { 139, 1, 1, 0, 1 }, { 161, 1, 1, 0, 1 }, { 183, 1, 1, 0, 1 }, { 205, 1, 1, 0, 1 }, { 227, 1, 1, 0, 1 }, { 16, 1, 1, 0, 1 }, { 46, 1, 1, 0, 1 }, { 27, 1, 1, 0, 1 }, { 57, 1, 1, 0, 1 }, { 84, 1, 1, 0, 1 }, { 106, 1, 1, 0, 1 }, { 128, 1, 1, 0, 1 }, { 150, 1, 1, 0, 1 }, { 172, 1, 1, 0, 1 }, { 194, 1, 1, 0, 1 }, { 216, 1, 1, 0, 1 }, { 238, 1, 1, 0, 1 }, { 4, 1, 1, 0, 1 }, { 34, 1, 1, 0, 1 }, { 69, 1, 1, 0, 1 }, { 91, 1, 1, 0, 1 }, { 113, 1, 1, 0, 1 }, { 135, 1, 1, 0, 1 }, { 157, 1, 1, 0, 1 }, { 179, 1, 1, 0, 1 }, { 201, 1, 1, 0, 1 }, { 223, 1, 1, 0, 1 }, { 12, 1, 1, 0, 1 }, { 42, 1, 1, 0, 1 }, { 77, 1, 1, 0, 1 }, { 99, 1, 1, 0, 1 }, { 121, 1, 1, 0, 1 }, { 143, 1, 1, 0, 1 }, { 165, 1, 1, 0, 1 }, { 187, 1, 1, 0, 1 }, { 209, 1, 1, 0, 1 }, { 231, 1, 1, 0, 1 }, { 20, 1, 1, 0, 1 }, { 50, 1, 1, 0, 1 }, { 60, 1, 1, 0, 1 }, }; // GPRegs Register Class... static const MCPhysReg GPRegs[] = { TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31, }; // GPRegs Bit set. static const uint8_t GPRegsBits[] = { 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, }; // AFRegs Register Class... static const MCPhysReg AFRegs[] = { TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, }; // AFRegs Bit set. static const uint8_t AFRegsBits[] = { 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // BFRegs Register Class... static const MCPhysReg BFRegs[] = { TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31, }; // BFRegs Bit set. static const uint8_t BFRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // ControlRegs Register Class... static const MCPhysReg ControlRegs[] = { TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR, }; // ControlRegs Bit set. static const uint8_t ControlRegsBits[] = { 0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, }; static const MCRegisterClass TMS320C64xMCRegisterClasses[] = { { GPRegs, GPRegsBits, TMS320C64x_GPRegsRegClassID }, { AFRegs, AFRegsBits, TMS320C64x_AFRegsRegClassID }, { BFRegs, BFRegsBits, TMS320C64x_BFRegsRegClassID }, { ControlRegs, ControlRegsBits, TMS320C64x_ControlRegsRegClassID }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c000064400000000000000000000423750072674642500223730ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifdef CAPSTONE_HAS_TMS320C64X #ifdef _MSC_VER // Disable security warnings for strcpy #ifndef _CRT_SECURE_NO_WARNINGS #define _CRT_SECURE_NO_WARNINGS #endif // Banned API Usage : strcpy is a Banned API as listed in dontuse.h for // security purposes. #pragma warning(disable:28719) #endif #include #include #include "TMS320C64xInstPrinter.h" #include "../../MCInst.h" #include "../../utils.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" #include "TMS320C64xMapping.h" #include "capstone/tms320c64x.h" static const char *getRegisterName(unsigned RegNo); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O); static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O); static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O); void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { SStream ss; char *p, *p2, tmp[8]; unsigned int unit = 0; int i; cs_tms320c64x *tms320c64x; if (mci->csh->detail) { tms320c64x = &mci->flat_insn->detail->tms320c64x; for (i = 0; i < insn->detail->groups_count; i++) { switch(insn->detail->groups[i]) { case TMS320C64X_GRP_FUNIT_D: unit = TMS320C64X_FUNIT_D; break; case TMS320C64X_GRP_FUNIT_L: unit = TMS320C64X_FUNIT_L; break; case TMS320C64X_GRP_FUNIT_M: unit = TMS320C64X_FUNIT_M; break; case TMS320C64X_GRP_FUNIT_S: unit = TMS320C64X_FUNIT_S; break; case TMS320C64X_GRP_FUNIT_NO: unit = TMS320C64X_FUNIT_NO; break; } if (unit != 0) break; } tms320c64x->funit.unit = unit; SStream_Init(&ss); if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg)); p = strchr(insn_asm, '\t'); if (p != NULL) *p++ = '\0'; SStream_concat0(&ss, insn_asm); if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) { while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b'))) p2--; if (p2 == p) { strcpy(insn_asm, "Invalid!"); return; } if (*p2 == 'a') strcpy(tmp, "1T"); else strcpy(tmp, "2T"); } else { tmp[0] = '\0'; } switch(tms320c64x->funit.unit) { case TMS320C64X_FUNIT_D: SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side); break; case TMS320C64X_FUNIT_L: SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side); break; case TMS320C64X_FUNIT_M: SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side); break; case TMS320C64X_FUNIT_S: SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side); break; } if (tms320c64x->funit.crosspath > 0) SStream_concat0(&ss, "X"); if (p != NULL) SStream_concat(&ss, "\t%s", p); if (tms320c64x->parallel != 0) SStream_concat(&ss, "\t||"); /* insn_asm is a buffer from an SStream, so there should be enough space */ strcpy(insn_asm, ss.buffer); } } #define PRINT_ALIAS_INSTR #include "TMS320C64xGenAsmWriter.inc" #define GET_INSTRINFO_ENUM #include "TMS320C64xGenInstrInfo.inc" static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); unsigned reg; if (MCOperand_isReg(Op)) { reg = MCOperand_getReg(Op); if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) { switch(reg) { case TMS320C64X_REG_EFR: SStream_concat0(O, "EFR"); break; case TMS320C64X_REG_IFR: SStream_concat0(O, "IFR"); break; default: SStream_concat0(O, getRegisterName(reg)); break; } } else { SStream_concat0(O, getRegisterName(reg)); } if (MI->csh->detail) { MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG; MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg; MI->flat_insn->detail->tms320c64x.op_count++; } } else if (MCOperand_isImm(Op)) { int64_t Imm = MCOperand_getImm(Op); if (Imm >= 0) { if (Imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, Imm); else SStream_concat(O, "%"PRIu64, Imm); } else { if (Imm < -HEX_THRESHOLD) SStream_concat(O, "-0x%"PRIx64, -Imm); else SStream_concat(O, "-%"PRIu64, -Imm); } if (MI->csh->detail) { MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM; MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm; MI->flat_insn->detail->tms320c64x.op_count++; } } } static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); int64_t Val = MCOperand_getImm(Op); unsigned scaled, base, offset, mode, unit; cs_tms320c64x *tms320c64x; char st, nd; scaled = (Val >> 19) & 1; base = (Val >> 12) & 0x7f; offset = (Val >> 5) & 0x7f; mode = (Val >> 1) & 0xf; unit = Val & 1; if (scaled) { st = '['; nd = ']'; } else { st = '('; nd = ')'; } switch(mode) { case 0: SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd); break; case 1: SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd); break; case 4: SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); break; case 5: SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); break; case 8: SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd); break; case 9: SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd); break; case 10: SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd); break; case 11: SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd); break; case 12: SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); break; case 13: SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); break; case 14: SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); break; case 15: SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd); break; } if (MI->csh->detail) { tms320c64x = &MI->flat_insn->detail->tms320c64x; tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM; tms320c64x->operands[tms320c64x->op_count].mem.base = base; tms320c64x->operands[tms320c64x->op_count].mem.disp = offset; tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1; tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled; switch(mode) { case 0: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; break; case 1: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; break; case 4: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; break; case 5: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; break; case 8: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; break; case 9: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; break; case 10: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; break; case 11: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; break; case 12: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; break; case 13: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE; break; case 14: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; break; case 15: tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST; break; } tms320c64x->op_count++; } } static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); int64_t Val = MCOperand_getImm(Op); uint16_t offset; unsigned basereg; cs_tms320c64x *tms320c64x; basereg = Val & 0x7f; offset = (Val >> 7) & 0x7fff; SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset); if (MI->csh->detail) { tms320c64x = &MI->flat_insn->detail->tms320c64x; tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM; tms320c64x->operands[tms320c64x->op_count].mem.base = basereg; tms320c64x->operands[tms320c64x->op_count].mem.unit = 2; tms320c64x->operands[tms320c64x->op_count].mem.disp = offset; tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT; tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW; tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO; tms320c64x->op_count++; } } static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); unsigned reg = MCOperand_getReg(Op); cs_tms320c64x *tms320c64x; SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg)); if (MI->csh->detail) { tms320c64x = &MI->flat_insn->detail->tms320c64x; tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR; tms320c64x->operands[tms320c64x->op_count].reg = reg; tms320c64x->op_count++; } } static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { unsigned opcode = MCInst_getOpcode(MI); MCOperand *op; switch(opcode) { /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */ case TMS320C64x_ADD_d2_rir: /* ADD.L -i, x, y -> SUB.L x, i, y */ case TMS320C64x_ADD_l1_irr: case TMS320C64x_ADD_l1_ipp: /* ADD.S -i, x, y -> SUB.S x, i, y */ case TMS320C64x_ADD_s1_irr: if ((MCInst_getNumOperands(MI) == 3) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) { MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB); op = MCInst_getOperand(MI, 2); MCOperand_setImm(op, -MCOperand_getImm(op)); SStream_concat0(O, "SUB\t"); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* ADD.D 0, x, y -> MV.D x, y */ case TMS320C64x_ADD_d1_rir: /* OR.D x, 0, y -> MV.D x, y */ case TMS320C64x_OR_d2_rir: /* ADD.L 0, x, y -> MV.L x, y */ case TMS320C64x_ADD_l1_irr: case TMS320C64x_ADD_l1_ipp: /* OR.L 0, x, y -> MV.L x, y */ case TMS320C64x_OR_l1_irr: /* ADD.S 0, x, y -> MV.S x, y */ case TMS320C64x_ADD_s1_irr: /* OR.S 0, x, y -> MV.S x, y */ case TMS320C64x_OR_s1_irr: if ((MCInst_getNumOperands(MI) == 3) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) { MCInst_setOpcodePub(MI, TMS320C64X_INS_MV); MI->size--; SStream_concat0(O, "MV\t"); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* XOR.D -1, x, y -> NOT.D x, y */ case TMS320C64x_XOR_d2_rir: /* XOR.L -1, x, y -> NOT.L x, y */ case TMS320C64x_XOR_l1_irr: /* XOR.S -1, x, y -> NOT.S x, y */ case TMS320C64x_XOR_s1_irr: if ((MCInst_getNumOperands(MI) == 3) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) { MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT); MI->size--; SStream_concat0(O, "NOT\t"); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* MVK.D 0, x -> ZERO.D x */ case TMS320C64x_MVK_d1_rr: /* MVK.L 0, x -> ZERO.L x */ case TMS320C64x_MVK_l2_ir: if ((MCInst_getNumOperands(MI) == 2) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isImm(MCInst_getOperand(MI, 1)) && (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) { MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO); MI->size--; SStream_concat0(O, "ZERO\t"); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* SUB.L x, x, y -> ZERO.L y */ case TMS320C64x_SUB_l1_rrp_x1: /* SUB.S x, x, y -> ZERO.S y */ case TMS320C64x_SUB_s1_rrr: if ((MCInst_getNumOperands(MI) == 3) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) { MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO); MI->size -= 2; SStream_concat0(O, "ZERO\t"); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* SUB.L 0, x, y -> NEG.L x, y */ case TMS320C64x_SUB_l1_irr: case TMS320C64x_SUB_l1_ipp: /* SUB.S 0, x, y -> NEG.S x, y */ case TMS320C64x_SUB_s1_irr: if ((MCInst_getNumOperands(MI) == 3) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) { MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG); MI->size--; SStream_concat0(O, "NEG\t"); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* PACKLH2.L x, x, y -> SWAP2.L x, y */ case TMS320C64x_PACKLH2_l1_rrr_x2: /* PACKLH2.S x, x, y -> SWAP2.S x, y */ case TMS320C64x_PACKLH2_s1_rrr: if ((MCInst_getNumOperands(MI) == 3) && MCOperand_isReg(MCInst_getOperand(MI, 0)) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) { MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2); MI->size--; SStream_concat0(O, "SWAP2\t"); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return true; } break; } switch(opcode) { /* NOP 16 -> IDLE */ /* NOP 1 -> NOP */ case TMS320C64x_NOP_n: if ((MCInst_getNumOperands(MI) == 1) && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) { MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE); MI->size--; SStream_concat0(O, "IDLE"); return true; } if ((MCInst_getNumOperands(MI) == 1) && MCOperand_isImm(MCInst_getOperand(MI, 0)) && (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) { MI->size--; SStream_concat0(O, "NOP"); return true; } break; } return false; } void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info) { if (!printAliasInstruction(MI, O, Info)) printInstruction(MI, O, Info); } #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h000064400000000000000000000006320072674642500223660ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifndef CS_TMS320C64XINSTPRINTER_H #define CS_TMS320C64XINSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info); void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xMapping.c000064400000000000000000001313540072674642500215010ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifdef CAPSTONE_HAS_TMS320C64X #include // debug #include #include "../../utils.h" #include "TMS320C64xMapping.h" #define GET_INSTRINFO_ENUM #include "TMS320C64xGenInstrInfo.inc" static const name_map reg_name_maps[] = { { TMS320C64X_REG_INVALID, NULL }, { TMS320C64X_REG_AMR, "amr" }, { TMS320C64X_REG_CSR, "csr" }, { TMS320C64X_REG_DIER, "dier" }, { TMS320C64X_REG_DNUM, "dnum" }, { TMS320C64X_REG_ECR, "ecr" }, { TMS320C64X_REG_GFPGFR, "gfpgfr" }, { TMS320C64X_REG_GPLYA, "gplya" }, { TMS320C64X_REG_GPLYB, "gplyb" }, { TMS320C64X_REG_ICR, "icr" }, { TMS320C64X_REG_IER, "ier" }, { TMS320C64X_REG_IERR, "ierr" }, { TMS320C64X_REG_ILC, "ilc" }, { TMS320C64X_REG_IRP, "irp" }, { TMS320C64X_REG_ISR, "isr" }, { TMS320C64X_REG_ISTP, "istp" }, { TMS320C64X_REG_ITSR, "itsr" }, { TMS320C64X_REG_NRP, "nrp" }, { TMS320C64X_REG_NTSR, "ntsr" }, { TMS320C64X_REG_REP, "rep" }, { TMS320C64X_REG_RILC, "rilc" }, { TMS320C64X_REG_SSR, "ssr" }, { TMS320C64X_REG_TSCH, "tsch" }, { TMS320C64X_REG_TSCL, "tscl" }, { TMS320C64X_REG_TSR, "tsr" }, { TMS320C64X_REG_A0, "a0" }, { TMS320C64X_REG_A1, "a1" }, { TMS320C64X_REG_A2, "a2" }, { TMS320C64X_REG_A3, "a3" }, { TMS320C64X_REG_A4, "a4" }, { TMS320C64X_REG_A5, "a5" }, { TMS320C64X_REG_A6, "a6" }, { TMS320C64X_REG_A7, "a7" }, { TMS320C64X_REG_A8, "a8" }, { TMS320C64X_REG_A9, "a9" }, { TMS320C64X_REG_A10, "a10" }, { TMS320C64X_REG_A11, "a11" }, { TMS320C64X_REG_A12, "a12" }, { TMS320C64X_REG_A13, "a13" }, { TMS320C64X_REG_A14, "a14" }, { TMS320C64X_REG_A15, "a15" }, { TMS320C64X_REG_A16, "a16" }, { TMS320C64X_REG_A17, "a17" }, { TMS320C64X_REG_A18, "a18" }, { TMS320C64X_REG_A19, "a19" }, { TMS320C64X_REG_A20, "a20" }, { TMS320C64X_REG_A21, "a21" }, { TMS320C64X_REG_A22, "a22" }, { TMS320C64X_REG_A23, "a23" }, { TMS320C64X_REG_A24, "a24" }, { TMS320C64X_REG_A25, "a25" }, { TMS320C64X_REG_A26, "a26" }, { TMS320C64X_REG_A27, "a27" }, { TMS320C64X_REG_A28, "a28" }, { TMS320C64X_REG_A29, "a29" }, { TMS320C64X_REG_A30, "a30" }, { TMS320C64X_REG_A31, "a31" }, { TMS320C64X_REG_B0, "b0" }, { TMS320C64X_REG_B1, "b1" }, { TMS320C64X_REG_B2, "b2" }, { TMS320C64X_REG_B3, "b3" }, { TMS320C64X_REG_B4, "b4" }, { TMS320C64X_REG_B5, "b5" }, { TMS320C64X_REG_B6, "b6" }, { TMS320C64X_REG_B7, "b7" }, { TMS320C64X_REG_B8, "b8" }, { TMS320C64X_REG_B9, "b9" }, { TMS320C64X_REG_B10, "b10" }, { TMS320C64X_REG_B11, "b11" }, { TMS320C64X_REG_B12, "b12" }, { TMS320C64X_REG_B13, "b13" }, { TMS320C64X_REG_B14, "b14" }, { TMS320C64X_REG_B15, "b15" }, { TMS320C64X_REG_B16, "b16" }, { TMS320C64X_REG_B17, "b17" }, { TMS320C64X_REG_B18, "b18" }, { TMS320C64X_REG_B19, "b19" }, { TMS320C64X_REG_B20, "b20" }, { TMS320C64X_REG_B21, "b21" }, { TMS320C64X_REG_B22, "b22" }, { TMS320C64X_REG_B23, "b23" }, { TMS320C64X_REG_B24, "b24" }, { TMS320C64X_REG_B25, "b25" }, { TMS320C64X_REG_B26, "b26" }, { TMS320C64X_REG_B27, "b27" }, { TMS320C64X_REG_B28, "b28" }, { TMS320C64X_REG_B29, "b29" }, { TMS320C64X_REG_B30, "b30" }, { TMS320C64X_REG_B31, "b31" }, { TMS320C64X_REG_PCE1, "pce1" }, }; const char *TMS320C64x_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } tms320c64x_reg TMS320C64x_reg_id(char *name) { int i; for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { if (!strcmp(name, reg_name_maps[i].name)) return reg_name_maps[i].id; } return 0; } static const insn_map insns[] = { { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { TMS320C64x_ABS2_l2_rr, TMS320C64X_INS_ABS2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ABS_l1_pp, TMS320C64X_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ABS_l1_rr, TMS320C64X_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD2_d2_rrr, TMS320C64X_INS_ADD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADD2_l1_rrr_x2, TMS320C64X_INS_ADD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD2_s1_rrr, TMS320C64X_INS_ADD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_ADD4_l1_rrr_x2, TMS320C64X_INS_ADD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAB_d1_rir, TMS320C64X_INS_ADDAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAB_d1_rrr, TMS320C64X_INS_ADDAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAD_d1_rir, TMS320C64X_INS_ADDAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAD_d1_rrr, TMS320C64X_INS_ADDAD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAH_d1_rir, TMS320C64X_INS_ADDAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAH_d1_rrr, TMS320C64X_INS_ADDAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAW_d1_rir, TMS320C64X_INS_ADDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDAW_d1_rrr, TMS320C64X_INS_ADDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADDKPC_s3_iir, TMS320C64X_INS_ADDKPC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_ADDK_s2_ir, TMS320C64X_INS_ADDK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_ADDU_l1_rpp, TMS320C64X_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADDU_l1_rrp_x2, TMS320C64X_INS_ADDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_d1_rir, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_d1_rrr, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_d2_rir, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_d2_rrr, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_l1_ipp, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_l1_irr, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_l1_rpp, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_l1_rrp_x2, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_l1_rrr_x2, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_s1_irr, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_ADD_s1_rrr, TMS320C64X_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_ANDN_d2_rrr, TMS320C64X_INS_ANDN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_ANDN_l1_rrr_x2, TMS320C64X_INS_ANDN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_ANDN_s4_rrr, TMS320C64X_INS_ANDN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_AND_d2_rir, TMS320C64X_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_AND_d2_rrr, TMS320C64X_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_AND_l1_irr, TMS320C64X_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_AND_l1_rrr_x2, TMS320C64X_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_AND_s1_irr, TMS320C64X_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_AND_s1_rrr, TMS320C64X_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_AVG2_m1_rrr, TMS320C64X_INS_AVG2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_AVGU4_m1_rrr, TMS320C64X_INS_AVGU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_BDEC_s8_ir, TMS320C64X_INS_BDEC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_BITC4_m2_rr, TMS320C64X_INS_BITC4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_BNOP_s10_ri, TMS320C64X_INS_BNOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_BNOP_s9_ii, TMS320C64X_INS_BNOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_BPOS_s8_ir, TMS320C64X_INS_BPOS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_B_s5_i, TMS320C64X_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_B_s6_r, TMS320C64X_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_B_s7_irp, TMS320C64X_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_B_s7_nrp, TMS320C64X_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0 #endif }, { TMS320C64x_CLR_s15_riir, TMS320C64X_INS_CLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_CLR_s1_rrr, TMS320C64X_INS_CLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_CMPEQ2_s1_rrr, TMS320C64X_INS_CMPEQ2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_CMPEQ4_s1_rrr, TMS320C64X_INS_CMPEQ4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_CMPEQ_l1_ipr, TMS320C64X_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPEQ_l1_irr, TMS320C64X_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPEQ_l1_rpr, TMS320C64X_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPEQ_l1_rrr_x2, TMS320C64X_INS_CMPEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPGT2_s1_rrr, TMS320C64X_INS_CMPGT2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_CMPGTU4_s1_rrr, TMS320C64X_INS_CMPGTU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_CMPGT_l1_ipr, TMS320C64X_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPGT_l1_irr, TMS320C64X_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPGT_l1_rpr, TMS320C64X_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPGT_l1_rrr_x2, TMS320C64X_INS_CMPGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLTU_l1_ipr, TMS320C64X_INS_CMPLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLTU_l1_irr, TMS320C64X_INS_CMPLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLTU_l1_rpr, TMS320C64X_INS_CMPLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLTU_l1_rrr_x2, TMS320C64X_INS_CMPLTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLT_l1_ipr, TMS320C64X_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLT_l1_irr, TMS320C64X_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLT_l1_rpr, TMS320C64X_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_CMPLT_l1_rrr_x2, TMS320C64X_INS_CMPLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_DEAL_m2_rr, TMS320C64X_INS_DEAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTP2_m1_rrp, TMS320C64X_INS_DOTP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTP2_m1_rrr, TMS320C64X_INS_DOTP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTPN2_m1_rrr, TMS320C64X_INS_DOTPN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTPNRSU2_m1_rrr, TMS320C64X_INS_DOTPNRSU2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTPRSU2_m1_rrr, TMS320C64X_INS_DOTPRSU2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTPSU4_m1_rrr, TMS320C64X_INS_DOTPSU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_DOTPU4_m1_rrr, TMS320C64X_INS_DOTPU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_EXTU_s15_riir, TMS320C64X_INS_EXTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_EXTU_s1_rrr, TMS320C64X_INS_EXTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_EXT_s15_riir, TMS320C64X_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_EXT_s1_rrr, TMS320C64X_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_GMPGTU_l1_ipr, TMS320C64X_INS_GMPGTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_GMPGTU_l1_irr, TMS320C64X_INS_GMPGTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_GMPGTU_l1_rpr, TMS320C64X_INS_GMPGTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_GMPGTU_l1_rrr_x2, TMS320C64X_INS_GMPGTU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_GMPY4_m1_rrr, TMS320C64X_INS_GMPY4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_LDBU_d5_mr, TMS320C64X_INS_LDBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDBU_d6_mr, TMS320C64X_INS_LDBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDB_d5_mr, TMS320C64X_INS_LDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDB_d6_mr, TMS320C64X_INS_LDB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDDW_d7_mp, TMS320C64X_INS_LDDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDHU_d5_mr, TMS320C64X_INS_LDHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDHU_d6_mr, TMS320C64X_INS_LDHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDH_d5_mr, TMS320C64X_INS_LDH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDH_d6_mr, TMS320C64X_INS_LDH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDNDW_d8_mp, TMS320C64X_INS_LDNDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDNW_d5_mr, TMS320C64X_INS_LDNW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDW_d5_mr, TMS320C64X_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LDW_d6_mr, TMS320C64X_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_LMBD_l1_irr, TMS320C64X_INS_LMBD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_LMBD_l1_rrr_x2, TMS320C64X_INS_LMBD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_MAX2_l1_rrr_x2, TMS320C64X_INS_MAX2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_MAXU4_l1_rrr_x2, TMS320C64X_INS_MAXU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_MIN2_l1_rrr_x2, TMS320C64X_INS_MIN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_MINU4_l1_rrr_x2, TMS320C64X_INS_MINU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_MPY2_m1_rrp, TMS320C64X_INS_MPY2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHIR_m1_rrr, TMS320C64X_INS_MPYHIR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHI_m1_rrp, TMS320C64X_INS_MPYHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHLU_m4_rrr, TMS320C64X_INS_MPYHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHL_m4_rrr, TMS320C64X_INS_MPYHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHSLU_m4_rrr, TMS320C64X_INS_MPYHSLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHSU_m4_rrr, TMS320C64X_INS_MPYHSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHULS_m4_rrr, TMS320C64X_INS_MPYHULS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHUS_m4_rrr, TMS320C64X_INS_MPYHUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYHU_m4_rrr, TMS320C64X_INS_MPYHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYH_m4_rrr, TMS320C64X_INS_MPYH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYLHU_m4_rrr, TMS320C64X_INS_MPYLHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYLH_m4_rrr, TMS320C64X_INS_MPYLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYLIR_m1_rrr, TMS320C64X_INS_MPYLIR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYLI_m1_rrp, TMS320C64X_INS_MPYLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYLSHU_m4_rrr, TMS320C64X_INS_MPYLSHU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYLUHS_m4_rrr, TMS320C64X_INS_MPYLUHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYSU4_m1_rrp, TMS320C64X_INS_MPYSU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYSU_m4_irr, TMS320C64X_INS_MPYSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYSU_m4_rrr, TMS320C64X_INS_MPYSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYU4_m1_rrp, TMS320C64X_INS_MPYU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYUS_m4_rrr, TMS320C64X_INS_MPYUS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPYU_m4_rrr, TMS320C64X_INS_MPYU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPY_m4_irr, TMS320C64X_INS_MPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MPY_m4_rrr, TMS320C64X_INS_MPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MVC_s1_rr, TMS320C64X_INS_MVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_MVC_s1_rr2, TMS320C64X_INS_MVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_MVD_m2_rr, TMS320C64X_INS_MVD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_MVKLH_s12_ir, TMS320C64X_INS_MVKLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_MVKL_s12_ir, TMS320C64X_INS_MVKL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_MVK_d1_rr, TMS320C64X_INS_MVK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_MVK_l2_ir, TMS320C64X_INS_MVK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_NOP_n, TMS320C64X_INS_NOP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_NO, 0 }, 0, 0 #endif }, { TMS320C64x_NORM_l1_pr, TMS320C64X_INS_NORM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_NORM_l1_rr, TMS320C64X_INS_NORM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_OR_d2_rir, TMS320C64X_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_OR_d2_rrr, TMS320C64X_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_OR_l1_irr, TMS320C64X_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_OR_l1_rrr_x2, TMS320C64X_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_OR_s1_irr, TMS320C64X_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_OR_s1_rrr, TMS320C64X_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_PACK2_l1_rrr_x2, TMS320C64X_INS_PACK2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_PACK2_s4_rrr, TMS320C64X_INS_PACK2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_PACKH2_l1_rrr_x2, TMS320C64X_INS_PACKH2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_PACKH2_s1_rrr, TMS320C64X_INS_PACKH2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_PACKH4_l1_rrr_x2, TMS320C64X_INS_PACKH4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_PACKHL2_l1_rrr_x2, TMS320C64X_INS_PACKHL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_PACKHL2_s1_rrr, TMS320C64X_INS_PACKHL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_PACKL4_l1_rrr_x2, TMS320C64X_INS_PACKL4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_PACKLH2_l1_rrr_x2, TMS320C64X_INS_PACKLH2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_PACKLH2_s1_rrr, TMS320C64X_INS_PACKLH2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_ROTL_m1_rir, TMS320C64X_INS_ROTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_ROTL_m1_rrr, TMS320C64X_INS_ROTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SADD2_s4_rrr, TMS320C64X_INS_SADD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SADDU4_s4_rrr, TMS320C64X_INS_SADDU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SADDUS2_s4_rrr, TMS320C64X_INS_SADDUS2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SADD_l1_ipp, TMS320C64X_INS_SADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SADD_l1_irr, TMS320C64X_INS_SADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SADD_l1_rpp, TMS320C64X_INS_SADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SADD_l1_rrr_x2, TMS320C64X_INS_SADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SADD_s1_rrr, TMS320C64X_INS_SADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SAT_l1_pr, TMS320C64X_INS_SAT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SET_s15_riir, TMS320C64X_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SET_s1_rrr, TMS320C64X_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHFL_m2_rr, TMS320C64X_INS_SHFL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SHLMB_l1_rrr_x2, TMS320C64X_INS_SHLMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SHLMB_s4_rrr, TMS320C64X_INS_SHLMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHL_s1_pip, TMS320C64X_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHL_s1_prp, TMS320C64X_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHL_s1_rip, TMS320C64X_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHL_s1_rir, TMS320C64X_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHL_s1_rrp, TMS320C64X_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHL_s1_rrr, TMS320C64X_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHR2_s1_rir, TMS320C64X_INS_SHR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHR2_s4_rrr, TMS320C64X_INS_SHR2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRMB_l1_rrr_x2, TMS320C64X_INS_SHRMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SHRMB_s4_rrr, TMS320C64X_INS_SHRMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRU2_s1_rir, TMS320C64X_INS_SHRU2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRU2_s4_rrr, TMS320C64X_INS_SHRU2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRU_s1_pip, TMS320C64X_INS_SHRU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRU_s1_prp, TMS320C64X_INS_SHRU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRU_s1_rir, TMS320C64X_INS_SHRU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHRU_s1_rrr, TMS320C64X_INS_SHRU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHR_s1_pip, TMS320C64X_INS_SHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHR_s1_prp, TMS320C64X_INS_SHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHR_s1_rir, TMS320C64X_INS_SHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SHR_s1_rrr, TMS320C64X_INS_SHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SMPY2_m1_rrp, TMS320C64X_INS_SMPY2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SMPYHL_m4_rrr, TMS320C64X_INS_SMPYHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SMPYH_m4_rrr, TMS320C64X_INS_SMPYH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SMPYLH_m4_rrr, TMS320C64X_INS_SMPYLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SMPY_m4_rrr, TMS320C64X_INS_SMPY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SPACK2_s4_rrr, TMS320C64X_INS_SPACK2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SPACKU4_s4_rrr, TMS320C64X_INS_SPACKU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SSHL_s1_rir, TMS320C64X_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SSHL_s1_rrr, TMS320C64X_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SSHVL_m1_rrr, TMS320C64X_INS_SSHVL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SSHVR_m1_rrr, TMS320C64X_INS_SSHVR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_SSUB_l1_ipp, TMS320C64X_INS_SSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SSUB_l1_irr, TMS320C64X_INS_SSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SSUB_l1_rrr_x1, TMS320C64X_INS_SSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SSUB_l1_rrr_x2, TMS320C64X_INS_SSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_STB_d5_rm, TMS320C64X_INS_STB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STB_d6_rm, TMS320C64X_INS_STB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STDW_d7_pm, TMS320C64X_INS_STDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STH_d5_rm, TMS320C64X_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STH_d6_rm, TMS320C64X_INS_STH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STNDW_d8_pm, TMS320C64X_INS_STNDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STNW_d5_rm, TMS320C64X_INS_STNW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STW_d5_rm, TMS320C64X_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_STW_d6_rm, TMS320C64X_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUB2_d2_rrr, TMS320C64X_INS_SUB2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUB2_l1_rrr_x2, TMS320C64X_INS_SUB2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB2_s1_rrr, TMS320C64X_INS_SUB2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SUB4_l1_rrr_x2, TMS320C64X_INS_SUB4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUBABS4_l1_rrr_x2, TMS320C64X_INS_SUBABS4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUBAB_d1_rir, TMS320C64X_INS_SUBAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUBAB_d1_rrr, TMS320C64X_INS_SUBAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUBAH_d1_rir, TMS320C64X_INS_SUBAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUBAH_d1_rrr, TMS320C64X_INS_SUBAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUBAW_d1_rir, TMS320C64X_INS_SUBAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUBAW_d1_rrr, TMS320C64X_INS_SUBAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUBC_l1_rrr_x2, TMS320C64X_INS_SUBC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUBU_l1_rrp_x1, TMS320C64X_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUBU_l1_rrp_x2, TMS320C64X_INS_SUBU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_d1_rir, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_d1_rrr, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_d2_rrr, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_l1_ipp, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_l1_irr, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_l1_rrp_x1, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_l1_rrp_x2, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_l1_rrr_x1, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_l1_rrr_x2, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_s1_irr, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_s1_rrr, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SUB_s4_rrr, TMS320C64X_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_SWAP4_l2_rr, TMS320C64X_INS_SWAP4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_UNPKHU4_l2_rr, TMS320C64X_INS_UNPKHU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_UNPKHU4_s14_rr, TMS320C64X_INS_UNPKHU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_UNPKLU4_l2_rr, TMS320C64X_INS_UNPKLU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_UNPKLU4_s14_rr, TMS320C64X_INS_UNPKLU4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_XOR_d2_rir, TMS320C64X_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_XOR_d2_rrr, TMS320C64X_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0 #endif }, { TMS320C64x_XOR_l1_irr, TMS320C64X_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_XOR_l1_rrr_x2, TMS320C64X_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0 #endif }, { TMS320C64x_XOR_s1_irr, TMS320C64X_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_XOR_s1_rrr, TMS320C64X_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0 #endif }, { TMS320C64x_XPND2_m2_rr, TMS320C64X_INS_XPND2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, { TMS320C64x_XPND4_m2_rr, TMS320C64X_INS_XPND4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0 #endif }, }; void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned short i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { insn->detail->groups[insn->detail->groups_count] = TMS320C64X_GRP_JUMP; insn->detail->groups_count++; } #endif } } } #ifndef CAPSTONE_DIET //grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}' static const name_map insn_name_maps[] = { {TMS320C64X_INS_INVALID, NULL}, {TMS320C64X_INS_ABS, "abs"}, {TMS320C64X_INS_ABS2, "abs2"}, {TMS320C64X_INS_ADD, "add"}, {TMS320C64X_INS_ADD2, "add2"}, {TMS320C64X_INS_ADD4, "add4"}, {TMS320C64X_INS_ADDAB, "addab"}, {TMS320C64X_INS_ADDAD, "addad"}, {TMS320C64X_INS_ADDAH, "addah"}, {TMS320C64X_INS_ADDAW, "addaw"}, {TMS320C64X_INS_ADDK, "addk"}, {TMS320C64X_INS_ADDKPC, "addkpc"}, {TMS320C64X_INS_ADDU, "addu"}, {TMS320C64X_INS_AND, "and"}, {TMS320C64X_INS_ANDN, "andn"}, {TMS320C64X_INS_AVG2, "avg2"}, {TMS320C64X_INS_AVGU4, "avgu4"}, {TMS320C64X_INS_B, "b"}, {TMS320C64X_INS_BDEC, "bdec"}, {TMS320C64X_INS_BITC4, "bitc4"}, {TMS320C64X_INS_BNOP, "bnop"}, {TMS320C64X_INS_BPOS, "bpos"}, {TMS320C64X_INS_CLR, "clr"}, {TMS320C64X_INS_CMPEQ, "cmpeq"}, {TMS320C64X_INS_CMPEQ2, "cmpeq2"}, {TMS320C64X_INS_CMPEQ4, "cmpeq4"}, {TMS320C64X_INS_CMPGT, "cmpgt"}, {TMS320C64X_INS_CMPGT2, "cmpgt2"}, {TMS320C64X_INS_CMPGTU4, "cmpgtu4"}, {TMS320C64X_INS_CMPLT, "cmplt"}, {TMS320C64X_INS_CMPLTU, "cmpltu"}, {TMS320C64X_INS_DEAL, "deal"}, {TMS320C64X_INS_DOTP2, "dotp2"}, {TMS320C64X_INS_DOTPN2, "dotpn2"}, {TMS320C64X_INS_DOTPNRSU2, "dotpnrsu2"}, {TMS320C64X_INS_DOTPRSU2, "dotprsu2"}, {TMS320C64X_INS_DOTPSU4, "dotpsu4"}, {TMS320C64X_INS_DOTPU4, "dotpu4"}, {TMS320C64X_INS_EXT, "ext"}, {TMS320C64X_INS_EXTU, "extu"}, {TMS320C64X_INS_GMPGTU, "gmpgtu"}, {TMS320C64X_INS_GMPY4, "gmpy4"}, {TMS320C64X_INS_LDB, "ldb"}, {TMS320C64X_INS_LDBU, "ldbu"}, {TMS320C64X_INS_LDDW, "lddw"}, {TMS320C64X_INS_LDH, "ldh"}, {TMS320C64X_INS_LDHU, "ldhu"}, {TMS320C64X_INS_LDNDW, "ldndw"}, {TMS320C64X_INS_LDNW, "ldnw"}, {TMS320C64X_INS_LDW, "ldw"}, {TMS320C64X_INS_LMBD, "lmbd"}, {TMS320C64X_INS_MAX2, "max2"}, {TMS320C64X_INS_MAXU4, "maxu4"}, {TMS320C64X_INS_MIN2, "min2"}, {TMS320C64X_INS_MINU4, "minu4"}, {TMS320C64X_INS_MPY, "mpy"}, {TMS320C64X_INS_MPY2, "mpy2"}, {TMS320C64X_INS_MPYH, "mpyh"}, {TMS320C64X_INS_MPYHI, "mpyhi"}, {TMS320C64X_INS_MPYHIR, "mpyhir"}, {TMS320C64X_INS_MPYHL, "mpyhl"}, {TMS320C64X_INS_MPYHLU, "mpyhlu"}, {TMS320C64X_INS_MPYHSLU, "mpyhslu"}, {TMS320C64X_INS_MPYHSU, "mpyhsu"}, {TMS320C64X_INS_MPYHU, "mpyhu"}, {TMS320C64X_INS_MPYHULS, "mpyhuls"}, {TMS320C64X_INS_MPYHUS, "mpyhus"}, {TMS320C64X_INS_MPYLH, "mpylh"}, {TMS320C64X_INS_MPYLHU, "mpylhu"}, {TMS320C64X_INS_MPYLI, "mpyli"}, {TMS320C64X_INS_MPYLIR, "mpylir"}, {TMS320C64X_INS_MPYLSHU, "mpylshu"}, {TMS320C64X_INS_MPYLUHS, "mpyluhs"}, {TMS320C64X_INS_MPYSU, "mpysu"}, {TMS320C64X_INS_MPYSU4, "mpysu4"}, {TMS320C64X_INS_MPYU, "mpyu"}, {TMS320C64X_INS_MPYU4, "mpyu4"}, {TMS320C64X_INS_MPYUS, "mpyus"}, {TMS320C64X_INS_MVC, "mvc"}, {TMS320C64X_INS_MVD, "mvd"}, {TMS320C64X_INS_MVK, "mvk"}, {TMS320C64X_INS_MVKL, "mvkl"}, {TMS320C64X_INS_MVKLH, "mvklh"}, {TMS320C64X_INS_NOP, "nop"}, {TMS320C64X_INS_NORM, "norm"}, {TMS320C64X_INS_OR, "or"}, {TMS320C64X_INS_PACK2, "pack2"}, {TMS320C64X_INS_PACKH2, "packh2"}, {TMS320C64X_INS_PACKH4, "packh4"}, {TMS320C64X_INS_PACKHL2, "packhl2"}, {TMS320C64X_INS_PACKL4, "packl4"}, {TMS320C64X_INS_PACKLH2, "packlh2"}, {TMS320C64X_INS_ROTL, "rotl"}, {TMS320C64X_INS_SADD, "sadd"}, {TMS320C64X_INS_SADD2, "sadd2"}, {TMS320C64X_INS_SADDU4, "saddu4"}, {TMS320C64X_INS_SADDUS2, "saddus2"}, {TMS320C64X_INS_SAT, "sat"}, {TMS320C64X_INS_SET, "set"}, {TMS320C64X_INS_SHFL, "shfl"}, {TMS320C64X_INS_SHL, "shl"}, {TMS320C64X_INS_SHLMB, "shlmb"}, {TMS320C64X_INS_SHR, "shr"}, {TMS320C64X_INS_SHR2, "shr2"}, {TMS320C64X_INS_SHRMB, "shrmb"}, {TMS320C64X_INS_SHRU, "shru"}, {TMS320C64X_INS_SHRU2, "shru2"}, {TMS320C64X_INS_SMPY, "smpy"}, {TMS320C64X_INS_SMPY2, "smpy2"}, {TMS320C64X_INS_SMPYH, "smpyh"}, {TMS320C64X_INS_SMPYHL, "smpyhl"}, {TMS320C64X_INS_SMPYLH, "smpylh"}, {TMS320C64X_INS_SPACK2, "spack2"}, {TMS320C64X_INS_SPACKU4, "spacku4"}, {TMS320C64X_INS_SSHL, "sshl"}, {TMS320C64X_INS_SSHVL, "sshvl"}, {TMS320C64X_INS_SSHVR, "sshvr"}, {TMS320C64X_INS_SSUB, "ssub"}, {TMS320C64X_INS_STB, "stb"}, {TMS320C64X_INS_STDW, "stdw"}, {TMS320C64X_INS_STH, "sth"}, {TMS320C64X_INS_STNDW, "stndw"}, {TMS320C64X_INS_STNW, "stnw"}, {TMS320C64X_INS_STW, "stw"}, {TMS320C64X_INS_SUB, "sub"}, {TMS320C64X_INS_SUB2, "sub2"}, {TMS320C64X_INS_SUB4, "sub4"}, {TMS320C64X_INS_SUBAB, "subab"}, {TMS320C64X_INS_SUBABS4, "subabs4"}, {TMS320C64X_INS_SUBAH, "subah"}, {TMS320C64X_INS_SUBAW, "subaw"}, {TMS320C64X_INS_SUBC, "subc"}, {TMS320C64X_INS_SUBU, "subu"}, {TMS320C64X_INS_SWAP4, "swap4"}, {TMS320C64X_INS_UNPKHU4, "unpkhu4"}, {TMS320C64X_INS_UNPKLU4, "unpklu4"}, {TMS320C64X_INS_XOR, "xor"}, {TMS320C64X_INS_XPND2, "xpnd2"}, {TMS320C64X_INS_XPND4, "xpnd4"}, {TMS320C64X_INS_IDLE, "idle"}, {TMS320C64X_INS_MV, "mv"}, {TMS320C64X_INS_NEG, "neg"}, {TMS320C64X_INS_NOT, "not"}, {TMS320C64X_INS_SWAP2, "swap2"}, {TMS320C64X_INS_ZERO, "zero"}, }; #endif const char *TMS320C64x_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= TMS320C64X_INS_ENDING) return NULL; return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { { TMS320C64X_GRP_INVALID, NULL }, { TMS320C64X_GRP_FUNIT_D, "funit_d" }, { TMS320C64X_GRP_FUNIT_L, "funit_l" }, { TMS320C64X_GRP_FUNIT_M, "funit_m" }, { TMS320C64X_GRP_FUNIT_S, "funit_s" }, { TMS320C64X_GRP_FUNIT_NO, "funit_no" }, { TMS320C64X_GRP_JUMP, "jump" }, }; #endif const char *TMS320C64x_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET unsigned int i; if (id >= TMS320C64X_GRP_ENDING) return NULL; for (i = 0; i < ARR_SIZE(group_name_maps); i++) { if (group_name_maps[i].id == id) return group_name_maps[i].name; } return group_name_maps[id].name; #else return NULL; #endif } tms320c64x_reg TMS320C64x_map_register(unsigned int r) { static unsigned int map[] = { 0, }; if (r < ARR_SIZE(map)) return map[r]; return 0; } #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xMapping.h000064400000000000000000000013640072674642500215030ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifndef CS_TMS320C64X_MAP_H #define CS_TMS320C64X_MAP_H #include "capstone/capstone.h" // return name of regiser in friendly string const char *TMS320C64x_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *TMS320C64x_insn_name(csh handle, unsigned int id); const char *TMS320C64x_group_name(csh handle, unsigned int id); // map internal raw register to 'public' register tms320c64x_reg TMS320C64x_map_register(unsigned int r); // map register name to register ID tms320c64x_reg TMS320C64x_reg_id(char *name); #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xModule.c000064400000000000000000000016170072674642500213310ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifdef CAPSTONE_HAS_TMS320C64X #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "TMS320C64xDisassembler.h" #include "TMS320C64xInstPrinter.h" #include "TMS320C64xMapping.h" #include "TMS320C64xModule.h" cs_err TMS320C64x_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); TMS320C64x_init(mri); ud->printer = TMS320C64x_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = TMS320C64x_getInstruction; ud->post_printer = TMS320C64x_post_printer; ud->reg_name = TMS320C64x_reg_name; ud->insn_id = TMS320C64x_get_insn_id; ud->insn_name = TMS320C64x_insn_name; ud->group_name = TMS320C64x_group_name; return CS_ERR_OK; } cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value) { return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/TMS320C64x/TMS320C64xModule.h000064400000000000000000000004650072674642500213360ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_TMS320C64X_MODULE_H #define CS_TMS320C64X_MODULE_H #include "../../utils.h" cs_err TMS320C64x_global_init(cs_struct *ud); cs_err TMS320C64x_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/WASM/WASMDisassembler.c000064400000000000000000000565570072674642500211620ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #include #include // offsetof macro // alternatively #include "../../utils.h" like everyone else #include "WASMDisassembler.h" #include "WASMMapping.h" #include "../../cs_priv.h" static const short opcodes[256] = { WASM_INS_UNREACHABLE, WASM_INS_NOP, WASM_INS_BLOCK, WASM_INS_LOOP, WASM_INS_IF, WASM_INS_ELSE, -1, -1, -1, -1, -1, WASM_INS_END, WASM_INS_BR, WASM_INS_BR_IF, WASM_INS_BR_TABLE, WASM_INS_RETURN, WASM_INS_CALL, WASM_INS_CALL_INDIRECT, -1, -1, -1, -1, -1, -1, -1, -1, WASM_INS_DROP, WASM_INS_SELECT, -1, -1, -1, -1, WASM_INS_GET_LOCAL, WASM_INS_SET_LOCAL, WASM_INS_TEE_LOCAL, WASM_INS_GET_GLOBAL, WASM_INS_SET_GLOBAL, -1, -1, -1, WASM_INS_I32_LOAD, WASM_INS_I64_LOAD, WASM_INS_F32_LOAD, WASM_INS_F64_LOAD, WASM_INS_I32_LOAD8_S, WASM_INS_I32_LOAD8_U, WASM_INS_I32_LOAD16_S, WASM_INS_I32_LOAD16_U, WASM_INS_I64_LOAD8_S, WASM_INS_I64_LOAD8_U, WASM_INS_I64_LOAD16_S, WASM_INS_I64_LOAD16_U, WASM_INS_I64_LOAD32_S, WASM_INS_I64_LOAD32_U, WASM_INS_I32_STORE, WASM_INS_I64_STORE, WASM_INS_F32_STORE, WASM_INS_F64_STORE, WASM_INS_I32_STORE8, WASM_INS_I32_STORE16, WASM_INS_I64_STORE8, WASM_INS_I64_STORE16, WASM_INS_I64_STORE32, WASM_INS_CURRENT_MEMORY, WASM_INS_GROW_MEMORY, WASM_INS_I32_CONST, WASM_INS_I64_CONST, WASM_INS_F32_CONST, WASM_INS_F64_CONST, WASM_INS_I32_EQZ, WASM_INS_I32_EQ, WASM_INS_I32_NE, WASM_INS_I32_LT_S, WASM_INS_I32_LT_U, WASM_INS_I32_GT_S, WASM_INS_I32_GT_U, WASM_INS_I32_LE_S, WASM_INS_I32_LE_U, WASM_INS_I32_GE_S, WASM_INS_I32_GE_U, WASM_INS_I64_EQZ, WASM_INS_I64_EQ, WASM_INS_I64_NE, WASM_INS_I64_LT_S, WASM_INS_I64_LT_U, WASN_INS_I64_GT_S, WASM_INS_I64_GT_U, WASM_INS_I64_LE_S, WASM_INS_I64_LE_U, WASM_INS_I64_GE_S, WASM_INS_I64_GE_U, WASM_INS_F32_EQ, WASM_INS_F32_NE, WASM_INS_F32_LT, WASM_INS_F32_GT, WASM_INS_F32_LE, WASM_INS_F32_GE, WASM_INS_F64_EQ, WASM_INS_F64_NE, WASM_INS_F64_LT, WASM_INS_F64_GT, WASM_INS_F64_LE, WASM_INS_F64_GE, WASM_INS_I32_CLZ, WASM_INS_I32_CTZ, WASM_INS_I32_POPCNT, WASM_INS_I32_ADD, WASM_INS_I32_SUB, WASM_INS_I32_MUL, WASM_INS_I32_DIV_S, WASM_INS_I32_DIV_U, WASM_INS_I32_REM_S, WASM_INS_I32_REM_U, WASM_INS_I32_AND, WASM_INS_I32_OR, WASM_INS_I32_XOR, WASM_INS_I32_SHL, WASM_INS_I32_SHR_S, WASM_INS_I32_SHR_U, WASM_INS_I32_ROTL, WASM_INS_I32_ROTR, WASM_INS_I64_CLZ, WASM_INS_I64_CTZ, WASM_INS_I64_POPCNT, WASM_INS_I64_ADD, WASM_INS_I64_SUB, WASM_INS_I64_MUL, WASM_INS_I64_DIV_S, WASM_INS_I64_DIV_U, WASM_INS_I64_REM_S, WASM_INS_I64_REM_U, WASM_INS_I64_AND, WASM_INS_I64_OR, WASM_INS_I64_XOR, WASM_INS_I64_SHL, WASM_INS_I64_SHR_S, WASM_INS_I64_SHR_U, WASM_INS_I64_ROTL, WASM_INS_I64_ROTR, WASM_INS_F32_ABS, WASM_INS_F32_NEG, WASM_INS_F32_CEIL, WASM_INS_F32_FLOOR, WASM_INS_F32_TRUNC, WASM_INS_F32_NEAREST, WASM_INS_F32_SQRT, WASM_INS_F32_ADD, WASM_INS_F32_SUB, WASM_INS_F32_MUL, WASM_INS_F32_DIV, WASM_INS_F32_MIN, WASM_INS_F32_MAX, WASM_INS_F32_COPYSIGN, WASM_INS_F64_ABS, WASM_INS_F64_NEG, WASM_INS_F64_CEIL, WASM_INS_F64_FLOOR, WASM_INS_F64_TRUNC, WASM_INS_F64_NEAREST, WASM_INS_F64_SQRT, WASM_INS_F64_ADD, WASM_INS_F64_SUB, WASM_INS_F64_MUL, WASM_INS_F64_DIV, WASM_INS_F64_MIN, WASM_INS_F64_MAX, WASM_INS_F64_COPYSIGN, WASM_INS_I32_WARP_I64, WASP_INS_I32_TRUNC_S_F32, WASM_INS_I32_TRUNC_U_F32, WASM_INS_I32_TRUNC_S_F64, WASM_INS_I32_TRUNC_U_F64, WASM_INS_I64_EXTEND_S_I32, WASM_INS_I64_EXTEND_U_I32, WASM_INS_I64_TRUNC_S_F32, WASM_INS_I64_TRUNC_U_F32, WASM_INS_I64_TRUNC_S_F64, WASM_INS_I64_TRUNC_U_F64, WASM_INS_F32_CONVERT_S_I32, WASM_INS_F32_CONVERT_U_I32, WASM_INS_F32_CONVERT_S_I64, WASM_INS_F32_CONVERT_U_I64, WASM_INS_F32_DEMOTE_F64, WASM_INS_F64_CONVERT_S_I32, WASM_INS_F64_CONVERT_U_I32, WASM_INS_F64_CONVERT_S_I64, WASM_INS_F64_CONVERT_U_I64, WASM_INS_F64_PROMOTE_F32, WASM_INS_I32_REINTERPRET_F32, WASM_INS_I64_REINTERPRET_F64, WASM_INS_F32_REINTERPRET_I32, WASM_INS_F64_REINTERPRET_I64, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }; // input | code: code pointer start from varuint32 // | code_len: real code len count from varint // | leng: return value, means length of varint. -1 means error // return | varint static uint32_t get_varuint32(const uint8_t *code, size_t code_len, size_t *leng) { uint32_t data = 0; int i; for(i = 0;; i++) { if (code_len < i + 1) { *leng = -1; return 0; } if (i > 4 || (i == 4 && (code[i] & 0x7f) > 0x0f)) { *leng = -1; return 0; } data = data + (((uint32_t) code[i] & 0x7f) << (i * 7)); if (code[i] >> 7 == 0) { break; } } *leng = i + 1; return data; } // input | code : code pointer start from varuint64 // | code_len : real code len count from varint // | leng: return value, means length of varint. -1 means error // return | varint static uint64_t get_varuint64(const uint8_t *code, size_t code_len, size_t *leng) { uint64_t data; int i; data = 0; for(i = 0;; i++){ if (code_len < i + 1) { *leng = -1; return 0; } if (i > 9 || (i == 9 && (code[i] & 0x7f) > 0x01)) { *leng = -1; return 0; } data = data + (((uint64_t) code[i] & 0x7f) << (i * 7)); if (code[i] >> 7 == 0) { break; } } *leng = i + 1; return data; } // input | code : code pointer start from uint32 // | dest : the pointer where we store the uint32 // return | None static void get_uint32(const uint8_t *code, uint32_t *dest) { memcpy(dest, code, 4); } // input | code : code pointer start from uint32 // | dest : the pointer where we store the uint64 // return | None static void get_uint64(const uint8_t *code, uint64_t *dest) { memcpy(dest, code, 8); } // input | code : code pointer start from varint7 // | code_len : start from the code pointer to the end, how long is it // | leng : length of the param , -1 means error // return | data of varint7 static int8_t get_varint7(const uint8_t *code, size_t code_len, size_t *leng) { int8_t data; if (code_len < 1) { *leng = -1; return -1; } *leng = 1; if (code[0] == 0x40) { return -1; } data = code[0] & 0x7f; return data; } // input | code : code pointer start from varuint32 // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_varuint32(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { size_t len = 0; uint32_t data; data = get_varuint32(code, code_len, &len); if (len == -1) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_VARUINT32; MI->flat_insn->detail->wasm.operands[0].size= len; MI->flat_insn->detail->wasm.operands[0].varuint32= data; } MI->wasm_data.size = len; MI->wasm_data.type = WASM_OP_VARUINT32; MI->wasm_data.uint32 = data; *param_size = len; return true; } // input | code : code pointer start from varuint64 // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_varuint64(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { size_t len = 0; uint64_t data; data = get_varuint64(code, code_len, &len); if (len == -1) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_VARUINT64; MI->flat_insn->detail->wasm.operands[0].size = len; MI->flat_insn->detail->wasm.operands[0].varuint64 = data; } MI->wasm_data.size = len; MI->wasm_data.type = WASM_OP_VARUINT64; MI->wasm_data.uint64 = data; *param_size = len; return true; } // input | code : code pointer start from memoryimmediate // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size (sum of two params) // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_memoryimmediate(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { size_t tmp, len = 0; uint32_t data[2]; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 2; } data[0] = get_varuint32(code, code_len, &tmp); if (tmp == -1) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_VARUINT32; MI->flat_insn->detail->wasm.operands[0].size = tmp; MI->flat_insn->detail->wasm.operands[0].varuint32 = data[0]; } len = tmp; data[1] = get_varuint32(&code[len], code_len - len, &tmp); if (len == -1) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.operands[1].type = WASM_OP_VARUINT32; MI->flat_insn->detail->wasm.operands[1].size = tmp; MI->flat_insn->detail->wasm.operands[1].varuint32 = data[1]; } len += tmp; MI->wasm_data.size = len; MI->wasm_data.type = WASM_OP_IMM; MI->wasm_data.immediate[0] = data[0]; MI->wasm_data.immediate[1] = data[1]; *param_size = len; return true; } // input | code : code pointer start from uint32 // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_uint32(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { if (code_len < 4) { return false; } get_uint32(code, &(MI->wasm_data.uint32)); if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_UINT32; MI->flat_insn->detail->wasm.operands[0].size = 4; get_uint32(code, &(MI->flat_insn->detail->wasm.operands[0].uint32)); } MI->wasm_data.size = 4; MI->wasm_data.type = WASM_OP_UINT32; *param_size = 4; return true; } // input | code : code pointer start from uint64 // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_uint64(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { if (code_len < 8) { return false; } get_uint64(code, &(MI->wasm_data.uint64)); if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_UINT64; MI->flat_insn->detail->wasm.operands[0].size = 8; get_uint64(code, &(MI->flat_insn->detail->wasm.operands[0].uint64)); } MI->wasm_data.size = 8; MI->wasm_data.type = WASM_OP_UINT64; *param_size = 8; return true; } // input | code : code pointer start from brtable // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size (sum of all param) // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_brtable(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { uint32_t length, default_target; int tmp_len = 0, i; size_t var_len; // read length length = get_varuint32(code, code_len, &var_len); if (var_len == -1) { return false; } tmp_len += var_len; MI->wasm_data.brtable.length = length; if (length >= UINT32_MAX - tmp_len) { // integer overflow check return false; } if (code_len < tmp_len + length) { // safety check that we have minimum enough data to read return false; } // base address + 1 byte opcode + tmp_len for number of cases = start of targets MI->wasm_data.brtable.address = MI->address + 1 + tmp_len; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_BRTABLE; MI->flat_insn->detail->wasm.operands[0].brtable.length = MI->wasm_data.brtable.length; MI->flat_insn->detail->wasm.operands[0].brtable.address = MI->wasm_data.brtable.address; } // read data for(i = 0; i < length; i++){ if (code_len < tmp_len) { return false; } get_varuint32(code + tmp_len, code_len - tmp_len, &var_len); if (var_len == -1) { return false; } tmp_len += var_len; } // read default target default_target = get_varuint32(code + tmp_len, code_len - tmp_len, &var_len); if (var_len == -1) { return false; } MI->wasm_data.brtable.default_target = default_target; MI->wasm_data.type = WASM_OP_BRTABLE; *param_size = tmp_len + var_len; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.operands[0].size = *param_size; MI->flat_insn->detail->wasm.operands[0].brtable.default_target = MI->wasm_data.brtable.default_target; } return true; } // input | code : code pointer start from varint7 // | code_len : start from the code pointer to the end, how long is it // | param_size : pointer of the param size // | MI : Mcinst handler in this round of disasm // return | true/false if the function successfully finished static bool read_varint7(const uint8_t *code, size_t code_len, uint16_t *param_size, MCInst *MI) { size_t len = 0; MI->wasm_data.type = WASM_OP_INT7; MI->wasm_data.int7 = get_varint7(code, code_len, &len); if (len == -1) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->wasm.operands[0].type = WASM_OP_INT7; MI->flat_insn->detail->wasm.operands[0].size = 1; MI->flat_insn->detail->wasm.operands[0].int7 = MI->wasm_data.int7; } *param_size = len; return true; } bool WASM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *inst_info) { unsigned char opcode; uint16_t param_size; if (code_len == 0) return false; opcode = code[0]; if (opcodes[opcode] == -1) { // invalid opcode return false; } // valid opcode MI->address = address; MI->OpcodePub = MI->Opcode = opcode; if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, wasm)+sizeof(cs_wasm)); WASM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode); } // setup groups switch(opcode) { default: return false; case WASM_INS_I32_CONST: if (code_len == 1 || !read_varuint32(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_NUMBERIC; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_I64_CONST: if (code_len == 1 || !read_varuint64(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_NUMBERIC; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_F32_CONST: if (code_len == 1 || !read_uint32(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_NUMBERIC; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_F64_CONST: if (code_len == 1 || !read_uint64(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_NUMBERIC; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_I32_EQZ: case WASM_INS_I32_EQ: case WASM_INS_I32_NE: case WASM_INS_I32_LT_S: case WASM_INS_I32_LT_U: case WASM_INS_I32_GT_S: case WASM_INS_I32_GT_U: case WASM_INS_I32_LE_S: case WASM_INS_I32_LE_U: case WASM_INS_I32_GE_S: case WASM_INS_I32_GE_U: case WASM_INS_I64_EQZ: case WASM_INS_I64_EQ: case WASM_INS_I64_NE: case WASM_INS_I64_LT_S: case WASM_INS_I64_LT_U: case WASN_INS_I64_GT_S: case WASM_INS_I64_GT_U: case WASM_INS_I64_LE_S: case WASM_INS_I64_LE_U: case WASM_INS_I64_GE_S: case WASM_INS_I64_GE_U: case WASM_INS_F32_EQ: case WASM_INS_F32_NE: case WASM_INS_F32_LT: case WASM_INS_F32_GT: case WASM_INS_F32_LE: case WASM_INS_F32_GE: case WASM_INS_F64_EQ: case WASM_INS_F64_NE: case WASM_INS_F64_LT: case WASM_INS_F64_GT: case WASM_INS_F64_LE: case WASM_INS_F64_GE: case WASM_INS_I32_CLZ: case WASM_INS_I32_CTZ: case WASM_INS_I32_POPCNT: case WASM_INS_I32_ADD: case WASM_INS_I32_SUB: case WASM_INS_I32_MUL: case WASM_INS_I32_DIV_S: case WASM_INS_I32_DIV_U: case WASM_INS_I32_REM_S: case WASM_INS_I32_REM_U: case WASM_INS_I32_AND: case WASM_INS_I32_OR: case WASM_INS_I32_XOR: case WASM_INS_I32_SHL: case WASM_INS_I32_SHR_S: case WASM_INS_I32_SHR_U: case WASM_INS_I32_ROTL: case WASM_INS_I32_ROTR: case WASM_INS_I64_CLZ: case WASM_INS_I64_CTZ: case WASM_INS_I64_POPCNT: case WASM_INS_I64_ADD: case WASM_INS_I64_SUB: case WASM_INS_I64_MUL: case WASM_INS_I64_DIV_S: case WASM_INS_I64_DIV_U: case WASM_INS_I64_REM_S: case WASM_INS_I64_REM_U: case WASM_INS_I64_AND: case WASM_INS_I64_OR: case WASM_INS_I64_XOR: case WASM_INS_I64_SHL: case WASM_INS_I64_SHR_S: case WASM_INS_I64_SHR_U: case WASM_INS_I64_ROTL: case WASM_INS_I64_ROTR: case WASM_INS_F32_ABS: case WASM_INS_F32_NEG: case WASM_INS_F32_CEIL: case WASM_INS_F32_FLOOR: case WASM_INS_F32_TRUNC: case WASM_INS_F32_NEAREST: case WASM_INS_F32_SQRT: case WASM_INS_F32_ADD: case WASM_INS_F32_SUB: case WASM_INS_F32_MUL: case WASM_INS_F32_DIV: case WASM_INS_F32_MIN: case WASM_INS_F32_MAX: case WASM_INS_F32_COPYSIGN: case WASM_INS_F64_ABS: case WASM_INS_F64_NEG: case WASM_INS_F64_CEIL: case WASM_INS_F64_FLOOR: case WASM_INS_F64_TRUNC: case WASM_INS_F64_NEAREST: case WASM_INS_F64_SQRT: case WASM_INS_F64_ADD: case WASM_INS_F64_SUB: case WASM_INS_F64_MUL: case WASM_INS_F64_DIV: case WASM_INS_F64_MIN: case WASM_INS_F64_MAX: case WASM_INS_F64_COPYSIGN: case WASM_INS_I32_WARP_I64: case WASP_INS_I32_TRUNC_S_F32: case WASM_INS_I32_TRUNC_U_F32: case WASM_INS_I32_TRUNC_S_F64: case WASM_INS_I32_TRUNC_U_F64: case WASM_INS_I64_EXTEND_S_I32: case WASM_INS_I64_EXTEND_U_I32: case WASM_INS_I64_TRUNC_S_F32: case WASM_INS_I64_TRUNC_U_F32: case WASM_INS_I64_TRUNC_S_F64: case WASM_INS_I64_TRUNC_U_F64: case WASM_INS_F32_CONVERT_S_I32: case WASM_INS_F32_CONVERT_U_I32: case WASM_INS_F32_CONVERT_S_I64: case WASM_INS_F32_CONVERT_U_I64: case WASM_INS_F32_DEMOTE_F64: case WASM_INS_F64_CONVERT_S_I32: case WASM_INS_F64_CONVERT_U_I32: case WASM_INS_F64_CONVERT_S_I64: case WASM_INS_F64_CONVERT_U_I64: case WASM_INS_F64_PROMOTE_F32: case WASM_INS_I32_REINTERPRET_F32: case WASM_INS_I64_REINTERPRET_F64: case WASM_INS_F32_REINTERPRET_I32: case WASM_INS_F64_REINTERPRET_I64: MI->wasm_data.type = WASM_OP_NONE; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 0; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_NUMBERIC; MI->flat_insn->detail->groups_count++; } *size = 1; break; case WASM_INS_DROP: case WASM_INS_SELECT: MI->wasm_data.type = WASM_OP_NONE; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 0; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_PARAMETRIC; MI->flat_insn->detail->groups_count++; } *size = 1; break; case WASM_INS_GET_LOCAL: case WASM_INS_SET_LOCAL: case WASM_INS_TEE_LOCAL: case WASM_INS_GET_GLOBAL: case WASM_INS_SET_GLOBAL: if (code_len == 1 || !read_varuint32(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_VARIABLE; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_I32_LOAD: case WASM_INS_I64_LOAD: case WASM_INS_F32_LOAD: case WASM_INS_F64_LOAD: case WASM_INS_I32_LOAD8_S: case WASM_INS_I32_LOAD8_U: case WASM_INS_I32_LOAD16_S: case WASM_INS_I32_LOAD16_U: case WASM_INS_I64_LOAD8_S: case WASM_INS_I64_LOAD8_U: case WASM_INS_I64_LOAD16_S: case WASM_INS_I64_LOAD16_U: case WASM_INS_I64_LOAD32_S: case WASM_INS_I64_LOAD32_U: case WASM_INS_I32_STORE: case WASM_INS_I64_STORE: case WASM_INS_F32_STORE: case WASM_INS_F64_STORE: case WASM_INS_I32_STORE8: case WASM_INS_I32_STORE16: case WASM_INS_I64_STORE8: case WASM_INS_I64_STORE16: case WASM_INS_I64_STORE32: if (code_len == 1 || !read_memoryimmediate(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 2; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_MEMORY; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_CURRENT_MEMORY: case WASM_INS_GROW_MEMORY: MI->wasm_data.type = WASM_OP_NONE; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 0; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_MEMORY; MI->flat_insn->detail->groups_count++; } *size = 1; break; case WASM_INS_UNREACHABLE: case WASM_INS_NOP: case WASM_INS_ELSE: case WASM_INS_END: case WASM_INS_RETURN: MI->wasm_data.type = WASM_OP_NONE; if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 0; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_CONTROL; MI->flat_insn->detail->groups_count++; } *size = 1; break; case WASM_INS_BLOCK: case WASM_INS_LOOP: case WASM_INS_IF: if (code_len == 1 || !read_varint7(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_CONTROL; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_BR: case WASM_INS_BR_IF: case WASM_INS_CALL: case WASM_INS_CALL_INDIRECT: if (code_len == 1 || !read_varuint32(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_CONTROL; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; case WASM_INS_BR_TABLE: if (code_len == 1 || !read_brtable(&code[1], code_len - 1, ¶m_size, MI)) { return false; } if (MI->flat_insn->detail) { MI->flat_insn->detail->wasm.op_count = 1; MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = WASM_GRP_CONTROL; MI->flat_insn->detail->groups_count++; } *size = param_size + 1; break; } return true; } capstone-sys-0.15.0/capstone/arch/WASM/WASMDisassembler.h000064400000000000000000000004460072674642500211510ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #ifndef CS_WASMDISASSEMBLER_H #define CS_WASMDISASSEMBLER_H #include "../../MCInst.h" bool WASM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/WASM/WASMInstPrinter.c000064400000000000000000000021530072674642500210050ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #include "WASMInstPrinter.h" #include "WASMMapping.h" void WASM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) { SStream_concat(O, WASM_insn_name((csh)MI->csh, MI->Opcode)); switch (MI->wasm_data.type) { default: break; case WASM_OP_VARUINT32: SStream_concat(O, "\t0x%x", MI->wasm_data.varuint32); break; case WASM_OP_VARUINT64: SStream_concat(O, "\t0x%lx", MI->wasm_data.varuint64); break; case WASM_OP_UINT32: SStream_concat(O, "\t0x%2" PRIx32, MI->wasm_data.uint32); break; case WASM_OP_UINT64: SStream_concat(O, "\t0x%2" PRIx64, MI->wasm_data.uint64); break; case WASM_OP_IMM: SStream_concat(O, "\t0x%x, 0x%x", MI->wasm_data.immediate[0], MI->wasm_data.immediate[1]); break; case WASM_OP_INT7: SStream_concat(O, "\t%d", MI->wasm_data.int7); break; case WASM_OP_BRTABLE: SStream_concat(O, "\t0x%x, [", MI->wasm_data.brtable.length); SStream_concat(O, "0x%x", MI->wasm_data.brtable.address); SStream_concat(O, "], 0x%x", MI->wasm_data.brtable.default_target); break; } } capstone-sys-0.15.0/capstone/arch/WASM/WASMInstPrinter.h000064400000000000000000000005760072674642500210210ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #ifndef CS_WASMINSTPRINTER_H #define CS_WASMINSTPRINTER_H #include "capstone/capstone.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../cs_priv.h" struct SStream; void WASM_printInst(MCInst *MI, struct SStream *O, void *Info); void printOperand(MCInst *MI, unsigned OpNo, SStream *O); #endif capstone-sys-0.15.0/capstone/arch/WASM/WASMMapping.c000064400000000000000000000245070072674642500201260ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #ifdef CAPSTONE_HAS_WASM #include #include "../../cs_priv.h" #include "../../utils.h" #include "WASMMapping.h" // fill in details void WASM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { insn->id = id; } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[256] = { { WASM_INS_UNREACHABLE, "unreachable" }, { WASM_INS_NOP, "nop" }, { WASM_INS_BLOCK, "block" }, { WASM_INS_LOOP, "loop" }, { WASM_INS_IF, "if" }, { WASM_INS_ELSE, "else" }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_END, "end" }, { WASM_INS_BR, "br" }, { WASM_INS_BR_IF, "br_if" }, { WASM_INS_BR_TABLE, "br_table" }, { WASM_INS_RETURN, "return" }, { WASM_INS_CALL, "call" }, { WASM_INS_CALL_INDIRECT, "call_indirect" }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_DROP, "drop" }, { WASM_INS_SELECT, "select" }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_GET_LOCAL, "get_local" }, { WASM_INS_SET_LOCAL, "set_local" }, { WASM_INS_TEE_LOCAL, "tee_local" }, { WASM_INS_GET_GLOBAL, "get_global" }, { WASM_INS_SET_GLOBAL, "set_global" }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_I32_LOAD, "i32.load" }, { WASM_INS_I64_LOAD, "i64.load" }, { WASM_INS_F32_LOAD, "f32.load" }, { WASM_INS_F64_LOAD, "f64.load" }, { WASM_INS_I32_LOAD8_S, "i32.load8_s" }, { WASM_INS_I32_LOAD8_U, "i32.load8_u" }, { WASM_INS_I32_LOAD16_S, "i32.load16_s" }, { WASM_INS_I32_LOAD16_U, "i32.load16_u" }, { WASM_INS_I64_LOAD8_S, "i64.load8_s" }, { WASM_INS_I64_LOAD8_U, "i64.load8_u" }, { WASM_INS_I64_LOAD16_S, "i64.load16_s" }, { WASM_INS_I64_LOAD16_U, "i64.load16_u"}, { WASM_INS_I64_LOAD32_S, "i64.load32_s"}, { WASM_INS_I64_LOAD32_U, "i64.load32_u" }, { WASM_INS_I32_STORE, "i32.store" }, { WASM_INS_I64_STORE, "i64.store" }, { WASM_INS_F32_STORE, "f32.store" }, { WASM_INS_F64_STORE, "f64.store" }, { WASM_INS_I32_STORE8, "i32.store8" }, { WASM_INS_I32_STORE16, "i32.store16" }, { WASM_INS_I64_STORE8, "i64.store8" }, { WASM_INS_I64_STORE16, "i64.store16" }, { WASM_INS_I64_STORE32, "i64.store32" }, { WASM_INS_CURRENT_MEMORY, "current_memory" }, { WASM_INS_GROW_MEMORY, "grow_memory" }, { WASM_INS_I32_CONST, "i32.const" }, { WASM_INS_I64_CONST, "i64.const" }, { WASM_INS_F32_CONST, "f32.const" }, { WASM_INS_F64_CONST, "f64.const" }, { WASM_INS_I32_EQZ, "i32.eqz" }, { WASM_INS_I32_EQ, "i32.eq" }, { WASM_INS_I32_NE, "i32.ne" }, { WASM_INS_I32_LT_S, "i32.lt_s" }, { WASM_INS_I32_LT_U, "i32.lt_u" }, { WASM_INS_I32_GT_S, "i32.gt_s" }, { WASM_INS_I32_GT_U, "i32.gt_u" }, { WASM_INS_I32_LE_S, "i32.le_s" }, { WASM_INS_I32_LE_U, "i32.le_u" }, { WASM_INS_I32_GE_S, "i32.ge_s" }, { WASM_INS_I32_GE_U, "i32.ge_u" }, { WASM_INS_I64_EQZ, "i64.eqz" }, { WASM_INS_I64_EQ, "i64.eq" }, { WASM_INS_I64_NE, "i64.ne" }, { WASM_INS_I64_LT_S, "i64.lt_s" }, { WASM_INS_I64_LT_U, "i64.lt_u" }, { WASN_INS_I64_GT_S, "i64.gt_s" }, { WASM_INS_I64_GT_U, "i64.gt_u" }, { WASM_INS_I64_LE_S, "i64.le_s" }, { WASM_INS_I64_LE_U, "i64.le_u" }, { WASM_INS_I64_GE_S, "i64.ge_s" }, { WASM_INS_I64_GE_U, "i64.ge_u" }, { WASM_INS_F32_EQ, "f32.eq" }, { WASM_INS_F32_NE, "f32.ne" }, { WASM_INS_F32_LT, "f32.lt" }, { WASM_INS_F32_GT, "f32.gt" }, { WASM_INS_F32_LE, "f32.le" }, { WASM_INS_F32_GE, "f32.ge" }, { WASM_INS_F64_EQ, "f64.eq" }, { WASM_INS_F64_NE, "f64.ne" }, { WASM_INS_F64_LT, "f64.lt" }, { WASM_INS_F64_GT, "f64.gt" }, { WASM_INS_F64_LE, "f64.le" }, { WASM_INS_F64_GE, "f64.ge" }, { WASM_INS_I32_CLZ, "i32.clz" }, { WASM_INS_I32_CTZ, "i32.ctz" }, { WASM_INS_I32_POPCNT, "i32.popcnt" }, { WASM_INS_I32_ADD, "i32.add" }, { WASM_INS_I32_SUB, "i32.sub" }, { WASM_INS_I32_MUL, "i32.mul" }, { WASM_INS_I32_DIV_S, "i32.div_s" }, { WASM_INS_I32_DIV_U, "i32.div_u" }, { WASM_INS_I32_REM_S, "i32.rem_s" }, { WASM_INS_I32_REM_U, "i32.rem_u" }, { WASM_INS_I32_AND, "i32.and" }, { WASM_INS_I32_OR, "i32.or" }, { WASM_INS_I32_XOR, "i32.xor" }, { WASM_INS_I32_SHL, "i32.shl" }, { WASM_INS_I32_SHR_S, "i32.shr_s" }, { WASM_INS_I32_SHR_U, "i32.shr_u" }, { WASM_INS_I32_ROTL, "i32.rotl" }, { WASM_INS_I32_ROTR, "i32.rotr" }, { WASM_INS_I64_CLZ, "i64.clz" }, { WASM_INS_I64_CTZ, "i64.ctz" }, { WASM_INS_I64_POPCNT, "i64.popcnt" }, { WASM_INS_I64_ADD, "i64.add" }, { WASM_INS_I64_SUB, "i64.sub" }, { WASM_INS_I64_MUL, "i64.mul" }, { WASM_INS_I64_DIV_S, "i64.div_s" }, { WASM_INS_I64_DIV_U, "i64.div_u" }, { WASM_INS_I64_REM_S, "i64.rem_s" }, { WASM_INS_I64_REM_U, "i64.rem_u" }, { WASM_INS_I64_AND, "i64.and" }, { WASM_INS_I64_OR, "i64.or" }, { WASM_INS_I64_XOR, "i64.xor" }, { WASM_INS_I64_SHL, "i64.shl" }, { WASM_INS_I64_SHR_S, "i64.shr_s" }, { WASM_INS_I64_SHR_U, "i64.shr_u" }, { WASM_INS_I64_ROTL, "i64.rotl" }, { WASM_INS_I64_ROTR, "i64.rotr" }, { WASM_INS_F32_ABS, "f32.abs" }, { WASM_INS_F32_NEG, "f32.neg" }, { WASM_INS_F32_CEIL, "f32.ceil" }, { WASM_INS_F32_FLOOR, "f32.floor" }, { WASM_INS_F32_TRUNC, "f32.trunc" }, { WASM_INS_F32_NEAREST, "f32.nearest" }, { WASM_INS_F32_SQRT, "f32.sqrt" }, { WASM_INS_F32_ADD, "f32.add" }, { WASM_INS_F32_SUB, "f32.sub" }, { WASM_INS_F32_MUL, "f32.mul" }, { WASM_INS_F32_DIV, "f32.div" }, { WASM_INS_F32_MIN, "f32.min" }, { WASM_INS_F32_MAX, "f32.max" }, { WASM_INS_F32_COPYSIGN, "f32.copysign" }, { WASM_INS_F64_ABS, "f64.abs" }, { WASM_INS_F64_NEG, "f64.neg" }, { WASM_INS_F64_CEIL, "f64.ceil" }, { WASM_INS_F64_FLOOR, "f64.floor" }, { WASM_INS_F64_TRUNC, "f64.trunc" }, { WASM_INS_F64_NEAREST, "f64.nearest" }, { WASM_INS_F64_SQRT, "f64.sqrt" }, { WASM_INS_F64_ADD, "f64.add" }, { WASM_INS_F64_SUB, "f64.sub" }, { WASM_INS_F64_MUL, "f64.mul" }, { WASM_INS_F64_DIV, "f64.div" }, { WASM_INS_F64_MIN, "f64.min" }, { WASM_INS_F64_MAX, "f64.max" }, { WASM_INS_F64_COPYSIGN, "f64.copysign" }, { WASM_INS_I32_WARP_I64, "i32.warp/i64" }, { WASP_INS_I32_TRUNC_S_F32, "i32.trunc_s/f32" }, { WASM_INS_I32_TRUNC_U_F32, "i32.trunc_u/f32" }, { WASM_INS_I32_TRUNC_S_F64, "i32/trunc_s/f64" }, { WASM_INS_I32_TRUNC_U_F64, "i32/trunc_u/f64" }, { WASM_INS_I64_EXTEND_S_I32, "i64/extend_s/i32" }, { WASM_INS_I64_EXTEND_U_I32, "i64/extend_u/i32" }, { WASM_INS_I64_TRUNC_S_F32, "i64.trunc_s/f32" }, { WASM_INS_I64_TRUNC_U_F32, "i64.trunc_u/f32" }, { WASM_INS_I64_TRUNC_S_F64, "f64.trunc_s/f64" }, { WASM_INS_I64_TRUNC_U_F64, "f64.trunc_u/f64" }, { WASM_INS_F32_CONVERT_S_I32, "f32.convert_s/i32" }, { WASM_INS_F32_CONVERT_U_I32, "f32.convert_u/i32" }, { WASM_INS_F32_CONVERT_S_I64, "f32.convert_s/i64" }, { WASM_INS_F32_CONVERT_U_I64, "f32.convert_u/i64" }, { WASM_INS_F32_DEMOTE_F64, "f32.demote/f64" }, { WASM_INS_F64_CONVERT_S_I32, "f64.convert_s/i32" }, { WASM_INS_F64_CONVERT_U_I32, "f64.convert_u/i32" }, { WASM_INS_F64_CONVERT_S_I64, "f64.convert_s/i64" }, { WASM_INS_F64_CONVERT_U_I64, "f64.convert_u/i64" }, { WASM_INS_F64_PROMOTE_F32, "f64.promote/f32" }, { WASM_INS_I32_REINTERPRET_F32, "i32.reinterpret/f32" }, { WASM_INS_I64_REINTERPRET_F64, "i64.reinterpret/f64" }, { WASM_INS_F32_REINTERPRET_I32, "f32.reinterpret/i32" }, { WASM_INS_F64_REINTERPRET_I64, "f64.reinterpret/i64" }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, { WASM_INS_INVALID, NULL }, }; #endif const char *WASM_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= ARR_SIZE(insn_name_maps)) return NULL; else return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { WASM_GRP_INVALID, NULL }, // special groups { WASM_GRP_NUMBERIC, "numberic"}, { WASM_GRP_PARAMETRIC, "parametric"}, { WASM_GRP_VARIABLE, "variable"}, { WASM_GRP_MEMORY, "memory"}, { WASM_GRP_CONTROL, "control"}, }; #endif #ifndef CAPSTONE_DIET static const name_map kind_name_maps[] = { { WASM_OP_INVALID, "Invalid" }, { WASM_OP_NONE, "None" }, { WASM_OP_INT7, "uint7" }, { WASM_OP_VARUINT32, "varuint32" }, { WASM_OP_VARUINT64, "varuint64" }, { WASM_OP_UINT32, "uint32" }, { WASM_OP_UINT64, "uint64" }, }; #endif const char *WASM_kind_name(unsigned int id){ #ifndef CAPSTONE_DIET return id2name(kind_name_maps, ARR_SIZE(kind_name_maps), id); #else return NULL; #endif } const char *WASM_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } #endif capstone-sys-0.15.0/capstone/arch/WASM/WASMMapping.h000064400000000000000000000005040072674642500201220ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #include void WASM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *WASM_insn_name(csh handle, unsigned int id); const char *WASM_group_name(csh handle, unsigned int id); const char *WASM_kind_name(unsigned int id); capstone-sys-0.15.0/capstone/arch/WASM/WASMModule.c000064400000000000000000000012270072674642500177520ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #ifdef CAPSTONE_HAS_WASM #include "../../cs_priv.h" #include "WASMDisassembler.h" #include "WASMInstPrinter.h" #include "WASMMapping.h" #include "WASMModule.h" cs_err WASM_global_init(cs_struct *ud) { // verify if requested mode is valid if (ud->mode) return CS_ERR_MODE; ud->printer = WASM_printInst; ud->printer_info = NULL; ud->insn_id = WASM_get_insn_id; ud->insn_name = WASM_insn_name; ud->group_name = WASM_group_name; ud->disasm = WASM_getInstruction; return CS_ERR_OK; } cs_err WASM_option(cs_struct *handle, cs_opt_type type, size_t value) { return CS_ERR_OPTION; } #endif capstone-sys-0.15.0/capstone/arch/WASM/WASMModule.h000064400000000000000000000004030072674642500177520ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike, xwings 2019 */ #ifndef CS_WASM_MODULE_H #define CS_WASM_MODULE_H #include "../../utils.h" cs_err WASM_global_init(cs_struct *ud); cs_err WASM_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/X86/X86ATTInstPrinter.c000064400000000000000000000672320072674642500210230ustar 00000000000000//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file includes code for rendering MCInst instances as AT&T-style // assembly. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ // this code is only relevant when DIET mode is disable #if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:4996) // disable MSVC's warning on strncpy() #pragma warning(disable:28719) // disable MSVC's warning on strncpy() #endif #if !defined(CAPSTONE_HAS_OSXKERNEL) #include #endif #include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include #else #include #include #endif #include #include "../../utils.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "X86Mapping.h" #include "X86BaseInfo.h" #include "X86InstPrinterCommon.h" #define GET_INSTRINFO_ENUM #ifdef CAPSTONE_X86_REDUCE #include "X86GenInstrInfo_reduce.inc" #else #include "X86GenInstrInfo.inc" #endif #define GET_REGINFO_ENUM #include "X86GenRegisterInfo.inc" static void printMemReference(MCInst *MI, unsigned Op, SStream *O); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (!status) // done, create the next operand slot MI->flat_insn->detail->x86.op_count++; } static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) { switch(MI->csh->mode) { case CS_MODE_16: switch(MI->flat_insn->id) { default: MI->x86opsize = 2; break; case X86_INS_LJMP: case X86_INS_LCALL: MI->x86opsize = 4; break; case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: MI->x86opsize = 6; break; } break; case CS_MODE_32: switch(MI->flat_insn->id) { default: MI->x86opsize = 4; break; case X86_INS_LJMP: case X86_INS_JMP: case X86_INS_LCALL: case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: MI->x86opsize = 6; break; } break; case CS_MODE_64: switch(MI->flat_insn->id) { default: MI->x86opsize = 8; break; case X86_INS_LJMP: case X86_INS_LCALL: case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: MI->x86opsize = 10; break; } break; default: // never reach break; } printMemReference(MI, OpNo, O); } static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 1; printMemReference(MI, OpNo, O); } static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 2; printMemReference(MI, OpNo, O); } static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 4; printMemReference(MI, OpNo, O); } static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 8; printMemReference(MI, OpNo, O); } static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 16; printMemReference(MI, OpNo, O); } static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 64; printMemReference(MI, OpNo, O); } #ifndef CAPSTONE_X86_REDUCE static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 32; printMemReference(MI, OpNo, O); } static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) { switch(MCInst_getOpcode(MI)) { default: MI->x86opsize = 4; break; case X86_FSTENVm: case X86_FLDENVm: // TODO: fix this in tablegen instead switch(MI->csh->mode) { default: // never reach break; case CS_MODE_16: MI->x86opsize = 14; break; case CS_MODE_32: case CS_MODE_64: MI->x86opsize = 28; break; } break; } printMemReference(MI, OpNo, O); } static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 8; printMemReference(MI, OpNo, O); } static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 10; printMemReference(MI, OpNo, O); } static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 16; printMemReference(MI, OpNo, O); } static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 32; printMemReference(MI, OpNo, O); } static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 64; printMemReference(MI, OpNo, O); } #endif static void printRegName(SStream *OS, unsigned RegNo); // local printOperand, without updating public operands static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { printRegName(O, MCOperand_getReg(Op)); } else if (MCOperand_isImm(Op)) { uint8_t encsize; uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); // Print X86 immediates as signed values. int64_t imm = MCOperand_getImm(Op); if (imm < 0) { if (MI->csh->imm_unsigned) { if (opsize) { switch(opsize) { default: break; case 1: imm &= 0xff; break; case 2: imm &= 0xffff; break; case 4: imm &= 0xffffffff; break; } } SStream_concat(O, "$0x%"PRIx64, imm); } else { if (imm < -HEX_THRESHOLD) SStream_concat(O, "$-0x%"PRIx64, -imm); else SStream_concat(O, "$-%"PRIu64, -imm); } } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "$0x%"PRIx64, imm); else SStream_concat(O, "$%"PRIu64, imm); } } } // convert Intel access info to AT&T access info static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) { uint8_t count, i; const uint8_t *arr = X86_get_op_access(h, id, eflags); if (!arr) { access[0] = 0; return; } // find the non-zero last entry for(count = 0; arr[count]; count++); if (count == 0) return; // copy in reverse order this access array from Intel syntax -> AT&T syntax count--; for(i = 0; i <= count; i++) { if (arr[count - i] != CS_AC_IGNORE) access[i] = arr[count - i]; else access[i] = 0; } } static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) { MCOperand *SegReg; int reg; if (MI->csh->detail) { uint8_t access[6]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; } SegReg = MCInst_getOperand(MI, Op+1); reg = MCOperand_getReg(SegReg); // If this has a segment register, print it. if (reg) { _printOperand(MI, Op + 1, O); SStream_concat0(O, ":"); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); } } SStream_concat0(O, "("); set_mem_access(MI, true); printOperand(MI, Op, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) { if (MI->csh->detail) { uint8_t access[6]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; } // DI accesses are always ES-based on non-64bit mode if (MI->csh->mode != CS_MODE_64) { SStream_concat0(O, "%es:("); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; } } else SStream_concat0(O, "("); set_mem_access(MI, true); printOperand(MI, Op, O); SStream_concat0(O, ")"); set_mem_access(MI, false); } static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 1; printSrcIdx(MI, OpNo, O); } static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 2; printSrcIdx(MI, OpNo, O); } static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 4; printSrcIdx(MI, OpNo, O); } static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 8; printSrcIdx(MI, OpNo, O); } static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 1; printDstIdx(MI, OpNo, O); } static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 2; printDstIdx(MI, OpNo, O); } static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 4; printDstIdx(MI, OpNo, O); } static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 8; printDstIdx(MI, OpNo, O); } static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) { MCOperand *DispSpec = MCInst_getOperand(MI, Op); MCOperand *SegReg = MCInst_getOperand(MI, Op+1); int reg; if (MI->csh->detail) { uint8_t access[6]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; } // If this has a segment register, print it. reg = MCOperand_getReg(SegReg); if (reg) { _printOperand(MI, Op + 1, O); SStream_concat0(O, ":"); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); } } if (MCOperand_isImm(DispSpec)) { int64_t imm = MCOperand_getImm(DispSpec); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; if (imm < 0) { SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); else SStream_concat(O, "%"PRIu64, imm); } } if (MI->csh->detail) MI->flat_insn->detail->x86.op_count++; } static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) { uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff; if (val > HEX_THRESHOLD) SStream_concat(O, "$0x%x", val); else SStream_concat(O, "$%u", val); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1; MI->flat_insn->detail->x86.op_count++; } } static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 1; printMemOffset(MI, OpNo, O); } static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 2; printMemOffset(MI, OpNo, O); } static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 4; printMemOffset(MI, OpNo, O); } static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 8; printMemOffset(MI, OpNo, O); } /// printPCRelImm - This is used to print an immediate value that ends up /// being encoded as a pc-relative value (e.g. for jumps and calls). These /// print slightly differently than normal immediates. For example, a $ is not /// emitted. static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; // truncat imm for non-64bit if (MI->csh->mode != CS_MODE_64) { imm = imm & 0xffffffff; } if (imm < 0) { SStream_concat(O, "0x%"PRIx64, imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); else SStream_concat(O, "%"PRIu64, imm); } if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; MI->has_imm = true; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; MI->flat_insn->detail->x86.op_count++; } } } static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { unsigned int reg = MCOperand_getReg(Op); printRegName(O, reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); } else { uint8_t access[6]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)]; get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; MI->flat_insn->detail->x86.op_count++; } } } else if (MCOperand_isImm(Op)) { // Print X86 immediates as signed values. uint8_t encsize; int64_t imm = MCOperand_getImm(Op); uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); if (opsize == 1) // print 1 byte immediate in positive form imm = imm & 0xff; switch(MI->flat_insn->id) { default: if (imm >= 0) { if (imm > HEX_THRESHOLD) SStream_concat(O, "$0x%"PRIx64, imm); else SStream_concat(O, "$%"PRIu64, imm); } else { if (MI->csh->imm_unsigned) { if (opsize) { switch(opsize) { default: break; case 1: imm &= 0xff; break; case 2: imm &= 0xffff; break; case 4: imm &= 0xffffffff; break; } } SStream_concat(O, "$0x%"PRIx64, imm); } else { if (imm == 0x8000000000000000LL) // imm == -imm SStream_concat0(O, "$0x8000000000000000"); else if (imm < -HEX_THRESHOLD) SStream_concat(O, "$-0x%"PRIx64, -imm); else SStream_concat(O, "$-%"PRIu64, -imm); } } break; case X86_INS_MOVABS: case X86_INS_MOV: // do not print number in negative form if (imm > HEX_THRESHOLD) SStream_concat(O, "$0x%"PRIx64, imm); else SStream_concat(O, "$%"PRIu64, imm); break; case X86_INS_IN: case X86_INS_OUT: case X86_INS_INT: // do not print number in negative form imm = imm & 0xff; if (imm >= 0 && imm <= HEX_THRESHOLD) SStream_concat(O, "$%u", imm); else { SStream_concat(O, "$0x%x", imm); } break; case X86_INS_LCALL: case X86_INS_LJMP: case X86_INS_JMP: // always print address in positive form if (OpNo == 1) { // selector is ptr16 imm = imm & 0xffff; opsize = 2; } else opsize = 4; SStream_concat(O, "$0x%"PRIx64, imm); break; case X86_INS_AND: case X86_INS_OR: case X86_INS_XOR: // do not print number in negative form if (imm >= 0 && imm <= HEX_THRESHOLD) SStream_concat(O, "$%u", imm); else { imm = arch_masks[opsize? opsize : MI->imm_size] & imm; SStream_concat(O, "$0x%"PRIx64, imm); } break; case X86_INS_RET: case X86_INS_RETF: // RET imm16 if (imm >= 0 && imm <= HEX_THRESHOLD) SStream_concat(O, "$%u", imm); else { imm = 0xffff & imm; SStream_concat(O, "$0x%x", imm); } break; } if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; } else { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; MI->has_imm = true; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; if (opsize > 0) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; MI->flat_insn->detail->x86.encoding.imm_size = encsize; } else if (MI->op1_size > 0) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size; else MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; MI->flat_insn->detail->x86.op_count++; } } } } static void printMemReference(MCInst *MI, unsigned Op, SStream *O) { MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); uint64_t ScaleVal; int segreg; int64_t DispVal = 1; if (MI->csh->detail) { uint8_t access[6]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg)); if (MCOperand_getReg(IndexReg) != X86_EIZ) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg)); } MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; } // If this has a segment register, print it. segreg = MCOperand_getReg(SegReg); if (segreg) { _printOperand(MI, Op + X86_AddrSegmentReg, O); SStream_concat0(O, ":"); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(segreg); } } if (MCOperand_isImm(DispSpec)) { DispVal = MCOperand_getImm(DispSpec); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; if (DispVal) { if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { printInt64(O, DispVal); } else { // only immediate as address of memory if (DispVal < 0) { SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); } else { if (DispVal > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, DispVal); else SStream_concat(O, "%"PRIu64, DispVal); } } } } if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { SStream_concat0(O, "("); if (MCOperand_getReg(BaseReg)) _printOperand(MI, Op + X86_AddrBaseReg, O); if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) { SStream_concat0(O, ", "); _printOperand(MI, Op + X86_AddrIndexReg, O); ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; if (ScaleVal != 1) { SStream_concat(O, ", %u", ScaleVal); } } SStream_concat0(O, ")"); } else { if (!DispVal) SStream_concat0(O, "0"); } if (MI->csh->detail) MI->flat_insn->detail->x86.op_count++; } static void printanymem(MCInst *MI, unsigned OpNo, SStream *O) { switch(MI->Opcode) { default: break; case X86_LEA16r: MI->x86opsize = 2; break; case X86_LEA32r: case X86_LEA64_32r: MI->x86opsize = 4; break; case X86_LEA64r: MI->x86opsize = 8; break; case X86_BNDCL32rm: case X86_BNDCN32rm: case X86_BNDCU32rm: case X86_BNDSTXmr: case X86_BNDLDXrm: case X86_BNDCL64rm: case X86_BNDCN64rm: case X86_BNDCU64rm: MI->x86opsize = 16; break; } printMemReference(MI, OpNo, O); } #include "X86InstPrinter.h" // Include the auto-generated portion of the assembly writer. #ifdef CAPSTONE_X86_REDUCE #include "X86GenAsmWriter_reduce.inc" #else #include "X86GenAsmWriter.inc" #endif #include "X86GenRegisterName.inc" static void printRegName(SStream *OS, unsigned RegNo) { SStream_concat(OS, "%%%s", getRegisterName(RegNo)); } void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) { x86_reg reg, reg2; enum cs_ac_type access1, access2; int i; // perhaps this instruction does not need printer if (MI->assembly[0]) { strncpy(OS->buffer, MI->assembly, sizeof(OS->buffer)); return; } // Output CALLpcrel32 as "callq" in 64-bit mode. // In Intel annotation it's always emitted as "call". // // TODO: Probably this hack should be redesigned via InstAlias in // InstrInfo.td as soon as Requires clause is supported properly // for InstAlias. if (MI->csh->mode == CS_MODE_64 && MCInst_getOpcode(MI) == X86_CALLpcrel32) { SStream_concat0(OS, "callq\t"); MCInst_setOpcodePub(MI, X86_INS_CALL); printPCRelImm(MI, 0, OS); return; } X86_lockrep(MI, OS); printInstruction(MI, OS); if (MI->has_imm) { // if op_count > 1, then this operand's size is taken from the destination op if (MI->flat_insn->detail->x86.op_count > 1) { if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP && MI->flat_insn->id != X86_INS_JMP) { for (i = 0; i < MI->flat_insn->detail->x86.op_count; i++) { if (MI->flat_insn->detail->x86.operands[i].type == X86_OP_IMM) MI->flat_insn->detail->x86.operands[i].size = MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].size; } } } else MI->flat_insn->detail->x86.operands[0].size = MI->imm_size; } if (MI->csh->detail) { uint8_t access[6] = {0}; // some instructions need to supply immediate 1 in the first op switch(MCInst_getOpcode(MI)) { default: break; case X86_SHL8r1: case X86_SHL16r1: case X86_SHL32r1: case X86_SHL64r1: case X86_SAL8r1: case X86_SAL16r1: case X86_SAL32r1: case X86_SAL64r1: case X86_SHR8r1: case X86_SHR16r1: case X86_SHR32r1: case X86_SHR64r1: case X86_SAR8r1: case X86_SAR16r1: case X86_SAR32r1: case X86_SAR64r1: case X86_RCL8r1: case X86_RCL16r1: case X86_RCL32r1: case X86_RCL64r1: case X86_RCR8r1: case X86_RCR16r1: case X86_RCR32r1: case X86_RCR64r1: case X86_ROL8r1: case X86_ROL16r1: case X86_ROL32r1: case X86_ROL64r1: case X86_ROR8r1: case X86_ROR16r1: case X86_ROR32r1: case X86_ROR64r1: case X86_SHL8m1: case X86_SHL16m1: case X86_SHL32m1: case X86_SHL64m1: case X86_SAL8m1: case X86_SAL16m1: case X86_SAL32m1: case X86_SAL64m1: case X86_SHR8m1: case X86_SHR16m1: case X86_SHR32m1: case X86_SHR64m1: case X86_SAR8m1: case X86_SAR16m1: case X86_SAR32m1: case X86_SAR64m1: case X86_RCL8m1: case X86_RCL16m1: case X86_RCL32m1: case X86_RCL64m1: case X86_RCR8m1: case X86_RCR16m1: case X86_RCR32m1: case X86_RCR64m1: case X86_ROL8m1: case X86_ROL16m1: case X86_ROL32m1: case X86_ROL64m1: case X86_ROR8m1: case X86_ROR16m1: case X86_ROR32m1: case X86_ROR64m1: // shift all the ops right to leave 1st slot for this new register op memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); MI->flat_insn->detail->x86.operands[0].type = X86_OP_IMM; MI->flat_insn->detail->x86.operands[0].imm = 1; MI->flat_insn->detail->x86.operands[0].size = 1; MI->flat_insn->detail->x86.op_count++; } // special instruction needs to supply register op // first op can be embedded in the asm by llvm. // so we have to add the missing register as the first operand //printf(">>> opcode = %u\n", MCInst_getOpcode(MI)); reg = X86_insn_reg_att(MCInst_getOpcode(MI), &access1); if (reg) { // shift all the ops right to leave 1st slot for this new register op memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[0].reg = reg; MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; MI->flat_insn->detail->x86.operands[0].access = access1; MI->flat_insn->detail->x86.op_count++; } else { if (X86_insn_reg_att2(MCInst_getOpcode(MI), ®, &access1, ®2, &access2)) { MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[0].reg = reg; MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; MI->flat_insn->detail->x86.operands[0].access = access1; MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[1].reg = reg2; MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; MI->flat_insn->detail->x86.operands[0].access = access2; MI->flat_insn->detail->x86.op_count = 2; } } #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[0].access = access[0]; MI->flat_insn->detail->x86.operands[1].access = access[1]; #endif } } #endif capstone-sys-0.15.0/capstone/arch/X86/X86BaseInfo.h000064400000000000000000000027630072674642500176620ustar 00000000000000//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file contains small standalone helper functions and enum definitions for // the X86 target useful for the compiler back-end and the MC libraries. // As such, it deliberately does not include references to LLVM core // code gen types, passes, etc.. // //===----------------------------------------------------------------------===// #ifndef CS_X86_BASEINFO_H #define CS_X86_BASEINFO_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ // Enums for memory operand decoding. Each memory operand is represented with // a 5 operand sequence in the form: // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] // These enums help decode this. enum { X86_AddrBaseReg = 0, X86_AddrScaleAmt = 1, X86_AddrIndexReg = 2, X86_AddrDisp = 3, /// AddrSegmentReg - The operand # of the segment in the memory operand. X86_AddrSegmentReg = 4, /// AddrNumOperands - Total number of operands in a memory reference. X86_AddrNumOperands = 5 }; enum IPREFIXES { X86_IP_NO_PREFIX = 0, X86_IP_HAS_OP_SIZE = 1, X86_IP_HAS_AD_SIZE = 2, X86_IP_HAS_REPEAT_NE = 4, X86_IP_HAS_REPEAT = 8, X86_IP_HAS_LOCK = 16, X86_IP_HAS_NOTRACK = 64 }; #endif capstone-sys-0.15.0/capstone/arch/X86/X86Disassembler.c000064400000000000000000001140450072674642500206010ustar 00000000000000//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file is part of the X86 Disassembler. // It contains code to translate the data produced by the decoder into // MCInsts. // // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and // 64-bit X86 instruction sets. The main decode sequence for an assembly // instruction in this disassembler is: // // 1. Read the prefix bytes and determine the attributes of the instruction. // These attributes, recorded in enum attributeBits // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM // provides a mapping from bitmasks to contexts, which are represented by // enum InstructionContext (ibid.). // // 2. Read the opcode, and determine what kind of opcode it is. The // disassembler distinguishes four kinds of opcodes, which are enumerated in // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. // // 3. Depending on the opcode type, look in one of four ClassDecision structures // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get // a ModRMDecision (ibid.). // // 4. Some instructions, such as escape opcodes or extended opcodes, or even // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the // ModR/M byte to complete decode. The ModRMDecision's type is an entry from // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the // ModR/M byte is required and how to interpret it. // // 5. After resolving the ModRMDecision, the disassembler has a unique ID // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and // meanings of its operands. // // 6. For each operand, its encoding is an entry from OperandEncoding // (X86DisassemblerDecoderCommon.h) and its type is an entry from // OperandType (ibid.). The encoding indicates how to read it from the // instruction; the type indicates how to interpret the value once it has // been read. For example, a register operand could be stored in the R/M // field of the ModR/M byte, the REG field of the ModR/M byte, or added to // the main opcode. This is orthogonal from its meaning (an GPR or an XMM // register, for instance). Given this information, the operands can be // extracted and interpreted. // // 7. As the last step, the disassembler translates the instruction information // and operands into a format understandable by the client - in this case, an // MCInst for use by the MC infrastructure. // // The disassembler is broken broadly into two parts: the table emitter that // emits the instruction decode tables discussed above during compilation, and // the disassembler itself. The table emitter is documented in more detail in // utils/TableGen/X86DisassemblerEmitter.h. // // X86Disassembler.cpp contains the code responsible for step 7, and for // invoking the decoder to execute steps 1-6. // X86DisassemblerDecoderCommon.h contains the definitions needed by both the // table emitter and the disassembler. // X86DisassemblerDecoder.h contains the public interface of the decoder, // factored out into C for possible use by other projects. // X86DisassemblerDecoder.c contains the source code of the decoder, which is // responsible for steps 1-6. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_X86 #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:4996) // disable MSVC's warning on strncpy() #pragma warning(disable:28719) // disable MSVC's warning on strncpy() #endif #include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #endif #include #include "../../cs_priv.h" #include "X86BaseInfo.h" #include "X86Disassembler.h" #include "X86DisassemblerDecoderCommon.h" #include "X86DisassemblerDecoder.h" #include "../../MCInst.h" #include "../../utils.h" #include "X86Mapping.h" #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "X86GenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #ifdef CAPSTONE_X86_REDUCE #include "X86GenInstrInfo_reduce.inc" #else #include "X86GenInstrInfo.inc" #endif // Fill-ins to make the compiler happy. These constants are never actually // assigned; they are just filler to make an automatically-generated switch // statement work. enum { X86_BX_SI = 500, X86_BX_DI = 501, X86_BP_SI = 502, X86_BP_DI = 503, X86_sib = 504, X86_sib64 = 505 }; // // Private code that translates from struct InternalInstructions to MCInsts. // /// translateRegister - Translates an internal register to the appropriate LLVM /// register, and appends it as an operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param reg - The Reg to append. static void translateRegister(MCInst *mcInst, Reg reg) { #define ENTRY(x) X86_##x, static const uint16_t llvmRegnums[] = { ALL_REGS 0 }; #undef ENTRY uint16_t llvmRegnum = llvmRegnums[reg]; MCOperand_CreateReg0(mcInst, llvmRegnum); } static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { 0, // SEG_OVERRIDE_NONE X86_CS, X86_SS, X86_DS, X86_ES, X86_FS, X86_GS }; /// translateSrcIndex - Appends a source index operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param insn - The internal instruction. static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn) { unsigned baseRegNo; if (insn->mode == MODE_64BIT) baseRegNo = insn->hasAdSize ? X86_ESI : X86_RSI; else if (insn->mode == MODE_32BIT) baseRegNo = insn->hasAdSize ? X86_SI : X86_ESI; else { // assert(insn->mode == MODE_16BIT); baseRegNo = insn->hasAdSize ? X86_ESI : X86_SI; } MCOperand_CreateReg0(mcInst, baseRegNo); MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); return false; } /// translateDstIndex - Appends a destination index operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param insn - The internal instruction. static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn) { unsigned baseRegNo; if (insn->mode == MODE_64BIT) baseRegNo = insn->hasAdSize ? X86_EDI : X86_RDI; else if (insn->mode == MODE_32BIT) baseRegNo = insn->hasAdSize ? X86_DI : X86_EDI; else { // assert(insn->mode == MODE_16BIT); baseRegNo = insn->hasAdSize ? X86_EDI : X86_DI; } MCOperand_CreateReg0(mcInst, baseRegNo); return false; } /// translateImmediate - Appends an immediate operand to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param immediate - The immediate value to append. /// @param operand - The operand, as stored in the descriptor table. /// @param insn - The internal instruction. static void translateImmediate(MCInst *mcInst, uint64_t immediate, const OperandSpecifier *operand, InternalInstruction *insn) { OperandType type; type = (OperandType)operand->type; if (type == TYPE_REL) { //isBranch = true; //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize; switch (operand->encoding) { default: break; case ENCODING_Iv: switch (insn->displacementSize) { default: break; case 1: if(immediate & 0x80) immediate |= ~(0xffull); break; case 2: if(immediate & 0x8000) immediate |= ~(0xffffull); break; case 4: if(immediate & 0x80000000) immediate |= ~(0xffffffffull); break; case 8: break; } break; case ENCODING_IB: if (immediate & 0x80) immediate |= ~(0xffull); break; case ENCODING_IW: if (immediate & 0x8000) immediate |= ~(0xffffull); break; case ENCODING_ID: if (immediate & 0x80000000) immediate |= ~(0xffffffffull); break; } } // By default sign-extend all X86 immediates based on their encoding. else if (type == TYPE_IMM) { switch (operand->encoding) { default: break; case ENCODING_IB: if(immediate & 0x80) immediate |= ~(0xffull); break; case ENCODING_IW: if(immediate & 0x8000) immediate |= ~(0xffffull); break; case ENCODING_ID: if(immediate & 0x80000000) immediate |= ~(0xffffffffull); break; case ENCODING_IO: break; } } else if (type == TYPE_IMM3) { #ifndef CAPSTONE_X86_REDUCE // Check for immediates that printSSECC can't handle. if (immediate >= 8) { unsigned NewOpc = 0; switch (MCInst_getOpcode(mcInst)) { default: break; // never reach case X86_CMPPDrmi: NewOpc = X86_CMPPDrmi_alt; break; case X86_CMPPDrri: NewOpc = X86_CMPPDrri_alt; break; case X86_CMPPSrmi: NewOpc = X86_CMPPSrmi_alt; break; case X86_CMPPSrri: NewOpc = X86_CMPPSrri_alt; break; case X86_CMPSDrm: NewOpc = X86_CMPSDrm_alt; break; case X86_CMPSDrr: NewOpc = X86_CMPSDrr_alt; break; case X86_CMPSSrm: NewOpc = X86_CMPSSrm_alt; break; case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; case X86_VPCOMBri: NewOpc = X86_VPCOMBri_alt; break; case X86_VPCOMBmi: NewOpc = X86_VPCOMBmi_alt; break; case X86_VPCOMWri: NewOpc = X86_VPCOMWri_alt; break; case X86_VPCOMWmi: NewOpc = X86_VPCOMWmi_alt; break; case X86_VPCOMDri: NewOpc = X86_VPCOMDri_alt; break; case X86_VPCOMDmi: NewOpc = X86_VPCOMDmi_alt; break; case X86_VPCOMQri: NewOpc = X86_VPCOMQri_alt; break; case X86_VPCOMQmi: NewOpc = X86_VPCOMQmi_alt; break; case X86_VPCOMUBri: NewOpc = X86_VPCOMUBri_alt; break; case X86_VPCOMUBmi: NewOpc = X86_VPCOMUBmi_alt; break; case X86_VPCOMUWri: NewOpc = X86_VPCOMUWri_alt; break; case X86_VPCOMUWmi: NewOpc = X86_VPCOMUWmi_alt; break; case X86_VPCOMUDri: NewOpc = X86_VPCOMUDri_alt; break; case X86_VPCOMUDmi: NewOpc = X86_VPCOMUDmi_alt; break; case X86_VPCOMUQri: NewOpc = X86_VPCOMUQri_alt; break; case X86_VPCOMUQmi: NewOpc = X86_VPCOMUQmi_alt; break; } // Switch opcode to the one that doesn't get special printing. if (NewOpc != 0) { MCInst_setOpcode(mcInst, NewOpc); } } #endif } else if (type == TYPE_IMM5) { #ifndef CAPSTONE_X86_REDUCE // Check for immediates that printAVXCC can't handle. if (immediate >= 32) { unsigned NewOpc = 0; switch (MCInst_getOpcode(mcInst)) { default: break; // unexpected opcode case X86_VCMPPDrmi: NewOpc = X86_VCMPPDrmi_alt; break; case X86_VCMPPDrri: NewOpc = X86_VCMPPDrri_alt; break; case X86_VCMPPSrmi: NewOpc = X86_VCMPPSrmi_alt; break; case X86_VCMPPSrri: NewOpc = X86_VCMPPSrri_alt; break; case X86_VCMPSDrm: NewOpc = X86_VCMPSDrm_alt; break; case X86_VCMPSDrr: NewOpc = X86_VCMPSDrr_alt; break; case X86_VCMPSSrm: NewOpc = X86_VCMPSSrm_alt; break; case X86_VCMPSSrr: NewOpc = X86_VCMPSSrr_alt; break; case X86_VCMPPDYrmi: NewOpc = X86_VCMPPDYrmi_alt; break; case X86_VCMPPDYrri: NewOpc = X86_VCMPPDYrri_alt; break; case X86_VCMPPSYrmi: NewOpc = X86_VCMPPSYrmi_alt; break; case X86_VCMPPSYrri: NewOpc = X86_VCMPPSYrri_alt; break; case X86_VCMPPDZrmi: NewOpc = X86_VCMPPDZrmi_alt; break; case X86_VCMPPDZrri: NewOpc = X86_VCMPPDZrri_alt; break; case X86_VCMPPDZrrib: NewOpc = X86_VCMPPDZrrib_alt; break; case X86_VCMPPSZrmi: NewOpc = X86_VCMPPSZrmi_alt; break; case X86_VCMPPSZrri: NewOpc = X86_VCMPPSZrri_alt; break; case X86_VCMPPSZrrib: NewOpc = X86_VCMPPSZrrib_alt; break; case X86_VCMPPDZ128rmi: NewOpc = X86_VCMPPDZ128rmi_alt; break; case X86_VCMPPDZ128rri: NewOpc = X86_VCMPPDZ128rri_alt; break; case X86_VCMPPSZ128rmi: NewOpc = X86_VCMPPSZ128rmi_alt; break; case X86_VCMPPSZ128rri: NewOpc = X86_VCMPPSZ128rri_alt; break; case X86_VCMPPDZ256rmi: NewOpc = X86_VCMPPDZ256rmi_alt; break; case X86_VCMPPDZ256rri: NewOpc = X86_VCMPPDZ256rri_alt; break; case X86_VCMPPSZ256rmi: NewOpc = X86_VCMPPSZ256rmi_alt; break; case X86_VCMPPSZ256rri: NewOpc = X86_VCMPPSZ256rri_alt; break; case X86_VCMPSDZrm_Int: NewOpc = X86_VCMPSDZrmi_alt; break; case X86_VCMPSDZrr_Int: NewOpc = X86_VCMPSDZrri_alt; break; case X86_VCMPSDZrrb_Int: NewOpc = X86_VCMPSDZrrb_alt; break; case X86_VCMPSSZrm_Int: NewOpc = X86_VCMPSSZrmi_alt; break; case X86_VCMPSSZrr_Int: NewOpc = X86_VCMPSSZrri_alt; break; case X86_VCMPSSZrrb_Int: NewOpc = X86_VCMPSSZrrb_alt; break; } // Switch opcode to the one that doesn't get special printing. if (NewOpc != 0) { MCInst_setOpcode(mcInst, NewOpc); } } #endif } else if (type == TYPE_AVX512ICC) { #ifndef CAPSTONE_X86_REDUCE if (immediate >= 8 || ((immediate & 0x3) == 3)) { unsigned NewOpc = 0; switch (MCInst_getOpcode(mcInst)) { default: // llvm_unreachable("unexpected opcode"); case X86_VPCMPBZ128rmi: NewOpc = X86_VPCMPBZ128rmi_alt; break; case X86_VPCMPBZ128rmik: NewOpc = X86_VPCMPBZ128rmik_alt; break; case X86_VPCMPBZ128rri: NewOpc = X86_VPCMPBZ128rri_alt; break; case X86_VPCMPBZ128rrik: NewOpc = X86_VPCMPBZ128rrik_alt; break; case X86_VPCMPBZ256rmi: NewOpc = X86_VPCMPBZ256rmi_alt; break; case X86_VPCMPBZ256rmik: NewOpc = X86_VPCMPBZ256rmik_alt; break; case X86_VPCMPBZ256rri: NewOpc = X86_VPCMPBZ256rri_alt; break; case X86_VPCMPBZ256rrik: NewOpc = X86_VPCMPBZ256rrik_alt; break; case X86_VPCMPBZrmi: NewOpc = X86_VPCMPBZrmi_alt; break; case X86_VPCMPBZrmik: NewOpc = X86_VPCMPBZrmik_alt; break; case X86_VPCMPBZrri: NewOpc = X86_VPCMPBZrri_alt; break; case X86_VPCMPBZrrik: NewOpc = X86_VPCMPBZrrik_alt; break; case X86_VPCMPDZ128rmi: NewOpc = X86_VPCMPDZ128rmi_alt; break; case X86_VPCMPDZ128rmib: NewOpc = X86_VPCMPDZ128rmib_alt; break; case X86_VPCMPDZ128rmibk: NewOpc = X86_VPCMPDZ128rmibk_alt; break; case X86_VPCMPDZ128rmik: NewOpc = X86_VPCMPDZ128rmik_alt; break; case X86_VPCMPDZ128rri: NewOpc = X86_VPCMPDZ128rri_alt; break; case X86_VPCMPDZ128rrik: NewOpc = X86_VPCMPDZ128rrik_alt; break; case X86_VPCMPDZ256rmi: NewOpc = X86_VPCMPDZ256rmi_alt; break; case X86_VPCMPDZ256rmib: NewOpc = X86_VPCMPDZ256rmib_alt; break; case X86_VPCMPDZ256rmibk: NewOpc = X86_VPCMPDZ256rmibk_alt; break; case X86_VPCMPDZ256rmik: NewOpc = X86_VPCMPDZ256rmik_alt; break; case X86_VPCMPDZ256rri: NewOpc = X86_VPCMPDZ256rri_alt; break; case X86_VPCMPDZ256rrik: NewOpc = X86_VPCMPDZ256rrik_alt; break; case X86_VPCMPDZrmi: NewOpc = X86_VPCMPDZrmi_alt; break; case X86_VPCMPDZrmib: NewOpc = X86_VPCMPDZrmib_alt; break; case X86_VPCMPDZrmibk: NewOpc = X86_VPCMPDZrmibk_alt; break; case X86_VPCMPDZrmik: NewOpc = X86_VPCMPDZrmik_alt; break; case X86_VPCMPDZrri: NewOpc = X86_VPCMPDZrri_alt; break; case X86_VPCMPDZrrik: NewOpc = X86_VPCMPDZrrik_alt; break; case X86_VPCMPQZ128rmi: NewOpc = X86_VPCMPQZ128rmi_alt; break; case X86_VPCMPQZ128rmib: NewOpc = X86_VPCMPQZ128rmib_alt; break; case X86_VPCMPQZ128rmibk: NewOpc = X86_VPCMPQZ128rmibk_alt; break; case X86_VPCMPQZ128rmik: NewOpc = X86_VPCMPQZ128rmik_alt; break; case X86_VPCMPQZ128rri: NewOpc = X86_VPCMPQZ128rri_alt; break; case X86_VPCMPQZ128rrik: NewOpc = X86_VPCMPQZ128rrik_alt; break; case X86_VPCMPQZ256rmi: NewOpc = X86_VPCMPQZ256rmi_alt; break; case X86_VPCMPQZ256rmib: NewOpc = X86_VPCMPQZ256rmib_alt; break; case X86_VPCMPQZ256rmibk: NewOpc = X86_VPCMPQZ256rmibk_alt; break; case X86_VPCMPQZ256rmik: NewOpc = X86_VPCMPQZ256rmik_alt; break; case X86_VPCMPQZ256rri: NewOpc = X86_VPCMPQZ256rri_alt; break; case X86_VPCMPQZ256rrik: NewOpc = X86_VPCMPQZ256rrik_alt; break; case X86_VPCMPQZrmi: NewOpc = X86_VPCMPQZrmi_alt; break; case X86_VPCMPQZrmib: NewOpc = X86_VPCMPQZrmib_alt; break; case X86_VPCMPQZrmibk: NewOpc = X86_VPCMPQZrmibk_alt; break; case X86_VPCMPQZrmik: NewOpc = X86_VPCMPQZrmik_alt; break; case X86_VPCMPQZrri: NewOpc = X86_VPCMPQZrri_alt; break; case X86_VPCMPQZrrik: NewOpc = X86_VPCMPQZrrik_alt; break; case X86_VPCMPUBZ128rmi: NewOpc = X86_VPCMPUBZ128rmi_alt; break; case X86_VPCMPUBZ128rmik: NewOpc = X86_VPCMPUBZ128rmik_alt; break; case X86_VPCMPUBZ128rri: NewOpc = X86_VPCMPUBZ128rri_alt; break; case X86_VPCMPUBZ128rrik: NewOpc = X86_VPCMPUBZ128rrik_alt; break; case X86_VPCMPUBZ256rmi: NewOpc = X86_VPCMPUBZ256rmi_alt; break; case X86_VPCMPUBZ256rmik: NewOpc = X86_VPCMPUBZ256rmik_alt; break; case X86_VPCMPUBZ256rri: NewOpc = X86_VPCMPUBZ256rri_alt; break; case X86_VPCMPUBZ256rrik: NewOpc = X86_VPCMPUBZ256rrik_alt; break; case X86_VPCMPUBZrmi: NewOpc = X86_VPCMPUBZrmi_alt; break; case X86_VPCMPUBZrmik: NewOpc = X86_VPCMPUBZrmik_alt; break; case X86_VPCMPUBZrri: NewOpc = X86_VPCMPUBZrri_alt; break; case X86_VPCMPUBZrrik: NewOpc = X86_VPCMPUBZrrik_alt; break; case X86_VPCMPUDZ128rmi: NewOpc = X86_VPCMPUDZ128rmi_alt; break; case X86_VPCMPUDZ128rmib: NewOpc = X86_VPCMPUDZ128rmib_alt; break; case X86_VPCMPUDZ128rmibk: NewOpc = X86_VPCMPUDZ128rmibk_alt; break; case X86_VPCMPUDZ128rmik: NewOpc = X86_VPCMPUDZ128rmik_alt; break; case X86_VPCMPUDZ128rri: NewOpc = X86_VPCMPUDZ128rri_alt; break; case X86_VPCMPUDZ128rrik: NewOpc = X86_VPCMPUDZ128rrik_alt; break; case X86_VPCMPUDZ256rmi: NewOpc = X86_VPCMPUDZ256rmi_alt; break; case X86_VPCMPUDZ256rmib: NewOpc = X86_VPCMPUDZ256rmib_alt; break; case X86_VPCMPUDZ256rmibk: NewOpc = X86_VPCMPUDZ256rmibk_alt; break; case X86_VPCMPUDZ256rmik: NewOpc = X86_VPCMPUDZ256rmik_alt; break; case X86_VPCMPUDZ256rri: NewOpc = X86_VPCMPUDZ256rri_alt; break; case X86_VPCMPUDZ256rrik: NewOpc = X86_VPCMPUDZ256rrik_alt; break; case X86_VPCMPUDZrmi: NewOpc = X86_VPCMPUDZrmi_alt; break; case X86_VPCMPUDZrmib: NewOpc = X86_VPCMPUDZrmib_alt; break; case X86_VPCMPUDZrmibk: NewOpc = X86_VPCMPUDZrmibk_alt; break; case X86_VPCMPUDZrmik: NewOpc = X86_VPCMPUDZrmik_alt; break; case X86_VPCMPUDZrri: NewOpc = X86_VPCMPUDZrri_alt; break; case X86_VPCMPUDZrrik: NewOpc = X86_VPCMPUDZrrik_alt; break; case X86_VPCMPUQZ128rmi: NewOpc = X86_VPCMPUQZ128rmi_alt; break; case X86_VPCMPUQZ128rmib: NewOpc = X86_VPCMPUQZ128rmib_alt; break; case X86_VPCMPUQZ128rmibk: NewOpc = X86_VPCMPUQZ128rmibk_alt; break; case X86_VPCMPUQZ128rmik: NewOpc = X86_VPCMPUQZ128rmik_alt; break; case X86_VPCMPUQZ128rri: NewOpc = X86_VPCMPUQZ128rri_alt; break; case X86_VPCMPUQZ128rrik: NewOpc = X86_VPCMPUQZ128rrik_alt; break; case X86_VPCMPUQZ256rmi: NewOpc = X86_VPCMPUQZ256rmi_alt; break; case X86_VPCMPUQZ256rmib: NewOpc = X86_VPCMPUQZ256rmib_alt; break; case X86_VPCMPUQZ256rmibk: NewOpc = X86_VPCMPUQZ256rmibk_alt; break; case X86_VPCMPUQZ256rmik: NewOpc = X86_VPCMPUQZ256rmik_alt; break; case X86_VPCMPUQZ256rri: NewOpc = X86_VPCMPUQZ256rri_alt; break; case X86_VPCMPUQZ256rrik: NewOpc = X86_VPCMPUQZ256rrik_alt; break; case X86_VPCMPUQZrmi: NewOpc = X86_VPCMPUQZrmi_alt; break; case X86_VPCMPUQZrmib: NewOpc = X86_VPCMPUQZrmib_alt; break; case X86_VPCMPUQZrmibk: NewOpc = X86_VPCMPUQZrmibk_alt; break; case X86_VPCMPUQZrmik: NewOpc = X86_VPCMPUQZrmik_alt; break; case X86_VPCMPUQZrri: NewOpc = X86_VPCMPUQZrri_alt; break; case X86_VPCMPUQZrrik: NewOpc = X86_VPCMPUQZrrik_alt; break; case X86_VPCMPUWZ128rmi: NewOpc = X86_VPCMPUWZ128rmi_alt; break; case X86_VPCMPUWZ128rmik: NewOpc = X86_VPCMPUWZ128rmik_alt; break; case X86_VPCMPUWZ128rri: NewOpc = X86_VPCMPUWZ128rri_alt; break; case X86_VPCMPUWZ128rrik: NewOpc = X86_VPCMPUWZ128rrik_alt; break; case X86_VPCMPUWZ256rmi: NewOpc = X86_VPCMPUWZ256rmi_alt; break; case X86_VPCMPUWZ256rmik: NewOpc = X86_VPCMPUWZ256rmik_alt; break; case X86_VPCMPUWZ256rri: NewOpc = X86_VPCMPUWZ256rri_alt; break; case X86_VPCMPUWZ256rrik: NewOpc = X86_VPCMPUWZ256rrik_alt; break; case X86_VPCMPUWZrmi: NewOpc = X86_VPCMPUWZrmi_alt; break; case X86_VPCMPUWZrmik: NewOpc = X86_VPCMPUWZrmik_alt; break; case X86_VPCMPUWZrri: NewOpc = X86_VPCMPUWZrri_alt; break; case X86_VPCMPUWZrrik: NewOpc = X86_VPCMPUWZrrik_alt; break; case X86_VPCMPWZ128rmi: NewOpc = X86_VPCMPWZ128rmi_alt; break; case X86_VPCMPWZ128rmik: NewOpc = X86_VPCMPWZ128rmik_alt; break; case X86_VPCMPWZ128rri: NewOpc = X86_VPCMPWZ128rri_alt; break; case X86_VPCMPWZ128rrik: NewOpc = X86_VPCMPWZ128rrik_alt; break; case X86_VPCMPWZ256rmi: NewOpc = X86_VPCMPWZ256rmi_alt; break; case X86_VPCMPWZ256rmik: NewOpc = X86_VPCMPWZ256rmik_alt; break; case X86_VPCMPWZ256rri: NewOpc = X86_VPCMPWZ256rri_alt; break; case X86_VPCMPWZ256rrik: NewOpc = X86_VPCMPWZ256rrik_alt; break; case X86_VPCMPWZrmi: NewOpc = X86_VPCMPWZrmi_alt; break; case X86_VPCMPWZrmik: NewOpc = X86_VPCMPWZrmik_alt; break; case X86_VPCMPWZrri: NewOpc = X86_VPCMPWZrri_alt; break; case X86_VPCMPWZrrik: NewOpc = X86_VPCMPWZrrik_alt; break; } // Switch opcode to the one that doesn't get special printing. if (NewOpc != 0) { MCInst_setOpcode(mcInst, NewOpc); } } #endif } switch (type) { case TYPE_XMM: MCOperand_CreateReg0(mcInst, X86_XMM0 + ((uint32_t)immediate >> 4)); return; case TYPE_YMM: MCOperand_CreateReg0(mcInst, X86_YMM0 + ((uint32_t)immediate >> 4)); return; case TYPE_ZMM: MCOperand_CreateReg0(mcInst, X86_ZMM0 + ((uint32_t)immediate >> 4)); return; default: // operand is 64 bits wide. Do nothing. break; } MCOperand_CreateImm0(mcInst, immediate); if (type == TYPE_MOFFS) { MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); } } /// translateRMRegister - Translates a register stored in the R/M field of the /// ModR/M byte to its LLVM equivalent and appends it to an MCInst. /// @param mcInst - The MCInst to append to. /// @param insn - The internal instruction to extract the R/M field /// from. /// @return - 0 on success; -1 otherwise static bool translateRMRegister(MCInst *mcInst, InternalInstruction *insn) { if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { //debug("A R/M register operand may not have a SIB byte"); return true; } switch (insn->eaBase) { case EA_BASE_NONE: //debug("EA_BASE_NONE for ModR/M base"); return true; #define ENTRY(x) case EA_BASE_##x: ALL_EA_BASES #undef ENTRY //debug("A R/M register operand may not have a base; " // "the operand must be a register."); return true; #define ENTRY(x) \ case EA_REG_##x: \ MCOperand_CreateReg0(mcInst, X86_##x); break; ALL_REGS #undef ENTRY default: //debug("Unexpected EA base register"); return true; } return false; } /// translateRMMemory - Translates a memory operand stored in the Mod and R/M /// fields of an internal instruction (and possibly its SIB byte) to a memory /// operand in LLVM's format, and appends it to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param insn - The instruction to extract Mod, R/M, and SIB fields /// from. /// @return - 0 on success; nonzero otherwise static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn) { // Addresses in an MCInst are represented as five operands: // 1. basereg (register) The R/M base, or (if there is a SIB) the // SIB base // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified // scale amount // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) // the index (which is multiplied by the // scale amount) // 4. displacement (immediate) 0, or the displacement if there is one // 5. segmentreg (register) x86_registerNONE for now, but could be set // if we have segment overrides int scaleAmount, indexReg; if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { if (insn->sibBase != SIB_BASE_NONE) { switch (insn->sibBase) { #define ENTRY(x) \ case SIB_BASE_##x: \ MCOperand_CreateReg0(mcInst, X86_##x); break; ALL_SIB_BASES #undef ENTRY default: //debug("Unexpected sibBase"); return true; } } else { MCOperand_CreateReg0(mcInst, 0); } if (insn->sibIndex != SIB_INDEX_NONE) { switch (insn->sibIndex) { default: //debug("Unexpected sibIndex"); return true; #define ENTRY(x) \ case SIB_INDEX_##x: \ indexReg = X86_##x; break; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM REGS_ZMM #undef ENTRY } } else { // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present, // but no index is used and modrm alone should have been enough. // -No base register in 32-bit mode. In 64-bit mode this is used to // avoid rip-relative addressing. // -Any base register used other than ESP/RSP/R12D/R12. Using these as a // base always requires a SIB byte. // -A scale other than 1 is used. if (insn->sibScale != 1 || (insn->sibBase == SIB_BASE_NONE && insn->mode != MODE_64BIT) || (insn->sibBase != SIB_BASE_NONE && insn->sibBase != SIB_BASE_ESP && insn->sibBase != SIB_BASE_RSP && insn->sibBase != SIB_BASE_R12D && insn->sibBase != SIB_BASE_R12)) { indexReg = insn->addressSize == 4? X86_EIZ : X86_RIZ; } else indexReg = 0; } scaleAmount = insn->sibScale; } else { switch (insn->eaBase) { case EA_BASE_NONE: if (insn->eaDisplacement == EA_DISP_NONE) { //debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); return true; } if (insn->mode == MODE_64BIT) { if (insn->prefix3 == 0x67) // address-size prefix overrides RIP relative addressing MCOperand_CreateReg0(mcInst, X86_EIP); else // Section 2.2.1.6 MCOperand_CreateReg0(mcInst, insn->addressSize == 4 ? X86_EIP : X86_RIP); } else { MCOperand_CreateReg0(mcInst, 0); } indexReg = 0; break; case EA_BASE_BX_SI: MCOperand_CreateReg0(mcInst, X86_BX); indexReg = X86_SI; break; case EA_BASE_BX_DI: MCOperand_CreateReg0(mcInst, X86_BX); indexReg = X86_DI; break; case EA_BASE_BP_SI: MCOperand_CreateReg0(mcInst, X86_BP); indexReg = X86_SI; break; case EA_BASE_BP_DI: MCOperand_CreateReg0(mcInst, X86_BP); indexReg = X86_DI; break; default: indexReg = 0; switch (insn->eaBase) { default: //debug("Unexpected eaBase"); return true; // Here, we will use the fill-ins defined above. However, // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and // sib and sib64 were handled in the top-level if, so they're only // placeholders to keep the compiler happy. #define ENTRY(x) \ case EA_BASE_##x: \ MCOperand_CreateReg0(mcInst, X86_##x); break; ALL_EA_BASES #undef ENTRY #define ENTRY(x) case EA_REG_##x: ALL_REGS #undef ENTRY //debug("A R/M memory operand may not be a register; " // "the base field must be a base."); return true; } } scaleAmount = 1; } MCOperand_CreateImm0(mcInst, scaleAmount); MCOperand_CreateReg0(mcInst, indexReg); MCOperand_CreateImm0(mcInst, insn->displacement); MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); return false; } /// translateRM - Translates an operand stored in the R/M (and possibly SIB) /// byte of an instruction to LLVM form, and appends it to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param operand - The operand, as stored in the descriptor table. /// @param insn - The instruction to extract Mod, R/M, and SIB fields /// from. /// @return - 0 on success; nonzero otherwise static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand, InternalInstruction *insn) { switch (operand->type) { default: //debug("Unexpected type for a R/M operand"); return true; case TYPE_R8: case TYPE_R16: case TYPE_R32: case TYPE_R64: case TYPE_Rv: case TYPE_MM64: case TYPE_XMM: case TYPE_YMM: case TYPE_ZMM: case TYPE_VK: case TYPE_DEBUGREG: case TYPE_CONTROLREG: case TYPE_BNDR: return translateRMRegister(mcInst, insn); case TYPE_M: case TYPE_MVSIBX: case TYPE_MVSIBY: case TYPE_MVSIBZ: return translateRMMemory(mcInst, insn); } } /// translateFPRegister - Translates a stack position on the FPU stack to its /// LLVM form, and appends it to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param stackPos - The stack position to translate. static void translateFPRegister(MCInst *mcInst, uint8_t stackPos) { MCOperand_CreateReg0(mcInst, X86_ST0 + stackPos); } /// translateMaskRegister - Translates a 3-bit mask register number to /// LLVM form, and appends it to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param maskRegNum - Number of mask register from 0 to 7. /// @return - false on success; true otherwise. static bool translateMaskRegister(MCInst *mcInst, uint8_t maskRegNum) { if (maskRegNum >= 8) { // debug("Invalid mask register number"); return true; } MCOperand_CreateReg0(mcInst, X86_K0 + maskRegNum); return false; } /// translateOperand - Translates an operand stored in an internal instruction /// to LLVM's format and appends it to an MCInst. /// /// @param mcInst - The MCInst to append to. /// @param operand - The operand, as stored in the descriptor table. /// @param insn - The internal instruction. /// @return - false on success; true otherwise. static bool translateOperand(MCInst *mcInst, const OperandSpecifier *operand, InternalInstruction *insn) { switch (operand->encoding) { case ENCODING_REG: translateRegister(mcInst, insn->reg); return false; case ENCODING_WRITEMASK: return translateMaskRegister(mcInst, insn->writemask); CASE_ENCODING_RM: CASE_ENCODING_VSIB: return translateRM(mcInst, operand, insn); case ENCODING_IB: case ENCODING_IW: case ENCODING_ID: case ENCODING_IO: case ENCODING_Iv: case ENCODING_Ia: translateImmediate(mcInst, insn->immediates[insn->numImmediatesTranslated++], operand, insn); return false; case ENCODING_IRC: MCOperand_CreateImm0(mcInst, insn->RC); return false; case ENCODING_SI: return translateSrcIndex(mcInst, insn); case ENCODING_DI: return translateDstIndex(mcInst, insn); case ENCODING_RB: case ENCODING_RW: case ENCODING_RD: case ENCODING_RO: case ENCODING_Rv: translateRegister(mcInst, insn->opcodeRegister); return false; case ENCODING_FP: translateFPRegister(mcInst, insn->modRM & 7); return false; case ENCODING_VVVV: translateRegister(mcInst, insn->vvvv); return false; case ENCODING_DUP: return translateOperand(mcInst, &insn->operands[operand->type - TYPE_DUP0], insn); default: //debug("Unhandled operand encoding during translation"); return true; } } static bool translateInstruction(MCInst *mcInst, InternalInstruction *insn) { int index; if (!insn->spec) { //debug("Instruction has no specification"); return true; } MCInst_clear(mcInst); MCInst_setOpcode(mcInst, insn->instructionID); // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 // prefix bytes should be disassembled as xrelease and xacquire then set the // opcode to those instead of the rep and repne opcodes. #ifndef CAPSTONE_X86_REDUCE if (insn->xAcquireRelease) { if (MCInst_getOpcode(mcInst) == X86_REP_PREFIX) MCInst_setOpcode(mcInst, X86_XRELEASE_PREFIX); else if (MCInst_getOpcode(mcInst) == X86_REPNE_PREFIX) MCInst_setOpcode(mcInst, X86_XACQUIRE_PREFIX); } #endif insn->numImmediatesTranslated = 0; for (index = 0; index < X86_MAX_OPERANDS; ++index) { if (insn->operands[index].encoding != ENCODING_NONE) { if (translateOperand(mcInst, &insn->operands[index], insn)) { return true; } } } return false; } static int reader(const struct reader_info *info, uint8_t *byte, uint64_t address) { if (address - info->offset >= info->size) // out of buffer range return -1; *byte = info->code[address - info->offset]; return 0; } // copy x86 detail information from internal structure to public structure static void update_pub_insn(cs_insn *pub, InternalInstruction *inter) { if (inter->vectorExtensionType != 0) { memcpy(pub->detail->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->detail->x86.opcode)); } else { if (inter->twoByteEscape) { if (inter->threeByteEscape) { pub->detail->x86.opcode[0] = inter->twoByteEscape; pub->detail->x86.opcode[1] = inter->threeByteEscape; pub->detail->x86.opcode[2] = inter->opcode; } else { pub->detail->x86.opcode[0] = inter->twoByteEscape; pub->detail->x86.opcode[1] = inter->opcode; } } else { pub->detail->x86.opcode[0] = inter->opcode; } } pub->detail->x86.rex = inter->rexPrefix; pub->detail->x86.addr_size = inter->addressSize; pub->detail->x86.modrm = inter->orgModRM; pub->detail->x86.encoding.modrm_offset = inter->modRMOffset; pub->detail->x86.sib = inter->sib; pub->detail->x86.sib_index = x86_map_sib_index(inter->sibIndex); pub->detail->x86.sib_scale = inter->sibScale; pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase); pub->detail->x86.disp = inter->displacement; if (inter->consumedDisplacement) { pub->detail->x86.encoding.disp_offset = inter->displacementOffset; pub->detail->x86.encoding.disp_size = inter->displacementSize; } pub->detail->x86.encoding.imm_offset = inter->immediateOffset; if (pub->detail->x86.encoding.imm_size == 0 && inter->immediateOffset != 0) pub->detail->x86.encoding.imm_size = inter->immediateSize; } void X86_init(MCRegisterInfo *MRI) { // InitMCRegisterInfo(), X86GenRegisterInfo.inc // RI->InitMCRegisterInfo(X86RegDesc, 277, // RA, PC, // X86MCRegisterClasses, 86, // X86RegUnitRoots, 162, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, // X86RegClassStrings, // X86SubRegIdxLists, 9, // X86SubRegIdxRanges, X86RegEncodingTable); /* InitMCRegisterInfo(X86RegDesc, 234, RA, PC, X86MCRegisterClasses, 79, X86RegUnitRoots, 119, X86RegDiffLists, X86RegStrings, X86SubRegIdxLists, 7, X86SubRegIdxRanges, X86RegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, X86RegDesc, 277, 0, 0, X86MCRegisterClasses, 86, 0, 0, X86RegDiffLists, 0, X86SubRegIdxLists, 9, 0); } // Public interface for the disassembler bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *_info) { cs_struct *handle = (cs_struct *)(uintptr_t)ud; InternalInstruction insn = { 0 }; struct reader_info info; int ret; bool result; info.code = code; info.size = code_len; info.offset = address; if (instr->flat_insn->detail) { // instr->flat_insn->detail initialization: 3 alternatives // 1. The whole structure, this is how it's done in other arch disassemblers // Probably overkill since cs_detail is huge because of the 36 operands of ARM //memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); // 2. Only the part relevant to x86 memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86) + sizeof(cs_x86)); // 3. The relevant part except for x86.operands // sizeof(cs_x86) is 0x1c0, sizeof(x86.operands) is 0x180 // marginally faster, should be okay since x86.op_count is set to 0 //memset(instr->flat_insn->detail, 0, offsetof(cs_detail, x86)+offsetof(cs_x86, operands)); } if (handle->mode & CS_MODE_16) ret = decodeInstruction(&insn, reader, &info, address, MODE_16BIT); else if (handle->mode & CS_MODE_32) ret = decodeInstruction(&insn, reader, &info, address, MODE_32BIT); else ret = decodeInstruction(&insn, reader, &info, address, MODE_64BIT); if (ret) { // *size = (uint16_t)(insn.readerCursor - address); return false; } else { *size = (uint16_t)insn.length; result = (!translateInstruction(instr, &insn)) ? true : false; if (result) { unsigned Flags = X86_IP_NO_PREFIX; instr->imm_size = insn.immSize; // copy all prefixes instr->x86_prefix[0] = insn.prefix0; instr->x86_prefix[1] = insn.prefix1; instr->x86_prefix[2] = insn.prefix2; instr->x86_prefix[3] = insn.prefix3; instr->xAcquireRelease = insn.xAcquireRelease; if (handle->detail) { update_pub_insn(instr->flat_insn, &insn); } if (insn.hasAdSize) Flags |= X86_IP_HAS_AD_SIZE; if (!insn.mandatoryPrefix) { if (insn.hasOpSize) Flags |= X86_IP_HAS_OP_SIZE; if (insn.repeatPrefix == 0xf2) Flags |= X86_IP_HAS_REPEAT_NE; else if (insn.repeatPrefix == 0xf3 && // It should not be 'pause' f3 90 insn.opcode != 0x90) Flags |= X86_IP_HAS_REPEAT; if (insn.hasLockPrefix) Flags |= X86_IP_HAS_LOCK; } instr->flags = Flags; } return result; } } #endif capstone-sys-0.15.0/capstone/arch/X86/X86Disassembler.h000064400000000000000000000014550072674642500206060ustar 00000000000000//===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_X86_DISASSEMBLER_H #define CS_X86_DISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "X86DisassemblerDecoderCommon.h" bool X86_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); void X86_init(MCRegisterInfo *MRI); #endif capstone-sys-0.15.0/capstone/arch/X86/X86DisassemblerDecoder.c000064400000000000000000002033770072674642500220760ustar 00000000000000/*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===* * * The LLVM Compiler Infrastructure * * This file is distributed under the University of Illinois Open Source * License. See LICENSE.TXT for details. * *===----------------------------------------------------------------------===* * * This file is part of the X86 Disassembler. * It contains the implementation of the instruction decoder. * Documentation for the disassembler can be found in X86Disassembler.h. * *===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_X86 #include /* for va_*() */ #if defined(CAPSTONE_HAS_OSXKERNEL) #include #else #include /* for exit() */ #endif #include #include "../../cs_priv.h" #include "../../utils.h" #include "X86DisassemblerDecoder.h" #include "X86Mapping.h" /// Specifies whether a ModR/M byte is needed and (if so) which /// instruction each possible value of the ModR/M byte corresponds to. Once /// this information is known, we have narrowed down to a single instruction. struct ModRMDecision { uint8_t modrm_type; uint16_t instructionIDs; }; /// Specifies which set of ModR/M->instruction tables to look at /// given a particular opcode. struct OpcodeDecision { struct ModRMDecision modRMDecisions[256]; }; /// Specifies which opcode->instruction tables to look at given /// a particular context (set of attributes). Since there are many possible /// contexts, the decoder first uses CONTEXTS_SYM to determine which context /// applies given a specific set of attributes. Hence there are only IC_max /// entries in this table, rather than 2^(ATTR_max). struct ContextDecision { struct OpcodeDecision opcodeDecisions[IC_max]; }; #ifdef CAPSTONE_X86_REDUCE #include "X86GenDisassemblerTables_reduce.inc" #include "X86GenDisassemblerTables_reduce2.inc" #include "X86Lookup16_reduce.inc" #else #include "X86GenDisassemblerTables.inc" #include "X86GenDisassemblerTables2.inc" #include "X86Lookup16.inc" #endif /* * contextForAttrs - Client for the instruction context table. Takes a set of * attributes and returns the appropriate decode context. * * @param attrMask - Attributes, from the enumeration attributeBits. * @return - The InstructionContext to use when looking up an * an instruction with these attributes. */ static InstructionContext contextForAttrs(uint16_t attrMask) { return CONTEXTS_SYM[attrMask]; } /* * modRMRequired - Reads the appropriate instruction table to determine whether * the ModR/M byte is required to decode a particular instruction. * * @param type - The opcode type (i.e., how many bytes it has). * @param insnContext - The context for the instruction, as returned by * contextForAttrs. * @param opcode - The last byte of the instruction's opcode, not counting * ModR/M extensions and escapes. * @return - true if the ModR/M byte is required, false otherwise. */ static int modRMRequired(OpcodeType type, InstructionContext insnContext, uint16_t opcode) { const struct OpcodeDecision *decision = NULL; const uint8_t *indextable = NULL; unsigned int index; switch (type) { default: break; case ONEBYTE: decision = ONEBYTE_SYM; indextable = index_x86DisassemblerOneByteOpcodes; break; case TWOBYTE: decision = TWOBYTE_SYM; indextable = index_x86DisassemblerTwoByteOpcodes; break; case THREEBYTE_38: decision = THREEBYTE38_SYM; indextable = index_x86DisassemblerThreeByte38Opcodes; break; case THREEBYTE_3A: decision = THREEBYTE3A_SYM; indextable = index_x86DisassemblerThreeByte3AOpcodes; break; #ifndef CAPSTONE_X86_REDUCE case XOP8_MAP: decision = XOP8_MAP_SYM; indextable = index_x86DisassemblerXOP8Opcodes; break; case XOP9_MAP: decision = XOP9_MAP_SYM; indextable = index_x86DisassemblerXOP9Opcodes; break; case XOPA_MAP: decision = XOPA_MAP_SYM; indextable = index_x86DisassemblerXOPAOpcodes; break; case THREEDNOW_MAP: // 3DNow instructions always have ModRM byte return true; #endif } // return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].modrm_type != MODRM_ONEENTRY; index = indextable[insnContext]; if (index) return decision[index - 1].modRMDecisions[opcode].modrm_type != MODRM_ONEENTRY; else return false; } /* * decode - Reads the appropriate instruction table to obtain the unique ID of * an instruction. * * @param type - See modRMRequired(). * @param insnContext - See modRMRequired(). * @param opcode - See modRMRequired(). * @param modRM - The ModR/M byte if required, or any value if not. * @return - The UID of the instruction, or 0 on failure. */ static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM) { const struct ModRMDecision *dec = NULL; unsigned int index; static const struct OpcodeDecision emptyDecision = { 0 }; switch (type) { default: break; // never reach case ONEBYTE: // dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerOneByteOpcodes[insnContext]; if (index) dec = &ONEBYTE_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; case TWOBYTE: //dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerTwoByteOpcodes[insnContext]; if (index) dec = &TWOBYTE_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; case THREEBYTE_38: // dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerThreeByte38Opcodes[insnContext]; if (index) dec = &THREEBYTE38_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; case THREEBYTE_3A: //dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerThreeByte3AOpcodes[insnContext]; if (index) dec = &THREEBYTE3A_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; #ifndef CAPSTONE_X86_REDUCE case XOP8_MAP: // dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerXOP8Opcodes[insnContext]; if (index) dec = &XOP8_MAP_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; case XOP9_MAP: // dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerXOP9Opcodes[insnContext]; if (index) dec = &XOP9_MAP_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; case XOPA_MAP: // dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86DisassemblerXOPAOpcodes[insnContext]; if (index) dec = &XOPA_MAP_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; case THREEDNOW_MAP: // dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; index = index_x86Disassembler3DNowOpcodes[insnContext]; if (index) dec = &THREEDNOW_MAP_SYM[index - 1].modRMDecisions[opcode]; else dec = &emptyDecision.modRMDecisions[opcode]; break; #endif } switch (dec->modrm_type) { default: // debug("Corrupt table! Unknown modrm_type"); return 0; case MODRM_ONEENTRY: return modRMTable[dec->instructionIDs]; case MODRM_SPLITRM: if (modFromModRM(modRM) == 0x3) return modRMTable[dec->instructionIDs + 1]; return modRMTable[dec->instructionIDs]; case MODRM_SPLITREG: if (modFromModRM(modRM) == 0x3) return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3) + 8]; return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; case MODRM_SPLITMISC: if (modFromModRM(modRM) == 0x3) return modRMTable[dec->instructionIDs+(modRM & 0x3f) + 8]; return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; case MODRM_FULL: return modRMTable[dec->instructionIDs+modRM]; } } /* * specifierForUID - Given a UID, returns the name and operand specification for * that instruction. * * @param uid - The unique ID for the instruction. This should be returned by * decode(); specifierForUID will not check bounds. * @return - A pointer to the specification for that instruction. */ static const struct InstructionSpecifier *specifierForUID(InstrUID uid) { return &INSTRUCTIONS_SYM[uid]; } /* * consumeByte - Uses the reader function provided by the user to consume one * byte from the instruction's memory and advance the cursor. * * @param insn - The instruction with the reader function to use. The cursor * for this instruction is advanced. * @param byte - A pointer to a pre-allocated memory buffer to be populated * with the data read. * @return - 0 if the read was successful; nonzero otherwise. */ static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); if (!ret) ++(insn->readerCursor); return ret; } /* * lookAtByte - Like consumeByte, but does not advance the cursor. * * @param insn - See consumeByte(). * @param byte - See consumeByte(). * @return - See consumeByte(). */ static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { return insn->reader(insn->readerArg, byte, insn->readerCursor); } static void unconsumeByte(struct InternalInstruction* insn) { insn->readerCursor--; } #define CONSUME_FUNC(name, type) \ static int name(struct InternalInstruction* insn, type* ptr) { \ type combined = 0; \ unsigned offset; \ for (offset = 0; offset < sizeof(type); ++offset) { \ uint8_t byte; \ int ret = insn->reader(insn->readerArg, \ &byte, \ insn->readerCursor + offset); \ if (ret) \ return ret; \ combined = combined | ((uint64_t)byte << (offset * 8)); \ } \ *ptr = combined; \ insn->readerCursor += sizeof(type); \ return 0; \ } /* * consume* - Use the reader function provided by the user to consume data * values of various sizes from the instruction's memory and advance the * cursor appropriately. These readers perform endian conversion. * * @param insn - See consumeByte(). * @param ptr - A pointer to a pre-allocated memory of appropriate size to * be populated with the data read. * @return - See consumeByte(). */ CONSUME_FUNC(consumeInt8, int8_t) CONSUME_FUNC(consumeInt16, int16_t) CONSUME_FUNC(consumeInt32, int32_t) CONSUME_FUNC(consumeUInt16, uint16_t) CONSUME_FUNC(consumeUInt32, uint32_t) CONSUME_FUNC(consumeUInt64, uint64_t) static bool isREX(struct InternalInstruction *insn, uint8_t prefix) { if (insn->mode == MODE_64BIT) return prefix >= 0x40 && prefix <= 0x4f; return false; } /* * setPrefixPresent - Marks that a particular prefix is present as mandatory * * @param insn - The instruction to be marked as having the prefix. * @param prefix - The prefix that is present. */ static void setPrefixPresent(struct InternalInstruction *insn, uint8_t prefix) { uint8_t nextByte; switch (prefix) { case 0xf0: // LOCK insn->hasLockPrefix = true; insn->repeatPrefix = 0; break; case 0xf2: // REPNE/REPNZ case 0xf3: // REP or REPE/REPZ if (lookAtByte(insn, &nextByte)) break; // TODO: // 1. There could be several 0x66 // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then // it's not mandatory prefix // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need // 0x0f exactly after it to be mandatory prefix if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66) // The last of 0xf2 /0xf3 is mandatory prefix insn->mandatoryPrefix = prefix; insn->repeatPrefix = prefix; insn->hasLockPrefix = false; break; case 0x66: if (lookAtByte(insn, &nextByte)) break; // 0x66 can't overwrite existing mandatory prefix and should be ignored if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte))) insn->mandatoryPrefix = prefix; break; } } /* * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the * instruction as having them. Also sets the instruction's default operand, * address, and other relevant data sizes to report operands correctly. * * @param insn - The instruction whose prefixes are to be read. * @return - 0 if the instruction could be read until the end of the prefix * bytes, and no prefixes conflicted; nonzero otherwise. */ static int readPrefixes(struct InternalInstruction* insn) { bool isPrefix = true; uint8_t byte = 0; uint8_t nextByte; while (isPrefix) { if (insn->mode == MODE_64BIT) { // eliminate consecutive redundant REX bytes in front if (consumeByte(insn, &byte)) return -1; if ((byte & 0xf0) == 0x40) { while(true) { if (lookAtByte(insn, &byte)) // out of input code return -1; if ((byte & 0xf0) == 0x40) { // another REX prefix, but we only remember the last one if (consumeByte(insn, &byte)) return -1; } else break; } // recover the last REX byte if next byte is not a legacy prefix switch (byte) { case 0xf2: /* REPNE/REPNZ */ case 0xf3: /* REP or REPE/REPZ */ case 0xf0: /* LOCK */ case 0x2e: /* CS segment override -OR- Branch not taken */ case 0x36: /* SS segment override -OR- Branch taken */ case 0x3e: /* DS segment override */ case 0x26: /* ES segment override */ case 0x64: /* FS segment override */ case 0x65: /* GS segment override */ case 0x66: /* Operand-size override */ case 0x67: /* Address-size override */ break; default: /* Not a prefix byte */ unconsumeByte(insn); break; } } else { unconsumeByte(insn); } } /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */ if (consumeByte(insn, &byte)) return -1; if (insn->readerCursor - 1 == insn->startLocation && (byte == 0xf2 || byte == 0xf3)) { // prefix requires next byte if (lookAtByte(insn, &nextByte)) return -1; /* * If the byte is 0xf2 or 0xf3, and any of the following conditions are * met: * - it is followed by a LOCK (0xf0) prefix * - it is followed by an xchg instruction * then it should be disassembled as a xacquire/xrelease not repne/rep. */ if (((nextByte == 0xf0) || ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) { insn->xAcquireRelease = byte; } /* * Also if the byte is 0xf3, and the following condition is met: * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or * "mov mem, imm" (opcode 0xc6/0xc7) instructions. * then it should be disassembled as an xrelease not rep. */ if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 || nextByte == 0xc6 || nextByte == 0xc7)) { insn->xAcquireRelease = byte; } if (isREX(insn, nextByte)) { uint8_t nnextByte; // Go to REX prefix after the current one if (consumeByte(insn, &nnextByte)) return -1; // We should be able to read next byte after REX prefix if (lookAtByte(insn, &nnextByte)) return -1; unconsumeByte(insn); } } switch (byte) { case 0xf0: /* LOCK */ case 0xf2: /* REPNE/REPNZ */ case 0xf3: /* REP or REPE/REPZ */ // only accept the last prefix setPrefixPresent(insn, byte); insn->prefix0 = byte; break; case 0x2e: /* CS segment override -OR- Branch not taken */ case 0x36: /* SS segment override -OR- Branch taken */ case 0x3e: /* DS segment override */ case 0x26: /* ES segment override */ case 0x64: /* FS segment override */ case 0x65: /* GS segment override */ switch (byte) { case 0x2e: insn->segmentOverride = SEG_OVERRIDE_CS; insn->prefix1 = byte; break; case 0x36: insn->segmentOverride = SEG_OVERRIDE_SS; insn->prefix1 = byte; break; case 0x3e: insn->segmentOverride = SEG_OVERRIDE_DS; insn->prefix1 = byte; break; case 0x26: insn->segmentOverride = SEG_OVERRIDE_ES; insn->prefix1 = byte; break; case 0x64: insn->segmentOverride = SEG_OVERRIDE_FS; insn->prefix1 = byte; break; case 0x65: insn->segmentOverride = SEG_OVERRIDE_GS; insn->prefix1 = byte; break; default: // debug("Unhandled override"); return -1; } setPrefixPresent(insn, byte); break; case 0x66: /* Operand-size override */ insn->hasOpSize = true; setPrefixPresent(insn, byte); insn->prefix2 = byte; break; case 0x67: /* Address-size override */ insn->hasAdSize = true; setPrefixPresent(insn, byte); insn->prefix3 = byte; break; default: /* Not a prefix byte */ isPrefix = false; break; } } insn->vectorExtensionType = TYPE_NO_VEX_XOP; if (byte == 0x62) { uint8_t byte1, byte2; if (consumeByte(insn, &byte1)) { // dbgprintf(insn, "Couldn't read second byte of EVEX prefix"); return -1; } if (lookAtByte(insn, &byte2)) { // dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); unconsumeByte(insn); /* unconsume byte1 */ unconsumeByte(insn); /* unconsume byte */ } else { if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) && ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) { insn->vectorExtensionType = TYPE_EVEX; } else { unconsumeByte(insn); /* unconsume byte1 */ unconsumeByte(insn); /* unconsume byte */ } } if (insn->vectorExtensionType == TYPE_EVEX) { insn->vectorExtensionPrefix[0] = byte; insn->vectorExtensionPrefix[1] = byte1; if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) { // dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); return -1; } if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) { // dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix"); return -1; } /* We simulate the REX prefix for simplicity's sake */ if (insn->mode == MODE_64BIT) { insn->rexPrefix = 0x40 | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); } // dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx", // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], // insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]); } } else if (byte == 0xc4) { uint8_t byte1; if (lookAtByte(insn, &byte1)) { // dbgprintf(insn, "Couldn't read second byte of VEX"); return -1; } if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) insn->vectorExtensionType = TYPE_VEX_3B; else unconsumeByte(insn); if (insn->vectorExtensionType == TYPE_VEX_3B) { insn->vectorExtensionPrefix[0] = byte; consumeByte(insn, &insn->vectorExtensionPrefix[1]); consumeByte(insn, &insn->vectorExtensionPrefix[2]); /* We simulate the REX prefix for simplicity's sake */ if (insn->mode == MODE_64BIT) insn->rexPrefix = 0x40 | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0); // dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], // insn->vectorExtensionPrefix[2]); } } else if (byte == 0xc5) { uint8_t byte1; if (lookAtByte(insn, &byte1)) { // dbgprintf(insn, "Couldn't read second byte of VEX"); return -1; } if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) insn->vectorExtensionType = TYPE_VEX_2B; else unconsumeByte(insn); if (insn->vectorExtensionType == TYPE_VEX_2B) { insn->vectorExtensionPrefix[0] = byte; consumeByte(insn, &insn->vectorExtensionPrefix[1]); if (insn->mode == MODE_64BIT) insn->rexPrefix = 0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2); switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { default: break; case VEX_PREFIX_66: insn->hasOpSize = true; break; } // dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", // insn->vectorExtensionPrefix[0], // insn->vectorExtensionPrefix[1]); } } else if (byte == 0x8f) { uint8_t byte1; if (lookAtByte(insn, &byte1)) { // dbgprintf(insn, "Couldn't read second byte of XOP"); return -1; } if ((byte1 & 0x38) != 0x0) /* 0 in these 3 bits is a POP instruction. */ insn->vectorExtensionType = TYPE_XOP; else unconsumeByte(insn); if (insn->vectorExtensionType == TYPE_XOP) { insn->vectorExtensionPrefix[0] = byte; consumeByte(insn, &insn->vectorExtensionPrefix[1]); consumeByte(insn, &insn->vectorExtensionPrefix[2]); /* We simulate the REX prefix for simplicity's sake */ if (insn->mode == MODE_64BIT) insn->rexPrefix = 0x40 | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0); switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { default: break; case VEX_PREFIX_66: insn->hasOpSize = true; break; } // dbgprintf(insn, "Found XOP prefix 0x%hhx 0x%hhx 0x%hhx", // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], // insn->vectorExtensionPrefix[2]); } } else if (isREX(insn, byte)) { if (lookAtByte(insn, &nextByte)) return -1; insn->rexPrefix = byte; // dbgprintf(insn, "Found REX prefix 0x%hhx", byte); } else unconsumeByte(insn); if (insn->mode == MODE_16BIT) { insn->registerSize = (insn->hasOpSize ? 4 : 2); insn->addressSize = (insn->hasAdSize ? 4 : 2); insn->displacementSize = (insn->hasAdSize ? 4 : 2); insn->immediateSize = (insn->hasOpSize ? 4 : 2); insn->immSize = (insn->hasOpSize ? 4 : 2); } else if (insn->mode == MODE_32BIT) { insn->registerSize = (insn->hasOpSize ? 2 : 4); insn->addressSize = (insn->hasAdSize ? 2 : 4); insn->displacementSize = (insn->hasAdSize ? 2 : 4); insn->immediateSize = (insn->hasOpSize ? 2 : 4); insn->immSize = (insn->hasOpSize ? 2 : 4); } else if (insn->mode == MODE_64BIT) { if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { insn->registerSize = 8; insn->addressSize = (insn->hasAdSize ? 4 : 8); insn->displacementSize = 4; insn->immediateSize = 4; insn->immSize = 4; } else { insn->registerSize = (insn->hasOpSize ? 2 : 4); insn->addressSize = (insn->hasAdSize ? 4 : 8); insn->displacementSize = (insn->hasOpSize ? 2 : 4); insn->immediateSize = (insn->hasOpSize ? 2 : 4); insn->immSize = (insn->hasOpSize ? 4 : 8); } } return 0; } static int readModRM(struct InternalInstruction* insn); /* * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of * extended or escape opcodes). * * @param insn - The instruction whose opcode is to be read. * @return - 0 if the opcode could be read successfully; nonzero otherwise. */ static int readOpcode(struct InternalInstruction* insn) { uint8_t current; // dbgprintf(insn, "readOpcode()"); insn->opcodeType = ONEBYTE; if (insn->vectorExtensionType == TYPE_EVEX) { switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { default: // dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)", // mmFromEVEX2of4(insn->vectorExtensionPrefix[1])); return -1; case VEX_LOB_0F: insn->opcodeType = TWOBYTE; return consumeByte(insn, &insn->opcode); case VEX_LOB_0F38: insn->opcodeType = THREEBYTE_38; return consumeByte(insn, &insn->opcode); case VEX_LOB_0F3A: insn->opcodeType = THREEBYTE_3A; return consumeByte(insn, &insn->opcode); } } else if (insn->vectorExtensionType == TYPE_VEX_3B) { switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { default: // dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", // mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); return -1; case VEX_LOB_0F: //insn->twoByteEscape = 0x0f; insn->opcodeType = TWOBYTE; return consumeByte(insn, &insn->opcode); case VEX_LOB_0F38: //insn->twoByteEscape = 0x0f; insn->opcodeType = THREEBYTE_38; return consumeByte(insn, &insn->opcode); case VEX_LOB_0F3A: //insn->twoByteEscape = 0x0f; insn->opcodeType = THREEBYTE_3A; return consumeByte(insn, &insn->opcode); } } else if (insn->vectorExtensionType == TYPE_VEX_2B) { //insn->twoByteEscape = 0x0f; insn->opcodeType = TWOBYTE; return consumeByte(insn, &insn->opcode); } else if (insn->vectorExtensionType == TYPE_XOP) { switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) { default: // dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", // mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); return -1; case XOP_MAP_SELECT_8: insn->opcodeType = XOP8_MAP; return consumeByte(insn, &insn->opcode); case XOP_MAP_SELECT_9: insn->opcodeType = XOP9_MAP; return consumeByte(insn, &insn->opcode); case XOP_MAP_SELECT_A: insn->opcodeType = XOPA_MAP; return consumeByte(insn, &insn->opcode); } } if (consumeByte(insn, ¤t)) return -1; // save this first byte for MOVcr, MOVdr, MOVrc, MOVrd insn->firstByte = current; if (current == 0x0f) { // dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current); insn->twoByteEscape = current; if (consumeByte(insn, ¤t)) return -1; if (current == 0x38) { // dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); if (consumeByte(insn, ¤t)) return -1; insn->opcodeType = THREEBYTE_38; } else if (current == 0x3a) { // dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); if (consumeByte(insn, ¤t)) return -1; insn->opcodeType = THREEBYTE_3A; } else if (current == 0x0f) { // dbgprintf(insn, "Found a 3dnow escape prefix (0x%hhx)", current); // Consume operands before the opcode to comply with the 3DNow encoding if (readModRM(insn)) return -1; if (consumeByte(insn, ¤t)) return -1; insn->opcodeType = THREEDNOW_MAP; } else { // dbgprintf(insn, "Didn't find a three-byte escape prefix"); insn->opcodeType = TWOBYTE; } } else if (insn->mandatoryPrefix) // The opcode with mandatory prefix must start with opcode escape. // If not it's legacy repeat prefix insn->mandatoryPrefix = 0; /* * At this point we have consumed the full opcode. * Anything we consume from here on must be unconsumed. */ insn->opcode = current; return 0; } // Hacky for FEMMS #define GET_INSTRINFO_ENUM #ifndef CAPSTONE_X86_REDUCE #include "X86GenInstrInfo.inc" #else #include "X86GenInstrInfo_reduce.inc" #endif /* * getIDWithAttrMask - Determines the ID of an instruction, consuming * the ModR/M byte as appropriate for extended and escape opcodes, * and using a supplied attribute mask. * * @param instructionID - A pointer whose target is filled in with the ID of the * instruction. * @param insn - The instruction whose ID is to be determined. * @param attrMask - The attribute mask to search. * @return - 0 if the ModR/M could be read when needed or was not * needed; nonzero otherwise. */ static int getIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction* insn, uint16_t attrMask) { bool hasModRMExtension; InstructionContext instructionClass = contextForAttrs(attrMask); hasModRMExtension = modRMRequired(insn->opcodeType, instructionClass, insn->opcode); if (hasModRMExtension) { if (readModRM(insn)) return -1; *instructionID = decode(insn->opcodeType, instructionClass, insn->opcode, insn->modRM); } else { *instructionID = decode(insn->opcodeType, instructionClass, insn->opcode, 0); } return 0; } /* * is16BitEquivalent - Determines whether two instruction names refer to * equivalent instructions but one is 16-bit whereas the other is not. * * @param orig - The instruction ID that is not 16-bit * @param equiv - The instruction ID that is 16-bit */ static bool is16BitEquivalent(unsigned orig, unsigned equiv) { size_t i; uint16_t idx; if ((idx = x86_16_bit_eq_lookup[orig]) != 0) { for (i = idx - 1; i < ARR_SIZE(x86_16_bit_eq_tbl) && x86_16_bit_eq_tbl[i].first == orig; i++) { if (x86_16_bit_eq_tbl[i].second == equiv) return true; } } return false; } /* * is64Bit - Determines whether this instruction is a 64-bit instruction. * * @param name - The instruction that is not 16-bit */ static bool is64Bit(uint16_t id) { unsigned int i = find_insn(id); if (i != -1) { return insns[i].is64bit; } // not found?? return false; } /* * getID - Determines the ID of an instruction, consuming the ModR/M byte as * appropriate for extended and escape opcodes. Determines the attributes and * context for the instruction before doing so. * * @param insn - The instruction whose ID is to be determined. * @return - 0 if the ModR/M could be read when needed or was not needed; * nonzero otherwise. */ static int getID(struct InternalInstruction *insn) { uint16_t attrMask; uint16_t instructionID; attrMask = ATTR_NONE; if (insn->mode == MODE_64BIT) attrMask |= ATTR_64BIT; if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) { attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX; if (insn->vectorExtensionType == TYPE_EVEX) { switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { case VEX_PREFIX_66: attrMask |= ATTR_OPSIZE; break; case VEX_PREFIX_F3: attrMask |= ATTR_XS; break; case VEX_PREFIX_F2: attrMask |= ATTR_XD; break; } if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXKZ; if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXB; if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXK; if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXL; if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXL2; } else if (insn->vectorExtensionType == TYPE_VEX_3B) { switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { case VEX_PREFIX_66: attrMask |= ATTR_OPSIZE; break; case VEX_PREFIX_F3: attrMask |= ATTR_XS; break; case VEX_PREFIX_F2: attrMask |= ATTR_XD; break; } if (lFromVEX3of3(insn->vectorExtensionPrefix[2])) attrMask |= ATTR_VEXL; } else if (insn->vectorExtensionType == TYPE_VEX_2B) { switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { case VEX_PREFIX_66: attrMask |= ATTR_OPSIZE; break; case VEX_PREFIX_F3: attrMask |= ATTR_XS; break; case VEX_PREFIX_F2: attrMask |= ATTR_XD; break; } if (lFromVEX2of2(insn->vectorExtensionPrefix[1])) attrMask |= ATTR_VEXL; } else if (insn->vectorExtensionType == TYPE_XOP) { switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { case VEX_PREFIX_66: attrMask |= ATTR_OPSIZE; break; case VEX_PREFIX_F3: attrMask |= ATTR_XS; break; case VEX_PREFIX_F2: attrMask |= ATTR_XD; break; } if (lFromXOP3of3(insn->vectorExtensionPrefix[2])) attrMask |= ATTR_VEXL; } else { return -1; } } else if (!insn->mandatoryPrefix) { // If we don't have mandatory prefix we should use legacy prefixes here if (insn->hasOpSize && (insn->mode != MODE_16BIT)) attrMask |= ATTR_OPSIZE; if (insn->hasAdSize) attrMask |= ATTR_ADSIZE; if (insn->opcodeType == ONEBYTE) { if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90)) // Special support for PAUSE attrMask |= ATTR_XS; } else { if (insn->repeatPrefix == 0xf2) attrMask |= ATTR_XD; else if (insn->repeatPrefix == 0xf3) attrMask |= ATTR_XS; } } else { switch (insn->mandatoryPrefix) { case 0xf2: attrMask |= ATTR_XD; break; case 0xf3: attrMask |= ATTR_XS; break; case 0x66: if (insn->mode != MODE_16BIT) attrMask |= ATTR_OPSIZE; break; case 0x67: attrMask |= ATTR_ADSIZE; break; } } if (insn->rexPrefix & 0x08) { attrMask |= ATTR_REXW; attrMask &= ~ATTR_ADSIZE; } /* * JCXZ/JECXZ need special handling for 16-bit mode because the meaning * of the AdSize prefix is inverted w.r.t. 32-bit mode. */ if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE && insn->opcode == 0xE3) attrMask ^= ATTR_ADSIZE; /* * In 64-bit mode all f64 superscripted opcodes ignore opcode size prefix * CALL/JMP/JCC instructions need to ignore 0x66 and consume 4 bytes */ if ((insn->mode == MODE_64BIT) && insn->hasOpSize) { switch (insn->opcode) { case 0xE8: case 0xE9: // Take care of psubsb and other mmx instructions. if (insn->opcodeType == ONEBYTE) { attrMask ^= ATTR_OPSIZE; insn->immediateSize = 4; insn->displacementSize = 4; } break; case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: case 0x89: case 0x8A: case 0x8B: case 0x8C: case 0x8D: case 0x8E: case 0x8F: // Take care of lea and three byte ops. if (insn->opcodeType == TWOBYTE) { attrMask ^= ATTR_OPSIZE; insn->immediateSize = 4; insn->displacementSize = 4; } break; } } if (getIDWithAttrMask(&instructionID, insn, attrMask)) { return -1; } /* The following clauses compensate for limitations of the tables. */ if (insn->mode != MODE_64BIT && insn->vectorExtensionType != TYPE_NO_VEX_XOP) { /* * The tables can't distinquish between cases where the W-bit is used to * select register size and cases where its a required part of the opcode. */ if ((insn->vectorExtensionType == TYPE_EVEX && wFromEVEX3of4(insn->vectorExtensionPrefix[2])) || (insn->vectorExtensionType == TYPE_VEX_3B && wFromVEX3of3(insn->vectorExtensionPrefix[2])) || (insn->vectorExtensionType == TYPE_XOP && wFromXOP3of3(insn->vectorExtensionPrefix[2]))) { uint16_t instructionIDWithREXW; if (getIDWithAttrMask(&instructionIDWithREXW, insn, attrMask | ATTR_REXW)) { insn->instructionID = instructionID; insn->spec = specifierForUID(instructionID); return 0; } // If not a 64-bit instruction. Switch the opcode. if (!is64Bit(instructionIDWithREXW)) { insn->instructionID = instructionIDWithREXW; insn->spec = specifierForUID(instructionIDWithREXW); return 0; } } } /* * Absolute moves, umonitor, and movdir64b need special handling. * -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are * inverted w.r.t. * -For 32-bit mode we need to ensure the ADSIZE prefix is observed in * any position. */ if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) || (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) || (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) { /* Make sure we observed the prefixes in any position. */ if (insn->hasAdSize) attrMask |= ATTR_ADSIZE; if (insn->hasOpSize) attrMask |= ATTR_OPSIZE; /* In 16-bit, invert the attributes. */ if (insn->mode == MODE_16BIT) { attrMask ^= ATTR_ADSIZE; /* The OpSize attribute is only valid with the absolute moves. */ if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) attrMask ^= ATTR_OPSIZE; } if (getIDWithAttrMask(&instructionID, insn, attrMask)) { return -1; } insn->instructionID = instructionID; insn->spec = specifierForUID(instructionID); return 0; } if ((insn->mode == MODE_16BIT || insn->hasOpSize) && !(attrMask & ATTR_OPSIZE)) { /* * The instruction tables make no distinction between instructions that * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a * particular spot (i.e., many MMX operations). In general we're * conservative, but in the specific case where OpSize is present but not * in the right place we check if there's a 16-bit operation. */ const struct InstructionSpecifier *spec; uint16_t instructionIDWithOpsize; spec = specifierForUID(instructionID); if (getIDWithAttrMask(&instructionIDWithOpsize, insn, attrMask | ATTR_OPSIZE)) { /* * ModRM required with OpSize but not present; give up and return version * without OpSize set */ insn->instructionID = instructionID; insn->spec = spec; return 0; } if (is16BitEquivalent(instructionID, instructionIDWithOpsize) && (insn->mode == MODE_16BIT) ^ insn->hasOpSize) { insn->instructionID = instructionIDWithOpsize; insn->spec = specifierForUID(instructionIDWithOpsize); } else { insn->instructionID = instructionID; insn->spec = spec; } return 0; } if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && insn->rexPrefix & 0x01) { /* * NOOP shouldn't decode as NOOP if REX.b is set. Instead * it should decode as XCHG %r8, %eax. */ const struct InstructionSpecifier *spec; uint16_t instructionIDWithNewOpcode; const struct InstructionSpecifier *specWithNewOpcode; spec = specifierForUID(instructionID); /* Borrow opcode from one of the other XCHGar opcodes */ insn->opcode = 0x91; if (getIDWithAttrMask(&instructionIDWithNewOpcode, insn, attrMask)) { insn->opcode = 0x90; insn->instructionID = instructionID; insn->spec = spec; return 0; } specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode); /* Change back */ insn->opcode = 0x90; insn->instructionID = instructionIDWithNewOpcode; insn->spec = specWithNewOpcode; return 0; } insn->instructionID = instructionID; insn->spec = specifierForUID(insn->instructionID); return 0; } /* * readSIB - Consumes the SIB byte to determine addressing information for an * instruction. * * @param insn - The instruction whose SIB byte is to be read. * @return - 0 if the SIB byte was successfully read; nonzero otherwise. */ static int readSIB(struct InternalInstruction* insn) { SIBBase sibBaseBase = SIB_BASE_NONE; uint8_t index, base; // dbgprintf(insn, "readSIB()"); if (insn->consumedSIB) return 0; insn->consumedSIB = true; switch (insn->addressSize) { case 2: // dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode"); return -1; case 4: insn->sibIndexBase = SIB_INDEX_EAX; sibBaseBase = SIB_BASE_EAX; break; case 8: insn->sibIndexBase = SIB_INDEX_RAX; sibBaseBase = SIB_BASE_RAX; break; } if (consumeByte(insn, &insn->sib)) return -1; index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); if (index == 0x4) { insn->sibIndex = SIB_INDEX_NONE; } else { insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index); } insn->sibScale = 1 << scaleFromSIB(insn->sib); base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); switch (base) { case 0x5: case 0xd: switch (modFromModRM(insn->modRM)) { case 0x0: insn->eaDisplacement = EA_DISP_32; insn->sibBase = SIB_BASE_NONE; break; case 0x1: insn->eaDisplacement = EA_DISP_8; insn->sibBase = (SIBBase)(sibBaseBase + base); break; case 0x2: insn->eaDisplacement = EA_DISP_32; insn->sibBase = (SIBBase)(sibBaseBase + base); break; case 0x3: // debug("Cannot have Mod = 0b11 and a SIB byte"); return -1; } break; default: insn->sibBase = (SIBBase)(sibBaseBase + base); break; } return 0; } /* * readDisplacement - Consumes the displacement of an instruction. * * @param insn - The instruction whose displacement is to be read. * @return - 0 if the displacement byte was successfully read; nonzero * otherwise. */ static int readDisplacement(struct InternalInstruction* insn) { int8_t d8; int16_t d16; int32_t d32; // dbgprintf(insn, "readDisplacement()"); if (insn->consumedDisplacement) return 0; insn->consumedDisplacement = true; insn->displacementOffset = insn->readerCursor - insn->startLocation; switch (insn->eaDisplacement) { case EA_DISP_NONE: insn->consumedDisplacement = false; break; case EA_DISP_8: if (consumeInt8(insn, &d8)) return -1; insn->displacement = d8; break; case EA_DISP_16: if (consumeInt16(insn, &d16)) return -1; insn->displacement = d16; break; case EA_DISP_32: if (consumeInt32(insn, &d32)) return -1; insn->displacement = d32; break; } return 0; } /* * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and * displacement) for an instruction and interprets it. * * @param insn - The instruction whose addressing information is to be read. * @return - 0 if the information was successfully read; nonzero otherwise. */ static int readModRM(struct InternalInstruction* insn) { uint8_t mod, rm, reg, evexrm; // dbgprintf(insn, "readModRM()"); if (insn->consumedModRM) return 0; insn->modRMOffset = (uint8_t)(insn->readerCursor - insn->startLocation); if (consumeByte(insn, &insn->modRM)) return -1; insn->consumedModRM = true; // save original ModRM for later reference insn->orgModRM = insn->modRM; // handle MOVcr, MOVdr, MOVrc, MOVrd by pretending they have MRM.mod = 3 if ((insn->firstByte == 0x0f && insn->opcodeType == TWOBYTE) && (insn->opcode >= 0x20 && insn->opcode <= 0x23 )) insn->modRM |= 0xC0; mod = modFromModRM(insn->modRM); rm = rmFromModRM(insn->modRM); reg = regFromModRM(insn->modRM); /* * This goes by insn->registerSize to pick the correct register, which messes * up if we're using (say) XMM or 8-bit register operands. That gets fixed in * fixupReg(). */ switch (insn->registerSize) { case 2: insn->regBase = MODRM_REG_AX; insn->eaRegBase = EA_REG_AX; break; case 4: insn->regBase = MODRM_REG_EAX; insn->eaRegBase = EA_REG_EAX; break; case 8: insn->regBase = MODRM_REG_RAX; insn->eaRegBase = EA_REG_RAX; break; } reg |= rFromREX(insn->rexPrefix) << 3; rm |= bFromREX(insn->rexPrefix) << 3; evexrm = 0; if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) { reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; evexrm = xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; } insn->reg = (Reg)(insn->regBase + reg); switch (insn->addressSize) { case 2: { EABase eaBaseBase = EA_BASE_BX_SI; switch (mod) { case 0x0: if (rm == 0x6) { insn->eaBase = EA_BASE_NONE; insn->eaDisplacement = EA_DISP_16; if (readDisplacement(insn)) return -1; } else { insn->eaBase = (EABase)(eaBaseBase + rm); insn->eaDisplacement = EA_DISP_NONE; } break; case 0x1: insn->eaBase = (EABase)(eaBaseBase + rm); insn->eaDisplacement = EA_DISP_8; insn->displacementSize = 1; if (readDisplacement(insn)) return -1; break; case 0x2: insn->eaBase = (EABase)(eaBaseBase + rm); insn->eaDisplacement = EA_DISP_16; if (readDisplacement(insn)) return -1; break; case 0x3: insn->eaBase = (EABase)(insn->eaRegBase + rm); if (readDisplacement(insn)) return -1; break; } break; } case 4: case 8: { EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); switch (mod) { default: break; case 0x0: insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */ // In determining whether RIP-relative mode is used (rm=5), // or whether a SIB byte is present (rm=4), // the extension bits (REX.b and EVEX.x) are ignored. switch (rm & 7) { case 0x4: // SIB byte is present insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64); if (readSIB(insn) || readDisplacement(insn)) return -1; break; case 0x5: // RIP-relative insn->eaBase = EA_BASE_NONE; insn->eaDisplacement = EA_DISP_32; if (readDisplacement(insn)) return -1; break; default: insn->eaBase = (EABase)(eaBaseBase + rm); break; } break; case 0x1: insn->displacementSize = 1; /* FALLTHROUGH */ case 0x2: insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); switch (rm & 7) { case 0x4: // SIB byte is present insn->eaBase = EA_BASE_sib; if (readSIB(insn) || readDisplacement(insn)) return -1; break; default: insn->eaBase = (EABase)(eaBaseBase + rm); if (readDisplacement(insn)) return -1; break; } break; case 0x3: insn->eaDisplacement = EA_DISP_NONE; insn->eaBase = (EABase)(insn->eaRegBase + rm + evexrm); break; } break; } } /* switch (insn->addressSize) */ return 0; } #define GENERIC_FIXUP_FUNC(name, base, prefix, mask) \ static uint16_t name(struct InternalInstruction *insn, \ OperandType type, \ uint8_t index, \ uint8_t *valid) { \ *valid = 1; \ switch (type) { \ default: \ *valid = 0; \ return 0; \ case TYPE_Rv: \ return base + index; \ case TYPE_R8: \ index &= mask; \ if (index > 0xf) \ *valid = 0; \ if (insn->rexPrefix && \ index >= 4 && index <= 7) { \ return prefix##_SPL + (index - 4); \ } else { \ return prefix##_AL + index; \ } \ case TYPE_R16: \ index &= mask; \ if (index > 0xf) \ *valid = 0; \ return prefix##_AX + index; \ case TYPE_R32: \ index &= mask; \ if (index > 0xf) \ *valid = 0; \ return prefix##_EAX + index; \ case TYPE_R64: \ index &= mask; \ if (index > 0xf) \ *valid = 0; \ return prefix##_RAX + index; \ case TYPE_ZMM: \ return prefix##_ZMM0 + index; \ case TYPE_YMM: \ return prefix##_YMM0 + index; \ case TYPE_XMM: \ return prefix##_XMM0 + index; \ case TYPE_VK: \ index &= 0xf; \ if (index > 7) \ *valid = 0; \ return prefix##_K0 + index; \ case TYPE_MM64: \ return prefix##_MM0 + (index & 0x7); \ case TYPE_SEGMENTREG: \ if ((index & 7) > 5) \ *valid = 0; \ return prefix##_ES + (index & 7); \ case TYPE_DEBUGREG: \ return prefix##_DR0 + index; \ case TYPE_CONTROLREG: \ return prefix##_CR0 + index; \ case TYPE_BNDR: \ if (index > 3) \ *valid = 0; \ return prefix##_BND0 + index; \ case TYPE_MVSIBX: \ return prefix##_XMM0 + index; \ case TYPE_MVSIBY: \ return prefix##_YMM0 + index; \ case TYPE_MVSIBZ: \ return prefix##_ZMM0 + index; \ } \ } /* * fixup*Value - Consults an operand type to determine the meaning of the * reg or R/M field. If the operand is an XMM operand, for example, an * operand would be XMM0 instead of AX, which readModRM() would otherwise * misinterpret it as. * * @param insn - The instruction containing the operand. * @param type - The operand type. * @param index - The existing value of the field as reported by readModRM(). * @param valid - The address of a uint8_t. The target is set to 1 if the * field is valid for the register class; 0 if not. * @return - The proper value. */ GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG, 0x1f) GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG, 0xf) /* * fixupReg - Consults an operand specifier to determine which of the * fixup*Value functions to use in correcting readModRM()'ss interpretation. * * @param insn - See fixup*Value(). * @param op - The operand specifier. * @return - 0 if fixup was successful; -1 if the register returned was * invalid for its class. */ static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op) { uint8_t valid; switch ((OperandEncoding)op->encoding) { default: // debug("Expected a REG or R/M encoding in fixupReg"); return -1; case ENCODING_VVVV: insn->vvvv = (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid); if (!valid) return -1; break; case ENCODING_REG: insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type, insn->reg - insn->regBase, &valid); if (!valid) return -1; break; CASE_ENCODING_RM: if (insn->eaBase >= insn->eaRegBase) { insn->eaBase = (EABase)fixupRMValue(insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid); if (!valid) return -1; } break; } return 0; } /* * readOpcodeRegister - Reads an operand from the opcode field of an * instruction and interprets it appropriately given the operand width. * Handles AddRegFrm instructions. * * @param insn - the instruction whose opcode field is to be read. * @param size - The width (in bytes) of the register being specified. * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means * RAX. * @return - 0 on success; nonzero otherwise. */ static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) { if (size == 0) size = insn->registerSize; switch (size) { case 1: insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 && insn->opcodeRegister < MODRM_REG_AL + 0x8) { insn->opcodeRegister = (Reg)(MODRM_REG_SPL + (insn->opcodeRegister - MODRM_REG_AL - 4)); } break; case 2: insn->opcodeRegister = (Reg)(MODRM_REG_AX + ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); break; case 4: insn->opcodeRegister = (Reg)(MODRM_REG_EAX + ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); break; case 8: insn->opcodeRegister = (Reg)(MODRM_REG_RAX + ((bFromREX(insn->rexPrefix) << 3) | (insn->opcode & 7))); break; } return 0; } /* * readImmediate - Consumes an immediate operand from an instruction, given the * desired operand size. * * @param insn - The instruction whose operand is to be read. * @param size - The width (in bytes) of the operand. * @return - 0 if the immediate was successfully consumed; nonzero * otherwise. */ static int readImmediate(struct InternalInstruction* insn, uint8_t size) { uint8_t imm8; uint16_t imm16; uint32_t imm32; uint64_t imm64; if (insn->numImmediatesConsumed == 2) { // debug("Already consumed two immediates"); return -1; } if (size == 0) size = insn->immediateSize; else insn->immediateSize = size; insn->immediateOffset = insn->readerCursor - insn->startLocation; switch (size) { case 1: if (consumeByte(insn, &imm8)) return -1; insn->immediates[insn->numImmediatesConsumed] = imm8; break; case 2: if (consumeUInt16(insn, &imm16)) return -1; insn->immediates[insn->numImmediatesConsumed] = imm16; break; case 4: if (consumeUInt32(insn, &imm32)) return -1; insn->immediates[insn->numImmediatesConsumed] = imm32; break; case 8: if (consumeUInt64(insn, &imm64)) return -1; insn->immediates[insn->numImmediatesConsumed] = imm64; break; } insn->numImmediatesConsumed++; return 0; } /* * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix. * * @param insn - The instruction whose operand is to be read. * @return - 0 if the vvvv was successfully consumed; nonzero * otherwise. */ static int readVVVV(struct InternalInstruction* insn) { int vvvv; if (insn->vectorExtensionType == TYPE_EVEX) vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); else if (insn->vectorExtensionType == TYPE_VEX_3B) vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); else if (insn->vectorExtensionType == TYPE_VEX_2B) vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); else if (insn->vectorExtensionType == TYPE_XOP) vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); else return -1; if (insn->mode != MODE_64BIT) vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later. insn->vvvv = (Reg)vvvv; return 0; } /* * readMaskRegister - Reads an mask register from the opcode field of an * instruction. * * @param insn - The instruction whose opcode field is to be read. * @return - 0 on success; nonzero otherwise. */ static int readMaskRegister(struct InternalInstruction* insn) { if (insn->vectorExtensionType != TYPE_EVEX) return -1; insn->writemask = (Reg)(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])); return 0; } /* * readOperands - Consults the specifier for an instruction and consumes all * operands for that instruction, interpreting them as it goes. * * @param insn - The instruction whose operands are to be read and interpreted. * @return - 0 if all operands could be read; nonzero otherwise. */ static int readOperands(struct InternalInstruction* insn) { int hasVVVV, needVVVV; int sawRegImm = 0; int i; /* If non-zero vvvv specified, need to make sure one of the operands uses it. */ hasVVVV = !readVVVV(insn); needVVVV = hasVVVV && (insn->vvvv != 0); for (i = 0; i < X86_MAX_OPERANDS; ++i) { const OperandSpecifier *op = &x86OperandSets[insn->spec->operands][i]; switch (op->encoding) { case ENCODING_NONE: case ENCODING_SI: case ENCODING_DI: break; CASE_ENCODING_VSIB: // VSIB can use the V2 bit so check only the other bits. if (needVVVV) needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); if (readModRM(insn)) return -1; // Reject if SIB wasn't used. if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64) return -1; // If sibIndex was set to SIB_INDEX_NONE, index offset is 4. if (insn->sibIndex == SIB_INDEX_NONE) insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4); // If EVEX.v2 is set this is one of the 16-31 registers. if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && v2FromEVEX4of4(insn->vectorExtensionPrefix[3])) insn->sibIndex = (SIBIndex)(insn->sibIndex + 16); // Adjust the index register to the correct size. switch (op->type) { default: // debug("Unhandled VSIB index type"); return -1; case TYPE_MVSIBX: insn->sibIndex = (SIBIndex)(SIB_INDEX_XMM0 + (insn->sibIndex - insn->sibIndexBase)); break; case TYPE_MVSIBY: insn->sibIndex = (SIBIndex)(SIB_INDEX_YMM0 + (insn->sibIndex - insn->sibIndexBase)); break; case TYPE_MVSIBZ: insn->sibIndex = (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase)); break; } // Apply the AVX512 compressed displacement scaling factor. if (op->encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) insn->displacement *= 1 << (op->encoding - ENCODING_VSIB); break; case ENCODING_REG: CASE_ENCODING_RM: if (readModRM(insn)) return -1; if (fixupReg(insn, op)) return -1; // Apply the AVX512 compressed displacement scaling factor. if (op->encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) insn->displacement *= 1 << (op->encoding - ENCODING_RM); break; case ENCODING_IB: if (sawRegImm) { /* Saw a register immediate so don't read again and instead split the previous immediate. FIXME: This is a hack. */ insn->immediates[insn->numImmediatesConsumed] = insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; ++insn->numImmediatesConsumed; break; } if (readImmediate(insn, 1)) return -1; if (op->type == TYPE_XMM || op->type == TYPE_YMM) sawRegImm = 1; break; case ENCODING_IW: if (readImmediate(insn, 2)) return -1; break; case ENCODING_ID: if (readImmediate(insn, 4)) return -1; break; case ENCODING_IO: if (readImmediate(insn, 8)) return -1; break; case ENCODING_Iv: if (readImmediate(insn, insn->immediateSize)) return -1; break; case ENCODING_Ia: if (readImmediate(insn, insn->addressSize)) return -1; break; case ENCODING_IRC: insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) | lFromEVEX4of4(insn->vectorExtensionPrefix[3]); break; case ENCODING_RB: if (readOpcodeRegister(insn, 1)) return -1; break; case ENCODING_RW: if (readOpcodeRegister(insn, 2)) return -1; break; case ENCODING_RD: if (readOpcodeRegister(insn, 4)) return -1; break; case ENCODING_RO: if (readOpcodeRegister(insn, 8)) return -1; break; case ENCODING_Rv: if (readOpcodeRegister(insn, 0)) return -1; break; case ENCODING_FP: break; case ENCODING_VVVV: if (!hasVVVV) return -1; needVVVV = 0; /* Mark that we have found a VVVV operand. */ if (insn->mode != MODE_64BIT) insn->vvvv = (Reg)(insn->vvvv & 0x7); if (fixupReg(insn, op)) return -1; break; case ENCODING_WRITEMASK: if (readMaskRegister(insn)) return -1; break; case ENCODING_DUP: break; default: // dbgprintf(insn, "Encountered an operand with an unknown encoding."); return -1; } } /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */ if (needVVVV) return -1; return 0; } // return True if instruction is illegal to use with prefixes // This also check & fix the isPrefixNN when a prefix is irrelevant. static bool checkPrefix(struct InternalInstruction *insn) { // LOCK prefix if (insn->hasLockPrefix) { switch(insn->instructionID) { default: // invalid LOCK return true; // nop dword [rax] case X86_NOOPL: // DEC case X86_DEC16m: case X86_DEC32m: case X86_DEC64m: case X86_DEC8m: // ADC case X86_ADC16mi: case X86_ADC16mi8: case X86_ADC16mr: case X86_ADC32mi: case X86_ADC32mi8: case X86_ADC32mr: case X86_ADC64mi32: case X86_ADC64mi8: case X86_ADC64mr: case X86_ADC8mi: case X86_ADC8mi8: case X86_ADC8mr: case X86_ADC8rm: case X86_ADC16rm: case X86_ADC32rm: case X86_ADC64rm: // ADD case X86_ADD16mi: case X86_ADD16mi8: case X86_ADD16mr: case X86_ADD32mi: case X86_ADD32mi8: case X86_ADD32mr: case X86_ADD64mi32: case X86_ADD64mi8: case X86_ADD64mr: case X86_ADD8mi: case X86_ADD8mi8: case X86_ADD8mr: case X86_ADD8rm: case X86_ADD16rm: case X86_ADD32rm: case X86_ADD64rm: // AND case X86_AND16mi: case X86_AND16mi8: case X86_AND16mr: case X86_AND32mi: case X86_AND32mi8: case X86_AND32mr: case X86_AND64mi32: case X86_AND64mi8: case X86_AND64mr: case X86_AND8mi: case X86_AND8mi8: case X86_AND8mr: case X86_AND8rm: case X86_AND16rm: case X86_AND32rm: case X86_AND64rm: // BTC case X86_BTC16mi8: case X86_BTC16mr: case X86_BTC32mi8: case X86_BTC32mr: case X86_BTC64mi8: case X86_BTC64mr: // BTR case X86_BTR16mi8: case X86_BTR16mr: case X86_BTR32mi8: case X86_BTR32mr: case X86_BTR64mi8: case X86_BTR64mr: // BTS case X86_BTS16mi8: case X86_BTS16mr: case X86_BTS32mi8: case X86_BTS32mr: case X86_BTS64mi8: case X86_BTS64mr: // CMPXCHG case X86_CMPXCHG16B: case X86_CMPXCHG16rm: case X86_CMPXCHG32rm: case X86_CMPXCHG64rm: case X86_CMPXCHG8rm: case X86_CMPXCHG8B: // INC case X86_INC16m: case X86_INC32m: case X86_INC64m: case X86_INC8m: // NEG case X86_NEG16m: case X86_NEG32m: case X86_NEG64m: case X86_NEG8m: // NOT case X86_NOT16m: case X86_NOT32m: case X86_NOT64m: case X86_NOT8m: // OR case X86_OR16mi: case X86_OR16mi8: case X86_OR16mr: case X86_OR32mi: case X86_OR32mi8: case X86_OR32mr: case X86_OR64mi32: case X86_OR64mi8: case X86_OR64mr: case X86_OR8mi8: case X86_OR8mi: case X86_OR8mr: case X86_OR8rm: case X86_OR16rm: case X86_OR32rm: case X86_OR64rm: // SBB case X86_SBB16mi: case X86_SBB16mi8: case X86_SBB16mr: case X86_SBB32mi: case X86_SBB32mi8: case X86_SBB32mr: case X86_SBB64mi32: case X86_SBB64mi8: case X86_SBB64mr: case X86_SBB8mi: case X86_SBB8mi8: case X86_SBB8mr: // SUB case X86_SUB16mi: case X86_SUB16mi8: case X86_SUB16mr: case X86_SUB32mi: case X86_SUB32mi8: case X86_SUB32mr: case X86_SUB64mi32: case X86_SUB64mi8: case X86_SUB64mr: case X86_SUB8mi8: case X86_SUB8mi: case X86_SUB8mr: case X86_SUB8rm: case X86_SUB16rm: case X86_SUB32rm: case X86_SUB64rm: // XADD case X86_XADD16rm: case X86_XADD32rm: case X86_XADD64rm: case X86_XADD8rm: // XCHG case X86_XCHG16rm: case X86_XCHG32rm: case X86_XCHG64rm: case X86_XCHG8rm: // XOR case X86_XOR16mi: case X86_XOR16mi8: case X86_XOR16mr: case X86_XOR32mi: case X86_XOR32mi8: case X86_XOR32mr: case X86_XOR64mi32: case X86_XOR64mi8: case X86_XOR64mr: case X86_XOR8mi8: case X86_XOR8mi: case X86_XOR8mr: case X86_XOR8rm: case X86_XOR16rm: case X86_XOR32rm: case X86_XOR64rm: // this instruction can be used with LOCK prefix return false; } } #if 0 // REPNE prefix if (insn->repeatPrefix) { // 0xf2 can be a part of instruction encoding, but not really a prefix. // In such a case, clear it. if (insn->twoByteEscape == 0x0f) { insn->prefix0 = 0; } } #endif // no invalid prefixes return false; } /* * decodeInstruction - Reads and interprets a full instruction provided by the * user. * * @param insn - A pointer to the instruction to be populated. Must be * pre-allocated. * @param reader - The function to be used to read the instruction's bytes. * @param readerArg - A generic argument to be passed to the reader to store * any internal state. * @param startLoc - The address (in the reader's address space) of the first * byte in the instruction. * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to * decode the instruction in. * @return - 0 if instruction is valid; nonzero if not. */ int decodeInstruction(struct InternalInstruction *insn, byteReader_t reader, const void *readerArg, uint64_t startLoc, DisassemblerMode mode) { insn->reader = reader; insn->readerArg = readerArg; insn->startLocation = startLoc; insn->readerCursor = startLoc; insn->mode = mode; insn->numImmediatesConsumed = 0; if (readPrefixes(insn) || readOpcode(insn) || getID(insn) || insn->instructionID == 0 || checkPrefix(insn) || readOperands(insn)) return -1; insn->length = (size_t)(insn->readerCursor - insn->startLocation); // instruction length must be <= 15 to be valid if (insn->length > 15) return -1; if (insn->operandSize == 0) insn->operandSize = insn->registerSize; insn->operands = &x86OperandSets[insn->spec->operands][0]; return 0; } #endif capstone-sys-0.15.0/capstone/arch/X86/X86DisassemblerDecoder.h000064400000000000000000000462260072674642500221010ustar 00000000000000/*===-- X86DisassemblerDecoderInternal.h - Disassembler decoder ---*- C -*-===* * * The LLVM Compiler Infrastructure * * This file is distributed under the University of Illinois Open Source * License. See LICENSE.TXT for details. * *===----------------------------------------------------------------------===* * * This file is part of the X86 Disassembler. * It contains the public interface of the instruction decoder. * Documentation for the disassembler can be found in X86Disassembler.h. * *===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_X86_DISASSEMBLERDECODER_H #define CS_X86_DISASSEMBLERDECODER_H #if defined(CAPSTONE_HAS_OSXKERNEL) #include #else #include #endif #include "X86DisassemblerDecoderCommon.h" /* * Accessor functions for various fields of an Intel instruction */ #define modFromModRM(modRM) (((modRM) & 0xc0) >> 6) #define regFromModRM(modRM) (((modRM) & 0x38) >> 3) #define rmFromModRM(modRM) ((modRM) & 0x7) #define scaleFromSIB(sib) (((sib) & 0xc0) >> 6) #define indexFromSIB(sib) (((sib) & 0x38) >> 3) #define baseFromSIB(sib) ((sib) & 0x7) #define wFromREX(rex) (((rex) & 0x8) >> 3) #define rFromREX(rex) (((rex) & 0x4) >> 2) #define xFromREX(rex) (((rex) & 0x2) >> 1) #define bFromREX(rex) ((rex) & 0x1) #define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7) #define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6) #define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5) #define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4) #define mmFromEVEX2of4(evex) ((evex) & 0x3) #define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7) #define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3) #define ppFromEVEX3of4(evex) ((evex) & 0x3) #define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7) #define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6) #define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5) #define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4) #define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3) #define aaaFromEVEX4of4(evex) ((evex) & 0x7) #define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7) #define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6) #define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5) #define mmmmmFromVEX2of3(vex) ((vex) & 0x1f) #define wFromVEX3of3(vex) (((vex) & 0x80) >> 7) #define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3) #define lFromVEX3of3(vex) (((vex) & 0x4) >> 2) #define ppFromVEX3of3(vex) ((vex) & 0x3) #define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7) #define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3) #define lFromVEX2of2(vex) (((vex) & 0x4) >> 2) #define ppFromVEX2of2(vex) ((vex) & 0x3) #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) #define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3) #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) #define ppFromXOP3of3(xop) ((xop) & 0x3) /* * These enums represent Intel registers for use by the decoder. */ #define REGS_8BIT \ ENTRY(AL) \ ENTRY(CL) \ ENTRY(DL) \ ENTRY(BL) \ ENTRY(AH) \ ENTRY(CH) \ ENTRY(DH) \ ENTRY(BH) \ ENTRY(R8B) \ ENTRY(R9B) \ ENTRY(R10B) \ ENTRY(R11B) \ ENTRY(R12B) \ ENTRY(R13B) \ ENTRY(R14B) \ ENTRY(R15B) \ ENTRY(SPL) \ ENTRY(BPL) \ ENTRY(SIL) \ ENTRY(DIL) #define EA_BASES_16BIT \ ENTRY(BX_SI) \ ENTRY(BX_DI) \ ENTRY(BP_SI) \ ENTRY(BP_DI) \ ENTRY(SI) \ ENTRY(DI) \ ENTRY(BP) \ ENTRY(BX) \ ENTRY(R8W) \ ENTRY(R9W) \ ENTRY(R10W) \ ENTRY(R11W) \ ENTRY(R12W) \ ENTRY(R13W) \ ENTRY(R14W) \ ENTRY(R15W) #define REGS_16BIT \ ENTRY(AX) \ ENTRY(CX) \ ENTRY(DX) \ ENTRY(BX) \ ENTRY(SP) \ ENTRY(BP) \ ENTRY(SI) \ ENTRY(DI) \ ENTRY(R8W) \ ENTRY(R9W) \ ENTRY(R10W) \ ENTRY(R11W) \ ENTRY(R12W) \ ENTRY(R13W) \ ENTRY(R14W) \ ENTRY(R15W) #define EA_BASES_32BIT \ ENTRY(EAX) \ ENTRY(ECX) \ ENTRY(EDX) \ ENTRY(EBX) \ ENTRY(sib) \ ENTRY(EBP) \ ENTRY(ESI) \ ENTRY(EDI) \ ENTRY(R8D) \ ENTRY(R9D) \ ENTRY(R10D) \ ENTRY(R11D) \ ENTRY(R12D) \ ENTRY(R13D) \ ENTRY(R14D) \ ENTRY(R15D) #define REGS_32BIT \ ENTRY(EAX) \ ENTRY(ECX) \ ENTRY(EDX) \ ENTRY(EBX) \ ENTRY(ESP) \ ENTRY(EBP) \ ENTRY(ESI) \ ENTRY(EDI) \ ENTRY(R8D) \ ENTRY(R9D) \ ENTRY(R10D) \ ENTRY(R11D) \ ENTRY(R12D) \ ENTRY(R13D) \ ENTRY(R14D) \ ENTRY(R15D) #define EA_BASES_64BIT \ ENTRY(RAX) \ ENTRY(RCX) \ ENTRY(RDX) \ ENTRY(RBX) \ ENTRY(sib64) \ ENTRY(RBP) \ ENTRY(RSI) \ ENTRY(RDI) \ ENTRY(R8) \ ENTRY(R9) \ ENTRY(R10) \ ENTRY(R11) \ ENTRY(R12) \ ENTRY(R13) \ ENTRY(R14) \ ENTRY(R15) #define REGS_64BIT \ ENTRY(RAX) \ ENTRY(RCX) \ ENTRY(RDX) \ ENTRY(RBX) \ ENTRY(RSP) \ ENTRY(RBP) \ ENTRY(RSI) \ ENTRY(RDI) \ ENTRY(R8) \ ENTRY(R9) \ ENTRY(R10) \ ENTRY(R11) \ ENTRY(R12) \ ENTRY(R13) \ ENTRY(R14) \ ENTRY(R15) #define REGS_MMX \ ENTRY(MM0) \ ENTRY(MM1) \ ENTRY(MM2) \ ENTRY(MM3) \ ENTRY(MM4) \ ENTRY(MM5) \ ENTRY(MM6) \ ENTRY(MM7) #define REGS_XMM \ ENTRY(XMM0) \ ENTRY(XMM1) \ ENTRY(XMM2) \ ENTRY(XMM3) \ ENTRY(XMM4) \ ENTRY(XMM5) \ ENTRY(XMM6) \ ENTRY(XMM7) \ ENTRY(XMM8) \ ENTRY(XMM9) \ ENTRY(XMM10) \ ENTRY(XMM11) \ ENTRY(XMM12) \ ENTRY(XMM13) \ ENTRY(XMM14) \ ENTRY(XMM15) \ ENTRY(XMM16) \ ENTRY(XMM17) \ ENTRY(XMM18) \ ENTRY(XMM19) \ ENTRY(XMM20) \ ENTRY(XMM21) \ ENTRY(XMM22) \ ENTRY(XMM23) \ ENTRY(XMM24) \ ENTRY(XMM25) \ ENTRY(XMM26) \ ENTRY(XMM27) \ ENTRY(XMM28) \ ENTRY(XMM29) \ ENTRY(XMM30) \ ENTRY(XMM31) #define REGS_YMM \ ENTRY(YMM0) \ ENTRY(YMM1) \ ENTRY(YMM2) \ ENTRY(YMM3) \ ENTRY(YMM4) \ ENTRY(YMM5) \ ENTRY(YMM6) \ ENTRY(YMM7) \ ENTRY(YMM8) \ ENTRY(YMM9) \ ENTRY(YMM10) \ ENTRY(YMM11) \ ENTRY(YMM12) \ ENTRY(YMM13) \ ENTRY(YMM14) \ ENTRY(YMM15) \ ENTRY(YMM16) \ ENTRY(YMM17) \ ENTRY(YMM18) \ ENTRY(YMM19) \ ENTRY(YMM20) \ ENTRY(YMM21) \ ENTRY(YMM22) \ ENTRY(YMM23) \ ENTRY(YMM24) \ ENTRY(YMM25) \ ENTRY(YMM26) \ ENTRY(YMM27) \ ENTRY(YMM28) \ ENTRY(YMM29) \ ENTRY(YMM30) \ ENTRY(YMM31) #define REGS_ZMM \ ENTRY(ZMM0) \ ENTRY(ZMM1) \ ENTRY(ZMM2) \ ENTRY(ZMM3) \ ENTRY(ZMM4) \ ENTRY(ZMM5) \ ENTRY(ZMM6) \ ENTRY(ZMM7) \ ENTRY(ZMM8) \ ENTRY(ZMM9) \ ENTRY(ZMM10) \ ENTRY(ZMM11) \ ENTRY(ZMM12) \ ENTRY(ZMM13) \ ENTRY(ZMM14) \ ENTRY(ZMM15) \ ENTRY(ZMM16) \ ENTRY(ZMM17) \ ENTRY(ZMM18) \ ENTRY(ZMM19) \ ENTRY(ZMM20) \ ENTRY(ZMM21) \ ENTRY(ZMM22) \ ENTRY(ZMM23) \ ENTRY(ZMM24) \ ENTRY(ZMM25) \ ENTRY(ZMM26) \ ENTRY(ZMM27) \ ENTRY(ZMM28) \ ENTRY(ZMM29) \ ENTRY(ZMM30) \ ENTRY(ZMM31) #define REGS_MASKS \ ENTRY(K0) \ ENTRY(K1) \ ENTRY(K2) \ ENTRY(K3) \ ENTRY(K4) \ ENTRY(K5) \ ENTRY(K6) \ ENTRY(K7) #define REGS_SEGMENT \ ENTRY(ES) \ ENTRY(CS) \ ENTRY(SS) \ ENTRY(DS) \ ENTRY(FS) \ ENTRY(GS) #define REGS_DEBUG \ ENTRY(DR0) \ ENTRY(DR1) \ ENTRY(DR2) \ ENTRY(DR3) \ ENTRY(DR4) \ ENTRY(DR5) \ ENTRY(DR6) \ ENTRY(DR7) \ ENTRY(DR8) \ ENTRY(DR9) \ ENTRY(DR10) \ ENTRY(DR11) \ ENTRY(DR12) \ ENTRY(DR13) \ ENTRY(DR14) \ ENTRY(DR15) #define REGS_CONTROL \ ENTRY(CR0) \ ENTRY(CR1) \ ENTRY(CR2) \ ENTRY(CR3) \ ENTRY(CR4) \ ENTRY(CR5) \ ENTRY(CR6) \ ENTRY(CR7) \ ENTRY(CR8) \ ENTRY(CR9) \ ENTRY(CR10) \ ENTRY(CR11) \ ENTRY(CR12) \ ENTRY(CR13) \ ENTRY(CR14) \ ENTRY(CR15) #define REGS_BOUND \ ENTRY(BND0) \ ENTRY(BND1) \ ENTRY(BND2) \ ENTRY(BND3) #define ALL_EA_BASES \ EA_BASES_16BIT \ EA_BASES_32BIT \ EA_BASES_64BIT #define ALL_SIB_BASES \ REGS_32BIT \ REGS_64BIT #define ALL_REGS \ REGS_8BIT \ REGS_16BIT \ REGS_32BIT \ REGS_64BIT \ REGS_MMX \ REGS_XMM \ REGS_YMM \ REGS_ZMM \ REGS_MASKS \ REGS_SEGMENT \ REGS_DEBUG \ REGS_CONTROL \ REGS_BOUND \ ENTRY(RIP) /* * EABase - All possible values of the base field for effective-address * computations, a.k.a. the Mod and R/M fields of the ModR/M byte. We * distinguish between bases (EA_BASE_*) and registers that just happen to be * referred to when Mod == 0b11 (EA_REG_*). */ typedef enum { EA_BASE_NONE, #define ENTRY(x) EA_BASE_##x, ALL_EA_BASES #undef ENTRY #define ENTRY(x) EA_REG_##x, ALL_REGS #undef ENTRY EA_max } EABase; /* * SIBIndex - All possible values of the SIB index field. * Borrows entries from ALL_EA_BASES with the special case that * sib is synonymous with NONE. * Vector SIB: index can be XMM or YMM. */ typedef enum { SIB_INDEX_NONE, #define ENTRY(x) SIB_INDEX_##x, ALL_EA_BASES REGS_XMM REGS_YMM REGS_ZMM #undef ENTRY SIB_INDEX_max } SIBIndex; /* * SIBBase - All possible values of the SIB base field. */ typedef enum { SIB_BASE_NONE, #define ENTRY(x) SIB_BASE_##x, ALL_SIB_BASES #undef ENTRY SIB_BASE_max } SIBBase; /* * EADisplacement - Possible displacement types for effective-address * computations. */ typedef enum { EA_DISP_NONE, EA_DISP_8, EA_DISP_16, EA_DISP_32 } EADisplacement; /* * Reg - All possible values of the reg field in the ModR/M byte. */ typedef enum { #define ENTRY(x) MODRM_REG_##x, ALL_REGS #undef ENTRY MODRM_REG_max } Reg; /* * SegmentOverride - All possible segment overrides. */ typedef enum { SEG_OVERRIDE_NONE, SEG_OVERRIDE_CS, SEG_OVERRIDE_SS, SEG_OVERRIDE_DS, SEG_OVERRIDE_ES, SEG_OVERRIDE_FS, SEG_OVERRIDE_GS, SEG_OVERRIDE_max } SegmentOverride; /* * VEXLeadingOpcodeByte - Possible values for the VEX.m-mmmm field */ typedef enum { VEX_LOB_0F = 0x1, VEX_LOB_0F38 = 0x2, VEX_LOB_0F3A = 0x3 } VEXLeadingOpcodeByte; typedef enum { XOP_MAP_SELECT_8 = 0x8, XOP_MAP_SELECT_9 = 0x9, XOP_MAP_SELECT_A = 0xA } XOPMapSelect; /* * VEXPrefixCode - Possible values for the VEX.pp/EVEX.pp field */ typedef enum { VEX_PREFIX_NONE = 0x0, VEX_PREFIX_66 = 0x1, VEX_PREFIX_F3 = 0x2, VEX_PREFIX_F2 = 0x3 } VEXPrefixCode; typedef enum { TYPE_NO_VEX_XOP = 0x0, TYPE_VEX_2B = 0x1, TYPE_VEX_3B = 0x2, TYPE_EVEX = 0x3, TYPE_XOP = 0x4 } VectorExtensionType; struct reader_info { const uint8_t *code; uint64_t size; uint64_t offset; }; /* * byteReader_t - Type for the byte reader that the consumer must provide to * the decoder. Reads a single byte from the instruction's address space. * @param arg - A baton that the consumer can associate with any internal * state that it needs. * @param byte - A pointer to a single byte in memory that should be set to * contain the value at address. * @param address - The address in the instruction's address space that should * be read from. * @return - -1 if the byte cannot be read for any reason; 0 otherwise. */ typedef int (*byteReader_t)(const struct reader_info *arg, uint8_t* byte, uint64_t address); /// The specification for how to extract and interpret a full instruction and /// its operands. struct InstructionSpecifier { #ifdef CAPSTONE_X86_REDUCE uint8_t operands; #else uint16_t operands; #endif }; /* * The x86 internal instruction, which is produced by the decoder. */ typedef struct InternalInstruction { // from here, all members must be initialized to ZERO to work properly uint8_t operandSize; uint8_t prefix0, prefix1, prefix2, prefix3; /* The value of the REX prefix, if present */ uint8_t rexPrefix; /* The segment override type */ SegmentOverride segmentOverride; bool consumedModRM; uint8_t orgModRM; // save original modRM because we will modify modRM /* The SIB byte, used for more complex 32- or 64-bit memory operands */ bool consumedSIB; uint8_t sib; /* The displacement, used for memory operands */ bool consumedDisplacement; int64_t displacement; /* The value of the two-byte escape prefix (usually 0x0f) */ uint8_t twoByteEscape; /* The value of the three-byte escape prefix (usually 0x38 or 0x3a) */ uint8_t threeByteEscape; /* SIB state */ SIBIndex sibIndexBase; SIBIndex sibIndex; uint8_t sibScale; SIBBase sibBase; // Embedded rounding control. uint8_t RC; uint8_t numImmediatesConsumed; /* 0xf2 or 0xf3 is xacquire or xrelease */ uint8_t xAcquireRelease; // Address-size override bool hasAdSize; // Operand-size override bool hasOpSize; // Lock prefix bool hasLockPrefix; // The repeat prefix if any uint8_t repeatPrefix; // The possible mandatory prefix uint8_t mandatoryPrefix; /* The value of the vector extension prefix(EVEX/VEX/XOP), if present */ uint8_t vectorExtensionPrefix[4]; /* Offsets from the start of the instruction to the pieces of data, which is needed to find relocation entries for adding symbolic operands */ uint8_t displacementOffset; uint8_t immediateOffset; uint8_t modRMOffset; // end-of-zero-members /* Reader interface (C) */ byteReader_t reader; /* Opaque value passed to the reader */ const void* readerArg; /* The address of the next byte to read via the reader */ uint64_t readerCursor; /* General instruction information */ /* The mode to disassemble for (64-bit, protected, real) */ DisassemblerMode mode; /* The start of the instruction, usable with the reader */ uint64_t startLocation; /* The length of the instruction, in bytes */ size_t length; /* Prefix state */ /* The type of the vector extension prefix */ VectorExtensionType vectorExtensionType; /* Sizes of various critical pieces of data, in bytes */ uint8_t registerSize; uint8_t addressSize; uint8_t displacementSize; uint8_t immediateSize; uint8_t immSize; // immediate size for X86_OP_IMM operand /* opcode state */ /* The last byte of the opcode, not counting any ModR/M extension */ uint8_t opcode; /* decode state */ /* The type of opcode, used for indexing into the array of decode tables */ OpcodeType opcodeType; /* The instruction ID, extracted from the decode table */ uint16_t instructionID; /* The specifier for the instruction, from the instruction info table */ const struct InstructionSpecifier *spec; /* state for additional bytes, consumed during operand decode. Pattern: consumed___ indicates that the byte was already consumed and does not need to be consumed again */ /* The VEX.vvvv field, which contains a third register operand for some AVX instructions */ Reg vvvv; /* The writemask for AVX-512 instructions which is contained in EVEX.aaa */ Reg writemask; /* The ModR/M byte, which contains most register operands and some portion of all memory operands */ uint8_t modRM; // special data to handle MOVcr, MOVdr, MOVrc, MOVrd uint8_t firstByte; // save the first byte in stream /* Immediates. There can be two in some cases */ uint8_t numImmediatesTranslated; uint64_t immediates[2]; /* A register or immediate operand encoded into the opcode */ Reg opcodeRegister; /* Portions of the ModR/M byte */ /* These fields determine the allowable values for the ModR/M fields, which depend on operand and address widths */ EABase eaRegBase; Reg regBase; /* The Mod and R/M fields can encode a base for an effective address, or a register. These are separated into two fields here */ EABase eaBase; EADisplacement eaDisplacement; /* The reg field always encodes a register */ Reg reg; const struct OperandSpecifier *operands; } InternalInstruction; /* decodeInstruction - Decode one instruction and store the decoding results in * a buffer provided by the consumer. * @param insn - The buffer to store the instruction in. Allocated by the * consumer. * @param reader - The byteReader_t for the bytes to be read. * @param readerArg - An argument to pass to the reader for storing context * specific to the consumer. May be NULL. * @param logger - The dlog_t to be used in printing status messages from the * disassembler. May be NULL. * @param loggerArg - An argument to pass to the logger for storing context * specific to the logger. May be NULL. * @param startLoc - The address (in the reader's address space) of the first * byte in the instruction. * @param mode - The mode (16-bit, 32-bit, 64-bit) to decode in. * @return - Nonzero if there was an error during decode, 0 otherwise. */ int decodeInstruction(struct InternalInstruction* insn, byteReader_t reader, const void* readerArg, uint64_t startLoc, DisassemblerMode mode); //const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii); #endif capstone-sys-0.15.0/capstone/arch/X86/X86DisassemblerDecoderCommon.h000064400000000000000000000717020072674642500232470ustar 00000000000000/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===* * * The LLVM Compiler Infrastructure * * This file is distributed under the University of Illinois Open Source * License. See LICENSE.TXT for details. * *===----------------------------------------------------------------------===* * * This file is part of the X86 Disassembler. * It contains common definitions used by both the disassembler and the table * generator. * Documentation for the disassembler can be found in X86Disassembler.h. * *===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ /* * This header file provides those definitions that need to be shared between * the decoder and the table generator in a C-friendly manner. */ #ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H #define CS_X86_DISASSEMBLERDECODERCOMMON_H #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers #define CONTEXTS_SYM x86DisassemblerContexts #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes #define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes /* * Attributes of an instruction that must be known before the opcode can be * processed correctly. Most of these indicate the presence of particular * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. */ #define ATTRIBUTE_BITS \ ENUM_ENTRY(ATTR_NONE, 0x00) \ ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \ ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \ ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \ ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \ ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \ ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \ ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \ ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \ ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \ ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \ ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \ ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \ ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \ ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13)) #define ENUM_ENTRY(n, v) n = v, enum attributeBits { ATTRIBUTE_BITS ATTR_max }; #undef ENUM_ENTRY /* * Combinations of the above attributes that are relevant to instruction * decode. Although other combinations are possible, they can be reduced to * these without affecting the ultimately decoded instruction. */ // Class name Rank Rationale for rank assignment #define INSTRUCTION_CONTEXTS \ ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ "64-bit mode but no more") \ ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ "but not the operands") \ ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ "but not the operands") \ ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\ "change width; overrides IC_OPSIZE") \ ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \ "prefix") \ ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \ "IC_ADSIZE") \ ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \ "secondary") \ ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \ ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \ ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \ "opcode") \ ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \ "IC_64BIT_REXW_XS") \ ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \ "else because this changes most " \ "operands' meaning") \ ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") #define ENUM_ENTRY(n, r, d) n, typedef enum { INSTRUCTION_CONTEXTS IC_max } InstructionContext; #undef ENUM_ENTRY /* * Opcode types, which determine which decode table to use, both in the Intel * manual and also for the decoder. */ typedef enum { ONEBYTE = 0, TWOBYTE = 1, THREEBYTE_38 = 2, THREEBYTE_3A = 3, XOP8_MAP = 4, XOP9_MAP = 5, XOPA_MAP = 6, THREEDNOW_MAP = 7 } OpcodeType; /* * The following structs are used for the hierarchical decode table. After * determining the instruction's class (i.e., which IC_* constant applies to * it), the decoder reads the opcode. Some instructions require specific * values of the ModR/M byte, so the ModR/M byte indexes into the final table. * * If a ModR/M byte is not required, "required" is left unset, and the values * for each instructionID are identical. */ typedef uint16_t InstrUID; /* * ModRMDecisionType - describes the type of ModR/M decision, allowing the * consumer to determine the number of entries in it. * * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded * instruction is the same. * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode * corresponds to one instruction; otherwise, it corresponds to * a different instruction. * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte * divided by 8 is used to select instruction; otherwise, each * value of the ModR/M byte could correspond to a different * instruction. * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This corresponds to instructions that use reg field as opcode * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond * to a different instruction. */ #define MODRMTYPES \ ENUM_ENTRY(MODRM_ONEENTRY) \ ENUM_ENTRY(MODRM_SPLITRM) \ ENUM_ENTRY(MODRM_SPLITMISC) \ ENUM_ENTRY(MODRM_SPLITREG) \ ENUM_ENTRY(MODRM_FULL) #define ENUM_ENTRY(n) n, typedef enum { MODRMTYPES MODRM_max } ModRMDecisionType; #undef ENUM_ENTRY #define CASE_ENCODING_RM \ case ENCODING_RM: \ case ENCODING_RM_CD2: \ case ENCODING_RM_CD4: \ case ENCODING_RM_CD8: \ case ENCODING_RM_CD16: \ case ENCODING_RM_CD32: \ case ENCODING_RM_CD64 #define CASE_ENCODING_VSIB \ case ENCODING_VSIB: \ case ENCODING_VSIB_CD2: \ case ENCODING_VSIB_CD4: \ case ENCODING_VSIB_CD8: \ case ENCODING_VSIB_CD16: \ case ENCODING_VSIB_CD32: \ case ENCODING_VSIB_CD64 // Physical encodings of instruction operands. #define ENCODINGS \ ENUM_ENTRY(ENCODING_NONE, "") \ ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \ ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \ ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ ENUM_ENTRY(ENCODING_IW, "2-byte") \ ENUM_ENTRY(ENCODING_ID, "4-byte") \ ENUM_ENTRY(ENCODING_IO, "8-byte") \ ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ "the opcode byte") \ ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ "byte.") \ ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \ ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ "opcode byte") \ ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ "in type") \ ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") #define ENUM_ENTRY(n, d) n, typedef enum { ENCODINGS ENCODING_max } OperandEncoding; #undef ENUM_ENTRY /* * Semantic interpretations of instruction operands. */ #define TYPES \ ENUM_ENTRY(TYPE_NONE, "") \ ENUM_ENTRY(TYPE_REL, "immediate address") \ ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ ENUM_ENTRY(TYPE_R16, "2-byte") \ ENUM_ENTRY(TYPE_R32, "4-byte") \ ENUM_ENTRY(TYPE_R64, "8-byte") \ ENUM_ENTRY(TYPE_IMM, "immediate operand") \ ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ ENUM_ENTRY(TYPE_M, "Memory operand") \ ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ ENUM_ENTRY(TYPE_XMM, "16-byte") \ ENUM_ENTRY(TYPE_YMM, "32-byte") \ ENUM_ENTRY(TYPE_ZMM, "64-byte") \ ENUM_ENTRY(TYPE_VK, "mask register") \ ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ \ ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ ENUM_ENTRY(TYPE_DUP1, "operand 1") \ ENUM_ENTRY(TYPE_DUP2, "operand 2") \ ENUM_ENTRY(TYPE_DUP3, "operand 3") \ ENUM_ENTRY(TYPE_DUP4, "operand 4") \ #define ENUM_ENTRY(n, d) n, typedef enum { TYPES TYPE_max } OperandType; #undef ENUM_ENTRY /* * The specification for how to extract and interpret one operand. */ typedef struct OperandSpecifier { uint8_t encoding; uint8_t type; } OperandSpecifier; #define X86_MAX_OPERANDS 6 /* * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, * respectively. */ typedef enum { MODE_16BIT, MODE_32BIT, MODE_64BIT } DisassemblerMode; #endif capstone-sys-0.15.0/capstone/arch/X86/X86GenAsmWriter.inc000064400000000000000000053613500072674642500210720ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '0', 9, 0, /* 12 */ 's', 'h', 'a', '1', 'm', 's', 'g', '1', 9, 0, /* 22 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '1', 9, 0, /* 34 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '1', 9, 0, /* 46 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '1', 9, 0, /* 56 */ 'p', 'f', 'r', 's', 'q', 'i', 't', '1', 9, 0, /* 66 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 't', '1', 9, 0, /* 79 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '3', '2', 9, 0, /* 90 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 9, 0, /* 101 */ 's', 'h', 'a', '1', 'm', 's', 'g', '2', 9, 0, /* 111 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '2', 9, 0, /* 123 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '2', 9, 0, /* 135 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '2', 9, 0, /* 145 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '2', 9, 0, /* 162 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '2', 9, 0, /* 179 */ 'v', 's', 'h', 'u', 'f', 'f', '6', '4', 'x', '2', 9, 0, /* 191 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '2', 9, 0, /* 206 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '2', 9, 0, /* 220 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '2', 9, 0, /* 237 */ 'v', 's', 'h', 'u', 'f', 'i', '6', '4', 'x', '2', 9, 0, /* 249 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '2', 9, 0, /* 264 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '2', 9, 0, /* 278 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '2', 9, 0, /* 295 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '6', '4', 9, 0, /* 306 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, /* 316 */ 'f', 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, /* 326 */ 'f', 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, /* 337 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, /* 347 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, /* 358 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, /* 370 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 9, 0, /* 381 */ 's', 'h', 'a', '1', 'r', 'n', 'd', 's', '4', 9, 0, /* 392 */ 'v', 's', 'h', 'u', 'f', 'f', '3', '2', 'x', '4', 9, 0, /* 404 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '4', 9, 0, /* 419 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '4', 9, 0, /* 433 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '4', 9, 0, /* 450 */ 'v', 's', 'h', 'u', 'f', 'i', '3', '2', 'x', '4', 9, 0, /* 462 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '4', 9, 0, /* 477 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '4', 9, 0, /* 491 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 9, 0, /* 508 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '4', 9, 0, /* 523 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '4', 9, 0, /* 537 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '4', 9, 0, /* 554 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '4', 9, 0, /* 569 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '4', 9, 0, /* 583 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 9, 0, /* 600 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '1', '6', 9, 0, /* 611 */ 'v', 'p', 'e', 'r', 'm', '2', 'f', '1', '2', '8', 9, 0, /* 623 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '1', '2', '8', 9, 0, /* 637 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '1', '2', '8', 9, 0, /* 650 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '1', '2', '8', 9, 0, /* 666 */ 'v', 'p', 'e', 'r', 'm', '2', 'i', '1', '2', '8', 9, 0, /* 678 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '1', '2', '8', 9, 0, /* 692 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '1', '2', '8', 9, 0, /* 705 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '1', '2', '8', 9, 0, /* 721 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '8', 9, 0, /* 731 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '8', 9, 0, /* 746 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '8', 9, 0, /* 760 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '8', 9, 0, /* 777 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '8', 9, 0, /* 792 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '8', 9, 0, /* 806 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '8', 9, 0, /* 823 */ 'j', 'a', 9, 0, /* 827 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 'a', 9, 0, /* 838 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', 9, 0, /* 847 */ 's', 'e', 't', 'a', 9, 0, /* 853 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'n', 't', 'a', 9, 0, /* 866 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, /* 874 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'b', 9, 0, /* 884 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'b', 9, 0, /* 894 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'b', 9, 0, /* 904 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, /* 915 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, /* 927 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, /* 938 */ 'v', 'p', 's', 'h', 'a', 'b', 9, 0, /* 946 */ 's', 'b', 'b', 'b', 9, 0, /* 952 */ 'v', 'p', 's', 'u', 'b', 'b', 9, 0, /* 960 */ 'a', 'd', 'c', 'b', 9, 0, /* 966 */ 'd', 'e', 'c', 'b', 9, 0, /* 972 */ 'i', 'n', 'c', 'b', 9, 0, /* 978 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 986 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 994 */ 'k', 'a', 'd', 'd', 'b', 9, 0, /* 1001 */ 'v', 'p', 'a', 'd', 'd', 'b', 9, 0, /* 1009 */ 'x', 'a', 'd', 'd', 'b', 9, 0, /* 1016 */ 'k', 'a', 'n', 'd', 'b', 9, 0, /* 1023 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'b', 9, 0, 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't', 'q', 'm', 'b', 9, 0, /* 1211 */ 'v', 'p', 'e', 'r', 'm', 'b', 9, 0, /* 1219 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'b', 9, 0, /* 1229 */ 'k', 'a', 'n', 'd', 'n', 'b', 9, 0, /* 1237 */ 'v', 'p', 's', 'i', 'g', 'n', 'b', 9, 0, /* 1246 */ 'i', 'n', 'b', 9, 0, /* 1251 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 9, 0, /* 1260 */ 'v', 'p', 'c', 'm', 'p', 'b', 9, 0, /* 1268 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'q', 'b', 9, 0, /* 1284 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'b', 9, 0, /* 1294 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'b', 9, 0, /* 1305 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'b', 9, 0, /* 1315 */ 'v', 'p', 'm', 'u', 'l', 't', 'i', 's', 'h', 'i', 'f', 't', 'q', 'b', 9, 0, /* 1331 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'i', 'n', 'v', 'q', 'b', 9, 0, /* 1350 */ 'v', 'p', 'm', 'o', 'v', 'q', 'b', 9, 0, /* 1359 */ 's', 'a', 'r', 'b', 9, 0, /* 1365 */ 'r', 'c', 'r', 'b', 9, 0, /* 1371 */ 's', 'h', 'r', 'b', 9, 0, /* 1377 */ 'k', 'o', 'r', 'b', 9, 0, /* 1383 */ 'k', 'x', 'n', 'o', 'r', 'b', 9, 0, /* 1391 */ 'r', 'o', 'r', 'b', 9, 0, /* 1397 */ 'k', 'x', 'o', 'r', 'b', 9, 0, /* 1404 */ 'v', 'p', 'i', 'n', 's', 'r', 'b', 9, 0, /* 1413 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'b', 9, 0, /* 1423 */ 'v', 'p', 'e', 'x', 't', 'r', 'b', 9, 0, /* 1432 */ 's', 'c', 'a', 's', 'b', 9, 0, /* 1439 */ 'v', 'p', 'a', 'b', 's', 'b', 9, 0, /* 1447 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, 0, /* 1456 */ 'v', 'p', 's', 'u', 'b', 's', 'b', 9, 0, /* 1465 */ 'v', 'p', 'a', 'd', 'd', 's', 'b', 9, 0, /* 1474 */ 'l', 'o', 'd', 's', 'b', 9, 0, /* 1481 */ 'v', 'p', 'm', 'i', 'n', 's', 'b', 9, 0, /* 1490 */ 'c', 'm', 'p', 's', 'b', 9, 0, /* 1497 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'b', 9, 0, /* 1510 */ 'o', 'u', 't', 's', 'b', 9, 0, /* 1517 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'b', 9, 0, /* 1527 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'b', 9, 0, /* 1537 */ 'p', 'a', 'v', 'g', 'u', 's', 'b', 9, 0, /* 1546 */ 'm', 'o', 'v', 's', 'b', 9, 0, /* 1553 */ 'v', 'p', 'm', 'a', 'x', 's', 'b', 9, 0, /* 1562 */ 's', 'e', 't', 'b', 9, 0, /* 1568 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'b', 9, 0, /* 1578 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 9, 0, /* 1588 */ 'k', 'n', 'o', 't', 'b', 9, 0, /* 1595 */ 'v', 'p', 'r', 'o', 't', 'b', 9, 0, /* 1603 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'b', 9, 0, /* 1617 */ 'k', 't', 'e', 's', 't', 'b', 9, 0, /* 1625 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'b', 9, 0, /* 1635 */ 'v', 'p', 'c', 'o', 'm', 'u', 'b', 9, 0, /* 1644 */ 'v', 'p', 'm', 'i', 'n', 'u', 'b', 9, 0, /* 1653 */ 'v', 'p', 'c', 'm', 'p', 'u', 'b', 9, 0, /* 1662 */ 'p', 'f', 's', 'u', 'b', 9, 0, /* 1669 */ 'v', 'p', 'm', 'a', 'x', 'u', 'b', 9, 0, /* 1678 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, 0, /* 1689 */ 'i', 'd', 'i', 'v', 'b', 9, 0, /* 1696 */ 'f', 'c', 'm', 'o', 'v', 'b', 9, 0, /* 1704 */ 'k', 'm', 'o', 'v', 'b', 9, 0, /* 1711 */ 'c', 'l', 'w', 'b', 9, 0, /* 1717 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'w', 'b', 9, 0, /* 1728 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'w', 'b', 9, 0, /* 1739 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'w', 'b', 9, 0, /* 1750 */ 'v', 'p', 'm', 'o', 'v', 's', 'w', 'b', 9, 0, /* 1760 */ 'v', 'p', 'm', 'o', 'v', 'w', 'b', 9, 0, /* 1769 */ 'p', 'f', 'a', 'c', 'c', 9, 0, /* 1776 */ 'p', 'f', 'n', 'a', 'c', 'c', 9, 0, /* 1784 */ 'p', 'f', 'p', 'n', 'a', 'c', 'c', 9, 0, /* 1793 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 9, 0, /* 1802 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, /* 1810 */ 'v', 'a', 'e', 's', 'i', 'm', 'c', 9, 0, /* 1819 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 9, 0, /* 1828 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'd', 9, 0, /* 1838 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'd', 9, 0, /* 1848 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'd', 9, 0, /* 1858 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'w', '2', 'd', 9, 0, /* 1875 */ 'a', 'a', 'd', 9, 0, /* 1880 */ 'v', 'p', 's', 'h', 'a', 'd', 9, 0, /* 1888 */ 'v', 'p', 's', 'r', 'a', 'd', 9, 0, /* 1896 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'd', 9, 0, /* 1906 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'd', 9, 0, /* 1917 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 9, 0, /* 1926 */ 'v', 'p', 's', 'u', 'b', 'd', 9, 0, /* 1934 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 9, 0, /* 1945 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 9, 0, /* 1956 */ 'p', 'f', 'a', 'd', 'd', 9, 0, /* 1963 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 9, 0, /* 1972 */ 'k', 'a', 'd', 'd', 'd', 9, 0, /* 1979 */ 'v', 'p', 'a', 'd', 'd', 'd', 9, 0, /* 1987 */ 'v', 'p', 's', 'h', 'l', 'd', 'd', 9, 0, /* 1996 */ 'k', 'a', 'n', 'd', 'd', 9, 0, /* 2003 */ 'v', 'p', 'a', 'n', 'd', 'd', 9, 0, /* 2011 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'd', 9, 0, /* 2022 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'd', 9, 0, /* 2032 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 9, 0, /* 2044 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'd', 9, 0, /* 2057 */ 'v', 'p', 's', 'h', 'r', 'd', 'd', 9, 0, /* 2066 */ 'v', 'p', 'm', 'a', 'c', 's', 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'e', 'r', 'm', 'd', 9, 0, /* 2250 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'd', 9, 0, /* 2260 */ 'v', 'p', 'a', 'n', 'd', 9, 0, /* 2267 */ 'k', 'a', 'n', 'd', 'n', 'd', 9, 0, /* 2275 */ 'v', 'p', 'a', 'n', 'd', 'n', 'd', 9, 0, /* 2284 */ 'v', 'a', 'l', 'i', 'g', 'n', 'd', 9, 0, /* 2293 */ 'v', 'p', 's', 'i', 'g', 'n', 'd', 9, 0, /* 2302 */ 'b', 'o', 'u', 'n', 'd', 9, 0, /* 2309 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, /* 2325 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, /* 2338 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, /* 2352 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, /* 2368 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, /* 2381 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, /* 2395 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, /* 2411 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, /* 2424 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, /* 2438 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, /* 2454 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, /* 2467 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, /* 2481 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 'd', 9, 0, /* 2492 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 'd', 9, 0, /* 2502 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 'd', 9, 0, /* 2514 */ 'v', 'e', 'x', 'p', '2', 'p', 'd', 9, 0, /* 2523 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 9, 0, /* 2534 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 'd', 9, 0, /* 2546 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 'd', 9, 0, /* 2557 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 'd', 9, 0, /* 2569 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, 0, /* 2580 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 'd', 9, 0, /* 2591 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, /* 2607 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, /* 2620 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, /* 2634 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, /* 2650 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, /* 2663 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, /* 2677 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 'd', 9, 0, /* 2687 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 'd', 9, 0, /* 2699 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 9, 0, /* 2709 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 9, 0, /* 2721 */ 'v', 'm', 'o', 'v', 'a', 'p', 'd', 9, 0, /* 2730 */ 'p', 's', 'w', 'a', 'p', 'd', 9, 0, /* 2738 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2751 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2762 */ 'v', 'h', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2771 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2781 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2792 */ 'v', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2800 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, 0, /* 2815 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, 0, /* 2831 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, 0, /* 2846 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, 0, /* 2862 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2875 */ 'v', 'h', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2884 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2894 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2905 */ 'v', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2913 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 'd', 9, 0, /* 2924 */ 'v', 'a', 'n', 'd', 'p', 'd', 9, 0, /* 2932 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 'd', 9, 0, /* 2942 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 'd', 9, 0, /* 2952 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 9, 0, /* 2964 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 'd', 9, 0, /* 2977 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 'd', 9, 0, /* 2988 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 'd', 9, 0, /* 2998 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 'd', 9, 0, /* 3011 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 'd', 9, 0, /* 3022 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 9, 0, /* 3031 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 'd', 9, 0, /* 3042 */ 'v', 'm', 'o', 'v', 'h', 'p', 'd', 9, 0, /* 3051 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 'd', 9, 0, /* 3062 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 9, 0, /* 3073 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 'd', 9, 0, /* 3084 */ 'v', 'm', 'u', 'l', 'p', 'd', 9, 0, /* 3092 */ 'v', 'm', 'o', 'v', 'l', 'p', 'd', 9, 0, /* 3101 */ 'v', 'p', 'c', 'm', 'p', 'd', 9, 0, /* 3109 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 'd', 9, 0, /* 3120 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 'd', 9, 0, /* 3133 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 9, 0, /* 3142 */ 'v', 'a', 'n', 'd', 'n', 'p', 'd', 9, 0, /* 3151 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, 0, /* 3159 */ 'v', 'd', 'p', 'p', 'd', 9, 0, /* 3166 */ 'v', 'c', 'm', 'p', 'p', 'd', 9, 0, /* 3174 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 'd', 9, 0, /* 3185 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, 0, /* 3200 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, 0, /* 3216 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, 0, /* 3231 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, 0, /* 3247 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 9, 0, /* 3259 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 'd', 9, 0, /* 3272 */ 'v', 'o', 'r', 'p', 'd', 9, 0, /* 3279 */ 'v', 'x', 'o', 'r', 'p', 'd', 9, 0, /* 3287 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 9, 0, /* 3299 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, /* 3308 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, /* 3316 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 'd', 9, 0, /* 3329 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 'd', 9, 0, /* 3341 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 'd', 9, 0, /* 3351 */ 'v', 's', 'q', 'r', 't', 'p', 'd', 9, 0, /* 3360 */ 'v', 't', 'e', 's', 't', 'p', 'd', 9, 0, /* 3369 */ 'v', 'm', 'o', 'v', 'u', 'p', 'd', 9, 0, /* 3378 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, 0, /* 3389 */ 'v', 'd', 'i', 'v', 'p', 'd', 9, 0, /* 3397 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 'd', 9, 0, /* 3409 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, 0, /* 3417 */ 'v', 'f', 'r', 'c', 'z', 'p', 'd', 9, 0, /* 3426 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'd', 9, 0, /* 3436 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 9, 0, /* 3448 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'd', 9, 0, /* 3461 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'd', 9, 0, /* 3472 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'd', 9, 0, /* 3482 */ 'v', 'p', 'm', 'o', 'v', 'q', 'd', 9, 0, /* 3491 */ 'k', 'o', 'r', 'd', 9, 0, /* 3497 */ 'k', 'x', 'n', 'o', 'r', 'd', 9, 0, /* 3505 */ 'v', 'p', 'o', 'r', 'd', 9, 0, /* 3512 */ 'v', 'p', 'r', 'o', 'r', 'd', 9, 0, /* 3520 */ 'k', 'x', 'o', 'r', 'd', 9, 0, /* 3527 */ 'v', 'p', 'x', 'o', 'r', 'd', 9, 0, /* 3535 */ 'v', 'p', 'i', 'n', 's', 'r', 'd', 9, 0, /* 3544 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'd', 9, 0, /* 3554 */ 'v', 'p', 'e', 'x', 't', 'r', 'd', 9, 0, /* 3563 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, /* 3576 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, /* 3590 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, /* 3603 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, /* 3617 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, /* 3630 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, /* 3644 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, /* 3657 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, /* 3671 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, 0, /* 3682 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, /* 3695 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, /* 3709 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, /* 3722 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, /* 3736 */ 'v', 'r', 'c', 'p', '1', '4', 's', 'd', 9, 0, /* 3746 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 'd', 9, 0, /* 3758 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 9, 0, /* 3768 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 9, 0, /* 3780 */ 'v', 'p', 'a', 'b', 's', 'd', 9, 0, /* 3788 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 'd', 9, 0, /* 3798 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 'd', 9, 0, /* 3809 */ 'v', 's', 'u', 'b', 's', 'd', 9, 0, /* 3817 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, /* 3827 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, /* 3838 */ 'v', 'a', 'd', 'd', 's', 'd', 9, 0, /* 3846 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 'd', 9, 0, /* 3856 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 'd', 9, 0, /* 3867 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 'd', 9, 0, /* 3877 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 'd', 9, 0, /* 3890 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 'd', 9, 0, /* 3901 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, /* 3911 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, /* 3920 */ 'v', 'm', 'u', 'l', 's', 'd', 9, 0, /* 3928 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 'd', 9, 0, /* 3941 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 9, 0, /* 3950 */ 'v', 'm', 'i', 'n', 's', 'd', 9, 0, /* 3958 */ 'v', 'c', 'm', 'p', 's', 'd', 9, 0, /* 3966 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 'd', 9, 0, /* 3977 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'd', 9, 0, /* 3990 */ 'w', 'r', 's', 's', 'd', 9, 0, /* 3997 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 'd', 9, 0, /* 4009 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, /* 4017 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 9, 0, /* 4028 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 9, 0, /* 4038 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 'd', 9, 0, /* 4050 */ 'm', 'o', 'v', 'n', 't', 's', 'd', 9, 0, /* 4059 */ 'v', 's', 'q', 'r', 't', 's', 'd', 9, 0, /* 4068 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 9, 0, /* 4082 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 9, 0, /* 4092 */ 'v', 'd', 'i', 'v', 's', 'd', 9, 0, /* 4100 */ 'v', 'm', 'o', 'v', 's', 'd', 9, 0, /* 4108 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 9, 0, /* 4117 */ 'v', 'm', 'a', 'x', 's', 'd', 9, 0, /* 4125 */ 'v', 'f', 'r', 'c', 'z', 's', 'd', 9, 0, /* 4134 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'd', 9, 0, /* 4147 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'd', 9, 0, /* 4157 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 9, 0, /* 4167 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'd', 9, 0, /* 4177 */ 'k', 'n', 'o', 't', 'd', 9, 0, /* 4184 */ 'v', 'p', 'r', 'o', 't', 'd', 9, 0, /* 4192 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 9, 0, /* 4206 */ 'k', 't', 'e', 's', 't', 'd', 9, 0, /* 4214 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'd', 9, 0, /* 4224 */ 'v', 'p', 'c', 'o', 'm', 'u', 'd', 9, 0, /* 4233 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 9, 0, /* 4242 */ 'v', 'p', 'c', 'm', 'p', 'u', 'd', 9, 0, /* 4251 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 9, 0, /* 4260 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 9, 0, /* 4269 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'd', 9, 0, /* 4279 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'd', 9, 0, /* 4289 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 9, 0, /* 4298 */ 'v', 'p', 'r', 'o', 'l', 'v', 'd', 9, 0, /* 4307 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 9, 0, /* 4316 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 9, 0, /* 4328 */ 'v', 'm', 'o', 'v', 'd', 9, 0, /* 4335 */ 'v', 'p', 'r', 'o', 'r', 'v', 'd', 9, 0, /* 4344 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 'd', 9, 0, /* 4354 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'd', 9, 0, /* 4364 */ 'v', 'p', 'm', 'a', 'd', 'd', 'w', 'd', 9, 0, /* 4374 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'w', 'd', 9, 0, /* 4386 */ 'k', 'u', 'n', 'p', 'c', 'k', 'w', 'd', 9, 0, /* 4396 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'w', 'd', 9, 0, /* 4408 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'd', 9, 0, /* 4418 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 'w', 'd', 9, 0, /* 4429 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'd', 9, 0, /* 4440 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 's', 'w', 'd', 9, 0, /* 4452 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'd', 9, 0, /* 4463 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 9, 0, /* 4474 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 9, 0, /* 4485 */ 'j', 'a', 'e', 9, 0, /* 4490 */ 's', 'e', 't', 'a', 'e', 9, 0, /* 4497 */ 'j', 'b', 'e', 9, 0, /* 4502 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 'e', 9, 0, /* 4512 */ 's', 'e', 't', 'b', 'e', 9, 0, /* 4519 */ 'f', 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, /* 4528 */ 'f', 'f', 'r', 'e', 'e', 9, 0, /* 4535 */ 'j', 'g', 'e', 9, 0, /* 4540 */ 'p', 'f', 'c', 'm', 'p', 'g', 'e', 9, 0, /* 4549 */ 's', 'e', 't', 'g', 'e', 9, 0, /* 4556 */ 'j', 'e', 9, 0, /* 4560 */ 'j', 'l', 'e', 9, 0, /* 4565 */ 's', 'e', 't', 'l', 'e', 9, 0, /* 4572 */ 'j', 'n', 'e', 9, 0, /* 4577 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, /* 4585 */ 's', 'e', 't', 'n', 'e', 9, 0, /* 4592 */ 'f', 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, /* 4601 */ 'l', 'o', 'o', 'p', 'e', 9, 0, /* 4608 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, /* 4616 */ 's', 'e', 't', 'e', 9, 0, /* 4622 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, /* 4632 */ 's', 'h', 'a', '1', 'n', 'e', 'x', 't', 'e', 9, 0, /* 4643 */ 'f', 'n', 's', 'a', 'v', 'e', 9, 0, /* 4651 */ 'f', 'x', 's', 'a', 'v', 'e', 9, 0, /* 4659 */ 'f', 'c', 'm', 'o', 'v', 'e', 9, 0, /* 4667 */ 'j', 'g', 9, 0, /* 4671 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, /* 4679 */ 's', 'e', 't', 'g', 9, 0, /* 4685 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 9, 0, /* 4695 */ 'f', 'x', 'c', 'h', 9, 0, /* 4701 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 9, 0, /* 4712 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'h', 9, 0, /* 4723 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'h', 9, 0, /* 4735 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 9, 0, /* 4744 */ 'f', 'c', 'o', 'm', 'i', 9, 0, /* 4751 */ 'f', 'u', 'c', 'o', 'm', 'i', 9, 0, /* 4759 */ 'c', 'v', 't', 't', 'p', 'd', '2', 'p', 'i', 9, 0, /* 4770 */ 'c', 'v', 't', 'p', 'd', '2', 'p', 'i', 9, 0, /* 4780 */ 'c', 'v', 't', 't', 'p', 's', '2', 'p', 'i', 9, 0, /* 4791 */ 'c', 'v', 't', 'p', 's', '2', 'p', 'i', 9, 0, /* 4801 */ 'f', 'c', 'o', 'm', 'p', 'i', 9, 0, /* 4809 */ 'f', 'u', 'c', 'o', 'm', 'p', 'i', 9, 0, /* 4818 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, /* 4827 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'i', 9, 0, /* 4839 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'i', 9, 0, /* 4851 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, 0, /* 4863 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 9, 0, /* 4874 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 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9, 0, /* 5056 */ 'b', 'l', 's', 'i', 'c', 'l', 9, 0, /* 5064 */ 't', '1', 'm', 's', 'k', 'c', 'l', 9, 0, /* 5073 */ 'i', 'n', 'c', 'l', 9, 0, /* 5079 */ 'b', 't', 'c', 'l', 9, 0, /* 5085 */ 'v', 'm', 'r', 'e', 'a', 'd', 'l', 9, 0, /* 5094 */ 'f', 'a', 'd', 'd', 'l', 9, 0, /* 5101 */ 'f', 'i', 'a', 'd', 'd', 'l', 9, 0, /* 5109 */ 'x', 'a', 'd', 'd', 'l', 9, 0, /* 5116 */ 'r', 'd', 's', 'e', 'e', 'd', 'l', 9, 0, /* 5125 */ 'f', 'l', 'd', 'l', 9, 0, /* 5131 */ 's', 'h', 'l', 'd', 'l', 9, 0, /* 5138 */ 'f', 'i', 'l', 'd', 'l', 9, 0, /* 5145 */ 'r', 'd', 'r', 'a', 'n', 'd', 'l', 9, 0, /* 5154 */ 's', 'h', 'r', 'd', 'l', 9, 0, /* 5161 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'l', 9, 0, /* 5173 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'l', 9, 0, /* 5186 */ 'c', 'm', 'o', 'v', 'a', 'e', 'l', 9, 0, /* 5195 */ 'c', 'm', 'o', 'v', 'b', 'e', 'l', 9, 0, /* 5204 */ 'c', 'm', 'o', 'v', 'g', 'e', 'l', 9, 0, /* 5213 */ 'c', 'm', 'o', 'v', 'l', 'e', 'l', 9, 0, /* 5222 */ 'c', 'm', 'o', 'v', 'n', 'e', 'l', 9, 0, /* 5231 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 5242 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 5253 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 5264 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 5275 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, /* 5285 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, /* 5295 */ 'c', 'm', 'o', 'v', 'e', 'l', 9, 0, /* 5303 */ 'b', 's', 'f', 'l', 9, 0, /* 5309 */ 'n', 'e', 'g', 'l', 9, 0, /* 5315 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'l', 9, 0, /* 5325 */ 'c', 'm', 'o', 'v', 'g', 'l', 9, 0, /* 5333 */ 'p', 'u', 's', 'h', 'l', 9, 0, /* 5340 */ 'b', 'l', 'c', 'i', 'l', 9, 0, /* 5347 */ 'b', 'z', 'h', 'i', 'l', 9, 0, /* 5354 */ 'b', 'l', 's', 'i', 'l', 9, 0, /* 5361 */ 'm', 'o', 'v', 'n', 't', 'i', 'l', 9, 0, /* 5370 */ 'j', 'l', 9, 0, /* 5374 */ 'b', 'l', 'c', 'm', 's', 'k', 'l', 9, 0, /* 5383 */ 'b', 'l', 's', 'm', 's', 'k', 'l', 9, 0, /* 5392 */ 't', 'z', 'm', 's', 'k', 'l', 9, 0, /* 5400 */ 's', 'a', 'l', 'l', 9, 0, /* 5406 */ 'r', 'c', 'l', 'l', 9, 0, /* 5412 */ 'f', 'i', 'l', 'd', 'l', 'l', 9, 0, /* 5420 */ 's', 'h', 'l', 'l', 9, 0, /* 5426 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, 0, /* 5434 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 'l', 9, 0, /* 5444 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 'l', 9, 0, /* 5454 */ 'r', 'o', 'l', 'l', 9, 0, /* 5460 */ 'f', 'i', 's', 't', 'p', 'l', 'l', 9, 0, /* 5469 */ 'f', 'i', 's', 't', 't', 'p', 'l', 'l', 9, 0, /* 5479 */ 'l', 's', 'l', 'l', 9, 0, /* 5485 */ 'f', 'm', 'u', 'l', 'l', 9, 0, /* 5492 */ 'f', 'i', 'm', 'u', 'l', 'l', 9, 0, /* 5500 */ 'c', 'm', 'o', 'v', 'l', 'l', 9, 0, /* 5508 */ 'f', 'c', 'o', 'm', 'l', 9, 0, /* 5515 */ 'f', 'i', 'c', 'o', 'm', 'l', 9, 0, /* 5523 */ 'a', 'n', 'd', 'n', 'l', 9, 0, /* 5530 */ 'i', 'n', 'l', 9, 0, /* 5535 */ 'c', 'm', 'o', 'v', 'n', 'o', 'l', 9, 0, /* 5544 */ 'c', 'm', 'o', 'v', 'o', 'l', 9, 0, /* 5552 */ 'b', 's', 'w', 'a', 'p', 'l', 9, 0, /* 5560 */ 'p', 'd', 'e', 'p', 'l', 9, 0, /* 5567 */ 'c', 'm', 'p', 'l', 9, 0, /* 5573 */ 'l', 'j', 'm', 'p', 'l', 9, 0, /* 5580 */ 'f', 'c', 'o', 'm', 'p', 'l', 9, 0, /* 5588 */ 'f', 'i', 'c', 'o', 'm', 'p', 'l', 9, 0, /* 5597 */ 'c', 'm', 'o', 'v', 'n', 'p', 'l', 9, 0, /* 5606 */ 'n', 'o', 'p', 'l', 9, 0, /* 5612 */ 'p', 'o', 'p', 'l', 9, 0, /* 5618 */ 'a', 'r', 'p', 'l', 9, 0, /* 5624 */ 'f', 's', 't', 'p', 'l', 9, 0, /* 5631 */ 'f', 'i', 's', 't', 'p', 'l', 9, 0, /* 5639 */ 'f', 'i', 's', 't', 't', 'p', 'l', 9, 0, /* 5648 */ 'c', 'm', 'o', 'v', 'p', 'l', 9, 0, /* 5656 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'l', 9, 0, /* 5667 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'l', 9, 0, /* 5679 */ 'l', 'a', 'r', 'l', 9, 0, /* 5685 */ 's', 'a', 'r', 'l', 9, 0, /* 5691 */ 'f', 's', 'u', 'b', 'r', 'l', 9, 0, /* 5699 */ 'f', 'i', 's', 'u', 'b', 'r', 'l', 9, 0, /* 5708 */ 'r', 'c', 'r', 'l', 9, 0, /* 5714 */ 's', 'h', 'r', 'l', 9, 0, /* 5720 */ 'r', 'o', 'r', 'l', 9, 0, /* 5726 */ 'x', 'o', 'r', 'l', 9, 0, /* 5732 */ 'b', 's', 'r', 'l', 9, 0, /* 5738 */ 'b', 'l', 's', 'r', 'l', 9, 0, /* 5745 */ 'b', 't', 'r', 'l', 9, 0, /* 5751 */ 's', 't', 'r', 'l', 9, 0, /* 5757 */ 'b', 'e', 'x', 't', 'r', 'l', 9, 0, /* 5765 */ 'f', 'd', 'i', 'v', 'r', 'l', 9, 0, /* 5773 */ 'f', 'i', 'd', 'i', 'v', 'r', 'l', 9, 0, /* 5782 */ 's', 'c', 'a', 's', 'l', 9, 0, /* 5789 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, 0, /* 5798 */ 'b', 'l', 'c', 's', 'l', 9, 0, /* 5805 */ 'l', 'd', 's', 'l', 9, 0, /* 5811 */ 'l', 'o', 'd', 's', 'l', 9, 0, /* 5818 */ 'l', 'e', 's', 'l', 9, 0, /* 5824 */ 'l', 'f', 's', 'l', 9, 0, /* 5830 */ 'l', 'g', 's', 'l', 9, 0, /* 5836 */ 'c', 'm', 'o', 'v', 'n', 's', 'l', 9, 0, /* 5845 */ 'c', 'm', 'p', 's', 'l', 9, 0, /* 5852 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'l', 9, 0, /* 5865 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'l', 9, 0, /* 5877 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'l', 9, 0, /* 5890 */ 'l', 's', 's', 'l', 9, 0, /* 5896 */ 'b', 't', 's', 'l', 9, 0, /* 5902 */ 'o', 'u', 't', 's', 'l', 9, 0, /* 5909 */ 'c', 'm', 'o', 'v', 's', 'l', 9, 0, /* 5917 */ 'b', 't', 'l', 9, 0, /* 5922 */ 'l', 'g', 'd', 't', 'l', 9, 0, /* 5929 */ 's', 'g', 'd', 't', 'l', 9, 0, /* 5936 */ 'l', 'i', 'd', 't', 'l', 9, 0, /* 5943 */ 's', 'i', 'd', 't', 'l', 9, 0, /* 5950 */ 's', 'l', 'd', 't', 'l', 9, 0, /* 5957 */ 'l', 'r', 'e', 't', 'l', 9, 0, /* 5964 */ 's', 'e', 't', 'l', 9, 0, /* 5970 */ 'p', 'o', 'p', 'c', 'n', 't', 'l', 9, 0, /* 5979 */ 'l', 'z', 'c', 'n', 't', 'l', 9, 0, /* 5987 */ 't', 'z', 'c', 'n', 't', 'l', 9, 0, /* 5995 */ 'n', 'o', 't', 'l', 9, 0, /* 6001 */ 't', 'e', 's', 't', 'l', 9, 0, /* 6008 */ 'f', 's', 't', 'l', 9, 0, /* 6014 */ 'f', 'i', 's', 't', 'l', 9, 0, /* 6021 */ 'p', 'e', 'x', 't', 'l', 9, 0, /* 6028 */ 'p', 'f', 'm', 'u', 'l', 9, 0, /* 6035 */ 'f', 'd', 'i', 'v', 'l', 9, 0, /* 6042 */ 'f', 'i', 'd', 'i', 'v', 'l', 9, 0, /* 6050 */ 'm', 'o', 'v', 'l', 9, 0, /* 6056 */ 's', 'm', 's', 'w', 'l', 9, 0, /* 6063 */ 'm', 'o', 'v', 's', 'w', 'l', 9, 0, /* 6071 */ 'm', 'o', 'v', 'z', 'w', 'l', 9, 0, /* 6079 */ 'a', 'd', 'c', 'x', 'l', 9, 0, /* 6086 */ 's', 'h', 'l', 'x', 'l', 9, 0, /* 6093 */ 'm', 'u', 'l', 'x', 'l', 9, 0, /* 6100 */ 'a', 'd', 'o', 'x', 'l', 9, 0, /* 6107 */ 's', 'a', 'r', 'x', 'l', 9, 0, /* 6114 */ 's', 'h', 'r', 'x', 'l', 9, 0, /* 6121 */ 'r', 'o', 'r', 'x', 'l', 9, 0, /* 6128 */ 'v', 'p', 'm', 'o', 'v', 'b', '2', 'm', 9, 0, /* 6138 */ 'v', 'p', 'm', 'o', 'v', 'd', '2', 'm', 9, 0, /* 6148 */ 'v', 'p', 'm', 'o', 'v', 'q', '2', 'm', 9, 0, /* 6158 */ 'v', 'p', 'm', 'o', 'v', 'w', '2', 'm', 9, 0, /* 6168 */ 'a', 'a', 'm', 9, 0, /* 6173 */ 'f', 'c', 'o', 'm', 9, 0, /* 6179 */ 'f', 'u', 'c', 'o', 'm', 9, 0, /* 6186 */ 'v', 'p', 'p', 'e', 'r', 'm', 9, 0, /* 6194 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'm', 9, 0, /* 6206 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'm', 9, 0, /* 6218 */ 'b', 'n', 'd', 'c', 'n', 9, 0, /* 6225 */ 'v', 'p', 'a', 'n', 'd', 'n', 9, 0, /* 6233 */ 'x', 'b', 'e', 'g', 'i', 'n', 9, 0, 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'p', 9, 0, /* 6408 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 9, 0, /* 6419 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 9, 0, /* 6430 */ 'f', 'd', 'i', 'v', 'p', 9, 0, /* 6437 */ 'c', 'r', 'c', '3', '2', 'q', 9, 0, /* 6445 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'b', '2', 'q', 9, 0, /* 6462 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'q', 9, 0, /* 6472 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'q', 9, 0, /* 6482 */ 'm', 'o', 'v', 'd', 'q', '2', 'q', 9, 0, /* 6491 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'q', 9, 0, /* 6501 */ 'l', 'e', 'a', 'q', 9, 0, /* 6507 */ 'v', 'p', 's', 'h', 'a', 'q', 9, 0, /* 6515 */ 'v', 'p', 's', 'r', 'a', 'q', 9, 0, /* 6523 */ 'c', 'm', 'o', 'v', 'a', 'q', 9, 0, /* 6531 */ 's', 'b', 'b', 'q', 9, 0, /* 6537 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'q', 9, 0, /* 6547 */ 'm', 'o', 'v', 's', 'b', 'q', 9, 0, /* 6555 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'q', 9, 0, /* 6566 */ 'v', 'p', 's', 'u', 'b', 'q', 9, 0, /* 6574 */ 'c', 'm', 'o', 'v', 'b', 'q', 9, 0, /* 6582 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 9, 0, /* 6593 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 9, 0, /* 6604 */ 'm', 'o', 'v', 'z', 'b', 'q', 9, 0, /* 6612 */ 'a', 'd', 'c', 'q', 9, 0, /* 6618 */ 'd', 'e', 'c', 'q', 9, 0, /* 6624 */ 'b', 'l', 'c', 'i', 'c', 'q', 9, 0, /* 6632 */ 'b', 'l', 's', 'i', 'c', 'q', 9, 0, /* 6640 */ 't', '1', 'm', 's', 'k', 'c', 'q', 9, 0, /* 6649 */ 'i', 'n', 'c', 'q', 9, 0, /* 6655 */ 'b', 't', 'c', 'q', 9, 0, /* 6661 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 9, 0, /* 6673 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 9, 0, /* 6684 */ 'm', 'o', 'v', 'q', '2', 'd', 'q', 9, 0, /* 6693 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 9, 0, /* 6705 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 9, 0, /* 6716 */ 'v', 'm', 'r', 'e', 'a', 'd', 'q', 9, 0, /* 6725 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 'q', 9, 0, /* 6735 */ 'k', 'a', 'd', 'd', 'q', 9, 0, /* 6742 */ 'v', 'p', 'a', 'd', 'd', 'q', 9, 0, /* 6750 */ 'x', 'a', 'd', 'd', 'q', 9, 0, /* 6757 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 'q', 9, 0, /* 6767 */ 'r', 'd', 's', 'e', 'e', 'd', 'q', 9, 0, /* 6776 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 9, 0, /* 6788 */ 'k', 'u', 'n', 'p', 'c', 'k', 'd', 'q', 9, 0, /* 6798 */ 'v', 'p', 's', 'h', 'l', 'd', 'q', 9, 0, /* 6807 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 9, 0, /* 6819 */ 'v', 'p', 's', 'l', 'l', 'd', 'q', 9, 0, /* 6828 */ 'v', 'p', 's', 'r', 'l', 'd', 'q', 9, 0, /* 6837 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 9, 0, /* 6846 */ 'k', 'a', 'n', 'd', 'q', 9, 0, /* 6853 */ 'v', 'p', 'a', 'n', 'd', 'q', 9, 0, /* 6861 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'q', 9, 0, /* 6872 */ 'r', 'd', 'r', 'a', 'n', 'd', 'q', 9, 0, /* 6881 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'q', 9, 0, /* 6894 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 9, 0, /* 6907 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 9, 0, /* 6920 */ 'v', 'p', 'c', 'l', 'm', 'u', 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'q', 9, 0, /* 8136 */ 'i', 'n', 's', 'e', 'r', 't', 'q', 9, 0, /* 8145 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 9, 0, /* 8159 */ 'k', 't', 'e', 's', 't', 'q', 9, 0, /* 8167 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'q', 9, 0, /* 8177 */ 'p', 'e', 'x', 't', 'q', 9, 0, /* 8184 */ 'v', 'p', 'm', 'a', 'd', 'd', '5', '2', 'h', 'u', 'q', 9, 0, /* 8197 */ 'v', 'p', 'm', 'a', 'd', 'd', '5', '2', 'l', 'u', 'q', 9, 0, /* 8210 */ 'v', 'p', 'c', 'o', 'm', 'u', 'q', 9, 0, /* 8219 */ 'v', 'p', 'm', 'i', 'n', 'u', 'q', 9, 0, /* 8228 */ 'v', 'p', 'c', 'm', 'p', 'u', 'q', 9, 0, /* 8237 */ 'v', 'p', 'm', 'a', 'x', 'u', 'q', 9, 0, /* 8246 */ 'v', 'p', 's', 'r', 'a', 'v', 'q', 9, 0, /* 8255 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'q', 9, 0, /* 8265 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'q', 9, 0, /* 8275 */ 'i', 'd', 'i', 'v', 'q', 9, 0, /* 8282 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 9, 0, /* 8291 */ 'v', 'p', 'r', 'o', 'l', 'v', 'q', 9, 0, /* 8300 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 9, 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'3', '2', 'p', 's', 9, 0, /* 8832 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, /* 8848 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, /* 8861 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, /* 8875 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 9, 0, /* 8886 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, 0, /* 8897 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 's', 9, 0, /* 8908 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 's', 9, 0, /* 8918 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 's', 9, 0, /* 8930 */ 'v', 'e', 'x', 'p', '2', 'p', 's', 9, 0, /* 8939 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 9, 0, /* 8950 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 's', 9, 0, /* 8962 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 9, 0, /* 8973 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 9, 0, /* 8985 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 's', 9, 0, /* 8996 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, /* 9012 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, /* 9025 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, /* 9039 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, /* 9055 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, /* 9068 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, /* 9082 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 's', 9, 0, /* 9092 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 's', 9, 0, /* 9104 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 9, 0, /* 9114 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 9, 0, /* 9126 */ 'v', 'm', 'o', 'v', 'a', 'p', 's', 9, 0, /* 9135 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, /* 9148 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, /* 9159 */ 'v', 'h', 's', 'u', 'b', 'p', 's', 9, 0, /* 9168 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 's', 9, 0, /* 9178 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 's', 9, 0, /* 9189 */ 'v', 's', 'u', 'b', 'p', 's', 9, 0, /* 9197 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, 0, /* 9212 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, 0, /* 9228 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, 0, /* 9243 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, 0, /* 9259 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9272 */ 'v', 'h', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9281 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9292 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9302 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9314 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9325 */ 'v', 'a', 'd', 'd', 'p', 's', 9, 0, /* 9333 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 's', 9, 0, /* 9344 */ 'v', 'a', 'n', 'd', 'p', 's', 9, 0, /* 9352 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 's', 9, 0, /* 9362 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 's', 9, 0, /* 9372 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 9, 0, /* 9384 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 's', 9, 0, /* 9397 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 's', 9, 0, /* 9408 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 's', 9, 0, /* 9418 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 's', 9, 0, /* 9431 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 's', 9, 0, /* 9442 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 9, 0, /* 9451 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 's', 9, 0, /* 9462 */ 'v', 'm', 'o', 'v', 'l', 'h', 'p', 's', 9, 0, /* 9472 */ 'v', 'm', 'o', 'v', 'h', 'p', 's', 9, 0, /* 9481 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 's', 9, 0, /* 9492 */ 'v', 'm', 'o', 'v', 'h', 'l', 'p', 's', 9, 0, /* 9502 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 9, 0, /* 9513 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 's', 9, 0, /* 9524 */ 'v', 'm', 'u', 'l', 'p', 's', 9, 0, /* 9532 */ 'v', 'm', 'o', 'v', 'l', 'p', 's', 9, 0, /* 9541 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 's', 9, 0, /* 9552 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 's', 9, 0, /* 9565 */ 'f', 'c', 'o', 'm', 'p', 's', 9, 0, /* 9573 */ 'f', 'i', 'c', 'o', 'm', 'p', 's', 9, 0, /* 9582 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 9, 0, /* 9591 */ 'v', 'a', 'n', 'd', 'n', 'p', 's', 9, 0, /* 9600 */ 'v', 'm', 'i', 'n', 'p', 's', 9, 0, /* 9608 */ 'v', 'r', 'c', 'p', 'p', 's', 9, 0, /* 9616 */ 'v', 'd', 'p', 'p', 's', 9, 0, /* 9623 */ 'v', 'c', 'm', 'p', 'p', 's', 9, 0, /* 9631 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 's', 9, 0, /* 9642 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, 0, /* 9657 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, 0, /* 9673 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, 0, /* 9688 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, 0, /* 9704 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 9, 0, /* 9716 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 's', 9, 0, /* 9729 */ 'v', 'o', 'r', 'p', 's', 9, 0, /* 9736 */ 'v', 'x', 'o', 'r', 'p', 's', 9, 0, /* 9744 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 9, 0, /* 9756 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 's', 9, 0, /* 9769 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'p', 's', 9, 0, /* 9781 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 's', 9, 0, /* 9793 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 's', 9, 0, /* 9803 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'p', 's', 9, 0, /* 9814 */ 'v', 'r', 's', 'q', 'r', 't', 'p', 's', 9, 0, /* 9824 */ 'v', 's', 'q', 'r', 't', 'p', 's', 9, 0, /* 9833 */ 'v', 't', 'e', 's', 't', 'p', 's', 9, 0, /* 9842 */ 'f', 's', 't', 'p', 's', 9, 0, /* 9849 */ 'f', 'i', 's', 't', 'p', 's', 9, 0, /* 9857 */ 'f', 'i', 's', 't', 't', 'p', 's', 9, 0, /* 9866 */ 'v', 'm', 'o', 'v', 'u', 'p', 's', 9, 0, /* 9875 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, 0, /* 9886 */ 'v', 'd', 'i', 'v', 'p', 's', 9, 0, /* 9894 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 's', 9, 0, /* 9906 */ 'v', 'm', 'a', 'x', 'p', 's', 9, 0, /* 9914 */ 'v', 'f', 'r', 'c', 'z', 'p', 's', 9, 0, /* 9923 */ 'f', 's', 'u', 'b', 'r', 's', 9, 0, /* 9931 */ 'f', 'i', 's', 'u', 'b', 'r', 's', 9, 0, /* 9940 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, /* 9949 */ 'f', 'd', 'i', 'v', 'r', 's', 9, 0, /* 9957 */ 'f', 'i', 'd', 'i', 'v', 'r', 's', 9, 0, /* 9966 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, /* 9979 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, /* 9993 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, /* 10006 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, /* 10020 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, /* 10033 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, /* 10047 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, /* 10060 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, /* 10074 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 's', 9, 0, /* 10085 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, /* 10098 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, /* 10112 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, /* 10125 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, /* 10139 */ 'v', 'r', 'c', 'p', '1', '4', 's', 's', 9, 0, /* 10149 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 's', 9, 0, /* 10161 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 9, 0, /* 10171 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 9, 0, /* 10183 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 's', 9, 0, /* 10193 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 's', 9, 0, /* 10204 */ 'v', 's', 'u', 'b', 's', 's', 9, 0, /* 10212 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 10223 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 10233 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 10245 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 10256 */ 'v', 'a', 'd', 'd', 's', 's', 9, 0, /* 10264 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 's', 9, 0, /* 10274 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 's', 9, 0, /* 10285 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 's', 9, 0, /* 10295 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 's', 9, 0, /* 10308 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 's', 9, 0, /* 10319 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, 0, /* 10329 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, 0, /* 10338 */ 'v', 'm', 'u', 'l', 's', 's', 9, 0, /* 10346 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 's', 9, 0, /* 10359 */ 'v', 'm', 'i', 'n', 's', 's', 9, 0, /* 10367 */ 'v', 'r', 'c', 'p', 's', 's', 9, 0, /* 10375 */ 'v', 'c', 'm', 'p', 's', 's', 9, 0, /* 10383 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 's', 9, 0, /* 10394 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 's', 9, 0, /* 10406 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 's', 9, 0, /* 10418 */ 'm', 'o', 'v', 'n', 't', 's', 's', 9, 0, /* 10427 */ 'v', 'r', 's', 'q', 'r', 't', 's', 's', 9, 0, /* 10437 */ 'v', 's', 'q', 'r', 't', 's', 's', 9, 0, /* 10446 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 9, 0, /* 10460 */ 'v', 'd', 'i', 'v', 's', 's', 9, 0, /* 10468 */ 'v', 'm', 'o', 'v', 's', 's', 9, 0, /* 10476 */ 'v', 'm', 'a', 'x', 's', 's', 9, 0, /* 10484 */ 'v', 'f', 'r', 'c', 'z', 's', 's', 9, 0, /* 10493 */ 's', 'e', 't', 's', 9, 0, /* 10499 */ 'f', 's', 't', 's', 9, 0, /* 10505 */ 'f', 'i', 's', 't', 's', 9, 0, /* 10512 */ 'f', 'd', 'i', 'v', 's', 9, 0, /* 10519 */ 'f', 'i', 'd', 'i', 'v', 's', 9, 0, /* 10527 */ 'f', 'l', 'd', 't', 9, 0, /* 10533 */ 'p', 'f', 'c', 'm', 'p', 'g', 't', 9, 0, /* 10542 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, /* 10550 */ 'i', 'n', 't', 9, 0, /* 10555 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, /* 10563 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, /* 10573 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, /* 10585 */ 'f', 's', 't', 'p', 't', 9, 0, /* 10592 */ 'x', 'a', 'b', 'o', 'r', 't', 9, 0, /* 10600 */ 'p', 'f', 'r', 's', 'q', 'r', 't', 9, 0, /* 10609 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 'l', 'a', 's', 't', 9, 0, /* 10622 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 'l', 'a', 's', 't', 9, 0, /* 10635 */ 'v', 'p', 't', 'e', 's', 't', 9, 0, /* 10643 */ 'f', 's', 't', 9, 0, /* 10648 */ 'v', 'a', 'e', 's', 'k', 'e', 'y', 'g', 'e', 'n', 'a', 's', 's', 'i', 's', 't', 9, 0, /* 10666 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, /* 10675 */ 'b', 'n', 'd', 'c', 'u', 9, 0, /* 10682 */ 'f', 'c', 'm', 'o', 'v', 'n', 'u', 9, 0, /* 10691 */ 'v', 'l', 'd', 'd', 'q', 'u', 9, 0, /* 10699 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, /* 10712 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, /* 10721 */ 'f', 'c', 'm', 'o', 'v', 'u', 9, 0, /* 10729 */ 'f', 'd', 'i', 'v', 9, 0, /* 10735 */ 'f', 'l', 'd', 'e', 'n', 'v', 9, 0, /* 10743 */ 'f', 'n', 's', 't', 'e', 'n', 'v', 9, 0, /* 10752 */ 'v', 'p', 'c', 'm', 'o', 'v', 9, 0, /* 10760 */ 'b', 'n', 'd', 'm', 'o', 'v', 9, 0, /* 10768 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, /* 10776 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'w', 9, 0, /* 10786 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'w', 9, 0, /* 10796 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'w', 9, 0, /* 10806 */ 'l', 'e', 'a', 'w', 9, 0, /* 10812 */ 'v', 'p', 's', 'h', 'a', 'w', 9, 0, /* 10820 */ 'v', 'p', 's', 'r', 'a', 'w', 9, 0, /* 10828 */ 'c', 'm', 'o', 'v', 'a', 'w', 9, 0, /* 10836 */ 's', 'b', 'b', 'w', 9, 0, /* 10842 */ 'v', 'p', 'h', 's', 'u', 'b', 'b', 'w', 9, 0, /* 10852 */ 'v', 'd', 'b', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, /* 10863 */ 'v', 'm', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, /* 10873 */ 'v', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, /* 10882 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'w', 9, 0, /* 10892 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'b', 'w', 9, 0, /* 10904 */ 'k', 'u', 'n', 'p', 'c', 'k', 'b', 'w', 9, 0, /* 10914 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'b', 'w', 9, 0, /* 10926 */ 'm', 'o', 'v', 's', 'b', 'w', 9, 0, /* 10934 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'w', 9, 0, /* 10945 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 9, 0, /* 10954 */ 'v', 'p', 's', 'u', 'b', 'w', 9, 0, /* 10962 */ 'c', 'm', 'o', 'v', 'b', 'w', 9, 0, /* 10970 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'w', 9, 0, /* 10981 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'w', 9, 0, /* 10992 */ 'm', 'o', 'v', 'z', 'b', 'w', 9, 0, /* 11000 */ 'a', 'd', 'c', 'w', 9, 0, /* 11006 */ 'f', 'l', 'd', 'c', 'w', 9, 0, /* 11013 */ 'd', 'e', 'c', 'w', 9, 0, /* 11019 */ 'i', 'n', 'c', 'w', 9, 0, /* 11025 */ 'b', 't', 'c', 'w', 9, 0, /* 11031 */ 'f', 'n', 's', 't', 'c', 'w', 9, 0, /* 11039 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 9, 0, /* 11048 */ 'k', 'a', 'd', 'd', 'w', 9, 0, /* 11055 */ 'v', 'p', 'a', 'd', 'd', 'w', 9, 0, /* 11063 */ 'x', 'a', 'd', 'd', 'w', 9, 0, /* 11070 */ 'r', 'd', 's', 'e', 'e', 'd', 'w', 9, 0, /* 11079 */ 'v', 'p', 's', 'h', 'l', 'd', 'w', 9, 0, /* 11088 */ 'k', 'a', 'n', 'd', 'w', 9, 0, /* 11095 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'w', 9, 0, /* 11106 */ 'r', 'd', 'r', 'a', 'n', 'd', 'w', 9, 0, /* 11115 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'w', 9, 0, /* 11125 */ 'v', 'p', 's', 'h', 'r', 'd', 'w', 9, 0, /* 11134 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'd', 'w', 9, 0, /* 11145 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'd', 'w', 9, 0, /* 11156 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'w', 9, 0, /* 11167 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'w', 9, 0, /* 11177 */ 'v', 'p', 'm', 'o', 'v', 'd', 'w', 9, 0, /* 11186 */ 'c', 'm', 'o', 'v', 'a', 'e', 'w', 9, 0, /* 11195 */ 'c', 'm', 'o', 'v', 'b', 'e', 'w', 9, 0, /* 11204 */ 'c', 'm', 'o', 'v', 'g', 'e', 'w', 9, 0, /* 11213 */ 'c', 'm', 'o', 'v', 'l', 'e', 'w', 9, 0, /* 11222 */ 'c', 'm', 'o', 'v', 'n', 'e', 'w', 9, 0, /* 11231 */ 'c', 'm', 'o', 'v', 'e', 'w', 9, 0, /* 11239 */ 'p', 'i', '2', 'f', 'w', 9, 0, /* 11246 */ 'b', 's', 'f', 'w', 9, 0, /* 11252 */ 'p', 's', 'h', 'u', 'f', 'w', 9, 0, /* 11260 */ 'n', 'e', 'g', 'w', 9, 0, /* 11266 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'w', 9, 0, /* 11276 */ 'v', 'p', 'a', 'v', 'g', 'w', 9, 0, /* 11284 */ 'c', 'm', 'o', 'v', 'g', 'w', 9, 0, /* 11292 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 9, 0, /* 11303 */ 'v', 'p', 's', 'h', 'u', 'f', 'h', 'w', 9, 0, /* 11313 */ 'v', 'p', 'm', 'u', 'l', 'h', 'w', 9, 0, /* 11322 */ 'p', 'u', 's', 'h', 'w', 9, 0, /* 11329 */ 'p', 'f', '2', 'i', 'w', 9, 0, /* 11336 */ 's', 'a', 'l', 'w', 9, 0, /* 11342 */ 'r', 'c', 'l', 'w', 9, 0, /* 11348 */ 'v', 'p', 's', 'h', 'u', 'f', 'l', 'w', 9, 0, /* 11358 */ 'v', 'p', 's', 'h', 'l', 'w', 9, 0, /* 11366 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, 0, /* 11374 */ 'v', 'p', 's', 'l', 'l', 'w', 9, 0, /* 11382 */ 'v', 'p', 'm', 'u', 'l', 'l', 'w', 9, 0, /* 11391 */ 'r', 'o', 'l', 'w', 9, 0, /* 11397 */ 'v', 'p', 's', 'r', 'l', 'w', 9, 0, /* 11405 */ 'l', 's', 'l', 'w', 9, 0, /* 11411 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'w', 9, 0, /* 11421 */ 'i', 'm', 'u', 'l', 'w', 9, 0, /* 11428 */ 'c', 'm', 'o', 'v', 'l', 'w', 9, 0, /* 11436 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'w', 9, 0, /* 11447 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'w', 9, 0, /* 11458 */ 'v', 'p', 'c', 'o', 'm', 'w', 9, 0, /* 11466 */ 'v', 'p', 'e', 'r', 'm', 'w', 9, 0, /* 11474 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'w', 9, 0, /* 11484 */ 'k', 'a', 'n', 'd', 'n', 'w', 9, 0, /* 11492 */ 'v', 'p', 's', 'i', 'g', 'n', 'w', 9, 0, /* 11501 */ 'i', 'n', 'w', 9, 0, /* 11506 */ 'c', 'm', 'o', 'v', 'n', 'o', 'w', 9, 0, /* 11515 */ 'c', 'm', 'o', 'v', 'o', 'w', 9, 0, /* 11523 */ 'b', 's', 'w', 'a', 'p', 'w', 9, 0, /* 11531 */ 'v', 'p', 'c', 'm', 'p', 'w', 9, 0, /* 11539 */ 'l', 'j', 'm', 'p', 'w', 9, 0, /* 11546 */ 'c', 'm', 'o', 'v', 'n', 'p', 'w', 9, 0, /* 11555 */ 'n', 'o', 'p', 'w', 9, 0, /* 11561 */ 'p', 'o', 'p', 'w', 9, 0, /* 11567 */ 'c', 'm', 'o', 'v', 'p', 'w', 9, 0, /* 11575 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'w', 9, 0, /* 11585 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'w', 9, 0, /* 11596 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'w', 9, 0, /* 11606 */ 'v', 'p', 'm', 'o', 'v', 'q', 'w', 9, 0, /* 11615 */ 'l', 'a', 'r', 'w', 9, 0, /* 11621 */ 's', 'a', 'r', 'w', 9, 0, /* 11627 */ 'r', 'c', 'r', 'w', 9, 0, /* 11633 */ 'v', 'e', 'r', 'w', 9, 0, /* 11639 */ 'p', 'm', 'u', 'l', 'h', 'r', 'w', 9, 0, /* 11648 */ 's', 'h', 'r', 'w', 9, 0, /* 11654 */ 'k', 'o', 'r', 'w', 9, 0, /* 11660 */ 'k', 'x', 'n', 'o', 'r', 'w', 9, 0, /* 11668 */ 'r', 'o', 'r', 'w', 9, 0, /* 11674 */ 'k', 'x', 'o', 'r', 'w', 9, 0, /* 11681 */ 'b', 's', 'r', 'w', 9, 0, /* 11687 */ 'v', 'p', 'i', 'n', 's', 'r', 'w', 9, 0, /* 11696 */ 'b', 't', 'r', 'w', 9, 0, /* 11702 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'w', 9, 0, /* 11712 */ 'l', 't', 'r', 'w', 9, 0, /* 11718 */ 's', 't', 'r', 'w', 9, 0, /* 11724 */ 'v', 'p', 'e', 'x', 't', 'r', 'w', 9, 0, /* 11733 */ 's', 'c', 'a', 's', 'w', 9, 0, /* 11740 */ 'v', 'p', 'a', 'b', 's', 'w', 9, 0, /* 11748 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, 0, /* 11757 */ 'v', 'p', 'm', 'a', 'd', 'd', 'u', 'b', 's', 'w', 9, 0, /* 11769 */ 'v', 'p', 'h', 's', 'u', 'b', 's', 'w', 9, 0, /* 11779 */ 'v', 'p', 's', 'u', 'b', 's', 'w', 9, 0, /* 11788 */ 'v', 'p', 'h', 'a', 'd', 'd', 's', 'w', 9, 0, /* 11798 */ 'v', 'p', 'a', 'd', 'd', 's', 'w', 9, 0, /* 11807 */ 'l', 'd', 's', 'w', 9, 0, /* 11813 */ 'l', 'o', 'd', 's', 'w', 9, 0, /* 11820 */ 'l', 'e', 's', 'w', 9, 0, /* 11826 */ 'l', 'f', 's', 'w', 9, 0, /* 11832 */ 'l', 'g', 's', 'w', 9, 0, /* 11838 */ 'v', 'p', 'm', 'i', 'n', 's', 'w', 9, 0, /* 11847 */ 'c', 'm', 'o', 'v', 'n', 's', 'w', 9, 0, /* 11856 */ 'c', 'm', 'p', 's', 'w', 9, 0, /* 11863 */ 'v', 'p', 'm', 'u', 'l', 'h', 'r', 's', 'w', 9, 0, /* 11874 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'w', 9, 0, /* 11887 */ 'l', 's', 's', 'w', 9, 0, /* 11893 */ 'b', 't', 's', 'w', 9, 0, /* 11899 */ 'f', 'n', 's', 't', 's', 'w', 9, 0, /* 11907 */ 'o', 'u', 't', 's', 'w', 9, 0, /* 11914 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'w', 9, 0, /* 11924 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'w', 9, 0, /* 11934 */ 'c', 'm', 'o', 'v', 's', 'w', 9, 0, /* 11942 */ 'v', 'p', 'm', 'a', 'x', 's', 'w', 9, 0, /* 11951 */ 'b', 't', 'w', 9, 0, /* 11956 */ 'l', 'g', 'd', 't', 'w', 9, 0, /* 11963 */ 's', 'g', 'd', 't', 'w', 9, 0, /* 11970 */ 'l', 'i', 'd', 't', 'w', 9, 0, /* 11977 */ 's', 'i', 'd', 't', 'w', 9, 0, /* 11984 */ 'l', 'l', 'd', 't', 'w', 9, 0, /* 11991 */ 's', 'l', 'd', 't', 'w', 9, 0, /* 11998 */ 'l', 'r', 'e', 't', 'w', 9, 0, /* 12005 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'w', 9, 0, /* 12015 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'w', 9, 0, /* 12025 */ 'l', 'z', 'c', 'n', 't', 'w', 9, 0, /* 12033 */ 't', 'z', 'c', 'n', 't', 'w', 9, 0, /* 12041 */ 'k', 'n', 'o', 't', 'w', 9, 0, /* 12048 */ 'v', 'p', 'r', 'o', 't', 'w', 9, 0, /* 12056 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'w', 9, 0, /* 12070 */ 'k', 't', 'e', 's', 't', 'w', 9, 0, /* 12078 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'w', 9, 0, /* 12088 */ 'v', 'p', 'm', 'u', 'l', 'h', 'u', 'w', 9, 0, /* 12098 */ 'v', 'p', 'c', 'o', 'm', 'u', 'w', 9, 0, /* 12107 */ 'v', 'p', 'm', 'i', 'n', 'u', 'w', 9, 0, /* 12116 */ 'v', 'p', 'c', 'm', 'p', 'u', 'w', 9, 0, /* 12125 */ 'v', 'p', 'h', 'm', 'i', 'n', 'p', 'o', 's', 'u', 'w', 9, 0, /* 12138 */ 'v', 'p', 'm', 'a', 'x', 'u', 'w', 9, 0, /* 12147 */ 'v', 'p', 's', 'r', 'a', 'v', 'w', 9, 0, /* 12156 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'w', 9, 0, /* 12166 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'w', 9, 0, /* 12176 */ 'i', 'd', 'i', 'v', 'w', 9, 0, /* 12183 */ 'v', 'p', 's', 'l', 'l', 'v', 'w', 9, 0, /* 12192 */ 'v', 'p', 's', 'r', 'l', 'v', 'w', 9, 0, /* 12201 */ 'k', 'm', 'o', 'v', 'w', 9, 0, /* 12208 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'w', 9, 0, /* 12218 */ 'l', 'm', 's', 'w', 'w', 9, 0, /* 12225 */ 's', 'm', 's', 'w', 'w', 9, 0, /* 12232 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'w', 9, 0, /* 12243 */ 'm', 'o', 'v', 's', 'w', 'w', 9, 0, /* 12251 */ 'm', 'o', 'v', 'z', 'w', 'w', 9, 0, /* 12259 */ 'p', 'f', 'm', 'a', 'x', 9, 0, /* 12266 */ 'b', 'n', 'd', 'l', 'd', 'x', 9, 0, /* 12274 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'x', 9, 0, /* 12287 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 'x', 9, 0, /* 12300 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 'x', 9, 0, /* 12312 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 'x', 9, 0, /* 12326 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 'x', 9, 0, /* 12339 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 'x', 9, 0, /* 12351 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 'x', 9, 0, /* 12363 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 'x', 9, 0, /* 12376 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'x', 9, 0, /* 12389 */ 'b', 'n', 'd', 's', 't', 'x', 9, 0, /* 12397 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'y', 9, 0, /* 12410 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 'y', 9, 0, /* 12423 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 'y', 9, 0, /* 12435 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 'y', 9, 0, /* 12449 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 'y', 9, 0, /* 12462 */ 'c', 'l', 'r', 's', 's', 'b', 's', 'y', 9, 0, /* 12472 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 'y', 9, 0, /* 12484 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 'y', 9, 0, /* 12496 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 'y', 9, 0, /* 12509 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'y', 9, 0, /* 12522 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 'z', 9, 0, /* 12535 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 'z', 9, 0, /* 12548 */ 'j', 'e', 'c', 'x', 'z', 9, 0, /* 12555 */ 'j', 'c', 'x', 'z', 9, 0, /* 12561 */ 'j', 'r', 'c', 'x', 'z', 9, 0, /* 12568 */ 'f', 's', 'u', 'b', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12582 */ 'f', 'a', 'd', 'd', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12596 */ 'f', 's', 't', 'p', 'n', 'c', 'e', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12613 */ 'f', 'm', 'u', 'l', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12627 */ 'f', 's', 'u', 'b', 'r', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12642 */ 'f', 'd', 'i', 'v', 'r', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12657 */ 'f', 'd', 'i', 'v', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, /* 12671 */ 's', 'h', 'a', '2', '5', '6', 'r', 'n', 'd', 's', '2', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, /* 12691 */ 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, /* 12708 */ 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, /* 12725 */ 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, '%', 'x', 'm', 'm', '0', ',', 32, 0, /* 12742 */ 's', 'a', 'l', 'b', 9, '$', '1', ',', 32, 0, /* 12752 */ 'r', 'c', 'l', 'b', 9, '$', '1', ',', 32, 0, /* 12762 */ 's', 'h', 'l', 'b', 9, '$', '1', ',', 32, 0, /* 12772 */ 'r', 'o', 'l', 'b', 9, '$', '1', ',', 32, 0, /* 12782 */ 's', 'a', 'r', 'b', 9, '$', '1', ',', 32, 0, /* 12792 */ 'r', 'c', 'r', 'b', 9, '$', '1', ',', 32, 0, /* 12802 */ 's', 'h', 'r', 'b', 9, '$', '1', ',', 32, 0, /* 12812 */ 'r', 'o', 'r', 'b', 9, '$', '1', ',', 32, 0, /* 12822 */ 's', 'a', 'l', 'l', 9, '$', '1', ',', 32, 0, /* 12832 */ 'r', 'c', 'l', 'l', 9, '$', '1', ',', 32, 0, /* 12842 */ 's', 'h', 'l', 'l', 9, '$', '1', ',', 32, 0, /* 12852 */ 'r', 'o', 'l', 'l', 9, '$', '1', ',', 32, 0, /* 12862 */ 's', 'a', 'r', 'l', 9, '$', '1', ',', 32, 0, /* 12872 */ 'r', 'c', 'r', 'l', 9, '$', '1', ',', 32, 0, /* 12882 */ 's', 'h', 'r', 'l', 9, '$', '1', ',', 32, 0, /* 12892 */ 'r', 'o', 'r', 'l', 9, '$', '1', ',', 32, 0, /* 12902 */ 's', 'a', 'l', 'q', 9, '$', '1', ',', 32, 0, /* 12912 */ 'r', 'c', 'l', 'q', 9, '$', '1', ',', 32, 0, /* 12922 */ 's', 'h', 'l', 'q', 9, '$', '1', ',', 32, 0, /* 12932 */ 'r', 'o', 'l', 'q', 9, '$', '1', ',', 32, 0, /* 12942 */ 's', 'a', 'r', 'q', 9, '$', '1', ',', 32, 0, /* 12952 */ 'r', 'c', 'r', 'q', 9, '$', '1', ',', 32, 0, /* 12962 */ 's', 'h', 'r', 'q', 9, '$', '1', ',', 32, 0, /* 12972 */ 'r', 'o', 'r', 'q', 9, '$', '1', ',', 32, 0, /* 12982 */ 's', 'a', 'l', 'w', 9, '$', '1', ',', 32, 0, /* 12992 */ 'r', 'c', 'l', 'w', 9, '$', '1', ',', 32, 0, /* 13002 */ 's', 'h', 'l', 'w', 9, '$', '1', ',', 32, 0, /* 13012 */ 'r', 'o', 'l', 'w', 9, '$', '1', ',', 32, 0, /* 13022 */ 's', 'a', 'r', 'w', 9, '$', '1', ',', 32, 0, /* 13032 */ 'r', 'c', 'r', 'w', 9, '$', '1', ',', 32, 0, /* 13042 */ 's', 'h', 'r', 'w', 9, '$', '1', ',', 32, 0, /* 13052 */ 'r', 'o', 'r', 'w', 9, '$', '1', ',', 32, 0, /* 13062 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 13076 */ 's', 't', 'o', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 13088 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 13099 */ 'm', 'o', 'v', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 13110 */ 's', 'a', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 13121 */ 'r', 'c', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 13132 */ 's', 'h', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 13143 */ 'r', 'o', 'l', 'b', 9, '%', 'c', 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'7', '_', 'n', 'o', 'p', 0, /* 15400 */ 'f', 'n', 'o', 'p', 0, /* 15405 */ 'f', 'c', 'o', 'm', 'p', 'p', 0, /* 15412 */ 'f', 'u', 'c', 'o', 'm', 'p', 'p', 0, /* 15420 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, /* 15432 */ 'f', 'd', 'e', 'c', 's', 't', 'p', 0, /* 15440 */ 'f', 'i', 'n', 'c', 's', 't', 'p', 0, /* 15448 */ 'p', 'u', 's', 'h', 'f', 'q', 0, /* 15455 */ 'p', 'o', 'p', 'f', 'q', 0, /* 15461 */ 'i', 'r', 'e', 't', 'q', 0, /* 15467 */ 'l', 'r', 'e', 't', 'q', 0, /* 15473 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, /* 15481 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, /* 15490 */ 'c', 'l', 't', 'q', 0, /* 15495 */ 'v', 'z', 'e', 'r', 'o', 'u', 'p', 'p', 'e', 'r', 0, /* 15506 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, /* 15515 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 0, /* 15523 */ 'r', 'd', 'm', 's', 'r', 0, /* 15529 */ 'w', 'r', 'm', 's', 'r', 0, /* 15535 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, /* 15545 */ 'a', 'a', 's', 0, /* 15549 */ 'd', 'a', 's', 0, /* 15553 */ 'f', 'a', 'b', 's', 0, /* 15558 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'c', 's', 0, /* 15568 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'c', 's', 0, /* 15578 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'd', 's', 0, /* 15588 */ 'p', 'o', 'p', 'l', 9, '%', 'd', 's', 0, /* 15597 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'd', 's', 0, /* 15607 */ 'p', 'o', 'p', 'w', 9, '%', 'd', 's', 0, /* 15616 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'e', 's', 0, /* 15626 */ 'p', 'o', 'p', 'l', 9, '%', 'e', 's', 0, /* 15635 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'e', 's', 0, /* 15645 */ 'p', 'o', 'p', 'w', 9, '%', 'e', 's', 0, /* 15654 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'f', 's', 0, /* 15664 */ 'p', 'o', 'p', 'l', 9, '%', 'f', 's', 0, /* 15673 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'f', 's', 0, /* 15683 */ 'p', 'o', 'p', 'q', 9, '%', 'f', 's', 0, /* 15692 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'f', 's', 0, /* 15702 */ 'p', 'o', 'p', 'w', 9, '%', 'f', 's', 0, /* 15711 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'g', 's', 0, /* 15721 */ 'p', 'o', 'p', 'l', 9, '%', 'g', 's', 0, /* 15730 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'g', 's', 0, /* 15740 */ 'p', 'o', 'p', 'q', 9, '%', 'g', 's', 0, /* 15749 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'g', 's', 0, /* 15759 */ 'p', 'o', 'p', 'w', 9, '%', 'g', 's', 0, /* 15768 */ 's', 'w', 'a', 'p', 'g', 's', 0, /* 15775 */ 'f', 'c', 'h', 's', 0, /* 15780 */ 'e', 'n', 'c', 'l', 's', 0, /* 15786 */ 'f', 'e', 'm', 'm', 's', 0, /* 15792 */ 'f', 'c', 'o', 's', 0, /* 15797 */ 'f', 's', 'i', 'n', 'c', 'o', 's', 0, /* 15805 */ 'p', 'u', 's', 'h', 'l', 9, '%', 's', 's', 0, /* 15815 */ 'p', 'o', 'p', 'l', 9, '%', 's', 's', 0, /* 15824 */ 'p', 'u', 's', 'h', 'w', 9, '%', 's', 's', 0, /* 15834 */ 'p', 'o', 'p', 'w', 9, '%', 's', 's', 0, /* 15843 */ 'c', 'l', 't', 's', 0, /* 15848 */ 'f', 'l', 'd', 'l', '2', 't', 0, /* 15855 */ 'f', 'x', 't', 'r', 'a', 'c', 't', 0, /* 15863 */ 'm', 'w', 'a', 'i', 't', 0, /* 15869 */ 'f', 'n', 'i', 'n', 'i', 't', 0, /* 15876 */ 'h', 'l', 't', 0, /* 15880 */ 'f', 'r', 'n', 'd', 'i', 'n', 't', 0, /* 15888 */ 'f', 's', 'q', 'r', 't', 0, /* 15894 */ 'x', 't', 'e', 's', 't', 0, /* 15900 */ 'f', 't', 's', 't', 0, /* 15905 */ 'e', 'n', 'c', 'l', 'u', 0, /* 15911 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, /* 15918 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, /* 15925 */ 'x', 'g', 'e', 't', 'b', 'v', 0, /* 15932 */ 'x', 's', 'e', 't', 'b', 'v', 0, /* 15939 */ 'e', 'n', 'c', 'l', 'v', 0, /* 15945 */ 'p', 'u', 's', 'h', 'a', 'w', 0, /* 15952 */ 'p', 'o', 'p', 'a', 'w', 0, /* 15958 */ 'p', 'u', 's', 'h', 'f', 'w', 0, /* 15965 */ 'p', 'o', 'p', 'f', 'w', 0, /* 15971 */ 'c', 'b', 't', 'w', 0, /* 15976 */ 'i', 'r', 'e', 't', 'w', 0, /* 15982 */ 'l', 'r', 'e', 't', 'w', 0, /* 15988 */ 'f', 'y', 'l', '2', 'x', 0, /* 15994 */ 'f', 'n', 's', 't', 's', 'w', 9, '%', 'a', 'x', 0, /* 16005 */ 'i', 'n', 'w', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'x', 0, /* 16018 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'e', 'a', 'x', 0, /* 16030 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'e', 'a', 'x', 0, /* 16042 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'e', 'a', 'x', 0, /* 16053 */ 's', 'k', 'i', 'n', 'i', 't', 9, '%', 'e', 'a', 'x', 0, /* 16065 */ 'i', 'n', 'l', 9, '%', 'd', 'x', ',', 32, '%', 'e', 'a', 'x', 0, /* 16079 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'r', 'a', 'x', 0, /* 16091 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'r', 'a', 'x', 0, /* 16103 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'r', 'a', 'x', 0, /* 16114 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, /* 16133 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'r', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, /* 16152 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, '%', 'd', 'x', 0, /* 16166 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, '%', 'd', 'x', 0, /* 16180 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'd', 'x', 0, /* 16195 */ 'f', 'n', 'c', 'l', 'e', 'x', 0, /* 16202 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, /* 16211 */ 'm', 'w', 'a', 'i', 't', 'x', 0, /* 16218 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, /* 16227 */ 'f', 'l', 'd', 'z', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 14825U, // DBG_VALUE 14835U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 14818U, // BUNDLE 14845U, // LIFETIME_START 14805U, // LIFETIME_END 0U, // STACKMAP 15201U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 14632U, // PATCHABLE_FUNCTION_ENTER 14552U, // PATCHABLE_RET 14678U, // PATCHABLE_FUNCTION_EXIT 14655U, // PATCHABLE_TAIL_CALL 14607U, // PATCHABLE_EVENT_CALL 14583U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // AVX1_SETALLONES 0U, // AVX2_SETALLONES 0U, // AVX512_128_SET0 0U, // AVX512_256_SET0 0U, // AVX512_512_SET0 0U, // AVX512_512_SETALLONES 0U, // AVX512_512_SEXT_MASK_32 0U, // AVX512_512_SEXT_MASK_64 0U, // AVX512_FsFLD0SD 0U, // AVX512_FsFLD0SS 0U, // AVX_SET0 0U, // KSET0D 0U, // KSET0Q 0U, // KSET0W 0U, // KSET1D 0U, // KSET1Q 0U, // KSET1W 0U, // MMX_SET0 0U, // V_SET0 0U, // V_SETALLONES 14860U, // AAA 18260U, // AAD8i8 22553U, // AAM8i8 15546U, // AAS 15554U, // ABS_F 0U, // ABS_Fp32 0U, // ABS_Fp64 0U, // ABS_Fp80 2124537U, // ADC16i16 4238073U, // ADC16mi 4238073U, // ADC16mi8 4238073U, // ADC16mr 6351609U, // ADC16ri 6351609U, // ADC16ri8 6367993U, // ADC16rm 6351609U, // ADC16rr 8448761U, // ADC16rr_REV 10507174U, // ADC32i32 12620710U, // ADC32mi 12620710U, // ADC32mi8 12620710U, // ADC32mr 6345638U, // ADC32ri 6345638U, // ADC32ri8 283202470U, // ADC32rm 6345638U, // ADC32rr 8442790U, // ADC32rr_REV 16800213U, // ADC64i32 18913749U, // ADC64mi32 18913749U, // ADC64mi8 18913749U, // ADC64mr 6347221U, // ADC64ri32 6347221U, // ADC64ri8 283220437U, // ADC64rm 6347221U, // ADC64rr 8444373U, // ADC64rr_REV 20988865U, // ADC8i8 23102401U, // ADC8mi 23102401U, // ADC8mi8 23102401U, // ADC8mr 6341569U, // ADC8ri 6341569U, // ADC8ri8 6407105U, // ADC8rm 6341569U, // ADC8rr 8438721U, // ADC8rr_REV 551638976U, // ADCX32rm 8443840U, // ADCX32rr 551657684U, // ADCX64rm 8446164U, // ADCX64rr 2124579U, // ADD16i16 4238115U, // ADD16mi 4238115U, // ADD16mi8 4238115U, // ADD16mr 6351651U, // ADD16ri 6351651U, // ADD16ri8 6368035U, // ADD16rm 6351651U, // ADD16rr 8448803U, // ADD16rr_REV 10507240U, // ADD32i32 12620776U, // ADD32mi 12620776U, // ADD32mi8 12620776U, // ADD32mr 6345704U, // ADD32ri 6345704U, // ADD32ri8 283202536U, // ADD32rm 6345704U, // ADD32rr 8442856U, // ADD32rr_REV 16800337U, // ADD64i32 18913873U, // ADD64mi32 18913873U, // ADD64mi8 18913873U, // ADD64mr 6347345U, // ADD64ri32 6347345U, // ADD64ri8 283220561U, // ADD64rm 6347345U, // ADD64rr 8444497U, // ADD64rr_REV 20988900U, // ADD8i8 23102436U, // ADD8mi 23102436U, // ADD8mi8 23102436U, // ADD8mr 6341604U, // ADD8ri 6341604U, // ADD8ri8 6407140U, // ADD8rm 6341604U, // ADD8rr 8438756U, // ADD8rr_REV 8522549U, // ADDPDrm 8440629U, // ADDPDrr 8528946U, // ADDPSrm 8447026U, // ADDPSrr 551702253U, // ADDSDrm 551702253U, // ADDSDrm_Int 8441581U, // ADDSDrr 8441581U, // ADDSDrr_Int 551725033U, // ADDSSrm 551725033U, // ADDSSrm_Int 8447977U, // ADDSSrr 8447977U, // ADDSSrr_Int 8522422U, // ADDSUBPDrm 8440502U, // ADDSUBPDrr 8528819U, // ADDSUBPSrm 8446899U, // ADDSUBPSrr 188799U, // ADD_F32m 201703U, // ADD_F64m 221574U, // ADD_FI16m 234478U, // ADD_FI32m 22676U, // ADD_FPrST0 18342U, // ADD_FST0r 0U, // ADD_Fp32 0U, // ADD_Fp32m 0U, // ADD_Fp64 0U, // ADD_Fp64m 0U, // ADD_Fp64m32 0U, // ADD_Fp80 0U, // ADD_Fp80m32 0U, // ADD_Fp80m64 0U, // ADD_FpI16m32 0U, // ADD_FpI16m64 0U, // ADD_FpI16m80 0U, // ADD_FpI32m32 0U, // ADD_FpI32m64 0U, // ADD_FpI32m80 28967U, // ADD_FrST0 551638997U, // ADOX32rm 8443861U, // ADOX32rr 551657705U, // ADOX64rm 8446185U, // ADOX64rr 8644979U, // AESDECLASTrm 8448371U, // AESDECLASTrr 8636163U, // AESDECrm 8439555U, // AESDECrr 8644992U, // AESENCLASTrm 8448384U, // AESENCLASTrr 8636189U, // AESENCrm 8439581U, // AESENCrr 263956U, // AESIMCrm 551831316U, // AESIMCrr 830777754U, // AESKEYGENASSIST128rm 283437466U, // AESKEYGENASSIST128rr 2124626U, // AND16i16 4238162U, // AND16mi 4238162U, // AND16mi8 4238162U, // AND16mr 6351698U, // AND16ri 6351698U, // AND16ri8 6368082U, // AND16rm 6351698U, // AND16rr 8448850U, // AND16rr_REV 10507293U, // AND32i32 12620829U, // AND32mi 12620829U, // AND32mi8 12620829U, // AND32mr 6345757U, // AND32ri 6345757U, // AND32ri8 283202589U, // AND32rm 6345757U, // AND32rr 8442909U, // AND32rr_REV 16800448U, // AND64i32 18913984U, // AND64mi32 18913984U, // AND64mi8 18913984U, // AND64mr 6347456U, // AND64ri32 6347456U, // AND64ri8 283220672U, // AND64rm 6347456U, // AND64rr 8444608U, // AND64rr_REV 20988922U, // AND8i8 23102458U, // AND8mi 23102458U, // AND8mi8 23102458U, // AND8mr 6341626U, // AND8ri 6341626U, // AND8ri8 6407162U, // AND8rm 6341626U, // AND8rr 8438778U, // AND8rr_REV 283202964U, // ANDN32rm 811652500U, // ANDN32rr 283221318U, // ANDN64rm 811654470U, // ANDN64rr 8522824U, // ANDNPDrm 8440904U, // ANDNPDrr 8529273U, // ANDNPSrm 8447353U, // ANDNPSrr 8522598U, // ANDPDrm 8440678U, // ANDPDrr 8529018U, // ANDPSrm 8447098U, // ANDPSrr 4232691U, // ARPL16mr 551835123U, // ARPL16rr 832902782U, // BEXTR32rm 811652734U, // BEXTR32rr 835002024U, // BEXTR64rm 811654824U, // BEXTR64rr 832902782U, // BEXTRI32mi 811652734U, // BEXTRI32ri 835002024U, // BEXTRI64mi 811654824U, // BEXTRI64ri 551900475U, // BLCFILL32rm 551834939U, // BLCFILL32rr 551918777U, // BLCFILL64rm 551836857U, // BLCFILL64rr 551900381U, // BLCI32rm 551834845U, // BLCI32rr 551918694U, // BLCI64rm 551836774U, // BLCI64rr 551900089U, // BLCIC32rm 551834553U, // BLCIC32rr 551918049U, // BLCIC64rm 551836129U, // BLCIC64rr 551900415U, // BLCMSK32rm 551834879U, // BLCMSK32rr 551918724U, // BLCMSK64rm 551836804U, // BLCMSK64rr 551900839U, // BLCS32rm 551835303U, // BLCS32rr 551919313U, // BLCS64rm 551837393U, // BLCS64rr 568707958U, // BLENDPDrmi 1088818038U, // BLENDPDrri 568714378U, // BLENDPSrmi 1088824458U, // BLENDPSrri 8532389U, // BLENDVPDrm0 8450469U, // BLENDVPDrr0 8532406U, // BLENDVPSrm0 8450486U, // BLENDVPSrr0 551900485U, // BLSFILL32rm 551834949U, // BLSFILL32rr 551918787U, // BLSFILL64rm 551836867U, // BLSFILL64rr 551900395U, // BLSI32rm 551834859U, // BLSI32rr 551918708U, // BLSI64rm 551836788U, // BLSI64rr 551900097U, // BLSIC32rm 551834561U, // BLSIC32rr 551918057U, // BLSIC64rm 551836137U, // BLSIC64rr 551900424U, // BLSMSK32rm 551834888U, // BLSMSK32rr 551918733U, // BLSMSK64rm 551836813U, // BLSMSK64rr 551900779U, // BLSR32rm 551835243U, // BLSR32rr 551919234U, // BLSR64rm 551837314U, // BLSR64rr 414636U, // BNDCL32rm 551834540U, // BNDCL32rr 414636U, // BNDCL64rm 551834540U, // BNDCL64rr 415819U, // BNDCN32rm 551835723U, // BNDCN32rr 415819U, // BNDCN64rm 551835723U, // BNDCN64rr 420276U, // BNDCU32rm 551840180U, // BNDCU32rr 420276U, // BNDCU64rm 551840180U, // BNDCU64rr 421867U, // BNDLDXrm 414548U, // BNDMK32rm 414548U, // BNDMK64rm 18917897U, // BNDMOV32mr 551922185U, // BNDMOV32rm 33597961U, // BNDMOV64mr 272905U, // BNDMOV64rm 551840265U, // BNDMOVrr 551840265U, // BNDMOVrr_REV 35696742U, // BNDSTXmr 1356876031U, // BOUNDS16rm 1625311487U, // BOUNDS32rm 437231U, // BSF16rm 551840751U, // BSF16rr 551900344U, // BSF32rm 551834808U, // BSF32rr 551918645U, // BSF64rm 551836725U, // BSF64rr 437666U, // BSR16rm 551841186U, // BSR16rr 551900773U, // BSR32rm 551835237U, // BSR32rr 551919228U, // BSR64rm 551837308U, // BSR64rr 27908U, // BSWAP16r_BAD 21937U, // BSWAP32r 23920U, // BSWAP64r 4239024U, // BT16mi8 4239024U, // BT16mr 551841456U, // BT16ri8 551841456U, // BT16rr 12621598U, // BT32mi8 12621598U, // BT32mr 551835422U, // BT32ri8 551835422U, // BT32rr 18915152U, // BT64mi8 18915152U, // BT64mr 551837520U, // BT64ri8 551837520U, // BT64rr 4238098U, // BTC16mi8 4238098U, // BTC16mr 6351634U, // BTC16ri8 6351634U, // BTC16rr 12620760U, // BTC32mi8 12620760U, // BTC32mr 6345688U, // BTC32ri8 6345688U, // BTC32rr 18913792U, // BTC64mi8 18913792U, // BTC64mr 6347264U, // BTC64ri8 6347264U, // BTC64rr 4238769U, // BTR16mi8 4238769U, // BTR16mr 6352305U, // BTR16ri8 6352305U, // BTR16rr 12621426U, // BTR32mi8 12621426U, // BTR32mr 6346354U, // BTR32ri8 6346354U, // BTR32rr 18914962U, // BTR64mi8 18914962U, // BTR64mr 6348434U, // BTR64ri8 6348434U, // BTR64rr 4238966U, // BTS16mi8 4238966U, // BTS16mr 6352502U, // BTS16ri8 6352502U, // BTS16rr 12621577U, // BTS32mi8 12621577U, // BTS32mr 6346505U, // BTS32ri8 6346505U, // BTS32rr 18915129U, // BTS64mi8 18915129U, // BTS64mr 6348601U, // BTS64ri8 6348601U, // BTS64rr 832902372U, // BZHI32rm 811652324U, // BZHI32rr 835001453U, // BZHI64rm 811654253U, // BZHI64rr 227528U, // CALL16m 227528U, // CALL16m_NT 30920U, // CALL16r 30920U, // CALL16r_NT 243878U, // CALL32m 243878U, // CALL32m_NT 30886U, // CALL32r 30886U, // CALL32r_NT 456887U, // CALL64m 456887U, // CALL64m_NT 466098U, // CALL64pcrel32 30903U, // CALL64r 30903U, // CALL64r_NT 470120U, // CALLpcrel16 464180U, // CALLpcrel32 15972U, // CBW 14982U, // CDQ 15491U, // CDQE 15776U, // CHS_F 0U, // CHS_Fp32 0U, // CHS_Fp64 0U, // CHS_Fp80 14904U, // CLAC 14936U, // CLC 14973U, // CLD 479759U, // CLDEMOTE 479872U, // CLFLUSH 485710U, // CLFLUSHOPT 15133U, // CLGI 15143U, // CLI 241839U, // CLRSSBSY 15844U, // CLTS 476848U, // CLWB 15335U, // CLZEROr 14940U, // CMC 8464973U, // CMOVA16rm 8448589U, // CMOVA16rr 551637865U, // CMOVA32rm 8442729U, // CMOVA32rr 551655804U, // CMOVA64rm 8444284U, // CMOVA64rr 8465331U, // CMOVAE16rm 8448947U, // CMOVAE16rr 551638083U, // CMOVAE32rm 8442947U, // CMOVAE32rr 551656375U, // CMOVAE64rm 8444855U, // CMOVAE64rr 8465107U, // CMOVB16rm 8448723U, // CMOVB16rr 551637910U, // CMOVB32rm 8442774U, // CMOVB32rr 551655855U, // CMOVB64rm 8444335U, // CMOVB64rr 8465340U, // CMOVBE16rm 8448956U, // CMOVBE16rr 551638092U, // CMOVBE32rm 8442956U, // CMOVBE32rr 551656384U, // CMOVBE64rm 8444864U, // CMOVBE64rr 37769640U, // CMOVBE_F 0U, // CMOVBE_Fp32 0U, // CMOVBE_Fp64 0U, // CMOVBE_Fp80 37766817U, // CMOVB_F 0U, // CMOVB_Fp32 0U, // CMOVB_Fp64 0U, // CMOVB_Fp80 8465376U, // CMOVE16rm 8448992U, // CMOVE16rr 551638192U, // CMOVE32rm 8443056U, // CMOVE32rr 551656493U, // CMOVE64rm 8444973U, // CMOVE64rr 37769780U, // CMOVE_F 0U, // CMOVE_Fp32 0U, // CMOVE_Fp64 0U, // CMOVE_Fp80 8465429U, // CMOVG16rm 8449045U, // CMOVG16rr 551638222U, // CMOVG32rm 8443086U, // CMOVG32rr 551656535U, // CMOVG64rm 8445015U, // CMOVG64rr 8465349U, // CMOVGE16rm 8448965U, // CMOVGE16rr 551638101U, // CMOVGE32rm 8442965U, // CMOVGE32rr 551656393U, // CMOVGE64rm 8444873U, // CMOVGE64rr 8465573U, // CMOVL16rm 8449189U, // CMOVL16rr 551638397U, // CMOVL32rm 8443261U, // CMOVL32rr 551656717U, // CMOVL64rm 8445197U, // CMOVL64rr 8465358U, // CMOVLE16rm 8448974U, // CMOVLE16rr 551638110U, // CMOVLE32rm 8442974U, // CMOVLE32rr 551656402U, // CMOVLE64rm 8444882U, // CMOVLE64rr 37769623U, // CMOVNBE_F 0U, // CMOVNBE_Fp32 0U, // CMOVNBE_Fp64 0U, // CMOVNBE_Fp80 37766372U, // CMOVNB_F 0U, // CMOVNB_Fp32 0U, // CMOVNB_Fp64 0U, // CMOVNB_Fp80 8465367U, // CMOVNE16rm 8448983U, // CMOVNE16rr 551638119U, // CMOVNE32rm 8442983U, // CMOVNE32rr 551656411U, // CMOVNE64rm 8444891U, // CMOVNE64rr 37769713U, // CMOVNE_F 0U, // CMOVNE_Fp32 0U, // CMOVNE_Fp64 0U, // CMOVNE_Fp80 8465651U, // CMOVNO16rm 8449267U, // CMOVNO16rr 551638432U, // CMOVNO32rm 8443296U, // CMOVNO32rr 551656799U, // CMOVNO64rm 8445279U, // CMOVNO64rr 8465691U, // CMOVNP16rm 8449307U, // CMOVNP16rr 551638494U, // CMOVNP32rm 8443358U, // CMOVNP32rr 551656839U, // CMOVNP64rm 8445319U, // CMOVNP64rr 37775803U, // CMOVNP_F 0U, // CMOVNP_Fp32 0U, // CMOVNP_Fp64 0U, // CMOVNP_Fp80 8465992U, // CMOVNS16rm 8449608U, // CMOVNS16rr 551638733U, // CMOVNS32rm 8443597U, // CMOVNS32rr 551657198U, // CMOVNS64rm 8445678U, // CMOVNS64rr 8465660U, // CMOVO16rm 8449276U, // CMOVO16rr 551638441U, // CMOVO32rm 8443305U, // CMOVO32rr 551656808U, // CMOVO64rm 8445288U, // CMOVO64rr 8465712U, // CMOVP16rm 8449328U, // CMOVP16rr 551638545U, // CMOVP32rm 8443409U, // CMOVP32rr 551656877U, // CMOVP64rm 8445357U, // CMOVP64rr 37775842U, // CMOVP_F 0U, // CMOVP_Fp32 0U, // CMOVP_Fp64 0U, // CMOVP_Fp80 8466079U, // CMOVS16rm 8449695U, // CMOVS16rr 551638806U, // CMOVS32rm 8443670U, // CMOVS32rr 551657279U, // CMOVS64rm 8445759U, // CMOVS64rr 2125070U, // CMP16i16 4238606U, // CMP16mi 4238606U, // CMP16mi8 4238606U, // CMP16mr 551841038U, // CMP16ri 551841038U, // CMP16ri8 437518U, // CMP16rm 551841038U, // CMP16rr 551841038U, // CMP16rr_REV 10507712U, // CMP32i32 12621248U, // CMP32mi 12621248U, // CMP32mi8 12621248U, // CMP32mr 551835072U, // CMP32ri 551835072U, // CMP32ri8 551900608U, // CMP32rm 551835072U, // CMP32rr 551835072U, // CMP32rr_REV 16801153U, // CMP64i32 18914689U, // CMP64mi32 18914689U, // CMP64mi8 18914689U, // CMP64mr 551837057U, // CMP64ri32 551837057U, // CMP64ri8 551918977U, // CMP64rm 551837057U, // CMP64rr 551837057U, // CMP64rr_REV 20989167U, // CMP8i8 23102703U, // CMP8mi 23102703U, // CMP8mi8 23102703U, // CMP8mr 551830767U, // CMP8ri 551830767U, // CMP8ri8 492783U, // CMP8rm 551830767U, // CMP8rr 551830767U, // CMP8rr_REV 1919417349U, // CMPPDrmi 568708192U, // CMPPDrmi_alt 1114127365U, // CMPPDrri 1088818272U, // CMPPDrri_alt 1921514501U, // CMPPSrmi 568714649U, // CMPPSrmi_alt 1116224517U, // CMPPSrri 1088824729U, // CMPPSrri_alt 2162705875U, // CMPSB 2460482565U, // CMPSDrm 2460482565U, // CMPSDrm_Int 851824504U, // CMPSDrm_alt 1118321669U, // CMPSDrr 1118321669U, // CMPSDrr_Int 1088819064U, // CMPSDrr_alt 2699597526U, // CMPSL 2968051447U, // CMPSQ 3269983237U, // CMPSSrm 3269983237U, // CMPSSrm_Int 856025225U, // CMPSSrm_alt 1122515973U, // CMPSSrr 1122515973U, // CMPSSrr_Int 1088825481U, // CMPSSrr_alt 3504942673U, // CMPSW 607124U, // CMPXCHG16B 4238339U, // CMPXCHG16rm 551840771U, // CMPXCHG16rr 12620996U, // CMPXCHG32rm 551834820U, // CMPXCHG32rr 18914369U, // CMPXCHG64rm 551836737U, // CMPXCHG64rr 443296U, // CMPXCHG8B 23102520U, // CMPXCHG8rm 551830584U, // CMPXCHG8rr 552177472U, // COMISDrm 552177472U, // COMISDrm_Int 551833408U, // COMISDrr 551833408U, // COMISDrr_Int 552200274U, // COMISSrm 552200274U, // COMISSrm_Int 551839826U, // COMISSrr 551839826U, // COMISSrr_Int 22707U, // COMP_FST0r 21186U, // COM_FIPr 21129U, // COM_FIr 22558U, // COM_FST0r 15793U, // COS_F 0U, // COS_Fp32 0U, // COS_Fp64 0U, // COS_Fp80 14967U, // CPUID 15347U, // CQO 6367761U, // CRC32r32m16 283202395U, // CRC32r32m32 6407011U, // CRC32r32m8 6351377U, // CRC32r32r16 6345563U, // CRC32r32r32 6341475U, // CRC32r32r8 283220262U, // CRC32r64m64 6407011U, // CRC32r64m8 6347046U, // CRC32r64r64 6341475U, // CRC32r64r8 551913949U, // CVTDQ2PDrm 551832029U, // CVTDQ2PDrr 271085U, // CVTDQ2PSrm 551838445U, // CVTDQ2PSrr 662035U, // CVTPD2DQrm 551836179U, // CVTPD2DQrr 664237U, // CVTPD2PSrm 551838381U, // CVTPD2PSrr 662067U, // CVTPS2DQrm 551836211U, // CVTPS2DQrr 552176139U, // CVTPS2PDrm 551832075U, // CVTPS2PDrr 552178433U, // CVTSD2SI64rm_Int 551834369U, // CVTSD2SI64rr_Int 552178433U, // CVTSD2SIrm_Int 551834369U, // CVTSD2SIrr_Int 552183644U, // CVTSD2SSrm 551708508U, // CVTSD2SSrm_Int 551839580U, // CVTSD2SSrr 8447836U, // CVTSD2SSrr_Int 551900203U, // CVTSI2SDrm 551638059U, // CVTSI2SDrm_Int 551834667U, // CVTSI2SDrr 8442923U, // CVTSI2SDrr_Int 551900907U, // CVTSI2SSrm 551638763U, // CVTSI2SSrm_Int 551835371U, // CVTSI2SSrr 8443627U, // CVTSI2SSrr_Int 551918392U, // CVTSI642SDrm 551656248U, // CVTSI642SDrm_Int 551836472U, // CVTSI642SDrr 8444728U, // CVTSI642SDrr_Int 551919359U, // CVTSI642SSrm 551657215U, // CVTSI642SSrm_Int 551837439U, // CVTSI642SSrr 8445695U, // CVTSI642SSrr_Int 552193625U, // CVTSS2SDrm 551718489U, // CVTSS2SDrm_Int 551833177U, // CVTSS2SDrr 8441433U, // CVTSS2SDrr_Int 552194840U, // CVTSS2SI64rm_Int 551834392U, // CVTSS2SI64rr_Int 552194840U, // CVTSS2SIrm_Int 551834392U, // CVTSS2SIrr_Int 662023U, // CVTTPD2DQrm 551836167U, // CVTTPD2DQrr 662055U, // CVTTPS2DQrm 551836199U, // CVTTPS2DQrr 552178421U, // CVTTSD2SI64rm 552178421U, // CVTTSD2SI64rm_Int 551834357U, // CVTTSD2SI64rr 551834357U, // CVTTSD2SI64rr_Int 552178421U, // CVTTSD2SIrm 552178421U, // CVTTSD2SIrm_Int 551834357U, // CVTTSD2SIrr 551834357U, // CVTTSD2SIrr_Int 552194828U, // CVTTSS2SI64rm 552194828U, // CVTTSS2SI64rm_Int 551834380U, // CVTTSS2SI64rr 551834380U, // CVTTSS2SI64rr_Int 552194828U, // CVTTSS2SIrm 552194828U, // CVTTSS2SIrm_Int 551834380U, // CVTTSS2SIrr 551834380U, // CVTTSS2SIrr_Int 14991U, // CWD 15276U, // CWDE 14864U, // DAA 15550U, // DAS 14790U, // DATA16_PREFIX 224006U, // DEC16m 27398U, // DEC16r 27398U, // DEC16r_alt 234419U, // DEC32m 21427U, // DEC32r 21427U, // DEC32r_alt 448987U, // DEC64m 23003U, // DEC64r 476103U, // DEC8m 17351U, // DEC8r 225170U, // DIV16m 28562U, // DIV16r 235413U, // DIV32m 22421U, // DIV32r 450645U, // DIV64m 24661U, // DIV64r 476827U, // DIV8m 18075U, // DIV8r 8523071U, // DIVPDrm 8441151U, // DIVPDrr 8529568U, // DIVPSrm 8447648U, // DIVPSrr 190174U, // DIVR_F32m 202374U, // DIVR_F64m 222950U, // DIVR_FI16m 235150U, // DIVR_FI32m 22815U, // DIVR_FPrST0 24937U, // DIVR_FST0r 0U, // DIVR_Fp32m 0U, // DIVR_Fp64m 0U, // DIVR_Fp64m32 0U, // DIVR_Fp80m32 0U, // DIVR_Fp80m64 0U, // DIVR_FpI16m32 0U, // DIVR_FpI16m64 0U, // DIVR_FpI16m80 0U, // DIVR_FpI32m32 0U, // DIVR_FpI32m64 0U, // DIVR_FpI32m80 29042U, // DIVR_FrST0 551702526U, // DIVSDrm 551702526U, // DIVSDrm_Int 8441854U, // DIVSDrr 8441854U, // DIVSDrr_Int 551725278U, // DIVSSrm 551725278U, // DIVSSrm_Int 8448222U, // DIVSSrr 8448222U, // DIVSSrr_Int 190737U, // DIV_F32m 202644U, // DIV_F64m 223512U, // DIV_FI16m 235419U, // DIV_FI32m 22753U, // DIV_FPrST0 27114U, // DIV_FST0r 0U, // DIV_Fp32 0U, // DIV_Fp32m 0U, // DIV_Fp64 0U, // DIV_Fp64m 0U, // DIV_Fp64m32 0U, // DIV_Fp80 0U, // DIV_Fp80m32 0U, // DIV_Fp80m64 0U, // DIV_FpI16m32 0U, // DIV_FpI16m64 0U, // DIV_FpI16m80 0U, // DIV_FpI32m32 0U, // DIV_FpI32m64 0U, // DIV_FpI32m80 29027U, // DIV_FrST0 568708185U, // DPPDrmi 1088818265U, // DPPDrri 568714642U, // DPPSrmi 1088824722U, // DPPSrri 15781U, // ENCLS 15906U, // ENCLU 15940U, // ENCLV 14745U, // ENDBR32 14776U, // ENDBR64 283140374U, // ENTER 3810829867U, // EXTRACTPSmr 283436587U, // EXTRACTPSrr 6348457U, // EXTRQ 4041612969U, // EXTRQI 14726U, // F2XM1 551840871U, // FARCALL16i 686279U, // FARCALL16m 551834931U, // FARCALL32i 686245U, // FARCALL32m 686262U, // FARCALL64 54816020U, // FARJMP16i 686288U, // FARJMP16m 54810054U, // FARJMP32i 686254U, // FARJMP32m 686271U, // FARJMP64 702596U, // FBLDm 702612U, // FBSTPm 188893U, // FCOM32m 202117U, // FCOM64m 189790U, // FCOMP32m 202189U, // FCOMP64m 15406U, // FCOMPP 15433U, // FDECSTP 15387U, // FDISI8087_NOP 15787U, // FEMMS 15374U, // FENI8087_NOP 20913U, // FFREE 22683U, // FFREEP 221668U, // FICOM16m 234892U, // FICOM32m 222566U, // FICOMP16m 234965U, // FICOMP32m 15441U, // FINCSTP 223999U, // FLDCW16m 190960U, // FLDENVm 15012U, // FLDL2E 15849U, // FLDL2T 14757U, // FLDLG2 14764U, // FLDLN2 15147U, // FLDPI 16196U, // FNCLEX 15870U, // FNINIT 15401U, // FNOP 224024U, // FNSTCW16m 15995U, // FNSTSW16r 224892U, // FNSTSWm 15317U, // FPATAN 28981U, // FPNCEST0r 15294U, // FPREM 14719U, // FPREM1 15324U, // FPTAN 15881U, // FRNDINT 188727U, // FRSTORm 184868U, // FSAVEm 15040U, // FSCALE 15306U, // FSETPM 15798U, // FSINCOS 190968U, // FSTENVm 15289U, // FXAM 680255U, // FXRSTOR 672071U, // FXRSTOR64 676396U, // FXSAVE 672061U, // FXSAVE64 15856U, // FXTRACT 15989U, // FYL2X 14732U, // FYL2XP1 14924U, // GETSEC 593872181U, // GF2P8AFFINEINVQBrmi 1088816437U, // GF2P8AFFINEINVQBrri 593872118U, // GF2P8AFFINEQBrmi 1088816374U, // GF2P8AFFINEQBrri 8635518U, // GF2P8MULBrm 8438910U, // GF2P8MULBrr 8522557U, // HADDPDrm 8440637U, // HADDPDrr 8528954U, // HADDPSrm 8447034U, // HADDPSrr 15877U, // HLT 8522444U, // HSUBPDrm 8440524U, // HSUBPDrr 8528841U, // HSUBPSrm 8446921U, // HSUBPSrr 225169U, // IDIV16m 28561U, // IDIV16r 235420U, // IDIV32m 22428U, // IDIV32r 450644U, // IDIV64m 24660U, // IDIV64r 476826U, // IDIV8m 18074U, // IDIV8r 221588U, // ILD_F16m 234515U, // ILD_F32m 447781U, // ILD_F64m 0U, // ILD_Fp16m32 0U, // ILD_Fp16m64 0U, // ILD_Fp16m80 0U, // ILD_Fp32m32 0U, // ILD_Fp32m64 0U, // ILD_Fp32m80 0U, // ILD_Fp64m32 0U, // ILD_Fp64m64 0U, // ILD_Fp64m80 224414U, // IMUL16m 27806U, // IMUL16r 8465566U, // IMUL16rm 59059358U, // IMUL16rmi 59059358U, // IMUL16rmi8 8449182U, // IMUL16rr 811658398U, // IMUL16rri 811658398U, // IMUL16rri8 234870U, // IMUL32m 21878U, // IMUL32r 551638390U, // IMUL32rm 832902518U, // IMUL32rmi 832902518U, // IMUL32rmi8 8443254U, // IMUL32rr 811652470U, // IMUL32rri 811652470U, // IMUL32rri8 449798U, // IMUL64m 23814U, // IMUL64r 551656710U, // IMUL64rm 835001606U, // IMUL64rmi32 835001606U, // IMUL64rmi8 8445190U, // IMUL64rr 811654406U, // IMUL64rri32 811654406U, // IMUL64rri8 476297U, // IMUL8m 17545U, // IMUL8r 2813166U, // IN16ri 16006U, // IN16rr 11195803U, // IN32ri 16066U, // IN32rr 21677279U, // IN8ri 15162U, // IN8rr 224012U, // INC16m 27404U, // INC16r 27404U, // INC16r_alt 234450U, // INC32m 21458U, // INC32r 21458U, // INC32r_alt 449018U, // INC64m 23034U, // INC64r 476109U, // INC8m 17357U, // INC8r 19684U, // INCSSPD 23964U, // INCSSPQ 554385U, // INSB 856024653U, // INSERTPSrm 1088824909U, // INSERTPSrr 6348745U, // INSERTQ 15409097U, // INSERTQI 570780U, // INSL 603559U, // INSW 715063U, // INT 14740U, // INT1 14771U, // INT3 15342U, // INTO 14998U, // INVD 272700U, // INVEPT32 272700U, // INVEPT64 479808U, // INVLPG 16115U, // INVLPGA32 16134U, // INVLPGA64 264267U, // INVPCID32 264267U, // INVPCID64 264283U, // INVVPID32 264283U, // INVVPID64 15977U, // IRET16 15247U, // IRET32 15462U, // IRET64 222850U, // ISTT_FP16m 235016U, // ISTT_FP32m 447838U, // ISTT_FP64m 0U, // ISTT_Fp16m32 0U, // ISTT_Fp16m64 0U, // ISTT_Fp16m80 0U, // ISTT_Fp32m32 0U, // ISTT_Fp32m64 0U, // ISTT_Fp32m80 0U, // ISTT_Fp64m32 0U, // ISTT_Fp64m64 0U, // ISTT_Fp64m80 223498U, // IST_F16m 235391U, // IST_F32m 222842U, // IST_FP16m 235008U, // IST_FP32m 447829U, // IST_FP64m 0U, // IST_Fp16m32 0U, // IST_Fp16m64 0U, // IST_Fp16m80 0U, // IST_Fp32m32 0U, // IST_Fp32m64 0U, // IST_Fp32m80 0U, // IST_Fp64m32 0U, // IST_Fp64m64 0U, // IST_Fp64m80 463238U, // JAE_1 463238U, // JAE_2 463238U, // JAE_4 459576U, // JA_1 459576U, // JA_2 459576U, // JA_4 463250U, // JBE_1 463250U, // JBE_2 463250U, // JBE_4 459850U, // JB_1 459850U, // JB_2 459850U, // JB_4 471308U, // JCXZ 471301U, // JECXZ 463309U, // JE_1 463309U, // JE_2 463309U, // JE_4 463288U, // JGE_1 463288U, // JGE_2 463288U, // JGE_4 463420U, // JG_1 463420U, // JG_2 463420U, // JG_4 463313U, // JLE_1 463313U, // JLE_2 463313U, // JLE_4 464123U, // JL_1 464123U, // JL_2 464123U, // JL_4 227537U, // JMP16m 227537U, // JMP16m_NT 30929U, // JMP16r 30929U, // JMP16r_NT 243887U, // JMP32m 243887U, // JMP32m_NT 30895U, // JMP32r 30895U, // JMP32r_NT 456896U, // JMP64m 456896U, // JMP64m_NT 30912U, // JMP64r 30912U, // JMP64r_NT 465070U, // JMP_1 465070U, // JMP_2 465070U, // JMP_4 463325U, // JNE_1 463325U, // JNE_2 463325U, // JNE_4 465012U, // JNO_1 465012U, // JNO_2 465012U, // JNO_4 465090U, // JNP_1 465090U, // JNP_2 465090U, // JNP_4 467444U, // JNS_1 467444U, // JNS_2 467444U, // JNS_4 465008U, // JO_1 465008U, // JO_2 465008U, // JO_4 465059U, // JP_1 465059U, // JP_2 465059U, // JP_4 471314U, // JRCXZ 467402U, // JS_1 467402U, // JS_2 467402U, // JS_4 811647971U, // KADDBrr 811648949U, // KADDDrr 811653712U, // KADDQrr 811658025U, // KADDWrr 811647993U, // KANDBrr 811648973U, // KANDDrr 811648206U, // KANDNBrr 811649244U, // KANDNDrr 811654469U, // KANDNQrr 811658461U, // KANDNWrr 811653823U, // KANDQrr 811658065U, // KANDWrr 551831209U, // KMOVBkk 493225U, // KMOVBkm 551831209U, // KMOVBkr 23103145U, // KMOVBmk 551831209U, // KMOVBrk 551833826U, // KMOVDkk 551899362U, // KMOVDkm 551833826U, // KMOVDkr 12620002U, // KMOVDmk 551833826U, // KMOVDrk 551837819U, // KMOVQkk 551919739U, // KMOVQkm 551837819U, // KMOVQkr 18915451U, // KMOVQmk 551837819U, // KMOVQrk 551841706U, // KMOVWkk 438186U, // KMOVWkm 551841706U, // KMOVWkr 4239274U, // KMOVWmk 551841706U, // KMOVWrk 551831093U, // KNOTBrr 551833682U, // KNOTDrr 551837626U, // KNOTQrr 551841546U, // KNOTWrr 811648354U, // KORBrr 811650468U, // KORDrr 811654736U, // KORQrr 551831130U, // KORTESTBrr 551833719U, // KORTESTDrr 551837672U, // KORTESTQrr 551841583U, // KORTESTWrr 811658631U, // KORWrr 283427955U, // KSHIFTLBri 283429019U, // KSHIFTLDri 283434236U, // KSHIFTLQri 283438228U, // KSHIFTLWri 283428230U, // KSHIFTRBri 283430361U, // KSHIFTRDri 283434648U, // KSHIFTRQri 283438519U, // KSHIFTRWri 551831122U, // KTESTBrr 551833711U, // KTESTDrr 551837664U, // KTESTQrr 551841575U, // KTESTWrr 811657881U, // KUNPCKBWrr 811653765U, // KUNPCKDQrr 811651363U, // KUNPCKWDrr 811648360U, // KXNORBrr 811650474U, // KXNORDrr 811654742U, // KXNORQrr 811658637U, // KXNORWrr 811648374U, // KXORBrr 811650497U, // KXORDrr 811654765U, // KXORQrr 811658651U, // KXORWrr 15106U, // LAHF 437600U, // LAR16rm 551841120U, // LAR16rr 431664U, // LAR32rm 551835184U, // LAR32rr 433720U, // LAR64rm 551837240U, // LAR64rr 272837U, // LDDQUrm 237910U, // LDMXCSR 749088U, // LDS16rm 743086U, // LDS32rm 16228U, // LD_F0 14710U, // LD_F1 188814U, // LD_F32m 201734U, // LD_F64m 698656U, // LD_F80m 0U, // LD_Fp032 0U, // LD_Fp064 0U, // LD_Fp080 0U, // LD_Fp132 0U, // LD_Fp164 0U, // LD_Fp180 0U, // LD_Fp32m 0U, // LD_Fp32m64 0U, // LD_Fp32m80 0U, // LD_Fp64m 0U, // LD_Fp64m80 0U, // LD_Fp80m 18532U, // LD_Frr 420407U, // LEA16r 414563U, // LEA32r 414563U, // LEA64_32r 416102U, // LEA64r 15093U, // LEAVE 15093U, // LEAVE64 749101U, // LES16rm 743099U, // LES32rm 15019U, // LFENCE 749107U, // LFS16rm 743105U, // LFS32rm 745183U, // LFS64rm 683701U, // LGDT16m 677667U, // LGDT32m 679778U, // LGDT64m 749113U, // LGS16rm 743111U, // LGS32rm 745925U, // LGS64rm 683715U, // LIDT16m 677681U, // LIDT32m 679792U, // LIDT64m 224977U, // LLDT16m 28369U, // LLDT16r 17363U, // LLWPCB 17363U, // LLWPCB64 225211U, // LMSW16m 28603U, // LMSW16r 15157U, // LOCK_PREFIX 21726659U, // LODSB 11261620U, // LODSL 794328U, // LODSQ 2911782U, // LODSW 465107U, // LOOP 463354U, // LOOPE 463330U, // LOOPNE 22342U, // LRETIL 24453U, // LRETIQ 28383U, // LRETIW 15253U, // LRETL 15468U, // LRETQ 15983U, // LRETW 437390U, // LSL16rm 551840910U, // LSL16rr 431464U, // LSL32rm 551834984U, // LSL32rr 433390U, // LSL64rm 551836910U, // LSL64rr 749168U, // LSS16rm 743171U, // LSS32rm 745252U, // LSS64rm 224705U, // LTRm 28097U, // LTRr 832905708U, // LWPINS32rmi 811655660U, // LWPINS32rri 832905708U, // LWPINS64rmi 811655660U, // LWPINS64rri 832902001U, // LWPVAL32rmi 811651953U, // LWPVAL32rri 832902001U, // LWPVAL64rmi 811651953U, // LWPVAL64rri 438010U, // LZCNT16rm 551841530U, // LZCNT16rr 551901020U, // LZCNT32rm 551835484U, // LZCNT32rr 551919522U, // LZCNT64rm 551837602U, // LZCNT64rr 551840205U, // MASKMOVDQU 551840205U, // MASKMOVDQU64 8523091U, // MAXCPDrm 8441171U, // MAXCPDrr 8529588U, // MAXCPSrm 8447668U, // MAXCPSrr 551702543U, // MAXCSDrm 8441871U, // MAXCSDrr 551725294U, // MAXCSSrm 8448238U, // MAXCSSrr 8523091U, // MAXPDrm 8441171U, // MAXPDrr 8529588U, // MAXPSrm 8447668U, // MAXPSrr 551702543U, // MAXSDrm 551702543U, // MAXSDrm_Int 8441871U, // MAXSDrr 8441871U, // MAXSDrr_Int 551725294U, // MAXSSrm 551725294U, // MAXSSrm_Int 8448238U, // MAXSSrr 8448238U, // MAXSSrr_Int 15026U, // MFENCE 8522833U, // MINCPDrm 8440913U, // MINCPDrr 8529282U, // MINCPSrm 8447362U, // MINCPSrr 551702376U, // MINCSDrm 8441704U, // MINCSDrr 551725177U, // MINCSSrm 8448121U, // MINCSSrr 8522833U, // MINPDrm 8440913U, // MINPDrr 8529282U, // MINPSrm 8447362U, // MINPSrr 551702376U, // MINSDrm 551702376U, // MINSDrm_Int 8441704U, // MINSDrr 8441704U, // MINSDrr_Int 551725177U, // MINSSrm 551725177U, // MINSSrm_Int 8448121U, // MINSSrr 8448121U, // MINSSrr_Int 660131U, // MMX_CVTPD2PIirm 551834275U, // MMX_CVTPD2PIirr 551913917U, // MMX_CVTPI2PDirm 551831997U, // MMX_CVTPI2PDirr 551658189U, // MMX_CVTPI2PSirm 8446669U, // MMX_CVTPI2PSirr 552178360U, // MMX_CVTPS2PIirm 551834296U, // MMX_CVTPS2PIirr 660120U, // MMX_CVTTPD2PIirm 551834264U, // MMX_CVTTPD2PIirr 552178349U, // MMX_CVTTPS2PIirm 551834285U, // MMX_CVTTPS2PIirr 15788U, // MMX_EMMS 551837816U, // MMX_MASKMOVQ 551837816U, // MMX_MASKMOVQ64 18915452U, // MMX_MOVD64from64rm 551837820U, // MMX_MOVD64from64rr 551833827U, // MMX_MOVD64grr 12620003U, // MMX_MOVD64mr 551899363U, // MMX_MOVD64rm 551833827U, // MMX_MOVD64rr 551919740U, // MMX_MOVD64to64rm 551837820U, // MMX_MOVD64to64rr 551835987U, // MMX_MOVDQ2Qrr 551835987U, // MMX_MOVFR642Qrr 18915250U, // MMX_MOVNTQmr 551836189U, // MMX_MOVQ2DQrr 551836189U, // MMX_MOVQ2FR64rr 18915452U, // MMX_MOVQ64mr 551919740U, // MMX_MOVQ64rm 551837820U, // MMX_MOVQ64rr 551837820U, // MMX_MOVQ64rr_REV 551912865U, // MMX_PABSBrm 551830945U, // MMX_PABSBrr 551915206U, // MMX_PABSDrm 551833286U, // MMX_PABSDrr 551923166U, // MMX_PABSWrm 551841246U, // MMX_PABSWrr 551660416U, // MMX_PACKSSDWirm 8448896U, // MMX_PACKSSDWirr 551650999U, // MMX_PACKSSWBirm 8439479U, // MMX_PACKSSWBirr 551651010U, // MMX_PACKUSWBirm 8439490U, // MMX_PACKUSWBirr 551650283U, // MMX_PADDBirm 8438763U, // MMX_PADDBirr 551651261U, // MMX_PADDDirm 8439741U, // MMX_PADDDirr 551656024U, // MMX_PADDQirm 8444504U, // MMX_PADDQirr 551650747U, // MMX_PADDSBirm 8439227U, // MMX_PADDSBirr 551661080U, // MMX_PADDSWirm 8449560U, // MMX_PADDSWirr 551650809U, // MMX_PADDUSBirm 8439289U, // MMX_PADDUSBirr 551661206U, // MMX_PADDUSWirm 8449686U, // MMX_PADDUSWirr 551660337U, // MMX_PADDWirm 8448817U, // MMX_PADDWirr 866509086U, // MMX_PALIGNRrmi 1088823582U, // MMX_PALIGNRrri 551655507U, // MMX_PANDNirm 8443987U, // MMX_PANDNirr 551651542U, // MMX_PANDirm 8440022U, // MMX_PANDirr 551650371U, // MMX_PAVGBirm 8438851U, // MMX_PAVGBirr 551660558U, // MMX_PAVGWirm 8449038U, // MMX_PAVGWirr 551650566U, // MMX_PCMPEQBirm 8439046U, // MMX_PCMPEQBirr 551652708U, // MMX_PCMPEQDirm 8441188U, // MMX_PCMPEQDirr 551660857U, // MMX_PCMPEQWirm 8449337U, // MMX_PCMPEQWirr 551650850U, // MMX_PCMPGTBirm 8439330U, // MMX_PCMPGTBirr 551653429U, // MMX_PCMPGTDirm 8441909U, // MMX_PCMPGTDirr 551661287U, // MMX_PCMPGTWirm 8449767U, // MMX_PCMPGTWirr 283438542U, // MMX_PEXTRWrr 551651245U, // MMX_PHADDDrm 8439725U, // MMX_PHADDDrr 551661070U, // MMX_PHADDSWrm 8449550U, // MMX_PHADDSWrr 551660321U, // MMX_PHADDWrm 8448801U, // MMX_PHADDWrr 551651199U, // MMX_PHSUBDrm 8439679U, // MMX_PHSUBDrr 551661051U, // MMX_PHSUBSWrm 8449531U, // MMX_PHSUBSWrr 551660227U, // MMX_PHSUBWrm 8448707U, // MMX_PHSUBWrr 600173993U, // MMX_PINSRWrm 1088826793U, // MMX_PINSRWrr 551661039U, // MMX_PMADDUBSWrm 8449519U, // MMX_PMADDUBSWrr 551653646U, // MMX_PMADDWDirm 8442126U, // MMX_PMADDWDirr 551661224U, // MMX_PMAXSWirm 8449704U, // MMX_PMAXSWirr 551650951U, // MMX_PMAXUBirm 8439431U, // MMX_PMAXUBirr 551661120U, // MMX_PMINSWirm 8449600U, // MMX_PMINSWirr 551650926U, // MMX_PMINUBirm 8439406U, // MMX_PMINUBirr 551830607U, // MMX_PMOVMSKBrr 551661145U, // MMX_PMULHRSWrm 8449625U, // MMX_PMULHRSWrr 551661370U, // MMX_PMULHUWirm 8449850U, // MMX_PMULHUWirr 551660595U, // MMX_PMULHWirm 8449075U, // MMX_PMULHWirr 551660664U, // MMX_PMULLWirm 8449144U, // MMX_PMULLWirr 551656344U, // MMX_PMULUDQirm 8444824U, // MMX_PMULUDQirr 551657768U, // MMX_PORirm 8446248U, // MMX_PORirr 551660136U, // MMX_PSADBWirm 8448616U, // MMX_PSADBWirr 551650346U, // MMX_PSHUFBrm 8438826U, // MMX_PSHUFBrr 834972661U, // MMX_PSHUFWmi 283438069U, // MMX_PSHUFWri 551650519U, // MMX_PSIGNBrm 8438999U, // MMX_PSIGNBrr 551651575U, // MMX_PSIGNDrm 8440055U, // MMX_PSIGNDrr 551660774U, // MMX_PSIGNWrm 8449254U, // MMX_PSIGNWrr 551864434U, // MMX_PSLLDri 551651442U, // MMX_PSLLDrm 8439922U, // MMX_PSLLDrr 551869646U, // MMX_PSLLQri 551656654U, // MMX_PSLLQrm 8445134U, // MMX_PSLLQrr 551873648U, // MMX_PSLLWri 551660656U, // MMX_PSLLWrm 8449136U, // MMX_PSLLWrr 551864162U, // MMX_PSRADri 551651170U, // MMX_PSRADrm 8439650U, // MMX_PSRADrr 551873094U, // MMX_PSRAWri 551660102U, // MMX_PSRAWrm 8448582U, // MMX_PSRAWrr 551864459U, // MMX_PSRLDri 551651467U, // MMX_PSRLDrm 8439947U, // MMX_PSRLDrr 551869671U, // MMX_PSRLQri 551656679U, // MMX_PSRLQrm 8445159U, // MMX_PSRLQrr 551873671U, // MMX_PSRLWri 551660679U, // MMX_PSRLWrm 8449159U, // MMX_PSRLWrr 551650234U, // MMX_PSUBBirm 8438714U, // MMX_PSUBBirr 551651208U, // MMX_PSUBDirm 8439688U, // MMX_PSUBDirr 551655848U, // MMX_PSUBQirm 8444328U, // MMX_PSUBQirr 551650738U, // MMX_PSUBSBirm 8439218U, // MMX_PSUBSBirr 551661061U, // MMX_PSUBSWirm 8449541U, // MMX_PSUBSWirr 551650799U, // MMX_PSUBUSBirm 8439279U, // MMX_PSUBUSBirr 551661196U, // MMX_PSUBUSWirm 8449676U, // MMX_PSUBUSWirr 551660236U, // MMX_PSUBWirm 8448716U, // MMX_PSUBWirr 551660174U, // MMX_PUNPCKHBWirm 8448654U, // MMX_PUNPCKHBWirr 551656058U, // MMX_PUNPCKHDQirm 8444538U, // MMX_PUNPCKHDQirr 551653656U, // MMX_PUNPCKHWDirm 8442136U, // MMX_PUNPCKHWDirr 551643812U, // MMX_PUNPCKLBWirm 8448676U, // MMX_PUNPCKLBWirr 551639705U, // MMX_PUNPCKLDQirm 8444569U, // MMX_PUNPCKLDQirr 551637294U, // MMX_PUNPCKLWDirm 8442158U, // MMX_PUNPCKLWDirr 551657801U, // MMX_PXORirm 8446281U, // MMX_PXORirr 16203U, // MONITORXrrr 15516U, // MONITORrrr 15281U, // MONTMUL 2928555U, // MOV16ao16 2928555U, // MOV16ao32 2928101U, // MOV16ao64 4239275U, // MOV16mi 4239275U, // MOV16mr 4239275U, // MOV16ms 832784U, // MOV16o16a 832784U, // MOV16o32a 832747U, // MOV16o64a 551841707U, // MOV16ri 551841707U, // MOV16ri_alt 438187U, // MOV16rm 551841707U, // MOV16rr 551841707U, // MOV16rr_REV 551841707U, // MOV16rs 438187U, // MOV16sm 551841707U, // MOV16sr 11327395U, // MOV32ao16 11327395U, // MOV32ao32 11327134U, // MOV32ao64 551835555U, // MOV32cr 551835555U, // MOV32dr 12621731U, // MOV32mi 12621731U, // MOV32mr 849232U, // MOV32o16a 849232U, // MOV32o32a 849192U, // MOV32o64a 551835555U, // MOV32rc 551835555U, // MOV32rd 551835555U, // MOV32ri 551835555U, // MOV32ri_alt 551901091U, // MOV32rm 551835555U, // MOV32rr 551835555U, // MOV32rr_REV 551835555U, // MOV32rs 551835555U, // MOV32sr 17637500U, // MOV64ao32 17637064U, // MOV64ao64 551837820U, // MOV64cr 551837820U, // MOV64dr 18915452U, // MOV64mi32 18915452U, // MOV64mr 865669U, // MOV64o32a 865641U, // MOV64o64a 551837820U, // MOV64rc 551837820U, // MOV64rd 551837384U, // MOV64ri 551837820U, // MOV64ri32 551919740U, // MOV64rm 551837820U, // MOV64rr 551837820U, // MOV64rr_REV 551837820U, // MOV64rs 551837820U, // MOV64sr 551919740U, // MOV64toPQIrm 551837820U, // MOV64toPQIrr 551919740U, // MOV64toSDrm 551837820U, // MOV64toSDrr 21841571U, // MOV8ao16 21841571U, // MOV8ao32 21841320U, // MOV8ao64 23103139U, // MOV8mi 23103139U, // MOV8mr 23103139U, // MOV8mr_NOREX 881452U, // MOV8o16a 881452U, // MOV8o32a 881415U, // MOV8o64a 551831203U, // MOV8ri 551831203U, // MOV8ri_alt 493219U, // MOV8rm 493219U, // MOV8rm_NOREX 551831203U, // MOV8rr 551831203U, // MOV8rr_NOREX 551831203U, // MOV8rr_REV 65047203U, // MOVAPDmr 658083U, // MOVAPDrm 551832227U, // MOVAPDrr 551832227U, // MOVAPDrr_REV 65053608U, // MOVAPSmr 664488U, // MOVAPSrm 551838632U, // MOVAPSrr 551838632U, // MOVAPSrr_REV 4238269U, // MOVBE16mr 437181U, // MOVBE16rm 12620877U, // MOVBE32mr 551900237U, // MOVBE32rm 18914241U, // MOVBE64mr 551918529U, // MOVBE64rm 552179968U, // MOVDDUPrm 551835904U, // MOVDDUPrr 551899363U, // MOVDI2PDIrm 551833827U, // MOVDI2PDIrr 551899363U, // MOVDI2SSrm 551833827U, // MOVDI2SSrr 552436617U, // MOVDIR64B16 552436617U, // MOVDIR64B32 552436617U, // MOVDIR64B64 12620499U, // MOVDIRI32 18911955U, // MOVDIRI64 33588040U, // MOVDQAmr 262984U, // MOVDQArm 551830344U, // MOVDQArr 551830344U, // MOVDQArr_REV 33597905U, // MOVDQUmr 272849U, // MOVDQUrm 551840209U, // MOVDQUrr 551840209U, // MOVDQUrr_REV 8447254U, // MOVHLPSrr 67144676U, // MOVHPDmr 551701476U, // MOVHPDrm 67151106U, // MOVHPSmr 551707906U, // MOVHPSrm 8447224U, // MOVLHPSrr 67144726U, // MOVLPDmr 551701526U, // MOVLPDrm 67151166U, // MOVLPSmr 551707966U, // MOVLPSrm 551832557U, // MOVMSKPDrr 551838987U, // MOVMSKPSrr 262973U, // MOVNTDQArm 65051473U, // MOVNTDQmr 18914427U, // MOVNTI_64mr 12621042U, // MOVNTImr 65047823U, // MOVNTPDmr 65054275U, // MOVNTPSmr 67145683U, // MOVNTSD 69249203U, // MOVNTSS 12620003U, // MOVPDI2DImr 551833827U, // MOVPDI2DIrr 18915452U, // MOVPQI2QImr 551837820U, // MOVPQI2QIrr 18915452U, // MOVPQIto64mr 551837820U, // MOVPQIto64rr 551919740U, // MOVQI2PQIrm 902667U, // MOVSB 67145734U, // MOVSDmr 552177670U, // MOVSDrm 8441862U, // MOVSDrr 8441862U, // MOVSDrr_REV 18915452U, // MOVSDto64mr 551837820U, // MOVSDto64rr 661770U, // MOVSHDUPrm 551835914U, // MOVSHDUPrr 923415U, // MOVSL 661781U, // MOVSLDUPrm 551835925U, // MOVSLDUPrr 941888U, // MOVSQ 12620003U, // MOVSS2DImr 551833827U, // MOVSS2DIrr 69249254U, // MOVSSmr 552200422U, // MOVSSrm 8448230U, // MOVSSrr 8448230U, // MOVSSrr_REV 962208U, // MOVSW 438228U, // MOVSX16rm16 502447U, // MOVSX16rm8 551841748U, // MOVSX16rr16 551840431U, // MOVSX16rr8 432048U, // MOVSX32rm16 496511U, // MOVSX32rm8 496511U, // MOVSX32rm8_NOREX 551835568U, // MOVSX32rr16 551834495U, // MOVSX32rr8 551834495U, // MOVSX32rr8_NOREX 434339U, // MOVSX64rm16 551902452U, // MOVSX64rm32 498068U, // MOVSX64rm8 551837859U, // MOVSX64rr16 551836916U, // MOVSX64rr32 551836052U, // MOVSX64rr8 65047851U, // MOVUPDmr 658731U, // MOVUPDrm 551832875U, // MOVUPDrr 551832875U, // MOVUPDrr_REV 65054348U, // MOVUPSmr 665228U, // MOVUPSrm 551839372U, // MOVUPSrr 551839372U, // MOVUPSrr_REV 551837820U, // MOVZPQILo2PQIrr 438236U, // MOVZX16rm16 502513U, // MOVZX16rm8 551841756U, // MOVZX16rr16 551840497U, // MOVZX16rr8 432056U, // MOVZX32rm16 496542U, // MOVZX32rm8 496542U, // MOVZX32rm8_NOREX 551835576U, // MOVZX32rr16 551834526U, // MOVZX32rr8 551834526U, // MOVZX32rr8_NOREX 434380U, // MOVZX64rm16 498125U, // MOVZX64rm8 551837900U, // MOVZX64rr16 551836109U, // MOVZX64rr8 593881713U, // MPSADBWrmi 1088825969U, // MPSADBWrri 224415U, // MUL16m 27807U, // MUL16r 234863U, // MUL32m 21871U, // MUL32r 449799U, // MUL64m 23815U, // MUL64r 476291U, // MUL8m 17539U, // MUL8r 8522766U, // MULPDrm 8440846U, // MULPDrr 8529206U, // MULPSrm 8447286U, // MULPSrr 551702354U, // MULSDrm 551702354U, // MULSDrm_Int 8441682U, // MULSDrr 8441682U, // MULSDrr_Int 551725156U, // MULSSrm 551725156U, // MULSSrm_Int 8448100U, // MULSSrr 8448100U, // MULSSrr_Int 283203534U, // MULX32rm 811653070U, // MULX32rr 283222242U, // MULX64rm 811655394U, // MULX64rr 188878U, // MUL_F32m 202094U, // MUL_F64m 221653U, // MUL_FI16m 234869U, // MUL_FI32m 22695U, // MUL_FPrST0 22414U, // MUL_FST0r 0U, // MUL_Fp32 0U, // MUL_Fp32m 0U, // MUL_Fp64 0U, // MUL_Fp64m 0U, // MUL_Fp64m32 0U, // MUL_Fp80 0U, // MUL_Fp80m32 0U, // MUL_Fp80m64 0U, // MUL_FpI16m32 0U, // MUL_FpI16m64 0U, // MUL_FpI16m80 0U, // MUL_FpI32m32 0U, // MUL_FpI32m64 0U, // MUL_FpI32m80 28998U, // MUL_FrST0 16212U, // MWAITXrrr 15864U, // MWAITrr 224253U, // NEG16m 27645U, // NEG16r 234686U, // NEG32m 21694U, // NEG32r 449595U, // NEG64m 23611U, // NEG64r 476210U, // NEG8m 17458U, // NEG8r 15383U, // NOOP 224548U, // NOOP18_16m4 224548U, // NOOP18_16m5 224548U, // NOOP18_16m6 224548U, // NOOP18_16m7 27940U, // NOOP18_16r4 27940U, // NOOP18_16r5 27940U, // NOOP18_16r6 27940U, // NOOP18_16r7 234983U, // NOOP18_m4 234983U, // NOOP18_m5 234983U, // NOOP18_m6 234983U, // NOOP18_m7 21991U, // NOOP18_r4 21991U, // NOOP18_r5 21991U, // NOOP18_r6 21991U, // NOOP18_r7 283138254U, // NOOP19rr 234983U, // NOOPL 234983U, // NOOPL_19 234983U, // NOOPL_1d 234983U, // NOOPL_1e 21991U, // NOOPLr 449936U, // NOOPQ 23952U, // NOOPQr 224548U, // NOOPW 224548U, // NOOPW_19 224548U, // NOOPW_1c 224548U, // NOOPW_1d 224548U, // NOOPW_1e 27940U, // NOOPWr 225035U, // NOT16m 28427U, // NOT16r 235372U, // NOT32m 22380U, // NOT32r 450491U, // NOT64m 24507U, // NOT64r 476726U, // NOT8m 17974U, // NOT8r 2125192U, // OR16i16 4238728U, // OR16mi 4238728U, // OR16mi8 4238728U, // OR16mr 6352264U, // OR16ri 6352264U, // OR16ri8 6368648U, // OR16rm 6352264U, // OR16rr 8449416U, // OR16rr_REV 10507866U, // OR32i32 12621402U, // OR32mi 12621402U, // OR32mi8 12621402U, // OR32mr 6346330U, // OR32ri 6346330U, // OR32ri8 283203162U, // OR32rm 6346330U, // OR32rr 8443482U, // OR32rr_REV 16801361U, // OR64i32 18914897U, // OR64mi32 18914897U, // OR64mi8 18914897U, // OR64mr 6348369U, // OR64ri32 6348369U, // OR64ri8 283221585U, // OR64rm 6348369U, // OR64rr 8445521U, // OR64rr_REV 20989283U, // OR8i8 23102819U, // OR8mi 23102819U, // OR8mi8 23102819U, // OR8mr 6341987U, // OR8ri 6341987U, // OR8ri8 6407523U, // OR8rm 6341987U, // OR8rr 8439139U, // OR8rr_REV 8522954U, // ORPDrm 8441034U, // ORPDrr 8529411U, // ORPSrm 8447491U, // ORPSrr 718085U, // OUT16ir 16167U, // OUT16rr 718148U, // OUT32ir 16181U, // OUT32rr 717601U, // OUT8ir 16153U, // OUT8rr 72058343U, // OUTSB 72079119U, // OUTSL 72117892U, // OUTSW 263585U, // PABSBrm 551830945U, // PABSBrr 265926U, // PABSDrm 551833286U, // PABSDrr 273886U, // PABSWrm 551841246U, // PABSWrr 8645504U, // PACKSSDWrm 8448896U, // PACKSSDWrr 8636087U, // PACKSSWBrm 8439479U, // PACKSSWBrr 8645515U, // PACKUSDWrm 8448907U, // PACKUSDWrr 8636098U, // PACKUSWBrm 8439490U, // PACKUSWBrr 8635371U, // PADDBrm 8438763U, // PADDBrr 8636349U, // PADDDrm 8439741U, // PADDDrr 8641112U, // PADDQrm 8444504U, // PADDQrr 8635835U, // PADDSBrm 8439227U, // PADDSBrr 8646168U, // PADDSWrm 8449560U, // PADDSWrr 8635897U, // PADDUSBrm 8439289U, // PADDUSBrr 8646294U, // PADDUSWrm 8449686U, // PADDUSWrr 8645425U, // PADDWrm 8448817U, // PADDWrr 593879326U, // PALIGNRrmi 1088823582U, // PALIGNRrri 8640595U, // PANDNrm 8443987U, // PANDNrr 8636630U, // PANDrm 8440022U, // PANDrr 15087U, // PAUSE 8635459U, // PAVGBrm 8438851U, // PAVGBrr 551650818U, // PAVGUSBrm 8439298U, // PAVGUSBrr 8645646U, // PAVGWrm 8449038U, // PAVGWrr 8647060U, // PBLENDVBrm0 8450452U, // PBLENDVBrr0 593881965U, // PBLENDWrmi 1088826221U, // PBLENDWrri 593877770U, // PCLMULQDQrm 1088822026U, // PCLMULQDQrr 8635654U, // PCMPEQBrm 8439046U, // PCMPEQBrr 8637796U, // PCMPEQDrm 8441188U, // PCMPEQDrr 8642020U, // PCMPEQQrm 8445412U, // PCMPEQQrr 8645945U, // PCMPEQWrm 8449337U, // PCMPEQWrr 830771933U, // PCMPESTRIrm 283431645U, // PCMPESTRIrr 830773300U, // PCMPESTRMrm 283433012U, // PCMPESTRMrr 8635938U, // PCMPGTBrm 8439330U, // PCMPGTBrr 8638517U, // PCMPGTDrm 8441909U, // PCMPGTDrr 8642445U, // PCMPGTQrm 8445837U, // PCMPGTQrr 8646375U, // PCMPGTWrm 8449767U, // PCMPGTWrr 830771945U, // PCMPISTRIrm 283431657U, // PCMPISTRIrr 830773312U, // PCMPISTRMrm 283433024U, // PCMPISTRMrr 15116U, // PCONFIG 283203001U, // PDEP32rm 811652537U, // PDEP32rr 283221368U, // PDEP64rm 811654520U, // PDEP64rr 283203462U, // PEXT32rm 811652998U, // PEXT32rr 283222002U, // PEXT64rm 811655154U, // PEXT64rr 321160593U, // PEXTRBmr 283428241U, // PEXTRBrr 589598180U, // PEXTRDmr 283430372U, // PEXTRDrr 858037937U, // PEXTRQmr 283434673U, // PEXTRQrr 1126477262U, // PEXTRWmr 283438542U, // PEXTRWrr 283438542U, // PEXTRWrr_REV 551913540U, // PF2IDrm 551831620U, // PF2IDrr 551922754U, // PF2IWrm 551840834U, // PF2IWrr 551651050U, // PFACCrm 8439530U, // PFACCrr 551651237U, // PFADDrm 8439717U, // PFADDrr 551656420U, // PFCMPEQrm 8444900U, // PFCMPEQrr 551653821U, // PFCMPGErm 8442301U, // PFCMPGErr 551659814U, // PFCMPGTrm 8448294U, // PFCMPGTrr 551661540U, // PFMAXrm 8450020U, // PFMAXrr 551655522U, // PFMINrm 8444002U, // PFMINrr 551655309U, // PFMULrm 8443789U, // PFMULrr 551651057U, // PFNACCrm 8439537U, // PFNACCrr 551651065U, // PFPNACCrm 8439545U, // PFPNACCrr 551649327U, // PFRCPIT1rm 8437807U, // PFRCPIT1rr 551649416U, // PFRCPIT2rm 8437896U, // PFRCPIT2rr 551917709U, // PFRCPrm 551835789U, // PFRCPrr 551649337U, // PFRSQIT1rm 8437817U, // PFRSQIT1rr 551922025U, // PFRSQRTrm 551840105U, // PFRSQRTrr 551657742U, // PFSUBRrm 8446222U, // PFSUBRrr 551650943U, // PFSUBrm 8439423U, // PFSUBrr 8636333U, // PHADDDrm 8439725U, // PHADDDrr 8646158U, // PHADDSWrm 8449550U, // PHADDSWrr 8645409U, // PHADDWrm 8448801U, // PHADDWrr 274271U, // PHMINPOSUWrm 551841631U, // PHMINPOSUWrr 8636287U, // PHSUBDrm 8439679U, // PHSUBDrr 8646139U, // PHSUBSWrm 8449531U, // PHSUBSWrr 8645315U, // PHSUBWrm 8448707U, // PHSUBWrr 551913512U, // PI2FDrm 551831592U, // PI2FDrr 551922664U, // PI2FWrm 551840744U, // PI2FWrr 879084926U, // PINSRBrm 1088816510U, // PINSRBrr 881184209U, // PINSRDrm 1088818641U, // PINSRDrr 866508426U, // PINSRQrm 1088822922U, // PINSRQrr 600173993U, // PINSRWrm 1088826793U, // PINSRWrr 8646127U, // PMADDUBSWrm 8449519U, // PMADDUBSWrr 8638734U, // PMADDWDrm 8442126U, // PMADDWDrr 8635923U, // PMAXSBrm 8439315U, // PMAXSBrr 8638478U, // PMAXSDrm 8441870U, // PMAXSDrr 8646312U, // PMAXSWrm 8449704U, // PMAXSWrr 8636039U, // PMAXUBrm 8439431U, // PMAXUBrr 8638621U, // PMAXUDrm 8442013U, // PMAXUDrr 8646508U, // PMAXUWrm 8449900U, // PMAXUWrr 8635851U, // PMINSBrm 8439243U, // PMINSBrr 8638311U, // PMINSDrm 8441703U, // PMINSDrr 8646208U, // PMINSWrm 8449600U, // PMINSWrr 8636014U, // PMINUBrm 8439406U, // PMINUBrr 8638603U, // PMINUDrm 8441995U, // PMINUDrr 8646477U, // PMINUWrm 8449869U, // PMINUWrr 551830607U, // PMOVMSKBrr 551896976U, // PMOVSXBDrm 551831440U, // PMOVSXBDrr 432568U, // PMOVSXBQrm 551836088U, // PMOVSXBQrr 551922396U, // PMOVSXBWrm 551840476U, // PMOVSXBWrr 551918498U, // PMOVSXDQrm 551836578U, // PMOVSXDQrr 551915889U, // PMOVSXWDrm 551833969U, // PMOVSXWDrr 551903415U, // PMOVSXWQrm 551837879U, // PMOVSXWQrr 551896987U, // PMOVZXBDrm 551831451U, // PMOVZXBDrr 432579U, // PMOVZXBQrm 551836099U, // PMOVZXBQrr 551922407U, // PMOVZXBWrm 551840487U, // PMOVZXBWrr 551918509U, // PMOVZXDQrm 551836589U, // PMOVZXDQrr 551915900U, // PMOVZXWDrm 551833980U, // PMOVZXWDrr 551903426U, // PMOVZXWQrm 551837890U, // PMOVZXWQrr 8641207U, // PMULDQrm 8444599U, // PMULDQrr 8646233U, // PMULHRSWrm 8449625U, // PMULHRSWrr 551660920U, // PMULHRWrm 8449400U, // PMULHRWrr 8646458U, // PMULHUWrm 8449850U, // PMULHUWrr 8645683U, // PMULHWrm 8449075U, // PMULHWrr 8636538U, // PMULLDrm 8439930U, // PMULLDrr 8645752U, // PMULLWrm 8449144U, // PMULLWrr 8641432U, // PMULUDQrm 8444824U, // PMULUDQrr 27946U, // POP16r 224554U, // POP16rmm 27946U, // POP16rmr 21997U, // POP32r 234989U, // POP32rmm 21997U, // POP32rmr 23958U, // POP64r 449942U, // POP64rmm 23958U, // POP64rmr 15953U, // POPA16 15182U, // POPA32 438001U, // POPCNT16rm 551841521U, // POPCNT16rr 551901011U, // POPCNT32rm 551835475U, // POPCNT32rr 551919511U, // POPCNT64rm 551837591U, // POPCNT64rr 15608U, // POPDS16 15589U, // POPDS32 15646U, // POPES16 15627U, // POPES32 15966U, // POPF16 15195U, // POPF32 15456U, // POPF64 15703U, // POPFS16 15665U, // POPFS32 15684U, // POPFS64 15760U, // POPGS16 15722U, // POPGS32 15741U, // POPGS64 15835U, // POPSS16 15816U, // POPSS32 8642856U, // PORrm 8446248U, // PORrr 479822U, // PREFETCH 475990U, // PREFETCHNTA 475137U, // PREFETCHT0 475171U, // PREFETCHT1 475260U, // PREFETCHT2 486429U, // PREFETCHW 475203U, // PREFETCHWT1 8645224U, // PSADBWrm 8448616U, // PSADBWrr 8635434U, // PSHUFBrm 8438826U, // PSHUFBrr 830769200U, // PSHUFDmi 283428912U, // PSHUFDri 830778409U, // PSHUFHWmi 283438121U, // PSHUFHWri 830778454U, // PSHUFLWmi 283438166U, // PSHUFLWri 8635607U, // PSIGNBrm 8438999U, // PSIGNBrr 8636663U, // PSIGNDrm 8440055U, // PSIGNDrr 8645862U, // PSIGNWrm 8449254U, // PSIGNWrr 551869093U, // PSLLDQri 551864434U, // PSLLDri 8636530U, // PSLLDrm 8439922U, // PSLLDrr 551869646U, // PSLLQri 8641742U, // PSLLQrm 8445134U, // PSLLQrr 551873648U, // PSLLWri 8645744U, // PSLLWrm 8449136U, // PSLLWrr 551864162U, // PSRADri 8636258U, // PSRADrm 8439650U, // PSRADrr 551873094U, // PSRAWri 8645190U, // PSRAWrm 8448582U, // PSRAWrr 551869102U, // PSRLDQri 551864459U, // PSRLDri 8636555U, // PSRLDrm 8439947U, // PSRLDrr 551869671U, // PSRLQri 8641767U, // PSRLQrm 8445159U, // PSRLQrr 551873671U, // PSRLWri 8645767U, // PSRLWrm 8449159U, // PSRLWrr 8635322U, // PSUBBrm 8438714U, // PSUBBrr 8636296U, // PSUBDrm 8439688U, // PSUBDrr 8640936U, // PSUBQrm 8444328U, // PSUBQrr 8635826U, // PSUBSBrm 8439218U, // PSUBSBrr 8646149U, // PSUBSWrm 8449541U, // PSUBSWrr 8635887U, // PSUBUSBrm 8439279U, // PSUBUSBrr 8646284U, // PSUBUSWrm 8449676U, // PSUBUSWrr 8645324U, // PSUBWrm 8448716U, // PSUBWrr 551914155U, // PSWAPDrm 551832235U, // PSWAPDrr 665997U, // PTESTrm 551840141U, // PTESTrr 449571U, // PTWRITE64m 23587U, // PTWRITE64r 234662U, // PTWRITEm 21670U, // PTWRITEr 8645262U, // PUNPCKHBWrm 8448654U, // PUNPCKHBWrr 8641146U, // PUNPCKHDQrm 8444538U, // PUNPCKHDQrr 8641264U, // PUNPCKHQDQrm 8444656U, // PUNPCKHQDQrr 8638744U, // PUNPCKHWDrm 8442136U, // PUNPCKHWDrr 8645284U, // PUNPCKLBWrm 8448676U, // PUNPCKLBWrr 8641177U, // PUNPCKLDQrm 8444569U, // PUNPCKLDQrr 8641277U, // PUNPCKLQDQrm 8444669U, // PUNPCKLQDQrr 8638766U, // PUNPCKLWDrm 8442158U, // PUNPCKLWDrr 27707U, // PUSH16i8 27707U, // PUSH16r 224315U, // PUSH16rmm 27707U, // PUSH16rmr 21718U, // PUSH32i8 21718U, // PUSH32r 234710U, // PUSH32rmm 21718U, // PUSH32rmr 23647U, // PUSH64i32 23647U, // PUSH64i8 23647U, // PUSH64r 449631U, // PUSH64rmm 23647U, // PUSH64rmr 15946U, // PUSHA16 15175U, // PUSHA32 15569U, // PUSHCS16 15559U, // PUSHCS32 15598U, // PUSHDS16 15579U, // PUSHDS32 15636U, // PUSHES16 15617U, // PUSHES32 15959U, // PUSHF16 15188U, // PUSHF32 15449U, // PUSHF64 15693U, // PUSHFS16 15655U, // PUSHFS32 15674U, // PUSHFS64 15750U, // PUSHGS16 15712U, // PUSHGS32 15731U, // PUSHGS64 15825U, // PUSHSS16 15806U, // PUSHSS32 27707U, // PUSHi16 21718U, // PUSHi32 8642889U, // PXORrm 8446281U, // PXORrr 224335U, // RCL16m1 226450U, // RCL16mCL 1089399887U, // RCL16mi 29377U, // RCL16r1 29842U, // RCL16rCL 551873615U, // RCL16ri 234783U, // RCL32m1 242610U, // RCL32mCL 552523039U, // RCL32mi 29217U, // RCL32r1 29618U, // RCL32rCL 551867679U, // RCL32ri 449700U, // RCL64m1 455714U, // RCL64mCL 820960420U, // RCL64mi 29297U, // RCL64r1 29730U, // RCL64rCL 551869604U, // RCL64ri 476255U, // RCL8m1 488258U, // RCL8mCL 284083295U, // RCL8mi 29137U, // RCL8r1 29506U, // RCL8rCL 551863391U, // RCL8ri 664970U, // RCPPSm 551839114U, // RCPPSr 552200321U, // RCPSSm 551725185U, // RCPSSm_Int 551839873U, // RCPSSr 8448129U, // RCPSSr_Int 226025U, // RCR16m1 226494U, // RCR16mCL 1089400172U, // RCR16mi 29417U, // RCR16r1 29886U, // RCR16rCL 551873900U, // RCR16ri 242249U, // RCR32m1 242654U, // RCR32mCL 552523341U, // RCR32mi 29257U, // RCR32r1 29662U, // RCR32rCL 551867981U, // RCR32ri 455321U, // RCR64m1 455758U, // RCR64mCL 820960836U, // RCR64mi 29337U, // RCR64r1 29774U, // RCR64rCL 551870020U, // RCR64ri 487929U, // RCR8m1 488302U, // RCR8mCL 284083542U, // RCR8mi 29177U, // RCR8r1 29550U, // RCR8rCL 551863638U, // RCR8ri 21616U, // RDFSBASE 23533U, // RDFSBASE64 21638U, // RDGSBASE 23555U, // RDGSBASE64 15524U, // RDMSR 18516U, // RDPID32 18516U, // RDPID64 15912U, // RDPKRUr 14944U, // RDPMC 27491U, // RDRAND16r 21530U, // RDRAND32r 23257U, // RDRAND64r 27455U, // RDSEED16r 21501U, // RDSEED32r 23152U, // RDSEED64r 19693U, // RDSSPD 23973U, // RDSSPQ 14957U, // RDTSC 15352U, // RDTSCP 15056U, // REPNE_PREFIX 15359U, // REP_PREFIX 22343U, // RETIL 24454U, // RETIQ 28384U, // RETIW 15248U, // RETL 15463U, // RETQ 15978U, // RETW 14784U, // REX64_PREFIX 224384U, // ROL16m1 226472U, // ROL16mCL 1089399936U, // ROL16mi 29397U, // ROL16r1 29864U, // ROL16rCL 551873664U, // ROL16ri 234831U, // ROL32m1 242632U, // ROL32mCL 552523087U, // ROL32mi 29237U, // ROL32r1 29640U, // ROL32rCL 551867727U, // ROL32ri 449760U, // ROL64m1 455736U, // ROL64mCL 820960480U, // ROL64mi 29317U, // ROL64r1 29752U, // ROL64rCL 551869664U, // ROL64ri 476269U, // ROL8m1 488280U, // ROL8mCL 284083309U, // ROL8mi 29157U, // ROL8r1 29528U, // ROL8rCL 551863405U, // ROL8ri 224661U, // ROR16m1 226516U, // ROR16mCL 1089400213U, // ROR16mi 29437U, // ROR16r1 29908U, // ROR16rCL 551873941U, // ROR16ri 235097U, // ROR32m1 242676U, // ROR32mCL 552523353U, // ROR32mi 29277U, // ROR32r1 29684U, // ROR32rCL 551867993U, // ROR32ri 450151U, // ROR64m1 455780U, // ROR64mCL 820960871U, // ROR64mi 29357U, // ROR64r1 29796U, // ROR64rCL 551870055U, // ROR64ri 476528U, // ROR8m1 488324U, // ROR8mCL 284083568U, // ROR8mi 29197U, // ROR8r1 29572U, // ROR8rCL 551863664U, // ROR8ri 832870378U, // RORX32mi 283432938U, // RORX32ri 834969854U, // RORX64mi 283435262U, // RORX64ri 77892480U, // ROUNDPDm 283429760U, // ROUNDPDr 77898900U, // ROUNDPSm 283436180U, // ROUNDPSr 885296904U, // ROUNDSDm 851824392U, // ROUNDSDm_Int 283430664U, // ROUNDSDr 1088818952U, // ROUNDSDr_Int 887400474U, // ROUNDSSm 856025114U, // ROUNDSSm_Int 283437082U, // ROUNDSSr 1088825370U, // ROUNDSSr_Int 15313U, // RSM 665176U, // RSQRTPSm 551839320U, // RSQRTPSr 552200381U, // RSQRTSSm 551725245U, // RSQRTSSm_Int 551839933U, // RSQRTSSr 8448189U, // RSQRTSSr_Int 235753U, // RSTORSSP 15111U, // SAHF 224329U, // SAL16m1 226439U, // SAL16mCL 4238409U, // SAL16mi 29367U, // SAL16r1 29831U, // SAL16rCL 8449097U, // SAL16ri 234777U, // SAL32m1 242599U, // SAL32mCL 12621081U, // SAL32mi 29207U, // SAL32r1 29607U, // SAL32rCL 8443161U, // SAL32ri 449694U, // SAL64m1 455703U, // SAL64mCL 18914462U, // SAL64mi 29287U, // SAL64r1 29719U, // SAL64rCL 8445086U, // SAL64ri 476249U, // SAL8m1 488247U, // SAL8mCL 23102553U, // SAL8mi 29127U, // SAL8r1 29495U, // SAL8rCL 8438873U, // SAL8ri 14931U, // SALC 224614U, // SAR16m1 226483U, // SAR16mCL 1089400166U, // SAR16mi 29407U, // SAR16r1 29875U, // SAR16rCL 551873894U, // SAR16ri 235062U, // SAR32m1 242643U, // SAR32mCL 552523318U, // SAR32mi 29247U, // SAR32r1 29651U, // SAR32rCL 551867958U, // SAR32ri 450110U, // SAR64m1 455747U, // SAR64mCL 820960830U, // SAR64mi 29327U, // SAR64r1 29763U, // SAR64rCL 551870014U, // SAR64ri 476496U, // SAR8m1 488291U, // SAR8mCL 284083536U, // SAR8mi 29167U, // SAR8r1 29539U, // SAR8rCL 551863632U, // SAR8ri 832903132U, // SARX32rm 811653084U, // SARX32rr 835002608U, // SARX64rm 811655408U, // SARX64rr 15421U, // SAVEPREVSSP 2124373U, // SBB16i16 4237909U, // SBB16mi 4237909U, // SBB16mi8 4237909U, // SBB16mr 6351445U, // SBB16ri 6351445U, // SBB16ri8 6367829U, // SBB16rm 6351445U, // SBB16rr 8448597U, // SBB16rr_REV 10507129U, // SBB32i32 12620665U, // SBB32mi 12620665U, // SBB32mi8 12620665U, // SBB32mr 6345593U, // SBB32ri 6345593U, // SBB32ri8 283202425U, // SBB32rm 6345593U, // SBB32rr 8442745U, // SBB32rr_REV 16800132U, // SBB64i32 18913668U, // SBB64mi32 18913668U, // SBB64mi8 18913668U, // SBB64mr 6347140U, // SBB64ri32 6347140U, // SBB64ri8 283220356U, // SBB64rm 6347140U, // SBB64rr 8444292U, // SBB64rr_REV 20988851U, // SBB8i8 23102387U, // SBB8mi 23102387U, // SBB8mi8 23102387U, // SBB8mr 6341555U, // SBB8ri 6341555U, // SBB8ri8 6407091U, // SBB8rm 6341555U, // SBB8rr 8438707U, // SBB8rr_REV 21513625U, // SCASB 11048599U, // SCASL 17358521U, // SCASQ 2698710U, // SCASW 479627U, // SETAEm 20875U, // SETAEr 475984U, // SETAm 17232U, // SETAr 479649U, // SETBEm 20897U, // SETBEr 476699U, // SETBm 17947U, // SETBr 479753U, // SETEm 21001U, // SETEr 479686U, // SETGEm 20934U, // SETGEr 479816U, // SETGm 21064U, // SETGr 479702U, // SETLEm 20950U, // SETLEr 481101U, // SETLm 22349U, // SETLr 479722U, // SETNEm 20970U, // SETNEr 481401U, // SETNOm 22649U, // SETNOr 481479U, // SETNPm 22727U, // SETNPr 483833U, // SETNSm 25081U, // SETNSr 481408U, // SETOm 22656U, // SETOr 481523U, // SETPm 22771U, // SETPr 16219U, // SETSSBSY 485630U, // SETSm 26878U, // SETSr 15033U, // SFENCE 683708U, // SGDT16m 677674U, // SGDT32m 679785U, // SGDT64m 8634381U, // SHA1MSG1rm 8437773U, // SHA1MSG1rr 8634470U, // SHA1MSG2rm 8437862U, // SHA1MSG2rr 8639001U, // SHA1NEXTErm 8442393U, // SHA1NEXTErr 593871230U, // SHA1RNDS4rmi 1088815486U, // SHA1RNDS4rri 8634391U, // SHA256MSG1rm 8437783U, // SHA256MSG1rr 8634480U, // SHA256MSG2rm 8437872U, // SHA256MSG2rr 8647040U, // SHA256RNDS2rm 8450432U, // SHA256RNDS2rr 224353U, // SHL16m1 226461U, // SHL16mCL 1089399905U, // SHL16mi 29387U, // SHL16r1 29853U, // SHL16rCL 551873633U, // SHL16ri 234797U, // SHL32m1 242621U, // SHL32mCL 552523053U, // SHL32mi 29227U, // SHL32r1 29629U, // SHL32rCL 551867693U, // SHL32ri 449708U, // SHL64m1 455725U, // SHL64mCL 820960428U, // SHL64mi 29307U, // SHL64r1 29741U, // SHL64rCL 551869612U, // SHL64ri 476263U, // SHL8m1 488269U, // SHL8mCL 284083303U, // SHL8mi 29147U, // SHL8r1 29517U, // SHL8rCL 551863399U, // SHL8ri 4240495U, // SHLD16mrCL 1126476618U, // SHLD16mri8 8451183U, // SHLD16rrCL 1088826186U, // SHLD16rri8 12628879U, // SHLD32mrCL 589599756U, // SHLD32mri8 8450959U, // SHLD32rrCL 1088820236U, // SHLD32rri8 18920447U, // SHLD64mrCL 858036881U, // SHLD64mri8 8451071U, // SHLD64rrCL 1088821905U, // SHLD64rri8 832903111U, // SHLX32rm 811653063U, // SHLX32rr 835002587U, // SHLX64rm 811655387U, // SHLX64rr 224641U, // SHR16m1 226505U, // SHR16mCL 1089400193U, // SHR16mi 29427U, // SHR16r1 29897U, // SHR16rCL 551873921U, // SHR16ri 235091U, // SHR32m1 242665U, // SHR32mCL 552523347U, // SHR32mi 29267U, // SHR32r1 29673U, // SHR32rCL 551867987U, // SHR32ri 450122U, // SHR64m1 455769U, // SHR64mCL 820960842U, // SHR64mi 29347U, // SHR64r1 29785U, // SHR64rCL 551870026U, // SHR64ri 476508U, // SHR8m1 488313U, // SHR8mCL 284083548U, // SHR8mi 29187U, // SHR8r1 29561U, // SHR8rCL 551863644U, // SHR8ri 4240507U, // SHRD16mrCL 1126476664U, // SHRD16mri8 8451195U, // SHRD16rrCL 1088826232U, // SHRD16rri8 12628891U, // SHRD32mrCL 589599779U, // SHRD32mri8 8450971U, // SHRD32rrCL 1088820259U, // SHRD32rri8 18920459U, // SHRD64mrCL 858037040U, // SHRD64mri8 8451083U, // SHRD64rrCL 1088822064U, // SHRD64rri8 832903139U, // SHRX32rm 811653091U, // SHRX32rr 835002615U, // SHRX64rm 811655415U, // SHRX64rr 568708048U, // SHUFPDrmi 1088818128U, // SHUFPDrri 568714468U, // SHUFPSrmi 1088824548U, // SHUFPSrri 683722U, // SIDT16m 677688U, // SIDT32m 679799U, // SIDT64m 15330U, // SIN_F 0U, // SIN_Fp32 0U, // SIN_Fp64 0U, // SIN_Fp80 16054U, // SKINIT 224984U, // SLDT16m 28376U, // SLDT16r 22335U, // SLDT32r 24446U, // SLDT64r 17371U, // SLWPCB 17371U, // SLWPCB64 225218U, // SMSW16m 28610U, // SMSW16r 22441U, // SMSW32r 24732U, // SMSW64r 658713U, // SQRTPDm 551832857U, // SQRTPDr 665177U, // SQRTPSm 551839321U, // SQRTPSr 552177629U, // SQRTSDm 551702493U, // SQRTSDm_Int 551833565U, // SQRTSDr 8441821U, // SQRTSDr_Int 552200382U, // SQRTSSm 551725246U, // SQRTSSm_Int 551839934U, // SQRTSSr 8448190U, // SQRTSSr_Int 15889U, // SQRT_F 0U, // SQRT_Fp32 0U, // SQRT_Fp64 0U, // SQRT_Fp80 14909U, // STAC 14963U, // STC 14987U, // STD 15138U, // STGI 15153U, // STI 237920U, // STMXCSR 553749U, // STOSB 570679U, // STOSL 587128U, // STOSQ 603385U, // STOSW 28103U, // STR16r 22136U, // STR32r 24226U, // STR64r 224711U, // STRm 190724U, // ST_F32m 202617U, // ST_F64m 190067U, // ST_FP32m 202233U, // ST_FP64m 698714U, // ST_FP80m 22777U, // ST_FPrr 0U, // ST_Fp32m 0U, // ST_Fp64m 0U, // ST_Fp64m32 0U, // ST_Fp80m32 0U, // ST_Fp80m64 0U, // ST_FpP32m 0U, // ST_FpP64m 0U, // ST_FpP64m32 0U, // ST_FpP80m 0U, // ST_FpP80m32 0U, // ST_FpP80m64 27028U, // ST_Frr 2124485U, // SUB16i16 4238021U, // SUB16mi 4238021U, // SUB16mi8 4238021U, // SUB16mr 6351557U, // SUB16ri 6351557U, // SUB16ri8 6367941U, // SUB16rm 6351557U, // SUB16rr 8448709U, // SUB16rr_REV 10507144U, // SUB32i32 12620680U, // SUB32mi 12620680U, // SUB32mi8 12620680U, // SUB32mr 6345608U, // SUB32ri 6345608U, // SUB32ri8 283202440U, // SUB32rm 6345608U, // SUB32rr 8442760U, // SUB32rr_REV 16800169U, // SUB64i32 18913705U, // SUB64mi32 18913705U, // SUB64mi8 18913705U, // SUB64mr 6347177U, // SUB64ri32 6347177U, // SUB64ri8 283220393U, // SUB64rm 6347177U, // SUB64rr 8444329U, // SUB64rr_REV 20988859U, // SUB8i8 23102395U, // SUB8mi 23102395U, // SUB8mi8 23102395U, // SUB8mr 6341563U, // SUB8ri 6341563U, // SUB8ri8 6407099U, // SUB8rm 6341563U, // SUB8rr 8438715U, // SUB8rr_REV 8522425U, // SUBPDrm 8440505U, // SUBPDrr 8528822U, // SUBPSrm 8446902U, // SUBPSrr 190148U, // SUBR_F32m 202300U, // SUBR_F64m 222924U, // SUBR_FI16m 235076U, // SUBR_FI32m 22662U, // SUBR_FPrST0 24847U, // SUBR_FST0r 0U, // SUBR_Fp32m 0U, // SUBR_Fp64m 0U, // SUBR_Fp64m32 0U, // SUBR_Fp80m32 0U, // SUBR_Fp80m64 0U, // SUBR_FpI16m32 0U, // SUBR_FpI16m64 0U, // SUBR_FpI16m80 0U, // SUBR_FpI32m32 0U, // SUBR_FpI32m64 0U, // SUBR_FpI32m80 28953U, // SUBR_FrST0 551702224U, // SUBSDrm 551702224U, // SUBSDrm_Int 8441552U, // SUBSDrr 8441552U, // SUBSDrr_Int 551725003U, // SUBSSrm 551725003U, // SUBSSrm_Int 8447947U, // SUBSSrr 8447947U, // SUBSSrr_Int 188784U, // SUB_F32m 201607U, // SUB_F64m 221559U, // SUB_FI16m 234382U, // SUB_FI32m 22745U, // SUB_FPrST0 18048U, // SUB_FST0r 0U, // SUB_Fp32 0U, // SUB_Fp32m 0U, // SUB_Fp64 0U, // SUB_Fp64m 0U, // SUB_Fp64m32 0U, // SUB_Fp80 0U, // SUB_Fp80m32 0U, // SUB_Fp80m64 0U, // SUB_FpI16m32 0U, // SUB_FpI16m64 0U, // SUB_FpI16m80 0U, // SUB_FpI32m32 0U, // SUB_FpI32m64 0U, // SUB_FpI32m80 29012U, // SUB_FrST0 15769U, // SWAPGS 15230U, // SYSCALL 15507U, // SYSENTER 15267U, // SYSEXIT 15482U, // SYSEXIT64 15259U, // SYSRET 15474U, // SYSRET64 551900105U, // T1MSKC32rm 551834569U, // T1MSKC32rr 551918065U, // T1MSKC64rm 551836145U, // T1MSKC64rr 2125608U, // TEST16i16 4239144U, // TEST16mi 4239144U, // TEST16mi_alt 4239144U, // TEST16mr 551841576U, // TEST16ri 551841576U, // TEST16ri_alt 551841576U, // TEST16rr 10508146U, // TEST32i32 12621682U, // TEST32mi 12621682U, // TEST32mi_alt 12621682U, // TEST32mr 551835506U, // TEST32ri 551835506U, // TEST32ri_alt 551835506U, // TEST32rr 16801761U, // TEST64i32 18915297U, // TEST64mi32 18915297U, // TEST64mi32_alt 18915297U, // TEST64mr 551837665U, // TEST64ri32 551837665U, // TEST64ri32_alt 551837665U, // TEST64rr 20989523U, // TEST8i8 23103059U, // TEST8mi 23103059U, // TEST8mi_alt 23103059U, // TEST8mr 551831123U, // TEST8ri 551831123U, // TEST8ri_alt 551831123U, // TEST8rr 20993U, // TPAUSE 15901U, // TST_F 0U, // TST_Fp32 0U, // TST_Fp64 0U, // TST_Fp80 438018U, // TZCNT16rm 551841538U, // TZCNT16rr 551901028U, // TZCNT32rm 551835492U, // TZCNT32rr 551919530U, // TZCNT64rm 551837610U, // TZCNT64rr 551900433U, // TZMSK32rm 551834897U, // TZMSK32rr 551918742U, // TZMSK64rm 551836822U, // TZMSK64rr 552177471U, // UCOMISDrm 552177471U, // UCOMISDrm_Int 551833407U, // UCOMISDrr 551833407U, // UCOMISDrr_Int 552200273U, // UCOMISSrm 552200273U, // UCOMISSrm_Int 551839825U, // UCOMISSrr 551839825U, // UCOMISSrr_Int 21194U, // UCOM_FIPr 21136U, // UCOM_FIr 15413U, // UCOM_FPPr 22714U, // UCOM_FPr 0U, // UCOM_FpIr32 0U, // UCOM_FpIr64 0U, // UCOM_FpIr80 0U, // UCOM_Fpr32 0U, // UCOM_Fpr64 0U, // UCOM_Fpr80 22564U, // UCOM_Fr 14700U, // UD0 14715U, // UD1 14753U, // UD2 24877U, // UMONITOR16 24877U, // UMONITOR32 24877U, // UMONITOR64 26927U, // UMWAIT 8522713U, // UNPCKHPDrm 8440793U, // UNPCKHPDrr 8529133U, // UNPCKHPSrm 8447213U, // UNPCKHPSrr 8522755U, // UNPCKLPDrm 8440835U, // UNPCKLPDrr 8529195U, // UNPCKLPSrm 8447275U, // UNPCKLPSrr 890184770U, // V4FMADDPSrm 86991938U, // V4FMADDPSrmk 89089090U, // V4FMADDPSrmkz 890185701U, // V4FMADDSSrm 86992869U, // V4FMADDSSrmk 89090021U, // V4FMADDSSrmkz 890184791U, // V4FNMADDPSrm 86991959U, // V4FNMADDPSrmk 89089111U, // V4FNMADDPSrmkz 890185722U, // V4FNMADDSSrm 86992890U, // V4FNMADDSSrmk 89090042U, // V4FNMADDSSrmkz 812616538U, // VADDPDYrm 811649882U, // VADDPDYrr 811731802U, // VADDPDZ128rm 358763354U, // VADDPDZ128rmb 1433389914U, // VADDPDZ128rmbk 1164970842U, // VADDPDZ128rmbkz 86985562U, // VADDPDZ128rmk 890178394U, // VADDPDZ128rmkz 811649882U, // VADDPDZ128rr 87051098U, // VADDPDZ128rrk 890276698U, // VADDPDZ128rrkz 812616538U, // VADDPDZ256rm 360860506U, // VADDPDZ256rmb 1435487066U, // VADDPDZ256rmbk 1167067994U, // VADDPDZ256rmbkz 87083866U, // VADDPDZ256rmk 890309466U, // VADDPDZ256rmkz 811649882U, // VADDPDZ256rr 87051098U, // VADDPDZ256rrk 890276698U, // VADDPDZ256rrkz 812731226U, // VADDPDZrm 362957658U, // VADDPDZrmb 1437584218U, // VADDPDZrmbk 1169165146U, // VADDPDZrmbkz 87133018U, // VADDPDZrmk 890358618U, // VADDPDZrmkz 811649882U, // VADDPDZrr 812780378U, // VADDPDZrrb 87182170U, // VADDPDZrrbk 890407770U, // VADDPDZrrbkz 87051098U, // VADDPDZrrk 890276698U, // VADDPDZrrkz 811731802U, // VADDPDrm 811649882U, // VADDPDrr 812622958U, // VADDPSYrm 811656302U, // VADDPSYrr 811738222U, // VADDPSZ128rm 360883310U, // VADDPSZ128rmb 1435690094U, // VADDPSZ128rmbk 1167271022U, // VADDPSZ128rmbkz 86991982U, // VADDPSZ128rmk 890184814U, // VADDPSZ128rmkz 811656302U, // VADDPSZ128rr 87057518U, // VADDPSZ128rrk 890283118U, // VADDPSZ128rrkz 812622958U, // VADDPSZ256rm 362980462U, // VADDPSZ256rmb 1437787246U, // VADDPSZ256rmbk 1169368174U, // VADDPSZ256rmbkz 87090286U, // VADDPSZ256rmk 890315886U, // VADDPSZ256rmkz 811656302U, // VADDPSZ256rr 87057518U, // VADDPSZ256rrk 890283118U, // VADDPSZ256rrkz 812737646U, // VADDPSZrm 365077614U, // VADDPSZrmb 1439884398U, // VADDPSZrmbk 1171465326U, // VADDPSZrmbkz 87139438U, // VADDPSZrmk 890365038U, // VADDPSZrmkz 811656302U, // VADDPSZrr 812786798U, // VADDPSZrrb 87188590U, // VADDPSZrrbk 890414190U, // VADDPSZrrbkz 87057518U, // VADDPSZrrk 890283118U, // VADDPSZrrkz 811738222U, // VADDPSrm 811656302U, // VADDPSrr 283266815U, // VADDSDZrm 283266815U, // VADDSDZrm_Int 1357893375U, // VADDSDZrm_Intk 1089474303U, // VADDSDZrm_Intkz 811650815U, // VADDSDZrr 811650815U, // VADDSDZrr_Int 87052031U, // VADDSDZrr_Intk 890277631U, // VADDSDZrr_Intkz 812781311U, // VADDSDZrrb_Int 87183103U, // VADDSDZrrb_Intk 890408703U, // VADDSDZrrb_Intkz 283266815U, // VADDSDrm 283266815U, // VADDSDrm_Int 811650815U, // VADDSDrr 811650815U, // VADDSDrr_Int 283289617U, // VADDSSZrm 283289617U, // VADDSSZrm_Int 1358096401U, // VADDSSZrm_Intk 1089677329U, // VADDSSZrm_Intkz 811657233U, // VADDSSZrr 811657233U, // VADDSSZrr_Int 87058449U, // VADDSSZrr_Intk 890284049U, // VADDSSZrr_Intkz 812787729U, // VADDSSZrrb_Int 87189521U, // VADDSSZrrb_Intk 890415121U, // VADDSSZrrb_Intkz 283289617U, // VADDSSrm 283289617U, // VADDSSrm_Int 811657233U, // VADDSSrr 811657233U, // VADDSSrr_Int 812616384U, // VADDSUBPDYrm 811649728U, // VADDSUBPDYrr 811731648U, // VADDSUBPDrm 811649728U, // VADDSUBPDrr 812622781U, // VADDSUBPSYrm 811656125U, // VADDSUBPSYrr 811738045U, // VADDSUBPSrm 811656125U, // VADDSUBPSrr 812870002U, // VAESDECLASTYrm 811657586U, // VAESDECLASTYrr 811854194U, // VAESDECLASTZ128rm 811657586U, // VAESDECLASTZ128rr 812870002U, // VAESDECLASTZ256rm 811657586U, // VAESDECLASTZ256rr 812886386U, // VAESDECLASTZrm 811657586U, // VAESDECLASTZrr 811854194U, // VAESDECLASTrm 811657586U, // VAESDECLASTrr 812861186U, // VAESDECYrm 811648770U, // VAESDECYrr 811845378U, // VAESDECZ128rm 811648770U, // VAESDECZ128rr 812861186U, // VAESDECZ256rm 811648770U, // VAESDECZ256rr 812877570U, // VAESDECZrm 811648770U, // VAESDECZrr 811845378U, // VAESDECrm 811648770U, // VAESDECrr 812870015U, // VAESENCLASTYrm 811657599U, // VAESENCLASTYrr 811854207U, // VAESENCLASTZ128rm 811657599U, // VAESENCLASTZ128rr 812870015U, // VAESENCLASTZ256rm 811657599U, // VAESENCLASTZ256rr 812886399U, // VAESENCLASTZrm 811657599U, // VAESENCLASTZrr 811854207U, // VAESENCLASTrm 811657599U, // VAESENCLASTrr 812861212U, // VAESENCYrm 811648796U, // VAESENCYrr 811845404U, // VAESENCZ128rm 811648796U, // VAESENCZ128rr 812861212U, // VAESENCZ256rm 811648796U, // VAESENCZ256rr 812877596U, // VAESENCZrm 811648796U, // VAESENCZrr 811845404U, // VAESENCrm 811648796U, // VAESENCrr 263955U, // VAESIMCrm 551831315U, // VAESIMCrr 830777753U, // VAESKEYGENASSIST128rm 283437465U, // VAESKEYGENASSIST128rr 1686489325U, // VALIGNDZ128rmbi 1710475501U, // VALIGNDZ128rmbik 1712589037U, // VALIGNDZ128rmbikz 325437677U, // VALIGNDZ128rmi 1983105261U, // VALIGNDZ128rmik 1179912429U, // VALIGNDZ128rmikz 1088817389U, // VALIGNDZ128rri 2163132653U, // VALIGNDZ128rrik 1357580525U, // VALIGNDZ128rrikz 2491795693U, // VALIGNDZ256rmbi 2515781869U, // VALIGNDZ256rmbik 2517895405U, // VALIGNDZ256rmbikz 375769325U, // VALIGNDZ256rmi 1989396717U, // VALIGNDZ256rmik 1186203885U, // VALIGNDZ256rmikz 1088817389U, // VALIGNDZ256rri 2163132653U, // VALIGNDZ256rrik 1357580525U, // VALIGNDZ256rrikz 2760231149U, // VALIGNDZrmbi 2784217325U, // VALIGNDZrmbik 2786330861U, // VALIGNDZrmbikz 382060781U, // VALIGNDZrmi 1995688173U, // VALIGNDZrmik 1192495341U, // VALIGNDZrmikz 1088817389U, // VALIGNDZrri 2163132653U, // VALIGNDZrrik 1357580525U, // VALIGNDZrrikz 3013991766U, // VALIGNQZ128rmbi 3073629526U, // VALIGNQZ128rmbik 3075743062U, // VALIGNQZ128rmbikz 325442902U, // VALIGNQZ128rmi 1983110486U, // VALIGNQZ128rmik 1179917654U, // VALIGNQZ128rmikz 1088822614U, // VALIGNQZ128rri 2163137878U, // VALIGNQZ128rrik 1357585750U, // VALIGNQZ128rrikz 1671814486U, // VALIGNQZ256rmbi 1731452246U, // VALIGNQZ256rmbik 1733565782U, // VALIGNQZ256rmbikz 375774550U, // VALIGNQZ256rmi 1989401942U, // VALIGNQZ256rmik 1186209110U, // VALIGNQZ256rmikz 1088822614U, // VALIGNQZ256rri 2163137878U, // VALIGNQZ256rrik 1357585750U, // VALIGNQZ256rrikz 2477120854U, // VALIGNQZrmbi 2536758614U, // VALIGNQZrmbik 2538872150U, // VALIGNQZrmbikz 382066006U, // VALIGNQZrmi 1995693398U, // VALIGNQZrmik 1192500566U, // VALIGNQZrmikz 1088822614U, // VALIGNQZrri 2163137878U, // VALIGNQZrrik 1357585750U, // VALIGNQZrrikz 812616775U, // VANDNPDYrm 811650119U, // VANDNPDYrr 811732039U, // VANDNPDZ128rm 358763591U, // VANDNPDZ128rmb 1433390151U, // VANDNPDZ128rmbk 1164971079U, // VANDNPDZ128rmbkz 86985799U, // VANDNPDZ128rmk 890178631U, // VANDNPDZ128rmkz 811650119U, // VANDNPDZ128rr 87051335U, // VANDNPDZ128rrk 890276935U, // VANDNPDZ128rrkz 812616775U, // VANDNPDZ256rm 360860743U, // VANDNPDZ256rmb 1435487303U, // VANDNPDZ256rmbk 1167068231U, // VANDNPDZ256rmbkz 87084103U, // VANDNPDZ256rmk 890309703U, // VANDNPDZ256rmkz 811650119U, // VANDNPDZ256rr 87051335U, // VANDNPDZ256rrk 890276935U, // VANDNPDZ256rrkz 812731463U, // VANDNPDZrm 362957895U, // VANDNPDZrmb 1437584455U, // VANDNPDZrmbk 1169165383U, // VANDNPDZrmbkz 87133255U, // VANDNPDZrmk 890358855U, // VANDNPDZrmkz 811650119U, // VANDNPDZrr 87051335U, // VANDNPDZrrk 890276935U, // VANDNPDZrrkz 811732039U, // VANDNPDrm 811650119U, // VANDNPDrr 812623224U, // VANDNPSYrm 811656568U, // VANDNPSYrr 811738488U, // VANDNPSZ128rm 360883576U, // VANDNPSZ128rmb 1435690360U, // VANDNPSZ128rmbk 1167271288U, // VANDNPSZ128rmbkz 86992248U, // VANDNPSZ128rmk 890185080U, // VANDNPSZ128rmkz 811656568U, // VANDNPSZ128rr 87057784U, // VANDNPSZ128rrk 890283384U, // VANDNPSZ128rrkz 812623224U, // VANDNPSZ256rm 362980728U, // VANDNPSZ256rmb 1437787512U, // VANDNPSZ256rmbk 1169368440U, // VANDNPSZ256rmbkz 87090552U, // VANDNPSZ256rmk 890316152U, // VANDNPSZ256rmkz 811656568U, // VANDNPSZ256rr 87057784U, // VANDNPSZ256rrk 890283384U, // VANDNPSZ256rrkz 812737912U, // VANDNPSZrm 365077880U, // VANDNPSZrmb 1439884664U, // VANDNPSZrmbk 1171465592U, // VANDNPSZrmbkz 87139704U, // VANDNPSZrmk 890365304U, // VANDNPSZrmkz 811656568U, // VANDNPSZrr 87057784U, // VANDNPSZrrk 890283384U, // VANDNPSZrrkz 811738488U, // VANDNPSrm 811656568U, // VANDNPSrr 812616557U, // VANDPDYrm 811649901U, // VANDPDYrr 811731821U, // VANDPDZ128rm 358763373U, // VANDPDZ128rmb 1433389933U, // VANDPDZ128rmbk 1164970861U, // VANDPDZ128rmbkz 86985581U, // VANDPDZ128rmk 890178413U, // VANDPDZ128rmkz 811649901U, // VANDPDZ128rr 87051117U, // VANDPDZ128rrk 890276717U, // VANDPDZ128rrkz 812616557U, // VANDPDZ256rm 360860525U, // VANDPDZ256rmb 1435487085U, // VANDPDZ256rmbk 1167068013U, // VANDPDZ256rmbkz 87083885U, // VANDPDZ256rmk 890309485U, // VANDPDZ256rmkz 811649901U, // VANDPDZ256rr 87051117U, // VANDPDZ256rrk 890276717U, // VANDPDZ256rrkz 812731245U, // VANDPDZrm 362957677U, // VANDPDZrmb 1437584237U, // VANDPDZrmbk 1169165165U, // VANDPDZrmbkz 87133037U, // VANDPDZrmk 890358637U, // VANDPDZrmkz 811649901U, // VANDPDZrr 87051117U, // VANDPDZrrk 890276717U, // VANDPDZrrkz 811731821U, // VANDPDrm 811649901U, // VANDPDrr 812622977U, // VANDPSYrm 811656321U, // VANDPSYrr 811738241U, // VANDPSZ128rm 360883329U, // VANDPSZ128rmb 1435690113U, // VANDPSZ128rmbk 1167271041U, // VANDPSZ128rmbkz 86992001U, // VANDPSZ128rmk 890184833U, // VANDPSZ128rmkz 811656321U, // VANDPSZ128rr 87057537U, // VANDPSZ128rrk 890283137U, // VANDPSZ128rrkz 812622977U, // VANDPSZ256rm 362980481U, // VANDPSZ256rmb 1437787265U, // VANDPSZ256rmbk 1169368193U, // VANDPSZ256rmbkz 87090305U, // VANDPSZ256rmk 890315905U, // VANDPSZ256rmkz 811656321U, // VANDPSZ256rr 87057537U, // VANDPSZ256rrk 890283137U, // VANDPSZ256rrkz 812737665U, // VANDPSZrm 365077633U, // VANDPSZrmb 1439884417U, // VANDPSZrmbk 1171465345U, // VANDPSZrmbkz 87139457U, // VANDPSZrmk 890365057U, // VANDPSZrmkz 811656321U, // VANDPSZrr 87057537U, // VANDPSZrrk 890283137U, // VANDPSZrrkz 811738241U, // VANDPSrm 811656321U, // VANDPSrr 811732006U, // VBLENDMPDZ128rm 358763558U, // VBLENDMPDZ128rmb 1164971046U, // VBLENDMPDZ128rmbk 1164971046U, // VBLENDMPDZ128rmbkz 890178598U, // VBLENDMPDZ128rmk 890178598U, // VBLENDMPDZ128rmkz 811650086U, // VBLENDMPDZ128rr 890276902U, // VBLENDMPDZ128rrk 890276902U, // VBLENDMPDZ128rrkz 812616742U, // VBLENDMPDZ256rm 360860710U, // VBLENDMPDZ256rmb 1167068198U, // VBLENDMPDZ256rmbk 1167068198U, // VBLENDMPDZ256rmbkz 890309670U, // VBLENDMPDZ256rmk 890309670U, // VBLENDMPDZ256rmkz 811650086U, // VBLENDMPDZ256rr 890276902U, // VBLENDMPDZ256rrk 890276902U, // VBLENDMPDZ256rrkz 812731430U, // VBLENDMPDZrm 362957862U, // VBLENDMPDZrmb 1169165350U, // VBLENDMPDZrmbk 1169165350U, // VBLENDMPDZrmbkz 890358822U, // VBLENDMPDZrmk 890358822U, // VBLENDMPDZrmkz 811650086U, // VBLENDMPDZrr 890276902U, // VBLENDMPDZrrk 890276902U, // VBLENDMPDZrrkz 811738438U, // VBLENDMPSZ128rm 360883526U, // VBLENDMPSZ128rmb 1167271238U, // VBLENDMPSZ128rmbk 1167271238U, // VBLENDMPSZ128rmbkz 890185030U, // VBLENDMPSZ128rmk 890185030U, // VBLENDMPSZ128rmkz 811656518U, // VBLENDMPSZ128rr 890283334U, // VBLENDMPSZ128rrk 890283334U, // VBLENDMPSZ128rrkz 812623174U, // VBLENDMPSZ256rm 362980678U, // VBLENDMPSZ256rmb 1169368390U, // VBLENDMPSZ256rmbk 1169368390U, // VBLENDMPSZ256rmbkz 890316102U, // VBLENDMPSZ256rmk 890316102U, // VBLENDMPSZ256rmkz 811656518U, // VBLENDMPSZ256rr 890283334U, // VBLENDMPSZ256rrk 890283334U, // VBLENDMPSZ256rrkz 812737862U, // VBLENDMPSZrm 365077830U, // VBLENDMPSZrmb 1171465542U, // VBLENDMPSZrmbk 1171465542U, // VBLENDMPSZrmbkz 890365254U, // VBLENDMPSZrmk 890365254U, // VBLENDMPSZrmkz 811656518U, // VBLENDMPSZrr 890283334U, // VBLENDMPSZrrk 890283334U, // VBLENDMPSZrrkz 392547189U, // VBLENDPDYrmi 1088818037U, // VBLENDPDYrri 300272501U, // VBLENDPDrmi 1088818037U, // VBLENDPDrri 392553609U, // VBLENDPSYrmi 1088824457U, // VBLENDPSYrri 300278921U, // VBLENDPSrmi 1088824457U, // VBLENDPSrri 393497907U, // VBLENDVPDYrm 890277171U, // VBLENDVPDYrr 301223219U, // VBLENDVPDrm 890277171U, // VBLENDVPDrr 393504404U, // VBLENDVPSYrm 890283668U, // VBLENDVPSYrr 301229716U, // VBLENDVPSrm 890283668U, // VBLENDVPSrr 656011U, // VBROADCASTF128 552173714U, // VBROADCASTF32X2Z256m 552599698U, // VBROADCASTF32X2Z256mk 551698578U, // VBROADCASTF32X2Z256mkz 551829650U, // VBROADCASTF32X2Z256r 3230695570U, // VBROADCASTF32X2Z256rk 3229663378U, // VBROADCASTF32X2Z256rkz 552173714U, // VBROADCASTF32X2Zm 552599698U, // VBROADCASTF32X2Zmk 551698578U, // VBROADCASTF32X2Zmkz 551829650U, // VBROADCASTF32X2Zr 3230695570U, // VBROADCASTF32X2Zrk 3229663378U, // VBROADCASTF32X2Zrkz 655794U, // VBROADCASTF32X4Z256rm 3230597554U, // VBROADCASTF32X4Z256rmk 3229745586U, // VBROADCASTF32X4Z256rmkz 655794U, // VBROADCASTF32X4rm 3230597554U, // VBROADCASTF32X4rmk 3229745586U, // VBROADCASTF32X4rmkz 1344249U, // VBROADCASTF32X8rm 3230728953U, // VBROADCASTF32X8rmk 3230630649U, // VBROADCASTF32X8rmkz 655581U, // VBROADCASTF64X2Z128rm 3230597341U, // VBROADCASTF64X2Z128rmk 3229745373U, // VBROADCASTF64X2Z128rmkz 655581U, // VBROADCASTF64X2rm 3230597341U, // VBROADCASTF64X2rmk 3229745373U, // VBROADCASTF64X2rmkz 1344026U, // VBROADCASTF64X4rm 3230728730U, // VBROADCASTF64X4rmk 3230630426U, // VBROADCASTF64X4rmkz 262850U, // VBROADCASTI128 551911587U, // VBROADCASTI32X2Z128m 552911011U, // VBROADCASTI32X2Z128mk 551649443U, // VBROADCASTI32X2Z128mkz 551829667U, // VBROADCASTI32X2Z128r 3230695587U, // VBROADCASTI32X2Z128rk 3229663395U, // VBROADCASTI32X2Z128rkz 551911587U, // VBROADCASTI32X2Z256m 552911011U, // VBROADCASTI32X2Z256mk 551649443U, // VBROADCASTI32X2Z256mkz 551829667U, // VBROADCASTI32X2Z256r 3230695587U, // VBROADCASTI32X2Z256rk 3229663395U, // VBROADCASTI32X2Z256rkz 551911587U, // VBROADCASTI32X2Zm 552911011U, // VBROADCASTI32X2Zmk 551649443U, // VBROADCASTI32X2Zmkz 551829667U, // VBROADCASTI32X2Zr 3230695587U, // VBROADCASTI32X2Zrk 3229663395U, // VBROADCASTI32X2Zrkz 262636U, // VBROADCASTI32X4Z256rm 3230990828U, // VBROADCASTI32X4Z256rmk 3229860332U, // VBROADCASTI32X4Z256rmkz 262636U, // VBROADCASTI32X4rm 3230990828U, // VBROADCASTI32X4rmk 3229860332U, // VBROADCASTI32X4rmkz 552944423U, // VBROADCASTI32X8rm 3231023911U, // VBROADCASTI32X8rmk 3230876455U, // VBROADCASTI32X8rmkz 262423U, // VBROADCASTI64X2Z128rm 3230990615U, // VBROADCASTI64X2Z128rmk 3229860119U, // VBROADCASTI64X2Z128rmkz 262423U, // VBROADCASTI64X2rm 3230990615U, // VBROADCASTI64X2rmk 3229860119U, // VBROADCASTI64X2rmkz 552944200U, // VBROADCASTI64X4rm 3231023688U, // VBROADCASTI64X4rmk 3230876232U, // VBROADCASTI64X4rmkz 552177637U, // VBROADCASTSDYrm 551833573U, // VBROADCASTSDYrr 552177637U, // VBROADCASTSDZ256m 552603621U, // VBROADCASTSDZ256mk 551702501U, // VBROADCASTSDZ256mkz 551833573U, // VBROADCASTSDZ256r 3230699493U, // VBROADCASTSDZ256rk 3229667301U, // VBROADCASTSDZ256rkz 552177637U, // VBROADCASTSDZm 552603621U, // VBROADCASTSDZmk 551702501U, // VBROADCASTSDZmkz 551833573U, // VBROADCASTSDZr 3230699493U, // VBROADCASTSDZrk 3229667301U, // VBROADCASTSDZrkz 552200399U, // VBROADCASTSSYrm 551839951U, // VBROADCASTSSYrr 552200399U, // VBROADCASTSSZ128m 552806607U, // VBROADCASTSSZ128mk 551725263U, // VBROADCASTSSZ128mkz 551839951U, // VBROADCASTSSZ128r 3230705871U, // VBROADCASTSSZ128rk 3229673679U, // VBROADCASTSSZ128rkz 552200399U, // VBROADCASTSSZ256m 552806607U, // VBROADCASTSSZ256mk 551725263U, // VBROADCASTSSZ256mkz 551839951U, // VBROADCASTSSZ256r 3230705871U, // VBROADCASTSSZ256rk 3229673679U, // VBROADCASTSSZ256rkz 552200399U, // VBROADCASTSSZm 552806607U, // VBROADCASTSSZmk 551725263U, // VBROADCASTSSZmkz 551839951U, // VBROADCASTSSZr 3230705871U, // VBROADCASTSSZrk 3229673679U, // VBROADCASTSSZrkz 552200399U, // VBROADCASTSSrm 551839951U, // VBROADCASTSSrr 3530030089U, // VCMPPDYrmi 392547423U, // VCMPPDYrmi_alt 1114127369U, // VCMPPDYrri 1088818271U, // VCMPPDYrri_alt 2456288265U, // VCMPPDZ128rmbi 2999307359U, // VCMPPDZ128rmbi_alt 3079933023U, // VCMPPDZ128rmbi_altk 3799383049U, // VCMPPDZ128rmbik 1919417353U, // VCMPPDZ128rmi 300272735U, // VCMPPDZ128rmi_alt 1202981983U, // VCMPPDZ128rmi_altk 4067818505U, // VCMPPDZ128rmik 1114127369U, // VCMPPDZ128rri 1088818271U, // VCMPPDZ128rri_alt 1357581407U, // VCMPPDZ128rri_altk 1383480329U, // VCMPPDZ128rrik 2456288265U, // VCMPPDZ256rmbi 1657130079U, // VCMPPDZ256rmbi_alt 1737755743U, // VCMPPDZ256rmbi_altk 3799383049U, // VCMPPDZ256rmbik 3530030089U, // VCMPPDZ256rmi 392547423U, // VCMPPDZ256rmi_alt 1205079135U, // VCMPPDZ256rmi_altk 41286665U, // VCMPPDZ256rmik 1114127369U, // VCMPPDZ256rri 1088818271U, // VCMPPDZ256rri_alt 1357581407U, // VCMPPDZ256rri_altk 1383480329U, // VCMPPDZ256rrik 2456288265U, // VCMPPDZrmbi 2462436447U, // VCMPPDZrmbi_alt 2543062111U, // VCMPPDZrmbi_altk 3799383049U, // VCMPPDZrmbik 308804617U, // VCMPPDZrmi 400936031U, // VCMPPDZrmi_alt 1209273439U, // VCMPPDZrmi_altk 578157577U, // VCMPPDZrmik 1114127369U, // VCMPPDZrri 1088818271U, // VCMPPDZrri_alt 1357581407U, // VCMPPDZrri_altk 1210596361U, // VCMPPDZrrib 1212550239U, // VCMPPDZrrib_alt 1481313375U, // VCMPPDZrrib_altk 1479949321U, // VCMPPDZrribk 1383480329U, // VCMPPDZrrik 1919417353U, // VCMPPDrmi 300272735U, // VCMPPDrmi_alt 1114127369U, // VCMPPDrri 1088818271U, // VCMPPDrri_alt 3532127241U, // VCMPPSYrmi 392553880U, // VCMPPSYrmi_alt 1116224521U, // VCMPPSYrri 1088824728U, // VCMPPSYrri_alt 3263691785U, // VCMPPSZ128rmbi 1661330840U, // VCMPPSZ128rmbi_alt 1752442264U, // VCMPPSZ128rmbi_altk 848690185U, // VCMPPSZ128rmbik 1921514505U, // VCMPPSZ128rmi 300279192U, // VCMPPSZ128rmi_alt 1202988440U, // VCMPPSZ128rmi_altk 4069915657U, // VCMPPSZ128rmik 1116224521U, // VCMPPSZ128rri 1088824728U, // VCMPPSZ128rri_alt 1357587864U, // VCMPPSZ128rri_altk 1385577481U, // VCMPPSZ128rrik 3263691785U, // VCMPPSZ256rmbi 2466637208U, // VCMPPSZ256rmbi_alt 2557748632U, // VCMPPSZ256rmbi_altk 848690185U, // VCMPPSZ256rmbik 3532127241U, // VCMPPSZ256rmi 392553880U, // VCMPPSZ256rmi_alt 1205085592U, // VCMPPSZ256rmi_altk 43383817U, // VCMPPSZ256rmik 1116224521U, // VCMPPSZ256rri 1088824728U, // VCMPPSZ256rri_alt 1357587864U, // VCMPPSZ256rri_altk 1385577481U, // VCMPPSZ256rrik 3263691785U, // VCMPPSZrmbi 2735072664U, // VCMPPSZrmbi_alt 2826184088U, // VCMPPSZrmbi_altk 848690185U, // VCMPPSZrmbik 310901769U, // VCMPPSZrmi 400942488U, // VCMPPSZrmi_alt 1209279896U, // VCMPPSZrmi_altk 580254729U, // VCMPPSZrmik 1116224521U, // VCMPPSZrri 1088824728U, // VCMPPSZrri_alt 1357587864U, // VCMPPSZrri_altk 1216887817U, // VCMPPSZrrib 1212556696U, // VCMPPSZrrib_alt 1481319832U, // VCMPPSZrrib_altk 1486240777U, // VCMPPSZrribk 1385577481U, // VCMPPSZrrik 1921514505U, // VCMPPSrmi 300279192U, // VCMPPSrmi_alt 1116224521U, // VCMPPSrri 1088824728U, // VCMPPSrri_alt 2460482569U, // VCMPSDZrm 2460482569U, // VCMPSDZrm_Int 3803577353U, // VCMPSDZrm_Intk 851824503U, // VCMPSDZrmi_alt 932450167U, // VCMPSDZrmi_altk 1118321673U, // VCMPSDZrr 1118321673U, // VCMPSDZrr_Int 1387674633U, // VCMPSDZrr_Intk 1218984969U, // VCMPSDZrrb_Int 1488337929U, // VCMPSDZrrb_Intk 1212551031U, // VCMPSDZrrb_alt 1481314167U, // VCMPSDZrrb_altk 1088819063U, // VCMPSDZrri_alt 1357582199U, // VCMPSDZrri_altk 2460482569U, // VCMPSDrm 2460482569U, // VCMPSDrm_Int 851824503U, // VCMPSDrm_alt 1118321673U, // VCMPSDrr 1118321673U, // VCMPSDrr_Int 1088819063U, // VCMPSDrr_alt 3269983241U, // VCMPSSZrm 3269983241U, // VCMPSSZrm_Int 854981641U, // VCMPSSZrm_Intk 856025224U, // VCMPSSZrmi_alt 947136648U, // VCMPSSZrmi_altk 1122515977U, // VCMPSSZrr 1122515977U, // VCMPSSZrr_Int 1391868937U, // VCMPSSZrr_Intk 1221082121U, // VCMPSSZrrb_Int 1490435081U, // VCMPSSZrrb_Intk 1212557448U, // VCMPSSZrrb_alt 1481320584U, // VCMPSSZrrb_altk 1088825480U, // VCMPSSZrri_alt 1357588616U, // VCMPSSZrri_altk 3269983241U, // VCMPSSrm 3269983241U, // VCMPSSrm_Int 856025224U, // VCMPSSrm_alt 1122515977U, // VCMPSSrr 1122515977U, // VCMPSSrr_Int 1088825480U, // VCMPSSrr_alt 552177480U, // VCOMISDZrm 552177480U, // VCOMISDZrm_Int 551833416U, // VCOMISDZrr 551833416U, // VCOMISDZrr_Int 551843439U, // VCOMISDZrrb 552177480U, // VCOMISDrm 552177480U, // VCOMISDrm_Int 551833416U, // VCOMISDrr 551833416U, // VCOMISDrr_Int 552200282U, // VCOMISSZrm 552200282U, // VCOMISSZrm_Int 551839834U, // VCOMISSZrr 551839834U, // VCOMISSZrr_Int 551843908U, // VCOMISSZrrb 552200282U, // VCOMISSrm 552200282U, // VCOMISSrm_Int 551839834U, // VCOMISSrr 551839834U, // VCOMISSrr_Int 65047797U, // VCOMPRESSPDZ128mr 3286568181U, // VCOMPRESSPDZ128mrk 551832821U, // VCOMPRESSPDZ128rr 3230698741U, // VCOMPRESSPDZ128rrk 3229666549U, // VCOMPRESSPDZ128rrkz 148933877U, // VCOMPRESSPDZ256mr 3370454261U, // VCOMPRESSPDZ256mrk 551832821U, // VCOMPRESSPDZ256rr 3230698741U, // VCOMPRESSPDZ256rrk 3229666549U, // VCOMPRESSPDZ256rrkz 151031029U, // VCOMPRESSPDZmr 3372551413U, // VCOMPRESSPDZmrk 551832821U, // VCOMPRESSPDZrr 3230698741U, // VCOMPRESSPDZrrk 3229666549U, // VCOMPRESSPDZrrkz 65054237U, // VCOMPRESSPSZ128mr 3286574621U, // VCOMPRESSPSZ128mrk 551839261U, // VCOMPRESSPSZ128rr 3230705181U, // VCOMPRESSPSZ128rrk 3229672989U, // VCOMPRESSPSZ128rrkz 148940317U, // VCOMPRESSPSZ256mr 3370460701U, // VCOMPRESSPSZ256mrk 551839261U, // VCOMPRESSPSZ256rr 3230705181U, // VCOMPRESSPSZ256rrk 3229672989U, // VCOMPRESSPSZ256rrkz 151037469U, // VCOMPRESSPSZmr 3372557853U, // VCOMPRESSPSZmrk 551839261U, // VCOMPRESSPSZrr 3230705181U, // VCOMPRESSPSZrrk 3229672989U, // VCOMPRESSPSZrrkz 264668U, // VCVTDQ2PDYrm 551832028U, // VCVTDQ2PDYrr 551913948U, // VCVTDQ2PDZ128rm 627395036U, // VCVTDQ2PDZ128rmb 628509148U, // VCVTDQ2PDZ128rmbk 627132892U, // VCVTDQ2PDZ128rmbkz 552913372U, // VCVTDQ2PDZ128rmk 551651804U, // VCVTDQ2PDZ128rmkz 551832028U, // VCVTDQ2PDZ128rr 3230697948U, // VCVTDQ2PDZ128rrk 3229665756U, // VCVTDQ2PDZ128rrkz 264668U, // VCVTDQ2PDZ256rm 629492188U, // VCVTDQ2PDZ256rmb 630606300U, // VCVTDQ2PDZ256rmbk 629230044U, // VCVTDQ2PDZ256rmbkz 3230992860U, // VCVTDQ2PDZ256rmk 3229862364U, // VCVTDQ2PDZ256rmkz 551832028U, // VCVTDQ2PDZ256rr 3230697948U, // VCVTDQ2PDZ256rrk 3229665756U, // VCVTDQ2PDZ256rrkz 552946140U, // VCVTDQ2PDZrm 631589340U, // VCVTDQ2PDZrmb 632703452U, // VCVTDQ2PDZrmbk 631327196U, // VCVTDQ2PDZrmbkz 3231025628U, // VCVTDQ2PDZrmk 3230878172U, // VCVTDQ2PDZrmkz 551832028U, // VCVTDQ2PDZrr 3230697948U, // VCVTDQ2PDZrrk 3229665756U, // VCVTDQ2PDZrrkz 551913948U, // VCVTDQ2PDrm 551832028U, // VCVTDQ2PDrr 552952556U, // VCVTDQ2PSYrm 551838444U, // VCVTDQ2PSYrr 271084U, // VCVTDQ2PSZ128rm 629498604U, // VCVTDQ2PSZ128rmb 630612716U, // VCVTDQ2PSZ128rmbk 629236460U, // VCVTDQ2PSZ128rmbkz 3230999276U, // VCVTDQ2PSZ128rmk 3229868780U, // VCVTDQ2PSZ128rmkz 551838444U, // VCVTDQ2PSZ128rr 3230704364U, // VCVTDQ2PSZ128rrk 3229672172U, // VCVTDQ2PSZ128rrkz 552952556U, // VCVTDQ2PSZ256rm 631595756U, // VCVTDQ2PSZ256rmb 632709868U, // VCVTDQ2PSZ256rmbk 631333612U, // VCVTDQ2PSZ256rmbkz 3231032044U, // VCVTDQ2PSZ256rmk 3230884588U, // VCVTDQ2PSZ256rmkz 551838444U, // VCVTDQ2PSZ256rr 3230704364U, // VCVTDQ2PSZ256rrk 3229672172U, // VCVTDQ2PSZ256rrkz 552444652U, // VCVTDQ2PSZrm 633692908U, // VCVTDQ2PSZrmb 634807020U, // VCVTDQ2PSZrmbk 633430764U, // VCVTDQ2PSZrmbkz 3231097580U, // VCVTDQ2PSZrmk 3230900972U, // VCVTDQ2PSZrmkz 551838444U, // VCVTDQ2PSZrr 1499884U, // VCVTDQ2PSZrrb 3230835436U, // VCVTDQ2PSZrrbk 3230802668U, // VCVTDQ2PSZrrbkz 3230704364U, // VCVTDQ2PSZrrk 3229672172U, // VCVTDQ2PSZrrkz 271084U, // VCVTDQ2PSrm 551838444U, // VCVTDQ2PSrr 1355912U, // VCVTPD2DQYrm 551836178U, // VCVTPD2DQYrr 667661U, // VCVTPD2DQZ128rm 627677714U, // VCVTPD2DQZ128rmb 628103698U, // VCVTPD2DQZ128rmbk 627202578U, // VCVTPD2DQZ128rmbkz 3230609421U, // VCVTPD2DQZ128rmk 3229757453U, // VCVTPD2DQZ128rmkz 551836178U, // VCVTPD2DQZ128rr 3230702098U, // VCVTPD2DQZ128rrk 3229669906U, // VCVTPD2DQZ128rrkz 1355912U, // VCVTPD2DQZ256rm 629774866U, // VCVTPD2DQZ256rmb 630200850U, // VCVTPD2DQZ256rmbk 629299730U, // VCVTPD2DQZ256rmbkz 3230740616U, // VCVTPD2DQZ256rmk 3230642312U, // VCVTPD2DQZ256rmkz 551836178U, // VCVTPD2DQZ256rr 3230702098U, // VCVTPD2DQZ256rrk 3229669906U, // VCVTPD2DQZ256rrkz 1514002U, // VCVTPD2DQZrm 631872018U, // VCVTPD2DQZrmb 632298002U, // VCVTPD2DQZrmbk 631396882U, // VCVTPD2DQZrmbkz 3230784018U, // VCVTPD2DQZrmk 3230751250U, // VCVTPD2DQZrmkz 551836178U, // VCVTPD2DQZrr 1497618U, // VCVTPD2DQZrrb 3230833170U, // VCVTPD2DQZrrbk 3230800402U, // VCVTPD2DQZrrbkz 3230702098U, // VCVTPD2DQZrrk 3229669906U, // VCVTPD2DQZrrkz 667661U, // VCVTPD2DQrm 551836178U, // VCVTPD2DQrr 1355961U, // VCVTPD2PSYrm 551838380U, // VCVTPD2PSYrr 667700U, // VCVTPD2PSZ128rm 627679916U, // VCVTPD2PSZ128rmb 628105900U, // VCVTPD2PSZ128rmbk 627204780U, // VCVTPD2PSZ128rmbkz 3230609460U, // VCVTPD2PSZ128rmk 3229757492U, // VCVTPD2PSZ128rmkz 551838380U, // VCVTPD2PSZ128rr 3230704300U, // VCVTPD2PSZ128rrk 3229672108U, // VCVTPD2PSZ128rrkz 1355961U, // VCVTPD2PSZ256rm 629777068U, // VCVTPD2PSZ256rmb 630203052U, // VCVTPD2PSZ256rmbk 629301932U, // VCVTPD2PSZ256rmbkz 3230740665U, // VCVTPD2PSZ256rmk 3230642361U, // VCVTPD2PSZ256rmkz 551838380U, // VCVTPD2PSZ256rr 3230704300U, // VCVTPD2PSZ256rrk 3229672108U, // VCVTPD2PSZ256rrkz 1516204U, // VCVTPD2PSZrm 631874220U, // VCVTPD2PSZrmb 632300204U, // VCVTPD2PSZrmbk 631399084U, // VCVTPD2PSZrmbkz 3230786220U, // VCVTPD2PSZrmk 3230753452U, // VCVTPD2PSZrmkz 551838380U, // VCVTPD2PSZrr 1499820U, // VCVTPD2PSZrrb 3230835372U, // VCVTPD2PSZrrbk 3230802604U, // VCVTPD2PSZrrbkz 3230704300U, // VCVTPD2PSZrrk 3229672108U, // VCVTPD2PSZrrkz 667700U, // VCVTPD2PSrm 551838380U, // VCVTPD2PSrr 662977U, // VCVTPD2QQZ128rm 627678657U, // VCVTPD2QQZ128rmb 628104641U, // VCVTPD2QQZ128rmbk 627203521U, // VCVTPD2QQZ128rmbkz 3230604737U, // VCVTPD2QQZ128rmk 3229752769U, // VCVTPD2QQZ128rmkz 551837121U, // VCVTPD2QQZ128rr 3230703041U, // VCVTPD2QQZ128rrk 3229670849U, // VCVTPD2QQZ128rrkz 1351105U, // VCVTPD2QQZ256rm 629775809U, // VCVTPD2QQZ256rmb 630201793U, // VCVTPD2QQZ256rmbk 629300673U, // VCVTPD2QQZ256rmbkz 3230735809U, // VCVTPD2QQZ256rmk 3230637505U, // VCVTPD2QQZ256rmkz 551837121U, // VCVTPD2QQZ256rr 3230703041U, // VCVTPD2QQZ256rrk 3229670849U, // VCVTPD2QQZ256rrkz 1514945U, // VCVTPD2QQZrm 631872961U, // VCVTPD2QQZrmb 632298945U, // VCVTPD2QQZrmbk 631397825U, // VCVTPD2QQZrmbkz 3230784961U, // VCVTPD2QQZrmk 3230752193U, // VCVTPD2QQZrmkz 551837121U, // VCVTPD2QQZrr 1498561U, // VCVTPD2QQZrrb 3230834113U, // VCVTPD2QQZrrbk 3230801345U, // VCVTPD2QQZrrbkz 3230703041U, // VCVTPD2QQZrrk 3229670849U, // VCVTPD2QQZrrkz 667687U, // VCVTPD2UDQZ128rm 627678055U, // VCVTPD2UDQZ128rmb 628104039U, // VCVTPD2UDQZ128rmbk 627202919U, // VCVTPD2UDQZ128rmbkz 3230609447U, // VCVTPD2UDQZ128rmk 3229757479U, // VCVTPD2UDQZ128rmkz 551836519U, // VCVTPD2UDQZ128rr 3230702439U, // VCVTPD2UDQZ128rrk 3229670247U, // VCVTPD2UDQZ128rrkz 1355938U, // VCVTPD2UDQZ256rm 629775207U, // VCVTPD2UDQZ256rmb 630201191U, // VCVTPD2UDQZ256rmbk 629300071U, // VCVTPD2UDQZ256rmbkz 3230740642U, // VCVTPD2UDQZ256rmk 3230642338U, // VCVTPD2UDQZ256rmkz 551836519U, // VCVTPD2UDQZ256rr 3230702439U, // VCVTPD2UDQZ256rrk 3229670247U, // VCVTPD2UDQZ256rrkz 1514343U, // VCVTPD2UDQZrm 631872359U, // VCVTPD2UDQZrmb 632298343U, // VCVTPD2UDQZrmbk 631397223U, // VCVTPD2UDQZrmbkz 3230784359U, // VCVTPD2UDQZrmk 3230751591U, // VCVTPD2UDQZrmkz 551836519U, // VCVTPD2UDQZrr 1497959U, // VCVTPD2UDQZrrb 3230833511U, // VCVTPD2UDQZrrbk 3230800743U, // VCVTPD2UDQZrrbkz 3230702439U, // VCVTPD2UDQZrrk 3229670247U, // VCVTPD2UDQZrrkz 663059U, // VCVTPD2UQQZ128rm 627678739U, // VCVTPD2UQQZ128rmb 628104723U, // VCVTPD2UQQZ128rmbk 627203603U, // VCVTPD2UQQZ128rmbkz 3230604819U, // VCVTPD2UQQZ128rmk 3229752851U, // VCVTPD2UQQZ128rmkz 551837203U, // VCVTPD2UQQZ128rr 3230703123U, // VCVTPD2UQQZ128rrk 3229670931U, // VCVTPD2UQQZ128rrkz 1351187U, // VCVTPD2UQQZ256rm 629775891U, // VCVTPD2UQQZ256rmb 630201875U, // VCVTPD2UQQZ256rmbk 629300755U, // VCVTPD2UQQZ256rmbkz 3230735891U, // VCVTPD2UQQZ256rmk 3230637587U, // VCVTPD2UQQZ256rmkz 551837203U, // VCVTPD2UQQZ256rr 3230703123U, // VCVTPD2UQQZ256rrk 3229670931U, // VCVTPD2UQQZ256rrkz 1515027U, // VCVTPD2UQQZrm 631873043U, // VCVTPD2UQQZrmb 632299027U, // VCVTPD2UQQZrmbk 631397907U, // VCVTPD2UQQZrmbkz 3230785043U, // VCVTPD2UQQZrmk 3230752275U, // VCVTPD2UQQZrmkz 551837203U, // VCVTPD2UQQZrr 1498643U, // VCVTPD2UQQZrrb 3230834195U, // VCVTPD2UQQZrrbk 3230801427U, // VCVTPD2UQQZrrbkz 3230703123U, // VCVTPD2UQQZrrk 3229670931U, // VCVTPD2UQQZrrkz 664247U, // VCVTPH2PSYrm 551838391U, // VCVTPH2PSYrr 552182455U, // VCVTPH2PSZ128rm 552608439U, // VCVTPH2PSZ128rmk 551707319U, // VCVTPH2PSZ128rmkz 551838391U, // VCVTPH2PSZ128rr 3230704311U, // VCVTPH2PSZ128rrk 3229672119U, // VCVTPH2PSZ128rrkz 664247U, // VCVTPH2PSZ256rm 3230606007U, // VCVTPH2PSZ256rmk 3229754039U, // VCVTPH2PSZ256rmkz 551838391U, // VCVTPH2PSZ256rr 3230704311U, // VCVTPH2PSZ256rrk 3229672119U, // VCVTPH2PSZ256rrkz 1352375U, // VCVTPH2PSZrm 3230737079U, // VCVTPH2PSZrmk 3230638775U, // VCVTPH2PSZrmkz 551838391U, // VCVTPH2PSZrr 551843737U, // VCVTPH2PSZrrb 3230709657U, // VCVTPH2PSZrrbk 3229677465U, // VCVTPH2PSZrrbkz 3230704311U, // VCVTPH2PSZrrk 3229672119U, // VCVTPH2PSZrrkz 552182455U, // VCVTPH2PSrm 551838391U, // VCVTPH2PSrr 1350194U, // VCVTPS2DQYrm 551836210U, // VCVTPS2DQYrr 662066U, // VCVTPS2DQZ128rm 629791282U, // VCVTPS2DQZ128rmb 630397490U, // VCVTPS2DQZ128rmbk 629316146U, // VCVTPS2DQZ128rmbkz 3230603826U, // VCVTPS2DQZ128rmk 3229751858U, // VCVTPS2DQZ128rmkz 551836210U, // VCVTPS2DQZ128rr 3230702130U, // VCVTPS2DQZ128rrk 3229669938U, // VCVTPS2DQZ128rrkz 1350194U, // VCVTPS2DQZ256rm 631888434U, // VCVTPS2DQZ256rmb 632494642U, // VCVTPS2DQZ256rmbk 631413298U, // VCVTPS2DQZ256rmbkz 3230734898U, // VCVTPS2DQZ256rmk 3230636594U, // VCVTPS2DQZ256rmkz 551836210U, // VCVTPS2DQZ256rr 3230702130U, // VCVTPS2DQZ256rrk 3229669938U, // VCVTPS2DQZ256rrkz 1514034U, // VCVTPS2DQZrm 633985586U, // VCVTPS2DQZrmb 634591794U, // VCVTPS2DQZrmbk 633510450U, // VCVTPS2DQZrmbkz 3230784050U, // VCVTPS2DQZrmk 3230751282U, // VCVTPS2DQZrmkz 551836210U, // VCVTPS2DQZrr 1497650U, // VCVTPS2DQZrrb 3230833202U, // VCVTPS2DQZrrbk 3230800434U, // VCVTPS2DQZrrbkz 3230702130U, // VCVTPS2DQZrrk 3229669938U, // VCVTPS2DQZrrkz 662066U, // VCVTPS2DQrm 551836210U, // VCVTPS2DQrr 657930U, // VCVTPS2PDYrm 551832074U, // VCVTPS2PDYrr 552176138U, // VCVTPS2PDZ128rm 627689994U, // VCVTPS2PDZ128rmb 628296202U, // VCVTPS2PDZ128rmbk 627214858U, // VCVTPS2PDZ128rmbkz 552602122U, // VCVTPS2PDZ128rmk 551701002U, // VCVTPS2PDZ128rmkz 551832074U, // VCVTPS2PDZ128rr 3230697994U, // VCVTPS2PDZ128rrk 3229665802U, // VCVTPS2PDZ128rrkz 657930U, // VCVTPS2PDZ256rm 629787146U, // VCVTPS2PDZ256rmb 630393354U, // VCVTPS2PDZ256rmbk 629312010U, // VCVTPS2PDZ256rmbkz 3230599690U, // VCVTPS2PDZ256rmk 3229747722U, // VCVTPS2PDZ256rmkz 551832074U, // VCVTPS2PDZ256rr 3230697994U, // VCVTPS2PDZ256rrk 3229665802U, // VCVTPS2PDZ256rrkz 1346058U, // VCVTPS2PDZrm 631884298U, // VCVTPS2PDZrmb 632490506U, // VCVTPS2PDZrmbk 631409162U, // VCVTPS2PDZrmbkz 3230730762U, // VCVTPS2PDZrmk 3230632458U, // VCVTPS2PDZrmkz 551832074U, // VCVTPS2PDZrr 551843266U, // VCVTPS2PDZrrb 3230709186U, // VCVTPS2PDZrrbk 3229676994U, // VCVTPS2PDZrrbkz 3230697994U, // VCVTPS2PDZrrk 3229665802U, // VCVTPS2PDZrrkz 552176138U, // VCVTPS2PDrm 551832074U, // VCVTPS2PDrr 1126470238U, // VCVTPS2PHYmr 283431518U, // VCVTPS2PHYrr 1394905694U, // VCVTPS2PHZ128mr 1495650910U, // VCVTPS2PHZ128mrk 283431518U, // VCVTPS2PHZ128rr 1357582942U, // VCVTPS2PHZ128rrk 1088819806U, // VCVTPS2PHZ128rrkz 1126470238U, // VCVTPS2PHZ256mr 1227215454U, // VCVTPS2PHZ256mrk 283431518U, // VCVTPS2PHZ256rr 1357582942U, // VCVTPS2PHZ256rrk 1088819806U, // VCVTPS2PHZ256rrkz 1663341150U, // VCVTPS2PHZmr 1764086366U, // VCVTPS2PHZmrk 283431518U, // VCVTPS2PHZrr 407163486U, // VCVTPS2PHZrrb 1481314910U, // VCVTPS2PHZrrbk 1212551774U, // VCVTPS2PHZrrbkz 1357582942U, // VCVTPS2PHZrrk 1088819806U, // VCVTPS2PHZrrkz 1394905694U, // VCVTPS2PHmr 283431518U, // VCVTPS2PHrr 552181208U, // VCVTPS2QQZ128rm 627695064U, // VCVTPS2QQZ128rmb 628301272U, // VCVTPS2QQZ128rmbk 627219928U, // VCVTPS2QQZ128rmbkz 552607192U, // VCVTPS2QQZ128rmk 551706072U, // VCVTPS2QQZ128rmkz 551837144U, // VCVTPS2QQZ128rr 3230703064U, // VCVTPS2QQZ128rrk 3229670872U, // VCVTPS2QQZ128rrkz 663000U, // VCVTPS2QQZ256rm 629792216U, // VCVTPS2QQZ256rmb 630398424U, // VCVTPS2QQZ256rmbk 629317080U, // VCVTPS2QQZ256rmbkz 3230604760U, // VCVTPS2QQZ256rmk 3229752792U, // VCVTPS2QQZ256rmkz 551837144U, // VCVTPS2QQZ256rr 3230703064U, // VCVTPS2QQZ256rrk 3229670872U, // VCVTPS2QQZ256rrkz 1351128U, // VCVTPS2QQZrm 631889368U, // VCVTPS2QQZrmb 632495576U, // VCVTPS2QQZrmbk 631414232U, // VCVTPS2QQZrmbkz 3230735832U, // VCVTPS2QQZrmk 3230637528U, // VCVTPS2QQZrmkz 551837144U, // VCVTPS2QQZrr 1498584U, // VCVTPS2QQZrrb 3230834136U, // VCVTPS2QQZrrbk 3230801368U, // VCVTPS2QQZrrbkz 3230703064U, // VCVTPS2QQZrrk 3229670872U, // VCVTPS2QQZrrkz 662400U, // VCVTPS2UDQZ128rm 629791616U, // VCVTPS2UDQZ128rmb 630397824U, // VCVTPS2UDQZ128rmbk 629316480U, // VCVTPS2UDQZ128rmbkz 3230604160U, // VCVTPS2UDQZ128rmk 3229752192U, // VCVTPS2UDQZ128rmkz 551836544U, // VCVTPS2UDQZ128rr 3230702464U, // VCVTPS2UDQZ128rrk 3229670272U, // VCVTPS2UDQZ128rrkz 1350528U, // VCVTPS2UDQZ256rm 631888768U, // VCVTPS2UDQZ256rmb 632494976U, // VCVTPS2UDQZ256rmbk 631413632U, // VCVTPS2UDQZ256rmbkz 3230735232U, // VCVTPS2UDQZ256rmk 3230636928U, // VCVTPS2UDQZ256rmkz 551836544U, // VCVTPS2UDQZ256rr 3230702464U, // VCVTPS2UDQZ256rrk 3229670272U, // VCVTPS2UDQZ256rrkz 1514368U, // VCVTPS2UDQZrm 633985920U, // VCVTPS2UDQZrmb 634592128U, // VCVTPS2UDQZrmbk 633510784U, // VCVTPS2UDQZrmbkz 3230784384U, // VCVTPS2UDQZrmk 3230751616U, // VCVTPS2UDQZrmkz 551836544U, // VCVTPS2UDQZrr 1497984U, // VCVTPS2UDQZrrb 3230833536U, // VCVTPS2UDQZrrbk 3230800768U, // VCVTPS2UDQZrrbkz 3230702464U, // VCVTPS2UDQZrrk 3229670272U, // VCVTPS2UDQZrrkz 552181292U, // VCVTPS2UQQZ128rm 627695148U, // VCVTPS2UQQZ128rmb 628301356U, // VCVTPS2UQQZ128rmbk 627220012U, // VCVTPS2UQQZ128rmbkz 552607276U, // VCVTPS2UQQZ128rmk 551706156U, // VCVTPS2UQQZ128rmkz 551837228U, // VCVTPS2UQQZ128rr 3230703148U, // VCVTPS2UQQZ128rrk 3229670956U, // VCVTPS2UQQZ128rrkz 663084U, // VCVTPS2UQQZ256rm 629792300U, // VCVTPS2UQQZ256rmb 630398508U, // VCVTPS2UQQZ256rmbk 629317164U, // VCVTPS2UQQZ256rmbkz 3230604844U, // VCVTPS2UQQZ256rmk 3229752876U, // VCVTPS2UQQZ256rmkz 551837228U, // VCVTPS2UQQZ256rr 3230703148U, // VCVTPS2UQQZ256rrk 3229670956U, // VCVTPS2UQQZ256rrkz 1351212U, // VCVTPS2UQQZrm 631889452U, // VCVTPS2UQQZrmb 632495660U, // VCVTPS2UQQZrmbk 631414316U, // VCVTPS2UQQZrmbkz 3230735916U, // VCVTPS2UQQZrmk 3230637612U, // VCVTPS2UQQZrmkz 551837228U, // VCVTPS2UQQZrr 1498668U, // VCVTPS2UQQZrrb 3230834220U, // VCVTPS2UQQZrrbk 3230801452U, // VCVTPS2UQQZrrbkz 3230703148U, // VCVTPS2UQQZrrk 3229670956U, // VCVTPS2UQQZrrkz 264691U, // VCVTQQ2PDZ128rm 627411443U, // VCVTQQ2PDZ128rmb 628410867U, // VCVTQQ2PDZ128rmbk 627149299U, // VCVTQQ2PDZ128rmbkz 3230992883U, // VCVTQQ2PDZ128rmk 3229862387U, // VCVTQQ2PDZ128rmkz 551832051U, // VCVTQQ2PDZ128rr 3230697971U, // VCVTQQ2PDZ128rrk 3229665779U, // VCVTQQ2PDZ128rrkz 552946163U, // VCVTQQ2PDZ256rm 629508595U, // VCVTQQ2PDZ256rmb 630508019U, // VCVTQQ2PDZ256rmbk 629246451U, // VCVTQQ2PDZ256rmbkz 3231025651U, // VCVTQQ2PDZ256rmk 3230878195U, // VCVTQQ2PDZ256rmkz 551832051U, // VCVTQQ2PDZ256rr 3230697971U, // VCVTQQ2PDZ256rrk 3229665779U, // VCVTQQ2PDZ256rrkz 552438259U, // VCVTQQ2PDZrm 631605747U, // VCVTQQ2PDZrmb 632605171U, // VCVTQQ2PDZrmbk 631343603U, // VCVTQQ2PDZrmbkz 3231091187U, // VCVTQQ2PDZrmk 3230894579U, // VCVTQQ2PDZrmkz 551832051U, // VCVTQQ2PDZrr 1493491U, // VCVTQQ2PDZrrb 3230829043U, // VCVTQQ2PDZrrbk 3230796275U, // VCVTQQ2PDZrrbkz 3230697971U, // VCVTQQ2PDZrrk 3229665779U, // VCVTQQ2PDZrrkz 274496U, // VCVTQQ2PSZ128rm 627417859U, // VCVTQQ2PSZ128rmb 628417283U, // VCVTQQ2PSZ128rmbk 627155715U, // VCVTQQ2PSZ128rmbkz 3231002688U, // VCVTQQ2PSZ128rmk 3229872192U, // VCVTQQ2PSZ128rmkz 551838467U, // VCVTQQ2PSZ128rr 3230704387U, // VCVTQQ2PSZ128rrk 3229672195U, // VCVTQQ2PSZ128rrkz 552956101U, // VCVTQQ2PSZ256rm 629515011U, // VCVTQQ2PSZ256rmb 630514435U, // VCVTQQ2PSZ256rmbk 629252867U, // VCVTQQ2PSZ256rmbkz 3231035589U, // VCVTQQ2PSZ256rmk 3230888133U, // VCVTQQ2PSZ256rmkz 551838467U, // VCVTQQ2PSZ256rr 3230704387U, // VCVTQQ2PSZ256rrk 3229672195U, // VCVTQQ2PSZ256rrkz 552444675U, // VCVTQQ2PSZrm 631612163U, // VCVTQQ2PSZrmb 632611587U, // VCVTQQ2PSZrmbk 631350019U, // VCVTQQ2PSZrmbkz 3231097603U, // VCVTQQ2PSZrmk 3230900995U, // VCVTQQ2PSZrmkz 551838467U, // VCVTQQ2PSZrr 1499907U, // VCVTQQ2PSZrrb 3230835459U, // VCVTQQ2PSZrrbk 3230802691U, // VCVTQQ2PSZrrbkz 3230704387U, // VCVTQQ2PSZrrk 3229672195U, // VCVTQQ2PSZrrkz 552178432U, // VCVTSD2SI64Zrm_Int 551834368U, // VCVTSD2SI64Zrr_Int 1495808U, // VCVTSD2SI64Zrrb_Int 552178432U, // VCVTSD2SI64rm_Int 551834368U, // VCVTSD2SI64rr_Int 552178432U, // VCVTSD2SIZrm_Int 551834368U, // VCVTSD2SIZrr_Int 1495808U, // VCVTSD2SIZrrb_Int 552178432U, // VCVTSD2SIrm_Int 551834368U, // VCVTSD2SIrr_Int 283273051U, // VCVTSD2SSZrm 283273051U, // VCVTSD2SSZrm_Int 1357899611U, // VCVTSD2SSZrm_Intk 1089480539U, // VCVTSD2SSZrm_Intkz 811657051U, // VCVTSD2SSZrr 811657051U, // VCVTSD2SSZrr_Int 87058267U, // VCVTSD2SSZrr_Intk 890283867U, // VCVTSD2SSZrr_Intkz 812787547U, // VCVTSD2SSZrrb_Int 87189339U, // VCVTSD2SSZrrb_Intk 890414939U, // VCVTSD2SSZrrb_Intkz 283273051U, // VCVTSD2SSrm 283273051U, // VCVTSD2SSrm_Int 811657051U, // VCVTSD2SSrr 811657051U, // VCVTSD2SSrr_Int 552178479U, // VCVTSD2USI64Zrm_Int 551834415U, // VCVTSD2USI64Zrr_Int 1495855U, // VCVTSD2USI64Zrrb_Int 552178479U, // VCVTSD2USIZrm_Int 551834415U, // VCVTSD2USIZrr_Int 1495855U, // VCVTSD2USIZrrb_Int 283202602U, // VCVTSI2SDZrm 283202602U, // VCVTSI2SDZrm_Int 811652138U, // VCVTSI2SDZrr 811652138U, // VCVTSI2SDZrr_Int 155243562U, // VCVTSI2SDZrrb_Int 283202602U, // VCVTSI2SDrm 283202602U, // VCVTSI2SDrm_Int 811652138U, // VCVTSI2SDrr 811652138U, // VCVTSI2SDrr_Int 283203306U, // VCVTSI2SSZrm 283203306U, // VCVTSI2SSZrm_Int 811652842U, // VCVTSI2SSZrr 811652842U, // VCVTSI2SSZrr_Int 155244266U, // VCVTSI2SSZrrb_Int 283203306U, // VCVTSI2SSrm 283203306U, // VCVTSI2SSrm_Int 811652842U, // VCVTSI2SSrr 811652842U, // VCVTSI2SSrr_Int 283220791U, // VCVTSI642SDZrm 283220791U, // VCVTSI642SDZrm_Int 811653943U, // VCVTSI642SDZrr 811653943U, // VCVTSI642SDZrr_Int 155245367U, // VCVTSI642SDZrrb_Int 283220791U, // VCVTSI642SDrm 283220791U, // VCVTSI642SDrm_Int 811653943U, // VCVTSI642SDrr 811653943U, // VCVTSI642SDrr_Int 283221758U, // VCVTSI642SSZrm 283221758U, // VCVTSI642SSZrm_Int 811654910U, // VCVTSI642SSZrr 811654910U, // VCVTSI642SSZrr_Int 155246334U, // VCVTSI642SSZrrb_Int 283221758U, // VCVTSI642SSrm 283221758U, // VCVTSI642SSrm_Int 811654910U, // VCVTSI642SSrr 811654910U, // VCVTSI642SSrr_Int 283283032U, // VCVTSS2SDZrm 283283032U, // VCVTSS2SDZrm_Int 1358089816U, // VCVTSS2SDZrm_Intk 1089670744U, // VCVTSS2SDZrm_Intkz 811650648U, // VCVTSS2SDZrr 811650648U, // VCVTSS2SDZrr_Int 87051864U, // VCVTSS2SDZrr_Intk 890277464U, // VCVTSS2SDZrr_Intkz 811660840U, // VCVTSS2SDZrrb_Int 87062056U, // VCVTSS2SDZrrb_Intk 890287656U, // VCVTSS2SDZrrb_Intkz 283283032U, // VCVTSS2SDrm 283283032U, // VCVTSS2SDrm_Int 811650648U, // VCVTSS2SDrr 811650648U, // VCVTSS2SDrr_Int 552194839U, // VCVTSS2SI64Zrm_Int 551834391U, // VCVTSS2SI64Zrr_Int 1495831U, // VCVTSS2SI64Zrrb_Int 552194839U, // VCVTSS2SI64rm_Int 551834391U, // VCVTSS2SI64rr_Int 552194839U, // VCVTSS2SIZrm_Int 551834391U, // VCVTSS2SIZrr_Int 1495831U, // VCVTSS2SIZrrb_Int 552194839U, // VCVTSS2SIrm_Int 551834391U, // VCVTSS2SIrr_Int 552194888U, // VCVTSS2USI64Zrm_Int 551834440U, // VCVTSS2USI64Zrr_Int 1495880U, // VCVTSS2USI64Zrrb_Int 552194888U, // VCVTSS2USIZrm_Int 551834440U, // VCVTSS2USIZrr_Int 1495880U, // VCVTSS2USIZrrb_Int 1355899U, // VCVTTPD2DQYrm 551836166U, // VCVTTPD2DQYrr 667648U, // VCVTTPD2DQZ128rm 627677702U, // VCVTTPD2DQZ128rmb 628103686U, // VCVTTPD2DQZ128rmbk 627202566U, // VCVTTPD2DQZ128rmbkz 3230609408U, // VCVTTPD2DQZ128rmk 3229757440U, // VCVTTPD2DQZ128rmkz 551836166U, // VCVTTPD2DQZ128rr 3230702086U, // VCVTTPD2DQZ128rrk 3229669894U, // VCVTTPD2DQZ128rrkz 1355899U, // VCVTTPD2DQZ256rm 629774854U, // VCVTTPD2DQZ256rmb 630200838U, // VCVTTPD2DQZ256rmbk 629299718U, // VCVTTPD2DQZ256rmbkz 3230740603U, // VCVTTPD2DQZ256rmk 3230642299U, // VCVTTPD2DQZ256rmkz 551836166U, // VCVTTPD2DQZ256rr 3230702086U, // VCVTTPD2DQZ256rrk 3229669894U, // VCVTTPD2DQZ256rrkz 1513990U, // VCVTTPD2DQZrm 631872006U, // VCVTTPD2DQZrmb 632297990U, // VCVTTPD2DQZrmbk 631396870U, // VCVTTPD2DQZrmbkz 3230784006U, // VCVTTPD2DQZrmk 3230751238U, // VCVTTPD2DQZrmkz 551836166U, // VCVTTPD2DQZrr 551843581U, // VCVTTPD2DQZrrb 3230709501U, // VCVTTPD2DQZrrbk 3229677309U, // VCVTTPD2DQZrrbkz 3230702086U, // VCVTTPD2DQZrrk 3229669894U, // VCVTTPD2DQZrrkz 667648U, // VCVTTPD2DQrm 551836166U, // VCVTTPD2DQrr 662965U, // VCVTTPD2QQZ128rm 627678645U, // VCVTTPD2QQZ128rmb 628104629U, // VCVTTPD2QQZ128rmbk 627203509U, // VCVTTPD2QQZ128rmbkz 3230604725U, // VCVTTPD2QQZ128rmk 3229752757U, // VCVTTPD2QQZ128rmkz 551837109U, // VCVTTPD2QQZ128rr 3230703029U, // VCVTTPD2QQZ128rrk 3229670837U, // VCVTTPD2QQZ128rrkz 1351093U, // VCVTTPD2QQZ256rm 629775797U, // VCVTTPD2QQZ256rmb 630201781U, // VCVTTPD2QQZ256rmbk 629300661U, // VCVTTPD2QQZ256rmbkz 3230735797U, // VCVTTPD2QQZ256rmk 3230637493U, // VCVTTPD2QQZ256rmkz 551837109U, // VCVTTPD2QQZ256rr 3230703029U, // VCVTTPD2QQZ256rrk 3229670837U, // VCVTTPD2QQZ256rrkz 1514933U, // VCVTTPD2QQZrm 631872949U, // VCVTTPD2QQZrmb 632298933U, // VCVTTPD2QQZrmbk 631397813U, // VCVTTPD2QQZrmbkz 3230784949U, // VCVTTPD2QQZrmk 3230752181U, // VCVTTPD2QQZrmkz 551837109U, // VCVTTPD2QQZrr 551843659U, // VCVTTPD2QQZrrb 3230709579U, // VCVTTPD2QQZrrbk 3229677387U, // VCVTTPD2QQZrrbkz 3230703029U, // VCVTTPD2QQZrrk 3229670837U, // VCVTTPD2QQZrrkz 667673U, // VCVTTPD2UDQZ128rm 627678042U, // VCVTTPD2UDQZ128rmb 628104026U, // VCVTTPD2UDQZ128rmbk 627202906U, // VCVTTPD2UDQZ128rmbkz 3230609433U, // VCVTTPD2UDQZ128rmk 3229757465U, // VCVTTPD2UDQZ128rmkz 551836506U, // VCVTTPD2UDQZ128rr 3230702426U, // VCVTTPD2UDQZ128rrk 3229670234U, // VCVTTPD2UDQZ128rrkz 1355924U, // VCVTTPD2UDQZ256rm 629775194U, // VCVTTPD2UDQZ256rmb 630201178U, // VCVTTPD2UDQZ256rmbk 629300058U, // VCVTTPD2UDQZ256rmbkz 3230740628U, // VCVTTPD2UDQZ256rmk 3230642324U, // VCVTTPD2UDQZ256rmkz 551836506U, // VCVTTPD2UDQZ256rr 3230702426U, // VCVTTPD2UDQZ256rrk 3229670234U, // VCVTTPD2UDQZ256rrkz 1514330U, // VCVTTPD2UDQZrm 631872346U, // VCVTTPD2UDQZrmb 632298330U, // VCVTTPD2UDQZrmbk 631397210U, // VCVTTPD2UDQZrmbkz 3230784346U, // VCVTTPD2UDQZrmk 3230751578U, // VCVTTPD2UDQZrmkz 551836506U, // VCVTTPD2UDQZrr 551843619U, // VCVTTPD2UDQZrrb 3230709539U, // VCVTTPD2UDQZrrbk 3229677347U, // VCVTTPD2UDQZrrbkz 3230702426U, // VCVTTPD2UDQZrrk 3229670234U, // VCVTTPD2UDQZrrkz 663046U, // VCVTTPD2UQQZ128rm 627678726U, // VCVTTPD2UQQZ128rmb 628104710U, // VCVTTPD2UQQZ128rmbk 627203590U, // VCVTTPD2UQQZ128rmbkz 3230604806U, // VCVTTPD2UQQZ128rmk 3229752838U, // VCVTTPD2UQQZ128rmkz 551837190U, // VCVTTPD2UQQZ128rr 3230703110U, // VCVTTPD2UQQZ128rrk 3229670918U, // VCVTTPD2UQQZ128rrkz 1351174U, // VCVTTPD2UQQZ256rm 629775878U, // VCVTTPD2UQQZ256rmb 630201862U, // VCVTTPD2UQQZ256rmbk 629300742U, // VCVTTPD2UQQZ256rmbkz 3230735878U, // VCVTTPD2UQQZ256rmk 3230637574U, // VCVTTPD2UQQZ256rmkz 551837190U, // VCVTTPD2UQQZ256rr 3230703110U, // VCVTTPD2UQQZ256rrk 3229670918U, // VCVTTPD2UQQZ256rrkz 1515014U, // VCVTTPD2UQQZrm 631873030U, // VCVTTPD2UQQZrmb 632299014U, // VCVTTPD2UQQZrmbk 631397894U, // VCVTTPD2UQQZrmbkz 3230785030U, // VCVTTPD2UQQZrmk 3230752262U, // VCVTTPD2UQQZrmkz 551837190U, // VCVTTPD2UQQZrr 551843697U, // VCVTTPD2UQQZrrb 3230709617U, // VCVTTPD2UQQZrrbk 3229677425U, // VCVTTPD2UQQZrrbkz 3230703110U, // VCVTTPD2UQQZrrk 3229670918U, // VCVTTPD2UQQZrrkz 1350182U, // VCVTTPS2DQYrm 551836198U, // VCVTTPS2DQYrr 662054U, // VCVTTPS2DQZ128rm 629791270U, // VCVTTPS2DQZ128rmb 630397478U, // VCVTTPS2DQZ128rmbk 629316134U, // VCVTTPS2DQZ128rmbkz 3230603814U, // VCVTTPS2DQZ128rmk 3229751846U, // VCVTTPS2DQZ128rmkz 551836198U, // VCVTTPS2DQZ128rr 3230702118U, // VCVTTPS2DQZ128rrk 3229669926U, // VCVTTPS2DQZ128rrkz 1350182U, // VCVTTPS2DQZ256rm 631888422U, // VCVTTPS2DQZ256rmb 632494630U, // VCVTTPS2DQZ256rmbk 631413286U, // VCVTTPS2DQZ256rmbkz 3230734886U, // VCVTTPS2DQZ256rmk 3230636582U, // VCVTTPS2DQZ256rmkz 551836198U, // VCVTTPS2DQZ256rr 3230702118U, // VCVTTPS2DQZ256rrk 3229669926U, // VCVTTPS2DQZ256rrkz 1514022U, // VCVTTPS2DQZrm 633985574U, // VCVTTPS2DQZrmb 634591782U, // VCVTTPS2DQZrmbk 633510438U, // VCVTTPS2DQZrmbkz 3230784038U, // VCVTTPS2DQZrmk 3230751270U, // VCVTTPS2DQZrmkz 551836198U, // VCVTTPS2DQZrr 551843600U, // VCVTTPS2DQZrrb 3230709520U, // VCVTTPS2DQZrrbk 3229677328U, // VCVTTPS2DQZrrbkz 3230702118U, // VCVTTPS2DQZrrk 3229669926U, // VCVTTPS2DQZrrkz 662054U, // VCVTTPS2DQrm 551836198U, // VCVTTPS2DQrr 552181196U, // VCVTTPS2QQZ128rm 627695052U, // VCVTTPS2QQZ128rmb 628301260U, // VCVTTPS2QQZ128rmbk 627219916U, // VCVTTPS2QQZ128rmbkz 552607180U, // VCVTTPS2QQZ128rmk 551706060U, // VCVTTPS2QQZ128rmkz 551837132U, // VCVTTPS2QQZ128rr 3230703052U, // VCVTTPS2QQZ128rrk 3229670860U, // VCVTTPS2QQZ128rrkz 662988U, // VCVTTPS2QQZ256rm 629792204U, // VCVTTPS2QQZ256rmb 630398412U, // VCVTTPS2QQZ256rmbk 629317068U, // VCVTTPS2QQZ256rmbkz 3230604748U, // VCVTTPS2QQZ256rmk 3229752780U, // VCVTTPS2QQZ256rmkz 551837132U, // VCVTTPS2QQZ256rr 3230703052U, // VCVTTPS2QQZ256rrk 3229670860U, // VCVTTPS2QQZ256rrkz 1351116U, // VCVTTPS2QQZrm 631889356U, // VCVTTPS2QQZrmb 632495564U, // VCVTTPS2QQZrmbk 631414220U, // VCVTTPS2QQZrmbkz 3230735820U, // VCVTTPS2QQZrmk 3230637516U, // VCVTTPS2QQZrmkz 551837132U, // VCVTTPS2QQZrr 551843678U, // VCVTTPS2QQZrrb 3230709598U, // VCVTTPS2QQZrrbk 3229677406U, // VCVTTPS2QQZrrbkz 3230703052U, // VCVTTPS2QQZrrk 3229670860U, // VCVTTPS2QQZrrkz 662387U, // VCVTTPS2UDQZ128rm 629791603U, // VCVTTPS2UDQZ128rmb 630397811U, // VCVTTPS2UDQZ128rmbk 629316467U, // VCVTTPS2UDQZ128rmbkz 3230604147U, // VCVTTPS2UDQZ128rmk 3229752179U, // VCVTTPS2UDQZ128rmkz 551836531U, // VCVTTPS2UDQZ128rr 3230702451U, // VCVTTPS2UDQZ128rrk 3229670259U, // VCVTTPS2UDQZ128rrkz 1350515U, // VCVTTPS2UDQZ256rm 631888755U, // VCVTTPS2UDQZ256rmb 632494963U, // VCVTTPS2UDQZ256rmbk 631413619U, // VCVTTPS2UDQZ256rmbkz 3230735219U, // VCVTTPS2UDQZ256rmk 3230636915U, // VCVTTPS2UDQZ256rmkz 551836531U, // VCVTTPS2UDQZ256rr 3230702451U, // VCVTTPS2UDQZ256rrk 3229670259U, // VCVTTPS2UDQZ256rrkz 1514355U, // VCVTTPS2UDQZrm 633985907U, // VCVTTPS2UDQZrmb 634592115U, // VCVTTPS2UDQZrmbk 633510771U, // VCVTTPS2UDQZrmbkz 3230784371U, // VCVTTPS2UDQZrmk 3230751603U, // VCVTTPS2UDQZrmkz 551836531U, // VCVTTPS2UDQZrr 551843639U, // VCVTTPS2UDQZrrb 3230709559U, // VCVTTPS2UDQZrrbk 3229677367U, // VCVTTPS2UDQZrrbkz 3230702451U, // VCVTTPS2UDQZrrk 3229670259U, // VCVTTPS2UDQZrrkz 552181279U, // VCVTTPS2UQQZ128rm 627695135U, // VCVTTPS2UQQZ128rmb 628301343U, // VCVTTPS2UQQZ128rmbk 627219999U, // VCVTTPS2UQQZ128rmbkz 552607263U, // VCVTTPS2UQQZ128rmk 551706143U, // VCVTTPS2UQQZ128rmkz 551837215U, // VCVTTPS2UQQZ128rr 3230703135U, // VCVTTPS2UQQZ128rrk 3229670943U, // VCVTTPS2UQQZ128rrkz 663071U, // VCVTTPS2UQQZ256rm 629792287U, // VCVTTPS2UQQZ256rmb 630398495U, // VCVTTPS2UQQZ256rmbk 629317151U, // VCVTTPS2UQQZ256rmbkz 3230604831U, // VCVTTPS2UQQZ256rmk 3229752863U, // VCVTTPS2UQQZ256rmkz 551837215U, // VCVTTPS2UQQZ256rr 3230703135U, // VCVTTPS2UQQZ256rrk 3229670943U, // VCVTTPS2UQQZ256rrkz 1351199U, // VCVTTPS2UQQZrm 631889439U, // VCVTTPS2UQQZrmb 632495647U, // VCVTTPS2UQQZrmbk 631414303U, // VCVTTPS2UQQZrmbkz 3230735903U, // VCVTTPS2UQQZrmk 3230637599U, // VCVTTPS2UQQZrmkz 551837215U, // VCVTTPS2UQQZrr 551843717U, // VCVTTPS2UQQZrrb 3230709637U, // VCVTTPS2UQQZrrbk 3229677445U, // VCVTTPS2UQQZrrbkz 3230703135U, // VCVTTPS2UQQZrrk 3229670943U, // VCVTTPS2UQQZrrkz 552178420U, // VCVTTSD2SI64Zrm 552178420U, // VCVTTSD2SI64Zrm_Int 551834356U, // VCVTTSD2SI64Zrr 551834356U, // VCVTTSD2SI64Zrr_Int 551843503U, // VCVTTSD2SI64Zrrb_Int 552178420U, // VCVTTSD2SI64rm 552178420U, // VCVTTSD2SI64rm_Int 551834356U, // VCVTTSD2SI64rr 551834356U, // VCVTTSD2SI64rr_Int 552178420U, // VCVTTSD2SIZrm 552178420U, // VCVTTSD2SIZrm_Int 551834356U, // VCVTTSD2SIZrr 551834356U, // VCVTTSD2SIZrr_Int 551843503U, // VCVTTSD2SIZrrb_Int 552178420U, // VCVTTSD2SIrm 552178420U, // VCVTTSD2SIrm_Int 551834356U, // VCVTTSD2SIrr 551834356U, // VCVTTSD2SIrr_Int 552178466U, // VCVTTSD2USI64Zrm 552178466U, // VCVTTSD2USI64Zrm_Int 551834402U, // VCVTTSD2USI64Zrr 551834402U, // VCVTTSD2USI64Zrr_Int 551843541U, // VCVTTSD2USI64Zrrb_Int 552178466U, // VCVTTSD2USIZrm 552178466U, // VCVTTSD2USIZrm_Int 551834402U, // VCVTTSD2USIZrr 551834402U, // VCVTTSD2USIZrr_Int 551843541U, // VCVTTSD2USIZrrb_Int 552194827U, // VCVTTSS2SI64Zrm 552194827U, // VCVTTSS2SI64Zrm_Int 551834379U, // VCVTTSS2SI64Zrr 551834379U, // VCVTTSS2SI64Zrr_Int 551843522U, // VCVTTSS2SI64Zrrb_Int 552194827U, // VCVTTSS2SI64rm 552194827U, // VCVTTSS2SI64rm_Int 551834379U, // VCVTTSS2SI64rr 551834379U, // VCVTTSS2SI64rr_Int 552194827U, // VCVTTSS2SIZrm 552194827U, // VCVTTSS2SIZrm_Int 551834379U, // VCVTTSS2SIZrr 551834379U, // VCVTTSS2SIZrr_Int 551843522U, // VCVTTSS2SIZrrb_Int 552194827U, // VCVTTSS2SIrm 552194827U, // VCVTTSS2SIrm_Int 551834379U, // VCVTTSS2SIrr 551834379U, // VCVTTSS2SIrr_Int 552194875U, // VCVTTSS2USI64Zrm 552194875U, // VCVTTSS2USI64Zrm_Int 551834427U, // VCVTTSS2USI64Zrr 551834427U, // VCVTTSS2USI64Zrr_Int 551843561U, // VCVTTSS2USI64Zrrb_Int 552194875U, // VCVTTSS2USIZrm 552194875U, // VCVTTSS2USIZrm_Int 551834427U, // VCVTTSS2USIZrr 551834427U, // VCVTTSS2USIZrr_Int 551843561U, // VCVTTSS2USIZrrb_Int 551913959U, // VCVTUDQ2PDZ128rm 627395047U, // VCVTUDQ2PDZ128rmb 628509159U, // VCVTUDQ2PDZ128rmbk 627132903U, // VCVTUDQ2PDZ128rmbkz 552913383U, // VCVTUDQ2PDZ128rmk 551651815U, // VCVTUDQ2PDZ128rmkz 551832039U, // VCVTUDQ2PDZ128rr 3230697959U, // VCVTUDQ2PDZ128rrk 3229665767U, // VCVTUDQ2PDZ128rrkz 264679U, // VCVTUDQ2PDZ256rm 629492199U, // VCVTUDQ2PDZ256rmb 630606311U, // VCVTUDQ2PDZ256rmbk 629230055U, // VCVTUDQ2PDZ256rmbkz 3230992871U, // VCVTUDQ2PDZ256rmk 3229862375U, // VCVTUDQ2PDZ256rmkz 551832039U, // VCVTUDQ2PDZ256rr 3230697959U, // VCVTUDQ2PDZ256rrk 3229665767U, // VCVTUDQ2PDZ256rrkz 552946151U, // VCVTUDQ2PDZrm 631589351U, // VCVTUDQ2PDZrmb 632703463U, // VCVTUDQ2PDZrmbk 631327207U, // VCVTUDQ2PDZrmbkz 3231025639U, // VCVTUDQ2PDZrmk 3230878183U, // VCVTUDQ2PDZrmkz 551832039U, // VCVTUDQ2PDZrr 3230697959U, // VCVTUDQ2PDZrrk 3229665767U, // VCVTUDQ2PDZrrkz 271095U, // VCVTUDQ2PSZ128rm 629498615U, // VCVTUDQ2PSZ128rmb 630612727U, // VCVTUDQ2PSZ128rmbk 629236471U, // VCVTUDQ2PSZ128rmbkz 3230999287U, // VCVTUDQ2PSZ128rmk 3229868791U, // VCVTUDQ2PSZ128rmkz 551838455U, // VCVTUDQ2PSZ128rr 3230704375U, // VCVTUDQ2PSZ128rrk 3229672183U, // VCVTUDQ2PSZ128rrkz 552952567U, // VCVTUDQ2PSZ256rm 631595767U, // VCVTUDQ2PSZ256rmb 632709879U, // VCVTUDQ2PSZ256rmbk 631333623U, // VCVTUDQ2PSZ256rmbkz 3231032055U, // VCVTUDQ2PSZ256rmk 3230884599U, // VCVTUDQ2PSZ256rmkz 551838455U, // VCVTUDQ2PSZ256rr 3230704375U, // VCVTUDQ2PSZ256rrk 3229672183U, // VCVTUDQ2PSZ256rrkz 552444663U, // VCVTUDQ2PSZrm 633692919U, // VCVTUDQ2PSZrmb 634807031U, // VCVTUDQ2PSZrmbk 633430775U, // VCVTUDQ2PSZrmbkz 3231097591U, // VCVTUDQ2PSZrmk 3230900983U, // VCVTUDQ2PSZrmkz 551838455U, // VCVTUDQ2PSZrr 1499895U, // VCVTUDQ2PSZrrb 3230835447U, // VCVTUDQ2PSZrrbk 3230802679U, // VCVTUDQ2PSZrrbkz 3230704375U, // VCVTUDQ2PSZrrk 3229672183U, // VCVTUDQ2PSZrrkz 264702U, // VCVTUQQ2PDZ128rm 627411454U, // VCVTUQQ2PDZ128rmb 628410878U, // VCVTUQQ2PDZ128rmbk 627149310U, // VCVTUQQ2PDZ128rmbkz 3230992894U, // VCVTUQQ2PDZ128rmk 3229862398U, // VCVTUQQ2PDZ128rmkz 551832062U, // VCVTUQQ2PDZ128rr 3230697982U, // VCVTUQQ2PDZ128rrk 3229665790U, // VCVTUQQ2PDZ128rrkz 552946174U, // VCVTUQQ2PDZ256rm 629508606U, // VCVTUQQ2PDZ256rmb 630508030U, // VCVTUQQ2PDZ256rmbk 629246462U, // VCVTUQQ2PDZ256rmbkz 3231025662U, // VCVTUQQ2PDZ256rmk 3230878206U, // VCVTUQQ2PDZ256rmkz 551832062U, // VCVTUQQ2PDZ256rr 3230697982U, // VCVTUQQ2PDZ256rrk 3229665790U, // VCVTUQQ2PDZ256rrkz 552438270U, // VCVTUQQ2PDZrm 631605758U, // VCVTUQQ2PDZrmb 632605182U, // VCVTUQQ2PDZrmbk 631343614U, // VCVTUQQ2PDZrmbkz 3231091198U, // VCVTUQQ2PDZrmk 3230894590U, // VCVTUQQ2PDZrmkz 551832062U, // VCVTUQQ2PDZrr 1493502U, // VCVTUQQ2PDZrrb 3230829054U, // VCVTUQQ2PDZrrbk 3230796286U, // VCVTUQQ2PDZrrbkz 3230697982U, // VCVTUQQ2PDZrrk 3229665790U, // VCVTUQQ2PDZrrkz 274508U, // VCVTUQQ2PSZ128rm 627417870U, // VCVTUQQ2PSZ128rmb 628417294U, // VCVTUQQ2PSZ128rmbk 627155726U, // VCVTUQQ2PSZ128rmbkz 3231002700U, // VCVTUQQ2PSZ128rmk 3229872204U, // VCVTUQQ2PSZ128rmkz 551838478U, // VCVTUQQ2PSZ128rr 3230704398U, // VCVTUQQ2PSZ128rrk 3229672206U, // VCVTUQQ2PSZ128rrkz 552956113U, // VCVTUQQ2PSZ256rm 629515022U, // VCVTUQQ2PSZ256rmb 630514446U, // VCVTUQQ2PSZ256rmbk 629252878U, // VCVTUQQ2PSZ256rmbkz 3231035601U, // VCVTUQQ2PSZ256rmk 3230888145U, // VCVTUQQ2PSZ256rmkz 551838478U, // VCVTUQQ2PSZ256rr 3230704398U, // VCVTUQQ2PSZ256rrk 3229672206U, // VCVTUQQ2PSZ256rrkz 552444686U, // VCVTUQQ2PSZrm 631612174U, // VCVTUQQ2PSZrmb 632611598U, // VCVTUQQ2PSZrmbk 631350030U, // VCVTUQQ2PSZrmbkz 3231097614U, // VCVTUQQ2PSZrmk 3230901006U, // VCVTUQQ2PSZrmkz 551838478U, // VCVTUQQ2PSZrr 1499918U, // VCVTUQQ2PSZrrb 3230835470U, // VCVTUQQ2PSZrrbk 3230802702U, // VCVTUQQ2PSZrrbkz 3230704398U, // VCVTUQQ2PSZrrk 3229672206U, // VCVTUQQ2PSZrrkz 283202614U, // VCVTUSI2SDZrm 283202614U, // VCVTUSI2SDZrm_Int 811652150U, // VCVTUSI2SDZrr 811652150U, // VCVTUSI2SDZrr_Int 283203318U, // VCVTUSI2SSZrm 283203318U, // VCVTUSI2SSZrm_Int 811652854U, // VCVTUSI2SSZrr 811652854U, // VCVTUSI2SSZrr_Int 155244278U, // VCVTUSI2SSZrrb_Int 283220803U, // VCVTUSI642SDZrm 283220803U, // VCVTUSI642SDZrm_Int 811653955U, // VCVTUSI642SDZrr 811653955U, // VCVTUSI642SDZrr_Int 155245379U, // VCVTUSI642SDZrrb_Int 283221770U, // VCVTUSI642SSZrm 283221770U, // VCVTUSI642SSZrm_Int 811654922U, // VCVTUSI642SSZrr 811654922U, // VCVTUSI642SSZrr_Int 155246346U, // VCVTUSI642SSZrrb_Int 325446245U, // VDBPSADBWZ128rmi 1983113829U, // VDBPSADBWZ128rmik 1179920997U, // VDBPSADBWZ128rmikz 1088825957U, // VDBPSADBWZ128rri 2163141221U, // VDBPSADBWZ128rrik 1357589093U, // VDBPSADBWZ128rrikz 375777893U, // VDBPSADBWZ256rmi 1989405285U, // VDBPSADBWZ256rmik 1186212453U, // VDBPSADBWZ256rmikz 1088825957U, // VDBPSADBWZ256rri 2163141221U, // VDBPSADBWZ256rrik 1357589093U, // VDBPSADBWZ256rrikz 382069349U, // VDBPSADBWZrmi 1995696741U, // VDBPSADBWZrmik 1192503909U, // VDBPSADBWZrmikz 1088825957U, // VDBPSADBWZrri 2163141221U, // VDBPSADBWZrrik 1357589093U, // VDBPSADBWZrrikz 812617022U, // VDIVPDYrm 811650366U, // VDIVPDYrr 811732286U, // VDIVPDZ128rm 358763838U, // VDIVPDZ128rmb 1433390398U, // VDIVPDZ128rmbk 1164971326U, // VDIVPDZ128rmbkz 86986046U, // VDIVPDZ128rmk 890178878U, // VDIVPDZ128rmkz 811650366U, // VDIVPDZ128rr 87051582U, // VDIVPDZ128rrk 890277182U, // VDIVPDZ128rrkz 812617022U, // VDIVPDZ256rm 360860990U, // VDIVPDZ256rmb 1435487550U, // VDIVPDZ256rmbk 1167068478U, // VDIVPDZ256rmbkz 87084350U, // VDIVPDZ256rmk 890309950U, // VDIVPDZ256rmkz 811650366U, // VDIVPDZ256rr 87051582U, // VDIVPDZ256rrk 890277182U, // VDIVPDZ256rrkz 812731710U, // VDIVPDZrm 362958142U, // VDIVPDZrmb 1437584702U, // VDIVPDZrmbk 1169165630U, // VDIVPDZrmbkz 87133502U, // VDIVPDZrmk 890359102U, // VDIVPDZrmkz 811650366U, // VDIVPDZrr 812780862U, // VDIVPDZrrb 87182654U, // VDIVPDZrrbk 890408254U, // VDIVPDZrrbkz 87051582U, // VDIVPDZrrk 890277182U, // VDIVPDZrrkz 811732286U, // VDIVPDrm 811650366U, // VDIVPDrr 812623519U, // VDIVPSYrm 811656863U, // VDIVPSYrr 811738783U, // VDIVPSZ128rm 360883871U, // VDIVPSZ128rmb 1435690655U, // VDIVPSZ128rmbk 1167271583U, // VDIVPSZ128rmbkz 86992543U, // VDIVPSZ128rmk 890185375U, // VDIVPSZ128rmkz 811656863U, // VDIVPSZ128rr 87058079U, // VDIVPSZ128rrk 890283679U, // VDIVPSZ128rrkz 812623519U, // VDIVPSZ256rm 362981023U, // VDIVPSZ256rmb 1437787807U, // VDIVPSZ256rmbk 1169368735U, // VDIVPSZ256rmbkz 87090847U, // VDIVPSZ256rmk 890316447U, // VDIVPSZ256rmkz 811656863U, // VDIVPSZ256rr 87058079U, // VDIVPSZ256rrk 890283679U, // VDIVPSZ256rrkz 812738207U, // VDIVPSZrm 365078175U, // VDIVPSZrmb 1439884959U, // VDIVPSZrmbk 1171465887U, // VDIVPSZrmbkz 87139999U, // VDIVPSZrmk 890365599U, // VDIVPSZrmkz 811656863U, // VDIVPSZrr 812787359U, // VDIVPSZrrb 87189151U, // VDIVPSZrrbk 890414751U, // VDIVPSZrrbkz 87058079U, // VDIVPSZrrk 890283679U, // VDIVPSZrrkz 811738783U, // VDIVPSrm 811656863U, // VDIVPSrr 283267069U, // VDIVSDZrm 283267069U, // VDIVSDZrm_Int 1357893629U, // VDIVSDZrm_Intk 1089474557U, // VDIVSDZrm_Intkz 811651069U, // VDIVSDZrr 811651069U, // VDIVSDZrr_Int 87052285U, // VDIVSDZrr_Intk 890277885U, // VDIVSDZrr_Intkz 812781565U, // VDIVSDZrrb_Int 87183357U, // VDIVSDZrrb_Intk 890408957U, // VDIVSDZrrb_Intkz 283267069U, // VDIVSDrm 283267069U, // VDIVSDrm_Int 811651069U, // VDIVSDrr 811651069U, // VDIVSDrr_Int 283289821U, // VDIVSSZrm 283289821U, // VDIVSSZrm_Int 1358096605U, // VDIVSSZrm_Intk 1089677533U, // VDIVSSZrm_Intkz 811657437U, // VDIVSSZrr 811657437U, // VDIVSSZrr_Int 87058653U, // VDIVSSZrr_Intk 890284253U, // VDIVSSZrr_Intkz 812787933U, // VDIVSSZrrb_Int 87189725U, // VDIVSSZrrb_Intk 890415325U, // VDIVSSZrrb_Intkz 283289821U, // VDIVSSrm 283289821U, // VDIVSSrm_Int 811657437U, // VDIVSSrr 811657437U, // VDIVSSrr_Int 300272728U, // VDPPDrmi 1088818264U, // VDPPDrri 375776657U, // VDPPSYrmi 1088824721U, // VDPPSYrri 300279185U, // VDPPSrmi 1088824721U, // VDPPSrri 221519U, // VERRm 24911U, // VERRr 224626U, // VERWm 28018U, // VERWr 1509843U, // VEXP2PDZm 631867859U, // VEXP2PDZmb 632293843U, // VEXP2PDZmbk 631392723U, // VEXP2PDZmbkz 3230779859U, // VEXP2PDZmk 3230747091U, // VEXP2PDZmkz 551832019U, // VEXP2PDZr 551843250U, // VEXP2PDZrb 3230709170U, // VEXP2PDZrbk 3229676978U, // VEXP2PDZrbkz 3230697939U, // VEXP2PDZrk 3229665747U, // VEXP2PDZrkz 1516259U, // VEXP2PSZm 633987811U, // VEXP2PSZmb 634594019U, // VEXP2PSZmbk 633512675U, // VEXP2PSZmbkz 3230786275U, // VEXP2PSZmk 3230753507U, // VEXP2PSZmkz 551838435U, // VEXP2PSZr 551843755U, // VEXP2PSZrb 3230709675U, // VEXP2PSZrbk 3229677483U, // VEXP2PSZrbkz 3230704355U, // VEXP2PSZrk 3229672163U, // VEXP2PSZrkz 658274U, // VEXPANDPDZ128rm 3230600034U, // VEXPANDPDZ128rmk 3229748066U, // VEXPANDPDZ128rmkz 551832418U, // VEXPANDPDZ128rr 3230698338U, // VEXPANDPDZ128rrk 3229666146U, // VEXPANDPDZ128rrkz 1346402U, // VEXPANDPDZ256rm 3230731106U, // VEXPANDPDZ256rmk 3230632802U, // VEXPANDPDZ256rmkz 551832418U, // VEXPANDPDZ256rr 3230698338U, // VEXPANDPDZ256rrk 3229666146U, // VEXPANDPDZ256rrkz 1510242U, // VEXPANDPDZrm 3230780258U, // VEXPANDPDZrmk 3230747490U, // VEXPANDPDZrmkz 551832418U, // VEXPANDPDZrr 3230698338U, // VEXPANDPDZrrk 3229666146U, // VEXPANDPDZrrkz 664694U, // VEXPANDPSZ128rm 3230606454U, // VEXPANDPSZ128rmk 3229754486U, // VEXPANDPSZ128rmkz 551838838U, // VEXPANDPSZ128rr 3230704758U, // VEXPANDPSZ128rrk 3229672566U, // VEXPANDPSZ128rrkz 1352822U, // VEXPANDPSZ256rm 3230737526U, // VEXPANDPSZ256rmk 3230639222U, // VEXPANDPSZ256rmkz 551838838U, // VEXPANDPSZ256rr 3230704758U, // VEXPANDPSZ256rrk 3229672566U, // VEXPANDPSZ256rrkz 1516662U, // VEXPANDPSZrm 3230786678U, // VEXPANDPSZrmk 3230753910U, // VEXPANDPSZrmkz 551838838U, // VEXPANDPSZrr 3230704758U, // VEXPANDPSZrrk 3229672566U, // VEXPANDPSZrrkz 1126466160U, // VEXTRACTF128mr 283427440U, // VEXTRACTF128rr 1126465941U, // VEXTRACTF32x4Z256mr 1227211157U, // VEXTRACTF32x4Z256mrk 283427221U, // VEXTRACTF32x4Z256rr 1357578645U, // VEXTRACTF32x4Z256rrk 1088815509U, // VEXTRACTF32x4Z256rrkz 1126465941U, // VEXTRACTF32x4Zmr 1227211157U, // VEXTRACTF32x4Zmrk 283427221U, // VEXTRACTF32x4Zrr 1357578645U, // VEXTRACTF32x4Zrrk 1088815509U, // VEXTRACTF32x4Zrrkz 1663337180U, // VEXTRACTF32x8Zmr 1764082396U, // VEXTRACTF32x8Zmrk 283427548U, // VEXTRACTF32x8Zrr 1357578972U, // VEXTRACTF32x8Zrrk 1088815836U, // VEXTRACTF32x8Zrrkz 1126465728U, // VEXTRACTF64x2Z256mr 1227210944U, // VEXTRACTF64x2Z256mrk 283427008U, // VEXTRACTF64x2Z256rr 1357578432U, // VEXTRACTF64x2Z256rrk 1088815296U, // VEXTRACTF64x2Z256rrkz 1126465728U, // VEXTRACTF64x2Zmr 1227210944U, // VEXTRACTF64x2Zmrk 283427008U, // VEXTRACTF64x2Zrr 1357578432U, // VEXTRACTF64x2Zrrk 1088815296U, // VEXTRACTF64x2Zrrkz 1663336957U, // VEXTRACTF64x4Zmr 1764082173U, // VEXTRACTF64x4Zmrk 283427325U, // VEXTRACTF64x4Zrr 1357578749U, // VEXTRACTF64x4Zrrk 1088815613U, // VEXTRACTF64x4Zrrkz 1931772583U, // VEXTRACTI128mr 283427495U, // VEXTRACTI128rr 1931772367U, // VEXTRACTI32x4Z256mr 2032517583U, // VEXTRACTI32x4Z256mrk 283427279U, // VEXTRACTI32x4Z256rr 1357578703U, // VEXTRACTI32x4Z256rrk 1088815567U, // VEXTRACTI32x4Z256rrkz 1931772367U, // VEXTRACTI32x4Zmr 2032517583U, // VEXTRACTI32x4Zmrk 283427279U, // VEXTRACTI32x4Zrr 1357578703U, // VEXTRACTI32x4Zrrk 1088815567U, // VEXTRACTI32x4Zrrkz 2200208138U, // VEXTRACTI32x8Zmr 2300953354U, // VEXTRACTI32x8Zmrk 283427594U, // VEXTRACTI32x8Zrr 1357579018U, // VEXTRACTI32x8Zrrk 1088815882U, // VEXTRACTI32x8Zrrkz 1931772154U, // VEXTRACTI64x2Z256mr 2032517370U, // VEXTRACTI64x2Z256mrk 283427066U, // VEXTRACTI64x2Z256rr 1357578490U, // VEXTRACTI64x2Z256rrk 1088815354U, // VEXTRACTI64x2Z256rrkz 1931772154U, // VEXTRACTI64x2Zmr 2032517370U, // VEXTRACTI64x2Zmrk 283427066U, // VEXTRACTI64x2Zrr 1357578490U, // VEXTRACTI64x2Zrrk 1088815354U, // VEXTRACTI64x2Zrrkz 2200207915U, // VEXTRACTI64x4Zmr 2300953131U, // VEXTRACTI64x4Zmrk 283427371U, // VEXTRACTI64x4Zrr 1357578795U, // VEXTRACTI64x4Zrrk 1088815659U, // VEXTRACTI64x4Zrrkz 3810829866U, // VEXTRACTPSZmr 283436586U, // VEXTRACTPSZrr 3810829866U, // VEXTRACTPSmr 283436586U, // VEXTRACTPSrr 3079932977U, // VFIXUPIMMPDZ128rmbi 3111373873U, // VFIXUPIMMPDZ128rmbik 3111373873U, // VFIXUPIMMPDZ128rmbikz 1202981937U, // VFIXUPIMMPDZ128rmi 2039729201U, // VFIXUPIMMPDZ128rmik 2576600113U, // VFIXUPIMMPDZ128rmikz 1357581361U, // VFIXUPIMMPDZ128rri 2163133489U, // VFIXUPIMMPDZ128rrik 2163133489U, // VFIXUPIMMPDZ128rrikz 1737755697U, // VFIXUPIMMPDZ256rmbi 1769196593U, // VFIXUPIMMPDZ256rmbik 1769196593U, // VFIXUPIMMPDZ256rmbikz 1205079089U, // VFIXUPIMMPDZ256rmi 2041826353U, // VFIXUPIMMPDZ256rmik 2578697265U, // VFIXUPIMMPDZ256rmikz 1357581361U, // VFIXUPIMMPDZ256rri 2163133489U, // VFIXUPIMMPDZ256rrik 2163133489U, // VFIXUPIMMPDZ256rrikz 2543062065U, // VFIXUPIMMPDZrmbi 2574502961U, // VFIXUPIMMPDZrmbik 2574502961U, // VFIXUPIMMPDZrmbikz 1209273393U, // VFIXUPIMMPDZrmi 2043923505U, // VFIXUPIMMPDZrmik 2580794417U, // VFIXUPIMMPDZrmikz 1357581361U, // VFIXUPIMMPDZrri 1481313329U, // VFIXUPIMMPDZrrib 2286865457U, // VFIXUPIMMPDZrribk 2286865457U, // VFIXUPIMMPDZrribkz 2163133489U, // VFIXUPIMMPDZrrik 2163133489U, // VFIXUPIMMPDZrrikz 1752442193U, // VFIXUPIMMPSZ128rmbi 1777591633U, // VFIXUPIMMPSZ128rmbik 1777591633U, // VFIXUPIMMPSZ128rmbikz 1202988369U, // VFIXUPIMMPSZ128rmi 2039735633U, // VFIXUPIMMPSZ128rmik 2576606545U, // VFIXUPIMMPSZ128rmikz 1357587793U, // VFIXUPIMMPSZ128rri 2163139921U, // VFIXUPIMMPSZ128rrik 2163139921U, // VFIXUPIMMPSZ128rrikz 2557748561U, // VFIXUPIMMPSZ256rmbi 2582898001U, // VFIXUPIMMPSZ256rmbik 2582898001U, // VFIXUPIMMPSZ256rmbikz 1205085521U, // VFIXUPIMMPSZ256rmi 2041832785U, // VFIXUPIMMPSZ256rmik 2578703697U, // VFIXUPIMMPSZ256rmikz 1357587793U, // VFIXUPIMMPSZ256rri 2163139921U, // VFIXUPIMMPSZ256rrik 2163139921U, // VFIXUPIMMPSZ256rrikz 2826184017U, // VFIXUPIMMPSZrmbi 2851333457U, // VFIXUPIMMPSZrmbik 2851333457U, // VFIXUPIMMPSZrmbikz 1209279825U, // VFIXUPIMMPSZrmi 2043929937U, // VFIXUPIMMPSZrmik 2580800849U, // VFIXUPIMMPSZrmikz 1357587793U, // VFIXUPIMMPSZrri 1481319761U, // VFIXUPIMMPSZrrib 2286871889U, // VFIXUPIMMPSZrribk 2286871889U, // VFIXUPIMMPSZrribkz 2163139921U, // VFIXUPIMMPSZrrik 2163139921U, // VFIXUPIMMPSZrrikz 932450137U, // VFIXUPIMMSDZrmi 963891033U, // VFIXUPIMMSDZrmik 963891033U, // VFIXUPIMMSDZrmikz 1357582169U, // VFIXUPIMMSDZrri 1481314137U, // VFIXUPIMMSDZrrib 2286866265U, // VFIXUPIMMSDZrribk 2286866265U, // VFIXUPIMMSDZrribkz 2163134297U, // VFIXUPIMMSDZrrik 2163134297U, // VFIXUPIMMSDZrrikz 947136619U, // VFIXUPIMMSSZrmi 972286059U, // VFIXUPIMMSSZrmik 972286059U, // VFIXUPIMMSSZrmikz 1357588587U, // VFIXUPIMMSSZrri 1481320555U, // VFIXUPIMMSSZrrib 2286872683U, // VFIXUPIMMSSZrribk 2286872683U, // VFIXUPIMMSSZrribkz 2163140715U, // VFIXUPIMMSSZrrik 2163140715U, // VFIXUPIMMSSZrrikz 890309015U, // VFMADD132PDYm 890276247U, // VFMADD132PDYr 890177943U, // VFMADD132PDZ128m 1164970391U, // VFMADD132PDZ128mb 1433389463U, // VFMADD132PDZ128mbk 1433389463U, // VFMADD132PDZ128mbkz 86985111U, // VFMADD132PDZ128mk 89082263U, // VFMADD132PDZ128mkz 890276247U, // VFMADD132PDZ128r 87050647U, // VFMADD132PDZ128rk 89147799U, // VFMADD132PDZ128rkz 890309015U, // VFMADD132PDZ256m 1167067543U, // VFMADD132PDZ256mb 1435486615U, // VFMADD132PDZ256mbk 1435486615U, // VFMADD132PDZ256mbkz 87083415U, // VFMADD132PDZ256mk 89180567U, // VFMADD132PDZ256mkz 890276247U, // VFMADD132PDZ256r 87050647U, // VFMADD132PDZ256rk 89147799U, // VFMADD132PDZ256rkz 890358167U, // VFMADD132PDZm 1169164695U, // VFMADD132PDZmb 1437583767U, // VFMADD132PDZmbk 1437583767U, // VFMADD132PDZmbkz 87132567U, // VFMADD132PDZmk 89229719U, // VFMADD132PDZmkz 890276247U, // VFMADD132PDZr 890407319U, // VFMADD132PDZrb 87181719U, // VFMADD132PDZrbk 89278871U, // VFMADD132PDZrbkz 87050647U, // VFMADD132PDZrk 89147799U, // VFMADD132PDZrkz 890177943U, // VFMADD132PDm 890276247U, // VFMADD132PDr 890315409U, // VFMADD132PSYm 890282641U, // VFMADD132PSYr 890184337U, // VFMADD132PSZ128m 1167270545U, // VFMADD132PSZ128mb 1435689617U, // VFMADD132PSZ128mbk 1435689617U, // VFMADD132PSZ128mbkz 86991505U, // VFMADD132PSZ128mk 89088657U, // VFMADD132PSZ128mkz 890282641U, // VFMADD132PSZ128r 87057041U, // VFMADD132PSZ128rk 89154193U, // VFMADD132PSZ128rkz 890315409U, // VFMADD132PSZ256m 1169367697U, // VFMADD132PSZ256mb 1437786769U, // VFMADD132PSZ256mbk 1437786769U, // VFMADD132PSZ256mbkz 87089809U, // VFMADD132PSZ256mk 89186961U, // VFMADD132PSZ256mkz 890282641U, // VFMADD132PSZ256r 87057041U, // VFMADD132PSZ256rk 89154193U, // VFMADD132PSZ256rkz 890364561U, // VFMADD132PSZm 1171464849U, // VFMADD132PSZmb 1439883921U, // VFMADD132PSZmbk 1439883921U, // VFMADD132PSZmbkz 87138961U, // VFMADD132PSZmk 89236113U, // VFMADD132PSZmkz 890282641U, // VFMADD132PSZr 890413713U, // VFMADD132PSZrb 87188113U, // VFMADD132PSZrbk 89285265U, // VFMADD132PSZrbkz 87057041U, // VFMADD132PSZrk 89154193U, // VFMADD132PSZrkz 890184337U, // VFMADD132PSm 890282641U, // VFMADD132PSr 1089474109U, // VFMADD132SDZm 1089474109U, // VFMADD132SDZm_Int 1357893181U, // VFMADD132SDZm_Intk 1357893181U, // VFMADD132SDZm_Intkz 890277437U, // VFMADD132SDZr 890277437U, // VFMADD132SDZr_Int 87051837U, // VFMADD132SDZr_Intk 89148989U, // VFMADD132SDZr_Intkz 890277437U, // VFMADD132SDZrb 890408509U, // VFMADD132SDZrb_Int 87182909U, // VFMADD132SDZrb_Intk 89280061U, // VFMADD132SDZrb_Intkz 1089474109U, // VFMADD132SDm 1089474109U, // VFMADD132SDm_Int 890277437U, // VFMADD132SDr 890277437U, // VFMADD132SDr_Int 1089677120U, // VFMADD132SSZm 1089677120U, // VFMADD132SSZm_Int 1358096192U, // VFMADD132SSZm_Intk 1358096192U, // VFMADD132SSZm_Intkz 890283840U, // VFMADD132SSZr 890283840U, // VFMADD132SSZr_Int 87058240U, // VFMADD132SSZr_Intk 89155392U, // VFMADD132SSZr_Intkz 890283840U, // VFMADD132SSZrb 890414912U, // VFMADD132SSZrb_Int 87189312U, // VFMADD132SSZrb_Intk 89286464U, // VFMADD132SSZrb_Intkz 1089677120U, // VFMADD132SSm 1089677120U, // VFMADD132SSm_Int 890283840U, // VFMADD132SSr 890283840U, // VFMADD132SSr_Int 890309211U, // VFMADD213PDYm 890276443U, // VFMADD213PDYr 890178139U, // VFMADD213PDZ128m 1164970587U, // VFMADD213PDZ128mb 1433389659U, // VFMADD213PDZ128mbk 1433389659U, // VFMADD213PDZ128mbkz 86985307U, // VFMADD213PDZ128mk 89082459U, // VFMADD213PDZ128mkz 890276443U, // VFMADD213PDZ128r 87050843U, // VFMADD213PDZ128rk 89147995U, // VFMADD213PDZ128rkz 890309211U, // VFMADD213PDZ256m 1167067739U, // VFMADD213PDZ256mb 1435486811U, // VFMADD213PDZ256mbk 1435486811U, // VFMADD213PDZ256mbkz 87083611U, // VFMADD213PDZ256mk 89180763U, // VFMADD213PDZ256mkz 890276443U, // VFMADD213PDZ256r 87050843U, // VFMADD213PDZ256rk 89147995U, // VFMADD213PDZ256rkz 890358363U, // VFMADD213PDZm 1169164891U, // VFMADD213PDZmb 1437583963U, // VFMADD213PDZmbk 1437583963U, // VFMADD213PDZmbkz 87132763U, // VFMADD213PDZmk 89229915U, // VFMADD213PDZmkz 890276443U, // VFMADD213PDZr 890407515U, // VFMADD213PDZrb 87181915U, // VFMADD213PDZrbk 89279067U, // VFMADD213PDZrbkz 87050843U, // VFMADD213PDZrk 89147995U, // VFMADD213PDZrkz 890178139U, // VFMADD213PDm 890276443U, // VFMADD213PDr 890315616U, // VFMADD213PSYm 890282848U, // VFMADD213PSYr 890184544U, // VFMADD213PSZ128m 1167270752U, // VFMADD213PSZ128mb 1435689824U, // VFMADD213PSZ128mbk 1435689824U, // VFMADD213PSZ128mbkz 86991712U, // VFMADD213PSZ128mk 89088864U, // VFMADD213PSZ128mkz 890282848U, // VFMADD213PSZ128r 87057248U, // VFMADD213PSZ128rk 89154400U, // VFMADD213PSZ128rkz 890315616U, // VFMADD213PSZ256m 1169367904U, // VFMADD213PSZ256mb 1437786976U, // VFMADD213PSZ256mbk 1437786976U, // VFMADD213PSZ256mbkz 87090016U, // VFMADD213PSZ256mk 89187168U, // VFMADD213PSZ256mkz 890282848U, // VFMADD213PSZ256r 87057248U, // VFMADD213PSZ256rk 89154400U, // VFMADD213PSZ256rkz 890364768U, // VFMADD213PSZm 1171465056U, // VFMADD213PSZmb 1439884128U, // VFMADD213PSZmbk 1439884128U, // VFMADD213PSZmbkz 87139168U, // VFMADD213PSZmk 89236320U, // VFMADD213PSZmkz 890282848U, // VFMADD213PSZr 890413920U, // VFMADD213PSZrb 87188320U, // VFMADD213PSZrbk 89285472U, // VFMADD213PSZrbkz 87057248U, // VFMADD213PSZrk 89154400U, // VFMADD213PSZrkz 890184544U, // VFMADD213PSm 890282848U, // VFMADD213PSr 1089474174U, // VFMADD213SDZm 1089474174U, // VFMADD213SDZm_Int 1357893246U, // VFMADD213SDZm_Intk 1357893246U, // VFMADD213SDZm_Intkz 890277502U, // VFMADD213SDZr 890277502U, // VFMADD213SDZr_Int 87051902U, // VFMADD213SDZr_Intk 89149054U, // VFMADD213SDZr_Intkz 890277502U, // VFMADD213SDZrb 890408574U, // VFMADD213SDZrb_Int 87182974U, // VFMADD213SDZrb_Intk 89280126U, // VFMADD213SDZrb_Intkz 1089474174U, // VFMADD213SDm 1089474174U, // VFMADD213SDm_Int 890277502U, // VFMADD213SDr 890277502U, // VFMADD213SDr_Int 1089677185U, // VFMADD213SSZm 1089677185U, // VFMADD213SSZm_Int 1358096257U, // VFMADD213SSZm_Intk 1358096257U, // VFMADD213SSZm_Intkz 890283905U, // VFMADD213SSZr 890283905U, // VFMADD213SSZr_Int 87058305U, // VFMADD213SSZr_Intk 89155457U, // VFMADD213SSZr_Intkz 890283905U, // VFMADD213SSZrb 890414977U, // VFMADD213SSZrb_Int 87189377U, // VFMADD213SSZrb_Intk 89286529U, // VFMADD213SSZrb_Intkz 1089677185U, // VFMADD213SSm 1089677185U, // VFMADD213SSm_Int 890283905U, // VFMADD213SSr 890283905U, // VFMADD213SSr_Int 890308929U, // VFMADD231PDYm 890276161U, // VFMADD231PDYr 890177857U, // VFMADD231PDZ128m 1164970305U, // VFMADD231PDZ128mb 1433389377U, // VFMADD231PDZ128mbk 1433389377U, // VFMADD231PDZ128mbkz 86985025U, // VFMADD231PDZ128mk 89082177U, // VFMADD231PDZ128mkz 890276161U, // VFMADD231PDZ128r 87050561U, // VFMADD231PDZ128rk 89147713U, // VFMADD231PDZ128rkz 890308929U, // VFMADD231PDZ256m 1167067457U, // VFMADD231PDZ256mb 1435486529U, // VFMADD231PDZ256mbk 1435486529U, // VFMADD231PDZ256mbkz 87083329U, // VFMADD231PDZ256mk 89180481U, // VFMADD231PDZ256mkz 890276161U, // VFMADD231PDZ256r 87050561U, // VFMADD231PDZ256rk 89147713U, // VFMADD231PDZ256rkz 890358081U, // VFMADD231PDZm 1169164609U, // VFMADD231PDZmb 1437583681U, // VFMADD231PDZmbk 1437583681U, // VFMADD231PDZmbkz 87132481U, // VFMADD231PDZmk 89229633U, // VFMADD231PDZmkz 890276161U, // VFMADD231PDZr 890407233U, // VFMADD231PDZrb 87181633U, // VFMADD231PDZrbk 89278785U, // VFMADD231PDZrbkz 87050561U, // VFMADD231PDZrk 89147713U, // VFMADD231PDZrkz 890177857U, // VFMADD231PDm 890276161U, // VFMADD231PDr 890315323U, // VFMADD231PSYm 890282555U, // VFMADD231PSYr 890184251U, // VFMADD231PSZ128m 1167270459U, // VFMADD231PSZ128mb 1435689531U, // VFMADD231PSZ128mbk 1435689531U, // VFMADD231PSZ128mbkz 86991419U, // VFMADD231PSZ128mk 89088571U, // VFMADD231PSZ128mkz 890282555U, // VFMADD231PSZ128r 87056955U, // VFMADD231PSZ128rk 89154107U, // VFMADD231PSZ128rkz 890315323U, // VFMADD231PSZ256m 1169367611U, // VFMADD231PSZ256mb 1437786683U, // VFMADD231PSZ256mbk 1437786683U, // VFMADD231PSZ256mbkz 87089723U, // VFMADD231PSZ256mk 89186875U, // VFMADD231PSZ256mkz 890282555U, // VFMADD231PSZ256r 87056955U, // VFMADD231PSZ256rk 89154107U, // VFMADD231PSZ256rkz 890364475U, // VFMADD231PSZm 1171464763U, // VFMADD231PSZmb 1439883835U, // VFMADD231PSZmbk 1439883835U, // VFMADD231PSZmbkz 87138875U, // VFMADD231PSZmk 89236027U, // VFMADD231PSZmkz 890282555U, // VFMADD231PSZr 890413627U, // VFMADD231PSZrb 87188027U, // VFMADD231PSZrbk 89285179U, // VFMADD231PSZrbkz 87056955U, // VFMADD231PSZrk 89154107U, // VFMADD231PSZrkz 890184251U, // VFMADD231PSm 890282555U, // VFMADD231PSr 1089474055U, // VFMADD231SDZm 1089474055U, // VFMADD231SDZm_Int 1357893127U, // VFMADD231SDZm_Intk 1357893127U, // VFMADD231SDZm_Intkz 890277383U, // VFMADD231SDZr 890277383U, // VFMADD231SDZr_Int 87051783U, // VFMADD231SDZr_Intk 89148935U, // VFMADD231SDZr_Intkz 890277383U, // VFMADD231SDZrb 890408455U, // VFMADD231SDZrb_Int 87182855U, // VFMADD231SDZrb_Intk 89280007U, // VFMADD231SDZrb_Intkz 1089474055U, // VFMADD231SDm 1089474055U, // VFMADD231SDm_Int 890277383U, // VFMADD231SDr 890277383U, // VFMADD231SDr_Int 1089677066U, // VFMADD231SSZm 1089677066U, // VFMADD231SSZm_Int 1358096138U, // VFMADD231SSZm_Intk 1358096138U, // VFMADD231SSZm_Intkz 890283786U, // VFMADD231SSZr 890283786U, // VFMADD231SSZr_Int 87058186U, // VFMADD231SSZr_Intk 89155338U, // VFMADD231SSZr_Intkz 890283786U, // VFMADD231SSZrb 890414858U, // VFMADD231SSZrb_Int 87189258U, // VFMADD231SSZrb_Intk 89286410U, // VFMADD231SSZrb_Intkz 1089677066U, // VFMADD231SSm 1089677066U, // VFMADD231SSm_Int 890283786U, // VFMADD231SSr 890283786U, // VFMADD231SSr_Int 393497413U, // VFMADDPD4Ymr 890309445U, // VFMADDPD4Yrm 890276677U, // VFMADDPD4Yrr 890276677U, // VFMADDPD4Yrr_REV 301222725U, // VFMADDPD4mr 890178373U, // VFMADDPD4rm 890276677U, // VFMADDPD4rr 890276677U, // VFMADDPD4rr_REV 393503821U, // VFMADDPS4Ymr 890315853U, // VFMADDPS4Yrm 890283085U, // VFMADDPS4Yrr 890283085U, // VFMADDPS4Yrr_REV 301229133U, // VFMADDPS4mr 890184781U, // VFMADDPS4rm 890283085U, // VFMADDPS4rr 890283085U, // VFMADDPS4rr_REV 852774634U, // VFMADDSD4mr 852774634U, // VFMADDSD4mr_Int 1089474282U, // VFMADDSD4rm 1089474282U, // VFMADDSD4rm_Int 890277610U, // VFMADDSD4rr 890277610U, // VFMADDSD4rr_Int 890277610U, // VFMADDSD4rr_Int_REV 890277610U, // VFMADDSD4rr_REV 856975344U, // VFMADDSS4mr 856975344U, // VFMADDSS4mr_Int 1089677296U, // VFMADDSS4rm 1089677296U, // VFMADDSS4rm_Int 890284016U, // VFMADDSS4rr 890284016U, // VFMADDSS4rr_Int 890284016U, // VFMADDSS4rr_Int_REV 890284016U, // VFMADDSS4rr_REV 890308956U, // VFMADDSUB132PDYm 890276188U, // VFMADDSUB132PDYr 890177884U, // VFMADDSUB132PDZ128m 1164970332U, // VFMADDSUB132PDZ128mb 1433389404U, // VFMADDSUB132PDZ128mbk 1433389404U, // VFMADDSUB132PDZ128mbkz 86985052U, // VFMADDSUB132PDZ128mk 89082204U, // VFMADDSUB132PDZ128mkz 890276188U, // VFMADDSUB132PDZ128r 87050588U, // VFMADDSUB132PDZ128rk 89147740U, // VFMADDSUB132PDZ128rkz 890308956U, // VFMADDSUB132PDZ256m 1167067484U, // VFMADDSUB132PDZ256mb 1435486556U, // VFMADDSUB132PDZ256mbk 1435486556U, // VFMADDSUB132PDZ256mbkz 87083356U, // VFMADDSUB132PDZ256mk 89180508U, // VFMADDSUB132PDZ256mkz 890276188U, // VFMADDSUB132PDZ256r 87050588U, // VFMADDSUB132PDZ256rk 89147740U, // VFMADDSUB132PDZ256rkz 890358108U, // VFMADDSUB132PDZm 1169164636U, // VFMADDSUB132PDZmb 1437583708U, // VFMADDSUB132PDZmbk 1437583708U, // VFMADDSUB132PDZmbkz 87132508U, // VFMADDSUB132PDZmk 89229660U, // VFMADDSUB132PDZmkz 890276188U, // VFMADDSUB132PDZr 890407260U, // VFMADDSUB132PDZrb 87181660U, // VFMADDSUB132PDZrbk 89278812U, // VFMADDSUB132PDZrbkz 87050588U, // VFMADDSUB132PDZrk 89147740U, // VFMADDSUB132PDZrkz 890177884U, // VFMADDSUB132PDm 890276188U, // VFMADDSUB132PDr 890315350U, // VFMADDSUB132PSYm 890282582U, // VFMADDSUB132PSYr 890184278U, // VFMADDSUB132PSZ128m 1167270486U, // VFMADDSUB132PSZ128mb 1435689558U, // VFMADDSUB132PSZ128mbk 1435689558U, // VFMADDSUB132PSZ128mbkz 86991446U, // VFMADDSUB132PSZ128mk 89088598U, // VFMADDSUB132PSZ128mkz 890282582U, // VFMADDSUB132PSZ128r 87056982U, // VFMADDSUB132PSZ128rk 89154134U, // VFMADDSUB132PSZ128rkz 890315350U, // VFMADDSUB132PSZ256m 1169367638U, // VFMADDSUB132PSZ256mb 1437786710U, // VFMADDSUB132PSZ256mbk 1437786710U, // VFMADDSUB132PSZ256mbkz 87089750U, // VFMADDSUB132PSZ256mk 89186902U, // VFMADDSUB132PSZ256mkz 890282582U, // VFMADDSUB132PSZ256r 87056982U, // VFMADDSUB132PSZ256rk 89154134U, // VFMADDSUB132PSZ256rkz 890364502U, // VFMADDSUB132PSZm 1171464790U, // VFMADDSUB132PSZmb 1439883862U, // VFMADDSUB132PSZmbk 1439883862U, // VFMADDSUB132PSZmbkz 87138902U, // VFMADDSUB132PSZmk 89236054U, // VFMADDSUB132PSZmkz 890282582U, // VFMADDSUB132PSZr 890413654U, // VFMADDSUB132PSZrb 87188054U, // VFMADDSUB132PSZrbk 89285206U, // VFMADDSUB132PSZrbkz 87056982U, // VFMADDSUB132PSZrk 89154134U, // VFMADDSUB132PSZrkz 890184278U, // VFMADDSUB132PSm 890282582U, // VFMADDSUB132PSr 890309152U, // VFMADDSUB213PDYm 890276384U, // VFMADDSUB213PDYr 890178080U, // VFMADDSUB213PDZ128m 1164970528U, // VFMADDSUB213PDZ128mb 1433389600U, // VFMADDSUB213PDZ128mbk 1433389600U, // VFMADDSUB213PDZ128mbkz 86985248U, // VFMADDSUB213PDZ128mk 89082400U, // VFMADDSUB213PDZ128mkz 890276384U, // VFMADDSUB213PDZ128r 87050784U, // VFMADDSUB213PDZ128rk 89147936U, // VFMADDSUB213PDZ128rkz 890309152U, // VFMADDSUB213PDZ256m 1167067680U, // VFMADDSUB213PDZ256mb 1435486752U, // VFMADDSUB213PDZ256mbk 1435486752U, // VFMADDSUB213PDZ256mbkz 87083552U, // VFMADDSUB213PDZ256mk 89180704U, // VFMADDSUB213PDZ256mkz 890276384U, // VFMADDSUB213PDZ256r 87050784U, // VFMADDSUB213PDZ256rk 89147936U, // VFMADDSUB213PDZ256rkz 890358304U, // VFMADDSUB213PDZm 1169164832U, // VFMADDSUB213PDZmb 1437583904U, // VFMADDSUB213PDZmbk 1437583904U, // VFMADDSUB213PDZmbkz 87132704U, // VFMADDSUB213PDZmk 89229856U, // VFMADDSUB213PDZmkz 890276384U, // VFMADDSUB213PDZr 890407456U, // VFMADDSUB213PDZrb 87181856U, // VFMADDSUB213PDZrbk 89279008U, // VFMADDSUB213PDZrbkz 87050784U, // VFMADDSUB213PDZrk 89147936U, // VFMADDSUB213PDZrkz 890178080U, // VFMADDSUB213PDm 890276384U, // VFMADDSUB213PDr 890315557U, // VFMADDSUB213PSYm 890282789U, // VFMADDSUB213PSYr 890184485U, // VFMADDSUB213PSZ128m 1167270693U, // VFMADDSUB213PSZ128mb 1435689765U, // VFMADDSUB213PSZ128mbk 1435689765U, // VFMADDSUB213PSZ128mbkz 86991653U, // VFMADDSUB213PSZ128mk 89088805U, // VFMADDSUB213PSZ128mkz 890282789U, // VFMADDSUB213PSZ128r 87057189U, // VFMADDSUB213PSZ128rk 89154341U, // VFMADDSUB213PSZ128rkz 890315557U, // VFMADDSUB213PSZ256m 1169367845U, // VFMADDSUB213PSZ256mb 1437786917U, // VFMADDSUB213PSZ256mbk 1437786917U, // VFMADDSUB213PSZ256mbkz 87089957U, // VFMADDSUB213PSZ256mk 89187109U, // VFMADDSUB213PSZ256mkz 890282789U, // VFMADDSUB213PSZ256r 87057189U, // VFMADDSUB213PSZ256rk 89154341U, // VFMADDSUB213PSZ256rkz 890364709U, // VFMADDSUB213PSZm 1171464997U, // VFMADDSUB213PSZmb 1439884069U, // VFMADDSUB213PSZmbk 1439884069U, // VFMADDSUB213PSZmbkz 87139109U, // VFMADDSUB213PSZmk 89236261U, // VFMADDSUB213PSZmkz 890282789U, // VFMADDSUB213PSZr 890413861U, // VFMADDSUB213PSZrb 87188261U, // VFMADDSUB213PSZrbk 89285413U, // VFMADDSUB213PSZrbkz 87057189U, // VFMADDSUB213PSZrk 89154341U, // VFMADDSUB213PSZrkz 890184485U, // VFMADDSUB213PSm 890282789U, // VFMADDSUB213PSr 890308870U, // VFMADDSUB231PDYm 890276102U, // VFMADDSUB231PDYr 890177798U, // VFMADDSUB231PDZ128m 1164970246U, // VFMADDSUB231PDZ128mb 1433389318U, // VFMADDSUB231PDZ128mbk 1433389318U, // VFMADDSUB231PDZ128mbkz 86984966U, // VFMADDSUB231PDZ128mk 89082118U, // VFMADDSUB231PDZ128mkz 890276102U, // VFMADDSUB231PDZ128r 87050502U, // VFMADDSUB231PDZ128rk 89147654U, // VFMADDSUB231PDZ128rkz 890308870U, // VFMADDSUB231PDZ256m 1167067398U, // VFMADDSUB231PDZ256mb 1435486470U, // VFMADDSUB231PDZ256mbk 1435486470U, // VFMADDSUB231PDZ256mbkz 87083270U, // VFMADDSUB231PDZ256mk 89180422U, // VFMADDSUB231PDZ256mkz 890276102U, // VFMADDSUB231PDZ256r 87050502U, // VFMADDSUB231PDZ256rk 89147654U, // VFMADDSUB231PDZ256rkz 890358022U, // VFMADDSUB231PDZm 1169164550U, // VFMADDSUB231PDZmb 1437583622U, // VFMADDSUB231PDZmbk 1437583622U, // VFMADDSUB231PDZmbkz 87132422U, // VFMADDSUB231PDZmk 89229574U, // VFMADDSUB231PDZmkz 890276102U, // VFMADDSUB231PDZr 890407174U, // VFMADDSUB231PDZrb 87181574U, // VFMADDSUB231PDZrbk 89278726U, // VFMADDSUB231PDZrbkz 87050502U, // VFMADDSUB231PDZrk 89147654U, // VFMADDSUB231PDZrkz 890177798U, // VFMADDSUB231PDm 890276102U, // VFMADDSUB231PDr 890315264U, // VFMADDSUB231PSYm 890282496U, // VFMADDSUB231PSYr 890184192U, // VFMADDSUB231PSZ128m 1167270400U, // VFMADDSUB231PSZ128mb 1435689472U, // VFMADDSUB231PSZ128mbk 1435689472U, // VFMADDSUB231PSZ128mbkz 86991360U, // VFMADDSUB231PSZ128mk 89088512U, // VFMADDSUB231PSZ128mkz 890282496U, // VFMADDSUB231PSZ128r 87056896U, // VFMADDSUB231PSZ128rk 89154048U, // VFMADDSUB231PSZ128rkz 890315264U, // VFMADDSUB231PSZ256m 1169367552U, // VFMADDSUB231PSZ256mb 1437786624U, // VFMADDSUB231PSZ256mbk 1437786624U, // VFMADDSUB231PSZ256mbkz 87089664U, // VFMADDSUB231PSZ256mk 89186816U, // VFMADDSUB231PSZ256mkz 890282496U, // VFMADDSUB231PSZ256r 87056896U, // VFMADDSUB231PSZ256rk 89154048U, // VFMADDSUB231PSZ256rkz 890364416U, // VFMADDSUB231PSZm 1171464704U, // VFMADDSUB231PSZmb 1439883776U, // VFMADDSUB231PSZmbk 1439883776U, // VFMADDSUB231PSZmbkz 87138816U, // VFMADDSUB231PSZmk 89235968U, // VFMADDSUB231PSZmkz 890282496U, // VFMADDSUB231PSZr 890413568U, // VFMADDSUB231PSZrb 87187968U, // VFMADDSUB231PSZrbk 89285120U, // VFMADDSUB231PSZrbkz 87056896U, // VFMADDSUB231PSZrk 89154048U, // VFMADDSUB231PSZrkz 890184192U, // VFMADDSUB231PSm 890282496U, // VFMADDSUB231PSr 393497267U, // VFMADDSUBPD4Ymr 890309299U, // VFMADDSUBPD4Yrm 890276531U, // VFMADDSUBPD4Yrr 890276531U, // VFMADDSUBPD4Yrr_REV 301222579U, // VFMADDSUBPD4mr 890178227U, // VFMADDSUBPD4rm 890276531U, // VFMADDSUBPD4rr 890276531U, // VFMADDSUBPD4rr_REV 393503664U, // VFMADDSUBPS4Ymr 890315696U, // VFMADDSUBPS4Yrm 890282928U, // VFMADDSUBPS4Yrr 890282928U, // VFMADDSUBPS4Yrr_REV 301228976U, // VFMADDSUBPS4mr 890184624U, // VFMADDSUBPS4rm 890282928U, // VFMADDSUBPS4rr 890282928U, // VFMADDSUBPS4rr_REV 890308972U, // VFMSUB132PDYm 890276204U, // VFMSUB132PDYr 890177900U, // VFMSUB132PDZ128m 1164970348U, // VFMSUB132PDZ128mb 1433389420U, // VFMSUB132PDZ128mbk 1433389420U, // VFMSUB132PDZ128mbkz 86985068U, // VFMSUB132PDZ128mk 89082220U, // VFMSUB132PDZ128mkz 890276204U, // VFMSUB132PDZ128r 87050604U, // VFMSUB132PDZ128rk 89147756U, // VFMSUB132PDZ128rkz 890308972U, // VFMSUB132PDZ256m 1167067500U, // VFMSUB132PDZ256mb 1435486572U, // VFMSUB132PDZ256mbk 1435486572U, // VFMSUB132PDZ256mbkz 87083372U, // VFMSUB132PDZ256mk 89180524U, // VFMSUB132PDZ256mkz 890276204U, // VFMSUB132PDZ256r 87050604U, // VFMSUB132PDZ256rk 89147756U, // VFMSUB132PDZ256rkz 890358124U, // VFMSUB132PDZm 1169164652U, // VFMSUB132PDZmb 1437583724U, // VFMSUB132PDZmbk 1437583724U, // VFMSUB132PDZmbkz 87132524U, // VFMSUB132PDZmk 89229676U, // VFMSUB132PDZmkz 890276204U, // VFMSUB132PDZr 890407276U, // VFMSUB132PDZrb 87181676U, // VFMSUB132PDZrbk 89278828U, // VFMSUB132PDZrbkz 87050604U, // VFMSUB132PDZrk 89147756U, // VFMSUB132PDZrkz 890177900U, // VFMSUB132PDm 890276204U, // VFMSUB132PDr 890315366U, // VFMSUB132PSYm 890282598U, // VFMSUB132PSYr 890184294U, // VFMSUB132PSZ128m 1167270502U, // VFMSUB132PSZ128mb 1435689574U, // VFMSUB132PSZ128mbk 1435689574U, // VFMSUB132PSZ128mbkz 86991462U, // VFMSUB132PSZ128mk 89088614U, // VFMSUB132PSZ128mkz 890282598U, // VFMSUB132PSZ128r 87056998U, // VFMSUB132PSZ128rk 89154150U, // VFMSUB132PSZ128rkz 890315366U, // VFMSUB132PSZ256m 1169367654U, // VFMSUB132PSZ256mb 1437786726U, // VFMSUB132PSZ256mbk 1437786726U, // VFMSUB132PSZ256mbkz 87089766U, // VFMSUB132PSZ256mk 89186918U, // VFMSUB132PSZ256mkz 890282598U, // VFMSUB132PSZ256r 87056998U, // VFMSUB132PSZ256rk 89154150U, // VFMSUB132PSZ256rkz 890364518U, // VFMSUB132PSZm 1171464806U, // VFMSUB132PSZmb 1439883878U, // VFMSUB132PSZmbk 1439883878U, // VFMSUB132PSZmbkz 87138918U, // VFMSUB132PSZmk 89236070U, // VFMSUB132PSZmkz 890282598U, // VFMSUB132PSZr 890413670U, // VFMSUB132PSZrb 87188070U, // VFMSUB132PSZrbk 89285222U, // VFMSUB132PSZrbkz 87056998U, // VFMSUB132PSZrk 89154150U, // VFMSUB132PSZrkz 890184294U, // VFMSUB132PSm 890282598U, // VFMSUB132PSr 1089474082U, // VFMSUB132SDZm 1089474082U, // VFMSUB132SDZm_Int 1357893154U, // VFMSUB132SDZm_Intk 1357893154U, // VFMSUB132SDZm_Intkz 890277410U, // VFMSUB132SDZr 890277410U, // VFMSUB132SDZr_Int 87051810U, // VFMSUB132SDZr_Intk 89148962U, // VFMSUB132SDZr_Intkz 890277410U, // VFMSUB132SDZrb 890408482U, // VFMSUB132SDZrb_Int 87182882U, // VFMSUB132SDZrb_Intk 89280034U, // VFMSUB132SDZrb_Intkz 1089474082U, // VFMSUB132SDm 1089474082U, // VFMSUB132SDm_Int 890277410U, // VFMSUB132SDr 890277410U, // VFMSUB132SDr_Int 1089677093U, // VFMSUB132SSZm 1089677093U, // VFMSUB132SSZm_Int 1358096165U, // VFMSUB132SSZm_Intk 1358096165U, // VFMSUB132SSZm_Intkz 890283813U, // VFMSUB132SSZr 890283813U, // VFMSUB132SSZr_Int 87058213U, // VFMSUB132SSZr_Intk 89155365U, // VFMSUB132SSZr_Intkz 890283813U, // VFMSUB132SSZrb 890414885U, // VFMSUB132SSZrb_Int 87189285U, // VFMSUB132SSZrb_Intk 89286437U, // VFMSUB132SSZrb_Intkz 1089677093U, // VFMSUB132SSm 1089677093U, // VFMSUB132SSm_Int 890283813U, // VFMSUB132SSr 890283813U, // VFMSUB132SSr_Int 890309168U, // VFMSUB213PDYm 890276400U, // VFMSUB213PDYr 890178096U, // VFMSUB213PDZ128m 1164970544U, // VFMSUB213PDZ128mb 1433389616U, // VFMSUB213PDZ128mbk 1433389616U, // VFMSUB213PDZ128mbkz 86985264U, // VFMSUB213PDZ128mk 89082416U, // VFMSUB213PDZ128mkz 890276400U, // VFMSUB213PDZ128r 87050800U, // VFMSUB213PDZ128rk 89147952U, // VFMSUB213PDZ128rkz 890309168U, // VFMSUB213PDZ256m 1167067696U, // VFMSUB213PDZ256mb 1435486768U, // VFMSUB213PDZ256mbk 1435486768U, // VFMSUB213PDZ256mbkz 87083568U, // VFMSUB213PDZ256mk 89180720U, // VFMSUB213PDZ256mkz 890276400U, // VFMSUB213PDZ256r 87050800U, // VFMSUB213PDZ256rk 89147952U, // VFMSUB213PDZ256rkz 890358320U, // VFMSUB213PDZm 1169164848U, // VFMSUB213PDZmb 1437583920U, // VFMSUB213PDZmbk 1437583920U, // VFMSUB213PDZmbkz 87132720U, // VFMSUB213PDZmk 89229872U, // VFMSUB213PDZmkz 890276400U, // VFMSUB213PDZr 890407472U, // VFMSUB213PDZrb 87181872U, // VFMSUB213PDZrbk 89279024U, // VFMSUB213PDZrbkz 87050800U, // VFMSUB213PDZrk 89147952U, // VFMSUB213PDZrkz 890178096U, // VFMSUB213PDm 890276400U, // VFMSUB213PDr 890315573U, // VFMSUB213PSYm 890282805U, // VFMSUB213PSYr 890184501U, // VFMSUB213PSZ128m 1167270709U, // VFMSUB213PSZ128mb 1435689781U, // VFMSUB213PSZ128mbk 1435689781U, // VFMSUB213PSZ128mbkz 86991669U, // VFMSUB213PSZ128mk 89088821U, // VFMSUB213PSZ128mkz 890282805U, // VFMSUB213PSZ128r 87057205U, // VFMSUB213PSZ128rk 89154357U, // VFMSUB213PSZ128rkz 890315573U, // VFMSUB213PSZ256m 1169367861U, // VFMSUB213PSZ256mb 1437786933U, // VFMSUB213PSZ256mbk 1437786933U, // VFMSUB213PSZ256mbkz 87089973U, // VFMSUB213PSZ256mk 89187125U, // VFMSUB213PSZ256mkz 890282805U, // VFMSUB213PSZ256r 87057205U, // VFMSUB213PSZ256rk 89154357U, // VFMSUB213PSZ256rkz 890364725U, // VFMSUB213PSZm 1171465013U, // VFMSUB213PSZmb 1439884085U, // VFMSUB213PSZmbk 1439884085U, // VFMSUB213PSZmbkz 87139125U, // VFMSUB213PSZmk 89236277U, // VFMSUB213PSZmkz 890282805U, // VFMSUB213PSZr 890413877U, // VFMSUB213PSZrb 87188277U, // VFMSUB213PSZrbk 89285429U, // VFMSUB213PSZrbkz 87057205U, // VFMSUB213PSZrk 89154357U, // VFMSUB213PSZrkz 890184501U, // VFMSUB213PSm 890282805U, // VFMSUB213PSr 1089474147U, // VFMSUB213SDZm 1089474147U, // VFMSUB213SDZm_Int 1357893219U, // VFMSUB213SDZm_Intk 1357893219U, // VFMSUB213SDZm_Intkz 890277475U, // VFMSUB213SDZr 890277475U, // VFMSUB213SDZr_Int 87051875U, // VFMSUB213SDZr_Intk 89149027U, // VFMSUB213SDZr_Intkz 890277475U, // VFMSUB213SDZrb 890408547U, // VFMSUB213SDZrb_Int 87182947U, // VFMSUB213SDZrb_Intk 89280099U, // VFMSUB213SDZrb_Intkz 1089474147U, // VFMSUB213SDm 1089474147U, // VFMSUB213SDm_Int 890277475U, // VFMSUB213SDr 890277475U, // VFMSUB213SDr_Int 1089677158U, // VFMSUB213SSZm 1089677158U, // VFMSUB213SSZm_Int 1358096230U, // VFMSUB213SSZm_Intk 1358096230U, // VFMSUB213SSZm_Intkz 890283878U, // VFMSUB213SSZr 890283878U, // VFMSUB213SSZr_Int 87058278U, // VFMSUB213SSZr_Intk 89155430U, // VFMSUB213SSZr_Intkz 890283878U, // VFMSUB213SSZrb 890414950U, // VFMSUB213SSZrb_Int 87189350U, // VFMSUB213SSZrb_Intk 89286502U, // VFMSUB213SSZrb_Intkz 1089677158U, // VFMSUB213SSm 1089677158U, // VFMSUB213SSm_Int 890283878U, // VFMSUB213SSr 890283878U, // VFMSUB213SSr_Int 890308886U, // VFMSUB231PDYm 890276118U, // VFMSUB231PDYr 890177814U, // VFMSUB231PDZ128m 1164970262U, // VFMSUB231PDZ128mb 1433389334U, // VFMSUB231PDZ128mbk 1433389334U, // VFMSUB231PDZ128mbkz 86984982U, // VFMSUB231PDZ128mk 89082134U, // VFMSUB231PDZ128mkz 890276118U, // VFMSUB231PDZ128r 87050518U, // VFMSUB231PDZ128rk 89147670U, // VFMSUB231PDZ128rkz 890308886U, // VFMSUB231PDZ256m 1167067414U, // VFMSUB231PDZ256mb 1435486486U, // VFMSUB231PDZ256mbk 1435486486U, // VFMSUB231PDZ256mbkz 87083286U, // VFMSUB231PDZ256mk 89180438U, // VFMSUB231PDZ256mkz 890276118U, // VFMSUB231PDZ256r 87050518U, // VFMSUB231PDZ256rk 89147670U, // VFMSUB231PDZ256rkz 890358038U, // VFMSUB231PDZm 1169164566U, // VFMSUB231PDZmb 1437583638U, // VFMSUB231PDZmbk 1437583638U, // VFMSUB231PDZmbkz 87132438U, // VFMSUB231PDZmk 89229590U, // VFMSUB231PDZmkz 890276118U, // VFMSUB231PDZr 890407190U, // VFMSUB231PDZrb 87181590U, // VFMSUB231PDZrbk 89278742U, // VFMSUB231PDZrbkz 87050518U, // VFMSUB231PDZrk 89147670U, // VFMSUB231PDZrkz 890177814U, // VFMSUB231PDm 890276118U, // VFMSUB231PDr 890315280U, // VFMSUB231PSYm 890282512U, // VFMSUB231PSYr 890184208U, // VFMSUB231PSZ128m 1167270416U, // VFMSUB231PSZ128mb 1435689488U, // VFMSUB231PSZ128mbk 1435689488U, // VFMSUB231PSZ128mbkz 86991376U, // VFMSUB231PSZ128mk 89088528U, // VFMSUB231PSZ128mkz 890282512U, // VFMSUB231PSZ128r 87056912U, // VFMSUB231PSZ128rk 89154064U, // VFMSUB231PSZ128rkz 890315280U, // VFMSUB231PSZ256m 1169367568U, // VFMSUB231PSZ256mb 1437786640U, // VFMSUB231PSZ256mbk 1437786640U, // VFMSUB231PSZ256mbkz 87089680U, // VFMSUB231PSZ256mk 89186832U, // VFMSUB231PSZ256mkz 890282512U, // VFMSUB231PSZ256r 87056912U, // VFMSUB231PSZ256rk 89154064U, // VFMSUB231PSZ256rkz 890364432U, // VFMSUB231PSZm 1171464720U, // VFMSUB231PSZmb 1439883792U, // VFMSUB231PSZmbk 1439883792U, // VFMSUB231PSZmbkz 87138832U, // VFMSUB231PSZmk 89235984U, // VFMSUB231PSZmkz 890282512U, // VFMSUB231PSZr 890413584U, // VFMSUB231PSZrb 87187984U, // VFMSUB231PSZrbk 89285136U, // VFMSUB231PSZrbkz 87056912U, // VFMSUB231PSZrk 89154064U, // VFMSUB231PSZrkz 890184208U, // VFMSUB231PSm 890282512U, // VFMSUB231PSr 1089474028U, // VFMSUB231SDZm 1089474028U, // VFMSUB231SDZm_Int 1357893100U, // VFMSUB231SDZm_Intk 1357893100U, // VFMSUB231SDZm_Intkz 890277356U, // VFMSUB231SDZr 890277356U, // VFMSUB231SDZr_Int 87051756U, // VFMSUB231SDZr_Intk 89148908U, // VFMSUB231SDZr_Intkz 890277356U, // VFMSUB231SDZrb 890408428U, // VFMSUB231SDZrb_Int 87182828U, // VFMSUB231SDZrb_Intk 89279980U, // VFMSUB231SDZrb_Intkz 1089474028U, // VFMSUB231SDm 1089474028U, // VFMSUB231SDm_Int 890277356U, // VFMSUB231SDr 890277356U, // VFMSUB231SDr_Int 1089677039U, // VFMSUB231SSZm 1089677039U, // VFMSUB231SSZm_Int 1358096111U, // VFMSUB231SSZm_Intk 1358096111U, // VFMSUB231SSZm_Intkz 890283759U, // VFMSUB231SSZr 890283759U, // VFMSUB231SSZr_Int 87058159U, // VFMSUB231SSZr_Intk 89155311U, // VFMSUB231SSZr_Intkz 890283759U, // VFMSUB231SSZrb 890414831U, // VFMSUB231SSZrb_Int 87189231U, // VFMSUB231SSZrb_Intk 89286383U, // VFMSUB231SSZrb_Intkz 1089677039U, // VFMSUB231SSm 1089677039U, // VFMSUB231SSm_Int 890283759U, // VFMSUB231SSr 890283759U, // VFMSUB231SSr_Int 890308999U, // VFMSUBADD132PDYm 890276231U, // VFMSUBADD132PDYr 890177927U, // VFMSUBADD132PDZ128m 1164970375U, // VFMSUBADD132PDZ128mb 1433389447U, // VFMSUBADD132PDZ128mbk 1433389447U, // VFMSUBADD132PDZ128mbkz 86985095U, // VFMSUBADD132PDZ128mk 89082247U, // VFMSUBADD132PDZ128mkz 890276231U, // VFMSUBADD132PDZ128r 87050631U, // VFMSUBADD132PDZ128rk 89147783U, // VFMSUBADD132PDZ128rkz 890308999U, // VFMSUBADD132PDZ256m 1167067527U, // VFMSUBADD132PDZ256mb 1435486599U, // VFMSUBADD132PDZ256mbk 1435486599U, // VFMSUBADD132PDZ256mbkz 87083399U, // VFMSUBADD132PDZ256mk 89180551U, // VFMSUBADD132PDZ256mkz 890276231U, // VFMSUBADD132PDZ256r 87050631U, // VFMSUBADD132PDZ256rk 89147783U, // VFMSUBADD132PDZ256rkz 890358151U, // VFMSUBADD132PDZm 1169164679U, // VFMSUBADD132PDZmb 1437583751U, // VFMSUBADD132PDZmbk 1437583751U, // VFMSUBADD132PDZmbkz 87132551U, // VFMSUBADD132PDZmk 89229703U, // VFMSUBADD132PDZmkz 890276231U, // VFMSUBADD132PDZr 890407303U, // VFMSUBADD132PDZrb 87181703U, // VFMSUBADD132PDZrbk 89278855U, // VFMSUBADD132PDZrbkz 87050631U, // VFMSUBADD132PDZrk 89147783U, // VFMSUBADD132PDZrkz 890177927U, // VFMSUBADD132PDm 890276231U, // VFMSUBADD132PDr 890315393U, // VFMSUBADD132PSYm 890282625U, // VFMSUBADD132PSYr 890184321U, // VFMSUBADD132PSZ128m 1167270529U, // VFMSUBADD132PSZ128mb 1435689601U, // VFMSUBADD132PSZ128mbk 1435689601U, // VFMSUBADD132PSZ128mbkz 86991489U, // VFMSUBADD132PSZ128mk 89088641U, // VFMSUBADD132PSZ128mkz 890282625U, // VFMSUBADD132PSZ128r 87057025U, // VFMSUBADD132PSZ128rk 89154177U, // VFMSUBADD132PSZ128rkz 890315393U, // VFMSUBADD132PSZ256m 1169367681U, // VFMSUBADD132PSZ256mb 1437786753U, // VFMSUBADD132PSZ256mbk 1437786753U, // VFMSUBADD132PSZ256mbkz 87089793U, // VFMSUBADD132PSZ256mk 89186945U, // VFMSUBADD132PSZ256mkz 890282625U, // VFMSUBADD132PSZ256r 87057025U, // VFMSUBADD132PSZ256rk 89154177U, // VFMSUBADD132PSZ256rkz 890364545U, // VFMSUBADD132PSZm 1171464833U, // VFMSUBADD132PSZmb 1439883905U, // VFMSUBADD132PSZmbk 1439883905U, // VFMSUBADD132PSZmbkz 87138945U, // VFMSUBADD132PSZmk 89236097U, // VFMSUBADD132PSZmkz 890282625U, // VFMSUBADD132PSZr 890413697U, // VFMSUBADD132PSZrb 87188097U, // VFMSUBADD132PSZrbk 89285249U, // VFMSUBADD132PSZrbkz 87057025U, // VFMSUBADD132PSZrk 89154177U, // VFMSUBADD132PSZrkz 890184321U, // VFMSUBADD132PSm 890282625U, // VFMSUBADD132PSr 890309195U, // VFMSUBADD213PDYm 890276427U, // VFMSUBADD213PDYr 890178123U, // VFMSUBADD213PDZ128m 1164970571U, // VFMSUBADD213PDZ128mb 1433389643U, // VFMSUBADD213PDZ128mbk 1433389643U, // VFMSUBADD213PDZ128mbkz 86985291U, // VFMSUBADD213PDZ128mk 89082443U, // VFMSUBADD213PDZ128mkz 890276427U, // VFMSUBADD213PDZ128r 87050827U, // VFMSUBADD213PDZ128rk 89147979U, // VFMSUBADD213PDZ128rkz 890309195U, // VFMSUBADD213PDZ256m 1167067723U, // VFMSUBADD213PDZ256mb 1435486795U, // VFMSUBADD213PDZ256mbk 1435486795U, // VFMSUBADD213PDZ256mbkz 87083595U, // VFMSUBADD213PDZ256mk 89180747U, // VFMSUBADD213PDZ256mkz 890276427U, // VFMSUBADD213PDZ256r 87050827U, // VFMSUBADD213PDZ256rk 89147979U, // VFMSUBADD213PDZ256rkz 890358347U, // VFMSUBADD213PDZm 1169164875U, // VFMSUBADD213PDZmb 1437583947U, // VFMSUBADD213PDZmbk 1437583947U, // VFMSUBADD213PDZmbkz 87132747U, // VFMSUBADD213PDZmk 89229899U, // VFMSUBADD213PDZmkz 890276427U, // VFMSUBADD213PDZr 890407499U, // VFMSUBADD213PDZrb 87181899U, // VFMSUBADD213PDZrbk 89279051U, // VFMSUBADD213PDZrbkz 87050827U, // VFMSUBADD213PDZrk 89147979U, // VFMSUBADD213PDZrkz 890178123U, // VFMSUBADD213PDm 890276427U, // VFMSUBADD213PDr 890315600U, // VFMSUBADD213PSYm 890282832U, // VFMSUBADD213PSYr 890184528U, // VFMSUBADD213PSZ128m 1167270736U, // VFMSUBADD213PSZ128mb 1435689808U, // VFMSUBADD213PSZ128mbk 1435689808U, // VFMSUBADD213PSZ128mbkz 86991696U, // VFMSUBADD213PSZ128mk 89088848U, // VFMSUBADD213PSZ128mkz 890282832U, // VFMSUBADD213PSZ128r 87057232U, // VFMSUBADD213PSZ128rk 89154384U, // VFMSUBADD213PSZ128rkz 890315600U, // VFMSUBADD213PSZ256m 1169367888U, // VFMSUBADD213PSZ256mb 1437786960U, // VFMSUBADD213PSZ256mbk 1437786960U, // VFMSUBADD213PSZ256mbkz 87090000U, // VFMSUBADD213PSZ256mk 89187152U, // VFMSUBADD213PSZ256mkz 890282832U, // VFMSUBADD213PSZ256r 87057232U, // VFMSUBADD213PSZ256rk 89154384U, // VFMSUBADD213PSZ256rkz 890364752U, // VFMSUBADD213PSZm 1171465040U, // VFMSUBADD213PSZmb 1439884112U, // VFMSUBADD213PSZmbk 1439884112U, // VFMSUBADD213PSZmbkz 87139152U, // VFMSUBADD213PSZmk 89236304U, // VFMSUBADD213PSZmkz 890282832U, // VFMSUBADD213PSZr 890413904U, // VFMSUBADD213PSZrb 87188304U, // VFMSUBADD213PSZrbk 89285456U, // VFMSUBADD213PSZrbkz 87057232U, // VFMSUBADD213PSZrk 89154384U, // VFMSUBADD213PSZrkz 890184528U, // VFMSUBADD213PSm 890282832U, // VFMSUBADD213PSr 890308913U, // VFMSUBADD231PDYm 890276145U, // VFMSUBADD231PDYr 890177841U, // VFMSUBADD231PDZ128m 1164970289U, // VFMSUBADD231PDZ128mb 1433389361U, // VFMSUBADD231PDZ128mbk 1433389361U, // VFMSUBADD231PDZ128mbkz 86985009U, // VFMSUBADD231PDZ128mk 89082161U, // VFMSUBADD231PDZ128mkz 890276145U, // VFMSUBADD231PDZ128r 87050545U, // VFMSUBADD231PDZ128rk 89147697U, // VFMSUBADD231PDZ128rkz 890308913U, // VFMSUBADD231PDZ256m 1167067441U, // VFMSUBADD231PDZ256mb 1435486513U, // VFMSUBADD231PDZ256mbk 1435486513U, // VFMSUBADD231PDZ256mbkz 87083313U, // VFMSUBADD231PDZ256mk 89180465U, // VFMSUBADD231PDZ256mkz 890276145U, // VFMSUBADD231PDZ256r 87050545U, // VFMSUBADD231PDZ256rk 89147697U, // VFMSUBADD231PDZ256rkz 890358065U, // VFMSUBADD231PDZm 1169164593U, // VFMSUBADD231PDZmb 1437583665U, // VFMSUBADD231PDZmbk 1437583665U, // VFMSUBADD231PDZmbkz 87132465U, // VFMSUBADD231PDZmk 89229617U, // VFMSUBADD231PDZmkz 890276145U, // VFMSUBADD231PDZr 890407217U, // VFMSUBADD231PDZrb 87181617U, // VFMSUBADD231PDZrbk 89278769U, // VFMSUBADD231PDZrbkz 87050545U, // VFMSUBADD231PDZrk 89147697U, // VFMSUBADD231PDZrkz 890177841U, // VFMSUBADD231PDm 890276145U, // VFMSUBADD231PDr 890315307U, // VFMSUBADD231PSYm 890282539U, // VFMSUBADD231PSYr 890184235U, // VFMSUBADD231PSZ128m 1167270443U, // VFMSUBADD231PSZ128mb 1435689515U, // VFMSUBADD231PSZ128mbk 1435689515U, // VFMSUBADD231PSZ128mbkz 86991403U, // VFMSUBADD231PSZ128mk 89088555U, // VFMSUBADD231PSZ128mkz 890282539U, // VFMSUBADD231PSZ128r 87056939U, // VFMSUBADD231PSZ128rk 89154091U, // VFMSUBADD231PSZ128rkz 890315307U, // VFMSUBADD231PSZ256m 1169367595U, // VFMSUBADD231PSZ256mb 1437786667U, // VFMSUBADD231PSZ256mbk 1437786667U, // VFMSUBADD231PSZ256mbkz 87089707U, // VFMSUBADD231PSZ256mk 89186859U, // VFMSUBADD231PSZ256mkz 890282539U, // VFMSUBADD231PSZ256r 87056939U, // VFMSUBADD231PSZ256rk 89154091U, // VFMSUBADD231PSZ256rkz 890364459U, // VFMSUBADD231PSZm 1171464747U, // VFMSUBADD231PSZmb 1439883819U, // VFMSUBADD231PSZmbk 1439883819U, // VFMSUBADD231PSZmbkz 87138859U, // VFMSUBADD231PSZmk 89236011U, // VFMSUBADD231PSZmkz 890282539U, // VFMSUBADD231PSZr 890413611U, // VFMSUBADD231PSZrb 87188011U, // VFMSUBADD231PSZrbk 89285163U, // VFMSUBADD231PSZrbkz 87056939U, // VFMSUBADD231PSZrk 89154091U, // VFMSUBADD231PSZrkz 890184235U, // VFMSUBADD231PSm 890282539U, // VFMSUBADD231PSr 393497391U, // VFMSUBADDPD4Ymr 890309423U, // VFMSUBADDPD4Yrm 890276655U, // VFMSUBADDPD4Yrr 890276655U, // VFMSUBADDPD4Yrr_REV 301222703U, // VFMSUBADDPD4mr 890178351U, // VFMSUBADDPD4rm 890276655U, // VFMSUBADDPD4rr 890276655U, // VFMSUBADDPD4rr_REV 393503788U, // VFMSUBADDPS4Ymr 890315820U, // VFMSUBADDPS4Yrm 890283052U, // VFMSUBADDPS4Yrr 890283052U, // VFMSUBADDPS4Yrr_REV 301229100U, // VFMSUBADDPS4mr 890184748U, // VFMSUBADDPS4rm 890283052U, // VFMSUBADDPS4rr 890283052U, // VFMSUBADDPS4rr_REV 393497300U, // VFMSUBPD4Ymr 890309332U, // VFMSUBPD4Yrm 890276564U, // VFMSUBPD4Yrr 890276564U, // VFMSUBPD4Yrr_REV 301222612U, // VFMSUBPD4mr 890178260U, // VFMSUBPD4rm 890276564U, // VFMSUBPD4rr 890276564U, // VFMSUBPD4rr_REV 393503697U, // VFMSUBPS4Ymr 890315729U, // VFMSUBPS4Yrm 890282961U, // VFMSUBPS4Yrr 890282961U, // VFMSUBPS4Yrr_REV 301229009U, // VFMSUBPS4mr 890184657U, // VFMSUBPS4rm 890282961U, // VFMSUBPS4rr 890282961U, // VFMSUBPS4rr_REV 852774605U, // VFMSUBSD4mr 852774605U, // VFMSUBSD4mr_Int 1089474253U, // VFMSUBSD4rm 1089474253U, // VFMSUBSD4rm_Int 890277581U, // VFMSUBSD4rr 890277581U, // VFMSUBSD4rr_Int 890277581U, // VFMSUBSD4rr_Int_REV 890277581U, // VFMSUBSD4rr_REV 856975304U, // VFMSUBSS4mr 856975304U, // VFMSUBSS4mr_Int 1089677256U, // VFMSUBSS4rm 1089677256U, // VFMSUBSS4rm_Int 890283976U, // VFMSUBSS4rr 890283976U, // VFMSUBSS4rr_Int 890283976U, // VFMSUBSS4rr_Int_REV 890283976U, // VFMSUBSS4rr_REV 890309028U, // VFNMADD132PDYm 890276260U, // VFNMADD132PDYr 890177956U, // VFNMADD132PDZ128m 1164970404U, // VFNMADD132PDZ128mb 1433389476U, // VFNMADD132PDZ128mbk 1433389476U, // VFNMADD132PDZ128mbkz 86985124U, // VFNMADD132PDZ128mk 89082276U, // VFNMADD132PDZ128mkz 890276260U, // VFNMADD132PDZ128r 87050660U, // VFNMADD132PDZ128rk 89147812U, // VFNMADD132PDZ128rkz 890309028U, // VFNMADD132PDZ256m 1167067556U, // VFNMADD132PDZ256mb 1435486628U, // VFNMADD132PDZ256mbk 1435486628U, // VFNMADD132PDZ256mbkz 87083428U, // VFNMADD132PDZ256mk 89180580U, // VFNMADD132PDZ256mkz 890276260U, // VFNMADD132PDZ256r 87050660U, // VFNMADD132PDZ256rk 89147812U, // VFNMADD132PDZ256rkz 890358180U, // VFNMADD132PDZm 1169164708U, // VFNMADD132PDZmb 1437583780U, // VFNMADD132PDZmbk 1437583780U, // VFNMADD132PDZmbkz 87132580U, // VFNMADD132PDZmk 89229732U, // VFNMADD132PDZmkz 890276260U, // VFNMADD132PDZr 890407332U, // VFNMADD132PDZrb 87181732U, // VFNMADD132PDZrbk 89278884U, // VFNMADD132PDZrbkz 87050660U, // VFNMADD132PDZrk 89147812U, // VFNMADD132PDZrkz 890177956U, // VFNMADD132PDm 890276260U, // VFNMADD132PDr 890315422U, // VFNMADD132PSYm 890282654U, // VFNMADD132PSYr 890184350U, // VFNMADD132PSZ128m 1167270558U, // VFNMADD132PSZ128mb 1435689630U, // VFNMADD132PSZ128mbk 1435689630U, // VFNMADD132PSZ128mbkz 86991518U, // VFNMADD132PSZ128mk 89088670U, // VFNMADD132PSZ128mkz 890282654U, // VFNMADD132PSZ128r 87057054U, // VFNMADD132PSZ128rk 89154206U, // VFNMADD132PSZ128rkz 890315422U, // VFNMADD132PSZ256m 1169367710U, // VFNMADD132PSZ256mb 1437786782U, // VFNMADD132PSZ256mbk 1437786782U, // VFNMADD132PSZ256mbkz 87089822U, // VFNMADD132PSZ256mk 89186974U, // VFNMADD132PSZ256mkz 890282654U, // VFNMADD132PSZ256r 87057054U, // VFNMADD132PSZ256rk 89154206U, // VFNMADD132PSZ256rkz 890364574U, // VFNMADD132PSZm 1171464862U, // VFNMADD132PSZmb 1439883934U, // VFNMADD132PSZmbk 1439883934U, // VFNMADD132PSZmbkz 87138974U, // VFNMADD132PSZmk 89236126U, // VFNMADD132PSZmkz 890282654U, // VFNMADD132PSZr 890413726U, // VFNMADD132PSZrb 87188126U, // VFNMADD132PSZrbk 89285278U, // VFNMADD132PSZrbkz 87057054U, // VFNMADD132PSZrk 89154206U, // VFNMADD132PSZrkz 890184350U, // VFNMADD132PSm 890282654U, // VFNMADD132PSr 1089474122U, // VFNMADD132SDZm 1089474122U, // VFNMADD132SDZm_Int 1357893194U, // VFNMADD132SDZm_Intk 1357893194U, // VFNMADD132SDZm_Intkz 890277450U, // VFNMADD132SDZr 890277450U, // VFNMADD132SDZr_Int 87051850U, // VFNMADD132SDZr_Intk 89149002U, // VFNMADD132SDZr_Intkz 890277450U, // VFNMADD132SDZrb 890408522U, // VFNMADD132SDZrb_Int 87182922U, // VFNMADD132SDZrb_Intk 89280074U, // VFNMADD132SDZrb_Intkz 1089474122U, // VFNMADD132SDm 1089474122U, // VFNMADD132SDm_Int 890277450U, // VFNMADD132SDr 890277450U, // VFNMADD132SDr_Int 1089677133U, // VFNMADD132SSZm 1089677133U, // VFNMADD132SSZm_Int 1358096205U, // VFNMADD132SSZm_Intk 1358096205U, // VFNMADD132SSZm_Intkz 890283853U, // VFNMADD132SSZr 890283853U, // VFNMADD132SSZr_Int 87058253U, // VFNMADD132SSZr_Intk 89155405U, // VFNMADD132SSZr_Intkz 890283853U, // VFNMADD132SSZrb 890414925U, // VFNMADD132SSZrb_Int 87189325U, // VFNMADD132SSZrb_Intk 89286477U, // VFNMADD132SSZrb_Intkz 1089677133U, // VFNMADD132SSm 1089677133U, // VFNMADD132SSm_Int 890283853U, // VFNMADD132SSr 890283853U, // VFNMADD132SSr_Int 890309224U, // VFNMADD213PDYm 890276456U, // VFNMADD213PDYr 890178152U, // VFNMADD213PDZ128m 1164970600U, // VFNMADD213PDZ128mb 1433389672U, // VFNMADD213PDZ128mbk 1433389672U, // VFNMADD213PDZ128mbkz 86985320U, // VFNMADD213PDZ128mk 89082472U, // VFNMADD213PDZ128mkz 890276456U, // VFNMADD213PDZ128r 87050856U, // VFNMADD213PDZ128rk 89148008U, // VFNMADD213PDZ128rkz 890309224U, // VFNMADD213PDZ256m 1167067752U, // VFNMADD213PDZ256mb 1435486824U, // VFNMADD213PDZ256mbk 1435486824U, // VFNMADD213PDZ256mbkz 87083624U, // VFNMADD213PDZ256mk 89180776U, // VFNMADD213PDZ256mkz 890276456U, // VFNMADD213PDZ256r 87050856U, // VFNMADD213PDZ256rk 89148008U, // VFNMADD213PDZ256rkz 890358376U, // VFNMADD213PDZm 1169164904U, // VFNMADD213PDZmb 1437583976U, // VFNMADD213PDZmbk 1437583976U, // VFNMADD213PDZmbkz 87132776U, // VFNMADD213PDZmk 89229928U, // VFNMADD213PDZmkz 890276456U, // VFNMADD213PDZr 890407528U, // VFNMADD213PDZrb 87181928U, // VFNMADD213PDZrbk 89279080U, // VFNMADD213PDZrbkz 87050856U, // VFNMADD213PDZrk 89148008U, // VFNMADD213PDZrkz 890178152U, // VFNMADD213PDm 890276456U, // VFNMADD213PDr 890315629U, // VFNMADD213PSYm 890282861U, // VFNMADD213PSYr 890184557U, // VFNMADD213PSZ128m 1167270765U, // VFNMADD213PSZ128mb 1435689837U, // VFNMADD213PSZ128mbk 1435689837U, // VFNMADD213PSZ128mbkz 86991725U, // VFNMADD213PSZ128mk 89088877U, // VFNMADD213PSZ128mkz 890282861U, // VFNMADD213PSZ128r 87057261U, // VFNMADD213PSZ128rk 89154413U, // VFNMADD213PSZ128rkz 890315629U, // VFNMADD213PSZ256m 1169367917U, // VFNMADD213PSZ256mb 1437786989U, // VFNMADD213PSZ256mbk 1437786989U, // VFNMADD213PSZ256mbkz 87090029U, // VFNMADD213PSZ256mk 89187181U, // VFNMADD213PSZ256mkz 890282861U, // VFNMADD213PSZ256r 87057261U, // VFNMADD213PSZ256rk 89154413U, // VFNMADD213PSZ256rkz 890364781U, // VFNMADD213PSZm 1171465069U, // VFNMADD213PSZmb 1439884141U, // VFNMADD213PSZmbk 1439884141U, // VFNMADD213PSZmbkz 87139181U, // VFNMADD213PSZmk 89236333U, // VFNMADD213PSZmkz 890282861U, // VFNMADD213PSZr 890413933U, // VFNMADD213PSZrb 87188333U, // VFNMADD213PSZrbk 89285485U, // VFNMADD213PSZrbkz 87057261U, // VFNMADD213PSZrk 89154413U, // VFNMADD213PSZrkz 890184557U, // VFNMADD213PSm 890282861U, // VFNMADD213PSr 1089474187U, // VFNMADD213SDZm 1089474187U, // VFNMADD213SDZm_Int 1357893259U, // VFNMADD213SDZm_Intk 1357893259U, // VFNMADD213SDZm_Intkz 890277515U, // VFNMADD213SDZr 890277515U, // VFNMADD213SDZr_Int 87051915U, // VFNMADD213SDZr_Intk 89149067U, // VFNMADD213SDZr_Intkz 890277515U, // VFNMADD213SDZrb 890408587U, // VFNMADD213SDZrb_Int 87182987U, // VFNMADD213SDZrb_Intk 89280139U, // VFNMADD213SDZrb_Intkz 1089474187U, // VFNMADD213SDm 1089474187U, // VFNMADD213SDm_Int 890277515U, // VFNMADD213SDr 890277515U, // VFNMADD213SDr_Int 1089677198U, // VFNMADD213SSZm 1089677198U, // VFNMADD213SSZm_Int 1358096270U, // VFNMADD213SSZm_Intk 1358096270U, // VFNMADD213SSZm_Intkz 890283918U, // VFNMADD213SSZr 890283918U, // VFNMADD213SSZr_Int 87058318U, // VFNMADD213SSZr_Intk 89155470U, // VFNMADD213SSZr_Intkz 890283918U, // VFNMADD213SSZrb 890414990U, // VFNMADD213SSZrb_Int 87189390U, // VFNMADD213SSZrb_Intk 89286542U, // VFNMADD213SSZrb_Intkz 1089677198U, // VFNMADD213SSm 1089677198U, // VFNMADD213SSm_Int 890283918U, // VFNMADD213SSr 890283918U, // VFNMADD213SSr_Int 890308942U, // VFNMADD231PDYm 890276174U, // VFNMADD231PDYr 890177870U, // VFNMADD231PDZ128m 1164970318U, // VFNMADD231PDZ128mb 1433389390U, // VFNMADD231PDZ128mbk 1433389390U, // VFNMADD231PDZ128mbkz 86985038U, // VFNMADD231PDZ128mk 89082190U, // VFNMADD231PDZ128mkz 890276174U, // VFNMADD231PDZ128r 87050574U, // VFNMADD231PDZ128rk 89147726U, // VFNMADD231PDZ128rkz 890308942U, // VFNMADD231PDZ256m 1167067470U, // VFNMADD231PDZ256mb 1435486542U, // VFNMADD231PDZ256mbk 1435486542U, // VFNMADD231PDZ256mbkz 87083342U, // VFNMADD231PDZ256mk 89180494U, // VFNMADD231PDZ256mkz 890276174U, // VFNMADD231PDZ256r 87050574U, // VFNMADD231PDZ256rk 89147726U, // VFNMADD231PDZ256rkz 890358094U, // VFNMADD231PDZm 1169164622U, // VFNMADD231PDZmb 1437583694U, // VFNMADD231PDZmbk 1437583694U, // VFNMADD231PDZmbkz 87132494U, // VFNMADD231PDZmk 89229646U, // VFNMADD231PDZmkz 890276174U, // VFNMADD231PDZr 890407246U, // VFNMADD231PDZrb 87181646U, // VFNMADD231PDZrbk 89278798U, // VFNMADD231PDZrbkz 87050574U, // VFNMADD231PDZrk 89147726U, // VFNMADD231PDZrkz 890177870U, // VFNMADD231PDm 890276174U, // VFNMADD231PDr 890315336U, // VFNMADD231PSYm 890282568U, // VFNMADD231PSYr 890184264U, // VFNMADD231PSZ128m 1167270472U, // VFNMADD231PSZ128mb 1435689544U, // VFNMADD231PSZ128mbk 1435689544U, // VFNMADD231PSZ128mbkz 86991432U, // VFNMADD231PSZ128mk 89088584U, // VFNMADD231PSZ128mkz 890282568U, // VFNMADD231PSZ128r 87056968U, // VFNMADD231PSZ128rk 89154120U, // VFNMADD231PSZ128rkz 890315336U, // VFNMADD231PSZ256m 1169367624U, // VFNMADD231PSZ256mb 1437786696U, // VFNMADD231PSZ256mbk 1437786696U, // VFNMADD231PSZ256mbkz 87089736U, // VFNMADD231PSZ256mk 89186888U, // VFNMADD231PSZ256mkz 890282568U, // VFNMADD231PSZ256r 87056968U, // VFNMADD231PSZ256rk 89154120U, // VFNMADD231PSZ256rkz 890364488U, // VFNMADD231PSZm 1171464776U, // VFNMADD231PSZmb 1439883848U, // VFNMADD231PSZmbk 1439883848U, // VFNMADD231PSZmbkz 87138888U, // VFNMADD231PSZmk 89236040U, // VFNMADD231PSZmkz 890282568U, // VFNMADD231PSZr 890413640U, // VFNMADD231PSZrb 87188040U, // VFNMADD231PSZrbk 89285192U, // VFNMADD231PSZrbkz 87056968U, // VFNMADD231PSZrk 89154120U, // VFNMADD231PSZrkz 890184264U, // VFNMADD231PSm 890282568U, // VFNMADD231PSr 1089474068U, // VFNMADD231SDZm 1089474068U, // VFNMADD231SDZm_Int 1357893140U, // VFNMADD231SDZm_Intk 1357893140U, // VFNMADD231SDZm_Intkz 890277396U, // VFNMADD231SDZr 890277396U, // VFNMADD231SDZr_Int 87051796U, // VFNMADD231SDZr_Intk 89148948U, // VFNMADD231SDZr_Intkz 890277396U, // VFNMADD231SDZrb 890408468U, // VFNMADD231SDZrb_Int 87182868U, // VFNMADD231SDZrb_Intk 89280020U, // VFNMADD231SDZrb_Intkz 1089474068U, // VFNMADD231SDm 1089474068U, // VFNMADD231SDm_Int 890277396U, // VFNMADD231SDr 890277396U, // VFNMADD231SDr_Int 1089677079U, // VFNMADD231SSZm 1089677079U, // VFNMADD231SSZm_Int 1358096151U, // VFNMADD231SSZm_Intk 1358096151U, // VFNMADD231SSZm_Intkz 890283799U, // VFNMADD231SSZr 890283799U, // VFNMADD231SSZr_Int 87058199U, // VFNMADD231SSZr_Intk 89155351U, // VFNMADD231SSZr_Intkz 890283799U, // VFNMADD231SSZrb 890414871U, // VFNMADD231SSZrb_Int 87189271U, // VFNMADD231SSZrb_Intk 89286423U, // VFNMADD231SSZrb_Intkz 1089677079U, // VFNMADD231SSm 1089677079U, // VFNMADD231SSm_Int 890283799U, // VFNMADD231SSr 890283799U, // VFNMADD231SSr_Int 393497423U, // VFNMADDPD4Ymr 890309455U, // VFNMADDPD4Yrm 890276687U, // VFNMADDPD4Yrr 890276687U, // VFNMADDPD4Yrr_REV 301222735U, // VFNMADDPD4mr 890178383U, // VFNMADDPD4rm 890276687U, // VFNMADDPD4rr 890276687U, // VFNMADDPD4rr_REV 393503843U, // VFNMADDPS4Ymr 890315875U, // VFNMADDPS4Yrm 890283107U, // VFNMADDPS4Yrr 890283107U, // VFNMADDPS4Yrr_REV 301229155U, // VFNMADDPS4mr 890184803U, // VFNMADDPS4rm 890283107U, // VFNMADDPS4rr 890283107U, // VFNMADDPS4rr_REV 852774644U, // VFNMADDSD4mr 852774644U, // VFNMADDSD4mr_Int 1089474292U, // VFNMADDSD4rm 1089474292U, // VFNMADDSD4rm_Int 890277620U, // VFNMADDSD4rr 890277620U, // VFNMADDSD4rr_Int 890277620U, // VFNMADDSD4rr_Int_REV 890277620U, // VFNMADDSD4rr_REV 856975366U, // VFNMADDSS4mr 856975366U, // VFNMADDSS4mr_Int 1089677318U, // VFNMADDSS4rm 1089677318U, // VFNMADDSS4rm_Int 890284038U, // VFNMADDSS4rr 890284038U, // VFNMADDSS4rr_Int 890284038U, // VFNMADDSS4rr_Int_REV 890284038U, // VFNMADDSS4rr_REV 890308985U, // VFNMSUB132PDYm 890276217U, // VFNMSUB132PDYr 890177913U, // VFNMSUB132PDZ128m 1164970361U, // VFNMSUB132PDZ128mb 1433389433U, // VFNMSUB132PDZ128mbk 1433389433U, // VFNMSUB132PDZ128mbkz 86985081U, // VFNMSUB132PDZ128mk 89082233U, // VFNMSUB132PDZ128mkz 890276217U, // VFNMSUB132PDZ128r 87050617U, // VFNMSUB132PDZ128rk 89147769U, // VFNMSUB132PDZ128rkz 890308985U, // VFNMSUB132PDZ256m 1167067513U, // VFNMSUB132PDZ256mb 1435486585U, // VFNMSUB132PDZ256mbk 1435486585U, // VFNMSUB132PDZ256mbkz 87083385U, // VFNMSUB132PDZ256mk 89180537U, // VFNMSUB132PDZ256mkz 890276217U, // VFNMSUB132PDZ256r 87050617U, // VFNMSUB132PDZ256rk 89147769U, // VFNMSUB132PDZ256rkz 890358137U, // VFNMSUB132PDZm 1169164665U, // VFNMSUB132PDZmb 1437583737U, // VFNMSUB132PDZmbk 1437583737U, // VFNMSUB132PDZmbkz 87132537U, // VFNMSUB132PDZmk 89229689U, // VFNMSUB132PDZmkz 890276217U, // VFNMSUB132PDZr 890407289U, // VFNMSUB132PDZrb 87181689U, // VFNMSUB132PDZrbk 89278841U, // VFNMSUB132PDZrbkz 87050617U, // VFNMSUB132PDZrk 89147769U, // VFNMSUB132PDZrkz 890177913U, // VFNMSUB132PDm 890276217U, // VFNMSUB132PDr 890315379U, // VFNMSUB132PSYm 890282611U, // VFNMSUB132PSYr 890184307U, // VFNMSUB132PSZ128m 1167270515U, // VFNMSUB132PSZ128mb 1435689587U, // VFNMSUB132PSZ128mbk 1435689587U, // VFNMSUB132PSZ128mbkz 86991475U, // VFNMSUB132PSZ128mk 89088627U, // VFNMSUB132PSZ128mkz 890282611U, // VFNMSUB132PSZ128r 87057011U, // VFNMSUB132PSZ128rk 89154163U, // VFNMSUB132PSZ128rkz 890315379U, // VFNMSUB132PSZ256m 1169367667U, // VFNMSUB132PSZ256mb 1437786739U, // VFNMSUB132PSZ256mbk 1437786739U, // VFNMSUB132PSZ256mbkz 87089779U, // VFNMSUB132PSZ256mk 89186931U, // VFNMSUB132PSZ256mkz 890282611U, // VFNMSUB132PSZ256r 87057011U, // VFNMSUB132PSZ256rk 89154163U, // VFNMSUB132PSZ256rkz 890364531U, // VFNMSUB132PSZm 1171464819U, // VFNMSUB132PSZmb 1439883891U, // VFNMSUB132PSZmbk 1439883891U, // VFNMSUB132PSZmbkz 87138931U, // VFNMSUB132PSZmk 89236083U, // VFNMSUB132PSZmkz 890282611U, // VFNMSUB132PSZr 890413683U, // VFNMSUB132PSZrb 87188083U, // VFNMSUB132PSZrbk 89285235U, // VFNMSUB132PSZrbkz 87057011U, // VFNMSUB132PSZrk 89154163U, // VFNMSUB132PSZrkz 890184307U, // VFNMSUB132PSm 890282611U, // VFNMSUB132PSr 1089474095U, // VFNMSUB132SDZm 1089474095U, // VFNMSUB132SDZm_Int 1357893167U, // VFNMSUB132SDZm_Intk 1357893167U, // VFNMSUB132SDZm_Intkz 890277423U, // VFNMSUB132SDZr 890277423U, // VFNMSUB132SDZr_Int 87051823U, // VFNMSUB132SDZr_Intk 89148975U, // VFNMSUB132SDZr_Intkz 890277423U, // VFNMSUB132SDZrb 890408495U, // VFNMSUB132SDZrb_Int 87182895U, // VFNMSUB132SDZrb_Intk 89280047U, // VFNMSUB132SDZrb_Intkz 1089474095U, // VFNMSUB132SDm 1089474095U, // VFNMSUB132SDm_Int 890277423U, // VFNMSUB132SDr 890277423U, // VFNMSUB132SDr_Int 1089677106U, // VFNMSUB132SSZm 1089677106U, // VFNMSUB132SSZm_Int 1358096178U, // VFNMSUB132SSZm_Intk 1358096178U, // VFNMSUB132SSZm_Intkz 890283826U, // VFNMSUB132SSZr 890283826U, // VFNMSUB132SSZr_Int 87058226U, // VFNMSUB132SSZr_Intk 89155378U, // VFNMSUB132SSZr_Intkz 890283826U, // VFNMSUB132SSZrb 890414898U, // VFNMSUB132SSZrb_Int 87189298U, // VFNMSUB132SSZrb_Intk 89286450U, // VFNMSUB132SSZrb_Intkz 1089677106U, // VFNMSUB132SSm 1089677106U, // VFNMSUB132SSm_Int 890283826U, // VFNMSUB132SSr 890283826U, // VFNMSUB132SSr_Int 890309181U, // VFNMSUB213PDYm 890276413U, // VFNMSUB213PDYr 890178109U, // VFNMSUB213PDZ128m 1164970557U, // VFNMSUB213PDZ128mb 1433389629U, // VFNMSUB213PDZ128mbk 1433389629U, // VFNMSUB213PDZ128mbkz 86985277U, // VFNMSUB213PDZ128mk 89082429U, // VFNMSUB213PDZ128mkz 890276413U, // VFNMSUB213PDZ128r 87050813U, // VFNMSUB213PDZ128rk 89147965U, // VFNMSUB213PDZ128rkz 890309181U, // VFNMSUB213PDZ256m 1167067709U, // VFNMSUB213PDZ256mb 1435486781U, // VFNMSUB213PDZ256mbk 1435486781U, // VFNMSUB213PDZ256mbkz 87083581U, // VFNMSUB213PDZ256mk 89180733U, // VFNMSUB213PDZ256mkz 890276413U, // VFNMSUB213PDZ256r 87050813U, // VFNMSUB213PDZ256rk 89147965U, // VFNMSUB213PDZ256rkz 890358333U, // VFNMSUB213PDZm 1169164861U, // VFNMSUB213PDZmb 1437583933U, // VFNMSUB213PDZmbk 1437583933U, // VFNMSUB213PDZmbkz 87132733U, // VFNMSUB213PDZmk 89229885U, // VFNMSUB213PDZmkz 890276413U, // VFNMSUB213PDZr 890407485U, // VFNMSUB213PDZrb 87181885U, // VFNMSUB213PDZrbk 89279037U, // VFNMSUB213PDZrbkz 87050813U, // VFNMSUB213PDZrk 89147965U, // VFNMSUB213PDZrkz 890178109U, // VFNMSUB213PDm 890276413U, // VFNMSUB213PDr 890315586U, // VFNMSUB213PSYm 890282818U, // VFNMSUB213PSYr 890184514U, // VFNMSUB213PSZ128m 1167270722U, // VFNMSUB213PSZ128mb 1435689794U, // VFNMSUB213PSZ128mbk 1435689794U, // VFNMSUB213PSZ128mbkz 86991682U, // VFNMSUB213PSZ128mk 89088834U, // VFNMSUB213PSZ128mkz 890282818U, // VFNMSUB213PSZ128r 87057218U, // VFNMSUB213PSZ128rk 89154370U, // VFNMSUB213PSZ128rkz 890315586U, // VFNMSUB213PSZ256m 1169367874U, // VFNMSUB213PSZ256mb 1437786946U, // VFNMSUB213PSZ256mbk 1437786946U, // VFNMSUB213PSZ256mbkz 87089986U, // VFNMSUB213PSZ256mk 89187138U, // VFNMSUB213PSZ256mkz 890282818U, // VFNMSUB213PSZ256r 87057218U, // VFNMSUB213PSZ256rk 89154370U, // VFNMSUB213PSZ256rkz 890364738U, // VFNMSUB213PSZm 1171465026U, // VFNMSUB213PSZmb 1439884098U, // VFNMSUB213PSZmbk 1439884098U, // VFNMSUB213PSZmbkz 87139138U, // VFNMSUB213PSZmk 89236290U, // VFNMSUB213PSZmkz 890282818U, // VFNMSUB213PSZr 890413890U, // VFNMSUB213PSZrb 87188290U, // VFNMSUB213PSZrbk 89285442U, // VFNMSUB213PSZrbkz 87057218U, // VFNMSUB213PSZrk 89154370U, // VFNMSUB213PSZrkz 890184514U, // VFNMSUB213PSm 890282818U, // VFNMSUB213PSr 1089474160U, // VFNMSUB213SDZm 1089474160U, // VFNMSUB213SDZm_Int 1357893232U, // VFNMSUB213SDZm_Intk 1357893232U, // VFNMSUB213SDZm_Intkz 890277488U, // VFNMSUB213SDZr 890277488U, // VFNMSUB213SDZr_Int 87051888U, // VFNMSUB213SDZr_Intk 89149040U, // VFNMSUB213SDZr_Intkz 890277488U, // VFNMSUB213SDZrb 890408560U, // VFNMSUB213SDZrb_Int 87182960U, // VFNMSUB213SDZrb_Intk 89280112U, // VFNMSUB213SDZrb_Intkz 1089474160U, // VFNMSUB213SDm 1089474160U, // VFNMSUB213SDm_Int 890277488U, // VFNMSUB213SDr 890277488U, // VFNMSUB213SDr_Int 1089677171U, // VFNMSUB213SSZm 1089677171U, // VFNMSUB213SSZm_Int 1358096243U, // VFNMSUB213SSZm_Intk 1358096243U, // VFNMSUB213SSZm_Intkz 890283891U, // VFNMSUB213SSZr 890283891U, // VFNMSUB213SSZr_Int 87058291U, // VFNMSUB213SSZr_Intk 89155443U, // VFNMSUB213SSZr_Intkz 890283891U, // VFNMSUB213SSZrb 890414963U, // VFNMSUB213SSZrb_Int 87189363U, // VFNMSUB213SSZrb_Intk 89286515U, // VFNMSUB213SSZrb_Intkz 1089677171U, // VFNMSUB213SSm 1089677171U, // VFNMSUB213SSm_Int 890283891U, // VFNMSUB213SSr 890283891U, // VFNMSUB213SSr_Int 890308899U, // VFNMSUB231PDYm 890276131U, // VFNMSUB231PDYr 890177827U, // VFNMSUB231PDZ128m 1164970275U, // VFNMSUB231PDZ128mb 1433389347U, // VFNMSUB231PDZ128mbk 1433389347U, // VFNMSUB231PDZ128mbkz 86984995U, // VFNMSUB231PDZ128mk 89082147U, // VFNMSUB231PDZ128mkz 890276131U, // VFNMSUB231PDZ128r 87050531U, // VFNMSUB231PDZ128rk 89147683U, // VFNMSUB231PDZ128rkz 890308899U, // VFNMSUB231PDZ256m 1167067427U, // VFNMSUB231PDZ256mb 1435486499U, // VFNMSUB231PDZ256mbk 1435486499U, // VFNMSUB231PDZ256mbkz 87083299U, // VFNMSUB231PDZ256mk 89180451U, // VFNMSUB231PDZ256mkz 890276131U, // VFNMSUB231PDZ256r 87050531U, // VFNMSUB231PDZ256rk 89147683U, // VFNMSUB231PDZ256rkz 890358051U, // VFNMSUB231PDZm 1169164579U, // VFNMSUB231PDZmb 1437583651U, // VFNMSUB231PDZmbk 1437583651U, // VFNMSUB231PDZmbkz 87132451U, // VFNMSUB231PDZmk 89229603U, // VFNMSUB231PDZmkz 890276131U, // VFNMSUB231PDZr 890407203U, // VFNMSUB231PDZrb 87181603U, // VFNMSUB231PDZrbk 89278755U, // VFNMSUB231PDZrbkz 87050531U, // VFNMSUB231PDZrk 89147683U, // VFNMSUB231PDZrkz 890177827U, // VFNMSUB231PDm 890276131U, // VFNMSUB231PDr 890315293U, // VFNMSUB231PSYm 890282525U, // VFNMSUB231PSYr 890184221U, // VFNMSUB231PSZ128m 1167270429U, // VFNMSUB231PSZ128mb 1435689501U, // VFNMSUB231PSZ128mbk 1435689501U, // VFNMSUB231PSZ128mbkz 86991389U, // VFNMSUB231PSZ128mk 89088541U, // VFNMSUB231PSZ128mkz 890282525U, // VFNMSUB231PSZ128r 87056925U, // VFNMSUB231PSZ128rk 89154077U, // VFNMSUB231PSZ128rkz 890315293U, // VFNMSUB231PSZ256m 1169367581U, // VFNMSUB231PSZ256mb 1437786653U, // VFNMSUB231PSZ256mbk 1437786653U, // VFNMSUB231PSZ256mbkz 87089693U, // VFNMSUB231PSZ256mk 89186845U, // VFNMSUB231PSZ256mkz 890282525U, // VFNMSUB231PSZ256r 87056925U, // VFNMSUB231PSZ256rk 89154077U, // VFNMSUB231PSZ256rkz 890364445U, // VFNMSUB231PSZm 1171464733U, // VFNMSUB231PSZmb 1439883805U, // VFNMSUB231PSZmbk 1439883805U, // VFNMSUB231PSZmbkz 87138845U, // VFNMSUB231PSZmk 89235997U, // VFNMSUB231PSZmkz 890282525U, // VFNMSUB231PSZr 890413597U, // VFNMSUB231PSZrb 87187997U, // VFNMSUB231PSZrbk 89285149U, // VFNMSUB231PSZrbkz 87056925U, // VFNMSUB231PSZrk 89154077U, // VFNMSUB231PSZrkz 890184221U, // VFNMSUB231PSm 890282525U, // VFNMSUB231PSr 1089474041U, // VFNMSUB231SDZm 1089474041U, // VFNMSUB231SDZm_Int 1357893113U, // VFNMSUB231SDZm_Intk 1357893113U, // VFNMSUB231SDZm_Intkz 890277369U, // VFNMSUB231SDZr 890277369U, // VFNMSUB231SDZr_Int 87051769U, // VFNMSUB231SDZr_Intk 89148921U, // VFNMSUB231SDZr_Intkz 890277369U, // VFNMSUB231SDZrb 890408441U, // VFNMSUB231SDZrb_Int 87182841U, // VFNMSUB231SDZrb_Intk 89279993U, // VFNMSUB231SDZrb_Intkz 1089474041U, // VFNMSUB231SDm 1089474041U, // VFNMSUB231SDm_Int 890277369U, // VFNMSUB231SDr 890277369U, // VFNMSUB231SDr_Int 1089677052U, // VFNMSUB231SSZm 1089677052U, // VFNMSUB231SSZm_Int 1358096124U, // VFNMSUB231SSZm_Intk 1358096124U, // VFNMSUB231SSZm_Intkz 890283772U, // VFNMSUB231SSZr 890283772U, // VFNMSUB231SSZr_Int 87058172U, // VFNMSUB231SSZr_Intk 89155324U, // VFNMSUB231SSZr_Intkz 890283772U, // VFNMSUB231SSZrb 890414844U, // VFNMSUB231SSZrb_Int 87189244U, // VFNMSUB231SSZrb_Intk 89286396U, // VFNMSUB231SSZrb_Intkz 1089677052U, // VFNMSUB231SSm 1089677052U, // VFNMSUB231SSm_Int 890283772U, // VFNMSUB231SSr 890283772U, // VFNMSUB231SSr_Int 393497310U, // VFNMSUBPD4Ymr 890309342U, // VFNMSUBPD4Yrm 890276574U, // VFNMSUBPD4Yrr 890276574U, // VFNMSUBPD4Yrr_REV 301222622U, // VFNMSUBPD4mr 890178270U, // VFNMSUBPD4rm 890276574U, // VFNMSUBPD4rr 890276574U, // VFNMSUBPD4rr_REV 393503707U, // VFNMSUBPS4Ymr 890315739U, // VFNMSUBPS4Yrm 890282971U, // VFNMSUBPS4Yrr 890282971U, // VFNMSUBPS4Yrr_REV 301229019U, // VFNMSUBPS4mr 890184667U, // VFNMSUBPS4rm 890282971U, // VFNMSUBPS4rr 890282971U, // VFNMSUBPS4rr_REV 852774615U, // VFNMSUBSD4mr 852774615U, // VFNMSUBSD4mr_Int 1089474263U, // VFNMSUBSD4rm 1089474263U, // VFNMSUBSD4rm_Int 890277591U, // VFNMSUBSD4rr 890277591U, // VFNMSUBSD4rr_Int 890277591U, // VFNMSUBSD4rr_Int_REV 890277591U, // VFNMSUBSD4rr_REV 856975314U, // VFNMSUBSS4mr 856975314U, // VFNMSUBSS4mr_Int 1089677266U, // VFNMSUBSS4rm 1089677266U, // VFNMSUBSS4rm_Int 890283986U, // VFNMSUBSS4rr 890283986U, // VFNMSUBSS4rr_Int 890283986U, // VFNMSUBSS4rr_Int_REV 890283986U, // VFNMSUBSS4rr_REV 77901811U, // VFPCLASSPDZ128rm 3032783586U, // VFPCLASSPDZ128rmb 2999311074U, // VFPCLASSPDZ128rmbk 568717299U, // VFPCLASSPDZ128rmk 283430104U, // VFPCLASSPDZ128rr 1088818392U, // VFPCLASSPDZ128rrk 168079470U, // VFPCLASSPDZ256rm 1690606306U, // VFPCLASSPDZ256rmb 1657133794U, // VFPCLASSPDZ256rmbk 660992110U, // VFPCLASSPDZ256rmk 283430104U, // VFPCLASSPDZ256rr 1088818392U, // VFPCLASSPDZ256rrk 170176747U, // VFPCLASSPDZrm 2495912674U, // VFPCLASSPDZrmb 2462440162U, // VFPCLASSPDZrmbk 669380843U, // VFPCLASSPDZrmk 283430104U, // VFPCLASSPDZrr 1088818392U, // VFPCLASSPDZrrk 77901913U, // VFPCLASSPSZ128rm 1692702429U, // VFPCLASSPSZ128rmb 1661327069U, // VFPCLASSPSZ128rmbk 568717401U, // VFPCLASSPSZ128rmk 283436561U, // VFPCLASSPSZ128rr 1088824849U, // VFPCLASSPSZ128rrk 168079582U, // VFPCLASSPSZ256rm 2498008797U, // VFPCLASSPSZ256rmb 2466633437U, // VFPCLASSPSZ256rmbk 660992222U, // VFPCLASSPSZ256rmk 283436561U, // VFPCLASSPSZ256rr 1088824849U, // VFPCLASSPSZ256rrk 170176760U, // VFPCLASSPSZrm 2766444253U, // VFPCLASSPSZrmb 2735068893U, // VFPCLASSPSZrmbk 669380856U, // VFPCLASSPSZrmk 283436561U, // VFPCLASSPSZrr 1088824849U, // VFPCLASSPSZrrk 885297054U, // VFPCLASSSDZrm 851824542U, // VFPCLASSSDZrmk 283430814U, // VFPCLASSSDZrr 1088819102U, // VFPCLASSSDZrrk 887400603U, // VFPCLASSSSZrm 856025243U, // VFPCLASSSSZrmk 283437211U, // VFPCLASSSSZrr 1088825499U, // VFPCLASSSSZrrk 1346906U, // VFRCZPDYrm 551832922U, // VFRCZPDYrr 658778U, // VFRCZPDrm 551832922U, // VFRCZPDrr 1353403U, // VFRCZPSYrm 551839419U, // VFRCZPSYrr 665275U, // VFRCZPSrm 551839419U, // VFRCZPSrr 552177694U, // VFRCZSDrm 551833630U, // VFRCZSDrr 552200437U, // VFRCZSSrm 551839989U, // VFRCZSSrr 649546633U, // VGATHERDPDYrm 3231157129U, // VGATHERDPDZ128rm 3231173513U, // VGATHERDPDZ256rm 3231189897U, // VGATHERDPDZrm 643255177U, // VGATHERDPDrm 649553053U, // VGATHERDPSYrm 3231163549U, // VGATHERDPSZ128rm 3231179933U, // VGATHERDPSZ256rm 3231196317U, // VGATHERDPSZrm 643261597U, // VGATHERDPSrm 172854001U, // VGATHERPF0DPDm 172860398U, // VGATHERPF0DPSm 172854386U, // VGATHERPF0QPDm 173368747U, // VGATHERPF0QPSm 172854032U, // VGATHERPF1DPDm 172860429U, // VGATHERPF1DPSm 172854417U, // VGATHERPF1QPDm 173368778U, // VGATHERPF1QPSm 649546928U, // VGATHERQPDYrm 3231157424U, // VGATHERQPDZ128rm 3231173808U, // VGATHERQPDZ256rm 3231190192U, // VGATHERQPDZrm 643255472U, // VGATHERQPDrm 643261929U, // VGATHERQPSYrm 553149929U, // VGATHERQPSZ128rm 3231163881U, // VGATHERQPSZ256rm 3231180265U, // VGATHERQPSZrm 928474601U, // VGATHERQPSrm 658535U, // VGETEXPPDZ128m 627674215U, // VGETEXPPDZ128mb 628100199U, // VGETEXPPDZ128mbk 627199079U, // VGETEXPPDZ128mbkz 3230600295U, // VGETEXPPDZ128mk 3229748327U, // VGETEXPPDZ128mkz 551832679U, // VGETEXPPDZ128r 3230698599U, // VGETEXPPDZ128rk 3229666407U, // VGETEXPPDZ128rkz 1346663U, // VGETEXPPDZ256m 629771367U, // VGETEXPPDZ256mb 630197351U, // VGETEXPPDZ256mbk 629296231U, // VGETEXPPDZ256mbkz 3230731367U, // VGETEXPPDZ256mk 3230633063U, // VGETEXPPDZ256mkz 551832679U, // VGETEXPPDZ256r 3230698599U, // VGETEXPPDZ256rk 3229666407U, // VGETEXPPDZ256rkz 1510503U, // VGETEXPPDZm 631868519U, // VGETEXPPDZmb 632294503U, // VGETEXPPDZmbk 631393383U, // VGETEXPPDZmbkz 3230780519U, // VGETEXPPDZmk 3230747751U, // VGETEXPPDZmkz 551832679U, // VGETEXPPDZr 551843335U, // VGETEXPPDZrb 3230709255U, // VGETEXPPDZrbk 3229677063U, // VGETEXPPDZrbkz 3230698599U, // VGETEXPPDZrk 3229666407U, // VGETEXPPDZrkz 664992U, // VGETEXPPSZ128m 629794208U, // VGETEXPPSZ128mb 630400416U, // VGETEXPPSZ128mbk 629319072U, // VGETEXPPSZ128mbkz 3230606752U, // VGETEXPPSZ128mk 3229754784U, // VGETEXPPSZ128mkz 551839136U, // VGETEXPPSZ128r 3230705056U, // VGETEXPPSZ128rk 3229672864U, // VGETEXPPSZ128rkz 1353120U, // VGETEXPPSZ256m 631891360U, // VGETEXPPSZ256mb 632497568U, // VGETEXPPSZ256mbk 631416224U, // VGETEXPPSZ256mbkz 3230737824U, // VGETEXPPSZ256mk 3230639520U, // VGETEXPPSZ256mkz 551839136U, // VGETEXPPSZ256r 3230705056U, // VGETEXPPSZ256rk 3229672864U, // VGETEXPPSZ256rkz 1516960U, // VGETEXPPSZm 633988512U, // VGETEXPPSZmb 634594720U, // VGETEXPPSZmbk 633513376U, // VGETEXPPSZmbkz 3230786976U, // VGETEXPPSZmk 3230754208U, // VGETEXPPSZmkz 551839136U, // VGETEXPPSZr 551843822U, // VGETEXPPSZrb 3230709742U, // VGETEXPPSZrbk 3229677550U, // VGETEXPPSZrbkz 3230705056U, // VGETEXPPSZrk 3229672864U, // VGETEXPPSZrkz 283266943U, // VGETEXPSDZm 1357893503U, // VGETEXPSDZmk 1089474431U, // VGETEXPSDZmkz 811650943U, // VGETEXPSDZr 811660942U, // VGETEXPSDZrb 87062158U, // VGETEXPSDZrbk 890287758U, // VGETEXPSDZrbkz 87052159U, // VGETEXPSDZrk 890277759U, // VGETEXPSDZrkz 283289744U, // VGETEXPSSZm 1358096528U, // VGETEXPSSZmk 1089677456U, // VGETEXPSSZmkz 811657360U, // VGETEXPSSZr 811661411U, // VGETEXPSSZrb 87062627U, // VGETEXPSSZrbk 890288227U, // VGETEXPSSZrbkz 87058576U, // VGETEXPSSZrk 890284176U, // VGETEXPSSZrkz 3032780034U, // VGETMANTPDZ128rmbi 3079933186U, // VGETMANTPDZ128rmbik 2999307522U, // VGETMANTPDZ128rmbikz 77892866U, // VGETMANTPDZ128rmi 666111234U, // VGETMANTPDZ128rmik 568708354U, // VGETMANTPDZ128rmikz 283430146U, // VGETMANTPDZ128rri 1357581570U, // VGETMANTPDZ128rrik 1088818434U, // VGETMANTPDZ128rrikz 1690602754U, // VGETMANTPDZ256rmbi 1737755906U, // VGETMANTPDZ256rmbik 1657130242U, // VGETMANTPDZ256rmbikz 168070402U, // VGETMANTPDZ256rmi 668208386U, // VGETMANTPDZ256rmik 660983042U, // VGETMANTPDZ256rmikz 283430146U, // VGETMANTPDZ256rri 1357581570U, // VGETMANTPDZ256rrik 1088818434U, // VGETMANTPDZ256rrikz 2495909122U, // VGETMANTPDZrmbi 2543062274U, // VGETMANTPDZrmbik 2462436610U, // VGETMANTPDZrmbikz 170167554U, // VGETMANTPDZrmi 672402690U, // VGETMANTPDZrmik 669371650U, // VGETMANTPDZrmikz 283430146U, // VGETMANTPDZrri 407162114U, // VGETMANTPDZrrib 1481313538U, // VGETMANTPDZrribk 1212550402U, // VGETMANTPDZrribkz 1357581570U, // VGETMANTPDZrrik 1088818434U, // VGETMANTPDZrrikz 1692706358U, // VGETMANTPSZ128rmbi 1752442422U, // VGETMANTPSZ128rmbik 1661330998U, // VGETMANTPSZ128rmbikz 77899318U, // VGETMANTPSZ128rmi 666117686U, // VGETMANTPSZ128rmik 568714806U, // VGETMANTPSZ128rmikz 283436598U, // VGETMANTPSZ128rri 1357588022U, // VGETMANTPSZ128rrik 1088824886U, // VGETMANTPSZ128rrikz 2498012726U, // VGETMANTPSZ256rmbi 2557748790U, // VGETMANTPSZ256rmbik 2466637366U, // VGETMANTPSZ256rmbikz 168076854U, // VGETMANTPSZ256rmi 668214838U, // VGETMANTPSZ256rmik 660989494U, // VGETMANTPSZ256rmikz 283436598U, // VGETMANTPSZ256rri 1357588022U, // VGETMANTPSZ256rrik 1088824886U, // VGETMANTPSZ256rrikz 2766448182U, // VGETMANTPSZrmbi 2826184246U, // VGETMANTPSZrmbik 2735072822U, // VGETMANTPSZrmbikz 170174006U, // VGETMANTPSZrmi 672409142U, // VGETMANTPSZrmik 669378102U, // VGETMANTPSZrmikz 283436598U, // VGETMANTPSZrri 407168566U, // VGETMANTPSZrrib 1481319990U, // VGETMANTPSZrribk 1212556854U, // VGETMANTPSZrribkz 1357588022U, // VGETMANTPSZrrik 1088824886U, // VGETMANTPSZrrikz 851824583U, // VGETMANTSDZrmi 963891143U, // VGETMANTSDZrmik 932450247U, // VGETMANTSDZrmikz 1088819143U, // VGETMANTSDZrri 1212551111U, // VGETMANTSDZrrib 2286866375U, // VGETMANTSDZrribk 1481314247U, // VGETMANTSDZrribkz 2163134407U, // VGETMANTSDZrrik 1357582279U, // VGETMANTSDZrrikz 856025255U, // VGETMANTSSZrmi 972286119U, // VGETMANTSSZrmik 947136679U, // VGETMANTSSZrmikz 1088825511U, // VGETMANTSSZrri 1212557479U, // VGETMANTSSZrrib 2286872743U, // VGETMANTSSZrribk 1481320615U, // VGETMANTSSZrribkz 2163140775U, // VGETMANTSSZrrik 1357588647U, // VGETMANTSSZrrikz 375768372U, // VGF2P8AFFINEINVQBYrmi 1088816436U, // VGF2P8AFFINEINVQBYrri 3026568500U, // VGF2P8AFFINEINVQBZ128rmbi 3128149300U, // VGF2P8AFFINEINVQBZ128rmbik 3130262836U, // VGF2P8AFFINEINVQBZ128rmbikz 325436724U, // VGF2P8AFFINEINVQBZ128rmi 1983104308U, // VGF2P8AFFINEINVQBZ128rmik 1179911476U, // VGF2P8AFFINEINVQBZ128rmikz 1088816436U, // VGF2P8AFFINEINVQBZ128rri 2163131700U, // VGF2P8AFFINEINVQBZ128rrik 1357579572U, // VGF2P8AFFINEINVQBZ128rrikz 1684391220U, // VGF2P8AFFINEINVQBZ256rmbi 1785972020U, // VGF2P8AFFINEINVQBZ256rmbik 1788085556U, // VGF2P8AFFINEINVQBZ256rmbikz 375768372U, // VGF2P8AFFINEINVQBZ256rmi 1989395764U, // VGF2P8AFFINEINVQBZ256rmik 1186202932U, // VGF2P8AFFINEINVQBZ256rmikz 1088816436U, // VGF2P8AFFINEINVQBZ256rri 2163131700U, // VGF2P8AFFINEINVQBZ256rrik 1357579572U, // VGF2P8AFFINEINVQBZ256rrikz 2489697588U, // VGF2P8AFFINEINVQBZrmbi 2591278388U, // VGF2P8AFFINEINVQBZrmbik 2593391924U, // VGF2P8AFFINEINVQBZrmbikz 382059828U, // VGF2P8AFFINEINVQBZrmi 1995687220U, // VGF2P8AFFINEINVQBZrmik 1192494388U, // VGF2P8AFFINEINVQBZrmikz 1088816436U, // VGF2P8AFFINEINVQBZrri 2163131700U, // VGF2P8AFFINEINVQBZrrik 1357579572U, // VGF2P8AFFINEINVQBZrrikz 325436724U, // VGF2P8AFFINEINVQBrmi 1088816436U, // VGF2P8AFFINEINVQBrri 375768309U, // VGF2P8AFFINEQBYrmi 1088816373U, // VGF2P8AFFINEQBYrri 3026568437U, // VGF2P8AFFINEQBZ128rmbi 3128149237U, // VGF2P8AFFINEQBZ128rmbik 3130262773U, // VGF2P8AFFINEQBZ128rmbikz 325436661U, // VGF2P8AFFINEQBZ128rmi 1983104245U, // VGF2P8AFFINEQBZ128rmik 1179911413U, // VGF2P8AFFINEQBZ128rmikz 1088816373U, // VGF2P8AFFINEQBZ128rri 2163131637U, // VGF2P8AFFINEQBZ128rrik 1357579509U, // VGF2P8AFFINEQBZ128rrikz 1684391157U, // VGF2P8AFFINEQBZ256rmbi 1785971957U, // VGF2P8AFFINEQBZ256rmbik 1788085493U, // VGF2P8AFFINEQBZ256rmbikz 375768309U, // VGF2P8AFFINEQBZ256rmi 1989395701U, // VGF2P8AFFINEQBZ256rmik 1186202869U, // VGF2P8AFFINEQBZ256rmikz 1088816373U, // VGF2P8AFFINEQBZ256rri 2163131637U, // VGF2P8AFFINEQBZ256rrik 1357579509U, // VGF2P8AFFINEQBZ256rrikz 2489697525U, // VGF2P8AFFINEQBZrmbi 2591278325U, // VGF2P8AFFINEQBZrmbik 2593391861U, // VGF2P8AFFINEQBZrmbikz 382059765U, // VGF2P8AFFINEQBZrmi 1995687157U, // VGF2P8AFFINEQBZrmik 1192494325U, // VGF2P8AFFINEQBZrmikz 1088816373U, // VGF2P8AFFINEQBZrri 2163131637U, // VGF2P8AFFINEQBZrrik 1357579509U, // VGF2P8AFFINEQBZrrikz 325436661U, // VGF2P8AFFINEQBrmi 1088816373U, // VGF2P8AFFINEQBrri 812860541U, // VGF2P8MULBYrm 811648125U, // VGF2P8MULBYrr 811844733U, // VGF2P8MULBZ128rm 985105533U, // VGF2P8MULBZ128rmk 890569853U, // VGF2P8MULBZ128rmkz 811648125U, // VGF2P8MULBZ128rr 87049341U, // VGF2P8MULBZ128rrk 890274941U, // VGF2P8MULBZ128rrkz 812860541U, // VGF2P8MULBZ256rm 985121917U, // VGF2P8MULBZ256rmk 890602621U, // VGF2P8MULBZ256rmkz 811648125U, // VGF2P8MULBZ256rr 87049341U, // VGF2P8MULBZ256rrk 890274941U, // VGF2P8MULBZ256rrkz 812876925U, // VGF2P8MULBZrm 985138301U, // VGF2P8MULBZrmk 890668157U, // VGF2P8MULBZrmkz 811648125U, // VGF2P8MULBZrr 87049341U, // VGF2P8MULBZrrk 890274941U, // VGF2P8MULBZrrkz 811844733U, // VGF2P8MULBrm 811648125U, // VGF2P8MULBrr 812616508U, // VHADDPDYrm 811649852U, // VHADDPDYrr 811731772U, // VHADDPDrm 811649852U, // VHADDPDrr 812622905U, // VHADDPSYrm 811656249U, // VHADDPSYrr 811738169U, // VHADDPSrm 811656249U, // VHADDPSrr 812616395U, // VHSUBPDYrm 811649739U, // VHSUBPDYrr 811731659U, // VHSUBPDrm 811649739U, // VHSUBPDrr 812622792U, // VHSUBPSYrm 811656136U, // VHSUBPSYrr 811738056U, // VHSUBPSrm 811656136U, // VHSUBPSrr 300270206U, // VINSERTF128rm 1088815742U, // VINSERTF128rr 300269988U, // VINSERTF32x4Z256rm 2039726500U, // VINSERTF32x4Z256rmk 1202979236U, // VINSERTF32x4Z256rmkz 1088815524U, // VINSERTF32x4Z256rr 2163130788U, // VINSERTF32x4Z256rrk 1357578660U, // VINSERTF32x4Z256rrkz 300269988U, // VINSERTF32x4Zrm 2039726500U, // VINSERTF32x4Zrmk 1202979236U, // VINSERTF32x4Zrmkz 1088815524U, // VINSERTF32x4Zrr 2163130788U, // VINSERTF32x4Zrrk 1357578660U, // VINSERTF32x4Zrrkz 392545003U, // VINSERTF32x8Zrm 2041823979U, // VINSERTF32x8Zrmk 1205076715U, // VINSERTF32x8Zrmkz 1088815851U, // VINSERTF32x8Zrr 2163131115U, // VINSERTF32x8Zrrk 1357578987U, // VINSERTF32x8Zrrkz 300269775U, // VINSERTF64x2Z256rm 2039726287U, // VINSERTF64x2Z256rmk 1202979023U, // VINSERTF64x2Z256rmkz 1088815311U, // VINSERTF64x2Z256rr 2163130575U, // VINSERTF64x2Z256rrk 1357578447U, // VINSERTF64x2Z256rrkz 300269775U, // VINSERTF64x2Zrm 2039726287U, // VINSERTF64x2Zrmk 1202979023U, // VINSERTF64x2Zrmkz 1088815311U, // VINSERTF64x2Zrr 2163130575U, // VINSERTF64x2Zrrk 1357578447U, // VINSERTF64x2Zrrkz 392544780U, // VINSERTF64x4Zrm 2041823756U, // VINSERTF64x4Zrmk 1205076492U, // VINSERTF64x4Zrmkz 1088815628U, // VINSERTF64x4Zrr 2163130892U, // VINSERTF64x4Zrrk 1357578764U, // VINSERTF64x4Zrrkz 325436085U, // VINSERTI128rm 1088815797U, // VINSERTI128rr 325435870U, // VINSERTI32x4Z256rm 1983103454U, // VINSERTI32x4Z256rmk 1179910622U, // VINSERTI32x4Z256rmkz 1088815582U, // VINSERTI32x4Z256rr 2163130846U, // VINSERTI32x4Z256rrk 1357578718U, // VINSERTI32x4Z256rrkz 325435870U, // VINSERTI32x4Zrm 1983103454U, // VINSERTI32x4Zrmk 1179910622U, // VINSERTI32x4Zrmkz 1088815582U, // VINSERTI32x4Zrr 2163130846U, // VINSERTI32x4Zrrk 1357578718U, // VINSERTI32x4Zrrkz 375767833U, // VINSERTI32x8Zrm 1989395225U, // VINSERTI32x8Zrmk 1186202393U, // VINSERTI32x8Zrmkz 1088815897U, // VINSERTI32x8Zrr 2163131161U, // VINSERTI32x8Zrrk 1357579033U, // VINSERTI32x8Zrrkz 325435657U, // VINSERTI64x2Z256rm 1983103241U, // VINSERTI64x2Z256rmk 1179910409U, // VINSERTI64x2Z256rmkz 1088815369U, // VINSERTI64x2Z256rr 2163130633U, // VINSERTI64x2Z256rrk 1357578505U, // VINSERTI64x2Z256rrkz 325435657U, // VINSERTI64x2Zrm 1983103241U, // VINSERTI64x2Zrmk 1179910409U, // VINSERTI64x2Zrmkz 1088815369U, // VINSERTI64x2Zrr 2163130633U, // VINSERTI64x2Zrrk 1357578505U, // VINSERTI64x2Zrrkz 375767610U, // VINSERTI64x4Zrm 1989395002U, // VINSERTI64x4Zrmk 1186202170U, // VINSERTI64x4Zrmkz 1088815674U, // VINSERTI64x4Zrr 2163130938U, // VINSERTI64x4Zrrk 1357578810U, // VINSERTI64x4Zrrkz 856024652U, // VINSERTPSZrm 1088824908U, // VINSERTPSZrr 856024652U, // VINSERTPSrm 1088824908U, // VINSERTPSrr 552954308U, // VLDDQUYrm 272836U, // VLDDQUrm 237909U, // VLDMXCSR 551840204U, // VMASKMOVDQU 551840204U, // VMASKMOVDQU64 1663372614U, // VMASKMOVPDYmr 812617030U, // VMASKMOVPDYrm 1126501702U, // VMASKMOVPDmr 811732294U, // VMASKMOVPDrm 1663379111U, // VMASKMOVPSYmr 812623527U, // VMASKMOVPSYrm 1126508199U, // VMASKMOVPSmr 811738791U, // VMASKMOVPSrm 812617042U, // VMAXCPDYrm 811650386U, // VMAXCPDYrr 811732306U, // VMAXCPDZ128rm 358763858U, // VMAXCPDZ128rmb 1433390418U, // VMAXCPDZ128rmbk 1164971346U, // VMAXCPDZ128rmbkz 86986066U, // VMAXCPDZ128rmk 890178898U, // VMAXCPDZ128rmkz 811650386U, // VMAXCPDZ128rr 87051602U, // VMAXCPDZ128rrk 890277202U, // VMAXCPDZ128rrkz 812617042U, // VMAXCPDZ256rm 360861010U, // VMAXCPDZ256rmb 1435487570U, // VMAXCPDZ256rmbk 1167068498U, // VMAXCPDZ256rmbkz 87084370U, // VMAXCPDZ256rmk 890309970U, // VMAXCPDZ256rmkz 811650386U, // VMAXCPDZ256rr 87051602U, // VMAXCPDZ256rrk 890277202U, // VMAXCPDZ256rrkz 812731730U, // VMAXCPDZrm 362958162U, // VMAXCPDZrmb 1437584722U, // VMAXCPDZrmbk 1169165650U, // VMAXCPDZrmbkz 87133522U, // VMAXCPDZrmk 890359122U, // VMAXCPDZrmkz 811650386U, // VMAXCPDZrr 87051602U, // VMAXCPDZrrk 890277202U, // VMAXCPDZrrkz 811732306U, // VMAXCPDrm 811650386U, // VMAXCPDrr 812623539U, // VMAXCPSYrm 811656883U, // VMAXCPSYrr 811738803U, // VMAXCPSZ128rm 360883891U, // VMAXCPSZ128rmb 1435690675U, // VMAXCPSZ128rmbk 1167271603U, // VMAXCPSZ128rmbkz 86992563U, // VMAXCPSZ128rmk 890185395U, // VMAXCPSZ128rmkz 811656883U, // VMAXCPSZ128rr 87058099U, // VMAXCPSZ128rrk 890283699U, // VMAXCPSZ128rrkz 812623539U, // VMAXCPSZ256rm 362981043U, // VMAXCPSZ256rmb 1437787827U, // VMAXCPSZ256rmbk 1169368755U, // VMAXCPSZ256rmbkz 87090867U, // VMAXCPSZ256rmk 890316467U, // VMAXCPSZ256rmkz 811656883U, // VMAXCPSZ256rr 87058099U, // VMAXCPSZ256rrk 890283699U, // VMAXCPSZ256rrkz 812738227U, // VMAXCPSZrm 365078195U, // VMAXCPSZrmb 1439884979U, // VMAXCPSZrmbk 1171465907U, // VMAXCPSZrmbkz 87140019U, // VMAXCPSZrmk 890365619U, // VMAXCPSZrmkz 811656883U, // VMAXCPSZrr 87058099U, // VMAXCPSZrrk 890283699U, // VMAXCPSZrrkz 811738803U, // VMAXCPSrm 811656883U, // VMAXCPSrr 283267094U, // VMAXCSDZrm 811651094U, // VMAXCSDZrr 283267094U, // VMAXCSDrm 811651094U, // VMAXCSDrr 283289837U, // VMAXCSSZrm 811657453U, // VMAXCSSZrr 283289837U, // VMAXCSSrm 811657453U, // VMAXCSSrr 812617042U, // VMAXPDYrm 811650386U, // VMAXPDYrr 811732306U, // VMAXPDZ128rm 358763858U, // VMAXPDZ128rmb 1433390418U, // VMAXPDZ128rmbk 1164971346U, // VMAXPDZ128rmbkz 86986066U, // VMAXPDZ128rmk 890178898U, // VMAXPDZ128rmkz 811650386U, // VMAXPDZ128rr 87051602U, // VMAXPDZ128rrk 890277202U, // VMAXPDZ128rrkz 812617042U, // VMAXPDZ256rm 360861010U, // VMAXPDZ256rmb 1435487570U, // VMAXPDZ256rmbk 1167068498U, // VMAXPDZ256rmbkz 87084370U, // VMAXPDZ256rmk 890309970U, // VMAXPDZ256rmkz 811650386U, // VMAXPDZ256rr 87051602U, // VMAXPDZ256rrk 890277202U, // VMAXPDZ256rrkz 812731730U, // VMAXPDZrm 362958162U, // VMAXPDZrmb 1437584722U, // VMAXPDZrmbk 1169165650U, // VMAXPDZrmbkz 87133522U, // VMAXPDZrmk 890359122U, // VMAXPDZrmkz 811650386U, // VMAXPDZrr 811660825U, // VMAXPDZrrb 87062041U, // VMAXPDZrrbk 890287641U, // VMAXPDZrrbkz 87051602U, // VMAXPDZrrk 890277202U, // VMAXPDZrrkz 811732306U, // VMAXPDrm 811650386U, // VMAXPDrr 812623539U, // VMAXPSYrm 811656883U, // VMAXPSYrr 811738803U, // VMAXPSZ128rm 360883891U, // VMAXPSZ128rmb 1435690675U, // VMAXPSZ128rmbk 1167271603U, // VMAXPSZ128rmbkz 86992563U, // VMAXPSZ128rmk 890185395U, // VMAXPSZ128rmkz 811656883U, // VMAXPSZ128rr 87058099U, // VMAXPSZ128rrk 890283699U, // VMAXPSZ128rrkz 812623539U, // VMAXPSZ256rm 362981043U, // VMAXPSZ256rmb 1437787827U, // VMAXPSZ256rmbk 1169368755U, // VMAXPSZ256rmbkz 87090867U, // VMAXPSZ256rmk 890316467U, // VMAXPSZ256rmkz 811656883U, // VMAXPSZ256rr 87058099U, // VMAXPSZ256rrk 890283699U, // VMAXPSZ256rrkz 812738227U, // VMAXPSZrm 365078195U, // VMAXPSZrmb 1439884979U, // VMAXPSZrmbk 1171465907U, // VMAXPSZrmbkz 87140019U, // VMAXPSZrmk 890365619U, // VMAXPSZrmkz 811656883U, // VMAXPSZrr 811661312U, // VMAXPSZrrb 87062528U, // VMAXPSZrrbk 890288128U, // VMAXPSZrrbkz 87058099U, // VMAXPSZrrk 890283699U, // VMAXPSZrrkz 811738803U, // VMAXPSrm 811656883U, // VMAXPSrr 283267094U, // VMAXSDZrm 283267094U, // VMAXSDZrm_Int 1357893654U, // VMAXSDZrm_Intk 1089474582U, // VMAXSDZrm_Intkz 811651094U, // VMAXSDZrr 811651094U, // VMAXSDZrr_Int 87052310U, // VMAXSDZrr_Intk 890277910U, // VMAXSDZrr_Intkz 811660960U, // VMAXSDZrrb_Int 87062176U, // VMAXSDZrrb_Intk 890287776U, // VMAXSDZrrb_Intkz 283267094U, // VMAXSDrm 283267094U, // VMAXSDrm_Int 811651094U, // VMAXSDrr 811651094U, // VMAXSDrr_Int 283289837U, // VMAXSSZrm 283289837U, // VMAXSSZrm_Int 1358096621U, // VMAXSSZrm_Intk 1089677549U, // VMAXSSZrm_Intkz 811657453U, // VMAXSSZrr 811657453U, // VMAXSSZrr_Int 87058669U, // VMAXSSZrr_Intk 890284269U, // VMAXSSZrr_Intkz 811661429U, // VMAXSSZrrb_Int 87062645U, // VMAXSSZrrb_Intk 890288245U, // VMAXSSZrrb_Intkz 283289837U, // VMAXSSrm 283289837U, // VMAXSSrm_Int 811657453U, // VMAXSSrr 811657453U, // VMAXSSrr_Int 15223U, // VMCALL 450821U, // VMCLEARm 14950U, // VMFUNC 812616784U, // VMINCPDYrm 811650128U, // VMINCPDYrr 811732048U, // VMINCPDZ128rm 358763600U, // VMINCPDZ128rmb 1433390160U, // VMINCPDZ128rmbk 1164971088U, // VMINCPDZ128rmbkz 86985808U, // VMINCPDZ128rmk 890178640U, // VMINCPDZ128rmkz 811650128U, // VMINCPDZ128rr 87051344U, // VMINCPDZ128rrk 890276944U, // VMINCPDZ128rrkz 812616784U, // VMINCPDZ256rm 360860752U, // VMINCPDZ256rmb 1435487312U, // VMINCPDZ256rmbk 1167068240U, // VMINCPDZ256rmbkz 87084112U, // VMINCPDZ256rmk 890309712U, // VMINCPDZ256rmkz 811650128U, // VMINCPDZ256rr 87051344U, // VMINCPDZ256rrk 890276944U, // VMINCPDZ256rrkz 812731472U, // VMINCPDZrm 362957904U, // VMINCPDZrmb 1437584464U, // VMINCPDZrmbk 1169165392U, // VMINCPDZrmbkz 87133264U, // VMINCPDZrmk 890358864U, // VMINCPDZrmkz 811650128U, // VMINCPDZrr 87051344U, // VMINCPDZrrk 890276944U, // VMINCPDZrrkz 811732048U, // VMINCPDrm 811650128U, // VMINCPDrr 812623233U, // VMINCPSYrm 811656577U, // VMINCPSYrr 811738497U, // VMINCPSZ128rm 360883585U, // VMINCPSZ128rmb 1435690369U, // VMINCPSZ128rmbk 1167271297U, // VMINCPSZ128rmbkz 86992257U, // VMINCPSZ128rmk 890185089U, // VMINCPSZ128rmkz 811656577U, // VMINCPSZ128rr 87057793U, // VMINCPSZ128rrk 890283393U, // VMINCPSZ128rrkz 812623233U, // VMINCPSZ256rm 362980737U, // VMINCPSZ256rmb 1437787521U, // VMINCPSZ256rmbk 1169368449U, // VMINCPSZ256rmbkz 87090561U, // VMINCPSZ256rmk 890316161U, // VMINCPSZ256rmkz 811656577U, // VMINCPSZ256rr 87057793U, // VMINCPSZ256rrk 890283393U, // VMINCPSZ256rrkz 812737921U, // VMINCPSZrm 365077889U, // VMINCPSZrmb 1439884673U, // VMINCPSZrmbk 1171465601U, // VMINCPSZrmbkz 87139713U, // VMINCPSZrmk 890365313U, // VMINCPSZrmkz 811656577U, // VMINCPSZrr 87057793U, // VMINCPSZrrk 890283393U, // VMINCPSZrrkz 811738497U, // VMINCPSrm 811656577U, // VMINCPSrr 283266927U, // VMINCSDZrm 811650927U, // VMINCSDZrr 283266927U, // VMINCSDrm 811650927U, // VMINCSDrr 283289720U, // VMINCSSZrm 811657336U, // VMINCSSZrr 283289720U, // VMINCSSrm 811657336U, // VMINCSSrr 812616784U, // VMINPDYrm 811650128U, // VMINPDYrr 811732048U, // VMINPDZ128rm 358763600U, // VMINPDZ128rmb 1433390160U, // VMINPDZ128rmbk 1164971088U, // VMINPDZ128rmbkz 86985808U, // VMINPDZ128rmk 890178640U, // VMINPDZ128rmkz 811650128U, // VMINPDZ128rr 87051344U, // VMINPDZ128rrk 890276944U, // VMINPDZ128rrkz 812616784U, // VMINPDZ256rm 360860752U, // VMINPDZ256rmb 1435487312U, // VMINPDZ256rmbk 1167068240U, // VMINPDZ256rmbkz 87084112U, // VMINPDZ256rmk 890309712U, // VMINPDZ256rmkz 811650128U, // VMINPDZ256rr 87051344U, // VMINPDZ256rrk 890276944U, // VMINPDZ256rrkz 812731472U, // VMINPDZrm 362957904U, // VMINPDZrmb 1437584464U, // VMINPDZrmbk 1169165392U, // VMINPDZrmbkz 87133264U, // VMINPDZrmk 890358864U, // VMINPDZrmkz 811650128U, // VMINPDZrr 811660792U, // VMINPDZrrb 87062008U, // VMINPDZrrbk 890287608U, // VMINPDZrrbkz 87051344U, // VMINPDZrrk 890276944U, // VMINPDZrrkz 811732048U, // VMINPDrm 811650128U, // VMINPDrr 812623233U, // VMINPSYrm 811656577U, // VMINPSYrr 811738497U, // VMINPSZ128rm 360883585U, // VMINPSZ128rmb 1435690369U, // VMINPSZ128rmbk 1167271297U, // VMINPSZ128rmbkz 86992257U, // VMINPSZ128rmk 890185089U, // VMINPSZ128rmkz 811656577U, // VMINPSZ128rr 87057793U, // VMINPSZ128rrk 890283393U, // VMINPSZ128rrkz 812623233U, // VMINPSZ256rm 362980737U, // VMINPSZ256rmb 1437787521U, // VMINPSZ256rmbk 1169368449U, // VMINPSZ256rmbkz 87090561U, // VMINPSZ256rmk 890316161U, // VMINPSZ256rmkz 811656577U, // VMINPSZ256rr 87057793U, // VMINPSZ256rrk 890283393U, // VMINPSZ256rrkz 812737921U, // VMINPSZrm 365077889U, // VMINPSZrmb 1439884673U, // VMINPSZrmbk 1171465601U, // VMINPSZrmbkz 87139713U, // VMINPSZrmk 890365313U, // VMINPSZrmkz 811656577U, // VMINPSZrr 811661279U, // VMINPSZrrb 87062495U, // VMINPSZrrbk 890288095U, // VMINPSZrrbkz 87057793U, // VMINPSZrrk 890283393U, // VMINPSZrrkz 811738497U, // VMINPSrm 811656577U, // VMINPSrr 283266927U, // VMINSDZrm 283266927U, // VMINSDZrm_Int 1357893487U, // VMINSDZrm_Intk 1089474415U, // VMINSDZrm_Intkz 811650927U, // VMINSDZrr 811650927U, // VMINSDZrr_Int 87052143U, // VMINSDZrr_Intk 890277743U, // VMINSDZrr_Intkz 811660927U, // VMINSDZrrb_Int 87062143U, // VMINSDZrrb_Intk 890287743U, // VMINSDZrrb_Intkz 283266927U, // VMINSDrm 283266927U, // VMINSDrm_Int 811650927U, // VMINSDrr 811650927U, // VMINSDrr_Int 283289720U, // VMINSSZrm 283289720U, // VMINSSZrm_Int 1358096504U, // VMINSSZrm_Intk 1089677432U, // VMINSSZrm_Intkz 811657336U, // VMINSSZrr 811657336U, // VMINSSZrr_Int 87058552U, // VMINSSZrr_Intk 890284152U, // VMINSSZrr_Intkz 811661396U, // VMINSSZrrb_Int 87062612U, // VMINSSZrrb_Intk 890288212U, // VMINSSZrrb_Intkz 283289720U, // VMINSSrm 283289720U, // VMINSSrm_Int 811657336U, // VMINSSrr 811657336U, // VMINSSrr_Int 15124U, // VMLAUNCH 16019U, // VMLOAD32 16080U, // VMLOAD64 15215U, // VMMCALL 551919746U, // VMOV64toPQIZrm 551837826U, // VMOV64toPQIZrr 551919746U, // VMOV64toPQIrm 551837826U, // VMOV64toPQIrr 551919746U, // VMOV64toSDZrm 551837826U, // VMOV64toSDZrr 551919746U, // VMOV64toSDrm 551837826U, // VMOV64toSDrr 148933282U, // VMOVAPDYmr 1346210U, // VMOVAPDYrm 551832226U, // VMOVAPDYrr 551832226U, // VMOVAPDYrr_REV 65047202U, // VMOVAPDZ128mr 3286567586U, // VMOVAPDZ128mrk 658082U, // VMOVAPDZ128rm 3230599842U, // VMOVAPDZ128rmk 3229747874U, // VMOVAPDZ128rmkz 551832226U, // VMOVAPDZ128rr 551832226U, // VMOVAPDZ128rr_REV 3230698146U, // VMOVAPDZ128rrk 3229665954U, // VMOVAPDZ128rrk_REV 3229665954U, // VMOVAPDZ128rrkz 3229665954U, // VMOVAPDZ128rrkz_REV 148933282U, // VMOVAPDZ256mr 3370453666U, // VMOVAPDZ256mrk 1346210U, // VMOVAPDZ256rm 3230730914U, // VMOVAPDZ256rmk 3230632610U, // VMOVAPDZ256rmkz 551832226U, // VMOVAPDZ256rr 551832226U, // VMOVAPDZ256rr_REV 3230698146U, // VMOVAPDZ256rrk 3229665954U, // VMOVAPDZ256rrk_REV 3229665954U, // VMOVAPDZ256rrkz 3229665954U, // VMOVAPDZ256rrkz_REV 151030434U, // VMOVAPDZmr 3372550818U, // VMOVAPDZmrk 1510050U, // VMOVAPDZrm 3230780066U, // VMOVAPDZrmk 3230747298U, // VMOVAPDZrmkz 551832226U, // VMOVAPDZrr 551832226U, // VMOVAPDZrr_REV 3230698146U, // VMOVAPDZrrk 3229665954U, // VMOVAPDZrrk_REV 3229665954U, // VMOVAPDZrrkz 3229665954U, // VMOVAPDZrrkz_REV 65047202U, // VMOVAPDmr 658082U, // VMOVAPDrm 551832226U, // VMOVAPDrr 551832226U, // VMOVAPDrr_REV 148939687U, // VMOVAPSYmr 1352615U, // VMOVAPSYrm 551838631U, // VMOVAPSYrr 551838631U, // VMOVAPSYrr_REV 65053607U, // VMOVAPSZ128mr 3286573991U, // VMOVAPSZ128mrk 664487U, // VMOVAPSZ128rm 3230606247U, // VMOVAPSZ128rmk 3229754279U, // VMOVAPSZ128rmkz 551838631U, // VMOVAPSZ128rr 551838631U, // VMOVAPSZ128rr_REV 3230704551U, // VMOVAPSZ128rrk 3229672359U, // VMOVAPSZ128rrk_REV 3229672359U, // VMOVAPSZ128rrkz 3229672359U, // VMOVAPSZ128rrkz_REV 148939687U, // VMOVAPSZ256mr 3370460071U, // VMOVAPSZ256mrk 1352615U, // VMOVAPSZ256rm 3230737319U, // VMOVAPSZ256rmk 3230639015U, // VMOVAPSZ256rmkz 551838631U, // VMOVAPSZ256rr 551838631U, // VMOVAPSZ256rr_REV 3230704551U, // VMOVAPSZ256rrk 3229672359U, // VMOVAPSZ256rrk_REV 3229672359U, // VMOVAPSZ256rrkz 3229672359U, // VMOVAPSZ256rrkz_REV 151036839U, // VMOVAPSZmr 3372557223U, // VMOVAPSZmrk 1516455U, // VMOVAPSZrm 3230786471U, // VMOVAPSZrmk 3230753703U, // VMOVAPSZrmkz 551838631U, // VMOVAPSZrr 551838631U, // VMOVAPSZrr_REV 3230704551U, // VMOVAPSZrrk 3229672359U, // VMOVAPSZrrk_REV 3229672359U, // VMOVAPSZrrkz 3229672359U, // VMOVAPSZrrkz_REV 65053607U, // VMOVAPSmr 664487U, // VMOVAPSrm 551838631U, // VMOVAPSrr 551838631U, // VMOVAPSrr_REV 1349887U, // VMOVDDUPYrm 551835903U, // VMOVDDUPYrr 552179967U, // VMOVDDUPZ128rm 552605951U, // VMOVDDUPZ128rmk 551704831U, // VMOVDDUPZ128rmkz 551835903U, // VMOVDDUPZ128rr 3230701823U, // VMOVDDUPZ128rrk 3229669631U, // VMOVDDUPZ128rrkz 1349887U, // VMOVDDUPZ256rm 3230734591U, // VMOVDDUPZ256rmk 3230636287U, // VMOVDDUPZ256rmkz 551835903U, // VMOVDDUPZ256rr 3230701823U, // VMOVDDUPZ256rrk 3229669631U, // VMOVDDUPZ256rrkz 1513727U, // VMOVDDUPZrm 3230783743U, // VMOVDDUPZrmk 3230750975U, // VMOVDDUPZrmkz 551835903U, // VMOVDDUPZrr 3230701823U, // VMOVDDUPZrrk 3229669631U, // VMOVDDUPZrrkz 552179967U, // VMOVDDUPrm 551835903U, // VMOVDDUPrr 551899369U, // VMOVDI2PDIZrm 551833833U, // VMOVDI2PDIZrr 551899369U, // VMOVDI2PDIrm 551833833U, // VMOVDI2PDIrr 551899369U, // VMOVDI2SSZrm 551833833U, // VMOVDI2SSZrr 551899369U, // VMOVDI2SSrm 551833833U, // VMOVDI2SSrr 33587280U, // VMOVDQA32Z128mr 3255107664U, // VMOVDQA32Z128mrk 262224U, // VMOVDQA32Z128rm 3230990416U, // VMOVDQA32Z128rmk 3229859920U, // VMOVDQA32Z128rmkz 551829584U, // VMOVDQA32Z128rr 551829584U, // VMOVDQA32Z128rr_REV 3230695504U, // VMOVDQA32Z128rrk 3229663312U, // VMOVDQA32Z128rrk_REV 3229663312U, // VMOVDQA32Z128rrkz 3229663312U, // VMOVDQA32Z128rrkz_REV 180387920U, // VMOVDQA32Z256mr 3401908304U, // VMOVDQA32Z256mrk 552943696U, // VMOVDQA32Z256rm 3231023184U, // VMOVDQA32Z256rmk 3230875728U, // VMOVDQA32Z256rmkz 551829584U, // VMOVDQA32Z256rr 551829584U, // VMOVDQA32Z256rr_REV 3230695504U, // VMOVDQA32Z256rrk 3229663312U, // VMOVDQA32Z256rrk_REV 3229663312U, // VMOVDQA32Z256rrkz 3229663312U, // VMOVDQA32Z256rrkz_REV 182485072U, // VMOVDQA32Zmr 3404005456U, // VMOVDQA32Zmrk 552435792U, // VMOVDQA32Zrm 3231088720U, // VMOVDQA32Zrmk 3230892112U, // VMOVDQA32Zrmkz 551829584U, // VMOVDQA32Zrr 551829584U, // VMOVDQA32Zrr_REV 3230695504U, // VMOVDQA32Zrrk 3229663312U, // VMOVDQA32Zrrk_REV 3229663312U, // VMOVDQA32Zrrkz 3229663312U, // VMOVDQA32Zrrkz_REV 33587496U, // VMOVDQA64Z128mr 3255107880U, // VMOVDQA64Z128mrk 262440U, // VMOVDQA64Z128rm 3230990632U, // VMOVDQA64Z128rmk 3229860136U, // VMOVDQA64Z128rmkz 551829800U, // VMOVDQA64Z128rr 551829800U, // VMOVDQA64Z128rr_REV 3230695720U, // VMOVDQA64Z128rrk 3229663528U, // VMOVDQA64Z128rrk_REV 3229663528U, // VMOVDQA64Z128rrkz 3229663528U, // VMOVDQA64Z128rrkz_REV 180388136U, // VMOVDQA64Z256mr 3401908520U, // VMOVDQA64Z256mrk 552943912U, // VMOVDQA64Z256rm 3231023400U, // VMOVDQA64Z256rmk 3230875944U, // VMOVDQA64Z256rmkz 551829800U, // VMOVDQA64Z256rr 551829800U, // VMOVDQA64Z256rr_REV 3230695720U, // VMOVDQA64Z256rrk 3229663528U, // VMOVDQA64Z256rrk_REV 3229663528U, // VMOVDQA64Z256rrkz 3229663528U, // VMOVDQA64Z256rrkz_REV 182485288U, // VMOVDQA64Zmr 3404005672U, // VMOVDQA64Zmrk 552436008U, // VMOVDQA64Zrm 3231088936U, // VMOVDQA64Zrmk 3230892328U, // VMOVDQA64Zrmkz 551829800U, // VMOVDQA64Zrr 551829800U, // VMOVDQA64Zrr_REV 3230695720U, // VMOVDQA64Zrrk 3229663528U, // VMOVDQA64Zrrk_REV 3229663528U, // VMOVDQA64Zrrkz 3229663528U, // VMOVDQA64Zrrkz_REV 180388679U, // VMOVDQAYmr 552944455U, // VMOVDQAYrm 551830343U, // VMOVDQAYrr 551830343U, // VMOVDQAYrr_REV 33588039U, // VMOVDQAmr 262983U, // VMOVDQArm 551830343U, // VMOVDQArr 551830343U, // VMOVDQArr_REV 33587801U, // VMOVDQU16Z128mr 3255108185U, // VMOVDQU16Z128mrk 262745U, // VMOVDQU16Z128rm 3230990937U, // VMOVDQU16Z128rmk 3229860441U, // VMOVDQU16Z128rmkz 551830105U, // VMOVDQU16Z128rr 551830105U, // VMOVDQU16Z128rr_REV 3230696025U, // VMOVDQU16Z128rrk 3229663833U, // VMOVDQU16Z128rrk_REV 3229663833U, // VMOVDQU16Z128rrkz 3229663833U, // VMOVDQU16Z128rrkz_REV 180388441U, // VMOVDQU16Z256mr 3401908825U, // VMOVDQU16Z256mrk 552944217U, // VMOVDQU16Z256rm 3231023705U, // VMOVDQU16Z256rmk 3230876249U, // VMOVDQU16Z256rmkz 551830105U, // VMOVDQU16Z256rr 551830105U, // VMOVDQU16Z256rr_REV 3230696025U, // VMOVDQU16Z256rrk 3229663833U, // VMOVDQU16Z256rrk_REV 3229663833U, // VMOVDQU16Z256rrkz 3229663833U, // VMOVDQU16Z256rrkz_REV 182485593U, // VMOVDQU16Zmr 3404005977U, // VMOVDQU16Zmrk 552436313U, // VMOVDQU16Zrm 3231089241U, // VMOVDQU16Zrmk 3230892633U, // VMOVDQU16Zrmkz 551830105U, // VMOVDQU16Zrr 551830105U, // VMOVDQU16Zrr_REV 3230696025U, // VMOVDQU16Zrrk 3229663833U, // VMOVDQU16Zrrk_REV 3229663833U, // VMOVDQU16Zrrkz 3229663833U, // VMOVDQU16Zrrkz_REV 33587291U, // VMOVDQU32Z128mr 3255107675U, // VMOVDQU32Z128mrk 262235U, // VMOVDQU32Z128rm 3230990427U, // VMOVDQU32Z128rmk 3229859931U, // VMOVDQU32Z128rmkz 551829595U, // VMOVDQU32Z128rr 551829595U, // VMOVDQU32Z128rr_REV 3230695515U, // VMOVDQU32Z128rrk 3229663323U, // VMOVDQU32Z128rrk_REV 3229663323U, // VMOVDQU32Z128rrkz 3229663323U, // VMOVDQU32Z128rrkz_REV 180387931U, // VMOVDQU32Z256mr 3401908315U, // VMOVDQU32Z256mrk 552943707U, // VMOVDQU32Z256rm 3231023195U, // VMOVDQU32Z256rmk 3230875739U, // VMOVDQU32Z256rmkz 551829595U, // VMOVDQU32Z256rr 551829595U, // VMOVDQU32Z256rr_REV 3230695515U, // VMOVDQU32Z256rrk 3229663323U, // VMOVDQU32Z256rrk_REV 3229663323U, // VMOVDQU32Z256rrkz 3229663323U, // VMOVDQU32Z256rrkz_REV 182485083U, // VMOVDQU32Zmr 3404005467U, // VMOVDQU32Zmrk 552435803U, // VMOVDQU32Zrm 3231088731U, // VMOVDQU32Zrmk 3230892123U, // VMOVDQU32Zrmkz 551829595U, // VMOVDQU32Zrr 551829595U, // VMOVDQU32Zrr_REV 3230695515U, // VMOVDQU32Zrrk 3229663323U, // VMOVDQU32Zrrk_REV 3229663323U, // VMOVDQU32Zrrkz 3229663323U, // VMOVDQU32Zrrkz_REV 33587571U, // VMOVDQU64Z128mr 3255107955U, // VMOVDQU64Z128mrk 262515U, // VMOVDQU64Z128rm 3230990707U, // VMOVDQU64Z128rmk 3229860211U, // VMOVDQU64Z128rmkz 551829875U, // VMOVDQU64Z128rr 551829875U, // VMOVDQU64Z128rr_REV 3230695795U, // VMOVDQU64Z128rrk 3229663603U, // VMOVDQU64Z128rrk_REV 3229663603U, // VMOVDQU64Z128rrkz 3229663603U, // VMOVDQU64Z128rrkz_REV 180388211U, // VMOVDQU64Z256mr 3401908595U, // VMOVDQU64Z256mrk 552943987U, // VMOVDQU64Z256rm 3231023475U, // VMOVDQU64Z256rmk 3230876019U, // VMOVDQU64Z256rmkz 551829875U, // VMOVDQU64Z256rr 551829875U, // VMOVDQU64Z256rr_REV 3230695795U, // VMOVDQU64Z256rrk 3229663603U, // VMOVDQU64Z256rrk_REV 3229663603U, // VMOVDQU64Z256rrkz 3229663603U, // VMOVDQU64Z256rrkz_REV 182485363U, // VMOVDQU64Zmr 3404005747U, // VMOVDQU64Zmrk 552436083U, // VMOVDQU64Zrm 3231089011U, // VMOVDQU64Zrmk 3230892403U, // VMOVDQU64Zrmkz 551829875U, // VMOVDQU64Zrr 551829875U, // VMOVDQU64Zrr_REV 3230695795U, // VMOVDQU64Zrrk 3229663603U, // VMOVDQU64Zrrk_REV 3229663603U, // VMOVDQU64Zrrkz 3229663603U, // VMOVDQU64Zrrkz_REV 33587922U, // VMOVDQU8Z128mr 3255108306U, // VMOVDQU8Z128mrk 262866U, // VMOVDQU8Z128rm 3230991058U, // VMOVDQU8Z128rmk 3229860562U, // VMOVDQU8Z128rmkz 551830226U, // VMOVDQU8Z128rr 551830226U, // VMOVDQU8Z128rr_REV 3230696146U, // VMOVDQU8Z128rrk 3229663954U, // VMOVDQU8Z128rrk_REV 3229663954U, // VMOVDQU8Z128rrkz 3229663954U, // VMOVDQU8Z128rrkz_REV 180388562U, // VMOVDQU8Z256mr 3401908946U, // VMOVDQU8Z256mrk 552944338U, // VMOVDQU8Z256rm 3231023826U, // VMOVDQU8Z256rmk 3230876370U, // VMOVDQU8Z256rmkz 551830226U, // VMOVDQU8Z256rr 551830226U, // VMOVDQU8Z256rr_REV 3230696146U, // VMOVDQU8Z256rrk 3229663954U, // VMOVDQU8Z256rrk_REV 3229663954U, // VMOVDQU8Z256rrkz 3229663954U, // VMOVDQU8Z256rrkz_REV 182485714U, // VMOVDQU8Zmr 3404006098U, // VMOVDQU8Zmrk 552436434U, // VMOVDQU8Zrm 3231089362U, // VMOVDQU8Zrmk 3230892754U, // VMOVDQU8Zrmkz 551830226U, // VMOVDQU8Zrr 551830226U, // VMOVDQU8Zrr_REV 3230696146U, // VMOVDQU8Zrrk 3229663954U, // VMOVDQU8Zrrk_REV 3229663954U, // VMOVDQU8Zrrkz 3229663954U, // VMOVDQU8Zrrkz_REV 180398553U, // VMOVDQUYmr 552954329U, // VMOVDQUYrm 551840217U, // VMOVDQUYrr 551840217U, // VMOVDQUYrr_REV 33597913U, // VMOVDQUmr 272857U, // VMOVDQUrm 551840217U, // VMOVDQUrr 551840217U, // VMOVDQUrr_REV 811656469U, // VMOVHLPSZrr 811656469U, // VMOVHLPSrr 67144675U, // VMOVHPDZ128mr 283266019U, // VMOVHPDZ128rm 67144675U, // VMOVHPDmr 283266019U, // VMOVHPDrm 67151105U, // VMOVHPSZ128mr 283272449U, // VMOVHPSZ128rm 67151105U, // VMOVHPSmr 283272449U, // VMOVHPSrm 811656439U, // VMOVLHPSZrr 811656439U, // VMOVLHPSrr 67144725U, // VMOVLPDZ128mr 283266069U, // VMOVLPDZ128rm 67144725U, // VMOVLPDmr 283266069U, // VMOVLPDrm 67151165U, // VMOVLPSZ128mr 283272509U, // VMOVLPSZ128rm 67151165U, // VMOVLPSmr 283272509U, // VMOVLPSrm 551832556U, // VMOVMSKPDYrr 551832556U, // VMOVMSKPDrr 551838986U, // VMOVMSKPSYrr 551838986U, // VMOVMSKPSrr 552944444U, // VMOVNTDQAYrm 262972U, // VMOVNTDQAZ128rm 552944444U, // VMOVNTDQAZ256rm 552436540U, // VMOVNTDQAZrm 262972U, // VMOVNTDQArm 180394832U, // VMOVNTDQYmr 33594192U, // VMOVNTDQZ128mr 180394832U, // VMOVNTDQZ256mr 182491984U, // VMOVNTDQZmr 33594192U, // VMOVNTDQmr 148933902U, // VMOVNTPDYmr 65047822U, // VMOVNTPDZ128mr 148933902U, // VMOVNTPDZ256mr 151031054U, // VMOVNTPDZmr 65047822U, // VMOVNTPDmr 148940354U, // VMOVNTPSYmr 65054274U, // VMOVNTPSZ128mr 148940354U, // VMOVNTPSZ256mr 151037506U, // VMOVNTPSZmr 65054274U, // VMOVNTPSmr 12620009U, // VMOVPDI2DIZmr 551833833U, // VMOVPDI2DIZrr 12620009U, // VMOVPDI2DImr 551833833U, // VMOVPDI2DIrr 18915458U, // VMOVPQI2QIZmr 551837826U, // VMOVPQI2QIZrr 18915458U, // VMOVPQI2QImr 551837826U, // VMOVPQI2QIrr 18915458U, // VMOVPQIto64Zmr 551837826U, // VMOVPQIto64Zrr 18915458U, // VMOVPQIto64mr 551837826U, // VMOVPQIto64rr 551919746U, // VMOVQI2PQIZrm 551919746U, // VMOVQI2PQIrm 67145733U, // VMOVSDZmr 3288666117U, // VMOVSDZmrk 552177669U, // VMOVSDZrm 552603653U, // VMOVSDZrmk 551702533U, // VMOVSDZrmkz 811651077U, // VMOVSDZrr 811651077U, // VMOVSDZrr_REV 87052293U, // VMOVSDZrrk 87052293U, // VMOVSDZrrk_REV 890277893U, // VMOVSDZrrkz 890277893U, // VMOVSDZrrkz_REV 67145733U, // VMOVSDmr 552177669U, // VMOVSDrm 811651077U, // VMOVSDrr 811651077U, // VMOVSDrr_REV 18915458U, // VMOVSDto64Zmr 551837826U, // VMOVSDto64Zrr 18915458U, // VMOVSDto64mr 551837826U, // VMOVSDto64rr 1349897U, // VMOVSHDUPYrm 551835913U, // VMOVSHDUPYrr 661769U, // VMOVSHDUPZ128rm 3230603529U, // VMOVSHDUPZ128rmk 3229751561U, // VMOVSHDUPZ128rmkz 551835913U, // VMOVSHDUPZ128rr 3230701833U, // VMOVSHDUPZ128rrk 3229669641U, // VMOVSHDUPZ128rrkz 1349897U, // VMOVSHDUPZ256rm 3230734601U, // VMOVSHDUPZ256rmk 3230636297U, // VMOVSHDUPZ256rmkz 551835913U, // VMOVSHDUPZ256rr 3230701833U, // VMOVSHDUPZ256rrk 3229669641U, // VMOVSHDUPZ256rrkz 1513737U, // VMOVSHDUPZrm 3230783753U, // VMOVSHDUPZrmk 3230750985U, // VMOVSHDUPZrmkz 551835913U, // VMOVSHDUPZrr 3230701833U, // VMOVSHDUPZrrk 3229669641U, // VMOVSHDUPZrrkz 661769U, // VMOVSHDUPrm 551835913U, // VMOVSHDUPrr 1349908U, // VMOVSLDUPYrm 551835924U, // VMOVSLDUPYrr 661780U, // VMOVSLDUPZ128rm 3230603540U, // VMOVSLDUPZ128rmk 3229751572U, // VMOVSLDUPZ128rmkz 551835924U, // VMOVSLDUPZ128rr 3230701844U, // VMOVSLDUPZ128rrk 3229669652U, // VMOVSLDUPZ128rrkz 1349908U, // VMOVSLDUPZ256rm 3230734612U, // VMOVSLDUPZ256rmk 3230636308U, // VMOVSLDUPZ256rmkz 551835924U, // VMOVSLDUPZ256rr 3230701844U, // VMOVSLDUPZ256rrk 3229669652U, // VMOVSLDUPZ256rrkz 1513748U, // VMOVSLDUPZrm 3230783764U, // VMOVSLDUPZrmk 3230750996U, // VMOVSLDUPZrmkz 551835924U, // VMOVSLDUPZrr 3230701844U, // VMOVSLDUPZrrk 3229669652U, // VMOVSLDUPZrrkz 661780U, // VMOVSLDUPrm 551835924U, // VMOVSLDUPrr 12620009U, // VMOVSS2DIZmr 551833833U, // VMOVSS2DIZrr 12620009U, // VMOVSS2DImr 551833833U, // VMOVSS2DIrr 69249253U, // VMOVSSZmr 3290769637U, // VMOVSSZmrk 552200421U, // VMOVSSZrm 552806629U, // VMOVSSZrmk 551725285U, // VMOVSSZrmkz 811657445U, // VMOVSSZrr 811657445U, // VMOVSSZrr_REV 87058661U, // VMOVSSZrrk 87058661U, // VMOVSSZrrk_REV 890284261U, // VMOVSSZrrkz 890284261U, // VMOVSSZrrkz_REV 69249253U, // VMOVSSmr 552200421U, // VMOVSSrm 811657445U, // VMOVSSrr 811657445U, // VMOVSSrr_REV 148933930U, // VMOVUPDYmr 1346858U, // VMOVUPDYrm 551832874U, // VMOVUPDYrr 551832874U, // VMOVUPDYrr_REV 65047850U, // VMOVUPDZ128mr 3286568234U, // VMOVUPDZ128mrk 658730U, // VMOVUPDZ128rm 3230600490U, // VMOVUPDZ128rmk 3229748522U, // VMOVUPDZ128rmkz 551832874U, // VMOVUPDZ128rr 551832874U, // VMOVUPDZ128rr_REV 3230698794U, // VMOVUPDZ128rrk 3229666602U, // VMOVUPDZ128rrk_REV 3229666602U, // VMOVUPDZ128rrkz 3229666602U, // VMOVUPDZ128rrkz_REV 148933930U, // VMOVUPDZ256mr 3370454314U, // VMOVUPDZ256mrk 1346858U, // VMOVUPDZ256rm 3230731562U, // VMOVUPDZ256rmk 3230633258U, // VMOVUPDZ256rmkz 551832874U, // VMOVUPDZ256rr 551832874U, // VMOVUPDZ256rr_REV 3230698794U, // VMOVUPDZ256rrk 3229666602U, // VMOVUPDZ256rrk_REV 3229666602U, // VMOVUPDZ256rrkz 3229666602U, // VMOVUPDZ256rrkz_REV 151031082U, // VMOVUPDZmr 3372551466U, // VMOVUPDZmrk 1510698U, // VMOVUPDZrm 3230780714U, // VMOVUPDZrmk 3230747946U, // VMOVUPDZrmkz 551832874U, // VMOVUPDZrr 551832874U, // VMOVUPDZrr_REV 3230698794U, // VMOVUPDZrrk 3229666602U, // VMOVUPDZrrk_REV 3229666602U, // VMOVUPDZrrkz 3229666602U, // VMOVUPDZrrkz_REV 65047850U, // VMOVUPDmr 658730U, // VMOVUPDrm 551832874U, // VMOVUPDrr 551832874U, // VMOVUPDrr_REV 148940427U, // VMOVUPSYmr 1353355U, // VMOVUPSYrm 551839371U, // VMOVUPSYrr 551839371U, // VMOVUPSYrr_REV 65054347U, // VMOVUPSZ128mr 3286574731U, // VMOVUPSZ128mrk 665227U, // VMOVUPSZ128rm 3230606987U, // VMOVUPSZ128rmk 3229755019U, // VMOVUPSZ128rmkz 551839371U, // VMOVUPSZ128rr 551839371U, // VMOVUPSZ128rr_REV 3230705291U, // VMOVUPSZ128rrk 3229673099U, // VMOVUPSZ128rrk_REV 3229673099U, // VMOVUPSZ128rrkz 3229673099U, // VMOVUPSZ128rrkz_REV 148940427U, // VMOVUPSZ256mr 3370460811U, // VMOVUPSZ256mrk 1353355U, // VMOVUPSZ256rm 3230738059U, // VMOVUPSZ256rmk 3230639755U, // VMOVUPSZ256rmkz 551839371U, // VMOVUPSZ256rr 551839371U, // VMOVUPSZ256rr_REV 3230705291U, // VMOVUPSZ256rrk 3229673099U, // VMOVUPSZ256rrk_REV 3229673099U, // VMOVUPSZ256rrkz 3229673099U, // VMOVUPSZ256rrkz_REV 151037579U, // VMOVUPSZmr 3372557963U, // VMOVUPSZmrk 1517195U, // VMOVUPSZrm 3230787211U, // VMOVUPSZrmk 3230754443U, // VMOVUPSZrmkz 551839371U, // VMOVUPSZrr 551839371U, // VMOVUPSZrr_REV 3230705291U, // VMOVUPSZrrk 3229673099U, // VMOVUPSZrrk_REV 3229673099U, // VMOVUPSZrrkz 3229673099U, // VMOVUPSZrrkz_REV 65054347U, // VMOVUPSmr 665227U, // VMOVUPSrm 551839371U, // VMOVUPSrr 551839371U, // VMOVUPSrr_REV 551837826U, // VMOVZPQILo2PQIZrr 551837826U, // VMOVZPQILo2PQIrr 375777904U, // VMPSADBWYrmi 1088825968U, // VMPSADBWYrri 325446256U, // VMPSADBWrmi 1088825968U, // VMPSADBWrri 444562U, // VMPTRLDm 453035U, // VMPTRSTm 12620766U, // VMREAD32mr 551834590U, // VMREAD32rr 18913853U, // VMREAD64mr 551836221U, // VMREAD64rr 15047U, // VMRESUME 16043U, // VMRUN32 16104U, // VMRUN64 16031U, // VMSAVE32 16092U, // VMSAVE64 812616717U, // VMULPDYrm 811650061U, // VMULPDYrr 811731981U, // VMULPDZ128rm 358763533U, // VMULPDZ128rmb 1433390093U, // VMULPDZ128rmbk 1164971021U, // VMULPDZ128rmbkz 86985741U, // VMULPDZ128rmk 890178573U, // VMULPDZ128rmkz 811650061U, // VMULPDZ128rr 87051277U, // VMULPDZ128rrk 890276877U, // VMULPDZ128rrkz 812616717U, // VMULPDZ256rm 360860685U, // VMULPDZ256rmb 1435487245U, // VMULPDZ256rmbk 1167068173U, // VMULPDZ256rmbkz 87084045U, // VMULPDZ256rmk 890309645U, // VMULPDZ256rmkz 811650061U, // VMULPDZ256rr 87051277U, // VMULPDZ256rrk 890276877U, // VMULPDZ256rrkz 812731405U, // VMULPDZrm 362957837U, // VMULPDZrmb 1437584397U, // VMULPDZrmbk 1169165325U, // VMULPDZrmbkz 87133197U, // VMULPDZrmk 890358797U, // VMULPDZrmkz 811650061U, // VMULPDZrr 812780557U, // VMULPDZrrb 87182349U, // VMULPDZrrbk 890407949U, // VMULPDZrrbkz 87051277U, // VMULPDZrrk 890276877U, // VMULPDZrrkz 811731981U, // VMULPDrm 811650061U, // VMULPDrr 812623157U, // VMULPSYrm 811656501U, // VMULPSYrr 811738421U, // VMULPSZ128rm 360883509U, // VMULPSZ128rmb 1435690293U, // VMULPSZ128rmbk 1167271221U, // VMULPSZ128rmbkz 86992181U, // VMULPSZ128rmk 890185013U, // VMULPSZ128rmkz 811656501U, // VMULPSZ128rr 87057717U, // VMULPSZ128rrk 890283317U, // VMULPSZ128rrkz 812623157U, // VMULPSZ256rm 362980661U, // VMULPSZ256rmb 1437787445U, // VMULPSZ256rmbk 1169368373U, // VMULPSZ256rmbkz 87090485U, // VMULPSZ256rmk 890316085U, // VMULPSZ256rmkz 811656501U, // VMULPSZ256rr 87057717U, // VMULPSZ256rrk 890283317U, // VMULPSZ256rrkz 812737845U, // VMULPSZrm 365077813U, // VMULPSZrmb 1439884597U, // VMULPSZrmbk 1171465525U, // VMULPSZrmbkz 87139637U, // VMULPSZrmk 890365237U, // VMULPSZrmkz 811656501U, // VMULPSZrr 812786997U, // VMULPSZrrb 87188789U, // VMULPSZrrbk 890414389U, // VMULPSZrrbkz 87057717U, // VMULPSZrrk 890283317U, // VMULPSZrrkz 811738421U, // VMULPSrm 811656501U, // VMULPSrr 283266897U, // VMULSDZrm 283266897U, // VMULSDZrm_Int 1357893457U, // VMULSDZrm_Intk 1089474385U, // VMULSDZrm_Intkz 811650897U, // VMULSDZrr 811650897U, // VMULSDZrr_Int 87052113U, // VMULSDZrr_Intk 890277713U, // VMULSDZrr_Intkz 812781393U, // VMULSDZrrb_Int 87183185U, // VMULSDZrrb_Intk 890408785U, // VMULSDZrrb_Intkz 283266897U, // VMULSDrm 283266897U, // VMULSDrm_Int 811650897U, // VMULSDrr 811650897U, // VMULSDrr_Int 283289699U, // VMULSSZrm 283289699U, // VMULSSZrm_Int 1358096483U, // VMULSSZrm_Intk 1089677411U, // VMULSSZrm_Intkz 811657315U, // VMULSSZrr 811657315U, // VMULSSZrr_Int 87058531U, // VMULSSZrr_Intk 890284131U, // VMULSSZrr_Intkz 812787811U, // VMULSSZrrb_Int 87189603U, // VMULSSZrrb_Intk 890415203U, // VMULSSZrrb_Intkz 283289699U, // VMULSSrm 283289699U, // VMULSSrm_Int 811657315U, // VMULSSrr 811657315U, // VMULSSrr_Int 551900316U, // VMWRITE32rm 551834780U, // VMWRITE32rr 551918617U, // VMWRITE64rm 551836697U, // VMWRITE64rr 15099U, // VMXOFF 448617U, // VMXON 812616905U, // VORPDYrm 811650249U, // VORPDYrr 811732169U, // VORPDZ128rm 358763721U, // VORPDZ128rmb 1433390281U, // VORPDZ128rmbk 1164971209U, // VORPDZ128rmbkz 86985929U, // VORPDZ128rmk 890178761U, // VORPDZ128rmkz 811650249U, // VORPDZ128rr 87051465U, // VORPDZ128rrk 890277065U, // VORPDZ128rrkz 812616905U, // VORPDZ256rm 360860873U, // VORPDZ256rmb 1435487433U, // VORPDZ256rmbk 1167068361U, // VORPDZ256rmbkz 87084233U, // VORPDZ256rmk 890309833U, // VORPDZ256rmkz 811650249U, // VORPDZ256rr 87051465U, // VORPDZ256rrk 890277065U, // VORPDZ256rrkz 812731593U, // VORPDZrm 362958025U, // VORPDZrmb 1437584585U, // VORPDZrmbk 1169165513U, // VORPDZrmbkz 87133385U, // VORPDZrmk 890358985U, // VORPDZrmkz 811650249U, // VORPDZrr 87051465U, // VORPDZrrk 890277065U, // VORPDZrrkz 811732169U, // VORPDrm 811650249U, // VORPDrr 812623362U, // VORPSYrm 811656706U, // VORPSYrr 811738626U, // VORPSZ128rm 360883714U, // VORPSZ128rmb 1435690498U, // VORPSZ128rmbk 1167271426U, // VORPSZ128rmbkz 86992386U, // VORPSZ128rmk 890185218U, // VORPSZ128rmkz 811656706U, // VORPSZ128rr 87057922U, // VORPSZ128rrk 890283522U, // VORPSZ128rrkz 812623362U, // VORPSZ256rm 362980866U, // VORPSZ256rmb 1437787650U, // VORPSZ256rmbk 1169368578U, // VORPSZ256rmbkz 87090690U, // VORPSZ256rmk 890316290U, // VORPSZ256rmkz 811656706U, // VORPSZ256rr 87057922U, // VORPSZ256rrk 890283522U, // VORPSZ256rrkz 812738050U, // VORPSZrm 365078018U, // VORPSZrmb 1439884802U, // VORPSZrmbk 1171465730U, // VORPSZrmbkz 87139842U, // VORPSZrmk 890365442U, // VORPSZrmkz 811656706U, // VORPSZrr 87057922U, // VORPSZrrk 890283522U, // VORPSZrrkz 811738626U, // VORPSrm 811656706U, // VORPSrr 890184091U, // VP4DPWSSDSrm 86991259U, // VP4DPWSSDSrmk 89088411U, // VP4DPWSSDSrmkz 890179506U, // VP4DPWSSDrm 86986674U, // VP4DPWSSDrmk 89083826U, // VP4DPWSSDrmkz 552945056U, // VPABSBYrm 551830944U, // VPABSBYrr 263584U, // VPABSBZ128rm 3230991776U, // VPABSBZ128rmk 3229861280U, // VPABSBZ128rmkz 551830944U, // VPABSBZ128rr 3230696864U, // VPABSBZ128rrk 3229664672U, // VPABSBZ128rrkz 552945056U, // VPABSBZ256rm 3231024544U, // VPABSBZ256rmk 3230877088U, // VPABSBZ256rmkz 551830944U, // VPABSBZ256rr 3230696864U, // VPABSBZ256rrk 3229664672U, // VPABSBZ256rrkz 552437152U, // VPABSBZrm 3231090080U, // VPABSBZrmk 3230893472U, // VPABSBZrmkz 551830944U, // VPABSBZrr 3230696864U, // VPABSBZrrk 3229664672U, // VPABSBZrrkz 263584U, // VPABSBrm 551830944U, // VPABSBrr 552947397U, // VPABSDYrm 551833285U, // VPABSDYrr 265925U, // VPABSDZ128rm 629493445U, // VPABSDZ128rmb 630607557U, // VPABSDZ128rmbk 629231301U, // VPABSDZ128rmbkz 3230994117U, // VPABSDZ128rmk 3229863621U, // VPABSDZ128rmkz 551833285U, // VPABSDZ128rr 3230699205U, // VPABSDZ128rrk 3229667013U, // VPABSDZ128rrkz 552947397U, // VPABSDZ256rm 631590597U, // VPABSDZ256rmb 632704709U, // VPABSDZ256rmbk 631328453U, // VPABSDZ256rmbkz 3231026885U, // VPABSDZ256rmk 3230879429U, // VPABSDZ256rmkz 551833285U, // VPABSDZ256rr 3230699205U, // VPABSDZ256rrk 3229667013U, // VPABSDZ256rrkz 552439493U, // VPABSDZrm 633687749U, // VPABSDZrmb 634801861U, // VPABSDZrmbk 633425605U, // VPABSDZrmbkz 3231092421U, // VPABSDZrmk 3230895813U, // VPABSDZrmkz 551833285U, // VPABSDZrr 3230699205U, // VPABSDZrrk 3229667013U, // VPABSDZrrkz 265925U, // VPABSDrm 551833285U, // VPABSDrr 270016U, // VPABSQZ128rm 627416768U, // VPABSQZ128rmb 628416192U, // VPABSQZ128rmbk 627154624U, // VPABSQZ128rmbkz 3230998208U, // VPABSQZ128rmk 3229867712U, // VPABSQZ128rmkz 551837376U, // VPABSQZ128rr 3230703296U, // VPABSQZ128rrk 3229671104U, // VPABSQZ128rrkz 552951488U, // VPABSQZ256rm 629513920U, // VPABSQZ256rmb 630513344U, // VPABSQZ256rmbk 629251776U, // VPABSQZ256rmbkz 3231030976U, // VPABSQZ256rmk 3230883520U, // VPABSQZ256rmkz 551837376U, // VPABSQZ256rr 3230703296U, // VPABSQZ256rrk 3229671104U, // VPABSQZ256rrkz 552443584U, // VPABSQZrm 631611072U, // VPABSQZrmb 632610496U, // VPABSQZrmbk 631348928U, // VPABSQZrmbkz 3231096512U, // VPABSQZrmk 3230899904U, // VPABSQZrmkz 551837376U, // VPABSQZrr 3230703296U, // VPABSQZrrk 3229671104U, // VPABSQZrrkz 552955357U, // VPABSWYrm 551841245U, // VPABSWYrr 273885U, // VPABSWZ128rm 3231002077U, // VPABSWZ128rmk 3229871581U, // VPABSWZ128rmkz 551841245U, // VPABSWZ128rr 3230707165U, // VPABSWZ128rrk 3229674973U, // VPABSWZ128rrkz 552955357U, // VPABSWZ256rm 3231034845U, // VPABSWZ256rmk 3230887389U, // VPABSWZ256rmkz 551841245U, // VPABSWZ256rr 3230707165U, // VPABSWZ256rrk 3229674973U, // VPABSWZ256rrkz 552447453U, // VPABSWZrm 3231100381U, // VPABSWZrmk 3230903773U, // VPABSWZrmkz 551841245U, // VPABSWZrr 3230707165U, // VPABSWZrrk 3229674973U, // VPABSWZrrkz 273885U, // VPABSWrm 551841245U, // VPABSWrr 812870527U, // VPACKSSDWYrm 811658111U, // VPACKSSDWYrr 811854719U, // VPACKSSDWZ128rm 360803199U, // VPACKSSDWZ128rmb 1436068735U, // VPACKSSDWZ128rmbk 1167485823U, // VPACKSSDWZ128rmbkz 985115519U, // VPACKSSDWZ128rmk 890579839U, // VPACKSSDWZ128rmkz 811658111U, // VPACKSSDWZ128rr 87059327U, // VPACKSSDWZ128rrk 890284927U, // VPACKSSDWZ128rrkz 812870527U, // VPACKSSDWZ256rm 362900351U, // VPACKSSDWZ256rmb 1438165887U, // VPACKSSDWZ256rmbk 1169582975U, // VPACKSSDWZ256rmbkz 985131903U, // VPACKSSDWZ256rmk 890612607U, // VPACKSSDWZ256rmkz 811658111U, // VPACKSSDWZ256rr 87059327U, // VPACKSSDWZ256rrk 890284927U, // VPACKSSDWZ256rrkz 812886911U, // VPACKSSDWZrm 364997503U, // VPACKSSDWZrmb 1440263039U, // VPACKSSDWZrmbk 1171680127U, // VPACKSSDWZrmbkz 985148287U, // VPACKSSDWZrmk 890678143U, // VPACKSSDWZrmkz 811658111U, // VPACKSSDWZrr 87059327U, // VPACKSSDWZrrk 890284927U, // VPACKSSDWZrrkz 811854719U, // VPACKSSDWrm 811658111U, // VPACKSSDWrr 812861110U, // VPACKSSWBYrm 811648694U, // VPACKSSWBYrr 811845302U, // VPACKSSWBZ128rm 985106102U, // VPACKSSWBZ128rmk 890570422U, // VPACKSSWBZ128rmkz 811648694U, // VPACKSSWBZ128rr 87049910U, // VPACKSSWBZ128rrk 890275510U, // VPACKSSWBZ128rrkz 812861110U, // VPACKSSWBZ256rm 985122486U, // VPACKSSWBZ256rmk 890603190U, // VPACKSSWBZ256rmkz 811648694U, // VPACKSSWBZ256rr 87049910U, // VPACKSSWBZ256rrk 890275510U, // VPACKSSWBZ256rrkz 812877494U, // VPACKSSWBZrm 985138870U, // VPACKSSWBZrmk 890668726U, // VPACKSSWBZrmkz 811648694U, // VPACKSSWBZrr 87049910U, // VPACKSSWBZrrk 890275510U, // VPACKSSWBZrrkz 811845302U, // VPACKSSWBrm 811648694U, // VPACKSSWBrr 812870538U, // VPACKUSDWYrm 811658122U, // VPACKUSDWYrr 811854730U, // VPACKUSDWZ128rm 360803210U, // VPACKUSDWZ128rmb 1436068746U, // VPACKUSDWZ128rmbk 1167485834U, // VPACKUSDWZ128rmbkz 985115530U, // VPACKUSDWZ128rmk 890579850U, // VPACKUSDWZ128rmkz 811658122U, // VPACKUSDWZ128rr 87059338U, // VPACKUSDWZ128rrk 890284938U, // VPACKUSDWZ128rrkz 812870538U, // VPACKUSDWZ256rm 362900362U, // VPACKUSDWZ256rmb 1438165898U, // VPACKUSDWZ256rmbk 1169582986U, // VPACKUSDWZ256rmbkz 985131914U, // VPACKUSDWZ256rmk 890612618U, // VPACKUSDWZ256rmkz 811658122U, // VPACKUSDWZ256rr 87059338U, // VPACKUSDWZ256rrk 890284938U, // VPACKUSDWZ256rrkz 812886922U, // VPACKUSDWZrm 364997514U, // VPACKUSDWZrmb 1440263050U, // VPACKUSDWZrmbk 1171680138U, // VPACKUSDWZrmbkz 985148298U, // VPACKUSDWZrmk 890678154U, // VPACKUSDWZrmkz 811658122U, // VPACKUSDWZrr 87059338U, // VPACKUSDWZrrk 890284938U, // VPACKUSDWZrrkz 811854730U, // VPACKUSDWrm 811658122U, // VPACKUSDWrr 812861121U, // VPACKUSWBYrm 811648705U, // VPACKUSWBYrr 811845313U, // VPACKUSWBZ128rm 985106113U, // VPACKUSWBZ128rmk 890570433U, // VPACKUSWBZ128rmkz 811648705U, // VPACKUSWBZ128rr 87049921U, // VPACKUSWBZ128rrk 890275521U, // VPACKUSWBZ128rrkz 812861121U, // VPACKUSWBZ256rm 985122497U, // VPACKUSWBZ256rmk 890603201U, // VPACKUSWBZ256rmkz 811648705U, // VPACKUSWBZ256rr 87049921U, // VPACKUSWBZ256rrk 890275521U, // VPACKUSWBZ256rrkz 812877505U, // VPACKUSWBZrm 985138881U, // VPACKUSWBZrmk 890668737U, // VPACKUSWBZrmkz 811648705U, // VPACKUSWBZrr 87049921U, // VPACKUSWBZrrk 890275521U, // VPACKUSWBZrrkz 811845313U, // VPACKUSWBrm 811648705U, // VPACKUSWBrr 812860394U, // VPADDBYrm 811647978U, // VPADDBYrr 811844586U, // VPADDBZ128rm 985105386U, // VPADDBZ128rmk 890569706U, // VPADDBZ128rmkz 811647978U, // VPADDBZ128rr 87049194U, // VPADDBZ128rrk 890274794U, // VPADDBZ128rrkz 812860394U, // VPADDBZ256rm 985121770U, // VPADDBZ256rmk 890602474U, // VPADDBZ256rmkz 811647978U, // VPADDBZ256rr 87049194U, // VPADDBZ256rrk 890274794U, // VPADDBZ256rrkz 812876778U, // VPADDBZrm 985138154U, // VPADDBZrmk 890668010U, // VPADDBZrmkz 811647978U, // VPADDBZrr 87049194U, // VPADDBZrrk 890274794U, // VPADDBZrrkz 811844586U, // VPADDBrm 811647978U, // VPADDBrr 812861372U, // VPADDDYrm 811648956U, // VPADDDYrr 811845564U, // VPADDDZ128rm 360794044U, // VPADDDZ128rmb 1436059580U, // VPADDDZ128rmbk 1167476668U, // VPADDDZ128rmbkz 985106364U, // VPADDDZ128rmk 890570684U, // VPADDDZ128rmkz 811648956U, // VPADDDZ128rr 87050172U, // VPADDDZ128rrk 890275772U, // VPADDDZ128rrkz 812861372U, // VPADDDZ256rm 362891196U, // VPADDDZ256rmb 1438156732U, // VPADDDZ256rmbk 1169573820U, // VPADDDZ256rmbkz 985122748U, // VPADDDZ256rmk 890603452U, // VPADDDZ256rmkz 811648956U, // VPADDDZ256rr 87050172U, // VPADDDZ256rrk 890275772U, // VPADDDZ256rrkz 812877756U, // VPADDDZrm 364988348U, // VPADDDZrmb 1440253884U, // VPADDDZrmbk 1171670972U, // VPADDDZrmbkz 985139132U, // VPADDDZrmk 890668988U, // VPADDDZrmkz 811648956U, // VPADDDZrr 87050172U, // VPADDDZrrk 890275772U, // VPADDDZrrkz 811845564U, // VPADDDrm 811648956U, // VPADDDrr 812866135U, // VPADDQYrm 811653719U, // VPADDQYrr 811850327U, // VPADDQZ128rm 358718039U, // VPADDQZ128rmb 1433950807U, // VPADDQZ128rmbk 1165285975U, // VPADDQZ128rmbkz 985111127U, // VPADDQZ128rmk 890575447U, // VPADDQZ128rmkz 811653719U, // VPADDQZ128rr 87054935U, // VPADDQZ128rrk 890280535U, // VPADDQZ128rrkz 812866135U, // VPADDQZ256rm 360815191U, // VPADDQZ256rmb 1436047959U, // VPADDQZ256rmbk 1167383127U, // VPADDQZ256rmbkz 985127511U, // VPADDQZ256rmk 890608215U, // VPADDQZ256rmkz 811653719U, // VPADDQZ256rr 87054935U, // VPADDQZ256rrk 890280535U, // VPADDQZ256rrkz 812882519U, // VPADDQZrm 362912343U, // VPADDQZrmb 1438145111U, // VPADDQZrmbk 1169480279U, // VPADDQZrmbkz 985143895U, // VPADDQZrmk 890673751U, // VPADDQZrmkz 811653719U, // VPADDQZrr 87054935U, // VPADDQZrrk 890280535U, // VPADDQZrrkz 811850327U, // VPADDQrm 811653719U, // VPADDQrr 812860858U, // VPADDSBYrm 811648442U, // VPADDSBYrr 811845050U, // VPADDSBZ128rm 985105850U, // VPADDSBZ128rmk 890570170U, // VPADDSBZ128rmkz 811648442U, // VPADDSBZ128rr 87049658U, // VPADDSBZ128rrk 890275258U, // VPADDSBZ128rrkz 812860858U, // VPADDSBZ256rm 985122234U, // VPADDSBZ256rmk 890602938U, // VPADDSBZ256rmkz 811648442U, // VPADDSBZ256rr 87049658U, // VPADDSBZ256rrk 890275258U, // VPADDSBZ256rrkz 812877242U, // VPADDSBZrm 985138618U, // VPADDSBZrmk 890668474U, // VPADDSBZrmkz 811648442U, // VPADDSBZrr 87049658U, // VPADDSBZrrk 890275258U, // VPADDSBZrrkz 811845050U, // VPADDSBrm 811648442U, // VPADDSBrr 812871191U, // VPADDSWYrm 811658775U, // VPADDSWYrr 811855383U, // VPADDSWZ128rm 985116183U, // VPADDSWZ128rmk 890580503U, // VPADDSWZ128rmkz 811658775U, // VPADDSWZ128rr 87059991U, // VPADDSWZ128rrk 890285591U, // VPADDSWZ128rrkz 812871191U, // VPADDSWZ256rm 985132567U, // VPADDSWZ256rmk 890613271U, // VPADDSWZ256rmkz 811658775U, // VPADDSWZ256rr 87059991U, // VPADDSWZ256rrk 890285591U, // VPADDSWZ256rrkz 812887575U, // VPADDSWZrm 985148951U, // VPADDSWZrmk 890678807U, // VPADDSWZrmkz 811658775U, // VPADDSWZrr 87059991U, // VPADDSWZrrk 890285591U, // VPADDSWZrrkz 811855383U, // VPADDSWrm 811658775U, // VPADDSWrr 812860920U, // VPADDUSBYrm 811648504U, // VPADDUSBYrr 811845112U, // VPADDUSBZ128rm 985105912U, // VPADDUSBZ128rmk 890570232U, // VPADDUSBZ128rmkz 811648504U, // VPADDUSBZ128rr 87049720U, // VPADDUSBZ128rrk 890275320U, // VPADDUSBZ128rrkz 812860920U, // VPADDUSBZ256rm 985122296U, // VPADDUSBZ256rmk 890603000U, // VPADDUSBZ256rmkz 811648504U, // VPADDUSBZ256rr 87049720U, // VPADDUSBZ256rrk 890275320U, // VPADDUSBZ256rrkz 812877304U, // VPADDUSBZrm 985138680U, // VPADDUSBZrmk 890668536U, // VPADDUSBZrmkz 811648504U, // VPADDUSBZrr 87049720U, // VPADDUSBZrrk 890275320U, // VPADDUSBZrrkz 811845112U, // VPADDUSBrm 811648504U, // VPADDUSBrr 812871317U, // VPADDUSWYrm 811658901U, // VPADDUSWYrr 811855509U, // VPADDUSWZ128rm 985116309U, // VPADDUSWZ128rmk 890580629U, // VPADDUSWZ128rmkz 811658901U, // VPADDUSWZ128rr 87060117U, // VPADDUSWZ128rrk 890285717U, // VPADDUSWZ128rrkz 812871317U, // VPADDUSWZ256rm 985132693U, // VPADDUSWZ256rmk 890613397U, // VPADDUSWZ256rmkz 811658901U, // VPADDUSWZ256rr 87060117U, // VPADDUSWZ256rrk 890285717U, // VPADDUSWZ256rrkz 812887701U, // VPADDUSWZrm 985149077U, // VPADDUSWZrmk 890678933U, // VPADDUSWZrmkz 811658901U, // VPADDUSWZrr 87060117U, // VPADDUSWZrrk 890285717U, // VPADDUSWZrrkz 811855509U, // VPADDUSWrm 811658901U, // VPADDUSWrr 812870448U, // VPADDWYrm 811658032U, // VPADDWYrr 811854640U, // VPADDWZ128rm 985115440U, // VPADDWZ128rmk 890579760U, // VPADDWZ128rmkz 811658032U, // VPADDWZ128rr 87059248U, // VPADDWZ128rrk 890284848U, // VPADDWZ128rrkz 812870448U, // VPADDWZ256rm 985131824U, // VPADDWZ256rmk 890612528U, // VPADDWZ256rmkz 811658032U, // VPADDWZ256rr 87059248U, // VPADDWZ256rrk 890284848U, // VPADDWZ256rrkz 812886832U, // VPADDWZrm 985148208U, // VPADDWZrmk 890678064U, // VPADDWZrmkz 811658032U, // VPADDWZrr 87059248U, // VPADDWZrrk 890284848U, // VPADDWZrrkz 811854640U, // VPADDWrm 811658032U, // VPADDWrr 375775517U, // VPALIGNRYrmi 1088823581U, // VPALIGNRYrri 325443869U, // VPALIGNRZ128rmi 1983111453U, // VPALIGNRZ128rmik 1179918621U, // VPALIGNRZ128rmikz 1088823581U, // VPALIGNRZ128rri 2163138845U, // VPALIGNRZ128rrik 1357586717U, // VPALIGNRZ128rrikz 375775517U, // VPALIGNRZ256rmi 1989402909U, // VPALIGNRZ256rmik 1186210077U, // VPALIGNRZ256rmikz 1088823581U, // VPALIGNRZ256rri 2163138845U, // VPALIGNRZ256rrik 1357586717U, // VPALIGNRZ256rrikz 382066973U, // VPALIGNRZrmi 1995694365U, // VPALIGNRZrmik 1192501533U, // VPALIGNRZrmikz 1088823581U, // VPALIGNRZrri 2163138845U, // VPALIGNRZrrik 1357586717U, // VPALIGNRZrrikz 325443869U, // VPALIGNRrmi 1088823581U, // VPALIGNRrri 811845588U, // VPANDDZ128rm 360794068U, // VPANDDZ128rmb 1436059604U, // VPANDDZ128rmbk 1167476692U, // VPANDDZ128rmbkz 985106388U, // VPANDDZ128rmk 890570708U, // VPANDDZ128rmkz 811648980U, // VPANDDZ128rr 87050196U, // VPANDDZ128rrk 890275796U, // VPANDDZ128rrkz 812861396U, // VPANDDZ256rm 362891220U, // VPANDDZ256rmb 1438156756U, // VPANDDZ256rmbk 1169573844U, // VPANDDZ256rmbkz 985122772U, // VPANDDZ256rmk 890603476U, // VPANDDZ256rmkz 811648980U, // VPANDDZ256rr 87050196U, // VPANDDZ256rrk 890275796U, // VPANDDZ256rrkz 812877780U, // VPANDDZrm 364988372U, // VPANDDZrmb 1440253908U, // VPANDDZrmbk 1171670996U, // VPANDDZrmbkz 985139156U, // VPANDDZrmk 890669012U, // VPANDDZrmkz 811648980U, // VPANDDZrr 87050196U, // VPANDDZrrk 890275796U, // VPANDDZrrkz 811845860U, // VPANDNDZ128rm 360794340U, // VPANDNDZ128rmb 1436059876U, // VPANDNDZ128rmbk 1167476964U, // VPANDNDZ128rmbkz 985106660U, // VPANDNDZ128rmk 890570980U, // VPANDNDZ128rmkz 811649252U, // VPANDNDZ128rr 87050468U, // VPANDNDZ128rrk 890276068U, // VPANDNDZ128rrkz 812861668U, // VPANDNDZ256rm 362891492U, // VPANDNDZ256rmb 1438157028U, // VPANDNDZ256rmbk 1169574116U, // VPANDNDZ256rmbkz 985123044U, // VPANDNDZ256rmk 890603748U, // VPANDNDZ256rmkz 811649252U, // VPANDNDZ256rr 87050468U, // VPANDNDZ256rrk 890276068U, // VPANDNDZ256rrkz 812878052U, // VPANDNDZrm 364988644U, // VPANDNDZrmb 1440254180U, // VPANDNDZrmbk 1171671268U, // VPANDNDZrmbkz 985139428U, // VPANDNDZrmk 890669284U, // VPANDNDZrmkz 811649252U, // VPANDNDZrr 87050468U, // VPANDNDZrrk 890276068U, // VPANDNDZrrkz 811851085U, // VPANDNQZ128rm 358718797U, // VPANDNQZ128rmb 1433951565U, // VPANDNQZ128rmbk 1165286733U, // VPANDNQZ128rmbkz 985111885U, // VPANDNQZ128rmk 890576205U, // VPANDNQZ128rmkz 811654477U, // VPANDNQZ128rr 87055693U, // VPANDNQZ128rrk 890281293U, // VPANDNQZ128rrkz 812866893U, // VPANDNQZ256rm 360815949U, // VPANDNQZ256rmb 1436048717U, // VPANDNQZ256rmbk 1167383885U, // VPANDNQZ256rmbkz 985128269U, // VPANDNQZ256rmk 890608973U, // VPANDNQZ256rmkz 811654477U, // VPANDNQZ256rr 87055693U, // VPANDNQZ256rrk 890281293U, // VPANDNQZ256rrkz 812883277U, // VPANDNQZrm 362913101U, // VPANDNQZrmb 1438145869U, // VPANDNQZrmbk 1169481037U, // VPANDNQZrmbkz 985144653U, // VPANDNQZrmk 890674509U, // VPANDNQZrmkz 811654477U, // VPANDNQZrr 87055693U, // VPANDNQZrrk 890281293U, // VPANDNQZrrkz 812865618U, // VPANDNYrm 811653202U, // VPANDNYrr 811849810U, // VPANDNrm 811653202U, // VPANDNrr 811850438U, // VPANDQZ128rm 358718150U, // VPANDQZ128rmb 1433950918U, // VPANDQZ128rmbk 1165286086U, // VPANDQZ128rmbkz 985111238U, // VPANDQZ128rmk 890575558U, // VPANDQZ128rmkz 811653830U, // VPANDQZ128rr 87055046U, // VPANDQZ128rrk 890280646U, // VPANDQZ128rrkz 812866246U, // VPANDQZ256rm 360815302U, // VPANDQZ256rmb 1436048070U, // VPANDQZ256rmbk 1167383238U, // VPANDQZ256rmbkz 985127622U, // VPANDQZ256rmk 890608326U, // VPANDQZ256rmkz 811653830U, // VPANDQZ256rr 87055046U, // VPANDQZ256rrk 890280646U, // VPANDQZ256rrkz 812882630U, // VPANDQZrm 362912454U, // VPANDQZrmb 1438145222U, // VPANDQZrmbk 1169480390U, // VPANDQZrmbkz 985144006U, // VPANDQZrmk 890673862U, // VPANDQZrmkz 811653830U, // VPANDQZrr 87055046U, // VPANDQZrrk 890280646U, // VPANDQZrrkz 812861653U, // VPANDYrm 811649237U, // VPANDYrr 811845845U, // VPANDrm 811649237U, // VPANDrr 812860482U, // VPAVGBYrm 811648066U, // VPAVGBYrr 811844674U, // VPAVGBZ128rm 985105474U, // VPAVGBZ128rmk 890569794U, // VPAVGBZ128rmkz 811648066U, // VPAVGBZ128rr 87049282U, // VPAVGBZ128rrk 890274882U, // VPAVGBZ128rrkz 812860482U, // VPAVGBZ256rm 985121858U, // VPAVGBZ256rmk 890602562U, // VPAVGBZ256rmkz 811648066U, // VPAVGBZ256rr 87049282U, // VPAVGBZ256rrk 890274882U, // VPAVGBZ256rrkz 812876866U, // VPAVGBZrm 985138242U, // VPAVGBZrmk 890668098U, // VPAVGBZrmkz 811648066U, // VPAVGBZrr 87049282U, // VPAVGBZrrk 890274882U, // VPAVGBZrrkz 811844674U, // VPAVGBrm 811648066U, // VPAVGBrr 812870669U, // VPAVGWYrm 811658253U, // VPAVGWYrr 811854861U, // VPAVGWZ128rm 985115661U, // VPAVGWZ128rmk 890579981U, // VPAVGWZ128rmkz 811658253U, // VPAVGWZ128rr 87059469U, // VPAVGWZ128rrk 890285069U, // VPAVGWZ128rrkz 812870669U, // VPAVGWZ256rm 985132045U, // VPAVGWZ256rmk 890612749U, // VPAVGWZ256rmkz 811658253U, // VPAVGWZ256rr 87059469U, // VPAVGWZ256rrk 890285069U, // VPAVGWZ256rrkz 812887053U, // VPAVGWZrm 985148429U, // VPAVGWZrmk 890678285U, // VPAVGWZrmkz 811658253U, // VPAVGWZrr 87059469U, // VPAVGWZrrk 890285069U, // VPAVGWZrrkz 811854861U, // VPAVGWrm 811658253U, // VPAVGWrr 375769063U, // VPBLENDDYrmi 1088817127U, // VPBLENDDYrri 325437415U, // VPBLENDDrmi 1088817127U, // VPBLENDDrri 811844752U, // VPBLENDMBZ128rm 890569872U, // VPBLENDMBZ128rmk 890569872U, // VPBLENDMBZ128rmkz 811648144U, // VPBLENDMBZ128rr 890274960U, // VPBLENDMBZ128rrk 890274960U, // VPBLENDMBZ128rrkz 812860560U, // VPBLENDMBZ256rm 890602640U, // VPBLENDMBZ256rmk 890602640U, // VPBLENDMBZ256rmkz 811648144U, // VPBLENDMBZ256rr 890274960U, // VPBLENDMBZ256rrk 890274960U, // VPBLENDMBZ256rrkz 812876944U, // VPBLENDMBZrm 890668176U, // VPBLENDMBZrmk 890668176U, // VPBLENDMBZrmkz 811648144U, // VPBLENDMBZrr 890274960U, // VPBLENDMBZrrk 890274960U, // VPBLENDMBZrrkz 811845797U, // VPBLENDMDZ128rm 360794277U, // VPBLENDMDZ128rmb 1167476901U, // VPBLENDMDZ128rmbk 1167476901U, // VPBLENDMDZ128rmbkz 890570917U, // VPBLENDMDZ128rmk 890570917U, // VPBLENDMDZ128rmkz 811649189U, // VPBLENDMDZ128rr 890276005U, // VPBLENDMDZ128rrk 890276005U, // VPBLENDMDZ128rrkz 812861605U, // VPBLENDMDZ256rm 362891429U, // VPBLENDMDZ256rmb 1169574053U, // VPBLENDMDZ256rmbk 1169574053U, // VPBLENDMDZ256rmbkz 890603685U, // VPBLENDMDZ256rmk 890603685U, // VPBLENDMDZ256rmkz 811649189U, // VPBLENDMDZ256rr 890276005U, // VPBLENDMDZ256rrk 890276005U, // VPBLENDMDZ256rrkz 812877989U, // VPBLENDMDZrm 364988581U, // VPBLENDMDZrmb 1171671205U, // VPBLENDMDZrmbk 1171671205U, // VPBLENDMDZrmbkz 890669221U, // VPBLENDMDZrmk 890669221U, // VPBLENDMDZrmkz 811649189U, // VPBLENDMDZrr 890276005U, // VPBLENDMDZrrk 890276005U, // VPBLENDMDZrrkz 811851029U, // VPBLENDMQZ128rm 358718741U, // VPBLENDMQZ128rmb 1165286677U, // VPBLENDMQZ128rmbk 1165286677U, // VPBLENDMQZ128rmbkz 890576149U, // VPBLENDMQZ128rmk 890576149U, // VPBLENDMQZ128rmkz 811654421U, // VPBLENDMQZ128rr 890281237U, // VPBLENDMQZ128rrk 890281237U, // VPBLENDMQZ128rrkz 812866837U, // VPBLENDMQZ256rm 360815893U, // VPBLENDMQZ256rmb 1167383829U, // VPBLENDMQZ256rmbk 1167383829U, // VPBLENDMQZ256rmbkz 890608917U, // VPBLENDMQZ256rmk 890608917U, // VPBLENDMQZ256rmkz 811654421U, // VPBLENDMQZ256rr 890281237U, // VPBLENDMQZ256rrk 890281237U, // VPBLENDMQZ256rrkz 812883221U, // VPBLENDMQZrm 362913045U, // VPBLENDMQZrmb 1169480981U, // VPBLENDMQZrmbk 1169480981U, // VPBLENDMQZrmbkz 890674453U, // VPBLENDMQZrmk 890674453U, // VPBLENDMQZrmkz 811654421U, // VPBLENDMQZrr 890281237U, // VPBLENDMQZrrk 890281237U, // VPBLENDMQZrrkz 811855021U, // VPBLENDMWZ128rm 890580141U, // VPBLENDMWZ128rmk 890580141U, // VPBLENDMWZ128rmkz 811658413U, // VPBLENDMWZ128rr 890285229U, // VPBLENDMWZ128rrk 890285229U, // VPBLENDMWZ128rrkz 812870829U, // VPBLENDMWZ256rm 890612909U, // VPBLENDMWZ256rmk 890612909U, // VPBLENDMWZ256rmkz 811658413U, // VPBLENDMWZ256rr 890285229U, // VPBLENDMWZ256rrk 890285229U, // VPBLENDMWZ256rrkz 812887213U, // VPBLENDMWZrm 890678445U, // VPBLENDMWZrmk 890678445U, // VPBLENDMWZrmkz 811658413U, // VPBLENDMWZrr 890285229U, // VPBLENDMWZrrk 890285229U, // VPBLENDMWZrrkz 376718991U, // VPBLENDVBYrm 890275471U, // VPBLENDVBYrr 326387343U, // VPBLENDVBrm 890275471U, // VPBLENDVBrr 375778156U, // VPBLENDWYrmi 1088826220U, // VPBLENDWYrri 325446508U, // VPBLENDWrmi 1088826220U, // VPBLENDWrri 493124U, // VPBROADCASTBYrm 551831108U, // VPBROADCASTBYrr 493124U, // VPBROADCASTBZ128m 1623620U, // VPBROADCASTBZ128mk 3229730372U, // VPBROADCASTBZ128mkz 551831108U, // VPBROADCASTBZ128r 3230697028U, // VPBROADCASTBZ128rk 3229664836U, // VPBROADCASTBZ128rkz 493124U, // VPBROADCASTBZ256m 1623620U, // VPBROADCASTBZ256mk 3229730372U, // VPBROADCASTBZ256mkz 551831108U, // VPBROADCASTBZ256r 3230697028U, // VPBROADCASTBZ256rk 3229664836U, // VPBROADCASTBZ256rkz 493124U, // VPBROADCASTBZm 1623620U, // VPBROADCASTBZmk 3229730372U, // VPBROADCASTBZmkz 551831108U, // VPBROADCASTBZr 3230697028U, // VPBROADCASTBZrk 3229664836U, // VPBROADCASTBZrkz 551831108U, // VPBROADCASTBrZ128r 3230697028U, // VPBROADCASTBrZ128rk 3229664836U, // VPBROADCASTBrZ128rkz 551831108U, // VPBROADCASTBrZ256r 3230697028U, // VPBROADCASTBrZ256rk 3229664836U, // VPBROADCASTBrZ256rkz 551831108U, // VPBROADCASTBrZr 3230697028U, // VPBROADCASTBrZrk 3229664836U, // VPBROADCASTBrZrkz 493124U, // VPBROADCASTBrm 551831108U, // VPBROADCASTBrr 551899233U, // VPBROADCASTDYrm 551833697U, // VPBROADCASTDYrr 551899233U, // VPBROADCASTDZ128m 553013345U, // VPBROADCASTDZ128mk 551637089U, // VPBROADCASTDZ128mkz 551833697U, // VPBROADCASTDZ128r 3230699617U, // VPBROADCASTDZ128rk 3229667425U, // VPBROADCASTDZ128rkz 551899233U, // VPBROADCASTDZ256m 553013345U, // VPBROADCASTDZ256mk 551637089U, // VPBROADCASTDZ256mkz 551833697U, // VPBROADCASTDZ256r 3230699617U, // VPBROADCASTDZ256rk 3229667425U, // VPBROADCASTDZ256rkz 551899233U, // VPBROADCASTDZm 553013345U, // VPBROADCASTDZmk 551637089U, // VPBROADCASTDZmkz 551833697U, // VPBROADCASTDZr 3230699617U, // VPBROADCASTDZrk 3229667425U, // VPBROADCASTDZrkz 551833697U, // VPBROADCASTDrZ128r 3230699617U, // VPBROADCASTDrZ128rk 3229667425U, // VPBROADCASTDrZ128rkz 551833697U, // VPBROADCASTDrZ256r 3230699617U, // VPBROADCASTDrZ256rk 3229667425U, // VPBROADCASTDrZ256rkz 551833697U, // VPBROADCASTDrZr 3230699617U, // VPBROADCASTDrZrk 3229667425U, // VPBROADCASTDrZrkz 551899233U, // VPBROADCASTDrm 551833697U, // VPBROADCASTDrr 551835950U, // VPBROADCASTMB2QZ128rr 551835950U, // VPBROADCASTMB2QZ256rr 551835950U, // VPBROADCASTMB2QZrr 551831363U, // VPBROADCASTMW2DZ128rr 551831363U, // VPBROADCASTMW2DZ256rr 551831363U, // VPBROADCASTMW2DZrr 551919570U, // VPBROADCASTQYrm 551837650U, // VPBROADCASTQYrr 551919570U, // VPBROADCASTQZ128m 552918994U, // VPBROADCASTQZ128mk 551657426U, // VPBROADCASTQZ128mkz 551837650U, // VPBROADCASTQZ128r 3230703570U, // VPBROADCASTQZ128rk 3229671378U, // VPBROADCASTQZ128rkz 551919570U, // VPBROADCASTQZ256m 552918994U, // VPBROADCASTQZ256mk 551657426U, // VPBROADCASTQZ256mkz 551837650U, // VPBROADCASTQZ256r 3230703570U, // VPBROADCASTQZ256rk 3229671378U, // VPBROADCASTQZ256rkz 551919570U, // VPBROADCASTQZm 552918994U, // VPBROADCASTQZmk 551657426U, // VPBROADCASTQZmkz 551837650U, // VPBROADCASTQZr 3230703570U, // VPBROADCASTQZrk 3229671378U, // VPBROADCASTQZrkz 551837650U, // VPBROADCASTQrZ128r 3230703570U, // VPBROADCASTQrZ128rk 3229671378U, // VPBROADCASTQrZ128rkz 551837650U, // VPBROADCASTQrZ256r 3230703570U, // VPBROADCASTQrZ256rk 3229671378U, // VPBROADCASTQrZ256rkz 551837650U, // VPBROADCASTQrZr 3230703570U, // VPBROADCASTQrZrk 3229671378U, // VPBROADCASTQrZrkz 551919570U, // VPBROADCASTQrm 551837650U, // VPBROADCASTQrr 438041U, // VPBROADCASTWYrm 551841561U, // VPBROADCASTWYrr 438041U, // VPBROADCASTWZ128m 1650457U, // VPBROADCASTWZ128mk 3229691673U, // VPBROADCASTWZ128mkz 551841561U, // VPBROADCASTWZ128r 3230707481U, // VPBROADCASTWZ128rk 3229675289U, // VPBROADCASTWZ128rkz 438041U, // VPBROADCASTWZ256m 1650457U, // VPBROADCASTWZ256mk 3229691673U, // VPBROADCASTWZ256mkz 551841561U, // VPBROADCASTWZ256r 3230707481U, // VPBROADCASTWZ256rk 3229675289U, // VPBROADCASTWZ256rkz 438041U, // VPBROADCASTWZm 1650457U, // VPBROADCASTWZmk 3229691673U, // VPBROADCASTWZmkz 551841561U, // VPBROADCASTWZr 3230707481U, // VPBROADCASTWZrk 3229675289U, // VPBROADCASTWZrkz 551841561U, // VPBROADCASTWrZ128r 3230707481U, // VPBROADCASTWrZ128rk 3229675289U, // VPBROADCASTWrZ128rkz 551841561U, // VPBROADCASTWrZ256r 3230707481U, // VPBROADCASTWrZ256rk 3229675289U, // VPBROADCASTWrZ256rkz 551841561U, // VPBROADCASTWrZr 3230707481U, // VPBROADCASTWrZrk 3229675289U, // VPBROADCASTWrZrkz 438041U, // VPBROADCASTWrm 551841561U, // VPBROADCASTWrr 375773961U, // VPCLMULQDQYrm 1088822025U, // VPCLMULQDQYrr 325442313U, // VPCLMULQDQZ128rm 1088822025U, // VPCLMULQDQZ128rr 375773961U, // VPCLMULQDQZ256rm 1088822025U, // VPCLMULQDQZ256rr 382065417U, // VPCLMULQDQZrm 1088822025U, // VPCLMULQDQZrr 325442313U, // VPCLMULQDQrm 1088822025U, // VPCLMULQDQrr 376728065U, // VPCMOVYrmr 890612225U, // VPCMOVYrrm 890284545U, // VPCMOVYrrr 890284545U, // VPCMOVYrrr_REV 326396417U, // VPCMOVrmr 890579457U, // VPCMOVrrm 890284545U, // VPCMOVrrr 890284545U, // VPCMOVrrr_REV 2869427203U, // VPCMPBZ128rmi 325436653U, // VPCMPBZ128rmi_alt 3138780163U, // VPCMPBZ128rmik 1179911405U, // VPCMPBZ128rmik_alt 1258830851U, // VPCMPBZ128rri 1088816365U, // VPCMPBZ128rri_alt 1528183811U, // VPCMPBZ128rrik 1357579501U, // VPCMPBZ128rrik_alt 3406298115U, // VPCMPBZ256rmi 375768301U, // VPCMPBZ256rmi_alt 3675651075U, // VPCMPBZ256rmik 1186202861U, // VPCMPBZ256rmik_alt 1258830851U, // VPCMPBZ256rri 1088816365U, // VPCMPBZ256rri_alt 1528183811U, // VPCMPBZ256rrik 1357579501U, // VPCMPBZ256rrik_alt 3943169027U, // VPCMPBZrmi 382059757U, // VPCMPBZrmi_alt 4212521987U, // VPCMPBZrmik 1192494317U, // VPCMPBZrmik_alt 1258830851U, // VPCMPBZrri 1088816365U, // VPCMPBZrri_alt 1528183811U, // VPCMPBZrrik 1357579501U, // VPCMPBZrrik_alt 2871524355U, // VPCMPDZ128rmi 325438494U, // VPCMPDZ128rmi_alt 187169795U, // VPCMPDZ128rmib 1686490142U, // VPCMPDZ128rmib_alt 456522755U, // VPCMPDZ128rmibk 1712589854U, // VPCMPDZ128rmibk_alt 3140877315U, // VPCMPDZ128rmik 1179913246U, // VPCMPDZ128rmik_alt 1260928003U, // VPCMPDZ128rri 1088818206U, // VPCMPDZ128rri_alt 1530280963U, // VPCMPDZ128rrik 1357581342U, // VPCMPDZ128rrik_alt 3408395267U, // VPCMPDZ256rmi 375770142U, // VPCMPDZ256rmi_alt 187169795U, // VPCMPDZ256rmib 2491796510U, // VPCMPDZ256rmib_alt 456522755U, // VPCMPDZ256rmibk 2517896222U, // VPCMPDZ256rmibk_alt 3677748227U, // VPCMPDZ256rmik 1186204702U, // VPCMPDZ256rmik_alt 1260928003U, // VPCMPDZ256rri 1088818206U, // VPCMPDZ256rri_alt 1530280963U, // VPCMPDZ256rrik 1357581342U, // VPCMPDZ256rrik_alt 3945266179U, // VPCMPDZrmi 382061598U, // VPCMPDZrmi_alt 187169795U, // VPCMPDZrmib 2760231966U, // VPCMPDZrmib_alt 456522755U, // VPCMPDZrmibk 2786331678U, // VPCMPDZrmibk_alt 4214619139U, // VPCMPDZrmik 1192496158U, // VPCMPDZrmik_alt 1260928003U, // VPCMPDZrri 1088818206U, // VPCMPDZrri_alt 1530280963U, // VPCMPDZrrik 1357581342U, // VPCMPDZrrik_alt 812860677U, // VPCMPEQBYrm 811648261U, // VPCMPEQBYrr 811844869U, // VPCMPEQBZ128rm 890569989U, // VPCMPEQBZ128rmk 811648261U, // VPCMPEQBZ128rr 890275077U, // VPCMPEQBZ128rrk 812860677U, // VPCMPEQBZ256rm 890602757U, // VPCMPEQBZ256rmk 811648261U, // VPCMPEQBZ256rr 890275077U, // VPCMPEQBZ256rrk 812877061U, // VPCMPEQBZrm 890668293U, // VPCMPEQBZrmk 811648261U, // VPCMPEQBZrr 890275077U, // VPCMPEQBZrrk 811844869U, // VPCMPEQBrm 811648261U, // VPCMPEQBrr 812862819U, // VPCMPEQDYrm 811650403U, // VPCMPEQDYrr 811847011U, // VPCMPEQDZ128rm 360795491U, // VPCMPEQDZ128rmb 1167478115U, // VPCMPEQDZ128rmbk 890572131U, // VPCMPEQDZ128rmk 811650403U, // VPCMPEQDZ128rr 890277219U, // VPCMPEQDZ128rrk 812862819U, // VPCMPEQDZ256rm 362892643U, // VPCMPEQDZ256rmb 1169575267U, // VPCMPEQDZ256rmbk 890604899U, // VPCMPEQDZ256rmk 811650403U, // VPCMPEQDZ256rr 890277219U, // VPCMPEQDZ256rrk 812879203U, // VPCMPEQDZrm 364989795U, // VPCMPEQDZrmb 1171672419U, // VPCMPEQDZrmbk 890670435U, // VPCMPEQDZrmk 811650403U, // VPCMPEQDZrr 890277219U, // VPCMPEQDZrrk 811847011U, // VPCMPEQDrm 811650403U, // VPCMPEQDrr 812867043U, // VPCMPEQQYrm 811654627U, // VPCMPEQQYrr 811851235U, // VPCMPEQQZ128rm 358718947U, // VPCMPEQQZ128rmb 1165286883U, // VPCMPEQQZ128rmbk 890576355U, // VPCMPEQQZ128rmk 811654627U, // VPCMPEQQZ128rr 890281443U, // VPCMPEQQZ128rrk 812867043U, // VPCMPEQQZ256rm 360816099U, // VPCMPEQQZ256rmb 1167384035U, // VPCMPEQQZ256rmbk 890609123U, // VPCMPEQQZ256rmk 811654627U, // VPCMPEQQZ256rr 890281443U, // VPCMPEQQZ256rrk 812883427U, // VPCMPEQQZrm 362913251U, // VPCMPEQQZrmb 1169481187U, // VPCMPEQQZrmbk 890674659U, // VPCMPEQQZrmk 811654627U, // VPCMPEQQZrr 890281443U, // VPCMPEQQZrrk 811851235U, // VPCMPEQQrm 811654627U, // VPCMPEQQrr 812870968U, // VPCMPEQWYrm 811658552U, // VPCMPEQWYrr 811855160U, // VPCMPEQWZ128rm 890580280U, // VPCMPEQWZ128rmk 811658552U, // VPCMPEQWZ128rr 890285368U, // VPCMPEQWZ128rrk 812870968U, // VPCMPEQWZ256rm 890613048U, // VPCMPEQWZ256rmk 811658552U, // VPCMPEQWZ256rr 890285368U, // VPCMPEQWZ256rrk 812887352U, // VPCMPEQWZrm 890678584U, // VPCMPEQWZrmk 811658552U, // VPCMPEQWZrr 890285368U, // VPCMPEQWZrrk 811855160U, // VPCMPEQWrm 811658552U, // VPCMPEQWrr 830771932U, // VPCMPESTRIrm 283431644U, // VPCMPESTRIrr 830773299U, // VPCMPESTRMrm 283433011U, // VPCMPESTRMrr 812860961U, // VPCMPGTBYrm 811648545U, // VPCMPGTBYrr 811845153U, // VPCMPGTBZ128rm 890570273U, // VPCMPGTBZ128rmk 811648545U, // VPCMPGTBZ128rr 890275361U, // VPCMPGTBZ128rrk 812860961U, // VPCMPGTBZ256rm 890603041U, // VPCMPGTBZ256rmk 811648545U, // VPCMPGTBZ256rr 890275361U, // VPCMPGTBZ256rrk 812877345U, // VPCMPGTBZrm 890668577U, // VPCMPGTBZrmk 811648545U, // VPCMPGTBZrr 890275361U, // VPCMPGTBZrrk 811845153U, // VPCMPGTBrm 811648545U, // VPCMPGTBrr 812863540U, // VPCMPGTDYrm 811651124U, // VPCMPGTDYrr 811847732U, // VPCMPGTDZ128rm 360796212U, // VPCMPGTDZ128rmb 1167478836U, // VPCMPGTDZ128rmbk 890572852U, // VPCMPGTDZ128rmk 811651124U, // VPCMPGTDZ128rr 890277940U, // VPCMPGTDZ128rrk 812863540U, // VPCMPGTDZ256rm 362893364U, // VPCMPGTDZ256rmb 1169575988U, // VPCMPGTDZ256rmbk 890605620U, // VPCMPGTDZ256rmk 811651124U, // VPCMPGTDZ256rr 890277940U, // VPCMPGTDZ256rrk 812879924U, // VPCMPGTDZrm 364990516U, // VPCMPGTDZrmb 1171673140U, // VPCMPGTDZrmbk 890671156U, // VPCMPGTDZrmk 811651124U, // VPCMPGTDZrr 890277940U, // VPCMPGTDZrrk 811847732U, // VPCMPGTDrm 811651124U, // VPCMPGTDrr 812867468U, // VPCMPGTQYrm 811655052U, // VPCMPGTQYrr 811851660U, // VPCMPGTQZ128rm 358719372U, // VPCMPGTQZ128rmb 1165287308U, // VPCMPGTQZ128rmbk 890576780U, // VPCMPGTQZ128rmk 811655052U, // VPCMPGTQZ128rr 890281868U, // VPCMPGTQZ128rrk 812867468U, // VPCMPGTQZ256rm 360816524U, // VPCMPGTQZ256rmb 1167384460U, // VPCMPGTQZ256rmbk 890609548U, // VPCMPGTQZ256rmk 811655052U, // VPCMPGTQZ256rr 890281868U, // VPCMPGTQZ256rrk 812883852U, // VPCMPGTQZrm 362913676U, // VPCMPGTQZrmb 1169481612U, // VPCMPGTQZrmbk 890675084U, // VPCMPGTQZrmk 811655052U, // VPCMPGTQZrr 890281868U, // VPCMPGTQZrrk 811851660U, // VPCMPGTQrm 811655052U, // VPCMPGTQrr 812871398U, // VPCMPGTWYrm 811658982U, // VPCMPGTWYrr 811855590U, // VPCMPGTWZ128rm 890580710U, // VPCMPGTWZ128rmk 811658982U, // VPCMPGTWZ128rr 890285798U, // VPCMPGTWZ128rrk 812871398U, // VPCMPGTWZ256rm 890613478U, // VPCMPGTWZ256rmk 811658982U, // VPCMPGTWZ256rr 890285798U, // VPCMPGTWZ256rrk 812887782U, // VPCMPGTWZrm 890679014U, // VPCMPGTWZrmk 811658982U, // VPCMPGTWZrr 890285798U, // VPCMPGTWZrrk 811855590U, // VPCMPGTWrm 811658982U, // VPCMPGTWrr 830771944U, // VPCMPISTRIrm 283431656U, // VPCMPISTRIrr 830773311U, // VPCMPISTRMrm 283433023U, // VPCMPISTRMrr 2873621507U, // VPCMPQZ128rmi 325442943U, // VPCMPQZ128rmi_alt 726137859U, // VPCMPQZ128rmib 3013991807U, // VPCMPQZ128rmib_alt 995490819U, // VPCMPQZ128rmibk 3075743103U, // VPCMPQZ128rmibk_alt 3142974467U, // VPCMPQZ128rmik 1179917695U, // VPCMPQZ128rmik_alt 1263025155U, // VPCMPQZ128rri 1088822655U, // VPCMPQZ128rri_alt 1532378115U, // VPCMPQZ128rrik 1357585791U, // VPCMPQZ128rrik_alt 3410492419U, // VPCMPQZ256rmi 375774591U, // VPCMPQZ256rmi_alt 726137859U, // VPCMPQZ256rmib 1671814527U, // VPCMPQZ256rmib_alt 995490819U, // VPCMPQZ256rmibk 1733565823U, // VPCMPQZ256rmibk_alt 3679845379U, // VPCMPQZ256rmik 1186209151U, // VPCMPQZ256rmik_alt 1263025155U, // VPCMPQZ256rri 1088822655U, // VPCMPQZ256rri_alt 1532378115U, // VPCMPQZ256rrik 1357585791U, // VPCMPQZ256rrik_alt 3947363331U, // VPCMPQZrmi 382066047U, // VPCMPQZrmi_alt 726137859U, // VPCMPQZrmib 2477120895U, // VPCMPQZrmib_alt 995490819U, // VPCMPQZrmibk 2538872191U, // VPCMPQZrmibk_alt 4216716291U, // VPCMPQZrmik 1192500607U, // VPCMPQZrmik_alt 1263025155U, // VPCMPQZrri 1088822655U, // VPCMPQZrri_alt 1532378115U, // VPCMPQZrrik 1357585791U, // VPCMPQZrrik_alt 2875718659U, // VPCMPUBZ128rmi 325437046U, // VPCMPUBZ128rmi_alt 3145071619U, // VPCMPUBZ128rmik 1179911798U, // VPCMPUBZ128rmik_alt 1265122307U, // VPCMPUBZ128rri 1088816758U, // VPCMPUBZ128rri_alt 1534475267U, // VPCMPUBZ128rrik 1357579894U, // VPCMPUBZ128rrik_alt 3412589571U, // VPCMPUBZ256rmi 375768694U, // VPCMPUBZ256rmi_alt 3681942531U, // VPCMPUBZ256rmik 1186203254U, // VPCMPUBZ256rmik_alt 1265122307U, // VPCMPUBZ256rri 1088816758U, // VPCMPUBZ256rri_alt 1534475267U, // VPCMPUBZ256rrik 1357579894U, // VPCMPUBZ256rrik_alt 3949460483U, // VPCMPUBZrmi 382060150U, // VPCMPUBZrmi_alt 4218813443U, // VPCMPUBZrmik 1192494710U, // VPCMPUBZrmik_alt 1265122307U, // VPCMPUBZrri 1088816758U, // VPCMPUBZrri_alt 1534475267U, // VPCMPUBZrrik 1357579894U, // VPCMPUBZrrik_alt 2877815811U, // VPCMPUDZ128rmi 325439635U, // VPCMPUDZ128rmi_alt 193461251U, // VPCMPUDZ128rmib 1686491283U, // VPCMPUDZ128rmib_alt 462814211U, // VPCMPUDZ128rmibk 1712590995U, // VPCMPUDZ128rmibk_alt 3147168771U, // VPCMPUDZ128rmik 1179914387U, // VPCMPUDZ128rmik_alt 1267219459U, // VPCMPUDZ128rri 1088819347U, // VPCMPUDZ128rri_alt 1536572419U, // VPCMPUDZ128rrik 1357582483U, // VPCMPUDZ128rrik_alt 3414686723U, // VPCMPUDZ256rmi 375771283U, // VPCMPUDZ256rmi_alt 193461251U, // VPCMPUDZ256rmib 2491797651U, // VPCMPUDZ256rmib_alt 462814211U, // VPCMPUDZ256rmibk 2517897363U, // VPCMPUDZ256rmibk_alt 3684039683U, // VPCMPUDZ256rmik 1186205843U, // VPCMPUDZ256rmik_alt 1267219459U, // VPCMPUDZ256rri 1088819347U, // VPCMPUDZ256rri_alt 1536572419U, // VPCMPUDZ256rrik 1357582483U, // VPCMPUDZ256rrik_alt 3951557635U, // VPCMPUDZrmi 382062739U, // VPCMPUDZrmi_alt 193461251U, // VPCMPUDZrmib 2760233107U, // VPCMPUDZrmib_alt 462814211U, // VPCMPUDZrmibk 2786332819U, // VPCMPUDZrmibk_alt 4220910595U, // VPCMPUDZrmik 1192497299U, // VPCMPUDZrmik_alt 1267219459U, // VPCMPUDZrri 1088819347U, // VPCMPUDZrri_alt 1536572419U, // VPCMPUDZrrik 1357582483U, // VPCMPUDZrrik_alt 2879912963U, // VPCMPUQZ128rmi 325443621U, // VPCMPUQZ128rmi_alt 732429315U, // VPCMPUQZ128rmib 3013992485U, // VPCMPUQZ128rmib_alt 1001782275U, // VPCMPUQZ128rmibk 3075743781U, // VPCMPUQZ128rmibk_alt 3149265923U, // VPCMPUQZ128rmik 1179918373U, // VPCMPUQZ128rmik_alt 1269316611U, // VPCMPUQZ128rri 1088823333U, // VPCMPUQZ128rri_alt 1538669571U, // VPCMPUQZ128rrik 1357586469U, // VPCMPUQZ128rrik_alt 3416783875U, // VPCMPUQZ256rmi 375775269U, // VPCMPUQZ256rmi_alt 732429315U, // VPCMPUQZ256rmib 1671815205U, // VPCMPUQZ256rmib_alt 1001782275U, // VPCMPUQZ256rmibk 1733566501U, // VPCMPUQZ256rmibk_alt 3686136835U, // VPCMPUQZ256rmik 1186209829U, // VPCMPUQZ256rmik_alt 1269316611U, // VPCMPUQZ256rri 1088823333U, // VPCMPUQZ256rri_alt 1538669571U, // VPCMPUQZ256rrik 1357586469U, // VPCMPUQZ256rrik_alt 3953654787U, // VPCMPUQZrmi 382066725U, // VPCMPUQZrmi_alt 732429315U, // VPCMPUQZrmib 2477121573U, // VPCMPUQZrmib_alt 1001782275U, // VPCMPUQZrmibk 2538872869U, // VPCMPUQZrmibk_alt 4223007747U, // VPCMPUQZrmik 1192501285U, // VPCMPUQZrmik_alt 1269316611U, // VPCMPUQZrri 1088823333U, // VPCMPUQZrri_alt 1538669571U, // VPCMPUQZrrik 1357586469U, // VPCMPUQZrrik_alt 2882010115U, // VPCMPUWZ128rmi 325447509U, // VPCMPUWZ128rmi_alt 3151363075U, // VPCMPUWZ128rmik 1179922261U, // VPCMPUWZ128rmik_alt 1271413763U, // VPCMPUWZ128rri 1088827221U, // VPCMPUWZ128rri_alt 1540766723U, // VPCMPUWZ128rrik 1357590357U, // VPCMPUWZ128rrik_alt 3418881027U, // VPCMPUWZ256rmi 375779157U, // VPCMPUWZ256rmi_alt 3688233987U, // VPCMPUWZ256rmik 1186213717U, // VPCMPUWZ256rmik_alt 1271413763U, // VPCMPUWZ256rri 1088827221U, // VPCMPUWZ256rri_alt 1540766723U, // VPCMPUWZ256rrik 1357590357U, // VPCMPUWZ256rrik_alt 3955751939U, // VPCMPUWZrmi 382070613U, // VPCMPUWZrmi_alt 4225104899U, // VPCMPUWZrmik 1192505173U, // VPCMPUWZrmik_alt 1271413763U, // VPCMPUWZrri 1088827221U, // VPCMPUWZrri_alt 1540766723U, // VPCMPUWZrrik 1357590357U, // VPCMPUWZrrik_alt 2884107267U, // VPCMPWZ128rmi 325446924U, // VPCMPWZ128rmi_alt 3153460227U, // VPCMPWZ128rmik 1179921676U, // VPCMPWZ128rmik_alt 1273510915U, // VPCMPWZ128rri 1088826636U, // VPCMPWZ128rri_alt 1542863875U, // VPCMPWZ128rrik 1357589772U, // VPCMPWZ128rrik_alt 3420978179U, // VPCMPWZ256rmi 375778572U, // VPCMPWZ256rmi_alt 3690331139U, // VPCMPWZ256rmik 1186213132U, // VPCMPWZ256rmik_alt 1273510915U, // VPCMPWZ256rri 1088826636U, // VPCMPWZ256rri_alt 1542863875U, // VPCMPWZ256rrik 1357589772U, // VPCMPWZ256rrik_alt 3957849091U, // VPCMPWZrmi 382070028U, // VPCMPWZrmi_alt 4227202051U, // VPCMPWZrmik 1192504588U, // VPCMPWZrmik_alt 1273510915U, // VPCMPWZrri 1088826636U, // VPCMPWZrri_alt 1542863875U, // VPCMPWZrrik 1357589772U, // VPCMPWZrrik_alt 2870574020U, // VPCOMBmi 325436582U, // VPCOMBmi_alt 1259977668U, // VPCOMBri 1088816294U, // VPCOMBri_alt 2872671172U, // VPCOMDmi 325437627U, // VPCOMDmi_alt 1262074820U, // VPCOMDri 1088817339U, // VPCOMDri_alt 33588698U, // VPCOMPRESSBZ128mr 3255109082U, // VPCOMPRESSBZ128mrk 551831002U, // VPCOMPRESSBZ128rr 3230696922U, // VPCOMPRESSBZ128rrk 3229664730U, // VPCOMPRESSBZ128rrkz 180389338U, // VPCOMPRESSBZ256mr 3401909722U, // VPCOMPRESSBZ256mrk 551831002U, // VPCOMPRESSBZ256rr 3230696922U, // VPCOMPRESSBZ256rrk 3229664730U, // VPCOMPRESSBZ256rrkz 182486490U, // VPCOMPRESSBZmr 3404006874U, // VPCOMPRESSBZmrk 551831002U, // VPCOMPRESSBZrr 3230696922U, // VPCOMPRESSBZrrk 3229664730U, // VPCOMPRESSBZrrkz 33591178U, // VPCOMPRESSDZ128mr 3255111562U, // VPCOMPRESSDZ128mrk 551833482U, // VPCOMPRESSDZ128rr 3230699402U, // VPCOMPRESSDZ128rrk 3229667210U, // VPCOMPRESSDZ128rrkz 180391818U, // VPCOMPRESSDZ256mr 3401912202U, // VPCOMPRESSDZ256mrk 551833482U, // VPCOMPRESSDZ256rr 3230699402U, // VPCOMPRESSDZ256rrk 3229667210U, // VPCOMPRESSDZ256rrkz 182488970U, // VPCOMPRESSDZmr 3404009354U, // VPCOMPRESSDZmrk 551833482U, // VPCOMPRESSDZrr 3230699402U, // VPCOMPRESSDZrrk 3229667210U, // VPCOMPRESSDZrrkz 33595159U, // VPCOMPRESSQZ128mr 3255115543U, // VPCOMPRESSQZ128mrk 551837463U, // VPCOMPRESSQZ128rr 3230703383U, // VPCOMPRESSQZ128rrk 3229671191U, // VPCOMPRESSQZ128rrkz 180395799U, // VPCOMPRESSQZ256mr 3401916183U, // VPCOMPRESSQZ256mrk 551837463U, // VPCOMPRESSQZ256rr 3230703383U, // VPCOMPRESSQZ256rrk 3229671191U, // VPCOMPRESSQZ256rrkz 182492951U, // VPCOMPRESSQZmr 3404013335U, // VPCOMPRESSQZmrk 551837463U, // VPCOMPRESSQZrr 3230703383U, // VPCOMPRESSQZrrk 3229671191U, // VPCOMPRESSQZrrkz 33599075U, // VPCOMPRESSWZ128mr 3255119459U, // VPCOMPRESSWZ128mrk 551841379U, // VPCOMPRESSWZ128rr 3230707299U, // VPCOMPRESSWZ128rrk 3229675107U, // VPCOMPRESSWZ128rrkz 180399715U, // VPCOMPRESSWZ256mr 3401920099U, // VPCOMPRESSWZ256mrk 551841379U, // VPCOMPRESSWZ256rr 3230707299U, // VPCOMPRESSWZ256rrk 3229675107U, // VPCOMPRESSWZ256rrkz 182496867U, // VPCOMPRESSWZmr 3404017251U, // VPCOMPRESSWZmrk 551841379U, // VPCOMPRESSWZrr 3230707299U, // VPCOMPRESSWZrrk 3229675107U, // VPCOMPRESSWZrrkz 2874768324U, // VPCOMQmi 325442859U, // VPCOMQmi_alt 1264171972U, // VPCOMQri 1088822571U, // VPCOMQri_alt 2876865476U, // VPCOMUBmi 325437028U, // VPCOMUBmi_alt 1266269124U, // VPCOMUBri 1088816740U, // VPCOMUBri_alt 2878962628U, // VPCOMUDmi 325439617U, // VPCOMUDmi_alt 1268366276U, // VPCOMUDri 1088819329U, // VPCOMUDri_alt 2881059780U, // VPCOMUQmi 325443603U, // VPCOMUQmi_alt 1270463428U, // VPCOMUQri 1088823315U, // VPCOMUQri_alt 2883156932U, // VPCOMUWmi 325447491U, // VPCOMUWmi_alt 1272560580U, // VPCOMUWri 1088827203U, // VPCOMUWri_alt 2885254084U, // VPCOMWmi 325446851U, // VPCOMWmi_alt 1274657732U, // VPCOMWri 1088826563U, // VPCOMWri_alt 266279U, // VPCONFLICTDZ128rm 629493799U, // VPCONFLICTDZ128rmb 630607911U, // VPCONFLICTDZ128rmbk 629231655U, // VPCONFLICTDZ128rmbkz 3230994471U, // VPCONFLICTDZ128rmk 3229863975U, // VPCONFLICTDZ128rmkz 551833639U, // VPCONFLICTDZ128rr 3230699559U, // VPCONFLICTDZ128rrk 3229667367U, // VPCONFLICTDZ128rrkz 552947751U, // VPCONFLICTDZ256rm 631590951U, // VPCONFLICTDZ256rmb 632705063U, // VPCONFLICTDZ256rmbk 631328807U, // VPCONFLICTDZ256rmbkz 3231027239U, // VPCONFLICTDZ256rmk 3230879783U, // VPCONFLICTDZ256rmkz 551833639U, // VPCONFLICTDZ256rr 3230699559U, // VPCONFLICTDZ256rrk 3229667367U, // VPCONFLICTDZ256rrkz 552439847U, // VPCONFLICTDZrm 633688103U, // VPCONFLICTDZrmb 634802215U, // VPCONFLICTDZrmbk 633425959U, // VPCONFLICTDZrmbkz 3231092775U, // VPCONFLICTDZrmk 3230896167U, // VPCONFLICTDZrmkz 551833639U, // VPCONFLICTDZrr 3230699559U, // VPCONFLICTDZrrk 3229667367U, // VPCONFLICTDZrrkz 270165U, // VPCONFLICTQZ128rm 627416917U, // VPCONFLICTQZ128rmb 628416341U, // VPCONFLICTQZ128rmbk 627154773U, // VPCONFLICTQZ128rmbkz 3230998357U, // VPCONFLICTQZ128rmk 3229867861U, // VPCONFLICTQZ128rmkz 551837525U, // VPCONFLICTQZ128rr 3230703445U, // VPCONFLICTQZ128rrk 3229671253U, // VPCONFLICTQZ128rrkz 552951637U, // VPCONFLICTQZ256rm 629514069U, // VPCONFLICTQZ256rmb 630513493U, // VPCONFLICTQZ256rmbk 629251925U, // VPCONFLICTQZ256rmbkz 3231031125U, // VPCONFLICTQZ256rmk 3230883669U, // VPCONFLICTQZ256rmkz 551837525U, // VPCONFLICTQZ256rr 3230703445U, // VPCONFLICTQZ256rrk 3229671253U, // VPCONFLICTQZ256rrkz 552443733U, // VPCONFLICTQZrm 631611221U, // VPCONFLICTQZrmb 632610645U, // VPCONFLICTQZrmbk 631349077U, // VPCONFLICTQZrmbkz 3231096661U, // VPCONFLICTQZrmk 3230900053U, // VPCONFLICTQZrmkz 551837525U, // VPCONFLICTQZrr 3230703445U, // VPCONFLICTQZrrk 3229671253U, // VPCONFLICTQZrrkz 890577330U, // VPDPBUSDSZ128m 1167483314U, // VPDPBUSDSZ128mb 1436066226U, // VPDPBUSDSZ128mbk 1436066226U, // VPDPBUSDSZ128mbkz 985113010U, // VPDPBUSDSZ128mk 985113010U, // VPDPBUSDSZ128mkz 890282418U, // VPDPBUSDSZ128r 87056818U, // VPDPBUSDSZ128rk 89153970U, // VPDPBUSDSZ128rkz 890610098U, // VPDPBUSDSZ256m 1169580466U, // VPDPBUSDSZ256mb 1438163378U, // VPDPBUSDSZ256mbk 1438163378U, // VPDPBUSDSZ256mbkz 985129394U, // VPDPBUSDSZ256mk 985129394U, // VPDPBUSDSZ256mkz 890282418U, // VPDPBUSDSZ256r 87056818U, // VPDPBUSDSZ256rk 89153970U, // VPDPBUSDSZ256rkz 890675634U, // VPDPBUSDSZm 1171677618U, // VPDPBUSDSZmb 1440260530U, // VPDPBUSDSZmbk 1440260530U, // VPDPBUSDSZmbkz 985145778U, // VPDPBUSDSZmk 985145778U, // VPDPBUSDSZmkz 890282418U, // VPDPBUSDSZr 87056818U, // VPDPBUSDSZrk 89153970U, // VPDPBUSDSZrkz 890572787U, // VPDPBUSDZ128m 1167478771U, // VPDPBUSDZ128mb 1436061683U, // VPDPBUSDZ128mbk 1436061683U, // VPDPBUSDZ128mbkz 985108467U, // VPDPBUSDZ128mk 985108467U, // VPDPBUSDZ128mkz 890277875U, // VPDPBUSDZ128r 87052275U, // VPDPBUSDZ128rk 89149427U, // VPDPBUSDZ128rkz 890605555U, // VPDPBUSDZ256m 1169575923U, // VPDPBUSDZ256mb 1438158835U, // VPDPBUSDZ256mbk 1438158835U, // VPDPBUSDZ256mbkz 985124851U, // VPDPBUSDZ256mk 985124851U, // VPDPBUSDZ256mkz 890277875U, // VPDPBUSDZ256r 87052275U, // VPDPBUSDZ256rk 89149427U, // VPDPBUSDZ256rkz 890671091U, // VPDPBUSDZm 1171673075U, // VPDPBUSDZmb 1440255987U, // VPDPBUSDZmbk 1440255987U, // VPDPBUSDZmbkz 985141235U, // VPDPBUSDZmk 985141235U, // VPDPBUSDZmkz 890277875U, // VPDPBUSDZr 87052275U, // VPDPBUSDZrk 89149427U, // VPDPBUSDZrkz 890577319U, // VPDPWSSDSZ128m 1167483303U, // VPDPWSSDSZ128mb 1436066215U, // VPDPWSSDSZ128mbk 1436066215U, // VPDPWSSDSZ128mbkz 985112999U, // VPDPWSSDSZ128mk 985112999U, // VPDPWSSDSZ128mkz 890282407U, // VPDPWSSDSZ128r 87056807U, // VPDPWSSDSZ128rk 89153959U, // VPDPWSSDSZ128rkz 890610087U, // VPDPWSSDSZ256m 1169580455U, // VPDPWSSDSZ256mb 1438163367U, // VPDPWSSDSZ256mbk 1438163367U, // VPDPWSSDSZ256mbkz 985129383U, // VPDPWSSDSZ256mk 985129383U, // VPDPWSSDSZ256mkz 890282407U, // VPDPWSSDSZ256r 87056807U, // VPDPWSSDSZ256rk 89153959U, // VPDPWSSDSZ256rkz 890675623U, // VPDPWSSDSZm 1171677607U, // VPDPWSSDSZmb 1440260519U, // VPDPWSSDSZmbk 1440260519U, // VPDPWSSDSZmbkz 985145767U, // VPDPWSSDSZmk 985145767U, // VPDPWSSDSZmkz 890282407U, // VPDPWSSDSZr 87056807U, // VPDPWSSDSZrk 89153959U, // VPDPWSSDSZrkz 890572733U, // VPDPWSSDZ128m 1167478717U, // VPDPWSSDZ128mb 1436061629U, // VPDPWSSDZ128mbk 1436061629U, // VPDPWSSDZ128mbkz 985108413U, // VPDPWSSDZ128mk 985108413U, // VPDPWSSDZ128mkz 890277821U, // VPDPWSSDZ128r 87052221U, // VPDPWSSDZ128rk 89149373U, // VPDPWSSDZ128rkz 890605501U, // VPDPWSSDZ256m 1169575869U, // VPDPWSSDZ256mb 1438158781U, // VPDPWSSDZ256mbk 1438158781U, // VPDPWSSDZ256mbkz 985124797U, // VPDPWSSDZ256mk 985124797U, // VPDPWSSDZ256mkz 890277821U, // VPDPWSSDZ256r 87052221U, // VPDPWSSDZ256rk 89149373U, // VPDPWSSDZ256rkz 890671037U, // VPDPWSSDZm 1171673021U, // VPDPWSSDZmb 1440255933U, // VPDPWSSDZmbk 1440255933U, // VPDPWSSDZmbkz 985141181U, // VPDPWSSDZmk 985141181U, // VPDPWSSDZmkz 890277821U, // VPDPWSSDZr 87052221U, // VPDPWSSDZrk 89149373U, // VPDPWSSDZrkz 392544868U, // VPERM2F128rm 1088815716U, // VPERM2F128rr 392544923U, // VPERM2I128rm 1088815771U, // VPERM2I128rr 811844796U, // VPERMBZ128rm 985105596U, // VPERMBZ128rmk 890569916U, // VPERMBZ128rmkz 811648188U, // VPERMBZ128rr 87049404U, // VPERMBZ128rrk 890275004U, // VPERMBZ128rrkz 812860604U, // VPERMBZ256rm 985121980U, // VPERMBZ256rmk 890602684U, // VPERMBZ256rmkz 811648188U, // VPERMBZ256rr 87049404U, // VPERMBZ256rrk 890275004U, // VPERMBZ256rrkz 812876988U, // VPERMBZrm 985138364U, // VPERMBZrmk 890668220U, // VPERMBZrmkz 811648188U, // VPERMBZrr 87049404U, // VPERMBZrrk 890275004U, // VPERMBZrrkz 812861635U, // VPERMDYrm 811649219U, // VPERMDYrr 812861635U, // VPERMDZ256rm 362891459U, // VPERMDZ256rmb 1438156995U, // VPERMDZ256rmbk 1169574083U, // VPERMDZ256rmbkz 985123011U, // VPERMDZ256rmk 890603715U, // VPERMDZ256rmkz 811649219U, // VPERMDZ256rr 87050435U, // VPERMDZ256rrk 890276035U, // VPERMDZ256rrkz 812878019U, // VPERMDZrm 364988611U, // VPERMDZrmb 1440254147U, // VPERMDZrmbk 1171671235U, // VPERMDZrmbkz 985139395U, // VPERMDZrmk 890669251U, // VPERMDZrmkz 811649219U, // VPERMDZrr 87050435U, // VPERMDZrrk 890276035U, // VPERMDZrrkz 890569579U, // VPERMI2B128rm 985105259U, // VPERMI2B128rmk 985105259U, // VPERMI2B128rmkz 890274667U, // VPERMI2B128rr 87049067U, // VPERMI2B128rrk 89146219U, // VPERMI2B128rrkz 890602347U, // VPERMI2B256rm 985121643U, // VPERMI2B256rmk 985121643U, // VPERMI2B256rmkz 890274667U, // VPERMI2B256rr 87049067U, // VPERMI2B256rrk 89146219U, // VPERMI2B256rrkz 890667883U, // VPERMI2Brm 985138027U, // VPERMI2Brmk 985138027U, // VPERMI2Brmkz 890274667U, // VPERMI2Brr 87049067U, // VPERMI2Brrk 89146219U, // VPERMI2Brrkz 890570533U, // VPERMI2D128rm 1167476517U, // VPERMI2D128rmb 1436059429U, // VPERMI2D128rmbk 1436059429U, // VPERMI2D128rmbkz 985106213U, // VPERMI2D128rmk 985106213U, // VPERMI2D128rmkz 890275621U, // VPERMI2D128rr 87050021U, // VPERMI2D128rrk 89147173U, // VPERMI2D128rrkz 890603301U, // VPERMI2D256rm 1169573669U, // VPERMI2D256rmb 1438156581U, // VPERMI2D256rmbk 1438156581U, // VPERMI2D256rmbkz 985122597U, // VPERMI2D256rmk 985122597U, // VPERMI2D256rmkz 890275621U, // VPERMI2D256rr 87050021U, // VPERMI2D256rrk 89147173U, // VPERMI2D256rrkz 890668837U, // VPERMI2Drm 1171670821U, // VPERMI2Drmb 1440253733U, // VPERMI2Drmbk 1440253733U, // VPERMI2Drmbkz 985138981U, // VPERMI2Drmk 985138981U, // VPERMI2Drmkz 890275621U, // VPERMI2Drr 87050021U, // VPERMI2Drrk 89147173U, // VPERMI2Drrkz 890177970U, // VPERMI2PD128rm 1164970418U, // VPERMI2PD128rmb 1433389490U, // VPERMI2PD128rmbk 1433389490U, // VPERMI2PD128rmbkz 86985138U, // VPERMI2PD128rmk 89082290U, // VPERMI2PD128rmkz 890276274U, // VPERMI2PD128rr 87050674U, // VPERMI2PD128rrk 89147826U, // VPERMI2PD128rrkz 890309042U, // VPERMI2PD256rm 1167067570U, // VPERMI2PD256rmb 1435486642U, // VPERMI2PD256rmbk 1435486642U, // VPERMI2PD256rmbkz 87083442U, // VPERMI2PD256rmk 89180594U, // VPERMI2PD256rmkz 890276274U, // VPERMI2PD256rr 87050674U, // VPERMI2PD256rrk 89147826U, // VPERMI2PD256rrkz 890358194U, // VPERMI2PDrm 1169164722U, // VPERMI2PDrmb 1437583794U, // VPERMI2PDrmbk 1437583794U, // VPERMI2PDrmbkz 87132594U, // VPERMI2PDrmk 89229746U, // VPERMI2PDrmkz 890276274U, // VPERMI2PDrr 87050674U, // VPERMI2PDrrk 89147826U, // VPERMI2PDrrkz 890184386U, // VPERMI2PS128rm 1167270594U, // VPERMI2PS128rmb 1435689666U, // VPERMI2PS128rmbk 1435689666U, // VPERMI2PS128rmbkz 86991554U, // VPERMI2PS128rmk 89088706U, // VPERMI2PS128rmkz 890282690U, // VPERMI2PS128rr 87057090U, // VPERMI2PS128rrk 89154242U, // VPERMI2PS128rrkz 890315458U, // VPERMI2PS256rm 1169367746U, // VPERMI2PS256rmb 1437786818U, // VPERMI2PS256rmbk 1437786818U, // VPERMI2PS256rmbkz 87089858U, // VPERMI2PS256rmk 89187010U, // VPERMI2PS256rmkz 890282690U, // VPERMI2PS256rr 87057090U, // VPERMI2PS256rrk 89154242U, // VPERMI2PS256rrkz 890364610U, // VPERMI2PSrm 1171464898U, // VPERMI2PSrmb 1439883970U, // VPERMI2PSrmbk 1439883970U, // VPERMI2PSrmbkz 87139010U, // VPERMI2PSrmk 89236162U, // VPERMI2PSrmkz 890282690U, // VPERMI2PSrr 87057090U, // VPERMI2PSrrk 89154242U, // VPERMI2PSrrkz 890575167U, // VPERMI2Q128rm 1165285695U, // VPERMI2Q128rmb 1433950527U, // VPERMI2Q128rmbk 1433950527U, // VPERMI2Q128rmbkz 985110847U, // VPERMI2Q128rmk 985110847U, // VPERMI2Q128rmkz 890280255U, // VPERMI2Q128rr 87054655U, // VPERMI2Q128rrk 89151807U, // VPERMI2Q128rrkz 890607935U, // VPERMI2Q256rm 1167382847U, // VPERMI2Q256rmb 1436047679U, // VPERMI2Q256rmbk 1436047679U, // VPERMI2Q256rmbkz 985127231U, // VPERMI2Q256rmk 985127231U, // VPERMI2Q256rmkz 890280255U, // VPERMI2Q256rr 87054655U, // VPERMI2Q256rrk 89151807U, // VPERMI2Q256rrkz 890673471U, // VPERMI2Qrm 1169479999U, // VPERMI2Qrmb 1438144831U, // VPERMI2Qrmbk 1438144831U, // VPERMI2Qrmbkz 985143615U, // VPERMI2Qrmk 985143615U, // VPERMI2Qrmkz 890280255U, // VPERMI2Qrr 87054655U, // VPERMI2Qrrk 89151807U, // VPERMI2Qrrkz 890579481U, // VPERMI2W128rm 985115161U, // VPERMI2W128rmk 985115161U, // VPERMI2W128rmkz 890284569U, // VPERMI2W128rr 87058969U, // VPERMI2W128rrk 89156121U, // VPERMI2W128rrkz 890612249U, // VPERMI2W256rm 985131545U, // VPERMI2W256rmk 985131545U, // VPERMI2W256rmkz 890284569U, // VPERMI2W256rr 87058969U, // VPERMI2W256rrk 89156121U, // VPERMI2W256rrkz 890677785U, // VPERMI2Wrm 985147929U, // VPERMI2Wrmk 985147929U, // VPERMI2Wrmkz 890284569U, // VPERMI2Wrr 87058969U, // VPERMI2Wrrk 89156121U, // VPERMI2Wrrkz 3692300743U, // VPERMIL2PDYmr 1186204103U, // VPERMIL2PDYrm 1357580743U, // VPERMIL2PDYrr 1357580743U, // VPERMIL2PDYrr_REV 2081688007U, // VPERMIL2PDmr 1179912647U, // VPERMIL2PDrm 1357580743U, // VPERMIL2PDrr 1357580743U, // VPERMIL2PDrr_REV 3692307159U, // VPERMIL2PSYmr 1186210519U, // VPERMIL2PSYrm 1357587159U, // VPERMIL2PSYrr 1357587159U, // VPERMIL2PSYrr_REV 2081694423U, // VPERMIL2PSmr 1179919063U, // VPERMIL2PSrm 1357587159U, // VPERMIL2PSrr 1357587159U, // VPERMIL2PSrr_REV 168070135U, // VPERMILPDYmi 283429879U, // VPERMILPDYri 812862455U, // VPERMILPDYrm 811650039U, // VPERMILPDYrr 3032779767U, // VPERMILPDZ128mbi 3079932919U, // VPERMILPDZ128mbik 2999307255U, // VPERMILPDZ128mbikz 77892599U, // VPERMILPDZ128mi 666110967U, // VPERMILPDZ128mik 568708087U, // VPERMILPDZ128mikz 283429879U, // VPERMILPDZ128ri 1357581303U, // VPERMILPDZ128rik 1088818167U, // VPERMILPDZ128rikz 811846647U, // VPERMILPDZ128rm 358763511U, // VPERMILPDZ128rmb 1433390071U, // VPERMILPDZ128rmbk 1164970999U, // VPERMILPDZ128rmbkz 985107447U, // VPERMILPDZ128rmk 890571767U, // VPERMILPDZ128rmkz 811650039U, // VPERMILPDZ128rr 87051255U, // VPERMILPDZ128rrk 890276855U, // VPERMILPDZ128rrkz 1690602487U, // VPERMILPDZ256mbi 1737755639U, // VPERMILPDZ256mbik 1657129975U, // VPERMILPDZ256mbikz 168070135U, // VPERMILPDZ256mi 668208119U, // VPERMILPDZ256mik 660982775U, // VPERMILPDZ256mikz 283429879U, // VPERMILPDZ256ri 1357581303U, // VPERMILPDZ256rik 1088818167U, // VPERMILPDZ256rikz 812862455U, // VPERMILPDZ256rm 360860663U, // VPERMILPDZ256rmb 1435487223U, // VPERMILPDZ256rmbk 1167068151U, // VPERMILPDZ256rmbkz 985123831U, // VPERMILPDZ256rmk 890604535U, // VPERMILPDZ256rmkz 811650039U, // VPERMILPDZ256rr 87051255U, // VPERMILPDZ256rrk 890276855U, // VPERMILPDZ256rrkz 2495908855U, // VPERMILPDZmbi 2543062007U, // VPERMILPDZmbik 2462436343U, // VPERMILPDZmbikz 170167287U, // VPERMILPDZmi 672402423U, // VPERMILPDZmik 669371383U, // VPERMILPDZmikz 283429879U, // VPERMILPDZri 1357581303U, // VPERMILPDZrik 1088818167U, // VPERMILPDZrikz 812878839U, // VPERMILPDZrm 362957815U, // VPERMILPDZrmb 1437584375U, // VPERMILPDZrmbk 1169165303U, // VPERMILPDZrmbkz 985140215U, // VPERMILPDZrmk 890670071U, // VPERMILPDZrmkz 811650039U, // VPERMILPDZrr 87051255U, // VPERMILPDZrrk 890276855U, // VPERMILPDZrrkz 77892599U, // VPERMILPDmi 283429879U, // VPERMILPDri 811846647U, // VPERMILPDrm 811650039U, // VPERMILPDrr 168076575U, // VPERMILPSYmi 283436319U, // VPERMILPSYri 812868895U, // VPERMILPSYrm 811656479U, // VPERMILPSYrr 1692706079U, // VPERMILPSZ128mbi 1752442143U, // VPERMILPSZ128mbik 1661330719U, // VPERMILPSZ128mbikz 77899039U, // VPERMILPSZ128mi 666117407U, // VPERMILPSZ128mik 568714527U, // VPERMILPSZ128mikz 283436319U, // VPERMILPSZ128ri 1357587743U, // VPERMILPSZ128rik 1088824607U, // VPERMILPSZ128rikz 811853087U, // VPERMILPSZ128rm 360883487U, // VPERMILPSZ128rmb 1435690271U, // VPERMILPSZ128rmbk 1167271199U, // VPERMILPSZ128rmbkz 985113887U, // VPERMILPSZ128rmk 890578207U, // VPERMILPSZ128rmkz 811656479U, // VPERMILPSZ128rr 87057695U, // VPERMILPSZ128rrk 890283295U, // VPERMILPSZ128rrkz 2498012447U, // VPERMILPSZ256mbi 2557748511U, // VPERMILPSZ256mbik 2466637087U, // VPERMILPSZ256mbikz 168076575U, // VPERMILPSZ256mi 668214559U, // VPERMILPSZ256mik 660989215U, // VPERMILPSZ256mikz 283436319U, // VPERMILPSZ256ri 1357587743U, // VPERMILPSZ256rik 1088824607U, // VPERMILPSZ256rikz 812868895U, // VPERMILPSZ256rm 362980639U, // VPERMILPSZ256rmb 1437787423U, // VPERMILPSZ256rmbk 1169368351U, // VPERMILPSZ256rmbkz 985130271U, // VPERMILPSZ256rmk 890610975U, // VPERMILPSZ256rmkz 811656479U, // VPERMILPSZ256rr 87057695U, // VPERMILPSZ256rrk 890283295U, // VPERMILPSZ256rrkz 2766447903U, // VPERMILPSZmbi 2826183967U, // VPERMILPSZmbik 2735072543U, // VPERMILPSZmbikz 170173727U, // VPERMILPSZmi 672408863U, // VPERMILPSZmik 669377823U, // VPERMILPSZmikz 283436319U, // VPERMILPSZri 1357587743U, // VPERMILPSZrik 1088824607U, // VPERMILPSZrikz 812885279U, // VPERMILPSZrm 365077791U, // VPERMILPSZrmb 1439884575U, // VPERMILPSZrmbk 1171465503U, // VPERMILPSZrmbkz 985146655U, // VPERMILPSZrmk 890676511U, // VPERMILPSZrmkz 811656479U, // VPERMILPSZrr 87057695U, // VPERMILPSZrrk 890283295U, // VPERMILPSZrrkz 77899039U, // VPERMILPSmi 283436319U, // VPERMILPSri 811853087U, // VPERMILPSrm 811656479U, // VPERMILPSrr 168070206U, // VPERMPDYmi 283429950U, // VPERMPDYri 1690602558U, // VPERMPDZ256mbi 1737755710U, // VPERMPDZ256mbik 1657130046U, // VPERMPDZ256mbikz 168070206U, // VPERMPDZ256mi 668208190U, // VPERMPDZ256mik 660982846U, // VPERMPDZ256mikz 283429950U, // VPERMPDZ256ri 1357581374U, // VPERMPDZ256rik 1088818238U, // VPERMPDZ256rikz 812616766U, // VPERMPDZ256rm 360860734U, // VPERMPDZ256rmb 1435487294U, // VPERMPDZ256rmbk 1167068222U, // VPERMPDZ256rmbkz 87084094U, // VPERMPDZ256rmk 890309694U, // VPERMPDZ256rmkz 811650110U, // VPERMPDZ256rr 87051326U, // VPERMPDZ256rrk 890276926U, // VPERMPDZ256rrkz 2495908926U, // VPERMPDZmbi 2543062078U, // VPERMPDZmbik 2462436414U, // VPERMPDZmbikz 170167358U, // VPERMPDZmi 672402494U, // VPERMPDZmik 669371454U, // VPERMPDZmikz 283429950U, // VPERMPDZri 1357581374U, // VPERMPDZrik 1088818238U, // VPERMPDZrikz 812731454U, // VPERMPDZrm 362957886U, // VPERMPDZrmb 1437584446U, // VPERMPDZrmbk 1169165374U, // VPERMPDZrmbkz 87133246U, // VPERMPDZrmk 890358846U, // VPERMPDZrmkz 811650110U, // VPERMPDZrr 87051326U, // VPERMPDZrrk 890276926U, // VPERMPDZrrkz 812623215U, // VPERMPSYrm 811656559U, // VPERMPSYrr 812623215U, // VPERMPSZ256rm 362980719U, // VPERMPSZ256rmb 1437787503U, // VPERMPSZ256rmbk 1169368431U, // VPERMPSZ256rmbkz 87090543U, // VPERMPSZ256rmk 890316143U, // VPERMPSZ256rmkz 811656559U, // VPERMPSZ256rr 87057775U, // VPERMPSZ256rrk 890283375U, // VPERMPSZ256rrkz 812737903U, // VPERMPSZrm 365077871U, // VPERMPSZrmb 1439884655U, // VPERMPSZrmbk 1171465583U, // VPERMPSZrmbkz 87139695U, // VPERMPSZrmk 890365295U, // VPERMPSZrmkz 811656559U, // VPERMPSZrr 87057775U, // VPERMPSZrrk 890283375U, // VPERMPSZrrkz 1009032499U, // VPERMQYmi 283434291U, // VPERMQYri 1640275251U, // VPERMQZ256mbi 1733565747U, // VPERMQZ256mbik 1671814451U, // VPERMQZ256mbikz 1009032499U, // VPERMQZ256mi 649338163U, // VPERMQZ256mik 644209971U, // VPERMQZ256mikz 283434291U, // VPERMQZ256ri 1357585715U, // VPERMQZ256rik 1088822579U, // VPERMQZ256rikz 812866867U, // VPERMQZ256rm 360815923U, // VPERMQZ256rmb 1436048691U, // VPERMQZ256rmbk 1167383859U, // VPERMQZ256rmbkz 985128243U, // VPERMQZ256rmk 890608947U, // VPERMQZ256rmkz 811654451U, // VPERMQZ256rr 87055667U, // VPERMQZ256rrk 890281267U, // VPERMQZ256rrkz 2445581619U, // VPERMQZmbi 2538872115U, // VPERMQZmbik 2477120819U, // VPERMQZmbikz 1011129651U, // VPERMQZmi 655629619U, // VPERMQZmik 650501427U, // VPERMQZmikz 283434291U, // VPERMQZri 1357585715U, // VPERMQZrik 1088822579U, // VPERMQZrikz 812883251U, // VPERMQZrm 362913075U, // VPERMQZrmb 1438145843U, // VPERMQZrmbk 1169481011U, // VPERMQZrmbkz 985144627U, // VPERMQZrmk 890674483U, // VPERMQZrmkz 811654451U, // VPERMQZrr 87055667U, // VPERMQZrrk 890281267U, // VPERMQZrrkz 890569599U, // VPERMT2B128rm 985105279U, // VPERMT2B128rmk 985105279U, // VPERMT2B128rmkz 890274687U, // VPERMT2B128rr 87049087U, // VPERMT2B128rrk 89146239U, // VPERMT2B128rrkz 890602367U, // VPERMT2B256rm 985121663U, // VPERMT2B256rmk 985121663U, // VPERMT2B256rmkz 890274687U, // VPERMT2B256rr 87049087U, // VPERMT2B256rrk 89146239U, // VPERMT2B256rrkz 890667903U, // VPERMT2Brm 985138047U, // VPERMT2Brmk 985138047U, // VPERMT2Brmkz 890274687U, // VPERMT2Brr 87049087U, // VPERMT2Brrk 89146239U, // VPERMT2Brrkz 890570553U, // VPERMT2D128rm 1167476537U, // VPERMT2D128rmb 1436059449U, // VPERMT2D128rmbk 1436059449U, // VPERMT2D128rmbkz 985106233U, // VPERMT2D128rmk 985106233U, // VPERMT2D128rmkz 890275641U, // VPERMT2D128rr 87050041U, // VPERMT2D128rrk 89147193U, // VPERMT2D128rrkz 890603321U, // VPERMT2D256rm 1169573689U, // VPERMT2D256rmb 1438156601U, // VPERMT2D256rmbk 1438156601U, // VPERMT2D256rmbkz 985122617U, // VPERMT2D256rmk 985122617U, // VPERMT2D256rmkz 890275641U, // VPERMT2D256rr 87050041U, // VPERMT2D256rrk 89147193U, // VPERMT2D256rrkz 890668857U, // VPERMT2Drm 1171670841U, // VPERMT2Drmb 1440253753U, // VPERMT2Drmbk 1440253753U, // VPERMT2Drmbkz 985139001U, // VPERMT2Drmk 985139001U, // VPERMT2Drmkz 890275641U, // VPERMT2Drr 87050041U, // VPERMT2Drrk 89147193U, // VPERMT2Drrkz 890178069U, // VPERMT2PD128rm 1164970517U, // VPERMT2PD128rmb 1433389589U, // VPERMT2PD128rmbk 1433389589U, // VPERMT2PD128rmbkz 86985237U, // VPERMT2PD128rmk 89082389U, // VPERMT2PD128rmkz 890276373U, // VPERMT2PD128rr 87050773U, // VPERMT2PD128rrk 89147925U, // VPERMT2PD128rrkz 890309141U, // VPERMT2PD256rm 1167067669U, // VPERMT2PD256rmb 1435486741U, // VPERMT2PD256rmbk 1435486741U, // VPERMT2PD256rmbkz 87083541U, // VPERMT2PD256rmk 89180693U, // VPERMT2PD256rmkz 890276373U, // VPERMT2PD256rr 87050773U, // VPERMT2PD256rrk 89147925U, // VPERMT2PD256rrkz 890358293U, // VPERMT2PDrm 1169164821U, // VPERMT2PDrmb 1437583893U, // VPERMT2PDrmbk 1437583893U, // VPERMT2PDrmbkz 87132693U, // VPERMT2PDrmk 89229845U, // VPERMT2PDrmkz 890276373U, // VPERMT2PDrr 87050773U, // VPERMT2PDrrk 89147925U, // VPERMT2PDrrkz 890184474U, // VPERMT2PS128rm 1167270682U, // VPERMT2PS128rmb 1435689754U, // VPERMT2PS128rmbk 1435689754U, // VPERMT2PS128rmbkz 86991642U, // VPERMT2PS128rmk 89088794U, // VPERMT2PS128rmkz 890282778U, // VPERMT2PS128rr 87057178U, // VPERMT2PS128rrk 89154330U, // VPERMT2PS128rrkz 890315546U, // VPERMT2PS256rm 1169367834U, // VPERMT2PS256rmb 1437786906U, // VPERMT2PS256rmbk 1437786906U, // VPERMT2PS256rmbkz 87089946U, // VPERMT2PS256rmk 89187098U, // VPERMT2PS256rmkz 890282778U, // VPERMT2PS256rr 87057178U, // VPERMT2PS256rrk 89154330U, // VPERMT2PS256rrkz 890364698U, // VPERMT2PSrm 1171464986U, // VPERMT2PSrmb 1439884058U, // VPERMT2PSrmbk 1439884058U, // VPERMT2PSrmbkz 87139098U, // VPERMT2PSrmk 89236250U, // VPERMT2PSrmkz 890282778U, // VPERMT2PSrr 87057178U, // VPERMT2PSrrk 89154330U, // VPERMT2PSrrkz 890575196U, // VPERMT2Q128rm 1165285724U, // VPERMT2Q128rmb 1433950556U, // VPERMT2Q128rmbk 1433950556U, // VPERMT2Q128rmbkz 985110876U, // VPERMT2Q128rmk 985110876U, // VPERMT2Q128rmkz 890280284U, // VPERMT2Q128rr 87054684U, // VPERMT2Q128rrk 89151836U, // VPERMT2Q128rrkz 890607964U, // VPERMT2Q256rm 1167382876U, // VPERMT2Q256rmb 1436047708U, // VPERMT2Q256rmbk 1436047708U, // VPERMT2Q256rmbkz 985127260U, // VPERMT2Q256rmk 985127260U, // VPERMT2Q256rmkz 890280284U, // VPERMT2Q256rr 87054684U, // VPERMT2Q256rrk 89151836U, // VPERMT2Q256rrkz 890673500U, // VPERMT2Qrm 1169480028U, // VPERMT2Qrmb 1438144860U, // VPERMT2Qrmbk 1438144860U, // VPERMT2Qrmbkz 985143644U, // VPERMT2Qrmk 985143644U, // VPERMT2Qrmkz 890280284U, // VPERMT2Qrr 87054684U, // VPERMT2Qrrk 89151836U, // VPERMT2Qrrkz 890579501U, // VPERMT2W128rm 985115181U, // VPERMT2W128rmk 985115181U, // VPERMT2W128rmkz 890284589U, // VPERMT2W128rr 87058989U, // VPERMT2W128rrk 89156141U, // VPERMT2W128rrkz 890612269U, // VPERMT2W256rm 985131565U, // VPERMT2W256rmk 985131565U, // VPERMT2W256rmkz 890284589U, // VPERMT2W256rr 87058989U, // VPERMT2W256rrk 89156141U, // VPERMT2W256rrkz 890677805U, // VPERMT2Wrm 985147949U, // VPERMT2Wrmk 985147949U, // VPERMT2Wrmkz 890284589U, // VPERMT2Wrr 87058989U, // VPERMT2Wrrk 89156141U, // VPERMT2Wrrkz 811855051U, // VPERMWZ128rm 985115851U, // VPERMWZ128rmk 890580171U, // VPERMWZ128rmkz 811658443U, // VPERMWZ128rr 87059659U, // VPERMWZ128rrk 890285259U, // VPERMWZ128rrkz 812870859U, // VPERMWZ256rm 985132235U, // VPERMWZ256rmk 890612939U, // VPERMWZ256rmkz 811658443U, // VPERMWZ256rr 87059659U, // VPERMWZ256rrk 890285259U, // VPERMWZ256rrkz 812887243U, // VPERMWZrm 985148619U, // VPERMWZrmk 890678475U, // VPERMWZrmkz 811658443U, // VPERMWZrr 87059659U, // VPERMWZrrk 890285259U, // VPERMWZrrkz 263168U, // VPEXPANDBZ128rm 3230991360U, // VPEXPANDBZ128rmk 3229860864U, // VPEXPANDBZ128rmkz 551830528U, // VPEXPANDBZ128rr 3230696448U, // VPEXPANDBZ128rrk 3229664256U, // VPEXPANDBZ128rrkz 552944640U, // VPEXPANDBZ256rm 3231024128U, // VPEXPANDBZ256rmk 3230876672U, // VPEXPANDBZ256rmkz 551830528U, // VPEXPANDBZ256rr 3230696448U, // VPEXPANDBZ256rrk 3229664256U, // VPEXPANDBZ256rrkz 552436736U, // VPEXPANDBZrm 3231089664U, // VPEXPANDBZrmk 3230893056U, // VPEXPANDBZrmkz 551830528U, // VPEXPANDBZrr 3230696448U, // VPEXPANDBZrrk 3229664256U, // VPEXPANDBZrrkz 264156U, // VPEXPANDDZ128rm 3230992348U, // VPEXPANDDZ128rmk 3229861852U, // VPEXPANDDZ128rmkz 551831516U, // VPEXPANDDZ128rr 3230697436U, // VPEXPANDDZ128rrk 3229665244U, // VPEXPANDDZ128rrkz 552945628U, // VPEXPANDDZ256rm 3231025116U, // VPEXPANDDZ256rmk 3230877660U, // VPEXPANDDZ256rmkz 551831516U, // VPEXPANDDZ256rr 3230697436U, // VPEXPANDDZ256rrk 3229665244U, // VPEXPANDDZ256rrkz 552437724U, // VPEXPANDDZrm 3231090652U, // VPEXPANDDZrmk 3230894044U, // VPEXPANDDZrmkz 551831516U, // VPEXPANDDZrr 3230697436U, // VPEXPANDDZrrk 3229665244U, // VPEXPANDDZrrkz 269006U, // VPEXPANDQZ128rm 3230997198U, // VPEXPANDQZ128rmk 3229866702U, // VPEXPANDQZ128rmkz 551836366U, // VPEXPANDQZ128rr 3230702286U, // VPEXPANDQZ128rrk 3229670094U, // VPEXPANDQZ128rrkz 552950478U, // VPEXPANDQZ256rm 3231029966U, // VPEXPANDQZ256rmk 3230882510U, // VPEXPANDQZ256rmkz 551836366U, // VPEXPANDQZ256rr 3230702286U, // VPEXPANDQZ256rrk 3229670094U, // VPEXPANDQZ256rrkz 552442574U, // VPEXPANDQZrm 3231095502U, // VPEXPANDQZrmk 3230898894U, // VPEXPANDQZrmkz 551836366U, // VPEXPANDQZrr 3230702286U, // VPEXPANDQZrrk 3229670094U, // VPEXPANDQZrrkz 273240U, // VPEXPANDWZ128rm 3231001432U, // VPEXPANDWZ128rmk 3229870936U, // VPEXPANDWZ128rmkz 551840600U, // VPEXPANDWZ128rr 3230706520U, // VPEXPANDWZ128rrk 3229674328U, // VPEXPANDWZ128rrkz 552954712U, // VPEXPANDWZ256rm 3231034200U, // VPEXPANDWZ256rmk 3230886744U, // VPEXPANDWZ256rmkz 551840600U, // VPEXPANDWZ256rr 3230706520U, // VPEXPANDWZ256rrk 3229674328U, // VPEXPANDWZ256rrkz 552446808U, // VPEXPANDWZrm 3231099736U, // VPEXPANDWZrmk 3230903128U, // VPEXPANDWZrmkz 551840600U, // VPEXPANDWZrr 3230706520U, // VPEXPANDWZrrk 3229674328U, // VPEXPANDWZrrkz 321160592U, // VPEXTRBZmr 283428240U, // VPEXTRBZrr 321160592U, // VPEXTRBmr 283428240U, // VPEXTRBrr 589598179U, // VPEXTRDZmr 283430371U, // VPEXTRDZrr 589598179U, // VPEXTRDmr 283430371U, // VPEXTRDrr 858037936U, // VPEXTRQZmr 283434672U, // VPEXTRQZrr 858037936U, // VPEXTRQmr 283434672U, // VPEXTRQrr 1126477261U, // VPEXTRWZmr 283438541U, // VPEXTRWZrr 283438541U, // VPEXTRWZrr_REV 1126477261U, // VPEXTRWmr 283438541U, // VPEXTRWrr 283438541U, // VPEXTRWrr_REV 649545713U, // VPGATHERDDYrm 3231156209U, // VPGATHERDDZ128rm 3231172593U, // VPGATHERDDZ256rm 3231188977U, // VPGATHERDDZrm 643254257U, // VPGATHERDDrm 649550613U, // VPGATHERDQYrm 3231161109U, // VPGATHERDQZ128rm 3231177493U, // VPGATHERDQZ256rm 3231193877U, // VPGATHERDQZrm 643259157U, // VPGATHERDQrm 643255661U, // VPGATHERQDYrm 553143661U, // VPGATHERQDZ128rm 3231157613U, // VPGATHERQDZ256rm 3231173997U, // VPGATHERQDZrm 928468333U, // VPGATHERQDrm 649551341U, // VPGATHERQQYrm 3231161837U, // VPGATHERQQZ128rm 3231178221U, // VPGATHERQQZ256rm 3231194605U, // VPGATHERQQZrm 643259885U, // VPGATHERQQrm 264041U, // VPHADDBDrm 551831401U, // VPHADDBDrr 268682U, // VPHADDBQrm 551836042U, // VPHADDBQrr 273027U, // VPHADDBWrm 551840387U, // VPHADDBWrr 268902U, // VPHADDDQrm 551836262U, // VPHADDDQrr 812861356U, // VPHADDDYrm 811648940U, // VPHADDDYrr 811845548U, // VPHADDDrm 811648940U, // VPHADDDrr 812871181U, // VPHADDSWYrm 811658765U, // VPHADDSWYrr 811855373U, // VPHADDSWrm 811658765U, // VPHADDSWrr 264051U, // VPHADDUBDrm 551831411U, // VPHADDUBDrr 268700U, // VPHADDUBQrm 551836060U, // VPHADDUBQrr 273079U, // VPHADDUBWrm 551840439U, // VPHADDUBWrr 269196U, // VPHADDUDQrm 551836556U, // VPHADDUDQrr 266597U, // VPHADDUWDrm 551833957U, // VPHADDUWDrr 270507U, // VPHADDUWQrm 551837867U, // VPHADDUWQrr 266499U, // VPHADDWDrm 551833859U, // VPHADDWDrr 270482U, // VPHADDWQrm 551837842U, // VPHADDWQrr 812870432U, // VPHADDWYrm 811658016U, // VPHADDWYrr 811854624U, // VPHADDWrm 811658016U, // VPHADDWrr 274270U, // VPHMINPOSUWrm 551841630U, // VPHMINPOSUWrr 272987U, // VPHSUBBWrm 551840347U, // VPHSUBBWrr 268870U, // VPHSUBDQrm 551836230U, // VPHSUBDQrr 812861310U, // VPHSUBDYrm 811648894U, // VPHSUBDYrr 811845502U, // VPHSUBDrm 811648894U, // VPHSUBDrr 812871162U, // VPHSUBSWYrm 811658746U, // VPHSUBSWYrr 811855354U, // VPHSUBSWrm 811658746U, // VPHSUBSWrr 266489U, // VPHSUBWDrm 551833849U, // VPHSUBWDrr 812870338U, // VPHSUBWYrm 811657922U, // VPHSUBWYrr 811854530U, // VPHSUBWrm 811657922U, // VPHSUBWrr 879084925U, // VPINSRBZrm 1088816509U, // VPINSRBZrr 879084925U, // VPINSRBrm 1088816509U, // VPINSRBrr 881184208U, // VPINSRDZrm 1088818640U, // VPINSRDZrr 881184208U, // VPINSRDrm 1088818640U, // VPINSRDrr 866508425U, // VPINSRQZrm 1088822921U, // VPINSRQZrr 866508425U, // VPINSRQrm 1088822921U, // VPINSRQrr 331738536U, // VPINSRWZrm 1088826792U, // VPINSRWZrr 331738536U, // VPINSRWrm 1088826792U, // VPINSRWrr 266312U, // VPLZCNTDZ128rm 629493832U, // VPLZCNTDZ128rmb 630607944U, // VPLZCNTDZ128rmbk 629231688U, // VPLZCNTDZ128rmbkz 3230994504U, // VPLZCNTDZ128rmk 3229864008U, // VPLZCNTDZ128rmkz 551833672U, // VPLZCNTDZ128rr 3230699592U, // VPLZCNTDZ128rrk 3229667400U, // VPLZCNTDZ128rrkz 552947784U, // VPLZCNTDZ256rm 631590984U, // VPLZCNTDZ256rmb 632705096U, // VPLZCNTDZ256rmbk 631328840U, // VPLZCNTDZ256rmbkz 3231027272U, // VPLZCNTDZ256rmk 3230879816U, // VPLZCNTDZ256rmkz 551833672U, // VPLZCNTDZ256rr 3230699592U, // VPLZCNTDZ256rrk 3229667400U, // VPLZCNTDZ256rrkz 552439880U, // VPLZCNTDZrm 633688136U, // VPLZCNTDZrmb 634802248U, // VPLZCNTDZrmbk 633425992U, // VPLZCNTDZrmbkz 3231092808U, // VPLZCNTDZrmk 3230896200U, // VPLZCNTDZrmkz 551833672U, // VPLZCNTDZrr 3230699592U, // VPLZCNTDZrrk 3229667400U, // VPLZCNTDZrrkz 270240U, // VPLZCNTQZ128rm 627416992U, // VPLZCNTQZ128rmb 628416416U, // VPLZCNTQZ128rmbk 627154848U, // VPLZCNTQZ128rmbkz 3230998432U, // VPLZCNTQZ128rmk 3229867936U, // VPLZCNTQZ128rmkz 551837600U, // VPLZCNTQZ128rr 3230703520U, // VPLZCNTQZ128rrk 3229671328U, // VPLZCNTQZ128rrkz 552951712U, // VPLZCNTQZ256rm 629514144U, // VPLZCNTQZ256rmb 630513568U, // VPLZCNTQZ256rmbk 629252000U, // VPLZCNTQZ256rmbkz 3231031200U, // VPLZCNTQZ256rmk 3230883744U, // VPLZCNTQZ256rmkz 551837600U, // VPLZCNTQZ256rr 3230703520U, // VPLZCNTQZ256rrk 3229671328U, // VPLZCNTQZ256rrkz 552443808U, // VPLZCNTQZrm 631611296U, // VPLZCNTQZrmb 632610720U, // VPLZCNTQZrmbk 631349152U, // VPLZCNTQZrmbkz 3231096736U, // VPLZCNTQZrmk 3230900128U, // VPLZCNTQZrmkz 551837600U, // VPLZCNTQZrr 3230703520U, // VPLZCNTQZrrk 3229671328U, // VPLZCNTQZrrkz 326387731U, // VPMACSDDrm 890275859U, // VPMACSDDrr 326390377U, // VPMACSDQHrm 890278505U, // VPMACSDQHrr 326391321U, // VPMACSDQLrm 890279449U, // VPMACSDQLrr 326387741U, // VPMACSSDDrm 890275869U, // VPMACSSDDrr 326390388U, // VPMACSSDQHrm 890278516U, // VPMACSSDQHrr 326391332U, // VPMACSSDQLrm 890279460U, // VPMACSSDQLrr 326390094U, // VPMACSSWDrm 890278222U, // VPMACSSWDrr 326397897U, // VPMACSSWWrm 890286025U, // VPMACSSWWrr 326390073U, // VPMACSWDrm 890278201U, // VPMACSWDrr 326397873U, // VPMACSWWrm 890286001U, // VPMACSWWrr 326390105U, // VPMADCSSWDrm 890278233U, // VPMADCSSWDrr 326390083U, // VPMADCSWDrm 890278211U, // VPMADCSWDrr 890576889U, // VPMADD52HUQZ128m 1165287417U, // VPMADD52HUQZ128mb 1433952249U, // VPMADD52HUQZ128mbk 1433952249U, // VPMADD52HUQZ128mbkz 985112569U, // VPMADD52HUQZ128mk 985112569U, // VPMADD52HUQZ128mkz 890281977U, // VPMADD52HUQZ128r 87056377U, // VPMADD52HUQZ128rk 89153529U, // VPMADD52HUQZ128rkz 890609657U, // VPMADD52HUQZ256m 1167384569U, // VPMADD52HUQZ256mb 1436049401U, // VPMADD52HUQZ256mbk 1436049401U, // VPMADD52HUQZ256mbkz 985128953U, // VPMADD52HUQZ256mk 985128953U, // VPMADD52HUQZ256mkz 890281977U, // VPMADD52HUQZ256r 87056377U, // VPMADD52HUQZ256rk 89153529U, // VPMADD52HUQZ256rkz 890675193U, // VPMADD52HUQZm 1169481721U, // VPMADD52HUQZmb 1438146553U, // VPMADD52HUQZmbk 1438146553U, // VPMADD52HUQZmbkz 985145337U, // VPMADD52HUQZmk 985145337U, // VPMADD52HUQZmkz 890281977U, // VPMADD52HUQZr 87056377U, // VPMADD52HUQZrk 89153529U, // VPMADD52HUQZrkz 890576902U, // VPMADD52LUQZ128m 1165287430U, // VPMADD52LUQZ128mb 1433952262U, // VPMADD52LUQZ128mbk 1433952262U, // VPMADD52LUQZ128mbkz 985112582U, // VPMADD52LUQZ128mk 985112582U, // VPMADD52LUQZ128mkz 890281990U, // VPMADD52LUQZ128r 87056390U, // VPMADD52LUQZ128rk 89153542U, // VPMADD52LUQZ128rkz 890609670U, // VPMADD52LUQZ256m 1167384582U, // VPMADD52LUQZ256mb 1436049414U, // VPMADD52LUQZ256mbk 1436049414U, // VPMADD52LUQZ256mbkz 985128966U, // VPMADD52LUQZ256mk 985128966U, // VPMADD52LUQZ256mkz 890281990U, // VPMADD52LUQZ256r 87056390U, // VPMADD52LUQZ256rk 89153542U, // VPMADD52LUQZ256rkz 890675206U, // VPMADD52LUQZm 1169481734U, // VPMADD52LUQZmb 1438146566U, // VPMADD52LUQZmbk 1438146566U, // VPMADD52LUQZmbkz 985145350U, // VPMADD52LUQZmk 985145350U, // VPMADD52LUQZmkz 890281990U, // VPMADD52LUQZr 87056390U, // VPMADD52LUQZrk 89153542U, // VPMADD52LUQZrkz 812871150U, // VPMADDUBSWYrm 811658734U, // VPMADDUBSWYrr 811855342U, // VPMADDUBSWZ128rm 985116142U, // VPMADDUBSWZ128rmk 890580462U, // VPMADDUBSWZ128rmkz 811658734U, // VPMADDUBSWZ128rr 87059950U, // VPMADDUBSWZ128rrk 890285550U, // VPMADDUBSWZ128rrkz 812871150U, // VPMADDUBSWZ256rm 985132526U, // VPMADDUBSWZ256rmk 890613230U, // VPMADDUBSWZ256rmkz 811658734U, // VPMADDUBSWZ256rr 87059950U, // VPMADDUBSWZ256rrk 890285550U, // VPMADDUBSWZ256rrkz 812887534U, // VPMADDUBSWZrm 985148910U, // VPMADDUBSWZrmk 890678766U, // VPMADDUBSWZrmkz 811658734U, // VPMADDUBSWZrr 87059950U, // VPMADDUBSWZrrk 890285550U, // VPMADDUBSWZrrkz 811855342U, // VPMADDUBSWrm 811658734U, // VPMADDUBSWrr 812863757U, // VPMADDWDYrm 811651341U, // VPMADDWDYrr 811847949U, // VPMADDWDZ128rm 985108749U, // VPMADDWDZ128rmk 890573069U, // VPMADDWDZ128rmkz 811651341U, // VPMADDWDZ128rr 87052557U, // VPMADDWDZ128rrk 890278157U, // VPMADDWDZ128rrkz 812863757U, // VPMADDWDZ256rm 985125133U, // VPMADDWDZ256rmk 890605837U, // VPMADDWDZ256rmkz 811651341U, // VPMADDWDZ256rr 87052557U, // VPMADDWDZ256rrk 890278157U, // VPMADDWDZ256rrkz 812880141U, // VPMADDWDZrm 985141517U, // VPMADDWDZrmk 890671373U, // VPMADDWDZrmkz 811651341U, // VPMADDWDZrr 87052557U, // VPMADDWDZrrk 890278157U, // VPMADDWDZrrkz 811847949U, // VPMADDWDrm 811651341U, // VPMADDWDrr 2200244445U, // VPMASKMOVDYmr 812863709U, // VPMASKMOVDYrm 1931808989U, // VPMASKMOVDmr 811847901U, // VPMASKMOVDrm 2200248438U, // VPMASKMOVQYmr 812867702U, // VPMASKMOVQYrm 1931812982U, // VPMASKMOVQmr 811851894U, // VPMASKMOVQrm 812860946U, // VPMAXSBYrm 811648530U, // VPMAXSBYrr 811845138U, // VPMAXSBZ128rm 985105938U, // VPMAXSBZ128rmk 890570258U, // VPMAXSBZ128rmkz 811648530U, // VPMAXSBZ128rr 87049746U, // VPMAXSBZ128rrk 890275346U, // VPMAXSBZ128rrkz 812860946U, // VPMAXSBZ256rm 985122322U, // VPMAXSBZ256rmk 890603026U, // VPMAXSBZ256rmkz 811648530U, // VPMAXSBZ256rr 87049746U, // VPMAXSBZ256rrk 890275346U, // VPMAXSBZ256rrkz 812877330U, // VPMAXSBZrm 985138706U, // VPMAXSBZrmk 890668562U, // VPMAXSBZrmkz 811648530U, // VPMAXSBZrr 87049746U, // VPMAXSBZrrk 890275346U, // VPMAXSBZrrkz 811845138U, // VPMAXSBrm 811648530U, // VPMAXSBrr 812863501U, // VPMAXSDYrm 811651085U, // VPMAXSDYrr 811847693U, // VPMAXSDZ128rm 360796173U, // VPMAXSDZ128rmb 1436061709U, // VPMAXSDZ128rmbk 1167478797U, // VPMAXSDZ128rmbkz 985108493U, // VPMAXSDZ128rmk 890572813U, // VPMAXSDZ128rmkz 811651085U, // VPMAXSDZ128rr 87052301U, // VPMAXSDZ128rrk 890277901U, // VPMAXSDZ128rrkz 812863501U, // VPMAXSDZ256rm 362893325U, // VPMAXSDZ256rmb 1438158861U, // VPMAXSDZ256rmbk 1169575949U, // VPMAXSDZ256rmbkz 985124877U, // VPMAXSDZ256rmk 890605581U, // VPMAXSDZ256rmkz 811651085U, // VPMAXSDZ256rr 87052301U, // VPMAXSDZ256rrk 890277901U, // VPMAXSDZ256rrkz 812879885U, // VPMAXSDZrm 364990477U, // VPMAXSDZrmb 1440256013U, // VPMAXSDZrmbk 1171673101U, // VPMAXSDZrmbkz 985141261U, // VPMAXSDZrmk 890671117U, // VPMAXSDZrmkz 811651085U, // VPMAXSDZrr 87052301U, // VPMAXSDZrrk 890277901U, // VPMAXSDZrrkz 811847693U, // VPMAXSDrm 811651085U, // VPMAXSDrr 811851591U, // VPMAXSQZ128rm 358719303U, // VPMAXSQZ128rmb 1433952071U, // VPMAXSQZ128rmbk 1165287239U, // VPMAXSQZ128rmbkz 985112391U, // VPMAXSQZ128rmk 890576711U, // VPMAXSQZ128rmkz 811654983U, // VPMAXSQZ128rr 87056199U, // VPMAXSQZ128rrk 890281799U, // VPMAXSQZ128rrkz 812867399U, // VPMAXSQZ256rm 360816455U, // VPMAXSQZ256rmb 1436049223U, // VPMAXSQZ256rmbk 1167384391U, // VPMAXSQZ256rmbkz 985128775U, // VPMAXSQZ256rmk 890609479U, // VPMAXSQZ256rmkz 811654983U, // VPMAXSQZ256rr 87056199U, // VPMAXSQZ256rrk 890281799U, // VPMAXSQZ256rrkz 812883783U, // VPMAXSQZrm 362913607U, // VPMAXSQZrmb 1438146375U, // VPMAXSQZrmbk 1169481543U, // VPMAXSQZrmbkz 985145159U, // VPMAXSQZrmk 890675015U, // VPMAXSQZrmkz 811654983U, // VPMAXSQZrr 87056199U, // VPMAXSQZrrk 890281799U, // VPMAXSQZrrkz 812871335U, // VPMAXSWYrm 811658919U, // VPMAXSWYrr 811855527U, // VPMAXSWZ128rm 985116327U, // VPMAXSWZ128rmk 890580647U, // VPMAXSWZ128rmkz 811658919U, // VPMAXSWZ128rr 87060135U, // VPMAXSWZ128rrk 890285735U, // VPMAXSWZ128rrkz 812871335U, // VPMAXSWZ256rm 985132711U, // VPMAXSWZ256rmk 890613415U, // VPMAXSWZ256rmkz 811658919U, // VPMAXSWZ256rr 87060135U, // VPMAXSWZ256rrk 890285735U, // VPMAXSWZ256rrkz 812887719U, // VPMAXSWZrm 985149095U, // VPMAXSWZrmk 890678951U, // VPMAXSWZrmkz 811658919U, // VPMAXSWZrr 87060135U, // VPMAXSWZrrk 890285735U, // VPMAXSWZrrkz 811855527U, // VPMAXSWrm 811658919U, // VPMAXSWrr 812861062U, // VPMAXUBYrm 811648646U, // VPMAXUBYrr 811845254U, // VPMAXUBZ128rm 985106054U, // VPMAXUBZ128rmk 890570374U, // VPMAXUBZ128rmkz 811648646U, // VPMAXUBZ128rr 87049862U, // VPMAXUBZ128rrk 890275462U, // VPMAXUBZ128rrkz 812861062U, // VPMAXUBZ256rm 985122438U, // VPMAXUBZ256rmk 890603142U, // VPMAXUBZ256rmkz 811648646U, // VPMAXUBZ256rr 87049862U, // VPMAXUBZ256rrk 890275462U, // VPMAXUBZ256rrkz 812877446U, // VPMAXUBZrm 985138822U, // VPMAXUBZrmk 890668678U, // VPMAXUBZrmkz 811648646U, // VPMAXUBZrr 87049862U, // VPMAXUBZrrk 890275462U, // VPMAXUBZrrkz 811845254U, // VPMAXUBrm 811648646U, // VPMAXUBrr 812863644U, // VPMAXUDYrm 811651228U, // VPMAXUDYrr 811847836U, // VPMAXUDZ128rm 360796316U, // VPMAXUDZ128rmb 1436061852U, // VPMAXUDZ128rmbk 1167478940U, // VPMAXUDZ128rmbkz 985108636U, // VPMAXUDZ128rmk 890572956U, // VPMAXUDZ128rmkz 811651228U, // VPMAXUDZ128rr 87052444U, // VPMAXUDZ128rrk 890278044U, // VPMAXUDZ128rrkz 812863644U, // VPMAXUDZ256rm 362893468U, // VPMAXUDZ256rmb 1438159004U, // VPMAXUDZ256rmbk 1169576092U, // VPMAXUDZ256rmbkz 985125020U, // VPMAXUDZ256rmk 890605724U, // VPMAXUDZ256rmkz 811651228U, // VPMAXUDZ256rr 87052444U, // VPMAXUDZ256rrk 890278044U, // VPMAXUDZ256rrkz 812880028U, // VPMAXUDZrm 364990620U, // VPMAXUDZrmb 1440256156U, // VPMAXUDZrmbk 1171673244U, // VPMAXUDZrmbkz 985141404U, // VPMAXUDZrmk 890671260U, // VPMAXUDZrmkz 811651228U, // VPMAXUDZrr 87052444U, // VPMAXUDZrrk 890278044U, // VPMAXUDZrrkz 811847836U, // VPMAXUDrm 811651228U, // VPMAXUDrr 811851822U, // VPMAXUQZ128rm 358719534U, // VPMAXUQZ128rmb 1433952302U, // VPMAXUQZ128rmbk 1165287470U, // VPMAXUQZ128rmbkz 985112622U, // VPMAXUQZ128rmk 890576942U, // VPMAXUQZ128rmkz 811655214U, // VPMAXUQZ128rr 87056430U, // VPMAXUQZ128rrk 890282030U, // VPMAXUQZ128rrkz 812867630U, // VPMAXUQZ256rm 360816686U, // VPMAXUQZ256rmb 1436049454U, // VPMAXUQZ256rmbk 1167384622U, // VPMAXUQZ256rmbkz 985129006U, // VPMAXUQZ256rmk 890609710U, // VPMAXUQZ256rmkz 811655214U, // VPMAXUQZ256rr 87056430U, // VPMAXUQZ256rrk 890282030U, // VPMAXUQZ256rrkz 812884014U, // VPMAXUQZrm 362913838U, // VPMAXUQZrmb 1438146606U, // VPMAXUQZrmbk 1169481774U, // VPMAXUQZrmbkz 985145390U, // VPMAXUQZrmk 890675246U, // VPMAXUQZrmkz 811655214U, // VPMAXUQZrr 87056430U, // VPMAXUQZrrk 890282030U, // VPMAXUQZrrkz 812871531U, // VPMAXUWYrm 811659115U, // VPMAXUWYrr 811855723U, // VPMAXUWZ128rm 985116523U, // VPMAXUWZ128rmk 890580843U, // VPMAXUWZ128rmkz 811659115U, // VPMAXUWZ128rr 87060331U, // VPMAXUWZ128rrk 890285931U, // VPMAXUWZ128rrkz 812871531U, // VPMAXUWZ256rm 985132907U, // VPMAXUWZ256rmk 890613611U, // VPMAXUWZ256rmkz 811659115U, // VPMAXUWZ256rr 87060331U, // VPMAXUWZ256rrk 890285931U, // VPMAXUWZ256rrkz 812887915U, // VPMAXUWZrm 985149291U, // VPMAXUWZrmk 890679147U, // VPMAXUWZrmkz 811659115U, // VPMAXUWZrr 87060331U, // VPMAXUWZrrk 890285931U, // VPMAXUWZrrkz 811855723U, // VPMAXUWrm 811659115U, // VPMAXUWrr 812860874U, // VPMINSBYrm 811648458U, // VPMINSBYrr 811845066U, // VPMINSBZ128rm 985105866U, // VPMINSBZ128rmk 890570186U, // VPMINSBZ128rmkz 811648458U, // VPMINSBZ128rr 87049674U, // VPMINSBZ128rrk 890275274U, // VPMINSBZ128rrkz 812860874U, // VPMINSBZ256rm 985122250U, // VPMINSBZ256rmk 890602954U, // VPMINSBZ256rmkz 811648458U, // VPMINSBZ256rr 87049674U, // VPMINSBZ256rrk 890275274U, // VPMINSBZ256rrkz 812877258U, // VPMINSBZrm 985138634U, // VPMINSBZrmk 890668490U, // VPMINSBZrmkz 811648458U, // VPMINSBZrr 87049674U, // VPMINSBZrrk 890275274U, // VPMINSBZrrkz 811845066U, // VPMINSBrm 811648458U, // VPMINSBrr 812863334U, // VPMINSDYrm 811650918U, // VPMINSDYrr 811847526U, // VPMINSDZ128rm 360796006U, // VPMINSDZ128rmb 1436061542U, // VPMINSDZ128rmbk 1167478630U, // VPMINSDZ128rmbkz 985108326U, // VPMINSDZ128rmk 890572646U, // VPMINSDZ128rmkz 811650918U, // VPMINSDZ128rr 87052134U, // VPMINSDZ128rrk 890277734U, // VPMINSDZ128rrkz 812863334U, // VPMINSDZ256rm 362893158U, // VPMINSDZ256rmb 1438158694U, // VPMINSDZ256rmbk 1169575782U, // VPMINSDZ256rmbkz 985124710U, // VPMINSDZ256rmk 890605414U, // VPMINSDZ256rmkz 811650918U, // VPMINSDZ256rr 87052134U, // VPMINSDZ256rrk 890277734U, // VPMINSDZ256rrkz 812879718U, // VPMINSDZrm 364990310U, // VPMINSDZrmb 1440255846U, // VPMINSDZrmbk 1171672934U, // VPMINSDZrmbkz 985141094U, // VPMINSDZrmk 890670950U, // VPMINSDZrmkz 811650918U, // VPMINSDZrr 87052134U, // VPMINSDZrrk 890277734U, // VPMINSDZrrkz 811847526U, // VPMINSDrm 811650918U, // VPMINSDrr 811851493U, // VPMINSQZ128rm 358719205U, // VPMINSQZ128rmb 1433951973U, // VPMINSQZ128rmbk 1165287141U, // VPMINSQZ128rmbkz 985112293U, // VPMINSQZ128rmk 890576613U, // VPMINSQZ128rmkz 811654885U, // VPMINSQZ128rr 87056101U, // VPMINSQZ128rrk 890281701U, // VPMINSQZ128rrkz 812867301U, // VPMINSQZ256rm 360816357U, // VPMINSQZ256rmb 1436049125U, // VPMINSQZ256rmbk 1167384293U, // VPMINSQZ256rmbkz 985128677U, // VPMINSQZ256rmk 890609381U, // VPMINSQZ256rmkz 811654885U, // VPMINSQZ256rr 87056101U, // VPMINSQZ256rrk 890281701U, // VPMINSQZ256rrkz 812883685U, // VPMINSQZrm 362913509U, // VPMINSQZrmb 1438146277U, // VPMINSQZrmbk 1169481445U, // VPMINSQZrmbkz 985145061U, // VPMINSQZrmk 890674917U, // VPMINSQZrmkz 811654885U, // VPMINSQZrr 87056101U, // VPMINSQZrrk 890281701U, // VPMINSQZrrkz 812871231U, // VPMINSWYrm 811658815U, // VPMINSWYrr 811855423U, // VPMINSWZ128rm 985116223U, // VPMINSWZ128rmk 890580543U, // VPMINSWZ128rmkz 811658815U, // VPMINSWZ128rr 87060031U, // VPMINSWZ128rrk 890285631U, // VPMINSWZ128rrkz 812871231U, // VPMINSWZ256rm 985132607U, // VPMINSWZ256rmk 890613311U, // VPMINSWZ256rmkz 811658815U, // VPMINSWZ256rr 87060031U, // VPMINSWZ256rrk 890285631U, // VPMINSWZ256rrkz 812887615U, // VPMINSWZrm 985148991U, // VPMINSWZrmk 890678847U, // VPMINSWZrmkz 811658815U, // VPMINSWZrr 87060031U, // VPMINSWZrrk 890285631U, // VPMINSWZrrkz 811855423U, // VPMINSWrm 811658815U, // VPMINSWrr 812861037U, // VPMINUBYrm 811648621U, // VPMINUBYrr 811845229U, // VPMINUBZ128rm 985106029U, // VPMINUBZ128rmk 890570349U, // VPMINUBZ128rmkz 811648621U, // VPMINUBZ128rr 87049837U, // VPMINUBZ128rrk 890275437U, // VPMINUBZ128rrkz 812861037U, // VPMINUBZ256rm 985122413U, // VPMINUBZ256rmk 890603117U, // VPMINUBZ256rmkz 811648621U, // VPMINUBZ256rr 87049837U, // VPMINUBZ256rrk 890275437U, // VPMINUBZ256rrkz 812877421U, // VPMINUBZrm 985138797U, // VPMINUBZrmk 890668653U, // VPMINUBZrmkz 811648621U, // VPMINUBZrr 87049837U, // VPMINUBZrrk 890275437U, // VPMINUBZrrkz 811845229U, // VPMINUBrm 811648621U, // VPMINUBrr 812863626U, // VPMINUDYrm 811651210U, // VPMINUDYrr 811847818U, // VPMINUDZ128rm 360796298U, // VPMINUDZ128rmb 1436061834U, // VPMINUDZ128rmbk 1167478922U, // VPMINUDZ128rmbkz 985108618U, // VPMINUDZ128rmk 890572938U, // VPMINUDZ128rmkz 811651210U, // VPMINUDZ128rr 87052426U, // VPMINUDZ128rrk 890278026U, // VPMINUDZ128rrkz 812863626U, // VPMINUDZ256rm 362893450U, // VPMINUDZ256rmb 1438158986U, // VPMINUDZ256rmbk 1169576074U, // VPMINUDZ256rmbkz 985125002U, // VPMINUDZ256rmk 890605706U, // VPMINUDZ256rmkz 811651210U, // VPMINUDZ256rr 87052426U, // VPMINUDZ256rrk 890278026U, // VPMINUDZ256rrkz 812880010U, // VPMINUDZrm 364990602U, // VPMINUDZrmb 1440256138U, // VPMINUDZrmbk 1171673226U, // VPMINUDZrmbkz 985141386U, // VPMINUDZrmk 890671242U, // VPMINUDZrmkz 811651210U, // VPMINUDZrr 87052426U, // VPMINUDZrrk 890278026U, // VPMINUDZrrkz 811847818U, // VPMINUDrm 811651210U, // VPMINUDrr 811851804U, // VPMINUQZ128rm 358719516U, // VPMINUQZ128rmb 1433952284U, // VPMINUQZ128rmbk 1165287452U, // VPMINUQZ128rmbkz 985112604U, // VPMINUQZ128rmk 890576924U, // VPMINUQZ128rmkz 811655196U, // VPMINUQZ128rr 87056412U, // VPMINUQZ128rrk 890282012U, // VPMINUQZ128rrkz 812867612U, // VPMINUQZ256rm 360816668U, // VPMINUQZ256rmb 1436049436U, // VPMINUQZ256rmbk 1167384604U, // VPMINUQZ256rmbkz 985128988U, // VPMINUQZ256rmk 890609692U, // VPMINUQZ256rmkz 811655196U, // VPMINUQZ256rr 87056412U, // VPMINUQZ256rrk 890282012U, // VPMINUQZ256rrkz 812883996U, // VPMINUQZrm 362913820U, // VPMINUQZrmb 1438146588U, // VPMINUQZrmbk 1169481756U, // VPMINUQZrmbkz 985145372U, // VPMINUQZrmk 890675228U, // VPMINUQZrmkz 811655196U, // VPMINUQZrr 87056412U, // VPMINUQZrrk 890282012U, // VPMINUQZrrkz 812871500U, // VPMINUWYrm 811659084U, // VPMINUWYrr 811855692U, // VPMINUWZ128rm 985116492U, // VPMINUWZ128rmk 890580812U, // VPMINUWZ128rmkz 811659084U, // VPMINUWZ128rr 87060300U, // VPMINUWZ128rrk 890285900U, // VPMINUWZ128rrkz 812871500U, // VPMINUWZ256rm 985132876U, // VPMINUWZ256rmk 890613580U, // VPMINUWZ256rmkz 811659084U, // VPMINUWZ256rr 87060300U, // VPMINUWZ256rrk 890285900U, // VPMINUWZ256rrkz 812887884U, // VPMINUWZrm 985149260U, // VPMINUWZrmk 890679116U, // VPMINUWZrmkz 811659084U, // VPMINUWZrr 87060300U, // VPMINUWZrrk 890285900U, // VPMINUWZrrkz 811855692U, // VPMINUWrm 811659084U, // VPMINUWrr 551835633U, // VPMOVB2MZ128rr 551835633U, // VPMOVB2MZ256rr 551835633U, // VPMOVB2MZrr 551835643U, // VPMOVD2MZ128rr 551835643U, // VPMOVD2MZ256rr 551835643U, // VPMOVD2MZrr 12616736U, // VPMOVDBZ128mr 3234137120U, // VPMOVDBZ128mrk 551830560U, // VPMOVDBZ128rr 3230696480U, // VPMOVDBZ128rrk 3229664288U, // VPMOVDBZ128rrkz 18908192U, // VPMOVDBZ256mr 3240428576U, // VPMOVDBZ256mrk 551830560U, // VPMOVDBZ256rr 3230696480U, // VPMOVDBZ256rrk 3229664288U, // VPMOVDBZ256rrkz 33588256U, // VPMOVDBZmr 3255108640U, // VPMOVDBZmrk 551830560U, // VPMOVDBZrr 3230696480U, // VPMOVDBZrrk 3229664288U, // VPMOVDBZrrkz 18918314U, // VPMOVDWZ128mr 3240438698U, // VPMOVDWZ128mrk 551840682U, // VPMOVDWZ128rr 3230706602U, // VPMOVDWZ128rrk 3229674410U, // VPMOVDWZ128rrkz 33598378U, // VPMOVDWZ256mr 3255118762U, // VPMOVDWZ256mrk 551840682U, // VPMOVDWZ256rr 3230706602U, // VPMOVDWZ256rrk 3229674410U, // VPMOVDWZ256rrkz 180399018U, // VPMOVDWZmr 3401919402U, // VPMOVDWZmrk 551840682U, // VPMOVDWZrr 3230706602U, // VPMOVDWZrrk 3229674410U, // VPMOVDWZrrkz 551830389U, // VPMOVM2BZ128rr 551830389U, // VPMOVM2BZ256rr 551830389U, // VPMOVM2BZrr 551831343U, // VPMOVM2DZ128rr 551831343U, // VPMOVM2DZ256rr 551831343U, // VPMOVM2DZrr 551835977U, // VPMOVM2QZ128rr 551835977U, // VPMOVM2QZ256rr 551835977U, // VPMOVM2QZrr 551840291U, // VPMOVM2WZ128rr 551840291U, // VPMOVM2WZ256rr 551840291U, // VPMOVM2WZrr 551830606U, // VPMOVMSKBYrr 551830606U, // VPMOVMSKBrr 551835653U, // VPMOVQ2MZ128rr 551835653U, // VPMOVQ2MZ256rr 551835653U, // VPMOVQ2MZrr 4228423U, // VPMOVQBZ128mr 3225748807U, // VPMOVQBZ128mrk 551830855U, // VPMOVQBZ128rr 3230696775U, // VPMOVQBZ128rrk 3229664583U, // VPMOVQBZ128rrkz 12617031U, // VPMOVQBZ256mr 3234137415U, // VPMOVQBZ256mrk 551830855U, // VPMOVQBZ256rr 3230696775U, // VPMOVQBZ256rrk 3229664583U, // VPMOVQBZ256rrkz 18908487U, // VPMOVQBZmr 3240428871U, // VPMOVQBZmrk 551830855U, // VPMOVQBZrr 3230696775U, // VPMOVQBZrrk 3229664583U, // VPMOVQBZrrkz 18910619U, // VPMOVQDZ128mr 3240431003U, // VPMOVQDZ128mrk 551832987U, // VPMOVQDZ128rr 3230698907U, // VPMOVQDZ128rrk 3229666715U, // VPMOVQDZ128rrkz 33590683U, // VPMOVQDZ256mr 3255111067U, // VPMOVQDZ256mrk 551832987U, // VPMOVQDZ256rr 3230698907U, // VPMOVQDZ256rrk 3229666715U, // VPMOVQDZ256rrkz 180391323U, // VPMOVQDZmr 3401911707U, // VPMOVQDZmrk 551832987U, // VPMOVQDZrr 3230698907U, // VPMOVQDZrrk 3229666715U, // VPMOVQDZrrkz 12627287U, // VPMOVQWZ128mr 3234147671U, // VPMOVQWZ128mrk 551841111U, // VPMOVQWZ128rr 3230707031U, // VPMOVQWZ128rrk 3229674839U, // VPMOVQWZ128rrkz 18918743U, // VPMOVQWZ256mr 3240439127U, // VPMOVQWZ256mrk 551841111U, // VPMOVQWZ256rr 3230707031U, // VPMOVQWZ256rrk 3229674839U, // VPMOVQWZ256rrkz 33598807U, // VPMOVQWZmr 3255119191U, // VPMOVQWZmrk 551841111U, // VPMOVQWZrr 3230707031U, // VPMOVQWZrrk 3229674839U, // VPMOVQWZrrkz 12616726U, // VPMOVSDBZ128mr 3234137110U, // VPMOVSDBZ128mrk 551830550U, // VPMOVSDBZ128rr 3230696470U, // VPMOVSDBZ128rrk 3229664278U, // VPMOVSDBZ128rrkz 18908182U, // VPMOVSDBZ256mr 3240428566U, // VPMOVSDBZ256mrk 551830550U, // VPMOVSDBZ256rr 3230696470U, // VPMOVSDBZ256rrk 3229664278U, // VPMOVSDBZ256rrkz 33588246U, // VPMOVSDBZmr 3255108630U, // VPMOVSDBZmrk 551830550U, // VPMOVSDBZrr 3230696470U, // VPMOVSDBZrrk 3229664278U, // VPMOVSDBZrrkz 18918304U, // VPMOVSDWZ128mr 3240438688U, // VPMOVSDWZ128mrk 551840672U, // VPMOVSDWZ128rr 3230706592U, // VPMOVSDWZ128rrk 3229674400U, // VPMOVSDWZ128rrkz 33598368U, // VPMOVSDWZ256mr 3255118752U, // VPMOVSDWZ256mrk 551840672U, // VPMOVSDWZ256rr 3230706592U, // VPMOVSDWZ256rrk 3229674400U, // VPMOVSDWZ256rrkz 180399008U, // VPMOVSDWZmr 3401919392U, // VPMOVSDWZmrk 551840672U, // VPMOVSDWZrr 3230706592U, // VPMOVSDWZrrk 3229674400U, // VPMOVSDWZrrkz 4228378U, // VPMOVSQBZ128mr 3225748762U, // VPMOVSQBZ128mrk 551830810U, // VPMOVSQBZ128rr 3230696730U, // VPMOVSQBZ128rrk 3229664538U, // VPMOVSQBZ128rrkz 12616986U, // VPMOVSQBZ256mr 3234137370U, // VPMOVSQBZ256mrk 551830810U, // VPMOVSQBZ256rr 3230696730U, // VPMOVSQBZ256rrk 3229664538U, // VPMOVSQBZ256rrkz 18908442U, // VPMOVSQBZmr 3240428826U, // VPMOVSQBZmrk 551830810U, // VPMOVSQBZrr 3230696730U, // VPMOVSQBZrrk 3229664538U, // VPMOVSQBZrrkz 18910609U, // VPMOVSQDZ128mr 3240430993U, // VPMOVSQDZ128mrk 551832977U, // VPMOVSQDZ128rr 3230698897U, // VPMOVSQDZ128rrk 3229666705U, // VPMOVSQDZ128rrkz 33590673U, // VPMOVSQDZ256mr 3255111057U, // VPMOVSQDZ256mrk 551832977U, // VPMOVSQDZ256rr 3230698897U, // VPMOVSQDZ256rrk 3229666705U, // VPMOVSQDZ256rrkz 180391313U, // VPMOVSQDZmr 3401911697U, // VPMOVSQDZmrk 551832977U, // VPMOVSQDZrr 3230698897U, // VPMOVSQDZrrk 3229666705U, // VPMOVSQDZrrkz 12627277U, // VPMOVSQWZ128mr 3234147661U, // VPMOVSQWZ128mrk 551841101U, // VPMOVSQWZ128rr 3230707021U, // VPMOVSQWZ128rrk 3229674829U, // VPMOVSQWZ128rrkz 18918733U, // VPMOVSQWZ256mr 3240439117U, // VPMOVSQWZ256mrk 551841101U, // VPMOVSQWZ256rr 3230707021U, // VPMOVSQWZ256rrk 3229674829U, // VPMOVSQWZ256rrkz 33598797U, // VPMOVSQWZmr 3255119181U, // VPMOVSQWZmrk 551841101U, // VPMOVSQWZrr 3230707021U, // VPMOVSQWZrrk 3229674829U, // VPMOVSQWZrrkz 18908887U, // VPMOVSWBZ128mr 3240429271U, // VPMOVSWBZ128mrk 551831255U, // VPMOVSWBZ128rr 3230697175U, // VPMOVSWBZ128rrk 3229664983U, // VPMOVSWBZ128rrkz 33588951U, // VPMOVSWBZ256mr 3255109335U, // VPMOVSWBZ256mrk 551831255U, // VPMOVSWBZ256rr 3230697175U, // VPMOVSWBZ256rrk 3229664983U, // VPMOVSWBZ256rrkz 180389591U, // VPMOVSWBZmr 3401909975U, // VPMOVSWBZmrk 551831255U, // VPMOVSWBZrr 3230697175U, // VPMOVSWBZrrk 3229664983U, // VPMOVSWBZrrkz 551913359U, // VPMOVSXBDYrm 551831439U, // VPMOVSXBDYrr 551896975U, // VPMOVSXBDZ128rm 553011087U, // VPMOVSXBDZ128rmk 551634831U, // VPMOVSXBDZ128rmkz 551831439U, // VPMOVSXBDZ128rr 3230697359U, // VPMOVSXBDZ128rrk 3229665167U, // VPMOVSXBDZ128rrkz 551913359U, // VPMOVSXBDZ256rm 552912783U, // VPMOVSXBDZ256rmk 551651215U, // VPMOVSXBDZ256rmkz 551831439U, // VPMOVSXBDZ256rr 3230697359U, // VPMOVSXBDZ256rrk 3229665167U, // VPMOVSXBDZ256rrkz 264079U, // VPMOVSXBDZrm 3230992271U, // VPMOVSXBDZrmk 3229861775U, // VPMOVSXBDZrmkz 551831439U, // VPMOVSXBDZrr 3230697359U, // VPMOVSXBDZrrk 3229665167U, // VPMOVSXBDZrrkz 551896975U, // VPMOVSXBDrm 551831439U, // VPMOVSXBDrr 551901623U, // VPMOVSXBQYrm 551836087U, // VPMOVSXBQYrr 432567U, // VPMOVSXBQZ128rm 1644983U, // VPMOVSXBQZ128rmk 3229686199U, // VPMOVSXBQZ128rmkz 551836087U, // VPMOVSXBQZ128rr 3230702007U, // VPMOVSXBQZ128rrk 3229669815U, // VPMOVSXBQZ128rrkz 551901623U, // VPMOVSXBQZ256rm 553015735U, // VPMOVSXBQZ256rmk 551639479U, // VPMOVSXBQZ256rmkz 551836087U, // VPMOVSXBQZ256rr 3230702007U, // VPMOVSXBQZ256rrk 3229669815U, // VPMOVSXBQZ256rrkz 551918007U, // VPMOVSXBQZrm 552917431U, // VPMOVSXBQZrmk 551655863U, // VPMOVSXBQZrmkz 551836087U, // VPMOVSXBQZrr 3230702007U, // VPMOVSXBQZrrk 3229669815U, // VPMOVSXBQZrrkz 432567U, // VPMOVSXBQrm 551836087U, // VPMOVSXBQrr 273115U, // VPMOVSXBWYrm 551840475U, // VPMOVSXBWYrr 551922395U, // VPMOVSXBWZ128rm 552921819U, // VPMOVSXBWZ128rmk 551660251U, // VPMOVSXBWZ128rmkz 551840475U, // VPMOVSXBWZ128rr 3230706395U, // VPMOVSXBWZ128rrk 3229674203U, // VPMOVSXBWZ128rrkz 273115U, // VPMOVSXBWZ256rm 3231001307U, // VPMOVSXBWZ256rmk 3229870811U, // VPMOVSXBWZ256rmkz 551840475U, // VPMOVSXBWZ256rr 3230706395U, // VPMOVSXBWZ256rrk 3229674203U, // VPMOVSXBWZ256rrkz 552954587U, // VPMOVSXBWZrm 3231034075U, // VPMOVSXBWZrmk 3230886619U, // VPMOVSXBWZrmkz 551840475U, // VPMOVSXBWZrr 3230706395U, // VPMOVSXBWZrrk 3229674203U, // VPMOVSXBWZrrkz 551922395U, // VPMOVSXBWrm 551840475U, // VPMOVSXBWrr 269217U, // VPMOVSXDQYrm 551836577U, // VPMOVSXDQYrr 551918497U, // VPMOVSXDQZ128rm 552917921U, // VPMOVSXDQZ128rmk 551656353U, // VPMOVSXDQZ128rmkz 551836577U, // VPMOVSXDQZ128rr 3230702497U, // VPMOVSXDQZ128rrk 3229670305U, // VPMOVSXDQZ128rrkz 269217U, // VPMOVSXDQZ256rm 3230997409U, // VPMOVSXDQZ256rmk 3229866913U, // VPMOVSXDQZ256rmkz 551836577U, // VPMOVSXDQZ256rr 3230702497U, // VPMOVSXDQZ256rrk 3229670305U, // VPMOVSXDQZ256rrkz 552950689U, // VPMOVSXDQZrm 3231030177U, // VPMOVSXDQZrmk 3230882721U, // VPMOVSXDQZrmkz 551836577U, // VPMOVSXDQZrr 3230702497U, // VPMOVSXDQZrrk 3229670305U, // VPMOVSXDQZrrkz 551918497U, // VPMOVSXDQrm 551836577U, // VPMOVSXDQrr 266608U, // VPMOVSXWDYrm 551833968U, // VPMOVSXWDYrr 551915888U, // VPMOVSXWDZ128rm 552915312U, // VPMOVSXWDZ128rmk 551653744U, // VPMOVSXWDZ128rmkz 551833968U, // VPMOVSXWDZ128rr 3230699888U, // VPMOVSXWDZ128rrk 3229667696U, // VPMOVSXWDZ128rrkz 266608U, // VPMOVSXWDZ256rm 3230994800U, // VPMOVSXWDZ256rmk 3229864304U, // VPMOVSXWDZ256rmkz 551833968U, // VPMOVSXWDZ256rr 3230699888U, // VPMOVSXWDZ256rrk 3229667696U, // VPMOVSXWDZ256rrkz 552948080U, // VPMOVSXWDZrm 3231027568U, // VPMOVSXWDZrmk 3230880112U, // VPMOVSXWDZrmkz 551833968U, // VPMOVSXWDZrr 3230699888U, // VPMOVSXWDZrrk 3229667696U, // VPMOVSXWDZrrkz 551915888U, // VPMOVSXWDrm 551833968U, // VPMOVSXWDrr 551919798U, // VPMOVSXWQYrm 551837878U, // VPMOVSXWQYrr 551903414U, // VPMOVSXWQZ128rm 553017526U, // VPMOVSXWQZ128rmk 551641270U, // VPMOVSXWQZ128rmkz 551837878U, // VPMOVSXWQZ128rr 3230703798U, // VPMOVSXWQZ128rrk 3229671606U, // VPMOVSXWQZ128rrkz 551919798U, // VPMOVSXWQZ256rm 552919222U, // VPMOVSXWQZ256rmk 551657654U, // VPMOVSXWQZ256rmkz 551837878U, // VPMOVSXWQZ256rr 3230703798U, // VPMOVSXWQZ256rrk 3229671606U, // VPMOVSXWQZ256rrkz 270518U, // VPMOVSXWQZrm 3230998710U, // VPMOVSXWQZrmk 3229868214U, // VPMOVSXWQZrmkz 551837878U, // VPMOVSXWQZrr 3230703798U, // VPMOVSXWQZrrk 3229671606U, // VPMOVSXWQZrrkz 551903414U, // VPMOVSXWQrm 551837878U, // VPMOVSXWQrr 12616715U, // VPMOVUSDBZ128mr 3234137099U, // VPMOVUSDBZ128mrk 551830539U, // VPMOVUSDBZ128rr 3230696459U, // VPMOVUSDBZ128rrk 3229664267U, // VPMOVUSDBZ128rrkz 18908171U, // VPMOVUSDBZ256mr 3240428555U, // VPMOVUSDBZ256mrk 551830539U, // VPMOVUSDBZ256rr 3230696459U, // VPMOVUSDBZ256rrk 3229664267U, // VPMOVUSDBZ256rrkz 33588235U, // VPMOVUSDBZmr 3255108619U, // VPMOVUSDBZmrk 551830539U, // VPMOVUSDBZrr 3230696459U, // VPMOVUSDBZrrk 3229664267U, // VPMOVUSDBZrrkz 18918293U, // VPMOVUSDWZ128mr 3240438677U, // VPMOVUSDWZ128mrk 551840661U, // VPMOVUSDWZ128rr 3230706581U, // VPMOVUSDWZ128rrk 3229674389U, // VPMOVUSDWZ128rrkz 33598357U, // VPMOVUSDWZ256mr 3255118741U, // VPMOVUSDWZ256mrk 551840661U, // VPMOVUSDWZ256rr 3230706581U, // VPMOVUSDWZ256rrk 3229674389U, // VPMOVUSDWZ256rrkz 180398997U, // VPMOVUSDWZmr 3401919381U, // VPMOVUSDWZmrk 551840661U, // VPMOVUSDWZrr 3230706581U, // VPMOVUSDWZrrk 3229674389U, // VPMOVUSDWZrrkz 4228367U, // VPMOVUSQBZ128mr 3225748751U, // VPMOVUSQBZ128mrk 551830799U, // VPMOVUSQBZ128rr 3230696719U, // VPMOVUSQBZ128rrk 3229664527U, // VPMOVUSQBZ128rrkz 12616975U, // VPMOVUSQBZ256mr 3234137359U, // VPMOVUSQBZ256mrk 551830799U, // VPMOVUSQBZ256rr 3230696719U, // VPMOVUSQBZ256rrk 3229664527U, // VPMOVUSQBZ256rrkz 18908431U, // VPMOVUSQBZmr 3240428815U, // VPMOVUSQBZmrk 551830799U, // VPMOVUSQBZrr 3230696719U, // VPMOVUSQBZrrk 3229664527U, // VPMOVUSQBZrrkz 18910598U, // VPMOVUSQDZ128mr 3240430982U, // VPMOVUSQDZ128mrk 551832966U, // VPMOVUSQDZ128rr 3230698886U, // VPMOVUSQDZ128rrk 3229666694U, // VPMOVUSQDZ128rrkz 33590662U, // VPMOVUSQDZ256mr 3255111046U, // VPMOVUSQDZ256mrk 551832966U, // VPMOVUSQDZ256rr 3230698886U, // VPMOVUSQDZ256rrk 3229666694U, // VPMOVUSQDZ256rrkz 180391302U, // VPMOVUSQDZmr 3401911686U, // VPMOVUSQDZmrk 551832966U, // VPMOVUSQDZrr 3230698886U, // VPMOVUSQDZrrk 3229666694U, // VPMOVUSQDZrrkz 12627266U, // VPMOVUSQWZ128mr 3234147650U, // VPMOVUSQWZ128mrk 551841090U, // VPMOVUSQWZ128rr 3230707010U, // VPMOVUSQWZ128rrk 3229674818U, // VPMOVUSQWZ128rrkz 18918722U, // VPMOVUSQWZ256mr 3240439106U, // VPMOVUSQWZ256mrk 551841090U, // VPMOVUSQWZ256rr 3230707010U, // VPMOVUSQWZ256rrk 3229674818U, // VPMOVUSQWZ256rrkz 33598786U, // VPMOVUSQWZmr 3255119170U, // VPMOVUSQWZmrk 551841090U, // VPMOVUSQWZrr 3230707010U, // VPMOVUSQWZrrk 3229674818U, // VPMOVUSQWZrrkz 18908876U, // VPMOVUSWBZ128mr 3240429260U, // VPMOVUSWBZ128mrk 551831244U, // VPMOVUSWBZ128rr 3230697164U, // VPMOVUSWBZ128rrk 3229664972U, // VPMOVUSWBZ128rrkz 33588940U, // VPMOVUSWBZ256mr 3255109324U, // VPMOVUSWBZ256mrk 551831244U, // VPMOVUSWBZ256rr 3230697164U, // VPMOVUSWBZ256rrk 3229664972U, // VPMOVUSWBZ256rrkz 180389580U, // VPMOVUSWBZmr 3401909964U, // VPMOVUSWBZmrk 551831244U, // VPMOVUSWBZrr 3230697164U, // VPMOVUSWBZrrk 3229664972U, // VPMOVUSWBZrrkz 551835663U, // VPMOVW2MZ128rr 551835663U, // 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VPMOVZXWQZ128rmkz 551837889U, // VPMOVZXWQZ128rr 3230703809U, // VPMOVZXWQZ128rrk 3229671617U, // VPMOVZXWQZ128rrkz 551919809U, // VPMOVZXWQZ256rm 552919233U, // VPMOVZXWQZ256rmk 551657665U, // VPMOVZXWQZ256rmkz 551837889U, // VPMOVZXWQZ256rr 3230703809U, // VPMOVZXWQZ256rrk 3229671617U, // VPMOVZXWQZ256rrkz 270529U, // VPMOVZXWQZrm 3230998721U, // VPMOVZXWQZrmk 3229868225U, // VPMOVZXWQZrmkz 551837889U, // VPMOVZXWQZrr 3230703809U, // VPMOVZXWQZrrk 3229671617U, // VPMOVZXWQZrrkz 551903425U, // VPMOVZXWQrm 551837889U, // VPMOVZXWQrr 812866230U, // VPMULDQYrm 811653814U, // VPMULDQYrr 811850422U, // VPMULDQZ128rm 358718134U, // VPMULDQZ128rmb 1433950902U, // VPMULDQZ128rmbk 1165286070U, // VPMULDQZ128rmbkz 985111222U, // VPMULDQZ128rmk 890575542U, // VPMULDQZ128rmkz 811653814U, // VPMULDQZ128rr 87055030U, // VPMULDQZ128rrk 890280630U, // VPMULDQZ128rrkz 812866230U, // VPMULDQZ256rm 360815286U, // VPMULDQZ256rmb 1436048054U, // VPMULDQZ256rmbk 1167383222U, // VPMULDQZ256rmbkz 985127606U, // VPMULDQZ256rmk 890608310U, // VPMULDQZ256rmkz 811653814U, // VPMULDQZ256rr 87055030U, // VPMULDQZ256rrk 890280630U, // VPMULDQZ256rrkz 812882614U, // VPMULDQZrm 362912438U, // VPMULDQZrmb 1438145206U, // VPMULDQZrmbk 1169480374U, // VPMULDQZrmbkz 985143990U, // VPMULDQZrmk 890673846U, // VPMULDQZrmkz 811653814U, // VPMULDQZrr 87055030U, // VPMULDQZrrk 890280630U, // VPMULDQZrrkz 811850422U, // VPMULDQrm 811653814U, // VPMULDQrr 812871256U, // VPMULHRSWYrm 811658840U, // VPMULHRSWYrr 811855448U, // VPMULHRSWZ128rm 985116248U, // VPMULHRSWZ128rmk 890580568U, // VPMULHRSWZ128rmkz 811658840U, // VPMULHRSWZ128rr 87060056U, // VPMULHRSWZ128rrk 890285656U, // VPMULHRSWZ128rrkz 812871256U, // VPMULHRSWZ256rm 985132632U, // VPMULHRSWZ256rmk 890613336U, // VPMULHRSWZ256rmkz 811658840U, // VPMULHRSWZ256rr 87060056U, // VPMULHRSWZ256rrk 890285656U, // VPMULHRSWZ256rrkz 812887640U, // VPMULHRSWZrm 985149016U, // VPMULHRSWZrmk 890678872U, // VPMULHRSWZrmkz 811658840U, // VPMULHRSWZrr 87060056U, // VPMULHRSWZrrk 890285656U, // VPMULHRSWZrrkz 811855448U, // VPMULHRSWrm 811658840U, // VPMULHRSWrr 812871481U, // VPMULHUWYrm 811659065U, // VPMULHUWYrr 811855673U, // VPMULHUWZ128rm 985116473U, // VPMULHUWZ128rmk 890580793U, // VPMULHUWZ128rmkz 811659065U, // VPMULHUWZ128rr 87060281U, // VPMULHUWZ128rrk 890285881U, // VPMULHUWZ128rrkz 812871481U, // VPMULHUWZ256rm 985132857U, // VPMULHUWZ256rmk 890613561U, // VPMULHUWZ256rmkz 811659065U, // VPMULHUWZ256rr 87060281U, // VPMULHUWZ256rrk 890285881U, // VPMULHUWZ256rrkz 812887865U, // VPMULHUWZrm 985149241U, // VPMULHUWZrmk 890679097U, // VPMULHUWZrmkz 811659065U, // VPMULHUWZrr 87060281U, // VPMULHUWZrrk 890285881U, // VPMULHUWZrrkz 811855673U, // VPMULHUWrm 811659065U, // VPMULHUWrr 812870706U, // VPMULHWYrm 811658290U, // VPMULHWYrr 811854898U, // VPMULHWZ128rm 985115698U, // VPMULHWZ128rmk 890580018U, // VPMULHWZ128rmkz 811658290U, // VPMULHWZ128rr 87059506U, // VPMULHWZ128rrk 890285106U, // VPMULHWZ128rrkz 812870706U, // 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VPMULLQZrr 87055573U, // VPMULLQZrrk 890281173U, // VPMULLQZrrkz 812870775U, // VPMULLWYrm 811658359U, // VPMULLWYrr 811854967U, // VPMULLWZ128rm 985115767U, // VPMULLWZ128rmk 890580087U, // VPMULLWZ128rmkz 811658359U, // VPMULLWZ128rr 87059575U, // VPMULLWZ128rrk 890285175U, // VPMULLWZ128rrkz 812870775U, // VPMULLWZ256rm 985132151U, // VPMULLWZ256rmk 890612855U, // VPMULLWZ256rmkz 811658359U, // VPMULLWZ256rr 87059575U, // VPMULLWZ256rrk 890285175U, // VPMULLWZ256rrkz 812887159U, // VPMULLWZrm 985148535U, // VPMULLWZrmk 890678391U, // VPMULLWZrmkz 811658359U, // VPMULLWZrr 87059575U, // VPMULLWZrrk 890285175U, // VPMULLWZrrkz 811854967U, // VPMULLWrm 811658359U, // VPMULLWrr 811844900U, // VPMULTISHIFTQBZ128rm 358712612U, // VPMULTISHIFTQBZ128rmb 1433945380U, // VPMULTISHIFTQBZ128rmbk 1165280548U, // VPMULTISHIFTQBZ128rmbkz 985105700U, // VPMULTISHIFTQBZ128rmk 890570020U, // VPMULTISHIFTQBZ128rmkz 811648292U, // VPMULTISHIFTQBZ128rr 87049508U, // VPMULTISHIFTQBZ128rrk 890275108U, // VPMULTISHIFTQBZ128rrkz 812860708U, // VPMULTISHIFTQBZ256rm 360809764U, // VPMULTISHIFTQBZ256rmb 1436042532U, // VPMULTISHIFTQBZ256rmbk 1167377700U, // VPMULTISHIFTQBZ256rmbkz 985122084U, // VPMULTISHIFTQBZ256rmk 890602788U, // VPMULTISHIFTQBZ256rmkz 811648292U, // VPMULTISHIFTQBZ256rr 87049508U, // VPMULTISHIFTQBZ256rrk 890275108U, // VPMULTISHIFTQBZ256rrkz 812877092U, // VPMULTISHIFTQBZrm 362906916U, // VPMULTISHIFTQBZrmb 1438139684U, // VPMULTISHIFTQBZrmbk 1169474852U, // VPMULTISHIFTQBZrmbkz 985138468U, // VPMULTISHIFTQBZrmk 890668324U, // VPMULTISHIFTQBZrmkz 811648292U, // VPMULTISHIFTQBZrr 87049508U, // VPMULTISHIFTQBZrrk 890275108U, // VPMULTISHIFTQBZrrkz 812866455U, // VPMULUDQYrm 811654039U, // VPMULUDQYrr 811850647U, // VPMULUDQZ128rm 358718359U, // VPMULUDQZ128rmb 1433951127U, // VPMULUDQZ128rmbk 1165286295U, // VPMULUDQZ128rmbkz 985111447U, // VPMULUDQZ128rmk 890575767U, // VPMULUDQZ128rmkz 811654039U, // VPMULUDQZ128rr 87055255U, // VPMULUDQZ128rrk 890280855U, // VPMULUDQZ128rrkz 812866455U, // VPMULUDQZ256rm 360815511U, // VPMULUDQZ256rmb 1436048279U, // VPMULUDQZ256rmbk 1167383447U, // VPMULUDQZ256rmbkz 985127831U, // VPMULUDQZ256rmk 890608535U, // VPMULUDQZ256rmkz 811654039U, // VPMULUDQZ256rr 87055255U, // VPMULUDQZ256rrk 890280855U, // VPMULUDQZ256rrkz 812882839U, // VPMULUDQZrm 362912663U, // VPMULUDQZrmb 1438145431U, // VPMULUDQZrmbk 1169480599U, // VPMULUDQZrmbkz 985144215U, // VPMULUDQZrmk 890674071U, // VPMULUDQZrmkz 811654039U, // VPMULUDQZrr 87055255U, // VPMULUDQZrrk 890280855U, // VPMULUDQZrrkz 811850647U, // VPMULUDQrm 811654039U, // VPMULUDQrr 263723U, // VPOPCNTBZ128rm 3230991915U, // VPOPCNTBZ128rmk 3229861419U, // VPOPCNTBZ128rmkz 551831083U, // VPOPCNTBZ128rr 3230697003U, // VPOPCNTBZ128rrk 3229664811U, // VPOPCNTBZ128rrkz 552945195U, // VPOPCNTBZ256rm 3231024683U, // VPOPCNTBZ256rmk 3230877227U, // VPOPCNTBZ256rmkz 551831083U, // VPOPCNTBZ256rr 3230697003U, // VPOPCNTBZ256rrk 3229664811U, // VPOPCNTBZ256rrkz 552437291U, // VPOPCNTBZrm 3231090219U, // VPOPCNTBZrmk 3230893611U, // VPOPCNTBZrmkz 551831083U, // VPOPCNTBZrr 3230697003U, // VPOPCNTBZrrk 3229664811U, // VPOPCNTBZrrkz 266302U, // VPOPCNTDZ128rm 629493822U, // VPOPCNTDZ128rmb 630607934U, // VPOPCNTDZ128rmbk 629231678U, // VPOPCNTDZ128rmbkz 3230994494U, // VPOPCNTDZ128rmk 3229863998U, // VPOPCNTDZ128rmkz 551833662U, // VPOPCNTDZ128rr 3230699582U, // VPOPCNTDZ128rrk 3229667390U, // VPOPCNTDZ128rrkz 552947774U, // VPOPCNTDZ256rm 631590974U, // VPOPCNTDZ256rmb 632705086U, // VPOPCNTDZ256rmbk 631328830U, // VPOPCNTDZ256rmbkz 3231027262U, // VPOPCNTDZ256rmk 3230879806U, // VPOPCNTDZ256rmkz 551833662U, // VPOPCNTDZ256rr 3230699582U, // VPOPCNTDZ256rrk 3229667390U, // VPOPCNTDZ256rrkz 552439870U, // VPOPCNTDZrm 633688126U, // VPOPCNTDZrmb 634802238U, // VPOPCNTDZrmbk 633425982U, // VPOPCNTDZrmbkz 3231092798U, // VPOPCNTDZrmk 3230896190U, // VPOPCNTDZrmkz 551833662U, // VPOPCNTDZrr 3230699582U, // VPOPCNTDZrrk 3229667390U, // VPOPCNTDZrrkz 270230U, // VPOPCNTQZ128rm 627416982U, // VPOPCNTQZ128rmb 628416406U, // VPOPCNTQZ128rmbk 627154838U, // VPOPCNTQZ128rmbkz 3230998422U, // VPOPCNTQZ128rmk 3229867926U, // VPOPCNTQZ128rmkz 551837590U, // VPOPCNTQZ128rr 3230703510U, // VPOPCNTQZ128rrk 3229671318U, // VPOPCNTQZ128rrkz 552951702U, // VPOPCNTQZ256rm 629514134U, // VPOPCNTQZ256rmb 630513558U, // VPOPCNTQZ256rmbk 629251990U, // VPOPCNTQZ256rmbkz 3231031190U, // VPOPCNTQZ256rmk 3230883734U, // VPOPCNTQZ256rmkz 551837590U, // VPOPCNTQZ256rr 3230703510U, // VPOPCNTQZ256rrk 3229671318U, // VPOPCNTQZ256rrkz 552443798U, // VPOPCNTQZrm 631611286U, // VPOPCNTQZrmb 632610710U, // VPOPCNTQZrmbk 631349142U, // VPOPCNTQZrmbkz 3231096726U, // VPOPCNTQZrmk 3230900118U, // VPOPCNTQZrmkz 551837590U, // VPOPCNTQZrr 3230703510U, // VPOPCNTQZrrk 3229671318U, // VPOPCNTQZrrkz 274160U, // VPOPCNTWZ128rm 3231002352U, // VPOPCNTWZ128rmk 3229871856U, // VPOPCNTWZ128rmkz 551841520U, // VPOPCNTWZ128rr 3230707440U, // VPOPCNTWZ128rrk 3229675248U, // VPOPCNTWZ128rrkz 552955632U, // VPOPCNTWZ256rm 3231035120U, // VPOPCNTWZ256rmk 3230887664U, // VPOPCNTWZ256rmkz 551841520U, // VPOPCNTWZ256rr 3230707440U, // VPOPCNTWZ256rrk 3229675248U, // VPOPCNTWZ256rrkz 552447728U, // VPOPCNTWZrm 3231100656U, // VPOPCNTWZrmk 3230904048U, // VPOPCNTWZrmkz 551841520U, // VPOPCNTWZrr 3230707440U, // VPOPCNTWZrrk 3229675248U, // VPOPCNTWZrrkz 811847090U, // VPORDZ128rm 360795570U, // VPORDZ128rmb 1436061106U, // VPORDZ128rmbk 1167478194U, // VPORDZ128rmbkz 985107890U, // VPORDZ128rmk 890572210U, // VPORDZ128rmkz 811650482U, // VPORDZ128rr 87051698U, // VPORDZ128rrk 890277298U, // VPORDZ128rrkz 812862898U, // VPORDZ256rm 362892722U, // VPORDZ256rmb 1438158258U, // VPORDZ256rmbk 1169575346U, // VPORDZ256rmbkz 985124274U, // VPORDZ256rmk 890604978U, // VPORDZ256rmkz 811650482U, // VPORDZ256rr 87051698U, // VPORDZ256rrk 890277298U, // VPORDZ256rrkz 812879282U, // VPORDZrm 364989874U, // VPORDZrmb 1440255410U, // VPORDZrmbk 1171672498U, // VPORDZrmbkz 985140658U, // VPORDZrmk 890670514U, // VPORDZrmkz 811650482U, // VPORDZrr 87051698U, // VPORDZrrk 890277298U, // VPORDZrrkz 811851358U, // VPORQZ128rm 358719070U, // VPORQZ128rmb 1433951838U, // VPORQZ128rmbk 1165287006U, // VPORQZ128rmbkz 985112158U, // VPORQZ128rmk 890576478U, // VPORQZ128rmkz 811654750U, // VPORQZ128rr 87055966U, // VPORQZ128rrk 890281566U, // VPORQZ128rrkz 812867166U, // VPORQZ256rm 360816222U, // VPORQZ256rmb 1436048990U, // VPORQZ256rmbk 1167384158U, // VPORQZ256rmbkz 985128542U, // VPORQZ256rmk 890609246U, // VPORQZ256rmkz 811654750U, // VPORQZ256rr 87055966U, // VPORQZ256rrk 890281566U, // VPORQZ256rrkz 812883550U, // VPORQZrm 362913374U, // VPORQZrmb 1438146142U, // VPORQZrmbk 1169481310U, // VPORQZrmbkz 985144926U, // VPORQZrmk 890674782U, // VPORQZrmkz 811654750U, // VPORQZrr 87055966U, // VPORQZrrk 890281566U, // VPORQZrrkz 812867879U, // VPORYrm 811655463U, // VPORYrr 811852071U, // VPORrm 811655463U, // VPORrr 326391851U, // VPPERMrmr 890574891U, // VPPERMrrm 890279979U, // VPPERMrrr 890279979U, // VPPERMrrr_REV 1638172802U, // VPROLDZ128mbi 1712588930U, // VPROLDZ128mbik 1686489218U, // VPROLDZ128mbikz 830769282U, // VPROLDZ128mi 643041410U, // VPROLDZ128mik 593873026U, // VPROLDZ128mikz 283428994U, // VPROLDZ128ri 1357580418U, // VPROLDZ128rik 1088817282U, // VPROLDZ128rikz 2443479170U, // VPROLDZ256mbi 2517895298U, // VPROLDZ256mbik 2491795586U, // VPROLDZ256mbikz 1009027202U, // VPROLDZ256mi 649332866U, // VPROLDZ256mik 644204674U, // VPROLDZ256mikz 283428994U, // VPROLDZ256ri 1357580418U, // VPROLDZ256rik 1088817282U, // VPROLDZ256rikz 2711914626U, // VPROLDZmbi 2786330754U, // VPROLDZmbik 2760231042U, // VPROLDZmbikz 1011124354U, // VPROLDZmi 655624322U, // VPROLDZmik 650496130U, // VPROLDZmikz 283428994U, // VPROLDZri 1357580418U, // VPROLDZrik 1088817282U, // VPROLDZrikz 2982452446U, // VPROLQZ128mbi 3075742942U, // VPROLQZ128mbik 3013991646U, // VPROLQZ128mbikz 830774494U, // VPROLQZ128mi 643046622U, // VPROLQZ128mik 593878238U, // VPROLQZ128mikz 283434206U, // VPROLQZ128ri 1357585630U, // VPROLQZ128rik 1088822494U, // VPROLQZ128rikz 1640275166U, // VPROLQZ256mbi 1733565662U, // VPROLQZ256mbik 1671814366U, // VPROLQZ256mbikz 1009032414U, // VPROLQZ256mi 649338078U, // VPROLQZ256mik 644209886U, // VPROLQZ256mikz 283434206U, // VPROLQZ256ri 1357585630U, // VPROLQZ256rik 1088822494U, // VPROLQZ256rikz 2445581534U, // VPROLQZmbi 2538872030U, // VPROLQZmbik 2477120734U, // VPROLQZmbikz 1011129566U, // VPROLQZmi 655629534U, // VPROLQZmik 650501342U, // VPROLQZmikz 283434206U, // VPROLQZri 1357585630U, // VPROLQZrik 1088822494U, // VPROLQZrikz 811847883U, // VPROLVDZ128rm 360796363U, // VPROLVDZ128rmb 1436061899U, // VPROLVDZ128rmbk 1167478987U, // VPROLVDZ128rmbkz 985108683U, // VPROLVDZ128rmk 890573003U, // VPROLVDZ128rmkz 811651275U, // VPROLVDZ128rr 87052491U, // VPROLVDZ128rrk 890278091U, // VPROLVDZ128rrkz 812863691U, // VPROLVDZ256rm 362893515U, // VPROLVDZ256rmb 1438159051U, // VPROLVDZ256rmbk 1169576139U, // VPROLVDZ256rmbkz 985125067U, // VPROLVDZ256rmk 890605771U, // VPROLVDZ256rmkz 811651275U, // VPROLVDZ256rr 87052491U, // VPROLVDZ256rrk 890278091U, // VPROLVDZ256rrkz 812880075U, // VPROLVDZrm 364990667U, // VPROLVDZrmb 1440256203U, // VPROLVDZrmbk 1171673291U, // VPROLVDZrmbkz 985141451U, // VPROLVDZrmk 890671307U, // VPROLVDZrmkz 811651275U, // VPROLVDZrr 87052491U, // VPROLVDZrrk 890278091U, // VPROLVDZrrkz 811851876U, // VPROLVQZ128rm 358719588U, // VPROLVQZ128rmb 1433952356U, // VPROLVQZ128rmbk 1165287524U, // VPROLVQZ128rmbkz 985112676U, // VPROLVQZ128rmk 890576996U, // VPROLVQZ128rmkz 811655268U, // VPROLVQZ128rr 87056484U, // VPROLVQZ128rrk 890282084U, // VPROLVQZ128rrkz 812867684U, // VPROLVQZ256rm 360816740U, // VPROLVQZ256rmb 1436049508U, // VPROLVQZ256rmbk 1167384676U, // VPROLVQZ256rmbkz 985129060U, // VPROLVQZ256rmk 890609764U, // VPROLVQZ256rmkz 811655268U, // VPROLVQZ256rr 87056484U, // VPROLVQZ256rrk 890282084U, // VPROLVQZ256rrkz 812884068U, // VPROLVQZrm 362913892U, // VPROLVQZrmb 1438146660U, // VPROLVQZrmbk 1169481828U, // VPROLVQZrmbkz 985145444U, // VPROLVQZrmk 890675300U, // VPROLVQZrmkz 811655268U, // VPROLVQZrr 87056484U, // VPROLVQZrrk 890282084U, // VPROLVQZrrkz 1638174137U, // VPRORDZ128mbi 1712590265U, // VPRORDZ128mbik 1686490553U, // VPRORDZ128mbikz 830770617U, // VPRORDZ128mi 643042745U, // VPRORDZ128mik 593874361U, // VPRORDZ128mikz 283430329U, // VPRORDZ128ri 1357581753U, // VPRORDZ128rik 1088818617U, // VPRORDZ128rikz 2443480505U, // VPRORDZ256mbi 2517896633U, // VPRORDZ256mbik 2491796921U, // VPRORDZ256mbikz 1009028537U, // VPRORDZ256mi 649334201U, // VPRORDZ256mik 644206009U, // VPRORDZ256mikz 283430329U, // VPRORDZ256ri 1357581753U, // VPRORDZ256rik 1088818617U, // VPRORDZ256rikz 2711915961U, // VPRORDZmbi 2786332089U, // VPRORDZmbik 2760232377U, // VPRORDZmbikz 1011125689U, // VPRORDZmi 655625657U, // VPRORDZmik 650497465U, // VPRORDZmikz 283430329U, // VPRORDZri 1357581753U, // VPRORDZrik 1088818617U, // VPRORDZrikz 2982452837U, // VPRORQZ128mbi 3075743333U, // VPRORQZ128mbik 3013992037U, // VPRORQZ128mbikz 830774885U, // VPRORQZ128mi 643047013U, // VPRORQZ128mik 593878629U, // VPRORQZ128mikz 283434597U, // VPRORQZ128ri 1357586021U, // VPRORQZ128rik 1088822885U, // VPRORQZ128rikz 1640275557U, // VPRORQZ256mbi 1733566053U, // VPRORQZ256mbik 1671814757U, // VPRORQZ256mbikz 1009032805U, // VPRORQZ256mi 649338469U, // VPRORQZ256mik 644210277U, // VPRORQZ256mikz 283434597U, // VPRORQZ256ri 1357586021U, // VPRORQZ256rik 1088822885U, // VPRORQZ256rikz 2445581925U, // VPRORQZmbi 2538872421U, // VPRORQZmbik 2477121125U, // VPRORQZmbikz 1011129957U, // VPRORQZmi 655629925U, // VPRORQZmik 650501733U, // VPRORQZmikz 283434597U, // VPRORQZri 1357586021U, // VPRORQZrik 1088822885U, // VPRORQZrikz 811847920U, // VPRORVDZ128rm 360796400U, // VPRORVDZ128rmb 1436061936U, // VPRORVDZ128rmbk 1167479024U, // VPRORVDZ128rmbkz 985108720U, // VPRORVDZ128rmk 890573040U, // VPRORVDZ128rmkz 811651312U, // VPRORVDZ128rr 87052528U, // VPRORVDZ128rrk 890278128U, // VPRORVDZ128rrkz 812863728U, // VPRORVDZ256rm 362893552U, // VPRORVDZ256rmb 1438159088U, // VPRORVDZ256rmbk 1169576176U, // VPRORVDZ256rmbkz 985125104U, // VPRORVDZ256rmk 890605808U, // VPRORVDZ256rmkz 811651312U, // VPRORVDZ256rr 87052528U, // VPRORVDZ256rrk 890278128U, // VPRORVDZ256rrkz 812880112U, // VPRORVDZrm 364990704U, // VPRORVDZrmb 1440256240U, // VPRORVDZrmbk 1171673328U, // VPRORVDZrmbkz 985141488U, // VPRORVDZrmk 890671344U, // VPRORVDZrmkz 811651312U, // VPRORVDZrr 87052528U, // VPRORVDZrrk 890278128U, // VPRORVDZrrkz 811851913U, // VPRORVQZ128rm 358719625U, // VPRORVQZ128rmb 1433952393U, // VPRORVQZ128rmbk 1165287561U, // VPRORVQZ128rmbkz 985112713U, // VPRORVQZ128rmk 890577033U, // VPRORVQZ128rmkz 811655305U, // VPRORVQZ128rr 87056521U, // VPRORVQZ128rrk 890282121U, // VPRORVQZ128rrkz 812867721U, // VPRORVQZ256rm 360816777U, // VPRORVQZ256rmb 1436049545U, // VPRORVQZ256rmbk 1167384713U, // VPRORVQZ256rmbkz 985129097U, // VPRORVQZ256rmk 890609801U, // VPRORVQZ256rmkz 811655305U, // VPRORVQZ256rr 87056521U, // VPRORVQZ256rrk 890282121U, // VPRORVQZ256rrkz 812884105U, // VPRORVQZrm 362913929U, // VPRORVQZrmb 1438146697U, // VPRORVQZrmbk 1169481865U, // VPRORVQZrmbkz 985145481U, // VPRORVQZrmk 890675337U, // VPRORVQZrmkz 811655305U, // VPRORVQZrr 87056521U, // VPRORVQZrrk 890282121U, // VPRORVQZrrkz 830768700U, // VPROTBmi 830801468U, // VPROTBmr 283428412U, // VPROTBri 811845180U, // VPROTBrm 811648572U, // VPROTBrr 811648572U, // VPROTBrr_REV 830771289U, // VPROTDmi 830804057U, // VPROTDmr 283431001U, // VPROTDri 811847769U, // VPROTDrm 811651161U, // VPROTDrr 811651161U, // VPROTDrr_REV 830775233U, // VPROTQmi 830808001U, // VPROTQmr 283434945U, // VPROTQri 811851713U, // VPROTQrm 811655105U, // VPROTQrr 811655105U, // VPROTQrr_REV 830779153U, // VPROTWmi 830811921U, // VPROTWmr 283438865U, // VPROTWri 811855633U, // VPROTWrm 811659025U, // VPROTWrr 811659025U, // VPROTWrr_REV 812870266U, // VPSADBWYrm 811657850U, // VPSADBWYrr 811854458U, // VPSADBWZ128rm 811657850U, // VPSADBWZ128rr 812870266U, // VPSADBWZ256rm 811657850U, // VPSADBWZ256rr 812886650U, // VPSADBWZrm 811657850U, // VPSADBWZrr 811854458U, // VPSADBWrm 811657850U, // VPSADBWrr 3247720445U, // VPSCATTERDDZ128mr 3425978365U, // VPSCATTERDDZ256mr 3428075517U, // VPSCATTERDDZmr 3247725345U, // VPSCATTERDQZ128mr 3425983265U, // VPSCATTERDQZ256mr 3428080417U, // VPSCATTERDQZmr 3251916153U, // VPSCATTERQDZ128mr 3247721849U, // VPSCATTERQDZ256mr 3425979769U, // VPSCATTERQDZmr 3247726073U, // VPSCATTERQQZ128mr 3425983993U, // VPSCATTERQQZ256mr 3428081145U, // VPSCATTERQQZmr 830800811U, // VPSHABmr 811844523U, // VPSHABrm 811647915U, // VPSHABrr 811647915U, // VPSHABrr_REV 830801753U, // VPSHADmr 811845465U, // VPSHADrm 811648857U, // VPSHADrr 811648857U, // VPSHADrr_REV 830806380U, // VPSHAQmr 811850092U, // VPSHAQrm 811653484U, // VPSHAQrr 811653484U, // VPSHAQrr_REV 830810685U, // VPSHAWmr 811854397U, // VPSHAWrm 811657789U, // VPSHAWrr 811657789U, // VPSHAWrr_REV 830800997U, // VPSHLBmr 811844709U, // VPSHLBrm 811648101U, // VPSHLBrr 811648101U, // VPSHLBrr_REV 1686489028U, // VPSHLDDZ128rmbi 1710475204U, // VPSHLDDZ128rmbik 1712588740U, // VPSHLDDZ128rmbikz 325437380U, // VPSHLDDZ128rmi 1983104964U, // VPSHLDDZ128rmik 1179912132U, // VPSHLDDZ128rmikz 1088817092U, // VPSHLDDZ128rri 2163132356U, // VPSHLDDZ128rrik 1357580228U, // VPSHLDDZ128rrikz 2491795396U, // VPSHLDDZ256rmbi 2515781572U, // VPSHLDDZ256rmbik 2517895108U, // VPSHLDDZ256rmbikz 375769028U, // VPSHLDDZ256rmi 1989396420U, // VPSHLDDZ256rmik 1186203588U, // VPSHLDDZ256rmikz 1088817092U, // VPSHLDDZ256rri 2163132356U, // VPSHLDDZ256rrik 1357580228U, // VPSHLDDZ256rrikz 2760230852U, // VPSHLDDZrmbi 2784217028U, // VPSHLDDZrmbik 2786330564U, // VPSHLDDZrmbikz 382060484U, // VPSHLDDZrmi 1995687876U, // VPSHLDDZrmik 1192495044U, // VPSHLDDZrmikz 1088817092U, // VPSHLDDZrri 2163132356U, // VPSHLDDZrrik 1357580228U, // VPSHLDDZrrikz 3013991055U, // VPSHLDQZ128rmbi 3073628815U, // VPSHLDQZ128rmbik 3075742351U, // VPSHLDQZ128rmbikz 325442191U, // VPSHLDQZ128rmi 1983109775U, // VPSHLDQZ128rmik 1179916943U, // VPSHLDQZ128rmikz 1088821903U, // VPSHLDQZ128rri 2163137167U, // VPSHLDQZ128rrik 1357585039U, // VPSHLDQZ128rrikz 1671813775U, // VPSHLDQZ256rmbi 1731451535U, // VPSHLDQZ256rmbik 1733565071U, // VPSHLDQZ256rmbikz 375773839U, // VPSHLDQZ256rmi 1989401231U, // VPSHLDQZ256rmik 1186208399U, // VPSHLDQZ256rmikz 1088821903U, // VPSHLDQZ256rri 2163137167U, // VPSHLDQZ256rrik 1357585039U, // VPSHLDQZ256rrikz 2477120143U, // VPSHLDQZrmbi 2536757903U, // VPSHLDQZrmbik 2538871439U, // VPSHLDQZrmbikz 382065295U, // VPSHLDQZrmi 1995692687U, // VPSHLDQZrmik 1192499855U, // VPSHLDQZrmikz 1088821903U, // VPSHLDQZrri 2163137167U, // VPSHLDQZrrik 1357585039U, // VPSHLDQZrrikz 890572974U, // VPSHLDVDZ128m 1167478958U, // VPSHLDVDZ128mb 1436061870U, // VPSHLDVDZ128mbk 1436061870U, // VPSHLDVDZ128mbkz 985108654U, // VPSHLDVDZ128mk 985108654U, // VPSHLDVDZ128mkz 890278062U, // VPSHLDVDZ128r 87052462U, // VPSHLDVDZ128rk 89149614U, // VPSHLDVDZ128rkz 890605742U, // VPSHLDVDZ256m 1169576110U, // VPSHLDVDZ256mb 1438159022U, // VPSHLDVDZ256mbk 1438159022U, // VPSHLDVDZ256mbkz 985125038U, // VPSHLDVDZ256mk 985125038U, // VPSHLDVDZ256mkz 890278062U, // VPSHLDVDZ256r 87052462U, // VPSHLDVDZ256rk 89149614U, // VPSHLDVDZ256rkz 890671278U, // VPSHLDVDZm 1171673262U, // VPSHLDVDZmb 1440256174U, // VPSHLDVDZmbk 1440256174U, // VPSHLDVDZmbkz 985141422U, // VPSHLDVDZmk 985141422U, // VPSHLDVDZmkz 890278062U, // VPSHLDVDZr 87052462U, // VPSHLDVDZrk 89149614U, // VPSHLDVDZrkz 890576960U, // VPSHLDVQZ128m 1165287488U, // VPSHLDVQZ128mb 1433952320U, // VPSHLDVQZ128mbk 1433952320U, // VPSHLDVQZ128mbkz 985112640U, // VPSHLDVQZ128mk 985112640U, // VPSHLDVQZ128mkz 890282048U, // VPSHLDVQZ128r 87056448U, // VPSHLDVQZ128rk 89153600U, // VPSHLDVQZ128rkz 890609728U, // VPSHLDVQZ256m 1167384640U, // VPSHLDVQZ256mb 1436049472U, // VPSHLDVQZ256mbk 1436049472U, // VPSHLDVQZ256mbkz 985129024U, // VPSHLDVQZ256mk 985129024U, // VPSHLDVQZ256mkz 890282048U, // VPSHLDVQZ256r 87056448U, // VPSHLDVQZ256rk 89153600U, // VPSHLDVQZ256rkz 890675264U, // VPSHLDVQZm 1169481792U, // VPSHLDVQZmb 1438146624U, // VPSHLDVQZmbk 1438146624U, // VPSHLDVQZmbkz 985145408U, // VPSHLDVQZmk 985145408U, // VPSHLDVQZmkz 890282048U, // VPSHLDVQZr 87056448U, // VPSHLDVQZrk 89153600U, // VPSHLDVQZrkz 890580861U, // VPSHLDVWZ128m 985116541U, // VPSHLDVWZ128mk 985116541U, // VPSHLDVWZ128mkz 890285949U, // VPSHLDVWZ128r 87060349U, // VPSHLDVWZ128rk 89157501U, // VPSHLDVWZ128rkz 890613629U, // VPSHLDVWZ256m 985132925U, // VPSHLDVWZ256mk 985132925U, // VPSHLDVWZ256mkz 890285949U, // VPSHLDVWZ256r 87060349U, // VPSHLDVWZ256rk 89157501U, // VPSHLDVWZ256rkz 890679165U, // VPSHLDVWZm 985149309U, // VPSHLDVWZmk 985149309U, // VPSHLDVWZmkz 890285949U, // VPSHLDVWZr 87060349U, // VPSHLDVWZrk 89157501U, // VPSHLDVWZrkz 325446472U, // VPSHLDWZ128rmi 1983114056U, // VPSHLDWZ128rmik 1179921224U, // VPSHLDWZ128rmikz 1088826184U, // VPSHLDWZ128rri 2163141448U, // VPSHLDWZ128rrik 1357589320U, // VPSHLDWZ128rrikz 375778120U, // VPSHLDWZ256rmi 1989405512U, // VPSHLDWZ256rmik 1186212680U, // VPSHLDWZ256rmikz 1088826184U, // VPSHLDWZ256rri 2163141448U, // VPSHLDWZ256rrik 1357589320U, // VPSHLDWZ256rrikz 382069576U, // VPSHLDWZrmi 1995696968U, // VPSHLDWZrmik 1192504136U, // VPSHLDWZrmikz 1088826184U, // VPSHLDWZrri 2163141448U, // VPSHLDWZrrik 1357589320U, // VPSHLDWZrrikz 830802025U, // VPSHLDmr 811845737U, // VPSHLDrm 811649129U, // VPSHLDrr 811649129U, // VPSHLDrr_REV 830807210U, // VPSHLQmr 811850922U, // VPSHLQrm 811654314U, // VPSHLQrr 811654314U, // VPSHLQrr_REV 830811231U, // VPSHLWmr 811854943U, // VPSHLWrm 811658335U, // VPSHLWrr 811658335U, // VPSHLWrr_REV 1686489098U, // VPSHRDDZ128rmbi 1710475274U, // VPSHRDDZ128rmbik 1712588810U, // VPSHRDDZ128rmbikz 325437450U, // VPSHRDDZ128rmi 1983105034U, // VPSHRDDZ128rmik 1179912202U, // VPSHRDDZ128rmikz 1088817162U, // VPSHRDDZ128rri 2163132426U, // VPSHRDDZ128rrik 1357580298U, // VPSHRDDZ128rrikz 2491795466U, // VPSHRDDZ256rmbi 2515781642U, // VPSHRDDZ256rmbik 2517895178U, // VPSHRDDZ256rmbikz 375769098U, // VPSHRDDZ256rmi 1989396490U, // VPSHRDDZ256rmik 1186203658U, // VPSHRDDZ256rmikz 1088817162U, // VPSHRDDZ256rri 2163132426U, // VPSHRDDZ256rrik 1357580298U, // VPSHRDDZ256rrikz 2760230922U, // VPSHRDDZrmbi 2784217098U, // VPSHRDDZrmbik 2786330634U, // VPSHRDDZrmbikz 382060554U, // VPSHRDDZrmi 1995687946U, // VPSHRDDZrmik 1192495114U, // VPSHRDDZrmikz 1088817162U, // VPSHRDDZrri 2163132426U, // VPSHRDDZrrik 1357580298U, // VPSHRDDZrrikz 3013991214U, // VPSHRDQZ128rmbi 3073628974U, // VPSHRDQZ128rmbik 3075742510U, // VPSHRDQZ128rmbikz 325442350U, // VPSHRDQZ128rmi 1983109934U, // VPSHRDQZ128rmik 1179917102U, // VPSHRDQZ128rmikz 1088822062U, // VPSHRDQZ128rri 2163137326U, // VPSHRDQZ128rrik 1357585198U, // VPSHRDQZ128rrikz 1671813934U, // VPSHRDQZ256rmbi 1731451694U, // VPSHRDQZ256rmbik 1733565230U, // VPSHRDQZ256rmbikz 375773998U, // VPSHRDQZ256rmi 1989401390U, // VPSHRDQZ256rmik 1186208558U, // VPSHRDQZ256rmikz 1088822062U, // VPSHRDQZ256rri 2163137326U, // VPSHRDQZ256rrik 1357585198U, // VPSHRDQZ256rrikz 2477120302U, // VPSHRDQZrmbi 2536758062U, // VPSHRDQZrmbik 2538871598U, // VPSHRDQZrmbikz 382065454U, // VPSHRDQZrmi 1995692846U, // VPSHRDQZrmik 1192500014U, // VPSHRDQZrmikz 1088822062U, // VPSHRDQZrri 2163137326U, // VPSHRDQZrrik 1357585198U, // VPSHRDQZrrikz 890572984U, // VPSHRDVDZ128m 1167478968U, // VPSHRDVDZ128mb 1436061880U, // VPSHRDVDZ128mbk 1436061880U, // VPSHRDVDZ128mbkz 985108664U, // VPSHRDVDZ128mk 985108664U, // VPSHRDVDZ128mkz 890278072U, // VPSHRDVDZ128r 87052472U, // VPSHRDVDZ128rk 89149624U, // VPSHRDVDZ128rkz 890605752U, // VPSHRDVDZ256m 1169576120U, // VPSHRDVDZ256mb 1438159032U, // VPSHRDVDZ256mbk 1438159032U, // VPSHRDVDZ256mbkz 985125048U, // VPSHRDVDZ256mk 985125048U, // VPSHRDVDZ256mkz 890278072U, // VPSHRDVDZ256r 87052472U, // VPSHRDVDZ256rk 89149624U, // VPSHRDVDZ256rkz 890671288U, // VPSHRDVDZm 1171673272U, // VPSHRDVDZmb 1440256184U, // VPSHRDVDZmbk 1440256184U, // VPSHRDVDZmbkz 985141432U, // VPSHRDVDZmk 985141432U, // VPSHRDVDZmkz 890278072U, // VPSHRDVDZr 87052472U, // VPSHRDVDZrk 89149624U, // VPSHRDVDZrkz 890576970U, // VPSHRDVQZ128m 1165287498U, // VPSHRDVQZ128mb 1433952330U, // VPSHRDVQZ128mbk 1433952330U, // VPSHRDVQZ128mbkz 985112650U, // VPSHRDVQZ128mk 985112650U, // VPSHRDVQZ128mkz 890282058U, // VPSHRDVQZ128r 87056458U, // VPSHRDVQZ128rk 89153610U, // VPSHRDVQZ128rkz 890609738U, // VPSHRDVQZ256m 1167384650U, // VPSHRDVQZ256mb 1436049482U, // VPSHRDVQZ256mbk 1436049482U, // VPSHRDVQZ256mbkz 985129034U, // VPSHRDVQZ256mk 985129034U, // VPSHRDVQZ256mkz 890282058U, // VPSHRDVQZ256r 87056458U, // VPSHRDVQZ256rk 89153610U, // VPSHRDVQZ256rkz 890675274U, // VPSHRDVQZm 1169481802U, // VPSHRDVQZmb 1438146634U, // VPSHRDVQZmbk 1438146634U, // VPSHRDVQZmbkz 985145418U, // VPSHRDVQZmk 985145418U, // VPSHRDVQZmkz 890282058U, // VPSHRDVQZr 87056458U, // VPSHRDVQZrk 89153610U, // VPSHRDVQZrkz 890580871U, // VPSHRDVWZ128m 985116551U, // VPSHRDVWZ128mk 985116551U, // VPSHRDVWZ128mkz 890285959U, // VPSHRDVWZ128r 87060359U, // VPSHRDVWZ128rk 89157511U, // VPSHRDVWZ128rkz 890613639U, // VPSHRDVWZ256m 985132935U, // VPSHRDVWZ256mk 985132935U, // VPSHRDVWZ256mkz 890285959U, // VPSHRDVWZ256r 87060359U, // VPSHRDVWZ256rk 89157511U, // VPSHRDVWZ256rkz 890679175U, // VPSHRDVWZm 985149319U, // VPSHRDVWZmk 985149319U, // VPSHRDVWZmkz 890285959U, // VPSHRDVWZr 87060359U, // VPSHRDVWZrk 89157511U, // VPSHRDVWZrkz 325446518U, // VPSHRDWZ128rmi 1983114102U, // VPSHRDWZ128rmik 1179921270U, // VPSHRDWZ128rmikz 1088826230U, // VPSHRDWZ128rri 2163141494U, // VPSHRDWZ128rrik 1357589366U, // VPSHRDWZ128rrikz 375778166U, // VPSHRDWZ256rmi 1989405558U, // VPSHRDWZ256rmik 1186212726U, // VPSHRDWZ256rmikz 1088826230U, // VPSHRDWZ256rri 2163141494U, // VPSHRDWZ256rrik 1357589366U, // VPSHRDWZ256rrikz 382069622U, // VPSHRDWZrmi 1995697014U, // VPSHRDWZrmik 1192504182U, // VPSHRDWZrmikz 1088826230U, // VPSHRDWZrri 2163141494U, // VPSHRDWZrrik 1357589366U, // VPSHRDWZrrikz 811844782U, // VPSHUFBITQMBZ128rm 890569902U, // VPSHUFBITQMBZ128rmk 811648174U, // VPSHUFBITQMBZ128rr 890274990U, // VPSHUFBITQMBZ128rrk 812860590U, // VPSHUFBITQMBZ256rm 890602670U, // VPSHUFBITQMBZ256rmk 811648174U, // VPSHUFBITQMBZ256rr 890274990U, // VPSHUFBITQMBZ256rrk 812876974U, // VPSHUFBITQMBZrm 890668206U, // VPSHUFBITQMBZrmk 811648174U, // VPSHUFBITQMBZrr 890274990U, // VPSHUFBITQMBZrrk 812860457U, // VPSHUFBYrm 811648041U, // VPSHUFBYrr 811844649U, // VPSHUFBZ128rm 985105449U, // VPSHUFBZ128rmk 890569769U, // VPSHUFBZ128rmkz 811648041U, // VPSHUFBZ128rr 87049257U, // VPSHUFBZ128rrk 890274857U, // VPSHUFBZ128rrkz 812860457U, // VPSHUFBZ256rm 985121833U, // VPSHUFBZ256rmk 890602537U, // VPSHUFBZ256rmkz 811648041U, // VPSHUFBZ256rr 87049257U, // VPSHUFBZ256rrk 890274857U, // VPSHUFBZ256rrkz 812876841U, // VPSHUFBZrm 985138217U, // VPSHUFBZrmk 890668073U, // VPSHUFBZrmkz 811648041U, // VPSHUFBZrr 87049257U, // VPSHUFBZrrk 890274857U, // VPSHUFBZrrkz 811844649U, // VPSHUFBrm 811648041U, // VPSHUFBrr 1009027119U, // VPSHUFDYmi 283428911U, // VPSHUFDYri 1638172719U, // VPSHUFDZ128mbi 1712588847U, // VPSHUFDZ128mbik 1686489135U, // VPSHUFDZ128mbikz 830769199U, // VPSHUFDZ128mi 643041327U, // VPSHUFDZ128mik 593872943U, // VPSHUFDZ128mikz 283428911U, // VPSHUFDZ128ri 1357580335U, // VPSHUFDZ128rik 1088817199U, // VPSHUFDZ128rikz 2443479087U, // VPSHUFDZ256mbi 2517895215U, // VPSHUFDZ256mbik 2491795503U, // VPSHUFDZ256mbikz 1009027119U, // VPSHUFDZ256mi 649332783U, // VPSHUFDZ256mik 644204591U, // VPSHUFDZ256mikz 283428911U, // VPSHUFDZ256ri 1357580335U, // VPSHUFDZ256rik 1088817199U, // VPSHUFDZ256rikz 2711914543U, // VPSHUFDZmbi 2786330671U, // VPSHUFDZmbik 2760230959U, // VPSHUFDZmbikz 1011124271U, // VPSHUFDZmi 655624239U, // VPSHUFDZmik 650496047U, // VPSHUFDZmikz 283428911U, // VPSHUFDZri 1357580335U, // VPSHUFDZrik 1088817199U, // VPSHUFDZrikz 830769199U, // VPSHUFDmi 283428911U, // VPSHUFDri 1009036328U, // VPSHUFHWYmi 283438120U, // VPSHUFHWYri 830778408U, // VPSHUFHWZ128mi 643050536U, // VPSHUFHWZ128mik 593882152U, // VPSHUFHWZ128mikz 283438120U, // VPSHUFHWZ128ri 1357589544U, // VPSHUFHWZ128rik 1088826408U, // VPSHUFHWZ128rikz 1009036328U, // VPSHUFHWZ256mi 649341992U, // VPSHUFHWZ256mik 644213800U, // VPSHUFHWZ256mikz 283438120U, // VPSHUFHWZ256ri 1357589544U, // VPSHUFHWZ256rik 1088826408U, // VPSHUFHWZ256rikz 1011133480U, // VPSHUFHWZmi 655633448U, // VPSHUFHWZmik 650505256U, // VPSHUFHWZmikz 283438120U, // VPSHUFHWZri 1357589544U, // VPSHUFHWZrik 1088826408U, // VPSHUFHWZrikz 830778408U, // VPSHUFHWmi 283438120U, // VPSHUFHWri 1009036373U, // VPSHUFLWYmi 283438165U, // VPSHUFLWYri 830778453U, // VPSHUFLWZ128mi 643050581U, // VPSHUFLWZ128mik 593882197U, // VPSHUFLWZ128mikz 283438165U, // VPSHUFLWZ128ri 1357589589U, // VPSHUFLWZ128rik 1088826453U, // VPSHUFLWZ128rikz 1009036373U, // VPSHUFLWZ256mi 649342037U, // VPSHUFLWZ256mik 644213845U, // VPSHUFLWZ256mikz 283438165U, // VPSHUFLWZ256ri 1357589589U, // VPSHUFLWZ256rik 1088826453U, // VPSHUFLWZ256rikz 1011133525U, // VPSHUFLWZmi 655633493U, // VPSHUFLWZmik 650505301U, // VPSHUFLWZmikz 283438165U, // VPSHUFLWZri 1357589589U, // VPSHUFLWZrik 1088826453U, // VPSHUFLWZrikz 830778453U, // VPSHUFLWmi 283438165U, // VPSHUFLWri 812860630U, // VPSIGNBYrm 811648214U, // VPSIGNBYrr 811844822U, // VPSIGNBrm 811648214U, // VPSIGNBrr 812861686U, // VPSIGNDYrm 811649270U, // VPSIGNDYrr 811845878U, // VPSIGNDrm 811649270U, // VPSIGNDrr 812870885U, // VPSIGNWYrm 811658469U, // VPSIGNWYrr 811855077U, // VPSIGNWrm 811658469U, // VPSIGNWrr 283433636U, // VPSLLDQYri 830773924U, // VPSLLDQZ128rm 283433636U, // VPSLLDQZ128rr 1009031844U, // VPSLLDQZ256rm 283433636U, // VPSLLDQZ256rr 1011128996U, // VPSLLDQZrm 283433636U, // VPSLLDQZrr 283433636U, // VPSLLDQri 283428977U, // VPSLLDYri 811845745U, // VPSLLDYrm 811649137U, // VPSLLDYrr 1638172785U, // VPSLLDZ128mbi 1712588913U, // VPSLLDZ128mbik 1686489201U, // VPSLLDZ128mbikz 830769265U, // VPSLLDZ128mi 643041393U, // VPSLLDZ128mik 593873009U, // VPSLLDZ128mikz 283428977U, // VPSLLDZ128ri 1357580401U, // VPSLLDZ128rik 1088817265U, // VPSLLDZ128rikz 811845745U, // VPSLLDZ128rm 985106545U, // VPSLLDZ128rmk 890570865U, // VPSLLDZ128rmkz 811649137U, // VPSLLDZ128rr 87050353U, // VPSLLDZ128rrk 890275953U, // VPSLLDZ128rrkz 2443479153U, // VPSLLDZ256mbi 2517895281U, // VPSLLDZ256mbik 2491795569U, // VPSLLDZ256mbikz 1009027185U, // VPSLLDZ256mi 649332849U, // VPSLLDZ256mik 644204657U, // VPSLLDZ256mikz 283428977U, // VPSLLDZ256ri 1357580401U, // VPSLLDZ256rik 1088817265U, // VPSLLDZ256rikz 811845745U, // VPSLLDZ256rm 985106545U, // VPSLLDZ256rmk 890570865U, // VPSLLDZ256rmkz 811649137U, // VPSLLDZ256rr 87050353U, // VPSLLDZ256rrk 890275953U, // VPSLLDZ256rrkz 2711914609U, // VPSLLDZmbi 2786330737U, // VPSLLDZmbik 2760231025U, // VPSLLDZmbikz 1011124337U, // VPSLLDZmi 655624305U, // VPSLLDZmik 650496113U, // VPSLLDZmikz 283428977U, // VPSLLDZri 1357580401U, // VPSLLDZrik 1088817265U, // VPSLLDZrikz 811845745U, // VPSLLDZrm 985106545U, // VPSLLDZrmk 890570865U, // VPSLLDZrmkz 811649137U, // VPSLLDZrr 87050353U, // VPSLLDZrrk 890275953U, // VPSLLDZrrkz 283428977U, // VPSLLDri 811845745U, // VPSLLDrm 811649137U, // VPSLLDrr 283434189U, // VPSLLQYri 811850957U, // VPSLLQYrm 811654349U, // VPSLLQYrr 2982452429U, // VPSLLQZ128mbi 3075742925U, // VPSLLQZ128mbik 3013991629U, // VPSLLQZ128mbikz 830774477U, // VPSLLQZ128mi 643046605U, // VPSLLQZ128mik 593878221U, // VPSLLQZ128mikz 283434189U, // VPSLLQZ128ri 1357585613U, // VPSLLQZ128rik 1088822477U, // VPSLLQZ128rikz 811850957U, // VPSLLQZ128rm 985111757U, // VPSLLQZ128rmk 890576077U, // VPSLLQZ128rmkz 811654349U, // VPSLLQZ128rr 87055565U, // VPSLLQZ128rrk 890281165U, // VPSLLQZ128rrkz 1640275149U, // VPSLLQZ256mbi 1733565645U, // VPSLLQZ256mbik 1671814349U, // VPSLLQZ256mbikz 1009032397U, // VPSLLQZ256mi 649338061U, // VPSLLQZ256mik 644209869U, // VPSLLQZ256mikz 283434189U, // VPSLLQZ256ri 1357585613U, // VPSLLQZ256rik 1088822477U, // VPSLLQZ256rikz 811850957U, // VPSLLQZ256rm 985111757U, // VPSLLQZ256rmk 890576077U, // VPSLLQZ256rmkz 811654349U, // VPSLLQZ256rr 87055565U, // VPSLLQZ256rrk 890281165U, // VPSLLQZ256rrkz 2445581517U, // VPSLLQZmbi 2538872013U, // VPSLLQZmbik 2477120717U, // VPSLLQZmbikz 1011129549U, // VPSLLQZmi 655629517U, // VPSLLQZmik 650501325U, // VPSLLQZmikz 283434189U, // VPSLLQZri 1357585613U, // VPSLLQZrik 1088822477U, // VPSLLQZrikz 811850957U, // VPSLLQZrm 985111757U, // VPSLLQZrmk 890576077U, // VPSLLQZrmkz 811654349U, // VPSLLQZrr 87055565U, // VPSLLQZrrk 890281165U, // VPSLLQZrrkz 283434189U, // VPSLLQri 811850957U, // VPSLLQrm 811654349U, // VPSLLQrr 812863682U, // VPSLLVDYrm 811651266U, // VPSLLVDYrr 811847874U, // VPSLLVDZ128rm 360796354U, // VPSLLVDZ128rmb 1436061890U, // VPSLLVDZ128rmbk 1167478978U, // VPSLLVDZ128rmbkz 985108674U, // VPSLLVDZ128rmk 890572994U, // VPSLLVDZ128rmkz 811651266U, // VPSLLVDZ128rr 87052482U, // VPSLLVDZ128rrk 890278082U, // VPSLLVDZ128rrkz 812863682U, // VPSLLVDZ256rm 362893506U, // VPSLLVDZ256rmb 1438159042U, // VPSLLVDZ256rmbk 1169576130U, // VPSLLVDZ256rmbkz 985125058U, // VPSLLVDZ256rmk 890605762U, // VPSLLVDZ256rmkz 811651266U, // VPSLLVDZ256rr 87052482U, // VPSLLVDZ256rrk 890278082U, // VPSLLVDZ256rrkz 812880066U, // VPSLLVDZrm 364990658U, // VPSLLVDZrmb 1440256194U, // VPSLLVDZrmbk 1171673282U, // VPSLLVDZrmbkz 985141442U, // VPSLLVDZrmk 890671298U, // VPSLLVDZrmkz 811651266U, // VPSLLVDZrr 87052482U, // VPSLLVDZrrk 890278082U, // VPSLLVDZrrkz 811847874U, // VPSLLVDrm 811651266U, // VPSLLVDrr 812867675U, // VPSLLVQYrm 811655259U, // VPSLLVQYrr 811851867U, // VPSLLVQZ128rm 358719579U, // VPSLLVQZ128rmb 1433952347U, // VPSLLVQZ128rmbk 1165287515U, // VPSLLVQZ128rmbkz 985112667U, // VPSLLVQZ128rmk 890576987U, // VPSLLVQZ128rmkz 811655259U, // VPSLLVQZ128rr 87056475U, // VPSLLVQZ128rrk 890282075U, // VPSLLVQZ128rrkz 812867675U, // VPSLLVQZ256rm 360816731U, // VPSLLVQZ256rmb 1436049499U, // VPSLLVQZ256rmbk 1167384667U, // VPSLLVQZ256rmbkz 985129051U, // VPSLLVQZ256rmk 890609755U, // VPSLLVQZ256rmkz 811655259U, // VPSLLVQZ256rr 87056475U, // VPSLLVQZ256rrk 890282075U, // VPSLLVQZ256rrkz 812884059U, // VPSLLVQZrm 362913883U, // VPSLLVQZrmb 1438146651U, // VPSLLVQZrmbk 1169481819U, // VPSLLVQZrmbkz 985145435U, // VPSLLVQZrmk 890675291U, // VPSLLVQZrmkz 811655259U, // VPSLLVQZrr 87056475U, // VPSLLVQZrrk 890282075U, // VPSLLVQZrrkz 811851867U, // VPSLLVQrm 811655259U, // VPSLLVQrr 811855768U, // VPSLLVWZ128rm 985116568U, // VPSLLVWZ128rmk 890580888U, // VPSLLVWZ128rmkz 811659160U, // VPSLLVWZ128rr 87060376U, // VPSLLVWZ128rrk 890285976U, // VPSLLVWZ128rrkz 812871576U, // VPSLLVWZ256rm 985132952U, // VPSLLVWZ256rmk 890613656U, // VPSLLVWZ256rmkz 811659160U, // VPSLLVWZ256rr 87060376U, // VPSLLVWZ256rrk 890285976U, // VPSLLVWZ256rrkz 812887960U, // VPSLLVWZrm 985149336U, // VPSLLVWZrmk 890679192U, // VPSLLVWZrmkz 811659160U, // VPSLLVWZrr 87060376U, // VPSLLVWZrrk 890285976U, // VPSLLVWZrrkz 283438191U, // VPSLLWYri 811854959U, // VPSLLWYrm 811658351U, // VPSLLWYrr 830778479U, // VPSLLWZ128mi 643050607U, // VPSLLWZ128mik 593882223U, // VPSLLWZ128mikz 283438191U, // VPSLLWZ128ri 1357589615U, // VPSLLWZ128rik 1088826479U, // VPSLLWZ128rikz 811854959U, // VPSLLWZ128rm 985115759U, // VPSLLWZ128rmk 890580079U, // VPSLLWZ128rmkz 811658351U, // VPSLLWZ128rr 87059567U, // VPSLLWZ128rrk 890285167U, // VPSLLWZ128rrkz 1009036399U, // VPSLLWZ256mi 649342063U, // VPSLLWZ256mik 644213871U, // VPSLLWZ256mikz 283438191U, // VPSLLWZ256ri 1357589615U, // VPSLLWZ256rik 1088826479U, // VPSLLWZ256rikz 811854959U, // VPSLLWZ256rm 985115759U, // VPSLLWZ256rmk 890580079U, // VPSLLWZ256rmkz 811658351U, // VPSLLWZ256rr 87059567U, // VPSLLWZ256rrk 890285167U, // VPSLLWZ256rrkz 1011133551U, // VPSLLWZmi 655633519U, // VPSLLWZmik 650505327U, // VPSLLWZmikz 283438191U, // VPSLLWZri 1357589615U, // VPSLLWZrik 1088826479U, // VPSLLWZrikz 811854959U, // VPSLLWZrm 985115759U, // VPSLLWZrmk 890580079U, // VPSLLWZrmkz 811658351U, // VPSLLWZrr 87059567U, // VPSLLWZrrk 890285167U, // VPSLLWZrrkz 283438191U, // VPSLLWri 811854959U, // VPSLLWrm 811658351U, // VPSLLWrr 283428705U, // VPSRADYri 811845473U, // VPSRADYrm 811648865U, // VPSRADYrr 1638172513U, // VPSRADZ128mbi 1712588641U, // VPSRADZ128mbik 1686488929U, // VPSRADZ128mbikz 830768993U, // VPSRADZ128mi 643041121U, // VPSRADZ128mik 593872737U, // VPSRADZ128mikz 283428705U, // VPSRADZ128ri 1357580129U, // VPSRADZ128rik 1088816993U, // VPSRADZ128rikz 811845473U, // VPSRADZ128rm 985106273U, // VPSRADZ128rmk 890570593U, // VPSRADZ128rmkz 811648865U, // VPSRADZ128rr 87050081U, // VPSRADZ128rrk 890275681U, // VPSRADZ128rrkz 2443478881U, // VPSRADZ256mbi 2517895009U, // VPSRADZ256mbik 2491795297U, // VPSRADZ256mbikz 1009026913U, // VPSRADZ256mi 649332577U, // VPSRADZ256mik 644204385U, // VPSRADZ256mikz 283428705U, // VPSRADZ256ri 1357580129U, // VPSRADZ256rik 1088816993U, // VPSRADZ256rikz 811845473U, // VPSRADZ256rm 985106273U, // VPSRADZ256rmk 890570593U, // VPSRADZ256rmkz 811648865U, // VPSRADZ256rr 87050081U, // VPSRADZ256rrk 890275681U, // VPSRADZ256rrkz 2711914337U, // VPSRADZmbi 2786330465U, // VPSRADZmbik 2760230753U, // VPSRADZmbikz 1011124065U, // VPSRADZmi 655624033U, // VPSRADZmik 650495841U, // VPSRADZmikz 283428705U, // VPSRADZri 1357580129U, // VPSRADZrik 1088816993U, // VPSRADZrikz 811845473U, // VPSRADZrm 985106273U, // VPSRADZrmk 890570593U, // VPSRADZrmkz 811648865U, // VPSRADZrr 87050081U, // VPSRADZrrk 890275681U, // VPSRADZrrkz 283428705U, // VPSRADri 811845473U, // VPSRADrm 811648865U, // VPSRADrr 2982451572U, // VPSRAQZ128mbi 3075742068U, // VPSRAQZ128mbik 3013990772U, // VPSRAQZ128mbikz 830773620U, // VPSRAQZ128mi 643045748U, // VPSRAQZ128mik 593877364U, // VPSRAQZ128mikz 283433332U, // VPSRAQZ128ri 1357584756U, // VPSRAQZ128rik 1088821620U, // VPSRAQZ128rikz 811850100U, // VPSRAQZ128rm 985110900U, // VPSRAQZ128rmk 890575220U, // VPSRAQZ128rmkz 811653492U, // VPSRAQZ128rr 87054708U, // VPSRAQZ128rrk 890280308U, // VPSRAQZ128rrkz 1640274292U, // VPSRAQZ256mbi 1733564788U, // VPSRAQZ256mbik 1671813492U, // VPSRAQZ256mbikz 1009031540U, // VPSRAQZ256mi 649337204U, // VPSRAQZ256mik 644209012U, // VPSRAQZ256mikz 283433332U, // VPSRAQZ256ri 1357584756U, // VPSRAQZ256rik 1088821620U, // VPSRAQZ256rikz 811850100U, // VPSRAQZ256rm 985110900U, // VPSRAQZ256rmk 890575220U, // VPSRAQZ256rmkz 811653492U, // VPSRAQZ256rr 87054708U, // VPSRAQZ256rrk 890280308U, // VPSRAQZ256rrkz 2445580660U, // VPSRAQZmbi 2538871156U, // VPSRAQZmbik 2477119860U, // VPSRAQZmbikz 1011128692U, // VPSRAQZmi 655628660U, // VPSRAQZmik 650500468U, // VPSRAQZmikz 283433332U, // VPSRAQZri 1357584756U, // VPSRAQZrik 1088821620U, // VPSRAQZrikz 811850100U, // VPSRAQZrm 985110900U, // VPSRAQZrmk 890575220U, // VPSRAQZrmkz 811653492U, // VPSRAQZrr 87054708U, // VPSRAQZrrk 890280308U, // VPSRAQZrrkz 812863653U, // VPSRAVDYrm 811651237U, // VPSRAVDYrr 811847845U, // VPSRAVDZ128rm 360796325U, // VPSRAVDZ128rmb 1436061861U, // VPSRAVDZ128rmbk 1167478949U, // VPSRAVDZ128rmbkz 985108645U, // VPSRAVDZ128rmk 890572965U, // VPSRAVDZ128rmkz 811651237U, // VPSRAVDZ128rr 87052453U, // VPSRAVDZ128rrk 890278053U, // VPSRAVDZ128rrkz 812863653U, // VPSRAVDZ256rm 362893477U, // VPSRAVDZ256rmb 1438159013U, // VPSRAVDZ256rmbk 1169576101U, // VPSRAVDZ256rmbkz 985125029U, // VPSRAVDZ256rmk 890605733U, // VPSRAVDZ256rmkz 811651237U, // VPSRAVDZ256rr 87052453U, // VPSRAVDZ256rrk 890278053U, // VPSRAVDZ256rrkz 812880037U, // VPSRAVDZrm 364990629U, // VPSRAVDZrmb 1440256165U, // VPSRAVDZrmbk 1171673253U, // VPSRAVDZrmbkz 985141413U, // VPSRAVDZrmk 890671269U, // VPSRAVDZrmkz 811651237U, // VPSRAVDZrr 87052453U, // VPSRAVDZrrk 890278053U, // VPSRAVDZrrkz 811847845U, // VPSRAVDrm 811651237U, // VPSRAVDrr 811851831U, // VPSRAVQZ128rm 358719543U, // VPSRAVQZ128rmb 1433952311U, // VPSRAVQZ128rmbk 1165287479U, // VPSRAVQZ128rmbkz 985112631U, // VPSRAVQZ128rmk 890576951U, // VPSRAVQZ128rmkz 811655223U, // VPSRAVQZ128rr 87056439U, // VPSRAVQZ128rrk 890282039U, // VPSRAVQZ128rrkz 812867639U, // VPSRAVQZ256rm 360816695U, // VPSRAVQZ256rmb 1436049463U, // VPSRAVQZ256rmbk 1167384631U, // VPSRAVQZ256rmbkz 985129015U, // VPSRAVQZ256rmk 890609719U, // VPSRAVQZ256rmkz 811655223U, // VPSRAVQZ256rr 87056439U, // VPSRAVQZ256rrk 890282039U, // VPSRAVQZ256rrkz 812884023U, // VPSRAVQZrm 362913847U, // VPSRAVQZrmb 1438146615U, // VPSRAVQZrmbk 1169481783U, // VPSRAVQZrmbkz 985145399U, // VPSRAVQZrmk 890675255U, // VPSRAVQZrmkz 811655223U, // VPSRAVQZrr 87056439U, // VPSRAVQZrrk 890282039U, // VPSRAVQZrrkz 811855732U, // VPSRAVWZ128rm 985116532U, // VPSRAVWZ128rmk 890580852U, // VPSRAVWZ128rmkz 811659124U, // VPSRAVWZ128rr 87060340U, // VPSRAVWZ128rrk 890285940U, // VPSRAVWZ128rrkz 812871540U, // VPSRAVWZ256rm 985132916U, // VPSRAVWZ256rmk 890613620U, // VPSRAVWZ256rmkz 811659124U, // VPSRAVWZ256rr 87060340U, // VPSRAVWZ256rrk 890285940U, // VPSRAVWZ256rrkz 812887924U, // VPSRAVWZrm 985149300U, // VPSRAVWZrmk 890679156U, // VPSRAVWZrmkz 811659124U, // VPSRAVWZrr 87060340U, // VPSRAVWZrrk 890285940U, // VPSRAVWZrrkz 283437637U, // VPSRAWYri 811854405U, // VPSRAWYrm 811657797U, // VPSRAWYrr 830777925U, // VPSRAWZ128mi 643050053U, // VPSRAWZ128mik 593881669U, // VPSRAWZ128mikz 283437637U, // VPSRAWZ128ri 1357589061U, // VPSRAWZ128rik 1088825925U, // VPSRAWZ128rikz 811854405U, // VPSRAWZ128rm 985115205U, // VPSRAWZ128rmk 890579525U, // VPSRAWZ128rmkz 811657797U, // VPSRAWZ128rr 87059013U, // VPSRAWZ128rrk 890284613U, // VPSRAWZ128rrkz 1009035845U, // VPSRAWZ256mi 649341509U, // VPSRAWZ256mik 644213317U, // VPSRAWZ256mikz 283437637U, // VPSRAWZ256ri 1357589061U, // VPSRAWZ256rik 1088825925U, // VPSRAWZ256rikz 811854405U, // VPSRAWZ256rm 985115205U, // VPSRAWZ256rmk 890579525U, // VPSRAWZ256rmkz 811657797U, // VPSRAWZ256rr 87059013U, // VPSRAWZ256rrk 890284613U, // VPSRAWZ256rrkz 1011132997U, // VPSRAWZmi 655632965U, // VPSRAWZmik 650504773U, // VPSRAWZmikz 283437637U, // VPSRAWZri 1357589061U, // VPSRAWZrik 1088825925U, // VPSRAWZrikz 811854405U, // VPSRAWZrm 985115205U, // VPSRAWZrmk 890579525U, // VPSRAWZrmkz 811657797U, // VPSRAWZrr 87059013U, // VPSRAWZrrk 890284613U, // VPSRAWZrrkz 283437637U, // VPSRAWri 811854405U, // VPSRAWrm 811657797U, // VPSRAWrr 283433645U, // VPSRLDQYri 830773933U, // VPSRLDQZ128rm 283433645U, // VPSRLDQZ128rr 1009031853U, // VPSRLDQZ256rm 283433645U, // VPSRLDQZ256rr 1011129005U, // VPSRLDQZrm 283433645U, // VPSRLDQZrr 283433645U, // VPSRLDQri 283429002U, // VPSRLDYri 811845770U, // VPSRLDYrm 811649162U, // VPSRLDYrr 1638172810U, // VPSRLDZ128mbi 1712588938U, // VPSRLDZ128mbik 1686489226U, // VPSRLDZ128mbikz 830769290U, // VPSRLDZ128mi 643041418U, // VPSRLDZ128mik 593873034U, // VPSRLDZ128mikz 283429002U, // VPSRLDZ128ri 1357580426U, // VPSRLDZ128rik 1088817290U, // VPSRLDZ128rikz 811845770U, // VPSRLDZ128rm 985106570U, // VPSRLDZ128rmk 890570890U, // VPSRLDZ128rmkz 811649162U, // VPSRLDZ128rr 87050378U, // VPSRLDZ128rrk 890275978U, // VPSRLDZ128rrkz 2443479178U, // VPSRLDZ256mbi 2517895306U, // VPSRLDZ256mbik 2491795594U, // VPSRLDZ256mbikz 1009027210U, // VPSRLDZ256mi 649332874U, // VPSRLDZ256mik 644204682U, // VPSRLDZ256mikz 283429002U, // VPSRLDZ256ri 1357580426U, // VPSRLDZ256rik 1088817290U, // VPSRLDZ256rikz 811845770U, // VPSRLDZ256rm 985106570U, // VPSRLDZ256rmk 890570890U, // VPSRLDZ256rmkz 811649162U, // VPSRLDZ256rr 87050378U, // VPSRLDZ256rrk 890275978U, // VPSRLDZ256rrkz 2711914634U, // VPSRLDZmbi 2786330762U, // VPSRLDZmbik 2760231050U, // VPSRLDZmbikz 1011124362U, // VPSRLDZmi 655624330U, // VPSRLDZmik 650496138U, // VPSRLDZmikz 283429002U, // VPSRLDZri 1357580426U, // VPSRLDZrik 1088817290U, // VPSRLDZrikz 811845770U, // VPSRLDZrm 985106570U, // VPSRLDZrmk 890570890U, // VPSRLDZrmkz 811649162U, // VPSRLDZrr 87050378U, // VPSRLDZrrk 890275978U, // VPSRLDZrrkz 283429002U, // VPSRLDri 811845770U, // VPSRLDrm 811649162U, // VPSRLDrr 283434214U, // VPSRLQYri 811850982U, // VPSRLQYrm 811654374U, // VPSRLQYrr 2982452454U, // VPSRLQZ128mbi 3075742950U, // VPSRLQZ128mbik 3013991654U, // VPSRLQZ128mbikz 830774502U, // VPSRLQZ128mi 643046630U, // VPSRLQZ128mik 593878246U, // VPSRLQZ128mikz 283434214U, // VPSRLQZ128ri 1357585638U, // VPSRLQZ128rik 1088822502U, // VPSRLQZ128rikz 811850982U, // VPSRLQZ128rm 985111782U, // VPSRLQZ128rmk 890576102U, // VPSRLQZ128rmkz 811654374U, // VPSRLQZ128rr 87055590U, // VPSRLQZ128rrk 890281190U, // VPSRLQZ128rrkz 1640275174U, // VPSRLQZ256mbi 1733565670U, // VPSRLQZ256mbik 1671814374U, // VPSRLQZ256mbikz 1009032422U, // VPSRLQZ256mi 649338086U, // VPSRLQZ256mik 644209894U, // VPSRLQZ256mikz 283434214U, // VPSRLQZ256ri 1357585638U, // VPSRLQZ256rik 1088822502U, // VPSRLQZ256rikz 811850982U, // VPSRLQZ256rm 985111782U, // VPSRLQZ256rmk 890576102U, // VPSRLQZ256rmkz 811654374U, // VPSRLQZ256rr 87055590U, // VPSRLQZ256rrk 890281190U, // VPSRLQZ256rrkz 2445581542U, // VPSRLQZmbi 2538872038U, // VPSRLQZmbik 2477120742U, // VPSRLQZmbikz 1011129574U, // VPSRLQZmi 655629542U, // VPSRLQZmik 650501350U, // VPSRLQZmikz 283434214U, // VPSRLQZri 1357585638U, // VPSRLQZrik 1088822502U, // VPSRLQZrikz 811850982U, // VPSRLQZrm 985111782U, // VPSRLQZrmk 890576102U, // VPSRLQZrmkz 811654374U, // VPSRLQZrr 87055590U, // VPSRLQZrrk 890281190U, // VPSRLQZrrkz 283434214U, // VPSRLQri 811850982U, // VPSRLQrm 811654374U, // VPSRLQrr 812863700U, // VPSRLVDYrm 811651284U, // VPSRLVDYrr 811847892U, // VPSRLVDZ128rm 360796372U, // VPSRLVDZ128rmb 1436061908U, // VPSRLVDZ128rmbk 1167478996U, // VPSRLVDZ128rmbkz 985108692U, // VPSRLVDZ128rmk 890573012U, // VPSRLVDZ128rmkz 811651284U, // VPSRLVDZ128rr 87052500U, // VPSRLVDZ128rrk 890278100U, // VPSRLVDZ128rrkz 812863700U, // VPSRLVDZ256rm 362893524U, // VPSRLVDZ256rmb 1438159060U, // VPSRLVDZ256rmbk 1169576148U, // VPSRLVDZ256rmbkz 985125076U, // VPSRLVDZ256rmk 890605780U, // VPSRLVDZ256rmkz 811651284U, // VPSRLVDZ256rr 87052500U, // VPSRLVDZ256rrk 890278100U, // VPSRLVDZ256rrkz 812880084U, // VPSRLVDZrm 364990676U, // VPSRLVDZrmb 1440256212U, // VPSRLVDZrmbk 1171673300U, // VPSRLVDZrmbkz 985141460U, // VPSRLVDZrmk 890671316U, // VPSRLVDZrmkz 811651284U, // VPSRLVDZrr 87052500U, // VPSRLVDZrrk 890278100U, // VPSRLVDZrrkz 811847892U, // VPSRLVDrm 811651284U, // VPSRLVDrr 812867693U, // VPSRLVQYrm 811655277U, // VPSRLVQYrr 811851885U, // VPSRLVQZ128rm 358719597U, // VPSRLVQZ128rmb 1433952365U, // VPSRLVQZ128rmbk 1165287533U, // VPSRLVQZ128rmbkz 985112685U, // VPSRLVQZ128rmk 890577005U, // VPSRLVQZ128rmkz 811655277U, // VPSRLVQZ128rr 87056493U, // VPSRLVQZ128rrk 890282093U, // VPSRLVQZ128rrkz 812867693U, // VPSRLVQZ256rm 360816749U, // VPSRLVQZ256rmb 1436049517U, // VPSRLVQZ256rmbk 1167384685U, // VPSRLVQZ256rmbkz 985129069U, // VPSRLVQZ256rmk 890609773U, // VPSRLVQZ256rmkz 811655277U, // VPSRLVQZ256rr 87056493U, // VPSRLVQZ256rrk 890282093U, // VPSRLVQZ256rrkz 812884077U, // VPSRLVQZrm 362913901U, // VPSRLVQZrmb 1438146669U, // VPSRLVQZrmbk 1169481837U, // VPSRLVQZrmbkz 985145453U, // VPSRLVQZrmk 890675309U, // VPSRLVQZrmkz 811655277U, // VPSRLVQZrr 87056493U, // VPSRLVQZrrk 890282093U, // VPSRLVQZrrkz 811851885U, // VPSRLVQrm 811655277U, // VPSRLVQrr 811855777U, // VPSRLVWZ128rm 985116577U, // VPSRLVWZ128rmk 890580897U, // VPSRLVWZ128rmkz 811659169U, // VPSRLVWZ128rr 87060385U, // VPSRLVWZ128rrk 890285985U, // VPSRLVWZ128rrkz 812871585U, // VPSRLVWZ256rm 985132961U, // VPSRLVWZ256rmk 890613665U, // VPSRLVWZ256rmkz 811659169U, // VPSRLVWZ256rr 87060385U, // VPSRLVWZ256rrk 890285985U, // VPSRLVWZ256rrkz 812887969U, // VPSRLVWZrm 985149345U, // VPSRLVWZrmk 890679201U, // VPSRLVWZrmkz 811659169U, // VPSRLVWZrr 87060385U, // VPSRLVWZrrk 890285985U, // VPSRLVWZrrkz 283438214U, // VPSRLWYri 811854982U, // VPSRLWYrm 811658374U, // VPSRLWYrr 830778502U, // VPSRLWZ128mi 643050630U, // VPSRLWZ128mik 593882246U, // VPSRLWZ128mikz 283438214U, // VPSRLWZ128ri 1357589638U, // VPSRLWZ128rik 1088826502U, // VPSRLWZ128rikz 811854982U, // VPSRLWZ128rm 985115782U, // VPSRLWZ128rmk 890580102U, // VPSRLWZ128rmkz 811658374U, // VPSRLWZ128rr 87059590U, // VPSRLWZ128rrk 890285190U, // VPSRLWZ128rrkz 1009036422U, // VPSRLWZ256mi 649342086U, // VPSRLWZ256mik 644213894U, // VPSRLWZ256mikz 283438214U, // VPSRLWZ256ri 1357589638U, // VPSRLWZ256rik 1088826502U, // VPSRLWZ256rikz 811854982U, // VPSRLWZ256rm 985115782U, // VPSRLWZ256rmk 890580102U, // VPSRLWZ256rmkz 811658374U, // VPSRLWZ256rr 87059590U, // VPSRLWZ256rrk 890285190U, // VPSRLWZ256rrkz 1011133574U, // VPSRLWZmi 655633542U, // VPSRLWZmik 650505350U, // VPSRLWZmikz 283438214U, // VPSRLWZri 1357589638U, // VPSRLWZrik 1088826502U, // VPSRLWZrikz 811854982U, // VPSRLWZrm 985115782U, // VPSRLWZrmk 890580102U, // VPSRLWZrmkz 811658374U, // VPSRLWZrr 87059590U, // VPSRLWZrrk 890285190U, // VPSRLWZrrkz 283438214U, // VPSRLWri 811854982U, // VPSRLWrm 811658374U, // VPSRLWrr 812860345U, // VPSUBBYrm 811647929U, // VPSUBBYrr 811844537U, // VPSUBBZ128rm 985105337U, // VPSUBBZ128rmk 890569657U, // VPSUBBZ128rmkz 811647929U, // VPSUBBZ128rr 87049145U, // VPSUBBZ128rrk 890274745U, // VPSUBBZ128rrkz 812860345U, // VPSUBBZ256rm 985121721U, // VPSUBBZ256rmk 890602425U, // VPSUBBZ256rmkz 811647929U, // VPSUBBZ256rr 87049145U, // VPSUBBZ256rrk 890274745U, // VPSUBBZ256rrkz 812876729U, // VPSUBBZrm 985138105U, // VPSUBBZrmk 890667961U, // VPSUBBZrmkz 811647929U, // VPSUBBZrr 87049145U, // VPSUBBZrrk 890274745U, // VPSUBBZrrkz 811844537U, // VPSUBBrm 811647929U, // VPSUBBrr 812861319U, // VPSUBDYrm 811648903U, // VPSUBDYrr 811845511U, // VPSUBDZ128rm 360793991U, // VPSUBDZ128rmb 1436059527U, // VPSUBDZ128rmbk 1167476615U, // VPSUBDZ128rmbkz 985106311U, // VPSUBDZ128rmk 890570631U, // VPSUBDZ128rmkz 811648903U, // VPSUBDZ128rr 87050119U, // VPSUBDZ128rrk 890275719U, // VPSUBDZ128rrkz 812861319U, // VPSUBDZ256rm 362891143U, // VPSUBDZ256rmb 1438156679U, // VPSUBDZ256rmbk 1169573767U, // VPSUBDZ256rmbkz 985122695U, // VPSUBDZ256rmk 890603399U, // VPSUBDZ256rmkz 811648903U, // VPSUBDZ256rr 87050119U, // VPSUBDZ256rrk 890275719U, // VPSUBDZ256rrkz 812877703U, // VPSUBDZrm 364988295U, // VPSUBDZrmb 1440253831U, // VPSUBDZrmbk 1171670919U, // VPSUBDZrmbkz 985139079U, // VPSUBDZrmk 890668935U, // VPSUBDZrmkz 811648903U, // VPSUBDZrr 87050119U, // VPSUBDZrrk 890275719U, // VPSUBDZrrkz 811845511U, // VPSUBDrm 811648903U, // VPSUBDrr 812865959U, // VPSUBQYrm 811653543U, // VPSUBQYrr 811850151U, // VPSUBQZ128rm 358717863U, // VPSUBQZ128rmb 1433950631U, // VPSUBQZ128rmbk 1165285799U, // VPSUBQZ128rmbkz 985110951U, // VPSUBQZ128rmk 890575271U, // VPSUBQZ128rmkz 811653543U, // VPSUBQZ128rr 87054759U, // VPSUBQZ128rrk 890280359U, // VPSUBQZ128rrkz 812865959U, // VPSUBQZ256rm 360815015U, // VPSUBQZ256rmb 1436047783U, // VPSUBQZ256rmbk 1167382951U, // VPSUBQZ256rmbkz 985127335U, // VPSUBQZ256rmk 890608039U, // VPSUBQZ256rmkz 811653543U, // VPSUBQZ256rr 87054759U, // VPSUBQZ256rrk 890280359U, // VPSUBQZ256rrkz 812882343U, // VPSUBQZrm 362912167U, // VPSUBQZrmb 1438144935U, // VPSUBQZrmbk 1169480103U, // VPSUBQZrmbkz 985143719U, // VPSUBQZrmk 890673575U, // VPSUBQZrmkz 811653543U, // VPSUBQZrr 87054759U, // VPSUBQZrrk 890280359U, // VPSUBQZrrkz 811850151U, // VPSUBQrm 811653543U, // VPSUBQrr 812860849U, // VPSUBSBYrm 811648433U, // VPSUBSBYrr 811845041U, // VPSUBSBZ128rm 985105841U, // VPSUBSBZ128rmk 890570161U, // VPSUBSBZ128rmkz 811648433U, // VPSUBSBZ128rr 87049649U, // VPSUBSBZ128rrk 890275249U, // VPSUBSBZ128rrkz 812860849U, // VPSUBSBZ256rm 985122225U, // VPSUBSBZ256rmk 890602929U, // VPSUBSBZ256rmkz 811648433U, // VPSUBSBZ256rr 87049649U, // VPSUBSBZ256rrk 890275249U, // VPSUBSBZ256rrkz 812877233U, // VPSUBSBZrm 985138609U, // VPSUBSBZrmk 890668465U, // VPSUBSBZrmkz 811648433U, // VPSUBSBZrr 87049649U, // VPSUBSBZrrk 890275249U, // VPSUBSBZrrkz 811845041U, // VPSUBSBrm 811648433U, // VPSUBSBrr 812871172U, // VPSUBSWYrm 811658756U, // VPSUBSWYrr 811855364U, // VPSUBSWZ128rm 985116164U, // VPSUBSWZ128rmk 890580484U, // VPSUBSWZ128rmkz 811658756U, // VPSUBSWZ128rr 87059972U, // VPSUBSWZ128rrk 890285572U, // VPSUBSWZ128rrkz 812871172U, // VPSUBSWZ256rm 985132548U, // VPSUBSWZ256rmk 890613252U, // VPSUBSWZ256rmkz 811658756U, // VPSUBSWZ256rr 87059972U, // VPSUBSWZ256rrk 890285572U, // VPSUBSWZ256rrkz 812887556U, // VPSUBSWZrm 985148932U, // VPSUBSWZrmk 890678788U, // VPSUBSWZrmkz 811658756U, // VPSUBSWZrr 87059972U, // VPSUBSWZrrk 890285572U, // VPSUBSWZrrkz 811855364U, // VPSUBSWrm 811658756U, // VPSUBSWrr 812860910U, // VPSUBUSBYrm 811648494U, // VPSUBUSBYrr 811845102U, // VPSUBUSBZ128rm 985105902U, // VPSUBUSBZ128rmk 890570222U, // VPSUBUSBZ128rmkz 811648494U, // VPSUBUSBZ128rr 87049710U, // VPSUBUSBZ128rrk 890275310U, // VPSUBUSBZ128rrkz 812860910U, // VPSUBUSBZ256rm 985122286U, // VPSUBUSBZ256rmk 890602990U, // VPSUBUSBZ256rmkz 811648494U, // VPSUBUSBZ256rr 87049710U, // VPSUBUSBZ256rrk 890275310U, // VPSUBUSBZ256rrkz 812877294U, // VPSUBUSBZrm 985138670U, // VPSUBUSBZrmk 890668526U, // VPSUBUSBZrmkz 811648494U, // VPSUBUSBZrr 87049710U, // VPSUBUSBZrrk 890275310U, // VPSUBUSBZrrkz 811845102U, // VPSUBUSBrm 811648494U, // VPSUBUSBrr 812871307U, // VPSUBUSWYrm 811658891U, // VPSUBUSWYrr 811855499U, // VPSUBUSWZ128rm 985116299U, // VPSUBUSWZ128rmk 890580619U, // VPSUBUSWZ128rmkz 811658891U, // VPSUBUSWZ128rr 87060107U, // VPSUBUSWZ128rrk 890285707U, // VPSUBUSWZ128rrkz 812871307U, // VPSUBUSWZ256rm 985132683U, // VPSUBUSWZ256rmk 890613387U, // VPSUBUSWZ256rmkz 811658891U, // VPSUBUSWZ256rr 87060107U, // VPSUBUSWZ256rrk 890285707U, // VPSUBUSWZ256rrkz 812887691U, // VPSUBUSWZrm 985149067U, // VPSUBUSWZrmk 890678923U, // VPSUBUSWZrmkz 811658891U, // VPSUBUSWZrr 87060107U, // VPSUBUSWZrrk 890285707U, // VPSUBUSWZrrkz 811855499U, // VPSUBUSWrm 811658891U, // VPSUBUSWrr 812870347U, // VPSUBWYrm 811657931U, // VPSUBWYrr 811854539U, // VPSUBWZ128rm 985115339U, // VPSUBWZ128rmk 890579659U, // VPSUBWZ128rmkz 811657931U, // VPSUBWZ128rr 87059147U, // VPSUBWZ128rrk 890284747U, // VPSUBWZ128rrkz 812870347U, // VPSUBWZ256rm 985131723U, // VPSUBWZ256rmk 890612427U, // VPSUBWZ256rmkz 811657931U, // VPSUBWZ256rr 87059147U, // VPSUBWZ256rrk 890284747U, // VPSUBWZ256rrkz 812886731U, // VPSUBWZrm 985148107U, // VPSUBWZrmk 890677963U, // VPSUBWZrmkz 811657931U, // VPSUBWZrr 87059147U, // VPSUBWZrrk 890284747U, // VPSUBWZrrkz 811854539U, // VPSUBWrm 811657931U, // VPSUBWrr 1712588856U, // VPTERNLOGDZ128rmbi 1710475320U, // VPTERNLOGDZ128rmbik 1710475320U, // VPTERNLOGDZ128rmbikz 1179912248U, // VPTERNLOGDZ128rmi 1983105080U, // VPTERNLOGDZ128rmik 2519975992U, // VPTERNLOGDZ128rmikz 1357580344U, // VPTERNLOGDZ128rri 2163132472U, // VPTERNLOGDZ128rrik 2163132472U, // VPTERNLOGDZ128rrikz 2517895224U, // VPTERNLOGDZ256rmbi 2515781688U, // VPTERNLOGDZ256rmbik 2515781688U, // VPTERNLOGDZ256rmbikz 1186203704U, // VPTERNLOGDZ256rmi 1989396536U, // VPTERNLOGDZ256rmik 2526267448U, // VPTERNLOGDZ256rmikz 1357580344U, // VPTERNLOGDZ256rri 2163132472U, // VPTERNLOGDZ256rrik 2163132472U, // VPTERNLOGDZ256rrikz 2786330680U, // VPTERNLOGDZrmbi 2784217144U, // VPTERNLOGDZrmbik 2784217144U, // VPTERNLOGDZrmbikz 1192495160U, // VPTERNLOGDZrmi 1995687992U, // VPTERNLOGDZrmik 2532558904U, // VPTERNLOGDZrmikz 1357580344U, // VPTERNLOGDZrri 2163132472U, // VPTERNLOGDZrrik 2163132472U, // VPTERNLOGDZrrikz 3075742795U, // VPTERNLOGQZ128rmbi 3073629259U, // VPTERNLOGQZ128rmbik 3073629259U, // VPTERNLOGQZ128rmbikz 1179917387U, // VPTERNLOGQZ128rmi 1983110219U, // VPTERNLOGQZ128rmik 2519981131U, // VPTERNLOGQZ128rmikz 1357585483U, // VPTERNLOGQZ128rri 2163137611U, // VPTERNLOGQZ128rrik 2163137611U, // VPTERNLOGQZ128rrikz 1733565515U, // VPTERNLOGQZ256rmbi 1731451979U, // VPTERNLOGQZ256rmbik 1731451979U, // VPTERNLOGQZ256rmbikz 1186208843U, // VPTERNLOGQZ256rmi 1989401675U, // VPTERNLOGQZ256rmik 2526272587U, // VPTERNLOGQZ256rmikz 1357585483U, // VPTERNLOGQZ256rri 2163137611U, // VPTERNLOGQZ256rrik 2163137611U, // VPTERNLOGQZ256rrikz 2538871883U, // VPTERNLOGQZrmbi 2536758347U, // VPTERNLOGQZrmbik 2536758347U, // VPTERNLOGQZrmbikz 1192500299U, // VPTERNLOGQZrmi 1995693131U, // VPTERNLOGQZrmik 2532564043U, // VPTERNLOGQZrmikz 1357585483U, // VPTERNLOGQZrri 2163137611U, // VPTERNLOGQZrrik 2163137611U, // VPTERNLOGQZrrikz 811844804U, // VPTESTMBZ128rm 890569924U, // VPTESTMBZ128rmk 811648196U, // VPTESTMBZ128rr 890275012U, // VPTESTMBZ128rrk 812860612U, // VPTESTMBZ256rm 890602692U, // VPTESTMBZ256rmk 811648196U, // VPTESTMBZ256rr 890275012U, // VPTESTMBZ256rrk 812876996U, // VPTESTMBZrm 890668228U, // VPTESTMBZrmk 811648196U, // VPTESTMBZrr 890275012U, // VPTESTMBZrrk 811845835U, // VPTESTMDZ128rm 360794315U, // VPTESTMDZ128rmb 1167476939U, // VPTESTMDZ128rmbk 890570955U, // VPTESTMDZ128rmk 811649227U, // VPTESTMDZ128rr 890276043U, // VPTESTMDZ128rrk 812861643U, // VPTESTMDZ256rm 362891467U, // VPTESTMDZ256rmb 1169574091U, // VPTESTMDZ256rmbk 890603723U, // VPTESTMDZ256rmk 811649227U, // VPTESTMDZ256rr 890276043U, // VPTESTMDZ256rrk 812878027U, // VPTESTMDZrm 364988619U, // VPTESTMDZrmb 1171671243U, // VPTESTMDZrmbk 890669259U, // VPTESTMDZrmk 811649227U, // VPTESTMDZrr 890276043U, // VPTESTMDZrrk 811851067U, // VPTESTMQZ128rm 358718779U, // VPTESTMQZ128rmb 1165286715U, // VPTESTMQZ128rmbk 890576187U, // VPTESTMQZ128rmk 811654459U, // VPTESTMQZ128rr 890281275U, // VPTESTMQZ128rrk 812866875U, // VPTESTMQZ256rm 360815931U, // VPTESTMQZ256rmb 1167383867U, // VPTESTMQZ256rmbk 890608955U, // VPTESTMQZ256rmk 811654459U, // VPTESTMQZ256rr 890281275U, // VPTESTMQZ256rrk 812883259U, // VPTESTMQZrm 362913083U, // VPTESTMQZrmb 1169481019U, // VPTESTMQZrmbk 890674491U, // VPTESTMQZrmk 811654459U, // VPTESTMQZrr 890281275U, // VPTESTMQZrrk 811855059U, // VPTESTMWZ128rm 890580179U, // VPTESTMWZ128rmk 811658451U, // VPTESTMWZ128rr 890285267U, // VPTESTMWZ128rrk 812870867U, // VPTESTMWZ256rm 890612947U, // VPTESTMWZ256rmk 811658451U, // VPTESTMWZ256rr 890285267U, // VPTESTMWZ256rrk 812887251U, // VPTESTMWZrm 890678483U, // VPTESTMWZrmk 811658451U, // VPTESTMWZrr 890285267U, // VPTESTMWZrrk 811844763U, // VPTESTNMBZ128rm 890569883U, // VPTESTNMBZ128rmk 811648155U, // VPTESTNMBZ128rr 890274971U, // VPTESTNMBZ128rrk 812860571U, // VPTESTNMBZ256rm 890602651U, // VPTESTNMBZ256rmk 811648155U, // VPTESTNMBZ256rr 890274971U, // VPTESTNMBZ256rrk 812876955U, // VPTESTNMBZrm 890668187U, // VPTESTNMBZrmk 811648155U, // VPTESTNMBZrr 890274971U, // VPTESTNMBZrrk 811845808U, // VPTESTNMDZ128rm 360794288U, // VPTESTNMDZ128rmb 1167476912U, // VPTESTNMDZ128rmbk 890570928U, // VPTESTNMDZ128rmk 811649200U, // VPTESTNMDZ128rr 890276016U, // VPTESTNMDZ128rrk 812861616U, // VPTESTNMDZ256rm 362891440U, // VPTESTNMDZ256rmb 1169574064U, // VPTESTNMDZ256rmbk 890603696U, // VPTESTNMDZ256rmk 811649200U, // VPTESTNMDZ256rr 890276016U, // VPTESTNMDZ256rrk 812878000U, // VPTESTNMDZrm 364988592U, // VPTESTNMDZrmb 1171671216U, // VPTESTNMDZrmbk 890669232U, // VPTESTNMDZrmk 811649200U, // VPTESTNMDZrr 890276016U, // VPTESTNMDZrrk 811851040U, // VPTESTNMQZ128rm 358718752U, // VPTESTNMQZ128rmb 1165286688U, // VPTESTNMQZ128rmbk 890576160U, // VPTESTNMQZ128rmk 811654432U, // VPTESTNMQZ128rr 890281248U, // VPTESTNMQZ128rrk 812866848U, // VPTESTNMQZ256rm 360815904U, // VPTESTNMQZ256rmb 1167383840U, // VPTESTNMQZ256rmbk 890608928U, // VPTESTNMQZ256rmk 811654432U, // VPTESTNMQZ256rr 890281248U, // VPTESTNMQZ256rrk 812883232U, // VPTESTNMQZrm 362913056U, // VPTESTNMQZrmb 1169480992U, // VPTESTNMQZrmbk 890674464U, // VPTESTNMQZrmk 811654432U, // VPTESTNMQZrr 890281248U, // VPTESTNMQZrrk 811855032U, // VPTESTNMWZ128rm 890580152U, // VPTESTNMWZ128rmk 811658424U, // VPTESTNMWZ128rr 890285240U, // VPTESTNMWZ128rrk 812870840U, // VPTESTNMWZ256rm 890612920U, // VPTESTNMWZ256rmk 811658424U, // VPTESTNMWZ256rr 890285240U, // VPTESTNMWZ256rrk 812887224U, // VPTESTNMWZrm 890678456U, // VPTESTNMWZrmk 811658424U, // VPTESTNMWZrr 890285240U, // VPTESTNMWZrrk 552954252U, // VPTESTYrm 551840140U, // VPTESTYrr 665996U, // VPTESTrm 551840140U, // VPTESTrr 812870285U, // VPUNPCKHBWYrm 811657869U, // VPUNPCKHBWYrr 811854477U, // VPUNPCKHBWZ128rm 985115277U, // VPUNPCKHBWZ128rmk 890579597U, // VPUNPCKHBWZ128rmkz 811657869U, // VPUNPCKHBWZ128rr 87059085U, // VPUNPCKHBWZ128rrk 890284685U, // VPUNPCKHBWZ128rrkz 812870285U, // VPUNPCKHBWZ256rm 985131661U, // VPUNPCKHBWZ256rmk 890612365U, // VPUNPCKHBWZ256rmkz 811657869U, // VPUNPCKHBWZ256rr 87059085U, // VPUNPCKHBWZ256rrk 890284685U, // VPUNPCKHBWZ256rrkz 812886669U, // VPUNPCKHBWZrm 985148045U, // VPUNPCKHBWZrmk 890677901U, // VPUNPCKHBWZrmkz 811657869U, // VPUNPCKHBWZrr 87059085U, // VPUNPCKHBWZrrk 890284685U, // VPUNPCKHBWZrrkz 811854477U, // VPUNPCKHBWrm 811657869U, // VPUNPCKHBWrr 812866169U, // VPUNPCKHDQYrm 811653753U, // VPUNPCKHDQYrr 811850361U, // VPUNPCKHDQZ128rm 360798841U, // VPUNPCKHDQZ128rmb 1436064377U, // VPUNPCKHDQZ128rmbk 1167481465U, // VPUNPCKHDQZ128rmbkz 985111161U, // VPUNPCKHDQZ128rmk 890575481U, // VPUNPCKHDQZ128rmkz 811653753U, // VPUNPCKHDQZ128rr 87054969U, // VPUNPCKHDQZ128rrk 890280569U, // VPUNPCKHDQZ128rrkz 812866169U, // VPUNPCKHDQZ256rm 362895993U, // VPUNPCKHDQZ256rmb 1438161529U, // VPUNPCKHDQZ256rmbk 1169578617U, // VPUNPCKHDQZ256rmbkz 985127545U, // VPUNPCKHDQZ256rmk 890608249U, // VPUNPCKHDQZ256rmkz 811653753U, // VPUNPCKHDQZ256rr 87054969U, // VPUNPCKHDQZ256rrk 890280569U, // VPUNPCKHDQZ256rrkz 812882553U, // VPUNPCKHDQZrm 364993145U, // VPUNPCKHDQZrmb 1440258681U, // VPUNPCKHDQZrmbk 1171675769U, // VPUNPCKHDQZrmbkz 985143929U, // VPUNPCKHDQZrmk 890673785U, // VPUNPCKHDQZrmkz 811653753U, // VPUNPCKHDQZrr 87054969U, // VPUNPCKHDQZrrk 890280569U, // VPUNPCKHDQZrrkz 811850361U, // VPUNPCKHDQrm 811653753U, // VPUNPCKHDQrr 812866287U, // VPUNPCKHQDQYrm 811653871U, // VPUNPCKHQDQYrr 811850479U, // VPUNPCKHQDQZ128rm 358718191U, // VPUNPCKHQDQZ128rmb 1433950959U, // VPUNPCKHQDQZ128rmbk 1165286127U, // VPUNPCKHQDQZ128rmbkz 985111279U, // VPUNPCKHQDQZ128rmk 890575599U, // VPUNPCKHQDQZ128rmkz 811653871U, // VPUNPCKHQDQZ128rr 87055087U, // VPUNPCKHQDQZ128rrk 890280687U, // VPUNPCKHQDQZ128rrkz 812866287U, // VPUNPCKHQDQZ256rm 360815343U, // VPUNPCKHQDQZ256rmb 1436048111U, // VPUNPCKHQDQZ256rmbk 1167383279U, // VPUNPCKHQDQZ256rmbkz 985127663U, // VPUNPCKHQDQZ256rmk 890608367U, // VPUNPCKHQDQZ256rmkz 811653871U, // VPUNPCKHQDQZ256rr 87055087U, // VPUNPCKHQDQZ256rrk 890280687U, // VPUNPCKHQDQZ256rrkz 812882671U, // VPUNPCKHQDQZrm 362912495U, // VPUNPCKHQDQZrmb 1438145263U, // VPUNPCKHQDQZrmbk 1169480431U, // VPUNPCKHQDQZrmbkz 985144047U, // VPUNPCKHQDQZrmk 890673903U, // VPUNPCKHQDQZrmkz 811653871U, // VPUNPCKHQDQZrr 87055087U, // VPUNPCKHQDQZrrk 890280687U, // VPUNPCKHQDQZrrkz 811850479U, // VPUNPCKHQDQrm 811653871U, // VPUNPCKHQDQrr 812863767U, // VPUNPCKHWDYrm 811651351U, // VPUNPCKHWDYrr 811847959U, // VPUNPCKHWDZ128rm 985108759U, // VPUNPCKHWDZ128rmk 890573079U, // VPUNPCKHWDZ128rmkz 811651351U, // VPUNPCKHWDZ128rr 87052567U, // VPUNPCKHWDZ128rrk 890278167U, // VPUNPCKHWDZ128rrkz 812863767U, // VPUNPCKHWDZ256rm 985125143U, // VPUNPCKHWDZ256rmk 890605847U, // VPUNPCKHWDZ256rmkz 811651351U, // VPUNPCKHWDZ256rr 87052567U, // VPUNPCKHWDZ256rrk 890278167U, // VPUNPCKHWDZ256rrkz 812880151U, // VPUNPCKHWDZrm 985141527U, // VPUNPCKHWDZrmk 890671383U, // VPUNPCKHWDZrmkz 811651351U, // VPUNPCKHWDZrr 87052567U, // VPUNPCKHWDZrrk 890278167U, // VPUNPCKHWDZrrkz 811847959U, // VPUNPCKHWDrm 811651351U, // VPUNPCKHWDrr 812870307U, // VPUNPCKLBWYrm 811657891U, // VPUNPCKLBWYrr 811854499U, // VPUNPCKLBWZ128rm 985115299U, // VPUNPCKLBWZ128rmk 890579619U, // VPUNPCKLBWZ128rmkz 811657891U, // VPUNPCKLBWZ128rr 87059107U, // VPUNPCKLBWZ128rrk 890284707U, // VPUNPCKLBWZ128rrkz 812870307U, // VPUNPCKLBWZ256rm 985131683U, // VPUNPCKLBWZ256rmk 890612387U, // VPUNPCKLBWZ256rmkz 811657891U, // VPUNPCKLBWZ256rr 87059107U, // VPUNPCKLBWZ256rrk 890284707U, // VPUNPCKLBWZ256rrkz 812886691U, // VPUNPCKLBWZrm 985148067U, // VPUNPCKLBWZrmk 890677923U, // VPUNPCKLBWZrmkz 811657891U, // VPUNPCKLBWZrr 87059107U, // VPUNPCKLBWZrrk 890284707U, // VPUNPCKLBWZrrkz 811854499U, // VPUNPCKLBWrm 811657891U, // VPUNPCKLBWrr 812866200U, // VPUNPCKLDQYrm 811653784U, // VPUNPCKLDQYrr 811850392U, // VPUNPCKLDQZ128rm 360798872U, // VPUNPCKLDQZ128rmb 1436064408U, // VPUNPCKLDQZ128rmbk 1167481496U, // VPUNPCKLDQZ128rmbkz 985111192U, // VPUNPCKLDQZ128rmk 890575512U, // VPUNPCKLDQZ128rmkz 811653784U, // VPUNPCKLDQZ128rr 87055000U, // VPUNPCKLDQZ128rrk 890280600U, // VPUNPCKLDQZ128rrkz 812866200U, // VPUNPCKLDQZ256rm 362896024U, // VPUNPCKLDQZ256rmb 1438161560U, // VPUNPCKLDQZ256rmbk 1169578648U, // VPUNPCKLDQZ256rmbkz 985127576U, // VPUNPCKLDQZ256rmk 890608280U, // VPUNPCKLDQZ256rmkz 811653784U, // VPUNPCKLDQZ256rr 87055000U, // VPUNPCKLDQZ256rrk 890280600U, // VPUNPCKLDQZ256rrkz 812882584U, // VPUNPCKLDQZrm 364993176U, // VPUNPCKLDQZrmb 1440258712U, // VPUNPCKLDQZrmbk 1171675800U, // VPUNPCKLDQZrmbkz 985143960U, // VPUNPCKLDQZrmk 890673816U, // VPUNPCKLDQZrmkz 811653784U, // VPUNPCKLDQZrr 87055000U, // VPUNPCKLDQZrrk 890280600U, // VPUNPCKLDQZrrkz 811850392U, // VPUNPCKLDQrm 811653784U, // VPUNPCKLDQrr 812866300U, // VPUNPCKLQDQYrm 811653884U, // VPUNPCKLQDQYrr 811850492U, // VPUNPCKLQDQZ128rm 358718204U, // VPUNPCKLQDQZ128rmb 1433950972U, // VPUNPCKLQDQZ128rmbk 1165286140U, // VPUNPCKLQDQZ128rmbkz 985111292U, // VPUNPCKLQDQZ128rmk 890575612U, // VPUNPCKLQDQZ128rmkz 811653884U, // VPUNPCKLQDQZ128rr 87055100U, // VPUNPCKLQDQZ128rrk 890280700U, // VPUNPCKLQDQZ128rrkz 812866300U, // VPUNPCKLQDQZ256rm 360815356U, // VPUNPCKLQDQZ256rmb 1436048124U, // VPUNPCKLQDQZ256rmbk 1167383292U, // VPUNPCKLQDQZ256rmbkz 985127676U, // VPUNPCKLQDQZ256rmk 890608380U, // VPUNPCKLQDQZ256rmkz 811653884U, // VPUNPCKLQDQZ256rr 87055100U, // VPUNPCKLQDQZ256rrk 890280700U, // VPUNPCKLQDQZ256rrkz 812882684U, // VPUNPCKLQDQZrm 362912508U, // VPUNPCKLQDQZrmb 1438145276U, // VPUNPCKLQDQZrmbk 1169480444U, // VPUNPCKLQDQZrmbkz 985144060U, // VPUNPCKLQDQZrmk 890673916U, // VPUNPCKLQDQZrmkz 811653884U, // VPUNPCKLQDQZrr 87055100U, // VPUNPCKLQDQZrrk 890280700U, // VPUNPCKLQDQZrrkz 811850492U, // VPUNPCKLQDQrm 811653884U, // VPUNPCKLQDQrr 812863789U, // VPUNPCKLWDYrm 811651373U, // VPUNPCKLWDYrr 811847981U, // VPUNPCKLWDZ128rm 985108781U, // VPUNPCKLWDZ128rmk 890573101U, // VPUNPCKLWDZ128rmkz 811651373U, // VPUNPCKLWDZ128rr 87052589U, // VPUNPCKLWDZ128rrk 890278189U, // VPUNPCKLWDZ128rrkz 812863789U, // VPUNPCKLWDZ256rm 985125165U, // VPUNPCKLWDZ256rmk 890605869U, // VPUNPCKLWDZ256rmkz 811651373U, // VPUNPCKLWDZ256rr 87052589U, // VPUNPCKLWDZ256rrk 890278189U, // VPUNPCKLWDZ256rrkz 812880173U, // VPUNPCKLWDZrm 985141549U, // VPUNPCKLWDZrmk 890671405U, // VPUNPCKLWDZrmkz 811651373U, // VPUNPCKLWDZrr 87052589U, // VPUNPCKLWDZrrk 890278189U, // VPUNPCKLWDZrrkz 811847981U, // VPUNPCKLWDrm 811651373U, // VPUNPCKLWDrr 811847112U, // VPXORDZ128rm 360795592U, // VPXORDZ128rmb 1436061128U, // VPXORDZ128rmbk 1167478216U, // VPXORDZ128rmbkz 985107912U, // VPXORDZ128rmk 890572232U, // VPXORDZ128rmkz 811650504U, // VPXORDZ128rr 87051720U, // VPXORDZ128rrk 890277320U, // VPXORDZ128rrkz 812862920U, // VPXORDZ256rm 362892744U, // VPXORDZ256rmb 1438158280U, // VPXORDZ256rmbk 1169575368U, // VPXORDZ256rmbkz 985124296U, // VPXORDZ256rmk 890605000U, // VPXORDZ256rmkz 811650504U, // VPXORDZ256rr 87051720U, // VPXORDZ256rrk 890277320U, // VPXORDZ256rrkz 812879304U, // VPXORDZrm 364989896U, // VPXORDZrmb 1440255432U, // VPXORDZrmbk 1171672520U, // VPXORDZrmbkz 985140680U, // VPXORDZrmk 890670536U, // VPXORDZrmkz 811650504U, // VPXORDZrr 87051720U, // VPXORDZrrk 890277320U, // VPXORDZrrkz 811851380U, // VPXORQZ128rm 358719092U, // VPXORQZ128rmb 1433951860U, // VPXORQZ128rmbk 1165287028U, // VPXORQZ128rmbkz 985112180U, // VPXORQZ128rmk 890576500U, // VPXORQZ128rmkz 811654772U, // VPXORQZ128rr 87055988U, // VPXORQZ128rrk 890281588U, // VPXORQZ128rrkz 812867188U, // VPXORQZ256rm 360816244U, // VPXORQZ256rmb 1436049012U, // VPXORQZ256rmbk 1167384180U, // VPXORQZ256rmbkz 985128564U, // VPXORQZ256rmk 890609268U, // VPXORQZ256rmkz 811654772U, // VPXORQZ256rr 87055988U, // VPXORQZ256rrk 890281588U, // VPXORQZ256rrkz 812883572U, // VPXORQZrm 362913396U, // VPXORQZrmb 1438146164U, // VPXORQZrmbk 1169481332U, // VPXORQZrmbkz 985144948U, // VPXORQZrmk 890674804U, // VPXORQZrmkz 811654772U, // VPXORQZrr 87055988U, // VPXORQZrrk 890281588U, // VPXORQZrrkz 812867912U, // VPXORYrm 811655496U, // VPXORYrr 811852104U, // VPXORrm 811655496U, // VPXORrr 2999307181U, // VRANGEPDZ128rmbi 3111373741U, // VRANGEPDZ128rmbik 3079932845U, // VRANGEPDZ128rmbikz 300272557U, // VRANGEPDZ128rmi 2039729069U, // VRANGEPDZ128rmik 1202981805U, // VRANGEPDZ128rmikz 1088818093U, // VRANGEPDZ128rri 2163133357U, // VRANGEPDZ128rrik 1357581229U, // VRANGEPDZ128rrikz 1657129901U, // VRANGEPDZ256rmbi 1769196461U, // VRANGEPDZ256rmbik 1737755565U, // VRANGEPDZ256rmbikz 392547245U, // VRANGEPDZ256rmi 2041826221U, // VRANGEPDZ256rmik 1205078957U, // VRANGEPDZ256rmikz 1088818093U, // VRANGEPDZ256rri 2163133357U, // VRANGEPDZ256rrik 1357581229U, // VRANGEPDZ256rrikz 2462436269U, // VRANGEPDZrmbi 2574502829U, // VRANGEPDZrmbik 2543061933U, // VRANGEPDZrmbikz 400935853U, // VRANGEPDZrmi 2043923373U, // VRANGEPDZrmik 1209273261U, // VRANGEPDZrmikz 1088818093U, // VRANGEPDZrri 1212550061U, // VRANGEPDZrrib 2286865325U, // VRANGEPDZrribk 1481313197U, // VRANGEPDZrribkz 2163133357U, // VRANGEPDZrrik 1357581229U, // VRANGEPDZrrikz 1661330625U, // VRANGEPSZ128rmbi 1777591489U, // VRANGEPSZ128rmbik 1752442049U, // VRANGEPSZ128rmbikz 300278977U, // VRANGEPSZ128rmi 2039735489U, // VRANGEPSZ128rmik 1202988225U, // VRANGEPSZ128rmikz 1088824513U, // VRANGEPSZ128rri 2163139777U, // VRANGEPSZ128rrik 1357587649U, // VRANGEPSZ128rrikz 2466636993U, // VRANGEPSZ256rmbi 2582897857U, // VRANGEPSZ256rmbik 2557748417U, // VRANGEPSZ256rmbikz 392553665U, // VRANGEPSZ256rmi 2041832641U, // VRANGEPSZ256rmik 1205085377U, // VRANGEPSZ256rmikz 1088824513U, // VRANGEPSZ256rri 2163139777U, // VRANGEPSZ256rrik 1357587649U, // VRANGEPSZ256rrikz 2735072449U, // VRANGEPSZrmbi 2851333313U, // VRANGEPSZrmbik 2826183873U, // VRANGEPSZrmbikz 400942273U, // VRANGEPSZrmi 2043929793U, // VRANGEPSZrmik 1209279681U, // VRANGEPSZrmikz 1088824513U, // VRANGEPSZrri 1212556481U, // VRANGEPSZrrib 2286871745U, // VRANGEPSZrribk 1481319617U, // VRANGEPSZrribkz 2163139777U, // VRANGEPSZrrik 1357587649U, // VRANGEPSZrrikz 851824412U, // VRANGESDZrmi 963890972U, // VRANGESDZrmik 932450076U, // VRANGESDZrmikz 1088818972U, // VRANGESDZrri 1212550940U, // VRANGESDZrrib 2286866204U, // VRANGESDZrribk 1481314076U, // VRANGESDZrribkz 2163134236U, // VRANGESDZrrik 1357582108U, // VRANGESDZrrikz 856025134U, // VRANGESSZrmi 972285998U, // VRANGESSZrmik 947136558U, // VRANGESSZrmikz 1088825390U, // VRANGESSZrri 1212557358U, // VRANGESSZrrib 2286872622U, // VRANGESSZrribk 1481320494U, // VRANGESSZrribkz 2163140654U, // VRANGESSZrrik 1357588526U, // VRANGESSZrrikz 658038U, // VRCP14PDZ128m 627673718U, // VRCP14PDZ128mb 628099702U, // VRCP14PDZ128mbk 627198582U, // VRCP14PDZ128mbkz 3230599798U, // VRCP14PDZ128mk 3229747830U, // VRCP14PDZ128mkz 551832182U, // VRCP14PDZ128r 3230698102U, // VRCP14PDZ128rk 3229665910U, // VRCP14PDZ128rkz 1346166U, // VRCP14PDZ256m 629770870U, // VRCP14PDZ256mb 630196854U, // VRCP14PDZ256mbk 629295734U, // VRCP14PDZ256mbkz 3230730870U, // VRCP14PDZ256mk 3230632566U, // VRCP14PDZ256mkz 551832182U, // VRCP14PDZ256r 3230698102U, // VRCP14PDZ256rk 3229665910U, // VRCP14PDZ256rkz 1510006U, // VRCP14PDZm 631868022U, // VRCP14PDZmb 632294006U, // VRCP14PDZmbk 631392886U, // VRCP14PDZmbkz 3230780022U, // VRCP14PDZmk 3230747254U, // VRCP14PDZmkz 551832182U, // VRCP14PDZr 3230698102U, // VRCP14PDZrk 3229665910U, // VRCP14PDZrkz 664443U, // VRCP14PSZ128m 629793659U, // VRCP14PSZ128mb 630399867U, // VRCP14PSZ128mbk 629318523U, // VRCP14PSZ128mbkz 3230606203U, // VRCP14PSZ128mk 3229754235U, // VRCP14PSZ128mkz 551838587U, // VRCP14PSZ128r 3230704507U, // VRCP14PSZ128rk 3229672315U, // VRCP14PSZ128rkz 1352571U, // VRCP14PSZ256m 631890811U, // VRCP14PSZ256mb 632497019U, // VRCP14PSZ256mbk 631415675U, // VRCP14PSZ256mbkz 3230737275U, // VRCP14PSZ256mk 3230638971U, // VRCP14PSZ256mkz 551838587U, // VRCP14PSZ256r 3230704507U, // VRCP14PSZ256rk 3229672315U, // VRCP14PSZ256rkz 1516411U, // VRCP14PSZm 633987963U, // VRCP14PSZmb 634594171U, // VRCP14PSZmbk 633512827U, // VRCP14PSZmbkz 3230786427U, // VRCP14PSZmk 3230753659U, // VRCP14PSZmkz 551838587U, // VRCP14PSZr 3230704507U, // VRCP14PSZrk 3229672315U, // VRCP14PSZrkz 283266713U, // VRCP14SDZrm 1357893273U, // VRCP14SDZrmk 1089474201U, // VRCP14SDZrmkz 811650713U, // VRCP14SDZrr 87051929U, // VRCP14SDZrrk 890277529U, // VRCP14SDZrrkz 283289500U, // VRCP14SSZrm 1358096284U, // VRCP14SSZrmk 1089677212U, // VRCP14SSZrmkz 811657116U, // VRCP14SSZrr 87058332U, // VRCP14SSZrrk 890283932U, // VRCP14SSZrrkz 1510028U, // VRCP28PDZm 631868044U, // VRCP28PDZmb 632294028U, // VRCP28PDZmbk 631392908U, // VRCP28PDZmbkz 3230780044U, // VRCP28PDZmk 3230747276U, // VRCP28PDZmkz 551832204U, // VRCP28PDZr 551843284U, // VRCP28PDZrb 3230709204U, // VRCP28PDZrbk 3229677012U, // VRCP28PDZrbkz 3230698124U, // VRCP28PDZrk 3229665932U, // VRCP28PDZrkz 1516433U, // VRCP28PSZm 633987985U, // VRCP28PSZmb 634594193U, // VRCP28PSZmbk 633512849U, // VRCP28PSZmbkz 3230786449U, // VRCP28PSZmk 3230753681U, // VRCP28PSZmkz 551838609U, // VRCP28PSZr 551843771U, // VRCP28PSZrb 3230709691U, // VRCP28PSZrbk 3229677499U, // VRCP28PSZrbkz 3230704529U, // VRCP28PSZrk 3229672337U, // VRCP28PSZrkz 283266735U, // VRCP28SDZm 1357893295U, // VRCP28SDZmk 1089474223U, // VRCP28SDZmkz 811650735U, // VRCP28SDZr 811660858U, // VRCP28SDZrb 87062074U, // VRCP28SDZrbk 890287674U, // VRCP28SDZrbkz 87051951U, // VRCP28SDZrk 890277551U, // VRCP28SDZrkz 283289522U, // VRCP28SSZm 1358096306U, // VRCP28SSZmk 1089677234U, // VRCP28SSZmkz 811657138U, // VRCP28SSZr 811661327U, // VRCP28SSZrb 87062543U, // VRCP28SSZrbk 890288143U, // VRCP28SSZrbkz 87058354U, // VRCP28SSZrk 890283954U, // VRCP28SSZrkz 1353097U, // VRCPPSYm 551839113U, // VRCPPSYr 664969U, // VRCPPSm 551839113U, // VRCPPSr 283289728U, // VRCPSSm 283289728U, // VRCPSSm_Int 811657344U, // VRCPSSr 811657344U, // VRCPSSr_Int 3032779682U, // VREDUCEPDZ128rmbi 3079932834U, // VREDUCEPDZ128rmbik 2999307170U, // VREDUCEPDZ128rmbikz 77892514U, // VREDUCEPDZ128rmi 666110882U, // VREDUCEPDZ128rmik 568708002U, // VREDUCEPDZ128rmikz 283429794U, // VREDUCEPDZ128rri 1357581218U, // VREDUCEPDZ128rrik 1088818082U, // VREDUCEPDZ128rrikz 1690602402U, // VREDUCEPDZ256rmbi 1737755554U, // VREDUCEPDZ256rmbik 1657129890U, // VREDUCEPDZ256rmbikz 168070050U, // VREDUCEPDZ256rmi 668208034U, // VREDUCEPDZ256rmik 660982690U, // VREDUCEPDZ256rmikz 283429794U, // VREDUCEPDZ256rri 1357581218U, // VREDUCEPDZ256rrik 1088818082U, // VREDUCEPDZ256rrikz 2495908770U, // VREDUCEPDZrmbi 2543061922U, // VREDUCEPDZrmbik 2462436258U, // VREDUCEPDZrmbikz 170167202U, // VREDUCEPDZrmi 672402338U, // VREDUCEPDZrmik 669371298U, // VREDUCEPDZrmikz 283429794U, // VREDUCEPDZrri 407161762U, // VREDUCEPDZrrib 1481313186U, // VREDUCEPDZrribk 1212550050U, // VREDUCEPDZrribkz 1357581218U, // VREDUCEPDZrrik 1088818082U, // VREDUCEPDZrrikz 1692705974U, // VREDUCEPSZ128rmbi 1752442038U, // VREDUCEPSZ128rmbik 1661330614U, // VREDUCEPSZ128rmbikz 77898934U, // VREDUCEPSZ128rmi 666117302U, // VREDUCEPSZ128rmik 568714422U, // VREDUCEPSZ128rmikz 283436214U, // VREDUCEPSZ128rri 1357587638U, // VREDUCEPSZ128rrik 1088824502U, // VREDUCEPSZ128rrikz 2498012342U, // VREDUCEPSZ256rmbi 2557748406U, // VREDUCEPSZ256rmbik 2466636982U, // VREDUCEPSZ256rmbikz 168076470U, // VREDUCEPSZ256rmi 668214454U, // VREDUCEPSZ256rmik 660989110U, // VREDUCEPSZ256rmikz 283436214U, // VREDUCEPSZ256rri 1357587638U, // VREDUCEPSZ256rrik 1088824502U, // VREDUCEPSZ256rrikz 2766447798U, // VREDUCEPSZrmbi 2826183862U, // VREDUCEPSZrmbik 2735072438U, // VREDUCEPSZrmbikz 170173622U, // VREDUCEPSZrmi 672408758U, // VREDUCEPSZrmik 669377718U, // VREDUCEPSZrmikz 283436214U, // VREDUCEPSZrri 407168182U, // VREDUCEPSZrrib 1481319606U, // VREDUCEPSZrribk 1212556470U, // VREDUCEPSZrribkz 1357587638U, // VREDUCEPSZrrik 1088824502U, // VREDUCEPSZrrikz 851824401U, // VREDUCESDZrmi 963890961U, // VREDUCESDZrmik 932450065U, // VREDUCESDZrmikz 1088818961U, // VREDUCESDZrri 1212550929U, // VREDUCESDZrrib 2286866193U, // VREDUCESDZrribk 1481314065U, // VREDUCESDZrribkz 2163134225U, // VREDUCESDZrrik 1357582097U, // VREDUCESDZrrikz 856025123U, // VREDUCESSZrmi 972285987U, // VREDUCESSZrmik 947136547U, // VREDUCESSZrmikz 1088825379U, // VREDUCESSZrri 1212557347U, // VREDUCESSZrrib 2286872611U, // VREDUCESSZrribk 1481320483U, // VREDUCESSZrribkz 2163140643U, // VREDUCESSZrrik 1357588515U, // VREDUCESSZrrikz 3032779703U, // VRNDSCALEPDZ128rmbi 3079932855U, // VRNDSCALEPDZ128rmbik 2999307191U, // VRNDSCALEPDZ128rmbikz 77892535U, // VRNDSCALEPDZ128rmi 666110903U, // VRNDSCALEPDZ128rmik 568708023U, // VRNDSCALEPDZ128rmikz 283429815U, // VRNDSCALEPDZ128rri 1357581239U, // VRNDSCALEPDZ128rrik 1088818103U, // VRNDSCALEPDZ128rrikz 1690602423U, // VRNDSCALEPDZ256rmbi 1737755575U, // VRNDSCALEPDZ256rmbik 1657129911U, // VRNDSCALEPDZ256rmbikz 168070071U, // VRNDSCALEPDZ256rmi 668208055U, // VRNDSCALEPDZ256rmik 660982711U, // VRNDSCALEPDZ256rmikz 283429815U, // VRNDSCALEPDZ256rri 1357581239U, // VRNDSCALEPDZ256rrik 1088818103U, // VRNDSCALEPDZ256rrikz 2495908791U, // VRNDSCALEPDZrmbi 2543061943U, // VRNDSCALEPDZrmbik 2462436279U, // VRNDSCALEPDZrmbikz 170167223U, // VRNDSCALEPDZrmi 672402359U, // VRNDSCALEPDZrmik 669371319U, // VRNDSCALEPDZrmikz 283429815U, // VRNDSCALEPDZrri 407161783U, // VRNDSCALEPDZrrib 1481313207U, // VRNDSCALEPDZrribk 1212550071U, // VRNDSCALEPDZrribkz 1357581239U, // VRNDSCALEPDZrrik 1088818103U, // VRNDSCALEPDZrrikz 1692705995U, // VRNDSCALEPSZ128rmbi 1752442059U, // VRNDSCALEPSZ128rmbik 1661330635U, // VRNDSCALEPSZ128rmbikz 77898955U, // VRNDSCALEPSZ128rmi 666117323U, // VRNDSCALEPSZ128rmik 568714443U, // VRNDSCALEPSZ128rmikz 283436235U, // VRNDSCALEPSZ128rri 1357587659U, // VRNDSCALEPSZ128rrik 1088824523U, // VRNDSCALEPSZ128rrikz 2498012363U, // VRNDSCALEPSZ256rmbi 2557748427U, // VRNDSCALEPSZ256rmbik 2466637003U, // VRNDSCALEPSZ256rmbikz 168076491U, // VRNDSCALEPSZ256rmi 668214475U, // VRNDSCALEPSZ256rmik 660989131U, // VRNDSCALEPSZ256rmikz 283436235U, // VRNDSCALEPSZ256rri 1357587659U, // VRNDSCALEPSZ256rrik 1088824523U, // VRNDSCALEPSZ256rrikz 2766447819U, // VRNDSCALEPSZrmbi 2826183883U, // VRNDSCALEPSZrmbik 2735072459U, // VRNDSCALEPSZrmbikz 170173643U, // VRNDSCALEPSZrmi 672408779U, // VRNDSCALEPSZrmik 669377739U, // VRNDSCALEPSZrmikz 283436235U, // VRNDSCALEPSZrri 407168203U, // VRNDSCALEPSZrrib 1481319627U, // VRNDSCALEPSZrribk 1212556491U, // VRNDSCALEPSZrribkz 1357587659U, // VRNDSCALEPSZrrik 1088824523U, // VRNDSCALEPSZrrikz 851824422U, // VRNDSCALESDZm 851824422U, // VRNDSCALESDZm_Int 963890982U, // VRNDSCALESDZm_Intk 932450086U, // VRNDSCALESDZm_Intkz 1088818982U, // VRNDSCALESDZr 1088818982U, // VRNDSCALESDZr_Int 2163134246U, // VRNDSCALESDZr_Intk 1357582118U, // VRNDSCALESDZr_Intkz 1212550950U, // VRNDSCALESDZrb_Int 2286866214U, // VRNDSCALESDZrb_Intk 1481314086U, // VRNDSCALESDZrb_Intkz 856025144U, // VRNDSCALESSZm 856025144U, // VRNDSCALESSZm_Int 972286008U, // VRNDSCALESSZm_Intk 947136568U, // VRNDSCALESSZm_Intkz 1088825400U, // VRNDSCALESSZr 1088825400U, // VRNDSCALESSZr_Int 2163140664U, // VRNDSCALESSZr_Intk 1357588536U, // VRNDSCALESSZr_Intkz 1212557368U, // VRNDSCALESSZrb_Int 2286872632U, // VRNDSCALESSZrb_Intk 1481320504U, // VRNDSCALESSZrb_Intkz 168070015U, // VROUNDPDYm 283429759U, // VROUNDPDYr 77892479U, // VROUNDPDm 283429759U, // VROUNDPDr 168076435U, // VROUNDPSYm 283436179U, // VROUNDPSYr 77898899U, // VROUNDPSm 283436179U, // VROUNDPSr 851824391U, // VROUNDSDm 851824391U, // VROUNDSDm_Int 1088818951U, // VROUNDSDr 1088818951U, // VROUNDSDr_Int 856025113U, // VROUNDSSm 856025113U, // VROUNDSSm_Int 1088825369U, // VROUNDSSr 1088825369U, // VROUNDSSr_Int 658048U, // VRSQRT14PDZ128m 627673728U, // VRSQRT14PDZ128mb 628099712U, // VRSQRT14PDZ128mbk 627198592U, // VRSQRT14PDZ128mbkz 3230599808U, // VRSQRT14PDZ128mk 3229747840U, // VRSQRT14PDZ128mkz 551832192U, // VRSQRT14PDZ128r 3230698112U, // VRSQRT14PDZ128rk 3229665920U, // VRSQRT14PDZ128rkz 1346176U, // VRSQRT14PDZ256m 629770880U, // VRSQRT14PDZ256mb 630196864U, // VRSQRT14PDZ256mbk 629295744U, // VRSQRT14PDZ256mbkz 3230730880U, // VRSQRT14PDZ256mk 3230632576U, // VRSQRT14PDZ256mkz 551832192U, // VRSQRT14PDZ256r 3230698112U, // VRSQRT14PDZ256rk 3229665920U, // VRSQRT14PDZ256rkz 1510016U, // VRSQRT14PDZm 631868032U, // VRSQRT14PDZmb 632294016U, // VRSQRT14PDZmbk 631392896U, // VRSQRT14PDZmbkz 3230780032U, // VRSQRT14PDZmk 3230747264U, // VRSQRT14PDZmkz 551832192U, // VRSQRT14PDZr 3230698112U, // VRSQRT14PDZrk 3229665920U, // VRSQRT14PDZrkz 664453U, // VRSQRT14PSZ128m 629793669U, // VRSQRT14PSZ128mb 630399877U, // VRSQRT14PSZ128mbk 629318533U, // VRSQRT14PSZ128mbkz 3230606213U, // VRSQRT14PSZ128mk 3229754245U, // VRSQRT14PSZ128mkz 551838597U, // VRSQRT14PSZ128r 3230704517U, // VRSQRT14PSZ128rk 3229672325U, // VRSQRT14PSZ128rkz 1352581U, // VRSQRT14PSZ256m 631890821U, // VRSQRT14PSZ256mb 632497029U, // VRSQRT14PSZ256mbk 631415685U, // VRSQRT14PSZ256mbkz 3230737285U, // VRSQRT14PSZ256mk 3230638981U, // VRSQRT14PSZ256mkz 551838597U, // VRSQRT14PSZ256r 3230704517U, // VRSQRT14PSZ256rk 3229672325U, // VRSQRT14PSZ256rkz 1516421U, // VRSQRT14PSZm 633987973U, // VRSQRT14PSZmb 634594181U, // VRSQRT14PSZmbk 633512837U, // VRSQRT14PSZmbkz 3230786437U, // VRSQRT14PSZmk 3230753669U, // VRSQRT14PSZmkz 551838597U, // VRSQRT14PSZr 3230704517U, // VRSQRT14PSZrk 3229672325U, // VRSQRT14PSZrkz 283266723U, // VRSQRT14SDZrm 1357893283U, // VRSQRT14SDZrmk 1089474211U, // VRSQRT14SDZrmkz 811650723U, // VRSQRT14SDZrr 87051939U, // VRSQRT14SDZrrk 890277539U, // VRSQRT14SDZrrkz 283289510U, // VRSQRT14SSZrm 1358096294U, // VRSQRT14SSZrmk 1089677222U, // VRSQRT14SSZrmkz 811657126U, // VRSQRT14SSZrr 87058342U, // VRSQRT14SSZrrk 890283942U, // VRSQRT14SSZrrkz 1510038U, // VRSQRT28PDZm 631868054U, // VRSQRT28PDZmb 632294038U, // VRSQRT28PDZmbk 631392918U, // VRSQRT28PDZmbkz 3230780054U, // VRSQRT28PDZmk 3230747286U, // VRSQRT28PDZmkz 551832214U, // VRSQRT28PDZr 551843301U, // VRSQRT28PDZrb 3230709221U, // VRSQRT28PDZrbk 3229677029U, // VRSQRT28PDZrbkz 3230698134U, // VRSQRT28PDZrk 3229665942U, // VRSQRT28PDZrkz 1516443U, // VRSQRT28PSZm 633987995U, // VRSQRT28PSZmb 634594203U, // VRSQRT28PSZmbk 633512859U, // VRSQRT28PSZmbkz 3230786459U, // VRSQRT28PSZmk 3230753691U, // VRSQRT28PSZmkz 551838619U, // VRSQRT28PSZr 551843788U, // VRSQRT28PSZrb 3230709708U, // VRSQRT28PSZrbk 3229677516U, // VRSQRT28PSZrbkz 3230704539U, // VRSQRT28PSZrk 3229672347U, // VRSQRT28PSZrkz 283266745U, // VRSQRT28SDZm 1357893305U, // VRSQRT28SDZmk 1089474233U, // VRSQRT28SDZmkz 811650745U, // VRSQRT28SDZr 811660875U, // VRSQRT28SDZrb 87062091U, // VRSQRT28SDZrbk 890287691U, // VRSQRT28SDZrbkz 87051961U, // VRSQRT28SDZrk 890277561U, // VRSQRT28SDZrkz 283289532U, // VRSQRT28SSZm 1358096316U, // VRSQRT28SSZmk 1089677244U, // VRSQRT28SSZmkz 811657148U, // VRSQRT28SSZr 811661344U, // VRSQRT28SSZrb 87062560U, // VRSQRT28SSZrbk 890288160U, // VRSQRT28SSZrbkz 87058364U, // VRSQRT28SSZrk 890283964U, // VRSQRT28SSZrkz 1353303U, // VRSQRTPSYm 551839319U, // VRSQRTPSYr 665175U, // VRSQRTPSm 551839319U, // VRSQRTPSr 283289788U, // VRSQRTSSm 283289788U, // VRSQRTSSm_Int 811657404U, // VRSQRTSSr 811657404U, // VRSQRTSSr_Int 811731908U, // VSCALEFPDZ128rm 358763460U, // VSCALEFPDZ128rmb 1433390020U, // VSCALEFPDZ128rmbk 1164970948U, // VSCALEFPDZ128rmbkz 86985668U, // VSCALEFPDZ128rmk 890178500U, // VSCALEFPDZ128rmkz 811649988U, // VSCALEFPDZ128rr 87051204U, // VSCALEFPDZ128rrk 890276804U, // VSCALEFPDZ128rrkz 812616644U, // VSCALEFPDZ256rm 360860612U, // VSCALEFPDZ256rmb 1435487172U, // VSCALEFPDZ256rmbk 1167068100U, // VSCALEFPDZ256rmbkz 87083972U, // VSCALEFPDZ256rmk 890309572U, // VSCALEFPDZ256rmkz 811649988U, // VSCALEFPDZ256rr 87051204U, // VSCALEFPDZ256rrk 890276804U, // VSCALEFPDZ256rrkz 812731332U, // VSCALEFPDZrm 362957764U, // VSCALEFPDZrmb 1437584324U, // VSCALEFPDZrmbk 1169165252U, // VSCALEFPDZrmbkz 87133124U, // VSCALEFPDZrmk 890358724U, // VSCALEFPDZrmkz 811649988U, // VSCALEFPDZrr 812780484U, // VSCALEFPDZrrb 87182276U, // VSCALEFPDZrrbk 890407876U, // VSCALEFPDZrrbkz 87051204U, // VSCALEFPDZrrk 890276804U, // VSCALEFPDZrrkz 811738328U, // VSCALEFPSZ128rm 360883416U, // VSCALEFPSZ128rmb 1435690200U, // VSCALEFPSZ128rmbk 1167271128U, // VSCALEFPSZ128rmbkz 86992088U, // VSCALEFPSZ128rmk 890184920U, // VSCALEFPSZ128rmkz 811656408U, // VSCALEFPSZ128rr 87057624U, // VSCALEFPSZ128rrk 890283224U, // VSCALEFPSZ128rrkz 812623064U, // VSCALEFPSZ256rm 362980568U, // VSCALEFPSZ256rmb 1437787352U, // VSCALEFPSZ256rmbk 1169368280U, // VSCALEFPSZ256rmbkz 87090392U, // VSCALEFPSZ256rmk 890315992U, // VSCALEFPSZ256rmkz 811656408U, // VSCALEFPSZ256rr 87057624U, // VSCALEFPSZ256rrk 890283224U, // VSCALEFPSZ256rrkz 812737752U, // VSCALEFPSZrm 365077720U, // VSCALEFPSZrmb 1439884504U, // VSCALEFPSZrmbk 1171465432U, // VSCALEFPSZrmbkz 87139544U, // VSCALEFPSZrmk 890365144U, // VSCALEFPSZrmkz 811656408U, // VSCALEFPSZrr 812786904U, // VSCALEFPSZrrb 87188696U, // VSCALEFPSZrrbk 890414296U, // VSCALEFPSZrrbkz 87057624U, // VSCALEFPSZrrk 890283224U, // VSCALEFPSZrrkz 283266867U, // VSCALEFSDZrm 1357893427U, // VSCALEFSDZrmk 1089474355U, // VSCALEFSDZrmkz 811650867U, // VSCALEFSDZrr 812781363U, // VSCALEFSDZrrb_Int 87183155U, // VSCALEFSDZrrb_Intk 890408755U, // VSCALEFSDZrrb_Intkz 87052083U, // VSCALEFSDZrrk 890277683U, // VSCALEFSDZrrkz 283289669U, // VSCALEFSSZrm 1358096453U, // VSCALEFSSZrmk 1089677381U, // VSCALEFSSZrmkz 811657285U, // VSCALEFSSZrr 812787781U, // VSCALEFSSZrrb_Int 87189573U, // VSCALEFSSZrrb_Intk 890415173U, // VSCALEFSSZrrb_Intkz 87058501U, // VSCALEFSSZrrk 890284101U, // VSCALEFSSZrrkz 3247721365U, // VSCATTERDPDZ128mr 3425979285U, // VSCATTERDPDZ256mr 3428076437U, // VSCATTERDPDZmr 3247727785U, // VSCATTERDPSZ128mr 3425985705U, // VSCATTERDPSZ256mr 3428082857U, // VSCATTERDPSZmr 172854016U, // VSCATTERPF0DPDm 172860413U, // VSCATTERPF0DPSm 172854401U, // VSCATTERPF0QPDm 173368762U, // VSCATTERPF0QPSm 172854047U, // VSCATTERPF1DPDm 172860444U, // VSCATTERPF1DPSm 172854432U, // VSCATTERPF1QPDm 173368793U, // VSCATTERPF1QPSm 3247721660U, // VSCATTERQPDZ128mr 3425979580U, // VSCATTERQPDZ256mr 3428076732U, // VSCATTERQPDZmr 3251922421U, // VSCATTERQPSZ128mr 3247728117U, // VSCATTERQPSZ256mr 3425986037U, // VSCATTERQPSZmr 2466627977U, // VSHUFF32X4Z256rmbi 2582888841U, // VSHUFF32X4Z256rmbik 2557739401U, // VSHUFF32X4Z256rmbikz 392544649U, // VSHUFF32X4Z256rmi 2041823625U, // VSHUFF32X4Z256rmik 1205076361U, // VSHUFF32X4Z256rmikz 1088815497U, // VSHUFF32X4Z256rri 2163130761U, // VSHUFF32X4Z256rrik 1357578633U, // VSHUFF32X4Z256rrikz 2735063433U, // VSHUFF32X4Zrmbi 2851324297U, // VSHUFF32X4Zrmbik 2826174857U, // VSHUFF32X4Zrmbikz 400933257U, // VSHUFF32X4Zrmi 2043920777U, // VSHUFF32X4Zrmik 1209270665U, // VSHUFF32X4Zrmikz 1088815497U, // VSHUFF32X4Zrri 2163130761U, // VSHUFF32X4Zrrik 1357578633U, // VSHUFF32X4Zrrikz 1657127092U, // VSHUFF64X2Z256rmbi 1769193652U, // VSHUFF64X2Z256rmbik 1737752756U, // VSHUFF64X2Z256rmbikz 392544436U, // VSHUFF64X2Z256rmi 2041823412U, // VSHUFF64X2Z256rmik 1205076148U, // VSHUFF64X2Z256rmikz 1088815284U, // VSHUFF64X2Z256rri 2163130548U, // VSHUFF64X2Z256rrik 1357578420U, // VSHUFF64X2Z256rrikz 2462433460U, // VSHUFF64X2Zrmbi 2574500020U, // VSHUFF64X2Zrmbik 2543059124U, // VSHUFF64X2Zrmbikz 400933044U, // VSHUFF64X2Zrmi 2043920564U, // VSHUFF64X2Zrmik 1209270452U, // VSHUFF64X2Zrmikz 1088815284U, // VSHUFF64X2Zrri 2163130548U, // VSHUFF64X2Zrrik 1357578420U, // VSHUFF64X2Zrrikz 2491793859U, // VSHUFI32X4Z256rmbi 2515780035U, // VSHUFI32X4Z256rmbik 2517893571U, // VSHUFI32X4Z256rmbikz 375767491U, // VSHUFI32X4Z256rmi 1989394883U, // VSHUFI32X4Z256rmik 1186202051U, // VSHUFI32X4Z256rmikz 1088815555U, // VSHUFI32X4Z256rri 2163130819U, // VSHUFI32X4Z256rrik 1357578691U, // VSHUFI32X4Z256rrikz 2760229315U, // VSHUFI32X4Zrmbi 2784215491U, // VSHUFI32X4Zrmbik 2786329027U, // VSHUFI32X4Zrmbikz 382058947U, // VSHUFI32X4Zrmi 1995686339U, // VSHUFI32X4Zrmik 1192493507U, // VSHUFI32X4Zrmikz 1088815555U, // VSHUFI32X4Zrri 2163130819U, // VSHUFI32X4Zrrik 1357578691U, // VSHUFI32X4Zrrikz 1671807214U, // VSHUFI64X2Z256rmbi 1731444974U, // VSHUFI64X2Z256rmbik 1733558510U, // VSHUFI64X2Z256rmbikz 375767278U, // VSHUFI64X2Z256rmi 1989394670U, // VSHUFI64X2Z256rmik 1186201838U, // VSHUFI64X2Z256rmikz 1088815342U, // VSHUFI64X2Z256rri 2163130606U, // VSHUFI64X2Z256rrik 1357578478U, // VSHUFI64X2Z256rrikz 2477113582U, // VSHUFI64X2Zrmbi 2536751342U, // VSHUFI64X2Zrmbik 2538864878U, // VSHUFI64X2Zrmbikz 382058734U, // VSHUFI64X2Zrmi 1995686126U, // VSHUFI64X2Zrmik 1192493294U, // VSHUFI64X2Zrmikz 1088815342U, // VSHUFI64X2Zrri 2163130606U, // VSHUFI64X2Zrrik 1357578478U, // VSHUFI64X2Zrrikz 392547279U, // VSHUFPDYrmi 1088818127U, // VSHUFPDYrri 2999307215U, // VSHUFPDZ128rmbi 3111373775U, // VSHUFPDZ128rmbik 3079932879U, // VSHUFPDZ128rmbikz 300272591U, // VSHUFPDZ128rmi 2039729103U, // VSHUFPDZ128rmik 1202981839U, // VSHUFPDZ128rmikz 1088818127U, // VSHUFPDZ128rri 2163133391U, // VSHUFPDZ128rrik 1357581263U, // VSHUFPDZ128rrikz 1657129935U, // VSHUFPDZ256rmbi 1769196495U, // VSHUFPDZ256rmbik 1737755599U, // VSHUFPDZ256rmbikz 392547279U, // VSHUFPDZ256rmi 2041826255U, // VSHUFPDZ256rmik 1205078991U, // VSHUFPDZ256rmikz 1088818127U, // VSHUFPDZ256rri 2163133391U, // VSHUFPDZ256rrik 1357581263U, // VSHUFPDZ256rrikz 2462436303U, // VSHUFPDZrmbi 2574502863U, // VSHUFPDZrmbik 2543061967U, // VSHUFPDZrmbikz 400935887U, // VSHUFPDZrmi 2043923407U, // VSHUFPDZrmik 1209273295U, // VSHUFPDZrmikz 1088818127U, // VSHUFPDZrri 2163133391U, // VSHUFPDZrrik 1357581263U, // VSHUFPDZrrikz 300272591U, // VSHUFPDrmi 1088818127U, // VSHUFPDrri 392553699U, // VSHUFPSYrmi 1088824547U, // VSHUFPSYrri 1661330659U, // VSHUFPSZ128rmbi 1777591523U, // VSHUFPSZ128rmbik 1752442083U, // VSHUFPSZ128rmbikz 300279011U, // VSHUFPSZ128rmi 2039735523U, // VSHUFPSZ128rmik 1202988259U, // VSHUFPSZ128rmikz 1088824547U, // VSHUFPSZ128rri 2163139811U, // VSHUFPSZ128rrik 1357587683U, // VSHUFPSZ128rrikz 2466637027U, // VSHUFPSZ256rmbi 2582897891U, // VSHUFPSZ256rmbik 2557748451U, // VSHUFPSZ256rmbikz 392553699U, // VSHUFPSZ256rmi 2041832675U, // VSHUFPSZ256rmik 1205085411U, // VSHUFPSZ256rmikz 1088824547U, // VSHUFPSZ256rri 2163139811U, // VSHUFPSZ256rrik 1357587683U, // VSHUFPSZ256rrikz 2735072483U, // VSHUFPSZrmbi 2851333347U, // VSHUFPSZrmbik 2826183907U, // VSHUFPSZrmbikz 400942307U, // VSHUFPSZrmi 2043929827U, // VSHUFPSZrmik 1209279715U, // VSHUFPSZrmikz 1088824547U, // VSHUFPSZrri 2163139811U, // VSHUFPSZrrik 1357587683U, // VSHUFPSZrrikz 300279011U, // VSHUFPSrmi 1088824547U, // VSHUFPSrri 1346840U, // VSQRTPDYm 551832856U, // VSQRTPDYr 658712U, // VSQRTPDZ128m 627674392U, // VSQRTPDZ128mb 628100376U, // VSQRTPDZ128mbk 627199256U, // VSQRTPDZ128mbkz 3230600472U, // VSQRTPDZ128mk 3229748504U, // VSQRTPDZ128mkz 551832856U, // VSQRTPDZ128r 3230698776U, // VSQRTPDZ128rk 3229666584U, // VSQRTPDZ128rkz 1346840U, // VSQRTPDZ256m 629771544U, // VSQRTPDZ256mb 630197528U, // VSQRTPDZ256mbk 629296408U, // VSQRTPDZ256mbkz 3230731544U, // VSQRTPDZ256mk 3230633240U, // VSQRTPDZ256mkz 551832856U, // VSQRTPDZ256r 3230698776U, // VSQRTPDZ256rk 3229666584U, // VSQRTPDZ256rkz 1510680U, // VSQRTPDZm 631868696U, // VSQRTPDZmb 632294680U, // VSQRTPDZmbk 631393560U, // VSQRTPDZmbkz 3230780696U, // VSQRTPDZmk 3230747928U, // VSQRTPDZmkz 551832856U, // VSQRTPDZr 1494296U, // VSQRTPDZrb 3230829848U, // VSQRTPDZrbk 3230797080U, // VSQRTPDZrbkz 3230698776U, // VSQRTPDZrk 3229666584U, // VSQRTPDZrkz 658712U, // VSQRTPDm 551832856U, // VSQRTPDr 1353313U, // VSQRTPSYm 551839329U, // VSQRTPSYr 665185U, // VSQRTPSZ128m 629794401U, // VSQRTPSZ128mb 630400609U, // VSQRTPSZ128mbk 629319265U, // VSQRTPSZ128mbkz 3230606945U, // VSQRTPSZ128mk 3229754977U, // VSQRTPSZ128mkz 551839329U, // VSQRTPSZ128r 3230705249U, // VSQRTPSZ128rk 3229673057U, // VSQRTPSZ128rkz 1353313U, // VSQRTPSZ256m 631891553U, // VSQRTPSZ256mb 632497761U, // VSQRTPSZ256mbk 631416417U, // VSQRTPSZ256mbkz 3230738017U, // VSQRTPSZ256mk 3230639713U, // VSQRTPSZ256mkz 551839329U, // VSQRTPSZ256r 3230705249U, // VSQRTPSZ256rk 3229673057U, // VSQRTPSZ256rkz 1517153U, // VSQRTPSZm 633988705U, // VSQRTPSZmb 634594913U, // VSQRTPSZmbk 633513569U, // VSQRTPSZmbkz 3230787169U, // VSQRTPSZmk 3230754401U, // VSQRTPSZmkz 551839329U, // VSQRTPSZr 1500769U, // VSQRTPSZrb 3230836321U, // VSQRTPSZrbk 3230803553U, // VSQRTPSZrbkz 3230705249U, // VSQRTPSZrk 3229673057U, // VSQRTPSZrkz 665185U, // VSQRTPSm 551839329U, // VSQRTPSr 283267036U, // VSQRTSDZm 283267036U, // VSQRTSDZm_Int 1357893596U, // VSQRTSDZm_Intk 1089474524U, // VSQRTSDZm_Intkz 811651036U, // VSQRTSDZr 811651036U, // VSQRTSDZr_Int 87052252U, // VSQRTSDZr_Intk 890277852U, // VSQRTSDZr_Intkz 812781532U, // VSQRTSDZrb_Int 87183324U, // VSQRTSDZrb_Intk 890408924U, // VSQRTSDZrb_Intkz 283267036U, // VSQRTSDm 283267036U, // VSQRTSDm_Int 811651036U, // VSQRTSDr 811651036U, // VSQRTSDr_Int 283289798U, // VSQRTSSZm 283289798U, // VSQRTSSZm_Int 1358096582U, // VSQRTSSZm_Intk 1089677510U, // VSQRTSSZm_Intkz 811657414U, // VSQRTSSZr 811657414U, // VSQRTSSZr_Int 87058630U, // VSQRTSSZr_Intk 890284230U, // VSQRTSSZr_Intkz 812787910U, // VSQRTSSZrb_Int 87189702U, // VSQRTSSZrb_Intk 890415302U, // VSQRTSSZrb_Intkz 283289798U, // VSQRTSSm 283289798U, // VSQRTSSm_Int 811657414U, // VSQRTSSr 811657414U, // VSQRTSSr_Int 237919U, // VSTMXCSR 812616425U, // VSUBPDYrm 811649769U, // VSUBPDYrr 811731689U, // VSUBPDZ128rm 358763241U, // VSUBPDZ128rmb 1433389801U, // VSUBPDZ128rmbk 1164970729U, // VSUBPDZ128rmbkz 86985449U, // VSUBPDZ128rmk 890178281U, // VSUBPDZ128rmkz 811649769U, // VSUBPDZ128rr 87050985U, // VSUBPDZ128rrk 890276585U, // VSUBPDZ128rrkz 812616425U, // VSUBPDZ256rm 360860393U, // VSUBPDZ256rmb 1435486953U, // VSUBPDZ256rmbk 1167067881U, // VSUBPDZ256rmbkz 87083753U, // VSUBPDZ256rmk 890309353U, // VSUBPDZ256rmkz 811649769U, // VSUBPDZ256rr 87050985U, // VSUBPDZ256rrk 890276585U, // VSUBPDZ256rrkz 812731113U, // VSUBPDZrm 362957545U, // VSUBPDZrmb 1437584105U, // VSUBPDZrmbk 1169165033U, // VSUBPDZrmbkz 87132905U, // VSUBPDZrmk 890358505U, // VSUBPDZrmkz 811649769U, // VSUBPDZrr 812780265U, // VSUBPDZrrb 87182057U, // VSUBPDZrrbk 890407657U, // VSUBPDZrrbkz 87050985U, // VSUBPDZrrk 890276585U, // VSUBPDZrrkz 811731689U, // VSUBPDrm 811649769U, // VSUBPDrr 812622822U, // VSUBPSYrm 811656166U, // VSUBPSYrr 811738086U, // VSUBPSZ128rm 360883174U, // VSUBPSZ128rmb 1435689958U, // VSUBPSZ128rmbk 1167270886U, // VSUBPSZ128rmbkz 86991846U, // VSUBPSZ128rmk 890184678U, // VSUBPSZ128rmkz 811656166U, // VSUBPSZ128rr 87057382U, // VSUBPSZ128rrk 890282982U, // VSUBPSZ128rrkz 812622822U, // VSUBPSZ256rm 362980326U, // VSUBPSZ256rmb 1437787110U, // VSUBPSZ256rmbk 1169368038U, // VSUBPSZ256rmbkz 87090150U, // VSUBPSZ256rmk 890315750U, // VSUBPSZ256rmkz 811656166U, // VSUBPSZ256rr 87057382U, // VSUBPSZ256rrk 890282982U, // VSUBPSZ256rrkz 812737510U, // VSUBPSZrm 365077478U, // VSUBPSZrmb 1439884262U, // VSUBPSZrmbk 1171465190U, // VSUBPSZrmbkz 87139302U, // VSUBPSZrmk 890364902U, // VSUBPSZrmkz 811656166U, // VSUBPSZrr 812786662U, // VSUBPSZrrb 87188454U, // VSUBPSZrrbk 890414054U, // VSUBPSZrrbkz 87057382U, // VSUBPSZrrk 890282982U, // VSUBPSZrrkz 811738086U, // VSUBPSrm 811656166U, // VSUBPSrr 283266786U, // VSUBSDZrm 283266786U, // VSUBSDZrm_Int 1357893346U, // VSUBSDZrm_Intk 1089474274U, // VSUBSDZrm_Intkz 811650786U, // VSUBSDZrr 811650786U, // VSUBSDZrr_Int 87052002U, // VSUBSDZrr_Intk 890277602U, // VSUBSDZrr_Intkz 812781282U, // VSUBSDZrrb_Int 87183074U, // VSUBSDZrrb_Intk 890408674U, // VSUBSDZrrb_Intkz 283266786U, // VSUBSDrm 283266786U, // VSUBSDrm_Int 811650786U, // VSUBSDrr 811650786U, // VSUBSDrr_Int 283289565U, // VSUBSSZrm 283289565U, // VSUBSSZrm_Int 1358096349U, // VSUBSSZrm_Intk 1089677277U, // VSUBSSZrm_Intkz 811657181U, // VSUBSSZrr 811657181U, // VSUBSSZrr_Int 87058397U, // VSUBSSZrr_Intk 890283997U, // VSUBSSZrr_Intkz 812787677U, // VSUBSSZrrb_Int 87189469U, // VSUBSSZrrb_Intk 890415069U, // VSUBSSZrrb_Intkz 283289565U, // VSUBSSrm 283289565U, // VSUBSSrm_Int 811657181U, // VSUBSSrr 811657181U, // VSUBSSrr_Int 1346849U, // VTESTPDYrm 551832865U, // VTESTPDYrr 658721U, // VTESTPDrm 551832865U, // VTESTPDrr 1353322U, // VTESTPSYrm 551839338U, // VTESTPSYrr 665194U, // VTESTPSrm 551839338U, // VTESTPSrr 552177470U, // VUCOMISDZrm 552177470U, // VUCOMISDZrm_Int 551833406U, // VUCOMISDZrr 551833406U, // VUCOMISDZrr_Int 551843422U, // VUCOMISDZrrb 552177470U, // VUCOMISDrm 552177470U, // VUCOMISDrm_Int 551833406U, // VUCOMISDrr 551833406U, // VUCOMISDrr_Int 552200272U, // VUCOMISSZrm 552200272U, // VUCOMISSZrm_Int 551839824U, // VUCOMISSZrr 551839824U, // VUCOMISSZrr_Int 551843891U, // VUCOMISSZrrb 552200272U, // VUCOMISSrm 552200272U, // VUCOMISSrm_Int 551839824U, // VUCOMISSrr 551839824U, // VUCOMISSrr_Int 812616664U, // VUNPCKHPDYrm 811650008U, // VUNPCKHPDYrr 811731928U, // VUNPCKHPDZ128rm 358763480U, // VUNPCKHPDZ128rmb 1433390040U, // VUNPCKHPDZ128rmbk 1164970968U, // VUNPCKHPDZ128rmbkz 86985688U, // VUNPCKHPDZ128rmk 890178520U, // VUNPCKHPDZ128rmkz 811650008U, // VUNPCKHPDZ128rr 87051224U, // VUNPCKHPDZ128rrk 890276824U, // VUNPCKHPDZ128rrkz 812616664U, // VUNPCKHPDZ256rm 360860632U, // VUNPCKHPDZ256rmb 1435487192U, // VUNPCKHPDZ256rmbk 1167068120U, // VUNPCKHPDZ256rmbkz 87083992U, // VUNPCKHPDZ256rmk 890309592U, // VUNPCKHPDZ256rmkz 811650008U, // VUNPCKHPDZ256rr 87051224U, // VUNPCKHPDZ256rrk 890276824U, // VUNPCKHPDZ256rrkz 812731352U, // VUNPCKHPDZrm 362957784U, // VUNPCKHPDZrmb 1437584344U, // VUNPCKHPDZrmbk 1169165272U, // VUNPCKHPDZrmbkz 87133144U, // VUNPCKHPDZrmk 890358744U, // VUNPCKHPDZrmkz 811650008U, // VUNPCKHPDZrr 87051224U, // VUNPCKHPDZrrk 890276824U, // VUNPCKHPDZrrkz 811731928U, // VUNPCKHPDrm 811650008U, // VUNPCKHPDrr 812623084U, // VUNPCKHPSYrm 811656428U, // VUNPCKHPSYrr 811738348U, // VUNPCKHPSZ128rm 360883436U, // VUNPCKHPSZ128rmb 1435690220U, // VUNPCKHPSZ128rmbk 1167271148U, // VUNPCKHPSZ128rmbkz 86992108U, // VUNPCKHPSZ128rmk 890184940U, // VUNPCKHPSZ128rmkz 811656428U, // VUNPCKHPSZ128rr 87057644U, // VUNPCKHPSZ128rrk 890283244U, // VUNPCKHPSZ128rrkz 812623084U, // VUNPCKHPSZ256rm 362980588U, // VUNPCKHPSZ256rmb 1437787372U, // VUNPCKHPSZ256rmbk 1169368300U, // VUNPCKHPSZ256rmbkz 87090412U, // VUNPCKHPSZ256rmk 890316012U, // VUNPCKHPSZ256rmkz 811656428U, // VUNPCKHPSZ256rr 87057644U, // VUNPCKHPSZ256rrk 890283244U, // VUNPCKHPSZ256rrkz 812737772U, // VUNPCKHPSZrm 365077740U, // VUNPCKHPSZrmb 1439884524U, // VUNPCKHPSZrmbk 1171465452U, // VUNPCKHPSZrmbkz 87139564U, // VUNPCKHPSZrmk 890365164U, // VUNPCKHPSZrmkz 811656428U, // VUNPCKHPSZrr 87057644U, // VUNPCKHPSZrrk 890283244U, // VUNPCKHPSZrrkz 811738348U, // VUNPCKHPSrm 811656428U, // VUNPCKHPSrr 812616706U, // VUNPCKLPDYrm 811650050U, // VUNPCKLPDYrr 811731970U, // VUNPCKLPDZ128rm 358763522U, // VUNPCKLPDZ128rmb 1433390082U, // VUNPCKLPDZ128rmbk 1164971010U, // VUNPCKLPDZ128rmbkz 86985730U, // VUNPCKLPDZ128rmk 890178562U, // VUNPCKLPDZ128rmkz 811650050U, // VUNPCKLPDZ128rr 87051266U, // VUNPCKLPDZ128rrk 890276866U, // VUNPCKLPDZ128rrkz 812616706U, // VUNPCKLPDZ256rm 360860674U, // VUNPCKLPDZ256rmb 1435487234U, // VUNPCKLPDZ256rmbk 1167068162U, // VUNPCKLPDZ256rmbkz 87084034U, // VUNPCKLPDZ256rmk 890309634U, // VUNPCKLPDZ256rmkz 811650050U, // VUNPCKLPDZ256rr 87051266U, // VUNPCKLPDZ256rrk 890276866U, // VUNPCKLPDZ256rrkz 812731394U, // VUNPCKLPDZrm 362957826U, // VUNPCKLPDZrmb 1437584386U, // VUNPCKLPDZrmbk 1169165314U, // VUNPCKLPDZrmbkz 87133186U, // VUNPCKLPDZrmk 890358786U, // VUNPCKLPDZrmkz 811650050U, // VUNPCKLPDZrr 87051266U, // VUNPCKLPDZrrk 890276866U, // VUNPCKLPDZrrkz 811731970U, // VUNPCKLPDrm 811650050U, // VUNPCKLPDrr 812623146U, // VUNPCKLPSYrm 811656490U, // VUNPCKLPSYrr 811738410U, // VUNPCKLPSZ128rm 360883498U, // VUNPCKLPSZ128rmb 1435690282U, // VUNPCKLPSZ128rmbk 1167271210U, // VUNPCKLPSZ128rmbkz 86992170U, // VUNPCKLPSZ128rmk 890185002U, // VUNPCKLPSZ128rmkz 811656490U, // VUNPCKLPSZ128rr 87057706U, // VUNPCKLPSZ128rrk 890283306U, // VUNPCKLPSZ128rrkz 812623146U, // VUNPCKLPSZ256rm 362980650U, // VUNPCKLPSZ256rmb 1437787434U, // VUNPCKLPSZ256rmbk 1169368362U, // VUNPCKLPSZ256rmbkz 87090474U, // VUNPCKLPSZ256rmk 890316074U, // VUNPCKLPSZ256rmkz 811656490U, // VUNPCKLPSZ256rr 87057706U, // VUNPCKLPSZ256rrk 890283306U, // VUNPCKLPSZ256rrkz 812737834U, // VUNPCKLPSZrm 365077802U, // VUNPCKLPSZrmb 1439884586U, // VUNPCKLPSZrmbk 1171465514U, // VUNPCKLPSZrmbkz 87139626U, // VUNPCKLPSZrmk 890365226U, // VUNPCKLPSZrmkz 811656490U, // VUNPCKLPSZrr 87057706U, // VUNPCKLPSZrrk 890283306U, // VUNPCKLPSZrrkz 811738410U, // VUNPCKLPSrm 811656490U, // VUNPCKLPSrr 812616912U, // VXORPDYrm 811650256U, // VXORPDYrr 811732176U, // VXORPDZ128rm 358763728U, // VXORPDZ128rmb 1433390288U, // VXORPDZ128rmbk 1164971216U, // VXORPDZ128rmbkz 86985936U, // VXORPDZ128rmk 890178768U, // VXORPDZ128rmkz 811650256U, // VXORPDZ128rr 87051472U, // VXORPDZ128rrk 890277072U, // VXORPDZ128rrkz 812616912U, // VXORPDZ256rm 360860880U, // VXORPDZ256rmb 1435487440U, // VXORPDZ256rmbk 1167068368U, // VXORPDZ256rmbkz 87084240U, // VXORPDZ256rmk 890309840U, // VXORPDZ256rmkz 811650256U, // VXORPDZ256rr 87051472U, // VXORPDZ256rrk 890277072U, // VXORPDZ256rrkz 812731600U, // VXORPDZrm 362958032U, // VXORPDZrmb 1437584592U, // VXORPDZrmbk 1169165520U, // VXORPDZrmbkz 87133392U, // VXORPDZrmk 890358992U, // VXORPDZrmkz 811650256U, // VXORPDZrr 87051472U, // VXORPDZrrk 890277072U, // VXORPDZrrkz 811732176U, // VXORPDrm 811650256U, // VXORPDrr 812623369U, // VXORPSYrm 811656713U, // VXORPSYrr 811738633U, // VXORPSZ128rm 360883721U, // VXORPSZ128rmb 1435690505U, // VXORPSZ128rmbk 1167271433U, // VXORPSZ128rmbkz 86992393U, // VXORPSZ128rmk 890185225U, // VXORPSZ128rmkz 811656713U, // VXORPSZ128rr 87057929U, // VXORPSZ128rrk 890283529U, // VXORPSZ128rrkz 812623369U, // VXORPSZ256rm 362980873U, // VXORPSZ256rmb 1437787657U, // VXORPSZ256rmbk 1169368585U, // VXORPSZ256rmbkz 87090697U, // VXORPSZ256rmk 890316297U, // VXORPSZ256rmkz 811656713U, // VXORPSZ256rr 87057929U, // VXORPSZ256rrk 890283529U, // VXORPSZ256rrkz 812738057U, // VXORPSZrm 365078025U, // VXORPSZrmb 1439884809U, // VXORPSZrmbk 1171465737U, // VXORPSZrmbkz 87139849U, // VXORPSZrmk 890365449U, // VXORPSZrmkz 811656713U, // VXORPSZrr 87057929U, // VXORPSZrrk 890283529U, // VXORPSZrrkz 811738633U, // VXORPSrm 811656713U, // VXORPSrr 15238U, // VZEROALL 15496U, // VZEROUPPER 15865U, // WAIT 14996U, // WBINVD 15003U, // WBNOINVD 21627U, // WRFSBASE 23544U, // WRFSBASE64 21649U, // WRGSBASE 23566U, // WRGSBASE64 15530U, // WRMSR 15919U, // WRPKRUr 12619671U, // WRSSD 18915114U, // WRSSQ 12619690U, // WRUSSD 18915121U, // WRUSSQ 26977U, // XABORT 15062U, // XACQUIRE_PREFIX 1088711480U, // XADD16rm 84978488U, // XADD16rr 14963702U, // XADD32rm 84972534U, // XADD32rr 551836255U, // XADD64rm 84974175U, // XADD64rr 1357136882U, // XADD8rm 84968434U, // XADD8rr 464986U, // XBEGIN_2 464986U, // XBEGIN_4 292063U, // XCHG16ar 1088711686U, // XCHG16rm 178318342U, // XCHG16rr 292123U, // XCHG32ar 14963911U, // XCHG32rm 178312391U, // XCHG32rr 292188U, // XCHG64ar 551836740U, // XCHG64rm 178314308U, // XCHG64rr 1357136955U, // XCHG8rm 178308155U, // XCHG8rr 21080U, // XCH_F 14914U, // XCRYPTCBC 14878U, // XCRYPTCFB 15536U, // XCRYPTCTR 14868U, // XCRYPTECB 14888U, // XCRYPTOFB 14977U, // XEND 15926U, // XGETBV 14898U, // XLAT 2125212U, // XOR16i16 4238748U, // XOR16mi 4238748U, // XOR16mi8 4238748U, // XOR16mr 6352284U, // XOR16ri 6352284U, // XOR16ri8 6368668U, // XOR16rm 6352284U, // XOR16rr 8449436U, // XOR16rr_REV 10507871U, // XOR32i32 12621407U, // XOR32mi 12621407U, // XOR32mi8 12621407U, // XOR32mr 6346335U, // XOR32ri 6346335U, // XOR32ri8 283203167U, // XOR32rm 6346335U, // XOR32rr 8443487U, // XOR32rr_REV 16801390U, // XOR64i32 18914926U, // XOR64mi32 18914926U, // XOR64mi8 18914926U, // XOR64mr 6348398U, // XOR64ri32 6348398U, // XOR64ri8 283221614U, // XOR64rm 6348398U, // XOR64rr 8445550U, // XOR64rr_REV 20989303U, // XOR8i8 23102839U, // XOR8mi 23102839U, // XOR8mi8 23102839U, // XOR8mr 6342007U, // XOR8ri 6342007U, // XOR8ri8 6407543U, // XOR8rm 6342007U, // XOR8rr 8439159U, // XOR8rr_REV 8522961U, // XORPDrm 8441041U, // XORPDrr 8529418U, // XORPSrm 8447498U, // XORPSrr 15078U, // XRELEASE_PREFIX 680256U, // XRSTOR 672072U, // XRSTOR64 681685U, // XRSTORS 672092U, // XRSTORS64 676397U, // XSAVE 672062U, // XSAVE64 673547U, // XSAVEC 672051U, // XSAVEC64 682308U, // XSAVEOPT 672103U, // XSAVEOPT64 680381U, // XSAVES 672082U, // XSAVES64 15933U, // XSETBV 14704U, // XSHA1 14797U, // XSHA256 15071U, // XSTORE 15895U, // XTEST }; static const uint16_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // AVX1_SETALLONES 0U, // AVX2_SETALLONES 0U, // AVX512_128_SET0 0U, // AVX512_256_SET0 0U, // AVX512_512_SET0 0U, // AVX512_512_SETALLONES 0U, // AVX512_512_SEXT_MASK_32 0U, // AVX512_512_SEXT_MASK_64 0U, // AVX512_FsFLD0SD 0U, // AVX512_FsFLD0SS 0U, // AVX_SET0 0U, // KSET0D 0U, // KSET0Q 0U, // KSET0W 0U, // KSET1D 0U, // KSET1Q 0U, // KSET1W 0U, // MMX_SET0 0U, // V_SET0 0U, // V_SETALLONES 0U, // AAA 0U, // AAD8i8 0U, // AAM8i8 0U, // AAS 0U, // ABS_F 0U, // ABS_Fp32 0U, // ABS_Fp64 0U, // ABS_Fp80 0U, // ADC16i16 0U, // ADC16mi 0U, // ADC16mi8 0U, // ADC16mr 0U, // ADC16ri 0U, // ADC16ri8 0U, // ADC16rm 0U, // ADC16rr 0U, // ADC16rr_REV 0U, // ADC32i32 0U, // ADC32mi 0U, // ADC32mi8 0U, // ADC32mr 0U, // ADC32ri 0U, // ADC32ri8 0U, // ADC32rm 0U, // ADC32rr 0U, // ADC32rr_REV 0U, // ADC64i32 0U, // ADC64mi32 0U, // ADC64mi8 0U, // ADC64mr 0U, // ADC64ri32 0U, // ADC64ri8 0U, // ADC64rm 0U, // ADC64rr 0U, // ADC64rr_REV 0U, // ADC8i8 0U, // ADC8mi 0U, // ADC8mi8 0U, // ADC8mr 0U, // ADC8ri 0U, // ADC8ri8 0U, // ADC8rm 0U, // ADC8rr 0U, // ADC8rr_REV 0U, // ADCX32rm 0U, // ADCX32rr 0U, // ADCX64rm 0U, // ADCX64rr 0U, // ADD16i16 0U, // ADD16mi 0U, // ADD16mi8 0U, // ADD16mr 0U, // ADD16ri 0U, // ADD16ri8 0U, // ADD16rm 0U, // ADD16rr 0U, // ADD16rr_REV 0U, // ADD32i32 0U, // ADD32mi 0U, // ADD32mi8 0U, // ADD32mr 0U, // ADD32ri 0U, // ADD32ri8 0U, // ADD32rm 0U, // ADD32rr 0U, // ADD32rr_REV 0U, // ADD64i32 0U, // ADD64mi32 0U, // ADD64mi8 0U, // ADD64mr 0U, // ADD64ri32 0U, // ADD64ri8 0U, // ADD64rm 0U, // ADD64rr 0U, // ADD64rr_REV 0U, // ADD8i8 0U, // ADD8mi 0U, // ADD8mi8 0U, // ADD8mr 0U, // ADD8ri 0U, // ADD8ri8 0U, // ADD8rm 0U, // ADD8rr 0U, // ADD8rr_REV 0U, // ADDPDrm 0U, // ADDPDrr 0U, // ADDPSrm 0U, // ADDPSrr 0U, // ADDSDrm 0U, // ADDSDrm_Int 0U, // ADDSDrr 0U, // ADDSDrr_Int 0U, // ADDSSrm 0U, // ADDSSrm_Int 0U, // ADDSSrr 0U, // ADDSSrr_Int 0U, // ADDSUBPDrm 0U, // ADDSUBPDrr 0U, // ADDSUBPSrm 0U, // ADDSUBPSrr 0U, // ADD_F32m 0U, // ADD_F64m 0U, // ADD_FI16m 0U, // ADD_FI32m 0U, // ADD_FPrST0 0U, // ADD_FST0r 0U, // ADD_Fp32 0U, // ADD_Fp32m 0U, // ADD_Fp64 0U, // ADD_Fp64m 0U, // ADD_Fp64m32 0U, // ADD_Fp80 0U, // ADD_Fp80m32 0U, // ADD_Fp80m64 0U, // ADD_FpI16m32 0U, // ADD_FpI16m64 0U, // ADD_FpI16m80 0U, // ADD_FpI32m32 0U, // ADD_FpI32m64 0U, // ADD_FpI32m80 0U, // ADD_FrST0 0U, // ADOX32rm 0U, // ADOX32rr 0U, // ADOX64rm 0U, // ADOX64rr 0U, // AESDECLASTrm 0U, // AESDECLASTrr 0U, // AESDECrm 0U, // AESDECrr 0U, // AESENCLASTrm 0U, // AESENCLASTrr 0U, // AESENCrm 0U, // AESENCrr 0U, // AESIMCrm 0U, // AESIMCrr 4U, // AESKEYGENASSIST128rm 72U, // AESKEYGENASSIST128rr 0U, // AND16i16 0U, // AND16mi 0U, // AND16mi8 0U, // AND16mr 0U, // AND16ri 0U, // AND16ri8 0U, // AND16rm 0U, // AND16rr 0U, // AND16rr_REV 0U, // AND32i32 0U, // AND32mi 0U, // AND32mi8 0U, // AND32mr 0U, // AND32ri 0U, // AND32ri8 0U, // AND32rm 0U, // AND32rr 0U, // AND32rr_REV 0U, // AND64i32 0U, // AND64mi32 0U, // AND64mi8 0U, // AND64mr 0U, // AND64ri32 0U, // AND64ri8 0U, // AND64rm 0U, // AND64rr 0U, // AND64rr_REV 0U, // AND8i8 0U, // AND8mi 0U, // AND8mi8 0U, // AND8mr 0U, // AND8ri 0U, // AND8ri8 0U, // AND8rm 0U, // AND8rr 0U, // AND8rr_REV 72U, // ANDN32rm 4U, // ANDN32rr 72U, // ANDN64rm 4U, // ANDN64rr 0U, // ANDNPDrm 0U, // ANDNPDrr 0U, // ANDNPSrm 0U, // ANDNPSrr 0U, // ANDPDrm 0U, // ANDPDrr 0U, // ANDPSrm 0U, // ANDPSrr 0U, // ARPL16mr 0U, // ARPL16rr 4U, // BEXTR32rm 4U, // BEXTR32rr 4U, // BEXTR64rm 4U, // BEXTR64rr 4U, // BEXTRI32mi 4U, // BEXTRI32ri 4U, // BEXTRI64mi 4U, // BEXTRI64ri 0U, // BLCFILL32rm 0U, // BLCFILL32rr 0U, // BLCFILL64rm 0U, // BLCFILL64rr 0U, // BLCI32rm 0U, // BLCI32rr 0U, // BLCI64rm 0U, // BLCI64rr 0U, // BLCIC32rm 0U, // BLCIC32rr 0U, // BLCIC64rm 0U, // BLCIC64rr 0U, // BLCMSK32rm 0U, // BLCMSK32rr 0U, // BLCMSK64rm 0U, // BLCMSK64rr 0U, // BLCS32rm 0U, // BLCS32rr 0U, // BLCS64rm 0U, // BLCS64rr 0U, // BLENDPDrmi 4U, // BLENDPDrri 0U, // BLENDPSrmi 4U, // BLENDPSrri 0U, // BLENDVPDrm0 0U, // BLENDVPDrr0 0U, // BLENDVPSrm0 0U, // BLENDVPSrr0 0U, // BLSFILL32rm 0U, // BLSFILL32rr 0U, // BLSFILL64rm 0U, // BLSFILL64rr 0U, // BLSI32rm 0U, // BLSI32rr 0U, // BLSI64rm 0U, // BLSI64rr 0U, // BLSIC32rm 0U, // BLSIC32rr 0U, // BLSIC64rm 0U, // BLSIC64rr 0U, // BLSMSK32rm 0U, // BLSMSK32rr 0U, // BLSMSK64rm 0U, // BLSMSK64rr 0U, // BLSR32rm 0U, // BLSR32rr 0U, // BLSR64rm 0U, // BLSR64rr 0U, // BNDCL32rm 0U, // BNDCL32rr 0U, // BNDCL64rm 0U, // BNDCL64rr 0U, // BNDCN32rm 0U, // BNDCN32rr 0U, // BNDCN64rm 0U, // BNDCN64rr 0U, // BNDCU32rm 0U, // BNDCU32rr 0U, // BNDCU64rm 0U, // BNDCU64rr 0U, // BNDLDXrm 0U, // BNDMK32rm 0U, // BNDMK64rm 0U, // BNDMOV32mr 0U, // BNDMOV32rm 0U, // BNDMOV64mr 0U, // BNDMOV64rm 0U, // BNDMOVrr 0U, // BNDMOVrr_REV 0U, // BNDSTXmr 0U, // BOUNDS16rm 0U, // BOUNDS32rm 0U, // BSF16rm 0U, // BSF16rr 0U, // BSF32rm 0U, // BSF32rr 0U, // BSF64rm 0U, // BSF64rr 0U, // BSR16rm 0U, // BSR16rr 0U, // BSR32rm 0U, // BSR32rr 0U, // BSR64rm 0U, // BSR64rr 0U, // BSWAP16r_BAD 0U, // BSWAP32r 0U, // BSWAP64r 0U, // BT16mi8 0U, // BT16mr 0U, // BT16ri8 0U, // BT16rr 0U, // BT32mi8 0U, // BT32mr 0U, // BT32ri8 0U, // BT32rr 0U, // BT64mi8 0U, // BT64mr 0U, // BT64ri8 0U, // BT64rr 0U, // BTC16mi8 0U, // BTC16mr 0U, // BTC16ri8 0U, // BTC16rr 0U, // BTC32mi8 0U, // BTC32mr 0U, // BTC32ri8 0U, // BTC32rr 0U, // BTC64mi8 0U, // BTC64mr 0U, // BTC64ri8 0U, // BTC64rr 0U, // BTR16mi8 0U, // BTR16mr 0U, // BTR16ri8 0U, // BTR16rr 0U, // BTR32mi8 0U, // BTR32mr 0U, // BTR32ri8 0U, // BTR32rr 0U, // BTR64mi8 0U, // BTR64mr 0U, // BTR64ri8 0U, // BTR64rr 0U, // BTS16mi8 0U, // BTS16mr 0U, // BTS16ri8 0U, // BTS16rr 0U, // BTS32mi8 0U, // BTS32mr 0U, // BTS32ri8 0U, // BTS32rr 0U, // BTS64mi8 0U, // BTS64mr 0U, // BTS64ri8 0U, // BTS64rr 4U, // BZHI32rm 4U, // BZHI32rr 4U, // BZHI64rm 4U, // BZHI64rr 0U, // CALL16m 0U, // CALL16m_NT 0U, // CALL16r 0U, // CALL16r_NT 0U, // CALL32m 0U, // CALL32m_NT 0U, // CALL32r 0U, // CALL32r_NT 0U, // CALL64m 0U, // CALL64m_NT 0U, // CALL64pcrel32 0U, // CALL64r 0U, // CALL64r_NT 0U, // CALLpcrel16 0U, // CALLpcrel32 0U, // CBW 0U, // CDQ 0U, // CDQE 0U, // CHS_F 0U, // CHS_Fp32 0U, // CHS_Fp64 0U, // CHS_Fp80 0U, // CLAC 0U, // CLC 0U, // CLD 0U, // CLDEMOTE 0U, // CLFLUSH 0U, // CLFLUSHOPT 0U, // CLGI 0U, // CLI 0U, // CLRSSBSY 0U, // CLTS 0U, // CLWB 0U, // CLZEROr 0U, // CMC 0U, // CMOVA16rm 0U, // CMOVA16rr 0U, // CMOVA32rm 0U, // CMOVA32rr 0U, // CMOVA64rm 0U, // CMOVA64rr 0U, // CMOVAE16rm 0U, // CMOVAE16rr 0U, // CMOVAE32rm 0U, // CMOVAE32rr 0U, // CMOVAE64rm 0U, // CMOVAE64rr 0U, // CMOVB16rm 0U, // CMOVB16rr 0U, // CMOVB32rm 0U, // CMOVB32rr 0U, // CMOVB64rm 0U, // CMOVB64rr 0U, // CMOVBE16rm 0U, // CMOVBE16rr 0U, // CMOVBE32rm 0U, // CMOVBE32rr 0U, // CMOVBE64rm 0U, // CMOVBE64rr 0U, // CMOVBE_F 0U, // CMOVBE_Fp32 0U, // CMOVBE_Fp64 0U, // CMOVBE_Fp80 0U, // CMOVB_F 0U, // CMOVB_Fp32 0U, // CMOVB_Fp64 0U, // CMOVB_Fp80 0U, // CMOVE16rm 0U, // CMOVE16rr 0U, // CMOVE32rm 0U, // CMOVE32rr 0U, // CMOVE64rm 0U, // CMOVE64rr 0U, // CMOVE_F 0U, // CMOVE_Fp32 0U, // CMOVE_Fp64 0U, // CMOVE_Fp80 0U, // CMOVG16rm 0U, // CMOVG16rr 0U, // CMOVG32rm 0U, // CMOVG32rr 0U, // CMOVG64rm 0U, // CMOVG64rr 0U, // CMOVGE16rm 0U, // CMOVGE16rr 0U, // CMOVGE32rm 0U, // CMOVGE32rr 0U, // CMOVGE64rm 0U, // CMOVGE64rr 0U, // CMOVL16rm 0U, // CMOVL16rr 0U, // CMOVL32rm 0U, // CMOVL32rr 0U, // CMOVL64rm 0U, // CMOVL64rr 0U, // CMOVLE16rm 0U, // CMOVLE16rr 0U, // CMOVLE32rm 0U, // CMOVLE32rr 0U, // CMOVLE64rm 0U, // CMOVLE64rr 0U, // CMOVNBE_F 0U, // CMOVNBE_Fp32 0U, // CMOVNBE_Fp64 0U, // CMOVNBE_Fp80 0U, // CMOVNB_F 0U, // CMOVNB_Fp32 0U, // CMOVNB_Fp64 0U, // CMOVNB_Fp80 0U, // CMOVNE16rm 0U, // CMOVNE16rr 0U, // CMOVNE32rm 0U, // CMOVNE32rr 0U, // CMOVNE64rm 0U, // CMOVNE64rr 0U, // CMOVNE_F 0U, // CMOVNE_Fp32 0U, // CMOVNE_Fp64 0U, // CMOVNE_Fp80 0U, // CMOVNO16rm 0U, // CMOVNO16rr 0U, // CMOVNO32rm 0U, // CMOVNO32rr 0U, // CMOVNO64rm 0U, // CMOVNO64rr 0U, // CMOVNP16rm 0U, // CMOVNP16rr 0U, // CMOVNP32rm 0U, // CMOVNP32rr 0U, // CMOVNP64rm 0U, // CMOVNP64rr 0U, // CMOVNP_F 0U, // CMOVNP_Fp32 0U, // CMOVNP_Fp64 0U, // CMOVNP_Fp80 0U, // CMOVNS16rm 0U, // CMOVNS16rr 0U, // CMOVNS32rm 0U, // CMOVNS32rr 0U, // CMOVNS64rm 0U, // CMOVNS64rr 0U, // CMOVO16rm 0U, // CMOVO16rr 0U, // CMOVO32rm 0U, // CMOVO32rr 0U, // CMOVO64rm 0U, // CMOVO64rr 0U, // CMOVP16rm 0U, // CMOVP16rr 0U, // CMOVP32rm 0U, // CMOVP32rr 0U, // CMOVP64rm 0U, // CMOVP64rr 0U, // CMOVP_F 0U, // CMOVP_Fp32 0U, // CMOVP_Fp64 0U, // CMOVP_Fp80 0U, // CMOVS16rm 0U, // CMOVS16rr 0U, // CMOVS32rm 0U, // CMOVS32rr 0U, // CMOVS64rm 0U, // CMOVS64rr 0U, // CMP16i16 0U, // CMP16mi 0U, // CMP16mi8 0U, // CMP16mr 0U, // CMP16ri 0U, // CMP16ri8 0U, // CMP16rm 0U, // CMP16rr 0U, // CMP16rr_REV 0U, // CMP32i32 0U, // CMP32mi 0U, // CMP32mi8 0U, // CMP32mr 0U, // CMP32ri 0U, // CMP32ri8 0U, // CMP32rm 0U, // CMP32rr 0U, // CMP32rr_REV 0U, // CMP64i32 0U, // CMP64mi32 0U, // CMP64mi8 0U, // CMP64mr 0U, // CMP64ri32 0U, // CMP64ri8 0U, // CMP64rm 0U, // CMP64rr 0U, // CMP64rr_REV 0U, // CMP8i8 0U, // CMP8mi 0U, // CMP8mi8 0U, // CMP8mr 0U, // CMP8ri 0U, // CMP8ri8 0U, // CMP8rm 0U, // CMP8rr 0U, // CMP8rr_REV 4U, // CMPPDrmi 0U, // CMPPDrmi_alt 4U, // CMPPDrri 4U, // CMPPDrri_alt 4U, // CMPPSrmi 0U, // CMPPSrmi_alt 4U, // CMPPSrri 4U, // CMPPSrri_alt 0U, // CMPSB 72U, // CMPSDrm 72U, // CMPSDrm_Int 4U, // CMPSDrm_alt 4U, // CMPSDrr 4U, // CMPSDrr_Int 4U, // CMPSDrr_alt 0U, // CMPSL 0U, // CMPSQ 72U, // CMPSSrm 72U, // CMPSSrm_Int 4U, // CMPSSrm_alt 4U, // CMPSSrr 4U, // CMPSSrr_Int 4U, // CMPSSrr_alt 0U, // CMPSW 0U, // CMPXCHG16B 0U, // CMPXCHG16rm 0U, // CMPXCHG16rr 0U, // CMPXCHG32rm 0U, // CMPXCHG32rr 0U, // CMPXCHG64rm 0U, // CMPXCHG64rr 0U, // CMPXCHG8B 0U, // CMPXCHG8rm 0U, // CMPXCHG8rr 0U, // COMISDrm 0U, // COMISDrm_Int 0U, // COMISDrr 0U, // COMISDrr_Int 0U, // COMISSrm 0U, // COMISSrm_Int 0U, // COMISSrr 0U, // COMISSrr_Int 0U, // COMP_FST0r 0U, // COM_FIPr 0U, // COM_FIr 0U, // COM_FST0r 0U, // COS_F 0U, // COS_Fp32 0U, // COS_Fp64 0U, // COS_Fp80 0U, // CPUID 0U, // CQO 0U, // CRC32r32m16 0U, // CRC32r32m32 0U, // CRC32r32m8 0U, // CRC32r32r16 0U, // CRC32r32r32 0U, // CRC32r32r8 0U, // CRC32r64m64 0U, // CRC32r64m8 0U, // CRC32r64r64 0U, // CRC32r64r8 0U, // CVTDQ2PDrm 0U, // CVTDQ2PDrr 0U, // CVTDQ2PSrm 0U, // CVTDQ2PSrr 0U, // CVTPD2DQrm 0U, // CVTPD2DQrr 0U, // CVTPD2PSrm 0U, // CVTPD2PSrr 0U, // CVTPS2DQrm 0U, // CVTPS2DQrr 0U, // CVTPS2PDrm 0U, // CVTPS2PDrr 0U, // CVTSD2SI64rm_Int 0U, // CVTSD2SI64rr_Int 0U, // CVTSD2SIrm_Int 0U, // CVTSD2SIrr_Int 0U, // CVTSD2SSrm 0U, // CVTSD2SSrm_Int 0U, // CVTSD2SSrr 0U, // CVTSD2SSrr_Int 0U, // CVTSI2SDrm 0U, // CVTSI2SDrm_Int 0U, // CVTSI2SDrr 0U, // CVTSI2SDrr_Int 0U, // CVTSI2SSrm 0U, // CVTSI2SSrm_Int 0U, // CVTSI2SSrr 0U, // CVTSI2SSrr_Int 0U, // CVTSI642SDrm 0U, // CVTSI642SDrm_Int 0U, // CVTSI642SDrr 0U, // CVTSI642SDrr_Int 0U, // CVTSI642SSrm 0U, // CVTSI642SSrm_Int 0U, // CVTSI642SSrr 0U, // CVTSI642SSrr_Int 0U, // CVTSS2SDrm 0U, // CVTSS2SDrm_Int 0U, // CVTSS2SDrr 0U, // CVTSS2SDrr_Int 0U, // CVTSS2SI64rm_Int 0U, // CVTSS2SI64rr_Int 0U, // CVTSS2SIrm_Int 0U, // CVTSS2SIrr_Int 0U, // CVTTPD2DQrm 0U, // CVTTPD2DQrr 0U, // CVTTPS2DQrm 0U, // CVTTPS2DQrr 0U, // CVTTSD2SI64rm 0U, // CVTTSD2SI64rm_Int 0U, // CVTTSD2SI64rr 0U, // CVTTSD2SI64rr_Int 0U, // CVTTSD2SIrm 0U, // CVTTSD2SIrm_Int 0U, // CVTTSD2SIrr 0U, // CVTTSD2SIrr_Int 0U, // CVTTSS2SI64rm 0U, // CVTTSS2SI64rm_Int 0U, // CVTTSS2SI64rr 0U, // CVTTSS2SI64rr_Int 0U, // CVTTSS2SIrm 0U, // CVTTSS2SIrm_Int 0U, // CVTTSS2SIrr 0U, // CVTTSS2SIrr_Int 0U, // CWD 0U, // CWDE 0U, // DAA 0U, // DAS 0U, // DATA16_PREFIX 0U, // DEC16m 0U, // DEC16r 0U, // DEC16r_alt 0U, // DEC32m 0U, // DEC32r 0U, // DEC32r_alt 0U, // DEC64m 0U, // DEC64r 0U, // DEC8m 0U, // DEC8r 0U, // DIV16m 0U, // DIV16r 0U, // DIV32m 0U, // DIV32r 0U, // DIV64m 0U, // DIV64r 0U, // DIV8m 0U, // DIV8r 0U, // DIVPDrm 0U, // DIVPDrr 0U, // DIVPSrm 0U, // DIVPSrr 0U, // DIVR_F32m 0U, // DIVR_F64m 0U, // DIVR_FI16m 0U, // DIVR_FI32m 0U, // DIVR_FPrST0 0U, // DIVR_FST0r 0U, // DIVR_Fp32m 0U, // DIVR_Fp64m 0U, // DIVR_Fp64m32 0U, // DIVR_Fp80m32 0U, // DIVR_Fp80m64 0U, // DIVR_FpI16m32 0U, // DIVR_FpI16m64 0U, // DIVR_FpI16m80 0U, // DIVR_FpI32m32 0U, // DIVR_FpI32m64 0U, // DIVR_FpI32m80 0U, // DIVR_FrST0 0U, // DIVSDrm 0U, // DIVSDrm_Int 0U, // DIVSDrr 0U, // DIVSDrr_Int 0U, // DIVSSrm 0U, // DIVSSrm_Int 0U, // DIVSSrr 0U, // DIVSSrr_Int 0U, // DIV_F32m 0U, // DIV_F64m 0U, // DIV_FI16m 0U, // DIV_FI32m 0U, // DIV_FPrST0 0U, // DIV_FST0r 0U, // DIV_Fp32 0U, // DIV_Fp32m 0U, // DIV_Fp64 0U, // DIV_Fp64m 0U, // DIV_Fp64m32 0U, // DIV_Fp80 0U, // DIV_Fp80m32 0U, // DIV_Fp80m64 0U, // DIV_FpI16m32 0U, // DIV_FpI16m64 0U, // DIV_FpI16m80 0U, // DIV_FpI32m32 0U, // DIV_FpI32m64 0U, // DIV_FpI32m80 0U, // DIV_FrST0 0U, // DPPDrmi 4U, // DPPDrri 0U, // DPPSrmi 4U, // DPPSrri 0U, // ENCLS 0U, // ENCLU 0U, // ENCLV 0U, // ENDBR32 0U, // ENDBR64 0U, // ENTER 0U, // EXTRACTPSmr 72U, // EXTRACTPSrr 0U, // EXTRQ 0U, // EXTRQI 0U, // F2XM1 0U, // FARCALL16i 0U, // FARCALL16m 0U, // FARCALL32i 0U, // FARCALL32m 0U, // FARCALL64 0U, // FARJMP16i 0U, // FARJMP16m 0U, // FARJMP32i 0U, // FARJMP32m 0U, // FARJMP64 0U, // FBLDm 0U, // FBSTPm 0U, // FCOM32m 0U, // FCOM64m 0U, // FCOMP32m 0U, // FCOMP64m 0U, // FCOMPP 0U, // FDECSTP 0U, // FDISI8087_NOP 0U, // FEMMS 0U, // FENI8087_NOP 0U, // FFREE 0U, // FFREEP 0U, // FICOM16m 0U, // FICOM32m 0U, // FICOMP16m 0U, // FICOMP32m 0U, // FINCSTP 0U, // FLDCW16m 0U, // FLDENVm 0U, // FLDL2E 0U, // FLDL2T 0U, // FLDLG2 0U, // FLDLN2 0U, // FLDPI 0U, // FNCLEX 0U, // FNINIT 0U, // FNOP 0U, // FNSTCW16m 0U, // FNSTSW16r 0U, // FNSTSWm 0U, // FPATAN 0U, // FPNCEST0r 0U, // FPREM 0U, // FPREM1 0U, // FPTAN 0U, // FRNDINT 0U, // FRSTORm 0U, // FSAVEm 0U, // FSCALE 0U, // FSETPM 0U, // FSINCOS 0U, // FSTENVm 0U, // FXAM 0U, // FXRSTOR 0U, // FXRSTOR64 0U, // FXSAVE 0U, // FXSAVE64 0U, // FXTRACT 0U, // FYL2X 0U, // FYL2XP1 0U, // GETSEC 0U, // GF2P8AFFINEINVQBrmi 4U, // GF2P8AFFINEINVQBrri 0U, // GF2P8AFFINEQBrmi 4U, // GF2P8AFFINEQBrri 0U, // GF2P8MULBrm 0U, // GF2P8MULBrr 0U, // HADDPDrm 0U, // HADDPDrr 0U, // HADDPSrm 0U, // HADDPSrr 0U, // HLT 0U, // HSUBPDrm 0U, // HSUBPDrr 0U, // HSUBPSrm 0U, // HSUBPSrr 0U, // IDIV16m 0U, // IDIV16r 0U, // IDIV32m 0U, // IDIV32r 0U, // IDIV64m 0U, // IDIV64r 0U, // IDIV8m 0U, // IDIV8r 0U, // ILD_F16m 0U, // ILD_F32m 0U, // ILD_F64m 0U, // ILD_Fp16m32 0U, // ILD_Fp16m64 0U, // ILD_Fp16m80 0U, // ILD_Fp32m32 0U, // ILD_Fp32m64 0U, // ILD_Fp32m80 0U, // ILD_Fp64m32 0U, // ILD_Fp64m64 0U, // ILD_Fp64m80 0U, // IMUL16m 0U, // IMUL16r 0U, // IMUL16rm 0U, // IMUL16rmi 0U, // IMUL16rmi8 0U, // IMUL16rr 4U, // IMUL16rri 4U, // IMUL16rri8 0U, // IMUL32m 0U, // IMUL32r 0U, // IMUL32rm 4U, // IMUL32rmi 4U, // IMUL32rmi8 0U, // IMUL32rr 4U, // IMUL32rri 4U, // IMUL32rri8 0U, // IMUL64m 0U, // IMUL64r 0U, // IMUL64rm 4U, // IMUL64rmi32 4U, // IMUL64rmi8 0U, // IMUL64rr 4U, // IMUL64rri32 4U, // IMUL64rri8 0U, // IMUL8m 0U, // IMUL8r 0U, // IN16ri 0U, // IN16rr 0U, // IN32ri 0U, // IN32rr 0U, // IN8ri 0U, // IN8rr 0U, // INC16m 0U, // INC16r 0U, // INC16r_alt 0U, // INC32m 0U, // INC32r 0U, // INC32r_alt 0U, // INC64m 0U, // INC64r 0U, // INC8m 0U, // INC8r 0U, // INCSSPD 0U, // INCSSPQ 0U, // INSB 4U, // INSERTPSrm 4U, // INSERTPSrr 0U, // INSERTQ 1U, // INSERTQI 0U, // INSL 0U, // INSW 0U, // INT 0U, // INT1 0U, // INT3 0U, // INTO 0U, // INVD 0U, // INVEPT32 0U, // INVEPT64 0U, // INVLPG 0U, // INVLPGA32 0U, // INVLPGA64 0U, // INVPCID32 0U, // INVPCID64 0U, // INVVPID32 0U, // INVVPID64 0U, // IRET16 0U, // IRET32 0U, // IRET64 0U, // ISTT_FP16m 0U, // ISTT_FP32m 0U, // ISTT_FP64m 0U, // ISTT_Fp16m32 0U, // ISTT_Fp16m64 0U, // ISTT_Fp16m80 0U, // ISTT_Fp32m32 0U, // ISTT_Fp32m64 0U, // ISTT_Fp32m80 0U, // ISTT_Fp64m32 0U, // ISTT_Fp64m64 0U, // ISTT_Fp64m80 0U, // IST_F16m 0U, // IST_F32m 0U, // IST_FP16m 0U, // IST_FP32m 0U, // IST_FP64m 0U, // IST_Fp16m32 0U, // IST_Fp16m64 0U, // IST_Fp16m80 0U, // IST_Fp32m32 0U, // IST_Fp32m64 0U, // IST_Fp32m80 0U, // IST_Fp64m32 0U, // IST_Fp64m64 0U, // IST_Fp64m80 0U, // JAE_1 0U, // JAE_2 0U, // JAE_4 0U, // JA_1 0U, // JA_2 0U, // JA_4 0U, // JBE_1 0U, // JBE_2 0U, // JBE_4 0U, // JB_1 0U, // JB_2 0U, // JB_4 0U, // JCXZ 0U, // JECXZ 0U, // JE_1 0U, // JE_2 0U, // JE_4 0U, // JGE_1 0U, // JGE_2 0U, // JGE_4 0U, // JG_1 0U, // JG_2 0U, // JG_4 0U, // JLE_1 0U, // JLE_2 0U, // JLE_4 0U, // JL_1 0U, // JL_2 0U, // JL_4 0U, // JMP16m 0U, // JMP16m_NT 0U, // JMP16r 0U, // JMP16r_NT 0U, // JMP32m 0U, // JMP32m_NT 0U, // JMP32r 0U, // JMP32r_NT 0U, // JMP64m 0U, // JMP64m_NT 0U, // JMP64r 0U, // JMP64r_NT 0U, // JMP_1 0U, // JMP_2 0U, // JMP_4 0U, // JNE_1 0U, // JNE_2 0U, // JNE_4 0U, // JNO_1 0U, // JNO_2 0U, // JNO_4 0U, // JNP_1 0U, // JNP_2 0U, // JNP_4 0U, // JNS_1 0U, // JNS_2 0U, // JNS_4 0U, // JO_1 0U, // JO_2 0U, // JO_4 0U, // JP_1 0U, // JP_2 0U, // JP_4 0U, // JRCXZ 0U, // JS_1 0U, // JS_2 0U, // JS_4 4U, // KADDBrr 4U, // KADDDrr 4U, // KADDQrr 4U, // KADDWrr 4U, // KANDBrr 4U, // KANDDrr 4U, // KANDNBrr 4U, // KANDNDrr 4U, // KANDNQrr 4U, // KANDNWrr 4U, // KANDQrr 4U, // KANDWrr 0U, // KMOVBkk 0U, // KMOVBkm 0U, // KMOVBkr 0U, // KMOVBmk 0U, // KMOVBrk 0U, // KMOVDkk 0U, // KMOVDkm 0U, // KMOVDkr 0U, // KMOVDmk 0U, // KMOVDrk 0U, // KMOVQkk 0U, // KMOVQkm 0U, // KMOVQkr 0U, // KMOVQmk 0U, // KMOVQrk 0U, // KMOVWkk 0U, // KMOVWkm 0U, // KMOVWkr 0U, // KMOVWmk 0U, // KMOVWrk 0U, // KNOTBrr 0U, // KNOTDrr 0U, // KNOTQrr 0U, // KNOTWrr 4U, // KORBrr 4U, // KORDrr 4U, // KORQrr 0U, // KORTESTBrr 0U, // KORTESTDrr 0U, // KORTESTQrr 0U, // KORTESTWrr 4U, // KORWrr 72U, // KSHIFTLBri 72U, // KSHIFTLDri 72U, // KSHIFTLQri 72U, // KSHIFTLWri 72U, // KSHIFTRBri 72U, // KSHIFTRDri 72U, // KSHIFTRQri 72U, // KSHIFTRWri 0U, // KTESTBrr 0U, // KTESTDrr 0U, // KTESTQrr 0U, // KTESTWrr 4U, // KUNPCKBWrr 4U, // KUNPCKDQrr 4U, // KUNPCKWDrr 4U, // KXNORBrr 4U, // KXNORDrr 4U, // KXNORQrr 4U, // KXNORWrr 4U, // KXORBrr 4U, // KXORDrr 4U, // KXORQrr 4U, // KXORWrr 0U, // LAHF 0U, // LAR16rm 0U, // LAR16rr 0U, // LAR32rm 0U, // LAR32rr 0U, // LAR64rm 0U, // LAR64rr 0U, // LDDQUrm 0U, // LDMXCSR 0U, // LDS16rm 0U, // LDS32rm 0U, // LD_F0 0U, // LD_F1 0U, // LD_F32m 0U, // LD_F64m 0U, // LD_F80m 0U, // LD_Fp032 0U, // LD_Fp064 0U, // LD_Fp080 0U, // LD_Fp132 0U, // LD_Fp164 0U, // LD_Fp180 0U, // LD_Fp32m 0U, // LD_Fp32m64 0U, // LD_Fp32m80 0U, // LD_Fp64m 0U, // LD_Fp64m80 0U, // LD_Fp80m 0U, // LD_Frr 0U, // LEA16r 0U, // LEA32r 0U, // LEA64_32r 0U, // LEA64r 0U, // LEAVE 0U, // LEAVE64 0U, // LES16rm 0U, // LES32rm 0U, // LFENCE 0U, // LFS16rm 0U, // LFS32rm 0U, // LFS64rm 0U, // LGDT16m 0U, // LGDT32m 0U, // LGDT64m 0U, // LGS16rm 0U, // LGS32rm 0U, // LGS64rm 0U, // LIDT16m 0U, // LIDT32m 0U, // LIDT64m 0U, // LLDT16m 0U, // LLDT16r 0U, // LLWPCB 0U, // LLWPCB64 0U, // LMSW16m 0U, // LMSW16r 0U, // LOCK_PREFIX 0U, // LODSB 0U, // LODSL 0U, // LODSQ 0U, // LODSW 0U, // LOOP 0U, // LOOPE 0U, // LOOPNE 0U, // LRETIL 0U, // LRETIQ 0U, // LRETIW 0U, // LRETL 0U, // LRETQ 0U, // LRETW 0U, // LSL16rm 0U, // LSL16rr 0U, // LSL32rm 0U, // LSL32rr 0U, // LSL64rm 0U, // LSL64rr 0U, // LSS16rm 0U, // LSS32rm 0U, // LSS64rm 0U, // LTRm 0U, // LTRr 4U, // LWPINS32rmi 4U, // LWPINS32rri 4U, // LWPINS64rmi 4U, // LWPINS64rri 4U, // LWPVAL32rmi 4U, // LWPVAL32rri 4U, // LWPVAL64rmi 4U, // LWPVAL64rri 0U, // LZCNT16rm 0U, // LZCNT16rr 0U, // LZCNT32rm 0U, // LZCNT32rr 0U, // LZCNT64rm 0U, // LZCNT64rr 0U, // MASKMOVDQU 0U, // MASKMOVDQU64 0U, // MAXCPDrm 0U, // MAXCPDrr 0U, // MAXCPSrm 0U, // MAXCPSrr 0U, // MAXCSDrm 0U, // MAXCSDrr 0U, // MAXCSSrm 0U, // MAXCSSrr 0U, // MAXPDrm 0U, // MAXPDrr 0U, // MAXPSrm 0U, // MAXPSrr 0U, // MAXSDrm 0U, // MAXSDrm_Int 0U, // MAXSDrr 0U, // MAXSDrr_Int 0U, // MAXSSrm 0U, // MAXSSrm_Int 0U, // MAXSSrr 0U, // MAXSSrr_Int 0U, // MFENCE 0U, // MINCPDrm 0U, // MINCPDrr 0U, // MINCPSrm 0U, // MINCPSrr 0U, // MINCSDrm 0U, // MINCSDrr 0U, // MINCSSrm 0U, // MINCSSrr 0U, // MINPDrm 0U, // MINPDrr 0U, // MINPSrm 0U, // MINPSrr 0U, // MINSDrm 0U, // MINSDrm_Int 0U, // MINSDrr 0U, // MINSDrr_Int 0U, // MINSSrm 0U, // MINSSrm_Int 0U, // MINSSrr 0U, // MINSSrr_Int 0U, // MMX_CVTPD2PIirm 0U, // MMX_CVTPD2PIirr 0U, // MMX_CVTPI2PDirm 0U, // MMX_CVTPI2PDirr 0U, // MMX_CVTPI2PSirm 0U, // MMX_CVTPI2PSirr 0U, // MMX_CVTPS2PIirm 0U, // MMX_CVTPS2PIirr 0U, // MMX_CVTTPD2PIirm 0U, // MMX_CVTTPD2PIirr 0U, // MMX_CVTTPS2PIirm 0U, // MMX_CVTTPS2PIirr 0U, // MMX_EMMS 0U, // MMX_MASKMOVQ 0U, // MMX_MASKMOVQ64 0U, // MMX_MOVD64from64rm 0U, // MMX_MOVD64from64rr 0U, // MMX_MOVD64grr 0U, // MMX_MOVD64mr 0U, // MMX_MOVD64rm 0U, // MMX_MOVD64rr 0U, // MMX_MOVD64to64rm 0U, // MMX_MOVD64to64rr 0U, // MMX_MOVDQ2Qrr 0U, // MMX_MOVFR642Qrr 0U, // MMX_MOVNTQmr 0U, // MMX_MOVQ2DQrr 0U, // MMX_MOVQ2FR64rr 0U, // MMX_MOVQ64mr 0U, // MMX_MOVQ64rm 0U, // MMX_MOVQ64rr 0U, // MMX_MOVQ64rr_REV 0U, // MMX_PABSBrm 0U, // MMX_PABSBrr 0U, // MMX_PABSDrm 0U, // MMX_PABSDrr 0U, // MMX_PABSWrm 0U, // MMX_PABSWrr 0U, // MMX_PACKSSDWirm 0U, // MMX_PACKSSDWirr 0U, // MMX_PACKSSWBirm 0U, // MMX_PACKSSWBirr 0U, // MMX_PACKUSWBirm 0U, // MMX_PACKUSWBirr 0U, // MMX_PADDBirm 0U, // MMX_PADDBirr 0U, // MMX_PADDDirm 0U, // MMX_PADDDirr 0U, // MMX_PADDQirm 0U, // MMX_PADDQirr 0U, // MMX_PADDSBirm 0U, // MMX_PADDSBirr 0U, // MMX_PADDSWirm 0U, // MMX_PADDSWirr 0U, // MMX_PADDUSBirm 0U, // MMX_PADDUSBirr 0U, // MMX_PADDUSWirm 0U, // MMX_PADDUSWirr 0U, // MMX_PADDWirm 0U, // MMX_PADDWirr 4U, // MMX_PALIGNRrmi 4U, // MMX_PALIGNRrri 0U, // MMX_PANDNirm 0U, // MMX_PANDNirr 0U, // MMX_PANDirm 0U, // MMX_PANDirr 0U, // MMX_PAVGBirm 0U, // MMX_PAVGBirr 0U, // MMX_PAVGWirm 0U, // MMX_PAVGWirr 0U, // MMX_PCMPEQBirm 0U, // MMX_PCMPEQBirr 0U, // MMX_PCMPEQDirm 0U, // MMX_PCMPEQDirr 0U, // MMX_PCMPEQWirm 0U, // MMX_PCMPEQWirr 0U, // MMX_PCMPGTBirm 0U, // MMX_PCMPGTBirr 0U, // MMX_PCMPGTDirm 0U, // MMX_PCMPGTDirr 0U, // MMX_PCMPGTWirm 0U, // MMX_PCMPGTWirr 72U, // MMX_PEXTRWrr 0U, // MMX_PHADDDrm 0U, // MMX_PHADDDrr 0U, // MMX_PHADDSWrm 0U, // MMX_PHADDSWrr 0U, // MMX_PHADDWrm 0U, // MMX_PHADDWrr 0U, // MMX_PHSUBDrm 0U, // MMX_PHSUBDrr 0U, // MMX_PHSUBSWrm 0U, // MMX_PHSUBSWrr 0U, // MMX_PHSUBWrm 0U, // MMX_PHSUBWrr 0U, // MMX_PINSRWrm 4U, // MMX_PINSRWrr 0U, // MMX_PMADDUBSWrm 0U, // MMX_PMADDUBSWrr 0U, // MMX_PMADDWDirm 0U, // MMX_PMADDWDirr 0U, // MMX_PMAXSWirm 0U, // MMX_PMAXSWirr 0U, // MMX_PMAXUBirm 0U, // MMX_PMAXUBirr 0U, // MMX_PMINSWirm 0U, // MMX_PMINSWirr 0U, // MMX_PMINUBirm 0U, // MMX_PMINUBirr 0U, // MMX_PMOVMSKBrr 0U, // MMX_PMULHRSWrm 0U, // MMX_PMULHRSWrr 0U, // MMX_PMULHUWirm 0U, // MMX_PMULHUWirr 0U, // MMX_PMULHWirm 0U, // MMX_PMULHWirr 0U, // MMX_PMULLWirm 0U, // MMX_PMULLWirr 0U, // MMX_PMULUDQirm 0U, // MMX_PMULUDQirr 0U, // MMX_PORirm 0U, // MMX_PORirr 0U, // MMX_PSADBWirm 0U, // MMX_PSADBWirr 0U, // MMX_PSHUFBrm 0U, // MMX_PSHUFBrr 4U, // MMX_PSHUFWmi 72U, // MMX_PSHUFWri 0U, // MMX_PSIGNBrm 0U, // MMX_PSIGNBrr 0U, // MMX_PSIGNDrm 0U, // MMX_PSIGNDrr 0U, // MMX_PSIGNWrm 0U, // MMX_PSIGNWrr 0U, // MMX_PSLLDri 0U, // MMX_PSLLDrm 0U, // MMX_PSLLDrr 0U, // MMX_PSLLQri 0U, // MMX_PSLLQrm 0U, // MMX_PSLLQrr 0U, // MMX_PSLLWri 0U, // MMX_PSLLWrm 0U, // MMX_PSLLWrr 0U, // MMX_PSRADri 0U, // MMX_PSRADrm 0U, // MMX_PSRADrr 0U, // MMX_PSRAWri 0U, // MMX_PSRAWrm 0U, // MMX_PSRAWrr 0U, // MMX_PSRLDri 0U, // MMX_PSRLDrm 0U, // MMX_PSRLDrr 0U, // MMX_PSRLQri 0U, // MMX_PSRLQrm 0U, // MMX_PSRLQrr 0U, // MMX_PSRLWri 0U, // MMX_PSRLWrm 0U, // MMX_PSRLWrr 0U, // MMX_PSUBBirm 0U, // MMX_PSUBBirr 0U, // MMX_PSUBDirm 0U, // MMX_PSUBDirr 0U, // MMX_PSUBQirm 0U, // MMX_PSUBQirr 0U, // MMX_PSUBSBirm 0U, // MMX_PSUBSBirr 0U, // MMX_PSUBSWirm 0U, // MMX_PSUBSWirr 0U, // MMX_PSUBUSBirm 0U, // MMX_PSUBUSBirr 0U, // MMX_PSUBUSWirm 0U, // MMX_PSUBUSWirr 0U, // MMX_PSUBWirm 0U, // MMX_PSUBWirr 0U, // MMX_PUNPCKHBWirm 0U, // MMX_PUNPCKHBWirr 0U, // MMX_PUNPCKHDQirm 0U, // MMX_PUNPCKHDQirr 0U, // MMX_PUNPCKHWDirm 0U, // MMX_PUNPCKHWDirr 0U, // MMX_PUNPCKLBWirm 0U, // MMX_PUNPCKLBWirr 0U, // MMX_PUNPCKLDQirm 0U, // MMX_PUNPCKLDQirr 0U, // MMX_PUNPCKLWDirm 0U, // MMX_PUNPCKLWDirr 0U, // MMX_PXORirm 0U, // MMX_PXORirr 0U, // MONITORXrrr 0U, // MONITORrrr 0U, // MONTMUL 0U, // MOV16ao16 0U, // MOV16ao32 0U, // MOV16ao64 0U, // MOV16mi 0U, // MOV16mr 0U, // MOV16ms 0U, // MOV16o16a 0U, // MOV16o32a 0U, // MOV16o64a 0U, // MOV16ri 0U, // MOV16ri_alt 0U, // MOV16rm 0U, // MOV16rr 0U, // MOV16rr_REV 0U, // MOV16rs 0U, // MOV16sm 0U, // MOV16sr 0U, // MOV32ao16 0U, // MOV32ao32 0U, // MOV32ao64 0U, // MOV32cr 0U, // MOV32dr 0U, // MOV32mi 0U, // MOV32mr 0U, // MOV32o16a 0U, // MOV32o32a 0U, // MOV32o64a 0U, // MOV32rc 0U, // MOV32rd 0U, // MOV32ri 0U, // MOV32ri_alt 0U, // MOV32rm 0U, // MOV32rr 0U, // MOV32rr_REV 0U, // MOV32rs 0U, // MOV32sr 0U, // MOV64ao32 0U, // MOV64ao64 0U, // MOV64cr 0U, // MOV64dr 0U, // MOV64mi32 0U, // MOV64mr 0U, // MOV64o32a 0U, // MOV64o64a 0U, // MOV64rc 0U, // MOV64rd 0U, // MOV64ri 0U, // MOV64ri32 0U, // MOV64rm 0U, // MOV64rr 0U, // MOV64rr_REV 0U, // MOV64rs 0U, // MOV64sr 0U, // MOV64toPQIrm 0U, // MOV64toPQIrr 0U, // MOV64toSDrm 0U, // MOV64toSDrr 0U, // MOV8ao16 0U, // MOV8ao32 0U, // MOV8ao64 0U, // MOV8mi 0U, // MOV8mr 0U, // MOV8mr_NOREX 0U, // MOV8o16a 0U, // MOV8o32a 0U, // MOV8o64a 0U, // MOV8ri 0U, // MOV8ri_alt 0U, // MOV8rm 0U, // MOV8rm_NOREX 0U, // MOV8rr 0U, // MOV8rr_NOREX 0U, // MOV8rr_REV 0U, // MOVAPDmr 0U, // MOVAPDrm 0U, // MOVAPDrr 0U, // MOVAPDrr_REV 0U, // MOVAPSmr 0U, // MOVAPSrm 0U, // MOVAPSrr 0U, // MOVAPSrr_REV 0U, // MOVBE16mr 0U, // MOVBE16rm 0U, // MOVBE32mr 0U, // MOVBE32rm 0U, // MOVBE64mr 0U, // MOVBE64rm 0U, // MOVDDUPrm 0U, // MOVDDUPrr 0U, // MOVDI2PDIrm 0U, // MOVDI2PDIrr 0U, // MOVDI2SSrm 0U, // MOVDI2SSrr 0U, // MOVDIR64B16 0U, // MOVDIR64B32 0U, // MOVDIR64B64 0U, // MOVDIRI32 0U, // MOVDIRI64 0U, // MOVDQAmr 0U, // MOVDQArm 0U, // MOVDQArr 0U, // MOVDQArr_REV 0U, // MOVDQUmr 0U, // MOVDQUrm 0U, // MOVDQUrr 0U, // MOVDQUrr_REV 0U, // MOVHLPSrr 0U, // MOVHPDmr 0U, // MOVHPDrm 0U, // MOVHPSmr 0U, // MOVHPSrm 0U, // MOVLHPSrr 0U, // MOVLPDmr 0U, // MOVLPDrm 0U, // MOVLPSmr 0U, // MOVLPSrm 0U, // MOVMSKPDrr 0U, // MOVMSKPSrr 0U, // MOVNTDQArm 0U, // MOVNTDQmr 0U, // MOVNTI_64mr 0U, // MOVNTImr 0U, // MOVNTPDmr 0U, // MOVNTPSmr 0U, // MOVNTSD 0U, // MOVNTSS 0U, // MOVPDI2DImr 0U, // MOVPDI2DIrr 0U, // MOVPQI2QImr 0U, // MOVPQI2QIrr 0U, // MOVPQIto64mr 0U, // MOVPQIto64rr 0U, // MOVQI2PQIrm 0U, // MOVSB 0U, // MOVSDmr 0U, // MOVSDrm 0U, // MOVSDrr 0U, // MOVSDrr_REV 0U, // MOVSDto64mr 0U, // MOVSDto64rr 0U, // MOVSHDUPrm 0U, // MOVSHDUPrr 0U, // MOVSL 0U, // MOVSLDUPrm 0U, // MOVSLDUPrr 0U, // MOVSQ 0U, // MOVSS2DImr 0U, // MOVSS2DIrr 0U, // MOVSSmr 0U, // MOVSSrm 0U, // MOVSSrr 0U, // MOVSSrr_REV 0U, // MOVSW 0U, // MOVSX16rm16 0U, // MOVSX16rm8 0U, // MOVSX16rr16 0U, // MOVSX16rr8 0U, // MOVSX32rm16 0U, // MOVSX32rm8 0U, // MOVSX32rm8_NOREX 0U, // MOVSX32rr16 0U, // MOVSX32rr8 0U, // MOVSX32rr8_NOREX 0U, // MOVSX64rm16 0U, // MOVSX64rm32 0U, // MOVSX64rm8 0U, // MOVSX64rr16 0U, // MOVSX64rr32 0U, // MOVSX64rr8 0U, // MOVUPDmr 0U, // MOVUPDrm 0U, // MOVUPDrr 0U, // MOVUPDrr_REV 0U, // MOVUPSmr 0U, // MOVUPSrm 0U, // MOVUPSrr 0U, // MOVUPSrr_REV 0U, // MOVZPQILo2PQIrr 0U, // MOVZX16rm16 0U, // MOVZX16rm8 0U, // MOVZX16rr16 0U, // MOVZX16rr8 0U, // MOVZX32rm16 0U, // MOVZX32rm8 0U, // MOVZX32rm8_NOREX 0U, // MOVZX32rr16 0U, // MOVZX32rr8 0U, // MOVZX32rr8_NOREX 0U, // MOVZX64rm16 0U, // MOVZX64rm8 0U, // MOVZX64rr16 0U, // MOVZX64rr8 0U, // MPSADBWrmi 4U, // MPSADBWrri 0U, // MUL16m 0U, // MUL16r 0U, // MUL32m 0U, // MUL32r 0U, // MUL64m 0U, // MUL64r 0U, // MUL8m 0U, // MUL8r 0U, // MULPDrm 0U, // MULPDrr 0U, // MULPSrm 0U, // MULPSrr 0U, // MULSDrm 0U, // MULSDrm_Int 0U, // MULSDrr 0U, // MULSDrr_Int 0U, // MULSSrm 0U, // MULSSrm_Int 0U, // MULSSrr 0U, // MULSSrr_Int 72U, // MULX32rm 4U, // MULX32rr 72U, // MULX64rm 4U, // MULX64rr 0U, // MUL_F32m 0U, // MUL_F64m 0U, // MUL_FI16m 0U, // MUL_FI32m 0U, // MUL_FPrST0 0U, // MUL_FST0r 0U, // MUL_Fp32 0U, // MUL_Fp32m 0U, // MUL_Fp64 0U, // MUL_Fp64m 0U, // MUL_Fp64m32 0U, // MUL_Fp80 0U, // MUL_Fp80m32 0U, // MUL_Fp80m64 0U, // MUL_FpI16m32 0U, // MUL_FpI16m64 0U, // MUL_FpI16m80 0U, // MUL_FpI32m32 0U, // MUL_FpI32m64 0U, // MUL_FpI32m80 0U, // MUL_FrST0 0U, // MWAITXrrr 0U, // MWAITrr 0U, // NEG16m 0U, // NEG16r 0U, // NEG32m 0U, // NEG32r 0U, // NEG64m 0U, // NEG64r 0U, // NEG8m 0U, // NEG8r 0U, // NOOP 0U, // NOOP18_16m4 0U, // NOOP18_16m5 0U, // NOOP18_16m6 0U, // NOOP18_16m7 0U, // NOOP18_16r4 0U, // NOOP18_16r5 0U, // NOOP18_16r6 0U, // NOOP18_16r7 0U, // NOOP18_m4 0U, // NOOP18_m5 0U, // NOOP18_m6 0U, // NOOP18_m7 0U, // NOOP18_r4 0U, // NOOP18_r5 0U, // NOOP18_r6 0U, // NOOP18_r7 0U, // NOOP19rr 0U, // NOOPL 0U, // NOOPL_19 0U, // NOOPL_1d 0U, // NOOPL_1e 0U, // NOOPLr 0U, // NOOPQ 0U, // NOOPQr 0U, // NOOPW 0U, // NOOPW_19 0U, // NOOPW_1c 0U, // NOOPW_1d 0U, // NOOPW_1e 0U, // NOOPWr 0U, // NOT16m 0U, // NOT16r 0U, // NOT32m 0U, // NOT32r 0U, // NOT64m 0U, // NOT64r 0U, // NOT8m 0U, // NOT8r 0U, // OR16i16 0U, // OR16mi 0U, // OR16mi8 0U, // OR16mr 0U, // OR16ri 0U, // OR16ri8 0U, // OR16rm 0U, // OR16rr 0U, // OR16rr_REV 0U, // OR32i32 0U, // OR32mi 0U, // OR32mi8 0U, // OR32mr 0U, // OR32ri 0U, // OR32ri8 0U, // OR32rm 0U, // OR32rr 0U, // OR32rr_REV 0U, // OR64i32 0U, // OR64mi32 0U, // OR64mi8 0U, // OR64mr 0U, // OR64ri32 0U, // OR64ri8 0U, // OR64rm 0U, // OR64rr 0U, // OR64rr_REV 0U, // OR8i8 0U, // OR8mi 0U, // OR8mi8 0U, // OR8mr 0U, // OR8ri 0U, // OR8ri8 0U, // OR8rm 0U, // OR8rr 0U, // OR8rr_REV 0U, // ORPDrm 0U, // ORPDrr 0U, // ORPSrm 0U, // ORPSrr 0U, // OUT16ir 0U, // OUT16rr 0U, // OUT32ir 0U, // OUT32rr 0U, // OUT8ir 0U, // OUT8rr 0U, // OUTSB 0U, // OUTSL 0U, // OUTSW 0U, // PABSBrm 0U, // PABSBrr 0U, // PABSDrm 0U, // PABSDrr 0U, // PABSWrm 0U, // PABSWrr 0U, // PACKSSDWrm 0U, // PACKSSDWrr 0U, // PACKSSWBrm 0U, // PACKSSWBrr 0U, // PACKUSDWrm 0U, // PACKUSDWrr 0U, // PACKUSWBrm 0U, // PACKUSWBrr 0U, // PADDBrm 0U, // PADDBrr 0U, // PADDDrm 0U, // PADDDrr 0U, // PADDQrm 0U, // PADDQrr 0U, // PADDSBrm 0U, // PADDSBrr 0U, // PADDSWrm 0U, // PADDSWrr 0U, // PADDUSBrm 0U, // PADDUSBrr 0U, // PADDUSWrm 0U, // PADDUSWrr 0U, // PADDWrm 0U, // PADDWrr 0U, // PALIGNRrmi 4U, // PALIGNRrri 0U, // PANDNrm 0U, // PANDNrr 0U, // PANDrm 0U, // PANDrr 0U, // PAUSE 0U, // PAVGBrm 0U, // PAVGBrr 0U, // PAVGUSBrm 0U, // PAVGUSBrr 0U, // PAVGWrm 0U, // PAVGWrr 0U, // PBLENDVBrm0 0U, // PBLENDVBrr0 0U, // PBLENDWrmi 4U, // PBLENDWrri 0U, // PCLMULQDQrm 4U, // PCLMULQDQrr 0U, // PCMPEQBrm 0U, // PCMPEQBrr 0U, // PCMPEQDrm 0U, // PCMPEQDrr 0U, // PCMPEQQrm 0U, // PCMPEQQrr 0U, // PCMPEQWrm 0U, // PCMPEQWrr 4U, // PCMPESTRIrm 72U, // PCMPESTRIrr 4U, // PCMPESTRMrm 72U, // PCMPESTRMrr 0U, // PCMPGTBrm 0U, // PCMPGTBrr 0U, // PCMPGTDrm 0U, // PCMPGTDrr 0U, // PCMPGTQrm 0U, // PCMPGTQrr 0U, // PCMPGTWrm 0U, // PCMPGTWrr 4U, // PCMPISTRIrm 72U, // PCMPISTRIrr 4U, // PCMPISTRMrm 72U, // PCMPISTRMrr 0U, // PCONFIG 72U, // PDEP32rm 4U, // PDEP32rr 72U, // PDEP64rm 4U, // PDEP64rr 72U, // PEXT32rm 4U, // PEXT32rr 72U, // PEXT64rm 4U, // PEXT64rr 1U, // PEXTRBmr 72U, // PEXTRBrr 1U, // PEXTRDmr 72U, // PEXTRDrr 1U, // PEXTRQmr 72U, // PEXTRQrr 1U, // PEXTRWmr 72U, // PEXTRWrr 72U, // PEXTRWrr_REV 0U, // PF2IDrm 0U, // PF2IDrr 0U, // PF2IWrm 0U, // PF2IWrr 0U, // PFACCrm 0U, // PFACCrr 0U, // PFADDrm 0U, // PFADDrr 0U, // PFCMPEQrm 0U, // PFCMPEQrr 0U, // PFCMPGErm 0U, // PFCMPGErr 0U, // PFCMPGTrm 0U, // PFCMPGTrr 0U, // PFMAXrm 0U, // PFMAXrr 0U, // PFMINrm 0U, // PFMINrr 0U, // PFMULrm 0U, // PFMULrr 0U, // PFNACCrm 0U, // PFNACCrr 0U, // PFPNACCrm 0U, // PFPNACCrr 0U, // PFRCPIT1rm 0U, // PFRCPIT1rr 0U, // PFRCPIT2rm 0U, // PFRCPIT2rr 0U, // PFRCPrm 0U, // PFRCPrr 0U, // PFRSQIT1rm 0U, // PFRSQIT1rr 0U, // PFRSQRTrm 0U, // PFRSQRTrr 0U, // PFSUBRrm 0U, // PFSUBRrr 0U, // PFSUBrm 0U, // PFSUBrr 0U, // PHADDDrm 0U, // PHADDDrr 0U, // PHADDSWrm 0U, // PHADDSWrr 0U, // PHADDWrm 0U, // PHADDWrr 0U, // PHMINPOSUWrm 0U, // PHMINPOSUWrr 0U, // PHSUBDrm 0U, // PHSUBDrr 0U, // PHSUBSWrm 0U, // PHSUBSWrr 0U, // PHSUBWrm 0U, // PHSUBWrr 0U, // PI2FDrm 0U, // PI2FDrr 0U, // PI2FWrm 0U, // PI2FWrr 4U, // PINSRBrm 4U, // PINSRBrr 4U, // PINSRDrm 4U, // PINSRDrr 4U, // PINSRQrm 4U, // PINSRQrr 0U, // PINSRWrm 4U, // PINSRWrr 0U, // PMADDUBSWrm 0U, // PMADDUBSWrr 0U, // PMADDWDrm 0U, // PMADDWDrr 0U, // PMAXSBrm 0U, // PMAXSBrr 0U, // PMAXSDrm 0U, // PMAXSDrr 0U, // PMAXSWrm 0U, // PMAXSWrr 0U, // PMAXUBrm 0U, // PMAXUBrr 0U, // PMAXUDrm 0U, // PMAXUDrr 0U, // PMAXUWrm 0U, // PMAXUWrr 0U, // PMINSBrm 0U, // PMINSBrr 0U, // PMINSDrm 0U, // PMINSDrr 0U, // PMINSWrm 0U, // PMINSWrr 0U, // PMINUBrm 0U, // PMINUBrr 0U, // PMINUDrm 0U, // PMINUDrr 0U, // PMINUWrm 0U, // PMINUWrr 0U, // PMOVMSKBrr 0U, // PMOVSXBDrm 0U, // PMOVSXBDrr 0U, // PMOVSXBQrm 0U, // PMOVSXBQrr 0U, // PMOVSXBWrm 0U, // PMOVSXBWrr 0U, // PMOVSXDQrm 0U, // PMOVSXDQrr 0U, // PMOVSXWDrm 0U, // PMOVSXWDrr 0U, // PMOVSXWQrm 0U, // PMOVSXWQrr 0U, // PMOVZXBDrm 0U, // PMOVZXBDrr 0U, // PMOVZXBQrm 0U, // PMOVZXBQrr 0U, // PMOVZXBWrm 0U, // PMOVZXBWrr 0U, // PMOVZXDQrm 0U, // PMOVZXDQrr 0U, // PMOVZXWDrm 0U, // PMOVZXWDrr 0U, // PMOVZXWQrm 0U, // PMOVZXWQrr 0U, // PMULDQrm 0U, // PMULDQrr 0U, // PMULHRSWrm 0U, // PMULHRSWrr 0U, // PMULHRWrm 0U, // PMULHRWrr 0U, // PMULHUWrm 0U, // PMULHUWrr 0U, // PMULHWrm 0U, // PMULHWrr 0U, // PMULLDrm 0U, // PMULLDrr 0U, // PMULLWrm 0U, // PMULLWrr 0U, // PMULUDQrm 0U, // PMULUDQrr 0U, // POP16r 0U, // POP16rmm 0U, // POP16rmr 0U, // POP32r 0U, // POP32rmm 0U, // POP32rmr 0U, // POP64r 0U, // POP64rmm 0U, // POP64rmr 0U, // POPA16 0U, // POPA32 0U, // POPCNT16rm 0U, // POPCNT16rr 0U, // POPCNT32rm 0U, // POPCNT32rr 0U, // POPCNT64rm 0U, // POPCNT64rr 0U, // POPDS16 0U, // POPDS32 0U, // POPES16 0U, // POPES32 0U, // POPF16 0U, // POPF32 0U, // POPF64 0U, // POPFS16 0U, // POPFS32 0U, // POPFS64 0U, // POPGS16 0U, // POPGS32 0U, // POPGS64 0U, // POPSS16 0U, // POPSS32 0U, // PORrm 0U, // PORrr 0U, // PREFETCH 0U, // PREFETCHNTA 0U, // PREFETCHT0 0U, // PREFETCHT1 0U, // PREFETCHT2 0U, // PREFETCHW 0U, // PREFETCHWT1 0U, // PSADBWrm 0U, // PSADBWrr 0U, // PSHUFBrm 0U, // PSHUFBrr 4U, // PSHUFDmi 72U, // PSHUFDri 4U, // PSHUFHWmi 72U, // PSHUFHWri 4U, // PSHUFLWmi 72U, // PSHUFLWri 0U, // PSIGNBrm 0U, // PSIGNBrr 0U, // PSIGNDrm 0U, // PSIGNDrr 0U, // PSIGNWrm 0U, // PSIGNWrr 0U, // PSLLDQri 0U, // PSLLDri 0U, // PSLLDrm 0U, // PSLLDrr 0U, // PSLLQri 0U, // PSLLQrm 0U, // PSLLQrr 0U, // PSLLWri 0U, // PSLLWrm 0U, // PSLLWrr 0U, // PSRADri 0U, // PSRADrm 0U, // PSRADrr 0U, // PSRAWri 0U, // PSRAWrm 0U, // PSRAWrr 0U, // PSRLDQri 0U, // PSRLDri 0U, // PSRLDrm 0U, // PSRLDrr 0U, // PSRLQri 0U, // PSRLQrm 0U, // PSRLQrr 0U, // PSRLWri 0U, // PSRLWrm 0U, // PSRLWrr 0U, // PSUBBrm 0U, // PSUBBrr 0U, // PSUBDrm 0U, // PSUBDrr 0U, // PSUBQrm 0U, // PSUBQrr 0U, // PSUBSBrm 0U, // PSUBSBrr 0U, // PSUBSWrm 0U, // PSUBSWrr 0U, // PSUBUSBrm 0U, // PSUBUSBrr 0U, // PSUBUSWrm 0U, // PSUBUSWrr 0U, // PSUBWrm 0U, // PSUBWrr 0U, // PSWAPDrm 0U, // PSWAPDrr 0U, // PTESTrm 0U, // PTESTrr 0U, // PTWRITE64m 0U, // PTWRITE64r 0U, // PTWRITEm 0U, // PTWRITEr 0U, // PUNPCKHBWrm 0U, // PUNPCKHBWrr 0U, // PUNPCKHDQrm 0U, // PUNPCKHDQrr 0U, // PUNPCKHQDQrm 0U, // PUNPCKHQDQrr 0U, // PUNPCKHWDrm 0U, // PUNPCKHWDrr 0U, // PUNPCKLBWrm 0U, // PUNPCKLBWrr 0U, // PUNPCKLDQrm 0U, // PUNPCKLDQrr 0U, // PUNPCKLQDQrm 0U, // PUNPCKLQDQrr 0U, // PUNPCKLWDrm 0U, // PUNPCKLWDrr 0U, // PUSH16i8 0U, // PUSH16r 0U, // PUSH16rmm 0U, // PUSH16rmr 0U, // PUSH32i8 0U, // PUSH32r 0U, // PUSH32rmm 0U, // PUSH32rmr 0U, // PUSH64i32 0U, // PUSH64i8 0U, // PUSH64r 0U, // PUSH64rmm 0U, // PUSH64rmr 0U, // PUSHA16 0U, // PUSHA32 0U, // PUSHCS16 0U, // PUSHCS32 0U, // PUSHDS16 0U, // PUSHDS32 0U, // PUSHES16 0U, // PUSHES32 0U, // PUSHF16 0U, // PUSHF32 0U, // PUSHF64 0U, // PUSHFS16 0U, // PUSHFS32 0U, // PUSHFS64 0U, // PUSHGS16 0U, // PUSHGS32 0U, // PUSHGS64 0U, // PUSHSS16 0U, // PUSHSS32 0U, // PUSHi16 0U, // PUSHi32 0U, // PXORrm 0U, // PXORrr 0U, // RCL16m1 0U, // RCL16mCL 1U, // RCL16mi 0U, // RCL16r1 0U, // RCL16rCL 0U, // RCL16ri 0U, // RCL32m1 0U, // RCL32mCL 1U, // RCL32mi 0U, // RCL32r1 0U, // RCL32rCL 0U, // RCL32ri 0U, // RCL64m1 0U, // RCL64mCL 1U, // RCL64mi 0U, // RCL64r1 0U, // RCL64rCL 0U, // RCL64ri 0U, // RCL8m1 0U, // RCL8mCL 1U, // RCL8mi 0U, // RCL8r1 0U, // RCL8rCL 0U, // RCL8ri 0U, // RCPPSm 0U, // RCPPSr 0U, // RCPSSm 0U, // RCPSSm_Int 0U, // RCPSSr 0U, // RCPSSr_Int 0U, // RCR16m1 0U, // RCR16mCL 1U, // RCR16mi 0U, // RCR16r1 0U, // RCR16rCL 0U, // RCR16ri 0U, // RCR32m1 0U, // RCR32mCL 1U, // RCR32mi 0U, // RCR32r1 0U, // RCR32rCL 0U, // RCR32ri 0U, // RCR64m1 0U, // RCR64mCL 1U, // RCR64mi 0U, // RCR64r1 0U, // RCR64rCL 0U, // RCR64ri 0U, // RCR8m1 0U, // RCR8mCL 1U, // RCR8mi 0U, // RCR8r1 0U, // RCR8rCL 0U, // RCR8ri 0U, // RDFSBASE 0U, // RDFSBASE64 0U, // RDGSBASE 0U, // RDGSBASE64 0U, // RDMSR 0U, // RDPID32 0U, // RDPID64 0U, // RDPKRUr 0U, // RDPMC 0U, // RDRAND16r 0U, // RDRAND32r 0U, // RDRAND64r 0U, // RDSEED16r 0U, // RDSEED32r 0U, // RDSEED64r 0U, // RDSSPD 0U, // RDSSPQ 0U, // RDTSC 0U, // RDTSCP 0U, // REPNE_PREFIX 0U, // REP_PREFIX 0U, // RETIL 0U, // RETIQ 0U, // RETIW 0U, // RETL 0U, // RETQ 0U, // RETW 0U, // REX64_PREFIX 0U, // ROL16m1 0U, // ROL16mCL 1U, // ROL16mi 0U, // ROL16r1 0U, // ROL16rCL 0U, // ROL16ri 0U, // ROL32m1 0U, // ROL32mCL 1U, // ROL32mi 0U, // ROL32r1 0U, // ROL32rCL 0U, // ROL32ri 0U, // ROL64m1 0U, // ROL64mCL 1U, // ROL64mi 0U, // ROL64r1 0U, // ROL64rCL 0U, // ROL64ri 0U, // ROL8m1 0U, // ROL8mCL 1U, // ROL8mi 0U, // ROL8r1 0U, // ROL8rCL 0U, // ROL8ri 0U, // ROR16m1 0U, // ROR16mCL 1U, // ROR16mi 0U, // ROR16r1 0U, // ROR16rCL 0U, // ROR16ri 0U, // ROR32m1 0U, // ROR32mCL 1U, // ROR32mi 0U, // ROR32r1 0U, // ROR32rCL 0U, // ROR32ri 0U, // ROR64m1 0U, // ROR64mCL 1U, // ROR64mi 0U, // ROR64r1 0U, // ROR64rCL 0U, // ROR64ri 0U, // ROR8m1 0U, // ROR8mCL 1U, // ROR8mi 0U, // ROR8r1 0U, // ROR8rCL 0U, // ROR8ri 4U, // RORX32mi 72U, // RORX32ri 4U, // RORX64mi 72U, // RORX64ri 0U, // ROUNDPDm 72U, // ROUNDPDr 0U, // ROUNDPSm 72U, // ROUNDPSr 4U, // ROUNDSDm 4U, // ROUNDSDm_Int 72U, // ROUNDSDr 4U, // ROUNDSDr_Int 4U, // ROUNDSSm 4U, // ROUNDSSm_Int 72U, // ROUNDSSr 4U, // ROUNDSSr_Int 0U, // RSM 0U, // RSQRTPSm 0U, // RSQRTPSr 0U, // RSQRTSSm 0U, // RSQRTSSm_Int 0U, // RSQRTSSr 0U, // RSQRTSSr_Int 0U, // RSTORSSP 0U, // SAHF 0U, // SAL16m1 0U, // SAL16mCL 0U, // SAL16mi 0U, // SAL16r1 0U, // SAL16rCL 0U, // SAL16ri 0U, // SAL32m1 0U, // SAL32mCL 0U, // SAL32mi 0U, // SAL32r1 0U, // SAL32rCL 0U, // SAL32ri 0U, // SAL64m1 0U, // SAL64mCL 0U, // SAL64mi 0U, // SAL64r1 0U, // SAL64rCL 0U, // SAL64ri 0U, // SAL8m1 0U, // SAL8mCL 0U, // SAL8mi 0U, // SAL8r1 0U, // SAL8rCL 0U, // SAL8ri 0U, // SALC 0U, // SAR16m1 0U, // SAR16mCL 1U, // SAR16mi 0U, // SAR16r1 0U, // SAR16rCL 0U, // SAR16ri 0U, // SAR32m1 0U, // SAR32mCL 1U, // SAR32mi 0U, // SAR32r1 0U, // SAR32rCL 0U, // SAR32ri 0U, // SAR64m1 0U, // SAR64mCL 1U, // SAR64mi 0U, // SAR64r1 0U, // SAR64rCL 0U, // SAR64ri 0U, // SAR8m1 0U, // SAR8mCL 1U, // SAR8mi 0U, // SAR8r1 0U, // SAR8rCL 0U, // SAR8ri 4U, // SARX32rm 4U, // SARX32rr 4U, // SARX64rm 4U, // SARX64rr 0U, // SAVEPREVSSP 0U, // SBB16i16 0U, // SBB16mi 0U, // SBB16mi8 0U, // SBB16mr 0U, // SBB16ri 0U, // SBB16ri8 0U, // SBB16rm 0U, // SBB16rr 0U, // SBB16rr_REV 0U, // SBB32i32 0U, // SBB32mi 0U, // SBB32mi8 0U, // SBB32mr 0U, // SBB32ri 0U, // SBB32ri8 0U, // SBB32rm 0U, // SBB32rr 0U, // SBB32rr_REV 0U, // SBB64i32 0U, // SBB64mi32 0U, // SBB64mi8 0U, // SBB64mr 0U, // SBB64ri32 0U, // SBB64ri8 0U, // SBB64rm 0U, // SBB64rr 0U, // SBB64rr_REV 0U, // SBB8i8 0U, // SBB8mi 0U, // SBB8mi8 0U, // SBB8mr 0U, // SBB8ri 0U, // SBB8ri8 0U, // SBB8rm 0U, // SBB8rr 0U, // SBB8rr_REV 0U, // SCASB 0U, // SCASL 0U, // SCASQ 0U, // SCASW 0U, // SETAEm 0U, // SETAEr 0U, // SETAm 0U, // SETAr 0U, // SETBEm 0U, // SETBEr 0U, // SETBm 0U, // SETBr 0U, // SETEm 0U, // SETEr 0U, // SETGEm 0U, // SETGEr 0U, // SETGm 0U, // SETGr 0U, // SETLEm 0U, // SETLEr 0U, // SETLm 0U, // SETLr 0U, // SETNEm 0U, // SETNEr 0U, // SETNOm 0U, // SETNOr 0U, // SETNPm 0U, // SETNPr 0U, // SETNSm 0U, // SETNSr 0U, // SETOm 0U, // SETOr 0U, // SETPm 0U, // SETPr 0U, // SETSSBSY 0U, // SETSm 0U, // SETSr 0U, // SFENCE 0U, // SGDT16m 0U, // SGDT32m 0U, // SGDT64m 0U, // SHA1MSG1rm 0U, // SHA1MSG1rr 0U, // SHA1MSG2rm 0U, // SHA1MSG2rr 0U, // SHA1NEXTErm 0U, // SHA1NEXTErr 0U, // SHA1RNDS4rmi 4U, // SHA1RNDS4rri 0U, // SHA256MSG1rm 0U, // SHA256MSG1rr 0U, // SHA256MSG2rm 0U, // SHA256MSG2rr 0U, // SHA256RNDS2rm 0U, // SHA256RNDS2rr 0U, // SHL16m1 0U, // SHL16mCL 1U, // SHL16mi 0U, // SHL16r1 0U, // SHL16rCL 0U, // SHL16ri 0U, // SHL32m1 0U, // SHL32mCL 1U, // SHL32mi 0U, // SHL32r1 0U, // SHL32rCL 0U, // SHL32ri 0U, // SHL64m1 0U, // SHL64mCL 1U, // SHL64mi 0U, // SHL64r1 0U, // SHL64rCL 0U, // SHL64ri 0U, // SHL8m1 0U, // SHL8mCL 1U, // SHL8mi 0U, // SHL8r1 0U, // SHL8rCL 0U, // SHL8ri 0U, // SHLD16mrCL 1U, // SHLD16mri8 0U, // SHLD16rrCL 4U, // SHLD16rri8 0U, // SHLD32mrCL 1U, // SHLD32mri8 0U, // SHLD32rrCL 4U, // SHLD32rri8 0U, // SHLD64mrCL 1U, // SHLD64mri8 0U, // SHLD64rrCL 4U, // SHLD64rri8 4U, // SHLX32rm 4U, // SHLX32rr 4U, // SHLX64rm 4U, // SHLX64rr 0U, // SHR16m1 0U, // SHR16mCL 1U, // SHR16mi 0U, // SHR16r1 0U, // SHR16rCL 0U, // SHR16ri 0U, // SHR32m1 0U, // SHR32mCL 1U, // SHR32mi 0U, // SHR32r1 0U, // SHR32rCL 0U, // SHR32ri 0U, // SHR64m1 0U, // SHR64mCL 1U, // SHR64mi 0U, // SHR64r1 0U, // SHR64rCL 0U, // SHR64ri 0U, // SHR8m1 0U, // SHR8mCL 1U, // SHR8mi 0U, // SHR8r1 0U, // SHR8rCL 0U, // SHR8ri 0U, // SHRD16mrCL 1U, // SHRD16mri8 0U, // SHRD16rrCL 4U, // SHRD16rri8 0U, // SHRD32mrCL 1U, // SHRD32mri8 0U, // SHRD32rrCL 4U, // SHRD32rri8 0U, // SHRD64mrCL 1U, // SHRD64mri8 0U, // SHRD64rrCL 4U, // SHRD64rri8 4U, // SHRX32rm 4U, // SHRX32rr 4U, // SHRX64rm 4U, // SHRX64rr 0U, // SHUFPDrmi 4U, // SHUFPDrri 0U, // SHUFPSrmi 4U, // SHUFPSrri 0U, // SIDT16m 0U, // SIDT32m 0U, // SIDT64m 0U, // SIN_F 0U, // SIN_Fp32 0U, // SIN_Fp64 0U, // SIN_Fp80 0U, // SKINIT 0U, // SLDT16m 0U, // SLDT16r 0U, // SLDT32r 0U, // SLDT64r 0U, // SLWPCB 0U, // SLWPCB64 0U, // SMSW16m 0U, // SMSW16r 0U, // SMSW32r 0U, // SMSW64r 0U, // SQRTPDm 0U, // SQRTPDr 0U, // SQRTPSm 0U, // SQRTPSr 0U, // SQRTSDm 0U, // SQRTSDm_Int 0U, // SQRTSDr 0U, // SQRTSDr_Int 0U, // SQRTSSm 0U, // SQRTSSm_Int 0U, // SQRTSSr 0U, // SQRTSSr_Int 0U, // SQRT_F 0U, // SQRT_Fp32 0U, // SQRT_Fp64 0U, // SQRT_Fp80 0U, // STAC 0U, // STC 0U, // STD 0U, // STGI 0U, // STI 0U, // STMXCSR 0U, // STOSB 0U, // STOSL 0U, // STOSQ 0U, // STOSW 0U, // STR16r 0U, // STR32r 0U, // STR64r 0U, // STRm 0U, // ST_F32m 0U, // ST_F64m 0U, // ST_FP32m 0U, // ST_FP64m 0U, // ST_FP80m 0U, // ST_FPrr 0U, // ST_Fp32m 0U, // ST_Fp64m 0U, // ST_Fp64m32 0U, // ST_Fp80m32 0U, // ST_Fp80m64 0U, // ST_FpP32m 0U, // ST_FpP64m 0U, // ST_FpP64m32 0U, // ST_FpP80m 0U, // ST_FpP80m32 0U, // ST_FpP80m64 0U, // ST_Frr 0U, // SUB16i16 0U, // SUB16mi 0U, // SUB16mi8 0U, // SUB16mr 0U, // SUB16ri 0U, // SUB16ri8 0U, // SUB16rm 0U, // SUB16rr 0U, // SUB16rr_REV 0U, // SUB32i32 0U, // SUB32mi 0U, // SUB32mi8 0U, // SUB32mr 0U, // SUB32ri 0U, // SUB32ri8 0U, // SUB32rm 0U, // SUB32rr 0U, // SUB32rr_REV 0U, // SUB64i32 0U, // SUB64mi32 0U, // SUB64mi8 0U, // SUB64mr 0U, // SUB64ri32 0U, // SUB64ri8 0U, // SUB64rm 0U, // SUB64rr 0U, // SUB64rr_REV 0U, // SUB8i8 0U, // SUB8mi 0U, // SUB8mi8 0U, // SUB8mr 0U, // SUB8ri 0U, // SUB8ri8 0U, // SUB8rm 0U, // SUB8rr 0U, // SUB8rr_REV 0U, // SUBPDrm 0U, // SUBPDrr 0U, // SUBPSrm 0U, // SUBPSrr 0U, // SUBR_F32m 0U, // SUBR_F64m 0U, // SUBR_FI16m 0U, // SUBR_FI32m 0U, // SUBR_FPrST0 0U, // SUBR_FST0r 0U, // SUBR_Fp32m 0U, // SUBR_Fp64m 0U, // SUBR_Fp64m32 0U, // SUBR_Fp80m32 0U, // SUBR_Fp80m64 0U, // SUBR_FpI16m32 0U, // SUBR_FpI16m64 0U, // SUBR_FpI16m80 0U, // SUBR_FpI32m32 0U, // SUBR_FpI32m64 0U, // SUBR_FpI32m80 0U, // SUBR_FrST0 0U, // SUBSDrm 0U, // SUBSDrm_Int 0U, // SUBSDrr 0U, // SUBSDrr_Int 0U, // SUBSSrm 0U, // SUBSSrm_Int 0U, // SUBSSrr 0U, // SUBSSrr_Int 0U, // SUB_F32m 0U, // SUB_F64m 0U, // SUB_FI16m 0U, // SUB_FI32m 0U, // SUB_FPrST0 0U, // SUB_FST0r 0U, // SUB_Fp32 0U, // SUB_Fp32m 0U, // SUB_Fp64 0U, // SUB_Fp64m 0U, // SUB_Fp64m32 0U, // SUB_Fp80 0U, // SUB_Fp80m32 0U, // SUB_Fp80m64 0U, // SUB_FpI16m32 0U, // SUB_FpI16m64 0U, // SUB_FpI16m80 0U, // SUB_FpI32m32 0U, // SUB_FpI32m64 0U, // SUB_FpI32m80 0U, // SUB_FrST0 0U, // SWAPGS 0U, // SYSCALL 0U, // SYSENTER 0U, // SYSEXIT 0U, // SYSEXIT64 0U, // SYSRET 0U, // SYSRET64 0U, // T1MSKC32rm 0U, // T1MSKC32rr 0U, // T1MSKC64rm 0U, // T1MSKC64rr 0U, // TEST16i16 0U, // TEST16mi 0U, // TEST16mi_alt 0U, // TEST16mr 0U, // TEST16ri 0U, // TEST16ri_alt 0U, // TEST16rr 0U, // TEST32i32 0U, // TEST32mi 0U, // TEST32mi_alt 0U, // TEST32mr 0U, // TEST32ri 0U, // TEST32ri_alt 0U, // TEST32rr 0U, // TEST64i32 0U, // TEST64mi32 0U, // TEST64mi32_alt 0U, // TEST64mr 0U, // TEST64ri32 0U, // TEST64ri32_alt 0U, // TEST64rr 0U, // TEST8i8 0U, // TEST8mi 0U, // TEST8mi_alt 0U, // TEST8mr 0U, // TEST8ri 0U, // TEST8ri_alt 0U, // TEST8rr 0U, // TPAUSE 0U, // TST_F 0U, // TST_Fp32 0U, // TST_Fp64 0U, // TST_Fp80 0U, // TZCNT16rm 0U, // TZCNT16rr 0U, // TZCNT32rm 0U, // TZCNT32rr 0U, // TZCNT64rm 0U, // TZCNT64rr 0U, // TZMSK32rm 0U, // TZMSK32rr 0U, // TZMSK64rm 0U, // TZMSK64rr 0U, // UCOMISDrm 0U, // UCOMISDrm_Int 0U, // UCOMISDrr 0U, // UCOMISDrr_Int 0U, // UCOMISSrm 0U, // UCOMISSrm_Int 0U, // UCOMISSrr 0U, // UCOMISSrr_Int 0U, // UCOM_FIPr 0U, // UCOM_FIr 0U, // UCOM_FPPr 0U, // UCOM_FPr 0U, // UCOM_FpIr32 0U, // UCOM_FpIr64 0U, // UCOM_FpIr80 0U, // UCOM_Fpr32 0U, // UCOM_Fpr64 0U, // UCOM_Fpr80 0U, // UCOM_Fr 0U, // UD0 0U, // UD1 0U, // UD2 0U, // UMONITOR16 0U, // UMONITOR32 0U, // UMONITOR64 0U, // UMWAIT 0U, // UNPCKHPDrm 0U, // UNPCKHPDrr 0U, // UNPCKHPSrm 0U, // UNPCKHPSrr 0U, // UNPCKLPDrm 0U, // UNPCKLPDrr 0U, // UNPCKLPSrm 0U, // UNPCKLPSrr 4U, // V4FMADDPSrm 0U, // V4FMADDPSrmk 0U, // V4FMADDPSrmkz 4U, // V4FMADDSSrm 0U, // V4FMADDSSrmk 0U, // V4FMADDSSrmkz 4U, // V4FNMADDPSrm 0U, // V4FNMADDPSrmk 0U, // V4FNMADDPSrmkz 4U, // V4FNMADDSSrm 0U, // V4FNMADDSSrmk 0U, // V4FNMADDSSrmkz 4U, // VADDPDYrm 4U, // VADDPDYrr 4U, // VADDPDZ128rm 72U, // VADDPDZ128rmb 133U, // VADDPDZ128rmbk 9348U, // VADDPDZ128rmbkz 0U, // VADDPDZ128rmk 9348U, // VADDPDZ128rmkz 4U, // VADDPDZ128rr 0U, // VADDPDZ128rrk 9348U, // VADDPDZ128rrkz 4U, // VADDPDZ256rm 72U, // VADDPDZ256rmb 133U, // VADDPDZ256rmbk 9348U, // VADDPDZ256rmbkz 0U, // VADDPDZ256rmk 9348U, // VADDPDZ256rmkz 4U, // VADDPDZ256rr 0U, // VADDPDZ256rrk 9348U, // VADDPDZ256rrkz 4U, // VADDPDZrm 72U, // VADDPDZrmb 133U, // VADDPDZrmbk 9348U, // VADDPDZrmbkz 0U, // VADDPDZrmk 9348U, // VADDPDZrmkz 4U, // VADDPDZrr 4U, // VADDPDZrrb 0U, // VADDPDZrrbk 9348U, // VADDPDZrrbkz 0U, // VADDPDZrrk 9348U, // VADDPDZrrkz 4U, // VADDPDrm 4U, // VADDPDrr 4U, // VADDPSYrm 4U, // VADDPSYrr 4U, // VADDPSZ128rm 72U, // VADDPSZ128rmb 133U, // VADDPSZ128rmbk 9348U, // VADDPSZ128rmbkz 0U, // VADDPSZ128rmk 9348U, // VADDPSZ128rmkz 4U, // VADDPSZ128rr 0U, // VADDPSZ128rrk 9348U, // VADDPSZ128rrkz 4U, // VADDPSZ256rm 72U, // VADDPSZ256rmb 133U, // VADDPSZ256rmbk 9348U, // VADDPSZ256rmbkz 0U, // VADDPSZ256rmk 9348U, // VADDPSZ256rmkz 4U, // VADDPSZ256rr 0U, // VADDPSZ256rrk 9348U, // VADDPSZ256rrkz 4U, // VADDPSZrm 72U, // VADDPSZrmb 133U, // VADDPSZrmbk 9348U, // VADDPSZrmbkz 0U, // VADDPSZrmk 9348U, // VADDPSZrmkz 4U, // VADDPSZrr 4U, // VADDPSZrrb 0U, // VADDPSZrrbk 9348U, // VADDPSZrrbkz 0U, // VADDPSZrrk 9348U, // VADDPSZrrkz 4U, // VADDPSrm 4U, // VADDPSrr 72U, // VADDSDZrm 72U, // VADDSDZrm_Int 133U, // VADDSDZrm_Intk 9348U, // VADDSDZrm_Intkz 4U, // VADDSDZrr 4U, // VADDSDZrr_Int 0U, // VADDSDZrr_Intk 9348U, // VADDSDZrr_Intkz 4U, // VADDSDZrrb_Int 0U, // VADDSDZrrb_Intk 9348U, // VADDSDZrrb_Intkz 72U, // VADDSDrm 72U, // VADDSDrm_Int 4U, // VADDSDrr 4U, // VADDSDrr_Int 72U, // VADDSSZrm 72U, // VADDSSZrm_Int 133U, // VADDSSZrm_Intk 9348U, // VADDSSZrm_Intkz 4U, // VADDSSZrr 4U, // VADDSSZrr_Int 0U, // VADDSSZrr_Intk 9348U, // VADDSSZrr_Intkz 4U, // VADDSSZrrb_Int 0U, // VADDSSZrrb_Intk 9348U, // VADDSSZrrb_Intkz 72U, // VADDSSrm 72U, // VADDSSrm_Int 4U, // VADDSSrr 4U, // VADDSSrr_Int 4U, // VADDSUBPDYrm 4U, // VADDSUBPDYrr 4U, // VADDSUBPDrm 4U, // VADDSUBPDrr 4U, // VADDSUBPSYrm 4U, // VADDSUBPSYrr 4U, // VADDSUBPSrm 4U, // VADDSUBPSrr 4U, // VAESDECLASTYrm 4U, // VAESDECLASTYrr 4U, // VAESDECLASTZ128rm 4U, // VAESDECLASTZ128rr 4U, // VAESDECLASTZ256rm 4U, // VAESDECLASTZ256rr 4U, // VAESDECLASTZrm 4U, // VAESDECLASTZrr 4U, // VAESDECLASTrm 4U, // VAESDECLASTrr 4U, // VAESDECYrm 4U, // VAESDECYrr 4U, // VAESDECZ128rm 4U, // VAESDECZ128rr 4U, // VAESDECZ256rm 4U, // VAESDECZ256rr 4U, // VAESDECZrm 4U, // VAESDECZrr 4U, // VAESDECrm 4U, // VAESDECrr 4U, // VAESENCLASTYrm 4U, // VAESENCLASTYrr 4U, // VAESENCLASTZ128rm 4U, // VAESENCLASTZ128rr 4U, // VAESENCLASTZ256rm 4U, // VAESENCLASTZ256rr 4U, // VAESENCLASTZrm 4U, // VAESENCLASTZrr 4U, // VAESENCLASTrm 4U, // VAESENCLASTrr 4U, // VAESENCYrm 4U, // VAESENCYrr 4U, // VAESENCZ128rm 4U, // VAESENCZ128rr 4U, // VAESENCZ256rm 4U, // VAESENCZ256rr 4U, // VAESENCZrm 4U, // VAESENCZrr 4U, // VAESENCrm 4U, // VAESENCrr 0U, // VAESIMCrm 0U, // VAESIMCrr 4U, // VAESKEYGENASSIST128rm 72U, // VAESKEYGENASSIST128rr 18637U, // VALIGNDZ128rmbi 26833U, // VALIGNDZ128rmbik 26837U, // VALIGNDZ128rmbikz 72U, // VALIGNDZ128rmi 1U, // VALIGNDZ128rmik 9348U, // VALIGNDZ128rmikz 18636U, // VALIGNDZ128rri 25U, // VALIGNDZ128rrik 26837U, // VALIGNDZ128rrikz 18637U, // VALIGNDZ256rmbi 26833U, // VALIGNDZ256rmbik 26837U, // VALIGNDZ256rmbikz 72U, // VALIGNDZ256rmi 1U, // VALIGNDZ256rmik 9348U, // VALIGNDZ256rmikz 18636U, // VALIGNDZ256rri 25U, // VALIGNDZ256rrik 26837U, // VALIGNDZ256rrikz 18637U, // VALIGNDZrmbi 26833U, // VALIGNDZrmbik 26837U, // VALIGNDZrmbikz 72U, // VALIGNDZrmi 1U, // VALIGNDZrmik 9348U, // VALIGNDZrmikz 18636U, // VALIGNDZrri 25U, // VALIGNDZrrik 26837U, // VALIGNDZrrikz 18637U, // VALIGNQZ128rmbi 26833U, // VALIGNQZ128rmbik 26837U, // VALIGNQZ128rmbikz 72U, // VALIGNQZ128rmi 1U, // VALIGNQZ128rmik 9348U, // VALIGNQZ128rmikz 18636U, // VALIGNQZ128rri 25U, // VALIGNQZ128rrik 26837U, // VALIGNQZ128rrikz 18637U, // VALIGNQZ256rmbi 26833U, // VALIGNQZ256rmbik 26837U, // VALIGNQZ256rmbikz 72U, // VALIGNQZ256rmi 1U, // VALIGNQZ256rmik 9348U, // VALIGNQZ256rmikz 18636U, // VALIGNQZ256rri 25U, // VALIGNQZ256rrik 26837U, // VALIGNQZ256rrikz 18637U, // VALIGNQZrmbi 26833U, // VALIGNQZrmbik 26837U, // VALIGNQZrmbikz 72U, // VALIGNQZrmi 1U, // VALIGNQZrmik 9348U, // VALIGNQZrmikz 18636U, // VALIGNQZrri 25U, // VALIGNQZrrik 26837U, // VALIGNQZrrikz 4U, // VANDNPDYrm 4U, // VANDNPDYrr 4U, // VANDNPDZ128rm 72U, // VANDNPDZ128rmb 133U, // VANDNPDZ128rmbk 9348U, // VANDNPDZ128rmbkz 0U, // VANDNPDZ128rmk 9348U, // VANDNPDZ128rmkz 4U, // VANDNPDZ128rr 0U, // VANDNPDZ128rrk 9348U, // VANDNPDZ128rrkz 4U, // VANDNPDZ256rm 72U, // VANDNPDZ256rmb 133U, // VANDNPDZ256rmbk 9348U, // VANDNPDZ256rmbkz 0U, // VANDNPDZ256rmk 9348U, // VANDNPDZ256rmkz 4U, // VANDNPDZ256rr 0U, // VANDNPDZ256rrk 9348U, // VANDNPDZ256rrkz 4U, // VANDNPDZrm 72U, // VANDNPDZrmb 133U, // VANDNPDZrmbk 9348U, // VANDNPDZrmbkz 0U, // VANDNPDZrmk 9348U, // VANDNPDZrmkz 4U, // VANDNPDZrr 0U, // VANDNPDZrrk 9348U, // VANDNPDZrrkz 4U, // VANDNPDrm 4U, // VANDNPDrr 4U, // VANDNPSYrm 4U, // VANDNPSYrr 4U, // VANDNPSZ128rm 72U, // VANDNPSZ128rmb 133U, // VANDNPSZ128rmbk 9348U, // VANDNPSZ128rmbkz 0U, // VANDNPSZ128rmk 9348U, // VANDNPSZ128rmkz 4U, // VANDNPSZ128rr 0U, // VANDNPSZ128rrk 9348U, // VANDNPSZ128rrkz 4U, // VANDNPSZ256rm 72U, // VANDNPSZ256rmb 133U, // VANDNPSZ256rmbk 9348U, // VANDNPSZ256rmbkz 0U, // VANDNPSZ256rmk 9348U, // VANDNPSZ256rmkz 4U, // VANDNPSZ256rr 0U, // VANDNPSZ256rrk 9348U, // VANDNPSZ256rrkz 4U, // VANDNPSZrm 72U, // VANDNPSZrmb 133U, // VANDNPSZrmbk 9348U, // VANDNPSZrmbkz 0U, // VANDNPSZrmk 9348U, // VANDNPSZrmkz 4U, // VANDNPSZrr 0U, // VANDNPSZrrk 9348U, // VANDNPSZrrkz 4U, // VANDNPSrm 4U, // VANDNPSrr 4U, // VANDPDYrm 4U, // VANDPDYrr 4U, // VANDPDZ128rm 72U, // VANDPDZ128rmb 133U, // VANDPDZ128rmbk 9348U, // VANDPDZ128rmbkz 0U, // VANDPDZ128rmk 9348U, // VANDPDZ128rmkz 4U, // VANDPDZ128rr 0U, // VANDPDZ128rrk 9348U, // VANDPDZ128rrkz 4U, // VANDPDZ256rm 72U, // VANDPDZ256rmb 133U, // VANDPDZ256rmbk 9348U, // VANDPDZ256rmbkz 0U, // VANDPDZ256rmk 9348U, // VANDPDZ256rmkz 4U, // VANDPDZ256rr 0U, // VANDPDZ256rrk 9348U, // VANDPDZ256rrkz 4U, // VANDPDZrm 72U, // VANDPDZrmb 133U, // VANDPDZrmbk 9348U, // VANDPDZrmbkz 0U, // VANDPDZrmk 9348U, // VANDPDZrmkz 4U, // VANDPDZrr 0U, // VANDPDZrrk 9348U, // VANDPDZrrkz 4U, // VANDPDrm 4U, // VANDPDrr 4U, // VANDPSYrm 4U, // VANDPSYrr 4U, // VANDPSZ128rm 72U, // VANDPSZ128rmb 133U, // VANDPSZ128rmbk 9348U, // VANDPSZ128rmbkz 0U, // VANDPSZ128rmk 9348U, // VANDPSZ128rmkz 4U, // VANDPSZ128rr 0U, // VANDPSZ128rrk 9348U, // VANDPSZ128rrkz 4U, // VANDPSZ256rm 72U, // VANDPSZ256rmb 133U, // VANDPSZ256rmbk 9348U, // VANDPSZ256rmbkz 0U, // VANDPSZ256rmk 9348U, // VANDPSZ256rmkz 4U, // VANDPSZ256rr 0U, // VANDPSZ256rrk 9348U, // VANDPSZ256rrkz 4U, // VANDPSZrm 72U, // VANDPSZrmb 133U, // VANDPSZrmbk 9348U, // VANDPSZrmbkz 0U, // VANDPSZrmk 9348U, // VANDPSZrmkz 4U, // VANDPSZrr 0U, // VANDPSZrrk 9348U, // VANDPSZrrkz 4U, // VANDPSrm 4U, // VANDPSrr 4U, // VBLENDMPDZ128rm 72U, // VBLENDMPDZ128rmb 1156U, // VBLENDMPDZ128rmbk 9348U, // VBLENDMPDZ128rmbkz 1156U, // VBLENDMPDZ128rmk 9348U, // VBLENDMPDZ128rmkz 4U, // VBLENDMPDZ128rr 1156U, // VBLENDMPDZ128rrk 9348U, // VBLENDMPDZ128rrkz 4U, // VBLENDMPDZ256rm 72U, // VBLENDMPDZ256rmb 1156U, // VBLENDMPDZ256rmbk 9348U, // VBLENDMPDZ256rmbkz 1156U, // VBLENDMPDZ256rmk 9348U, // VBLENDMPDZ256rmkz 4U, // VBLENDMPDZ256rr 1156U, // VBLENDMPDZ256rrk 9348U, // VBLENDMPDZ256rrkz 4U, // VBLENDMPDZrm 72U, // VBLENDMPDZrmb 1156U, // VBLENDMPDZrmbk 9348U, // VBLENDMPDZrmbkz 1156U, // VBLENDMPDZrmk 9348U, // VBLENDMPDZrmkz 4U, // VBLENDMPDZrr 1156U, // VBLENDMPDZrrk 9348U, // VBLENDMPDZrrkz 4U, // VBLENDMPSZ128rm 72U, // VBLENDMPSZ128rmb 1156U, // VBLENDMPSZ128rmbk 9348U, // VBLENDMPSZ128rmbkz 1156U, // VBLENDMPSZ128rmk 9348U, // VBLENDMPSZ128rmkz 4U, // VBLENDMPSZ128rr 1156U, // VBLENDMPSZ128rrk 9348U, // VBLENDMPSZ128rrkz 4U, // VBLENDMPSZ256rm 72U, // VBLENDMPSZ256rmb 1156U, // VBLENDMPSZ256rmbk 9348U, // VBLENDMPSZ256rmbkz 1156U, // VBLENDMPSZ256rmk 9348U, // VBLENDMPSZ256rmkz 4U, // VBLENDMPSZ256rr 1156U, // VBLENDMPSZ256rrk 9348U, // VBLENDMPSZ256rrkz 4U, // VBLENDMPSZrm 72U, // VBLENDMPSZrmb 1156U, // VBLENDMPSZrmbk 9348U, // VBLENDMPSZrmbkz 1156U, // VBLENDMPSZrmk 9348U, // VBLENDMPSZrmkz 4U, // VBLENDMPSZrr 1156U, // VBLENDMPSZrrk 9348U, // VBLENDMPSZrrkz 72U, // VBLENDPDYrmi 18636U, // VBLENDPDYrri 72U, // VBLENDPDrmi 18636U, // VBLENDPDrri 72U, // VBLENDPSYrmi 18636U, // VBLENDPSYrri 72U, // VBLENDPSrmi 18636U, // VBLENDPSrri 72U, // VBLENDVPDYrm 18636U, // VBLENDVPDYrr 72U, // VBLENDVPDrm 18636U, // VBLENDVPDrr 72U, // VBLENDVPSYrm 18636U, // VBLENDVPSYrr 72U, // VBLENDVPSrm 18636U, // VBLENDVPSrr 0U, // VBROADCASTF128 0U, // VBROADCASTF32X2Z256m 3356U, // VBROADCASTF32X2Z256mk 4444U, // VBROADCASTF32X2Z256mkz 0U, // VBROADCASTF32X2Z256r 405U, // VBROADCASTF32X2Z256rk 461U, // VBROADCASTF32X2Z256rkz 0U, // VBROADCASTF32X2Zm 3356U, // VBROADCASTF32X2Zmk 4444U, // VBROADCASTF32X2Zmkz 0U, // VBROADCASTF32X2Zr 405U, // VBROADCASTF32X2Zrk 461U, // VBROADCASTF32X2Zrkz 0U, // VBROADCASTF32X4Z256rm 405U, // VBROADCASTF32X4Z256rmk 461U, // VBROADCASTF32X4Z256rmkz 0U, // VBROADCASTF32X4rm 405U, // VBROADCASTF32X4rmk 461U, // VBROADCASTF32X4rmkz 0U, // VBROADCASTF32X8rm 405U, // VBROADCASTF32X8rmk 461U, // VBROADCASTF32X8rmkz 0U, // VBROADCASTF64X2Z128rm 405U, // VBROADCASTF64X2Z128rmk 461U, // VBROADCASTF64X2Z128rmkz 0U, // VBROADCASTF64X2rm 405U, // VBROADCASTF64X2rmk 461U, // VBROADCASTF64X2rmkz 0U, // VBROADCASTF64X4rm 405U, // VBROADCASTF64X4rmk 461U, // VBROADCASTF64X4rmkz 0U, // VBROADCASTI128 0U, // VBROADCASTI32X2Z128m 3356U, // VBROADCASTI32X2Z128mk 4444U, // VBROADCASTI32X2Z128mkz 0U, // VBROADCASTI32X2Z128r 405U, // VBROADCASTI32X2Z128rk 461U, // VBROADCASTI32X2Z128rkz 0U, // VBROADCASTI32X2Z256m 3356U, // VBROADCASTI32X2Z256mk 4444U, // VBROADCASTI32X2Z256mkz 0U, // VBROADCASTI32X2Z256r 405U, // VBROADCASTI32X2Z256rk 461U, // VBROADCASTI32X2Z256rkz 0U, // VBROADCASTI32X2Zm 3356U, // VBROADCASTI32X2Zmk 4444U, // VBROADCASTI32X2Zmkz 0U, // VBROADCASTI32X2Zr 405U, // VBROADCASTI32X2Zrk 461U, // VBROADCASTI32X2Zrkz 0U, // VBROADCASTI32X4Z256rm 405U, // VBROADCASTI32X4Z256rmk 461U, // VBROADCASTI32X4Z256rmkz 0U, // VBROADCASTI32X4rm 405U, // VBROADCASTI32X4rmk 461U, // VBROADCASTI32X4rmkz 0U, // VBROADCASTI32X8rm 405U, // VBROADCASTI32X8rmk 461U, // VBROADCASTI32X8rmkz 0U, // VBROADCASTI64X2Z128rm 405U, // VBROADCASTI64X2Z128rmk 461U, // VBROADCASTI64X2Z128rmkz 0U, // VBROADCASTI64X2rm 405U, // VBROADCASTI64X2rmk 461U, // VBROADCASTI64X2rmkz 0U, // VBROADCASTI64X4rm 405U, // VBROADCASTI64X4rmk 461U, // VBROADCASTI64X4rmkz 0U, // VBROADCASTSDYrm 0U, // VBROADCASTSDYrr 0U, // VBROADCASTSDZ256m 3356U, // VBROADCASTSDZ256mk 4444U, // VBROADCASTSDZ256mkz 0U, // VBROADCASTSDZ256r 405U, // VBROADCASTSDZ256rk 461U, // VBROADCASTSDZ256rkz 0U, // VBROADCASTSDZm 3356U, // VBROADCASTSDZmk 4444U, // VBROADCASTSDZmkz 0U, // VBROADCASTSDZr 405U, // VBROADCASTSDZrk 461U, // VBROADCASTSDZrkz 0U, // VBROADCASTSSYrm 0U, // VBROADCASTSSYrr 0U, // VBROADCASTSSZ128m 3356U, // VBROADCASTSSZ128mk 4444U, // VBROADCASTSSZ128mkz 0U, // VBROADCASTSSZ128r 405U, // VBROADCASTSSZ128rk 461U, // VBROADCASTSSZ128rkz 0U, // VBROADCASTSSZ256m 3356U, // VBROADCASTSSZ256mk 4444U, // VBROADCASTSSZ256mkz 0U, // VBROADCASTSSZ256r 405U, // VBROADCASTSSZ256rk 461U, // VBROADCASTSSZ256rkz 0U, // VBROADCASTSSZm 3356U, // VBROADCASTSSZmk 4444U, // VBROADCASTSSZmkz 0U, // VBROADCASTSSZr 405U, // VBROADCASTSSZrk 461U, // VBROADCASTSSZrkz 0U, // VBROADCASTSSrm 0U, // VBROADCASTSSrr 1U, // VCMPPDYrmi 72U, // VCMPPDYrmi_alt 18636U, // VCMPPDYrri 18636U, // VCMPPDYrri_alt 21856U, // VCMPPDZ128rmbi 18637U, // VCMPPDZ128rmbi_alt 26837U, // VCMPPDZ128rmbi_altk 29985U, // VCMPPDZ128rmbik 18636U, // VCMPPDZ128rmi 72U, // VCMPPDZ128rmi_alt 1156U, // VCMPPDZ128rmi_altk 1U, // VCMPPDZ128rmik 18636U, // VCMPPDZ128rri 18636U, // VCMPPDZ128rri_alt 26837U, // VCMPPDZ128rri_altk 26837U, // VCMPPDZ128rrik 21860U, // VCMPPDZ256rmbi 18637U, // VCMPPDZ256rmbi_alt 26837U, // VCMPPDZ256rmbi_altk 29989U, // VCMPPDZ256rmbik 1U, // VCMPPDZ256rmi 72U, // VCMPPDZ256rmi_alt 1156U, // VCMPPDZ256rmi_altk 2U, // VCMPPDZ256rmik 18636U, // VCMPPDZ256rri 18636U, // VCMPPDZ256rri_alt 26837U, // VCMPPDZ256rri_altk 26837U, // VCMPPDZ256rrik 21864U, // VCMPPDZrmbi 18637U, // VCMPPDZrmbi_alt 26837U, // VCMPPDZrmbi_altk 29993U, // VCMPPDZrmbik 2U, // VCMPPDZrmi 72U, // VCMPPDZrmi_alt 1156U, // VCMPPDZrmi_altk 2U, // VCMPPDZrmik 18636U, // VCMPPDZrri 18636U, // VCMPPDZrri_alt 26837U, // VCMPPDZrri_altk 18636U, // VCMPPDZrrib 18636U, // VCMPPDZrrib_alt 26837U, // VCMPPDZrrib_altk 26837U, // VCMPPDZrribk 26837U, // VCMPPDZrrik 18636U, // VCMPPDrmi 72U, // VCMPPDrmi_alt 18636U, // VCMPPDrri 18636U, // VCMPPDrri_alt 1U, // VCMPPSYrmi 72U, // VCMPPSYrmi_alt 18636U, // VCMPPSYrri 18636U, // VCMPPSYrri_alt 21860U, // VCMPPSZ128rmbi 18637U, // VCMPPSZ128rmbi_alt 26837U, // VCMPPSZ128rmbi_altk 29990U, // VCMPPSZ128rmbik 18636U, // VCMPPSZ128rmi 72U, // VCMPPSZ128rmi_alt 1156U, // VCMPPSZ128rmi_altk 1U, // VCMPPSZ128rmik 18636U, // VCMPPSZ128rri 18636U, // VCMPPSZ128rri_alt 26837U, // VCMPPSZ128rri_altk 26837U, // VCMPPSZ128rrik 21864U, // VCMPPSZ256rmbi 18637U, // VCMPPSZ256rmbi_alt 26837U, // VCMPPSZ256rmbi_altk 29994U, // VCMPPSZ256rmbik 1U, // VCMPPSZ256rmi 72U, // VCMPPSZ256rmi_alt 1156U, // VCMPPSZ256rmi_altk 2U, // VCMPPSZ256rmik 18636U, // VCMPPSZ256rri 18636U, // VCMPPSZ256rri_alt 26837U, // VCMPPSZ256rri_altk 26837U, // VCMPPSZ256rrik 21868U, // VCMPPSZrmbi 18637U, // VCMPPSZrmbi_alt 26837U, // VCMPPSZrmbi_altk 29998U, // VCMPPSZrmbik 2U, // VCMPPSZrmi 72U, // VCMPPSZrmi_alt 1156U, // VCMPPSZrmi_altk 2U, // VCMPPSZrmik 18636U, // VCMPPSZrri 18636U, // VCMPPSZrri_alt 26837U, // VCMPPSZrri_altk 18636U, // VCMPPSZrrib 18636U, // VCMPPSZrrib_alt 26837U, // VCMPPSZrrib_altk 26837U, // VCMPPSZrribk 26837U, // VCMPPSZrrik 18636U, // VCMPPSrmi 72U, // VCMPPSrmi_alt 18636U, // VCMPPSrri 18636U, // VCMPPSrri_alt 21832U, // VCMPSDZrm 21832U, // VCMPSDZrm_Int 29961U, // VCMPSDZrm_Intk 18636U, // VCMPSDZrmi_alt 26836U, // VCMPSDZrmi_altk 18636U, // VCMPSDZrr 18636U, // VCMPSDZrr_Int 26837U, // VCMPSDZrr_Intk 18636U, // VCMPSDZrrb_Int 26837U, // VCMPSDZrrb_Intk 18636U, // VCMPSDZrrb_alt 26837U, // VCMPSDZrrb_altk 18636U, // VCMPSDZrri_alt 26837U, // VCMPSDZrri_altk 21832U, // VCMPSDrm 21832U, // VCMPSDrm_Int 18636U, // VCMPSDrm_alt 18636U, // VCMPSDrr 18636U, // VCMPSDrr_Int 18636U, // VCMPSDrr_alt 21832U, // VCMPSSZrm 21832U, // VCMPSSZrm_Int 29962U, // VCMPSSZrm_Intk 18636U, // VCMPSSZrmi_alt 26836U, // VCMPSSZrmi_altk 18636U, // VCMPSSZrr 18636U, // VCMPSSZrr_Int 26837U, // VCMPSSZrr_Intk 18636U, // VCMPSSZrrb_Int 26837U, // VCMPSSZrrb_Intk 18636U, // VCMPSSZrrb_alt 26837U, // VCMPSSZrrb_altk 18636U, // VCMPSSZrri_alt 26837U, // VCMPSSZrri_altk 21832U, // VCMPSSrm 21832U, // VCMPSSrm_Int 18636U, // VCMPSSrm_alt 18636U, // VCMPSSrr 18636U, // VCMPSSrr_Int 18636U, // VCMPSSrr_alt 0U, // VCOMISDZrm 0U, // VCOMISDZrm_Int 0U, // VCOMISDZrr 0U, // VCOMISDZrr_Int 0U, // VCOMISDZrrb 0U, // VCOMISDrm 0U, // VCOMISDrm_Int 0U, // VCOMISDrr 0U, // VCOMISDrr_Int 0U, // VCOMISSZrm 0U, // VCOMISSZrm_Int 0U, // VCOMISSZrr 0U, // VCOMISSZrr_Int 0U, // VCOMISSZrrb 0U, // VCOMISSrm 0U, // VCOMISSrm_Int 0U, // VCOMISSrr 0U, // VCOMISSrr_Int 0U, // VCOMPRESSPDZ128mr 49U, // VCOMPRESSPDZ128mrk 0U, // VCOMPRESSPDZ128rr 405U, // VCOMPRESSPDZ128rrk 461U, // VCOMPRESSPDZ128rrkz 0U, // VCOMPRESSPDZ256mr 49U, // VCOMPRESSPDZ256mrk 0U, // VCOMPRESSPDZ256rr 405U, // VCOMPRESSPDZ256rrk 461U, // VCOMPRESSPDZ256rrkz 0U, // VCOMPRESSPDZmr 49U, // VCOMPRESSPDZmrk 0U, // VCOMPRESSPDZrr 405U, // VCOMPRESSPDZrrk 461U, // VCOMPRESSPDZrrkz 0U, // VCOMPRESSPSZ128mr 49U, // VCOMPRESSPSZ128mrk 0U, // VCOMPRESSPSZ128rr 405U, // VCOMPRESSPSZ128rrk 461U, // VCOMPRESSPSZ128rrkz 0U, // VCOMPRESSPSZ256mr 49U, // VCOMPRESSPSZ256mrk 0U, // VCOMPRESSPSZ256rr 405U, // VCOMPRESSPSZ256rrk 461U, // VCOMPRESSPSZ256rrkz 0U, // VCOMPRESSPSZmr 49U, // VCOMPRESSPSZmrk 0U, // VCOMPRESSPSZrr 405U, // VCOMPRESSPSZrrk 461U, // VCOMPRESSPSZrrkz 0U, // VCVTDQ2PDYrm 0U, // VCVTDQ2PDYrr 0U, // VCVTDQ2PDZ128rm 0U, // VCVTDQ2PDZ128rmb 3356U, // VCVTDQ2PDZ128rmbk 4444U, // VCVTDQ2PDZ128rmbkz 3356U, // VCVTDQ2PDZ128rmk 4444U, // VCVTDQ2PDZ128rmkz 0U, // VCVTDQ2PDZ128rr 405U, // VCVTDQ2PDZ128rrk 461U, // VCVTDQ2PDZ128rrkz 0U, // VCVTDQ2PDZ256rm 0U, // VCVTDQ2PDZ256rmb 3356U, // VCVTDQ2PDZ256rmbk 4444U, // VCVTDQ2PDZ256rmbkz 405U, // VCVTDQ2PDZ256rmk 461U, // VCVTDQ2PDZ256rmkz 0U, // VCVTDQ2PDZ256rr 405U, // VCVTDQ2PDZ256rrk 461U, // VCVTDQ2PDZ256rrkz 0U, // VCVTDQ2PDZrm 0U, // VCVTDQ2PDZrmb 3356U, // VCVTDQ2PDZrmbk 4444U, // VCVTDQ2PDZrmbkz 405U, // VCVTDQ2PDZrmk 461U, // VCVTDQ2PDZrmkz 0U, // VCVTDQ2PDZrr 405U, // VCVTDQ2PDZrrk 461U, // VCVTDQ2PDZrrkz 0U, // VCVTDQ2PDrm 0U, // VCVTDQ2PDrr 0U, // VCVTDQ2PSYrm 0U, // VCVTDQ2PSYrr 0U, // VCVTDQ2PSZ128rm 0U, // VCVTDQ2PSZ128rmb 3356U, // VCVTDQ2PSZ128rmbk 4444U, // VCVTDQ2PSZ128rmbkz 405U, // VCVTDQ2PSZ128rmk 461U, // VCVTDQ2PSZ128rmkz 0U, // VCVTDQ2PSZ128rr 405U, // VCVTDQ2PSZ128rrk 461U, // VCVTDQ2PSZ128rrkz 0U, // VCVTDQ2PSZ256rm 0U, // VCVTDQ2PSZ256rmb 3356U, // VCVTDQ2PSZ256rmbk 4444U, // VCVTDQ2PSZ256rmbkz 405U, // VCVTDQ2PSZ256rmk 461U, // VCVTDQ2PSZ256rmkz 0U, // VCVTDQ2PSZ256rr 405U, // VCVTDQ2PSZ256rrk 461U, // VCVTDQ2PSZ256rrkz 0U, // VCVTDQ2PSZrm 0U, // VCVTDQ2PSZrmb 3356U, // VCVTDQ2PSZrmbk 4444U, // VCVTDQ2PSZrmbkz 405U, // VCVTDQ2PSZrmk 461U, // VCVTDQ2PSZrmkz 0U, // VCVTDQ2PSZrr 0U, // VCVTDQ2PSZrrb 405U, // VCVTDQ2PSZrrbk 461U, // VCVTDQ2PSZrrbkz 405U, // VCVTDQ2PSZrrk 461U, // VCVTDQ2PSZrrkz 0U, // VCVTDQ2PSrm 0U, // VCVTDQ2PSrr 0U, // VCVTPD2DQYrm 0U, // VCVTPD2DQYrr 0U, // VCVTPD2DQZ128rm 0U, // VCVTPD2DQZ128rmb 3356U, // VCVTPD2DQZ128rmbk 4444U, // VCVTPD2DQZ128rmbkz 405U, // VCVTPD2DQZ128rmk 461U, // VCVTPD2DQZ128rmkz 0U, // VCVTPD2DQZ128rr 405U, // VCVTPD2DQZ128rrk 461U, // VCVTPD2DQZ128rrkz 0U, // VCVTPD2DQZ256rm 0U, // VCVTPD2DQZ256rmb 3356U, // VCVTPD2DQZ256rmbk 4444U, // VCVTPD2DQZ256rmbkz 405U, // VCVTPD2DQZ256rmk 461U, // VCVTPD2DQZ256rmkz 0U, // VCVTPD2DQZ256rr 405U, // VCVTPD2DQZ256rrk 461U, // VCVTPD2DQZ256rrkz 0U, // VCVTPD2DQZrm 0U, // VCVTPD2DQZrmb 3356U, // VCVTPD2DQZrmbk 4444U, // VCVTPD2DQZrmbkz 405U, // VCVTPD2DQZrmk 461U, // VCVTPD2DQZrmkz 0U, // VCVTPD2DQZrr 0U, // VCVTPD2DQZrrb 405U, // VCVTPD2DQZrrbk 461U, // VCVTPD2DQZrrbkz 405U, // VCVTPD2DQZrrk 461U, // VCVTPD2DQZrrkz 0U, // VCVTPD2DQrm 0U, // VCVTPD2DQrr 0U, // VCVTPD2PSYrm 0U, // VCVTPD2PSYrr 0U, // VCVTPD2PSZ128rm 0U, // VCVTPD2PSZ128rmb 3356U, // VCVTPD2PSZ128rmbk 4444U, // VCVTPD2PSZ128rmbkz 405U, // VCVTPD2PSZ128rmk 461U, // VCVTPD2PSZ128rmkz 0U, // VCVTPD2PSZ128rr 405U, // VCVTPD2PSZ128rrk 461U, // VCVTPD2PSZ128rrkz 0U, // VCVTPD2PSZ256rm 0U, // VCVTPD2PSZ256rmb 3356U, // VCVTPD2PSZ256rmbk 4444U, // VCVTPD2PSZ256rmbkz 405U, // VCVTPD2PSZ256rmk 461U, // VCVTPD2PSZ256rmkz 0U, // VCVTPD2PSZ256rr 405U, // VCVTPD2PSZ256rrk 461U, // VCVTPD2PSZ256rrkz 0U, // VCVTPD2PSZrm 0U, // VCVTPD2PSZrmb 3356U, // VCVTPD2PSZrmbk 4444U, // VCVTPD2PSZrmbkz 405U, // VCVTPD2PSZrmk 461U, // VCVTPD2PSZrmkz 0U, // VCVTPD2PSZrr 0U, // VCVTPD2PSZrrb 405U, // VCVTPD2PSZrrbk 461U, // VCVTPD2PSZrrbkz 405U, // VCVTPD2PSZrrk 461U, // VCVTPD2PSZrrkz 0U, // VCVTPD2PSrm 0U, // VCVTPD2PSrr 0U, // VCVTPD2QQZ128rm 0U, // VCVTPD2QQZ128rmb 3356U, // VCVTPD2QQZ128rmbk 4444U, // VCVTPD2QQZ128rmbkz 405U, // VCVTPD2QQZ128rmk 461U, // VCVTPD2QQZ128rmkz 0U, // VCVTPD2QQZ128rr 405U, // VCVTPD2QQZ128rrk 461U, // VCVTPD2QQZ128rrkz 0U, // VCVTPD2QQZ256rm 0U, // VCVTPD2QQZ256rmb 3356U, // VCVTPD2QQZ256rmbk 4444U, // VCVTPD2QQZ256rmbkz 405U, // VCVTPD2QQZ256rmk 461U, // VCVTPD2QQZ256rmkz 0U, // VCVTPD2QQZ256rr 405U, // VCVTPD2QQZ256rrk 461U, // VCVTPD2QQZ256rrkz 0U, // VCVTPD2QQZrm 0U, // VCVTPD2QQZrmb 3356U, // VCVTPD2QQZrmbk 4444U, // VCVTPD2QQZrmbkz 405U, // VCVTPD2QQZrmk 461U, // VCVTPD2QQZrmkz 0U, // VCVTPD2QQZrr 0U, // VCVTPD2QQZrrb 405U, // VCVTPD2QQZrrbk 461U, // VCVTPD2QQZrrbkz 405U, // VCVTPD2QQZrrk 461U, // VCVTPD2QQZrrkz 0U, // VCVTPD2UDQZ128rm 0U, // VCVTPD2UDQZ128rmb 3356U, // VCVTPD2UDQZ128rmbk 4444U, // VCVTPD2UDQZ128rmbkz 405U, // VCVTPD2UDQZ128rmk 461U, // VCVTPD2UDQZ128rmkz 0U, // VCVTPD2UDQZ128rr 405U, // VCVTPD2UDQZ128rrk 461U, // VCVTPD2UDQZ128rrkz 0U, // VCVTPD2UDQZ256rm 0U, // VCVTPD2UDQZ256rmb 3356U, // VCVTPD2UDQZ256rmbk 4444U, // VCVTPD2UDQZ256rmbkz 405U, // VCVTPD2UDQZ256rmk 461U, // VCVTPD2UDQZ256rmkz 0U, // VCVTPD2UDQZ256rr 405U, // VCVTPD2UDQZ256rrk 461U, // VCVTPD2UDQZ256rrkz 0U, // VCVTPD2UDQZrm 0U, // VCVTPD2UDQZrmb 3356U, // VCVTPD2UDQZrmbk 4444U, // VCVTPD2UDQZrmbkz 405U, // VCVTPD2UDQZrmk 461U, // VCVTPD2UDQZrmkz 0U, // VCVTPD2UDQZrr 0U, // VCVTPD2UDQZrrb 405U, // VCVTPD2UDQZrrbk 461U, // VCVTPD2UDQZrrbkz 405U, // VCVTPD2UDQZrrk 461U, // VCVTPD2UDQZrrkz 0U, // VCVTPD2UQQZ128rm 0U, // VCVTPD2UQQZ128rmb 3356U, // VCVTPD2UQQZ128rmbk 4444U, // VCVTPD2UQQZ128rmbkz 405U, // VCVTPD2UQQZ128rmk 461U, // VCVTPD2UQQZ128rmkz 0U, // VCVTPD2UQQZ128rr 405U, // VCVTPD2UQQZ128rrk 461U, // VCVTPD2UQQZ128rrkz 0U, // VCVTPD2UQQZ256rm 0U, // VCVTPD2UQQZ256rmb 3356U, // VCVTPD2UQQZ256rmbk 4444U, // VCVTPD2UQQZ256rmbkz 405U, // VCVTPD2UQQZ256rmk 461U, // VCVTPD2UQQZ256rmkz 0U, // VCVTPD2UQQZ256rr 405U, // VCVTPD2UQQZ256rrk 461U, // VCVTPD2UQQZ256rrkz 0U, // VCVTPD2UQQZrm 0U, // VCVTPD2UQQZrmb 3356U, // VCVTPD2UQQZrmbk 4444U, // VCVTPD2UQQZrmbkz 405U, // VCVTPD2UQQZrmk 461U, // VCVTPD2UQQZrmkz 0U, // VCVTPD2UQQZrr 0U, // VCVTPD2UQQZrrb 405U, // VCVTPD2UQQZrrbk 461U, // VCVTPD2UQQZrrbkz 405U, // VCVTPD2UQQZrrk 461U, // VCVTPD2UQQZrrkz 0U, // VCVTPH2PSYrm 0U, // VCVTPH2PSYrr 0U, // VCVTPH2PSZ128rm 3356U, // VCVTPH2PSZ128rmk 4444U, // VCVTPH2PSZ128rmkz 0U, // VCVTPH2PSZ128rr 405U, // VCVTPH2PSZ128rrk 461U, // VCVTPH2PSZ128rrkz 0U, // VCVTPH2PSZ256rm 405U, // VCVTPH2PSZ256rmk 461U, // VCVTPH2PSZ256rmkz 0U, // VCVTPH2PSZ256rr 405U, // VCVTPH2PSZ256rrk 461U, // VCVTPH2PSZ256rrkz 0U, // VCVTPH2PSZrm 405U, // VCVTPH2PSZrmk 461U, // VCVTPH2PSZrmkz 0U, // VCVTPH2PSZrr 0U, // VCVTPH2PSZrrb 405U, // VCVTPH2PSZrrbk 461U, // VCVTPH2PSZrrbkz 405U, // VCVTPH2PSZrrk 461U, // VCVTPH2PSZrrkz 0U, // VCVTPH2PSrm 0U, // VCVTPH2PSrr 0U, // VCVTPS2DQYrm 0U, // VCVTPS2DQYrr 0U, // VCVTPS2DQZ128rm 0U, // VCVTPS2DQZ128rmb 3356U, // VCVTPS2DQZ128rmbk 4444U, // VCVTPS2DQZ128rmbkz 405U, // VCVTPS2DQZ128rmk 461U, // VCVTPS2DQZ128rmkz 0U, // VCVTPS2DQZ128rr 405U, // VCVTPS2DQZ128rrk 461U, // VCVTPS2DQZ128rrkz 0U, // VCVTPS2DQZ256rm 0U, // VCVTPS2DQZ256rmb 3356U, // VCVTPS2DQZ256rmbk 4444U, // VCVTPS2DQZ256rmbkz 405U, // VCVTPS2DQZ256rmk 461U, // VCVTPS2DQZ256rmkz 0U, // VCVTPS2DQZ256rr 405U, // VCVTPS2DQZ256rrk 461U, // VCVTPS2DQZ256rrkz 0U, // VCVTPS2DQZrm 0U, // VCVTPS2DQZrmb 3356U, // VCVTPS2DQZrmbk 4444U, // VCVTPS2DQZrmbkz 405U, // VCVTPS2DQZrmk 461U, // VCVTPS2DQZrmkz 0U, // VCVTPS2DQZrr 0U, // VCVTPS2DQZrrb 405U, // VCVTPS2DQZrrbk 461U, // VCVTPS2DQZrrbkz 405U, // VCVTPS2DQZrrk 461U, // VCVTPS2DQZrrkz 0U, // VCVTPS2DQrm 0U, // VCVTPS2DQrr 0U, // VCVTPS2PDYrm 0U, // VCVTPS2PDYrr 0U, // VCVTPS2PDZ128rm 0U, // VCVTPS2PDZ128rmb 3356U, // VCVTPS2PDZ128rmbk 4444U, // VCVTPS2PDZ128rmbkz 3356U, // VCVTPS2PDZ128rmk 4444U, // VCVTPS2PDZ128rmkz 0U, // VCVTPS2PDZ128rr 405U, // VCVTPS2PDZ128rrk 461U, // VCVTPS2PDZ128rrkz 0U, // VCVTPS2PDZ256rm 0U, // VCVTPS2PDZ256rmb 3356U, // VCVTPS2PDZ256rmbk 4444U, // VCVTPS2PDZ256rmbkz 405U, // VCVTPS2PDZ256rmk 461U, // VCVTPS2PDZ256rmkz 0U, // VCVTPS2PDZ256rr 405U, // VCVTPS2PDZ256rrk 461U, // VCVTPS2PDZ256rrkz 0U, // VCVTPS2PDZrm 0U, // VCVTPS2PDZrmb 3356U, // VCVTPS2PDZrmbk 4444U, // VCVTPS2PDZrmbkz 405U, // VCVTPS2PDZrmk 461U, // VCVTPS2PDZrmkz 0U, // VCVTPS2PDZrr 0U, // VCVTPS2PDZrrb 405U, // VCVTPS2PDZrrbk 461U, // VCVTPS2PDZrrbkz 405U, // VCVTPS2PDZrrk 461U, // VCVTPS2PDZrrkz 0U, // VCVTPS2PDrm 0U, // VCVTPS2PDrr 2U, // VCVTPS2PHYmr 72U, // VCVTPS2PHYrr 2U, // VCVTPS2PHZ128mr 542U, // VCVTPS2PHZ128mrk 72U, // VCVTPS2PHZ128rr 133U, // VCVTPS2PHZ128rrk 9348U, // VCVTPS2PHZ128rrkz 2U, // VCVTPS2PHZ256mr 542U, // VCVTPS2PHZ256mrk 72U, // VCVTPS2PHZ256rr 133U, // VCVTPS2PHZ256rrk 9348U, // VCVTPS2PHZ256rrkz 2U, // VCVTPS2PHZmr 542U, // VCVTPS2PHZmrk 72U, // VCVTPS2PHZrr 72U, // VCVTPS2PHZrrb 133U, // VCVTPS2PHZrrbk 9348U, // VCVTPS2PHZrrbkz 133U, // VCVTPS2PHZrrk 9348U, // VCVTPS2PHZrrkz 2U, // VCVTPS2PHmr 72U, // VCVTPS2PHrr 0U, // VCVTPS2QQZ128rm 0U, // VCVTPS2QQZ128rmb 3356U, // VCVTPS2QQZ128rmbk 4444U, // VCVTPS2QQZ128rmbkz 3356U, // VCVTPS2QQZ128rmk 4444U, // VCVTPS2QQZ128rmkz 0U, // VCVTPS2QQZ128rr 405U, // VCVTPS2QQZ128rrk 461U, // VCVTPS2QQZ128rrkz 0U, // VCVTPS2QQZ256rm 0U, // VCVTPS2QQZ256rmb 3356U, // VCVTPS2QQZ256rmbk 4444U, // VCVTPS2QQZ256rmbkz 405U, // VCVTPS2QQZ256rmk 461U, // VCVTPS2QQZ256rmkz 0U, // VCVTPS2QQZ256rr 405U, // VCVTPS2QQZ256rrk 461U, // VCVTPS2QQZ256rrkz 0U, // VCVTPS2QQZrm 0U, // VCVTPS2QQZrmb 3356U, // VCVTPS2QQZrmbk 4444U, // VCVTPS2QQZrmbkz 405U, // VCVTPS2QQZrmk 461U, // VCVTPS2QQZrmkz 0U, // VCVTPS2QQZrr 0U, // VCVTPS2QQZrrb 405U, // VCVTPS2QQZrrbk 461U, // VCVTPS2QQZrrbkz 405U, // VCVTPS2QQZrrk 461U, // VCVTPS2QQZrrkz 0U, // VCVTPS2UDQZ128rm 0U, // VCVTPS2UDQZ128rmb 3356U, // VCVTPS2UDQZ128rmbk 4444U, // VCVTPS2UDQZ128rmbkz 405U, // VCVTPS2UDQZ128rmk 461U, // VCVTPS2UDQZ128rmkz 0U, // VCVTPS2UDQZ128rr 405U, // VCVTPS2UDQZ128rrk 461U, // VCVTPS2UDQZ128rrkz 0U, // VCVTPS2UDQZ256rm 0U, // VCVTPS2UDQZ256rmb 3356U, // VCVTPS2UDQZ256rmbk 4444U, // VCVTPS2UDQZ256rmbkz 405U, // VCVTPS2UDQZ256rmk 461U, // VCVTPS2UDQZ256rmkz 0U, // VCVTPS2UDQZ256rr 405U, // VCVTPS2UDQZ256rrk 461U, // VCVTPS2UDQZ256rrkz 0U, // VCVTPS2UDQZrm 0U, // VCVTPS2UDQZrmb 3356U, // VCVTPS2UDQZrmbk 4444U, // VCVTPS2UDQZrmbkz 405U, // VCVTPS2UDQZrmk 461U, // VCVTPS2UDQZrmkz 0U, // VCVTPS2UDQZrr 0U, // VCVTPS2UDQZrrb 405U, // VCVTPS2UDQZrrbk 461U, // VCVTPS2UDQZrrbkz 405U, // VCVTPS2UDQZrrk 461U, // VCVTPS2UDQZrrkz 0U, // VCVTPS2UQQZ128rm 0U, // VCVTPS2UQQZ128rmb 3356U, // VCVTPS2UQQZ128rmbk 4444U, // VCVTPS2UQQZ128rmbkz 3356U, // VCVTPS2UQQZ128rmk 4444U, // VCVTPS2UQQZ128rmkz 0U, // VCVTPS2UQQZ128rr 405U, // VCVTPS2UQQZ128rrk 461U, // VCVTPS2UQQZ128rrkz 0U, // VCVTPS2UQQZ256rm 0U, // VCVTPS2UQQZ256rmb 3356U, // VCVTPS2UQQZ256rmbk 4444U, // VCVTPS2UQQZ256rmbkz 405U, // VCVTPS2UQQZ256rmk 461U, // VCVTPS2UQQZ256rmkz 0U, // VCVTPS2UQQZ256rr 405U, // VCVTPS2UQQZ256rrk 461U, // VCVTPS2UQQZ256rrkz 0U, // VCVTPS2UQQZrm 0U, // VCVTPS2UQQZrmb 3356U, // VCVTPS2UQQZrmbk 4444U, // VCVTPS2UQQZrmbkz 405U, // VCVTPS2UQQZrmk 461U, // VCVTPS2UQQZrmkz 0U, // VCVTPS2UQQZrr 0U, // VCVTPS2UQQZrrb 405U, // VCVTPS2UQQZrrbk 461U, // VCVTPS2UQQZrrbkz 405U, // VCVTPS2UQQZrrk 461U, // VCVTPS2UQQZrrkz 0U, // VCVTQQ2PDZ128rm 0U, // VCVTQQ2PDZ128rmb 3356U, // VCVTQQ2PDZ128rmbk 4444U, // VCVTQQ2PDZ128rmbkz 405U, // VCVTQQ2PDZ128rmk 461U, // VCVTQQ2PDZ128rmkz 0U, // VCVTQQ2PDZ128rr 405U, // VCVTQQ2PDZ128rrk 461U, // VCVTQQ2PDZ128rrkz 0U, // VCVTQQ2PDZ256rm 0U, // VCVTQQ2PDZ256rmb 3356U, // VCVTQQ2PDZ256rmbk 4444U, // VCVTQQ2PDZ256rmbkz 405U, // VCVTQQ2PDZ256rmk 461U, // VCVTQQ2PDZ256rmkz 0U, // VCVTQQ2PDZ256rr 405U, // VCVTQQ2PDZ256rrk 461U, // VCVTQQ2PDZ256rrkz 0U, // VCVTQQ2PDZrm 0U, // VCVTQQ2PDZrmb 3356U, // VCVTQQ2PDZrmbk 4444U, // VCVTQQ2PDZrmbkz 405U, // VCVTQQ2PDZrmk 461U, // VCVTQQ2PDZrmkz 0U, // VCVTQQ2PDZrr 0U, // VCVTQQ2PDZrrb 405U, // VCVTQQ2PDZrrbk 461U, // VCVTQQ2PDZrrbkz 405U, // VCVTQQ2PDZrrk 461U, // VCVTQQ2PDZrrkz 0U, // VCVTQQ2PSZ128rm 0U, // VCVTQQ2PSZ128rmb 3356U, // VCVTQQ2PSZ128rmbk 4444U, // VCVTQQ2PSZ128rmbkz 405U, // VCVTQQ2PSZ128rmk 461U, // VCVTQQ2PSZ128rmkz 0U, // VCVTQQ2PSZ128rr 405U, // VCVTQQ2PSZ128rrk 461U, // VCVTQQ2PSZ128rrkz 0U, // VCVTQQ2PSZ256rm 0U, // VCVTQQ2PSZ256rmb 3356U, // VCVTQQ2PSZ256rmbk 4444U, // VCVTQQ2PSZ256rmbkz 405U, // VCVTQQ2PSZ256rmk 461U, // VCVTQQ2PSZ256rmkz 0U, // VCVTQQ2PSZ256rr 405U, // VCVTQQ2PSZ256rrk 461U, // VCVTQQ2PSZ256rrkz 0U, // VCVTQQ2PSZrm 0U, // VCVTQQ2PSZrmb 3356U, // VCVTQQ2PSZrmbk 4444U, // VCVTQQ2PSZrmbkz 405U, // VCVTQQ2PSZrmk 461U, // VCVTQQ2PSZrmkz 0U, // VCVTQQ2PSZrr 0U, // VCVTQQ2PSZrrb 405U, // VCVTQQ2PSZrrbk 461U, // VCVTQQ2PSZrrbkz 405U, // VCVTQQ2PSZrrk 461U, // VCVTQQ2PSZrrkz 0U, // VCVTSD2SI64Zrm_Int 0U, // VCVTSD2SI64Zrr_Int 0U, // VCVTSD2SI64Zrrb_Int 0U, // VCVTSD2SI64rm_Int 0U, // VCVTSD2SI64rr_Int 0U, // VCVTSD2SIZrm_Int 0U, // VCVTSD2SIZrr_Int 0U, // VCVTSD2SIZrrb_Int 0U, // VCVTSD2SIrm_Int 0U, // VCVTSD2SIrr_Int 72U, // VCVTSD2SSZrm 72U, // VCVTSD2SSZrm_Int 133U, // VCVTSD2SSZrm_Intk 9348U, // VCVTSD2SSZrm_Intkz 4U, // VCVTSD2SSZrr 4U, // VCVTSD2SSZrr_Int 0U, // VCVTSD2SSZrr_Intk 9348U, // VCVTSD2SSZrr_Intkz 4U, // VCVTSD2SSZrrb_Int 0U, // VCVTSD2SSZrrb_Intk 9348U, // VCVTSD2SSZrrb_Intkz 72U, // VCVTSD2SSrm 72U, // VCVTSD2SSrm_Int 4U, // VCVTSD2SSrr 4U, // VCVTSD2SSrr_Int 0U, // VCVTSD2USI64Zrm_Int 0U, // VCVTSD2USI64Zrr_Int 0U, // VCVTSD2USI64Zrrb_Int 0U, // VCVTSD2USIZrm_Int 0U, // VCVTSD2USIZrr_Int 0U, // VCVTSD2USIZrrb_Int 72U, // VCVTSI2SDZrm 72U, // VCVTSI2SDZrm_Int 4U, // VCVTSI2SDZrr 4U, // VCVTSI2SDZrr_Int 0U, // VCVTSI2SDZrrb_Int 72U, // VCVTSI2SDrm 72U, // VCVTSI2SDrm_Int 4U, // VCVTSI2SDrr 4U, // VCVTSI2SDrr_Int 72U, // VCVTSI2SSZrm 72U, // VCVTSI2SSZrm_Int 4U, // VCVTSI2SSZrr 4U, // VCVTSI2SSZrr_Int 0U, // VCVTSI2SSZrrb_Int 72U, // VCVTSI2SSrm 72U, // VCVTSI2SSrm_Int 4U, // VCVTSI2SSrr 4U, // VCVTSI2SSrr_Int 72U, // VCVTSI642SDZrm 72U, // VCVTSI642SDZrm_Int 4U, // VCVTSI642SDZrr 4U, // VCVTSI642SDZrr_Int 0U, // VCVTSI642SDZrrb_Int 72U, // VCVTSI642SDrm 72U, // VCVTSI642SDrm_Int 4U, // VCVTSI642SDrr 4U, // VCVTSI642SDrr_Int 72U, // VCVTSI642SSZrm 72U, // VCVTSI642SSZrm_Int 4U, // VCVTSI642SSZrr 4U, // VCVTSI642SSZrr_Int 0U, // VCVTSI642SSZrrb_Int 72U, // VCVTSI642SSrm 72U, // VCVTSI642SSrm_Int 4U, // VCVTSI642SSrr 4U, // VCVTSI642SSrr_Int 72U, // VCVTSS2SDZrm 72U, // VCVTSS2SDZrm_Int 133U, // VCVTSS2SDZrm_Intk 9348U, // VCVTSS2SDZrm_Intkz 4U, // VCVTSS2SDZrr 4U, // VCVTSS2SDZrr_Int 0U, // VCVTSS2SDZrr_Intk 9348U, // VCVTSS2SDZrr_Intkz 4U, // VCVTSS2SDZrrb_Int 0U, // VCVTSS2SDZrrb_Intk 9348U, // VCVTSS2SDZrrb_Intkz 72U, // VCVTSS2SDrm 72U, // VCVTSS2SDrm_Int 4U, // VCVTSS2SDrr 4U, // VCVTSS2SDrr_Int 0U, // VCVTSS2SI64Zrm_Int 0U, // VCVTSS2SI64Zrr_Int 0U, // VCVTSS2SI64Zrrb_Int 0U, // VCVTSS2SI64rm_Int 0U, // VCVTSS2SI64rr_Int 0U, // VCVTSS2SIZrm_Int 0U, // VCVTSS2SIZrr_Int 0U, // VCVTSS2SIZrrb_Int 0U, // VCVTSS2SIrm_Int 0U, // VCVTSS2SIrr_Int 0U, // VCVTSS2USI64Zrm_Int 0U, // VCVTSS2USI64Zrr_Int 0U, // VCVTSS2USI64Zrrb_Int 0U, // VCVTSS2USIZrm_Int 0U, // VCVTSS2USIZrr_Int 0U, // VCVTSS2USIZrrb_Int 0U, // VCVTTPD2DQYrm 0U, // VCVTTPD2DQYrr 0U, // VCVTTPD2DQZ128rm 0U, // VCVTTPD2DQZ128rmb 3356U, // VCVTTPD2DQZ128rmbk 4444U, // VCVTTPD2DQZ128rmbkz 405U, // VCVTTPD2DQZ128rmk 461U, // VCVTTPD2DQZ128rmkz 0U, // VCVTTPD2DQZ128rr 405U, // VCVTTPD2DQZ128rrk 461U, // VCVTTPD2DQZ128rrkz 0U, // VCVTTPD2DQZ256rm 0U, // VCVTTPD2DQZ256rmb 3356U, // VCVTTPD2DQZ256rmbk 4444U, // VCVTTPD2DQZ256rmbkz 405U, // VCVTTPD2DQZ256rmk 461U, // VCVTTPD2DQZ256rmkz 0U, // VCVTTPD2DQZ256rr 405U, // VCVTTPD2DQZ256rrk 461U, // VCVTTPD2DQZ256rrkz 0U, // VCVTTPD2DQZrm 0U, // VCVTTPD2DQZrmb 3356U, // VCVTTPD2DQZrmbk 4444U, // VCVTTPD2DQZrmbkz 405U, // VCVTTPD2DQZrmk 461U, // VCVTTPD2DQZrmkz 0U, // VCVTTPD2DQZrr 0U, // VCVTTPD2DQZrrb 405U, // VCVTTPD2DQZrrbk 461U, // VCVTTPD2DQZrrbkz 405U, // VCVTTPD2DQZrrk 461U, // VCVTTPD2DQZrrkz 0U, // VCVTTPD2DQrm 0U, // VCVTTPD2DQrr 0U, // VCVTTPD2QQZ128rm 0U, // VCVTTPD2QQZ128rmb 3356U, // VCVTTPD2QQZ128rmbk 4444U, // VCVTTPD2QQZ128rmbkz 405U, // VCVTTPD2QQZ128rmk 461U, // VCVTTPD2QQZ128rmkz 0U, // VCVTTPD2QQZ128rr 405U, // VCVTTPD2QQZ128rrk 461U, // VCVTTPD2QQZ128rrkz 0U, // VCVTTPD2QQZ256rm 0U, // VCVTTPD2QQZ256rmb 3356U, // VCVTTPD2QQZ256rmbk 4444U, // VCVTTPD2QQZ256rmbkz 405U, // VCVTTPD2QQZ256rmk 461U, // VCVTTPD2QQZ256rmkz 0U, // VCVTTPD2QQZ256rr 405U, // VCVTTPD2QQZ256rrk 461U, // VCVTTPD2QQZ256rrkz 0U, // VCVTTPD2QQZrm 0U, // VCVTTPD2QQZrmb 3356U, // VCVTTPD2QQZrmbk 4444U, // VCVTTPD2QQZrmbkz 405U, // VCVTTPD2QQZrmk 461U, // VCVTTPD2QQZrmkz 0U, // VCVTTPD2QQZrr 0U, // VCVTTPD2QQZrrb 405U, // VCVTTPD2QQZrrbk 461U, // VCVTTPD2QQZrrbkz 405U, // VCVTTPD2QQZrrk 461U, // VCVTTPD2QQZrrkz 0U, // VCVTTPD2UDQZ128rm 0U, // VCVTTPD2UDQZ128rmb 3356U, // VCVTTPD2UDQZ128rmbk 4444U, // VCVTTPD2UDQZ128rmbkz 405U, // VCVTTPD2UDQZ128rmk 461U, // VCVTTPD2UDQZ128rmkz 0U, // VCVTTPD2UDQZ128rr 405U, // VCVTTPD2UDQZ128rrk 461U, // VCVTTPD2UDQZ128rrkz 0U, // VCVTTPD2UDQZ256rm 0U, // VCVTTPD2UDQZ256rmb 3356U, // VCVTTPD2UDQZ256rmbk 4444U, // VCVTTPD2UDQZ256rmbkz 405U, // VCVTTPD2UDQZ256rmk 461U, // VCVTTPD2UDQZ256rmkz 0U, // VCVTTPD2UDQZ256rr 405U, // VCVTTPD2UDQZ256rrk 461U, // VCVTTPD2UDQZ256rrkz 0U, // VCVTTPD2UDQZrm 0U, // VCVTTPD2UDQZrmb 3356U, // VCVTTPD2UDQZrmbk 4444U, // VCVTTPD2UDQZrmbkz 405U, // VCVTTPD2UDQZrmk 461U, // VCVTTPD2UDQZrmkz 0U, // VCVTTPD2UDQZrr 0U, // VCVTTPD2UDQZrrb 405U, // VCVTTPD2UDQZrrbk 461U, // VCVTTPD2UDQZrrbkz 405U, // VCVTTPD2UDQZrrk 461U, // VCVTTPD2UDQZrrkz 0U, // VCVTTPD2UQQZ128rm 0U, // VCVTTPD2UQQZ128rmb 3356U, // VCVTTPD2UQQZ128rmbk 4444U, // VCVTTPD2UQQZ128rmbkz 405U, // VCVTTPD2UQQZ128rmk 461U, // VCVTTPD2UQQZ128rmkz 0U, // VCVTTPD2UQQZ128rr 405U, // VCVTTPD2UQQZ128rrk 461U, // VCVTTPD2UQQZ128rrkz 0U, // VCVTTPD2UQQZ256rm 0U, // VCVTTPD2UQQZ256rmb 3356U, // VCVTTPD2UQQZ256rmbk 4444U, // VCVTTPD2UQQZ256rmbkz 405U, // VCVTTPD2UQQZ256rmk 461U, // VCVTTPD2UQQZ256rmkz 0U, // VCVTTPD2UQQZ256rr 405U, // VCVTTPD2UQQZ256rrk 461U, // VCVTTPD2UQQZ256rrkz 0U, // VCVTTPD2UQQZrm 0U, // VCVTTPD2UQQZrmb 3356U, // VCVTTPD2UQQZrmbk 4444U, // VCVTTPD2UQQZrmbkz 405U, // VCVTTPD2UQQZrmk 461U, // VCVTTPD2UQQZrmkz 0U, // VCVTTPD2UQQZrr 0U, // VCVTTPD2UQQZrrb 405U, // VCVTTPD2UQQZrrbk 461U, // VCVTTPD2UQQZrrbkz 405U, // VCVTTPD2UQQZrrk 461U, // VCVTTPD2UQQZrrkz 0U, // VCVTTPS2DQYrm 0U, // VCVTTPS2DQYrr 0U, // VCVTTPS2DQZ128rm 0U, // VCVTTPS2DQZ128rmb 3356U, // VCVTTPS2DQZ128rmbk 4444U, // VCVTTPS2DQZ128rmbkz 405U, // VCVTTPS2DQZ128rmk 461U, // VCVTTPS2DQZ128rmkz 0U, // VCVTTPS2DQZ128rr 405U, // VCVTTPS2DQZ128rrk 461U, // VCVTTPS2DQZ128rrkz 0U, // VCVTTPS2DQZ256rm 0U, // VCVTTPS2DQZ256rmb 3356U, // VCVTTPS2DQZ256rmbk 4444U, // VCVTTPS2DQZ256rmbkz 405U, // VCVTTPS2DQZ256rmk 461U, // VCVTTPS2DQZ256rmkz 0U, // VCVTTPS2DQZ256rr 405U, // VCVTTPS2DQZ256rrk 461U, // VCVTTPS2DQZ256rrkz 0U, // VCVTTPS2DQZrm 0U, // VCVTTPS2DQZrmb 3356U, // VCVTTPS2DQZrmbk 4444U, // VCVTTPS2DQZrmbkz 405U, // VCVTTPS2DQZrmk 461U, // VCVTTPS2DQZrmkz 0U, // VCVTTPS2DQZrr 0U, // VCVTTPS2DQZrrb 405U, // VCVTTPS2DQZrrbk 461U, // VCVTTPS2DQZrrbkz 405U, // VCVTTPS2DQZrrk 461U, // VCVTTPS2DQZrrkz 0U, // VCVTTPS2DQrm 0U, // VCVTTPS2DQrr 0U, // VCVTTPS2QQZ128rm 0U, // VCVTTPS2QQZ128rmb 3356U, // VCVTTPS2QQZ128rmbk 4444U, // VCVTTPS2QQZ128rmbkz 3356U, // VCVTTPS2QQZ128rmk 4444U, // VCVTTPS2QQZ128rmkz 0U, // VCVTTPS2QQZ128rr 405U, // VCVTTPS2QQZ128rrk 461U, // VCVTTPS2QQZ128rrkz 0U, // VCVTTPS2QQZ256rm 0U, // VCVTTPS2QQZ256rmb 3356U, // VCVTTPS2QQZ256rmbk 4444U, // VCVTTPS2QQZ256rmbkz 405U, // VCVTTPS2QQZ256rmk 461U, // VCVTTPS2QQZ256rmkz 0U, // VCVTTPS2QQZ256rr 405U, // VCVTTPS2QQZ256rrk 461U, // VCVTTPS2QQZ256rrkz 0U, // VCVTTPS2QQZrm 0U, // VCVTTPS2QQZrmb 3356U, // VCVTTPS2QQZrmbk 4444U, // VCVTTPS2QQZrmbkz 405U, // VCVTTPS2QQZrmk 461U, // VCVTTPS2QQZrmkz 0U, // VCVTTPS2QQZrr 0U, // VCVTTPS2QQZrrb 405U, // VCVTTPS2QQZrrbk 461U, // VCVTTPS2QQZrrbkz 405U, // VCVTTPS2QQZrrk 461U, // VCVTTPS2QQZrrkz 0U, // VCVTTPS2UDQZ128rm 0U, // VCVTTPS2UDQZ128rmb 3356U, // VCVTTPS2UDQZ128rmbk 4444U, // VCVTTPS2UDQZ128rmbkz 405U, // VCVTTPS2UDQZ128rmk 461U, // VCVTTPS2UDQZ128rmkz 0U, // VCVTTPS2UDQZ128rr 405U, // VCVTTPS2UDQZ128rrk 461U, // VCVTTPS2UDQZ128rrkz 0U, // VCVTTPS2UDQZ256rm 0U, // VCVTTPS2UDQZ256rmb 3356U, // VCVTTPS2UDQZ256rmbk 4444U, // VCVTTPS2UDQZ256rmbkz 405U, // VCVTTPS2UDQZ256rmk 461U, // VCVTTPS2UDQZ256rmkz 0U, // VCVTTPS2UDQZ256rr 405U, // VCVTTPS2UDQZ256rrk 461U, // VCVTTPS2UDQZ256rrkz 0U, // VCVTTPS2UDQZrm 0U, // VCVTTPS2UDQZrmb 3356U, // VCVTTPS2UDQZrmbk 4444U, // VCVTTPS2UDQZrmbkz 405U, // VCVTTPS2UDQZrmk 461U, // VCVTTPS2UDQZrmkz 0U, // VCVTTPS2UDQZrr 0U, // VCVTTPS2UDQZrrb 405U, // VCVTTPS2UDQZrrbk 461U, // VCVTTPS2UDQZrrbkz 405U, // VCVTTPS2UDQZrrk 461U, // VCVTTPS2UDQZrrkz 0U, // VCVTTPS2UQQZ128rm 0U, // VCVTTPS2UQQZ128rmb 3356U, // VCVTTPS2UQQZ128rmbk 4444U, // VCVTTPS2UQQZ128rmbkz 3356U, // VCVTTPS2UQQZ128rmk 4444U, // VCVTTPS2UQQZ128rmkz 0U, // VCVTTPS2UQQZ128rr 405U, // VCVTTPS2UQQZ128rrk 461U, // VCVTTPS2UQQZ128rrkz 0U, // VCVTTPS2UQQZ256rm 0U, // VCVTTPS2UQQZ256rmb 3356U, // VCVTTPS2UQQZ256rmbk 4444U, // VCVTTPS2UQQZ256rmbkz 405U, // VCVTTPS2UQQZ256rmk 461U, // VCVTTPS2UQQZ256rmkz 0U, // VCVTTPS2UQQZ256rr 405U, // VCVTTPS2UQQZ256rrk 461U, // VCVTTPS2UQQZ256rrkz 0U, // VCVTTPS2UQQZrm 0U, // VCVTTPS2UQQZrmb 3356U, // VCVTTPS2UQQZrmbk 4444U, // VCVTTPS2UQQZrmbkz 405U, // VCVTTPS2UQQZrmk 461U, // VCVTTPS2UQQZrmkz 0U, // VCVTTPS2UQQZrr 0U, // VCVTTPS2UQQZrrb 405U, // VCVTTPS2UQQZrrbk 461U, // VCVTTPS2UQQZrrbkz 405U, // VCVTTPS2UQQZrrk 461U, // VCVTTPS2UQQZrrkz 0U, // VCVTTSD2SI64Zrm 0U, // VCVTTSD2SI64Zrm_Int 0U, // VCVTTSD2SI64Zrr 0U, // VCVTTSD2SI64Zrr_Int 0U, // VCVTTSD2SI64Zrrb_Int 0U, // VCVTTSD2SI64rm 0U, // VCVTTSD2SI64rm_Int 0U, // VCVTTSD2SI64rr 0U, // VCVTTSD2SI64rr_Int 0U, // VCVTTSD2SIZrm 0U, // VCVTTSD2SIZrm_Int 0U, // VCVTTSD2SIZrr 0U, // VCVTTSD2SIZrr_Int 0U, // VCVTTSD2SIZrrb_Int 0U, // VCVTTSD2SIrm 0U, // VCVTTSD2SIrm_Int 0U, // VCVTTSD2SIrr 0U, // VCVTTSD2SIrr_Int 0U, // VCVTTSD2USI64Zrm 0U, // VCVTTSD2USI64Zrm_Int 0U, // VCVTTSD2USI64Zrr 0U, // VCVTTSD2USI64Zrr_Int 0U, // VCVTTSD2USI64Zrrb_Int 0U, // VCVTTSD2USIZrm 0U, // VCVTTSD2USIZrm_Int 0U, // VCVTTSD2USIZrr 0U, // VCVTTSD2USIZrr_Int 0U, // VCVTTSD2USIZrrb_Int 0U, // VCVTTSS2SI64Zrm 0U, // VCVTTSS2SI64Zrm_Int 0U, // VCVTTSS2SI64Zrr 0U, // VCVTTSS2SI64Zrr_Int 0U, // VCVTTSS2SI64Zrrb_Int 0U, // VCVTTSS2SI64rm 0U, // VCVTTSS2SI64rm_Int 0U, // VCVTTSS2SI64rr 0U, // VCVTTSS2SI64rr_Int 0U, // VCVTTSS2SIZrm 0U, // VCVTTSS2SIZrm_Int 0U, // VCVTTSS2SIZrr 0U, // VCVTTSS2SIZrr_Int 0U, // VCVTTSS2SIZrrb_Int 0U, // VCVTTSS2SIrm 0U, // VCVTTSS2SIrm_Int 0U, // VCVTTSS2SIrr 0U, // VCVTTSS2SIrr_Int 0U, // VCVTTSS2USI64Zrm 0U, // VCVTTSS2USI64Zrm_Int 0U, // VCVTTSS2USI64Zrr 0U, // VCVTTSS2USI64Zrr_Int 0U, // VCVTTSS2USI64Zrrb_Int 0U, // VCVTTSS2USIZrm 0U, // VCVTTSS2USIZrm_Int 0U, // VCVTTSS2USIZrr 0U, // VCVTTSS2USIZrr_Int 0U, // VCVTTSS2USIZrrb_Int 0U, // VCVTUDQ2PDZ128rm 0U, // VCVTUDQ2PDZ128rmb 3356U, // VCVTUDQ2PDZ128rmbk 4444U, // VCVTUDQ2PDZ128rmbkz 3356U, // VCVTUDQ2PDZ128rmk 4444U, // VCVTUDQ2PDZ128rmkz 0U, // VCVTUDQ2PDZ128rr 405U, // VCVTUDQ2PDZ128rrk 461U, // VCVTUDQ2PDZ128rrkz 0U, // VCVTUDQ2PDZ256rm 0U, // VCVTUDQ2PDZ256rmb 3356U, // VCVTUDQ2PDZ256rmbk 4444U, // VCVTUDQ2PDZ256rmbkz 405U, // VCVTUDQ2PDZ256rmk 461U, // VCVTUDQ2PDZ256rmkz 0U, // VCVTUDQ2PDZ256rr 405U, // VCVTUDQ2PDZ256rrk 461U, // VCVTUDQ2PDZ256rrkz 0U, // VCVTUDQ2PDZrm 0U, // VCVTUDQ2PDZrmb 3356U, // VCVTUDQ2PDZrmbk 4444U, // VCVTUDQ2PDZrmbkz 405U, // VCVTUDQ2PDZrmk 461U, // VCVTUDQ2PDZrmkz 0U, // VCVTUDQ2PDZrr 405U, // VCVTUDQ2PDZrrk 461U, // VCVTUDQ2PDZrrkz 0U, // VCVTUDQ2PSZ128rm 0U, // VCVTUDQ2PSZ128rmb 3356U, // VCVTUDQ2PSZ128rmbk 4444U, // VCVTUDQ2PSZ128rmbkz 405U, // VCVTUDQ2PSZ128rmk 461U, // VCVTUDQ2PSZ128rmkz 0U, // VCVTUDQ2PSZ128rr 405U, // VCVTUDQ2PSZ128rrk 461U, // VCVTUDQ2PSZ128rrkz 0U, // VCVTUDQ2PSZ256rm 0U, // VCVTUDQ2PSZ256rmb 3356U, // VCVTUDQ2PSZ256rmbk 4444U, // VCVTUDQ2PSZ256rmbkz 405U, // VCVTUDQ2PSZ256rmk 461U, // VCVTUDQ2PSZ256rmkz 0U, // VCVTUDQ2PSZ256rr 405U, // VCVTUDQ2PSZ256rrk 461U, // VCVTUDQ2PSZ256rrkz 0U, // VCVTUDQ2PSZrm 0U, // VCVTUDQ2PSZrmb 3356U, // VCVTUDQ2PSZrmbk 4444U, // VCVTUDQ2PSZrmbkz 405U, // VCVTUDQ2PSZrmk 461U, // VCVTUDQ2PSZrmkz 0U, // VCVTUDQ2PSZrr 0U, // VCVTUDQ2PSZrrb 405U, // VCVTUDQ2PSZrrbk 461U, // VCVTUDQ2PSZrrbkz 405U, // VCVTUDQ2PSZrrk 461U, // VCVTUDQ2PSZrrkz 0U, // VCVTUQQ2PDZ128rm 0U, // VCVTUQQ2PDZ128rmb 3356U, // VCVTUQQ2PDZ128rmbk 4444U, // VCVTUQQ2PDZ128rmbkz 405U, // VCVTUQQ2PDZ128rmk 461U, // VCVTUQQ2PDZ128rmkz 0U, // VCVTUQQ2PDZ128rr 405U, // VCVTUQQ2PDZ128rrk 461U, // VCVTUQQ2PDZ128rrkz 0U, // VCVTUQQ2PDZ256rm 0U, // VCVTUQQ2PDZ256rmb 3356U, // VCVTUQQ2PDZ256rmbk 4444U, // VCVTUQQ2PDZ256rmbkz 405U, // VCVTUQQ2PDZ256rmk 461U, // VCVTUQQ2PDZ256rmkz 0U, // VCVTUQQ2PDZ256rr 405U, // VCVTUQQ2PDZ256rrk 461U, // VCVTUQQ2PDZ256rrkz 0U, // VCVTUQQ2PDZrm 0U, // VCVTUQQ2PDZrmb 3356U, // VCVTUQQ2PDZrmbk 4444U, // VCVTUQQ2PDZrmbkz 405U, // VCVTUQQ2PDZrmk 461U, // VCVTUQQ2PDZrmkz 0U, // VCVTUQQ2PDZrr 0U, // VCVTUQQ2PDZrrb 405U, // VCVTUQQ2PDZrrbk 461U, // VCVTUQQ2PDZrrbkz 405U, // VCVTUQQ2PDZrrk 461U, // VCVTUQQ2PDZrrkz 0U, // VCVTUQQ2PSZ128rm 0U, // VCVTUQQ2PSZ128rmb 3356U, // VCVTUQQ2PSZ128rmbk 4444U, // VCVTUQQ2PSZ128rmbkz 405U, // VCVTUQQ2PSZ128rmk 461U, // VCVTUQQ2PSZ128rmkz 0U, // VCVTUQQ2PSZ128rr 405U, // VCVTUQQ2PSZ128rrk 461U, // VCVTUQQ2PSZ128rrkz 0U, // VCVTUQQ2PSZ256rm 0U, // VCVTUQQ2PSZ256rmb 3356U, // VCVTUQQ2PSZ256rmbk 4444U, // VCVTUQQ2PSZ256rmbkz 405U, // VCVTUQQ2PSZ256rmk 461U, // VCVTUQQ2PSZ256rmkz 0U, // VCVTUQQ2PSZ256rr 405U, // VCVTUQQ2PSZ256rrk 461U, // VCVTUQQ2PSZ256rrkz 0U, // VCVTUQQ2PSZrm 0U, // VCVTUQQ2PSZrmb 3356U, // VCVTUQQ2PSZrmbk 4444U, // VCVTUQQ2PSZrmbkz 405U, // VCVTUQQ2PSZrmk 461U, // VCVTUQQ2PSZrmkz 0U, // VCVTUQQ2PSZrr 0U, // VCVTUQQ2PSZrrb 405U, // VCVTUQQ2PSZrrbk 461U, // VCVTUQQ2PSZrrbkz 405U, // VCVTUQQ2PSZrrk 461U, // VCVTUQQ2PSZrrkz 72U, // VCVTUSI2SDZrm 72U, // VCVTUSI2SDZrm_Int 4U, // VCVTUSI2SDZrr 4U, // VCVTUSI2SDZrr_Int 72U, // VCVTUSI2SSZrm 72U, // VCVTUSI2SSZrm_Int 4U, // VCVTUSI2SSZrr 4U, // VCVTUSI2SSZrr_Int 0U, // VCVTUSI2SSZrrb_Int 72U, // VCVTUSI642SDZrm 72U, // VCVTUSI642SDZrm_Int 4U, // VCVTUSI642SDZrr 4U, // VCVTUSI642SDZrr_Int 0U, // VCVTUSI642SDZrrb_Int 72U, // VCVTUSI642SSZrm 72U, // VCVTUSI642SSZrm_Int 4U, // VCVTUSI642SSZrr 4U, // VCVTUSI642SSZrr_Int 0U, // VCVTUSI642SSZrrb_Int 72U, // VDBPSADBWZ128rmi 1U, // VDBPSADBWZ128rmik 9348U, // VDBPSADBWZ128rmikz 18636U, // VDBPSADBWZ128rri 25U, // VDBPSADBWZ128rrik 26837U, // VDBPSADBWZ128rrikz 72U, // VDBPSADBWZ256rmi 1U, // VDBPSADBWZ256rmik 9348U, // VDBPSADBWZ256rmikz 18636U, // VDBPSADBWZ256rri 25U, // VDBPSADBWZ256rrik 26837U, // VDBPSADBWZ256rrikz 72U, // VDBPSADBWZrmi 1U, // VDBPSADBWZrmik 9348U, // VDBPSADBWZrmikz 18636U, // VDBPSADBWZrri 25U, // VDBPSADBWZrrik 26837U, // VDBPSADBWZrrikz 4U, // VDIVPDYrm 4U, // VDIVPDYrr 4U, // VDIVPDZ128rm 72U, // VDIVPDZ128rmb 133U, // VDIVPDZ128rmbk 9348U, // VDIVPDZ128rmbkz 0U, // VDIVPDZ128rmk 9348U, // VDIVPDZ128rmkz 4U, // VDIVPDZ128rr 0U, // VDIVPDZ128rrk 9348U, // VDIVPDZ128rrkz 4U, // VDIVPDZ256rm 72U, // VDIVPDZ256rmb 133U, // VDIVPDZ256rmbk 9348U, // VDIVPDZ256rmbkz 0U, // VDIVPDZ256rmk 9348U, // VDIVPDZ256rmkz 4U, // VDIVPDZ256rr 0U, // VDIVPDZ256rrk 9348U, // VDIVPDZ256rrkz 4U, // VDIVPDZrm 72U, // VDIVPDZrmb 133U, // VDIVPDZrmbk 9348U, // VDIVPDZrmbkz 0U, // VDIVPDZrmk 9348U, // VDIVPDZrmkz 4U, // VDIVPDZrr 4U, // VDIVPDZrrb 0U, // VDIVPDZrrbk 9348U, // VDIVPDZrrbkz 0U, // VDIVPDZrrk 9348U, // VDIVPDZrrkz 4U, // VDIVPDrm 4U, // VDIVPDrr 4U, // VDIVPSYrm 4U, // VDIVPSYrr 4U, // VDIVPSZ128rm 72U, // VDIVPSZ128rmb 133U, // VDIVPSZ128rmbk 9348U, // VDIVPSZ128rmbkz 0U, // VDIVPSZ128rmk 9348U, // VDIVPSZ128rmkz 4U, // VDIVPSZ128rr 0U, // VDIVPSZ128rrk 9348U, // VDIVPSZ128rrkz 4U, // VDIVPSZ256rm 72U, // VDIVPSZ256rmb 133U, // VDIVPSZ256rmbk 9348U, // VDIVPSZ256rmbkz 0U, // VDIVPSZ256rmk 9348U, // VDIVPSZ256rmkz 4U, // VDIVPSZ256rr 0U, // VDIVPSZ256rrk 9348U, // VDIVPSZ256rrkz 4U, // VDIVPSZrm 72U, // VDIVPSZrmb 133U, // VDIVPSZrmbk 9348U, // VDIVPSZrmbkz 0U, // VDIVPSZrmk 9348U, // VDIVPSZrmkz 4U, // VDIVPSZrr 4U, // VDIVPSZrrb 0U, // VDIVPSZrrbk 9348U, // VDIVPSZrrbkz 0U, // VDIVPSZrrk 9348U, // VDIVPSZrrkz 4U, // VDIVPSrm 4U, // VDIVPSrr 72U, // VDIVSDZrm 72U, // VDIVSDZrm_Int 133U, // VDIVSDZrm_Intk 9348U, // VDIVSDZrm_Intkz 4U, // VDIVSDZrr 4U, // VDIVSDZrr_Int 0U, // VDIVSDZrr_Intk 9348U, // VDIVSDZrr_Intkz 4U, // VDIVSDZrrb_Int 0U, // VDIVSDZrrb_Intk 9348U, // VDIVSDZrrb_Intkz 72U, // VDIVSDrm 72U, // VDIVSDrm_Int 4U, // VDIVSDrr 4U, // VDIVSDrr_Int 72U, // VDIVSSZrm 72U, // VDIVSSZrm_Int 133U, // VDIVSSZrm_Intk 9348U, // VDIVSSZrm_Intkz 4U, // VDIVSSZrr 4U, // VDIVSSZrr_Int 0U, // VDIVSSZrr_Intk 9348U, // VDIVSSZrr_Intkz 4U, // VDIVSSZrrb_Int 0U, // VDIVSSZrrb_Intk 9348U, // VDIVSSZrrb_Intkz 72U, // VDIVSSrm 72U, // VDIVSSrm_Int 4U, // VDIVSSrr 4U, // VDIVSSrr_Int 72U, // VDPPDrmi 18636U, // VDPPDrri 72U, // VDPPSYrmi 18636U, // VDPPSYrri 72U, // VDPPSrmi 18636U, // VDPPSrri 0U, // VERRm 0U, // VERRr 0U, // VERWm 0U, // VERWr 0U, // VEXP2PDZm 0U, // VEXP2PDZmb 3356U, // VEXP2PDZmbk 4444U, // VEXP2PDZmbkz 405U, // VEXP2PDZmk 461U, // VEXP2PDZmkz 0U, // VEXP2PDZr 0U, // VEXP2PDZrb 405U, // VEXP2PDZrbk 461U, // VEXP2PDZrbkz 405U, // VEXP2PDZrk 461U, // VEXP2PDZrkz 0U, // VEXP2PSZm 0U, // VEXP2PSZmb 3356U, // VEXP2PSZmbk 4444U, // VEXP2PSZmbkz 405U, // VEXP2PSZmk 461U, // VEXP2PSZmkz 0U, // VEXP2PSZr 0U, // VEXP2PSZrb 405U, // VEXP2PSZrbk 461U, // VEXP2PSZrbkz 405U, // VEXP2PSZrk 461U, // VEXP2PSZrkz 0U, // VEXPANDPDZ128rm 405U, // VEXPANDPDZ128rmk 461U, // VEXPANDPDZ128rmkz 0U, // VEXPANDPDZ128rr 405U, // VEXPANDPDZ128rrk 461U, // VEXPANDPDZ128rrkz 0U, // VEXPANDPDZ256rm 405U, // VEXPANDPDZ256rmk 461U, // VEXPANDPDZ256rmkz 0U, // VEXPANDPDZ256rr 405U, // VEXPANDPDZ256rrk 461U, // VEXPANDPDZ256rrkz 0U, // VEXPANDPDZrm 405U, // VEXPANDPDZrmk 461U, // VEXPANDPDZrmkz 0U, // VEXPANDPDZrr 405U, // VEXPANDPDZrrk 461U, // VEXPANDPDZrrkz 0U, // VEXPANDPSZ128rm 405U, // VEXPANDPSZ128rmk 461U, // VEXPANDPSZ128rmkz 0U, // VEXPANDPSZ128rr 405U, // VEXPANDPSZ128rrk 461U, // VEXPANDPSZ128rrkz 0U, // VEXPANDPSZ256rm 405U, // VEXPANDPSZ256rmk 461U, // VEXPANDPSZ256rmkz 0U, // VEXPANDPSZ256rr 405U, // VEXPANDPSZ256rrk 461U, // VEXPANDPSZ256rrkz 0U, // VEXPANDPSZrm 405U, // VEXPANDPSZrmk 461U, // VEXPANDPSZrmkz 0U, // VEXPANDPSZrr 405U, // VEXPANDPSZrrk 461U, // VEXPANDPSZrrkz 2U, // VEXTRACTF128mr 72U, // VEXTRACTF128rr 2U, // VEXTRACTF32x4Z256mr 542U, // VEXTRACTF32x4Z256mrk 72U, // VEXTRACTF32x4Z256rr 133U, // VEXTRACTF32x4Z256rrk 9348U, // VEXTRACTF32x4Z256rrkz 2U, // VEXTRACTF32x4Zmr 542U, // VEXTRACTF32x4Zmrk 72U, // VEXTRACTF32x4Zrr 133U, // VEXTRACTF32x4Zrrk 9348U, // VEXTRACTF32x4Zrrkz 2U, // VEXTRACTF32x8Zmr 542U, // VEXTRACTF32x8Zmrk 72U, // VEXTRACTF32x8Zrr 133U, // VEXTRACTF32x8Zrrk 9348U, // VEXTRACTF32x8Zrrkz 2U, // VEXTRACTF64x2Z256mr 542U, // VEXTRACTF64x2Z256mrk 72U, // VEXTRACTF64x2Z256rr 133U, // VEXTRACTF64x2Z256rrk 9348U, // VEXTRACTF64x2Z256rrkz 2U, // VEXTRACTF64x2Zmr 542U, // VEXTRACTF64x2Zmrk 72U, // VEXTRACTF64x2Zrr 133U, // VEXTRACTF64x2Zrrk 9348U, // VEXTRACTF64x2Zrrkz 2U, // VEXTRACTF64x4Zmr 542U, // VEXTRACTF64x4Zmrk 72U, // VEXTRACTF64x4Zrr 133U, // VEXTRACTF64x4Zrrk 9348U, // VEXTRACTF64x4Zrrkz 2U, // VEXTRACTI128mr 72U, // VEXTRACTI128rr 2U, // VEXTRACTI32x4Z256mr 542U, // VEXTRACTI32x4Z256mrk 72U, // VEXTRACTI32x4Z256rr 133U, // VEXTRACTI32x4Z256rrk 9348U, // VEXTRACTI32x4Z256rrkz 2U, // VEXTRACTI32x4Zmr 542U, // VEXTRACTI32x4Zmrk 72U, // VEXTRACTI32x4Zrr 133U, // VEXTRACTI32x4Zrrk 9348U, // VEXTRACTI32x4Zrrkz 2U, // VEXTRACTI32x8Zmr 542U, // VEXTRACTI32x8Zmrk 72U, // VEXTRACTI32x8Zrr 133U, // VEXTRACTI32x8Zrrk 9348U, // VEXTRACTI32x8Zrrkz 2U, // VEXTRACTI64x2Z256mr 542U, // VEXTRACTI64x2Z256mrk 72U, // VEXTRACTI64x2Z256rr 133U, // VEXTRACTI64x2Z256rrk 9348U, // VEXTRACTI64x2Z256rrkz 2U, // VEXTRACTI64x2Zmr 542U, // VEXTRACTI64x2Zmrk 72U, // VEXTRACTI64x2Zrr 133U, // VEXTRACTI64x2Zrrk 9348U, // VEXTRACTI64x2Zrrkz 2U, // VEXTRACTI64x4Zmr 542U, // VEXTRACTI64x4Zmrk 72U, // VEXTRACTI64x4Zrr 133U, // VEXTRACTI64x4Zrrk 9348U, // VEXTRACTI64x4Zrrkz 0U, // VEXTRACTPSZmr 72U, // VEXTRACTPSZrr 0U, // VEXTRACTPSmr 72U, // VEXTRACTPSrr 18645U, // VFIXUPIMMPDZ128rmbi 26833U, // VFIXUPIMMPDZ128rmbik 26833U, // VFIXUPIMMPDZ128rmbikz 4U, // VFIXUPIMMPDZ128rmi 1U, // VFIXUPIMMPDZ128rmik 2U, // VFIXUPIMMPDZ128rmikz 18645U, // VFIXUPIMMPDZ128rri 25U, // VFIXUPIMMPDZ128rrik 53U, // VFIXUPIMMPDZ128rrikz 18645U, // VFIXUPIMMPDZ256rmbi 26833U, // VFIXUPIMMPDZ256rmbik 26833U, // VFIXUPIMMPDZ256rmbikz 4U, // VFIXUPIMMPDZ256rmi 1U, // VFIXUPIMMPDZ256rmik 2U, // VFIXUPIMMPDZ256rmikz 18645U, // VFIXUPIMMPDZ256rri 25U, // VFIXUPIMMPDZ256rrik 53U, // VFIXUPIMMPDZ256rrikz 18645U, // VFIXUPIMMPDZrmbi 26833U, // VFIXUPIMMPDZrmbik 26833U, // VFIXUPIMMPDZrmbikz 4U, // VFIXUPIMMPDZrmi 1U, // VFIXUPIMMPDZrmik 2U, // VFIXUPIMMPDZrmikz 18645U, // VFIXUPIMMPDZrri 18645U, // VFIXUPIMMPDZrrib 25U, // VFIXUPIMMPDZrribk 53U, // VFIXUPIMMPDZrribkz 25U, // VFIXUPIMMPDZrrik 53U, // VFIXUPIMMPDZrrikz 18645U, // VFIXUPIMMPSZ128rmbi 26833U, // VFIXUPIMMPSZ128rmbik 26833U, // VFIXUPIMMPSZ128rmbikz 4U, // VFIXUPIMMPSZ128rmi 1U, // VFIXUPIMMPSZ128rmik 2U, // VFIXUPIMMPSZ128rmikz 18645U, // VFIXUPIMMPSZ128rri 25U, // VFIXUPIMMPSZ128rrik 53U, // VFIXUPIMMPSZ128rrikz 18645U, // VFIXUPIMMPSZ256rmbi 26833U, // VFIXUPIMMPSZ256rmbik 26833U, // VFIXUPIMMPSZ256rmbikz 4U, // VFIXUPIMMPSZ256rmi 1U, // VFIXUPIMMPSZ256rmik 2U, // VFIXUPIMMPSZ256rmikz 18645U, // VFIXUPIMMPSZ256rri 25U, // VFIXUPIMMPSZ256rrik 53U, // VFIXUPIMMPSZ256rrikz 18645U, // VFIXUPIMMPSZrmbi 26833U, // VFIXUPIMMPSZrmbik 26833U, // VFIXUPIMMPSZrmbikz 4U, // VFIXUPIMMPSZrmi 1U, // VFIXUPIMMPSZrmik 2U, // VFIXUPIMMPSZrmikz 18645U, // VFIXUPIMMPSZrri 18645U, // VFIXUPIMMPSZrrib 25U, // VFIXUPIMMPSZrribk 53U, // VFIXUPIMMPSZrribkz 25U, // VFIXUPIMMPSZrrik 53U, // VFIXUPIMMPSZrrikz 18644U, // VFIXUPIMMSDZrmi 26832U, // VFIXUPIMMSDZrmik 26832U, // VFIXUPIMMSDZrmikz 18645U, // VFIXUPIMMSDZrri 18645U, // VFIXUPIMMSDZrrib 25U, // VFIXUPIMMSDZrribk 53U, // VFIXUPIMMSDZrribkz 25U, // VFIXUPIMMSDZrrik 53U, // VFIXUPIMMSDZrrikz 18644U, // VFIXUPIMMSSZrmi 26832U, // VFIXUPIMMSSZrmik 26832U, // VFIXUPIMMSSZrmikz 18645U, // VFIXUPIMMSSZrri 18645U, // VFIXUPIMMSSZrrib 25U, // VFIXUPIMMSSZrribk 53U, // VFIXUPIMMSSZrribkz 25U, // VFIXUPIMMSSZrrik 53U, // VFIXUPIMMSSZrrikz 4U, // VFMADD132PDYm 4U, // VFMADD132PDYr 4U, // VFMADD132PDZ128m 4U, // VFMADD132PDZ128mb 133U, // VFMADD132PDZ128mbk 8325U, // VFMADD132PDZ128mbkz 0U, // VFMADD132PDZ128mk 0U, // VFMADD132PDZ128mkz 4U, // VFMADD132PDZ128r 0U, // VFMADD132PDZ128rk 0U, // VFMADD132PDZ128rkz 4U, // VFMADD132PDZ256m 4U, // VFMADD132PDZ256mb 133U, // VFMADD132PDZ256mbk 8325U, // VFMADD132PDZ256mbkz 0U, // VFMADD132PDZ256mk 0U, // VFMADD132PDZ256mkz 4U, // VFMADD132PDZ256r 0U, // VFMADD132PDZ256rk 0U, // VFMADD132PDZ256rkz 4U, // VFMADD132PDZm 4U, // VFMADD132PDZmb 133U, // VFMADD132PDZmbk 8325U, // VFMADD132PDZmbkz 0U, // VFMADD132PDZmk 0U, // VFMADD132PDZmkz 4U, // VFMADD132PDZr 4U, // VFMADD132PDZrb 0U, // VFMADD132PDZrbk 0U, // VFMADD132PDZrbkz 0U, // VFMADD132PDZrk 0U, // VFMADD132PDZrkz 4U, // VFMADD132PDm 4U, // VFMADD132PDr 4U, // VFMADD132PSYm 4U, // VFMADD132PSYr 4U, // VFMADD132PSZ128m 4U, // VFMADD132PSZ128mb 133U, // VFMADD132PSZ128mbk 8325U, // VFMADD132PSZ128mbkz 0U, // VFMADD132PSZ128mk 0U, // VFMADD132PSZ128mkz 4U, // VFMADD132PSZ128r 0U, // VFMADD132PSZ128rk 0U, // VFMADD132PSZ128rkz 4U, // VFMADD132PSZ256m 4U, // VFMADD132PSZ256mb 133U, // VFMADD132PSZ256mbk 8325U, // VFMADD132PSZ256mbkz 0U, // VFMADD132PSZ256mk 0U, // VFMADD132PSZ256mkz 4U, // VFMADD132PSZ256r 0U, // VFMADD132PSZ256rk 0U, // VFMADD132PSZ256rkz 4U, // VFMADD132PSZm 4U, // VFMADD132PSZmb 133U, // VFMADD132PSZmbk 8325U, // VFMADD132PSZmbkz 0U, // VFMADD132PSZmk 0U, // VFMADD132PSZmkz 4U, // VFMADD132PSZr 4U, // VFMADD132PSZrb 0U, // VFMADD132PSZrbk 0U, // VFMADD132PSZrbkz 0U, // VFMADD132PSZrk 0U, // VFMADD132PSZrkz 4U, // VFMADD132PSm 4U, // VFMADD132PSr 4U, // VFMADD132SDZm 4U, // VFMADD132SDZm_Int 133U, // VFMADD132SDZm_Intk 8325U, // VFMADD132SDZm_Intkz 4U, // VFMADD132SDZr 4U, // VFMADD132SDZr_Int 0U, // VFMADD132SDZr_Intk 0U, // VFMADD132SDZr_Intkz 4U, // VFMADD132SDZrb 4U, // VFMADD132SDZrb_Int 0U, // VFMADD132SDZrb_Intk 0U, // VFMADD132SDZrb_Intkz 4U, // VFMADD132SDm 4U, // VFMADD132SDm_Int 4U, // VFMADD132SDr 4U, // VFMADD132SDr_Int 4U, // VFMADD132SSZm 4U, // VFMADD132SSZm_Int 133U, // VFMADD132SSZm_Intk 8325U, // VFMADD132SSZm_Intkz 4U, // VFMADD132SSZr 4U, // VFMADD132SSZr_Int 0U, // VFMADD132SSZr_Intk 0U, // VFMADD132SSZr_Intkz 4U, // VFMADD132SSZrb 4U, // VFMADD132SSZrb_Int 0U, // VFMADD132SSZrb_Intk 0U, // VFMADD132SSZrb_Intkz 4U, // VFMADD132SSm 4U, // VFMADD132SSm_Int 4U, // VFMADD132SSr 4U, // VFMADD132SSr_Int 4U, // VFMADD213PDYm 4U, // VFMADD213PDYr 4U, // VFMADD213PDZ128m 4U, // VFMADD213PDZ128mb 133U, // VFMADD213PDZ128mbk 8325U, // VFMADD213PDZ128mbkz 0U, // VFMADD213PDZ128mk 0U, // VFMADD213PDZ128mkz 4U, // VFMADD213PDZ128r 0U, // VFMADD213PDZ128rk 0U, // VFMADD213PDZ128rkz 4U, // VFMADD213PDZ256m 4U, // VFMADD213PDZ256mb 133U, // VFMADD213PDZ256mbk 8325U, // VFMADD213PDZ256mbkz 0U, // VFMADD213PDZ256mk 0U, // VFMADD213PDZ256mkz 4U, // VFMADD213PDZ256r 0U, // VFMADD213PDZ256rk 0U, // VFMADD213PDZ256rkz 4U, // VFMADD213PDZm 4U, // VFMADD213PDZmb 133U, // VFMADD213PDZmbk 8325U, // VFMADD213PDZmbkz 0U, // VFMADD213PDZmk 0U, // VFMADD213PDZmkz 4U, // VFMADD213PDZr 4U, // VFMADD213PDZrb 0U, // VFMADD213PDZrbk 0U, // VFMADD213PDZrbkz 0U, // VFMADD213PDZrk 0U, // VFMADD213PDZrkz 4U, // VFMADD213PDm 4U, // VFMADD213PDr 4U, // VFMADD213PSYm 4U, // VFMADD213PSYr 4U, // VFMADD213PSZ128m 4U, // VFMADD213PSZ128mb 133U, // VFMADD213PSZ128mbk 8325U, // VFMADD213PSZ128mbkz 0U, // VFMADD213PSZ128mk 0U, // VFMADD213PSZ128mkz 4U, // VFMADD213PSZ128r 0U, // VFMADD213PSZ128rk 0U, // VFMADD213PSZ128rkz 4U, // VFMADD213PSZ256m 4U, // VFMADD213PSZ256mb 133U, // VFMADD213PSZ256mbk 8325U, // VFMADD213PSZ256mbkz 0U, // VFMADD213PSZ256mk 0U, // VFMADD213PSZ256mkz 4U, // VFMADD213PSZ256r 0U, // VFMADD213PSZ256rk 0U, // VFMADD213PSZ256rkz 4U, // VFMADD213PSZm 4U, // VFMADD213PSZmb 133U, // VFMADD213PSZmbk 8325U, // VFMADD213PSZmbkz 0U, // VFMADD213PSZmk 0U, // VFMADD213PSZmkz 4U, // VFMADD213PSZr 4U, // VFMADD213PSZrb 0U, // VFMADD213PSZrbk 0U, // VFMADD213PSZrbkz 0U, // VFMADD213PSZrk 0U, // VFMADD213PSZrkz 4U, // VFMADD213PSm 4U, // VFMADD213PSr 4U, // VFMADD213SDZm 4U, // VFMADD213SDZm_Int 133U, // VFMADD213SDZm_Intk 8325U, // VFMADD213SDZm_Intkz 4U, // VFMADD213SDZr 4U, // VFMADD213SDZr_Int 0U, // VFMADD213SDZr_Intk 0U, // VFMADD213SDZr_Intkz 4U, // VFMADD213SDZrb 4U, // VFMADD213SDZrb_Int 0U, // VFMADD213SDZrb_Intk 0U, // VFMADD213SDZrb_Intkz 4U, // VFMADD213SDm 4U, // VFMADD213SDm_Int 4U, // VFMADD213SDr 4U, // VFMADD213SDr_Int 4U, // VFMADD213SSZm 4U, // VFMADD213SSZm_Int 133U, // VFMADD213SSZm_Intk 8325U, // VFMADD213SSZm_Intkz 4U, // VFMADD213SSZr 4U, // VFMADD213SSZr_Int 0U, // VFMADD213SSZr_Intk 0U, // VFMADD213SSZr_Intkz 4U, // VFMADD213SSZrb 4U, // VFMADD213SSZrb_Int 0U, // VFMADD213SSZrb_Intk 0U, // VFMADD213SSZrb_Intkz 4U, // VFMADD213SSm 4U, // VFMADD213SSm_Int 4U, // VFMADD213SSr 4U, // VFMADD213SSr_Int 4U, // VFMADD231PDYm 4U, // VFMADD231PDYr 4U, // VFMADD231PDZ128m 4U, // VFMADD231PDZ128mb 133U, // VFMADD231PDZ128mbk 8325U, // VFMADD231PDZ128mbkz 0U, // VFMADD231PDZ128mk 0U, // VFMADD231PDZ128mkz 4U, // VFMADD231PDZ128r 0U, // VFMADD231PDZ128rk 0U, // VFMADD231PDZ128rkz 4U, // VFMADD231PDZ256m 4U, // VFMADD231PDZ256mb 133U, // VFMADD231PDZ256mbk 8325U, // VFMADD231PDZ256mbkz 0U, // VFMADD231PDZ256mk 0U, // VFMADD231PDZ256mkz 4U, // VFMADD231PDZ256r 0U, // VFMADD231PDZ256rk 0U, // VFMADD231PDZ256rkz 4U, // VFMADD231PDZm 4U, // VFMADD231PDZmb 133U, // VFMADD231PDZmbk 8325U, // VFMADD231PDZmbkz 0U, // VFMADD231PDZmk 0U, // VFMADD231PDZmkz 4U, // VFMADD231PDZr 4U, // VFMADD231PDZrb 0U, // VFMADD231PDZrbk 0U, // VFMADD231PDZrbkz 0U, // VFMADD231PDZrk 0U, // VFMADD231PDZrkz 4U, // VFMADD231PDm 4U, // VFMADD231PDr 4U, // VFMADD231PSYm 4U, // VFMADD231PSYr 4U, // VFMADD231PSZ128m 4U, // VFMADD231PSZ128mb 133U, // VFMADD231PSZ128mbk 8325U, // VFMADD231PSZ128mbkz 0U, // VFMADD231PSZ128mk 0U, // VFMADD231PSZ128mkz 4U, // VFMADD231PSZ128r 0U, // VFMADD231PSZ128rk 0U, // VFMADD231PSZ128rkz 4U, // VFMADD231PSZ256m 4U, // VFMADD231PSZ256mb 133U, // VFMADD231PSZ256mbk 8325U, // VFMADD231PSZ256mbkz 0U, // VFMADD231PSZ256mk 0U, // VFMADD231PSZ256mkz 4U, // VFMADD231PSZ256r 0U, // VFMADD231PSZ256rk 0U, // VFMADD231PSZ256rkz 4U, // VFMADD231PSZm 4U, // VFMADD231PSZmb 133U, // VFMADD231PSZmbk 8325U, // VFMADD231PSZmbkz 0U, // VFMADD231PSZmk 0U, // VFMADD231PSZmkz 4U, // VFMADD231PSZr 4U, // VFMADD231PSZrb 0U, // VFMADD231PSZrbk 0U, // VFMADD231PSZrbkz 0U, // VFMADD231PSZrk 0U, // VFMADD231PSZrkz 4U, // VFMADD231PSm 4U, // VFMADD231PSr 4U, // VFMADD231SDZm 4U, // VFMADD231SDZm_Int 133U, // VFMADD231SDZm_Intk 8325U, // VFMADD231SDZm_Intkz 4U, // VFMADD231SDZr 4U, // VFMADD231SDZr_Int 0U, // VFMADD231SDZr_Intk 0U, // VFMADD231SDZr_Intkz 4U, // VFMADD231SDZrb 4U, // VFMADD231SDZrb_Int 0U, // VFMADD231SDZrb_Intk 0U, // VFMADD231SDZrb_Intkz 4U, // VFMADD231SDm 4U, // VFMADD231SDm_Int 4U, // VFMADD231SDr 4U, // VFMADD231SDr_Int 4U, // VFMADD231SSZm 4U, // VFMADD231SSZm_Int 133U, // VFMADD231SSZm_Intk 8325U, // VFMADD231SSZm_Intkz 4U, // VFMADD231SSZr 4U, // VFMADD231SSZr_Int 0U, // VFMADD231SSZr_Intk 0U, // VFMADD231SSZr_Intkz 4U, // VFMADD231SSZrb 4U, // VFMADD231SSZrb_Int 0U, // VFMADD231SSZrb_Intk 0U, // VFMADD231SSZrb_Intkz 4U, // VFMADD231SSm 4U, // VFMADD231SSm_Int 4U, // VFMADD231SSr 4U, // VFMADD231SSr_Int 72U, // VFMADDPD4Ymr 18636U, // VFMADDPD4Yrm 18636U, // VFMADDPD4Yrr 18636U, // VFMADDPD4Yrr_REV 72U, // VFMADDPD4mr 18636U, // VFMADDPD4rm 18636U, // VFMADDPD4rr 18636U, // VFMADDPD4rr_REV 72U, // VFMADDPS4Ymr 18636U, // VFMADDPS4Yrm 18636U, // VFMADDPS4Yrr 18636U, // VFMADDPS4Yrr_REV 72U, // VFMADDPS4mr 18636U, // VFMADDPS4rm 18636U, // VFMADDPS4rr 18636U, // VFMADDPS4rr_REV 18636U, // VFMADDSD4mr 18636U, // VFMADDSD4mr_Int 18636U, // VFMADDSD4rm 18636U, // VFMADDSD4rm_Int 18636U, // VFMADDSD4rr 18636U, // VFMADDSD4rr_Int 18636U, // VFMADDSD4rr_Int_REV 18636U, // VFMADDSD4rr_REV 18636U, // VFMADDSS4mr 18636U, // VFMADDSS4mr_Int 18636U, // VFMADDSS4rm 18636U, // VFMADDSS4rm_Int 18636U, // VFMADDSS4rr 18636U, // VFMADDSS4rr_Int 18636U, // VFMADDSS4rr_Int_REV 18636U, // VFMADDSS4rr_REV 4U, // VFMADDSUB132PDYm 4U, // VFMADDSUB132PDYr 4U, // VFMADDSUB132PDZ128m 4U, // VFMADDSUB132PDZ128mb 133U, // VFMADDSUB132PDZ128mbk 8325U, // VFMADDSUB132PDZ128mbkz 0U, // VFMADDSUB132PDZ128mk 0U, // VFMADDSUB132PDZ128mkz 4U, // VFMADDSUB132PDZ128r 0U, // VFMADDSUB132PDZ128rk 0U, // VFMADDSUB132PDZ128rkz 4U, // VFMADDSUB132PDZ256m 4U, // VFMADDSUB132PDZ256mb 133U, // VFMADDSUB132PDZ256mbk 8325U, // VFMADDSUB132PDZ256mbkz 0U, // VFMADDSUB132PDZ256mk 0U, // VFMADDSUB132PDZ256mkz 4U, // VFMADDSUB132PDZ256r 0U, // VFMADDSUB132PDZ256rk 0U, // VFMADDSUB132PDZ256rkz 4U, // VFMADDSUB132PDZm 4U, // VFMADDSUB132PDZmb 133U, // VFMADDSUB132PDZmbk 8325U, // VFMADDSUB132PDZmbkz 0U, // VFMADDSUB132PDZmk 0U, // VFMADDSUB132PDZmkz 4U, // VFMADDSUB132PDZr 4U, // VFMADDSUB132PDZrb 0U, // VFMADDSUB132PDZrbk 0U, // VFMADDSUB132PDZrbkz 0U, // VFMADDSUB132PDZrk 0U, // VFMADDSUB132PDZrkz 4U, // VFMADDSUB132PDm 4U, // VFMADDSUB132PDr 4U, // VFMADDSUB132PSYm 4U, // VFMADDSUB132PSYr 4U, // VFMADDSUB132PSZ128m 4U, // VFMADDSUB132PSZ128mb 133U, // VFMADDSUB132PSZ128mbk 8325U, // VFMADDSUB132PSZ128mbkz 0U, // VFMADDSUB132PSZ128mk 0U, // VFMADDSUB132PSZ128mkz 4U, // VFMADDSUB132PSZ128r 0U, // VFMADDSUB132PSZ128rk 0U, // VFMADDSUB132PSZ128rkz 4U, // VFMADDSUB132PSZ256m 4U, // VFMADDSUB132PSZ256mb 133U, // VFMADDSUB132PSZ256mbk 8325U, // VFMADDSUB132PSZ256mbkz 0U, // VFMADDSUB132PSZ256mk 0U, // VFMADDSUB132PSZ256mkz 4U, // VFMADDSUB132PSZ256r 0U, // VFMADDSUB132PSZ256rk 0U, // VFMADDSUB132PSZ256rkz 4U, // VFMADDSUB132PSZm 4U, // VFMADDSUB132PSZmb 133U, // VFMADDSUB132PSZmbk 8325U, // VFMADDSUB132PSZmbkz 0U, // VFMADDSUB132PSZmk 0U, // VFMADDSUB132PSZmkz 4U, // VFMADDSUB132PSZr 4U, // VFMADDSUB132PSZrb 0U, // VFMADDSUB132PSZrbk 0U, // VFMADDSUB132PSZrbkz 0U, // VFMADDSUB132PSZrk 0U, // VFMADDSUB132PSZrkz 4U, // VFMADDSUB132PSm 4U, // VFMADDSUB132PSr 4U, // VFMADDSUB213PDYm 4U, // VFMADDSUB213PDYr 4U, // VFMADDSUB213PDZ128m 4U, // VFMADDSUB213PDZ128mb 133U, // VFMADDSUB213PDZ128mbk 8325U, // VFMADDSUB213PDZ128mbkz 0U, // VFMADDSUB213PDZ128mk 0U, // VFMADDSUB213PDZ128mkz 4U, // VFMADDSUB213PDZ128r 0U, // VFMADDSUB213PDZ128rk 0U, // VFMADDSUB213PDZ128rkz 4U, // VFMADDSUB213PDZ256m 4U, // VFMADDSUB213PDZ256mb 133U, // VFMADDSUB213PDZ256mbk 8325U, // VFMADDSUB213PDZ256mbkz 0U, // VFMADDSUB213PDZ256mk 0U, // VFMADDSUB213PDZ256mkz 4U, // VFMADDSUB213PDZ256r 0U, // VFMADDSUB213PDZ256rk 0U, // VFMADDSUB213PDZ256rkz 4U, // VFMADDSUB213PDZm 4U, // VFMADDSUB213PDZmb 133U, // VFMADDSUB213PDZmbk 8325U, // VFMADDSUB213PDZmbkz 0U, // VFMADDSUB213PDZmk 0U, // VFMADDSUB213PDZmkz 4U, // VFMADDSUB213PDZr 4U, // VFMADDSUB213PDZrb 0U, // VFMADDSUB213PDZrbk 0U, // VFMADDSUB213PDZrbkz 0U, // VFMADDSUB213PDZrk 0U, // VFMADDSUB213PDZrkz 4U, // VFMADDSUB213PDm 4U, // VFMADDSUB213PDr 4U, // VFMADDSUB213PSYm 4U, // VFMADDSUB213PSYr 4U, // VFMADDSUB213PSZ128m 4U, // VFMADDSUB213PSZ128mb 133U, // VFMADDSUB213PSZ128mbk 8325U, // VFMADDSUB213PSZ128mbkz 0U, // VFMADDSUB213PSZ128mk 0U, // VFMADDSUB213PSZ128mkz 4U, // VFMADDSUB213PSZ128r 0U, // VFMADDSUB213PSZ128rk 0U, // VFMADDSUB213PSZ128rkz 4U, // VFMADDSUB213PSZ256m 4U, // VFMADDSUB213PSZ256mb 133U, // VFMADDSUB213PSZ256mbk 8325U, // VFMADDSUB213PSZ256mbkz 0U, // VFMADDSUB213PSZ256mk 0U, // VFMADDSUB213PSZ256mkz 4U, // VFMADDSUB213PSZ256r 0U, // VFMADDSUB213PSZ256rk 0U, // VFMADDSUB213PSZ256rkz 4U, // VFMADDSUB213PSZm 4U, // VFMADDSUB213PSZmb 133U, // VFMADDSUB213PSZmbk 8325U, // VFMADDSUB213PSZmbkz 0U, // VFMADDSUB213PSZmk 0U, // VFMADDSUB213PSZmkz 4U, // VFMADDSUB213PSZr 4U, // VFMADDSUB213PSZrb 0U, // VFMADDSUB213PSZrbk 0U, // VFMADDSUB213PSZrbkz 0U, // VFMADDSUB213PSZrk 0U, // VFMADDSUB213PSZrkz 4U, // VFMADDSUB213PSm 4U, // VFMADDSUB213PSr 4U, // VFMADDSUB231PDYm 4U, // VFMADDSUB231PDYr 4U, // VFMADDSUB231PDZ128m 4U, // VFMADDSUB231PDZ128mb 133U, // VFMADDSUB231PDZ128mbk 8325U, // VFMADDSUB231PDZ128mbkz 0U, // VFMADDSUB231PDZ128mk 0U, // VFMADDSUB231PDZ128mkz 4U, // VFMADDSUB231PDZ128r 0U, // VFMADDSUB231PDZ128rk 0U, // VFMADDSUB231PDZ128rkz 4U, // VFMADDSUB231PDZ256m 4U, // VFMADDSUB231PDZ256mb 133U, // VFMADDSUB231PDZ256mbk 8325U, // VFMADDSUB231PDZ256mbkz 0U, // VFMADDSUB231PDZ256mk 0U, // VFMADDSUB231PDZ256mkz 4U, // VFMADDSUB231PDZ256r 0U, // VFMADDSUB231PDZ256rk 0U, // VFMADDSUB231PDZ256rkz 4U, // VFMADDSUB231PDZm 4U, // VFMADDSUB231PDZmb 133U, // VFMADDSUB231PDZmbk 8325U, // VFMADDSUB231PDZmbkz 0U, // VFMADDSUB231PDZmk 0U, // VFMADDSUB231PDZmkz 4U, // VFMADDSUB231PDZr 4U, // VFMADDSUB231PDZrb 0U, // VFMADDSUB231PDZrbk 0U, // VFMADDSUB231PDZrbkz 0U, // VFMADDSUB231PDZrk 0U, // VFMADDSUB231PDZrkz 4U, // VFMADDSUB231PDm 4U, // VFMADDSUB231PDr 4U, // VFMADDSUB231PSYm 4U, // VFMADDSUB231PSYr 4U, // VFMADDSUB231PSZ128m 4U, // VFMADDSUB231PSZ128mb 133U, // VFMADDSUB231PSZ128mbk 8325U, // VFMADDSUB231PSZ128mbkz 0U, // VFMADDSUB231PSZ128mk 0U, // VFMADDSUB231PSZ128mkz 4U, // VFMADDSUB231PSZ128r 0U, // VFMADDSUB231PSZ128rk 0U, // VFMADDSUB231PSZ128rkz 4U, // VFMADDSUB231PSZ256m 4U, // VFMADDSUB231PSZ256mb 133U, // VFMADDSUB231PSZ256mbk 8325U, // VFMADDSUB231PSZ256mbkz 0U, // VFMADDSUB231PSZ256mk 0U, // VFMADDSUB231PSZ256mkz 4U, // VFMADDSUB231PSZ256r 0U, // VFMADDSUB231PSZ256rk 0U, // VFMADDSUB231PSZ256rkz 4U, // VFMADDSUB231PSZm 4U, // VFMADDSUB231PSZmb 133U, // VFMADDSUB231PSZmbk 8325U, // VFMADDSUB231PSZmbkz 0U, // VFMADDSUB231PSZmk 0U, // VFMADDSUB231PSZmkz 4U, // VFMADDSUB231PSZr 4U, // VFMADDSUB231PSZrb 0U, // VFMADDSUB231PSZrbk 0U, // VFMADDSUB231PSZrbkz 0U, // VFMADDSUB231PSZrk 0U, // VFMADDSUB231PSZrkz 4U, // VFMADDSUB231PSm 4U, // VFMADDSUB231PSr 72U, // VFMADDSUBPD4Ymr 18636U, // VFMADDSUBPD4Yrm 18636U, // VFMADDSUBPD4Yrr 18636U, // VFMADDSUBPD4Yrr_REV 72U, // VFMADDSUBPD4mr 18636U, // VFMADDSUBPD4rm 18636U, // VFMADDSUBPD4rr 18636U, // VFMADDSUBPD4rr_REV 72U, // VFMADDSUBPS4Ymr 18636U, // VFMADDSUBPS4Yrm 18636U, // VFMADDSUBPS4Yrr 18636U, // VFMADDSUBPS4Yrr_REV 72U, // VFMADDSUBPS4mr 18636U, // VFMADDSUBPS4rm 18636U, // VFMADDSUBPS4rr 18636U, // VFMADDSUBPS4rr_REV 4U, // VFMSUB132PDYm 4U, // VFMSUB132PDYr 4U, // VFMSUB132PDZ128m 4U, // VFMSUB132PDZ128mb 133U, // VFMSUB132PDZ128mbk 8325U, // VFMSUB132PDZ128mbkz 0U, // VFMSUB132PDZ128mk 0U, // VFMSUB132PDZ128mkz 4U, // VFMSUB132PDZ128r 0U, // VFMSUB132PDZ128rk 0U, // VFMSUB132PDZ128rkz 4U, // VFMSUB132PDZ256m 4U, // VFMSUB132PDZ256mb 133U, // VFMSUB132PDZ256mbk 8325U, // VFMSUB132PDZ256mbkz 0U, // VFMSUB132PDZ256mk 0U, // VFMSUB132PDZ256mkz 4U, // VFMSUB132PDZ256r 0U, // VFMSUB132PDZ256rk 0U, // VFMSUB132PDZ256rkz 4U, // VFMSUB132PDZm 4U, // VFMSUB132PDZmb 133U, // VFMSUB132PDZmbk 8325U, // VFMSUB132PDZmbkz 0U, // VFMSUB132PDZmk 0U, // VFMSUB132PDZmkz 4U, // VFMSUB132PDZr 4U, // VFMSUB132PDZrb 0U, // VFMSUB132PDZrbk 0U, // VFMSUB132PDZrbkz 0U, // VFMSUB132PDZrk 0U, // VFMSUB132PDZrkz 4U, // VFMSUB132PDm 4U, // VFMSUB132PDr 4U, // VFMSUB132PSYm 4U, // VFMSUB132PSYr 4U, // VFMSUB132PSZ128m 4U, // VFMSUB132PSZ128mb 133U, // VFMSUB132PSZ128mbk 8325U, // VFMSUB132PSZ128mbkz 0U, // VFMSUB132PSZ128mk 0U, // VFMSUB132PSZ128mkz 4U, // VFMSUB132PSZ128r 0U, // VFMSUB132PSZ128rk 0U, // VFMSUB132PSZ128rkz 4U, // VFMSUB132PSZ256m 4U, // VFMSUB132PSZ256mb 133U, // VFMSUB132PSZ256mbk 8325U, // VFMSUB132PSZ256mbkz 0U, // VFMSUB132PSZ256mk 0U, // VFMSUB132PSZ256mkz 4U, // VFMSUB132PSZ256r 0U, // VFMSUB132PSZ256rk 0U, // VFMSUB132PSZ256rkz 4U, // VFMSUB132PSZm 4U, // VFMSUB132PSZmb 133U, // VFMSUB132PSZmbk 8325U, // VFMSUB132PSZmbkz 0U, // VFMSUB132PSZmk 0U, // VFMSUB132PSZmkz 4U, // VFMSUB132PSZr 4U, // VFMSUB132PSZrb 0U, // VFMSUB132PSZrbk 0U, // VFMSUB132PSZrbkz 0U, // VFMSUB132PSZrk 0U, // VFMSUB132PSZrkz 4U, // VFMSUB132PSm 4U, // VFMSUB132PSr 4U, // VFMSUB132SDZm 4U, // VFMSUB132SDZm_Int 133U, // VFMSUB132SDZm_Intk 8325U, // VFMSUB132SDZm_Intkz 4U, // VFMSUB132SDZr 4U, // VFMSUB132SDZr_Int 0U, // VFMSUB132SDZr_Intk 0U, // VFMSUB132SDZr_Intkz 4U, // VFMSUB132SDZrb 4U, // VFMSUB132SDZrb_Int 0U, // VFMSUB132SDZrb_Intk 0U, // VFMSUB132SDZrb_Intkz 4U, // VFMSUB132SDm 4U, // VFMSUB132SDm_Int 4U, // VFMSUB132SDr 4U, // VFMSUB132SDr_Int 4U, // VFMSUB132SSZm 4U, // VFMSUB132SSZm_Int 133U, // VFMSUB132SSZm_Intk 8325U, // VFMSUB132SSZm_Intkz 4U, // VFMSUB132SSZr 4U, // VFMSUB132SSZr_Int 0U, // VFMSUB132SSZr_Intk 0U, // VFMSUB132SSZr_Intkz 4U, // VFMSUB132SSZrb 4U, // VFMSUB132SSZrb_Int 0U, // VFMSUB132SSZrb_Intk 0U, // VFMSUB132SSZrb_Intkz 4U, // VFMSUB132SSm 4U, // VFMSUB132SSm_Int 4U, // VFMSUB132SSr 4U, // VFMSUB132SSr_Int 4U, // VFMSUB213PDYm 4U, // VFMSUB213PDYr 4U, // VFMSUB213PDZ128m 4U, // VFMSUB213PDZ128mb 133U, // VFMSUB213PDZ128mbk 8325U, // VFMSUB213PDZ128mbkz 0U, // VFMSUB213PDZ128mk 0U, // VFMSUB213PDZ128mkz 4U, // VFMSUB213PDZ128r 0U, // VFMSUB213PDZ128rk 0U, // VFMSUB213PDZ128rkz 4U, // VFMSUB213PDZ256m 4U, // VFMSUB213PDZ256mb 133U, // VFMSUB213PDZ256mbk 8325U, // VFMSUB213PDZ256mbkz 0U, // VFMSUB213PDZ256mk 0U, // VFMSUB213PDZ256mkz 4U, // VFMSUB213PDZ256r 0U, // VFMSUB213PDZ256rk 0U, // VFMSUB213PDZ256rkz 4U, // VFMSUB213PDZm 4U, // VFMSUB213PDZmb 133U, // VFMSUB213PDZmbk 8325U, // VFMSUB213PDZmbkz 0U, // VFMSUB213PDZmk 0U, // VFMSUB213PDZmkz 4U, // VFMSUB213PDZr 4U, // VFMSUB213PDZrb 0U, // VFMSUB213PDZrbk 0U, // VFMSUB213PDZrbkz 0U, // VFMSUB213PDZrk 0U, // VFMSUB213PDZrkz 4U, // VFMSUB213PDm 4U, // VFMSUB213PDr 4U, // VFMSUB213PSYm 4U, // VFMSUB213PSYr 4U, // VFMSUB213PSZ128m 4U, // VFMSUB213PSZ128mb 133U, // VFMSUB213PSZ128mbk 8325U, // VFMSUB213PSZ128mbkz 0U, // VFMSUB213PSZ128mk 0U, // VFMSUB213PSZ128mkz 4U, // VFMSUB213PSZ128r 0U, // VFMSUB213PSZ128rk 0U, // VFMSUB213PSZ128rkz 4U, // VFMSUB213PSZ256m 4U, // VFMSUB213PSZ256mb 133U, // VFMSUB213PSZ256mbk 8325U, // VFMSUB213PSZ256mbkz 0U, // VFMSUB213PSZ256mk 0U, // VFMSUB213PSZ256mkz 4U, // VFMSUB213PSZ256r 0U, // VFMSUB213PSZ256rk 0U, // VFMSUB213PSZ256rkz 4U, // VFMSUB213PSZm 4U, // VFMSUB213PSZmb 133U, // VFMSUB213PSZmbk 8325U, // VFMSUB213PSZmbkz 0U, // VFMSUB213PSZmk 0U, // VFMSUB213PSZmkz 4U, // VFMSUB213PSZr 4U, // VFMSUB213PSZrb 0U, // VFMSUB213PSZrbk 0U, // VFMSUB213PSZrbkz 0U, // VFMSUB213PSZrk 0U, // VFMSUB213PSZrkz 4U, // VFMSUB213PSm 4U, // VFMSUB213PSr 4U, // VFMSUB213SDZm 4U, // VFMSUB213SDZm_Int 133U, // VFMSUB213SDZm_Intk 8325U, // VFMSUB213SDZm_Intkz 4U, // VFMSUB213SDZr 4U, // VFMSUB213SDZr_Int 0U, // VFMSUB213SDZr_Intk 0U, // VFMSUB213SDZr_Intkz 4U, // VFMSUB213SDZrb 4U, // VFMSUB213SDZrb_Int 0U, // VFMSUB213SDZrb_Intk 0U, // VFMSUB213SDZrb_Intkz 4U, // VFMSUB213SDm 4U, // VFMSUB213SDm_Int 4U, // VFMSUB213SDr 4U, // VFMSUB213SDr_Int 4U, // VFMSUB213SSZm 4U, // VFMSUB213SSZm_Int 133U, // VFMSUB213SSZm_Intk 8325U, // VFMSUB213SSZm_Intkz 4U, // VFMSUB213SSZr 4U, // VFMSUB213SSZr_Int 0U, // VFMSUB213SSZr_Intk 0U, // VFMSUB213SSZr_Intkz 4U, // VFMSUB213SSZrb 4U, // VFMSUB213SSZrb_Int 0U, // VFMSUB213SSZrb_Intk 0U, // VFMSUB213SSZrb_Intkz 4U, // VFMSUB213SSm 4U, // VFMSUB213SSm_Int 4U, // VFMSUB213SSr 4U, // VFMSUB213SSr_Int 4U, // VFMSUB231PDYm 4U, // VFMSUB231PDYr 4U, // VFMSUB231PDZ128m 4U, // VFMSUB231PDZ128mb 133U, // VFMSUB231PDZ128mbk 8325U, // VFMSUB231PDZ128mbkz 0U, // VFMSUB231PDZ128mk 0U, // VFMSUB231PDZ128mkz 4U, // VFMSUB231PDZ128r 0U, // VFMSUB231PDZ128rk 0U, // VFMSUB231PDZ128rkz 4U, // VFMSUB231PDZ256m 4U, // VFMSUB231PDZ256mb 133U, // VFMSUB231PDZ256mbk 8325U, // VFMSUB231PDZ256mbkz 0U, // VFMSUB231PDZ256mk 0U, // VFMSUB231PDZ256mkz 4U, // VFMSUB231PDZ256r 0U, // VFMSUB231PDZ256rk 0U, // VFMSUB231PDZ256rkz 4U, // VFMSUB231PDZm 4U, // VFMSUB231PDZmb 133U, // VFMSUB231PDZmbk 8325U, // VFMSUB231PDZmbkz 0U, // VFMSUB231PDZmk 0U, // VFMSUB231PDZmkz 4U, // VFMSUB231PDZr 4U, // VFMSUB231PDZrb 0U, // VFMSUB231PDZrbk 0U, // VFMSUB231PDZrbkz 0U, // VFMSUB231PDZrk 0U, // VFMSUB231PDZrkz 4U, // VFMSUB231PDm 4U, // VFMSUB231PDr 4U, // VFMSUB231PSYm 4U, // VFMSUB231PSYr 4U, // VFMSUB231PSZ128m 4U, // VFMSUB231PSZ128mb 133U, // VFMSUB231PSZ128mbk 8325U, // VFMSUB231PSZ128mbkz 0U, // VFMSUB231PSZ128mk 0U, // VFMSUB231PSZ128mkz 4U, // VFMSUB231PSZ128r 0U, // VFMSUB231PSZ128rk 0U, // VFMSUB231PSZ128rkz 4U, // VFMSUB231PSZ256m 4U, // VFMSUB231PSZ256mb 133U, // VFMSUB231PSZ256mbk 8325U, // VFMSUB231PSZ256mbkz 0U, // VFMSUB231PSZ256mk 0U, // VFMSUB231PSZ256mkz 4U, // VFMSUB231PSZ256r 0U, // VFMSUB231PSZ256rk 0U, // VFMSUB231PSZ256rkz 4U, // VFMSUB231PSZm 4U, // VFMSUB231PSZmb 133U, // VFMSUB231PSZmbk 8325U, // VFMSUB231PSZmbkz 0U, // VFMSUB231PSZmk 0U, // VFMSUB231PSZmkz 4U, // VFMSUB231PSZr 4U, // VFMSUB231PSZrb 0U, // VFMSUB231PSZrbk 0U, // VFMSUB231PSZrbkz 0U, // VFMSUB231PSZrk 0U, // VFMSUB231PSZrkz 4U, // VFMSUB231PSm 4U, // VFMSUB231PSr 4U, // VFMSUB231SDZm 4U, // VFMSUB231SDZm_Int 133U, // VFMSUB231SDZm_Intk 8325U, // VFMSUB231SDZm_Intkz 4U, // VFMSUB231SDZr 4U, // VFMSUB231SDZr_Int 0U, // VFMSUB231SDZr_Intk 0U, // VFMSUB231SDZr_Intkz 4U, // VFMSUB231SDZrb 4U, // VFMSUB231SDZrb_Int 0U, // VFMSUB231SDZrb_Intk 0U, // VFMSUB231SDZrb_Intkz 4U, // VFMSUB231SDm 4U, // VFMSUB231SDm_Int 4U, // VFMSUB231SDr 4U, // VFMSUB231SDr_Int 4U, // VFMSUB231SSZm 4U, // VFMSUB231SSZm_Int 133U, // VFMSUB231SSZm_Intk 8325U, // VFMSUB231SSZm_Intkz 4U, // VFMSUB231SSZr 4U, // VFMSUB231SSZr_Int 0U, // VFMSUB231SSZr_Intk 0U, // VFMSUB231SSZr_Intkz 4U, // VFMSUB231SSZrb 4U, // VFMSUB231SSZrb_Int 0U, // VFMSUB231SSZrb_Intk 0U, // VFMSUB231SSZrb_Intkz 4U, // VFMSUB231SSm 4U, // VFMSUB231SSm_Int 4U, // VFMSUB231SSr 4U, // VFMSUB231SSr_Int 4U, // VFMSUBADD132PDYm 4U, // VFMSUBADD132PDYr 4U, // VFMSUBADD132PDZ128m 4U, // VFMSUBADD132PDZ128mb 133U, // VFMSUBADD132PDZ128mbk 8325U, // VFMSUBADD132PDZ128mbkz 0U, // VFMSUBADD132PDZ128mk 0U, // VFMSUBADD132PDZ128mkz 4U, // VFMSUBADD132PDZ128r 0U, // VFMSUBADD132PDZ128rk 0U, // VFMSUBADD132PDZ128rkz 4U, // VFMSUBADD132PDZ256m 4U, // VFMSUBADD132PDZ256mb 133U, // VFMSUBADD132PDZ256mbk 8325U, // VFMSUBADD132PDZ256mbkz 0U, // VFMSUBADD132PDZ256mk 0U, // VFMSUBADD132PDZ256mkz 4U, // VFMSUBADD132PDZ256r 0U, // VFMSUBADD132PDZ256rk 0U, // VFMSUBADD132PDZ256rkz 4U, // VFMSUBADD132PDZm 4U, // VFMSUBADD132PDZmb 133U, // VFMSUBADD132PDZmbk 8325U, // VFMSUBADD132PDZmbkz 0U, // VFMSUBADD132PDZmk 0U, // VFMSUBADD132PDZmkz 4U, // VFMSUBADD132PDZr 4U, // VFMSUBADD132PDZrb 0U, // VFMSUBADD132PDZrbk 0U, // VFMSUBADD132PDZrbkz 0U, // VFMSUBADD132PDZrk 0U, // VFMSUBADD132PDZrkz 4U, // VFMSUBADD132PDm 4U, // VFMSUBADD132PDr 4U, // VFMSUBADD132PSYm 4U, // VFMSUBADD132PSYr 4U, // VFMSUBADD132PSZ128m 4U, // VFMSUBADD132PSZ128mb 133U, // VFMSUBADD132PSZ128mbk 8325U, // VFMSUBADD132PSZ128mbkz 0U, // VFMSUBADD132PSZ128mk 0U, // VFMSUBADD132PSZ128mkz 4U, // VFMSUBADD132PSZ128r 0U, // VFMSUBADD132PSZ128rk 0U, // VFMSUBADD132PSZ128rkz 4U, // VFMSUBADD132PSZ256m 4U, // VFMSUBADD132PSZ256mb 133U, // VFMSUBADD132PSZ256mbk 8325U, // VFMSUBADD132PSZ256mbkz 0U, // VFMSUBADD132PSZ256mk 0U, // VFMSUBADD132PSZ256mkz 4U, // VFMSUBADD132PSZ256r 0U, // VFMSUBADD132PSZ256rk 0U, // VFMSUBADD132PSZ256rkz 4U, // VFMSUBADD132PSZm 4U, // VFMSUBADD132PSZmb 133U, // VFMSUBADD132PSZmbk 8325U, // VFMSUBADD132PSZmbkz 0U, // VFMSUBADD132PSZmk 0U, // VFMSUBADD132PSZmkz 4U, // VFMSUBADD132PSZr 4U, // VFMSUBADD132PSZrb 0U, // VFMSUBADD132PSZrbk 0U, // VFMSUBADD132PSZrbkz 0U, // VFMSUBADD132PSZrk 0U, // VFMSUBADD132PSZrkz 4U, // VFMSUBADD132PSm 4U, // VFMSUBADD132PSr 4U, // VFMSUBADD213PDYm 4U, // VFMSUBADD213PDYr 4U, // VFMSUBADD213PDZ128m 4U, // VFMSUBADD213PDZ128mb 133U, // VFMSUBADD213PDZ128mbk 8325U, // VFMSUBADD213PDZ128mbkz 0U, // VFMSUBADD213PDZ128mk 0U, // VFMSUBADD213PDZ128mkz 4U, // VFMSUBADD213PDZ128r 0U, // VFMSUBADD213PDZ128rk 0U, // VFMSUBADD213PDZ128rkz 4U, // VFMSUBADD213PDZ256m 4U, // VFMSUBADD213PDZ256mb 133U, // VFMSUBADD213PDZ256mbk 8325U, // VFMSUBADD213PDZ256mbkz 0U, // VFMSUBADD213PDZ256mk 0U, // VFMSUBADD213PDZ256mkz 4U, // VFMSUBADD213PDZ256r 0U, // VFMSUBADD213PDZ256rk 0U, // VFMSUBADD213PDZ256rkz 4U, // VFMSUBADD213PDZm 4U, // VFMSUBADD213PDZmb 133U, // VFMSUBADD213PDZmbk 8325U, // VFMSUBADD213PDZmbkz 0U, // VFMSUBADD213PDZmk 0U, // VFMSUBADD213PDZmkz 4U, // VFMSUBADD213PDZr 4U, // VFMSUBADD213PDZrb 0U, // VFMSUBADD213PDZrbk 0U, // VFMSUBADD213PDZrbkz 0U, // VFMSUBADD213PDZrk 0U, // VFMSUBADD213PDZrkz 4U, // VFMSUBADD213PDm 4U, // VFMSUBADD213PDr 4U, // VFMSUBADD213PSYm 4U, // VFMSUBADD213PSYr 4U, // VFMSUBADD213PSZ128m 4U, // VFMSUBADD213PSZ128mb 133U, // VFMSUBADD213PSZ128mbk 8325U, // VFMSUBADD213PSZ128mbkz 0U, // VFMSUBADD213PSZ128mk 0U, // VFMSUBADD213PSZ128mkz 4U, // VFMSUBADD213PSZ128r 0U, // VFMSUBADD213PSZ128rk 0U, // VFMSUBADD213PSZ128rkz 4U, // VFMSUBADD213PSZ256m 4U, // VFMSUBADD213PSZ256mb 133U, // VFMSUBADD213PSZ256mbk 8325U, // VFMSUBADD213PSZ256mbkz 0U, // VFMSUBADD213PSZ256mk 0U, // VFMSUBADD213PSZ256mkz 4U, // VFMSUBADD213PSZ256r 0U, // VFMSUBADD213PSZ256rk 0U, // VFMSUBADD213PSZ256rkz 4U, // VFMSUBADD213PSZm 4U, // VFMSUBADD213PSZmb 133U, // VFMSUBADD213PSZmbk 8325U, // VFMSUBADD213PSZmbkz 0U, // VFMSUBADD213PSZmk 0U, // VFMSUBADD213PSZmkz 4U, // VFMSUBADD213PSZr 4U, // VFMSUBADD213PSZrb 0U, // VFMSUBADD213PSZrbk 0U, // VFMSUBADD213PSZrbkz 0U, // VFMSUBADD213PSZrk 0U, // VFMSUBADD213PSZrkz 4U, // VFMSUBADD213PSm 4U, // VFMSUBADD213PSr 4U, // VFMSUBADD231PDYm 4U, // VFMSUBADD231PDYr 4U, // VFMSUBADD231PDZ128m 4U, // VFMSUBADD231PDZ128mb 133U, // VFMSUBADD231PDZ128mbk 8325U, // VFMSUBADD231PDZ128mbkz 0U, // VFMSUBADD231PDZ128mk 0U, // VFMSUBADD231PDZ128mkz 4U, // VFMSUBADD231PDZ128r 0U, // VFMSUBADD231PDZ128rk 0U, // VFMSUBADD231PDZ128rkz 4U, // VFMSUBADD231PDZ256m 4U, // VFMSUBADD231PDZ256mb 133U, // VFMSUBADD231PDZ256mbk 8325U, // VFMSUBADD231PDZ256mbkz 0U, // VFMSUBADD231PDZ256mk 0U, // VFMSUBADD231PDZ256mkz 4U, // VFMSUBADD231PDZ256r 0U, // VFMSUBADD231PDZ256rk 0U, // VFMSUBADD231PDZ256rkz 4U, // VFMSUBADD231PDZm 4U, // VFMSUBADD231PDZmb 133U, // VFMSUBADD231PDZmbk 8325U, // VFMSUBADD231PDZmbkz 0U, // VFMSUBADD231PDZmk 0U, // VFMSUBADD231PDZmkz 4U, // VFMSUBADD231PDZr 4U, // VFMSUBADD231PDZrb 0U, // VFMSUBADD231PDZrbk 0U, // VFMSUBADD231PDZrbkz 0U, // VFMSUBADD231PDZrk 0U, // VFMSUBADD231PDZrkz 4U, // VFMSUBADD231PDm 4U, // VFMSUBADD231PDr 4U, // VFMSUBADD231PSYm 4U, // VFMSUBADD231PSYr 4U, // VFMSUBADD231PSZ128m 4U, // VFMSUBADD231PSZ128mb 133U, // VFMSUBADD231PSZ128mbk 8325U, // VFMSUBADD231PSZ128mbkz 0U, // VFMSUBADD231PSZ128mk 0U, // VFMSUBADD231PSZ128mkz 4U, // VFMSUBADD231PSZ128r 0U, // VFMSUBADD231PSZ128rk 0U, // VFMSUBADD231PSZ128rkz 4U, // VFMSUBADD231PSZ256m 4U, // VFMSUBADD231PSZ256mb 133U, // VFMSUBADD231PSZ256mbk 8325U, // VFMSUBADD231PSZ256mbkz 0U, // VFMSUBADD231PSZ256mk 0U, // VFMSUBADD231PSZ256mkz 4U, // VFMSUBADD231PSZ256r 0U, // VFMSUBADD231PSZ256rk 0U, // VFMSUBADD231PSZ256rkz 4U, // VFMSUBADD231PSZm 4U, // VFMSUBADD231PSZmb 133U, // VFMSUBADD231PSZmbk 8325U, // VFMSUBADD231PSZmbkz 0U, // VFMSUBADD231PSZmk 0U, // VFMSUBADD231PSZmkz 4U, // VFMSUBADD231PSZr 4U, // VFMSUBADD231PSZrb 0U, // VFMSUBADD231PSZrbk 0U, // VFMSUBADD231PSZrbkz 0U, // VFMSUBADD231PSZrk 0U, // VFMSUBADD231PSZrkz 4U, // VFMSUBADD231PSm 4U, // VFMSUBADD231PSr 72U, // VFMSUBADDPD4Ymr 18636U, // VFMSUBADDPD4Yrm 18636U, // VFMSUBADDPD4Yrr 18636U, // VFMSUBADDPD4Yrr_REV 72U, // VFMSUBADDPD4mr 18636U, // VFMSUBADDPD4rm 18636U, // VFMSUBADDPD4rr 18636U, // VFMSUBADDPD4rr_REV 72U, // VFMSUBADDPS4Ymr 18636U, // VFMSUBADDPS4Yrm 18636U, // VFMSUBADDPS4Yrr 18636U, // VFMSUBADDPS4Yrr_REV 72U, // VFMSUBADDPS4mr 18636U, // VFMSUBADDPS4rm 18636U, // VFMSUBADDPS4rr 18636U, // VFMSUBADDPS4rr_REV 72U, // VFMSUBPD4Ymr 18636U, // VFMSUBPD4Yrm 18636U, // VFMSUBPD4Yrr 18636U, // VFMSUBPD4Yrr_REV 72U, // VFMSUBPD4mr 18636U, // VFMSUBPD4rm 18636U, // VFMSUBPD4rr 18636U, // VFMSUBPD4rr_REV 72U, // VFMSUBPS4Ymr 18636U, // VFMSUBPS4Yrm 18636U, // VFMSUBPS4Yrr 18636U, // VFMSUBPS4Yrr_REV 72U, // VFMSUBPS4mr 18636U, // VFMSUBPS4rm 18636U, // VFMSUBPS4rr 18636U, // VFMSUBPS4rr_REV 18636U, // VFMSUBSD4mr 18636U, // VFMSUBSD4mr_Int 18636U, // VFMSUBSD4rm 18636U, // VFMSUBSD4rm_Int 18636U, // VFMSUBSD4rr 18636U, // VFMSUBSD4rr_Int 18636U, // VFMSUBSD4rr_Int_REV 18636U, // VFMSUBSD4rr_REV 18636U, // VFMSUBSS4mr 18636U, // VFMSUBSS4mr_Int 18636U, // VFMSUBSS4rm 18636U, // VFMSUBSS4rm_Int 18636U, // VFMSUBSS4rr 18636U, // VFMSUBSS4rr_Int 18636U, // VFMSUBSS4rr_Int_REV 18636U, // VFMSUBSS4rr_REV 4U, // VFNMADD132PDYm 4U, // VFNMADD132PDYr 4U, // VFNMADD132PDZ128m 4U, // VFNMADD132PDZ128mb 133U, // VFNMADD132PDZ128mbk 8325U, // VFNMADD132PDZ128mbkz 0U, // VFNMADD132PDZ128mk 0U, // VFNMADD132PDZ128mkz 4U, // VFNMADD132PDZ128r 0U, // VFNMADD132PDZ128rk 0U, // VFNMADD132PDZ128rkz 4U, // VFNMADD132PDZ256m 4U, // VFNMADD132PDZ256mb 133U, // VFNMADD132PDZ256mbk 8325U, // VFNMADD132PDZ256mbkz 0U, // VFNMADD132PDZ256mk 0U, // VFNMADD132PDZ256mkz 4U, // VFNMADD132PDZ256r 0U, // VFNMADD132PDZ256rk 0U, // VFNMADD132PDZ256rkz 4U, // VFNMADD132PDZm 4U, // VFNMADD132PDZmb 133U, // VFNMADD132PDZmbk 8325U, // VFNMADD132PDZmbkz 0U, // VFNMADD132PDZmk 0U, // VFNMADD132PDZmkz 4U, // VFNMADD132PDZr 4U, // VFNMADD132PDZrb 0U, // VFNMADD132PDZrbk 0U, // VFNMADD132PDZrbkz 0U, // VFNMADD132PDZrk 0U, // VFNMADD132PDZrkz 4U, // VFNMADD132PDm 4U, // VFNMADD132PDr 4U, // VFNMADD132PSYm 4U, // VFNMADD132PSYr 4U, // VFNMADD132PSZ128m 4U, // VFNMADD132PSZ128mb 133U, // VFNMADD132PSZ128mbk 8325U, // VFNMADD132PSZ128mbkz 0U, // VFNMADD132PSZ128mk 0U, // VFNMADD132PSZ128mkz 4U, // VFNMADD132PSZ128r 0U, // VFNMADD132PSZ128rk 0U, // VFNMADD132PSZ128rkz 4U, // VFNMADD132PSZ256m 4U, // VFNMADD132PSZ256mb 133U, // VFNMADD132PSZ256mbk 8325U, // VFNMADD132PSZ256mbkz 0U, // VFNMADD132PSZ256mk 0U, // VFNMADD132PSZ256mkz 4U, // VFNMADD132PSZ256r 0U, // VFNMADD132PSZ256rk 0U, // VFNMADD132PSZ256rkz 4U, // VFNMADD132PSZm 4U, // VFNMADD132PSZmb 133U, // VFNMADD132PSZmbk 8325U, // VFNMADD132PSZmbkz 0U, // VFNMADD132PSZmk 0U, // VFNMADD132PSZmkz 4U, // VFNMADD132PSZr 4U, // VFNMADD132PSZrb 0U, // VFNMADD132PSZrbk 0U, // VFNMADD132PSZrbkz 0U, // VFNMADD132PSZrk 0U, // VFNMADD132PSZrkz 4U, // VFNMADD132PSm 4U, // VFNMADD132PSr 4U, // VFNMADD132SDZm 4U, // VFNMADD132SDZm_Int 133U, // VFNMADD132SDZm_Intk 8325U, // VFNMADD132SDZm_Intkz 4U, // VFNMADD132SDZr 4U, // VFNMADD132SDZr_Int 0U, // VFNMADD132SDZr_Intk 0U, // VFNMADD132SDZr_Intkz 4U, // VFNMADD132SDZrb 4U, // VFNMADD132SDZrb_Int 0U, // VFNMADD132SDZrb_Intk 0U, // VFNMADD132SDZrb_Intkz 4U, // VFNMADD132SDm 4U, // VFNMADD132SDm_Int 4U, // VFNMADD132SDr 4U, // VFNMADD132SDr_Int 4U, // VFNMADD132SSZm 4U, // VFNMADD132SSZm_Int 133U, // VFNMADD132SSZm_Intk 8325U, // VFNMADD132SSZm_Intkz 4U, // VFNMADD132SSZr 4U, // VFNMADD132SSZr_Int 0U, // VFNMADD132SSZr_Intk 0U, // VFNMADD132SSZr_Intkz 4U, // VFNMADD132SSZrb 4U, // VFNMADD132SSZrb_Int 0U, // VFNMADD132SSZrb_Intk 0U, // VFNMADD132SSZrb_Intkz 4U, // VFNMADD132SSm 4U, // VFNMADD132SSm_Int 4U, // VFNMADD132SSr 4U, // VFNMADD132SSr_Int 4U, // VFNMADD213PDYm 4U, // VFNMADD213PDYr 4U, // VFNMADD213PDZ128m 4U, // VFNMADD213PDZ128mb 133U, // VFNMADD213PDZ128mbk 8325U, // VFNMADD213PDZ128mbkz 0U, // VFNMADD213PDZ128mk 0U, // VFNMADD213PDZ128mkz 4U, // VFNMADD213PDZ128r 0U, // VFNMADD213PDZ128rk 0U, // VFNMADD213PDZ128rkz 4U, // VFNMADD213PDZ256m 4U, // VFNMADD213PDZ256mb 133U, // VFNMADD213PDZ256mbk 8325U, // VFNMADD213PDZ256mbkz 0U, // VFNMADD213PDZ256mk 0U, // VFNMADD213PDZ256mkz 4U, // VFNMADD213PDZ256r 0U, // VFNMADD213PDZ256rk 0U, // VFNMADD213PDZ256rkz 4U, // VFNMADD213PDZm 4U, // VFNMADD213PDZmb 133U, // VFNMADD213PDZmbk 8325U, // VFNMADD213PDZmbkz 0U, // VFNMADD213PDZmk 0U, // VFNMADD213PDZmkz 4U, // VFNMADD213PDZr 4U, // VFNMADD213PDZrb 0U, // VFNMADD213PDZrbk 0U, // VFNMADD213PDZrbkz 0U, // VFNMADD213PDZrk 0U, // VFNMADD213PDZrkz 4U, // VFNMADD213PDm 4U, // VFNMADD213PDr 4U, // VFNMADD213PSYm 4U, // VFNMADD213PSYr 4U, // VFNMADD213PSZ128m 4U, // VFNMADD213PSZ128mb 133U, // VFNMADD213PSZ128mbk 8325U, // VFNMADD213PSZ128mbkz 0U, // VFNMADD213PSZ128mk 0U, // VFNMADD213PSZ128mkz 4U, // VFNMADD213PSZ128r 0U, // VFNMADD213PSZ128rk 0U, // VFNMADD213PSZ128rkz 4U, // VFNMADD213PSZ256m 4U, // VFNMADD213PSZ256mb 133U, // VFNMADD213PSZ256mbk 8325U, // VFNMADD213PSZ256mbkz 0U, // VFNMADD213PSZ256mk 0U, // VFNMADD213PSZ256mkz 4U, // VFNMADD213PSZ256r 0U, // VFNMADD213PSZ256rk 0U, // VFNMADD213PSZ256rkz 4U, // VFNMADD213PSZm 4U, // VFNMADD213PSZmb 133U, // VFNMADD213PSZmbk 8325U, // VFNMADD213PSZmbkz 0U, // VFNMADD213PSZmk 0U, // VFNMADD213PSZmkz 4U, // VFNMADD213PSZr 4U, // VFNMADD213PSZrb 0U, // VFNMADD213PSZrbk 0U, // VFNMADD213PSZrbkz 0U, // VFNMADD213PSZrk 0U, // VFNMADD213PSZrkz 4U, // VFNMADD213PSm 4U, // VFNMADD213PSr 4U, // VFNMADD213SDZm 4U, // VFNMADD213SDZm_Int 133U, // VFNMADD213SDZm_Intk 8325U, // VFNMADD213SDZm_Intkz 4U, // VFNMADD213SDZr 4U, // VFNMADD213SDZr_Int 0U, // VFNMADD213SDZr_Intk 0U, // VFNMADD213SDZr_Intkz 4U, // VFNMADD213SDZrb 4U, // VFNMADD213SDZrb_Int 0U, // VFNMADD213SDZrb_Intk 0U, // VFNMADD213SDZrb_Intkz 4U, // VFNMADD213SDm 4U, // VFNMADD213SDm_Int 4U, // VFNMADD213SDr 4U, // VFNMADD213SDr_Int 4U, // VFNMADD213SSZm 4U, // VFNMADD213SSZm_Int 133U, // VFNMADD213SSZm_Intk 8325U, // VFNMADD213SSZm_Intkz 4U, // VFNMADD213SSZr 4U, // VFNMADD213SSZr_Int 0U, // VFNMADD213SSZr_Intk 0U, // VFNMADD213SSZr_Intkz 4U, // VFNMADD213SSZrb 4U, // VFNMADD213SSZrb_Int 0U, // VFNMADD213SSZrb_Intk 0U, // VFNMADD213SSZrb_Intkz 4U, // VFNMADD213SSm 4U, // VFNMADD213SSm_Int 4U, // VFNMADD213SSr 4U, // VFNMADD213SSr_Int 4U, // VFNMADD231PDYm 4U, // VFNMADD231PDYr 4U, // VFNMADD231PDZ128m 4U, // VFNMADD231PDZ128mb 133U, // VFNMADD231PDZ128mbk 8325U, // VFNMADD231PDZ128mbkz 0U, // VFNMADD231PDZ128mk 0U, // VFNMADD231PDZ128mkz 4U, // VFNMADD231PDZ128r 0U, // VFNMADD231PDZ128rk 0U, // VFNMADD231PDZ128rkz 4U, // VFNMADD231PDZ256m 4U, // VFNMADD231PDZ256mb 133U, // VFNMADD231PDZ256mbk 8325U, // VFNMADD231PDZ256mbkz 0U, // VFNMADD231PDZ256mk 0U, // VFNMADD231PDZ256mkz 4U, // VFNMADD231PDZ256r 0U, // VFNMADD231PDZ256rk 0U, // VFNMADD231PDZ256rkz 4U, // VFNMADD231PDZm 4U, // VFNMADD231PDZmb 133U, // VFNMADD231PDZmbk 8325U, // VFNMADD231PDZmbkz 0U, // VFNMADD231PDZmk 0U, // VFNMADD231PDZmkz 4U, // VFNMADD231PDZr 4U, // VFNMADD231PDZrb 0U, // VFNMADD231PDZrbk 0U, // VFNMADD231PDZrbkz 0U, // VFNMADD231PDZrk 0U, // VFNMADD231PDZrkz 4U, // VFNMADD231PDm 4U, // VFNMADD231PDr 4U, // VFNMADD231PSYm 4U, // VFNMADD231PSYr 4U, // VFNMADD231PSZ128m 4U, // VFNMADD231PSZ128mb 133U, // VFNMADD231PSZ128mbk 8325U, // VFNMADD231PSZ128mbkz 0U, // VFNMADD231PSZ128mk 0U, // VFNMADD231PSZ128mkz 4U, // VFNMADD231PSZ128r 0U, // VFNMADD231PSZ128rk 0U, // VFNMADD231PSZ128rkz 4U, // VFNMADD231PSZ256m 4U, // VFNMADD231PSZ256mb 133U, // VFNMADD231PSZ256mbk 8325U, // VFNMADD231PSZ256mbkz 0U, // VFNMADD231PSZ256mk 0U, // VFNMADD231PSZ256mkz 4U, // VFNMADD231PSZ256r 0U, // VFNMADD231PSZ256rk 0U, // VFNMADD231PSZ256rkz 4U, // VFNMADD231PSZm 4U, // VFNMADD231PSZmb 133U, // VFNMADD231PSZmbk 8325U, // VFNMADD231PSZmbkz 0U, // VFNMADD231PSZmk 0U, // VFNMADD231PSZmkz 4U, // VFNMADD231PSZr 4U, // VFNMADD231PSZrb 0U, // VFNMADD231PSZrbk 0U, // VFNMADD231PSZrbkz 0U, // VFNMADD231PSZrk 0U, // VFNMADD231PSZrkz 4U, // VFNMADD231PSm 4U, // VFNMADD231PSr 4U, // VFNMADD231SDZm 4U, // VFNMADD231SDZm_Int 133U, // VFNMADD231SDZm_Intk 8325U, // VFNMADD231SDZm_Intkz 4U, // VFNMADD231SDZr 4U, // VFNMADD231SDZr_Int 0U, // VFNMADD231SDZr_Intk 0U, // VFNMADD231SDZr_Intkz 4U, // VFNMADD231SDZrb 4U, // VFNMADD231SDZrb_Int 0U, // VFNMADD231SDZrb_Intk 0U, // VFNMADD231SDZrb_Intkz 4U, // VFNMADD231SDm 4U, // VFNMADD231SDm_Int 4U, // VFNMADD231SDr 4U, // VFNMADD231SDr_Int 4U, // VFNMADD231SSZm 4U, // VFNMADD231SSZm_Int 133U, // VFNMADD231SSZm_Intk 8325U, // VFNMADD231SSZm_Intkz 4U, // VFNMADD231SSZr 4U, // VFNMADD231SSZr_Int 0U, // VFNMADD231SSZr_Intk 0U, // VFNMADD231SSZr_Intkz 4U, // VFNMADD231SSZrb 4U, // VFNMADD231SSZrb_Int 0U, // VFNMADD231SSZrb_Intk 0U, // VFNMADD231SSZrb_Intkz 4U, // VFNMADD231SSm 4U, // VFNMADD231SSm_Int 4U, // VFNMADD231SSr 4U, // VFNMADD231SSr_Int 72U, // VFNMADDPD4Ymr 18636U, // VFNMADDPD4Yrm 18636U, // VFNMADDPD4Yrr 18636U, // VFNMADDPD4Yrr_REV 72U, // VFNMADDPD4mr 18636U, // VFNMADDPD4rm 18636U, // VFNMADDPD4rr 18636U, // VFNMADDPD4rr_REV 72U, // VFNMADDPS4Ymr 18636U, // VFNMADDPS4Yrm 18636U, // VFNMADDPS4Yrr 18636U, // VFNMADDPS4Yrr_REV 72U, // VFNMADDPS4mr 18636U, // VFNMADDPS4rm 18636U, // VFNMADDPS4rr 18636U, // VFNMADDPS4rr_REV 18636U, // VFNMADDSD4mr 18636U, // VFNMADDSD4mr_Int 18636U, // VFNMADDSD4rm 18636U, // VFNMADDSD4rm_Int 18636U, // VFNMADDSD4rr 18636U, // VFNMADDSD4rr_Int 18636U, // VFNMADDSD4rr_Int_REV 18636U, // VFNMADDSD4rr_REV 18636U, // VFNMADDSS4mr 18636U, // VFNMADDSS4mr_Int 18636U, // VFNMADDSS4rm 18636U, // VFNMADDSS4rm_Int 18636U, // VFNMADDSS4rr 18636U, // VFNMADDSS4rr_Int 18636U, // VFNMADDSS4rr_Int_REV 18636U, // VFNMADDSS4rr_REV 4U, // VFNMSUB132PDYm 4U, // VFNMSUB132PDYr 4U, // VFNMSUB132PDZ128m 4U, // VFNMSUB132PDZ128mb 133U, // VFNMSUB132PDZ128mbk 8325U, // VFNMSUB132PDZ128mbkz 0U, // VFNMSUB132PDZ128mk 0U, // VFNMSUB132PDZ128mkz 4U, // VFNMSUB132PDZ128r 0U, // VFNMSUB132PDZ128rk 0U, // VFNMSUB132PDZ128rkz 4U, // VFNMSUB132PDZ256m 4U, // VFNMSUB132PDZ256mb 133U, // VFNMSUB132PDZ256mbk 8325U, // VFNMSUB132PDZ256mbkz 0U, // VFNMSUB132PDZ256mk 0U, // VFNMSUB132PDZ256mkz 4U, // VFNMSUB132PDZ256r 0U, // VFNMSUB132PDZ256rk 0U, // VFNMSUB132PDZ256rkz 4U, // VFNMSUB132PDZm 4U, // VFNMSUB132PDZmb 133U, // VFNMSUB132PDZmbk 8325U, // VFNMSUB132PDZmbkz 0U, // VFNMSUB132PDZmk 0U, // VFNMSUB132PDZmkz 4U, // VFNMSUB132PDZr 4U, // VFNMSUB132PDZrb 0U, // VFNMSUB132PDZrbk 0U, // VFNMSUB132PDZrbkz 0U, // VFNMSUB132PDZrk 0U, // VFNMSUB132PDZrkz 4U, // VFNMSUB132PDm 4U, // VFNMSUB132PDr 4U, // VFNMSUB132PSYm 4U, // VFNMSUB132PSYr 4U, // VFNMSUB132PSZ128m 4U, // VFNMSUB132PSZ128mb 133U, // VFNMSUB132PSZ128mbk 8325U, // VFNMSUB132PSZ128mbkz 0U, // VFNMSUB132PSZ128mk 0U, // VFNMSUB132PSZ128mkz 4U, // VFNMSUB132PSZ128r 0U, // VFNMSUB132PSZ128rk 0U, // VFNMSUB132PSZ128rkz 4U, // VFNMSUB132PSZ256m 4U, // VFNMSUB132PSZ256mb 133U, // VFNMSUB132PSZ256mbk 8325U, // VFNMSUB132PSZ256mbkz 0U, // VFNMSUB132PSZ256mk 0U, // VFNMSUB132PSZ256mkz 4U, // VFNMSUB132PSZ256r 0U, // VFNMSUB132PSZ256rk 0U, // VFNMSUB132PSZ256rkz 4U, // VFNMSUB132PSZm 4U, // VFNMSUB132PSZmb 133U, // VFNMSUB132PSZmbk 8325U, // VFNMSUB132PSZmbkz 0U, // VFNMSUB132PSZmk 0U, // VFNMSUB132PSZmkz 4U, // VFNMSUB132PSZr 4U, // VFNMSUB132PSZrb 0U, // VFNMSUB132PSZrbk 0U, // VFNMSUB132PSZrbkz 0U, // VFNMSUB132PSZrk 0U, // VFNMSUB132PSZrkz 4U, // VFNMSUB132PSm 4U, // VFNMSUB132PSr 4U, // VFNMSUB132SDZm 4U, // VFNMSUB132SDZm_Int 133U, // VFNMSUB132SDZm_Intk 8325U, // VFNMSUB132SDZm_Intkz 4U, // VFNMSUB132SDZr 4U, // VFNMSUB132SDZr_Int 0U, // VFNMSUB132SDZr_Intk 0U, // VFNMSUB132SDZr_Intkz 4U, // VFNMSUB132SDZrb 4U, // VFNMSUB132SDZrb_Int 0U, // VFNMSUB132SDZrb_Intk 0U, // VFNMSUB132SDZrb_Intkz 4U, // VFNMSUB132SDm 4U, // VFNMSUB132SDm_Int 4U, // VFNMSUB132SDr 4U, // VFNMSUB132SDr_Int 4U, // VFNMSUB132SSZm 4U, // VFNMSUB132SSZm_Int 133U, // VFNMSUB132SSZm_Intk 8325U, // VFNMSUB132SSZm_Intkz 4U, // VFNMSUB132SSZr 4U, // VFNMSUB132SSZr_Int 0U, // VFNMSUB132SSZr_Intk 0U, // VFNMSUB132SSZr_Intkz 4U, // VFNMSUB132SSZrb 4U, // VFNMSUB132SSZrb_Int 0U, // VFNMSUB132SSZrb_Intk 0U, // VFNMSUB132SSZrb_Intkz 4U, // VFNMSUB132SSm 4U, // VFNMSUB132SSm_Int 4U, // VFNMSUB132SSr 4U, // VFNMSUB132SSr_Int 4U, // VFNMSUB213PDYm 4U, // VFNMSUB213PDYr 4U, // VFNMSUB213PDZ128m 4U, // VFNMSUB213PDZ128mb 133U, // VFNMSUB213PDZ128mbk 8325U, // VFNMSUB213PDZ128mbkz 0U, // VFNMSUB213PDZ128mk 0U, // VFNMSUB213PDZ128mkz 4U, // VFNMSUB213PDZ128r 0U, // VFNMSUB213PDZ128rk 0U, // VFNMSUB213PDZ128rkz 4U, // VFNMSUB213PDZ256m 4U, // VFNMSUB213PDZ256mb 133U, // VFNMSUB213PDZ256mbk 8325U, // VFNMSUB213PDZ256mbkz 0U, // VFNMSUB213PDZ256mk 0U, // VFNMSUB213PDZ256mkz 4U, // VFNMSUB213PDZ256r 0U, // VFNMSUB213PDZ256rk 0U, // VFNMSUB213PDZ256rkz 4U, // VFNMSUB213PDZm 4U, // VFNMSUB213PDZmb 133U, // VFNMSUB213PDZmbk 8325U, // VFNMSUB213PDZmbkz 0U, // VFNMSUB213PDZmk 0U, // VFNMSUB213PDZmkz 4U, // VFNMSUB213PDZr 4U, // VFNMSUB213PDZrb 0U, // VFNMSUB213PDZrbk 0U, // VFNMSUB213PDZrbkz 0U, // VFNMSUB213PDZrk 0U, // VFNMSUB213PDZrkz 4U, // VFNMSUB213PDm 4U, // VFNMSUB213PDr 4U, // VFNMSUB213PSYm 4U, // VFNMSUB213PSYr 4U, // VFNMSUB213PSZ128m 4U, // VFNMSUB213PSZ128mb 133U, // VFNMSUB213PSZ128mbk 8325U, // VFNMSUB213PSZ128mbkz 0U, // VFNMSUB213PSZ128mk 0U, // VFNMSUB213PSZ128mkz 4U, // VFNMSUB213PSZ128r 0U, // VFNMSUB213PSZ128rk 0U, // VFNMSUB213PSZ128rkz 4U, // VFNMSUB213PSZ256m 4U, // VFNMSUB213PSZ256mb 133U, // VFNMSUB213PSZ256mbk 8325U, // VFNMSUB213PSZ256mbkz 0U, // VFNMSUB213PSZ256mk 0U, // VFNMSUB213PSZ256mkz 4U, // VFNMSUB213PSZ256r 0U, // VFNMSUB213PSZ256rk 0U, // VFNMSUB213PSZ256rkz 4U, // VFNMSUB213PSZm 4U, // VFNMSUB213PSZmb 133U, // VFNMSUB213PSZmbk 8325U, // VFNMSUB213PSZmbkz 0U, // VFNMSUB213PSZmk 0U, // VFNMSUB213PSZmkz 4U, // VFNMSUB213PSZr 4U, // VFNMSUB213PSZrb 0U, // VFNMSUB213PSZrbk 0U, // VFNMSUB213PSZrbkz 0U, // VFNMSUB213PSZrk 0U, // VFNMSUB213PSZrkz 4U, // VFNMSUB213PSm 4U, // VFNMSUB213PSr 4U, // VFNMSUB213SDZm 4U, // VFNMSUB213SDZm_Int 133U, // VFNMSUB213SDZm_Intk 8325U, // VFNMSUB213SDZm_Intkz 4U, // VFNMSUB213SDZr 4U, // VFNMSUB213SDZr_Int 0U, // VFNMSUB213SDZr_Intk 0U, // VFNMSUB213SDZr_Intkz 4U, // VFNMSUB213SDZrb 4U, // VFNMSUB213SDZrb_Int 0U, // VFNMSUB213SDZrb_Intk 0U, // VFNMSUB213SDZrb_Intkz 4U, // VFNMSUB213SDm 4U, // VFNMSUB213SDm_Int 4U, // VFNMSUB213SDr 4U, // VFNMSUB213SDr_Int 4U, // VFNMSUB213SSZm 4U, // VFNMSUB213SSZm_Int 133U, // VFNMSUB213SSZm_Intk 8325U, // VFNMSUB213SSZm_Intkz 4U, // VFNMSUB213SSZr 4U, // VFNMSUB213SSZr_Int 0U, // VFNMSUB213SSZr_Intk 0U, // VFNMSUB213SSZr_Intkz 4U, // VFNMSUB213SSZrb 4U, // VFNMSUB213SSZrb_Int 0U, // VFNMSUB213SSZrb_Intk 0U, // VFNMSUB213SSZrb_Intkz 4U, // VFNMSUB213SSm 4U, // VFNMSUB213SSm_Int 4U, // VFNMSUB213SSr 4U, // VFNMSUB213SSr_Int 4U, // VFNMSUB231PDYm 4U, // VFNMSUB231PDYr 4U, // VFNMSUB231PDZ128m 4U, // VFNMSUB231PDZ128mb 133U, // VFNMSUB231PDZ128mbk 8325U, // VFNMSUB231PDZ128mbkz 0U, // VFNMSUB231PDZ128mk 0U, // VFNMSUB231PDZ128mkz 4U, // VFNMSUB231PDZ128r 0U, // VFNMSUB231PDZ128rk 0U, // VFNMSUB231PDZ128rkz 4U, // VFNMSUB231PDZ256m 4U, // VFNMSUB231PDZ256mb 133U, // VFNMSUB231PDZ256mbk 8325U, // VFNMSUB231PDZ256mbkz 0U, // VFNMSUB231PDZ256mk 0U, // VFNMSUB231PDZ256mkz 4U, // VFNMSUB231PDZ256r 0U, // VFNMSUB231PDZ256rk 0U, // VFNMSUB231PDZ256rkz 4U, // VFNMSUB231PDZm 4U, // VFNMSUB231PDZmb 133U, // VFNMSUB231PDZmbk 8325U, // VFNMSUB231PDZmbkz 0U, // VFNMSUB231PDZmk 0U, // VFNMSUB231PDZmkz 4U, // VFNMSUB231PDZr 4U, // VFNMSUB231PDZrb 0U, // VFNMSUB231PDZrbk 0U, // VFNMSUB231PDZrbkz 0U, // VFNMSUB231PDZrk 0U, // VFNMSUB231PDZrkz 4U, // VFNMSUB231PDm 4U, // VFNMSUB231PDr 4U, // VFNMSUB231PSYm 4U, // VFNMSUB231PSYr 4U, // VFNMSUB231PSZ128m 4U, // VFNMSUB231PSZ128mb 133U, // VFNMSUB231PSZ128mbk 8325U, // VFNMSUB231PSZ128mbkz 0U, // VFNMSUB231PSZ128mk 0U, // VFNMSUB231PSZ128mkz 4U, // VFNMSUB231PSZ128r 0U, // VFNMSUB231PSZ128rk 0U, // VFNMSUB231PSZ128rkz 4U, // VFNMSUB231PSZ256m 4U, // VFNMSUB231PSZ256mb 133U, // VFNMSUB231PSZ256mbk 8325U, // VFNMSUB231PSZ256mbkz 0U, // VFNMSUB231PSZ256mk 0U, // VFNMSUB231PSZ256mkz 4U, // VFNMSUB231PSZ256r 0U, // VFNMSUB231PSZ256rk 0U, // VFNMSUB231PSZ256rkz 4U, // VFNMSUB231PSZm 4U, // VFNMSUB231PSZmb 133U, // VFNMSUB231PSZmbk 8325U, // VFNMSUB231PSZmbkz 0U, // VFNMSUB231PSZmk 0U, // VFNMSUB231PSZmkz 4U, // VFNMSUB231PSZr 4U, // VFNMSUB231PSZrb 0U, // VFNMSUB231PSZrbk 0U, // VFNMSUB231PSZrbkz 0U, // VFNMSUB231PSZrk 0U, // VFNMSUB231PSZrkz 4U, // VFNMSUB231PSm 4U, // VFNMSUB231PSr 4U, // VFNMSUB231SDZm 4U, // VFNMSUB231SDZm_Int 133U, // VFNMSUB231SDZm_Intk 8325U, // VFNMSUB231SDZm_Intkz 4U, // VFNMSUB231SDZr 4U, // VFNMSUB231SDZr_Int 0U, // VFNMSUB231SDZr_Intk 0U, // VFNMSUB231SDZr_Intkz 4U, // VFNMSUB231SDZrb 4U, // VFNMSUB231SDZrb_Int 0U, // VFNMSUB231SDZrb_Intk 0U, // VFNMSUB231SDZrb_Intkz 4U, // VFNMSUB231SDm 4U, // VFNMSUB231SDm_Int 4U, // VFNMSUB231SDr 4U, // VFNMSUB231SDr_Int 4U, // VFNMSUB231SSZm 4U, // VFNMSUB231SSZm_Int 133U, // VFNMSUB231SSZm_Intk 8325U, // VFNMSUB231SSZm_Intkz 4U, // VFNMSUB231SSZr 4U, // VFNMSUB231SSZr_Int 0U, // VFNMSUB231SSZr_Intk 0U, // VFNMSUB231SSZr_Intkz 4U, // VFNMSUB231SSZrb 4U, // VFNMSUB231SSZrb_Int 0U, // VFNMSUB231SSZrb_Intk 0U, // VFNMSUB231SSZrb_Intkz 4U, // VFNMSUB231SSm 4U, // VFNMSUB231SSm_Int 4U, // VFNMSUB231SSr 4U, // VFNMSUB231SSr_Int 72U, // VFNMSUBPD4Ymr 18636U, // VFNMSUBPD4Yrm 18636U, // VFNMSUBPD4Yrr 18636U, // VFNMSUBPD4Yrr_REV 72U, // VFNMSUBPD4mr 18636U, // VFNMSUBPD4rm 18636U, // VFNMSUBPD4rr 18636U, // VFNMSUBPD4rr_REV 72U, // VFNMSUBPS4Ymr 18636U, // VFNMSUBPS4Yrm 18636U, // VFNMSUBPS4Yrr 18636U, // VFNMSUBPS4Yrr_REV 72U, // VFNMSUBPS4mr 18636U, // VFNMSUBPS4rm 18636U, // VFNMSUBPS4rr 18636U, // VFNMSUBPS4rr_REV 18636U, // VFNMSUBSD4mr 18636U, // VFNMSUBSD4mr_Int 18636U, // VFNMSUBSD4rm 18636U, // VFNMSUBSD4rm_Int 18636U, // VFNMSUBSD4rr 18636U, // VFNMSUBSD4rr_Int 18636U, // VFNMSUBSD4rr_Int_REV 18636U, // VFNMSUBSD4rr_REV 18636U, // VFNMSUBSS4mr 18636U, // VFNMSUBSS4mr_Int 18636U, // VFNMSUBSS4rm 18636U, // VFNMSUBSS4rm_Int 18636U, // VFNMSUBSS4rr 18636U, // VFNMSUBSS4rr_Int 18636U, // VFNMSUBSS4rr_Int_REV 18636U, // VFNMSUBSS4rr_REV 0U, // VFPCLASSPDZ128rm 5U, // VFPCLASSPDZ128rmb 1157U, // VFPCLASSPDZ128rmbk 3420U, // VFPCLASSPDZ128rmk 72U, // VFPCLASSPDZ128rr 1156U, // VFPCLASSPDZ128rrk 0U, // VFPCLASSPDZ256rm 5U, // VFPCLASSPDZ256rmb 1157U, // VFPCLASSPDZ256rmbk 3420U, // VFPCLASSPDZ256rmk 72U, // VFPCLASSPDZ256rr 1156U, // VFPCLASSPDZ256rrk 0U, // VFPCLASSPDZrm 5U, // VFPCLASSPDZrmb 1157U, // VFPCLASSPDZrmbk 3420U, // VFPCLASSPDZrmk 72U, // VFPCLASSPDZrr 1156U, // VFPCLASSPDZrrk 0U, // VFPCLASSPSZ128rm 5U, // VFPCLASSPSZ128rmb 1157U, // VFPCLASSPSZ128rmbk 3420U, // VFPCLASSPSZ128rmk 72U, // VFPCLASSPSZ128rr 1156U, // VFPCLASSPSZ128rrk 0U, // VFPCLASSPSZ256rm 5U, // VFPCLASSPSZ256rmb 1157U, // VFPCLASSPSZ256rmbk 3420U, // VFPCLASSPSZ256rmk 72U, // VFPCLASSPSZ256rr 1156U, // VFPCLASSPSZ256rrk 0U, // VFPCLASSPSZrm 5U, // VFPCLASSPSZrmb 1157U, // VFPCLASSPSZrmbk 3420U, // VFPCLASSPSZrmk 72U, // VFPCLASSPSZrr 1156U, // VFPCLASSPSZrrk 4U, // VFPCLASSSDZrm 1156U, // VFPCLASSSDZrmk 72U, // VFPCLASSSDZrr 1156U, // VFPCLASSSDZrrk 4U, // VFPCLASSSSZrm 1156U, // VFPCLASSSSZrmk 72U, // VFPCLASSSSZrr 1156U, // VFPCLASSSSZrrk 0U, // VFRCZPDYrm 0U, // VFRCZPDYrr 0U, // VFRCZPDrm 0U, // VFRCZPDrr 0U, // VFRCZPSYrm 0U, // VFRCZPSYrr 0U, // VFRCZPSrm 0U, // VFRCZPSrr 0U, // VFRCZSDrm 0U, // VFRCZSDrr 0U, // VFRCZSSrm 0U, // VFRCZSSrr 0U, // VGATHERDPDYrm 401U, // VGATHERDPDZ128rm 401U, // VGATHERDPDZ256rm 401U, // VGATHERDPDZrm 0U, // VGATHERDPDrm 0U, // VGATHERDPSYrm 401U, // VGATHERDPSZ128rm 401U, // VGATHERDPSZ256rm 401U, // VGATHERDPSZrm 0U, // VGATHERDPSrm 0U, // VGATHERPF0DPDm 0U, // VGATHERPF0DPSm 0U, // VGATHERPF0QPDm 0U, // VGATHERPF0QPSm 0U, // VGATHERPF1DPDm 0U, // VGATHERPF1DPSm 0U, // VGATHERPF1QPDm 0U, // VGATHERPF1QPSm 0U, // VGATHERQPDYrm 401U, // VGATHERQPDZ128rm 401U, // VGATHERQPDZ256rm 401U, // VGATHERQPDZrm 0U, // VGATHERQPDrm 0U, // VGATHERQPSYrm 604U, // VGATHERQPSZ128rm 401U, // VGATHERQPSZ256rm 401U, // VGATHERQPSZrm 4U, // VGATHERQPSrm 0U, // VGETEXPPDZ128m 0U, // VGETEXPPDZ128mb 3356U, // VGETEXPPDZ128mbk 4444U, // VGETEXPPDZ128mbkz 405U, // VGETEXPPDZ128mk 461U, // VGETEXPPDZ128mkz 0U, // VGETEXPPDZ128r 405U, // VGETEXPPDZ128rk 461U, // VGETEXPPDZ128rkz 0U, // VGETEXPPDZ256m 0U, // VGETEXPPDZ256mb 3356U, // VGETEXPPDZ256mbk 4444U, // VGETEXPPDZ256mbkz 405U, // VGETEXPPDZ256mk 461U, // VGETEXPPDZ256mkz 0U, // VGETEXPPDZ256r 405U, // VGETEXPPDZ256rk 461U, // VGETEXPPDZ256rkz 0U, // VGETEXPPDZm 0U, // VGETEXPPDZmb 3356U, // VGETEXPPDZmbk 4444U, // VGETEXPPDZmbkz 405U, // VGETEXPPDZmk 461U, // VGETEXPPDZmkz 0U, // VGETEXPPDZr 0U, // VGETEXPPDZrb 405U, // VGETEXPPDZrbk 461U, // VGETEXPPDZrbkz 405U, // VGETEXPPDZrk 461U, // VGETEXPPDZrkz 0U, // VGETEXPPSZ128m 0U, // VGETEXPPSZ128mb 3356U, // VGETEXPPSZ128mbk 4444U, // VGETEXPPSZ128mbkz 405U, // VGETEXPPSZ128mk 461U, // VGETEXPPSZ128mkz 0U, // VGETEXPPSZ128r 405U, // VGETEXPPSZ128rk 461U, // VGETEXPPSZ128rkz 0U, // VGETEXPPSZ256m 0U, // VGETEXPPSZ256mb 3356U, // VGETEXPPSZ256mbk 4444U, // VGETEXPPSZ256mbkz 405U, // VGETEXPPSZ256mk 461U, // VGETEXPPSZ256mkz 0U, // VGETEXPPSZ256r 405U, // VGETEXPPSZ256rk 461U, // VGETEXPPSZ256rkz 0U, // VGETEXPPSZm 0U, // VGETEXPPSZmb 3356U, // VGETEXPPSZmbk 4444U, // VGETEXPPSZmbkz 405U, // VGETEXPPSZmk 461U, // VGETEXPPSZmkz 0U, // VGETEXPPSZr 0U, // VGETEXPPSZrb 405U, // VGETEXPPSZrbk 461U, // VGETEXPPSZrbkz 405U, // VGETEXPPSZrk 461U, // VGETEXPPSZrkz 72U, // VGETEXPSDZm 133U, // VGETEXPSDZmk 9348U, // VGETEXPSDZmkz 4U, // VGETEXPSDZr 4U, // VGETEXPSDZrb 0U, // VGETEXPSDZrbk 9348U, // VGETEXPSDZrbkz 0U, // VGETEXPSDZrk 9348U, // VGETEXPSDZrkz 72U, // VGETEXPSSZm 133U, // VGETEXPSSZmk 9348U, // VGETEXPSSZmkz 4U, // VGETEXPSSZr 4U, // VGETEXPSSZrb 0U, // VGETEXPSSZrbk 9348U, // VGETEXPSSZrbkz 0U, // VGETEXPSSZrk 9348U, // VGETEXPSSZrkz 5U, // VGETMANTPDZ128rmbi 133U, // VGETMANTPDZ128rmbik 9349U, // VGETMANTPDZ128rmbikz 0U, // VGETMANTPDZ128rmi 3356U, // VGETMANTPDZ128rmik 4444U, // VGETMANTPDZ128rmikz 72U, // VGETMANTPDZ128rri 133U, // VGETMANTPDZ128rrik 9348U, // VGETMANTPDZ128rrikz 5U, // VGETMANTPDZ256rmbi 133U, // VGETMANTPDZ256rmbik 9349U, // VGETMANTPDZ256rmbikz 0U, // VGETMANTPDZ256rmi 3356U, // VGETMANTPDZ256rmik 4444U, // VGETMANTPDZ256rmikz 72U, // VGETMANTPDZ256rri 133U, // VGETMANTPDZ256rrik 9348U, // VGETMANTPDZ256rrikz 5U, // VGETMANTPDZrmbi 133U, // VGETMANTPDZrmbik 9349U, // VGETMANTPDZrmbikz 0U, // VGETMANTPDZrmi 3356U, // VGETMANTPDZrmik 4444U, // VGETMANTPDZrmikz 72U, // VGETMANTPDZrri 72U, // VGETMANTPDZrrib 133U, // VGETMANTPDZrribk 9348U, // VGETMANTPDZrribkz 133U, // VGETMANTPDZrrik 9348U, // VGETMANTPDZrrikz 5U, // VGETMANTPSZ128rmbi 133U, // VGETMANTPSZ128rmbik 9349U, // VGETMANTPSZ128rmbikz 0U, // VGETMANTPSZ128rmi 3356U, // VGETMANTPSZ128rmik 4444U, // VGETMANTPSZ128rmikz 72U, // VGETMANTPSZ128rri 133U, // VGETMANTPSZ128rrik 9348U, // VGETMANTPSZ128rrikz 5U, // VGETMANTPSZ256rmbi 133U, // VGETMANTPSZ256rmbik 9349U, // VGETMANTPSZ256rmbikz 0U, // VGETMANTPSZ256rmi 3356U, // VGETMANTPSZ256rmik 4444U, // VGETMANTPSZ256rmikz 72U, // VGETMANTPSZ256rri 133U, // VGETMANTPSZ256rrik 9348U, // VGETMANTPSZ256rrikz 5U, // VGETMANTPSZrmbi 133U, // VGETMANTPSZrmbik 9349U, // VGETMANTPSZrmbikz 0U, // VGETMANTPSZrmi 3356U, // VGETMANTPSZrmik 4444U, // VGETMANTPSZrmikz 72U, // VGETMANTPSZrri 72U, // VGETMANTPSZrrib 133U, // VGETMANTPSZrribk 9348U, // VGETMANTPSZrribkz 133U, // VGETMANTPSZrrik 9348U, // VGETMANTPSZrrikz 18636U, // VGETMANTSDZrmi 26832U, // VGETMANTSDZrmik 26836U, // VGETMANTSDZrmikz 18636U, // VGETMANTSDZrri 18636U, // VGETMANTSDZrrib 25U, // VGETMANTSDZrribk 26837U, // VGETMANTSDZrribkz 25U, // VGETMANTSDZrrik 26837U, // VGETMANTSDZrrikz 18636U, // VGETMANTSSZrmi 26832U, // VGETMANTSSZrmik 26836U, // VGETMANTSSZrmikz 18636U, // VGETMANTSSZrri 18636U, // VGETMANTSSZrrib 25U, // VGETMANTSSZrribk 26837U, // VGETMANTSSZrribkz 25U, // VGETMANTSSZrrik 26837U, // VGETMANTSSZrrikz 72U, // VGF2P8AFFINEINVQBYrmi 18636U, // VGF2P8AFFINEINVQBYrri 18637U, // VGF2P8AFFINEINVQBZ128rmbi 26833U, // VGF2P8AFFINEINVQBZ128rmbik 26837U, // VGF2P8AFFINEINVQBZ128rmbikz 72U, // VGF2P8AFFINEINVQBZ128rmi 1U, // VGF2P8AFFINEINVQBZ128rmik 9348U, // VGF2P8AFFINEINVQBZ128rmikz 18636U, // VGF2P8AFFINEINVQBZ128rri 25U, // VGF2P8AFFINEINVQBZ128rrik 26837U, // VGF2P8AFFINEINVQBZ128rrikz 18637U, // VGF2P8AFFINEINVQBZ256rmbi 26833U, // VGF2P8AFFINEINVQBZ256rmbik 26837U, // VGF2P8AFFINEINVQBZ256rmbikz 72U, // VGF2P8AFFINEINVQBZ256rmi 1U, // VGF2P8AFFINEINVQBZ256rmik 9348U, // VGF2P8AFFINEINVQBZ256rmikz 18636U, // VGF2P8AFFINEINVQBZ256rri 25U, // VGF2P8AFFINEINVQBZ256rrik 26837U, // VGF2P8AFFINEINVQBZ256rrikz 18637U, // VGF2P8AFFINEINVQBZrmbi 26833U, // VGF2P8AFFINEINVQBZrmbik 26837U, // VGF2P8AFFINEINVQBZrmbikz 72U, // VGF2P8AFFINEINVQBZrmi 1U, // VGF2P8AFFINEINVQBZrmik 9348U, // VGF2P8AFFINEINVQBZrmikz 18636U, // VGF2P8AFFINEINVQBZrri 25U, // VGF2P8AFFINEINVQBZrrik 26837U, // VGF2P8AFFINEINVQBZrrikz 72U, // VGF2P8AFFINEINVQBrmi 18636U, // VGF2P8AFFINEINVQBrri 72U, // VGF2P8AFFINEQBYrmi 18636U, // VGF2P8AFFINEQBYrri 18637U, // VGF2P8AFFINEQBZ128rmbi 26833U, // VGF2P8AFFINEQBZ128rmbik 26837U, // VGF2P8AFFINEQBZ128rmbikz 72U, // VGF2P8AFFINEQBZ128rmi 1U, // VGF2P8AFFINEQBZ128rmik 9348U, // VGF2P8AFFINEQBZ128rmikz 18636U, // VGF2P8AFFINEQBZ128rri 25U, // VGF2P8AFFINEQBZ128rrik 26837U, // VGF2P8AFFINEQBZ128rrikz 18637U, // VGF2P8AFFINEQBZ256rmbi 26833U, // VGF2P8AFFINEQBZ256rmbik 26837U, // VGF2P8AFFINEQBZ256rmbikz 72U, // VGF2P8AFFINEQBZ256rmi 1U, // VGF2P8AFFINEQBZ256rmik 9348U, // VGF2P8AFFINEQBZ256rmikz 18636U, // VGF2P8AFFINEQBZ256rri 25U, // VGF2P8AFFINEQBZ256rrik 26837U, // VGF2P8AFFINEQBZ256rrikz 18637U, // VGF2P8AFFINEQBZrmbi 26833U, // VGF2P8AFFINEQBZrmbik 26837U, // VGF2P8AFFINEQBZrmbikz 72U, // VGF2P8AFFINEQBZrmi 1U, // VGF2P8AFFINEQBZrmik 9348U, // VGF2P8AFFINEQBZrmikz 18636U, // VGF2P8AFFINEQBZrri 25U, // VGF2P8AFFINEQBZrrik 26837U, // VGF2P8AFFINEQBZrrikz 72U, // VGF2P8AFFINEQBrmi 18636U, // VGF2P8AFFINEQBrri 4U, // VGF2P8MULBYrm 4U, // VGF2P8MULBYrr 4U, // VGF2P8MULBZ128rm 132U, // VGF2P8MULBZ128rmk 9348U, // VGF2P8MULBZ128rmkz 4U, // VGF2P8MULBZ128rr 0U, // VGF2P8MULBZ128rrk 9348U, // VGF2P8MULBZ128rrkz 4U, // VGF2P8MULBZ256rm 132U, // VGF2P8MULBZ256rmk 9348U, // VGF2P8MULBZ256rmkz 4U, // VGF2P8MULBZ256rr 0U, // VGF2P8MULBZ256rrk 9348U, // VGF2P8MULBZ256rrkz 4U, // VGF2P8MULBZrm 132U, // VGF2P8MULBZrmk 9348U, // VGF2P8MULBZrmkz 4U, // VGF2P8MULBZrr 0U, // VGF2P8MULBZrrk 9348U, // VGF2P8MULBZrrkz 4U, // VGF2P8MULBrm 4U, // VGF2P8MULBrr 4U, // VHADDPDYrm 4U, // VHADDPDYrr 4U, // VHADDPDrm 4U, // VHADDPDrr 4U, // VHADDPSYrm 4U, // VHADDPSYrr 4U, // VHADDPSrm 4U, // VHADDPSrr 4U, // VHSUBPDYrm 4U, // VHSUBPDYrr 4U, // VHSUBPDrm 4U, // VHSUBPDrr 4U, // VHSUBPSYrm 4U, // VHSUBPSYrr 4U, // VHSUBPSrm 4U, // VHSUBPSrr 72U, // VINSERTF128rm 18636U, // VINSERTF128rr 72U, // VINSERTF32x4Z256rm 1U, // VINSERTF32x4Z256rmk 9348U, // VINSERTF32x4Z256rmkz 18636U, // VINSERTF32x4Z256rr 25U, // VINSERTF32x4Z256rrk 26837U, // VINSERTF32x4Z256rrkz 72U, // VINSERTF32x4Zrm 1U, // VINSERTF32x4Zrmk 9348U, // VINSERTF32x4Zrmkz 18636U, // VINSERTF32x4Zrr 25U, // VINSERTF32x4Zrrk 26837U, // VINSERTF32x4Zrrkz 72U, // VINSERTF32x8Zrm 1U, // VINSERTF32x8Zrmk 9348U, // VINSERTF32x8Zrmkz 18636U, // VINSERTF32x8Zrr 25U, // VINSERTF32x8Zrrk 26837U, // VINSERTF32x8Zrrkz 72U, // VINSERTF64x2Z256rm 1U, // VINSERTF64x2Z256rmk 9348U, // VINSERTF64x2Z256rmkz 18636U, // VINSERTF64x2Z256rr 25U, // VINSERTF64x2Z256rrk 26837U, // VINSERTF64x2Z256rrkz 72U, // VINSERTF64x2Zrm 1U, // VINSERTF64x2Zrmk 9348U, // VINSERTF64x2Zrmkz 18636U, // VINSERTF64x2Zrr 25U, // VINSERTF64x2Zrrk 26837U, // VINSERTF64x2Zrrkz 72U, // VINSERTF64x4Zrm 1U, // VINSERTF64x4Zrmk 9348U, // VINSERTF64x4Zrmkz 18636U, // VINSERTF64x4Zrr 25U, // VINSERTF64x4Zrrk 26837U, // VINSERTF64x4Zrrkz 72U, // VINSERTI128rm 18636U, // VINSERTI128rr 72U, // VINSERTI32x4Z256rm 1U, // VINSERTI32x4Z256rmk 9348U, // VINSERTI32x4Z256rmkz 18636U, // VINSERTI32x4Z256rr 25U, // VINSERTI32x4Z256rrk 26837U, // VINSERTI32x4Z256rrkz 72U, // VINSERTI32x4Zrm 1U, // VINSERTI32x4Zrmk 9348U, // VINSERTI32x4Zrmkz 18636U, // VINSERTI32x4Zrr 25U, // VINSERTI32x4Zrrk 26837U, // VINSERTI32x4Zrrkz 72U, // VINSERTI32x8Zrm 1U, // VINSERTI32x8Zrmk 9348U, // VINSERTI32x8Zrmkz 18636U, // VINSERTI32x8Zrr 25U, // VINSERTI32x8Zrrk 26837U, // VINSERTI32x8Zrrkz 72U, // VINSERTI64x2Z256rm 1U, // VINSERTI64x2Z256rmk 9348U, // VINSERTI64x2Z256rmkz 18636U, // VINSERTI64x2Z256rr 25U, // VINSERTI64x2Z256rrk 26837U, // VINSERTI64x2Z256rrkz 72U, // VINSERTI64x2Zrm 1U, // VINSERTI64x2Zrmk 9348U, // VINSERTI64x2Zrmkz 18636U, // VINSERTI64x2Zrr 25U, // VINSERTI64x2Zrrk 26837U, // VINSERTI64x2Zrrkz 72U, // VINSERTI64x4Zrm 1U, // VINSERTI64x4Zrmk 9348U, // VINSERTI64x4Zrmkz 18636U, // VINSERTI64x4Zrr 25U, // VINSERTI64x4Zrrk 26837U, // VINSERTI64x4Zrrkz 18636U, // VINSERTPSZrm 18636U, // VINSERTPSZrr 18636U, // VINSERTPSrm 18636U, // VINSERTPSrr 0U, // VLDDQUYrm 0U, // VLDDQUrm 0U, // VLDMXCSR 0U, // VMASKMOVDQU 0U, // VMASKMOVDQU64 2U, // VMASKMOVPDYmr 4U, // VMASKMOVPDYrm 2U, // VMASKMOVPDmr 4U, // VMASKMOVPDrm 2U, // VMASKMOVPSYmr 4U, // VMASKMOVPSYrm 2U, // VMASKMOVPSmr 4U, // VMASKMOVPSrm 4U, // VMAXCPDYrm 4U, // VMAXCPDYrr 4U, // VMAXCPDZ128rm 72U, // VMAXCPDZ128rmb 133U, // VMAXCPDZ128rmbk 9348U, // VMAXCPDZ128rmbkz 0U, // VMAXCPDZ128rmk 9348U, // VMAXCPDZ128rmkz 4U, // VMAXCPDZ128rr 0U, // VMAXCPDZ128rrk 9348U, // VMAXCPDZ128rrkz 4U, // VMAXCPDZ256rm 72U, // VMAXCPDZ256rmb 133U, // VMAXCPDZ256rmbk 9348U, // VMAXCPDZ256rmbkz 0U, // VMAXCPDZ256rmk 9348U, // VMAXCPDZ256rmkz 4U, // VMAXCPDZ256rr 0U, // VMAXCPDZ256rrk 9348U, // VMAXCPDZ256rrkz 4U, // VMAXCPDZrm 72U, // VMAXCPDZrmb 133U, // VMAXCPDZrmbk 9348U, // VMAXCPDZrmbkz 0U, // VMAXCPDZrmk 9348U, // VMAXCPDZrmkz 4U, // VMAXCPDZrr 0U, // VMAXCPDZrrk 9348U, // VMAXCPDZrrkz 4U, // VMAXCPDrm 4U, // VMAXCPDrr 4U, // VMAXCPSYrm 4U, // VMAXCPSYrr 4U, // VMAXCPSZ128rm 72U, // VMAXCPSZ128rmb 133U, // VMAXCPSZ128rmbk 9348U, // VMAXCPSZ128rmbkz 0U, // VMAXCPSZ128rmk 9348U, // VMAXCPSZ128rmkz 4U, // VMAXCPSZ128rr 0U, // VMAXCPSZ128rrk 9348U, // VMAXCPSZ128rrkz 4U, // VMAXCPSZ256rm 72U, // VMAXCPSZ256rmb 133U, // VMAXCPSZ256rmbk 9348U, // VMAXCPSZ256rmbkz 0U, // VMAXCPSZ256rmk 9348U, // VMAXCPSZ256rmkz 4U, // VMAXCPSZ256rr 0U, // VMAXCPSZ256rrk 9348U, // VMAXCPSZ256rrkz 4U, // VMAXCPSZrm 72U, // VMAXCPSZrmb 133U, // VMAXCPSZrmbk 9348U, // VMAXCPSZrmbkz 0U, // VMAXCPSZrmk 9348U, // VMAXCPSZrmkz 4U, // VMAXCPSZrr 0U, // VMAXCPSZrrk 9348U, // VMAXCPSZrrkz 4U, // VMAXCPSrm 4U, // VMAXCPSrr 72U, // VMAXCSDZrm 4U, // VMAXCSDZrr 72U, // VMAXCSDrm 4U, // VMAXCSDrr 72U, // VMAXCSSZrm 4U, // VMAXCSSZrr 72U, // VMAXCSSrm 4U, // VMAXCSSrr 4U, // VMAXPDYrm 4U, // VMAXPDYrr 4U, // VMAXPDZ128rm 72U, // VMAXPDZ128rmb 133U, // VMAXPDZ128rmbk 9348U, // VMAXPDZ128rmbkz 0U, // VMAXPDZ128rmk 9348U, // VMAXPDZ128rmkz 4U, // VMAXPDZ128rr 0U, // VMAXPDZ128rrk 9348U, // VMAXPDZ128rrkz 4U, // VMAXPDZ256rm 72U, // VMAXPDZ256rmb 133U, // VMAXPDZ256rmbk 9348U, // VMAXPDZ256rmbkz 0U, // VMAXPDZ256rmk 9348U, // VMAXPDZ256rmkz 4U, // VMAXPDZ256rr 0U, // VMAXPDZ256rrk 9348U, // VMAXPDZ256rrkz 4U, // VMAXPDZrm 72U, // VMAXPDZrmb 133U, // VMAXPDZrmbk 9348U, // VMAXPDZrmbkz 0U, // VMAXPDZrmk 9348U, // VMAXPDZrmkz 4U, // VMAXPDZrr 4U, // VMAXPDZrrb 0U, // VMAXPDZrrbk 9348U, // VMAXPDZrrbkz 0U, // VMAXPDZrrk 9348U, // VMAXPDZrrkz 4U, // VMAXPDrm 4U, // VMAXPDrr 4U, // VMAXPSYrm 4U, // VMAXPSYrr 4U, // VMAXPSZ128rm 72U, // VMAXPSZ128rmb 133U, // VMAXPSZ128rmbk 9348U, // VMAXPSZ128rmbkz 0U, // VMAXPSZ128rmk 9348U, // VMAXPSZ128rmkz 4U, // VMAXPSZ128rr 0U, // VMAXPSZ128rrk 9348U, // VMAXPSZ128rrkz 4U, // VMAXPSZ256rm 72U, // VMAXPSZ256rmb 133U, // VMAXPSZ256rmbk 9348U, // VMAXPSZ256rmbkz 0U, // VMAXPSZ256rmk 9348U, // VMAXPSZ256rmkz 4U, // VMAXPSZ256rr 0U, // VMAXPSZ256rrk 9348U, // VMAXPSZ256rrkz 4U, // VMAXPSZrm 72U, // VMAXPSZrmb 133U, // VMAXPSZrmbk 9348U, // VMAXPSZrmbkz 0U, // VMAXPSZrmk 9348U, // VMAXPSZrmkz 4U, // VMAXPSZrr 4U, // VMAXPSZrrb 0U, // VMAXPSZrrbk 9348U, // VMAXPSZrrbkz 0U, // VMAXPSZrrk 9348U, // VMAXPSZrrkz 4U, // VMAXPSrm 4U, // VMAXPSrr 72U, // VMAXSDZrm 72U, // VMAXSDZrm_Int 133U, // VMAXSDZrm_Intk 9348U, // VMAXSDZrm_Intkz 4U, // VMAXSDZrr 4U, // VMAXSDZrr_Int 0U, // VMAXSDZrr_Intk 9348U, // VMAXSDZrr_Intkz 4U, // VMAXSDZrrb_Int 0U, // VMAXSDZrrb_Intk 9348U, // VMAXSDZrrb_Intkz 72U, // VMAXSDrm 72U, // VMAXSDrm_Int 4U, // VMAXSDrr 4U, // VMAXSDrr_Int 72U, // VMAXSSZrm 72U, // VMAXSSZrm_Int 133U, // VMAXSSZrm_Intk 9348U, // VMAXSSZrm_Intkz 4U, // VMAXSSZrr 4U, // VMAXSSZrr_Int 0U, // VMAXSSZrr_Intk 9348U, // VMAXSSZrr_Intkz 4U, // VMAXSSZrrb_Int 0U, // VMAXSSZrrb_Intk 9348U, // VMAXSSZrrb_Intkz 72U, // VMAXSSrm 72U, // VMAXSSrm_Int 4U, // VMAXSSrr 4U, // VMAXSSrr_Int 0U, // VMCALL 0U, // VMCLEARm 0U, // VMFUNC 4U, // VMINCPDYrm 4U, // VMINCPDYrr 4U, // VMINCPDZ128rm 72U, // VMINCPDZ128rmb 133U, // VMINCPDZ128rmbk 9348U, // VMINCPDZ128rmbkz 0U, // VMINCPDZ128rmk 9348U, // VMINCPDZ128rmkz 4U, // VMINCPDZ128rr 0U, // VMINCPDZ128rrk 9348U, // VMINCPDZ128rrkz 4U, // VMINCPDZ256rm 72U, // VMINCPDZ256rmb 133U, // VMINCPDZ256rmbk 9348U, // VMINCPDZ256rmbkz 0U, // VMINCPDZ256rmk 9348U, // VMINCPDZ256rmkz 4U, // VMINCPDZ256rr 0U, // VMINCPDZ256rrk 9348U, // VMINCPDZ256rrkz 4U, // VMINCPDZrm 72U, // VMINCPDZrmb 133U, // VMINCPDZrmbk 9348U, // VMINCPDZrmbkz 0U, // VMINCPDZrmk 9348U, // VMINCPDZrmkz 4U, // VMINCPDZrr 0U, // VMINCPDZrrk 9348U, // VMINCPDZrrkz 4U, // VMINCPDrm 4U, // VMINCPDrr 4U, // VMINCPSYrm 4U, // VMINCPSYrr 4U, // VMINCPSZ128rm 72U, // VMINCPSZ128rmb 133U, // VMINCPSZ128rmbk 9348U, // VMINCPSZ128rmbkz 0U, // VMINCPSZ128rmk 9348U, // VMINCPSZ128rmkz 4U, // VMINCPSZ128rr 0U, // VMINCPSZ128rrk 9348U, // VMINCPSZ128rrkz 4U, // VMINCPSZ256rm 72U, // VMINCPSZ256rmb 133U, // VMINCPSZ256rmbk 9348U, // VMINCPSZ256rmbkz 0U, // VMINCPSZ256rmk 9348U, // VMINCPSZ256rmkz 4U, // VMINCPSZ256rr 0U, // VMINCPSZ256rrk 9348U, // VMINCPSZ256rrkz 4U, // VMINCPSZrm 72U, // VMINCPSZrmb 133U, // VMINCPSZrmbk 9348U, // VMINCPSZrmbkz 0U, // VMINCPSZrmk 9348U, // VMINCPSZrmkz 4U, // VMINCPSZrr 0U, // VMINCPSZrrk 9348U, // VMINCPSZrrkz 4U, // VMINCPSrm 4U, // VMINCPSrr 72U, // VMINCSDZrm 4U, // VMINCSDZrr 72U, // VMINCSDrm 4U, // VMINCSDrr 72U, // VMINCSSZrm 4U, // VMINCSSZrr 72U, // VMINCSSrm 4U, // VMINCSSrr 4U, // VMINPDYrm 4U, // VMINPDYrr 4U, // VMINPDZ128rm 72U, // VMINPDZ128rmb 133U, // VMINPDZ128rmbk 9348U, // VMINPDZ128rmbkz 0U, // VMINPDZ128rmk 9348U, // VMINPDZ128rmkz 4U, // VMINPDZ128rr 0U, // VMINPDZ128rrk 9348U, // VMINPDZ128rrkz 4U, // VMINPDZ256rm 72U, // VMINPDZ256rmb 133U, // VMINPDZ256rmbk 9348U, // VMINPDZ256rmbkz 0U, // VMINPDZ256rmk 9348U, // VMINPDZ256rmkz 4U, // VMINPDZ256rr 0U, // VMINPDZ256rrk 9348U, // VMINPDZ256rrkz 4U, // VMINPDZrm 72U, // VMINPDZrmb 133U, // VMINPDZrmbk 9348U, // VMINPDZrmbkz 0U, // VMINPDZrmk 9348U, // VMINPDZrmkz 4U, // VMINPDZrr 4U, // VMINPDZrrb 0U, // VMINPDZrrbk 9348U, // VMINPDZrrbkz 0U, // VMINPDZrrk 9348U, // VMINPDZrrkz 4U, // VMINPDrm 4U, // VMINPDrr 4U, // VMINPSYrm 4U, // VMINPSYrr 4U, // VMINPSZ128rm 72U, // VMINPSZ128rmb 133U, // VMINPSZ128rmbk 9348U, // VMINPSZ128rmbkz 0U, // VMINPSZ128rmk 9348U, // VMINPSZ128rmkz 4U, // VMINPSZ128rr 0U, // VMINPSZ128rrk 9348U, // VMINPSZ128rrkz 4U, // VMINPSZ256rm 72U, // VMINPSZ256rmb 133U, // VMINPSZ256rmbk 9348U, // VMINPSZ256rmbkz 0U, // VMINPSZ256rmk 9348U, // VMINPSZ256rmkz 4U, // VMINPSZ256rr 0U, // VMINPSZ256rrk 9348U, // VMINPSZ256rrkz 4U, // VMINPSZrm 72U, // VMINPSZrmb 133U, // VMINPSZrmbk 9348U, // VMINPSZrmbkz 0U, // VMINPSZrmk 9348U, // VMINPSZrmkz 4U, // VMINPSZrr 4U, // VMINPSZrrb 0U, // VMINPSZrrbk 9348U, // VMINPSZrrbkz 0U, // VMINPSZrrk 9348U, // VMINPSZrrkz 4U, // VMINPSrm 4U, // VMINPSrr 72U, // VMINSDZrm 72U, // VMINSDZrm_Int 133U, // VMINSDZrm_Intk 9348U, // VMINSDZrm_Intkz 4U, // VMINSDZrr 4U, // VMINSDZrr_Int 0U, // VMINSDZrr_Intk 9348U, // VMINSDZrr_Intkz 4U, // VMINSDZrrb_Int 0U, // VMINSDZrrb_Intk 9348U, // VMINSDZrrb_Intkz 72U, // VMINSDrm 72U, // VMINSDrm_Int 4U, // VMINSDrr 4U, // VMINSDrr_Int 72U, // VMINSSZrm 72U, // VMINSSZrm_Int 133U, // VMINSSZrm_Intk 9348U, // VMINSSZrm_Intkz 4U, // VMINSSZrr 4U, // VMINSSZrr_Int 0U, // VMINSSZrr_Intk 9348U, // VMINSSZrr_Intkz 4U, // VMINSSZrrb_Int 0U, // VMINSSZrrb_Intk 9348U, // VMINSSZrrb_Intkz 72U, // VMINSSrm 72U, // VMINSSrm_Int 4U, // VMINSSrr 4U, // VMINSSrr_Int 0U, // VMLAUNCH 0U, // VMLOAD32 0U, // VMLOAD64 0U, // VMMCALL 0U, // VMOV64toPQIZrm 0U, // VMOV64toPQIZrr 0U, // VMOV64toPQIrm 0U, // VMOV64toPQIrr 0U, // VMOV64toSDZrm 0U, // VMOV64toSDZrr 0U, // VMOV64toSDrm 0U, // VMOV64toSDrr 0U, // VMOVAPDYmr 0U, // VMOVAPDYrm 0U, // VMOVAPDYrr 0U, // VMOVAPDYrr_REV 0U, // VMOVAPDZ128mr 49U, // VMOVAPDZ128mrk 0U, // VMOVAPDZ128rm 405U, // VMOVAPDZ128rmk 461U, // VMOVAPDZ128rmkz 0U, // VMOVAPDZ128rr 0U, // VMOVAPDZ128rr_REV 405U, // VMOVAPDZ128rrk 397U, // VMOVAPDZ128rrk_REV 461U, // VMOVAPDZ128rrkz 461U, // VMOVAPDZ128rrkz_REV 0U, // VMOVAPDZ256mr 49U, // VMOVAPDZ256mrk 0U, // VMOVAPDZ256rm 405U, // VMOVAPDZ256rmk 461U, // VMOVAPDZ256rmkz 0U, // VMOVAPDZ256rr 0U, // VMOVAPDZ256rr_REV 405U, // VMOVAPDZ256rrk 397U, // VMOVAPDZ256rrk_REV 461U, // VMOVAPDZ256rrkz 461U, // VMOVAPDZ256rrkz_REV 0U, // VMOVAPDZmr 49U, // VMOVAPDZmrk 0U, // VMOVAPDZrm 405U, // VMOVAPDZrmk 461U, // VMOVAPDZrmkz 0U, // VMOVAPDZrr 0U, // VMOVAPDZrr_REV 405U, // VMOVAPDZrrk 397U, // VMOVAPDZrrk_REV 461U, // VMOVAPDZrrkz 461U, // VMOVAPDZrrkz_REV 0U, // VMOVAPDmr 0U, // VMOVAPDrm 0U, // VMOVAPDrr 0U, // VMOVAPDrr_REV 0U, // VMOVAPSYmr 0U, // VMOVAPSYrm 0U, // VMOVAPSYrr 0U, // VMOVAPSYrr_REV 0U, // VMOVAPSZ128mr 49U, // VMOVAPSZ128mrk 0U, // VMOVAPSZ128rm 405U, // VMOVAPSZ128rmk 461U, // VMOVAPSZ128rmkz 0U, // VMOVAPSZ128rr 0U, // VMOVAPSZ128rr_REV 405U, // VMOVAPSZ128rrk 397U, // VMOVAPSZ128rrk_REV 461U, // VMOVAPSZ128rrkz 461U, // VMOVAPSZ128rrkz_REV 0U, // VMOVAPSZ256mr 49U, // VMOVAPSZ256mrk 0U, // VMOVAPSZ256rm 405U, // VMOVAPSZ256rmk 461U, // VMOVAPSZ256rmkz 0U, // VMOVAPSZ256rr 0U, // VMOVAPSZ256rr_REV 405U, // VMOVAPSZ256rrk 397U, // VMOVAPSZ256rrk_REV 461U, // VMOVAPSZ256rrkz 461U, // VMOVAPSZ256rrkz_REV 0U, // VMOVAPSZmr 49U, // VMOVAPSZmrk 0U, // VMOVAPSZrm 405U, // VMOVAPSZrmk 461U, // VMOVAPSZrmkz 0U, // VMOVAPSZrr 0U, // VMOVAPSZrr_REV 405U, // VMOVAPSZrrk 397U, // VMOVAPSZrrk_REV 461U, // VMOVAPSZrrkz 461U, // VMOVAPSZrrkz_REV 0U, // VMOVAPSmr 0U, // VMOVAPSrm 0U, // VMOVAPSrr 0U, // VMOVAPSrr_REV 0U, // VMOVDDUPYrm 0U, // VMOVDDUPYrr 0U, // VMOVDDUPZ128rm 3356U, // VMOVDDUPZ128rmk 4444U, // VMOVDDUPZ128rmkz 0U, // VMOVDDUPZ128rr 405U, // VMOVDDUPZ128rrk 461U, // VMOVDDUPZ128rrkz 0U, // VMOVDDUPZ256rm 405U, // VMOVDDUPZ256rmk 461U, // VMOVDDUPZ256rmkz 0U, // VMOVDDUPZ256rr 405U, // VMOVDDUPZ256rrk 461U, // VMOVDDUPZ256rrkz 0U, // VMOVDDUPZrm 405U, // VMOVDDUPZrmk 461U, // VMOVDDUPZrmkz 0U, // VMOVDDUPZrr 405U, // VMOVDDUPZrrk 461U, // VMOVDDUPZrrkz 0U, // VMOVDDUPrm 0U, // VMOVDDUPrr 0U, // VMOVDI2PDIZrm 0U, // VMOVDI2PDIZrr 0U, // VMOVDI2PDIrm 0U, // VMOVDI2PDIrr 0U, // VMOVDI2SSZrm 0U, // VMOVDI2SSZrr 0U, // VMOVDI2SSrm 0U, // VMOVDI2SSrr 0U, // VMOVDQA32Z128mr 49U, // VMOVDQA32Z128mrk 0U, // VMOVDQA32Z128rm 405U, // VMOVDQA32Z128rmk 461U, // VMOVDQA32Z128rmkz 0U, // VMOVDQA32Z128rr 0U, // VMOVDQA32Z128rr_REV 405U, // VMOVDQA32Z128rrk 397U, // VMOVDQA32Z128rrk_REV 461U, // VMOVDQA32Z128rrkz 461U, // VMOVDQA32Z128rrkz_REV 0U, // VMOVDQA32Z256mr 49U, // VMOVDQA32Z256mrk 0U, // VMOVDQA32Z256rm 405U, // VMOVDQA32Z256rmk 461U, // VMOVDQA32Z256rmkz 0U, // VMOVDQA32Z256rr 0U, // VMOVDQA32Z256rr_REV 405U, // VMOVDQA32Z256rrk 397U, // VMOVDQA32Z256rrk_REV 461U, // VMOVDQA32Z256rrkz 461U, // VMOVDQA32Z256rrkz_REV 0U, // VMOVDQA32Zmr 49U, // VMOVDQA32Zmrk 0U, // VMOVDQA32Zrm 405U, // VMOVDQA32Zrmk 461U, // VMOVDQA32Zrmkz 0U, // VMOVDQA32Zrr 0U, // VMOVDQA32Zrr_REV 405U, // VMOVDQA32Zrrk 397U, // VMOVDQA32Zrrk_REV 461U, // VMOVDQA32Zrrkz 461U, // VMOVDQA32Zrrkz_REV 0U, // VMOVDQA64Z128mr 49U, // VMOVDQA64Z128mrk 0U, // VMOVDQA64Z128rm 405U, // VMOVDQA64Z128rmk 461U, // VMOVDQA64Z128rmkz 0U, // VMOVDQA64Z128rr 0U, // VMOVDQA64Z128rr_REV 405U, // VMOVDQA64Z128rrk 397U, // VMOVDQA64Z128rrk_REV 461U, // VMOVDQA64Z128rrkz 461U, // VMOVDQA64Z128rrkz_REV 0U, // VMOVDQA64Z256mr 49U, // VMOVDQA64Z256mrk 0U, // VMOVDQA64Z256rm 405U, // VMOVDQA64Z256rmk 461U, // VMOVDQA64Z256rmkz 0U, // VMOVDQA64Z256rr 0U, // VMOVDQA64Z256rr_REV 405U, // VMOVDQA64Z256rrk 397U, // VMOVDQA64Z256rrk_REV 461U, // VMOVDQA64Z256rrkz 461U, // VMOVDQA64Z256rrkz_REV 0U, // VMOVDQA64Zmr 49U, // VMOVDQA64Zmrk 0U, // VMOVDQA64Zrm 405U, // VMOVDQA64Zrmk 461U, // VMOVDQA64Zrmkz 0U, // VMOVDQA64Zrr 0U, // VMOVDQA64Zrr_REV 405U, // VMOVDQA64Zrrk 397U, // VMOVDQA64Zrrk_REV 461U, // VMOVDQA64Zrrkz 461U, // VMOVDQA64Zrrkz_REV 0U, // VMOVDQAYmr 0U, // VMOVDQAYrm 0U, // VMOVDQAYrr 0U, // VMOVDQAYrr_REV 0U, // VMOVDQAmr 0U, // VMOVDQArm 0U, // VMOVDQArr 0U, // VMOVDQArr_REV 0U, // VMOVDQU16Z128mr 49U, // VMOVDQU16Z128mrk 0U, // VMOVDQU16Z128rm 405U, // VMOVDQU16Z128rmk 461U, // VMOVDQU16Z128rmkz 0U, // VMOVDQU16Z128rr 0U, // VMOVDQU16Z128rr_REV 405U, // VMOVDQU16Z128rrk 397U, // VMOVDQU16Z128rrk_REV 461U, // VMOVDQU16Z128rrkz 461U, // VMOVDQU16Z128rrkz_REV 0U, // VMOVDQU16Z256mr 49U, // VMOVDQU16Z256mrk 0U, // VMOVDQU16Z256rm 405U, // VMOVDQU16Z256rmk 461U, // VMOVDQU16Z256rmkz 0U, // VMOVDQU16Z256rr 0U, // VMOVDQU16Z256rr_REV 405U, // VMOVDQU16Z256rrk 397U, // VMOVDQU16Z256rrk_REV 461U, // VMOVDQU16Z256rrkz 461U, // VMOVDQU16Z256rrkz_REV 0U, // VMOVDQU16Zmr 49U, // VMOVDQU16Zmrk 0U, // VMOVDQU16Zrm 405U, // VMOVDQU16Zrmk 461U, // VMOVDQU16Zrmkz 0U, // VMOVDQU16Zrr 0U, // VMOVDQU16Zrr_REV 405U, // VMOVDQU16Zrrk 397U, // VMOVDQU16Zrrk_REV 461U, // VMOVDQU16Zrrkz 461U, // VMOVDQU16Zrrkz_REV 0U, // VMOVDQU32Z128mr 49U, // VMOVDQU32Z128mrk 0U, // VMOVDQU32Z128rm 405U, // VMOVDQU32Z128rmk 461U, // VMOVDQU32Z128rmkz 0U, // VMOVDQU32Z128rr 0U, // VMOVDQU32Z128rr_REV 405U, // VMOVDQU32Z128rrk 397U, // VMOVDQU32Z128rrk_REV 461U, // VMOVDQU32Z128rrkz 461U, // VMOVDQU32Z128rrkz_REV 0U, // VMOVDQU32Z256mr 49U, // VMOVDQU32Z256mrk 0U, // VMOVDQU32Z256rm 405U, // VMOVDQU32Z256rmk 461U, // VMOVDQU32Z256rmkz 0U, // VMOVDQU32Z256rr 0U, // VMOVDQU32Z256rr_REV 405U, // VMOVDQU32Z256rrk 397U, // VMOVDQU32Z256rrk_REV 461U, // VMOVDQU32Z256rrkz 461U, // VMOVDQU32Z256rrkz_REV 0U, // VMOVDQU32Zmr 49U, // VMOVDQU32Zmrk 0U, // VMOVDQU32Zrm 405U, // VMOVDQU32Zrmk 461U, // VMOVDQU32Zrmkz 0U, // VMOVDQU32Zrr 0U, // VMOVDQU32Zrr_REV 405U, // VMOVDQU32Zrrk 397U, // VMOVDQU32Zrrk_REV 461U, // VMOVDQU32Zrrkz 461U, // VMOVDQU32Zrrkz_REV 0U, // VMOVDQU64Z128mr 49U, // VMOVDQU64Z128mrk 0U, // VMOVDQU64Z128rm 405U, // VMOVDQU64Z128rmk 461U, // VMOVDQU64Z128rmkz 0U, // VMOVDQU64Z128rr 0U, // VMOVDQU64Z128rr_REV 405U, // VMOVDQU64Z128rrk 397U, // VMOVDQU64Z128rrk_REV 461U, // VMOVDQU64Z128rrkz 461U, // VMOVDQU64Z128rrkz_REV 0U, // VMOVDQU64Z256mr 49U, // VMOVDQU64Z256mrk 0U, // VMOVDQU64Z256rm 405U, // VMOVDQU64Z256rmk 461U, // VMOVDQU64Z256rmkz 0U, // VMOVDQU64Z256rr 0U, // VMOVDQU64Z256rr_REV 405U, // VMOVDQU64Z256rrk 397U, // VMOVDQU64Z256rrk_REV 461U, // VMOVDQU64Z256rrkz 461U, // VMOVDQU64Z256rrkz_REV 0U, // VMOVDQU64Zmr 49U, // VMOVDQU64Zmrk 0U, // VMOVDQU64Zrm 405U, // VMOVDQU64Zrmk 461U, // VMOVDQU64Zrmkz 0U, // VMOVDQU64Zrr 0U, // VMOVDQU64Zrr_REV 405U, // VMOVDQU64Zrrk 397U, // VMOVDQU64Zrrk_REV 461U, // VMOVDQU64Zrrkz 461U, // VMOVDQU64Zrrkz_REV 0U, // VMOVDQU8Z128mr 49U, // VMOVDQU8Z128mrk 0U, // VMOVDQU8Z128rm 405U, // VMOVDQU8Z128rmk 461U, // VMOVDQU8Z128rmkz 0U, // VMOVDQU8Z128rr 0U, // VMOVDQU8Z128rr_REV 405U, // VMOVDQU8Z128rrk 397U, // VMOVDQU8Z128rrk_REV 461U, // VMOVDQU8Z128rrkz 461U, // VMOVDQU8Z128rrkz_REV 0U, // VMOVDQU8Z256mr 49U, // VMOVDQU8Z256mrk 0U, // VMOVDQU8Z256rm 405U, // VMOVDQU8Z256rmk 461U, // VMOVDQU8Z256rmkz 0U, // VMOVDQU8Z256rr 0U, // VMOVDQU8Z256rr_REV 405U, // VMOVDQU8Z256rrk 397U, // VMOVDQU8Z256rrk_REV 461U, // VMOVDQU8Z256rrkz 461U, // VMOVDQU8Z256rrkz_REV 0U, // VMOVDQU8Zmr 49U, // VMOVDQU8Zmrk 0U, // VMOVDQU8Zrm 405U, // VMOVDQU8Zrmk 461U, // VMOVDQU8Zrmkz 0U, // VMOVDQU8Zrr 0U, // VMOVDQU8Zrr_REV 405U, // VMOVDQU8Zrrk 397U, // VMOVDQU8Zrrk_REV 461U, // VMOVDQU8Zrrkz 461U, // VMOVDQU8Zrrkz_REV 0U, // VMOVDQUYmr 0U, // VMOVDQUYrm 0U, // VMOVDQUYrr 0U, // VMOVDQUYrr_REV 0U, // VMOVDQUmr 0U, // VMOVDQUrm 0U, // VMOVDQUrr 0U, // VMOVDQUrr_REV 4U, // VMOVHLPSZrr 4U, // VMOVHLPSrr 0U, // VMOVHPDZ128mr 72U, // VMOVHPDZ128rm 0U, // VMOVHPDmr 72U, // VMOVHPDrm 0U, // VMOVHPSZ128mr 72U, // VMOVHPSZ128rm 0U, // VMOVHPSmr 72U, // VMOVHPSrm 4U, // VMOVLHPSZrr 4U, // VMOVLHPSrr 0U, // VMOVLPDZ128mr 72U, // VMOVLPDZ128rm 0U, // VMOVLPDmr 72U, // VMOVLPDrm 0U, // VMOVLPSZ128mr 72U, // VMOVLPSZ128rm 0U, // VMOVLPSmr 72U, // VMOVLPSrm 0U, // VMOVMSKPDYrr 0U, // VMOVMSKPDrr 0U, // VMOVMSKPSYrr 0U, // VMOVMSKPSrr 0U, // VMOVNTDQAYrm 0U, // VMOVNTDQAZ128rm 0U, // VMOVNTDQAZ256rm 0U, // VMOVNTDQAZrm 0U, // VMOVNTDQArm 0U, // VMOVNTDQYmr 0U, // VMOVNTDQZ128mr 0U, // VMOVNTDQZ256mr 0U, // VMOVNTDQZmr 0U, // VMOVNTDQmr 0U, // VMOVNTPDYmr 0U, // VMOVNTPDZ128mr 0U, // VMOVNTPDZ256mr 0U, // VMOVNTPDZmr 0U, // VMOVNTPDmr 0U, // VMOVNTPSYmr 0U, // VMOVNTPSZ128mr 0U, // VMOVNTPSZ256mr 0U, // VMOVNTPSZmr 0U, // VMOVNTPSmr 0U, // VMOVPDI2DIZmr 0U, // VMOVPDI2DIZrr 0U, // VMOVPDI2DImr 0U, // VMOVPDI2DIrr 0U, // VMOVPQI2QIZmr 0U, // VMOVPQI2QIZrr 0U, // VMOVPQI2QImr 0U, // VMOVPQI2QIrr 0U, // VMOVPQIto64Zmr 0U, // VMOVPQIto64Zrr 0U, // VMOVPQIto64mr 0U, // VMOVPQIto64rr 0U, // VMOVQI2PQIZrm 0U, // VMOVQI2PQIrm 0U, // VMOVSDZmr 49U, // VMOVSDZmrk 0U, // VMOVSDZrm 3356U, // VMOVSDZrmk 4444U, // VMOVSDZrmkz 4U, // VMOVSDZrr 4U, // VMOVSDZrr_REV 0U, // VMOVSDZrrk 0U, // VMOVSDZrrk_REV 9348U, // VMOVSDZrrkz 9348U, // VMOVSDZrrkz_REV 0U, // VMOVSDmr 0U, // VMOVSDrm 4U, // VMOVSDrr 4U, // VMOVSDrr_REV 0U, // VMOVSDto64Zmr 0U, // VMOVSDto64Zrr 0U, // VMOVSDto64mr 0U, // VMOVSDto64rr 0U, // VMOVSHDUPYrm 0U, // VMOVSHDUPYrr 0U, // VMOVSHDUPZ128rm 405U, // VMOVSHDUPZ128rmk 461U, // VMOVSHDUPZ128rmkz 0U, // VMOVSHDUPZ128rr 405U, // VMOVSHDUPZ128rrk 461U, // VMOVSHDUPZ128rrkz 0U, // VMOVSHDUPZ256rm 405U, // VMOVSHDUPZ256rmk 461U, // VMOVSHDUPZ256rmkz 0U, // VMOVSHDUPZ256rr 405U, // VMOVSHDUPZ256rrk 461U, // VMOVSHDUPZ256rrkz 0U, // VMOVSHDUPZrm 405U, // VMOVSHDUPZrmk 461U, // VMOVSHDUPZrmkz 0U, // VMOVSHDUPZrr 405U, // VMOVSHDUPZrrk 461U, // VMOVSHDUPZrrkz 0U, // VMOVSHDUPrm 0U, // VMOVSHDUPrr 0U, // VMOVSLDUPYrm 0U, // VMOVSLDUPYrr 0U, // VMOVSLDUPZ128rm 405U, // VMOVSLDUPZ128rmk 461U, // VMOVSLDUPZ128rmkz 0U, // VMOVSLDUPZ128rr 405U, // VMOVSLDUPZ128rrk 461U, // VMOVSLDUPZ128rrkz 0U, // VMOVSLDUPZ256rm 405U, // VMOVSLDUPZ256rmk 461U, // VMOVSLDUPZ256rmkz 0U, // VMOVSLDUPZ256rr 405U, // VMOVSLDUPZ256rrk 461U, // VMOVSLDUPZ256rrkz 0U, // VMOVSLDUPZrm 405U, // VMOVSLDUPZrmk 461U, // VMOVSLDUPZrmkz 0U, // VMOVSLDUPZrr 405U, // VMOVSLDUPZrrk 461U, // VMOVSLDUPZrrkz 0U, // VMOVSLDUPrm 0U, // VMOVSLDUPrr 0U, // VMOVSS2DIZmr 0U, // VMOVSS2DIZrr 0U, // VMOVSS2DImr 0U, // VMOVSS2DIrr 0U, // VMOVSSZmr 49U, // VMOVSSZmrk 0U, // VMOVSSZrm 3356U, // VMOVSSZrmk 4444U, // VMOVSSZrmkz 4U, // VMOVSSZrr 4U, // VMOVSSZrr_REV 0U, // VMOVSSZrrk 0U, // VMOVSSZrrk_REV 9348U, // VMOVSSZrrkz 9348U, // VMOVSSZrrkz_REV 0U, // VMOVSSmr 0U, // VMOVSSrm 4U, // VMOVSSrr 4U, // VMOVSSrr_REV 0U, // VMOVUPDYmr 0U, // VMOVUPDYrm 0U, // VMOVUPDYrr 0U, // VMOVUPDYrr_REV 0U, // VMOVUPDZ128mr 49U, // VMOVUPDZ128mrk 0U, // VMOVUPDZ128rm 405U, // VMOVUPDZ128rmk 461U, // VMOVUPDZ128rmkz 0U, // VMOVUPDZ128rr 0U, // VMOVUPDZ128rr_REV 405U, // VMOVUPDZ128rrk 397U, // VMOVUPDZ128rrk_REV 461U, // VMOVUPDZ128rrkz 461U, // VMOVUPDZ128rrkz_REV 0U, // VMOVUPDZ256mr 49U, // VMOVUPDZ256mrk 0U, // VMOVUPDZ256rm 405U, // VMOVUPDZ256rmk 461U, // VMOVUPDZ256rmkz 0U, // VMOVUPDZ256rr 0U, // VMOVUPDZ256rr_REV 405U, // VMOVUPDZ256rrk 397U, // VMOVUPDZ256rrk_REV 461U, // VMOVUPDZ256rrkz 461U, // VMOVUPDZ256rrkz_REV 0U, // VMOVUPDZmr 49U, // VMOVUPDZmrk 0U, // VMOVUPDZrm 405U, // VMOVUPDZrmk 461U, // VMOVUPDZrmkz 0U, // VMOVUPDZrr 0U, // VMOVUPDZrr_REV 405U, // VMOVUPDZrrk 397U, // VMOVUPDZrrk_REV 461U, // VMOVUPDZrrkz 461U, // VMOVUPDZrrkz_REV 0U, // VMOVUPDmr 0U, // VMOVUPDrm 0U, // VMOVUPDrr 0U, // VMOVUPDrr_REV 0U, // VMOVUPSYmr 0U, // VMOVUPSYrm 0U, // VMOVUPSYrr 0U, // VMOVUPSYrr_REV 0U, // VMOVUPSZ128mr 49U, // VMOVUPSZ128mrk 0U, // VMOVUPSZ128rm 405U, // VMOVUPSZ128rmk 461U, // VMOVUPSZ128rmkz 0U, // VMOVUPSZ128rr 0U, // VMOVUPSZ128rr_REV 405U, // VMOVUPSZ128rrk 397U, // VMOVUPSZ128rrk_REV 461U, // VMOVUPSZ128rrkz 461U, // VMOVUPSZ128rrkz_REV 0U, // VMOVUPSZ256mr 49U, // VMOVUPSZ256mrk 0U, // VMOVUPSZ256rm 405U, // VMOVUPSZ256rmk 461U, // VMOVUPSZ256rmkz 0U, // VMOVUPSZ256rr 0U, // VMOVUPSZ256rr_REV 405U, // VMOVUPSZ256rrk 397U, // VMOVUPSZ256rrk_REV 461U, // VMOVUPSZ256rrkz 461U, // VMOVUPSZ256rrkz_REV 0U, // VMOVUPSZmr 49U, // VMOVUPSZmrk 0U, // VMOVUPSZrm 405U, // VMOVUPSZrmk 461U, // VMOVUPSZrmkz 0U, // VMOVUPSZrr 0U, // VMOVUPSZrr_REV 405U, // VMOVUPSZrrk 397U, // VMOVUPSZrrk_REV 461U, // VMOVUPSZrrkz 461U, // VMOVUPSZrrkz_REV 0U, // VMOVUPSmr 0U, // VMOVUPSrm 0U, // VMOVUPSrr 0U, // VMOVUPSrr_REV 0U, // VMOVZPQILo2PQIZrr 0U, // VMOVZPQILo2PQIrr 72U, // VMPSADBWYrmi 18636U, // VMPSADBWYrri 72U, // VMPSADBWrmi 18636U, // VMPSADBWrri 0U, // VMPTRLDm 0U, // VMPTRSTm 0U, // VMREAD32mr 0U, // VMREAD32rr 0U, // VMREAD64mr 0U, // VMREAD64rr 0U, // VMRESUME 0U, // VMRUN32 0U, // VMRUN64 0U, // VMSAVE32 0U, // VMSAVE64 4U, // VMULPDYrm 4U, // VMULPDYrr 4U, // VMULPDZ128rm 72U, // VMULPDZ128rmb 133U, // VMULPDZ128rmbk 9348U, // VMULPDZ128rmbkz 0U, // VMULPDZ128rmk 9348U, // VMULPDZ128rmkz 4U, // VMULPDZ128rr 0U, // VMULPDZ128rrk 9348U, // VMULPDZ128rrkz 4U, // VMULPDZ256rm 72U, // VMULPDZ256rmb 133U, // VMULPDZ256rmbk 9348U, // VMULPDZ256rmbkz 0U, // VMULPDZ256rmk 9348U, // VMULPDZ256rmkz 4U, // VMULPDZ256rr 0U, // VMULPDZ256rrk 9348U, // VMULPDZ256rrkz 4U, // VMULPDZrm 72U, // VMULPDZrmb 133U, // VMULPDZrmbk 9348U, // VMULPDZrmbkz 0U, // VMULPDZrmk 9348U, // VMULPDZrmkz 4U, // VMULPDZrr 4U, // VMULPDZrrb 0U, // VMULPDZrrbk 9348U, // VMULPDZrrbkz 0U, // VMULPDZrrk 9348U, // VMULPDZrrkz 4U, // VMULPDrm 4U, // VMULPDrr 4U, // VMULPSYrm 4U, // VMULPSYrr 4U, // VMULPSZ128rm 72U, // VMULPSZ128rmb 133U, // VMULPSZ128rmbk 9348U, // VMULPSZ128rmbkz 0U, // VMULPSZ128rmk 9348U, // VMULPSZ128rmkz 4U, // VMULPSZ128rr 0U, // VMULPSZ128rrk 9348U, // VMULPSZ128rrkz 4U, // VMULPSZ256rm 72U, // VMULPSZ256rmb 133U, // VMULPSZ256rmbk 9348U, // VMULPSZ256rmbkz 0U, // VMULPSZ256rmk 9348U, // VMULPSZ256rmkz 4U, // VMULPSZ256rr 0U, // VMULPSZ256rrk 9348U, // VMULPSZ256rrkz 4U, // VMULPSZrm 72U, // VMULPSZrmb 133U, // VMULPSZrmbk 9348U, // VMULPSZrmbkz 0U, // VMULPSZrmk 9348U, // VMULPSZrmkz 4U, // VMULPSZrr 4U, // VMULPSZrrb 0U, // VMULPSZrrbk 9348U, // VMULPSZrrbkz 0U, // VMULPSZrrk 9348U, // VMULPSZrrkz 4U, // VMULPSrm 4U, // VMULPSrr 72U, // VMULSDZrm 72U, // VMULSDZrm_Int 133U, // VMULSDZrm_Intk 9348U, // VMULSDZrm_Intkz 4U, // VMULSDZrr 4U, // VMULSDZrr_Int 0U, // VMULSDZrr_Intk 9348U, // VMULSDZrr_Intkz 4U, // VMULSDZrrb_Int 0U, // VMULSDZrrb_Intk 9348U, // VMULSDZrrb_Intkz 72U, // VMULSDrm 72U, // VMULSDrm_Int 4U, // VMULSDrr 4U, // VMULSDrr_Int 72U, // VMULSSZrm 72U, // VMULSSZrm_Int 133U, // VMULSSZrm_Intk 9348U, // VMULSSZrm_Intkz 4U, // VMULSSZrr 4U, // VMULSSZrr_Int 0U, // VMULSSZrr_Intk 9348U, // VMULSSZrr_Intkz 4U, // VMULSSZrrb_Int 0U, // VMULSSZrrb_Intk 9348U, // VMULSSZrrb_Intkz 72U, // VMULSSrm 72U, // VMULSSrm_Int 4U, // VMULSSrr 4U, // VMULSSrr_Int 0U, // VMWRITE32rm 0U, // VMWRITE32rr 0U, // VMWRITE64rm 0U, // VMWRITE64rr 0U, // VMXOFF 0U, // VMXON 4U, // VORPDYrm 4U, // VORPDYrr 4U, // VORPDZ128rm 72U, // VORPDZ128rmb 133U, // VORPDZ128rmbk 9348U, // VORPDZ128rmbkz 0U, // VORPDZ128rmk 9348U, // VORPDZ128rmkz 4U, // VORPDZ128rr 0U, // VORPDZ128rrk 9348U, // VORPDZ128rrkz 4U, // VORPDZ256rm 72U, // VORPDZ256rmb 133U, // VORPDZ256rmbk 9348U, // VORPDZ256rmbkz 0U, // VORPDZ256rmk 9348U, // VORPDZ256rmkz 4U, // VORPDZ256rr 0U, // VORPDZ256rrk 9348U, // VORPDZ256rrkz 4U, // VORPDZrm 72U, // VORPDZrmb 133U, // VORPDZrmbk 9348U, // VORPDZrmbkz 0U, // VORPDZrmk 9348U, // VORPDZrmkz 4U, // VORPDZrr 0U, // VORPDZrrk 9348U, // VORPDZrrkz 4U, // VORPDrm 4U, // VORPDrr 4U, // VORPSYrm 4U, // VORPSYrr 4U, // VORPSZ128rm 72U, // VORPSZ128rmb 133U, // VORPSZ128rmbk 9348U, // VORPSZ128rmbkz 0U, // VORPSZ128rmk 9348U, // VORPSZ128rmkz 4U, // VORPSZ128rr 0U, // VORPSZ128rrk 9348U, // VORPSZ128rrkz 4U, // VORPSZ256rm 72U, // VORPSZ256rmb 133U, // VORPSZ256rmbk 9348U, // VORPSZ256rmbkz 0U, // VORPSZ256rmk 9348U, // VORPSZ256rmkz 4U, // VORPSZ256rr 0U, // VORPSZ256rrk 9348U, // VORPSZ256rrkz 4U, // VORPSZrm 72U, // VORPSZrmb 133U, // VORPSZrmbk 9348U, // VORPSZrmbkz 0U, // VORPSZrmk 9348U, // VORPSZrmkz 4U, // VORPSZrr 0U, // VORPSZrrk 9348U, // VORPSZrrkz 4U, // VORPSrm 4U, // VORPSrr 4U, // VP4DPWSSDSrm 0U, // VP4DPWSSDSrmk 0U, // VP4DPWSSDSrmkz 4U, // VP4DPWSSDrm 0U, // VP4DPWSSDrmk 0U, // VP4DPWSSDrmkz 0U, // VPABSBYrm 0U, // VPABSBYrr 0U, // VPABSBZ128rm 405U, // VPABSBZ128rmk 461U, // VPABSBZ128rmkz 0U, // VPABSBZ128rr 405U, // VPABSBZ128rrk 461U, // VPABSBZ128rrkz 0U, // VPABSBZ256rm 405U, // VPABSBZ256rmk 461U, // VPABSBZ256rmkz 0U, // VPABSBZ256rr 405U, // VPABSBZ256rrk 461U, // VPABSBZ256rrkz 0U, // VPABSBZrm 405U, // VPABSBZrmk 461U, // VPABSBZrmkz 0U, // VPABSBZrr 405U, // VPABSBZrrk 461U, // VPABSBZrrkz 0U, // VPABSBrm 0U, // VPABSBrr 0U, // VPABSDYrm 0U, // VPABSDYrr 0U, // VPABSDZ128rm 0U, // VPABSDZ128rmb 3356U, // VPABSDZ128rmbk 4444U, // VPABSDZ128rmbkz 405U, // VPABSDZ128rmk 461U, // VPABSDZ128rmkz 0U, // VPABSDZ128rr 405U, // VPABSDZ128rrk 461U, // VPABSDZ128rrkz 0U, // VPABSDZ256rm 0U, // VPABSDZ256rmb 3356U, // VPABSDZ256rmbk 4444U, // VPABSDZ256rmbkz 405U, // VPABSDZ256rmk 461U, // VPABSDZ256rmkz 0U, // VPABSDZ256rr 405U, // VPABSDZ256rrk 461U, // VPABSDZ256rrkz 0U, // VPABSDZrm 0U, // VPABSDZrmb 3356U, // VPABSDZrmbk 4444U, // VPABSDZrmbkz 405U, // VPABSDZrmk 461U, // VPABSDZrmkz 0U, // VPABSDZrr 405U, // VPABSDZrrk 461U, // VPABSDZrrkz 0U, // VPABSDrm 0U, // VPABSDrr 0U, // VPABSQZ128rm 0U, // VPABSQZ128rmb 3356U, // VPABSQZ128rmbk 4444U, // VPABSQZ128rmbkz 405U, // VPABSQZ128rmk 461U, // VPABSQZ128rmkz 0U, // VPABSQZ128rr 405U, // VPABSQZ128rrk 461U, // VPABSQZ128rrkz 0U, // VPABSQZ256rm 0U, // VPABSQZ256rmb 3356U, // VPABSQZ256rmbk 4444U, // VPABSQZ256rmbkz 405U, // VPABSQZ256rmk 461U, // VPABSQZ256rmkz 0U, // VPABSQZ256rr 405U, // VPABSQZ256rrk 461U, // VPABSQZ256rrkz 0U, // VPABSQZrm 0U, // VPABSQZrmb 3356U, // VPABSQZrmbk 4444U, // VPABSQZrmbkz 405U, // VPABSQZrmk 461U, // VPABSQZrmkz 0U, // VPABSQZrr 405U, // VPABSQZrrk 461U, // VPABSQZrrkz 0U, // VPABSWYrm 0U, // VPABSWYrr 0U, // VPABSWZ128rm 405U, // VPABSWZ128rmk 461U, // VPABSWZ128rmkz 0U, // VPABSWZ128rr 405U, // VPABSWZ128rrk 461U, // VPABSWZ128rrkz 0U, // VPABSWZ256rm 405U, // VPABSWZ256rmk 461U, // VPABSWZ256rmkz 0U, // VPABSWZ256rr 405U, // VPABSWZ256rrk 461U, // VPABSWZ256rrkz 0U, // VPABSWZrm 405U, // VPABSWZrmk 461U, // VPABSWZrmkz 0U, // VPABSWZrr 405U, // VPABSWZrrk 461U, // VPABSWZrrkz 0U, // VPABSWrm 0U, // VPABSWrr 4U, // VPACKSSDWYrm 4U, // VPACKSSDWYrr 4U, // VPACKSSDWZ128rm 72U, // VPACKSSDWZ128rmb 133U, // VPACKSSDWZ128rmbk 9348U, // VPACKSSDWZ128rmbkz 132U, // VPACKSSDWZ128rmk 9348U, // VPACKSSDWZ128rmkz 4U, // VPACKSSDWZ128rr 0U, // VPACKSSDWZ128rrk 9348U, // VPACKSSDWZ128rrkz 4U, // VPACKSSDWZ256rm 72U, // VPACKSSDWZ256rmb 133U, // VPACKSSDWZ256rmbk 9348U, // VPACKSSDWZ256rmbkz 132U, // VPACKSSDWZ256rmk 9348U, // VPACKSSDWZ256rmkz 4U, // VPACKSSDWZ256rr 0U, // VPACKSSDWZ256rrk 9348U, // VPACKSSDWZ256rrkz 4U, // VPACKSSDWZrm 72U, // VPACKSSDWZrmb 133U, // VPACKSSDWZrmbk 9348U, // VPACKSSDWZrmbkz 132U, // VPACKSSDWZrmk 9348U, // VPACKSSDWZrmkz 4U, // VPACKSSDWZrr 0U, // VPACKSSDWZrrk 9348U, // VPACKSSDWZrrkz 4U, // VPACKSSDWrm 4U, // VPACKSSDWrr 4U, // VPACKSSWBYrm 4U, // VPACKSSWBYrr 4U, // VPACKSSWBZ128rm 132U, // VPACKSSWBZ128rmk 9348U, // VPACKSSWBZ128rmkz 4U, // VPACKSSWBZ128rr 0U, // VPACKSSWBZ128rrk 9348U, // VPACKSSWBZ128rrkz 4U, // VPACKSSWBZ256rm 132U, // VPACKSSWBZ256rmk 9348U, // VPACKSSWBZ256rmkz 4U, // VPACKSSWBZ256rr 0U, // VPACKSSWBZ256rrk 9348U, // VPACKSSWBZ256rrkz 4U, // VPACKSSWBZrm 132U, // VPACKSSWBZrmk 9348U, // VPACKSSWBZrmkz 4U, // VPACKSSWBZrr 0U, // VPACKSSWBZrrk 9348U, // VPACKSSWBZrrkz 4U, // VPACKSSWBrm 4U, // VPACKSSWBrr 4U, // VPACKUSDWYrm 4U, // VPACKUSDWYrr 4U, // VPACKUSDWZ128rm 72U, // VPACKUSDWZ128rmb 133U, // VPACKUSDWZ128rmbk 9348U, // VPACKUSDWZ128rmbkz 132U, // VPACKUSDWZ128rmk 9348U, // VPACKUSDWZ128rmkz 4U, // VPACKUSDWZ128rr 0U, // VPACKUSDWZ128rrk 9348U, // VPACKUSDWZ128rrkz 4U, // VPACKUSDWZ256rm 72U, // VPACKUSDWZ256rmb 133U, // VPACKUSDWZ256rmbk 9348U, // VPACKUSDWZ256rmbkz 132U, // VPACKUSDWZ256rmk 9348U, // VPACKUSDWZ256rmkz 4U, // VPACKUSDWZ256rr 0U, // VPACKUSDWZ256rrk 9348U, // VPACKUSDWZ256rrkz 4U, // VPACKUSDWZrm 72U, // VPACKUSDWZrmb 133U, // VPACKUSDWZrmbk 9348U, // VPACKUSDWZrmbkz 132U, // VPACKUSDWZrmk 9348U, // VPACKUSDWZrmkz 4U, // VPACKUSDWZrr 0U, // VPACKUSDWZrrk 9348U, // VPACKUSDWZrrkz 4U, // VPACKUSDWrm 4U, // VPACKUSDWrr 4U, // VPACKUSWBYrm 4U, // VPACKUSWBYrr 4U, // VPACKUSWBZ128rm 132U, // VPACKUSWBZ128rmk 9348U, // VPACKUSWBZ128rmkz 4U, // VPACKUSWBZ128rr 0U, // VPACKUSWBZ128rrk 9348U, // VPACKUSWBZ128rrkz 4U, // VPACKUSWBZ256rm 132U, // VPACKUSWBZ256rmk 9348U, // VPACKUSWBZ256rmkz 4U, // VPACKUSWBZ256rr 0U, // VPACKUSWBZ256rrk 9348U, // VPACKUSWBZ256rrkz 4U, // VPACKUSWBZrm 132U, // VPACKUSWBZrmk 9348U, // VPACKUSWBZrmkz 4U, // VPACKUSWBZrr 0U, // VPACKUSWBZrrk 9348U, // VPACKUSWBZrrkz 4U, // VPACKUSWBrm 4U, // VPACKUSWBrr 4U, // VPADDBYrm 4U, // VPADDBYrr 4U, // VPADDBZ128rm 132U, // VPADDBZ128rmk 9348U, // VPADDBZ128rmkz 4U, // VPADDBZ128rr 0U, // VPADDBZ128rrk 9348U, // VPADDBZ128rrkz 4U, // VPADDBZ256rm 132U, // VPADDBZ256rmk 9348U, // VPADDBZ256rmkz 4U, // VPADDBZ256rr 0U, // VPADDBZ256rrk 9348U, // VPADDBZ256rrkz 4U, // VPADDBZrm 132U, // VPADDBZrmk 9348U, // VPADDBZrmkz 4U, // VPADDBZrr 0U, // VPADDBZrrk 9348U, // VPADDBZrrkz 4U, // VPADDBrm 4U, // VPADDBrr 4U, // VPADDDYrm 4U, // VPADDDYrr 4U, // VPADDDZ128rm 72U, // VPADDDZ128rmb 133U, // VPADDDZ128rmbk 9348U, // VPADDDZ128rmbkz 132U, // VPADDDZ128rmk 9348U, // VPADDDZ128rmkz 4U, // VPADDDZ128rr 0U, // VPADDDZ128rrk 9348U, // VPADDDZ128rrkz 4U, // VPADDDZ256rm 72U, // VPADDDZ256rmb 133U, // VPADDDZ256rmbk 9348U, // VPADDDZ256rmbkz 132U, // VPADDDZ256rmk 9348U, // VPADDDZ256rmkz 4U, // VPADDDZ256rr 0U, // VPADDDZ256rrk 9348U, // VPADDDZ256rrkz 4U, // VPADDDZrm 72U, // VPADDDZrmb 133U, // VPADDDZrmbk 9348U, // VPADDDZrmbkz 132U, // VPADDDZrmk 9348U, // VPADDDZrmkz 4U, // VPADDDZrr 0U, // VPADDDZrrk 9348U, // VPADDDZrrkz 4U, // VPADDDrm 4U, // VPADDDrr 4U, // VPADDQYrm 4U, // VPADDQYrr 4U, // VPADDQZ128rm 72U, // VPADDQZ128rmb 133U, // VPADDQZ128rmbk 9348U, // VPADDQZ128rmbkz 132U, // VPADDQZ128rmk 9348U, // VPADDQZ128rmkz 4U, // VPADDQZ128rr 0U, // VPADDQZ128rrk 9348U, // VPADDQZ128rrkz 4U, // VPADDQZ256rm 72U, // VPADDQZ256rmb 133U, // VPADDQZ256rmbk 9348U, // VPADDQZ256rmbkz 132U, // VPADDQZ256rmk 9348U, // VPADDQZ256rmkz 4U, // VPADDQZ256rr 0U, // VPADDQZ256rrk 9348U, // VPADDQZ256rrkz 4U, // VPADDQZrm 72U, // VPADDQZrmb 133U, // VPADDQZrmbk 9348U, // VPADDQZrmbkz 132U, // VPADDQZrmk 9348U, // VPADDQZrmkz 4U, // VPADDQZrr 0U, // VPADDQZrrk 9348U, // VPADDQZrrkz 4U, // VPADDQrm 4U, // VPADDQrr 4U, // VPADDSBYrm 4U, // VPADDSBYrr 4U, // VPADDSBZ128rm 132U, // VPADDSBZ128rmk 9348U, // VPADDSBZ128rmkz 4U, // VPADDSBZ128rr 0U, // VPADDSBZ128rrk 9348U, // VPADDSBZ128rrkz 4U, // VPADDSBZ256rm 132U, // VPADDSBZ256rmk 9348U, // VPADDSBZ256rmkz 4U, // VPADDSBZ256rr 0U, // VPADDSBZ256rrk 9348U, // VPADDSBZ256rrkz 4U, // VPADDSBZrm 132U, // VPADDSBZrmk 9348U, // VPADDSBZrmkz 4U, // VPADDSBZrr 0U, // VPADDSBZrrk 9348U, // VPADDSBZrrkz 4U, // VPADDSBrm 4U, // VPADDSBrr 4U, // VPADDSWYrm 4U, // VPADDSWYrr 4U, // VPADDSWZ128rm 132U, // VPADDSWZ128rmk 9348U, // VPADDSWZ128rmkz 4U, // VPADDSWZ128rr 0U, // VPADDSWZ128rrk 9348U, // VPADDSWZ128rrkz 4U, // VPADDSWZ256rm 132U, // VPADDSWZ256rmk 9348U, // VPADDSWZ256rmkz 4U, // VPADDSWZ256rr 0U, // VPADDSWZ256rrk 9348U, // VPADDSWZ256rrkz 4U, // VPADDSWZrm 132U, // VPADDSWZrmk 9348U, // VPADDSWZrmkz 4U, // VPADDSWZrr 0U, // VPADDSWZrrk 9348U, // VPADDSWZrrkz 4U, // VPADDSWrm 4U, // VPADDSWrr 4U, // VPADDUSBYrm 4U, // VPADDUSBYrr 4U, // VPADDUSBZ128rm 132U, // VPADDUSBZ128rmk 9348U, // VPADDUSBZ128rmkz 4U, // VPADDUSBZ128rr 0U, // VPADDUSBZ128rrk 9348U, // VPADDUSBZ128rrkz 4U, // VPADDUSBZ256rm 132U, // VPADDUSBZ256rmk 9348U, // VPADDUSBZ256rmkz 4U, // VPADDUSBZ256rr 0U, // VPADDUSBZ256rrk 9348U, // VPADDUSBZ256rrkz 4U, // VPADDUSBZrm 132U, // VPADDUSBZrmk 9348U, // VPADDUSBZrmkz 4U, // VPADDUSBZrr 0U, // VPADDUSBZrrk 9348U, // VPADDUSBZrrkz 4U, // VPADDUSBrm 4U, // VPADDUSBrr 4U, // VPADDUSWYrm 4U, // VPADDUSWYrr 4U, // VPADDUSWZ128rm 132U, // VPADDUSWZ128rmk 9348U, // VPADDUSWZ128rmkz 4U, // VPADDUSWZ128rr 0U, // VPADDUSWZ128rrk 9348U, // VPADDUSWZ128rrkz 4U, // VPADDUSWZ256rm 132U, // VPADDUSWZ256rmk 9348U, // VPADDUSWZ256rmkz 4U, // VPADDUSWZ256rr 0U, // VPADDUSWZ256rrk 9348U, // VPADDUSWZ256rrkz 4U, // VPADDUSWZrm 132U, // VPADDUSWZrmk 9348U, // VPADDUSWZrmkz 4U, // VPADDUSWZrr 0U, // VPADDUSWZrrk 9348U, // VPADDUSWZrrkz 4U, // VPADDUSWrm 4U, // VPADDUSWrr 4U, // VPADDWYrm 4U, // VPADDWYrr 4U, // VPADDWZ128rm 132U, // VPADDWZ128rmk 9348U, // VPADDWZ128rmkz 4U, // VPADDWZ128rr 0U, // VPADDWZ128rrk 9348U, // VPADDWZ128rrkz 4U, // VPADDWZ256rm 132U, // VPADDWZ256rmk 9348U, // VPADDWZ256rmkz 4U, // VPADDWZ256rr 0U, // VPADDWZ256rrk 9348U, // VPADDWZ256rrkz 4U, // VPADDWZrm 132U, // VPADDWZrmk 9348U, // VPADDWZrmkz 4U, // VPADDWZrr 0U, // VPADDWZrrk 9348U, // VPADDWZrrkz 4U, // VPADDWrm 4U, // VPADDWrr 72U, // VPALIGNRYrmi 18636U, // VPALIGNRYrri 72U, // VPALIGNRZ128rmi 1U, // VPALIGNRZ128rmik 9348U, // VPALIGNRZ128rmikz 18636U, // VPALIGNRZ128rri 25U, // VPALIGNRZ128rrik 26837U, // VPALIGNRZ128rrikz 72U, // VPALIGNRZ256rmi 1U, // VPALIGNRZ256rmik 9348U, // VPALIGNRZ256rmikz 18636U, // VPALIGNRZ256rri 25U, // VPALIGNRZ256rrik 26837U, // VPALIGNRZ256rrikz 72U, // VPALIGNRZrmi 1U, // VPALIGNRZrmik 9348U, // VPALIGNRZrmikz 18636U, // VPALIGNRZrri 25U, // VPALIGNRZrrik 26837U, // VPALIGNRZrrikz 72U, // VPALIGNRrmi 18636U, // VPALIGNRrri 4U, // VPANDDZ128rm 72U, // VPANDDZ128rmb 133U, // VPANDDZ128rmbk 9348U, // VPANDDZ128rmbkz 132U, // VPANDDZ128rmk 9348U, // VPANDDZ128rmkz 4U, // VPANDDZ128rr 0U, // VPANDDZ128rrk 9348U, // VPANDDZ128rrkz 4U, // VPANDDZ256rm 72U, // VPANDDZ256rmb 133U, // VPANDDZ256rmbk 9348U, // VPANDDZ256rmbkz 132U, // VPANDDZ256rmk 9348U, // VPANDDZ256rmkz 4U, // VPANDDZ256rr 0U, // VPANDDZ256rrk 9348U, // VPANDDZ256rrkz 4U, // VPANDDZrm 72U, // VPANDDZrmb 133U, // VPANDDZrmbk 9348U, // VPANDDZrmbkz 132U, // VPANDDZrmk 9348U, // VPANDDZrmkz 4U, // VPANDDZrr 0U, // VPANDDZrrk 9348U, // VPANDDZrrkz 4U, // VPANDNDZ128rm 72U, // VPANDNDZ128rmb 133U, // VPANDNDZ128rmbk 9348U, // VPANDNDZ128rmbkz 132U, // VPANDNDZ128rmk 9348U, // VPANDNDZ128rmkz 4U, // VPANDNDZ128rr 0U, // VPANDNDZ128rrk 9348U, // VPANDNDZ128rrkz 4U, // VPANDNDZ256rm 72U, // VPANDNDZ256rmb 133U, // VPANDNDZ256rmbk 9348U, // VPANDNDZ256rmbkz 132U, // VPANDNDZ256rmk 9348U, // VPANDNDZ256rmkz 4U, // VPANDNDZ256rr 0U, // VPANDNDZ256rrk 9348U, // VPANDNDZ256rrkz 4U, // VPANDNDZrm 72U, // VPANDNDZrmb 133U, // VPANDNDZrmbk 9348U, // VPANDNDZrmbkz 132U, // VPANDNDZrmk 9348U, // VPANDNDZrmkz 4U, // VPANDNDZrr 0U, // VPANDNDZrrk 9348U, // VPANDNDZrrkz 4U, // VPANDNQZ128rm 72U, // VPANDNQZ128rmb 133U, // VPANDNQZ128rmbk 9348U, // VPANDNQZ128rmbkz 132U, // VPANDNQZ128rmk 9348U, // VPANDNQZ128rmkz 4U, // VPANDNQZ128rr 0U, // VPANDNQZ128rrk 9348U, // VPANDNQZ128rrkz 4U, // VPANDNQZ256rm 72U, // VPANDNQZ256rmb 133U, // VPANDNQZ256rmbk 9348U, // VPANDNQZ256rmbkz 132U, // VPANDNQZ256rmk 9348U, // VPANDNQZ256rmkz 4U, // VPANDNQZ256rr 0U, // VPANDNQZ256rrk 9348U, // VPANDNQZ256rrkz 4U, // VPANDNQZrm 72U, // VPANDNQZrmb 133U, // VPANDNQZrmbk 9348U, // VPANDNQZrmbkz 132U, // VPANDNQZrmk 9348U, // VPANDNQZrmkz 4U, // VPANDNQZrr 0U, // VPANDNQZrrk 9348U, // VPANDNQZrrkz 4U, // VPANDNYrm 4U, // VPANDNYrr 4U, // VPANDNrm 4U, // VPANDNrr 4U, // VPANDQZ128rm 72U, // VPANDQZ128rmb 133U, // VPANDQZ128rmbk 9348U, // VPANDQZ128rmbkz 132U, // VPANDQZ128rmk 9348U, // VPANDQZ128rmkz 4U, // VPANDQZ128rr 0U, // VPANDQZ128rrk 9348U, // VPANDQZ128rrkz 4U, // VPANDQZ256rm 72U, // VPANDQZ256rmb 133U, // VPANDQZ256rmbk 9348U, // VPANDQZ256rmbkz 132U, // VPANDQZ256rmk 9348U, // VPANDQZ256rmkz 4U, // VPANDQZ256rr 0U, // VPANDQZ256rrk 9348U, // VPANDQZ256rrkz 4U, // VPANDQZrm 72U, // VPANDQZrmb 133U, // VPANDQZrmbk 9348U, // VPANDQZrmbkz 132U, // VPANDQZrmk 9348U, // VPANDQZrmkz 4U, // VPANDQZrr 0U, // VPANDQZrrk 9348U, // VPANDQZrrkz 4U, // VPANDYrm 4U, // VPANDYrr 4U, // VPANDrm 4U, // VPANDrr 4U, // VPAVGBYrm 4U, // VPAVGBYrr 4U, // VPAVGBZ128rm 132U, // VPAVGBZ128rmk 9348U, // VPAVGBZ128rmkz 4U, // VPAVGBZ128rr 0U, // VPAVGBZ128rrk 9348U, // VPAVGBZ128rrkz 4U, // VPAVGBZ256rm 132U, // VPAVGBZ256rmk 9348U, // VPAVGBZ256rmkz 4U, // VPAVGBZ256rr 0U, // VPAVGBZ256rrk 9348U, // VPAVGBZ256rrkz 4U, // VPAVGBZrm 132U, // VPAVGBZrmk 9348U, // VPAVGBZrmkz 4U, // VPAVGBZrr 0U, // VPAVGBZrrk 9348U, // VPAVGBZrrkz 4U, // VPAVGBrm 4U, // VPAVGBrr 4U, // VPAVGWYrm 4U, // VPAVGWYrr 4U, // VPAVGWZ128rm 132U, // VPAVGWZ128rmk 9348U, // VPAVGWZ128rmkz 4U, // VPAVGWZ128rr 0U, // VPAVGWZ128rrk 9348U, // VPAVGWZ128rrkz 4U, // VPAVGWZ256rm 132U, // VPAVGWZ256rmk 9348U, // VPAVGWZ256rmkz 4U, // VPAVGWZ256rr 0U, // VPAVGWZ256rrk 9348U, // VPAVGWZ256rrkz 4U, // VPAVGWZrm 132U, // VPAVGWZrmk 9348U, // VPAVGWZrmkz 4U, // VPAVGWZrr 0U, // VPAVGWZrrk 9348U, // VPAVGWZrrkz 4U, // VPAVGWrm 4U, // VPAVGWrr 72U, // VPBLENDDYrmi 18636U, // VPBLENDDYrri 72U, // VPBLENDDrmi 18636U, // VPBLENDDrri 4U, // VPBLENDMBZ128rm 1156U, // VPBLENDMBZ128rmk 9348U, // VPBLENDMBZ128rmkz 4U, // VPBLENDMBZ128rr 1156U, // VPBLENDMBZ128rrk 9348U, // VPBLENDMBZ128rrkz 4U, // VPBLENDMBZ256rm 1156U, // VPBLENDMBZ256rmk 9348U, // VPBLENDMBZ256rmkz 4U, // VPBLENDMBZ256rr 1156U, // VPBLENDMBZ256rrk 9348U, // VPBLENDMBZ256rrkz 4U, // VPBLENDMBZrm 1156U, // VPBLENDMBZrmk 9348U, // VPBLENDMBZrmkz 4U, // VPBLENDMBZrr 1156U, // VPBLENDMBZrrk 9348U, // VPBLENDMBZrrkz 4U, // VPBLENDMDZ128rm 72U, // VPBLENDMDZ128rmb 1156U, // VPBLENDMDZ128rmbk 9348U, // VPBLENDMDZ128rmbkz 1156U, // VPBLENDMDZ128rmk 9348U, // VPBLENDMDZ128rmkz 4U, // VPBLENDMDZ128rr 1156U, // VPBLENDMDZ128rrk 9348U, // VPBLENDMDZ128rrkz 4U, // VPBLENDMDZ256rm 72U, // VPBLENDMDZ256rmb 1156U, // VPBLENDMDZ256rmbk 9348U, // VPBLENDMDZ256rmbkz 1156U, // VPBLENDMDZ256rmk 9348U, // VPBLENDMDZ256rmkz 4U, // VPBLENDMDZ256rr 1156U, // VPBLENDMDZ256rrk 9348U, // VPBLENDMDZ256rrkz 4U, // VPBLENDMDZrm 72U, // VPBLENDMDZrmb 1156U, // VPBLENDMDZrmbk 9348U, // VPBLENDMDZrmbkz 1156U, // VPBLENDMDZrmk 9348U, // VPBLENDMDZrmkz 4U, // VPBLENDMDZrr 1156U, // VPBLENDMDZrrk 9348U, // VPBLENDMDZrrkz 4U, // VPBLENDMQZ128rm 72U, // VPBLENDMQZ128rmb 1156U, // VPBLENDMQZ128rmbk 9348U, // VPBLENDMQZ128rmbkz 1156U, // VPBLENDMQZ128rmk 9348U, // VPBLENDMQZ128rmkz 4U, // VPBLENDMQZ128rr 1156U, // VPBLENDMQZ128rrk 9348U, // VPBLENDMQZ128rrkz 4U, // VPBLENDMQZ256rm 72U, // VPBLENDMQZ256rmb 1156U, // VPBLENDMQZ256rmbk 9348U, // VPBLENDMQZ256rmbkz 1156U, // VPBLENDMQZ256rmk 9348U, // VPBLENDMQZ256rmkz 4U, // VPBLENDMQZ256rr 1156U, // VPBLENDMQZ256rrk 9348U, // VPBLENDMQZ256rrkz 4U, // VPBLENDMQZrm 72U, // VPBLENDMQZrmb 1156U, // VPBLENDMQZrmbk 9348U, // VPBLENDMQZrmbkz 1156U, // VPBLENDMQZrmk 9348U, // VPBLENDMQZrmkz 4U, // VPBLENDMQZrr 1156U, // VPBLENDMQZrrk 9348U, // VPBLENDMQZrrkz 4U, // VPBLENDMWZ128rm 1156U, // VPBLENDMWZ128rmk 9348U, // VPBLENDMWZ128rmkz 4U, // VPBLENDMWZ128rr 1156U, // VPBLENDMWZ128rrk 9348U, // VPBLENDMWZ128rrkz 4U, // VPBLENDMWZ256rm 1156U, // VPBLENDMWZ256rmk 9348U, // VPBLENDMWZ256rmkz 4U, // VPBLENDMWZ256rr 1156U, // VPBLENDMWZ256rrk 9348U, // VPBLENDMWZ256rrkz 4U, // VPBLENDMWZrm 1156U, // VPBLENDMWZrmk 9348U, // VPBLENDMWZrmkz 4U, // VPBLENDMWZrr 1156U, // VPBLENDMWZrrk 9348U, // VPBLENDMWZrrkz 72U, // VPBLENDVBYrm 18636U, // VPBLENDVBYrr 72U, // VPBLENDVBrm 18636U, // VPBLENDVBrr 72U, // VPBLENDWYrmi 18636U, // VPBLENDWYrri 72U, // VPBLENDWrmi 18636U, // VPBLENDWrri 0U, // VPBROADCASTBYrm 0U, // VPBROADCASTBYrr 0U, // VPBROADCASTBZ128m 0U, // VPBROADCASTBZ128mk 461U, // VPBROADCASTBZ128mkz 0U, // VPBROADCASTBZ128r 405U, // VPBROADCASTBZ128rk 461U, // VPBROADCASTBZ128rkz 0U, // VPBROADCASTBZ256m 0U, // VPBROADCASTBZ256mk 461U, // VPBROADCASTBZ256mkz 0U, // VPBROADCASTBZ256r 405U, // VPBROADCASTBZ256rk 461U, // VPBROADCASTBZ256rkz 0U, // VPBROADCASTBZm 0U, // VPBROADCASTBZmk 461U, // VPBROADCASTBZmkz 0U, // VPBROADCASTBZr 405U, // VPBROADCASTBZrk 461U, // VPBROADCASTBZrkz 0U, // VPBROADCASTBrZ128r 405U, // VPBROADCASTBrZ128rk 461U, // VPBROADCASTBrZ128rkz 0U, // VPBROADCASTBrZ256r 405U, // VPBROADCASTBrZ256rk 461U, // VPBROADCASTBrZ256rkz 0U, // VPBROADCASTBrZr 405U, // VPBROADCASTBrZrk 461U, // VPBROADCASTBrZrkz 0U, // VPBROADCASTBrm 0U, // VPBROADCASTBrr 0U, // VPBROADCASTDYrm 0U, // VPBROADCASTDYrr 0U, // VPBROADCASTDZ128m 3356U, // VPBROADCASTDZ128mk 4444U, // VPBROADCASTDZ128mkz 0U, // VPBROADCASTDZ128r 405U, // VPBROADCASTDZ128rk 461U, // VPBROADCASTDZ128rkz 0U, // VPBROADCASTDZ256m 3356U, // VPBROADCASTDZ256mk 4444U, // VPBROADCASTDZ256mkz 0U, // VPBROADCASTDZ256r 405U, // VPBROADCASTDZ256rk 461U, // VPBROADCASTDZ256rkz 0U, // VPBROADCASTDZm 3356U, // VPBROADCASTDZmk 4444U, // VPBROADCASTDZmkz 0U, // VPBROADCASTDZr 405U, // VPBROADCASTDZrk 461U, // VPBROADCASTDZrkz 0U, // VPBROADCASTDrZ128r 405U, // VPBROADCASTDrZ128rk 461U, // VPBROADCASTDrZ128rkz 0U, // VPBROADCASTDrZ256r 405U, // VPBROADCASTDrZ256rk 461U, // VPBROADCASTDrZ256rkz 0U, // VPBROADCASTDrZr 405U, // VPBROADCASTDrZrk 461U, // VPBROADCASTDrZrkz 0U, // VPBROADCASTDrm 0U, // VPBROADCASTDrr 0U, // VPBROADCASTMB2QZ128rr 0U, // VPBROADCASTMB2QZ256rr 0U, // VPBROADCASTMB2QZrr 0U, // VPBROADCASTMW2DZ128rr 0U, // VPBROADCASTMW2DZ256rr 0U, // VPBROADCASTMW2DZrr 0U, // VPBROADCASTQYrm 0U, // VPBROADCASTQYrr 0U, // VPBROADCASTQZ128m 3356U, // VPBROADCASTQZ128mk 4444U, // VPBROADCASTQZ128mkz 0U, // VPBROADCASTQZ128r 405U, // VPBROADCASTQZ128rk 461U, // VPBROADCASTQZ128rkz 0U, // VPBROADCASTQZ256m 3356U, // VPBROADCASTQZ256mk 4444U, // VPBROADCASTQZ256mkz 0U, // VPBROADCASTQZ256r 405U, // VPBROADCASTQZ256rk 461U, // VPBROADCASTQZ256rkz 0U, // VPBROADCASTQZm 3356U, // VPBROADCASTQZmk 4444U, // VPBROADCASTQZmkz 0U, // VPBROADCASTQZr 405U, // VPBROADCASTQZrk 461U, // VPBROADCASTQZrkz 0U, // VPBROADCASTQrZ128r 405U, // VPBROADCASTQrZ128rk 461U, // VPBROADCASTQrZ128rkz 0U, // VPBROADCASTQrZ256r 405U, // VPBROADCASTQrZ256rk 461U, // VPBROADCASTQrZ256rkz 0U, // VPBROADCASTQrZr 405U, // VPBROADCASTQrZrk 461U, // VPBROADCASTQrZrkz 0U, // VPBROADCASTQrm 0U, // VPBROADCASTQrr 0U, // VPBROADCASTWYrm 0U, // VPBROADCASTWYrr 0U, // VPBROADCASTWZ128m 0U, // VPBROADCASTWZ128mk 461U, // VPBROADCASTWZ128mkz 0U, // VPBROADCASTWZ128r 405U, // VPBROADCASTWZ128rk 461U, // VPBROADCASTWZ128rkz 0U, // VPBROADCASTWZ256m 0U, // VPBROADCASTWZ256mk 461U, // VPBROADCASTWZ256mkz 0U, // VPBROADCASTWZ256r 405U, // VPBROADCASTWZ256rk 461U, // VPBROADCASTWZ256rkz 0U, // VPBROADCASTWZm 0U, // VPBROADCASTWZmk 461U, // VPBROADCASTWZmkz 0U, // VPBROADCASTWZr 405U, // VPBROADCASTWZrk 461U, // VPBROADCASTWZrkz 0U, // VPBROADCASTWrZ128r 405U, // VPBROADCASTWrZ128rk 461U, // VPBROADCASTWrZ128rkz 0U, // VPBROADCASTWrZ256r 405U, // VPBROADCASTWrZ256rk 461U, // VPBROADCASTWrZ256rkz 0U, // VPBROADCASTWrZr 405U, // VPBROADCASTWrZrk 461U, // VPBROADCASTWrZrkz 0U, // VPBROADCASTWrm 0U, // VPBROADCASTWrr 72U, // VPCLMULQDQYrm 18636U, // VPCLMULQDQYrr 72U, // VPCLMULQDQZ128rm 18636U, // VPCLMULQDQZ128rr 72U, // VPCLMULQDQZ256rm 18636U, // VPCLMULQDQZ256rr 72U, // VPCLMULQDQZrm 18636U, // VPCLMULQDQZrr 72U, // VPCLMULQDQrm 18636U, // VPCLMULQDQrr 72U, // VPCMOVYrmr 18636U, // VPCMOVYrrm 18636U, // VPCMOVYrrr 18636U, // VPCMOVYrrr_REV 72U, // VPCMOVrmr 18636U, // VPCMOVrrm 18636U, // VPCMOVrrr 18636U, // VPCMOVrrr_REV 2U, // VPCMPBZ128rmi 72U, // VPCMPBZ128rmi_alt 2U, // VPCMPBZ128rmik 1156U, // VPCMPBZ128rmik_alt 18636U, // VPCMPBZ128rri 18636U, // VPCMPBZ128rri_alt 26837U, // VPCMPBZ128rrik 26837U, // VPCMPBZ128rrik_alt 2U, // VPCMPBZ256rmi 72U, // VPCMPBZ256rmi_alt 2U, // VPCMPBZ256rmik 1156U, // VPCMPBZ256rmik_alt 18636U, // VPCMPBZ256rri 18636U, // VPCMPBZ256rri_alt 26837U, // VPCMPBZ256rrik 26837U, // VPCMPBZ256rrik_alt 2U, // VPCMPBZrmi 72U, // VPCMPBZrmi_alt 2U, // VPCMPBZrmik 1156U, // VPCMPBZrmik_alt 18636U, // VPCMPBZrri 18636U, // VPCMPBZrri_alt 26837U, // VPCMPBZrrik 26837U, // VPCMPBZrrik_alt 2U, // VPCMPDZ128rmi 72U, // VPCMPDZ128rmi_alt 21863U, // VPCMPDZ128rmib 18637U, // VPCMPDZ128rmib_alt 29991U, // VPCMPDZ128rmibk 26837U, // VPCMPDZ128rmibk_alt 2U, // VPCMPDZ128rmik 1156U, // VPCMPDZ128rmik_alt 18636U, // VPCMPDZ128rri 18636U, // VPCMPDZ128rri_alt 26837U, // VPCMPDZ128rrik 26837U, // VPCMPDZ128rrik_alt 2U, // VPCMPDZ256rmi 72U, // VPCMPDZ256rmi_alt 21867U, // VPCMPDZ256rmib 18637U, // VPCMPDZ256rmib_alt 29995U, // VPCMPDZ256rmibk 26837U, // VPCMPDZ256rmibk_alt 2U, // VPCMPDZ256rmik 1156U, // VPCMPDZ256rmik_alt 18636U, // VPCMPDZ256rri 18636U, // VPCMPDZ256rri_alt 26837U, // VPCMPDZ256rrik 26837U, // VPCMPDZ256rrik_alt 2U, // VPCMPDZrmi 72U, // VPCMPDZrmi_alt 21871U, // VPCMPDZrmib 18637U, // VPCMPDZrmib_alt 29999U, // VPCMPDZrmibk 26837U, // VPCMPDZrmibk_alt 2U, // VPCMPDZrmik 1156U, // VPCMPDZrmik_alt 18636U, // VPCMPDZrri 18636U, // VPCMPDZrri_alt 26837U, // VPCMPDZrrik 26837U, // VPCMPDZrrik_alt 4U, // VPCMPEQBYrm 4U, // VPCMPEQBYrr 4U, // VPCMPEQBZ128rm 1156U, // VPCMPEQBZ128rmk 4U, // VPCMPEQBZ128rr 1156U, // VPCMPEQBZ128rrk 4U, // VPCMPEQBZ256rm 1156U, // VPCMPEQBZ256rmk 4U, // VPCMPEQBZ256rr 1156U, // VPCMPEQBZ256rrk 4U, // VPCMPEQBZrm 1156U, // VPCMPEQBZrmk 4U, // VPCMPEQBZrr 1156U, // VPCMPEQBZrrk 4U, // VPCMPEQBrm 4U, // VPCMPEQBrr 4U, // VPCMPEQDYrm 4U, // VPCMPEQDYrr 4U, // VPCMPEQDZ128rm 72U, // VPCMPEQDZ128rmb 1156U, // VPCMPEQDZ128rmbk 1156U, // VPCMPEQDZ128rmk 4U, // VPCMPEQDZ128rr 1156U, // VPCMPEQDZ128rrk 4U, // VPCMPEQDZ256rm 72U, // VPCMPEQDZ256rmb 1156U, // VPCMPEQDZ256rmbk 1156U, // VPCMPEQDZ256rmk 4U, // VPCMPEQDZ256rr 1156U, // VPCMPEQDZ256rrk 4U, // VPCMPEQDZrm 72U, // VPCMPEQDZrmb 1156U, // VPCMPEQDZrmbk 1156U, // VPCMPEQDZrmk 4U, // VPCMPEQDZrr 1156U, // VPCMPEQDZrrk 4U, // VPCMPEQDrm 4U, // VPCMPEQDrr 4U, // VPCMPEQQYrm 4U, // VPCMPEQQYrr 4U, // VPCMPEQQZ128rm 72U, // VPCMPEQQZ128rmb 1156U, // VPCMPEQQZ128rmbk 1156U, // VPCMPEQQZ128rmk 4U, // VPCMPEQQZ128rr 1156U, // VPCMPEQQZ128rrk 4U, // VPCMPEQQZ256rm 72U, // VPCMPEQQZ256rmb 1156U, // VPCMPEQQZ256rmbk 1156U, // VPCMPEQQZ256rmk 4U, // VPCMPEQQZ256rr 1156U, // VPCMPEQQZ256rrk 4U, // VPCMPEQQZrm 72U, // VPCMPEQQZrmb 1156U, // VPCMPEQQZrmbk 1156U, // VPCMPEQQZrmk 4U, // VPCMPEQQZrr 1156U, // VPCMPEQQZrrk 4U, // VPCMPEQQrm 4U, // VPCMPEQQrr 4U, // VPCMPEQWYrm 4U, // VPCMPEQWYrr 4U, // VPCMPEQWZ128rm 1156U, // VPCMPEQWZ128rmk 4U, // VPCMPEQWZ128rr 1156U, // VPCMPEQWZ128rrk 4U, // VPCMPEQWZ256rm 1156U, // VPCMPEQWZ256rmk 4U, // VPCMPEQWZ256rr 1156U, // VPCMPEQWZ256rrk 4U, // VPCMPEQWZrm 1156U, // VPCMPEQWZrmk 4U, // VPCMPEQWZrr 1156U, // VPCMPEQWZrrk 4U, // VPCMPEQWrm 4U, // VPCMPEQWrr 4U, // VPCMPESTRIrm 72U, // VPCMPESTRIrr 4U, // VPCMPESTRMrm 72U, // VPCMPESTRMrr 4U, // VPCMPGTBYrm 4U, // VPCMPGTBYrr 4U, // VPCMPGTBZ128rm 1156U, // VPCMPGTBZ128rmk 4U, // VPCMPGTBZ128rr 1156U, // VPCMPGTBZ128rrk 4U, // VPCMPGTBZ256rm 1156U, // VPCMPGTBZ256rmk 4U, // VPCMPGTBZ256rr 1156U, // VPCMPGTBZ256rrk 4U, // VPCMPGTBZrm 1156U, // VPCMPGTBZrmk 4U, // VPCMPGTBZrr 1156U, // VPCMPGTBZrrk 4U, // VPCMPGTBrm 4U, // VPCMPGTBrr 4U, // VPCMPGTDYrm 4U, // VPCMPGTDYrr 4U, // VPCMPGTDZ128rm 72U, // VPCMPGTDZ128rmb 1156U, // VPCMPGTDZ128rmbk 1156U, // VPCMPGTDZ128rmk 4U, // VPCMPGTDZ128rr 1156U, // VPCMPGTDZ128rrk 4U, // VPCMPGTDZ256rm 72U, // VPCMPGTDZ256rmb 1156U, // VPCMPGTDZ256rmbk 1156U, // VPCMPGTDZ256rmk 4U, // VPCMPGTDZ256rr 1156U, // VPCMPGTDZ256rrk 4U, // VPCMPGTDZrm 72U, // VPCMPGTDZrmb 1156U, // VPCMPGTDZrmbk 1156U, // VPCMPGTDZrmk 4U, // VPCMPGTDZrr 1156U, // VPCMPGTDZrrk 4U, // VPCMPGTDrm 4U, // VPCMPGTDrr 4U, // VPCMPGTQYrm 4U, // VPCMPGTQYrr 4U, // VPCMPGTQZ128rm 72U, // VPCMPGTQZ128rmb 1156U, // VPCMPGTQZ128rmbk 1156U, // VPCMPGTQZ128rmk 4U, // VPCMPGTQZ128rr 1156U, // VPCMPGTQZ128rrk 4U, // VPCMPGTQZ256rm 72U, // VPCMPGTQZ256rmb 1156U, // VPCMPGTQZ256rmbk 1156U, // VPCMPGTQZ256rmk 4U, // VPCMPGTQZ256rr 1156U, // VPCMPGTQZ256rrk 4U, // VPCMPGTQZrm 72U, // VPCMPGTQZrmb 1156U, // VPCMPGTQZrmbk 1156U, // VPCMPGTQZrmk 4U, // VPCMPGTQZrr 1156U, // VPCMPGTQZrrk 4U, // VPCMPGTQrm 4U, // VPCMPGTQrr 4U, // VPCMPGTWYrm 4U, // VPCMPGTWYrr 4U, // VPCMPGTWZ128rm 1156U, // VPCMPGTWZ128rmk 4U, // VPCMPGTWZ128rr 1156U, // VPCMPGTWZ128rrk 4U, // VPCMPGTWZ256rm 1156U, // VPCMPGTWZ256rmk 4U, // VPCMPGTWZ256rr 1156U, // VPCMPGTWZ256rrk 4U, // VPCMPGTWZrm 1156U, // VPCMPGTWZrmk 4U, // VPCMPGTWZrr 1156U, // VPCMPGTWZrrk 4U, // VPCMPGTWrm 4U, // VPCMPGTWrr 4U, // VPCMPISTRIrm 72U, // VPCMPISTRIrr 4U, // VPCMPISTRMrm 72U, // VPCMPISTRMrr 2U, // VPCMPQZ128rmi 72U, // VPCMPQZ128rmi_alt 21859U, // VPCMPQZ128rmib 18637U, // VPCMPQZ128rmib_alt 29987U, // VPCMPQZ128rmibk 26837U, // VPCMPQZ128rmibk_alt 2U, // VPCMPQZ128rmik 1156U, // VPCMPQZ128rmik_alt 18636U, // VPCMPQZ128rri 18636U, // VPCMPQZ128rri_alt 26837U, // VPCMPQZ128rrik 26837U, // VPCMPQZ128rrik_alt 2U, // VPCMPQZ256rmi 72U, // VPCMPQZ256rmi_alt 21863U, // VPCMPQZ256rmib 18637U, // VPCMPQZ256rmib_alt 29991U, // VPCMPQZ256rmibk 26837U, // VPCMPQZ256rmibk_alt 2U, // VPCMPQZ256rmik 1156U, // VPCMPQZ256rmik_alt 18636U, // VPCMPQZ256rri 18636U, // VPCMPQZ256rri_alt 26837U, // VPCMPQZ256rrik 26837U, // VPCMPQZ256rrik_alt 2U, // VPCMPQZrmi 72U, // VPCMPQZrmi_alt 21867U, // VPCMPQZrmib 18637U, // VPCMPQZrmib_alt 29995U, // VPCMPQZrmibk 26837U, // VPCMPQZrmibk_alt 2U, // VPCMPQZrmik 1156U, // VPCMPQZrmik_alt 18636U, // VPCMPQZrri 18636U, // VPCMPQZrri_alt 26837U, // VPCMPQZrrik 26837U, // VPCMPQZrrik_alt 2U, // VPCMPUBZ128rmi 72U, // VPCMPUBZ128rmi_alt 2U, // VPCMPUBZ128rmik 1156U, // VPCMPUBZ128rmik_alt 18636U, // VPCMPUBZ128rri 18636U, // VPCMPUBZ128rri_alt 26837U, // VPCMPUBZ128rrik 26837U, // VPCMPUBZ128rrik_alt 2U, // VPCMPUBZ256rmi 72U, // VPCMPUBZ256rmi_alt 2U, // VPCMPUBZ256rmik 1156U, // VPCMPUBZ256rmik_alt 18636U, // VPCMPUBZ256rri 18636U, // VPCMPUBZ256rri_alt 26837U, // VPCMPUBZ256rrik 26837U, // VPCMPUBZ256rrik_alt 2U, // VPCMPUBZrmi 72U, // VPCMPUBZrmi_alt 2U, // VPCMPUBZrmik 1156U, // VPCMPUBZrmik_alt 18636U, // VPCMPUBZrri 18636U, // VPCMPUBZrri_alt 26837U, // VPCMPUBZrrik 26837U, // VPCMPUBZrrik_alt 2U, // VPCMPUDZ128rmi 72U, // VPCMPUDZ128rmi_alt 21863U, // VPCMPUDZ128rmib 18637U, // VPCMPUDZ128rmib_alt 29991U, // VPCMPUDZ128rmibk 26837U, // VPCMPUDZ128rmibk_alt 2U, // VPCMPUDZ128rmik 1156U, // VPCMPUDZ128rmik_alt 18636U, // VPCMPUDZ128rri 18636U, // VPCMPUDZ128rri_alt 26837U, // VPCMPUDZ128rrik 26837U, // VPCMPUDZ128rrik_alt 2U, // VPCMPUDZ256rmi 72U, // VPCMPUDZ256rmi_alt 21867U, // VPCMPUDZ256rmib 18637U, // VPCMPUDZ256rmib_alt 29995U, // VPCMPUDZ256rmibk 26837U, // VPCMPUDZ256rmibk_alt 2U, // VPCMPUDZ256rmik 1156U, // VPCMPUDZ256rmik_alt 18636U, // VPCMPUDZ256rri 18636U, // VPCMPUDZ256rri_alt 26837U, // VPCMPUDZ256rrik 26837U, // VPCMPUDZ256rrik_alt 2U, // VPCMPUDZrmi 72U, // VPCMPUDZrmi_alt 21871U, // VPCMPUDZrmib 18637U, // VPCMPUDZrmib_alt 29999U, // VPCMPUDZrmibk 26837U, // VPCMPUDZrmibk_alt 2U, // VPCMPUDZrmik 1156U, // VPCMPUDZrmik_alt 18636U, // VPCMPUDZrri 18636U, // VPCMPUDZrri_alt 26837U, // VPCMPUDZrrik 26837U, // VPCMPUDZrrik_alt 2U, // VPCMPUQZ128rmi 72U, // VPCMPUQZ128rmi_alt 21859U, // VPCMPUQZ128rmib 18637U, // VPCMPUQZ128rmib_alt 29987U, // VPCMPUQZ128rmibk 26837U, // VPCMPUQZ128rmibk_alt 2U, // VPCMPUQZ128rmik 1156U, // VPCMPUQZ128rmik_alt 18636U, // VPCMPUQZ128rri 18636U, // VPCMPUQZ128rri_alt 26837U, // VPCMPUQZ128rrik 26837U, // VPCMPUQZ128rrik_alt 2U, // VPCMPUQZ256rmi 72U, // VPCMPUQZ256rmi_alt 21863U, // VPCMPUQZ256rmib 18637U, // VPCMPUQZ256rmib_alt 29991U, // VPCMPUQZ256rmibk 26837U, // VPCMPUQZ256rmibk_alt 2U, // VPCMPUQZ256rmik 1156U, // VPCMPUQZ256rmik_alt 18636U, // VPCMPUQZ256rri 18636U, // VPCMPUQZ256rri_alt 26837U, // VPCMPUQZ256rrik 26837U, // VPCMPUQZ256rrik_alt 2U, // VPCMPUQZrmi 72U, // VPCMPUQZrmi_alt 21867U, // VPCMPUQZrmib 18637U, // VPCMPUQZrmib_alt 29995U, // VPCMPUQZrmibk 26837U, // VPCMPUQZrmibk_alt 2U, // VPCMPUQZrmik 1156U, // VPCMPUQZrmik_alt 18636U, // VPCMPUQZrri 18636U, // VPCMPUQZrri_alt 26837U, // VPCMPUQZrrik 26837U, // VPCMPUQZrrik_alt 2U, // VPCMPUWZ128rmi 72U, // VPCMPUWZ128rmi_alt 2U, // VPCMPUWZ128rmik 1156U, // VPCMPUWZ128rmik_alt 18636U, // VPCMPUWZ128rri 18636U, // VPCMPUWZ128rri_alt 26837U, // VPCMPUWZ128rrik 26837U, // VPCMPUWZ128rrik_alt 2U, // VPCMPUWZ256rmi 72U, // VPCMPUWZ256rmi_alt 2U, // VPCMPUWZ256rmik 1156U, // VPCMPUWZ256rmik_alt 18636U, // VPCMPUWZ256rri 18636U, // VPCMPUWZ256rri_alt 26837U, // VPCMPUWZ256rrik 26837U, // VPCMPUWZ256rrik_alt 2U, // VPCMPUWZrmi 72U, // VPCMPUWZrmi_alt 2U, // VPCMPUWZrmik 1156U, // VPCMPUWZrmik_alt 18636U, // VPCMPUWZrri 18636U, // VPCMPUWZrri_alt 26837U, // VPCMPUWZrrik 26837U, // VPCMPUWZrrik_alt 2U, // VPCMPWZ128rmi 72U, // VPCMPWZ128rmi_alt 2U, // VPCMPWZ128rmik 1156U, // VPCMPWZ128rmik_alt 18636U, // VPCMPWZ128rri 18636U, // VPCMPWZ128rri_alt 26837U, // VPCMPWZ128rrik 26837U, // VPCMPWZ128rrik_alt 2U, // VPCMPWZ256rmi 72U, // VPCMPWZ256rmi_alt 2U, // VPCMPWZ256rmik 1156U, // VPCMPWZ256rmik_alt 18636U, // VPCMPWZ256rri 18636U, // VPCMPWZ256rri_alt 26837U, // VPCMPWZ256rrik 26837U, // VPCMPWZ256rrik_alt 2U, // VPCMPWZrmi 72U, // VPCMPWZrmi_alt 2U, // VPCMPWZrmik 1156U, // VPCMPWZrmik_alt 18636U, // VPCMPWZrri 18636U, // VPCMPWZrri_alt 26837U, // VPCMPWZrrik 26837U, // VPCMPWZrrik_alt 2U, // VPCOMBmi 72U, // VPCOMBmi_alt 18636U, // VPCOMBri 18636U, // VPCOMBri_alt 2U, // VPCOMDmi 72U, // VPCOMDmi_alt 18636U, // VPCOMDri 18636U, // VPCOMDri_alt 0U, // VPCOMPRESSBZ128mr 49U, // VPCOMPRESSBZ128mrk 0U, // VPCOMPRESSBZ128rr 405U, // VPCOMPRESSBZ128rrk 461U, // VPCOMPRESSBZ128rrkz 0U, // VPCOMPRESSBZ256mr 49U, // VPCOMPRESSBZ256mrk 0U, // VPCOMPRESSBZ256rr 405U, // VPCOMPRESSBZ256rrk 461U, // VPCOMPRESSBZ256rrkz 0U, // VPCOMPRESSBZmr 49U, // VPCOMPRESSBZmrk 0U, // VPCOMPRESSBZrr 405U, // VPCOMPRESSBZrrk 461U, // VPCOMPRESSBZrrkz 0U, // VPCOMPRESSDZ128mr 49U, // VPCOMPRESSDZ128mrk 0U, // VPCOMPRESSDZ128rr 405U, // VPCOMPRESSDZ128rrk 461U, // VPCOMPRESSDZ128rrkz 0U, // VPCOMPRESSDZ256mr 49U, // VPCOMPRESSDZ256mrk 0U, // VPCOMPRESSDZ256rr 405U, // VPCOMPRESSDZ256rrk 461U, // VPCOMPRESSDZ256rrkz 0U, // VPCOMPRESSDZmr 49U, // VPCOMPRESSDZmrk 0U, // VPCOMPRESSDZrr 405U, // VPCOMPRESSDZrrk 461U, // VPCOMPRESSDZrrkz 0U, // VPCOMPRESSQZ128mr 49U, // VPCOMPRESSQZ128mrk 0U, // VPCOMPRESSQZ128rr 405U, // VPCOMPRESSQZ128rrk 461U, // VPCOMPRESSQZ128rrkz 0U, // VPCOMPRESSQZ256mr 49U, // VPCOMPRESSQZ256mrk 0U, // VPCOMPRESSQZ256rr 405U, // VPCOMPRESSQZ256rrk 461U, // VPCOMPRESSQZ256rrkz 0U, // VPCOMPRESSQZmr 49U, // VPCOMPRESSQZmrk 0U, // VPCOMPRESSQZrr 405U, // VPCOMPRESSQZrrk 461U, // VPCOMPRESSQZrrkz 0U, // VPCOMPRESSWZ128mr 49U, // VPCOMPRESSWZ128mrk 0U, // VPCOMPRESSWZ128rr 405U, // VPCOMPRESSWZ128rrk 461U, // VPCOMPRESSWZ128rrkz 0U, // VPCOMPRESSWZ256mr 49U, // VPCOMPRESSWZ256mrk 0U, // VPCOMPRESSWZ256rr 405U, // VPCOMPRESSWZ256rrk 461U, // VPCOMPRESSWZ256rrkz 0U, // VPCOMPRESSWZmr 49U, // VPCOMPRESSWZmrk 0U, // VPCOMPRESSWZrr 405U, // VPCOMPRESSWZrrk 461U, // VPCOMPRESSWZrrkz 2U, // VPCOMQmi 72U, // VPCOMQmi_alt 18636U, // VPCOMQri 18636U, // VPCOMQri_alt 2U, // VPCOMUBmi 72U, // VPCOMUBmi_alt 18636U, // VPCOMUBri 18636U, // VPCOMUBri_alt 2U, // VPCOMUDmi 72U, // VPCOMUDmi_alt 18636U, // VPCOMUDri 18636U, // VPCOMUDri_alt 2U, // VPCOMUQmi 72U, // VPCOMUQmi_alt 18636U, // VPCOMUQri 18636U, // VPCOMUQri_alt 2U, // VPCOMUWmi 72U, // VPCOMUWmi_alt 18636U, // VPCOMUWri 18636U, // VPCOMUWri_alt 2U, // VPCOMWmi 72U, // VPCOMWmi_alt 18636U, // VPCOMWri 18636U, // VPCOMWri_alt 0U, // VPCONFLICTDZ128rm 0U, // VPCONFLICTDZ128rmb 3356U, // VPCONFLICTDZ128rmbk 4444U, // VPCONFLICTDZ128rmbkz 405U, // VPCONFLICTDZ128rmk 461U, // VPCONFLICTDZ128rmkz 0U, // VPCONFLICTDZ128rr 405U, // VPCONFLICTDZ128rrk 461U, // VPCONFLICTDZ128rrkz 0U, // VPCONFLICTDZ256rm 0U, // VPCONFLICTDZ256rmb 3356U, // VPCONFLICTDZ256rmbk 4444U, // VPCONFLICTDZ256rmbkz 405U, // VPCONFLICTDZ256rmk 461U, // VPCONFLICTDZ256rmkz 0U, // VPCONFLICTDZ256rr 405U, // VPCONFLICTDZ256rrk 461U, // VPCONFLICTDZ256rrkz 0U, // VPCONFLICTDZrm 0U, // VPCONFLICTDZrmb 3356U, // VPCONFLICTDZrmbk 4444U, // VPCONFLICTDZrmbkz 405U, // VPCONFLICTDZrmk 461U, // VPCONFLICTDZrmkz 0U, // VPCONFLICTDZrr 405U, // VPCONFLICTDZrrk 461U, // VPCONFLICTDZrrkz 0U, // VPCONFLICTQZ128rm 0U, // VPCONFLICTQZ128rmb 3356U, // VPCONFLICTQZ128rmbk 4444U, // VPCONFLICTQZ128rmbkz 405U, // VPCONFLICTQZ128rmk 461U, // VPCONFLICTQZ128rmkz 0U, // VPCONFLICTQZ128rr 405U, // VPCONFLICTQZ128rrk 461U, // VPCONFLICTQZ128rrkz 0U, // VPCONFLICTQZ256rm 0U, // VPCONFLICTQZ256rmb 3356U, // VPCONFLICTQZ256rmbk 4444U, // VPCONFLICTQZ256rmbkz 405U, // VPCONFLICTQZ256rmk 461U, // VPCONFLICTQZ256rmkz 0U, // VPCONFLICTQZ256rr 405U, // VPCONFLICTQZ256rrk 461U, // VPCONFLICTQZ256rrkz 0U, // VPCONFLICTQZrm 0U, // VPCONFLICTQZrmb 3356U, // VPCONFLICTQZrmbk 4444U, // VPCONFLICTQZrmbkz 405U, // VPCONFLICTQZrmk 461U, // VPCONFLICTQZrmkz 0U, // VPCONFLICTQZrr 405U, // VPCONFLICTQZrrk 461U, // VPCONFLICTQZrrkz 4U, // VPDPBUSDSZ128m 4U, // VPDPBUSDSZ128mb 133U, // VPDPBUSDSZ128mbk 8325U, // VPDPBUSDSZ128mbkz 132U, // VPDPBUSDSZ128mk 8324U, // VPDPBUSDSZ128mkz 4U, // VPDPBUSDSZ128r 0U, // VPDPBUSDSZ128rk 0U, // VPDPBUSDSZ128rkz 4U, // VPDPBUSDSZ256m 4U, // VPDPBUSDSZ256mb 133U, // VPDPBUSDSZ256mbk 8325U, // VPDPBUSDSZ256mbkz 132U, // VPDPBUSDSZ256mk 8324U, // VPDPBUSDSZ256mkz 4U, // VPDPBUSDSZ256r 0U, // VPDPBUSDSZ256rk 0U, // VPDPBUSDSZ256rkz 4U, // VPDPBUSDSZm 4U, // VPDPBUSDSZmb 133U, // VPDPBUSDSZmbk 8325U, // VPDPBUSDSZmbkz 132U, // VPDPBUSDSZmk 8324U, // VPDPBUSDSZmkz 4U, // VPDPBUSDSZr 0U, // VPDPBUSDSZrk 0U, // VPDPBUSDSZrkz 4U, // VPDPBUSDZ128m 4U, // VPDPBUSDZ128mb 133U, // VPDPBUSDZ128mbk 8325U, // VPDPBUSDZ128mbkz 132U, // VPDPBUSDZ128mk 8324U, // VPDPBUSDZ128mkz 4U, // VPDPBUSDZ128r 0U, // VPDPBUSDZ128rk 0U, // VPDPBUSDZ128rkz 4U, // VPDPBUSDZ256m 4U, // VPDPBUSDZ256mb 133U, // VPDPBUSDZ256mbk 8325U, // VPDPBUSDZ256mbkz 132U, // VPDPBUSDZ256mk 8324U, // VPDPBUSDZ256mkz 4U, // VPDPBUSDZ256r 0U, // VPDPBUSDZ256rk 0U, // VPDPBUSDZ256rkz 4U, // VPDPBUSDZm 4U, // VPDPBUSDZmb 133U, // VPDPBUSDZmbk 8325U, // VPDPBUSDZmbkz 132U, // VPDPBUSDZmk 8324U, // VPDPBUSDZmkz 4U, // VPDPBUSDZr 0U, // VPDPBUSDZrk 0U, // VPDPBUSDZrkz 4U, // VPDPWSSDSZ128m 4U, // VPDPWSSDSZ128mb 133U, // VPDPWSSDSZ128mbk 8325U, // VPDPWSSDSZ128mbkz 132U, // VPDPWSSDSZ128mk 8324U, // VPDPWSSDSZ128mkz 4U, // VPDPWSSDSZ128r 0U, // VPDPWSSDSZ128rk 0U, // VPDPWSSDSZ128rkz 4U, // VPDPWSSDSZ256m 4U, // VPDPWSSDSZ256mb 133U, // VPDPWSSDSZ256mbk 8325U, // VPDPWSSDSZ256mbkz 132U, // VPDPWSSDSZ256mk 8324U, // VPDPWSSDSZ256mkz 4U, // VPDPWSSDSZ256r 0U, // VPDPWSSDSZ256rk 0U, // VPDPWSSDSZ256rkz 4U, // VPDPWSSDSZm 4U, // VPDPWSSDSZmb 133U, // VPDPWSSDSZmbk 8325U, // VPDPWSSDSZmbkz 132U, // VPDPWSSDSZmk 8324U, // VPDPWSSDSZmkz 4U, // VPDPWSSDSZr 0U, // VPDPWSSDSZrk 0U, // VPDPWSSDSZrkz 4U, // VPDPWSSDZ128m 4U, // VPDPWSSDZ128mb 133U, // VPDPWSSDZ128mbk 8325U, // VPDPWSSDZ128mbkz 132U, // VPDPWSSDZ128mk 8324U, // VPDPWSSDZ128mkz 4U, // VPDPWSSDZ128r 0U, // VPDPWSSDZ128rk 0U, // VPDPWSSDZ128rkz 4U, // VPDPWSSDZ256m 4U, // VPDPWSSDZ256mb 133U, // VPDPWSSDZ256mbk 8325U, // VPDPWSSDZ256mbkz 132U, // VPDPWSSDZ256mk 8324U, // VPDPWSSDZ256mkz 4U, // VPDPWSSDZ256r 0U, // VPDPWSSDZ256rk 0U, // VPDPWSSDZ256rkz 4U, // VPDPWSSDZm 4U, // VPDPWSSDZmb 133U, // VPDPWSSDZmbk 8325U, // VPDPWSSDZmbkz 132U, // VPDPWSSDZmk 8324U, // VPDPWSSDZmkz 4U, // VPDPWSSDZr 0U, // VPDPWSSDZrk 0U, // VPDPWSSDZrkz 72U, // VPERM2F128rm 18636U, // VPERM2F128rr 72U, // VPERM2I128rm 18636U, // VPERM2I128rr 4U, // VPERMBZ128rm 132U, // VPERMBZ128rmk 9348U, // VPERMBZ128rmkz 4U, // VPERMBZ128rr 0U, // VPERMBZ128rrk 9348U, // VPERMBZ128rrkz 4U, // VPERMBZ256rm 132U, // VPERMBZ256rmk 9348U, // VPERMBZ256rmkz 4U, // VPERMBZ256rr 0U, // VPERMBZ256rrk 9348U, // VPERMBZ256rrkz 4U, // VPERMBZrm 132U, // VPERMBZrmk 9348U, // VPERMBZrmkz 4U, // VPERMBZrr 0U, // VPERMBZrrk 9348U, // VPERMBZrrkz 4U, // VPERMDYrm 4U, // VPERMDYrr 4U, // VPERMDZ256rm 72U, // VPERMDZ256rmb 133U, // VPERMDZ256rmbk 9348U, // VPERMDZ256rmbkz 132U, // VPERMDZ256rmk 9348U, // VPERMDZ256rmkz 4U, // VPERMDZ256rr 0U, // VPERMDZ256rrk 9348U, // VPERMDZ256rrkz 4U, // VPERMDZrm 72U, // VPERMDZrmb 133U, // VPERMDZrmbk 9348U, // VPERMDZrmbkz 132U, // VPERMDZrmk 9348U, // VPERMDZrmkz 4U, // VPERMDZrr 0U, // VPERMDZrrk 9348U, // VPERMDZrrkz 4U, // VPERMI2B128rm 132U, // VPERMI2B128rmk 8324U, // VPERMI2B128rmkz 4U, // VPERMI2B128rr 0U, // VPERMI2B128rrk 0U, // VPERMI2B128rrkz 4U, // VPERMI2B256rm 132U, // VPERMI2B256rmk 8324U, // VPERMI2B256rmkz 4U, // VPERMI2B256rr 0U, // VPERMI2B256rrk 0U, // VPERMI2B256rrkz 4U, // VPERMI2Brm 132U, // VPERMI2Brmk 8324U, // VPERMI2Brmkz 4U, // VPERMI2Brr 0U, // VPERMI2Brrk 0U, // VPERMI2Brrkz 4U, // VPERMI2D128rm 4U, // VPERMI2D128rmb 133U, // VPERMI2D128rmbk 8325U, // VPERMI2D128rmbkz 132U, // VPERMI2D128rmk 8324U, // VPERMI2D128rmkz 4U, // VPERMI2D128rr 0U, // VPERMI2D128rrk 0U, // VPERMI2D128rrkz 4U, // VPERMI2D256rm 4U, // VPERMI2D256rmb 133U, // VPERMI2D256rmbk 8325U, // VPERMI2D256rmbkz 132U, // VPERMI2D256rmk 8324U, // VPERMI2D256rmkz 4U, // VPERMI2D256rr 0U, // VPERMI2D256rrk 0U, // VPERMI2D256rrkz 4U, // VPERMI2Drm 4U, // VPERMI2Drmb 133U, // VPERMI2Drmbk 8325U, // VPERMI2Drmbkz 132U, // VPERMI2Drmk 8324U, // VPERMI2Drmkz 4U, // VPERMI2Drr 0U, // VPERMI2Drrk 0U, // VPERMI2Drrkz 4U, // VPERMI2PD128rm 4U, // VPERMI2PD128rmb 133U, // VPERMI2PD128rmbk 8325U, // VPERMI2PD128rmbkz 0U, // VPERMI2PD128rmk 0U, // VPERMI2PD128rmkz 4U, // VPERMI2PD128rr 0U, // VPERMI2PD128rrk 0U, // VPERMI2PD128rrkz 4U, // VPERMI2PD256rm 4U, // VPERMI2PD256rmb 133U, // VPERMI2PD256rmbk 8325U, // VPERMI2PD256rmbkz 0U, // VPERMI2PD256rmk 0U, // VPERMI2PD256rmkz 4U, // VPERMI2PD256rr 0U, // VPERMI2PD256rrk 0U, // VPERMI2PD256rrkz 4U, // VPERMI2PDrm 4U, // VPERMI2PDrmb 133U, // VPERMI2PDrmbk 8325U, // VPERMI2PDrmbkz 0U, // VPERMI2PDrmk 0U, // VPERMI2PDrmkz 4U, // VPERMI2PDrr 0U, // VPERMI2PDrrk 0U, // VPERMI2PDrrkz 4U, // VPERMI2PS128rm 4U, // VPERMI2PS128rmb 133U, // VPERMI2PS128rmbk 8325U, // VPERMI2PS128rmbkz 0U, // VPERMI2PS128rmk 0U, // VPERMI2PS128rmkz 4U, // VPERMI2PS128rr 0U, // VPERMI2PS128rrk 0U, // VPERMI2PS128rrkz 4U, // VPERMI2PS256rm 4U, // VPERMI2PS256rmb 133U, // VPERMI2PS256rmbk 8325U, // VPERMI2PS256rmbkz 0U, // VPERMI2PS256rmk 0U, // VPERMI2PS256rmkz 4U, // VPERMI2PS256rr 0U, // VPERMI2PS256rrk 0U, // VPERMI2PS256rrkz 4U, // VPERMI2PSrm 4U, // VPERMI2PSrmb 133U, // VPERMI2PSrmbk 8325U, // VPERMI2PSrmbkz 0U, // VPERMI2PSrmk 0U, // VPERMI2PSrmkz 4U, // VPERMI2PSrr 0U, // VPERMI2PSrrk 0U, // VPERMI2PSrrkz 4U, // VPERMI2Q128rm 4U, // VPERMI2Q128rmb 133U, // VPERMI2Q128rmbk 8325U, // VPERMI2Q128rmbkz 132U, // VPERMI2Q128rmk 8324U, // VPERMI2Q128rmkz 4U, // VPERMI2Q128rr 0U, // VPERMI2Q128rrk 0U, // VPERMI2Q128rrkz 4U, // VPERMI2Q256rm 4U, // VPERMI2Q256rmb 133U, // VPERMI2Q256rmbk 8325U, // VPERMI2Q256rmbkz 132U, // VPERMI2Q256rmk 8324U, // VPERMI2Q256rmkz 4U, // VPERMI2Q256rr 0U, // VPERMI2Q256rrk 0U, // VPERMI2Q256rrkz 4U, // VPERMI2Qrm 4U, // VPERMI2Qrmb 133U, // VPERMI2Qrmbk 8325U, // VPERMI2Qrmbkz 132U, // VPERMI2Qrmk 8324U, // VPERMI2Qrmkz 4U, // VPERMI2Qrr 0U, // VPERMI2Qrrk 0U, // VPERMI2Qrrkz 4U, // VPERMI2W128rm 132U, // VPERMI2W128rmk 8324U, // VPERMI2W128rmkz 4U, // VPERMI2W128rr 0U, // VPERMI2W128rrk 0U, // VPERMI2W128rrkz 4U, // VPERMI2W256rm 132U, // VPERMI2W256rmk 8324U, // VPERMI2W256rmkz 4U, // VPERMI2W256rr 0U, // VPERMI2W256rrk 0U, // VPERMI2W256rrkz 4U, // VPERMI2Wrm 132U, // VPERMI2Wrmk 8324U, // VPERMI2Wrmkz 4U, // VPERMI2Wrr 0U, // VPERMI2Wrrk 0U, // VPERMI2Wrrkz 1U, // VPERMIL2PDYmr 18636U, // VPERMIL2PDYrm 34005U, // VPERMIL2PDYrr 34005U, // VPERMIL2PDYrr_REV 18636U, // VPERMIL2PDmr 18636U, // VPERMIL2PDrm 34005U, // VPERMIL2PDrr 34005U, // VPERMIL2PDrr_REV 1U, // VPERMIL2PSYmr 18636U, // VPERMIL2PSYrm 34005U, // VPERMIL2PSYrr 34005U, // VPERMIL2PSYrr_REV 18636U, // VPERMIL2PSmr 18636U, // VPERMIL2PSrm 34005U, // VPERMIL2PSrr 34005U, // VPERMIL2PSrr_REV 0U, // VPERMILPDYmi 72U, // VPERMILPDYri 4U, // VPERMILPDYrm 4U, // VPERMILPDYrr 5U, // VPERMILPDZ128mbi 133U, // VPERMILPDZ128mbik 9349U, // VPERMILPDZ128mbikz 0U, // VPERMILPDZ128mi 3356U, // VPERMILPDZ128mik 4444U, // VPERMILPDZ128mikz 72U, // VPERMILPDZ128ri 133U, // VPERMILPDZ128rik 9348U, // VPERMILPDZ128rikz 4U, // VPERMILPDZ128rm 72U, // VPERMILPDZ128rmb 133U, // VPERMILPDZ128rmbk 9348U, // VPERMILPDZ128rmbkz 132U, // VPERMILPDZ128rmk 9348U, // VPERMILPDZ128rmkz 4U, // VPERMILPDZ128rr 0U, // VPERMILPDZ128rrk 9348U, // VPERMILPDZ128rrkz 5U, // VPERMILPDZ256mbi 133U, // VPERMILPDZ256mbik 9349U, // VPERMILPDZ256mbikz 0U, // VPERMILPDZ256mi 3356U, // VPERMILPDZ256mik 4444U, // VPERMILPDZ256mikz 72U, // VPERMILPDZ256ri 133U, // VPERMILPDZ256rik 9348U, // VPERMILPDZ256rikz 4U, // VPERMILPDZ256rm 72U, // VPERMILPDZ256rmb 133U, // VPERMILPDZ256rmbk 9348U, // VPERMILPDZ256rmbkz 132U, // VPERMILPDZ256rmk 9348U, // VPERMILPDZ256rmkz 4U, // VPERMILPDZ256rr 0U, // VPERMILPDZ256rrk 9348U, // VPERMILPDZ256rrkz 5U, // VPERMILPDZmbi 133U, // VPERMILPDZmbik 9349U, // VPERMILPDZmbikz 0U, // VPERMILPDZmi 3356U, // VPERMILPDZmik 4444U, // VPERMILPDZmikz 72U, // VPERMILPDZri 133U, // VPERMILPDZrik 9348U, // VPERMILPDZrikz 4U, // VPERMILPDZrm 72U, // VPERMILPDZrmb 133U, // VPERMILPDZrmbk 9348U, // VPERMILPDZrmbkz 132U, // VPERMILPDZrmk 9348U, // VPERMILPDZrmkz 4U, // VPERMILPDZrr 0U, // VPERMILPDZrrk 9348U, // VPERMILPDZrrkz 0U, // VPERMILPDmi 72U, // VPERMILPDri 4U, // VPERMILPDrm 4U, // VPERMILPDrr 0U, // VPERMILPSYmi 72U, // VPERMILPSYri 4U, // VPERMILPSYrm 4U, // VPERMILPSYrr 5U, // VPERMILPSZ128mbi 133U, // VPERMILPSZ128mbik 9349U, // VPERMILPSZ128mbikz 0U, // VPERMILPSZ128mi 3356U, // VPERMILPSZ128mik 4444U, // VPERMILPSZ128mikz 72U, // VPERMILPSZ128ri 133U, // VPERMILPSZ128rik 9348U, // VPERMILPSZ128rikz 4U, // VPERMILPSZ128rm 72U, // VPERMILPSZ128rmb 133U, // VPERMILPSZ128rmbk 9348U, // VPERMILPSZ128rmbkz 132U, // VPERMILPSZ128rmk 9348U, // VPERMILPSZ128rmkz 4U, // VPERMILPSZ128rr 0U, // VPERMILPSZ128rrk 9348U, // VPERMILPSZ128rrkz 5U, // VPERMILPSZ256mbi 133U, // VPERMILPSZ256mbik 9349U, // VPERMILPSZ256mbikz 0U, // VPERMILPSZ256mi 3356U, // VPERMILPSZ256mik 4444U, // VPERMILPSZ256mikz 72U, // VPERMILPSZ256ri 133U, // VPERMILPSZ256rik 9348U, // VPERMILPSZ256rikz 4U, // VPERMILPSZ256rm 72U, // VPERMILPSZ256rmb 133U, // VPERMILPSZ256rmbk 9348U, // VPERMILPSZ256rmbkz 132U, // VPERMILPSZ256rmk 9348U, // VPERMILPSZ256rmkz 4U, // VPERMILPSZ256rr 0U, // VPERMILPSZ256rrk 9348U, // VPERMILPSZ256rrkz 5U, // VPERMILPSZmbi 133U, // VPERMILPSZmbik 9349U, // VPERMILPSZmbikz 0U, // VPERMILPSZmi 3356U, // VPERMILPSZmik 4444U, // VPERMILPSZmikz 72U, // VPERMILPSZri 133U, // VPERMILPSZrik 9348U, // VPERMILPSZrikz 4U, // VPERMILPSZrm 72U, // VPERMILPSZrmb 133U, // VPERMILPSZrmbk 9348U, // VPERMILPSZrmbkz 132U, // VPERMILPSZrmk 9348U, // VPERMILPSZrmkz 4U, // VPERMILPSZrr 0U, // VPERMILPSZrrk 9348U, // VPERMILPSZrrkz 0U, // VPERMILPSmi 72U, // VPERMILPSri 4U, // VPERMILPSrm 4U, // VPERMILPSrr 0U, // VPERMPDYmi 72U, // VPERMPDYri 5U, // VPERMPDZ256mbi 133U, // VPERMPDZ256mbik 9349U, // VPERMPDZ256mbikz 0U, // VPERMPDZ256mi 3356U, // VPERMPDZ256mik 4444U, // VPERMPDZ256mikz 72U, // VPERMPDZ256ri 133U, // VPERMPDZ256rik 9348U, // VPERMPDZ256rikz 4U, // VPERMPDZ256rm 72U, // VPERMPDZ256rmb 133U, // VPERMPDZ256rmbk 9348U, // VPERMPDZ256rmbkz 0U, // VPERMPDZ256rmk 9348U, // VPERMPDZ256rmkz 4U, // VPERMPDZ256rr 0U, // VPERMPDZ256rrk 9348U, // VPERMPDZ256rrkz 5U, // VPERMPDZmbi 133U, // VPERMPDZmbik 9349U, // VPERMPDZmbikz 0U, // VPERMPDZmi 3356U, // VPERMPDZmik 4444U, // VPERMPDZmikz 72U, // VPERMPDZri 133U, // VPERMPDZrik 9348U, // VPERMPDZrikz 4U, // VPERMPDZrm 72U, // VPERMPDZrmb 133U, // VPERMPDZrmbk 9348U, // VPERMPDZrmbkz 0U, // VPERMPDZrmk 9348U, // VPERMPDZrmkz 4U, // VPERMPDZrr 0U, // VPERMPDZrrk 9348U, // VPERMPDZrrkz 4U, // VPERMPSYrm 4U, // VPERMPSYrr 4U, // VPERMPSZ256rm 72U, // VPERMPSZ256rmb 133U, // VPERMPSZ256rmbk 9348U, // VPERMPSZ256rmbkz 0U, // VPERMPSZ256rmk 9348U, // VPERMPSZ256rmkz 4U, // VPERMPSZ256rr 0U, // VPERMPSZ256rrk 9348U, // VPERMPSZ256rrkz 4U, // VPERMPSZrm 72U, // VPERMPSZrmb 133U, // VPERMPSZrmbk 9348U, // VPERMPSZrmbkz 0U, // VPERMPSZrmk 9348U, // VPERMPSZrmkz 4U, // VPERMPSZrr 0U, // VPERMPSZrrk 9348U, // VPERMPSZrrkz 4U, // VPERMQYmi 72U, // VPERMQYri 5U, // VPERMQZ256mbi 133U, // VPERMQZ256mbik 9349U, // VPERMQZ256mbikz 4U, // VPERMQZ256mi 3356U, // VPERMQZ256mik 4444U, // VPERMQZ256mikz 72U, // VPERMQZ256ri 133U, // VPERMQZ256rik 9348U, // VPERMQZ256rikz 4U, // VPERMQZ256rm 72U, // VPERMQZ256rmb 133U, // VPERMQZ256rmbk 9348U, // VPERMQZ256rmbkz 132U, // VPERMQZ256rmk 9348U, // VPERMQZ256rmkz 4U, // VPERMQZ256rr 0U, // VPERMQZ256rrk 9348U, // VPERMQZ256rrkz 5U, // VPERMQZmbi 133U, // VPERMQZmbik 9349U, // VPERMQZmbikz 4U, // VPERMQZmi 3356U, // VPERMQZmik 4444U, // VPERMQZmikz 72U, // VPERMQZri 133U, // VPERMQZrik 9348U, // VPERMQZrikz 4U, // VPERMQZrm 72U, // VPERMQZrmb 133U, // VPERMQZrmbk 9348U, // VPERMQZrmbkz 132U, // VPERMQZrmk 9348U, // VPERMQZrmkz 4U, // VPERMQZrr 0U, // VPERMQZrrk 9348U, // VPERMQZrrkz 4U, // VPERMT2B128rm 132U, // VPERMT2B128rmk 8324U, // VPERMT2B128rmkz 4U, // VPERMT2B128rr 0U, // VPERMT2B128rrk 0U, // VPERMT2B128rrkz 4U, // VPERMT2B256rm 132U, // VPERMT2B256rmk 8324U, // VPERMT2B256rmkz 4U, // VPERMT2B256rr 0U, // VPERMT2B256rrk 0U, // VPERMT2B256rrkz 4U, // VPERMT2Brm 132U, // VPERMT2Brmk 8324U, // VPERMT2Brmkz 4U, // VPERMT2Brr 0U, // VPERMT2Brrk 0U, // VPERMT2Brrkz 4U, // VPERMT2D128rm 4U, // VPERMT2D128rmb 133U, // VPERMT2D128rmbk 8325U, // VPERMT2D128rmbkz 132U, // VPERMT2D128rmk 8324U, // VPERMT2D128rmkz 4U, // VPERMT2D128rr 0U, // VPERMT2D128rrk 0U, // VPERMT2D128rrkz 4U, // VPERMT2D256rm 4U, // VPERMT2D256rmb 133U, // VPERMT2D256rmbk 8325U, // VPERMT2D256rmbkz 132U, // VPERMT2D256rmk 8324U, // VPERMT2D256rmkz 4U, // VPERMT2D256rr 0U, // VPERMT2D256rrk 0U, // VPERMT2D256rrkz 4U, // VPERMT2Drm 4U, // VPERMT2Drmb 133U, // VPERMT2Drmbk 8325U, // VPERMT2Drmbkz 132U, // VPERMT2Drmk 8324U, // VPERMT2Drmkz 4U, // VPERMT2Drr 0U, // VPERMT2Drrk 0U, // VPERMT2Drrkz 4U, // VPERMT2PD128rm 4U, // VPERMT2PD128rmb 133U, // VPERMT2PD128rmbk 8325U, // VPERMT2PD128rmbkz 0U, // VPERMT2PD128rmk 0U, // VPERMT2PD128rmkz 4U, // VPERMT2PD128rr 0U, // VPERMT2PD128rrk 0U, // VPERMT2PD128rrkz 4U, // VPERMT2PD256rm 4U, // VPERMT2PD256rmb 133U, // VPERMT2PD256rmbk 8325U, // VPERMT2PD256rmbkz 0U, // VPERMT2PD256rmk 0U, // VPERMT2PD256rmkz 4U, // VPERMT2PD256rr 0U, // VPERMT2PD256rrk 0U, // VPERMT2PD256rrkz 4U, // VPERMT2PDrm 4U, // VPERMT2PDrmb 133U, // VPERMT2PDrmbk 8325U, // VPERMT2PDrmbkz 0U, // VPERMT2PDrmk 0U, // VPERMT2PDrmkz 4U, // VPERMT2PDrr 0U, // VPERMT2PDrrk 0U, // VPERMT2PDrrkz 4U, // VPERMT2PS128rm 4U, // VPERMT2PS128rmb 133U, // VPERMT2PS128rmbk 8325U, // VPERMT2PS128rmbkz 0U, // VPERMT2PS128rmk 0U, // VPERMT2PS128rmkz 4U, // VPERMT2PS128rr 0U, // VPERMT2PS128rrk 0U, // VPERMT2PS128rrkz 4U, // VPERMT2PS256rm 4U, // VPERMT2PS256rmb 133U, // VPERMT2PS256rmbk 8325U, // VPERMT2PS256rmbkz 0U, // VPERMT2PS256rmk 0U, // VPERMT2PS256rmkz 4U, // VPERMT2PS256rr 0U, // VPERMT2PS256rrk 0U, // VPERMT2PS256rrkz 4U, // VPERMT2PSrm 4U, // VPERMT2PSrmb 133U, // VPERMT2PSrmbk 8325U, // VPERMT2PSrmbkz 0U, // VPERMT2PSrmk 0U, // VPERMT2PSrmkz 4U, // VPERMT2PSrr 0U, // VPERMT2PSrrk 0U, // VPERMT2PSrrkz 4U, // VPERMT2Q128rm 4U, // VPERMT2Q128rmb 133U, // VPERMT2Q128rmbk 8325U, // VPERMT2Q128rmbkz 132U, // VPERMT2Q128rmk 8324U, // VPERMT2Q128rmkz 4U, // VPERMT2Q128rr 0U, // VPERMT2Q128rrk 0U, // VPERMT2Q128rrkz 4U, // VPERMT2Q256rm 4U, // VPERMT2Q256rmb 133U, // VPERMT2Q256rmbk 8325U, // VPERMT2Q256rmbkz 132U, // VPERMT2Q256rmk 8324U, // VPERMT2Q256rmkz 4U, // VPERMT2Q256rr 0U, // VPERMT2Q256rrk 0U, // VPERMT2Q256rrkz 4U, // VPERMT2Qrm 4U, // VPERMT2Qrmb 133U, // VPERMT2Qrmbk 8325U, // VPERMT2Qrmbkz 132U, // VPERMT2Qrmk 8324U, // VPERMT2Qrmkz 4U, // VPERMT2Qrr 0U, // VPERMT2Qrrk 0U, // VPERMT2Qrrkz 4U, // VPERMT2W128rm 132U, // VPERMT2W128rmk 8324U, // VPERMT2W128rmkz 4U, // VPERMT2W128rr 0U, // VPERMT2W128rrk 0U, // VPERMT2W128rrkz 4U, // VPERMT2W256rm 132U, // VPERMT2W256rmk 8324U, // VPERMT2W256rmkz 4U, // VPERMT2W256rr 0U, // VPERMT2W256rrk 0U, // VPERMT2W256rrkz 4U, // VPERMT2Wrm 132U, // VPERMT2Wrmk 8324U, // VPERMT2Wrmkz 4U, // VPERMT2Wrr 0U, // VPERMT2Wrrk 0U, // VPERMT2Wrrkz 4U, // VPERMWZ128rm 132U, // VPERMWZ128rmk 9348U, // VPERMWZ128rmkz 4U, // VPERMWZ128rr 0U, // VPERMWZ128rrk 9348U, // VPERMWZ128rrkz 4U, // VPERMWZ256rm 132U, // VPERMWZ256rmk 9348U, // VPERMWZ256rmkz 4U, // VPERMWZ256rr 0U, // VPERMWZ256rrk 9348U, // VPERMWZ256rrkz 4U, // VPERMWZrm 132U, // VPERMWZrmk 9348U, // VPERMWZrmkz 4U, // VPERMWZrr 0U, // VPERMWZrrk 9348U, // VPERMWZrrkz 0U, // VPEXPANDBZ128rm 405U, // VPEXPANDBZ128rmk 461U, // VPEXPANDBZ128rmkz 0U, // VPEXPANDBZ128rr 405U, // VPEXPANDBZ128rrk 461U, // VPEXPANDBZ128rrkz 0U, // VPEXPANDBZ256rm 405U, // VPEXPANDBZ256rmk 461U, // VPEXPANDBZ256rmkz 0U, // VPEXPANDBZ256rr 405U, // VPEXPANDBZ256rrk 461U, // VPEXPANDBZ256rrkz 0U, // VPEXPANDBZrm 405U, // VPEXPANDBZrmk 461U, // VPEXPANDBZrmkz 0U, // VPEXPANDBZrr 405U, // VPEXPANDBZrrk 461U, // VPEXPANDBZrrkz 0U, // VPEXPANDDZ128rm 405U, // VPEXPANDDZ128rmk 461U, // VPEXPANDDZ128rmkz 0U, // VPEXPANDDZ128rr 405U, // VPEXPANDDZ128rrk 461U, // VPEXPANDDZ128rrkz 0U, // VPEXPANDDZ256rm 405U, // VPEXPANDDZ256rmk 461U, // VPEXPANDDZ256rmkz 0U, // VPEXPANDDZ256rr 405U, // VPEXPANDDZ256rrk 461U, // VPEXPANDDZ256rrkz 0U, // VPEXPANDDZrm 405U, // VPEXPANDDZrmk 461U, // VPEXPANDDZrmkz 0U, // VPEXPANDDZrr 405U, // VPEXPANDDZrrk 461U, // VPEXPANDDZrrkz 0U, // VPEXPANDQZ128rm 405U, // VPEXPANDQZ128rmk 461U, // VPEXPANDQZ128rmkz 0U, // VPEXPANDQZ128rr 405U, // VPEXPANDQZ128rrk 461U, // VPEXPANDQZ128rrkz 0U, // VPEXPANDQZ256rm 405U, // VPEXPANDQZ256rmk 461U, // VPEXPANDQZ256rmkz 0U, // VPEXPANDQZ256rr 405U, // VPEXPANDQZ256rrk 461U, // VPEXPANDQZ256rrkz 0U, // VPEXPANDQZrm 405U, // VPEXPANDQZrmk 461U, // VPEXPANDQZrmkz 0U, // VPEXPANDQZrr 405U, // VPEXPANDQZrrk 461U, // VPEXPANDQZrrkz 0U, // VPEXPANDWZ128rm 405U, // VPEXPANDWZ128rmk 461U, // VPEXPANDWZ128rmkz 0U, // VPEXPANDWZ128rr 405U, // VPEXPANDWZ128rrk 461U, // VPEXPANDWZ128rrkz 0U, // VPEXPANDWZ256rm 405U, // VPEXPANDWZ256rmk 461U, // VPEXPANDWZ256rmkz 0U, // VPEXPANDWZ256rr 405U, // VPEXPANDWZ256rrk 461U, // VPEXPANDWZ256rrkz 0U, // VPEXPANDWZrm 405U, // VPEXPANDWZrmk 461U, // VPEXPANDWZrmkz 0U, // VPEXPANDWZrr 405U, // VPEXPANDWZrrk 461U, // VPEXPANDWZrrkz 1U, // VPEXTRBZmr 72U, // VPEXTRBZrr 1U, // VPEXTRBmr 72U, // VPEXTRBrr 1U, // VPEXTRDZmr 72U, // VPEXTRDZrr 1U, // VPEXTRDmr 72U, // VPEXTRDrr 1U, // VPEXTRQZmr 72U, // VPEXTRQZrr 1U, // VPEXTRQmr 72U, // VPEXTRQrr 1U, // VPEXTRWZmr 72U, // VPEXTRWZrr 72U, // VPEXTRWZrr_REV 1U, // VPEXTRWmr 72U, // VPEXTRWrr 72U, // VPEXTRWrr_REV 0U, // VPGATHERDDYrm 401U, // VPGATHERDDZ128rm 401U, // VPGATHERDDZ256rm 401U, // VPGATHERDDZrm 0U, // VPGATHERDDrm 0U, // VPGATHERDQYrm 401U, // VPGATHERDQZ128rm 401U, // VPGATHERDQZ256rm 401U, // VPGATHERDQZrm 0U, // VPGATHERDQrm 0U, // VPGATHERQDYrm 604U, // VPGATHERQDZ128rm 401U, // VPGATHERQDZ256rm 401U, // VPGATHERQDZrm 4U, // VPGATHERQDrm 0U, // VPGATHERQQYrm 401U, // VPGATHERQQZ128rm 401U, // VPGATHERQQZ256rm 401U, // VPGATHERQQZrm 0U, // VPGATHERQQrm 0U, // VPHADDBDrm 0U, // VPHADDBDrr 0U, // VPHADDBQrm 0U, // VPHADDBQrr 0U, // VPHADDBWrm 0U, // VPHADDBWrr 0U, // VPHADDDQrm 0U, // VPHADDDQrr 4U, // VPHADDDYrm 4U, // VPHADDDYrr 4U, // VPHADDDrm 4U, // VPHADDDrr 4U, // VPHADDSWYrm 4U, // VPHADDSWYrr 4U, // VPHADDSWrm 4U, // VPHADDSWrr 0U, // VPHADDUBDrm 0U, // VPHADDUBDrr 0U, // VPHADDUBQrm 0U, // VPHADDUBQrr 0U, // VPHADDUBWrm 0U, // VPHADDUBWrr 0U, // VPHADDUDQrm 0U, // VPHADDUDQrr 0U, // VPHADDUWDrm 0U, // VPHADDUWDrr 0U, // VPHADDUWQrm 0U, // VPHADDUWQrr 0U, // VPHADDWDrm 0U, // VPHADDWDrr 0U, // VPHADDWQrm 0U, // VPHADDWQrr 4U, // VPHADDWYrm 4U, // VPHADDWYrr 4U, // VPHADDWrm 4U, // VPHADDWrr 0U, // VPHMINPOSUWrm 0U, // VPHMINPOSUWrr 0U, // VPHSUBBWrm 0U, // VPHSUBBWrr 0U, // VPHSUBDQrm 0U, // VPHSUBDQrr 4U, // VPHSUBDYrm 4U, // VPHSUBDYrr 4U, // VPHSUBDrm 4U, // VPHSUBDrr 4U, // VPHSUBSWYrm 4U, // VPHSUBSWYrr 4U, // VPHSUBSWrm 4U, // VPHSUBSWrr 0U, // VPHSUBWDrm 0U, // VPHSUBWDrr 4U, // VPHSUBWYrm 4U, // VPHSUBWYrr 4U, // VPHSUBWrm 4U, // VPHSUBWrr 18636U, // VPINSRBZrm 18636U, // VPINSRBZrr 18636U, // VPINSRBrm 18636U, // VPINSRBrr 18636U, // VPINSRDZrm 18636U, // VPINSRDZrr 18636U, // VPINSRDrm 18636U, // VPINSRDrr 18636U, // VPINSRQZrm 18636U, // VPINSRQZrr 18636U, // VPINSRQrm 18636U, // VPINSRQrr 72U, // VPINSRWZrm 18636U, // VPINSRWZrr 72U, // VPINSRWrm 18636U, // VPINSRWrr 0U, // VPLZCNTDZ128rm 0U, // VPLZCNTDZ128rmb 3356U, // VPLZCNTDZ128rmbk 4444U, // VPLZCNTDZ128rmbkz 405U, // VPLZCNTDZ128rmk 461U, // VPLZCNTDZ128rmkz 0U, // VPLZCNTDZ128rr 405U, // VPLZCNTDZ128rrk 461U, // VPLZCNTDZ128rrkz 0U, // VPLZCNTDZ256rm 0U, // VPLZCNTDZ256rmb 3356U, // VPLZCNTDZ256rmbk 4444U, // VPLZCNTDZ256rmbkz 405U, // VPLZCNTDZ256rmk 461U, // VPLZCNTDZ256rmkz 0U, // VPLZCNTDZ256rr 405U, // VPLZCNTDZ256rrk 461U, // VPLZCNTDZ256rrkz 0U, // VPLZCNTDZrm 0U, // VPLZCNTDZrmb 3356U, // VPLZCNTDZrmbk 4444U, // VPLZCNTDZrmbkz 405U, // VPLZCNTDZrmk 461U, // VPLZCNTDZrmkz 0U, // VPLZCNTDZrr 405U, // VPLZCNTDZrrk 461U, // VPLZCNTDZrrkz 0U, // VPLZCNTQZ128rm 0U, // VPLZCNTQZ128rmb 3356U, // VPLZCNTQZ128rmbk 4444U, // VPLZCNTQZ128rmbkz 405U, // VPLZCNTQZ128rmk 461U, // VPLZCNTQZ128rmkz 0U, // VPLZCNTQZ128rr 405U, // VPLZCNTQZ128rrk 461U, // VPLZCNTQZ128rrkz 0U, // VPLZCNTQZ256rm 0U, // VPLZCNTQZ256rmb 3356U, // VPLZCNTQZ256rmbk 4444U, // VPLZCNTQZ256rmbkz 405U, // VPLZCNTQZ256rmk 461U, // VPLZCNTQZ256rmkz 0U, // VPLZCNTQZ256rr 405U, // VPLZCNTQZ256rrk 461U, // VPLZCNTQZ256rrkz 0U, // VPLZCNTQZrm 0U, // VPLZCNTQZrmb 3356U, // VPLZCNTQZrmbk 4444U, // VPLZCNTQZrmbkz 405U, // VPLZCNTQZrmk 461U, // VPLZCNTQZrmkz 0U, // VPLZCNTQZrr 405U, // VPLZCNTQZrrk 461U, // VPLZCNTQZrrkz 72U, // VPMACSDDrm 18636U, // VPMACSDDrr 72U, // VPMACSDQHrm 18636U, // VPMACSDQHrr 72U, // VPMACSDQLrm 18636U, // VPMACSDQLrr 72U, // VPMACSSDDrm 18636U, // VPMACSSDDrr 72U, // VPMACSSDQHrm 18636U, // VPMACSSDQHrr 72U, // VPMACSSDQLrm 18636U, // VPMACSSDQLrr 72U, // VPMACSSWDrm 18636U, // VPMACSSWDrr 72U, // VPMACSSWWrm 18636U, // VPMACSSWWrr 72U, // VPMACSWDrm 18636U, // VPMACSWDrr 72U, // VPMACSWWrm 18636U, // VPMACSWWrr 72U, // VPMADCSSWDrm 18636U, // VPMADCSSWDrr 72U, // VPMADCSWDrm 18636U, // VPMADCSWDrr 4U, // VPMADD52HUQZ128m 4U, // VPMADD52HUQZ128mb 133U, // VPMADD52HUQZ128mbk 8325U, // VPMADD52HUQZ128mbkz 132U, // VPMADD52HUQZ128mk 8324U, // VPMADD52HUQZ128mkz 4U, // VPMADD52HUQZ128r 0U, // VPMADD52HUQZ128rk 0U, // VPMADD52HUQZ128rkz 4U, // VPMADD52HUQZ256m 4U, // VPMADD52HUQZ256mb 133U, // VPMADD52HUQZ256mbk 8325U, // VPMADD52HUQZ256mbkz 132U, // VPMADD52HUQZ256mk 8324U, // VPMADD52HUQZ256mkz 4U, // VPMADD52HUQZ256r 0U, // VPMADD52HUQZ256rk 0U, // VPMADD52HUQZ256rkz 4U, // VPMADD52HUQZm 4U, // VPMADD52HUQZmb 133U, // VPMADD52HUQZmbk 8325U, // VPMADD52HUQZmbkz 132U, // VPMADD52HUQZmk 8324U, // VPMADD52HUQZmkz 4U, // VPMADD52HUQZr 0U, // VPMADD52HUQZrk 0U, // VPMADD52HUQZrkz 4U, // VPMADD52LUQZ128m 4U, // VPMADD52LUQZ128mb 133U, // VPMADD52LUQZ128mbk 8325U, // VPMADD52LUQZ128mbkz 132U, // VPMADD52LUQZ128mk 8324U, // VPMADD52LUQZ128mkz 4U, // VPMADD52LUQZ128r 0U, // VPMADD52LUQZ128rk 0U, // VPMADD52LUQZ128rkz 4U, // VPMADD52LUQZ256m 4U, // VPMADD52LUQZ256mb 133U, // VPMADD52LUQZ256mbk 8325U, // VPMADD52LUQZ256mbkz 132U, // VPMADD52LUQZ256mk 8324U, // VPMADD52LUQZ256mkz 4U, // VPMADD52LUQZ256r 0U, // VPMADD52LUQZ256rk 0U, // VPMADD52LUQZ256rkz 4U, // VPMADD52LUQZm 4U, // VPMADD52LUQZmb 133U, // VPMADD52LUQZmbk 8325U, // VPMADD52LUQZmbkz 132U, // VPMADD52LUQZmk 8324U, // VPMADD52LUQZmkz 4U, // VPMADD52LUQZr 0U, // VPMADD52LUQZrk 0U, // VPMADD52LUQZrkz 4U, // VPMADDUBSWYrm 4U, // VPMADDUBSWYrr 4U, // VPMADDUBSWZ128rm 132U, // VPMADDUBSWZ128rmk 9348U, // VPMADDUBSWZ128rmkz 4U, // VPMADDUBSWZ128rr 0U, // VPMADDUBSWZ128rrk 9348U, // VPMADDUBSWZ128rrkz 4U, // VPMADDUBSWZ256rm 132U, // VPMADDUBSWZ256rmk 9348U, // VPMADDUBSWZ256rmkz 4U, // VPMADDUBSWZ256rr 0U, // VPMADDUBSWZ256rrk 9348U, // VPMADDUBSWZ256rrkz 4U, // VPMADDUBSWZrm 132U, // VPMADDUBSWZrmk 9348U, // VPMADDUBSWZrmkz 4U, // VPMADDUBSWZrr 0U, // VPMADDUBSWZrrk 9348U, // VPMADDUBSWZrrkz 4U, // VPMADDUBSWrm 4U, // VPMADDUBSWrr 4U, // VPMADDWDYrm 4U, // VPMADDWDYrr 4U, // VPMADDWDZ128rm 132U, // VPMADDWDZ128rmk 9348U, // VPMADDWDZ128rmkz 4U, // VPMADDWDZ128rr 0U, // VPMADDWDZ128rrk 9348U, // VPMADDWDZ128rrkz 4U, // VPMADDWDZ256rm 132U, // VPMADDWDZ256rmk 9348U, // VPMADDWDZ256rmkz 4U, // VPMADDWDZ256rr 0U, // VPMADDWDZ256rrk 9348U, // VPMADDWDZ256rrkz 4U, // VPMADDWDZrm 132U, // VPMADDWDZrmk 9348U, // VPMADDWDZrmkz 4U, // VPMADDWDZrr 0U, // VPMADDWDZrrk 9348U, // VPMADDWDZrrkz 4U, // VPMADDWDrm 4U, // VPMADDWDrr 2U, // VPMASKMOVDYmr 4U, // VPMASKMOVDYrm 2U, // VPMASKMOVDmr 4U, // VPMASKMOVDrm 2U, // VPMASKMOVQYmr 4U, // VPMASKMOVQYrm 2U, // VPMASKMOVQmr 4U, // VPMASKMOVQrm 4U, // VPMAXSBYrm 4U, // VPMAXSBYrr 4U, // VPMAXSBZ128rm 132U, // VPMAXSBZ128rmk 9348U, // VPMAXSBZ128rmkz 4U, // VPMAXSBZ128rr 0U, // VPMAXSBZ128rrk 9348U, // VPMAXSBZ128rrkz 4U, // VPMAXSBZ256rm 132U, // VPMAXSBZ256rmk 9348U, // VPMAXSBZ256rmkz 4U, // VPMAXSBZ256rr 0U, // VPMAXSBZ256rrk 9348U, // VPMAXSBZ256rrkz 4U, // VPMAXSBZrm 132U, // VPMAXSBZrmk 9348U, // VPMAXSBZrmkz 4U, // VPMAXSBZrr 0U, // VPMAXSBZrrk 9348U, // VPMAXSBZrrkz 4U, // VPMAXSBrm 4U, // VPMAXSBrr 4U, // VPMAXSDYrm 4U, // VPMAXSDYrr 4U, // VPMAXSDZ128rm 72U, // VPMAXSDZ128rmb 133U, // VPMAXSDZ128rmbk 9348U, // VPMAXSDZ128rmbkz 132U, // VPMAXSDZ128rmk 9348U, // VPMAXSDZ128rmkz 4U, // VPMAXSDZ128rr 0U, // VPMAXSDZ128rrk 9348U, // VPMAXSDZ128rrkz 4U, // VPMAXSDZ256rm 72U, // VPMAXSDZ256rmb 133U, // VPMAXSDZ256rmbk 9348U, // VPMAXSDZ256rmbkz 132U, // VPMAXSDZ256rmk 9348U, // VPMAXSDZ256rmkz 4U, // VPMAXSDZ256rr 0U, // VPMAXSDZ256rrk 9348U, // VPMAXSDZ256rrkz 4U, // VPMAXSDZrm 72U, // VPMAXSDZrmb 133U, // VPMAXSDZrmbk 9348U, // VPMAXSDZrmbkz 132U, // VPMAXSDZrmk 9348U, // VPMAXSDZrmkz 4U, // VPMAXSDZrr 0U, // VPMAXSDZrrk 9348U, // VPMAXSDZrrkz 4U, // VPMAXSDrm 4U, // VPMAXSDrr 4U, // VPMAXSQZ128rm 72U, // VPMAXSQZ128rmb 133U, // VPMAXSQZ128rmbk 9348U, // VPMAXSQZ128rmbkz 132U, // VPMAXSQZ128rmk 9348U, // VPMAXSQZ128rmkz 4U, // VPMAXSQZ128rr 0U, // VPMAXSQZ128rrk 9348U, // VPMAXSQZ128rrkz 4U, // VPMAXSQZ256rm 72U, // VPMAXSQZ256rmb 133U, // VPMAXSQZ256rmbk 9348U, // VPMAXSQZ256rmbkz 132U, // VPMAXSQZ256rmk 9348U, // VPMAXSQZ256rmkz 4U, // VPMAXSQZ256rr 0U, // VPMAXSQZ256rrk 9348U, // VPMAXSQZ256rrkz 4U, // VPMAXSQZrm 72U, // VPMAXSQZrmb 133U, // VPMAXSQZrmbk 9348U, // VPMAXSQZrmbkz 132U, // VPMAXSQZrmk 9348U, // VPMAXSQZrmkz 4U, // VPMAXSQZrr 0U, // VPMAXSQZrrk 9348U, // VPMAXSQZrrkz 4U, // VPMAXSWYrm 4U, // VPMAXSWYrr 4U, // VPMAXSWZ128rm 132U, // VPMAXSWZ128rmk 9348U, // VPMAXSWZ128rmkz 4U, // VPMAXSWZ128rr 0U, // VPMAXSWZ128rrk 9348U, // VPMAXSWZ128rrkz 4U, // VPMAXSWZ256rm 132U, // VPMAXSWZ256rmk 9348U, // VPMAXSWZ256rmkz 4U, // VPMAXSWZ256rr 0U, // VPMAXSWZ256rrk 9348U, // VPMAXSWZ256rrkz 4U, // VPMAXSWZrm 132U, // VPMAXSWZrmk 9348U, // VPMAXSWZrmkz 4U, // VPMAXSWZrr 0U, // VPMAXSWZrrk 9348U, // VPMAXSWZrrkz 4U, // VPMAXSWrm 4U, // VPMAXSWrr 4U, // VPMAXUBYrm 4U, // VPMAXUBYrr 4U, // VPMAXUBZ128rm 132U, // VPMAXUBZ128rmk 9348U, // VPMAXUBZ128rmkz 4U, // VPMAXUBZ128rr 0U, // VPMAXUBZ128rrk 9348U, // VPMAXUBZ128rrkz 4U, // VPMAXUBZ256rm 132U, // VPMAXUBZ256rmk 9348U, // VPMAXUBZ256rmkz 4U, // VPMAXUBZ256rr 0U, // VPMAXUBZ256rrk 9348U, // VPMAXUBZ256rrkz 4U, // VPMAXUBZrm 132U, // VPMAXUBZrmk 9348U, // VPMAXUBZrmkz 4U, // VPMAXUBZrr 0U, // VPMAXUBZrrk 9348U, // VPMAXUBZrrkz 4U, // VPMAXUBrm 4U, // VPMAXUBrr 4U, // VPMAXUDYrm 4U, // VPMAXUDYrr 4U, // VPMAXUDZ128rm 72U, // VPMAXUDZ128rmb 133U, // VPMAXUDZ128rmbk 9348U, // VPMAXUDZ128rmbkz 132U, // VPMAXUDZ128rmk 9348U, // VPMAXUDZ128rmkz 4U, // VPMAXUDZ128rr 0U, // VPMAXUDZ128rrk 9348U, // VPMAXUDZ128rrkz 4U, // VPMAXUDZ256rm 72U, // VPMAXUDZ256rmb 133U, // VPMAXUDZ256rmbk 9348U, // VPMAXUDZ256rmbkz 132U, // VPMAXUDZ256rmk 9348U, // VPMAXUDZ256rmkz 4U, // VPMAXUDZ256rr 0U, // VPMAXUDZ256rrk 9348U, // VPMAXUDZ256rrkz 4U, // VPMAXUDZrm 72U, // VPMAXUDZrmb 133U, // VPMAXUDZrmbk 9348U, // VPMAXUDZrmbkz 132U, // VPMAXUDZrmk 9348U, // VPMAXUDZrmkz 4U, // VPMAXUDZrr 0U, // VPMAXUDZrrk 9348U, // VPMAXUDZrrkz 4U, // VPMAXUDrm 4U, // VPMAXUDrr 4U, // VPMAXUQZ128rm 72U, // VPMAXUQZ128rmb 133U, // VPMAXUQZ128rmbk 9348U, // VPMAXUQZ128rmbkz 132U, // VPMAXUQZ128rmk 9348U, // VPMAXUQZ128rmkz 4U, // VPMAXUQZ128rr 0U, // VPMAXUQZ128rrk 9348U, // VPMAXUQZ128rrkz 4U, // VPMAXUQZ256rm 72U, // VPMAXUQZ256rmb 133U, // VPMAXUQZ256rmbk 9348U, // VPMAXUQZ256rmbkz 132U, // VPMAXUQZ256rmk 9348U, // VPMAXUQZ256rmkz 4U, // VPMAXUQZ256rr 0U, // VPMAXUQZ256rrk 9348U, // VPMAXUQZ256rrkz 4U, // VPMAXUQZrm 72U, // VPMAXUQZrmb 133U, // VPMAXUQZrmbk 9348U, // VPMAXUQZrmbkz 132U, // VPMAXUQZrmk 9348U, // VPMAXUQZrmkz 4U, // VPMAXUQZrr 0U, // VPMAXUQZrrk 9348U, // VPMAXUQZrrkz 4U, // VPMAXUWYrm 4U, // VPMAXUWYrr 4U, // VPMAXUWZ128rm 132U, // VPMAXUWZ128rmk 9348U, // VPMAXUWZ128rmkz 4U, // VPMAXUWZ128rr 0U, // VPMAXUWZ128rrk 9348U, // VPMAXUWZ128rrkz 4U, // VPMAXUWZ256rm 132U, // VPMAXUWZ256rmk 9348U, // VPMAXUWZ256rmkz 4U, // VPMAXUWZ256rr 0U, // VPMAXUWZ256rrk 9348U, // VPMAXUWZ256rrkz 4U, // VPMAXUWZrm 132U, // VPMAXUWZrmk 9348U, // VPMAXUWZrmkz 4U, // VPMAXUWZrr 0U, // VPMAXUWZrrk 9348U, // VPMAXUWZrrkz 4U, // VPMAXUWrm 4U, // VPMAXUWrr 4U, // VPMINSBYrm 4U, // VPMINSBYrr 4U, // VPMINSBZ128rm 132U, // VPMINSBZ128rmk 9348U, // VPMINSBZ128rmkz 4U, // VPMINSBZ128rr 0U, // VPMINSBZ128rrk 9348U, // VPMINSBZ128rrkz 4U, // VPMINSBZ256rm 132U, // VPMINSBZ256rmk 9348U, // VPMINSBZ256rmkz 4U, // VPMINSBZ256rr 0U, // VPMINSBZ256rrk 9348U, // VPMINSBZ256rrkz 4U, // VPMINSBZrm 132U, // VPMINSBZrmk 9348U, // VPMINSBZrmkz 4U, // VPMINSBZrr 0U, // VPMINSBZrrk 9348U, // VPMINSBZrrkz 4U, // VPMINSBrm 4U, // VPMINSBrr 4U, // VPMINSDYrm 4U, // VPMINSDYrr 4U, // VPMINSDZ128rm 72U, // VPMINSDZ128rmb 133U, // VPMINSDZ128rmbk 9348U, // VPMINSDZ128rmbkz 132U, // VPMINSDZ128rmk 9348U, // VPMINSDZ128rmkz 4U, // VPMINSDZ128rr 0U, // VPMINSDZ128rrk 9348U, // VPMINSDZ128rrkz 4U, // VPMINSDZ256rm 72U, // VPMINSDZ256rmb 133U, // VPMINSDZ256rmbk 9348U, // VPMINSDZ256rmbkz 132U, // VPMINSDZ256rmk 9348U, // VPMINSDZ256rmkz 4U, // VPMINSDZ256rr 0U, // VPMINSDZ256rrk 9348U, // VPMINSDZ256rrkz 4U, // VPMINSDZrm 72U, // VPMINSDZrmb 133U, // VPMINSDZrmbk 9348U, // VPMINSDZrmbkz 132U, // VPMINSDZrmk 9348U, // VPMINSDZrmkz 4U, // VPMINSDZrr 0U, // VPMINSDZrrk 9348U, // VPMINSDZrrkz 4U, // VPMINSDrm 4U, // VPMINSDrr 4U, // VPMINSQZ128rm 72U, // VPMINSQZ128rmb 133U, // VPMINSQZ128rmbk 9348U, // VPMINSQZ128rmbkz 132U, // VPMINSQZ128rmk 9348U, // VPMINSQZ128rmkz 4U, // VPMINSQZ128rr 0U, // VPMINSQZ128rrk 9348U, // VPMINSQZ128rrkz 4U, // VPMINSQZ256rm 72U, // VPMINSQZ256rmb 133U, // VPMINSQZ256rmbk 9348U, // VPMINSQZ256rmbkz 132U, // VPMINSQZ256rmk 9348U, // VPMINSQZ256rmkz 4U, // VPMINSQZ256rr 0U, // VPMINSQZ256rrk 9348U, // VPMINSQZ256rrkz 4U, // VPMINSQZrm 72U, // VPMINSQZrmb 133U, // VPMINSQZrmbk 9348U, // VPMINSQZrmbkz 132U, // VPMINSQZrmk 9348U, // VPMINSQZrmkz 4U, // VPMINSQZrr 0U, // VPMINSQZrrk 9348U, // VPMINSQZrrkz 4U, // VPMINSWYrm 4U, // VPMINSWYrr 4U, // VPMINSWZ128rm 132U, // VPMINSWZ128rmk 9348U, // VPMINSWZ128rmkz 4U, // VPMINSWZ128rr 0U, // VPMINSWZ128rrk 9348U, // VPMINSWZ128rrkz 4U, // VPMINSWZ256rm 132U, // VPMINSWZ256rmk 9348U, // VPMINSWZ256rmkz 4U, // VPMINSWZ256rr 0U, // VPMINSWZ256rrk 9348U, // VPMINSWZ256rrkz 4U, // VPMINSWZrm 132U, // VPMINSWZrmk 9348U, // VPMINSWZrmkz 4U, // VPMINSWZrr 0U, // VPMINSWZrrk 9348U, // VPMINSWZrrkz 4U, // VPMINSWrm 4U, // VPMINSWrr 4U, // VPMINUBYrm 4U, // VPMINUBYrr 4U, // VPMINUBZ128rm 132U, // VPMINUBZ128rmk 9348U, // VPMINUBZ128rmkz 4U, // VPMINUBZ128rr 0U, // VPMINUBZ128rrk 9348U, // VPMINUBZ128rrkz 4U, // VPMINUBZ256rm 132U, // VPMINUBZ256rmk 9348U, // VPMINUBZ256rmkz 4U, // VPMINUBZ256rr 0U, // VPMINUBZ256rrk 9348U, // VPMINUBZ256rrkz 4U, // VPMINUBZrm 132U, // VPMINUBZrmk 9348U, // VPMINUBZrmkz 4U, // VPMINUBZrr 0U, // VPMINUBZrrk 9348U, // VPMINUBZrrkz 4U, // VPMINUBrm 4U, // VPMINUBrr 4U, // VPMINUDYrm 4U, // VPMINUDYrr 4U, // VPMINUDZ128rm 72U, // VPMINUDZ128rmb 133U, // VPMINUDZ128rmbk 9348U, // VPMINUDZ128rmbkz 132U, // VPMINUDZ128rmk 9348U, // VPMINUDZ128rmkz 4U, // VPMINUDZ128rr 0U, // VPMINUDZ128rrk 9348U, // VPMINUDZ128rrkz 4U, // VPMINUDZ256rm 72U, // VPMINUDZ256rmb 133U, // VPMINUDZ256rmbk 9348U, // VPMINUDZ256rmbkz 132U, // VPMINUDZ256rmk 9348U, // VPMINUDZ256rmkz 4U, // VPMINUDZ256rr 0U, // VPMINUDZ256rrk 9348U, // VPMINUDZ256rrkz 4U, // VPMINUDZrm 72U, // VPMINUDZrmb 133U, // VPMINUDZrmbk 9348U, // VPMINUDZrmbkz 132U, // VPMINUDZrmk 9348U, // VPMINUDZrmkz 4U, // VPMINUDZrr 0U, // VPMINUDZrrk 9348U, // VPMINUDZrrkz 4U, // VPMINUDrm 4U, // VPMINUDrr 4U, // VPMINUQZ128rm 72U, // VPMINUQZ128rmb 133U, // VPMINUQZ128rmbk 9348U, // VPMINUQZ128rmbkz 132U, // VPMINUQZ128rmk 9348U, // VPMINUQZ128rmkz 4U, // VPMINUQZ128rr 0U, // VPMINUQZ128rrk 9348U, // VPMINUQZ128rrkz 4U, // VPMINUQZ256rm 72U, // VPMINUQZ256rmb 133U, // VPMINUQZ256rmbk 9348U, // VPMINUQZ256rmbkz 132U, // VPMINUQZ256rmk 9348U, // VPMINUQZ256rmkz 4U, // VPMINUQZ256rr 0U, // VPMINUQZ256rrk 9348U, // VPMINUQZ256rrkz 4U, // VPMINUQZrm 72U, // VPMINUQZrmb 133U, // VPMINUQZrmbk 9348U, // VPMINUQZrmbkz 132U, // VPMINUQZrmk 9348U, // VPMINUQZrmkz 4U, // VPMINUQZrr 0U, // VPMINUQZrrk 9348U, // VPMINUQZrrkz 4U, // VPMINUWYrm 4U, // VPMINUWYrr 4U, // VPMINUWZ128rm 132U, // VPMINUWZ128rmk 9348U, // VPMINUWZ128rmkz 4U, // VPMINUWZ128rr 0U, // VPMINUWZ128rrk 9348U, // VPMINUWZ128rrkz 4U, // VPMINUWZ256rm 132U, // VPMINUWZ256rmk 9348U, // VPMINUWZ256rmkz 4U, // VPMINUWZ256rr 0U, // VPMINUWZ256rrk 9348U, // VPMINUWZ256rrkz 4U, // VPMINUWZrm 132U, // VPMINUWZrmk 9348U, // VPMINUWZrmkz 4U, // VPMINUWZrr 0U, // VPMINUWZrrk 9348U, // VPMINUWZrrkz 4U, // VPMINUWrm 4U, // VPMINUWrr 0U, // VPMOVB2MZ128rr 0U, // VPMOVB2MZ256rr 0U, // VPMOVB2MZrr 0U, // VPMOVD2MZ128rr 0U, // VPMOVD2MZ256rr 0U, // VPMOVD2MZrr 0U, // VPMOVDBZ128mr 49U, // VPMOVDBZ128mrk 0U, // VPMOVDBZ128rr 405U, // VPMOVDBZ128rrk 461U, // VPMOVDBZ128rrkz 0U, // VPMOVDBZ256mr 49U, // VPMOVDBZ256mrk 0U, // VPMOVDBZ256rr 405U, // VPMOVDBZ256rrk 461U, // VPMOVDBZ256rrkz 0U, // VPMOVDBZmr 49U, // VPMOVDBZmrk 0U, // VPMOVDBZrr 405U, // VPMOVDBZrrk 461U, // VPMOVDBZrrkz 0U, // VPMOVDWZ128mr 49U, // VPMOVDWZ128mrk 0U, // VPMOVDWZ128rr 405U, // VPMOVDWZ128rrk 461U, // VPMOVDWZ128rrkz 0U, // VPMOVDWZ256mr 49U, // VPMOVDWZ256mrk 0U, // VPMOVDWZ256rr 405U, // VPMOVDWZ256rrk 461U, // VPMOVDWZ256rrkz 0U, // VPMOVDWZmr 49U, // VPMOVDWZmrk 0U, // VPMOVDWZrr 405U, // VPMOVDWZrrk 461U, // VPMOVDWZrrkz 0U, // VPMOVM2BZ128rr 0U, // VPMOVM2BZ256rr 0U, // VPMOVM2BZrr 0U, // VPMOVM2DZ128rr 0U, // VPMOVM2DZ256rr 0U, // VPMOVM2DZrr 0U, // VPMOVM2QZ128rr 0U, // VPMOVM2QZ256rr 0U, // VPMOVM2QZrr 0U, // VPMOVM2WZ128rr 0U, // VPMOVM2WZ256rr 0U, // VPMOVM2WZrr 0U, // VPMOVMSKBYrr 0U, // VPMOVMSKBrr 0U, // VPMOVQ2MZ128rr 0U, // VPMOVQ2MZ256rr 0U, // VPMOVQ2MZrr 0U, // VPMOVQBZ128mr 49U, // VPMOVQBZ128mrk 0U, // VPMOVQBZ128rr 405U, // VPMOVQBZ128rrk 461U, // VPMOVQBZ128rrkz 0U, // VPMOVQBZ256mr 49U, // VPMOVQBZ256mrk 0U, // VPMOVQBZ256rr 405U, // VPMOVQBZ256rrk 461U, // VPMOVQBZ256rrkz 0U, // VPMOVQBZmr 49U, // VPMOVQBZmrk 0U, // VPMOVQBZrr 405U, // VPMOVQBZrrk 461U, // VPMOVQBZrrkz 0U, // VPMOVQDZ128mr 49U, // VPMOVQDZ128mrk 0U, // VPMOVQDZ128rr 405U, // VPMOVQDZ128rrk 461U, // VPMOVQDZ128rrkz 0U, // VPMOVQDZ256mr 49U, // VPMOVQDZ256mrk 0U, // VPMOVQDZ256rr 405U, // VPMOVQDZ256rrk 461U, // VPMOVQDZ256rrkz 0U, // VPMOVQDZmr 49U, // VPMOVQDZmrk 0U, // VPMOVQDZrr 405U, // VPMOVQDZrrk 461U, // VPMOVQDZrrkz 0U, // VPMOVQWZ128mr 49U, // VPMOVQWZ128mrk 0U, // VPMOVQWZ128rr 405U, // VPMOVQWZ128rrk 461U, // VPMOVQWZ128rrkz 0U, // VPMOVQWZ256mr 49U, // VPMOVQWZ256mrk 0U, // VPMOVQWZ256rr 405U, // VPMOVQWZ256rrk 461U, // VPMOVQWZ256rrkz 0U, // VPMOVQWZmr 49U, // VPMOVQWZmrk 0U, // VPMOVQWZrr 405U, // VPMOVQWZrrk 461U, // VPMOVQWZrrkz 0U, // VPMOVSDBZ128mr 49U, // VPMOVSDBZ128mrk 0U, // VPMOVSDBZ128rr 405U, // VPMOVSDBZ128rrk 461U, // VPMOVSDBZ128rrkz 0U, // VPMOVSDBZ256mr 49U, // VPMOVSDBZ256mrk 0U, // VPMOVSDBZ256rr 405U, // VPMOVSDBZ256rrk 461U, // VPMOVSDBZ256rrkz 0U, // VPMOVSDBZmr 49U, // VPMOVSDBZmrk 0U, // VPMOVSDBZrr 405U, // VPMOVSDBZrrk 461U, // VPMOVSDBZrrkz 0U, // VPMOVSDWZ128mr 49U, // VPMOVSDWZ128mrk 0U, // VPMOVSDWZ128rr 405U, // VPMOVSDWZ128rrk 461U, // VPMOVSDWZ128rrkz 0U, // VPMOVSDWZ256mr 49U, // VPMOVSDWZ256mrk 0U, // VPMOVSDWZ256rr 405U, // VPMOVSDWZ256rrk 461U, // VPMOVSDWZ256rrkz 0U, // VPMOVSDWZmr 49U, // VPMOVSDWZmrk 0U, // VPMOVSDWZrr 405U, // VPMOVSDWZrrk 461U, // VPMOVSDWZrrkz 0U, // VPMOVSQBZ128mr 49U, // VPMOVSQBZ128mrk 0U, // VPMOVSQBZ128rr 405U, // VPMOVSQBZ128rrk 461U, // VPMOVSQBZ128rrkz 0U, // VPMOVSQBZ256mr 49U, // VPMOVSQBZ256mrk 0U, // VPMOVSQBZ256rr 405U, // VPMOVSQBZ256rrk 461U, // VPMOVSQBZ256rrkz 0U, // VPMOVSQBZmr 49U, // VPMOVSQBZmrk 0U, // VPMOVSQBZrr 405U, // VPMOVSQBZrrk 461U, // VPMOVSQBZrrkz 0U, // VPMOVSQDZ128mr 49U, // VPMOVSQDZ128mrk 0U, // VPMOVSQDZ128rr 405U, // VPMOVSQDZ128rrk 461U, // VPMOVSQDZ128rrkz 0U, // VPMOVSQDZ256mr 49U, // VPMOVSQDZ256mrk 0U, // VPMOVSQDZ256rr 405U, // VPMOVSQDZ256rrk 461U, // VPMOVSQDZ256rrkz 0U, // VPMOVSQDZmr 49U, // VPMOVSQDZmrk 0U, // VPMOVSQDZrr 405U, // VPMOVSQDZrrk 461U, // VPMOVSQDZrrkz 0U, // VPMOVSQWZ128mr 49U, // VPMOVSQWZ128mrk 0U, // VPMOVSQWZ128rr 405U, // VPMOVSQWZ128rrk 461U, // VPMOVSQWZ128rrkz 0U, // VPMOVSQWZ256mr 49U, // VPMOVSQWZ256mrk 0U, // VPMOVSQWZ256rr 405U, // VPMOVSQWZ256rrk 461U, // VPMOVSQWZ256rrkz 0U, // VPMOVSQWZmr 49U, // VPMOVSQWZmrk 0U, // VPMOVSQWZrr 405U, // VPMOVSQWZrrk 461U, // VPMOVSQWZrrkz 0U, // VPMOVSWBZ128mr 49U, // VPMOVSWBZ128mrk 0U, // VPMOVSWBZ128rr 405U, // VPMOVSWBZ128rrk 461U, // VPMOVSWBZ128rrkz 0U, // VPMOVSWBZ256mr 49U, // VPMOVSWBZ256mrk 0U, // VPMOVSWBZ256rr 405U, // VPMOVSWBZ256rrk 461U, // VPMOVSWBZ256rrkz 0U, // VPMOVSWBZmr 49U, // VPMOVSWBZmrk 0U, // VPMOVSWBZrr 405U, // VPMOVSWBZrrk 461U, // VPMOVSWBZrrkz 0U, // VPMOVSXBDYrm 0U, // VPMOVSXBDYrr 0U, // VPMOVSXBDZ128rm 3356U, // VPMOVSXBDZ128rmk 4444U, // VPMOVSXBDZ128rmkz 0U, // VPMOVSXBDZ128rr 405U, // VPMOVSXBDZ128rrk 461U, // VPMOVSXBDZ128rrkz 0U, // VPMOVSXBDZ256rm 3356U, // VPMOVSXBDZ256rmk 4444U, // VPMOVSXBDZ256rmkz 0U, // VPMOVSXBDZ256rr 405U, // VPMOVSXBDZ256rrk 461U, // VPMOVSXBDZ256rrkz 0U, // VPMOVSXBDZrm 405U, // VPMOVSXBDZrmk 461U, // VPMOVSXBDZrmkz 0U, // VPMOVSXBDZrr 405U, // VPMOVSXBDZrrk 461U, // VPMOVSXBDZrrkz 0U, // VPMOVSXBDrm 0U, // VPMOVSXBDrr 0U, // VPMOVSXBQYrm 0U, // VPMOVSXBQYrr 0U, // VPMOVSXBQZ128rm 0U, // VPMOVSXBQZ128rmk 461U, // VPMOVSXBQZ128rmkz 0U, // VPMOVSXBQZ128rr 405U, // VPMOVSXBQZ128rrk 461U, // VPMOVSXBQZ128rrkz 0U, // VPMOVSXBQZ256rm 3356U, // VPMOVSXBQZ256rmk 4444U, // VPMOVSXBQZ256rmkz 0U, // VPMOVSXBQZ256rr 405U, // VPMOVSXBQZ256rrk 461U, // VPMOVSXBQZ256rrkz 0U, // VPMOVSXBQZrm 3356U, // VPMOVSXBQZrmk 4444U, // VPMOVSXBQZrmkz 0U, // VPMOVSXBQZrr 405U, // VPMOVSXBQZrrk 461U, // VPMOVSXBQZrrkz 0U, // VPMOVSXBQrm 0U, // VPMOVSXBQrr 0U, // VPMOVSXBWYrm 0U, // VPMOVSXBWYrr 0U, // VPMOVSXBWZ128rm 3356U, // VPMOVSXBWZ128rmk 4444U, // VPMOVSXBWZ128rmkz 0U, // VPMOVSXBWZ128rr 405U, // VPMOVSXBWZ128rrk 461U, // VPMOVSXBWZ128rrkz 0U, // VPMOVSXBWZ256rm 405U, // VPMOVSXBWZ256rmk 461U, // VPMOVSXBWZ256rmkz 0U, // VPMOVSXBWZ256rr 405U, // VPMOVSXBWZ256rrk 461U, // VPMOVSXBWZ256rrkz 0U, // VPMOVSXBWZrm 405U, // VPMOVSXBWZrmk 461U, // VPMOVSXBWZrmkz 0U, // VPMOVSXBWZrr 405U, // VPMOVSXBWZrrk 461U, // VPMOVSXBWZrrkz 0U, // VPMOVSXBWrm 0U, // VPMOVSXBWrr 0U, // VPMOVSXDQYrm 0U, // VPMOVSXDQYrr 0U, // VPMOVSXDQZ128rm 3356U, // VPMOVSXDQZ128rmk 4444U, // VPMOVSXDQZ128rmkz 0U, // VPMOVSXDQZ128rr 405U, // VPMOVSXDQZ128rrk 461U, // VPMOVSXDQZ128rrkz 0U, // VPMOVSXDQZ256rm 405U, // VPMOVSXDQZ256rmk 461U, // VPMOVSXDQZ256rmkz 0U, // VPMOVSXDQZ256rr 405U, // VPMOVSXDQZ256rrk 461U, // VPMOVSXDQZ256rrkz 0U, // VPMOVSXDQZrm 405U, // VPMOVSXDQZrmk 461U, // VPMOVSXDQZrmkz 0U, // VPMOVSXDQZrr 405U, // VPMOVSXDQZrrk 461U, // VPMOVSXDQZrrkz 0U, // VPMOVSXDQrm 0U, // VPMOVSXDQrr 0U, // VPMOVSXWDYrm 0U, // VPMOVSXWDYrr 0U, // VPMOVSXWDZ128rm 3356U, // VPMOVSXWDZ128rmk 4444U, // VPMOVSXWDZ128rmkz 0U, // VPMOVSXWDZ128rr 405U, // VPMOVSXWDZ128rrk 461U, // VPMOVSXWDZ128rrkz 0U, // VPMOVSXWDZ256rm 405U, // VPMOVSXWDZ256rmk 461U, // VPMOVSXWDZ256rmkz 0U, // VPMOVSXWDZ256rr 405U, // VPMOVSXWDZ256rrk 461U, // VPMOVSXWDZ256rrkz 0U, // VPMOVSXWDZrm 405U, // VPMOVSXWDZrmk 461U, // VPMOVSXWDZrmkz 0U, // VPMOVSXWDZrr 405U, // VPMOVSXWDZrrk 461U, // VPMOVSXWDZrrkz 0U, // VPMOVSXWDrm 0U, // VPMOVSXWDrr 0U, // VPMOVSXWQYrm 0U, // VPMOVSXWQYrr 0U, // VPMOVSXWQZ128rm 3356U, // VPMOVSXWQZ128rmk 4444U, // VPMOVSXWQZ128rmkz 0U, // VPMOVSXWQZ128rr 405U, // VPMOVSXWQZ128rrk 461U, // VPMOVSXWQZ128rrkz 0U, // VPMOVSXWQZ256rm 3356U, // VPMOVSXWQZ256rmk 4444U, // VPMOVSXWQZ256rmkz 0U, // VPMOVSXWQZ256rr 405U, // VPMOVSXWQZ256rrk 461U, // VPMOVSXWQZ256rrkz 0U, // VPMOVSXWQZrm 405U, // VPMOVSXWQZrmk 461U, // VPMOVSXWQZrmkz 0U, // VPMOVSXWQZrr 405U, // VPMOVSXWQZrrk 461U, // VPMOVSXWQZrrkz 0U, // VPMOVSXWQrm 0U, // VPMOVSXWQrr 0U, // VPMOVUSDBZ128mr 49U, // VPMOVUSDBZ128mrk 0U, // VPMOVUSDBZ128rr 405U, // VPMOVUSDBZ128rrk 461U, // VPMOVUSDBZ128rrkz 0U, // VPMOVUSDBZ256mr 49U, // VPMOVUSDBZ256mrk 0U, // VPMOVUSDBZ256rr 405U, // VPMOVUSDBZ256rrk 461U, // VPMOVUSDBZ256rrkz 0U, // VPMOVUSDBZmr 49U, // VPMOVUSDBZmrk 0U, // VPMOVUSDBZrr 405U, // VPMOVUSDBZrrk 461U, // VPMOVUSDBZrrkz 0U, // VPMOVUSDWZ128mr 49U, // VPMOVUSDWZ128mrk 0U, // VPMOVUSDWZ128rr 405U, // VPMOVUSDWZ128rrk 461U, // VPMOVUSDWZ128rrkz 0U, // VPMOVUSDWZ256mr 49U, // VPMOVUSDWZ256mrk 0U, // VPMOVUSDWZ256rr 405U, // VPMOVUSDWZ256rrk 461U, // VPMOVUSDWZ256rrkz 0U, // VPMOVUSDWZmr 49U, // VPMOVUSDWZmrk 0U, // VPMOVUSDWZrr 405U, // VPMOVUSDWZrrk 461U, // VPMOVUSDWZrrkz 0U, // VPMOVUSQBZ128mr 49U, // VPMOVUSQBZ128mrk 0U, // VPMOVUSQBZ128rr 405U, // VPMOVUSQBZ128rrk 461U, // VPMOVUSQBZ128rrkz 0U, // VPMOVUSQBZ256mr 49U, // VPMOVUSQBZ256mrk 0U, // VPMOVUSQBZ256rr 405U, // VPMOVUSQBZ256rrk 461U, // VPMOVUSQBZ256rrkz 0U, // VPMOVUSQBZmr 49U, // VPMOVUSQBZmrk 0U, // VPMOVUSQBZrr 405U, // VPMOVUSQBZrrk 461U, // VPMOVUSQBZrrkz 0U, // VPMOVUSQDZ128mr 49U, // VPMOVUSQDZ128mrk 0U, // VPMOVUSQDZ128rr 405U, // VPMOVUSQDZ128rrk 461U, // VPMOVUSQDZ128rrkz 0U, // VPMOVUSQDZ256mr 49U, // VPMOVUSQDZ256mrk 0U, // VPMOVUSQDZ256rr 405U, // VPMOVUSQDZ256rrk 461U, // VPMOVUSQDZ256rrkz 0U, // VPMOVUSQDZmr 49U, // VPMOVUSQDZmrk 0U, // VPMOVUSQDZrr 405U, // VPMOVUSQDZrrk 461U, // VPMOVUSQDZrrkz 0U, // VPMOVUSQWZ128mr 49U, // VPMOVUSQWZ128mrk 0U, // VPMOVUSQWZ128rr 405U, // VPMOVUSQWZ128rrk 461U, // VPMOVUSQWZ128rrkz 0U, // VPMOVUSQWZ256mr 49U, // VPMOVUSQWZ256mrk 0U, // VPMOVUSQWZ256rr 405U, // VPMOVUSQWZ256rrk 461U, // VPMOVUSQWZ256rrkz 0U, // VPMOVUSQWZmr 49U, // VPMOVUSQWZmrk 0U, // VPMOVUSQWZrr 405U, // VPMOVUSQWZrrk 461U, // VPMOVUSQWZrrkz 0U, // VPMOVUSWBZ128mr 49U, // VPMOVUSWBZ128mrk 0U, // VPMOVUSWBZ128rr 405U, // VPMOVUSWBZ128rrk 461U, // VPMOVUSWBZ128rrkz 0U, // VPMOVUSWBZ256mr 49U, // VPMOVUSWBZ256mrk 0U, // VPMOVUSWBZ256rr 405U, // VPMOVUSWBZ256rrk 461U, // VPMOVUSWBZ256rrkz 0U, // VPMOVUSWBZmr 49U, // VPMOVUSWBZmrk 0U, // VPMOVUSWBZrr 405U, // VPMOVUSWBZrrk 461U, // VPMOVUSWBZrrkz 0U, // VPMOVW2MZ128rr 0U, // VPMOVW2MZ256rr 0U, // VPMOVW2MZrr 0U, // VPMOVWBZ128mr 49U, // VPMOVWBZ128mrk 0U, // VPMOVWBZ128rr 405U, // VPMOVWBZ128rrk 461U, // VPMOVWBZ128rrkz 0U, // VPMOVWBZ256mr 49U, // VPMOVWBZ256mrk 0U, // VPMOVWBZ256rr 405U, // VPMOVWBZ256rrk 461U, // VPMOVWBZ256rrkz 0U, // VPMOVWBZmr 49U, // VPMOVWBZmrk 0U, // VPMOVWBZrr 405U, // VPMOVWBZrrk 461U, // VPMOVWBZrrkz 0U, // VPMOVZXBDYrm 0U, // VPMOVZXBDYrr 0U, // VPMOVZXBDZ128rm 3356U, // VPMOVZXBDZ128rmk 4444U, // VPMOVZXBDZ128rmkz 0U, // VPMOVZXBDZ128rr 405U, // VPMOVZXBDZ128rrk 461U, // VPMOVZXBDZ128rrkz 0U, // VPMOVZXBDZ256rm 3356U, // VPMOVZXBDZ256rmk 4444U, // VPMOVZXBDZ256rmkz 0U, // VPMOVZXBDZ256rr 405U, // VPMOVZXBDZ256rrk 461U, // VPMOVZXBDZ256rrkz 0U, // VPMOVZXBDZrm 405U, // VPMOVZXBDZrmk 461U, // VPMOVZXBDZrmkz 0U, // VPMOVZXBDZrr 405U, // VPMOVZXBDZrrk 461U, // VPMOVZXBDZrrkz 0U, // VPMOVZXBDrm 0U, // VPMOVZXBDrr 0U, // VPMOVZXBQYrm 0U, // VPMOVZXBQYrr 0U, // VPMOVZXBQZ128rm 0U, // VPMOVZXBQZ128rmk 461U, // VPMOVZXBQZ128rmkz 0U, // VPMOVZXBQZ128rr 405U, // VPMOVZXBQZ128rrk 461U, // VPMOVZXBQZ128rrkz 0U, // VPMOVZXBQZ256rm 3356U, // VPMOVZXBQZ256rmk 4444U, // VPMOVZXBQZ256rmkz 0U, // VPMOVZXBQZ256rr 405U, // VPMOVZXBQZ256rrk 461U, // VPMOVZXBQZ256rrkz 0U, // VPMOVZXBQZrm 3356U, // VPMOVZXBQZrmk 4444U, // VPMOVZXBQZrmkz 0U, // VPMOVZXBQZrr 405U, // VPMOVZXBQZrrk 461U, // VPMOVZXBQZrrkz 0U, // VPMOVZXBQrm 0U, // VPMOVZXBQrr 0U, // VPMOVZXBWYrm 0U, // VPMOVZXBWYrr 0U, // VPMOVZXBWZ128rm 3356U, // VPMOVZXBWZ128rmk 4444U, // VPMOVZXBWZ128rmkz 0U, // VPMOVZXBWZ128rr 405U, // VPMOVZXBWZ128rrk 461U, // VPMOVZXBWZ128rrkz 0U, // VPMOVZXBWZ256rm 405U, // VPMOVZXBWZ256rmk 461U, // VPMOVZXBWZ256rmkz 0U, // VPMOVZXBWZ256rr 405U, // VPMOVZXBWZ256rrk 461U, // VPMOVZXBWZ256rrkz 0U, // VPMOVZXBWZrm 405U, // VPMOVZXBWZrmk 461U, // VPMOVZXBWZrmkz 0U, // VPMOVZXBWZrr 405U, // VPMOVZXBWZrrk 461U, // VPMOVZXBWZrrkz 0U, // VPMOVZXBWrm 0U, // VPMOVZXBWrr 0U, // VPMOVZXDQYrm 0U, // VPMOVZXDQYrr 0U, // VPMOVZXDQZ128rm 3356U, // VPMOVZXDQZ128rmk 4444U, // VPMOVZXDQZ128rmkz 0U, // VPMOVZXDQZ128rr 405U, // VPMOVZXDQZ128rrk 461U, // VPMOVZXDQZ128rrkz 0U, // VPMOVZXDQZ256rm 405U, // VPMOVZXDQZ256rmk 461U, // VPMOVZXDQZ256rmkz 0U, // VPMOVZXDQZ256rr 405U, // VPMOVZXDQZ256rrk 461U, // VPMOVZXDQZ256rrkz 0U, // VPMOVZXDQZrm 405U, // VPMOVZXDQZrmk 461U, // VPMOVZXDQZrmkz 0U, // VPMOVZXDQZrr 405U, // VPMOVZXDQZrrk 461U, // VPMOVZXDQZrrkz 0U, // VPMOVZXDQrm 0U, // VPMOVZXDQrr 0U, // VPMOVZXWDYrm 0U, // VPMOVZXWDYrr 0U, // VPMOVZXWDZ128rm 3356U, // VPMOVZXWDZ128rmk 4444U, // VPMOVZXWDZ128rmkz 0U, // VPMOVZXWDZ128rr 405U, // VPMOVZXWDZ128rrk 461U, // VPMOVZXWDZ128rrkz 0U, // VPMOVZXWDZ256rm 405U, // VPMOVZXWDZ256rmk 461U, // VPMOVZXWDZ256rmkz 0U, // VPMOVZXWDZ256rr 405U, // VPMOVZXWDZ256rrk 461U, // VPMOVZXWDZ256rrkz 0U, // VPMOVZXWDZrm 405U, // VPMOVZXWDZrmk 461U, // VPMOVZXWDZrmkz 0U, // VPMOVZXWDZrr 405U, // VPMOVZXWDZrrk 461U, // VPMOVZXWDZrrkz 0U, // VPMOVZXWDrm 0U, // VPMOVZXWDrr 0U, // VPMOVZXWQYrm 0U, // VPMOVZXWQYrr 0U, // VPMOVZXWQZ128rm 3356U, // VPMOVZXWQZ128rmk 4444U, // VPMOVZXWQZ128rmkz 0U, // VPMOVZXWQZ128rr 405U, // VPMOVZXWQZ128rrk 461U, // VPMOVZXWQZ128rrkz 0U, // VPMOVZXWQZ256rm 3356U, // VPMOVZXWQZ256rmk 4444U, // VPMOVZXWQZ256rmkz 0U, // VPMOVZXWQZ256rr 405U, // VPMOVZXWQZ256rrk 461U, // VPMOVZXWQZ256rrkz 0U, // VPMOVZXWQZrm 405U, // VPMOVZXWQZrmk 461U, // VPMOVZXWQZrmkz 0U, // VPMOVZXWQZrr 405U, // VPMOVZXWQZrrk 461U, // VPMOVZXWQZrrkz 0U, // VPMOVZXWQrm 0U, // VPMOVZXWQrr 4U, // VPMULDQYrm 4U, // VPMULDQYrr 4U, // VPMULDQZ128rm 72U, // VPMULDQZ128rmb 133U, // VPMULDQZ128rmbk 9348U, // VPMULDQZ128rmbkz 132U, // VPMULDQZ128rmk 9348U, // VPMULDQZ128rmkz 4U, // VPMULDQZ128rr 0U, // VPMULDQZ128rrk 9348U, // VPMULDQZ128rrkz 4U, // VPMULDQZ256rm 72U, // VPMULDQZ256rmb 133U, // VPMULDQZ256rmbk 9348U, // VPMULDQZ256rmbkz 132U, // VPMULDQZ256rmk 9348U, // VPMULDQZ256rmkz 4U, // VPMULDQZ256rr 0U, // VPMULDQZ256rrk 9348U, // VPMULDQZ256rrkz 4U, // VPMULDQZrm 72U, // VPMULDQZrmb 133U, // VPMULDQZrmbk 9348U, // VPMULDQZrmbkz 132U, // VPMULDQZrmk 9348U, // VPMULDQZrmkz 4U, // VPMULDQZrr 0U, // VPMULDQZrrk 9348U, // VPMULDQZrrkz 4U, // VPMULDQrm 4U, // VPMULDQrr 4U, // VPMULHRSWYrm 4U, // VPMULHRSWYrr 4U, // VPMULHRSWZ128rm 132U, // VPMULHRSWZ128rmk 9348U, // VPMULHRSWZ128rmkz 4U, // VPMULHRSWZ128rr 0U, // VPMULHRSWZ128rrk 9348U, // VPMULHRSWZ128rrkz 4U, // VPMULHRSWZ256rm 132U, // VPMULHRSWZ256rmk 9348U, // VPMULHRSWZ256rmkz 4U, // VPMULHRSWZ256rr 0U, // VPMULHRSWZ256rrk 9348U, // VPMULHRSWZ256rrkz 4U, // VPMULHRSWZrm 132U, // VPMULHRSWZrmk 9348U, // VPMULHRSWZrmkz 4U, // VPMULHRSWZrr 0U, // VPMULHRSWZrrk 9348U, // VPMULHRSWZrrkz 4U, // VPMULHRSWrm 4U, // VPMULHRSWrr 4U, // VPMULHUWYrm 4U, // VPMULHUWYrr 4U, // VPMULHUWZ128rm 132U, // VPMULHUWZ128rmk 9348U, // VPMULHUWZ128rmkz 4U, // VPMULHUWZ128rr 0U, // VPMULHUWZ128rrk 9348U, // VPMULHUWZ128rrkz 4U, // VPMULHUWZ256rm 132U, // VPMULHUWZ256rmk 9348U, // VPMULHUWZ256rmkz 4U, // VPMULHUWZ256rr 0U, // VPMULHUWZ256rrk 9348U, // VPMULHUWZ256rrkz 4U, // VPMULHUWZrm 132U, // VPMULHUWZrmk 9348U, // VPMULHUWZrmkz 4U, // VPMULHUWZrr 0U, // VPMULHUWZrrk 9348U, // VPMULHUWZrrkz 4U, // VPMULHUWrm 4U, // VPMULHUWrr 4U, // VPMULHWYrm 4U, // VPMULHWYrr 4U, // VPMULHWZ128rm 132U, // VPMULHWZ128rmk 9348U, // VPMULHWZ128rmkz 4U, // VPMULHWZ128rr 0U, // VPMULHWZ128rrk 9348U, // VPMULHWZ128rrkz 4U, // VPMULHWZ256rm 132U, // VPMULHWZ256rmk 9348U, // VPMULHWZ256rmkz 4U, // VPMULHWZ256rr 0U, // VPMULHWZ256rrk 9348U, // VPMULHWZ256rrkz 4U, // VPMULHWZrm 132U, // VPMULHWZrmk 9348U, // VPMULHWZrmkz 4U, // VPMULHWZrr 0U, // VPMULHWZrrk 9348U, // VPMULHWZrrkz 4U, // VPMULHWrm 4U, // VPMULHWrr 4U, // VPMULLDYrm 4U, // VPMULLDYrr 4U, // VPMULLDZ128rm 72U, // VPMULLDZ128rmb 133U, // VPMULLDZ128rmbk 9348U, // VPMULLDZ128rmbkz 132U, // VPMULLDZ128rmk 9348U, // VPMULLDZ128rmkz 4U, // VPMULLDZ128rr 0U, // VPMULLDZ128rrk 9348U, // VPMULLDZ128rrkz 4U, // VPMULLDZ256rm 72U, // VPMULLDZ256rmb 133U, // VPMULLDZ256rmbk 9348U, // VPMULLDZ256rmbkz 132U, // VPMULLDZ256rmk 9348U, // VPMULLDZ256rmkz 4U, // VPMULLDZ256rr 0U, // VPMULLDZ256rrk 9348U, // VPMULLDZ256rrkz 4U, // VPMULLDZrm 72U, // VPMULLDZrmb 133U, // VPMULLDZrmbk 9348U, // VPMULLDZrmbkz 132U, // VPMULLDZrmk 9348U, // VPMULLDZrmkz 4U, // VPMULLDZrr 0U, // VPMULLDZrrk 9348U, // VPMULLDZrrkz 4U, // VPMULLDrm 4U, // VPMULLDrr 4U, // VPMULLQZ128rm 72U, // VPMULLQZ128rmb 133U, // VPMULLQZ128rmbk 9348U, // VPMULLQZ128rmbkz 132U, // VPMULLQZ128rmk 9348U, // VPMULLQZ128rmkz 4U, // VPMULLQZ128rr 0U, // VPMULLQZ128rrk 9348U, // VPMULLQZ128rrkz 4U, // VPMULLQZ256rm 72U, // VPMULLQZ256rmb 133U, // VPMULLQZ256rmbk 9348U, // VPMULLQZ256rmbkz 132U, // VPMULLQZ256rmk 9348U, // VPMULLQZ256rmkz 4U, // VPMULLQZ256rr 0U, // VPMULLQZ256rrk 9348U, // VPMULLQZ256rrkz 4U, // VPMULLQZrm 72U, // VPMULLQZrmb 133U, // VPMULLQZrmbk 9348U, // VPMULLQZrmbkz 132U, // VPMULLQZrmk 9348U, // VPMULLQZrmkz 4U, // VPMULLQZrr 0U, // VPMULLQZrrk 9348U, // VPMULLQZrrkz 4U, // VPMULLWYrm 4U, // VPMULLWYrr 4U, // VPMULLWZ128rm 132U, // VPMULLWZ128rmk 9348U, // VPMULLWZ128rmkz 4U, // VPMULLWZ128rr 0U, // VPMULLWZ128rrk 9348U, // VPMULLWZ128rrkz 4U, // VPMULLWZ256rm 132U, // VPMULLWZ256rmk 9348U, // VPMULLWZ256rmkz 4U, // VPMULLWZ256rr 0U, // VPMULLWZ256rrk 9348U, // VPMULLWZ256rrkz 4U, // VPMULLWZrm 132U, // VPMULLWZrmk 9348U, // VPMULLWZrmkz 4U, // VPMULLWZrr 0U, // VPMULLWZrrk 9348U, // VPMULLWZrrkz 4U, // VPMULLWrm 4U, // VPMULLWrr 4U, // VPMULTISHIFTQBZ128rm 72U, // VPMULTISHIFTQBZ128rmb 133U, // VPMULTISHIFTQBZ128rmbk 9348U, // VPMULTISHIFTQBZ128rmbkz 132U, // VPMULTISHIFTQBZ128rmk 9348U, // VPMULTISHIFTQBZ128rmkz 4U, // VPMULTISHIFTQBZ128rr 0U, // VPMULTISHIFTQBZ128rrk 9348U, // VPMULTISHIFTQBZ128rrkz 4U, // VPMULTISHIFTQBZ256rm 72U, // VPMULTISHIFTQBZ256rmb 133U, // VPMULTISHIFTQBZ256rmbk 9348U, // VPMULTISHIFTQBZ256rmbkz 132U, // VPMULTISHIFTQBZ256rmk 9348U, // VPMULTISHIFTQBZ256rmkz 4U, // VPMULTISHIFTQBZ256rr 0U, // VPMULTISHIFTQBZ256rrk 9348U, // VPMULTISHIFTQBZ256rrkz 4U, // VPMULTISHIFTQBZrm 72U, // VPMULTISHIFTQBZrmb 133U, // VPMULTISHIFTQBZrmbk 9348U, // VPMULTISHIFTQBZrmbkz 132U, // VPMULTISHIFTQBZrmk 9348U, // VPMULTISHIFTQBZrmkz 4U, // VPMULTISHIFTQBZrr 0U, // VPMULTISHIFTQBZrrk 9348U, // VPMULTISHIFTQBZrrkz 4U, // VPMULUDQYrm 4U, // VPMULUDQYrr 4U, // VPMULUDQZ128rm 72U, // VPMULUDQZ128rmb 133U, // VPMULUDQZ128rmbk 9348U, // VPMULUDQZ128rmbkz 132U, // VPMULUDQZ128rmk 9348U, // VPMULUDQZ128rmkz 4U, // VPMULUDQZ128rr 0U, // VPMULUDQZ128rrk 9348U, // VPMULUDQZ128rrkz 4U, // VPMULUDQZ256rm 72U, // VPMULUDQZ256rmb 133U, // VPMULUDQZ256rmbk 9348U, // VPMULUDQZ256rmbkz 132U, // VPMULUDQZ256rmk 9348U, // VPMULUDQZ256rmkz 4U, // VPMULUDQZ256rr 0U, // VPMULUDQZ256rrk 9348U, // VPMULUDQZ256rrkz 4U, // VPMULUDQZrm 72U, // VPMULUDQZrmb 133U, // VPMULUDQZrmbk 9348U, // VPMULUDQZrmbkz 132U, // VPMULUDQZrmk 9348U, // VPMULUDQZrmkz 4U, // VPMULUDQZrr 0U, // VPMULUDQZrrk 9348U, // VPMULUDQZrrkz 4U, // VPMULUDQrm 4U, // VPMULUDQrr 0U, // VPOPCNTBZ128rm 405U, // VPOPCNTBZ128rmk 461U, // VPOPCNTBZ128rmkz 0U, // VPOPCNTBZ128rr 405U, // VPOPCNTBZ128rrk 461U, // VPOPCNTBZ128rrkz 0U, // VPOPCNTBZ256rm 405U, // VPOPCNTBZ256rmk 461U, // VPOPCNTBZ256rmkz 0U, // VPOPCNTBZ256rr 405U, // VPOPCNTBZ256rrk 461U, // VPOPCNTBZ256rrkz 0U, // VPOPCNTBZrm 405U, // VPOPCNTBZrmk 461U, // VPOPCNTBZrmkz 0U, // VPOPCNTBZrr 405U, // VPOPCNTBZrrk 461U, // VPOPCNTBZrrkz 0U, // VPOPCNTDZ128rm 0U, // VPOPCNTDZ128rmb 3356U, // VPOPCNTDZ128rmbk 4444U, // VPOPCNTDZ128rmbkz 405U, // VPOPCNTDZ128rmk 461U, // VPOPCNTDZ128rmkz 0U, // VPOPCNTDZ128rr 405U, // VPOPCNTDZ128rrk 461U, // VPOPCNTDZ128rrkz 0U, // VPOPCNTDZ256rm 0U, // VPOPCNTDZ256rmb 3356U, // VPOPCNTDZ256rmbk 4444U, // VPOPCNTDZ256rmbkz 405U, // VPOPCNTDZ256rmk 461U, // VPOPCNTDZ256rmkz 0U, // VPOPCNTDZ256rr 405U, // VPOPCNTDZ256rrk 461U, // VPOPCNTDZ256rrkz 0U, // VPOPCNTDZrm 0U, // VPOPCNTDZrmb 3356U, // VPOPCNTDZrmbk 4444U, // VPOPCNTDZrmbkz 405U, // VPOPCNTDZrmk 461U, // VPOPCNTDZrmkz 0U, // VPOPCNTDZrr 405U, // VPOPCNTDZrrk 461U, // VPOPCNTDZrrkz 0U, // VPOPCNTQZ128rm 0U, // VPOPCNTQZ128rmb 3356U, // VPOPCNTQZ128rmbk 4444U, // VPOPCNTQZ128rmbkz 405U, // VPOPCNTQZ128rmk 461U, // VPOPCNTQZ128rmkz 0U, // VPOPCNTQZ128rr 405U, // VPOPCNTQZ128rrk 461U, // VPOPCNTQZ128rrkz 0U, // VPOPCNTQZ256rm 0U, // VPOPCNTQZ256rmb 3356U, // VPOPCNTQZ256rmbk 4444U, // VPOPCNTQZ256rmbkz 405U, // VPOPCNTQZ256rmk 461U, // VPOPCNTQZ256rmkz 0U, // VPOPCNTQZ256rr 405U, // VPOPCNTQZ256rrk 461U, // VPOPCNTQZ256rrkz 0U, // VPOPCNTQZrm 0U, // VPOPCNTQZrmb 3356U, // VPOPCNTQZrmbk 4444U, // VPOPCNTQZrmbkz 405U, // VPOPCNTQZrmk 461U, // VPOPCNTQZrmkz 0U, // VPOPCNTQZrr 405U, // VPOPCNTQZrrk 461U, // VPOPCNTQZrrkz 0U, // VPOPCNTWZ128rm 405U, // VPOPCNTWZ128rmk 461U, // VPOPCNTWZ128rmkz 0U, // VPOPCNTWZ128rr 405U, // VPOPCNTWZ128rrk 461U, // VPOPCNTWZ128rrkz 0U, // VPOPCNTWZ256rm 405U, // VPOPCNTWZ256rmk 461U, // VPOPCNTWZ256rmkz 0U, // VPOPCNTWZ256rr 405U, // VPOPCNTWZ256rrk 461U, // VPOPCNTWZ256rrkz 0U, // VPOPCNTWZrm 405U, // VPOPCNTWZrmk 461U, // VPOPCNTWZrmkz 0U, // VPOPCNTWZrr 405U, // VPOPCNTWZrrk 461U, // VPOPCNTWZrrkz 4U, // VPORDZ128rm 72U, // VPORDZ128rmb 133U, // VPORDZ128rmbk 9348U, // VPORDZ128rmbkz 132U, // VPORDZ128rmk 9348U, // VPORDZ128rmkz 4U, // VPORDZ128rr 0U, // VPORDZ128rrk 9348U, // VPORDZ128rrkz 4U, // VPORDZ256rm 72U, // VPORDZ256rmb 133U, // VPORDZ256rmbk 9348U, // VPORDZ256rmbkz 132U, // VPORDZ256rmk 9348U, // VPORDZ256rmkz 4U, // VPORDZ256rr 0U, // VPORDZ256rrk 9348U, // VPORDZ256rrkz 4U, // VPORDZrm 72U, // VPORDZrmb 133U, // VPORDZrmbk 9348U, // VPORDZrmbkz 132U, // VPORDZrmk 9348U, // VPORDZrmkz 4U, // VPORDZrr 0U, // VPORDZrrk 9348U, // VPORDZrrkz 4U, // VPORQZ128rm 72U, // VPORQZ128rmb 133U, // VPORQZ128rmbk 9348U, // VPORQZ128rmbkz 132U, // VPORQZ128rmk 9348U, // VPORQZ128rmkz 4U, // VPORQZ128rr 0U, // VPORQZ128rrk 9348U, // VPORQZ128rrkz 4U, // VPORQZ256rm 72U, // VPORQZ256rmb 133U, // VPORQZ256rmbk 9348U, // VPORQZ256rmbkz 132U, // VPORQZ256rmk 9348U, // VPORQZ256rmkz 4U, // VPORQZ256rr 0U, // VPORQZ256rrk 9348U, // VPORQZ256rrkz 4U, // VPORQZrm 72U, // VPORQZrmb 133U, // VPORQZrmbk 9348U, // VPORQZrmbkz 132U, // VPORQZrmk 9348U, // VPORQZrmkz 4U, // VPORQZrr 0U, // VPORQZrrk 9348U, // VPORQZrrkz 4U, // VPORYrm 4U, // VPORYrr 4U, // VPORrm 4U, // VPORrr 72U, // VPPERMrmr 18636U, // VPPERMrrm 18636U, // VPPERMrrr 18636U, // VPPERMrrr_REV 5U, // VPROLDZ128mbi 133U, // VPROLDZ128mbik 9349U, // VPROLDZ128mbikz 4U, // VPROLDZ128mi 3356U, // VPROLDZ128mik 4444U, // VPROLDZ128mikz 72U, // VPROLDZ128ri 133U, // VPROLDZ128rik 9348U, // VPROLDZ128rikz 5U, // VPROLDZ256mbi 133U, // VPROLDZ256mbik 9349U, // VPROLDZ256mbikz 4U, // VPROLDZ256mi 3356U, // VPROLDZ256mik 4444U, // VPROLDZ256mikz 72U, // VPROLDZ256ri 133U, // VPROLDZ256rik 9348U, // VPROLDZ256rikz 5U, // VPROLDZmbi 133U, // VPROLDZmbik 9349U, // VPROLDZmbikz 4U, // VPROLDZmi 3356U, // VPROLDZmik 4444U, // VPROLDZmikz 72U, // VPROLDZri 133U, // VPROLDZrik 9348U, // VPROLDZrikz 5U, // VPROLQZ128mbi 133U, // VPROLQZ128mbik 9349U, // VPROLQZ128mbikz 4U, // VPROLQZ128mi 3356U, // VPROLQZ128mik 4444U, // VPROLQZ128mikz 72U, // VPROLQZ128ri 133U, // VPROLQZ128rik 9348U, // VPROLQZ128rikz 5U, // VPROLQZ256mbi 133U, // VPROLQZ256mbik 9349U, // VPROLQZ256mbikz 4U, // VPROLQZ256mi 3356U, // VPROLQZ256mik 4444U, // VPROLQZ256mikz 72U, // VPROLQZ256ri 133U, // VPROLQZ256rik 9348U, // VPROLQZ256rikz 5U, // VPROLQZmbi 133U, // VPROLQZmbik 9349U, // VPROLQZmbikz 4U, // VPROLQZmi 3356U, // VPROLQZmik 4444U, // VPROLQZmikz 72U, // VPROLQZri 133U, // VPROLQZrik 9348U, // VPROLQZrikz 4U, // VPROLVDZ128rm 72U, // VPROLVDZ128rmb 133U, // VPROLVDZ128rmbk 9348U, // VPROLVDZ128rmbkz 132U, // VPROLVDZ128rmk 9348U, // VPROLVDZ128rmkz 4U, // VPROLVDZ128rr 0U, // VPROLVDZ128rrk 9348U, // VPROLVDZ128rrkz 4U, // VPROLVDZ256rm 72U, // VPROLVDZ256rmb 133U, // VPROLVDZ256rmbk 9348U, // VPROLVDZ256rmbkz 132U, // VPROLVDZ256rmk 9348U, // VPROLVDZ256rmkz 4U, // VPROLVDZ256rr 0U, // VPROLVDZ256rrk 9348U, // VPROLVDZ256rrkz 4U, // VPROLVDZrm 72U, // VPROLVDZrmb 133U, // VPROLVDZrmbk 9348U, // VPROLVDZrmbkz 132U, // VPROLVDZrmk 9348U, // VPROLVDZrmkz 4U, // VPROLVDZrr 0U, // VPROLVDZrrk 9348U, // VPROLVDZrrkz 4U, // VPROLVQZ128rm 72U, // VPROLVQZ128rmb 133U, // VPROLVQZ128rmbk 9348U, // VPROLVQZ128rmbkz 132U, // VPROLVQZ128rmk 9348U, // VPROLVQZ128rmkz 4U, // VPROLVQZ128rr 0U, // VPROLVQZ128rrk 9348U, // VPROLVQZ128rrkz 4U, // VPROLVQZ256rm 72U, // VPROLVQZ256rmb 133U, // VPROLVQZ256rmbk 9348U, // VPROLVQZ256rmbkz 132U, // VPROLVQZ256rmk 9348U, // VPROLVQZ256rmkz 4U, // VPROLVQZ256rr 0U, // VPROLVQZ256rrk 9348U, // VPROLVQZ256rrkz 4U, // VPROLVQZrm 72U, // VPROLVQZrmb 133U, // VPROLVQZrmbk 9348U, // VPROLVQZrmbkz 132U, // VPROLVQZrmk 9348U, // VPROLVQZrmkz 4U, // VPROLVQZrr 0U, // VPROLVQZrrk 9348U, // VPROLVQZrrkz 5U, // VPRORDZ128mbi 133U, // VPRORDZ128mbik 9349U, // VPRORDZ128mbikz 4U, // VPRORDZ128mi 3356U, // VPRORDZ128mik 4444U, // VPRORDZ128mikz 72U, // VPRORDZ128ri 133U, // VPRORDZ128rik 9348U, // VPRORDZ128rikz 5U, // VPRORDZ256mbi 133U, // VPRORDZ256mbik 9349U, // VPRORDZ256mbikz 4U, // VPRORDZ256mi 3356U, // VPRORDZ256mik 4444U, // VPRORDZ256mikz 72U, // VPRORDZ256ri 133U, // VPRORDZ256rik 9348U, // VPRORDZ256rikz 5U, // VPRORDZmbi 133U, // VPRORDZmbik 9349U, // VPRORDZmbikz 4U, // VPRORDZmi 3356U, // VPRORDZmik 4444U, // VPRORDZmikz 72U, // VPRORDZri 133U, // VPRORDZrik 9348U, // VPRORDZrikz 5U, // VPRORQZ128mbi 133U, // VPRORQZ128mbik 9349U, // VPRORQZ128mbikz 4U, // VPRORQZ128mi 3356U, // VPRORQZ128mik 4444U, // VPRORQZ128mikz 72U, // VPRORQZ128ri 133U, // VPRORQZ128rik 9348U, // VPRORQZ128rikz 5U, // VPRORQZ256mbi 133U, // VPRORQZ256mbik 9349U, // VPRORQZ256mbikz 4U, // VPRORQZ256mi 3356U, // VPRORQZ256mik 4444U, // VPRORQZ256mikz 72U, // VPRORQZ256ri 133U, // VPRORQZ256rik 9348U, // VPRORQZ256rikz 5U, // VPRORQZmbi 133U, // VPRORQZmbik 9349U, // VPRORQZmbikz 4U, // VPRORQZmi 3356U, // VPRORQZmik 4444U, // VPRORQZmikz 72U, // VPRORQZri 133U, // VPRORQZrik 9348U, // VPRORQZrikz 4U, // VPRORVDZ128rm 72U, // VPRORVDZ128rmb 133U, // VPRORVDZ128rmbk 9348U, // VPRORVDZ128rmbkz 132U, // VPRORVDZ128rmk 9348U, // VPRORVDZ128rmkz 4U, // VPRORVDZ128rr 0U, // VPRORVDZ128rrk 9348U, // VPRORVDZ128rrkz 4U, // VPRORVDZ256rm 72U, // VPRORVDZ256rmb 133U, // VPRORVDZ256rmbk 9348U, // VPRORVDZ256rmbkz 132U, // VPRORVDZ256rmk 9348U, // VPRORVDZ256rmkz 4U, // VPRORVDZ256rr 0U, // VPRORVDZ256rrk 9348U, // VPRORVDZ256rrkz 4U, // VPRORVDZrm 72U, // VPRORVDZrmb 133U, // VPRORVDZrmbk 9348U, // VPRORVDZrmbkz 132U, // VPRORVDZrmk 9348U, // VPRORVDZrmkz 4U, // VPRORVDZrr 0U, // VPRORVDZrrk 9348U, // VPRORVDZrrkz 4U, // VPRORVQZ128rm 72U, // VPRORVQZ128rmb 133U, // VPRORVQZ128rmbk 9348U, // VPRORVQZ128rmbkz 132U, // VPRORVQZ128rmk 9348U, // VPRORVQZ128rmkz 4U, // VPRORVQZ128rr 0U, // VPRORVQZ128rrk 9348U, // VPRORVQZ128rrkz 4U, // VPRORVQZ256rm 72U, // VPRORVQZ256rmb 133U, // VPRORVQZ256rmbk 9348U, // VPRORVQZ256rmbkz 132U, // VPRORVQZ256rmk 9348U, // VPRORVQZ256rmkz 4U, // VPRORVQZ256rr 0U, // VPRORVQZ256rrk 9348U, // VPRORVQZ256rrkz 4U, // VPRORVQZrm 72U, // VPRORVQZrmb 133U, // VPRORVQZrmbk 9348U, // VPRORVQZrmbkz 132U, // VPRORVQZrmk 9348U, // VPRORVQZrmkz 4U, // VPRORVQZrr 0U, // VPRORVQZrrk 9348U, // VPRORVQZrrkz 4U, // VPROTBmi 4U, // VPROTBmr 72U, // VPROTBri 4U, // VPROTBrm 4U, // VPROTBrr 4U, // VPROTBrr_REV 4U, // VPROTDmi 4U, // VPROTDmr 72U, // VPROTDri 4U, // VPROTDrm 4U, // VPROTDrr 4U, // VPROTDrr_REV 4U, // VPROTQmi 4U, // VPROTQmr 72U, // VPROTQri 4U, // VPROTQrm 4U, // VPROTQrr 4U, // VPROTQrr_REV 4U, // VPROTWmi 4U, // VPROTWmr 72U, // VPROTWri 4U, // VPROTWrm 4U, // VPROTWrr 4U, // VPROTWrr_REV 4U, // VPSADBWYrm 4U, // VPSADBWYrr 4U, // VPSADBWZ128rm 4U, // VPSADBWZ128rr 4U, // VPSADBWZ256rm 4U, // VPSADBWZ256rr 4U, // VPSADBWZrm 4U, // VPSADBWZrr 4U, // VPSADBWrm 4U, // VPSADBWrr 57U, // VPSCATTERDDZ128mr 57U, // VPSCATTERDDZ256mr 57U, // VPSCATTERDDZmr 57U, // VPSCATTERDQZ128mr 57U, // VPSCATTERDQZ256mr 57U, // VPSCATTERDQZmr 57U, // VPSCATTERQDZ128mr 57U, // VPSCATTERQDZ256mr 57U, // VPSCATTERQDZmr 57U, // VPSCATTERQQZ128mr 57U, // VPSCATTERQQZ256mr 57U, // VPSCATTERQQZmr 4U, // VPSHABmr 4U, // VPSHABrm 4U, // VPSHABrr 4U, // VPSHABrr_REV 4U, // VPSHADmr 4U, // VPSHADrm 4U, // VPSHADrr 4U, // VPSHADrr_REV 4U, // VPSHAQmr 4U, // VPSHAQrm 4U, // VPSHAQrr 4U, // VPSHAQrr_REV 4U, // VPSHAWmr 4U, // VPSHAWrm 4U, // VPSHAWrr 4U, // VPSHAWrr_REV 4U, // VPSHLBmr 4U, // VPSHLBrm 4U, // VPSHLBrr 4U, // VPSHLBrr_REV 18637U, // VPSHLDDZ128rmbi 26833U, // VPSHLDDZ128rmbik 26837U, // VPSHLDDZ128rmbikz 72U, // VPSHLDDZ128rmi 1U, // VPSHLDDZ128rmik 9348U, // VPSHLDDZ128rmikz 18636U, // VPSHLDDZ128rri 25U, // VPSHLDDZ128rrik 26837U, // VPSHLDDZ128rrikz 18637U, // VPSHLDDZ256rmbi 26833U, // VPSHLDDZ256rmbik 26837U, // VPSHLDDZ256rmbikz 72U, // VPSHLDDZ256rmi 1U, // VPSHLDDZ256rmik 9348U, // VPSHLDDZ256rmikz 18636U, // VPSHLDDZ256rri 25U, // VPSHLDDZ256rrik 26837U, // VPSHLDDZ256rrikz 18637U, // VPSHLDDZrmbi 26833U, // VPSHLDDZrmbik 26837U, // VPSHLDDZrmbikz 72U, // VPSHLDDZrmi 1U, // VPSHLDDZrmik 9348U, // VPSHLDDZrmikz 18636U, // VPSHLDDZrri 25U, // VPSHLDDZrrik 26837U, // VPSHLDDZrrikz 18637U, // VPSHLDQZ128rmbi 26833U, // VPSHLDQZ128rmbik 26837U, // VPSHLDQZ128rmbikz 72U, // VPSHLDQZ128rmi 1U, // VPSHLDQZ128rmik 9348U, // VPSHLDQZ128rmikz 18636U, // VPSHLDQZ128rri 25U, // VPSHLDQZ128rrik 26837U, // VPSHLDQZ128rrikz 18637U, // VPSHLDQZ256rmbi 26833U, // VPSHLDQZ256rmbik 26837U, // VPSHLDQZ256rmbikz 72U, // VPSHLDQZ256rmi 1U, // VPSHLDQZ256rmik 9348U, // VPSHLDQZ256rmikz 18636U, // VPSHLDQZ256rri 25U, // VPSHLDQZ256rrik 26837U, // VPSHLDQZ256rrikz 18637U, // VPSHLDQZrmbi 26833U, // VPSHLDQZrmbik 26837U, // VPSHLDQZrmbikz 72U, // VPSHLDQZrmi 1U, // VPSHLDQZrmik 9348U, // VPSHLDQZrmikz 18636U, // VPSHLDQZrri 25U, // VPSHLDQZrrik 26837U, // VPSHLDQZrrikz 4U, // VPSHLDVDZ128m 4U, // VPSHLDVDZ128mb 133U, // VPSHLDVDZ128mbk 8325U, // VPSHLDVDZ128mbkz 132U, // VPSHLDVDZ128mk 8324U, // VPSHLDVDZ128mkz 4U, // VPSHLDVDZ128r 0U, // VPSHLDVDZ128rk 0U, // VPSHLDVDZ128rkz 4U, // VPSHLDVDZ256m 4U, // VPSHLDVDZ256mb 133U, // VPSHLDVDZ256mbk 8325U, // VPSHLDVDZ256mbkz 132U, // VPSHLDVDZ256mk 8324U, // VPSHLDVDZ256mkz 4U, // VPSHLDVDZ256r 0U, // VPSHLDVDZ256rk 0U, // VPSHLDVDZ256rkz 4U, // VPSHLDVDZm 4U, // VPSHLDVDZmb 133U, // VPSHLDVDZmbk 8325U, // VPSHLDVDZmbkz 132U, // VPSHLDVDZmk 8324U, // VPSHLDVDZmkz 4U, // VPSHLDVDZr 0U, // VPSHLDVDZrk 0U, // VPSHLDVDZrkz 4U, // VPSHLDVQZ128m 4U, // VPSHLDVQZ128mb 133U, // VPSHLDVQZ128mbk 8325U, // VPSHLDVQZ128mbkz 132U, // VPSHLDVQZ128mk 8324U, // VPSHLDVQZ128mkz 4U, // VPSHLDVQZ128r 0U, // VPSHLDVQZ128rk 0U, // VPSHLDVQZ128rkz 4U, // VPSHLDVQZ256m 4U, // VPSHLDVQZ256mb 133U, // VPSHLDVQZ256mbk 8325U, // VPSHLDVQZ256mbkz 132U, // VPSHLDVQZ256mk 8324U, // VPSHLDVQZ256mkz 4U, // VPSHLDVQZ256r 0U, // VPSHLDVQZ256rk 0U, // VPSHLDVQZ256rkz 4U, // VPSHLDVQZm 4U, // VPSHLDVQZmb 133U, // VPSHLDVQZmbk 8325U, // VPSHLDVQZmbkz 132U, // VPSHLDVQZmk 8324U, // VPSHLDVQZmkz 4U, // VPSHLDVQZr 0U, // VPSHLDVQZrk 0U, // VPSHLDVQZrkz 4U, // VPSHLDVWZ128m 132U, // VPSHLDVWZ128mk 8324U, // VPSHLDVWZ128mkz 4U, // VPSHLDVWZ128r 0U, // VPSHLDVWZ128rk 0U, // VPSHLDVWZ128rkz 4U, // VPSHLDVWZ256m 132U, // VPSHLDVWZ256mk 8324U, // VPSHLDVWZ256mkz 4U, // VPSHLDVWZ256r 0U, // VPSHLDVWZ256rk 0U, // VPSHLDVWZ256rkz 4U, // VPSHLDVWZm 132U, // VPSHLDVWZmk 8324U, // VPSHLDVWZmkz 4U, // VPSHLDVWZr 0U, // VPSHLDVWZrk 0U, // VPSHLDVWZrkz 72U, // VPSHLDWZ128rmi 1U, // VPSHLDWZ128rmik 9348U, // VPSHLDWZ128rmikz 18636U, // VPSHLDWZ128rri 25U, // VPSHLDWZ128rrik 26837U, // VPSHLDWZ128rrikz 72U, // VPSHLDWZ256rmi 1U, // VPSHLDWZ256rmik 9348U, // VPSHLDWZ256rmikz 18636U, // VPSHLDWZ256rri 25U, // VPSHLDWZ256rrik 26837U, // VPSHLDWZ256rrikz 72U, // VPSHLDWZrmi 1U, // VPSHLDWZrmik 9348U, // VPSHLDWZrmikz 18636U, // VPSHLDWZrri 25U, // VPSHLDWZrrik 26837U, // VPSHLDWZrrikz 4U, // VPSHLDmr 4U, // VPSHLDrm 4U, // VPSHLDrr 4U, // VPSHLDrr_REV 4U, // VPSHLQmr 4U, // VPSHLQrm 4U, // VPSHLQrr 4U, // VPSHLQrr_REV 4U, // VPSHLWmr 4U, // VPSHLWrm 4U, // VPSHLWrr 4U, // VPSHLWrr_REV 18637U, // VPSHRDDZ128rmbi 26833U, // VPSHRDDZ128rmbik 26837U, // VPSHRDDZ128rmbikz 72U, // VPSHRDDZ128rmi 1U, // VPSHRDDZ128rmik 9348U, // VPSHRDDZ128rmikz 18636U, // VPSHRDDZ128rri 25U, // VPSHRDDZ128rrik 26837U, // VPSHRDDZ128rrikz 18637U, // VPSHRDDZ256rmbi 26833U, // VPSHRDDZ256rmbik 26837U, // VPSHRDDZ256rmbikz 72U, // VPSHRDDZ256rmi 1U, // VPSHRDDZ256rmik 9348U, // VPSHRDDZ256rmikz 18636U, // VPSHRDDZ256rri 25U, // VPSHRDDZ256rrik 26837U, // VPSHRDDZ256rrikz 18637U, // VPSHRDDZrmbi 26833U, // VPSHRDDZrmbik 26837U, // VPSHRDDZrmbikz 72U, // VPSHRDDZrmi 1U, // VPSHRDDZrmik 9348U, // VPSHRDDZrmikz 18636U, // VPSHRDDZrri 25U, // VPSHRDDZrrik 26837U, // VPSHRDDZrrikz 18637U, // VPSHRDQZ128rmbi 26833U, // VPSHRDQZ128rmbik 26837U, // VPSHRDQZ128rmbikz 72U, // VPSHRDQZ128rmi 1U, // VPSHRDQZ128rmik 9348U, // VPSHRDQZ128rmikz 18636U, // VPSHRDQZ128rri 25U, // VPSHRDQZ128rrik 26837U, // VPSHRDQZ128rrikz 18637U, // VPSHRDQZ256rmbi 26833U, // VPSHRDQZ256rmbik 26837U, // VPSHRDQZ256rmbikz 72U, // VPSHRDQZ256rmi 1U, // VPSHRDQZ256rmik 9348U, // VPSHRDQZ256rmikz 18636U, // VPSHRDQZ256rri 25U, // VPSHRDQZ256rrik 26837U, // VPSHRDQZ256rrikz 18637U, // VPSHRDQZrmbi 26833U, // VPSHRDQZrmbik 26837U, // VPSHRDQZrmbikz 72U, // VPSHRDQZrmi 1U, // VPSHRDQZrmik 9348U, // VPSHRDQZrmikz 18636U, // VPSHRDQZrri 25U, // VPSHRDQZrrik 26837U, // VPSHRDQZrrikz 4U, // VPSHRDVDZ128m 4U, // VPSHRDVDZ128mb 133U, // VPSHRDVDZ128mbk 8325U, // VPSHRDVDZ128mbkz 132U, // VPSHRDVDZ128mk 8324U, // VPSHRDVDZ128mkz 4U, // VPSHRDVDZ128r 0U, // VPSHRDVDZ128rk 0U, // VPSHRDVDZ128rkz 4U, // VPSHRDVDZ256m 4U, // VPSHRDVDZ256mb 133U, // VPSHRDVDZ256mbk 8325U, // VPSHRDVDZ256mbkz 132U, // VPSHRDVDZ256mk 8324U, // VPSHRDVDZ256mkz 4U, // VPSHRDVDZ256r 0U, // VPSHRDVDZ256rk 0U, // VPSHRDVDZ256rkz 4U, // VPSHRDVDZm 4U, // VPSHRDVDZmb 133U, // VPSHRDVDZmbk 8325U, // VPSHRDVDZmbkz 132U, // VPSHRDVDZmk 8324U, // VPSHRDVDZmkz 4U, // VPSHRDVDZr 0U, // VPSHRDVDZrk 0U, // VPSHRDVDZrkz 4U, // VPSHRDVQZ128m 4U, // VPSHRDVQZ128mb 133U, // VPSHRDVQZ128mbk 8325U, // VPSHRDVQZ128mbkz 132U, // VPSHRDVQZ128mk 8324U, // VPSHRDVQZ128mkz 4U, // VPSHRDVQZ128r 0U, // VPSHRDVQZ128rk 0U, // VPSHRDVQZ128rkz 4U, // VPSHRDVQZ256m 4U, // VPSHRDVQZ256mb 133U, // VPSHRDVQZ256mbk 8325U, // VPSHRDVQZ256mbkz 132U, // VPSHRDVQZ256mk 8324U, // VPSHRDVQZ256mkz 4U, // VPSHRDVQZ256r 0U, // VPSHRDVQZ256rk 0U, // VPSHRDVQZ256rkz 4U, // VPSHRDVQZm 4U, // VPSHRDVQZmb 133U, // VPSHRDVQZmbk 8325U, // VPSHRDVQZmbkz 132U, // VPSHRDVQZmk 8324U, // VPSHRDVQZmkz 4U, // VPSHRDVQZr 0U, // VPSHRDVQZrk 0U, // VPSHRDVQZrkz 4U, // VPSHRDVWZ128m 132U, // VPSHRDVWZ128mk 8324U, // VPSHRDVWZ128mkz 4U, // VPSHRDVWZ128r 0U, // VPSHRDVWZ128rk 0U, // VPSHRDVWZ128rkz 4U, // VPSHRDVWZ256m 132U, // VPSHRDVWZ256mk 8324U, // VPSHRDVWZ256mkz 4U, // VPSHRDVWZ256r 0U, // VPSHRDVWZ256rk 0U, // VPSHRDVWZ256rkz 4U, // VPSHRDVWZm 132U, // VPSHRDVWZmk 8324U, // VPSHRDVWZmkz 4U, // VPSHRDVWZr 0U, // VPSHRDVWZrk 0U, // VPSHRDVWZrkz 72U, // VPSHRDWZ128rmi 1U, // VPSHRDWZ128rmik 9348U, // VPSHRDWZ128rmikz 18636U, // VPSHRDWZ128rri 25U, // VPSHRDWZ128rrik 26837U, // VPSHRDWZ128rrikz 72U, // VPSHRDWZ256rmi 1U, // VPSHRDWZ256rmik 9348U, // VPSHRDWZ256rmikz 18636U, // VPSHRDWZ256rri 25U, // VPSHRDWZ256rrik 26837U, // VPSHRDWZ256rrikz 72U, // VPSHRDWZrmi 1U, // VPSHRDWZrmik 9348U, // VPSHRDWZrmikz 18636U, // VPSHRDWZrri 25U, // VPSHRDWZrrik 26837U, // VPSHRDWZrrikz 4U, // VPSHUFBITQMBZ128rm 1156U, // VPSHUFBITQMBZ128rmk 4U, // VPSHUFBITQMBZ128rr 1156U, // VPSHUFBITQMBZ128rrk 4U, // VPSHUFBITQMBZ256rm 1156U, // VPSHUFBITQMBZ256rmk 4U, // VPSHUFBITQMBZ256rr 1156U, // VPSHUFBITQMBZ256rrk 4U, // VPSHUFBITQMBZrm 1156U, // VPSHUFBITQMBZrmk 4U, // VPSHUFBITQMBZrr 1156U, // VPSHUFBITQMBZrrk 4U, // VPSHUFBYrm 4U, // VPSHUFBYrr 4U, // VPSHUFBZ128rm 132U, // VPSHUFBZ128rmk 9348U, // VPSHUFBZ128rmkz 4U, // VPSHUFBZ128rr 0U, // VPSHUFBZ128rrk 9348U, // VPSHUFBZ128rrkz 4U, // VPSHUFBZ256rm 132U, // VPSHUFBZ256rmk 9348U, // VPSHUFBZ256rmkz 4U, // VPSHUFBZ256rr 0U, // VPSHUFBZ256rrk 9348U, // VPSHUFBZ256rrkz 4U, // VPSHUFBZrm 132U, // VPSHUFBZrmk 9348U, // VPSHUFBZrmkz 4U, // VPSHUFBZrr 0U, // VPSHUFBZrrk 9348U, // VPSHUFBZrrkz 4U, // VPSHUFBrm 4U, // VPSHUFBrr 4U, // VPSHUFDYmi 72U, // VPSHUFDYri 5U, // VPSHUFDZ128mbi 133U, // VPSHUFDZ128mbik 9349U, // VPSHUFDZ128mbikz 4U, // VPSHUFDZ128mi 3356U, // VPSHUFDZ128mik 4444U, // VPSHUFDZ128mikz 72U, // VPSHUFDZ128ri 133U, // VPSHUFDZ128rik 9348U, // VPSHUFDZ128rikz 5U, // VPSHUFDZ256mbi 133U, // VPSHUFDZ256mbik 9349U, // VPSHUFDZ256mbikz 4U, // VPSHUFDZ256mi 3356U, // VPSHUFDZ256mik 4444U, // VPSHUFDZ256mikz 72U, // VPSHUFDZ256ri 133U, // VPSHUFDZ256rik 9348U, // VPSHUFDZ256rikz 5U, // VPSHUFDZmbi 133U, // VPSHUFDZmbik 9349U, // VPSHUFDZmbikz 4U, // VPSHUFDZmi 3356U, // VPSHUFDZmik 4444U, // VPSHUFDZmikz 72U, // VPSHUFDZri 133U, // VPSHUFDZrik 9348U, // VPSHUFDZrikz 4U, // VPSHUFDmi 72U, // VPSHUFDri 4U, // VPSHUFHWYmi 72U, // VPSHUFHWYri 4U, // VPSHUFHWZ128mi 3356U, // VPSHUFHWZ128mik 4444U, // VPSHUFHWZ128mikz 72U, // VPSHUFHWZ128ri 133U, // VPSHUFHWZ128rik 9348U, // VPSHUFHWZ128rikz 4U, // VPSHUFHWZ256mi 3356U, // VPSHUFHWZ256mik 4444U, // VPSHUFHWZ256mikz 72U, // VPSHUFHWZ256ri 133U, // VPSHUFHWZ256rik 9348U, // VPSHUFHWZ256rikz 4U, // VPSHUFHWZmi 3356U, // VPSHUFHWZmik 4444U, // VPSHUFHWZmikz 72U, // VPSHUFHWZri 133U, // VPSHUFHWZrik 9348U, // VPSHUFHWZrikz 4U, // VPSHUFHWmi 72U, // VPSHUFHWri 4U, // VPSHUFLWYmi 72U, // VPSHUFLWYri 4U, // VPSHUFLWZ128mi 3356U, // VPSHUFLWZ128mik 4444U, // VPSHUFLWZ128mikz 72U, // VPSHUFLWZ128ri 133U, // VPSHUFLWZ128rik 9348U, // VPSHUFLWZ128rikz 4U, // VPSHUFLWZ256mi 3356U, // VPSHUFLWZ256mik 4444U, // VPSHUFLWZ256mikz 72U, // VPSHUFLWZ256ri 133U, // VPSHUFLWZ256rik 9348U, // VPSHUFLWZ256rikz 4U, // VPSHUFLWZmi 3356U, // VPSHUFLWZmik 4444U, // VPSHUFLWZmikz 72U, // VPSHUFLWZri 133U, // VPSHUFLWZrik 9348U, // VPSHUFLWZrikz 4U, // VPSHUFLWmi 72U, // VPSHUFLWri 4U, // VPSIGNBYrm 4U, // VPSIGNBYrr 4U, // VPSIGNBrm 4U, // VPSIGNBrr 4U, // VPSIGNDYrm 4U, // VPSIGNDYrr 4U, // VPSIGNDrm 4U, // VPSIGNDrr 4U, // VPSIGNWYrm 4U, // VPSIGNWYrr 4U, // VPSIGNWrm 4U, // VPSIGNWrr 72U, // VPSLLDQYri 4U, // VPSLLDQZ128rm 72U, // VPSLLDQZ128rr 4U, // VPSLLDQZ256rm 72U, // VPSLLDQZ256rr 4U, // VPSLLDQZrm 72U, // VPSLLDQZrr 72U, // VPSLLDQri 72U, // VPSLLDYri 4U, // VPSLLDYrm 4U, // VPSLLDYrr 5U, // VPSLLDZ128mbi 133U, // VPSLLDZ128mbik 9349U, // VPSLLDZ128mbikz 4U, // VPSLLDZ128mi 3356U, // VPSLLDZ128mik 4444U, // VPSLLDZ128mikz 72U, // VPSLLDZ128ri 133U, // VPSLLDZ128rik 9348U, // VPSLLDZ128rikz 4U, // VPSLLDZ128rm 132U, // VPSLLDZ128rmk 9348U, // VPSLLDZ128rmkz 4U, // VPSLLDZ128rr 0U, // VPSLLDZ128rrk 9348U, // VPSLLDZ128rrkz 5U, // VPSLLDZ256mbi 133U, // VPSLLDZ256mbik 9349U, // VPSLLDZ256mbikz 4U, // VPSLLDZ256mi 3356U, // VPSLLDZ256mik 4444U, // VPSLLDZ256mikz 72U, // VPSLLDZ256ri 133U, // VPSLLDZ256rik 9348U, // VPSLLDZ256rikz 4U, // VPSLLDZ256rm 132U, // VPSLLDZ256rmk 9348U, // VPSLLDZ256rmkz 4U, // VPSLLDZ256rr 0U, // VPSLLDZ256rrk 9348U, // VPSLLDZ256rrkz 5U, // VPSLLDZmbi 133U, // VPSLLDZmbik 9349U, // VPSLLDZmbikz 4U, // VPSLLDZmi 3356U, // VPSLLDZmik 4444U, // VPSLLDZmikz 72U, // VPSLLDZri 133U, // VPSLLDZrik 9348U, // VPSLLDZrikz 4U, // VPSLLDZrm 132U, // VPSLLDZrmk 9348U, // VPSLLDZrmkz 4U, // VPSLLDZrr 0U, // VPSLLDZrrk 9348U, // VPSLLDZrrkz 72U, // VPSLLDri 4U, // VPSLLDrm 4U, // VPSLLDrr 72U, // VPSLLQYri 4U, // VPSLLQYrm 4U, // VPSLLQYrr 5U, // VPSLLQZ128mbi 133U, // VPSLLQZ128mbik 9349U, // VPSLLQZ128mbikz 4U, // VPSLLQZ128mi 3356U, // VPSLLQZ128mik 4444U, // VPSLLQZ128mikz 72U, // VPSLLQZ128ri 133U, // VPSLLQZ128rik 9348U, // VPSLLQZ128rikz 4U, // VPSLLQZ128rm 132U, // VPSLLQZ128rmk 9348U, // VPSLLQZ128rmkz 4U, // VPSLLQZ128rr 0U, // VPSLLQZ128rrk 9348U, // VPSLLQZ128rrkz 5U, // VPSLLQZ256mbi 133U, // VPSLLQZ256mbik 9349U, // VPSLLQZ256mbikz 4U, // VPSLLQZ256mi 3356U, // VPSLLQZ256mik 4444U, // VPSLLQZ256mikz 72U, // VPSLLQZ256ri 133U, // VPSLLQZ256rik 9348U, // VPSLLQZ256rikz 4U, // VPSLLQZ256rm 132U, // VPSLLQZ256rmk 9348U, // VPSLLQZ256rmkz 4U, // VPSLLQZ256rr 0U, // VPSLLQZ256rrk 9348U, // VPSLLQZ256rrkz 5U, // VPSLLQZmbi 133U, // VPSLLQZmbik 9349U, // VPSLLQZmbikz 4U, // VPSLLQZmi 3356U, // VPSLLQZmik 4444U, // VPSLLQZmikz 72U, // VPSLLQZri 133U, // VPSLLQZrik 9348U, // VPSLLQZrikz 4U, // VPSLLQZrm 132U, // VPSLLQZrmk 9348U, // VPSLLQZrmkz 4U, // VPSLLQZrr 0U, // VPSLLQZrrk 9348U, // VPSLLQZrrkz 72U, // VPSLLQri 4U, // VPSLLQrm 4U, // VPSLLQrr 4U, // VPSLLVDYrm 4U, // VPSLLVDYrr 4U, // VPSLLVDZ128rm 72U, // VPSLLVDZ128rmb 133U, // VPSLLVDZ128rmbk 9348U, // VPSLLVDZ128rmbkz 132U, // VPSLLVDZ128rmk 9348U, // VPSLLVDZ128rmkz 4U, // VPSLLVDZ128rr 0U, // VPSLLVDZ128rrk 9348U, // VPSLLVDZ128rrkz 4U, // VPSLLVDZ256rm 72U, // VPSLLVDZ256rmb 133U, // VPSLLVDZ256rmbk 9348U, // VPSLLVDZ256rmbkz 132U, // VPSLLVDZ256rmk 9348U, // VPSLLVDZ256rmkz 4U, // VPSLLVDZ256rr 0U, // VPSLLVDZ256rrk 9348U, // VPSLLVDZ256rrkz 4U, // VPSLLVDZrm 72U, // VPSLLVDZrmb 133U, // VPSLLVDZrmbk 9348U, // VPSLLVDZrmbkz 132U, // VPSLLVDZrmk 9348U, // VPSLLVDZrmkz 4U, // VPSLLVDZrr 0U, // VPSLLVDZrrk 9348U, // VPSLLVDZrrkz 4U, // VPSLLVDrm 4U, // VPSLLVDrr 4U, // VPSLLVQYrm 4U, // VPSLLVQYrr 4U, // VPSLLVQZ128rm 72U, // VPSLLVQZ128rmb 133U, // VPSLLVQZ128rmbk 9348U, // VPSLLVQZ128rmbkz 132U, // VPSLLVQZ128rmk 9348U, // VPSLLVQZ128rmkz 4U, // VPSLLVQZ128rr 0U, // VPSLLVQZ128rrk 9348U, // VPSLLVQZ128rrkz 4U, // VPSLLVQZ256rm 72U, // VPSLLVQZ256rmb 133U, // VPSLLVQZ256rmbk 9348U, // VPSLLVQZ256rmbkz 132U, // VPSLLVQZ256rmk 9348U, // VPSLLVQZ256rmkz 4U, // VPSLLVQZ256rr 0U, // VPSLLVQZ256rrk 9348U, // VPSLLVQZ256rrkz 4U, // VPSLLVQZrm 72U, // VPSLLVQZrmb 133U, // VPSLLVQZrmbk 9348U, // VPSLLVQZrmbkz 132U, // VPSLLVQZrmk 9348U, // VPSLLVQZrmkz 4U, // VPSLLVQZrr 0U, // VPSLLVQZrrk 9348U, // VPSLLVQZrrkz 4U, // VPSLLVQrm 4U, // VPSLLVQrr 4U, // VPSLLVWZ128rm 132U, // VPSLLVWZ128rmk 9348U, // VPSLLVWZ128rmkz 4U, // VPSLLVWZ128rr 0U, // VPSLLVWZ128rrk 9348U, // VPSLLVWZ128rrkz 4U, // VPSLLVWZ256rm 132U, // VPSLLVWZ256rmk 9348U, // VPSLLVWZ256rmkz 4U, // VPSLLVWZ256rr 0U, // VPSLLVWZ256rrk 9348U, // VPSLLVWZ256rrkz 4U, // VPSLLVWZrm 132U, // VPSLLVWZrmk 9348U, // VPSLLVWZrmkz 4U, // VPSLLVWZrr 0U, // VPSLLVWZrrk 9348U, // VPSLLVWZrrkz 72U, // VPSLLWYri 4U, // VPSLLWYrm 4U, // VPSLLWYrr 4U, // VPSLLWZ128mi 3356U, // VPSLLWZ128mik 4444U, // VPSLLWZ128mikz 72U, // VPSLLWZ128ri 133U, // VPSLLWZ128rik 9348U, // VPSLLWZ128rikz 4U, // VPSLLWZ128rm 132U, // VPSLLWZ128rmk 9348U, // VPSLLWZ128rmkz 4U, // VPSLLWZ128rr 0U, // VPSLLWZ128rrk 9348U, // VPSLLWZ128rrkz 4U, // VPSLLWZ256mi 3356U, // VPSLLWZ256mik 4444U, // VPSLLWZ256mikz 72U, // VPSLLWZ256ri 133U, // VPSLLWZ256rik 9348U, // VPSLLWZ256rikz 4U, // VPSLLWZ256rm 132U, // VPSLLWZ256rmk 9348U, // VPSLLWZ256rmkz 4U, // VPSLLWZ256rr 0U, // VPSLLWZ256rrk 9348U, // VPSLLWZ256rrkz 4U, // VPSLLWZmi 3356U, // VPSLLWZmik 4444U, // VPSLLWZmikz 72U, // VPSLLWZri 133U, // VPSLLWZrik 9348U, // VPSLLWZrikz 4U, // VPSLLWZrm 132U, // VPSLLWZrmk 9348U, // VPSLLWZrmkz 4U, // VPSLLWZrr 0U, // VPSLLWZrrk 9348U, // VPSLLWZrrkz 72U, // VPSLLWri 4U, // VPSLLWrm 4U, // VPSLLWrr 72U, // VPSRADYri 4U, // VPSRADYrm 4U, // VPSRADYrr 5U, // VPSRADZ128mbi 133U, // VPSRADZ128mbik 9349U, // VPSRADZ128mbikz 4U, // VPSRADZ128mi 3356U, // VPSRADZ128mik 4444U, // VPSRADZ128mikz 72U, // VPSRADZ128ri 133U, // VPSRADZ128rik 9348U, // VPSRADZ128rikz 4U, // VPSRADZ128rm 132U, // VPSRADZ128rmk 9348U, // VPSRADZ128rmkz 4U, // VPSRADZ128rr 0U, // VPSRADZ128rrk 9348U, // VPSRADZ128rrkz 5U, // VPSRADZ256mbi 133U, // VPSRADZ256mbik 9349U, // VPSRADZ256mbikz 4U, // VPSRADZ256mi 3356U, // VPSRADZ256mik 4444U, // VPSRADZ256mikz 72U, // VPSRADZ256ri 133U, // VPSRADZ256rik 9348U, // VPSRADZ256rikz 4U, // VPSRADZ256rm 132U, // VPSRADZ256rmk 9348U, // VPSRADZ256rmkz 4U, // VPSRADZ256rr 0U, // VPSRADZ256rrk 9348U, // VPSRADZ256rrkz 5U, // VPSRADZmbi 133U, // VPSRADZmbik 9349U, // VPSRADZmbikz 4U, // VPSRADZmi 3356U, // VPSRADZmik 4444U, // VPSRADZmikz 72U, // VPSRADZri 133U, // VPSRADZrik 9348U, // VPSRADZrikz 4U, // VPSRADZrm 132U, // VPSRADZrmk 9348U, // VPSRADZrmkz 4U, // VPSRADZrr 0U, // VPSRADZrrk 9348U, // VPSRADZrrkz 72U, // VPSRADri 4U, // VPSRADrm 4U, // VPSRADrr 5U, // VPSRAQZ128mbi 133U, // VPSRAQZ128mbik 9349U, // VPSRAQZ128mbikz 4U, // VPSRAQZ128mi 3356U, // VPSRAQZ128mik 4444U, // VPSRAQZ128mikz 72U, // VPSRAQZ128ri 133U, // VPSRAQZ128rik 9348U, // VPSRAQZ128rikz 4U, // VPSRAQZ128rm 132U, // VPSRAQZ128rmk 9348U, // VPSRAQZ128rmkz 4U, // VPSRAQZ128rr 0U, // VPSRAQZ128rrk 9348U, // VPSRAQZ128rrkz 5U, // VPSRAQZ256mbi 133U, // VPSRAQZ256mbik 9349U, // VPSRAQZ256mbikz 4U, // VPSRAQZ256mi 3356U, // VPSRAQZ256mik 4444U, // VPSRAQZ256mikz 72U, // VPSRAQZ256ri 133U, // VPSRAQZ256rik 9348U, // VPSRAQZ256rikz 4U, // VPSRAQZ256rm 132U, // VPSRAQZ256rmk 9348U, // VPSRAQZ256rmkz 4U, // VPSRAQZ256rr 0U, // VPSRAQZ256rrk 9348U, // VPSRAQZ256rrkz 5U, // VPSRAQZmbi 133U, // VPSRAQZmbik 9349U, // VPSRAQZmbikz 4U, // VPSRAQZmi 3356U, // VPSRAQZmik 4444U, // VPSRAQZmikz 72U, // VPSRAQZri 133U, // VPSRAQZrik 9348U, // VPSRAQZrikz 4U, // VPSRAQZrm 132U, // VPSRAQZrmk 9348U, // VPSRAQZrmkz 4U, // VPSRAQZrr 0U, // VPSRAQZrrk 9348U, // VPSRAQZrrkz 4U, // VPSRAVDYrm 4U, // VPSRAVDYrr 4U, // VPSRAVDZ128rm 72U, // VPSRAVDZ128rmb 133U, // VPSRAVDZ128rmbk 9348U, // VPSRAVDZ128rmbkz 132U, // VPSRAVDZ128rmk 9348U, // VPSRAVDZ128rmkz 4U, // VPSRAVDZ128rr 0U, // VPSRAVDZ128rrk 9348U, // VPSRAVDZ128rrkz 4U, // VPSRAVDZ256rm 72U, // VPSRAVDZ256rmb 133U, // VPSRAVDZ256rmbk 9348U, // VPSRAVDZ256rmbkz 132U, // VPSRAVDZ256rmk 9348U, // VPSRAVDZ256rmkz 4U, // VPSRAVDZ256rr 0U, // VPSRAVDZ256rrk 9348U, // VPSRAVDZ256rrkz 4U, // VPSRAVDZrm 72U, // VPSRAVDZrmb 133U, // VPSRAVDZrmbk 9348U, // VPSRAVDZrmbkz 132U, // VPSRAVDZrmk 9348U, // VPSRAVDZrmkz 4U, // VPSRAVDZrr 0U, // VPSRAVDZrrk 9348U, // VPSRAVDZrrkz 4U, // VPSRAVDrm 4U, // VPSRAVDrr 4U, // VPSRAVQZ128rm 72U, // VPSRAVQZ128rmb 133U, // VPSRAVQZ128rmbk 9348U, // VPSRAVQZ128rmbkz 132U, // VPSRAVQZ128rmk 9348U, // VPSRAVQZ128rmkz 4U, // VPSRAVQZ128rr 0U, // VPSRAVQZ128rrk 9348U, // VPSRAVQZ128rrkz 4U, // VPSRAVQZ256rm 72U, // VPSRAVQZ256rmb 133U, // VPSRAVQZ256rmbk 9348U, // VPSRAVQZ256rmbkz 132U, // VPSRAVQZ256rmk 9348U, // VPSRAVQZ256rmkz 4U, // VPSRAVQZ256rr 0U, // VPSRAVQZ256rrk 9348U, // VPSRAVQZ256rrkz 4U, // VPSRAVQZrm 72U, // VPSRAVQZrmb 133U, // VPSRAVQZrmbk 9348U, // VPSRAVQZrmbkz 132U, // VPSRAVQZrmk 9348U, // VPSRAVQZrmkz 4U, // VPSRAVQZrr 0U, // VPSRAVQZrrk 9348U, // VPSRAVQZrrkz 4U, // VPSRAVWZ128rm 132U, // VPSRAVWZ128rmk 9348U, // VPSRAVWZ128rmkz 4U, // VPSRAVWZ128rr 0U, // VPSRAVWZ128rrk 9348U, // VPSRAVWZ128rrkz 4U, // VPSRAVWZ256rm 132U, // VPSRAVWZ256rmk 9348U, // VPSRAVWZ256rmkz 4U, // VPSRAVWZ256rr 0U, // VPSRAVWZ256rrk 9348U, // VPSRAVWZ256rrkz 4U, // VPSRAVWZrm 132U, // VPSRAVWZrmk 9348U, // VPSRAVWZrmkz 4U, // VPSRAVWZrr 0U, // VPSRAVWZrrk 9348U, // VPSRAVWZrrkz 72U, // VPSRAWYri 4U, // VPSRAWYrm 4U, // VPSRAWYrr 4U, // VPSRAWZ128mi 3356U, // VPSRAWZ128mik 4444U, // VPSRAWZ128mikz 72U, // VPSRAWZ128ri 133U, // VPSRAWZ128rik 9348U, // VPSRAWZ128rikz 4U, // VPSRAWZ128rm 132U, // VPSRAWZ128rmk 9348U, // VPSRAWZ128rmkz 4U, // VPSRAWZ128rr 0U, // VPSRAWZ128rrk 9348U, // VPSRAWZ128rrkz 4U, // VPSRAWZ256mi 3356U, // VPSRAWZ256mik 4444U, // VPSRAWZ256mikz 72U, // VPSRAWZ256ri 133U, // VPSRAWZ256rik 9348U, // VPSRAWZ256rikz 4U, // VPSRAWZ256rm 132U, // VPSRAWZ256rmk 9348U, // VPSRAWZ256rmkz 4U, // VPSRAWZ256rr 0U, // VPSRAWZ256rrk 9348U, // VPSRAWZ256rrkz 4U, // VPSRAWZmi 3356U, // VPSRAWZmik 4444U, // VPSRAWZmikz 72U, // VPSRAWZri 133U, // VPSRAWZrik 9348U, // VPSRAWZrikz 4U, // VPSRAWZrm 132U, // VPSRAWZrmk 9348U, // VPSRAWZrmkz 4U, // VPSRAWZrr 0U, // VPSRAWZrrk 9348U, // VPSRAWZrrkz 72U, // VPSRAWri 4U, // VPSRAWrm 4U, // VPSRAWrr 72U, // VPSRLDQYri 4U, // VPSRLDQZ128rm 72U, // VPSRLDQZ128rr 4U, // VPSRLDQZ256rm 72U, // VPSRLDQZ256rr 4U, // VPSRLDQZrm 72U, // VPSRLDQZrr 72U, // VPSRLDQri 72U, // VPSRLDYri 4U, // VPSRLDYrm 4U, // VPSRLDYrr 5U, // VPSRLDZ128mbi 133U, // VPSRLDZ128mbik 9349U, // VPSRLDZ128mbikz 4U, // VPSRLDZ128mi 3356U, // VPSRLDZ128mik 4444U, // VPSRLDZ128mikz 72U, // VPSRLDZ128ri 133U, // VPSRLDZ128rik 9348U, // VPSRLDZ128rikz 4U, // VPSRLDZ128rm 132U, // VPSRLDZ128rmk 9348U, // VPSRLDZ128rmkz 4U, // VPSRLDZ128rr 0U, // VPSRLDZ128rrk 9348U, // VPSRLDZ128rrkz 5U, // VPSRLDZ256mbi 133U, // VPSRLDZ256mbik 9349U, // VPSRLDZ256mbikz 4U, // VPSRLDZ256mi 3356U, // VPSRLDZ256mik 4444U, // VPSRLDZ256mikz 72U, // VPSRLDZ256ri 133U, // VPSRLDZ256rik 9348U, // VPSRLDZ256rikz 4U, // VPSRLDZ256rm 132U, // VPSRLDZ256rmk 9348U, // VPSRLDZ256rmkz 4U, // VPSRLDZ256rr 0U, // VPSRLDZ256rrk 9348U, // VPSRLDZ256rrkz 5U, // VPSRLDZmbi 133U, // VPSRLDZmbik 9349U, // VPSRLDZmbikz 4U, // VPSRLDZmi 3356U, // VPSRLDZmik 4444U, // VPSRLDZmikz 72U, // VPSRLDZri 133U, // VPSRLDZrik 9348U, // VPSRLDZrikz 4U, // VPSRLDZrm 132U, // VPSRLDZrmk 9348U, // VPSRLDZrmkz 4U, // VPSRLDZrr 0U, // VPSRLDZrrk 9348U, // VPSRLDZrrkz 72U, // VPSRLDri 4U, // VPSRLDrm 4U, // VPSRLDrr 72U, // VPSRLQYri 4U, // VPSRLQYrm 4U, // VPSRLQYrr 5U, // VPSRLQZ128mbi 133U, // VPSRLQZ128mbik 9349U, // VPSRLQZ128mbikz 4U, // VPSRLQZ128mi 3356U, // VPSRLQZ128mik 4444U, // VPSRLQZ128mikz 72U, // VPSRLQZ128ri 133U, // VPSRLQZ128rik 9348U, // VPSRLQZ128rikz 4U, // VPSRLQZ128rm 132U, // VPSRLQZ128rmk 9348U, // VPSRLQZ128rmkz 4U, // VPSRLQZ128rr 0U, // VPSRLQZ128rrk 9348U, // VPSRLQZ128rrkz 5U, // VPSRLQZ256mbi 133U, // VPSRLQZ256mbik 9349U, // VPSRLQZ256mbikz 4U, // VPSRLQZ256mi 3356U, // VPSRLQZ256mik 4444U, // VPSRLQZ256mikz 72U, // VPSRLQZ256ri 133U, // VPSRLQZ256rik 9348U, // VPSRLQZ256rikz 4U, // VPSRLQZ256rm 132U, // VPSRLQZ256rmk 9348U, // VPSRLQZ256rmkz 4U, // VPSRLQZ256rr 0U, // VPSRLQZ256rrk 9348U, // VPSRLQZ256rrkz 5U, // VPSRLQZmbi 133U, // VPSRLQZmbik 9349U, // VPSRLQZmbikz 4U, // VPSRLQZmi 3356U, // VPSRLQZmik 4444U, // VPSRLQZmikz 72U, // VPSRLQZri 133U, // VPSRLQZrik 9348U, // VPSRLQZrikz 4U, // VPSRLQZrm 132U, // VPSRLQZrmk 9348U, // VPSRLQZrmkz 4U, // VPSRLQZrr 0U, // VPSRLQZrrk 9348U, // VPSRLQZrrkz 72U, // VPSRLQri 4U, // VPSRLQrm 4U, // VPSRLQrr 4U, // VPSRLVDYrm 4U, // VPSRLVDYrr 4U, // VPSRLVDZ128rm 72U, // VPSRLVDZ128rmb 133U, // VPSRLVDZ128rmbk 9348U, // VPSRLVDZ128rmbkz 132U, // VPSRLVDZ128rmk 9348U, // VPSRLVDZ128rmkz 4U, // VPSRLVDZ128rr 0U, // VPSRLVDZ128rrk 9348U, // VPSRLVDZ128rrkz 4U, // VPSRLVDZ256rm 72U, // VPSRLVDZ256rmb 133U, // VPSRLVDZ256rmbk 9348U, // VPSRLVDZ256rmbkz 132U, // VPSRLVDZ256rmk 9348U, // VPSRLVDZ256rmkz 4U, // VPSRLVDZ256rr 0U, // VPSRLVDZ256rrk 9348U, // VPSRLVDZ256rrkz 4U, // VPSRLVDZrm 72U, // VPSRLVDZrmb 133U, // VPSRLVDZrmbk 9348U, // VPSRLVDZrmbkz 132U, // VPSRLVDZrmk 9348U, // VPSRLVDZrmkz 4U, // VPSRLVDZrr 0U, // VPSRLVDZrrk 9348U, // VPSRLVDZrrkz 4U, // VPSRLVDrm 4U, // VPSRLVDrr 4U, // VPSRLVQYrm 4U, // VPSRLVQYrr 4U, // VPSRLVQZ128rm 72U, // VPSRLVQZ128rmb 133U, // VPSRLVQZ128rmbk 9348U, // VPSRLVQZ128rmbkz 132U, // VPSRLVQZ128rmk 9348U, // VPSRLVQZ128rmkz 4U, // VPSRLVQZ128rr 0U, // VPSRLVQZ128rrk 9348U, // VPSRLVQZ128rrkz 4U, // VPSRLVQZ256rm 72U, // VPSRLVQZ256rmb 133U, // VPSRLVQZ256rmbk 9348U, // VPSRLVQZ256rmbkz 132U, // VPSRLVQZ256rmk 9348U, // VPSRLVQZ256rmkz 4U, // VPSRLVQZ256rr 0U, // VPSRLVQZ256rrk 9348U, // VPSRLVQZ256rrkz 4U, // VPSRLVQZrm 72U, // VPSRLVQZrmb 133U, // VPSRLVQZrmbk 9348U, // VPSRLVQZrmbkz 132U, // VPSRLVQZrmk 9348U, // VPSRLVQZrmkz 4U, // VPSRLVQZrr 0U, // VPSRLVQZrrk 9348U, // VPSRLVQZrrkz 4U, // VPSRLVQrm 4U, // VPSRLVQrr 4U, // VPSRLVWZ128rm 132U, // VPSRLVWZ128rmk 9348U, // VPSRLVWZ128rmkz 4U, // VPSRLVWZ128rr 0U, // VPSRLVWZ128rrk 9348U, // VPSRLVWZ128rrkz 4U, // VPSRLVWZ256rm 132U, // VPSRLVWZ256rmk 9348U, // VPSRLVWZ256rmkz 4U, // VPSRLVWZ256rr 0U, // VPSRLVWZ256rrk 9348U, // VPSRLVWZ256rrkz 4U, // VPSRLVWZrm 132U, // VPSRLVWZrmk 9348U, // VPSRLVWZrmkz 4U, // VPSRLVWZrr 0U, // VPSRLVWZrrk 9348U, // VPSRLVWZrrkz 72U, // VPSRLWYri 4U, // VPSRLWYrm 4U, // VPSRLWYrr 4U, // VPSRLWZ128mi 3356U, // VPSRLWZ128mik 4444U, // VPSRLWZ128mikz 72U, // VPSRLWZ128ri 133U, // VPSRLWZ128rik 9348U, // VPSRLWZ128rikz 4U, // VPSRLWZ128rm 132U, // VPSRLWZ128rmk 9348U, // VPSRLWZ128rmkz 4U, // VPSRLWZ128rr 0U, // VPSRLWZ128rrk 9348U, // VPSRLWZ128rrkz 4U, // VPSRLWZ256mi 3356U, // VPSRLWZ256mik 4444U, // VPSRLWZ256mikz 72U, // VPSRLWZ256ri 133U, // VPSRLWZ256rik 9348U, // VPSRLWZ256rikz 4U, // VPSRLWZ256rm 132U, // VPSRLWZ256rmk 9348U, // VPSRLWZ256rmkz 4U, // VPSRLWZ256rr 0U, // VPSRLWZ256rrk 9348U, // VPSRLWZ256rrkz 4U, // VPSRLWZmi 3356U, // VPSRLWZmik 4444U, // VPSRLWZmikz 72U, // VPSRLWZri 133U, // VPSRLWZrik 9348U, // VPSRLWZrikz 4U, // VPSRLWZrm 132U, // VPSRLWZrmk 9348U, // VPSRLWZrmkz 4U, // VPSRLWZrr 0U, // VPSRLWZrrk 9348U, // VPSRLWZrrkz 72U, // VPSRLWri 4U, // VPSRLWrm 4U, // VPSRLWrr 4U, // VPSUBBYrm 4U, // VPSUBBYrr 4U, // VPSUBBZ128rm 132U, // VPSUBBZ128rmk 9348U, // VPSUBBZ128rmkz 4U, // VPSUBBZ128rr 0U, // VPSUBBZ128rrk 9348U, // VPSUBBZ128rrkz 4U, // VPSUBBZ256rm 132U, // VPSUBBZ256rmk 9348U, // VPSUBBZ256rmkz 4U, // VPSUBBZ256rr 0U, // VPSUBBZ256rrk 9348U, // VPSUBBZ256rrkz 4U, // VPSUBBZrm 132U, // VPSUBBZrmk 9348U, // VPSUBBZrmkz 4U, // VPSUBBZrr 0U, // VPSUBBZrrk 9348U, // VPSUBBZrrkz 4U, // VPSUBBrm 4U, // VPSUBBrr 4U, // VPSUBDYrm 4U, // VPSUBDYrr 4U, // VPSUBDZ128rm 72U, // VPSUBDZ128rmb 133U, // VPSUBDZ128rmbk 9348U, // VPSUBDZ128rmbkz 132U, // VPSUBDZ128rmk 9348U, // VPSUBDZ128rmkz 4U, // VPSUBDZ128rr 0U, // VPSUBDZ128rrk 9348U, // VPSUBDZ128rrkz 4U, // VPSUBDZ256rm 72U, // VPSUBDZ256rmb 133U, // VPSUBDZ256rmbk 9348U, // VPSUBDZ256rmbkz 132U, // VPSUBDZ256rmk 9348U, // VPSUBDZ256rmkz 4U, // VPSUBDZ256rr 0U, // VPSUBDZ256rrk 9348U, // VPSUBDZ256rrkz 4U, // VPSUBDZrm 72U, // VPSUBDZrmb 133U, // VPSUBDZrmbk 9348U, // VPSUBDZrmbkz 132U, // VPSUBDZrmk 9348U, // VPSUBDZrmkz 4U, // VPSUBDZrr 0U, // VPSUBDZrrk 9348U, // VPSUBDZrrkz 4U, // VPSUBDrm 4U, // VPSUBDrr 4U, // VPSUBQYrm 4U, // VPSUBQYrr 4U, // VPSUBQZ128rm 72U, // VPSUBQZ128rmb 133U, // VPSUBQZ128rmbk 9348U, // VPSUBQZ128rmbkz 132U, // VPSUBQZ128rmk 9348U, // VPSUBQZ128rmkz 4U, // VPSUBQZ128rr 0U, // VPSUBQZ128rrk 9348U, // VPSUBQZ128rrkz 4U, // VPSUBQZ256rm 72U, // VPSUBQZ256rmb 133U, // VPSUBQZ256rmbk 9348U, // VPSUBQZ256rmbkz 132U, // VPSUBQZ256rmk 9348U, // VPSUBQZ256rmkz 4U, // VPSUBQZ256rr 0U, // VPSUBQZ256rrk 9348U, // VPSUBQZ256rrkz 4U, // VPSUBQZrm 72U, // VPSUBQZrmb 133U, // VPSUBQZrmbk 9348U, // VPSUBQZrmbkz 132U, // VPSUBQZrmk 9348U, // VPSUBQZrmkz 4U, // VPSUBQZrr 0U, // VPSUBQZrrk 9348U, // VPSUBQZrrkz 4U, // VPSUBQrm 4U, // VPSUBQrr 4U, // VPSUBSBYrm 4U, // VPSUBSBYrr 4U, // VPSUBSBZ128rm 132U, // VPSUBSBZ128rmk 9348U, // VPSUBSBZ128rmkz 4U, // VPSUBSBZ128rr 0U, // VPSUBSBZ128rrk 9348U, // VPSUBSBZ128rrkz 4U, // VPSUBSBZ256rm 132U, // VPSUBSBZ256rmk 9348U, // VPSUBSBZ256rmkz 4U, // VPSUBSBZ256rr 0U, // VPSUBSBZ256rrk 9348U, // VPSUBSBZ256rrkz 4U, // VPSUBSBZrm 132U, // VPSUBSBZrmk 9348U, // VPSUBSBZrmkz 4U, // VPSUBSBZrr 0U, // VPSUBSBZrrk 9348U, // VPSUBSBZrrkz 4U, // VPSUBSBrm 4U, // VPSUBSBrr 4U, // VPSUBSWYrm 4U, // VPSUBSWYrr 4U, // VPSUBSWZ128rm 132U, // VPSUBSWZ128rmk 9348U, // VPSUBSWZ128rmkz 4U, // VPSUBSWZ128rr 0U, // VPSUBSWZ128rrk 9348U, // VPSUBSWZ128rrkz 4U, // VPSUBSWZ256rm 132U, // VPSUBSWZ256rmk 9348U, // VPSUBSWZ256rmkz 4U, // VPSUBSWZ256rr 0U, // VPSUBSWZ256rrk 9348U, // VPSUBSWZ256rrkz 4U, // VPSUBSWZrm 132U, // VPSUBSWZrmk 9348U, // VPSUBSWZrmkz 4U, // VPSUBSWZrr 0U, // VPSUBSWZrrk 9348U, // VPSUBSWZrrkz 4U, // VPSUBSWrm 4U, // VPSUBSWrr 4U, // VPSUBUSBYrm 4U, // VPSUBUSBYrr 4U, // VPSUBUSBZ128rm 132U, // VPSUBUSBZ128rmk 9348U, // VPSUBUSBZ128rmkz 4U, // VPSUBUSBZ128rr 0U, // VPSUBUSBZ128rrk 9348U, // VPSUBUSBZ128rrkz 4U, // VPSUBUSBZ256rm 132U, // VPSUBUSBZ256rmk 9348U, // VPSUBUSBZ256rmkz 4U, // VPSUBUSBZ256rr 0U, // VPSUBUSBZ256rrk 9348U, // VPSUBUSBZ256rrkz 4U, // VPSUBUSBZrm 132U, // VPSUBUSBZrmk 9348U, // VPSUBUSBZrmkz 4U, // VPSUBUSBZrr 0U, // VPSUBUSBZrrk 9348U, // VPSUBUSBZrrkz 4U, // VPSUBUSBrm 4U, // VPSUBUSBrr 4U, // VPSUBUSWYrm 4U, // VPSUBUSWYrr 4U, // VPSUBUSWZ128rm 132U, // VPSUBUSWZ128rmk 9348U, // VPSUBUSWZ128rmkz 4U, // VPSUBUSWZ128rr 0U, // VPSUBUSWZ128rrk 9348U, // VPSUBUSWZ128rrkz 4U, // VPSUBUSWZ256rm 132U, // VPSUBUSWZ256rmk 9348U, // VPSUBUSWZ256rmkz 4U, // VPSUBUSWZ256rr 0U, // VPSUBUSWZ256rrk 9348U, // VPSUBUSWZ256rrkz 4U, // VPSUBUSWZrm 132U, // VPSUBUSWZrmk 9348U, // VPSUBUSWZrmkz 4U, // VPSUBUSWZrr 0U, // VPSUBUSWZrrk 9348U, // VPSUBUSWZrrkz 4U, // VPSUBUSWrm 4U, // VPSUBUSWrr 4U, // VPSUBWYrm 4U, // VPSUBWYrr 4U, // VPSUBWZ128rm 132U, // VPSUBWZ128rmk 9348U, // VPSUBWZ128rmkz 4U, // VPSUBWZ128rr 0U, // VPSUBWZ128rrk 9348U, // VPSUBWZ128rrkz 4U, // VPSUBWZ256rm 132U, // VPSUBWZ256rmk 9348U, // VPSUBWZ256rmkz 4U, // VPSUBWZ256rr 0U, // VPSUBWZ256rrk 9348U, // VPSUBWZ256rrkz 4U, // VPSUBWZrm 132U, // VPSUBWZrmk 9348U, // VPSUBWZrmkz 4U, // VPSUBWZrr 0U, // VPSUBWZrrk 9348U, // VPSUBWZrrkz 4U, // VPSUBWrm 4U, // VPSUBWrr 18645U, // VPTERNLOGDZ128rmbi 26833U, // VPTERNLOGDZ128rmbik 26833U, // VPTERNLOGDZ128rmbikz 4U, // VPTERNLOGDZ128rmi 1U, // VPTERNLOGDZ128rmik 2U, // VPTERNLOGDZ128rmikz 18645U, // VPTERNLOGDZ128rri 25U, // VPTERNLOGDZ128rrik 53U, // VPTERNLOGDZ128rrikz 18645U, // VPTERNLOGDZ256rmbi 26833U, // VPTERNLOGDZ256rmbik 26833U, // VPTERNLOGDZ256rmbikz 4U, // VPTERNLOGDZ256rmi 1U, // VPTERNLOGDZ256rmik 2U, // VPTERNLOGDZ256rmikz 18645U, // VPTERNLOGDZ256rri 25U, // VPTERNLOGDZ256rrik 53U, // VPTERNLOGDZ256rrikz 18645U, // VPTERNLOGDZrmbi 26833U, // VPTERNLOGDZrmbik 26833U, // VPTERNLOGDZrmbikz 4U, // VPTERNLOGDZrmi 1U, // VPTERNLOGDZrmik 2U, // VPTERNLOGDZrmikz 18645U, // VPTERNLOGDZrri 25U, // VPTERNLOGDZrrik 53U, // VPTERNLOGDZrrikz 18645U, // VPTERNLOGQZ128rmbi 26833U, // VPTERNLOGQZ128rmbik 26833U, // VPTERNLOGQZ128rmbikz 4U, // VPTERNLOGQZ128rmi 1U, // VPTERNLOGQZ128rmik 2U, // VPTERNLOGQZ128rmikz 18645U, // VPTERNLOGQZ128rri 25U, // VPTERNLOGQZ128rrik 53U, // VPTERNLOGQZ128rrikz 18645U, // VPTERNLOGQZ256rmbi 26833U, // VPTERNLOGQZ256rmbik 26833U, // VPTERNLOGQZ256rmbikz 4U, // VPTERNLOGQZ256rmi 1U, // VPTERNLOGQZ256rmik 2U, // VPTERNLOGQZ256rmikz 18645U, // VPTERNLOGQZ256rri 25U, // VPTERNLOGQZ256rrik 53U, // VPTERNLOGQZ256rrikz 18645U, // VPTERNLOGQZrmbi 26833U, // VPTERNLOGQZrmbik 26833U, // VPTERNLOGQZrmbikz 4U, // VPTERNLOGQZrmi 1U, // VPTERNLOGQZrmik 2U, // VPTERNLOGQZrmikz 18645U, // VPTERNLOGQZrri 25U, // VPTERNLOGQZrrik 53U, // VPTERNLOGQZrrikz 4U, // VPTESTMBZ128rm 1156U, // VPTESTMBZ128rmk 4U, // VPTESTMBZ128rr 1156U, // VPTESTMBZ128rrk 4U, // VPTESTMBZ256rm 1156U, // VPTESTMBZ256rmk 4U, // VPTESTMBZ256rr 1156U, // VPTESTMBZ256rrk 4U, // VPTESTMBZrm 1156U, // VPTESTMBZrmk 4U, // VPTESTMBZrr 1156U, // VPTESTMBZrrk 4U, // VPTESTMDZ128rm 72U, // VPTESTMDZ128rmb 1156U, // VPTESTMDZ128rmbk 1156U, // VPTESTMDZ128rmk 4U, // VPTESTMDZ128rr 1156U, // VPTESTMDZ128rrk 4U, // VPTESTMDZ256rm 72U, // VPTESTMDZ256rmb 1156U, // VPTESTMDZ256rmbk 1156U, // VPTESTMDZ256rmk 4U, // VPTESTMDZ256rr 1156U, // VPTESTMDZ256rrk 4U, // VPTESTMDZrm 72U, // VPTESTMDZrmb 1156U, // VPTESTMDZrmbk 1156U, // VPTESTMDZrmk 4U, // VPTESTMDZrr 1156U, // VPTESTMDZrrk 4U, // VPTESTMQZ128rm 72U, // VPTESTMQZ128rmb 1156U, // VPTESTMQZ128rmbk 1156U, // VPTESTMQZ128rmk 4U, // VPTESTMQZ128rr 1156U, // VPTESTMQZ128rrk 4U, // VPTESTMQZ256rm 72U, // VPTESTMQZ256rmb 1156U, // VPTESTMQZ256rmbk 1156U, // VPTESTMQZ256rmk 4U, // VPTESTMQZ256rr 1156U, // VPTESTMQZ256rrk 4U, // VPTESTMQZrm 72U, // VPTESTMQZrmb 1156U, // VPTESTMQZrmbk 1156U, // VPTESTMQZrmk 4U, // VPTESTMQZrr 1156U, // VPTESTMQZrrk 4U, // VPTESTMWZ128rm 1156U, // VPTESTMWZ128rmk 4U, // VPTESTMWZ128rr 1156U, // VPTESTMWZ128rrk 4U, // VPTESTMWZ256rm 1156U, // VPTESTMWZ256rmk 4U, // VPTESTMWZ256rr 1156U, // VPTESTMWZ256rrk 4U, // VPTESTMWZrm 1156U, // VPTESTMWZrmk 4U, // VPTESTMWZrr 1156U, // VPTESTMWZrrk 4U, // VPTESTNMBZ128rm 1156U, // VPTESTNMBZ128rmk 4U, // VPTESTNMBZ128rr 1156U, // VPTESTNMBZ128rrk 4U, // VPTESTNMBZ256rm 1156U, // VPTESTNMBZ256rmk 4U, // VPTESTNMBZ256rr 1156U, // VPTESTNMBZ256rrk 4U, // VPTESTNMBZrm 1156U, // VPTESTNMBZrmk 4U, // VPTESTNMBZrr 1156U, // VPTESTNMBZrrk 4U, // VPTESTNMDZ128rm 72U, // VPTESTNMDZ128rmb 1156U, // VPTESTNMDZ128rmbk 1156U, // VPTESTNMDZ128rmk 4U, // VPTESTNMDZ128rr 1156U, // VPTESTNMDZ128rrk 4U, // VPTESTNMDZ256rm 72U, // VPTESTNMDZ256rmb 1156U, // VPTESTNMDZ256rmbk 1156U, // VPTESTNMDZ256rmk 4U, // VPTESTNMDZ256rr 1156U, // VPTESTNMDZ256rrk 4U, // VPTESTNMDZrm 72U, // VPTESTNMDZrmb 1156U, // VPTESTNMDZrmbk 1156U, // VPTESTNMDZrmk 4U, // VPTESTNMDZrr 1156U, // VPTESTNMDZrrk 4U, // VPTESTNMQZ128rm 72U, // VPTESTNMQZ128rmb 1156U, // VPTESTNMQZ128rmbk 1156U, // VPTESTNMQZ128rmk 4U, // VPTESTNMQZ128rr 1156U, // VPTESTNMQZ128rrk 4U, // VPTESTNMQZ256rm 72U, // VPTESTNMQZ256rmb 1156U, // VPTESTNMQZ256rmbk 1156U, // VPTESTNMQZ256rmk 4U, // VPTESTNMQZ256rr 1156U, // VPTESTNMQZ256rrk 4U, // VPTESTNMQZrm 72U, // VPTESTNMQZrmb 1156U, // VPTESTNMQZrmbk 1156U, // VPTESTNMQZrmk 4U, // VPTESTNMQZrr 1156U, // VPTESTNMQZrrk 4U, // VPTESTNMWZ128rm 1156U, // VPTESTNMWZ128rmk 4U, // VPTESTNMWZ128rr 1156U, // VPTESTNMWZ128rrk 4U, // VPTESTNMWZ256rm 1156U, // VPTESTNMWZ256rmk 4U, // VPTESTNMWZ256rr 1156U, // VPTESTNMWZ256rrk 4U, // VPTESTNMWZrm 1156U, // VPTESTNMWZrmk 4U, // VPTESTNMWZrr 1156U, // VPTESTNMWZrrk 0U, // VPTESTYrm 0U, // VPTESTYrr 0U, // VPTESTrm 0U, // VPTESTrr 4U, // VPUNPCKHBWYrm 4U, // VPUNPCKHBWYrr 4U, // VPUNPCKHBWZ128rm 132U, // VPUNPCKHBWZ128rmk 9348U, // VPUNPCKHBWZ128rmkz 4U, // VPUNPCKHBWZ128rr 0U, // VPUNPCKHBWZ128rrk 9348U, // VPUNPCKHBWZ128rrkz 4U, // VPUNPCKHBWZ256rm 132U, // VPUNPCKHBWZ256rmk 9348U, // VPUNPCKHBWZ256rmkz 4U, // VPUNPCKHBWZ256rr 0U, // VPUNPCKHBWZ256rrk 9348U, // VPUNPCKHBWZ256rrkz 4U, // VPUNPCKHBWZrm 132U, // VPUNPCKHBWZrmk 9348U, // VPUNPCKHBWZrmkz 4U, // VPUNPCKHBWZrr 0U, // VPUNPCKHBWZrrk 9348U, // VPUNPCKHBWZrrkz 4U, // VPUNPCKHBWrm 4U, // VPUNPCKHBWrr 4U, // VPUNPCKHDQYrm 4U, // VPUNPCKHDQYrr 4U, // VPUNPCKHDQZ128rm 72U, // VPUNPCKHDQZ128rmb 133U, // VPUNPCKHDQZ128rmbk 9348U, // VPUNPCKHDQZ128rmbkz 132U, // VPUNPCKHDQZ128rmk 9348U, // VPUNPCKHDQZ128rmkz 4U, // VPUNPCKHDQZ128rr 0U, // VPUNPCKHDQZ128rrk 9348U, // VPUNPCKHDQZ128rrkz 4U, // VPUNPCKHDQZ256rm 72U, // VPUNPCKHDQZ256rmb 133U, // VPUNPCKHDQZ256rmbk 9348U, // VPUNPCKHDQZ256rmbkz 132U, // VPUNPCKHDQZ256rmk 9348U, // VPUNPCKHDQZ256rmkz 4U, // VPUNPCKHDQZ256rr 0U, // VPUNPCKHDQZ256rrk 9348U, // VPUNPCKHDQZ256rrkz 4U, // VPUNPCKHDQZrm 72U, // VPUNPCKHDQZrmb 133U, // VPUNPCKHDQZrmbk 9348U, // VPUNPCKHDQZrmbkz 132U, // VPUNPCKHDQZrmk 9348U, // VPUNPCKHDQZrmkz 4U, // VPUNPCKHDQZrr 0U, // VPUNPCKHDQZrrk 9348U, // VPUNPCKHDQZrrkz 4U, // VPUNPCKHDQrm 4U, // VPUNPCKHDQrr 4U, // VPUNPCKHQDQYrm 4U, // VPUNPCKHQDQYrr 4U, // VPUNPCKHQDQZ128rm 72U, // VPUNPCKHQDQZ128rmb 133U, // VPUNPCKHQDQZ128rmbk 9348U, // VPUNPCKHQDQZ128rmbkz 132U, // VPUNPCKHQDQZ128rmk 9348U, // VPUNPCKHQDQZ128rmkz 4U, // VPUNPCKHQDQZ128rr 0U, // VPUNPCKHQDQZ128rrk 9348U, // VPUNPCKHQDQZ128rrkz 4U, // VPUNPCKHQDQZ256rm 72U, // VPUNPCKHQDQZ256rmb 133U, // VPUNPCKHQDQZ256rmbk 9348U, // VPUNPCKHQDQZ256rmbkz 132U, // VPUNPCKHQDQZ256rmk 9348U, // VPUNPCKHQDQZ256rmkz 4U, // VPUNPCKHQDQZ256rr 0U, // VPUNPCKHQDQZ256rrk 9348U, // VPUNPCKHQDQZ256rrkz 4U, // VPUNPCKHQDQZrm 72U, // VPUNPCKHQDQZrmb 133U, // VPUNPCKHQDQZrmbk 9348U, // VPUNPCKHQDQZrmbkz 132U, // VPUNPCKHQDQZrmk 9348U, // VPUNPCKHQDQZrmkz 4U, // VPUNPCKHQDQZrr 0U, // VPUNPCKHQDQZrrk 9348U, // VPUNPCKHQDQZrrkz 4U, // VPUNPCKHQDQrm 4U, // VPUNPCKHQDQrr 4U, // VPUNPCKHWDYrm 4U, // VPUNPCKHWDYrr 4U, // VPUNPCKHWDZ128rm 132U, // VPUNPCKHWDZ128rmk 9348U, // VPUNPCKHWDZ128rmkz 4U, // VPUNPCKHWDZ128rr 0U, // VPUNPCKHWDZ128rrk 9348U, // VPUNPCKHWDZ128rrkz 4U, // VPUNPCKHWDZ256rm 132U, // VPUNPCKHWDZ256rmk 9348U, // VPUNPCKHWDZ256rmkz 4U, // VPUNPCKHWDZ256rr 0U, // VPUNPCKHWDZ256rrk 9348U, // VPUNPCKHWDZ256rrkz 4U, // VPUNPCKHWDZrm 132U, // VPUNPCKHWDZrmk 9348U, // VPUNPCKHWDZrmkz 4U, // VPUNPCKHWDZrr 0U, // VPUNPCKHWDZrrk 9348U, // VPUNPCKHWDZrrkz 4U, // VPUNPCKHWDrm 4U, // VPUNPCKHWDrr 4U, // VPUNPCKLBWYrm 4U, // VPUNPCKLBWYrr 4U, // VPUNPCKLBWZ128rm 132U, // VPUNPCKLBWZ128rmk 9348U, // VPUNPCKLBWZ128rmkz 4U, // VPUNPCKLBWZ128rr 0U, // VPUNPCKLBWZ128rrk 9348U, // VPUNPCKLBWZ128rrkz 4U, // VPUNPCKLBWZ256rm 132U, // VPUNPCKLBWZ256rmk 9348U, // VPUNPCKLBWZ256rmkz 4U, // VPUNPCKLBWZ256rr 0U, // VPUNPCKLBWZ256rrk 9348U, // VPUNPCKLBWZ256rrkz 4U, // VPUNPCKLBWZrm 132U, // VPUNPCKLBWZrmk 9348U, // VPUNPCKLBWZrmkz 4U, // VPUNPCKLBWZrr 0U, // VPUNPCKLBWZrrk 9348U, // VPUNPCKLBWZrrkz 4U, // VPUNPCKLBWrm 4U, // VPUNPCKLBWrr 4U, // VPUNPCKLDQYrm 4U, // VPUNPCKLDQYrr 4U, // VPUNPCKLDQZ128rm 72U, // VPUNPCKLDQZ128rmb 133U, // VPUNPCKLDQZ128rmbk 9348U, // VPUNPCKLDQZ128rmbkz 132U, // VPUNPCKLDQZ128rmk 9348U, // VPUNPCKLDQZ128rmkz 4U, // VPUNPCKLDQZ128rr 0U, // VPUNPCKLDQZ128rrk 9348U, // VPUNPCKLDQZ128rrkz 4U, // VPUNPCKLDQZ256rm 72U, // VPUNPCKLDQZ256rmb 133U, // VPUNPCKLDQZ256rmbk 9348U, // VPUNPCKLDQZ256rmbkz 132U, // VPUNPCKLDQZ256rmk 9348U, // VPUNPCKLDQZ256rmkz 4U, // VPUNPCKLDQZ256rr 0U, // VPUNPCKLDQZ256rrk 9348U, // VPUNPCKLDQZ256rrkz 4U, // VPUNPCKLDQZrm 72U, // VPUNPCKLDQZrmb 133U, // VPUNPCKLDQZrmbk 9348U, // VPUNPCKLDQZrmbkz 132U, // VPUNPCKLDQZrmk 9348U, // VPUNPCKLDQZrmkz 4U, // VPUNPCKLDQZrr 0U, // VPUNPCKLDQZrrk 9348U, // VPUNPCKLDQZrrkz 4U, // VPUNPCKLDQrm 4U, // VPUNPCKLDQrr 4U, // VPUNPCKLQDQYrm 4U, // VPUNPCKLQDQYrr 4U, // VPUNPCKLQDQZ128rm 72U, // VPUNPCKLQDQZ128rmb 133U, // VPUNPCKLQDQZ128rmbk 9348U, // VPUNPCKLQDQZ128rmbkz 132U, // VPUNPCKLQDQZ128rmk 9348U, // VPUNPCKLQDQZ128rmkz 4U, // VPUNPCKLQDQZ128rr 0U, // VPUNPCKLQDQZ128rrk 9348U, // VPUNPCKLQDQZ128rrkz 4U, // VPUNPCKLQDQZ256rm 72U, // VPUNPCKLQDQZ256rmb 133U, // VPUNPCKLQDQZ256rmbk 9348U, // VPUNPCKLQDQZ256rmbkz 132U, // VPUNPCKLQDQZ256rmk 9348U, // VPUNPCKLQDQZ256rmkz 4U, // VPUNPCKLQDQZ256rr 0U, // VPUNPCKLQDQZ256rrk 9348U, // VPUNPCKLQDQZ256rrkz 4U, // VPUNPCKLQDQZrm 72U, // VPUNPCKLQDQZrmb 133U, // VPUNPCKLQDQZrmbk 9348U, // VPUNPCKLQDQZrmbkz 132U, // VPUNPCKLQDQZrmk 9348U, // VPUNPCKLQDQZrmkz 4U, // VPUNPCKLQDQZrr 0U, // VPUNPCKLQDQZrrk 9348U, // VPUNPCKLQDQZrrkz 4U, // VPUNPCKLQDQrm 4U, // VPUNPCKLQDQrr 4U, // VPUNPCKLWDYrm 4U, // VPUNPCKLWDYrr 4U, // VPUNPCKLWDZ128rm 132U, // VPUNPCKLWDZ128rmk 9348U, // VPUNPCKLWDZ128rmkz 4U, // VPUNPCKLWDZ128rr 0U, // VPUNPCKLWDZ128rrk 9348U, // VPUNPCKLWDZ128rrkz 4U, // VPUNPCKLWDZ256rm 132U, // VPUNPCKLWDZ256rmk 9348U, // VPUNPCKLWDZ256rmkz 4U, // VPUNPCKLWDZ256rr 0U, // VPUNPCKLWDZ256rrk 9348U, // VPUNPCKLWDZ256rrkz 4U, // VPUNPCKLWDZrm 132U, // VPUNPCKLWDZrmk 9348U, // VPUNPCKLWDZrmkz 4U, // VPUNPCKLWDZrr 0U, // VPUNPCKLWDZrrk 9348U, // VPUNPCKLWDZrrkz 4U, // VPUNPCKLWDrm 4U, // VPUNPCKLWDrr 4U, // VPXORDZ128rm 72U, // VPXORDZ128rmb 133U, // VPXORDZ128rmbk 9348U, // VPXORDZ128rmbkz 132U, // VPXORDZ128rmk 9348U, // VPXORDZ128rmkz 4U, // VPXORDZ128rr 0U, // VPXORDZ128rrk 9348U, // VPXORDZ128rrkz 4U, // VPXORDZ256rm 72U, // VPXORDZ256rmb 133U, // VPXORDZ256rmbk 9348U, // VPXORDZ256rmbkz 132U, // VPXORDZ256rmk 9348U, // VPXORDZ256rmkz 4U, // VPXORDZ256rr 0U, // VPXORDZ256rrk 9348U, // VPXORDZ256rrkz 4U, // VPXORDZrm 72U, // VPXORDZrmb 133U, // VPXORDZrmbk 9348U, // VPXORDZrmbkz 132U, // VPXORDZrmk 9348U, // VPXORDZrmkz 4U, // VPXORDZrr 0U, // VPXORDZrrk 9348U, // VPXORDZrrkz 4U, // VPXORQZ128rm 72U, // VPXORQZ128rmb 133U, // VPXORQZ128rmbk 9348U, // VPXORQZ128rmbkz 132U, // VPXORQZ128rmk 9348U, // VPXORQZ128rmkz 4U, // VPXORQZ128rr 0U, // VPXORQZ128rrk 9348U, // VPXORQZ128rrkz 4U, // VPXORQZ256rm 72U, // VPXORQZ256rmb 133U, // VPXORQZ256rmbk 9348U, // VPXORQZ256rmbkz 132U, // VPXORQZ256rmk 9348U, // VPXORQZ256rmkz 4U, // VPXORQZ256rr 0U, // VPXORQZ256rrk 9348U, // VPXORQZ256rrkz 4U, // VPXORQZrm 72U, // VPXORQZrmb 133U, // VPXORQZrmbk 9348U, // VPXORQZrmbkz 132U, // VPXORQZrmk 9348U, // VPXORQZrmkz 4U, // VPXORQZrr 0U, // VPXORQZrrk 9348U, // VPXORQZrrkz 4U, // VPXORYrm 4U, // VPXORYrr 4U, // VPXORrm 4U, // VPXORrr 18637U, // VRANGEPDZ128rmbi 26833U, // VRANGEPDZ128rmbik 26837U, // VRANGEPDZ128rmbikz 72U, // VRANGEPDZ128rmi 1U, // VRANGEPDZ128rmik 9348U, // VRANGEPDZ128rmikz 18636U, // VRANGEPDZ128rri 25U, // VRANGEPDZ128rrik 26837U, // VRANGEPDZ128rrikz 18637U, // VRANGEPDZ256rmbi 26833U, // VRANGEPDZ256rmbik 26837U, // VRANGEPDZ256rmbikz 72U, // VRANGEPDZ256rmi 1U, // VRANGEPDZ256rmik 9348U, // VRANGEPDZ256rmikz 18636U, // VRANGEPDZ256rri 25U, // VRANGEPDZ256rrik 26837U, // VRANGEPDZ256rrikz 18637U, // VRANGEPDZrmbi 26833U, // VRANGEPDZrmbik 26837U, // VRANGEPDZrmbikz 72U, // VRANGEPDZrmi 1U, // VRANGEPDZrmik 9348U, // VRANGEPDZrmikz 18636U, // VRANGEPDZrri 18636U, // VRANGEPDZrrib 25U, // VRANGEPDZrribk 26837U, // VRANGEPDZrribkz 25U, // VRANGEPDZrrik 26837U, // VRANGEPDZrrikz 18637U, // VRANGEPSZ128rmbi 26833U, // VRANGEPSZ128rmbik 26837U, // VRANGEPSZ128rmbikz 72U, // VRANGEPSZ128rmi 1U, // VRANGEPSZ128rmik 9348U, // VRANGEPSZ128rmikz 18636U, // VRANGEPSZ128rri 25U, // VRANGEPSZ128rrik 26837U, // VRANGEPSZ128rrikz 18637U, // VRANGEPSZ256rmbi 26833U, // VRANGEPSZ256rmbik 26837U, // VRANGEPSZ256rmbikz 72U, // VRANGEPSZ256rmi 1U, // VRANGEPSZ256rmik 9348U, // VRANGEPSZ256rmikz 18636U, // VRANGEPSZ256rri 25U, // VRANGEPSZ256rrik 26837U, // VRANGEPSZ256rrikz 18637U, // VRANGEPSZrmbi 26833U, // VRANGEPSZrmbik 26837U, // VRANGEPSZrmbikz 72U, // VRANGEPSZrmi 1U, // VRANGEPSZrmik 9348U, // VRANGEPSZrmikz 18636U, // VRANGEPSZrri 18636U, // VRANGEPSZrrib 25U, // VRANGEPSZrribk 26837U, // VRANGEPSZrribkz 25U, // VRANGEPSZrrik 26837U, // VRANGEPSZrrikz 18636U, // VRANGESDZrmi 26832U, // VRANGESDZrmik 26836U, // VRANGESDZrmikz 18636U, // VRANGESDZrri 18636U, // VRANGESDZrrib 25U, // VRANGESDZrribk 26837U, // VRANGESDZrribkz 25U, // VRANGESDZrrik 26837U, // VRANGESDZrrikz 18636U, // VRANGESSZrmi 26832U, // VRANGESSZrmik 26836U, // VRANGESSZrmikz 18636U, // VRANGESSZrri 18636U, // VRANGESSZrrib 25U, // VRANGESSZrribk 26837U, // VRANGESSZrribkz 25U, // VRANGESSZrrik 26837U, // VRANGESSZrrikz 0U, // VRCP14PDZ128m 0U, // VRCP14PDZ128mb 3356U, // VRCP14PDZ128mbk 4444U, // VRCP14PDZ128mbkz 405U, // VRCP14PDZ128mk 461U, // VRCP14PDZ128mkz 0U, // VRCP14PDZ128r 405U, // VRCP14PDZ128rk 461U, // VRCP14PDZ128rkz 0U, // VRCP14PDZ256m 0U, // VRCP14PDZ256mb 3356U, // VRCP14PDZ256mbk 4444U, // VRCP14PDZ256mbkz 405U, // VRCP14PDZ256mk 461U, // VRCP14PDZ256mkz 0U, // VRCP14PDZ256r 405U, // VRCP14PDZ256rk 461U, // VRCP14PDZ256rkz 0U, // VRCP14PDZm 0U, // VRCP14PDZmb 3356U, // VRCP14PDZmbk 4444U, // VRCP14PDZmbkz 405U, // VRCP14PDZmk 461U, // VRCP14PDZmkz 0U, // VRCP14PDZr 405U, // VRCP14PDZrk 461U, // VRCP14PDZrkz 0U, // VRCP14PSZ128m 0U, // VRCP14PSZ128mb 3356U, // VRCP14PSZ128mbk 4444U, // VRCP14PSZ128mbkz 405U, // VRCP14PSZ128mk 461U, // VRCP14PSZ128mkz 0U, // VRCP14PSZ128r 405U, // VRCP14PSZ128rk 461U, // VRCP14PSZ128rkz 0U, // VRCP14PSZ256m 0U, // VRCP14PSZ256mb 3356U, // VRCP14PSZ256mbk 4444U, // VRCP14PSZ256mbkz 405U, // VRCP14PSZ256mk 461U, // VRCP14PSZ256mkz 0U, // VRCP14PSZ256r 405U, // VRCP14PSZ256rk 461U, // VRCP14PSZ256rkz 0U, // VRCP14PSZm 0U, // VRCP14PSZmb 3356U, // VRCP14PSZmbk 4444U, // VRCP14PSZmbkz 405U, // VRCP14PSZmk 461U, // VRCP14PSZmkz 0U, // VRCP14PSZr 405U, // VRCP14PSZrk 461U, // VRCP14PSZrkz 72U, // VRCP14SDZrm 133U, // VRCP14SDZrmk 9348U, // VRCP14SDZrmkz 4U, // VRCP14SDZrr 0U, // VRCP14SDZrrk 9348U, // VRCP14SDZrrkz 72U, // VRCP14SSZrm 133U, // VRCP14SSZrmk 9348U, // VRCP14SSZrmkz 4U, // VRCP14SSZrr 0U, // VRCP14SSZrrk 9348U, // VRCP14SSZrrkz 0U, // VRCP28PDZm 0U, // VRCP28PDZmb 3356U, // VRCP28PDZmbk 4444U, // VRCP28PDZmbkz 405U, // VRCP28PDZmk 461U, // VRCP28PDZmkz 0U, // VRCP28PDZr 0U, // VRCP28PDZrb 405U, // VRCP28PDZrbk 461U, // VRCP28PDZrbkz 405U, // VRCP28PDZrk 461U, // VRCP28PDZrkz 0U, // VRCP28PSZm 0U, // VRCP28PSZmb 3356U, // VRCP28PSZmbk 4444U, // VRCP28PSZmbkz 405U, // VRCP28PSZmk 461U, // VRCP28PSZmkz 0U, // VRCP28PSZr 0U, // VRCP28PSZrb 405U, // VRCP28PSZrbk 461U, // VRCP28PSZrbkz 405U, // VRCP28PSZrk 461U, // VRCP28PSZrkz 72U, // VRCP28SDZm 133U, // VRCP28SDZmk 9348U, // VRCP28SDZmkz 4U, // VRCP28SDZr 4U, // VRCP28SDZrb 0U, // VRCP28SDZrbk 9348U, // VRCP28SDZrbkz 0U, // VRCP28SDZrk 9348U, // VRCP28SDZrkz 72U, // VRCP28SSZm 133U, // VRCP28SSZmk 9348U, // VRCP28SSZmkz 4U, // VRCP28SSZr 4U, // VRCP28SSZrb 0U, // VRCP28SSZrbk 9348U, // VRCP28SSZrbkz 0U, // VRCP28SSZrk 9348U, // VRCP28SSZrkz 0U, // VRCPPSYm 0U, // VRCPPSYr 0U, // VRCPPSm 0U, // VRCPPSr 72U, // VRCPSSm 72U, // VRCPSSm_Int 4U, // VRCPSSr 4U, // VRCPSSr_Int 5U, // VREDUCEPDZ128rmbi 133U, // VREDUCEPDZ128rmbik 9349U, // VREDUCEPDZ128rmbikz 0U, // VREDUCEPDZ128rmi 3356U, // VREDUCEPDZ128rmik 4444U, // VREDUCEPDZ128rmikz 72U, // VREDUCEPDZ128rri 133U, // VREDUCEPDZ128rrik 9348U, // VREDUCEPDZ128rrikz 5U, // VREDUCEPDZ256rmbi 133U, // VREDUCEPDZ256rmbik 9349U, // VREDUCEPDZ256rmbikz 0U, // VREDUCEPDZ256rmi 3356U, // VREDUCEPDZ256rmik 4444U, // VREDUCEPDZ256rmikz 72U, // VREDUCEPDZ256rri 133U, // VREDUCEPDZ256rrik 9348U, // VREDUCEPDZ256rrikz 5U, // VREDUCEPDZrmbi 133U, // VREDUCEPDZrmbik 9349U, // VREDUCEPDZrmbikz 0U, // VREDUCEPDZrmi 3356U, // VREDUCEPDZrmik 4444U, // VREDUCEPDZrmikz 72U, // VREDUCEPDZrri 72U, // VREDUCEPDZrrib 133U, // VREDUCEPDZrribk 9348U, // VREDUCEPDZrribkz 133U, // VREDUCEPDZrrik 9348U, // VREDUCEPDZrrikz 5U, // VREDUCEPSZ128rmbi 133U, // VREDUCEPSZ128rmbik 9349U, // VREDUCEPSZ128rmbikz 0U, // VREDUCEPSZ128rmi 3356U, // VREDUCEPSZ128rmik 4444U, // VREDUCEPSZ128rmikz 72U, // VREDUCEPSZ128rri 133U, // VREDUCEPSZ128rrik 9348U, // VREDUCEPSZ128rrikz 5U, // VREDUCEPSZ256rmbi 133U, // VREDUCEPSZ256rmbik 9349U, // VREDUCEPSZ256rmbikz 0U, // VREDUCEPSZ256rmi 3356U, // VREDUCEPSZ256rmik 4444U, // VREDUCEPSZ256rmikz 72U, // VREDUCEPSZ256rri 133U, // VREDUCEPSZ256rrik 9348U, // VREDUCEPSZ256rrikz 5U, // VREDUCEPSZrmbi 133U, // VREDUCEPSZrmbik 9349U, // VREDUCEPSZrmbikz 0U, // VREDUCEPSZrmi 3356U, // VREDUCEPSZrmik 4444U, // VREDUCEPSZrmikz 72U, // VREDUCEPSZrri 72U, // VREDUCEPSZrrib 133U, // VREDUCEPSZrribk 9348U, // VREDUCEPSZrribkz 133U, // VREDUCEPSZrrik 9348U, // VREDUCEPSZrrikz 18636U, // VREDUCESDZrmi 26832U, // VREDUCESDZrmik 26836U, // VREDUCESDZrmikz 18636U, // VREDUCESDZrri 18636U, // VREDUCESDZrrib 25U, // VREDUCESDZrribk 26837U, // VREDUCESDZrribkz 25U, // VREDUCESDZrrik 26837U, // VREDUCESDZrrikz 18636U, // VREDUCESSZrmi 26832U, // VREDUCESSZrmik 26836U, // VREDUCESSZrmikz 18636U, // VREDUCESSZrri 18636U, // VREDUCESSZrrib 25U, // VREDUCESSZrribk 26837U, // VREDUCESSZrribkz 25U, // VREDUCESSZrrik 26837U, // VREDUCESSZrrikz 5U, // VRNDSCALEPDZ128rmbi 133U, // VRNDSCALEPDZ128rmbik 9349U, // VRNDSCALEPDZ128rmbikz 0U, // VRNDSCALEPDZ128rmi 3356U, // VRNDSCALEPDZ128rmik 4444U, // VRNDSCALEPDZ128rmikz 72U, // VRNDSCALEPDZ128rri 133U, // VRNDSCALEPDZ128rrik 9348U, // VRNDSCALEPDZ128rrikz 5U, // VRNDSCALEPDZ256rmbi 133U, // VRNDSCALEPDZ256rmbik 9349U, // VRNDSCALEPDZ256rmbikz 0U, // VRNDSCALEPDZ256rmi 3356U, // VRNDSCALEPDZ256rmik 4444U, // VRNDSCALEPDZ256rmikz 72U, // VRNDSCALEPDZ256rri 133U, // VRNDSCALEPDZ256rrik 9348U, // VRNDSCALEPDZ256rrikz 5U, // VRNDSCALEPDZrmbi 133U, // VRNDSCALEPDZrmbik 9349U, // VRNDSCALEPDZrmbikz 0U, // VRNDSCALEPDZrmi 3356U, // VRNDSCALEPDZrmik 4444U, // VRNDSCALEPDZrmikz 72U, // VRNDSCALEPDZrri 72U, // VRNDSCALEPDZrrib 133U, // VRNDSCALEPDZrribk 9348U, // VRNDSCALEPDZrribkz 133U, // VRNDSCALEPDZrrik 9348U, // VRNDSCALEPDZrrikz 5U, // VRNDSCALEPSZ128rmbi 133U, // VRNDSCALEPSZ128rmbik 9349U, // VRNDSCALEPSZ128rmbikz 0U, // VRNDSCALEPSZ128rmi 3356U, // VRNDSCALEPSZ128rmik 4444U, // VRNDSCALEPSZ128rmikz 72U, // VRNDSCALEPSZ128rri 133U, // VRNDSCALEPSZ128rrik 9348U, // VRNDSCALEPSZ128rrikz 5U, // VRNDSCALEPSZ256rmbi 133U, // VRNDSCALEPSZ256rmbik 9349U, // VRNDSCALEPSZ256rmbikz 0U, // VRNDSCALEPSZ256rmi 3356U, // VRNDSCALEPSZ256rmik 4444U, // VRNDSCALEPSZ256rmikz 72U, // VRNDSCALEPSZ256rri 133U, // VRNDSCALEPSZ256rrik 9348U, // VRNDSCALEPSZ256rrikz 5U, // VRNDSCALEPSZrmbi 133U, // VRNDSCALEPSZrmbik 9349U, // VRNDSCALEPSZrmbikz 0U, // VRNDSCALEPSZrmi 3356U, // VRNDSCALEPSZrmik 4444U, // VRNDSCALEPSZrmikz 72U, // VRNDSCALEPSZrri 72U, // VRNDSCALEPSZrrib 133U, // VRNDSCALEPSZrribk 9348U, // VRNDSCALEPSZrribkz 133U, // VRNDSCALEPSZrrik 9348U, // VRNDSCALEPSZrrikz 18636U, // VRNDSCALESDZm 18636U, // VRNDSCALESDZm_Int 26832U, // VRNDSCALESDZm_Intk 26836U, // VRNDSCALESDZm_Intkz 18636U, // VRNDSCALESDZr 18636U, // VRNDSCALESDZr_Int 25U, // VRNDSCALESDZr_Intk 26837U, // VRNDSCALESDZr_Intkz 18636U, // VRNDSCALESDZrb_Int 25U, // VRNDSCALESDZrb_Intk 26837U, // VRNDSCALESDZrb_Intkz 18636U, // VRNDSCALESSZm 18636U, // VRNDSCALESSZm_Int 26832U, // VRNDSCALESSZm_Intk 26836U, // VRNDSCALESSZm_Intkz 18636U, // VRNDSCALESSZr 18636U, // VRNDSCALESSZr_Int 25U, // VRNDSCALESSZr_Intk 26837U, // VRNDSCALESSZr_Intkz 18636U, // VRNDSCALESSZrb_Int 25U, // VRNDSCALESSZrb_Intk 26837U, // VRNDSCALESSZrb_Intkz 0U, // VROUNDPDYm 72U, // VROUNDPDYr 0U, // VROUNDPDm 72U, // VROUNDPDr 0U, // VROUNDPSYm 72U, // VROUNDPSYr 0U, // VROUNDPSm 72U, // VROUNDPSr 18636U, // VROUNDSDm 18636U, // VROUNDSDm_Int 18636U, // VROUNDSDr 18636U, // VROUNDSDr_Int 18636U, // VROUNDSSm 18636U, // VROUNDSSm_Int 18636U, // VROUNDSSr 18636U, // VROUNDSSr_Int 0U, // VRSQRT14PDZ128m 0U, // VRSQRT14PDZ128mb 3356U, // VRSQRT14PDZ128mbk 4444U, // VRSQRT14PDZ128mbkz 405U, // VRSQRT14PDZ128mk 461U, // VRSQRT14PDZ128mkz 0U, // VRSQRT14PDZ128r 405U, // VRSQRT14PDZ128rk 461U, // VRSQRT14PDZ128rkz 0U, // VRSQRT14PDZ256m 0U, // VRSQRT14PDZ256mb 3356U, // VRSQRT14PDZ256mbk 4444U, // VRSQRT14PDZ256mbkz 405U, // VRSQRT14PDZ256mk 461U, // VRSQRT14PDZ256mkz 0U, // VRSQRT14PDZ256r 405U, // VRSQRT14PDZ256rk 461U, // VRSQRT14PDZ256rkz 0U, // VRSQRT14PDZm 0U, // VRSQRT14PDZmb 3356U, // VRSQRT14PDZmbk 4444U, // VRSQRT14PDZmbkz 405U, // VRSQRT14PDZmk 461U, // VRSQRT14PDZmkz 0U, // VRSQRT14PDZr 405U, // VRSQRT14PDZrk 461U, // VRSQRT14PDZrkz 0U, // VRSQRT14PSZ128m 0U, // VRSQRT14PSZ128mb 3356U, // VRSQRT14PSZ128mbk 4444U, // VRSQRT14PSZ128mbkz 405U, // VRSQRT14PSZ128mk 461U, // VRSQRT14PSZ128mkz 0U, // VRSQRT14PSZ128r 405U, // VRSQRT14PSZ128rk 461U, // VRSQRT14PSZ128rkz 0U, // VRSQRT14PSZ256m 0U, // VRSQRT14PSZ256mb 3356U, // VRSQRT14PSZ256mbk 4444U, // VRSQRT14PSZ256mbkz 405U, // VRSQRT14PSZ256mk 461U, // VRSQRT14PSZ256mkz 0U, // VRSQRT14PSZ256r 405U, // VRSQRT14PSZ256rk 461U, // VRSQRT14PSZ256rkz 0U, // VRSQRT14PSZm 0U, // VRSQRT14PSZmb 3356U, // VRSQRT14PSZmbk 4444U, // VRSQRT14PSZmbkz 405U, // VRSQRT14PSZmk 461U, // VRSQRT14PSZmkz 0U, // VRSQRT14PSZr 405U, // VRSQRT14PSZrk 461U, // VRSQRT14PSZrkz 72U, // VRSQRT14SDZrm 133U, // VRSQRT14SDZrmk 9348U, // VRSQRT14SDZrmkz 4U, // VRSQRT14SDZrr 0U, // VRSQRT14SDZrrk 9348U, // VRSQRT14SDZrrkz 72U, // VRSQRT14SSZrm 133U, // VRSQRT14SSZrmk 9348U, // VRSQRT14SSZrmkz 4U, // VRSQRT14SSZrr 0U, // VRSQRT14SSZrrk 9348U, // VRSQRT14SSZrrkz 0U, // VRSQRT28PDZm 0U, // VRSQRT28PDZmb 3356U, // VRSQRT28PDZmbk 4444U, // VRSQRT28PDZmbkz 405U, // VRSQRT28PDZmk 461U, // VRSQRT28PDZmkz 0U, // VRSQRT28PDZr 0U, // VRSQRT28PDZrb 405U, // VRSQRT28PDZrbk 461U, // VRSQRT28PDZrbkz 405U, // VRSQRT28PDZrk 461U, // VRSQRT28PDZrkz 0U, // VRSQRT28PSZm 0U, // VRSQRT28PSZmb 3356U, // VRSQRT28PSZmbk 4444U, // VRSQRT28PSZmbkz 405U, // VRSQRT28PSZmk 461U, // VRSQRT28PSZmkz 0U, // VRSQRT28PSZr 0U, // VRSQRT28PSZrb 405U, // VRSQRT28PSZrbk 461U, // VRSQRT28PSZrbkz 405U, // VRSQRT28PSZrk 461U, // VRSQRT28PSZrkz 72U, // VRSQRT28SDZm 133U, // VRSQRT28SDZmk 9348U, // VRSQRT28SDZmkz 4U, // VRSQRT28SDZr 4U, // VRSQRT28SDZrb 0U, // VRSQRT28SDZrbk 9348U, // VRSQRT28SDZrbkz 0U, // VRSQRT28SDZrk 9348U, // VRSQRT28SDZrkz 72U, // VRSQRT28SSZm 133U, // VRSQRT28SSZmk 9348U, // VRSQRT28SSZmkz 4U, // VRSQRT28SSZr 4U, // VRSQRT28SSZrb 0U, // VRSQRT28SSZrbk 9348U, // VRSQRT28SSZrbkz 0U, // VRSQRT28SSZrk 9348U, // VRSQRT28SSZrkz 0U, // VRSQRTPSYm 0U, // VRSQRTPSYr 0U, // VRSQRTPSm 0U, // VRSQRTPSr 72U, // VRSQRTSSm 72U, // VRSQRTSSm_Int 4U, // VRSQRTSSr 4U, // VRSQRTSSr_Int 4U, // VSCALEFPDZ128rm 72U, // VSCALEFPDZ128rmb 133U, // VSCALEFPDZ128rmbk 9348U, // VSCALEFPDZ128rmbkz 0U, // VSCALEFPDZ128rmk 9348U, // VSCALEFPDZ128rmkz 4U, // VSCALEFPDZ128rr 0U, // VSCALEFPDZ128rrk 9348U, // VSCALEFPDZ128rrkz 4U, // VSCALEFPDZ256rm 72U, // VSCALEFPDZ256rmb 133U, // VSCALEFPDZ256rmbk 9348U, // VSCALEFPDZ256rmbkz 0U, // VSCALEFPDZ256rmk 9348U, // VSCALEFPDZ256rmkz 4U, // VSCALEFPDZ256rr 0U, // VSCALEFPDZ256rrk 9348U, // VSCALEFPDZ256rrkz 4U, // VSCALEFPDZrm 72U, // VSCALEFPDZrmb 133U, // VSCALEFPDZrmbk 9348U, // VSCALEFPDZrmbkz 0U, // VSCALEFPDZrmk 9348U, // VSCALEFPDZrmkz 4U, // VSCALEFPDZrr 4U, // VSCALEFPDZrrb 0U, // VSCALEFPDZrrbk 9348U, // VSCALEFPDZrrbkz 0U, // VSCALEFPDZrrk 9348U, // VSCALEFPDZrrkz 4U, // VSCALEFPSZ128rm 72U, // VSCALEFPSZ128rmb 133U, // VSCALEFPSZ128rmbk 9348U, // VSCALEFPSZ128rmbkz 0U, // VSCALEFPSZ128rmk 9348U, // VSCALEFPSZ128rmkz 4U, // VSCALEFPSZ128rr 0U, // VSCALEFPSZ128rrk 9348U, // VSCALEFPSZ128rrkz 4U, // VSCALEFPSZ256rm 72U, // VSCALEFPSZ256rmb 133U, // VSCALEFPSZ256rmbk 9348U, // VSCALEFPSZ256rmbkz 0U, // VSCALEFPSZ256rmk 9348U, // VSCALEFPSZ256rmkz 4U, // VSCALEFPSZ256rr 0U, // VSCALEFPSZ256rrk 9348U, // VSCALEFPSZ256rrkz 4U, // VSCALEFPSZrm 72U, // VSCALEFPSZrmb 133U, // VSCALEFPSZrmbk 9348U, // VSCALEFPSZrmbkz 0U, // VSCALEFPSZrmk 9348U, // VSCALEFPSZrmkz 4U, // VSCALEFPSZrr 4U, // VSCALEFPSZrrb 0U, // VSCALEFPSZrrbk 9348U, // VSCALEFPSZrrbkz 0U, // VSCALEFPSZrrk 9348U, // VSCALEFPSZrrkz 72U, // VSCALEFSDZrm 133U, // VSCALEFSDZrmk 9348U, // VSCALEFSDZrmkz 4U, // VSCALEFSDZrr 4U, // VSCALEFSDZrrb_Int 0U, // VSCALEFSDZrrb_Intk 9348U, // VSCALEFSDZrrb_Intkz 0U, // VSCALEFSDZrrk 9348U, // VSCALEFSDZrrkz 72U, // VSCALEFSSZrm 133U, // VSCALEFSSZrmk 9348U, // VSCALEFSSZrmkz 4U, // VSCALEFSSZrr 4U, // VSCALEFSSZrrb_Int 0U, // VSCALEFSSZrrb_Intk 9348U, // VSCALEFSSZrrb_Intkz 0U, // VSCALEFSSZrrk 9348U, // VSCALEFSSZrrkz 57U, // VSCATTERDPDZ128mr 57U, // VSCATTERDPDZ256mr 57U, // VSCATTERDPDZmr 57U, // VSCATTERDPSZ128mr 57U, // VSCATTERDPSZ256mr 57U, // VSCATTERDPSZmr 0U, // VSCATTERPF0DPDm 0U, // VSCATTERPF0DPSm 0U, // VSCATTERPF0QPDm 0U, // VSCATTERPF0QPSm 0U, // VSCATTERPF1DPDm 0U, // VSCATTERPF1DPSm 0U, // VSCATTERPF1QPDm 0U, // VSCATTERPF1QPSm 57U, // VSCATTERQPDZ128mr 57U, // VSCATTERQPDZ256mr 57U, // VSCATTERQPDZmr 57U, // VSCATTERQPSZ128mr 57U, // VSCATTERQPSZ256mr 57U, // VSCATTERQPSZmr 18637U, // VSHUFF32X4Z256rmbi 26833U, // VSHUFF32X4Z256rmbik 26837U, // VSHUFF32X4Z256rmbikz 72U, // VSHUFF32X4Z256rmi 1U, // VSHUFF32X4Z256rmik 9348U, // VSHUFF32X4Z256rmikz 18636U, // VSHUFF32X4Z256rri 25U, // VSHUFF32X4Z256rrik 26837U, // VSHUFF32X4Z256rrikz 18637U, // VSHUFF32X4Zrmbi 26833U, // VSHUFF32X4Zrmbik 26837U, // VSHUFF32X4Zrmbikz 72U, // VSHUFF32X4Zrmi 1U, // VSHUFF32X4Zrmik 9348U, // VSHUFF32X4Zrmikz 18636U, // VSHUFF32X4Zrri 25U, // VSHUFF32X4Zrrik 26837U, // VSHUFF32X4Zrrikz 18637U, // VSHUFF64X2Z256rmbi 26833U, // VSHUFF64X2Z256rmbik 26837U, // VSHUFF64X2Z256rmbikz 72U, // VSHUFF64X2Z256rmi 1U, // VSHUFF64X2Z256rmik 9348U, // VSHUFF64X2Z256rmikz 18636U, // VSHUFF64X2Z256rri 25U, // VSHUFF64X2Z256rrik 26837U, // VSHUFF64X2Z256rrikz 18637U, // VSHUFF64X2Zrmbi 26833U, // VSHUFF64X2Zrmbik 26837U, // VSHUFF64X2Zrmbikz 72U, // VSHUFF64X2Zrmi 1U, // VSHUFF64X2Zrmik 9348U, // VSHUFF64X2Zrmikz 18636U, // VSHUFF64X2Zrri 25U, // VSHUFF64X2Zrrik 26837U, // VSHUFF64X2Zrrikz 18637U, // VSHUFI32X4Z256rmbi 26833U, // VSHUFI32X4Z256rmbik 26837U, // VSHUFI32X4Z256rmbikz 72U, // VSHUFI32X4Z256rmi 1U, // VSHUFI32X4Z256rmik 9348U, // VSHUFI32X4Z256rmikz 18636U, // VSHUFI32X4Z256rri 25U, // VSHUFI32X4Z256rrik 26837U, // VSHUFI32X4Z256rrikz 18637U, // VSHUFI32X4Zrmbi 26833U, // VSHUFI32X4Zrmbik 26837U, // VSHUFI32X4Zrmbikz 72U, // VSHUFI32X4Zrmi 1U, // VSHUFI32X4Zrmik 9348U, // VSHUFI32X4Zrmikz 18636U, // VSHUFI32X4Zrri 25U, // VSHUFI32X4Zrrik 26837U, // VSHUFI32X4Zrrikz 18637U, // VSHUFI64X2Z256rmbi 26833U, // VSHUFI64X2Z256rmbik 26837U, // VSHUFI64X2Z256rmbikz 72U, // VSHUFI64X2Z256rmi 1U, // VSHUFI64X2Z256rmik 9348U, // VSHUFI64X2Z256rmikz 18636U, // VSHUFI64X2Z256rri 25U, // VSHUFI64X2Z256rrik 26837U, // VSHUFI64X2Z256rrikz 18637U, // VSHUFI64X2Zrmbi 26833U, // VSHUFI64X2Zrmbik 26837U, // VSHUFI64X2Zrmbikz 72U, // VSHUFI64X2Zrmi 1U, // VSHUFI64X2Zrmik 9348U, // VSHUFI64X2Zrmikz 18636U, // VSHUFI64X2Zrri 25U, // VSHUFI64X2Zrrik 26837U, // VSHUFI64X2Zrrikz 72U, // VSHUFPDYrmi 18636U, // VSHUFPDYrri 18637U, // VSHUFPDZ128rmbi 26833U, // VSHUFPDZ128rmbik 26837U, // VSHUFPDZ128rmbikz 72U, // VSHUFPDZ128rmi 1U, // VSHUFPDZ128rmik 9348U, // VSHUFPDZ128rmikz 18636U, // VSHUFPDZ128rri 25U, // VSHUFPDZ128rrik 26837U, // VSHUFPDZ128rrikz 18637U, // VSHUFPDZ256rmbi 26833U, // VSHUFPDZ256rmbik 26837U, // VSHUFPDZ256rmbikz 72U, // VSHUFPDZ256rmi 1U, // VSHUFPDZ256rmik 9348U, // VSHUFPDZ256rmikz 18636U, // VSHUFPDZ256rri 25U, // VSHUFPDZ256rrik 26837U, // VSHUFPDZ256rrikz 18637U, // VSHUFPDZrmbi 26833U, // VSHUFPDZrmbik 26837U, // VSHUFPDZrmbikz 72U, // VSHUFPDZrmi 1U, // VSHUFPDZrmik 9348U, // VSHUFPDZrmikz 18636U, // VSHUFPDZrri 25U, // VSHUFPDZrrik 26837U, // VSHUFPDZrrikz 72U, // VSHUFPDrmi 18636U, // VSHUFPDrri 72U, // VSHUFPSYrmi 18636U, // VSHUFPSYrri 18637U, // VSHUFPSZ128rmbi 26833U, // VSHUFPSZ128rmbik 26837U, // VSHUFPSZ128rmbikz 72U, // VSHUFPSZ128rmi 1U, // VSHUFPSZ128rmik 9348U, // VSHUFPSZ128rmikz 18636U, // VSHUFPSZ128rri 25U, // VSHUFPSZ128rrik 26837U, // VSHUFPSZ128rrikz 18637U, // VSHUFPSZ256rmbi 26833U, // VSHUFPSZ256rmbik 26837U, // VSHUFPSZ256rmbikz 72U, // VSHUFPSZ256rmi 1U, // VSHUFPSZ256rmik 9348U, // VSHUFPSZ256rmikz 18636U, // VSHUFPSZ256rri 25U, // VSHUFPSZ256rrik 26837U, // VSHUFPSZ256rrikz 18637U, // VSHUFPSZrmbi 26833U, // VSHUFPSZrmbik 26837U, // VSHUFPSZrmbikz 72U, // VSHUFPSZrmi 1U, // VSHUFPSZrmik 9348U, // VSHUFPSZrmikz 18636U, // VSHUFPSZrri 25U, // VSHUFPSZrrik 26837U, // VSHUFPSZrrikz 72U, // VSHUFPSrmi 18636U, // VSHUFPSrri 0U, // VSQRTPDYm 0U, // VSQRTPDYr 0U, // VSQRTPDZ128m 0U, // VSQRTPDZ128mb 3356U, // VSQRTPDZ128mbk 4444U, // VSQRTPDZ128mbkz 405U, // VSQRTPDZ128mk 461U, // VSQRTPDZ128mkz 0U, // VSQRTPDZ128r 405U, // VSQRTPDZ128rk 461U, // VSQRTPDZ128rkz 0U, // VSQRTPDZ256m 0U, // VSQRTPDZ256mb 3356U, // VSQRTPDZ256mbk 4444U, // VSQRTPDZ256mbkz 405U, // VSQRTPDZ256mk 461U, // VSQRTPDZ256mkz 0U, // VSQRTPDZ256r 405U, // VSQRTPDZ256rk 461U, // VSQRTPDZ256rkz 0U, // VSQRTPDZm 0U, // VSQRTPDZmb 3356U, // VSQRTPDZmbk 4444U, // VSQRTPDZmbkz 405U, // VSQRTPDZmk 461U, // VSQRTPDZmkz 0U, // VSQRTPDZr 0U, // VSQRTPDZrb 405U, // VSQRTPDZrbk 461U, // VSQRTPDZrbkz 405U, // VSQRTPDZrk 461U, // VSQRTPDZrkz 0U, // VSQRTPDm 0U, // VSQRTPDr 0U, // VSQRTPSYm 0U, // VSQRTPSYr 0U, // VSQRTPSZ128m 0U, // VSQRTPSZ128mb 3356U, // VSQRTPSZ128mbk 4444U, // VSQRTPSZ128mbkz 405U, // VSQRTPSZ128mk 461U, // VSQRTPSZ128mkz 0U, // VSQRTPSZ128r 405U, // VSQRTPSZ128rk 461U, // VSQRTPSZ128rkz 0U, // VSQRTPSZ256m 0U, // VSQRTPSZ256mb 3356U, // VSQRTPSZ256mbk 4444U, // VSQRTPSZ256mbkz 405U, // VSQRTPSZ256mk 461U, // VSQRTPSZ256mkz 0U, // VSQRTPSZ256r 405U, // VSQRTPSZ256rk 461U, // VSQRTPSZ256rkz 0U, // VSQRTPSZm 0U, // VSQRTPSZmb 3356U, // VSQRTPSZmbk 4444U, // VSQRTPSZmbkz 405U, // VSQRTPSZmk 461U, // VSQRTPSZmkz 0U, // VSQRTPSZr 0U, // VSQRTPSZrb 405U, // VSQRTPSZrbk 461U, // VSQRTPSZrbkz 405U, // VSQRTPSZrk 461U, // VSQRTPSZrkz 0U, // VSQRTPSm 0U, // VSQRTPSr 72U, // VSQRTSDZm 72U, // VSQRTSDZm_Int 133U, // VSQRTSDZm_Intk 9348U, // VSQRTSDZm_Intkz 4U, // VSQRTSDZr 4U, // VSQRTSDZr_Int 0U, // VSQRTSDZr_Intk 9348U, // VSQRTSDZr_Intkz 4U, // VSQRTSDZrb_Int 0U, // VSQRTSDZrb_Intk 9348U, // VSQRTSDZrb_Intkz 72U, // VSQRTSDm 72U, // VSQRTSDm_Int 4U, // VSQRTSDr 4U, // VSQRTSDr_Int 72U, // VSQRTSSZm 72U, // VSQRTSSZm_Int 133U, // VSQRTSSZm_Intk 9348U, // VSQRTSSZm_Intkz 4U, // VSQRTSSZr 4U, // VSQRTSSZr_Int 0U, // VSQRTSSZr_Intk 9348U, // VSQRTSSZr_Intkz 4U, // VSQRTSSZrb_Int 0U, // VSQRTSSZrb_Intk 9348U, // VSQRTSSZrb_Intkz 72U, // VSQRTSSm 72U, // VSQRTSSm_Int 4U, // VSQRTSSr 4U, // VSQRTSSr_Int 0U, // VSTMXCSR 4U, // VSUBPDYrm 4U, // VSUBPDYrr 4U, // VSUBPDZ128rm 72U, // VSUBPDZ128rmb 133U, // VSUBPDZ128rmbk 9348U, // VSUBPDZ128rmbkz 0U, // VSUBPDZ128rmk 9348U, // VSUBPDZ128rmkz 4U, // VSUBPDZ128rr 0U, // VSUBPDZ128rrk 9348U, // VSUBPDZ128rrkz 4U, // VSUBPDZ256rm 72U, // VSUBPDZ256rmb 133U, // VSUBPDZ256rmbk 9348U, // VSUBPDZ256rmbkz 0U, // VSUBPDZ256rmk 9348U, // VSUBPDZ256rmkz 4U, // VSUBPDZ256rr 0U, // VSUBPDZ256rrk 9348U, // VSUBPDZ256rrkz 4U, // VSUBPDZrm 72U, // VSUBPDZrmb 133U, // VSUBPDZrmbk 9348U, // VSUBPDZrmbkz 0U, // VSUBPDZrmk 9348U, // VSUBPDZrmkz 4U, // VSUBPDZrr 4U, // VSUBPDZrrb 0U, // VSUBPDZrrbk 9348U, // VSUBPDZrrbkz 0U, // VSUBPDZrrk 9348U, // VSUBPDZrrkz 4U, // VSUBPDrm 4U, // VSUBPDrr 4U, // VSUBPSYrm 4U, // VSUBPSYrr 4U, // VSUBPSZ128rm 72U, // VSUBPSZ128rmb 133U, // VSUBPSZ128rmbk 9348U, // VSUBPSZ128rmbkz 0U, // VSUBPSZ128rmk 9348U, // VSUBPSZ128rmkz 4U, // VSUBPSZ128rr 0U, // VSUBPSZ128rrk 9348U, // VSUBPSZ128rrkz 4U, // VSUBPSZ256rm 72U, // VSUBPSZ256rmb 133U, // VSUBPSZ256rmbk 9348U, // VSUBPSZ256rmbkz 0U, // VSUBPSZ256rmk 9348U, // VSUBPSZ256rmkz 4U, // VSUBPSZ256rr 0U, // VSUBPSZ256rrk 9348U, // VSUBPSZ256rrkz 4U, // VSUBPSZrm 72U, // VSUBPSZrmb 133U, // VSUBPSZrmbk 9348U, // VSUBPSZrmbkz 0U, // VSUBPSZrmk 9348U, // VSUBPSZrmkz 4U, // VSUBPSZrr 4U, // VSUBPSZrrb 0U, // VSUBPSZrrbk 9348U, // VSUBPSZrrbkz 0U, // VSUBPSZrrk 9348U, // VSUBPSZrrkz 4U, // VSUBPSrm 4U, // VSUBPSrr 72U, // VSUBSDZrm 72U, // VSUBSDZrm_Int 133U, // VSUBSDZrm_Intk 9348U, // VSUBSDZrm_Intkz 4U, // VSUBSDZrr 4U, // VSUBSDZrr_Int 0U, // VSUBSDZrr_Intk 9348U, // VSUBSDZrr_Intkz 4U, // VSUBSDZrrb_Int 0U, // VSUBSDZrrb_Intk 9348U, // VSUBSDZrrb_Intkz 72U, // VSUBSDrm 72U, // VSUBSDrm_Int 4U, // VSUBSDrr 4U, // VSUBSDrr_Int 72U, // VSUBSSZrm 72U, // VSUBSSZrm_Int 133U, // VSUBSSZrm_Intk 9348U, // VSUBSSZrm_Intkz 4U, // VSUBSSZrr 4U, // VSUBSSZrr_Int 0U, // VSUBSSZrr_Intk 9348U, // VSUBSSZrr_Intkz 4U, // VSUBSSZrrb_Int 0U, // VSUBSSZrrb_Intk 9348U, // VSUBSSZrrb_Intkz 72U, // VSUBSSrm 72U, // VSUBSSrm_Int 4U, // VSUBSSrr 4U, // VSUBSSrr_Int 0U, // VTESTPDYrm 0U, // VTESTPDYrr 0U, // VTESTPDrm 0U, // VTESTPDrr 0U, // VTESTPSYrm 0U, // VTESTPSYrr 0U, // VTESTPSrm 0U, // VTESTPSrr 0U, // VUCOMISDZrm 0U, // VUCOMISDZrm_Int 0U, // VUCOMISDZrr 0U, // VUCOMISDZrr_Int 0U, // VUCOMISDZrrb 0U, // VUCOMISDrm 0U, // VUCOMISDrm_Int 0U, // VUCOMISDrr 0U, // VUCOMISDrr_Int 0U, // VUCOMISSZrm 0U, // VUCOMISSZrm_Int 0U, // VUCOMISSZrr 0U, // VUCOMISSZrr_Int 0U, // VUCOMISSZrrb 0U, // VUCOMISSrm 0U, // VUCOMISSrm_Int 0U, // VUCOMISSrr 0U, // VUCOMISSrr_Int 4U, // VUNPCKHPDYrm 4U, // VUNPCKHPDYrr 4U, // VUNPCKHPDZ128rm 72U, // VUNPCKHPDZ128rmb 133U, // VUNPCKHPDZ128rmbk 9348U, // VUNPCKHPDZ128rmbkz 0U, // VUNPCKHPDZ128rmk 9348U, // VUNPCKHPDZ128rmkz 4U, // VUNPCKHPDZ128rr 0U, // VUNPCKHPDZ128rrk 9348U, // VUNPCKHPDZ128rrkz 4U, // VUNPCKHPDZ256rm 72U, // VUNPCKHPDZ256rmb 133U, // VUNPCKHPDZ256rmbk 9348U, // VUNPCKHPDZ256rmbkz 0U, // VUNPCKHPDZ256rmk 9348U, // VUNPCKHPDZ256rmkz 4U, // VUNPCKHPDZ256rr 0U, // VUNPCKHPDZ256rrk 9348U, // VUNPCKHPDZ256rrkz 4U, // VUNPCKHPDZrm 72U, // VUNPCKHPDZrmb 133U, // VUNPCKHPDZrmbk 9348U, // VUNPCKHPDZrmbkz 0U, // VUNPCKHPDZrmk 9348U, // VUNPCKHPDZrmkz 4U, // VUNPCKHPDZrr 0U, // VUNPCKHPDZrrk 9348U, // VUNPCKHPDZrrkz 4U, // VUNPCKHPDrm 4U, // VUNPCKHPDrr 4U, // VUNPCKHPSYrm 4U, // VUNPCKHPSYrr 4U, // VUNPCKHPSZ128rm 72U, // VUNPCKHPSZ128rmb 133U, // VUNPCKHPSZ128rmbk 9348U, // VUNPCKHPSZ128rmbkz 0U, // VUNPCKHPSZ128rmk 9348U, // VUNPCKHPSZ128rmkz 4U, // VUNPCKHPSZ128rr 0U, // VUNPCKHPSZ128rrk 9348U, // VUNPCKHPSZ128rrkz 4U, // VUNPCKHPSZ256rm 72U, // VUNPCKHPSZ256rmb 133U, // VUNPCKHPSZ256rmbk 9348U, // VUNPCKHPSZ256rmbkz 0U, // VUNPCKHPSZ256rmk 9348U, // VUNPCKHPSZ256rmkz 4U, // VUNPCKHPSZ256rr 0U, // VUNPCKHPSZ256rrk 9348U, // VUNPCKHPSZ256rrkz 4U, // VUNPCKHPSZrm 72U, // VUNPCKHPSZrmb 133U, // VUNPCKHPSZrmbk 9348U, // VUNPCKHPSZrmbkz 0U, // VUNPCKHPSZrmk 9348U, // VUNPCKHPSZrmkz 4U, // VUNPCKHPSZrr 0U, // VUNPCKHPSZrrk 9348U, // VUNPCKHPSZrrkz 4U, // VUNPCKHPSrm 4U, // VUNPCKHPSrr 4U, // VUNPCKLPDYrm 4U, // VUNPCKLPDYrr 4U, // VUNPCKLPDZ128rm 72U, // VUNPCKLPDZ128rmb 133U, // VUNPCKLPDZ128rmbk 9348U, // VUNPCKLPDZ128rmbkz 0U, // VUNPCKLPDZ128rmk 9348U, // VUNPCKLPDZ128rmkz 4U, // VUNPCKLPDZ128rr 0U, // VUNPCKLPDZ128rrk 9348U, // VUNPCKLPDZ128rrkz 4U, // VUNPCKLPDZ256rm 72U, // VUNPCKLPDZ256rmb 133U, // VUNPCKLPDZ256rmbk 9348U, // VUNPCKLPDZ256rmbkz 0U, // VUNPCKLPDZ256rmk 9348U, // VUNPCKLPDZ256rmkz 4U, // VUNPCKLPDZ256rr 0U, // VUNPCKLPDZ256rrk 9348U, // VUNPCKLPDZ256rrkz 4U, // VUNPCKLPDZrm 72U, // VUNPCKLPDZrmb 133U, // VUNPCKLPDZrmbk 9348U, // VUNPCKLPDZrmbkz 0U, // VUNPCKLPDZrmk 9348U, // VUNPCKLPDZrmkz 4U, // VUNPCKLPDZrr 0U, // VUNPCKLPDZrrk 9348U, // VUNPCKLPDZrrkz 4U, // VUNPCKLPDrm 4U, // VUNPCKLPDrr 4U, // VUNPCKLPSYrm 4U, // VUNPCKLPSYrr 4U, // VUNPCKLPSZ128rm 72U, // VUNPCKLPSZ128rmb 133U, // VUNPCKLPSZ128rmbk 9348U, // VUNPCKLPSZ128rmbkz 0U, // VUNPCKLPSZ128rmk 9348U, // VUNPCKLPSZ128rmkz 4U, // VUNPCKLPSZ128rr 0U, // VUNPCKLPSZ128rrk 9348U, // VUNPCKLPSZ128rrkz 4U, // VUNPCKLPSZ256rm 72U, // VUNPCKLPSZ256rmb 133U, // VUNPCKLPSZ256rmbk 9348U, // VUNPCKLPSZ256rmbkz 0U, // VUNPCKLPSZ256rmk 9348U, // VUNPCKLPSZ256rmkz 4U, // VUNPCKLPSZ256rr 0U, // VUNPCKLPSZ256rrk 9348U, // VUNPCKLPSZ256rrkz 4U, // VUNPCKLPSZrm 72U, // VUNPCKLPSZrmb 133U, // VUNPCKLPSZrmbk 9348U, // VUNPCKLPSZrmbkz 0U, // VUNPCKLPSZrmk 9348U, // VUNPCKLPSZrmkz 4U, // VUNPCKLPSZrr 0U, // VUNPCKLPSZrrk 9348U, // VUNPCKLPSZrrkz 4U, // VUNPCKLPSrm 4U, // VUNPCKLPSrr 4U, // VXORPDYrm 4U, // VXORPDYrr 4U, // VXORPDZ128rm 72U, // VXORPDZ128rmb 133U, // VXORPDZ128rmbk 9348U, // VXORPDZ128rmbkz 0U, // VXORPDZ128rmk 9348U, // VXORPDZ128rmkz 4U, // VXORPDZ128rr 0U, // VXORPDZ128rrk 9348U, // VXORPDZ128rrkz 4U, // VXORPDZ256rm 72U, // VXORPDZ256rmb 133U, // VXORPDZ256rmbk 9348U, // VXORPDZ256rmbkz 0U, // VXORPDZ256rmk 9348U, // VXORPDZ256rmkz 4U, // VXORPDZ256rr 0U, // VXORPDZ256rrk 9348U, // VXORPDZ256rrkz 4U, // VXORPDZrm 72U, // VXORPDZrmb 133U, // VXORPDZrmbk 9348U, // VXORPDZrmbkz 0U, // VXORPDZrmk 9348U, // VXORPDZrmkz 4U, // VXORPDZrr 0U, // VXORPDZrrk 9348U, // VXORPDZrrkz 4U, // VXORPDrm 4U, // VXORPDrr 4U, // VXORPSYrm 4U, // VXORPSYrr 4U, // VXORPSZ128rm 72U, // VXORPSZ128rmb 133U, // VXORPSZ128rmbk 9348U, // VXORPSZ128rmbkz 0U, // VXORPSZ128rmk 9348U, // VXORPSZ128rmkz 4U, // VXORPSZ128rr 0U, // VXORPSZ128rrk 9348U, // VXORPSZ128rrkz 4U, // VXORPSZ256rm 72U, // VXORPSZ256rmb 133U, // VXORPSZ256rmbk 9348U, // VXORPSZ256rmbkz 0U, // VXORPSZ256rmk 9348U, // VXORPSZ256rmkz 4U, // VXORPSZ256rr 0U, // VXORPSZ256rrk 9348U, // VXORPSZ256rrkz 4U, // VXORPSZrm 72U, // VXORPSZrmb 133U, // VXORPSZrmbk 9348U, // VXORPSZrmbkz 0U, // VXORPSZrmk 9348U, // VXORPSZrmkz 4U, // VXORPSZrr 0U, // VXORPSZrrk 9348U, // VXORPSZrrkz 4U, // VXORPSrm 4U, // VXORPSrr 0U, // VZEROALL 0U, // VZEROUPPER 0U, // WAIT 0U, // WBINVD 0U, // WBNOINVD 0U, // WRFSBASE 0U, // WRFSBASE64 0U, // WRGSBASE 0U, // WRGSBASE64 0U, // WRMSR 0U, // WRPKRUr 0U, // WRSSD 0U, // WRSSQ 0U, // WRUSSD 0U, // WRUSSQ 0U, // XABORT 0U, // XACQUIRE_PREFIX 3U, // XADD16rm 0U, // XADD16rr 3U, // XADD32rm 0U, // XADD32rr 3U, // XADD64rm 0U, // XADD64rr 3U, // XADD8rm 0U, // XADD8rr 0U, // XBEGIN_2 0U, // XBEGIN_4 0U, // XCHG16ar 3U, // XCHG16rm 0U, // XCHG16rr 0U, // XCHG32ar 3U, // XCHG32rm 0U, // XCHG32rr 0U, // XCHG64ar 3U, // XCHG64rm 0U, // XCHG64rr 3U, // XCHG8rm 0U, // XCHG8rr 0U, // XCH_F 0U, // XCRYPTCBC 0U, // XCRYPTCFB 0U, // XCRYPTCTR 0U, // XCRYPTECB 0U, // XCRYPTOFB 0U, // XEND 0U, // XGETBV 0U, // XLAT 0U, // XOR16i16 0U, // XOR16mi 0U, // XOR16mi8 0U, // XOR16mr 0U, // XOR16ri 0U, // XOR16ri8 0U, // XOR16rm 0U, // XOR16rr 0U, // XOR16rr_REV 0U, // XOR32i32 0U, // XOR32mi 0U, // XOR32mi8 0U, // XOR32mr 0U, // XOR32ri 0U, // XOR32ri8 0U, // XOR32rm 0U, // XOR32rr 0U, // XOR32rr_REV 0U, // XOR64i32 0U, // XOR64mi32 0U, // XOR64mi8 0U, // XOR64mr 0U, // XOR64ri32 0U, // XOR64ri8 0U, // XOR64rm 0U, // XOR64rr 0U, // XOR64rr_REV 0U, // XOR8i8 0U, // XOR8mi 0U, // XOR8mi8 0U, // XOR8mr 0U, // XOR8ri 0U, // XOR8ri8 0U, // XOR8rm 0U, // XOR8rr 0U, // XOR8rr_REV 0U, // XORPDrm 0U, // XORPDrr 0U, // XORPSrm 0U, // XORPSrr 0U, // XRELEASE_PREFIX 0U, // XRSTOR 0U, // XRSTOR64 0U, // XRSTORS 0U, // XRSTORS64 0U, // XSAVE 0U, // XSAVE64 0U, // XSAVEC 0U, // XSAVEC64 0U, // XSAVEOPT 0U, // XSAVEOPT64 0U, // XSAVES 0U, // XSAVES64 0U, // XSETBV 0U, // XSHA1 0U, // XSHA256 0U, // XSTORE 0U, // XTEST }; static const uint8_t OpInfo2[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // AVX1_SETALLONES 0U, // AVX2_SETALLONES 0U, // AVX512_128_SET0 0U, // AVX512_256_SET0 0U, // AVX512_512_SET0 0U, // AVX512_512_SETALLONES 0U, // AVX512_512_SEXT_MASK_32 0U, // AVX512_512_SEXT_MASK_64 0U, // AVX512_FsFLD0SD 0U, // AVX512_FsFLD0SS 0U, // AVX_SET0 0U, // KSET0D 0U, // KSET0Q 0U, // KSET0W 0U, // KSET1D 0U, // KSET1Q 0U, // KSET1W 0U, // MMX_SET0 0U, // V_SET0 0U, // V_SETALLONES 0U, // AAA 0U, // AAD8i8 0U, // AAM8i8 0U, // AAS 0U, // ABS_F 0U, // ABS_Fp32 0U, // ABS_Fp64 0U, // ABS_Fp80 0U, // ADC16i16 0U, // ADC16mi 0U, // ADC16mi8 0U, // ADC16mr 0U, // ADC16ri 0U, // ADC16ri8 0U, // ADC16rm 0U, // ADC16rr 0U, // ADC16rr_REV 0U, // ADC32i32 0U, // ADC32mi 0U, // ADC32mi8 0U, // ADC32mr 0U, // ADC32ri 0U, // ADC32ri8 0U, // ADC32rm 0U, // ADC32rr 0U, // ADC32rr_REV 0U, // ADC64i32 0U, // ADC64mi32 0U, // ADC64mi8 0U, // ADC64mr 0U, // ADC64ri32 0U, // ADC64ri8 0U, // ADC64rm 0U, // ADC64rr 0U, // ADC64rr_REV 0U, // ADC8i8 0U, // ADC8mi 0U, // ADC8mi8 0U, // ADC8mr 0U, // ADC8ri 0U, // ADC8ri8 0U, // ADC8rm 0U, // ADC8rr 0U, // ADC8rr_REV 0U, // ADCX32rm 0U, // ADCX32rr 0U, // ADCX64rm 0U, // ADCX64rr 0U, // ADD16i16 0U, // ADD16mi 0U, // ADD16mi8 0U, // ADD16mr 0U, // ADD16ri 0U, // ADD16ri8 0U, // ADD16rm 0U, // ADD16rr 0U, // ADD16rr_REV 0U, // ADD32i32 0U, // ADD32mi 0U, // ADD32mi8 0U, // ADD32mr 0U, // ADD32ri 0U, // ADD32ri8 0U, // ADD32rm 0U, // ADD32rr 0U, // ADD32rr_REV 0U, // ADD64i32 0U, // ADD64mi32 0U, // ADD64mi8 0U, // ADD64mr 0U, // ADD64ri32 0U, // ADD64ri8 0U, // ADD64rm 0U, // ADD64rr 0U, // ADD64rr_REV 0U, // ADD8i8 0U, // ADD8mi 0U, // ADD8mi8 0U, // ADD8mr 0U, // ADD8ri 0U, // ADD8ri8 0U, // ADD8rm 0U, // ADD8rr 0U, // ADD8rr_REV 0U, // ADDPDrm 0U, // ADDPDrr 0U, // ADDPSrm 0U, // ADDPSrr 0U, // ADDSDrm 0U, // ADDSDrm_Int 0U, // ADDSDrr 0U, // ADDSDrr_Int 0U, // ADDSSrm 0U, // ADDSSrm_Int 0U, // ADDSSrr 0U, // ADDSSrr_Int 0U, // ADDSUBPDrm 0U, // ADDSUBPDrr 0U, // ADDSUBPSrm 0U, // ADDSUBPSrr 0U, // ADD_F32m 0U, // ADD_F64m 0U, // ADD_FI16m 0U, // ADD_FI32m 0U, // ADD_FPrST0 0U, // ADD_FST0r 0U, // ADD_Fp32 0U, // ADD_Fp32m 0U, // ADD_Fp64 0U, // ADD_Fp64m 0U, // ADD_Fp64m32 0U, // ADD_Fp80 0U, // ADD_Fp80m32 0U, // ADD_Fp80m64 0U, // ADD_FpI16m32 0U, // ADD_FpI16m64 0U, // ADD_FpI16m80 0U, // ADD_FpI32m32 0U, // ADD_FpI32m64 0U, // ADD_FpI32m80 0U, // ADD_FrST0 0U, // ADOX32rm 0U, // ADOX32rr 0U, // ADOX64rm 0U, // ADOX64rr 0U, // AESDECLASTrm 0U, // AESDECLASTrr 0U, // AESDECrm 0U, // AESDECrr 0U, // AESENCLASTrm 0U, // AESENCLASTrr 0U, // AESENCrm 0U, // AESENCrr 0U, // AESIMCrm 0U, // AESIMCrr 0U, // AESKEYGENASSIST128rm 0U, // AESKEYGENASSIST128rr 0U, // AND16i16 0U, // AND16mi 0U, // AND16mi8 0U, // AND16mr 0U, // AND16ri 0U, // AND16ri8 0U, // AND16rm 0U, // AND16rr 0U, // AND16rr_REV 0U, // AND32i32 0U, // AND32mi 0U, // AND32mi8 0U, // AND32mr 0U, // AND32ri 0U, // AND32ri8 0U, // AND32rm 0U, // AND32rr 0U, // AND32rr_REV 0U, // AND64i32 0U, // AND64mi32 0U, // AND64mi8 0U, // AND64mr 0U, // AND64ri32 0U, // AND64ri8 0U, // AND64rm 0U, // AND64rr 0U, // AND64rr_REV 0U, // AND8i8 0U, // AND8mi 0U, // AND8mi8 0U, // AND8mr 0U, // AND8ri 0U, // AND8ri8 0U, // AND8rm 0U, // AND8rr 0U, // AND8rr_REV 0U, // ANDN32rm 0U, // ANDN32rr 0U, // ANDN64rm 0U, // ANDN64rr 0U, // ANDNPDrm 0U, // ANDNPDrr 0U, // ANDNPSrm 0U, // ANDNPSrr 0U, // ANDPDrm 0U, // ANDPDrr 0U, // ANDPSrm 0U, // ANDPSrr 0U, // ARPL16mr 0U, // ARPL16rr 0U, // BEXTR32rm 0U, // BEXTR32rr 0U, // BEXTR64rm 0U, // BEXTR64rr 0U, // BEXTRI32mi 0U, // BEXTRI32ri 0U, // BEXTRI64mi 0U, // BEXTRI64ri 0U, // BLCFILL32rm 0U, // BLCFILL32rr 0U, // BLCFILL64rm 0U, // BLCFILL64rr 0U, // BLCI32rm 0U, // BLCI32rr 0U, // BLCI64rm 0U, // BLCI64rr 0U, // BLCIC32rm 0U, // BLCIC32rr 0U, // BLCIC64rm 0U, // BLCIC64rr 0U, // BLCMSK32rm 0U, // BLCMSK32rr 0U, // BLCMSK64rm 0U, // BLCMSK64rr 0U, // BLCS32rm 0U, // BLCS32rr 0U, // BLCS64rm 0U, // BLCS64rr 0U, // BLENDPDrmi 0U, // BLENDPDrri 0U, // BLENDPSrmi 0U, // BLENDPSrri 0U, // BLENDVPDrm0 0U, // BLENDVPDrr0 0U, // BLENDVPSrm0 0U, // BLENDVPSrr0 0U, // BLSFILL32rm 0U, // BLSFILL32rr 0U, // BLSFILL64rm 0U, // BLSFILL64rr 0U, // BLSI32rm 0U, // BLSI32rr 0U, // BLSI64rm 0U, // BLSI64rr 0U, // BLSIC32rm 0U, // BLSIC32rr 0U, // BLSIC64rm 0U, // BLSIC64rr 0U, // BLSMSK32rm 0U, // BLSMSK32rr 0U, // BLSMSK64rm 0U, // BLSMSK64rr 0U, // BLSR32rm 0U, // BLSR32rr 0U, // BLSR64rm 0U, // BLSR64rr 0U, // BNDCL32rm 0U, // BNDCL32rr 0U, // BNDCL64rm 0U, // BNDCL64rr 0U, // BNDCN32rm 0U, // BNDCN32rr 0U, // BNDCN64rm 0U, // BNDCN64rr 0U, // BNDCU32rm 0U, // BNDCU32rr 0U, // BNDCU64rm 0U, // BNDCU64rr 0U, // BNDLDXrm 0U, // BNDMK32rm 0U, // BNDMK64rm 0U, // BNDMOV32mr 0U, // BNDMOV32rm 0U, // BNDMOV64mr 0U, // BNDMOV64rm 0U, // BNDMOVrr 0U, // BNDMOVrr_REV 0U, // BNDSTXmr 0U, // BOUNDS16rm 0U, // BOUNDS32rm 0U, // BSF16rm 0U, // BSF16rr 0U, // BSF32rm 0U, // BSF32rr 0U, // BSF64rm 0U, // BSF64rr 0U, // BSR16rm 0U, // BSR16rr 0U, // BSR32rm 0U, // BSR32rr 0U, // BSR64rm 0U, // BSR64rr 0U, // BSWAP16r_BAD 0U, // BSWAP32r 0U, // BSWAP64r 0U, // BT16mi8 0U, // BT16mr 0U, // BT16ri8 0U, // BT16rr 0U, // BT32mi8 0U, // BT32mr 0U, // BT32ri8 0U, // BT32rr 0U, // BT64mi8 0U, // BT64mr 0U, // BT64ri8 0U, // BT64rr 0U, // BTC16mi8 0U, // BTC16mr 0U, // BTC16ri8 0U, // BTC16rr 0U, // BTC32mi8 0U, // BTC32mr 0U, // BTC32ri8 0U, // BTC32rr 0U, // BTC64mi8 0U, // BTC64mr 0U, // BTC64ri8 0U, // BTC64rr 0U, // BTR16mi8 0U, // BTR16mr 0U, // BTR16ri8 0U, // BTR16rr 0U, // BTR32mi8 0U, // BTR32mr 0U, // BTR32ri8 0U, // BTR32rr 0U, // BTR64mi8 0U, // BTR64mr 0U, // BTR64ri8 0U, // BTR64rr 0U, // BTS16mi8 0U, // BTS16mr 0U, // BTS16ri8 0U, // BTS16rr 0U, // BTS32mi8 0U, // BTS32mr 0U, // BTS32ri8 0U, // BTS32rr 0U, // BTS64mi8 0U, // BTS64mr 0U, // BTS64ri8 0U, // BTS64rr 0U, // BZHI32rm 0U, // BZHI32rr 0U, // BZHI64rm 0U, // BZHI64rr 0U, // CALL16m 0U, // CALL16m_NT 0U, // CALL16r 0U, // CALL16r_NT 0U, // CALL32m 0U, // CALL32m_NT 0U, // CALL32r 0U, // CALL32r_NT 0U, // CALL64m 0U, // CALL64m_NT 0U, // CALL64pcrel32 0U, // CALL64r 0U, // CALL64r_NT 0U, // CALLpcrel16 0U, // CALLpcrel32 0U, // CBW 0U, // CDQ 0U, // CDQE 0U, // CHS_F 0U, // CHS_Fp32 0U, // CHS_Fp64 0U, // CHS_Fp80 0U, // CLAC 0U, // CLC 0U, // CLD 0U, // CLDEMOTE 0U, // CLFLUSH 0U, // CLFLUSHOPT 0U, // CLGI 0U, // CLI 0U, // CLRSSBSY 0U, // CLTS 0U, // CLWB 0U, // CLZEROr 0U, // CMC 0U, // CMOVA16rm 0U, // CMOVA16rr 0U, // CMOVA32rm 0U, // CMOVA32rr 0U, // CMOVA64rm 0U, // CMOVA64rr 0U, // CMOVAE16rm 0U, // CMOVAE16rr 0U, // CMOVAE32rm 0U, // CMOVAE32rr 0U, // CMOVAE64rm 0U, // CMOVAE64rr 0U, // CMOVB16rm 0U, // CMOVB16rr 0U, // CMOVB32rm 0U, // CMOVB32rr 0U, // CMOVB64rm 0U, // CMOVB64rr 0U, // CMOVBE16rm 0U, // CMOVBE16rr 0U, // CMOVBE32rm 0U, // CMOVBE32rr 0U, // CMOVBE64rm 0U, // CMOVBE64rr 0U, // CMOVBE_F 0U, // CMOVBE_Fp32 0U, // CMOVBE_Fp64 0U, // CMOVBE_Fp80 0U, // CMOVB_F 0U, // CMOVB_Fp32 0U, // CMOVB_Fp64 0U, // CMOVB_Fp80 0U, // CMOVE16rm 0U, // CMOVE16rr 0U, // CMOVE32rm 0U, // CMOVE32rr 0U, // CMOVE64rm 0U, // CMOVE64rr 0U, // CMOVE_F 0U, // CMOVE_Fp32 0U, // CMOVE_Fp64 0U, // CMOVE_Fp80 0U, // CMOVG16rm 0U, // CMOVG16rr 0U, // CMOVG32rm 0U, // CMOVG32rr 0U, // CMOVG64rm 0U, // CMOVG64rr 0U, // CMOVGE16rm 0U, // CMOVGE16rr 0U, // CMOVGE32rm 0U, // CMOVGE32rr 0U, // CMOVGE64rm 0U, // CMOVGE64rr 0U, // CMOVL16rm 0U, // CMOVL16rr 0U, // CMOVL32rm 0U, // CMOVL32rr 0U, // CMOVL64rm 0U, // CMOVL64rr 0U, // CMOVLE16rm 0U, // CMOVLE16rr 0U, // CMOVLE32rm 0U, // CMOVLE32rr 0U, // CMOVLE64rm 0U, // CMOVLE64rr 0U, // CMOVNBE_F 0U, // CMOVNBE_Fp32 0U, // CMOVNBE_Fp64 0U, // CMOVNBE_Fp80 0U, // CMOVNB_F 0U, // CMOVNB_Fp32 0U, // CMOVNB_Fp64 0U, // CMOVNB_Fp80 0U, // CMOVNE16rm 0U, // CMOVNE16rr 0U, // CMOVNE32rm 0U, // CMOVNE32rr 0U, // CMOVNE64rm 0U, // CMOVNE64rr 0U, // CMOVNE_F 0U, // CMOVNE_Fp32 0U, // CMOVNE_Fp64 0U, // CMOVNE_Fp80 0U, // CMOVNO16rm 0U, // CMOVNO16rr 0U, // CMOVNO32rm 0U, // CMOVNO32rr 0U, // CMOVNO64rm 0U, // CMOVNO64rr 0U, // CMOVNP16rm 0U, // CMOVNP16rr 0U, // CMOVNP32rm 0U, // CMOVNP32rr 0U, // CMOVNP64rm 0U, // CMOVNP64rr 0U, // CMOVNP_F 0U, // CMOVNP_Fp32 0U, // CMOVNP_Fp64 0U, // CMOVNP_Fp80 0U, // CMOVNS16rm 0U, // CMOVNS16rr 0U, // CMOVNS32rm 0U, // CMOVNS32rr 0U, // CMOVNS64rm 0U, // CMOVNS64rr 0U, // CMOVO16rm 0U, // CMOVO16rr 0U, // CMOVO32rm 0U, // CMOVO32rr 0U, // CMOVO64rm 0U, // CMOVO64rr 0U, // CMOVP16rm 0U, // CMOVP16rr 0U, // CMOVP32rm 0U, // CMOVP32rr 0U, // CMOVP64rm 0U, // CMOVP64rr 0U, // CMOVP_F 0U, // CMOVP_Fp32 0U, // CMOVP_Fp64 0U, // CMOVP_Fp80 0U, // CMOVS16rm 0U, // CMOVS16rr 0U, // CMOVS32rm 0U, // CMOVS32rr 0U, // CMOVS64rm 0U, // CMOVS64rr 0U, // CMP16i16 0U, // CMP16mi 0U, // CMP16mi8 0U, // CMP16mr 0U, // CMP16ri 0U, // CMP16ri8 0U, // CMP16rm 0U, // CMP16rr 0U, // CMP16rr_REV 0U, // CMP32i32 0U, // CMP32mi 0U, // CMP32mi8 0U, // CMP32mr 0U, // CMP32ri 0U, // CMP32ri8 0U, // CMP32rm 0U, // CMP32rr 0U, // CMP32rr_REV 0U, // CMP64i32 0U, // CMP64mi32 0U, // CMP64mi8 0U, // CMP64mr 0U, // CMP64ri32 0U, // CMP64ri8 0U, // CMP64rm 0U, // CMP64rr 0U, // CMP64rr_REV 0U, // CMP8i8 0U, // CMP8mi 0U, // CMP8mi8 0U, // CMP8mr 0U, // CMP8ri 0U, // CMP8ri8 0U, // CMP8rm 0U, // CMP8rr 0U, // CMP8rr_REV 0U, // CMPPDrmi 0U, // CMPPDrmi_alt 0U, // CMPPDrri 0U, // CMPPDrri_alt 0U, // CMPPSrmi 0U, // CMPPSrmi_alt 0U, // CMPPSrri 0U, // CMPPSrri_alt 0U, // CMPSB 0U, // CMPSDrm 0U, // CMPSDrm_Int 0U, // CMPSDrm_alt 0U, // CMPSDrr 0U, // CMPSDrr_Int 0U, // CMPSDrr_alt 0U, // CMPSL 0U, // CMPSQ 0U, // CMPSSrm 0U, // CMPSSrm_Int 0U, // CMPSSrm_alt 0U, // CMPSSrr 0U, // CMPSSrr_Int 0U, // CMPSSrr_alt 0U, // CMPSW 0U, // CMPXCHG16B 0U, // CMPXCHG16rm 0U, // CMPXCHG16rr 0U, // CMPXCHG32rm 0U, // CMPXCHG32rr 0U, // CMPXCHG64rm 0U, // CMPXCHG64rr 0U, // CMPXCHG8B 0U, // CMPXCHG8rm 0U, // CMPXCHG8rr 0U, // COMISDrm 0U, // COMISDrm_Int 0U, // COMISDrr 0U, // COMISDrr_Int 0U, // COMISSrm 0U, // COMISSrm_Int 0U, // COMISSrr 0U, // COMISSrr_Int 0U, // COMP_FST0r 0U, // COM_FIPr 0U, // COM_FIr 0U, // COM_FST0r 0U, // COS_F 0U, // COS_Fp32 0U, // COS_Fp64 0U, // COS_Fp80 0U, // CPUID 0U, // CQO 0U, // CRC32r32m16 0U, // CRC32r32m32 0U, // CRC32r32m8 0U, // CRC32r32r16 0U, // CRC32r32r32 0U, // CRC32r32r8 0U, // CRC32r64m64 0U, // CRC32r64m8 0U, // CRC32r64r64 0U, // CRC32r64r8 0U, // CVTDQ2PDrm 0U, // CVTDQ2PDrr 0U, // CVTDQ2PSrm 0U, // CVTDQ2PSrr 0U, // CVTPD2DQrm 0U, // CVTPD2DQrr 0U, // CVTPD2PSrm 0U, // CVTPD2PSrr 0U, // CVTPS2DQrm 0U, // CVTPS2DQrr 0U, // CVTPS2PDrm 0U, // CVTPS2PDrr 0U, // CVTSD2SI64rm_Int 0U, // CVTSD2SI64rr_Int 0U, // CVTSD2SIrm_Int 0U, // CVTSD2SIrr_Int 0U, // CVTSD2SSrm 0U, // CVTSD2SSrm_Int 0U, // CVTSD2SSrr 0U, // CVTSD2SSrr_Int 0U, // CVTSI2SDrm 0U, // CVTSI2SDrm_Int 0U, // CVTSI2SDrr 0U, // CVTSI2SDrr_Int 0U, // CVTSI2SSrm 0U, // CVTSI2SSrm_Int 0U, // CVTSI2SSrr 0U, // CVTSI2SSrr_Int 0U, // CVTSI642SDrm 0U, // CVTSI642SDrm_Int 0U, // CVTSI642SDrr 0U, // CVTSI642SDrr_Int 0U, // CVTSI642SSrm 0U, // CVTSI642SSrm_Int 0U, // CVTSI642SSrr 0U, // CVTSI642SSrr_Int 0U, // CVTSS2SDrm 0U, // CVTSS2SDrm_Int 0U, // CVTSS2SDrr 0U, // CVTSS2SDrr_Int 0U, // CVTSS2SI64rm_Int 0U, // CVTSS2SI64rr_Int 0U, // CVTSS2SIrm_Int 0U, // CVTSS2SIrr_Int 0U, // CVTTPD2DQrm 0U, // CVTTPD2DQrr 0U, // CVTTPS2DQrm 0U, // CVTTPS2DQrr 0U, // CVTTSD2SI64rm 0U, // CVTTSD2SI64rm_Int 0U, // CVTTSD2SI64rr 0U, // CVTTSD2SI64rr_Int 0U, // CVTTSD2SIrm 0U, // CVTTSD2SIrm_Int 0U, // CVTTSD2SIrr 0U, // CVTTSD2SIrr_Int 0U, // CVTTSS2SI64rm 0U, // CVTTSS2SI64rm_Int 0U, // CVTTSS2SI64rr 0U, // CVTTSS2SI64rr_Int 0U, // CVTTSS2SIrm 0U, // CVTTSS2SIrm_Int 0U, // CVTTSS2SIrr 0U, // CVTTSS2SIrr_Int 0U, // CWD 0U, // CWDE 0U, // DAA 0U, // DAS 0U, // DATA16_PREFIX 0U, // DEC16m 0U, // DEC16r 0U, // DEC16r_alt 0U, // DEC32m 0U, // DEC32r 0U, // DEC32r_alt 0U, // DEC64m 0U, // DEC64r 0U, // DEC8m 0U, // DEC8r 0U, // DIV16m 0U, // DIV16r 0U, // DIV32m 0U, // DIV32r 0U, // DIV64m 0U, // DIV64r 0U, // DIV8m 0U, // DIV8r 0U, // DIVPDrm 0U, // DIVPDrr 0U, // DIVPSrm 0U, // DIVPSrr 0U, // DIVR_F32m 0U, // DIVR_F64m 0U, // DIVR_FI16m 0U, // DIVR_FI32m 0U, // DIVR_FPrST0 0U, // DIVR_FST0r 0U, // DIVR_Fp32m 0U, // DIVR_Fp64m 0U, // DIVR_Fp64m32 0U, // DIVR_Fp80m32 0U, // DIVR_Fp80m64 0U, // DIVR_FpI16m32 0U, // DIVR_FpI16m64 0U, // DIVR_FpI16m80 0U, // DIVR_FpI32m32 0U, // DIVR_FpI32m64 0U, // DIVR_FpI32m80 0U, // DIVR_FrST0 0U, // DIVSDrm 0U, // DIVSDrm_Int 0U, // DIVSDrr 0U, // DIVSDrr_Int 0U, // DIVSSrm 0U, // DIVSSrm_Int 0U, // DIVSSrr 0U, // DIVSSrr_Int 0U, // DIV_F32m 0U, // DIV_F64m 0U, // DIV_FI16m 0U, // DIV_FI32m 0U, // DIV_FPrST0 0U, // DIV_FST0r 0U, // DIV_Fp32 0U, // DIV_Fp32m 0U, // DIV_Fp64 0U, // DIV_Fp64m 0U, // DIV_Fp64m32 0U, // DIV_Fp80 0U, // DIV_Fp80m32 0U, // DIV_Fp80m64 0U, // DIV_FpI16m32 0U, // DIV_FpI16m64 0U, // DIV_FpI16m80 0U, // DIV_FpI32m32 0U, // DIV_FpI32m64 0U, // DIV_FpI32m80 0U, // DIV_FrST0 0U, // DPPDrmi 0U, // DPPDrri 0U, // DPPSrmi 0U, // DPPSrri 0U, // ENCLS 0U, // ENCLU 0U, // ENCLV 0U, // ENDBR32 0U, // ENDBR64 0U, // ENTER 0U, // EXTRACTPSmr 0U, // EXTRACTPSrr 0U, // EXTRQ 0U, // EXTRQI 0U, // F2XM1 0U, // FARCALL16i 0U, // FARCALL16m 0U, // FARCALL32i 0U, // FARCALL32m 0U, // FARCALL64 0U, // FARJMP16i 0U, // FARJMP16m 0U, // FARJMP32i 0U, // FARJMP32m 0U, // FARJMP64 0U, // FBLDm 0U, // FBSTPm 0U, // FCOM32m 0U, // FCOM64m 0U, // FCOMP32m 0U, // FCOMP64m 0U, // FCOMPP 0U, // FDECSTP 0U, // FDISI8087_NOP 0U, // FEMMS 0U, // FENI8087_NOP 0U, // FFREE 0U, // FFREEP 0U, // FICOM16m 0U, // FICOM32m 0U, // FICOMP16m 0U, // FICOMP32m 0U, // FINCSTP 0U, // FLDCW16m 0U, // FLDENVm 0U, // FLDL2E 0U, // FLDL2T 0U, // FLDLG2 0U, // FLDLN2 0U, // FLDPI 0U, // FNCLEX 0U, // FNINIT 0U, // FNOP 0U, // FNSTCW16m 0U, // FNSTSW16r 0U, // FNSTSWm 0U, // FPATAN 0U, // FPNCEST0r 0U, // FPREM 0U, // FPREM1 0U, // FPTAN 0U, // FRNDINT 0U, // FRSTORm 0U, // FSAVEm 0U, // FSCALE 0U, // FSETPM 0U, // FSINCOS 0U, // FSTENVm 0U, // FXAM 0U, // FXRSTOR 0U, // FXRSTOR64 0U, // FXSAVE 0U, // FXSAVE64 0U, // FXTRACT 0U, // FYL2X 0U, // FYL2XP1 0U, // GETSEC 0U, // GF2P8AFFINEINVQBrmi 0U, // GF2P8AFFINEINVQBrri 0U, // GF2P8AFFINEQBrmi 0U, // GF2P8AFFINEQBrri 0U, // GF2P8MULBrm 0U, // GF2P8MULBrr 0U, // HADDPDrm 0U, // HADDPDrr 0U, // HADDPSrm 0U, // HADDPSrr 0U, // HLT 0U, // HSUBPDrm 0U, // HSUBPDrr 0U, // HSUBPSrm 0U, // HSUBPSrr 0U, // IDIV16m 0U, // IDIV16r 0U, // IDIV32m 0U, // IDIV32r 0U, // IDIV64m 0U, // IDIV64r 0U, // IDIV8m 0U, // IDIV8r 0U, // ILD_F16m 0U, // ILD_F32m 0U, // ILD_F64m 0U, // ILD_Fp16m32 0U, // ILD_Fp16m64 0U, // ILD_Fp16m80 0U, // ILD_Fp32m32 0U, // ILD_Fp32m64 0U, // ILD_Fp32m80 0U, // ILD_Fp64m32 0U, // ILD_Fp64m64 0U, // ILD_Fp64m80 0U, // IMUL16m 0U, // IMUL16r 0U, // IMUL16rm 0U, // IMUL16rmi 0U, // IMUL16rmi8 0U, // IMUL16rr 0U, // IMUL16rri 0U, // IMUL16rri8 0U, // IMUL32m 0U, // IMUL32r 0U, // IMUL32rm 0U, // IMUL32rmi 0U, // IMUL32rmi8 0U, // IMUL32rr 0U, // IMUL32rri 0U, // IMUL32rri8 0U, // IMUL64m 0U, // IMUL64r 0U, // IMUL64rm 0U, // IMUL64rmi32 0U, // IMUL64rmi8 0U, // IMUL64rr 0U, // IMUL64rri32 0U, // IMUL64rri8 0U, // IMUL8m 0U, // IMUL8r 0U, // IN16ri 0U, // IN16rr 0U, // IN32ri 0U, // IN32rr 0U, // IN8ri 0U, // IN8rr 0U, // INC16m 0U, // INC16r 0U, // INC16r_alt 0U, // INC32m 0U, // INC32r 0U, // INC32r_alt 0U, // INC64m 0U, // INC64r 0U, // INC8m 0U, // INC8r 0U, // INCSSPD 0U, // INCSSPQ 0U, // INSB 0U, // INSERTPSrm 0U, // INSERTPSrr 0U, // INSERTQ 0U, // INSERTQI 0U, // INSL 0U, // INSW 0U, // INT 0U, // INT1 0U, // INT3 0U, // INTO 0U, // INVD 0U, // INVEPT32 0U, // INVEPT64 0U, // INVLPG 0U, // INVLPGA32 0U, // INVLPGA64 0U, // INVPCID32 0U, // INVPCID64 0U, // INVVPID32 0U, // INVVPID64 0U, // IRET16 0U, // IRET32 0U, // IRET64 0U, // ISTT_FP16m 0U, // ISTT_FP32m 0U, // ISTT_FP64m 0U, // ISTT_Fp16m32 0U, // ISTT_Fp16m64 0U, // ISTT_Fp16m80 0U, // ISTT_Fp32m32 0U, // ISTT_Fp32m64 0U, // ISTT_Fp32m80 0U, // ISTT_Fp64m32 0U, // ISTT_Fp64m64 0U, // ISTT_Fp64m80 0U, // IST_F16m 0U, // IST_F32m 0U, // IST_FP16m 0U, // IST_FP32m 0U, // IST_FP64m 0U, // IST_Fp16m32 0U, // IST_Fp16m64 0U, // IST_Fp16m80 0U, // IST_Fp32m32 0U, // IST_Fp32m64 0U, // IST_Fp32m80 0U, // IST_Fp64m32 0U, // IST_Fp64m64 0U, // IST_Fp64m80 0U, // JAE_1 0U, // JAE_2 0U, // JAE_4 0U, // JA_1 0U, // JA_2 0U, // JA_4 0U, // JBE_1 0U, // JBE_2 0U, // JBE_4 0U, // JB_1 0U, // JB_2 0U, // JB_4 0U, // JCXZ 0U, // JECXZ 0U, // JE_1 0U, // JE_2 0U, // JE_4 0U, // JGE_1 0U, // JGE_2 0U, // JGE_4 0U, // JG_1 0U, // JG_2 0U, // JG_4 0U, // JLE_1 0U, // JLE_2 0U, // JLE_4 0U, // JL_1 0U, // JL_2 0U, // JL_4 0U, // JMP16m 0U, // JMP16m_NT 0U, // JMP16r 0U, // JMP16r_NT 0U, // JMP32m 0U, // JMP32m_NT 0U, // JMP32r 0U, // JMP32r_NT 0U, // JMP64m 0U, // JMP64m_NT 0U, // JMP64r 0U, // JMP64r_NT 0U, // JMP_1 0U, // JMP_2 0U, // JMP_4 0U, // JNE_1 0U, // JNE_2 0U, // JNE_4 0U, // JNO_1 0U, // JNO_2 0U, // JNO_4 0U, // JNP_1 0U, // JNP_2 0U, // JNP_4 0U, // JNS_1 0U, // JNS_2 0U, // JNS_4 0U, // JO_1 0U, // JO_2 0U, // JO_4 0U, // JP_1 0U, // JP_2 0U, // JP_4 0U, // JRCXZ 0U, // JS_1 0U, // JS_2 0U, // JS_4 0U, // KADDBrr 0U, // KADDDrr 0U, // KADDQrr 0U, // KADDWrr 0U, // KANDBrr 0U, // KANDDrr 0U, // KANDNBrr 0U, // KANDNDrr 0U, // KANDNQrr 0U, // KANDNWrr 0U, // KANDQrr 0U, // KANDWrr 0U, // KMOVBkk 0U, // KMOVBkm 0U, // KMOVBkr 0U, // KMOVBmk 0U, // KMOVBrk 0U, // KMOVDkk 0U, // KMOVDkm 0U, // KMOVDkr 0U, // KMOVDmk 0U, // KMOVDrk 0U, // KMOVQkk 0U, // KMOVQkm 0U, // KMOVQkr 0U, // KMOVQmk 0U, // KMOVQrk 0U, // KMOVWkk 0U, // KMOVWkm 0U, // KMOVWkr 0U, // KMOVWmk 0U, // KMOVWrk 0U, // KNOTBrr 0U, // KNOTDrr 0U, // KNOTQrr 0U, // KNOTWrr 0U, // KORBrr 0U, // KORDrr 0U, // KORQrr 0U, // KORTESTBrr 0U, // KORTESTDrr 0U, // KORTESTQrr 0U, // KORTESTWrr 0U, // KORWrr 0U, // KSHIFTLBri 0U, // KSHIFTLDri 0U, // KSHIFTLQri 0U, // KSHIFTLWri 0U, // KSHIFTRBri 0U, // KSHIFTRDri 0U, // KSHIFTRQri 0U, // KSHIFTRWri 0U, // KTESTBrr 0U, // KTESTDrr 0U, // KTESTQrr 0U, // KTESTWrr 0U, // KUNPCKBWrr 0U, // KUNPCKDQrr 0U, // KUNPCKWDrr 0U, // KXNORBrr 0U, // KXNORDrr 0U, // KXNORQrr 0U, // KXNORWrr 0U, // KXORBrr 0U, // KXORDrr 0U, // KXORQrr 0U, // KXORWrr 0U, // LAHF 0U, // LAR16rm 0U, // LAR16rr 0U, // LAR32rm 0U, // LAR32rr 0U, // LAR64rm 0U, // LAR64rr 0U, // LDDQUrm 0U, // LDMXCSR 0U, // LDS16rm 0U, // LDS32rm 0U, // LD_F0 0U, // LD_F1 0U, // LD_F32m 0U, // LD_F64m 0U, // LD_F80m 0U, // LD_Fp032 0U, // LD_Fp064 0U, // LD_Fp080 0U, // LD_Fp132 0U, // LD_Fp164 0U, // LD_Fp180 0U, // LD_Fp32m 0U, // LD_Fp32m64 0U, // LD_Fp32m80 0U, // LD_Fp64m 0U, // LD_Fp64m80 0U, // LD_Fp80m 0U, // LD_Frr 0U, // LEA16r 0U, // LEA32r 0U, // LEA64_32r 0U, // LEA64r 0U, // LEAVE 0U, // LEAVE64 0U, // LES16rm 0U, // LES32rm 0U, // LFENCE 0U, // LFS16rm 0U, // LFS32rm 0U, // LFS64rm 0U, // LGDT16m 0U, // LGDT32m 0U, // LGDT64m 0U, // LGS16rm 0U, // LGS32rm 0U, // LGS64rm 0U, // LIDT16m 0U, // LIDT32m 0U, // LIDT64m 0U, // LLDT16m 0U, // LLDT16r 0U, // LLWPCB 0U, // LLWPCB64 0U, // LMSW16m 0U, // LMSW16r 0U, // LOCK_PREFIX 0U, // LODSB 0U, // LODSL 0U, // LODSQ 0U, // LODSW 0U, // LOOP 0U, // LOOPE 0U, // LOOPNE 0U, // LRETIL 0U, // LRETIQ 0U, // LRETIW 0U, // LRETL 0U, // LRETQ 0U, // LRETW 0U, // LSL16rm 0U, // LSL16rr 0U, // LSL32rm 0U, // LSL32rr 0U, // LSL64rm 0U, // LSL64rr 0U, // LSS16rm 0U, // LSS32rm 0U, // LSS64rm 0U, // LTRm 0U, // LTRr 0U, // LWPINS32rmi 0U, // LWPINS32rri 0U, // LWPINS64rmi 0U, // LWPINS64rri 0U, // LWPVAL32rmi 0U, // LWPVAL32rri 0U, // LWPVAL64rmi 0U, // LWPVAL64rri 0U, // LZCNT16rm 0U, // LZCNT16rr 0U, // LZCNT32rm 0U, // LZCNT32rr 0U, // LZCNT64rm 0U, // LZCNT64rr 0U, // MASKMOVDQU 0U, // MASKMOVDQU64 0U, // MAXCPDrm 0U, // MAXCPDrr 0U, // MAXCPSrm 0U, // MAXCPSrr 0U, // MAXCSDrm 0U, // MAXCSDrr 0U, // MAXCSSrm 0U, // MAXCSSrr 0U, // MAXPDrm 0U, // MAXPDrr 0U, // MAXPSrm 0U, // MAXPSrr 0U, // MAXSDrm 0U, // MAXSDrm_Int 0U, // MAXSDrr 0U, // MAXSDrr_Int 0U, // MAXSSrm 0U, // MAXSSrm_Int 0U, // MAXSSrr 0U, // MAXSSrr_Int 0U, // MFENCE 0U, // MINCPDrm 0U, // MINCPDrr 0U, // MINCPSrm 0U, // MINCPSrr 0U, // MINCSDrm 0U, // MINCSDrr 0U, // MINCSSrm 0U, // MINCSSrr 0U, // MINPDrm 0U, // MINPDrr 0U, // MINPSrm 0U, // MINPSrr 0U, // MINSDrm 0U, // MINSDrm_Int 0U, // MINSDrr 0U, // MINSDrr_Int 0U, // MINSSrm 0U, // MINSSrm_Int 0U, // MINSSrr 0U, // MINSSrr_Int 0U, // MMX_CVTPD2PIirm 0U, // MMX_CVTPD2PIirr 0U, // MMX_CVTPI2PDirm 0U, // MMX_CVTPI2PDirr 0U, // MMX_CVTPI2PSirm 0U, // MMX_CVTPI2PSirr 0U, // MMX_CVTPS2PIirm 0U, // MMX_CVTPS2PIirr 0U, // MMX_CVTTPD2PIirm 0U, // MMX_CVTTPD2PIirr 0U, // MMX_CVTTPS2PIirm 0U, // MMX_CVTTPS2PIirr 0U, // MMX_EMMS 0U, // MMX_MASKMOVQ 0U, // MMX_MASKMOVQ64 0U, // MMX_MOVD64from64rm 0U, // MMX_MOVD64from64rr 0U, // MMX_MOVD64grr 0U, // MMX_MOVD64mr 0U, // MMX_MOVD64rm 0U, // MMX_MOVD64rr 0U, // MMX_MOVD64to64rm 0U, // MMX_MOVD64to64rr 0U, // MMX_MOVDQ2Qrr 0U, // MMX_MOVFR642Qrr 0U, // MMX_MOVNTQmr 0U, // MMX_MOVQ2DQrr 0U, // MMX_MOVQ2FR64rr 0U, // MMX_MOVQ64mr 0U, // MMX_MOVQ64rm 0U, // MMX_MOVQ64rr 0U, // MMX_MOVQ64rr_REV 0U, // MMX_PABSBrm 0U, // MMX_PABSBrr 0U, // MMX_PABSDrm 0U, // MMX_PABSDrr 0U, // MMX_PABSWrm 0U, // MMX_PABSWrr 0U, // MMX_PACKSSDWirm 0U, // MMX_PACKSSDWirr 0U, // MMX_PACKSSWBirm 0U, // MMX_PACKSSWBirr 0U, // MMX_PACKUSWBirm 0U, // MMX_PACKUSWBirr 0U, // MMX_PADDBirm 0U, // MMX_PADDBirr 0U, // MMX_PADDDirm 0U, // MMX_PADDDirr 0U, // MMX_PADDQirm 0U, // MMX_PADDQirr 0U, // MMX_PADDSBirm 0U, // MMX_PADDSBirr 0U, // MMX_PADDSWirm 0U, // MMX_PADDSWirr 0U, // MMX_PADDUSBirm 0U, // MMX_PADDUSBirr 0U, // MMX_PADDUSWirm 0U, // MMX_PADDUSWirr 0U, // MMX_PADDWirm 0U, // MMX_PADDWirr 0U, // MMX_PALIGNRrmi 0U, // MMX_PALIGNRrri 0U, // MMX_PANDNirm 0U, // MMX_PANDNirr 0U, // MMX_PANDirm 0U, // MMX_PANDirr 0U, // MMX_PAVGBirm 0U, // MMX_PAVGBirr 0U, // MMX_PAVGWirm 0U, // MMX_PAVGWirr 0U, // MMX_PCMPEQBirm 0U, // MMX_PCMPEQBirr 0U, // MMX_PCMPEQDirm 0U, // MMX_PCMPEQDirr 0U, // MMX_PCMPEQWirm 0U, // MMX_PCMPEQWirr 0U, // MMX_PCMPGTBirm 0U, // MMX_PCMPGTBirr 0U, // MMX_PCMPGTDirm 0U, // MMX_PCMPGTDirr 0U, // MMX_PCMPGTWirm 0U, // MMX_PCMPGTWirr 0U, // MMX_PEXTRWrr 0U, // MMX_PHADDDrm 0U, // MMX_PHADDDrr 0U, // MMX_PHADDSWrm 0U, // MMX_PHADDSWrr 0U, // MMX_PHADDWrm 0U, // MMX_PHADDWrr 0U, // MMX_PHSUBDrm 0U, // MMX_PHSUBDrr 0U, // MMX_PHSUBSWrm 0U, // MMX_PHSUBSWrr 0U, // MMX_PHSUBWrm 0U, // MMX_PHSUBWrr 0U, // MMX_PINSRWrm 0U, // MMX_PINSRWrr 0U, // MMX_PMADDUBSWrm 0U, // MMX_PMADDUBSWrr 0U, // MMX_PMADDWDirm 0U, // MMX_PMADDWDirr 0U, // MMX_PMAXSWirm 0U, // MMX_PMAXSWirr 0U, // MMX_PMAXUBirm 0U, // MMX_PMAXUBirr 0U, // MMX_PMINSWirm 0U, // MMX_PMINSWirr 0U, // MMX_PMINUBirm 0U, // MMX_PMINUBirr 0U, // MMX_PMOVMSKBrr 0U, // MMX_PMULHRSWrm 0U, // MMX_PMULHRSWrr 0U, // MMX_PMULHUWirm 0U, // MMX_PMULHUWirr 0U, // MMX_PMULHWirm 0U, // MMX_PMULHWirr 0U, // MMX_PMULLWirm 0U, // MMX_PMULLWirr 0U, // MMX_PMULUDQirm 0U, // MMX_PMULUDQirr 0U, // MMX_PORirm 0U, // MMX_PORirr 0U, // MMX_PSADBWirm 0U, // MMX_PSADBWirr 0U, // MMX_PSHUFBrm 0U, // MMX_PSHUFBrr 0U, // MMX_PSHUFWmi 0U, // MMX_PSHUFWri 0U, // MMX_PSIGNBrm 0U, // MMX_PSIGNBrr 0U, // MMX_PSIGNDrm 0U, // MMX_PSIGNDrr 0U, // MMX_PSIGNWrm 0U, // MMX_PSIGNWrr 0U, // MMX_PSLLDri 0U, // MMX_PSLLDrm 0U, // MMX_PSLLDrr 0U, // MMX_PSLLQri 0U, // MMX_PSLLQrm 0U, // MMX_PSLLQrr 0U, // MMX_PSLLWri 0U, // MMX_PSLLWrm 0U, // MMX_PSLLWrr 0U, // MMX_PSRADri 0U, // MMX_PSRADrm 0U, // MMX_PSRADrr 0U, // MMX_PSRAWri 0U, // MMX_PSRAWrm 0U, // MMX_PSRAWrr 0U, // MMX_PSRLDri 0U, // MMX_PSRLDrm 0U, // MMX_PSRLDrr 0U, // MMX_PSRLQri 0U, // MMX_PSRLQrm 0U, // MMX_PSRLQrr 0U, // MMX_PSRLWri 0U, // MMX_PSRLWrm 0U, // MMX_PSRLWrr 0U, // MMX_PSUBBirm 0U, // MMX_PSUBBirr 0U, // MMX_PSUBDirm 0U, // MMX_PSUBDirr 0U, // MMX_PSUBQirm 0U, // MMX_PSUBQirr 0U, // MMX_PSUBSBirm 0U, // MMX_PSUBSBirr 0U, // MMX_PSUBSWirm 0U, // MMX_PSUBSWirr 0U, // MMX_PSUBUSBirm 0U, // MMX_PSUBUSBirr 0U, // MMX_PSUBUSWirm 0U, // MMX_PSUBUSWirr 0U, // MMX_PSUBWirm 0U, // MMX_PSUBWirr 0U, // MMX_PUNPCKHBWirm 0U, // MMX_PUNPCKHBWirr 0U, // MMX_PUNPCKHDQirm 0U, // MMX_PUNPCKHDQirr 0U, // MMX_PUNPCKHWDirm 0U, // MMX_PUNPCKHWDirr 0U, // MMX_PUNPCKLBWirm 0U, // MMX_PUNPCKLBWirr 0U, // MMX_PUNPCKLDQirm 0U, // MMX_PUNPCKLDQirr 0U, // MMX_PUNPCKLWDirm 0U, // MMX_PUNPCKLWDirr 0U, // MMX_PXORirm 0U, // MMX_PXORirr 0U, // MONITORXrrr 0U, // MONITORrrr 0U, // MONTMUL 0U, // MOV16ao16 0U, // MOV16ao32 0U, // MOV16ao64 0U, // MOV16mi 0U, // MOV16mr 0U, // MOV16ms 0U, // MOV16o16a 0U, // MOV16o32a 0U, // MOV16o64a 0U, // MOV16ri 0U, // MOV16ri_alt 0U, // MOV16rm 0U, // MOV16rr 0U, // MOV16rr_REV 0U, // MOV16rs 0U, // MOV16sm 0U, // MOV16sr 0U, // MOV32ao16 0U, // MOV32ao32 0U, // MOV32ao64 0U, // MOV32cr 0U, // MOV32dr 0U, // MOV32mi 0U, // MOV32mr 0U, // MOV32o16a 0U, // MOV32o32a 0U, // MOV32o64a 0U, // MOV32rc 0U, // MOV32rd 0U, // MOV32ri 0U, // MOV32ri_alt 0U, // MOV32rm 0U, // MOV32rr 0U, // MOV32rr_REV 0U, // MOV32rs 0U, // MOV32sr 0U, // MOV64ao32 0U, // MOV64ao64 0U, // MOV64cr 0U, // MOV64dr 0U, // MOV64mi32 0U, // MOV64mr 0U, // MOV64o32a 0U, // MOV64o64a 0U, // MOV64rc 0U, // MOV64rd 0U, // MOV64ri 0U, // MOV64ri32 0U, // MOV64rm 0U, // MOV64rr 0U, // MOV64rr_REV 0U, // MOV64rs 0U, // MOV64sr 0U, // MOV64toPQIrm 0U, // MOV64toPQIrr 0U, // MOV64toSDrm 0U, // MOV64toSDrr 0U, // MOV8ao16 0U, // MOV8ao32 0U, // MOV8ao64 0U, // MOV8mi 0U, // MOV8mr 0U, // MOV8mr_NOREX 0U, // MOV8o16a 0U, // MOV8o32a 0U, // MOV8o64a 0U, // MOV8ri 0U, // MOV8ri_alt 0U, // MOV8rm 0U, // MOV8rm_NOREX 0U, // MOV8rr 0U, // MOV8rr_NOREX 0U, // MOV8rr_REV 0U, // MOVAPDmr 0U, // MOVAPDrm 0U, // MOVAPDrr 0U, // MOVAPDrr_REV 0U, // MOVAPSmr 0U, // MOVAPSrm 0U, // MOVAPSrr 0U, // MOVAPSrr_REV 0U, // MOVBE16mr 0U, // MOVBE16rm 0U, // MOVBE32mr 0U, // MOVBE32rm 0U, // MOVBE64mr 0U, // MOVBE64rm 0U, // MOVDDUPrm 0U, // MOVDDUPrr 0U, // MOVDI2PDIrm 0U, // MOVDI2PDIrr 0U, // MOVDI2SSrm 0U, // MOVDI2SSrr 0U, // MOVDIR64B16 0U, // MOVDIR64B32 0U, // MOVDIR64B64 0U, // MOVDIRI32 0U, // MOVDIRI64 0U, // MOVDQAmr 0U, // MOVDQArm 0U, // MOVDQArr 0U, // MOVDQArr_REV 0U, // MOVDQUmr 0U, // MOVDQUrm 0U, // MOVDQUrr 0U, // MOVDQUrr_REV 0U, // MOVHLPSrr 0U, // MOVHPDmr 0U, // MOVHPDrm 0U, // MOVHPSmr 0U, // MOVHPSrm 0U, // MOVLHPSrr 0U, // MOVLPDmr 0U, // MOVLPDrm 0U, // MOVLPSmr 0U, // MOVLPSrm 0U, // MOVMSKPDrr 0U, // MOVMSKPSrr 0U, // MOVNTDQArm 0U, // MOVNTDQmr 0U, // MOVNTI_64mr 0U, // MOVNTImr 0U, // MOVNTPDmr 0U, // MOVNTPSmr 0U, // MOVNTSD 0U, // MOVNTSS 0U, // MOVPDI2DImr 0U, // MOVPDI2DIrr 0U, // MOVPQI2QImr 0U, // MOVPQI2QIrr 0U, // MOVPQIto64mr 0U, // MOVPQIto64rr 0U, // MOVQI2PQIrm 0U, // MOVSB 0U, // MOVSDmr 0U, // MOVSDrm 0U, // MOVSDrr 0U, // MOVSDrr_REV 0U, // MOVSDto64mr 0U, // MOVSDto64rr 0U, // MOVSHDUPrm 0U, // MOVSHDUPrr 0U, // MOVSL 0U, // MOVSLDUPrm 0U, // MOVSLDUPrr 0U, // MOVSQ 0U, // MOVSS2DImr 0U, // MOVSS2DIrr 0U, // MOVSSmr 0U, // MOVSSrm 0U, // MOVSSrr 0U, // MOVSSrr_REV 0U, // MOVSW 0U, // MOVSX16rm16 0U, // MOVSX16rm8 0U, // MOVSX16rr16 0U, // MOVSX16rr8 0U, // MOVSX32rm16 0U, // MOVSX32rm8 0U, // MOVSX32rm8_NOREX 0U, // MOVSX32rr16 0U, // MOVSX32rr8 0U, // MOVSX32rr8_NOREX 0U, // MOVSX64rm16 0U, // MOVSX64rm32 0U, // MOVSX64rm8 0U, // MOVSX64rr16 0U, // MOVSX64rr32 0U, // MOVSX64rr8 0U, // MOVUPDmr 0U, // MOVUPDrm 0U, // MOVUPDrr 0U, // MOVUPDrr_REV 0U, // MOVUPSmr 0U, // MOVUPSrm 0U, // MOVUPSrr 0U, // MOVUPSrr_REV 0U, // MOVZPQILo2PQIrr 0U, // MOVZX16rm16 0U, // MOVZX16rm8 0U, // MOVZX16rr16 0U, // MOVZX16rr8 0U, // MOVZX32rm16 0U, // MOVZX32rm8 0U, // MOVZX32rm8_NOREX 0U, // MOVZX32rr16 0U, // MOVZX32rr8 0U, // MOVZX32rr8_NOREX 0U, // MOVZX64rm16 0U, // MOVZX64rm8 0U, // MOVZX64rr16 0U, // MOVZX64rr8 0U, // MPSADBWrmi 0U, // MPSADBWrri 0U, // MUL16m 0U, // MUL16r 0U, // MUL32m 0U, // MUL32r 0U, // MUL64m 0U, // MUL64r 0U, // MUL8m 0U, // MUL8r 0U, // MULPDrm 0U, // MULPDrr 0U, // MULPSrm 0U, // MULPSrr 0U, // MULSDrm 0U, // MULSDrm_Int 0U, // MULSDrr 0U, // MULSDrr_Int 0U, // MULSSrm 0U, // MULSSrm_Int 0U, // MULSSrr 0U, // MULSSrr_Int 0U, // MULX32rm 0U, // MULX32rr 0U, // MULX64rm 0U, // MULX64rr 0U, // MUL_F32m 0U, // MUL_F64m 0U, // MUL_FI16m 0U, // MUL_FI32m 0U, // MUL_FPrST0 0U, // MUL_FST0r 0U, // MUL_Fp32 0U, // MUL_Fp32m 0U, // MUL_Fp64 0U, // MUL_Fp64m 0U, // MUL_Fp64m32 0U, // MUL_Fp80 0U, // MUL_Fp80m32 0U, // MUL_Fp80m64 0U, // MUL_FpI16m32 0U, // MUL_FpI16m64 0U, // MUL_FpI16m80 0U, // MUL_FpI32m32 0U, // MUL_FpI32m64 0U, // MUL_FpI32m80 0U, // MUL_FrST0 0U, // MWAITXrrr 0U, // MWAITrr 0U, // NEG16m 0U, // NEG16r 0U, // NEG32m 0U, // NEG32r 0U, // NEG64m 0U, // NEG64r 0U, // NEG8m 0U, // NEG8r 0U, // NOOP 0U, // NOOP18_16m4 0U, // NOOP18_16m5 0U, // NOOP18_16m6 0U, // NOOP18_16m7 0U, // NOOP18_16r4 0U, // NOOP18_16r5 0U, // NOOP18_16r6 0U, // NOOP18_16r7 0U, // NOOP18_m4 0U, // NOOP18_m5 0U, // NOOP18_m6 0U, // NOOP18_m7 0U, // NOOP18_r4 0U, // NOOP18_r5 0U, // NOOP18_r6 0U, // NOOP18_r7 0U, // NOOP19rr 0U, // NOOPL 0U, // NOOPL_19 0U, // NOOPL_1d 0U, // NOOPL_1e 0U, // NOOPLr 0U, // NOOPQ 0U, // NOOPQr 0U, // NOOPW 0U, // NOOPW_19 0U, // NOOPW_1c 0U, // NOOPW_1d 0U, // NOOPW_1e 0U, // NOOPWr 0U, // NOT16m 0U, // NOT16r 0U, // NOT32m 0U, // NOT32r 0U, // NOT64m 0U, // NOT64r 0U, // NOT8m 0U, // NOT8r 0U, // OR16i16 0U, // OR16mi 0U, // OR16mi8 0U, // OR16mr 0U, // OR16ri 0U, // OR16ri8 0U, // OR16rm 0U, // OR16rr 0U, // OR16rr_REV 0U, // OR32i32 0U, // OR32mi 0U, // OR32mi8 0U, // OR32mr 0U, // OR32ri 0U, // OR32ri8 0U, // OR32rm 0U, // OR32rr 0U, // OR32rr_REV 0U, // OR64i32 0U, // OR64mi32 0U, // OR64mi8 0U, // OR64mr 0U, // OR64ri32 0U, // OR64ri8 0U, // OR64rm 0U, // OR64rr 0U, // OR64rr_REV 0U, // OR8i8 0U, // OR8mi 0U, // OR8mi8 0U, // OR8mr 0U, // OR8ri 0U, // OR8ri8 0U, // OR8rm 0U, // OR8rr 0U, // OR8rr_REV 0U, // ORPDrm 0U, // ORPDrr 0U, // ORPSrm 0U, // ORPSrr 0U, // OUT16ir 0U, // OUT16rr 0U, // OUT32ir 0U, // OUT32rr 0U, // OUT8ir 0U, // OUT8rr 0U, // OUTSB 0U, // OUTSL 0U, // OUTSW 0U, // PABSBrm 0U, // PABSBrr 0U, // PABSDrm 0U, // PABSDrr 0U, // PABSWrm 0U, // PABSWrr 0U, // PACKSSDWrm 0U, // PACKSSDWrr 0U, // PACKSSWBrm 0U, // PACKSSWBrr 0U, // PACKUSDWrm 0U, // PACKUSDWrr 0U, // PACKUSWBrm 0U, // PACKUSWBrr 0U, // PADDBrm 0U, // PADDBrr 0U, // PADDDrm 0U, // PADDDrr 0U, // PADDQrm 0U, // PADDQrr 0U, // PADDSBrm 0U, // PADDSBrr 0U, // PADDSWrm 0U, // PADDSWrr 0U, // PADDUSBrm 0U, // PADDUSBrr 0U, // PADDUSWrm 0U, // PADDUSWrr 0U, // PADDWrm 0U, // PADDWrr 0U, // PALIGNRrmi 0U, // PALIGNRrri 0U, // PANDNrm 0U, // PANDNrr 0U, // PANDrm 0U, // PANDrr 0U, // PAUSE 0U, // PAVGBrm 0U, // PAVGBrr 0U, // PAVGUSBrm 0U, // PAVGUSBrr 0U, // PAVGWrm 0U, // PAVGWrr 0U, // PBLENDVBrm0 0U, // PBLENDVBrr0 0U, // PBLENDWrmi 0U, // PBLENDWrri 0U, // PCLMULQDQrm 0U, // PCLMULQDQrr 0U, // PCMPEQBrm 0U, // PCMPEQBrr 0U, // PCMPEQDrm 0U, // PCMPEQDrr 0U, // PCMPEQQrm 0U, // PCMPEQQrr 0U, // PCMPEQWrm 0U, // PCMPEQWrr 0U, // PCMPESTRIrm 0U, // PCMPESTRIrr 0U, // PCMPESTRMrm 0U, // PCMPESTRMrr 0U, // PCMPGTBrm 0U, // PCMPGTBrr 0U, // PCMPGTDrm 0U, // PCMPGTDrr 0U, // PCMPGTQrm 0U, // PCMPGTQrr 0U, // PCMPGTWrm 0U, // PCMPGTWrr 0U, // PCMPISTRIrm 0U, // PCMPISTRIrr 0U, // PCMPISTRMrm 0U, // PCMPISTRMrr 0U, // PCONFIG 0U, // PDEP32rm 0U, // PDEP32rr 0U, // PDEP64rm 0U, // PDEP64rr 0U, // PEXT32rm 0U, // PEXT32rr 0U, // PEXT64rm 0U, // PEXT64rr 0U, // PEXTRBmr 0U, // PEXTRBrr 0U, // PEXTRDmr 0U, // PEXTRDrr 0U, // PEXTRQmr 0U, // PEXTRQrr 0U, // PEXTRWmr 0U, // PEXTRWrr 0U, // PEXTRWrr_REV 0U, // PF2IDrm 0U, // PF2IDrr 0U, // PF2IWrm 0U, // PF2IWrr 0U, // PFACCrm 0U, // PFACCrr 0U, // PFADDrm 0U, // PFADDrr 0U, // PFCMPEQrm 0U, // PFCMPEQrr 0U, // PFCMPGErm 0U, // PFCMPGErr 0U, // PFCMPGTrm 0U, // PFCMPGTrr 0U, // PFMAXrm 0U, // PFMAXrr 0U, // PFMINrm 0U, // PFMINrr 0U, // PFMULrm 0U, // PFMULrr 0U, // PFNACCrm 0U, // PFNACCrr 0U, // PFPNACCrm 0U, // PFPNACCrr 0U, // PFRCPIT1rm 0U, // PFRCPIT1rr 0U, // PFRCPIT2rm 0U, // PFRCPIT2rr 0U, // PFRCPrm 0U, // PFRCPrr 0U, // PFRSQIT1rm 0U, // PFRSQIT1rr 0U, // PFRSQRTrm 0U, // PFRSQRTrr 0U, // PFSUBRrm 0U, // PFSUBRrr 0U, // PFSUBrm 0U, // PFSUBrr 0U, // PHADDDrm 0U, // PHADDDrr 0U, // PHADDSWrm 0U, // PHADDSWrr 0U, // PHADDWrm 0U, // PHADDWrr 0U, // PHMINPOSUWrm 0U, // PHMINPOSUWrr 0U, // PHSUBDrm 0U, // PHSUBDrr 0U, // PHSUBSWrm 0U, // PHSUBSWrr 0U, // PHSUBWrm 0U, // PHSUBWrr 0U, // PI2FDrm 0U, // PI2FDrr 0U, // PI2FWrm 0U, // PI2FWrr 0U, // PINSRBrm 0U, // PINSRBrr 0U, // PINSRDrm 0U, // PINSRDrr 0U, // PINSRQrm 0U, // PINSRQrr 0U, // PINSRWrm 0U, // PINSRWrr 0U, // PMADDUBSWrm 0U, // PMADDUBSWrr 0U, // PMADDWDrm 0U, // PMADDWDrr 0U, // PMAXSBrm 0U, // PMAXSBrr 0U, // PMAXSDrm 0U, // PMAXSDrr 0U, // PMAXSWrm 0U, // PMAXSWrr 0U, // PMAXUBrm 0U, // PMAXUBrr 0U, // PMAXUDrm 0U, // PMAXUDrr 0U, // PMAXUWrm 0U, // PMAXUWrr 0U, // PMINSBrm 0U, // PMINSBrr 0U, // PMINSDrm 0U, // PMINSDrr 0U, // PMINSWrm 0U, // PMINSWrr 0U, // PMINUBrm 0U, // PMINUBrr 0U, // PMINUDrm 0U, // PMINUDrr 0U, // PMINUWrm 0U, // PMINUWrr 0U, // PMOVMSKBrr 0U, // PMOVSXBDrm 0U, // PMOVSXBDrr 0U, // PMOVSXBQrm 0U, // PMOVSXBQrr 0U, // PMOVSXBWrm 0U, // PMOVSXBWrr 0U, // PMOVSXDQrm 0U, // PMOVSXDQrr 0U, // PMOVSXWDrm 0U, // PMOVSXWDrr 0U, // PMOVSXWQrm 0U, // PMOVSXWQrr 0U, // PMOVZXBDrm 0U, // PMOVZXBDrr 0U, // PMOVZXBQrm 0U, // PMOVZXBQrr 0U, // PMOVZXBWrm 0U, // PMOVZXBWrr 0U, // PMOVZXDQrm 0U, // PMOVZXDQrr 0U, // PMOVZXWDrm 0U, // PMOVZXWDrr 0U, // PMOVZXWQrm 0U, // PMOVZXWQrr 0U, // PMULDQrm 0U, // PMULDQrr 0U, // PMULHRSWrm 0U, // PMULHRSWrr 0U, // PMULHRWrm 0U, // PMULHRWrr 0U, // PMULHUWrm 0U, // PMULHUWrr 0U, // PMULHWrm 0U, // PMULHWrr 0U, // PMULLDrm 0U, // PMULLDrr 0U, // PMULLWrm 0U, // PMULLWrr 0U, // PMULUDQrm 0U, // PMULUDQrr 0U, // POP16r 0U, // POP16rmm 0U, // POP16rmr 0U, // POP32r 0U, // POP32rmm 0U, // POP32rmr 0U, // POP64r 0U, // POP64rmm 0U, // POP64rmr 0U, // POPA16 0U, // POPA32 0U, // POPCNT16rm 0U, // POPCNT16rr 0U, // POPCNT32rm 0U, // POPCNT32rr 0U, // POPCNT64rm 0U, // POPCNT64rr 0U, // POPDS16 0U, // POPDS32 0U, // POPES16 0U, // POPES32 0U, // POPF16 0U, // POPF32 0U, // POPF64 0U, // POPFS16 0U, // POPFS32 0U, // POPFS64 0U, // POPGS16 0U, // POPGS32 0U, // POPGS64 0U, // POPSS16 0U, // POPSS32 0U, // PORrm 0U, // PORrr 0U, // PREFETCH 0U, // PREFETCHNTA 0U, // PREFETCHT0 0U, // PREFETCHT1 0U, // PREFETCHT2 0U, // PREFETCHW 0U, // PREFETCHWT1 0U, // PSADBWrm 0U, // PSADBWrr 0U, // PSHUFBrm 0U, // PSHUFBrr 0U, // PSHUFDmi 0U, // PSHUFDri 0U, // PSHUFHWmi 0U, // PSHUFHWri 0U, // PSHUFLWmi 0U, // PSHUFLWri 0U, // PSIGNBrm 0U, // PSIGNBrr 0U, // PSIGNDrm 0U, // PSIGNDrr 0U, // PSIGNWrm 0U, // PSIGNWrr 0U, // PSLLDQri 0U, // PSLLDri 0U, // PSLLDrm 0U, // PSLLDrr 0U, // PSLLQri 0U, // PSLLQrm 0U, // PSLLQrr 0U, // PSLLWri 0U, // PSLLWrm 0U, // PSLLWrr 0U, // PSRADri 0U, // PSRADrm 0U, // PSRADrr 0U, // PSRAWri 0U, // PSRAWrm 0U, // PSRAWrr 0U, // PSRLDQri 0U, // PSRLDri 0U, // PSRLDrm 0U, // PSRLDrr 0U, // PSRLQri 0U, // PSRLQrm 0U, // PSRLQrr 0U, // PSRLWri 0U, // PSRLWrm 0U, // PSRLWrr 0U, // PSUBBrm 0U, // PSUBBrr 0U, // PSUBDrm 0U, // PSUBDrr 0U, // PSUBQrm 0U, // PSUBQrr 0U, // PSUBSBrm 0U, // PSUBSBrr 0U, // PSUBSWrm 0U, // PSUBSWrr 0U, // PSUBUSBrm 0U, // PSUBUSBrr 0U, // PSUBUSWrm 0U, // PSUBUSWrr 0U, // PSUBWrm 0U, // PSUBWrr 0U, // PSWAPDrm 0U, // PSWAPDrr 0U, // PTESTrm 0U, // PTESTrr 0U, // PTWRITE64m 0U, // PTWRITE64r 0U, // PTWRITEm 0U, // PTWRITEr 0U, // PUNPCKHBWrm 0U, // PUNPCKHBWrr 0U, // PUNPCKHDQrm 0U, // PUNPCKHDQrr 0U, // PUNPCKHQDQrm 0U, // PUNPCKHQDQrr 0U, // PUNPCKHWDrm 0U, // PUNPCKHWDrr 0U, // PUNPCKLBWrm 0U, // PUNPCKLBWrr 0U, // PUNPCKLDQrm 0U, // PUNPCKLDQrr 0U, // PUNPCKLQDQrm 0U, // PUNPCKLQDQrr 0U, // PUNPCKLWDrm 0U, // PUNPCKLWDrr 0U, // PUSH16i8 0U, // PUSH16r 0U, // PUSH16rmm 0U, // PUSH16rmr 0U, // PUSH32i8 0U, // PUSH32r 0U, // PUSH32rmm 0U, // PUSH32rmr 0U, // PUSH64i32 0U, // PUSH64i8 0U, // PUSH64r 0U, // PUSH64rmm 0U, // PUSH64rmr 0U, // PUSHA16 0U, // PUSHA32 0U, // PUSHCS16 0U, // PUSHCS32 0U, // PUSHDS16 0U, // PUSHDS32 0U, // PUSHES16 0U, // PUSHES32 0U, // PUSHF16 0U, // PUSHF32 0U, // PUSHF64 0U, // PUSHFS16 0U, // PUSHFS32 0U, // PUSHFS64 0U, // PUSHGS16 0U, // PUSHGS32 0U, // PUSHGS64 0U, // PUSHSS16 0U, // PUSHSS32 0U, // PUSHi16 0U, // PUSHi32 0U, // PXORrm 0U, // PXORrr 0U, // RCL16m1 0U, // RCL16mCL 0U, // RCL16mi 0U, // RCL16r1 0U, // RCL16rCL 0U, // RCL16ri 0U, // RCL32m1 0U, // RCL32mCL 0U, // RCL32mi 0U, // RCL32r1 0U, // RCL32rCL 0U, // RCL32ri 0U, // RCL64m1 0U, // RCL64mCL 0U, // RCL64mi 0U, // RCL64r1 0U, // RCL64rCL 0U, // RCL64ri 0U, // RCL8m1 0U, // RCL8mCL 0U, // RCL8mi 0U, // RCL8r1 0U, // RCL8rCL 0U, // RCL8ri 0U, // RCPPSm 0U, // RCPPSr 0U, // RCPSSm 0U, // RCPSSm_Int 0U, // RCPSSr 0U, // RCPSSr_Int 0U, // RCR16m1 0U, // RCR16mCL 0U, // RCR16mi 0U, // RCR16r1 0U, // RCR16rCL 0U, // RCR16ri 0U, // RCR32m1 0U, // RCR32mCL 0U, // RCR32mi 0U, // RCR32r1 0U, // RCR32rCL 0U, // RCR32ri 0U, // RCR64m1 0U, // RCR64mCL 0U, // RCR64mi 0U, // RCR64r1 0U, // RCR64rCL 0U, // RCR64ri 0U, // RCR8m1 0U, // RCR8mCL 0U, // RCR8mi 0U, // RCR8r1 0U, // RCR8rCL 0U, // RCR8ri 0U, // RDFSBASE 0U, // RDFSBASE64 0U, // RDGSBASE 0U, // RDGSBASE64 0U, // RDMSR 0U, // RDPID32 0U, // RDPID64 0U, // RDPKRUr 0U, // RDPMC 0U, // RDRAND16r 0U, // RDRAND32r 0U, // RDRAND64r 0U, // RDSEED16r 0U, // RDSEED32r 0U, // RDSEED64r 0U, // RDSSPD 0U, // RDSSPQ 0U, // RDTSC 0U, // RDTSCP 0U, // REPNE_PREFIX 0U, // REP_PREFIX 0U, // RETIL 0U, // RETIQ 0U, // RETIW 0U, // RETL 0U, // RETQ 0U, // RETW 0U, // REX64_PREFIX 0U, // ROL16m1 0U, // ROL16mCL 0U, // ROL16mi 0U, // ROL16r1 0U, // ROL16rCL 0U, // ROL16ri 0U, // ROL32m1 0U, // ROL32mCL 0U, // ROL32mi 0U, // ROL32r1 0U, // ROL32rCL 0U, // ROL32ri 0U, // ROL64m1 0U, // ROL64mCL 0U, // ROL64mi 0U, // ROL64r1 0U, // ROL64rCL 0U, // ROL64ri 0U, // ROL8m1 0U, // ROL8mCL 0U, // ROL8mi 0U, // ROL8r1 0U, // ROL8rCL 0U, // ROL8ri 0U, // ROR16m1 0U, // ROR16mCL 0U, // ROR16mi 0U, // ROR16r1 0U, // ROR16rCL 0U, // ROR16ri 0U, // ROR32m1 0U, // ROR32mCL 0U, // ROR32mi 0U, // ROR32r1 0U, // ROR32rCL 0U, // ROR32ri 0U, // ROR64m1 0U, // ROR64mCL 0U, // ROR64mi 0U, // ROR64r1 0U, // ROR64rCL 0U, // ROR64ri 0U, // ROR8m1 0U, // ROR8mCL 0U, // ROR8mi 0U, // ROR8r1 0U, // ROR8rCL 0U, // ROR8ri 0U, // RORX32mi 0U, // RORX32ri 0U, // RORX64mi 0U, // RORX64ri 0U, // ROUNDPDm 0U, // ROUNDPDr 0U, // ROUNDPSm 0U, // ROUNDPSr 0U, // ROUNDSDm 0U, // ROUNDSDm_Int 0U, // ROUNDSDr 0U, // ROUNDSDr_Int 0U, // ROUNDSSm 0U, // ROUNDSSm_Int 0U, // ROUNDSSr 0U, // ROUNDSSr_Int 0U, // RSM 0U, // RSQRTPSm 0U, // RSQRTPSr 0U, // RSQRTSSm 0U, // RSQRTSSm_Int 0U, // RSQRTSSr 0U, // RSQRTSSr_Int 0U, // RSTORSSP 0U, // SAHF 0U, // SAL16m1 0U, // SAL16mCL 0U, // SAL16mi 0U, // SAL16r1 0U, // SAL16rCL 0U, // SAL16ri 0U, // SAL32m1 0U, // SAL32mCL 0U, // SAL32mi 0U, // SAL32r1 0U, // SAL32rCL 0U, // SAL32ri 0U, // SAL64m1 0U, // SAL64mCL 0U, // SAL64mi 0U, // SAL64r1 0U, // SAL64rCL 0U, // SAL64ri 0U, // SAL8m1 0U, // SAL8mCL 0U, // SAL8mi 0U, // SAL8r1 0U, // SAL8rCL 0U, // SAL8ri 0U, // SALC 0U, // SAR16m1 0U, // SAR16mCL 0U, // SAR16mi 0U, // SAR16r1 0U, // SAR16rCL 0U, // SAR16ri 0U, // SAR32m1 0U, // SAR32mCL 0U, // SAR32mi 0U, // SAR32r1 0U, // SAR32rCL 0U, // SAR32ri 0U, // SAR64m1 0U, // SAR64mCL 0U, // SAR64mi 0U, // SAR64r1 0U, // SAR64rCL 0U, // SAR64ri 0U, // SAR8m1 0U, // SAR8mCL 0U, // SAR8mi 0U, // SAR8r1 0U, // SAR8rCL 0U, // SAR8ri 0U, // SARX32rm 0U, // SARX32rr 0U, // SARX64rm 0U, // SARX64rr 0U, // SAVEPREVSSP 0U, // SBB16i16 0U, // SBB16mi 0U, // SBB16mi8 0U, // SBB16mr 0U, // SBB16ri 0U, // SBB16ri8 0U, // SBB16rm 0U, // SBB16rr 0U, // SBB16rr_REV 0U, // SBB32i32 0U, // SBB32mi 0U, // SBB32mi8 0U, // SBB32mr 0U, // SBB32ri 0U, // SBB32ri8 0U, // SBB32rm 0U, // SBB32rr 0U, // SBB32rr_REV 0U, // SBB64i32 0U, // SBB64mi32 0U, // SBB64mi8 0U, // SBB64mr 0U, // SBB64ri32 0U, // SBB64ri8 0U, // SBB64rm 0U, // SBB64rr 0U, // SBB64rr_REV 0U, // SBB8i8 0U, // SBB8mi 0U, // SBB8mi8 0U, // SBB8mr 0U, // SBB8ri 0U, // SBB8ri8 0U, // SBB8rm 0U, // SBB8rr 0U, // SBB8rr_REV 0U, // SCASB 0U, // SCASL 0U, // SCASQ 0U, // SCASW 0U, // SETAEm 0U, // SETAEr 0U, // SETAm 0U, // SETAr 0U, // SETBEm 0U, // SETBEr 0U, // SETBm 0U, // SETBr 0U, // SETEm 0U, // SETEr 0U, // SETGEm 0U, // SETGEr 0U, // SETGm 0U, // SETGr 0U, // SETLEm 0U, // SETLEr 0U, // SETLm 0U, // SETLr 0U, // SETNEm 0U, // SETNEr 0U, // SETNOm 0U, // SETNOr 0U, // SETNPm 0U, // SETNPr 0U, // SETNSm 0U, // SETNSr 0U, // SETOm 0U, // SETOr 0U, // SETPm 0U, // SETPr 0U, // SETSSBSY 0U, // SETSm 0U, // SETSr 0U, // SFENCE 0U, // SGDT16m 0U, // SGDT32m 0U, // SGDT64m 0U, // SHA1MSG1rm 0U, // SHA1MSG1rr 0U, // SHA1MSG2rm 0U, // SHA1MSG2rr 0U, // SHA1NEXTErm 0U, // SHA1NEXTErr 0U, // SHA1RNDS4rmi 0U, // SHA1RNDS4rri 0U, // SHA256MSG1rm 0U, // SHA256MSG1rr 0U, // SHA256MSG2rm 0U, // SHA256MSG2rr 0U, // SHA256RNDS2rm 0U, // SHA256RNDS2rr 0U, // SHL16m1 0U, // SHL16mCL 0U, // SHL16mi 0U, // SHL16r1 0U, // SHL16rCL 0U, // SHL16ri 0U, // SHL32m1 0U, // SHL32mCL 0U, // SHL32mi 0U, // SHL32r1 0U, // SHL32rCL 0U, // SHL32ri 0U, // SHL64m1 0U, // SHL64mCL 0U, // SHL64mi 0U, // SHL64r1 0U, // SHL64rCL 0U, // SHL64ri 0U, // SHL8m1 0U, // SHL8mCL 0U, // SHL8mi 0U, // SHL8r1 0U, // SHL8rCL 0U, // SHL8ri 0U, // SHLD16mrCL 0U, // SHLD16mri8 0U, // SHLD16rrCL 0U, // SHLD16rri8 0U, // SHLD32mrCL 0U, // SHLD32mri8 0U, // SHLD32rrCL 0U, // SHLD32rri8 0U, // SHLD64mrCL 0U, // SHLD64mri8 0U, // SHLD64rrCL 0U, // SHLD64rri8 0U, // SHLX32rm 0U, // SHLX32rr 0U, // SHLX64rm 0U, // SHLX64rr 0U, // SHR16m1 0U, // SHR16mCL 0U, // SHR16mi 0U, // SHR16r1 0U, // SHR16rCL 0U, // SHR16ri 0U, // SHR32m1 0U, // SHR32mCL 0U, // SHR32mi 0U, // SHR32r1 0U, // SHR32rCL 0U, // SHR32ri 0U, // SHR64m1 0U, // SHR64mCL 0U, // SHR64mi 0U, // SHR64r1 0U, // SHR64rCL 0U, // SHR64ri 0U, // SHR8m1 0U, // SHR8mCL 0U, // SHR8mi 0U, // SHR8r1 0U, // SHR8rCL 0U, // SHR8ri 0U, // SHRD16mrCL 0U, // SHRD16mri8 0U, // SHRD16rrCL 0U, // SHRD16rri8 0U, // SHRD32mrCL 0U, // SHRD32mri8 0U, // SHRD32rrCL 0U, // SHRD32rri8 0U, // SHRD64mrCL 0U, // SHRD64mri8 0U, // SHRD64rrCL 0U, // SHRD64rri8 0U, // SHRX32rm 0U, // SHRX32rr 0U, // SHRX64rm 0U, // SHRX64rr 0U, // SHUFPDrmi 0U, // SHUFPDrri 0U, // SHUFPSrmi 0U, // SHUFPSrri 0U, // SIDT16m 0U, // SIDT32m 0U, // SIDT64m 0U, // SIN_F 0U, // SIN_Fp32 0U, // SIN_Fp64 0U, // SIN_Fp80 0U, // SKINIT 0U, // SLDT16m 0U, // SLDT16r 0U, // SLDT32r 0U, // SLDT64r 0U, // SLWPCB 0U, // SLWPCB64 0U, // SMSW16m 0U, // SMSW16r 0U, // SMSW32r 0U, // SMSW64r 0U, // SQRTPDm 0U, // SQRTPDr 0U, // SQRTPSm 0U, // SQRTPSr 0U, // SQRTSDm 0U, // SQRTSDm_Int 0U, // SQRTSDr 0U, // SQRTSDr_Int 0U, // SQRTSSm 0U, // SQRTSSm_Int 0U, // SQRTSSr 0U, // SQRTSSr_Int 0U, // SQRT_F 0U, // SQRT_Fp32 0U, // SQRT_Fp64 0U, // SQRT_Fp80 0U, // STAC 0U, // STC 0U, // STD 0U, // STGI 0U, // STI 0U, // STMXCSR 0U, // STOSB 0U, // STOSL 0U, // STOSQ 0U, // STOSW 0U, // STR16r 0U, // STR32r 0U, // STR64r 0U, // STRm 0U, // ST_F32m 0U, // ST_F64m 0U, // ST_FP32m 0U, // ST_FP64m 0U, // ST_FP80m 0U, // ST_FPrr 0U, // ST_Fp32m 0U, // ST_Fp64m 0U, // ST_Fp64m32 0U, // ST_Fp80m32 0U, // ST_Fp80m64 0U, // ST_FpP32m 0U, // ST_FpP64m 0U, // ST_FpP64m32 0U, // ST_FpP80m 0U, // ST_FpP80m32 0U, // ST_FpP80m64 0U, // ST_Frr 0U, // SUB16i16 0U, // SUB16mi 0U, // SUB16mi8 0U, // SUB16mr 0U, // SUB16ri 0U, // SUB16ri8 0U, // SUB16rm 0U, // SUB16rr 0U, // SUB16rr_REV 0U, // SUB32i32 0U, // SUB32mi 0U, // SUB32mi8 0U, // SUB32mr 0U, // SUB32ri 0U, // SUB32ri8 0U, // SUB32rm 0U, // SUB32rr 0U, // SUB32rr_REV 0U, // SUB64i32 0U, // SUB64mi32 0U, // SUB64mi8 0U, // SUB64mr 0U, // SUB64ri32 0U, // SUB64ri8 0U, // SUB64rm 0U, // SUB64rr 0U, // SUB64rr_REV 0U, // SUB8i8 0U, // SUB8mi 0U, // SUB8mi8 0U, // SUB8mr 0U, // SUB8ri 0U, // SUB8ri8 0U, // SUB8rm 0U, // SUB8rr 0U, // SUB8rr_REV 0U, // SUBPDrm 0U, // SUBPDrr 0U, // SUBPSrm 0U, // SUBPSrr 0U, // SUBR_F32m 0U, // SUBR_F64m 0U, // SUBR_FI16m 0U, // SUBR_FI32m 0U, // SUBR_FPrST0 0U, // SUBR_FST0r 0U, // SUBR_Fp32m 0U, // SUBR_Fp64m 0U, // SUBR_Fp64m32 0U, // SUBR_Fp80m32 0U, // SUBR_Fp80m64 0U, // SUBR_FpI16m32 0U, // SUBR_FpI16m64 0U, // SUBR_FpI16m80 0U, // SUBR_FpI32m32 0U, // SUBR_FpI32m64 0U, // SUBR_FpI32m80 0U, // SUBR_FrST0 0U, // SUBSDrm 0U, // SUBSDrm_Int 0U, // SUBSDrr 0U, // SUBSDrr_Int 0U, // SUBSSrm 0U, // SUBSSrm_Int 0U, // SUBSSrr 0U, // SUBSSrr_Int 0U, // SUB_F32m 0U, // SUB_F64m 0U, // SUB_FI16m 0U, // SUB_FI32m 0U, // SUB_FPrST0 0U, // SUB_FST0r 0U, // SUB_Fp32 0U, // SUB_Fp32m 0U, // SUB_Fp64 0U, // SUB_Fp64m 0U, // SUB_Fp64m32 0U, // SUB_Fp80 0U, // SUB_Fp80m32 0U, // SUB_Fp80m64 0U, // SUB_FpI16m32 0U, // SUB_FpI16m64 0U, // SUB_FpI16m80 0U, // SUB_FpI32m32 0U, // SUB_FpI32m64 0U, // SUB_FpI32m80 0U, // SUB_FrST0 0U, // SWAPGS 0U, // SYSCALL 0U, // SYSENTER 0U, // SYSEXIT 0U, // SYSEXIT64 0U, // SYSRET 0U, // SYSRET64 0U, // T1MSKC32rm 0U, // T1MSKC32rr 0U, // T1MSKC64rm 0U, // T1MSKC64rr 0U, // TEST16i16 0U, // TEST16mi 0U, // TEST16mi_alt 0U, // TEST16mr 0U, // TEST16ri 0U, // TEST16ri_alt 0U, // TEST16rr 0U, // TEST32i32 0U, // TEST32mi 0U, // TEST32mi_alt 0U, // TEST32mr 0U, // TEST32ri 0U, // TEST32ri_alt 0U, // TEST32rr 0U, // TEST64i32 0U, // TEST64mi32 0U, // TEST64mi32_alt 0U, // TEST64mr 0U, // TEST64ri32 0U, // TEST64ri32_alt 0U, // TEST64rr 0U, // TEST8i8 0U, // TEST8mi 0U, // TEST8mi_alt 0U, // TEST8mr 0U, // TEST8ri 0U, // TEST8ri_alt 0U, // TEST8rr 0U, // TPAUSE 0U, // TST_F 0U, // TST_Fp32 0U, // TST_Fp64 0U, // TST_Fp80 0U, // TZCNT16rm 0U, // TZCNT16rr 0U, // TZCNT32rm 0U, // TZCNT32rr 0U, // TZCNT64rm 0U, // TZCNT64rr 0U, // TZMSK32rm 0U, // TZMSK32rr 0U, // TZMSK64rm 0U, // TZMSK64rr 0U, // UCOMISDrm 0U, // UCOMISDrm_Int 0U, // UCOMISDrr 0U, // UCOMISDrr_Int 0U, // UCOMISSrm 0U, // UCOMISSrm_Int 0U, // UCOMISSrr 0U, // UCOMISSrr_Int 0U, // UCOM_FIPr 0U, // UCOM_FIr 0U, // UCOM_FPPr 0U, // UCOM_FPr 0U, // UCOM_FpIr32 0U, // UCOM_FpIr64 0U, // UCOM_FpIr80 0U, // UCOM_Fpr32 0U, // UCOM_Fpr64 0U, // UCOM_Fpr80 0U, // UCOM_Fr 0U, // UD0 0U, // UD1 0U, // UD2 0U, // UMONITOR16 0U, // UMONITOR32 0U, // UMONITOR64 0U, // UMWAIT 0U, // UNPCKHPDrm 0U, // UNPCKHPDrr 0U, // UNPCKHPSrm 0U, // UNPCKHPSrr 0U, // UNPCKLPDrm 0U, // UNPCKLPDrr 0U, // UNPCKLPSrm 0U, // UNPCKLPSrr 0U, // V4FMADDPSrm 0U, // V4FMADDPSrmk 0U, // V4FMADDPSrmkz 0U, // V4FMADDSSrm 0U, // V4FMADDSSrmk 0U, // V4FMADDSSrmkz 0U, // V4FNMADDPSrm 0U, // V4FNMADDPSrmk 0U, // V4FNMADDPSrmkz 0U, // V4FNMADDSSrm 0U, // V4FNMADDSSrmk 0U, // V4FNMADDSSrmkz 0U, // VADDPDYrm 0U, // VADDPDYrr 0U, // VADDPDZ128rm 0U, // VADDPDZ128rmb 0U, // VADDPDZ128rmbk 0U, // VADDPDZ128rmbkz 0U, // VADDPDZ128rmk 0U, // VADDPDZ128rmkz 0U, // VADDPDZ128rr 0U, // VADDPDZ128rrk 0U, // VADDPDZ128rrkz 0U, // VADDPDZ256rm 0U, // VADDPDZ256rmb 0U, // VADDPDZ256rmbk 0U, // VADDPDZ256rmbkz 0U, // VADDPDZ256rmk 0U, // VADDPDZ256rmkz 0U, // VADDPDZ256rr 0U, // VADDPDZ256rrk 0U, // VADDPDZ256rrkz 0U, // VADDPDZrm 0U, // VADDPDZrmb 0U, // VADDPDZrmbk 0U, // VADDPDZrmbkz 0U, // VADDPDZrmk 0U, // VADDPDZrmkz 0U, // VADDPDZrr 0U, // VADDPDZrrb 0U, // VADDPDZrrbk 0U, // VADDPDZrrbkz 0U, // VADDPDZrrk 0U, // VADDPDZrrkz 0U, // VADDPDrm 0U, // VADDPDrr 0U, // VADDPSYrm 0U, // VADDPSYrr 0U, // VADDPSZ128rm 0U, // VADDPSZ128rmb 0U, // VADDPSZ128rmbk 0U, // VADDPSZ128rmbkz 0U, // VADDPSZ128rmk 0U, // VADDPSZ128rmkz 0U, // VADDPSZ128rr 0U, // VADDPSZ128rrk 0U, // VADDPSZ128rrkz 0U, // VADDPSZ256rm 0U, // VADDPSZ256rmb 0U, // VADDPSZ256rmbk 0U, // VADDPSZ256rmbkz 0U, // VADDPSZ256rmk 0U, // VADDPSZ256rmkz 0U, // VADDPSZ256rr 0U, // VADDPSZ256rrk 0U, // VADDPSZ256rrkz 0U, // VADDPSZrm 0U, // VADDPSZrmb 0U, // VADDPSZrmbk 0U, // VADDPSZrmbkz 0U, // VADDPSZrmk 0U, // VADDPSZrmkz 0U, // VADDPSZrr 0U, // VADDPSZrrb 0U, // VADDPSZrrbk 0U, // VADDPSZrrbkz 0U, // VADDPSZrrk 0U, // VADDPSZrrkz 0U, // VADDPSrm 0U, // VADDPSrr 0U, // VADDSDZrm 0U, // VADDSDZrm_Int 0U, // VADDSDZrm_Intk 0U, // VADDSDZrm_Intkz 0U, // VADDSDZrr 0U, // VADDSDZrr_Int 0U, // VADDSDZrr_Intk 0U, // VADDSDZrr_Intkz 0U, // VADDSDZrrb_Int 0U, // VADDSDZrrb_Intk 0U, // VADDSDZrrb_Intkz 0U, // VADDSDrm 0U, // VADDSDrm_Int 0U, // VADDSDrr 0U, // VADDSDrr_Int 0U, // VADDSSZrm 0U, // VADDSSZrm_Int 0U, // VADDSSZrm_Intk 0U, // VADDSSZrm_Intkz 0U, // VADDSSZrr 0U, // VADDSSZrr_Int 0U, // VADDSSZrr_Intk 0U, // VADDSSZrr_Intkz 0U, // VADDSSZrrb_Int 0U, // VADDSSZrrb_Intk 0U, // VADDSSZrrb_Intkz 0U, // VADDSSrm 0U, // VADDSSrm_Int 0U, // VADDSSrr 0U, // VADDSSrr_Int 0U, // VADDSUBPDYrm 0U, // VADDSUBPDYrr 0U, // VADDSUBPDrm 0U, // VADDSUBPDrr 0U, // VADDSUBPSYrm 0U, // VADDSUBPSYrr 0U, // VADDSUBPSrm 0U, // VADDSUBPSrr 0U, // VAESDECLASTYrm 0U, // VAESDECLASTYrr 0U, // VAESDECLASTZ128rm 0U, // VAESDECLASTZ128rr 0U, // VAESDECLASTZ256rm 0U, // VAESDECLASTZ256rr 0U, // VAESDECLASTZrm 0U, // VAESDECLASTZrr 0U, // VAESDECLASTrm 0U, // VAESDECLASTrr 0U, // VAESDECYrm 0U, // VAESDECYrr 0U, // VAESDECZ128rm 0U, // VAESDECZ128rr 0U, // VAESDECZ256rm 0U, // VAESDECZ256rr 0U, // VAESDECZrm 0U, // VAESDECZrr 0U, // VAESDECrm 0U, // VAESDECrr 0U, // VAESENCLASTYrm 0U, // VAESENCLASTYrr 0U, // VAESENCLASTZ128rm 0U, // VAESENCLASTZ128rr 0U, // VAESENCLASTZ256rm 0U, // VAESENCLASTZ256rr 0U, // VAESENCLASTZrm 0U, // VAESENCLASTZrr 0U, // VAESENCLASTrm 0U, // VAESENCLASTrr 0U, // VAESENCYrm 0U, // VAESENCYrr 0U, // VAESENCZ128rm 0U, // VAESENCZ128rr 0U, // VAESENCZ256rm 0U, // VAESENCZ256rr 0U, // VAESENCZrm 0U, // VAESENCZrr 0U, // VAESENCrm 0U, // VAESENCrr 0U, // VAESIMCrm 0U, // VAESIMCrr 0U, // VAESKEYGENASSIST128rm 0U, // VAESKEYGENASSIST128rr 0U, // VALIGNDZ128rmbi 0U, // VALIGNDZ128rmbik 3U, // VALIGNDZ128rmbikz 0U, // VALIGNDZ128rmi 0U, // VALIGNDZ128rmik 0U, // VALIGNDZ128rmikz 0U, // VALIGNDZ128rri 0U, // VALIGNDZ128rrik 3U, // VALIGNDZ128rrikz 0U, // VALIGNDZ256rmbi 0U, // VALIGNDZ256rmbik 3U, // VALIGNDZ256rmbikz 0U, // VALIGNDZ256rmi 0U, // VALIGNDZ256rmik 0U, // VALIGNDZ256rmikz 0U, // VALIGNDZ256rri 0U, // VALIGNDZ256rrik 3U, // VALIGNDZ256rrikz 0U, // VALIGNDZrmbi 0U, // VALIGNDZrmbik 3U, // VALIGNDZrmbikz 0U, // VALIGNDZrmi 0U, // VALIGNDZrmik 0U, // VALIGNDZrmikz 0U, // VALIGNDZrri 0U, // VALIGNDZrrik 3U, // VALIGNDZrrikz 0U, // VALIGNQZ128rmbi 0U, // VALIGNQZ128rmbik 3U, // VALIGNQZ128rmbikz 0U, // VALIGNQZ128rmi 0U, // VALIGNQZ128rmik 0U, // VALIGNQZ128rmikz 0U, // VALIGNQZ128rri 0U, // VALIGNQZ128rrik 3U, // VALIGNQZ128rrikz 0U, // VALIGNQZ256rmbi 0U, // VALIGNQZ256rmbik 3U, // VALIGNQZ256rmbikz 0U, // VALIGNQZ256rmi 0U, // VALIGNQZ256rmik 0U, // VALIGNQZ256rmikz 0U, // VALIGNQZ256rri 0U, // VALIGNQZ256rrik 3U, // VALIGNQZ256rrikz 0U, // VALIGNQZrmbi 0U, // VALIGNQZrmbik 3U, // VALIGNQZrmbikz 0U, // VALIGNQZrmi 0U, // VALIGNQZrmik 0U, // VALIGNQZrmikz 0U, // VALIGNQZrri 0U, // VALIGNQZrrik 3U, // VALIGNQZrrikz 0U, // VANDNPDYrm 0U, // VANDNPDYrr 0U, // VANDNPDZ128rm 0U, // VANDNPDZ128rmb 0U, // VANDNPDZ128rmbk 0U, // VANDNPDZ128rmbkz 0U, // VANDNPDZ128rmk 0U, // VANDNPDZ128rmkz 0U, // VANDNPDZ128rr 0U, // VANDNPDZ128rrk 0U, // VANDNPDZ128rrkz 0U, // VANDNPDZ256rm 0U, // VANDNPDZ256rmb 0U, // VANDNPDZ256rmbk 0U, // VANDNPDZ256rmbkz 0U, // VANDNPDZ256rmk 0U, // VANDNPDZ256rmkz 0U, // VANDNPDZ256rr 0U, // VANDNPDZ256rrk 0U, // VANDNPDZ256rrkz 0U, // VANDNPDZrm 0U, // VANDNPDZrmb 0U, // VANDNPDZrmbk 0U, // VANDNPDZrmbkz 0U, // VANDNPDZrmk 0U, // VANDNPDZrmkz 0U, // VANDNPDZrr 0U, // VANDNPDZrrk 0U, // VANDNPDZrrkz 0U, // VANDNPDrm 0U, // VANDNPDrr 0U, // VANDNPSYrm 0U, // VANDNPSYrr 0U, // VANDNPSZ128rm 0U, // VANDNPSZ128rmb 0U, // VANDNPSZ128rmbk 0U, // VANDNPSZ128rmbkz 0U, // VANDNPSZ128rmk 0U, // VANDNPSZ128rmkz 0U, // VANDNPSZ128rr 0U, // VANDNPSZ128rrk 0U, // VANDNPSZ128rrkz 0U, // VANDNPSZ256rm 0U, // VANDNPSZ256rmb 0U, // VANDNPSZ256rmbk 0U, // VANDNPSZ256rmbkz 0U, // VANDNPSZ256rmk 0U, // VANDNPSZ256rmkz 0U, // VANDNPSZ256rr 0U, // VANDNPSZ256rrk 0U, // VANDNPSZ256rrkz 0U, // VANDNPSZrm 0U, // VANDNPSZrmb 0U, // VANDNPSZrmbk 0U, // VANDNPSZrmbkz 0U, // VANDNPSZrmk 0U, // VANDNPSZrmkz 0U, // VANDNPSZrr 0U, // VANDNPSZrrk 0U, // VANDNPSZrrkz 0U, // VANDNPSrm 0U, // VANDNPSrr 0U, // VANDPDYrm 0U, // VANDPDYrr 0U, // VANDPDZ128rm 0U, // VANDPDZ128rmb 0U, // VANDPDZ128rmbk 0U, // VANDPDZ128rmbkz 0U, // VANDPDZ128rmk 0U, // VANDPDZ128rmkz 0U, // VANDPDZ128rr 0U, // VANDPDZ128rrk 0U, // VANDPDZ128rrkz 0U, // VANDPDZ256rm 0U, // VANDPDZ256rmb 0U, // VANDPDZ256rmbk 0U, // VANDPDZ256rmbkz 0U, // VANDPDZ256rmk 0U, // VANDPDZ256rmkz 0U, // VANDPDZ256rr 0U, // VANDPDZ256rrk 0U, // VANDPDZ256rrkz 0U, // VANDPDZrm 0U, // VANDPDZrmb 0U, // VANDPDZrmbk 0U, // VANDPDZrmbkz 0U, // VANDPDZrmk 0U, // VANDPDZrmkz 0U, // VANDPDZrr 0U, // VANDPDZrrk 0U, // VANDPDZrrkz 0U, // VANDPDrm 0U, // VANDPDrr 0U, // VANDPSYrm 0U, // VANDPSYrr 0U, // VANDPSZ128rm 0U, // VANDPSZ128rmb 0U, // VANDPSZ128rmbk 0U, // VANDPSZ128rmbkz 0U, // VANDPSZ128rmk 0U, // VANDPSZ128rmkz 0U, // VANDPSZ128rr 0U, // VANDPSZ128rrk 0U, // VANDPSZ128rrkz 0U, // VANDPSZ256rm 0U, // VANDPSZ256rmb 0U, // VANDPSZ256rmbk 0U, // VANDPSZ256rmbkz 0U, // VANDPSZ256rmk 0U, // VANDPSZ256rmkz 0U, // VANDPSZ256rr 0U, // VANDPSZ256rrk 0U, // VANDPSZ256rrkz 0U, // VANDPSZrm 0U, // VANDPSZrmb 0U, // VANDPSZrmbk 0U, // VANDPSZrmbkz 0U, // VANDPSZrmk 0U, // VANDPSZrmkz 0U, // VANDPSZrr 0U, // VANDPSZrrk 0U, // VANDPSZrrkz 0U, // VANDPSrm 0U, // VANDPSrr 0U, // VBLENDMPDZ128rm 0U, // VBLENDMPDZ128rmb 0U, // VBLENDMPDZ128rmbk 0U, // VBLENDMPDZ128rmbkz 0U, // VBLENDMPDZ128rmk 0U, // VBLENDMPDZ128rmkz 0U, // VBLENDMPDZ128rr 0U, // VBLENDMPDZ128rrk 0U, // VBLENDMPDZ128rrkz 0U, // VBLENDMPDZ256rm 0U, // VBLENDMPDZ256rmb 0U, // VBLENDMPDZ256rmbk 0U, // VBLENDMPDZ256rmbkz 0U, // VBLENDMPDZ256rmk 0U, // VBLENDMPDZ256rmkz 0U, // VBLENDMPDZ256rr 0U, // VBLENDMPDZ256rrk 0U, // VBLENDMPDZ256rrkz 0U, // VBLENDMPDZrm 0U, // VBLENDMPDZrmb 0U, // VBLENDMPDZrmbk 0U, // VBLENDMPDZrmbkz 0U, // VBLENDMPDZrmk 0U, // VBLENDMPDZrmkz 0U, // VBLENDMPDZrr 0U, // VBLENDMPDZrrk 0U, // VBLENDMPDZrrkz 0U, // VBLENDMPSZ128rm 0U, // VBLENDMPSZ128rmb 0U, // VBLENDMPSZ128rmbk 0U, // VBLENDMPSZ128rmbkz 0U, // VBLENDMPSZ128rmk 0U, // VBLENDMPSZ128rmkz 0U, // VBLENDMPSZ128rr 0U, // VBLENDMPSZ128rrk 0U, // VBLENDMPSZ128rrkz 0U, // VBLENDMPSZ256rm 0U, // VBLENDMPSZ256rmb 0U, // VBLENDMPSZ256rmbk 0U, // VBLENDMPSZ256rmbkz 0U, // VBLENDMPSZ256rmk 0U, // VBLENDMPSZ256rmkz 0U, // VBLENDMPSZ256rr 0U, // VBLENDMPSZ256rrk 0U, // VBLENDMPSZ256rrkz 0U, // VBLENDMPSZrm 0U, // VBLENDMPSZrmb 0U, // VBLENDMPSZrmbk 0U, // VBLENDMPSZrmbkz 0U, // VBLENDMPSZrmk 0U, // VBLENDMPSZrmkz 0U, // VBLENDMPSZrr 0U, // VBLENDMPSZrrk 0U, // VBLENDMPSZrrkz 0U, // VBLENDPDYrmi 0U, // VBLENDPDYrri 0U, // VBLENDPDrmi 0U, // VBLENDPDrri 0U, // VBLENDPSYrmi 0U, // VBLENDPSYrri 0U, // VBLENDPSrmi 0U, // VBLENDPSrri 0U, // VBLENDVPDYrm 0U, // VBLENDVPDYrr 0U, // VBLENDVPDrm 0U, // VBLENDVPDrr 0U, // VBLENDVPSYrm 0U, // VBLENDVPSYrr 0U, // VBLENDVPSrm 0U, // VBLENDVPSrr 0U, // VBROADCASTF128 0U, // VBROADCASTF32X2Z256m 0U, // VBROADCASTF32X2Z256mk 0U, // VBROADCASTF32X2Z256mkz 0U, // VBROADCASTF32X2Z256r 0U, // VBROADCASTF32X2Z256rk 0U, // VBROADCASTF32X2Z256rkz 0U, // VBROADCASTF32X2Zm 0U, // VBROADCASTF32X2Zmk 0U, // VBROADCASTF32X2Zmkz 0U, // VBROADCASTF32X2Zr 0U, // VBROADCASTF32X2Zrk 0U, // VBROADCASTF32X2Zrkz 0U, // VBROADCASTF32X4Z256rm 0U, // VBROADCASTF32X4Z256rmk 0U, // VBROADCASTF32X4Z256rmkz 0U, // VBROADCASTF32X4rm 0U, // VBROADCASTF32X4rmk 0U, // VBROADCASTF32X4rmkz 0U, // VBROADCASTF32X8rm 0U, // VBROADCASTF32X8rmk 0U, // VBROADCASTF32X8rmkz 0U, // VBROADCASTF64X2Z128rm 0U, // VBROADCASTF64X2Z128rmk 0U, // VBROADCASTF64X2Z128rmkz 0U, // VBROADCASTF64X2rm 0U, // VBROADCASTF64X2rmk 0U, // VBROADCASTF64X2rmkz 0U, // VBROADCASTF64X4rm 0U, // VBROADCASTF64X4rmk 0U, // VBROADCASTF64X4rmkz 0U, // VBROADCASTI128 0U, // VBROADCASTI32X2Z128m 0U, // VBROADCASTI32X2Z128mk 0U, // VBROADCASTI32X2Z128mkz 0U, // VBROADCASTI32X2Z128r 0U, // VBROADCASTI32X2Z128rk 0U, // VBROADCASTI32X2Z128rkz 0U, // VBROADCASTI32X2Z256m 0U, // VBROADCASTI32X2Z256mk 0U, // VBROADCASTI32X2Z256mkz 0U, // VBROADCASTI32X2Z256r 0U, // VBROADCASTI32X2Z256rk 0U, // VBROADCASTI32X2Z256rkz 0U, // VBROADCASTI32X2Zm 0U, // VBROADCASTI32X2Zmk 0U, // VBROADCASTI32X2Zmkz 0U, // VBROADCASTI32X2Zr 0U, // VBROADCASTI32X2Zrk 0U, // VBROADCASTI32X2Zrkz 0U, // VBROADCASTI32X4Z256rm 0U, // VBROADCASTI32X4Z256rmk 0U, // VBROADCASTI32X4Z256rmkz 0U, // VBROADCASTI32X4rm 0U, // VBROADCASTI32X4rmk 0U, // VBROADCASTI32X4rmkz 0U, // VBROADCASTI32X8rm 0U, // VBROADCASTI32X8rmk 0U, // VBROADCASTI32X8rmkz 0U, // VBROADCASTI64X2Z128rm 0U, // VBROADCASTI64X2Z128rmk 0U, // VBROADCASTI64X2Z128rmkz 0U, // VBROADCASTI64X2rm 0U, // VBROADCASTI64X2rmk 0U, // VBROADCASTI64X2rmkz 0U, // VBROADCASTI64X4rm 0U, // VBROADCASTI64X4rmk 0U, // VBROADCASTI64X4rmkz 0U, // VBROADCASTSDYrm 0U, // VBROADCASTSDYrr 0U, // VBROADCASTSDZ256m 0U, // VBROADCASTSDZ256mk 0U, // VBROADCASTSDZ256mkz 0U, // VBROADCASTSDZ256r 0U, // VBROADCASTSDZ256rk 0U, // VBROADCASTSDZ256rkz 0U, // VBROADCASTSDZm 0U, // VBROADCASTSDZmk 0U, // VBROADCASTSDZmkz 0U, // VBROADCASTSDZr 0U, // VBROADCASTSDZrk 0U, // VBROADCASTSDZrkz 0U, // VBROADCASTSSYrm 0U, // VBROADCASTSSYrr 0U, // VBROADCASTSSZ128m 0U, // VBROADCASTSSZ128mk 0U, // VBROADCASTSSZ128mkz 0U, // VBROADCASTSSZ128r 0U, // VBROADCASTSSZ128rk 0U, // VBROADCASTSSZ128rkz 0U, // VBROADCASTSSZ256m 0U, // VBROADCASTSSZ256mk 0U, // VBROADCASTSSZ256mkz 0U, // VBROADCASTSSZ256r 0U, // VBROADCASTSSZ256rk 0U, // VBROADCASTSSZ256rkz 0U, // VBROADCASTSSZm 0U, // VBROADCASTSSZmk 0U, // VBROADCASTSSZmkz 0U, // VBROADCASTSSZr 0U, // VBROADCASTSSZrk 0U, // VBROADCASTSSZrkz 0U, // VBROADCASTSSrm 0U, // VBROADCASTSSrr 0U, // VCMPPDYrmi 0U, // VCMPPDYrmi_alt 0U, // VCMPPDYrri 0U, // VCMPPDYrri_alt 0U, // VCMPPDZ128rmbi 0U, // VCMPPDZ128rmbi_alt 1U, // VCMPPDZ128rmbi_altk 1U, // VCMPPDZ128rmbik 0U, // VCMPPDZ128rmi 0U, // VCMPPDZ128rmi_alt 0U, // VCMPPDZ128rmi_altk 0U, // VCMPPDZ128rmik 0U, // VCMPPDZ128rri 0U, // VCMPPDZ128rri_alt 1U, // VCMPPDZ128rri_altk 1U, // VCMPPDZ128rrik 0U, // VCMPPDZ256rmbi 0U, // VCMPPDZ256rmbi_alt 1U, // VCMPPDZ256rmbi_altk 1U, // VCMPPDZ256rmbik 0U, // VCMPPDZ256rmi 0U, // VCMPPDZ256rmi_alt 0U, // VCMPPDZ256rmi_altk 0U, // VCMPPDZ256rmik 0U, // VCMPPDZ256rri 0U, // VCMPPDZ256rri_alt 1U, // VCMPPDZ256rri_altk 1U, // VCMPPDZ256rrik 0U, // VCMPPDZrmbi 0U, // VCMPPDZrmbi_alt 1U, // VCMPPDZrmbi_altk 1U, // VCMPPDZrmbik 0U, // VCMPPDZrmi 0U, // VCMPPDZrmi_alt 0U, // VCMPPDZrmi_altk 0U, // VCMPPDZrmik 0U, // VCMPPDZrri 0U, // VCMPPDZrri_alt 1U, // VCMPPDZrri_altk 0U, // VCMPPDZrrib 0U, // VCMPPDZrrib_alt 1U, // VCMPPDZrrib_altk 1U, // VCMPPDZrribk 1U, // VCMPPDZrrik 0U, // VCMPPDrmi 0U, // VCMPPDrmi_alt 0U, // VCMPPDrri 0U, // VCMPPDrri_alt 0U, // VCMPPSYrmi 0U, // VCMPPSYrmi_alt 0U, // VCMPPSYrri 0U, // VCMPPSYrri_alt 0U, // VCMPPSZ128rmbi 0U, // VCMPPSZ128rmbi_alt 1U, // VCMPPSZ128rmbi_altk 1U, // VCMPPSZ128rmbik 0U, // VCMPPSZ128rmi 0U, // VCMPPSZ128rmi_alt 0U, // VCMPPSZ128rmi_altk 0U, // VCMPPSZ128rmik 0U, // VCMPPSZ128rri 0U, // VCMPPSZ128rri_alt 1U, // VCMPPSZ128rri_altk 1U, // VCMPPSZ128rrik 0U, // VCMPPSZ256rmbi 0U, // VCMPPSZ256rmbi_alt 1U, // VCMPPSZ256rmbi_altk 1U, // VCMPPSZ256rmbik 0U, // VCMPPSZ256rmi 0U, // VCMPPSZ256rmi_alt 0U, // VCMPPSZ256rmi_altk 0U, // VCMPPSZ256rmik 0U, // VCMPPSZ256rri 0U, // VCMPPSZ256rri_alt 1U, // VCMPPSZ256rri_altk 1U, // VCMPPSZ256rrik 0U, // VCMPPSZrmbi 0U, // VCMPPSZrmbi_alt 1U, // VCMPPSZrmbi_altk 1U, // VCMPPSZrmbik 0U, // VCMPPSZrmi 0U, // VCMPPSZrmi_alt 0U, // VCMPPSZrmi_altk 0U, // VCMPPSZrmik 0U, // VCMPPSZrri 0U, // VCMPPSZrri_alt 1U, // VCMPPSZrri_altk 0U, // VCMPPSZrrib 0U, // VCMPPSZrrib_alt 1U, // VCMPPSZrrib_altk 1U, // VCMPPSZrribk 1U, // VCMPPSZrrik 0U, // VCMPPSrmi 0U, // VCMPPSrmi_alt 0U, // VCMPPSrri 0U, // VCMPPSrri_alt 0U, // VCMPSDZrm 0U, // VCMPSDZrm_Int 1U, // VCMPSDZrm_Intk 0U, // VCMPSDZrmi_alt 1U, // VCMPSDZrmi_altk 0U, // VCMPSDZrr 0U, // VCMPSDZrr_Int 1U, // VCMPSDZrr_Intk 0U, // VCMPSDZrrb_Int 1U, // VCMPSDZrrb_Intk 0U, // VCMPSDZrrb_alt 1U, // VCMPSDZrrb_altk 0U, // VCMPSDZrri_alt 1U, // VCMPSDZrri_altk 0U, // VCMPSDrm 0U, // VCMPSDrm_Int 0U, // VCMPSDrm_alt 0U, // VCMPSDrr 0U, // VCMPSDrr_Int 0U, // VCMPSDrr_alt 0U, // VCMPSSZrm 0U, // VCMPSSZrm_Int 1U, // VCMPSSZrm_Intk 0U, // VCMPSSZrmi_alt 1U, // VCMPSSZrmi_altk 0U, // VCMPSSZrr 0U, // VCMPSSZrr_Int 1U, // VCMPSSZrr_Intk 0U, // VCMPSSZrrb_Int 1U, // VCMPSSZrrb_Intk 0U, // VCMPSSZrrb_alt 1U, // VCMPSSZrrb_altk 0U, // VCMPSSZrri_alt 1U, // VCMPSSZrri_altk 0U, // VCMPSSrm 0U, // VCMPSSrm_Int 0U, // VCMPSSrm_alt 0U, // VCMPSSrr 0U, // VCMPSSrr_Int 0U, // VCMPSSrr_alt 0U, // VCOMISDZrm 0U, // VCOMISDZrm_Int 0U, // VCOMISDZrr 0U, // VCOMISDZrr_Int 0U, // VCOMISDZrrb 0U, // VCOMISDrm 0U, // VCOMISDrm_Int 0U, // VCOMISDrr 0U, // VCOMISDrr_Int 0U, // VCOMISSZrm 0U, // VCOMISSZrm_Int 0U, // VCOMISSZrr 0U, // VCOMISSZrr_Int 0U, // VCOMISSZrrb 0U, // VCOMISSrm 0U, // VCOMISSrm_Int 0U, // VCOMISSrr 0U, // VCOMISSrr_Int 0U, // VCOMPRESSPDZ128mr 0U, // VCOMPRESSPDZ128mrk 0U, // VCOMPRESSPDZ128rr 0U, // VCOMPRESSPDZ128rrk 0U, // VCOMPRESSPDZ128rrkz 0U, // VCOMPRESSPDZ256mr 0U, // VCOMPRESSPDZ256mrk 0U, // VCOMPRESSPDZ256rr 0U, // VCOMPRESSPDZ256rrk 0U, // VCOMPRESSPDZ256rrkz 0U, // VCOMPRESSPDZmr 0U, // VCOMPRESSPDZmrk 0U, // VCOMPRESSPDZrr 0U, // VCOMPRESSPDZrrk 0U, // VCOMPRESSPDZrrkz 0U, // VCOMPRESSPSZ128mr 0U, // VCOMPRESSPSZ128mrk 0U, // VCOMPRESSPSZ128rr 0U, // VCOMPRESSPSZ128rrk 0U, // VCOMPRESSPSZ128rrkz 0U, // VCOMPRESSPSZ256mr 0U, // VCOMPRESSPSZ256mrk 0U, // VCOMPRESSPSZ256rr 0U, // VCOMPRESSPSZ256rrk 0U, // VCOMPRESSPSZ256rrkz 0U, // VCOMPRESSPSZmr 0U, // VCOMPRESSPSZmrk 0U, // VCOMPRESSPSZrr 0U, // VCOMPRESSPSZrrk 0U, // VCOMPRESSPSZrrkz 0U, // VCVTDQ2PDYrm 0U, // VCVTDQ2PDYrr 0U, // VCVTDQ2PDZ128rm 0U, // VCVTDQ2PDZ128rmb 0U, // VCVTDQ2PDZ128rmbk 0U, // VCVTDQ2PDZ128rmbkz 0U, // VCVTDQ2PDZ128rmk 0U, // VCVTDQ2PDZ128rmkz 0U, // VCVTDQ2PDZ128rr 0U, // VCVTDQ2PDZ128rrk 0U, // VCVTDQ2PDZ128rrkz 0U, // VCVTDQ2PDZ256rm 0U, // VCVTDQ2PDZ256rmb 0U, // VCVTDQ2PDZ256rmbk 0U, // VCVTDQ2PDZ256rmbkz 0U, // VCVTDQ2PDZ256rmk 0U, // VCVTDQ2PDZ256rmkz 0U, // VCVTDQ2PDZ256rr 0U, // VCVTDQ2PDZ256rrk 0U, // VCVTDQ2PDZ256rrkz 0U, // VCVTDQ2PDZrm 0U, // VCVTDQ2PDZrmb 0U, // VCVTDQ2PDZrmbk 0U, // VCVTDQ2PDZrmbkz 0U, // VCVTDQ2PDZrmk 0U, // VCVTDQ2PDZrmkz 0U, // VCVTDQ2PDZrr 0U, // VCVTDQ2PDZrrk 0U, // VCVTDQ2PDZrrkz 0U, // VCVTDQ2PDrm 0U, // VCVTDQ2PDrr 0U, // VCVTDQ2PSYrm 0U, // VCVTDQ2PSYrr 0U, // VCVTDQ2PSZ128rm 0U, // VCVTDQ2PSZ128rmb 0U, // VCVTDQ2PSZ128rmbk 0U, // VCVTDQ2PSZ128rmbkz 0U, // VCVTDQ2PSZ128rmk 0U, // VCVTDQ2PSZ128rmkz 0U, // VCVTDQ2PSZ128rr 0U, // VCVTDQ2PSZ128rrk 0U, // VCVTDQ2PSZ128rrkz 0U, // VCVTDQ2PSZ256rm 0U, // VCVTDQ2PSZ256rmb 0U, // VCVTDQ2PSZ256rmbk 0U, // VCVTDQ2PSZ256rmbkz 0U, // VCVTDQ2PSZ256rmk 0U, // VCVTDQ2PSZ256rmkz 0U, // VCVTDQ2PSZ256rr 0U, // VCVTDQ2PSZ256rrk 0U, // VCVTDQ2PSZ256rrkz 0U, // VCVTDQ2PSZrm 0U, // VCVTDQ2PSZrmb 0U, // VCVTDQ2PSZrmbk 0U, // VCVTDQ2PSZrmbkz 0U, // VCVTDQ2PSZrmk 0U, // VCVTDQ2PSZrmkz 0U, // VCVTDQ2PSZrr 0U, // VCVTDQ2PSZrrb 0U, // VCVTDQ2PSZrrbk 0U, // VCVTDQ2PSZrrbkz 0U, // VCVTDQ2PSZrrk 0U, // VCVTDQ2PSZrrkz 0U, // VCVTDQ2PSrm 0U, // VCVTDQ2PSrr 0U, // VCVTPD2DQYrm 0U, // VCVTPD2DQYrr 0U, // VCVTPD2DQZ128rm 0U, // VCVTPD2DQZ128rmb 0U, // VCVTPD2DQZ128rmbk 0U, // VCVTPD2DQZ128rmbkz 0U, // VCVTPD2DQZ128rmk 0U, // VCVTPD2DQZ128rmkz 0U, // VCVTPD2DQZ128rr 0U, // VCVTPD2DQZ128rrk 0U, // VCVTPD2DQZ128rrkz 0U, // VCVTPD2DQZ256rm 0U, // VCVTPD2DQZ256rmb 0U, // VCVTPD2DQZ256rmbk 0U, // VCVTPD2DQZ256rmbkz 0U, // VCVTPD2DQZ256rmk 0U, // VCVTPD2DQZ256rmkz 0U, // VCVTPD2DQZ256rr 0U, // VCVTPD2DQZ256rrk 0U, // VCVTPD2DQZ256rrkz 0U, // VCVTPD2DQZrm 0U, // VCVTPD2DQZrmb 0U, // VCVTPD2DQZrmbk 0U, // VCVTPD2DQZrmbkz 0U, // VCVTPD2DQZrmk 0U, // VCVTPD2DQZrmkz 0U, // VCVTPD2DQZrr 0U, // VCVTPD2DQZrrb 0U, // VCVTPD2DQZrrbk 0U, // VCVTPD2DQZrrbkz 0U, // VCVTPD2DQZrrk 0U, // VCVTPD2DQZrrkz 0U, // VCVTPD2DQrm 0U, // VCVTPD2DQrr 0U, // VCVTPD2PSYrm 0U, // VCVTPD2PSYrr 0U, // VCVTPD2PSZ128rm 0U, // VCVTPD2PSZ128rmb 0U, // VCVTPD2PSZ128rmbk 0U, // VCVTPD2PSZ128rmbkz 0U, // VCVTPD2PSZ128rmk 0U, // VCVTPD2PSZ128rmkz 0U, // VCVTPD2PSZ128rr 0U, // VCVTPD2PSZ128rrk 0U, // VCVTPD2PSZ128rrkz 0U, // VCVTPD2PSZ256rm 0U, // VCVTPD2PSZ256rmb 0U, // VCVTPD2PSZ256rmbk 0U, // VCVTPD2PSZ256rmbkz 0U, // VCVTPD2PSZ256rmk 0U, // VCVTPD2PSZ256rmkz 0U, // VCVTPD2PSZ256rr 0U, // VCVTPD2PSZ256rrk 0U, // VCVTPD2PSZ256rrkz 0U, // VCVTPD2PSZrm 0U, // VCVTPD2PSZrmb 0U, // VCVTPD2PSZrmbk 0U, // VCVTPD2PSZrmbkz 0U, // VCVTPD2PSZrmk 0U, // VCVTPD2PSZrmkz 0U, // VCVTPD2PSZrr 0U, // VCVTPD2PSZrrb 0U, // VCVTPD2PSZrrbk 0U, // VCVTPD2PSZrrbkz 0U, // VCVTPD2PSZrrk 0U, // VCVTPD2PSZrrkz 0U, // VCVTPD2PSrm 0U, // VCVTPD2PSrr 0U, // VCVTPD2QQZ128rm 0U, // VCVTPD2QQZ128rmb 0U, // VCVTPD2QQZ128rmbk 0U, // VCVTPD2QQZ128rmbkz 0U, // VCVTPD2QQZ128rmk 0U, // VCVTPD2QQZ128rmkz 0U, // VCVTPD2QQZ128rr 0U, // VCVTPD2QQZ128rrk 0U, // VCVTPD2QQZ128rrkz 0U, // VCVTPD2QQZ256rm 0U, // VCVTPD2QQZ256rmb 0U, // VCVTPD2QQZ256rmbk 0U, // VCVTPD2QQZ256rmbkz 0U, // VCVTPD2QQZ256rmk 0U, // VCVTPD2QQZ256rmkz 0U, // VCVTPD2QQZ256rr 0U, // VCVTPD2QQZ256rrk 0U, // VCVTPD2QQZ256rrkz 0U, // VCVTPD2QQZrm 0U, // VCVTPD2QQZrmb 0U, // VCVTPD2QQZrmbk 0U, // VCVTPD2QQZrmbkz 0U, // VCVTPD2QQZrmk 0U, // VCVTPD2QQZrmkz 0U, // VCVTPD2QQZrr 0U, // VCVTPD2QQZrrb 0U, // VCVTPD2QQZrrbk 0U, // VCVTPD2QQZrrbkz 0U, // VCVTPD2QQZrrk 0U, // VCVTPD2QQZrrkz 0U, // VCVTPD2UDQZ128rm 0U, // VCVTPD2UDQZ128rmb 0U, // VCVTPD2UDQZ128rmbk 0U, // VCVTPD2UDQZ128rmbkz 0U, // VCVTPD2UDQZ128rmk 0U, // VCVTPD2UDQZ128rmkz 0U, // VCVTPD2UDQZ128rr 0U, // VCVTPD2UDQZ128rrk 0U, // VCVTPD2UDQZ128rrkz 0U, // VCVTPD2UDQZ256rm 0U, // VCVTPD2UDQZ256rmb 0U, // VCVTPD2UDQZ256rmbk 0U, // VCVTPD2UDQZ256rmbkz 0U, // VCVTPD2UDQZ256rmk 0U, // VCVTPD2UDQZ256rmkz 0U, // VCVTPD2UDQZ256rr 0U, // VCVTPD2UDQZ256rrk 0U, // VCVTPD2UDQZ256rrkz 0U, // VCVTPD2UDQZrm 0U, // VCVTPD2UDQZrmb 0U, // VCVTPD2UDQZrmbk 0U, // VCVTPD2UDQZrmbkz 0U, // VCVTPD2UDQZrmk 0U, // VCVTPD2UDQZrmkz 0U, // VCVTPD2UDQZrr 0U, // VCVTPD2UDQZrrb 0U, // VCVTPD2UDQZrrbk 0U, // VCVTPD2UDQZrrbkz 0U, // VCVTPD2UDQZrrk 0U, // VCVTPD2UDQZrrkz 0U, // VCVTPD2UQQZ128rm 0U, // VCVTPD2UQQZ128rmb 0U, // VCVTPD2UQQZ128rmbk 0U, // VCVTPD2UQQZ128rmbkz 0U, // VCVTPD2UQQZ128rmk 0U, // VCVTPD2UQQZ128rmkz 0U, // VCVTPD2UQQZ128rr 0U, // VCVTPD2UQQZ128rrk 0U, // VCVTPD2UQQZ128rrkz 0U, // VCVTPD2UQQZ256rm 0U, // VCVTPD2UQQZ256rmb 0U, // VCVTPD2UQQZ256rmbk 0U, // VCVTPD2UQQZ256rmbkz 0U, // VCVTPD2UQQZ256rmk 0U, // VCVTPD2UQQZ256rmkz 0U, // VCVTPD2UQQZ256rr 0U, // VCVTPD2UQQZ256rrk 0U, // VCVTPD2UQQZ256rrkz 0U, // VCVTPD2UQQZrm 0U, // VCVTPD2UQQZrmb 0U, // VCVTPD2UQQZrmbk 0U, // VCVTPD2UQQZrmbkz 0U, // VCVTPD2UQQZrmk 0U, // VCVTPD2UQQZrmkz 0U, // VCVTPD2UQQZrr 0U, // VCVTPD2UQQZrrb 0U, // VCVTPD2UQQZrrbk 0U, // VCVTPD2UQQZrrbkz 0U, // VCVTPD2UQQZrrk 0U, // VCVTPD2UQQZrrkz 0U, // VCVTPH2PSYrm 0U, // VCVTPH2PSYrr 0U, // VCVTPH2PSZ128rm 0U, // VCVTPH2PSZ128rmk 0U, // VCVTPH2PSZ128rmkz 0U, // VCVTPH2PSZ128rr 0U, // VCVTPH2PSZ128rrk 0U, // VCVTPH2PSZ128rrkz 0U, // VCVTPH2PSZ256rm 0U, // VCVTPH2PSZ256rmk 0U, // VCVTPH2PSZ256rmkz 0U, // VCVTPH2PSZ256rr 0U, // VCVTPH2PSZ256rrk 0U, // VCVTPH2PSZ256rrkz 0U, // VCVTPH2PSZrm 0U, // VCVTPH2PSZrmk 0U, // VCVTPH2PSZrmkz 0U, // VCVTPH2PSZrr 0U, // VCVTPH2PSZrrb 0U, // VCVTPH2PSZrrbk 0U, // VCVTPH2PSZrrbkz 0U, // VCVTPH2PSZrrk 0U, // VCVTPH2PSZrrkz 0U, // VCVTPH2PSrm 0U, // VCVTPH2PSrr 0U, // VCVTPS2DQYrm 0U, // VCVTPS2DQYrr 0U, // VCVTPS2DQZ128rm 0U, // VCVTPS2DQZ128rmb 0U, // VCVTPS2DQZ128rmbk 0U, // VCVTPS2DQZ128rmbkz 0U, // VCVTPS2DQZ128rmk 0U, // VCVTPS2DQZ128rmkz 0U, // VCVTPS2DQZ128rr 0U, // VCVTPS2DQZ128rrk 0U, // VCVTPS2DQZ128rrkz 0U, // VCVTPS2DQZ256rm 0U, // VCVTPS2DQZ256rmb 0U, // VCVTPS2DQZ256rmbk 0U, // VCVTPS2DQZ256rmbkz 0U, // VCVTPS2DQZ256rmk 0U, // VCVTPS2DQZ256rmkz 0U, // VCVTPS2DQZ256rr 0U, // VCVTPS2DQZ256rrk 0U, // VCVTPS2DQZ256rrkz 0U, // VCVTPS2DQZrm 0U, // VCVTPS2DQZrmb 0U, // VCVTPS2DQZrmbk 0U, // VCVTPS2DQZrmbkz 0U, // VCVTPS2DQZrmk 0U, // VCVTPS2DQZrmkz 0U, // VCVTPS2DQZrr 0U, // VCVTPS2DQZrrb 0U, // VCVTPS2DQZrrbk 0U, // VCVTPS2DQZrrbkz 0U, // VCVTPS2DQZrrk 0U, // VCVTPS2DQZrrkz 0U, // VCVTPS2DQrm 0U, // VCVTPS2DQrr 0U, // VCVTPS2PDYrm 0U, // VCVTPS2PDYrr 0U, // VCVTPS2PDZ128rm 0U, // VCVTPS2PDZ128rmb 0U, // VCVTPS2PDZ128rmbk 0U, // VCVTPS2PDZ128rmbkz 0U, // VCVTPS2PDZ128rmk 0U, // VCVTPS2PDZ128rmkz 0U, // VCVTPS2PDZ128rr 0U, // VCVTPS2PDZ128rrk 0U, // VCVTPS2PDZ128rrkz 0U, // VCVTPS2PDZ256rm 0U, // VCVTPS2PDZ256rmb 0U, // VCVTPS2PDZ256rmbk 0U, // VCVTPS2PDZ256rmbkz 0U, // VCVTPS2PDZ256rmk 0U, // VCVTPS2PDZ256rmkz 0U, // VCVTPS2PDZ256rr 0U, // VCVTPS2PDZ256rrk 0U, // VCVTPS2PDZ256rrkz 0U, // VCVTPS2PDZrm 0U, // VCVTPS2PDZrmb 0U, // VCVTPS2PDZrmbk 0U, // VCVTPS2PDZrmbkz 0U, // VCVTPS2PDZrmk 0U, // VCVTPS2PDZrmkz 0U, // VCVTPS2PDZrr 0U, // VCVTPS2PDZrrb 0U, // VCVTPS2PDZrrbk 0U, // VCVTPS2PDZrrbkz 0U, // VCVTPS2PDZrrk 0U, // VCVTPS2PDZrrkz 0U, // VCVTPS2PDrm 0U, // VCVTPS2PDrr 0U, // VCVTPS2PHYmr 0U, // VCVTPS2PHYrr 0U, // VCVTPS2PHZ128mr 0U, // VCVTPS2PHZ128mrk 0U, // VCVTPS2PHZ128rr 0U, // VCVTPS2PHZ128rrk 0U, // VCVTPS2PHZ128rrkz 0U, // VCVTPS2PHZ256mr 0U, // VCVTPS2PHZ256mrk 0U, // VCVTPS2PHZ256rr 0U, // VCVTPS2PHZ256rrk 0U, // VCVTPS2PHZ256rrkz 0U, // VCVTPS2PHZmr 0U, // VCVTPS2PHZmrk 0U, // VCVTPS2PHZrr 0U, // VCVTPS2PHZrrb 0U, // VCVTPS2PHZrrbk 0U, // VCVTPS2PHZrrbkz 0U, // VCVTPS2PHZrrk 0U, // VCVTPS2PHZrrkz 0U, // VCVTPS2PHmr 0U, // VCVTPS2PHrr 0U, // VCVTPS2QQZ128rm 0U, // VCVTPS2QQZ128rmb 0U, // VCVTPS2QQZ128rmbk 0U, // VCVTPS2QQZ128rmbkz 0U, // VCVTPS2QQZ128rmk 0U, // VCVTPS2QQZ128rmkz 0U, // VCVTPS2QQZ128rr 0U, // VCVTPS2QQZ128rrk 0U, // VCVTPS2QQZ128rrkz 0U, // VCVTPS2QQZ256rm 0U, // VCVTPS2QQZ256rmb 0U, // VCVTPS2QQZ256rmbk 0U, // VCVTPS2QQZ256rmbkz 0U, // VCVTPS2QQZ256rmk 0U, // VCVTPS2QQZ256rmkz 0U, // VCVTPS2QQZ256rr 0U, // VCVTPS2QQZ256rrk 0U, // VCVTPS2QQZ256rrkz 0U, // VCVTPS2QQZrm 0U, // VCVTPS2QQZrmb 0U, // VCVTPS2QQZrmbk 0U, // VCVTPS2QQZrmbkz 0U, // VCVTPS2QQZrmk 0U, // VCVTPS2QQZrmkz 0U, // VCVTPS2QQZrr 0U, // VCVTPS2QQZrrb 0U, // VCVTPS2QQZrrbk 0U, // VCVTPS2QQZrrbkz 0U, // VCVTPS2QQZrrk 0U, // VCVTPS2QQZrrkz 0U, // VCVTPS2UDQZ128rm 0U, // VCVTPS2UDQZ128rmb 0U, // VCVTPS2UDQZ128rmbk 0U, // VCVTPS2UDQZ128rmbkz 0U, // VCVTPS2UDQZ128rmk 0U, // VCVTPS2UDQZ128rmkz 0U, // VCVTPS2UDQZ128rr 0U, // VCVTPS2UDQZ128rrk 0U, // VCVTPS2UDQZ128rrkz 0U, // VCVTPS2UDQZ256rm 0U, // VCVTPS2UDQZ256rmb 0U, // VCVTPS2UDQZ256rmbk 0U, // VCVTPS2UDQZ256rmbkz 0U, // VCVTPS2UDQZ256rmk 0U, // VCVTPS2UDQZ256rmkz 0U, // VCVTPS2UDQZ256rr 0U, // VCVTPS2UDQZ256rrk 0U, // VCVTPS2UDQZ256rrkz 0U, // VCVTPS2UDQZrm 0U, // VCVTPS2UDQZrmb 0U, // VCVTPS2UDQZrmbk 0U, // VCVTPS2UDQZrmbkz 0U, // VCVTPS2UDQZrmk 0U, // VCVTPS2UDQZrmkz 0U, // VCVTPS2UDQZrr 0U, // VCVTPS2UDQZrrb 0U, // VCVTPS2UDQZrrbk 0U, // VCVTPS2UDQZrrbkz 0U, // VCVTPS2UDQZrrk 0U, // VCVTPS2UDQZrrkz 0U, // VCVTPS2UQQZ128rm 0U, // VCVTPS2UQQZ128rmb 0U, // VCVTPS2UQQZ128rmbk 0U, // VCVTPS2UQQZ128rmbkz 0U, // VCVTPS2UQQZ128rmk 0U, // VCVTPS2UQQZ128rmkz 0U, // VCVTPS2UQQZ128rr 0U, // VCVTPS2UQQZ128rrk 0U, // VCVTPS2UQQZ128rrkz 0U, // VCVTPS2UQQZ256rm 0U, // VCVTPS2UQQZ256rmb 0U, // VCVTPS2UQQZ256rmbk 0U, // VCVTPS2UQQZ256rmbkz 0U, // VCVTPS2UQQZ256rmk 0U, // VCVTPS2UQQZ256rmkz 0U, // VCVTPS2UQQZ256rr 0U, // VCVTPS2UQQZ256rrk 0U, // VCVTPS2UQQZ256rrkz 0U, // VCVTPS2UQQZrm 0U, // VCVTPS2UQQZrmb 0U, // VCVTPS2UQQZrmbk 0U, // VCVTPS2UQQZrmbkz 0U, // VCVTPS2UQQZrmk 0U, // VCVTPS2UQQZrmkz 0U, // VCVTPS2UQQZrr 0U, // VCVTPS2UQQZrrb 0U, // VCVTPS2UQQZrrbk 0U, // VCVTPS2UQQZrrbkz 0U, // VCVTPS2UQQZrrk 0U, // VCVTPS2UQQZrrkz 0U, // VCVTQQ2PDZ128rm 0U, // VCVTQQ2PDZ128rmb 0U, // VCVTQQ2PDZ128rmbk 0U, // VCVTQQ2PDZ128rmbkz 0U, // VCVTQQ2PDZ128rmk 0U, // VCVTQQ2PDZ128rmkz 0U, // VCVTQQ2PDZ128rr 0U, // VCVTQQ2PDZ128rrk 0U, // VCVTQQ2PDZ128rrkz 0U, // VCVTQQ2PDZ256rm 0U, // VCVTQQ2PDZ256rmb 0U, // VCVTQQ2PDZ256rmbk 0U, // VCVTQQ2PDZ256rmbkz 0U, // VCVTQQ2PDZ256rmk 0U, // VCVTQQ2PDZ256rmkz 0U, // VCVTQQ2PDZ256rr 0U, // VCVTQQ2PDZ256rrk 0U, // VCVTQQ2PDZ256rrkz 0U, // VCVTQQ2PDZrm 0U, // VCVTQQ2PDZrmb 0U, // VCVTQQ2PDZrmbk 0U, // VCVTQQ2PDZrmbkz 0U, // VCVTQQ2PDZrmk 0U, // VCVTQQ2PDZrmkz 0U, // VCVTQQ2PDZrr 0U, // VCVTQQ2PDZrrb 0U, // VCVTQQ2PDZrrbk 0U, // VCVTQQ2PDZrrbkz 0U, // VCVTQQ2PDZrrk 0U, // VCVTQQ2PDZrrkz 0U, // VCVTQQ2PSZ128rm 0U, // VCVTQQ2PSZ128rmb 0U, // VCVTQQ2PSZ128rmbk 0U, // VCVTQQ2PSZ128rmbkz 0U, // VCVTQQ2PSZ128rmk 0U, // VCVTQQ2PSZ128rmkz 0U, // VCVTQQ2PSZ128rr 0U, // VCVTQQ2PSZ128rrk 0U, // VCVTQQ2PSZ128rrkz 0U, // VCVTQQ2PSZ256rm 0U, // VCVTQQ2PSZ256rmb 0U, // VCVTQQ2PSZ256rmbk 0U, // VCVTQQ2PSZ256rmbkz 0U, // VCVTQQ2PSZ256rmk 0U, // VCVTQQ2PSZ256rmkz 0U, // VCVTQQ2PSZ256rr 0U, // VCVTQQ2PSZ256rrk 0U, // VCVTQQ2PSZ256rrkz 0U, // VCVTQQ2PSZrm 0U, // VCVTQQ2PSZrmb 0U, // VCVTQQ2PSZrmbk 0U, // VCVTQQ2PSZrmbkz 0U, // VCVTQQ2PSZrmk 0U, // VCVTQQ2PSZrmkz 0U, // VCVTQQ2PSZrr 0U, // VCVTQQ2PSZrrb 0U, // VCVTQQ2PSZrrbk 0U, // VCVTQQ2PSZrrbkz 0U, // VCVTQQ2PSZrrk 0U, // VCVTQQ2PSZrrkz 0U, // VCVTSD2SI64Zrm_Int 0U, // VCVTSD2SI64Zrr_Int 0U, // VCVTSD2SI64Zrrb_Int 0U, // VCVTSD2SI64rm_Int 0U, // VCVTSD2SI64rr_Int 0U, // VCVTSD2SIZrm_Int 0U, // VCVTSD2SIZrr_Int 0U, // VCVTSD2SIZrrb_Int 0U, // VCVTSD2SIrm_Int 0U, // VCVTSD2SIrr_Int 0U, // VCVTSD2SSZrm 0U, // VCVTSD2SSZrm_Int 0U, // VCVTSD2SSZrm_Intk 0U, // VCVTSD2SSZrm_Intkz 0U, // VCVTSD2SSZrr 0U, // VCVTSD2SSZrr_Int 0U, // VCVTSD2SSZrr_Intk 0U, // VCVTSD2SSZrr_Intkz 0U, // VCVTSD2SSZrrb_Int 0U, // VCVTSD2SSZrrb_Intk 0U, // VCVTSD2SSZrrb_Intkz 0U, // VCVTSD2SSrm 0U, // VCVTSD2SSrm_Int 0U, // VCVTSD2SSrr 0U, // VCVTSD2SSrr_Int 0U, // VCVTSD2USI64Zrm_Int 0U, // VCVTSD2USI64Zrr_Int 0U, // VCVTSD2USI64Zrrb_Int 0U, // VCVTSD2USIZrm_Int 0U, // VCVTSD2USIZrr_Int 0U, // VCVTSD2USIZrrb_Int 0U, // VCVTSI2SDZrm 0U, // VCVTSI2SDZrm_Int 0U, // VCVTSI2SDZrr 0U, // VCVTSI2SDZrr_Int 0U, // VCVTSI2SDZrrb_Int 0U, // VCVTSI2SDrm 0U, // VCVTSI2SDrm_Int 0U, // VCVTSI2SDrr 0U, // VCVTSI2SDrr_Int 0U, // VCVTSI2SSZrm 0U, // VCVTSI2SSZrm_Int 0U, // VCVTSI2SSZrr 0U, // VCVTSI2SSZrr_Int 0U, // VCVTSI2SSZrrb_Int 0U, // VCVTSI2SSrm 0U, // VCVTSI2SSrm_Int 0U, // VCVTSI2SSrr 0U, // VCVTSI2SSrr_Int 0U, // VCVTSI642SDZrm 0U, // VCVTSI642SDZrm_Int 0U, // VCVTSI642SDZrr 0U, // VCVTSI642SDZrr_Int 0U, // VCVTSI642SDZrrb_Int 0U, // VCVTSI642SDrm 0U, // VCVTSI642SDrm_Int 0U, // VCVTSI642SDrr 0U, // VCVTSI642SDrr_Int 0U, // VCVTSI642SSZrm 0U, // VCVTSI642SSZrm_Int 0U, // VCVTSI642SSZrr 0U, // VCVTSI642SSZrr_Int 0U, // VCVTSI642SSZrrb_Int 0U, // VCVTSI642SSrm 0U, // VCVTSI642SSrm_Int 0U, // VCVTSI642SSrr 0U, // VCVTSI642SSrr_Int 0U, // VCVTSS2SDZrm 0U, // VCVTSS2SDZrm_Int 0U, // VCVTSS2SDZrm_Intk 0U, // VCVTSS2SDZrm_Intkz 0U, // VCVTSS2SDZrr 0U, // VCVTSS2SDZrr_Int 0U, // VCVTSS2SDZrr_Intk 0U, // VCVTSS2SDZrr_Intkz 0U, // VCVTSS2SDZrrb_Int 0U, // VCVTSS2SDZrrb_Intk 0U, // VCVTSS2SDZrrb_Intkz 0U, // VCVTSS2SDrm 0U, // VCVTSS2SDrm_Int 0U, // VCVTSS2SDrr 0U, // VCVTSS2SDrr_Int 0U, // VCVTSS2SI64Zrm_Int 0U, // VCVTSS2SI64Zrr_Int 0U, // VCVTSS2SI64Zrrb_Int 0U, // VCVTSS2SI64rm_Int 0U, // VCVTSS2SI64rr_Int 0U, // VCVTSS2SIZrm_Int 0U, // VCVTSS2SIZrr_Int 0U, // VCVTSS2SIZrrb_Int 0U, // VCVTSS2SIrm_Int 0U, // VCVTSS2SIrr_Int 0U, // VCVTSS2USI64Zrm_Int 0U, // VCVTSS2USI64Zrr_Int 0U, // VCVTSS2USI64Zrrb_Int 0U, // VCVTSS2USIZrm_Int 0U, // VCVTSS2USIZrr_Int 0U, // VCVTSS2USIZrrb_Int 0U, // VCVTTPD2DQYrm 0U, // VCVTTPD2DQYrr 0U, // VCVTTPD2DQZ128rm 0U, // VCVTTPD2DQZ128rmb 0U, // VCVTTPD2DQZ128rmbk 0U, // VCVTTPD2DQZ128rmbkz 0U, // VCVTTPD2DQZ128rmk 0U, // VCVTTPD2DQZ128rmkz 0U, // VCVTTPD2DQZ128rr 0U, // VCVTTPD2DQZ128rrk 0U, // VCVTTPD2DQZ128rrkz 0U, // VCVTTPD2DQZ256rm 0U, // VCVTTPD2DQZ256rmb 0U, // VCVTTPD2DQZ256rmbk 0U, // VCVTTPD2DQZ256rmbkz 0U, // VCVTTPD2DQZ256rmk 0U, // VCVTTPD2DQZ256rmkz 0U, // VCVTTPD2DQZ256rr 0U, // VCVTTPD2DQZ256rrk 0U, // VCVTTPD2DQZ256rrkz 0U, // VCVTTPD2DQZrm 0U, // VCVTTPD2DQZrmb 0U, // VCVTTPD2DQZrmbk 0U, // VCVTTPD2DQZrmbkz 0U, // VCVTTPD2DQZrmk 0U, // VCVTTPD2DQZrmkz 0U, // VCVTTPD2DQZrr 0U, // VCVTTPD2DQZrrb 0U, // VCVTTPD2DQZrrbk 0U, // VCVTTPD2DQZrrbkz 0U, // VCVTTPD2DQZrrk 0U, // VCVTTPD2DQZrrkz 0U, // VCVTTPD2DQrm 0U, // VCVTTPD2DQrr 0U, // VCVTTPD2QQZ128rm 0U, // VCVTTPD2QQZ128rmb 0U, // VCVTTPD2QQZ128rmbk 0U, // VCVTTPD2QQZ128rmbkz 0U, // VCVTTPD2QQZ128rmk 0U, // VCVTTPD2QQZ128rmkz 0U, // VCVTTPD2QQZ128rr 0U, // VCVTTPD2QQZ128rrk 0U, // VCVTTPD2QQZ128rrkz 0U, // VCVTTPD2QQZ256rm 0U, // VCVTTPD2QQZ256rmb 0U, // VCVTTPD2QQZ256rmbk 0U, // VCVTTPD2QQZ256rmbkz 0U, // VCVTTPD2QQZ256rmk 0U, // VCVTTPD2QQZ256rmkz 0U, // VCVTTPD2QQZ256rr 0U, // VCVTTPD2QQZ256rrk 0U, // VCVTTPD2QQZ256rrkz 0U, // VCVTTPD2QQZrm 0U, // VCVTTPD2QQZrmb 0U, // VCVTTPD2QQZrmbk 0U, // VCVTTPD2QQZrmbkz 0U, // VCVTTPD2QQZrmk 0U, // VCVTTPD2QQZrmkz 0U, // VCVTTPD2QQZrr 0U, // VCVTTPD2QQZrrb 0U, // VCVTTPD2QQZrrbk 0U, // VCVTTPD2QQZrrbkz 0U, // VCVTTPD2QQZrrk 0U, // VCVTTPD2QQZrrkz 0U, // VCVTTPD2UDQZ128rm 0U, // VCVTTPD2UDQZ128rmb 0U, // VCVTTPD2UDQZ128rmbk 0U, // VCVTTPD2UDQZ128rmbkz 0U, // VCVTTPD2UDQZ128rmk 0U, // VCVTTPD2UDQZ128rmkz 0U, // VCVTTPD2UDQZ128rr 0U, // VCVTTPD2UDQZ128rrk 0U, // VCVTTPD2UDQZ128rrkz 0U, // VCVTTPD2UDQZ256rm 0U, // VCVTTPD2UDQZ256rmb 0U, // VCVTTPD2UDQZ256rmbk 0U, // VCVTTPD2UDQZ256rmbkz 0U, // VCVTTPD2UDQZ256rmk 0U, // VCVTTPD2UDQZ256rmkz 0U, // VCVTTPD2UDQZ256rr 0U, // VCVTTPD2UDQZ256rrk 0U, // VCVTTPD2UDQZ256rrkz 0U, // VCVTTPD2UDQZrm 0U, // VCVTTPD2UDQZrmb 0U, // VCVTTPD2UDQZrmbk 0U, // VCVTTPD2UDQZrmbkz 0U, // VCVTTPD2UDQZrmk 0U, // VCVTTPD2UDQZrmkz 0U, // VCVTTPD2UDQZrr 0U, // VCVTTPD2UDQZrrb 0U, // VCVTTPD2UDQZrrbk 0U, // VCVTTPD2UDQZrrbkz 0U, // VCVTTPD2UDQZrrk 0U, // VCVTTPD2UDQZrrkz 0U, // VCVTTPD2UQQZ128rm 0U, // VCVTTPD2UQQZ128rmb 0U, // VCVTTPD2UQQZ128rmbk 0U, // VCVTTPD2UQQZ128rmbkz 0U, // VCVTTPD2UQQZ128rmk 0U, // VCVTTPD2UQQZ128rmkz 0U, // VCVTTPD2UQQZ128rr 0U, // VCVTTPD2UQQZ128rrk 0U, // VCVTTPD2UQQZ128rrkz 0U, // VCVTTPD2UQQZ256rm 0U, // VCVTTPD2UQQZ256rmb 0U, // VCVTTPD2UQQZ256rmbk 0U, // VCVTTPD2UQQZ256rmbkz 0U, // VCVTTPD2UQQZ256rmk 0U, // VCVTTPD2UQQZ256rmkz 0U, // VCVTTPD2UQQZ256rr 0U, // VCVTTPD2UQQZ256rrk 0U, // VCVTTPD2UQQZ256rrkz 0U, // VCVTTPD2UQQZrm 0U, // VCVTTPD2UQQZrmb 0U, // VCVTTPD2UQQZrmbk 0U, // VCVTTPD2UQQZrmbkz 0U, // VCVTTPD2UQQZrmk 0U, // VCVTTPD2UQQZrmkz 0U, // VCVTTPD2UQQZrr 0U, // VCVTTPD2UQQZrrb 0U, // VCVTTPD2UQQZrrbk 0U, // VCVTTPD2UQQZrrbkz 0U, // VCVTTPD2UQQZrrk 0U, // VCVTTPD2UQQZrrkz 0U, // VCVTTPS2DQYrm 0U, // VCVTTPS2DQYrr 0U, // VCVTTPS2DQZ128rm 0U, // VCVTTPS2DQZ128rmb 0U, // VCVTTPS2DQZ128rmbk 0U, // VCVTTPS2DQZ128rmbkz 0U, // VCVTTPS2DQZ128rmk 0U, // VCVTTPS2DQZ128rmkz 0U, // VCVTTPS2DQZ128rr 0U, // VCVTTPS2DQZ128rrk 0U, // VCVTTPS2DQZ128rrkz 0U, // VCVTTPS2DQZ256rm 0U, // VCVTTPS2DQZ256rmb 0U, // VCVTTPS2DQZ256rmbk 0U, // VCVTTPS2DQZ256rmbkz 0U, // VCVTTPS2DQZ256rmk 0U, // VCVTTPS2DQZ256rmkz 0U, // VCVTTPS2DQZ256rr 0U, // VCVTTPS2DQZ256rrk 0U, // VCVTTPS2DQZ256rrkz 0U, // VCVTTPS2DQZrm 0U, // VCVTTPS2DQZrmb 0U, // VCVTTPS2DQZrmbk 0U, // VCVTTPS2DQZrmbkz 0U, // VCVTTPS2DQZrmk 0U, // VCVTTPS2DQZrmkz 0U, // VCVTTPS2DQZrr 0U, // VCVTTPS2DQZrrb 0U, // VCVTTPS2DQZrrbk 0U, // VCVTTPS2DQZrrbkz 0U, // VCVTTPS2DQZrrk 0U, // VCVTTPS2DQZrrkz 0U, // VCVTTPS2DQrm 0U, // VCVTTPS2DQrr 0U, // VCVTTPS2QQZ128rm 0U, // VCVTTPS2QQZ128rmb 0U, // VCVTTPS2QQZ128rmbk 0U, // VCVTTPS2QQZ128rmbkz 0U, // VCVTTPS2QQZ128rmk 0U, // VCVTTPS2QQZ128rmkz 0U, // VCVTTPS2QQZ128rr 0U, // VCVTTPS2QQZ128rrk 0U, // VCVTTPS2QQZ128rrkz 0U, // VCVTTPS2QQZ256rm 0U, // VCVTTPS2QQZ256rmb 0U, // VCVTTPS2QQZ256rmbk 0U, // VCVTTPS2QQZ256rmbkz 0U, // VCVTTPS2QQZ256rmk 0U, // VCVTTPS2QQZ256rmkz 0U, // VCVTTPS2QQZ256rr 0U, // VCVTTPS2QQZ256rrk 0U, // VCVTTPS2QQZ256rrkz 0U, // VCVTTPS2QQZrm 0U, // VCVTTPS2QQZrmb 0U, // VCVTTPS2QQZrmbk 0U, // VCVTTPS2QQZrmbkz 0U, // VCVTTPS2QQZrmk 0U, // VCVTTPS2QQZrmkz 0U, // VCVTTPS2QQZrr 0U, // VCVTTPS2QQZrrb 0U, // VCVTTPS2QQZrrbk 0U, // VCVTTPS2QQZrrbkz 0U, // VCVTTPS2QQZrrk 0U, // VCVTTPS2QQZrrkz 0U, // VCVTTPS2UDQZ128rm 0U, // VCVTTPS2UDQZ128rmb 0U, // VCVTTPS2UDQZ128rmbk 0U, // VCVTTPS2UDQZ128rmbkz 0U, // VCVTTPS2UDQZ128rmk 0U, // VCVTTPS2UDQZ128rmkz 0U, // VCVTTPS2UDQZ128rr 0U, // VCVTTPS2UDQZ128rrk 0U, // VCVTTPS2UDQZ128rrkz 0U, // VCVTTPS2UDQZ256rm 0U, // VCVTTPS2UDQZ256rmb 0U, // VCVTTPS2UDQZ256rmbk 0U, // VCVTTPS2UDQZ256rmbkz 0U, // VCVTTPS2UDQZ256rmk 0U, // VCVTTPS2UDQZ256rmkz 0U, // VCVTTPS2UDQZ256rr 0U, // VCVTTPS2UDQZ256rrk 0U, // VCVTTPS2UDQZ256rrkz 0U, // VCVTTPS2UDQZrm 0U, // VCVTTPS2UDQZrmb 0U, // VCVTTPS2UDQZrmbk 0U, // VCVTTPS2UDQZrmbkz 0U, // VCVTTPS2UDQZrmk 0U, // VCVTTPS2UDQZrmkz 0U, // VCVTTPS2UDQZrr 0U, // VCVTTPS2UDQZrrb 0U, // VCVTTPS2UDQZrrbk 0U, // VCVTTPS2UDQZrrbkz 0U, // VCVTTPS2UDQZrrk 0U, // VCVTTPS2UDQZrrkz 0U, // VCVTTPS2UQQZ128rm 0U, // VCVTTPS2UQQZ128rmb 0U, // VCVTTPS2UQQZ128rmbk 0U, // VCVTTPS2UQQZ128rmbkz 0U, // VCVTTPS2UQQZ128rmk 0U, // VCVTTPS2UQQZ128rmkz 0U, // VCVTTPS2UQQZ128rr 0U, // VCVTTPS2UQQZ128rrk 0U, // VCVTTPS2UQQZ128rrkz 0U, // VCVTTPS2UQQZ256rm 0U, // VCVTTPS2UQQZ256rmb 0U, // VCVTTPS2UQQZ256rmbk 0U, // VCVTTPS2UQQZ256rmbkz 0U, // VCVTTPS2UQQZ256rmk 0U, // VCVTTPS2UQQZ256rmkz 0U, // VCVTTPS2UQQZ256rr 0U, // VCVTTPS2UQQZ256rrk 0U, // VCVTTPS2UQQZ256rrkz 0U, // VCVTTPS2UQQZrm 0U, // VCVTTPS2UQQZrmb 0U, // VCVTTPS2UQQZrmbk 0U, // VCVTTPS2UQQZrmbkz 0U, // VCVTTPS2UQQZrmk 0U, // VCVTTPS2UQQZrmkz 0U, // VCVTTPS2UQQZrr 0U, // VCVTTPS2UQQZrrb 0U, // VCVTTPS2UQQZrrbk 0U, // VCVTTPS2UQQZrrbkz 0U, // VCVTTPS2UQQZrrk 0U, // VCVTTPS2UQQZrrkz 0U, // VCVTTSD2SI64Zrm 0U, // VCVTTSD2SI64Zrm_Int 0U, // VCVTTSD2SI64Zrr 0U, // VCVTTSD2SI64Zrr_Int 0U, // VCVTTSD2SI64Zrrb_Int 0U, // VCVTTSD2SI64rm 0U, // VCVTTSD2SI64rm_Int 0U, // VCVTTSD2SI64rr 0U, // VCVTTSD2SI64rr_Int 0U, // VCVTTSD2SIZrm 0U, // VCVTTSD2SIZrm_Int 0U, // VCVTTSD2SIZrr 0U, // VCVTTSD2SIZrr_Int 0U, // VCVTTSD2SIZrrb_Int 0U, // VCVTTSD2SIrm 0U, // VCVTTSD2SIrm_Int 0U, // VCVTTSD2SIrr 0U, // VCVTTSD2SIrr_Int 0U, // VCVTTSD2USI64Zrm 0U, // VCVTTSD2USI64Zrm_Int 0U, // VCVTTSD2USI64Zrr 0U, // VCVTTSD2USI64Zrr_Int 0U, // VCVTTSD2USI64Zrrb_Int 0U, // VCVTTSD2USIZrm 0U, // VCVTTSD2USIZrm_Int 0U, // VCVTTSD2USIZrr 0U, // VCVTTSD2USIZrr_Int 0U, // VCVTTSD2USIZrrb_Int 0U, // VCVTTSS2SI64Zrm 0U, // VCVTTSS2SI64Zrm_Int 0U, // VCVTTSS2SI64Zrr 0U, // VCVTTSS2SI64Zrr_Int 0U, // VCVTTSS2SI64Zrrb_Int 0U, // VCVTTSS2SI64rm 0U, // VCVTTSS2SI64rm_Int 0U, // VCVTTSS2SI64rr 0U, // VCVTTSS2SI64rr_Int 0U, // VCVTTSS2SIZrm 0U, // VCVTTSS2SIZrm_Int 0U, // VCVTTSS2SIZrr 0U, // VCVTTSS2SIZrr_Int 0U, // VCVTTSS2SIZrrb_Int 0U, // VCVTTSS2SIrm 0U, // VCVTTSS2SIrm_Int 0U, // VCVTTSS2SIrr 0U, // VCVTTSS2SIrr_Int 0U, // VCVTTSS2USI64Zrm 0U, // VCVTTSS2USI64Zrm_Int 0U, // VCVTTSS2USI64Zrr 0U, // VCVTTSS2USI64Zrr_Int 0U, // VCVTTSS2USI64Zrrb_Int 0U, // VCVTTSS2USIZrm 0U, // VCVTTSS2USIZrm_Int 0U, // VCVTTSS2USIZrr 0U, // VCVTTSS2USIZrr_Int 0U, // VCVTTSS2USIZrrb_Int 0U, // VCVTUDQ2PDZ128rm 0U, // VCVTUDQ2PDZ128rmb 0U, // VCVTUDQ2PDZ128rmbk 0U, // VCVTUDQ2PDZ128rmbkz 0U, // VCVTUDQ2PDZ128rmk 0U, // VCVTUDQ2PDZ128rmkz 0U, // VCVTUDQ2PDZ128rr 0U, // VCVTUDQ2PDZ128rrk 0U, // VCVTUDQ2PDZ128rrkz 0U, // VCVTUDQ2PDZ256rm 0U, // VCVTUDQ2PDZ256rmb 0U, // VCVTUDQ2PDZ256rmbk 0U, // VCVTUDQ2PDZ256rmbkz 0U, // VCVTUDQ2PDZ256rmk 0U, // VCVTUDQ2PDZ256rmkz 0U, // VCVTUDQ2PDZ256rr 0U, // VCVTUDQ2PDZ256rrk 0U, // VCVTUDQ2PDZ256rrkz 0U, // VCVTUDQ2PDZrm 0U, // VCVTUDQ2PDZrmb 0U, // VCVTUDQ2PDZrmbk 0U, // VCVTUDQ2PDZrmbkz 0U, // VCVTUDQ2PDZrmk 0U, // VCVTUDQ2PDZrmkz 0U, // VCVTUDQ2PDZrr 0U, // VCVTUDQ2PDZrrk 0U, // VCVTUDQ2PDZrrkz 0U, // VCVTUDQ2PSZ128rm 0U, // VCVTUDQ2PSZ128rmb 0U, // VCVTUDQ2PSZ128rmbk 0U, // VCVTUDQ2PSZ128rmbkz 0U, // VCVTUDQ2PSZ128rmk 0U, // VCVTUDQ2PSZ128rmkz 0U, // VCVTUDQ2PSZ128rr 0U, // VCVTUDQ2PSZ128rrk 0U, // VCVTUDQ2PSZ128rrkz 0U, // VCVTUDQ2PSZ256rm 0U, // VCVTUDQ2PSZ256rmb 0U, // VCVTUDQ2PSZ256rmbk 0U, // VCVTUDQ2PSZ256rmbkz 0U, // VCVTUDQ2PSZ256rmk 0U, // VCVTUDQ2PSZ256rmkz 0U, // VCVTUDQ2PSZ256rr 0U, // VCVTUDQ2PSZ256rrk 0U, // VCVTUDQ2PSZ256rrkz 0U, // VCVTUDQ2PSZrm 0U, // VCVTUDQ2PSZrmb 0U, // VCVTUDQ2PSZrmbk 0U, // VCVTUDQ2PSZrmbkz 0U, // VCVTUDQ2PSZrmk 0U, // VCVTUDQ2PSZrmkz 0U, // VCVTUDQ2PSZrr 0U, // VCVTUDQ2PSZrrb 0U, // VCVTUDQ2PSZrrbk 0U, // VCVTUDQ2PSZrrbkz 0U, // VCVTUDQ2PSZrrk 0U, // VCVTUDQ2PSZrrkz 0U, // VCVTUQQ2PDZ128rm 0U, // VCVTUQQ2PDZ128rmb 0U, // VCVTUQQ2PDZ128rmbk 0U, // VCVTUQQ2PDZ128rmbkz 0U, // VCVTUQQ2PDZ128rmk 0U, // VCVTUQQ2PDZ128rmkz 0U, // VCVTUQQ2PDZ128rr 0U, // VCVTUQQ2PDZ128rrk 0U, // VCVTUQQ2PDZ128rrkz 0U, // VCVTUQQ2PDZ256rm 0U, // VCVTUQQ2PDZ256rmb 0U, // VCVTUQQ2PDZ256rmbk 0U, // VCVTUQQ2PDZ256rmbkz 0U, // VCVTUQQ2PDZ256rmk 0U, // VCVTUQQ2PDZ256rmkz 0U, // VCVTUQQ2PDZ256rr 0U, // VCVTUQQ2PDZ256rrk 0U, // VCVTUQQ2PDZ256rrkz 0U, // VCVTUQQ2PDZrm 0U, // VCVTUQQ2PDZrmb 0U, // VCVTUQQ2PDZrmbk 0U, // VCVTUQQ2PDZrmbkz 0U, // VCVTUQQ2PDZrmk 0U, // VCVTUQQ2PDZrmkz 0U, // VCVTUQQ2PDZrr 0U, // VCVTUQQ2PDZrrb 0U, // VCVTUQQ2PDZrrbk 0U, // VCVTUQQ2PDZrrbkz 0U, // VCVTUQQ2PDZrrk 0U, // VCVTUQQ2PDZrrkz 0U, // VCVTUQQ2PSZ128rm 0U, // VCVTUQQ2PSZ128rmb 0U, // VCVTUQQ2PSZ128rmbk 0U, // VCVTUQQ2PSZ128rmbkz 0U, // VCVTUQQ2PSZ128rmk 0U, // VCVTUQQ2PSZ128rmkz 0U, // VCVTUQQ2PSZ128rr 0U, // VCVTUQQ2PSZ128rrk 0U, // VCVTUQQ2PSZ128rrkz 0U, // VCVTUQQ2PSZ256rm 0U, // VCVTUQQ2PSZ256rmb 0U, // VCVTUQQ2PSZ256rmbk 0U, // VCVTUQQ2PSZ256rmbkz 0U, // VCVTUQQ2PSZ256rmk 0U, // VCVTUQQ2PSZ256rmkz 0U, // VCVTUQQ2PSZ256rr 0U, // VCVTUQQ2PSZ256rrk 0U, // VCVTUQQ2PSZ256rrkz 0U, // VCVTUQQ2PSZrm 0U, // VCVTUQQ2PSZrmb 0U, // VCVTUQQ2PSZrmbk 0U, // VCVTUQQ2PSZrmbkz 0U, // VCVTUQQ2PSZrmk 0U, // VCVTUQQ2PSZrmkz 0U, // VCVTUQQ2PSZrr 0U, // VCVTUQQ2PSZrrb 0U, // VCVTUQQ2PSZrrbk 0U, // VCVTUQQ2PSZrrbkz 0U, // VCVTUQQ2PSZrrk 0U, // VCVTUQQ2PSZrrkz 0U, // VCVTUSI2SDZrm 0U, // VCVTUSI2SDZrm_Int 0U, // VCVTUSI2SDZrr 0U, // VCVTUSI2SDZrr_Int 0U, // VCVTUSI2SSZrm 0U, // VCVTUSI2SSZrm_Int 0U, // VCVTUSI2SSZrr 0U, // VCVTUSI2SSZrr_Int 0U, // VCVTUSI2SSZrrb_Int 0U, // VCVTUSI642SDZrm 0U, // VCVTUSI642SDZrm_Int 0U, // VCVTUSI642SDZrr 0U, // VCVTUSI642SDZrr_Int 0U, // VCVTUSI642SDZrrb_Int 0U, // VCVTUSI642SSZrm 0U, // VCVTUSI642SSZrm_Int 0U, // VCVTUSI642SSZrr 0U, // VCVTUSI642SSZrr_Int 0U, // VCVTUSI642SSZrrb_Int 0U, // VDBPSADBWZ128rmi 0U, // VDBPSADBWZ128rmik 0U, // VDBPSADBWZ128rmikz 0U, // VDBPSADBWZ128rri 0U, // VDBPSADBWZ128rrik 3U, // VDBPSADBWZ128rrikz 0U, // VDBPSADBWZ256rmi 0U, // VDBPSADBWZ256rmik 0U, // VDBPSADBWZ256rmikz 0U, // VDBPSADBWZ256rri 0U, // VDBPSADBWZ256rrik 3U, // VDBPSADBWZ256rrikz 0U, // VDBPSADBWZrmi 0U, // VDBPSADBWZrmik 0U, // VDBPSADBWZrmikz 0U, // VDBPSADBWZrri 0U, // VDBPSADBWZrrik 3U, // VDBPSADBWZrrikz 0U, // VDIVPDYrm 0U, // VDIVPDYrr 0U, // VDIVPDZ128rm 0U, // VDIVPDZ128rmb 0U, // VDIVPDZ128rmbk 0U, // VDIVPDZ128rmbkz 0U, // VDIVPDZ128rmk 0U, // VDIVPDZ128rmkz 0U, // VDIVPDZ128rr 0U, // VDIVPDZ128rrk 0U, // VDIVPDZ128rrkz 0U, // VDIVPDZ256rm 0U, // VDIVPDZ256rmb 0U, // VDIVPDZ256rmbk 0U, // VDIVPDZ256rmbkz 0U, // VDIVPDZ256rmk 0U, // VDIVPDZ256rmkz 0U, // VDIVPDZ256rr 0U, // VDIVPDZ256rrk 0U, // VDIVPDZ256rrkz 0U, // VDIVPDZrm 0U, // VDIVPDZrmb 0U, // VDIVPDZrmbk 0U, // VDIVPDZrmbkz 0U, // VDIVPDZrmk 0U, // VDIVPDZrmkz 0U, // VDIVPDZrr 0U, // VDIVPDZrrb 0U, // VDIVPDZrrbk 0U, // VDIVPDZrrbkz 0U, // VDIVPDZrrk 0U, // VDIVPDZrrkz 0U, // VDIVPDrm 0U, // VDIVPDrr 0U, // VDIVPSYrm 0U, // VDIVPSYrr 0U, // VDIVPSZ128rm 0U, // VDIVPSZ128rmb 0U, // VDIVPSZ128rmbk 0U, // VDIVPSZ128rmbkz 0U, // VDIVPSZ128rmk 0U, // VDIVPSZ128rmkz 0U, // VDIVPSZ128rr 0U, // VDIVPSZ128rrk 0U, // VDIVPSZ128rrkz 0U, // VDIVPSZ256rm 0U, // VDIVPSZ256rmb 0U, // VDIVPSZ256rmbk 0U, // VDIVPSZ256rmbkz 0U, // VDIVPSZ256rmk 0U, // VDIVPSZ256rmkz 0U, // VDIVPSZ256rr 0U, // VDIVPSZ256rrk 0U, // VDIVPSZ256rrkz 0U, // VDIVPSZrm 0U, // VDIVPSZrmb 0U, // VDIVPSZrmbk 0U, // VDIVPSZrmbkz 0U, // VDIVPSZrmk 0U, // VDIVPSZrmkz 0U, // VDIVPSZrr 0U, // VDIVPSZrrb 0U, // VDIVPSZrrbk 0U, // VDIVPSZrrbkz 0U, // VDIVPSZrrk 0U, // VDIVPSZrrkz 0U, // VDIVPSrm 0U, // VDIVPSrr 0U, // VDIVSDZrm 0U, // VDIVSDZrm_Int 0U, // VDIVSDZrm_Intk 0U, // VDIVSDZrm_Intkz 0U, // VDIVSDZrr 0U, // VDIVSDZrr_Int 0U, // VDIVSDZrr_Intk 0U, // VDIVSDZrr_Intkz 0U, // VDIVSDZrrb_Int 0U, // VDIVSDZrrb_Intk 0U, // VDIVSDZrrb_Intkz 0U, // VDIVSDrm 0U, // VDIVSDrm_Int 0U, // VDIVSDrr 0U, // VDIVSDrr_Int 0U, // VDIVSSZrm 0U, // VDIVSSZrm_Int 0U, // VDIVSSZrm_Intk 0U, // VDIVSSZrm_Intkz 0U, // VDIVSSZrr 0U, // VDIVSSZrr_Int 0U, // VDIVSSZrr_Intk 0U, // VDIVSSZrr_Intkz 0U, // VDIVSSZrrb_Int 0U, // VDIVSSZrrb_Intk 0U, // VDIVSSZrrb_Intkz 0U, // VDIVSSrm 0U, // VDIVSSrm_Int 0U, // VDIVSSrr 0U, // VDIVSSrr_Int 0U, // VDPPDrmi 0U, // VDPPDrri 0U, // VDPPSYrmi 0U, // VDPPSYrri 0U, // VDPPSrmi 0U, // VDPPSrri 0U, // VERRm 0U, // VERRr 0U, // VERWm 0U, // VERWr 0U, // VEXP2PDZm 0U, // VEXP2PDZmb 0U, // VEXP2PDZmbk 0U, // VEXP2PDZmbkz 0U, // VEXP2PDZmk 0U, // VEXP2PDZmkz 0U, // VEXP2PDZr 0U, // VEXP2PDZrb 0U, // VEXP2PDZrbk 0U, // VEXP2PDZrbkz 0U, // VEXP2PDZrk 0U, // VEXP2PDZrkz 0U, // VEXP2PSZm 0U, // VEXP2PSZmb 0U, // VEXP2PSZmbk 0U, // VEXP2PSZmbkz 0U, // VEXP2PSZmk 0U, // VEXP2PSZmkz 0U, // VEXP2PSZr 0U, // VEXP2PSZrb 0U, // VEXP2PSZrbk 0U, // VEXP2PSZrbkz 0U, // VEXP2PSZrk 0U, // VEXP2PSZrkz 0U, // VEXPANDPDZ128rm 0U, // VEXPANDPDZ128rmk 0U, // VEXPANDPDZ128rmkz 0U, // VEXPANDPDZ128rr 0U, // VEXPANDPDZ128rrk 0U, // VEXPANDPDZ128rrkz 0U, // VEXPANDPDZ256rm 0U, // VEXPANDPDZ256rmk 0U, // VEXPANDPDZ256rmkz 0U, // VEXPANDPDZ256rr 0U, // VEXPANDPDZ256rrk 0U, // VEXPANDPDZ256rrkz 0U, // VEXPANDPDZrm 0U, // VEXPANDPDZrmk 0U, // VEXPANDPDZrmkz 0U, // VEXPANDPDZrr 0U, // VEXPANDPDZrrk 0U, // VEXPANDPDZrrkz 0U, // VEXPANDPSZ128rm 0U, // VEXPANDPSZ128rmk 0U, // VEXPANDPSZ128rmkz 0U, // VEXPANDPSZ128rr 0U, // VEXPANDPSZ128rrk 0U, // VEXPANDPSZ128rrkz 0U, // VEXPANDPSZ256rm 0U, // VEXPANDPSZ256rmk 0U, // VEXPANDPSZ256rmkz 0U, // VEXPANDPSZ256rr 0U, // VEXPANDPSZ256rrk 0U, // VEXPANDPSZ256rrkz 0U, // VEXPANDPSZrm 0U, // VEXPANDPSZrmk 0U, // VEXPANDPSZrmkz 0U, // VEXPANDPSZrr 0U, // VEXPANDPSZrrk 0U, // VEXPANDPSZrrkz 0U, // VEXTRACTF128mr 0U, // VEXTRACTF128rr 0U, // VEXTRACTF32x4Z256mr 0U, // VEXTRACTF32x4Z256mrk 0U, // VEXTRACTF32x4Z256rr 0U, // VEXTRACTF32x4Z256rrk 0U, // VEXTRACTF32x4Z256rrkz 0U, // VEXTRACTF32x4Zmr 0U, // VEXTRACTF32x4Zmrk 0U, // VEXTRACTF32x4Zrr 0U, // VEXTRACTF32x4Zrrk 0U, // VEXTRACTF32x4Zrrkz 0U, // VEXTRACTF32x8Zmr 0U, // VEXTRACTF32x8Zmrk 0U, // VEXTRACTF32x8Zrr 0U, // VEXTRACTF32x8Zrrk 0U, // VEXTRACTF32x8Zrrkz 0U, // VEXTRACTF64x2Z256mr 0U, // VEXTRACTF64x2Z256mrk 0U, // VEXTRACTF64x2Z256rr 0U, // VEXTRACTF64x2Z256rrk 0U, // VEXTRACTF64x2Z256rrkz 0U, // VEXTRACTF64x2Zmr 0U, // VEXTRACTF64x2Zmrk 0U, // VEXTRACTF64x2Zrr 0U, // VEXTRACTF64x2Zrrk 0U, // VEXTRACTF64x2Zrrkz 0U, // VEXTRACTF64x4Zmr 0U, // VEXTRACTF64x4Zmrk 0U, // VEXTRACTF64x4Zrr 0U, // VEXTRACTF64x4Zrrk 0U, // VEXTRACTF64x4Zrrkz 0U, // VEXTRACTI128mr 0U, // VEXTRACTI128rr 0U, // VEXTRACTI32x4Z256mr 0U, // VEXTRACTI32x4Z256mrk 0U, // VEXTRACTI32x4Z256rr 0U, // VEXTRACTI32x4Z256rrk 0U, // VEXTRACTI32x4Z256rrkz 0U, // VEXTRACTI32x4Zmr 0U, // VEXTRACTI32x4Zmrk 0U, // VEXTRACTI32x4Zrr 0U, // VEXTRACTI32x4Zrrk 0U, // VEXTRACTI32x4Zrrkz 0U, // VEXTRACTI32x8Zmr 0U, // VEXTRACTI32x8Zmrk 0U, // VEXTRACTI32x8Zrr 0U, // VEXTRACTI32x8Zrrk 0U, // VEXTRACTI32x8Zrrkz 0U, // VEXTRACTI64x2Z256mr 0U, // VEXTRACTI64x2Z256mrk 0U, // VEXTRACTI64x2Z256rr 0U, // VEXTRACTI64x2Z256rrk 0U, // VEXTRACTI64x2Z256rrkz 0U, // VEXTRACTI64x2Zmr 0U, // VEXTRACTI64x2Zmrk 0U, // VEXTRACTI64x2Zrr 0U, // VEXTRACTI64x2Zrrk 0U, // VEXTRACTI64x2Zrrkz 0U, // VEXTRACTI64x4Zmr 0U, // VEXTRACTI64x4Zmrk 0U, // VEXTRACTI64x4Zrr 0U, // VEXTRACTI64x4Zrrk 0U, // VEXTRACTI64x4Zrrkz 0U, // VEXTRACTPSZmr 0U, // VEXTRACTPSZrr 0U, // VEXTRACTPSmr 0U, // VEXTRACTPSrr 0U, // VFIXUPIMMPDZ128rmbi 0U, // VFIXUPIMMPDZ128rmbik 2U, // VFIXUPIMMPDZ128rmbikz 0U, // VFIXUPIMMPDZ128rmi 0U, // VFIXUPIMMPDZ128rmik 0U, // VFIXUPIMMPDZ128rmikz 0U, // VFIXUPIMMPDZ128rri 0U, // VFIXUPIMMPDZ128rrik 0U, // VFIXUPIMMPDZ128rrikz 0U, // VFIXUPIMMPDZ256rmbi 0U, // VFIXUPIMMPDZ256rmbik 2U, // VFIXUPIMMPDZ256rmbikz 0U, // VFIXUPIMMPDZ256rmi 0U, // VFIXUPIMMPDZ256rmik 0U, // VFIXUPIMMPDZ256rmikz 0U, // VFIXUPIMMPDZ256rri 0U, // VFIXUPIMMPDZ256rrik 0U, // VFIXUPIMMPDZ256rrikz 0U, // VFIXUPIMMPDZrmbi 0U, // VFIXUPIMMPDZrmbik 2U, // VFIXUPIMMPDZrmbikz 0U, // VFIXUPIMMPDZrmi 0U, // VFIXUPIMMPDZrmik 0U, // VFIXUPIMMPDZrmikz 0U, // VFIXUPIMMPDZrri 0U, // VFIXUPIMMPDZrrib 0U, // VFIXUPIMMPDZrribk 0U, // VFIXUPIMMPDZrribkz 0U, // VFIXUPIMMPDZrrik 0U, // VFIXUPIMMPDZrrikz 0U, // VFIXUPIMMPSZ128rmbi 0U, // VFIXUPIMMPSZ128rmbik 2U, // VFIXUPIMMPSZ128rmbikz 0U, // VFIXUPIMMPSZ128rmi 0U, // VFIXUPIMMPSZ128rmik 0U, // VFIXUPIMMPSZ128rmikz 0U, // VFIXUPIMMPSZ128rri 0U, // VFIXUPIMMPSZ128rrik 0U, // VFIXUPIMMPSZ128rrikz 0U, // VFIXUPIMMPSZ256rmbi 0U, // VFIXUPIMMPSZ256rmbik 2U, // VFIXUPIMMPSZ256rmbikz 0U, // VFIXUPIMMPSZ256rmi 0U, // VFIXUPIMMPSZ256rmik 0U, // VFIXUPIMMPSZ256rmikz 0U, // VFIXUPIMMPSZ256rri 0U, // VFIXUPIMMPSZ256rrik 0U, // VFIXUPIMMPSZ256rrikz 0U, // VFIXUPIMMPSZrmbi 0U, // VFIXUPIMMPSZrmbik 2U, // VFIXUPIMMPSZrmbikz 0U, // VFIXUPIMMPSZrmi 0U, // VFIXUPIMMPSZrmik 0U, // VFIXUPIMMPSZrmikz 0U, // VFIXUPIMMPSZrri 0U, // VFIXUPIMMPSZrrib 0U, // VFIXUPIMMPSZrribk 0U, // VFIXUPIMMPSZrribkz 0U, // VFIXUPIMMPSZrrik 0U, // VFIXUPIMMPSZrrikz 0U, // VFIXUPIMMSDZrmi 0U, // VFIXUPIMMSDZrmik 2U, // VFIXUPIMMSDZrmikz 0U, // VFIXUPIMMSDZrri 0U, // VFIXUPIMMSDZrrib 0U, // VFIXUPIMMSDZrribk 0U, // VFIXUPIMMSDZrribkz 0U, // VFIXUPIMMSDZrrik 0U, // VFIXUPIMMSDZrrikz 0U, // VFIXUPIMMSSZrmi 0U, // VFIXUPIMMSSZrmik 2U, // VFIXUPIMMSSZrmikz 0U, // VFIXUPIMMSSZrri 0U, // VFIXUPIMMSSZrrib 0U, // VFIXUPIMMSSZrribk 0U, // VFIXUPIMMSSZrribkz 0U, // VFIXUPIMMSSZrrik 0U, // VFIXUPIMMSSZrrikz 0U, // VFMADD132PDYm 0U, // VFMADD132PDYr 0U, // VFMADD132PDZ128m 0U, // VFMADD132PDZ128mb 0U, // VFMADD132PDZ128mbk 0U, // VFMADD132PDZ128mbkz 0U, // VFMADD132PDZ128mk 0U, // VFMADD132PDZ128mkz 0U, // VFMADD132PDZ128r 0U, // VFMADD132PDZ128rk 0U, // VFMADD132PDZ128rkz 0U, // VFMADD132PDZ256m 0U, // VFMADD132PDZ256mb 0U, // VFMADD132PDZ256mbk 0U, // VFMADD132PDZ256mbkz 0U, // VFMADD132PDZ256mk 0U, // VFMADD132PDZ256mkz 0U, // VFMADD132PDZ256r 0U, // VFMADD132PDZ256rk 0U, // VFMADD132PDZ256rkz 0U, // VFMADD132PDZm 0U, // VFMADD132PDZmb 0U, // VFMADD132PDZmbk 0U, // VFMADD132PDZmbkz 0U, // VFMADD132PDZmk 0U, // VFMADD132PDZmkz 0U, // VFMADD132PDZr 0U, // VFMADD132PDZrb 0U, // VFMADD132PDZrbk 0U, // VFMADD132PDZrbkz 0U, // VFMADD132PDZrk 0U, // VFMADD132PDZrkz 0U, // VFMADD132PDm 0U, // VFMADD132PDr 0U, // VFMADD132PSYm 0U, // VFMADD132PSYr 0U, // VFMADD132PSZ128m 0U, // VFMADD132PSZ128mb 0U, // VFMADD132PSZ128mbk 0U, // VFMADD132PSZ128mbkz 0U, // VFMADD132PSZ128mk 0U, // VFMADD132PSZ128mkz 0U, // VFMADD132PSZ128r 0U, // VFMADD132PSZ128rk 0U, // VFMADD132PSZ128rkz 0U, // VFMADD132PSZ256m 0U, // VFMADD132PSZ256mb 0U, // VFMADD132PSZ256mbk 0U, // VFMADD132PSZ256mbkz 0U, // VFMADD132PSZ256mk 0U, // VFMADD132PSZ256mkz 0U, // VFMADD132PSZ256r 0U, // VFMADD132PSZ256rk 0U, // VFMADD132PSZ256rkz 0U, // VFMADD132PSZm 0U, // VFMADD132PSZmb 0U, // VFMADD132PSZmbk 0U, // VFMADD132PSZmbkz 0U, // VFMADD132PSZmk 0U, // VFMADD132PSZmkz 0U, // VFMADD132PSZr 0U, // VFMADD132PSZrb 0U, // VFMADD132PSZrbk 0U, // VFMADD132PSZrbkz 0U, // VFMADD132PSZrk 0U, // VFMADD132PSZrkz 0U, // VFMADD132PSm 0U, // VFMADD132PSr 0U, // VFMADD132SDZm 0U, // VFMADD132SDZm_Int 0U, // VFMADD132SDZm_Intk 0U, // VFMADD132SDZm_Intkz 0U, // VFMADD132SDZr 0U, // VFMADD132SDZr_Int 0U, // VFMADD132SDZr_Intk 0U, // VFMADD132SDZr_Intkz 0U, // VFMADD132SDZrb 0U, // VFMADD132SDZrb_Int 0U, // VFMADD132SDZrb_Intk 0U, // VFMADD132SDZrb_Intkz 0U, // VFMADD132SDm 0U, // VFMADD132SDm_Int 0U, // VFMADD132SDr 0U, // VFMADD132SDr_Int 0U, // VFMADD132SSZm 0U, // VFMADD132SSZm_Int 0U, // VFMADD132SSZm_Intk 0U, // VFMADD132SSZm_Intkz 0U, // VFMADD132SSZr 0U, // VFMADD132SSZr_Int 0U, // VFMADD132SSZr_Intk 0U, // VFMADD132SSZr_Intkz 0U, // VFMADD132SSZrb 0U, // VFMADD132SSZrb_Int 0U, // VFMADD132SSZrb_Intk 0U, // VFMADD132SSZrb_Intkz 0U, // VFMADD132SSm 0U, // VFMADD132SSm_Int 0U, // VFMADD132SSr 0U, // VFMADD132SSr_Int 0U, // VFMADD213PDYm 0U, // VFMADD213PDYr 0U, // VFMADD213PDZ128m 0U, // VFMADD213PDZ128mb 0U, // VFMADD213PDZ128mbk 0U, // VFMADD213PDZ128mbkz 0U, // VFMADD213PDZ128mk 0U, // VFMADD213PDZ128mkz 0U, // VFMADD213PDZ128r 0U, // VFMADD213PDZ128rk 0U, // VFMADD213PDZ128rkz 0U, // VFMADD213PDZ256m 0U, // VFMADD213PDZ256mb 0U, // VFMADD213PDZ256mbk 0U, // VFMADD213PDZ256mbkz 0U, // VFMADD213PDZ256mk 0U, // VFMADD213PDZ256mkz 0U, // VFMADD213PDZ256r 0U, // VFMADD213PDZ256rk 0U, // VFMADD213PDZ256rkz 0U, // VFMADD213PDZm 0U, // VFMADD213PDZmb 0U, // VFMADD213PDZmbk 0U, // VFMADD213PDZmbkz 0U, // VFMADD213PDZmk 0U, // VFMADD213PDZmkz 0U, // VFMADD213PDZr 0U, // VFMADD213PDZrb 0U, // VFMADD213PDZrbk 0U, // VFMADD213PDZrbkz 0U, // VFMADD213PDZrk 0U, // VFMADD213PDZrkz 0U, // VFMADD213PDm 0U, // VFMADD213PDr 0U, // VFMADD213PSYm 0U, // VFMADD213PSYr 0U, // VFMADD213PSZ128m 0U, // VFMADD213PSZ128mb 0U, // VFMADD213PSZ128mbk 0U, // VFMADD213PSZ128mbkz 0U, // VFMADD213PSZ128mk 0U, // VFMADD213PSZ128mkz 0U, // VFMADD213PSZ128r 0U, // VFMADD213PSZ128rk 0U, // VFMADD213PSZ128rkz 0U, // VFMADD213PSZ256m 0U, // VFMADD213PSZ256mb 0U, // VFMADD213PSZ256mbk 0U, // VFMADD213PSZ256mbkz 0U, // VFMADD213PSZ256mk 0U, // VFMADD213PSZ256mkz 0U, // VFMADD213PSZ256r 0U, // VFMADD213PSZ256rk 0U, // VFMADD213PSZ256rkz 0U, // VFMADD213PSZm 0U, // VFMADD213PSZmb 0U, // VFMADD213PSZmbk 0U, // VFMADD213PSZmbkz 0U, // VFMADD213PSZmk 0U, // VFMADD213PSZmkz 0U, // VFMADD213PSZr 0U, // VFMADD213PSZrb 0U, // VFMADD213PSZrbk 0U, // VFMADD213PSZrbkz 0U, // VFMADD213PSZrk 0U, // VFMADD213PSZrkz 0U, // VFMADD213PSm 0U, // VFMADD213PSr 0U, // VFMADD213SDZm 0U, // VFMADD213SDZm_Int 0U, // VFMADD213SDZm_Intk 0U, // VFMADD213SDZm_Intkz 0U, // VFMADD213SDZr 0U, // VFMADD213SDZr_Int 0U, // VFMADD213SDZr_Intk 0U, // VFMADD213SDZr_Intkz 0U, // VFMADD213SDZrb 0U, // VFMADD213SDZrb_Int 0U, // VFMADD213SDZrb_Intk 0U, // VFMADD213SDZrb_Intkz 0U, // VFMADD213SDm 0U, // VFMADD213SDm_Int 0U, // VFMADD213SDr 0U, // VFMADD213SDr_Int 0U, // VFMADD213SSZm 0U, // VFMADD213SSZm_Int 0U, // VFMADD213SSZm_Intk 0U, // VFMADD213SSZm_Intkz 0U, // VFMADD213SSZr 0U, // VFMADD213SSZr_Int 0U, // VFMADD213SSZr_Intk 0U, // VFMADD213SSZr_Intkz 0U, // VFMADD213SSZrb 0U, // VFMADD213SSZrb_Int 0U, // VFMADD213SSZrb_Intk 0U, // VFMADD213SSZrb_Intkz 0U, // VFMADD213SSm 0U, // VFMADD213SSm_Int 0U, // VFMADD213SSr 0U, // VFMADD213SSr_Int 0U, // VFMADD231PDYm 0U, // VFMADD231PDYr 0U, // VFMADD231PDZ128m 0U, // VFMADD231PDZ128mb 0U, // VFMADD231PDZ128mbk 0U, // VFMADD231PDZ128mbkz 0U, // VFMADD231PDZ128mk 0U, // VFMADD231PDZ128mkz 0U, // VFMADD231PDZ128r 0U, // VFMADD231PDZ128rk 0U, // VFMADD231PDZ128rkz 0U, // VFMADD231PDZ256m 0U, // VFMADD231PDZ256mb 0U, // VFMADD231PDZ256mbk 0U, // VFMADD231PDZ256mbkz 0U, // VFMADD231PDZ256mk 0U, // VFMADD231PDZ256mkz 0U, // VFMADD231PDZ256r 0U, // VFMADD231PDZ256rk 0U, // VFMADD231PDZ256rkz 0U, // VFMADD231PDZm 0U, // VFMADD231PDZmb 0U, // VFMADD231PDZmbk 0U, // VFMADD231PDZmbkz 0U, // VFMADD231PDZmk 0U, // VFMADD231PDZmkz 0U, // VFMADD231PDZr 0U, // VFMADD231PDZrb 0U, // VFMADD231PDZrbk 0U, // VFMADD231PDZrbkz 0U, // VFMADD231PDZrk 0U, // VFMADD231PDZrkz 0U, // VFMADD231PDm 0U, // VFMADD231PDr 0U, // VFMADD231PSYm 0U, // VFMADD231PSYr 0U, // VFMADD231PSZ128m 0U, // VFMADD231PSZ128mb 0U, // VFMADD231PSZ128mbk 0U, // VFMADD231PSZ128mbkz 0U, // VFMADD231PSZ128mk 0U, // VFMADD231PSZ128mkz 0U, // VFMADD231PSZ128r 0U, // VFMADD231PSZ128rk 0U, // VFMADD231PSZ128rkz 0U, // VFMADD231PSZ256m 0U, // VFMADD231PSZ256mb 0U, // VFMADD231PSZ256mbk 0U, // VFMADD231PSZ256mbkz 0U, // VFMADD231PSZ256mk 0U, // VFMADD231PSZ256mkz 0U, // VFMADD231PSZ256r 0U, // VFMADD231PSZ256rk 0U, // VFMADD231PSZ256rkz 0U, // VFMADD231PSZm 0U, // VFMADD231PSZmb 0U, // VFMADD231PSZmbk 0U, // VFMADD231PSZmbkz 0U, // VFMADD231PSZmk 0U, // VFMADD231PSZmkz 0U, // VFMADD231PSZr 0U, // VFMADD231PSZrb 0U, // VFMADD231PSZrbk 0U, // VFMADD231PSZrbkz 0U, // VFMADD231PSZrk 0U, // VFMADD231PSZrkz 0U, // VFMADD231PSm 0U, // VFMADD231PSr 0U, // VFMADD231SDZm 0U, // VFMADD231SDZm_Int 0U, // VFMADD231SDZm_Intk 0U, // VFMADD231SDZm_Intkz 0U, // VFMADD231SDZr 0U, // VFMADD231SDZr_Int 0U, // VFMADD231SDZr_Intk 0U, // VFMADD231SDZr_Intkz 0U, // VFMADD231SDZrb 0U, // VFMADD231SDZrb_Int 0U, // VFMADD231SDZrb_Intk 0U, // VFMADD231SDZrb_Intkz 0U, // VFMADD231SDm 0U, // VFMADD231SDm_Int 0U, // VFMADD231SDr 0U, // VFMADD231SDr_Int 0U, // VFMADD231SSZm 0U, // VFMADD231SSZm_Int 0U, // VFMADD231SSZm_Intk 0U, // VFMADD231SSZm_Intkz 0U, // VFMADD231SSZr 0U, // VFMADD231SSZr_Int 0U, // VFMADD231SSZr_Intk 0U, // VFMADD231SSZr_Intkz 0U, // VFMADD231SSZrb 0U, // VFMADD231SSZrb_Int 0U, // VFMADD231SSZrb_Intk 0U, // VFMADD231SSZrb_Intkz 0U, // VFMADD231SSm 0U, // VFMADD231SSm_Int 0U, // VFMADD231SSr 0U, // VFMADD231SSr_Int 0U, // VFMADDPD4Ymr 0U, // VFMADDPD4Yrm 0U, // VFMADDPD4Yrr 0U, // VFMADDPD4Yrr_REV 0U, // VFMADDPD4mr 0U, // VFMADDPD4rm 0U, // VFMADDPD4rr 0U, // VFMADDPD4rr_REV 0U, // VFMADDPS4Ymr 0U, // VFMADDPS4Yrm 0U, // VFMADDPS4Yrr 0U, // VFMADDPS4Yrr_REV 0U, // VFMADDPS4mr 0U, // VFMADDPS4rm 0U, // VFMADDPS4rr 0U, // VFMADDPS4rr_REV 0U, // VFMADDSD4mr 0U, // VFMADDSD4mr_Int 0U, // VFMADDSD4rm 0U, // VFMADDSD4rm_Int 0U, // VFMADDSD4rr 0U, // VFMADDSD4rr_Int 0U, // VFMADDSD4rr_Int_REV 0U, // VFMADDSD4rr_REV 0U, // VFMADDSS4mr 0U, // VFMADDSS4mr_Int 0U, // VFMADDSS4rm 0U, // VFMADDSS4rm_Int 0U, // VFMADDSS4rr 0U, // VFMADDSS4rr_Int 0U, // VFMADDSS4rr_Int_REV 0U, // VFMADDSS4rr_REV 0U, // VFMADDSUB132PDYm 0U, // VFMADDSUB132PDYr 0U, // VFMADDSUB132PDZ128m 0U, // VFMADDSUB132PDZ128mb 0U, // VFMADDSUB132PDZ128mbk 0U, // VFMADDSUB132PDZ128mbkz 0U, // VFMADDSUB132PDZ128mk 0U, // VFMADDSUB132PDZ128mkz 0U, // VFMADDSUB132PDZ128r 0U, // VFMADDSUB132PDZ128rk 0U, // VFMADDSUB132PDZ128rkz 0U, // VFMADDSUB132PDZ256m 0U, // VFMADDSUB132PDZ256mb 0U, // VFMADDSUB132PDZ256mbk 0U, // VFMADDSUB132PDZ256mbkz 0U, // VFMADDSUB132PDZ256mk 0U, // VFMADDSUB132PDZ256mkz 0U, // VFMADDSUB132PDZ256r 0U, // VFMADDSUB132PDZ256rk 0U, // VFMADDSUB132PDZ256rkz 0U, // VFMADDSUB132PDZm 0U, // VFMADDSUB132PDZmb 0U, // VFMADDSUB132PDZmbk 0U, // VFMADDSUB132PDZmbkz 0U, // VFMADDSUB132PDZmk 0U, // VFMADDSUB132PDZmkz 0U, // VFMADDSUB132PDZr 0U, // VFMADDSUB132PDZrb 0U, // VFMADDSUB132PDZrbk 0U, // VFMADDSUB132PDZrbkz 0U, // VFMADDSUB132PDZrk 0U, // VFMADDSUB132PDZrkz 0U, // VFMADDSUB132PDm 0U, // VFMADDSUB132PDr 0U, // VFMADDSUB132PSYm 0U, // VFMADDSUB132PSYr 0U, // VFMADDSUB132PSZ128m 0U, // VFMADDSUB132PSZ128mb 0U, // VFMADDSUB132PSZ128mbk 0U, // VFMADDSUB132PSZ128mbkz 0U, // VFMADDSUB132PSZ128mk 0U, // VFMADDSUB132PSZ128mkz 0U, // VFMADDSUB132PSZ128r 0U, // VFMADDSUB132PSZ128rk 0U, // VFMADDSUB132PSZ128rkz 0U, // VFMADDSUB132PSZ256m 0U, // VFMADDSUB132PSZ256mb 0U, // VFMADDSUB132PSZ256mbk 0U, // VFMADDSUB132PSZ256mbkz 0U, // VFMADDSUB132PSZ256mk 0U, // VFMADDSUB132PSZ256mkz 0U, // VFMADDSUB132PSZ256r 0U, // VFMADDSUB132PSZ256rk 0U, // VFMADDSUB132PSZ256rkz 0U, // VFMADDSUB132PSZm 0U, // VFMADDSUB132PSZmb 0U, // VFMADDSUB132PSZmbk 0U, // VFMADDSUB132PSZmbkz 0U, // VFMADDSUB132PSZmk 0U, // VFMADDSUB132PSZmkz 0U, // VFMADDSUB132PSZr 0U, // VFMADDSUB132PSZrb 0U, // VFMADDSUB132PSZrbk 0U, // VFMADDSUB132PSZrbkz 0U, // VFMADDSUB132PSZrk 0U, // VFMADDSUB132PSZrkz 0U, // VFMADDSUB132PSm 0U, // VFMADDSUB132PSr 0U, // VFMADDSUB213PDYm 0U, // VFMADDSUB213PDYr 0U, // VFMADDSUB213PDZ128m 0U, // VFMADDSUB213PDZ128mb 0U, // VFMADDSUB213PDZ128mbk 0U, // VFMADDSUB213PDZ128mbkz 0U, // VFMADDSUB213PDZ128mk 0U, // VFMADDSUB213PDZ128mkz 0U, // VFMADDSUB213PDZ128r 0U, // VFMADDSUB213PDZ128rk 0U, // VFMADDSUB213PDZ128rkz 0U, // VFMADDSUB213PDZ256m 0U, // VFMADDSUB213PDZ256mb 0U, // VFMADDSUB213PDZ256mbk 0U, // VFMADDSUB213PDZ256mbkz 0U, // VFMADDSUB213PDZ256mk 0U, // VFMADDSUB213PDZ256mkz 0U, // VFMADDSUB213PDZ256r 0U, // VFMADDSUB213PDZ256rk 0U, // VFMADDSUB213PDZ256rkz 0U, // VFMADDSUB213PDZm 0U, // VFMADDSUB213PDZmb 0U, // VFMADDSUB213PDZmbk 0U, // VFMADDSUB213PDZmbkz 0U, // VFMADDSUB213PDZmk 0U, // VFMADDSUB213PDZmkz 0U, // VFMADDSUB213PDZr 0U, // VFMADDSUB213PDZrb 0U, // VFMADDSUB213PDZrbk 0U, // VFMADDSUB213PDZrbkz 0U, // VFMADDSUB213PDZrk 0U, // VFMADDSUB213PDZrkz 0U, // VFMADDSUB213PDm 0U, // VFMADDSUB213PDr 0U, // VFMADDSUB213PSYm 0U, // VFMADDSUB213PSYr 0U, // VFMADDSUB213PSZ128m 0U, // VFMADDSUB213PSZ128mb 0U, // VFMADDSUB213PSZ128mbk 0U, // VFMADDSUB213PSZ128mbkz 0U, // VFMADDSUB213PSZ128mk 0U, // VFMADDSUB213PSZ128mkz 0U, // VFMADDSUB213PSZ128r 0U, // VFMADDSUB213PSZ128rk 0U, // VFMADDSUB213PSZ128rkz 0U, // VFMADDSUB213PSZ256m 0U, // VFMADDSUB213PSZ256mb 0U, // VFMADDSUB213PSZ256mbk 0U, // VFMADDSUB213PSZ256mbkz 0U, // VFMADDSUB213PSZ256mk 0U, // VFMADDSUB213PSZ256mkz 0U, // VFMADDSUB213PSZ256r 0U, // VFMADDSUB213PSZ256rk 0U, // VFMADDSUB213PSZ256rkz 0U, // VFMADDSUB213PSZm 0U, // VFMADDSUB213PSZmb 0U, // VFMADDSUB213PSZmbk 0U, // VFMADDSUB213PSZmbkz 0U, // VFMADDSUB213PSZmk 0U, // VFMADDSUB213PSZmkz 0U, // VFMADDSUB213PSZr 0U, // VFMADDSUB213PSZrb 0U, // VFMADDSUB213PSZrbk 0U, // VFMADDSUB213PSZrbkz 0U, // VFMADDSUB213PSZrk 0U, // VFMADDSUB213PSZrkz 0U, // VFMADDSUB213PSm 0U, // VFMADDSUB213PSr 0U, // VFMADDSUB231PDYm 0U, // VFMADDSUB231PDYr 0U, // VFMADDSUB231PDZ128m 0U, // VFMADDSUB231PDZ128mb 0U, // VFMADDSUB231PDZ128mbk 0U, // VFMADDSUB231PDZ128mbkz 0U, // VFMADDSUB231PDZ128mk 0U, // VFMADDSUB231PDZ128mkz 0U, // VFMADDSUB231PDZ128r 0U, // VFMADDSUB231PDZ128rk 0U, // VFMADDSUB231PDZ128rkz 0U, // VFMADDSUB231PDZ256m 0U, // VFMADDSUB231PDZ256mb 0U, // VFMADDSUB231PDZ256mbk 0U, // VFMADDSUB231PDZ256mbkz 0U, // VFMADDSUB231PDZ256mk 0U, // VFMADDSUB231PDZ256mkz 0U, // VFMADDSUB231PDZ256r 0U, // VFMADDSUB231PDZ256rk 0U, // VFMADDSUB231PDZ256rkz 0U, // VFMADDSUB231PDZm 0U, // VFMADDSUB231PDZmb 0U, // VFMADDSUB231PDZmbk 0U, // VFMADDSUB231PDZmbkz 0U, // VFMADDSUB231PDZmk 0U, // VFMADDSUB231PDZmkz 0U, // VFMADDSUB231PDZr 0U, // VFMADDSUB231PDZrb 0U, // VFMADDSUB231PDZrbk 0U, // VFMADDSUB231PDZrbkz 0U, // VFMADDSUB231PDZrk 0U, // VFMADDSUB231PDZrkz 0U, // VFMADDSUB231PDm 0U, // VFMADDSUB231PDr 0U, // VFMADDSUB231PSYm 0U, // VFMADDSUB231PSYr 0U, // VFMADDSUB231PSZ128m 0U, // VFMADDSUB231PSZ128mb 0U, // VFMADDSUB231PSZ128mbk 0U, // VFMADDSUB231PSZ128mbkz 0U, // VFMADDSUB231PSZ128mk 0U, // VFMADDSUB231PSZ128mkz 0U, // VFMADDSUB231PSZ128r 0U, // VFMADDSUB231PSZ128rk 0U, // VFMADDSUB231PSZ128rkz 0U, // VFMADDSUB231PSZ256m 0U, // VFMADDSUB231PSZ256mb 0U, // VFMADDSUB231PSZ256mbk 0U, // VFMADDSUB231PSZ256mbkz 0U, // VFMADDSUB231PSZ256mk 0U, // VFMADDSUB231PSZ256mkz 0U, // VFMADDSUB231PSZ256r 0U, // VFMADDSUB231PSZ256rk 0U, // VFMADDSUB231PSZ256rkz 0U, // VFMADDSUB231PSZm 0U, // VFMADDSUB231PSZmb 0U, // VFMADDSUB231PSZmbk 0U, // VFMADDSUB231PSZmbkz 0U, // VFMADDSUB231PSZmk 0U, // VFMADDSUB231PSZmkz 0U, // VFMADDSUB231PSZr 0U, // VFMADDSUB231PSZrb 0U, // VFMADDSUB231PSZrbk 0U, // VFMADDSUB231PSZrbkz 0U, // VFMADDSUB231PSZrk 0U, // VFMADDSUB231PSZrkz 0U, // VFMADDSUB231PSm 0U, // VFMADDSUB231PSr 0U, // VFMADDSUBPD4Ymr 0U, // VFMADDSUBPD4Yrm 0U, // VFMADDSUBPD4Yrr 0U, // VFMADDSUBPD4Yrr_REV 0U, // VFMADDSUBPD4mr 0U, // VFMADDSUBPD4rm 0U, // VFMADDSUBPD4rr 0U, // VFMADDSUBPD4rr_REV 0U, // VFMADDSUBPS4Ymr 0U, // VFMADDSUBPS4Yrm 0U, // VFMADDSUBPS4Yrr 0U, // VFMADDSUBPS4Yrr_REV 0U, // VFMADDSUBPS4mr 0U, // VFMADDSUBPS4rm 0U, // VFMADDSUBPS4rr 0U, // VFMADDSUBPS4rr_REV 0U, // VFMSUB132PDYm 0U, // VFMSUB132PDYr 0U, // VFMSUB132PDZ128m 0U, // VFMSUB132PDZ128mb 0U, // VFMSUB132PDZ128mbk 0U, // VFMSUB132PDZ128mbkz 0U, // VFMSUB132PDZ128mk 0U, // VFMSUB132PDZ128mkz 0U, // VFMSUB132PDZ128r 0U, // VFMSUB132PDZ128rk 0U, // VFMSUB132PDZ128rkz 0U, // VFMSUB132PDZ256m 0U, // VFMSUB132PDZ256mb 0U, // VFMSUB132PDZ256mbk 0U, // VFMSUB132PDZ256mbkz 0U, // VFMSUB132PDZ256mk 0U, // VFMSUB132PDZ256mkz 0U, // VFMSUB132PDZ256r 0U, // VFMSUB132PDZ256rk 0U, // VFMSUB132PDZ256rkz 0U, // VFMSUB132PDZm 0U, // VFMSUB132PDZmb 0U, // VFMSUB132PDZmbk 0U, // VFMSUB132PDZmbkz 0U, // VFMSUB132PDZmk 0U, // VFMSUB132PDZmkz 0U, // VFMSUB132PDZr 0U, // VFMSUB132PDZrb 0U, // VFMSUB132PDZrbk 0U, // VFMSUB132PDZrbkz 0U, // VFMSUB132PDZrk 0U, // VFMSUB132PDZrkz 0U, // VFMSUB132PDm 0U, // VFMSUB132PDr 0U, // VFMSUB132PSYm 0U, // VFMSUB132PSYr 0U, // VFMSUB132PSZ128m 0U, // VFMSUB132PSZ128mb 0U, // VFMSUB132PSZ128mbk 0U, // VFMSUB132PSZ128mbkz 0U, // VFMSUB132PSZ128mk 0U, // VFMSUB132PSZ128mkz 0U, // VFMSUB132PSZ128r 0U, // VFMSUB132PSZ128rk 0U, // VFMSUB132PSZ128rkz 0U, // VFMSUB132PSZ256m 0U, // VFMSUB132PSZ256mb 0U, // VFMSUB132PSZ256mbk 0U, // VFMSUB132PSZ256mbkz 0U, // VFMSUB132PSZ256mk 0U, // VFMSUB132PSZ256mkz 0U, // VFMSUB132PSZ256r 0U, // VFMSUB132PSZ256rk 0U, // VFMSUB132PSZ256rkz 0U, // VFMSUB132PSZm 0U, // VFMSUB132PSZmb 0U, // VFMSUB132PSZmbk 0U, // VFMSUB132PSZmbkz 0U, // VFMSUB132PSZmk 0U, // VFMSUB132PSZmkz 0U, // VFMSUB132PSZr 0U, // VFMSUB132PSZrb 0U, // VFMSUB132PSZrbk 0U, // VFMSUB132PSZrbkz 0U, // VFMSUB132PSZrk 0U, // VFMSUB132PSZrkz 0U, // VFMSUB132PSm 0U, // VFMSUB132PSr 0U, // VFMSUB132SDZm 0U, // VFMSUB132SDZm_Int 0U, // VFMSUB132SDZm_Intk 0U, // VFMSUB132SDZm_Intkz 0U, // VFMSUB132SDZr 0U, // VFMSUB132SDZr_Int 0U, // VFMSUB132SDZr_Intk 0U, // VFMSUB132SDZr_Intkz 0U, // VFMSUB132SDZrb 0U, // VFMSUB132SDZrb_Int 0U, // VFMSUB132SDZrb_Intk 0U, // VFMSUB132SDZrb_Intkz 0U, // VFMSUB132SDm 0U, // VFMSUB132SDm_Int 0U, // VFMSUB132SDr 0U, // VFMSUB132SDr_Int 0U, // VFMSUB132SSZm 0U, // VFMSUB132SSZm_Int 0U, // VFMSUB132SSZm_Intk 0U, // VFMSUB132SSZm_Intkz 0U, // VFMSUB132SSZr 0U, // VFMSUB132SSZr_Int 0U, // VFMSUB132SSZr_Intk 0U, // VFMSUB132SSZr_Intkz 0U, // VFMSUB132SSZrb 0U, // VFMSUB132SSZrb_Int 0U, // VFMSUB132SSZrb_Intk 0U, // VFMSUB132SSZrb_Intkz 0U, // VFMSUB132SSm 0U, // VFMSUB132SSm_Int 0U, // VFMSUB132SSr 0U, // VFMSUB132SSr_Int 0U, // VFMSUB213PDYm 0U, // VFMSUB213PDYr 0U, // VFMSUB213PDZ128m 0U, // VFMSUB213PDZ128mb 0U, // VFMSUB213PDZ128mbk 0U, // VFMSUB213PDZ128mbkz 0U, // VFMSUB213PDZ128mk 0U, // VFMSUB213PDZ128mkz 0U, // VFMSUB213PDZ128r 0U, // VFMSUB213PDZ128rk 0U, // VFMSUB213PDZ128rkz 0U, // VFMSUB213PDZ256m 0U, // VFMSUB213PDZ256mb 0U, // VFMSUB213PDZ256mbk 0U, // VFMSUB213PDZ256mbkz 0U, // VFMSUB213PDZ256mk 0U, // VFMSUB213PDZ256mkz 0U, // VFMSUB213PDZ256r 0U, // VFMSUB213PDZ256rk 0U, // VFMSUB213PDZ256rkz 0U, // VFMSUB213PDZm 0U, // VFMSUB213PDZmb 0U, // VFMSUB213PDZmbk 0U, // VFMSUB213PDZmbkz 0U, // VFMSUB213PDZmk 0U, // VFMSUB213PDZmkz 0U, // VFMSUB213PDZr 0U, // VFMSUB213PDZrb 0U, // VFMSUB213PDZrbk 0U, // VFMSUB213PDZrbkz 0U, // VFMSUB213PDZrk 0U, // VFMSUB213PDZrkz 0U, // VFMSUB213PDm 0U, // VFMSUB213PDr 0U, // VFMSUB213PSYm 0U, // VFMSUB213PSYr 0U, // VFMSUB213PSZ128m 0U, // VFMSUB213PSZ128mb 0U, // VFMSUB213PSZ128mbk 0U, // VFMSUB213PSZ128mbkz 0U, // VFMSUB213PSZ128mk 0U, // VFMSUB213PSZ128mkz 0U, // VFMSUB213PSZ128r 0U, // VFMSUB213PSZ128rk 0U, // VFMSUB213PSZ128rkz 0U, // VFMSUB213PSZ256m 0U, // VFMSUB213PSZ256mb 0U, // VFMSUB213PSZ256mbk 0U, // VFMSUB213PSZ256mbkz 0U, // VFMSUB213PSZ256mk 0U, // VFMSUB213PSZ256mkz 0U, // VFMSUB213PSZ256r 0U, // VFMSUB213PSZ256rk 0U, // VFMSUB213PSZ256rkz 0U, // VFMSUB213PSZm 0U, // VFMSUB213PSZmb 0U, // VFMSUB213PSZmbk 0U, // VFMSUB213PSZmbkz 0U, // VFMSUB213PSZmk 0U, // VFMSUB213PSZmkz 0U, // VFMSUB213PSZr 0U, // VFMSUB213PSZrb 0U, // VFMSUB213PSZrbk 0U, // VFMSUB213PSZrbkz 0U, // VFMSUB213PSZrk 0U, // VFMSUB213PSZrkz 0U, // VFMSUB213PSm 0U, // VFMSUB213PSr 0U, // VFMSUB213SDZm 0U, // VFMSUB213SDZm_Int 0U, // VFMSUB213SDZm_Intk 0U, // VFMSUB213SDZm_Intkz 0U, // VFMSUB213SDZr 0U, // VFMSUB213SDZr_Int 0U, // VFMSUB213SDZr_Intk 0U, // VFMSUB213SDZr_Intkz 0U, // VFMSUB213SDZrb 0U, // VFMSUB213SDZrb_Int 0U, // VFMSUB213SDZrb_Intk 0U, // VFMSUB213SDZrb_Intkz 0U, // VFMSUB213SDm 0U, // VFMSUB213SDm_Int 0U, // VFMSUB213SDr 0U, // VFMSUB213SDr_Int 0U, // VFMSUB213SSZm 0U, // VFMSUB213SSZm_Int 0U, // VFMSUB213SSZm_Intk 0U, // VFMSUB213SSZm_Intkz 0U, // VFMSUB213SSZr 0U, // VFMSUB213SSZr_Int 0U, // VFMSUB213SSZr_Intk 0U, // VFMSUB213SSZr_Intkz 0U, // VFMSUB213SSZrb 0U, // VFMSUB213SSZrb_Int 0U, // VFMSUB213SSZrb_Intk 0U, // VFMSUB213SSZrb_Intkz 0U, // VFMSUB213SSm 0U, // VFMSUB213SSm_Int 0U, // VFMSUB213SSr 0U, // VFMSUB213SSr_Int 0U, // VFMSUB231PDYm 0U, // VFMSUB231PDYr 0U, // VFMSUB231PDZ128m 0U, // VFMSUB231PDZ128mb 0U, // VFMSUB231PDZ128mbk 0U, // VFMSUB231PDZ128mbkz 0U, // VFMSUB231PDZ128mk 0U, // VFMSUB231PDZ128mkz 0U, // VFMSUB231PDZ128r 0U, // VFMSUB231PDZ128rk 0U, // VFMSUB231PDZ128rkz 0U, // VFMSUB231PDZ256m 0U, // VFMSUB231PDZ256mb 0U, // VFMSUB231PDZ256mbk 0U, // VFMSUB231PDZ256mbkz 0U, // VFMSUB231PDZ256mk 0U, // VFMSUB231PDZ256mkz 0U, // VFMSUB231PDZ256r 0U, // VFMSUB231PDZ256rk 0U, // VFMSUB231PDZ256rkz 0U, // VFMSUB231PDZm 0U, // VFMSUB231PDZmb 0U, // VFMSUB231PDZmbk 0U, // VFMSUB231PDZmbkz 0U, // VFMSUB231PDZmk 0U, // VFMSUB231PDZmkz 0U, // VFMSUB231PDZr 0U, // VFMSUB231PDZrb 0U, // VFMSUB231PDZrbk 0U, // VFMSUB231PDZrbkz 0U, // VFMSUB231PDZrk 0U, // VFMSUB231PDZrkz 0U, // VFMSUB231PDm 0U, // VFMSUB231PDr 0U, // VFMSUB231PSYm 0U, // VFMSUB231PSYr 0U, // VFMSUB231PSZ128m 0U, // VFMSUB231PSZ128mb 0U, // VFMSUB231PSZ128mbk 0U, // VFMSUB231PSZ128mbkz 0U, // VFMSUB231PSZ128mk 0U, // VFMSUB231PSZ128mkz 0U, // VFMSUB231PSZ128r 0U, // VFMSUB231PSZ128rk 0U, // VFMSUB231PSZ128rkz 0U, // VFMSUB231PSZ256m 0U, // VFMSUB231PSZ256mb 0U, // VFMSUB231PSZ256mbk 0U, // VFMSUB231PSZ256mbkz 0U, // VFMSUB231PSZ256mk 0U, // VFMSUB231PSZ256mkz 0U, // VFMSUB231PSZ256r 0U, // VFMSUB231PSZ256rk 0U, // VFMSUB231PSZ256rkz 0U, // VFMSUB231PSZm 0U, // VFMSUB231PSZmb 0U, // VFMSUB231PSZmbk 0U, // VFMSUB231PSZmbkz 0U, // VFMSUB231PSZmk 0U, // VFMSUB231PSZmkz 0U, // VFMSUB231PSZr 0U, // VFMSUB231PSZrb 0U, // VFMSUB231PSZrbk 0U, // VFMSUB231PSZrbkz 0U, // VFMSUB231PSZrk 0U, // VFMSUB231PSZrkz 0U, // VFMSUB231PSm 0U, // VFMSUB231PSr 0U, // VFMSUB231SDZm 0U, // VFMSUB231SDZm_Int 0U, // VFMSUB231SDZm_Intk 0U, // VFMSUB231SDZm_Intkz 0U, // VFMSUB231SDZr 0U, // VFMSUB231SDZr_Int 0U, // VFMSUB231SDZr_Intk 0U, // VFMSUB231SDZr_Intkz 0U, // VFMSUB231SDZrb 0U, // VFMSUB231SDZrb_Int 0U, // VFMSUB231SDZrb_Intk 0U, // VFMSUB231SDZrb_Intkz 0U, // VFMSUB231SDm 0U, // VFMSUB231SDm_Int 0U, // VFMSUB231SDr 0U, // VFMSUB231SDr_Int 0U, // VFMSUB231SSZm 0U, // VFMSUB231SSZm_Int 0U, // VFMSUB231SSZm_Intk 0U, // VFMSUB231SSZm_Intkz 0U, // VFMSUB231SSZr 0U, // VFMSUB231SSZr_Int 0U, // VFMSUB231SSZr_Intk 0U, // VFMSUB231SSZr_Intkz 0U, // VFMSUB231SSZrb 0U, // VFMSUB231SSZrb_Int 0U, // VFMSUB231SSZrb_Intk 0U, // VFMSUB231SSZrb_Intkz 0U, // VFMSUB231SSm 0U, // VFMSUB231SSm_Int 0U, // VFMSUB231SSr 0U, // VFMSUB231SSr_Int 0U, // VFMSUBADD132PDYm 0U, // VFMSUBADD132PDYr 0U, // VFMSUBADD132PDZ128m 0U, // VFMSUBADD132PDZ128mb 0U, // VFMSUBADD132PDZ128mbk 0U, // VFMSUBADD132PDZ128mbkz 0U, // VFMSUBADD132PDZ128mk 0U, // VFMSUBADD132PDZ128mkz 0U, // VFMSUBADD132PDZ128r 0U, // VFMSUBADD132PDZ128rk 0U, // VFMSUBADD132PDZ128rkz 0U, // VFMSUBADD132PDZ256m 0U, // VFMSUBADD132PDZ256mb 0U, // VFMSUBADD132PDZ256mbk 0U, // VFMSUBADD132PDZ256mbkz 0U, // VFMSUBADD132PDZ256mk 0U, // VFMSUBADD132PDZ256mkz 0U, // VFMSUBADD132PDZ256r 0U, // VFMSUBADD132PDZ256rk 0U, // VFMSUBADD132PDZ256rkz 0U, // VFMSUBADD132PDZm 0U, // VFMSUBADD132PDZmb 0U, // VFMSUBADD132PDZmbk 0U, // VFMSUBADD132PDZmbkz 0U, // VFMSUBADD132PDZmk 0U, // VFMSUBADD132PDZmkz 0U, // VFMSUBADD132PDZr 0U, // VFMSUBADD132PDZrb 0U, // VFMSUBADD132PDZrbk 0U, // VFMSUBADD132PDZrbkz 0U, // VFMSUBADD132PDZrk 0U, // VFMSUBADD132PDZrkz 0U, // VFMSUBADD132PDm 0U, // VFMSUBADD132PDr 0U, // VFMSUBADD132PSYm 0U, // VFMSUBADD132PSYr 0U, // VFMSUBADD132PSZ128m 0U, // VFMSUBADD132PSZ128mb 0U, // VFMSUBADD132PSZ128mbk 0U, // VFMSUBADD132PSZ128mbkz 0U, // VFMSUBADD132PSZ128mk 0U, // VFMSUBADD132PSZ128mkz 0U, // VFMSUBADD132PSZ128r 0U, // VFMSUBADD132PSZ128rk 0U, // VFMSUBADD132PSZ128rkz 0U, // VFMSUBADD132PSZ256m 0U, // VFMSUBADD132PSZ256mb 0U, // VFMSUBADD132PSZ256mbk 0U, // VFMSUBADD132PSZ256mbkz 0U, // VFMSUBADD132PSZ256mk 0U, // VFMSUBADD132PSZ256mkz 0U, // VFMSUBADD132PSZ256r 0U, // VFMSUBADD132PSZ256rk 0U, // VFMSUBADD132PSZ256rkz 0U, // VFMSUBADD132PSZm 0U, // VFMSUBADD132PSZmb 0U, // VFMSUBADD132PSZmbk 0U, // VFMSUBADD132PSZmbkz 0U, // VFMSUBADD132PSZmk 0U, // VFMSUBADD132PSZmkz 0U, // VFMSUBADD132PSZr 0U, // VFMSUBADD132PSZrb 0U, // VFMSUBADD132PSZrbk 0U, // VFMSUBADD132PSZrbkz 0U, // VFMSUBADD132PSZrk 0U, // VFMSUBADD132PSZrkz 0U, // VFMSUBADD132PSm 0U, // VFMSUBADD132PSr 0U, // VFMSUBADD213PDYm 0U, // VFMSUBADD213PDYr 0U, // VFMSUBADD213PDZ128m 0U, // VFMSUBADD213PDZ128mb 0U, // VFMSUBADD213PDZ128mbk 0U, // VFMSUBADD213PDZ128mbkz 0U, // VFMSUBADD213PDZ128mk 0U, // VFMSUBADD213PDZ128mkz 0U, // VFMSUBADD213PDZ128r 0U, // VFMSUBADD213PDZ128rk 0U, // VFMSUBADD213PDZ128rkz 0U, // VFMSUBADD213PDZ256m 0U, // VFMSUBADD213PDZ256mb 0U, // VFMSUBADD213PDZ256mbk 0U, // VFMSUBADD213PDZ256mbkz 0U, // VFMSUBADD213PDZ256mk 0U, // VFMSUBADD213PDZ256mkz 0U, // VFMSUBADD213PDZ256r 0U, // VFMSUBADD213PDZ256rk 0U, // VFMSUBADD213PDZ256rkz 0U, // VFMSUBADD213PDZm 0U, // VFMSUBADD213PDZmb 0U, // VFMSUBADD213PDZmbk 0U, // VFMSUBADD213PDZmbkz 0U, // VFMSUBADD213PDZmk 0U, // VFMSUBADD213PDZmkz 0U, // VFMSUBADD213PDZr 0U, // VFMSUBADD213PDZrb 0U, // VFMSUBADD213PDZrbk 0U, // VFMSUBADD213PDZrbkz 0U, // VFMSUBADD213PDZrk 0U, // VFMSUBADD213PDZrkz 0U, // VFMSUBADD213PDm 0U, // VFMSUBADD213PDr 0U, // VFMSUBADD213PSYm 0U, // VFMSUBADD213PSYr 0U, // VFMSUBADD213PSZ128m 0U, // VFMSUBADD213PSZ128mb 0U, // VFMSUBADD213PSZ128mbk 0U, // VFMSUBADD213PSZ128mbkz 0U, // VFMSUBADD213PSZ128mk 0U, // VFMSUBADD213PSZ128mkz 0U, // VFMSUBADD213PSZ128r 0U, // VFMSUBADD213PSZ128rk 0U, // VFMSUBADD213PSZ128rkz 0U, // VFMSUBADD213PSZ256m 0U, // VFMSUBADD213PSZ256mb 0U, // VFMSUBADD213PSZ256mbk 0U, // VFMSUBADD213PSZ256mbkz 0U, // VFMSUBADD213PSZ256mk 0U, // VFMSUBADD213PSZ256mkz 0U, // VFMSUBADD213PSZ256r 0U, // VFMSUBADD213PSZ256rk 0U, // VFMSUBADD213PSZ256rkz 0U, // VFMSUBADD213PSZm 0U, // VFMSUBADD213PSZmb 0U, // VFMSUBADD213PSZmbk 0U, // VFMSUBADD213PSZmbkz 0U, // VFMSUBADD213PSZmk 0U, // VFMSUBADD213PSZmkz 0U, // VFMSUBADD213PSZr 0U, // VFMSUBADD213PSZrb 0U, // VFMSUBADD213PSZrbk 0U, // VFMSUBADD213PSZrbkz 0U, // VFMSUBADD213PSZrk 0U, // VFMSUBADD213PSZrkz 0U, // VFMSUBADD213PSm 0U, // VFMSUBADD213PSr 0U, // VFMSUBADD231PDYm 0U, // VFMSUBADD231PDYr 0U, // VFMSUBADD231PDZ128m 0U, // VFMSUBADD231PDZ128mb 0U, // VFMSUBADD231PDZ128mbk 0U, // VFMSUBADD231PDZ128mbkz 0U, // VFMSUBADD231PDZ128mk 0U, // VFMSUBADD231PDZ128mkz 0U, // VFMSUBADD231PDZ128r 0U, // VFMSUBADD231PDZ128rk 0U, // VFMSUBADD231PDZ128rkz 0U, // VFMSUBADD231PDZ256m 0U, // VFMSUBADD231PDZ256mb 0U, // VFMSUBADD231PDZ256mbk 0U, // VFMSUBADD231PDZ256mbkz 0U, // VFMSUBADD231PDZ256mk 0U, // VFMSUBADD231PDZ256mkz 0U, // VFMSUBADD231PDZ256r 0U, // VFMSUBADD231PDZ256rk 0U, // VFMSUBADD231PDZ256rkz 0U, // VFMSUBADD231PDZm 0U, // VFMSUBADD231PDZmb 0U, // VFMSUBADD231PDZmbk 0U, // VFMSUBADD231PDZmbkz 0U, // VFMSUBADD231PDZmk 0U, // VFMSUBADD231PDZmkz 0U, // VFMSUBADD231PDZr 0U, // VFMSUBADD231PDZrb 0U, // VFMSUBADD231PDZrbk 0U, // VFMSUBADD231PDZrbkz 0U, // VFMSUBADD231PDZrk 0U, // VFMSUBADD231PDZrkz 0U, // VFMSUBADD231PDm 0U, // VFMSUBADD231PDr 0U, // VFMSUBADD231PSYm 0U, // VFMSUBADD231PSYr 0U, // VFMSUBADD231PSZ128m 0U, // VFMSUBADD231PSZ128mb 0U, // VFMSUBADD231PSZ128mbk 0U, // VFMSUBADD231PSZ128mbkz 0U, // VFMSUBADD231PSZ128mk 0U, // VFMSUBADD231PSZ128mkz 0U, // VFMSUBADD231PSZ128r 0U, // VFMSUBADD231PSZ128rk 0U, // VFMSUBADD231PSZ128rkz 0U, // VFMSUBADD231PSZ256m 0U, // VFMSUBADD231PSZ256mb 0U, // VFMSUBADD231PSZ256mbk 0U, // VFMSUBADD231PSZ256mbkz 0U, // VFMSUBADD231PSZ256mk 0U, // VFMSUBADD231PSZ256mkz 0U, // VFMSUBADD231PSZ256r 0U, // VFMSUBADD231PSZ256rk 0U, // VFMSUBADD231PSZ256rkz 0U, // VFMSUBADD231PSZm 0U, // VFMSUBADD231PSZmb 0U, // VFMSUBADD231PSZmbk 0U, // VFMSUBADD231PSZmbkz 0U, // VFMSUBADD231PSZmk 0U, // VFMSUBADD231PSZmkz 0U, // VFMSUBADD231PSZr 0U, // VFMSUBADD231PSZrb 0U, // VFMSUBADD231PSZrbk 0U, // VFMSUBADD231PSZrbkz 0U, // VFMSUBADD231PSZrk 0U, // VFMSUBADD231PSZrkz 0U, // VFMSUBADD231PSm 0U, // VFMSUBADD231PSr 0U, // VFMSUBADDPD4Ymr 0U, // VFMSUBADDPD4Yrm 0U, // VFMSUBADDPD4Yrr 0U, // VFMSUBADDPD4Yrr_REV 0U, // VFMSUBADDPD4mr 0U, // VFMSUBADDPD4rm 0U, // VFMSUBADDPD4rr 0U, // VFMSUBADDPD4rr_REV 0U, // VFMSUBADDPS4Ymr 0U, // VFMSUBADDPS4Yrm 0U, // VFMSUBADDPS4Yrr 0U, // VFMSUBADDPS4Yrr_REV 0U, // VFMSUBADDPS4mr 0U, // VFMSUBADDPS4rm 0U, // VFMSUBADDPS4rr 0U, // VFMSUBADDPS4rr_REV 0U, // VFMSUBPD4Ymr 0U, // VFMSUBPD4Yrm 0U, // VFMSUBPD4Yrr 0U, // VFMSUBPD4Yrr_REV 0U, // VFMSUBPD4mr 0U, // VFMSUBPD4rm 0U, // VFMSUBPD4rr 0U, // VFMSUBPD4rr_REV 0U, // VFMSUBPS4Ymr 0U, // VFMSUBPS4Yrm 0U, // VFMSUBPS4Yrr 0U, // VFMSUBPS4Yrr_REV 0U, // VFMSUBPS4mr 0U, // VFMSUBPS4rm 0U, // VFMSUBPS4rr 0U, // VFMSUBPS4rr_REV 0U, // VFMSUBSD4mr 0U, // VFMSUBSD4mr_Int 0U, // VFMSUBSD4rm 0U, // VFMSUBSD4rm_Int 0U, // VFMSUBSD4rr 0U, // VFMSUBSD4rr_Int 0U, // VFMSUBSD4rr_Int_REV 0U, // VFMSUBSD4rr_REV 0U, // VFMSUBSS4mr 0U, // VFMSUBSS4mr_Int 0U, // VFMSUBSS4rm 0U, // VFMSUBSS4rm_Int 0U, // VFMSUBSS4rr 0U, // VFMSUBSS4rr_Int 0U, // VFMSUBSS4rr_Int_REV 0U, // VFMSUBSS4rr_REV 0U, // VFNMADD132PDYm 0U, // VFNMADD132PDYr 0U, // VFNMADD132PDZ128m 0U, // VFNMADD132PDZ128mb 0U, // VFNMADD132PDZ128mbk 0U, // VFNMADD132PDZ128mbkz 0U, // VFNMADD132PDZ128mk 0U, // VFNMADD132PDZ128mkz 0U, // VFNMADD132PDZ128r 0U, // VFNMADD132PDZ128rk 0U, // VFNMADD132PDZ128rkz 0U, // VFNMADD132PDZ256m 0U, // VFNMADD132PDZ256mb 0U, // VFNMADD132PDZ256mbk 0U, // VFNMADD132PDZ256mbkz 0U, // VFNMADD132PDZ256mk 0U, // VFNMADD132PDZ256mkz 0U, // VFNMADD132PDZ256r 0U, // VFNMADD132PDZ256rk 0U, // VFNMADD132PDZ256rkz 0U, // VFNMADD132PDZm 0U, // VFNMADD132PDZmb 0U, // VFNMADD132PDZmbk 0U, // VFNMADD132PDZmbkz 0U, // VFNMADD132PDZmk 0U, // VFNMADD132PDZmkz 0U, // VFNMADD132PDZr 0U, // VFNMADD132PDZrb 0U, // VFNMADD132PDZrbk 0U, // VFNMADD132PDZrbkz 0U, // VFNMADD132PDZrk 0U, // VFNMADD132PDZrkz 0U, // VFNMADD132PDm 0U, // VFNMADD132PDr 0U, // VFNMADD132PSYm 0U, // VFNMADD132PSYr 0U, // VFNMADD132PSZ128m 0U, // VFNMADD132PSZ128mb 0U, // VFNMADD132PSZ128mbk 0U, // VFNMADD132PSZ128mbkz 0U, // VFNMADD132PSZ128mk 0U, // VFNMADD132PSZ128mkz 0U, // VFNMADD132PSZ128r 0U, // VFNMADD132PSZ128rk 0U, // VFNMADD132PSZ128rkz 0U, // VFNMADD132PSZ256m 0U, // VFNMADD132PSZ256mb 0U, // VFNMADD132PSZ256mbk 0U, // VFNMADD132PSZ256mbkz 0U, // VFNMADD132PSZ256mk 0U, // VFNMADD132PSZ256mkz 0U, // VFNMADD132PSZ256r 0U, // VFNMADD132PSZ256rk 0U, // VFNMADD132PSZ256rkz 0U, // VFNMADD132PSZm 0U, // VFNMADD132PSZmb 0U, // VFNMADD132PSZmbk 0U, // VFNMADD132PSZmbkz 0U, // VFNMADD132PSZmk 0U, // VFNMADD132PSZmkz 0U, // VFNMADD132PSZr 0U, // VFNMADD132PSZrb 0U, // VFNMADD132PSZrbk 0U, // VFNMADD132PSZrbkz 0U, // VFNMADD132PSZrk 0U, // VFNMADD132PSZrkz 0U, // VFNMADD132PSm 0U, // VFNMADD132PSr 0U, // VFNMADD132SDZm 0U, // VFNMADD132SDZm_Int 0U, // VFNMADD132SDZm_Intk 0U, // VFNMADD132SDZm_Intkz 0U, // VFNMADD132SDZr 0U, // VFNMADD132SDZr_Int 0U, // VFNMADD132SDZr_Intk 0U, // VFNMADD132SDZr_Intkz 0U, // VFNMADD132SDZrb 0U, // VFNMADD132SDZrb_Int 0U, // VFNMADD132SDZrb_Intk 0U, // VFNMADD132SDZrb_Intkz 0U, // VFNMADD132SDm 0U, // VFNMADD132SDm_Int 0U, // VFNMADD132SDr 0U, // VFNMADD132SDr_Int 0U, // VFNMADD132SSZm 0U, // VFNMADD132SSZm_Int 0U, // VFNMADD132SSZm_Intk 0U, // VFNMADD132SSZm_Intkz 0U, // VFNMADD132SSZr 0U, // VFNMADD132SSZr_Int 0U, // VFNMADD132SSZr_Intk 0U, // VFNMADD132SSZr_Intkz 0U, // VFNMADD132SSZrb 0U, // VFNMADD132SSZrb_Int 0U, // VFNMADD132SSZrb_Intk 0U, // VFNMADD132SSZrb_Intkz 0U, // VFNMADD132SSm 0U, // VFNMADD132SSm_Int 0U, // VFNMADD132SSr 0U, // VFNMADD132SSr_Int 0U, // VFNMADD213PDYm 0U, // VFNMADD213PDYr 0U, // VFNMADD213PDZ128m 0U, // VFNMADD213PDZ128mb 0U, // VFNMADD213PDZ128mbk 0U, // VFNMADD213PDZ128mbkz 0U, // VFNMADD213PDZ128mk 0U, // VFNMADD213PDZ128mkz 0U, // VFNMADD213PDZ128r 0U, // VFNMADD213PDZ128rk 0U, // VFNMADD213PDZ128rkz 0U, // VFNMADD213PDZ256m 0U, // VFNMADD213PDZ256mb 0U, // VFNMADD213PDZ256mbk 0U, // VFNMADD213PDZ256mbkz 0U, // VFNMADD213PDZ256mk 0U, // VFNMADD213PDZ256mkz 0U, // VFNMADD213PDZ256r 0U, // VFNMADD213PDZ256rk 0U, // VFNMADD213PDZ256rkz 0U, // VFNMADD213PDZm 0U, // VFNMADD213PDZmb 0U, // VFNMADD213PDZmbk 0U, // VFNMADD213PDZmbkz 0U, // VFNMADD213PDZmk 0U, // VFNMADD213PDZmkz 0U, // VFNMADD213PDZr 0U, // VFNMADD213PDZrb 0U, // VFNMADD213PDZrbk 0U, // VFNMADD213PDZrbkz 0U, // VFNMADD213PDZrk 0U, // VFNMADD213PDZrkz 0U, // VFNMADD213PDm 0U, // VFNMADD213PDr 0U, // VFNMADD213PSYm 0U, // VFNMADD213PSYr 0U, // VFNMADD213PSZ128m 0U, // VFNMADD213PSZ128mb 0U, // VFNMADD213PSZ128mbk 0U, // VFNMADD213PSZ128mbkz 0U, // VFNMADD213PSZ128mk 0U, // VFNMADD213PSZ128mkz 0U, // VFNMADD213PSZ128r 0U, // VFNMADD213PSZ128rk 0U, // VFNMADD213PSZ128rkz 0U, // VFNMADD213PSZ256m 0U, // VFNMADD213PSZ256mb 0U, // VFNMADD213PSZ256mbk 0U, // VFNMADD213PSZ256mbkz 0U, // VFNMADD213PSZ256mk 0U, // VFNMADD213PSZ256mkz 0U, // VFNMADD213PSZ256r 0U, // VFNMADD213PSZ256rk 0U, // VFNMADD213PSZ256rkz 0U, // VFNMADD213PSZm 0U, // VFNMADD213PSZmb 0U, // VFNMADD213PSZmbk 0U, // VFNMADD213PSZmbkz 0U, // VFNMADD213PSZmk 0U, // VFNMADD213PSZmkz 0U, // VFNMADD213PSZr 0U, // VFNMADD213PSZrb 0U, // VFNMADD213PSZrbk 0U, // VFNMADD213PSZrbkz 0U, // VFNMADD213PSZrk 0U, // VFNMADD213PSZrkz 0U, // VFNMADD213PSm 0U, // VFNMADD213PSr 0U, // VFNMADD213SDZm 0U, // VFNMADD213SDZm_Int 0U, // VFNMADD213SDZm_Intk 0U, // VFNMADD213SDZm_Intkz 0U, // VFNMADD213SDZr 0U, // VFNMADD213SDZr_Int 0U, // VFNMADD213SDZr_Intk 0U, // VFNMADD213SDZr_Intkz 0U, // VFNMADD213SDZrb 0U, // VFNMADD213SDZrb_Int 0U, // VFNMADD213SDZrb_Intk 0U, // VFNMADD213SDZrb_Intkz 0U, // VFNMADD213SDm 0U, // VFNMADD213SDm_Int 0U, // VFNMADD213SDr 0U, // VFNMADD213SDr_Int 0U, // VFNMADD213SSZm 0U, // VFNMADD213SSZm_Int 0U, // VFNMADD213SSZm_Intk 0U, // VFNMADD213SSZm_Intkz 0U, // VFNMADD213SSZr 0U, // VFNMADD213SSZr_Int 0U, // VFNMADD213SSZr_Intk 0U, // VFNMADD213SSZr_Intkz 0U, // VFNMADD213SSZrb 0U, // VFNMADD213SSZrb_Int 0U, // VFNMADD213SSZrb_Intk 0U, // VFNMADD213SSZrb_Intkz 0U, // VFNMADD213SSm 0U, // VFNMADD213SSm_Int 0U, // VFNMADD213SSr 0U, // VFNMADD213SSr_Int 0U, // VFNMADD231PDYm 0U, // VFNMADD231PDYr 0U, // VFNMADD231PDZ128m 0U, // VFNMADD231PDZ128mb 0U, // VFNMADD231PDZ128mbk 0U, // VFNMADD231PDZ128mbkz 0U, // VFNMADD231PDZ128mk 0U, // VFNMADD231PDZ128mkz 0U, // VFNMADD231PDZ128r 0U, // VFNMADD231PDZ128rk 0U, // VFNMADD231PDZ128rkz 0U, // VFNMADD231PDZ256m 0U, // VFNMADD231PDZ256mb 0U, // VFNMADD231PDZ256mbk 0U, // VFNMADD231PDZ256mbkz 0U, // VFNMADD231PDZ256mk 0U, // VFNMADD231PDZ256mkz 0U, // VFNMADD231PDZ256r 0U, // VFNMADD231PDZ256rk 0U, // VFNMADD231PDZ256rkz 0U, // VFNMADD231PDZm 0U, // VFNMADD231PDZmb 0U, // VFNMADD231PDZmbk 0U, // VFNMADD231PDZmbkz 0U, // VFNMADD231PDZmk 0U, // VFNMADD231PDZmkz 0U, // VFNMADD231PDZr 0U, // VFNMADD231PDZrb 0U, // VFNMADD231PDZrbk 0U, // VFNMADD231PDZrbkz 0U, // VFNMADD231PDZrk 0U, // VFNMADD231PDZrkz 0U, // VFNMADD231PDm 0U, // VFNMADD231PDr 0U, // VFNMADD231PSYm 0U, // VFNMADD231PSYr 0U, // VFNMADD231PSZ128m 0U, // VFNMADD231PSZ128mb 0U, // VFNMADD231PSZ128mbk 0U, // VFNMADD231PSZ128mbkz 0U, // VFNMADD231PSZ128mk 0U, // VFNMADD231PSZ128mkz 0U, // VFNMADD231PSZ128r 0U, // VFNMADD231PSZ128rk 0U, // VFNMADD231PSZ128rkz 0U, // VFNMADD231PSZ256m 0U, // VFNMADD231PSZ256mb 0U, // VFNMADD231PSZ256mbk 0U, // VFNMADD231PSZ256mbkz 0U, // VFNMADD231PSZ256mk 0U, // VFNMADD231PSZ256mkz 0U, // VFNMADD231PSZ256r 0U, // VFNMADD231PSZ256rk 0U, // VFNMADD231PSZ256rkz 0U, // VFNMADD231PSZm 0U, // VFNMADD231PSZmb 0U, // VFNMADD231PSZmbk 0U, // VFNMADD231PSZmbkz 0U, // VFNMADD231PSZmk 0U, // VFNMADD231PSZmkz 0U, // VFNMADD231PSZr 0U, // VFNMADD231PSZrb 0U, // VFNMADD231PSZrbk 0U, // VFNMADD231PSZrbkz 0U, // VFNMADD231PSZrk 0U, // VFNMADD231PSZrkz 0U, // VFNMADD231PSm 0U, // VFNMADD231PSr 0U, // VFNMADD231SDZm 0U, // VFNMADD231SDZm_Int 0U, // VFNMADD231SDZm_Intk 0U, // VFNMADD231SDZm_Intkz 0U, // VFNMADD231SDZr 0U, // VFNMADD231SDZr_Int 0U, // VFNMADD231SDZr_Intk 0U, // VFNMADD231SDZr_Intkz 0U, // VFNMADD231SDZrb 0U, // VFNMADD231SDZrb_Int 0U, // VFNMADD231SDZrb_Intk 0U, // VFNMADD231SDZrb_Intkz 0U, // VFNMADD231SDm 0U, // VFNMADD231SDm_Int 0U, // VFNMADD231SDr 0U, // VFNMADD231SDr_Int 0U, // VFNMADD231SSZm 0U, // VFNMADD231SSZm_Int 0U, // VFNMADD231SSZm_Intk 0U, // VFNMADD231SSZm_Intkz 0U, // VFNMADD231SSZr 0U, // VFNMADD231SSZr_Int 0U, // VFNMADD231SSZr_Intk 0U, // VFNMADD231SSZr_Intkz 0U, // VFNMADD231SSZrb 0U, // VFNMADD231SSZrb_Int 0U, // VFNMADD231SSZrb_Intk 0U, // VFNMADD231SSZrb_Intkz 0U, // VFNMADD231SSm 0U, // VFNMADD231SSm_Int 0U, // VFNMADD231SSr 0U, // VFNMADD231SSr_Int 0U, // VFNMADDPD4Ymr 0U, // VFNMADDPD4Yrm 0U, // VFNMADDPD4Yrr 0U, // VFNMADDPD4Yrr_REV 0U, // VFNMADDPD4mr 0U, // VFNMADDPD4rm 0U, // VFNMADDPD4rr 0U, // VFNMADDPD4rr_REV 0U, // VFNMADDPS4Ymr 0U, // VFNMADDPS4Yrm 0U, // VFNMADDPS4Yrr 0U, // VFNMADDPS4Yrr_REV 0U, // VFNMADDPS4mr 0U, // VFNMADDPS4rm 0U, // VFNMADDPS4rr 0U, // VFNMADDPS4rr_REV 0U, // VFNMADDSD4mr 0U, // VFNMADDSD4mr_Int 0U, // VFNMADDSD4rm 0U, // VFNMADDSD4rm_Int 0U, // VFNMADDSD4rr 0U, // VFNMADDSD4rr_Int 0U, // VFNMADDSD4rr_Int_REV 0U, // VFNMADDSD4rr_REV 0U, // VFNMADDSS4mr 0U, // VFNMADDSS4mr_Int 0U, // VFNMADDSS4rm 0U, // VFNMADDSS4rm_Int 0U, // VFNMADDSS4rr 0U, // VFNMADDSS4rr_Int 0U, // VFNMADDSS4rr_Int_REV 0U, // VFNMADDSS4rr_REV 0U, // VFNMSUB132PDYm 0U, // VFNMSUB132PDYr 0U, // VFNMSUB132PDZ128m 0U, // VFNMSUB132PDZ128mb 0U, // VFNMSUB132PDZ128mbk 0U, // VFNMSUB132PDZ128mbkz 0U, // VFNMSUB132PDZ128mk 0U, // VFNMSUB132PDZ128mkz 0U, // VFNMSUB132PDZ128r 0U, // VFNMSUB132PDZ128rk 0U, // VFNMSUB132PDZ128rkz 0U, // VFNMSUB132PDZ256m 0U, // VFNMSUB132PDZ256mb 0U, // VFNMSUB132PDZ256mbk 0U, // VFNMSUB132PDZ256mbkz 0U, // VFNMSUB132PDZ256mk 0U, // VFNMSUB132PDZ256mkz 0U, // VFNMSUB132PDZ256r 0U, // VFNMSUB132PDZ256rk 0U, // VFNMSUB132PDZ256rkz 0U, // VFNMSUB132PDZm 0U, // VFNMSUB132PDZmb 0U, // VFNMSUB132PDZmbk 0U, // VFNMSUB132PDZmbkz 0U, // VFNMSUB132PDZmk 0U, // VFNMSUB132PDZmkz 0U, // VFNMSUB132PDZr 0U, // VFNMSUB132PDZrb 0U, // VFNMSUB132PDZrbk 0U, // VFNMSUB132PDZrbkz 0U, // VFNMSUB132PDZrk 0U, // VFNMSUB132PDZrkz 0U, // VFNMSUB132PDm 0U, // VFNMSUB132PDr 0U, // VFNMSUB132PSYm 0U, // VFNMSUB132PSYr 0U, // VFNMSUB132PSZ128m 0U, // VFNMSUB132PSZ128mb 0U, // VFNMSUB132PSZ128mbk 0U, // VFNMSUB132PSZ128mbkz 0U, // VFNMSUB132PSZ128mk 0U, // VFNMSUB132PSZ128mkz 0U, // VFNMSUB132PSZ128r 0U, // VFNMSUB132PSZ128rk 0U, // VFNMSUB132PSZ128rkz 0U, // VFNMSUB132PSZ256m 0U, // VFNMSUB132PSZ256mb 0U, // VFNMSUB132PSZ256mbk 0U, // VFNMSUB132PSZ256mbkz 0U, // VFNMSUB132PSZ256mk 0U, // VFNMSUB132PSZ256mkz 0U, // VFNMSUB132PSZ256r 0U, // VFNMSUB132PSZ256rk 0U, // VFNMSUB132PSZ256rkz 0U, // VFNMSUB132PSZm 0U, // VFNMSUB132PSZmb 0U, // VFNMSUB132PSZmbk 0U, // VFNMSUB132PSZmbkz 0U, // VFNMSUB132PSZmk 0U, // VFNMSUB132PSZmkz 0U, // VFNMSUB132PSZr 0U, // VFNMSUB132PSZrb 0U, // VFNMSUB132PSZrbk 0U, // VFNMSUB132PSZrbkz 0U, // VFNMSUB132PSZrk 0U, // VFNMSUB132PSZrkz 0U, // VFNMSUB132PSm 0U, // VFNMSUB132PSr 0U, // VFNMSUB132SDZm 0U, // VFNMSUB132SDZm_Int 0U, // VFNMSUB132SDZm_Intk 0U, // VFNMSUB132SDZm_Intkz 0U, // VFNMSUB132SDZr 0U, // VFNMSUB132SDZr_Int 0U, // VFNMSUB132SDZr_Intk 0U, // VFNMSUB132SDZr_Intkz 0U, // VFNMSUB132SDZrb 0U, // VFNMSUB132SDZrb_Int 0U, // VFNMSUB132SDZrb_Intk 0U, // VFNMSUB132SDZrb_Intkz 0U, // VFNMSUB132SDm 0U, // VFNMSUB132SDm_Int 0U, // VFNMSUB132SDr 0U, // VFNMSUB132SDr_Int 0U, // VFNMSUB132SSZm 0U, // VFNMSUB132SSZm_Int 0U, // VFNMSUB132SSZm_Intk 0U, // VFNMSUB132SSZm_Intkz 0U, // VFNMSUB132SSZr 0U, // VFNMSUB132SSZr_Int 0U, // VFNMSUB132SSZr_Intk 0U, // VFNMSUB132SSZr_Intkz 0U, // VFNMSUB132SSZrb 0U, // VFNMSUB132SSZrb_Int 0U, // VFNMSUB132SSZrb_Intk 0U, // VFNMSUB132SSZrb_Intkz 0U, // VFNMSUB132SSm 0U, // VFNMSUB132SSm_Int 0U, // VFNMSUB132SSr 0U, // VFNMSUB132SSr_Int 0U, // VFNMSUB213PDYm 0U, // VFNMSUB213PDYr 0U, // VFNMSUB213PDZ128m 0U, // VFNMSUB213PDZ128mb 0U, // VFNMSUB213PDZ128mbk 0U, // VFNMSUB213PDZ128mbkz 0U, // VFNMSUB213PDZ128mk 0U, // VFNMSUB213PDZ128mkz 0U, // VFNMSUB213PDZ128r 0U, // VFNMSUB213PDZ128rk 0U, // VFNMSUB213PDZ128rkz 0U, // VFNMSUB213PDZ256m 0U, // VFNMSUB213PDZ256mb 0U, // VFNMSUB213PDZ256mbk 0U, // VFNMSUB213PDZ256mbkz 0U, // VFNMSUB213PDZ256mk 0U, // VFNMSUB213PDZ256mkz 0U, // VFNMSUB213PDZ256r 0U, // VFNMSUB213PDZ256rk 0U, // VFNMSUB213PDZ256rkz 0U, // VFNMSUB213PDZm 0U, // VFNMSUB213PDZmb 0U, // VFNMSUB213PDZmbk 0U, // VFNMSUB213PDZmbkz 0U, // VFNMSUB213PDZmk 0U, // VFNMSUB213PDZmkz 0U, // VFNMSUB213PDZr 0U, // VFNMSUB213PDZrb 0U, // VFNMSUB213PDZrbk 0U, // VFNMSUB213PDZrbkz 0U, // VFNMSUB213PDZrk 0U, // VFNMSUB213PDZrkz 0U, // VFNMSUB213PDm 0U, // VFNMSUB213PDr 0U, // VFNMSUB213PSYm 0U, // VFNMSUB213PSYr 0U, // VFNMSUB213PSZ128m 0U, // VFNMSUB213PSZ128mb 0U, // VFNMSUB213PSZ128mbk 0U, // VFNMSUB213PSZ128mbkz 0U, // VFNMSUB213PSZ128mk 0U, // VFNMSUB213PSZ128mkz 0U, // VFNMSUB213PSZ128r 0U, // VFNMSUB213PSZ128rk 0U, // VFNMSUB213PSZ128rkz 0U, // VFNMSUB213PSZ256m 0U, // VFNMSUB213PSZ256mb 0U, // VFNMSUB213PSZ256mbk 0U, // VFNMSUB213PSZ256mbkz 0U, // VFNMSUB213PSZ256mk 0U, // VFNMSUB213PSZ256mkz 0U, // VFNMSUB213PSZ256r 0U, // VFNMSUB213PSZ256rk 0U, // VFNMSUB213PSZ256rkz 0U, // VFNMSUB213PSZm 0U, // VFNMSUB213PSZmb 0U, // VFNMSUB213PSZmbk 0U, // VFNMSUB213PSZmbkz 0U, // VFNMSUB213PSZmk 0U, // VFNMSUB213PSZmkz 0U, // VFNMSUB213PSZr 0U, // VFNMSUB213PSZrb 0U, // VFNMSUB213PSZrbk 0U, // VFNMSUB213PSZrbkz 0U, // VFNMSUB213PSZrk 0U, // VFNMSUB213PSZrkz 0U, // VFNMSUB213PSm 0U, // VFNMSUB213PSr 0U, // VFNMSUB213SDZm 0U, // VFNMSUB213SDZm_Int 0U, // VFNMSUB213SDZm_Intk 0U, // VFNMSUB213SDZm_Intkz 0U, // VFNMSUB213SDZr 0U, // VFNMSUB213SDZr_Int 0U, // VFNMSUB213SDZr_Intk 0U, // VFNMSUB213SDZr_Intkz 0U, // VFNMSUB213SDZrb 0U, // VFNMSUB213SDZrb_Int 0U, // VFNMSUB213SDZrb_Intk 0U, // VFNMSUB213SDZrb_Intkz 0U, // VFNMSUB213SDm 0U, // VFNMSUB213SDm_Int 0U, // VFNMSUB213SDr 0U, // VFNMSUB213SDr_Int 0U, // VFNMSUB213SSZm 0U, // VFNMSUB213SSZm_Int 0U, // VFNMSUB213SSZm_Intk 0U, // VFNMSUB213SSZm_Intkz 0U, // VFNMSUB213SSZr 0U, // VFNMSUB213SSZr_Int 0U, // VFNMSUB213SSZr_Intk 0U, // VFNMSUB213SSZr_Intkz 0U, // VFNMSUB213SSZrb 0U, // VFNMSUB213SSZrb_Int 0U, // VFNMSUB213SSZrb_Intk 0U, // VFNMSUB213SSZrb_Intkz 0U, // VFNMSUB213SSm 0U, // VFNMSUB213SSm_Int 0U, // VFNMSUB213SSr 0U, // VFNMSUB213SSr_Int 0U, // VFNMSUB231PDYm 0U, // VFNMSUB231PDYr 0U, // VFNMSUB231PDZ128m 0U, // VFNMSUB231PDZ128mb 0U, // VFNMSUB231PDZ128mbk 0U, // VFNMSUB231PDZ128mbkz 0U, // VFNMSUB231PDZ128mk 0U, // VFNMSUB231PDZ128mkz 0U, // VFNMSUB231PDZ128r 0U, // VFNMSUB231PDZ128rk 0U, // VFNMSUB231PDZ128rkz 0U, // VFNMSUB231PDZ256m 0U, // VFNMSUB231PDZ256mb 0U, // VFNMSUB231PDZ256mbk 0U, // VFNMSUB231PDZ256mbkz 0U, // VFNMSUB231PDZ256mk 0U, // VFNMSUB231PDZ256mkz 0U, // VFNMSUB231PDZ256r 0U, // VFNMSUB231PDZ256rk 0U, // VFNMSUB231PDZ256rkz 0U, // VFNMSUB231PDZm 0U, // VFNMSUB231PDZmb 0U, // VFNMSUB231PDZmbk 0U, // VFNMSUB231PDZmbkz 0U, // VFNMSUB231PDZmk 0U, // VFNMSUB231PDZmkz 0U, // VFNMSUB231PDZr 0U, // VFNMSUB231PDZrb 0U, // VFNMSUB231PDZrbk 0U, // VFNMSUB231PDZrbkz 0U, // VFNMSUB231PDZrk 0U, // VFNMSUB231PDZrkz 0U, // VFNMSUB231PDm 0U, // VFNMSUB231PDr 0U, // VFNMSUB231PSYm 0U, // VFNMSUB231PSYr 0U, // VFNMSUB231PSZ128m 0U, // VFNMSUB231PSZ128mb 0U, // VFNMSUB231PSZ128mbk 0U, // VFNMSUB231PSZ128mbkz 0U, // VFNMSUB231PSZ128mk 0U, // VFNMSUB231PSZ128mkz 0U, // VFNMSUB231PSZ128r 0U, // VFNMSUB231PSZ128rk 0U, // VFNMSUB231PSZ128rkz 0U, // VFNMSUB231PSZ256m 0U, // VFNMSUB231PSZ256mb 0U, // VFNMSUB231PSZ256mbk 0U, // VFNMSUB231PSZ256mbkz 0U, // VFNMSUB231PSZ256mk 0U, // VFNMSUB231PSZ256mkz 0U, // VFNMSUB231PSZ256r 0U, // VFNMSUB231PSZ256rk 0U, // VFNMSUB231PSZ256rkz 0U, // VFNMSUB231PSZm 0U, // VFNMSUB231PSZmb 0U, // VFNMSUB231PSZmbk 0U, // VFNMSUB231PSZmbkz 0U, // VFNMSUB231PSZmk 0U, // VFNMSUB231PSZmkz 0U, // VFNMSUB231PSZr 0U, // VFNMSUB231PSZrb 0U, // VFNMSUB231PSZrbk 0U, // VFNMSUB231PSZrbkz 0U, // VFNMSUB231PSZrk 0U, // VFNMSUB231PSZrkz 0U, // VFNMSUB231PSm 0U, // VFNMSUB231PSr 0U, // VFNMSUB231SDZm 0U, // VFNMSUB231SDZm_Int 0U, // VFNMSUB231SDZm_Intk 0U, // VFNMSUB231SDZm_Intkz 0U, // VFNMSUB231SDZr 0U, // VFNMSUB231SDZr_Int 0U, // VFNMSUB231SDZr_Intk 0U, // VFNMSUB231SDZr_Intkz 0U, // VFNMSUB231SDZrb 0U, // VFNMSUB231SDZrb_Int 0U, // VFNMSUB231SDZrb_Intk 0U, // VFNMSUB231SDZrb_Intkz 0U, // VFNMSUB231SDm 0U, // VFNMSUB231SDm_Int 0U, // VFNMSUB231SDr 0U, // VFNMSUB231SDr_Int 0U, // VFNMSUB231SSZm 0U, // VFNMSUB231SSZm_Int 0U, // VFNMSUB231SSZm_Intk 0U, // VFNMSUB231SSZm_Intkz 0U, // VFNMSUB231SSZr 0U, // VFNMSUB231SSZr_Int 0U, // VFNMSUB231SSZr_Intk 0U, // VFNMSUB231SSZr_Intkz 0U, // VFNMSUB231SSZrb 0U, // VFNMSUB231SSZrb_Int 0U, // VFNMSUB231SSZrb_Intk 0U, // VFNMSUB231SSZrb_Intkz 0U, // VFNMSUB231SSm 0U, // VFNMSUB231SSm_Int 0U, // VFNMSUB231SSr 0U, // VFNMSUB231SSr_Int 0U, // VFNMSUBPD4Ymr 0U, // VFNMSUBPD4Yrm 0U, // VFNMSUBPD4Yrr 0U, // VFNMSUBPD4Yrr_REV 0U, // VFNMSUBPD4mr 0U, // VFNMSUBPD4rm 0U, // VFNMSUBPD4rr 0U, // VFNMSUBPD4rr_REV 0U, // VFNMSUBPS4Ymr 0U, // VFNMSUBPS4Yrm 0U, // VFNMSUBPS4Yrr 0U, // VFNMSUBPS4Yrr_REV 0U, // VFNMSUBPS4mr 0U, // VFNMSUBPS4rm 0U, // VFNMSUBPS4rr 0U, // VFNMSUBPS4rr_REV 0U, // VFNMSUBSD4mr 0U, // VFNMSUBSD4mr_Int 0U, // VFNMSUBSD4rm 0U, // VFNMSUBSD4rm_Int 0U, // VFNMSUBSD4rr 0U, // VFNMSUBSD4rr_Int 0U, // VFNMSUBSD4rr_Int_REV 0U, // VFNMSUBSD4rr_REV 0U, // VFNMSUBSS4mr 0U, // VFNMSUBSS4mr_Int 0U, // VFNMSUBSS4rm 0U, // VFNMSUBSS4rm_Int 0U, // VFNMSUBSS4rr 0U, // VFNMSUBSS4rr_Int 0U, // VFNMSUBSS4rr_Int_REV 0U, // VFNMSUBSS4rr_REV 0U, // VFPCLASSPDZ128rm 0U, // VFPCLASSPDZ128rmb 0U, // VFPCLASSPDZ128rmbk 0U, // VFPCLASSPDZ128rmk 0U, // VFPCLASSPDZ128rr 0U, // VFPCLASSPDZ128rrk 0U, // VFPCLASSPDZ256rm 0U, // VFPCLASSPDZ256rmb 0U, // VFPCLASSPDZ256rmbk 0U, // VFPCLASSPDZ256rmk 0U, // VFPCLASSPDZ256rr 0U, // VFPCLASSPDZ256rrk 0U, // VFPCLASSPDZrm 0U, // VFPCLASSPDZrmb 0U, // VFPCLASSPDZrmbk 0U, // VFPCLASSPDZrmk 0U, // VFPCLASSPDZrr 0U, // VFPCLASSPDZrrk 0U, // VFPCLASSPSZ128rm 0U, // VFPCLASSPSZ128rmb 0U, // VFPCLASSPSZ128rmbk 0U, // VFPCLASSPSZ128rmk 0U, // VFPCLASSPSZ128rr 0U, // VFPCLASSPSZ128rrk 0U, // VFPCLASSPSZ256rm 0U, // VFPCLASSPSZ256rmb 0U, // VFPCLASSPSZ256rmbk 0U, // VFPCLASSPSZ256rmk 0U, // VFPCLASSPSZ256rr 0U, // VFPCLASSPSZ256rrk 0U, // VFPCLASSPSZrm 0U, // VFPCLASSPSZrmb 0U, // VFPCLASSPSZrmbk 0U, // VFPCLASSPSZrmk 0U, // VFPCLASSPSZrr 0U, // VFPCLASSPSZrrk 0U, // VFPCLASSSDZrm 0U, // VFPCLASSSDZrmk 0U, // VFPCLASSSDZrr 0U, // VFPCLASSSDZrrk 0U, // VFPCLASSSSZrm 0U, // VFPCLASSSSZrmk 0U, // VFPCLASSSSZrr 0U, // VFPCLASSSSZrrk 0U, // VFRCZPDYrm 0U, // VFRCZPDYrr 0U, // VFRCZPDrm 0U, // VFRCZPDrr 0U, // VFRCZPSYrm 0U, // VFRCZPSYrr 0U, // VFRCZPSrm 0U, // VFRCZPSrr 0U, // VFRCZSDrm 0U, // VFRCZSDrr 0U, // VFRCZSSrm 0U, // VFRCZSSrr 0U, // VGATHERDPDYrm 0U, // VGATHERDPDZ128rm 0U, // VGATHERDPDZ256rm 0U, // VGATHERDPDZrm 0U, // VGATHERDPDrm 0U, // VGATHERDPSYrm 0U, // VGATHERDPSZ128rm 0U, // VGATHERDPSZ256rm 0U, // VGATHERDPSZrm 0U, // VGATHERDPSrm 0U, // VGATHERPF0DPDm 0U, // VGATHERPF0DPSm 0U, // VGATHERPF0QPDm 0U, // VGATHERPF0QPSm 0U, // VGATHERPF1DPDm 0U, // VGATHERPF1DPSm 0U, // VGATHERPF1QPDm 0U, // VGATHERPF1QPSm 0U, // VGATHERQPDYrm 0U, // VGATHERQPDZ128rm 0U, // VGATHERQPDZ256rm 0U, // VGATHERQPDZrm 0U, // VGATHERQPDrm 0U, // VGATHERQPSYrm 0U, // VGATHERQPSZ128rm 0U, // VGATHERQPSZ256rm 0U, // VGATHERQPSZrm 0U, // VGATHERQPSrm 0U, // VGETEXPPDZ128m 0U, // VGETEXPPDZ128mb 0U, // VGETEXPPDZ128mbk 0U, // VGETEXPPDZ128mbkz 0U, // VGETEXPPDZ128mk 0U, // VGETEXPPDZ128mkz 0U, // VGETEXPPDZ128r 0U, // VGETEXPPDZ128rk 0U, // VGETEXPPDZ128rkz 0U, // VGETEXPPDZ256m 0U, // VGETEXPPDZ256mb 0U, // VGETEXPPDZ256mbk 0U, // VGETEXPPDZ256mbkz 0U, // VGETEXPPDZ256mk 0U, // VGETEXPPDZ256mkz 0U, // VGETEXPPDZ256r 0U, // VGETEXPPDZ256rk 0U, // VGETEXPPDZ256rkz 0U, // VGETEXPPDZm 0U, // VGETEXPPDZmb 0U, // VGETEXPPDZmbk 0U, // VGETEXPPDZmbkz 0U, // VGETEXPPDZmk 0U, // VGETEXPPDZmkz 0U, // VGETEXPPDZr 0U, // VGETEXPPDZrb 0U, // VGETEXPPDZrbk 0U, // VGETEXPPDZrbkz 0U, // VGETEXPPDZrk 0U, // VGETEXPPDZrkz 0U, // VGETEXPPSZ128m 0U, // VGETEXPPSZ128mb 0U, // VGETEXPPSZ128mbk 0U, // VGETEXPPSZ128mbkz 0U, // VGETEXPPSZ128mk 0U, // VGETEXPPSZ128mkz 0U, // VGETEXPPSZ128r 0U, // VGETEXPPSZ128rk 0U, // VGETEXPPSZ128rkz 0U, // VGETEXPPSZ256m 0U, // VGETEXPPSZ256mb 0U, // VGETEXPPSZ256mbk 0U, // VGETEXPPSZ256mbkz 0U, // VGETEXPPSZ256mk 0U, // VGETEXPPSZ256mkz 0U, // VGETEXPPSZ256r 0U, // VGETEXPPSZ256rk 0U, // VGETEXPPSZ256rkz 0U, // VGETEXPPSZm 0U, // VGETEXPPSZmb 0U, // VGETEXPPSZmbk 0U, // VGETEXPPSZmbkz 0U, // VGETEXPPSZmk 0U, // VGETEXPPSZmkz 0U, // VGETEXPPSZr 0U, // VGETEXPPSZrb 0U, // VGETEXPPSZrbk 0U, // VGETEXPPSZrbkz 0U, // VGETEXPPSZrk 0U, // VGETEXPPSZrkz 0U, // VGETEXPSDZm 0U, // VGETEXPSDZmk 0U, // VGETEXPSDZmkz 0U, // VGETEXPSDZr 0U, // VGETEXPSDZrb 0U, // VGETEXPSDZrbk 0U, // VGETEXPSDZrbkz 0U, // VGETEXPSDZrk 0U, // VGETEXPSDZrkz 0U, // VGETEXPSSZm 0U, // VGETEXPSSZmk 0U, // VGETEXPSSZmkz 0U, // VGETEXPSSZr 0U, // VGETEXPSSZrb 0U, // VGETEXPSSZrbk 0U, // VGETEXPSSZrbkz 0U, // VGETEXPSSZrk 0U, // VGETEXPSSZrkz 0U, // VGETMANTPDZ128rmbi 0U, // VGETMANTPDZ128rmbik 0U, // VGETMANTPDZ128rmbikz 0U, // VGETMANTPDZ128rmi 0U, // VGETMANTPDZ128rmik 0U, // VGETMANTPDZ128rmikz 0U, // VGETMANTPDZ128rri 0U, // VGETMANTPDZ128rrik 0U, // VGETMANTPDZ128rrikz 0U, // VGETMANTPDZ256rmbi 0U, // VGETMANTPDZ256rmbik 0U, // VGETMANTPDZ256rmbikz 0U, // VGETMANTPDZ256rmi 0U, // VGETMANTPDZ256rmik 0U, // VGETMANTPDZ256rmikz 0U, // VGETMANTPDZ256rri 0U, // VGETMANTPDZ256rrik 0U, // VGETMANTPDZ256rrikz 0U, // VGETMANTPDZrmbi 0U, // VGETMANTPDZrmbik 0U, // VGETMANTPDZrmbikz 0U, // VGETMANTPDZrmi 0U, // VGETMANTPDZrmik 0U, // VGETMANTPDZrmikz 0U, // VGETMANTPDZrri 0U, // VGETMANTPDZrrib 0U, // VGETMANTPDZrribk 0U, // VGETMANTPDZrribkz 0U, // VGETMANTPDZrrik 0U, // VGETMANTPDZrrikz 0U, // VGETMANTPSZ128rmbi 0U, // VGETMANTPSZ128rmbik 0U, // VGETMANTPSZ128rmbikz 0U, // VGETMANTPSZ128rmi 0U, // VGETMANTPSZ128rmik 0U, // VGETMANTPSZ128rmikz 0U, // VGETMANTPSZ128rri 0U, // VGETMANTPSZ128rrik 0U, // VGETMANTPSZ128rrikz 0U, // VGETMANTPSZ256rmbi 0U, // VGETMANTPSZ256rmbik 0U, // VGETMANTPSZ256rmbikz 0U, // VGETMANTPSZ256rmi 0U, // VGETMANTPSZ256rmik 0U, // VGETMANTPSZ256rmikz 0U, // VGETMANTPSZ256rri 0U, // VGETMANTPSZ256rrik 0U, // VGETMANTPSZ256rrikz 0U, // VGETMANTPSZrmbi 0U, // VGETMANTPSZrmbik 0U, // VGETMANTPSZrmbikz 0U, // VGETMANTPSZrmi 0U, // VGETMANTPSZrmik 0U, // VGETMANTPSZrmikz 0U, // VGETMANTPSZrri 0U, // VGETMANTPSZrrib 0U, // VGETMANTPSZrribk 0U, // VGETMANTPSZrribkz 0U, // VGETMANTPSZrrik 0U, // VGETMANTPSZrrikz 0U, // VGETMANTSDZrmi 0U, // VGETMANTSDZrmik 3U, // VGETMANTSDZrmikz 0U, // VGETMANTSDZrri 0U, // VGETMANTSDZrrib 0U, // VGETMANTSDZrribk 3U, // VGETMANTSDZrribkz 0U, // VGETMANTSDZrrik 3U, // VGETMANTSDZrrikz 0U, // VGETMANTSSZrmi 0U, // VGETMANTSSZrmik 3U, // VGETMANTSSZrmikz 0U, // VGETMANTSSZrri 0U, // VGETMANTSSZrrib 0U, // VGETMANTSSZrribk 3U, // VGETMANTSSZrribkz 0U, // VGETMANTSSZrrik 3U, // VGETMANTSSZrrikz 0U, // VGF2P8AFFINEINVQBYrmi 0U, // VGF2P8AFFINEINVQBYrri 0U, // VGF2P8AFFINEINVQBZ128rmbi 0U, // VGF2P8AFFINEINVQBZ128rmbik 3U, // VGF2P8AFFINEINVQBZ128rmbikz 0U, // VGF2P8AFFINEINVQBZ128rmi 0U, // VGF2P8AFFINEINVQBZ128rmik 0U, // VGF2P8AFFINEINVQBZ128rmikz 0U, // VGF2P8AFFINEINVQBZ128rri 0U, // VGF2P8AFFINEINVQBZ128rrik 3U, // VGF2P8AFFINEINVQBZ128rrikz 0U, // VGF2P8AFFINEINVQBZ256rmbi 0U, // VGF2P8AFFINEINVQBZ256rmbik 3U, // VGF2P8AFFINEINVQBZ256rmbikz 0U, // VGF2P8AFFINEINVQBZ256rmi 0U, // VGF2P8AFFINEINVQBZ256rmik 0U, // VGF2P8AFFINEINVQBZ256rmikz 0U, // VGF2P8AFFINEINVQBZ256rri 0U, // VGF2P8AFFINEINVQBZ256rrik 3U, // VGF2P8AFFINEINVQBZ256rrikz 0U, // VGF2P8AFFINEINVQBZrmbi 0U, // VGF2P8AFFINEINVQBZrmbik 3U, // VGF2P8AFFINEINVQBZrmbikz 0U, // VGF2P8AFFINEINVQBZrmi 0U, // VGF2P8AFFINEINVQBZrmik 0U, // VGF2P8AFFINEINVQBZrmikz 0U, // VGF2P8AFFINEINVQBZrri 0U, // VGF2P8AFFINEINVQBZrrik 3U, // VGF2P8AFFINEINVQBZrrikz 0U, // VGF2P8AFFINEINVQBrmi 0U, // VGF2P8AFFINEINVQBrri 0U, // VGF2P8AFFINEQBYrmi 0U, // VGF2P8AFFINEQBYrri 0U, // VGF2P8AFFINEQBZ128rmbi 0U, // VGF2P8AFFINEQBZ128rmbik 3U, // VGF2P8AFFINEQBZ128rmbikz 0U, // VGF2P8AFFINEQBZ128rmi 0U, // VGF2P8AFFINEQBZ128rmik 0U, // VGF2P8AFFINEQBZ128rmikz 0U, // VGF2P8AFFINEQBZ128rri 0U, // VGF2P8AFFINEQBZ128rrik 3U, // VGF2P8AFFINEQBZ128rrikz 0U, // VGF2P8AFFINEQBZ256rmbi 0U, // VGF2P8AFFINEQBZ256rmbik 3U, // VGF2P8AFFINEQBZ256rmbikz 0U, // VGF2P8AFFINEQBZ256rmi 0U, // VGF2P8AFFINEQBZ256rmik 0U, // VGF2P8AFFINEQBZ256rmikz 0U, // VGF2P8AFFINEQBZ256rri 0U, // VGF2P8AFFINEQBZ256rrik 3U, // VGF2P8AFFINEQBZ256rrikz 0U, // VGF2P8AFFINEQBZrmbi 0U, // VGF2P8AFFINEQBZrmbik 3U, // VGF2P8AFFINEQBZrmbikz 0U, // VGF2P8AFFINEQBZrmi 0U, // VGF2P8AFFINEQBZrmik 0U, // VGF2P8AFFINEQBZrmikz 0U, // VGF2P8AFFINEQBZrri 0U, // VGF2P8AFFINEQBZrrik 3U, // VGF2P8AFFINEQBZrrikz 0U, // VGF2P8AFFINEQBrmi 0U, // VGF2P8AFFINEQBrri 0U, // VGF2P8MULBYrm 0U, // VGF2P8MULBYrr 0U, // VGF2P8MULBZ128rm 0U, // VGF2P8MULBZ128rmk 0U, // VGF2P8MULBZ128rmkz 0U, // VGF2P8MULBZ128rr 0U, // VGF2P8MULBZ128rrk 0U, // VGF2P8MULBZ128rrkz 0U, // VGF2P8MULBZ256rm 0U, // VGF2P8MULBZ256rmk 0U, // VGF2P8MULBZ256rmkz 0U, // VGF2P8MULBZ256rr 0U, // VGF2P8MULBZ256rrk 0U, // VGF2P8MULBZ256rrkz 0U, // VGF2P8MULBZrm 0U, // VGF2P8MULBZrmk 0U, // VGF2P8MULBZrmkz 0U, // VGF2P8MULBZrr 0U, // VGF2P8MULBZrrk 0U, // VGF2P8MULBZrrkz 0U, // VGF2P8MULBrm 0U, // VGF2P8MULBrr 0U, // VHADDPDYrm 0U, // VHADDPDYrr 0U, // VHADDPDrm 0U, // VHADDPDrr 0U, // VHADDPSYrm 0U, // VHADDPSYrr 0U, // VHADDPSrm 0U, // VHADDPSrr 0U, // VHSUBPDYrm 0U, // VHSUBPDYrr 0U, // VHSUBPDrm 0U, // VHSUBPDrr 0U, // VHSUBPSYrm 0U, // VHSUBPSYrr 0U, // VHSUBPSrm 0U, // VHSUBPSrr 0U, // VINSERTF128rm 0U, // VINSERTF128rr 0U, // VINSERTF32x4Z256rm 0U, // VINSERTF32x4Z256rmk 0U, // VINSERTF32x4Z256rmkz 0U, // VINSERTF32x4Z256rr 0U, // VINSERTF32x4Z256rrk 3U, // VINSERTF32x4Z256rrkz 0U, // VINSERTF32x4Zrm 0U, // VINSERTF32x4Zrmk 0U, // VINSERTF32x4Zrmkz 0U, // VINSERTF32x4Zrr 0U, // VINSERTF32x4Zrrk 3U, // VINSERTF32x4Zrrkz 0U, // VINSERTF32x8Zrm 0U, // VINSERTF32x8Zrmk 0U, // VINSERTF32x8Zrmkz 0U, // VINSERTF32x8Zrr 0U, // VINSERTF32x8Zrrk 3U, // VINSERTF32x8Zrrkz 0U, // VINSERTF64x2Z256rm 0U, // VINSERTF64x2Z256rmk 0U, // VINSERTF64x2Z256rmkz 0U, // VINSERTF64x2Z256rr 0U, // VINSERTF64x2Z256rrk 3U, // VINSERTF64x2Z256rrkz 0U, // VINSERTF64x2Zrm 0U, // VINSERTF64x2Zrmk 0U, // VINSERTF64x2Zrmkz 0U, // VINSERTF64x2Zrr 0U, // VINSERTF64x2Zrrk 3U, // VINSERTF64x2Zrrkz 0U, // VINSERTF64x4Zrm 0U, // VINSERTF64x4Zrmk 0U, // VINSERTF64x4Zrmkz 0U, // VINSERTF64x4Zrr 0U, // VINSERTF64x4Zrrk 3U, // VINSERTF64x4Zrrkz 0U, // VINSERTI128rm 0U, // VINSERTI128rr 0U, // VINSERTI32x4Z256rm 0U, // VINSERTI32x4Z256rmk 0U, // VINSERTI32x4Z256rmkz 0U, // VINSERTI32x4Z256rr 0U, // VINSERTI32x4Z256rrk 3U, // VINSERTI32x4Z256rrkz 0U, // VINSERTI32x4Zrm 0U, // VINSERTI32x4Zrmk 0U, // VINSERTI32x4Zrmkz 0U, // VINSERTI32x4Zrr 0U, // VINSERTI32x4Zrrk 3U, // VINSERTI32x4Zrrkz 0U, // VINSERTI32x8Zrm 0U, // VINSERTI32x8Zrmk 0U, // VINSERTI32x8Zrmkz 0U, // VINSERTI32x8Zrr 0U, // VINSERTI32x8Zrrk 3U, // VINSERTI32x8Zrrkz 0U, // VINSERTI64x2Z256rm 0U, // VINSERTI64x2Z256rmk 0U, // VINSERTI64x2Z256rmkz 0U, // VINSERTI64x2Z256rr 0U, // VINSERTI64x2Z256rrk 3U, // VINSERTI64x2Z256rrkz 0U, // VINSERTI64x2Zrm 0U, // VINSERTI64x2Zrmk 0U, // VINSERTI64x2Zrmkz 0U, // VINSERTI64x2Zrr 0U, // VINSERTI64x2Zrrk 3U, // VINSERTI64x2Zrrkz 0U, // VINSERTI64x4Zrm 0U, // VINSERTI64x4Zrmk 0U, // VINSERTI64x4Zrmkz 0U, // VINSERTI64x4Zrr 0U, // VINSERTI64x4Zrrk 3U, // VINSERTI64x4Zrrkz 0U, // VINSERTPSZrm 0U, // VINSERTPSZrr 0U, // VINSERTPSrm 0U, // VINSERTPSrr 0U, // VLDDQUYrm 0U, // VLDDQUrm 0U, // VLDMXCSR 0U, // VMASKMOVDQU 0U, // VMASKMOVDQU64 0U, // VMASKMOVPDYmr 0U, // VMASKMOVPDYrm 0U, // VMASKMOVPDmr 0U, // VMASKMOVPDrm 0U, // VMASKMOVPSYmr 0U, // VMASKMOVPSYrm 0U, // VMASKMOVPSmr 0U, // VMASKMOVPSrm 0U, // VMAXCPDYrm 0U, // VMAXCPDYrr 0U, // VMAXCPDZ128rm 0U, // VMAXCPDZ128rmb 0U, // VMAXCPDZ128rmbk 0U, // VMAXCPDZ128rmbkz 0U, // VMAXCPDZ128rmk 0U, // VMAXCPDZ128rmkz 0U, // VMAXCPDZ128rr 0U, // VMAXCPDZ128rrk 0U, // VMAXCPDZ128rrkz 0U, // VMAXCPDZ256rm 0U, // VMAXCPDZ256rmb 0U, // VMAXCPDZ256rmbk 0U, // VMAXCPDZ256rmbkz 0U, // VMAXCPDZ256rmk 0U, // VMAXCPDZ256rmkz 0U, // VMAXCPDZ256rr 0U, // VMAXCPDZ256rrk 0U, // VMAXCPDZ256rrkz 0U, // VMAXCPDZrm 0U, // VMAXCPDZrmb 0U, // VMAXCPDZrmbk 0U, // VMAXCPDZrmbkz 0U, // VMAXCPDZrmk 0U, // VMAXCPDZrmkz 0U, // VMAXCPDZrr 0U, // VMAXCPDZrrk 0U, // VMAXCPDZrrkz 0U, // VMAXCPDrm 0U, // VMAXCPDrr 0U, // VMAXCPSYrm 0U, // VMAXCPSYrr 0U, // VMAXCPSZ128rm 0U, // VMAXCPSZ128rmb 0U, // VMAXCPSZ128rmbk 0U, // VMAXCPSZ128rmbkz 0U, // VMAXCPSZ128rmk 0U, // VMAXCPSZ128rmkz 0U, // VMAXCPSZ128rr 0U, // VMAXCPSZ128rrk 0U, // VMAXCPSZ128rrkz 0U, // VMAXCPSZ256rm 0U, // VMAXCPSZ256rmb 0U, // VMAXCPSZ256rmbk 0U, // VMAXCPSZ256rmbkz 0U, // VMAXCPSZ256rmk 0U, // VMAXCPSZ256rmkz 0U, // VMAXCPSZ256rr 0U, // VMAXCPSZ256rrk 0U, // VMAXCPSZ256rrkz 0U, // VMAXCPSZrm 0U, // VMAXCPSZrmb 0U, // VMAXCPSZrmbk 0U, // VMAXCPSZrmbkz 0U, // VMAXCPSZrmk 0U, // VMAXCPSZrmkz 0U, // VMAXCPSZrr 0U, // VMAXCPSZrrk 0U, // VMAXCPSZrrkz 0U, // VMAXCPSrm 0U, // VMAXCPSrr 0U, // VMAXCSDZrm 0U, // VMAXCSDZrr 0U, // VMAXCSDrm 0U, // VMAXCSDrr 0U, // VMAXCSSZrm 0U, // VMAXCSSZrr 0U, // VMAXCSSrm 0U, // VMAXCSSrr 0U, // VMAXPDYrm 0U, // VMAXPDYrr 0U, // VMAXPDZ128rm 0U, // VMAXPDZ128rmb 0U, // VMAXPDZ128rmbk 0U, // VMAXPDZ128rmbkz 0U, // VMAXPDZ128rmk 0U, // VMAXPDZ128rmkz 0U, // VMAXPDZ128rr 0U, // VMAXPDZ128rrk 0U, // VMAXPDZ128rrkz 0U, // VMAXPDZ256rm 0U, // VMAXPDZ256rmb 0U, // VMAXPDZ256rmbk 0U, // VMAXPDZ256rmbkz 0U, // VMAXPDZ256rmk 0U, // VMAXPDZ256rmkz 0U, // VMAXPDZ256rr 0U, // VMAXPDZ256rrk 0U, // VMAXPDZ256rrkz 0U, // VMAXPDZrm 0U, // VMAXPDZrmb 0U, // VMAXPDZrmbk 0U, // VMAXPDZrmbkz 0U, // VMAXPDZrmk 0U, // VMAXPDZrmkz 0U, // VMAXPDZrr 0U, // VMAXPDZrrb 0U, // VMAXPDZrrbk 0U, // VMAXPDZrrbkz 0U, // VMAXPDZrrk 0U, // VMAXPDZrrkz 0U, // VMAXPDrm 0U, // VMAXPDrr 0U, // VMAXPSYrm 0U, // VMAXPSYrr 0U, // VMAXPSZ128rm 0U, // VMAXPSZ128rmb 0U, // VMAXPSZ128rmbk 0U, // VMAXPSZ128rmbkz 0U, // VMAXPSZ128rmk 0U, // VMAXPSZ128rmkz 0U, // VMAXPSZ128rr 0U, // VMAXPSZ128rrk 0U, // VMAXPSZ128rrkz 0U, // VMAXPSZ256rm 0U, // VMAXPSZ256rmb 0U, // VMAXPSZ256rmbk 0U, // VMAXPSZ256rmbkz 0U, // VMAXPSZ256rmk 0U, // VMAXPSZ256rmkz 0U, // VMAXPSZ256rr 0U, // VMAXPSZ256rrk 0U, // VMAXPSZ256rrkz 0U, // VMAXPSZrm 0U, // VMAXPSZrmb 0U, // VMAXPSZrmbk 0U, // VMAXPSZrmbkz 0U, // VMAXPSZrmk 0U, // VMAXPSZrmkz 0U, // VMAXPSZrr 0U, // VMAXPSZrrb 0U, // VMAXPSZrrbk 0U, // VMAXPSZrrbkz 0U, // VMAXPSZrrk 0U, // VMAXPSZrrkz 0U, // VMAXPSrm 0U, // VMAXPSrr 0U, // VMAXSDZrm 0U, // VMAXSDZrm_Int 0U, // VMAXSDZrm_Intk 0U, // VMAXSDZrm_Intkz 0U, // VMAXSDZrr 0U, // VMAXSDZrr_Int 0U, // VMAXSDZrr_Intk 0U, // VMAXSDZrr_Intkz 0U, // VMAXSDZrrb_Int 0U, // VMAXSDZrrb_Intk 0U, // VMAXSDZrrb_Intkz 0U, // VMAXSDrm 0U, // VMAXSDrm_Int 0U, // VMAXSDrr 0U, // VMAXSDrr_Int 0U, // VMAXSSZrm 0U, // VMAXSSZrm_Int 0U, // VMAXSSZrm_Intk 0U, // VMAXSSZrm_Intkz 0U, // VMAXSSZrr 0U, // VMAXSSZrr_Int 0U, // VMAXSSZrr_Intk 0U, // VMAXSSZrr_Intkz 0U, // VMAXSSZrrb_Int 0U, // VMAXSSZrrb_Intk 0U, // VMAXSSZrrb_Intkz 0U, // VMAXSSrm 0U, // VMAXSSrm_Int 0U, // VMAXSSrr 0U, // VMAXSSrr_Int 0U, // VMCALL 0U, // VMCLEARm 0U, // VMFUNC 0U, // VMINCPDYrm 0U, // VMINCPDYrr 0U, // VMINCPDZ128rm 0U, // VMINCPDZ128rmb 0U, // VMINCPDZ128rmbk 0U, // VMINCPDZ128rmbkz 0U, // VMINCPDZ128rmk 0U, // VMINCPDZ128rmkz 0U, // VMINCPDZ128rr 0U, // VMINCPDZ128rrk 0U, // VMINCPDZ128rrkz 0U, // VMINCPDZ256rm 0U, // VMINCPDZ256rmb 0U, // VMINCPDZ256rmbk 0U, // VMINCPDZ256rmbkz 0U, // VMINCPDZ256rmk 0U, // VMINCPDZ256rmkz 0U, // VMINCPDZ256rr 0U, // VMINCPDZ256rrk 0U, // VMINCPDZ256rrkz 0U, // VMINCPDZrm 0U, // VMINCPDZrmb 0U, // VMINCPDZrmbk 0U, // VMINCPDZrmbkz 0U, // VMINCPDZrmk 0U, // VMINCPDZrmkz 0U, // VMINCPDZrr 0U, // VMINCPDZrrk 0U, // VMINCPDZrrkz 0U, // VMINCPDrm 0U, // VMINCPDrr 0U, // VMINCPSYrm 0U, // VMINCPSYrr 0U, // VMINCPSZ128rm 0U, // VMINCPSZ128rmb 0U, // VMINCPSZ128rmbk 0U, // VMINCPSZ128rmbkz 0U, // VMINCPSZ128rmk 0U, // VMINCPSZ128rmkz 0U, // VMINCPSZ128rr 0U, // VMINCPSZ128rrk 0U, // VMINCPSZ128rrkz 0U, // VMINCPSZ256rm 0U, // VMINCPSZ256rmb 0U, // VMINCPSZ256rmbk 0U, // VMINCPSZ256rmbkz 0U, // VMINCPSZ256rmk 0U, // VMINCPSZ256rmkz 0U, // VMINCPSZ256rr 0U, // VMINCPSZ256rrk 0U, // VMINCPSZ256rrkz 0U, // VMINCPSZrm 0U, // VMINCPSZrmb 0U, // VMINCPSZrmbk 0U, // VMINCPSZrmbkz 0U, // VMINCPSZrmk 0U, // VMINCPSZrmkz 0U, // VMINCPSZrr 0U, // VMINCPSZrrk 0U, // VMINCPSZrrkz 0U, // VMINCPSrm 0U, // VMINCPSrr 0U, // VMINCSDZrm 0U, // VMINCSDZrr 0U, // VMINCSDrm 0U, // VMINCSDrr 0U, // VMINCSSZrm 0U, // VMINCSSZrr 0U, // VMINCSSrm 0U, // VMINCSSrr 0U, // VMINPDYrm 0U, // VMINPDYrr 0U, // VMINPDZ128rm 0U, // VMINPDZ128rmb 0U, // VMINPDZ128rmbk 0U, // VMINPDZ128rmbkz 0U, // VMINPDZ128rmk 0U, // VMINPDZ128rmkz 0U, // VMINPDZ128rr 0U, // VMINPDZ128rrk 0U, // VMINPDZ128rrkz 0U, // VMINPDZ256rm 0U, // VMINPDZ256rmb 0U, // VMINPDZ256rmbk 0U, // VMINPDZ256rmbkz 0U, // VMINPDZ256rmk 0U, // VMINPDZ256rmkz 0U, // VMINPDZ256rr 0U, // VMINPDZ256rrk 0U, // VMINPDZ256rrkz 0U, // VMINPDZrm 0U, // VMINPDZrmb 0U, // VMINPDZrmbk 0U, // VMINPDZrmbkz 0U, // VMINPDZrmk 0U, // VMINPDZrmkz 0U, // VMINPDZrr 0U, // VMINPDZrrb 0U, // VMINPDZrrbk 0U, // VMINPDZrrbkz 0U, // VMINPDZrrk 0U, // VMINPDZrrkz 0U, // VMINPDrm 0U, // VMINPDrr 0U, // VMINPSYrm 0U, // VMINPSYrr 0U, // VMINPSZ128rm 0U, // VMINPSZ128rmb 0U, // VMINPSZ128rmbk 0U, // VMINPSZ128rmbkz 0U, // VMINPSZ128rmk 0U, // VMINPSZ128rmkz 0U, // VMINPSZ128rr 0U, // VMINPSZ128rrk 0U, // VMINPSZ128rrkz 0U, // VMINPSZ256rm 0U, // VMINPSZ256rmb 0U, // VMINPSZ256rmbk 0U, // VMINPSZ256rmbkz 0U, // VMINPSZ256rmk 0U, // VMINPSZ256rmkz 0U, // VMINPSZ256rr 0U, // VMINPSZ256rrk 0U, // VMINPSZ256rrkz 0U, // VMINPSZrm 0U, // VMINPSZrmb 0U, // VMINPSZrmbk 0U, // VMINPSZrmbkz 0U, // VMINPSZrmk 0U, // VMINPSZrmkz 0U, // VMINPSZrr 0U, // VMINPSZrrb 0U, // VMINPSZrrbk 0U, // VMINPSZrrbkz 0U, // VMINPSZrrk 0U, // VMINPSZrrkz 0U, // VMINPSrm 0U, // VMINPSrr 0U, // VMINSDZrm 0U, // VMINSDZrm_Int 0U, // VMINSDZrm_Intk 0U, // VMINSDZrm_Intkz 0U, // VMINSDZrr 0U, // VMINSDZrr_Int 0U, // VMINSDZrr_Intk 0U, // VMINSDZrr_Intkz 0U, // VMINSDZrrb_Int 0U, // VMINSDZrrb_Intk 0U, // VMINSDZrrb_Intkz 0U, // VMINSDrm 0U, // VMINSDrm_Int 0U, // VMINSDrr 0U, // VMINSDrr_Int 0U, // VMINSSZrm 0U, // VMINSSZrm_Int 0U, // VMINSSZrm_Intk 0U, // VMINSSZrm_Intkz 0U, // VMINSSZrr 0U, // VMINSSZrr_Int 0U, // VMINSSZrr_Intk 0U, // VMINSSZrr_Intkz 0U, // VMINSSZrrb_Int 0U, // VMINSSZrrb_Intk 0U, // VMINSSZrrb_Intkz 0U, // VMINSSrm 0U, // VMINSSrm_Int 0U, // VMINSSrr 0U, // VMINSSrr_Int 0U, // VMLAUNCH 0U, // VMLOAD32 0U, // VMLOAD64 0U, // VMMCALL 0U, // VMOV64toPQIZrm 0U, // VMOV64toPQIZrr 0U, // VMOV64toPQIrm 0U, // VMOV64toPQIrr 0U, // VMOV64toSDZrm 0U, // VMOV64toSDZrr 0U, // VMOV64toSDrm 0U, // VMOV64toSDrr 0U, // VMOVAPDYmr 0U, // VMOVAPDYrm 0U, // VMOVAPDYrr 0U, // VMOVAPDYrr_REV 0U, // VMOVAPDZ128mr 0U, // VMOVAPDZ128mrk 0U, // VMOVAPDZ128rm 0U, // VMOVAPDZ128rmk 0U, // VMOVAPDZ128rmkz 0U, // VMOVAPDZ128rr 0U, // VMOVAPDZ128rr_REV 0U, // VMOVAPDZ128rrk 0U, // VMOVAPDZ128rrk_REV 0U, // VMOVAPDZ128rrkz 0U, // VMOVAPDZ128rrkz_REV 0U, // VMOVAPDZ256mr 0U, // VMOVAPDZ256mrk 0U, // VMOVAPDZ256rm 0U, // VMOVAPDZ256rmk 0U, // VMOVAPDZ256rmkz 0U, // VMOVAPDZ256rr 0U, // VMOVAPDZ256rr_REV 0U, // VMOVAPDZ256rrk 0U, // VMOVAPDZ256rrk_REV 0U, // VMOVAPDZ256rrkz 0U, // VMOVAPDZ256rrkz_REV 0U, // VMOVAPDZmr 0U, // VMOVAPDZmrk 0U, // VMOVAPDZrm 0U, // VMOVAPDZrmk 0U, // VMOVAPDZrmkz 0U, // VMOVAPDZrr 0U, // VMOVAPDZrr_REV 0U, // VMOVAPDZrrk 0U, // VMOVAPDZrrk_REV 0U, // VMOVAPDZrrkz 0U, // VMOVAPDZrrkz_REV 0U, // VMOVAPDmr 0U, // VMOVAPDrm 0U, // VMOVAPDrr 0U, // VMOVAPDrr_REV 0U, // VMOVAPSYmr 0U, // VMOVAPSYrm 0U, // VMOVAPSYrr 0U, // VMOVAPSYrr_REV 0U, // VMOVAPSZ128mr 0U, // VMOVAPSZ128mrk 0U, // VMOVAPSZ128rm 0U, // VMOVAPSZ128rmk 0U, // VMOVAPSZ128rmkz 0U, // VMOVAPSZ128rr 0U, // VMOVAPSZ128rr_REV 0U, // VMOVAPSZ128rrk 0U, // VMOVAPSZ128rrk_REV 0U, // VMOVAPSZ128rrkz 0U, // VMOVAPSZ128rrkz_REV 0U, // VMOVAPSZ256mr 0U, // VMOVAPSZ256mrk 0U, // VMOVAPSZ256rm 0U, // VMOVAPSZ256rmk 0U, // VMOVAPSZ256rmkz 0U, // VMOVAPSZ256rr 0U, // VMOVAPSZ256rr_REV 0U, // VMOVAPSZ256rrk 0U, // VMOVAPSZ256rrk_REV 0U, // VMOVAPSZ256rrkz 0U, // VMOVAPSZ256rrkz_REV 0U, // VMOVAPSZmr 0U, // VMOVAPSZmrk 0U, // VMOVAPSZrm 0U, // VMOVAPSZrmk 0U, // VMOVAPSZrmkz 0U, // VMOVAPSZrr 0U, // VMOVAPSZrr_REV 0U, // VMOVAPSZrrk 0U, // VMOVAPSZrrk_REV 0U, // VMOVAPSZrrkz 0U, // VMOVAPSZrrkz_REV 0U, // VMOVAPSmr 0U, // VMOVAPSrm 0U, // VMOVAPSrr 0U, // VMOVAPSrr_REV 0U, // VMOVDDUPYrm 0U, // VMOVDDUPYrr 0U, // VMOVDDUPZ128rm 0U, // VMOVDDUPZ128rmk 0U, // VMOVDDUPZ128rmkz 0U, // VMOVDDUPZ128rr 0U, // VMOVDDUPZ128rrk 0U, // VMOVDDUPZ128rrkz 0U, // VMOVDDUPZ256rm 0U, // VMOVDDUPZ256rmk 0U, // VMOVDDUPZ256rmkz 0U, // VMOVDDUPZ256rr 0U, // VMOVDDUPZ256rrk 0U, // VMOVDDUPZ256rrkz 0U, // VMOVDDUPZrm 0U, // VMOVDDUPZrmk 0U, // VMOVDDUPZrmkz 0U, // VMOVDDUPZrr 0U, // VMOVDDUPZrrk 0U, // VMOVDDUPZrrkz 0U, // VMOVDDUPrm 0U, // VMOVDDUPrr 0U, // VMOVDI2PDIZrm 0U, // VMOVDI2PDIZrr 0U, // VMOVDI2PDIrm 0U, // VMOVDI2PDIrr 0U, // VMOVDI2SSZrm 0U, // VMOVDI2SSZrr 0U, // VMOVDI2SSrm 0U, // VMOVDI2SSrr 0U, // VMOVDQA32Z128mr 0U, // VMOVDQA32Z128mrk 0U, // VMOVDQA32Z128rm 0U, // VMOVDQA32Z128rmk 0U, // VMOVDQA32Z128rmkz 0U, // VMOVDQA32Z128rr 0U, // VMOVDQA32Z128rr_REV 0U, // VMOVDQA32Z128rrk 0U, // VMOVDQA32Z128rrk_REV 0U, // VMOVDQA32Z128rrkz 0U, // VMOVDQA32Z128rrkz_REV 0U, // VMOVDQA32Z256mr 0U, // VMOVDQA32Z256mrk 0U, // VMOVDQA32Z256rm 0U, // VMOVDQA32Z256rmk 0U, // VMOVDQA32Z256rmkz 0U, // VMOVDQA32Z256rr 0U, // VMOVDQA32Z256rr_REV 0U, // VMOVDQA32Z256rrk 0U, // VMOVDQA32Z256rrk_REV 0U, // VMOVDQA32Z256rrkz 0U, // VMOVDQA32Z256rrkz_REV 0U, // VMOVDQA32Zmr 0U, // VMOVDQA32Zmrk 0U, // VMOVDQA32Zrm 0U, // VMOVDQA32Zrmk 0U, // VMOVDQA32Zrmkz 0U, // VMOVDQA32Zrr 0U, // VMOVDQA32Zrr_REV 0U, // VMOVDQA32Zrrk 0U, // VMOVDQA32Zrrk_REV 0U, // VMOVDQA32Zrrkz 0U, // VMOVDQA32Zrrkz_REV 0U, // VMOVDQA64Z128mr 0U, // VMOVDQA64Z128mrk 0U, // VMOVDQA64Z128rm 0U, // VMOVDQA64Z128rmk 0U, // VMOVDQA64Z128rmkz 0U, // VMOVDQA64Z128rr 0U, // VMOVDQA64Z128rr_REV 0U, // VMOVDQA64Z128rrk 0U, // VMOVDQA64Z128rrk_REV 0U, // VMOVDQA64Z128rrkz 0U, // VMOVDQA64Z128rrkz_REV 0U, // VMOVDQA64Z256mr 0U, // VMOVDQA64Z256mrk 0U, // VMOVDQA64Z256rm 0U, // VMOVDQA64Z256rmk 0U, // VMOVDQA64Z256rmkz 0U, // VMOVDQA64Z256rr 0U, // VMOVDQA64Z256rr_REV 0U, // VMOVDQA64Z256rrk 0U, // VMOVDQA64Z256rrk_REV 0U, // VMOVDQA64Z256rrkz 0U, // VMOVDQA64Z256rrkz_REV 0U, // VMOVDQA64Zmr 0U, // VMOVDQA64Zmrk 0U, // VMOVDQA64Zrm 0U, // VMOVDQA64Zrmk 0U, // VMOVDQA64Zrmkz 0U, // VMOVDQA64Zrr 0U, // VMOVDQA64Zrr_REV 0U, // VMOVDQA64Zrrk 0U, // VMOVDQA64Zrrk_REV 0U, // VMOVDQA64Zrrkz 0U, // VMOVDQA64Zrrkz_REV 0U, // VMOVDQAYmr 0U, // VMOVDQAYrm 0U, // VMOVDQAYrr 0U, // VMOVDQAYrr_REV 0U, // VMOVDQAmr 0U, // VMOVDQArm 0U, // VMOVDQArr 0U, // VMOVDQArr_REV 0U, // VMOVDQU16Z128mr 0U, // VMOVDQU16Z128mrk 0U, // VMOVDQU16Z128rm 0U, // VMOVDQU16Z128rmk 0U, // VMOVDQU16Z128rmkz 0U, // VMOVDQU16Z128rr 0U, // VMOVDQU16Z128rr_REV 0U, // VMOVDQU16Z128rrk 0U, // VMOVDQU16Z128rrk_REV 0U, // VMOVDQU16Z128rrkz 0U, // VMOVDQU16Z128rrkz_REV 0U, // VMOVDQU16Z256mr 0U, // VMOVDQU16Z256mrk 0U, // VMOVDQU16Z256rm 0U, // VMOVDQU16Z256rmk 0U, // VMOVDQU16Z256rmkz 0U, // VMOVDQU16Z256rr 0U, // VMOVDQU16Z256rr_REV 0U, // VMOVDQU16Z256rrk 0U, // VMOVDQU16Z256rrk_REV 0U, // VMOVDQU16Z256rrkz 0U, // VMOVDQU16Z256rrkz_REV 0U, // VMOVDQU16Zmr 0U, // VMOVDQU16Zmrk 0U, // VMOVDQU16Zrm 0U, // VMOVDQU16Zrmk 0U, // VMOVDQU16Zrmkz 0U, // VMOVDQU16Zrr 0U, // VMOVDQU16Zrr_REV 0U, // VMOVDQU16Zrrk 0U, // VMOVDQU16Zrrk_REV 0U, // VMOVDQU16Zrrkz 0U, // VMOVDQU16Zrrkz_REV 0U, // VMOVDQU32Z128mr 0U, // VMOVDQU32Z128mrk 0U, // VMOVDQU32Z128rm 0U, // VMOVDQU32Z128rmk 0U, // VMOVDQU32Z128rmkz 0U, // VMOVDQU32Z128rr 0U, // VMOVDQU32Z128rr_REV 0U, // VMOVDQU32Z128rrk 0U, // VMOVDQU32Z128rrk_REV 0U, // VMOVDQU32Z128rrkz 0U, // VMOVDQU32Z128rrkz_REV 0U, // VMOVDQU32Z256mr 0U, // VMOVDQU32Z256mrk 0U, // VMOVDQU32Z256rm 0U, // VMOVDQU32Z256rmk 0U, // VMOVDQU32Z256rmkz 0U, // VMOVDQU32Z256rr 0U, // VMOVDQU32Z256rr_REV 0U, // VMOVDQU32Z256rrk 0U, // VMOVDQU32Z256rrk_REV 0U, // VMOVDQU32Z256rrkz 0U, // VMOVDQU32Z256rrkz_REV 0U, // VMOVDQU32Zmr 0U, // VMOVDQU32Zmrk 0U, // VMOVDQU32Zrm 0U, // VMOVDQU32Zrmk 0U, // VMOVDQU32Zrmkz 0U, // VMOVDQU32Zrr 0U, // VMOVDQU32Zrr_REV 0U, // VMOVDQU32Zrrk 0U, // VMOVDQU32Zrrk_REV 0U, // VMOVDQU32Zrrkz 0U, // VMOVDQU32Zrrkz_REV 0U, // VMOVDQU64Z128mr 0U, // VMOVDQU64Z128mrk 0U, // VMOVDQU64Z128rm 0U, // VMOVDQU64Z128rmk 0U, // VMOVDQU64Z128rmkz 0U, // VMOVDQU64Z128rr 0U, // VMOVDQU64Z128rr_REV 0U, // VMOVDQU64Z128rrk 0U, // VMOVDQU64Z128rrk_REV 0U, // VMOVDQU64Z128rrkz 0U, // VMOVDQU64Z128rrkz_REV 0U, // VMOVDQU64Z256mr 0U, // VMOVDQU64Z256mrk 0U, // VMOVDQU64Z256rm 0U, // VMOVDQU64Z256rmk 0U, // VMOVDQU64Z256rmkz 0U, // VMOVDQU64Z256rr 0U, // VMOVDQU64Z256rr_REV 0U, // VMOVDQU64Z256rrk 0U, // VMOVDQU64Z256rrk_REV 0U, // VMOVDQU64Z256rrkz 0U, // VMOVDQU64Z256rrkz_REV 0U, // VMOVDQU64Zmr 0U, // VMOVDQU64Zmrk 0U, // VMOVDQU64Zrm 0U, // VMOVDQU64Zrmk 0U, // VMOVDQU64Zrmkz 0U, // VMOVDQU64Zrr 0U, // VMOVDQU64Zrr_REV 0U, // VMOVDQU64Zrrk 0U, // VMOVDQU64Zrrk_REV 0U, // VMOVDQU64Zrrkz 0U, // VMOVDQU64Zrrkz_REV 0U, // VMOVDQU8Z128mr 0U, // VMOVDQU8Z128mrk 0U, // VMOVDQU8Z128rm 0U, // VMOVDQU8Z128rmk 0U, // VMOVDQU8Z128rmkz 0U, // VMOVDQU8Z128rr 0U, // VMOVDQU8Z128rr_REV 0U, // VMOVDQU8Z128rrk 0U, // VMOVDQU8Z128rrk_REV 0U, // VMOVDQU8Z128rrkz 0U, // VMOVDQU8Z128rrkz_REV 0U, // VMOVDQU8Z256mr 0U, // VMOVDQU8Z256mrk 0U, // VMOVDQU8Z256rm 0U, // VMOVDQU8Z256rmk 0U, // VMOVDQU8Z256rmkz 0U, // VMOVDQU8Z256rr 0U, // VMOVDQU8Z256rr_REV 0U, // VMOVDQU8Z256rrk 0U, // VMOVDQU8Z256rrk_REV 0U, // VMOVDQU8Z256rrkz 0U, // VMOVDQU8Z256rrkz_REV 0U, // VMOVDQU8Zmr 0U, // VMOVDQU8Zmrk 0U, // VMOVDQU8Zrm 0U, // VMOVDQU8Zrmk 0U, // VMOVDQU8Zrmkz 0U, // VMOVDQU8Zrr 0U, // VMOVDQU8Zrr_REV 0U, // VMOVDQU8Zrrk 0U, // VMOVDQU8Zrrk_REV 0U, // VMOVDQU8Zrrkz 0U, // VMOVDQU8Zrrkz_REV 0U, // VMOVDQUYmr 0U, // VMOVDQUYrm 0U, // VMOVDQUYrr 0U, // VMOVDQUYrr_REV 0U, // VMOVDQUmr 0U, // VMOVDQUrm 0U, // VMOVDQUrr 0U, // VMOVDQUrr_REV 0U, // VMOVHLPSZrr 0U, // VMOVHLPSrr 0U, // VMOVHPDZ128mr 0U, // VMOVHPDZ128rm 0U, // VMOVHPDmr 0U, // VMOVHPDrm 0U, // VMOVHPSZ128mr 0U, // VMOVHPSZ128rm 0U, // VMOVHPSmr 0U, // VMOVHPSrm 0U, // VMOVLHPSZrr 0U, // VMOVLHPSrr 0U, // VMOVLPDZ128mr 0U, // VMOVLPDZ128rm 0U, // VMOVLPDmr 0U, // VMOVLPDrm 0U, // VMOVLPSZ128mr 0U, // VMOVLPSZ128rm 0U, // VMOVLPSmr 0U, // VMOVLPSrm 0U, // VMOVMSKPDYrr 0U, // VMOVMSKPDrr 0U, // VMOVMSKPSYrr 0U, // VMOVMSKPSrr 0U, // VMOVNTDQAYrm 0U, // VMOVNTDQAZ128rm 0U, // VMOVNTDQAZ256rm 0U, // VMOVNTDQAZrm 0U, // VMOVNTDQArm 0U, // VMOVNTDQYmr 0U, // VMOVNTDQZ128mr 0U, // VMOVNTDQZ256mr 0U, // VMOVNTDQZmr 0U, // VMOVNTDQmr 0U, // VMOVNTPDYmr 0U, // VMOVNTPDZ128mr 0U, // VMOVNTPDZ256mr 0U, // VMOVNTPDZmr 0U, // VMOVNTPDmr 0U, // VMOVNTPSYmr 0U, // VMOVNTPSZ128mr 0U, // VMOVNTPSZ256mr 0U, // VMOVNTPSZmr 0U, // VMOVNTPSmr 0U, // VMOVPDI2DIZmr 0U, // VMOVPDI2DIZrr 0U, // VMOVPDI2DImr 0U, // VMOVPDI2DIrr 0U, // VMOVPQI2QIZmr 0U, // VMOVPQI2QIZrr 0U, // VMOVPQI2QImr 0U, // VMOVPQI2QIrr 0U, // VMOVPQIto64Zmr 0U, // VMOVPQIto64Zrr 0U, // VMOVPQIto64mr 0U, // VMOVPQIto64rr 0U, // VMOVQI2PQIZrm 0U, // VMOVQI2PQIrm 0U, // VMOVSDZmr 0U, // VMOVSDZmrk 0U, // VMOVSDZrm 0U, // VMOVSDZrmk 0U, // VMOVSDZrmkz 0U, // VMOVSDZrr 0U, // VMOVSDZrr_REV 0U, // VMOVSDZrrk 0U, // VMOVSDZrrk_REV 0U, // VMOVSDZrrkz 0U, // VMOVSDZrrkz_REV 0U, // VMOVSDmr 0U, // VMOVSDrm 0U, // VMOVSDrr 0U, // VMOVSDrr_REV 0U, // VMOVSDto64Zmr 0U, // VMOVSDto64Zrr 0U, // VMOVSDto64mr 0U, // VMOVSDto64rr 0U, // VMOVSHDUPYrm 0U, // VMOVSHDUPYrr 0U, // VMOVSHDUPZ128rm 0U, // VMOVSHDUPZ128rmk 0U, // VMOVSHDUPZ128rmkz 0U, // VMOVSHDUPZ128rr 0U, // VMOVSHDUPZ128rrk 0U, // VMOVSHDUPZ128rrkz 0U, // VMOVSHDUPZ256rm 0U, // VMOVSHDUPZ256rmk 0U, // VMOVSHDUPZ256rmkz 0U, // VMOVSHDUPZ256rr 0U, // VMOVSHDUPZ256rrk 0U, // VMOVSHDUPZ256rrkz 0U, // VMOVSHDUPZrm 0U, // VMOVSHDUPZrmk 0U, // VMOVSHDUPZrmkz 0U, // VMOVSHDUPZrr 0U, // VMOVSHDUPZrrk 0U, // VMOVSHDUPZrrkz 0U, // VMOVSHDUPrm 0U, // VMOVSHDUPrr 0U, // VMOVSLDUPYrm 0U, // VMOVSLDUPYrr 0U, // VMOVSLDUPZ128rm 0U, // VMOVSLDUPZ128rmk 0U, // VMOVSLDUPZ128rmkz 0U, // VMOVSLDUPZ128rr 0U, // VMOVSLDUPZ128rrk 0U, // VMOVSLDUPZ128rrkz 0U, // VMOVSLDUPZ256rm 0U, // VMOVSLDUPZ256rmk 0U, // VMOVSLDUPZ256rmkz 0U, // VMOVSLDUPZ256rr 0U, // VMOVSLDUPZ256rrk 0U, // VMOVSLDUPZ256rrkz 0U, // VMOVSLDUPZrm 0U, // VMOVSLDUPZrmk 0U, // VMOVSLDUPZrmkz 0U, // VMOVSLDUPZrr 0U, // VMOVSLDUPZrrk 0U, // VMOVSLDUPZrrkz 0U, // VMOVSLDUPrm 0U, // VMOVSLDUPrr 0U, // VMOVSS2DIZmr 0U, // VMOVSS2DIZrr 0U, // VMOVSS2DImr 0U, // VMOVSS2DIrr 0U, // VMOVSSZmr 0U, // VMOVSSZmrk 0U, // VMOVSSZrm 0U, // VMOVSSZrmk 0U, // VMOVSSZrmkz 0U, // VMOVSSZrr 0U, // VMOVSSZrr_REV 0U, // VMOVSSZrrk 0U, // VMOVSSZrrk_REV 0U, // VMOVSSZrrkz 0U, // VMOVSSZrrkz_REV 0U, // VMOVSSmr 0U, // VMOVSSrm 0U, // VMOVSSrr 0U, // VMOVSSrr_REV 0U, // VMOVUPDYmr 0U, // VMOVUPDYrm 0U, // VMOVUPDYrr 0U, // VMOVUPDYrr_REV 0U, // VMOVUPDZ128mr 0U, // VMOVUPDZ128mrk 0U, // VMOVUPDZ128rm 0U, // VMOVUPDZ128rmk 0U, // VMOVUPDZ128rmkz 0U, // VMOVUPDZ128rr 0U, // VMOVUPDZ128rr_REV 0U, // VMOVUPDZ128rrk 0U, // VMOVUPDZ128rrk_REV 0U, // VMOVUPDZ128rrkz 0U, // VMOVUPDZ128rrkz_REV 0U, // VMOVUPDZ256mr 0U, // VMOVUPDZ256mrk 0U, // VMOVUPDZ256rm 0U, // VMOVUPDZ256rmk 0U, // VMOVUPDZ256rmkz 0U, // VMOVUPDZ256rr 0U, // VMOVUPDZ256rr_REV 0U, // VMOVUPDZ256rrk 0U, // VMOVUPDZ256rrk_REV 0U, // VMOVUPDZ256rrkz 0U, // VMOVUPDZ256rrkz_REV 0U, // VMOVUPDZmr 0U, // VMOVUPDZmrk 0U, // VMOVUPDZrm 0U, // VMOVUPDZrmk 0U, // VMOVUPDZrmkz 0U, // VMOVUPDZrr 0U, // VMOVUPDZrr_REV 0U, // VMOVUPDZrrk 0U, // VMOVUPDZrrk_REV 0U, // VMOVUPDZrrkz 0U, // VMOVUPDZrrkz_REV 0U, // VMOVUPDmr 0U, // VMOVUPDrm 0U, // VMOVUPDrr 0U, // VMOVUPDrr_REV 0U, // VMOVUPSYmr 0U, // VMOVUPSYrm 0U, // VMOVUPSYrr 0U, // VMOVUPSYrr_REV 0U, // VMOVUPSZ128mr 0U, // VMOVUPSZ128mrk 0U, // VMOVUPSZ128rm 0U, // VMOVUPSZ128rmk 0U, // VMOVUPSZ128rmkz 0U, // VMOVUPSZ128rr 0U, // VMOVUPSZ128rr_REV 0U, // VMOVUPSZ128rrk 0U, // VMOVUPSZ128rrk_REV 0U, // VMOVUPSZ128rrkz 0U, // VMOVUPSZ128rrkz_REV 0U, // VMOVUPSZ256mr 0U, // VMOVUPSZ256mrk 0U, // VMOVUPSZ256rm 0U, // VMOVUPSZ256rmk 0U, // VMOVUPSZ256rmkz 0U, // VMOVUPSZ256rr 0U, // VMOVUPSZ256rr_REV 0U, // VMOVUPSZ256rrk 0U, // VMOVUPSZ256rrk_REV 0U, // VMOVUPSZ256rrkz 0U, // VMOVUPSZ256rrkz_REV 0U, // VMOVUPSZmr 0U, // VMOVUPSZmrk 0U, // VMOVUPSZrm 0U, // VMOVUPSZrmk 0U, // VMOVUPSZrmkz 0U, // VMOVUPSZrr 0U, // VMOVUPSZrr_REV 0U, // VMOVUPSZrrk 0U, // VMOVUPSZrrk_REV 0U, // VMOVUPSZrrkz 0U, // VMOVUPSZrrkz_REV 0U, // VMOVUPSmr 0U, // VMOVUPSrm 0U, // VMOVUPSrr 0U, // VMOVUPSrr_REV 0U, // VMOVZPQILo2PQIZrr 0U, // VMOVZPQILo2PQIrr 0U, // VMPSADBWYrmi 0U, // VMPSADBWYrri 0U, // VMPSADBWrmi 0U, // VMPSADBWrri 0U, // VMPTRLDm 0U, // VMPTRSTm 0U, // VMREAD32mr 0U, // VMREAD32rr 0U, // VMREAD64mr 0U, // VMREAD64rr 0U, // VMRESUME 0U, // VMRUN32 0U, // VMRUN64 0U, // VMSAVE32 0U, // VMSAVE64 0U, // VMULPDYrm 0U, // VMULPDYrr 0U, // VMULPDZ128rm 0U, // VMULPDZ128rmb 0U, // VMULPDZ128rmbk 0U, // VMULPDZ128rmbkz 0U, // VMULPDZ128rmk 0U, // VMULPDZ128rmkz 0U, // VMULPDZ128rr 0U, // VMULPDZ128rrk 0U, // VMULPDZ128rrkz 0U, // VMULPDZ256rm 0U, // VMULPDZ256rmb 0U, // VMULPDZ256rmbk 0U, // VMULPDZ256rmbkz 0U, // VMULPDZ256rmk 0U, // VMULPDZ256rmkz 0U, // VMULPDZ256rr 0U, // VMULPDZ256rrk 0U, // VMULPDZ256rrkz 0U, // VMULPDZrm 0U, // VMULPDZrmb 0U, // VMULPDZrmbk 0U, // VMULPDZrmbkz 0U, // VMULPDZrmk 0U, // VMULPDZrmkz 0U, // VMULPDZrr 0U, // VMULPDZrrb 0U, // VMULPDZrrbk 0U, // VMULPDZrrbkz 0U, // VMULPDZrrk 0U, // VMULPDZrrkz 0U, // VMULPDrm 0U, // VMULPDrr 0U, // VMULPSYrm 0U, // VMULPSYrr 0U, // VMULPSZ128rm 0U, // VMULPSZ128rmb 0U, // VMULPSZ128rmbk 0U, // VMULPSZ128rmbkz 0U, // VMULPSZ128rmk 0U, // VMULPSZ128rmkz 0U, // VMULPSZ128rr 0U, // VMULPSZ128rrk 0U, // VMULPSZ128rrkz 0U, // VMULPSZ256rm 0U, // VMULPSZ256rmb 0U, // VMULPSZ256rmbk 0U, // VMULPSZ256rmbkz 0U, // VMULPSZ256rmk 0U, // VMULPSZ256rmkz 0U, // VMULPSZ256rr 0U, // VMULPSZ256rrk 0U, // VMULPSZ256rrkz 0U, // VMULPSZrm 0U, // VMULPSZrmb 0U, // VMULPSZrmbk 0U, // VMULPSZrmbkz 0U, // VMULPSZrmk 0U, // VMULPSZrmkz 0U, // VMULPSZrr 0U, // VMULPSZrrb 0U, // VMULPSZrrbk 0U, // VMULPSZrrbkz 0U, // VMULPSZrrk 0U, // VMULPSZrrkz 0U, // VMULPSrm 0U, // VMULPSrr 0U, // VMULSDZrm 0U, // VMULSDZrm_Int 0U, // VMULSDZrm_Intk 0U, // VMULSDZrm_Intkz 0U, // VMULSDZrr 0U, // VMULSDZrr_Int 0U, // VMULSDZrr_Intk 0U, // VMULSDZrr_Intkz 0U, // VMULSDZrrb_Int 0U, // VMULSDZrrb_Intk 0U, // VMULSDZrrb_Intkz 0U, // VMULSDrm 0U, // VMULSDrm_Int 0U, // VMULSDrr 0U, // VMULSDrr_Int 0U, // VMULSSZrm 0U, // VMULSSZrm_Int 0U, // VMULSSZrm_Intk 0U, // VMULSSZrm_Intkz 0U, // VMULSSZrr 0U, // VMULSSZrr_Int 0U, // VMULSSZrr_Intk 0U, // VMULSSZrr_Intkz 0U, // VMULSSZrrb_Int 0U, // VMULSSZrrb_Intk 0U, // VMULSSZrrb_Intkz 0U, // VMULSSrm 0U, // VMULSSrm_Int 0U, // VMULSSrr 0U, // VMULSSrr_Int 0U, // VMWRITE32rm 0U, // VMWRITE32rr 0U, // VMWRITE64rm 0U, // VMWRITE64rr 0U, // VMXOFF 0U, // VMXON 0U, // VORPDYrm 0U, // VORPDYrr 0U, // VORPDZ128rm 0U, // VORPDZ128rmb 0U, // VORPDZ128rmbk 0U, // VORPDZ128rmbkz 0U, // VORPDZ128rmk 0U, // VORPDZ128rmkz 0U, // VORPDZ128rr 0U, // VORPDZ128rrk 0U, // VORPDZ128rrkz 0U, // VORPDZ256rm 0U, // VORPDZ256rmb 0U, // VORPDZ256rmbk 0U, // VORPDZ256rmbkz 0U, // VORPDZ256rmk 0U, // VORPDZ256rmkz 0U, // VORPDZ256rr 0U, // VORPDZ256rrk 0U, // VORPDZ256rrkz 0U, // VORPDZrm 0U, // VORPDZrmb 0U, // VORPDZrmbk 0U, // VORPDZrmbkz 0U, // VORPDZrmk 0U, // VORPDZrmkz 0U, // VORPDZrr 0U, // VORPDZrrk 0U, // VORPDZrrkz 0U, // VORPDrm 0U, // VORPDrr 0U, // VORPSYrm 0U, // VORPSYrr 0U, // VORPSZ128rm 0U, // VORPSZ128rmb 0U, // VORPSZ128rmbk 0U, // VORPSZ128rmbkz 0U, // VORPSZ128rmk 0U, // VORPSZ128rmkz 0U, // VORPSZ128rr 0U, // VORPSZ128rrk 0U, // VORPSZ128rrkz 0U, // VORPSZ256rm 0U, // VORPSZ256rmb 0U, // VORPSZ256rmbk 0U, // VORPSZ256rmbkz 0U, // VORPSZ256rmk 0U, // VORPSZ256rmkz 0U, // VORPSZ256rr 0U, // VORPSZ256rrk 0U, // VORPSZ256rrkz 0U, // VORPSZrm 0U, // VORPSZrmb 0U, // VORPSZrmbk 0U, // VORPSZrmbkz 0U, // VORPSZrmk 0U, // VORPSZrmkz 0U, // VORPSZrr 0U, // VORPSZrrk 0U, // VORPSZrrkz 0U, // VORPSrm 0U, // VORPSrr 0U, // VP4DPWSSDSrm 0U, // VP4DPWSSDSrmk 0U, // VP4DPWSSDSrmkz 0U, // VP4DPWSSDrm 0U, // VP4DPWSSDrmk 0U, // VP4DPWSSDrmkz 0U, // VPABSBYrm 0U, // VPABSBYrr 0U, // VPABSBZ128rm 0U, // VPABSBZ128rmk 0U, // VPABSBZ128rmkz 0U, // VPABSBZ128rr 0U, // VPABSBZ128rrk 0U, // VPABSBZ128rrkz 0U, // VPABSBZ256rm 0U, // VPABSBZ256rmk 0U, // VPABSBZ256rmkz 0U, // VPABSBZ256rr 0U, // VPABSBZ256rrk 0U, // VPABSBZ256rrkz 0U, // VPABSBZrm 0U, // VPABSBZrmk 0U, // VPABSBZrmkz 0U, // VPABSBZrr 0U, // VPABSBZrrk 0U, // VPABSBZrrkz 0U, // VPABSBrm 0U, // VPABSBrr 0U, // VPABSDYrm 0U, // VPABSDYrr 0U, // VPABSDZ128rm 0U, // VPABSDZ128rmb 0U, // VPABSDZ128rmbk 0U, // VPABSDZ128rmbkz 0U, // VPABSDZ128rmk 0U, // VPABSDZ128rmkz 0U, // VPABSDZ128rr 0U, // VPABSDZ128rrk 0U, // VPABSDZ128rrkz 0U, // VPABSDZ256rm 0U, // VPABSDZ256rmb 0U, // VPABSDZ256rmbk 0U, // VPABSDZ256rmbkz 0U, // VPABSDZ256rmk 0U, // VPABSDZ256rmkz 0U, // VPABSDZ256rr 0U, // VPABSDZ256rrk 0U, // VPABSDZ256rrkz 0U, // VPABSDZrm 0U, // VPABSDZrmb 0U, // VPABSDZrmbk 0U, // VPABSDZrmbkz 0U, // VPABSDZrmk 0U, // VPABSDZrmkz 0U, // VPABSDZrr 0U, // VPABSDZrrk 0U, // VPABSDZrrkz 0U, // VPABSDrm 0U, // VPABSDrr 0U, // VPABSQZ128rm 0U, // VPABSQZ128rmb 0U, // VPABSQZ128rmbk 0U, // VPABSQZ128rmbkz 0U, // VPABSQZ128rmk 0U, // VPABSQZ128rmkz 0U, // VPABSQZ128rr 0U, // VPABSQZ128rrk 0U, // VPABSQZ128rrkz 0U, // VPABSQZ256rm 0U, // VPABSQZ256rmb 0U, // VPABSQZ256rmbk 0U, // VPABSQZ256rmbkz 0U, // VPABSQZ256rmk 0U, // VPABSQZ256rmkz 0U, // VPABSQZ256rr 0U, // VPABSQZ256rrk 0U, // VPABSQZ256rrkz 0U, // VPABSQZrm 0U, // VPABSQZrmb 0U, // VPABSQZrmbk 0U, // VPABSQZrmbkz 0U, // VPABSQZrmk 0U, // VPABSQZrmkz 0U, // VPABSQZrr 0U, // VPABSQZrrk 0U, // VPABSQZrrkz 0U, // VPABSWYrm 0U, // VPABSWYrr 0U, // VPABSWZ128rm 0U, // VPABSWZ128rmk 0U, // VPABSWZ128rmkz 0U, // VPABSWZ128rr 0U, // VPABSWZ128rrk 0U, // VPABSWZ128rrkz 0U, // VPABSWZ256rm 0U, // VPABSWZ256rmk 0U, // VPABSWZ256rmkz 0U, // VPABSWZ256rr 0U, // VPABSWZ256rrk 0U, // VPABSWZ256rrkz 0U, // VPABSWZrm 0U, // VPABSWZrmk 0U, // VPABSWZrmkz 0U, // VPABSWZrr 0U, // VPABSWZrrk 0U, // VPABSWZrrkz 0U, // VPABSWrm 0U, // VPABSWrr 0U, // VPACKSSDWYrm 0U, // VPACKSSDWYrr 0U, // VPACKSSDWZ128rm 0U, // VPACKSSDWZ128rmb 0U, // VPACKSSDWZ128rmbk 0U, // VPACKSSDWZ128rmbkz 0U, // VPACKSSDWZ128rmk 0U, // VPACKSSDWZ128rmkz 0U, // VPACKSSDWZ128rr 0U, // VPACKSSDWZ128rrk 0U, // VPACKSSDWZ128rrkz 0U, // VPACKSSDWZ256rm 0U, // VPACKSSDWZ256rmb 0U, // VPACKSSDWZ256rmbk 0U, // VPACKSSDWZ256rmbkz 0U, // VPACKSSDWZ256rmk 0U, // VPACKSSDWZ256rmkz 0U, // VPACKSSDWZ256rr 0U, // VPACKSSDWZ256rrk 0U, // VPACKSSDWZ256rrkz 0U, // VPACKSSDWZrm 0U, // VPACKSSDWZrmb 0U, // VPACKSSDWZrmbk 0U, // VPACKSSDWZrmbkz 0U, // VPACKSSDWZrmk 0U, // VPACKSSDWZrmkz 0U, // VPACKSSDWZrr 0U, // VPACKSSDWZrrk 0U, // VPACKSSDWZrrkz 0U, // VPACKSSDWrm 0U, // VPACKSSDWrr 0U, // VPACKSSWBYrm 0U, // VPACKSSWBYrr 0U, // VPACKSSWBZ128rm 0U, // VPACKSSWBZ128rmk 0U, // VPACKSSWBZ128rmkz 0U, // VPACKSSWBZ128rr 0U, // VPACKSSWBZ128rrk 0U, // VPACKSSWBZ128rrkz 0U, // VPACKSSWBZ256rm 0U, // VPACKSSWBZ256rmk 0U, // VPACKSSWBZ256rmkz 0U, // VPACKSSWBZ256rr 0U, // VPACKSSWBZ256rrk 0U, // VPACKSSWBZ256rrkz 0U, // VPACKSSWBZrm 0U, // VPACKSSWBZrmk 0U, // VPACKSSWBZrmkz 0U, // VPACKSSWBZrr 0U, // VPACKSSWBZrrk 0U, // VPACKSSWBZrrkz 0U, // VPACKSSWBrm 0U, // VPACKSSWBrr 0U, // VPACKUSDWYrm 0U, // VPACKUSDWYrr 0U, // VPACKUSDWZ128rm 0U, // VPACKUSDWZ128rmb 0U, // VPACKUSDWZ128rmbk 0U, // VPACKUSDWZ128rmbkz 0U, // VPACKUSDWZ128rmk 0U, // VPACKUSDWZ128rmkz 0U, // VPACKUSDWZ128rr 0U, // VPACKUSDWZ128rrk 0U, // VPACKUSDWZ128rrkz 0U, // VPACKUSDWZ256rm 0U, // VPACKUSDWZ256rmb 0U, // VPACKUSDWZ256rmbk 0U, // VPACKUSDWZ256rmbkz 0U, // VPACKUSDWZ256rmk 0U, // VPACKUSDWZ256rmkz 0U, // VPACKUSDWZ256rr 0U, // VPACKUSDWZ256rrk 0U, // VPACKUSDWZ256rrkz 0U, // VPACKUSDWZrm 0U, // VPACKUSDWZrmb 0U, // VPACKUSDWZrmbk 0U, // VPACKUSDWZrmbkz 0U, // VPACKUSDWZrmk 0U, // VPACKUSDWZrmkz 0U, // VPACKUSDWZrr 0U, // VPACKUSDWZrrk 0U, // VPACKUSDWZrrkz 0U, // VPACKUSDWrm 0U, // VPACKUSDWrr 0U, // VPACKUSWBYrm 0U, // VPACKUSWBYrr 0U, // VPACKUSWBZ128rm 0U, // VPACKUSWBZ128rmk 0U, // VPACKUSWBZ128rmkz 0U, // VPACKUSWBZ128rr 0U, // VPACKUSWBZ128rrk 0U, // VPACKUSWBZ128rrkz 0U, // VPACKUSWBZ256rm 0U, // VPACKUSWBZ256rmk 0U, // VPACKUSWBZ256rmkz 0U, // VPACKUSWBZ256rr 0U, // VPACKUSWBZ256rrk 0U, // VPACKUSWBZ256rrkz 0U, // VPACKUSWBZrm 0U, // VPACKUSWBZrmk 0U, // VPACKUSWBZrmkz 0U, // VPACKUSWBZrr 0U, // VPACKUSWBZrrk 0U, // VPACKUSWBZrrkz 0U, // VPACKUSWBrm 0U, // VPACKUSWBrr 0U, // VPADDBYrm 0U, // VPADDBYrr 0U, // VPADDBZ128rm 0U, // VPADDBZ128rmk 0U, // VPADDBZ128rmkz 0U, // VPADDBZ128rr 0U, // VPADDBZ128rrk 0U, // VPADDBZ128rrkz 0U, // VPADDBZ256rm 0U, // VPADDBZ256rmk 0U, // VPADDBZ256rmkz 0U, // VPADDBZ256rr 0U, // VPADDBZ256rrk 0U, // VPADDBZ256rrkz 0U, // VPADDBZrm 0U, // VPADDBZrmk 0U, // VPADDBZrmkz 0U, // VPADDBZrr 0U, // VPADDBZrrk 0U, // VPADDBZrrkz 0U, // VPADDBrm 0U, // VPADDBrr 0U, // VPADDDYrm 0U, // VPADDDYrr 0U, // VPADDDZ128rm 0U, // VPADDDZ128rmb 0U, // VPADDDZ128rmbk 0U, // VPADDDZ128rmbkz 0U, // VPADDDZ128rmk 0U, // VPADDDZ128rmkz 0U, // VPADDDZ128rr 0U, // VPADDDZ128rrk 0U, // VPADDDZ128rrkz 0U, // VPADDDZ256rm 0U, // VPADDDZ256rmb 0U, // VPADDDZ256rmbk 0U, // VPADDDZ256rmbkz 0U, // VPADDDZ256rmk 0U, // VPADDDZ256rmkz 0U, // VPADDDZ256rr 0U, // VPADDDZ256rrk 0U, // VPADDDZ256rrkz 0U, // VPADDDZrm 0U, // VPADDDZrmb 0U, // VPADDDZrmbk 0U, // VPADDDZrmbkz 0U, // VPADDDZrmk 0U, // VPADDDZrmkz 0U, // VPADDDZrr 0U, // VPADDDZrrk 0U, // VPADDDZrrkz 0U, // VPADDDrm 0U, // VPADDDrr 0U, // VPADDQYrm 0U, // VPADDQYrr 0U, // VPADDQZ128rm 0U, // VPADDQZ128rmb 0U, // VPADDQZ128rmbk 0U, // VPADDQZ128rmbkz 0U, // VPADDQZ128rmk 0U, // VPADDQZ128rmkz 0U, // VPADDQZ128rr 0U, // VPADDQZ128rrk 0U, // VPADDQZ128rrkz 0U, // VPADDQZ256rm 0U, // VPADDQZ256rmb 0U, // VPADDQZ256rmbk 0U, // VPADDQZ256rmbkz 0U, // VPADDQZ256rmk 0U, // VPADDQZ256rmkz 0U, // VPADDQZ256rr 0U, // VPADDQZ256rrk 0U, // VPADDQZ256rrkz 0U, // VPADDQZrm 0U, // VPADDQZrmb 0U, // VPADDQZrmbk 0U, // VPADDQZrmbkz 0U, // VPADDQZrmk 0U, // VPADDQZrmkz 0U, // VPADDQZrr 0U, // VPADDQZrrk 0U, // VPADDQZrrkz 0U, // VPADDQrm 0U, // VPADDQrr 0U, // VPADDSBYrm 0U, // VPADDSBYrr 0U, // VPADDSBZ128rm 0U, // VPADDSBZ128rmk 0U, // VPADDSBZ128rmkz 0U, // VPADDSBZ128rr 0U, // VPADDSBZ128rrk 0U, // VPADDSBZ128rrkz 0U, // VPADDSBZ256rm 0U, // VPADDSBZ256rmk 0U, // VPADDSBZ256rmkz 0U, // VPADDSBZ256rr 0U, // VPADDSBZ256rrk 0U, // VPADDSBZ256rrkz 0U, // VPADDSBZrm 0U, // VPADDSBZrmk 0U, // VPADDSBZrmkz 0U, // VPADDSBZrr 0U, // VPADDSBZrrk 0U, // VPADDSBZrrkz 0U, // VPADDSBrm 0U, // VPADDSBrr 0U, // VPADDSWYrm 0U, // VPADDSWYrr 0U, // VPADDSWZ128rm 0U, // VPADDSWZ128rmk 0U, // VPADDSWZ128rmkz 0U, // VPADDSWZ128rr 0U, // VPADDSWZ128rrk 0U, // VPADDSWZ128rrkz 0U, // VPADDSWZ256rm 0U, // VPADDSWZ256rmk 0U, // VPADDSWZ256rmkz 0U, // VPADDSWZ256rr 0U, // VPADDSWZ256rrk 0U, // VPADDSWZ256rrkz 0U, // VPADDSWZrm 0U, // VPADDSWZrmk 0U, // VPADDSWZrmkz 0U, // VPADDSWZrr 0U, // VPADDSWZrrk 0U, // VPADDSWZrrkz 0U, // VPADDSWrm 0U, // VPADDSWrr 0U, // VPADDUSBYrm 0U, // VPADDUSBYrr 0U, // VPADDUSBZ128rm 0U, // VPADDUSBZ128rmk 0U, // VPADDUSBZ128rmkz 0U, // VPADDUSBZ128rr 0U, // VPADDUSBZ128rrk 0U, // VPADDUSBZ128rrkz 0U, // VPADDUSBZ256rm 0U, // VPADDUSBZ256rmk 0U, // VPADDUSBZ256rmkz 0U, // VPADDUSBZ256rr 0U, // VPADDUSBZ256rrk 0U, // VPADDUSBZ256rrkz 0U, // VPADDUSBZrm 0U, // VPADDUSBZrmk 0U, // VPADDUSBZrmkz 0U, // VPADDUSBZrr 0U, // VPADDUSBZrrk 0U, // VPADDUSBZrrkz 0U, // VPADDUSBrm 0U, // VPADDUSBrr 0U, // VPADDUSWYrm 0U, // VPADDUSWYrr 0U, // VPADDUSWZ128rm 0U, // VPADDUSWZ128rmk 0U, // VPADDUSWZ128rmkz 0U, // VPADDUSWZ128rr 0U, // VPADDUSWZ128rrk 0U, // VPADDUSWZ128rrkz 0U, // VPADDUSWZ256rm 0U, // VPADDUSWZ256rmk 0U, // VPADDUSWZ256rmkz 0U, // VPADDUSWZ256rr 0U, // VPADDUSWZ256rrk 0U, // VPADDUSWZ256rrkz 0U, // VPADDUSWZrm 0U, // VPADDUSWZrmk 0U, // VPADDUSWZrmkz 0U, // VPADDUSWZrr 0U, // VPADDUSWZrrk 0U, // VPADDUSWZrrkz 0U, // VPADDUSWrm 0U, // VPADDUSWrr 0U, // VPADDWYrm 0U, // VPADDWYrr 0U, // VPADDWZ128rm 0U, // VPADDWZ128rmk 0U, // VPADDWZ128rmkz 0U, // VPADDWZ128rr 0U, // VPADDWZ128rrk 0U, // VPADDWZ128rrkz 0U, // VPADDWZ256rm 0U, // VPADDWZ256rmk 0U, // VPADDWZ256rmkz 0U, // VPADDWZ256rr 0U, // VPADDWZ256rrk 0U, // VPADDWZ256rrkz 0U, // VPADDWZrm 0U, // VPADDWZrmk 0U, // VPADDWZrmkz 0U, // VPADDWZrr 0U, // VPADDWZrrk 0U, // VPADDWZrrkz 0U, // VPADDWrm 0U, // VPADDWrr 0U, // VPALIGNRYrmi 0U, // VPALIGNRYrri 0U, // VPALIGNRZ128rmi 0U, // VPALIGNRZ128rmik 0U, // VPALIGNRZ128rmikz 0U, // VPALIGNRZ128rri 0U, // VPALIGNRZ128rrik 3U, // VPALIGNRZ128rrikz 0U, // VPALIGNRZ256rmi 0U, // VPALIGNRZ256rmik 0U, // VPALIGNRZ256rmikz 0U, // VPALIGNRZ256rri 0U, // VPALIGNRZ256rrik 3U, // VPALIGNRZ256rrikz 0U, // VPALIGNRZrmi 0U, // VPALIGNRZrmik 0U, // VPALIGNRZrmikz 0U, // VPALIGNRZrri 0U, // VPALIGNRZrrik 3U, // VPALIGNRZrrikz 0U, // VPALIGNRrmi 0U, // VPALIGNRrri 0U, // VPANDDZ128rm 0U, // VPANDDZ128rmb 0U, // VPANDDZ128rmbk 0U, // VPANDDZ128rmbkz 0U, // VPANDDZ128rmk 0U, // VPANDDZ128rmkz 0U, // VPANDDZ128rr 0U, // VPANDDZ128rrk 0U, // VPANDDZ128rrkz 0U, // VPANDDZ256rm 0U, // VPANDDZ256rmb 0U, // VPANDDZ256rmbk 0U, // VPANDDZ256rmbkz 0U, // VPANDDZ256rmk 0U, // VPANDDZ256rmkz 0U, // VPANDDZ256rr 0U, // VPANDDZ256rrk 0U, // VPANDDZ256rrkz 0U, // VPANDDZrm 0U, // VPANDDZrmb 0U, // VPANDDZrmbk 0U, // VPANDDZrmbkz 0U, // VPANDDZrmk 0U, // VPANDDZrmkz 0U, // VPANDDZrr 0U, // VPANDDZrrk 0U, // VPANDDZrrkz 0U, // VPANDNDZ128rm 0U, // VPANDNDZ128rmb 0U, // VPANDNDZ128rmbk 0U, // VPANDNDZ128rmbkz 0U, // VPANDNDZ128rmk 0U, // VPANDNDZ128rmkz 0U, // VPANDNDZ128rr 0U, // VPANDNDZ128rrk 0U, // VPANDNDZ128rrkz 0U, // VPANDNDZ256rm 0U, // VPANDNDZ256rmb 0U, // VPANDNDZ256rmbk 0U, // VPANDNDZ256rmbkz 0U, // VPANDNDZ256rmk 0U, // VPANDNDZ256rmkz 0U, // VPANDNDZ256rr 0U, // VPANDNDZ256rrk 0U, // VPANDNDZ256rrkz 0U, // VPANDNDZrm 0U, // VPANDNDZrmb 0U, // VPANDNDZrmbk 0U, // VPANDNDZrmbkz 0U, // VPANDNDZrmk 0U, // VPANDNDZrmkz 0U, // VPANDNDZrr 0U, // VPANDNDZrrk 0U, // VPANDNDZrrkz 0U, // VPANDNQZ128rm 0U, // VPANDNQZ128rmb 0U, // VPANDNQZ128rmbk 0U, // VPANDNQZ128rmbkz 0U, // VPANDNQZ128rmk 0U, // VPANDNQZ128rmkz 0U, // VPANDNQZ128rr 0U, // VPANDNQZ128rrk 0U, // VPANDNQZ128rrkz 0U, // VPANDNQZ256rm 0U, // VPANDNQZ256rmb 0U, // VPANDNQZ256rmbk 0U, // VPANDNQZ256rmbkz 0U, // VPANDNQZ256rmk 0U, // VPANDNQZ256rmkz 0U, // VPANDNQZ256rr 0U, // VPANDNQZ256rrk 0U, // VPANDNQZ256rrkz 0U, // VPANDNQZrm 0U, // VPANDNQZrmb 0U, // VPANDNQZrmbk 0U, // VPANDNQZrmbkz 0U, // VPANDNQZrmk 0U, // VPANDNQZrmkz 0U, // VPANDNQZrr 0U, // VPANDNQZrrk 0U, // VPANDNQZrrkz 0U, // VPANDNYrm 0U, // VPANDNYrr 0U, // VPANDNrm 0U, // VPANDNrr 0U, // VPANDQZ128rm 0U, // VPANDQZ128rmb 0U, // VPANDQZ128rmbk 0U, // VPANDQZ128rmbkz 0U, // VPANDQZ128rmk 0U, // VPANDQZ128rmkz 0U, // VPANDQZ128rr 0U, // VPANDQZ128rrk 0U, // VPANDQZ128rrkz 0U, // VPANDQZ256rm 0U, // VPANDQZ256rmb 0U, // VPANDQZ256rmbk 0U, // VPANDQZ256rmbkz 0U, // VPANDQZ256rmk 0U, // VPANDQZ256rmkz 0U, // VPANDQZ256rr 0U, // VPANDQZ256rrk 0U, // VPANDQZ256rrkz 0U, // VPANDQZrm 0U, // VPANDQZrmb 0U, // VPANDQZrmbk 0U, // VPANDQZrmbkz 0U, // VPANDQZrmk 0U, // VPANDQZrmkz 0U, // VPANDQZrr 0U, // VPANDQZrrk 0U, // VPANDQZrrkz 0U, // VPANDYrm 0U, // VPANDYrr 0U, // VPANDrm 0U, // VPANDrr 0U, // VPAVGBYrm 0U, // VPAVGBYrr 0U, // VPAVGBZ128rm 0U, // VPAVGBZ128rmk 0U, // VPAVGBZ128rmkz 0U, // VPAVGBZ128rr 0U, // VPAVGBZ128rrk 0U, // VPAVGBZ128rrkz 0U, // VPAVGBZ256rm 0U, // VPAVGBZ256rmk 0U, // VPAVGBZ256rmkz 0U, // VPAVGBZ256rr 0U, // VPAVGBZ256rrk 0U, // VPAVGBZ256rrkz 0U, // VPAVGBZrm 0U, // VPAVGBZrmk 0U, // VPAVGBZrmkz 0U, // VPAVGBZrr 0U, // VPAVGBZrrk 0U, // VPAVGBZrrkz 0U, // VPAVGBrm 0U, // VPAVGBrr 0U, // VPAVGWYrm 0U, // VPAVGWYrr 0U, // VPAVGWZ128rm 0U, // VPAVGWZ128rmk 0U, // VPAVGWZ128rmkz 0U, // VPAVGWZ128rr 0U, // VPAVGWZ128rrk 0U, // VPAVGWZ128rrkz 0U, // VPAVGWZ256rm 0U, // VPAVGWZ256rmk 0U, // VPAVGWZ256rmkz 0U, // VPAVGWZ256rr 0U, // VPAVGWZ256rrk 0U, // VPAVGWZ256rrkz 0U, // VPAVGWZrm 0U, // VPAVGWZrmk 0U, // VPAVGWZrmkz 0U, // VPAVGWZrr 0U, // VPAVGWZrrk 0U, // VPAVGWZrrkz 0U, // VPAVGWrm 0U, // VPAVGWrr 0U, // VPBLENDDYrmi 0U, // VPBLENDDYrri 0U, // VPBLENDDrmi 0U, // VPBLENDDrri 0U, // VPBLENDMBZ128rm 0U, // VPBLENDMBZ128rmk 0U, // VPBLENDMBZ128rmkz 0U, // VPBLENDMBZ128rr 0U, // VPBLENDMBZ128rrk 0U, // VPBLENDMBZ128rrkz 0U, // VPBLENDMBZ256rm 0U, // VPBLENDMBZ256rmk 0U, // VPBLENDMBZ256rmkz 0U, // VPBLENDMBZ256rr 0U, // VPBLENDMBZ256rrk 0U, // VPBLENDMBZ256rrkz 0U, // VPBLENDMBZrm 0U, // VPBLENDMBZrmk 0U, // VPBLENDMBZrmkz 0U, // VPBLENDMBZrr 0U, // VPBLENDMBZrrk 0U, // VPBLENDMBZrrkz 0U, // VPBLENDMDZ128rm 0U, // VPBLENDMDZ128rmb 0U, // VPBLENDMDZ128rmbk 0U, // VPBLENDMDZ128rmbkz 0U, // VPBLENDMDZ128rmk 0U, // VPBLENDMDZ128rmkz 0U, // VPBLENDMDZ128rr 0U, // VPBLENDMDZ128rrk 0U, // VPBLENDMDZ128rrkz 0U, // VPBLENDMDZ256rm 0U, // VPBLENDMDZ256rmb 0U, // VPBLENDMDZ256rmbk 0U, // VPBLENDMDZ256rmbkz 0U, // VPBLENDMDZ256rmk 0U, // VPBLENDMDZ256rmkz 0U, // VPBLENDMDZ256rr 0U, // VPBLENDMDZ256rrk 0U, // VPBLENDMDZ256rrkz 0U, // VPBLENDMDZrm 0U, // VPBLENDMDZrmb 0U, // VPBLENDMDZrmbk 0U, // VPBLENDMDZrmbkz 0U, // VPBLENDMDZrmk 0U, // VPBLENDMDZrmkz 0U, // VPBLENDMDZrr 0U, // VPBLENDMDZrrk 0U, // VPBLENDMDZrrkz 0U, // VPBLENDMQZ128rm 0U, // VPBLENDMQZ128rmb 0U, // VPBLENDMQZ128rmbk 0U, // VPBLENDMQZ128rmbkz 0U, // VPBLENDMQZ128rmk 0U, // VPBLENDMQZ128rmkz 0U, // VPBLENDMQZ128rr 0U, // VPBLENDMQZ128rrk 0U, // VPBLENDMQZ128rrkz 0U, // VPBLENDMQZ256rm 0U, // VPBLENDMQZ256rmb 0U, // VPBLENDMQZ256rmbk 0U, // VPBLENDMQZ256rmbkz 0U, // VPBLENDMQZ256rmk 0U, // VPBLENDMQZ256rmkz 0U, // VPBLENDMQZ256rr 0U, // VPBLENDMQZ256rrk 0U, // VPBLENDMQZ256rrkz 0U, // VPBLENDMQZrm 0U, // VPBLENDMQZrmb 0U, // VPBLENDMQZrmbk 0U, // VPBLENDMQZrmbkz 0U, // VPBLENDMQZrmk 0U, // VPBLENDMQZrmkz 0U, // VPBLENDMQZrr 0U, // VPBLENDMQZrrk 0U, // VPBLENDMQZrrkz 0U, // VPBLENDMWZ128rm 0U, // VPBLENDMWZ128rmk 0U, // VPBLENDMWZ128rmkz 0U, // VPBLENDMWZ128rr 0U, // VPBLENDMWZ128rrk 0U, // VPBLENDMWZ128rrkz 0U, // VPBLENDMWZ256rm 0U, // VPBLENDMWZ256rmk 0U, // VPBLENDMWZ256rmkz 0U, // VPBLENDMWZ256rr 0U, // VPBLENDMWZ256rrk 0U, // VPBLENDMWZ256rrkz 0U, // VPBLENDMWZrm 0U, // VPBLENDMWZrmk 0U, // VPBLENDMWZrmkz 0U, // VPBLENDMWZrr 0U, // VPBLENDMWZrrk 0U, // VPBLENDMWZrrkz 0U, // VPBLENDVBYrm 0U, // VPBLENDVBYrr 0U, // VPBLENDVBrm 0U, // VPBLENDVBrr 0U, // VPBLENDWYrmi 0U, // VPBLENDWYrri 0U, // VPBLENDWrmi 0U, // VPBLENDWrri 0U, // VPBROADCASTBYrm 0U, // VPBROADCASTBYrr 0U, // VPBROADCASTBZ128m 0U, // VPBROADCASTBZ128mk 0U, // VPBROADCASTBZ128mkz 0U, // VPBROADCASTBZ128r 0U, // VPBROADCASTBZ128rk 0U, // VPBROADCASTBZ128rkz 0U, // VPBROADCASTBZ256m 0U, // VPBROADCASTBZ256mk 0U, // VPBROADCASTBZ256mkz 0U, // VPBROADCASTBZ256r 0U, // VPBROADCASTBZ256rk 0U, // VPBROADCASTBZ256rkz 0U, // VPBROADCASTBZm 0U, // VPBROADCASTBZmk 0U, // VPBROADCASTBZmkz 0U, // VPBROADCASTBZr 0U, // VPBROADCASTBZrk 0U, // VPBROADCASTBZrkz 0U, // VPBROADCASTBrZ128r 0U, // VPBROADCASTBrZ128rk 0U, // VPBROADCASTBrZ128rkz 0U, // VPBROADCASTBrZ256r 0U, // VPBROADCASTBrZ256rk 0U, // VPBROADCASTBrZ256rkz 0U, // VPBROADCASTBrZr 0U, // VPBROADCASTBrZrk 0U, // VPBROADCASTBrZrkz 0U, // VPBROADCASTBrm 0U, // VPBROADCASTBrr 0U, // VPBROADCASTDYrm 0U, // VPBROADCASTDYrr 0U, // VPBROADCASTDZ128m 0U, // VPBROADCASTDZ128mk 0U, // VPBROADCASTDZ128mkz 0U, // VPBROADCASTDZ128r 0U, // VPBROADCASTDZ128rk 0U, // VPBROADCASTDZ128rkz 0U, // VPBROADCASTDZ256m 0U, // VPBROADCASTDZ256mk 0U, // VPBROADCASTDZ256mkz 0U, // VPBROADCASTDZ256r 0U, // VPBROADCASTDZ256rk 0U, // VPBROADCASTDZ256rkz 0U, // VPBROADCASTDZm 0U, // VPBROADCASTDZmk 0U, // VPBROADCASTDZmkz 0U, // VPBROADCASTDZr 0U, // VPBROADCASTDZrk 0U, // VPBROADCASTDZrkz 0U, // VPBROADCASTDrZ128r 0U, // VPBROADCASTDrZ128rk 0U, // VPBROADCASTDrZ128rkz 0U, // VPBROADCASTDrZ256r 0U, // VPBROADCASTDrZ256rk 0U, // VPBROADCASTDrZ256rkz 0U, // VPBROADCASTDrZr 0U, // VPBROADCASTDrZrk 0U, // VPBROADCASTDrZrkz 0U, // VPBROADCASTDrm 0U, // VPBROADCASTDrr 0U, // VPBROADCASTMB2QZ128rr 0U, // VPBROADCASTMB2QZ256rr 0U, // VPBROADCASTMB2QZrr 0U, // VPBROADCASTMW2DZ128rr 0U, // VPBROADCASTMW2DZ256rr 0U, // VPBROADCASTMW2DZrr 0U, // VPBROADCASTQYrm 0U, // VPBROADCASTQYrr 0U, // VPBROADCASTQZ128m 0U, // VPBROADCASTQZ128mk 0U, // VPBROADCASTQZ128mkz 0U, // VPBROADCASTQZ128r 0U, // VPBROADCASTQZ128rk 0U, // VPBROADCASTQZ128rkz 0U, // VPBROADCASTQZ256m 0U, // VPBROADCASTQZ256mk 0U, // VPBROADCASTQZ256mkz 0U, // VPBROADCASTQZ256r 0U, // VPBROADCASTQZ256rk 0U, // VPBROADCASTQZ256rkz 0U, // VPBROADCASTQZm 0U, // VPBROADCASTQZmk 0U, // VPBROADCASTQZmkz 0U, // VPBROADCASTQZr 0U, // VPBROADCASTQZrk 0U, // VPBROADCASTQZrkz 0U, // VPBROADCASTQrZ128r 0U, // VPBROADCASTQrZ128rk 0U, // VPBROADCASTQrZ128rkz 0U, // VPBROADCASTQrZ256r 0U, // VPBROADCASTQrZ256rk 0U, // VPBROADCASTQrZ256rkz 0U, // VPBROADCASTQrZr 0U, // VPBROADCASTQrZrk 0U, // VPBROADCASTQrZrkz 0U, // VPBROADCASTQrm 0U, // VPBROADCASTQrr 0U, // VPBROADCASTWYrm 0U, // VPBROADCASTWYrr 0U, // VPBROADCASTWZ128m 0U, // VPBROADCASTWZ128mk 0U, // VPBROADCASTWZ128mkz 0U, // VPBROADCASTWZ128r 0U, // VPBROADCASTWZ128rk 0U, // VPBROADCASTWZ128rkz 0U, // VPBROADCASTWZ256m 0U, // VPBROADCASTWZ256mk 0U, // VPBROADCASTWZ256mkz 0U, // VPBROADCASTWZ256r 0U, // VPBROADCASTWZ256rk 0U, // VPBROADCASTWZ256rkz 0U, // VPBROADCASTWZm 0U, // VPBROADCASTWZmk 0U, // VPBROADCASTWZmkz 0U, // VPBROADCASTWZr 0U, // VPBROADCASTWZrk 0U, // VPBROADCASTWZrkz 0U, // VPBROADCASTWrZ128r 0U, // VPBROADCASTWrZ128rk 0U, // VPBROADCASTWrZ128rkz 0U, // VPBROADCASTWrZ256r 0U, // VPBROADCASTWrZ256rk 0U, // VPBROADCASTWrZ256rkz 0U, // VPBROADCASTWrZr 0U, // VPBROADCASTWrZrk 0U, // VPBROADCASTWrZrkz 0U, // VPBROADCASTWrm 0U, // VPBROADCASTWrr 0U, // VPCLMULQDQYrm 0U, // VPCLMULQDQYrr 0U, // VPCLMULQDQZ128rm 0U, // VPCLMULQDQZ128rr 0U, // VPCLMULQDQZ256rm 0U, // VPCLMULQDQZ256rr 0U, // VPCLMULQDQZrm 0U, // VPCLMULQDQZrr 0U, // VPCLMULQDQrm 0U, // VPCLMULQDQrr 0U, // VPCMOVYrmr 0U, // VPCMOVYrrm 0U, // VPCMOVYrrr 0U, // VPCMOVYrrr_REV 0U, // VPCMOVrmr 0U, // VPCMOVrrm 0U, // VPCMOVrrr 0U, // VPCMOVrrr_REV 0U, // VPCMPBZ128rmi 0U, // VPCMPBZ128rmi_alt 0U, // VPCMPBZ128rmik 0U, // VPCMPBZ128rmik_alt 0U, // VPCMPBZ128rri 0U, // VPCMPBZ128rri_alt 1U, // VPCMPBZ128rrik 1U, // VPCMPBZ128rrik_alt 0U, // VPCMPBZ256rmi 0U, // VPCMPBZ256rmi_alt 0U, // VPCMPBZ256rmik 0U, // VPCMPBZ256rmik_alt 0U, // VPCMPBZ256rri 0U, // VPCMPBZ256rri_alt 1U, // VPCMPBZ256rrik 1U, // VPCMPBZ256rrik_alt 0U, // VPCMPBZrmi 0U, // VPCMPBZrmi_alt 0U, // VPCMPBZrmik 0U, // VPCMPBZrmik_alt 0U, // VPCMPBZrri 0U, // VPCMPBZrri_alt 1U, // VPCMPBZrrik 1U, // VPCMPBZrrik_alt 0U, // VPCMPDZ128rmi 0U, // VPCMPDZ128rmi_alt 0U, // VPCMPDZ128rmib 0U, // VPCMPDZ128rmib_alt 1U, // VPCMPDZ128rmibk 1U, // VPCMPDZ128rmibk_alt 0U, // VPCMPDZ128rmik 0U, // VPCMPDZ128rmik_alt 0U, // VPCMPDZ128rri 0U, // VPCMPDZ128rri_alt 1U, // VPCMPDZ128rrik 1U, // VPCMPDZ128rrik_alt 0U, // VPCMPDZ256rmi 0U, // VPCMPDZ256rmi_alt 0U, // VPCMPDZ256rmib 0U, // VPCMPDZ256rmib_alt 1U, // VPCMPDZ256rmibk 1U, // VPCMPDZ256rmibk_alt 0U, // VPCMPDZ256rmik 0U, // VPCMPDZ256rmik_alt 0U, // VPCMPDZ256rri 0U, // VPCMPDZ256rri_alt 1U, // VPCMPDZ256rrik 1U, // VPCMPDZ256rrik_alt 0U, // VPCMPDZrmi 0U, // VPCMPDZrmi_alt 0U, // VPCMPDZrmib 0U, // VPCMPDZrmib_alt 1U, // VPCMPDZrmibk 1U, // VPCMPDZrmibk_alt 0U, // VPCMPDZrmik 0U, // VPCMPDZrmik_alt 0U, // VPCMPDZrri 0U, // VPCMPDZrri_alt 1U, // VPCMPDZrrik 1U, // VPCMPDZrrik_alt 0U, // VPCMPEQBYrm 0U, // VPCMPEQBYrr 0U, // VPCMPEQBZ128rm 0U, // VPCMPEQBZ128rmk 0U, // VPCMPEQBZ128rr 0U, // VPCMPEQBZ128rrk 0U, // VPCMPEQBZ256rm 0U, // VPCMPEQBZ256rmk 0U, // VPCMPEQBZ256rr 0U, // VPCMPEQBZ256rrk 0U, // VPCMPEQBZrm 0U, // VPCMPEQBZrmk 0U, // VPCMPEQBZrr 0U, // VPCMPEQBZrrk 0U, // VPCMPEQBrm 0U, // VPCMPEQBrr 0U, // VPCMPEQDYrm 0U, // VPCMPEQDYrr 0U, // VPCMPEQDZ128rm 0U, // VPCMPEQDZ128rmb 0U, // VPCMPEQDZ128rmbk 0U, // VPCMPEQDZ128rmk 0U, // VPCMPEQDZ128rr 0U, // VPCMPEQDZ128rrk 0U, // VPCMPEQDZ256rm 0U, // VPCMPEQDZ256rmb 0U, // VPCMPEQDZ256rmbk 0U, // VPCMPEQDZ256rmk 0U, // VPCMPEQDZ256rr 0U, // VPCMPEQDZ256rrk 0U, // VPCMPEQDZrm 0U, // VPCMPEQDZrmb 0U, // VPCMPEQDZrmbk 0U, // VPCMPEQDZrmk 0U, // VPCMPEQDZrr 0U, // VPCMPEQDZrrk 0U, // VPCMPEQDrm 0U, // VPCMPEQDrr 0U, // VPCMPEQQYrm 0U, // VPCMPEQQYrr 0U, // VPCMPEQQZ128rm 0U, // VPCMPEQQZ128rmb 0U, // VPCMPEQQZ128rmbk 0U, // VPCMPEQQZ128rmk 0U, // VPCMPEQQZ128rr 0U, // VPCMPEQQZ128rrk 0U, // VPCMPEQQZ256rm 0U, // VPCMPEQQZ256rmb 0U, // VPCMPEQQZ256rmbk 0U, // VPCMPEQQZ256rmk 0U, // VPCMPEQQZ256rr 0U, // VPCMPEQQZ256rrk 0U, // VPCMPEQQZrm 0U, // VPCMPEQQZrmb 0U, // VPCMPEQQZrmbk 0U, // VPCMPEQQZrmk 0U, // VPCMPEQQZrr 0U, // VPCMPEQQZrrk 0U, // VPCMPEQQrm 0U, // VPCMPEQQrr 0U, // VPCMPEQWYrm 0U, // VPCMPEQWYrr 0U, // VPCMPEQWZ128rm 0U, // VPCMPEQWZ128rmk 0U, // VPCMPEQWZ128rr 0U, // VPCMPEQWZ128rrk 0U, // VPCMPEQWZ256rm 0U, // VPCMPEQWZ256rmk 0U, // VPCMPEQWZ256rr 0U, // VPCMPEQWZ256rrk 0U, // VPCMPEQWZrm 0U, // VPCMPEQWZrmk 0U, // VPCMPEQWZrr 0U, // VPCMPEQWZrrk 0U, // VPCMPEQWrm 0U, // VPCMPEQWrr 0U, // VPCMPESTRIrm 0U, // VPCMPESTRIrr 0U, // VPCMPESTRMrm 0U, // VPCMPESTRMrr 0U, // VPCMPGTBYrm 0U, // VPCMPGTBYrr 0U, // VPCMPGTBZ128rm 0U, // VPCMPGTBZ128rmk 0U, // VPCMPGTBZ128rr 0U, // VPCMPGTBZ128rrk 0U, // VPCMPGTBZ256rm 0U, // VPCMPGTBZ256rmk 0U, // VPCMPGTBZ256rr 0U, // VPCMPGTBZ256rrk 0U, // VPCMPGTBZrm 0U, // VPCMPGTBZrmk 0U, // VPCMPGTBZrr 0U, // VPCMPGTBZrrk 0U, // VPCMPGTBrm 0U, // VPCMPGTBrr 0U, // VPCMPGTDYrm 0U, // VPCMPGTDYrr 0U, // VPCMPGTDZ128rm 0U, // VPCMPGTDZ128rmb 0U, // VPCMPGTDZ128rmbk 0U, // VPCMPGTDZ128rmk 0U, // VPCMPGTDZ128rr 0U, // VPCMPGTDZ128rrk 0U, // VPCMPGTDZ256rm 0U, // VPCMPGTDZ256rmb 0U, // VPCMPGTDZ256rmbk 0U, // VPCMPGTDZ256rmk 0U, // VPCMPGTDZ256rr 0U, // VPCMPGTDZ256rrk 0U, // VPCMPGTDZrm 0U, // VPCMPGTDZrmb 0U, // VPCMPGTDZrmbk 0U, // VPCMPGTDZrmk 0U, // VPCMPGTDZrr 0U, // VPCMPGTDZrrk 0U, // VPCMPGTDrm 0U, // VPCMPGTDrr 0U, // VPCMPGTQYrm 0U, // VPCMPGTQYrr 0U, // VPCMPGTQZ128rm 0U, // VPCMPGTQZ128rmb 0U, // VPCMPGTQZ128rmbk 0U, // VPCMPGTQZ128rmk 0U, // VPCMPGTQZ128rr 0U, // VPCMPGTQZ128rrk 0U, // VPCMPGTQZ256rm 0U, // VPCMPGTQZ256rmb 0U, // VPCMPGTQZ256rmbk 0U, // VPCMPGTQZ256rmk 0U, // VPCMPGTQZ256rr 0U, // VPCMPGTQZ256rrk 0U, // VPCMPGTQZrm 0U, // VPCMPGTQZrmb 0U, // VPCMPGTQZrmbk 0U, // VPCMPGTQZrmk 0U, // VPCMPGTQZrr 0U, // VPCMPGTQZrrk 0U, // VPCMPGTQrm 0U, // VPCMPGTQrr 0U, // VPCMPGTWYrm 0U, // VPCMPGTWYrr 0U, // VPCMPGTWZ128rm 0U, // VPCMPGTWZ128rmk 0U, // VPCMPGTWZ128rr 0U, // VPCMPGTWZ128rrk 0U, // VPCMPGTWZ256rm 0U, // VPCMPGTWZ256rmk 0U, // VPCMPGTWZ256rr 0U, // VPCMPGTWZ256rrk 0U, // VPCMPGTWZrm 0U, // VPCMPGTWZrmk 0U, // VPCMPGTWZrr 0U, // VPCMPGTWZrrk 0U, // VPCMPGTWrm 0U, // VPCMPGTWrr 0U, // VPCMPISTRIrm 0U, // VPCMPISTRIrr 0U, // VPCMPISTRMrm 0U, // VPCMPISTRMrr 0U, // VPCMPQZ128rmi 0U, // VPCMPQZ128rmi_alt 0U, // VPCMPQZ128rmib 0U, // VPCMPQZ128rmib_alt 1U, // VPCMPQZ128rmibk 1U, // VPCMPQZ128rmibk_alt 0U, // VPCMPQZ128rmik 0U, // VPCMPQZ128rmik_alt 0U, // VPCMPQZ128rri 0U, // VPCMPQZ128rri_alt 1U, // VPCMPQZ128rrik 1U, // VPCMPQZ128rrik_alt 0U, // VPCMPQZ256rmi 0U, // VPCMPQZ256rmi_alt 0U, // VPCMPQZ256rmib 0U, // VPCMPQZ256rmib_alt 1U, // VPCMPQZ256rmibk 1U, // VPCMPQZ256rmibk_alt 0U, // VPCMPQZ256rmik 0U, // VPCMPQZ256rmik_alt 0U, // VPCMPQZ256rri 0U, // VPCMPQZ256rri_alt 1U, // VPCMPQZ256rrik 1U, // VPCMPQZ256rrik_alt 0U, // VPCMPQZrmi 0U, // VPCMPQZrmi_alt 0U, // VPCMPQZrmib 0U, // VPCMPQZrmib_alt 1U, // VPCMPQZrmibk 1U, // VPCMPQZrmibk_alt 0U, // VPCMPQZrmik 0U, // VPCMPQZrmik_alt 0U, // VPCMPQZrri 0U, // VPCMPQZrri_alt 1U, // VPCMPQZrrik 1U, // VPCMPQZrrik_alt 0U, // VPCMPUBZ128rmi 0U, // VPCMPUBZ128rmi_alt 0U, // VPCMPUBZ128rmik 0U, // VPCMPUBZ128rmik_alt 0U, // VPCMPUBZ128rri 0U, // VPCMPUBZ128rri_alt 1U, // VPCMPUBZ128rrik 1U, // VPCMPUBZ128rrik_alt 0U, // VPCMPUBZ256rmi 0U, // VPCMPUBZ256rmi_alt 0U, // VPCMPUBZ256rmik 0U, // VPCMPUBZ256rmik_alt 0U, // VPCMPUBZ256rri 0U, // VPCMPUBZ256rri_alt 1U, // VPCMPUBZ256rrik 1U, // VPCMPUBZ256rrik_alt 0U, // VPCMPUBZrmi 0U, // VPCMPUBZrmi_alt 0U, // VPCMPUBZrmik 0U, // VPCMPUBZrmik_alt 0U, // VPCMPUBZrri 0U, // VPCMPUBZrri_alt 1U, // VPCMPUBZrrik 1U, // VPCMPUBZrrik_alt 0U, // VPCMPUDZ128rmi 0U, // VPCMPUDZ128rmi_alt 0U, // VPCMPUDZ128rmib 0U, // VPCMPUDZ128rmib_alt 1U, // VPCMPUDZ128rmibk 1U, // VPCMPUDZ128rmibk_alt 0U, // VPCMPUDZ128rmik 0U, // VPCMPUDZ128rmik_alt 0U, // VPCMPUDZ128rri 0U, // VPCMPUDZ128rri_alt 1U, // VPCMPUDZ128rrik 1U, // VPCMPUDZ128rrik_alt 0U, // VPCMPUDZ256rmi 0U, // VPCMPUDZ256rmi_alt 0U, // VPCMPUDZ256rmib 0U, // VPCMPUDZ256rmib_alt 1U, // VPCMPUDZ256rmibk 1U, // VPCMPUDZ256rmibk_alt 0U, // VPCMPUDZ256rmik 0U, // VPCMPUDZ256rmik_alt 0U, // VPCMPUDZ256rri 0U, // VPCMPUDZ256rri_alt 1U, // VPCMPUDZ256rrik 1U, // VPCMPUDZ256rrik_alt 0U, // VPCMPUDZrmi 0U, // VPCMPUDZrmi_alt 0U, // VPCMPUDZrmib 0U, // VPCMPUDZrmib_alt 1U, // VPCMPUDZrmibk 1U, // VPCMPUDZrmibk_alt 0U, // VPCMPUDZrmik 0U, // VPCMPUDZrmik_alt 0U, // VPCMPUDZrri 0U, // VPCMPUDZrri_alt 1U, // VPCMPUDZrrik 1U, // VPCMPUDZrrik_alt 0U, // VPCMPUQZ128rmi 0U, // VPCMPUQZ128rmi_alt 0U, // VPCMPUQZ128rmib 0U, // VPCMPUQZ128rmib_alt 1U, // VPCMPUQZ128rmibk 1U, // VPCMPUQZ128rmibk_alt 0U, // VPCMPUQZ128rmik 0U, // VPCMPUQZ128rmik_alt 0U, // VPCMPUQZ128rri 0U, // VPCMPUQZ128rri_alt 1U, // VPCMPUQZ128rrik 1U, // VPCMPUQZ128rrik_alt 0U, // VPCMPUQZ256rmi 0U, // VPCMPUQZ256rmi_alt 0U, // VPCMPUQZ256rmib 0U, // VPCMPUQZ256rmib_alt 1U, // VPCMPUQZ256rmibk 1U, // VPCMPUQZ256rmibk_alt 0U, // VPCMPUQZ256rmik 0U, // VPCMPUQZ256rmik_alt 0U, // VPCMPUQZ256rri 0U, // VPCMPUQZ256rri_alt 1U, // VPCMPUQZ256rrik 1U, // VPCMPUQZ256rrik_alt 0U, // VPCMPUQZrmi 0U, // VPCMPUQZrmi_alt 0U, // VPCMPUQZrmib 0U, // VPCMPUQZrmib_alt 1U, // VPCMPUQZrmibk 1U, // VPCMPUQZrmibk_alt 0U, // VPCMPUQZrmik 0U, // VPCMPUQZrmik_alt 0U, // VPCMPUQZrri 0U, // VPCMPUQZrri_alt 1U, // VPCMPUQZrrik 1U, // VPCMPUQZrrik_alt 0U, // VPCMPUWZ128rmi 0U, // VPCMPUWZ128rmi_alt 0U, // VPCMPUWZ128rmik 0U, // VPCMPUWZ128rmik_alt 0U, // VPCMPUWZ128rri 0U, // VPCMPUWZ128rri_alt 1U, // VPCMPUWZ128rrik 1U, // VPCMPUWZ128rrik_alt 0U, // VPCMPUWZ256rmi 0U, // VPCMPUWZ256rmi_alt 0U, // VPCMPUWZ256rmik 0U, // VPCMPUWZ256rmik_alt 0U, // VPCMPUWZ256rri 0U, // VPCMPUWZ256rri_alt 1U, // VPCMPUWZ256rrik 1U, // VPCMPUWZ256rrik_alt 0U, // VPCMPUWZrmi 0U, // VPCMPUWZrmi_alt 0U, // VPCMPUWZrmik 0U, // VPCMPUWZrmik_alt 0U, // VPCMPUWZrri 0U, // VPCMPUWZrri_alt 1U, // VPCMPUWZrrik 1U, // VPCMPUWZrrik_alt 0U, // VPCMPWZ128rmi 0U, // VPCMPWZ128rmi_alt 0U, // VPCMPWZ128rmik 0U, // VPCMPWZ128rmik_alt 0U, // VPCMPWZ128rri 0U, // VPCMPWZ128rri_alt 1U, // VPCMPWZ128rrik 1U, // VPCMPWZ128rrik_alt 0U, // VPCMPWZ256rmi 0U, // VPCMPWZ256rmi_alt 0U, // VPCMPWZ256rmik 0U, // VPCMPWZ256rmik_alt 0U, // VPCMPWZ256rri 0U, // VPCMPWZ256rri_alt 1U, // VPCMPWZ256rrik 1U, // VPCMPWZ256rrik_alt 0U, // VPCMPWZrmi 0U, // VPCMPWZrmi_alt 0U, // VPCMPWZrmik 0U, // VPCMPWZrmik_alt 0U, // VPCMPWZrri 0U, // VPCMPWZrri_alt 1U, // VPCMPWZrrik 1U, // VPCMPWZrrik_alt 0U, // VPCOMBmi 0U, // VPCOMBmi_alt 0U, // VPCOMBri 0U, // VPCOMBri_alt 0U, // VPCOMDmi 0U, // VPCOMDmi_alt 0U, // VPCOMDri 0U, // VPCOMDri_alt 0U, // VPCOMPRESSBZ128mr 0U, // VPCOMPRESSBZ128mrk 0U, // VPCOMPRESSBZ128rr 0U, // VPCOMPRESSBZ128rrk 0U, // VPCOMPRESSBZ128rrkz 0U, // VPCOMPRESSBZ256mr 0U, // VPCOMPRESSBZ256mrk 0U, // VPCOMPRESSBZ256rr 0U, // VPCOMPRESSBZ256rrk 0U, // VPCOMPRESSBZ256rrkz 0U, // VPCOMPRESSBZmr 0U, // VPCOMPRESSBZmrk 0U, // VPCOMPRESSBZrr 0U, // VPCOMPRESSBZrrk 0U, // VPCOMPRESSBZrrkz 0U, // VPCOMPRESSDZ128mr 0U, // VPCOMPRESSDZ128mrk 0U, // VPCOMPRESSDZ128rr 0U, // VPCOMPRESSDZ128rrk 0U, // VPCOMPRESSDZ128rrkz 0U, // VPCOMPRESSDZ256mr 0U, // VPCOMPRESSDZ256mrk 0U, // VPCOMPRESSDZ256rr 0U, // VPCOMPRESSDZ256rrk 0U, // VPCOMPRESSDZ256rrkz 0U, // VPCOMPRESSDZmr 0U, // VPCOMPRESSDZmrk 0U, // VPCOMPRESSDZrr 0U, // VPCOMPRESSDZrrk 0U, // VPCOMPRESSDZrrkz 0U, // VPCOMPRESSQZ128mr 0U, // VPCOMPRESSQZ128mrk 0U, // VPCOMPRESSQZ128rr 0U, // VPCOMPRESSQZ128rrk 0U, // VPCOMPRESSQZ128rrkz 0U, // VPCOMPRESSQZ256mr 0U, // VPCOMPRESSQZ256mrk 0U, // VPCOMPRESSQZ256rr 0U, // VPCOMPRESSQZ256rrk 0U, // VPCOMPRESSQZ256rrkz 0U, // VPCOMPRESSQZmr 0U, // VPCOMPRESSQZmrk 0U, // VPCOMPRESSQZrr 0U, // VPCOMPRESSQZrrk 0U, // VPCOMPRESSQZrrkz 0U, // VPCOMPRESSWZ128mr 0U, // VPCOMPRESSWZ128mrk 0U, // VPCOMPRESSWZ128rr 0U, // VPCOMPRESSWZ128rrk 0U, // VPCOMPRESSWZ128rrkz 0U, // VPCOMPRESSWZ256mr 0U, // VPCOMPRESSWZ256mrk 0U, // VPCOMPRESSWZ256rr 0U, // VPCOMPRESSWZ256rrk 0U, // VPCOMPRESSWZ256rrkz 0U, // VPCOMPRESSWZmr 0U, // VPCOMPRESSWZmrk 0U, // VPCOMPRESSWZrr 0U, // VPCOMPRESSWZrrk 0U, // VPCOMPRESSWZrrkz 0U, // VPCOMQmi 0U, // VPCOMQmi_alt 0U, // VPCOMQri 0U, // VPCOMQri_alt 0U, // VPCOMUBmi 0U, // VPCOMUBmi_alt 0U, // VPCOMUBri 0U, // VPCOMUBri_alt 0U, // VPCOMUDmi 0U, // VPCOMUDmi_alt 0U, // VPCOMUDri 0U, // VPCOMUDri_alt 0U, // VPCOMUQmi 0U, // VPCOMUQmi_alt 0U, // VPCOMUQri 0U, // VPCOMUQri_alt 0U, // VPCOMUWmi 0U, // VPCOMUWmi_alt 0U, // VPCOMUWri 0U, // VPCOMUWri_alt 0U, // VPCOMWmi 0U, // VPCOMWmi_alt 0U, // VPCOMWri 0U, // VPCOMWri_alt 0U, // VPCONFLICTDZ128rm 0U, // VPCONFLICTDZ128rmb 0U, // VPCONFLICTDZ128rmbk 0U, // VPCONFLICTDZ128rmbkz 0U, // VPCONFLICTDZ128rmk 0U, // VPCONFLICTDZ128rmkz 0U, // VPCONFLICTDZ128rr 0U, // VPCONFLICTDZ128rrk 0U, // VPCONFLICTDZ128rrkz 0U, // VPCONFLICTDZ256rm 0U, // VPCONFLICTDZ256rmb 0U, // VPCONFLICTDZ256rmbk 0U, // VPCONFLICTDZ256rmbkz 0U, // VPCONFLICTDZ256rmk 0U, // VPCONFLICTDZ256rmkz 0U, // VPCONFLICTDZ256rr 0U, // VPCONFLICTDZ256rrk 0U, // VPCONFLICTDZ256rrkz 0U, // VPCONFLICTDZrm 0U, // VPCONFLICTDZrmb 0U, // VPCONFLICTDZrmbk 0U, // VPCONFLICTDZrmbkz 0U, // VPCONFLICTDZrmk 0U, // VPCONFLICTDZrmkz 0U, // VPCONFLICTDZrr 0U, // VPCONFLICTDZrrk 0U, // VPCONFLICTDZrrkz 0U, // VPCONFLICTQZ128rm 0U, // VPCONFLICTQZ128rmb 0U, // VPCONFLICTQZ128rmbk 0U, // VPCONFLICTQZ128rmbkz 0U, // VPCONFLICTQZ128rmk 0U, // VPCONFLICTQZ128rmkz 0U, // VPCONFLICTQZ128rr 0U, // VPCONFLICTQZ128rrk 0U, // VPCONFLICTQZ128rrkz 0U, // VPCONFLICTQZ256rm 0U, // VPCONFLICTQZ256rmb 0U, // VPCONFLICTQZ256rmbk 0U, // VPCONFLICTQZ256rmbkz 0U, // VPCONFLICTQZ256rmk 0U, // VPCONFLICTQZ256rmkz 0U, // VPCONFLICTQZ256rr 0U, // VPCONFLICTQZ256rrk 0U, // VPCONFLICTQZ256rrkz 0U, // VPCONFLICTQZrm 0U, // VPCONFLICTQZrmb 0U, // VPCONFLICTQZrmbk 0U, // VPCONFLICTQZrmbkz 0U, // VPCONFLICTQZrmk 0U, // VPCONFLICTQZrmkz 0U, // VPCONFLICTQZrr 0U, // VPCONFLICTQZrrk 0U, // VPCONFLICTQZrrkz 0U, // VPDPBUSDSZ128m 0U, // VPDPBUSDSZ128mb 0U, // VPDPBUSDSZ128mbk 0U, // VPDPBUSDSZ128mbkz 0U, // VPDPBUSDSZ128mk 0U, // VPDPBUSDSZ128mkz 0U, // VPDPBUSDSZ128r 0U, // VPDPBUSDSZ128rk 0U, // VPDPBUSDSZ128rkz 0U, // VPDPBUSDSZ256m 0U, // VPDPBUSDSZ256mb 0U, // VPDPBUSDSZ256mbk 0U, // VPDPBUSDSZ256mbkz 0U, // VPDPBUSDSZ256mk 0U, // VPDPBUSDSZ256mkz 0U, // VPDPBUSDSZ256r 0U, // VPDPBUSDSZ256rk 0U, // VPDPBUSDSZ256rkz 0U, // VPDPBUSDSZm 0U, // VPDPBUSDSZmb 0U, // VPDPBUSDSZmbk 0U, // VPDPBUSDSZmbkz 0U, // VPDPBUSDSZmk 0U, // VPDPBUSDSZmkz 0U, // VPDPBUSDSZr 0U, // VPDPBUSDSZrk 0U, // VPDPBUSDSZrkz 0U, // VPDPBUSDZ128m 0U, // VPDPBUSDZ128mb 0U, // VPDPBUSDZ128mbk 0U, // VPDPBUSDZ128mbkz 0U, // VPDPBUSDZ128mk 0U, // VPDPBUSDZ128mkz 0U, // VPDPBUSDZ128r 0U, // VPDPBUSDZ128rk 0U, // VPDPBUSDZ128rkz 0U, // VPDPBUSDZ256m 0U, // VPDPBUSDZ256mb 0U, // VPDPBUSDZ256mbk 0U, // VPDPBUSDZ256mbkz 0U, // VPDPBUSDZ256mk 0U, // VPDPBUSDZ256mkz 0U, // VPDPBUSDZ256r 0U, // VPDPBUSDZ256rk 0U, // VPDPBUSDZ256rkz 0U, // VPDPBUSDZm 0U, // VPDPBUSDZmb 0U, // VPDPBUSDZmbk 0U, // VPDPBUSDZmbkz 0U, // VPDPBUSDZmk 0U, // VPDPBUSDZmkz 0U, // VPDPBUSDZr 0U, // VPDPBUSDZrk 0U, // VPDPBUSDZrkz 0U, // VPDPWSSDSZ128m 0U, // VPDPWSSDSZ128mb 0U, // VPDPWSSDSZ128mbk 0U, // VPDPWSSDSZ128mbkz 0U, // VPDPWSSDSZ128mk 0U, // VPDPWSSDSZ128mkz 0U, // VPDPWSSDSZ128r 0U, // VPDPWSSDSZ128rk 0U, // VPDPWSSDSZ128rkz 0U, // VPDPWSSDSZ256m 0U, // VPDPWSSDSZ256mb 0U, // VPDPWSSDSZ256mbk 0U, // VPDPWSSDSZ256mbkz 0U, // VPDPWSSDSZ256mk 0U, // VPDPWSSDSZ256mkz 0U, // VPDPWSSDSZ256r 0U, // VPDPWSSDSZ256rk 0U, // VPDPWSSDSZ256rkz 0U, // VPDPWSSDSZm 0U, // VPDPWSSDSZmb 0U, // VPDPWSSDSZmbk 0U, // VPDPWSSDSZmbkz 0U, // VPDPWSSDSZmk 0U, // VPDPWSSDSZmkz 0U, // VPDPWSSDSZr 0U, // VPDPWSSDSZrk 0U, // VPDPWSSDSZrkz 0U, // VPDPWSSDZ128m 0U, // VPDPWSSDZ128mb 0U, // VPDPWSSDZ128mbk 0U, // VPDPWSSDZ128mbkz 0U, // VPDPWSSDZ128mk 0U, // VPDPWSSDZ128mkz 0U, // VPDPWSSDZ128r 0U, // VPDPWSSDZ128rk 0U, // VPDPWSSDZ128rkz 0U, // VPDPWSSDZ256m 0U, // VPDPWSSDZ256mb 0U, // VPDPWSSDZ256mbk 0U, // VPDPWSSDZ256mbkz 0U, // VPDPWSSDZ256mk 0U, // VPDPWSSDZ256mkz 0U, // VPDPWSSDZ256r 0U, // VPDPWSSDZ256rk 0U, // VPDPWSSDZ256rkz 0U, // VPDPWSSDZm 0U, // VPDPWSSDZmb 0U, // VPDPWSSDZmbk 0U, // VPDPWSSDZmbkz 0U, // VPDPWSSDZmk 0U, // VPDPWSSDZmkz 0U, // VPDPWSSDZr 0U, // VPDPWSSDZrk 0U, // VPDPWSSDZrkz 0U, // VPERM2F128rm 0U, // VPERM2F128rr 0U, // VPERM2I128rm 0U, // VPERM2I128rr 0U, // VPERMBZ128rm 0U, // VPERMBZ128rmk 0U, // VPERMBZ128rmkz 0U, // VPERMBZ128rr 0U, // VPERMBZ128rrk 0U, // VPERMBZ128rrkz 0U, // VPERMBZ256rm 0U, // VPERMBZ256rmk 0U, // VPERMBZ256rmkz 0U, // VPERMBZ256rr 0U, // VPERMBZ256rrk 0U, // VPERMBZ256rrkz 0U, // VPERMBZrm 0U, // VPERMBZrmk 0U, // VPERMBZrmkz 0U, // VPERMBZrr 0U, // VPERMBZrrk 0U, // VPERMBZrrkz 0U, // VPERMDYrm 0U, // VPERMDYrr 0U, // VPERMDZ256rm 0U, // VPERMDZ256rmb 0U, // VPERMDZ256rmbk 0U, // VPERMDZ256rmbkz 0U, // VPERMDZ256rmk 0U, // VPERMDZ256rmkz 0U, // VPERMDZ256rr 0U, // VPERMDZ256rrk 0U, // VPERMDZ256rrkz 0U, // VPERMDZrm 0U, // VPERMDZrmb 0U, // VPERMDZrmbk 0U, // VPERMDZrmbkz 0U, // VPERMDZrmk 0U, // VPERMDZrmkz 0U, // VPERMDZrr 0U, // VPERMDZrrk 0U, // VPERMDZrrkz 0U, // VPERMI2B128rm 0U, // VPERMI2B128rmk 0U, // VPERMI2B128rmkz 0U, // VPERMI2B128rr 0U, // VPERMI2B128rrk 0U, // VPERMI2B128rrkz 0U, // VPERMI2B256rm 0U, // VPERMI2B256rmk 0U, // VPERMI2B256rmkz 0U, // VPERMI2B256rr 0U, // VPERMI2B256rrk 0U, // VPERMI2B256rrkz 0U, // VPERMI2Brm 0U, // VPERMI2Brmk 0U, // VPERMI2Brmkz 0U, // VPERMI2Brr 0U, // VPERMI2Brrk 0U, // VPERMI2Brrkz 0U, // VPERMI2D128rm 0U, // VPERMI2D128rmb 0U, // VPERMI2D128rmbk 0U, // VPERMI2D128rmbkz 0U, // VPERMI2D128rmk 0U, // VPERMI2D128rmkz 0U, // VPERMI2D128rr 0U, // VPERMI2D128rrk 0U, // VPERMI2D128rrkz 0U, // VPERMI2D256rm 0U, // VPERMI2D256rmb 0U, // VPERMI2D256rmbk 0U, // VPERMI2D256rmbkz 0U, // VPERMI2D256rmk 0U, // VPERMI2D256rmkz 0U, // VPERMI2D256rr 0U, // VPERMI2D256rrk 0U, // VPERMI2D256rrkz 0U, // VPERMI2Drm 0U, // VPERMI2Drmb 0U, // VPERMI2Drmbk 0U, // VPERMI2Drmbkz 0U, // VPERMI2Drmk 0U, // VPERMI2Drmkz 0U, // VPERMI2Drr 0U, // VPERMI2Drrk 0U, // VPERMI2Drrkz 0U, // VPERMI2PD128rm 0U, // VPERMI2PD128rmb 0U, // VPERMI2PD128rmbk 0U, // VPERMI2PD128rmbkz 0U, // VPERMI2PD128rmk 0U, // VPERMI2PD128rmkz 0U, // VPERMI2PD128rr 0U, // VPERMI2PD128rrk 0U, // VPERMI2PD128rrkz 0U, // VPERMI2PD256rm 0U, // VPERMI2PD256rmb 0U, // VPERMI2PD256rmbk 0U, // VPERMI2PD256rmbkz 0U, // VPERMI2PD256rmk 0U, // VPERMI2PD256rmkz 0U, // VPERMI2PD256rr 0U, // VPERMI2PD256rrk 0U, // VPERMI2PD256rrkz 0U, // VPERMI2PDrm 0U, // VPERMI2PDrmb 0U, // VPERMI2PDrmbk 0U, // VPERMI2PDrmbkz 0U, // VPERMI2PDrmk 0U, // VPERMI2PDrmkz 0U, // VPERMI2PDrr 0U, // VPERMI2PDrrk 0U, // VPERMI2PDrrkz 0U, // VPERMI2PS128rm 0U, // VPERMI2PS128rmb 0U, // VPERMI2PS128rmbk 0U, // VPERMI2PS128rmbkz 0U, // VPERMI2PS128rmk 0U, // VPERMI2PS128rmkz 0U, // VPERMI2PS128rr 0U, // VPERMI2PS128rrk 0U, // VPERMI2PS128rrkz 0U, // VPERMI2PS256rm 0U, // VPERMI2PS256rmb 0U, // VPERMI2PS256rmbk 0U, // VPERMI2PS256rmbkz 0U, // VPERMI2PS256rmk 0U, // VPERMI2PS256rmkz 0U, // VPERMI2PS256rr 0U, // VPERMI2PS256rrk 0U, // VPERMI2PS256rrkz 0U, // VPERMI2PSrm 0U, // VPERMI2PSrmb 0U, // VPERMI2PSrmbk 0U, // VPERMI2PSrmbkz 0U, // VPERMI2PSrmk 0U, // VPERMI2PSrmkz 0U, // VPERMI2PSrr 0U, // VPERMI2PSrrk 0U, // VPERMI2PSrrkz 0U, // VPERMI2Q128rm 0U, // VPERMI2Q128rmb 0U, // VPERMI2Q128rmbk 0U, // VPERMI2Q128rmbkz 0U, // VPERMI2Q128rmk 0U, // VPERMI2Q128rmkz 0U, // VPERMI2Q128rr 0U, // VPERMI2Q128rrk 0U, // VPERMI2Q128rrkz 0U, // VPERMI2Q256rm 0U, // VPERMI2Q256rmb 0U, // VPERMI2Q256rmbk 0U, // VPERMI2Q256rmbkz 0U, // VPERMI2Q256rmk 0U, // VPERMI2Q256rmkz 0U, // VPERMI2Q256rr 0U, // VPERMI2Q256rrk 0U, // VPERMI2Q256rrkz 0U, // VPERMI2Qrm 0U, // VPERMI2Qrmb 0U, // VPERMI2Qrmbk 0U, // VPERMI2Qrmbkz 0U, // VPERMI2Qrmk 0U, // VPERMI2Qrmkz 0U, // VPERMI2Qrr 0U, // VPERMI2Qrrk 0U, // VPERMI2Qrrkz 0U, // VPERMI2W128rm 0U, // VPERMI2W128rmk 0U, // VPERMI2W128rmkz 0U, // VPERMI2W128rr 0U, // VPERMI2W128rrk 0U, // VPERMI2W128rrkz 0U, // VPERMI2W256rm 0U, // VPERMI2W256rmk 0U, // VPERMI2W256rmkz 0U, // VPERMI2W256rr 0U, // VPERMI2W256rrk 0U, // VPERMI2W256rrkz 0U, // VPERMI2Wrm 0U, // VPERMI2Wrmk 0U, // VPERMI2Wrmkz 0U, // VPERMI2Wrr 0U, // VPERMI2Wrrk 0U, // VPERMI2Wrrkz 0U, // VPERMIL2PDYmr 0U, // VPERMIL2PDYrm 0U, // VPERMIL2PDYrr 0U, // VPERMIL2PDYrr_REV 0U, // VPERMIL2PDmr 0U, // VPERMIL2PDrm 0U, // VPERMIL2PDrr 0U, // VPERMIL2PDrr_REV 0U, // VPERMIL2PSYmr 0U, // VPERMIL2PSYrm 0U, // VPERMIL2PSYrr 0U, // VPERMIL2PSYrr_REV 0U, // VPERMIL2PSmr 0U, // VPERMIL2PSrm 0U, // VPERMIL2PSrr 0U, // VPERMIL2PSrr_REV 0U, // VPERMILPDYmi 0U, // VPERMILPDYri 0U, // VPERMILPDYrm 0U, // VPERMILPDYrr 0U, // VPERMILPDZ128mbi 0U, // VPERMILPDZ128mbik 0U, // VPERMILPDZ128mbikz 0U, // VPERMILPDZ128mi 0U, // VPERMILPDZ128mik 0U, // VPERMILPDZ128mikz 0U, // VPERMILPDZ128ri 0U, // VPERMILPDZ128rik 0U, // VPERMILPDZ128rikz 0U, // VPERMILPDZ128rm 0U, // VPERMILPDZ128rmb 0U, // VPERMILPDZ128rmbk 0U, // VPERMILPDZ128rmbkz 0U, // VPERMILPDZ128rmk 0U, // VPERMILPDZ128rmkz 0U, // VPERMILPDZ128rr 0U, // VPERMILPDZ128rrk 0U, // VPERMILPDZ128rrkz 0U, // VPERMILPDZ256mbi 0U, // VPERMILPDZ256mbik 0U, // VPERMILPDZ256mbikz 0U, // VPERMILPDZ256mi 0U, // VPERMILPDZ256mik 0U, // VPERMILPDZ256mikz 0U, // VPERMILPDZ256ri 0U, // VPERMILPDZ256rik 0U, // VPERMILPDZ256rikz 0U, // VPERMILPDZ256rm 0U, // VPERMILPDZ256rmb 0U, // VPERMILPDZ256rmbk 0U, // VPERMILPDZ256rmbkz 0U, // VPERMILPDZ256rmk 0U, // VPERMILPDZ256rmkz 0U, // VPERMILPDZ256rr 0U, // VPERMILPDZ256rrk 0U, // VPERMILPDZ256rrkz 0U, // VPERMILPDZmbi 0U, // VPERMILPDZmbik 0U, // VPERMILPDZmbikz 0U, // VPERMILPDZmi 0U, // VPERMILPDZmik 0U, // VPERMILPDZmikz 0U, // VPERMILPDZri 0U, // VPERMILPDZrik 0U, // VPERMILPDZrikz 0U, // VPERMILPDZrm 0U, // VPERMILPDZrmb 0U, // VPERMILPDZrmbk 0U, // VPERMILPDZrmbkz 0U, // VPERMILPDZrmk 0U, // VPERMILPDZrmkz 0U, // VPERMILPDZrr 0U, // VPERMILPDZrrk 0U, // VPERMILPDZrrkz 0U, // VPERMILPDmi 0U, // VPERMILPDri 0U, // VPERMILPDrm 0U, // VPERMILPDrr 0U, // VPERMILPSYmi 0U, // VPERMILPSYri 0U, // VPERMILPSYrm 0U, // VPERMILPSYrr 0U, // VPERMILPSZ128mbi 0U, // VPERMILPSZ128mbik 0U, // VPERMILPSZ128mbikz 0U, // VPERMILPSZ128mi 0U, // VPERMILPSZ128mik 0U, // VPERMILPSZ128mikz 0U, // VPERMILPSZ128ri 0U, // VPERMILPSZ128rik 0U, // VPERMILPSZ128rikz 0U, // VPERMILPSZ128rm 0U, // VPERMILPSZ128rmb 0U, // VPERMILPSZ128rmbk 0U, // VPERMILPSZ128rmbkz 0U, // VPERMILPSZ128rmk 0U, // VPERMILPSZ128rmkz 0U, // VPERMILPSZ128rr 0U, // VPERMILPSZ128rrk 0U, // VPERMILPSZ128rrkz 0U, // VPERMILPSZ256mbi 0U, // VPERMILPSZ256mbik 0U, // VPERMILPSZ256mbikz 0U, // VPERMILPSZ256mi 0U, // VPERMILPSZ256mik 0U, // VPERMILPSZ256mikz 0U, // VPERMILPSZ256ri 0U, // VPERMILPSZ256rik 0U, // VPERMILPSZ256rikz 0U, // VPERMILPSZ256rm 0U, // VPERMILPSZ256rmb 0U, // VPERMILPSZ256rmbk 0U, // VPERMILPSZ256rmbkz 0U, // VPERMILPSZ256rmk 0U, // VPERMILPSZ256rmkz 0U, // VPERMILPSZ256rr 0U, // VPERMILPSZ256rrk 0U, // VPERMILPSZ256rrkz 0U, // VPERMILPSZmbi 0U, // VPERMILPSZmbik 0U, // VPERMILPSZmbikz 0U, // VPERMILPSZmi 0U, // VPERMILPSZmik 0U, // VPERMILPSZmikz 0U, // VPERMILPSZri 0U, // VPERMILPSZrik 0U, // VPERMILPSZrikz 0U, // VPERMILPSZrm 0U, // VPERMILPSZrmb 0U, // VPERMILPSZrmbk 0U, // VPERMILPSZrmbkz 0U, // VPERMILPSZrmk 0U, // VPERMILPSZrmkz 0U, // VPERMILPSZrr 0U, // VPERMILPSZrrk 0U, // VPERMILPSZrrkz 0U, // VPERMILPSmi 0U, // VPERMILPSri 0U, // VPERMILPSrm 0U, // VPERMILPSrr 0U, // VPERMPDYmi 0U, // VPERMPDYri 0U, // VPERMPDZ256mbi 0U, // VPERMPDZ256mbik 0U, // VPERMPDZ256mbikz 0U, // VPERMPDZ256mi 0U, // VPERMPDZ256mik 0U, // VPERMPDZ256mikz 0U, // VPERMPDZ256ri 0U, // VPERMPDZ256rik 0U, // VPERMPDZ256rikz 0U, // VPERMPDZ256rm 0U, // VPERMPDZ256rmb 0U, // VPERMPDZ256rmbk 0U, // VPERMPDZ256rmbkz 0U, // VPERMPDZ256rmk 0U, // VPERMPDZ256rmkz 0U, // VPERMPDZ256rr 0U, // VPERMPDZ256rrk 0U, // VPERMPDZ256rrkz 0U, // VPERMPDZmbi 0U, // VPERMPDZmbik 0U, // VPERMPDZmbikz 0U, // VPERMPDZmi 0U, // VPERMPDZmik 0U, // VPERMPDZmikz 0U, // VPERMPDZri 0U, // VPERMPDZrik 0U, // VPERMPDZrikz 0U, // VPERMPDZrm 0U, // VPERMPDZrmb 0U, // VPERMPDZrmbk 0U, // VPERMPDZrmbkz 0U, // VPERMPDZrmk 0U, // VPERMPDZrmkz 0U, // VPERMPDZrr 0U, // VPERMPDZrrk 0U, // VPERMPDZrrkz 0U, // VPERMPSYrm 0U, // VPERMPSYrr 0U, // VPERMPSZ256rm 0U, // VPERMPSZ256rmb 0U, // VPERMPSZ256rmbk 0U, // VPERMPSZ256rmbkz 0U, // VPERMPSZ256rmk 0U, // VPERMPSZ256rmkz 0U, // VPERMPSZ256rr 0U, // VPERMPSZ256rrk 0U, // VPERMPSZ256rrkz 0U, // VPERMPSZrm 0U, // VPERMPSZrmb 0U, // VPERMPSZrmbk 0U, // VPERMPSZrmbkz 0U, // VPERMPSZrmk 0U, // VPERMPSZrmkz 0U, // VPERMPSZrr 0U, // VPERMPSZrrk 0U, // VPERMPSZrrkz 0U, // VPERMQYmi 0U, // VPERMQYri 0U, // VPERMQZ256mbi 0U, // VPERMQZ256mbik 0U, // VPERMQZ256mbikz 0U, // VPERMQZ256mi 0U, // VPERMQZ256mik 0U, // VPERMQZ256mikz 0U, // VPERMQZ256ri 0U, // VPERMQZ256rik 0U, // VPERMQZ256rikz 0U, // VPERMQZ256rm 0U, // VPERMQZ256rmb 0U, // VPERMQZ256rmbk 0U, // VPERMQZ256rmbkz 0U, // VPERMQZ256rmk 0U, // VPERMQZ256rmkz 0U, // VPERMQZ256rr 0U, // VPERMQZ256rrk 0U, // VPERMQZ256rrkz 0U, // VPERMQZmbi 0U, // VPERMQZmbik 0U, // VPERMQZmbikz 0U, // VPERMQZmi 0U, // VPERMQZmik 0U, // VPERMQZmikz 0U, // VPERMQZri 0U, // VPERMQZrik 0U, // VPERMQZrikz 0U, // VPERMQZrm 0U, // VPERMQZrmb 0U, // VPERMQZrmbk 0U, // VPERMQZrmbkz 0U, // VPERMQZrmk 0U, // VPERMQZrmkz 0U, // VPERMQZrr 0U, // VPERMQZrrk 0U, // VPERMQZrrkz 0U, // VPERMT2B128rm 0U, // VPERMT2B128rmk 0U, // VPERMT2B128rmkz 0U, // VPERMT2B128rr 0U, // VPERMT2B128rrk 0U, // VPERMT2B128rrkz 0U, // VPERMT2B256rm 0U, // VPERMT2B256rmk 0U, // VPERMT2B256rmkz 0U, // VPERMT2B256rr 0U, // VPERMT2B256rrk 0U, // VPERMT2B256rrkz 0U, // VPERMT2Brm 0U, // VPERMT2Brmk 0U, // VPERMT2Brmkz 0U, // VPERMT2Brr 0U, // VPERMT2Brrk 0U, // VPERMT2Brrkz 0U, // VPERMT2D128rm 0U, // VPERMT2D128rmb 0U, // VPERMT2D128rmbk 0U, // VPERMT2D128rmbkz 0U, // VPERMT2D128rmk 0U, // VPERMT2D128rmkz 0U, // VPERMT2D128rr 0U, // VPERMT2D128rrk 0U, // VPERMT2D128rrkz 0U, // VPERMT2D256rm 0U, // VPERMT2D256rmb 0U, // VPERMT2D256rmbk 0U, // VPERMT2D256rmbkz 0U, // VPERMT2D256rmk 0U, // VPERMT2D256rmkz 0U, // VPERMT2D256rr 0U, // VPERMT2D256rrk 0U, // VPERMT2D256rrkz 0U, // VPERMT2Drm 0U, // VPERMT2Drmb 0U, // VPERMT2Drmbk 0U, // VPERMT2Drmbkz 0U, // VPERMT2Drmk 0U, // VPERMT2Drmkz 0U, // VPERMT2Drr 0U, // VPERMT2Drrk 0U, // VPERMT2Drrkz 0U, // VPERMT2PD128rm 0U, // VPERMT2PD128rmb 0U, // VPERMT2PD128rmbk 0U, // VPERMT2PD128rmbkz 0U, // VPERMT2PD128rmk 0U, // VPERMT2PD128rmkz 0U, // VPERMT2PD128rr 0U, // VPERMT2PD128rrk 0U, // VPERMT2PD128rrkz 0U, // VPERMT2PD256rm 0U, // VPERMT2PD256rmb 0U, // VPERMT2PD256rmbk 0U, // VPERMT2PD256rmbkz 0U, // VPERMT2PD256rmk 0U, // VPERMT2PD256rmkz 0U, // VPERMT2PD256rr 0U, // VPERMT2PD256rrk 0U, // VPERMT2PD256rrkz 0U, // VPERMT2PDrm 0U, // VPERMT2PDrmb 0U, // VPERMT2PDrmbk 0U, // VPERMT2PDrmbkz 0U, // VPERMT2PDrmk 0U, // VPERMT2PDrmkz 0U, // VPERMT2PDrr 0U, // VPERMT2PDrrk 0U, // VPERMT2PDrrkz 0U, // VPERMT2PS128rm 0U, // VPERMT2PS128rmb 0U, // VPERMT2PS128rmbk 0U, // VPERMT2PS128rmbkz 0U, // VPERMT2PS128rmk 0U, // VPERMT2PS128rmkz 0U, // VPERMT2PS128rr 0U, // VPERMT2PS128rrk 0U, // VPERMT2PS128rrkz 0U, // VPERMT2PS256rm 0U, // VPERMT2PS256rmb 0U, // VPERMT2PS256rmbk 0U, // VPERMT2PS256rmbkz 0U, // VPERMT2PS256rmk 0U, // VPERMT2PS256rmkz 0U, // VPERMT2PS256rr 0U, // VPERMT2PS256rrk 0U, // VPERMT2PS256rrkz 0U, // VPERMT2PSrm 0U, // VPERMT2PSrmb 0U, // VPERMT2PSrmbk 0U, // VPERMT2PSrmbkz 0U, // VPERMT2PSrmk 0U, // VPERMT2PSrmkz 0U, // VPERMT2PSrr 0U, // VPERMT2PSrrk 0U, // VPERMT2PSrrkz 0U, // VPERMT2Q128rm 0U, // VPERMT2Q128rmb 0U, // VPERMT2Q128rmbk 0U, // VPERMT2Q128rmbkz 0U, // VPERMT2Q128rmk 0U, // VPERMT2Q128rmkz 0U, // VPERMT2Q128rr 0U, // VPERMT2Q128rrk 0U, // VPERMT2Q128rrkz 0U, // VPERMT2Q256rm 0U, // VPERMT2Q256rmb 0U, // VPERMT2Q256rmbk 0U, // VPERMT2Q256rmbkz 0U, // VPERMT2Q256rmk 0U, // VPERMT2Q256rmkz 0U, // VPERMT2Q256rr 0U, // VPERMT2Q256rrk 0U, // VPERMT2Q256rrkz 0U, // VPERMT2Qrm 0U, // VPERMT2Qrmb 0U, // VPERMT2Qrmbk 0U, // VPERMT2Qrmbkz 0U, // VPERMT2Qrmk 0U, // VPERMT2Qrmkz 0U, // VPERMT2Qrr 0U, // VPERMT2Qrrk 0U, // VPERMT2Qrrkz 0U, // VPERMT2W128rm 0U, // VPERMT2W128rmk 0U, // VPERMT2W128rmkz 0U, // VPERMT2W128rr 0U, // VPERMT2W128rrk 0U, // VPERMT2W128rrkz 0U, // VPERMT2W256rm 0U, // VPERMT2W256rmk 0U, // VPERMT2W256rmkz 0U, // VPERMT2W256rr 0U, // VPERMT2W256rrk 0U, // VPERMT2W256rrkz 0U, // VPERMT2Wrm 0U, // VPERMT2Wrmk 0U, // VPERMT2Wrmkz 0U, // VPERMT2Wrr 0U, // VPERMT2Wrrk 0U, // VPERMT2Wrrkz 0U, // VPERMWZ128rm 0U, // VPERMWZ128rmk 0U, // VPERMWZ128rmkz 0U, // VPERMWZ128rr 0U, // VPERMWZ128rrk 0U, // VPERMWZ128rrkz 0U, // VPERMWZ256rm 0U, // VPERMWZ256rmk 0U, // VPERMWZ256rmkz 0U, // VPERMWZ256rr 0U, // VPERMWZ256rrk 0U, // VPERMWZ256rrkz 0U, // VPERMWZrm 0U, // VPERMWZrmk 0U, // VPERMWZrmkz 0U, // VPERMWZrr 0U, // VPERMWZrrk 0U, // VPERMWZrrkz 0U, // VPEXPANDBZ128rm 0U, // VPEXPANDBZ128rmk 0U, // VPEXPANDBZ128rmkz 0U, // VPEXPANDBZ128rr 0U, // VPEXPANDBZ128rrk 0U, // VPEXPANDBZ128rrkz 0U, // VPEXPANDBZ256rm 0U, // VPEXPANDBZ256rmk 0U, // VPEXPANDBZ256rmkz 0U, // VPEXPANDBZ256rr 0U, // VPEXPANDBZ256rrk 0U, // VPEXPANDBZ256rrkz 0U, // VPEXPANDBZrm 0U, // VPEXPANDBZrmk 0U, // VPEXPANDBZrmkz 0U, // VPEXPANDBZrr 0U, // VPEXPANDBZrrk 0U, // VPEXPANDBZrrkz 0U, // VPEXPANDDZ128rm 0U, // VPEXPANDDZ128rmk 0U, // VPEXPANDDZ128rmkz 0U, // VPEXPANDDZ128rr 0U, // VPEXPANDDZ128rrk 0U, // VPEXPANDDZ128rrkz 0U, // VPEXPANDDZ256rm 0U, // VPEXPANDDZ256rmk 0U, // VPEXPANDDZ256rmkz 0U, // VPEXPANDDZ256rr 0U, // VPEXPANDDZ256rrk 0U, // VPEXPANDDZ256rrkz 0U, // VPEXPANDDZrm 0U, // VPEXPANDDZrmk 0U, // VPEXPANDDZrmkz 0U, // VPEXPANDDZrr 0U, // VPEXPANDDZrrk 0U, // VPEXPANDDZrrkz 0U, // VPEXPANDQZ128rm 0U, // VPEXPANDQZ128rmk 0U, // VPEXPANDQZ128rmkz 0U, // VPEXPANDQZ128rr 0U, // VPEXPANDQZ128rrk 0U, // VPEXPANDQZ128rrkz 0U, // VPEXPANDQZ256rm 0U, // VPEXPANDQZ256rmk 0U, // VPEXPANDQZ256rmkz 0U, // VPEXPANDQZ256rr 0U, // VPEXPANDQZ256rrk 0U, // VPEXPANDQZ256rrkz 0U, // VPEXPANDQZrm 0U, // VPEXPANDQZrmk 0U, // VPEXPANDQZrmkz 0U, // VPEXPANDQZrr 0U, // VPEXPANDQZrrk 0U, // VPEXPANDQZrrkz 0U, // VPEXPANDWZ128rm 0U, // VPEXPANDWZ128rmk 0U, // VPEXPANDWZ128rmkz 0U, // VPEXPANDWZ128rr 0U, // VPEXPANDWZ128rrk 0U, // VPEXPANDWZ128rrkz 0U, // VPEXPANDWZ256rm 0U, // VPEXPANDWZ256rmk 0U, // VPEXPANDWZ256rmkz 0U, // VPEXPANDWZ256rr 0U, // VPEXPANDWZ256rrk 0U, // VPEXPANDWZ256rrkz 0U, // VPEXPANDWZrm 0U, // VPEXPANDWZrmk 0U, // VPEXPANDWZrmkz 0U, // VPEXPANDWZrr 0U, // VPEXPANDWZrrk 0U, // VPEXPANDWZrrkz 0U, // VPEXTRBZmr 0U, // VPEXTRBZrr 0U, // VPEXTRBmr 0U, // VPEXTRBrr 0U, // VPEXTRDZmr 0U, // VPEXTRDZrr 0U, // VPEXTRDmr 0U, // VPEXTRDrr 0U, // VPEXTRQZmr 0U, // VPEXTRQZrr 0U, // VPEXTRQmr 0U, // VPEXTRQrr 0U, // VPEXTRWZmr 0U, // VPEXTRWZrr 0U, // VPEXTRWZrr_REV 0U, // VPEXTRWmr 0U, // VPEXTRWrr 0U, // VPEXTRWrr_REV 0U, // VPGATHERDDYrm 0U, // VPGATHERDDZ128rm 0U, // VPGATHERDDZ256rm 0U, // VPGATHERDDZrm 0U, // VPGATHERDDrm 0U, // VPGATHERDQYrm 0U, // VPGATHERDQZ128rm 0U, // VPGATHERDQZ256rm 0U, // VPGATHERDQZrm 0U, // VPGATHERDQrm 0U, // VPGATHERQDYrm 0U, // VPGATHERQDZ128rm 0U, // VPGATHERQDZ256rm 0U, // VPGATHERQDZrm 0U, // VPGATHERQDrm 0U, // VPGATHERQQYrm 0U, // VPGATHERQQZ128rm 0U, // VPGATHERQQZ256rm 0U, // VPGATHERQQZrm 0U, // VPGATHERQQrm 0U, // VPHADDBDrm 0U, // VPHADDBDrr 0U, // VPHADDBQrm 0U, // VPHADDBQrr 0U, // VPHADDBWrm 0U, // VPHADDBWrr 0U, // VPHADDDQrm 0U, // VPHADDDQrr 0U, // VPHADDDYrm 0U, // VPHADDDYrr 0U, // VPHADDDrm 0U, // VPHADDDrr 0U, // VPHADDSWYrm 0U, // VPHADDSWYrr 0U, // VPHADDSWrm 0U, // VPHADDSWrr 0U, // VPHADDUBDrm 0U, // VPHADDUBDrr 0U, // VPHADDUBQrm 0U, // VPHADDUBQrr 0U, // VPHADDUBWrm 0U, // VPHADDUBWrr 0U, // VPHADDUDQrm 0U, // VPHADDUDQrr 0U, // VPHADDUWDrm 0U, // VPHADDUWDrr 0U, // VPHADDUWQrm 0U, // VPHADDUWQrr 0U, // VPHADDWDrm 0U, // VPHADDWDrr 0U, // VPHADDWQrm 0U, // VPHADDWQrr 0U, // VPHADDWYrm 0U, // VPHADDWYrr 0U, // VPHADDWrm 0U, // VPHADDWrr 0U, // VPHMINPOSUWrm 0U, // VPHMINPOSUWrr 0U, // VPHSUBBWrm 0U, // VPHSUBBWrr 0U, // VPHSUBDQrm 0U, // VPHSUBDQrr 0U, // VPHSUBDYrm 0U, // VPHSUBDYrr 0U, // VPHSUBDrm 0U, // VPHSUBDrr 0U, // VPHSUBSWYrm 0U, // VPHSUBSWYrr 0U, // VPHSUBSWrm 0U, // VPHSUBSWrr 0U, // VPHSUBWDrm 0U, // VPHSUBWDrr 0U, // VPHSUBWYrm 0U, // VPHSUBWYrr 0U, // VPHSUBWrm 0U, // VPHSUBWrr 0U, // VPINSRBZrm 0U, // VPINSRBZrr 0U, // VPINSRBrm 0U, // VPINSRBrr 0U, // VPINSRDZrm 0U, // VPINSRDZrr 0U, // VPINSRDrm 0U, // VPINSRDrr 0U, // VPINSRQZrm 0U, // VPINSRQZrr 0U, // VPINSRQrm 0U, // VPINSRQrr 0U, // VPINSRWZrm 0U, // VPINSRWZrr 0U, // VPINSRWrm 0U, // VPINSRWrr 0U, // VPLZCNTDZ128rm 0U, // VPLZCNTDZ128rmb 0U, // VPLZCNTDZ128rmbk 0U, // VPLZCNTDZ128rmbkz 0U, // VPLZCNTDZ128rmk 0U, // VPLZCNTDZ128rmkz 0U, // VPLZCNTDZ128rr 0U, // VPLZCNTDZ128rrk 0U, // VPLZCNTDZ128rrkz 0U, // VPLZCNTDZ256rm 0U, // VPLZCNTDZ256rmb 0U, // VPLZCNTDZ256rmbk 0U, // VPLZCNTDZ256rmbkz 0U, // VPLZCNTDZ256rmk 0U, // VPLZCNTDZ256rmkz 0U, // VPLZCNTDZ256rr 0U, // VPLZCNTDZ256rrk 0U, // VPLZCNTDZ256rrkz 0U, // VPLZCNTDZrm 0U, // VPLZCNTDZrmb 0U, // VPLZCNTDZrmbk 0U, // VPLZCNTDZrmbkz 0U, // VPLZCNTDZrmk 0U, // VPLZCNTDZrmkz 0U, // VPLZCNTDZrr 0U, // VPLZCNTDZrrk 0U, // VPLZCNTDZrrkz 0U, // VPLZCNTQZ128rm 0U, // VPLZCNTQZ128rmb 0U, // VPLZCNTQZ128rmbk 0U, // VPLZCNTQZ128rmbkz 0U, // VPLZCNTQZ128rmk 0U, // VPLZCNTQZ128rmkz 0U, // VPLZCNTQZ128rr 0U, // VPLZCNTQZ128rrk 0U, // VPLZCNTQZ128rrkz 0U, // VPLZCNTQZ256rm 0U, // VPLZCNTQZ256rmb 0U, // VPLZCNTQZ256rmbk 0U, // VPLZCNTQZ256rmbkz 0U, // VPLZCNTQZ256rmk 0U, // VPLZCNTQZ256rmkz 0U, // VPLZCNTQZ256rr 0U, // VPLZCNTQZ256rrk 0U, // VPLZCNTQZ256rrkz 0U, // VPLZCNTQZrm 0U, // VPLZCNTQZrmb 0U, // VPLZCNTQZrmbk 0U, // VPLZCNTQZrmbkz 0U, // VPLZCNTQZrmk 0U, // VPLZCNTQZrmkz 0U, // VPLZCNTQZrr 0U, // VPLZCNTQZrrk 0U, // VPLZCNTQZrrkz 0U, // VPMACSDDrm 0U, // VPMACSDDrr 0U, // VPMACSDQHrm 0U, // VPMACSDQHrr 0U, // VPMACSDQLrm 0U, // VPMACSDQLrr 0U, // VPMACSSDDrm 0U, // VPMACSSDDrr 0U, // VPMACSSDQHrm 0U, // VPMACSSDQHrr 0U, // VPMACSSDQLrm 0U, // VPMACSSDQLrr 0U, // VPMACSSWDrm 0U, // VPMACSSWDrr 0U, // VPMACSSWWrm 0U, // VPMACSSWWrr 0U, // VPMACSWDrm 0U, // VPMACSWDrr 0U, // VPMACSWWrm 0U, // VPMACSWWrr 0U, // VPMADCSSWDrm 0U, // VPMADCSSWDrr 0U, // VPMADCSWDrm 0U, // VPMADCSWDrr 0U, // VPMADD52HUQZ128m 0U, // VPMADD52HUQZ128mb 0U, // VPMADD52HUQZ128mbk 0U, // VPMADD52HUQZ128mbkz 0U, // VPMADD52HUQZ128mk 0U, // VPMADD52HUQZ128mkz 0U, // VPMADD52HUQZ128r 0U, // VPMADD52HUQZ128rk 0U, // VPMADD52HUQZ128rkz 0U, // VPMADD52HUQZ256m 0U, // VPMADD52HUQZ256mb 0U, // VPMADD52HUQZ256mbk 0U, // VPMADD52HUQZ256mbkz 0U, // VPMADD52HUQZ256mk 0U, // VPMADD52HUQZ256mkz 0U, // VPMADD52HUQZ256r 0U, // VPMADD52HUQZ256rk 0U, // VPMADD52HUQZ256rkz 0U, // VPMADD52HUQZm 0U, // VPMADD52HUQZmb 0U, // VPMADD52HUQZmbk 0U, // VPMADD52HUQZmbkz 0U, // VPMADD52HUQZmk 0U, // VPMADD52HUQZmkz 0U, // VPMADD52HUQZr 0U, // VPMADD52HUQZrk 0U, // VPMADD52HUQZrkz 0U, // VPMADD52LUQZ128m 0U, // VPMADD52LUQZ128mb 0U, // VPMADD52LUQZ128mbk 0U, // VPMADD52LUQZ128mbkz 0U, // VPMADD52LUQZ128mk 0U, // VPMADD52LUQZ128mkz 0U, // VPMADD52LUQZ128r 0U, // VPMADD52LUQZ128rk 0U, // VPMADD52LUQZ128rkz 0U, // VPMADD52LUQZ256m 0U, // VPMADD52LUQZ256mb 0U, // VPMADD52LUQZ256mbk 0U, // VPMADD52LUQZ256mbkz 0U, // VPMADD52LUQZ256mk 0U, // VPMADD52LUQZ256mkz 0U, // VPMADD52LUQZ256r 0U, // VPMADD52LUQZ256rk 0U, // VPMADD52LUQZ256rkz 0U, // VPMADD52LUQZm 0U, // VPMADD52LUQZmb 0U, // VPMADD52LUQZmbk 0U, // VPMADD52LUQZmbkz 0U, // VPMADD52LUQZmk 0U, // VPMADD52LUQZmkz 0U, // VPMADD52LUQZr 0U, // VPMADD52LUQZrk 0U, // VPMADD52LUQZrkz 0U, // VPMADDUBSWYrm 0U, // VPMADDUBSWYrr 0U, // VPMADDUBSWZ128rm 0U, // VPMADDUBSWZ128rmk 0U, // VPMADDUBSWZ128rmkz 0U, // VPMADDUBSWZ128rr 0U, // VPMADDUBSWZ128rrk 0U, // VPMADDUBSWZ128rrkz 0U, // VPMADDUBSWZ256rm 0U, // VPMADDUBSWZ256rmk 0U, // VPMADDUBSWZ256rmkz 0U, // VPMADDUBSWZ256rr 0U, // VPMADDUBSWZ256rrk 0U, // VPMADDUBSWZ256rrkz 0U, // VPMADDUBSWZrm 0U, // VPMADDUBSWZrmk 0U, // VPMADDUBSWZrmkz 0U, // VPMADDUBSWZrr 0U, // VPMADDUBSWZrrk 0U, // VPMADDUBSWZrrkz 0U, // VPMADDUBSWrm 0U, // VPMADDUBSWrr 0U, // VPMADDWDYrm 0U, // VPMADDWDYrr 0U, // VPMADDWDZ128rm 0U, // VPMADDWDZ128rmk 0U, // VPMADDWDZ128rmkz 0U, // VPMADDWDZ128rr 0U, // VPMADDWDZ128rrk 0U, // VPMADDWDZ128rrkz 0U, // VPMADDWDZ256rm 0U, // VPMADDWDZ256rmk 0U, // VPMADDWDZ256rmkz 0U, // VPMADDWDZ256rr 0U, // VPMADDWDZ256rrk 0U, // VPMADDWDZ256rrkz 0U, // VPMADDWDZrm 0U, // VPMADDWDZrmk 0U, // VPMADDWDZrmkz 0U, // VPMADDWDZrr 0U, // VPMADDWDZrrk 0U, // VPMADDWDZrrkz 0U, // VPMADDWDrm 0U, // VPMADDWDrr 0U, // VPMASKMOVDYmr 0U, // VPMASKMOVDYrm 0U, // VPMASKMOVDmr 0U, // VPMASKMOVDrm 0U, // VPMASKMOVQYmr 0U, // VPMASKMOVQYrm 0U, // VPMASKMOVQmr 0U, // VPMASKMOVQrm 0U, // VPMAXSBYrm 0U, // VPMAXSBYrr 0U, // VPMAXSBZ128rm 0U, // VPMAXSBZ128rmk 0U, // VPMAXSBZ128rmkz 0U, // VPMAXSBZ128rr 0U, // VPMAXSBZ128rrk 0U, // VPMAXSBZ128rrkz 0U, // VPMAXSBZ256rm 0U, // VPMAXSBZ256rmk 0U, // VPMAXSBZ256rmkz 0U, // VPMAXSBZ256rr 0U, // VPMAXSBZ256rrk 0U, // VPMAXSBZ256rrkz 0U, // VPMAXSBZrm 0U, // VPMAXSBZrmk 0U, // VPMAXSBZrmkz 0U, // VPMAXSBZrr 0U, // VPMAXSBZrrk 0U, // VPMAXSBZrrkz 0U, // VPMAXSBrm 0U, // VPMAXSBrr 0U, // VPMAXSDYrm 0U, // VPMAXSDYrr 0U, // VPMAXSDZ128rm 0U, // VPMAXSDZ128rmb 0U, // VPMAXSDZ128rmbk 0U, // VPMAXSDZ128rmbkz 0U, // VPMAXSDZ128rmk 0U, // VPMAXSDZ128rmkz 0U, // VPMAXSDZ128rr 0U, // VPMAXSDZ128rrk 0U, // VPMAXSDZ128rrkz 0U, // VPMAXSDZ256rm 0U, // VPMAXSDZ256rmb 0U, // VPMAXSDZ256rmbk 0U, // VPMAXSDZ256rmbkz 0U, // VPMAXSDZ256rmk 0U, // VPMAXSDZ256rmkz 0U, // VPMAXSDZ256rr 0U, // VPMAXSDZ256rrk 0U, // VPMAXSDZ256rrkz 0U, // VPMAXSDZrm 0U, // VPMAXSDZrmb 0U, // VPMAXSDZrmbk 0U, // VPMAXSDZrmbkz 0U, // VPMAXSDZrmk 0U, // VPMAXSDZrmkz 0U, // VPMAXSDZrr 0U, // VPMAXSDZrrk 0U, // VPMAXSDZrrkz 0U, // VPMAXSDrm 0U, // VPMAXSDrr 0U, // VPMAXSQZ128rm 0U, // VPMAXSQZ128rmb 0U, // VPMAXSQZ128rmbk 0U, // VPMAXSQZ128rmbkz 0U, // VPMAXSQZ128rmk 0U, // VPMAXSQZ128rmkz 0U, // VPMAXSQZ128rr 0U, // VPMAXSQZ128rrk 0U, // VPMAXSQZ128rrkz 0U, // VPMAXSQZ256rm 0U, // VPMAXSQZ256rmb 0U, // VPMAXSQZ256rmbk 0U, // VPMAXSQZ256rmbkz 0U, // VPMAXSQZ256rmk 0U, // VPMAXSQZ256rmkz 0U, // VPMAXSQZ256rr 0U, // VPMAXSQZ256rrk 0U, // VPMAXSQZ256rrkz 0U, // VPMAXSQZrm 0U, // VPMAXSQZrmb 0U, // VPMAXSQZrmbk 0U, // VPMAXSQZrmbkz 0U, // VPMAXSQZrmk 0U, // VPMAXSQZrmkz 0U, // VPMAXSQZrr 0U, // VPMAXSQZrrk 0U, // VPMAXSQZrrkz 0U, // VPMAXSWYrm 0U, // VPMAXSWYrr 0U, // VPMAXSWZ128rm 0U, // VPMAXSWZ128rmk 0U, // VPMAXSWZ128rmkz 0U, // VPMAXSWZ128rr 0U, // VPMAXSWZ128rrk 0U, // VPMAXSWZ128rrkz 0U, // VPMAXSWZ256rm 0U, // VPMAXSWZ256rmk 0U, // VPMAXSWZ256rmkz 0U, // VPMAXSWZ256rr 0U, // VPMAXSWZ256rrk 0U, // VPMAXSWZ256rrkz 0U, // VPMAXSWZrm 0U, // VPMAXSWZrmk 0U, // VPMAXSWZrmkz 0U, // VPMAXSWZrr 0U, // VPMAXSWZrrk 0U, // VPMAXSWZrrkz 0U, // VPMAXSWrm 0U, // VPMAXSWrr 0U, // VPMAXUBYrm 0U, // VPMAXUBYrr 0U, // VPMAXUBZ128rm 0U, // VPMAXUBZ128rmk 0U, // VPMAXUBZ128rmkz 0U, // VPMAXUBZ128rr 0U, // VPMAXUBZ128rrk 0U, // VPMAXUBZ128rrkz 0U, // VPMAXUBZ256rm 0U, // VPMAXUBZ256rmk 0U, // VPMAXUBZ256rmkz 0U, // VPMAXUBZ256rr 0U, // VPMAXUBZ256rrk 0U, // VPMAXUBZ256rrkz 0U, // VPMAXUBZrm 0U, // VPMAXUBZrmk 0U, // VPMAXUBZrmkz 0U, // VPMAXUBZrr 0U, // VPMAXUBZrrk 0U, // VPMAXUBZrrkz 0U, // VPMAXUBrm 0U, // VPMAXUBrr 0U, // VPMAXUDYrm 0U, // VPMAXUDYrr 0U, // VPMAXUDZ128rm 0U, // VPMAXUDZ128rmb 0U, // VPMAXUDZ128rmbk 0U, // VPMAXUDZ128rmbkz 0U, // VPMAXUDZ128rmk 0U, // VPMAXUDZ128rmkz 0U, // VPMAXUDZ128rr 0U, // VPMAXUDZ128rrk 0U, // VPMAXUDZ128rrkz 0U, // VPMAXUDZ256rm 0U, // VPMAXUDZ256rmb 0U, // VPMAXUDZ256rmbk 0U, // VPMAXUDZ256rmbkz 0U, // VPMAXUDZ256rmk 0U, // VPMAXUDZ256rmkz 0U, // VPMAXUDZ256rr 0U, // VPMAXUDZ256rrk 0U, // VPMAXUDZ256rrkz 0U, // VPMAXUDZrm 0U, // VPMAXUDZrmb 0U, // VPMAXUDZrmbk 0U, // VPMAXUDZrmbkz 0U, // VPMAXUDZrmk 0U, // VPMAXUDZrmkz 0U, // VPMAXUDZrr 0U, // VPMAXUDZrrk 0U, // VPMAXUDZrrkz 0U, // VPMAXUDrm 0U, // VPMAXUDrr 0U, // VPMAXUQZ128rm 0U, // VPMAXUQZ128rmb 0U, // VPMAXUQZ128rmbk 0U, // VPMAXUQZ128rmbkz 0U, // VPMAXUQZ128rmk 0U, // VPMAXUQZ128rmkz 0U, // VPMAXUQZ128rr 0U, // VPMAXUQZ128rrk 0U, // VPMAXUQZ128rrkz 0U, // VPMAXUQZ256rm 0U, // VPMAXUQZ256rmb 0U, // VPMAXUQZ256rmbk 0U, // VPMAXUQZ256rmbkz 0U, // VPMAXUQZ256rmk 0U, // VPMAXUQZ256rmkz 0U, // VPMAXUQZ256rr 0U, // VPMAXUQZ256rrk 0U, // VPMAXUQZ256rrkz 0U, // VPMAXUQZrm 0U, // VPMAXUQZrmb 0U, // VPMAXUQZrmbk 0U, // VPMAXUQZrmbkz 0U, // VPMAXUQZrmk 0U, // VPMAXUQZrmkz 0U, // VPMAXUQZrr 0U, // VPMAXUQZrrk 0U, // VPMAXUQZrrkz 0U, // VPMAXUWYrm 0U, // VPMAXUWYrr 0U, // VPMAXUWZ128rm 0U, // VPMAXUWZ128rmk 0U, // VPMAXUWZ128rmkz 0U, // VPMAXUWZ128rr 0U, // VPMAXUWZ128rrk 0U, // VPMAXUWZ128rrkz 0U, // VPMAXUWZ256rm 0U, // VPMAXUWZ256rmk 0U, // VPMAXUWZ256rmkz 0U, // VPMAXUWZ256rr 0U, // VPMAXUWZ256rrk 0U, // VPMAXUWZ256rrkz 0U, // VPMAXUWZrm 0U, // VPMAXUWZrmk 0U, // VPMAXUWZrmkz 0U, // VPMAXUWZrr 0U, // VPMAXUWZrrk 0U, // VPMAXUWZrrkz 0U, // VPMAXUWrm 0U, // VPMAXUWrr 0U, // VPMINSBYrm 0U, // VPMINSBYrr 0U, // VPMINSBZ128rm 0U, // VPMINSBZ128rmk 0U, // VPMINSBZ128rmkz 0U, // VPMINSBZ128rr 0U, // VPMINSBZ128rrk 0U, // VPMINSBZ128rrkz 0U, // VPMINSBZ256rm 0U, // VPMINSBZ256rmk 0U, // VPMINSBZ256rmkz 0U, // VPMINSBZ256rr 0U, // VPMINSBZ256rrk 0U, // VPMINSBZ256rrkz 0U, // VPMINSBZrm 0U, // VPMINSBZrmk 0U, // VPMINSBZrmkz 0U, // VPMINSBZrr 0U, // VPMINSBZrrk 0U, // VPMINSBZrrkz 0U, // VPMINSBrm 0U, // VPMINSBrr 0U, // VPMINSDYrm 0U, // VPMINSDYrr 0U, // VPMINSDZ128rm 0U, // VPMINSDZ128rmb 0U, // VPMINSDZ128rmbk 0U, // VPMINSDZ128rmbkz 0U, // VPMINSDZ128rmk 0U, // VPMINSDZ128rmkz 0U, // VPMINSDZ128rr 0U, // VPMINSDZ128rrk 0U, // VPMINSDZ128rrkz 0U, // VPMINSDZ256rm 0U, // VPMINSDZ256rmb 0U, // VPMINSDZ256rmbk 0U, // VPMINSDZ256rmbkz 0U, // VPMINSDZ256rmk 0U, // VPMINSDZ256rmkz 0U, // VPMINSDZ256rr 0U, // VPMINSDZ256rrk 0U, // VPMINSDZ256rrkz 0U, // VPMINSDZrm 0U, // VPMINSDZrmb 0U, // VPMINSDZrmbk 0U, // VPMINSDZrmbkz 0U, // VPMINSDZrmk 0U, // VPMINSDZrmkz 0U, // VPMINSDZrr 0U, // VPMINSDZrrk 0U, // VPMINSDZrrkz 0U, // VPMINSDrm 0U, // VPMINSDrr 0U, // VPMINSQZ128rm 0U, // VPMINSQZ128rmb 0U, // VPMINSQZ128rmbk 0U, // VPMINSQZ128rmbkz 0U, // VPMINSQZ128rmk 0U, // VPMINSQZ128rmkz 0U, // VPMINSQZ128rr 0U, // VPMINSQZ128rrk 0U, // VPMINSQZ128rrkz 0U, // VPMINSQZ256rm 0U, // VPMINSQZ256rmb 0U, // VPMINSQZ256rmbk 0U, // VPMINSQZ256rmbkz 0U, // VPMINSQZ256rmk 0U, // VPMINSQZ256rmkz 0U, // VPMINSQZ256rr 0U, // VPMINSQZ256rrk 0U, // VPMINSQZ256rrkz 0U, // VPMINSQZrm 0U, // VPMINSQZrmb 0U, // VPMINSQZrmbk 0U, // VPMINSQZrmbkz 0U, // VPMINSQZrmk 0U, // VPMINSQZrmkz 0U, // VPMINSQZrr 0U, // VPMINSQZrrk 0U, // VPMINSQZrrkz 0U, // VPMINSWYrm 0U, // VPMINSWYrr 0U, // VPMINSWZ128rm 0U, // VPMINSWZ128rmk 0U, // VPMINSWZ128rmkz 0U, // VPMINSWZ128rr 0U, // VPMINSWZ128rrk 0U, // VPMINSWZ128rrkz 0U, // VPMINSWZ256rm 0U, // VPMINSWZ256rmk 0U, // VPMINSWZ256rmkz 0U, // VPMINSWZ256rr 0U, // VPMINSWZ256rrk 0U, // VPMINSWZ256rrkz 0U, // VPMINSWZrm 0U, // VPMINSWZrmk 0U, // VPMINSWZrmkz 0U, // VPMINSWZrr 0U, // VPMINSWZrrk 0U, // VPMINSWZrrkz 0U, // VPMINSWrm 0U, // VPMINSWrr 0U, // VPMINUBYrm 0U, // VPMINUBYrr 0U, // VPMINUBZ128rm 0U, // VPMINUBZ128rmk 0U, // VPMINUBZ128rmkz 0U, // VPMINUBZ128rr 0U, // VPMINUBZ128rrk 0U, // VPMINUBZ128rrkz 0U, // VPMINUBZ256rm 0U, // VPMINUBZ256rmk 0U, // VPMINUBZ256rmkz 0U, // VPMINUBZ256rr 0U, // VPMINUBZ256rrk 0U, // VPMINUBZ256rrkz 0U, // VPMINUBZrm 0U, // VPMINUBZrmk 0U, // VPMINUBZrmkz 0U, // VPMINUBZrr 0U, // VPMINUBZrrk 0U, // VPMINUBZrrkz 0U, // VPMINUBrm 0U, // VPMINUBrr 0U, // VPMINUDYrm 0U, // VPMINUDYrr 0U, // VPMINUDZ128rm 0U, // VPMINUDZ128rmb 0U, // VPMINUDZ128rmbk 0U, // VPMINUDZ128rmbkz 0U, // VPMINUDZ128rmk 0U, // VPMINUDZ128rmkz 0U, // VPMINUDZ128rr 0U, // VPMINUDZ128rrk 0U, // VPMINUDZ128rrkz 0U, // VPMINUDZ256rm 0U, // VPMINUDZ256rmb 0U, // VPMINUDZ256rmbk 0U, // VPMINUDZ256rmbkz 0U, // VPMINUDZ256rmk 0U, // VPMINUDZ256rmkz 0U, // VPMINUDZ256rr 0U, // VPMINUDZ256rrk 0U, // VPMINUDZ256rrkz 0U, // VPMINUDZrm 0U, // VPMINUDZrmb 0U, // VPMINUDZrmbk 0U, // VPMINUDZrmbkz 0U, // VPMINUDZrmk 0U, // VPMINUDZrmkz 0U, // VPMINUDZrr 0U, // VPMINUDZrrk 0U, // VPMINUDZrrkz 0U, // VPMINUDrm 0U, // VPMINUDrr 0U, // VPMINUQZ128rm 0U, // VPMINUQZ128rmb 0U, // VPMINUQZ128rmbk 0U, // VPMINUQZ128rmbkz 0U, // VPMINUQZ128rmk 0U, // VPMINUQZ128rmkz 0U, // VPMINUQZ128rr 0U, // VPMINUQZ128rrk 0U, // VPMINUQZ128rrkz 0U, // VPMINUQZ256rm 0U, // VPMINUQZ256rmb 0U, // VPMINUQZ256rmbk 0U, // VPMINUQZ256rmbkz 0U, // VPMINUQZ256rmk 0U, // VPMINUQZ256rmkz 0U, // VPMINUQZ256rr 0U, // VPMINUQZ256rrk 0U, // VPMINUQZ256rrkz 0U, // VPMINUQZrm 0U, // VPMINUQZrmb 0U, // VPMINUQZrmbk 0U, // VPMINUQZrmbkz 0U, // VPMINUQZrmk 0U, // VPMINUQZrmkz 0U, // VPMINUQZrr 0U, // VPMINUQZrrk 0U, // VPMINUQZrrkz 0U, // VPMINUWYrm 0U, // VPMINUWYrr 0U, // VPMINUWZ128rm 0U, // VPMINUWZ128rmk 0U, // VPMINUWZ128rmkz 0U, // VPMINUWZ128rr 0U, // VPMINUWZ128rrk 0U, // VPMINUWZ128rrkz 0U, // VPMINUWZ256rm 0U, // VPMINUWZ256rmk 0U, // VPMINUWZ256rmkz 0U, // VPMINUWZ256rr 0U, // VPMINUWZ256rrk 0U, // VPMINUWZ256rrkz 0U, // VPMINUWZrm 0U, // VPMINUWZrmk 0U, // VPMINUWZrmkz 0U, // VPMINUWZrr 0U, // VPMINUWZrrk 0U, // VPMINUWZrrkz 0U, // VPMINUWrm 0U, // VPMINUWrr 0U, // VPMOVB2MZ128rr 0U, // VPMOVB2MZ256rr 0U, // VPMOVB2MZrr 0U, // VPMOVD2MZ128rr 0U, // VPMOVD2MZ256rr 0U, // VPMOVD2MZrr 0U, // VPMOVDBZ128mr 0U, // VPMOVDBZ128mrk 0U, // VPMOVDBZ128rr 0U, // VPMOVDBZ128rrk 0U, // VPMOVDBZ128rrkz 0U, // VPMOVDBZ256mr 0U, // VPMOVDBZ256mrk 0U, // VPMOVDBZ256rr 0U, // VPMOVDBZ256rrk 0U, // VPMOVDBZ256rrkz 0U, // VPMOVDBZmr 0U, // VPMOVDBZmrk 0U, // VPMOVDBZrr 0U, // VPMOVDBZrrk 0U, // VPMOVDBZrrkz 0U, // VPMOVDWZ128mr 0U, // VPMOVDWZ128mrk 0U, // VPMOVDWZ128rr 0U, // VPMOVDWZ128rrk 0U, // VPMOVDWZ128rrkz 0U, // VPMOVDWZ256mr 0U, // VPMOVDWZ256mrk 0U, // VPMOVDWZ256rr 0U, // VPMOVDWZ256rrk 0U, // VPMOVDWZ256rrkz 0U, // VPMOVDWZmr 0U, // VPMOVDWZmrk 0U, // VPMOVDWZrr 0U, // VPMOVDWZrrk 0U, // VPMOVDWZrrkz 0U, // VPMOVM2BZ128rr 0U, // VPMOVM2BZ256rr 0U, // VPMOVM2BZrr 0U, // VPMOVM2DZ128rr 0U, // VPMOVM2DZ256rr 0U, // VPMOVM2DZrr 0U, // VPMOVM2QZ128rr 0U, // VPMOVM2QZ256rr 0U, // VPMOVM2QZrr 0U, // VPMOVM2WZ128rr 0U, // VPMOVM2WZ256rr 0U, // VPMOVM2WZrr 0U, // VPMOVMSKBYrr 0U, // VPMOVMSKBrr 0U, // VPMOVQ2MZ128rr 0U, // VPMOVQ2MZ256rr 0U, // VPMOVQ2MZrr 0U, // VPMOVQBZ128mr 0U, // VPMOVQBZ128mrk 0U, // VPMOVQBZ128rr 0U, // VPMOVQBZ128rrk 0U, // VPMOVQBZ128rrkz 0U, // VPMOVQBZ256mr 0U, // VPMOVQBZ256mrk 0U, // VPMOVQBZ256rr 0U, // VPMOVQBZ256rrk 0U, // VPMOVQBZ256rrkz 0U, // VPMOVQBZmr 0U, // VPMOVQBZmrk 0U, // VPMOVQBZrr 0U, // VPMOVQBZrrk 0U, // VPMOVQBZrrkz 0U, // VPMOVQDZ128mr 0U, // VPMOVQDZ128mrk 0U, // VPMOVQDZ128rr 0U, // VPMOVQDZ128rrk 0U, // VPMOVQDZ128rrkz 0U, // VPMOVQDZ256mr 0U, // VPMOVQDZ256mrk 0U, // VPMOVQDZ256rr 0U, // VPMOVQDZ256rrk 0U, // VPMOVQDZ256rrkz 0U, // VPMOVQDZmr 0U, // VPMOVQDZmrk 0U, // VPMOVQDZrr 0U, // VPMOVQDZrrk 0U, // VPMOVQDZrrkz 0U, // VPMOVQWZ128mr 0U, // VPMOVQWZ128mrk 0U, // VPMOVQWZ128rr 0U, // VPMOVQWZ128rrk 0U, // VPMOVQWZ128rrkz 0U, // VPMOVQWZ256mr 0U, // VPMOVQWZ256mrk 0U, // VPMOVQWZ256rr 0U, // VPMOVQWZ256rrk 0U, // VPMOVQWZ256rrkz 0U, // VPMOVQWZmr 0U, // VPMOVQWZmrk 0U, // VPMOVQWZrr 0U, // VPMOVQWZrrk 0U, // VPMOVQWZrrkz 0U, // VPMOVSDBZ128mr 0U, // VPMOVSDBZ128mrk 0U, // VPMOVSDBZ128rr 0U, // VPMOVSDBZ128rrk 0U, // VPMOVSDBZ128rrkz 0U, // VPMOVSDBZ256mr 0U, // VPMOVSDBZ256mrk 0U, // VPMOVSDBZ256rr 0U, // VPMOVSDBZ256rrk 0U, // VPMOVSDBZ256rrkz 0U, // VPMOVSDBZmr 0U, // VPMOVSDBZmrk 0U, // VPMOVSDBZrr 0U, // VPMOVSDBZrrk 0U, // VPMOVSDBZrrkz 0U, // VPMOVSDWZ128mr 0U, // VPMOVSDWZ128mrk 0U, // VPMOVSDWZ128rr 0U, // VPMOVSDWZ128rrk 0U, // VPMOVSDWZ128rrkz 0U, // VPMOVSDWZ256mr 0U, // VPMOVSDWZ256mrk 0U, // VPMOVSDWZ256rr 0U, // VPMOVSDWZ256rrk 0U, // VPMOVSDWZ256rrkz 0U, // VPMOVSDWZmr 0U, // VPMOVSDWZmrk 0U, // VPMOVSDWZrr 0U, // VPMOVSDWZrrk 0U, // VPMOVSDWZrrkz 0U, // VPMOVSQBZ128mr 0U, // VPMOVSQBZ128mrk 0U, // VPMOVSQBZ128rr 0U, // VPMOVSQBZ128rrk 0U, // VPMOVSQBZ128rrkz 0U, // VPMOVSQBZ256mr 0U, // VPMOVSQBZ256mrk 0U, // VPMOVSQBZ256rr 0U, // VPMOVSQBZ256rrk 0U, // VPMOVSQBZ256rrkz 0U, // VPMOVSQBZmr 0U, // VPMOVSQBZmrk 0U, // VPMOVSQBZrr 0U, // VPMOVSQBZrrk 0U, // VPMOVSQBZrrkz 0U, // VPMOVSQDZ128mr 0U, // VPMOVSQDZ128mrk 0U, // VPMOVSQDZ128rr 0U, // VPMOVSQDZ128rrk 0U, // VPMOVSQDZ128rrkz 0U, // VPMOVSQDZ256mr 0U, // VPMOVSQDZ256mrk 0U, // VPMOVSQDZ256rr 0U, // VPMOVSQDZ256rrk 0U, // VPMOVSQDZ256rrkz 0U, // VPMOVSQDZmr 0U, // VPMOVSQDZmrk 0U, // VPMOVSQDZrr 0U, // VPMOVSQDZrrk 0U, // VPMOVSQDZrrkz 0U, // VPMOVSQWZ128mr 0U, // VPMOVSQWZ128mrk 0U, // VPMOVSQWZ128rr 0U, // VPMOVSQWZ128rrk 0U, // VPMOVSQWZ128rrkz 0U, // VPMOVSQWZ256mr 0U, // VPMOVSQWZ256mrk 0U, // VPMOVSQWZ256rr 0U, // VPMOVSQWZ256rrk 0U, // VPMOVSQWZ256rrkz 0U, // VPMOVSQWZmr 0U, // VPMOVSQWZmrk 0U, // VPMOVSQWZrr 0U, // VPMOVSQWZrrk 0U, // VPMOVSQWZrrkz 0U, // VPMOVSWBZ128mr 0U, // VPMOVSWBZ128mrk 0U, // VPMOVSWBZ128rr 0U, // VPMOVSWBZ128rrk 0U, // VPMOVSWBZ128rrkz 0U, // VPMOVSWBZ256mr 0U, // VPMOVSWBZ256mrk 0U, // VPMOVSWBZ256rr 0U, // VPMOVSWBZ256rrk 0U, // VPMOVSWBZ256rrkz 0U, // VPMOVSWBZmr 0U, // VPMOVSWBZmrk 0U, // VPMOVSWBZrr 0U, // VPMOVSWBZrrk 0U, // VPMOVSWBZrrkz 0U, // VPMOVSXBDYrm 0U, // VPMOVSXBDYrr 0U, // VPMOVSXBDZ128rm 0U, // VPMOVSXBDZ128rmk 0U, // VPMOVSXBDZ128rmkz 0U, // VPMOVSXBDZ128rr 0U, // VPMOVSXBDZ128rrk 0U, // VPMOVSXBDZ128rrkz 0U, // VPMOVSXBDZ256rm 0U, // VPMOVSXBDZ256rmk 0U, // VPMOVSXBDZ256rmkz 0U, // VPMOVSXBDZ256rr 0U, // VPMOVSXBDZ256rrk 0U, // VPMOVSXBDZ256rrkz 0U, // VPMOVSXBDZrm 0U, // VPMOVSXBDZrmk 0U, // VPMOVSXBDZrmkz 0U, // VPMOVSXBDZrr 0U, // VPMOVSXBDZrrk 0U, // VPMOVSXBDZrrkz 0U, // VPMOVSXBDrm 0U, // VPMOVSXBDrr 0U, // VPMOVSXBQYrm 0U, // VPMOVSXBQYrr 0U, // VPMOVSXBQZ128rm 0U, // VPMOVSXBQZ128rmk 0U, // VPMOVSXBQZ128rmkz 0U, // VPMOVSXBQZ128rr 0U, // VPMOVSXBQZ128rrk 0U, // VPMOVSXBQZ128rrkz 0U, // VPMOVSXBQZ256rm 0U, // VPMOVSXBQZ256rmk 0U, // VPMOVSXBQZ256rmkz 0U, // VPMOVSXBQZ256rr 0U, // VPMOVSXBQZ256rrk 0U, // VPMOVSXBQZ256rrkz 0U, // VPMOVSXBQZrm 0U, // VPMOVSXBQZrmk 0U, // VPMOVSXBQZrmkz 0U, // VPMOVSXBQZrr 0U, // VPMOVSXBQZrrk 0U, // VPMOVSXBQZrrkz 0U, // VPMOVSXBQrm 0U, // VPMOVSXBQrr 0U, // VPMOVSXBWYrm 0U, // VPMOVSXBWYrr 0U, // VPMOVSXBWZ128rm 0U, // VPMOVSXBWZ128rmk 0U, // VPMOVSXBWZ128rmkz 0U, // VPMOVSXBWZ128rr 0U, // VPMOVSXBWZ128rrk 0U, // VPMOVSXBWZ128rrkz 0U, // VPMOVSXBWZ256rm 0U, // VPMOVSXBWZ256rmk 0U, // VPMOVSXBWZ256rmkz 0U, // VPMOVSXBWZ256rr 0U, // VPMOVSXBWZ256rrk 0U, // VPMOVSXBWZ256rrkz 0U, // VPMOVSXBWZrm 0U, // VPMOVSXBWZrmk 0U, // VPMOVSXBWZrmkz 0U, // VPMOVSXBWZrr 0U, // VPMOVSXBWZrrk 0U, // VPMOVSXBWZrrkz 0U, // VPMOVSXBWrm 0U, // VPMOVSXBWrr 0U, // VPMOVSXDQYrm 0U, // VPMOVSXDQYrr 0U, // VPMOVSXDQZ128rm 0U, // VPMOVSXDQZ128rmk 0U, // VPMOVSXDQZ128rmkz 0U, // VPMOVSXDQZ128rr 0U, // VPMOVSXDQZ128rrk 0U, // VPMOVSXDQZ128rrkz 0U, // VPMOVSXDQZ256rm 0U, // VPMOVSXDQZ256rmk 0U, // VPMOVSXDQZ256rmkz 0U, // VPMOVSXDQZ256rr 0U, // VPMOVSXDQZ256rrk 0U, // VPMOVSXDQZ256rrkz 0U, // VPMOVSXDQZrm 0U, // VPMOVSXDQZrmk 0U, // VPMOVSXDQZrmkz 0U, // VPMOVSXDQZrr 0U, // VPMOVSXDQZrrk 0U, // VPMOVSXDQZrrkz 0U, // VPMOVSXDQrm 0U, // VPMOVSXDQrr 0U, // VPMOVSXWDYrm 0U, // VPMOVSXWDYrr 0U, // VPMOVSXWDZ128rm 0U, // VPMOVSXWDZ128rmk 0U, // VPMOVSXWDZ128rmkz 0U, // VPMOVSXWDZ128rr 0U, // VPMOVSXWDZ128rrk 0U, // VPMOVSXWDZ128rrkz 0U, // VPMOVSXWDZ256rm 0U, // VPMOVSXWDZ256rmk 0U, // VPMOVSXWDZ256rmkz 0U, // VPMOVSXWDZ256rr 0U, // VPMOVSXWDZ256rrk 0U, // VPMOVSXWDZ256rrkz 0U, // VPMOVSXWDZrm 0U, // VPMOVSXWDZrmk 0U, // VPMOVSXWDZrmkz 0U, // VPMOVSXWDZrr 0U, // VPMOVSXWDZrrk 0U, // VPMOVSXWDZrrkz 0U, // VPMOVSXWDrm 0U, // VPMOVSXWDrr 0U, // VPMOVSXWQYrm 0U, // VPMOVSXWQYrr 0U, // VPMOVSXWQZ128rm 0U, // VPMOVSXWQZ128rmk 0U, // VPMOVSXWQZ128rmkz 0U, // VPMOVSXWQZ128rr 0U, // VPMOVSXWQZ128rrk 0U, // VPMOVSXWQZ128rrkz 0U, // VPMOVSXWQZ256rm 0U, // VPMOVSXWQZ256rmk 0U, // VPMOVSXWQZ256rmkz 0U, // VPMOVSXWQZ256rr 0U, // VPMOVSXWQZ256rrk 0U, // VPMOVSXWQZ256rrkz 0U, // VPMOVSXWQZrm 0U, // VPMOVSXWQZrmk 0U, // VPMOVSXWQZrmkz 0U, // VPMOVSXWQZrr 0U, // VPMOVSXWQZrrk 0U, // VPMOVSXWQZrrkz 0U, // VPMOVSXWQrm 0U, // VPMOVSXWQrr 0U, // VPMOVUSDBZ128mr 0U, // VPMOVUSDBZ128mrk 0U, // VPMOVUSDBZ128rr 0U, // VPMOVUSDBZ128rrk 0U, // VPMOVUSDBZ128rrkz 0U, // VPMOVUSDBZ256mr 0U, // VPMOVUSDBZ256mrk 0U, // VPMOVUSDBZ256rr 0U, // VPMOVUSDBZ256rrk 0U, // VPMOVUSDBZ256rrkz 0U, // VPMOVUSDBZmr 0U, // VPMOVUSDBZmrk 0U, // VPMOVUSDBZrr 0U, // VPMOVUSDBZrrk 0U, // VPMOVUSDBZrrkz 0U, // VPMOVUSDWZ128mr 0U, // VPMOVUSDWZ128mrk 0U, // VPMOVUSDWZ128rr 0U, // VPMOVUSDWZ128rrk 0U, // VPMOVUSDWZ128rrkz 0U, // VPMOVUSDWZ256mr 0U, // VPMOVUSDWZ256mrk 0U, // VPMOVUSDWZ256rr 0U, // VPMOVUSDWZ256rrk 0U, // VPMOVUSDWZ256rrkz 0U, // VPMOVUSDWZmr 0U, // VPMOVUSDWZmrk 0U, // VPMOVUSDWZrr 0U, // VPMOVUSDWZrrk 0U, // VPMOVUSDWZrrkz 0U, // VPMOVUSQBZ128mr 0U, // VPMOVUSQBZ128mrk 0U, // VPMOVUSQBZ128rr 0U, // VPMOVUSQBZ128rrk 0U, // VPMOVUSQBZ128rrkz 0U, // VPMOVUSQBZ256mr 0U, // VPMOVUSQBZ256mrk 0U, // VPMOVUSQBZ256rr 0U, // VPMOVUSQBZ256rrk 0U, // VPMOVUSQBZ256rrkz 0U, // VPMOVUSQBZmr 0U, // VPMOVUSQBZmrk 0U, // VPMOVUSQBZrr 0U, // VPMOVUSQBZrrk 0U, // VPMOVUSQBZrrkz 0U, // VPMOVUSQDZ128mr 0U, // VPMOVUSQDZ128mrk 0U, // VPMOVUSQDZ128rr 0U, // VPMOVUSQDZ128rrk 0U, // VPMOVUSQDZ128rrkz 0U, // VPMOVUSQDZ256mr 0U, // VPMOVUSQDZ256mrk 0U, // VPMOVUSQDZ256rr 0U, // VPMOVUSQDZ256rrk 0U, // VPMOVUSQDZ256rrkz 0U, // VPMOVUSQDZmr 0U, // VPMOVUSQDZmrk 0U, // VPMOVUSQDZrr 0U, // VPMOVUSQDZrrk 0U, // VPMOVUSQDZrrkz 0U, // VPMOVUSQWZ128mr 0U, // VPMOVUSQWZ128mrk 0U, // VPMOVUSQWZ128rr 0U, // VPMOVUSQWZ128rrk 0U, // VPMOVUSQWZ128rrkz 0U, // VPMOVUSQWZ256mr 0U, // VPMOVUSQWZ256mrk 0U, // VPMOVUSQWZ256rr 0U, // VPMOVUSQWZ256rrk 0U, // VPMOVUSQWZ256rrkz 0U, // VPMOVUSQWZmr 0U, // VPMOVUSQWZmrk 0U, // VPMOVUSQWZrr 0U, // VPMOVUSQWZrrk 0U, // VPMOVUSQWZrrkz 0U, // VPMOVUSWBZ128mr 0U, // VPMOVUSWBZ128mrk 0U, // VPMOVUSWBZ128rr 0U, // VPMOVUSWBZ128rrk 0U, // VPMOVUSWBZ128rrkz 0U, // VPMOVUSWBZ256mr 0U, // VPMOVUSWBZ256mrk 0U, // VPMOVUSWBZ256rr 0U, // VPMOVUSWBZ256rrk 0U, // VPMOVUSWBZ256rrkz 0U, // VPMOVUSWBZmr 0U, // VPMOVUSWBZmrk 0U, // VPMOVUSWBZrr 0U, // VPMOVUSWBZrrk 0U, // VPMOVUSWBZrrkz 0U, // VPMOVW2MZ128rr 0U, // VPMOVW2MZ256rr 0U, // VPMOVW2MZrr 0U, // VPMOVWBZ128mr 0U, // VPMOVWBZ128mrk 0U, // VPMOVWBZ128rr 0U, // VPMOVWBZ128rrk 0U, // VPMOVWBZ128rrkz 0U, // VPMOVWBZ256mr 0U, // VPMOVWBZ256mrk 0U, // VPMOVWBZ256rr 0U, // VPMOVWBZ256rrk 0U, // VPMOVWBZ256rrkz 0U, // VPMOVWBZmr 0U, // VPMOVWBZmrk 0U, // VPMOVWBZrr 0U, // VPMOVWBZrrk 0U, // VPMOVWBZrrkz 0U, // VPMOVZXBDYrm 0U, // VPMOVZXBDYrr 0U, // VPMOVZXBDZ128rm 0U, // VPMOVZXBDZ128rmk 0U, // VPMOVZXBDZ128rmkz 0U, // VPMOVZXBDZ128rr 0U, // VPMOVZXBDZ128rrk 0U, // VPMOVZXBDZ128rrkz 0U, // VPMOVZXBDZ256rm 0U, // VPMOVZXBDZ256rmk 0U, // VPMOVZXBDZ256rmkz 0U, // VPMOVZXBDZ256rr 0U, // VPMOVZXBDZ256rrk 0U, // VPMOVZXBDZ256rrkz 0U, // VPMOVZXBDZrm 0U, // VPMOVZXBDZrmk 0U, // VPMOVZXBDZrmkz 0U, // VPMOVZXBDZrr 0U, // VPMOVZXBDZrrk 0U, // VPMOVZXBDZrrkz 0U, // VPMOVZXBDrm 0U, // VPMOVZXBDrr 0U, // VPMOVZXBQYrm 0U, // VPMOVZXBQYrr 0U, // VPMOVZXBQZ128rm 0U, // VPMOVZXBQZ128rmk 0U, // VPMOVZXBQZ128rmkz 0U, // VPMOVZXBQZ128rr 0U, // VPMOVZXBQZ128rrk 0U, // VPMOVZXBQZ128rrkz 0U, // VPMOVZXBQZ256rm 0U, // VPMOVZXBQZ256rmk 0U, // VPMOVZXBQZ256rmkz 0U, // VPMOVZXBQZ256rr 0U, // VPMOVZXBQZ256rrk 0U, // VPMOVZXBQZ256rrkz 0U, // VPMOVZXBQZrm 0U, // VPMOVZXBQZrmk 0U, // VPMOVZXBQZrmkz 0U, // VPMOVZXBQZrr 0U, // VPMOVZXBQZrrk 0U, // VPMOVZXBQZrrkz 0U, // VPMOVZXBQrm 0U, // VPMOVZXBQrr 0U, // VPMOVZXBWYrm 0U, // VPMOVZXBWYrr 0U, // VPMOVZXBWZ128rm 0U, // VPMOVZXBWZ128rmk 0U, // VPMOVZXBWZ128rmkz 0U, // VPMOVZXBWZ128rr 0U, // VPMOVZXBWZ128rrk 0U, // VPMOVZXBWZ128rrkz 0U, // VPMOVZXBWZ256rm 0U, // VPMOVZXBWZ256rmk 0U, // VPMOVZXBWZ256rmkz 0U, // VPMOVZXBWZ256rr 0U, // VPMOVZXBWZ256rrk 0U, // VPMOVZXBWZ256rrkz 0U, // VPMOVZXBWZrm 0U, // VPMOVZXBWZrmk 0U, // VPMOVZXBWZrmkz 0U, // VPMOVZXBWZrr 0U, // VPMOVZXBWZrrk 0U, // VPMOVZXBWZrrkz 0U, // VPMOVZXBWrm 0U, // VPMOVZXBWrr 0U, // VPMOVZXDQYrm 0U, // VPMOVZXDQYrr 0U, // VPMOVZXDQZ128rm 0U, // VPMOVZXDQZ128rmk 0U, // VPMOVZXDQZ128rmkz 0U, // VPMOVZXDQZ128rr 0U, // VPMOVZXDQZ128rrk 0U, // VPMOVZXDQZ128rrkz 0U, // VPMOVZXDQZ256rm 0U, // VPMOVZXDQZ256rmk 0U, // VPMOVZXDQZ256rmkz 0U, // VPMOVZXDQZ256rr 0U, // VPMOVZXDQZ256rrk 0U, // VPMOVZXDQZ256rrkz 0U, // VPMOVZXDQZrm 0U, // VPMOVZXDQZrmk 0U, // VPMOVZXDQZrmkz 0U, // VPMOVZXDQZrr 0U, // VPMOVZXDQZrrk 0U, // VPMOVZXDQZrrkz 0U, // VPMOVZXDQrm 0U, // VPMOVZXDQrr 0U, // VPMOVZXWDYrm 0U, // VPMOVZXWDYrr 0U, // VPMOVZXWDZ128rm 0U, // VPMOVZXWDZ128rmk 0U, // VPMOVZXWDZ128rmkz 0U, // VPMOVZXWDZ128rr 0U, // VPMOVZXWDZ128rrk 0U, // VPMOVZXWDZ128rrkz 0U, // VPMOVZXWDZ256rm 0U, // VPMOVZXWDZ256rmk 0U, // VPMOVZXWDZ256rmkz 0U, // VPMOVZXWDZ256rr 0U, // VPMOVZXWDZ256rrk 0U, // VPMOVZXWDZ256rrkz 0U, // VPMOVZXWDZrm 0U, // VPMOVZXWDZrmk 0U, // VPMOVZXWDZrmkz 0U, // VPMOVZXWDZrr 0U, // VPMOVZXWDZrrk 0U, // VPMOVZXWDZrrkz 0U, // VPMOVZXWDrm 0U, // VPMOVZXWDrr 0U, // VPMOVZXWQYrm 0U, // VPMOVZXWQYrr 0U, // VPMOVZXWQZ128rm 0U, // VPMOVZXWQZ128rmk 0U, // VPMOVZXWQZ128rmkz 0U, // VPMOVZXWQZ128rr 0U, // VPMOVZXWQZ128rrk 0U, // VPMOVZXWQZ128rrkz 0U, // VPMOVZXWQZ256rm 0U, // VPMOVZXWQZ256rmk 0U, // VPMOVZXWQZ256rmkz 0U, // VPMOVZXWQZ256rr 0U, // VPMOVZXWQZ256rrk 0U, // VPMOVZXWQZ256rrkz 0U, // VPMOVZXWQZrm 0U, // VPMOVZXWQZrmk 0U, // VPMOVZXWQZrmkz 0U, // VPMOVZXWQZrr 0U, // VPMOVZXWQZrrk 0U, // VPMOVZXWQZrrkz 0U, // VPMOVZXWQrm 0U, // VPMOVZXWQrr 0U, // VPMULDQYrm 0U, // VPMULDQYrr 0U, // VPMULDQZ128rm 0U, // VPMULDQZ128rmb 0U, // VPMULDQZ128rmbk 0U, // VPMULDQZ128rmbkz 0U, // VPMULDQZ128rmk 0U, // VPMULDQZ128rmkz 0U, // VPMULDQZ128rr 0U, // VPMULDQZ128rrk 0U, // VPMULDQZ128rrkz 0U, // VPMULDQZ256rm 0U, // VPMULDQZ256rmb 0U, // VPMULDQZ256rmbk 0U, // VPMULDQZ256rmbkz 0U, // VPMULDQZ256rmk 0U, // VPMULDQZ256rmkz 0U, // VPMULDQZ256rr 0U, // VPMULDQZ256rrk 0U, // VPMULDQZ256rrkz 0U, // VPMULDQZrm 0U, // VPMULDQZrmb 0U, // VPMULDQZrmbk 0U, // VPMULDQZrmbkz 0U, // VPMULDQZrmk 0U, // VPMULDQZrmkz 0U, // VPMULDQZrr 0U, // VPMULDQZrrk 0U, // VPMULDQZrrkz 0U, // VPMULDQrm 0U, // VPMULDQrr 0U, // VPMULHRSWYrm 0U, // VPMULHRSWYrr 0U, // VPMULHRSWZ128rm 0U, // VPMULHRSWZ128rmk 0U, // VPMULHRSWZ128rmkz 0U, // VPMULHRSWZ128rr 0U, // VPMULHRSWZ128rrk 0U, // VPMULHRSWZ128rrkz 0U, // VPMULHRSWZ256rm 0U, // VPMULHRSWZ256rmk 0U, // VPMULHRSWZ256rmkz 0U, // VPMULHRSWZ256rr 0U, // VPMULHRSWZ256rrk 0U, // VPMULHRSWZ256rrkz 0U, // VPMULHRSWZrm 0U, // VPMULHRSWZrmk 0U, // VPMULHRSWZrmkz 0U, // VPMULHRSWZrr 0U, // VPMULHRSWZrrk 0U, // VPMULHRSWZrrkz 0U, // VPMULHRSWrm 0U, // VPMULHRSWrr 0U, // VPMULHUWYrm 0U, // VPMULHUWYrr 0U, // VPMULHUWZ128rm 0U, // VPMULHUWZ128rmk 0U, // VPMULHUWZ128rmkz 0U, // VPMULHUWZ128rr 0U, // VPMULHUWZ128rrk 0U, // VPMULHUWZ128rrkz 0U, // VPMULHUWZ256rm 0U, // VPMULHUWZ256rmk 0U, // VPMULHUWZ256rmkz 0U, // VPMULHUWZ256rr 0U, // VPMULHUWZ256rrk 0U, // VPMULHUWZ256rrkz 0U, // VPMULHUWZrm 0U, // VPMULHUWZrmk 0U, // VPMULHUWZrmkz 0U, // VPMULHUWZrr 0U, // VPMULHUWZrrk 0U, // VPMULHUWZrrkz 0U, // VPMULHUWrm 0U, // VPMULHUWrr 0U, // VPMULHWYrm 0U, // VPMULHWYrr 0U, // VPMULHWZ128rm 0U, // VPMULHWZ128rmk 0U, // VPMULHWZ128rmkz 0U, // VPMULHWZ128rr 0U, // VPMULHWZ128rrk 0U, // VPMULHWZ128rrkz 0U, // VPMULHWZ256rm 0U, // VPMULHWZ256rmk 0U, // VPMULHWZ256rmkz 0U, // VPMULHWZ256rr 0U, // VPMULHWZ256rrk 0U, // VPMULHWZ256rrkz 0U, // VPMULHWZrm 0U, // VPMULHWZrmk 0U, // VPMULHWZrmkz 0U, // VPMULHWZrr 0U, // VPMULHWZrrk 0U, // VPMULHWZrrkz 0U, // VPMULHWrm 0U, // VPMULHWrr 0U, // VPMULLDYrm 0U, // VPMULLDYrr 0U, // VPMULLDZ128rm 0U, // VPMULLDZ128rmb 0U, // VPMULLDZ128rmbk 0U, // VPMULLDZ128rmbkz 0U, // VPMULLDZ128rmk 0U, // VPMULLDZ128rmkz 0U, // VPMULLDZ128rr 0U, // VPMULLDZ128rrk 0U, // VPMULLDZ128rrkz 0U, // VPMULLDZ256rm 0U, // VPMULLDZ256rmb 0U, // VPMULLDZ256rmbk 0U, // VPMULLDZ256rmbkz 0U, // VPMULLDZ256rmk 0U, // VPMULLDZ256rmkz 0U, // VPMULLDZ256rr 0U, // VPMULLDZ256rrk 0U, // VPMULLDZ256rrkz 0U, // VPMULLDZrm 0U, // VPMULLDZrmb 0U, // VPMULLDZrmbk 0U, // VPMULLDZrmbkz 0U, // VPMULLDZrmk 0U, // VPMULLDZrmkz 0U, // VPMULLDZrr 0U, // VPMULLDZrrk 0U, // VPMULLDZrrkz 0U, // VPMULLDrm 0U, // VPMULLDrr 0U, // VPMULLQZ128rm 0U, // VPMULLQZ128rmb 0U, // VPMULLQZ128rmbk 0U, // VPMULLQZ128rmbkz 0U, // VPMULLQZ128rmk 0U, // VPMULLQZ128rmkz 0U, // VPMULLQZ128rr 0U, // VPMULLQZ128rrk 0U, // VPMULLQZ128rrkz 0U, // VPMULLQZ256rm 0U, // VPMULLQZ256rmb 0U, // VPMULLQZ256rmbk 0U, // VPMULLQZ256rmbkz 0U, // VPMULLQZ256rmk 0U, // VPMULLQZ256rmkz 0U, // VPMULLQZ256rr 0U, // VPMULLQZ256rrk 0U, // VPMULLQZ256rrkz 0U, // VPMULLQZrm 0U, // VPMULLQZrmb 0U, // VPMULLQZrmbk 0U, // VPMULLQZrmbkz 0U, // VPMULLQZrmk 0U, // VPMULLQZrmkz 0U, // VPMULLQZrr 0U, // VPMULLQZrrk 0U, // VPMULLQZrrkz 0U, // VPMULLWYrm 0U, // VPMULLWYrr 0U, // VPMULLWZ128rm 0U, // VPMULLWZ128rmk 0U, // VPMULLWZ128rmkz 0U, // VPMULLWZ128rr 0U, // VPMULLWZ128rrk 0U, // VPMULLWZ128rrkz 0U, // VPMULLWZ256rm 0U, // VPMULLWZ256rmk 0U, // VPMULLWZ256rmkz 0U, // VPMULLWZ256rr 0U, // VPMULLWZ256rrk 0U, // VPMULLWZ256rrkz 0U, // VPMULLWZrm 0U, // VPMULLWZrmk 0U, // VPMULLWZrmkz 0U, // VPMULLWZrr 0U, // VPMULLWZrrk 0U, // VPMULLWZrrkz 0U, // VPMULLWrm 0U, // VPMULLWrr 0U, // VPMULTISHIFTQBZ128rm 0U, // VPMULTISHIFTQBZ128rmb 0U, // VPMULTISHIFTQBZ128rmbk 0U, // VPMULTISHIFTQBZ128rmbkz 0U, // VPMULTISHIFTQBZ128rmk 0U, // VPMULTISHIFTQBZ128rmkz 0U, // VPMULTISHIFTQBZ128rr 0U, // VPMULTISHIFTQBZ128rrk 0U, // VPMULTISHIFTQBZ128rrkz 0U, // VPMULTISHIFTQBZ256rm 0U, // VPMULTISHIFTQBZ256rmb 0U, // VPMULTISHIFTQBZ256rmbk 0U, // VPMULTISHIFTQBZ256rmbkz 0U, // VPMULTISHIFTQBZ256rmk 0U, // VPMULTISHIFTQBZ256rmkz 0U, // VPMULTISHIFTQBZ256rr 0U, // VPMULTISHIFTQBZ256rrk 0U, // VPMULTISHIFTQBZ256rrkz 0U, // VPMULTISHIFTQBZrm 0U, // VPMULTISHIFTQBZrmb 0U, // VPMULTISHIFTQBZrmbk 0U, // VPMULTISHIFTQBZrmbkz 0U, // VPMULTISHIFTQBZrmk 0U, // VPMULTISHIFTQBZrmkz 0U, // VPMULTISHIFTQBZrr 0U, // VPMULTISHIFTQBZrrk 0U, // VPMULTISHIFTQBZrrkz 0U, // VPMULUDQYrm 0U, // VPMULUDQYrr 0U, // VPMULUDQZ128rm 0U, // VPMULUDQZ128rmb 0U, // VPMULUDQZ128rmbk 0U, // VPMULUDQZ128rmbkz 0U, // VPMULUDQZ128rmk 0U, // VPMULUDQZ128rmkz 0U, // VPMULUDQZ128rr 0U, // VPMULUDQZ128rrk 0U, // VPMULUDQZ128rrkz 0U, // VPMULUDQZ256rm 0U, // VPMULUDQZ256rmb 0U, // VPMULUDQZ256rmbk 0U, // VPMULUDQZ256rmbkz 0U, // VPMULUDQZ256rmk 0U, // VPMULUDQZ256rmkz 0U, // VPMULUDQZ256rr 0U, // VPMULUDQZ256rrk 0U, // VPMULUDQZ256rrkz 0U, // VPMULUDQZrm 0U, // VPMULUDQZrmb 0U, // VPMULUDQZrmbk 0U, // VPMULUDQZrmbkz 0U, // VPMULUDQZrmk 0U, // VPMULUDQZrmkz 0U, // VPMULUDQZrr 0U, // VPMULUDQZrrk 0U, // VPMULUDQZrrkz 0U, // VPMULUDQrm 0U, // VPMULUDQrr 0U, // VPOPCNTBZ128rm 0U, // VPOPCNTBZ128rmk 0U, // VPOPCNTBZ128rmkz 0U, // VPOPCNTBZ128rr 0U, // VPOPCNTBZ128rrk 0U, // VPOPCNTBZ128rrkz 0U, // VPOPCNTBZ256rm 0U, // VPOPCNTBZ256rmk 0U, // VPOPCNTBZ256rmkz 0U, // VPOPCNTBZ256rr 0U, // VPOPCNTBZ256rrk 0U, // VPOPCNTBZ256rrkz 0U, // VPOPCNTBZrm 0U, // VPOPCNTBZrmk 0U, // VPOPCNTBZrmkz 0U, // VPOPCNTBZrr 0U, // VPOPCNTBZrrk 0U, // VPOPCNTBZrrkz 0U, // VPOPCNTDZ128rm 0U, // VPOPCNTDZ128rmb 0U, // VPOPCNTDZ128rmbk 0U, // VPOPCNTDZ128rmbkz 0U, // VPOPCNTDZ128rmk 0U, // VPOPCNTDZ128rmkz 0U, // VPOPCNTDZ128rr 0U, // VPOPCNTDZ128rrk 0U, // VPOPCNTDZ128rrkz 0U, // VPOPCNTDZ256rm 0U, // VPOPCNTDZ256rmb 0U, // VPOPCNTDZ256rmbk 0U, // VPOPCNTDZ256rmbkz 0U, // VPOPCNTDZ256rmk 0U, // VPOPCNTDZ256rmkz 0U, // VPOPCNTDZ256rr 0U, // VPOPCNTDZ256rrk 0U, // VPOPCNTDZ256rrkz 0U, // VPOPCNTDZrm 0U, // VPOPCNTDZrmb 0U, // VPOPCNTDZrmbk 0U, // VPOPCNTDZrmbkz 0U, // VPOPCNTDZrmk 0U, // VPOPCNTDZrmkz 0U, // VPOPCNTDZrr 0U, // VPOPCNTDZrrk 0U, // VPOPCNTDZrrkz 0U, // VPOPCNTQZ128rm 0U, // VPOPCNTQZ128rmb 0U, // VPOPCNTQZ128rmbk 0U, // VPOPCNTQZ128rmbkz 0U, // VPOPCNTQZ128rmk 0U, // VPOPCNTQZ128rmkz 0U, // VPOPCNTQZ128rr 0U, // VPOPCNTQZ128rrk 0U, // VPOPCNTQZ128rrkz 0U, // VPOPCNTQZ256rm 0U, // VPOPCNTQZ256rmb 0U, // VPOPCNTQZ256rmbk 0U, // VPOPCNTQZ256rmbkz 0U, // VPOPCNTQZ256rmk 0U, // VPOPCNTQZ256rmkz 0U, // VPOPCNTQZ256rr 0U, // VPOPCNTQZ256rrk 0U, // VPOPCNTQZ256rrkz 0U, // VPOPCNTQZrm 0U, // VPOPCNTQZrmb 0U, // VPOPCNTQZrmbk 0U, // VPOPCNTQZrmbkz 0U, // VPOPCNTQZrmk 0U, // VPOPCNTQZrmkz 0U, // VPOPCNTQZrr 0U, // VPOPCNTQZrrk 0U, // VPOPCNTQZrrkz 0U, // VPOPCNTWZ128rm 0U, // VPOPCNTWZ128rmk 0U, // VPOPCNTWZ128rmkz 0U, // VPOPCNTWZ128rr 0U, // VPOPCNTWZ128rrk 0U, // VPOPCNTWZ128rrkz 0U, // VPOPCNTWZ256rm 0U, // VPOPCNTWZ256rmk 0U, // VPOPCNTWZ256rmkz 0U, // VPOPCNTWZ256rr 0U, // VPOPCNTWZ256rrk 0U, // VPOPCNTWZ256rrkz 0U, // VPOPCNTWZrm 0U, // VPOPCNTWZrmk 0U, // VPOPCNTWZrmkz 0U, // VPOPCNTWZrr 0U, // VPOPCNTWZrrk 0U, // VPOPCNTWZrrkz 0U, // VPORDZ128rm 0U, // VPORDZ128rmb 0U, // VPORDZ128rmbk 0U, // VPORDZ128rmbkz 0U, // VPORDZ128rmk 0U, // VPORDZ128rmkz 0U, // VPORDZ128rr 0U, // VPORDZ128rrk 0U, // VPORDZ128rrkz 0U, // VPORDZ256rm 0U, // VPORDZ256rmb 0U, // VPORDZ256rmbk 0U, // VPORDZ256rmbkz 0U, // VPORDZ256rmk 0U, // VPORDZ256rmkz 0U, // VPORDZ256rr 0U, // VPORDZ256rrk 0U, // VPORDZ256rrkz 0U, // VPORDZrm 0U, // VPORDZrmb 0U, // VPORDZrmbk 0U, // VPORDZrmbkz 0U, // VPORDZrmk 0U, // VPORDZrmkz 0U, // VPORDZrr 0U, // VPORDZrrk 0U, // VPORDZrrkz 0U, // VPORQZ128rm 0U, // VPORQZ128rmb 0U, // VPORQZ128rmbk 0U, // VPORQZ128rmbkz 0U, // VPORQZ128rmk 0U, // VPORQZ128rmkz 0U, // VPORQZ128rr 0U, // VPORQZ128rrk 0U, // VPORQZ128rrkz 0U, // VPORQZ256rm 0U, // VPORQZ256rmb 0U, // VPORQZ256rmbk 0U, // VPORQZ256rmbkz 0U, // VPORQZ256rmk 0U, // VPORQZ256rmkz 0U, // VPORQZ256rr 0U, // VPORQZ256rrk 0U, // VPORQZ256rrkz 0U, // VPORQZrm 0U, // VPORQZrmb 0U, // VPORQZrmbk 0U, // VPORQZrmbkz 0U, // VPORQZrmk 0U, // VPORQZrmkz 0U, // VPORQZrr 0U, // VPORQZrrk 0U, // VPORQZrrkz 0U, // VPORYrm 0U, // VPORYrr 0U, // VPORrm 0U, // VPORrr 0U, // VPPERMrmr 0U, // VPPERMrrm 0U, // VPPERMrrr 0U, // VPPERMrrr_REV 0U, // VPROLDZ128mbi 0U, // VPROLDZ128mbik 0U, // VPROLDZ128mbikz 0U, // VPROLDZ128mi 0U, // VPROLDZ128mik 0U, // VPROLDZ128mikz 0U, // VPROLDZ128ri 0U, // VPROLDZ128rik 0U, // VPROLDZ128rikz 0U, // VPROLDZ256mbi 0U, // VPROLDZ256mbik 0U, // VPROLDZ256mbikz 0U, // VPROLDZ256mi 0U, // VPROLDZ256mik 0U, // VPROLDZ256mikz 0U, // VPROLDZ256ri 0U, // VPROLDZ256rik 0U, // VPROLDZ256rikz 0U, // VPROLDZmbi 0U, // VPROLDZmbik 0U, // VPROLDZmbikz 0U, // VPROLDZmi 0U, // VPROLDZmik 0U, // VPROLDZmikz 0U, // VPROLDZri 0U, // VPROLDZrik 0U, // VPROLDZrikz 0U, // VPROLQZ128mbi 0U, // VPROLQZ128mbik 0U, // VPROLQZ128mbikz 0U, // VPROLQZ128mi 0U, // VPROLQZ128mik 0U, // VPROLQZ128mikz 0U, // VPROLQZ128ri 0U, // VPROLQZ128rik 0U, // VPROLQZ128rikz 0U, // VPROLQZ256mbi 0U, // VPROLQZ256mbik 0U, // VPROLQZ256mbikz 0U, // VPROLQZ256mi 0U, // VPROLQZ256mik 0U, // VPROLQZ256mikz 0U, // VPROLQZ256ri 0U, // VPROLQZ256rik 0U, // VPROLQZ256rikz 0U, // VPROLQZmbi 0U, // VPROLQZmbik 0U, // VPROLQZmbikz 0U, // VPROLQZmi 0U, // VPROLQZmik 0U, // VPROLQZmikz 0U, // VPROLQZri 0U, // VPROLQZrik 0U, // VPROLQZrikz 0U, // VPROLVDZ128rm 0U, // VPROLVDZ128rmb 0U, // VPROLVDZ128rmbk 0U, // VPROLVDZ128rmbkz 0U, // VPROLVDZ128rmk 0U, // VPROLVDZ128rmkz 0U, // VPROLVDZ128rr 0U, // VPROLVDZ128rrk 0U, // VPROLVDZ128rrkz 0U, // VPROLVDZ256rm 0U, // VPROLVDZ256rmb 0U, // VPROLVDZ256rmbk 0U, // VPROLVDZ256rmbkz 0U, // VPROLVDZ256rmk 0U, // VPROLVDZ256rmkz 0U, // VPROLVDZ256rr 0U, // VPROLVDZ256rrk 0U, // VPROLVDZ256rrkz 0U, // VPROLVDZrm 0U, // VPROLVDZrmb 0U, // VPROLVDZrmbk 0U, // VPROLVDZrmbkz 0U, // VPROLVDZrmk 0U, // VPROLVDZrmkz 0U, // VPROLVDZrr 0U, // VPROLVDZrrk 0U, // VPROLVDZrrkz 0U, // VPROLVQZ128rm 0U, // VPROLVQZ128rmb 0U, // VPROLVQZ128rmbk 0U, // VPROLVQZ128rmbkz 0U, // VPROLVQZ128rmk 0U, // VPROLVQZ128rmkz 0U, // VPROLVQZ128rr 0U, // VPROLVQZ128rrk 0U, // VPROLVQZ128rrkz 0U, // VPROLVQZ256rm 0U, // VPROLVQZ256rmb 0U, // VPROLVQZ256rmbk 0U, // VPROLVQZ256rmbkz 0U, // VPROLVQZ256rmk 0U, // VPROLVQZ256rmkz 0U, // VPROLVQZ256rr 0U, // VPROLVQZ256rrk 0U, // VPROLVQZ256rrkz 0U, // VPROLVQZrm 0U, // VPROLVQZrmb 0U, // VPROLVQZrmbk 0U, // VPROLVQZrmbkz 0U, // VPROLVQZrmk 0U, // VPROLVQZrmkz 0U, // VPROLVQZrr 0U, // VPROLVQZrrk 0U, // VPROLVQZrrkz 0U, // VPRORDZ128mbi 0U, // VPRORDZ128mbik 0U, // VPRORDZ128mbikz 0U, // VPRORDZ128mi 0U, // VPRORDZ128mik 0U, // VPRORDZ128mikz 0U, // VPRORDZ128ri 0U, // VPRORDZ128rik 0U, // VPRORDZ128rikz 0U, // VPRORDZ256mbi 0U, // VPRORDZ256mbik 0U, // VPRORDZ256mbikz 0U, // VPRORDZ256mi 0U, // VPRORDZ256mik 0U, // VPRORDZ256mikz 0U, // VPRORDZ256ri 0U, // VPRORDZ256rik 0U, // VPRORDZ256rikz 0U, // VPRORDZmbi 0U, // VPRORDZmbik 0U, // VPRORDZmbikz 0U, // VPRORDZmi 0U, // VPRORDZmik 0U, // VPRORDZmikz 0U, // VPRORDZri 0U, // VPRORDZrik 0U, // VPRORDZrikz 0U, // VPRORQZ128mbi 0U, // VPRORQZ128mbik 0U, // VPRORQZ128mbikz 0U, // VPRORQZ128mi 0U, // VPRORQZ128mik 0U, // VPRORQZ128mikz 0U, // VPRORQZ128ri 0U, // VPRORQZ128rik 0U, // VPRORQZ128rikz 0U, // VPRORQZ256mbi 0U, // VPRORQZ256mbik 0U, // VPRORQZ256mbikz 0U, // VPRORQZ256mi 0U, // VPRORQZ256mik 0U, // VPRORQZ256mikz 0U, // VPRORQZ256ri 0U, // VPRORQZ256rik 0U, // VPRORQZ256rikz 0U, // VPRORQZmbi 0U, // VPRORQZmbik 0U, // VPRORQZmbikz 0U, // VPRORQZmi 0U, // VPRORQZmik 0U, // VPRORQZmikz 0U, // VPRORQZri 0U, // VPRORQZrik 0U, // VPRORQZrikz 0U, // VPRORVDZ128rm 0U, // VPRORVDZ128rmb 0U, // VPRORVDZ128rmbk 0U, // VPRORVDZ128rmbkz 0U, // VPRORVDZ128rmk 0U, // VPRORVDZ128rmkz 0U, // VPRORVDZ128rr 0U, // VPRORVDZ128rrk 0U, // VPRORVDZ128rrkz 0U, // VPRORVDZ256rm 0U, // VPRORVDZ256rmb 0U, // VPRORVDZ256rmbk 0U, // VPRORVDZ256rmbkz 0U, // VPRORVDZ256rmk 0U, // VPRORVDZ256rmkz 0U, // VPRORVDZ256rr 0U, // VPRORVDZ256rrk 0U, // VPRORVDZ256rrkz 0U, // VPRORVDZrm 0U, // VPRORVDZrmb 0U, // VPRORVDZrmbk 0U, // VPRORVDZrmbkz 0U, // VPRORVDZrmk 0U, // VPRORVDZrmkz 0U, // VPRORVDZrr 0U, // VPRORVDZrrk 0U, // VPRORVDZrrkz 0U, // VPRORVQZ128rm 0U, // VPRORVQZ128rmb 0U, // VPRORVQZ128rmbk 0U, // VPRORVQZ128rmbkz 0U, // VPRORVQZ128rmk 0U, // VPRORVQZ128rmkz 0U, // VPRORVQZ128rr 0U, // VPRORVQZ128rrk 0U, // VPRORVQZ128rrkz 0U, // VPRORVQZ256rm 0U, // VPRORVQZ256rmb 0U, // VPRORVQZ256rmbk 0U, // VPRORVQZ256rmbkz 0U, // VPRORVQZ256rmk 0U, // VPRORVQZ256rmkz 0U, // VPRORVQZ256rr 0U, // VPRORVQZ256rrk 0U, // VPRORVQZ256rrkz 0U, // VPRORVQZrm 0U, // VPRORVQZrmb 0U, // VPRORVQZrmbk 0U, // VPRORVQZrmbkz 0U, // VPRORVQZrmk 0U, // VPRORVQZrmkz 0U, // VPRORVQZrr 0U, // VPRORVQZrrk 0U, // VPRORVQZrrkz 0U, // VPROTBmi 0U, // VPROTBmr 0U, // VPROTBri 0U, // VPROTBrm 0U, // VPROTBrr 0U, // VPROTBrr_REV 0U, // VPROTDmi 0U, // VPROTDmr 0U, // VPROTDri 0U, // VPROTDrm 0U, // VPROTDrr 0U, // VPROTDrr_REV 0U, // VPROTQmi 0U, // VPROTQmr 0U, // VPROTQri 0U, // VPROTQrm 0U, // VPROTQrr 0U, // VPROTQrr_REV 0U, // VPROTWmi 0U, // VPROTWmr 0U, // VPROTWri 0U, // VPROTWrm 0U, // VPROTWrr 0U, // VPROTWrr_REV 0U, // VPSADBWYrm 0U, // VPSADBWYrr 0U, // VPSADBWZ128rm 0U, // VPSADBWZ128rr 0U, // VPSADBWZ256rm 0U, // VPSADBWZ256rr 0U, // VPSADBWZrm 0U, // VPSADBWZrr 0U, // VPSADBWrm 0U, // VPSADBWrr 0U, // VPSCATTERDDZ128mr 0U, // VPSCATTERDDZ256mr 0U, // VPSCATTERDDZmr 0U, // VPSCATTERDQZ128mr 0U, // VPSCATTERDQZ256mr 0U, // VPSCATTERDQZmr 0U, // VPSCATTERQDZ128mr 0U, // VPSCATTERQDZ256mr 0U, // VPSCATTERQDZmr 0U, // VPSCATTERQQZ128mr 0U, // VPSCATTERQQZ256mr 0U, // VPSCATTERQQZmr 0U, // VPSHABmr 0U, // VPSHABrm 0U, // VPSHABrr 0U, // VPSHABrr_REV 0U, // VPSHADmr 0U, // VPSHADrm 0U, // VPSHADrr 0U, // VPSHADrr_REV 0U, // VPSHAQmr 0U, // VPSHAQrm 0U, // VPSHAQrr 0U, // VPSHAQrr_REV 0U, // VPSHAWmr 0U, // VPSHAWrm 0U, // VPSHAWrr 0U, // VPSHAWrr_REV 0U, // VPSHLBmr 0U, // VPSHLBrm 0U, // VPSHLBrr 0U, // VPSHLBrr_REV 0U, // VPSHLDDZ128rmbi 0U, // VPSHLDDZ128rmbik 3U, // VPSHLDDZ128rmbikz 0U, // VPSHLDDZ128rmi 0U, // VPSHLDDZ128rmik 0U, // VPSHLDDZ128rmikz 0U, // VPSHLDDZ128rri 0U, // VPSHLDDZ128rrik 3U, // VPSHLDDZ128rrikz 0U, // VPSHLDDZ256rmbi 0U, // VPSHLDDZ256rmbik 3U, // VPSHLDDZ256rmbikz 0U, // VPSHLDDZ256rmi 0U, // VPSHLDDZ256rmik 0U, // VPSHLDDZ256rmikz 0U, // VPSHLDDZ256rri 0U, // VPSHLDDZ256rrik 3U, // VPSHLDDZ256rrikz 0U, // VPSHLDDZrmbi 0U, // VPSHLDDZrmbik 3U, // VPSHLDDZrmbikz 0U, // VPSHLDDZrmi 0U, // VPSHLDDZrmik 0U, // VPSHLDDZrmikz 0U, // VPSHLDDZrri 0U, // VPSHLDDZrrik 3U, // VPSHLDDZrrikz 0U, // VPSHLDQZ128rmbi 0U, // VPSHLDQZ128rmbik 3U, // VPSHLDQZ128rmbikz 0U, // VPSHLDQZ128rmi 0U, // VPSHLDQZ128rmik 0U, // VPSHLDQZ128rmikz 0U, // VPSHLDQZ128rri 0U, // VPSHLDQZ128rrik 3U, // VPSHLDQZ128rrikz 0U, // VPSHLDQZ256rmbi 0U, // VPSHLDQZ256rmbik 3U, // VPSHLDQZ256rmbikz 0U, // VPSHLDQZ256rmi 0U, // VPSHLDQZ256rmik 0U, // VPSHLDQZ256rmikz 0U, // VPSHLDQZ256rri 0U, // VPSHLDQZ256rrik 3U, // VPSHLDQZ256rrikz 0U, // VPSHLDQZrmbi 0U, // VPSHLDQZrmbik 3U, // VPSHLDQZrmbikz 0U, // VPSHLDQZrmi 0U, // VPSHLDQZrmik 0U, // VPSHLDQZrmikz 0U, // VPSHLDQZrri 0U, // VPSHLDQZrrik 3U, // VPSHLDQZrrikz 0U, // VPSHLDVDZ128m 0U, // VPSHLDVDZ128mb 0U, // VPSHLDVDZ128mbk 0U, // VPSHLDVDZ128mbkz 0U, // VPSHLDVDZ128mk 0U, // VPSHLDVDZ128mkz 0U, // VPSHLDVDZ128r 0U, // VPSHLDVDZ128rk 0U, // VPSHLDVDZ128rkz 0U, // VPSHLDVDZ256m 0U, // VPSHLDVDZ256mb 0U, // VPSHLDVDZ256mbk 0U, // VPSHLDVDZ256mbkz 0U, // VPSHLDVDZ256mk 0U, // VPSHLDVDZ256mkz 0U, // VPSHLDVDZ256r 0U, // VPSHLDVDZ256rk 0U, // VPSHLDVDZ256rkz 0U, // VPSHLDVDZm 0U, // VPSHLDVDZmb 0U, // VPSHLDVDZmbk 0U, // VPSHLDVDZmbkz 0U, // VPSHLDVDZmk 0U, // VPSHLDVDZmkz 0U, // VPSHLDVDZr 0U, // VPSHLDVDZrk 0U, // VPSHLDVDZrkz 0U, // VPSHLDVQZ128m 0U, // VPSHLDVQZ128mb 0U, // VPSHLDVQZ128mbk 0U, // VPSHLDVQZ128mbkz 0U, // VPSHLDVQZ128mk 0U, // VPSHLDVQZ128mkz 0U, // VPSHLDVQZ128r 0U, // VPSHLDVQZ128rk 0U, // VPSHLDVQZ128rkz 0U, // VPSHLDVQZ256m 0U, // VPSHLDVQZ256mb 0U, // VPSHLDVQZ256mbk 0U, // VPSHLDVQZ256mbkz 0U, // VPSHLDVQZ256mk 0U, // VPSHLDVQZ256mkz 0U, // VPSHLDVQZ256r 0U, // VPSHLDVQZ256rk 0U, // VPSHLDVQZ256rkz 0U, // VPSHLDVQZm 0U, // VPSHLDVQZmb 0U, // VPSHLDVQZmbk 0U, // VPSHLDVQZmbkz 0U, // VPSHLDVQZmk 0U, // VPSHLDVQZmkz 0U, // VPSHLDVQZr 0U, // VPSHLDVQZrk 0U, // VPSHLDVQZrkz 0U, // VPSHLDVWZ128m 0U, // VPSHLDVWZ128mk 0U, // VPSHLDVWZ128mkz 0U, // VPSHLDVWZ128r 0U, // VPSHLDVWZ128rk 0U, // VPSHLDVWZ128rkz 0U, // VPSHLDVWZ256m 0U, // VPSHLDVWZ256mk 0U, // VPSHLDVWZ256mkz 0U, // VPSHLDVWZ256r 0U, // VPSHLDVWZ256rk 0U, // VPSHLDVWZ256rkz 0U, // VPSHLDVWZm 0U, // VPSHLDVWZmk 0U, // VPSHLDVWZmkz 0U, // VPSHLDVWZr 0U, // VPSHLDVWZrk 0U, // VPSHLDVWZrkz 0U, // VPSHLDWZ128rmi 0U, // VPSHLDWZ128rmik 0U, // VPSHLDWZ128rmikz 0U, // VPSHLDWZ128rri 0U, // VPSHLDWZ128rrik 3U, // VPSHLDWZ128rrikz 0U, // VPSHLDWZ256rmi 0U, // VPSHLDWZ256rmik 0U, // VPSHLDWZ256rmikz 0U, // VPSHLDWZ256rri 0U, // VPSHLDWZ256rrik 3U, // VPSHLDWZ256rrikz 0U, // VPSHLDWZrmi 0U, // VPSHLDWZrmik 0U, // VPSHLDWZrmikz 0U, // VPSHLDWZrri 0U, // VPSHLDWZrrik 3U, // VPSHLDWZrrikz 0U, // VPSHLDmr 0U, // VPSHLDrm 0U, // VPSHLDrr 0U, // VPSHLDrr_REV 0U, // VPSHLQmr 0U, // VPSHLQrm 0U, // VPSHLQrr 0U, // VPSHLQrr_REV 0U, // VPSHLWmr 0U, // VPSHLWrm 0U, // VPSHLWrr 0U, // VPSHLWrr_REV 0U, // VPSHRDDZ128rmbi 0U, // VPSHRDDZ128rmbik 3U, // VPSHRDDZ128rmbikz 0U, // VPSHRDDZ128rmi 0U, // VPSHRDDZ128rmik 0U, // VPSHRDDZ128rmikz 0U, // VPSHRDDZ128rri 0U, // VPSHRDDZ128rrik 3U, // VPSHRDDZ128rrikz 0U, // VPSHRDDZ256rmbi 0U, // VPSHRDDZ256rmbik 3U, // VPSHRDDZ256rmbikz 0U, // VPSHRDDZ256rmi 0U, // VPSHRDDZ256rmik 0U, // VPSHRDDZ256rmikz 0U, // VPSHRDDZ256rri 0U, // VPSHRDDZ256rrik 3U, // VPSHRDDZ256rrikz 0U, // VPSHRDDZrmbi 0U, // VPSHRDDZrmbik 3U, // VPSHRDDZrmbikz 0U, // VPSHRDDZrmi 0U, // VPSHRDDZrmik 0U, // VPSHRDDZrmikz 0U, // VPSHRDDZrri 0U, // VPSHRDDZrrik 3U, // VPSHRDDZrrikz 0U, // VPSHRDQZ128rmbi 0U, // VPSHRDQZ128rmbik 3U, // VPSHRDQZ128rmbikz 0U, // VPSHRDQZ128rmi 0U, // VPSHRDQZ128rmik 0U, // VPSHRDQZ128rmikz 0U, // VPSHRDQZ128rri 0U, // VPSHRDQZ128rrik 3U, // VPSHRDQZ128rrikz 0U, // VPSHRDQZ256rmbi 0U, // VPSHRDQZ256rmbik 3U, // VPSHRDQZ256rmbikz 0U, // VPSHRDQZ256rmi 0U, // VPSHRDQZ256rmik 0U, // VPSHRDQZ256rmikz 0U, // VPSHRDQZ256rri 0U, // VPSHRDQZ256rrik 3U, // VPSHRDQZ256rrikz 0U, // VPSHRDQZrmbi 0U, // VPSHRDQZrmbik 3U, // VPSHRDQZrmbikz 0U, // VPSHRDQZrmi 0U, // VPSHRDQZrmik 0U, // VPSHRDQZrmikz 0U, // VPSHRDQZrri 0U, // VPSHRDQZrrik 3U, // VPSHRDQZrrikz 0U, // VPSHRDVDZ128m 0U, // VPSHRDVDZ128mb 0U, // VPSHRDVDZ128mbk 0U, // VPSHRDVDZ128mbkz 0U, // VPSHRDVDZ128mk 0U, // VPSHRDVDZ128mkz 0U, // VPSHRDVDZ128r 0U, // VPSHRDVDZ128rk 0U, // VPSHRDVDZ128rkz 0U, // VPSHRDVDZ256m 0U, // VPSHRDVDZ256mb 0U, // VPSHRDVDZ256mbk 0U, // VPSHRDVDZ256mbkz 0U, // VPSHRDVDZ256mk 0U, // VPSHRDVDZ256mkz 0U, // VPSHRDVDZ256r 0U, // VPSHRDVDZ256rk 0U, // VPSHRDVDZ256rkz 0U, // VPSHRDVDZm 0U, // VPSHRDVDZmb 0U, // VPSHRDVDZmbk 0U, // VPSHRDVDZmbkz 0U, // VPSHRDVDZmk 0U, // VPSHRDVDZmkz 0U, // VPSHRDVDZr 0U, // VPSHRDVDZrk 0U, // VPSHRDVDZrkz 0U, // VPSHRDVQZ128m 0U, // VPSHRDVQZ128mb 0U, // VPSHRDVQZ128mbk 0U, // VPSHRDVQZ128mbkz 0U, // VPSHRDVQZ128mk 0U, // VPSHRDVQZ128mkz 0U, // VPSHRDVQZ128r 0U, // VPSHRDVQZ128rk 0U, // VPSHRDVQZ128rkz 0U, // VPSHRDVQZ256m 0U, // VPSHRDVQZ256mb 0U, // VPSHRDVQZ256mbk 0U, // VPSHRDVQZ256mbkz 0U, // VPSHRDVQZ256mk 0U, // VPSHRDVQZ256mkz 0U, // VPSHRDVQZ256r 0U, // VPSHRDVQZ256rk 0U, // VPSHRDVQZ256rkz 0U, // VPSHRDVQZm 0U, // VPSHRDVQZmb 0U, // VPSHRDVQZmbk 0U, // VPSHRDVQZmbkz 0U, // VPSHRDVQZmk 0U, // VPSHRDVQZmkz 0U, // VPSHRDVQZr 0U, // VPSHRDVQZrk 0U, // VPSHRDVQZrkz 0U, // VPSHRDVWZ128m 0U, // VPSHRDVWZ128mk 0U, // VPSHRDVWZ128mkz 0U, // VPSHRDVWZ128r 0U, // VPSHRDVWZ128rk 0U, // VPSHRDVWZ128rkz 0U, // VPSHRDVWZ256m 0U, // VPSHRDVWZ256mk 0U, // VPSHRDVWZ256mkz 0U, // VPSHRDVWZ256r 0U, // VPSHRDVWZ256rk 0U, // VPSHRDVWZ256rkz 0U, // VPSHRDVWZm 0U, // VPSHRDVWZmk 0U, // VPSHRDVWZmkz 0U, // VPSHRDVWZr 0U, // VPSHRDVWZrk 0U, // VPSHRDVWZrkz 0U, // VPSHRDWZ128rmi 0U, // VPSHRDWZ128rmik 0U, // VPSHRDWZ128rmikz 0U, // VPSHRDWZ128rri 0U, // VPSHRDWZ128rrik 3U, // VPSHRDWZ128rrikz 0U, // VPSHRDWZ256rmi 0U, // VPSHRDWZ256rmik 0U, // VPSHRDWZ256rmikz 0U, // VPSHRDWZ256rri 0U, // VPSHRDWZ256rrik 3U, // VPSHRDWZ256rrikz 0U, // VPSHRDWZrmi 0U, // VPSHRDWZrmik 0U, // VPSHRDWZrmikz 0U, // VPSHRDWZrri 0U, // VPSHRDWZrrik 3U, // VPSHRDWZrrikz 0U, // VPSHUFBITQMBZ128rm 0U, // VPSHUFBITQMBZ128rmk 0U, // VPSHUFBITQMBZ128rr 0U, // VPSHUFBITQMBZ128rrk 0U, // VPSHUFBITQMBZ256rm 0U, // VPSHUFBITQMBZ256rmk 0U, // VPSHUFBITQMBZ256rr 0U, // VPSHUFBITQMBZ256rrk 0U, // VPSHUFBITQMBZrm 0U, // VPSHUFBITQMBZrmk 0U, // VPSHUFBITQMBZrr 0U, // VPSHUFBITQMBZrrk 0U, // VPSHUFBYrm 0U, // VPSHUFBYrr 0U, // VPSHUFBZ128rm 0U, // VPSHUFBZ128rmk 0U, // VPSHUFBZ128rmkz 0U, // VPSHUFBZ128rr 0U, // VPSHUFBZ128rrk 0U, // VPSHUFBZ128rrkz 0U, // VPSHUFBZ256rm 0U, // VPSHUFBZ256rmk 0U, // VPSHUFBZ256rmkz 0U, // VPSHUFBZ256rr 0U, // VPSHUFBZ256rrk 0U, // VPSHUFBZ256rrkz 0U, // VPSHUFBZrm 0U, // VPSHUFBZrmk 0U, // VPSHUFBZrmkz 0U, // VPSHUFBZrr 0U, // VPSHUFBZrrk 0U, // VPSHUFBZrrkz 0U, // VPSHUFBrm 0U, // VPSHUFBrr 0U, // VPSHUFDYmi 0U, // VPSHUFDYri 0U, // VPSHUFDZ128mbi 0U, // VPSHUFDZ128mbik 0U, // VPSHUFDZ128mbikz 0U, // VPSHUFDZ128mi 0U, // VPSHUFDZ128mik 0U, // VPSHUFDZ128mikz 0U, // VPSHUFDZ128ri 0U, // VPSHUFDZ128rik 0U, // VPSHUFDZ128rikz 0U, // VPSHUFDZ256mbi 0U, // VPSHUFDZ256mbik 0U, // VPSHUFDZ256mbikz 0U, // VPSHUFDZ256mi 0U, // VPSHUFDZ256mik 0U, // VPSHUFDZ256mikz 0U, // VPSHUFDZ256ri 0U, // VPSHUFDZ256rik 0U, // VPSHUFDZ256rikz 0U, // VPSHUFDZmbi 0U, // VPSHUFDZmbik 0U, // VPSHUFDZmbikz 0U, // VPSHUFDZmi 0U, // VPSHUFDZmik 0U, // VPSHUFDZmikz 0U, // VPSHUFDZri 0U, // VPSHUFDZrik 0U, // VPSHUFDZrikz 0U, // VPSHUFDmi 0U, // VPSHUFDri 0U, // VPSHUFHWYmi 0U, // VPSHUFHWYri 0U, // VPSHUFHWZ128mi 0U, // VPSHUFHWZ128mik 0U, // VPSHUFHWZ128mikz 0U, // VPSHUFHWZ128ri 0U, // VPSHUFHWZ128rik 0U, // VPSHUFHWZ128rikz 0U, // VPSHUFHWZ256mi 0U, // VPSHUFHWZ256mik 0U, // VPSHUFHWZ256mikz 0U, // VPSHUFHWZ256ri 0U, // VPSHUFHWZ256rik 0U, // VPSHUFHWZ256rikz 0U, // VPSHUFHWZmi 0U, // VPSHUFHWZmik 0U, // VPSHUFHWZmikz 0U, // VPSHUFHWZri 0U, // VPSHUFHWZrik 0U, // VPSHUFHWZrikz 0U, // VPSHUFHWmi 0U, // VPSHUFHWri 0U, // VPSHUFLWYmi 0U, // VPSHUFLWYri 0U, // VPSHUFLWZ128mi 0U, // VPSHUFLWZ128mik 0U, // VPSHUFLWZ128mikz 0U, // VPSHUFLWZ128ri 0U, // VPSHUFLWZ128rik 0U, // VPSHUFLWZ128rikz 0U, // VPSHUFLWZ256mi 0U, // VPSHUFLWZ256mik 0U, // VPSHUFLWZ256mikz 0U, // VPSHUFLWZ256ri 0U, // VPSHUFLWZ256rik 0U, // VPSHUFLWZ256rikz 0U, // VPSHUFLWZmi 0U, // VPSHUFLWZmik 0U, // VPSHUFLWZmikz 0U, // VPSHUFLWZri 0U, // VPSHUFLWZrik 0U, // VPSHUFLWZrikz 0U, // VPSHUFLWmi 0U, // VPSHUFLWri 0U, // VPSIGNBYrm 0U, // VPSIGNBYrr 0U, // VPSIGNBrm 0U, // VPSIGNBrr 0U, // VPSIGNDYrm 0U, // VPSIGNDYrr 0U, // VPSIGNDrm 0U, // VPSIGNDrr 0U, // VPSIGNWYrm 0U, // VPSIGNWYrr 0U, // VPSIGNWrm 0U, // VPSIGNWrr 0U, // VPSLLDQYri 0U, // VPSLLDQZ128rm 0U, // VPSLLDQZ128rr 0U, // VPSLLDQZ256rm 0U, // VPSLLDQZ256rr 0U, // VPSLLDQZrm 0U, // VPSLLDQZrr 0U, // VPSLLDQri 0U, // VPSLLDYri 0U, // VPSLLDYrm 0U, // VPSLLDYrr 0U, // VPSLLDZ128mbi 0U, // VPSLLDZ128mbik 0U, // VPSLLDZ128mbikz 0U, // VPSLLDZ128mi 0U, // VPSLLDZ128mik 0U, // VPSLLDZ128mikz 0U, // VPSLLDZ128ri 0U, // VPSLLDZ128rik 0U, // VPSLLDZ128rikz 0U, // VPSLLDZ128rm 0U, // VPSLLDZ128rmk 0U, // VPSLLDZ128rmkz 0U, // VPSLLDZ128rr 0U, // VPSLLDZ128rrk 0U, // VPSLLDZ128rrkz 0U, // VPSLLDZ256mbi 0U, // VPSLLDZ256mbik 0U, // VPSLLDZ256mbikz 0U, // VPSLLDZ256mi 0U, // VPSLLDZ256mik 0U, // VPSLLDZ256mikz 0U, // VPSLLDZ256ri 0U, // VPSLLDZ256rik 0U, // VPSLLDZ256rikz 0U, // VPSLLDZ256rm 0U, // VPSLLDZ256rmk 0U, // VPSLLDZ256rmkz 0U, // VPSLLDZ256rr 0U, // VPSLLDZ256rrk 0U, // VPSLLDZ256rrkz 0U, // VPSLLDZmbi 0U, // VPSLLDZmbik 0U, // VPSLLDZmbikz 0U, // VPSLLDZmi 0U, // VPSLLDZmik 0U, // VPSLLDZmikz 0U, // VPSLLDZri 0U, // VPSLLDZrik 0U, // VPSLLDZrikz 0U, // VPSLLDZrm 0U, // VPSLLDZrmk 0U, // VPSLLDZrmkz 0U, // VPSLLDZrr 0U, // VPSLLDZrrk 0U, // VPSLLDZrrkz 0U, // VPSLLDri 0U, // VPSLLDrm 0U, // VPSLLDrr 0U, // VPSLLQYri 0U, // VPSLLQYrm 0U, // VPSLLQYrr 0U, // VPSLLQZ128mbi 0U, // VPSLLQZ128mbik 0U, // VPSLLQZ128mbikz 0U, // VPSLLQZ128mi 0U, // VPSLLQZ128mik 0U, // VPSLLQZ128mikz 0U, // VPSLLQZ128ri 0U, // VPSLLQZ128rik 0U, // VPSLLQZ128rikz 0U, // VPSLLQZ128rm 0U, // VPSLLQZ128rmk 0U, // VPSLLQZ128rmkz 0U, // VPSLLQZ128rr 0U, // VPSLLQZ128rrk 0U, // VPSLLQZ128rrkz 0U, // VPSLLQZ256mbi 0U, // VPSLLQZ256mbik 0U, // VPSLLQZ256mbikz 0U, // VPSLLQZ256mi 0U, // VPSLLQZ256mik 0U, // VPSLLQZ256mikz 0U, // VPSLLQZ256ri 0U, // VPSLLQZ256rik 0U, // VPSLLQZ256rikz 0U, // VPSLLQZ256rm 0U, // VPSLLQZ256rmk 0U, // VPSLLQZ256rmkz 0U, // VPSLLQZ256rr 0U, // VPSLLQZ256rrk 0U, // VPSLLQZ256rrkz 0U, // VPSLLQZmbi 0U, // VPSLLQZmbik 0U, // VPSLLQZmbikz 0U, // VPSLLQZmi 0U, // VPSLLQZmik 0U, // VPSLLQZmikz 0U, // VPSLLQZri 0U, // VPSLLQZrik 0U, // VPSLLQZrikz 0U, // VPSLLQZrm 0U, // VPSLLQZrmk 0U, // VPSLLQZrmkz 0U, // VPSLLQZrr 0U, // VPSLLQZrrk 0U, // VPSLLQZrrkz 0U, // VPSLLQri 0U, // VPSLLQrm 0U, // VPSLLQrr 0U, // VPSLLVDYrm 0U, // VPSLLVDYrr 0U, // VPSLLVDZ128rm 0U, // VPSLLVDZ128rmb 0U, // VPSLLVDZ128rmbk 0U, // VPSLLVDZ128rmbkz 0U, // VPSLLVDZ128rmk 0U, // VPSLLVDZ128rmkz 0U, // VPSLLVDZ128rr 0U, // VPSLLVDZ128rrk 0U, // VPSLLVDZ128rrkz 0U, // VPSLLVDZ256rm 0U, // VPSLLVDZ256rmb 0U, // VPSLLVDZ256rmbk 0U, // VPSLLVDZ256rmbkz 0U, // VPSLLVDZ256rmk 0U, // VPSLLVDZ256rmkz 0U, // VPSLLVDZ256rr 0U, // VPSLLVDZ256rrk 0U, // VPSLLVDZ256rrkz 0U, // VPSLLVDZrm 0U, // VPSLLVDZrmb 0U, // VPSLLVDZrmbk 0U, // VPSLLVDZrmbkz 0U, // VPSLLVDZrmk 0U, // VPSLLVDZrmkz 0U, // VPSLLVDZrr 0U, // VPSLLVDZrrk 0U, // VPSLLVDZrrkz 0U, // VPSLLVDrm 0U, // VPSLLVDrr 0U, // VPSLLVQYrm 0U, // VPSLLVQYrr 0U, // VPSLLVQZ128rm 0U, // VPSLLVQZ128rmb 0U, // VPSLLVQZ128rmbk 0U, // VPSLLVQZ128rmbkz 0U, // VPSLLVQZ128rmk 0U, // VPSLLVQZ128rmkz 0U, // VPSLLVQZ128rr 0U, // VPSLLVQZ128rrk 0U, // VPSLLVQZ128rrkz 0U, // VPSLLVQZ256rm 0U, // VPSLLVQZ256rmb 0U, // VPSLLVQZ256rmbk 0U, // VPSLLVQZ256rmbkz 0U, // VPSLLVQZ256rmk 0U, // VPSLLVQZ256rmkz 0U, // VPSLLVQZ256rr 0U, // VPSLLVQZ256rrk 0U, // VPSLLVQZ256rrkz 0U, // VPSLLVQZrm 0U, // VPSLLVQZrmb 0U, // VPSLLVQZrmbk 0U, // VPSLLVQZrmbkz 0U, // VPSLLVQZrmk 0U, // VPSLLVQZrmkz 0U, // VPSLLVQZrr 0U, // VPSLLVQZrrk 0U, // VPSLLVQZrrkz 0U, // VPSLLVQrm 0U, // VPSLLVQrr 0U, // VPSLLVWZ128rm 0U, // VPSLLVWZ128rmk 0U, // VPSLLVWZ128rmkz 0U, // VPSLLVWZ128rr 0U, // VPSLLVWZ128rrk 0U, // VPSLLVWZ128rrkz 0U, // VPSLLVWZ256rm 0U, // VPSLLVWZ256rmk 0U, // VPSLLVWZ256rmkz 0U, // VPSLLVWZ256rr 0U, // VPSLLVWZ256rrk 0U, // VPSLLVWZ256rrkz 0U, // VPSLLVWZrm 0U, // VPSLLVWZrmk 0U, // VPSLLVWZrmkz 0U, // VPSLLVWZrr 0U, // VPSLLVWZrrk 0U, // VPSLLVWZrrkz 0U, // VPSLLWYri 0U, // VPSLLWYrm 0U, // VPSLLWYrr 0U, // VPSLLWZ128mi 0U, // VPSLLWZ128mik 0U, // VPSLLWZ128mikz 0U, // VPSLLWZ128ri 0U, // VPSLLWZ128rik 0U, // VPSLLWZ128rikz 0U, // VPSLLWZ128rm 0U, // VPSLLWZ128rmk 0U, // VPSLLWZ128rmkz 0U, // VPSLLWZ128rr 0U, // VPSLLWZ128rrk 0U, // VPSLLWZ128rrkz 0U, // VPSLLWZ256mi 0U, // VPSLLWZ256mik 0U, // VPSLLWZ256mikz 0U, // VPSLLWZ256ri 0U, // VPSLLWZ256rik 0U, // VPSLLWZ256rikz 0U, // VPSLLWZ256rm 0U, // VPSLLWZ256rmk 0U, // VPSLLWZ256rmkz 0U, // VPSLLWZ256rr 0U, // VPSLLWZ256rrk 0U, // VPSLLWZ256rrkz 0U, // VPSLLWZmi 0U, // VPSLLWZmik 0U, // VPSLLWZmikz 0U, // VPSLLWZri 0U, // VPSLLWZrik 0U, // VPSLLWZrikz 0U, // VPSLLWZrm 0U, // VPSLLWZrmk 0U, // VPSLLWZrmkz 0U, // VPSLLWZrr 0U, // VPSLLWZrrk 0U, // VPSLLWZrrkz 0U, // VPSLLWri 0U, // VPSLLWrm 0U, // VPSLLWrr 0U, // VPSRADYri 0U, // VPSRADYrm 0U, // VPSRADYrr 0U, // VPSRADZ128mbi 0U, // VPSRADZ128mbik 0U, // VPSRADZ128mbikz 0U, // VPSRADZ128mi 0U, // VPSRADZ128mik 0U, // VPSRADZ128mikz 0U, // VPSRADZ128ri 0U, // VPSRADZ128rik 0U, // VPSRADZ128rikz 0U, // VPSRADZ128rm 0U, // VPSRADZ128rmk 0U, // VPSRADZ128rmkz 0U, // VPSRADZ128rr 0U, // VPSRADZ128rrk 0U, // VPSRADZ128rrkz 0U, // VPSRADZ256mbi 0U, // VPSRADZ256mbik 0U, // VPSRADZ256mbikz 0U, // VPSRADZ256mi 0U, // VPSRADZ256mik 0U, // VPSRADZ256mikz 0U, // VPSRADZ256ri 0U, // VPSRADZ256rik 0U, // VPSRADZ256rikz 0U, // VPSRADZ256rm 0U, // VPSRADZ256rmk 0U, // VPSRADZ256rmkz 0U, // VPSRADZ256rr 0U, // VPSRADZ256rrk 0U, // VPSRADZ256rrkz 0U, // VPSRADZmbi 0U, // VPSRADZmbik 0U, // VPSRADZmbikz 0U, // VPSRADZmi 0U, // VPSRADZmik 0U, // VPSRADZmikz 0U, // VPSRADZri 0U, // VPSRADZrik 0U, // VPSRADZrikz 0U, // VPSRADZrm 0U, // VPSRADZrmk 0U, // VPSRADZrmkz 0U, // VPSRADZrr 0U, // VPSRADZrrk 0U, // VPSRADZrrkz 0U, // VPSRADri 0U, // VPSRADrm 0U, // VPSRADrr 0U, // VPSRAQZ128mbi 0U, // VPSRAQZ128mbik 0U, // VPSRAQZ128mbikz 0U, // VPSRAQZ128mi 0U, // VPSRAQZ128mik 0U, // VPSRAQZ128mikz 0U, // VPSRAQZ128ri 0U, // VPSRAQZ128rik 0U, // VPSRAQZ128rikz 0U, // VPSRAQZ128rm 0U, // VPSRAQZ128rmk 0U, // VPSRAQZ128rmkz 0U, // VPSRAQZ128rr 0U, // VPSRAQZ128rrk 0U, // VPSRAQZ128rrkz 0U, // VPSRAQZ256mbi 0U, // VPSRAQZ256mbik 0U, // VPSRAQZ256mbikz 0U, // VPSRAQZ256mi 0U, // VPSRAQZ256mik 0U, // VPSRAQZ256mikz 0U, // VPSRAQZ256ri 0U, // VPSRAQZ256rik 0U, // VPSRAQZ256rikz 0U, // VPSRAQZ256rm 0U, // VPSRAQZ256rmk 0U, // VPSRAQZ256rmkz 0U, // VPSRAQZ256rr 0U, // VPSRAQZ256rrk 0U, // VPSRAQZ256rrkz 0U, // VPSRAQZmbi 0U, // VPSRAQZmbik 0U, // VPSRAQZmbikz 0U, // VPSRAQZmi 0U, // VPSRAQZmik 0U, // VPSRAQZmikz 0U, // VPSRAQZri 0U, // VPSRAQZrik 0U, // VPSRAQZrikz 0U, // VPSRAQZrm 0U, // VPSRAQZrmk 0U, // VPSRAQZrmkz 0U, // VPSRAQZrr 0U, // VPSRAQZrrk 0U, // VPSRAQZrrkz 0U, // VPSRAVDYrm 0U, // VPSRAVDYrr 0U, // VPSRAVDZ128rm 0U, // VPSRAVDZ128rmb 0U, // VPSRAVDZ128rmbk 0U, // VPSRAVDZ128rmbkz 0U, // VPSRAVDZ128rmk 0U, // VPSRAVDZ128rmkz 0U, // VPSRAVDZ128rr 0U, // VPSRAVDZ128rrk 0U, // VPSRAVDZ128rrkz 0U, // VPSRAVDZ256rm 0U, // VPSRAVDZ256rmb 0U, // VPSRAVDZ256rmbk 0U, // VPSRAVDZ256rmbkz 0U, // VPSRAVDZ256rmk 0U, // VPSRAVDZ256rmkz 0U, // VPSRAVDZ256rr 0U, // VPSRAVDZ256rrk 0U, // VPSRAVDZ256rrkz 0U, // VPSRAVDZrm 0U, // VPSRAVDZrmb 0U, // VPSRAVDZrmbk 0U, // VPSRAVDZrmbkz 0U, // VPSRAVDZrmk 0U, // VPSRAVDZrmkz 0U, // VPSRAVDZrr 0U, // VPSRAVDZrrk 0U, // VPSRAVDZrrkz 0U, // VPSRAVDrm 0U, // VPSRAVDrr 0U, // VPSRAVQZ128rm 0U, // VPSRAVQZ128rmb 0U, // VPSRAVQZ128rmbk 0U, // VPSRAVQZ128rmbkz 0U, // VPSRAVQZ128rmk 0U, // VPSRAVQZ128rmkz 0U, // VPSRAVQZ128rr 0U, // VPSRAVQZ128rrk 0U, // VPSRAVQZ128rrkz 0U, // VPSRAVQZ256rm 0U, // VPSRAVQZ256rmb 0U, // VPSRAVQZ256rmbk 0U, // VPSRAVQZ256rmbkz 0U, // VPSRAVQZ256rmk 0U, // VPSRAVQZ256rmkz 0U, // VPSRAVQZ256rr 0U, // VPSRAVQZ256rrk 0U, // VPSRAVQZ256rrkz 0U, // VPSRAVQZrm 0U, // VPSRAVQZrmb 0U, // VPSRAVQZrmbk 0U, // VPSRAVQZrmbkz 0U, // VPSRAVQZrmk 0U, // VPSRAVQZrmkz 0U, // VPSRAVQZrr 0U, // VPSRAVQZrrk 0U, // VPSRAVQZrrkz 0U, // VPSRAVWZ128rm 0U, // VPSRAVWZ128rmk 0U, // VPSRAVWZ128rmkz 0U, // VPSRAVWZ128rr 0U, // VPSRAVWZ128rrk 0U, // VPSRAVWZ128rrkz 0U, // VPSRAVWZ256rm 0U, // VPSRAVWZ256rmk 0U, // VPSRAVWZ256rmkz 0U, // VPSRAVWZ256rr 0U, // VPSRAVWZ256rrk 0U, // VPSRAVWZ256rrkz 0U, // VPSRAVWZrm 0U, // VPSRAVWZrmk 0U, // VPSRAVWZrmkz 0U, // VPSRAVWZrr 0U, // VPSRAVWZrrk 0U, // VPSRAVWZrrkz 0U, // VPSRAWYri 0U, // VPSRAWYrm 0U, // VPSRAWYrr 0U, // VPSRAWZ128mi 0U, // VPSRAWZ128mik 0U, // VPSRAWZ128mikz 0U, // VPSRAWZ128ri 0U, // VPSRAWZ128rik 0U, // VPSRAWZ128rikz 0U, // VPSRAWZ128rm 0U, // VPSRAWZ128rmk 0U, // VPSRAWZ128rmkz 0U, // VPSRAWZ128rr 0U, // VPSRAWZ128rrk 0U, // VPSRAWZ128rrkz 0U, // VPSRAWZ256mi 0U, // VPSRAWZ256mik 0U, // VPSRAWZ256mikz 0U, // VPSRAWZ256ri 0U, // VPSRAWZ256rik 0U, // VPSRAWZ256rikz 0U, // VPSRAWZ256rm 0U, // VPSRAWZ256rmk 0U, // VPSRAWZ256rmkz 0U, // VPSRAWZ256rr 0U, // VPSRAWZ256rrk 0U, // VPSRAWZ256rrkz 0U, // VPSRAWZmi 0U, // VPSRAWZmik 0U, // VPSRAWZmikz 0U, // VPSRAWZri 0U, // VPSRAWZrik 0U, // VPSRAWZrikz 0U, // VPSRAWZrm 0U, // VPSRAWZrmk 0U, // VPSRAWZrmkz 0U, // VPSRAWZrr 0U, // VPSRAWZrrk 0U, // VPSRAWZrrkz 0U, // VPSRAWri 0U, // VPSRAWrm 0U, // VPSRAWrr 0U, // VPSRLDQYri 0U, // VPSRLDQZ128rm 0U, // VPSRLDQZ128rr 0U, // VPSRLDQZ256rm 0U, // VPSRLDQZ256rr 0U, // VPSRLDQZrm 0U, // VPSRLDQZrr 0U, // VPSRLDQri 0U, // VPSRLDYri 0U, // VPSRLDYrm 0U, // VPSRLDYrr 0U, // VPSRLDZ128mbi 0U, // VPSRLDZ128mbik 0U, // VPSRLDZ128mbikz 0U, // VPSRLDZ128mi 0U, // VPSRLDZ128mik 0U, // VPSRLDZ128mikz 0U, // VPSRLDZ128ri 0U, // VPSRLDZ128rik 0U, // VPSRLDZ128rikz 0U, // VPSRLDZ128rm 0U, // VPSRLDZ128rmk 0U, // VPSRLDZ128rmkz 0U, // VPSRLDZ128rr 0U, // VPSRLDZ128rrk 0U, // VPSRLDZ128rrkz 0U, // VPSRLDZ256mbi 0U, // VPSRLDZ256mbik 0U, // VPSRLDZ256mbikz 0U, // VPSRLDZ256mi 0U, // VPSRLDZ256mik 0U, // VPSRLDZ256mikz 0U, // VPSRLDZ256ri 0U, // VPSRLDZ256rik 0U, // VPSRLDZ256rikz 0U, // VPSRLDZ256rm 0U, // VPSRLDZ256rmk 0U, // VPSRLDZ256rmkz 0U, // VPSRLDZ256rr 0U, // VPSRLDZ256rrk 0U, // VPSRLDZ256rrkz 0U, // VPSRLDZmbi 0U, // VPSRLDZmbik 0U, // VPSRLDZmbikz 0U, // VPSRLDZmi 0U, // VPSRLDZmik 0U, // VPSRLDZmikz 0U, // VPSRLDZri 0U, // VPSRLDZrik 0U, // VPSRLDZrikz 0U, // VPSRLDZrm 0U, // VPSRLDZrmk 0U, // VPSRLDZrmkz 0U, // VPSRLDZrr 0U, // VPSRLDZrrk 0U, // VPSRLDZrrkz 0U, // VPSRLDri 0U, // VPSRLDrm 0U, // VPSRLDrr 0U, // VPSRLQYri 0U, // VPSRLQYrm 0U, // VPSRLQYrr 0U, // VPSRLQZ128mbi 0U, // VPSRLQZ128mbik 0U, // VPSRLQZ128mbikz 0U, // VPSRLQZ128mi 0U, // VPSRLQZ128mik 0U, // VPSRLQZ128mikz 0U, // VPSRLQZ128ri 0U, // VPSRLQZ128rik 0U, // VPSRLQZ128rikz 0U, // VPSRLQZ128rm 0U, // VPSRLQZ128rmk 0U, // VPSRLQZ128rmkz 0U, // VPSRLQZ128rr 0U, // VPSRLQZ128rrk 0U, // VPSRLQZ128rrkz 0U, // VPSRLQZ256mbi 0U, // VPSRLQZ256mbik 0U, // VPSRLQZ256mbikz 0U, // VPSRLQZ256mi 0U, // VPSRLQZ256mik 0U, // VPSRLQZ256mikz 0U, // VPSRLQZ256ri 0U, // VPSRLQZ256rik 0U, // VPSRLQZ256rikz 0U, // VPSRLQZ256rm 0U, // VPSRLQZ256rmk 0U, // VPSRLQZ256rmkz 0U, // VPSRLQZ256rr 0U, // VPSRLQZ256rrk 0U, // VPSRLQZ256rrkz 0U, // VPSRLQZmbi 0U, // VPSRLQZmbik 0U, // VPSRLQZmbikz 0U, // VPSRLQZmi 0U, // VPSRLQZmik 0U, // VPSRLQZmikz 0U, // VPSRLQZri 0U, // VPSRLQZrik 0U, // VPSRLQZrikz 0U, // VPSRLQZrm 0U, // VPSRLQZrmk 0U, // VPSRLQZrmkz 0U, // VPSRLQZrr 0U, // VPSRLQZrrk 0U, // VPSRLQZrrkz 0U, // VPSRLQri 0U, // VPSRLQrm 0U, // VPSRLQrr 0U, // VPSRLVDYrm 0U, // VPSRLVDYrr 0U, // VPSRLVDZ128rm 0U, // VPSRLVDZ128rmb 0U, // VPSRLVDZ128rmbk 0U, // VPSRLVDZ128rmbkz 0U, // VPSRLVDZ128rmk 0U, // VPSRLVDZ128rmkz 0U, // VPSRLVDZ128rr 0U, // VPSRLVDZ128rrk 0U, // VPSRLVDZ128rrkz 0U, // VPSRLVDZ256rm 0U, // VPSRLVDZ256rmb 0U, // VPSRLVDZ256rmbk 0U, // VPSRLVDZ256rmbkz 0U, // VPSRLVDZ256rmk 0U, // VPSRLVDZ256rmkz 0U, // VPSRLVDZ256rr 0U, // VPSRLVDZ256rrk 0U, // VPSRLVDZ256rrkz 0U, // VPSRLVDZrm 0U, // VPSRLVDZrmb 0U, // VPSRLVDZrmbk 0U, // VPSRLVDZrmbkz 0U, // VPSRLVDZrmk 0U, // VPSRLVDZrmkz 0U, // VPSRLVDZrr 0U, // VPSRLVDZrrk 0U, // VPSRLVDZrrkz 0U, // VPSRLVDrm 0U, // VPSRLVDrr 0U, // VPSRLVQYrm 0U, // VPSRLVQYrr 0U, // VPSRLVQZ128rm 0U, // VPSRLVQZ128rmb 0U, // VPSRLVQZ128rmbk 0U, // VPSRLVQZ128rmbkz 0U, // VPSRLVQZ128rmk 0U, // VPSRLVQZ128rmkz 0U, // VPSRLVQZ128rr 0U, // VPSRLVQZ128rrk 0U, // VPSRLVQZ128rrkz 0U, // VPSRLVQZ256rm 0U, // VPSRLVQZ256rmb 0U, // VPSRLVQZ256rmbk 0U, // VPSRLVQZ256rmbkz 0U, // VPSRLVQZ256rmk 0U, // VPSRLVQZ256rmkz 0U, // VPSRLVQZ256rr 0U, // VPSRLVQZ256rrk 0U, // VPSRLVQZ256rrkz 0U, // VPSRLVQZrm 0U, // VPSRLVQZrmb 0U, // VPSRLVQZrmbk 0U, // VPSRLVQZrmbkz 0U, // VPSRLVQZrmk 0U, // VPSRLVQZrmkz 0U, // VPSRLVQZrr 0U, // VPSRLVQZrrk 0U, // VPSRLVQZrrkz 0U, // VPSRLVQrm 0U, // VPSRLVQrr 0U, // VPSRLVWZ128rm 0U, // VPSRLVWZ128rmk 0U, // VPSRLVWZ128rmkz 0U, // VPSRLVWZ128rr 0U, // VPSRLVWZ128rrk 0U, // VPSRLVWZ128rrkz 0U, // VPSRLVWZ256rm 0U, // VPSRLVWZ256rmk 0U, // VPSRLVWZ256rmkz 0U, // VPSRLVWZ256rr 0U, // VPSRLVWZ256rrk 0U, // VPSRLVWZ256rrkz 0U, // VPSRLVWZrm 0U, // VPSRLVWZrmk 0U, // VPSRLVWZrmkz 0U, // VPSRLVWZrr 0U, // VPSRLVWZrrk 0U, // VPSRLVWZrrkz 0U, // VPSRLWYri 0U, // VPSRLWYrm 0U, // VPSRLWYrr 0U, // VPSRLWZ128mi 0U, // VPSRLWZ128mik 0U, // VPSRLWZ128mikz 0U, // VPSRLWZ128ri 0U, // VPSRLWZ128rik 0U, // VPSRLWZ128rikz 0U, // VPSRLWZ128rm 0U, // VPSRLWZ128rmk 0U, // VPSRLWZ128rmkz 0U, // VPSRLWZ128rr 0U, // VPSRLWZ128rrk 0U, // VPSRLWZ128rrkz 0U, // VPSRLWZ256mi 0U, // VPSRLWZ256mik 0U, // VPSRLWZ256mikz 0U, // VPSRLWZ256ri 0U, // VPSRLWZ256rik 0U, // VPSRLWZ256rikz 0U, // VPSRLWZ256rm 0U, // VPSRLWZ256rmk 0U, // VPSRLWZ256rmkz 0U, // VPSRLWZ256rr 0U, // VPSRLWZ256rrk 0U, // VPSRLWZ256rrkz 0U, // VPSRLWZmi 0U, // VPSRLWZmik 0U, // VPSRLWZmikz 0U, // VPSRLWZri 0U, // VPSRLWZrik 0U, // VPSRLWZrikz 0U, // VPSRLWZrm 0U, // VPSRLWZrmk 0U, // VPSRLWZrmkz 0U, // VPSRLWZrr 0U, // VPSRLWZrrk 0U, // VPSRLWZrrkz 0U, // VPSRLWri 0U, // VPSRLWrm 0U, // VPSRLWrr 0U, // VPSUBBYrm 0U, // VPSUBBYrr 0U, // VPSUBBZ128rm 0U, // VPSUBBZ128rmk 0U, // VPSUBBZ128rmkz 0U, // VPSUBBZ128rr 0U, // VPSUBBZ128rrk 0U, // VPSUBBZ128rrkz 0U, // VPSUBBZ256rm 0U, // VPSUBBZ256rmk 0U, // VPSUBBZ256rmkz 0U, // VPSUBBZ256rr 0U, // VPSUBBZ256rrk 0U, // VPSUBBZ256rrkz 0U, // VPSUBBZrm 0U, // VPSUBBZrmk 0U, // VPSUBBZrmkz 0U, // VPSUBBZrr 0U, // VPSUBBZrrk 0U, // VPSUBBZrrkz 0U, // VPSUBBrm 0U, // VPSUBBrr 0U, // VPSUBDYrm 0U, // VPSUBDYrr 0U, // VPSUBDZ128rm 0U, // VPSUBDZ128rmb 0U, // VPSUBDZ128rmbk 0U, // VPSUBDZ128rmbkz 0U, // VPSUBDZ128rmk 0U, // VPSUBDZ128rmkz 0U, // VPSUBDZ128rr 0U, // VPSUBDZ128rrk 0U, // VPSUBDZ128rrkz 0U, // VPSUBDZ256rm 0U, // VPSUBDZ256rmb 0U, // VPSUBDZ256rmbk 0U, // VPSUBDZ256rmbkz 0U, // VPSUBDZ256rmk 0U, // VPSUBDZ256rmkz 0U, // VPSUBDZ256rr 0U, // VPSUBDZ256rrk 0U, // VPSUBDZ256rrkz 0U, // VPSUBDZrm 0U, // VPSUBDZrmb 0U, // VPSUBDZrmbk 0U, // VPSUBDZrmbkz 0U, // VPSUBDZrmk 0U, // VPSUBDZrmkz 0U, // VPSUBDZrr 0U, // VPSUBDZrrk 0U, // VPSUBDZrrkz 0U, // VPSUBDrm 0U, // VPSUBDrr 0U, // VPSUBQYrm 0U, // VPSUBQYrr 0U, // VPSUBQZ128rm 0U, // VPSUBQZ128rmb 0U, // VPSUBQZ128rmbk 0U, // VPSUBQZ128rmbkz 0U, // VPSUBQZ128rmk 0U, // VPSUBQZ128rmkz 0U, // VPSUBQZ128rr 0U, // VPSUBQZ128rrk 0U, // VPSUBQZ128rrkz 0U, // VPSUBQZ256rm 0U, // VPSUBQZ256rmb 0U, // VPSUBQZ256rmbk 0U, // VPSUBQZ256rmbkz 0U, // VPSUBQZ256rmk 0U, // VPSUBQZ256rmkz 0U, // VPSUBQZ256rr 0U, // VPSUBQZ256rrk 0U, // VPSUBQZ256rrkz 0U, // VPSUBQZrm 0U, // VPSUBQZrmb 0U, // VPSUBQZrmbk 0U, // VPSUBQZrmbkz 0U, // VPSUBQZrmk 0U, // VPSUBQZrmkz 0U, // VPSUBQZrr 0U, // VPSUBQZrrk 0U, // VPSUBQZrrkz 0U, // VPSUBQrm 0U, // VPSUBQrr 0U, // VPSUBSBYrm 0U, // VPSUBSBYrr 0U, // VPSUBSBZ128rm 0U, // VPSUBSBZ128rmk 0U, // VPSUBSBZ128rmkz 0U, // VPSUBSBZ128rr 0U, // VPSUBSBZ128rrk 0U, // VPSUBSBZ128rrkz 0U, // VPSUBSBZ256rm 0U, // VPSUBSBZ256rmk 0U, // VPSUBSBZ256rmkz 0U, // VPSUBSBZ256rr 0U, // VPSUBSBZ256rrk 0U, // VPSUBSBZ256rrkz 0U, // VPSUBSBZrm 0U, // VPSUBSBZrmk 0U, // VPSUBSBZrmkz 0U, // VPSUBSBZrr 0U, // VPSUBSBZrrk 0U, // VPSUBSBZrrkz 0U, // VPSUBSBrm 0U, // VPSUBSBrr 0U, // VPSUBSWYrm 0U, // VPSUBSWYrr 0U, // VPSUBSWZ128rm 0U, // VPSUBSWZ128rmk 0U, // VPSUBSWZ128rmkz 0U, // VPSUBSWZ128rr 0U, // VPSUBSWZ128rrk 0U, // VPSUBSWZ128rrkz 0U, // VPSUBSWZ256rm 0U, // VPSUBSWZ256rmk 0U, // VPSUBSWZ256rmkz 0U, // VPSUBSWZ256rr 0U, // VPSUBSWZ256rrk 0U, // VPSUBSWZ256rrkz 0U, // VPSUBSWZrm 0U, // VPSUBSWZrmk 0U, // VPSUBSWZrmkz 0U, // VPSUBSWZrr 0U, // VPSUBSWZrrk 0U, // VPSUBSWZrrkz 0U, // VPSUBSWrm 0U, // VPSUBSWrr 0U, // VPSUBUSBYrm 0U, // VPSUBUSBYrr 0U, // VPSUBUSBZ128rm 0U, // VPSUBUSBZ128rmk 0U, // VPSUBUSBZ128rmkz 0U, // VPSUBUSBZ128rr 0U, // VPSUBUSBZ128rrk 0U, // VPSUBUSBZ128rrkz 0U, // VPSUBUSBZ256rm 0U, // VPSUBUSBZ256rmk 0U, // VPSUBUSBZ256rmkz 0U, // VPSUBUSBZ256rr 0U, // VPSUBUSBZ256rrk 0U, // VPSUBUSBZ256rrkz 0U, // VPSUBUSBZrm 0U, // VPSUBUSBZrmk 0U, // VPSUBUSBZrmkz 0U, // VPSUBUSBZrr 0U, // VPSUBUSBZrrk 0U, // VPSUBUSBZrrkz 0U, // VPSUBUSBrm 0U, // VPSUBUSBrr 0U, // VPSUBUSWYrm 0U, // VPSUBUSWYrr 0U, // VPSUBUSWZ128rm 0U, // VPSUBUSWZ128rmk 0U, // VPSUBUSWZ128rmkz 0U, // VPSUBUSWZ128rr 0U, // VPSUBUSWZ128rrk 0U, // VPSUBUSWZ128rrkz 0U, // VPSUBUSWZ256rm 0U, // VPSUBUSWZ256rmk 0U, // VPSUBUSWZ256rmkz 0U, // VPSUBUSWZ256rr 0U, // VPSUBUSWZ256rrk 0U, // VPSUBUSWZ256rrkz 0U, // VPSUBUSWZrm 0U, // VPSUBUSWZrmk 0U, // VPSUBUSWZrmkz 0U, // VPSUBUSWZrr 0U, // VPSUBUSWZrrk 0U, // VPSUBUSWZrrkz 0U, // VPSUBUSWrm 0U, // VPSUBUSWrr 0U, // VPSUBWYrm 0U, // VPSUBWYrr 0U, // VPSUBWZ128rm 0U, // VPSUBWZ128rmk 0U, // VPSUBWZ128rmkz 0U, // VPSUBWZ128rr 0U, // VPSUBWZ128rrk 0U, // VPSUBWZ128rrkz 0U, // VPSUBWZ256rm 0U, // VPSUBWZ256rmk 0U, // VPSUBWZ256rmkz 0U, // VPSUBWZ256rr 0U, // VPSUBWZ256rrk 0U, // VPSUBWZ256rrkz 0U, // VPSUBWZrm 0U, // VPSUBWZrmk 0U, // VPSUBWZrmkz 0U, // VPSUBWZrr 0U, // VPSUBWZrrk 0U, // VPSUBWZrrkz 0U, // VPSUBWrm 0U, // VPSUBWrr 0U, // VPTERNLOGDZ128rmbi 0U, // VPTERNLOGDZ128rmbik 2U, // VPTERNLOGDZ128rmbikz 0U, // VPTERNLOGDZ128rmi 0U, // VPTERNLOGDZ128rmik 0U, // VPTERNLOGDZ128rmikz 0U, // VPTERNLOGDZ128rri 0U, // VPTERNLOGDZ128rrik 0U, // VPTERNLOGDZ128rrikz 0U, // VPTERNLOGDZ256rmbi 0U, // VPTERNLOGDZ256rmbik 2U, // VPTERNLOGDZ256rmbikz 0U, // VPTERNLOGDZ256rmi 0U, // VPTERNLOGDZ256rmik 0U, // VPTERNLOGDZ256rmikz 0U, // VPTERNLOGDZ256rri 0U, // VPTERNLOGDZ256rrik 0U, // VPTERNLOGDZ256rrikz 0U, // VPTERNLOGDZrmbi 0U, // VPTERNLOGDZrmbik 2U, // VPTERNLOGDZrmbikz 0U, // VPTERNLOGDZrmi 0U, // VPTERNLOGDZrmik 0U, // VPTERNLOGDZrmikz 0U, // VPTERNLOGDZrri 0U, // VPTERNLOGDZrrik 0U, // VPTERNLOGDZrrikz 0U, // VPTERNLOGQZ128rmbi 0U, // VPTERNLOGQZ128rmbik 2U, // VPTERNLOGQZ128rmbikz 0U, // VPTERNLOGQZ128rmi 0U, // VPTERNLOGQZ128rmik 0U, // VPTERNLOGQZ128rmikz 0U, // VPTERNLOGQZ128rri 0U, // VPTERNLOGQZ128rrik 0U, // VPTERNLOGQZ128rrikz 0U, // VPTERNLOGQZ256rmbi 0U, // VPTERNLOGQZ256rmbik 2U, // VPTERNLOGQZ256rmbikz 0U, // VPTERNLOGQZ256rmi 0U, // VPTERNLOGQZ256rmik 0U, // VPTERNLOGQZ256rmikz 0U, // VPTERNLOGQZ256rri 0U, // VPTERNLOGQZ256rrik 0U, // VPTERNLOGQZ256rrikz 0U, // VPTERNLOGQZrmbi 0U, // VPTERNLOGQZrmbik 2U, // VPTERNLOGQZrmbikz 0U, // VPTERNLOGQZrmi 0U, // VPTERNLOGQZrmik 0U, // VPTERNLOGQZrmikz 0U, // VPTERNLOGQZrri 0U, // VPTERNLOGQZrrik 0U, // VPTERNLOGQZrrikz 0U, // VPTESTMBZ128rm 0U, // VPTESTMBZ128rmk 0U, // VPTESTMBZ128rr 0U, // VPTESTMBZ128rrk 0U, // VPTESTMBZ256rm 0U, // VPTESTMBZ256rmk 0U, // VPTESTMBZ256rr 0U, // VPTESTMBZ256rrk 0U, // VPTESTMBZrm 0U, // VPTESTMBZrmk 0U, // VPTESTMBZrr 0U, // VPTESTMBZrrk 0U, // VPTESTMDZ128rm 0U, // VPTESTMDZ128rmb 0U, // VPTESTMDZ128rmbk 0U, // VPTESTMDZ128rmk 0U, // VPTESTMDZ128rr 0U, // VPTESTMDZ128rrk 0U, // VPTESTMDZ256rm 0U, // VPTESTMDZ256rmb 0U, // VPTESTMDZ256rmbk 0U, // VPTESTMDZ256rmk 0U, // VPTESTMDZ256rr 0U, // VPTESTMDZ256rrk 0U, // VPTESTMDZrm 0U, // VPTESTMDZrmb 0U, // VPTESTMDZrmbk 0U, // VPTESTMDZrmk 0U, // VPTESTMDZrr 0U, // VPTESTMDZrrk 0U, // VPTESTMQZ128rm 0U, // VPTESTMQZ128rmb 0U, // VPTESTMQZ128rmbk 0U, // VPTESTMQZ128rmk 0U, // VPTESTMQZ128rr 0U, // VPTESTMQZ128rrk 0U, // VPTESTMQZ256rm 0U, // VPTESTMQZ256rmb 0U, // VPTESTMQZ256rmbk 0U, // VPTESTMQZ256rmk 0U, // VPTESTMQZ256rr 0U, // VPTESTMQZ256rrk 0U, // VPTESTMQZrm 0U, // VPTESTMQZrmb 0U, // VPTESTMQZrmbk 0U, // VPTESTMQZrmk 0U, // VPTESTMQZrr 0U, // VPTESTMQZrrk 0U, // VPTESTMWZ128rm 0U, // VPTESTMWZ128rmk 0U, // VPTESTMWZ128rr 0U, // VPTESTMWZ128rrk 0U, // VPTESTMWZ256rm 0U, // VPTESTMWZ256rmk 0U, // VPTESTMWZ256rr 0U, // VPTESTMWZ256rrk 0U, // VPTESTMWZrm 0U, // VPTESTMWZrmk 0U, // VPTESTMWZrr 0U, // VPTESTMWZrrk 0U, // VPTESTNMBZ128rm 0U, // VPTESTNMBZ128rmk 0U, // VPTESTNMBZ128rr 0U, // VPTESTNMBZ128rrk 0U, // VPTESTNMBZ256rm 0U, // VPTESTNMBZ256rmk 0U, // VPTESTNMBZ256rr 0U, // VPTESTNMBZ256rrk 0U, // VPTESTNMBZrm 0U, // VPTESTNMBZrmk 0U, // VPTESTNMBZrr 0U, // VPTESTNMBZrrk 0U, // VPTESTNMDZ128rm 0U, // VPTESTNMDZ128rmb 0U, // VPTESTNMDZ128rmbk 0U, // VPTESTNMDZ128rmk 0U, // VPTESTNMDZ128rr 0U, // VPTESTNMDZ128rrk 0U, // VPTESTNMDZ256rm 0U, // VPTESTNMDZ256rmb 0U, // VPTESTNMDZ256rmbk 0U, // VPTESTNMDZ256rmk 0U, // VPTESTNMDZ256rr 0U, // VPTESTNMDZ256rrk 0U, // VPTESTNMDZrm 0U, // VPTESTNMDZrmb 0U, // VPTESTNMDZrmbk 0U, // VPTESTNMDZrmk 0U, // VPTESTNMDZrr 0U, // VPTESTNMDZrrk 0U, // VPTESTNMQZ128rm 0U, // VPTESTNMQZ128rmb 0U, // VPTESTNMQZ128rmbk 0U, // VPTESTNMQZ128rmk 0U, // VPTESTNMQZ128rr 0U, // VPTESTNMQZ128rrk 0U, // VPTESTNMQZ256rm 0U, // VPTESTNMQZ256rmb 0U, // VPTESTNMQZ256rmbk 0U, // VPTESTNMQZ256rmk 0U, // VPTESTNMQZ256rr 0U, // VPTESTNMQZ256rrk 0U, // VPTESTNMQZrm 0U, // VPTESTNMQZrmb 0U, // VPTESTNMQZrmbk 0U, // VPTESTNMQZrmk 0U, // VPTESTNMQZrr 0U, // VPTESTNMQZrrk 0U, // VPTESTNMWZ128rm 0U, // VPTESTNMWZ128rmk 0U, // VPTESTNMWZ128rr 0U, // VPTESTNMWZ128rrk 0U, // VPTESTNMWZ256rm 0U, // VPTESTNMWZ256rmk 0U, // VPTESTNMWZ256rr 0U, // VPTESTNMWZ256rrk 0U, // VPTESTNMWZrm 0U, // VPTESTNMWZrmk 0U, // VPTESTNMWZrr 0U, // VPTESTNMWZrrk 0U, // VPTESTYrm 0U, // VPTESTYrr 0U, // VPTESTrm 0U, // VPTESTrr 0U, // VPUNPCKHBWYrm 0U, // VPUNPCKHBWYrr 0U, // VPUNPCKHBWZ128rm 0U, // VPUNPCKHBWZ128rmk 0U, // VPUNPCKHBWZ128rmkz 0U, // VPUNPCKHBWZ128rr 0U, // VPUNPCKHBWZ128rrk 0U, // VPUNPCKHBWZ128rrkz 0U, // VPUNPCKHBWZ256rm 0U, // VPUNPCKHBWZ256rmk 0U, // VPUNPCKHBWZ256rmkz 0U, // VPUNPCKHBWZ256rr 0U, // VPUNPCKHBWZ256rrk 0U, // VPUNPCKHBWZ256rrkz 0U, // VPUNPCKHBWZrm 0U, // VPUNPCKHBWZrmk 0U, // VPUNPCKHBWZrmkz 0U, // VPUNPCKHBWZrr 0U, // VPUNPCKHBWZrrk 0U, // VPUNPCKHBWZrrkz 0U, // VPUNPCKHBWrm 0U, // VPUNPCKHBWrr 0U, // VPUNPCKHDQYrm 0U, // VPUNPCKHDQYrr 0U, // VPUNPCKHDQZ128rm 0U, // VPUNPCKHDQZ128rmb 0U, // VPUNPCKHDQZ128rmbk 0U, // VPUNPCKHDQZ128rmbkz 0U, // VPUNPCKHDQZ128rmk 0U, // VPUNPCKHDQZ128rmkz 0U, // VPUNPCKHDQZ128rr 0U, // VPUNPCKHDQZ128rrk 0U, // VPUNPCKHDQZ128rrkz 0U, // VPUNPCKHDQZ256rm 0U, // VPUNPCKHDQZ256rmb 0U, // VPUNPCKHDQZ256rmbk 0U, // VPUNPCKHDQZ256rmbkz 0U, // VPUNPCKHDQZ256rmk 0U, // VPUNPCKHDQZ256rmkz 0U, // VPUNPCKHDQZ256rr 0U, // VPUNPCKHDQZ256rrk 0U, // VPUNPCKHDQZ256rrkz 0U, // VPUNPCKHDQZrm 0U, // VPUNPCKHDQZrmb 0U, // VPUNPCKHDQZrmbk 0U, // VPUNPCKHDQZrmbkz 0U, // VPUNPCKHDQZrmk 0U, // VPUNPCKHDQZrmkz 0U, // VPUNPCKHDQZrr 0U, // VPUNPCKHDQZrrk 0U, // VPUNPCKHDQZrrkz 0U, // VPUNPCKHDQrm 0U, // VPUNPCKHDQrr 0U, // VPUNPCKHQDQYrm 0U, // VPUNPCKHQDQYrr 0U, // VPUNPCKHQDQZ128rm 0U, // VPUNPCKHQDQZ128rmb 0U, // VPUNPCKHQDQZ128rmbk 0U, // VPUNPCKHQDQZ128rmbkz 0U, // VPUNPCKHQDQZ128rmk 0U, // VPUNPCKHQDQZ128rmkz 0U, // VPUNPCKHQDQZ128rr 0U, // VPUNPCKHQDQZ128rrk 0U, // VPUNPCKHQDQZ128rrkz 0U, // VPUNPCKHQDQZ256rm 0U, // VPUNPCKHQDQZ256rmb 0U, // VPUNPCKHQDQZ256rmbk 0U, // VPUNPCKHQDQZ256rmbkz 0U, // VPUNPCKHQDQZ256rmk 0U, // VPUNPCKHQDQZ256rmkz 0U, // VPUNPCKHQDQZ256rr 0U, // VPUNPCKHQDQZ256rrk 0U, // VPUNPCKHQDQZ256rrkz 0U, // VPUNPCKHQDQZrm 0U, // VPUNPCKHQDQZrmb 0U, // VPUNPCKHQDQZrmbk 0U, // VPUNPCKHQDQZrmbkz 0U, // VPUNPCKHQDQZrmk 0U, // VPUNPCKHQDQZrmkz 0U, // VPUNPCKHQDQZrr 0U, // VPUNPCKHQDQZrrk 0U, // VPUNPCKHQDQZrrkz 0U, // VPUNPCKHQDQrm 0U, // VPUNPCKHQDQrr 0U, // VPUNPCKHWDYrm 0U, // VPUNPCKHWDYrr 0U, // VPUNPCKHWDZ128rm 0U, // VPUNPCKHWDZ128rmk 0U, // VPUNPCKHWDZ128rmkz 0U, // VPUNPCKHWDZ128rr 0U, // VPUNPCKHWDZ128rrk 0U, // VPUNPCKHWDZ128rrkz 0U, // VPUNPCKHWDZ256rm 0U, // VPUNPCKHWDZ256rmk 0U, // VPUNPCKHWDZ256rmkz 0U, // VPUNPCKHWDZ256rr 0U, // VPUNPCKHWDZ256rrk 0U, // VPUNPCKHWDZ256rrkz 0U, // VPUNPCKHWDZrm 0U, // VPUNPCKHWDZrmk 0U, // VPUNPCKHWDZrmkz 0U, // VPUNPCKHWDZrr 0U, // VPUNPCKHWDZrrk 0U, // VPUNPCKHWDZrrkz 0U, // VPUNPCKHWDrm 0U, // VPUNPCKHWDrr 0U, // VPUNPCKLBWYrm 0U, // VPUNPCKLBWYrr 0U, // VPUNPCKLBWZ128rm 0U, // VPUNPCKLBWZ128rmk 0U, // VPUNPCKLBWZ128rmkz 0U, // VPUNPCKLBWZ128rr 0U, // VPUNPCKLBWZ128rrk 0U, // VPUNPCKLBWZ128rrkz 0U, // VPUNPCKLBWZ256rm 0U, // VPUNPCKLBWZ256rmk 0U, // VPUNPCKLBWZ256rmkz 0U, // VPUNPCKLBWZ256rr 0U, // VPUNPCKLBWZ256rrk 0U, // VPUNPCKLBWZ256rrkz 0U, // VPUNPCKLBWZrm 0U, // VPUNPCKLBWZrmk 0U, // VPUNPCKLBWZrmkz 0U, // VPUNPCKLBWZrr 0U, // VPUNPCKLBWZrrk 0U, // VPUNPCKLBWZrrkz 0U, // VPUNPCKLBWrm 0U, // VPUNPCKLBWrr 0U, // VPUNPCKLDQYrm 0U, // VPUNPCKLDQYrr 0U, // VPUNPCKLDQZ128rm 0U, // VPUNPCKLDQZ128rmb 0U, // VPUNPCKLDQZ128rmbk 0U, // VPUNPCKLDQZ128rmbkz 0U, // VPUNPCKLDQZ128rmk 0U, // VPUNPCKLDQZ128rmkz 0U, // VPUNPCKLDQZ128rr 0U, // VPUNPCKLDQZ128rrk 0U, // VPUNPCKLDQZ128rrkz 0U, // VPUNPCKLDQZ256rm 0U, // VPUNPCKLDQZ256rmb 0U, // VPUNPCKLDQZ256rmbk 0U, // VPUNPCKLDQZ256rmbkz 0U, // VPUNPCKLDQZ256rmk 0U, // VPUNPCKLDQZ256rmkz 0U, // VPUNPCKLDQZ256rr 0U, // VPUNPCKLDQZ256rrk 0U, // VPUNPCKLDQZ256rrkz 0U, // VPUNPCKLDQZrm 0U, // VPUNPCKLDQZrmb 0U, // VPUNPCKLDQZrmbk 0U, // VPUNPCKLDQZrmbkz 0U, // VPUNPCKLDQZrmk 0U, // VPUNPCKLDQZrmkz 0U, // VPUNPCKLDQZrr 0U, // VPUNPCKLDQZrrk 0U, // VPUNPCKLDQZrrkz 0U, // VPUNPCKLDQrm 0U, // VPUNPCKLDQrr 0U, // VPUNPCKLQDQYrm 0U, // VPUNPCKLQDQYrr 0U, // VPUNPCKLQDQZ128rm 0U, // VPUNPCKLQDQZ128rmb 0U, // VPUNPCKLQDQZ128rmbk 0U, // VPUNPCKLQDQZ128rmbkz 0U, // VPUNPCKLQDQZ128rmk 0U, // VPUNPCKLQDQZ128rmkz 0U, // VPUNPCKLQDQZ128rr 0U, // VPUNPCKLQDQZ128rrk 0U, // VPUNPCKLQDQZ128rrkz 0U, // VPUNPCKLQDQZ256rm 0U, // VPUNPCKLQDQZ256rmb 0U, // VPUNPCKLQDQZ256rmbk 0U, // VPUNPCKLQDQZ256rmbkz 0U, // VPUNPCKLQDQZ256rmk 0U, // VPUNPCKLQDQZ256rmkz 0U, // VPUNPCKLQDQZ256rr 0U, // VPUNPCKLQDQZ256rrk 0U, // VPUNPCKLQDQZ256rrkz 0U, // VPUNPCKLQDQZrm 0U, // VPUNPCKLQDQZrmb 0U, // VPUNPCKLQDQZrmbk 0U, // VPUNPCKLQDQZrmbkz 0U, // VPUNPCKLQDQZrmk 0U, // VPUNPCKLQDQZrmkz 0U, // VPUNPCKLQDQZrr 0U, // VPUNPCKLQDQZrrk 0U, // VPUNPCKLQDQZrrkz 0U, // VPUNPCKLQDQrm 0U, // VPUNPCKLQDQrr 0U, // VPUNPCKLWDYrm 0U, // VPUNPCKLWDYrr 0U, // VPUNPCKLWDZ128rm 0U, // VPUNPCKLWDZ128rmk 0U, // VPUNPCKLWDZ128rmkz 0U, // VPUNPCKLWDZ128rr 0U, // VPUNPCKLWDZ128rrk 0U, // VPUNPCKLWDZ128rrkz 0U, // VPUNPCKLWDZ256rm 0U, // VPUNPCKLWDZ256rmk 0U, // VPUNPCKLWDZ256rmkz 0U, // VPUNPCKLWDZ256rr 0U, // VPUNPCKLWDZ256rrk 0U, // VPUNPCKLWDZ256rrkz 0U, // VPUNPCKLWDZrm 0U, // VPUNPCKLWDZrmk 0U, // VPUNPCKLWDZrmkz 0U, // VPUNPCKLWDZrr 0U, // VPUNPCKLWDZrrk 0U, // VPUNPCKLWDZrrkz 0U, // VPUNPCKLWDrm 0U, // VPUNPCKLWDrr 0U, // VPXORDZ128rm 0U, // VPXORDZ128rmb 0U, // VPXORDZ128rmbk 0U, // VPXORDZ128rmbkz 0U, // VPXORDZ128rmk 0U, // VPXORDZ128rmkz 0U, // VPXORDZ128rr 0U, // VPXORDZ128rrk 0U, // VPXORDZ128rrkz 0U, // VPXORDZ256rm 0U, // VPXORDZ256rmb 0U, // VPXORDZ256rmbk 0U, // VPXORDZ256rmbkz 0U, // VPXORDZ256rmk 0U, // VPXORDZ256rmkz 0U, // VPXORDZ256rr 0U, // VPXORDZ256rrk 0U, // VPXORDZ256rrkz 0U, // VPXORDZrm 0U, // VPXORDZrmb 0U, // VPXORDZrmbk 0U, // VPXORDZrmbkz 0U, // VPXORDZrmk 0U, // VPXORDZrmkz 0U, // VPXORDZrr 0U, // VPXORDZrrk 0U, // VPXORDZrrkz 0U, // VPXORQZ128rm 0U, // VPXORQZ128rmb 0U, // VPXORQZ128rmbk 0U, // VPXORQZ128rmbkz 0U, // VPXORQZ128rmk 0U, // VPXORQZ128rmkz 0U, // VPXORQZ128rr 0U, // VPXORQZ128rrk 0U, // VPXORQZ128rrkz 0U, // VPXORQZ256rm 0U, // VPXORQZ256rmb 0U, // VPXORQZ256rmbk 0U, // VPXORQZ256rmbkz 0U, // VPXORQZ256rmk 0U, // VPXORQZ256rmkz 0U, // VPXORQZ256rr 0U, // VPXORQZ256rrk 0U, // VPXORQZ256rrkz 0U, // VPXORQZrm 0U, // VPXORQZrmb 0U, // VPXORQZrmbk 0U, // VPXORQZrmbkz 0U, // VPXORQZrmk 0U, // VPXORQZrmkz 0U, // VPXORQZrr 0U, // VPXORQZrrk 0U, // VPXORQZrrkz 0U, // VPXORYrm 0U, // VPXORYrr 0U, // VPXORrm 0U, // VPXORrr 0U, // VRANGEPDZ128rmbi 0U, // VRANGEPDZ128rmbik 3U, // VRANGEPDZ128rmbikz 0U, // VRANGEPDZ128rmi 0U, // VRANGEPDZ128rmik 0U, // VRANGEPDZ128rmikz 0U, // VRANGEPDZ128rri 0U, // VRANGEPDZ128rrik 3U, // VRANGEPDZ128rrikz 0U, // VRANGEPDZ256rmbi 0U, // VRANGEPDZ256rmbik 3U, // VRANGEPDZ256rmbikz 0U, // VRANGEPDZ256rmi 0U, // VRANGEPDZ256rmik 0U, // VRANGEPDZ256rmikz 0U, // VRANGEPDZ256rri 0U, // VRANGEPDZ256rrik 3U, // VRANGEPDZ256rrikz 0U, // VRANGEPDZrmbi 0U, // VRANGEPDZrmbik 3U, // VRANGEPDZrmbikz 0U, // VRANGEPDZrmi 0U, // VRANGEPDZrmik 0U, // VRANGEPDZrmikz 0U, // VRANGEPDZrri 0U, // VRANGEPDZrrib 0U, // VRANGEPDZrribk 3U, // VRANGEPDZrribkz 0U, // VRANGEPDZrrik 3U, // VRANGEPDZrrikz 0U, // VRANGEPSZ128rmbi 0U, // VRANGEPSZ128rmbik 3U, // VRANGEPSZ128rmbikz 0U, // VRANGEPSZ128rmi 0U, // VRANGEPSZ128rmik 0U, // VRANGEPSZ128rmikz 0U, // VRANGEPSZ128rri 0U, // VRANGEPSZ128rrik 3U, // VRANGEPSZ128rrikz 0U, // VRANGEPSZ256rmbi 0U, // VRANGEPSZ256rmbik 3U, // VRANGEPSZ256rmbikz 0U, // VRANGEPSZ256rmi 0U, // VRANGEPSZ256rmik 0U, // VRANGEPSZ256rmikz 0U, // VRANGEPSZ256rri 0U, // VRANGEPSZ256rrik 3U, // VRANGEPSZ256rrikz 0U, // VRANGEPSZrmbi 0U, // VRANGEPSZrmbik 3U, // VRANGEPSZrmbikz 0U, // VRANGEPSZrmi 0U, // VRANGEPSZrmik 0U, // VRANGEPSZrmikz 0U, // VRANGEPSZrri 0U, // VRANGEPSZrrib 0U, // VRANGEPSZrribk 3U, // VRANGEPSZrribkz 0U, // VRANGEPSZrrik 3U, // VRANGEPSZrrikz 0U, // VRANGESDZrmi 0U, // VRANGESDZrmik 3U, // VRANGESDZrmikz 0U, // VRANGESDZrri 0U, // VRANGESDZrrib 0U, // VRANGESDZrribk 3U, // VRANGESDZrribkz 0U, // VRANGESDZrrik 3U, // VRANGESDZrrikz 0U, // VRANGESSZrmi 0U, // VRANGESSZrmik 3U, // VRANGESSZrmikz 0U, // VRANGESSZrri 0U, // VRANGESSZrrib 0U, // VRANGESSZrribk 3U, // VRANGESSZrribkz 0U, // VRANGESSZrrik 3U, // VRANGESSZrrikz 0U, // VRCP14PDZ128m 0U, // VRCP14PDZ128mb 0U, // VRCP14PDZ128mbk 0U, // VRCP14PDZ128mbkz 0U, // VRCP14PDZ128mk 0U, // VRCP14PDZ128mkz 0U, // VRCP14PDZ128r 0U, // VRCP14PDZ128rk 0U, // VRCP14PDZ128rkz 0U, // VRCP14PDZ256m 0U, // VRCP14PDZ256mb 0U, // VRCP14PDZ256mbk 0U, // VRCP14PDZ256mbkz 0U, // VRCP14PDZ256mk 0U, // VRCP14PDZ256mkz 0U, // VRCP14PDZ256r 0U, // VRCP14PDZ256rk 0U, // VRCP14PDZ256rkz 0U, // VRCP14PDZm 0U, // VRCP14PDZmb 0U, // VRCP14PDZmbk 0U, // VRCP14PDZmbkz 0U, // VRCP14PDZmk 0U, // VRCP14PDZmkz 0U, // VRCP14PDZr 0U, // VRCP14PDZrk 0U, // VRCP14PDZrkz 0U, // VRCP14PSZ128m 0U, // VRCP14PSZ128mb 0U, // VRCP14PSZ128mbk 0U, // VRCP14PSZ128mbkz 0U, // VRCP14PSZ128mk 0U, // VRCP14PSZ128mkz 0U, // VRCP14PSZ128r 0U, // VRCP14PSZ128rk 0U, // VRCP14PSZ128rkz 0U, // VRCP14PSZ256m 0U, // VRCP14PSZ256mb 0U, // VRCP14PSZ256mbk 0U, // VRCP14PSZ256mbkz 0U, // VRCP14PSZ256mk 0U, // VRCP14PSZ256mkz 0U, // VRCP14PSZ256r 0U, // VRCP14PSZ256rk 0U, // VRCP14PSZ256rkz 0U, // VRCP14PSZm 0U, // VRCP14PSZmb 0U, // VRCP14PSZmbk 0U, // VRCP14PSZmbkz 0U, // VRCP14PSZmk 0U, // VRCP14PSZmkz 0U, // VRCP14PSZr 0U, // VRCP14PSZrk 0U, // VRCP14PSZrkz 0U, // VRCP14SDZrm 0U, // VRCP14SDZrmk 0U, // VRCP14SDZrmkz 0U, // VRCP14SDZrr 0U, // VRCP14SDZrrk 0U, // VRCP14SDZrrkz 0U, // VRCP14SSZrm 0U, // VRCP14SSZrmk 0U, // VRCP14SSZrmkz 0U, // VRCP14SSZrr 0U, // VRCP14SSZrrk 0U, // VRCP14SSZrrkz 0U, // VRCP28PDZm 0U, // VRCP28PDZmb 0U, // VRCP28PDZmbk 0U, // VRCP28PDZmbkz 0U, // VRCP28PDZmk 0U, // VRCP28PDZmkz 0U, // VRCP28PDZr 0U, // VRCP28PDZrb 0U, // VRCP28PDZrbk 0U, // VRCP28PDZrbkz 0U, // VRCP28PDZrk 0U, // VRCP28PDZrkz 0U, // VRCP28PSZm 0U, // VRCP28PSZmb 0U, // VRCP28PSZmbk 0U, // VRCP28PSZmbkz 0U, // VRCP28PSZmk 0U, // VRCP28PSZmkz 0U, // VRCP28PSZr 0U, // VRCP28PSZrb 0U, // VRCP28PSZrbk 0U, // VRCP28PSZrbkz 0U, // VRCP28PSZrk 0U, // VRCP28PSZrkz 0U, // VRCP28SDZm 0U, // VRCP28SDZmk 0U, // VRCP28SDZmkz 0U, // VRCP28SDZr 0U, // VRCP28SDZrb 0U, // VRCP28SDZrbk 0U, // VRCP28SDZrbkz 0U, // VRCP28SDZrk 0U, // VRCP28SDZrkz 0U, // VRCP28SSZm 0U, // VRCP28SSZmk 0U, // VRCP28SSZmkz 0U, // VRCP28SSZr 0U, // VRCP28SSZrb 0U, // VRCP28SSZrbk 0U, // VRCP28SSZrbkz 0U, // VRCP28SSZrk 0U, // VRCP28SSZrkz 0U, // VRCPPSYm 0U, // VRCPPSYr 0U, // VRCPPSm 0U, // VRCPPSr 0U, // VRCPSSm 0U, // VRCPSSm_Int 0U, // VRCPSSr 0U, // VRCPSSr_Int 0U, // VREDUCEPDZ128rmbi 0U, // VREDUCEPDZ128rmbik 0U, // VREDUCEPDZ128rmbikz 0U, // VREDUCEPDZ128rmi 0U, // VREDUCEPDZ128rmik 0U, // VREDUCEPDZ128rmikz 0U, // VREDUCEPDZ128rri 0U, // VREDUCEPDZ128rrik 0U, // VREDUCEPDZ128rrikz 0U, // VREDUCEPDZ256rmbi 0U, // VREDUCEPDZ256rmbik 0U, // VREDUCEPDZ256rmbikz 0U, // VREDUCEPDZ256rmi 0U, // VREDUCEPDZ256rmik 0U, // VREDUCEPDZ256rmikz 0U, // VREDUCEPDZ256rri 0U, // VREDUCEPDZ256rrik 0U, // VREDUCEPDZ256rrikz 0U, // VREDUCEPDZrmbi 0U, // VREDUCEPDZrmbik 0U, // VREDUCEPDZrmbikz 0U, // VREDUCEPDZrmi 0U, // VREDUCEPDZrmik 0U, // VREDUCEPDZrmikz 0U, // VREDUCEPDZrri 0U, // VREDUCEPDZrrib 0U, // VREDUCEPDZrribk 0U, // VREDUCEPDZrribkz 0U, // VREDUCEPDZrrik 0U, // VREDUCEPDZrrikz 0U, // VREDUCEPSZ128rmbi 0U, // VREDUCEPSZ128rmbik 0U, // VREDUCEPSZ128rmbikz 0U, // VREDUCEPSZ128rmi 0U, // VREDUCEPSZ128rmik 0U, // VREDUCEPSZ128rmikz 0U, // VREDUCEPSZ128rri 0U, // VREDUCEPSZ128rrik 0U, // VREDUCEPSZ128rrikz 0U, // VREDUCEPSZ256rmbi 0U, // VREDUCEPSZ256rmbik 0U, // VREDUCEPSZ256rmbikz 0U, // VREDUCEPSZ256rmi 0U, // VREDUCEPSZ256rmik 0U, // VREDUCEPSZ256rmikz 0U, // VREDUCEPSZ256rri 0U, // VREDUCEPSZ256rrik 0U, // VREDUCEPSZ256rrikz 0U, // VREDUCEPSZrmbi 0U, // VREDUCEPSZrmbik 0U, // VREDUCEPSZrmbikz 0U, // VREDUCEPSZrmi 0U, // VREDUCEPSZrmik 0U, // VREDUCEPSZrmikz 0U, // VREDUCEPSZrri 0U, // VREDUCEPSZrrib 0U, // VREDUCEPSZrribk 0U, // VREDUCEPSZrribkz 0U, // VREDUCEPSZrrik 0U, // VREDUCEPSZrrikz 0U, // VREDUCESDZrmi 0U, // VREDUCESDZrmik 3U, // VREDUCESDZrmikz 0U, // VREDUCESDZrri 0U, // VREDUCESDZrrib 0U, // VREDUCESDZrribk 3U, // VREDUCESDZrribkz 0U, // VREDUCESDZrrik 3U, // VREDUCESDZrrikz 0U, // VREDUCESSZrmi 0U, // VREDUCESSZrmik 3U, // VREDUCESSZrmikz 0U, // VREDUCESSZrri 0U, // VREDUCESSZrrib 0U, // VREDUCESSZrribk 3U, // VREDUCESSZrribkz 0U, // VREDUCESSZrrik 3U, // VREDUCESSZrrikz 0U, // VRNDSCALEPDZ128rmbi 0U, // VRNDSCALEPDZ128rmbik 0U, // VRNDSCALEPDZ128rmbikz 0U, // VRNDSCALEPDZ128rmi 0U, // VRNDSCALEPDZ128rmik 0U, // VRNDSCALEPDZ128rmikz 0U, // VRNDSCALEPDZ128rri 0U, // VRNDSCALEPDZ128rrik 0U, // VRNDSCALEPDZ128rrikz 0U, // VRNDSCALEPDZ256rmbi 0U, // VRNDSCALEPDZ256rmbik 0U, // VRNDSCALEPDZ256rmbikz 0U, // VRNDSCALEPDZ256rmi 0U, // VRNDSCALEPDZ256rmik 0U, // VRNDSCALEPDZ256rmikz 0U, // VRNDSCALEPDZ256rri 0U, // VRNDSCALEPDZ256rrik 0U, // VRNDSCALEPDZ256rrikz 0U, // VRNDSCALEPDZrmbi 0U, // VRNDSCALEPDZrmbik 0U, // VRNDSCALEPDZrmbikz 0U, // VRNDSCALEPDZrmi 0U, // VRNDSCALEPDZrmik 0U, // VRNDSCALEPDZrmikz 0U, // VRNDSCALEPDZrri 0U, // VRNDSCALEPDZrrib 0U, // VRNDSCALEPDZrribk 0U, // VRNDSCALEPDZrribkz 0U, // VRNDSCALEPDZrrik 0U, // VRNDSCALEPDZrrikz 0U, // VRNDSCALEPSZ128rmbi 0U, // VRNDSCALEPSZ128rmbik 0U, // VRNDSCALEPSZ128rmbikz 0U, // VRNDSCALEPSZ128rmi 0U, // VRNDSCALEPSZ128rmik 0U, // VRNDSCALEPSZ128rmikz 0U, // VRNDSCALEPSZ128rri 0U, // VRNDSCALEPSZ128rrik 0U, // VRNDSCALEPSZ128rrikz 0U, // VRNDSCALEPSZ256rmbi 0U, // VRNDSCALEPSZ256rmbik 0U, // VRNDSCALEPSZ256rmbikz 0U, // VRNDSCALEPSZ256rmi 0U, // VRNDSCALEPSZ256rmik 0U, // VRNDSCALEPSZ256rmikz 0U, // VRNDSCALEPSZ256rri 0U, // VRNDSCALEPSZ256rrik 0U, // VRNDSCALEPSZ256rrikz 0U, // VRNDSCALEPSZrmbi 0U, // VRNDSCALEPSZrmbik 0U, // VRNDSCALEPSZrmbikz 0U, // VRNDSCALEPSZrmi 0U, // VRNDSCALEPSZrmik 0U, // VRNDSCALEPSZrmikz 0U, // VRNDSCALEPSZrri 0U, // VRNDSCALEPSZrrib 0U, // VRNDSCALEPSZrribk 0U, // VRNDSCALEPSZrribkz 0U, // VRNDSCALEPSZrrik 0U, // VRNDSCALEPSZrrikz 0U, // VRNDSCALESDZm 0U, // VRNDSCALESDZm_Int 0U, // VRNDSCALESDZm_Intk 3U, // VRNDSCALESDZm_Intkz 0U, // VRNDSCALESDZr 0U, // VRNDSCALESDZr_Int 0U, // VRNDSCALESDZr_Intk 3U, // VRNDSCALESDZr_Intkz 0U, // VRNDSCALESDZrb_Int 0U, // VRNDSCALESDZrb_Intk 3U, // VRNDSCALESDZrb_Intkz 0U, // VRNDSCALESSZm 0U, // VRNDSCALESSZm_Int 0U, // VRNDSCALESSZm_Intk 3U, // VRNDSCALESSZm_Intkz 0U, // VRNDSCALESSZr 0U, // VRNDSCALESSZr_Int 0U, // VRNDSCALESSZr_Intk 3U, // VRNDSCALESSZr_Intkz 0U, // VRNDSCALESSZrb_Int 0U, // VRNDSCALESSZrb_Intk 3U, // VRNDSCALESSZrb_Intkz 0U, // VROUNDPDYm 0U, // VROUNDPDYr 0U, // VROUNDPDm 0U, // VROUNDPDr 0U, // VROUNDPSYm 0U, // VROUNDPSYr 0U, // VROUNDPSm 0U, // VROUNDPSr 0U, // VROUNDSDm 0U, // VROUNDSDm_Int 0U, // VROUNDSDr 0U, // VROUNDSDr_Int 0U, // VROUNDSSm 0U, // VROUNDSSm_Int 0U, // VROUNDSSr 0U, // VROUNDSSr_Int 0U, // VRSQRT14PDZ128m 0U, // VRSQRT14PDZ128mb 0U, // VRSQRT14PDZ128mbk 0U, // VRSQRT14PDZ128mbkz 0U, // VRSQRT14PDZ128mk 0U, // VRSQRT14PDZ128mkz 0U, // VRSQRT14PDZ128r 0U, // VRSQRT14PDZ128rk 0U, // VRSQRT14PDZ128rkz 0U, // VRSQRT14PDZ256m 0U, // VRSQRT14PDZ256mb 0U, // VRSQRT14PDZ256mbk 0U, // VRSQRT14PDZ256mbkz 0U, // VRSQRT14PDZ256mk 0U, // VRSQRT14PDZ256mkz 0U, // VRSQRT14PDZ256r 0U, // VRSQRT14PDZ256rk 0U, // VRSQRT14PDZ256rkz 0U, // VRSQRT14PDZm 0U, // VRSQRT14PDZmb 0U, // VRSQRT14PDZmbk 0U, // VRSQRT14PDZmbkz 0U, // VRSQRT14PDZmk 0U, // VRSQRT14PDZmkz 0U, // VRSQRT14PDZr 0U, // VRSQRT14PDZrk 0U, // VRSQRT14PDZrkz 0U, // VRSQRT14PSZ128m 0U, // VRSQRT14PSZ128mb 0U, // VRSQRT14PSZ128mbk 0U, // VRSQRT14PSZ128mbkz 0U, // VRSQRT14PSZ128mk 0U, // VRSQRT14PSZ128mkz 0U, // VRSQRT14PSZ128r 0U, // VRSQRT14PSZ128rk 0U, // VRSQRT14PSZ128rkz 0U, // VRSQRT14PSZ256m 0U, // VRSQRT14PSZ256mb 0U, // VRSQRT14PSZ256mbk 0U, // VRSQRT14PSZ256mbkz 0U, // VRSQRT14PSZ256mk 0U, // VRSQRT14PSZ256mkz 0U, // VRSQRT14PSZ256r 0U, // VRSQRT14PSZ256rk 0U, // VRSQRT14PSZ256rkz 0U, // VRSQRT14PSZm 0U, // VRSQRT14PSZmb 0U, // VRSQRT14PSZmbk 0U, // VRSQRT14PSZmbkz 0U, // VRSQRT14PSZmk 0U, // VRSQRT14PSZmkz 0U, // VRSQRT14PSZr 0U, // VRSQRT14PSZrk 0U, // VRSQRT14PSZrkz 0U, // VRSQRT14SDZrm 0U, // VRSQRT14SDZrmk 0U, // VRSQRT14SDZrmkz 0U, // VRSQRT14SDZrr 0U, // VRSQRT14SDZrrk 0U, // VRSQRT14SDZrrkz 0U, // VRSQRT14SSZrm 0U, // VRSQRT14SSZrmk 0U, // VRSQRT14SSZrmkz 0U, // VRSQRT14SSZrr 0U, // VRSQRT14SSZrrk 0U, // VRSQRT14SSZrrkz 0U, // VRSQRT28PDZm 0U, // VRSQRT28PDZmb 0U, // VRSQRT28PDZmbk 0U, // VRSQRT28PDZmbkz 0U, // VRSQRT28PDZmk 0U, // VRSQRT28PDZmkz 0U, // VRSQRT28PDZr 0U, // VRSQRT28PDZrb 0U, // VRSQRT28PDZrbk 0U, // VRSQRT28PDZrbkz 0U, // VRSQRT28PDZrk 0U, // VRSQRT28PDZrkz 0U, // VRSQRT28PSZm 0U, // VRSQRT28PSZmb 0U, // VRSQRT28PSZmbk 0U, // VRSQRT28PSZmbkz 0U, // VRSQRT28PSZmk 0U, // VRSQRT28PSZmkz 0U, // VRSQRT28PSZr 0U, // VRSQRT28PSZrb 0U, // VRSQRT28PSZrbk 0U, // VRSQRT28PSZrbkz 0U, // VRSQRT28PSZrk 0U, // VRSQRT28PSZrkz 0U, // VRSQRT28SDZm 0U, // VRSQRT28SDZmk 0U, // VRSQRT28SDZmkz 0U, // VRSQRT28SDZr 0U, // VRSQRT28SDZrb 0U, // VRSQRT28SDZrbk 0U, // VRSQRT28SDZrbkz 0U, // VRSQRT28SDZrk 0U, // VRSQRT28SDZrkz 0U, // VRSQRT28SSZm 0U, // VRSQRT28SSZmk 0U, // VRSQRT28SSZmkz 0U, // VRSQRT28SSZr 0U, // VRSQRT28SSZrb 0U, // VRSQRT28SSZrbk 0U, // VRSQRT28SSZrbkz 0U, // VRSQRT28SSZrk 0U, // VRSQRT28SSZrkz 0U, // VRSQRTPSYm 0U, // VRSQRTPSYr 0U, // VRSQRTPSm 0U, // VRSQRTPSr 0U, // VRSQRTSSm 0U, // VRSQRTSSm_Int 0U, // VRSQRTSSr 0U, // VRSQRTSSr_Int 0U, // VSCALEFPDZ128rm 0U, // VSCALEFPDZ128rmb 0U, // VSCALEFPDZ128rmbk 0U, // VSCALEFPDZ128rmbkz 0U, // VSCALEFPDZ128rmk 0U, // VSCALEFPDZ128rmkz 0U, // VSCALEFPDZ128rr 0U, // VSCALEFPDZ128rrk 0U, // VSCALEFPDZ128rrkz 0U, // VSCALEFPDZ256rm 0U, // VSCALEFPDZ256rmb 0U, // VSCALEFPDZ256rmbk 0U, // VSCALEFPDZ256rmbkz 0U, // VSCALEFPDZ256rmk 0U, // VSCALEFPDZ256rmkz 0U, // VSCALEFPDZ256rr 0U, // VSCALEFPDZ256rrk 0U, // VSCALEFPDZ256rrkz 0U, // VSCALEFPDZrm 0U, // VSCALEFPDZrmb 0U, // VSCALEFPDZrmbk 0U, // VSCALEFPDZrmbkz 0U, // VSCALEFPDZrmk 0U, // VSCALEFPDZrmkz 0U, // VSCALEFPDZrr 0U, // VSCALEFPDZrrb 0U, // VSCALEFPDZrrbk 0U, // VSCALEFPDZrrbkz 0U, // VSCALEFPDZrrk 0U, // VSCALEFPDZrrkz 0U, // VSCALEFPSZ128rm 0U, // VSCALEFPSZ128rmb 0U, // VSCALEFPSZ128rmbk 0U, // VSCALEFPSZ128rmbkz 0U, // VSCALEFPSZ128rmk 0U, // VSCALEFPSZ128rmkz 0U, // VSCALEFPSZ128rr 0U, // VSCALEFPSZ128rrk 0U, // VSCALEFPSZ128rrkz 0U, // VSCALEFPSZ256rm 0U, // VSCALEFPSZ256rmb 0U, // VSCALEFPSZ256rmbk 0U, // VSCALEFPSZ256rmbkz 0U, // VSCALEFPSZ256rmk 0U, // VSCALEFPSZ256rmkz 0U, // VSCALEFPSZ256rr 0U, // VSCALEFPSZ256rrk 0U, // VSCALEFPSZ256rrkz 0U, // VSCALEFPSZrm 0U, // VSCALEFPSZrmb 0U, // VSCALEFPSZrmbk 0U, // VSCALEFPSZrmbkz 0U, // VSCALEFPSZrmk 0U, // VSCALEFPSZrmkz 0U, // VSCALEFPSZrr 0U, // VSCALEFPSZrrb 0U, // VSCALEFPSZrrbk 0U, // VSCALEFPSZrrbkz 0U, // VSCALEFPSZrrk 0U, // VSCALEFPSZrrkz 0U, // VSCALEFSDZrm 0U, // VSCALEFSDZrmk 0U, // VSCALEFSDZrmkz 0U, // VSCALEFSDZrr 0U, // VSCALEFSDZrrb_Int 0U, // VSCALEFSDZrrb_Intk 0U, // VSCALEFSDZrrb_Intkz 0U, // VSCALEFSDZrrk 0U, // VSCALEFSDZrrkz 0U, // VSCALEFSSZrm 0U, // VSCALEFSSZrmk 0U, // VSCALEFSSZrmkz 0U, // VSCALEFSSZrr 0U, // VSCALEFSSZrrb_Int 0U, // VSCALEFSSZrrb_Intk 0U, // VSCALEFSSZrrb_Intkz 0U, // VSCALEFSSZrrk 0U, // VSCALEFSSZrrkz 0U, // VSCATTERDPDZ128mr 0U, // VSCATTERDPDZ256mr 0U, // VSCATTERDPDZmr 0U, // VSCATTERDPSZ128mr 0U, // VSCATTERDPSZ256mr 0U, // VSCATTERDPSZmr 0U, // VSCATTERPF0DPDm 0U, // VSCATTERPF0DPSm 0U, // VSCATTERPF0QPDm 0U, // VSCATTERPF0QPSm 0U, // VSCATTERPF1DPDm 0U, // VSCATTERPF1DPSm 0U, // VSCATTERPF1QPDm 0U, // VSCATTERPF1QPSm 0U, // VSCATTERQPDZ128mr 0U, // VSCATTERQPDZ256mr 0U, // VSCATTERQPDZmr 0U, // VSCATTERQPSZ128mr 0U, // VSCATTERQPSZ256mr 0U, // VSCATTERQPSZmr 0U, // VSHUFF32X4Z256rmbi 0U, // VSHUFF32X4Z256rmbik 3U, // VSHUFF32X4Z256rmbikz 0U, // VSHUFF32X4Z256rmi 0U, // VSHUFF32X4Z256rmik 0U, // VSHUFF32X4Z256rmikz 0U, // VSHUFF32X4Z256rri 0U, // VSHUFF32X4Z256rrik 3U, // VSHUFF32X4Z256rrikz 0U, // VSHUFF32X4Zrmbi 0U, // VSHUFF32X4Zrmbik 3U, // VSHUFF32X4Zrmbikz 0U, // VSHUFF32X4Zrmi 0U, // VSHUFF32X4Zrmik 0U, // VSHUFF32X4Zrmikz 0U, // VSHUFF32X4Zrri 0U, // VSHUFF32X4Zrrik 3U, // VSHUFF32X4Zrrikz 0U, // VSHUFF64X2Z256rmbi 0U, // VSHUFF64X2Z256rmbik 3U, // VSHUFF64X2Z256rmbikz 0U, // VSHUFF64X2Z256rmi 0U, // VSHUFF64X2Z256rmik 0U, // VSHUFF64X2Z256rmikz 0U, // VSHUFF64X2Z256rri 0U, // VSHUFF64X2Z256rrik 3U, // VSHUFF64X2Z256rrikz 0U, // VSHUFF64X2Zrmbi 0U, // VSHUFF64X2Zrmbik 3U, // VSHUFF64X2Zrmbikz 0U, // VSHUFF64X2Zrmi 0U, // VSHUFF64X2Zrmik 0U, // VSHUFF64X2Zrmikz 0U, // VSHUFF64X2Zrri 0U, // VSHUFF64X2Zrrik 3U, // VSHUFF64X2Zrrikz 0U, // VSHUFI32X4Z256rmbi 0U, // VSHUFI32X4Z256rmbik 3U, // VSHUFI32X4Z256rmbikz 0U, // VSHUFI32X4Z256rmi 0U, // VSHUFI32X4Z256rmik 0U, // VSHUFI32X4Z256rmikz 0U, // VSHUFI32X4Z256rri 0U, // VSHUFI32X4Z256rrik 3U, // VSHUFI32X4Z256rrikz 0U, // VSHUFI32X4Zrmbi 0U, // VSHUFI32X4Zrmbik 3U, // VSHUFI32X4Zrmbikz 0U, // VSHUFI32X4Zrmi 0U, // VSHUFI32X4Zrmik 0U, // VSHUFI32X4Zrmikz 0U, // VSHUFI32X4Zrri 0U, // VSHUFI32X4Zrrik 3U, // VSHUFI32X4Zrrikz 0U, // VSHUFI64X2Z256rmbi 0U, // VSHUFI64X2Z256rmbik 3U, // VSHUFI64X2Z256rmbikz 0U, // VSHUFI64X2Z256rmi 0U, // VSHUFI64X2Z256rmik 0U, // VSHUFI64X2Z256rmikz 0U, // VSHUFI64X2Z256rri 0U, // VSHUFI64X2Z256rrik 3U, // VSHUFI64X2Z256rrikz 0U, // VSHUFI64X2Zrmbi 0U, // VSHUFI64X2Zrmbik 3U, // VSHUFI64X2Zrmbikz 0U, // VSHUFI64X2Zrmi 0U, // VSHUFI64X2Zrmik 0U, // VSHUFI64X2Zrmikz 0U, // VSHUFI64X2Zrri 0U, // VSHUFI64X2Zrrik 3U, // VSHUFI64X2Zrrikz 0U, // VSHUFPDYrmi 0U, // VSHUFPDYrri 0U, // VSHUFPDZ128rmbi 0U, // VSHUFPDZ128rmbik 3U, // VSHUFPDZ128rmbikz 0U, // VSHUFPDZ128rmi 0U, // VSHUFPDZ128rmik 0U, // VSHUFPDZ128rmikz 0U, // VSHUFPDZ128rri 0U, // VSHUFPDZ128rrik 3U, // VSHUFPDZ128rrikz 0U, // VSHUFPDZ256rmbi 0U, // VSHUFPDZ256rmbik 3U, // VSHUFPDZ256rmbikz 0U, // VSHUFPDZ256rmi 0U, // VSHUFPDZ256rmik 0U, // VSHUFPDZ256rmikz 0U, // VSHUFPDZ256rri 0U, // VSHUFPDZ256rrik 3U, // VSHUFPDZ256rrikz 0U, // VSHUFPDZrmbi 0U, // VSHUFPDZrmbik 3U, // VSHUFPDZrmbikz 0U, // VSHUFPDZrmi 0U, // VSHUFPDZrmik 0U, // VSHUFPDZrmikz 0U, // VSHUFPDZrri 0U, // VSHUFPDZrrik 3U, // VSHUFPDZrrikz 0U, // VSHUFPDrmi 0U, // VSHUFPDrri 0U, // VSHUFPSYrmi 0U, // VSHUFPSYrri 0U, // VSHUFPSZ128rmbi 0U, // VSHUFPSZ128rmbik 3U, // VSHUFPSZ128rmbikz 0U, // VSHUFPSZ128rmi 0U, // VSHUFPSZ128rmik 0U, // VSHUFPSZ128rmikz 0U, // VSHUFPSZ128rri 0U, // VSHUFPSZ128rrik 3U, // VSHUFPSZ128rrikz 0U, // VSHUFPSZ256rmbi 0U, // VSHUFPSZ256rmbik 3U, // VSHUFPSZ256rmbikz 0U, // VSHUFPSZ256rmi 0U, // VSHUFPSZ256rmik 0U, // VSHUFPSZ256rmikz 0U, // VSHUFPSZ256rri 0U, // VSHUFPSZ256rrik 3U, // VSHUFPSZ256rrikz 0U, // VSHUFPSZrmbi 0U, // VSHUFPSZrmbik 3U, // VSHUFPSZrmbikz 0U, // VSHUFPSZrmi 0U, // VSHUFPSZrmik 0U, // VSHUFPSZrmikz 0U, // VSHUFPSZrri 0U, // VSHUFPSZrrik 3U, // VSHUFPSZrrikz 0U, // VSHUFPSrmi 0U, // VSHUFPSrri 0U, // VSQRTPDYm 0U, // VSQRTPDYr 0U, // VSQRTPDZ128m 0U, // VSQRTPDZ128mb 0U, // VSQRTPDZ128mbk 0U, // VSQRTPDZ128mbkz 0U, // VSQRTPDZ128mk 0U, // VSQRTPDZ128mkz 0U, // VSQRTPDZ128r 0U, // VSQRTPDZ128rk 0U, // VSQRTPDZ128rkz 0U, // VSQRTPDZ256m 0U, // VSQRTPDZ256mb 0U, // VSQRTPDZ256mbk 0U, // VSQRTPDZ256mbkz 0U, // VSQRTPDZ256mk 0U, // VSQRTPDZ256mkz 0U, // VSQRTPDZ256r 0U, // VSQRTPDZ256rk 0U, // VSQRTPDZ256rkz 0U, // VSQRTPDZm 0U, // VSQRTPDZmb 0U, // VSQRTPDZmbk 0U, // VSQRTPDZmbkz 0U, // VSQRTPDZmk 0U, // VSQRTPDZmkz 0U, // VSQRTPDZr 0U, // VSQRTPDZrb 0U, // VSQRTPDZrbk 0U, // VSQRTPDZrbkz 0U, // VSQRTPDZrk 0U, // VSQRTPDZrkz 0U, // VSQRTPDm 0U, // VSQRTPDr 0U, // VSQRTPSYm 0U, // VSQRTPSYr 0U, // VSQRTPSZ128m 0U, // VSQRTPSZ128mb 0U, // VSQRTPSZ128mbk 0U, // VSQRTPSZ128mbkz 0U, // VSQRTPSZ128mk 0U, // VSQRTPSZ128mkz 0U, // VSQRTPSZ128r 0U, // VSQRTPSZ128rk 0U, // VSQRTPSZ128rkz 0U, // VSQRTPSZ256m 0U, // VSQRTPSZ256mb 0U, // VSQRTPSZ256mbk 0U, // VSQRTPSZ256mbkz 0U, // VSQRTPSZ256mk 0U, // VSQRTPSZ256mkz 0U, // VSQRTPSZ256r 0U, // VSQRTPSZ256rk 0U, // VSQRTPSZ256rkz 0U, // VSQRTPSZm 0U, // VSQRTPSZmb 0U, // VSQRTPSZmbk 0U, // VSQRTPSZmbkz 0U, // VSQRTPSZmk 0U, // VSQRTPSZmkz 0U, // VSQRTPSZr 0U, // VSQRTPSZrb 0U, // VSQRTPSZrbk 0U, // VSQRTPSZrbkz 0U, // VSQRTPSZrk 0U, // VSQRTPSZrkz 0U, // VSQRTPSm 0U, // VSQRTPSr 0U, // VSQRTSDZm 0U, // VSQRTSDZm_Int 0U, // VSQRTSDZm_Intk 0U, // VSQRTSDZm_Intkz 0U, // VSQRTSDZr 0U, // VSQRTSDZr_Int 0U, // VSQRTSDZr_Intk 0U, // VSQRTSDZr_Intkz 0U, // VSQRTSDZrb_Int 0U, // VSQRTSDZrb_Intk 0U, // VSQRTSDZrb_Intkz 0U, // VSQRTSDm 0U, // VSQRTSDm_Int 0U, // VSQRTSDr 0U, // VSQRTSDr_Int 0U, // VSQRTSSZm 0U, // VSQRTSSZm_Int 0U, // VSQRTSSZm_Intk 0U, // VSQRTSSZm_Intkz 0U, // VSQRTSSZr 0U, // VSQRTSSZr_Int 0U, // VSQRTSSZr_Intk 0U, // VSQRTSSZr_Intkz 0U, // VSQRTSSZrb_Int 0U, // VSQRTSSZrb_Intk 0U, // VSQRTSSZrb_Intkz 0U, // VSQRTSSm 0U, // VSQRTSSm_Int 0U, // VSQRTSSr 0U, // VSQRTSSr_Int 0U, // VSTMXCSR 0U, // VSUBPDYrm 0U, // VSUBPDYrr 0U, // VSUBPDZ128rm 0U, // VSUBPDZ128rmb 0U, // VSUBPDZ128rmbk 0U, // VSUBPDZ128rmbkz 0U, // VSUBPDZ128rmk 0U, // VSUBPDZ128rmkz 0U, // VSUBPDZ128rr 0U, // VSUBPDZ128rrk 0U, // VSUBPDZ128rrkz 0U, // VSUBPDZ256rm 0U, // VSUBPDZ256rmb 0U, // VSUBPDZ256rmbk 0U, // VSUBPDZ256rmbkz 0U, // VSUBPDZ256rmk 0U, // VSUBPDZ256rmkz 0U, // VSUBPDZ256rr 0U, // VSUBPDZ256rrk 0U, // VSUBPDZ256rrkz 0U, // VSUBPDZrm 0U, // VSUBPDZrmb 0U, // VSUBPDZrmbk 0U, // VSUBPDZrmbkz 0U, // VSUBPDZrmk 0U, // VSUBPDZrmkz 0U, // VSUBPDZrr 0U, // VSUBPDZrrb 0U, // VSUBPDZrrbk 0U, // VSUBPDZrrbkz 0U, // VSUBPDZrrk 0U, // VSUBPDZrrkz 0U, // VSUBPDrm 0U, // VSUBPDrr 0U, // VSUBPSYrm 0U, // VSUBPSYrr 0U, // VSUBPSZ128rm 0U, // VSUBPSZ128rmb 0U, // VSUBPSZ128rmbk 0U, // VSUBPSZ128rmbkz 0U, // VSUBPSZ128rmk 0U, // VSUBPSZ128rmkz 0U, // VSUBPSZ128rr 0U, // VSUBPSZ128rrk 0U, // VSUBPSZ128rrkz 0U, // VSUBPSZ256rm 0U, // VSUBPSZ256rmb 0U, // VSUBPSZ256rmbk 0U, // VSUBPSZ256rmbkz 0U, // VSUBPSZ256rmk 0U, // VSUBPSZ256rmkz 0U, // VSUBPSZ256rr 0U, // VSUBPSZ256rrk 0U, // VSUBPSZ256rrkz 0U, // VSUBPSZrm 0U, // VSUBPSZrmb 0U, // VSUBPSZrmbk 0U, // VSUBPSZrmbkz 0U, // VSUBPSZrmk 0U, // VSUBPSZrmkz 0U, // VSUBPSZrr 0U, // VSUBPSZrrb 0U, // VSUBPSZrrbk 0U, // VSUBPSZrrbkz 0U, // VSUBPSZrrk 0U, // VSUBPSZrrkz 0U, // VSUBPSrm 0U, // VSUBPSrr 0U, // VSUBSDZrm 0U, // VSUBSDZrm_Int 0U, // VSUBSDZrm_Intk 0U, // VSUBSDZrm_Intkz 0U, // VSUBSDZrr 0U, // VSUBSDZrr_Int 0U, // VSUBSDZrr_Intk 0U, // VSUBSDZrr_Intkz 0U, // VSUBSDZrrb_Int 0U, // VSUBSDZrrb_Intk 0U, // VSUBSDZrrb_Intkz 0U, // VSUBSDrm 0U, // VSUBSDrm_Int 0U, // VSUBSDrr 0U, // VSUBSDrr_Int 0U, // VSUBSSZrm 0U, // VSUBSSZrm_Int 0U, // VSUBSSZrm_Intk 0U, // VSUBSSZrm_Intkz 0U, // VSUBSSZrr 0U, // VSUBSSZrr_Int 0U, // VSUBSSZrr_Intk 0U, // VSUBSSZrr_Intkz 0U, // VSUBSSZrrb_Int 0U, // VSUBSSZrrb_Intk 0U, // VSUBSSZrrb_Intkz 0U, // VSUBSSrm 0U, // VSUBSSrm_Int 0U, // VSUBSSrr 0U, // VSUBSSrr_Int 0U, // VTESTPDYrm 0U, // VTESTPDYrr 0U, // VTESTPDrm 0U, // VTESTPDrr 0U, // VTESTPSYrm 0U, // VTESTPSYrr 0U, // VTESTPSrm 0U, // VTESTPSrr 0U, // VUCOMISDZrm 0U, // VUCOMISDZrm_Int 0U, // VUCOMISDZrr 0U, // VUCOMISDZrr_Int 0U, // VUCOMISDZrrb 0U, // VUCOMISDrm 0U, // VUCOMISDrm_Int 0U, // VUCOMISDrr 0U, // VUCOMISDrr_Int 0U, // VUCOMISSZrm 0U, // VUCOMISSZrm_Int 0U, // VUCOMISSZrr 0U, // VUCOMISSZrr_Int 0U, // VUCOMISSZrrb 0U, // VUCOMISSrm 0U, // VUCOMISSrm_Int 0U, // VUCOMISSrr 0U, // VUCOMISSrr_Int 0U, // VUNPCKHPDYrm 0U, // VUNPCKHPDYrr 0U, // VUNPCKHPDZ128rm 0U, // VUNPCKHPDZ128rmb 0U, // VUNPCKHPDZ128rmbk 0U, // VUNPCKHPDZ128rmbkz 0U, // VUNPCKHPDZ128rmk 0U, // VUNPCKHPDZ128rmkz 0U, // VUNPCKHPDZ128rr 0U, // VUNPCKHPDZ128rrk 0U, // VUNPCKHPDZ128rrkz 0U, // VUNPCKHPDZ256rm 0U, // VUNPCKHPDZ256rmb 0U, // VUNPCKHPDZ256rmbk 0U, // VUNPCKHPDZ256rmbkz 0U, // VUNPCKHPDZ256rmk 0U, // VUNPCKHPDZ256rmkz 0U, // VUNPCKHPDZ256rr 0U, // VUNPCKHPDZ256rrk 0U, // VUNPCKHPDZ256rrkz 0U, // VUNPCKHPDZrm 0U, // VUNPCKHPDZrmb 0U, // VUNPCKHPDZrmbk 0U, // VUNPCKHPDZrmbkz 0U, // VUNPCKHPDZrmk 0U, // VUNPCKHPDZrmkz 0U, // VUNPCKHPDZrr 0U, // VUNPCKHPDZrrk 0U, // VUNPCKHPDZrrkz 0U, // VUNPCKHPDrm 0U, // VUNPCKHPDrr 0U, // VUNPCKHPSYrm 0U, // VUNPCKHPSYrr 0U, // VUNPCKHPSZ128rm 0U, // VUNPCKHPSZ128rmb 0U, // VUNPCKHPSZ128rmbk 0U, // VUNPCKHPSZ128rmbkz 0U, // VUNPCKHPSZ128rmk 0U, // VUNPCKHPSZ128rmkz 0U, // VUNPCKHPSZ128rr 0U, // VUNPCKHPSZ128rrk 0U, // VUNPCKHPSZ128rrkz 0U, // VUNPCKHPSZ256rm 0U, // VUNPCKHPSZ256rmb 0U, // VUNPCKHPSZ256rmbk 0U, // VUNPCKHPSZ256rmbkz 0U, // VUNPCKHPSZ256rmk 0U, // VUNPCKHPSZ256rmkz 0U, // VUNPCKHPSZ256rr 0U, // VUNPCKHPSZ256rrk 0U, // VUNPCKHPSZ256rrkz 0U, // VUNPCKHPSZrm 0U, // VUNPCKHPSZrmb 0U, // VUNPCKHPSZrmbk 0U, // VUNPCKHPSZrmbkz 0U, // VUNPCKHPSZrmk 0U, // VUNPCKHPSZrmkz 0U, // VUNPCKHPSZrr 0U, // VUNPCKHPSZrrk 0U, // VUNPCKHPSZrrkz 0U, // VUNPCKHPSrm 0U, // VUNPCKHPSrr 0U, // VUNPCKLPDYrm 0U, // VUNPCKLPDYrr 0U, // VUNPCKLPDZ128rm 0U, // VUNPCKLPDZ128rmb 0U, // VUNPCKLPDZ128rmbk 0U, // VUNPCKLPDZ128rmbkz 0U, // VUNPCKLPDZ128rmk 0U, // VUNPCKLPDZ128rmkz 0U, // VUNPCKLPDZ128rr 0U, // VUNPCKLPDZ128rrk 0U, // VUNPCKLPDZ128rrkz 0U, // VUNPCKLPDZ256rm 0U, // VUNPCKLPDZ256rmb 0U, // VUNPCKLPDZ256rmbk 0U, // VUNPCKLPDZ256rmbkz 0U, // VUNPCKLPDZ256rmk 0U, // VUNPCKLPDZ256rmkz 0U, // VUNPCKLPDZ256rr 0U, // VUNPCKLPDZ256rrk 0U, // VUNPCKLPDZ256rrkz 0U, // VUNPCKLPDZrm 0U, // VUNPCKLPDZrmb 0U, // VUNPCKLPDZrmbk 0U, // VUNPCKLPDZrmbkz 0U, // VUNPCKLPDZrmk 0U, // VUNPCKLPDZrmkz 0U, // VUNPCKLPDZrr 0U, // VUNPCKLPDZrrk 0U, // VUNPCKLPDZrrkz 0U, // VUNPCKLPDrm 0U, // VUNPCKLPDrr 0U, // VUNPCKLPSYrm 0U, // VUNPCKLPSYrr 0U, // VUNPCKLPSZ128rm 0U, // VUNPCKLPSZ128rmb 0U, // VUNPCKLPSZ128rmbk 0U, // VUNPCKLPSZ128rmbkz 0U, // VUNPCKLPSZ128rmk 0U, // VUNPCKLPSZ128rmkz 0U, // VUNPCKLPSZ128rr 0U, // VUNPCKLPSZ128rrk 0U, // VUNPCKLPSZ128rrkz 0U, // VUNPCKLPSZ256rm 0U, // VUNPCKLPSZ256rmb 0U, // VUNPCKLPSZ256rmbk 0U, // VUNPCKLPSZ256rmbkz 0U, // VUNPCKLPSZ256rmk 0U, // VUNPCKLPSZ256rmkz 0U, // VUNPCKLPSZ256rr 0U, // VUNPCKLPSZ256rrk 0U, // VUNPCKLPSZ256rrkz 0U, // VUNPCKLPSZrm 0U, // VUNPCKLPSZrmb 0U, // VUNPCKLPSZrmbk 0U, // VUNPCKLPSZrmbkz 0U, // VUNPCKLPSZrmk 0U, // VUNPCKLPSZrmkz 0U, // VUNPCKLPSZrr 0U, // VUNPCKLPSZrrk 0U, // VUNPCKLPSZrrkz 0U, // VUNPCKLPSrm 0U, // VUNPCKLPSrr 0U, // VXORPDYrm 0U, // VXORPDYrr 0U, // VXORPDZ128rm 0U, // VXORPDZ128rmb 0U, // VXORPDZ128rmbk 0U, // VXORPDZ128rmbkz 0U, // VXORPDZ128rmk 0U, // VXORPDZ128rmkz 0U, // VXORPDZ128rr 0U, // VXORPDZ128rrk 0U, // VXORPDZ128rrkz 0U, // VXORPDZ256rm 0U, // VXORPDZ256rmb 0U, // VXORPDZ256rmbk 0U, // VXORPDZ256rmbkz 0U, // VXORPDZ256rmk 0U, // VXORPDZ256rmkz 0U, // VXORPDZ256rr 0U, // VXORPDZ256rrk 0U, // VXORPDZ256rrkz 0U, // VXORPDZrm 0U, // VXORPDZrmb 0U, // VXORPDZrmbk 0U, // VXORPDZrmbkz 0U, // VXORPDZrmk 0U, // VXORPDZrmkz 0U, // VXORPDZrr 0U, // VXORPDZrrk 0U, // VXORPDZrrkz 0U, // VXORPDrm 0U, // VXORPDrr 0U, // VXORPSYrm 0U, // VXORPSYrr 0U, // VXORPSZ128rm 0U, // VXORPSZ128rmb 0U, // VXORPSZ128rmbk 0U, // VXORPSZ128rmbkz 0U, // VXORPSZ128rmk 0U, // VXORPSZ128rmkz 0U, // VXORPSZ128rr 0U, // VXORPSZ128rrk 0U, // VXORPSZ128rrkz 0U, // VXORPSZ256rm 0U, // VXORPSZ256rmb 0U, // VXORPSZ256rmbk 0U, // VXORPSZ256rmbkz 0U, // VXORPSZ256rmk 0U, // VXORPSZ256rmkz 0U, // VXORPSZ256rr 0U, // VXORPSZ256rrk 0U, // VXORPSZ256rrkz 0U, // VXORPSZrm 0U, // VXORPSZrmb 0U, // VXORPSZrmbk 0U, // VXORPSZrmbkz 0U, // VXORPSZrmk 0U, // VXORPSZrmkz 0U, // VXORPSZrr 0U, // VXORPSZrrk 0U, // VXORPSZrrkz 0U, // VXORPSrm 0U, // VXORPSrr 0U, // VZEROALL 0U, // VZEROUPPER 0U, // WAIT 0U, // WBINVD 0U, // WBNOINVD 0U, // WRFSBASE 0U, // WRFSBASE64 0U, // WRGSBASE 0U, // WRGSBASE64 0U, // WRMSR 0U, // WRPKRUr 0U, // WRSSD 0U, // WRSSQ 0U, // WRUSSD 0U, // WRUSSQ 0U, // XABORT 0U, // XACQUIRE_PREFIX 0U, // XADD16rm 0U, // XADD16rr 0U, // XADD32rm 0U, // XADD32rr 0U, // XADD64rm 0U, // XADD64rr 0U, // XADD8rm 0U, // XADD8rr 0U, // XBEGIN_2 0U, // XBEGIN_4 0U, // XCHG16ar 0U, // XCHG16rm 0U, // XCHG16rr 0U, // XCHG32ar 0U, // XCHG32rm 0U, // XCHG32rr 0U, // XCHG64ar 0U, // XCHG64rm 0U, // XCHG64rr 0U, // XCHG8rm 0U, // XCHG8rr 0U, // XCH_F 0U, // XCRYPTCBC 0U, // XCRYPTCFB 0U, // XCRYPTCTR 0U, // XCRYPTECB 0U, // XCRYPTOFB 0U, // XEND 0U, // XGETBV 0U, // XLAT 0U, // XOR16i16 0U, // XOR16mi 0U, // XOR16mi8 0U, // XOR16mr 0U, // XOR16ri 0U, // XOR16ri8 0U, // XOR16rm 0U, // XOR16rr 0U, // XOR16rr_REV 0U, // XOR32i32 0U, // XOR32mi 0U, // XOR32mi8 0U, // XOR32mr 0U, // XOR32ri 0U, // XOR32ri8 0U, // XOR32rm 0U, // XOR32rr 0U, // XOR32rr_REV 0U, // XOR64i32 0U, // XOR64mi32 0U, // XOR64mi8 0U, // XOR64mr 0U, // XOR64ri32 0U, // XOR64ri8 0U, // XOR64rm 0U, // XOR64rr 0U, // XOR64rr_REV 0U, // XOR8i8 0U, // XOR8mi 0U, // XOR8mi8 0U, // XOR8mr 0U, // XOR8ri 0U, // XOR8ri8 0U, // XOR8rm 0U, // XOR8rr 0U, // XOR8rr_REV 0U, // XORPDrm 0U, // XORPDrr 0U, // XORPSrm 0U, // XORPSrr 0U, // XRELEASE_PREFIX 0U, // XRSTOR 0U, // XRSTOR64 0U, // XRSTORS 0U, // XRSTORS64 0U, // XSAVE 0U, // XSAVE64 0U, // XSAVEC 0U, // XSAVEC64 0U, // XSAVEOPT 0U, // XSAVEOPT64 0U, // XSAVES 0U, // XSAVES64 0U, // XSETBV 0U, // XSHA1 0U, // XSHA256 0U, // XSTORE 0U, // XTEST }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint64_t Bits = 0; Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; Bits |= (uint64_t)OpInfo2[opcode] << 48; SStream_concat0(O, AsmStrs+(Bits & 16383)-1); // Fragment 0 encoded into 7 bits for 103 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 127)); switch ((Bits >> 14) & 127) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... printOperand(MI, 0, O); break; case 2: // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... printOperand(MI, 5, O); SStream_concat0(O, ", "); break; case 3: // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 4: // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... printi16mem(MI, 2, O); SStream_concat0(O, ", "); break; case 5: // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, ANDN32rm, CMOVA32rm, CM... printi32mem(MI, 2, O); break; case 6: // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, ANDN64rm, CMOVA64rm, CM... printi64mem(MI, 2, O); break; case 7: // ADC8rm, ADD8rm, AND8rm, CRC32r32m8, CRC32r64m8, OR8rm, SBB8rm, SUB8rm,... printi8mem(MI, 2, O); SStream_concat0(O, ", "); break; case 8: // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,... printf128mem(MI, 2, O); SStream_concat0(O, ", "); break; case 9: // ADDSDrm, ADDSDrm_Int, CVTSD2SSrm_Int, DIVSDrm, DIVSDrm_Int, MAXCSDrm, ... printf64mem(MI, 2, O); break; case 10: // ADDSSrm, ADDSSrm_Int, CVTSS2SDrm_Int, DIVSSrm, DIVSSrm_Int, MAXCSSrm, ... printf32mem(MI, 2, O); break; case 11: // ADD_F32m, DIVR_F32m, DIV_F32m, FCOM32m, FCOMP32m, FLDENVm, FRSTORm, FS... printf32mem(MI, 0, O); return; break; case 12: // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MUL_F64m, S... printf64mem(MI, 0, O); return; break; case 13: // ADD_FI16m, CALL16m, CALL16m_NT, DEC16m, DIV16m, DIVR_FI16m, DIV_FI16m,... printi16mem(MI, 0, O); return; break; case 14: // ADD_FI32m, CALL32m, CALL32m_NT, CLRSSBSY, DEC32m, DIV32m, DIVR_FI32m, ... printi32mem(MI, 0, O); return; break; case 15: // AESDECLASTrm, AESDECrm, AESENCLASTrm, AESENCrm, GF2P8MULBrm, PACKSSDWr... printi128mem(MI, 2, O); SStream_concat0(O, ", "); break; case 16: // AESIMCrm, BNDMOV64rm, CVTDQ2PSrm, INVEPT32, INVEPT64, INVPCID32, INVPC... printi128mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 17: // AESIMCrr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCI... printOperand(MI, 1, O); break; case 18: // AESKEYGENASSIST128rm, EXTRACTPSmr, MMX_PSHUFWmi, PCMPESTRIrm, PCMPESTR... printU8Imm(MI, 6, O); SStream_concat0(O, ", "); break; case 19: // AESKEYGENASSIST128rr, EXTRACTPSrr, KSHIFTLBri, KSHIFTLDri, KSHIFTLQri,... printU8Imm(MI, 2, O); break; case 20: // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... printOperand(MI, 6, O); SStream_concat0(O, ", "); break; case 21: // BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, BLCS32rm, BLSFILL32rm, B... printi32mem(MI, 1, O); break; case 22: // BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, BLCS64rm, BLSFILL64rm, B... printi64mem(MI, 1, O); break; case 23: // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, CMPSDrm_alt, CMPSS... printU8Imm(MI, 7, O); SStream_concat0(O, ", "); break; case 24: // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... printU8Imm(MI, 3, O); break; case 25: // BNDCL32rm, BNDCL64rm, BNDCN32rm, BNDCN64rm, BNDCU32rm, BNDCU64rm, BNDL... printanymem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 26: // BSF16rm, BSR16rm, CMP16rm, KMOVWkm, LAR16rm, LAR32rm, LAR64rm, LSL16rm... printi16mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 27: // CALL64m, CALL64m_NT, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, ILD_F64m, IMU... printi64mem(MI, 0, O); return; break; case 28: // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... printPCRelImm(MI, 0, O); return; break; case 29: // CLDEMOTE, CLFLUSH, CLFLUSHOPT, CLWB, DEC8m, DIV8m, IDIV8m, IMUL8m, INC... printi8mem(MI, 0, O); return; break; case 30: // CMP8rm, KMOVBkm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32... printi8mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 31: // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSDrm_Int, CMPSSrm, CMPSSrm_Int, VCMPPD... printSSEAVXCC(MI, 7, O); break; case 32: // CMPPDrri, CMPPSrri, CMPSDrr, CMPSDrr_Int, CMPSSrr, CMPSSrr_Int, VCMPPD... printSSEAVXCC(MI, 3, O); break; case 33: // CMPSB, INSB, SCASB, STOSB printDstIdx8(MI, 0, O); break; case 34: // CMPSL, INSL, SCASL, STOSL printDstIdx32(MI, 0, O); break; case 35: // CMPSQ, SCASQ, STOSQ printDstIdx64(MI, 0, O); break; case 36: // CMPSW, INSW, SCASW, STOSW printDstIdx16(MI, 0, O); break; case 37: // CMPXCHG16B printi128mem(MI, 0, O); return; break; case 38: // COMISDrm, COMISDrm_Int, CVTPS2PDrm, CVTSD2SI64rm_Int, CVTSD2SIrm_Int, ... printf64mem(MI, 1, O); break; case 39: // COMISSrm, COMISSrm_Int, CVTSS2SDrm, CVTSS2SI64rm_Int, CVTSS2SIrm_Int, ... printf32mem(MI, 1, O); break; case 40: // CVTPD2DQrm, CVTPD2PSrm, CVTPS2DQrm, CVTTPD2DQrm, CVTTPS2DQrm, MMX_CVTP... printf128mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 41: // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR... printopaquemem(MI, 0, O); return; break; case 42: // FBLDm, FBSTPm, LD_F80m, ST_FP80m printf80mem(MI, 0, O); return; break; case 43: // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir printU8Imm(MI, 0, O); break; case 44: // INSERTQI, VALIGNDZ128rrikz, VALIGNDZ256rrikz, VALIGNDZrrikz, VALIGNQZ1... printU8Imm(MI, 4, O); break; case 45: // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... printopaquemem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 46: // LODSB, OUTSB printSrcIdx8(MI, 0, O); break; case 47: // LODSL, OUTSL printSrcIdx32(MI, 0, O); break; case 48: // LODSQ printSrcIdx64(MI, 0, O); SStream_concat0(O, ", %rax"); op_addReg(MI, X86_REG_RAX); return; break; case 49: // LODSW, OUTSW printSrcIdx16(MI, 0, O); break; case 50: // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a printMemOffs16(MI, 0, O); break; case 51: // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a printMemOffs32(MI, 0, O); break; case 52: // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a printMemOffs64(MI, 0, O); break; case 53: // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a printMemOffs8(MI, 0, O); break; case 54: // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64, VCVTDQ2PSZrm, VCVTQQ2PDZrm, VCV... printi512mem(MI, 1, O); break; case 55: // MOVSB printSrcIdx8(MI, 1, O); SStream_concat0(O, ", "); printDstIdx8(MI, 0, O); return; break; case 56: // MOVSL printSrcIdx32(MI, 1, O); SStream_concat0(O, ", "); printDstIdx32(MI, 0, O); return; break; case 57: // MOVSQ printSrcIdx64(MI, 1, O); SStream_concat0(O, ", "); printDstIdx64(MI, 0, O); return; break; case 58: // MOVSW printSrcIdx16(MI, 1, O); SStream_concat0(O, ", "); printDstIdx16(MI, 0, O); return; break; case 59: // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... printU8Imm(MI, 5, O); break; case 60: // V4FMADDPSrm, V4FMADDSSrm, V4FNMADDPSrm, V4FNMADDSSrm, VADDPDZ128rmkz, ... printf128mem(MI, 3, O); SStream_concat0(O, ", "); break; case 61: // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... printf128mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 62: // VADDPDYrm, VADDPDZ256rm, VADDPSYrm, VADDPSZ256rm, VADDSUBPDYrm, VADDSU... printf256mem(MI, 2, O); SStream_concat0(O, ", "); break; case 63: // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDSDZrm_Intk, VANDNPDZ1... printf64mem(MI, 4, O); break; case 64: // VADDPDZ128rmbkz, VADDPDZ256rmbkz, VADDPDZrmbkz, VADDSDZrm_Intkz, VANDN... printf64mem(MI, 3, O); break; case 65: // VADDPDZ128rrk, VADDPDZ256rrk, VADDPDZrrk, VADDPSZ128rrk, VADDPSZ256rrk... printOperand(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 66: // VADDPDZ128rrkz, VADDPDZ256rrkz, VADDPDZrrkz, VADDPSZ128rrkz, VADDPSZ25... printOperand(MI, 3, O); SStream_concat0(O, ", "); break; case 67: // VADDPDZ256rmk, VADDPSZ256rmk, VANDNPDZ256rmk, VANDNPSZ256rmk, VANDPDZ2... printf256mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 68: // VADDPDZ256rmkz, VADDPSZ256rmkz, VANDNPDZ256rmkz, VANDNPSZ256rmkz, VAND... printf256mem(MI, 3, O); SStream_concat0(O, ", "); break; case 69: // VADDPDZrm, VADDPSZrm, VANDNPDZrm, VANDNPSZrm, VANDPDZrm, VANDPSZrm, VB... printf512mem(MI, 2, O); SStream_concat0(O, ", "); break; case 70: // VADDPDZrmk, VADDPSZrmk, VANDNPDZrmk, VANDNPSZrmk, VANDPDZrmk, VANDPSZr... printf512mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 71: // VADDPDZrmkz, VADDPSZrmkz, VANDNPDZrmkz, VANDNPSZrmkz, VANDPDZrmkz, VAN... printf512mem(MI, 3, O); SStream_concat0(O, ", "); break; case 72: // VADDPDZrrb, VADDPSZrrb, VADDSDZrrb_Int, VADDSSZrrb_Int, VCVTDQ2PSZrrbk... printRoundingControl(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 73: // VADDPDZrrbk, VADDPSZrrbk, VADDSDZrrb_Intk, VADDSSZrrb_Intk, VCVTSD2SSZ... printRoundingControl(MI, 5, O); SStream_concat0(O, ", "); printOperand(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 74: // VADDPDZrrbkz, VADDPSZrrbkz, VADDSDZrrb_Intkz, VADDSSZrrb_Intkz, VCVTDQ... printRoundingControl(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); break; case 75: // VADDPSZ128rmbk, VADDPSZ256rmbk, VADDPSZrmbk, VADDSSZrm_Intk, VANDNPSZ1... printf32mem(MI, 4, O); break; case 76: // VADDPSZ128rmbkz, VADDPSZ256rmbkz, VADDPSZrmbkz, VADDSSZrm_Intkz, VANDN... printf32mem(MI, 3, O); break; case 77: // VAESDECLASTYrm, VAESDECLASTZ256rm, VAESDECYrm, VAESDECZ256rm, VAESENCL... printi256mem(MI, 2, O); SStream_concat0(O, ", "); break; case 78: // VAESDECLASTZrm, VAESDECZrm, VAESENCLASTZrm, VAESENCZrm, VCVTDQ2PSZrmkz... printi512mem(MI, 2, O); SStream_concat0(O, ", "); break; case 79: // VALIGNDZ128rmbik, VALIGNDZ128rmik, VALIGNDZ256rmbik, VALIGNDZ256rmik, ... printU8Imm(MI, 9, O); SStream_concat0(O, ", "); break; case 80: // VALIGNDZ128rmbikz, VALIGNDZ128rmikz, VALIGNDZ256rmbikz, VALIGNDZ256rmi... printU8Imm(MI, 8, O); SStream_concat0(O, ", "); break; case 81: // VBLENDVPDYrm, VBLENDVPDrm, VBLENDVPSYrm, VBLENDVPSrm, VFMADDPD4Ymr, VF... printOperand(MI, 7, O); SStream_concat0(O, ", "); break; case 82: // VBROADCASTF32X8rm, VBROADCASTF64X4rm, VCVTPD2DQYrm, VCVTPD2DQZ256rm, V... printf256mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 83: // VBROADCASTI32X2Z128mk, VBROADCASTI32X2Z256mk, VBROADCASTI32X2Zmk, VCVT... printi64mem(MI, 3, O); break; case 84: // VBROADCASTI32X4Z256rmk, VBROADCASTI32X4rmk, VBROADCASTI64X2Z128rmk, VB... printi128mem(MI, 3, O); SStream_concat0(O, ", "); break; case 85: // VBROADCASTI32X8rm, VBROADCASTI64X4rm, VCVTDQ2PDZrm, VCVTDQ2PSYrm, VCVT... printi256mem(MI, 1, O); break; case 86: // VBROADCASTI32X8rmk, VBROADCASTI64X4rmk, VCVTDQ2PDZrmk, VCVTDQ2PSZ256rm... printi256mem(MI, 3, O); SStream_concat0(O, ", "); break; case 87: // VCMPPDZ128rmbik, VCMPPDZ128rmik, VCMPPDZ256rmbik, VCMPPDZ256rmik, VCMP... printSSEAVXCC(MI, 8, O); break; case 88: // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrribk, VCMPPDZrrik, VCMPPSZ128r... printSSEAVXCC(MI, 4, O); break; case 89: // VCVTDQ2PDZ128rmbk, VCVTDQ2PDZ256rmbk, VCVTDQ2PDZrmbk, VCVTDQ2PSZ128rmb... printi32mem(MI, 3, O); break; case 90: // VCVTDQ2PSZrmk, VCVTQQ2PDZrmk, VCVTQQ2PSZrmk, VCVTUDQ2PSZrmk, VCVTUQQ2P... printi512mem(MI, 3, O); SStream_concat0(O, ", "); break; case 91: // VCVTDQ2PSZrrb, VCVTPD2DQZrrb, VCVTPD2PSZrrb, VCVTPD2QQZrrb, VCVTPD2UDQ... printRoundingControl(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 92: // VCVTPD2DQZrm, VCVTPD2PSZrm, VCVTPD2QQZrm, VCVTPD2UDQZrm, VCVTPD2UQQZrm... printf512mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 93: // VGATHERDPDYrm, VGATHERDPDrm, VGATHERDPSYrm, VGATHERDPSrm, VGATHERQPDYr... printOperand(MI, 8, O); SStream_concat0(O, ", "); break; case 94: // VGATHERDPDZ128rm, VGATHERDPSZ128rm, VGATHERQPDZ128rm, VGATHERQPSZ256rm... printi128mem(MI, 4, O); SStream_concat0(O, ", "); break; case 95: // VGATHERDPDZ256rm, VGATHERDPSZ256rm, VGATHERQPDZ256rm, VGATHERQPSZrm, V... printi256mem(MI, 4, O); SStream_concat0(O, ", "); break; case 96: // VGATHERDPDZrm, VGATHERDPSZrm, VGATHERQPDZrm, VGF2P8MULBZrmk, VPACKSSDW... printi512mem(MI, 4, O); SStream_concat0(O, ", "); break; case 97: // VGATHERQPSZ128rm, VPADDQZ128rmbk, VPADDQZ256rmbk, VPADDQZrmbk, VPANDNQ... printi64mem(MI, 4, O); break; case 98: // VPACKSSDWZ128rmbk, VPACKSSDWZ256rmbk, VPACKSSDWZrmbk, VPACKUSDWZ128rmb... printi32mem(MI, 4, O); break; case 99: // VPBROADCASTBZ128mk, VPBROADCASTBZ256mk, VPBROADCASTBZmk printi8mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); SStream_concat0(O, "}"); return; break; case 100: // VPBROADCASTWZ128mk, VPBROADCASTWZ256mk, VPBROADCASTWZmk, VPMOVSXBQZ128... printi16mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); SStream_concat0(O, "}"); return; break; case 101: // VPCOMBmi, VPCOMDmi, VPCOMQmi, VPCOMUBmi, VPCOMUDmi, VPCOMUQmi, VPCOMUW... printXOPCC(MI, 7, O); break; case 102: // VPCOMBri, VPCOMDri, VPCOMQri, VPCOMUBri, VPCOMUDri, VPCOMUQri, VPCOMUW... printXOPCC(MI, 3, O); break; } // Fragment 1 encoded into 7 bits for 99 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 21) & 127)); switch ((Bits >> 21) & 127) { default: // unreachable case 0: // AAD8i8, AAM8i8, ADD_FPrST0, ADD_FST0r, ADD_FrST0, BSWAP16r_BAD, BSWAP3... return; break; case 1: // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, LODSW, MOV16ao16, MOV1... SStream_concat0(O, ", %ax"); op_addReg(MI, X86_REG_AX); return; break; case 2: // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... printi16mem(MI, 0, O); break; case 3: // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64... printOperand(MI, 1, O); break; case 4: // ADC16rr_REV, ADC32rr_REV, ADC64rr_REV, ADC8rr_REV, ADCX32rr, ADCX64rr,... printOperand(MI, 0, O); break; case 5: // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, LODSL, MOV32ao16, MOV3... SStream_concat0(O, ", %eax"); op_addReg(MI, X86_REG_EAX); return; break; case 6: // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... printi32mem(MI, 0, O); break; case 7: // ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADD32rm, ADD64rm, ADDSDrm, ADDSD... SStream_concat0(O, ", "); break; case 8: // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64ao32, MOV64ao64, OR64i32,... SStream_concat0(O, ", %rax"); op_addReg(MI, X86_REG_RAX); return; break; case 9: // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... printi64mem(MI, 0, O); break; case 10: // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, LODSB, MOV8ao16, MOV8ao32, MOV8... SStream_concat0(O, ", %al"); op_addReg(MI, X86_REG_AL); return; break; case 11: // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... printi8mem(MI, 0, O); return; break; case 12: // AESKEYGENASSIST128rm, PCMPESTRIrm, PCMPESTRMrm, PCMPISTRIrm, PCMPISTRM... printi128mem(MI, 1, O); break; case 13: // BEXTR32rm, BEXTRI32mi, BZHI32rm, IMUL32rmi, IMUL32rmi8, LWPINS32rmi, L... printi32mem(MI, 1, O); break; case 14: // BEXTR64rm, BEXTRI64mi, BZHI64rm, IMUL64rmi32, IMUL64rmi8, MMX_PSHUFWmi... printi64mem(MI, 1, O); break; case 15: // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, DPPDrmi, DPPSrmi, ... printf128mem(MI, 2, O); SStream_concat0(O, ", "); break; case 16: // BNDMOV64mr, MOVDQAmr, MOVDQUmr, VMOVDQA32Z128mr, VMOVDQA32Z128mrk, VMO... printi128mem(MI, 0, O); break; case 17: // BNDSTXmr printanymem(MI, 0, O); return; break; case 18: // CMOVBE_F, CMOVB_F, CMOVE_F, CMOVNBE_F, CMOVNB_F, CMOVNE_F, CMOVNP_F, C... SStream_concat0(O, ", %st(0)"); op_addReg(MI, X86_REG_ST0); return; break; case 19: // CMPPDrmi, CMPPDrri, VCMPPDYrmi, VCMPPDYrri, VCMPPDZ128rmbi, VCMPPDZ128... SStream_concat0(O, "pd\t"); break; case 20: // CMPPSrmi, CMPPSrri, VCMPPSYrmi, VCMPPSYrri, VCMPPSZ128rmbi, VCMPPSZ128... SStream_concat0(O, "ps\t"); break; case 21: // CMPSDrm, CMPSDrm_Int, CMPSDrr, CMPSDrr_Int, VCMPSDZrm, VCMPSDZrm_Int, ... SStream_concat0(O, "sd\t"); break; case 22: // CMPSDrm_alt, ROUNDSDm_Int, VCMPPDZ128rmbi_alt, VCMPPDZ256rmbi_alt, VCM... printf64mem(MI, 2, O); break; case 23: // CMPSSrm, CMPSSrm_Int, CMPSSrr, CMPSSrr_Int, VCMPSSZrm, VCMPSSZrm_Int, ... SStream_concat0(O, "ss\t"); break; case 24: // CMPSSrm_alt, INSERTPSrm, ROUNDSSm_Int, VCMPPSZ128rmbi_alt, VCMPPSZ256r... printf32mem(MI, 2, O); break; case 25: // EXTRACTPSmr, PEXTRBmr, PEXTRDmr, PEXTRQmr, PEXTRWmr, SHLD16mri8, SHLD3... printOperand(MI, 5, O); SStream_concat0(O, ", "); break; case 26: // FARJMP16i, FARJMP32i SStream_concat0(O, ":"); printOperand(MI, 0, O); return; break; case 27: // GF2P8AFFINEINVQBrmi, GF2P8AFFINEQBrmi, MPSADBWrmi, PALIGNRrmi, PBLENDW... printi128mem(MI, 2, O); SStream_concat0(O, ", "); break; case 28: // IMUL16rmi, IMUL16rmi8 printi16mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 29: // MMX_PALIGNRrmi, PINSRQrm, VALIGNQZ128rmbi, VALIGNQZ256rmbi, VALIGNQZrm... printi64mem(MI, 2, O); break; case 30: // MMX_PINSRWrm, PINSRWrm, VPINSRWZrm, VPINSRWrm printi16mem(MI, 2, O); SStream_concat0(O, ", "); break; case 31: // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVNTPDmr, MOVNTPSmr, MOVUPDmr, MOVUPSm... printf128mem(MI, 0, O); break; case 32: // MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVNTSD, MOVSDmr, VMOVHPDZ128m... printf64mem(MI, 0, O); break; case 33: // MOVNTSS, MOVSSmr, VMOVSSZmr, VMOVSSZmrk, VMOVSSmr printf32mem(MI, 0, O); break; case 34: // OUTSB, OUTSL, OUTSW SStream_concat0(O, ", %dx"); op_addReg(MI, X86_REG_DX); return; break; case 35: // PINSRBrm, VGF2P8AFFINEINVQBZ128rmbi, VGF2P8AFFINEINVQBZ256rmbi, VGF2P8... printi8mem(MI, 2, O); break; case 36: // PINSRDrm, VALIGNDZ128rmbi, VALIGNDZ256rmbi, VALIGNDZrmbi, VPCMPDZ128rm... printi32mem(MI, 2, O); break; case 37: // ROUNDPDm, ROUNDPSm, VFPCLASSPDZ128rm, VFPCLASSPSZ128rm, VGETMANTPDZ128... printf128mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 38: // ROUNDSDm, VFPCLASSPDZ128rmb, VFPCLASSPDZ256rmb, VFPCLASSPDZrmb, VFPCLA... printf64mem(MI, 1, O); break; case 39: // ROUNDSSm, VFPCLASSPSZ128rmb, VFPCLASSPSZ256rmb, VFPCLASSPSZrmb, VFPCLA... printf32mem(MI, 1, O); break; case 40: // V4FMADDPSrm, V4FMADDSSrm, V4FNMADDPSrm, V4FNMADDSSrm, VADDPDZ128rmkz, ... printOperand(MI, 2, O); break; case 41: // V4FMADDPSrmk, V4FMADDSSrmk, V4FNMADDPSrmk, V4FNMADDSSrmk, VADDPDZ128rm... SStream_concat0(O, "}"); return; break; case 42: // V4FMADDPSrmkz, V4FMADDSSrmkz, V4FNMADDPSrmkz, V4FNMADDSSrmkz, VFMADD13... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; break; case 43: // VADDPDZ128rmb, VADDPDZ128rmbk, VADDPDZ128rmbkz, VANDNPDZ128rmb, VANDNP... SStream_concat0(O, "{1to2}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_2); break; case 44: // VADDPDZ256rmb, VADDPDZ256rmbk, VADDPDZ256rmbkz, VADDPSZ128rmb, VADDPSZ... SStream_concat0(O, "{1to4}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_4); break; case 45: // VADDPDZrmb, VADDPDZrmbk, VADDPDZrmbkz, VADDPSZ256rmb, VADDPSZ256rmbk, ... SStream_concat0(O, "{1to8}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_8); break; case 46: // VADDPSZrmb, VADDPSZrmbk, VADDPSZrmbkz, VANDNPSZrmb, VANDNPSZrmbk, VAND... SStream_concat0(O, "{1to16}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_16); break; case 47: // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VPSHLDDZ128rmbik, V... printi32mem(MI, 4, O); break; case 48: // VALIGNDZ128rmbikz, VALIGNDZ256rmbikz, VALIGNDZrmbikz, VPCMPDZ128rmibk_... printi32mem(MI, 3, O); break; case 49: // VALIGNDZ128rmik, VALIGNQZ128rmik, VDBPSADBWZ128rmik, VGF2P8AFFINEINVQB... printi128mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 50: // VALIGNDZ128rmikz, VALIGNQZ128rmikz, VDBPSADBWZ128rmikz, VGATHERDPDrm, ... printi128mem(MI, 3, O); SStream_concat0(O, ", "); break; case 51: // VALIGNDZ256rmi, VALIGNQZ256rmi, VDBPSADBWZ256rmi, VDPPSYrmi, VGF2P8AFF... printi256mem(MI, 2, O); SStream_concat0(O, ", "); break; case 52: // VALIGNDZ256rmik, VALIGNQZ256rmik, VDBPSADBWZ256rmik, VGF2P8AFFINEINVQB... printi256mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 53: // VALIGNDZ256rmikz, VALIGNQZ256rmikz, VDBPSADBWZ256rmikz, VGATHERDPDYrm,... printi256mem(MI, 3, O); SStream_concat0(O, ", "); break; case 54: // VALIGNDZrmi, VALIGNQZrmi, VDBPSADBWZrmi, VGF2P8AFFINEINVQBZrmi, VGF2P8... printi512mem(MI, 2, O); SStream_concat0(O, ", "); break; case 55: // VALIGNDZrmik, VALIGNQZrmik, VDBPSADBWZrmik, VGF2P8AFFINEINVQBZrmik, VG... printi512mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 56: // VALIGNDZrmikz, VALIGNQZrmikz, VDBPSADBWZrmikz, VGF2P8AFFINEINVQBZrmikz... printi512mem(MI, 3, O); SStream_concat0(O, ", "); break; case 57: // VALIGNQZ128rmbik, VALIGNQZ256rmbik, VALIGNQZrmbik, VPSHLDQZ128rmbik, V... printi64mem(MI, 4, O); break; case 58: // VALIGNQZ128rmbikz, VALIGNQZ256rmbikz, VALIGNQZrmbikz, VGATHERQPSrm, VP... printi64mem(MI, 3, O); break; case 59: // VBLENDPDYrmi, VBLENDPSYrmi, VBLENDVPDYrm, VBLENDVPSYrm, VCMPPDYrmi_alt... printf256mem(MI, 2, O); SStream_concat0(O, ", "); break; case 60: // VCMPPDZ128rmbi_altk, VCMPPDZ256rmbi_altk, VCMPPDZrmbi_altk, VCMPSDZrmi... printf64mem(MI, 3, O); break; case 61: // VCMPPDZ128rmi_altk, VCMPPSZ128rmi_altk, VFIXUPIMMPDZ128rmi, VFIXUPIMMP... printf128mem(MI, 3, O); SStream_concat0(O, ", "); break; case 62: // VCMPPDZ256rmi_altk, VCMPPSZ256rmi_altk, VFIXUPIMMPDZ256rmi, VFIXUPIMMP... printf256mem(MI, 3, O); SStream_concat0(O, ", "); break; case 63: // VCMPPDZrmi_alt, VCMPPSZrmi_alt, VFPCLASSPDZrmk, VFPCLASSPSZrmk, VGETMA... printf512mem(MI, 2, O); SStream_concat0(O, ", "); break; case 64: // VCMPPDZrmi_altk, VCMPPSZrmi_altk, VFIXUPIMMPDZrmi, VFIXUPIMMPSZrmi, VG... printf512mem(MI, 3, O); SStream_concat0(O, ", "); break; case 65: // VCMPPDZrrib, VCMPPDZrribk SStream_concat0(O, "pd\t{sae}, "); op_addAvxSae(MI); break; case 66: // VCMPPDZrrib_alt, VCMPPDZrrib_altk, VCMPPSZrrib_alt, VCMPPSZrrib_altk, ... SStream_concat0(O, ", {sae}, "); op_addAvxSae(MI); break; case 67: // VCMPPSZ128rmbi_altk, VCMPPSZ256rmbi_altk, VCMPPSZrmbi_altk, VCMPSSZrmi... printf32mem(MI, 3, O); break; case 68: // VCMPPSZrrib, VCMPPSZrribk SStream_concat0(O, "ps\t{sae}, "); op_addAvxSae(MI); break; case 69: // VCMPSDZrrb_Int, VCMPSDZrrb_Intk SStream_concat0(O, "sd\t{sae}, "); op_addAvxSae(MI); break; case 70: // VCMPSSZrrb_Int, VCMPSSZrrb_Intk SStream_concat0(O, "ss\t{sae}, "); op_addAvxSae(MI); break; case 71: // VCOMPRESSPDZ256mr, VCOMPRESSPDZ256mrk, VCOMPRESSPSZ256mr, VCOMPRESSPSZ... printf256mem(MI, 0, O); break; case 72: // VCOMPRESSPDZmr, VCOMPRESSPDZmrk, VCOMPRESSPSZmr, VCOMPRESSPSZmrk, VMOV... printf512mem(MI, 0, O); break; case 73: // VCVTPS2PHZ128mrk, VCVTPS2PHZ256mrk, VCVTPS2PHZmrk, VEXTRACTF32x4Z256mr... printOperand(MI, 6, O); SStream_concat0(O, ", "); break; case 74: // VCVTSI2SDZrrb_Int, VCVTSI2SSZrrb_Int, VCVTSI642SDZrrb_Int, VCVTSI642SS... printRoundingControl(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 75: // VFIXUPIMMPDZ128rmbik, VFIXUPIMMPDZ128rmbikz, VFIXUPIMMPDZ256rmbik, VFI... printf64mem(MI, 4, O); break; case 76: // VFIXUPIMMPDZ128rmik, VFIXUPIMMPDZ128rmikz, VFIXUPIMMPSZ128rmik, VFIXUP... printf128mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 77: // VFIXUPIMMPDZ256rmik, VFIXUPIMMPDZ256rmikz, VFIXUPIMMPSZ256rmik, VFIXUP... printf256mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 78: // VFIXUPIMMPDZrmik, VFIXUPIMMPDZrmikz, VFIXUPIMMPSZrmik, VFIXUPIMMPSZrmi... printf512mem(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 79: // VFIXUPIMMPSZ128rmbik, VFIXUPIMMPSZ128rmbikz, VFIXUPIMMPSZ256rmbik, VFI... printf32mem(MI, 4, O); break; case 80: // VFPCLASSPDZ256rm, VFPCLASSPSZ256rm, VGETMANTPDZ256rmi, VGETMANTPSZ256r... printf256mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 81: // VFPCLASSPDZrm, VFPCLASSPSZrm, VGETMANTPDZrmi, VGETMANTPSZrmi, VPERMILP... printf512mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 82: // VGATHERPF0DPDm, VGATHERPF0DPSm, VGATHERPF0QPDm, VGATHERPF0QPSm, VGATHE... SStream_concat0(O, " {"); printOperand(MI, 0, O); SStream_concat0(O, "}"); return; break; case 83: // VGF2P8AFFINEINVQBZ128rmbik, VGF2P8AFFINEINVQBZ256rmbik, VGF2P8AFFINEIN... printi8mem(MI, 4, O); break; case 84: // VGF2P8AFFINEINVQBZ128rmbikz, VGF2P8AFFINEINVQBZ256rmbikz, VGF2P8AFFINE... printi8mem(MI, 3, O); break; case 85: // VGF2P8MULBZ128rmk, VGF2P8MULBZ256rmk, VGF2P8MULBZrmk, VPACKSSDWZ128rmk... printOperand(MI, 3, O); break; case 86: // VMOVDQA32Z256mr, VMOVDQA32Z256mrk, VMOVDQA64Z256mr, VMOVDQA64Z256mrk, ... printi256mem(MI, 0, O); break; case 87: // VMOVDQA32Zmr, VMOVDQA32Zmrk, VMOVDQA64Zmr, VMOVDQA64Zmrk, VMOVDQU16Zmr... printi512mem(MI, 0, O); break; case 88: // VPCMPBZ128rmi, VPCMPBZ128rmik, VPCMPBZ128rri, VPCMPBZ128rrik, VPCMPBZ2... SStream_concat0(O, "b\t"); break; case 89: // VPCMPDZ128rmi, VPCMPDZ128rmib, VPCMPDZ128rmibk, VPCMPDZ128rmik, VPCMPD... SStream_concat0(O, "d\t"); break; case 90: // VPCMPQZ128rmi, VPCMPQZ128rmib, VPCMPQZ128rmibk, VPCMPQZ128rmik, VPCMPQ... SStream_concat0(O, "q\t"); break; case 91: // VPCMPUBZ128rmi, VPCMPUBZ128rmik, VPCMPUBZ128rri, VPCMPUBZ128rrik, VPCM... SStream_concat0(O, "ub\t"); break; case 92: // VPCMPUDZ128rmi, VPCMPUDZ128rmib, VPCMPUDZ128rmibk, VPCMPUDZ128rmik, VP... SStream_concat0(O, "ud\t"); break; case 93: // VPCMPUQZ128rmi, VPCMPUQZ128rmib, VPCMPUQZ128rmibk, VPCMPUQZ128rmik, VP... SStream_concat0(O, "uq\t"); break; case 94: // VPCMPUWZ128rmi, VPCMPUWZ128rmik, VPCMPUWZ128rri, VPCMPUWZ128rrik, VPCM... SStream_concat0(O, "uw\t"); break; case 95: // VPCMPWZ128rmi, VPCMPWZ128rmik, VPCMPWZ128rri, VPCMPWZ128rrik, VPCMPWZ2... SStream_concat0(O, "w\t"); break; case 96: // VPERMIL2PDYmr, VPERMIL2PDmr, VPERMIL2PSYmr, VPERMIL2PSmr printOperand(MI, 7, O); SStream_concat0(O, ", "); break; case 97: // VPERMQYmi, VPERMQZ256mi, VPROLDZ256mi, VPROLQZ256mi, VPRORDZ256mi, VPR... printi256mem(MI, 1, O); break; case 98: // VPERMQZmi, VPROLDZmi, VPROLQZmi, VPRORDZmi, VPRORQZmi, VPSCATTERDDZmr,... printi512mem(MI, 1, O); break; } // Fragment 2 encoded into 6 bits for 54 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 28) & 63)); switch ((Bits >> 28) & 63) { default: // unreachable case 0: // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... return; break; case 1: // ADC32rm, ADC64rm, ADD32rm, ADD64rm, AESKEYGENASSIST128rr, AND32rm, AND... printOperand(MI, 1, O); break; case 2: // ADCX32rm, ADCX64rm, ADDSDrm, ADDSDrm_Int, ADDSSrm, ADDSSrm_Int, ADOX32... printOperand(MI, 0, O); break; case 3: // AESKEYGENASSIST128rm, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... SStream_concat0(O, ", "); break; case 4: // BLENDPDrri, BLENDPSrri, CMPPDrri, CMPPDrri_alt, CMPPSrri, CMPPSrri_alt... printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 5: // BOUNDS16rm printi32mem(MI, 1, O); return; break; case 6: // BOUNDS32rm printi64mem(MI, 1, O); return; break; case 7: // CMPPDrmi, CMPPSrmi, VCMPPDZ128rmi, VCMPPDrmi, VCMPPSZ128rmi, VCMPPSrmi... printf128mem(MI, 2, O); SStream_concat0(O, ", "); break; case 8: // CMPSB printSrcIdx8(MI, 1, O); return; break; case 9: // CMPSDrm, CMPSDrm_Int, VCMPPDZ128rmbi, VCMPPDZ256rmbi, VCMPPDZrmbi, VCM... printf64mem(MI, 2, O); break; case 10: // CMPSL printSrcIdx32(MI, 1, O); return; break; case 11: // CMPSQ printSrcIdx64(MI, 1, O); return; break; case 12: // CMPSSrm, CMPSSrm_Int, VCMPPSZ128rmbi, VCMPPSZ256rmbi, VCMPPSZrmbi, VCM... printf32mem(MI, 2, O); break; case 13: // CMPSW printSrcIdx16(MI, 1, O); return; break; case 14: // EXTRACTPSmr, VEXTRACTPSZmr, VEXTRACTPSmr printf32mem(MI, 0, O); return; break; case 15: // EXTRQI printU8Imm(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 16: // INSERTQI printU8Imm(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 17: // PEXTRBmr, RCL8mi, RCR8mi, ROL8mi, ROR8mi, SAR8mi, SHL8mi, SHR8mi, VPEX... printi8mem(MI, 0, O); return; break; case 18: // PEXTRDmr, RCL32mi, RCR32mi, ROL32mi, ROR32mi, SAR32mi, SHL32mi, SHLD32... printi32mem(MI, 0, O); return; break; case 19: // PEXTRQmr, RCL64mi, RCR64mi, ROL64mi, ROR64mi, SAR64mi, SHL64mi, SHLD64... printi64mem(MI, 0, O); return; break; case 20: // PEXTRWmr, RCL16mi, RCR16mi, ROL16mi, ROR16mi, SAR16mi, SHL16mi, SHLD16... printi16mem(MI, 0, O); return; break; case 21: // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDPSZ128rmbk, VADDPSZ25... printOperand(MI, 3, O); SStream_concat0(O, ", "); break; case 22: // VALIGNDZ128rmbi, VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNQZ256rmbi,... SStream_concat0(O, "{1to4}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_4); break; case 23: // VALIGNDZ128rmik, VALIGNDZ256rmik, VALIGNDZrmik, VALIGNQZ128rmik, VALIG... SStream_concat0(O, "}"); return; break; case 24: // VALIGNDZ128rrik, VALIGNDZ256rrik, VALIGNDZrrik, VALIGNQZ128rrik, VALIG... printOperand(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 2, O); break; case 25: // VALIGNDZ256rmbi, VALIGNDZ256rmbik, VALIGNDZ256rmbikz, VALIGNQZrmbi, VA... SStream_concat0(O, "{1to8}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_8); break; case 26: // VALIGNDZrmbi, VALIGNDZrmbik, VALIGNDZrmbikz, VCMPPSZrmbi_alt, VCMPPSZr... SStream_concat0(O, "{1to16}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_16); break; case 27: // VALIGNQZ128rmbi, VALIGNQZ128rmbik, VALIGNQZ128rmbikz, VCMPPDZ128rmbi_a... SStream_concat0(O, "{1to2}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_2); break; case 28: // VBROADCASTF32X2Z256rk, VBROADCASTF32X2Z256rkz, VBROADCASTF32X2Zrk, VBR... SStream_concat0(O, " {"); break; case 29: // VCMPPDYrmi, VCMPPDZ256rmi, VCMPPSYrmi, VCMPPSZ256rmi, VPERMIL2PDYmr, V... printf256mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 30: // VCMPPDZ128rmbik, VCMPPDZ256rmbik, VCMPPDZrmbik, VCMPSDZrm_Intk printf64mem(MI, 3, O); break; case 31: // VCMPPDZ128rmik, VCMPPSZ128rmik printf128mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}"); return; break; case 32: // VCMPPDZ256rmik, VCMPPSZ256rmik printf256mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}"); return; break; case 33: // VCMPPDZrmi, VCMPPSZrmi printf512mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 34: // VCMPPDZrmik, VCMPPSZrmik printf512mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}"); return; break; case 35: // VCMPPSZ128rmbik, VCMPPSZ256rmbik, VCMPPSZrmbik, VCMPSSZrm_Intk printf32mem(MI, 3, O); break; case 36: // VCVTPS2PHYmr, VCVTPS2PHZ256mr, VCVTPS2PHZ256mrk, VEXTRACTF128mr, VEXTR... printf128mem(MI, 0, O); break; case 37: // VCVTPS2PHZ128mr, VCVTPS2PHZ128mrk, VCVTPS2PHmr printf64mem(MI, 0, O); break; case 38: // VCVTPS2PHZmr, VCVTPS2PHZmrk, VEXTRACTF32x8Zmr, VEXTRACTF32x8Zmrk, VEXT... printf256mem(MI, 0, O); break; case 39: // VEXTRACTI128mr, VEXTRACTI32x4Z256mr, VEXTRACTI32x4Z256mrk, VEXTRACTI32... printi128mem(MI, 0, O); break; case 40: // VEXTRACTI32x8Zmr, VEXTRACTI32x8Zmrk, VEXTRACTI64x4Zmr, VEXTRACTI64x4Zm... printi256mem(MI, 0, O); break; case 41: // VFIXUPIMMPDZ128rmikz, VFIXUPIMMPDZ256rmikz, VFIXUPIMMPDZrmikz, VFIXUPI... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; break; case 42: // VPCMPBZ128rmi, VPCMPDZ128rmi, VPCMPQZ128rmi, VPCMPUBZ128rmi, VPCMPUDZ1... printi128mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 43: // VPCMPBZ128rmik, VPCMPDZ128rmik, VPCMPQZ128rmik, VPCMPUBZ128rmik, VPCMP... printi128mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}"); return; break; case 44: // VPCMPBZ256rmi, VPCMPDZ256rmi, VPCMPQZ256rmi, VPCMPUBZ256rmi, VPCMPUDZ2... printi256mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 45: // VPCMPBZ256rmik, VPCMPDZ256rmik, VPCMPQZ256rmik, VPCMPUBZ256rmik, VPCMP... printi256mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}"); return; break; case 46: // VPCMPBZrmi, VPCMPDZrmi, VPCMPQZrmi, VPCMPUBZrmi, VPCMPUDZrmi, VPCMPUQZ... printi512mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 47: // VPCMPBZrmik, VPCMPDZrmik, VPCMPQZrmik, VPCMPUBZrmik, VPCMPUDZrmik, VPC... printi512mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}"); return; break; case 48: // VPCMPDZ128rmib, VPCMPDZ256rmib, VPCMPDZrmib, VPCMPUDZ128rmib, VPCMPUDZ... printi32mem(MI, 2, O); break; case 49: // VPCMPDZ128rmibk, VPCMPDZ256rmibk, VPCMPDZrmibk, VPCMPUDZ128rmibk, VPCM... printi32mem(MI, 3, O); break; case 50: // VPCMPQZ128rmib, VPCMPQZ256rmib, VPCMPQZrmib, VPCMPUQZ128rmib, VPCMPUQZ... printi64mem(MI, 2, O); break; case 51: // VPCMPQZ128rmibk, VPCMPQZ256rmibk, VPCMPQZrmibk, VPCMPUQZ128rmibk, VPCM... printi64mem(MI, 3, O); break; case 52: // XADD16rm, XCHG16rm printi16mem(MI, 2, O); return; break; case 53: // XADD8rm, XCHG8rm printi8mem(MI, 2, O); return; break; } // Fragment 3 encoded into 4 bits for 15 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 34) & 15)); switch ((Bits >> 34) & 15) { default: // unreachable case 0: // ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADD32rm, ADD64rm, ADDSDrm, ADDSD... return; break; case 1: // AESKEYGENASSIST128rm, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... printOperand(MI, 0, O); break; case 2: // AESKEYGENASSIST128rr, ANDN32rm, ANDN64rm, CMPSDrm, CMPSDrm_Int, CMPSSr... SStream_concat0(O, ", "); break; case 3: // VALIGNDZ128rmbi, VALIGNDZ128rri, VALIGNDZ256rmbi, VALIGNDZ256rri, VALI... printOperand(MI, 1, O); break; case 4: // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VALIGNQZ128rmbik, V... printOperand(MI, 3, O); break; case 5: // VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbikz, VALIGNDZ256rri... printOperand(MI, 2, O); break; case 6: // VALIGNDZ128rrik, VALIGNDZ256rrik, VALIGNDZrrik, VALIGNQZ128rrik, VALIG... SStream_concat0(O, "}"); return; break; case 7: // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Z256mkz, VBROADCASTF32X2Zmk, VBR... SStream_concat0(O, " {"); break; case 8: // VCMPPDZ128rmbi, VCMPPDZ128rmbik, VPCMPQZ128rmib, VPCMPQZ128rmibk, VPCM... SStream_concat0(O, "{1to2}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_2); break; case 9: // VCMPPDZ256rmbi, VCMPPDZ256rmbik, VCMPPSZ128rmbi, VCMPPSZ128rmbik, VPCM... SStream_concat0(O, "{1to4}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_4); break; case 10: // VCMPPDZrmbi, VCMPPDZrmbik, VCMPPSZ256rmbi, VCMPPSZ256rmbik, VPCMPDZ256... SStream_concat0(O, "{1to8}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_8); break; case 11: // VCMPPSZrmbi, VCMPPSZrmbik, VPCMPDZrmib, VPCMPDZrmibk, VPCMPUDZrmib, VP... SStream_concat0(O, "{1to16}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_16); break; case 12: // VCOMPRESSPDZ128mrk, VCOMPRESSPDZ256mrk, VCOMPRESSPDZmrk, VCOMPRESSPSZ1... printOperand(MI, 5, O); SStream_concat0(O, "}"); return; break; case 13: // VFIXUPIMMPDZ128rrikz, VFIXUPIMMPDZ256rrikz, VFIXUPIMMPDZrribkz, VFIXUP... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; break; case 14: // VPSCATTERDDZ128mr, VPSCATTERDDZ256mr, VPSCATTERDDZmr, VPSCATTERDQZ128m... printOperand(MI, 6, O); SStream_concat0(O, "}"); return; break; } // Fragment 4 encoded into 4 bits for 10 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 38) & 15)); switch ((Bits >> 38) & 15) { default: // unreachable case 0: // AESKEYGENASSIST128rm, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... return; break; case 1: // AESKEYGENASSIST128rr, ANDN32rm, ANDN64rm, CMPSDrm, CMPSDrm_Int, CMPSSr... printOperand(MI, 0, O); return; break; case 2: // VADDPDZ128rmbk, VADDPDZ128rmbkz, VADDPDZ128rmkz, VADDPDZ128rrkz, VADDP... SStream_concat0(O, " {"); break; case 3: // VALIGNDZ128rmbi, VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNDZ128rri, ... SStream_concat0(O, ", "); break; case 4: // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Zmk, VBROADCASTI32X2Z128mk, VBRO... printOperand(MI, 2, O); break; case 5: // VBROADCASTF32X2Z256mkz, VBROADCASTF32X2Zmkz, VBROADCASTI32X2Z128mkz, V... printOperand(MI, 1, O); break; case 6: // VBROADCASTF32X2Z256rk, VBROADCASTF32X2Zrk, VBROADCASTF32X4Z256rmk, VBR... SStream_concat0(O, "}"); return; break; case 7: // VBROADCASTF32X2Z256rkz, VBROADCASTF32X2Zrkz, VBROADCASTF32X4Z256rmkz, ... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; break; case 8: // VCVTPS2PHZ128mrk, VCVTPS2PHZ256mrk, VCVTPS2PHZmrk, VEXTRACTF32x4Z256mr... printOperand(MI, 5, O); SStream_concat0(O, "}"); return; break; case 9: // VGATHERQPSZ128rm, VPGATHERQDZ128rm printOperand(MI, 3, O); SStream_concat0(O, "}"); return; break; } // Fragment 5 encoded into 3 bits for 6 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 7)); switch ((Bits >> 42) & 7) { default: // unreachable case 0: // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDPSZ128rmbk, VADDPSZ25... printOperand(MI, 2, O); break; case 1: // VADDPDZ128rmbkz, VADDPDZ128rmkz, VADDPDZ128rrkz, VADDPDZ256rmbkz, VADD... printOperand(MI, 1, O); break; case 2: // VALIGNDZ128rmbi, VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNDZ128rri, ... printOperand(MI, 0, O); break; case 3: // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Zmk, VBROADCASTI32X2Z128mk, VBRO... SStream_concat0(O, "}"); return; break; case 4: // VBROADCASTF32X2Z256mkz, VBROADCASTF32X2Zmkz, VBROADCASTI32X2Z128mkz, V... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; break; case 5: // VCMPPDZ128rmbi, VCMPPDZ128rmbik, VCMPPDZ256rmbi, VCMPPDZ256rmbik, VCMP... SStream_concat0(O, ", "); printOperand(MI, 0, O); break; } // Fragment 6 encoded into 3 bits for 5 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 45) & 7)); switch ((Bits >> 45) & 7) { default: // unreachable case 0: // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDPSZ128rmbk, VADDPSZ25... SStream_concat0(O, "}"); return; break; case 1: // VADDPDZ128rmbkz, VADDPDZ128rmkz, VADDPDZ128rrkz, VADDPDZ256rmbkz, VADD... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; break; case 2: // VALIGNDZ128rmbi, VALIGNDZ128rri, VALIGNDZ256rmbi, VALIGNDZ256rri, VALI... return; break; case 3: // VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbi... SStream_concat0(O, " {"); break; case 4: // VPERMIL2PDYrr, VPERMIL2PDYrr_REV, VPERMIL2PDrr, VPERMIL2PDrr_REV, VPER... SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; } // Fragment 7 encoded into 1 bits for 2 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 48) & 1)); if ((Bits >> 48) & 1) { // VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbikz, VALIGNDZ256rri... printOperand(MI, 1, O); } else { // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VALIGNQZ128rmbik, V... printOperand(MI, 2, O); } // Fragment 8 encoded into 1 bits for 2 unique commands. // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 49) & 1)); if ((Bits >> 49) & 1) { // VALIGNDZ128rmbikz, VALIGNDZ128rrikz, VALIGNDZ256rmbikz, VALIGNDZ256rri... SStream_concat0(O, "} {z}"); op_addAvxZeroOpmask(MI); return; } else { // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VALIGNQZ128rmbik, V... SStream_concat0(O, "}"); return; } } capstone-sys-0.15.0/capstone/arch/X86/X86GenAsmWriter1.inc000064400000000000000000037652770072674642500211710ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '0', 9, 0, /* 12 */ 's', 'h', 'a', '1', 'm', 's', 'g', '1', 9, 0, /* 22 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '1', 9, 0, /* 34 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '1', 9, 0, /* 46 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '1', 9, 0, /* 56 */ 'p', 'f', 'r', 's', 'q', 'i', 't', '1', 9, 0, /* 66 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 't', '1', 9, 0, /* 79 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '3', '2', 9, 0, /* 90 */ 'c', 'r', 'c', '3', '2', 9, 0, /* 97 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 9, 0, /* 108 */ 's', 'h', 'a', '1', 'm', 's', 'g', '2', 9, 0, /* 118 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '2', 9, 0, /* 130 */ 's', 'h', 'a', '2', '5', '6', 'r', 'n', 'd', 's', '2', 9, 0, /* 143 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '2', 9, 0, /* 155 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '2', 9, 0, /* 165 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '2', 9, 0, /* 182 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '2', 9, 0, /* 199 */ 'v', 's', 'h', 'u', 'f', 'f', '6', '4', 'x', '2', 9, 0, /* 211 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '2', 9, 0, /* 226 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '2', 9, 0, /* 240 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '2', 9, 0, /* 257 */ 'v', 's', 'h', 'u', 'f', 'i', '6', '4', 'x', '2', 9, 0, /* 269 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '2', 9, 0, /* 284 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '2', 9, 0, /* 298 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '2', 9, 0, /* 315 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '6', '4', 9, 0, /* 326 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, /* 336 */ 'f', 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, /* 346 */ 'f', 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, /* 357 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, /* 367 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, /* 378 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, /* 390 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 9, 0, /* 401 */ 's', 'h', 'a', '1', 'r', 'n', 'd', 's', '4', 9, 0, /* 412 */ 'v', 's', 'h', 'u', 'f', 'f', '3', '2', 'x', '4', 9, 0, /* 424 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '4', 9, 0, /* 439 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '4', 9, 0, /* 453 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '4', 9, 0, /* 470 */ 'v', 's', 'h', 'u', 'f', 'i', '3', '2', 'x', '4', 9, 0, /* 482 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '4', 9, 0, /* 497 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '4', 9, 0, /* 511 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 9, 0, /* 528 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '4', 9, 0, /* 543 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '4', 9, 0, /* 557 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '6', '4', 'x', '4', 9, 0, /* 574 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '4', 9, 0, /* 589 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '4', 9, 0, /* 603 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 9, 0, /* 620 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '1', '6', 9, 0, /* 631 */ 'v', 'p', 'e', 'r', 'm', '2', 'f', '1', '2', '8', 9, 0, /* 643 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '1', '2', '8', 9, 0, /* 657 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '1', '2', '8', 9, 0, /* 670 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '1', '2', '8', 9, 0, /* 686 */ 'v', 'p', 'e', 'r', 'm', '2', 'i', '1', '2', '8', 9, 0, /* 698 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '1', '2', '8', 9, 0, /* 712 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '1', '2', '8', 9, 0, /* 725 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '1', '2', '8', 9, 0, /* 741 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '8', 9, 0, /* 751 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '8', 9, 0, /* 766 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '8', 9, 0, /* 780 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '3', '2', 'x', '8', 9, 0, /* 797 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '8', 9, 0, /* 812 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '8', 9, 0, /* 826 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '8', 9, 0, /* 843 */ 'l', 'e', 'a', 9, 0, /* 848 */ 'j', 'a', 9, 0, /* 852 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 'a', 9, 0, /* 863 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', 9, 0, /* 872 */ 's', 'e', 't', 'a', 9, 0, /* 878 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'n', 't', 'a', 9, 0, /* 891 */ 'c', 'm', 'o', 'v', 'a', 9, 0, /* 898 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'b', 9, 0, /* 908 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'b', 9, 0, /* 918 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'b', 9, 0, /* 928 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, /* 939 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, /* 951 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, /* 962 */ 'v', 'p', 's', 'h', 'a', 'b', 9, 0, /* 970 */ 's', 'b', 'b', 9, 0, /* 975 */ 'v', 'p', 's', 'u', 'b', 'b', 9, 0, /* 983 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 991 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 999 */ 'k', 'a', 'd', 'd', 'b', 9, 0, /* 1006 */ 'v', 'p', 'a', 'd', 'd', 'b', 9, 0, /* 1014 */ 'k', 'a', 'n', 'd', 'b', 9, 0, /* 1021 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'b', 9, 0, /* 1032 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'b', 9, 0, /* 1043 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'b', 9, 0, /* 1053 */ 'v', 'p', 'm', 'o', 'v', 'd', 'b', 9, 0, /* 1062 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 9, 0, /* 1071 */ 'v', 'p', 'a', 'v', 'g', 'b', 9, 0, /* 1079 */ 'j', 'b', 9, 0, /* 1083 */ 'v', 'p', 'm', 'o', 'v', 'm', 's', 'k', 'b', 9, 0, /* 1094 */ 'v', 'p', 's', 'h', 'l', 'b', 9, 0, /* 1102 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'b', 9, 0, /* 1112 */ 'v', 'g', 'f', '2', 'p', '8', 'm', 'u', 'l', 'b', 9, 0, /* 1124 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'b', 9, 0, /* 1135 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'b', 9, 0, /* 1146 */ 'v', 'p', 'c', 'o', 'm', 'b', 9, 0, /* 1154 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 'i', 't', 'q', 'm', 'b', 9, 0, /* 1168 */ 'v', 'p', 'e', 'r', 'm', 'b', 9, 0, /* 1176 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'b', 9, 0, /* 1186 */ 'k', 'a', 'n', 'd', 'n', 'b', 9, 0, /* 1194 */ 'v', 'p', 's', 'i', 'g', 'n', 'b', 9, 0, /* 1203 */ 'v', 'p', 'c', 'm', 'p', 'b', 9, 0, /* 1211 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'q', 'b', 9, 0, /* 1227 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'b', 9, 0, /* 1237 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'b', 9, 0, /* 1248 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'b', 9, 0, /* 1258 */ 'v', 'p', 'm', 'u', 'l', 't', 'i', 's', 'h', 'i', 'f', 't', 'q', 'b', 9, 0, /* 1274 */ 'v', 'g', 'f', '2', 'p', '8', 'a', 'f', 'f', 'i', 'n', 'e', 'i', 'n', 'v', 'q', 'b', 9, 0, /* 1293 */ 'v', 'p', 'm', 'o', 'v', 'q', 'b', 9, 0, /* 1302 */ 'k', 'o', 'r', 'b', 9, 0, /* 1308 */ 'k', 'x', 'n', 'o', 'r', 'b', 9, 0, /* 1316 */ 'k', 'x', 'o', 'r', 'b', 9, 0, /* 1323 */ 'v', 'p', 'i', 'n', 's', 'r', 'b', 9, 0, /* 1332 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'b', 9, 0, /* 1342 */ 'v', 'p', 'e', 'x', 't', 'r', 'b', 9, 0, /* 1351 */ 'v', 'p', 'a', 'b', 's', 'b', 9, 0, /* 1359 */ 'v', 'p', 's', 'u', 'b', 's', 'b', 9, 0, /* 1368 */ 'v', 'p', 'a', 'd', 'd', 's', 'b', 9, 0, /* 1377 */ 'v', 'p', 'm', 'i', 'n', 's', 'b', 9, 0, /* 1386 */ 's', 't', 'o', 's', 'b', 9, 0, /* 1393 */ 'c', 'm', 'p', 's', 'b', 9, 0, /* 1400 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'b', 9, 0, /* 1413 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'b', 9, 0, /* 1423 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'b', 9, 0, /* 1433 */ 'p', 'a', 'v', 'g', 'u', 's', 'b', 9, 0, /* 1442 */ 'm', 'o', 'v', 's', 'b', 9, 0, /* 1449 */ 'v', 'p', 'm', 'a', 'x', 's', 'b', 9, 0, /* 1458 */ 's', 'e', 't', 'b', 9, 0, /* 1464 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'b', 9, 0, /* 1474 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'b', 9, 0, /* 1484 */ 'k', 'n', 'o', 't', 'b', 9, 0, /* 1491 */ 'v', 'p', 'r', 'o', 't', 'b', 9, 0, /* 1499 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'b', 9, 0, /* 1513 */ 'k', 't', 'e', 's', 't', 'b', 9, 0, /* 1521 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'b', 9, 0, /* 1531 */ 'v', 'p', 'c', 'o', 'm', 'u', 'b', 9, 0, /* 1540 */ 'v', 'p', 'm', 'i', 'n', 'u', 'b', 9, 0, /* 1549 */ 'v', 'p', 'c', 'm', 'p', 'u', 'b', 9, 0, /* 1558 */ 'p', 'f', 's', 'u', 'b', 9, 0, /* 1565 */ 'f', 'i', 's', 'u', 'b', 9, 0, /* 1572 */ 'v', 'p', 'm', 'a', 'x', 'u', 'b', 9, 0, /* 1581 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, 0, /* 1592 */ 'c', 'm', 'o', 'v', 'b', 9, 0, /* 1599 */ 'k', 'm', 'o', 'v', 'b', 9, 0, /* 1606 */ 'c', 'l', 'w', 'b', 9, 0, /* 1612 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'w', 'b', 9, 0, /* 1623 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'w', 'b', 9, 0, /* 1634 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'w', 'b', 9, 0, /* 1645 */ 'v', 'p', 'm', 'o', 'v', 's', 'w', 'b', 9, 0, /* 1655 */ 'v', 'p', 'm', 'o', 'v', 'w', 'b', 9, 0, /* 1664 */ 'p', 'f', 'a', 'c', 'c', 9, 0, /* 1671 */ 'p', 'f', 'n', 'a', 'c', 'c', 9, 0, /* 1679 */ 'p', 'f', 'p', 'n', 'a', 'c', 'c', 9, 0, /* 1688 */ 'a', 'd', 'c', 9, 0, /* 1693 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 9, 0, /* 1702 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, /* 1710 */ 'b', 'l', 'c', 'i', 'c', 9, 0, /* 1717 */ 'b', 'l', 's', 'i', 'c', 9, 0, /* 1724 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, /* 1732 */ 'v', 'a', 'e', 's', 'i', 'm', 'c', 9, 0, /* 1741 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 9, 0, /* 1750 */ 'i', 'n', 'c', 9, 0, /* 1755 */ 'b', 't', 'c', 9, 0, /* 1760 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'd', 9, 0, /* 1770 */ 'v', 'p', 'm', 'o', 'v', 'm', '2', 'd', 9, 0, /* 1780 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'd', 9, 0, /* 1790 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'w', '2', 'd', 9, 0, /* 1807 */ 'a', 'a', 'd', 9, 0, /* 1812 */ 'v', 'm', 'r', 'e', 'a', 'd', 9, 0, /* 1820 */ 'v', 'p', 's', 'h', 'a', 'd', 9, 0, /* 1828 */ 'v', 'p', 's', 'r', 'a', 'd', 9, 0, /* 1836 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'd', 9, 0, /* 1846 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'd', 9, 0, /* 1857 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 9, 0, /* 1866 */ 'v', 'p', 's', 'u', 'b', 'd', 9, 0, /* 1874 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 9, 0, /* 1885 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 9, 0, /* 1896 */ 'p', 'f', 'a', 'd', 'd', 9, 0, /* 1903 */ 'f', 'i', 'a', 'd', 'd', 9, 0, /* 1910 */ 'x', 'a', 'd', 'd', 9, 0, /* 1916 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 9, 0, /* 1925 */ 'k', 'a', 'd', 'd', 'd', 9, 0, /* 1932 */ 'v', 'p', 'a', 'd', 'd', 'd', 9, 0, /* 1940 */ 'v', 'p', 's', 'h', 'l', 'd', 'd', 9, 0, /* 1949 */ 'k', 'a', 'n', 'd', 'd', 9, 0, /* 1956 */ 'v', 'p', 'a', 'n', 'd', 'd', 9, 0, /* 1964 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'd', 9, 0, /* 1975 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'd', 9, 0, /* 1985 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 9, 0, /* 1997 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'd', 9, 0, /* 2010 */ 'v', 'p', 's', 'h', 'r', 'd', 'd', 9, 0, /* 2019 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'd', 9, 0, /* 2029 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'd', 9, 0, /* 2040 */ 'r', 'd', 's', 'e', 'e', 'd', 9, 0, /* 2048 */ 'p', 'i', '2', 'f', 'd', 9, 0, /* 2055 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 9, 0, /* 2064 */ 'v', 'p', 't', 'e', 'r', 'n', 'l', 'o', 'g', 'd', 9, 0, /* 2076 */ 'p', 'f', '2', 'i', 'd', 9, 0, /* 2083 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, /* 2092 */ 'r', 'd', 'p', 'i', 'd', 9, 0, /* 2099 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, /* 2108 */ 'f', 'l', 'd', 9, 0, /* 2113 */ 'v', 'p', 's', 'h', 'l', 'd', 9, 0, /* 2121 */ 'f', 'i', 'l', 'd', 9, 0, /* 2127 */ 'v', 'p', 's', 'l', 'l', 'd', 9, 0, /* 2135 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 9, 0, /* 2144 */ 'v', 'p', 'r', 'o', 'l', 'd', 9, 0, /* 2152 */ 'v', 'p', 's', 'r', 'l', 'd', 9, 0, /* 2160 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, /* 2169 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'd', 9, 0, /* 2179 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'd', 9, 0, /* 2190 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'd', 9, 0, /* 2201 */ 'v', 'p', 'c', 'o', 'm', 'd', 9, 0, /* 2209 */ 'v', 'p', 'e', 'r', 'm', 'd', 9, 0, /* 2217 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'd', 9, 0, /* 2227 */ 'v', 'p', 'a', 'n', 'd', 9, 0, /* 2234 */ 'r', 'd', 'r', 'a', 'n', 'd', 9, 0, /* 2242 */ 'k', 'a', 'n', 'd', 'n', 'd', 9, 0, /* 2250 */ 'v', 'p', 'a', 'n', 'd', 'n', 'd', 9, 0, /* 2259 */ 'v', 'a', 'l', 'i', 'g', 'n', 'd', 9, 0, /* 2268 */ 'v', 'p', 's', 'i', 'g', 'n', 'd', 9, 0, /* 2277 */ 'b', 'o', 'u', 'n', 'd', 9, 0, /* 2284 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, /* 2300 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, /* 2313 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, /* 2327 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, /* 2343 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, /* 2356 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, /* 2370 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, /* 2386 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, /* 2399 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, /* 2413 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, /* 2429 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, /* 2442 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, /* 2456 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 'd', 9, 0, /* 2467 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 'd', 9, 0, /* 2477 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 'd', 9, 0, /* 2489 */ 'v', 'e', 'x', 'p', '2', 'p', 'd', 9, 0, /* 2498 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 9, 0, /* 2509 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 'd', 9, 0, /* 2521 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 'd', 9, 0, /* 2532 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 'd', 9, 0, /* 2544 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, 0, /* 2555 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 'd', 9, 0, /* 2566 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, /* 2582 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, /* 2595 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, /* 2609 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, /* 2625 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, /* 2638 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, /* 2652 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 'd', 9, 0, /* 2662 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 'd', 9, 0, /* 2674 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 9, 0, /* 2684 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 9, 0, /* 2696 */ 'v', 'm', 'o', 'v', 'a', 'p', 'd', 9, 0, /* 2705 */ 'p', 's', 'w', 'a', 'p', 'd', 9, 0, /* 2713 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2726 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2737 */ 'v', 'h', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2746 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2756 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2767 */ 'v', 's', 'u', 'b', 'p', 'd', 9, 0, /* 2775 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2788 */ 'v', 'h', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2797 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2807 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2818 */ 'v', 'a', 'd', 'd', 'p', 'd', 9, 0, /* 2826 */ 'v', 'e', 'x', 'p', 'a', 'n', 'd', 'p', 'd', 9, 0, /* 2837 */ 'v', 'a', 'n', 'd', 'p', 'd', 9, 0, /* 2845 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 'd', 9, 0, /* 2855 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 'd', 9, 0, /* 2865 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 9, 0, /* 2877 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 'd', 9, 0, /* 2890 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 'p', 'd', 9, 0, /* 2901 */ 'v', 'r', 'a', 'n', 'g', 'e', 'p', 'd', 9, 0, /* 2911 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 'd', 9, 0, /* 2924 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 'p', 'd', 9, 0, /* 2935 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 9, 0, /* 2944 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 'd', 9, 0, /* 2955 */ 'v', 'm', 'o', 'v', 'h', 'p', 'd', 9, 0, /* 2964 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 'd', 9, 0, /* 2975 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 9, 0, /* 2986 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 'd', 9, 0, /* 2997 */ 'v', 'm', 'u', 'l', 'p', 'd', 9, 0, /* 3005 */ 'v', 'm', 'o', 'v', 'l', 'p', 'd', 9, 0, /* 3014 */ 'v', 'p', 'c', 'm', 'p', 'd', 9, 0, /* 3022 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 'd', 9, 0, /* 3033 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 'd', 9, 0, /* 3046 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 9, 0, /* 3055 */ 'v', 'a', 'n', 'd', 'n', 'p', 'd', 9, 0, /* 3064 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, 0, /* 3072 */ 'v', 'd', 'p', 'p', 'd', 9, 0, /* 3079 */ 'v', 'c', 'm', 'p', 'p', 'd', 9, 0, /* 3087 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 'd', 9, 0, /* 3098 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 9, 0, /* 3110 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 'd', 9, 0, /* 3123 */ 'v', 'o', 'r', 'p', 'd', 9, 0, /* 3130 */ 'v', 'x', 'o', 'r', 'p', 'd', 9, 0, /* 3138 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 'd', 9, 0, /* 3150 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, /* 3159 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, /* 3167 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 'd', 9, 0, /* 3180 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 'd', 9, 0, /* 3192 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 'd', 9, 0, /* 3202 */ 'v', 's', 'q', 'r', 't', 'p', 'd', 9, 0, /* 3211 */ 'v', 't', 'e', 's', 't', 'p', 'd', 9, 0, /* 3220 */ 'v', 'm', 'o', 'v', 'u', 'p', 'd', 9, 0, /* 3229 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, 0, /* 3240 */ 'v', 'd', 'i', 'v', 'p', 'd', 9, 0, /* 3248 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 'd', 9, 0, /* 3260 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, 0, /* 3268 */ 'v', 'f', 'r', 'c', 'z', 'p', 'd', 9, 0, /* 3277 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'd', 9, 0, /* 3287 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 9, 0, /* 3299 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'd', 9, 0, /* 3312 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'd', 9, 0, /* 3323 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'd', 9, 0, /* 3333 */ 'v', 'p', 'm', 'o', 'v', 'q', 'd', 9, 0, /* 3342 */ 's', 'h', 'r', 'd', 9, 0, /* 3348 */ 'k', 'o', 'r', 'd', 9, 0, /* 3354 */ 'k', 'x', 'n', 'o', 'r', 'd', 9, 0, /* 3362 */ 'v', 'p', 'o', 'r', 'd', 9, 0, /* 3369 */ 'v', 'p', 'r', 'o', 'r', 'd', 9, 0, /* 3377 */ 'k', 'x', 'o', 'r', 'd', 9, 0, /* 3384 */ 'v', 'p', 'x', 'o', 'r', 'd', 9, 0, /* 3392 */ 'v', 'p', 'i', 'n', 's', 'r', 'd', 9, 0, /* 3401 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'd', 9, 0, /* 3411 */ 'v', 'p', 'e', 'x', 't', 'r', 'd', 9, 0, /* 3420 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, /* 3433 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, /* 3447 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, /* 3460 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, /* 3474 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, /* 3487 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, /* 3501 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, /* 3514 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, /* 3528 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 9, 0, /* 3539 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 9, 0, /* 3551 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, 0, /* 3562 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, /* 3575 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, /* 3589 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, /* 3602 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, /* 3616 */ 'v', 'r', 'c', 'p', '1', '4', 's', 'd', 9, 0, /* 3626 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 'd', 9, 0, /* 3638 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 9, 0, /* 3648 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 9, 0, /* 3660 */ 'v', 'p', 'a', 'b', 's', 'd', 9, 0, /* 3668 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 'd', 9, 0, /* 3678 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 'd', 9, 0, /* 3689 */ 'v', 's', 'u', 'b', 's', 'd', 9, 0, /* 3697 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, /* 3707 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, /* 3718 */ 'v', 'a', 'd', 'd', 's', 'd', 9, 0, /* 3726 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 'd', 9, 0, /* 3736 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 'd', 9, 0, /* 3747 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 'd', 9, 0, /* 3757 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 'd', 9, 0, /* 3770 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 'd', 9, 0, /* 3781 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, /* 3791 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, /* 3800 */ 'v', 'm', 'u', 'l', 's', 'd', 9, 0, /* 3808 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 'd', 9, 0, /* 3821 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 9, 0, /* 3830 */ 'v', 'm', 'i', 'n', 's', 'd', 9, 0, /* 3838 */ 's', 't', 'o', 's', 'd', 9, 0, /* 3845 */ 'v', 'c', 'm', 'p', 's', 'd', 9, 0, /* 3853 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 'd', 9, 0, /* 3864 */ 'v', 'p', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'd', 9, 0, /* 3877 */ 'w', 'r', 's', 's', 'd', 9, 0, /* 3884 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 'd', 9, 0, /* 3896 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, /* 3904 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 9, 0, /* 3915 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 9, 0, /* 3925 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 'd', 9, 0, /* 3937 */ 'm', 'o', 'v', 'n', 't', 's', 'd', 9, 0, /* 3946 */ 'v', 's', 'q', 'r', 't', 's', 'd', 9, 0, /* 3955 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 9, 0, /* 3969 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 9, 0, /* 3979 */ 'v', 'd', 'i', 'v', 's', 'd', 9, 0, /* 3987 */ 'v', 'm', 'o', 'v', 's', 'd', 9, 0, /* 3995 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 9, 0, /* 4004 */ 'v', 'm', 'a', 'x', 's', 'd', 9, 0, /* 4012 */ 'v', 'f', 'r', 'c', 'z', 's', 'd', 9, 0, /* 4021 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'd', 9, 0, /* 4034 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'd', 9, 0, /* 4044 */ 'v', 'p', 'o', 'p', 'c', 'n', 't', 'd', 9, 0, /* 4054 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'd', 9, 0, /* 4064 */ 'k', 'n', 'o', 't', 'd', 9, 0, /* 4071 */ 'v', 'p', 'r', 'o', 't', 'd', 9, 0, /* 4079 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 9, 0, /* 4093 */ 'k', 't', 'e', 's', 't', 'd', 9, 0, /* 4101 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'd', 9, 0, /* 4111 */ 'v', 'p', 'c', 'o', 'm', 'u', 'd', 9, 0, /* 4120 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 9, 0, /* 4129 */ 'v', 'p', 'c', 'm', 'p', 'u', 'd', 9, 0, /* 4138 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 9, 0, /* 4147 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 9, 0, /* 4156 */ 'v', 'p', 's', 'h', 'l', 'd', 'v', 'd', 9, 0, /* 4166 */ 'v', 'p', 's', 'h', 'r', 'd', 'v', 'd', 9, 0, /* 4176 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 9, 0, /* 4185 */ 'v', 'p', 'r', 'o', 'l', 'v', 'd', 9, 0, /* 4194 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 9, 0, /* 4203 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 9, 0, /* 4215 */ 'v', 'm', 'o', 'v', 'd', 9, 0, /* 4222 */ 'v', 'p', 'r', 'o', 'r', 'v', 'd', 9, 0, /* 4231 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 'd', 9, 0, /* 4241 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'd', 9, 0, /* 4251 */ 'v', 'p', 'm', 'a', 'd', 'd', 'w', 'd', 9, 0, /* 4261 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'w', 'd', 9, 0, /* 4273 */ 'k', 'u', 'n', 'p', 'c', 'k', 'w', 'd', 9, 0, /* 4283 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'w', 'd', 9, 0, /* 4295 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'd', 9, 0, /* 4305 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 'w', 'd', 9, 0, /* 4316 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'd', 9, 0, /* 4327 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 's', 'w', 'd', 9, 0, /* 4339 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'd', 9, 0, /* 4350 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 9, 0, /* 4361 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 9, 0, /* 4372 */ 'm', 'o', 'v', 's', 'x', 'd', 9, 0, /* 4380 */ 'j', 'a', 'e', 9, 0, /* 4385 */ 's', 'e', 't', 'a', 'e', 9, 0, /* 4392 */ 'c', 'm', 'o', 'v', 'a', 'e', 9, 0, /* 4400 */ 'j', 'b', 'e', 9, 0, /* 4405 */ 's', 'e', 't', 'b', 'e', 9, 0, /* 4412 */ 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, /* 4420 */ 'f', 's', 't', 'p', 'n', 'c', 'e', 9, 0, /* 4429 */ 'f', 'f', 'r', 'e', 'e', 9, 0, /* 4436 */ 'j', 'g', 'e', 9, 0, /* 4441 */ 'p', 'f', 'c', 'm', 'p', 'g', 'e', 9, 0, /* 4450 */ 's', 'e', 't', 'g', 'e', 9, 0, /* 4457 */ 'c', 'm', 'o', 'v', 'g', 'e', 9, 0, /* 4465 */ 'j', 'e', 9, 0, /* 4469 */ 'j', 'l', 'e', 9, 0, /* 4474 */ 's', 'e', 't', 'l', 'e', 9, 0, /* 4481 */ 'c', 'm', 'o', 'v', 'l', 'e', 9, 0, /* 4489 */ 'j', 'n', 'e', 9, 0, /* 4494 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, /* 4502 */ 's', 'e', 't', 'n', 'e', 9, 0, /* 4509 */ 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, /* 4517 */ 'l', 'o', 'o', 'p', 'e', 9, 0, /* 4524 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 9, 0, /* 4534 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 9, 0, /* 4544 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 9, 0, /* 4554 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 9, 0, /* 4564 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, /* 4572 */ 's', 'e', 't', 'e', 9, 0, /* 4578 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 9, 0, /* 4587 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 9, 0, /* 4596 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, /* 4606 */ 's', 'h', 'a', '1', 'n', 'e', 'x', 't', 'e', 9, 0, /* 4617 */ 'f', 'n', 's', 'a', 'v', 'e', 9, 0, /* 4625 */ 'f', 'x', 's', 'a', 'v', 'e', 9, 0, /* 4633 */ 'c', 'm', 'o', 'v', 'e', 9, 0, /* 4640 */ 'b', 's', 'f', 9, 0, /* 4645 */ 'r', 'e', 't', 'f', 9, 0, /* 4651 */ 'n', 'e', 'g', 9, 0, /* 4656 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 9, 0, /* 4665 */ 'j', 'g', 9, 0, /* 4669 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, /* 4677 */ 's', 'e', 't', 'g', 9, 0, /* 4683 */ 'c', 'm', 'o', 'v', 'g', 9, 0, /* 4690 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 9, 0, /* 4700 */ 'f', 'x', 'c', 'h', 9, 0, /* 4706 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 9, 0, /* 4717 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'h', 9, 0, /* 4728 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'h', 9, 0, /* 4740 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 9, 0, /* 4749 */ 'p', 'u', 's', 'h', 9, 0, /* 4755 */ 'b', 'l', 'c', 'i', 9, 0, /* 4761 */ 'b', 'z', 'h', 'i', 9, 0, /* 4767 */ 'f', 'c', 'o', 'm', 'i', 9, 0, /* 4774 */ 'f', 'u', 'c', 'o', 'm', 'i', 9, 0, /* 4782 */ 'c', 'v', 't', 't', 'p', 'd', '2', 'p', 'i', 9, 0, /* 4793 */ 'c', 'v', 't', 'p', 'd', '2', 'p', 'i', 9, 0, /* 4803 */ 'c', 'v', 't', 't', 'p', 's', '2', 'p', 'i', 9, 0, /* 4814 */ 'c', 'v', 't', 'p', 's', '2', 'p', 'i', 9, 0, /* 4824 */ 'f', 'c', 'o', 'm', 'p', 'i', 9, 0, /* 4832 */ 'f', 'u', 'c', 'o', 'm', 'p', 'i', 9, 0, /* 4841 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, /* 4850 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'i', 9, 0, /* 4862 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'i', 9, 0, /* 4874 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, 0, /* 4886 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 9, 0, /* 4897 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 9, 0, /* 4909 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 9, 0, /* 4920 */ 'b', 'l', 's', 'i', 9, 0, /* 4926 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 'u', 's', 'i', 9, 0, /* 4939 */ 'v', 'c', 'v', 't', 's', 'd', '2', 'u', 's', 'i', 9, 0, /* 4951 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 'u', 's', 'i', 9, 0, /* 4964 */ 'v', 'c', 'v', 't', 's', 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5822 */ 'v', 'p', 'a', 'n', 'd', 'q', 9, 0, /* 5830 */ 'v', 'p', 'e', 'x', 'p', 'a', 'n', 'd', 'q', 9, 0, /* 5841 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 9, 0, /* 5854 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 9, 0, /* 5867 */ 'v', 'p', 'c', 'l', 'm', 'u', 'l', 'q', 'd', 'q', 9, 0, /* 5879 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 9, 0, /* 5891 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'q', 9, 0, /* 5904 */ 'v', 'p', 's', 'h', 'r', 'd', 'q', 9, 0, /* 5913 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 9, 0, /* 5923 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, 0, /* 5936 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 9, 0, /* 5948 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'd', 'q', 9, 0, /* 5961 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'd', 'q', 9, 0, /* 5973 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'd', 'q', 9, 0, /* 5984 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 9, 0, /* 5994 */ 'v', 'p', 'm', 'o', 'v', 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'm', 'p', 'q', 9, 0, /* 6177 */ 'i', 'n', 'c', 's', 's', 'p', 'q', 9, 0, /* 6186 */ 'r', 'd', 's', 's', 'p', 'q', 9, 0, /* 6194 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'q', 'q', 9, 0, /* 6206 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'q', 'q', 9, 0, /* 6217 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'q', 'q', 9, 0, /* 6229 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'q', 'q', 9, 0, /* 6240 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'q', 9, 0, /* 6250 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 9, 0, /* 6262 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'q', 9, 0, /* 6275 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, 0, /* 6288 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'q', 'q', 9, 0, /* 6300 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'q', 'q', 9, 0, /* 6313 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'q', 'q', 9, 0, /* 6325 */ 'k', 'o', 'r', 'q', 9, 0, /* 6331 */ 'k', 'x', 'n', 'o', 'r', 'q', 9, 0, /* 6339 */ 'v', 'p', 'o', 'r', 'q', 9, 0, /* 6346 */ 'v', 'p', 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0, /* 6868 */ 'v', 'p', 'x', 'o', 'r', 9, 0, /* 6875 */ 'v', 'e', 'r', 'r', 9, 0, /* 6881 */ 'b', 's', 'r', 9, 0, /* 6886 */ 'v', 'l', 'd', 'm', 'x', 'c', 's', 'r', 9, 0, /* 6896 */ 'v', 's', 't', 'm', 'x', 'c', 's', 'r', 9, 0, /* 6906 */ 'b', 'l', 's', 'r', 9, 0, /* 6912 */ 'b', 't', 'r', 9, 0, /* 6917 */ 'l', 't', 'r', 9, 0, /* 6922 */ 's', 't', 'r', 9, 0, /* 6927 */ 'b', 'e', 'x', 't', 'r', 9, 0, /* 6934 */ 'f', 'd', 'i', 'v', 'r', 9, 0, /* 6941 */ 'f', 'i', 'd', 'i', 'v', 'r', 9, 0, /* 6949 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 0, /* 6957 */ 'b', 'l', 'c', 's', 9, 0, /* 6963 */ 'l', 'd', 's', 9, 0, /* 6968 */ 'v', 'p', '4', 'd', 'p', 'w', 's', 's', 'd', 's', 9, 0, /* 6980 */ 'v', 'p', 'd', 'p', 'w', 's', 's', 'd', 's', 9, 0, /* 6991 */ 'v', 'p', 'd', 'p', 'b', 'u', 's', 'd', 's', 9, 0, /* 7002 */ 'l', 'e', 's', 9, 0, /* 7007 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, /* 7015 */ 'l', 'f', 's', 9, 0, /* 7020 */ 'l', 'g', 's', 9, 0, /* 7025 */ 'j', 's', 9, 0, /* 7029 */ 'l', 'w', 'p', 'i', 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0, /* 7215 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, /* 7229 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 9, 0, /* 7240 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, 0, /* 7251 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 's', 9, 0, /* 7262 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 's', 9, 0, /* 7272 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 's', 9, 0, /* 7284 */ 'v', 'e', 'x', 'p', '2', 'p', 's', 9, 0, /* 7293 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 9, 0, /* 7304 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 's', 9, 0, /* 7316 */ 'v', 'c', 'v', 't', 'q', 'q', '2', 'p', 's', 9, 0, /* 7327 */ 'v', 'c', 'v', 't', 'u', 'q', 'q', '2', 'p', 's', 9, 0, /* 7339 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 's', 9, 0, /* 7350 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, /* 7366 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, /* 7379 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, /* 7393 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, /* 7409 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, /* 7422 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, /* 7436 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 's', 9, 0, /* 7446 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 's', 9, 0, /* 7458 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 9, 0, /* 7468 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 9, 0, /* 7480 */ 'v', 'm', 'o', 'v', 'a', 'p', 's', 9, 0, /* 7489 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, /* 7502 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, /* 7513 */ 'v', 'h', 's', 'u', 'b', 'p', 's', 9, 0, /* 7522 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 's', 9, 0, /* 7532 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 's', 9, 0, /* 7543 */ 'v', 's', 'u', 'b', 'p', 's', 9, 0, /* 7551 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 's', 9, 0, /* 7564 */ 'v', 'h', 'a', 'd', 'd', 'p', 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'p', 'c', 'k', 'h', 'p', 's', 9, 0, /* 7754 */ 'v', 'm', 'o', 'v', 'l', 'h', 'p', 's', 9, 0, /* 7764 */ 'v', 'm', 'o', 'v', 'h', 'p', 's', 9, 0, /* 7773 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 's', 9, 0, /* 7784 */ 'v', 'm', 'o', 'v', 'h', 'l', 'p', 's', 9, 0, /* 7794 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 9, 0, /* 7805 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 's', 9, 0, /* 7816 */ 'v', 'm', 'u', 'l', 'p', 's', 9, 0, /* 7824 */ 'v', 'm', 'o', 'v', 'l', 'p', 's', 9, 0, /* 7833 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 's', 9, 0, /* 7844 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 'p', 's', 9, 0, /* 7857 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 9, 0, /* 7866 */ 'v', 'a', 'n', 'd', 'n', 'p', 's', 9, 0, /* 7875 */ 'v', 'm', 'i', 'n', 'p', 's', 9, 0, /* 7883 */ 'v', 'r', 'c', 'p', 'p', 's', 9, 0, /* 7891 */ 'v', 'd', 'p', 'p', 's', 9, 0, /* 7898 */ 'v', 'c', 'm', 'p', 'p', 's', 9, 0, /* 7906 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 'p', 's', 9, 0, /* 7917 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 9, 0, /* 7929 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 's', 9, 0, /* 7942 */ 'v', 'o', 'r', 'p', 's', 9, 0, /* 7949 */ 'v', 'x', 'o', 'r', 'p', 's', 9, 0, /* 7957 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 'p', 's', 9, 0, /* 7969 */ 'v', 'c', 'o', 'm', 'p', 'r', 'e', 's', 's', 'p', 's', 9, 0, /* 7982 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'p', 's', 9, 0, /* 7994 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 'p', 's', 9, 0, /* 8006 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 's', 9, 0, /* 8016 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'p', 's', 9, 0, /* 8027 */ 'v', 'r', 's', 'q', 'r', 't', 'p', 's', 9, 0, /* 8037 */ 'v', 's', 'q', 'r', 't', 'p', 's', 9, 0, /* 8046 */ 'v', 't', 'e', 's', 't', 'p', 's', 9, 0, /* 8055 */ 'v', 'm', 'o', 'v', 'u', 'p', 's', 9, 0, /* 8064 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, 0, /* 8075 */ 'v', 'd', 'i', 'v', 'p', 's', 9, 0, /* 8083 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 's', 9, 0, /* 8095 */ 'v', 'm', 'a', 'x', 'p', 's', 9, 0, /* 8103 */ 'v', 'f', 'r', 'c', 'z', 'p', 's', 9, 0, /* 8112 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, /* 8121 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, /* 8134 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, /* 8148 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, /* 8161 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, /* 8175 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, /* 8188 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, /* 8202 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, /* 8215 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, /* 8229 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 's', 9, 0, /* 8240 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 9, 0, /* 8251 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 9, 0, /* 8263 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, /* 8276 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, /* 8290 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, /* 8303 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, /* 8317 */ 'v', 'r', 'c', 'p', '1', '4', 's', 's', 9, 0, /* 8327 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 's', 9, 0, /* 8339 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 9, 0, /* 8349 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 9, 0, /* 8361 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 's', 9, 0, /* 8371 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 's', 9, 0, /* 8382 */ 'v', 's', 'u', 'b', 's', 's', 9, 0, /* 8390 */ 'v', '4', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 8401 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 8411 */ 'v', '4', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 8423 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, /* 8434 */ 'v', 'a', 'd', 'd', 's', 's', 9, 0, /* 8442 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 's', 9, 0, /* 8452 */ 'v', 'r', 'e', 'd', 'u', 'c', 'e', 's', 's', 9, 0, /* 8463 */ 'v', 'r', 'a', 'n', 'g', 'e', 's', 's', 9, 0, /* 8473 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 's', 9, 0, /* 8486 */ 'v', 's', 'c', 'a', 'l', 'e', 'f', 's', 's', 9, 0, /* 8497 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, 0, /* 8507 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, 0, /* 8516 */ 'v', 'm', 'u', 'l', 's', 's', 9, 0, /* 8524 */ 'v', 'f', 'i', 'x', 'u', 'p', 'i', 'm', 'm', 's', 's', 9, 0, /* 8537 */ 'v', 'm', 'i', 'n', 's', 's', 9, 0, /* 8545 */ 'v', 'r', 'c', 'p', 's', 's', 9, 0, /* 8553 */ 'v', 'c', 'm', 'p', 's', 's', 9, 0, /* 8561 */ 'v', 'g', 'e', 't', 'e', 'x', 'p', 's', 's', 9, 0, /* 8572 */ 'v', 'f', 'p', 'c', 'l', 'a', 's', 's', 's', 's', 9, 0, /* 8584 */ 'v', 'g', 'e', 't', 'm', 'a', 'n', 't', 's', 's', 9, 0, /* 8596 */ 'm', 'o', 'v', 'n', 't', 's', 's', 9, 0, /* 8605 */ 'v', 'r', 's', 'q', 'r', 't', 's', 's', 9, 0, /* 8615 */ 'v', 's', 'q', 'r', 't', 's', 's', 9, 0, /* 8624 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 9, 0, /* 8638 */ 'v', 'd', 'i', 'v', 's', 's', 9, 0, /* 8646 */ 'v', 'm', 'o', 'v', 's', 's', 9, 0, /* 8654 */ 'v', 'm', 'a', 'x', 's', 's', 9, 0, /* 8662 */ 'v', 'f', 'r', 'c', 'z', 's', 's', 9, 0, /* 8671 */ 'b', 't', 's', 9, 0, /* 8676 */ 's', 'e', 't', 's', 9, 0, /* 8682 */ 'c', 'm', 'o', 'v', 's', 9, 0, /* 8689 */ 'b', 't', 9, 0, /* 8693 */ 'l', 'g', 'd', 't', 9, 0, /* 8699 */ 's', 'g', 'd', 't', 9, 0, /* 8705 */ 'l', 'i', 'd', 't', 9, 0, /* 8711 */ 's', 'i', 'd', 't', 9, 0, /* 8717 */ 'l', 'l', 'd', 't', 9, 0, /* 8723 */ 's', 'l', 'd', 't', 9, 0, /* 8729 */ 'r', 'e', 't', 9, 0, /* 8734 */ 'p', 'f', 'c', 'm', 'p', 'g', 't', 9, 0, /* 8743 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, /* 8751 */ 'p', 'o', 'p', 'c', 'n', 't', 9, 0, /* 8759 */ 'l', 'z', 'c', 'n', 't', 9, 0, /* 8766 */ 't', 'z', 'c', 'n', 't', 9, 0, /* 8773 */ 'i', 'n', 't', 9, 0, /* 8778 */ 'n', 'o', 't', 9, 0, /* 8783 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, /* 8791 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, /* 8801 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, /* 8813 */ 'x', 'a', 'b', 'o', 'r', 't', 9, 0, /* 8821 */ 'p', 'f', 'r', 's', 'q', 'r', 't', 9, 0, /* 8830 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 'l', 'a', 's', 't', 9, 0, /* 8843 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 'l', 'a', 's', 't', 9, 0, /* 8856 */ 'v', 'p', 't', 'e', 's', 't', 9, 0, /* 8864 */ 'f', 's', 't', 9, 0, /* 8869 */ 'f', 'i', 's', 't', 9, 0, /* 8875 */ 'v', 'a', 'e', 's', 'k', 'e', 'y', 'g', 'e', 'n', 'a', 's', 's', 'i', 's', 't', 9, 0, /* 8893 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, /* 8902 */ 'o', 'u', 't', 9, 0, /* 8907 */ 'p', 'e', 'x', 't', 9, 0, /* 8913 */ 'b', 'n', 'd', 'c', 'u', 9, 0, /* 8920 */ 'v', 'l', 'd', 'd', 'q', 'u', 9, 0, /* 8928 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, /* 8941 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, /* 8950 */ 'f', 'd', 'i', 'v', 9, 0, /* 8956 */ 'f', 'i', 'd', 'i', 'v', 9, 0, /* 8963 */ 'f', 'l', 'd', 'e', 'n', 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'd', 0, /* 11213 */ 'c', 'l', 'd', 0, /* 11217 */ 'x', 'e', 'n', 'd', 0, /* 11222 */ 'i', 'r', 'e', 't', 'd', 0, /* 11228 */ 's', 't', 'd', 0, /* 11232 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, /* 11239 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, /* 11248 */ 'c', 'w', 'd', 0, /* 11252 */ 'f', 'l', 'd', 'l', '2', 'e', 0, /* 11259 */ 'l', 'f', 'e', 'n', 'c', 'e', 0, /* 11266 */ 'm', 'f', 'e', 'n', 'c', 'e', 0, /* 11273 */ 's', 'f', 'e', 'n', 'c', 'e', 0, /* 11280 */ 'c', 'w', 'd', 'e', 0, /* 11285 */ 'f', 's', 'c', 'a', 'l', 'e', 0, /* 11292 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, /* 11301 */ 'r', 'e', 'p', 'n', 'e', 0, /* 11307 */ 'c', 'd', 'q', 'e', 0, /* 11312 */ 'x', 'a', 'c', 'q', 'u', 'i', 'r', 'e', 0, /* 11321 */ 'x', 's', 't', 'o', 'r', 'e', 0, /* 11328 */ 'x', 'r', 'e', 'l', 'e', 'a', 's', 'e', 0, /* 11337 */ 'p', 'a', 'u', 's', 'e', 0, /* 11343 */ 'l', 'e', 'a', 'v', 'e', 0, /* 11349 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, /* 11356 */ 'l', 'a', 'h', 'f', 0, /* 11361 */ 's', 'a', 'h', 'f', 0, /* 11366 */ 'p', 'u', 's', 'h', 'f', 0, /* 11372 */ 'p', 'o', 'p', 'f', 0, /* 11377 */ 'r', 'e', 't', 'f', 0, /* 11382 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, /* 11390 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, /* 11399 */ 'c', 'l', 'g', 'i', 0, /* 11404 */ 's', 't', 'g', 'i', 0, /* 11409 */ 'c', 'l', 'i', 0, /* 11413 */ 'f', 'l', 'd', 'p', 'i', 0, /* 11419 */ 's', 't', 'i', 0, /* 11423 */ 'l', 'o', 'c', 'k', 0, /* 11428 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'l', 0, /* 11439 */ 'p', 'u', 's', 'h', 'a', 'l', 0, /* 11446 */ 'p', 'o', 'p', 'a', 'l', 0, /* 11452 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 11466 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, /* 11474 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, /* 11481 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, /* 11489 */ 'v', 'z', 'e', 'r', 'o', 'a', 'l', 'l', 0, /* 11498 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, /* 11506 */ 'f', 'x', 'a', 'm', 0, /* 11511 */ 'f', 'p', 'r', 'e', 'm', 0, /* 11517 */ 'v', 'p', 'c', 'o', 'm', 0, /* 11523 */ 'f', 's', 'e', 't', 'p', 'm', 0, /* 11530 */ 'r', 's', 'm', 0, /* 11534 */ 'f', 'p', 'a', 't', 'a', 'n', 0, /* 11541 */ 'f', 'p', 't', 'a', 'n', 0, /* 11547 */ 'f', 's', 'i', 'n', 0, /* 11552 */ 'c', 'q', 'o', 0, /* 11556 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, /* 11563 */ 'i', 'n', 't', 'o', 0, /* 11568 */ 'r', 'd', 't', 's', 'c', 'p', 0, /* 11575 */ 'r', 'e', 'p', 0, /* 11579 */ 'v', 'p', 'c', 'm', 'p', 0, /* 11585 */ 'v', 'c', 'm', 'p', 0, /* 11590 */ 'f', 'e', 'n', 'i', '8', '0', '8', '7', '_', 'n', 'o', 'p', 0, /* 11603 */ 'f', 'd', 'i', 's', 'i', '8', '0', '8', '7', '_', 'n', 'o', 'p', 0, /* 11617 */ 'f', 'n', 'o', 'p', 0, /* 11622 */ 'f', 'c', 'o', 'm', 'p', 'p', 0, /* 11629 */ 'f', 'u', 'c', 'o', 'm', 'p', 'p', 0, /* 11637 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, /* 11649 */ 'f', 'd', 'e', 'c', 's', 't', 'p', 0, /* 11657 */ 'f', 'i', 'n', 'c', 's', 't', 'p', 0, /* 11665 */ 'c', 'd', 'q', 0, /* 11669 */ 'p', 'u', 's', 'h', 'f', 'q', 0, /* 11676 */ 'p', 'o', 'p', 'f', 'q', 0, /* 11682 */ 'r', 'e', 't', 'f', 'q', 0, /* 11688 */ 'i', 'r', 'e', 't', 'q', 0, /* 11694 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, /* 11702 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, /* 11711 */ 'v', 'z', 'e', 'r', 'o', 'u', 'p', 'p', 'e', 'r', 0, /* 11722 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, /* 11731 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 0, /* 11739 */ 'r', 'd', 'm', 's', 'r', 0, /* 11745 */ 'w', 'r', 'm', 's', 'r', 0, /* 11751 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, /* 11761 */ 'a', 'a', 's', 0, /* 11765 */ 'd', 'a', 's', 0, /* 11769 */ 'f', 'a', 'b', 's', 0, /* 11774 */ 'p', 'u', 's', 'h', 9, 'c', 's', 0, /* 11782 */ 'p', 'u', 's', 'h', 9, 'd', 's', 0, /* 11790 */ 'p', 'o', 'p', 9, 'd', 's', 0, /* 11797 */ 'p', 'u', 's', 'h', 9, 'e', 's', 0, /* 11805 */ 'p', 'o', 'p', 9, 'e', 's', 0, /* 11812 */ 'p', 'u', 's', 'h', 9, 'f', 's', 0, /* 11820 */ 'p', 'o', 'p', 9, 'f', 's', 0, /* 11827 */ 'p', 'u', 's', 'h', 9, 'g', 's', 0, /* 11835 */ 'p', 'o', 'p', 9, 'g', 's', 0, /* 11842 */ 's', 'w', 'a', 'p', 'g', 's', 0, /* 11849 */ 'f', 'c', 'h', 's', 0, /* 11854 */ 'e', 'n', 'c', 'l', 's', 0, /* 11860 */ 'f', 'e', 'm', 'm', 's', 0, /* 11866 */ 'f', 'c', 'o', 's', 0, /* 11871 */ 'f', 's', 'i', 'n', 'c', 'o', 's', 0, /* 11879 */ 'p', 'u', 's', 'h', 9, 's', 's', 0, /* 11887 */ 'p', 'o', 'p', 9, 's', 's', 0, /* 11894 */ 'c', 'l', 't', 's', 0, /* 11899 */ 'f', 'l', 'd', 'l', '2', 't', 0, /* 11906 */ 'f', 'x', 't', 'r', 'a', 'c', 't', 0, /* 11914 */ 'i', 'r', 'e', 't', 0, /* 11919 */ 's', 'y', 's', 'r', 'e', 't', 0, /* 11926 */ 'm', 'w', 'a', 'i', 't', 0, /* 11932 */ 'f', 'n', 'i', 'n', 'i', 't', 0, /* 11939 */ 's', 'y', 's', 'e', 'x', 'i', 't', 0, /* 11947 */ 'h', 'l', 't', 0, /* 11951 */ 'f', 'r', 'n', 'd', 'i', 'n', 't', 0, /* 11959 */ 'f', 's', 'q', 'r', 't', 0, /* 11965 */ 'x', 't', 'e', 's', 't', 0, /* 11971 */ 'f', 't', 's', 't', 0, /* 11976 */ 'e', 'n', 'c', 'l', 'u', 0, /* 11982 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, /* 11989 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, /* 11996 */ 'x', 'g', 'e', 't', 'b', 'v', 0, /* 12003 */ 'x', 's', 'e', 't', 'b', 'v', 0, /* 12010 */ 'e', 'n', 'c', 'l', 'v', 0, /* 12016 */ 'p', 'u', 's', 'h', 'a', 'w', 0, /* 12023 */ 'p', 'o', 'p', 'a', 'w', 0, /* 12029 */ 'c', 'b', 'w', 0, /* 12033 */ 'f', 'y', 'l', '2', 'x', 0, /* 12039 */ 'f', 'n', 's', 't', 's', 'w', 9, 'a', 'x', 0, /* 12049 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'x', 0, /* 12060 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'e', 'a', 'x', 0, /* 12071 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'e', 'a', 'x', 0, /* 12082 */ 'v', 'm', 'r', 'u', 'n', 9, 'e', 'a', 'x', 0, /* 12092 */ 's', 'k', 'i', 'n', 'i', 't', 9, 'e', 'a', 'x', 0, /* 12103 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'e', 'a', 'x', 0, /* 12115 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'r', 'a', 'x', 0, /* 12126 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'r', 'a', 'x', 0, /* 12137 */ 'v', 'm', 'r', 'u', 'n', 9, 'r', 'a', 'x', 0, /* 12147 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'e', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, /* 12164 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'r', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, /* 12181 */ 'i', 'n', 9, 'a', 'l', ',', 32, 'd', 'x', 0, /* 12191 */ 'i', 'n', 9, 'a', 'x', ',', 32, 'd', 'x', 0, /* 12201 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 'd', 'x', 0, /* 12212 */ 'f', 'n', 'c', 'l', 'e', 'x', 0, /* 12219 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, /* 12228 */ 'm', 'w', 'a', 'i', 't', 'x', 0, /* 12235 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, /* 12244 */ 'f', 'l', 'd', 'z', 0, /* 12249 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, '{', 0, /* 12265 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 9, '{', 0, /* 12282 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, '{', 0, /* 12298 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 9, '{', 0, /* 12315 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, '{', 0, /* 12331 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 9, '{', 0, /* 12348 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, '{', 0, /* 12364 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 9, '{', 0, /* 12381 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, '{', 0, /* 12397 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 9, '{', 0, /* 12414 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, '{', 0, /* 12430 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 9, '{', 0, /* 12447 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, '{', 0, /* 12463 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 9, '{', 0, /* 12480 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, '{', 0, /* 12496 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 9, '{', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 11053U, // DBG_VALUE 11063U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 11046U, // BUNDLE 11073U, // LIFETIME_START 11033U, // LIFETIME_END 0U, // STACKMAP 11453U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 10860U, // PATCHABLE_FUNCTION_ENTER 10780U, // PATCHABLE_RET 10906U, // PATCHABLE_FUNCTION_EXIT 10883U, // PATCHABLE_TAIL_CALL 10835U, // PATCHABLE_EVENT_CALL 10811U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // AVX1_SETALLONES 0U, // AVX2_SETALLONES 0U, // AVX512_128_SET0 0U, // AVX512_256_SET0 0U, // AVX512_512_SET0 0U, // AVX512_512_SETALLONES 0U, // AVX512_512_SEXT_MASK_32 0U, // AVX512_512_SEXT_MASK_64 0U, // AVX512_FsFLD0SD 0U, // AVX512_FsFLD0SS 0U, // AVX_SET0 0U, // KSET0D 0U, // KSET0Q 0U, // KSET0W 0U, // KSET1D 0U, // KSET1Q 0U, // KSET1W 0U, // MMX_SET0 0U, // V_SET0 0U, // V_SETALLONES 11088U, // AAA 18192U, // AAD8i8 21564U, // AAM8i8 11762U, // AAS 11770U, // ABS_F 0U, // ABS_Fp32 0U, // ABS_Fp64 0U, // ABS_Fp80 26727U, // ADC16i16 1083033U, // ADC16mi 1083033U, // ADC16mi8 1083033U, // ADC16mr 34653849U, // ADC16ri 34653849U, // ADC16ri8 68208281U, // ADC16rm 34653849U, // ADC16rr 34621081U, // ADC16rr_REV 26853U, // ADC32i32 1115801U, // ADC32mi 1115801U, // ADC32mi8 1115801U, // ADC32mr 34653849U, // ADC32ri 34653849U, // ADC32ri8 101762713U, // ADC32rm 34653849U, // ADC32rr 34621081U, // ADC32rr_REV 26990U, // ADC64i32 1132185U, // ADC64mi32 1132185U, // ADC64mi8 1132185U, // ADC64mr 34653849U, // ADC64ri32 34653849U, // ADC64ri8 135317145U, // ADC64rm 34653849U, // ADC64rr 34621081U, // ADC64rr_REV 26625U, // ADC8i8 1148569U, // ADC8mi 1148569U, // ADC8mi8 1148569U, // ADC8mr 34653849U, // ADC8ri 34653849U, // ADC8ri8 168871577U, // ADC8rm 34653849U, // ADC8rr 34621081U, // ADC8rr_REV 101738229U, // ADCX32rm 34629365U, // ADCX32rr 135292661U, // ADCX64rm 34629365U, // ADCX64rr 26736U, // ADD16i16 1083243U, // ADD16mi 1083243U, // ADD16mi8 1083243U, // ADD16mr 34654059U, // ADD16ri 34654059U, // ADD16ri8 68208491U, // ADD16rm 34654059U, // ADD16rr 34621291U, // ADD16rr_REV 26863U, // ADD32i32 1116011U, // ADD32mi 1116011U, // ADD32mi8 1116011U, // ADD32mr 34654059U, // ADD32ri 34654059U, // ADD32ri8 101762923U, // ADD32rm 34654059U, // ADD32rr 34621291U, // ADD32rr_REV 27000U, // ADD64i32 1132395U, // ADD64mi32 1132395U, // ADD64mi8 1132395U, // ADD64mr 34654059U, // ADD64ri32 34654059U, // ADD64ri8 135317355U, // ADD64rm 34654059U, // ADD64rr 34621291U, // ADD64rr_REV 26634U, // ADD8i8 1148779U, // ADD8mi 1148779U, // ADD8mi8 1148779U, // ADD8mr 34654059U, // ADD8ri 34654059U, // ADD8ri8 168871787U, // ADD8rm 34654059U, // ADD8rr 34621291U, // ADD8rr_REV 202394334U, // ADDPDrm 34622174U, // ADDPDrr 202399110U, // ADDPSrm 34626950U, // ADDPSrr 235949685U, // ADDSDrm 235949685U, // ADDSDrm_Int 34623093U, // ADDSDrr 34623093U, // ADDSDrr_Int 269508811U, // ADDSSrm 269508811U, // ADDSSrm_Int 34627787U, // ADDSSrr 34627787U, // ADDSSrr_Int 202394269U, // ADDSUBPDrm 34622109U, // ADDSUBPDrr 202399045U, // ADDSUBPSrm 34626885U, // ADDSUBPSrr 116586U, // ADD_F32m 132970U, // ADD_F64m 34672U, // ADD_FI16m 67440U, // ADD_FI32m 21716U, // ADD_FPrST0 18282U, // ADD_FST0r 0U, // ADD_Fp32 0U, // ADD_Fp32m 0U, // ADD_Fp64 0U, // ADD_Fp64m 0U, // ADD_Fp64m32 0U, // ADD_Fp80 0U, // ADD_Fp80m32 0U, // ADD_Fp80m64 0U, // ADD_FpI16m32 0U, // ADD_FpI16m64 0U, // ADD_FpI16m80 0U, // ADD_FpI32m32 0U, // ADD_FpI32m64 0U, // ADD_FpI32m80 2115434U, // ADD_FrST0 101738255U, // ADOX32rm 34629391U, // ADOX32rr 135292687U, // ADOX64rm 34629391U, // ADOX64rr 303063680U, // AESDECLASTrm 34628224U, // AESDECLASTrr 303056543U, // AESDECrm 34621087U, // AESDECrr 303063693U, // AESENCLASTrm 34628237U, // AESENCLASTrr 303056591U, // AESENCrm 34621135U, // AESENCrr 336611014U, // AESIMCrm 370165446U, // AESIMCrr 2484101805U, // AESKEYGENASSIST128rm 2517656237U, // AESKEYGENASSIST128rr 26745U, // AND16i16 1083574U, // AND16mi 1083574U, // AND16mi8 1083574U, // AND16mr 34654390U, // AND16ri 34654390U, // AND16ri8 68208822U, // AND16rm 34654390U, // AND16rr 34621622U, // AND16rr_REV 26873U, // AND32i32 1116342U, // AND32mi 1116342U, // AND32mi8 1116342U, // AND32mr 34654390U, // AND32ri 34654390U, // AND32ri8 101763254U, // AND32rm 34654390U, // AND32rr 34621622U, // AND32rr_REV 27010U, // AND64i32 1132726U, // AND64mi32 1132726U, // AND64mi8 1132726U, // AND64mr 34654390U, // AND64ri32 34654390U, // AND64ri8 135317686U, // AND64rm 34654390U, // AND64rr 34621622U, // AND64rr_REV 26643U, // AND8i8 1149110U, // AND8mi 1149110U, // AND8mi8 1149110U, // AND8mr 34654390U, // AND8ri 34654390U, // AND8ri8 168872118U, // AND8rm 34654390U, // AND8rr 34621622U, // AND8rr_REV 2517652606U, // ANDN32rm 2517652606U, // ANDN32rr 2517652606U, // ANDN64rm 2517652606U, // ANDN64rr 202394609U, // ANDNPDrm 34622449U, // ANDNPDrr 202399420U, // ANDNPSrm 34627260U, // ANDNPSrr 202394383U, // ANDPDrm 34622223U, // ANDPDrr 202399182U, // ANDPSrm 34627022U, // ANDPSrr 1086423U, // ARPL16mr 370168791U, // ARPL16rr 2551208720U, // BEXTR32rm 2517654288U, // BEXTR32rr 2584763152U, // BEXTR64rm 2517654288U, // BEXTR64rr 2551208720U, // BEXTRI32mi 2517654288U, // BEXTRI32ri 2584763152U, // BEXTRI64mi 2517654288U, // BEXTRI64ri 403723200U, // BLCFILL32rm 370168768U, // BLCFILL32rr 437277632U, // BLCFILL64rm 370168768U, // BLCFILL64rr 403722900U, // BLCI32rm 370168468U, // BLCI32rr 437277332U, // BLCI64rm 370168468U, // BLCI64rr 403719855U, // BLCIC32rm 370165423U, // BLCIC32rr 437274287U, // BLCIC64rm 370165423U, // BLCIC64rr 403723136U, // BLCMSK32rm 370168704U, // BLCMSK32rr 437277568U, // BLCMSK64rm 370168704U, // BLCMSK64rr 403725102U, // BLCS32rm 370170670U, // BLCS32rr 437279534U, // BLCS64rm 370170670U, // BLCS64rr 2349878047U, // BLENDPDrmi 2182105887U, // BLENDPDrri 2349882846U, // BLENDPSrmi 2182110686U, // BLENDPSrri 202394783U, // BLENDVPDrm0 34622623U, // BLENDVPDrr0 202399618U, // BLENDVPSrm0 34627458U, // BLENDVPSrr0 403723209U, // BLSFILL32rm 370168777U, // BLSFILL32rr 437277641U, // BLSFILL64rm 370168777U, // BLSFILL64rr 403723065U, // BLSI32rm 370168633U, // BLSI32rr 437277497U, // BLSI64rm 370168633U, // BLSI64rr 403719862U, // BLSIC32rm 370165430U, // BLSIC32rr 437274294U, // BLSIC64rm 370165430U, // BLSIC64rr 403723144U, // BLSMSK32rm 370168712U, // BLSMSK32rr 437277576U, // BLSMSK64rm 370168712U, // BLSMSK64rr 403725051U, // BLSR32rm 370170619U, // BLSR32rr 437279483U, // BLSR64rm 370170619U, // BLSR64rr 470832036U, // BNDCL32rm 370168740U, // BNDCL32rr 470832036U, // BNDCL64rm 370168740U, // BNDCL64rr 470832245U, // BNDCN32rm 370168949U, // BNDCN32rr 470832245U, // BNDCN64rm 370168949U, // BNDCN64rr 470835922U, // BNDCU32rm 370172626U, // BNDCU32rr 470835922U, // BNDCU64rm 370172626U, // BNDCU64rr 470836987U, // BNDLDXrm 470831993U, // BNDMK32rm 470831993U, // BNDMK64rm 1139485U, // BNDMOV32mr 437281565U, // BNDMOV32rm 1205021U, // BNDMOV64mr 336618269U, // BNDMOV64rm 370172701U, // BNDMOVrr 370172701U, // BNDMOVrr_REV 173870U, // BNDSTXmr 403720422U, // BOUNDS16rm 437274854U, // BOUNDS32rm 504386081U, // BSF16rm 370168353U, // BSF16rr 403722785U, // BSF32rm 370168353U, // BSF32rr 437277217U, // BSF64rm 370168353U, // BSF64rr 504388322U, // BSR16rm 370170594U, // BSR16rr 403725026U, // BSR32rm 370170594U, // BSR32rr 437279458U, // BSR64rm 370170594U, // BSR64rr 21695U, // BSWAP16r_BAD 21695U, // BSWAP32r 21695U, // BSWAP64r 1090034U, // BT16mi8 1090034U, // BT16mr 370172402U, // BT16ri8 370172402U, // BT16rr 1122802U, // BT32mi8 1122802U, // BT32mr 370172402U, // BT32ri8 370172402U, // BT32rr 1139186U, // BT64mi8 1139186U, // BT64mr 370172402U, // BT64ri8 370172402U, // BT64rr 1083100U, // BTC16mi8 1083100U, // BTC16mr 34653916U, // BTC16ri8 34653916U, // BTC16rr 1115868U, // BTC32mi8 1115868U, // BTC32mr 34653916U, // BTC32ri8 34653916U, // BTC32rr 1132252U, // BTC64mi8 1132252U, // BTC64mr 34653916U, // BTC64ri8 34653916U, // BTC64rr 1088257U, // BTR16mi8 1088257U, // BTR16mr 34659073U, // BTR16ri8 34659073U, // BTR16rr 1121025U, // BTR32mi8 1121025U, // BTR32mr 34659073U, // BTR32ri8 34659073U, // BTR32rr 1137409U, // BTR64mi8 1137409U, // BTR64mr 34659073U, // BTR64ri8 34659073U, // BTR64rr 1090016U, // BTS16mi8 1090016U, // BTS16mr 34660832U, // BTS16ri8 34660832U, // BTS16rr 1122784U, // BTS32mi8 1122784U, // BTS32mr 34660832U, // BTS32ri8 34660832U, // BTS32rr 1139168U, // BTS64mi8 1139168U, // BTS64mr 34660832U, // BTS64ri8 34660832U, // BTS64rr 2551206554U, // BZHI32rm 2517652122U, // BZHI32rr 2584760986U, // BZHI64rm 2517652122U, // BZHI64rr 37818U, // CALL16m 37818U, // CALL16m_NT 21434U, // CALL16r 21434U, // CALL16r_NT 70586U, // CALL32m 70586U, // CALL32m_NT 21434U, // CALL32r 21434U, // CALL32r_NT 86970U, // CALL64m 86970U, // CALL64m_NT 185274U, // CALL64pcrel32 21434U, // CALL64r 21434U, // CALL64r_NT 185274U, // CALLpcrel16 185274U, // CALLpcrel32 12030U, // CBW 11666U, // CDQ 11308U, // CDQE 11850U, // CHS_F 0U, // CHS_Fp32 0U, // CHS_Fp64 0U, // CHS_Fp80 11132U, // CLAC 11164U, // CLC 11214U, // CLD 102901U, // CLDEMOTE 103045U, // CLFLUSH 107106U, // CLFLUSHOPT 11400U, // CLGI 11410U, // CLI 75581U, // CLRSSBSY 11895U, // CLTS 99911U, // CLWB 11557U, // CLZEROr 11168U, // CMC 68174716U, // CMOVA16rm 34620284U, // CMOVA16rr 101729148U, // CMOVA32rm 34620284U, // CMOVA32rr 135283580U, // CMOVA64rm 34620284U, // CMOVA64rr 68178217U, // CMOVAE16rm 34623785U, // CMOVAE16rr 101732649U, // CMOVAE32rm 34623785U, // CMOVAE32rr 135287081U, // CMOVAE64rm 34623785U, // CMOVAE64rr 68175417U, // CMOVB16rm 34620985U, // CMOVB16rr 101729849U, // CMOVB32rm 34620985U, // CMOVB32rr 135284281U, // CMOVB64rm 34620985U, // CMOVB64rr 68178237U, // CMOVBE16rm 34623805U, // CMOVBE16rr 101732669U, // CMOVBE32rm 34623805U, // CMOVBE32rr 135287101U, // CMOVBE64rm 34623805U, // CMOVBE64rr 26507U, // CMOVBE_F 0U, // CMOVBE_Fp32 0U, // CMOVBE_Fp64 0U, // CMOVBE_Fp80 26475U, // CMOVB_F 0U, // CMOVB_Fp32 0U, // CMOVB_Fp64 0U, // CMOVB_Fp80 68178458U, // CMOVE16rm 34624026U, // CMOVE16rr 101732890U, // CMOVE32rm 34624026U, // CMOVE32rr 135287322U, // CMOVE64rm 34624026U, // CMOVE64rr 26539U, // CMOVE_F 0U, // CMOVE_Fp32 0U, // CMOVE_Fp64 0U, // CMOVE_Fp80 68178508U, // CMOVG16rm 34624076U, // CMOVG16rr 101732940U, // CMOVG32rm 34624076U, // CMOVG32rr 135287372U, // CMOVG64rm 34624076U, // CMOVG64rr 68178282U, // CMOVGE16rm 34623850U, // CMOVGE16rr 101732714U, // CMOVGE32rm 34623850U, // CMOVGE32rr 135287146U, // CMOVGE64rm 34623850U, // CMOVGE64rr 68178957U, // CMOVL16rm 34624525U, // CMOVL16rr 101733389U, // CMOVL32rm 34624525U, // CMOVL32rr 135287821U, // CMOVL64rm 34624525U, // CMOVL64rr 68178306U, // CMOVLE16rm 34623874U, // CMOVLE16rr 101732738U, // CMOVLE32rm 34623874U, // CMOVLE32rr 135287170U, // CMOVLE64rm 34623874U, // CMOVLE64rr 26490U, // CMOVNBE_F 0U, // CMOVNBE_Fp32 0U, // CMOVNBE_Fp64 0U, // CMOVNBE_Fp80 26459U, // CMOVNB_F 0U, // CMOVNB_Fp32 0U, // CMOVNB_Fp64 0U, // CMOVNB_Fp80 68178334U, // CMOVNE16rm 34623902U, // CMOVNE16rr 101732766U, // CMOVNE32rm 34623902U, // CMOVNE32rr 135287198U, // CMOVNE64rm 34623902U, // CMOVNE64rr 26523U, // CMOVNE_F 0U, // CMOVNE_Fp32 0U, // CMOVNE_Fp64 0U, // CMOVNE_Fp80 68179114U, // CMOVNO16rm 34624682U, // CMOVNO16rr 101733546U, // CMOVNO32rm 34624682U, // CMOVNO32rr 135287978U, // CMOVNO64rm 34624682U, // CMOVNO64rr 68179234U, // CMOVNP16rm 34624802U, // CMOVNP16rr 101733666U, // CMOVNP32rm 34624802U, // CMOVNP32rr 135288098U, // CMOVNP64rm 34624802U, // CMOVNP64rr 26554U, // CMOVNP_F 0U, // CMOVNP_Fp32 0U, // CMOVNP_Fp64 0U, // CMOVNP_Fp80 68180874U, // CMOVNS16rm 34626442U, // CMOVNS16rr 101735306U, // CMOVNS32rm 34626442U, // CMOVNS32rr 135289738U, // CMOVNS64rm 34626442U, // CMOVNS64rr 68179128U, // CMOVO16rm 34624696U, // CMOVO16rr 101733560U, // CMOVO32rm 34624696U, // CMOVO32rr 135287992U, // CMOVO64rm 34624696U, // CMOVO64rr 68179350U, // CMOVP16rm 34624918U, // CMOVP16rr 101733782U, // CMOVP32rm 34624918U, // CMOVP32rr 135288214U, // CMOVP64rm 34624918U, // CMOVP64rr 26570U, // CMOVP_F 0U, // CMOVP_Fp32 0U, // CMOVP_Fp64 0U, // CMOVP_Fp80 68182507U, // CMOVS16rm 34628075U, // CMOVS16rr 101736939U, // CMOVS32rm 34628075U, // CMOVS32rr 135291371U, // CMOVS64rm 34628075U, // CMOVS64rr 26762U, // CMP16i16 1086708U, // CMP16mi 1086708U, // CMP16mi8 1086708U, // CMP16mr 370169076U, // CMP16ri 370169076U, // CMP16ri8 504386804U, // CMP16rm 370169076U, // CMP16rr 370169076U, // CMP16rr_REV 26916U, // CMP32i32 1119476U, // CMP32mi 1119476U, // CMP32mi8 1119476U, // CMP32mr 370169076U, // CMP32ri 370169076U, // CMP32ri8 403723508U, // CMP32rm 370169076U, // CMP32rr 370169076U, // CMP32rr_REV 27020U, // CMP64i32 1135860U, // CMP64mi32 1135860U, // CMP64mi8 1135860U, // CMP64mr 370169076U, // CMP64ri32 370169076U, // CMP64ri8 437277940U, // CMP64rm 370169076U, // CMP64rr 370169076U, // CMP64rr_REV 26660U, // CMP8i8 1152244U, // CMP8mi 1152244U, // CMP8mi8 1152244U, // CMP8mr 370169076U, // CMP8ri 370169076U, // CMP8ri8 537941236U, // CMP8rm 370169076U, // CMP8rr 370169076U, // CMP8rr_REV 2721262910U, // CMPPDrmi 2349878281U, // CMPPDrmi_alt 573795646U, // CMPPDrri 2182106121U, // CMPPDrri_alt 2722311486U, // CMPPSrmi 2349883100U, // CMPPSrmi_alt 574844222U, // CMPPSrri 2182110940U, // CMPPSrri_alt 230770U, // CMPSB 2723360062U, // CMPSDrm 2723360062U, // CMPSDrm_Int 2383433479U, // CMPSDrm_alt 575892798U, // CMPSDrr 575892798U, // CMPSDrr_Int 2182106887U, // CMPSDrr_alt 249607U, // CMPSL 268566U, // CMPSQ 576924990U, // CMPSSrm 576924990U, // CMPSSrm_Int 2416992619U, // CMPSSrm_alt 576941374U, // CMPSSrr 576941374U, // CMPSSrr_Int 2182111595U, // CMPSSrr_alt 288218U, // CMPSW 148396U, // CMPXCHG16B 1086001U, // CMPXCHG16rm 370168369U, // CMPXCHG16rr 1118769U, // CMPXCHG32rm 370168369U, // CMPXCHG32rr 1135153U, // CMPXCHG64rm 370168369U, // CMPXCHG64rr 82872U, // CMPXCHG8B 1151537U, // CMPXCHG8rm 370168369U, // CMPXCHG8rr 605048520U, // COMISDrm 605048520U, // COMISDrm_Int 370167496U, // COMISDrr 370167496U, // COMISDrr_Int 638607668U, // COMISSrm 638607668U, // COMISSrm_Int 370172212U, // COMISSrr 370172212U, // COMISSrr_Int 21759U, // COMP_FST0r 21209U, // COM_FIPr 21152U, // COM_FIr 21569U, // COM_FST0r 11867U, // COS_F 0U, // COS_Fp32 0U, // COS_Fp64 0U, // COS_Fp80 11208U, // CPUID 11553U, // CQO 68206683U, // CRC32r32m16 101761115U, // CRC32r32m32 168869979U, // CRC32r32m8 34652251U, // CRC32r32r16 34652251U, // CRC32r32r32 34652251U, // CRC32r32r8 135315547U, // CRC32r64m64 168869979U, // CRC32r64m8 34652251U, // CRC32r64r64 34652251U, // CRC32r64r8 437275076U, // CVTDQ2PDrm 370166212U, // CVTDQ2PDrr 336616575U, // CVTDQ2PSrm 370171007U, // CVTDQ2PSrr 672159269U, // CVTPD2DQrm 370169381U, // CVTPD2DQrr 672160831U, // CVTPD2PSrm 370170943U, // CVTPD2PSrr 672159301U, // CVTPS2DQrm 370169413U, // CVTPS2DQrr 605047282U, // CVTPS2PDrm 370166258U, // CVTPS2PDrr 605049624U, // CVTSD2SI64rm_Int 370168600U, // CVTSD2SI64rr_Int 605049624U, // CVTSD2SIrm_Int 370168600U, // CVTSD2SIrr_Int 605052967U, // CVTSD2SSrm 235954215U, // CVTSD2SSrm_Int 370171943U, // CVTSD2SSrr 34627623U, // CVTSD2SSrr_Int 403721674U, // CVTSI2SDrm 101731786U, // CVTSI2SDrm_Int 370167242U, // CVTSI2SDrr 34622922U, // CVTSI2SDrr_Int 403726386U, // CVTSI2SSrm 101736498U, // CVTSI2SSrm_Int 370171954U, // CVTSI2SSrr 34627634U, // CVTSI2SSrr_Int 437276106U, // CVTSI642SDrm 135286218U, // CVTSI642SDrm_Int 370167242U, // CVTSI642SDrr 34622922U, // CVTSI642SDrr_Int 437280818U, // CVTSI642SSrm 135290930U, // CVTSI642SSrm_Int 370171954U, // CVTSI642SSrr 34627634U, // CVTSI642SSrr_Int 638602721U, // CVTSS2SDrm 269503969U, // CVTSS2SDrm_Int 370167265U, // CVTSS2SDrr 34622945U, // CVTSS2SDrr_Int 638604079U, // CVTSS2SI64rm_Int 370168623U, // CVTSS2SI64rr_Int 638604079U, // CVTSS2SIrm_Int 370168623U, // CVTSS2SIrr_Int 672159257U, // CVTTPD2DQrm 370169369U, // CVTTPD2DQrr 672159289U, // CVTTPS2DQrm 370169401U, // CVTTPS2DQrr 605049612U, // CVTTSD2SI64rm 605049612U, // CVTTSD2SI64rm_Int 370168588U, // CVTTSD2SI64rr 370168588U, // CVTTSD2SI64rr_Int 605049612U, // CVTTSD2SIrm 605049612U, // CVTTSD2SIrm_Int 370168588U, // CVTTSD2SIrr 370168588U, // CVTTSD2SIrr_Int 638604067U, // CVTTSS2SI64rm 638604067U, // CVTTSS2SI64rm_Int 370168611U, // CVTTSS2SI64rr 370168611U, // CVTTSS2SI64rr_Int 638604067U, // CVTTSS2SIrm 638604067U, // CVTTSS2SIrm_Int 370168611U, // CVTTSS2SIrr 370168611U, // CVTTSS2SIrr_Int 11249U, // CWD 11281U, // CWDE 11092U, // DAA 11766U, // DAS 11018U, // DATA16_PREFIX 34466U, // DEC16m 18082U, // DEC16r 18082U, // DEC16r_alt 67234U, // DEC32m 18082U, // DEC32r 18082U, // DEC32r_alt 83618U, // DEC64m 18082U, // DEC64r 100002U, // DEC8m 18082U, // DEC8r 41720U, // DIV16m 25336U, // DIV16r 74488U, // DIV32m 25336U, // DIV32r 90872U, // DIV64m 25336U, // DIV64r 107256U, // DIV8m 25336U, // DIV8r 202394794U, // DIVPDrm 34622634U, // DIVPDrr 202399629U, // DIVPSrm 34627469U, // DIVPSrr 121623U, // DIVR_F32m 138007U, // DIVR_F64m 39710U, // DIVR_FI16m 72478U, // DIVR_FI32m 21826U, // DIVR_FPrST0 23319U, // DIVR_FST0r 0U, // DIVR_Fp32m 0U, // DIVR_Fp64m 0U, // DIVR_Fp64m32 0U, // DIVR_Fp80m32 0U, // DIVR_Fp80m64 0U, // DIVR_FpI16m32 0U, // DIVR_FpI16m64 0U, // DIVR_FpI16m80 0U, // DIVR_FpI32m32 0U, // DIVR_FpI32m64 0U, // DIVR_FpI32m80 2120471U, // DIVR_FrST0 235949965U, // DIVSDrm 235949965U, // DIVSDrm_Int 34623373U, // DIVSDrr 34623373U, // DIVSDrr_Int 269509056U, // DIVSSrm 269509056U, // DIVSSrm_Int 34628032U, // DIVSSrr 34628032U, // DIVSSrr_Int 123639U, // DIV_F32m 140023U, // DIV_F64m 41725U, // DIV_FI16m 74493U, // DIV_FI32m 21903U, // DIV_FPrST0 25335U, // DIV_FST0r 0U, // DIV_Fp32 0U, // DIV_Fp32m 0U, // DIV_Fp64 0U, // DIV_Fp64m 0U, // DIV_Fp64m32 0U, // DIV_Fp80 0U, // DIV_Fp80m32 0U, // DIV_Fp80m64 0U, // DIV_FpI16m32 0U, // DIV_FpI16m64 0U, // DIV_FpI16m80 0U, // DIV_FpI32m32 0U, // DIV_FpI32m64 0U, // DIV_FpI32m80 2122487U, // DIV_FrST0 2349878274U, // DPPDrmi 2182106114U, // DPPDrri 2349883093U, // DPPSrmi 2182110933U, // DPPSrri 11855U, // ENCLS 11977U, // ENCLU 12011U, // ENCLV 10973U, // ENDBR32 11004U, // ENDBR64 370170521U, // ENTER 2148654896U, // EXTRACTPSmr 2517655344U, // EXTRACTPSrr 34658551U, // EXTRQ 2853230839U, // EXTRQI 10954U, // F2XM1 739300281U, // FARCALL16i 299961U, // FARCALL16m 739300281U, // FARCALL32i 299962U, // FARCALL32m 299961U, // FARCALL64 7394553U, // FARJMP16i 300281U, // FARJMP16m 7394553U, // FARJMP32i 300282U, // FARJMP32m 300281U, // FARJMP64 322043U, // FBLDm 322059U, // FBSTPm 119873U, // FCOM32m 136257U, // FCOM64m 120063U, // FCOMP32m 136447U, // FCOMP64m 11623U, // FCOMPP 11650U, // FDECSTP 11604U, // FDISI8087_NOP 11861U, // FEMMS 11591U, // FENI8087_NOP 20814U, // FFREE 21729U, // FFREEP 37959U, // FICOM16m 70727U, // FICOM32m 38150U, // FICOMP16m 70918U, // FICOMP32m 11658U, // FINCSTP 41945U, // FLDCW16m 123652U, // FLDENVm 11253U, // FLDL2E 11900U, // FLDL2T 10985U, // FLDLG2 10992U, // FLDLN2 11414U, // FLDPI 12213U, // FNCLEX 11933U, // FNINIT 11618U, // FNOP 41952U, // FNSTCW16m 12040U, // FNSTSW16r 42489U, // FNSTSWm 11535U, // FPATAN 2117957U, // FPNCEST0r 11512U, // FPREM 10947U, // FPREM1 11542U, // FPTAN 11952U, // FRNDINT 121540U, // FRSTORm 119306U, // FSAVEm 11286U, // FSCALE 11524U, // FSETPM 11872U, // FSINCOS 123660U, // FSTENVm 11507U, // FXAM 301772U, // FXRSTOR 295259U, // FXRSTOR64 299538U, // FXSAVE 295249U, // FXSAVE64 11907U, // FXTRACT 12034U, // FYL2X 10960U, // FYL2XP1 11152U, // GETSEC 2450539772U, // GF2P8AFFINEINVQBrmi 2182104316U, // GF2P8AFFINEINVQBrri 2450539709U, // GF2P8AFFINEQBrmi 2182104253U, // GF2P8AFFINEQBrri 303055962U, // GF2P8MULBrm 34620506U, // GF2P8MULBrr 202394342U, // HADDPDrm 34622182U, // HADDPDrr 202399118U, // HADDPSrm 34626958U, // HADDPSrr 11948U, // HLT 202394291U, // HSUBPDrm 34622131U, // HSUBPDrr 202399067U, // HSUBPSrm 34626907U, // HSUBPSrr 41726U, // IDIV16m 25342U, // IDIV16r 74494U, // IDIV32m 25342U, // IDIV32r 90878U, // IDIV64m 25342U, // IDIV64r 107262U, // IDIV8m 25342U, // IDIV8r 34890U, // ILD_F16m 67658U, // ILD_F32m 84042U, // ILD_F64m 0U, // ILD_Fp16m32 0U, // ILD_Fp16m64 0U, // ILD_Fp16m80 0U, // ILD_Fp32m32 0U, // ILD_Fp32m64 0U, // ILD_Fp32m80 0U, // ILD_Fp64m32 0U, // ILD_Fp64m64 0U, // ILD_Fp64m80 37895U, // IMUL16m 21511U, // IMUL16r 68178951U, // IMUL16rm 2651870215U, // IMUL16rmi 2651870215U, // IMUL16rmi8 34624519U, // IMUL16rr 2517652487U, // IMUL16rri 2517652487U, // IMUL16rri8 70663U, // IMUL32m 21511U, // IMUL32r 101733383U, // IMUL32rm 2551206919U, // IMUL32rmi 2551206919U, // IMUL32rmi8 34624519U, // IMUL32rr 2517652487U, // IMUL32rri 2517652487U, // IMUL32rri8 87047U, // IMUL64m 21511U, // IMUL64r 135287815U, // IMUL64rm 2584761351U, // IMUL64rmi32 2584761351U, // IMUL64rmi8 34624519U, // IMUL64rr 2517652487U, // IMUL64rri32 2517652487U, // IMUL64rri8 103431U, // IMUL8m 21511U, // IMUL8r 338050U, // IN16ri 12192U, // IN16rr 338203U, // IN32ri 12202U, // IN32rr 337948U, // IN8ri 12182U, // IN8rr 34519U, // INC16m 18135U, // INC16r 18135U, // INC16r_alt 67287U, // INC32m 18135U, // INC32r 18135U, // INC32r_alt 83671U, // INC64m 18135U, // INC64r 100055U, // INC8m 18135U, // INC8r 19535U, // INCSSPD 22562U, // INCSSPQ 8734053U, // INSB 2416992082U, // INSERTPSrm 2182111058U, // INSERTPSrr 34658699U, // INSERTQ 2182142347U, // INSERTQI 8752881U, // INSL 8775117U, // INSW 336454U, // INT 10968U, // INT1 10999U, // INT3 11564U, // INTO 11235U, // INVD 336618064U, // INVEPT32 336618064U, // INVEPT64 102974U, // INVLPG 12148U, // INVLPGA32 12165U, // INVLPGA64 336611364U, // INVPCID32 336611364U, // INVPCID64 336611380U, // INVVPID32 336611380U, // INVVPID64 11915U, // IRET16 11223U, // IRET32 11689U, // IRET64 38247U, // ISTT_FP16m 71015U, // ISTT_FP32m 87399U, // ISTT_FP64m 0U, // ISTT_Fp16m32 0U, // ISTT_Fp16m64 0U, // ISTT_Fp16m80 0U, // ISTT_Fp32m32 0U, // ISTT_Fp32m64 0U, // ISTT_Fp32m80 0U, // ISTT_Fp64m32 0U, // ISTT_Fp64m64 0U, // ISTT_Fp64m80 41638U, // IST_F16m 74406U, // IST_F32m 38240U, // IST_FP16m 71008U, // IST_FP32m 87392U, // IST_FP64m 0U, // IST_Fp16m32 0U, // IST_Fp16m64 0U, // IST_Fp16m80 0U, // IST_Fp32m32 0U, // IST_Fp32m64 0U, // IST_Fp32m80 0U, // IST_Fp64m32 0U, // IST_Fp64m64 0U, // IST_Fp64m80 184605U, // JAE_1 184605U, // JAE_2 184605U, // JAE_4 181073U, // JA_1 181073U, // JA_2 181073U, // JA_4 184625U, // JBE_1 184625U, // JBE_2 184625U, // JBE_4 181304U, // JB_1 181304U, // JB_2 181304U, // JB_4 190286U, // JCXZ 190279U, // JECXZ 184690U, // JE_1 184690U, // JE_2 184690U, // JE_4 184661U, // JGE_1 184661U, // JGE_2 184661U, // JGE_4 184890U, // JG_1 184890U, // JG_2 184890U, // JG_4 184694U, // JLE_1 184694U, // JLE_2 184694U, // JLE_4 185269U, // JL_1 185269U, // JL_2 185269U, // JL_4 38138U, // JMP16m 38138U, // JMP16m_NT 21754U, // JMP16r 21754U, // JMP16r_NT 70906U, // JMP32m 70906U, // JMP32m_NT 21754U, // JMP32r 21754U, // JMP32r_NT 87290U, // JMP64m 87290U, // JMP64m_NT 21754U, // JMP64r 21754U, // JMP64r_NT 185594U, // JMP_1 185594U, // JMP_2 185594U, // JMP_4 184714U, // JNE_1 184714U, // JNE_2 184714U, // JNE_4 185502U, // JNO_1 185502U, // JNO_2 185502U, // JNO_4 185622U, // JNP_1 185622U, // JNP_2 185622U, // JNP_4 187262U, // JNS_1 187262U, // JNS_2 187262U, // JNS_4 185498U, // JO_1 185498U, // JO_2 185498U, // JO_4 185577U, // JP_1 185577U, // JP_2 185577U, // JP_4 190292U, // JRCXZ 187250U, // JS_1 187250U, // JS_2 187250U, // JS_4 2517648360U, // KADDBrr 2517649286U, // KADDDrr 2517653081U, // KADDQrr 2517656561U, // KADDWrr 2517648375U, // KANDBrr 2517649310U, // KANDDrr 2517648547U, // KANDNBrr 2517649603U, // KANDNDrr 2517653504U, // KANDNQrr 2517656835U, // KANDNWrr 2517653176U, // KANDQrr 2517656585U, // KANDWrr 370165312U, // KMOVBkk 537937472U, // KMOVBkm 370165312U, // KMOVBkr 1148480U, // KMOVBmk 370165312U, // KMOVBrk 370167921U, // KMOVDkk 403722353U, // KMOVDkm 370167921U, // KMOVDkr 1118321U, // KMOVDmk 370167921U, // KMOVDrk 370170415U, // KMOVQkk 437279279U, // KMOVQkm 370170415U, // KMOVQkr 1137199U, // KMOVQmk 370170415U, // KMOVQrk 370173650U, // KMOVWkk 504391378U, // KMOVWkm 370173650U, // KMOVWkr 1091282U, // KMOVWmk 370173650U, // KMOVWrk 370165197U, // KNOTBrr 370167777U, // KNOTDrr 370170236U, // KNOTQrr 370173497U, // KNOTWrr 2517648663U, // KORBrr 2517650709U, // KORDrr 2517653686U, // KORQrr 370165234U, // KORTESTBrr 370167814U, // KORTESTDrr 370170282U, // KORTESTQrr 370173534U, // KORTESTWrr 2517656915U, // KORWrr 2517648463U, // KSHIFTLBri 2517649530U, // KSHIFTLDri 2517653446U, // KSHIFTLQri 2517656777U, // KSHIFTLWri 2517648693U, // KSHIFTRBri 2517650762U, // KSHIFTRDri 2517653739U, // KSHIFTRQri 2517656945U, // KSHIFTRWri 370165226U, // KTESTBrr 370167806U, // KTESTDrr 370170274U, // KTESTQrr 370173526U, // KTESTWrr 2517656465U, // KUNPCKBWrr 2517653118U, // KUNPCKDQrr 2517651634U, // KUNPCKWDrr 2517648669U, // KXNORBrr 2517650715U, // KXNORDrr 2517653692U, // KXNORQrr 2517656921U, // KXNORWrr 2517648677U, // KXORBrr 2517650738U, // KXORDrr 2517653715U, // KXORQrr 2517656929U, // KXORWrr 11357U, // LAHF 504388218U, // LAR16rm 370170490U, // LAR16rr 504388218U, // LAR32rm 370170490U, // LAR32rr 504388218U, // LAR64rm 370170490U, // LAR64rr 336618202U, // LDDQUrm 72424U, // LDMXCSR 772823860U, // LDS16rm 772823860U, // LDS32rm 12245U, // LD_F0 10938U, // LD_F1 116797U, // LD_F32m 133181U, // LD_F64m 313405U, // LD_F80m 0U, // LD_Fp032 0U, // LD_Fp064 0U, // LD_Fp080 0U, // LD_Fp132 0U, // LD_Fp164 0U, // LD_Fp180 0U, // LD_Fp32m 0U, // LD_Fp32m64 0U, // LD_Fp32m80 0U, // LD_Fp64m 0U, // LD_Fp64m80 0U, // LD_Fp80m 18493U, // LD_Frr 470827852U, // LEA16r 470827852U, // LEA32r 470827852U, // LEA64_32r 470827852U, // LEA64r 11344U, // LEAVE 11344U, // LEAVE64 772823899U, // LES16rm 772823899U, // LES32rm 11260U, // LFENCE 772823912U, // LFS16rm 772823912U, // LFS32rm 772823912U, // LFS64rm 303606U, // LGDT16m 303606U, // LGDT32m 303606U, // LGDT64m 772823917U, // LGS16rm 772823917U, // LGS32rm 772823917U, // LGS64rm 303618U, // LIDT16m 303618U, // LIDT32m 303618U, // LIDT64m 41486U, // LLDT16m 25102U, // LLDT16r 17368U, // LLWPCB 17368U, // LLWPCB64 42430U, // LMSW16m 26046U, // LMSW16r 11424U, // LOCK_PREFIX 403437U, // LODSB 420111U, // LODSL 436642U, // LODSQ 452806U, // LODSW 185647U, // LOOP 184742U, // LOOPE 184719U, // LOOPNE 21030U, // LRETIL 22410U, // LRETIQ 21030U, // LRETIW 11378U, // LRETL 11683U, // LRETQ 11378U, // LRETW 504386548U, // LSL16rm 370168820U, // LSL16rr 504386548U, // LSL32rm 370168820U, // LSL32rr 504386548U, // LSL64rm 370168820U, // LSL64rr 772825416U, // LSS16rm 772825416U, // LSS32rm 772825416U, // LSS64rm 39686U, // LTRm 23302U, // LTRr 2551208822U, // LWPINS32rmi 2517654390U, // LWPINS32rri 2551208822U, // LWPINS64rmi 2517654390U, // LWPINS64rri 2551206812U, // LWPVAL32rmi 2517652380U, // LWPVAL32rri 2551206812U, // LWPVAL64rmi 2517652380U, // LWPVAL64rri 504390200U, // LZCNT16rm 370172472U, // LZCNT16rr 403726904U, // LZCNT32rm 370172472U, // LZCNT32rr 437281336U, // LZCNT64rm 370172472U, // LZCNT64rr 370172642U, // MASKMOVDQU 370172642U, // MASKMOVDQU64 202394814U, // MAXCPDrm 34622654U, // MAXCPDrr 202399649U, // MAXCPSrm 34627489U, // MAXCPSrr 235949982U, // MAXCSDrm 34623390U, // MAXCSDrr 269509072U, // MAXCSSrm 34628048U, // MAXCSSrr 202394814U, // MAXPDrm 34622654U, // MAXPDrr 202399649U, // MAXPSrm 34627489U, // MAXPSrr 235949982U, // MAXSDrm 235949982U, // MAXSDrm_Int 34623390U, // MAXSDrr 34623390U, // MAXSDrr_Int 269509072U, // MAXSSrm 269509072U, // MAXSSrm_Int 34628048U, // MAXSSrr 34628048U, // MAXSSrr_Int 11267U, // MFENCE 202394618U, // MINCPDrm 34622458U, // MINCPDrr 202399429U, // MINCPSrm 34627269U, // MINCPSrr 235949808U, // MINCSDrm 34623216U, // MINCSDrr 269508955U, // MINCSSrm 34627931U, // MINCSSrr 202394618U, // MINPDrm 34622458U, // MINPDrr 202399429U, // MINPSrm 34627269U, // MINPSrr 235949808U, // MINSDrm 235949808U, // MINSDrm_Int 34623216U, // MINSDrr 34623216U, // MINSDrr_Int 269508955U, // MINSSrm 269508955U, // MINSSrm_Int 34627931U, // MINSSrr 34627931U, // MINSSrr_Int 672158394U, // MMX_CVTPD2PIirm 370168506U, // MMX_CVTPD2PIirr 437275044U, // MMX_CVTPI2PDirm 370166180U, // MMX_CVTPI2PDirr 135289951U, // MMX_CVTPI2PSirm 34626655U, // MMX_CVTPI2PSirr 605049551U, // MMX_CVTPS2PIirm 370168527U, // MMX_CVTPS2PIirr 672158383U, // MMX_CVTTPD2PIirm 370168495U, // MMX_CVTTPD2PIirr 605049540U, // MMX_CVTTPS2PIirm 370168516U, // MMX_CVTTPS2PIirr 11862U, // MMX_EMMS 370170412U, // MMX_MASKMOVQ 370170412U, // MMX_MASKMOVQ64 1137200U, // MMX_MOVD64from64rm 370170416U, // MMX_MOVD64from64rr 370167922U, // MMX_MOVD64grr 1118322U, // MMX_MOVD64mr 403722354U, // MMX_MOVD64rm 370167922U, // MMX_MOVD64rr 437279280U, // MMX_MOVD64to64rm 370170416U, // MMX_MOVD64to64rr 370169282U, // MMX_MOVDQ2Qrr 370169282U, // MMX_MOVFR642Qrr 1137012U, // MMX_MOVNTQmr 370169391U, // MMX_MOVQ2DQrr 370169391U, // MMX_MOVQ2FR64rr 1137200U, // MMX_MOVQ64mr 437279280U, // MMX_MOVQ64rm 370170416U, // MMX_MOVQ64rr 370170416U, // MMX_MOVQ64rr_REV 437273929U, // MMX_PABSBrm 370165065U, // MMX_PABSBrr 437276238U, // MMX_PABSDrm 370167374U, // MMX_PABSDrr 437282181U, // MMX_PABSWrm 370173317U, // MMX_PABSWrr 135291951U, // MMX_PACKSSDWirm 34628655U, // MMX_PACKSSDWirr 135284302U, // MMX_PACKSSWBirm 34621006U, // MMX_PACKSSWBirr 135284313U, // MMX_PACKUSWBirm 34621017U, // MMX_PACKUSWBirr 135283696U, // MMX_PADDBirm 34620400U, // MMX_PADDBirr 135284622U, // MMX_PADDDirm 34621326U, // MMX_PADDDirr 135288417U, // MMX_PADDQirm 34625121U, // MMX_PADDQirr 135284058U, // MMX_PADDSBirm 34620762U, // MMX_PADDSBirr 135292342U, // MMX_PADDSWirm 34629046U, // MMX_PADDSWirr 135284113U, // MMX_PADDUSBirm 34620817U, // MMX_PADDUSBirr 135292428U, // MMX_PADDUSWirm 34629132U, // MMX_PADDUSWirr 135291897U, // MMX_PADDWirm 34628601U, // MMX_PADDWirr 2282773158U, // MMX_PALIGNRrmi 2182109862U, // MMX_PALIGNRrri 135287933U, // MMX_PANDNirm 34624637U, // MMX_PANDNirr 135284917U, // MMX_PANDirm 34621621U, // MMX_PANDirr 135283761U, // MMX_PAVGBirm 34620465U, // MMX_PAVGBirr 135292018U, // MMX_PAVGWirm 34628722U, // MMX_PAVGWirr 135283917U, // MMX_PCMPEQBirm 34620621U, // MMX_PCMPEQBirr 135285967U, // MMX_PCMPEQDirm 34622671U, // MMX_PCMPEQDirr 135292189U, // MMX_PCMPEQWirm 34628893U, // MMX_PCMPEQWirr 135284154U, // MMX_PCMPGTBirm 34620858U, // MMX_PCMPGTBirr 135286724U, // MMX_PCMPGTDirm 34623428U, // MMX_PCMPGTDirr 135292454U, // MMX_PCMPGTWirm 34629158U, // MMX_PCMPGTWirr 2517656956U, // MMX_PEXTRWrr 135284606U, // MMX_PHADDDrm 34621310U, // MMX_PHADDDrr 135292332U, // MMX_PHADDSWrm 34629036U, // MMX_PHADDSWrr 135291881U, // MMX_PHADDWrm 34628585U, // MMX_PHADDWrr 135284547U, // MMX_PHSUBDrm 34621251U, // MMX_PHSUBDrr 135292313U, // MMX_PHSUBSWrm 34629017U, // MMX_PHSUBSWrr 135291827U, // MMX_PHSUBWrm 34628531U, // MMX_PHSUBWrr 2215667049U, // MMX_PINSRWrm 2182112617U, // MMX_PINSRWrr 135292301U, // MMX_PMADDUBSWrm 34629005U, // MMX_PMADDUBSWrr 135286941U, // MMX_PMADDWDirm 34623645U, // MMX_PMADDWDirr 135292445U, // MMX_PMAXSWirm 34629149U, // MMX_PMAXSWirr 135284262U, // MMX_PMAXUBirm 34620966U, // MMX_PMAXUBirr 135292363U, // MMX_PMINSWirm 34629067U, // MMX_PMINSWirr 135284230U, // MMX_PMINUBirm 34620934U, // MMX_PMINUBirr 370164797U, // MMX_PMOVMSKBrr 135292386U, // MMX_PMULHRSWrm 34629090U, // MMX_PMULHRSWrr 135292521U, // MMX_PMULHUWirm 34629225U, // MMX_PMULHUWirr 135292047U, // MMX_PMULHWirm 34628751U, // MMX_PMULHWirr 135292089U, // MMX_PMULLWirm 34628793U, // MMX_PMULLWirr 135288674U, // MMX_PMULUDQirm 34625378U, // MMX_PMULUDQirr 135289520U, // MMX_PORirm 34626224U, // MMX_PORirr 135291744U, // MMX_PSADBWirm 34628448U, // MMX_PSADBWirr 135283752U, // MMX_PSHUFBrm 34620456U, // MMX_PSHUFBrr 2584765545U, // MMX_PSHUFWmi 2517656681U, // MMX_PSHUFWri 135283884U, // MMX_PSIGNBrm 34620588U, // MMX_PSIGNBrr 135284958U, // MMX_PSIGNDrm 34621662U, // MMX_PSIGNDrr 135292172U, // MMX_PSIGNWrm 34628876U, // MMX_PSIGNWrr 705710161U, // MMX_PSLLDri 135284817U, // MMX_PSLLDrm 34621521U, // MMX_PSLLDrr 705714086U, // MMX_PSLLQri 135288742U, // MMX_PSLLQrm 34625446U, // MMX_PSLLQrr 705717425U, // MMX_PSLLWri 135292081U, // MMX_PSLLWrm 34628785U, // MMX_PSLLWrr 705709862U, // MMX_PSRADri 135284518U, // MMX_PSRADrm 34621222U, // MMX_PSRADrr 705717068U, // MMX_PSRAWri 135291724U, // MMX_PSRAWrm 34628428U, // MMX_PSRAWrr 705710186U, // MMX_PSRLDri 135284842U, // MMX_PSRLDrm 34621546U, // MMX_PSRLDrr 705714111U, // MMX_PSRLQri 135288767U, // MMX_PSRLQrm 34625471U, // MMX_PSRLQrr 705717442U, // MMX_PSRLWri 135292098U, // MMX_PSRLWrm 34628802U, // MMX_PSRLWrr 135283665U, // MMX_PSUBBirm 34620369U, // MMX_PSUBBirr 135284556U, // MMX_PSUBDirm 34621260U, // MMX_PSUBDirr 135288315U, // MMX_PSUBQirm 34625019U, // MMX_PSUBQirr 135284049U, // MMX_PSUBSBirm 34620753U, // MMX_PSUBSBirr 135292323U, // MMX_PSUBSWirm 34629027U, // MMX_PSUBSWirr 135284103U, // MMX_PSUBUSBirm 34620807U, // MMX_PSUBUSBirr 135292418U, // MMX_PSUBUSWirm 34629122U, // MMX_PSUBUSWirr 135291836U, // MMX_PSUBWirm 34628540U, // MMX_PSUBWirr 135291782U, // MMX_PUNPCKHBWirm 34628486U, // MMX_PUNPCKHBWirr 135288435U, // MMX_PUNPCKHDQirm 34625139U, // MMX_PUNPCKHDQirr 135286951U, // MMX_PUNPCKHWDirm 34623655U, // MMX_PUNPCKHWDirr 101737372U, // MMX_PUNPCKLBWirm 34628508U, // MMX_PUNPCKLBWirr 101734034U, // MMX_PUNPCKLDQirm 34625170U, // MMX_PUNPCKLDQirr 101732541U, // MMX_PUNPCKLWDirm 34623677U, // MMX_PUNPCKLWDirr 135289558U, // MMX_PXORirm 34626262U, // MMX_PXORirr 12220U, // MONITORXrrr 11732U, // MONITORrrr 11499U, // MONTMUL 469170U, // MOV16ao16 469170U, // MOV16ao32 469148U, // MOV16ao64 1090328U, // MOV16mi 1090328U, // MOV16mr 1090328U, // MOV16ms 9904920U, // MOV16o16a 9904920U, // MOV16o32a 9902886U, // MOV16o64a 370172696U, // MOV16ri 370172696U, // MOV16ri_alt 504390424U, // MOV16rm 370172696U, // MOV16rr 370172696U, // MOV16rr_REV 370172696U, // MOV16rs 504390424U, // MOV16sm 370172696U, // MOV16sr 485712U, // MOV32ao16 485712U, // MOV32ao32 485688U, // MOV32ao64 370172696U, // MOV32cr 370172696U, // MOV32dr 1123096U, // MOV32mi 1123096U, // MOV32mr 10969880U, // MOV32o16a 10969880U, // MOV32o32a 10967846U, // MOV32o64a 370172696U, // MOV32rc 370172696U, // MOV32rd 370172696U, // MOV32ri 370172696U, // MOV32ri_alt 403727128U, // MOV32rm 370172696U, // MOV32rr 370172696U, // MOV32rr_REV 370172696U, // MOV32rs 370172696U, // MOV32sr 502224U, // MOV64ao32 502200U, // MOV64ao64 370172696U, // MOV64cr 370172696U, // MOV64dr 1139480U, // MOV64mi32 1139480U, // MOV64mr 12034840U, // MOV64o32a 12032806U, // MOV64o64a 370172696U, // MOV64rc 370172696U, // MOV64rd 370170662U, // MOV64ri 370172696U, // MOV64ri32 437281560U, // MOV64rm 370172696U, // MOV64rr 370172696U, // MOV64rr_REV 370172696U, // MOV64rs 370172696U, // MOV64sr 437279280U, // MOV64toPQIrm 370170416U, // MOV64toPQIrr 437279280U, // MOV64toSDrm 370170416U, // MOV64toSDrr 518220U, // MOV8ao16 518220U, // MOV8ao32 518198U, // MOV8ao64 1155864U, // MOV8mi 1155864U, // MOV8mr 1155864U, // MOV8mr_NOREX 13099800U, // MOV8o16a 13099800U, // MOV8o32a 13097766U, // MOV8o64a 370172696U, // MOV8ri 370172696U, // MOV8ri_alt 537944856U, // MOV8rm 537944856U, // MOV8rm_NOREX 370172696U, // MOV8rr 370172696U, // MOV8rr_NOREX 370172696U, // MOV8rr_REV 1575562U, // MOVAPDmr 672156298U, // MOVAPDrm 370166410U, // MOVAPDrr 370166410U, // MOVAPDrr_REV 1580346U, // MOVAPSmr 672161082U, // MOVAPSrm 370171194U, // MOVAPSrr 370171194U, // MOVAPSrr_REV 1085758U, // MOVBE16mr 504385854U, // MOVBE16rm 1118526U, // MOVBE32mr 403722558U, // MOVBE32rm 1134910U, // MOVBE64mr 437276990U, // MOVBE64rm 605050224U, // MOVDDUPrm 370169200U, // MOVDDUPrr 403722354U, // MOVDI2PDIrm 370167922U, // MOVDI2PDIrr 403722354U, // MOVDI2SSrm 370167922U, // MOVDI2SSrr 806372257U, // MOVDIR64B16 806372257U, // MOVDIR64B32 806372257U, // MOVDIR64B64 1118954U, // MOVDIRI32 1135338U, // MOVDIRI64 1196897U, // MOVDQAmr 336610145U, // MOVDQArm 370164577U, // MOVDQArr 370164577U, // MOVDQArr_REV 1204966U, // MOVDQUmr 336618214U, // MOVDQUrm 370172646U, // MOVDQUrr 370172646U, // MOVDQUrr_REV 34627178U, // MOVHLPSrr 1182605U, // MOVHPDmr 235948941U, // MOVHPDrm 1187414U, // MOVHPSmr 235953750U, // MOVHPSrm 34627148U, // MOVLHPSrr 1182655U, // MOVLPDmr 235948991U, // MOVLPDrm 1187474U, // MOVLPSmr 235953810U, // MOVLPSrm 370166678U, // MOVMSKPDrr 370171487U, // MOVMSKPSrr 336610134U, // MOVNTDQArm 1578779U, // MOVNTDQmr 1135473U, // MOVNTI_64mr 1119089U, // MOVNTImr 1576058U, // MOVNTPDmr 1580872U, // MOVNTPSmr 1183586U, // MOVNTSD 1171861U, // MOVNTSS 1118322U, // MOVPDI2DImr 370167922U, // MOVPDI2DIrr 1137200U, // MOVPQI2QImr 370170416U, // MOVPQI2QIrr 1137200U, // MOVPQIto64mr 370170416U, // MOVPQIto64rr 437279280U, // MOVQI2PQIrm 840254883U, // MOVSB 1183637U, // MOVSDmr 605048725U, // MOVSDrm 34623381U, // MOVSDrr 34623381U, // MOVSDrr_REV 1137200U, // MOVSDto64mr 370170416U, // MOVSDto64rr 672159098U, // MOVSHDUPrm 370169210U, // MOVSHDUPrr 873828245U, // MOVSL 672159109U, // MOVSLDUPrm 370169221U, // MOVSLDUPrr 907565369U, // MOVSQ 1118322U, // MOVSS2DImr 370167922U, // MOVSS2DIrr 1171912U, // MOVSSmr 638607816U, // MOVSSrm 34628040U, // MOVSSrr 34628040U, // MOVSSrr_REV 940959253U, // MOVSW 504391463U, // MOVSX16rm16 537945895U, // MOVSX16rm8 370173735U, // MOVSX16rr16 370173735U, // MOVSX16rr8 504391463U, // MOVSX32rm16 537945895U, // MOVSX32rm8 537945895U, // MOVSX32rm8_NOREX 370173735U, // MOVSX32rr16 370173735U, // MOVSX32rr8 370173735U, // MOVSX32rr8_NOREX 504391463U, // MOVSX64rm16 403722517U, // MOVSX64rm32 537945895U, // MOVSX64rm8 370173735U, // MOVSX64rr16 370168085U, // MOVSX64rr32 370173735U, // MOVSX64rr8 1576086U, // MOVUPDmr 672156822U, // MOVUPDrm 370166934U, // MOVUPDrr 370166934U, // MOVUPDrr_REV 1580921U, // MOVUPSmr 672161657U, // MOVUPSrm 370171769U, // MOVUPSrr 370171769U, // MOVUPSrr_REV 370170416U, // MOVZPQILo2PQIrr 504391478U, // MOVZX16rm16 537945910U, // MOVZX16rm8 370173750U, // MOVZX16rr16 370173750U, // MOVZX16rr8 504391478U, // MOVZX32rm16 537945910U, // MOVZX32rm8 537945910U, // MOVZX32rm8_NOREX 370173750U, // MOVZX32rr16 370173750U, // MOVZX32rr8 370173750U, // MOVZX32rr8_NOREX 504391478U, // MOVZX64rm16 537945910U, // MOVZX64rm8 370173750U, // MOVZX64rr16 370173750U, // MOVZX64rr8 2450547561U, // MPSADBWrmi 2182112105U, // MPSADBWrri 37889U, // MUL16m 21505U, // MUL16r 70657U, // MUL32m 21505U, // MUL32r 87041U, // MUL64m 21505U, // MUL64r 103425U, // MUL8m 21505U, // MUL8r 202394551U, // MULPDrm 34622391U, // MULPDrr 202399370U, // MULPSrm 34627210U, // MULPSrr 235949786U, // MULSDrm 235949786U, // MULSDrm_Int 34623194U, // MULSDrr 34623194U, // MULSDrr_Int 269508934U, // MULSSrm 269508934U, // MULSSrm_Int 34627910U, // MULSSrr 34627910U, // MULSSrr_Int 2517657353U, // MULX32rm 2517657353U, // MULX32rr 2517657353U, // MULX64rm 2517657353U, // MULX64rr 119808U, // MUL_F32m 136192U, // MUL_F64m 37894U, // MUL_FI16m 70662U, // MUL_FI32m 21741U, // MUL_FPrST0 21504U, // MUL_FST0r 0U, // MUL_Fp32 0U, // MUL_Fp32m 0U, // MUL_Fp64 0U, // MUL_Fp64m 0U, // MUL_Fp64m32 0U, // MUL_Fp80 0U, // MUL_Fp80m32 0U, // MUL_Fp80m64 0U, // MUL_FpI16m32 0U, // MUL_FpI16m64 0U, // MUL_FpI16m80 0U, // MUL_FpI32m32 0U, // MUL_FpI32m64 0U, // MUL_FpI32m80 2118656U, // MUL_FrST0 12229U, // MWAITXrrr 11927U, // MWAITrr 37420U, // NEG16m 21036U, // NEG16r 70188U, // NEG32m 21036U, // NEG32r 86572U, // NEG64m 21036U, // NEG64r 102956U, // NEG8m 21036U, // NEG8r 11600U, // NOOP 38186U, // NOOP18_16m4 38186U, // NOOP18_16m5 38186U, // NOOP18_16m6 38186U, // NOOP18_16m7 21802U, // NOOP18_16r4 21802U, // NOOP18_16r5 21802U, // NOOP18_16r6 21802U, // NOOP18_16r7 70954U, // NOOP18_m4 70954U, // NOOP18_m5 70954U, // NOOP18_m6 70954U, // NOOP18_m7 21802U, // NOOP18_r4 21802U, // NOOP18_r5 21802U, // NOOP18_r6 21802U, // NOOP18_r7 739300650U, // NOOP19rr 70954U, // NOOPL 70954U, // NOOPL_19 70954U, // NOOPL_1d 70954U, // NOOPL_1e 21802U, // NOOPLr 87338U, // NOOPQ 21802U, // NOOPQr 38186U, // NOOPW 38186U, // NOOPW_19 38186U, // NOOPW_1c 38186U, // NOOPW_1d 38186U, // NOOPW_1e 21802U, // NOOPWr 41547U, // NOT16m 25163U, // NOT16r 74315U, // NOT32m 25163U, // NOT32r 90699U, // NOT64m 25163U, // NOT64r 107083U, // NOT8m 25163U, // NOT8r 26772U, // OR16i16 1088177U, // OR16mi 1088177U, // OR16mi8 1088177U, // OR16mr 34658993U, // OR16ri 34658993U, // OR16ri8 68213425U, // OR16rm 34658993U, // OR16rr 34626225U, // OR16rr_REV 26927U, // OR32i32 1120945U, // OR32mi 1120945U, // OR32mi8 1120945U, // OR32mr 34658993U, // OR32ri 34658993U, // OR32ri8 101767857U, // OR32rm 34658993U, // OR32rr 34626225U, // OR32rr_REV 27055U, // OR64i32 1137329U, // OR64mi32 1137329U, // OR64mi8 1137329U, // OR64mr 34658993U, // OR64ri32 34658993U, // OR64ri8 135322289U, // OR64rm 34658993U, // OR64rr 34626225U, // OR64rr_REV 26670U, // OR8i8 1153713U, // OR8mi 1153713U, // OR8mi8 1153713U, // OR8mr 34658993U, // OR8ri 34658993U, // OR8ri8 168876721U, // OR8rm 34658993U, // OR8rr 34626225U, // OR8rr_REV 202394677U, // ORPDrm 34622517U, // ORPDrr 202399496U, // ORPSrm 34627336U, // ORPSrr 9773767U, // OUT16ir 12050U, // OUT16rr 10822343U, // OUT32ir 12104U, // OUT32rr 12919495U, // OUT8ir 11429U, // OUT8rr 403930U, // OUTSB 420325U, // OUTSL 453104U, // OUTSW 336610633U, // PABSBrm 370165065U, // PABSBrr 336612942U, // PABSDrm 370167374U, // PABSDrr 336618885U, // PABSWrm 370173317U, // PABSWrr 303064111U, // PACKSSDWrm 34628655U, // PACKSSDWrr 303056462U, // PACKSSWBrm 34621006U, // PACKSSWBrr 303064122U, // PACKUSDWrm 34628666U, // PACKUSDWrr 303056473U, // PACKUSWBrm 34621017U, // PACKUSWBrr 303055856U, // PADDBrm 34620400U, // PADDBrr 303056782U, // PADDDrm 34621326U, // PADDDrr 303060577U, // PADDQrm 34625121U, // PADDQrr 303056218U, // PADDSBrm 34620762U, // PADDSBrr 303064502U, // PADDSWrm 34629046U, // PADDSWrr 303056273U, // PADDUSBrm 34620817U, // PADDUSBrr 303064588U, // PADDUSWrm 34629132U, // PADDUSWrr 303064057U, // PADDWrm 34628601U, // PADDWrr 2450545318U, // PALIGNRrmi 2182109862U, // PALIGNRrri 303060093U, // PANDNrm 34624637U, // PANDNrr 303057077U, // PANDrm 34621621U, // PANDrr 11338U, // PAUSE 303055921U, // PAVGBrm 34620465U, // PAVGBrr 135284122U, // PAVGUSBrm 34620826U, // PAVGUSBrr 303064178U, // PAVGWrm 34628722U, // PAVGWrr 303056431U, // PBLENDVBrm0 34620975U, // PBLENDVBrr0 2450547740U, // PBLENDWrmi 2182112284U, // PBLENDWrri 2450544365U, // PCLMULQDQrm 2182108909U, // PCLMULQDQrr 303056077U, // PCMPEQBrm 34620621U, // PCMPEQBrr 303058127U, // PCMPEQDrm 34622671U, // PCMPEQDrr 303061090U, // PCMPEQQrm 34625634U, // PCMPEQQrr 303064349U, // PCMPEQWrm 34628893U, // PCMPEQWrr 2484097780U, // PCMPESTRIrm 2517652212U, // PCMPESTRIrr 2484098142U, // PCMPESTRMrm 2517652574U, // PCMPESTRMrr 303056314U, // PCMPGTBrm 34620858U, // PCMPGTBrr 303058884U, // PCMPGTDrm 34623428U, // PCMPGTDrr 303061335U, // PCMPGTQrm 34625879U, // PCMPGTQrr 303064614U, // PCMPGTWrm 34629158U, // PCMPGTWrr 2484097792U, // PCMPISTRIrm 2517652224U, // PCMPISTRIrr 2484098154U, // PCMPISTRMrm 2517652586U, // PCMPISTRMrr 11383U, // PCONFIG 2517652699U, // PDEP32rm 2517652699U, // PDEP32rr 2517652699U, // PDEP64rm 2517652699U, // PDEP64rr 2517656268U, // PEXT32rm 2517656268U, // PEXT32rr 2517656268U, // PEXT64rm 2517656268U, // PEXT64rr 2148631872U, // PEXTRBmr 2517648704U, // PEXTRBrr 2148601173U, // PEXTRDmr 2517650773U, // PEXTRDrr 2148620534U, // PEXTRQmr 2517653750U, // PEXTRQrr 2148574588U, // PEXTRWmr 2517656956U, // PEXTRWrr 2517656956U, // PEXTRWrr_REV 437274653U, // PF2IDrm 370165789U, // PF2IDrr 437281943U, // PF2IWrm 370173079U, // PF2IWrr 135284353U, // PFACCrm 34621057U, // PFACCrr 135284585U, // PFADDrm 34621289U, // PFADDrr 135288705U, // PFCMPEQrm 34625409U, // PFCMPEQrr 135287130U, // PFCMPGErm 34623834U, // PFCMPGErr 135291423U, // PFCMPGTrm 34628127U, // PFCMPGTrr 135292654U, // PFMAXrm 34629358U, // PFMAXrr 135287948U, // PFMINrm 34624652U, // PFMINrr 135287807U, // PFMULrm 34624511U, // PFMULrr 135284360U, // PFNACCrm 34621064U, // PFNACCrr 135284368U, // PFPNACCrm 34621072U, // PFPNACCrr 135282735U, // PFRCPIT1rm 34619439U, // PFRCPIT1rr 135282844U, // PFRCPIT2rm 34619548U, // PFRCPIT2rr 437277901U, // PFRCPrm 370169037U, // PFRCPrr 135282745U, // PFRSQIT1rm 34619449U, // PFRSQIT1rr 437281398U, // PFRSQRTrm 370172534U, // PFRSQRTrr 135289476U, // PFSUBRrm 34626180U, // PFSUBRrr 135284247U, // PFSUBrm 34620951U, // PFSUBrr 303056766U, // PHADDDrm 34621310U, // PHADDDrr 303064492U, // PHADDSWrm 34629036U, // PHADDSWrr 303064041U, // PHADDWrm 34628585U, // PHADDWrr 336619150U, // PHMINPOSUWrm 370173582U, // PHMINPOSUWrr 303056707U, // PHSUBDrm 34621251U, // PHSUBDrr 303064473U, // PHSUBSWrm 34629017U, // PHSUBSWrr 303063987U, // PHSUBWrm 34628531U, // PHSUBWrr 437274625U, // PI2FDrm 370165761U, // PI2FDrr 437281890U, // PI2FWrm 370173026U, // PI2FWrr 2316322093U, // PINSRBrm 2182104365U, // PINSRBrr 2249215298U, // PINSRDrm 2182106434U, // PINSRDrr 2282772707U, // PINSRQrm 2182109411U, // PINSRQrr 2215667049U, // PINSRWrm 2182112617U, // PINSRWrr 303064461U, // PMADDUBSWrm 34629005U, // PMADDUBSWrr 303059101U, // PMADDWDrm 34623645U, // PMADDWDrr 303056299U, // PMAXSBrm 34620843U, // PMAXSBrr 303058845U, // PMAXSDrm 34623389U, // PMAXSDrr 303064605U, // PMAXSWrm 34629149U, // PMAXSWrr 303056422U, // PMAXUBrm 34620966U, // PMAXUBrr 303058988U, // PMAXUDrm 34623532U, // PMAXUDrr 303064731U, // PMAXUWrm 34629275U, // PMAXUWrr 303056227U, // PMINSBrm 34620771U, // PMINSBrr 303058671U, // PMINSDrm 34623215U, // PMINSDrr 303064523U, // PMINSWrm 34629067U, // PMINSWrr 303056390U, // PMINUBrm 34620934U, // PMINUBrr 303058970U, // PMINUDrm 34623514U, // PMINUDrr 303064700U, // PMINUWrm 34629244U, // PMINUWrr 370164797U, // PMOVMSKBrr 403720020U, // PMOVSXBDrm 370165588U, // PMOVSXBDrr 504387075U, // PMOVSXBQrm 370169347U, // PMOVSXBQrr 437281732U, // PMOVSXBWrm 370172868U, // PMOVSXBWrr 437278572U, // PMOVSXDQrm 370169708U, // PMOVSXDQrr 437276928U, // PMOVSXWDrm 370168064U, // PMOVSXWDrr 403724892U, // PMOVSXWQrm 370170460U, // PMOVSXWQrr 403720031U, // PMOVZXBDrm 370165599U, // PMOVZXBDrr 504387086U, // PMOVZXBQrm 370169358U, // PMOVZXBQrr 437281743U, // PMOVZXBWrm 370172879U, // PMOVZXBWrr 437278583U, // PMOVZXDQrm 370169719U, // PMOVZXDQrr 437276939U, // PMOVZXWDrm 370168075U, // PMOVZXWDrr 403724903U, // PMOVZXWQrm 370170471U, // PMOVZXWQrr 303060656U, // PMULDQrm 34625200U, // PMULDQrr 303064546U, // PMULHRSWrm 34629090U, // PMULHRSWrr 135292234U, // PMULHRWrm 34628938U, // PMULHRWrr 303064681U, // PMULHUWrm 34629225U, // PMULHUWrr 303064207U, // PMULHWrm 34628751U, // PMULHWrr 303056985U, // PMULLDrm 34621529U, // PMULLDrr 303064249U, // PMULLWrm 34628793U, // PMULLWrr 303060834U, // PMULUDQrm 34625378U, // PMULUDQrr 21813U, // POP16r 38197U, // POP16rmm 21813U, // POP16rmr 21813U, // POP32r 70965U, // POP32rmm 21813U, // POP32rmr 21813U, // POP64r 87349U, // POP64rmm 21813U, // POP64rmr 12024U, // POPA16 11447U, // POPA32 504390192U, // POPCNT16rm 370172464U, // POPCNT16rr 403726896U, // POPCNT32rm 370172464U, // POPCNT32rr 437281328U, // POPCNT64rm 370172464U, // POPCNT64rr 11791U, // POPDS16 11791U, // POPDS32 11806U, // POPES16 11806U, // POPES32 11373U, // POPF16 11202U, // POPF32 11677U, // POPF64 11821U, // POPFS16 11821U, // POPFS32 11821U, // POPFS64 11836U, // POPGS16 11836U, // POPGS32 11836U, // POPGS64 11888U, // POPSS16 11888U, // POPSS32 303061680U, // PORrm 34626224U, // PORrr 102995U, // PREFETCH 99183U, // PREFETCHNTA 98305U, // PREFETCHT0 98339U, // PREFETCHT1 98448U, // PREFETCHT2 107641U, // PREFETCHW 98371U, // PREFETCHWT1 303063904U, // PSADBWrm 34628448U, // PSADBWrr 303055912U, // PSHUFBrm 34620456U, // PSHUFBrr 2484094985U, // PSHUFDmi 2517649417U, // PSHUFDri 2484102277U, // PSHUFHWmi 2517656709U, // PSHUFHWri 2484102303U, // PSHUFLWmi 2517656735U, // PSHUFLWri 303056044U, // PSIGNBrm 34620588U, // PSIGNBrr 303057118U, // PSIGNDrm 34621662U, // PSIGNDrr 303064332U, // PSIGNWrm 34628876U, // PSIGNWrr 705713822U, // PSLLDQri 705710161U, // PSLLDri 303056977U, // PSLLDrm 34621521U, // PSLLDrr 705714086U, // PSLLQri 303060902U, // PSLLQrm 34625446U, // PSLLQrr 705717425U, // PSLLWri 303064241U, // PSLLWrm 34628785U, // PSLLWrr 705709862U, // PSRADri 303056678U, // PSRADrm 34621222U, // PSRADrr 705717068U, // PSRAWri 303063884U, // PSRAWrm 34628428U, // PSRAWrr 705713831U, // PSRLDQri 705710186U, // PSRLDri 303057002U, // PSRLDrm 34621546U, // PSRLDrr 705714111U, // PSRLQri 303060927U, // PSRLQrm 34625471U, // PSRLQrr 705717442U, // PSRLWri 303064258U, // PSRLWrm 34628802U, // PSRLWrr 303055825U, // PSUBBrm 34620369U, // PSUBBrr 303056716U, // PSUBDrm 34621260U, // PSUBDrr 303060475U, // PSUBQrm 34625019U, // PSUBQrr 303056209U, // PSUBSBrm 34620753U, // PSUBSBrr 303064483U, // PSUBSWrm 34629027U, // PSUBSWrr 303056263U, // PSUBUSBrm 34620807U, // PSUBUSBrr 303064578U, // PSUBUSWrm 34629122U, // PSUBUSWrr 303063996U, // PSUBWrm 34628540U, // PSUBWrr 437275282U, // PSWAPDrm 370166418U, // PSWAPDrr 672162458U, // PTESTrm 370172570U, // PTESTrr 86508U, // PTWRITE64m 20972U, // PTWRITE64r 70124U, // PTWRITEm 20972U, // PTWRITEr 303063942U, // PUNPCKHBWrm 34628486U, // PUNPCKHBWrr 303060595U, // PUNPCKHDQrm 34625139U, // PUNPCKHDQrr 303060691U, // PUNPCKHQDQrm 34625235U, // PUNPCKHQDQrr 303059111U, // PUNPCKHWDrm 34623655U, // PUNPCKHWDrr 303063964U, // PUNPCKLBWrm 34628508U, // PUNPCKLBWrr 303060626U, // PUNPCKLDQrm 34625170U, // PUNPCKLDQrr 303060704U, // PUNPCKLQDQrm 34625248U, // PUNPCKLQDQrr 303059133U, // PUNPCKLWDrm 34623677U, // PUNPCKLWDrr 21134U, // PUSH16i8 21134U, // PUSH16r 37518U, // PUSH16rmm 21134U, // PUSH16rmr 21134U, // PUSH32i8 21134U, // PUSH32r 70286U, // PUSH32rmm 21134U, // PUSH32rmr 21134U, // PUSH64i32 21134U, // PUSH64i8 21134U, // PUSH64r 86670U, // PUSH64rmm 21134U, // PUSH64rmr 12017U, // PUSHA16 11440U, // PUSHA32 11775U, // PUSHCS16 11775U, // PUSHCS32 11783U, // PUSHDS16 11783U, // PUSHDS32 11798U, // PUSHES16 11798U, // PUSHES32 11367U, // PUSHF16 11195U, // PUSHF32 11670U, // PUSHF64 11813U, // PUSHFS16 11813U, // PUSHFS32 11813U, // PUSHFS64 11828U, // PUSHGS16 11828U, // PUSHGS32 11828U, // PUSHGS64 11880U, // PUSHSS16 11880U, // PUSHSS32 21134U, // PUSHi16 21134U, // PUSHi32 303061718U, // PXORrm 34626262U, // PXORrr 37803U, // RCL16m1 13669291U, // RCL16mCL 974164907U, // RCL16mi 14701483U, // RCL16r1 13652907U, // RCL16rCL 705713067U, // RCL16ri 70571U, // RCL32m1 13702059U, // RCL32mCL 974197675U, // RCL32mi 14701483U, // RCL32r1 13652907U, // RCL32rCL 705713067U, // RCL32ri 86955U, // RCL64m1 13718443U, // RCL64mCL 974214059U, // RCL64mi 14701483U, // RCL64r1 13652907U, // RCL64rCL 705713067U, // RCL64ri 103339U, // RCL8m1 13734827U, // RCL8mCL 974230443U, // RCL8mi 14701483U, // RCL8r1 13652907U, // RCL8rCL 705713067U, // RCL8ri 672161485U, // RCPPSm 370171597U, // RCPPSr 638607715U, // RCPSSm 269508963U, // RCPSSm_Int 370172259U, // RCPSSr 34627939U, // RCPSSr_Int 14719636U, // RCR16m1 13671060U, // RCR16mCL 974166676U, // RCR16mi 14703252U, // RCR16r1 13654676U, // RCR16rCL 705714836U, // RCR16ri 14752404U, // RCR32m1 13703828U, // RCR32mCL 974199444U, // RCR32mi 14703252U, // RCR32r1 13654676U, // RCR32rCL 705714836U, // RCR32ri 14768788U, // RCR64m1 13720212U, // RCR64mCL 974215828U, // RCR64mi 14703252U, // RCR64r1 13654676U, // RCR64rCL 705714836U, // RCR64ri 14785172U, // RCR8m1 13736596U, // RCR8mCL 974232212U, // RCR8mi 14703252U, // RCR8r1 13654676U, // RCR8rCL 705714836U, // RCR8ri 20909U, // RDFSBASE 20909U, // RDFSBASE64 20929U, // RDGSBASE 20929U, // RDGSBASE64 11740U, // RDMSR 18477U, // RDPID32 18477U, // RDPID64 11983U, // RDPKRUr 11172U, // RDPMC 18619U, // RDRAND16r 18619U, // RDRAND32r 18619U, // RDRAND64r 18425U, // RDSEED16r 18425U, // RDSEED32r 18425U, // RDSEED64r 19544U, // RDSSPD 22571U, // RDSSPQ 11185U, // RDTSC 11569U, // RDTSCP 11302U, // REPNE_PREFIX 11576U, // REP_PREFIX 25114U, // RETIL 25114U, // RETIQ 25114U, // RETIW 11916U, // RETL 11916U, // RETQ 11916U, // RETW 11012U, // REX64_PREFIX 14717906U, // ROL16m1 13669330U, // ROL16mCL 974164946U, // ROL16mi 14701522U, // ROL16r1 13652946U, // ROL16rCL 705713106U, // ROL16ri 14750674U, // ROL32m1 13702098U, // ROL32mCL 974197714U, // ROL32mi 14701522U, // ROL32r1 13652946U, // ROL32rCL 705713106U, // ROL32ri 14767058U, // ROL64m1 13718482U, // ROL64mCL 974214098U, // ROL64mi 14701522U, // ROL64r1 13652946U, // ROL64rCL 705713106U, // ROL64ri 14783442U, // ROL8m1 13734866U, // ROL8mCL 974230482U, // ROL8mi 14701522U, // ROL8r1 13652946U, // ROL8rCL 705713106U, // ROL8ri 14719669U, // ROR16m1 13671093U, // ROR16mCL 974166709U, // ROR16mi 14703285U, // ROR16r1 13654709U, // ROR16rCL 705714869U, // ROR16ri 14752437U, // ROR32m1 13703861U, // ROR32mCL 974199477U, // ROR32mi 14703285U, // ROR32r1 13654709U, // ROR32rCL 705714869U, // ROR32ri 14768821U, // ROR64m1 13720245U, // ROR64mCL 974215861U, // ROR64mi 14703285U, // ROR64r1 13654709U, // ROR64rCL 705714869U, // ROR64ri 14785205U, // ROR8m1 13736629U, // ROR8mCL 974232245U, // ROR8mi 14703285U, // ROR8r1 13654709U, // ROR8rCL 705714869U, // ROR8ri 2551211809U, // RORX32mi 2517657377U, // RORX32ri 2584766241U, // RORX64mi 2517657377U, // RORX64ri 2819640105U, // ROUNDPDm 2517650217U, // ROUNDPDr 2819644904U, // ROUNDPSm 2517655016U, // ROUNDPSr 2752532112U, // ROUNDSDm 2383433360U, // ROUNDSDm_Int 2517651088U, // ROUNDSDr 2182106768U, // ROUNDSDr_Int 2786091260U, // ROUNDSSm 2416992508U, // ROUNDSSm_Int 2517655804U, // ROUNDSSr 2182111484U, // ROUNDSSr_Int 11531U, // RSM 672161629U, // RSQRTPSm 370171741U, // RSQRTPSr 638607775U, // RSQRTSSm 269509023U, // RSQRTSSm_Int 370172319U, // RSQRTSSr 34627999U, // RSQRTSSr_Int 70986U, // RSTORSSP 11362U, // SAHF 14717847U, // SAL16m1 13669271U, // SAL16mCL 1086359U, // SAL16mi 14701463U, // SAL16r1 13652887U, // SAL16rCL 34624407U, // SAL16ri 14750615U, // SAL32m1 13702039U, // SAL32mCL 1119127U, // SAL32mi 14701463U, // SAL32r1 13652887U, // SAL32rCL 34624407U, // SAL32ri 14766999U, // SAL64m1 13718423U, // SAL64mCL 1135511U, // SAL64mi 14701463U, // SAL64r1 13652887U, // SAL64rCL 34624407U, // SAL64ri 14783383U, // SAL8m1 13734807U, // SAL8mCL 1151895U, // SAL8mi 14701463U, // SAL8r1 13652887U, // SAL8rCL 34624407U, // SAL8ri 11159U, // SALC 14719615U, // SAR16m1 13671039U, // SAR16mCL 974166655U, // SAR16mi 14703231U, // SAR16r1 13654655U, // SAR16rCL 705714815U, // SAR16ri 14752383U, // SAR32m1 13703807U, // SAR32mCL 974199423U, // SAR32mi 14703231U, // SAR32r1 13654655U, // SAR32rCL 705714815U, // SAR32ri 14768767U, // SAR64m1 13720191U, // SAR64mCL 974215807U, // SAR64mi 14703231U, // SAR64r1 13654655U, // SAR64rCL 705714815U, // SAR64ri 14785151U, // SAR8m1 13736575U, // SAR8mCL 974232191U, // SAR8mi 14703231U, // SAR8r1 13654655U, // SAR8rCL 705714815U, // SAR8ri 2551211797U, // SARX32rm 2517657365U, // SARX32rr 2584766229U, // SARX64rm 2517657365U, // SARX64rr 11638U, // SAVEPREVSSP 26709U, // SBB16i16 1082315U, // SBB16mi 1082315U, // SBB16mi8 1082315U, // SBB16mr 34653131U, // SBB16ri 34653131U, // SBB16ri8 68207563U, // SBB16rm 34653131U, // SBB16rr 34620363U, // SBB16rr_REV 26833U, // SBB32i32 1115083U, // SBB32mi 1115083U, // SBB32mi8 1115083U, // SBB32mr 34653131U, // SBB32ri 34653131U, // SBB32ri8 101761995U, // SBB32rm 34653131U, // SBB32rr 34620363U, // SBB32rr_REV 26970U, // SBB64i32 1131467U, // SBB64mi32 1131467U, // SBB64mi8 1131467U, // SBB64mr 34653131U, // SBB64ri32 34653131U, // SBB64ri8 135316427U, // SBB64rm 34653131U, // SBB64rr 34620363U, // SBB64rr_REV 26585U, // SBB8i8 1147851U, // SBB8mi 1147851U, // SBB8mi8 1147851U, // SBB8mr 34653131U, // SBB8ri 34653131U, // SBB8ri8 168870859U, // SBB8rm 34653131U, // SBB8rr 34620363U, // SBB8rr_REV 354274U, // SCASB 370947U, // SCASL 551318U, // SCASQ 387259U, // SCASW 102690U, // SETAEm 20770U, // SETAEr 99177U, // SETAm 17257U, // SETAr 102710U, // SETBEm 20790U, // SETBEr 99763U, // SETBm 17843U, // SETBr 102877U, // SETEm 20957U, // SETEr 102755U, // SETGEm 20835U, // SETGEr 102982U, // SETGm 21062U, // SETGr 102779U, // SETLEm 20859U, // SETLEr 103417U, // SETLm 21497U, // SETLr 102807U, // SETNEm 20887U, // SETNEr 103587U, // SETNOm 21667U, // SETNOr 103707U, // SETNPm 21787U, // SETNPr 105347U, // SETNSm 23427U, // SETNSr 103602U, // SETOm 21682U, // SETOr 103764U, // SETPm 21844U, // SETPr 12236U, // SETSSBSY 106981U, // SETSm 25061U, // SETSr 11274U, // SFENCE 303612U, // SGDT16m 303612U, // SGDT32m 303612U, // SGDT64m 303054861U, // SHA1MSG1rm 34619405U, // SHA1MSG1rr 303054957U, // SHA1MSG2rm 34619501U, // SHA1MSG2rr 303059455U, // SHA1NEXTErm 34623999U, // SHA1NEXTErr 2450538898U, // SHA1RNDS4rmi 2182103442U, // SHA1RNDS4rri 303054871U, // SHA256MSG1rm 34619415U, // SHA256MSG1rr 303054967U, // SHA256MSG2rm 34619511U, // SHA256MSG2rr 303054979U, // SHA256RNDS2rm 34619523U, // SHA256RNDS2rr 14717872U, // SHL16m1 13669296U, // SHL16mCL 974164912U, // SHL16mi 14701488U, // SHL16r1 13652912U, // SHL16rCL 705713072U, // SHL16ri 14750640U, // SHL32m1 13702064U, // SHL32mCL 974197680U, // SHL32mi 14701488U, // SHL32r1 13652912U, // SHL32rCL 705713072U, // SHL32ri 14767024U, // SHL64m1 13718448U, // SHL64mCL 974214064U, // SHL64mi 14701488U, // SHL64r1 13652912U, // SHL64rCL 705713072U, // SHL64ri 14783408U, // SHL8m1 13734832U, // SHL8mCL 974230448U, // SHL8mi 14701488U, // SHL8r1 13652912U, // SHL8rCL 705713072U, // SHL8ri 2148567108U, // SHLD16mrCL 2148567108U, // SHLD16mri8 2182105156U, // SHLD16rrCL 2182105156U, // SHLD16rri8 2148599876U, // SHLD32mrCL 2148599876U, // SHLD32mri8 2182105156U, // SHLD32rrCL 2182105156U, // SHLD32rri8 2148616260U, // SHLD64mrCL 2148616260U, // SHLD64mri8 2182105156U, // SHLD64rrCL 2182105156U, // SHLD64rri8 2551211779U, // SHLX32rm 2517657347U, // SHLX32rr 2584766211U, // SHLX64rm 2517657347U, // SHLX64rr 14719648U, // SHR16m1 13671072U, // SHR16mCL 974166688U, // SHR16mi 14703264U, // SHR16r1 13654688U, // SHR16rCL 705714848U, // SHR16ri 14752416U, // SHR32m1 13703840U, // SHR32mCL 974199456U, // SHR32mi 14703264U, // SHR32r1 13654688U, // SHR32rCL 705714848U, // SHR32ri 14768800U, // SHR64m1 13720224U, // SHR64mCL 974215840U, // SHR64mi 14703264U, // SHR64r1 13654688U, // SHR64rCL 705714848U, // SHR64ri 14785184U, // SHR8m1 13736608U, // SHR8mCL 974232224U, // SHR8mi 14703264U, // SHR8r1 13654688U, // SHR8rCL 705714848U, // SHR8ri 2148568335U, // SHRD16mrCL 2148568335U, // SHRD16mri8 2182106383U, // SHRD16rrCL 2182106383U, // SHRD16rri8 2148601103U, // SHRD32mrCL 2148601103U, // SHRD32mri8 2182106383U, // SHRD32rrCL 2182106383U, // SHRD32rri8 2148617487U, // SHRD64mrCL 2148617487U, // SHRD64mri8 2182106383U, // SHRD64rrCL 2182106383U, // SHRD64rri8 2551211803U, // SHRX32rm 2517657371U, // SHRX32rr 2584766235U, // SHRX64rm 2517657371U, // SHRX64rr 2349878137U, // SHUFPDrmi 2182105977U, // SHUFPDrri 2349882936U, // SHUFPSrmi 2182110776U, // SHUFPSrri 303624U, // SIDT16m 303624U, // SIDT32m 303624U, // SIDT64m 11548U, // SIN_F 0U, // SIN_Fp32 0U, // SIN_Fp64 0U, // SIN_Fp80 12093U, // SKINIT 41492U, // SLDT16m 25108U, // SLDT16r 25108U, // SLDT32r 25108U, // SLDT64r 17376U, // SLWPCB 17376U, // SLWPCB64 42436U, // SMSW16m 26052U, // SMSW16r 26052U, // SMSW32r 26052U, // SMSW64r 672156804U, // SQRTPDm 370166916U, // SQRTPDr 672161630U, // SQRTPSm 370171742U, // SQRTPSr 605048684U, // SQRTSDm 235949932U, // SQRTSDm_Int 370167660U, // SQRTSDr 34623340U, // SQRTSDr_Int 638607776U, // SQRTSSm 269509024U, // SQRTSSm_Int 370172320U, // SQRTSSr 34628000U, // SQRTSSr_Int 11960U, // SQRT_F 0U, // SQRT_Fp32 0U, // SQRT_Fp64 0U, // SQRT_Fp80 11137U, // STAC 11191U, // STC 11229U, // STD 11405U, // STGI 11420U, // STI 72434U, // STMXCSR 12928363U, // STOSB 10850047U, // STOSL 12081423U, // STOSQ 9823699U, // STOSW 23307U, // STR16r 23307U, // STR32r 23307U, // STR64r 39691U, // STRm 123553U, // ST_F32m 139937U, // ST_F64m 120154U, // ST_FP32m 136538U, // ST_FP64m 316762U, // ST_FP80m 21850U, // ST_FPrr 0U, // ST_Fp32m 0U, // ST_Fp64m 0U, // ST_Fp64m32 0U, // ST_Fp80m32 0U, // ST_Fp80m64 0U, // ST_FpP32m 0U, // ST_FpP64m 0U, // ST_FpP64m32 0U, // ST_FpP80m 0U, // ST_FpP80m32 0U, // ST_FpP80m64 25249U, // ST_Frr 26718U, // SUB16i16 1082905U, // SUB16mi 1082905U, // SUB16mi8 1082905U, // SUB16mr 34653721U, // SUB16ri 34653721U, // SUB16ri8 68208153U, // SUB16rm 34653721U, // SUB16rr 34620953U, // SUB16rr_REV 26843U, // SUB32i32 1115673U, // SUB32mi 1115673U, // SUB32mi8 1115673U, // SUB32mr 34653721U, // SUB32ri 34653721U, // SUB32ri8 101762585U, // SUB32rm 34653721U, // SUB32rr 34620953U, // SUB32rr_REV 26980U, // SUB64i32 1132057U, // SUB64mi32 1132057U, // SUB64mi8 1132057U, // SUB64mr 34653721U, // SUB64ri32 34653721U, // SUB64ri8 135317017U, // SUB64rm 34653721U, // SUB64rr 34620953U, // SUB64rr_REV 26616U, // SUB8i8 1148441U, // SUB8mi 1148441U, // SUB8mi8 1148441U, // SUB8mr 34653721U, // SUB8ri 34653721U, // SUB8ri8 168871449U, // SUB8rm 34653721U, // SUB8rr 34620953U, // SUB8rr_REV 202394272U, // SUBPDrm 34622112U, // SUBPDrr 202399048U, // SUBPSrm 34626888U, // SUBPSrr 121477U, // SUBR_F32m 137861U, // SUBR_F64m 39564U, // SUBR_FI16m 72332U, // SUBR_FI32m 21818U, // SUBR_FPrST0 23173U, // SUBR_FST0r 0U, // SUBR_Fp32m 0U, // SUBR_Fp64m 0U, // SUBR_Fp64m32 0U, // SUBR_Fp80m32 0U, // SUBR_Fp80m64 0U, // SUBR_FpI16m32 0U, // SUBR_FpI16m64 0U, // SUBR_FpI16m80 0U, // SUBR_FpI32m32 0U, // SUBR_FpI32m64 0U, // SUBR_FpI32m80 2120325U, // SUBR_FrST0 235949656U, // SUBSDrm 235949656U, // SUBSDrm_Int 34623064U, // SUBSDrr 34623064U, // SUBSDrr_Int 269508781U, // SUBSSrm 269508781U, // SUBSSrm_Int 34627757U, // SUBSSrr 34627757U, // SUBSSrr_Int 116248U, // SUB_F32m 132632U, // SUB_F64m 34334U, // SUB_FI16m 67102U, // SUB_FI32m 21702U, // SUB_FPrST0 17944U, // SUB_FST0r 0U, // SUB_Fp32 0U, // SUB_Fp32m 0U, // SUB_Fp64 0U, // SUB_Fp64m 0U, // SUB_Fp64m32 0U, // SUB_Fp80 0U, // SUB_Fp80m32 0U, // SUB_Fp80m64 0U, // SUB_FpI16m32 0U, // SUB_FpI16m64 0U, // SUB_FpI16m80 0U, // SUB_FpI32m32 0U, // SUB_FpI32m64 0U, // SUB_FpI32m80 2115096U, // SUB_FrST0 11843U, // SWAPGS 11482U, // SYSCALL 11723U, // SYSENTER 11940U, // SYSEXIT 11703U, // SYSEXIT64 11920U, // SYSRET 11695U, // SYSRET64 403719869U, // T1MSKC32rm 370165437U, // T1MSKC32rr 437274301U, // T1MSKC64rm 370165437U, // T1MSKC64rr 26792U, // TEST16i16 1090203U, // TEST16mi 1090203U, // TEST16mi_alt 1090203U, // TEST16mr 370172571U, // TEST16ri 370172571U, // TEST16ri_alt 370172571U, // TEST16rr 26949U, // TEST32i32 1122971U, // TEST32mi 1122971U, // TEST32mi_alt 1122971U, // TEST32mr 370172571U, // TEST32ri 370172571U, // TEST32ri_alt 370172571U, // TEST32rr 27077U, // TEST64i32 1139355U, // TEST64mi32 1139355U, // TEST64mi32_alt 1139355U, // TEST64mr 370172571U, // TEST64ri32 370172571U, // TEST64ri32_alt 370172571U, // TEST64rr 26690U, // TEST8i8 1155739U, // TEST8mi 1155739U, // TEST8mi_alt 1155739U, // TEST8mr 370172571U, // TEST8ri 370172571U, // TEST8ri_alt 370172571U, // TEST8rr 20949U, // TPAUSE 11972U, // TST_F 0U, // TST_Fp32 0U, // TST_Fp64 0U, // TST_Fp80 504390207U, // TZCNT16rm 370172479U, // TZCNT16rr 403726911U, // TZCNT32rm 370172479U, // TZCNT32rr 437281343U, // TZCNT64rm 370172479U, // TZCNT64rr 403723152U, // TZMSK32rm 370168720U, // TZMSK32rr 437277584U, // TZMSK64rm 370168720U, // TZMSK64rr 605048519U, // UCOMISDrm 605048519U, // UCOMISDrm_Int 370167495U, // UCOMISDrr 370167495U, // UCOMISDrr_Int 638607667U, // UCOMISSrm 638607667U, // UCOMISSrm_Int 370172211U, // UCOMISSrr 370172211U, // UCOMISSrr_Int 21217U, // UCOM_FIPr 21159U, // UCOM_FIr 11630U, // UCOM_FPPr 21774U, // UCOM_FPr 0U, // UCOM_FpIr32 0U, // UCOM_FpIr64 0U, // UCOM_FpIr80 0U, // UCOM_Fpr32 0U, // UCOM_Fpr64 0U, // UCOM_Fpr80 21582U, // UCOM_Fr 10928U, // UD0 10943U, // UD1 10981U, // UD2 23226U, // UMONITOR16 23226U, // UMONITOR32 23226U, // UMONITOR64 25128U, // UMWAIT 202394498U, // UNPCKHPDrm 34622338U, // UNPCKHPDrr 202399297U, // UNPCKHPSrm 34627137U, // UNPCKHPSrr 202394540U, // UNPCKLPDrm 34622380U, // UNPCKLPDrr 202399359U, // UNPCKLPSrm 34627199U, // UNPCKLPSrr 2182110614U, // V4FMADDPSrm 49307030U, // V4FMADDPSrmk 2196790678U, // V4FMADDPSrmkz 2182111431U, // V4FMADDSSrm 49307847U, // V4FMADDSSrmk 2196791495U, // V4FMADDSSrmkz 2182110635U, // V4FNMADDPSrm 49307051U, // V4FNMADDPSrmk 2196790699U, // V4FNMADDPSrmkz 2182111452U, // V4FNMADDSSrm 49307868U, // V4FNMADDSSrmk 2196791516U, // V4FNMADDSSrmkz 2517650179U, // VADDPDYrm 2517650179U, // VADDPDYrr 2517650179U, // VADDPDZ128rm 2517650179U, // VADDPDZ128rmb 49302275U, // VADDPDZ128rmbk 2532330243U, // VADDPDZ128rmbkz 49302275U, // VADDPDZ128rmk 2532330243U, // VADDPDZ128rmkz 2517650179U, // VADDPDZ128rr 49302275U, // VADDPDZ128rrk 2532330243U, // VADDPDZ128rrkz 2517650179U, // VADDPDZ256rm 2517650179U, // VADDPDZ256rmb 49302275U, // VADDPDZ256rmbk 2532330243U, // VADDPDZ256rmbkz 49302275U, // VADDPDZ256rmk 2532330243U, // VADDPDZ256rmkz 2517650179U, // VADDPDZ256rr 49302275U, // VADDPDZ256rrk 2532330243U, // VADDPDZ256rrkz 2517650179U, // VADDPDZrm 2517650179U, // VADDPDZrmb 49302275U, // VADDPDZrmbk 2532330243U, // VADDPDZrmbkz 49302275U, // VADDPDZrmk 2532330243U, // VADDPDZrmkz 2517650179U, // VADDPDZrr 2517650179U, // VADDPDZrrb 49302275U, // VADDPDZrrbk 2532330243U, // VADDPDZrrbkz 49302275U, // VADDPDZrrk 2532330243U, // VADDPDZrrkz 2517650179U, // VADDPDrm 2517650179U, // VADDPDrr 2517654978U, // VADDPSYrm 2517654978U, // VADDPSYrr 2517654978U, // VADDPSZ128rm 2517654978U, // VADDPSZ128rmb 49307074U, // VADDPSZ128rmbk 2532335042U, // VADDPSZ128rmbkz 49307074U, // VADDPSZ128rmk 2532335042U, // VADDPSZ128rmkz 2517654978U, // VADDPSZ128rr 49307074U, // VADDPSZ128rrk 2532335042U, // VADDPSZ128rrkz 2517654978U, // VADDPSZ256rm 2517654978U, // VADDPSZ256rmb 49307074U, // VADDPSZ256rmbk 2532335042U, // VADDPSZ256rmbkz 49307074U, // VADDPSZ256rmk 2532335042U, // VADDPSZ256rmkz 2517654978U, // VADDPSZ256rr 49307074U, // VADDPSZ256rrk 2532335042U, // VADDPSZ256rrkz 2517654978U, // VADDPSZrm 2517654978U, // VADDPSZrmb 49307074U, // VADDPSZrmbk 2532335042U, // VADDPSZrmbkz 49307074U, // VADDPSZrmk 2532335042U, // VADDPSZrmkz 2517654978U, // VADDPSZrr 2517654978U, // VADDPSZrrb 49307074U, // VADDPSZrrbk 2532335042U, // VADDPSZrrbkz 49307074U, // VADDPSZrrk 2532335042U, // VADDPSZrrkz 2517654978U, // VADDPSrm 2517654978U, // VADDPSrr 2517651079U, // VADDSDZrm 2517651079U, // VADDSDZrm_Int 49303175U, // VADDSDZrm_Intk 2532331143U, // VADDSDZrm_Intkz 2517651079U, // VADDSDZrr 2517651079U, // VADDSDZrr_Int 49303175U, // VADDSDZrr_Intk 2532331143U, // VADDSDZrr_Intkz 2517651079U, // VADDSDZrrb_Int 49303175U, // VADDSDZrrb_Intk 2532331143U, // VADDSDZrrb_Intkz 2517651079U, // VADDSDrm 2517651079U, // VADDSDrm_Int 2517651079U, // VADDSDrr 2517651079U, // VADDSDrr_Int 2517655795U, // VADDSSZrm 2517655795U, // VADDSSZrm_Int 49307891U, // VADDSSZrm_Intk 2532335859U, // VADDSSZrm_Intkz 2517655795U, // VADDSSZrr 2517655795U, // VADDSSZrr_Int 49307891U, // VADDSSZrr_Intk 2532335859U, // VADDSSZrr_Intkz 2517655795U, // VADDSSZrrb_Int 49307891U, // VADDSSZrrb_Intk 2532335859U, // VADDSSZrrb_Intkz 2517655795U, // VADDSSrm 2517655795U, // VADDSSrm_Int 2517655795U, // VADDSSrr 2517655795U, // VADDSSrr_Int 2517650087U, // VADDSUBPDYrm 2517650087U, // VADDSUBPDYrr 2517650087U, // VADDSUBPDrm 2517650087U, // VADDSUBPDrr 2517654863U, // VADDSUBPSYrm 2517654863U, // VADDSUBPSYrr 2517654863U, // VADDSUBPSrm 2517654863U, // VADDSUBPSrr 2517656191U, // VAESDECLASTYrm 2517656191U, // VAESDECLASTYrr 2517656191U, // VAESDECLASTZ128rm 2517656191U, // VAESDECLASTZ128rr 2517656191U, // VAESDECLASTZ256rm 2517656191U, // VAESDECLASTZ256rr 2517656191U, // VAESDECLASTZrm 2517656191U, // VAESDECLASTZrr 2517656191U, // VAESDECLASTrm 2517656191U, // VAESDECLASTrr 2517649054U, // VAESDECYrm 2517649054U, // VAESDECYrr 2517649054U, // VAESDECZ128rm 2517649054U, // VAESDECZ128rr 2517649054U, // VAESDECZ256rm 2517649054U, // VAESDECZ256rr 2517649054U, // VAESDECZrm 2517649054U, // VAESDECZrr 2517649054U, // VAESDECrm 2517649054U, // VAESDECrr 2517656204U, // VAESENCLASTYrm 2517656204U, // VAESENCLASTYrr 2517656204U, // VAESENCLASTZ128rm 2517656204U, // VAESENCLASTZ128rr 2517656204U, // VAESENCLASTZ256rm 2517656204U, // VAESENCLASTZ256rr 2517656204U, // VAESENCLASTZrm 2517656204U, // VAESENCLASTZrr 2517656204U, // VAESENCLASTrm 2517656204U, // VAESENCLASTrr 2517649102U, // VAESENCYrm 2517649102U, // VAESENCYrr 2517649102U, // VAESENCZ128rm 2517649102U, // VAESENCZ128rr 2517649102U, // VAESENCZ256rm 2517649102U, // VAESENCZ256rr 2517649102U, // VAESENCZrm 2517649102U, // VAESENCZrr 2517649102U, // VAESENCrm 2517649102U, // VAESENCrr 336611013U, // VAESIMCrm 370165445U, // VAESIMCrr 2484101804U, // VAESKEYGENASSIST128rm 2517656236U, // VAESKEYGENASSIST128rr 2517649620U, // VALIGNDZ128rmbi 49301716U, // VALIGNDZ128rmbik 2532329684U, // VALIGNDZ128rmbikz 2517649620U, // VALIGNDZ128rmi 49301716U, // VALIGNDZ128rmik 2532329684U, // VALIGNDZ128rmikz 2517649620U, // VALIGNDZ128rri 49301716U, // VALIGNDZ128rrik 2532329684U, // VALIGNDZ128rrikz 2517649620U, // VALIGNDZ256rmbi 49301716U, // VALIGNDZ256rmbik 2532329684U, // VALIGNDZ256rmbikz 2517649620U, // VALIGNDZ256rmi 49301716U, // VALIGNDZ256rmik 2532329684U, // VALIGNDZ256rmikz 2517649620U, // VALIGNDZ256rri 49301716U, // VALIGNDZ256rrik 2532329684U, // VALIGNDZ256rrikz 2517649620U, // VALIGNDZrmbi 49301716U, // VALIGNDZrmbik 2532329684U, // VALIGNDZrmbikz 2517649620U, // VALIGNDZrmi 49301716U, // VALIGNDZrmik 2532329684U, // VALIGNDZrmikz 2517649620U, // VALIGNDZrri 49301716U, // VALIGNDZrrik 2532329684U, // VALIGNDZrrikz 2517653521U, // VALIGNQZ128rmbi 49305617U, // VALIGNQZ128rmbik 2532333585U, // VALIGNQZ128rmbikz 2517653521U, // VALIGNQZ128rmi 49305617U, // VALIGNQZ128rmik 2532333585U, // VALIGNQZ128rmikz 2517653521U, // VALIGNQZ128rri 49305617U, // VALIGNQZ128rrik 2532333585U, // VALIGNQZ128rrikz 2517653521U, // VALIGNQZ256rmbi 49305617U, // VALIGNQZ256rmbik 2532333585U, // VALIGNQZ256rmbikz 2517653521U, // VALIGNQZ256rmi 49305617U, // VALIGNQZ256rmik 2532333585U, // VALIGNQZ256rmikz 2517653521U, // VALIGNQZ256rri 49305617U, // VALIGNQZ256rrik 2532333585U, // VALIGNQZ256rrikz 2517653521U, // VALIGNQZrmbi 49305617U, // VALIGNQZrmbik 2532333585U, // VALIGNQZrmbikz 2517653521U, // VALIGNQZrmi 49305617U, // VALIGNQZrmik 2532333585U, // VALIGNQZrmikz 2517653521U, // VALIGNQZrri 49305617U, // VALIGNQZrrik 2532333585U, // VALIGNQZrrikz 2517650416U, // VANDNPDYrm 2517650416U, // VANDNPDYrr 2517650416U, // VANDNPDZ128rm 2517650416U, // VANDNPDZ128rmb 49302512U, // VANDNPDZ128rmbk 2532330480U, // VANDNPDZ128rmbkz 49302512U, // VANDNPDZ128rmk 2532330480U, // VANDNPDZ128rmkz 2517650416U, // VANDNPDZ128rr 49302512U, // VANDNPDZ128rrk 2532330480U, // VANDNPDZ128rrkz 2517650416U, // VANDNPDZ256rm 2517650416U, // VANDNPDZ256rmb 49302512U, // VANDNPDZ256rmbk 2532330480U, // VANDNPDZ256rmbkz 49302512U, // VANDNPDZ256rmk 2532330480U, // VANDNPDZ256rmkz 2517650416U, // VANDNPDZ256rr 49302512U, // VANDNPDZ256rrk 2532330480U, // VANDNPDZ256rrkz 2517650416U, // VANDNPDZrm 2517650416U, // VANDNPDZrmb 49302512U, // VANDNPDZrmbk 2532330480U, // VANDNPDZrmbkz 49302512U, // VANDNPDZrmk 2532330480U, // VANDNPDZrmkz 2517650416U, // VANDNPDZrr 49302512U, // VANDNPDZrrk 2532330480U, // VANDNPDZrrkz 2517650416U, // VANDNPDrm 2517650416U, // VANDNPDrr 2517655227U, // VANDNPSYrm 2517655227U, // VANDNPSYrr 2517655227U, // VANDNPSZ128rm 2517655227U, // VANDNPSZ128rmb 49307323U, // VANDNPSZ128rmbk 2532335291U, // VANDNPSZ128rmbkz 49307323U, // VANDNPSZ128rmk 2532335291U, // VANDNPSZ128rmkz 2517655227U, // VANDNPSZ128rr 49307323U, // VANDNPSZ128rrk 2532335291U, // VANDNPSZ128rrkz 2517655227U, // VANDNPSZ256rm 2517655227U, // VANDNPSZ256rmb 49307323U, // VANDNPSZ256rmbk 2532335291U, // VANDNPSZ256rmbkz 49307323U, // VANDNPSZ256rmk 2532335291U, // VANDNPSZ256rmkz 2517655227U, // VANDNPSZ256rr 49307323U, // VANDNPSZ256rrk 2532335291U, // VANDNPSZ256rrkz 2517655227U, // VANDNPSZrm 2517655227U, // VANDNPSZrmb 49307323U, // VANDNPSZrmbk 2532335291U, // VANDNPSZrmbkz 49307323U, // VANDNPSZrmk 2532335291U, // VANDNPSZrmkz 2517655227U, // VANDNPSZrr 49307323U, // VANDNPSZrrk 2532335291U, // VANDNPSZrrkz 2517655227U, // VANDNPSrm 2517655227U, // VANDNPSrr 2517650198U, // VANDPDYrm 2517650198U, // VANDPDYrr 2517650198U, // VANDPDZ128rm 2517650198U, // VANDPDZ128rmb 49302294U, // VANDPDZ128rmbk 2532330262U, // VANDPDZ128rmbkz 49302294U, // VANDPDZ128rmk 2532330262U, // VANDPDZ128rmkz 2517650198U, // VANDPDZ128rr 49302294U, // VANDPDZ128rrk 2532330262U, // VANDPDZ128rrkz 2517650198U, // VANDPDZ256rm 2517650198U, // VANDPDZ256rmb 49302294U, // VANDPDZ256rmbk 2532330262U, // VANDPDZ256rmbkz 49302294U, // VANDPDZ256rmk 2532330262U, // VANDPDZ256rmkz 2517650198U, // VANDPDZ256rr 49302294U, // VANDPDZ256rrk 2532330262U, // VANDPDZ256rrkz 2517650198U, // VANDPDZrm 2517650198U, // VANDPDZrmb 49302294U, // VANDPDZrmbk 2532330262U, // VANDPDZrmbkz 49302294U, // VANDPDZrmk 2532330262U, // VANDPDZrmkz 2517650198U, // VANDPDZrr 49302294U, // VANDPDZrrk 2532330262U, // VANDPDZrrkz 2517650198U, // VANDPDrm 2517650198U, // VANDPDrr 2517654997U, // VANDPSYrm 2517654997U, // VANDPSYrr 2517654997U, // VANDPSZ128rm 2517654997U, // VANDPSZ128rmb 49307093U, // VANDPSZ128rmbk 2532335061U, // VANDPSZ128rmbkz 49307093U, // VANDPSZ128rmk 2532335061U, // VANDPSZ128rmkz 2517654997U, // VANDPSZ128rr 49307093U, // VANDPSZ128rrk 2532335061U, // VANDPSZ128rrkz 2517654997U, // VANDPSZ256rm 2517654997U, // VANDPSZ256rmb 49307093U, // VANDPSZ256rmbk 2532335061U, // VANDPSZ256rmbkz 49307093U, // VANDPSZ256rmk 2532335061U, // VANDPSZ256rmkz 2517654997U, // VANDPSZ256rr 49307093U, // VANDPSZ256rrk 2532335061U, // VANDPSZ256rrkz 2517654997U, // VANDPSZrm 2517654997U, // VANDPSZrmb 49307093U, // VANDPSZrmbk 2532335061U, // VANDPSZrmbkz 49307093U, // VANDPSZrmk 2532335061U, // VANDPSZrmkz 2517654997U, // VANDPSZrr 49307093U, // VANDPSZrrk 2532335061U, // VANDPSZrrkz 2517654997U, // VANDPSrm 2517654997U, // VANDPSrr 2517650383U, // VBLENDMPDZ128rm 2517650383U, // VBLENDMPDZ128rmb 384846799U, // VBLENDMPDZ128rmbk 2532330447U, // VBLENDMPDZ128rmbkz 384846799U, // VBLENDMPDZ128rmk 2532330447U, // VBLENDMPDZ128rmkz 2517650383U, // VBLENDMPDZ128rr 384846799U, // VBLENDMPDZ128rrk 2532330447U, // VBLENDMPDZ128rrkz 2517650383U, // VBLENDMPDZ256rm 2517650383U, // VBLENDMPDZ256rmb 384846799U, // VBLENDMPDZ256rmbk 2532330447U, // VBLENDMPDZ256rmbkz 384846799U, // VBLENDMPDZ256rmk 2532330447U, // VBLENDMPDZ256rmkz 2517650383U, // VBLENDMPDZ256rr 384846799U, // VBLENDMPDZ256rrk 2532330447U, // VBLENDMPDZ256rrkz 2517650383U, // VBLENDMPDZrm 2517650383U, // VBLENDMPDZrmb 384846799U, // VBLENDMPDZrmbk 2532330447U, // VBLENDMPDZrmbkz 384846799U, // VBLENDMPDZrmk 2532330447U, // VBLENDMPDZrmkz 2517650383U, // VBLENDMPDZrr 384846799U, // VBLENDMPDZrrk 2532330447U, // VBLENDMPDZrrkz 2517655194U, // VBLENDMPSZ128rm 2517655194U, // VBLENDMPSZ128rmb 384851610U, // VBLENDMPSZ128rmbk 2532335258U, // VBLENDMPSZ128rmbkz 384851610U, // VBLENDMPSZ128rmk 2532335258U, // VBLENDMPSZ128rmkz 2517655194U, // VBLENDMPSZ128rr 384851610U, // VBLENDMPSZ128rrk 2532335258U, // VBLENDMPSZ128rrkz 2517655194U, // VBLENDMPSZ256rm 2517655194U, // VBLENDMPSZ256rmb 384851610U, // VBLENDMPSZ256rmbk 2532335258U, // VBLENDMPSZ256rmbkz 384851610U, // VBLENDMPSZ256rmk 2532335258U, // VBLENDMPSZ256rmkz 2517655194U, // VBLENDMPSZ256rr 384851610U, // VBLENDMPSZ256rrk 2532335258U, // VBLENDMPSZ256rrkz 2517655194U, // VBLENDMPSZrm 2517655194U, // VBLENDMPSZrmb 384851610U, // VBLENDMPSZrmbk 2532335258U, // VBLENDMPSZrmbkz 384851610U, // VBLENDMPSZrmk 2532335258U, // VBLENDMPSZrmkz 2517655194U, // VBLENDMPSZrr 384851610U, // VBLENDMPSZrrk 2532335258U, // VBLENDMPSZrrkz 2517650206U, // VBLENDPDYrmi 2517650206U, // VBLENDPDYrri 2517650206U, // VBLENDPDrmi 2517650206U, // VBLENDPDrri 2517655005U, // VBLENDPSYrmi 2517655005U, // VBLENDPSYrri 2517655005U, // VBLENDPSrmi 2517655005U, // VBLENDPSrri 2517650590U, // VBLENDVPDYrm 2517650590U, // VBLENDVPDYrr 2517650590U, // VBLENDVPDrm 2517650590U, // VBLENDVPDrr 2517655425U, // VBLENDVPSYrm 2517655425U, // VBLENDVPSYrr 2517655425U, // VBLENDVPSrm 2517655425U, // VBLENDVPSrr 672154271U, // VBROADCASTF128 605044902U, // VBROADCASTF32X2Z256m 49299622U, // VBROADCASTF32X2Z256mk 2532327590U, // VBROADCASTF32X2Z256mkz 370163878U, // VBROADCASTF32X2Z256r 49299622U, // VBROADCASTF32X2Z256rk 2532327590U, // VBROADCASTF32X2Z256rkz 605044902U, // VBROADCASTF32X2Zm 49299622U, // VBROADCASTF32X2Zmk 2532327590U, // VBROADCASTF32X2Zmkz 370163878U, // VBROADCASTF32X2Zr 49299622U, // VBROADCASTF32X2Zrk 2532327590U, // VBROADCASTF32X2Zrkz 672154054U, // VBROADCASTF32X4Z256rm 49299910U, // VBROADCASTF32X4Z256rmk 2532327878U, // VBROADCASTF32X4Z256rmkz 672154054U, // VBROADCASTF32X4rm 49299910U, // VBROADCASTF32X4rmk 2532327878U, // VBROADCASTF32X4rmkz 1007698701U, // VBROADCASTF32X8rm 49300237U, // VBROADCASTF32X8rmk 2532328205U, // VBROADCASTF32X8rmkz 672153841U, // VBROADCASTF64X2Z128rm 49299697U, // VBROADCASTF64X2Z128rmk 2532327665U, // VBROADCASTF64X2Z128rmkz 672153841U, // VBROADCASTF64X2rm 49299697U, // VBROADCASTF64X2rmk 2532327665U, // VBROADCASTF64X2rmkz 1007698478U, // VBROADCASTF64X4rm 49300014U, // VBROADCASTF64X4rmk 2532327982U, // VBROADCASTF64X4rmkz 336610006U, // VBROADCASTI128 437272759U, // VBROADCASTI32X2Z128m 49299639U, // VBROADCASTI32X2Z128mk 2532327607U, // VBROADCASTI32X2Z128mkz 370163895U, // VBROADCASTI32X2Z128r 49299639U, // VBROADCASTI32X2Z128rk 2532327607U, // VBROADCASTI32X2Z128rkz 437272759U, // VBROADCASTI32X2Z256m 49299639U, // VBROADCASTI32X2Z256mk 2532327607U, // VBROADCASTI32X2Z256mkz 370163895U, // VBROADCASTI32X2Z256r 49299639U, // VBROADCASTI32X2Z256rk 2532327607U, // VBROADCASTI32X2Z256rkz 437272759U, // VBROADCASTI32X2Zm 49299639U, // VBROADCASTI32X2Zmk 2532327607U, // VBROADCASTI32X2Zmkz 370163895U, // VBROADCASTI32X2Zr 49299639U, // VBROADCASTI32X2Zrk 2532327607U, // VBROADCASTI32X2Zrkz 336609792U, // VBROADCASTI32X4Z256rm 49299968U, // VBROADCASTI32X4Z256rmk 2532327936U, // VBROADCASTI32X4Z256rmkz 336609792U, // VBROADCASTI32X4rm 49299968U, // VBROADCASTI32X4rmk 2532327936U, // VBROADCASTI32X4rmkz 1041253179U, // VBROADCASTI32X8rm 49300283U, // VBROADCASTI32X8rmk 2532328251U, // VBROADCASTI32X8rmkz 336609579U, // VBROADCASTI64X2Z128rm 49299755U, // VBROADCASTI64X2Z128rmk 2532327723U, // VBROADCASTI64X2Z128rmkz 336609579U, // VBROADCASTI64X2rm 49299755U, // VBROADCASTI64X2rmk 2532327723U, // VBROADCASTI64X2rmkz 1041252956U, // VBROADCASTI64X4rm 49300060U, // VBROADCASTI64X4rmk 2532328028U, // VBROADCASTI64X4rmkz 605048692U, // VBROADCASTSDYrm 370167668U, // VBROADCASTSDYrr 605048692U, // VBROADCASTSDZ256m 49303412U, // VBROADCASTSDZ256mk 2532331380U, // VBROADCASTSDZ256mkz 370167668U, // VBROADCASTSDZ256r 49303412U, // VBROADCASTSDZ256rk 2532331380U, // VBROADCASTSDZ256rkz 605048692U, // VBROADCASTSDZm 49303412U, // VBROADCASTSDZmk 2532331380U, // VBROADCASTSDZmkz 370167668U, // VBROADCASTSDZr 49303412U, // VBROADCASTSDZrk 2532331380U, // VBROADCASTSDZrkz 638607793U, // VBROADCASTSSYrm 370172337U, // VBROADCASTSSYrr 638607793U, // VBROADCASTSSZ128m 49308081U, // VBROADCASTSSZ128mk 2532336049U, // VBROADCASTSSZ128mkz 370172337U, // VBROADCASTSSZ128r 49308081U, // VBROADCASTSSZ128rk 2532336049U, // VBROADCASTSSZ128rkz 638607793U, // VBROADCASTSSZ256m 49308081U, // VBROADCASTSSZ256mk 2532336049U, // VBROADCASTSSZ256mkz 370172337U, // VBROADCASTSSZ256r 49308081U, // VBROADCASTSSZ256rk 2532336049U, // VBROADCASTSSZ256rkz 638607793U, // VBROADCASTSSZm 49308081U, // VBROADCASTSSZmk 2532336049U, // VBROADCASTSSZmkz 370172337U, // VBROADCASTSSZr 49308081U, // VBROADCASTSSZrk 2532336049U, // VBROADCASTSSZrkz 638607793U, // VBROADCASTSSrm 370172337U, // VBROADCASTSSrr 573779266U, // VCMPPDYrmi 2517650440U, // VCMPPDYrmi_alt 573795650U, // VCMPPDYrri 2517650440U, // VCMPPDYrri_alt 573779266U, // VCMPPDZ128rmbi 2517650440U, // VCMPPDZ128rmbi_alt 384846856U, // VCMPPDZ128rmbi_altk 3224939842U, // VCMPPDZ128rmbik 573779266U, // VCMPPDZ128rmi 2517650440U, // VCMPPDZ128rmi_alt 384846856U, // VCMPPDZ128rmi_altk 1077456194U, // VCMPPDZ128rmik 573795650U, // VCMPPDZ128rri 2517650440U, // VCMPPDZ128rri_alt 384846856U, // VCMPPDZ128rri_altk 3224956226U, // VCMPPDZ128rrik 573779266U, // VCMPPDZ256rmbi 2517650440U, // VCMPPDZ256rmbi_alt 384846856U, // VCMPPDZ256rmbi_altk 3224939842U, // VCMPPDZ256rmbik 573779266U, // VCMPPDZ256rmi 2517650440U, // VCMPPDZ256rmi_alt 384846856U, // VCMPPDZ256rmi_altk 1077456194U, // VCMPPDZ256rmik 573795650U, // VCMPPDZ256rri 2517650440U, // VCMPPDZ256rri_alt 384846856U, // VCMPPDZ256rri_altk 3224956226U, // VCMPPDZ256rrik 573779266U, // VCMPPDZrmbi 2517650440U, // VCMPPDZrmbi_alt 384846856U, // VCMPPDZrmbi_altk 3224939842U, // VCMPPDZrmbik 573779266U, // VCMPPDZrmi 2517650440U, // VCMPPDZrmi_alt 384846856U, // VCMPPDZrmi_altk 3224939842U, // VCMPPDZrmik 573795650U, // VCMPPDZrri 2517650440U, // VCMPPDZrri_alt 384846856U, // VCMPPDZrri_altk 573795650U, // VCMPPDZrrib 2517650440U, // VCMPPDZrrib_alt 384846856U, // VCMPPDZrrib_altk 3224956226U, // VCMPPDZrribk 3224956226U, // VCMPPDZrrik 573779266U, // VCMPPDrmi 2517650440U, // VCMPPDrmi_alt 573795650U, // VCMPPDrri 2517650440U, // VCMPPDrri_alt 574827842U, // VCMPPSYrmi 2517655259U, // VCMPPSYrmi_alt 574844226U, // VCMPPSYrri 2517655259U, // VCMPPSYrri_alt 574827842U, // VCMPPSZ128rmbi 2517655259U, // VCMPPSZ128rmbi_alt 384851675U, // VCMPPSZ128rmbi_altk 1078504770U, // VCMPPSZ128rmbik 574827842U, // VCMPPSZ128rmi 2517655259U, // VCMPPSZ128rmi_alt 384851675U, // VCMPPSZ128rmi_altk 1078504770U, // VCMPPSZ128rmik 574844226U, // VCMPPSZ128rri 2517655259U, // VCMPPSZ128rri_alt 384851675U, // VCMPPSZ128rri_altk 3226004802U, // VCMPPSZ128rrik 574827842U, // VCMPPSZ256rmbi 2517655259U, // VCMPPSZ256rmbi_alt 384851675U, // VCMPPSZ256rmbi_altk 1078504770U, // VCMPPSZ256rmbik 574827842U, // VCMPPSZ256rmi 2517655259U, // VCMPPSZ256rmi_alt 384851675U, // VCMPPSZ256rmi_altk 1078504770U, // VCMPPSZ256rmik 574844226U, // VCMPPSZ256rri 2517655259U, // VCMPPSZ256rri_alt 384851675U, // VCMPPSZ256rri_altk 3226004802U, // VCMPPSZ256rrik 574827842U, // VCMPPSZrmbi 2517655259U, // VCMPPSZrmbi_alt 384851675U, // VCMPPSZrmbi_altk 1078504770U, // VCMPPSZrmbik 574827842U, // VCMPPSZrmi 2517655259U, // VCMPPSZrmi_alt 384851675U, // VCMPPSZrmi_altk 3225988418U, // VCMPPSZrmik 574844226U, // VCMPPSZrri 2517655259U, // VCMPPSZrri_alt 384851675U, // VCMPPSZrri_altk 574844226U, // VCMPPSZrrib 2517655259U, // VCMPPSZrrib_alt 384851675U, // VCMPPSZrrib_altk 3226004802U, // VCMPPSZrribk 3226004802U, // VCMPPSZrrik 574827842U, // VCMPPSrmi 2517655259U, // VCMPPSrmi_alt 574844226U, // VCMPPSrri 2517655259U, // VCMPPSrri_alt 575876418U, // VCMPSDZrm 575876418U, // VCMPSDZrm_Int 3227036994U, // VCMPSDZrm_Intk 2517651206U, // VCMPSDZrmi_alt 384847622U, // VCMPSDZrmi_altk 575892802U, // VCMPSDZrr 575892802U, // VCMPSDZrr_Int 3227053378U, // VCMPSDZrr_Intk 575892802U, // VCMPSDZrrb_Int 3227053378U, // VCMPSDZrrb_Intk 2517651206U, // VCMPSDZrrb_alt 384847622U, // VCMPSDZrrb_altk 2517651206U, // VCMPSDZrri_alt 384847622U, // VCMPSDZrri_altk 575876418U, // VCMPSDrm 575876418U, // VCMPSDrm_Int 2517651206U, // VCMPSDrm_alt 575892802U, // VCMPSDrr 575892802U, // VCMPSDrr_Int 2517651206U, // VCMPSDrr_alt 576924994U, // VCMPSSZrm 576924994U, // VCMPSSZrm_Int 1080601922U, // VCMPSSZrm_Intk 2517655914U, // VCMPSSZrmi_alt 384852330U, // VCMPSSZrmi_altk 576941378U, // VCMPSSZrr 576941378U, // VCMPSSZrr_Int 3228101954U, // VCMPSSZrr_Intk 576941378U, // VCMPSSZrrb_Int 3228101954U, // VCMPSSZrrb_Intk 2517655914U, // VCMPSSZrrb_alt 384852330U, // VCMPSSZrrb_altk 2517655914U, // VCMPSSZrri_alt 384852330U, // VCMPSSZrri_altk 576924994U, // VCMPSSrm 576924994U, // VCMPSSrm_Int 2517655914U, // VCMPSSrm_alt 576941378U, // VCMPSSrr 576941378U, // VCMPSSrr_Int 2517655914U, // VCMPSSrr_alt 605048528U, // VCOMISDZrm 605048528U, // VCOMISDZrm_Int 370167504U, // VCOMISDZrr 370167504U, // VCOMISDZrr_Int 2517651152U, // VCOMISDZrrb 605048528U, // VCOMISDrm 605048528U, // VCOMISDrm_Int 370167504U, // VCOMISDrr 370167504U, // VCOMISDrr_Int 638607676U, // VCOMISSZrm 638607676U, // VCOMISSZrm_Int 370172220U, // VCOMISSZrr 370172220U, // VCOMISSZrr_Int 2517655868U, // VCOMISSZrrb 638607676U, // VCOMISSrm 638607676U, // VCOMISSrm_Int 370172220U, // VCOMISSrr 370172220U, // VCOMISSrr_Int 1576032U, // VCOMPRESSPDZ128mr 16256096U, // VCOMPRESSPDZ128mrk 370166880U, // VCOMPRESSPDZ128rr 49302624U, // VCOMPRESSPDZ128rrk 2532330592U, // VCOMPRESSPDZ128rrkz 1641568U, // VCOMPRESSPDZ256mr 16321632U, // VCOMPRESSPDZ256mrk 370166880U, // VCOMPRESSPDZ256rr 49302624U, // VCOMPRESSPDZ256rrk 2532330592U, // VCOMPRESSPDZ256rrkz 1657952U, // VCOMPRESSPDZmr 16338016U, // VCOMPRESSPDZmrk 370166880U, // VCOMPRESSPDZrr 49302624U, // VCOMPRESSPDZrrk 2532330592U, // VCOMPRESSPDZrrkz 1580834U, // VCOMPRESSPSZ128mr 16260898U, // VCOMPRESSPSZ128mrk 370171682U, // VCOMPRESSPSZ128rr 49307426U, // VCOMPRESSPSZ128rrk 2532335394U, // VCOMPRESSPSZ128rrkz 1646370U, // VCOMPRESSPSZ256mr 16326434U, // VCOMPRESSPSZ256mrk 370171682U, // VCOMPRESSPSZ256rr 49307426U, // VCOMPRESSPSZ256rrk 2532335394U, // VCOMPRESSPSZ256rrkz 1662754U, // VCOMPRESSPSZmr 16342818U, // VCOMPRESSPSZmrk 370171682U, // VCOMPRESSPSZrr 49307426U, // VCOMPRESSPSZrrk 2532335394U, // VCOMPRESSPSZrrkz 336611779U, // VCVTDQ2PDYrm 370166211U, // VCVTDQ2PDYrr 437275075U, // VCVTDQ2PDZ128rm 403720643U, // VCVTDQ2PDZ128rmb 49301955U, // VCVTDQ2PDZ128rmbk 2532329923U, // VCVTDQ2PDZ128rmbkz 49301955U, // VCVTDQ2PDZ128rmk 2532329923U, // VCVTDQ2PDZ128rmkz 370166211U, // VCVTDQ2PDZ128rr 49301955U, // VCVTDQ2PDZ128rrk 2532329923U, // VCVTDQ2PDZ128rrkz 336611779U, // VCVTDQ2PDZ256rm 2551204291U, // VCVTDQ2PDZ256rmb 49301955U, // VCVTDQ2PDZ256rmbk 2532329923U, // VCVTDQ2PDZ256rmbkz 49301955U, // VCVTDQ2PDZ256rmk 2532329923U, // VCVTDQ2PDZ256rmkz 370166211U, // VCVTDQ2PDZ256rr 49301955U, // VCVTDQ2PDZ256rrk 2532329923U, // VCVTDQ2PDZ256rrkz 1041254851U, // VCVTDQ2PDZrm 403720643U, // VCVTDQ2PDZrmb 49301955U, // VCVTDQ2PDZrmbk 2532329923U, // VCVTDQ2PDZrmbkz 49301955U, // VCVTDQ2PDZrmk 2532329923U, // VCVTDQ2PDZrmkz 370166211U, // VCVTDQ2PDZrr 49301955U, // VCVTDQ2PDZrrk 2532329923U, // VCVTDQ2PDZrrkz 437275075U, // VCVTDQ2PDrm 370166211U, // VCVTDQ2PDrr 1041259646U, // VCVTDQ2PSYrm 370171006U, // VCVTDQ2PSYrr 336616574U, // VCVTDQ2PSZ128rm 2551209086U, // VCVTDQ2PSZ128rmb 49306750U, // VCVTDQ2PSZ128rmbk 2532334718U, // VCVTDQ2PSZ128rmbkz 49306750U, // VCVTDQ2PSZ128rmk 2532334718U, // VCVTDQ2PSZ128rmkz 370171006U, // VCVTDQ2PSZ128rr 49306750U, // VCVTDQ2PSZ128rrk 2532334718U, // VCVTDQ2PSZ128rrkz 1041259646U, // VCVTDQ2PSZ256rm 403725438U, // VCVTDQ2PSZ256rmb 49306750U, // VCVTDQ2PSZ256rmbk 2532334718U, // VCVTDQ2PSZ256rmbkz 49306750U, // VCVTDQ2PSZ256rmk 2532334718U, // VCVTDQ2PSZ256rmkz 370171006U, // VCVTDQ2PSZ256rr 49306750U, // VCVTDQ2PSZ256rrk 2532334718U, // VCVTDQ2PSZ256rrkz 806378622U, // VCVTDQ2PSZrm 2551209086U, // VCVTDQ2PSZrmb 49306750U, // VCVTDQ2PSZrmbk 2532334718U, // VCVTDQ2PSZrmbkz 49306750U, // VCVTDQ2PSZrmk 2532334718U, // VCVTDQ2PSZrmkz 370171006U, // VCVTDQ2PSZrr 2517654654U, // VCVTDQ2PSZrrb 49306750U, // VCVTDQ2PSZrrbk 2532334718U, // VCVTDQ2PSZrrbkz 49306750U, // VCVTDQ2PSZrrk 2532334718U, // VCVTDQ2PSZrrkz 336616574U, // VCVTDQ2PSrm 370171006U, // VCVTDQ2PSrr 1007703588U, // VCVTPD2DQYrm 370169380U, // VCVTPD2DQYrr 672159268U, // VCVTPD2DQZ128rm 605050404U, // VCVTPD2DQZ128rmb 49305124U, // VCVTPD2DQZ128rmbk 2532333092U, // VCVTPD2DQZ128rmbkz 49305124U, // VCVTPD2DQZ128rmk 2532333092U, // VCVTPD2DQZ128rmkz 370169380U, // VCVTPD2DQZ128rr 49305124U, // VCVTPD2DQZ128rrk 2532333092U, // VCVTPD2DQZ128rrkz 1007703588U, // VCVTPD2DQZ256rm 2752534052U, // VCVTPD2DQZ256rmb 49305124U, // VCVTPD2DQZ256rmbk 2532333092U, // VCVTPD2DQZ256rmbkz 49305124U, // VCVTPD2DQZ256rmk 2532333092U, // VCVTPD2DQZ256rmkz 370169380U, // VCVTPD2DQZ256rr 49305124U, // VCVTPD2DQZ256rrk 2532333092U, // VCVTPD2DQZ256rrkz 1108366884U, // VCVTPD2DQZrm 605050404U, // VCVTPD2DQZrmb 49305124U, // VCVTPD2DQZrmbk 2532333092U, // VCVTPD2DQZrmbkz 49305124U, // VCVTPD2DQZrmk 2532333092U, // VCVTPD2DQZrmkz 370169380U, // VCVTPD2DQZrr 2517653028U, // VCVTPD2DQZrrb 49305124U, // VCVTPD2DQZrrbk 2532333092U, // VCVTPD2DQZrrbkz 49305124U, // VCVTPD2DQZrrk 2532333092U, // VCVTPD2DQZrrkz 672159268U, // VCVTPD2DQrm 370169380U, // VCVTPD2DQrr 1007705150U, // VCVTPD2PSYrm 370170942U, // VCVTPD2PSYrr 672160830U, // VCVTPD2PSZ128rm 605051966U, // VCVTPD2PSZ128rmb 49306686U, // VCVTPD2PSZ128rmbk 2532334654U, // VCVTPD2PSZ128rmbkz 49306686U, // VCVTPD2PSZ128rmk 2532334654U, // VCVTPD2PSZ128rmkz 370170942U, // VCVTPD2PSZ128rr 49306686U, // VCVTPD2PSZ128rrk 2532334654U, // VCVTPD2PSZ128rrkz 1007705150U, // VCVTPD2PSZ256rm 2752535614U, // VCVTPD2PSZ256rmb 49306686U, // VCVTPD2PSZ256rmbk 2532334654U, // VCVTPD2PSZ256rmbkz 49306686U, // VCVTPD2PSZ256rmk 2532334654U, // VCVTPD2PSZ256rmkz 370170942U, // VCVTPD2PSZ256rr 49306686U, // VCVTPD2PSZ256rrk 2532334654U, // VCVTPD2PSZ256rrkz 1108368446U, // VCVTPD2PSZrm 605051966U, // VCVTPD2PSZrmb 49306686U, // VCVTPD2PSZrmbk 2532334654U, // VCVTPD2PSZrmbkz 49306686U, // VCVTPD2PSZrmk 2532334654U, // VCVTPD2PSZrmkz 370170942U, // VCVTPD2PSZrr 2517654590U, // VCVTPD2PSZrrb 49306686U, // VCVTPD2PSZrrbk 2532334654U, // VCVTPD2PSZrrbkz 49306686U, // VCVTPD2PSZrrk 2532334654U, // VCVTPD2PSZrrkz 672160830U, // VCVTPD2PSrm 370170942U, // VCVTPD2PSrr 672159807U, // VCVTPD2QQZ128rm 605050943U, // VCVTPD2QQZ128rmb 49305663U, // VCVTPD2QQZ128rmbk 2532333631U, // VCVTPD2QQZ128rmbkz 49305663U, // VCVTPD2QQZ128rmk 2532333631U, // VCVTPD2QQZ128rmkz 370169919U, // VCVTPD2QQZ128rr 49305663U, // VCVTPD2QQZ128rrk 2532333631U, // VCVTPD2QQZ128rrkz 1007704127U, // VCVTPD2QQZ256rm 2752534591U, // VCVTPD2QQZ256rmb 49305663U, // VCVTPD2QQZ256rmbk 2532333631U, // VCVTPD2QQZ256rmbkz 49305663U, // VCVTPD2QQZ256rmk 2532333631U, // VCVTPD2QQZ256rmkz 370169919U, // VCVTPD2QQZ256rr 49305663U, // VCVTPD2QQZ256rrk 2532333631U, // VCVTPD2QQZ256rrkz 1108367423U, // VCVTPD2QQZrm 605050943U, // VCVTPD2QQZrmb 49305663U, // VCVTPD2QQZrmbk 2532333631U, // VCVTPD2QQZrmbkz 49305663U, // VCVTPD2QQZrmk 2532333631U, // VCVTPD2QQZrmkz 370169919U, // VCVTPD2QQZrr 2517653567U, // VCVTPD2QQZrrb 49305663U, // VCVTPD2QQZrrbk 2532333631U, // VCVTPD2QQZrrbkz 49305663U, // VCVTPD2QQZrrk 2532333631U, // VCVTPD2QQZrrkz 672159537U, // VCVTPD2UDQZ128rm 605050673U, // VCVTPD2UDQZ128rmb 49305393U, // VCVTPD2UDQZ128rmbk 2532333361U, // VCVTPD2UDQZ128rmbkz 49305393U, // VCVTPD2UDQZ128rmk 2532333361U, // VCVTPD2UDQZ128rmkz 370169649U, // VCVTPD2UDQZ128rr 49305393U, // VCVTPD2UDQZ128rrk 2532333361U, // VCVTPD2UDQZ128rrkz 1007703857U, // VCVTPD2UDQZ256rm 2752534321U, // VCVTPD2UDQZ256rmb 49305393U, // VCVTPD2UDQZ256rmbk 2532333361U, // VCVTPD2UDQZ256rmbkz 49305393U, // VCVTPD2UDQZ256rmk 2532333361U, // VCVTPD2UDQZ256rmkz 370169649U, // VCVTPD2UDQZ256rr 49305393U, // VCVTPD2UDQZ256rrk 2532333361U, // VCVTPD2UDQZ256rrkz 1108367153U, // VCVTPD2UDQZrm 605050673U, // VCVTPD2UDQZrmb 49305393U, // VCVTPD2UDQZrmbk 2532333361U, // VCVTPD2UDQZrmbkz 49305393U, // VCVTPD2UDQZrmk 2532333361U, // VCVTPD2UDQZrmkz 370169649U, // VCVTPD2UDQZrr 2517653297U, // VCVTPD2UDQZrrb 49305393U, // VCVTPD2UDQZrrbk 2532333361U, // VCVTPD2UDQZrrbkz 49305393U, // VCVTPD2UDQZrrk 2532333361U, // VCVTPD2UDQZrrkz 672159889U, // VCVTPD2UQQZ128rm 605051025U, // VCVTPD2UQQZ128rmb 49305745U, // VCVTPD2UQQZ128rmbk 2532333713U, // VCVTPD2UQQZ128rmbkz 49305745U, // VCVTPD2UQQZ128rmk 2532333713U, // VCVTPD2UQQZ128rmkz 370170001U, // VCVTPD2UQQZ128rr 49305745U, // VCVTPD2UQQZ128rrk 2532333713U, // VCVTPD2UQQZ128rrkz 1007704209U, // VCVTPD2UQQZ256rm 2752534673U, // VCVTPD2UQQZ256rmb 49305745U, // VCVTPD2UQQZ256rmbk 2532333713U, // VCVTPD2UQQZ256rmbkz 49305745U, // VCVTPD2UQQZ256rmk 2532333713U, // VCVTPD2UQQZ256rmkz 370170001U, // VCVTPD2UQQZ256rr 49305745U, // VCVTPD2UQQZ256rrk 2532333713U, // VCVTPD2UQQZ256rrkz 1108367505U, // VCVTPD2UQQZrm 605051025U, // VCVTPD2UQQZrmb 49305745U, // VCVTPD2UQQZrmbk 2532333713U, // VCVTPD2UQQZrmbkz 49305745U, // VCVTPD2UQQZrmk 2532333713U, // VCVTPD2UQQZrmkz 370170001U, // VCVTPD2UQQZrr 2517653649U, // VCVTPD2UQQZrrb 49305745U, // VCVTPD2UQQZrrbk 2532333713U, // VCVTPD2UQQZrrbkz 49305745U, // VCVTPD2UQQZrrk 2532333713U, // VCVTPD2UQQZrrkz 672160841U, // VCVTPH2PSYrm 370170953U, // VCVTPH2PSYrr 605051977U, // VCVTPH2PSZ128rm 49306697U, // VCVTPH2PSZ128rmk 2532334665U, // VCVTPH2PSZ128rmkz 370170953U, // VCVTPH2PSZ128rr 49306697U, // VCVTPH2PSZ128rrk 2532334665U, // VCVTPH2PSZ128rrkz 672160841U, // VCVTPH2PSZ256rm 49306697U, // VCVTPH2PSZ256rmk 2532334665U, // VCVTPH2PSZ256rmkz 370170953U, // VCVTPH2PSZ256rr 49306697U, // VCVTPH2PSZ256rrk 2532334665U, // VCVTPH2PSZ256rrkz 1007705161U, // VCVTPH2PSZrm 49306697U, // VCVTPH2PSZrmk 2532334665U, // VCVTPH2PSZrmkz 370170953U, // VCVTPH2PSZrr 2517654601U, // VCVTPH2PSZrrb 49306697U, // VCVTPH2PSZrrbk 2532334665U, // VCVTPH2PSZrrbkz 49306697U, // VCVTPH2PSZrrk 2532334665U, // VCVTPH2PSZrrkz 605051977U, // VCVTPH2PSrm 370170953U, // VCVTPH2PSrr 1007703620U, // VCVTPS2DQYrm 370169412U, // VCVTPS2DQYrr 672159300U, // VCVTPS2DQZ128rm 2786088516U, // VCVTPS2DQZ128rmb 49305156U, // VCVTPS2DQZ128rmbk 2532333124U, // VCVTPS2DQZ128rmbkz 49305156U, // VCVTPS2DQZ128rmk 2532333124U, // VCVTPS2DQZ128rmkz 370169412U, // VCVTPS2DQZ128rr 49305156U, // VCVTPS2DQZ128rrk 2532333124U, // VCVTPS2DQZ128rrkz 1007703620U, // VCVTPS2DQZ256rm 638604868U, // VCVTPS2DQZ256rmb 49305156U, // VCVTPS2DQZ256rmbk 2532333124U, // VCVTPS2DQZ256rmbkz 49305156U, // VCVTPS2DQZ256rmk 2532333124U, // VCVTPS2DQZ256rmkz 370169412U, // VCVTPS2DQZ256rr 49305156U, // VCVTPS2DQZ256rrk 2532333124U, // VCVTPS2DQZ256rrkz 1108366916U, // VCVTPS2DQZrm 2786088516U, // VCVTPS2DQZrmb 49305156U, // VCVTPS2DQZrmbk 2532333124U, // VCVTPS2DQZrmbkz 49305156U, // VCVTPS2DQZrmk 2532333124U, // VCVTPS2DQZrmkz 370169412U, // VCVTPS2DQZrr 2517653060U, // VCVTPS2DQZrrb 49305156U, // VCVTPS2DQZrrbk 2532333124U, // VCVTPS2DQZrrbkz 49305156U, // VCVTPS2DQZrrk 2532333124U, // VCVTPS2DQZrrkz 672159300U, // VCVTPS2DQrm 370169412U, // VCVTPS2DQrr 672156145U, // VCVTPS2PDYrm 370166257U, // VCVTPS2PDYrr 605047281U, // VCVTPS2PDZ128rm 638601713U, // VCVTPS2PDZ128rmb 49302001U, // VCVTPS2PDZ128rmbk 2532329969U, // VCVTPS2PDZ128rmbkz 49302001U, // VCVTPS2PDZ128rmk 2532329969U, // VCVTPS2PDZ128rmkz 370166257U, // VCVTPS2PDZ128rr 49302001U, // VCVTPS2PDZ128rrk 2532329969U, // VCVTPS2PDZ128rrkz 672156145U, // VCVTPS2PDZ256rm 2786085361U, // VCVTPS2PDZ256rmb 49302001U, // VCVTPS2PDZ256rmbk 2532329969U, // VCVTPS2PDZ256rmbkz 49302001U, // VCVTPS2PDZ256rmk 2532329969U, // VCVTPS2PDZ256rmkz 370166257U, // VCVTPS2PDZ256rr 49302001U, // VCVTPS2PDZ256rrk 2532329969U, // VCVTPS2PDZ256rrkz 1007700465U, // VCVTPS2PDZrm 638601713U, // VCVTPS2PDZrmb 49302001U, // VCVTPS2PDZrmbk 2532329969U, // VCVTPS2PDZrmbkz 49302001U, // VCVTPS2PDZrmk 2532329969U, // VCVTPS2PDZrmkz 370166257U, // VCVTPS2PDZrr 2517649905U, // VCVTPS2PDZrrb 49302001U, // VCVTPS2PDZrrbk 2532329969U, // VCVTPS2PDZrrbkz 49302001U, // VCVTPS2PDZrrk 2532329969U, // VCVTPS2PDZrrkz 605047281U, // VCVTPS2PDrm 370166257U, // VCVTPS2PDrr 2149061219U, // VCVTPS2PHYmr 2517652067U, // VCVTPS2PHYrr 2148668003U, // VCVTPS2PHZ128mr 15864419U, // VCVTPS2PHZ128mrk 2517652067U, // VCVTPS2PHZ128rr 49304163U, // VCVTPS2PHZ128rrk 2532332131U, // VCVTPS2PHZ128rrkz 2149061219U, // VCVTPS2PHZ256mr 16257635U, // VCVTPS2PHZ256mrk 2517652067U, // VCVTPS2PHZ256rr 49304163U, // VCVTPS2PHZ256rrk 2532332131U, // VCVTPS2PHZ256rrkz 2149126755U, // VCVTPS2PHZmr 16323171U, // VCVTPS2PHZmrk 2517652067U, // VCVTPS2PHZrr 370168419U, // VCVTPS2PHZrrb 49304163U, // VCVTPS2PHZrrbk 2532332131U, // VCVTPS2PHZrrbkz 49304163U, // VCVTPS2PHZrrk 2532332131U, // VCVTPS2PHZrrkz 2148668003U, // VCVTPS2PHmr 2517652067U, // VCVTPS2PHrr 605050966U, // VCVTPS2QQZ128rm 638605398U, // VCVTPS2QQZ128rmb 49305686U, // VCVTPS2QQZ128rmbk 2532333654U, // VCVTPS2QQZ128rmbkz 49305686U, // VCVTPS2QQZ128rmk 2532333654U, // VCVTPS2QQZ128rmkz 370169942U, // VCVTPS2QQZ128rr 49305686U, // VCVTPS2QQZ128rrk 2532333654U, // VCVTPS2QQZ128rrkz 672159830U, // VCVTPS2QQZ256rm 2786089046U, // VCVTPS2QQZ256rmb 49305686U, // VCVTPS2QQZ256rmbk 2532333654U, // VCVTPS2QQZ256rmbkz 49305686U, // VCVTPS2QQZ256rmk 2532333654U, // VCVTPS2QQZ256rmkz 370169942U, // VCVTPS2QQZ256rr 49305686U, // VCVTPS2QQZ256rrk 2532333654U, // VCVTPS2QQZ256rrkz 1007704150U, // VCVTPS2QQZrm 638605398U, // VCVTPS2QQZrmb 49305686U, // VCVTPS2QQZrmbk 2532333654U, // VCVTPS2QQZrmbkz 49305686U, // VCVTPS2QQZrmk 2532333654U, // VCVTPS2QQZrmkz 370169942U, // VCVTPS2QQZrr 2517653590U, // VCVTPS2QQZrrb 49305686U, // VCVTPS2QQZrrbk 2532333654U, // VCVTPS2QQZrrbkz 49305686U, // VCVTPS2QQZrrk 2532333654U, // VCVTPS2QQZrrkz 672159562U, // VCVTPS2UDQZ128rm 2786088778U, // VCVTPS2UDQZ128rmb 49305418U, // VCVTPS2UDQZ128rmbk 2532333386U, // VCVTPS2UDQZ128rmbkz 49305418U, // VCVTPS2UDQZ128rmk 2532333386U, // VCVTPS2UDQZ128rmkz 370169674U, // VCVTPS2UDQZ128rr 49305418U, // VCVTPS2UDQZ128rrk 2532333386U, // VCVTPS2UDQZ128rrkz 1007703882U, // VCVTPS2UDQZ256rm 638605130U, // VCVTPS2UDQZ256rmb 49305418U, // VCVTPS2UDQZ256rmbk 2532333386U, // VCVTPS2UDQZ256rmbkz 49305418U, // VCVTPS2UDQZ256rmk 2532333386U, // VCVTPS2UDQZ256rmkz 370169674U, // VCVTPS2UDQZ256rr 49305418U, // VCVTPS2UDQZ256rrk 2532333386U, // VCVTPS2UDQZ256rrkz 1108367178U, // VCVTPS2UDQZrm 2786088778U, // VCVTPS2UDQZrmb 49305418U, // VCVTPS2UDQZrmbk 2532333386U, // VCVTPS2UDQZrmbkz 49305418U, // VCVTPS2UDQZrmk 2532333386U, // VCVTPS2UDQZrmkz 370169674U, // VCVTPS2UDQZrr 2517653322U, // VCVTPS2UDQZrrb 49305418U, // VCVTPS2UDQZrrbk 2532333386U, // VCVTPS2UDQZrrbkz 49305418U, // VCVTPS2UDQZrrk 2532333386U, // VCVTPS2UDQZrrkz 605051050U, // VCVTPS2UQQZ128rm 638605482U, // VCVTPS2UQQZ128rmb 49305770U, // VCVTPS2UQQZ128rmbk 2532333738U, // VCVTPS2UQQZ128rmbkz 49305770U, // VCVTPS2UQQZ128rmk 2532333738U, // VCVTPS2UQQZ128rmkz 370170026U, // VCVTPS2UQQZ128rr 49305770U, // VCVTPS2UQQZ128rrk 2532333738U, // VCVTPS2UQQZ128rrkz 672159914U, // VCVTPS2UQQZ256rm 2786089130U, // VCVTPS2UQQZ256rmb 49305770U, // VCVTPS2UQQZ256rmbk 2532333738U, // VCVTPS2UQQZ256rmbkz 49305770U, // VCVTPS2UQQZ256rmk 2532333738U, // VCVTPS2UQQZ256rmkz 370170026U, // VCVTPS2UQQZ256rr 49305770U, // VCVTPS2UQQZ256rrk 2532333738U, // VCVTPS2UQQZ256rrkz 1007704234U, // VCVTPS2UQQZrm 638605482U, // VCVTPS2UQQZrmb 49305770U, // VCVTPS2UQQZrmbk 2532333738U, // VCVTPS2UQQZrmbkz 49305770U, // VCVTPS2UQQZrmk 2532333738U, // VCVTPS2UQQZrmkz 370170026U, // VCVTPS2UQQZrr 2517653674U, // VCVTPS2UQQZrrb 49305770U, // VCVTPS2UQQZrrbk 2532333738U, // VCVTPS2UQQZrrbkz 49305770U, // VCVTPS2UQQZrrk 2532333738U, // VCVTPS2UQQZrrkz 336611802U, // VCVTQQ2PDZ128rm 437275098U, // VCVTQQ2PDZ128rmb 49301978U, // VCVTQQ2PDZ128rmbk 2532329946U, // VCVTQQ2PDZ128rmbkz 49301978U, // VCVTQQ2PDZ128rmk 2532329946U, // VCVTQQ2PDZ128rmkz 370166234U, // VCVTQQ2PDZ128rr 49301978U, // VCVTQQ2PDZ128rrk 2532329946U, // VCVTQQ2PDZ128rrkz 1041254874U, // VCVTQQ2PDZ256rm 2584758746U, // VCVTQQ2PDZ256rmb 49301978U, // VCVTQQ2PDZ256rmbk 2532329946U, // VCVTQQ2PDZ256rmbkz 49301978U, // VCVTQQ2PDZ256rmk 2532329946U, // VCVTQQ2PDZ256rmkz 370166234U, // VCVTQQ2PDZ256rr 49301978U, // VCVTQQ2PDZ256rrk 2532329946U, // VCVTQQ2PDZ256rrkz 806373850U, // VCVTQQ2PDZrm 437275098U, // VCVTQQ2PDZrmb 49301978U, // VCVTQQ2PDZrmbk 2532329946U, // VCVTQQ2PDZrmbkz 49301978U, // VCVTQQ2PDZrmk 2532329946U, // VCVTQQ2PDZrmkz 370166234U, // VCVTQQ2PDZrr 2517649882U, // VCVTQQ2PDZrrb 49301978U, // VCVTQQ2PDZrrbk 2532329946U, // VCVTQQ2PDZrrbkz 49301978U, // VCVTQQ2PDZrrk 2532329946U, // VCVTQQ2PDZrrkz 336616597U, // VCVTQQ2PSZ128rm 437279893U, // VCVTQQ2PSZ128rmb 49306773U, // VCVTQQ2PSZ128rmbk 2532334741U, // VCVTQQ2PSZ128rmbkz 49306773U, // VCVTQQ2PSZ128rmk 2532334741U, // VCVTQQ2PSZ128rmkz 370171029U, // VCVTQQ2PSZ128rr 49306773U, // VCVTQQ2PSZ128rrk 2532334741U, // VCVTQQ2PSZ128rrkz 1041259669U, // VCVTQQ2PSZ256rm 2584763541U, // VCVTQQ2PSZ256rmb 49306773U, // VCVTQQ2PSZ256rmbk 2532334741U, // VCVTQQ2PSZ256rmbkz 49306773U, // VCVTQQ2PSZ256rmk 2532334741U, // VCVTQQ2PSZ256rmkz 370171029U, // VCVTQQ2PSZ256rr 49306773U, // VCVTQQ2PSZ256rrk 2532334741U, // VCVTQQ2PSZ256rrkz 806378645U, // VCVTQQ2PSZrm 437279893U, // VCVTQQ2PSZrmb 49306773U, // VCVTQQ2PSZrmbk 2532334741U, // VCVTQQ2PSZrmbkz 49306773U, // VCVTQQ2PSZrmk 2532334741U, // VCVTQQ2PSZrmkz 370171029U, // VCVTQQ2PSZrr 2517654677U, // VCVTQQ2PSZrrb 49306773U, // VCVTQQ2PSZrrbk 2532334741U, // VCVTQQ2PSZrrbkz 49306773U, // VCVTQQ2PSZrrk 2532334741U, // VCVTQQ2PSZrrkz 605049623U, // VCVTSD2SI64Zrm_Int 370168599U, // VCVTSD2SI64Zrr_Int 2517652247U, // VCVTSD2SI64Zrrb_Int 605049623U, // VCVTSD2SI64rm_Int 370168599U, // VCVTSD2SI64rr_Int 605049623U, // VCVTSD2SIZrm_Int 370168599U, // VCVTSD2SIZrr_Int 2517652247U, // VCVTSD2SIZrrb_Int 605049623U, // VCVTSD2SIrm_Int 370168599U, // VCVTSD2SIrr_Int 2517655590U, // VCVTSD2SSZrm 2517655590U, // VCVTSD2SSZrm_Int 49307686U, // VCVTSD2SSZrm_Intk 2532335654U, // VCVTSD2SSZrm_Intkz 2517655590U, // VCVTSD2SSZrr 2517655590U, // VCVTSD2SSZrr_Int 49307686U, // VCVTSD2SSZrr_Intk 2532335654U, // VCVTSD2SSZrr_Intkz 2517655590U, // VCVTSD2SSZrrb_Int 49307686U, // VCVTSD2SSZrrb_Intk 2532335654U, // VCVTSD2SSZrrb_Intkz 2517655590U, // VCVTSD2SSrm 2517655590U, // VCVTSD2SSrm_Int 2517655590U, // VCVTSD2SSrr 2517655590U, // VCVTSD2SSrr_Int 605049676U, // VCVTSD2USI64Zrm_Int 370168652U, // VCVTSD2USI64Zrr_Int 2517652300U, // VCVTSD2USI64Zrrb_Int 605049676U, // VCVTSD2USIZrm_Int 370168652U, // VCVTSD2USIZrr_Int 2517652300U, // VCVTSD2USIZrrb_Int 2517650889U, // VCVTSI2SDZrm 2517650889U, // VCVTSI2SDZrm_Int 2517650889U, // VCVTSI2SDZrr 2517650889U, // VCVTSI2SDZrr_Int 2517650889U, // VCVTSI2SDZrrb_Int 2517650889U, // VCVTSI2SDrm 2517650889U, // VCVTSI2SDrm_Int 2517650889U, // VCVTSI2SDrr 2517650889U, // VCVTSI2SDrr_Int 2517655601U, // VCVTSI2SSZrm 2517655601U, // VCVTSI2SSZrm_Int 2517655601U, // VCVTSI2SSZrr 2517655601U, // VCVTSI2SSZrr_Int 2517655601U, // VCVTSI2SSZrrb_Int 2517655601U, // VCVTSI2SSrm 2517655601U, // VCVTSI2SSrm_Int 2517655601U, // VCVTSI2SSrr 2517655601U, // VCVTSI2SSrr_Int 2517650889U, // VCVTSI642SDZrm 2517650889U, // VCVTSI642SDZrm_Int 2517650889U, // VCVTSI642SDZrr 2517650889U, // VCVTSI642SDZrr_Int 2517650889U, // VCVTSI642SDZrrb_Int 2517650889U, // VCVTSI642SDrm 2517650889U, // VCVTSI642SDrm_Int 2517650889U, // VCVTSI642SDrr 2517650889U, // VCVTSI642SDrr_Int 2517655601U, // VCVTSI642SSZrm 2517655601U, // VCVTSI642SSZrm_Int 2517655601U, // VCVTSI642SSZrr 2517655601U, // VCVTSI642SSZrr_Int 2517655601U, // VCVTSI642SSZrrb_Int 2517655601U, // VCVTSI642SSrm 2517655601U, // VCVTSI642SSrm_Int 2517655601U, // VCVTSI642SSrr 2517655601U, // VCVTSI642SSrr_Int 2517650912U, // VCVTSS2SDZrm 2517650912U, // VCVTSS2SDZrm_Int 49303008U, // VCVTSS2SDZrm_Intk 2532330976U, // VCVTSS2SDZrm_Intkz 2517650912U, // VCVTSS2SDZrr 2517650912U, // VCVTSS2SDZrr_Int 49303008U, // VCVTSS2SDZrr_Intk 2532330976U, // VCVTSS2SDZrr_Intkz 2517650912U, // VCVTSS2SDZrrb_Int 49303008U, // VCVTSS2SDZrrb_Intk 2532330976U, // VCVTSS2SDZrrb_Intkz 2517650912U, // VCVTSS2SDrm 2517650912U, // VCVTSS2SDrm_Int 2517650912U, // VCVTSS2SDrr 2517650912U, // VCVTSS2SDrr_Int 638604078U, // VCVTSS2SI64Zrm_Int 370168622U, // VCVTSS2SI64Zrr_Int 2517652270U, // VCVTSS2SI64Zrrb_Int 638604078U, // VCVTSS2SI64rm_Int 370168622U, // VCVTSS2SI64rr_Int 638604078U, // VCVTSS2SIZrm_Int 370168622U, // VCVTSS2SIZrr_Int 2517652270U, // VCVTSS2SIZrrb_Int 638604078U, // VCVTSS2SIrm_Int 370168622U, // VCVTSS2SIrr_Int 638604133U, // VCVTSS2USI64Zrm_Int 370168677U, // VCVTSS2USI64Zrr_Int 2517652325U, // VCVTSS2USI64Zrrb_Int 638604133U, // VCVTSS2USIZrm_Int 370168677U, // VCVTSS2USIZrr_Int 2517652325U, // VCVTSS2USIZrrb_Int 1007703576U, // VCVTTPD2DQYrm 370169368U, // VCVTTPD2DQYrr 672159256U, // VCVTTPD2DQZ128rm 605050392U, // VCVTTPD2DQZ128rmb 49305112U, // VCVTTPD2DQZ128rmbk 2532333080U, // VCVTTPD2DQZ128rmbkz 49305112U, // VCVTTPD2DQZ128rmk 2532333080U, // VCVTTPD2DQZ128rmkz 370169368U, // VCVTTPD2DQZ128rr 49305112U, // VCVTTPD2DQZ128rrk 2532333080U, // VCVTTPD2DQZ128rrkz 1007703576U, // VCVTTPD2DQZ256rm 2752534040U, // VCVTTPD2DQZ256rmb 49305112U, // VCVTTPD2DQZ256rmbk 2532333080U, // VCVTTPD2DQZ256rmbkz 49305112U, // VCVTTPD2DQZ256rmk 2532333080U, // VCVTTPD2DQZ256rmkz 370169368U, // VCVTTPD2DQZ256rr 49305112U, // VCVTTPD2DQZ256rrk 2532333080U, // VCVTTPD2DQZ256rrkz 1108366872U, // VCVTTPD2DQZrm 605050392U, // VCVTTPD2DQZrmb 49305112U, // VCVTTPD2DQZrmbk 2532333080U, // VCVTTPD2DQZrmbkz 49305112U, // VCVTTPD2DQZrmk 2532333080U, // VCVTTPD2DQZrmkz 370169368U, // VCVTTPD2DQZrr 2517653016U, // VCVTTPD2DQZrrb 49305112U, // VCVTTPD2DQZrrbk 2532333080U, // VCVTTPD2DQZrrbkz 49305112U, // VCVTTPD2DQZrrk 2532333080U, // VCVTTPD2DQZrrkz 672159256U, // VCVTTPD2DQrm 370169368U, // VCVTTPD2DQrr 672159795U, // VCVTTPD2QQZ128rm 605050931U, // VCVTTPD2QQZ128rmb 49305651U, // VCVTTPD2QQZ128rmbk 2532333619U, // VCVTTPD2QQZ128rmbkz 49305651U, // VCVTTPD2QQZ128rmk 2532333619U, // VCVTTPD2QQZ128rmkz 370169907U, // VCVTTPD2QQZ128rr 49305651U, // VCVTTPD2QQZ128rrk 2532333619U, // VCVTTPD2QQZ128rrkz 1007704115U, // VCVTTPD2QQZ256rm 2752534579U, // VCVTTPD2QQZ256rmb 49305651U, // VCVTTPD2QQZ256rmbk 2532333619U, // VCVTTPD2QQZ256rmbkz 49305651U, // VCVTTPD2QQZ256rmk 2532333619U, // VCVTTPD2QQZ256rmkz 370169907U, // VCVTTPD2QQZ256rr 49305651U, // VCVTTPD2QQZ256rrk 2532333619U, // VCVTTPD2QQZ256rrkz 1108367411U, // VCVTTPD2QQZrm 605050931U, // VCVTTPD2QQZrmb 49305651U, // VCVTTPD2QQZrmbk 2532333619U, // VCVTTPD2QQZrmbkz 49305651U, // VCVTTPD2QQZrmk 2532333619U, // VCVTTPD2QQZrmkz 370169907U, // VCVTTPD2QQZrr 2517653555U, // VCVTTPD2QQZrrb 49305651U, // VCVTTPD2QQZrrbk 2532333619U, // VCVTTPD2QQZrrbkz 49305651U, // VCVTTPD2QQZrrk 2532333619U, // VCVTTPD2QQZrrkz 672159524U, // VCVTTPD2UDQZ128rm 605050660U, // VCVTTPD2UDQZ128rmb 49305380U, // VCVTTPD2UDQZ128rmbk 2532333348U, // VCVTTPD2UDQZ128rmbkz 49305380U, // VCVTTPD2UDQZ128rmk 2532333348U, // VCVTTPD2UDQZ128rmkz 370169636U, // VCVTTPD2UDQZ128rr 49305380U, // VCVTTPD2UDQZ128rrk 2532333348U, // VCVTTPD2UDQZ128rrkz 1007703844U, // VCVTTPD2UDQZ256rm 2752534308U, // VCVTTPD2UDQZ256rmb 49305380U, // VCVTTPD2UDQZ256rmbk 2532333348U, // VCVTTPD2UDQZ256rmbkz 49305380U, // VCVTTPD2UDQZ256rmk 2532333348U, // VCVTTPD2UDQZ256rmkz 370169636U, // VCVTTPD2UDQZ256rr 49305380U, // VCVTTPD2UDQZ256rrk 2532333348U, // VCVTTPD2UDQZ256rrkz 1108367140U, // VCVTTPD2UDQZrm 605050660U, // VCVTTPD2UDQZrmb 49305380U, // VCVTTPD2UDQZrmbk 2532333348U, // VCVTTPD2UDQZrmbkz 49305380U, // VCVTTPD2UDQZrmk 2532333348U, // VCVTTPD2UDQZrmkz 370169636U, // VCVTTPD2UDQZrr 2517653284U, // VCVTTPD2UDQZrrb 49305380U, // VCVTTPD2UDQZrrbk 2532333348U, // VCVTTPD2UDQZrrbkz 49305380U, // VCVTTPD2UDQZrrk 2532333348U, // VCVTTPD2UDQZrrkz 672159876U, // VCVTTPD2UQQZ128rm 605051012U, // VCVTTPD2UQQZ128rmb 49305732U, // VCVTTPD2UQQZ128rmbk 2532333700U, // VCVTTPD2UQQZ128rmbkz 49305732U, // VCVTTPD2UQQZ128rmk 2532333700U, // VCVTTPD2UQQZ128rmkz 370169988U, // VCVTTPD2UQQZ128rr 49305732U, // VCVTTPD2UQQZ128rrk 2532333700U, // VCVTTPD2UQQZ128rrkz 1007704196U, // VCVTTPD2UQQZ256rm 2752534660U, // VCVTTPD2UQQZ256rmb 49305732U, // VCVTTPD2UQQZ256rmbk 2532333700U, // VCVTTPD2UQQZ256rmbkz 49305732U, // VCVTTPD2UQQZ256rmk 2532333700U, // VCVTTPD2UQQZ256rmkz 370169988U, // VCVTTPD2UQQZ256rr 49305732U, // VCVTTPD2UQQZ256rrk 2532333700U, // VCVTTPD2UQQZ256rrkz 1108367492U, // VCVTTPD2UQQZrm 605051012U, // VCVTTPD2UQQZrmb 49305732U, // VCVTTPD2UQQZrmbk 2532333700U, // VCVTTPD2UQQZrmbkz 49305732U, // VCVTTPD2UQQZrmk 2532333700U, // VCVTTPD2UQQZrmkz 370169988U, // VCVTTPD2UQQZrr 2517653636U, // VCVTTPD2UQQZrrb 49305732U, // VCVTTPD2UQQZrrbk 2532333700U, // VCVTTPD2UQQZrrbkz 49305732U, // VCVTTPD2UQQZrrk 2532333700U, // VCVTTPD2UQQZrrkz 1007703608U, // VCVTTPS2DQYrm 370169400U, // VCVTTPS2DQYrr 672159288U, // VCVTTPS2DQZ128rm 2786088504U, // VCVTTPS2DQZ128rmb 49305144U, // VCVTTPS2DQZ128rmbk 2532333112U, // VCVTTPS2DQZ128rmbkz 49305144U, // VCVTTPS2DQZ128rmk 2532333112U, // VCVTTPS2DQZ128rmkz 370169400U, // VCVTTPS2DQZ128rr 49305144U, // VCVTTPS2DQZ128rrk 2532333112U, // VCVTTPS2DQZ128rrkz 1007703608U, // VCVTTPS2DQZ256rm 638604856U, // VCVTTPS2DQZ256rmb 49305144U, // VCVTTPS2DQZ256rmbk 2532333112U, // VCVTTPS2DQZ256rmbkz 49305144U, // VCVTTPS2DQZ256rmk 2532333112U, // VCVTTPS2DQZ256rmkz 370169400U, // VCVTTPS2DQZ256rr 49305144U, // VCVTTPS2DQZ256rrk 2532333112U, // VCVTTPS2DQZ256rrkz 1108366904U, // VCVTTPS2DQZrm 2786088504U, // VCVTTPS2DQZrmb 49305144U, // VCVTTPS2DQZrmbk 2532333112U, // VCVTTPS2DQZrmbkz 49305144U, // VCVTTPS2DQZrmk 2532333112U, // VCVTTPS2DQZrmkz 370169400U, // VCVTTPS2DQZrr 2517653048U, // VCVTTPS2DQZrrb 49305144U, // VCVTTPS2DQZrrbk 2532333112U, // VCVTTPS2DQZrrbkz 49305144U, // VCVTTPS2DQZrrk 2532333112U, // VCVTTPS2DQZrrkz 672159288U, // VCVTTPS2DQrm 370169400U, // VCVTTPS2DQrr 605050954U, // VCVTTPS2QQZ128rm 638605386U, // VCVTTPS2QQZ128rmb 49305674U, // VCVTTPS2QQZ128rmbk 2532333642U, // VCVTTPS2QQZ128rmbkz 49305674U, // VCVTTPS2QQZ128rmk 2532333642U, // VCVTTPS2QQZ128rmkz 370169930U, // VCVTTPS2QQZ128rr 49305674U, // VCVTTPS2QQZ128rrk 2532333642U, // VCVTTPS2QQZ128rrkz 672159818U, // VCVTTPS2QQZ256rm 2786089034U, // VCVTTPS2QQZ256rmb 49305674U, // VCVTTPS2QQZ256rmbk 2532333642U, // VCVTTPS2QQZ256rmbkz 49305674U, // VCVTTPS2QQZ256rmk 2532333642U, // VCVTTPS2QQZ256rmkz 370169930U, // VCVTTPS2QQZ256rr 49305674U, // VCVTTPS2QQZ256rrk 2532333642U, // VCVTTPS2QQZ256rrkz 1007704138U, // VCVTTPS2QQZrm 638605386U, // VCVTTPS2QQZrmb 49305674U, // VCVTTPS2QQZrmbk 2532333642U, // VCVTTPS2QQZrmbkz 49305674U, // VCVTTPS2QQZrmk 2532333642U, // VCVTTPS2QQZrmkz 370169930U, // VCVTTPS2QQZrr 2517653578U, // VCVTTPS2QQZrrb 49305674U, // VCVTTPS2QQZrrbk 2532333642U, // VCVTTPS2QQZrrbkz 49305674U, // VCVTTPS2QQZrrk 2532333642U, // VCVTTPS2QQZrrkz 672159549U, // VCVTTPS2UDQZ128rm 2786088765U, // VCVTTPS2UDQZ128rmb 49305405U, // VCVTTPS2UDQZ128rmbk 2532333373U, // VCVTTPS2UDQZ128rmbkz 49305405U, // VCVTTPS2UDQZ128rmk 2532333373U, // VCVTTPS2UDQZ128rmkz 370169661U, // VCVTTPS2UDQZ128rr 49305405U, // VCVTTPS2UDQZ128rrk 2532333373U, // VCVTTPS2UDQZ128rrkz 1007703869U, // VCVTTPS2UDQZ256rm 638605117U, // VCVTTPS2UDQZ256rmb 49305405U, // VCVTTPS2UDQZ256rmbk 2532333373U, // VCVTTPS2UDQZ256rmbkz 49305405U, // VCVTTPS2UDQZ256rmk 2532333373U, // VCVTTPS2UDQZ256rmkz 370169661U, // VCVTTPS2UDQZ256rr 49305405U, // VCVTTPS2UDQZ256rrk 2532333373U, // VCVTTPS2UDQZ256rrkz 1108367165U, // VCVTTPS2UDQZrm 2786088765U, // VCVTTPS2UDQZrmb 49305405U, // VCVTTPS2UDQZrmbk 2532333373U, // VCVTTPS2UDQZrmbkz 49305405U, // VCVTTPS2UDQZrmk 2532333373U, // VCVTTPS2UDQZrmkz 370169661U, // VCVTTPS2UDQZrr 2517653309U, // VCVTTPS2UDQZrrb 49305405U, // VCVTTPS2UDQZrrbk 2532333373U, // VCVTTPS2UDQZrrbkz 49305405U, // VCVTTPS2UDQZrrk 2532333373U, // VCVTTPS2UDQZrrkz 605051037U, // VCVTTPS2UQQZ128rm 638605469U, // VCVTTPS2UQQZ128rmb 49305757U, // VCVTTPS2UQQZ128rmbk 2532333725U, // VCVTTPS2UQQZ128rmbkz 49305757U, // VCVTTPS2UQQZ128rmk 2532333725U, // VCVTTPS2UQQZ128rmkz 370170013U, // VCVTTPS2UQQZ128rr 49305757U, // VCVTTPS2UQQZ128rrk 2532333725U, // VCVTTPS2UQQZ128rrkz 672159901U, // VCVTTPS2UQQZ256rm 2786089117U, // VCVTTPS2UQQZ256rmb 49305757U, // VCVTTPS2UQQZ256rmbk 2532333725U, // VCVTTPS2UQQZ256rmbkz 49305757U, // VCVTTPS2UQQZ256rmk 2532333725U, // VCVTTPS2UQQZ256rmkz 370170013U, // VCVTTPS2UQQZ256rr 49305757U, // VCVTTPS2UQQZ256rrk 2532333725U, // VCVTTPS2UQQZ256rrkz 1007704221U, // VCVTTPS2UQQZrm 638605469U, // VCVTTPS2UQQZrmb 49305757U, // VCVTTPS2UQQZrmbk 2532333725U, // VCVTTPS2UQQZrmbkz 49305757U, // VCVTTPS2UQQZrmk 2532333725U, // VCVTTPS2UQQZrmkz 370170013U, // VCVTTPS2UQQZrr 2517653661U, // VCVTTPS2UQQZrrb 49305757U, // VCVTTPS2UQQZrrbk 2532333725U, // VCVTTPS2UQQZrrbkz 49305757U, // VCVTTPS2UQQZrrk 2532333725U, // VCVTTPS2UQQZrrkz 605049611U, // VCVTTSD2SI64Zrm 605049611U, // VCVTTSD2SI64Zrm_Int 370168587U, // VCVTTSD2SI64Zrr 370168587U, // VCVTTSD2SI64Zrr_Int 2517652235U, // VCVTTSD2SI64Zrrb_Int 605049611U, // VCVTTSD2SI64rm 605049611U, // VCVTTSD2SI64rm_Int 370168587U, // VCVTTSD2SI64rr 370168587U, // VCVTTSD2SI64rr_Int 605049611U, // VCVTTSD2SIZrm 605049611U, // VCVTTSD2SIZrm_Int 370168587U, // VCVTTSD2SIZrr 370168587U, // VCVTTSD2SIZrr_Int 2517652235U, // VCVTTSD2SIZrrb_Int 605049611U, // VCVTTSD2SIrm 605049611U, // VCVTTSD2SIrm_Int 370168587U, // VCVTTSD2SIrr 370168587U, // VCVTTSD2SIrr_Int 605049663U, // VCVTTSD2USI64Zrm 605049663U, // VCVTTSD2USI64Zrm_Int 370168639U, // VCVTTSD2USI64Zrr 370168639U, // VCVTTSD2USI64Zrr_Int 2517652287U, // VCVTTSD2USI64Zrrb_Int 605049663U, // VCVTTSD2USIZrm 605049663U, // VCVTTSD2USIZrm_Int 370168639U, // VCVTTSD2USIZrr 370168639U, // VCVTTSD2USIZrr_Int 2517652287U, // VCVTTSD2USIZrrb_Int 638604066U, // VCVTTSS2SI64Zrm 638604066U, // VCVTTSS2SI64Zrm_Int 370168610U, // VCVTTSS2SI64Zrr 370168610U, // VCVTTSS2SI64Zrr_Int 2517652258U, // VCVTTSS2SI64Zrrb_Int 638604066U, // VCVTTSS2SI64rm 638604066U, // VCVTTSS2SI64rm_Int 370168610U, // VCVTTSS2SI64rr 370168610U, // VCVTTSS2SI64rr_Int 638604066U, // VCVTTSS2SIZrm 638604066U, // VCVTTSS2SIZrm_Int 370168610U, // VCVTTSS2SIZrr 370168610U, // VCVTTSS2SIZrr_Int 2517652258U, // VCVTTSS2SIZrrb_Int 638604066U, // VCVTTSS2SIrm 638604066U, // VCVTTSS2SIrm_Int 370168610U, // VCVTTSS2SIrr 370168610U, // VCVTTSS2SIrr_Int 638604120U, // VCVTTSS2USI64Zrm 638604120U, // VCVTTSS2USI64Zrm_Int 370168664U, // VCVTTSS2USI64Zrr 370168664U, // VCVTTSS2USI64Zrr_Int 2517652312U, // VCVTTSS2USI64Zrrb_Int 638604120U, // VCVTTSS2USIZrm 638604120U, // VCVTTSS2USIZrm_Int 370168664U, // VCVTTSS2USIZrr 370168664U, // VCVTTSS2USIZrr_Int 2517652312U, // VCVTTSS2USIZrrb_Int 437275086U, // VCVTUDQ2PDZ128rm 403720654U, // VCVTUDQ2PDZ128rmb 49301966U, // VCVTUDQ2PDZ128rmbk 2532329934U, // VCVTUDQ2PDZ128rmbkz 49301966U, // VCVTUDQ2PDZ128rmk 2532329934U, // VCVTUDQ2PDZ128rmkz 370166222U, // VCVTUDQ2PDZ128rr 49301966U, // VCVTUDQ2PDZ128rrk 2532329934U, // VCVTUDQ2PDZ128rrkz 336611790U, // VCVTUDQ2PDZ256rm 2551204302U, // VCVTUDQ2PDZ256rmb 49301966U, // VCVTUDQ2PDZ256rmbk 2532329934U, // VCVTUDQ2PDZ256rmbkz 49301966U, // VCVTUDQ2PDZ256rmk 2532329934U, // VCVTUDQ2PDZ256rmkz 370166222U, // VCVTUDQ2PDZ256rr 49301966U, // VCVTUDQ2PDZ256rrk 2532329934U, // VCVTUDQ2PDZ256rrkz 1041254862U, // VCVTUDQ2PDZrm 403720654U, // VCVTUDQ2PDZrmb 49301966U, // VCVTUDQ2PDZrmbk 2532329934U, // VCVTUDQ2PDZrmbkz 49301966U, // VCVTUDQ2PDZrmk 2532329934U, // VCVTUDQ2PDZrmkz 370166222U, // VCVTUDQ2PDZrr 49301966U, // VCVTUDQ2PDZrrk 2532329934U, // VCVTUDQ2PDZrrkz 336616585U, // VCVTUDQ2PSZ128rm 2551209097U, // VCVTUDQ2PSZ128rmb 49306761U, // VCVTUDQ2PSZ128rmbk 2532334729U, // VCVTUDQ2PSZ128rmbkz 49306761U, // VCVTUDQ2PSZ128rmk 2532334729U, // VCVTUDQ2PSZ128rmkz 370171017U, // VCVTUDQ2PSZ128rr 49306761U, // VCVTUDQ2PSZ128rrk 2532334729U, // VCVTUDQ2PSZ128rrkz 1041259657U, // VCVTUDQ2PSZ256rm 403725449U, // VCVTUDQ2PSZ256rmb 49306761U, // VCVTUDQ2PSZ256rmbk 2532334729U, // VCVTUDQ2PSZ256rmbkz 49306761U, // VCVTUDQ2PSZ256rmk 2532334729U, // VCVTUDQ2PSZ256rmkz 370171017U, // VCVTUDQ2PSZ256rr 49306761U, // VCVTUDQ2PSZ256rrk 2532334729U, // VCVTUDQ2PSZ256rrkz 806378633U, // VCVTUDQ2PSZrm 2551209097U, // VCVTUDQ2PSZrmb 49306761U, // VCVTUDQ2PSZrmbk 2532334729U, // VCVTUDQ2PSZrmbkz 49306761U, // VCVTUDQ2PSZrmk 2532334729U, // VCVTUDQ2PSZrmkz 370171017U, // VCVTUDQ2PSZrr 2517654665U, // VCVTUDQ2PSZrrb 49306761U, // VCVTUDQ2PSZrrbk 2532334729U, // VCVTUDQ2PSZrrbkz 49306761U, // VCVTUDQ2PSZrrk 2532334729U, // VCVTUDQ2PSZrrkz 336611813U, // VCVTUQQ2PDZ128rm 437275109U, // VCVTUQQ2PDZ128rmb 49301989U, // VCVTUQQ2PDZ128rmbk 2532329957U, // VCVTUQQ2PDZ128rmbkz 49301989U, // VCVTUQQ2PDZ128rmk 2532329957U, // VCVTUQQ2PDZ128rmkz 370166245U, // VCVTUQQ2PDZ128rr 49301989U, // VCVTUQQ2PDZ128rrk 2532329957U, // VCVTUQQ2PDZ128rrkz 1041254885U, // VCVTUQQ2PDZ256rm 2584758757U, // VCVTUQQ2PDZ256rmb 49301989U, // VCVTUQQ2PDZ256rmbk 2532329957U, // VCVTUQQ2PDZ256rmbkz 49301989U, // VCVTUQQ2PDZ256rmk 2532329957U, // VCVTUQQ2PDZ256rmkz 370166245U, // VCVTUQQ2PDZ256rr 49301989U, // VCVTUQQ2PDZ256rrk 2532329957U, // VCVTUQQ2PDZ256rrkz 806373861U, // VCVTUQQ2PDZrm 437275109U, // VCVTUQQ2PDZrmb 49301989U, // VCVTUQQ2PDZrmbk 2532329957U, // VCVTUQQ2PDZrmbkz 49301989U, // VCVTUQQ2PDZrmk 2532329957U, // VCVTUQQ2PDZrmkz 370166245U, // VCVTUQQ2PDZrr 2517649893U, // VCVTUQQ2PDZrrb 49301989U, // VCVTUQQ2PDZrrbk 2532329957U, // VCVTUQQ2PDZrrbkz 49301989U, // VCVTUQQ2PDZrrk 2532329957U, // VCVTUQQ2PDZrrkz 336616608U, // VCVTUQQ2PSZ128rm 437279904U, // VCVTUQQ2PSZ128rmb 49306784U, // VCVTUQQ2PSZ128rmbk 2532334752U, // VCVTUQQ2PSZ128rmbkz 49306784U, // VCVTUQQ2PSZ128rmk 2532334752U, // VCVTUQQ2PSZ128rmkz 370171040U, // VCVTUQQ2PSZ128rr 49306784U, // VCVTUQQ2PSZ128rrk 2532334752U, // VCVTUQQ2PSZ128rrkz 1041259680U, // VCVTUQQ2PSZ256rm 2584763552U, // VCVTUQQ2PSZ256rmb 49306784U, // VCVTUQQ2PSZ256rmbk 2532334752U, // VCVTUQQ2PSZ256rmbkz 49306784U, // VCVTUQQ2PSZ256rmk 2532334752U, // VCVTUQQ2PSZ256rmkz 370171040U, // VCVTUQQ2PSZ256rr 49306784U, // VCVTUQQ2PSZ256rrk 2532334752U, // VCVTUQQ2PSZ256rrkz 806378656U, // VCVTUQQ2PSZrm 437279904U, // VCVTUQQ2PSZrmb 49306784U, // VCVTUQQ2PSZrmbk 2532334752U, // VCVTUQQ2PSZrmbkz 49306784U, // VCVTUQQ2PSZrmk 2532334752U, // VCVTUQQ2PSZrmkz 370171040U, // VCVTUQQ2PSZrr 2517654688U, // VCVTUQQ2PSZrrb 49306784U, // VCVTUQQ2PSZrrbk 2532334752U, // VCVTUQQ2PSZrrbkz 49306784U, // VCVTUQQ2PSZrrk 2532334752U, // VCVTUQQ2PSZrrkz 2517650900U, // VCVTUSI2SDZrm 2517650900U, // VCVTUSI2SDZrm_Int 2517650900U, // VCVTUSI2SDZrr 2517650900U, // VCVTUSI2SDZrr_Int 2517655612U, // VCVTUSI2SSZrm 2517655612U, // VCVTUSI2SSZrm_Int 2517655612U, // VCVTUSI2SSZrr 2517655612U, // VCVTUSI2SSZrr_Int 2517655612U, // VCVTUSI2SSZrrb_Int 2517650900U, // VCVTUSI642SDZrm 2517650900U, // VCVTUSI642SDZrm_Int 2517650900U, // VCVTUSI642SDZrr 2517650900U, // VCVTUSI642SDZrr_Int 2517650900U, // VCVTUSI642SDZrrb_Int 2517655612U, // VCVTUSI642SSZrm 2517655612U, // VCVTUSI642SSZrm_Int 2517655612U, // VCVTUSI642SSZrr 2517655612U, // VCVTUSI642SSZrr_Int 2517655612U, // VCVTUSI642SSZrrb_Int 2517656413U, // VDBPSADBWZ128rmi 49308509U, // VDBPSADBWZ128rmik 2532336477U, // VDBPSADBWZ128rmikz 2517656413U, // VDBPSADBWZ128rri 49308509U, // VDBPSADBWZ128rrik 2532336477U, // VDBPSADBWZ128rrikz 2517656413U, // VDBPSADBWZ256rmi 49308509U, // VDBPSADBWZ256rmik 2532336477U, // VDBPSADBWZ256rmikz 2517656413U, // VDBPSADBWZ256rri 49308509U, // VDBPSADBWZ256rrik 2532336477U, // VDBPSADBWZ256rrikz 2517656413U, // VDBPSADBWZrmi 49308509U, // VDBPSADBWZrmik 2532336477U, // VDBPSADBWZrmikz 2517656413U, // VDBPSADBWZrri 49308509U, // VDBPSADBWZrrik 2532336477U, // VDBPSADBWZrrikz 2517650601U, // VDIVPDYrm 2517650601U, // VDIVPDYrr 2517650601U, // VDIVPDZ128rm 2517650601U, // VDIVPDZ128rmb 49302697U, // VDIVPDZ128rmbk 2532330665U, // VDIVPDZ128rmbkz 49302697U, // VDIVPDZ128rmk 2532330665U, // VDIVPDZ128rmkz 2517650601U, // VDIVPDZ128rr 49302697U, // VDIVPDZ128rrk 2532330665U, // VDIVPDZ128rrkz 2517650601U, // VDIVPDZ256rm 2517650601U, // VDIVPDZ256rmb 49302697U, // VDIVPDZ256rmbk 2532330665U, // VDIVPDZ256rmbkz 49302697U, // VDIVPDZ256rmk 2532330665U, // VDIVPDZ256rmkz 2517650601U, // VDIVPDZ256rr 49302697U, // VDIVPDZ256rrk 2532330665U, // VDIVPDZ256rrkz 2517650601U, // VDIVPDZrm 2517650601U, // VDIVPDZrmb 49302697U, // VDIVPDZrmbk 2532330665U, // VDIVPDZrmbkz 49302697U, // VDIVPDZrmk 2532330665U, // VDIVPDZrmkz 2517650601U, // VDIVPDZrr 2517650601U, // VDIVPDZrrb 49302697U, // VDIVPDZrrbk 2532330665U, // VDIVPDZrrbkz 49302697U, // VDIVPDZrrk 2532330665U, // VDIVPDZrrkz 2517650601U, // VDIVPDrm 2517650601U, // VDIVPDrr 2517655436U, // VDIVPSYrm 2517655436U, // VDIVPSYrr 2517655436U, // VDIVPSZ128rm 2517655436U, // VDIVPSZ128rmb 49307532U, // VDIVPSZ128rmbk 2532335500U, // VDIVPSZ128rmbkz 49307532U, // VDIVPSZ128rmk 2532335500U, // VDIVPSZ128rmkz 2517655436U, // VDIVPSZ128rr 49307532U, // VDIVPSZ128rrk 2532335500U, // VDIVPSZ128rrkz 2517655436U, // VDIVPSZ256rm 2517655436U, // VDIVPSZ256rmb 49307532U, // VDIVPSZ256rmbk 2532335500U, // VDIVPSZ256rmbkz 49307532U, // VDIVPSZ256rmk 2532335500U, // VDIVPSZ256rmkz 2517655436U, // VDIVPSZ256rr 49307532U, // VDIVPSZ256rrk 2532335500U, // VDIVPSZ256rrkz 2517655436U, // VDIVPSZrm 2517655436U, // VDIVPSZrmb 49307532U, // VDIVPSZrmbk 2532335500U, // VDIVPSZrmbkz 49307532U, // VDIVPSZrmk 2532335500U, // VDIVPSZrmkz 2517655436U, // VDIVPSZrr 2517655436U, // VDIVPSZrrb 49307532U, // VDIVPSZrrbk 2532335500U, // VDIVPSZrrbkz 49307532U, // VDIVPSZrrk 2532335500U, // VDIVPSZrrkz 2517655436U, // VDIVPSrm 2517655436U, // VDIVPSrr 2517651340U, // VDIVSDZrm 2517651340U, // VDIVSDZrm_Int 49303436U, // VDIVSDZrm_Intk 2532331404U, // VDIVSDZrm_Intkz 2517651340U, // VDIVSDZrr 2517651340U, // VDIVSDZrr_Int 49303436U, // VDIVSDZrr_Intk 2532331404U, // VDIVSDZrr_Intkz 2517651340U, // VDIVSDZrrb_Int 49303436U, // VDIVSDZrrb_Intk 2532331404U, // VDIVSDZrrb_Intkz 2517651340U, // VDIVSDrm 2517651340U, // VDIVSDrm_Int 2517651340U, // VDIVSDrr 2517651340U, // VDIVSDrr_Int 2517655999U, // VDIVSSZrm 2517655999U, // VDIVSSZrm_Int 49308095U, // VDIVSSZrm_Intk 2532336063U, // VDIVSSZrm_Intkz 2517655999U, // VDIVSSZrr 2517655999U, // VDIVSSZrr_Int 49308095U, // VDIVSSZrr_Intk 2532336063U, // VDIVSSZrr_Intkz 2517655999U, // VDIVSSZrrb_Int 49308095U, // VDIVSSZrrb_Intk 2532336063U, // VDIVSSZrrb_Intkz 2517655999U, // VDIVSSrm 2517655999U, // VDIVSSrm_Int 2517655999U, // VDIVSSrr 2517655999U, // VDIVSSrr_Int 2517650433U, // VDPPDrmi 2517650433U, // VDPPDrri 2517655252U, // VDPPSYrmi 2517655252U, // VDPPSYrri 2517655252U, // VDPPSrmi 2517655252U, // VDPPSrri 39644U, // VERRm 23260U, // VERRr 42308U, // VERWm 25924U, // VERWr 1108363706U, // VEXP2PDZm 605047226U, // VEXP2PDZmb 49301946U, // VEXP2PDZmbk 2532329914U, // VEXP2PDZmbkz 49301946U, // VEXP2PDZmk 2532329914U, // VEXP2PDZmkz 370166202U, // VEXP2PDZr 2517649850U, // VEXP2PDZrb 49301946U, // VEXP2PDZrbk 2532329914U, // VEXP2PDZrbkz 49301946U, // VEXP2PDZrk 2532329914U, // VEXP2PDZrkz 1108368501U, // VEXP2PSZm 2786090101U, // VEXP2PSZmb 49306741U, // VEXP2PSZmbk 2532334709U, // VEXP2PSZmbkz 49306741U, // VEXP2PSZmk 2532334709U, // VEXP2PSZmkz 370170997U, // VEXP2PSZr 2517654645U, // VEXP2PSZrb 49306741U, // VEXP2PSZrbk 2532334709U, // VEXP2PSZrbkz 49306741U, // VEXP2PSZrk 2532334709U, // VEXP2PSZrkz 672156427U, // VEXPANDPDZ128rm 49302283U, // VEXPANDPDZ128rmk 2532330251U, // VEXPANDPDZ128rmkz 370166539U, // VEXPANDPDZ128rr 49302283U, // VEXPANDPDZ128rrk 2532330251U, // VEXPANDPDZ128rrkz 1007700747U, // VEXPANDPDZ256rm 49302283U, // VEXPANDPDZ256rmk 2532330251U, // VEXPANDPDZ256rmkz 370166539U, // VEXPANDPDZ256rr 49302283U, // VEXPANDPDZ256rrk 2532330251U, // VEXPANDPDZ256rrkz 1108364043U, // VEXPANDPDZrm 49302283U, // VEXPANDPDZrmk 2532330251U, // VEXPANDPDZrmkz 370166539U, // VEXPANDPDZrr 49302283U, // VEXPANDPDZrrk 2532330251U, // VEXPANDPDZrrkz 672161226U, // VEXPANDPSZ128rm 49307082U, // VEXPANDPSZ128rmk 2532335050U, // VEXPANDPSZ128rmkz 370171338U, // VEXPANDPSZ128rr 49307082U, // VEXPANDPSZ128rrk 2532335050U, // VEXPANDPSZ128rrkz 1007705546U, // VEXPANDPSZ256rm 49307082U, // VEXPANDPSZ256rmk 2532335050U, // VEXPANDPSZ256rmkz 370171338U, // VEXPANDPSZ256rr 49307082U, // VEXPANDPSZ256rrk 2532335050U, // VEXPANDPSZ256rrkz 1108368842U, // VEXPANDPSZrm 49307082U, // VEXPANDPSZrmk 2532335050U, // VEXPANDPSZrmkz 370171338U, // VEXPANDPSZrr 49307082U, // VEXPANDPSZrrk 2532335050U, // VEXPANDPSZrrkz 2149057156U, // VEXTRACTF128mr 2517648004U, // VEXTRACTF128rr 2149056937U, // VEXTRACTF32x4Z256mr 16253353U, // VEXTRACTF32x4Z256mrk 2517647785U, // VEXTRACTF32x4Z256rr 49299881U, // VEXTRACTF32x4Z256rrk 2532327849U, // VEXTRACTF32x4Z256rrkz 2149056937U, // VEXTRACTF32x4Zmr 16253353U, // VEXTRACTF32x4Zmrk 2517647785U, // VEXTRACTF32x4Zrr 49299881U, // VEXTRACTF32x4Zrrk 2532327849U, // VEXTRACTF32x4Zrrkz 2149122800U, // VEXTRACTF32x8Zmr 16319216U, // VEXTRACTF32x8Zmrk 2517648112U, // VEXTRACTF32x8Zrr 49300208U, // VEXTRACTF32x8Zrrk 2532328176U, // VEXTRACTF32x8Zrrkz 2149056724U, // VEXTRACTF64x2Z256mr 16253140U, // VEXTRACTF64x2Z256mrk 2517647572U, // VEXTRACTF64x2Z256rr 49299668U, // VEXTRACTF64x2Z256rrk 2532327636U, // VEXTRACTF64x2Z256rrkz 2149056724U, // VEXTRACTF64x2Zmr 16253140U, // VEXTRACTF64x2Zmrk 2517647572U, // VEXTRACTF64x2Zrr 49299668U, // VEXTRACTF64x2Zrrk 2532327636U, // VEXTRACTF64x2Zrrkz 2149122577U, // VEXTRACTF64x4Zmr 16318993U, // VEXTRACTF64x4Zmrk 2517647889U, // VEXTRACTF64x4Zrr 49299985U, // VEXTRACTF64x4Zrrk 2532327953U, // VEXTRACTF64x4Zrrkz 2148680379U, // VEXTRACTI128mr 2517648059U, // VEXTRACTI128rr 2148680163U, // VEXTRACTI32x4Z256mr 15876579U, // VEXTRACTI32x4Z256mrk 2517647843U, // VEXTRACTI32x4Z256rr 49299939U, // VEXTRACTI32x4Z256rrk 2532327907U, // VEXTRACTI32x4Z256rrkz 2148680163U, // VEXTRACTI32x4Zmr 15876579U, // VEXTRACTI32x4Zmrk 2517647843U, // VEXTRACTI32x4Zrr 49299939U, // VEXTRACTI32x4Zrrk 2532327907U, // VEXTRACTI32x4Zrrkz 2149155614U, // VEXTRACTI32x8Zmr 16352030U, // VEXTRACTI32x8Zmrk 2517648158U, // VEXTRACTI32x8Zrr 49300254U, // VEXTRACTI32x8Zrrk 2532328222U, // VEXTRACTI32x8Zrrkz 2148679950U, // VEXTRACTI64x2Z256mr 15876366U, // VEXTRACTI64x2Z256mrk 2517647630U, // VEXTRACTI64x2Z256rr 49299726U, // VEXTRACTI64x2Z256rrk 2532327694U, // VEXTRACTI64x2Z256rrkz 2148679950U, // VEXTRACTI64x2Zmr 15876366U, // VEXTRACTI64x2Zmrk 2517647630U, // VEXTRACTI64x2Zrr 49299726U, // VEXTRACTI64x2Zrrk 2532327694U, // VEXTRACTI64x2Zrrkz 2149155391U, // VEXTRACTI64x4Zmr 16351807U, // VEXTRACTI64x4Zmrk 2517647935U, // VEXTRACTI64x4Zrr 49300031U, // VEXTRACTI64x4Zrrk 2532327999U, // VEXTRACTI64x4Zrrkz 2148654895U, // VEXTRACTPSZmr 2517655343U, // VEXTRACTPSZrr 2148654895U, // VEXTRACTPSmr 2517655343U, // VEXTRACTPSrr 2182106074U, // VFIXUPIMMPDZ128rmbi 49302490U, // VFIXUPIMMPDZ128rmbik 2196786138U, // VFIXUPIMMPDZ128rmbikz 2182106074U, // VFIXUPIMMPDZ128rmi 49302490U, // VFIXUPIMMPDZ128rmik 2196786138U, // VFIXUPIMMPDZ128rmikz 2182106074U, // VFIXUPIMMPDZ128rri 49302490U, // VFIXUPIMMPDZ128rrik 2196786138U, // VFIXUPIMMPDZ128rrikz 2182106074U, // VFIXUPIMMPDZ256rmbi 49302490U, // VFIXUPIMMPDZ256rmbik 2196786138U, // VFIXUPIMMPDZ256rmbikz 2182106074U, // VFIXUPIMMPDZ256rmi 49302490U, // VFIXUPIMMPDZ256rmik 2196786138U, // VFIXUPIMMPDZ256rmikz 2182106074U, // VFIXUPIMMPDZ256rri 49302490U, // VFIXUPIMMPDZ256rrik 2196786138U, // VFIXUPIMMPDZ256rrikz 2182106074U, // VFIXUPIMMPDZrmbi 49302490U, // VFIXUPIMMPDZrmbik 2196786138U, // VFIXUPIMMPDZrmbikz 2182106074U, // VFIXUPIMMPDZrmi 49302490U, // VFIXUPIMMPDZrmik 2196786138U, // VFIXUPIMMPDZrmikz 2182106074U, // VFIXUPIMMPDZrri 2182106074U, // VFIXUPIMMPDZrrib 49302490U, // VFIXUPIMMPDZrribk 2196786138U, // VFIXUPIMMPDZrribkz 49302490U, // VFIXUPIMMPDZrrik 2196786138U, // VFIXUPIMMPDZrrikz 2182110885U, // VFIXUPIMMPSZ128rmbi 49307301U, // VFIXUPIMMPSZ128rmbik 2196790949U, // VFIXUPIMMPSZ128rmbikz 2182110885U, // VFIXUPIMMPSZ128rmi 49307301U, // VFIXUPIMMPSZ128rmik 2196790949U, // VFIXUPIMMPSZ128rmikz 2182110885U, // VFIXUPIMMPSZ128rri 49307301U, // VFIXUPIMMPSZ128rrik 2196790949U, // VFIXUPIMMPSZ128rrikz 2182110885U, // VFIXUPIMMPSZ256rmbi 49307301U, // VFIXUPIMMPSZ256rmbik 2196790949U, // VFIXUPIMMPSZ256rmbikz 2182110885U, // VFIXUPIMMPSZ256rmi 49307301U, // VFIXUPIMMPSZ256rmik 2196790949U, // VFIXUPIMMPSZ256rmikz 2182110885U, // VFIXUPIMMPSZ256rri 49307301U, // VFIXUPIMMPSZ256rrik 2196790949U, // VFIXUPIMMPSZ256rrikz 2182110885U, // VFIXUPIMMPSZrmbi 49307301U, // VFIXUPIMMPSZrmbik 2196790949U, // VFIXUPIMMPSZrmbikz 2182110885U, // VFIXUPIMMPSZrmi 49307301U, // VFIXUPIMMPSZrmik 2196790949U, // VFIXUPIMMPSZrmikz 2182110885U, // VFIXUPIMMPSZrri 2182110885U, // VFIXUPIMMPSZrrib 49307301U, // VFIXUPIMMPSZrribk 2196790949U, // VFIXUPIMMPSZrribkz 49307301U, // VFIXUPIMMPSZrrik 2196790949U, // VFIXUPIMMPSZrrikz 2182106849U, // VFIXUPIMMSDZrmi 49303265U, // VFIXUPIMMSDZrmik 2196786913U, // VFIXUPIMMSDZrmikz 2182106849U, // VFIXUPIMMSDZrri 2182106849U, // VFIXUPIMMSDZrrib 49303265U, // VFIXUPIMMSDZrribk 2196786913U, // VFIXUPIMMSDZrribkz 49303265U, // VFIXUPIMMSDZrrik 2196786913U, // VFIXUPIMMSDZrrikz 2182111565U, // VFIXUPIMMSSZrmi 49307981U, // VFIXUPIMMSSZrmik 2196791629U, // VFIXUPIMMSSZrmikz 2182111565U, // VFIXUPIMMSSZrri 2182111565U, // VFIXUPIMMSSZrrib 49307981U, // VFIXUPIMMSSZrribk 2196791629U, // VFIXUPIMMSSZrribkz 49307981U, // VFIXUPIMMSSZrrik 2196791629U, // VFIXUPIMMSSZrrikz 2182105470U, // VFMADD132PDYm 2182105470U, // VFMADD132PDYr 2182105470U, // VFMADD132PDZ128m 2182105470U, // VFMADD132PDZ128mb 49301886U, // VFMADD132PDZ128mbk 2196785534U, // VFMADD132PDZ128mbkz 49301886U, // VFMADD132PDZ128mk 2196785534U, // VFMADD132PDZ128mkz 2182105470U, // VFMADD132PDZ128r 49301886U, // VFMADD132PDZ128rk 2196785534U, // VFMADD132PDZ128rkz 2182105470U, // VFMADD132PDZ256m 2182105470U, // VFMADD132PDZ256mb 49301886U, // VFMADD132PDZ256mbk 2196785534U, // VFMADD132PDZ256mbkz 49301886U, // VFMADD132PDZ256mk 2196785534U, // VFMADD132PDZ256mkz 2182105470U, // VFMADD132PDZ256r 49301886U, // VFMADD132PDZ256rk 2196785534U, // VFMADD132PDZ256rkz 2182105470U, // VFMADD132PDZm 2182105470U, // VFMADD132PDZmb 49301886U, // VFMADD132PDZmbk 2196785534U, // VFMADD132PDZmbkz 49301886U, // VFMADD132PDZmk 2196785534U, // VFMADD132PDZmkz 2182105470U, // VFMADD132PDZr 2182105470U, // VFMADD132PDZrb 49301886U, // VFMADD132PDZrbk 2196785534U, // VFMADD132PDZrbkz 49301886U, // VFMADD132PDZrk 2196785534U, // VFMADD132PDZrkz 2182105470U, // VFMADD132PDm 2182105470U, // VFMADD132PDr 2182110243U, // VFMADD132PSYm 2182110243U, // VFMADD132PSYr 2182110243U, // VFMADD132PSZ128m 2182110243U, // VFMADD132PSZ128mb 49306659U, // VFMADD132PSZ128mbk 2196790307U, // VFMADD132PSZ128mbkz 49306659U, // VFMADD132PSZ128mk 2196790307U, // VFMADD132PSZ128mkz 2182110243U, // VFMADD132PSZ128r 49306659U, // VFMADD132PSZ128rk 2196790307U, // VFMADD132PSZ128rkz 2182110243U, // VFMADD132PSZ256m 2182110243U, // VFMADD132PSZ256mb 49306659U, // VFMADD132PSZ256mbk 2196790307U, // VFMADD132PSZ256mbkz 49306659U, // VFMADD132PSZ256mk 2196790307U, // VFMADD132PSZ256mkz 2182110243U, // VFMADD132PSZ256r 49306659U, // VFMADD132PSZ256rk 2196790307U, // VFMADD132PSZ256rkz 2182110243U, // VFMADD132PSZm 2182110243U, // VFMADD132PSZmb 49306659U, // VFMADD132PSZmbk 2196790307U, // VFMADD132PSZmbkz 49306659U, // VFMADD132PSZmk 2196790307U, // VFMADD132PSZmkz 2182110243U, // VFMADD132PSZr 2182110243U, // VFMADD132PSZrb 49306659U, // VFMADD132PSZrbk 2196790307U, // VFMADD132PSZrbkz 49306659U, // VFMADD132PSZrk 2196790307U, // VFMADD132PSZrkz 2182110243U, // VFMADD132PSm 2182110243U, // VFMADD132PSr 2182106542U, // VFMADD132SDZm 2182106542U, // VFMADD132SDZm_Int 49302958U, // VFMADD132SDZm_Intk 2196786606U, // VFMADD132SDZm_Intkz 2182106542U, // VFMADD132SDZr 2182106542U, // VFMADD132SDZr_Int 49302958U, // VFMADD132SDZr_Intk 2196786606U, // VFMADD132SDZr_Intkz 2182106542U, // VFMADD132SDZrb 2182106542U, // VFMADD132SDZrb_Int 49302958U, // VFMADD132SDZrb_Intk 2196786606U, // VFMADD132SDZrb_Intkz 2182106542U, // VFMADD132SDm 2182106542U, // VFMADD132SDm_Int 2182106542U, // VFMADD132SDr 2182106542U, // VFMADD132SDr_Int 2182111243U, // VFMADD132SSZm 2182111243U, // VFMADD132SSZm_Int 49307659U, // VFMADD132SSZm_Intk 2196791307U, // VFMADD132SSZm_Intkz 2182111243U, // VFMADD132SSZr 2182111243U, // VFMADD132SSZr_Int 49307659U, // VFMADD132SSZr_Intk 2196791307U, // VFMADD132SSZr_Intkz 2182111243U, // VFMADD132SSZrb 2182111243U, // VFMADD132SSZrb_Int 49307659U, // VFMADD132SSZrb_Intk 2196791307U, // VFMADD132SSZrb_Intkz 2182111243U, // VFMADD132SSm 2182111243U, // VFMADD132SSm_Int 2182111243U, // VFMADD132SSr 2182111243U, // VFMADD132SSr_Int 2182105666U, // VFMADD213PDYm 2182105666U, // VFMADD213PDYr 2182105666U, // VFMADD213PDZ128m 2182105666U, // VFMADD213PDZ128mb 49302082U, // VFMADD213PDZ128mbk 2196785730U, // VFMADD213PDZ128mbkz 49302082U, // VFMADD213PDZ128mk 2196785730U, // VFMADD213PDZ128mkz 2182105666U, // VFMADD213PDZ128r 49302082U, // VFMADD213PDZ128rk 2196785730U, // VFMADD213PDZ128rkz 2182105666U, // VFMADD213PDZ256m 2182105666U, // VFMADD213PDZ256mb 49302082U, // VFMADD213PDZ256mbk 2196785730U, // VFMADD213PDZ256mbkz 49302082U, // VFMADD213PDZ256mk 2196785730U, // VFMADD213PDZ256mkz 2182105666U, // VFMADD213PDZ256r 49302082U, // VFMADD213PDZ256rk 2196785730U, // VFMADD213PDZ256rkz 2182105666U, // VFMADD213PDZm 2182105666U, // VFMADD213PDZmb 49302082U, // VFMADD213PDZmbk 2196785730U, // VFMADD213PDZmbkz 49302082U, // VFMADD213PDZmk 2196785730U, // VFMADD213PDZmkz 2182105666U, // VFMADD213PDZr 2182105666U, // VFMADD213PDZrb 49302082U, // VFMADD213PDZrbk 2196785730U, // VFMADD213PDZrbkz 49302082U, // VFMADD213PDZrk 2196785730U, // VFMADD213PDZrkz 2182105666U, // VFMADD213PDm 2182105666U, // VFMADD213PDr 2182110450U, // VFMADD213PSYm 2182110450U, // VFMADD213PSYr 2182110450U, // VFMADD213PSZ128m 2182110450U, // VFMADD213PSZ128mb 49306866U, // VFMADD213PSZ128mbk 2196790514U, // VFMADD213PSZ128mbkz 49306866U, // VFMADD213PSZ128mk 2196790514U, // VFMADD213PSZ128mkz 2182110450U, // VFMADD213PSZ128r 49306866U, // VFMADD213PSZ128rk 2196790514U, // VFMADD213PSZ128rkz 2182110450U, // VFMADD213PSZ256m 2182110450U, // VFMADD213PSZ256mb 49306866U, // VFMADD213PSZ256mbk 2196790514U, // VFMADD213PSZ256mbkz 49306866U, // VFMADD213PSZ256mk 2196790514U, // VFMADD213PSZ256mkz 2182110450U, // VFMADD213PSZ256r 49306866U, // VFMADD213PSZ256rk 2196790514U, // VFMADD213PSZ256rkz 2182110450U, // VFMADD213PSZm 2182110450U, // VFMADD213PSZmb 49306866U, // VFMADD213PSZmbk 2196790514U, // VFMADD213PSZmbkz 49306866U, // VFMADD213PSZmk 2196790514U, // VFMADD213PSZmkz 2182110450U, // VFMADD213PSZr 2182110450U, // VFMADD213PSZrb 49306866U, // VFMADD213PSZrbk 2196790514U, // VFMADD213PSZrbkz 49306866U, // VFMADD213PSZrk 2196790514U, // VFMADD213PSZrkz 2182110450U, // VFMADD213PSm 2182110450U, // VFMADD213PSr 2182106630U, // VFMADD213SDZm 2182106630U, // VFMADD213SDZm_Int 49303046U, // VFMADD213SDZm_Intk 2196786694U, // VFMADD213SDZm_Intkz 2182106630U, // VFMADD213SDZr 2182106630U, // VFMADD213SDZr_Int 49303046U, // VFMADD213SDZr_Intk 2196786694U, // VFMADD213SDZr_Intkz 2182106630U, // VFMADD213SDZrb 2182106630U, // VFMADD213SDZrb_Int 49303046U, // VFMADD213SDZrb_Intk 2196786694U, // VFMADD213SDZrb_Intkz 2182106630U, // VFMADD213SDm 2182106630U, // VFMADD213SDm_Int 2182106630U, // VFMADD213SDr 2182106630U, // VFMADD213SDr_Int 2182111331U, // VFMADD213SSZm 2182111331U, // VFMADD213SSZm_Int 49307747U, // VFMADD213SSZm_Intk 2196791395U, // VFMADD213SSZm_Intkz 2182111331U, // VFMADD213SSZr 2182111331U, // VFMADD213SSZr_Int 49307747U, // VFMADD213SSZr_Intk 2196791395U, // VFMADD213SSZr_Intkz 2182111331U, // VFMADD213SSZrb 2182111331U, // VFMADD213SSZrb_Int 49307747U, // VFMADD213SSZrb_Intk 2196791395U, // VFMADD213SSZrb_Intkz 2182111331U, // VFMADD213SSm 2182111331U, // VFMADD213SSm_Int 2182111331U, // VFMADD213SSr 2182111331U, // VFMADD213SSr_Int 2182105384U, // VFMADD231PDYm 2182105384U, // VFMADD231PDYr 2182105384U, // VFMADD231PDZ128m 2182105384U, // VFMADD231PDZ128mb 49301800U, // VFMADD231PDZ128mbk 2196785448U, // VFMADD231PDZ128mbkz 49301800U, // VFMADD231PDZ128mk 2196785448U, // VFMADD231PDZ128mkz 2182105384U, // VFMADD231PDZ128r 49301800U, // VFMADD231PDZ128rk 2196785448U, // VFMADD231PDZ128rkz 2182105384U, // VFMADD231PDZ256m 2182105384U, // VFMADD231PDZ256mb 49301800U, // VFMADD231PDZ256mbk 2196785448U, // VFMADD231PDZ256mbkz 49301800U, // VFMADD231PDZ256mk 2196785448U, // VFMADD231PDZ256mkz 2182105384U, // VFMADD231PDZ256r 49301800U, // VFMADD231PDZ256rk 2196785448U, // VFMADD231PDZ256rkz 2182105384U, // VFMADD231PDZm 2182105384U, // VFMADD231PDZmb 49301800U, // VFMADD231PDZmbk 2196785448U, // VFMADD231PDZmbkz 49301800U, // VFMADD231PDZmk 2196785448U, // VFMADD231PDZmkz 2182105384U, // VFMADD231PDZr 2182105384U, // VFMADD231PDZrb 49301800U, // VFMADD231PDZrbk 2196785448U, // VFMADD231PDZrbkz 49301800U, // VFMADD231PDZrk 2196785448U, // VFMADD231PDZrkz 2182105384U, // VFMADD231PDm 2182105384U, // VFMADD231PDr 2182110157U, // VFMADD231PSYm 2182110157U, // VFMADD231PSYr 2182110157U, // VFMADD231PSZ128m 2182110157U, // VFMADD231PSZ128mb 49306573U, // VFMADD231PSZ128mbk 2196790221U, // VFMADD231PSZ128mbkz 49306573U, // VFMADD231PSZ128mk 2196790221U, // VFMADD231PSZ128mkz 2182110157U, // VFMADD231PSZ128r 49306573U, // VFMADD231PSZ128rk 2196790221U, // VFMADD231PSZ128rkz 2182110157U, // VFMADD231PSZ256m 2182110157U, // VFMADD231PSZ256mb 49306573U, // VFMADD231PSZ256mbk 2196790221U, // VFMADD231PSZ256mbkz 49306573U, // VFMADD231PSZ256mk 2196790221U, // VFMADD231PSZ256mkz 2182110157U, // VFMADD231PSZ256r 49306573U, // VFMADD231PSZ256rk 2196790221U, // VFMADD231PSZ256rkz 2182110157U, // VFMADD231PSZm 2182110157U, // VFMADD231PSZmb 49306573U, // VFMADD231PSZmbk 2196790221U, // VFMADD231PSZmbkz 49306573U, // VFMADD231PSZmk 2196790221U, // VFMADD231PSZmkz 2182110157U, // VFMADD231PSZr 2182110157U, // VFMADD231PSZrb 49306573U, // VFMADD231PSZrbk 2196790221U, // VFMADD231PSZrbkz 49306573U, // VFMADD231PSZrk 2196790221U, // VFMADD231PSZrkz 2182110157U, // VFMADD231PSm 2182110157U, // VFMADD231PSr 2182106488U, // VFMADD231SDZm 2182106488U, // VFMADD231SDZm_Int 49302904U, // VFMADD231SDZm_Intk 2196786552U, // VFMADD231SDZm_Intkz 2182106488U, // VFMADD231SDZr 2182106488U, // VFMADD231SDZr_Int 49302904U, // VFMADD231SDZr_Intk 2196786552U, // VFMADD231SDZr_Intkz 2182106488U, // VFMADD231SDZrb 2182106488U, // VFMADD231SDZrb_Int 49302904U, // VFMADD231SDZrb_Intk 2196786552U, // VFMADD231SDZrb_Intkz 2182106488U, // VFMADD231SDm 2182106488U, // VFMADD231SDm_Int 2182106488U, // VFMADD231SDr 2182106488U, // VFMADD231SDr_Int 2182111189U, // VFMADD231SSZm 2182111189U, // VFMADD231SSZm_Int 49307605U, // VFMADD231SSZm_Intk 2196791253U, // VFMADD231SSZm_Intkz 2182111189U, // VFMADD231SSZr 2182111189U, // VFMADD231SSZr_Int 49307605U, // VFMADD231SSZr_Intk 2196791253U, // VFMADD231SSZr_Intkz 2182111189U, // VFMADD231SSZrb 2182111189U, // VFMADD231SSZrb_Int 49307605U, // VFMADD231SSZrb_Intk 2196791253U, // VFMADD231SSZrb_Intkz 2182111189U, // VFMADD231SSm 2182111189U, // VFMADD231SSm_Int 2182111189U, // VFMADD231SSr 2182111189U, // VFMADD231SSr_Int 2517650158U, // VFMADDPD4Ymr 2517650158U, // VFMADDPD4Yrm 2517650158U, // VFMADDPD4Yrr 2517650158U, // VFMADDPD4Yrr_REV 2517650158U, // VFMADDPD4mr 2517650158U, // VFMADDPD4rm 2517650158U, // VFMADDPD4rr 2517650158U, // VFMADDPD4rr_REV 2517654945U, // VFMADDPS4Ymr 2517654945U, // VFMADDPS4Yrm 2517654945U, // VFMADDPS4Yrr 2517654945U, // VFMADDPS4Yrr_REV 2517654945U, // VFMADDPS4mr 2517654945U, // VFMADDPS4rm 2517654945U, // VFMADDPS4rr 2517654945U, // VFMADDPS4rr_REV 2517651058U, // VFMADDSD4mr 2517651058U, // VFMADDSD4mr_Int 2517651058U, // VFMADDSD4rm 2517651058U, // VFMADDSD4rm_Int 2517651058U, // VFMADDSD4rr 2517651058U, // VFMADDSD4rr_Int 2517651058U, // VFMADDSD4rr_Int_REV 2517651058U, // VFMADDSD4rr_REV 2517655762U, // VFMADDSS4mr 2517655762U, // VFMADDSS4mr_Int 2517655762U, // VFMADDSS4rm 2517655762U, // VFMADDSS4rm_Int 2517655762U, // VFMADDSS4rr 2517655762U, // VFMADDSS4rr_Int 2517655762U, // VFMADDSS4rr_Int_REV 2517655762U, // VFMADDSS4rr_REV 2182105411U, // VFMADDSUB132PDYm 2182105411U, // VFMADDSUB132PDYr 2182105411U, // VFMADDSUB132PDZ128m 2182105411U, // VFMADDSUB132PDZ128mb 49301827U, // VFMADDSUB132PDZ128mbk 2196785475U, // VFMADDSUB132PDZ128mbkz 49301827U, // VFMADDSUB132PDZ128mk 2196785475U, // VFMADDSUB132PDZ128mkz 2182105411U, // VFMADDSUB132PDZ128r 49301827U, // VFMADDSUB132PDZ128rk 2196785475U, // VFMADDSUB132PDZ128rkz 2182105411U, // VFMADDSUB132PDZ256m 2182105411U, // VFMADDSUB132PDZ256mb 49301827U, // VFMADDSUB132PDZ256mbk 2196785475U, // VFMADDSUB132PDZ256mbkz 49301827U, // VFMADDSUB132PDZ256mk 2196785475U, // VFMADDSUB132PDZ256mkz 2182105411U, // VFMADDSUB132PDZ256r 49301827U, // VFMADDSUB132PDZ256rk 2196785475U, // VFMADDSUB132PDZ256rkz 2182105411U, // VFMADDSUB132PDZm 2182105411U, // VFMADDSUB132PDZmb 49301827U, // VFMADDSUB132PDZmbk 2196785475U, // VFMADDSUB132PDZmbkz 49301827U, // VFMADDSUB132PDZmk 2196785475U, // VFMADDSUB132PDZmkz 2182105411U, // VFMADDSUB132PDZr 2182105411U, // VFMADDSUB132PDZrb 49301827U, // VFMADDSUB132PDZrbk 2196785475U, // VFMADDSUB132PDZrbkz 49301827U, // VFMADDSUB132PDZrk 2196785475U, // VFMADDSUB132PDZrkz 2182105411U, // VFMADDSUB132PDm 2182105411U, // VFMADDSUB132PDr 2182110184U, // VFMADDSUB132PSYm 2182110184U, // VFMADDSUB132PSYr 2182110184U, // VFMADDSUB132PSZ128m 2182110184U, // VFMADDSUB132PSZ128mb 49306600U, // VFMADDSUB132PSZ128mbk 2196790248U, // VFMADDSUB132PSZ128mbkz 49306600U, // VFMADDSUB132PSZ128mk 2196790248U, // VFMADDSUB132PSZ128mkz 2182110184U, // VFMADDSUB132PSZ128r 49306600U, // VFMADDSUB132PSZ128rk 2196790248U, // VFMADDSUB132PSZ128rkz 2182110184U, // VFMADDSUB132PSZ256m 2182110184U, // VFMADDSUB132PSZ256mb 49306600U, // VFMADDSUB132PSZ256mbk 2196790248U, // VFMADDSUB132PSZ256mbkz 49306600U, // VFMADDSUB132PSZ256mk 2196790248U, // VFMADDSUB132PSZ256mkz 2182110184U, // VFMADDSUB132PSZ256r 49306600U, // VFMADDSUB132PSZ256rk 2196790248U, // VFMADDSUB132PSZ256rkz 2182110184U, // VFMADDSUB132PSZm 2182110184U, // VFMADDSUB132PSZmb 49306600U, // VFMADDSUB132PSZmbk 2196790248U, // VFMADDSUB132PSZmbkz 49306600U, // VFMADDSUB132PSZmk 2196790248U, // VFMADDSUB132PSZmkz 2182110184U, // VFMADDSUB132PSZr 2182110184U, // VFMADDSUB132PSZrb 49306600U, // VFMADDSUB132PSZrbk 2196790248U, // VFMADDSUB132PSZrbkz 49306600U, // VFMADDSUB132PSZrk 2196790248U, // VFMADDSUB132PSZrkz 2182110184U, // VFMADDSUB132PSm 2182110184U, // VFMADDSUB132PSr 2182105607U, // VFMADDSUB213PDYm 2182105607U, // VFMADDSUB213PDYr 2182105607U, // VFMADDSUB213PDZ128m 2182105607U, // VFMADDSUB213PDZ128mb 49302023U, // VFMADDSUB213PDZ128mbk 2196785671U, // VFMADDSUB213PDZ128mbkz 49302023U, // VFMADDSUB213PDZ128mk 2196785671U, // VFMADDSUB213PDZ128mkz 2182105607U, // VFMADDSUB213PDZ128r 49302023U, // VFMADDSUB213PDZ128rk 2196785671U, // VFMADDSUB213PDZ128rkz 2182105607U, // VFMADDSUB213PDZ256m 2182105607U, // VFMADDSUB213PDZ256mb 49302023U, // VFMADDSUB213PDZ256mbk 2196785671U, // VFMADDSUB213PDZ256mbkz 49302023U, // VFMADDSUB213PDZ256mk 2196785671U, // VFMADDSUB213PDZ256mkz 2182105607U, // VFMADDSUB213PDZ256r 49302023U, // VFMADDSUB213PDZ256rk 2196785671U, // VFMADDSUB213PDZ256rkz 2182105607U, // VFMADDSUB213PDZm 2182105607U, // VFMADDSUB213PDZmb 49302023U, // VFMADDSUB213PDZmbk 2196785671U, // VFMADDSUB213PDZmbkz 49302023U, // VFMADDSUB213PDZmk 2196785671U, // VFMADDSUB213PDZmkz 2182105607U, // VFMADDSUB213PDZr 2182105607U, // VFMADDSUB213PDZrb 49302023U, // VFMADDSUB213PDZrbk 2196785671U, // VFMADDSUB213PDZrbkz 49302023U, // VFMADDSUB213PDZrk 2196785671U, // VFMADDSUB213PDZrkz 2182105607U, // VFMADDSUB213PDm 2182105607U, // VFMADDSUB213PDr 2182110391U, // VFMADDSUB213PSYm 2182110391U, // VFMADDSUB213PSYr 2182110391U, // VFMADDSUB213PSZ128m 2182110391U, // VFMADDSUB213PSZ128mb 49306807U, // VFMADDSUB213PSZ128mbk 2196790455U, // VFMADDSUB213PSZ128mbkz 49306807U, // VFMADDSUB213PSZ128mk 2196790455U, // VFMADDSUB213PSZ128mkz 2182110391U, // VFMADDSUB213PSZ128r 49306807U, // VFMADDSUB213PSZ128rk 2196790455U, // VFMADDSUB213PSZ128rkz 2182110391U, // VFMADDSUB213PSZ256m 2182110391U, // VFMADDSUB213PSZ256mb 49306807U, // VFMADDSUB213PSZ256mbk 2196790455U, // VFMADDSUB213PSZ256mbkz 49306807U, // VFMADDSUB213PSZ256mk 2196790455U, // VFMADDSUB213PSZ256mkz 2182110391U, // VFMADDSUB213PSZ256r 49306807U, // VFMADDSUB213PSZ256rk 2196790455U, // VFMADDSUB213PSZ256rkz 2182110391U, // VFMADDSUB213PSZm 2182110391U, // VFMADDSUB213PSZmb 49306807U, // VFMADDSUB213PSZmbk 2196790455U, // VFMADDSUB213PSZmbkz 49306807U, // VFMADDSUB213PSZmk 2196790455U, // VFMADDSUB213PSZmkz 2182110391U, // VFMADDSUB213PSZr 2182110391U, // VFMADDSUB213PSZrb 49306807U, // VFMADDSUB213PSZrbk 2196790455U, // VFMADDSUB213PSZrbkz 49306807U, // VFMADDSUB213PSZrk 2196790455U, // VFMADDSUB213PSZrkz 2182110391U, // VFMADDSUB213PSm 2182110391U, // VFMADDSUB213PSr 2182105325U, // VFMADDSUB231PDYm 2182105325U, // VFMADDSUB231PDYr 2182105325U, // VFMADDSUB231PDZ128m 2182105325U, // VFMADDSUB231PDZ128mb 49301741U, // VFMADDSUB231PDZ128mbk 2196785389U, // VFMADDSUB231PDZ128mbkz 49301741U, // VFMADDSUB231PDZ128mk 2196785389U, // VFMADDSUB231PDZ128mkz 2182105325U, // VFMADDSUB231PDZ128r 49301741U, // VFMADDSUB231PDZ128rk 2196785389U, // VFMADDSUB231PDZ128rkz 2182105325U, // VFMADDSUB231PDZ256m 2182105325U, // VFMADDSUB231PDZ256mb 49301741U, // VFMADDSUB231PDZ256mbk 2196785389U, // VFMADDSUB231PDZ256mbkz 49301741U, // VFMADDSUB231PDZ256mk 2196785389U, // VFMADDSUB231PDZ256mkz 2182105325U, // VFMADDSUB231PDZ256r 49301741U, // VFMADDSUB231PDZ256rk 2196785389U, // VFMADDSUB231PDZ256rkz 2182105325U, // VFMADDSUB231PDZm 2182105325U, // VFMADDSUB231PDZmb 49301741U, // VFMADDSUB231PDZmbk 2196785389U, // VFMADDSUB231PDZmbkz 49301741U, // VFMADDSUB231PDZmk 2196785389U, // VFMADDSUB231PDZmkz 2182105325U, // VFMADDSUB231PDZr 2182105325U, // VFMADDSUB231PDZrb 49301741U, // VFMADDSUB231PDZrbk 2196785389U, // VFMADDSUB231PDZrbkz 49301741U, // VFMADDSUB231PDZrk 2196785389U, // VFMADDSUB231PDZrkz 2182105325U, // VFMADDSUB231PDm 2182105325U, // VFMADDSUB231PDr 2182110098U, // VFMADDSUB231PSYm 2182110098U, // VFMADDSUB231PSYr 2182110098U, // VFMADDSUB231PSZ128m 2182110098U, // VFMADDSUB231PSZ128mb 49306514U, // VFMADDSUB231PSZ128mbk 2196790162U, // VFMADDSUB231PSZ128mbkz 49306514U, // VFMADDSUB231PSZ128mk 2196790162U, // VFMADDSUB231PSZ128mkz 2182110098U, // VFMADDSUB231PSZ128r 49306514U, // VFMADDSUB231PSZ128rk 2196790162U, // VFMADDSUB231PSZ128rkz 2182110098U, // VFMADDSUB231PSZ256m 2182110098U, // VFMADDSUB231PSZ256mb 49306514U, // VFMADDSUB231PSZ256mbk 2196790162U, // VFMADDSUB231PSZ256mbkz 49306514U, // VFMADDSUB231PSZ256mk 2196790162U, // VFMADDSUB231PSZ256mkz 2182110098U, // VFMADDSUB231PSZ256r 49306514U, // VFMADDSUB231PSZ256rk 2196790162U, // VFMADDSUB231PSZ256rkz 2182110098U, // VFMADDSUB231PSZm 2182110098U, // VFMADDSUB231PSZmb 49306514U, // VFMADDSUB231PSZmbk 2196790162U, // VFMADDSUB231PSZmbkz 49306514U, // VFMADDSUB231PSZmk 2196790162U, // VFMADDSUB231PSZmkz 2182110098U, // VFMADDSUB231PSZr 2182110098U, // VFMADDSUB231PSZrb 49306514U, // VFMADDSUB231PSZrbk 2196790162U, // VFMADDSUB231PSZrbkz 49306514U, // VFMADDSUB231PSZrk 2196790162U, // VFMADDSUB231PSZrkz 2182110098U, // VFMADDSUB231PSm 2182110098U, // VFMADDSUB231PSr 2517650074U, // VFMADDSUBPD4Ymr 2517650074U, // VFMADDSUBPD4Yrm 2517650074U, // VFMADDSUBPD4Yrr 2517650074U, // VFMADDSUBPD4Yrr_REV 2517650074U, // VFMADDSUBPD4mr 2517650074U, // VFMADDSUBPD4rm 2517650074U, // VFMADDSUBPD4rr 2517650074U, // VFMADDSUBPD4rr_REV 2517654850U, // VFMADDSUBPS4Ymr 2517654850U, // VFMADDSUBPS4Yrm 2517654850U, // VFMADDSUBPS4Yrr 2517654850U, // VFMADDSUBPS4Yrr_REV 2517654850U, // VFMADDSUBPS4mr 2517654850U, // VFMADDSUBPS4rm 2517654850U, // VFMADDSUBPS4rr 2517654850U, // VFMADDSUBPS4rr_REV 2182105427U, // VFMSUB132PDYm 2182105427U, // VFMSUB132PDYr 2182105427U, // VFMSUB132PDZ128m 2182105427U, // VFMSUB132PDZ128mb 49301843U, // VFMSUB132PDZ128mbk 2196785491U, // VFMSUB132PDZ128mbkz 49301843U, // VFMSUB132PDZ128mk 2196785491U, // VFMSUB132PDZ128mkz 2182105427U, // VFMSUB132PDZ128r 49301843U, // VFMSUB132PDZ128rk 2196785491U, // VFMSUB132PDZ128rkz 2182105427U, // VFMSUB132PDZ256m 2182105427U, // VFMSUB132PDZ256mb 49301843U, // VFMSUB132PDZ256mbk 2196785491U, // VFMSUB132PDZ256mbkz 49301843U, // VFMSUB132PDZ256mk 2196785491U, // VFMSUB132PDZ256mkz 2182105427U, // VFMSUB132PDZ256r 49301843U, // VFMSUB132PDZ256rk 2196785491U, // VFMSUB132PDZ256rkz 2182105427U, // VFMSUB132PDZm 2182105427U, // VFMSUB132PDZmb 49301843U, // VFMSUB132PDZmbk 2196785491U, // VFMSUB132PDZmbkz 49301843U, // VFMSUB132PDZmk 2196785491U, // VFMSUB132PDZmkz 2182105427U, // VFMSUB132PDZr 2182105427U, // VFMSUB132PDZrb 49301843U, // VFMSUB132PDZrbk 2196785491U, // VFMSUB132PDZrbkz 49301843U, // VFMSUB132PDZrk 2196785491U, // VFMSUB132PDZrkz 2182105427U, // VFMSUB132PDm 2182105427U, // VFMSUB132PDr 2182110200U, // VFMSUB132PSYm 2182110200U, // VFMSUB132PSYr 2182110200U, // VFMSUB132PSZ128m 2182110200U, // VFMSUB132PSZ128mb 49306616U, // VFMSUB132PSZ128mbk 2196790264U, // VFMSUB132PSZ128mbkz 49306616U, // VFMSUB132PSZ128mk 2196790264U, // VFMSUB132PSZ128mkz 2182110200U, // VFMSUB132PSZ128r 49306616U, // VFMSUB132PSZ128rk 2196790264U, // VFMSUB132PSZ128rkz 2182110200U, // VFMSUB132PSZ256m 2182110200U, // VFMSUB132PSZ256mb 49306616U, // VFMSUB132PSZ256mbk 2196790264U, // VFMSUB132PSZ256mbkz 49306616U, // VFMSUB132PSZ256mk 2196790264U, // VFMSUB132PSZ256mkz 2182110200U, // VFMSUB132PSZ256r 49306616U, // VFMSUB132PSZ256rk 2196790264U, // VFMSUB132PSZ256rkz 2182110200U, // VFMSUB132PSZm 2182110200U, // VFMSUB132PSZmb 49306616U, // VFMSUB132PSZmbk 2196790264U, // VFMSUB132PSZmbkz 49306616U, // VFMSUB132PSZmk 2196790264U, // VFMSUB132PSZmkz 2182110200U, // VFMSUB132PSZr 2182110200U, // VFMSUB132PSZrb 49306616U, // VFMSUB132PSZrbk 2196790264U, // VFMSUB132PSZrbkz 49306616U, // VFMSUB132PSZrk 2196790264U, // VFMSUB132PSZrkz 2182110200U, // VFMSUB132PSm 2182110200U, // VFMSUB132PSr 2182106515U, // VFMSUB132SDZm 2182106515U, // VFMSUB132SDZm_Int 49302931U, // VFMSUB132SDZm_Intk 2196786579U, // VFMSUB132SDZm_Intkz 2182106515U, // VFMSUB132SDZr 2182106515U, // VFMSUB132SDZr_Int 49302931U, // VFMSUB132SDZr_Intk 2196786579U, // VFMSUB132SDZr_Intkz 2182106515U, // VFMSUB132SDZrb 2182106515U, // VFMSUB132SDZrb_Int 49302931U, // VFMSUB132SDZrb_Intk 2196786579U, // VFMSUB132SDZrb_Intkz 2182106515U, // VFMSUB132SDm 2182106515U, // VFMSUB132SDm_Int 2182106515U, // VFMSUB132SDr 2182106515U, // VFMSUB132SDr_Int 2182111216U, // VFMSUB132SSZm 2182111216U, // VFMSUB132SSZm_Int 49307632U, // VFMSUB132SSZm_Intk 2196791280U, // VFMSUB132SSZm_Intkz 2182111216U, // VFMSUB132SSZr 2182111216U, // VFMSUB132SSZr_Int 49307632U, // VFMSUB132SSZr_Intk 2196791280U, // VFMSUB132SSZr_Intkz 2182111216U, // VFMSUB132SSZrb 2182111216U, // VFMSUB132SSZrb_Int 49307632U, // VFMSUB132SSZrb_Intk 2196791280U, // VFMSUB132SSZrb_Intkz 2182111216U, // VFMSUB132SSm 2182111216U, // VFMSUB132SSm_Int 2182111216U, // VFMSUB132SSr 2182111216U, // VFMSUB132SSr_Int 2182105623U, // VFMSUB213PDYm 2182105623U, // VFMSUB213PDYr 2182105623U, // VFMSUB213PDZ128m 2182105623U, // VFMSUB213PDZ128mb 49302039U, // VFMSUB213PDZ128mbk 2196785687U, // VFMSUB213PDZ128mbkz 49302039U, // VFMSUB213PDZ128mk 2196785687U, // VFMSUB213PDZ128mkz 2182105623U, // VFMSUB213PDZ128r 49302039U, // VFMSUB213PDZ128rk 2196785687U, // VFMSUB213PDZ128rkz 2182105623U, // VFMSUB213PDZ256m 2182105623U, // VFMSUB213PDZ256mb 49302039U, // VFMSUB213PDZ256mbk 2196785687U, // VFMSUB213PDZ256mbkz 49302039U, // VFMSUB213PDZ256mk 2196785687U, // VFMSUB213PDZ256mkz 2182105623U, // VFMSUB213PDZ256r 49302039U, // VFMSUB213PDZ256rk 2196785687U, // VFMSUB213PDZ256rkz 2182105623U, // VFMSUB213PDZm 2182105623U, // VFMSUB213PDZmb 49302039U, // VFMSUB213PDZmbk 2196785687U, // VFMSUB213PDZmbkz 49302039U, // VFMSUB213PDZmk 2196785687U, // VFMSUB213PDZmkz 2182105623U, // VFMSUB213PDZr 2182105623U, // VFMSUB213PDZrb 49302039U, // VFMSUB213PDZrbk 2196785687U, // VFMSUB213PDZrbkz 49302039U, // VFMSUB213PDZrk 2196785687U, // VFMSUB213PDZrkz 2182105623U, // VFMSUB213PDm 2182105623U, // VFMSUB213PDr 2182110407U, // VFMSUB213PSYm 2182110407U, // VFMSUB213PSYr 2182110407U, // VFMSUB213PSZ128m 2182110407U, // VFMSUB213PSZ128mb 49306823U, // VFMSUB213PSZ128mbk 2196790471U, // VFMSUB213PSZ128mbkz 49306823U, // VFMSUB213PSZ128mk 2196790471U, // VFMSUB213PSZ128mkz 2182110407U, // VFMSUB213PSZ128r 49306823U, // VFMSUB213PSZ128rk 2196790471U, // VFMSUB213PSZ128rkz 2182110407U, // VFMSUB213PSZ256m 2182110407U, // VFMSUB213PSZ256mb 49306823U, // VFMSUB213PSZ256mbk 2196790471U, // VFMSUB213PSZ256mbkz 49306823U, // VFMSUB213PSZ256mk 2196790471U, // VFMSUB213PSZ256mkz 2182110407U, // VFMSUB213PSZ256r 49306823U, // VFMSUB213PSZ256rk 2196790471U, // VFMSUB213PSZ256rkz 2182110407U, // VFMSUB213PSZm 2182110407U, // VFMSUB213PSZmb 49306823U, // VFMSUB213PSZmbk 2196790471U, // VFMSUB213PSZmbkz 49306823U, // VFMSUB213PSZmk 2196790471U, // VFMSUB213PSZmkz 2182110407U, // VFMSUB213PSZr 2182110407U, // VFMSUB213PSZrb 49306823U, // VFMSUB213PSZrbk 2196790471U, // VFMSUB213PSZrbkz 49306823U, // VFMSUB213PSZrk 2196790471U, // VFMSUB213PSZrkz 2182110407U, // VFMSUB213PSm 2182110407U, // VFMSUB213PSr 2182106603U, // VFMSUB213SDZm 2182106603U, // VFMSUB213SDZm_Int 49303019U, // VFMSUB213SDZm_Intk 2196786667U, // VFMSUB213SDZm_Intkz 2182106603U, // VFMSUB213SDZr 2182106603U, // VFMSUB213SDZr_Int 49303019U, // VFMSUB213SDZr_Intk 2196786667U, // VFMSUB213SDZr_Intkz 2182106603U, // VFMSUB213SDZrb 2182106603U, // VFMSUB213SDZrb_Int 49303019U, // VFMSUB213SDZrb_Intk 2196786667U, // VFMSUB213SDZrb_Intkz 2182106603U, // VFMSUB213SDm 2182106603U, // VFMSUB213SDm_Int 2182106603U, // VFMSUB213SDr 2182106603U, // VFMSUB213SDr_Int 2182111304U, // VFMSUB213SSZm 2182111304U, // VFMSUB213SSZm_Int 49307720U, // VFMSUB213SSZm_Intk 2196791368U, // VFMSUB213SSZm_Intkz 2182111304U, // VFMSUB213SSZr 2182111304U, // VFMSUB213SSZr_Int 49307720U, // VFMSUB213SSZr_Intk 2196791368U, // VFMSUB213SSZr_Intkz 2182111304U, // VFMSUB213SSZrb 2182111304U, // VFMSUB213SSZrb_Int 49307720U, // VFMSUB213SSZrb_Intk 2196791368U, // VFMSUB213SSZrb_Intkz 2182111304U, // VFMSUB213SSm 2182111304U, // VFMSUB213SSm_Int 2182111304U, // VFMSUB213SSr 2182111304U, // VFMSUB213SSr_Int 2182105341U, // VFMSUB231PDYm 2182105341U, // VFMSUB231PDYr 2182105341U, // VFMSUB231PDZ128m 2182105341U, // VFMSUB231PDZ128mb 49301757U, // VFMSUB231PDZ128mbk 2196785405U, // VFMSUB231PDZ128mbkz 49301757U, // VFMSUB231PDZ128mk 2196785405U, // VFMSUB231PDZ128mkz 2182105341U, // VFMSUB231PDZ128r 49301757U, // VFMSUB231PDZ128rk 2196785405U, // VFMSUB231PDZ128rkz 2182105341U, // VFMSUB231PDZ256m 2182105341U, // VFMSUB231PDZ256mb 49301757U, // VFMSUB231PDZ256mbk 2196785405U, // VFMSUB231PDZ256mbkz 49301757U, // VFMSUB231PDZ256mk 2196785405U, // VFMSUB231PDZ256mkz 2182105341U, // VFMSUB231PDZ256r 49301757U, // VFMSUB231PDZ256rk 2196785405U, // VFMSUB231PDZ256rkz 2182105341U, // VFMSUB231PDZm 2182105341U, // VFMSUB231PDZmb 49301757U, // VFMSUB231PDZmbk 2196785405U, // VFMSUB231PDZmbkz 49301757U, // VFMSUB231PDZmk 2196785405U, // VFMSUB231PDZmkz 2182105341U, // VFMSUB231PDZr 2182105341U, // VFMSUB231PDZrb 49301757U, // VFMSUB231PDZrbk 2196785405U, // VFMSUB231PDZrbkz 49301757U, // VFMSUB231PDZrk 2196785405U, // VFMSUB231PDZrkz 2182105341U, // VFMSUB231PDm 2182105341U, // VFMSUB231PDr 2182110114U, // VFMSUB231PSYm 2182110114U, // VFMSUB231PSYr 2182110114U, // VFMSUB231PSZ128m 2182110114U, // VFMSUB231PSZ128mb 49306530U, // VFMSUB231PSZ128mbk 2196790178U, // VFMSUB231PSZ128mbkz 49306530U, // VFMSUB231PSZ128mk 2196790178U, // VFMSUB231PSZ128mkz 2182110114U, // VFMSUB231PSZ128r 49306530U, // VFMSUB231PSZ128rk 2196790178U, // VFMSUB231PSZ128rkz 2182110114U, // VFMSUB231PSZ256m 2182110114U, // VFMSUB231PSZ256mb 49306530U, // VFMSUB231PSZ256mbk 2196790178U, // VFMSUB231PSZ256mbkz 49306530U, // VFMSUB231PSZ256mk 2196790178U, // VFMSUB231PSZ256mkz 2182110114U, // VFMSUB231PSZ256r 49306530U, // VFMSUB231PSZ256rk 2196790178U, // VFMSUB231PSZ256rkz 2182110114U, // VFMSUB231PSZm 2182110114U, // VFMSUB231PSZmb 49306530U, // VFMSUB231PSZmbk 2196790178U, // VFMSUB231PSZmbkz 49306530U, // VFMSUB231PSZmk 2196790178U, // VFMSUB231PSZmkz 2182110114U, // VFMSUB231PSZr 2182110114U, // VFMSUB231PSZrb 49306530U, // VFMSUB231PSZrbk 2196790178U, // VFMSUB231PSZrbkz 49306530U, // VFMSUB231PSZrk 2196790178U, // VFMSUB231PSZrkz 2182110114U, // VFMSUB231PSm 2182110114U, // VFMSUB231PSr 2182106461U, // VFMSUB231SDZm 2182106461U, // VFMSUB231SDZm_Int 49302877U, // VFMSUB231SDZm_Intk 2196786525U, // VFMSUB231SDZm_Intkz 2182106461U, // VFMSUB231SDZr 2182106461U, // VFMSUB231SDZr_Int 49302877U, // VFMSUB231SDZr_Intk 2196786525U, // VFMSUB231SDZr_Intkz 2182106461U, // VFMSUB231SDZrb 2182106461U, // VFMSUB231SDZrb_Int 49302877U, // VFMSUB231SDZrb_Intk 2196786525U, // VFMSUB231SDZrb_Intkz 2182106461U, // VFMSUB231SDm 2182106461U, // VFMSUB231SDm_Int 2182106461U, // VFMSUB231SDr 2182106461U, // VFMSUB231SDr_Int 2182111162U, // VFMSUB231SSZm 2182111162U, // VFMSUB231SSZm_Int 49307578U, // VFMSUB231SSZm_Intk 2196791226U, // VFMSUB231SSZm_Intkz 2182111162U, // VFMSUB231SSZr 2182111162U, // VFMSUB231SSZr_Int 49307578U, // VFMSUB231SSZr_Intk 2196791226U, // VFMSUB231SSZr_Intkz 2182111162U, // VFMSUB231SSZrb 2182111162U, // VFMSUB231SSZrb_Int 49307578U, // VFMSUB231SSZrb_Intk 2196791226U, // VFMSUB231SSZrb_Intkz 2182111162U, // VFMSUB231SSm 2182111162U, // VFMSUB231SSm_Int 2182111162U, // VFMSUB231SSr 2182111162U, // VFMSUB231SSr_Int 2182105454U, // VFMSUBADD132PDYm 2182105454U, // VFMSUBADD132PDYr 2182105454U, // VFMSUBADD132PDZ128m 2182105454U, // VFMSUBADD132PDZ128mb 49301870U, // VFMSUBADD132PDZ128mbk 2196785518U, // VFMSUBADD132PDZ128mbkz 49301870U, // VFMSUBADD132PDZ128mk 2196785518U, // VFMSUBADD132PDZ128mkz 2182105454U, // VFMSUBADD132PDZ128r 49301870U, // VFMSUBADD132PDZ128rk 2196785518U, // VFMSUBADD132PDZ128rkz 2182105454U, // VFMSUBADD132PDZ256m 2182105454U, // VFMSUBADD132PDZ256mb 49301870U, // VFMSUBADD132PDZ256mbk 2196785518U, // VFMSUBADD132PDZ256mbkz 49301870U, // VFMSUBADD132PDZ256mk 2196785518U, // VFMSUBADD132PDZ256mkz 2182105454U, // VFMSUBADD132PDZ256r 49301870U, // VFMSUBADD132PDZ256rk 2196785518U, // VFMSUBADD132PDZ256rkz 2182105454U, // VFMSUBADD132PDZm 2182105454U, // VFMSUBADD132PDZmb 49301870U, // VFMSUBADD132PDZmbk 2196785518U, // VFMSUBADD132PDZmbkz 49301870U, // VFMSUBADD132PDZmk 2196785518U, // VFMSUBADD132PDZmkz 2182105454U, // VFMSUBADD132PDZr 2182105454U, // VFMSUBADD132PDZrb 49301870U, // VFMSUBADD132PDZrbk 2196785518U, // VFMSUBADD132PDZrbkz 49301870U, // VFMSUBADD132PDZrk 2196785518U, // VFMSUBADD132PDZrkz 2182105454U, // VFMSUBADD132PDm 2182105454U, // VFMSUBADD132PDr 2182110227U, // VFMSUBADD132PSYm 2182110227U, // VFMSUBADD132PSYr 2182110227U, // VFMSUBADD132PSZ128m 2182110227U, // VFMSUBADD132PSZ128mb 49306643U, // VFMSUBADD132PSZ128mbk 2196790291U, // VFMSUBADD132PSZ128mbkz 49306643U, // VFMSUBADD132PSZ128mk 2196790291U, // VFMSUBADD132PSZ128mkz 2182110227U, // VFMSUBADD132PSZ128r 49306643U, // VFMSUBADD132PSZ128rk 2196790291U, // VFMSUBADD132PSZ128rkz 2182110227U, // VFMSUBADD132PSZ256m 2182110227U, // VFMSUBADD132PSZ256mb 49306643U, // VFMSUBADD132PSZ256mbk 2196790291U, // VFMSUBADD132PSZ256mbkz 49306643U, // VFMSUBADD132PSZ256mk 2196790291U, // VFMSUBADD132PSZ256mkz 2182110227U, // VFMSUBADD132PSZ256r 49306643U, // VFMSUBADD132PSZ256rk 2196790291U, // VFMSUBADD132PSZ256rkz 2182110227U, // VFMSUBADD132PSZm 2182110227U, // VFMSUBADD132PSZmb 49306643U, // VFMSUBADD132PSZmbk 2196790291U, // VFMSUBADD132PSZmbkz 49306643U, // VFMSUBADD132PSZmk 2196790291U, // VFMSUBADD132PSZmkz 2182110227U, // VFMSUBADD132PSZr 2182110227U, // VFMSUBADD132PSZrb 49306643U, // VFMSUBADD132PSZrbk 2196790291U, // VFMSUBADD132PSZrbkz 49306643U, // VFMSUBADD132PSZrk 2196790291U, // VFMSUBADD132PSZrkz 2182110227U, // VFMSUBADD132PSm 2182110227U, // VFMSUBADD132PSr 2182105650U, // VFMSUBADD213PDYm 2182105650U, // VFMSUBADD213PDYr 2182105650U, // VFMSUBADD213PDZ128m 2182105650U, // VFMSUBADD213PDZ128mb 49302066U, // VFMSUBADD213PDZ128mbk 2196785714U, // VFMSUBADD213PDZ128mbkz 49302066U, // VFMSUBADD213PDZ128mk 2196785714U, // VFMSUBADD213PDZ128mkz 2182105650U, // VFMSUBADD213PDZ128r 49302066U, // VFMSUBADD213PDZ128rk 2196785714U, // VFMSUBADD213PDZ128rkz 2182105650U, // VFMSUBADD213PDZ256m 2182105650U, // VFMSUBADD213PDZ256mb 49302066U, // VFMSUBADD213PDZ256mbk 2196785714U, // VFMSUBADD213PDZ256mbkz 49302066U, // VFMSUBADD213PDZ256mk 2196785714U, // VFMSUBADD213PDZ256mkz 2182105650U, // VFMSUBADD213PDZ256r 49302066U, // VFMSUBADD213PDZ256rk 2196785714U, // VFMSUBADD213PDZ256rkz 2182105650U, // VFMSUBADD213PDZm 2182105650U, // VFMSUBADD213PDZmb 49302066U, // VFMSUBADD213PDZmbk 2196785714U, // VFMSUBADD213PDZmbkz 49302066U, // VFMSUBADD213PDZmk 2196785714U, // VFMSUBADD213PDZmkz 2182105650U, // VFMSUBADD213PDZr 2182105650U, // VFMSUBADD213PDZrb 49302066U, // VFMSUBADD213PDZrbk 2196785714U, // VFMSUBADD213PDZrbkz 49302066U, // VFMSUBADD213PDZrk 2196785714U, // VFMSUBADD213PDZrkz 2182105650U, // VFMSUBADD213PDm 2182105650U, // VFMSUBADD213PDr 2182110434U, // VFMSUBADD213PSYm 2182110434U, // VFMSUBADD213PSYr 2182110434U, // VFMSUBADD213PSZ128m 2182110434U, // VFMSUBADD213PSZ128mb 49306850U, // VFMSUBADD213PSZ128mbk 2196790498U, // VFMSUBADD213PSZ128mbkz 49306850U, // VFMSUBADD213PSZ128mk 2196790498U, // VFMSUBADD213PSZ128mkz 2182110434U, // VFMSUBADD213PSZ128r 49306850U, // VFMSUBADD213PSZ128rk 2196790498U, // VFMSUBADD213PSZ128rkz 2182110434U, // VFMSUBADD213PSZ256m 2182110434U, // VFMSUBADD213PSZ256mb 49306850U, // VFMSUBADD213PSZ256mbk 2196790498U, // VFMSUBADD213PSZ256mbkz 49306850U, // VFMSUBADD213PSZ256mk 2196790498U, // VFMSUBADD213PSZ256mkz 2182110434U, // VFMSUBADD213PSZ256r 49306850U, // VFMSUBADD213PSZ256rk 2196790498U, // VFMSUBADD213PSZ256rkz 2182110434U, // VFMSUBADD213PSZm 2182110434U, // VFMSUBADD213PSZmb 49306850U, // VFMSUBADD213PSZmbk 2196790498U, // VFMSUBADD213PSZmbkz 49306850U, // VFMSUBADD213PSZmk 2196790498U, // VFMSUBADD213PSZmkz 2182110434U, // VFMSUBADD213PSZr 2182110434U, // VFMSUBADD213PSZrb 49306850U, // VFMSUBADD213PSZrbk 2196790498U, // VFMSUBADD213PSZrbkz 49306850U, // VFMSUBADD213PSZrk 2196790498U, // VFMSUBADD213PSZrkz 2182110434U, // VFMSUBADD213PSm 2182110434U, // VFMSUBADD213PSr 2182105368U, // VFMSUBADD231PDYm 2182105368U, // VFMSUBADD231PDYr 2182105368U, // VFMSUBADD231PDZ128m 2182105368U, // VFMSUBADD231PDZ128mb 49301784U, // VFMSUBADD231PDZ128mbk 2196785432U, // VFMSUBADD231PDZ128mbkz 49301784U, // VFMSUBADD231PDZ128mk 2196785432U, // VFMSUBADD231PDZ128mkz 2182105368U, // VFMSUBADD231PDZ128r 49301784U, // VFMSUBADD231PDZ128rk 2196785432U, // VFMSUBADD231PDZ128rkz 2182105368U, // VFMSUBADD231PDZ256m 2182105368U, // VFMSUBADD231PDZ256mb 49301784U, // VFMSUBADD231PDZ256mbk 2196785432U, // VFMSUBADD231PDZ256mbkz 49301784U, // VFMSUBADD231PDZ256mk 2196785432U, // VFMSUBADD231PDZ256mkz 2182105368U, // VFMSUBADD231PDZ256r 49301784U, // VFMSUBADD231PDZ256rk 2196785432U, // VFMSUBADD231PDZ256rkz 2182105368U, // VFMSUBADD231PDZm 2182105368U, // VFMSUBADD231PDZmb 49301784U, // VFMSUBADD231PDZmbk 2196785432U, // VFMSUBADD231PDZmbkz 49301784U, // VFMSUBADD231PDZmk 2196785432U, // VFMSUBADD231PDZmkz 2182105368U, // VFMSUBADD231PDZr 2182105368U, // VFMSUBADD231PDZrb 49301784U, // VFMSUBADD231PDZrbk 2196785432U, // VFMSUBADD231PDZrbkz 49301784U, // VFMSUBADD231PDZrk 2196785432U, // VFMSUBADD231PDZrkz 2182105368U, // VFMSUBADD231PDm 2182105368U, // VFMSUBADD231PDr 2182110141U, // VFMSUBADD231PSYm 2182110141U, // VFMSUBADD231PSYr 2182110141U, // VFMSUBADD231PSZ128m 2182110141U, // VFMSUBADD231PSZ128mb 49306557U, // VFMSUBADD231PSZ128mbk 2196790205U, // VFMSUBADD231PSZ128mbkz 49306557U, // VFMSUBADD231PSZ128mk 2196790205U, // VFMSUBADD231PSZ128mkz 2182110141U, // VFMSUBADD231PSZ128r 49306557U, // VFMSUBADD231PSZ128rk 2196790205U, // VFMSUBADD231PSZ128rkz 2182110141U, // VFMSUBADD231PSZ256m 2182110141U, // VFMSUBADD231PSZ256mb 49306557U, // VFMSUBADD231PSZ256mbk 2196790205U, // VFMSUBADD231PSZ256mbkz 49306557U, // VFMSUBADD231PSZ256mk 2196790205U, // VFMSUBADD231PSZ256mkz 2182110141U, // VFMSUBADD231PSZ256r 49306557U, // VFMSUBADD231PSZ256rk 2196790205U, // VFMSUBADD231PSZ256rkz 2182110141U, // VFMSUBADD231PSZm 2182110141U, // VFMSUBADD231PSZmb 49306557U, // VFMSUBADD231PSZmbk 2196790205U, // VFMSUBADD231PSZmbkz 49306557U, // VFMSUBADD231PSZmk 2196790205U, // VFMSUBADD231PSZmkz 2182110141U, // VFMSUBADD231PSZr 2182110141U, // VFMSUBADD231PSZrb 49306557U, // VFMSUBADD231PSZrbk 2196790205U, // VFMSUBADD231PSZrbkz 49306557U, // VFMSUBADD231PSZrk 2196790205U, // VFMSUBADD231PSZrkz 2182110141U, // VFMSUBADD231PSm 2182110141U, // VFMSUBADD231PSr 2517650136U, // VFMSUBADDPD4Ymr 2517650136U, // VFMSUBADDPD4Yrm 2517650136U, // VFMSUBADDPD4Yrr 2517650136U, // VFMSUBADDPD4Yrr_REV 2517650136U, // VFMSUBADDPD4mr 2517650136U, // VFMSUBADDPD4rm 2517650136U, // VFMSUBADDPD4rr 2517650136U, // VFMSUBADDPD4rr_REV 2517654912U, // VFMSUBADDPS4Ymr 2517654912U, // VFMSUBADDPS4Yrm 2517654912U, // VFMSUBADDPS4Yrr 2517654912U, // VFMSUBADDPS4Yrr_REV 2517654912U, // VFMSUBADDPS4mr 2517654912U, // VFMSUBADDPS4rm 2517654912U, // VFMSUBADDPS4rr 2517654912U, // VFMSUBADDPS4rr_REV 2517650107U, // VFMSUBPD4Ymr 2517650107U, // VFMSUBPD4Yrm 2517650107U, // VFMSUBPD4Yrr 2517650107U, // VFMSUBPD4Yrr_REV 2517650107U, // VFMSUBPD4mr 2517650107U, // VFMSUBPD4rm 2517650107U, // VFMSUBPD4rr 2517650107U, // VFMSUBPD4rr_REV 2517654883U, // VFMSUBPS4Ymr 2517654883U, // VFMSUBPS4Yrm 2517654883U, // VFMSUBPS4Yrr 2517654883U, // VFMSUBPS4Yrr_REV 2517654883U, // VFMSUBPS4mr 2517654883U, // VFMSUBPS4rm 2517654883U, // VFMSUBPS4rr 2517654883U, // VFMSUBPS4rr_REV 2517651029U, // VFMSUBSD4mr 2517651029U, // VFMSUBSD4mr_Int 2517651029U, // VFMSUBSD4rm 2517651029U, // VFMSUBSD4rm_Int 2517651029U, // VFMSUBSD4rr 2517651029U, // VFMSUBSD4rr_Int 2517651029U, // VFMSUBSD4rr_Int_REV 2517651029U, // VFMSUBSD4rr_REV 2517655722U, // VFMSUBSS4mr 2517655722U, // VFMSUBSS4mr_Int 2517655722U, // VFMSUBSS4rm 2517655722U, // VFMSUBSS4rm_Int 2517655722U, // VFMSUBSS4rr 2517655722U, // VFMSUBSS4rr_Int 2517655722U, // VFMSUBSS4rr_Int_REV 2517655722U, // VFMSUBSS4rr_REV 2182105483U, // VFNMADD132PDYm 2182105483U, // VFNMADD132PDYr 2182105483U, // VFNMADD132PDZ128m 2182105483U, // VFNMADD132PDZ128mb 49301899U, // VFNMADD132PDZ128mbk 2196785547U, // VFNMADD132PDZ128mbkz 49301899U, // VFNMADD132PDZ128mk 2196785547U, // VFNMADD132PDZ128mkz 2182105483U, // VFNMADD132PDZ128r 49301899U, // VFNMADD132PDZ128rk 2196785547U, // VFNMADD132PDZ128rkz 2182105483U, // VFNMADD132PDZ256m 2182105483U, // VFNMADD132PDZ256mb 49301899U, // VFNMADD132PDZ256mbk 2196785547U, // VFNMADD132PDZ256mbkz 49301899U, // VFNMADD132PDZ256mk 2196785547U, // VFNMADD132PDZ256mkz 2182105483U, // VFNMADD132PDZ256r 49301899U, // VFNMADD132PDZ256rk 2196785547U, // VFNMADD132PDZ256rkz 2182105483U, // VFNMADD132PDZm 2182105483U, // VFNMADD132PDZmb 49301899U, // VFNMADD132PDZmbk 2196785547U, // VFNMADD132PDZmbkz 49301899U, // VFNMADD132PDZmk 2196785547U, // VFNMADD132PDZmkz 2182105483U, // VFNMADD132PDZr 2182105483U, // VFNMADD132PDZrb 49301899U, // VFNMADD132PDZrbk 2196785547U, // VFNMADD132PDZrbkz 49301899U, // VFNMADD132PDZrk 2196785547U, // VFNMADD132PDZrkz 2182105483U, // VFNMADD132PDm 2182105483U, // VFNMADD132PDr 2182110256U, // VFNMADD132PSYm 2182110256U, // VFNMADD132PSYr 2182110256U, // VFNMADD132PSZ128m 2182110256U, // VFNMADD132PSZ128mb 49306672U, // VFNMADD132PSZ128mbk 2196790320U, // VFNMADD132PSZ128mbkz 49306672U, // VFNMADD132PSZ128mk 2196790320U, // VFNMADD132PSZ128mkz 2182110256U, // VFNMADD132PSZ128r 49306672U, // VFNMADD132PSZ128rk 2196790320U, // VFNMADD132PSZ128rkz 2182110256U, // VFNMADD132PSZ256m 2182110256U, // VFNMADD132PSZ256mb 49306672U, // VFNMADD132PSZ256mbk 2196790320U, // VFNMADD132PSZ256mbkz 49306672U, // VFNMADD132PSZ256mk 2196790320U, // VFNMADD132PSZ256mkz 2182110256U, // VFNMADD132PSZ256r 49306672U, // VFNMADD132PSZ256rk 2196790320U, // VFNMADD132PSZ256rkz 2182110256U, // VFNMADD132PSZm 2182110256U, // VFNMADD132PSZmb 49306672U, // VFNMADD132PSZmbk 2196790320U, // VFNMADD132PSZmbkz 49306672U, // VFNMADD132PSZmk 2196790320U, // VFNMADD132PSZmkz 2182110256U, // VFNMADD132PSZr 2182110256U, // VFNMADD132PSZrb 49306672U, // VFNMADD132PSZrbk 2196790320U, // VFNMADD132PSZrbkz 49306672U, // VFNMADD132PSZrk 2196790320U, // VFNMADD132PSZrkz 2182110256U, // VFNMADD132PSm 2182110256U, // VFNMADD132PSr 2182106555U, // VFNMADD132SDZm 2182106555U, // VFNMADD132SDZm_Int 49302971U, // VFNMADD132SDZm_Intk 2196786619U, // VFNMADD132SDZm_Intkz 2182106555U, // VFNMADD132SDZr 2182106555U, // VFNMADD132SDZr_Int 49302971U, // VFNMADD132SDZr_Intk 2196786619U, // VFNMADD132SDZr_Intkz 2182106555U, // VFNMADD132SDZrb 2182106555U, // VFNMADD132SDZrb_Int 49302971U, // VFNMADD132SDZrb_Intk 2196786619U, // VFNMADD132SDZrb_Intkz 2182106555U, // VFNMADD132SDm 2182106555U, // VFNMADD132SDm_Int 2182106555U, // VFNMADD132SDr 2182106555U, // VFNMADD132SDr_Int 2182111256U, // VFNMADD132SSZm 2182111256U, // VFNMADD132SSZm_Int 49307672U, // VFNMADD132SSZm_Intk 2196791320U, // VFNMADD132SSZm_Intkz 2182111256U, // VFNMADD132SSZr 2182111256U, // VFNMADD132SSZr_Int 49307672U, // VFNMADD132SSZr_Intk 2196791320U, // VFNMADD132SSZr_Intkz 2182111256U, // VFNMADD132SSZrb 2182111256U, // VFNMADD132SSZrb_Int 49307672U, // VFNMADD132SSZrb_Intk 2196791320U, // VFNMADD132SSZrb_Intkz 2182111256U, // VFNMADD132SSm 2182111256U, // VFNMADD132SSm_Int 2182111256U, // VFNMADD132SSr 2182111256U, // VFNMADD132SSr_Int 2182105679U, // VFNMADD213PDYm 2182105679U, // VFNMADD213PDYr 2182105679U, // VFNMADD213PDZ128m 2182105679U, // VFNMADD213PDZ128mb 49302095U, // VFNMADD213PDZ128mbk 2196785743U, // VFNMADD213PDZ128mbkz 49302095U, // VFNMADD213PDZ128mk 2196785743U, // VFNMADD213PDZ128mkz 2182105679U, // VFNMADD213PDZ128r 49302095U, // VFNMADD213PDZ128rk 2196785743U, // VFNMADD213PDZ128rkz 2182105679U, // VFNMADD213PDZ256m 2182105679U, // VFNMADD213PDZ256mb 49302095U, // VFNMADD213PDZ256mbk 2196785743U, // VFNMADD213PDZ256mbkz 49302095U, // VFNMADD213PDZ256mk 2196785743U, // VFNMADD213PDZ256mkz 2182105679U, // VFNMADD213PDZ256r 49302095U, // VFNMADD213PDZ256rk 2196785743U, // VFNMADD213PDZ256rkz 2182105679U, // VFNMADD213PDZm 2182105679U, // VFNMADD213PDZmb 49302095U, // VFNMADD213PDZmbk 2196785743U, // VFNMADD213PDZmbkz 49302095U, // VFNMADD213PDZmk 2196785743U, // VFNMADD213PDZmkz 2182105679U, // VFNMADD213PDZr 2182105679U, // VFNMADD213PDZrb 49302095U, // VFNMADD213PDZrbk 2196785743U, // VFNMADD213PDZrbkz 49302095U, // VFNMADD213PDZrk 2196785743U, // VFNMADD213PDZrkz 2182105679U, // VFNMADD213PDm 2182105679U, // VFNMADD213PDr 2182110463U, // VFNMADD213PSYm 2182110463U, // VFNMADD213PSYr 2182110463U, // VFNMADD213PSZ128m 2182110463U, // VFNMADD213PSZ128mb 49306879U, // VFNMADD213PSZ128mbk 2196790527U, // VFNMADD213PSZ128mbkz 49306879U, // VFNMADD213PSZ128mk 2196790527U, // VFNMADD213PSZ128mkz 2182110463U, // VFNMADD213PSZ128r 49306879U, // VFNMADD213PSZ128rk 2196790527U, // VFNMADD213PSZ128rkz 2182110463U, // VFNMADD213PSZ256m 2182110463U, // VFNMADD213PSZ256mb 49306879U, // VFNMADD213PSZ256mbk 2196790527U, // VFNMADD213PSZ256mbkz 49306879U, // VFNMADD213PSZ256mk 2196790527U, // VFNMADD213PSZ256mkz 2182110463U, // VFNMADD213PSZ256r 49306879U, // VFNMADD213PSZ256rk 2196790527U, // VFNMADD213PSZ256rkz 2182110463U, // VFNMADD213PSZm 2182110463U, // VFNMADD213PSZmb 49306879U, // VFNMADD213PSZmbk 2196790527U, // VFNMADD213PSZmbkz 49306879U, // VFNMADD213PSZmk 2196790527U, // VFNMADD213PSZmkz 2182110463U, // VFNMADD213PSZr 2182110463U, // VFNMADD213PSZrb 49306879U, // VFNMADD213PSZrbk 2196790527U, // VFNMADD213PSZrbkz 49306879U, // VFNMADD213PSZrk 2196790527U, // VFNMADD213PSZrkz 2182110463U, // VFNMADD213PSm 2182110463U, // VFNMADD213PSr 2182106643U, // VFNMADD213SDZm 2182106643U, // VFNMADD213SDZm_Int 49303059U, // VFNMADD213SDZm_Intk 2196786707U, // VFNMADD213SDZm_Intkz 2182106643U, // VFNMADD213SDZr 2182106643U, // VFNMADD213SDZr_Int 49303059U, // VFNMADD213SDZr_Intk 2196786707U, // VFNMADD213SDZr_Intkz 2182106643U, // VFNMADD213SDZrb 2182106643U, // VFNMADD213SDZrb_Int 49303059U, // VFNMADD213SDZrb_Intk 2196786707U, // VFNMADD213SDZrb_Intkz 2182106643U, // VFNMADD213SDm 2182106643U, // VFNMADD213SDm_Int 2182106643U, // VFNMADD213SDr 2182106643U, // VFNMADD213SDr_Int 2182111344U, // VFNMADD213SSZm 2182111344U, // VFNMADD213SSZm_Int 49307760U, // VFNMADD213SSZm_Intk 2196791408U, // VFNMADD213SSZm_Intkz 2182111344U, // VFNMADD213SSZr 2182111344U, // VFNMADD213SSZr_Int 49307760U, // VFNMADD213SSZr_Intk 2196791408U, // VFNMADD213SSZr_Intkz 2182111344U, // VFNMADD213SSZrb 2182111344U, // VFNMADD213SSZrb_Int 49307760U, // VFNMADD213SSZrb_Intk 2196791408U, // VFNMADD213SSZrb_Intkz 2182111344U, // VFNMADD213SSm 2182111344U, // VFNMADD213SSm_Int 2182111344U, // VFNMADD213SSr 2182111344U, // VFNMADD213SSr_Int 2182105397U, // VFNMADD231PDYm 2182105397U, // VFNMADD231PDYr 2182105397U, // VFNMADD231PDZ128m 2182105397U, // VFNMADD231PDZ128mb 49301813U, // VFNMADD231PDZ128mbk 2196785461U, // VFNMADD231PDZ128mbkz 49301813U, // VFNMADD231PDZ128mk 2196785461U, // VFNMADD231PDZ128mkz 2182105397U, // VFNMADD231PDZ128r 49301813U, // VFNMADD231PDZ128rk 2196785461U, // VFNMADD231PDZ128rkz 2182105397U, // VFNMADD231PDZ256m 2182105397U, // VFNMADD231PDZ256mb 49301813U, // VFNMADD231PDZ256mbk 2196785461U, // VFNMADD231PDZ256mbkz 49301813U, // VFNMADD231PDZ256mk 2196785461U, // VFNMADD231PDZ256mkz 2182105397U, // VFNMADD231PDZ256r 49301813U, // VFNMADD231PDZ256rk 2196785461U, // VFNMADD231PDZ256rkz 2182105397U, // VFNMADD231PDZm 2182105397U, // VFNMADD231PDZmb 49301813U, // VFNMADD231PDZmbk 2196785461U, // VFNMADD231PDZmbkz 49301813U, // VFNMADD231PDZmk 2196785461U, // VFNMADD231PDZmkz 2182105397U, // VFNMADD231PDZr 2182105397U, // VFNMADD231PDZrb 49301813U, // VFNMADD231PDZrbk 2196785461U, // VFNMADD231PDZrbkz 49301813U, // VFNMADD231PDZrk 2196785461U, // VFNMADD231PDZrkz 2182105397U, // VFNMADD231PDm 2182105397U, // VFNMADD231PDr 2182110170U, // VFNMADD231PSYm 2182110170U, // VFNMADD231PSYr 2182110170U, // VFNMADD231PSZ128m 2182110170U, // VFNMADD231PSZ128mb 49306586U, // VFNMADD231PSZ128mbk 2196790234U, // VFNMADD231PSZ128mbkz 49306586U, // VFNMADD231PSZ128mk 2196790234U, // VFNMADD231PSZ128mkz 2182110170U, // VFNMADD231PSZ128r 49306586U, // VFNMADD231PSZ128rk 2196790234U, // VFNMADD231PSZ128rkz 2182110170U, // VFNMADD231PSZ256m 2182110170U, // VFNMADD231PSZ256mb 49306586U, // VFNMADD231PSZ256mbk 2196790234U, // VFNMADD231PSZ256mbkz 49306586U, // VFNMADD231PSZ256mk 2196790234U, // VFNMADD231PSZ256mkz 2182110170U, // VFNMADD231PSZ256r 49306586U, // VFNMADD231PSZ256rk 2196790234U, // VFNMADD231PSZ256rkz 2182110170U, // VFNMADD231PSZm 2182110170U, // VFNMADD231PSZmb 49306586U, // VFNMADD231PSZmbk 2196790234U, // VFNMADD231PSZmbkz 49306586U, // VFNMADD231PSZmk 2196790234U, // VFNMADD231PSZmkz 2182110170U, // VFNMADD231PSZr 2182110170U, // VFNMADD231PSZrb 49306586U, // VFNMADD231PSZrbk 2196790234U, // VFNMADD231PSZrbkz 49306586U, // VFNMADD231PSZrk 2196790234U, // VFNMADD231PSZrkz 2182110170U, // VFNMADD231PSm 2182110170U, // VFNMADD231PSr 2182106501U, // VFNMADD231SDZm 2182106501U, // VFNMADD231SDZm_Int 49302917U, // VFNMADD231SDZm_Intk 2196786565U, // VFNMADD231SDZm_Intkz 2182106501U, // VFNMADD231SDZr 2182106501U, // VFNMADD231SDZr_Int 49302917U, // VFNMADD231SDZr_Intk 2196786565U, // VFNMADD231SDZr_Intkz 2182106501U, // VFNMADD231SDZrb 2182106501U, // VFNMADD231SDZrb_Int 49302917U, // VFNMADD231SDZrb_Intk 2196786565U, // VFNMADD231SDZrb_Intkz 2182106501U, // VFNMADD231SDm 2182106501U, // VFNMADD231SDm_Int 2182106501U, // VFNMADD231SDr 2182106501U, // VFNMADD231SDr_Int 2182111202U, // VFNMADD231SSZm 2182111202U, // VFNMADD231SSZm_Int 49307618U, // VFNMADD231SSZm_Intk 2196791266U, // VFNMADD231SSZm_Intkz 2182111202U, // VFNMADD231SSZr 2182111202U, // VFNMADD231SSZr_Int 49307618U, // VFNMADD231SSZr_Intk 2196791266U, // VFNMADD231SSZr_Intkz 2182111202U, // VFNMADD231SSZrb 2182111202U, // VFNMADD231SSZrb_Int 49307618U, // VFNMADD231SSZrb_Intk 2196791266U, // VFNMADD231SSZrb_Intkz 2182111202U, // VFNMADD231SSm 2182111202U, // VFNMADD231SSm_Int 2182111202U, // VFNMADD231SSr 2182111202U, // VFNMADD231SSr_Int 2517650168U, // VFNMADDPD4Ymr 2517650168U, // VFNMADDPD4Yrm 2517650168U, // VFNMADDPD4Yrr 2517650168U, // VFNMADDPD4Yrr_REV 2517650168U, // VFNMADDPD4mr 2517650168U, // VFNMADDPD4rm 2517650168U, // VFNMADDPD4rr 2517650168U, // VFNMADDPD4rr_REV 2517654967U, // VFNMADDPS4Ymr 2517654967U, // VFNMADDPS4Yrm 2517654967U, // VFNMADDPS4Yrr 2517654967U, // VFNMADDPS4Yrr_REV 2517654967U, // VFNMADDPS4mr 2517654967U, // VFNMADDPS4rm 2517654967U, // VFNMADDPS4rr 2517654967U, // VFNMADDPS4rr_REV 2517651068U, // VFNMADDSD4mr 2517651068U, // VFNMADDSD4mr_Int 2517651068U, // VFNMADDSD4rm 2517651068U, // VFNMADDSD4rm_Int 2517651068U, // VFNMADDSD4rr 2517651068U, // VFNMADDSD4rr_Int 2517651068U, // VFNMADDSD4rr_Int_REV 2517651068U, // VFNMADDSD4rr_REV 2517655784U, // VFNMADDSS4mr 2517655784U, // VFNMADDSS4mr_Int 2517655784U, // VFNMADDSS4rm 2517655784U, // VFNMADDSS4rm_Int 2517655784U, // VFNMADDSS4rr 2517655784U, // VFNMADDSS4rr_Int 2517655784U, // VFNMADDSS4rr_Int_REV 2517655784U, // VFNMADDSS4rr_REV 2182105440U, // VFNMSUB132PDYm 2182105440U, // VFNMSUB132PDYr 2182105440U, // VFNMSUB132PDZ128m 2182105440U, // VFNMSUB132PDZ128mb 49301856U, // VFNMSUB132PDZ128mbk 2196785504U, // VFNMSUB132PDZ128mbkz 49301856U, // VFNMSUB132PDZ128mk 2196785504U, // VFNMSUB132PDZ128mkz 2182105440U, // VFNMSUB132PDZ128r 49301856U, // VFNMSUB132PDZ128rk 2196785504U, // VFNMSUB132PDZ128rkz 2182105440U, // VFNMSUB132PDZ256m 2182105440U, // VFNMSUB132PDZ256mb 49301856U, // VFNMSUB132PDZ256mbk 2196785504U, // VFNMSUB132PDZ256mbkz 49301856U, // VFNMSUB132PDZ256mk 2196785504U, // VFNMSUB132PDZ256mkz 2182105440U, // VFNMSUB132PDZ256r 49301856U, // VFNMSUB132PDZ256rk 2196785504U, // VFNMSUB132PDZ256rkz 2182105440U, // VFNMSUB132PDZm 2182105440U, // VFNMSUB132PDZmb 49301856U, // VFNMSUB132PDZmbk 2196785504U, // VFNMSUB132PDZmbkz 49301856U, // VFNMSUB132PDZmk 2196785504U, // VFNMSUB132PDZmkz 2182105440U, // VFNMSUB132PDZr 2182105440U, // VFNMSUB132PDZrb 49301856U, // VFNMSUB132PDZrbk 2196785504U, // VFNMSUB132PDZrbkz 49301856U, // VFNMSUB132PDZrk 2196785504U, // VFNMSUB132PDZrkz 2182105440U, // VFNMSUB132PDm 2182105440U, // VFNMSUB132PDr 2182110213U, // VFNMSUB132PSYm 2182110213U, // VFNMSUB132PSYr 2182110213U, // VFNMSUB132PSZ128m 2182110213U, // VFNMSUB132PSZ128mb 49306629U, // VFNMSUB132PSZ128mbk 2196790277U, // VFNMSUB132PSZ128mbkz 49306629U, // VFNMSUB132PSZ128mk 2196790277U, // VFNMSUB132PSZ128mkz 2182110213U, // VFNMSUB132PSZ128r 49306629U, // VFNMSUB132PSZ128rk 2196790277U, // VFNMSUB132PSZ128rkz 2182110213U, // VFNMSUB132PSZ256m 2182110213U, // VFNMSUB132PSZ256mb 49306629U, // VFNMSUB132PSZ256mbk 2196790277U, // VFNMSUB132PSZ256mbkz 49306629U, // VFNMSUB132PSZ256mk 2196790277U, // VFNMSUB132PSZ256mkz 2182110213U, // VFNMSUB132PSZ256r 49306629U, // VFNMSUB132PSZ256rk 2196790277U, // VFNMSUB132PSZ256rkz 2182110213U, // VFNMSUB132PSZm 2182110213U, // VFNMSUB132PSZmb 49306629U, // VFNMSUB132PSZmbk 2196790277U, // VFNMSUB132PSZmbkz 49306629U, // VFNMSUB132PSZmk 2196790277U, // VFNMSUB132PSZmkz 2182110213U, // VFNMSUB132PSZr 2182110213U, // VFNMSUB132PSZrb 49306629U, // VFNMSUB132PSZrbk 2196790277U, // VFNMSUB132PSZrbkz 49306629U, // VFNMSUB132PSZrk 2196790277U, // VFNMSUB132PSZrkz 2182110213U, // VFNMSUB132PSm 2182110213U, // VFNMSUB132PSr 2182106528U, // VFNMSUB132SDZm 2182106528U, // VFNMSUB132SDZm_Int 49302944U, // VFNMSUB132SDZm_Intk 2196786592U, // VFNMSUB132SDZm_Intkz 2182106528U, // VFNMSUB132SDZr 2182106528U, // VFNMSUB132SDZr_Int 49302944U, // VFNMSUB132SDZr_Intk 2196786592U, // VFNMSUB132SDZr_Intkz 2182106528U, // VFNMSUB132SDZrb 2182106528U, // VFNMSUB132SDZrb_Int 49302944U, // VFNMSUB132SDZrb_Intk 2196786592U, // VFNMSUB132SDZrb_Intkz 2182106528U, // VFNMSUB132SDm 2182106528U, // VFNMSUB132SDm_Int 2182106528U, // VFNMSUB132SDr 2182106528U, // VFNMSUB132SDr_Int 2182111229U, // VFNMSUB132SSZm 2182111229U, // VFNMSUB132SSZm_Int 49307645U, // VFNMSUB132SSZm_Intk 2196791293U, // VFNMSUB132SSZm_Intkz 2182111229U, // VFNMSUB132SSZr 2182111229U, // VFNMSUB132SSZr_Int 49307645U, // VFNMSUB132SSZr_Intk 2196791293U, // VFNMSUB132SSZr_Intkz 2182111229U, // VFNMSUB132SSZrb 2182111229U, // VFNMSUB132SSZrb_Int 49307645U, // VFNMSUB132SSZrb_Intk 2196791293U, // VFNMSUB132SSZrb_Intkz 2182111229U, // VFNMSUB132SSm 2182111229U, // VFNMSUB132SSm_Int 2182111229U, // VFNMSUB132SSr 2182111229U, // VFNMSUB132SSr_Int 2182105636U, // VFNMSUB213PDYm 2182105636U, // VFNMSUB213PDYr 2182105636U, // VFNMSUB213PDZ128m 2182105636U, // VFNMSUB213PDZ128mb 49302052U, // VFNMSUB213PDZ128mbk 2196785700U, // VFNMSUB213PDZ128mbkz 49302052U, // VFNMSUB213PDZ128mk 2196785700U, // VFNMSUB213PDZ128mkz 2182105636U, // VFNMSUB213PDZ128r 49302052U, // VFNMSUB213PDZ128rk 2196785700U, // VFNMSUB213PDZ128rkz 2182105636U, // VFNMSUB213PDZ256m 2182105636U, // VFNMSUB213PDZ256mb 49302052U, // VFNMSUB213PDZ256mbk 2196785700U, // VFNMSUB213PDZ256mbkz 49302052U, // VFNMSUB213PDZ256mk 2196785700U, // VFNMSUB213PDZ256mkz 2182105636U, // VFNMSUB213PDZ256r 49302052U, // VFNMSUB213PDZ256rk 2196785700U, // VFNMSUB213PDZ256rkz 2182105636U, // VFNMSUB213PDZm 2182105636U, // VFNMSUB213PDZmb 49302052U, // VFNMSUB213PDZmbk 2196785700U, // VFNMSUB213PDZmbkz 49302052U, // VFNMSUB213PDZmk 2196785700U, // VFNMSUB213PDZmkz 2182105636U, // VFNMSUB213PDZr 2182105636U, // VFNMSUB213PDZrb 49302052U, // VFNMSUB213PDZrbk 2196785700U, // VFNMSUB213PDZrbkz 49302052U, // VFNMSUB213PDZrk 2196785700U, // VFNMSUB213PDZrkz 2182105636U, // VFNMSUB213PDm 2182105636U, // VFNMSUB213PDr 2182110420U, // VFNMSUB213PSYm 2182110420U, // VFNMSUB213PSYr 2182110420U, // VFNMSUB213PSZ128m 2182110420U, // VFNMSUB213PSZ128mb 49306836U, // VFNMSUB213PSZ128mbk 2196790484U, // VFNMSUB213PSZ128mbkz 49306836U, // VFNMSUB213PSZ128mk 2196790484U, // VFNMSUB213PSZ128mkz 2182110420U, // VFNMSUB213PSZ128r 49306836U, // VFNMSUB213PSZ128rk 2196790484U, // VFNMSUB213PSZ128rkz 2182110420U, // VFNMSUB213PSZ256m 2182110420U, // VFNMSUB213PSZ256mb 49306836U, // VFNMSUB213PSZ256mbk 2196790484U, // VFNMSUB213PSZ256mbkz 49306836U, // VFNMSUB213PSZ256mk 2196790484U, // VFNMSUB213PSZ256mkz 2182110420U, // VFNMSUB213PSZ256r 49306836U, // VFNMSUB213PSZ256rk 2196790484U, // VFNMSUB213PSZ256rkz 2182110420U, // VFNMSUB213PSZm 2182110420U, // VFNMSUB213PSZmb 49306836U, // VFNMSUB213PSZmbk 2196790484U, // VFNMSUB213PSZmbkz 49306836U, // VFNMSUB213PSZmk 2196790484U, // VFNMSUB213PSZmkz 2182110420U, // VFNMSUB213PSZr 2182110420U, // VFNMSUB213PSZrb 49306836U, // VFNMSUB213PSZrbk 2196790484U, // VFNMSUB213PSZrbkz 49306836U, // VFNMSUB213PSZrk 2196790484U, // VFNMSUB213PSZrkz 2182110420U, // VFNMSUB213PSm 2182110420U, // VFNMSUB213PSr 2182106616U, // VFNMSUB213SDZm 2182106616U, // VFNMSUB213SDZm_Int 49303032U, // VFNMSUB213SDZm_Intk 2196786680U, // VFNMSUB213SDZm_Intkz 2182106616U, // VFNMSUB213SDZr 2182106616U, // VFNMSUB213SDZr_Int 49303032U, // VFNMSUB213SDZr_Intk 2196786680U, // VFNMSUB213SDZr_Intkz 2182106616U, // VFNMSUB213SDZrb 2182106616U, // VFNMSUB213SDZrb_Int 49303032U, // VFNMSUB213SDZrb_Intk 2196786680U, // VFNMSUB213SDZrb_Intkz 2182106616U, // VFNMSUB213SDm 2182106616U, // VFNMSUB213SDm_Int 2182106616U, // VFNMSUB213SDr 2182106616U, // VFNMSUB213SDr_Int 2182111317U, // VFNMSUB213SSZm 2182111317U, // VFNMSUB213SSZm_Int 49307733U, // VFNMSUB213SSZm_Intk 2196791381U, // VFNMSUB213SSZm_Intkz 2182111317U, // VFNMSUB213SSZr 2182111317U, // VFNMSUB213SSZr_Int 49307733U, // VFNMSUB213SSZr_Intk 2196791381U, // VFNMSUB213SSZr_Intkz 2182111317U, // VFNMSUB213SSZrb 2182111317U, // VFNMSUB213SSZrb_Int 49307733U, // VFNMSUB213SSZrb_Intk 2196791381U, // VFNMSUB213SSZrb_Intkz 2182111317U, // VFNMSUB213SSm 2182111317U, // VFNMSUB213SSm_Int 2182111317U, // VFNMSUB213SSr 2182111317U, // VFNMSUB213SSr_Int 2182105354U, // VFNMSUB231PDYm 2182105354U, // VFNMSUB231PDYr 2182105354U, // VFNMSUB231PDZ128m 2182105354U, // VFNMSUB231PDZ128mb 49301770U, // VFNMSUB231PDZ128mbk 2196785418U, // VFNMSUB231PDZ128mbkz 49301770U, // VFNMSUB231PDZ128mk 2196785418U, // VFNMSUB231PDZ128mkz 2182105354U, // VFNMSUB231PDZ128r 49301770U, // VFNMSUB231PDZ128rk 2196785418U, // VFNMSUB231PDZ128rkz 2182105354U, // VFNMSUB231PDZ256m 2182105354U, // VFNMSUB231PDZ256mb 49301770U, // VFNMSUB231PDZ256mbk 2196785418U, // VFNMSUB231PDZ256mbkz 49301770U, // VFNMSUB231PDZ256mk 2196785418U, // VFNMSUB231PDZ256mkz 2182105354U, // VFNMSUB231PDZ256r 49301770U, // VFNMSUB231PDZ256rk 2196785418U, // VFNMSUB231PDZ256rkz 2182105354U, // VFNMSUB231PDZm 2182105354U, // VFNMSUB231PDZmb 49301770U, // VFNMSUB231PDZmbk 2196785418U, // VFNMSUB231PDZmbkz 49301770U, // VFNMSUB231PDZmk 2196785418U, // VFNMSUB231PDZmkz 2182105354U, // VFNMSUB231PDZr 2182105354U, // VFNMSUB231PDZrb 49301770U, // VFNMSUB231PDZrbk 2196785418U, // VFNMSUB231PDZrbkz 49301770U, // VFNMSUB231PDZrk 2196785418U, // VFNMSUB231PDZrkz 2182105354U, // VFNMSUB231PDm 2182105354U, // VFNMSUB231PDr 2182110127U, // VFNMSUB231PSYm 2182110127U, // VFNMSUB231PSYr 2182110127U, // VFNMSUB231PSZ128m 2182110127U, // VFNMSUB231PSZ128mb 49306543U, // VFNMSUB231PSZ128mbk 2196790191U, // VFNMSUB231PSZ128mbkz 49306543U, // VFNMSUB231PSZ128mk 2196790191U, // VFNMSUB231PSZ128mkz 2182110127U, // VFNMSUB231PSZ128r 49306543U, // VFNMSUB231PSZ128rk 2196790191U, // VFNMSUB231PSZ128rkz 2182110127U, // VFNMSUB231PSZ256m 2182110127U, // VFNMSUB231PSZ256mb 49306543U, // VFNMSUB231PSZ256mbk 2196790191U, // VFNMSUB231PSZ256mbkz 49306543U, // VFNMSUB231PSZ256mk 2196790191U, // VFNMSUB231PSZ256mkz 2182110127U, // VFNMSUB231PSZ256r 49306543U, // VFNMSUB231PSZ256rk 2196790191U, // VFNMSUB231PSZ256rkz 2182110127U, // VFNMSUB231PSZm 2182110127U, // VFNMSUB231PSZmb 49306543U, // VFNMSUB231PSZmbk 2196790191U, // VFNMSUB231PSZmbkz 49306543U, // VFNMSUB231PSZmk 2196790191U, // VFNMSUB231PSZmkz 2182110127U, // VFNMSUB231PSZr 2182110127U, // VFNMSUB231PSZrb 49306543U, // VFNMSUB231PSZrbk 2196790191U, // VFNMSUB231PSZrbkz 49306543U, // VFNMSUB231PSZrk 2196790191U, // VFNMSUB231PSZrkz 2182110127U, // VFNMSUB231PSm 2182110127U, // VFNMSUB231PSr 2182106474U, // VFNMSUB231SDZm 2182106474U, // VFNMSUB231SDZm_Int 49302890U, // VFNMSUB231SDZm_Intk 2196786538U, // VFNMSUB231SDZm_Intkz 2182106474U, // VFNMSUB231SDZr 2182106474U, // VFNMSUB231SDZr_Int 49302890U, // VFNMSUB231SDZr_Intk 2196786538U, // VFNMSUB231SDZr_Intkz 2182106474U, // VFNMSUB231SDZrb 2182106474U, // VFNMSUB231SDZrb_Int 49302890U, // VFNMSUB231SDZrb_Intk 2196786538U, // VFNMSUB231SDZrb_Intkz 2182106474U, // VFNMSUB231SDm 2182106474U, // VFNMSUB231SDm_Int 2182106474U, // VFNMSUB231SDr 2182106474U, // VFNMSUB231SDr_Int 2182111175U, // VFNMSUB231SSZm 2182111175U, // VFNMSUB231SSZm_Int 49307591U, // VFNMSUB231SSZm_Intk 2196791239U, // VFNMSUB231SSZm_Intkz 2182111175U, // VFNMSUB231SSZr 2182111175U, // VFNMSUB231SSZr_Int 49307591U, // VFNMSUB231SSZr_Intk 2196791239U, // VFNMSUB231SSZr_Intkz 2182111175U, // VFNMSUB231SSZrb 2182111175U, // VFNMSUB231SSZrb_Int 49307591U, // VFNMSUB231SSZrb_Intk 2196791239U, // VFNMSUB231SSZrb_Intkz 2182111175U, // VFNMSUB231SSm 2182111175U, // VFNMSUB231SSm_Int 2182111175U, // VFNMSUB231SSr 2182111175U, // VFNMSUB231SSr_Int 2517650117U, // VFNMSUBPD4Ymr 2517650117U, // VFNMSUBPD4Yrm 2517650117U, // VFNMSUBPD4Yrr 2517650117U, // VFNMSUBPD4Yrr_REV 2517650117U, // VFNMSUBPD4mr 2517650117U, // VFNMSUBPD4rm 2517650117U, // VFNMSUBPD4rr 2517650117U, // VFNMSUBPD4rr_REV 2517654893U, // VFNMSUBPS4Ymr 2517654893U, // VFNMSUBPS4Yrm 2517654893U, // VFNMSUBPS4Yrr 2517654893U, // VFNMSUBPS4Yrr_REV 2517654893U, // VFNMSUBPS4mr 2517654893U, // VFNMSUBPS4rm 2517654893U, // VFNMSUBPS4rr 2517654893U, // VFNMSUBPS4rr_REV 2517651039U, // VFNMSUBSD4mr 2517651039U, // VFNMSUBSD4mr_Int 2517651039U, // VFNMSUBSD4rm 2517651039U, // VFNMSUBSD4rm_Int 2517651039U, // VFNMSUBSD4rr 2517651039U, // VFNMSUBSD4rr_Int 2517651039U, // VFNMSUBSD4rr_Int_REV 2517651039U, // VFNMSUBSD4rr_REV 2517655732U, // VFNMSUBSS4mr 2517655732U, // VFNMSUBSS4mr_Int 2517655732U, // VFNMSUBSS4rm 2517655732U, // VFNMSUBSS4rm_Int 2517655732U, // VFNMSUBSS4rr 2517655732U, // VFNMSUBSS4rr_Int 2517655732U, // VFNMSUBSS4rr_Int_REV 2517655732U, // VFNMSUBSS4rr_REV 2819640387U, // VFPCLASSPDZ128rm 2752531523U, // VFPCLASSPDZ128rmb 384846915U, // VFPCLASSPDZ128rmbk 384846915U, // VFPCLASSPDZ128rmk 2517650499U, // VFPCLASSPDZ128rr 384846915U, // VFPCLASSPDZ128rrk 3155184707U, // VFPCLASSPDZ256rm 605047875U, // VFPCLASSPDZ256rmb 384846915U, // VFPCLASSPDZ256rmbk 384846915U, // VFPCLASSPDZ256rmk 2517650499U, // VFPCLASSPDZ256rr 384846915U, // VFPCLASSPDZ256rrk 3255848003U, // VFPCLASSPDZrm 2752531523U, // VFPCLASSPDZrmb 384846915U, // VFPCLASSPDZrmbk 384846915U, // VFPCLASSPDZrmk 2517650499U, // VFPCLASSPDZrr 384846915U, // VFPCLASSPDZrrk 2819645206U, // VFPCLASSPSZ128rm 638607126U, // VFPCLASSPSZ128rmb 384851734U, // VFPCLASSPSZ128rmbk 384851734U, // VFPCLASSPSZ128rmk 2517655318U, // VFPCLASSPSZ128rr 384851734U, // VFPCLASSPSZ128rrk 3155189526U, // VFPCLASSPSZ256rm 2786090774U, // VFPCLASSPSZ256rmb 384851734U, // VFPCLASSPSZ256rmbk 384851734U, // VFPCLASSPSZ256rmk 2517655318U, // VFPCLASSPSZ256rr 384851734U, // VFPCLASSPSZ256rrk 3255852822U, // VFPCLASSPSZrm 638607126U, // VFPCLASSPSZrmb 384851734U, // VFPCLASSPSZrmbk 384851734U, // VFPCLASSPSZrmk 2517655318U, // VFPCLASSPSZrr 384851734U, // VFPCLASSPSZrrk 2752532269U, // VFPCLASSSDZrm 384847661U, // VFPCLASSSDZrmk 2517651245U, // VFPCLASSSDZrr 384847661U, // VFPCLASSSDZrrk 2786091389U, // VFPCLASSSSZrm 384852349U, // VFPCLASSSSZrmk 2517655933U, // VFPCLASSSSZrr 384852349U, // VFPCLASSSSZrrk 1007701189U, // VFRCZPDYrm 370166981U, // VFRCZPDYrr 672156869U, // VFRCZPDrm 370166981U, // VFRCZPDrr 1007706024U, // VFRCZPSYrm 370171816U, // VFRCZPSYrr 672161704U, // VFRCZPSrm 370171816U, // VFRCZPSrr 605048749U, // VFRCZSDrm 370167725U, // VFRCZSDrr 638607831U, // VFRCZSSrm 370172375U, // VFRCZSSrr 1141918514U, // VGATHERDPDYrm 3337636658U, // VGATHERDPDZ128rm 1190153010U, // VGATHERDPDZ256rm 3337636658U, // VGATHERDPDZrm 1209027378U, // VGATHERDPDrm 1141923313U, // VGATHERDPSYrm 3337641457U, // VGATHERDPSZ128rm 1190157809U, // VGATHERDPSZ256rm 3337641457U, // VGATHERDPSZrm 1209032177U, // VGATHERDPSrm 822112218U, // VGATHERPF0DPDm 822112350U, // VGATHERPF0DPSm 822112284U, // VGATHERPF0QPDm 1056993440U, // VGATHERPF0QPSm 822112251U, // VGATHERPF1DPDm 822112383U, // VGATHERPF1DPSm 822112317U, // VGATHERPF1QPDm 1056993473U, // VGATHERPF1QPSm 1141918747U, // VGATHERQPDYrm 3337636891U, // VGATHERQPDZ128rm 1190153243U, // VGATHERQPDZ256rm 3337636891U, // VGATHERQPDZrm 1209027611U, // VGATHERQPDrm 1209032430U, // VGATHERQPSYrm 1190158062U, // VGATHERQPSZ128rm 3337641710U, // VGATHERQPSZ256rm 1190158062U, // VGATHERQPSZrm 1242586862U, // VGATHERQPSrm 672156688U, // VGETEXPPDZ128m 605047824U, // VGETEXPPDZ128mb 49302544U, // VGETEXPPDZ128mbk 2532330512U, // VGETEXPPDZ128mbkz 49302544U, // VGETEXPPDZ128mk 2532330512U, // VGETEXPPDZ128mkz 370166800U, // VGETEXPPDZ128r 49302544U, // VGETEXPPDZ128rk 2532330512U, // VGETEXPPDZ128rkz 1007701008U, // VGETEXPPDZ256m 2752531472U, // VGETEXPPDZ256mb 49302544U, // VGETEXPPDZ256mbk 2532330512U, // VGETEXPPDZ256mbkz 49302544U, // VGETEXPPDZ256mk 2532330512U, // VGETEXPPDZ256mkz 370166800U, // VGETEXPPDZ256r 49302544U, // VGETEXPPDZ256rk 2532330512U, // VGETEXPPDZ256rkz 1108364304U, // VGETEXPPDZm 605047824U, // VGETEXPPDZmb 49302544U, // VGETEXPPDZmbk 2532330512U, // VGETEXPPDZmbkz 49302544U, // VGETEXPPDZmk 2532330512U, // VGETEXPPDZmkz 370166800U, // VGETEXPPDZr 2517650448U, // VGETEXPPDZrb 49302544U, // VGETEXPPDZrbk 2532330512U, // VGETEXPPDZrbkz 49302544U, // VGETEXPPDZrk 2532330512U, // VGETEXPPDZrkz 672161507U, // VGETEXPPSZ128m 2786090723U, // VGETEXPPSZ128mb 49307363U, // VGETEXPPSZ128mbk 2532335331U, // VGETEXPPSZ128mbkz 49307363U, // VGETEXPPSZ128mk 2532335331U, // VGETEXPPSZ128mkz 370171619U, // VGETEXPPSZ128r 49307363U, // VGETEXPPSZ128rk 2532335331U, // VGETEXPPSZ128rkz 1007705827U, // VGETEXPPSZ256m 638607075U, // VGETEXPPSZ256mb 49307363U, // VGETEXPPSZ256mbk 2532335331U, // VGETEXPPSZ256mbkz 49307363U, // VGETEXPPSZ256mk 2532335331U, // VGETEXPPSZ256mkz 370171619U, // VGETEXPPSZ256r 49307363U, // VGETEXPPSZ256rk 2532335331U, // VGETEXPPSZ256rkz 1108369123U, // VGETEXPPSZm 2786090723U, // VGETEXPPSZmb 49307363U, // VGETEXPPSZmbk 2532335331U, // VGETEXPPSZmbkz 49307363U, // VGETEXPPSZmk 2532335331U, // VGETEXPPSZmkz 370171619U, // VGETEXPPSZr 2517655267U, // VGETEXPPSZrb 49307363U, // VGETEXPPSZrbk 2532335331U, // VGETEXPPSZrbkz 49307363U, // VGETEXPPSZrk 2532335331U, // VGETEXPPSZrkz 2517651214U, // VGETEXPSDZm 49303310U, // VGETEXPSDZmk 2532331278U, // VGETEXPSDZmkz 2517651214U, // VGETEXPSDZr 2517651214U, // VGETEXPSDZrb 49303310U, // VGETEXPSDZrbk 2532331278U, // VGETEXPSDZrbkz 49303310U, // VGETEXPSDZrk 2532331278U, // VGETEXPSDZrkz 2517655922U, // VGETEXPSSZm 49308018U, // VGETEXPSSZmk 2532335986U, // VGETEXPSSZmkz 2517655922U, // VGETEXPSSZr 2517655922U, // VGETEXPSSZrb 49308018U, // VGETEXPSSZrbk 2532335986U, // VGETEXPSSZrbkz 49308018U, // VGETEXPSSZrk 2532335986U, // VGETEXPSSZrkz 2752531565U, // VGETMANTPDZ128rmbi 49302637U, // VGETMANTPDZ128rmbik 2532330605U, // VGETMANTPDZ128rmbikz 2819640429U, // VGETMANTPDZ128rmi 49302637U, // VGETMANTPDZ128rmik 2532330605U, // VGETMANTPDZ128rmikz 2517650541U, // VGETMANTPDZ128rri 49302637U, // VGETMANTPDZ128rrik 2532330605U, // VGETMANTPDZ128rrikz 605047917U, // VGETMANTPDZ256rmbi 49302637U, // VGETMANTPDZ256rmbik 2532330605U, // VGETMANTPDZ256rmbikz 3155184749U, // VGETMANTPDZ256rmi 49302637U, // VGETMANTPDZ256rmik 2532330605U, // VGETMANTPDZ256rmikz 2517650541U, // VGETMANTPDZ256rri 49302637U, // VGETMANTPDZ256rrik 2532330605U, // VGETMANTPDZ256rrikz 2752531565U, // VGETMANTPDZrmbi 49302637U, // VGETMANTPDZrmbik 2532330605U, // VGETMANTPDZrmbikz 3255848045U, // VGETMANTPDZrmi 49302637U, // VGETMANTPDZrmik 2532330605U, // VGETMANTPDZrmikz 2517650541U, // VGETMANTPDZrri 370166893U, // VGETMANTPDZrrib 49302637U, // VGETMANTPDZrribk 2532330605U, // VGETMANTPDZrribkz 49302637U, // VGETMANTPDZrrik 2532330605U, // VGETMANTPDZrrikz 638607163U, // VGETMANTPSZ128rmbi 49307451U, // VGETMANTPSZ128rmbik 2532335419U, // VGETMANTPSZ128rmbikz 2819645243U, // VGETMANTPSZ128rmi 49307451U, // VGETMANTPSZ128rmik 2532335419U, // VGETMANTPSZ128rmikz 2517655355U, // VGETMANTPSZ128rri 49307451U, // VGETMANTPSZ128rrik 2532335419U, // VGETMANTPSZ128rrikz 2786090811U, // VGETMANTPSZ256rmbi 49307451U, // VGETMANTPSZ256rmbik 2532335419U, // VGETMANTPSZ256rmbikz 3155189563U, // VGETMANTPSZ256rmi 49307451U, // VGETMANTPSZ256rmik 2532335419U, // VGETMANTPSZ256rmikz 2517655355U, // VGETMANTPSZ256rri 49307451U, // VGETMANTPSZ256rrik 2532335419U, // VGETMANTPSZ256rrikz 638607163U, // VGETMANTPSZrmbi 49307451U, // VGETMANTPSZrmbik 2532335419U, // VGETMANTPSZrmbikz 3255852859U, // VGETMANTPSZrmi 49307451U, // VGETMANTPSZrmik 2532335419U, // VGETMANTPSZrmikz 2517655355U, // VGETMANTPSZrri 370171707U, // VGETMANTPSZrrib 49307451U, // VGETMANTPSZrribk 2532335419U, // VGETMANTPSZrribkz 49307451U, // VGETMANTPSZrrik 2532335419U, // VGETMANTPSZrrikz 2517651286U, // VGETMANTSDZrmi 49303382U, // VGETMANTSDZrmik 2532331350U, // VGETMANTSDZrmikz 2517651286U, // VGETMANTSDZrri 2517651286U, // VGETMANTSDZrrib 49303382U, // VGETMANTSDZrribk 2532331350U, // VGETMANTSDZrribkz 49303382U, // VGETMANTSDZrrik 2532331350U, // VGETMANTSDZrrikz 2517655945U, // VGETMANTSSZrmi 49308041U, // VGETMANTSSZrmik 2532336009U, // VGETMANTSSZrmikz 2517655945U, // VGETMANTSSZrri 2517655945U, // VGETMANTSSZrrib 49308041U, // VGETMANTSSZrribk 2532336009U, // VGETMANTSSZrribkz 49308041U, // VGETMANTSSZrrik 2532336009U, // VGETMANTSSZrrikz 2517648635U, // VGF2P8AFFINEINVQBYrmi 2517648635U, // VGF2P8AFFINEINVQBYrri 2517648635U, // VGF2P8AFFINEINVQBZ128rmbi 49300731U, // VGF2P8AFFINEINVQBZ128rmbik 2532328699U, // VGF2P8AFFINEINVQBZ128rmbikz 2517648635U, // VGF2P8AFFINEINVQBZ128rmi 49300731U, // VGF2P8AFFINEINVQBZ128rmik 2532328699U, // VGF2P8AFFINEINVQBZ128rmikz 2517648635U, // VGF2P8AFFINEINVQBZ128rri 49300731U, // VGF2P8AFFINEINVQBZ128rrik 2532328699U, // VGF2P8AFFINEINVQBZ128rrikz 2517648635U, // VGF2P8AFFINEINVQBZ256rmbi 49300731U, // VGF2P8AFFINEINVQBZ256rmbik 2532328699U, // VGF2P8AFFINEINVQBZ256rmbikz 2517648635U, // VGF2P8AFFINEINVQBZ256rmi 49300731U, // VGF2P8AFFINEINVQBZ256rmik 2532328699U, // VGF2P8AFFINEINVQBZ256rmikz 2517648635U, // VGF2P8AFFINEINVQBZ256rri 49300731U, // VGF2P8AFFINEINVQBZ256rrik 2532328699U, // VGF2P8AFFINEINVQBZ256rrikz 2517648635U, // VGF2P8AFFINEINVQBZrmbi 49300731U, // VGF2P8AFFINEINVQBZrmbik 2532328699U, // VGF2P8AFFINEINVQBZrmbikz 2517648635U, // VGF2P8AFFINEINVQBZrmi 49300731U, // VGF2P8AFFINEINVQBZrmik 2532328699U, // VGF2P8AFFINEINVQBZrmikz 2517648635U, // VGF2P8AFFINEINVQBZrri 49300731U, // VGF2P8AFFINEINVQBZrrik 2532328699U, // VGF2P8AFFINEINVQBZrrikz 2517648635U, // VGF2P8AFFINEINVQBrmi 2517648635U, // VGF2P8AFFINEINVQBrri 2517648572U, // VGF2P8AFFINEQBYrmi 2517648572U, // VGF2P8AFFINEQBYrri 2517648572U, // VGF2P8AFFINEQBZ128rmbi 49300668U, // VGF2P8AFFINEQBZ128rmbik 2532328636U, // VGF2P8AFFINEQBZ128rmbikz 2517648572U, // VGF2P8AFFINEQBZ128rmi 49300668U, // VGF2P8AFFINEQBZ128rmik 2532328636U, // VGF2P8AFFINEQBZ128rmikz 2517648572U, // VGF2P8AFFINEQBZ128rri 49300668U, // VGF2P8AFFINEQBZ128rrik 2532328636U, // VGF2P8AFFINEQBZ128rrikz 2517648572U, // VGF2P8AFFINEQBZ256rmbi 49300668U, // VGF2P8AFFINEQBZ256rmbik 2532328636U, // VGF2P8AFFINEQBZ256rmbikz 2517648572U, // VGF2P8AFFINEQBZ256rmi 49300668U, // VGF2P8AFFINEQBZ256rmik 2532328636U, // VGF2P8AFFINEQBZ256rmikz 2517648572U, // VGF2P8AFFINEQBZ256rri 49300668U, // VGF2P8AFFINEQBZ256rrik 2532328636U, // VGF2P8AFFINEQBZ256rrikz 2517648572U, // VGF2P8AFFINEQBZrmbi 49300668U, // VGF2P8AFFINEQBZrmbik 2532328636U, // VGF2P8AFFINEQBZrmbikz 2517648572U, // VGF2P8AFFINEQBZrmi 49300668U, // VGF2P8AFFINEQBZrmik 2532328636U, // VGF2P8AFFINEQBZrmikz 2517648572U, // VGF2P8AFFINEQBZrri 49300668U, // VGF2P8AFFINEQBZrrik 2532328636U, // VGF2P8AFFINEQBZrrikz 2517648572U, // VGF2P8AFFINEQBrmi 2517648572U, // VGF2P8AFFINEQBrri 2517648473U, // VGF2P8MULBYrm 2517648473U, // VGF2P8MULBYrr 2517648473U, // VGF2P8MULBZ128rm 49300569U, // VGF2P8MULBZ128rmk 2532328537U, // VGF2P8MULBZ128rmkz 2517648473U, // VGF2P8MULBZ128rr 49300569U, // VGF2P8MULBZ128rrk 2532328537U, // VGF2P8MULBZ128rrkz 2517648473U, // VGF2P8MULBZ256rm 49300569U, // VGF2P8MULBZ256rmk 2532328537U, // VGF2P8MULBZ256rmkz 2517648473U, // VGF2P8MULBZ256rr 49300569U, // VGF2P8MULBZ256rrk 2532328537U, // VGF2P8MULBZ256rrkz 2517648473U, // VGF2P8MULBZrm 49300569U, // VGF2P8MULBZrmk 2532328537U, // VGF2P8MULBZrmkz 2517648473U, // VGF2P8MULBZrr 49300569U, // VGF2P8MULBZrrk 2532328537U, // VGF2P8MULBZrrkz 2517648473U, // VGF2P8MULBrm 2517648473U, // VGF2P8MULBrr 2517650149U, // VHADDPDYrm 2517650149U, // VHADDPDYrr 2517650149U, // VHADDPDrm 2517650149U, // VHADDPDrr 2517654925U, // VHADDPSYrm 2517654925U, // VHADDPSYrr 2517654925U, // VHADDPSrm 2517654925U, // VHADDPSrr 2517650098U, // VHSUBPDYrm 2517650098U, // VHSUBPDYrr 2517650098U, // VHSUBPDrm 2517650098U, // VHSUBPDrr 2517654874U, // VHSUBPSYrm 2517654874U, // VHSUBPSYrr 2517654874U, // VHSUBPSrm 2517654874U, // VHSUBPSrr 2517648018U, // VINSERTF128rm 2517648018U, // VINSERTF128rr 2517647800U, // VINSERTF32x4Z256rm 49299896U, // VINSERTF32x4Z256rmk 2532327864U, // VINSERTF32x4Z256rmkz 2517647800U, // VINSERTF32x4Z256rr 49299896U, // VINSERTF32x4Z256rrk 2532327864U, // VINSERTF32x4Z256rrkz 2517647800U, // VINSERTF32x4Zrm 49299896U, // VINSERTF32x4Zrmk 2532327864U, // VINSERTF32x4Zrmkz 2517647800U, // VINSERTF32x4Zrr 49299896U, // VINSERTF32x4Zrrk 2532327864U, // VINSERTF32x4Zrrkz 2517648127U, // VINSERTF32x8Zrm 49300223U, // VINSERTF32x8Zrmk 2532328191U, // VINSERTF32x8Zrmkz 2517648127U, // VINSERTF32x8Zrr 49300223U, // VINSERTF32x8Zrrk 2532328191U, // VINSERTF32x8Zrrkz 2517647587U, // VINSERTF64x2Z256rm 49299683U, // VINSERTF64x2Z256rmk 2532327651U, // VINSERTF64x2Z256rmkz 2517647587U, // VINSERTF64x2Z256rr 49299683U, // VINSERTF64x2Z256rrk 2532327651U, // VINSERTF64x2Z256rrkz 2517647587U, // VINSERTF64x2Zrm 49299683U, // VINSERTF64x2Zrmk 2532327651U, // VINSERTF64x2Zrmkz 2517647587U, // VINSERTF64x2Zrr 49299683U, // VINSERTF64x2Zrrk 2532327651U, // VINSERTF64x2Zrrkz 2517647904U, // VINSERTF64x4Zrm 49300000U, // VINSERTF64x4Zrmk 2532327968U, // VINSERTF64x4Zrmkz 2517647904U, // VINSERTF64x4Zrr 49300000U, // VINSERTF64x4Zrrk 2532327968U, // VINSERTF64x4Zrrkz 2517648073U, // VINSERTI128rm 2517648073U, // VINSERTI128rr 2517647858U, // VINSERTI32x4Z256rm 49299954U, // VINSERTI32x4Z256rmk 2532327922U, // VINSERTI32x4Z256rmkz 2517647858U, // VINSERTI32x4Z256rr 49299954U, // VINSERTI32x4Z256rrk 2532327922U, // VINSERTI32x4Z256rrkz 2517647858U, // VINSERTI32x4Zrm 49299954U, // VINSERTI32x4Zrmk 2532327922U, // VINSERTI32x4Zrmkz 2517647858U, // VINSERTI32x4Zrr 49299954U, // VINSERTI32x4Zrrk 2532327922U, // VINSERTI32x4Zrrkz 2517648173U, // VINSERTI32x8Zrm 49300269U, // VINSERTI32x8Zrmk 2532328237U, // VINSERTI32x8Zrmkz 2517648173U, // VINSERTI32x8Zrr 49300269U, // VINSERTI32x8Zrrk 2532328237U, // VINSERTI32x8Zrrkz 2517647645U, // VINSERTI64x2Z256rm 49299741U, // VINSERTI64x2Z256rmk 2532327709U, // VINSERTI64x2Z256rmkz 2517647645U, // VINSERTI64x2Z256rr 49299741U, // VINSERTI64x2Z256rrk 2532327709U, // VINSERTI64x2Z256rrkz 2517647645U, // VINSERTI64x2Zrm 49299741U, // VINSERTI64x2Zrmk 2532327709U, // VINSERTI64x2Zrmkz 2517647645U, // VINSERTI64x2Zrr 49299741U, // VINSERTI64x2Zrrk 2532327709U, // VINSERTI64x2Zrrkz 2517647950U, // VINSERTI64x4Zrm 49300046U, // VINSERTI64x4Zrmk 2532328014U, // VINSERTI64x4Zrmkz 2517647950U, // VINSERTI64x4Zrr 49300046U, // VINSERTI64x4Zrrk 2532328014U, // VINSERTI64x4Zrrkz 2517655377U, // VINSERTPSZrm 2517655377U, // VINSERTPSZrr 2517655377U, // VINSERTPSrm 2517655377U, // VINSERTPSrr 1041261273U, // VLDDQUYrm 336618201U, // VLDDQUrm 72423U, // VLDMXCSR 370172641U, // VMASKMOVDQU 370172641U, // VMASKMOVDQU64 2149125297U, // VMASKMOVPDYmr 2517650609U, // VMASKMOVPDYrm 2149059761U, // VMASKMOVPDmr 2517650609U, // VMASKMOVPDrm 2149130132U, // VMASKMOVPSYmr 2517655444U, // VMASKMOVPSYrm 2149064596U, // VMASKMOVPSmr 2517655444U, // VMASKMOVPSrm 2517650621U, // VMAXCPDYrm 2517650621U, // VMAXCPDYrr 2517650621U, // VMAXCPDZ128rm 2517650621U, // VMAXCPDZ128rmb 49302717U, // VMAXCPDZ128rmbk 2532330685U, // VMAXCPDZ128rmbkz 49302717U, // VMAXCPDZ128rmk 2532330685U, // VMAXCPDZ128rmkz 2517650621U, // VMAXCPDZ128rr 49302717U, // VMAXCPDZ128rrk 2532330685U, // VMAXCPDZ128rrkz 2517650621U, // VMAXCPDZ256rm 2517650621U, // VMAXCPDZ256rmb 49302717U, // VMAXCPDZ256rmbk 2532330685U, // VMAXCPDZ256rmbkz 49302717U, // VMAXCPDZ256rmk 2532330685U, // VMAXCPDZ256rmkz 2517650621U, // VMAXCPDZ256rr 49302717U, // VMAXCPDZ256rrk 2532330685U, // VMAXCPDZ256rrkz 2517650621U, // VMAXCPDZrm 2517650621U, // VMAXCPDZrmb 49302717U, // VMAXCPDZrmbk 2532330685U, // VMAXCPDZrmbkz 49302717U, // VMAXCPDZrmk 2532330685U, // VMAXCPDZrmkz 2517650621U, // VMAXCPDZrr 49302717U, // VMAXCPDZrrk 2532330685U, // VMAXCPDZrrkz 2517650621U, // VMAXCPDrm 2517650621U, // VMAXCPDrr 2517655456U, // VMAXCPSYrm 2517655456U, // VMAXCPSYrr 2517655456U, // VMAXCPSZ128rm 2517655456U, // VMAXCPSZ128rmb 49307552U, // VMAXCPSZ128rmbk 2532335520U, // VMAXCPSZ128rmbkz 49307552U, // VMAXCPSZ128rmk 2532335520U, // VMAXCPSZ128rmkz 2517655456U, // VMAXCPSZ128rr 49307552U, // VMAXCPSZ128rrk 2532335520U, // VMAXCPSZ128rrkz 2517655456U, // VMAXCPSZ256rm 2517655456U, // VMAXCPSZ256rmb 49307552U, // VMAXCPSZ256rmbk 2532335520U, // VMAXCPSZ256rmbkz 49307552U, // VMAXCPSZ256rmk 2532335520U, // VMAXCPSZ256rmkz 2517655456U, // VMAXCPSZ256rr 49307552U, // VMAXCPSZ256rrk 2532335520U, // VMAXCPSZ256rrkz 2517655456U, // VMAXCPSZrm 2517655456U, // VMAXCPSZrmb 49307552U, // VMAXCPSZrmbk 2532335520U, // VMAXCPSZrmbkz 49307552U, // VMAXCPSZrmk 2532335520U, // VMAXCPSZrmkz 2517655456U, // VMAXCPSZrr 49307552U, // VMAXCPSZrrk 2532335520U, // VMAXCPSZrrkz 2517655456U, // VMAXCPSrm 2517655456U, // VMAXCPSrr 2517651365U, // VMAXCSDZrm 2517651365U, // VMAXCSDZrr 2517651365U, // VMAXCSDrm 2517651365U, // VMAXCSDrr 2517656015U, // VMAXCSSZrm 2517656015U, // VMAXCSSZrr 2517656015U, // VMAXCSSrm 2517656015U, // VMAXCSSrr 2517650621U, // VMAXPDYrm 2517650621U, // VMAXPDYrr 2517650621U, // VMAXPDZ128rm 2517650621U, // VMAXPDZ128rmb 49302717U, // VMAXPDZ128rmbk 2532330685U, // VMAXPDZ128rmbkz 49302717U, // VMAXPDZ128rmk 2532330685U, // VMAXPDZ128rmkz 2517650621U, // VMAXPDZ128rr 49302717U, // VMAXPDZ128rrk 2532330685U, // VMAXPDZ128rrkz 2517650621U, // VMAXPDZ256rm 2517650621U, // VMAXPDZ256rmb 49302717U, // VMAXPDZ256rmbk 2532330685U, // VMAXPDZ256rmbkz 49302717U, // VMAXPDZ256rmk 2532330685U, // VMAXPDZ256rmkz 2517650621U, // VMAXPDZ256rr 49302717U, // VMAXPDZ256rrk 2532330685U, // VMAXPDZ256rrkz 2517650621U, // VMAXPDZrm 2517650621U, // VMAXPDZrmb 49302717U, // VMAXPDZrmbk 2532330685U, // VMAXPDZrmbkz 49302717U, // VMAXPDZrmk 2532330685U, // VMAXPDZrmkz 2517650621U, // VMAXPDZrr 2517650621U, // VMAXPDZrrb 49302717U, // VMAXPDZrrbk 2532330685U, // VMAXPDZrrbkz 49302717U, // VMAXPDZrrk 2532330685U, // VMAXPDZrrkz 2517650621U, // VMAXPDrm 2517650621U, // VMAXPDrr 2517655456U, // VMAXPSYrm 2517655456U, // VMAXPSYrr 2517655456U, // VMAXPSZ128rm 2517655456U, // VMAXPSZ128rmb 49307552U, // VMAXPSZ128rmbk 2532335520U, // VMAXPSZ128rmbkz 49307552U, // VMAXPSZ128rmk 2532335520U, // VMAXPSZ128rmkz 2517655456U, // VMAXPSZ128rr 49307552U, // VMAXPSZ128rrk 2532335520U, // VMAXPSZ128rrkz 2517655456U, // VMAXPSZ256rm 2517655456U, // VMAXPSZ256rmb 49307552U, // VMAXPSZ256rmbk 2532335520U, // VMAXPSZ256rmbkz 49307552U, // VMAXPSZ256rmk 2532335520U, // VMAXPSZ256rmkz 2517655456U, // VMAXPSZ256rr 49307552U, // VMAXPSZ256rrk 2532335520U, // VMAXPSZ256rrkz 2517655456U, // VMAXPSZrm 2517655456U, // VMAXPSZrmb 49307552U, // VMAXPSZrmbk 2532335520U, // VMAXPSZrmbkz 49307552U, // VMAXPSZrmk 2532335520U, // VMAXPSZrmkz 2517655456U, // VMAXPSZrr 2517655456U, // VMAXPSZrrb 49307552U, // VMAXPSZrrbk 2532335520U, // VMAXPSZrrbkz 49307552U, // VMAXPSZrrk 2532335520U, // VMAXPSZrrkz 2517655456U, // VMAXPSrm 2517655456U, // VMAXPSrr 2517651365U, // VMAXSDZrm 2517651365U, // VMAXSDZrm_Int 49303461U, // VMAXSDZrm_Intk 2532331429U, // VMAXSDZrm_Intkz 2517651365U, // VMAXSDZrr 2517651365U, // VMAXSDZrr_Int 49303461U, // VMAXSDZrr_Intk 2532331429U, // VMAXSDZrr_Intkz 2517651365U, // VMAXSDZrrb_Int 49303461U, // VMAXSDZrrb_Intk 2532331429U, // VMAXSDZrrb_Intkz 2517651365U, // VMAXSDrm 2517651365U, // VMAXSDrm_Int 2517651365U, // VMAXSDrr 2517651365U, // VMAXSDrr_Int 2517656015U, // VMAXSSZrm 2517656015U, // VMAXSSZrm_Int 49308111U, // VMAXSSZrm_Intk 2532336079U, // VMAXSSZrm_Intkz 2517656015U, // VMAXSSZrr 2517656015U, // VMAXSSZrr_Int 49308111U, // VMAXSSZrr_Intk 2532336079U, // VMAXSSZrr_Intkz 2517656015U, // VMAXSSZrrb_Int 49308111U, // VMAXSSZrrb_Intk 2532336079U, // VMAXSSZrrb_Intkz 2517656015U, // VMAXSSrm 2517656015U, // VMAXSSrm_Int 2517656015U, // VMAXSSrr 2517656015U, // VMAXSSrr_Int 11475U, // VMCALL 88689U, // VMCLEARm 11178U, // VMFUNC 2517650425U, // VMINCPDYrm 2517650425U, // VMINCPDYrr 2517650425U, // VMINCPDZ128rm 2517650425U, // VMINCPDZ128rmb 49302521U, // VMINCPDZ128rmbk 2532330489U, // VMINCPDZ128rmbkz 49302521U, // VMINCPDZ128rmk 2532330489U, // VMINCPDZ128rmkz 2517650425U, // VMINCPDZ128rr 49302521U, // VMINCPDZ128rrk 2532330489U, // VMINCPDZ128rrkz 2517650425U, // VMINCPDZ256rm 2517650425U, // VMINCPDZ256rmb 49302521U, // VMINCPDZ256rmbk 2532330489U, // VMINCPDZ256rmbkz 49302521U, // VMINCPDZ256rmk 2532330489U, // VMINCPDZ256rmkz 2517650425U, // VMINCPDZ256rr 49302521U, // VMINCPDZ256rrk 2532330489U, // VMINCPDZ256rrkz 2517650425U, // VMINCPDZrm 2517650425U, // VMINCPDZrmb 49302521U, // VMINCPDZrmbk 2532330489U, // VMINCPDZrmbkz 49302521U, // VMINCPDZrmk 2532330489U, // VMINCPDZrmkz 2517650425U, // VMINCPDZrr 49302521U, // VMINCPDZrrk 2532330489U, // VMINCPDZrrkz 2517650425U, // VMINCPDrm 2517650425U, // VMINCPDrr 2517655236U, // VMINCPSYrm 2517655236U, // VMINCPSYrr 2517655236U, // VMINCPSZ128rm 2517655236U, // VMINCPSZ128rmb 49307332U, // VMINCPSZ128rmbk 2532335300U, // VMINCPSZ128rmbkz 49307332U, // VMINCPSZ128rmk 2532335300U, // VMINCPSZ128rmkz 2517655236U, // VMINCPSZ128rr 49307332U, // VMINCPSZ128rrk 2532335300U, // VMINCPSZ128rrkz 2517655236U, // VMINCPSZ256rm 2517655236U, // VMINCPSZ256rmb 49307332U, // VMINCPSZ256rmbk 2532335300U, // VMINCPSZ256rmbkz 49307332U, // VMINCPSZ256rmk 2532335300U, // VMINCPSZ256rmkz 2517655236U, // VMINCPSZ256rr 49307332U, // VMINCPSZ256rrk 2532335300U, // VMINCPSZ256rrkz 2517655236U, // VMINCPSZrm 2517655236U, // VMINCPSZrmb 49307332U, // VMINCPSZrmbk 2532335300U, // VMINCPSZrmbkz 49307332U, // VMINCPSZrmk 2532335300U, // VMINCPSZrmkz 2517655236U, // VMINCPSZrr 49307332U, // VMINCPSZrrk 2532335300U, // VMINCPSZrrkz 2517655236U, // VMINCPSrm 2517655236U, // VMINCPSrr 2517651191U, // VMINCSDZrm 2517651191U, // VMINCSDZrr 2517651191U, // VMINCSDrm 2517651191U, // VMINCSDrr 2517655898U, // VMINCSSZrm 2517655898U, // VMINCSSZrr 2517655898U, // VMINCSSrm 2517655898U, // VMINCSSrr 2517650425U, // VMINPDYrm 2517650425U, // VMINPDYrr 2517650425U, // VMINPDZ128rm 2517650425U, // VMINPDZ128rmb 49302521U, // VMINPDZ128rmbk 2532330489U, // VMINPDZ128rmbkz 49302521U, // VMINPDZ128rmk 2532330489U, // VMINPDZ128rmkz 2517650425U, // VMINPDZ128rr 49302521U, // VMINPDZ128rrk 2532330489U, // VMINPDZ128rrkz 2517650425U, // VMINPDZ256rm 2517650425U, // VMINPDZ256rmb 49302521U, // VMINPDZ256rmbk 2532330489U, // VMINPDZ256rmbkz 49302521U, // VMINPDZ256rmk 2532330489U, // VMINPDZ256rmkz 2517650425U, // VMINPDZ256rr 49302521U, // VMINPDZ256rrk 2532330489U, // VMINPDZ256rrkz 2517650425U, // VMINPDZrm 2517650425U, // VMINPDZrmb 49302521U, // VMINPDZrmbk 2532330489U, // VMINPDZrmbkz 49302521U, // VMINPDZrmk 2532330489U, // VMINPDZrmkz 2517650425U, // VMINPDZrr 2517650425U, // VMINPDZrrb 49302521U, // VMINPDZrrbk 2532330489U, // VMINPDZrrbkz 49302521U, // VMINPDZrrk 2532330489U, // VMINPDZrrkz 2517650425U, // VMINPDrm 2517650425U, // VMINPDrr 2517655236U, // VMINPSYrm 2517655236U, // VMINPSYrr 2517655236U, // VMINPSZ128rm 2517655236U, // VMINPSZ128rmb 49307332U, // VMINPSZ128rmbk 2532335300U, // VMINPSZ128rmbkz 49307332U, // VMINPSZ128rmk 2532335300U, // VMINPSZ128rmkz 2517655236U, // VMINPSZ128rr 49307332U, // VMINPSZ128rrk 2532335300U, // VMINPSZ128rrkz 2517655236U, // VMINPSZ256rm 2517655236U, // VMINPSZ256rmb 49307332U, // VMINPSZ256rmbk 2532335300U, // VMINPSZ256rmbkz 49307332U, // VMINPSZ256rmk 2532335300U, // VMINPSZ256rmkz 2517655236U, // VMINPSZ256rr 49307332U, // VMINPSZ256rrk 2532335300U, // VMINPSZ256rrkz 2517655236U, // VMINPSZrm 2517655236U, // VMINPSZrmb 49307332U, // VMINPSZrmbk 2532335300U, // VMINPSZrmbkz 49307332U, // VMINPSZrmk 2532335300U, // VMINPSZrmkz 2517655236U, // VMINPSZrr 2517655236U, // VMINPSZrrb 49307332U, // VMINPSZrrbk 2532335300U, // VMINPSZrrbkz 49307332U, // VMINPSZrrk 2532335300U, // VMINPSZrrkz 2517655236U, // VMINPSrm 2517655236U, // VMINPSrr 2517651191U, // VMINSDZrm 2517651191U, // VMINSDZrm_Int 49303287U, // VMINSDZrm_Intk 2532331255U, // VMINSDZrm_Intkz 2517651191U, // VMINSDZrr 2517651191U, // VMINSDZrr_Int 49303287U, // VMINSDZrr_Intk 2532331255U, // VMINSDZrr_Intkz 2517651191U, // VMINSDZrrb_Int 49303287U, // VMINSDZrrb_Intk 2532331255U, // VMINSDZrrb_Intkz 2517651191U, // VMINSDrm 2517651191U, // VMINSDrm_Int 2517651191U, // VMINSDrr 2517651191U, // VMINSDrr_Int 2517655898U, // VMINSSZrm 2517655898U, // VMINSSZrm_Int 49307994U, // VMINSSZrm_Intk 2532335962U, // VMINSSZrm_Intkz 2517655898U, // VMINSSZrr 2517655898U, // VMINSSZrr_Int 49307994U, // VMINSSZrr_Intk 2532335962U, // VMINSSZrr_Intkz 2517655898U, // VMINSSZrrb_Int 49307994U, // VMINSSZrrb_Intk 2532335962U, // VMINSSZrrb_Intkz 2517655898U, // VMINSSrm 2517655898U, // VMINSSrm_Int 2517655898U, // VMINSSrr 2517655898U, // VMINSSrr_Int 11391U, // VMLAUNCH 12061U, // VMLOAD32 12116U, // VMLOAD64 11467U, // VMMCALL 437279286U, // VMOV64toPQIZrm 370170422U, // VMOV64toPQIZrr 437279286U, // VMOV64toPQIrm 370170422U, // VMOV64toPQIrr 437279286U, // VMOV64toSDZrm 370170422U, // VMOV64toSDZrr 437279286U, // VMOV64toSDrm 370170422U, // VMOV64toSDrr 1641097U, // VMOVAPDYmr 1007700617U, // VMOVAPDYrm 370166409U, // VMOVAPDYrr 370166409U, // VMOVAPDYrr_REV 1575561U, // VMOVAPDZ128mr 16255625U, // VMOVAPDZ128mrk 672156297U, // VMOVAPDZ128rm 49302153U, // VMOVAPDZ128rmk 2532330121U, // VMOVAPDZ128rmkz 370166409U, // VMOVAPDZ128rr 370166409U, // VMOVAPDZ128rr_REV 49302153U, // VMOVAPDZ128rrk 384846473U, // VMOVAPDZ128rrk_REV 2532330121U, // VMOVAPDZ128rrkz 2532330121U, // VMOVAPDZ128rrkz_REV 1641097U, // VMOVAPDZ256mr 16321161U, // VMOVAPDZ256mrk 1007700617U, // VMOVAPDZ256rm 49302153U, // VMOVAPDZ256rmk 2532330121U, // VMOVAPDZ256rmkz 370166409U, // VMOVAPDZ256rr 370166409U, // VMOVAPDZ256rr_REV 49302153U, // VMOVAPDZ256rrk 384846473U, // VMOVAPDZ256rrk_REV 2532330121U, // VMOVAPDZ256rrkz 2532330121U, // VMOVAPDZ256rrkz_REV 1657481U, // VMOVAPDZmr 16337545U, // VMOVAPDZmrk 1108363913U, // VMOVAPDZrm 49302153U, // VMOVAPDZrmk 2532330121U, // VMOVAPDZrmkz 370166409U, // VMOVAPDZrr 370166409U, // VMOVAPDZrr_REV 49302153U, // VMOVAPDZrrk 384846473U, // VMOVAPDZrrk_REV 2532330121U, // VMOVAPDZrrkz 2532330121U, // VMOVAPDZrrkz_REV 1575561U, // VMOVAPDmr 672156297U, // VMOVAPDrm 370166409U, // VMOVAPDrr 370166409U, // VMOVAPDrr_REV 1645881U, // VMOVAPSYmr 1007705401U, // VMOVAPSYrm 370171193U, // VMOVAPSYrr 370171193U, // VMOVAPSYrr_REV 1580345U, // VMOVAPSZ128mr 16260409U, // VMOVAPSZ128mrk 672161081U, // VMOVAPSZ128rm 49306937U, // VMOVAPSZ128rmk 2532334905U, // VMOVAPSZ128rmkz 370171193U, // VMOVAPSZ128rr 370171193U, // VMOVAPSZ128rr_REV 49306937U, // VMOVAPSZ128rrk 384851257U, // VMOVAPSZ128rrk_REV 2532334905U, // VMOVAPSZ128rrkz 2532334905U, // VMOVAPSZ128rrkz_REV 1645881U, // VMOVAPSZ256mr 16325945U, // VMOVAPSZ256mrk 1007705401U, // VMOVAPSZ256rm 49306937U, // VMOVAPSZ256rmk 2532334905U, // VMOVAPSZ256rmkz 370171193U, // VMOVAPSZ256rr 370171193U, // VMOVAPSZ256rr_REV 49306937U, // VMOVAPSZ256rrk 384851257U, // VMOVAPSZ256rrk_REV 2532334905U, // VMOVAPSZ256rrkz 2532334905U, // VMOVAPSZ256rrkz_REV 1662265U, // VMOVAPSZmr 16342329U, // VMOVAPSZmrk 1108368697U, // VMOVAPSZrm 49306937U, // VMOVAPSZrmk 2532334905U, // VMOVAPSZrmkz 370171193U, // VMOVAPSZrr 370171193U, // VMOVAPSZrr_REV 49306937U, // VMOVAPSZrrk 384851257U, // VMOVAPSZrrk_REV 2532334905U, // VMOVAPSZrrkz 2532334905U, // VMOVAPSZrrkz_REV 1580345U, // VMOVAPSmr 672161081U, // VMOVAPSrm 370171193U, // VMOVAPSrr 370171193U, // VMOVAPSrr_REV 1007703407U, // VMOVDDUPYrm 370169199U, // VMOVDDUPYrr 605050223U, // VMOVDDUPZ128rm 49304943U, // VMOVDDUPZ128rmk 2532332911U, // VMOVDDUPZ128rmkz 370169199U, // VMOVDDUPZ128rr 49304943U, // VMOVDDUPZ128rrk 2532332911U, // VMOVDDUPZ128rrkz 1007703407U, // VMOVDDUPZ256rm 49304943U, // VMOVDDUPZ256rmk 2532332911U, // VMOVDDUPZ256rmkz 370169199U, // VMOVDDUPZ256rr 49304943U, // VMOVDDUPZ256rrk 2532332911U, // VMOVDDUPZ256rrkz 1108366703U, // VMOVDDUPZrm 49304943U, // VMOVDDUPZrmk 2532332911U, // VMOVDDUPZrmkz 370169199U, // VMOVDDUPZrr 49304943U, // VMOVDDUPZrrk 2532332911U, // VMOVDDUPZrrkz 605050223U, // VMOVDDUPrm 370169199U, // VMOVDDUPrr 403722360U, // VMOVDI2PDIZrm 370167928U, // VMOVDI2PDIZrr 403722360U, // VMOVDI2PDIrm 370167928U, // VMOVDI2PDIrr 403722360U, // VMOVDI2SSZrm 370167928U, // VMOVDI2SSZrr 403722360U, // VMOVDI2SSrm 370167928U, // VMOVDI2SSrr 1196112U, // VMOVDQA32Z128mr 15876176U, // VMOVDQA32Z128mrk 336609360U, // VMOVDQA32Z128rm 49299536U, // VMOVDQA32Z128rmk 2532327504U, // VMOVDQA32Z128rmkz 370163792U, // VMOVDQA32Z128rr 370163792U, // VMOVDQA32Z128rr_REV 49299536U, // VMOVDQA32Z128rrk 384843856U, // VMOVDQA32Z128rrk_REV 2532327504U, // VMOVDQA32Z128rrkz 2532327504U, // VMOVDQA32Z128rrkz_REV 1671248U, // VMOVDQA32Z256mr 16351312U, // VMOVDQA32Z256mrk 1041252432U, // VMOVDQA32Z256rm 49299536U, // VMOVDQA32Z256rmk 2532327504U, // VMOVDQA32Z256rmkz 370163792U, // VMOVDQA32Z256rr 370163792U, // VMOVDQA32Z256rr_REV 49299536U, // VMOVDQA32Z256rrk 384843856U, // VMOVDQA32Z256rrk_REV 2532327504U, // VMOVDQA32Z256rrkz 2532327504U, // VMOVDQA32Z256rrkz_REV 1687632U, // VMOVDQA32Zmr 16367696U, // VMOVDQA32Zmrk 806371408U, // VMOVDQA32Zrm 49299536U, // VMOVDQA32Zrmk 2532327504U, // VMOVDQA32Zrmkz 370163792U, // VMOVDQA32Zrr 370163792U, // VMOVDQA32Zrr_REV 49299536U, // VMOVDQA32Zrrk 384843856U, // VMOVDQA32Zrrk_REV 2532327504U, // VMOVDQA32Zrrkz 2532327504U, // VMOVDQA32Zrrkz_REV 1196348U, // VMOVDQA64Z128mr 15876412U, // VMOVDQA64Z128mrk 336609596U, // VMOVDQA64Z128rm 49299772U, // VMOVDQA64Z128rmk 2532327740U, // VMOVDQA64Z128rmkz 370164028U, // VMOVDQA64Z128rr 370164028U, // VMOVDQA64Z128rr_REV 49299772U, // VMOVDQA64Z128rrk 384844092U, // VMOVDQA64Z128rrk_REV 2532327740U, // VMOVDQA64Z128rrkz 2532327740U, // VMOVDQA64Z128rrkz_REV 1671484U, // VMOVDQA64Z256mr 16351548U, // VMOVDQA64Z256mrk 1041252668U, // VMOVDQA64Z256rm 49299772U, // VMOVDQA64Z256rmk 2532327740U, // VMOVDQA64Z256rmkz 370164028U, // VMOVDQA64Z256rr 370164028U, // VMOVDQA64Z256rr_REV 49299772U, // VMOVDQA64Z256rrk 384844092U, // VMOVDQA64Z256rrk_REV 2532327740U, // VMOVDQA64Z256rrkz 2532327740U, // VMOVDQA64Z256rrkz_REV 1687868U, // VMOVDQA64Zmr 16367932U, // VMOVDQA64Zmrk 806371644U, // VMOVDQA64Zrm 49299772U, // VMOVDQA64Zrmk 2532327740U, // VMOVDQA64Zrmkz 370164028U, // VMOVDQA64Zrr 370164028U, // VMOVDQA64Zrr_REV 49299772U, // VMOVDQA64Zrrk 384844092U, // VMOVDQA64Zrrk_REV 2532327740U, // VMOVDQA64Zrrkz 2532327740U, // VMOVDQA64Zrrkz_REV 1672032U, // VMOVDQAYmr 1041253216U, // VMOVDQAYrm 370164576U, // VMOVDQAYrr 370164576U, // VMOVDQAYrr_REV 1196896U, // VMOVDQAmr 336610144U, // VMOVDQArm 370164576U, // VMOVDQArr 370164576U, // VMOVDQArr_REV 1196653U, // VMOVDQU16Z128mr 15876717U, // VMOVDQU16Z128mrk 336609901U, // VMOVDQU16Z128rm 49300077U, // VMOVDQU16Z128rmk 2532328045U, // VMOVDQU16Z128rmkz 370164333U, // VMOVDQU16Z128rr 370164333U, // VMOVDQU16Z128rr_REV 49300077U, // VMOVDQU16Z128rrk 384844397U, // VMOVDQU16Z128rrk_REV 2532328045U, // VMOVDQU16Z128rrkz 2532328045U, // VMOVDQU16Z128rrkz_REV 1671789U, // VMOVDQU16Z256mr 16351853U, // VMOVDQU16Z256mrk 1041252973U, // VMOVDQU16Z256rm 49300077U, // VMOVDQU16Z256rmk 2532328045U, // VMOVDQU16Z256rmkz 370164333U, // VMOVDQU16Z256rr 370164333U, // VMOVDQU16Z256rr_REV 49300077U, // VMOVDQU16Z256rrk 384844397U, // VMOVDQU16Z256rrk_REV 2532328045U, // VMOVDQU16Z256rrkz 2532328045U, // VMOVDQU16Z256rrkz_REV 1688173U, // VMOVDQU16Zmr 16368237U, // VMOVDQU16Zmrk 806371949U, // VMOVDQU16Zrm 49300077U, // VMOVDQU16Zrmk 2532328045U, // VMOVDQU16Zrmkz 370164333U, // VMOVDQU16Zrr 370164333U, // VMOVDQU16Zrr_REV 49300077U, // VMOVDQU16Zrrk 384844397U, // VMOVDQU16Zrrk_REV 2532328045U, // VMOVDQU16Zrrkz 2532328045U, // VMOVDQU16Zrrkz_REV 1196130U, // VMOVDQU32Z128mr 15876194U, // VMOVDQU32Z128mrk 336609378U, // VMOVDQU32Z128rm 49299554U, // VMOVDQU32Z128rmk 2532327522U, // VMOVDQU32Z128rmkz 370163810U, // VMOVDQU32Z128rr 370163810U, // VMOVDQU32Z128rr_REV 49299554U, // VMOVDQU32Z128rrk 384843874U, // VMOVDQU32Z128rrk_REV 2532327522U, // VMOVDQU32Z128rrkz 2532327522U, // VMOVDQU32Z128rrkz_REV 1671266U, // VMOVDQU32Z256mr 16351330U, // VMOVDQU32Z256mrk 1041252450U, // VMOVDQU32Z256rm 49299554U, // VMOVDQU32Z256rmk 2532327522U, // VMOVDQU32Z256rmkz 370163810U, // VMOVDQU32Z256rr 370163810U, // VMOVDQU32Z256rr_REV 49299554U, // VMOVDQU32Z256rrk 384843874U, // VMOVDQU32Z256rrk_REV 2532327522U, // VMOVDQU32Z256rrkz 2532327522U, // VMOVDQU32Z256rrkz_REV 1687650U, // VMOVDQU32Zmr 16367714U, // VMOVDQU32Zmrk 806371426U, // VMOVDQU32Zrm 49299554U, // VMOVDQU32Zrmk 2532327522U, // VMOVDQU32Zrmkz 370163810U, // VMOVDQU32Zrr 370163810U, // VMOVDQU32Zrr_REV 49299554U, // VMOVDQU32Zrrk 384843874U, // VMOVDQU32Zrrk_REV 2532327522U, // VMOVDQU32Zrrkz 2532327522U, // VMOVDQU32Zrrkz_REV 1196423U, // VMOVDQU64Z128mr 15876487U, // VMOVDQU64Z128mrk 336609671U, // VMOVDQU64Z128rm 49299847U, // VMOVDQU64Z128rmk 2532327815U, // VMOVDQU64Z128rmkz 370164103U, // VMOVDQU64Z128rr 370164103U, // VMOVDQU64Z128rr_REV 49299847U, // VMOVDQU64Z128rrk 384844167U, // VMOVDQU64Z128rrk_REV 2532327815U, // VMOVDQU64Z128rrkz 2532327815U, // VMOVDQU64Z128rrkz_REV 1671559U, // VMOVDQU64Z256mr 16351623U, // VMOVDQU64Z256mrk 1041252743U, // VMOVDQU64Z256rm 49299847U, // VMOVDQU64Z256rmk 2532327815U, // VMOVDQU64Z256rmkz 370164103U, // VMOVDQU64Z256rr 370164103U, // VMOVDQU64Z256rr_REV 49299847U, // VMOVDQU64Z256rrk 384844167U, // VMOVDQU64Z256rrk_REV 2532327815U, // VMOVDQU64Z256rrkz 2532327815U, // VMOVDQU64Z256rrkz_REV 1687943U, // VMOVDQU64Zmr 16368007U, // VMOVDQU64Zmrk 806371719U, // VMOVDQU64Zrm 49299847U, // VMOVDQU64Zrmk 2532327815U, // VMOVDQU64Zrmkz 370164103U, // VMOVDQU64Zrr 370164103U, // VMOVDQU64Zrr_REV 49299847U, // VMOVDQU64Zrrk 384844167U, // VMOVDQU64Zrrk_REV 2532327815U, // VMOVDQU64Zrrkz 2532327815U, // VMOVDQU64Zrrkz_REV 1196774U, // VMOVDQU8Z128mr 15876838U, // VMOVDQU8Z128mrk 336610022U, // VMOVDQU8Z128rm 49300198U, // VMOVDQU8Z128rmk 2532328166U, // VMOVDQU8Z128rmkz 370164454U, // VMOVDQU8Z128rr 370164454U, // VMOVDQU8Z128rr_REV 49300198U, // VMOVDQU8Z128rrk 384844518U, // VMOVDQU8Z128rrk_REV 2532328166U, // VMOVDQU8Z128rrkz 2532328166U, // VMOVDQU8Z128rrkz_REV 1671910U, // VMOVDQU8Z256mr 16351974U, // VMOVDQU8Z256mrk 1041253094U, // VMOVDQU8Z256rm 49300198U, // VMOVDQU8Z256rmk 2532328166U, // VMOVDQU8Z256rmkz 370164454U, // VMOVDQU8Z256rr 370164454U, // VMOVDQU8Z256rr_REV 49300198U, // VMOVDQU8Z256rrk 384844518U, // VMOVDQU8Z256rrk_REV 2532328166U, // VMOVDQU8Z256rrkz 2532328166U, // VMOVDQU8Z256rrkz_REV 1688294U, // VMOVDQU8Zmr 16368358U, // VMOVDQU8Zmrk 806372070U, // VMOVDQU8Zrm 49300198U, // VMOVDQU8Zrmk 2532328166U, // VMOVDQU8Zrmkz 370164454U, // VMOVDQU8Zrr 370164454U, // VMOVDQU8Zrr_REV 49300198U, // VMOVDQU8Zrrk 384844518U, // VMOVDQU8Zrrk_REV 2532328166U, // VMOVDQU8Zrrkz 2532328166U, // VMOVDQU8Zrrkz_REV 1680110U, // VMOVDQUYmr 1041261294U, // VMOVDQUYrm 370172654U, // VMOVDQUYrr 370172654U, // VMOVDQUYrr_REV 1204974U, // VMOVDQUmr 336618222U, // VMOVDQUrm 370172654U, // VMOVDQUrr 370172654U, // VMOVDQUrr_REV 2517655145U, // VMOVHLPSZrr 2517655145U, // VMOVHLPSrr 1182604U, // VMOVHPDZ128mr 2517650316U, // VMOVHPDZ128rm 1182604U, // VMOVHPDmr 2517650316U, // VMOVHPDrm 1187413U, // VMOVHPSZ128mr 2517655125U, // VMOVHPSZ128rm 1187413U, // VMOVHPSmr 2517655125U, // VMOVHPSrm 2517655115U, // VMOVLHPSZrr 2517655115U, // VMOVLHPSrr 1182654U, // VMOVLPDZ128mr 2517650366U, // VMOVLPDZ128rm 1182654U, // VMOVLPDmr 2517650366U, // VMOVLPDrm 1187473U, // VMOVLPSZ128mr 2517655185U, // VMOVLPSZ128rm 1187473U, // VMOVLPSmr 2517655185U, // VMOVLPSrm 370166677U, // VMOVMSKPDYrr 370166677U, // VMOVMSKPDrr 370171486U, // VMOVMSKPSYrr 370171486U, // VMOVMSKPSrr 1041253205U, // VMOVNTDQAYrm 336610133U, // VMOVNTDQAZ128rm 1041253205U, // VMOVNTDQAZ256rm 806372181U, // VMOVNTDQAZrm 336610133U, // VMOVNTDQArm 1677082U, // VMOVNTDQYmr 1201946U, // VMOVNTDQZ128mr 1677082U, // VMOVNTDQZ256mr 1693466U, // VMOVNTDQZmr 1201946U, // VMOVNTDQmr 1641593U, // VMOVNTPDYmr 1576057U, // VMOVNTPDZ128mr 1641593U, // VMOVNTPDZ256mr 1657977U, // VMOVNTPDZmr 1576057U, // VMOVNTPDmr 1646407U, // VMOVNTPSYmr 1580871U, // VMOVNTPSZ128mr 1646407U, // VMOVNTPSZ256mr 1662791U, // VMOVNTPSZmr 1580871U, // VMOVNTPSmr 1118328U, // VMOVPDI2DIZmr 370167928U, // VMOVPDI2DIZrr 1118328U, // VMOVPDI2DImr 370167928U, // VMOVPDI2DIrr 1137206U, // VMOVPQI2QIZmr 370170422U, // VMOVPQI2QIZrr 1137206U, // VMOVPQI2QImr 370170422U, // VMOVPQI2QIrr 1137206U, // VMOVPQIto64Zmr 370170422U, // VMOVPQIto64Zrr 1137206U, // VMOVPQIto64mr 370170422U, // VMOVPQIto64rr 437279286U, // VMOVQI2PQIZrm 437279286U, // VMOVQI2PQIrm 1183636U, // VMOVSDZmr 15863700U, // VMOVSDZmrk 605048724U, // VMOVSDZrm 49303444U, // VMOVSDZrmk 2532331412U, // VMOVSDZrmkz 2517651348U, // VMOVSDZrr 2517651348U, // VMOVSDZrr_REV 49303444U, // VMOVSDZrrk 49303444U, // VMOVSDZrrk_REV 2532331412U, // VMOVSDZrrkz 2532331412U, // VMOVSDZrrkz_REV 1183636U, // VMOVSDmr 605048724U, // VMOVSDrm 2517651348U, // VMOVSDrr 2517651348U, // VMOVSDrr_REV 1137206U, // VMOVSDto64Zmr 370170422U, // VMOVSDto64Zrr 1137206U, // VMOVSDto64mr 370170422U, // VMOVSDto64rr 1007703417U, // VMOVSHDUPYrm 370169209U, // VMOVSHDUPYrr 672159097U, // VMOVSHDUPZ128rm 49304953U, // VMOVSHDUPZ128rmk 2532332921U, // VMOVSHDUPZ128rmkz 370169209U, // VMOVSHDUPZ128rr 49304953U, // VMOVSHDUPZ128rrk 2532332921U, // VMOVSHDUPZ128rrkz 1007703417U, // VMOVSHDUPZ256rm 49304953U, // VMOVSHDUPZ256rmk 2532332921U, // VMOVSHDUPZ256rmkz 370169209U, // VMOVSHDUPZ256rr 49304953U, // VMOVSHDUPZ256rrk 2532332921U, // VMOVSHDUPZ256rrkz 1108366713U, // VMOVSHDUPZrm 49304953U, // VMOVSHDUPZrmk 2532332921U, // VMOVSHDUPZrmkz 370169209U, // VMOVSHDUPZrr 49304953U, // VMOVSHDUPZrrk 2532332921U, // VMOVSHDUPZrrkz 672159097U, // VMOVSHDUPrm 370169209U, // VMOVSHDUPrr 1007703428U, // VMOVSLDUPYrm 370169220U, // VMOVSLDUPYrr 672159108U, // VMOVSLDUPZ128rm 49304964U, // VMOVSLDUPZ128rmk 2532332932U, // VMOVSLDUPZ128rmkz 370169220U, // VMOVSLDUPZ128rr 49304964U, // VMOVSLDUPZ128rrk 2532332932U, // VMOVSLDUPZ128rrkz 1007703428U, // VMOVSLDUPZ256rm 49304964U, // VMOVSLDUPZ256rmk 2532332932U, // VMOVSLDUPZ256rmkz 370169220U, // VMOVSLDUPZ256rr 49304964U, // VMOVSLDUPZ256rrk 2532332932U, // VMOVSLDUPZ256rrkz 1108366724U, // VMOVSLDUPZrm 49304964U, // VMOVSLDUPZrmk 2532332932U, // VMOVSLDUPZrmkz 370169220U, // VMOVSLDUPZrr 49304964U, // VMOVSLDUPZrrk 2532332932U, // VMOVSLDUPZrrkz 672159108U, // VMOVSLDUPrm 370169220U, // VMOVSLDUPrr 1118328U, // VMOVSS2DIZmr 370167928U, // VMOVSS2DIZrr 1118328U, // VMOVSS2DImr 370167928U, // VMOVSS2DIrr 1171911U, // VMOVSSZmr 15851975U, // VMOVSSZmrk 638607815U, // VMOVSSZrm 49308103U, // VMOVSSZrmk 2532336071U, // VMOVSSZrmkz 2517656007U, // VMOVSSZrr 2517656007U, // VMOVSSZrr_REV 49308103U, // VMOVSSZrrk 49308103U, // VMOVSSZrrk_REV 2532336071U, // VMOVSSZrrkz 2532336071U, // VMOVSSZrrkz_REV 1171911U, // VMOVSSmr 638607815U, // VMOVSSrm 2517656007U, // VMOVSSrr 2517656007U, // VMOVSSrr_REV 1641621U, // VMOVUPDYmr 1007701141U, // VMOVUPDYrm 370166933U, // VMOVUPDYrr 370166933U, // VMOVUPDYrr_REV 1576085U, // VMOVUPDZ128mr 16256149U, // VMOVUPDZ128mrk 672156821U, // VMOVUPDZ128rm 49302677U, // VMOVUPDZ128rmk 2532330645U, // VMOVUPDZ128rmkz 370166933U, // VMOVUPDZ128rr 370166933U, // VMOVUPDZ128rr_REV 49302677U, // VMOVUPDZ128rrk 384846997U, // VMOVUPDZ128rrk_REV 2532330645U, // VMOVUPDZ128rrkz 2532330645U, // VMOVUPDZ128rrkz_REV 1641621U, // VMOVUPDZ256mr 16321685U, // VMOVUPDZ256mrk 1007701141U, // VMOVUPDZ256rm 49302677U, // VMOVUPDZ256rmk 2532330645U, // VMOVUPDZ256rmkz 370166933U, // VMOVUPDZ256rr 370166933U, // VMOVUPDZ256rr_REV 49302677U, // VMOVUPDZ256rrk 384846997U, // VMOVUPDZ256rrk_REV 2532330645U, // VMOVUPDZ256rrkz 2532330645U, // VMOVUPDZ256rrkz_REV 1658005U, // VMOVUPDZmr 16338069U, // VMOVUPDZmrk 1108364437U, // VMOVUPDZrm 49302677U, // VMOVUPDZrmk 2532330645U, // VMOVUPDZrmkz 370166933U, // VMOVUPDZrr 370166933U, // VMOVUPDZrr_REV 49302677U, // VMOVUPDZrrk 384846997U, // VMOVUPDZrrk_REV 2532330645U, // VMOVUPDZrrkz 2532330645U, // VMOVUPDZrrkz_REV 1576085U, // VMOVUPDmr 672156821U, // VMOVUPDrm 370166933U, // VMOVUPDrr 370166933U, // VMOVUPDrr_REV 1646456U, // VMOVUPSYmr 1007705976U, // VMOVUPSYrm 370171768U, // VMOVUPSYrr 370171768U, // VMOVUPSYrr_REV 1580920U, // VMOVUPSZ128mr 16260984U, // VMOVUPSZ128mrk 672161656U, // VMOVUPSZ128rm 49307512U, // VMOVUPSZ128rmk 2532335480U, // VMOVUPSZ128rmkz 370171768U, // VMOVUPSZ128rr 370171768U, // VMOVUPSZ128rr_REV 49307512U, // VMOVUPSZ128rrk 384851832U, // VMOVUPSZ128rrk_REV 2532335480U, // VMOVUPSZ128rrkz 2532335480U, // VMOVUPSZ128rrkz_REV 1646456U, // VMOVUPSZ256mr 16326520U, // VMOVUPSZ256mrk 1007705976U, // VMOVUPSZ256rm 49307512U, // VMOVUPSZ256rmk 2532335480U, // VMOVUPSZ256rmkz 370171768U, // VMOVUPSZ256rr 370171768U, // VMOVUPSZ256rr_REV 49307512U, // VMOVUPSZ256rrk 384851832U, // VMOVUPSZ256rrk_REV 2532335480U, // VMOVUPSZ256rrkz 2532335480U, // VMOVUPSZ256rrkz_REV 1662840U, // VMOVUPSZmr 16342904U, // VMOVUPSZmrk 1108369272U, // VMOVUPSZrm 49307512U, // VMOVUPSZrmk 2532335480U, // VMOVUPSZrmkz 370171768U, // VMOVUPSZrr 370171768U, // VMOVUPSZrr_REV 49307512U, // VMOVUPSZrrk 384851832U, // VMOVUPSZrrk_REV 2532335480U, // VMOVUPSZrrkz 2532335480U, // VMOVUPSZrrkz_REV 1580920U, // VMOVUPSmr 672161656U, // VMOVUPSrm 370171768U, // VMOVUPSrr 370171768U, // VMOVUPSrr_REV 370170422U, // VMOVZPQILo2PQIZrr 370170422U, // VMOVZPQILo2PQIrr 2517656424U, // VMPSADBWYrmi 2517656424U, // VMPSADBWYrri 2517656424U, // VMPSADBWrmi 2517656424U, // VMPSADBWrri 84081U, // VMPTRLDm 90814U, // VMPTRSTm 1115925U, // VMREAD32mr 370165525U, // VMREAD32rr 1132309U, // VMREAD64mr 370165525U, // VMREAD64rr 11293U, // VMRESUME 12083U, // VMRUN32 12138U, // VMRUN64 12072U, // VMSAVE32 12127U, // VMSAVE64 2517650358U, // VMULPDYrm 2517650358U, // VMULPDYrr 2517650358U, // VMULPDZ128rm 2517650358U, // VMULPDZ128rmb 49302454U, // VMULPDZ128rmbk 2532330422U, // VMULPDZ128rmbkz 49302454U, // VMULPDZ128rmk 2532330422U, // VMULPDZ128rmkz 2517650358U, // VMULPDZ128rr 49302454U, // VMULPDZ128rrk 2532330422U, // VMULPDZ128rrkz 2517650358U, // VMULPDZ256rm 2517650358U, // VMULPDZ256rmb 49302454U, // VMULPDZ256rmbk 2532330422U, // VMULPDZ256rmbkz 49302454U, // VMULPDZ256rmk 2532330422U, // VMULPDZ256rmkz 2517650358U, // VMULPDZ256rr 49302454U, // VMULPDZ256rrk 2532330422U, // VMULPDZ256rrkz 2517650358U, // VMULPDZrm 2517650358U, // VMULPDZrmb 49302454U, // VMULPDZrmbk 2532330422U, // VMULPDZrmbkz 49302454U, // VMULPDZrmk 2532330422U, // VMULPDZrmkz 2517650358U, // VMULPDZrr 2517650358U, // VMULPDZrrb 49302454U, // VMULPDZrrbk 2532330422U, // VMULPDZrrbkz 49302454U, // VMULPDZrrk 2532330422U, // VMULPDZrrkz 2517650358U, // VMULPDrm 2517650358U, // VMULPDrr 2517655177U, // VMULPSYrm 2517655177U, // VMULPSYrr 2517655177U, // VMULPSZ128rm 2517655177U, // VMULPSZ128rmb 49307273U, // VMULPSZ128rmbk 2532335241U, // VMULPSZ128rmbkz 49307273U, // VMULPSZ128rmk 2532335241U, // VMULPSZ128rmkz 2517655177U, // VMULPSZ128rr 49307273U, // VMULPSZ128rrk 2532335241U, // VMULPSZ128rrkz 2517655177U, // VMULPSZ256rm 2517655177U, // VMULPSZ256rmb 49307273U, // VMULPSZ256rmbk 2532335241U, // VMULPSZ256rmbkz 49307273U, // VMULPSZ256rmk 2532335241U, // VMULPSZ256rmkz 2517655177U, // VMULPSZ256rr 49307273U, // VMULPSZ256rrk 2532335241U, // VMULPSZ256rrkz 2517655177U, // VMULPSZrm 2517655177U, // VMULPSZrmb 49307273U, // VMULPSZrmbk 2532335241U, // VMULPSZrmbkz 49307273U, // VMULPSZrmk 2532335241U, // VMULPSZrmkz 2517655177U, // VMULPSZrr 2517655177U, // VMULPSZrrb 49307273U, // VMULPSZrrbk 2532335241U, // VMULPSZrrbkz 49307273U, // VMULPSZrrk 2532335241U, // VMULPSZrrkz 2517655177U, // VMULPSrm 2517655177U, // VMULPSrr 2517651161U, // VMULSDZrm 2517651161U, // VMULSDZrm_Int 49303257U, // VMULSDZrm_Intk 2532331225U, // VMULSDZrm_Intkz 2517651161U, // VMULSDZrr 2517651161U, // VMULSDZrr_Int 49303257U, // VMULSDZrr_Intk 2532331225U, // VMULSDZrr_Intkz 2517651161U, // VMULSDZrrb_Int 49303257U, // VMULSDZrrb_Intk 2532331225U, // VMULSDZrrb_Intkz 2517651161U, // VMULSDrm 2517651161U, // VMULSDrm_Int 2517651161U, // VMULSDrr 2517651161U, // VMULSDrr_Int 2517655877U, // VMULSSZrm 2517655877U, // VMULSSZrm_Int 49307973U, // VMULSSZrm_Intk 2532335941U, // VMULSSZrm_Intkz 2517655877U, // VMULSSZrr 2517655877U, // VMULSSZrr_Int 49307973U, // VMULSSZrr_Intk 2532335941U, // VMULSSZrr_Intkz 2517655877U, // VMULSSZrrb_Int 49307973U, // VMULSSZrrb_Intk 2532335941U, // VMULSSZrrb_Intkz 2517655877U, // VMULSSrm 2517655877U, // VMULSSrm_Int 2517655877U, // VMULSSrr 2517655877U, // VMULSSrr_Int 403722723U, // VMWRITE32rm 370168291U, // VMWRITE32rr 437277155U, // VMWRITE64rm 370168291U, // VMWRITE64rr 11350U, // VMXOFF 87187U, // VMXON 2517650484U, // VORPDYrm 2517650484U, // VORPDYrr 2517650484U, // VORPDZ128rm 2517650484U, // VORPDZ128rmb 49302580U, // VORPDZ128rmbk 2532330548U, // VORPDZ128rmbkz 49302580U, // VORPDZ128rmk 2532330548U, // VORPDZ128rmkz 2517650484U, // VORPDZ128rr 49302580U, // VORPDZ128rrk 2532330548U, // VORPDZ128rrkz 2517650484U, // VORPDZ256rm 2517650484U, // VORPDZ256rmb 49302580U, // VORPDZ256rmbk 2532330548U, // VORPDZ256rmbkz 49302580U, // VORPDZ256rmk 2532330548U, // VORPDZ256rmkz 2517650484U, // VORPDZ256rr 49302580U, // VORPDZ256rrk 2532330548U, // VORPDZ256rrkz 2517650484U, // VORPDZrm 2517650484U, // VORPDZrmb 49302580U, // VORPDZrmbk 2532330548U, // VORPDZrmbkz 49302580U, // VORPDZrmk 2532330548U, // VORPDZrmkz 2517650484U, // VORPDZrr 49302580U, // VORPDZrrk 2532330548U, // VORPDZrrkz 2517650484U, // VORPDrm 2517650484U, // VORPDrr 2517655303U, // VORPSYrm 2517655303U, // VORPSYrr 2517655303U, // VORPSZ128rm 2517655303U, // VORPSZ128rmb 49307399U, // VORPSZ128rmbk 2532335367U, // VORPSZ128rmbkz 49307399U, // VORPSZ128rmk 2532335367U, // VORPSZ128rmkz 2517655303U, // VORPSZ128rr 49307399U, // VORPSZ128rrk 2532335367U, // VORPSZ128rrkz 2517655303U, // VORPSZ256rm 2517655303U, // VORPSZ256rmb 49307399U, // VORPSZ256rmbk 2532335367U, // VORPSZ256rmbkz 49307399U, // VORPSZ256rmk 2532335367U, // VORPSZ256rmkz 2517655303U, // VORPSZ256rr 49307399U, // VORPSZ256rrk 2532335367U, // VORPSZ256rrkz 2517655303U, // VORPSZrm 2517655303U, // VORPSZrmb 49307399U, // VORPSZrmbk 2532335367U, // VORPSZrmbkz 49307399U, // VORPSZrmk 2532335367U, // VORPSZrmkz 2517655303U, // VORPSZrr 49307399U, // VORPSZrrk 2532335367U, // VORPSZrrkz 2517655303U, // VORPSrm 2517655303U, // VORPSrr 2182110009U, // VP4DPWSSDSrm 49306425U, // VP4DPWSSDSrmk 2196790073U, // VP4DPWSSDSrmkz 2182106945U, // VP4DPWSSDrm 49303361U, // VP4DPWSSDrmk 2196787009U, // VP4DPWSSDrmkz 1041253704U, // VPABSBYrm 370165064U, // VPABSBYrr 336610632U, // VPABSBZ128rm 49300808U, // VPABSBZ128rmk 2532328776U, // VPABSBZ128rmkz 370165064U, // VPABSBZ128rr 49300808U, // VPABSBZ128rrk 2532328776U, // VPABSBZ128rrkz 1041253704U, // VPABSBZ256rm 49300808U, // VPABSBZ256rmk 2532328776U, // VPABSBZ256rmkz 370165064U, // VPABSBZ256rr 49300808U, // VPABSBZ256rrk 2532328776U, // VPABSBZ256rrkz 806372680U, // VPABSBZrm 49300808U, // VPABSBZrmk 2532328776U, // VPABSBZrmkz 370165064U, // VPABSBZrr 49300808U, // VPABSBZrrk 2532328776U, // VPABSBZrrkz 336610632U, // VPABSBrm 370165064U, // VPABSBrr 1041256013U, // VPABSDYrm 370167373U, // VPABSDYrr 336612941U, // VPABSDZ128rm 2551205453U, // VPABSDZ128rmb 49303117U, // VPABSDZ128rmbk 2532331085U, // VPABSDZ128rmbkz 49303117U, // VPABSDZ128rmk 2532331085U, // VPABSDZ128rmkz 370167373U, // VPABSDZ128rr 49303117U, // VPABSDZ128rrk 2532331085U, // VPABSDZ128rrkz 1041256013U, // VPABSDZ256rm 403721805U, // VPABSDZ256rmb 49303117U, // VPABSDZ256rmbk 2532331085U, // VPABSDZ256rmbkz 49303117U, // VPABSDZ256rmk 2532331085U, // VPABSDZ256rmkz 370167373U, // VPABSDZ256rr 49303117U, // VPABSDZ256rrk 2532331085U, // VPABSDZ256rrkz 806374989U, // VPABSDZrm 2551205453U, // VPABSDZrmb 49303117U, // VPABSDZrmbk 2532331085U, // VPABSDZrmbkz 49303117U, // VPABSDZrmk 2532331085U, // VPABSDZrmkz 370167373U, // VPABSDZrr 49303117U, // VPABSDZrrk 2532331085U, // VPABSDZrrkz 336612941U, // VPABSDrm 370167373U, // VPABSDrr 336615678U, // VPABSQZ128rm 437278974U, // VPABSQZ128rmb 49305854U, // VPABSQZ128rmbk 2532333822U, // VPABSQZ128rmbkz 49305854U, // VPABSQZ128rmk 2532333822U, // VPABSQZ128rmkz 370170110U, // VPABSQZ128rr 49305854U, // VPABSQZ128rrk 2532333822U, // VPABSQZ128rrkz 1041258750U, // VPABSQZ256rm 2584762622U, // VPABSQZ256rmb 49305854U, // VPABSQZ256rmbk 2532333822U, // VPABSQZ256rmbkz 49305854U, // VPABSQZ256rmk 2532333822U, // VPABSQZ256rmkz 370170110U, // VPABSQZ256rr 49305854U, // VPABSQZ256rrk 2532333822U, // VPABSQZ256rrkz 806377726U, // VPABSQZrm 437278974U, // VPABSQZrmb 49305854U, // VPABSQZrmbk 2532333822U, // VPABSQZrmbkz 49305854U, // VPABSQZrmk 2532333822U, // VPABSQZrmkz 370170110U, // VPABSQZrr 49305854U, // VPABSQZrrk 2532333822U, // VPABSQZrrkz 1041261956U, // VPABSWYrm 370173316U, // VPABSWYrr 336618884U, // VPABSWZ128rm 49309060U, // VPABSWZ128rmk 2532337028U, // VPABSWZ128rmkz 370173316U, // VPABSWZ128rr 49309060U, // VPABSWZ128rrk 2532337028U, // VPABSWZ128rrkz 1041261956U, // VPABSWZ256rm 49309060U, // VPABSWZ256rmk 2532337028U, // VPABSWZ256rmkz 370173316U, // VPABSWZ256rr 49309060U, // VPABSWZ256rrk 2532337028U, // VPABSWZ256rrkz 806380932U, // VPABSWZrm 49309060U, // VPABSWZrmk 2532337028U, // VPABSWZrmkz 370173316U, // VPABSWZrr 49309060U, // VPABSWZrrk 2532337028U, // VPABSWZrrkz 336618884U, // VPABSWrm 370173316U, // VPABSWrr 2517656622U, // VPACKSSDWYrm 2517656622U, // VPACKSSDWYrr 2517656622U, // VPACKSSDWZ128rm 2517656622U, // VPACKSSDWZ128rmb 49308718U, // VPACKSSDWZ128rmbk 2532336686U, // VPACKSSDWZ128rmbkz 49308718U, // VPACKSSDWZ128rmk 2532336686U, // VPACKSSDWZ128rmkz 2517656622U, // VPACKSSDWZ128rr 49308718U, // VPACKSSDWZ128rrk 2532336686U, // VPACKSSDWZ128rrkz 2517656622U, // VPACKSSDWZ256rm 2517656622U, // VPACKSSDWZ256rmb 49308718U, // VPACKSSDWZ256rmbk 2532336686U, // VPACKSSDWZ256rmbkz 49308718U, // VPACKSSDWZ256rmk 2532336686U, // VPACKSSDWZ256rmkz 2517656622U, // VPACKSSDWZ256rr 49308718U, // VPACKSSDWZ256rrk 2532336686U, // VPACKSSDWZ256rrkz 2517656622U, // VPACKSSDWZrm 2517656622U, // VPACKSSDWZrmb 49308718U, // VPACKSSDWZrmbk 2532336686U, // VPACKSSDWZrmbkz 49308718U, // VPACKSSDWZrmk 2532336686U, // VPACKSSDWZrmkz 2517656622U, // VPACKSSDWZrr 49308718U, // VPACKSSDWZrrk 2532336686U, // VPACKSSDWZrrkz 2517656622U, // VPACKSSDWrm 2517656622U, // VPACKSSDWrr 2517648973U, // VPACKSSWBYrm 2517648973U, // VPACKSSWBYrr 2517648973U, // VPACKSSWBZ128rm 49301069U, // VPACKSSWBZ128rmk 2532329037U, // VPACKSSWBZ128rmkz 2517648973U, // VPACKSSWBZ128rr 49301069U, // VPACKSSWBZ128rrk 2532329037U, // VPACKSSWBZ128rrkz 2517648973U, // VPACKSSWBZ256rm 49301069U, // VPACKSSWBZ256rmk 2532329037U, // VPACKSSWBZ256rmkz 2517648973U, // VPACKSSWBZ256rr 49301069U, // VPACKSSWBZ256rrk 2532329037U, // VPACKSSWBZ256rrkz 2517648973U, // VPACKSSWBZrm 49301069U, // VPACKSSWBZrmk 2532329037U, // VPACKSSWBZrmkz 2517648973U, // VPACKSSWBZrr 49301069U, // VPACKSSWBZrrk 2532329037U, // VPACKSSWBZrrkz 2517648973U, // VPACKSSWBrm 2517648973U, // VPACKSSWBrr 2517656633U, // VPACKUSDWYrm 2517656633U, // VPACKUSDWYrr 2517656633U, // VPACKUSDWZ128rm 2517656633U, // VPACKUSDWZ128rmb 49308729U, // VPACKUSDWZ128rmbk 2532336697U, // VPACKUSDWZ128rmbkz 49308729U, // VPACKUSDWZ128rmk 2532336697U, // VPACKUSDWZ128rmkz 2517656633U, // VPACKUSDWZ128rr 49308729U, // VPACKUSDWZ128rrk 2532336697U, // VPACKUSDWZ128rrkz 2517656633U, // VPACKUSDWZ256rm 2517656633U, // VPACKUSDWZ256rmb 49308729U, // VPACKUSDWZ256rmbk 2532336697U, // VPACKUSDWZ256rmbkz 49308729U, // VPACKUSDWZ256rmk 2532336697U, // VPACKUSDWZ256rmkz 2517656633U, // VPACKUSDWZ256rr 49308729U, // VPACKUSDWZ256rrk 2532336697U, // VPACKUSDWZ256rrkz 2517656633U, // VPACKUSDWZrm 2517656633U, // VPACKUSDWZrmb 49308729U, // VPACKUSDWZrmbk 2532336697U, // VPACKUSDWZrmbkz 49308729U, // VPACKUSDWZrmk 2532336697U, // VPACKUSDWZrmkz 2517656633U, // VPACKUSDWZrr 49308729U, // VPACKUSDWZrrk 2532336697U, // VPACKUSDWZrrkz 2517656633U, // VPACKUSDWrm 2517656633U, // VPACKUSDWrr 2517648984U, // VPACKUSWBYrm 2517648984U, // VPACKUSWBYrr 2517648984U, // VPACKUSWBZ128rm 49301080U, // VPACKUSWBZ128rmk 2532329048U, // VPACKUSWBZ128rmkz 2517648984U, // VPACKUSWBZ128rr 49301080U, // VPACKUSWBZ128rrk 2532329048U, // VPACKUSWBZ128rrkz 2517648984U, // VPACKUSWBZ256rm 49301080U, // VPACKUSWBZ256rmk 2532329048U, // VPACKUSWBZ256rmkz 2517648984U, // VPACKUSWBZ256rr 49301080U, // VPACKUSWBZ256rrk 2532329048U, // VPACKUSWBZ256rrkz 2517648984U, // VPACKUSWBZrm 49301080U, // VPACKUSWBZrmk 2532329048U, // VPACKUSWBZrmkz 2517648984U, // VPACKUSWBZrr 49301080U, // VPACKUSWBZrrk 2532329048U, // VPACKUSWBZrrkz 2517648984U, // VPACKUSWBrm 2517648984U, // VPACKUSWBrr 2517648367U, // VPADDBYrm 2517648367U, // VPADDBYrr 2517648367U, // VPADDBZ128rm 49300463U, // VPADDBZ128rmk 2532328431U, // VPADDBZ128rmkz 2517648367U, // VPADDBZ128rr 49300463U, // VPADDBZ128rrk 2532328431U, // VPADDBZ128rrkz 2517648367U, // VPADDBZ256rm 49300463U, // VPADDBZ256rmk 2532328431U, // VPADDBZ256rmkz 2517648367U, // VPADDBZ256rr 49300463U, // VPADDBZ256rrk 2532328431U, // VPADDBZ256rrkz 2517648367U, // VPADDBZrm 49300463U, // VPADDBZrmk 2532328431U, // VPADDBZrmkz 2517648367U, // VPADDBZrr 49300463U, // VPADDBZrrk 2532328431U, // VPADDBZrrkz 2517648367U, // VPADDBrm 2517648367U, // VPADDBrr 2517649293U, // VPADDDYrm 2517649293U, // VPADDDYrr 2517649293U, // VPADDDZ128rm 2517649293U, // VPADDDZ128rmb 49301389U, // VPADDDZ128rmbk 2532329357U, // VPADDDZ128rmbkz 49301389U, // VPADDDZ128rmk 2532329357U, // VPADDDZ128rmkz 2517649293U, // VPADDDZ128rr 49301389U, // VPADDDZ128rrk 2532329357U, // VPADDDZ128rrkz 2517649293U, // VPADDDZ256rm 2517649293U, // VPADDDZ256rmb 49301389U, // VPADDDZ256rmbk 2532329357U, // VPADDDZ256rmbkz 49301389U, // VPADDDZ256rmk 2532329357U, // VPADDDZ256rmkz 2517649293U, // VPADDDZ256rr 49301389U, // VPADDDZ256rrk 2532329357U, // VPADDDZ256rrkz 2517649293U, // VPADDDZrm 2517649293U, // VPADDDZrmb 49301389U, // VPADDDZrmbk 2532329357U, // VPADDDZrmbkz 49301389U, // VPADDDZrmk 2532329357U, // VPADDDZrmkz 2517649293U, // VPADDDZrr 49301389U, // VPADDDZrrk 2532329357U, // VPADDDZrrkz 2517649293U, // VPADDDrm 2517649293U, // VPADDDrr 2517653088U, // VPADDQYrm 2517653088U, // VPADDQYrr 2517653088U, // VPADDQZ128rm 2517653088U, // VPADDQZ128rmb 49305184U, // VPADDQZ128rmbk 2532333152U, // VPADDQZ128rmbkz 49305184U, // VPADDQZ128rmk 2532333152U, // VPADDQZ128rmkz 2517653088U, // VPADDQZ128rr 49305184U, // VPADDQZ128rrk 2532333152U, // VPADDQZ128rrkz 2517653088U, // VPADDQZ256rm 2517653088U, // VPADDQZ256rmb 49305184U, // VPADDQZ256rmbk 2532333152U, // VPADDQZ256rmbkz 49305184U, // VPADDQZ256rmk 2532333152U, // VPADDQZ256rmkz 2517653088U, // VPADDQZ256rr 49305184U, // VPADDQZ256rrk 2532333152U, // VPADDQZ256rrkz 2517653088U, // VPADDQZrm 2517653088U, // VPADDQZrmb 49305184U, // VPADDQZrmbk 2532333152U, // VPADDQZrmbkz 49305184U, // VPADDQZrmk 2532333152U, // VPADDQZrmkz 2517653088U, // VPADDQZrr 49305184U, // VPADDQZrrk 2532333152U, // VPADDQZrrkz 2517653088U, // VPADDQrm 2517653088U, // VPADDQrr 2517648729U, // VPADDSBYrm 2517648729U, // VPADDSBYrr 2517648729U, // VPADDSBZ128rm 49300825U, // VPADDSBZ128rmk 2532328793U, // VPADDSBZ128rmkz 2517648729U, // VPADDSBZ128rr 49300825U, // VPADDSBZ128rrk 2532328793U, // VPADDSBZ128rrkz 2517648729U, // VPADDSBZ256rm 49300825U, // VPADDSBZ256rmk 2532328793U, // VPADDSBZ256rmkz 2517648729U, // VPADDSBZ256rr 49300825U, // VPADDSBZ256rrk 2532328793U, // VPADDSBZ256rrkz 2517648729U, // VPADDSBZrm 49300825U, // VPADDSBZrmk 2532328793U, // VPADDSBZrmkz 2517648729U, // VPADDSBZrr 49300825U, // VPADDSBZrrk 2532328793U, // VPADDSBZrrkz 2517648729U, // VPADDSBrm 2517648729U, // VPADDSBrr 2517657013U, // VPADDSWYrm 2517657013U, // VPADDSWYrr 2517657013U, // VPADDSWZ128rm 49309109U, // VPADDSWZ128rmk 2532337077U, // VPADDSWZ128rmkz 2517657013U, // VPADDSWZ128rr 49309109U, // VPADDSWZ128rrk 2532337077U, // VPADDSWZ128rrkz 2517657013U, // VPADDSWZ256rm 49309109U, // VPADDSWZ256rmk 2532337077U, // VPADDSWZ256rmkz 2517657013U, // VPADDSWZ256rr 49309109U, // VPADDSWZ256rrk 2532337077U, // VPADDSWZ256rrkz 2517657013U, // VPADDSWZrm 49309109U, // VPADDSWZrmk 2532337077U, // VPADDSWZrmkz 2517657013U, // VPADDSWZrr 49309109U, // VPADDSWZrrk 2532337077U, // VPADDSWZrrkz 2517657013U, // VPADDSWrm 2517657013U, // VPADDSWrr 2517648784U, // VPADDUSBYrm 2517648784U, // VPADDUSBYrr 2517648784U, // VPADDUSBZ128rm 49300880U, // VPADDUSBZ128rmk 2532328848U, // VPADDUSBZ128rmkz 2517648784U, // VPADDUSBZ128rr 49300880U, // VPADDUSBZ128rrk 2532328848U, // VPADDUSBZ128rrkz 2517648784U, // VPADDUSBZ256rm 49300880U, // VPADDUSBZ256rmk 2532328848U, // VPADDUSBZ256rmkz 2517648784U, // VPADDUSBZ256rr 49300880U, // VPADDUSBZ256rrk 2532328848U, // VPADDUSBZ256rrkz 2517648784U, // VPADDUSBZrm 49300880U, // VPADDUSBZrmk 2532328848U, // VPADDUSBZrmkz 2517648784U, // VPADDUSBZrr 49300880U, // VPADDUSBZrrk 2532328848U, // VPADDUSBZrrkz 2517648784U, // VPADDUSBrm 2517648784U, // VPADDUSBrr 2517657099U, // VPADDUSWYrm 2517657099U, // VPADDUSWYrr 2517657099U, // VPADDUSWZ128rm 49309195U, // VPADDUSWZ128rmk 2532337163U, // VPADDUSWZ128rmkz 2517657099U, // VPADDUSWZ128rr 49309195U, // VPADDUSWZ128rrk 2532337163U, // VPADDUSWZ128rrkz 2517657099U, // VPADDUSWZ256rm 49309195U, // VPADDUSWZ256rmk 2532337163U, // VPADDUSWZ256rmkz 2517657099U, // VPADDUSWZ256rr 49309195U, // VPADDUSWZ256rrk 2532337163U, // VPADDUSWZ256rrkz 2517657099U, // VPADDUSWZrm 49309195U, // VPADDUSWZrmk 2532337163U, // VPADDUSWZrmkz 2517657099U, // VPADDUSWZrr 49309195U, // VPADDUSWZrrk 2532337163U, // VPADDUSWZrrkz 2517657099U, // VPADDUSWrm 2517657099U, // VPADDUSWrr 2517656568U, // VPADDWYrm 2517656568U, // VPADDWYrr 2517656568U, // VPADDWZ128rm 49308664U, // VPADDWZ128rmk 2532336632U, // VPADDWZ128rmkz 2517656568U, // VPADDWZ128rr 49308664U, // VPADDWZ128rrk 2532336632U, // VPADDWZ128rrkz 2517656568U, // VPADDWZ256rm 49308664U, // VPADDWZ256rmk 2532336632U, // VPADDWZ256rmkz 2517656568U, // VPADDWZ256rr 49308664U, // VPADDWZ256rrk 2532336632U, // VPADDWZ256rrkz 2517656568U, // VPADDWZrm 49308664U, // VPADDWZrmk 2532336632U, // VPADDWZrmkz 2517656568U, // VPADDWZrr 49308664U, // VPADDWZrrk 2532336632U, // VPADDWZrrkz 2517656568U, // VPADDWrm 2517656568U, // VPADDWrr 2517654181U, // VPALIGNRYrmi 2517654181U, // VPALIGNRYrri 2517654181U, // VPALIGNRZ128rmi 49306277U, // VPALIGNRZ128rmik 2532334245U, // VPALIGNRZ128rmikz 2517654181U, // VPALIGNRZ128rri 49306277U, // VPALIGNRZ128rrik 2532334245U, // VPALIGNRZ128rrikz 2517654181U, // VPALIGNRZ256rmi 49306277U, // VPALIGNRZ256rmik 2532334245U, // VPALIGNRZ256rmikz 2517654181U, // VPALIGNRZ256rri 49306277U, // VPALIGNRZ256rrik 2532334245U, // VPALIGNRZ256rrikz 2517654181U, // VPALIGNRZrmi 49306277U, // VPALIGNRZrmik 2532334245U, // VPALIGNRZrmikz 2517654181U, // VPALIGNRZrri 49306277U, // VPALIGNRZrrik 2532334245U, // VPALIGNRZrrikz 2517654181U, // VPALIGNRrmi 2517654181U, // VPALIGNRrri 2517649317U, // VPANDDZ128rm 2517649317U, // VPANDDZ128rmb 49301413U, // VPANDDZ128rmbk 2532329381U, // VPANDDZ128rmbkz 49301413U, // VPANDDZ128rmk 2532329381U, // VPANDDZ128rmkz 2517649317U, // VPANDDZ128rr 49301413U, // VPANDDZ128rrk 2532329381U, // VPANDDZ128rrkz 2517649317U, // VPANDDZ256rm 2517649317U, // VPANDDZ256rmb 49301413U, // VPANDDZ256rmbk 2532329381U, // VPANDDZ256rmbkz 49301413U, // VPANDDZ256rmk 2532329381U, // VPANDDZ256rmkz 2517649317U, // VPANDDZ256rr 49301413U, // VPANDDZ256rrk 2532329381U, // VPANDDZ256rrkz 2517649317U, // VPANDDZrm 2517649317U, // VPANDDZrmb 49301413U, // VPANDDZrmbk 2532329381U, // VPANDDZrmbkz 49301413U, // VPANDDZrmk 2532329381U, // VPANDDZrmkz 2517649317U, // VPANDDZrr 49301413U, // VPANDDZrrk 2532329381U, // VPANDDZrrkz 2517649611U, // VPANDNDZ128rm 2517649611U, // VPANDNDZ128rmb 49301707U, // VPANDNDZ128rmbk 2532329675U, // VPANDNDZ128rmbkz 49301707U, // VPANDNDZ128rmk 2532329675U, // VPANDNDZ128rmkz 2517649611U, // VPANDNDZ128rr 49301707U, // VPANDNDZ128rrk 2532329675U, // VPANDNDZ128rrkz 2517649611U, // VPANDNDZ256rm 2517649611U, // VPANDNDZ256rmb 49301707U, // VPANDNDZ256rmbk 2532329675U, // VPANDNDZ256rmbkz 49301707U, // VPANDNDZ256rmk 2532329675U, // VPANDNDZ256rmkz 2517649611U, // VPANDNDZ256rr 49301707U, // VPANDNDZ256rrk 2532329675U, // VPANDNDZ256rrkz 2517649611U, // VPANDNDZrm 2517649611U, // VPANDNDZrmb 49301707U, // VPANDNDZrmbk 2532329675U, // VPANDNDZrmbkz 49301707U, // VPANDNDZrmk 2532329675U, // VPANDNDZrmkz 2517649611U, // VPANDNDZrr 49301707U, // VPANDNDZrrk 2532329675U, // VPANDNDZrrkz 2517653512U, // VPANDNQZ128rm 2517653512U, // VPANDNQZ128rmb 49305608U, // VPANDNQZ128rmbk 2532333576U, // VPANDNQZ128rmbkz 49305608U, // VPANDNQZ128rmk 2532333576U, // VPANDNQZ128rmkz 2517653512U, // VPANDNQZ128rr 49305608U, // VPANDNQZ128rrk 2532333576U, // VPANDNQZ128rrkz 2517653512U, // VPANDNQZ256rm 2517653512U, // VPANDNQZ256rmb 49305608U, // VPANDNQZ256rmbk 2532333576U, // VPANDNQZ256rmbkz 49305608U, // VPANDNQZ256rmk 2532333576U, // VPANDNQZ256rmkz 2517653512U, // VPANDNQZ256rr 49305608U, // VPANDNQZ256rrk 2532333576U, // VPANDNQZ256rrkz 2517653512U, // VPANDNQZrm 2517653512U, // VPANDNQZrmb 49305608U, // VPANDNQZrmbk 2532333576U, // VPANDNQZrmbkz 49305608U, // VPANDNQZrmk 2532333576U, // VPANDNQZrmkz 2517653512U, // VPANDNQZrr 49305608U, // VPANDNQZrrk 2532333576U, // VPANDNQZrrkz 2517652604U, // VPANDNYrm 2517652604U, // VPANDNYrr 2517652604U, // VPANDNrm 2517652604U, // VPANDNrr 2517653183U, // VPANDQZ128rm 2517653183U, // VPANDQZ128rmb 49305279U, // VPANDQZ128rmbk 2532333247U, // VPANDQZ128rmbkz 49305279U, // VPANDQZ128rmk 2532333247U, // VPANDQZ128rmkz 2517653183U, // VPANDQZ128rr 49305279U, // VPANDQZ128rrk 2532333247U, // VPANDQZ128rrkz 2517653183U, // VPANDQZ256rm 2517653183U, // VPANDQZ256rmb 49305279U, // VPANDQZ256rmbk 2532333247U, // VPANDQZ256rmbkz 49305279U, // VPANDQZ256rmk 2532333247U, // VPANDQZ256rmkz 2517653183U, // VPANDQZ256rr 49305279U, // VPANDQZ256rrk 2532333247U, // VPANDQZ256rrkz 2517653183U, // VPANDQZrm 2517653183U, // VPANDQZrmb 49305279U, // VPANDQZrmbk 2532333247U, // VPANDQZrmbkz 49305279U, // VPANDQZrmk 2532333247U, // VPANDQZrmkz 2517653183U, // VPANDQZrr 49305279U, // VPANDQZrrk 2532333247U, // VPANDQZrrkz 2517649588U, // VPANDYrm 2517649588U, // VPANDYrr 2517649588U, // VPANDrm 2517649588U, // VPANDrr 2517648432U, // VPAVGBYrm 2517648432U, // VPAVGBYrr 2517648432U, // VPAVGBZ128rm 49300528U, // VPAVGBZ128rmk 2532328496U, // VPAVGBZ128rmkz 2517648432U, // VPAVGBZ128rr 49300528U, // VPAVGBZ128rrk 2532328496U, // VPAVGBZ128rrkz 2517648432U, // VPAVGBZ256rm 49300528U, // VPAVGBZ256rmk 2532328496U, // VPAVGBZ256rmkz 2517648432U, // VPAVGBZ256rr 49300528U, // VPAVGBZ256rrk 2532328496U, // VPAVGBZ256rrkz 2517648432U, // VPAVGBZrm 49300528U, // VPAVGBZrmk 2532328496U, // VPAVGBZrmkz 2517648432U, // VPAVGBZrr 49300528U, // VPAVGBZrrk 2532328496U, // VPAVGBZrrkz 2517648432U, // VPAVGBrm 2517648432U, // VPAVGBrr 2517656689U, // VPAVGWYrm 2517656689U, // VPAVGWYrr 2517656689U, // VPAVGWZ128rm 49308785U, // VPAVGWZ128rmk 2532336753U, // VPAVGWZ128rmkz 2517656689U, // VPAVGWZ128rr 49308785U, // VPAVGWZ128rrk 2532336753U, // VPAVGWZ128rrkz 2517656689U, // VPAVGWZ256rm 49308785U, // VPAVGWZ256rmk 2532336753U, // VPAVGWZ256rmkz 2517656689U, // VPAVGWZ256rr 49308785U, // VPAVGWZ256rrk 2532336753U, // VPAVGWZ256rrkz 2517656689U, // VPAVGWZrm 49308785U, // VPAVGWZrmk 2532336753U, // VPAVGWZrmkz 2517656689U, // VPAVGWZrr 49308785U, // VPAVGWZrrk 2532336753U, // VPAVGWZrrkz 2517656689U, // VPAVGWrm 2517656689U, // VPAVGWrr 2517649336U, // VPBLENDDYrmi 2517649336U, // VPBLENDDYrri 2517649336U, // VPBLENDDrmi 2517649336U, // VPBLENDDrri 2517648485U, // VPBLENDMBZ128rm 384844901U, // VPBLENDMBZ128rmk 2532328549U, // VPBLENDMBZ128rmkz 2517648485U, // VPBLENDMBZ128rr 384844901U, // VPBLENDMBZ128rrk 2532328549U, // VPBLENDMBZ128rrkz 2517648485U, // VPBLENDMBZ256rm 384844901U, // VPBLENDMBZ256rmk 2532328549U, // VPBLENDMBZ256rmkz 2517648485U, // VPBLENDMBZ256rr 384844901U, // VPBLENDMBZ256rrk 2532328549U, // VPBLENDMBZ256rrkz 2517648485U, // VPBLENDMBZrm 384844901U, // VPBLENDMBZrmk 2532328549U, // VPBLENDMBZrmkz 2517648485U, // VPBLENDMBZrr 384844901U, // VPBLENDMBZrrk 2532328549U, // VPBLENDMBZrrkz 2517649540U, // VPBLENDMDZ128rm 2517649540U, // VPBLENDMDZ128rmb 384845956U, // VPBLENDMDZ128rmbk 2532329604U, // VPBLENDMDZ128rmbkz 384845956U, // VPBLENDMDZ128rmk 2532329604U, // VPBLENDMDZ128rmkz 2517649540U, // VPBLENDMDZ128rr 384845956U, // VPBLENDMDZ128rrk 2532329604U, // VPBLENDMDZ128rrkz 2517649540U, // VPBLENDMDZ256rm 2517649540U, // VPBLENDMDZ256rmb 384845956U, // VPBLENDMDZ256rmbk 2532329604U, // VPBLENDMDZ256rmbkz 384845956U, // VPBLENDMDZ256rmk 2532329604U, // VPBLENDMDZ256rmkz 2517649540U, // VPBLENDMDZ256rr 384845956U, // VPBLENDMDZ256rrk 2532329604U, // VPBLENDMDZ256rrkz 2517649540U, // VPBLENDMDZrm 2517649540U, // VPBLENDMDZrmb 384845956U, // VPBLENDMDZrmbk 2532329604U, // VPBLENDMDZrmbkz 384845956U, // VPBLENDMDZrmk 2532329604U, // VPBLENDMDZrmkz 2517649540U, // VPBLENDMDZrr 384845956U, // VPBLENDMDZrrk 2532329604U, // VPBLENDMDZrrkz 2517653456U, // VPBLENDMQZ128rm 2517653456U, // VPBLENDMQZ128rmb 384849872U, // VPBLENDMQZ128rmbk 2532333520U, // VPBLENDMQZ128rmbkz 384849872U, // VPBLENDMQZ128rmk 2532333520U, // VPBLENDMQZ128rmkz 2517653456U, // VPBLENDMQZ128rr 384849872U, // VPBLENDMQZ128rrk 2532333520U, // VPBLENDMQZ128rrkz 2517653456U, // VPBLENDMQZ256rm 2517653456U, // VPBLENDMQZ256rmb 384849872U, // VPBLENDMQZ256rmbk 2532333520U, // VPBLENDMQZ256rmbkz 384849872U, // VPBLENDMQZ256rmk 2532333520U, // VPBLENDMQZ256rmkz 2517653456U, // VPBLENDMQZ256rr 384849872U, // VPBLENDMQZ256rrk 2532333520U, // VPBLENDMQZ256rrkz 2517653456U, // VPBLENDMQZrm 2517653456U, // VPBLENDMQZrmb 384849872U, // VPBLENDMQZrmbk 2532333520U, // VPBLENDMQZrmbkz 384849872U, // VPBLENDMQZrmk 2532333520U, // VPBLENDMQZrmkz 2517653456U, // VPBLENDMQZrr 384849872U, // VPBLENDMQZrrk 2532333520U, // VPBLENDMQZrrkz 2517656787U, // VPBLENDMWZ128rm 384853203U, // VPBLENDMWZ128rmk 2532336851U, // VPBLENDMWZ128rmkz 2517656787U, // VPBLENDMWZ128rr 384853203U, // VPBLENDMWZ128rrk 2532336851U, // VPBLENDMWZ128rrkz 2517656787U, // VPBLENDMWZ256rm 384853203U, // VPBLENDMWZ256rmk 2532336851U, // VPBLENDMWZ256rmkz 2517656787U, // VPBLENDMWZ256rr 384853203U, // VPBLENDMWZ256rrk 2532336851U, // VPBLENDMWZ256rrkz 2517656787U, // VPBLENDMWZrm 384853203U, // VPBLENDMWZrmk 2532336851U, // VPBLENDMWZrmkz 2517656787U, // VPBLENDMWZrr 384853203U, // VPBLENDMWZrrk 2532336851U, // VPBLENDMWZrrkz 2517648942U, // VPBLENDVBYrm 2517648942U, // VPBLENDVBYrr 2517648942U, // VPBLENDVBrm 2517648942U, // VPBLENDVBrr 2517656603U, // VPBLENDWYrmi 2517656603U, // VPBLENDWYrri 2517656603U, // VPBLENDWrmi 2517656603U, // VPBLENDWrri 537937372U, // VPBROADCASTBYrm 370165212U, // VPBROADCASTBYrr 537937372U, // VPBROADCASTBZ128m 49300956U, // VPBROADCASTBZ128mk 2532328924U, // VPBROADCASTBZ128mkz 370165212U, // VPBROADCASTBZ128r 49300956U, // VPBROADCASTBZ128rk 2532328924U, // VPBROADCASTBZ128rkz 537937372U, // VPBROADCASTBZ256m 49300956U, // VPBROADCASTBZ256mk 2532328924U, // VPBROADCASTBZ256mkz 370165212U, // VPBROADCASTBZ256r 49300956U, // VPBROADCASTBZ256rk 2532328924U, // VPBROADCASTBZ256rkz 537937372U, // VPBROADCASTBZm 49300956U, // VPBROADCASTBZmk 2532328924U, // VPBROADCASTBZmkz 370165212U, // VPBROADCASTBZr 49300956U, // VPBROADCASTBZrk 2532328924U, // VPBROADCASTBZrkz 370165212U, // VPBROADCASTBrZ128r 49300956U, // VPBROADCASTBrZ128rk 2532328924U, // VPBROADCASTBrZ128rkz 370165212U, // VPBROADCASTBrZ256r 49300956U, // VPBROADCASTBrZ256rk 2532328924U, // VPBROADCASTBrZ256rkz 370165212U, // VPBROADCASTBrZr 49300956U, // VPBROADCASTBrZrk 2532328924U, // VPBROADCASTBrZrkz 537937372U, // VPBROADCASTBrm 370165212U, // VPBROADCASTBrr 403722224U, // VPBROADCASTDYrm 370167792U, // VPBROADCASTDYrr 403722224U, // VPBROADCASTDZ128m 49303536U, // VPBROADCASTDZ128mk 2532331504U, // VPBROADCASTDZ128mkz 370167792U, // VPBROADCASTDZ128r 49303536U, // VPBROADCASTDZ128rk 2532331504U, // VPBROADCASTDZ128rkz 403722224U, // VPBROADCASTDZ256m 49303536U, // VPBROADCASTDZ256mk 2532331504U, // VPBROADCASTDZ256mkz 370167792U, // VPBROADCASTDZ256r 49303536U, // VPBROADCASTDZ256rk 2532331504U, // VPBROADCASTDZ256rkz 403722224U, // VPBROADCASTDZm 49303536U, // VPBROADCASTDZmk 2532331504U, // VPBROADCASTDZmkz 370167792U, // VPBROADCASTDZr 49303536U, // VPBROADCASTDZrk 2532331504U, // VPBROADCASTDZrkz 370167792U, // VPBROADCASTDrZ128r 49303536U, // VPBROADCASTDrZ128rk 2532331504U, // VPBROADCASTDrZ128rkz 370167792U, // VPBROADCASTDrZ256r 49303536U, // VPBROADCASTDrZ256rk 2532331504U, // VPBROADCASTDrZ256rkz 370167792U, // VPBROADCASTDrZr 49303536U, // VPBROADCASTDrZrk 2532331504U, // VPBROADCASTDrZrkz 403722224U, // VPBROADCASTDrm 370167792U, // VPBROADCASTDrr 370169245U, // VPBROADCASTMB2QZ128rr 370169245U, // VPBROADCASTMB2QZ256rr 370169245U, // VPBROADCASTMB2QZrr 370165503U, // VPBROADCASTMW2DZ128rr 370165503U, // VPBROADCASTMW2DZ256rr 370165503U, // VPBROADCASTMW2DZrr 437279124U, // VPBROADCASTQYrm 370170260U, // VPBROADCASTQYrr 437279124U, // VPBROADCASTQZ128m 49306004U, // VPBROADCASTQZ128mk 2532333972U, // VPBROADCASTQZ128mkz 370170260U, // VPBROADCASTQZ128r 49306004U, // VPBROADCASTQZ128rk 2532333972U, // VPBROADCASTQZ128rkz 437279124U, // VPBROADCASTQZ256m 49306004U, // VPBROADCASTQZ256mk 2532333972U, // VPBROADCASTQZ256mkz 370170260U, // VPBROADCASTQZ256r 49306004U, // VPBROADCASTQZ256rk 2532333972U, // VPBROADCASTQZ256rkz 437279124U, // VPBROADCASTQZm 49306004U, // VPBROADCASTQZmk 2532333972U, // VPBROADCASTQZmkz 370170260U, // VPBROADCASTQZr 49306004U, // VPBROADCASTQZrk 2532333972U, // VPBROADCASTQZrkz 370170260U, // VPBROADCASTQrZ128r 49306004U, // VPBROADCASTQrZ128rk 2532333972U, // VPBROADCASTQrZ128rkz 370170260U, // VPBROADCASTQrZ256r 49306004U, // VPBROADCASTQrZ256rk 2532333972U, // VPBROADCASTQrZ256rkz 370170260U, // VPBROADCASTQrZr 49306004U, // VPBROADCASTQrZrk 2532333972U, // VPBROADCASTQrZrkz 437279124U, // VPBROADCASTQrm 370170260U, // VPBROADCASTQrr 504391240U, // VPBROADCASTWYrm 370173512U, // VPBROADCASTWYrr 504391240U, // VPBROADCASTWZ128m 49309256U, // VPBROADCASTWZ128mk 2532337224U, // VPBROADCASTWZ128mkz 370173512U, // VPBROADCASTWZ128r 49309256U, // VPBROADCASTWZ128rk 2532337224U, // VPBROADCASTWZ128rkz 504391240U, // VPBROADCASTWZ256m 49309256U, // VPBROADCASTWZ256mk 2532337224U, // VPBROADCASTWZ256mkz 370173512U, // VPBROADCASTWZ256r 49309256U, // VPBROADCASTWZ256rk 2532337224U, // VPBROADCASTWZ256rkz 504391240U, // VPBROADCASTWZm 49309256U, // VPBROADCASTWZmk 2532337224U, // VPBROADCASTWZmkz 370173512U, // VPBROADCASTWZr 49309256U, // VPBROADCASTWZrk 2532337224U, // VPBROADCASTWZrkz 370173512U, // VPBROADCASTWrZ128r 49309256U, // VPBROADCASTWrZ128rk 2532337224U, // VPBROADCASTWrZ128rkz 370173512U, // VPBROADCASTWrZ256r 49309256U, // VPBROADCASTWrZ256rk 2532337224U, // VPBROADCASTWrZ256rkz 370173512U, // VPBROADCASTWrZr 49309256U, // VPBROADCASTWrZrk 2532337224U, // VPBROADCASTWrZrkz 504391240U, // VPBROADCASTWrm 370173512U, // VPBROADCASTWrr 2517653228U, // VPCLMULQDQYrm 2517653228U, // VPCLMULQDQYrr 2517653228U, // VPCLMULQDQZ128rm 2517653228U, // VPCLMULQDQZ128rr 2517653228U, // VPCLMULQDQZ256rm 2517653228U, // VPCLMULQDQZ256rr 2517653228U, // VPCLMULQDQZrm 2517653228U, // VPCLMULQDQZrr 2517653228U, // VPCLMULQDQrm 2517653228U, // VPCLMULQDQrr 2517656341U, // VPCMOVYrmr 2517656341U, // VPCMOVYrrm 2517656341U, // VPCMOVYrrr 2517656341U, // VPCMOVYrrr_REV 2517656341U, // VPCMOVrmr 2517656341U, // VPCMOVrrm 2517656341U, // VPCMOVrrr 2517656341U, // VPCMOVrrr_REV 588459324U, // VPCMPBZ128rmi 2517648564U, // VPCMPBZ128rmi_alt 3239619900U, // VPCMPBZ128rmik 384844980U, // VPCMPBZ128rmik_alt 588475708U, // VPCMPBZ128rri 2517648564U, // VPCMPBZ128rri_alt 3239636284U, // VPCMPBZ128rrik 384844980U, // VPCMPBZ128rrik_alt 588459324U, // VPCMPBZ256rmi 2517648564U, // VPCMPBZ256rmi_alt 1092136252U, // VPCMPBZ256rmik 384844980U, // VPCMPBZ256rmik_alt 588475708U, // VPCMPBZ256rri 2517648564U, // VPCMPBZ256rri_alt 3239636284U, // VPCMPBZ256rrik 384844980U, // VPCMPBZ256rrik_alt 588459324U, // VPCMPBZrmi 2517648564U, // VPCMPBZrmi_alt 3239619900U, // VPCMPBZrmik 384844980U, // VPCMPBZrmik_alt 588475708U, // VPCMPBZrri 2517648564U, // VPCMPBZrri_alt 3239636284U, // VPCMPBZrrik 384844980U, // VPCMPBZrrik_alt 589507900U, // VPCMPDZ128rmi 2517650375U, // VPCMPDZ128rmi_alt 589507900U, // VPCMPDZ128rmib 2517650375U, // VPCMPDZ128rmib_alt 1093184828U, // VPCMPDZ128rmibk 384846791U, // VPCMPDZ128rmibk_alt 3240668476U, // VPCMPDZ128rmik 384846791U, // VPCMPDZ128rmik_alt 589524284U, // VPCMPDZ128rri 2517650375U, // VPCMPDZ128rri_alt 3240684860U, // VPCMPDZ128rrik 384846791U, // VPCMPDZ128rrik_alt 589507900U, // VPCMPDZ256rmi 2517650375U, // VPCMPDZ256rmi_alt 589507900U, // VPCMPDZ256rmib 2517650375U, // VPCMPDZ256rmib_alt 1093184828U, // VPCMPDZ256rmibk 384846791U, // VPCMPDZ256rmibk_alt 1093184828U, // VPCMPDZ256rmik 384846791U, // VPCMPDZ256rmik_alt 589524284U, // VPCMPDZ256rri 2517650375U, // VPCMPDZ256rri_alt 3240684860U, // VPCMPDZ256rrik 384846791U, // VPCMPDZ256rrik_alt 589507900U, // VPCMPDZrmi 2517650375U, // VPCMPDZrmi_alt 589507900U, // VPCMPDZrmib 2517650375U, // VPCMPDZrmib_alt 1093184828U, // VPCMPDZrmibk 384846791U, // VPCMPDZrmibk_alt 3240668476U, // VPCMPDZrmik 384846791U, // VPCMPDZrmik_alt 589524284U, // VPCMPDZrri 2517650375U, // VPCMPDZrri_alt 3240684860U, // VPCMPDZrrik 384846791U, // VPCMPDZrrik_alt 2517648588U, // VPCMPEQBYrm 2517648588U, // VPCMPEQBYrr 2517648588U, // VPCMPEQBZ128rm 384845004U, // VPCMPEQBZ128rmk 2517648588U, // VPCMPEQBZ128rr 384845004U, // VPCMPEQBZ128rrk 2517648588U, // VPCMPEQBZ256rm 384845004U, // VPCMPEQBZ256rmk 2517648588U, // VPCMPEQBZ256rr 384845004U, // VPCMPEQBZ256rrk 2517648588U, // VPCMPEQBZrm 384845004U, // VPCMPEQBZrmk 2517648588U, // VPCMPEQBZrr 384845004U, // VPCMPEQBZrrk 2517648588U, // VPCMPEQBrm 2517648588U, // VPCMPEQBrr 2517650638U, // VPCMPEQDYrm 2517650638U, // VPCMPEQDYrr 2517650638U, // VPCMPEQDZ128rm 2517650638U, // VPCMPEQDZ128rmb 384847054U, // VPCMPEQDZ128rmbk 384847054U, // VPCMPEQDZ128rmk 2517650638U, // VPCMPEQDZ128rr 384847054U, // VPCMPEQDZ128rrk 2517650638U, // VPCMPEQDZ256rm 2517650638U, // VPCMPEQDZ256rmb 384847054U, // VPCMPEQDZ256rmbk 384847054U, // VPCMPEQDZ256rmk 2517650638U, // VPCMPEQDZ256rr 384847054U, // VPCMPEQDZ256rrk 2517650638U, // VPCMPEQDZrm 2517650638U, // VPCMPEQDZrmb 384847054U, // VPCMPEQDZrmbk 384847054U, // VPCMPEQDZrmk 2517650638U, // VPCMPEQDZrr 384847054U, // VPCMPEQDZrrk 2517650638U, // VPCMPEQDrm 2517650638U, // VPCMPEQDrr 2517653601U, // VPCMPEQQYrm 2517653601U, // VPCMPEQQYrr 2517653601U, // VPCMPEQQZ128rm 2517653601U, // VPCMPEQQZ128rmb 384850017U, // VPCMPEQQZ128rmbk 384850017U, // VPCMPEQQZ128rmk 2517653601U, // VPCMPEQQZ128rr 384850017U, // VPCMPEQQZ128rrk 2517653601U, // VPCMPEQQZ256rm 2517653601U, // VPCMPEQQZ256rmb 384850017U, // VPCMPEQQZ256rmbk 384850017U, // VPCMPEQQZ256rmk 2517653601U, // VPCMPEQQZ256rr 384850017U, // VPCMPEQQZ256rrk 2517653601U, // VPCMPEQQZrm 2517653601U, // VPCMPEQQZrmb 384850017U, // VPCMPEQQZrmbk 384850017U, // VPCMPEQQZrmk 2517653601U, // VPCMPEQQZrr 384850017U, // VPCMPEQQZrrk 2517653601U, // VPCMPEQQrm 2517653601U, // VPCMPEQQrr 2517656860U, // VPCMPEQWYrm 2517656860U, // VPCMPEQWYrr 2517656860U, // VPCMPEQWZ128rm 384853276U, // VPCMPEQWZ128rmk 2517656860U, // VPCMPEQWZ128rr 384853276U, // VPCMPEQWZ128rrk 2517656860U, // VPCMPEQWZ256rm 384853276U, // VPCMPEQWZ256rmk 2517656860U, // VPCMPEQWZ256rr 384853276U, // VPCMPEQWZ256rrk 2517656860U, // VPCMPEQWZrm 384853276U, // VPCMPEQWZrmk 2517656860U, // VPCMPEQWZrr 384853276U, // VPCMPEQWZrrk 2517656860U, // VPCMPEQWrm 2517656860U, // VPCMPEQWrr 2484097779U, // VPCMPESTRIrm 2517652211U, // VPCMPESTRIrr 2484098141U, // VPCMPESTRMrm 2517652573U, // VPCMPESTRMrr 2517648825U, // VPCMPGTBYrm 2517648825U, // VPCMPGTBYrr 2517648825U, // VPCMPGTBZ128rm 384845241U, // VPCMPGTBZ128rmk 2517648825U, // VPCMPGTBZ128rr 384845241U, // VPCMPGTBZ128rrk 2517648825U, // VPCMPGTBZ256rm 384845241U, // VPCMPGTBZ256rmk 2517648825U, // VPCMPGTBZ256rr 384845241U, // VPCMPGTBZ256rrk 2517648825U, // VPCMPGTBZrm 384845241U, // VPCMPGTBZrmk 2517648825U, // VPCMPGTBZrr 384845241U, // VPCMPGTBZrrk 2517648825U, // VPCMPGTBrm 2517648825U, // VPCMPGTBrr 2517651395U, // VPCMPGTDYrm 2517651395U, // VPCMPGTDYrr 2517651395U, // VPCMPGTDZ128rm 2517651395U, // VPCMPGTDZ128rmb 384847811U, // VPCMPGTDZ128rmbk 384847811U, // VPCMPGTDZ128rmk 2517651395U, // VPCMPGTDZ128rr 384847811U, // VPCMPGTDZ128rrk 2517651395U, // VPCMPGTDZ256rm 2517651395U, // VPCMPGTDZ256rmb 384847811U, // VPCMPGTDZ256rmbk 384847811U, // VPCMPGTDZ256rmk 2517651395U, // VPCMPGTDZ256rr 384847811U, // VPCMPGTDZ256rrk 2517651395U, // VPCMPGTDZrm 2517651395U, // VPCMPGTDZrmb 384847811U, // VPCMPGTDZrmbk 384847811U, // VPCMPGTDZrmk 2517651395U, // VPCMPGTDZrr 384847811U, // VPCMPGTDZrrk 2517651395U, // VPCMPGTDrm 2517651395U, // VPCMPGTDrr 2517653846U, // VPCMPGTQYrm 2517653846U, // VPCMPGTQYrr 2517653846U, // VPCMPGTQZ128rm 2517653846U, // VPCMPGTQZ128rmb 384850262U, // VPCMPGTQZ128rmbk 384850262U, // VPCMPGTQZ128rmk 2517653846U, // VPCMPGTQZ128rr 384850262U, // VPCMPGTQZ128rrk 2517653846U, // VPCMPGTQZ256rm 2517653846U, // VPCMPGTQZ256rmb 384850262U, // VPCMPGTQZ256rmbk 384850262U, // VPCMPGTQZ256rmk 2517653846U, // VPCMPGTQZ256rr 384850262U, // VPCMPGTQZ256rrk 2517653846U, // VPCMPGTQZrm 2517653846U, // VPCMPGTQZrmb 384850262U, // VPCMPGTQZrmbk 384850262U, // VPCMPGTQZrmk 2517653846U, // VPCMPGTQZrr 384850262U, // VPCMPGTQZrrk 2517653846U, // VPCMPGTQrm 2517653846U, // VPCMPGTQrr 2517657125U, // VPCMPGTWYrm 2517657125U, // VPCMPGTWYrr 2517657125U, // VPCMPGTWZ128rm 384853541U, // VPCMPGTWZ128rmk 2517657125U, // VPCMPGTWZ128rr 384853541U, // VPCMPGTWZ128rrk 2517657125U, // VPCMPGTWZ256rm 384853541U, // VPCMPGTWZ256rmk 2517657125U, // VPCMPGTWZ256rr 384853541U, // VPCMPGTWZ256rrk 2517657125U, // VPCMPGTWZrm 384853541U, // VPCMPGTWZrmk 2517657125U, // VPCMPGTWZrr 384853541U, // VPCMPGTWZrrk 2517657125U, // VPCMPGTWrm 2517657125U, // VPCMPGTWrr 2484097791U, // VPCMPISTRIrm 2517652223U, // VPCMPISTRIrr 2484098153U, // VPCMPISTRMrm 2517652585U, // VPCMPISTRMrr 590556476U, // VPCMPQZ128rmi 2517653530U, // VPCMPQZ128rmi_alt 590556476U, // VPCMPQZ128rmib 2517653530U, // VPCMPQZ128rmib_alt 3241717052U, // VPCMPQZ128rmibk 384849946U, // VPCMPQZ128rmibk_alt 3241717052U, // VPCMPQZ128rmik 384849946U, // VPCMPQZ128rmik_alt 590572860U, // VPCMPQZ128rri 2517653530U, // VPCMPQZ128rri_alt 3241733436U, // VPCMPQZ128rrik 384849946U, // VPCMPQZ128rrik_alt 590556476U, // VPCMPQZ256rmi 2517653530U, // VPCMPQZ256rmi_alt 590556476U, // VPCMPQZ256rmib 2517653530U, // VPCMPQZ256rmib_alt 3241717052U, // VPCMPQZ256rmibk 384849946U, // VPCMPQZ256rmibk_alt 1094233404U, // VPCMPQZ256rmik 384849946U, // VPCMPQZ256rmik_alt 590572860U, // VPCMPQZ256rri 2517653530U, // VPCMPQZ256rri_alt 3241733436U, // VPCMPQZ256rrik 384849946U, // VPCMPQZ256rrik_alt 590556476U, // VPCMPQZrmi 2517653530U, // VPCMPQZrmi_alt 590556476U, // VPCMPQZrmib 2517653530U, // VPCMPQZrmib_alt 3241717052U, // VPCMPQZrmibk 384849946U, // VPCMPQZrmibk_alt 3241717052U, // VPCMPQZrmik 384849946U, // VPCMPQZrmik_alt 590572860U, // VPCMPQZrri 2517653530U, // VPCMPQZrri_alt 3241733436U, // VPCMPQZrrik 384849946U, // VPCMPQZrrik_alt 591605052U, // VPCMPUBZ128rmi 2517648910U, // VPCMPUBZ128rmi_alt 3242765628U, // VPCMPUBZ128rmik 384845326U, // VPCMPUBZ128rmik_alt 591621436U, // VPCMPUBZ128rri 2517648910U, // VPCMPUBZ128rri_alt 3242782012U, // VPCMPUBZ128rrik 384845326U, // VPCMPUBZ128rrik_alt 591605052U, // VPCMPUBZ256rmi 2517648910U, // VPCMPUBZ256rmi_alt 1095281980U, // VPCMPUBZ256rmik 384845326U, // VPCMPUBZ256rmik_alt 591621436U, // VPCMPUBZ256rri 2517648910U, // VPCMPUBZ256rri_alt 3242782012U, // VPCMPUBZ256rrik 384845326U, // VPCMPUBZ256rrik_alt 591605052U, // VPCMPUBZrmi 2517648910U, // VPCMPUBZrmi_alt 3242765628U, // VPCMPUBZrmik 384845326U, // VPCMPUBZrmik_alt 591621436U, // VPCMPUBZrri 2517648910U, // VPCMPUBZrri_alt 3242782012U, // VPCMPUBZrrik 384845326U, // VPCMPUBZrrik_alt 592653628U, // VPCMPUDZ128rmi 2517651490U, // VPCMPUDZ128rmi_alt 592653628U, // VPCMPUDZ128rmib 2517651490U, // VPCMPUDZ128rmib_alt 1096330556U, // VPCMPUDZ128rmibk 384847906U, // VPCMPUDZ128rmibk_alt 3243814204U, // VPCMPUDZ128rmik 384847906U, // VPCMPUDZ128rmik_alt 592670012U, // VPCMPUDZ128rri 2517651490U, // VPCMPUDZ128rri_alt 3243830588U, // VPCMPUDZ128rrik 384847906U, // VPCMPUDZ128rrik_alt 592653628U, // VPCMPUDZ256rmi 2517651490U, // VPCMPUDZ256rmi_alt 592653628U, // VPCMPUDZ256rmib 2517651490U, // VPCMPUDZ256rmib_alt 1096330556U, // VPCMPUDZ256rmibk 384847906U, // VPCMPUDZ256rmibk_alt 1096330556U, // VPCMPUDZ256rmik 384847906U, // VPCMPUDZ256rmik_alt 592670012U, // VPCMPUDZ256rri 2517651490U, // VPCMPUDZ256rri_alt 3243830588U, // VPCMPUDZ256rrik 384847906U, // VPCMPUDZ256rrik_alt 592653628U, // VPCMPUDZrmi 2517651490U, // VPCMPUDZrmi_alt 592653628U, // VPCMPUDZrmib 2517651490U, // VPCMPUDZrmib_alt 1096330556U, // VPCMPUDZrmibk 384847906U, // VPCMPUDZrmibk_alt 3243814204U, // VPCMPUDZrmik 384847906U, // VPCMPUDZrmik_alt 592670012U, // VPCMPUDZrri 2517651490U, // VPCMPUDZrri_alt 3243830588U, // VPCMPUDZrrik 384847906U, // VPCMPUDZrrik_alt 593702204U, // VPCMPUQZ128rmi 2517653984U, // VPCMPUQZ128rmi_alt 593702204U, // VPCMPUQZ128rmib 2517653984U, // VPCMPUQZ128rmib_alt 3244862780U, // VPCMPUQZ128rmibk 384850400U, // VPCMPUQZ128rmibk_alt 3244862780U, // VPCMPUQZ128rmik 384850400U, // VPCMPUQZ128rmik_alt 593718588U, // VPCMPUQZ128rri 2517653984U, // VPCMPUQZ128rri_alt 3244879164U, // VPCMPUQZ128rrik 384850400U, // VPCMPUQZ128rrik_alt 593702204U, // VPCMPUQZ256rmi 2517653984U, // VPCMPUQZ256rmi_alt 593702204U, // VPCMPUQZ256rmib 2517653984U, // VPCMPUQZ256rmib_alt 3244862780U, // VPCMPUQZ256rmibk 384850400U, // VPCMPUQZ256rmibk_alt 1097379132U, // VPCMPUQZ256rmik 384850400U, // VPCMPUQZ256rmik_alt 593718588U, // VPCMPUQZ256rri 2517653984U, // VPCMPUQZ256rri_alt 3244879164U, // VPCMPUQZ256rrik 384850400U, // VPCMPUQZ256rrik_alt 593702204U, // VPCMPUQZrmi 2517653984U, // VPCMPUQZrmi_alt 593702204U, // VPCMPUQZrmib 2517653984U, // VPCMPUQZrmib_alt 3244862780U, // VPCMPUQZrmibk 384850400U, // VPCMPUQZrmibk_alt 3244862780U, // VPCMPUQZrmik 384850400U, // VPCMPUQZrmik_alt 593718588U, // VPCMPUQZrri 2517653984U, // VPCMPUQZrri_alt 3244879164U, // VPCMPUQZrrik 384850400U, // VPCMPUQZrrik_alt 594750780U, // VPCMPUWZ128rmi 2517657220U, // VPCMPUWZ128rmi_alt 3245911356U, // VPCMPUWZ128rmik 384853636U, // VPCMPUWZ128rmik_alt 594767164U, // VPCMPUWZ128rri 2517657220U, // VPCMPUWZ128rri_alt 3245927740U, // VPCMPUWZ128rrik 384853636U, // VPCMPUWZ128rrik_alt 594750780U, // VPCMPUWZ256rmi 2517657220U, // VPCMPUWZ256rmi_alt 1098427708U, // VPCMPUWZ256rmik 384853636U, // VPCMPUWZ256rmik_alt 594767164U, // VPCMPUWZ256rri 2517657220U, // VPCMPUWZ256rri_alt 3245927740U, // VPCMPUWZ256rrik 384853636U, // VPCMPUWZ256rrik_alt 594750780U, // VPCMPUWZrmi 2517657220U, // VPCMPUWZrmi_alt 3245911356U, // VPCMPUWZrmik 384853636U, // VPCMPUWZrmik_alt 594767164U, // VPCMPUWZrri 2517657220U, // VPCMPUWZrri_alt 3245927740U, // VPCMPUWZrrik 384853636U, // VPCMPUWZrrik_alt 595799356U, // VPCMPWZ128rmi 2517656852U, // VPCMPWZ128rmi_alt 3246959932U, // VPCMPWZ128rmik 384853268U, // VPCMPWZ128rmik_alt 595815740U, // VPCMPWZ128rri 2517656852U, // VPCMPWZ128rri_alt 3246976316U, // VPCMPWZ128rrik 384853268U, // VPCMPWZ128rrik_alt 595799356U, // VPCMPWZ256rmi 2517656852U, // VPCMPWZ256rmi_alt 1099476284U, // VPCMPWZ256rmik 384853268U, // VPCMPWZ256rmik_alt 595815740U, // VPCMPWZ256rri 2517656852U, // VPCMPWZ256rri_alt 3246976316U, // VPCMPWZ256rrik 384853268U, // VPCMPWZ256rrik_alt 595799356U, // VPCMPWZrmi 2517656852U, // VPCMPWZrmi_alt 3246959932U, // VPCMPWZrmik 384853268U, // VPCMPWZrmik_alt 595815740U, // VPCMPWZrri 2517656852U, // VPCMPWZrri_alt 3246976316U, // VPCMPWZrrik 384853268U, // VPCMPWZrrik_alt 588918014U, // VPCOMBmi 2517648507U, // VPCOMBmi_alt 588934398U, // VPCOMBri 2517648507U, // VPCOMBri_alt 589966590U, // VPCOMDmi 2517649562U, // VPCOMDmi_alt 589982974U, // VPCOMDri 2517649562U, // VPCOMDri_alt 1197433U, // VPCOMPRESSBZ128mr 15877497U, // VPCOMPRESSBZ128mrk 370165113U, // VPCOMPRESSBZ128rr 49300857U, // VPCOMPRESSBZ128rrk 2532328825U, // VPCOMPRESSBZ128rrkz 1672569U, // VPCOMPRESSBZ256mr 16352633U, // VPCOMPRESSBZ256mrk 370165113U, // VPCOMPRESSBZ256rr 49300857U, // VPCOMPRESSBZ256rrk 2532328825U, // VPCOMPRESSBZ256rrkz 1688953U, // VPCOMPRESSBZmr 16369017U, // VPCOMPRESSBZmrk 370165113U, // VPCOMPRESSBZrr 49300857U, // VPCOMPRESSBZrrk 2532328825U, // VPCOMPRESSBZrrkz 1199897U, // VPCOMPRESSDZ128mr 15879961U, // VPCOMPRESSDZ128mrk 370167577U, // VPCOMPRESSDZ128rr 49303321U, // VPCOMPRESSDZ128rrk 2532331289U, // VPCOMPRESSDZ128rrkz 1675033U, // VPCOMPRESSDZ256mr 16355097U, // VPCOMPRESSDZ256mrk 370167577U, // VPCOMPRESSDZ256rr 49303321U, // VPCOMPRESSDZ256rrk 2532331289U, // VPCOMPRESSDZ256rrkz 1691417U, // VPCOMPRESSDZmr 16371481U, // VPCOMPRESSDZmrk 370167577U, // VPCOMPRESSDZrr 49303321U, // VPCOMPRESSDZrrk 2532331289U, // VPCOMPRESSDZrrkz 1202461U, // VPCOMPRESSQZ128mr 15882525U, // VPCOMPRESSQZ128mrk 370170141U, // VPCOMPRESSQZ128rr 49305885U, // VPCOMPRESSQZ128rrk 2532333853U, // VPCOMPRESSQZ128rrkz 1677597U, // VPCOMPRESSQZ256mr 16357661U, // VPCOMPRESSQZ256mrk 370170141U, // VPCOMPRESSQZ256rr 49305885U, // VPCOMPRESSQZ256rrk 2532333853U, // VPCOMPRESSQZ256rrkz 1693981U, // VPCOMPRESSQZmr 16374045U, // VPCOMPRESSQZmrk 370170141U, // VPCOMPRESSQZrr 49305885U, // VPCOMPRESSQZrrk 2532333853U, // VPCOMPRESSQZrrkz 1205740U, // VPCOMPRESSWZ128mr 15885804U, // VPCOMPRESSWZ128mrk 370173420U, // VPCOMPRESSWZ128rr 49309164U, // VPCOMPRESSWZ128rrk 2532337132U, // VPCOMPRESSWZ128rrkz 1680876U, // VPCOMPRESSWZ256mr 16360940U, // VPCOMPRESSWZ256mrk 370173420U, // VPCOMPRESSWZ256rr 49309164U, // VPCOMPRESSWZ256rrk 2532337132U, // VPCOMPRESSWZ256rrkz 1697260U, // VPCOMPRESSWZmr 16377324U, // VPCOMPRESSWZmrk 370173420U, // VPCOMPRESSWZrr 49309164U, // VPCOMPRESSWZrrk 2532337132U, // VPCOMPRESSWZrrkz 591015166U, // VPCOMQmi 2517653478U, // VPCOMQmi_alt 591031550U, // VPCOMQri 2517653478U, // VPCOMQri_alt 592063742U, // VPCOMUBmi 2517648892U, // VPCOMUBmi_alt 592080126U, // VPCOMUBri 2517648892U, // VPCOMUBri_alt 593112318U, // VPCOMUDmi 2517651472U, // VPCOMUDmi_alt 593128702U, // VPCOMUDri 2517651472U, // VPCOMUDri_alt 594160894U, // VPCOMUQmi 2517653966U, // VPCOMUQmi_alt 594177278U, // VPCOMUQri 2517653966U, // VPCOMUQri_alt 595209470U, // VPCOMUWmi 2517657202U, // VPCOMUWmi_alt 595225854U, // VPCOMUWri 2517657202U, // VPCOMUWri_alt 596258046U, // VPCOMWmi 2517656809U, // VPCOMWmi_alt 596274430U, // VPCOMWri 2517656809U, // VPCOMWri_alt 336613302U, // VPCONFLICTDZ128rm 2551205814U, // VPCONFLICTDZ128rmb 49303478U, // VPCONFLICTDZ128rmbk 2532331446U, // VPCONFLICTDZ128rmbkz 49303478U, // VPCONFLICTDZ128rmk 2532331446U, // VPCONFLICTDZ128rmkz 370167734U, // VPCONFLICTDZ128rr 49303478U, // VPCONFLICTDZ128rrk 2532331446U, // VPCONFLICTDZ128rrkz 1041256374U, // VPCONFLICTDZ256rm 403722166U, // VPCONFLICTDZ256rmb 49303478U, // VPCONFLICTDZ256rmbk 2532331446U, // VPCONFLICTDZ256rmbkz 49303478U, // VPCONFLICTDZ256rmk 2532331446U, // VPCONFLICTDZ256rmkz 370167734U, // VPCONFLICTDZ256rr 49303478U, // VPCONFLICTDZ256rrk 2532331446U, // VPCONFLICTDZ256rrkz 806375350U, // VPCONFLICTDZrm 2551205814U, // VPCONFLICTDZrmb 49303478U, // VPCONFLICTDZrmbk 2532331446U, // VPCONFLICTDZrmbkz 49303478U, // VPCONFLICTDZrmk 2532331446U, // VPCONFLICTDZrmkz 370167734U, // VPCONFLICTDZrr 49303478U, // VPCONFLICTDZrrk 2532331446U, // VPCONFLICTDZrrkz 336615753U, // VPCONFLICTQZ128rm 437279049U, // VPCONFLICTQZ128rmb 49305929U, // VPCONFLICTQZ128rmbk 2532333897U, // VPCONFLICTQZ128rmbkz 49305929U, // VPCONFLICTQZ128rmk 2532333897U, // VPCONFLICTQZ128rmkz 370170185U, // VPCONFLICTQZ128rr 49305929U, // VPCONFLICTQZ128rrk 2532333897U, // VPCONFLICTQZ128rrkz 1041258825U, // VPCONFLICTQZ256rm 2584762697U, // VPCONFLICTQZ256rmb 49305929U, // VPCONFLICTQZ256rmbk 2532333897U, // VPCONFLICTQZ256rmbkz 49305929U, // VPCONFLICTQZ256rmk 2532333897U, // VPCONFLICTQZ256rmkz 370170185U, // VPCONFLICTQZ256rr 49305929U, // VPCONFLICTQZ256rrk 2532333897U, // VPCONFLICTQZ256rrkz 806377801U, // VPCONFLICTQZrm 437279049U, // VPCONFLICTQZrmb 49305929U, // VPCONFLICTQZrmbk 2532333897U, // VPCONFLICTQZrmbkz 49305929U, // VPCONFLICTQZrmk 2532333897U, // VPCONFLICTQZrmkz 370170185U, // VPCONFLICTQZrr 49305929U, // VPCONFLICTQZrrk 2532333897U, // VPCONFLICTQZrrkz 2182110032U, // VPDPBUSDSZ128m 2182110032U, // VPDPBUSDSZ128mb 49306448U, // VPDPBUSDSZ128mbk 2196790096U, // VPDPBUSDSZ128mbkz 49306448U, // VPDPBUSDSZ128mk 2196790096U, // VPDPBUSDSZ128mkz 2182110032U, // VPDPBUSDSZ128r 49306448U, // VPDPBUSDSZ128rk 2196790096U, // VPDPBUSDSZ128rkz 2182110032U, // VPDPBUSDSZ256m 2182110032U, // VPDPBUSDSZ256mb 49306448U, // VPDPBUSDSZ256mbk 2196790096U, // VPDPBUSDSZ256mbkz 49306448U, // VPDPBUSDSZ256mk 2196790096U, // VPDPBUSDSZ256mkz 2182110032U, // VPDPBUSDSZ256r 49306448U, // VPDPBUSDSZ256rk 2196790096U, // VPDPBUSDSZ256rkz 2182110032U, // VPDPBUSDSZm 2182110032U, // VPDPBUSDSZmb 49306448U, // VPDPBUSDSZmbk 2196790096U, // VPDPBUSDSZmbkz 49306448U, // VPDPBUSDSZmk 2196790096U, // VPDPBUSDSZmkz 2182110032U, // VPDPBUSDSZr 49306448U, // VPDPBUSDSZrk 2196790096U, // VPDPBUSDSZrkz 2182107010U, // VPDPBUSDZ128m 2182107010U, // VPDPBUSDZ128mb 49303426U, // VPDPBUSDZ128mbk 2196787074U, // VPDPBUSDZ128mbkz 49303426U, // VPDPBUSDZ128mk 2196787074U, // VPDPBUSDZ128mkz 2182107010U, // VPDPBUSDZ128r 49303426U, // VPDPBUSDZ128rk 2196787074U, // VPDPBUSDZ128rkz 2182107010U, // VPDPBUSDZ256m 2182107010U, // VPDPBUSDZ256mb 49303426U, // VPDPBUSDZ256mbk 2196787074U, // VPDPBUSDZ256mbkz 49303426U, // VPDPBUSDZ256mk 2196787074U, // VPDPBUSDZ256mkz 2182107010U, // VPDPBUSDZ256r 49303426U, // VPDPBUSDZ256rk 2196787074U, // VPDPBUSDZ256rkz 2182107010U, // VPDPBUSDZm 2182107010U, // VPDPBUSDZmb 49303426U, // VPDPBUSDZmbk 2196787074U, // VPDPBUSDZmbkz 49303426U, // VPDPBUSDZmk 2196787074U, // VPDPBUSDZmkz 2182107010U, // VPDPBUSDZr 49303426U, // VPDPBUSDZrk 2196787074U, // VPDPBUSDZrkz 2182110021U, // VPDPWSSDSZ128m 2182110021U, // VPDPWSSDSZ128mb 49306437U, // VPDPWSSDSZ128mbk 2196790085U, // VPDPWSSDSZ128mbkz 49306437U, // VPDPWSSDSZ128mk 2196790085U, // VPDPWSSDSZ128mkz 2182110021U, // VPDPWSSDSZ128r 49306437U, // VPDPWSSDSZ128rk 2196790085U, // VPDPWSSDSZ128rkz 2182110021U, // VPDPWSSDSZ256m 2182110021U, // VPDPWSSDSZ256mb 49306437U, // VPDPWSSDSZ256mbk 2196790085U, // VPDPWSSDSZ256mbkz 49306437U, // VPDPWSSDSZ256mk 2196790085U, // VPDPWSSDSZ256mkz 2182110021U, // VPDPWSSDSZ256r 49306437U, // VPDPWSSDSZ256rk 2196790085U, // VPDPWSSDSZ256rkz 2182110021U, // VPDPWSSDSZm 2182110021U, // VPDPWSSDSZmb 49306437U, // VPDPWSSDSZmbk 2196790085U, // VPDPWSSDSZmbkz 49306437U, // VPDPWSSDSZmk 2196790085U, // VPDPWSSDSZmkz 2182110021U, // VPDPWSSDSZr 49306437U, // VPDPWSSDSZrk 2196790085U, // VPDPWSSDSZrkz 2182106956U, // VPDPWSSDZ128m 2182106956U, // VPDPWSSDZ128mb 49303372U, // VPDPWSSDZ128mbk 2196787020U, // VPDPWSSDZ128mbkz 49303372U, // VPDPWSSDZ128mk 2196787020U, // VPDPWSSDZ128mkz 2182106956U, // VPDPWSSDZ128r 49303372U, // VPDPWSSDZ128rk 2196787020U, // VPDPWSSDZ128rkz 2182106956U, // VPDPWSSDZ256m 2182106956U, // VPDPWSSDZ256mb 49303372U, // VPDPWSSDZ256mbk 2196787020U, // VPDPWSSDZ256mbkz 49303372U, // VPDPWSSDZ256mk 2196787020U, // VPDPWSSDZ256mkz 2182106956U, // VPDPWSSDZ256r 49303372U, // VPDPWSSDZ256rk 2196787020U, // VPDPWSSDZ256rkz 2182106956U, // VPDPWSSDZm 2182106956U, // VPDPWSSDZmb 49303372U, // VPDPWSSDZmbk 2196787020U, // VPDPWSSDZmbkz 49303372U, // VPDPWSSDZmk 2196787020U, // VPDPWSSDZmkz 2182106956U, // VPDPWSSDZr 49303372U, // VPDPWSSDZrk 2196787020U, // VPDPWSSDZrkz 2517647992U, // VPERM2F128rm 2517647992U, // VPERM2F128rr 2517648047U, // VPERM2I128rm 2517648047U, // VPERM2I128rr 2517648529U, // VPERMBZ128rm 49300625U, // VPERMBZ128rmk 2532328593U, // VPERMBZ128rmkz 2517648529U, // VPERMBZ128rr 49300625U, // VPERMBZ128rrk 2532328593U, // VPERMBZ128rrkz 2517648529U, // VPERMBZ256rm 49300625U, // VPERMBZ256rmk 2532328593U, // VPERMBZ256rmkz 2517648529U, // VPERMBZ256rr 49300625U, // VPERMBZ256rrk 2532328593U, // VPERMBZ256rrkz 2517648529U, // VPERMBZrm 49300625U, // VPERMBZrmk 2532328593U, // VPERMBZrmkz 2517648529U, // VPERMBZrr 49300625U, // VPERMBZrrk 2532328593U, // VPERMBZrrkz 2517649570U, // VPERMDYrm 2517649570U, // VPERMDYrr 2517649570U, // VPERMDZ256rm 2517649570U, // VPERMDZ256rmb 49301666U, // VPERMDZ256rmbk 2532329634U, // VPERMDZ256rmbkz 49301666U, // VPERMDZ256rmk 2532329634U, // VPERMDZ256rmkz 2517649570U, // VPERMDZ256rr 49301666U, // VPERMDZ256rrk 2532329634U, // VPERMDZ256rrkz 2517649570U, // VPERMDZrm 2517649570U, // VPERMDZrmb 49301666U, // VPERMDZrmbk 2532329634U, // VPERMDZrmbkz 49301666U, // VPERMDZrmk 2532329634U, // VPERMDZrmkz 2517649570U, // VPERMDZrr 49301666U, // VPERMDZrrk 2532329634U, // VPERMDZrrkz 2182103939U, // VPERMI2B128rm 49300355U, // VPERMI2B128rmk 2196784003U, // VPERMI2B128rmkz 2182103939U, // VPERMI2B128rr 49300355U, // VPERMI2B128rrk 2196784003U, // VPERMI2B128rrkz 2182103939U, // VPERMI2B256rm 49300355U, // VPERMI2B256rmk 2196784003U, // VPERMI2B256rmkz 2182103939U, // VPERMI2B256rr 49300355U, // VPERMI2B256rrk 2196784003U, // VPERMI2B256rrkz 2182103939U, // VPERMI2Brm 49300355U, // VPERMI2Brmk 2196784003U, // VPERMI2Brmkz 2182103939U, // VPERMI2Brr 49300355U, // VPERMI2Brrk 2196784003U, // VPERMI2Brrkz 2182104801U, // VPERMI2D128rm 2182104801U, // VPERMI2D128rmb 49301217U, // VPERMI2D128rmbk 2196784865U, // VPERMI2D128rmbkz 49301217U, // VPERMI2D128rmk 2196784865U, // VPERMI2D128rmkz 2182104801U, // VPERMI2D128rr 49301217U, // VPERMI2D128rrk 2196784865U, // VPERMI2D128rrkz 2182104801U, // VPERMI2D256rm 2182104801U, // VPERMI2D256rmb 49301217U, // VPERMI2D256rmbk 2196784865U, // VPERMI2D256rmbkz 49301217U, // VPERMI2D256rmk 2196784865U, // VPERMI2D256rmkz 2182104801U, // VPERMI2D256rr 49301217U, // VPERMI2D256rrk 2196784865U, // VPERMI2D256rrkz 2182104801U, // VPERMI2Drm 2182104801U, // VPERMI2Drmb 49301217U, // VPERMI2Drmbk 2196784865U, // VPERMI2Drmbkz 49301217U, // VPERMI2Drmk 2196784865U, // VPERMI2Drmkz 2182104801U, // VPERMI2Drr 49301217U, // VPERMI2Drrk 2196784865U, // VPERMI2Drrkz 2182105497U, // VPERMI2PD128rm 2182105497U, // VPERMI2PD128rmb 49301913U, // VPERMI2PD128rmbk 2196785561U, // VPERMI2PD128rmbkz 49301913U, // VPERMI2PD128rmk 2196785561U, // VPERMI2PD128rmkz 2182105497U, // VPERMI2PD128rr 49301913U, // VPERMI2PD128rrk 2196785561U, // VPERMI2PD128rrkz 2182105497U, // VPERMI2PD256rm 2182105497U, // VPERMI2PD256rmb 49301913U, // VPERMI2PD256rmbk 2196785561U, // VPERMI2PD256rmbkz 49301913U, // VPERMI2PD256rmk 2196785561U, // VPERMI2PD256rmkz 2182105497U, // VPERMI2PD256rr 49301913U, // VPERMI2PD256rrk 2196785561U, // VPERMI2PD256rrkz 2182105497U, // VPERMI2PDrm 2182105497U, // VPERMI2PDrmb 49301913U, // VPERMI2PDrmbk 2196785561U, // VPERMI2PDrmbkz 49301913U, // VPERMI2PDrmk 2196785561U, // VPERMI2PDrmkz 2182105497U, // VPERMI2PDrr 49301913U, // VPERMI2PDrrk 2196785561U, // VPERMI2PDrrkz 2182110292U, // VPERMI2PS128rm 2182110292U, // VPERMI2PS128rmb 49306708U, // VPERMI2PS128rmbk 2196790356U, // VPERMI2PS128rmbkz 49306708U, // VPERMI2PS128rmk 2196790356U, // VPERMI2PS128rmkz 2182110292U, // VPERMI2PS128rr 49306708U, // VPERMI2PS128rrk 2196790356U, // VPERMI2PS128rrkz 2182110292U, // VPERMI2PS256rm 2182110292U, // VPERMI2PS256rmb 49306708U, // VPERMI2PS256rmbk 2196790356U, // VPERMI2PS256rmbkz 49306708U, // VPERMI2PS256rmk 2196790356U, // VPERMI2PS256rmkz 2182110292U, // VPERMI2PS256rr 49306708U, // VPERMI2PS256rrk 2196790356U, // VPERMI2PS256rrkz 2182110292U, // VPERMI2PSrm 2182110292U, // VPERMI2PSrmb 49306708U, // VPERMI2PSrmbk 2196790356U, // VPERMI2PSrmbkz 49306708U, // VPERMI2PSrmk 2196790356U, // VPERMI2PSrmkz 2182110292U, // VPERMI2PSrr 49306708U, // VPERMI2PSrrk 2196790356U, // VPERMI2PSrrkz 2182108590U, // VPERMI2Q128rm 2182108590U, // VPERMI2Q128rmb 49305006U, // VPERMI2Q128rmbk 2196788654U, // VPERMI2Q128rmbkz 49305006U, // VPERMI2Q128rmk 2196788654U, // VPERMI2Q128rmkz 2182108590U, // VPERMI2Q128rr 49305006U, // VPERMI2Q128rrk 2196788654U, // VPERMI2Q128rrkz 2182108590U, // VPERMI2Q256rm 2182108590U, // VPERMI2Q256rmb 49305006U, // VPERMI2Q256rmbk 2196788654U, // VPERMI2Q256rmbkz 49305006U, // VPERMI2Q256rmk 2196788654U, // VPERMI2Q256rmkz 2182108590U, // VPERMI2Q256rr 49305006U, // VPERMI2Q256rrk 2196788654U, // VPERMI2Q256rrkz 2182108590U, // VPERMI2Qrm 2182108590U, // VPERMI2Qrmb 49305006U, // VPERMI2Qrmbk 2196788654U, // VPERMI2Qrmbkz 49305006U, // VPERMI2Qrmk 2196788654U, // VPERMI2Qrmkz 2182108590U, // VPERMI2Qrr 49305006U, // VPERMI2Qrrk 2196788654U, // VPERMI2Qrrkz 2182112037U, // VPERMI2W128rm 49308453U, // VPERMI2W128rmk 2196792101U, // VPERMI2W128rmkz 2182112037U, // VPERMI2W128rr 49308453U, // VPERMI2W128rrk 2196792101U, // VPERMI2W128rrkz 2182112037U, // VPERMI2W256rm 49308453U, // VPERMI2W256rmk 2196792101U, // VPERMI2W256rmkz 2182112037U, // VPERMI2W256rr 49308453U, // VPERMI2W256rrk 2196792101U, // VPERMI2W256rrkz 2182112037U, // VPERMI2Wrm 49308453U, // VPERMI2Wrmk 2196792101U, // VPERMI2Wrmkz 2182112037U, // VPERMI2Wrr 49308453U, // VPERMI2Wrrk 2196792101U, // VPERMI2Wrrkz 2517649838U, // VPERMIL2PDYmr 2517649838U, // VPERMIL2PDYrm 2517649838U, // VPERMIL2PDYrr 2517649838U, // VPERMIL2PDYrr_REV 2517649838U, // VPERMIL2PDmr 2517649838U, // VPERMIL2PDrm 2517649838U, // VPERMIL2PDrr 2517649838U, // VPERMIL2PDrr_REV 2517654633U, // VPERMIL2PSYmr 2517654633U, // VPERMIL2PSYrm 2517654633U, // VPERMIL2PSYrr 2517654633U, // VPERMIL2PSYrr_REV 2517654633U, // VPERMIL2PSmr 2517654633U, // VPERMIL2PSrm 2517654633U, // VPERMIL2PSrr 2517654633U, // VPERMIL2PSrr_REV 3155184544U, // VPERMILPDYmi 2517650336U, // VPERMILPDYri 2517650336U, // VPERMILPDYrm 2517650336U, // VPERMILPDYrr 2752531360U, // VPERMILPDZ128mbi 49302432U, // VPERMILPDZ128mbik 2532330400U, // VPERMILPDZ128mbikz 2819640224U, // VPERMILPDZ128mi 49302432U, // VPERMILPDZ128mik 2532330400U, // VPERMILPDZ128mikz 2517650336U, // VPERMILPDZ128ri 49302432U, // VPERMILPDZ128rik 2532330400U, // VPERMILPDZ128rikz 2517650336U, // VPERMILPDZ128rm 2517650336U, // VPERMILPDZ128rmb 49302432U, // VPERMILPDZ128rmbk 2532330400U, // VPERMILPDZ128rmbkz 49302432U, // VPERMILPDZ128rmk 2532330400U, // VPERMILPDZ128rmkz 2517650336U, // VPERMILPDZ128rr 49302432U, // VPERMILPDZ128rrk 2532330400U, // VPERMILPDZ128rrkz 605047712U, // VPERMILPDZ256mbi 49302432U, // VPERMILPDZ256mbik 2532330400U, // VPERMILPDZ256mbikz 3155184544U, // VPERMILPDZ256mi 49302432U, // VPERMILPDZ256mik 2532330400U, // VPERMILPDZ256mikz 2517650336U, // VPERMILPDZ256ri 49302432U, // VPERMILPDZ256rik 2532330400U, // VPERMILPDZ256rikz 2517650336U, // VPERMILPDZ256rm 2517650336U, // VPERMILPDZ256rmb 49302432U, // VPERMILPDZ256rmbk 2532330400U, // VPERMILPDZ256rmbkz 49302432U, // VPERMILPDZ256rmk 2532330400U, // VPERMILPDZ256rmkz 2517650336U, // VPERMILPDZ256rr 49302432U, // VPERMILPDZ256rrk 2532330400U, // VPERMILPDZ256rrkz 2752531360U, // VPERMILPDZmbi 49302432U, // VPERMILPDZmbik 2532330400U, // VPERMILPDZmbikz 3255847840U, // VPERMILPDZmi 49302432U, // VPERMILPDZmik 2532330400U, // VPERMILPDZmikz 2517650336U, // VPERMILPDZri 49302432U, // VPERMILPDZrik 2532330400U, // VPERMILPDZrikz 2517650336U, // VPERMILPDZrm 2517650336U, // VPERMILPDZrmb 49302432U, // VPERMILPDZrmbk 2532330400U, // VPERMILPDZrmbkz 49302432U, // VPERMILPDZrmk 2532330400U, // VPERMILPDZrmkz 2517650336U, // VPERMILPDZrr 49302432U, // VPERMILPDZrrk 2532330400U, // VPERMILPDZrrkz 2819640224U, // VPERMILPDmi 2517650336U, // VPERMILPDri 2517650336U, // VPERMILPDrm 2517650336U, // VPERMILPDrr 3155189363U, // VPERMILPSYmi 2517655155U, // VPERMILPSYri 2517655155U, // VPERMILPSYrm 2517655155U, // VPERMILPSYrr 638606963U, // VPERMILPSZ128mbi 49307251U, // VPERMILPSZ128mbik 2532335219U, // VPERMILPSZ128mbikz 2819645043U, // VPERMILPSZ128mi 49307251U, // VPERMILPSZ128mik 2532335219U, // VPERMILPSZ128mikz 2517655155U, // VPERMILPSZ128ri 49307251U, // VPERMILPSZ128rik 2532335219U, // VPERMILPSZ128rikz 2517655155U, // VPERMILPSZ128rm 2517655155U, // VPERMILPSZ128rmb 49307251U, // VPERMILPSZ128rmbk 2532335219U, // VPERMILPSZ128rmbkz 49307251U, // VPERMILPSZ128rmk 2532335219U, // VPERMILPSZ128rmkz 2517655155U, // VPERMILPSZ128rr 49307251U, // VPERMILPSZ128rrk 2532335219U, // VPERMILPSZ128rrkz 2786090611U, // VPERMILPSZ256mbi 49307251U, // VPERMILPSZ256mbik 2532335219U, // VPERMILPSZ256mbikz 3155189363U, // VPERMILPSZ256mi 49307251U, // VPERMILPSZ256mik 2532335219U, // VPERMILPSZ256mikz 2517655155U, // VPERMILPSZ256ri 49307251U, // VPERMILPSZ256rik 2532335219U, // VPERMILPSZ256rikz 2517655155U, // VPERMILPSZ256rm 2517655155U, // VPERMILPSZ256rmb 49307251U, // VPERMILPSZ256rmbk 2532335219U, // VPERMILPSZ256rmbkz 49307251U, // VPERMILPSZ256rmk 2532335219U, // VPERMILPSZ256rmkz 2517655155U, // VPERMILPSZ256rr 49307251U, // VPERMILPSZ256rrk 2532335219U, // VPERMILPSZ256rrkz 638606963U, // VPERMILPSZmbi 49307251U, // VPERMILPSZmbik 2532335219U, // VPERMILPSZmbikz 3255852659U, // VPERMILPSZmi 49307251U, // VPERMILPSZmik 2532335219U, // VPERMILPSZmikz 2517655155U, // VPERMILPSZri 49307251U, // VPERMILPSZrik 2532335219U, // VPERMILPSZrikz 2517655155U, // VPERMILPSZrm 2517655155U, // VPERMILPSZrmb 49307251U, // VPERMILPSZrmbk 2532335219U, // VPERMILPSZrmbkz 49307251U, // VPERMILPSZrmk 2532335219U, // VPERMILPSZrmkz 2517655155U, // VPERMILPSZrr 49307251U, // VPERMILPSZrrk 2532335219U, // VPERMILPSZrrkz 2819645043U, // VPERMILPSmi 2517655155U, // VPERMILPSri 2517655155U, // VPERMILPSrm 2517655155U, // VPERMILPSrr 3155184615U, // VPERMPDYmi 2517650407U, // VPERMPDYri 605047783U, // VPERMPDZ256mbi 49302503U, // VPERMPDZ256mbik 2532330471U, // VPERMPDZ256mbikz 3155184615U, // VPERMPDZ256mi 49302503U, // VPERMPDZ256mik 2532330471U, // VPERMPDZ256mikz 2517650407U, // VPERMPDZ256ri 49302503U, // VPERMPDZ256rik 2532330471U, // VPERMPDZ256rikz 2517650407U, // VPERMPDZ256rm 2517650407U, // VPERMPDZ256rmb 49302503U, // VPERMPDZ256rmbk 2532330471U, // VPERMPDZ256rmbkz 49302503U, // VPERMPDZ256rmk 2532330471U, // VPERMPDZ256rmkz 2517650407U, // VPERMPDZ256rr 49302503U, // VPERMPDZ256rrk 2532330471U, // VPERMPDZ256rrkz 2752531431U, // VPERMPDZmbi 49302503U, // VPERMPDZmbik 2532330471U, // VPERMPDZmbikz 3255847911U, // VPERMPDZmi 49302503U, // VPERMPDZmik 2532330471U, // VPERMPDZmikz 2517650407U, // VPERMPDZri 49302503U, // VPERMPDZrik 2532330471U, // VPERMPDZrikz 2517650407U, // VPERMPDZrm 2517650407U, // VPERMPDZrmb 49302503U, // VPERMPDZrmbk 2532330471U, // VPERMPDZrmbkz 49302503U, // VPERMPDZrmk 2532330471U, // VPERMPDZrmkz 2517650407U, // VPERMPDZrr 49302503U, // VPERMPDZrrk 2532330471U, // VPERMPDZrrkz 2517655218U, // VPERMPSYrm 2517655218U, // VPERMPSYrr 2517655218U, // VPERMPSZ256rm 2517655218U, // VPERMPSZ256rmb 49307314U, // VPERMPSZ256rmbk 2532335282U, // VPERMPSZ256rmbkz 49307314U, // VPERMPSZ256rmk 2532335282U, // VPERMPSZ256rmkz 2517655218U, // VPERMPSZ256rr 49307314U, // VPERMPSZ256rrk 2532335282U, // VPERMPSZ256rrkz 2517655218U, // VPERMPSZrm 2517655218U, // VPERMPSZrmb 49307314U, // VPERMPSZrmbk 2532335282U, // VPERMPSZrmbkz 49307314U, // VPERMPSZrmk 2532335282U, // VPERMPSZrmkz 2517655218U, // VPERMPSZrr 49307314U, // VPERMPSZrrk 2532335282U, // VPERMPSZrrkz 3188742126U, // VPERMQYmi 2517653486U, // VPERMQYri 437278702U, // VPERMQZ256mbi 49305582U, // VPERMQZ256mbik 2532333550U, // VPERMQZ256mbikz 3188742126U, // VPERMQZ256mi 49305582U, // VPERMQZ256mik 2532333550U, // VPERMQZ256mikz 2517653486U, // VPERMQZ256ri 49305582U, // VPERMQZ256rik 2532333550U, // VPERMQZ256rikz 2517653486U, // VPERMQZ256rm 2517653486U, // VPERMQZ256rmb 49305582U, // VPERMQZ256rmbk 2532333550U, // VPERMQZ256rmbkz 49305582U, // VPERMQZ256rmk 2532333550U, // VPERMQZ256rmkz 2517653486U, // VPERMQZ256rr 49305582U, // VPERMQZ256rrk 2532333550U, // VPERMQZ256rrkz 2584762350U, // VPERMQZmbi 49305582U, // VPERMQZmbik 2532333550U, // VPERMQZmbikz 2953861102U, // VPERMQZmi 49305582U, // VPERMQZmik 2532333550U, // VPERMQZmikz 2517653486U, // VPERMQZri 49305582U, // VPERMQZrik 2532333550U, // VPERMQZrikz 2517653486U, // VPERMQZrm 2517653486U, // VPERMQZrmb 49305582U, // VPERMQZrmbk 2532333550U, // VPERMQZrmbkz 49305582U, // VPERMQZrmk 2532333550U, // VPERMQZrmkz 2517653486U, // VPERMQZrr 49305582U, // VPERMQZrrk 2532333550U, // VPERMQZrrkz 2182103959U, // VPERMT2B128rm 49300375U, // VPERMT2B128rmk 2196784023U, // VPERMT2B128rmkz 2182103959U, // VPERMT2B128rr 49300375U, // VPERMT2B128rrk 2196784023U, // VPERMT2B128rrkz 2182103959U, // VPERMT2B256rm 49300375U, // VPERMT2B256rmk 2196784023U, // VPERMT2B256rmkz 2182103959U, // VPERMT2B256rr 49300375U, // VPERMT2B256rrk 2196784023U, // VPERMT2B256rrkz 2182103959U, // VPERMT2Brm 49300375U, // VPERMT2Brmk 2196784023U, // VPERMT2Brmkz 2182103959U, // VPERMT2Brr 49300375U, // VPERMT2Brrk 2196784023U, // VPERMT2Brrkz 2182104821U, // VPERMT2D128rm 2182104821U, // VPERMT2D128rmb 49301237U, // VPERMT2D128rmbk 2196784885U, // VPERMT2D128rmbkz 49301237U, // VPERMT2D128rmk 2196784885U, // VPERMT2D128rmkz 2182104821U, // VPERMT2D128rr 49301237U, // VPERMT2D128rrk 2196784885U, // VPERMT2D128rrkz 2182104821U, // VPERMT2D256rm 2182104821U, // VPERMT2D256rmb 49301237U, // VPERMT2D256rmbk 2196784885U, // VPERMT2D256rmbkz 49301237U, // VPERMT2D256rmk 2196784885U, // VPERMT2D256rmkz 2182104821U, // VPERMT2D256rr 49301237U, // VPERMT2D256rrk 2196784885U, // VPERMT2D256rrkz 2182104821U, // VPERMT2Drm 2182104821U, // VPERMT2Drmb 49301237U, // VPERMT2Drmbk 2196784885U, // VPERMT2Drmbkz 49301237U, // VPERMT2Drmk 2196784885U, // VPERMT2Drmkz 2182104821U, // VPERMT2Drr 49301237U, // VPERMT2Drrk 2196784885U, // VPERMT2Drrkz 2182105596U, // VPERMT2PD128rm 2182105596U, // VPERMT2PD128rmb 49302012U, // VPERMT2PD128rmbk 2196785660U, // VPERMT2PD128rmbkz 49302012U, // VPERMT2PD128rmk 2196785660U, // VPERMT2PD128rmkz 2182105596U, // VPERMT2PD128rr 49302012U, // VPERMT2PD128rrk 2196785660U, // VPERMT2PD128rrkz 2182105596U, // VPERMT2PD256rm 2182105596U, // VPERMT2PD256rmb 49302012U, // VPERMT2PD256rmbk 2196785660U, // VPERMT2PD256rmbkz 49302012U, // VPERMT2PD256rmk 2196785660U, // VPERMT2PD256rmkz 2182105596U, // VPERMT2PD256rr 49302012U, // VPERMT2PD256rrk 2196785660U, // VPERMT2PD256rrkz 2182105596U, // VPERMT2PDrm 2182105596U, // VPERMT2PDrmb 49302012U, // VPERMT2PDrmbk 2196785660U, // VPERMT2PDrmbkz 49302012U, // VPERMT2PDrmk 2196785660U, // VPERMT2PDrmkz 2182105596U, // VPERMT2PDrr 49302012U, // VPERMT2PDrrk 2196785660U, // VPERMT2PDrrkz 2182110380U, // VPERMT2PS128rm 2182110380U, // VPERMT2PS128rmb 49306796U, // VPERMT2PS128rmbk 2196790444U, // VPERMT2PS128rmbkz 49306796U, // VPERMT2PS128rmk 2196790444U, // VPERMT2PS128rmkz 2182110380U, // VPERMT2PS128rr 49306796U, // VPERMT2PS128rrk 2196790444U, // VPERMT2PS128rrkz 2182110380U, // VPERMT2PS256rm 2182110380U, // VPERMT2PS256rmb 49306796U, // VPERMT2PS256rmbk 2196790444U, // VPERMT2PS256rmbkz 49306796U, // VPERMT2PS256rmk 2196790444U, // VPERMT2PS256rmkz 2182110380U, // VPERMT2PS256rr 49306796U, // VPERMT2PS256rrk 2196790444U, // VPERMT2PS256rrkz 2182110380U, // VPERMT2PSrm 2182110380U, // VPERMT2PSrmb 49306796U, // VPERMT2PSrmbk 2196790444U, // VPERMT2PSrmbkz 49306796U, // VPERMT2PSrmk 2196790444U, // VPERMT2PSrmkz 2182110380U, // VPERMT2PSrr 49306796U, // VPERMT2PSrrk 2196790444U, // VPERMT2PSrrkz 2182108619U, // VPERMT2Q128rm 2182108619U, // VPERMT2Q128rmb 49305035U, // VPERMT2Q128rmbk 2196788683U, // VPERMT2Q128rmbkz 49305035U, // VPERMT2Q128rmk 2196788683U, // VPERMT2Q128rmkz 2182108619U, // VPERMT2Q128rr 49305035U, // VPERMT2Q128rrk 2196788683U, // VPERMT2Q128rrkz 2182108619U, // VPERMT2Q256rm 2182108619U, // VPERMT2Q256rmb 49305035U, // VPERMT2Q256rmbk 2196788683U, // VPERMT2Q256rmbkz 49305035U, // VPERMT2Q256rmk 2196788683U, // VPERMT2Q256rmkz 2182108619U, // VPERMT2Q256rr 49305035U, // VPERMT2Q256rrk 2196788683U, // VPERMT2Q256rrkz 2182108619U, // VPERMT2Qrm 2182108619U, // VPERMT2Qrmb 49305035U, // VPERMT2Qrmbk 2196788683U, // VPERMT2Qrmbkz 49305035U, // VPERMT2Qrmk 2196788683U, // VPERMT2Qrmkz 2182108619U, // VPERMT2Qrr 49305035U, // VPERMT2Qrrk 2196788683U, // VPERMT2Qrrkz 2182112057U, // VPERMT2W128rm 49308473U, // VPERMT2W128rmk 2196792121U, // VPERMT2W128rmkz 2182112057U, // VPERMT2W128rr 49308473U, // VPERMT2W128rrk 2196792121U, // VPERMT2W128rrkz 2182112057U, // VPERMT2W256rm 49308473U, // VPERMT2W256rmk 2196792121U, // VPERMT2W256rmkz 2182112057U, // VPERMT2W256rr 49308473U, // VPERMT2W256rrk 2196792121U, // VPERMT2W256rrkz 2182112057U, // VPERMT2Wrm 49308473U, // VPERMT2Wrmk 2196792121U, // VPERMT2Wrmkz 2182112057U, // VPERMT2Wrr 49308473U, // VPERMT2Wrrk 2196792121U, // VPERMT2Wrrkz 2517656817U, // VPERMWZ128rm 49308913U, // VPERMWZ128rmk 2532336881U, // VPERMWZ128rmkz 2517656817U, // VPERMWZ128rr 49308913U, // VPERMWZ128rrk 2532336881U, // VPERMWZ128rrkz 2517656817U, // VPERMWZ256rm 49308913U, // VPERMWZ256rmk 2532336881U, // VPERMWZ256rmkz 2517656817U, // VPERMWZ256rr 49308913U, // VPERMWZ256rrk 2532336881U, // VPERMWZ256rrkz 2517656817U, // VPERMWZrm 49308913U, // VPERMWZrmk 2532336881U, // VPERMWZrmkz 2517656817U, // VPERMWZrr 49308913U, // VPERMWZrrk 2532336881U, // VPERMWZrrkz 336610302U, // VPEXPANDBZ128rm 49300478U, // VPEXPANDBZ128rmk 2532328446U, // VPEXPANDBZ128rmkz 370164734U, // VPEXPANDBZ128rr 49300478U, // VPEXPANDBZ128rrk 2532328446U, // VPEXPANDBZ128rrkz 1041253374U, // VPEXPANDBZ256rm 49300478U, // VPEXPANDBZ256rmk 2532328446U, // VPEXPANDBZ256rmkz 370164734U, // VPEXPANDBZ256rr 49300478U, // VPEXPANDBZ256rrk 2532328446U, // VPEXPANDBZ256rrkz 806372350U, // VPEXPANDBZrm 49300478U, // VPEXPANDBZrmk 2532328446U, // VPEXPANDBZrmkz 370164734U, // VPEXPANDBZrr 49300478U, // VPEXPANDBZrrk 2532328446U, // VPEXPANDBZrrkz 336611245U, // VPEXPANDDZ128rm 49301421U, // VPEXPANDDZ128rmk 2532329389U, // VPEXPANDDZ128rmkz 370165677U, // VPEXPANDDZ128rr 49301421U, // VPEXPANDDZ128rrk 2532329389U, // VPEXPANDDZ128rrkz 1041254317U, // VPEXPANDDZ256rm 49301421U, // VPEXPANDDZ256rmk 2532329389U, // VPEXPANDDZ256rmkz 370165677U, // VPEXPANDDZ256rr 49301421U, // VPEXPANDDZ256rrk 2532329389U, // VPEXPANDDZ256rrkz 806373293U, // VPEXPANDDZrm 49301421U, // VPEXPANDDZrmk 2532329389U, // VPEXPANDDZrmkz 370165677U, // VPEXPANDDZrr 49301421U, // VPEXPANDDZrrk 2532329389U, // VPEXPANDDZrrkz 336615111U, // VPEXPANDQZ128rm 49305287U, // VPEXPANDQZ128rmk 2532333255U, // VPEXPANDQZ128rmkz 370169543U, // VPEXPANDQZ128rr 49305287U, // VPEXPANDQZ128rrk 2532333255U, // VPEXPANDQZ128rrkz 1041258183U, // VPEXPANDQZ256rm 49305287U, // VPEXPANDQZ256rmk 2532333255U, // VPEXPANDQZ256rmkz 370169543U, // VPEXPANDQZ256rr 49305287U, // VPEXPANDQZ256rrk 2532333255U, // VPEXPANDQZ256rrkz 806377159U, // VPEXPANDQZrm 49305287U, // VPEXPANDQZrmk 2532333255U, // VPEXPANDQZrmkz 370169543U, // VPEXPANDQZrr 49305287U, // VPEXPANDQZrrk 2532333255U, // VPEXPANDQZrrkz 336618512U, // VPEXPANDWZ128rm 49308688U, // VPEXPANDWZ128rmk 2532336656U, // VPEXPANDWZ128rmkz 370172944U, // VPEXPANDWZ128rr 49308688U, // VPEXPANDWZ128rrk 2532336656U, // VPEXPANDWZ128rrkz 1041261584U, // VPEXPANDWZ256rm 49308688U, // VPEXPANDWZ256rmk 2532336656U, // VPEXPANDWZ256rmkz 370172944U, // VPEXPANDWZ256rr 49308688U, // VPEXPANDWZ256rrk 2532336656U, // VPEXPANDWZ256rrkz 806380560U, // VPEXPANDWZrm 49308688U, // VPEXPANDWZrmk 2532336656U, // VPEXPANDWZrmkz 370172944U, // VPEXPANDWZrr 49308688U, // VPEXPANDWZrrk 2532336656U, // VPEXPANDWZrrkz 2148631871U, // VPEXTRBZmr 2517648703U, // VPEXTRBZrr 2148631871U, // VPEXTRBmr 2517648703U, // VPEXTRBrr 2148601172U, // VPEXTRDZmr 2517650772U, // VPEXTRDZrr 2148601172U, // VPEXTRDmr 2517650772U, // VPEXTRDrr 2148620533U, // VPEXTRQZmr 2517653749U, // VPEXTRQZrr 2148620533U, // VPEXTRQmr 2517653749U, // VPEXTRQrr 2148574587U, // VPEXTRWZmr 2517656955U, // VPEXTRWZrr 2517656955U, // VPEXTRWZrr_REV 2148574587U, // VPEXTRWmr 2517656955U, // VPEXTRWrr 2517656955U, // VPEXTRWrr_REV 1141917634U, // VPGATHERDDYrm 3337635778U, // VPGATHERDDZ128rm 1190152130U, // VPGATHERDDZ256rm 3337635778U, // VPGATHERDDZrm 1209026498U, // VPGATHERDDrm 1141921528U, // VPGATHERDQYrm 3337639672U, // VPGATHERDQZ128rm 1190156024U, // VPGATHERDQZ256rm 3337639672U, // VPGATHERDQZrm 1209030392U, // VPGATHERDQrm 1209027800U, // VPGATHERQDYrm 1190153432U, // VPGATHERQDZ128rm 3337637080U, // VPGATHERQDZ256rm 1190153432U, // VPGATHERQDZrm 1242582232U, // VPGATHERQDrm 1141921899U, // VPGATHERQQYrm 3337640043U, // VPGATHERQQZ128rm 1190156395U, // VPGATHERQQZ256rm 3337640043U, // VPGATHERQQZrm 1209030763U, // VPGATHERQQrm 336611117U, // VPHADDBDrm 370165549U, // VPHADDBDrr 336614885U, // VPHADDBQrm 370169317U, // VPHADDBQrr 336618363U, // VPHADDBWrm 370172795U, // VPHADDBWrr 336615016U, // VPHADDDQrm 370169448U, // VPHADDDQrr 2517649277U, // VPHADDDYrm 2517649277U, // VPHADDDYrr 2517649277U, // VPHADDDrm 2517649277U, // VPHADDDrr 2517657003U, // VPHADDSWYrm 2517657003U, // VPHADDSWYrr 2517657003U, // VPHADDSWrm 2517657003U, // VPHADDSWrr 336611127U, // VPHADDUBDrm 370165559U, // VPHADDUBDrr 336614895U, // VPHADDUBQrm 370169327U, // VPHADDUBQrr 336618407U, // VPHADDUBWrm 370172839U, // VPHADDUBWrr 336615254U, // VPHADDUDQrm 370169686U, // VPHADDUDQrr 336613620U, // VPHADDUWDrm 370168052U, // VPHADDUWDrr 336616016U, // VPHADDUWQrm 370170448U, // VPHADDUWQrr 336613522U, // VPHADDWDrm 370167954U, // VPHADDWDrr 336616006U, // VPHADDWQrm 370170438U, // VPHADDWQrr 2517656552U, // VPHADDWYrm 2517656552U, // VPHADDWYrr 2517656552U, // VPHADDWrm 2517656552U, // VPHADDWrr 336619149U, // VPHMINPOSUWrm 370173581U, // VPHMINPOSUWrr 336618323U, // VPHSUBBWrm 370172755U, // VPHSUBBWrr 336614991U, // VPHSUBDQrm 370169423U, // VPHSUBDQrr 2517649218U, // VPHSUBDYrm 2517649218U, // VPHSUBDYrr 2517649218U, // VPHSUBDrm 2517649218U, // VPHSUBDrr 2517656984U, // VPHSUBSWYrm 2517656984U, // VPHSUBSWYrr 2517656984U, // VPHSUBSWrm 2517656984U, // VPHSUBSWrr 336613512U, // VPHSUBWDrm 370167944U, // VPHSUBWDrr 2517656498U, // VPHSUBWYrm 2517656498U, // VPHSUBWYrr 2517656498U, // VPHSUBWrm 2517656498U, // VPHSUBWrr 2517648684U, // VPINSRBZrm 2517648684U, // VPINSRBZrr 2517648684U, // VPINSRBrm 2517648684U, // VPINSRBrr 2517650753U, // VPINSRDZrm 2517650753U, // VPINSRDZrr 2517650753U, // VPINSRDrm 2517650753U, // VPINSRDrr 2517653730U, // VPINSRQZrm 2517653730U, // VPINSRQZrr 2517653730U, // VPINSRQrm 2517653730U, // VPINSRQrr 2517656936U, // VPINSRWZrm 2517656936U, // VPINSRWZrr 2517656936U, // VPINSRWrm 2517656936U, // VPINSRWrr 336613335U, // VPLZCNTDZ128rm 2551205847U, // VPLZCNTDZ128rmb 49303511U, // VPLZCNTDZ128rmbk 2532331479U, // VPLZCNTDZ128rmbkz 49303511U, // VPLZCNTDZ128rmk 2532331479U, // VPLZCNTDZ128rmkz 370167767U, // VPLZCNTDZ128rr 49303511U, // VPLZCNTDZ128rrk 2532331479U, // VPLZCNTDZ128rrkz 1041256407U, // VPLZCNTDZ256rm 403722199U, // VPLZCNTDZ256rmb 49303511U, // VPLZCNTDZ256rmbk 2532331479U, // VPLZCNTDZ256rmbkz 49303511U, // VPLZCNTDZ256rmk 2532331479U, // VPLZCNTDZ256rmkz 370167767U, // VPLZCNTDZ256rr 49303511U, // VPLZCNTDZ256rrk 2532331479U, // VPLZCNTDZ256rrkz 806375383U, // VPLZCNTDZrm 2551205847U, // VPLZCNTDZrmb 49303511U, // VPLZCNTDZrmbk 2532331479U, // VPLZCNTDZrmbkz 49303511U, // VPLZCNTDZrmk 2532331479U, // VPLZCNTDZrmkz 370167767U, // VPLZCNTDZrr 49303511U, // VPLZCNTDZrrk 2532331479U, // VPLZCNTDZrrkz 336615786U, // VPLZCNTQZ128rm 437279082U, // VPLZCNTQZ128rmb 49305962U, // VPLZCNTQZ128rmbk 2532333930U, // VPLZCNTQZ128rmbkz 49305962U, // VPLZCNTQZ128rmk 2532333930U, // VPLZCNTQZ128rmkz 370170218U, // VPLZCNTQZ128rr 49305962U, // VPLZCNTQZ128rrk 2532333930U, // VPLZCNTQZ128rrkz 1041258858U, // VPLZCNTQZ256rm 2584762730U, // VPLZCNTQZ256rmb 49305962U, // VPLZCNTQZ256rmbk 2532333930U, // VPLZCNTQZ256rmbkz 49305962U, // VPLZCNTQZ256rmk 2532333930U, // VPLZCNTQZ256rmkz 370170218U, // VPLZCNTQZ256rr 49305962U, // VPLZCNTQZ256rrk 2532333930U, // VPLZCNTQZ256rrkz 806377834U, // VPLZCNTQZrm 437279082U, // VPLZCNTQZrmb 49305962U, // VPLZCNTQZrmbk 2532333930U, // VPLZCNTQZrmbkz 49305962U, // VPLZCNTQZrmk 2532333930U, // VPLZCNTQZrmkz 370170218U, // VPLZCNTQZrr 49305962U, // VPLZCNTQZrrk 2532333930U, // VPLZCNTQZrrkz 2517649380U, // VPMACSDDrm 2517649380U, // VPMACSDDrr 2517652078U, // VPMACSDQHrm 2517652078U, // VPMACSDQHrr 2517652445U, // VPMACSDQLrm 2517652445U, // VPMACSDQLrr 2517649390U, // VPMACSSDDrm 2517649390U, // VPMACSSDDrr 2517652089U, // VPMACSSDQHrm 2517652089U, // VPMACSSDQHrr 2517652456U, // VPMACSSDQLrm 2517652456U, // VPMACSSDQLrr 2517651677U, // VPMACSSWDrm 2517651677U, // VPMACSSWDrr 2517657315U, // VPMACSSWWrm 2517657315U, // VPMACSSWWrr 2517651656U, // VPMACSWDrm 2517651656U, // VPMACSWDrr 2517657305U, // VPMACSWWrm 2517657305U, // VPMACSWWrr 2517651688U, // VPMADCSSWDrm 2517651688U, // VPMADCSSWDrr 2517651666U, // VPMADCSWDrm 2517651666U, // VPMADCSWDrr 2182109620U, // VPMADD52HUQZ128m 2182109620U, // VPMADD52HUQZ128mb 49306036U, // VPMADD52HUQZ128mbk 2196789684U, // VPMADD52HUQZ128mbkz 49306036U, // VPMADD52HUQZ128mk 2196789684U, // VPMADD52HUQZ128mkz 2182109620U, // VPMADD52HUQZ128r 49306036U, // VPMADD52HUQZ128rk 2196789684U, // VPMADD52HUQZ128rkz 2182109620U, // VPMADD52HUQZ256m 2182109620U, // VPMADD52HUQZ256mb 49306036U, // VPMADD52HUQZ256mbk 2196789684U, // VPMADD52HUQZ256mbkz 49306036U, // VPMADD52HUQZ256mk 2196789684U, // VPMADD52HUQZ256mkz 2182109620U, // VPMADD52HUQZ256r 49306036U, // VPMADD52HUQZ256rk 2196789684U, // VPMADD52HUQZ256rkz 2182109620U, // VPMADD52HUQZm 2182109620U, // VPMADD52HUQZmb 49306036U, // VPMADD52HUQZmbk 2196789684U, // VPMADD52HUQZmbkz 49306036U, // VPMADD52HUQZmk 2196789684U, // VPMADD52HUQZmkz 2182109620U, // VPMADD52HUQZr 49306036U, // VPMADD52HUQZrk 2196789684U, // VPMADD52HUQZrkz 2182109633U, // VPMADD52LUQZ128m 2182109633U, // VPMADD52LUQZ128mb 49306049U, // VPMADD52LUQZ128mbk 2196789697U, // VPMADD52LUQZ128mbkz 49306049U, // VPMADD52LUQZ128mk 2196789697U, // VPMADD52LUQZ128mkz 2182109633U, // VPMADD52LUQZ128r 49306049U, // VPMADD52LUQZ128rk 2196789697U, // VPMADD52LUQZ128rkz 2182109633U, // VPMADD52LUQZ256m 2182109633U, // VPMADD52LUQZ256mb 49306049U, // VPMADD52LUQZ256mbk 2196789697U, // VPMADD52LUQZ256mbkz 49306049U, // VPMADD52LUQZ256mk 2196789697U, // VPMADD52LUQZ256mkz 2182109633U, // VPMADD52LUQZ256r 49306049U, // VPMADD52LUQZ256rk 2196789697U, // VPMADD52LUQZ256rkz 2182109633U, // VPMADD52LUQZm 2182109633U, // VPMADD52LUQZmb 49306049U, // VPMADD52LUQZmbk 2196789697U, // VPMADD52LUQZmbkz 49306049U, // VPMADD52LUQZmk 2196789697U, // VPMADD52LUQZmkz 2182109633U, // VPMADD52LUQZr 49306049U, // VPMADD52LUQZrk 2196789697U, // VPMADD52LUQZrkz 2517656972U, // VPMADDUBSWYrm 2517656972U, // VPMADDUBSWYrr 2517656972U, // VPMADDUBSWZ128rm 49309068U, // VPMADDUBSWZ128rmk 2532337036U, // VPMADDUBSWZ128rmkz 2517656972U, // VPMADDUBSWZ128rr 49309068U, // VPMADDUBSWZ128rrk 2532337036U, // VPMADDUBSWZ128rrkz 2517656972U, // VPMADDUBSWZ256rm 49309068U, // VPMADDUBSWZ256rmk 2532337036U, // VPMADDUBSWZ256rmkz 2517656972U, // VPMADDUBSWZ256rr 49309068U, // VPMADDUBSWZ256rrk 2532337036U, // VPMADDUBSWZ256rrkz 2517656972U, // VPMADDUBSWZrm 49309068U, // VPMADDUBSWZrmk 2532337036U, // VPMADDUBSWZrmkz 2517656972U, // VPMADDUBSWZrr 49309068U, // VPMADDUBSWZrrk 2532337036U, // VPMADDUBSWZrrkz 2517656972U, // VPMADDUBSWrm 2517656972U, // VPMADDUBSWrr 2517651612U, // VPMADDWDYrm 2517651612U, // VPMADDWDYrr 2517651612U, // VPMADDWDZ128rm 49303708U, // VPMADDWDZ128rmk 2532331676U, // VPMADDWDZ128rmkz 2517651612U, // VPMADDWDZ128rr 49303708U, // VPMADDWDZ128rrk 2532331676U, // VPMADDWDZ128rrkz 2517651612U, // VPMADDWDZ256rm 49303708U, // VPMADDWDZ256rmk 2532331676U, // VPMADDWDZ256rmkz 2517651612U, // VPMADDWDZ256rr 49303708U, // VPMADDWDZ256rrk 2532331676U, // VPMADDWDZ256rrkz 2517651612U, // VPMADDWDZrm 49303708U, // VPMADDWDZrmk 2532331676U, // VPMADDWDZrmkz 2517651612U, // VPMADDWDZrr 49303708U, // VPMADDWDZrrk 2532331676U, // VPMADDWDZrrkz 2517651612U, // VPMADDWDrm 2517651612U, // VPMADDWDrr 2149159020U, // VPMASKMOVDYmr 2517651564U, // VPMASKMOVDYrm 2148683884U, // VPMASKMOVDmr 2517651564U, // VPMASKMOVDrm 2149161514U, // VPMASKMOVQYmr 2517654058U, // VPMASKMOVQYrm 2148686378U, // VPMASKMOVQmr 2517654058U, // VPMASKMOVQrm 2517648810U, // VPMAXSBYrm 2517648810U, // VPMAXSBYrr 2517648810U, // VPMAXSBZ128rm 49300906U, // VPMAXSBZ128rmk 2532328874U, // VPMAXSBZ128rmkz 2517648810U, // VPMAXSBZ128rr 49300906U, // VPMAXSBZ128rrk 2532328874U, // VPMAXSBZ128rrkz 2517648810U, // VPMAXSBZ256rm 49300906U, // VPMAXSBZ256rmk 2532328874U, // VPMAXSBZ256rmkz 2517648810U, // VPMAXSBZ256rr 49300906U, // VPMAXSBZ256rrk 2532328874U, // VPMAXSBZ256rrkz 2517648810U, // VPMAXSBZrm 49300906U, // VPMAXSBZrmk 2532328874U, // VPMAXSBZrmkz 2517648810U, // VPMAXSBZrr 49300906U, // VPMAXSBZrrk 2532328874U, // VPMAXSBZrrkz 2517648810U, // VPMAXSBrm 2517648810U, // VPMAXSBrr 2517651356U, // VPMAXSDYrm 2517651356U, // VPMAXSDYrr 2517651356U, // VPMAXSDZ128rm 2517651356U, // VPMAXSDZ128rmb 49303452U, // VPMAXSDZ128rmbk 2532331420U, // VPMAXSDZ128rmbkz 49303452U, // VPMAXSDZ128rmk 2532331420U, // VPMAXSDZ128rmkz 2517651356U, // VPMAXSDZ128rr 49303452U, // VPMAXSDZ128rrk 2532331420U, // VPMAXSDZ128rrkz 2517651356U, // VPMAXSDZ256rm 2517651356U, // VPMAXSDZ256rmb 49303452U, // VPMAXSDZ256rmbk 2532331420U, // VPMAXSDZ256rmbkz 49303452U, // VPMAXSDZ256rmk 2532331420U, // VPMAXSDZ256rmkz 2517651356U, // VPMAXSDZ256rr 49303452U, // VPMAXSDZ256rrk 2532331420U, // VPMAXSDZ256rrkz 2517651356U, // VPMAXSDZrm 2517651356U, // VPMAXSDZrmb 49303452U, // VPMAXSDZrmbk 2532331420U, // VPMAXSDZrmbkz 49303452U, // VPMAXSDZrmk 2532331420U, // VPMAXSDZrmkz 2517651356U, // VPMAXSDZrr 49303452U, // VPMAXSDZrrk 2532331420U, // VPMAXSDZrrkz 2517651356U, // VPMAXSDrm 2517651356U, // VPMAXSDrr 2517653824U, // VPMAXSQZ128rm 2517653824U, // VPMAXSQZ128rmb 49305920U, // VPMAXSQZ128rmbk 2532333888U, // VPMAXSQZ128rmbkz 49305920U, // VPMAXSQZ128rmk 2532333888U, // VPMAXSQZ128rmkz 2517653824U, // VPMAXSQZ128rr 49305920U, // VPMAXSQZ128rrk 2532333888U, // VPMAXSQZ128rrkz 2517653824U, // VPMAXSQZ256rm 2517653824U, // VPMAXSQZ256rmb 49305920U, // VPMAXSQZ256rmbk 2532333888U, // VPMAXSQZ256rmbkz 49305920U, // VPMAXSQZ256rmk 2532333888U, // VPMAXSQZ256rmkz 2517653824U, // VPMAXSQZ256rr 49305920U, // VPMAXSQZ256rrk 2532333888U, // VPMAXSQZ256rrkz 2517653824U, // VPMAXSQZrm 2517653824U, // VPMAXSQZrmb 49305920U, // VPMAXSQZrmbk 2532333888U, // VPMAXSQZrmbkz 49305920U, // VPMAXSQZrmk 2532333888U, // VPMAXSQZrmkz 2517653824U, // VPMAXSQZrr 49305920U, // VPMAXSQZrrk 2532333888U, // VPMAXSQZrrkz 2517657116U, // VPMAXSWYrm 2517657116U, // VPMAXSWYrr 2517657116U, // VPMAXSWZ128rm 49309212U, // VPMAXSWZ128rmk 2532337180U, // VPMAXSWZ128rmkz 2517657116U, // VPMAXSWZ128rr 49309212U, // VPMAXSWZ128rrk 2532337180U, // VPMAXSWZ128rrkz 2517657116U, // VPMAXSWZ256rm 49309212U, // VPMAXSWZ256rmk 2532337180U, // VPMAXSWZ256rmkz 2517657116U, // VPMAXSWZ256rr 49309212U, // VPMAXSWZ256rrk 2532337180U, // VPMAXSWZ256rrkz 2517657116U, // VPMAXSWZrm 49309212U, // VPMAXSWZrmk 2532337180U, // VPMAXSWZrmkz 2517657116U, // VPMAXSWZrr 49309212U, // VPMAXSWZrrk 2532337180U, // VPMAXSWZrrkz 2517657116U, // VPMAXSWrm 2517657116U, // VPMAXSWrr 2517648933U, // VPMAXUBYrm 2517648933U, // VPMAXUBYrr 2517648933U, // VPMAXUBZ128rm 49301029U, // VPMAXUBZ128rmk 2532328997U, // VPMAXUBZ128rmkz 2517648933U, // VPMAXUBZ128rr 49301029U, // VPMAXUBZ128rrk 2532328997U, // VPMAXUBZ128rrkz 2517648933U, // VPMAXUBZ256rm 49301029U, // VPMAXUBZ256rmk 2532328997U, // VPMAXUBZ256rmkz 2517648933U, // VPMAXUBZ256rr 49301029U, // VPMAXUBZ256rrk 2532328997U, // VPMAXUBZ256rrkz 2517648933U, // VPMAXUBZrm 49301029U, // VPMAXUBZrmk 2532328997U, // VPMAXUBZrmkz 2517648933U, // VPMAXUBZrr 49301029U, // VPMAXUBZrrk 2532328997U, // VPMAXUBZrrkz 2517648933U, // VPMAXUBrm 2517648933U, // VPMAXUBrr 2517651499U, // VPMAXUDYrm 2517651499U, // VPMAXUDYrr 2517651499U, // VPMAXUDZ128rm 2517651499U, // VPMAXUDZ128rmb 49303595U, // VPMAXUDZ128rmbk 2532331563U, // VPMAXUDZ128rmbkz 49303595U, // VPMAXUDZ128rmk 2532331563U, // VPMAXUDZ128rmkz 2517651499U, // VPMAXUDZ128rr 49303595U, // VPMAXUDZ128rrk 2532331563U, // VPMAXUDZ128rrkz 2517651499U, // VPMAXUDZ256rm 2517651499U, // VPMAXUDZ256rmb 49303595U, // VPMAXUDZ256rmbk 2532331563U, // VPMAXUDZ256rmbkz 49303595U, // VPMAXUDZ256rmk 2532331563U, // VPMAXUDZ256rmkz 2517651499U, // VPMAXUDZ256rr 49303595U, // VPMAXUDZ256rrk 2532331563U, // VPMAXUDZ256rrkz 2517651499U, // VPMAXUDZrm 2517651499U, // VPMAXUDZrmb 49303595U, // VPMAXUDZrmbk 2532331563U, // VPMAXUDZrmbkz 49303595U, // VPMAXUDZrmk 2532331563U, // VPMAXUDZrmkz 2517651499U, // VPMAXUDZrr 49303595U, // VPMAXUDZrrk 2532331563U, // VPMAXUDZrrkz 2517651499U, // VPMAXUDrm 2517651499U, // VPMAXUDrr 2517653993U, // VPMAXUQZ128rm 2517653993U, // VPMAXUQZ128rmb 49306089U, // VPMAXUQZ128rmbk 2532334057U, // VPMAXUQZ128rmbkz 49306089U, // VPMAXUQZ128rmk 2532334057U, // VPMAXUQZ128rmkz 2517653993U, // VPMAXUQZ128rr 49306089U, // VPMAXUQZ128rrk 2532334057U, // VPMAXUQZ128rrkz 2517653993U, // VPMAXUQZ256rm 2517653993U, // VPMAXUQZ256rmb 49306089U, // VPMAXUQZ256rmbk 2532334057U, // VPMAXUQZ256rmbkz 49306089U, // VPMAXUQZ256rmk 2532334057U, // VPMAXUQZ256rmkz 2517653993U, // VPMAXUQZ256rr 49306089U, // VPMAXUQZ256rrk 2532334057U, // VPMAXUQZ256rrkz 2517653993U, // VPMAXUQZrm 2517653993U, // VPMAXUQZrmb 49306089U, // VPMAXUQZrmbk 2532334057U, // VPMAXUQZrmbkz 49306089U, // VPMAXUQZrmk 2532334057U, // VPMAXUQZrmkz 2517653993U, // VPMAXUQZrr 49306089U, // VPMAXUQZrrk 2532334057U, // VPMAXUQZrrkz 2517657242U, // VPMAXUWYrm 2517657242U, // VPMAXUWYrr 2517657242U, // VPMAXUWZ128rm 49309338U, // VPMAXUWZ128rmk 2532337306U, // VPMAXUWZ128rmkz 2517657242U, // VPMAXUWZ128rr 49309338U, // VPMAXUWZ128rrk 2532337306U, // VPMAXUWZ128rrkz 2517657242U, // VPMAXUWZ256rm 49309338U, // VPMAXUWZ256rmk 2532337306U, // VPMAXUWZ256rmkz 2517657242U, // VPMAXUWZ256rr 49309338U, // VPMAXUWZ256rrk 2532337306U, // VPMAXUWZ256rrkz 2517657242U, // VPMAXUWZrm 49309338U, // VPMAXUWZrmk 2532337306U, // VPMAXUWZrmkz 2517657242U, // VPMAXUWZrr 49309338U, // VPMAXUWZrrk 2532337306U, // VPMAXUWZrrkz 2517657242U, // VPMAXUWrm 2517657242U, // VPMAXUWrr 2517648738U, // VPMINSBYrm 2517648738U, // VPMINSBYrr 2517648738U, // VPMINSBZ128rm 49300834U, // VPMINSBZ128rmk 2532328802U, // VPMINSBZ128rmkz 2517648738U, // VPMINSBZ128rr 49300834U, // VPMINSBZ128rrk 2532328802U, // VPMINSBZ128rrkz 2517648738U, // VPMINSBZ256rm 49300834U, // VPMINSBZ256rmk 2532328802U, // VPMINSBZ256rmkz 2517648738U, // VPMINSBZ256rr 49300834U, // VPMINSBZ256rrk 2532328802U, // VPMINSBZ256rrkz 2517648738U, // VPMINSBZrm 49300834U, // VPMINSBZrmk 2532328802U, // VPMINSBZrmkz 2517648738U, // VPMINSBZrr 49300834U, // VPMINSBZrrk 2532328802U, // VPMINSBZrrkz 2517648738U, // VPMINSBrm 2517648738U, // VPMINSBrr 2517651182U, // VPMINSDYrm 2517651182U, // VPMINSDYrr 2517651182U, // VPMINSDZ128rm 2517651182U, // VPMINSDZ128rmb 49303278U, // VPMINSDZ128rmbk 2532331246U, // VPMINSDZ128rmbkz 49303278U, // VPMINSDZ128rmk 2532331246U, // VPMINSDZ128rmkz 2517651182U, // VPMINSDZ128rr 49303278U, // VPMINSDZ128rrk 2532331246U, // VPMINSDZ128rrkz 2517651182U, // VPMINSDZ256rm 2517651182U, // VPMINSDZ256rmb 49303278U, // VPMINSDZ256rmbk 2532331246U, // VPMINSDZ256rmbkz 49303278U, // VPMINSDZ256rmk 2532331246U, // VPMINSDZ256rmkz 2517651182U, // VPMINSDZ256rr 49303278U, // VPMINSDZ256rrk 2532331246U, // VPMINSDZ256rrkz 2517651182U, // VPMINSDZrm 2517651182U, // VPMINSDZrmb 49303278U, // VPMINSDZrmbk 2532331246U, // VPMINSDZrmbkz 49303278U, // VPMINSDZrmk 2532331246U, // VPMINSDZrmkz 2517651182U, // VPMINSDZrr 49303278U, // VPMINSDZrrk 2532331246U, // VPMINSDZrrkz 2517651182U, // VPMINSDrm 2517651182U, // VPMINSDrr 2517653766U, // VPMINSQZ128rm 2517653766U, // VPMINSQZ128rmb 49305862U, // VPMINSQZ128rmbk 2532333830U, // VPMINSQZ128rmbkz 49305862U, // VPMINSQZ128rmk 2532333830U, // VPMINSQZ128rmkz 2517653766U, // VPMINSQZ128rr 49305862U, // VPMINSQZ128rrk 2532333830U, // VPMINSQZ128rrkz 2517653766U, // VPMINSQZ256rm 2517653766U, // VPMINSQZ256rmb 49305862U, // VPMINSQZ256rmbk 2532333830U, // VPMINSQZ256rmbkz 49305862U, // VPMINSQZ256rmk 2532333830U, // VPMINSQZ256rmkz 2517653766U, // VPMINSQZ256rr 49305862U, // VPMINSQZ256rrk 2532333830U, // VPMINSQZ256rrkz 2517653766U, // VPMINSQZrm 2517653766U, // VPMINSQZrmb 49305862U, // VPMINSQZrmbk 2532333830U, // VPMINSQZrmbkz 49305862U, // VPMINSQZrmk 2532333830U, // VPMINSQZrmkz 2517653766U, // VPMINSQZrr 49305862U, // VPMINSQZrrk 2532333830U, // VPMINSQZrrkz 2517657034U, // VPMINSWYrm 2517657034U, // VPMINSWYrr 2517657034U, // VPMINSWZ128rm 49309130U, // VPMINSWZ128rmk 2532337098U, // VPMINSWZ128rmkz 2517657034U, // VPMINSWZ128rr 49309130U, // VPMINSWZ128rrk 2532337098U, // VPMINSWZ128rrkz 2517657034U, // VPMINSWZ256rm 49309130U, // VPMINSWZ256rmk 2532337098U, // VPMINSWZ256rmkz 2517657034U, // VPMINSWZ256rr 49309130U, // VPMINSWZ256rrk 2532337098U, // VPMINSWZ256rrkz 2517657034U, // VPMINSWZrm 49309130U, // VPMINSWZrmk 2532337098U, // VPMINSWZrmkz 2517657034U, // VPMINSWZrr 49309130U, // VPMINSWZrrk 2532337098U, // VPMINSWZrrkz 2517657034U, // VPMINSWrm 2517657034U, // VPMINSWrr 2517648901U, // VPMINUBYrm 2517648901U, // VPMINUBYrr 2517648901U, // VPMINUBZ128rm 49300997U, // VPMINUBZ128rmk 2532328965U, // VPMINUBZ128rmkz 2517648901U, // VPMINUBZ128rr 49300997U, // VPMINUBZ128rrk 2532328965U, // VPMINUBZ128rrkz 2517648901U, // VPMINUBZ256rm 49300997U, // VPMINUBZ256rmk 2532328965U, // VPMINUBZ256rmkz 2517648901U, // VPMINUBZ256rr 49300997U, // VPMINUBZ256rrk 2532328965U, // VPMINUBZ256rrkz 2517648901U, // VPMINUBZrm 49300997U, // VPMINUBZrmk 2532328965U, // VPMINUBZrmkz 2517648901U, // VPMINUBZrr 49300997U, // VPMINUBZrrk 2532328965U, // VPMINUBZrrkz 2517648901U, // VPMINUBrm 2517648901U, // VPMINUBrr 2517651481U, // VPMINUDYrm 2517651481U, // VPMINUDYrr 2517651481U, // VPMINUDZ128rm 2517651481U, // VPMINUDZ128rmb 49303577U, // VPMINUDZ128rmbk 2532331545U, // VPMINUDZ128rmbkz 49303577U, // VPMINUDZ128rmk 2532331545U, // VPMINUDZ128rmkz 2517651481U, // VPMINUDZ128rr 49303577U, // VPMINUDZ128rrk 2532331545U, // VPMINUDZ128rrkz 2517651481U, // VPMINUDZ256rm 2517651481U, // VPMINUDZ256rmb 49303577U, // VPMINUDZ256rmbk 2532331545U, // VPMINUDZ256rmbkz 49303577U, // VPMINUDZ256rmk 2532331545U, // VPMINUDZ256rmkz 2517651481U, // VPMINUDZ256rr 49303577U, // VPMINUDZ256rrk 2532331545U, // VPMINUDZ256rrkz 2517651481U, // VPMINUDZrm 2517651481U, // VPMINUDZrmb 49303577U, // VPMINUDZrmbk 2532331545U, // VPMINUDZrmbkz 49303577U, // VPMINUDZrmk 2532331545U, // VPMINUDZrmkz 2517651481U, // VPMINUDZrr 49303577U, // VPMINUDZrrk 2532331545U, // VPMINUDZrrkz 2517651481U, // VPMINUDrm 2517651481U, // VPMINUDrr 2517653975U, // VPMINUQZ128rm 2517653975U, // VPMINUQZ128rmb 49306071U, // VPMINUQZ128rmbk 2532334039U, // VPMINUQZ128rmbkz 49306071U, // VPMINUQZ128rmk 2532334039U, // VPMINUQZ128rmkz 2517653975U, // VPMINUQZ128rr 49306071U, // VPMINUQZ128rrk 2532334039U, // VPMINUQZ128rrkz 2517653975U, // VPMINUQZ256rm 2517653975U, // VPMINUQZ256rmb 49306071U, // VPMINUQZ256rmbk 2532334039U, // VPMINUQZ256rmbkz 49306071U, // VPMINUQZ256rmk 2532334039U, // VPMINUQZ256rmkz 2517653975U, // VPMINUQZ256rr 49306071U, // VPMINUQZ256rrk 2532334039U, // VPMINUQZ256rrkz 2517653975U, // VPMINUQZrm 2517653975U, // VPMINUQZrmb 49306071U, // VPMINUQZrmbk 2532334039U, // VPMINUQZrmbkz 49306071U, // VPMINUQZrmk 2532334039U, // VPMINUQZrmkz 2517653975U, // VPMINUQZrr 49306071U, // VPMINUQZrrk 2532334039U, // VPMINUQZrrkz 2517657211U, // VPMINUWYrm 2517657211U, // VPMINUWYrr 2517657211U, // VPMINUWZ128rm 49309307U, // VPMINUWZ128rmk 2532337275U, // VPMINUWZ128rmkz 2517657211U, // VPMINUWZ128rr 49309307U, // VPMINUWZ128rrk 2532337275U, // VPMINUWZ128rrkz 2517657211U, // VPMINUWZ256rm 49309307U, // VPMINUWZ256rmk 2532337275U, // VPMINUWZ256rmkz 2517657211U, // VPMINUWZ256rr 49309307U, // VPMINUWZ256rrk 2532337275U, // VPMINUWZ256rrkz 2517657211U, // VPMINUWZrm 49309307U, // VPMINUWZrmk 2532337275U, // VPMINUWZrmkz 2517657211U, // VPMINUWZrr 49309307U, // VPMINUWZrrk 2532337275U, // VPMINUWZrrkz 2517657211U, // VPMINUWrm 2517657211U, // VPMINUWrr 370168852U, // VPMOVB2MZ128rr 370168852U, // VPMOVB2MZ256rr 370168852U, // VPMOVB2MZrr 370168862U, // VPMOVD2MZ128rr 370168862U, // VPMOVD2MZ256rr 370168862U, // VPMOVD2MZrr 1115166U, // VPMOVDBZ128mr 15795230U, // VPMOVDBZ128mrk 370164766U, // VPMOVDBZ128rr 49300510U, // VPMOVDBZ128rrk 2532328478U, // VPMOVDBZ128rrkz 1131550U, // VPMOVDBZ256mr 15811614U, // VPMOVDBZ256mrk 370164766U, // VPMOVDBZ256rr 49300510U, // VPMOVDBZ256rrk 2532328478U, // VPMOVDBZ256rrkz 1197086U, // VPMOVDBZmr 15877150U, // VPMOVDBZmrk 370164766U, // VPMOVDBZrr 49300510U, // VPMOVDBZrrk 2532328478U, // VPMOVDBZrrkz 1139801U, // VPMOVDWZ128mr 15819865U, // VPMOVDWZ128mrk 370173017U, // VPMOVDWZ128rr 49308761U, // VPMOVDWZ128rrk 2532336729U, // VPMOVDWZ128rrkz 1205337U, // VPMOVDWZ256mr 15885401U, // VPMOVDWZ256mrk 370173017U, // VPMOVDWZ256rr 49308761U, // VPMOVDWZ256rrk 2532336729U, // VPMOVDWZ256rrkz 1680473U, // VPMOVDWZmr 16360537U, // VPMOVDWZmrk 370173017U, // VPMOVDWZrr 49308761U, // VPMOVDWZrrk 2532336729U, // VPMOVDWZrrkz 370164621U, // VPMOVM2BZ128rr 370164621U, // VPMOVM2BZ256rr 370164621U, // VPMOVM2BZrr 370165483U, // VPMOVM2DZ128rr 370165483U, // VPMOVM2DZ256rr 370165483U, // VPMOVM2DZrr 370169272U, // VPMOVM2QZ128rr 370169272U, // VPMOVM2QZ256rr 370169272U, // VPMOVM2QZrr 370172719U, // VPMOVM2WZ128rr 370172719U, // VPMOVM2WZ256rr 370172719U, // VPMOVM2WZrr 370164796U, // VPMOVMSKBYrr 370164796U, // VPMOVMSKBrr 370168872U, // VPMOVQ2MZ128rr 370168872U, // VPMOVQ2MZ256rr 370168872U, // VPMOVQ2MZrr 1082638U, // VPMOVQBZ128mr 15762702U, // VPMOVQBZ128mrk 370165006U, // VPMOVQBZ128rr 49300750U, // VPMOVQBZ128rrk 2532328718U, // VPMOVQBZ128rrkz 1115406U, // VPMOVQBZ256mr 15795470U, // VPMOVQBZ256mrk 370165006U, // VPMOVQBZ256rr 49300750U, // VPMOVQBZ256rrk 2532328718U, // VPMOVQBZ256rrkz 1131790U, // VPMOVQBZmr 15811854U, // VPMOVQBZmrk 370165006U, // VPMOVQBZrr 49300750U, // VPMOVQBZrrk 2532328718U, // VPMOVQBZrrkz 1133830U, // VPMOVQDZ128mr 15813894U, // VPMOVQDZ128mrk 370167046U, // VPMOVQDZ128rr 49302790U, // VPMOVQDZ128rrk 2532330758U, // VPMOVQDZ128rrkz 1199366U, // VPMOVQDZ256mr 15879430U, // VPMOVQDZ256mrk 370167046U, // VPMOVQDZ256rr 49302790U, // VPMOVQDZ256rrk 2532330758U, // VPMOVQDZ256rrkz 1674502U, // VPMOVQDZmr 16354566U, // VPMOVQDZmrk 370167046U, // VPMOVQDZrr 49302790U, // VPMOVQDZrrk 2532330758U, // VPMOVQDZrrkz 1123643U, // VPMOVQWZ128mr 15803707U, // VPMOVQWZ128mrk 370173243U, // VPMOVQWZ128rr 49308987U, // VPMOVQWZ128rrk 2532336955U, // VPMOVQWZ128rrkz 1140027U, // VPMOVQWZ256mr 15820091U, // VPMOVQWZ256mrk 370173243U, // VPMOVQWZ256rr 49308987U, // VPMOVQWZ256rrk 2532336955U, // VPMOVQWZ256rrkz 1205563U, // VPMOVQWZmr 15885627U, // VPMOVQWZmrk 370173243U, // VPMOVQWZrr 49308987U, // VPMOVQWZrrk 2532336955U, // VPMOVQWZrrkz 1115156U, // VPMOVSDBZ128mr 15795220U, // VPMOVSDBZ128mrk 370164756U, // VPMOVSDBZ128rr 49300500U, // VPMOVSDBZ128rrk 2532328468U, // VPMOVSDBZ128rrkz 1131540U, // VPMOVSDBZ256mr 15811604U, // VPMOVSDBZ256mrk 370164756U, // VPMOVSDBZ256rr 49300500U, // VPMOVSDBZ256rrk 2532328468U, // VPMOVSDBZ256rrkz 1197076U, // VPMOVSDBZmr 15877140U, // VPMOVSDBZmrk 370164756U, // VPMOVSDBZrr 49300500U, // VPMOVSDBZrrk 2532328468U, // VPMOVSDBZrrkz 1139791U, // VPMOVSDWZ128mr 15819855U, // VPMOVSDWZ128mrk 370173007U, // VPMOVSDWZ128rr 49308751U, // VPMOVSDWZ128rrk 2532336719U, // VPMOVSDWZ128rrkz 1205327U, // VPMOVSDWZ256mr 15885391U, // VPMOVSDWZ256mrk 370173007U, // VPMOVSDWZ256rr 49308751U, // VPMOVSDWZ256rrk 2532336719U, // VPMOVSDWZ256rrkz 1680463U, // VPMOVSDWZmr 16360527U, // VPMOVSDWZmrk 370173007U, // VPMOVSDWZrr 49308751U, // VPMOVSDWZrrk 2532336719U, // VPMOVSDWZrrkz 1082593U, // VPMOVSQBZ128mr 15762657U, // VPMOVSQBZ128mrk 370164961U, // VPMOVSQBZ128rr 49300705U, // VPMOVSQBZ128rrk 2532328673U, // VPMOVSQBZ128rrkz 1115361U, // VPMOVSQBZ256mr 15795425U, // VPMOVSQBZ256mrk 370164961U, // VPMOVSQBZ256rr 49300705U, // VPMOVSQBZ256rrk 2532328673U, // VPMOVSQBZ256rrkz 1131745U, // VPMOVSQBZmr 15811809U, // VPMOVSQBZmrk 370164961U, // VPMOVSQBZrr 49300705U, // VPMOVSQBZrrk 2532328673U, // VPMOVSQBZrrkz 1133820U, // VPMOVSQDZ128mr 15813884U, // VPMOVSQDZ128mrk 370167036U, // VPMOVSQDZ128rr 49302780U, // VPMOVSQDZ128rrk 2532330748U, // VPMOVSQDZ128rrkz 1199356U, // VPMOVSQDZ256mr 15879420U, // VPMOVSQDZ256mrk 370167036U, // VPMOVSQDZ256rr 49302780U, // VPMOVSQDZ256rrk 2532330748U, // VPMOVSQDZ256rrkz 1674492U, // VPMOVSQDZmr 16354556U, // VPMOVSQDZmrk 370167036U, // VPMOVSQDZrr 49302780U, // VPMOVSQDZrrk 2532330748U, // VPMOVSQDZrrkz 1123633U, // VPMOVSQWZ128mr 15803697U, // VPMOVSQWZ128mrk 370173233U, // VPMOVSQWZ128rr 49308977U, // VPMOVSQWZ128rrk 2532336945U, // VPMOVSQWZ128rrkz 1140017U, // VPMOVSQWZ256mr 15820081U, // VPMOVSQWZ256mrk 370173233U, // VPMOVSQWZ256rr 49308977U, // VPMOVSQWZ256rrk 2532336945U, // VPMOVSQWZ256rrkz 1205553U, // VPMOVSQWZmr 15885617U, // VPMOVSQWZmrk 370173233U, // VPMOVSQWZrr 49308977U, // VPMOVSQWZrrk 2532336945U, // VPMOVSQWZrrkz 1132142U, // VPMOVSWBZ128mr 15812206U, // VPMOVSWBZ128mrk 370165358U, // VPMOVSWBZ128rr 49301102U, // VPMOVSWBZ128rrk 2532329070U, // VPMOVSWBZ128rrkz 1197678U, // VPMOVSWBZ256mr 15877742U, // VPMOVSWBZ256mrk 370165358U, // VPMOVSWBZ256rr 49301102U, // VPMOVSWBZ256rrk 2532329070U, // VPMOVSWBZ256rrkz 1672814U, // VPMOVSWBZmr 16352878U, // VPMOVSWBZmrk 370165358U, // VPMOVSWBZrr 49301102U, // VPMOVSWBZrrk 2532329070U, // VPMOVSWBZrrkz 437274451U, // VPMOVSXBDYrm 370165587U, // VPMOVSXBDYrr 403720019U, // VPMOVSXBDZ128rm 49301331U, // VPMOVSXBDZ128rmk 2532329299U, // VPMOVSXBDZ128rmkz 370165587U, // VPMOVSXBDZ128rr 49301331U, // VPMOVSXBDZ128rrk 2532329299U, // VPMOVSXBDZ128rrkz 437274451U, // VPMOVSXBDZ256rm 49301331U, // VPMOVSXBDZ256rmk 2532329299U, // VPMOVSXBDZ256rmkz 370165587U, // VPMOVSXBDZ256rr 49301331U, // VPMOVSXBDZ256rrk 2532329299U, // VPMOVSXBDZ256rrkz 336611155U, // VPMOVSXBDZrm 49301331U, // VPMOVSXBDZrmk 2532329299U, // VPMOVSXBDZrmkz 370165587U, // VPMOVSXBDZrr 49301331U, // VPMOVSXBDZrrk 2532329299U, // VPMOVSXBDZrrkz 403720019U, // VPMOVSXBDrm 370165587U, // VPMOVSXBDrr 403723778U, // VPMOVSXBQYrm 370169346U, // VPMOVSXBQYrr 504387074U, // VPMOVSXBQZ128rm 49305090U, // VPMOVSXBQZ128rmk 2532333058U, // VPMOVSXBQZ128rmkz 370169346U, // VPMOVSXBQZ128rr 49305090U, // VPMOVSXBQZ128rrk 2532333058U, // VPMOVSXBQZ128rrkz 403723778U, // VPMOVSXBQZ256rm 49305090U, // VPMOVSXBQZ256rmk 2532333058U, // VPMOVSXBQZ256rmkz 370169346U, // VPMOVSXBQZ256rr 49305090U, // VPMOVSXBQZ256rrk 2532333058U, // VPMOVSXBQZ256rrkz 437278210U, // VPMOVSXBQZrm 49305090U, // VPMOVSXBQZrmk 2532333058U, // VPMOVSXBQZrmkz 370169346U, // VPMOVSXBQZrr 49305090U, // VPMOVSXBQZrrk 2532333058U, // VPMOVSXBQZrrkz 504387074U, // VPMOVSXBQrm 370169346U, // VPMOVSXBQrr 336618435U, // VPMOVSXBWYrm 370172867U, // VPMOVSXBWYrr 437281731U, // VPMOVSXBWZ128rm 49308611U, // VPMOVSXBWZ128rmk 2532336579U, // VPMOVSXBWZ128rmkz 370172867U, // VPMOVSXBWZ128rr 49308611U, // VPMOVSXBWZ128rrk 2532336579U, // VPMOVSXBWZ128rrkz 336618435U, // VPMOVSXBWZ256rm 49308611U, // VPMOVSXBWZ256rmk 2532336579U, // VPMOVSXBWZ256rmkz 370172867U, // VPMOVSXBWZ256rr 49308611U, // VPMOVSXBWZ256rrk 2532336579U, // VPMOVSXBWZ256rrkz 1041261507U, // VPMOVSXBWZrm 49308611U, // VPMOVSXBWZrmk 2532336579U, // VPMOVSXBWZrmkz 370172867U, // VPMOVSXBWZrr 49308611U, // VPMOVSXBWZrrk 2532336579U, // VPMOVSXBWZrrkz 437281731U, // VPMOVSXBWrm 370172867U, // VPMOVSXBWrr 336615275U, // VPMOVSXDQYrm 370169707U, // VPMOVSXDQYrr 437278571U, // VPMOVSXDQZ128rm 49305451U, // VPMOVSXDQZ128rmk 2532333419U, // VPMOVSXDQZ128rmkz 370169707U, // VPMOVSXDQZ128rr 49305451U, // VPMOVSXDQZ128rrk 2532333419U, // VPMOVSXDQZ128rrkz 336615275U, // VPMOVSXDQZ256rm 49305451U, // VPMOVSXDQZ256rmk 2532333419U, // VPMOVSXDQZ256rmkz 370169707U, // VPMOVSXDQZ256rr 49305451U, // VPMOVSXDQZ256rrk 2532333419U, // VPMOVSXDQZ256rrkz 1041258347U, // VPMOVSXDQZrm 49305451U, // VPMOVSXDQZrmk 2532333419U, // VPMOVSXDQZrmkz 370169707U, // VPMOVSXDQZrr 49305451U, // VPMOVSXDQZrrk 2532333419U, // VPMOVSXDQZrrkz 437278571U, // VPMOVSXDQrm 370169707U, // VPMOVSXDQrr 336613631U, // VPMOVSXWDYrm 370168063U, // VPMOVSXWDYrr 437276927U, // VPMOVSXWDZ128rm 49303807U, // VPMOVSXWDZ128rmk 2532331775U, // VPMOVSXWDZ128rmkz 370168063U, // VPMOVSXWDZ128rr 49303807U, // VPMOVSXWDZ128rrk 2532331775U, // VPMOVSXWDZ128rrkz 336613631U, // VPMOVSXWDZ256rm 49303807U, // VPMOVSXWDZ256rmk 2532331775U, // VPMOVSXWDZ256rmkz 370168063U, // VPMOVSXWDZ256rr 49303807U, // VPMOVSXWDZ256rrk 2532331775U, // VPMOVSXWDZ256rrkz 1041256703U, // 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// VPMOVWBZmr 16352888U, // VPMOVWBZmrk 370165368U, // VPMOVWBZrr 49301112U, // VPMOVWBZrrk 2532329080U, // VPMOVWBZrrkz 437274462U, // VPMOVZXBDYrm 370165598U, // VPMOVZXBDYrr 403720030U, // VPMOVZXBDZ128rm 49301342U, // VPMOVZXBDZ128rmk 2532329310U, // VPMOVZXBDZ128rmkz 370165598U, // VPMOVZXBDZ128rr 49301342U, // VPMOVZXBDZ128rrk 2532329310U, // VPMOVZXBDZ128rrkz 437274462U, // VPMOVZXBDZ256rm 49301342U, // VPMOVZXBDZ256rmk 2532329310U, // VPMOVZXBDZ256rmkz 370165598U, // VPMOVZXBDZ256rr 49301342U, // VPMOVZXBDZ256rrk 2532329310U, // VPMOVZXBDZ256rrkz 336611166U, // VPMOVZXBDZrm 49301342U, // VPMOVZXBDZrmk 2532329310U, // VPMOVZXBDZrmkz 370165598U, // VPMOVZXBDZrr 49301342U, // VPMOVZXBDZrrk 2532329310U, // VPMOVZXBDZrrkz 403720030U, // VPMOVZXBDrm 370165598U, // VPMOVZXBDrr 403723789U, // VPMOVZXBQYrm 370169357U, // VPMOVZXBQYrr 504387085U, // VPMOVZXBQZ128rm 49305101U, // VPMOVZXBQZ128rmk 2532333069U, // VPMOVZXBQZ128rmkz 370169357U, // VPMOVZXBQZ128rr 49305101U, // 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// VPMULHUWZ256rm 49309288U, // VPMULHUWZ256rmk 2532337256U, // VPMULHUWZ256rmkz 2517657192U, // VPMULHUWZ256rr 49309288U, // VPMULHUWZ256rrk 2532337256U, // VPMULHUWZ256rrkz 2517657192U, // VPMULHUWZrm 49309288U, // VPMULHUWZrmk 2532337256U, // VPMULHUWZrmkz 2517657192U, // VPMULHUWZrr 49309288U, // VPMULHUWZrrk 2532337256U, // VPMULHUWZrrkz 2517657192U, // VPMULHUWrm 2517657192U, // VPMULHUWrr 2517656718U, // VPMULHWYrm 2517656718U, // VPMULHWYrr 2517656718U, // VPMULHWZ128rm 49308814U, // VPMULHWZ128rmk 2532336782U, // VPMULHWZ128rmkz 2517656718U, // VPMULHWZ128rr 49308814U, // VPMULHWZ128rrk 2532336782U, // VPMULHWZ128rrkz 2517656718U, // VPMULHWZ256rm 49308814U, // VPMULHWZ256rmk 2532336782U, // VPMULHWZ256rmkz 2517656718U, // VPMULHWZ256rr 49308814U, // VPMULHWZ256rrk 2532336782U, // VPMULHWZ256rrkz 2517656718U, // VPMULHWZrm 49308814U, // VPMULHWZrmk 2532336782U, // VPMULHWZrmkz 2517656718U, // VPMULHWZrr 49308814U, // VPMULHWZrrk 2532336782U, // VPMULHWZrrkz 2517656718U, // VPMULHWrm 2517656718U, // VPMULHWrr 2517649496U, // VPMULLDYrm 2517649496U, // VPMULLDYrr 2517649496U, // VPMULLDZ128rm 2517649496U, // VPMULLDZ128rmb 49301592U, // VPMULLDZ128rmbk 2532329560U, // VPMULLDZ128rmbkz 49301592U, // VPMULLDZ128rmk 2532329560U, // VPMULLDZ128rmkz 2517649496U, // VPMULLDZ128rr 49301592U, // VPMULLDZ128rrk 2532329560U, // VPMULLDZ128rrkz 2517649496U, // VPMULLDZ256rm 2517649496U, // VPMULLDZ256rmb 49301592U, // VPMULLDZ256rmbk 2532329560U, // VPMULLDZ256rmbkz 49301592U, // VPMULLDZ256rmk 2532329560U, // VPMULLDZ256rmkz 2517649496U, // VPMULLDZ256rr 49301592U, // VPMULLDZ256rrk 2532329560U, // VPMULLDZ256rrkz 2517649496U, // VPMULLDZrm 2517649496U, // VPMULLDZrmb 49301592U, // VPMULLDZrmbk 2532329560U, // VPMULLDZrmbkz 49301592U, // VPMULLDZrmk 2532329560U, // VPMULLDZrmkz 2517649496U, // VPMULLDZrr 49301592U, // VPMULLDZrrk 2532329560U, // VPMULLDZrrkz 2517649496U, // VPMULLDrm 2517649496U, // VPMULLDrr 2517653421U, // VPMULLQZ128rm 2517653421U, // VPMULLQZ128rmb 49305517U, // VPMULLQZ128rmbk 2532333485U, // VPMULLQZ128rmbkz 49305517U, // VPMULLQZ128rmk 2532333485U, // VPMULLQZ128rmkz 2517653421U, // VPMULLQZ128rr 49305517U, // VPMULLQZ128rrk 2532333485U, // VPMULLQZ128rrkz 2517653421U, // VPMULLQZ256rm 2517653421U, // VPMULLQZ256rmb 49305517U, // VPMULLQZ256rmbk 2532333485U, // VPMULLQZ256rmbkz 49305517U, // VPMULLQZ256rmk 2532333485U, // VPMULLQZ256rmkz 2517653421U, // VPMULLQZ256rr 49305517U, // VPMULLQZ256rrk 2532333485U, // VPMULLQZ256rrkz 2517653421U, // VPMULLQZrm 2517653421U, // VPMULLQZrmb 49305517U, // VPMULLQZrmbk 2532333485U, // VPMULLQZrmbkz 49305517U, // VPMULLQZrmk 2532333485U, // VPMULLQZrmkz 2517653421U, // VPMULLQZrr 49305517U, // VPMULLQZrrk 2532333485U, // VPMULLQZrrkz 2517656760U, // VPMULLWYrm 2517656760U, // VPMULLWYrr 2517656760U, // VPMULLWZ128rm 49308856U, // VPMULLWZ128rmk 2532336824U, // VPMULLWZ128rmkz 2517656760U, // VPMULLWZ128rr 49308856U, // VPMULLWZ128rrk 2532336824U, // VPMULLWZ128rrkz 2517656760U, // VPMULLWZ256rm 49308856U, // VPMULLWZ256rmk 2532336824U, // VPMULLWZ256rmkz 2517656760U, // VPMULLWZ256rr 49308856U, // VPMULLWZ256rrk 2532336824U, // VPMULLWZ256rrkz 2517656760U, // VPMULLWZrm 49308856U, // VPMULLWZrmk 2532336824U, // VPMULLWZrmkz 2517656760U, // VPMULLWZrr 49308856U, // VPMULLWZrrk 2532336824U, // VPMULLWZrrkz 2517656760U, // VPMULLWrm 2517656760U, // VPMULLWrr 2517648619U, // VPMULTISHIFTQBZ128rm 2517648619U, // VPMULTISHIFTQBZ128rmb 49300715U, // VPMULTISHIFTQBZ128rmbk 2532328683U, // VPMULTISHIFTQBZ128rmbkz 49300715U, // VPMULTISHIFTQBZ128rmk 2532328683U, // VPMULTISHIFTQBZ128rmkz 2517648619U, // VPMULTISHIFTQBZ128rr 49300715U, // VPMULTISHIFTQBZ128rrk 2532328683U, // VPMULTISHIFTQBZ128rrkz 2517648619U, // VPMULTISHIFTQBZ256rm 2517648619U, // VPMULTISHIFTQBZ256rmb 49300715U, // VPMULTISHIFTQBZ256rmbk 2532328683U, // VPMULTISHIFTQBZ256rmbkz 49300715U, // VPMULTISHIFTQBZ256rmk 2532328683U, // VPMULTISHIFTQBZ256rmkz 2517648619U, // VPMULTISHIFTQBZ256rr 49300715U, // VPMULTISHIFTQBZ256rrk 2532328683U, // VPMULTISHIFTQBZ256rrkz 2517648619U, // VPMULTISHIFTQBZrm 2517648619U, // VPMULTISHIFTQBZrmb 49300715U, // VPMULTISHIFTQBZrmbk 2532328683U, // VPMULTISHIFTQBZrmbkz 49300715U, // VPMULTISHIFTQBZrmk 2532328683U, // VPMULTISHIFTQBZrmkz 2517648619U, // VPMULTISHIFTQBZrr 49300715U, // VPMULTISHIFTQBZrrk 2532328683U, // VPMULTISHIFTQBZrrkz 2517653345U, // VPMULUDQYrm 2517653345U, // VPMULUDQYrr 2517653345U, // VPMULUDQZ128rm 2517653345U, // VPMULUDQZ128rmb 49305441U, // VPMULUDQZ128rmbk 2532333409U, // VPMULUDQZ128rmbkz 49305441U, // VPMULUDQZ128rmk 2532333409U, // VPMULUDQZ128rmkz 2517653345U, // VPMULUDQZ128rr 49305441U, // VPMULUDQZ128rrk 2532333409U, // VPMULUDQZ128rrkz 2517653345U, // VPMULUDQZ256rm 2517653345U, // VPMULUDQZ256rmb 49305441U, // VPMULUDQZ256rmbk 2532333409U, // VPMULUDQZ256rmbkz 49305441U, // VPMULUDQZ256rmk 2532333409U, // VPMULUDQZ256rmkz 2517653345U, // VPMULUDQZ256rr 49305441U, // VPMULUDQZ256rrk 2532333409U, // VPMULUDQZ256rrkz 2517653345U, // VPMULUDQZrm 2517653345U, // VPMULUDQZrmb 49305441U, // VPMULUDQZrmbk 2532333409U, // VPMULUDQZrmbkz 49305441U, // VPMULUDQZrmk 2532333409U, // VPMULUDQZrmkz 2517653345U, // VPMULUDQZrr 49305441U, // VPMULUDQZrrk 2532333409U, // VPMULUDQZrrkz 2517653345U, // VPMULUDQrm 2517653345U, // VPMULUDQrr 336610755U, // VPOPCNTBZ128rm 49300931U, // VPOPCNTBZ128rmk 2532328899U, // VPOPCNTBZ128rmkz 370165187U, // VPOPCNTBZ128rr 49300931U, // VPOPCNTBZ128rrk 2532328899U, // VPOPCNTBZ128rrkz 1041253827U, // VPOPCNTBZ256rm 49300931U, // VPOPCNTBZ256rmk 2532328899U, // VPOPCNTBZ256rmkz 370165187U, // VPOPCNTBZ256rr 49300931U, // VPOPCNTBZ256rrk 2532328899U, // VPOPCNTBZ256rrkz 806372803U, // VPOPCNTBZrm 49300931U, // VPOPCNTBZrmk 2532328899U, // VPOPCNTBZrmkz 370165187U, // VPOPCNTBZrr 49300931U, // VPOPCNTBZrrk 2532328899U, // VPOPCNTBZrrkz 336613325U, // VPOPCNTDZ128rm 2551205837U, // VPOPCNTDZ128rmb 49303501U, // VPOPCNTDZ128rmbk 2532331469U, // VPOPCNTDZ128rmbkz 49303501U, // VPOPCNTDZ128rmk 2532331469U, // VPOPCNTDZ128rmkz 370167757U, // VPOPCNTDZ128rr 49303501U, // VPOPCNTDZ128rrk 2532331469U, // VPOPCNTDZ128rrkz 1041256397U, // VPOPCNTDZ256rm 403722189U, // VPOPCNTDZ256rmb 49303501U, // VPOPCNTDZ256rmbk 2532331469U, // VPOPCNTDZ256rmbkz 49303501U, // VPOPCNTDZ256rmk 2532331469U, // VPOPCNTDZ256rmkz 370167757U, // VPOPCNTDZ256rr 49303501U, // VPOPCNTDZ256rrk 2532331469U, // VPOPCNTDZ256rrkz 806375373U, // VPOPCNTDZrm 2551205837U, // VPOPCNTDZrmb 49303501U, // VPOPCNTDZrmbk 2532331469U, // VPOPCNTDZrmbkz 49303501U, // VPOPCNTDZrmk 2532331469U, // VPOPCNTDZrmkz 370167757U, // VPOPCNTDZrr 49303501U, // VPOPCNTDZrrk 2532331469U, // VPOPCNTDZrrkz 336615776U, // VPOPCNTQZ128rm 437279072U, // VPOPCNTQZ128rmb 49305952U, // VPOPCNTQZ128rmbk 2532333920U, // VPOPCNTQZ128rmbkz 49305952U, // VPOPCNTQZ128rmk 2532333920U, // VPOPCNTQZ128rmkz 370170208U, // VPOPCNTQZ128rr 49305952U, // VPOPCNTQZ128rrk 2532333920U, // VPOPCNTQZ128rrkz 1041258848U, // VPOPCNTQZ256rm 2584762720U, // VPOPCNTQZ256rmb 49305952U, // VPOPCNTQZ256rmbk 2532333920U, // VPOPCNTQZ256rmbkz 49305952U, // VPOPCNTQZ256rmk 2532333920U, // VPOPCNTQZ256rmkz 370170208U, // VPOPCNTQZ256rr 49305952U, // VPOPCNTQZ256rrk 2532333920U, // VPOPCNTQZ256rrkz 806377824U, // VPOPCNTQZrm 437279072U, // VPOPCNTQZrmb 49305952U, // VPOPCNTQZrmbk 2532333920U, // VPOPCNTQZrmbkz 49305952U, // VPOPCNTQZrmk 2532333920U, // VPOPCNTQZrmkz 370170208U, // VPOPCNTQZrr 49305952U, // VPOPCNTQZrrk 2532333920U, // VPOPCNTQZrrkz 336619055U, // VPOPCNTWZ128rm 49309231U, // VPOPCNTWZ128rmk 2532337199U, // VPOPCNTWZ128rmkz 370173487U, // VPOPCNTWZ128rr 49309231U, // VPOPCNTWZ128rrk 2532337199U, // VPOPCNTWZ128rrkz 1041262127U, // VPOPCNTWZ256rm 49309231U, // VPOPCNTWZ256rmk 2532337199U, // VPOPCNTWZ256rmkz 370173487U, // VPOPCNTWZ256rr 49309231U, // VPOPCNTWZ256rrk 2532337199U, // VPOPCNTWZ256rrkz 806381103U, // VPOPCNTWZrm 49309231U, // VPOPCNTWZrmk 2532337199U, // VPOPCNTWZrmkz 370173487U, // VPOPCNTWZrr 49309231U, // VPOPCNTWZrrk 2532337199U, // VPOPCNTWZrrkz 2517650723U, // VPORDZ128rm 2517650723U, // VPORDZ128rmb 49302819U, // VPORDZ128rmbk 2532330787U, // VPORDZ128rmbkz 49302819U, // VPORDZ128rmk 2532330787U, // VPORDZ128rmkz 2517650723U, // VPORDZ128rr 49302819U, // VPORDZ128rrk 2532330787U, // VPORDZ128rrkz 2517650723U, // VPORDZ256rm 2517650723U, // VPORDZ256rmb 49302819U, // VPORDZ256rmbk 2532330787U, // VPORDZ256rmbkz 49302819U, // VPORDZ256rmk 2532330787U, // VPORDZ256rmkz 2517650723U, // VPORDZ256rr 49302819U, // VPORDZ256rrk 2532330787U, // VPORDZ256rrkz 2517650723U, // VPORDZrm 2517650723U, // VPORDZrmb 49302819U, // VPORDZrmbk 2532330787U, // VPORDZrmbkz 49302819U, // VPORDZrmk 2532330787U, // VPORDZrmkz 2517650723U, // VPORDZrr 49302819U, // VPORDZrrk 2532330787U, // VPORDZrrkz 2517653700U, // VPORQZ128rm 2517653700U, // VPORQZ128rmb 49305796U, // VPORQZ128rmbk 2532333764U, // VPORQZ128rmbkz 49305796U, // VPORQZ128rmk 2532333764U, // VPORQZ128rmkz 2517653700U, // VPORQZ128rr 49305796U, // VPORQZ128rrk 2532333764U, // VPORQZ128rrkz 2517653700U, // VPORQZ256rm 2517653700U, // VPORQZ256rmb 49305796U, // VPORQZ256rmbk 2532333764U, // VPORQZ256rmbkz 49305796U, // VPORQZ256rmk 2532333764U, // VPORQZ256rmkz 2517653700U, // VPORQZ256rr 49305796U, // VPORQZ256rrk 2532333764U, // VPORQZ256rrkz 2517653700U, // VPORQZrm 2517653700U, // VPORQZrmb 49305796U, // VPORQZrmbk 2532333764U, // VPORQZrmbkz 49305796U, // VPORQZrmk 2532333764U, // VPORQZrmkz 2517653700U, // VPORQZrr 49305796U, // VPORQZrrk 2532333764U, // VPORQZrrkz 2517654191U, // VPORYrm 2517654191U, // VPORYrr 2517654191U, // VPORrm 2517654191U, // VPORrr 2517652565U, // VPPERMrmr 2517652565U, // VPPERMrrm 2517652565U, // VPPERMrrr 2517652565U, // VPPERMrrr_REV 403720289U, // VPROLDZ128mbi 49301601U, // VPROLDZ128mbik 2532329569U, // VPROLDZ128mbikz 2484095073U, // VPROLDZ128mi 49301601U, // VPROLDZ128mik 2532329569U, // VPROLDZ128mikz 2517649505U, // VPROLDZ128ri 49301601U, // VPROLDZ128rik 2532329569U, // VPROLDZ128rikz 2551203937U, // VPROLDZ256mbi 49301601U, // VPROLDZ256mbik 2532329569U, // VPROLDZ256mbikz 3188738145U, // VPROLDZ256mi 49301601U, // VPROLDZ256mik 2532329569U, // VPROLDZ256mikz 2517649505U, // VPROLDZ256ri 49301601U, // VPROLDZ256rik 2532329569U, // VPROLDZ256rikz 403720289U, // VPROLDZmbi 49301601U, // VPROLDZmbik 2532329569U, // VPROLDZmbikz 2953857121U, // VPROLDZmi 49301601U, // VPROLDZmik 2532329569U, // VPROLDZmikz 2517649505U, // VPROLDZri 49301601U, // VPROLDZrik 2532329569U, // VPROLDZrikz 2584762294U, // VPROLQZ128mbi 49305526U, // VPROLQZ128mbik 2532333494U, // VPROLQZ128mbikz 2484098998U, // VPROLQZ128mi 49305526U, // VPROLQZ128mik 2532333494U, // VPROLQZ128mikz 2517653430U, // VPROLQZ128ri 49305526U, // VPROLQZ128rik 2532333494U, // VPROLQZ128rikz 437278646U, // VPROLQZ256mbi 49305526U, // VPROLQZ256mbik 2532333494U, // VPROLQZ256mbikz 3188742070U, // VPROLQZ256mi 49305526U, // VPROLQZ256mik 2532333494U, // VPROLQZ256mikz 2517653430U, // VPROLQZ256ri 49305526U, // VPROLQZ256rik 2532333494U, // VPROLQZ256rikz 2584762294U, // VPROLQZmbi 49305526U, // VPROLQZmbik 2532333494U, // VPROLQZmbikz 2953861046U, // VPROLQZmi 49305526U, // VPROLQZmik 2532333494U, // VPROLQZmikz 2517653430U, // VPROLQZri 49305526U, // VPROLQZrik 2532333494U, // VPROLQZrikz 2517651546U, // VPROLVDZ128rm 2517651546U, // VPROLVDZ128rmb 49303642U, // VPROLVDZ128rmbk 2532331610U, // VPROLVDZ128rmbkz 49303642U, // VPROLVDZ128rmk 2532331610U, // VPROLVDZ128rmkz 2517651546U, // VPROLVDZ128rr 49303642U, // VPROLVDZ128rrk 2532331610U, // VPROLVDZ128rrkz 2517651546U, // VPROLVDZ256rm 2517651546U, // VPROLVDZ256rmb 49303642U, // VPROLVDZ256rmbk 2532331610U, // VPROLVDZ256rmbkz 49303642U, // VPROLVDZ256rmk 2532331610U, // VPROLVDZ256rmkz 2517651546U, // VPROLVDZ256rr 49303642U, // VPROLVDZ256rrk 2532331610U, // VPROLVDZ256rrkz 2517651546U, // VPROLVDZrm 2517651546U, // VPROLVDZrmb 49303642U, // VPROLVDZrmbk 2532331610U, // VPROLVDZrmbkz 49303642U, // VPROLVDZrmk 2532331610U, // VPROLVDZrmkz 2517651546U, // VPROLVDZrr 49303642U, // VPROLVDZrrk 2532331610U, // VPROLVDZrrkz 2517654040U, // VPROLVQZ128rm 2517654040U, // VPROLVQZ128rmb 49306136U, // VPROLVQZ128rmbk 2532334104U, // VPROLVQZ128rmbkz 49306136U, // VPROLVQZ128rmk 2532334104U, // VPROLVQZ128rmkz 2517654040U, // VPROLVQZ128rr 49306136U, // VPROLVQZ128rrk 2532334104U, // VPROLVQZ128rrkz 2517654040U, // VPROLVQZ256rm 2517654040U, // VPROLVQZ256rmb 49306136U, // VPROLVQZ256rmbk 2532334104U, // VPROLVQZ256rmbkz 49306136U, // VPROLVQZ256rmk 2532334104U, // VPROLVQZ256rmkz 2517654040U, // VPROLVQZ256rr 49306136U, // VPROLVQZ256rrk 2532334104U, // VPROLVQZ256rrkz 2517654040U, // VPROLVQZrm 2517654040U, // VPROLVQZrmb 49306136U, // VPROLVQZrmbk 2532334104U, // VPROLVQZrmbkz 49306136U, // VPROLVQZrmk 2532334104U, // VPROLVQZrmkz 2517654040U, // VPROLVQZrr 49306136U, // VPROLVQZrrk 2532334104U, // VPROLVQZrrkz 403721514U, // VPRORDZ128mbi 49302826U, // VPRORDZ128mbik 2532330794U, // VPRORDZ128mbikz 2484096298U, // VPRORDZ128mi 49302826U, // VPRORDZ128mik 2532330794U, // VPRORDZ128mikz 2517650730U, // VPRORDZ128ri 49302826U, // VPRORDZ128rik 2532330794U, // VPRORDZ128rikz 2551205162U, // VPRORDZ256mbi 49302826U, // VPRORDZ256mbik 2532330794U, // VPRORDZ256mbikz 3188739370U, // VPRORDZ256mi 49302826U, // VPRORDZ256mik 2532330794U, // VPRORDZ256mikz 2517650730U, // VPRORDZ256ri 49302826U, // VPRORDZ256rik 2532330794U, // VPRORDZ256rikz 403721514U, // VPRORDZmbi 49302826U, // VPRORDZmbik 2532330794U, // VPRORDZmbikz 2953858346U, // VPRORDZmi 49302826U, // VPRORDZmik 2532330794U, // VPRORDZmikz 2517650730U, // VPRORDZri 49302826U, // VPRORDZrik 2532330794U, // VPRORDZrikz 2584762571U, // VPRORQZ128mbi 49305803U, // VPRORQZ128mbik 2532333771U, // VPRORQZ128mbikz 2484099275U, // VPRORQZ128mi 49305803U, // VPRORQZ128mik 2532333771U, // VPRORQZ128mikz 2517653707U, // VPRORQZ128ri 49305803U, // VPRORQZ128rik 2532333771U, // VPRORQZ128rikz 437278923U, // VPRORQZ256mbi 49305803U, // VPRORQZ256mbik 2532333771U, // VPRORQZ256mbikz 3188742347U, // VPRORQZ256mi 49305803U, // VPRORQZ256mik 2532333771U, // VPRORQZ256mikz 2517653707U, // VPRORQZ256ri 49305803U, // VPRORQZ256rik 2532333771U, // VPRORQZ256rikz 2584762571U, // VPRORQZmbi 49305803U, // VPRORQZmbik 2532333771U, // VPRORQZmbikz 2953861323U, // VPRORQZmi 49305803U, // VPRORQZmik 2532333771U, // VPRORQZmikz 2517653707U, // VPRORQZri 49305803U, // VPRORQZrik 2532333771U, // VPRORQZrikz 2517651583U, // VPRORVDZ128rm 2517651583U, // VPRORVDZ128rmb 49303679U, // VPRORVDZ128rmbk 2532331647U, // VPRORVDZ128rmbkz 49303679U, // VPRORVDZ128rmk 2532331647U, // VPRORVDZ128rmkz 2517651583U, // VPRORVDZ128rr 49303679U, // VPRORVDZ128rrk 2532331647U, // VPRORVDZ128rrkz 2517651583U, // VPRORVDZ256rm 2517651583U, // VPRORVDZ256rmb 49303679U, // VPRORVDZ256rmbk 2532331647U, // VPRORVDZ256rmbkz 49303679U, // VPRORVDZ256rmk 2532331647U, // VPRORVDZ256rmkz 2517651583U, // VPRORVDZ256rr 49303679U, // VPRORVDZ256rrk 2532331647U, // VPRORVDZ256rrkz 2517651583U, // VPRORVDZrm 2517651583U, // VPRORVDZrmb 49303679U, // VPRORVDZrmbk 2532331647U, // VPRORVDZrmbkz 49303679U, // VPRORVDZrmk 2532331647U, // VPRORVDZrmkz 2517651583U, // VPRORVDZrr 49303679U, // VPRORVDZrrk 2532331647U, // VPRORVDZrrkz 2517654077U, // VPRORVQZ128rm 2517654077U, // VPRORVQZ128rmb 49306173U, // VPRORVQZ128rmbk 2532334141U, // VPRORVQZ128rmbkz 49306173U, // VPRORVQZ128rmk 2532334141U, // VPRORVQZ128rmkz 2517654077U, // VPRORVQZ128rr 49306173U, // VPRORVQZ128rrk 2532334141U, // VPRORVQZ128rrkz 2517654077U, // VPRORVQZ256rm 2517654077U, // VPRORVQZ256rmb 49306173U, // VPRORVQZ256rmbk 2532334141U, // VPRORVQZ256rmbkz 49306173U, // VPRORVQZ256rmk 2532334141U, // VPRORVQZ256rmkz 2517654077U, // VPRORVQZ256rr 49306173U, // VPRORVQZ256rrk 2532334141U, // VPRORVQZ256rrkz 2517654077U, // VPRORVQZrm 2517654077U, // VPRORVQZrmb 49306173U, // VPRORVQZrmbk 2532334141U, // VPRORVQZrmbkz 49306173U, // VPRORVQZrmk 2532334141U, // VPRORVQZrmkz 2517654077U, // VPRORVQZrr 49306173U, // VPRORVQZrrk 2532334141U, // VPRORVQZrrkz 2484094420U, // VPROTBmi 2484094420U, // VPROTBmr 2517648852U, // VPROTBri 2517648852U, // VPROTBrm 2517648852U, // VPROTBrr 2517648852U, // VPROTBrr_REV 2484097000U, // VPROTDmi 2484097000U, // VPROTDmr 2517651432U, // VPROTDri 2517651432U, // VPROTDrm 2517651432U, // VPROTDrr 2517651432U, // VPROTDrr_REV 2484099459U, // VPROTQmi 2484099459U, // VPROTQmr 2517653891U, // VPROTQri 2517653891U, // VPROTQrm 2517653891U, // VPROTQrr 2517653891U, // VPROTQrr_REV 2484102720U, // VPROTWmi 2484102720U, // VPROTWmr 2517657152U, // VPROTWri 2517657152U, // VPROTWrm 2517657152U, // VPROTWrr 2517657152U, // VPROTWrr_REV 2517656434U, // VPSADBWYrm 2517656434U, // VPSADBWYrr 2517656434U, // VPSADBWZ128rm 2517656434U, // VPSADBWZ128rr 2517656434U, // VPSADBWZ256rm 2517656434U, // VPSADBWZ256rr 2517656434U, // VPSADBWZrm 2517656434U, // VPSADBWZrr 2517656434U, // VPSADBWrm 2517656434U, // VPSADBWrr 690126U, // VPSCATTERDDZ128mr 706510U, // VPSCATTERDDZ256mr 722894U, // VPSCATTERDDZmr 694020U, // VPSCATTERDQZ128mr 710404U, // VPSCATTERDQZ256mr 726788U, // VPSCATTERDQZmr 740580U, // VPSCATTERQDZ128mr 691428U, // VPSCATTERQDZ256mr 707812U, // VPSCATTERQDZmr 694391U, // VPSCATTERQQZ128mr 710775U, // VPSCATTERQQZ256mr 727159U, // VPSCATTERQQZmr 2484093891U, // VPSHABmr 2517648323U, // VPSHABrm 2517648323U, // VPSHABrr 2517648323U, // VPSHABrr_REV 2484094749U, // VPSHADmr 2517649181U, // VPSHADrm 2517649181U, // VPSHADrr 2517649181U, // VPSHADrr_REV 2484098517U, // VPSHAQmr 2517652949U, // VPSHAQrm 2517652949U, // VPSHAQrr 2517652949U, // VPSHAQrr_REV 2484101955U, // VPSHAWmr 2517656387U, // VPSHAWrm 2517656387U, // VPSHAWrr 2517656387U, // VPSHAWrr_REV 2484094023U, // VPSHLBmr 2517648455U, // VPSHLBrm 2517648455U, // VPSHLBrr 2517648455U, // VPSHLBrr_REV 2517649301U, // VPSHLDDZ128rmbi 49301397U, // VPSHLDDZ128rmbik 2532329365U, // VPSHLDDZ128rmbikz 2517649301U, // VPSHLDDZ128rmi 49301397U, // VPSHLDDZ128rmik 2532329365U, // VPSHLDDZ128rmikz 2517649301U, // VPSHLDDZ128rri 49301397U, // VPSHLDDZ128rrik 2532329365U, // VPSHLDDZ128rrikz 2517649301U, // VPSHLDDZ256rmbi 49301397U, // VPSHLDDZ256rmbik 2532329365U, // VPSHLDDZ256rmbikz 2517649301U, // VPSHLDDZ256rmi 49301397U, // VPSHLDDZ256rmik 2532329365U, // VPSHLDDZ256rmikz 2517649301U, // VPSHLDDZ256rri 49301397U, // VPSHLDDZ256rrik 2532329365U, // VPSHLDDZ256rrikz 2517649301U, // VPSHLDDZrmbi 49301397U, // VPSHLDDZrmbik 2532329365U, // VPSHLDDZrmbikz 2517649301U, // VPSHLDDZrmi 49301397U, // VPSHLDDZrmik 2532329365U, // VPSHLDDZrmikz 2517649301U, // VPSHLDDZrri 49301397U, // VPSHLDDZrrik 2532329365U, // VPSHLDDZrrikz 2517653128U, // VPSHLDQZ128rmbi 49305224U, // VPSHLDQZ128rmbik 2532333192U, // VPSHLDQZ128rmbikz 2517653128U, // VPSHLDQZ128rmi 49305224U, // VPSHLDQZ128rmik 2532333192U, // VPSHLDQZ128rmikz 2517653128U, // VPSHLDQZ128rri 49305224U, // VPSHLDQZ128rrik 2532333192U, // VPSHLDQZ128rrikz 2517653128U, // VPSHLDQZ256rmbi 49305224U, // VPSHLDQZ256rmbik 2532333192U, // VPSHLDQZ256rmbikz 2517653128U, // VPSHLDQZ256rmi 49305224U, // VPSHLDQZ256rmik 2532333192U, // VPSHLDQZ256rmikz 2517653128U, // VPSHLDQZ256rri 49305224U, // VPSHLDQZ256rrik 2532333192U, // VPSHLDQZ256rrikz 2517653128U, // VPSHLDQZrmbi 49305224U, // VPSHLDQZrmbik 2532333192U, // VPSHLDQZrmbikz 2517653128U, // VPSHLDQZrmi 49305224U, // VPSHLDQZrmik 2532333192U, // VPSHLDQZrmikz 2517653128U, // VPSHLDQZrri 49305224U, // VPSHLDQZrrik 2532333192U, // VPSHLDQZrrikz 2182107197U, // VPSHLDVDZ128m 2182107197U, // VPSHLDVDZ128mb 49303613U, // VPSHLDVDZ128mbk 2196787261U, // VPSHLDVDZ128mbkz 49303613U, // VPSHLDVDZ128mk 2196787261U, // VPSHLDVDZ128mkz 2182107197U, // VPSHLDVDZ128r 49303613U, // VPSHLDVDZ128rk 2196787261U, // VPSHLDVDZ128rkz 2182107197U, // VPSHLDVDZ256m 2182107197U, // VPSHLDVDZ256mb 49303613U, // VPSHLDVDZ256mbk 2196787261U, // VPSHLDVDZ256mbkz 49303613U, // VPSHLDVDZ256mk 2196787261U, // VPSHLDVDZ256mkz 2182107197U, // VPSHLDVDZ256r 49303613U, // VPSHLDVDZ256rk 2196787261U, // VPSHLDVDZ256rkz 2182107197U, // VPSHLDVDZm 2182107197U, // VPSHLDVDZmb 49303613U, // VPSHLDVDZmbk 2196787261U, // VPSHLDVDZmbkz 49303613U, // VPSHLDVDZmk 2196787261U, // VPSHLDVDZmkz 2182107197U, // VPSHLDVDZr 49303613U, // VPSHLDVDZrk 2196787261U, // VPSHLDVDZrkz 2182109691U, // VPSHLDVQZ128m 2182109691U, // VPSHLDVQZ128mb 49306107U, // VPSHLDVQZ128mbk 2196789755U, // VPSHLDVQZ128mbkz 49306107U, // VPSHLDVQZ128mk 2196789755U, // VPSHLDVQZ128mkz 2182109691U, // VPSHLDVQZ128r 49306107U, // VPSHLDVQZ128rk 2196789755U, // VPSHLDVQZ128rkz 2182109691U, // VPSHLDVQZ256m 2182109691U, // VPSHLDVQZ256mb 49306107U, // VPSHLDVQZ256mbk 2196789755U, // VPSHLDVQZ256mbkz 49306107U, // VPSHLDVQZ256mk 2196789755U, // VPSHLDVQZ256mkz 2182109691U, // VPSHLDVQZ256r 49306107U, // VPSHLDVQZ256rk 2196789755U, // VPSHLDVQZ256rkz 2182109691U, // VPSHLDVQZm 2182109691U, // VPSHLDVQZmb 49306107U, // VPSHLDVQZmbk 2196789755U, // VPSHLDVQZmbkz 49306107U, // VPSHLDVQZmk 2196789755U, // VPSHLDVQZmkz 2182109691U, // VPSHLDVQZr 49306107U, // VPSHLDVQZrk 2196789755U, // VPSHLDVQZrkz 2182112940U, // VPSHLDVWZ128m 49309356U, // VPSHLDVWZ128mk 2196793004U, // VPSHLDVWZ128mkz 2182112940U, // VPSHLDVWZ128r 49309356U, // VPSHLDVWZ128rk 2196793004U, // VPSHLDVWZ128rkz 2182112940U, // VPSHLDVWZ256m 49309356U, // VPSHLDVWZ256mk 2196793004U, // VPSHLDVWZ256mkz 2182112940U, // VPSHLDVWZ256r 49309356U, // VPSHLDVWZ256rk 2196793004U, // VPSHLDVWZ256rkz 2182112940U, // VPSHLDVWZm 49309356U, // VPSHLDVWZmk 2196793004U, // VPSHLDVWZmkz 2182112940U, // VPSHLDVWZr 49309356U, // VPSHLDVWZrk 2196793004U, // VPSHLDVWZrkz 2517656576U, // VPSHLDWZ128rmi 49308672U, // VPSHLDWZ128rmik 2532336640U, // VPSHLDWZ128rmikz 2517656576U, // VPSHLDWZ128rri 49308672U, // VPSHLDWZ128rrik 2532336640U, // VPSHLDWZ128rrikz 2517656576U, // VPSHLDWZ256rmi 49308672U, // VPSHLDWZ256rmik 2532336640U, // VPSHLDWZ256rmikz 2517656576U, // VPSHLDWZ256rri 49308672U, // VPSHLDWZ256rrik 2532336640U, // VPSHLDWZ256rrikz 2517656576U, // VPSHLDWZrmi 49308672U, // VPSHLDWZrmik 2532336640U, // VPSHLDWZrmikz 2517656576U, // VPSHLDWZrri 49308672U, // VPSHLDWZrrik 2532336640U, // VPSHLDWZrrikz 2484095042U, // VPSHLDmr 2517649474U, // VPSHLDrm 2517649474U, // VPSHLDrr 2517649474U, // VPSHLDrr_REV 2484098973U, // VPSHLQmr 2517653405U, // VPSHLQrm 2517653405U, // VPSHLQrr 2517653405U, // VPSHLQrr_REV 2484102312U, // VPSHLWmr 2517656744U, // VPSHLWrm 2517656744U, // VPSHLWrr 2517656744U, // VPSHLWrr_REV 2517649371U, // VPSHRDDZ128rmbi 49301467U, // VPSHRDDZ128rmbik 2532329435U, // VPSHRDDZ128rmbikz 2517649371U, // VPSHRDDZ128rmi 49301467U, // VPSHRDDZ128rmik 2532329435U, // VPSHRDDZ128rmikz 2517649371U, // VPSHRDDZ128rri 49301467U, // VPSHRDDZ128rrik 2532329435U, // VPSHRDDZ128rrikz 2517649371U, // VPSHRDDZ256rmbi 49301467U, // VPSHRDDZ256rmbik 2532329435U, // VPSHRDDZ256rmbikz 2517649371U, // VPSHRDDZ256rmi 49301467U, // VPSHRDDZ256rmik 2532329435U, // VPSHRDDZ256rmikz 2517649371U, // VPSHRDDZ256rri 49301467U, // VPSHRDDZ256rrik 2532329435U, // VPSHRDDZ256rrikz 2517649371U, // VPSHRDDZrmbi 49301467U, // VPSHRDDZrmbik 2532329435U, // VPSHRDDZrmbikz 2517649371U, // VPSHRDDZrmi 49301467U, // VPSHRDDZrmik 2532329435U, // VPSHRDDZrmikz 2517649371U, // VPSHRDDZrri 49301467U, // VPSHRDDZrrik 2532329435U, // VPSHRDDZrrikz 2517653265U, // VPSHRDQZ128rmbi 49305361U, // VPSHRDQZ128rmbik 2532333329U, // VPSHRDQZ128rmbikz 2517653265U, // VPSHRDQZ128rmi 49305361U, // VPSHRDQZ128rmik 2532333329U, // VPSHRDQZ128rmikz 2517653265U, // VPSHRDQZ128rri 49305361U, // VPSHRDQZ128rrik 2532333329U, // VPSHRDQZ128rrikz 2517653265U, // VPSHRDQZ256rmbi 49305361U, // VPSHRDQZ256rmbik 2532333329U, // VPSHRDQZ256rmbikz 2517653265U, // VPSHRDQZ256rmi 49305361U, // VPSHRDQZ256rmik 2532333329U, // VPSHRDQZ256rmikz 2517653265U, // VPSHRDQZ256rri 49305361U, // VPSHRDQZ256rrik 2532333329U, // VPSHRDQZ256rrikz 2517653265U, // VPSHRDQZrmbi 49305361U, // VPSHRDQZrmbik 2532333329U, // VPSHRDQZrmbikz 2517653265U, // VPSHRDQZrmi 49305361U, // VPSHRDQZrmik 2532333329U, // VPSHRDQZrmikz 2517653265U, // VPSHRDQZrri 49305361U, // VPSHRDQZrrik 2532333329U, // VPSHRDQZrrikz 2182107207U, // VPSHRDVDZ128m 2182107207U, // VPSHRDVDZ128mb 49303623U, // VPSHRDVDZ128mbk 2196787271U, // VPSHRDVDZ128mbkz 49303623U, // VPSHRDVDZ128mk 2196787271U, // VPSHRDVDZ128mkz 2182107207U, // VPSHRDVDZ128r 49303623U, // VPSHRDVDZ128rk 2196787271U, // VPSHRDVDZ128rkz 2182107207U, // VPSHRDVDZ256m 2182107207U, // VPSHRDVDZ256mb 49303623U, // VPSHRDVDZ256mbk 2196787271U, // VPSHRDVDZ256mbkz 49303623U, // VPSHRDVDZ256mk 2196787271U, // VPSHRDVDZ256mkz 2182107207U, // VPSHRDVDZ256r 49303623U, // VPSHRDVDZ256rk 2196787271U, // VPSHRDVDZ256rkz 2182107207U, // VPSHRDVDZm 2182107207U, // VPSHRDVDZmb 49303623U, // VPSHRDVDZmbk 2196787271U, // VPSHRDVDZmbkz 49303623U, // VPSHRDVDZmk 2196787271U, // VPSHRDVDZmkz 2182107207U, // VPSHRDVDZr 49303623U, // VPSHRDVDZrk 2196787271U, // VPSHRDVDZrkz 2182109701U, // VPSHRDVQZ128m 2182109701U, // VPSHRDVQZ128mb 49306117U, // VPSHRDVQZ128mbk 2196789765U, // VPSHRDVQZ128mbkz 49306117U, // VPSHRDVQZ128mk 2196789765U, // VPSHRDVQZ128mkz 2182109701U, // VPSHRDVQZ128r 49306117U, // VPSHRDVQZ128rk 2196789765U, // VPSHRDVQZ128rkz 2182109701U, // VPSHRDVQZ256m 2182109701U, // VPSHRDVQZ256mb 49306117U, // VPSHRDVQZ256mbk 2196789765U, // VPSHRDVQZ256mbkz 49306117U, // VPSHRDVQZ256mk 2196789765U, // VPSHRDVQZ256mkz 2182109701U, // VPSHRDVQZ256r 49306117U, // VPSHRDVQZ256rk 2196789765U, // VPSHRDVQZ256rkz 2182109701U, // VPSHRDVQZm 2182109701U, // VPSHRDVQZmb 49306117U, // VPSHRDVQZmbk 2196789765U, // VPSHRDVQZmbkz 49306117U, // VPSHRDVQZmk 2196789765U, // VPSHRDVQZmkz 2182109701U, // VPSHRDVQZr 49306117U, // VPSHRDVQZrk 2196789765U, // VPSHRDVQZrkz 2182112950U, // VPSHRDVWZ128m 49309366U, // VPSHRDVWZ128mk 2196793014U, // VPSHRDVWZ128mkz 2182112950U, // VPSHRDVWZ128r 49309366U, // VPSHRDVWZ128rk 2196793014U, // VPSHRDVWZ128rkz 2182112950U, // VPSHRDVWZ256m 49309366U, // VPSHRDVWZ256mk 2196793014U, // VPSHRDVWZ256mkz 2182112950U, // VPSHRDVWZ256r 49309366U, // VPSHRDVWZ256rk 2196793014U, // VPSHRDVWZ256rkz 2182112950U, // VPSHRDVWZm 49309366U, // VPSHRDVWZmk 2196793014U, // VPSHRDVWZmkz 2182112950U, // VPSHRDVWZr 49309366U, // VPSHRDVWZrk 2196793014U, // VPSHRDVWZrkz 2517656613U, // VPSHRDWZ128rmi 49308709U, // VPSHRDWZ128rmik 2532336677U, // VPSHRDWZ128rmikz 2517656613U, // VPSHRDWZ128rri 49308709U, // VPSHRDWZ128rrik 2532336677U, // VPSHRDWZ128rrikz 2517656613U, // VPSHRDWZ256rmi 49308709U, // VPSHRDWZ256rmik 2532336677U, // VPSHRDWZ256rmikz 2517656613U, // VPSHRDWZ256rri 49308709U, // VPSHRDWZ256rrik 2532336677U, // VPSHRDWZ256rrikz 2517656613U, // VPSHRDWZrmi 49308709U, // VPSHRDWZrmik 2532336677U, // VPSHRDWZrmikz 2517656613U, // VPSHRDWZrri 49308709U, // VPSHRDWZrrik 2532336677U, // VPSHRDWZrrikz 2517648515U, // VPSHUFBITQMBZ128rm 384844931U, // VPSHUFBITQMBZ128rmk 2517648515U, // VPSHUFBITQMBZ128rr 384844931U, // VPSHUFBITQMBZ128rrk 2517648515U, // VPSHUFBITQMBZ256rm 384844931U, // VPSHUFBITQMBZ256rmk 2517648515U, // VPSHUFBITQMBZ256rr 384844931U, // VPSHUFBITQMBZ256rrk 2517648515U, // VPSHUFBITQMBZrm 384844931U, // VPSHUFBITQMBZrmk 2517648515U, // VPSHUFBITQMBZrr 384844931U, // VPSHUFBITQMBZrrk 2517648423U, // VPSHUFBYrm 2517648423U, // VPSHUFBYrr 2517648423U, // VPSHUFBZ128rm 49300519U, // VPSHUFBZ128rmk 2532328487U, // VPSHUFBZ128rmkz 2517648423U, // VPSHUFBZ128rr 49300519U, // VPSHUFBZ128rrk 2532328487U, // VPSHUFBZ128rrkz 2517648423U, // VPSHUFBZ256rm 49300519U, // VPSHUFBZ256rmk 2532328487U, // VPSHUFBZ256rmkz 2517648423U, // VPSHUFBZ256rr 49300519U, // VPSHUFBZ256rrk 2532328487U, // VPSHUFBZ256rrkz 2517648423U, // VPSHUFBZrm 49300519U, // VPSHUFBZrmk 2532328487U, // VPSHUFBZrmkz 2517648423U, // VPSHUFBZrr 49300519U, // VPSHUFBZrrk 2532328487U, // VPSHUFBZrrkz 2517648423U, // VPSHUFBrm 2517648423U, // VPSHUFBrr 3188738056U, // VPSHUFDYmi 2517649416U, // VPSHUFDYri 403720200U, // VPSHUFDZ128mbi 49301512U, // VPSHUFDZ128mbik 2532329480U, // VPSHUFDZ128mbikz 2484094984U, // VPSHUFDZ128mi 49301512U, // VPSHUFDZ128mik 2532329480U, // VPSHUFDZ128mikz 2517649416U, // VPSHUFDZ128ri 49301512U, // VPSHUFDZ128rik 2532329480U, // VPSHUFDZ128rikz 2551203848U, // VPSHUFDZ256mbi 49301512U, // VPSHUFDZ256mbik 2532329480U, // VPSHUFDZ256mbikz 3188738056U, // VPSHUFDZ256mi 49301512U, // VPSHUFDZ256mik 2532329480U, // VPSHUFDZ256mikz 2517649416U, // VPSHUFDZ256ri 49301512U, // VPSHUFDZ256rik 2532329480U, // VPSHUFDZ256rikz 403720200U, // VPSHUFDZmbi 49301512U, // VPSHUFDZmbik 2532329480U, // VPSHUFDZmbikz 2953857032U, // VPSHUFDZmi 49301512U, // VPSHUFDZmik 2532329480U, // VPSHUFDZmikz 2517649416U, // VPSHUFDZri 49301512U, // VPSHUFDZrik 2532329480U, // VPSHUFDZrikz 2484094984U, // VPSHUFDmi 2517649416U, // VPSHUFDri 3188745348U, // VPSHUFHWYmi 2517656708U, // VPSHUFHWYri 2484102276U, // VPSHUFHWZ128mi 49308804U, // VPSHUFHWZ128mik 2532336772U, // VPSHUFHWZ128mikz 2517656708U, // VPSHUFHWZ128ri 49308804U, // VPSHUFHWZ128rik 2532336772U, // VPSHUFHWZ128rikz 3188745348U, // VPSHUFHWZ256mi 49308804U, // VPSHUFHWZ256mik 2532336772U, // VPSHUFHWZ256mikz 2517656708U, // VPSHUFHWZ256ri 49308804U, // VPSHUFHWZ256rik 2532336772U, // VPSHUFHWZ256rikz 2953864324U, // VPSHUFHWZmi 49308804U, // VPSHUFHWZmik 2532336772U, // VPSHUFHWZmikz 2517656708U, // VPSHUFHWZri 49308804U, // VPSHUFHWZrik 2532336772U, // VPSHUFHWZrikz 2484102276U, // VPSHUFHWmi 2517656708U, // VPSHUFHWri 3188745374U, // VPSHUFLWYmi 2517656734U, // VPSHUFLWYri 2484102302U, // VPSHUFLWZ128mi 49308830U, // VPSHUFLWZ128mik 2532336798U, // VPSHUFLWZ128mikz 2517656734U, // VPSHUFLWZ128ri 49308830U, // VPSHUFLWZ128rik 2532336798U, // VPSHUFLWZ128rikz 3188745374U, // VPSHUFLWZ256mi 49308830U, // VPSHUFLWZ256mik 2532336798U, // VPSHUFLWZ256mikz 2517656734U, // VPSHUFLWZ256ri 49308830U, // VPSHUFLWZ256rik 2532336798U, // VPSHUFLWZ256rikz 2953864350U, // VPSHUFLWZmi 49308830U, // VPSHUFLWZmik 2532336798U, // VPSHUFLWZmikz 2517656734U, // VPSHUFLWZri 49308830U, // VPSHUFLWZrik 2532336798U, // VPSHUFLWZrikz 2484102302U, // VPSHUFLWmi 2517656734U, // VPSHUFLWri 2517648555U, // VPSIGNBYrm 2517648555U, // VPSIGNBYrr 2517648555U, // VPSIGNBrm 2517648555U, // VPSIGNBrr 2517649629U, // VPSIGNDYrm 2517649629U, // VPSIGNDYrr 2517649629U, // VPSIGNDrm 2517649629U, // VPSIGNDrr 2517656843U, // VPSIGNWYrm 2517656843U, // VPSIGNWYrr 2517656843U, // VPSIGNWrm 2517656843U, // VPSIGNWrr 2517653149U, // VPSLLDQYri 2484098717U, // VPSLLDQZ128rm 2517653149U, // VPSLLDQZ128rr 3188741789U, // VPSLLDQZ256rm 2517653149U, // VPSLLDQZ256rr 2953860765U, // VPSLLDQZrm 2517653149U, // VPSLLDQZrr 2517653149U, // VPSLLDQri 2517649488U, // VPSLLDYri 2517649488U, // VPSLLDYrm 2517649488U, // VPSLLDYrr 403720272U, // VPSLLDZ128mbi 49301584U, // VPSLLDZ128mbik 2532329552U, // VPSLLDZ128mbikz 2484095056U, // VPSLLDZ128mi 49301584U, // VPSLLDZ128mik 2532329552U, // VPSLLDZ128mikz 2517649488U, // VPSLLDZ128ri 49301584U, // VPSLLDZ128rik 2532329552U, // VPSLLDZ128rikz 2517649488U, // VPSLLDZ128rm 49301584U, // VPSLLDZ128rmk 2532329552U, // VPSLLDZ128rmkz 2517649488U, // VPSLLDZ128rr 49301584U, // VPSLLDZ128rrk 2532329552U, // VPSLLDZ128rrkz 2551203920U, // VPSLLDZ256mbi 49301584U, // VPSLLDZ256mbik 2532329552U, // VPSLLDZ256mbikz 3188738128U, // VPSLLDZ256mi 49301584U, // VPSLLDZ256mik 2532329552U, // VPSLLDZ256mikz 2517649488U, // VPSLLDZ256ri 49301584U, // VPSLLDZ256rik 2532329552U, // VPSLLDZ256rikz 2517649488U, // VPSLLDZ256rm 49301584U, // VPSLLDZ256rmk 2532329552U, // VPSLLDZ256rmkz 2517649488U, // VPSLLDZ256rr 49301584U, // VPSLLDZ256rrk 2532329552U, // VPSLLDZ256rrkz 403720272U, // VPSLLDZmbi 49301584U, // VPSLLDZmbik 2532329552U, // VPSLLDZmbikz 2953857104U, // VPSLLDZmi 49301584U, // VPSLLDZmik 2532329552U, // VPSLLDZmikz 2517649488U, // VPSLLDZri 49301584U, // VPSLLDZrik 2532329552U, // VPSLLDZrikz 2517649488U, // VPSLLDZrm 49301584U, // VPSLLDZrmk 2532329552U, // VPSLLDZrmkz 2517649488U, // VPSLLDZrr 49301584U, // VPSLLDZrrk 2532329552U, // VPSLLDZrrkz 2517649488U, // VPSLLDri 2517649488U, // VPSLLDrm 2517649488U, // VPSLLDrr 2517653413U, // VPSLLQYri 2517653413U, // VPSLLQYrm 2517653413U, // VPSLLQYrr 2584762277U, // VPSLLQZ128mbi 49305509U, // VPSLLQZ128mbik 2532333477U, // VPSLLQZ128mbikz 2484098981U, // VPSLLQZ128mi 49305509U, // VPSLLQZ128mik 2532333477U, // VPSLLQZ128mikz 2517653413U, // VPSLLQZ128ri 49305509U, // VPSLLQZ128rik 2532333477U, // VPSLLQZ128rikz 2517653413U, // VPSLLQZ128rm 49305509U, // VPSLLQZ128rmk 2532333477U, // VPSLLQZ128rmkz 2517653413U, // VPSLLQZ128rr 49305509U, // VPSLLQZ128rrk 2532333477U, // VPSLLQZ128rrkz 437278629U, // VPSLLQZ256mbi 49305509U, // VPSLLQZ256mbik 2532333477U, // VPSLLQZ256mbikz 3188742053U, // VPSLLQZ256mi 49305509U, // VPSLLQZ256mik 2532333477U, // VPSLLQZ256mikz 2517653413U, // VPSLLQZ256ri 49305509U, // VPSLLQZ256rik 2532333477U, // VPSLLQZ256rikz 2517653413U, // VPSLLQZ256rm 49305509U, // VPSLLQZ256rmk 2532333477U, // VPSLLQZ256rmkz 2517653413U, // VPSLLQZ256rr 49305509U, // VPSLLQZ256rrk 2532333477U, // VPSLLQZ256rrkz 2584762277U, // VPSLLQZmbi 49305509U, // VPSLLQZmbik 2532333477U, // VPSLLQZmbikz 2953861029U, // VPSLLQZmi 49305509U, // VPSLLQZmik 2532333477U, // VPSLLQZmikz 2517653413U, // VPSLLQZri 49305509U, // VPSLLQZrik 2532333477U, // VPSLLQZrikz 2517653413U, // VPSLLQZrm 49305509U, // VPSLLQZrmk 2532333477U, // VPSLLQZrmkz 2517653413U, // VPSLLQZrr 49305509U, // VPSLLQZrrk 2532333477U, // VPSLLQZrrkz 2517653413U, // VPSLLQri 2517653413U, // VPSLLQrm 2517653413U, // VPSLLQrr 2517651537U, // VPSLLVDYrm 2517651537U, // VPSLLVDYrr 2517651537U, // VPSLLVDZ128rm 2517651537U, // VPSLLVDZ128rmb 49303633U, // VPSLLVDZ128rmbk 2532331601U, // VPSLLVDZ128rmbkz 49303633U, // VPSLLVDZ128rmk 2532331601U, // VPSLLVDZ128rmkz 2517651537U, // VPSLLVDZ128rr 49303633U, // VPSLLVDZ128rrk 2532331601U, // VPSLLVDZ128rrkz 2517651537U, // VPSLLVDZ256rm 2517651537U, // VPSLLVDZ256rmb 49303633U, // VPSLLVDZ256rmbk 2532331601U, // VPSLLVDZ256rmbkz 49303633U, // VPSLLVDZ256rmk 2532331601U, // VPSLLVDZ256rmkz 2517651537U, // VPSLLVDZ256rr 49303633U, // VPSLLVDZ256rrk 2532331601U, // VPSLLVDZ256rrkz 2517651537U, // VPSLLVDZrm 2517651537U, // VPSLLVDZrmb 49303633U, // VPSLLVDZrmbk 2532331601U, // VPSLLVDZrmbkz 49303633U, // VPSLLVDZrmk 2532331601U, // VPSLLVDZrmkz 2517651537U, // VPSLLVDZrr 49303633U, // VPSLLVDZrrk 2532331601U, // VPSLLVDZrrkz 2517651537U, // VPSLLVDrm 2517651537U, // VPSLLVDrr 2517654031U, // VPSLLVQYrm 2517654031U, // VPSLLVQYrr 2517654031U, // VPSLLVQZ128rm 2517654031U, // VPSLLVQZ128rmb 49306127U, // VPSLLVQZ128rmbk 2532334095U, // VPSLLVQZ128rmbkz 49306127U, // VPSLLVQZ128rmk 2532334095U, // VPSLLVQZ128rmkz 2517654031U, // VPSLLVQZ128rr 49306127U, // VPSLLVQZ128rrk 2532334095U, // VPSLLVQZ128rrkz 2517654031U, // VPSLLVQZ256rm 2517654031U, // VPSLLVQZ256rmb 49306127U, // VPSLLVQZ256rmbk 2532334095U, // VPSLLVQZ256rmbkz 49306127U, // VPSLLVQZ256rmk 2532334095U, // VPSLLVQZ256rmkz 2517654031U, // VPSLLVQZ256rr 49306127U, // VPSLLVQZ256rrk 2532334095U, // VPSLLVQZ256rrkz 2517654031U, // VPSLLVQZrm 2517654031U, // VPSLLVQZrmb 49306127U, // VPSLLVQZrmbk 2532334095U, // VPSLLVQZrmbkz 49306127U, // VPSLLVQZrmk 2532334095U, // VPSLLVQZrmkz 2517654031U, // VPSLLVQZrr 49306127U, // VPSLLVQZrrk 2532334095U, // VPSLLVQZrrkz 2517654031U, // VPSLLVQrm 2517654031U, // VPSLLVQrr 2517657280U, // VPSLLVWZ128rm 49309376U, // VPSLLVWZ128rmk 2532337344U, // VPSLLVWZ128rmkz 2517657280U, // VPSLLVWZ128rr 49309376U, // VPSLLVWZ128rrk 2532337344U, // VPSLLVWZ128rrkz 2517657280U, // VPSLLVWZ256rm 49309376U, // VPSLLVWZ256rmk 2532337344U, // VPSLLVWZ256rmkz 2517657280U, // VPSLLVWZ256rr 49309376U, // VPSLLVWZ256rrk 2532337344U, // VPSLLVWZ256rrkz 2517657280U, // VPSLLVWZrm 49309376U, // VPSLLVWZrmk 2532337344U, // VPSLLVWZrmkz 2517657280U, // VPSLLVWZrr 49309376U, // VPSLLVWZrrk 2532337344U, // VPSLLVWZrrkz 2517656752U, // VPSLLWYri 2517656752U, // VPSLLWYrm 2517656752U, // VPSLLWYrr 2484102320U, // VPSLLWZ128mi 49308848U, // VPSLLWZ128mik 2532336816U, // VPSLLWZ128mikz 2517656752U, // VPSLLWZ128ri 49308848U, // VPSLLWZ128rik 2532336816U, // VPSLLWZ128rikz 2517656752U, // VPSLLWZ128rm 49308848U, // VPSLLWZ128rmk 2532336816U, // VPSLLWZ128rmkz 2517656752U, // VPSLLWZ128rr 49308848U, // VPSLLWZ128rrk 2532336816U, // VPSLLWZ128rrkz 3188745392U, // VPSLLWZ256mi 49308848U, // VPSLLWZ256mik 2532336816U, // VPSLLWZ256mikz 2517656752U, // VPSLLWZ256ri 49308848U, // VPSLLWZ256rik 2532336816U, // VPSLLWZ256rikz 2517656752U, // VPSLLWZ256rm 49308848U, // VPSLLWZ256rmk 2532336816U, // VPSLLWZ256rmkz 2517656752U, // VPSLLWZ256rr 49308848U, // VPSLLWZ256rrk 2532336816U, // VPSLLWZ256rrkz 2953864368U, // VPSLLWZmi 49308848U, // VPSLLWZmik 2532336816U, // VPSLLWZmikz 2517656752U, // VPSLLWZri 49308848U, // VPSLLWZrik 2532336816U, // VPSLLWZrikz 2517656752U, // VPSLLWZrm 49308848U, // VPSLLWZrmk 2532336816U, // VPSLLWZrmkz 2517656752U, // VPSLLWZrr 49308848U, // VPSLLWZrrk 2532336816U, // VPSLLWZrrkz 2517656752U, // VPSLLWri 2517656752U, // VPSLLWrm 2517656752U, // VPSLLWrr 2517649189U, // VPSRADYri 2517649189U, // VPSRADYrm 2517649189U, // VPSRADYrr 403719973U, // VPSRADZ128mbi 49301285U, // VPSRADZ128mbik 2532329253U, // VPSRADZ128mbikz 2484094757U, // VPSRADZ128mi 49301285U, // VPSRADZ128mik 2532329253U, // VPSRADZ128mikz 2517649189U, // VPSRADZ128ri 49301285U, // VPSRADZ128rik 2532329253U, // VPSRADZ128rikz 2517649189U, // VPSRADZ128rm 49301285U, // VPSRADZ128rmk 2532329253U, // VPSRADZ128rmkz 2517649189U, // VPSRADZ128rr 49301285U, // VPSRADZ128rrk 2532329253U, // VPSRADZ128rrkz 2551203621U, // VPSRADZ256mbi 49301285U, // VPSRADZ256mbik 2532329253U, // VPSRADZ256mbikz 3188737829U, // VPSRADZ256mi 49301285U, // VPSRADZ256mik 2532329253U, // VPSRADZ256mikz 2517649189U, // VPSRADZ256ri 49301285U, // VPSRADZ256rik 2532329253U, // VPSRADZ256rikz 2517649189U, // VPSRADZ256rm 49301285U, // VPSRADZ256rmk 2532329253U, // VPSRADZ256rmkz 2517649189U, // VPSRADZ256rr 49301285U, // VPSRADZ256rrk 2532329253U, // VPSRADZ256rrkz 403719973U, // VPSRADZmbi 49301285U, // VPSRADZmbik 2532329253U, // VPSRADZmbikz 2953856805U, // VPSRADZmi 49301285U, // VPSRADZmik 2532329253U, // VPSRADZmikz 2517649189U, // VPSRADZri 49301285U, // VPSRADZrik 2532329253U, // VPSRADZrikz 2517649189U, // VPSRADZrm 49301285U, // VPSRADZrmk 2532329253U, // VPSRADZrmkz 2517649189U, // VPSRADZrr 49301285U, // VPSRADZrrk 2532329253U, // VPSRADZrrkz 2517649189U, // VPSRADri 2517649189U, // VPSRADrm 2517649189U, // VPSRADrr 2584761821U, // VPSRAQZ128mbi 49305053U, // VPSRAQZ128mbik 2532333021U, // VPSRAQZ128mbikz 2484098525U, // VPSRAQZ128mi 49305053U, // VPSRAQZ128mik 2532333021U, // VPSRAQZ128mikz 2517652957U, // VPSRAQZ128ri 49305053U, // VPSRAQZ128rik 2532333021U, // VPSRAQZ128rikz 2517652957U, // VPSRAQZ128rm 49305053U, // VPSRAQZ128rmk 2532333021U, // VPSRAQZ128rmkz 2517652957U, // VPSRAQZ128rr 49305053U, // VPSRAQZ128rrk 2532333021U, // VPSRAQZ128rrkz 437278173U, // VPSRAQZ256mbi 49305053U, // VPSRAQZ256mbik 2532333021U, // VPSRAQZ256mbikz 3188741597U, // VPSRAQZ256mi 49305053U, // VPSRAQZ256mik 2532333021U, // VPSRAQZ256mikz 2517652957U, // VPSRAQZ256ri 49305053U, // VPSRAQZ256rik 2532333021U, // VPSRAQZ256rikz 2517652957U, // VPSRAQZ256rm 49305053U, // VPSRAQZ256rmk 2532333021U, // VPSRAQZ256rmkz 2517652957U, // VPSRAQZ256rr 49305053U, // VPSRAQZ256rrk 2532333021U, // VPSRAQZ256rrkz 2584761821U, // VPSRAQZmbi 49305053U, // VPSRAQZmbik 2532333021U, // VPSRAQZmbikz 2953860573U, // VPSRAQZmi 49305053U, // VPSRAQZmik 2532333021U, // VPSRAQZmikz 2517652957U, // VPSRAQZri 49305053U, // VPSRAQZrik 2532333021U, // VPSRAQZrikz 2517652957U, // VPSRAQZrm 49305053U, // VPSRAQZrmk 2532333021U, // VPSRAQZrmkz 2517652957U, // VPSRAQZrr 49305053U, // VPSRAQZrrk 2532333021U, // VPSRAQZrrkz 2517651508U, // VPSRAVDYrm 2517651508U, // VPSRAVDYrr 2517651508U, // VPSRAVDZ128rm 2517651508U, // VPSRAVDZ128rmb 49303604U, // VPSRAVDZ128rmbk 2532331572U, // VPSRAVDZ128rmbkz 49303604U, // VPSRAVDZ128rmk 2532331572U, // VPSRAVDZ128rmkz 2517651508U, // VPSRAVDZ128rr 49303604U, // VPSRAVDZ128rrk 2532331572U, // VPSRAVDZ128rrkz 2517651508U, // VPSRAVDZ256rm 2517651508U, // VPSRAVDZ256rmb 49303604U, // VPSRAVDZ256rmbk 2532331572U, // VPSRAVDZ256rmbkz 49303604U, // VPSRAVDZ256rmk 2532331572U, // VPSRAVDZ256rmkz 2517651508U, // VPSRAVDZ256rr 49303604U, // VPSRAVDZ256rrk 2532331572U, // VPSRAVDZ256rrkz 2517651508U, // VPSRAVDZrm 2517651508U, // VPSRAVDZrmb 49303604U, // VPSRAVDZrmbk 2532331572U, // VPSRAVDZrmbkz 49303604U, // VPSRAVDZrmk 2532331572U, // VPSRAVDZrmkz 2517651508U, // VPSRAVDZrr 49303604U, // VPSRAVDZrrk 2532331572U, // VPSRAVDZrrkz 2517651508U, // VPSRAVDrm 2517651508U, // VPSRAVDrr 2517654002U, // VPSRAVQZ128rm 2517654002U, // VPSRAVQZ128rmb 49306098U, // VPSRAVQZ128rmbk 2532334066U, // VPSRAVQZ128rmbkz 49306098U, // VPSRAVQZ128rmk 2532334066U, // VPSRAVQZ128rmkz 2517654002U, // VPSRAVQZ128rr 49306098U, // VPSRAVQZ128rrk 2532334066U, // VPSRAVQZ128rrkz 2517654002U, // VPSRAVQZ256rm 2517654002U, // VPSRAVQZ256rmb 49306098U, // VPSRAVQZ256rmbk 2532334066U, // VPSRAVQZ256rmbkz 49306098U, // VPSRAVQZ256rmk 2532334066U, // VPSRAVQZ256rmkz 2517654002U, // VPSRAVQZ256rr 49306098U, // VPSRAVQZ256rrk 2532334066U, // VPSRAVQZ256rrkz 2517654002U, // VPSRAVQZrm 2517654002U, // VPSRAVQZrmb 49306098U, // VPSRAVQZrmbk 2532334066U, // VPSRAVQZrmbkz 49306098U, // VPSRAVQZrmk 2532334066U, // VPSRAVQZrmkz 2517654002U, // VPSRAVQZrr 49306098U, // VPSRAVQZrrk 2532334066U, // VPSRAVQZrrkz 2517657251U, // VPSRAVWZ128rm 49309347U, // VPSRAVWZ128rmk 2532337315U, // VPSRAVWZ128rmkz 2517657251U, // VPSRAVWZ128rr 49309347U, // VPSRAVWZ128rrk 2532337315U, // VPSRAVWZ128rrkz 2517657251U, // VPSRAVWZ256rm 49309347U, // VPSRAVWZ256rmk 2532337315U, // VPSRAVWZ256rmkz 2517657251U, // VPSRAVWZ256rr 49309347U, // VPSRAVWZ256rrk 2532337315U, // VPSRAVWZ256rrkz 2517657251U, // VPSRAVWZrm 49309347U, // VPSRAVWZrmk 2532337315U, // VPSRAVWZrmkz 2517657251U, // VPSRAVWZrr 49309347U, // VPSRAVWZrrk 2532337315U, // VPSRAVWZrrkz 2517656395U, // VPSRAWYri 2517656395U, // VPSRAWYrm 2517656395U, // VPSRAWYrr 2484101963U, // VPSRAWZ128mi 49308491U, // VPSRAWZ128mik 2532336459U, // VPSRAWZ128mikz 2517656395U, // VPSRAWZ128ri 49308491U, // VPSRAWZ128rik 2532336459U, // VPSRAWZ128rikz 2517656395U, // VPSRAWZ128rm 49308491U, // VPSRAWZ128rmk 2532336459U, // VPSRAWZ128rmkz 2517656395U, // VPSRAWZ128rr 49308491U, // VPSRAWZ128rrk 2532336459U, // VPSRAWZ128rrkz 3188745035U, // VPSRAWZ256mi 49308491U, // VPSRAWZ256mik 2532336459U, // VPSRAWZ256mikz 2517656395U, // VPSRAWZ256ri 49308491U, // VPSRAWZ256rik 2532336459U, // VPSRAWZ256rikz 2517656395U, // VPSRAWZ256rm 49308491U, // VPSRAWZ256rmk 2532336459U, // VPSRAWZ256rmkz 2517656395U, // VPSRAWZ256rr 49308491U, // VPSRAWZ256rrk 2532336459U, // VPSRAWZ256rrkz 2953864011U, // VPSRAWZmi 49308491U, // VPSRAWZmik 2532336459U, // VPSRAWZmikz 2517656395U, // VPSRAWZri 49308491U, // VPSRAWZrik 2532336459U, // VPSRAWZrikz 2517656395U, // VPSRAWZrm 49308491U, // VPSRAWZrmk 2532336459U, // VPSRAWZrmkz 2517656395U, // VPSRAWZrr 49308491U, // VPSRAWZrrk 2532336459U, // VPSRAWZrrkz 2517656395U, // VPSRAWri 2517656395U, // VPSRAWrm 2517656395U, // VPSRAWrr 2517653158U, // VPSRLDQYri 2484098726U, // VPSRLDQZ128rm 2517653158U, // VPSRLDQZ128rr 3188741798U, // VPSRLDQZ256rm 2517653158U, // VPSRLDQZ256rr 2953860774U, // VPSRLDQZrm 2517653158U, // VPSRLDQZrr 2517653158U, // VPSRLDQri 2517649513U, // VPSRLDYri 2517649513U, // VPSRLDYrm 2517649513U, // VPSRLDYrr 403720297U, // VPSRLDZ128mbi 49301609U, // VPSRLDZ128mbik 2532329577U, // VPSRLDZ128mbikz 2484095081U, // VPSRLDZ128mi 49301609U, // VPSRLDZ128mik 2532329577U, // VPSRLDZ128mikz 2517649513U, // VPSRLDZ128ri 49301609U, // VPSRLDZ128rik 2532329577U, // VPSRLDZ128rikz 2517649513U, // VPSRLDZ128rm 49301609U, // VPSRLDZ128rmk 2532329577U, // VPSRLDZ128rmkz 2517649513U, // VPSRLDZ128rr 49301609U, // VPSRLDZ128rrk 2532329577U, // VPSRLDZ128rrkz 2551203945U, // VPSRLDZ256mbi 49301609U, // VPSRLDZ256mbik 2532329577U, // VPSRLDZ256mbikz 3188738153U, // VPSRLDZ256mi 49301609U, // VPSRLDZ256mik 2532329577U, // VPSRLDZ256mikz 2517649513U, // VPSRLDZ256ri 49301609U, // VPSRLDZ256rik 2532329577U, // VPSRLDZ256rikz 2517649513U, // VPSRLDZ256rm 49301609U, // VPSRLDZ256rmk 2532329577U, // VPSRLDZ256rmkz 2517649513U, // VPSRLDZ256rr 49301609U, // VPSRLDZ256rrk 2532329577U, // VPSRLDZ256rrkz 403720297U, // VPSRLDZmbi 49301609U, // VPSRLDZmbik 2532329577U, // VPSRLDZmbikz 2953857129U, // VPSRLDZmi 49301609U, // VPSRLDZmik 2532329577U, // VPSRLDZmikz 2517649513U, // VPSRLDZri 49301609U, // VPSRLDZrik 2532329577U, // VPSRLDZrikz 2517649513U, // VPSRLDZrm 49301609U, // VPSRLDZrmk 2532329577U, // VPSRLDZrmkz 2517649513U, // VPSRLDZrr 49301609U, // VPSRLDZrrk 2532329577U, // VPSRLDZrrkz 2517649513U, // VPSRLDri 2517649513U, // VPSRLDrm 2517649513U, // VPSRLDrr 2517653438U, // VPSRLQYri 2517653438U, // VPSRLQYrm 2517653438U, // VPSRLQYrr 2584762302U, // VPSRLQZ128mbi 49305534U, // VPSRLQZ128mbik 2532333502U, // VPSRLQZ128mbikz 2484099006U, // VPSRLQZ128mi 49305534U, // VPSRLQZ128mik 2532333502U, // VPSRLQZ128mikz 2517653438U, // VPSRLQZ128ri 49305534U, // VPSRLQZ128rik 2532333502U, // VPSRLQZ128rikz 2517653438U, // VPSRLQZ128rm 49305534U, // VPSRLQZ128rmk 2532333502U, // VPSRLQZ128rmkz 2517653438U, // VPSRLQZ128rr 49305534U, // VPSRLQZ128rrk 2532333502U, // VPSRLQZ128rrkz 437278654U, // VPSRLQZ256mbi 49305534U, // VPSRLQZ256mbik 2532333502U, // VPSRLQZ256mbikz 3188742078U, // VPSRLQZ256mi 49305534U, // VPSRLQZ256mik 2532333502U, // VPSRLQZ256mikz 2517653438U, // VPSRLQZ256ri 49305534U, // VPSRLQZ256rik 2532333502U, // VPSRLQZ256rikz 2517653438U, // VPSRLQZ256rm 49305534U, // VPSRLQZ256rmk 2532333502U, // VPSRLQZ256rmkz 2517653438U, // VPSRLQZ256rr 49305534U, // VPSRLQZ256rrk 2532333502U, // VPSRLQZ256rrkz 2584762302U, // VPSRLQZmbi 49305534U, // VPSRLQZmbik 2532333502U, // VPSRLQZmbikz 2953861054U, // VPSRLQZmi 49305534U, // VPSRLQZmik 2532333502U, // VPSRLQZmikz 2517653438U, // VPSRLQZri 49305534U, // VPSRLQZrik 2532333502U, // VPSRLQZrikz 2517653438U, // VPSRLQZrm 49305534U, // VPSRLQZrmk 2532333502U, // VPSRLQZrmkz 2517653438U, // VPSRLQZrr 49305534U, // VPSRLQZrrk 2532333502U, // VPSRLQZrrkz 2517653438U, // VPSRLQri 2517653438U, // VPSRLQrm 2517653438U, // VPSRLQrr 2517651555U, // VPSRLVDYrm 2517651555U, // VPSRLVDYrr 2517651555U, // VPSRLVDZ128rm 2517651555U, // VPSRLVDZ128rmb 49303651U, // VPSRLVDZ128rmbk 2532331619U, // VPSRLVDZ128rmbkz 49303651U, // VPSRLVDZ128rmk 2532331619U, // VPSRLVDZ128rmkz 2517651555U, // VPSRLVDZ128rr 49303651U, // VPSRLVDZ128rrk 2532331619U, // VPSRLVDZ128rrkz 2517651555U, // VPSRLVDZ256rm 2517651555U, // VPSRLVDZ256rmb 49303651U, // VPSRLVDZ256rmbk 2532331619U, // VPSRLVDZ256rmbkz 49303651U, // VPSRLVDZ256rmk 2532331619U, // VPSRLVDZ256rmkz 2517651555U, // VPSRLVDZ256rr 49303651U, // VPSRLVDZ256rrk 2532331619U, // VPSRLVDZ256rrkz 2517651555U, // VPSRLVDZrm 2517651555U, // VPSRLVDZrmb 49303651U, // VPSRLVDZrmbk 2532331619U, // VPSRLVDZrmbkz 49303651U, // VPSRLVDZrmk 2532331619U, // VPSRLVDZrmkz 2517651555U, // VPSRLVDZrr 49303651U, // VPSRLVDZrrk 2532331619U, // VPSRLVDZrrkz 2517651555U, // VPSRLVDrm 2517651555U, // VPSRLVDrr 2517654049U, // VPSRLVQYrm 2517654049U, // VPSRLVQYrr 2517654049U, // VPSRLVQZ128rm 2517654049U, // VPSRLVQZ128rmb 49306145U, // VPSRLVQZ128rmbk 2532334113U, // VPSRLVQZ128rmbkz 49306145U, // VPSRLVQZ128rmk 2532334113U, // VPSRLVQZ128rmkz 2517654049U, // VPSRLVQZ128rr 49306145U, // VPSRLVQZ128rrk 2532334113U, // VPSRLVQZ128rrkz 2517654049U, // VPSRLVQZ256rm 2517654049U, // VPSRLVQZ256rmb 49306145U, // VPSRLVQZ256rmbk 2532334113U, // VPSRLVQZ256rmbkz 49306145U, // VPSRLVQZ256rmk 2532334113U, // VPSRLVQZ256rmkz 2517654049U, // VPSRLVQZ256rr 49306145U, // VPSRLVQZ256rrk 2532334113U, // VPSRLVQZ256rrkz 2517654049U, // VPSRLVQZrm 2517654049U, // VPSRLVQZrmb 49306145U, // VPSRLVQZrmbk 2532334113U, // VPSRLVQZrmbkz 49306145U, // VPSRLVQZrmk 2532334113U, // VPSRLVQZrmkz 2517654049U, // VPSRLVQZrr 49306145U, // VPSRLVQZrrk 2532334113U, // VPSRLVQZrrkz 2517654049U, // VPSRLVQrm 2517654049U, // VPSRLVQrr 2517657289U, // VPSRLVWZ128rm 49309385U, // VPSRLVWZ128rmk 2532337353U, // VPSRLVWZ128rmkz 2517657289U, // VPSRLVWZ128rr 49309385U, // VPSRLVWZ128rrk 2532337353U, // VPSRLVWZ128rrkz 2517657289U, // VPSRLVWZ256rm 49309385U, // VPSRLVWZ256rmk 2532337353U, // VPSRLVWZ256rmkz 2517657289U, // VPSRLVWZ256rr 49309385U, // VPSRLVWZ256rrk 2532337353U, // VPSRLVWZ256rrkz 2517657289U, // VPSRLVWZrm 49309385U, // VPSRLVWZrmk 2532337353U, // VPSRLVWZrmkz 2517657289U, // VPSRLVWZrr 49309385U, // VPSRLVWZrrk 2532337353U, // VPSRLVWZrrkz 2517656769U, // VPSRLWYri 2517656769U, // VPSRLWYrm 2517656769U, // VPSRLWYrr 2484102337U, // VPSRLWZ128mi 49308865U, // VPSRLWZ128mik 2532336833U, // VPSRLWZ128mikz 2517656769U, // VPSRLWZ128ri 49308865U, // VPSRLWZ128rik 2532336833U, // VPSRLWZ128rikz 2517656769U, // VPSRLWZ128rm 49308865U, // VPSRLWZ128rmk 2532336833U, // VPSRLWZ128rmkz 2517656769U, // VPSRLWZ128rr 49308865U, // VPSRLWZ128rrk 2532336833U, // VPSRLWZ128rrkz 3188745409U, // VPSRLWZ256mi 49308865U, // VPSRLWZ256mik 2532336833U, // VPSRLWZ256mikz 2517656769U, // VPSRLWZ256ri 49308865U, // VPSRLWZ256rik 2532336833U, // VPSRLWZ256rikz 2517656769U, // VPSRLWZ256rm 49308865U, // VPSRLWZ256rmk 2532336833U, // VPSRLWZ256rmkz 2517656769U, // VPSRLWZ256rr 49308865U, // VPSRLWZ256rrk 2532336833U, // VPSRLWZ256rrkz 2953864385U, // VPSRLWZmi 49308865U, // VPSRLWZmik 2532336833U, // VPSRLWZmikz 2517656769U, // VPSRLWZri 49308865U, // VPSRLWZrik 2532336833U, // VPSRLWZrikz 2517656769U, // VPSRLWZrm 49308865U, // VPSRLWZrmk 2532336833U, // VPSRLWZrmkz 2517656769U, // VPSRLWZrr 49308865U, // VPSRLWZrrk 2532336833U, // VPSRLWZrrkz 2517656769U, // VPSRLWri 2517656769U, // VPSRLWrm 2517656769U, // VPSRLWrr 2517648336U, // VPSUBBYrm 2517648336U, // VPSUBBYrr 2517648336U, // VPSUBBZ128rm 49300432U, // VPSUBBZ128rmk 2532328400U, // VPSUBBZ128rmkz 2517648336U, // VPSUBBZ128rr 49300432U, // VPSUBBZ128rrk 2532328400U, // VPSUBBZ128rrkz 2517648336U, // VPSUBBZ256rm 49300432U, // VPSUBBZ256rmk 2532328400U, // VPSUBBZ256rmkz 2517648336U, // VPSUBBZ256rr 49300432U, // VPSUBBZ256rrk 2532328400U, // VPSUBBZ256rrkz 2517648336U, // VPSUBBZrm 49300432U, // VPSUBBZrmk 2532328400U, // VPSUBBZrmkz 2517648336U, // VPSUBBZrr 49300432U, // VPSUBBZrrk 2532328400U, // VPSUBBZrrkz 2517648336U, // VPSUBBrm 2517648336U, // VPSUBBrr 2517649227U, // VPSUBDYrm 2517649227U, // VPSUBDYrr 2517649227U, // VPSUBDZ128rm 2517649227U, // VPSUBDZ128rmb 49301323U, // VPSUBDZ128rmbk 2532329291U, // VPSUBDZ128rmbkz 49301323U, // VPSUBDZ128rmk 2532329291U, // VPSUBDZ128rmkz 2517649227U, // VPSUBDZ128rr 49301323U, // VPSUBDZ128rrk 2532329291U, // VPSUBDZ128rrkz 2517649227U, // VPSUBDZ256rm 2517649227U, // VPSUBDZ256rmb 49301323U, // VPSUBDZ256rmbk 2532329291U, // VPSUBDZ256rmbkz 49301323U, // VPSUBDZ256rmk 2532329291U, // VPSUBDZ256rmkz 2517649227U, // VPSUBDZ256rr 49301323U, // VPSUBDZ256rrk 2532329291U, // VPSUBDZ256rrkz 2517649227U, // VPSUBDZrm 2517649227U, // VPSUBDZrmb 49301323U, // VPSUBDZrmbk 2532329291U, // VPSUBDZrmbkz 49301323U, // VPSUBDZrmk 2532329291U, // VPSUBDZrmkz 2517649227U, // VPSUBDZrr 49301323U, // VPSUBDZrrk 2532329291U, // VPSUBDZrrkz 2517649227U, // VPSUBDrm 2517649227U, // VPSUBDrr 2517652986U, // VPSUBQYrm 2517652986U, // VPSUBQYrr 2517652986U, // VPSUBQZ128rm 2517652986U, // VPSUBQZ128rmb 49305082U, // VPSUBQZ128rmbk 2532333050U, // VPSUBQZ128rmbkz 49305082U, // VPSUBQZ128rmk 2532333050U, // VPSUBQZ128rmkz 2517652986U, // VPSUBQZ128rr 49305082U, // VPSUBQZ128rrk 2532333050U, // VPSUBQZ128rrkz 2517652986U, // VPSUBQZ256rm 2517652986U, // VPSUBQZ256rmb 49305082U, // VPSUBQZ256rmbk 2532333050U, // VPSUBQZ256rmbkz 49305082U, // VPSUBQZ256rmk 2532333050U, // VPSUBQZ256rmkz 2517652986U, // VPSUBQZ256rr 49305082U, // VPSUBQZ256rrk 2532333050U, // VPSUBQZ256rrkz 2517652986U, // VPSUBQZrm 2517652986U, // VPSUBQZrmb 49305082U, // VPSUBQZrmbk 2532333050U, // VPSUBQZrmbkz 49305082U, // VPSUBQZrmk 2532333050U, // VPSUBQZrmkz 2517652986U, // VPSUBQZrr 49305082U, // VPSUBQZrrk 2532333050U, // VPSUBQZrrkz 2517652986U, // VPSUBQrm 2517652986U, // VPSUBQrr 2517648720U, // VPSUBSBYrm 2517648720U, // VPSUBSBYrr 2517648720U, // VPSUBSBZ128rm 49300816U, // VPSUBSBZ128rmk 2532328784U, // VPSUBSBZ128rmkz 2517648720U, // VPSUBSBZ128rr 49300816U, // VPSUBSBZ128rrk 2532328784U, // VPSUBSBZ128rrkz 2517648720U, // VPSUBSBZ256rm 49300816U, // VPSUBSBZ256rmk 2532328784U, // VPSUBSBZ256rmkz 2517648720U, // VPSUBSBZ256rr 49300816U, // VPSUBSBZ256rrk 2532328784U, // VPSUBSBZ256rrkz 2517648720U, // VPSUBSBZrm 49300816U, // VPSUBSBZrmk 2532328784U, // VPSUBSBZrmkz 2517648720U, // VPSUBSBZrr 49300816U, // VPSUBSBZrrk 2532328784U, // VPSUBSBZrrkz 2517648720U, // VPSUBSBrm 2517648720U, // VPSUBSBrr 2517656994U, // VPSUBSWYrm 2517656994U, // VPSUBSWYrr 2517656994U, // VPSUBSWZ128rm 49309090U, // VPSUBSWZ128rmk 2532337058U, // VPSUBSWZ128rmkz 2517656994U, // VPSUBSWZ128rr 49309090U, // VPSUBSWZ128rrk 2532337058U, // VPSUBSWZ128rrkz 2517656994U, // VPSUBSWZ256rm 49309090U, // VPSUBSWZ256rmk 2532337058U, // VPSUBSWZ256rmkz 2517656994U, // VPSUBSWZ256rr 49309090U, // VPSUBSWZ256rrk 2532337058U, // VPSUBSWZ256rrkz 2517656994U, // VPSUBSWZrm 49309090U, // VPSUBSWZrmk 2532337058U, // VPSUBSWZrmkz 2517656994U, // VPSUBSWZrr 49309090U, // VPSUBSWZrrk 2532337058U, // VPSUBSWZrrkz 2517656994U, // VPSUBSWrm 2517656994U, // VPSUBSWrr 2517648774U, // VPSUBUSBYrm 2517648774U, // VPSUBUSBYrr 2517648774U, // VPSUBUSBZ128rm 49300870U, // VPSUBUSBZ128rmk 2532328838U, // VPSUBUSBZ128rmkz 2517648774U, // VPSUBUSBZ128rr 49300870U, // VPSUBUSBZ128rrk 2532328838U, // VPSUBUSBZ128rrkz 2517648774U, // VPSUBUSBZ256rm 49300870U, // VPSUBUSBZ256rmk 2532328838U, // VPSUBUSBZ256rmkz 2517648774U, // VPSUBUSBZ256rr 49300870U, // VPSUBUSBZ256rrk 2532328838U, // VPSUBUSBZ256rrkz 2517648774U, // VPSUBUSBZrm 49300870U, // VPSUBUSBZrmk 2532328838U, // VPSUBUSBZrmkz 2517648774U, // VPSUBUSBZrr 49300870U, // VPSUBUSBZrrk 2532328838U, // VPSUBUSBZrrkz 2517648774U, // VPSUBUSBrm 2517648774U, // VPSUBUSBrr 2517657089U, // VPSUBUSWYrm 2517657089U, // VPSUBUSWYrr 2517657089U, // VPSUBUSWZ128rm 49309185U, // VPSUBUSWZ128rmk 2532337153U, // VPSUBUSWZ128rmkz 2517657089U, // VPSUBUSWZ128rr 49309185U, // VPSUBUSWZ128rrk 2532337153U, // VPSUBUSWZ128rrkz 2517657089U, // VPSUBUSWZ256rm 49309185U, // VPSUBUSWZ256rmk 2532337153U, // VPSUBUSWZ256rmkz 2517657089U, // VPSUBUSWZ256rr 49309185U, // VPSUBUSWZ256rrk 2532337153U, // VPSUBUSWZ256rrkz 2517657089U, // VPSUBUSWZrm 49309185U, // VPSUBUSWZrmk 2532337153U, // VPSUBUSWZrmkz 2517657089U, // VPSUBUSWZrr 49309185U, // VPSUBUSWZrrk 2532337153U, // VPSUBUSWZrrkz 2517657089U, // VPSUBUSWrm 2517657089U, // VPSUBUSWrr 2517656507U, // VPSUBWYrm 2517656507U, // VPSUBWYrr 2517656507U, // VPSUBWZ128rm 49308603U, // VPSUBWZ128rmk 2532336571U, // VPSUBWZ128rmkz 2517656507U, // VPSUBWZ128rr 49308603U, // VPSUBWZ128rrk 2532336571U, // VPSUBWZ128rrkz 2517656507U, // VPSUBWZ256rm 49308603U, // VPSUBWZ256rmk 2532336571U, // VPSUBWZ256rmkz 2517656507U, // VPSUBWZ256rr 49308603U, // VPSUBWZ256rrk 2532336571U, // VPSUBWZ256rrkz 2517656507U, // VPSUBWZrm 49308603U, // VPSUBWZrmk 2532336571U, // VPSUBWZrmkz 2517656507U, // VPSUBWZrr 49308603U, // VPSUBWZrrk 2532336571U, // VPSUBWZrrkz 2517656507U, // VPSUBWrm 2517656507U, // VPSUBWrr 2182105105U, // VPTERNLOGDZ128rmbi 49301521U, // VPTERNLOGDZ128rmbik 2196785169U, // VPTERNLOGDZ128rmbikz 2182105105U, // VPTERNLOGDZ128rmi 49301521U, // VPTERNLOGDZ128rmik 2196785169U, // VPTERNLOGDZ128rmikz 2182105105U, // VPTERNLOGDZ128rri 49301521U, // VPTERNLOGDZ128rrik 2196785169U, // VPTERNLOGDZ128rrikz 2182105105U, // VPTERNLOGDZ256rmbi 49301521U, // VPTERNLOGDZ256rmbik 2196785169U, // VPTERNLOGDZ256rmbikz 2182105105U, // VPTERNLOGDZ256rmi 49301521U, // VPTERNLOGDZ256rmik 2196785169U, // VPTERNLOGDZ256rmikz 2182105105U, // VPTERNLOGDZ256rri 49301521U, // VPTERNLOGDZ256rrik 2196785169U, // VPTERNLOGDZ256rrikz 2182105105U, // VPTERNLOGDZrmbi 49301521U, // VPTERNLOGDZrmbik 2196785169U, // VPTERNLOGDZrmbikz 2182105105U, // VPTERNLOGDZrmi 49301521U, // VPTERNLOGDZrmik 2196785169U, // VPTERNLOGDZrmikz 2182105105U, // VPTERNLOGDZrri 49301521U, // VPTERNLOGDZrrik 2196785169U, // VPTERNLOGDZrrikz 2182109073U, // VPTERNLOGQZ128rmbi 49305489U, // VPTERNLOGQZ128rmbik 2196789137U, // VPTERNLOGQZ128rmbikz 2182109073U, // VPTERNLOGQZ128rmi 49305489U, // VPTERNLOGQZ128rmik 2196789137U, // VPTERNLOGQZ128rmikz 2182109073U, // VPTERNLOGQZ128rri 49305489U, // VPTERNLOGQZ128rrik 2196789137U, // VPTERNLOGQZ128rrikz 2182109073U, // VPTERNLOGQZ256rmbi 49305489U, // VPTERNLOGQZ256rmbik 2196789137U, // VPTERNLOGQZ256rmbikz 2182109073U, // VPTERNLOGQZ256rmi 49305489U, // VPTERNLOGQZ256rmik 2196789137U, // VPTERNLOGQZ256rmikz 2182109073U, // VPTERNLOGQZ256rri 49305489U, // VPTERNLOGQZ256rrik 2196789137U, // VPTERNLOGQZ256rrikz 2182109073U, // VPTERNLOGQZrmbi 49305489U, // VPTERNLOGQZrmbik 2196789137U, // VPTERNLOGQZrmbikz 2182109073U, // VPTERNLOGQZrmi 49305489U, // VPTERNLOGQZrmik 2196789137U, // VPTERNLOGQZrmikz 2182109073U, // VPTERNLOGQZrri 49305489U, // VPTERNLOGQZrrik 2196789137U, // VPTERNLOGQZrrikz 2517648537U, // VPTESTMBZ128rm 384844953U, // VPTESTMBZ128rmk 2517648537U, // VPTESTMBZ128rr 384844953U, // VPTESTMBZ128rrk 2517648537U, // VPTESTMBZ256rm 384844953U, // VPTESTMBZ256rmk 2517648537U, // VPTESTMBZ256rr 384844953U, // VPTESTMBZ256rrk 2517648537U, // VPTESTMBZrm 384844953U, // VPTESTMBZrmk 2517648537U, // VPTESTMBZrr 384844953U, // VPTESTMBZrrk 2517649578U, // VPTESTMDZ128rm 2517649578U, // VPTESTMDZ128rmb 384845994U, // VPTESTMDZ128rmbk 384845994U, // VPTESTMDZ128rmk 2517649578U, // VPTESTMDZ128rr 384845994U, // VPTESTMDZ128rrk 2517649578U, // VPTESTMDZ256rm 2517649578U, // VPTESTMDZ256rmb 384845994U, // VPTESTMDZ256rmbk 384845994U, // VPTESTMDZ256rmk 2517649578U, // VPTESTMDZ256rr 384845994U, // VPTESTMDZ256rrk 2517649578U, // VPTESTMDZrm 2517649578U, // VPTESTMDZrmb 384845994U, // VPTESTMDZrmbk 384845994U, // VPTESTMDZrmk 2517649578U, // VPTESTMDZrr 384845994U, // VPTESTMDZrrk 2517653494U, // VPTESTMQZ128rm 2517653494U, // VPTESTMQZ128rmb 384849910U, // VPTESTMQZ128rmbk 384849910U, // VPTESTMQZ128rmk 2517653494U, // VPTESTMQZ128rr 384849910U, // VPTESTMQZ128rrk 2517653494U, // VPTESTMQZ256rm 2517653494U, // VPTESTMQZ256rmb 384849910U, // VPTESTMQZ256rmbk 384849910U, // VPTESTMQZ256rmk 2517653494U, // VPTESTMQZ256rr 384849910U, // VPTESTMQZ256rrk 2517653494U, // VPTESTMQZrm 2517653494U, // VPTESTMQZrmb 384849910U, // VPTESTMQZrmbk 384849910U, // VPTESTMQZrmk 2517653494U, // VPTESTMQZrr 384849910U, // VPTESTMQZrrk 2517656825U, // VPTESTMWZ128rm 384853241U, // VPTESTMWZ128rmk 2517656825U, // VPTESTMWZ128rr 384853241U, // VPTESTMWZ128rrk 2517656825U, // VPTESTMWZ256rm 384853241U, // VPTESTMWZ256rmk 2517656825U, // VPTESTMWZ256rr 384853241U, // VPTESTMWZ256rrk 2517656825U, // VPTESTMWZrm 384853241U, // VPTESTMWZrmk 2517656825U, // VPTESTMWZrr 384853241U, // VPTESTMWZrrk 2517648496U, // VPTESTNMBZ128rm 384844912U, // VPTESTNMBZ128rmk 2517648496U, // VPTESTNMBZ128rr 384844912U, // VPTESTNMBZ128rrk 2517648496U, // VPTESTNMBZ256rm 384844912U, // VPTESTNMBZ256rmk 2517648496U, // VPTESTNMBZ256rr 384844912U, // VPTESTNMBZ256rrk 2517648496U, // VPTESTNMBZrm 384844912U, // VPTESTNMBZrmk 2517648496U, // VPTESTNMBZrr 384844912U, // VPTESTNMBZrrk 2517649551U, // VPTESTNMDZ128rm 2517649551U, // VPTESTNMDZ128rmb 384845967U, // VPTESTNMDZ128rmbk 384845967U, // VPTESTNMDZ128rmk 2517649551U, // VPTESTNMDZ128rr 384845967U, // VPTESTNMDZ128rrk 2517649551U, // VPTESTNMDZ256rm 2517649551U, // VPTESTNMDZ256rmb 384845967U, // VPTESTNMDZ256rmbk 384845967U, // VPTESTNMDZ256rmk 2517649551U, // VPTESTNMDZ256rr 384845967U, // VPTESTNMDZ256rrk 2517649551U, // VPTESTNMDZrm 2517649551U, // VPTESTNMDZrmb 384845967U, // VPTESTNMDZrmbk 384845967U, // VPTESTNMDZrmk 2517649551U, // VPTESTNMDZrr 384845967U, // VPTESTNMDZrrk 2517653467U, // VPTESTNMQZ128rm 2517653467U, // VPTESTNMQZ128rmb 384849883U, // VPTESTNMQZ128rmbk 384849883U, // VPTESTNMQZ128rmk 2517653467U, // VPTESTNMQZ128rr 384849883U, // VPTESTNMQZ128rrk 2517653467U, // VPTESTNMQZ256rm 2517653467U, // VPTESTNMQZ256rmb 384849883U, // VPTESTNMQZ256rmbk 384849883U, // VPTESTNMQZ256rmk 2517653467U, // VPTESTNMQZ256rr 384849883U, // VPTESTNMQZ256rrk 2517653467U, // VPTESTNMQZrm 2517653467U, // VPTESTNMQZrmb 384849883U, // VPTESTNMQZrmbk 384849883U, // VPTESTNMQZrmk 2517653467U, // VPTESTNMQZrr 384849883U, // VPTESTNMQZrrk 2517656798U, // VPTESTNMWZ128rm 384853214U, // VPTESTNMWZ128rmk 2517656798U, // VPTESTNMWZ128rr 384853214U, // VPTESTNMWZ128rrk 2517656798U, // VPTESTNMWZ256rm 384853214U, // VPTESTNMWZ256rmk 2517656798U, // VPTESTNMWZ256rr 384853214U, // VPTESTNMWZ256rrk 2517656798U, // VPTESTNMWZrm 384853214U, // VPTESTNMWZrmk 2517656798U, // VPTESTNMWZrr 384853214U, // VPTESTNMWZrrk 1041261209U, // VPTESTYrm 370172569U, // VPTESTYrr 672162457U, // VPTESTrm 370172569U, // VPTESTrr 2517656453U, // VPUNPCKHBWYrm 2517656453U, // VPUNPCKHBWYrr 2517656453U, // VPUNPCKHBWZ128rm 49308549U, // VPUNPCKHBWZ128rmk 2532336517U, // VPUNPCKHBWZ128rmkz 2517656453U, // VPUNPCKHBWZ128rr 49308549U, // VPUNPCKHBWZ128rrk 2532336517U, // VPUNPCKHBWZ128rrkz 2517656453U, // VPUNPCKHBWZ256rm 49308549U, // VPUNPCKHBWZ256rmk 2532336517U, // VPUNPCKHBWZ256rmkz 2517656453U, // VPUNPCKHBWZ256rr 49308549U, // VPUNPCKHBWZ256rrk 2532336517U, // VPUNPCKHBWZ256rrkz 2517656453U, // VPUNPCKHBWZrm 49308549U, // VPUNPCKHBWZrmk 2532336517U, // VPUNPCKHBWZrmkz 2517656453U, // VPUNPCKHBWZrr 49308549U, // VPUNPCKHBWZrrk 2532336517U, // VPUNPCKHBWZrrkz 2517656453U, // VPUNPCKHBWrm 2517656453U, // VPUNPCKHBWrr 2517653106U, // VPUNPCKHDQYrm 2517653106U, // VPUNPCKHDQYrr 2517653106U, // VPUNPCKHDQZ128rm 2517653106U, // VPUNPCKHDQZ128rmb 49305202U, // VPUNPCKHDQZ128rmbk 2532333170U, // VPUNPCKHDQZ128rmbkz 49305202U, // VPUNPCKHDQZ128rmk 2532333170U, // VPUNPCKHDQZ128rmkz 2517653106U, // VPUNPCKHDQZ128rr 49305202U, // VPUNPCKHDQZ128rrk 2532333170U, // VPUNPCKHDQZ128rrkz 2517653106U, // VPUNPCKHDQZ256rm 2517653106U, // VPUNPCKHDQZ256rmb 49305202U, // VPUNPCKHDQZ256rmbk 2532333170U, // VPUNPCKHDQZ256rmbkz 49305202U, // VPUNPCKHDQZ256rmk 2532333170U, // VPUNPCKHDQZ256rmkz 2517653106U, // VPUNPCKHDQZ256rr 49305202U, // VPUNPCKHDQZ256rrk 2532333170U, // VPUNPCKHDQZ256rrkz 2517653106U, // VPUNPCKHDQZrm 2517653106U, // VPUNPCKHDQZrmb 49305202U, // VPUNPCKHDQZrmbk 2532333170U, // VPUNPCKHDQZrmbkz 49305202U, // VPUNPCKHDQZrmk 2532333170U, // VPUNPCKHDQZrmkz 2517653106U, // VPUNPCKHDQZrr 49305202U, // VPUNPCKHDQZrrk 2532333170U, // VPUNPCKHDQZrrkz 2517653106U, // VPUNPCKHDQrm 2517653106U, // VPUNPCKHDQrr 2517653202U, // VPUNPCKHQDQYrm 2517653202U, // VPUNPCKHQDQYrr 2517653202U, // VPUNPCKHQDQZ128rm 2517653202U, // VPUNPCKHQDQZ128rmb 49305298U, // VPUNPCKHQDQZ128rmbk 2532333266U, // VPUNPCKHQDQZ128rmbkz 49305298U, // VPUNPCKHQDQZ128rmk 2532333266U, // VPUNPCKHQDQZ128rmkz 2517653202U, // VPUNPCKHQDQZ128rr 49305298U, // VPUNPCKHQDQZ128rrk 2532333266U, // VPUNPCKHQDQZ128rrkz 2517653202U, // VPUNPCKHQDQZ256rm 2517653202U, // VPUNPCKHQDQZ256rmb 49305298U, // VPUNPCKHQDQZ256rmbk 2532333266U, // VPUNPCKHQDQZ256rmbkz 49305298U, // VPUNPCKHQDQZ256rmk 2532333266U, // VPUNPCKHQDQZ256rmkz 2517653202U, // VPUNPCKHQDQZ256rr 49305298U, // VPUNPCKHQDQZ256rrk 2532333266U, // VPUNPCKHQDQZ256rrkz 2517653202U, // VPUNPCKHQDQZrm 2517653202U, // VPUNPCKHQDQZrmb 49305298U, // VPUNPCKHQDQZrmbk 2532333266U, // VPUNPCKHQDQZrmbkz 49305298U, // VPUNPCKHQDQZrmk 2532333266U, // VPUNPCKHQDQZrmkz 2517653202U, // VPUNPCKHQDQZrr 49305298U, // VPUNPCKHQDQZrrk 2532333266U, // VPUNPCKHQDQZrrkz 2517653202U, // VPUNPCKHQDQrm 2517653202U, // VPUNPCKHQDQrr 2517651622U, // VPUNPCKHWDYrm 2517651622U, // VPUNPCKHWDYrr 2517651622U, // VPUNPCKHWDZ128rm 49303718U, // VPUNPCKHWDZ128rmk 2532331686U, // VPUNPCKHWDZ128rmkz 2517651622U, // VPUNPCKHWDZ128rr 49303718U, // VPUNPCKHWDZ128rrk 2532331686U, // VPUNPCKHWDZ128rrkz 2517651622U, // VPUNPCKHWDZ256rm 49303718U, // VPUNPCKHWDZ256rmk 2532331686U, // VPUNPCKHWDZ256rmkz 2517651622U, // VPUNPCKHWDZ256rr 49303718U, // VPUNPCKHWDZ256rrk 2532331686U, // VPUNPCKHWDZ256rrkz 2517651622U, // VPUNPCKHWDZrm 49303718U, // VPUNPCKHWDZrmk 2532331686U, // VPUNPCKHWDZrmkz 2517651622U, // VPUNPCKHWDZrr 49303718U, // VPUNPCKHWDZrrk 2532331686U, // VPUNPCKHWDZrrkz 2517651622U, // VPUNPCKHWDrm 2517651622U, // VPUNPCKHWDrr 2517656475U, // VPUNPCKLBWYrm 2517656475U, // VPUNPCKLBWYrr 2517656475U, // VPUNPCKLBWZ128rm 49308571U, // VPUNPCKLBWZ128rmk 2532336539U, // VPUNPCKLBWZ128rmkz 2517656475U, // VPUNPCKLBWZ128rr 49308571U, // VPUNPCKLBWZ128rrk 2532336539U, // VPUNPCKLBWZ128rrkz 2517656475U, // VPUNPCKLBWZ256rm 49308571U, // VPUNPCKLBWZ256rmk 2532336539U, // VPUNPCKLBWZ256rmkz 2517656475U, // VPUNPCKLBWZ256rr 49308571U, // VPUNPCKLBWZ256rrk 2532336539U, // VPUNPCKLBWZ256rrkz 2517656475U, // VPUNPCKLBWZrm 49308571U, // VPUNPCKLBWZrmk 2532336539U, // VPUNPCKLBWZrmkz 2517656475U, // VPUNPCKLBWZrr 49308571U, // VPUNPCKLBWZrrk 2532336539U, // VPUNPCKLBWZrrkz 2517656475U, // VPUNPCKLBWrm 2517656475U, // VPUNPCKLBWrr 2517653137U, // VPUNPCKLDQYrm 2517653137U, // VPUNPCKLDQYrr 2517653137U, // VPUNPCKLDQZ128rm 2517653137U, // VPUNPCKLDQZ128rmb 49305233U, // VPUNPCKLDQZ128rmbk 2532333201U, // VPUNPCKLDQZ128rmbkz 49305233U, // VPUNPCKLDQZ128rmk 2532333201U, // VPUNPCKLDQZ128rmkz 2517653137U, // VPUNPCKLDQZ128rr 49305233U, // VPUNPCKLDQZ128rrk 2532333201U, // VPUNPCKLDQZ128rrkz 2517653137U, // VPUNPCKLDQZ256rm 2517653137U, // VPUNPCKLDQZ256rmb 49305233U, // VPUNPCKLDQZ256rmbk 2532333201U, // VPUNPCKLDQZ256rmbkz 49305233U, // VPUNPCKLDQZ256rmk 2532333201U, // VPUNPCKLDQZ256rmkz 2517653137U, // VPUNPCKLDQZ256rr 49305233U, // VPUNPCKLDQZ256rrk 2532333201U, // VPUNPCKLDQZ256rrkz 2517653137U, // VPUNPCKLDQZrm 2517653137U, // VPUNPCKLDQZrmb 49305233U, // VPUNPCKLDQZrmbk 2532333201U, // VPUNPCKLDQZrmbkz 49305233U, // VPUNPCKLDQZrmk 2532333201U, // VPUNPCKLDQZrmkz 2517653137U, // VPUNPCKLDQZrr 49305233U, // VPUNPCKLDQZrrk 2532333201U, // VPUNPCKLDQZrrkz 2517653137U, // VPUNPCKLDQrm 2517653137U, // VPUNPCKLDQrr 2517653215U, // VPUNPCKLQDQYrm 2517653215U, // VPUNPCKLQDQYrr 2517653215U, // VPUNPCKLQDQZ128rm 2517653215U, // VPUNPCKLQDQZ128rmb 49305311U, // VPUNPCKLQDQZ128rmbk 2532333279U, // VPUNPCKLQDQZ128rmbkz 49305311U, // VPUNPCKLQDQZ128rmk 2532333279U, // VPUNPCKLQDQZ128rmkz 2517653215U, // VPUNPCKLQDQZ128rr 49305311U, // VPUNPCKLQDQZ128rrk 2532333279U, // VPUNPCKLQDQZ128rrkz 2517653215U, // VPUNPCKLQDQZ256rm 2517653215U, // VPUNPCKLQDQZ256rmb 49305311U, // VPUNPCKLQDQZ256rmbk 2532333279U, // VPUNPCKLQDQZ256rmbkz 49305311U, // VPUNPCKLQDQZ256rmk 2532333279U, // VPUNPCKLQDQZ256rmkz 2517653215U, // VPUNPCKLQDQZ256rr 49305311U, // VPUNPCKLQDQZ256rrk 2532333279U, // VPUNPCKLQDQZ256rrkz 2517653215U, // VPUNPCKLQDQZrm 2517653215U, // VPUNPCKLQDQZrmb 49305311U, // VPUNPCKLQDQZrmbk 2532333279U, // VPUNPCKLQDQZrmbkz 49305311U, // VPUNPCKLQDQZrmk 2532333279U, // VPUNPCKLQDQZrmkz 2517653215U, // VPUNPCKLQDQZrr 49305311U, // VPUNPCKLQDQZrrk 2532333279U, // VPUNPCKLQDQZrrkz 2517653215U, // VPUNPCKLQDQrm 2517653215U, // VPUNPCKLQDQrr 2517651644U, // VPUNPCKLWDYrm 2517651644U, // VPUNPCKLWDYrr 2517651644U, // VPUNPCKLWDZ128rm 49303740U, // VPUNPCKLWDZ128rmk 2532331708U, // VPUNPCKLWDZ128rmkz 2517651644U, // VPUNPCKLWDZ128rr 49303740U, // VPUNPCKLWDZ128rrk 2532331708U, // VPUNPCKLWDZ128rrkz 2517651644U, // VPUNPCKLWDZ256rm 49303740U, // VPUNPCKLWDZ256rmk 2532331708U, // VPUNPCKLWDZ256rmkz 2517651644U, // VPUNPCKLWDZ256rr 49303740U, // VPUNPCKLWDZ256rrk 2532331708U, // VPUNPCKLWDZ256rrkz 2517651644U, // VPUNPCKLWDZrm 49303740U, // VPUNPCKLWDZrmk 2532331708U, // VPUNPCKLWDZrmkz 2517651644U, // VPUNPCKLWDZrr 49303740U, // VPUNPCKLWDZrrk 2532331708U, // VPUNPCKLWDZrrkz 2517651644U, // VPUNPCKLWDrm 2517651644U, // VPUNPCKLWDrr 2517650745U, // VPXORDZ128rm 2517650745U, // VPXORDZ128rmb 49302841U, // VPXORDZ128rmbk 2532330809U, // VPXORDZ128rmbkz 49302841U, // VPXORDZ128rmk 2532330809U, // VPXORDZ128rmkz 2517650745U, // VPXORDZ128rr 49302841U, // VPXORDZ128rrk 2532330809U, // VPXORDZ128rrkz 2517650745U, // VPXORDZ256rm 2517650745U, // VPXORDZ256rmb 49302841U, // VPXORDZ256rmbk 2532330809U, // VPXORDZ256rmbkz 49302841U, // VPXORDZ256rmk 2532330809U, // VPXORDZ256rmkz 2517650745U, // VPXORDZ256rr 49302841U, // VPXORDZ256rrk 2532330809U, // VPXORDZ256rrkz 2517650745U, // VPXORDZrm 2517650745U, // VPXORDZrmb 49302841U, // VPXORDZrmbk 2532330809U, // VPXORDZrmbkz 49302841U, // VPXORDZrmk 2532330809U, // VPXORDZrmkz 2517650745U, // VPXORDZrr 49302841U, // VPXORDZrrk 2532330809U, // VPXORDZrrkz 2517653722U, // VPXORQZ128rm 2517653722U, // VPXORQZ128rmb 49305818U, // VPXORQZ128rmbk 2532333786U, // VPXORQZ128rmbkz 49305818U, // VPXORQZ128rmk 2532333786U, // VPXORQZ128rmkz 2517653722U, // VPXORQZ128rr 49305818U, // VPXORQZ128rrk 2532333786U, // VPXORQZ128rrkz 2517653722U, // VPXORQZ256rm 2517653722U, // VPXORQZ256rmb 49305818U, // VPXORQZ256rmbk 2532333786U, // VPXORQZ256rmbkz 49305818U, // VPXORQZ256rmk 2532333786U, // VPXORQZ256rmkz 2517653722U, // VPXORQZ256rr 49305818U, // VPXORQZ256rrk 2532333786U, // VPXORQZ256rrkz 2517653722U, // VPXORQZrm 2517653722U, // VPXORQZrmb 49305818U, // VPXORQZrmbk 2532333786U, // VPXORQZrmbkz 49305818U, // VPXORQZrmk 2532333786U, // VPXORQZrmkz 2517653722U, // VPXORQZrr 49305818U, // VPXORQZrrk 2532333786U, // VPXORQZrrkz 2517654229U, // VPXORYrm 2517654229U, // VPXORYrr 2517654229U, // VPXORrm 2517654229U, // VPXORrr 2517650262U, // VRANGEPDZ128rmbi 49302358U, // VRANGEPDZ128rmbik 2532330326U, // VRANGEPDZ128rmbikz 2517650262U, // VRANGEPDZ128rmi 49302358U, // VRANGEPDZ128rmik 2532330326U, // VRANGEPDZ128rmikz 2517650262U, // VRANGEPDZ128rri 49302358U, // VRANGEPDZ128rrik 2532330326U, // VRANGEPDZ128rrikz 2517650262U, // VRANGEPDZ256rmbi 49302358U, // VRANGEPDZ256rmbik 2532330326U, // VRANGEPDZ256rmbikz 2517650262U, // VRANGEPDZ256rmi 49302358U, // VRANGEPDZ256rmik 2532330326U, // VRANGEPDZ256rmikz 2517650262U, // VRANGEPDZ256rri 49302358U, // VRANGEPDZ256rrik 2532330326U, // VRANGEPDZ256rrikz 2517650262U, // VRANGEPDZrmbi 49302358U, // VRANGEPDZrmbik 2532330326U, // VRANGEPDZrmbikz 2517650262U, // VRANGEPDZrmi 49302358U, // VRANGEPDZrmik 2532330326U, // VRANGEPDZrmikz 2517650262U, // VRANGEPDZrri 2517650262U, // VRANGEPDZrrib 49302358U, // VRANGEPDZrribk 2532330326U, // VRANGEPDZrribkz 49302358U, // VRANGEPDZrrik 2532330326U, // VRANGEPDZrrikz 2517655061U, // VRANGEPSZ128rmbi 49307157U, // VRANGEPSZ128rmbik 2532335125U, // VRANGEPSZ128rmbikz 2517655061U, // VRANGEPSZ128rmi 49307157U, // VRANGEPSZ128rmik 2532335125U, // VRANGEPSZ128rmikz 2517655061U, // VRANGEPSZ128rri 49307157U, // VRANGEPSZ128rrik 2532335125U, // VRANGEPSZ128rrikz 2517655061U, // VRANGEPSZ256rmbi 49307157U, // VRANGEPSZ256rmbik 2532335125U, // VRANGEPSZ256rmbikz 2517655061U, // VRANGEPSZ256rmi 49307157U, // VRANGEPSZ256rmik 2532335125U, // VRANGEPSZ256rmikz 2517655061U, // VRANGEPSZ256rri 49307157U, // VRANGEPSZ256rrik 2532335125U, // VRANGEPSZ256rrikz 2517655061U, // VRANGEPSZrmbi 49307157U, // VRANGEPSZrmbik 2532335125U, // VRANGEPSZrmbikz 2517655061U, // VRANGEPSZrmi 49307157U, // VRANGEPSZrmik 2532335125U, // VRANGEPSZrmikz 2517655061U, // VRANGEPSZrri 2517655061U, // VRANGEPSZrrib 49307157U, // VRANGEPSZrribk 2532335125U, // VRANGEPSZrribkz 49307157U, // VRANGEPSZrrik 2532335125U, // VRANGEPSZrrikz 2517651108U, // VRANGESDZrmi 49303204U, // VRANGESDZrmik 2532331172U, // VRANGESDZrmikz 2517651108U, // VRANGESDZrri 2517651108U, // VRANGESDZrrib 49303204U, // VRANGESDZrribk 2532331172U, // VRANGESDZrribkz 49303204U, // VRANGESDZrrik 2532331172U, // VRANGESDZrrikz 2517655824U, // VRANGESSZrmi 49307920U, // VRANGESSZrmik 2532335888U, // VRANGESSZrmikz 2517655824U, // VRANGESSZrri 2517655824U, // VRANGESSZrrib 49307920U, // VRANGESSZrribk 2532335888U, // VRANGESSZrribkz 49307920U, // VRANGESSZrrik 2532335888U, // VRANGESSZrrikz 672156253U, // VRCP14PDZ128m 605047389U, // VRCP14PDZ128mb 49302109U, // VRCP14PDZ128mbk 2532330077U, // VRCP14PDZ128mbkz 49302109U, // VRCP14PDZ128mk 2532330077U, // VRCP14PDZ128mkz 370166365U, // VRCP14PDZ128r 49302109U, // VRCP14PDZ128rk 2532330077U, // VRCP14PDZ128rkz 1007700573U, // VRCP14PDZ256m 2752531037U, // VRCP14PDZ256mb 49302109U, // VRCP14PDZ256mbk 2532330077U, // VRCP14PDZ256mbkz 49302109U, // VRCP14PDZ256mk 2532330077U, // VRCP14PDZ256mkz 370166365U, // VRCP14PDZ256r 49302109U, // VRCP14PDZ256rk 2532330077U, // VRCP14PDZ256rkz 1108363869U, // VRCP14PDZm 605047389U, // VRCP14PDZmb 49302109U, // VRCP14PDZmbk 2532330077U, // VRCP14PDZmbkz 49302109U, // VRCP14PDZmk 2532330077U, // VRCP14PDZmkz 370166365U, // VRCP14PDZr 49302109U, // VRCP14PDZrk 2532330077U, // VRCP14PDZrkz 672161037U, // VRCP14PSZ128m 2786090253U, // VRCP14PSZ128mb 49306893U, // VRCP14PSZ128mbk 2532334861U, // VRCP14PSZ128mbkz 49306893U, // VRCP14PSZ128mk 2532334861U, // VRCP14PSZ128mkz 370171149U, // VRCP14PSZ128r 49306893U, // VRCP14PSZ128rk 2532334861U, // VRCP14PSZ128rkz 1007705357U, // VRCP14PSZ256m 638606605U, // VRCP14PSZ256mb 49306893U, // VRCP14PSZ256mbk 2532334861U, // VRCP14PSZ256mbkz 49306893U, // VRCP14PSZ256mk 2532334861U, // VRCP14PSZ256mkz 370171149U, // VRCP14PSZ256r 49306893U, // VRCP14PSZ256rk 2532334861U, // VRCP14PSZ256rkz 1108368653U, // VRCP14PSZm 2786090253U, // VRCP14PSZmb 49306893U, // VRCP14PSZmbk 2532334861U, // VRCP14PSZmbkz 49306893U, // VRCP14PSZmk 2532334861U, // VRCP14PSZmkz 370171149U, // VRCP14PSZr 49306893U, // VRCP14PSZrk 2532334861U, // VRCP14PSZrkz 2517650977U, // VRCP14SDZrm 49303073U, // VRCP14SDZrmk 2532331041U, // VRCP14SDZrmkz 2517650977U, // VRCP14SDZrr 49303073U, // VRCP14SDZrrk 2532331041U, // VRCP14SDZrrkz 2517655678U, // VRCP14SSZrm 49307774U, // VRCP14SSZrmk 2532335742U, // VRCP14SSZrmkz 2517655678U, // VRCP14SSZrr 49307774U, // VRCP14SSZrrk 2532335742U, // VRCP14SSZrrkz 1108363891U, // VRCP28PDZm 605047411U, // VRCP28PDZmb 49302131U, // VRCP28PDZmbk 2532330099U, // VRCP28PDZmbkz 49302131U, // VRCP28PDZmk 2532330099U, // VRCP28PDZmkz 370166387U, // VRCP28PDZr 2517650035U, // VRCP28PDZrb 49302131U, // VRCP28PDZrbk 2532330099U, // VRCP28PDZrbkz 49302131U, // VRCP28PDZrk 2532330099U, // VRCP28PDZrkz 1108368675U, // VRCP28PSZm 2786090275U, // VRCP28PSZmb 49306915U, // VRCP28PSZmbk 2532334883U, // VRCP28PSZmbkz 49306915U, // VRCP28PSZmk 2532334883U, // VRCP28PSZmkz 370171171U, // VRCP28PSZr 2517654819U, // VRCP28PSZrb 49306915U, // VRCP28PSZrbk 2532334883U, // VRCP28PSZrbkz 49306915U, // VRCP28PSZrk 2532334883U, // VRCP28PSZrkz 2517650999U, // VRCP28SDZm 49303095U, // VRCP28SDZmk 2532331063U, // VRCP28SDZmkz 2517650999U, // VRCP28SDZr 2517650999U, // VRCP28SDZrb 49303095U, // VRCP28SDZrbk 2532331063U, // VRCP28SDZrbkz 49303095U, // VRCP28SDZrk 2532331063U, // VRCP28SDZrkz 2517655700U, // VRCP28SSZm 49307796U, // VRCP28SSZmk 2532335764U, // VRCP28SSZmkz 2517655700U, // VRCP28SSZr 2517655700U, // VRCP28SSZrb 49307796U, // VRCP28SSZrbk 2532335764U, // VRCP28SSZrbkz 49307796U, // VRCP28SSZrk 2532335764U, // VRCP28SSZrkz 1007705804U, // VRCPPSYm 370171596U, // VRCPPSYr 672161484U, // VRCPPSm 370171596U, // VRCPPSr 2517655906U, // VRCPSSm 2517655906U, // VRCPSSm_Int 2517655906U, // VRCPSSr 2517655906U, // VRCPSSr_Int 2752531275U, // VREDUCEPDZ128rmbi 49302347U, // VREDUCEPDZ128rmbik 2532330315U, // VREDUCEPDZ128rmbikz 2819640139U, // VREDUCEPDZ128rmi 49302347U, // VREDUCEPDZ128rmik 2532330315U, // VREDUCEPDZ128rmikz 2517650251U, // VREDUCEPDZ128rri 49302347U, // VREDUCEPDZ128rrik 2532330315U, // VREDUCEPDZ128rrikz 605047627U, // VREDUCEPDZ256rmbi 49302347U, // VREDUCEPDZ256rmbik 2532330315U, // VREDUCEPDZ256rmbikz 3155184459U, // VREDUCEPDZ256rmi 49302347U, // VREDUCEPDZ256rmik 2532330315U, // VREDUCEPDZ256rmikz 2517650251U, // VREDUCEPDZ256rri 49302347U, // VREDUCEPDZ256rrik 2532330315U, // VREDUCEPDZ256rrikz 2752531275U, // VREDUCEPDZrmbi 49302347U, // VREDUCEPDZrmbik 2532330315U, // VREDUCEPDZrmbikz 3255847755U, // VREDUCEPDZrmi 49302347U, // VREDUCEPDZrmik 2532330315U, // VREDUCEPDZrmikz 2517650251U, // VREDUCEPDZrri 370166603U, // VREDUCEPDZrrib 49302347U, // VREDUCEPDZrribk 2532330315U, // VREDUCEPDZrribkz 49302347U, // VREDUCEPDZrrik 2532330315U, // VREDUCEPDZrrikz 638606858U, // VREDUCEPSZ128rmbi 49307146U, // VREDUCEPSZ128rmbik 2532335114U, // VREDUCEPSZ128rmbikz 2819644938U, // VREDUCEPSZ128rmi 49307146U, // VREDUCEPSZ128rmik 2532335114U, // VREDUCEPSZ128rmikz 2517655050U, // VREDUCEPSZ128rri 49307146U, // VREDUCEPSZ128rrik 2532335114U, // VREDUCEPSZ128rrikz 2786090506U, // VREDUCEPSZ256rmbi 49307146U, // VREDUCEPSZ256rmbik 2532335114U, // VREDUCEPSZ256rmbikz 3155189258U, // VREDUCEPSZ256rmi 49307146U, // VREDUCEPSZ256rmik 2532335114U, // VREDUCEPSZ256rmikz 2517655050U, // VREDUCEPSZ256rri 49307146U, // VREDUCEPSZ256rrik 2532335114U, // VREDUCEPSZ256rrikz 638606858U, // VREDUCEPSZrmbi 49307146U, // VREDUCEPSZrmbik 2532335114U, // VREDUCEPSZrmbikz 3255852554U, // VREDUCEPSZrmi 49307146U, // VREDUCEPSZrmik 2532335114U, // VREDUCEPSZrmikz 2517655050U, // VREDUCEPSZrri 370171402U, // VREDUCEPSZrrib 49307146U, // VREDUCEPSZrribk 2532335114U, // VREDUCEPSZrribkz 49307146U, // VREDUCEPSZrrik 2532335114U, // VREDUCEPSZrrikz 2517651097U, // VREDUCESDZrmi 49303193U, // VREDUCESDZrmik 2532331161U, // VREDUCESDZrmikz 2517651097U, // VREDUCESDZrri 2517651097U, // VREDUCESDZrrib 49303193U, // VREDUCESDZrribk 2532331161U, // VREDUCESDZrribkz 49303193U, // VREDUCESDZrrik 2532331161U, // VREDUCESDZrrikz 2517655813U, // VREDUCESSZrmi 49307909U, // VREDUCESSZrmik 2532335877U, // VREDUCESSZrmikz 2517655813U, // VREDUCESSZrri 2517655813U, // VREDUCESSZrrib 49307909U, // VREDUCESSZrribk 2532335877U, // VREDUCESSZrribkz 49307909U, // VREDUCESSZrrik 2532335877U, // VREDUCESSZrrikz 2752531296U, // VRNDSCALEPDZ128rmbi 49302368U, // VRNDSCALEPDZ128rmbik 2532330336U, // VRNDSCALEPDZ128rmbikz 2819640160U, // VRNDSCALEPDZ128rmi 49302368U, // VRNDSCALEPDZ128rmik 2532330336U, // VRNDSCALEPDZ128rmikz 2517650272U, // VRNDSCALEPDZ128rri 49302368U, // VRNDSCALEPDZ128rrik 2532330336U, // VRNDSCALEPDZ128rrikz 605047648U, // VRNDSCALEPDZ256rmbi 49302368U, // VRNDSCALEPDZ256rmbik 2532330336U, // VRNDSCALEPDZ256rmbikz 3155184480U, // VRNDSCALEPDZ256rmi 49302368U, // VRNDSCALEPDZ256rmik 2532330336U, // VRNDSCALEPDZ256rmikz 2517650272U, // VRNDSCALEPDZ256rri 49302368U, // VRNDSCALEPDZ256rrik 2532330336U, // VRNDSCALEPDZ256rrikz 2752531296U, // VRNDSCALEPDZrmbi 49302368U, // VRNDSCALEPDZrmbik 2532330336U, // VRNDSCALEPDZrmbikz 3255847776U, // VRNDSCALEPDZrmi 49302368U, // VRNDSCALEPDZrmik 2532330336U, // VRNDSCALEPDZrmikz 2517650272U, // VRNDSCALEPDZrri 370166624U, // VRNDSCALEPDZrrib 49302368U, // VRNDSCALEPDZrribk 2532330336U, // VRNDSCALEPDZrribkz 49302368U, // VRNDSCALEPDZrrik 2532330336U, // VRNDSCALEPDZrrikz 638606879U, // VRNDSCALEPSZ128rmbi 49307167U, // VRNDSCALEPSZ128rmbik 2532335135U, // VRNDSCALEPSZ128rmbikz 2819644959U, // VRNDSCALEPSZ128rmi 49307167U, // VRNDSCALEPSZ128rmik 2532335135U, // VRNDSCALEPSZ128rmikz 2517655071U, // VRNDSCALEPSZ128rri 49307167U, // VRNDSCALEPSZ128rrik 2532335135U, // VRNDSCALEPSZ128rrikz 2786090527U, // VRNDSCALEPSZ256rmbi 49307167U, // VRNDSCALEPSZ256rmbik 2532335135U, // VRNDSCALEPSZ256rmbikz 3155189279U, // VRNDSCALEPSZ256rmi 49307167U, // VRNDSCALEPSZ256rmik 2532335135U, // VRNDSCALEPSZ256rmikz 2517655071U, // VRNDSCALEPSZ256rri 49307167U, // VRNDSCALEPSZ256rrik 2532335135U, // VRNDSCALEPSZ256rrikz 638606879U, // VRNDSCALEPSZrmbi 49307167U, // VRNDSCALEPSZrmbik 2532335135U, // VRNDSCALEPSZrmbikz 3255852575U, // VRNDSCALEPSZrmi 49307167U, // VRNDSCALEPSZrmik 2532335135U, // VRNDSCALEPSZrmikz 2517655071U, // VRNDSCALEPSZrri 370171423U, // VRNDSCALEPSZrrib 49307167U, // VRNDSCALEPSZrribk 2532335135U, // VRNDSCALEPSZrribkz 49307167U, // VRNDSCALEPSZrrik 2532335135U, // VRNDSCALEPSZrrikz 2517651118U, // VRNDSCALESDZm 2517651118U, // VRNDSCALESDZm_Int 49303214U, // VRNDSCALESDZm_Intk 2532331182U, // VRNDSCALESDZm_Intkz 2517651118U, // VRNDSCALESDZr 2517651118U, // VRNDSCALESDZr_Int 49303214U, // VRNDSCALESDZr_Intk 2532331182U, // VRNDSCALESDZr_Intkz 2517651118U, // VRNDSCALESDZrb_Int 49303214U, // VRNDSCALESDZrb_Intk 2532331182U, // VRNDSCALESDZrb_Intkz 2517655834U, // VRNDSCALESSZm 2517655834U, // VRNDSCALESSZm_Int 49307930U, // VRNDSCALESSZm_Intk 2532335898U, // VRNDSCALESSZm_Intkz 2517655834U, // VRNDSCALESSZr 2517655834U, // VRNDSCALESSZr_Int 49307930U, // VRNDSCALESSZr_Intk 2532335898U, // VRNDSCALESSZr_Intkz 2517655834U, // VRNDSCALESSZrb_Int 49307930U, // VRNDSCALESSZrb_Intk 2532335898U, // VRNDSCALESSZrb_Intkz 3155184424U, // VROUNDPDYm 2517650216U, // VROUNDPDYr 2819640104U, // VROUNDPDm 2517650216U, // VROUNDPDr 3155189223U, // VROUNDPSYm 2517655015U, // VROUNDPSYr 2819644903U, // VROUNDPSm 2517655015U, // VROUNDPSr 2517651087U, // VROUNDSDm 2517651087U, // VROUNDSDm_Int 2517651087U, // VROUNDSDr 2517651087U, // VROUNDSDr_Int 2517655803U, // VROUNDSSm 2517655803U, // VROUNDSSm_Int 2517655803U, // VROUNDSSr 2517655803U, // VROUNDSSr_Int 672156263U, // VRSQRT14PDZ128m 605047399U, // VRSQRT14PDZ128mb 49302119U, // VRSQRT14PDZ128mbk 2532330087U, // VRSQRT14PDZ128mbkz 49302119U, // VRSQRT14PDZ128mk 2532330087U, // VRSQRT14PDZ128mkz 370166375U, // VRSQRT14PDZ128r 49302119U, // VRSQRT14PDZ128rk 2532330087U, // VRSQRT14PDZ128rkz 1007700583U, // VRSQRT14PDZ256m 2752531047U, // VRSQRT14PDZ256mb 49302119U, // VRSQRT14PDZ256mbk 2532330087U, // VRSQRT14PDZ256mbkz 49302119U, // VRSQRT14PDZ256mk 2532330087U, // VRSQRT14PDZ256mkz 370166375U, // VRSQRT14PDZ256r 49302119U, // VRSQRT14PDZ256rk 2532330087U, // VRSQRT14PDZ256rkz 1108363879U, // VRSQRT14PDZm 605047399U, // VRSQRT14PDZmb 49302119U, // VRSQRT14PDZmbk 2532330087U, // VRSQRT14PDZmbkz 49302119U, // VRSQRT14PDZmk 2532330087U, // VRSQRT14PDZmkz 370166375U, // VRSQRT14PDZr 49302119U, // VRSQRT14PDZrk 2532330087U, // VRSQRT14PDZrkz 672161047U, // VRSQRT14PSZ128m 2786090263U, // VRSQRT14PSZ128mb 49306903U, // VRSQRT14PSZ128mbk 2532334871U, // VRSQRT14PSZ128mbkz 49306903U, // VRSQRT14PSZ128mk 2532334871U, // VRSQRT14PSZ128mkz 370171159U, // VRSQRT14PSZ128r 49306903U, // VRSQRT14PSZ128rk 2532334871U, // VRSQRT14PSZ128rkz 1007705367U, // VRSQRT14PSZ256m 638606615U, // VRSQRT14PSZ256mb 49306903U, // VRSQRT14PSZ256mbk 2532334871U, // VRSQRT14PSZ256mbkz 49306903U, // VRSQRT14PSZ256mk 2532334871U, // VRSQRT14PSZ256mkz 370171159U, // VRSQRT14PSZ256r 49306903U, // VRSQRT14PSZ256rk 2532334871U, // VRSQRT14PSZ256rkz 1108368663U, // VRSQRT14PSZm 2786090263U, // VRSQRT14PSZmb 49306903U, // VRSQRT14PSZmbk 2532334871U, // VRSQRT14PSZmbkz 49306903U, // VRSQRT14PSZmk 2532334871U, // VRSQRT14PSZmkz 370171159U, // VRSQRT14PSZr 49306903U, // VRSQRT14PSZrk 2532334871U, // VRSQRT14PSZrkz 2517650987U, // VRSQRT14SDZrm 49303083U, // VRSQRT14SDZrmk 2532331051U, // VRSQRT14SDZrmkz 2517650987U, // VRSQRT14SDZrr 49303083U, // VRSQRT14SDZrrk 2532331051U, // VRSQRT14SDZrrkz 2517655688U, // VRSQRT14SSZrm 49307784U, // VRSQRT14SSZrmk 2532335752U, // VRSQRT14SSZrmkz 2517655688U, // VRSQRT14SSZrr 49307784U, // VRSQRT14SSZrrk 2532335752U, // VRSQRT14SSZrrkz 1108363901U, // VRSQRT28PDZm 605047421U, // VRSQRT28PDZmb 49302141U, // VRSQRT28PDZmbk 2532330109U, // VRSQRT28PDZmbkz 49302141U, // VRSQRT28PDZmk 2532330109U, // VRSQRT28PDZmkz 370166397U, // VRSQRT28PDZr 2517650045U, // VRSQRT28PDZrb 49302141U, // VRSQRT28PDZrbk 2532330109U, // VRSQRT28PDZrbkz 49302141U, // VRSQRT28PDZrk 2532330109U, // VRSQRT28PDZrkz 1108368685U, // VRSQRT28PSZm 2786090285U, // VRSQRT28PSZmb 49306925U, // VRSQRT28PSZmbk 2532334893U, // VRSQRT28PSZmbkz 49306925U, // VRSQRT28PSZmk 2532334893U, // VRSQRT28PSZmkz 370171181U, // VRSQRT28PSZr 2517654829U, // VRSQRT28PSZrb 49306925U, // VRSQRT28PSZrbk 2532334893U, // VRSQRT28PSZrbkz 49306925U, // VRSQRT28PSZrk 2532334893U, // VRSQRT28PSZrkz 2517651009U, // VRSQRT28SDZm 49303105U, // VRSQRT28SDZmk 2532331073U, // VRSQRT28SDZmkz 2517651009U, // VRSQRT28SDZr 2517651009U, // VRSQRT28SDZrb 49303105U, // VRSQRT28SDZrbk 2532331073U, // VRSQRT28SDZrbkz 49303105U, // VRSQRT28SDZrk 2532331073U, // VRSQRT28SDZrkz 2517655710U, // VRSQRT28SSZm 49307806U, // VRSQRT28SSZmk 2532335774U, // VRSQRT28SSZmkz 2517655710U, // VRSQRT28SSZr 2517655710U, // VRSQRT28SSZrb 49307806U, // VRSQRT28SSZrbk 2532335774U, // VRSQRT28SSZrbkz 49307806U, // VRSQRT28SSZrk 2532335774U, // VRSQRT28SSZrkz 1007705948U, // VRSQRTPSYm 370171740U, // VRSQRTPSYr 672161628U, // VRSQRTPSm 370171740U, // VRSQRTPSr 2517655966U, // VRSQRTSSm 2517655966U, // VRSQRTSSm_Int 2517655966U, // VRSQRTSSr 2517655966U, // VRSQRTSSr_Int 2517650285U, // VSCALEFPDZ128rm 2517650285U, // VSCALEFPDZ128rmb 49302381U, // VSCALEFPDZ128rmbk 2532330349U, // VSCALEFPDZ128rmbkz 49302381U, // VSCALEFPDZ128rmk 2532330349U, // VSCALEFPDZ128rmkz 2517650285U, // VSCALEFPDZ128rr 49302381U, // VSCALEFPDZ128rrk 2532330349U, // VSCALEFPDZ128rrkz 2517650285U, // VSCALEFPDZ256rm 2517650285U, // VSCALEFPDZ256rmb 49302381U, // VSCALEFPDZ256rmbk 2532330349U, // VSCALEFPDZ256rmbkz 49302381U, // VSCALEFPDZ256rmk 2532330349U, // VSCALEFPDZ256rmkz 2517650285U, // VSCALEFPDZ256rr 49302381U, // VSCALEFPDZ256rrk 2532330349U, // VSCALEFPDZ256rrkz 2517650285U, // VSCALEFPDZrm 2517650285U, // VSCALEFPDZrmb 49302381U, // VSCALEFPDZrmbk 2532330349U, // VSCALEFPDZrmbkz 49302381U, // VSCALEFPDZrmk 2532330349U, // VSCALEFPDZrmkz 2517650285U, // VSCALEFPDZrr 2517650285U, // VSCALEFPDZrrb 49302381U, // VSCALEFPDZrrbk 2532330349U, // VSCALEFPDZrrbkz 49302381U, // VSCALEFPDZrrk 2532330349U, // VSCALEFPDZrrkz 2517655084U, // VSCALEFPSZ128rm 2517655084U, // VSCALEFPSZ128rmb 49307180U, // VSCALEFPSZ128rmbk 2532335148U, // VSCALEFPSZ128rmbkz 49307180U, // VSCALEFPSZ128rmk 2532335148U, // VSCALEFPSZ128rmkz 2517655084U, // VSCALEFPSZ128rr 49307180U, // VSCALEFPSZ128rrk 2532335148U, // VSCALEFPSZ128rrkz 2517655084U, // VSCALEFPSZ256rm 2517655084U, // VSCALEFPSZ256rmb 49307180U, // VSCALEFPSZ256rmbk 2532335148U, // VSCALEFPSZ256rmbkz 49307180U, // VSCALEFPSZ256rmk 2532335148U, // VSCALEFPSZ256rmkz 2517655084U, // VSCALEFPSZ256rr 49307180U, // VSCALEFPSZ256rrk 2532335148U, // VSCALEFPSZ256rrkz 2517655084U, // VSCALEFPSZrm 2517655084U, // VSCALEFPSZrmb 49307180U, // VSCALEFPSZrmbk 2532335148U, // VSCALEFPSZrmbkz 49307180U, // VSCALEFPSZrmk 2532335148U, // VSCALEFPSZrmkz 2517655084U, // VSCALEFPSZrr 2517655084U, // VSCALEFPSZrrb 49307180U, // VSCALEFPSZrrbk 2532335148U, // VSCALEFPSZrrbkz 49307180U, // VSCALEFPSZrrk 2532335148U, // VSCALEFPSZrrkz 2517651131U, // VSCALEFSDZrm 49303227U, // VSCALEFSDZrmk 2532331195U, // VSCALEFSDZrmkz 2517651131U, // VSCALEFSDZrr 2517651131U, // VSCALEFSDZrrb_Int 49303227U, // VSCALEFSDZrrb_Intk 2532331195U, // VSCALEFSDZrrb_Intkz 49303227U, // VSCALEFSDZrrk 2532331195U, // VSCALEFSDZrrkz 2517655847U, // VSCALEFSSZrm 49307943U, // VSCALEFSSZrmk 2532335911U, // VSCALEFSSZrmkz 2517655847U, // VSCALEFSSZrr 2517655847U, // VSCALEFSSZrrb_Int 49307943U, // VSCALEFSSZrrb_Intk 2532335911U, // VSCALEFSSZrrb_Intkz 49307943U, // VSCALEFSSZrrk 2532335911U, // VSCALEFSSZrrkz 691006U, // VSCATTERDPDZ128mr 707390U, // VSCATTERDPDZ256mr 723774U, // VSCATTERDPDZmr 695805U, // VSCATTERDPSZ128mr 712189U, // VSCATTERDPSZ256mr 728573U, // VSCATTERDPSZmr 822112234U, // VSCATTERPF0DPDm 822112366U, // VSCATTERPF0DPSm 822112300U, // VSCATTERPF0QPDm 1056993456U, // VSCATTERPF0QPSm 822112267U, // VSCATTERPF1DPDm 822112399U, // VSCATTERPF1DPSm 822112333U, // VSCATTERPF1QPDm 1056993489U, // VSCATTERPF1QPSm 691239U, // VSCATTERQPDZ128mr 707623U, // VSCATTERQPDZ256mr 724007U, // VSCATTERQPDZmr 745210U, // VSCATTERQPSZ128mr 696058U, // VSCATTERQPSZ256mr 712442U, // VSCATTERQPSZmr 2517647773U, // VSHUFF32X4Z256rmbi 49299869U, // VSHUFF32X4Z256rmbik 2532327837U, // VSHUFF32X4Z256rmbikz 2517647773U, // VSHUFF32X4Z256rmi 49299869U, // VSHUFF32X4Z256rmik 2532327837U, // VSHUFF32X4Z256rmikz 2517647773U, // VSHUFF32X4Z256rri 49299869U, // VSHUFF32X4Z256rrik 2532327837U, // VSHUFF32X4Z256rrikz 2517647773U, // VSHUFF32X4Zrmbi 49299869U, // VSHUFF32X4Zrmbik 2532327837U, // VSHUFF32X4Zrmbikz 2517647773U, // VSHUFF32X4Zrmi 49299869U, // VSHUFF32X4Zrmik 2532327837U, // VSHUFF32X4Zrmikz 2517647773U, // VSHUFF32X4Zrri 49299869U, // VSHUFF32X4Zrrik 2532327837U, // VSHUFF32X4Zrrikz 2517647560U, // VSHUFF64X2Z256rmbi 49299656U, // VSHUFF64X2Z256rmbik 2532327624U, // VSHUFF64X2Z256rmbikz 2517647560U, // VSHUFF64X2Z256rmi 49299656U, // VSHUFF64X2Z256rmik 2532327624U, // VSHUFF64X2Z256rmikz 2517647560U, // VSHUFF64X2Z256rri 49299656U, // VSHUFF64X2Z256rrik 2532327624U, // VSHUFF64X2Z256rrikz 2517647560U, // VSHUFF64X2Zrmbi 49299656U, // VSHUFF64X2Zrmbik 2532327624U, // VSHUFF64X2Zrmbikz 2517647560U, // VSHUFF64X2Zrmi 49299656U, // VSHUFF64X2Zrmik 2532327624U, // VSHUFF64X2Zrmikz 2517647560U, // VSHUFF64X2Zrri 49299656U, // VSHUFF64X2Zrrik 2532327624U, // VSHUFF64X2Zrrikz 2517647831U, // VSHUFI32X4Z256rmbi 49299927U, // VSHUFI32X4Z256rmbik 2532327895U, // VSHUFI32X4Z256rmbikz 2517647831U, // VSHUFI32X4Z256rmi 49299927U, // VSHUFI32X4Z256rmik 2532327895U, // VSHUFI32X4Z256rmikz 2517647831U, // VSHUFI32X4Z256rri 49299927U, // VSHUFI32X4Z256rrik 2532327895U, // VSHUFI32X4Z256rrikz 2517647831U, // VSHUFI32X4Zrmbi 49299927U, // VSHUFI32X4Zrmbik 2532327895U, // VSHUFI32X4Zrmbikz 2517647831U, // VSHUFI32X4Zrmi 49299927U, // VSHUFI32X4Zrmik 2532327895U, // VSHUFI32X4Zrmikz 2517647831U, // VSHUFI32X4Zrri 49299927U, // VSHUFI32X4Zrrik 2532327895U, // VSHUFI32X4Zrrikz 2517647618U, // VSHUFI64X2Z256rmbi 49299714U, // VSHUFI64X2Z256rmbik 2532327682U, // VSHUFI64X2Z256rmbikz 2517647618U, // VSHUFI64X2Z256rmi 49299714U, // VSHUFI64X2Z256rmik 2532327682U, // VSHUFI64X2Z256rmikz 2517647618U, // VSHUFI64X2Z256rri 49299714U, // VSHUFI64X2Z256rrik 2532327682U, // VSHUFI64X2Z256rrikz 2517647618U, // VSHUFI64X2Zrmbi 49299714U, // VSHUFI64X2Zrmbik 2532327682U, // VSHUFI64X2Zrmbikz 2517647618U, // VSHUFI64X2Zrmi 49299714U, // VSHUFI64X2Zrmik 2532327682U, // VSHUFI64X2Zrmikz 2517647618U, // VSHUFI64X2Zrri 49299714U, // VSHUFI64X2Zrrik 2532327682U, // VSHUFI64X2Zrrikz 2517650296U, // VSHUFPDYrmi 2517650296U, // VSHUFPDYrri 2517650296U, // VSHUFPDZ128rmbi 49302392U, // VSHUFPDZ128rmbik 2532330360U, // VSHUFPDZ128rmbikz 2517650296U, // VSHUFPDZ128rmi 49302392U, // VSHUFPDZ128rmik 2532330360U, // VSHUFPDZ128rmikz 2517650296U, // VSHUFPDZ128rri 49302392U, // VSHUFPDZ128rrik 2532330360U, // VSHUFPDZ128rrikz 2517650296U, // VSHUFPDZ256rmbi 49302392U, // VSHUFPDZ256rmbik 2532330360U, // VSHUFPDZ256rmbikz 2517650296U, // VSHUFPDZ256rmi 49302392U, // VSHUFPDZ256rmik 2532330360U, // VSHUFPDZ256rmikz 2517650296U, // VSHUFPDZ256rri 49302392U, // VSHUFPDZ256rrik 2532330360U, // VSHUFPDZ256rrikz 2517650296U, // VSHUFPDZrmbi 49302392U, // VSHUFPDZrmbik 2532330360U, // VSHUFPDZrmbikz 2517650296U, // VSHUFPDZrmi 49302392U, // VSHUFPDZrmik 2532330360U, // VSHUFPDZrmikz 2517650296U, // VSHUFPDZrri 49302392U, // VSHUFPDZrrik 2532330360U, // VSHUFPDZrrikz 2517650296U, // VSHUFPDrmi 2517650296U, // VSHUFPDrri 2517655095U, // VSHUFPSYrmi 2517655095U, // VSHUFPSYrri 2517655095U, // VSHUFPSZ128rmbi 49307191U, // VSHUFPSZ128rmbik 2532335159U, // VSHUFPSZ128rmbikz 2517655095U, // VSHUFPSZ128rmi 49307191U, // VSHUFPSZ128rmik 2532335159U, // VSHUFPSZ128rmikz 2517655095U, // VSHUFPSZ128rri 49307191U, // VSHUFPSZ128rrik 2532335159U, // VSHUFPSZ128rrikz 2517655095U, // VSHUFPSZ256rmbi 49307191U, // VSHUFPSZ256rmbik 2532335159U, // VSHUFPSZ256rmbikz 2517655095U, // VSHUFPSZ256rmi 49307191U, // VSHUFPSZ256rmik 2532335159U, // VSHUFPSZ256rmikz 2517655095U, // VSHUFPSZ256rri 49307191U, // VSHUFPSZ256rrik 2532335159U, // VSHUFPSZ256rrikz 2517655095U, // VSHUFPSZrmbi 49307191U, // VSHUFPSZrmbik 2532335159U, // VSHUFPSZrmbikz 2517655095U, // VSHUFPSZrmi 49307191U, // VSHUFPSZrmik 2532335159U, // VSHUFPSZrmikz 2517655095U, // VSHUFPSZrri 49307191U, // VSHUFPSZrrik 2532335159U, // VSHUFPSZrrikz 2517655095U, // VSHUFPSrmi 2517655095U, // VSHUFPSrri 1007701123U, // VSQRTPDYm 370166915U, // VSQRTPDYr 672156803U, // VSQRTPDZ128m 605047939U, // VSQRTPDZ128mb 49302659U, // VSQRTPDZ128mbk 2532330627U, // VSQRTPDZ128mbkz 49302659U, // VSQRTPDZ128mk 2532330627U, // VSQRTPDZ128mkz 370166915U, // VSQRTPDZ128r 49302659U, // VSQRTPDZ128rk 2532330627U, // VSQRTPDZ128rkz 1007701123U, // VSQRTPDZ256m 2752531587U, // VSQRTPDZ256mb 49302659U, // VSQRTPDZ256mbk 2532330627U, // VSQRTPDZ256mbkz 49302659U, // VSQRTPDZ256mk 2532330627U, // VSQRTPDZ256mkz 370166915U, // VSQRTPDZ256r 49302659U, // VSQRTPDZ256rk 2532330627U, // VSQRTPDZ256rkz 1108364419U, // VSQRTPDZm 605047939U, // VSQRTPDZmb 49302659U, // VSQRTPDZmbk 2532330627U, // VSQRTPDZmbkz 49302659U, // VSQRTPDZmk 2532330627U, // VSQRTPDZmkz 370166915U, // VSQRTPDZr 2517650563U, // VSQRTPDZrb 49302659U, // VSQRTPDZrbk 2532330627U, // VSQRTPDZrbkz 49302659U, // VSQRTPDZrk 2532330627U, // VSQRTPDZrkz 672156803U, // VSQRTPDm 370166915U, // VSQRTPDr 1007705958U, // VSQRTPSYm 370171750U, // VSQRTPSYr 672161638U, // VSQRTPSZ128m 2786090854U, // VSQRTPSZ128mb 49307494U, // VSQRTPSZ128mbk 2532335462U, // VSQRTPSZ128mbkz 49307494U, // VSQRTPSZ128mk 2532335462U, // VSQRTPSZ128mkz 370171750U, // VSQRTPSZ128r 49307494U, // VSQRTPSZ128rk 2532335462U, // VSQRTPSZ128rkz 1007705958U, // VSQRTPSZ256m 638607206U, // VSQRTPSZ256mb 49307494U, // VSQRTPSZ256mbk 2532335462U, // VSQRTPSZ256mbkz 49307494U, // VSQRTPSZ256mk 2532335462U, // VSQRTPSZ256mkz 370171750U, // VSQRTPSZ256r 49307494U, // VSQRTPSZ256rk 2532335462U, // VSQRTPSZ256rkz 1108369254U, // VSQRTPSZm 2786090854U, // VSQRTPSZmb 49307494U, // VSQRTPSZmbk 2532335462U, // VSQRTPSZmbkz 49307494U, // VSQRTPSZmk 2532335462U, // VSQRTPSZmkz 370171750U, // VSQRTPSZr 2517655398U, // VSQRTPSZrb 49307494U, // VSQRTPSZrbk 2532335462U, // VSQRTPSZrbkz 49307494U, // VSQRTPSZrk 2532335462U, // VSQRTPSZrkz 672161638U, // VSQRTPSm 370171750U, // VSQRTPSr 2517651307U, // VSQRTSDZm 2517651307U, // VSQRTSDZm_Int 49303403U, // VSQRTSDZm_Intk 2532331371U, // VSQRTSDZm_Intkz 2517651307U, // VSQRTSDZr 2517651307U, // VSQRTSDZr_Int 49303403U, // VSQRTSDZr_Intk 2532331371U, // VSQRTSDZr_Intkz 2517651307U, // VSQRTSDZrb_Int 49303403U, // VSQRTSDZrb_Intk 2532331371U, // VSQRTSDZrb_Intkz 2517651307U, // VSQRTSDm 2517651307U, // VSQRTSDm_Int 2517651307U, // VSQRTSDr 2517651307U, // VSQRTSDr_Int 2517655976U, // VSQRTSSZm 2517655976U, // VSQRTSSZm_Int 49308072U, // VSQRTSSZm_Intk 2532336040U, // VSQRTSSZm_Intkz 2517655976U, // VSQRTSSZr 2517655976U, // VSQRTSSZr_Int 49308072U, // VSQRTSSZr_Intk 2532336040U, // VSQRTSSZr_Intkz 2517655976U, // VSQRTSSZrb_Int 49308072U, // VSQRTSSZrb_Intk 2532336040U, // VSQRTSSZrb_Intkz 2517655976U, // VSQRTSSm 2517655976U, // VSQRTSSm_Int 2517655976U, // VSQRTSSr 2517655976U, // VSQRTSSr_Int 72433U, // VSTMXCSR 2517650128U, // VSUBPDYrm 2517650128U, // VSUBPDYrr 2517650128U, // VSUBPDZ128rm 2517650128U, // VSUBPDZ128rmb 49302224U, // VSUBPDZ128rmbk 2532330192U, // VSUBPDZ128rmbkz 49302224U, // VSUBPDZ128rmk 2532330192U, // VSUBPDZ128rmkz 2517650128U, // VSUBPDZ128rr 49302224U, // VSUBPDZ128rrk 2532330192U, // VSUBPDZ128rrkz 2517650128U, // VSUBPDZ256rm 2517650128U, // VSUBPDZ256rmb 49302224U, // VSUBPDZ256rmbk 2532330192U, // VSUBPDZ256rmbkz 49302224U, // VSUBPDZ256rmk 2532330192U, // VSUBPDZ256rmkz 2517650128U, // VSUBPDZ256rr 49302224U, // VSUBPDZ256rrk 2532330192U, // VSUBPDZ256rrkz 2517650128U, // VSUBPDZrm 2517650128U, // VSUBPDZrmb 49302224U, // VSUBPDZrmbk 2532330192U, // VSUBPDZrmbkz 49302224U, // VSUBPDZrmk 2532330192U, // VSUBPDZrmkz 2517650128U, // VSUBPDZrr 2517650128U, // VSUBPDZrrb 49302224U, // VSUBPDZrrbk 2532330192U, // VSUBPDZrrbkz 49302224U, // VSUBPDZrrk 2532330192U, // VSUBPDZrrkz 2517650128U, // VSUBPDrm 2517650128U, // VSUBPDrr 2517654904U, // VSUBPSYrm 2517654904U, // VSUBPSYrr 2517654904U, // VSUBPSZ128rm 2517654904U, // VSUBPSZ128rmb 49307000U, // VSUBPSZ128rmbk 2532334968U, // VSUBPSZ128rmbkz 49307000U, // VSUBPSZ128rmk 2532334968U, // VSUBPSZ128rmkz 2517654904U, // VSUBPSZ128rr 49307000U, // VSUBPSZ128rrk 2532334968U, // VSUBPSZ128rrkz 2517654904U, // VSUBPSZ256rm 2517654904U, // VSUBPSZ256rmb 49307000U, // VSUBPSZ256rmbk 2532334968U, // VSUBPSZ256rmbkz 49307000U, // VSUBPSZ256rmk 2532334968U, // VSUBPSZ256rmkz 2517654904U, // VSUBPSZ256rr 49307000U, // VSUBPSZ256rrk 2532334968U, // VSUBPSZ256rrkz 2517654904U, // VSUBPSZrm 2517654904U, // VSUBPSZrmb 49307000U, // VSUBPSZrmbk 2532334968U, // VSUBPSZrmbkz 49307000U, // VSUBPSZrmk 2532334968U, // VSUBPSZrmkz 2517654904U, // VSUBPSZrr 2517654904U, // VSUBPSZrrb 49307000U, // VSUBPSZrrbk 2532334968U, // VSUBPSZrrbkz 49307000U, // VSUBPSZrrk 2532334968U, // VSUBPSZrrkz 2517654904U, // VSUBPSrm 2517654904U, // VSUBPSrr 2517651050U, // VSUBSDZrm 2517651050U, // VSUBSDZrm_Int 49303146U, // VSUBSDZrm_Intk 2532331114U, // VSUBSDZrm_Intkz 2517651050U, // VSUBSDZrr 2517651050U, // VSUBSDZrr_Int 49303146U, // VSUBSDZrr_Intk 2532331114U, // VSUBSDZrr_Intkz 2517651050U, // VSUBSDZrrb_Int 49303146U, // VSUBSDZrrb_Intk 2532331114U, // VSUBSDZrrb_Intkz 2517651050U, // VSUBSDrm 2517651050U, // VSUBSDrm_Int 2517651050U, // VSUBSDrr 2517651050U, // VSUBSDrr_Int 2517655743U, // VSUBSSZrm 2517655743U, // VSUBSSZrm_Int 49307839U, // VSUBSSZrm_Intk 2532335807U, // VSUBSSZrm_Intkz 2517655743U, // VSUBSSZrr 2517655743U, // VSUBSSZrr_Int 49307839U, // VSUBSSZrr_Intk 2532335807U, // VSUBSSZrr_Intkz 2517655743U, // VSUBSSZrrb_Int 49307839U, // VSUBSSZrrb_Intk 2532335807U, // VSUBSSZrrb_Intkz 2517655743U, // VSUBSSrm 2517655743U, // VSUBSSrm_Int 2517655743U, // VSUBSSrr 2517655743U, // VSUBSSrr_Int 1007701132U, // VTESTPDYrm 370166924U, // VTESTPDYrr 672156812U, // VTESTPDrm 370166924U, // VTESTPDrr 1007705967U, // VTESTPSYrm 370171759U, // VTESTPSYrr 672161647U, // VTESTPSrm 370171759U, // VTESTPSrr 605048518U, // VUCOMISDZrm 605048518U, // VUCOMISDZrm_Int 370167494U, // VUCOMISDZrr 370167494U, // VUCOMISDZrr_Int 2517651142U, // VUCOMISDZrrb 605048518U, // VUCOMISDrm 605048518U, // VUCOMISDrm_Int 370167494U, // VUCOMISDrr 370167494U, // VUCOMISDrr_Int 638607666U, // VUCOMISSZrm 638607666U, // VUCOMISSZrm_Int 370172210U, // VUCOMISSZrr 370172210U, // VUCOMISSZrr_Int 2517655858U, // VUCOMISSZrrb 638607666U, // VUCOMISSrm 638607666U, // VUCOMISSrm_Int 370172210U, // VUCOMISSrr 370172210U, // VUCOMISSrr_Int 2517650305U, // VUNPCKHPDYrm 2517650305U, // VUNPCKHPDYrr 2517650305U, // VUNPCKHPDZ128rm 2517650305U, // VUNPCKHPDZ128rmb 49302401U, // VUNPCKHPDZ128rmbk 2532330369U, // VUNPCKHPDZ128rmbkz 49302401U, // VUNPCKHPDZ128rmk 2532330369U, // VUNPCKHPDZ128rmkz 2517650305U, // VUNPCKHPDZ128rr 49302401U, // VUNPCKHPDZ128rrk 2532330369U, // VUNPCKHPDZ128rrkz 2517650305U, // VUNPCKHPDZ256rm 2517650305U, // VUNPCKHPDZ256rmb 49302401U, // VUNPCKHPDZ256rmbk 2532330369U, // VUNPCKHPDZ256rmbkz 49302401U, // VUNPCKHPDZ256rmk 2532330369U, // VUNPCKHPDZ256rmkz 2517650305U, // VUNPCKHPDZ256rr 49302401U, // VUNPCKHPDZ256rrk 2532330369U, // VUNPCKHPDZ256rrkz 2517650305U, // VUNPCKHPDZrm 2517650305U, // VUNPCKHPDZrmb 49302401U, // VUNPCKHPDZrmbk 2532330369U, // VUNPCKHPDZrmbkz 49302401U, // VUNPCKHPDZrmk 2532330369U, // VUNPCKHPDZrmkz 2517650305U, // VUNPCKHPDZrr 49302401U, // VUNPCKHPDZrrk 2532330369U, // VUNPCKHPDZrrkz 2517650305U, // VUNPCKHPDrm 2517650305U, // VUNPCKHPDrr 2517655104U, // VUNPCKHPSYrm 2517655104U, // VUNPCKHPSYrr 2517655104U, // VUNPCKHPSZ128rm 2517655104U, // VUNPCKHPSZ128rmb 49307200U, // VUNPCKHPSZ128rmbk 2532335168U, // VUNPCKHPSZ128rmbkz 49307200U, // VUNPCKHPSZ128rmk 2532335168U, // VUNPCKHPSZ128rmkz 2517655104U, // VUNPCKHPSZ128rr 49307200U, // VUNPCKHPSZ128rrk 2532335168U, // VUNPCKHPSZ128rrkz 2517655104U, // VUNPCKHPSZ256rm 2517655104U, // VUNPCKHPSZ256rmb 49307200U, // VUNPCKHPSZ256rmbk 2532335168U, // VUNPCKHPSZ256rmbkz 49307200U, // VUNPCKHPSZ256rmk 2532335168U, // VUNPCKHPSZ256rmkz 2517655104U, // VUNPCKHPSZ256rr 49307200U, // VUNPCKHPSZ256rrk 2532335168U, // VUNPCKHPSZ256rrkz 2517655104U, // VUNPCKHPSZrm 2517655104U, // VUNPCKHPSZrmb 49307200U, // VUNPCKHPSZrmbk 2532335168U, // VUNPCKHPSZrmbkz 49307200U, // VUNPCKHPSZrmk 2532335168U, // VUNPCKHPSZrmkz 2517655104U, // VUNPCKHPSZrr 49307200U, // VUNPCKHPSZrrk 2532335168U, // VUNPCKHPSZrrkz 2517655104U, // VUNPCKHPSrm 2517655104U, // VUNPCKHPSrr 2517650347U, // VUNPCKLPDYrm 2517650347U, // VUNPCKLPDYrr 2517650347U, // VUNPCKLPDZ128rm 2517650347U, // VUNPCKLPDZ128rmb 49302443U, // VUNPCKLPDZ128rmbk 2532330411U, // VUNPCKLPDZ128rmbkz 49302443U, // VUNPCKLPDZ128rmk 2532330411U, // VUNPCKLPDZ128rmkz 2517650347U, // VUNPCKLPDZ128rr 49302443U, // VUNPCKLPDZ128rrk 2532330411U, // VUNPCKLPDZ128rrkz 2517650347U, // VUNPCKLPDZ256rm 2517650347U, // VUNPCKLPDZ256rmb 49302443U, // VUNPCKLPDZ256rmbk 2532330411U, // VUNPCKLPDZ256rmbkz 49302443U, // VUNPCKLPDZ256rmk 2532330411U, // VUNPCKLPDZ256rmkz 2517650347U, // VUNPCKLPDZ256rr 49302443U, // VUNPCKLPDZ256rrk 2532330411U, // VUNPCKLPDZ256rrkz 2517650347U, // VUNPCKLPDZrm 2517650347U, // VUNPCKLPDZrmb 49302443U, // VUNPCKLPDZrmbk 2532330411U, // VUNPCKLPDZrmbkz 49302443U, // VUNPCKLPDZrmk 2532330411U, // VUNPCKLPDZrmkz 2517650347U, // VUNPCKLPDZrr 49302443U, // VUNPCKLPDZrrk 2532330411U, // VUNPCKLPDZrrkz 2517650347U, // VUNPCKLPDrm 2517650347U, // VUNPCKLPDrr 2517655166U, // VUNPCKLPSYrm 2517655166U, // VUNPCKLPSYrr 2517655166U, // VUNPCKLPSZ128rm 2517655166U, // VUNPCKLPSZ128rmb 49307262U, // VUNPCKLPSZ128rmbk 2532335230U, // VUNPCKLPSZ128rmbkz 49307262U, // VUNPCKLPSZ128rmk 2532335230U, // VUNPCKLPSZ128rmkz 2517655166U, // VUNPCKLPSZ128rr 49307262U, // VUNPCKLPSZ128rrk 2532335230U, // VUNPCKLPSZ128rrkz 2517655166U, // VUNPCKLPSZ256rm 2517655166U, // VUNPCKLPSZ256rmb 49307262U, // VUNPCKLPSZ256rmbk 2532335230U, // VUNPCKLPSZ256rmbkz 49307262U, // VUNPCKLPSZ256rmk 2532335230U, // VUNPCKLPSZ256rmkz 2517655166U, // VUNPCKLPSZ256rr 49307262U, // VUNPCKLPSZ256rrk 2532335230U, // VUNPCKLPSZ256rrkz 2517655166U, // VUNPCKLPSZrm 2517655166U, // VUNPCKLPSZrmb 49307262U, // VUNPCKLPSZrmbk 2532335230U, // VUNPCKLPSZrmbkz 49307262U, // VUNPCKLPSZrmk 2532335230U, // VUNPCKLPSZrmkz 2517655166U, // VUNPCKLPSZrr 49307262U, // VUNPCKLPSZrrk 2532335230U, // VUNPCKLPSZrrkz 2517655166U, // VUNPCKLPSrm 2517655166U, // VUNPCKLPSrr 2517650491U, // VXORPDYrm 2517650491U, // VXORPDYrr 2517650491U, // VXORPDZ128rm 2517650491U, // VXORPDZ128rmb 49302587U, // VXORPDZ128rmbk 2532330555U, // VXORPDZ128rmbkz 49302587U, // VXORPDZ128rmk 2532330555U, // VXORPDZ128rmkz 2517650491U, // VXORPDZ128rr 49302587U, // VXORPDZ128rrk 2532330555U, // VXORPDZ128rrkz 2517650491U, // VXORPDZ256rm 2517650491U, // VXORPDZ256rmb 49302587U, // VXORPDZ256rmbk 2532330555U, // VXORPDZ256rmbkz 49302587U, // VXORPDZ256rmk 2532330555U, // VXORPDZ256rmkz 2517650491U, // VXORPDZ256rr 49302587U, // VXORPDZ256rrk 2532330555U, // VXORPDZ256rrkz 2517650491U, // VXORPDZrm 2517650491U, // VXORPDZrmb 49302587U, // VXORPDZrmbk 2532330555U, // VXORPDZrmbkz 49302587U, // VXORPDZrmk 2532330555U, // VXORPDZrmkz 2517650491U, // VXORPDZrr 49302587U, // VXORPDZrrk 2532330555U, // VXORPDZrrkz 2517650491U, // VXORPDrm 2517650491U, // VXORPDrr 2517655310U, // VXORPSYrm 2517655310U, // VXORPSYrr 2517655310U, // VXORPSZ128rm 2517655310U, // VXORPSZ128rmb 49307406U, // VXORPSZ128rmbk 2532335374U, // VXORPSZ128rmbkz 49307406U, // VXORPSZ128rmk 2532335374U, // VXORPSZ128rmkz 2517655310U, // VXORPSZ128rr 49307406U, // VXORPSZ128rrk 2532335374U, // VXORPSZ128rrkz 2517655310U, // VXORPSZ256rm 2517655310U, // VXORPSZ256rmb 49307406U, // VXORPSZ256rmbk 2532335374U, // VXORPSZ256rmbkz 49307406U, // VXORPSZ256rmk 2532335374U, // VXORPSZ256rmkz 2517655310U, // VXORPSZ256rr 49307406U, // VXORPSZ256rrk 2532335374U, // VXORPSZ256rrkz 2517655310U, // VXORPSZrm 2517655310U, // VXORPSZrmb 49307406U, // VXORPSZrmbk 2532335374U, // VXORPSZrmbkz 49307406U, // VXORPSZrmk 2532335374U, // VXORPSZrmkz 2517655310U, // VXORPSZrr 49307406U, // VXORPSZrrk 2532335374U, // VXORPSZrrkz 2517655310U, // VXORPSrm 2517655310U, // VXORPSrr 11490U, // VZEROALL 11712U, // VZEROUPPER 11928U, // WAIT 11233U, // WBINVD 11240U, // WBNOINVD 20919U, // WRFSBASE 20919U, // WRFSBASE64 20939U, // WRGSBASE 20939U, // WRGSBASE64 11746U, // WRMSR 11990U, // WRPKRUr 1117990U, // WRSSD 1136938U, // WRSSQ 1118009U, // WRUSSD 1136945U, // WRUSSQ 25198U, // XABORT 11313U, // XACQUIRE_PREFIX 755575U, // XADD16rm 771959U, // XADD16rr 788343U, // XADD32rm 771959U, // XADD32rr 804727U, // XADD64rm 771959U, // XADD64rr 821111U, // XADD8rm 771959U, // XADD8rr 185476U, // XBEGIN_2 185476U, // XBEGIN_4 9490996U, // XCHG16ar 758324U, // XCHG16rm 840244U, // XCHG16rr 10539572U, // XCHG32ar 791092U, // XCHG32rm 840244U, // XCHG32rr 11588148U, // XCHG64ar 807476U, // XCHG64rm 840244U, // XCHG64rr 823860U, // XCHG8rm 840244U, // XCHG8rr 21085U, // XCH_F 11142U, // XCRYPTCBC 11106U, // XCRYPTCFB 11752U, // XCRYPTCTR 11096U, // XCRYPTECB 11116U, // XCRYPTOFB 11218U, // XEND 11997U, // XGETBV 11126U, // XLAT 26771U, // XOR16i16 1088215U, // XOR16mi 1088215U, // XOR16mi8 1088215U, // XOR16mr 34659031U, // XOR16ri 34659031U, // XOR16ri8 68213463U, // XOR16rm 34659031U, // XOR16rr 34626263U, // XOR16rr_REV 26926U, // XOR32i32 1120983U, // XOR32mi 1120983U, // XOR32mi8 1120983U, // XOR32mr 34659031U, // XOR32ri 34659031U, // XOR32ri8 101767895U, // XOR32rm 34659031U, // XOR32rr 34626263U, // XOR32rr_REV 27054U, // XOR64i32 1137367U, // XOR64mi32 1137367U, // XOR64mi8 1137367U, // XOR64mr 34659031U, // XOR64ri32 34659031U, // XOR64ri8 135322327U, // XOR64rm 34659031U, // XOR64rr 34626263U, // XOR64rr_REV 26669U, // XOR8i8 1153751U, // XOR8mi 1153751U, // XOR8mi8 1153751U, // XOR8mr 34659031U, // XOR8ri 34659031U, // XOR8ri8 168876759U, // XOR8rm 34659031U, // XOR8rr 34626263U, // XOR8rr_REV 202394684U, // XORPDrm 34622524U, // XORPDrr 202399503U, // XORPSrm 34627343U, // XORPSrr 11329U, // XRELEASE_PREFIX 301773U, // XRSTOR 295260U, // XRSTOR64 303025U, // XRSTORS 295280U, // XRSTORS64 299539U, // XSAVE 295250U, // XSAVE64 296615U, // XSAVEC 295239U, // XSAVEC64 303704U, // XSAVEOPT 295291U, // XSAVEOPT64 301920U, // XSAVES 295270U, // XSAVES64 12004U, // XSETBV 10932U, // XSHA1 11025U, // XSHA256 11322U, // XSTORE 11966U, // XTEST }; static const uint32_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 0U, // PATCHABLE_FUNCTION_ENTER 0U, // PATCHABLE_RET 0U, // PATCHABLE_FUNCTION_EXIT 0U, // PATCHABLE_TAIL_CALL 0U, // PATCHABLE_EVENT_CALL 0U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 0U, // AVX1_SETALLONES 0U, // AVX2_SETALLONES 0U, // AVX512_128_SET0 0U, // AVX512_256_SET0 0U, // AVX512_512_SET0 0U, // AVX512_512_SETALLONES 0U, // AVX512_512_SEXT_MASK_32 0U, // AVX512_512_SEXT_MASK_64 0U, // AVX512_FsFLD0SD 0U, // AVX512_FsFLD0SS 0U, // AVX_SET0 0U, // KSET0D 0U, // KSET0Q 0U, // KSET0W 0U, // KSET1D 0U, // KSET1Q 0U, // KSET1W 0U, // MMX_SET0 0U, // V_SET0 0U, // V_SETALLONES 0U, // AAA 0U, // AAD8i8 0U, // AAM8i8 0U, // AAS 0U, // ABS_F 0U, // ABS_Fp32 0U, // ABS_Fp64 0U, // ABS_Fp80 0U, // ADC16i16 0U, // ADC16mi 0U, // ADC16mi8 0U, // ADC16mr 0U, // ADC16ri 0U, // ADC16ri8 0U, // ADC16rm 0U, // ADC16rr 0U, // ADC16rr_REV 0U, // ADC32i32 0U, // ADC32mi 0U, // ADC32mi8 0U, // ADC32mr 0U, // ADC32ri 0U, // ADC32ri8 0U, // ADC32rm 0U, // ADC32rr 0U, // ADC32rr_REV 0U, // ADC64i32 0U, // ADC64mi32 0U, // ADC64mi8 0U, // ADC64mr 0U, // ADC64ri32 0U, // ADC64ri8 0U, // ADC64rm 0U, // ADC64rr 0U, // ADC64rr_REV 0U, // ADC8i8 0U, // ADC8mi 0U, // ADC8mi8 0U, // ADC8mr 0U, // ADC8ri 0U, // ADC8ri8 0U, // ADC8rm 0U, // ADC8rr 0U, // ADC8rr_REV 0U, // ADCX32rm 0U, // ADCX32rr 0U, // ADCX64rm 0U, // ADCX64rr 0U, // ADD16i16 0U, // ADD16mi 0U, // ADD16mi8 0U, // ADD16mr 0U, // ADD16ri 0U, // ADD16ri8 0U, // ADD16rm 0U, // ADD16rr 0U, // ADD16rr_REV 0U, // ADD32i32 0U, // ADD32mi 0U, // ADD32mi8 0U, // ADD32mr 0U, // ADD32ri 0U, // ADD32ri8 0U, // ADD32rm 0U, // ADD32rr 0U, // ADD32rr_REV 0U, // ADD64i32 0U, // ADD64mi32 0U, // ADD64mi8 0U, // ADD64mr 0U, // ADD64ri32 0U, // ADD64ri8 0U, // ADD64rm 0U, // ADD64rr 0U, // ADD64rr_REV 0U, // ADD8i8 0U, // ADD8mi 0U, // ADD8mi8 0U, // ADD8mr 0U, // ADD8ri 0U, // ADD8ri8 0U, // ADD8rm 0U, // ADD8rr 0U, // ADD8rr_REV 0U, // ADDPDrm 0U, // ADDPDrr 0U, // ADDPSrm 0U, // ADDPSrr 0U, // ADDSDrm 0U, // ADDSDrm_Int 0U, // ADDSDrr 0U, // ADDSDrr_Int 0U, // ADDSSrm 0U, // ADDSSrm_Int 0U, // ADDSSrr 0U, // ADDSSrr_Int 0U, // ADDSUBPDrm 0U, // ADDSUBPDrr 0U, // ADDSUBPSrm 0U, // ADDSUBPSrr 0U, // ADD_F32m 0U, // ADD_F64m 0U, // ADD_FI16m 0U, // ADD_FI32m 0U, // ADD_FPrST0 0U, // ADD_FST0r 0U, // ADD_Fp32 0U, // ADD_Fp32m 0U, // ADD_Fp64 0U, // ADD_Fp64m 0U, // ADD_Fp64m32 0U, // ADD_Fp80 0U, // ADD_Fp80m32 0U, // ADD_Fp80m64 0U, // ADD_FpI16m32 0U, // ADD_FpI16m64 0U, // ADD_FpI16m80 0U, // ADD_FpI32m32 0U, // ADD_FpI32m64 0U, // ADD_FpI32m80 0U, // ADD_FrST0 0U, // ADOX32rm 0U, // ADOX32rr 0U, // ADOX64rm 0U, // ADOX64rr 0U, // AESDECLASTrm 0U, // AESDECLASTrr 0U, // AESDECrm 0U, // AESDECrr 0U, // AESENCLASTrm 0U, // AESENCLASTrr 0U, // AESENCrm 0U, // AESENCrr 0U, // AESIMCrm 0U, // AESIMCrr 0U, // AESKEYGENASSIST128rm 32U, // AESKEYGENASSIST128rr 0U, // AND16i16 0U, // AND16mi 0U, // AND16mi8 0U, // AND16mr 0U, // AND16ri 0U, // AND16ri8 0U, // AND16rm 0U, // AND16rr 0U, // AND16rr_REV 0U, // AND32i32 0U, // AND32mi 0U, // AND32mi8 0U, // AND32mr 0U, // AND32ri 0U, // AND32ri8 0U, // AND32rm 0U, // AND32rr 0U, // AND32rr_REV 0U, // AND64i32 0U, // AND64mi32 0U, // AND64mi8 0U, // AND64mr 0U, // AND64ri32 0U, // AND64ri8 0U, // AND64rm 0U, // AND64rr 0U, // AND64rr_REV 0U, // AND8i8 0U, // AND8mi 0U, // AND8mi8 0U, // AND8mr 0U, // AND8ri 0U, // AND8ri8 0U, // AND8rm 0U, // AND8rr 0U, // AND8rr_REV 64U, // ANDN32rm 96U, // ANDN32rr 128U, // ANDN64rm 96U, // ANDN64rr 0U, // ANDNPDrm 0U, // ANDNPDrr 0U, // ANDNPSrm 0U, // ANDNPSrr 0U, // ANDPDrm 0U, // ANDPDrr 0U, // ANDPSrm 0U, // ANDPSrr 0U, // ARPL16mr 0U, // ARPL16rr 160U, // BEXTR32rm 96U, // BEXTR32rr 160U, // BEXTR64rm 96U, // BEXTR64rr 160U, // BEXTRI32mi 96U, // BEXTRI32ri 160U, // BEXTRI64mi 96U, // BEXTRI64ri 0U, // BLCFILL32rm 0U, // BLCFILL32rr 0U, // BLCFILL64rm 0U, // BLCFILL64rr 0U, // BLCI32rm 0U, // BLCI32rr 0U, // BLCI64rm 0U, // BLCI64rr 0U, // BLCIC32rm 0U, // BLCIC32rr 0U, // BLCIC64rm 0U, // BLCIC64rr 0U, // BLCMSK32rm 0U, // BLCMSK32rr 0U, // BLCMSK64rm 0U, // BLCMSK64rr 0U, // BLCS32rm 0U, // BLCS32rr 0U, // BLCS64rm 0U, // BLCS64rr 192U, // BLENDPDrmi 224U, // BLENDPDrri 192U, // BLENDPSrmi 224U, // BLENDPSrri 1U, // BLENDVPDrm0 1U, // BLENDVPDrr0 1U, // BLENDVPSrm0 1U, // BLENDVPSrr0 0U, // BLSFILL32rm 0U, // BLSFILL32rr 0U, // BLSFILL64rm 0U, // BLSFILL64rr 0U, // BLSI32rm 0U, // BLSI32rr 0U, // BLSI64rm 0U, // BLSI64rr 0U, // BLSIC32rm 0U, // BLSIC32rr 0U, // BLSIC64rm 0U, // BLSIC64rr 0U, // BLSMSK32rm 0U, // BLSMSK32rr 0U, // BLSMSK64rm 0U, // BLSMSK64rr 0U, // BLSR32rm 0U, // BLSR32rr 0U, // BLSR64rm 0U, // BLSR64rr 0U, // BNDCL32rm 0U, // BNDCL32rr 0U, // BNDCL64rm 0U, // BNDCL64rr 0U, // BNDCN32rm 0U, // BNDCN32rr 0U, // BNDCN64rm 0U, // BNDCN64rr 0U, // BNDCU32rm 0U, // BNDCU32rr 0U, // BNDCU64rm 0U, // BNDCU64rr 0U, // BNDLDXrm 0U, // BNDMK32rm 0U, // BNDMK64rm 0U, // BNDMOV32mr 0U, // BNDMOV32rm 0U, // BNDMOV64mr 0U, // BNDMOV64rm 0U, // BNDMOVrr 0U, // BNDMOVrr_REV 0U, // BNDSTXmr 0U, // BOUNDS16rm 0U, // BOUNDS32rm 0U, // BSF16rm 0U, // BSF16rr 0U, // BSF32rm 0U, // BSF32rr 0U, // BSF64rm 0U, // BSF64rr 0U, // BSR16rm 0U, // BSR16rr 0U, // BSR32rm 0U, // BSR32rr 0U, // BSR64rm 0U, // BSR64rr 0U, // BSWAP16r_BAD 0U, // BSWAP32r 0U, // BSWAP64r 0U, // BT16mi8 0U, // BT16mr 0U, // BT16ri8 0U, // BT16rr 0U, // BT32mi8 0U, // BT32mr 0U, // BT32ri8 0U, // BT32rr 0U, // BT64mi8 0U, // BT64mr 0U, // BT64ri8 0U, // BT64rr 0U, // BTC16mi8 0U, // BTC16mr 0U, // BTC16ri8 0U, // BTC16rr 0U, // BTC32mi8 0U, // BTC32mr 0U, // BTC32ri8 0U, // BTC32rr 0U, // BTC64mi8 0U, // BTC64mr 0U, // BTC64ri8 0U, // BTC64rr 0U, // BTR16mi8 0U, // BTR16mr 0U, // BTR16ri8 0U, // BTR16rr 0U, // BTR32mi8 0U, // BTR32mr 0U, // BTR32ri8 0U, // BTR32rr 0U, // BTR64mi8 0U, // BTR64mr 0U, // BTR64ri8 0U, // BTR64rr 0U, // BTS16mi8 0U, // BTS16mr 0U, // BTS16ri8 0U, // BTS16rr 0U, // BTS32mi8 0U, // BTS32mr 0U, // BTS32ri8 0U, // BTS32rr 0U, // BTS64mi8 0U, // BTS64mr 0U, // BTS64ri8 0U, // BTS64rr 160U, // BZHI32rm 96U, // BZHI32rr 160U, // BZHI64rm 96U, // BZHI64rr 0U, // CALL16m 0U, // CALL16m_NT 0U, // CALL16r 0U, // CALL16r_NT 0U, // CALL32m 0U, // CALL32m_NT 0U, // CALL32r 0U, // CALL32r_NT 0U, // CALL64m 0U, // CALL64m_NT 0U, // CALL64pcrel32 0U, // CALL64r 0U, // CALL64r_NT 0U, // CALLpcrel16 0U, // CALLpcrel32 0U, // CBW 0U, // CDQ 0U, // CDQE 0U, // CHS_F 0U, // CHS_Fp32 0U, // CHS_Fp64 0U, // CHS_Fp80 0U, // CLAC 0U, // CLC 0U, // CLD 0U, // CLDEMOTE 0U, // CLFLUSH 0U, // CLFLUSHOPT 0U, // CLGI 0U, // CLI 0U, // CLRSSBSY 0U, // CLTS 0U, // CLWB 0U, // CLZEROr 0U, // CMC 0U, // CMOVA16rm 0U, // CMOVA16rr 0U, // CMOVA32rm 0U, // CMOVA32rr 0U, // CMOVA64rm 0U, // CMOVA64rr 0U, // CMOVAE16rm 0U, // CMOVAE16rr 0U, // CMOVAE32rm 0U, // CMOVAE32rr 0U, // CMOVAE64rm 0U, // CMOVAE64rr 0U, // CMOVB16rm 0U, // CMOVB16rr 0U, // CMOVB32rm 0U, // CMOVB32rr 0U, // CMOVB64rm 0U, // CMOVB64rr 0U, // CMOVBE16rm 0U, // CMOVBE16rr 0U, // CMOVBE32rm 0U, // CMOVBE32rr 0U, // CMOVBE64rm 0U, // CMOVBE64rr 0U, // CMOVBE_F 0U, // CMOVBE_Fp32 0U, // CMOVBE_Fp64 0U, // CMOVBE_Fp80 0U, // CMOVB_F 0U, // CMOVB_Fp32 0U, // CMOVB_Fp64 0U, // CMOVB_Fp80 0U, // CMOVE16rm 0U, // CMOVE16rr 0U, // CMOVE32rm 0U, // CMOVE32rr 0U, // CMOVE64rm 0U, // CMOVE64rr 0U, // CMOVE_F 0U, // CMOVE_Fp32 0U, // CMOVE_Fp64 0U, // CMOVE_Fp80 0U, // CMOVG16rm 0U, // CMOVG16rr 0U, // CMOVG32rm 0U, // CMOVG32rr 0U, // CMOVG64rm 0U, // CMOVG64rr 0U, // CMOVGE16rm 0U, // CMOVGE16rr 0U, // CMOVGE32rm 0U, // CMOVGE32rr 0U, // CMOVGE64rm 0U, // CMOVGE64rr 0U, // CMOVL16rm 0U, // CMOVL16rr 0U, // CMOVL32rm 0U, // CMOVL32rr 0U, // CMOVL64rm 0U, // CMOVL64rr 0U, // CMOVLE16rm 0U, // CMOVLE16rr 0U, // CMOVLE32rm 0U, // CMOVLE32rr 0U, // CMOVLE64rm 0U, // CMOVLE64rr 0U, // CMOVNBE_F 0U, // CMOVNBE_Fp32 0U, // CMOVNBE_Fp64 0U, // CMOVNBE_Fp80 0U, // CMOVNB_F 0U, // CMOVNB_Fp32 0U, // CMOVNB_Fp64 0U, // CMOVNB_Fp80 0U, // CMOVNE16rm 0U, // CMOVNE16rr 0U, // CMOVNE32rm 0U, // CMOVNE32rr 0U, // CMOVNE64rm 0U, // CMOVNE64rr 0U, // CMOVNE_F 0U, // CMOVNE_Fp32 0U, // CMOVNE_Fp64 0U, // CMOVNE_Fp80 0U, // CMOVNO16rm 0U, // CMOVNO16rr 0U, // CMOVNO32rm 0U, // CMOVNO32rr 0U, // CMOVNO64rm 0U, // CMOVNO64rr 0U, // CMOVNP16rm 0U, // CMOVNP16rr 0U, // CMOVNP32rm 0U, // CMOVNP32rr 0U, // CMOVNP64rm 0U, // CMOVNP64rr 0U, // CMOVNP_F 0U, // CMOVNP_Fp32 0U, // CMOVNP_Fp64 0U, // CMOVNP_Fp80 0U, // CMOVNS16rm 0U, // CMOVNS16rr 0U, // CMOVNS32rm 0U, // CMOVNS32rr 0U, // CMOVNS64rm 0U, // CMOVNS64rr 0U, // CMOVO16rm 0U, // CMOVO16rr 0U, // CMOVO32rm 0U, // CMOVO32rr 0U, // CMOVO64rm 0U, // CMOVO64rr 0U, // CMOVP16rm 0U, // CMOVP16rr 0U, // CMOVP32rm 0U, // CMOVP32rr 0U, // CMOVP64rm 0U, // CMOVP64rr 0U, // CMOVP_F 0U, // CMOVP_Fp32 0U, // CMOVP_Fp64 0U, // CMOVP_Fp80 0U, // CMOVS16rm 0U, // CMOVS16rr 0U, // CMOVS32rm 0U, // CMOVS32rr 0U, // CMOVS64rm 0U, // CMOVS64rr 0U, // CMP16i16 0U, // CMP16mi 0U, // CMP16mi8 0U, // CMP16mr 0U, // CMP16ri 0U, // CMP16ri8 0U, // CMP16rm 0U, // CMP16rr 0U, // CMP16rr_REV 0U, // CMP32i32 0U, // CMP32mi 0U, // CMP32mi8 0U, // CMP32mr 0U, // CMP32ri 0U, // CMP32ri8 0U, // CMP32rm 0U, // CMP32rr 0U, // CMP32rr_REV 0U, // CMP64i32 0U, // CMP64mi32 0U, // CMP64mi8 0U, // CMP64mr 0U, // CMP64ri32 0U, // CMP64ri8 0U, // CMP64rm 0U, // CMP64rr 0U, // CMP64rr_REV 0U, // CMP8i8 0U, // CMP8mi 0U, // CMP8mi8 0U, // CMP8mr 0U, // CMP8ri 0U, // CMP8ri8 0U, // CMP8rm 0U, // CMP8rr 0U, // CMP8rr_REV 1U, // CMPPDrmi 192U, // CMPPDrmi_alt 2U, // CMPPDrri 224U, // CMPPDrri_alt 1U, // CMPPSrmi 192U, // CMPPSrmi_alt 2U, // CMPPSrri 224U, // CMPPSrri_alt 0U, // CMPSB 2U, // CMPSDrm 2U, // CMPSDrm_Int 192U, // CMPSDrm_alt 2U, // CMPSDrr 2U, // CMPSDrr_Int 224U, // CMPSDrr_alt 0U, // CMPSL 0U, // CMPSQ 3U, // CMPSSrm 3U, // CMPSSrm_Int 192U, // CMPSSrm_alt 2U, // CMPSSrr 2U, // CMPSSrr_Int 224U, // CMPSSrr_alt 0U, // CMPSW 0U, // CMPXCHG16B 0U, // CMPXCHG16rm 0U, // CMPXCHG16rr 0U, // CMPXCHG32rm 0U, // CMPXCHG32rr 0U, // CMPXCHG64rm 0U, // CMPXCHG64rr 0U, // CMPXCHG8B 0U, // CMPXCHG8rm 0U, // CMPXCHG8rr 0U, // COMISDrm 0U, // COMISDrm_Int 0U, // COMISDrr 0U, // COMISDrr_Int 0U, // COMISSrm 0U, // COMISSrm_Int 0U, // COMISSrr 0U, // COMISSrr_Int 0U, // COMP_FST0r 0U, // COM_FIPr 0U, // COM_FIr 0U, // COM_FST0r 0U, // COS_F 0U, // COS_Fp32 0U, // COS_Fp64 0U, // COS_Fp80 0U, // CPUID 0U, // CQO 0U, // CRC32r32m16 0U, // CRC32r32m32 0U, // CRC32r32m8 0U, // CRC32r32r16 0U, // CRC32r32r32 0U, // CRC32r32r8 0U, // CRC32r64m64 0U, // CRC32r64m8 0U, // CRC32r64r64 0U, // CRC32r64r8 0U, // CVTDQ2PDrm 0U, // CVTDQ2PDrr 0U, // CVTDQ2PSrm 0U, // CVTDQ2PSrr 0U, // CVTPD2DQrm 0U, // CVTPD2DQrr 0U, // CVTPD2PSrm 0U, // CVTPD2PSrr 0U, // CVTPS2DQrm 0U, // CVTPS2DQrr 0U, // CVTPS2PDrm 0U, // CVTPS2PDrr 0U, // CVTSD2SI64rm_Int 0U, // CVTSD2SI64rr_Int 0U, // CVTSD2SIrm_Int 0U, // CVTSD2SIrr_Int 0U, // CVTSD2SSrm 0U, // CVTSD2SSrm_Int 0U, // CVTSD2SSrr 0U, // CVTSD2SSrr_Int 0U, // CVTSI2SDrm 0U, // CVTSI2SDrm_Int 0U, // CVTSI2SDrr 0U, // CVTSI2SDrr_Int 0U, // CVTSI2SSrm 0U, // CVTSI2SSrm_Int 0U, // CVTSI2SSrr 0U, // CVTSI2SSrr_Int 0U, // CVTSI642SDrm 0U, // CVTSI642SDrm_Int 0U, // CVTSI642SDrr 0U, // CVTSI642SDrr_Int 0U, // CVTSI642SSrm 0U, // CVTSI642SSrm_Int 0U, // CVTSI642SSrr 0U, // CVTSI642SSrr_Int 0U, // CVTSS2SDrm 0U, // CVTSS2SDrm_Int 0U, // CVTSS2SDrr 0U, // CVTSS2SDrr_Int 0U, // CVTSS2SI64rm_Int 0U, // CVTSS2SI64rr_Int 0U, // CVTSS2SIrm_Int 0U, // CVTSS2SIrr_Int 0U, // CVTTPD2DQrm 0U, // CVTTPD2DQrr 0U, // CVTTPS2DQrm 0U, // CVTTPS2DQrr 0U, // CVTTSD2SI64rm 0U, // CVTTSD2SI64rm_Int 0U, // CVTTSD2SI64rr 0U, // CVTTSD2SI64rr_Int 0U, // CVTTSD2SIrm 0U, // CVTTSD2SIrm_Int 0U, // CVTTSD2SIrr 0U, // CVTTSD2SIrr_Int 0U, // CVTTSS2SI64rm 0U, // CVTTSS2SI64rm_Int 0U, // CVTTSS2SI64rr 0U, // CVTTSS2SI64rr_Int 0U, // CVTTSS2SIrm 0U, // CVTTSS2SIrm_Int 0U, // CVTTSS2SIrr 0U, // CVTTSS2SIrr_Int 0U, // CWD 0U, // CWDE 0U, // DAA 0U, // DAS 0U, // DATA16_PREFIX 0U, // DEC16m 0U, // DEC16r 0U, // DEC16r_alt 0U, // DEC32m 0U, // DEC32r 0U, // DEC32r_alt 0U, // DEC64m 0U, // DEC64r 0U, // DEC8m 0U, // DEC8r 0U, // DIV16m 0U, // DIV16r 0U, // DIV32m 0U, // DIV32r 0U, // DIV64m 0U, // DIV64r 0U, // DIV8m 0U, // DIV8r 0U, // DIVPDrm 0U, // DIVPDrr 0U, // DIVPSrm 0U, // DIVPSrr 0U, // DIVR_F32m 0U, // DIVR_F64m 0U, // DIVR_FI16m 0U, // DIVR_FI32m 0U, // DIVR_FPrST0 0U, // DIVR_FST0r 0U, // DIVR_Fp32m 0U, // DIVR_Fp64m 0U, // DIVR_Fp64m32 0U, // DIVR_Fp80m32 0U, // DIVR_Fp80m64 0U, // DIVR_FpI16m32 0U, // DIVR_FpI16m64 0U, // DIVR_FpI16m80 0U, // DIVR_FpI32m32 0U, // DIVR_FpI32m64 0U, // DIVR_FpI32m80 0U, // DIVR_FrST0 0U, // DIVSDrm 0U, // DIVSDrm_Int 0U, // DIVSDrr 0U, // DIVSDrr_Int 0U, // DIVSSrm 0U, // DIVSSrm_Int 0U, // DIVSSrr 0U, // DIVSSrr_Int 0U, // DIV_F32m 0U, // DIV_F64m 0U, // DIV_FI16m 0U, // DIV_FI32m 0U, // DIV_FPrST0 0U, // DIV_FST0r 0U, // DIV_Fp32 0U, // DIV_Fp32m 0U, // DIV_Fp64 0U, // DIV_Fp64m 0U, // DIV_Fp64m32 0U, // DIV_Fp80 0U, // DIV_Fp80m32 0U, // DIV_Fp80m64 0U, // DIV_FpI16m32 0U, // DIV_FpI16m64 0U, // DIV_FpI16m80 0U, // DIV_FpI32m32 0U, // DIV_FpI32m64 0U, // DIV_FpI32m80 0U, // DIV_FrST0 192U, // DPPDrmi 224U, // DPPDrri 192U, // DPPSrmi 224U, // DPPSrri 0U, // ENCLS 0U, // ENCLU 0U, // ENCLV 0U, // ENDBR32 0U, // ENDBR64 0U, // ENTER 0U, // EXTRACTPSmr 32U, // EXTRACTPSrr 0U, // EXTRQ 224U, // EXTRQI 0U, // F2XM1 0U, // FARCALL16i 0U, // FARCALL16m 0U, // FARCALL32i 0U, // FARCALL32m 0U, // FARCALL64 0U, // FARJMP16i 0U, // FARJMP16m 0U, // FARJMP32i 0U, // FARJMP32m 0U, // FARJMP64 0U, // FBLDm 0U, // FBSTPm 0U, // FCOM32m 0U, // FCOM64m 0U, // FCOMP32m 0U, // FCOMP64m 0U, // FCOMPP 0U, // FDECSTP 0U, // FDISI8087_NOP 0U, // FEMMS 0U, // FENI8087_NOP 0U, // FFREE 0U, // FFREEP 0U, // FICOM16m 0U, // FICOM32m 0U, // FICOMP16m 0U, // FICOMP32m 0U, // FINCSTP 0U, // FLDCW16m 0U, // FLDENVm 0U, // FLDL2E 0U, // FLDL2T 0U, // FLDLG2 0U, // FLDLN2 0U, // FLDPI 0U, // FNCLEX 0U, // FNINIT 0U, // FNOP 0U, // FNSTCW16m 0U, // FNSTSW16r 0U, // FNSTSWm 0U, // FPATAN 0U, // FPNCEST0r 0U, // FPREM 0U, // FPREM1 0U, // FPTAN 0U, // FRNDINT 0U, // FRSTORm 0U, // FSAVEm 0U, // FSCALE 0U, // FSETPM 0U, // FSINCOS 0U, // FSTENVm 0U, // FXAM 0U, // FXRSTOR 0U, // FXRSTOR64 0U, // FXSAVE 0U, // FXSAVE64 0U, // FXTRACT 0U, // FYL2X 0U, // FYL2XP1 0U, // GETSEC 192U, // GF2P8AFFINEINVQBrmi 224U, // GF2P8AFFINEINVQBrri 192U, // GF2P8AFFINEQBrmi 224U, // GF2P8AFFINEQBrri 0U, // GF2P8MULBrm 0U, // GF2P8MULBrr 0U, // HADDPDrm 0U, // HADDPDrr 0U, // HADDPSrm 0U, // HADDPSrr 0U, // HLT 0U, // HSUBPDrm 0U, // HSUBPDrr 0U, // HSUBPSrm 0U, // HSUBPSrr 0U, // IDIV16m 0U, // IDIV16r 0U, // IDIV32m 0U, // IDIV32r 0U, // IDIV64m 0U, // IDIV64r 0U, // IDIV8m 0U, // IDIV8r 0U, // ILD_F16m 0U, // ILD_F32m 0U, // ILD_F64m 0U, // ILD_Fp16m32 0U, // ILD_Fp16m64 0U, // ILD_Fp16m80 0U, // ILD_Fp32m32 0U, // ILD_Fp32m64 0U, // ILD_Fp32m80 0U, // ILD_Fp64m32 0U, // ILD_Fp64m64 0U, // ILD_Fp64m80 0U, // IMUL16m 0U, // IMUL16r 0U, // IMUL16rm 160U, // IMUL16rmi 160U, // IMUL16rmi8 0U, // IMUL16rr 96U, // IMUL16rri 96U, // IMUL16rri8 0U, // IMUL32m 0U, // IMUL32r 0U, // IMUL32rm 160U, // IMUL32rmi 160U, // IMUL32rmi8 0U, // IMUL32rr 96U, // IMUL32rri 96U, // IMUL32rri8 0U, // IMUL64m 0U, // IMUL64r 0U, // IMUL64rm 160U, // IMUL64rmi32 160U, // IMUL64rmi8 0U, // IMUL64rr 96U, // IMUL64rri32 96U, // IMUL64rri8 0U, // IMUL8m 0U, // IMUL8r 0U, // IN16ri 0U, // IN16rr 0U, // IN32ri 0U, // IN32rr 0U, // IN8ri 0U, // IN8rr 0U, // INC16m 0U, // INC16r 0U, // INC16r_alt 0U, // INC32m 0U, // INC32r 0U, // INC32r_alt 0U, // INC64m 0U, // INC64r 0U, // INC8m 0U, // INC8r 0U, // INCSSPD 0U, // INCSSPQ 0U, // INSB 192U, // INSERTPSrm 224U, // INSERTPSrr 0U, // INSERTQ 2272U, // INSERTQI 0U, // INSL 0U, // INSW 0U, // INT 0U, // INT1 0U, // INT3 0U, // INTO 0U, // INVD 0U, // INVEPT32 0U, // INVEPT64 0U, // INVLPG 0U, // INVLPGA32 0U, // INVLPGA64 0U, // INVPCID32 0U, // INVPCID64 0U, // INVVPID32 0U, // INVVPID64 0U, // IRET16 0U, // IRET32 0U, // IRET64 0U, // ISTT_FP16m 0U, // ISTT_FP32m 0U, // ISTT_FP64m 0U, // ISTT_Fp16m32 0U, // ISTT_Fp16m64 0U, // ISTT_Fp16m80 0U, // ISTT_Fp32m32 0U, // ISTT_Fp32m64 0U, // ISTT_Fp32m80 0U, // ISTT_Fp64m32 0U, // ISTT_Fp64m64 0U, // ISTT_Fp64m80 0U, // IST_F16m 0U, // IST_F32m 0U, // IST_FP16m 0U, // IST_FP32m 0U, // IST_FP64m 0U, // IST_Fp16m32 0U, // IST_Fp16m64 0U, // IST_Fp16m80 0U, // IST_Fp32m32 0U, // IST_Fp32m64 0U, // IST_Fp32m80 0U, // IST_Fp64m32 0U, // IST_Fp64m64 0U, // IST_Fp64m80 0U, // JAE_1 0U, // JAE_2 0U, // JAE_4 0U, // JA_1 0U, // JA_2 0U, // JA_4 0U, // JBE_1 0U, // JBE_2 0U, // JBE_4 0U, // JB_1 0U, // JB_2 0U, // JB_4 0U, // JCXZ 0U, // JECXZ 0U, // JE_1 0U, // JE_2 0U, // JE_4 0U, // JGE_1 0U, // JGE_2 0U, // JGE_4 0U, // JG_1 0U, // JG_2 0U, // JG_4 0U, // JLE_1 0U, // JLE_2 0U, // JLE_4 0U, // JL_1 0U, // JL_2 0U, // JL_4 0U, // JMP16m 0U, // JMP16m_NT 0U, // JMP16r 0U, // JMP16r_NT 0U, // JMP32m 0U, // JMP32m_NT 0U, // JMP32r 0U, // JMP32r_NT 0U, // JMP64m 0U, // JMP64m_NT 0U, // JMP64r 0U, // JMP64r_NT 0U, // JMP_1 0U, // JMP_2 0U, // JMP_4 0U, // JNE_1 0U, // JNE_2 0U, // JNE_4 0U, // JNO_1 0U, // JNO_2 0U, // JNO_4 0U, // JNP_1 0U, // JNP_2 0U, // JNP_4 0U, // JNS_1 0U, // JNS_2 0U, // JNS_4 0U, // JO_1 0U, // JO_2 0U, // JO_4 0U, // JP_1 0U, // JP_2 0U, // JP_4 0U, // JRCXZ 0U, // JS_1 0U, // JS_2 0U, // JS_4 96U, // KADDBrr 96U, // KADDDrr 96U, // KADDQrr 96U, // KADDWrr 96U, // KANDBrr 96U, // KANDDrr 96U, // KANDNBrr 96U, // KANDNDrr 96U, // KANDNQrr 96U, // KANDNWrr 96U, // KANDQrr 96U, // KANDWrr 0U, // KMOVBkk 0U, // KMOVBkm 0U, // KMOVBkr 0U, // KMOVBmk 0U, // KMOVBrk 0U, // KMOVDkk 0U, // KMOVDkm 0U, // KMOVDkr 0U, // KMOVDmk 0U, // KMOVDrk 0U, // KMOVQkk 0U, // KMOVQkm 0U, // KMOVQkr 0U, // KMOVQmk 0U, // KMOVQrk 0U, // KMOVWkk 0U, // KMOVWkm 0U, // KMOVWkr 0U, // KMOVWmk 0U, // KMOVWrk 0U, // KNOTBrr 0U, // KNOTDrr 0U, // KNOTQrr 0U, // KNOTWrr 96U, // KORBrr 96U, // KORDrr 96U, // KORQrr 0U, // KORTESTBrr 0U, // KORTESTDrr 0U, // KORTESTQrr 0U, // KORTESTWrr 96U, // KORWrr 32U, // KSHIFTLBri 32U, // KSHIFTLDri 32U, // KSHIFTLQri 32U, // KSHIFTLWri 32U, // KSHIFTRBri 32U, // KSHIFTRDri 32U, // KSHIFTRQri 32U, // KSHIFTRWri 0U, // KTESTBrr 0U, // KTESTDrr 0U, // KTESTQrr 0U, // KTESTWrr 96U, // KUNPCKBWrr 96U, // KUNPCKDQrr 96U, // KUNPCKWDrr 96U, // KXNORBrr 96U, // KXNORDrr 96U, // KXNORQrr 96U, // KXNORWrr 96U, // KXORBrr 96U, // KXORDrr 96U, // KXORQrr 96U, // KXORWrr 0U, // LAHF 0U, // LAR16rm 0U, // LAR16rr 0U, // LAR32rm 0U, // LAR32rr 0U, // LAR64rm 0U, // LAR64rr 0U, // LDDQUrm 0U, // LDMXCSR 0U, // LDS16rm 0U, // LDS32rm 0U, // LD_F0 0U, // LD_F1 0U, // LD_F32m 0U, // LD_F64m 0U, // LD_F80m 0U, // LD_Fp032 0U, // LD_Fp064 0U, // LD_Fp080 0U, // LD_Fp132 0U, // LD_Fp164 0U, // LD_Fp180 0U, // LD_Fp32m 0U, // LD_Fp32m64 0U, // LD_Fp32m80 0U, // LD_Fp64m 0U, // LD_Fp64m80 0U, // LD_Fp80m 0U, // LD_Frr 0U, // LEA16r 0U, // LEA32r 0U, // LEA64_32r 0U, // LEA64r 0U, // LEAVE 0U, // LEAVE64 0U, // LES16rm 0U, // LES32rm 0U, // LFENCE 0U, // LFS16rm 0U, // LFS32rm 0U, // LFS64rm 0U, // LGDT16m 0U, // LGDT32m 0U, // LGDT64m 0U, // LGS16rm 0U, // LGS32rm 0U, // LGS64rm 0U, // LIDT16m 0U, // LIDT32m 0U, // LIDT64m 0U, // LLDT16m 0U, // LLDT16r 0U, // LLWPCB 0U, // LLWPCB64 0U, // LMSW16m 0U, // LMSW16r 0U, // LOCK_PREFIX 0U, // LODSB 0U, // LODSL 0U, // LODSQ 0U, // LODSW 0U, // LOOP 0U, // LOOPE 0U, // LOOPNE 0U, // LRETIL 0U, // LRETIQ 0U, // LRETIW 0U, // LRETL 0U, // LRETQ 0U, // LRETW 0U, // LSL16rm 0U, // LSL16rr 0U, // LSL32rm 0U, // LSL32rr 0U, // LSL64rm 0U, // LSL64rr 0U, // LSS16rm 0U, // LSS32rm 0U, // LSS64rm 0U, // LTRm 0U, // LTRr 160U, // LWPINS32rmi 96U, // LWPINS32rri 160U, // LWPINS64rmi 96U, // LWPINS64rri 160U, // LWPVAL32rmi 96U, // LWPVAL32rri 160U, // LWPVAL64rmi 96U, // LWPVAL64rri 0U, // LZCNT16rm 0U, // LZCNT16rr 0U, // LZCNT32rm 0U, // LZCNT32rr 0U, // LZCNT64rm 0U, // LZCNT64rr 0U, // MASKMOVDQU 0U, // MASKMOVDQU64 0U, // MAXCPDrm 0U, // MAXCPDrr 0U, // MAXCPSrm 0U, // MAXCPSrr 0U, // MAXCSDrm 0U, // MAXCSDrr 0U, // MAXCSSrm 0U, // MAXCSSrr 0U, // MAXPDrm 0U, // MAXPDrr 0U, // MAXPSrm 0U, // MAXPSrr 0U, // MAXSDrm 0U, // MAXSDrm_Int 0U, // MAXSDrr 0U, // MAXSDrr_Int 0U, // MAXSSrm 0U, // MAXSSrm_Int 0U, // MAXSSrr 0U, // MAXSSrr_Int 0U, // MFENCE 0U, // MINCPDrm 0U, // MINCPDrr 0U, // MINCPSrm 0U, // MINCPSrr 0U, // MINCSDrm 0U, // MINCSDrr 0U, // MINCSSrm 0U, // MINCSSrr 0U, // MINPDrm 0U, // MINPDrr 0U, // MINPSrm 0U, // MINPSrr 0U, // MINSDrm 0U, // MINSDrm_Int 0U, // MINSDrr 0U, // MINSDrr_Int 0U, // MINSSrm 0U, // MINSSrm_Int 0U, // MINSSrr 0U, // MINSSrr_Int 0U, // MMX_CVTPD2PIirm 0U, // MMX_CVTPD2PIirr 0U, // MMX_CVTPI2PDirm 0U, // MMX_CVTPI2PDirr 0U, // MMX_CVTPI2PSirm 0U, // MMX_CVTPI2PSirr 0U, // MMX_CVTPS2PIirm 0U, // MMX_CVTPS2PIirr 0U, // MMX_CVTTPD2PIirm 0U, // MMX_CVTTPD2PIirr 0U, // MMX_CVTTPS2PIirm 0U, // MMX_CVTTPS2PIirr 0U, // MMX_EMMS 0U, // MMX_MASKMOVQ 0U, // MMX_MASKMOVQ64 0U, // MMX_MOVD64from64rm 0U, // MMX_MOVD64from64rr 0U, // MMX_MOVD64grr 0U, // MMX_MOVD64mr 0U, // MMX_MOVD64rm 0U, // MMX_MOVD64rr 0U, // MMX_MOVD64to64rm 0U, // MMX_MOVD64to64rr 0U, // MMX_MOVDQ2Qrr 0U, // MMX_MOVFR642Qrr 0U, // MMX_MOVNTQmr 0U, // MMX_MOVQ2DQrr 0U, // MMX_MOVQ2FR64rr 0U, // MMX_MOVQ64mr 0U, // MMX_MOVQ64rm 0U, // MMX_MOVQ64rr 0U, // MMX_MOVQ64rr_REV 0U, // MMX_PABSBrm 0U, // MMX_PABSBrr 0U, // MMX_PABSDrm 0U, // MMX_PABSDrr 0U, // MMX_PABSWrm 0U, // MMX_PABSWrr 0U, // MMX_PACKSSDWirm 0U, // MMX_PACKSSDWirr 0U, // MMX_PACKSSWBirm 0U, // MMX_PACKSSWBirr 0U, // MMX_PACKUSWBirm 0U, // MMX_PACKUSWBirr 0U, // MMX_PADDBirm 0U, // MMX_PADDBirr 0U, // MMX_PADDDirm 0U, // MMX_PADDDirr 0U, // MMX_PADDQirm 0U, // MMX_PADDQirr 0U, // MMX_PADDSBirm 0U, // MMX_PADDSBirr 0U, // MMX_PADDSWirm 0U, // MMX_PADDSWirr 0U, // MMX_PADDUSBirm 0U, // MMX_PADDUSBirr 0U, // MMX_PADDUSWirm 0U, // MMX_PADDUSWirr 0U, // MMX_PADDWirm 0U, // MMX_PADDWirr 192U, // MMX_PALIGNRrmi 224U, // MMX_PALIGNRrri 0U, // MMX_PANDNirm 0U, // MMX_PANDNirr 0U, // MMX_PANDirm 0U, // MMX_PANDirr 0U, // MMX_PAVGBirm 0U, // MMX_PAVGBirr 0U, // MMX_PAVGWirm 0U, // MMX_PAVGWirr 0U, // MMX_PCMPEQBirm 0U, // MMX_PCMPEQBirr 0U, // MMX_PCMPEQDirm 0U, // MMX_PCMPEQDirr 0U, // MMX_PCMPEQWirm 0U, // MMX_PCMPEQWirr 0U, // MMX_PCMPGTBirm 0U, // MMX_PCMPGTBirr 0U, // MMX_PCMPGTDirm 0U, // MMX_PCMPGTDirr 0U, // MMX_PCMPGTWirm 0U, // MMX_PCMPGTWirr 32U, // MMX_PEXTRWrr 0U, // MMX_PHADDDrm 0U, // MMX_PHADDDrr 0U, // MMX_PHADDSWrm 0U, // MMX_PHADDSWrr 0U, // MMX_PHADDWrm 0U, // MMX_PHADDWrr 0U, // MMX_PHSUBDrm 0U, // MMX_PHSUBDrr 0U, // MMX_PHSUBSWrm 0U, // MMX_PHSUBSWrr 0U, // MMX_PHSUBWrm 0U, // MMX_PHSUBWrr 192U, // MMX_PINSRWrm 224U, // MMX_PINSRWrr 0U, // MMX_PMADDUBSWrm 0U, // MMX_PMADDUBSWrr 0U, // MMX_PMADDWDirm 0U, // MMX_PMADDWDirr 0U, // MMX_PMAXSWirm 0U, // MMX_PMAXSWirr 0U, // MMX_PMAXUBirm 0U, // MMX_PMAXUBirr 0U, // MMX_PMINSWirm 0U, // MMX_PMINSWirr 0U, // MMX_PMINUBirm 0U, // MMX_PMINUBirr 0U, // MMX_PMOVMSKBrr 0U, // MMX_PMULHRSWrm 0U, // MMX_PMULHRSWrr 0U, // MMX_PMULHUWirm 0U, // MMX_PMULHUWirr 0U, // MMX_PMULHWirm 0U, // MMX_PMULHWirr 0U, // MMX_PMULLWirm 0U, // MMX_PMULLWirr 0U, // MMX_PMULUDQirm 0U, // MMX_PMULUDQirr 0U, // MMX_PORirm 0U, // MMX_PORirr 0U, // MMX_PSADBWirm 0U, // MMX_PSADBWirr 0U, // MMX_PSHUFBrm 0U, // MMX_PSHUFBrr 0U, // MMX_PSHUFWmi 32U, // MMX_PSHUFWri 0U, // MMX_PSIGNBrm 0U, // MMX_PSIGNBrr 0U, // MMX_PSIGNDrm 0U, // MMX_PSIGNDrr 0U, // MMX_PSIGNWrm 0U, // MMX_PSIGNWrr 0U, // MMX_PSLLDri 0U, // MMX_PSLLDrm 0U, // MMX_PSLLDrr 0U, // MMX_PSLLQri 0U, // MMX_PSLLQrm 0U, // MMX_PSLLQrr 0U, // MMX_PSLLWri 0U, // MMX_PSLLWrm 0U, // MMX_PSLLWrr 0U, // MMX_PSRADri 0U, // MMX_PSRADrm 0U, // MMX_PSRADrr 0U, // MMX_PSRAWri 0U, // MMX_PSRAWrm 0U, // MMX_PSRAWrr 0U, // MMX_PSRLDri 0U, // MMX_PSRLDrm 0U, // MMX_PSRLDrr 0U, // MMX_PSRLQri 0U, // MMX_PSRLQrm 0U, // MMX_PSRLQrr 0U, // MMX_PSRLWri 0U, // MMX_PSRLWrm 0U, // MMX_PSRLWrr 0U, // MMX_PSUBBirm 0U, // MMX_PSUBBirr 0U, // MMX_PSUBDirm 0U, // MMX_PSUBDirr 0U, // MMX_PSUBQirm 0U, // MMX_PSUBQirr 0U, // MMX_PSUBSBirm 0U, // MMX_PSUBSBirr 0U, // MMX_PSUBSWirm 0U, // MMX_PSUBSWirr 0U, // MMX_PSUBUSBirm 0U, // MMX_PSUBUSBirr 0U, // MMX_PSUBUSWirm 0U, // MMX_PSUBUSWirr 0U, // MMX_PSUBWirm 0U, // MMX_PSUBWirr 0U, // MMX_PUNPCKHBWirm 0U, // MMX_PUNPCKHBWirr 0U, // MMX_PUNPCKHDQirm 0U, // MMX_PUNPCKHDQirr 0U, // MMX_PUNPCKHWDirm 0U, // MMX_PUNPCKHWDirr 0U, // MMX_PUNPCKLBWirm 0U, // MMX_PUNPCKLBWirr 0U, // MMX_PUNPCKLDQirm 0U, // MMX_PUNPCKLDQirr 0U, // MMX_PUNPCKLWDirm 0U, // MMX_PUNPCKLWDirr 0U, // MMX_PXORirm 0U, // MMX_PXORirr 0U, // MONITORXrrr 0U, // MONITORrrr 0U, // MONTMUL 0U, // MOV16ao16 0U, // MOV16ao32 0U, // MOV16ao64 0U, // MOV16mi 0U, // MOV16mr 0U, // MOV16ms 0U, // MOV16o16a 0U, // MOV16o32a 0U, // MOV16o64a 0U, // MOV16ri 0U, // MOV16ri_alt 0U, // MOV16rm 0U, // MOV16rr 0U, // MOV16rr_REV 0U, // MOV16rs 0U, // MOV16sm 0U, // MOV16sr 0U, // MOV32ao16 0U, // MOV32ao32 0U, // MOV32ao64 0U, // MOV32cr 0U, // MOV32dr 0U, // MOV32mi 0U, // MOV32mr 0U, // MOV32o16a 0U, // MOV32o32a 0U, // MOV32o64a 0U, // MOV32rc 0U, // MOV32rd 0U, // MOV32ri 0U, // MOV32ri_alt 0U, // MOV32rm 0U, // MOV32rr 0U, // MOV32rr_REV 0U, // MOV32rs 0U, // MOV32sr 0U, // MOV64ao32 0U, // MOV64ao64 0U, // MOV64cr 0U, // MOV64dr 0U, // MOV64mi32 0U, // MOV64mr 0U, // MOV64o32a 0U, // MOV64o64a 0U, // MOV64rc 0U, // MOV64rd 0U, // MOV64ri 0U, // MOV64ri32 0U, // MOV64rm 0U, // MOV64rr 0U, // MOV64rr_REV 0U, // MOV64rs 0U, // MOV64sr 0U, // MOV64toPQIrm 0U, // MOV64toPQIrr 0U, // MOV64toSDrm 0U, // MOV64toSDrr 0U, // MOV8ao16 0U, // MOV8ao32 0U, // MOV8ao64 0U, // MOV8mi 0U, // MOV8mr 0U, // MOV8mr_NOREX 0U, // MOV8o16a 0U, // MOV8o32a 0U, // MOV8o64a 0U, // MOV8ri 0U, // MOV8ri_alt 0U, // MOV8rm 0U, // MOV8rm_NOREX 0U, // MOV8rr 0U, // MOV8rr_NOREX 0U, // MOV8rr_REV 0U, // MOVAPDmr 0U, // MOVAPDrm 0U, // MOVAPDrr 0U, // MOVAPDrr_REV 0U, // MOVAPSmr 0U, // MOVAPSrm 0U, // MOVAPSrr 0U, // MOVAPSrr_REV 0U, // MOVBE16mr 0U, // MOVBE16rm 0U, // MOVBE32mr 0U, // MOVBE32rm 0U, // MOVBE64mr 0U, // MOVBE64rm 0U, // MOVDDUPrm 0U, // MOVDDUPrr 0U, // MOVDI2PDIrm 0U, // MOVDI2PDIrr 0U, // MOVDI2SSrm 0U, // MOVDI2SSrr 0U, // MOVDIR64B16 0U, // MOVDIR64B32 0U, // MOVDIR64B64 0U, // MOVDIRI32 0U, // MOVDIRI64 0U, // MOVDQAmr 0U, // MOVDQArm 0U, // MOVDQArr 0U, // MOVDQArr_REV 0U, // MOVDQUmr 0U, // MOVDQUrm 0U, // MOVDQUrr 0U, // MOVDQUrr_REV 0U, // MOVHLPSrr 0U, // MOVHPDmr 0U, // MOVHPDrm 0U, // MOVHPSmr 0U, // MOVHPSrm 0U, // MOVLHPSrr 0U, // MOVLPDmr 0U, // MOVLPDrm 0U, // MOVLPSmr 0U, // MOVLPSrm 0U, // MOVMSKPDrr 0U, // MOVMSKPSrr 0U, // MOVNTDQArm 0U, // MOVNTDQmr 0U, // MOVNTI_64mr 0U, // MOVNTImr 0U, // MOVNTPDmr 0U, // MOVNTPSmr 0U, // MOVNTSD 0U, // MOVNTSS 0U, // MOVPDI2DImr 0U, // MOVPDI2DIrr 0U, // MOVPQI2QImr 0U, // MOVPQI2QIrr 0U, // MOVPQIto64mr 0U, // MOVPQIto64rr 0U, // MOVQI2PQIrm 0U, // MOVSB 0U, // MOVSDmr 0U, // MOVSDrm 0U, // MOVSDrr 0U, // MOVSDrr_REV 0U, // MOVSDto64mr 0U, // MOVSDto64rr 0U, // MOVSHDUPrm 0U, // MOVSHDUPrr 0U, // MOVSL 0U, // MOVSLDUPrm 0U, // MOVSLDUPrr 0U, // MOVSQ 0U, // MOVSS2DImr 0U, // MOVSS2DIrr 0U, // MOVSSmr 0U, // MOVSSrm 0U, // MOVSSrr 0U, // MOVSSrr_REV 0U, // MOVSW 0U, // MOVSX16rm16 0U, // MOVSX16rm8 0U, // MOVSX16rr16 0U, // MOVSX16rr8 0U, // MOVSX32rm16 0U, // MOVSX32rm8 0U, // MOVSX32rm8_NOREX 0U, // MOVSX32rr16 0U, // MOVSX32rr8 0U, // MOVSX32rr8_NOREX 0U, // MOVSX64rm16 0U, // MOVSX64rm32 0U, // MOVSX64rm8 0U, // MOVSX64rr16 0U, // MOVSX64rr32 0U, // MOVSX64rr8 0U, // MOVUPDmr 0U, // MOVUPDrm 0U, // MOVUPDrr 0U, // MOVUPDrr_REV 0U, // MOVUPSmr 0U, // MOVUPSrm 0U, // MOVUPSrr 0U, // MOVUPSrr_REV 0U, // MOVZPQILo2PQIrr 0U, // MOVZX16rm16 0U, // MOVZX16rm8 0U, // MOVZX16rr16 0U, // MOVZX16rr8 0U, // MOVZX32rm16 0U, // MOVZX32rm8 0U, // MOVZX32rm8_NOREX 0U, // MOVZX32rr16 0U, // MOVZX32rr8 0U, // MOVZX32rr8_NOREX 0U, // MOVZX64rm16 0U, // MOVZX64rm8 0U, // MOVZX64rr16 0U, // MOVZX64rr8 192U, // MPSADBWrmi 224U, // MPSADBWrri 0U, // MUL16m 0U, // MUL16r 0U, // MUL32m 0U, // MUL32r 0U, // MUL64m 0U, // MUL64r 0U, // MUL8m 0U, // MUL8r 0U, // MULPDrm 0U, // MULPDrr 0U, // MULPSrm 0U, // MULPSrr 0U, // MULSDrm 0U, // MULSDrm_Int 0U, // MULSDrr 0U, // MULSDrr_Int 0U, // MULSSrm 0U, // MULSSrm_Int 0U, // MULSSrr 0U, // MULSSrr_Int 64U, // MULX32rm 96U, // MULX32rr 128U, // MULX64rm 96U, // MULX64rr 0U, // MUL_F32m 0U, // MUL_F64m 0U, // MUL_FI16m 0U, // MUL_FI32m 0U, // MUL_FPrST0 0U, // MUL_FST0r 0U, // MUL_Fp32 0U, // MUL_Fp32m 0U, // MUL_Fp64 0U, // MUL_Fp64m 0U, // MUL_Fp64m32 0U, // MUL_Fp80 0U, // MUL_Fp80m32 0U, // MUL_Fp80m64 0U, // MUL_FpI16m32 0U, // MUL_FpI16m64 0U, // MUL_FpI16m80 0U, // MUL_FpI32m32 0U, // MUL_FpI32m64 0U, // MUL_FpI32m80 0U, // MUL_FrST0 0U, // MWAITXrrr 0U, // MWAITrr 0U, // NEG16m 0U, // NEG16r 0U, // NEG32m 0U, // NEG32r 0U, // NEG64m 0U, // NEG64r 0U, // NEG8m 0U, // NEG8r 0U, // NOOP 0U, // NOOP18_16m4 0U, // NOOP18_16m5 0U, // NOOP18_16m6 0U, // NOOP18_16m7 0U, // NOOP18_16r4 0U, // NOOP18_16r5 0U, // NOOP18_16r6 0U, // NOOP18_16r7 0U, // NOOP18_m4 0U, // NOOP18_m5 0U, // NOOP18_m6 0U, // NOOP18_m7 0U, // NOOP18_r4 0U, // NOOP18_r5 0U, // NOOP18_r6 0U, // NOOP18_r7 0U, // NOOP19rr 0U, // NOOPL 0U, // NOOPL_19 0U, // NOOPL_1d 0U, // NOOPL_1e 0U, // NOOPLr 0U, // NOOPQ 0U, // NOOPQr 0U, // NOOPW 0U, // NOOPW_19 0U, // NOOPW_1c 0U, // NOOPW_1d 0U, // NOOPW_1e 0U, // NOOPWr 0U, // NOT16m 0U, // NOT16r 0U, // NOT32m 0U, // NOT32r 0U, // NOT64m 0U, // NOT64r 0U, // NOT8m 0U, // NOT8r 0U, // OR16i16 0U, // OR16mi 0U, // OR16mi8 0U, // OR16mr 0U, // OR16ri 0U, // OR16ri8 0U, // OR16rm 0U, // OR16rr 0U, // OR16rr_REV 0U, // OR32i32 0U, // OR32mi 0U, // OR32mi8 0U, // OR32mr 0U, // OR32ri 0U, // OR32ri8 0U, // OR32rm 0U, // OR32rr 0U, // OR32rr_REV 0U, // OR64i32 0U, // OR64mi32 0U, // OR64mi8 0U, // OR64mr 0U, // OR64ri32 0U, // OR64ri8 0U, // OR64rm 0U, // OR64rr 0U, // OR64rr_REV 0U, // OR8i8 0U, // OR8mi 0U, // OR8mi8 0U, // OR8mr 0U, // OR8ri 0U, // OR8ri8 0U, // OR8rm 0U, // OR8rr 0U, // OR8rr_REV 0U, // ORPDrm 0U, // ORPDrr 0U, // ORPSrm 0U, // ORPSrr 0U, // OUT16ir 0U, // OUT16rr 0U, // OUT32ir 0U, // OUT32rr 0U, // OUT8ir 0U, // OUT8rr 0U, // OUTSB 0U, // OUTSL 0U, // OUTSW 0U, // PABSBrm 0U, // PABSBrr 0U, // PABSDrm 0U, // PABSDrr 0U, // PABSWrm 0U, // PABSWrr 0U, // PACKSSDWrm 0U, // PACKSSDWrr 0U, // PACKSSWBrm 0U, // PACKSSWBrr 0U, // PACKUSDWrm 0U, // PACKUSDWrr 0U, // PACKUSWBrm 0U, // PACKUSWBrr 0U, // PADDBrm 0U, // PADDBrr 0U, // PADDDrm 0U, // PADDDrr 0U, // PADDQrm 0U, // PADDQrr 0U, // PADDSBrm 0U, // PADDSBrr 0U, // PADDSWrm 0U, // PADDSWrr 0U, // PADDUSBrm 0U, // PADDUSBrr 0U, // PADDUSWrm 0U, // PADDUSWrr 0U, // PADDWrm 0U, // PADDWrr 192U, // PALIGNRrmi 224U, // PALIGNRrri 0U, // PANDNrm 0U, // PANDNrr 0U, // PANDrm 0U, // PANDrr 0U, // PAUSE 0U, // PAVGBrm 0U, // PAVGBrr 0U, // PAVGUSBrm 0U, // PAVGUSBrr 0U, // PAVGWrm 0U, // PAVGWrr 1U, // PBLENDVBrm0 1U, // PBLENDVBrr0 192U, // PBLENDWrmi 224U, // PBLENDWrri 192U, // PCLMULQDQrm 224U, // PCLMULQDQrr 0U, // PCMPEQBrm 0U, // PCMPEQBrr 0U, // PCMPEQDrm 0U, // PCMPEQDrr 0U, // PCMPEQQrm 0U, // PCMPEQQrr 0U, // PCMPEQWrm 0U, // PCMPEQWrr 0U, // PCMPESTRIrm 32U, // PCMPESTRIrr 0U, // PCMPESTRMrm 32U, // PCMPESTRMrr 0U, // PCMPGTBrm 0U, // PCMPGTBrr 0U, // PCMPGTDrm 0U, // PCMPGTDrr 0U, // PCMPGTQrm 0U, // PCMPGTQrr 0U, // PCMPGTWrm 0U, // PCMPGTWrr 0U, // PCMPISTRIrm 32U, // PCMPISTRIrr 0U, // PCMPISTRMrm 32U, // PCMPISTRMrr 0U, // PCONFIG 64U, // PDEP32rm 96U, // PDEP32rr 128U, // PDEP64rm 96U, // PDEP64rr 64U, // PEXT32rm 96U, // PEXT32rr 128U, // PEXT64rm 96U, // PEXT64rr 0U, // PEXTRBmr 32U, // PEXTRBrr 0U, // PEXTRDmr 32U, // PEXTRDrr 0U, // PEXTRQmr 32U, // PEXTRQrr 0U, // PEXTRWmr 32U, // PEXTRWrr 32U, // PEXTRWrr_REV 0U, // PF2IDrm 0U, // PF2IDrr 0U, // PF2IWrm 0U, // PF2IWrr 0U, // PFACCrm 0U, // PFACCrr 0U, // PFADDrm 0U, // PFADDrr 0U, // PFCMPEQrm 0U, // PFCMPEQrr 0U, // PFCMPGErm 0U, // PFCMPGErr 0U, // PFCMPGTrm 0U, // PFCMPGTrr 0U, // PFMAXrm 0U, // PFMAXrr 0U, // PFMINrm 0U, // PFMINrr 0U, // PFMULrm 0U, // PFMULrr 0U, // PFNACCrm 0U, // PFNACCrr 0U, // PFPNACCrm 0U, // PFPNACCrr 0U, // PFRCPIT1rm 0U, // PFRCPIT1rr 0U, // PFRCPIT2rm 0U, // PFRCPIT2rr 0U, // PFRCPrm 0U, // PFRCPrr 0U, // PFRSQIT1rm 0U, // PFRSQIT1rr 0U, // PFRSQRTrm 0U, // PFRSQRTrr 0U, // PFSUBRrm 0U, // PFSUBRrr 0U, // PFSUBrm 0U, // PFSUBrr 0U, // PHADDDrm 0U, // PHADDDrr 0U, // PHADDSWrm 0U, // PHADDSWrr 0U, // PHADDWrm 0U, // PHADDWrr 0U, // PHMINPOSUWrm 0U, // PHMINPOSUWrr 0U, // PHSUBDrm 0U, // PHSUBDrr 0U, // PHSUBSWrm 0U, // PHSUBSWrr 0U, // PHSUBWrm 0U, // PHSUBWrr 0U, // PI2FDrm 0U, // PI2FDrr 0U, // PI2FWrm 0U, // PI2FWrr 192U, // PINSRBrm 224U, // PINSRBrr 192U, // PINSRDrm 224U, // PINSRDrr 192U, // PINSRQrm 224U, // PINSRQrr 192U, // PINSRWrm 224U, // PINSRWrr 0U, // PMADDUBSWrm 0U, // PMADDUBSWrr 0U, // PMADDWDrm 0U, // PMADDWDrr 0U, // PMAXSBrm 0U, // PMAXSBrr 0U, // PMAXSDrm 0U, // PMAXSDrr 0U, // PMAXSWrm 0U, // PMAXSWrr 0U, // PMAXUBrm 0U, // PMAXUBrr 0U, // PMAXUDrm 0U, // PMAXUDrr 0U, // PMAXUWrm 0U, // PMAXUWrr 0U, // PMINSBrm 0U, // PMINSBrr 0U, // PMINSDrm 0U, // PMINSDrr 0U, // PMINSWrm 0U, // PMINSWrr 0U, // PMINUBrm 0U, // PMINUBrr 0U, // PMINUDrm 0U, // PMINUDrr 0U, // PMINUWrm 0U, // PMINUWrr 0U, // PMOVMSKBrr 0U, // PMOVSXBDrm 0U, // PMOVSXBDrr 0U, // PMOVSXBQrm 0U, // PMOVSXBQrr 0U, // PMOVSXBWrm 0U, // PMOVSXBWrr 0U, // PMOVSXDQrm 0U, // PMOVSXDQrr 0U, // PMOVSXWDrm 0U, // PMOVSXWDrr 0U, // PMOVSXWQrm 0U, // PMOVSXWQrr 0U, // PMOVZXBDrm 0U, // PMOVZXBDrr 0U, // PMOVZXBQrm 0U, // PMOVZXBQrr 0U, // PMOVZXBWrm 0U, // PMOVZXBWrr 0U, // PMOVZXDQrm 0U, // PMOVZXDQrr 0U, // PMOVZXWDrm 0U, // PMOVZXWDrr 0U, // PMOVZXWQrm 0U, // PMOVZXWQrr 0U, // PMULDQrm 0U, // PMULDQrr 0U, // PMULHRSWrm 0U, // PMULHRSWrr 0U, // PMULHRWrm 0U, // PMULHRWrr 0U, // PMULHUWrm 0U, // PMULHUWrr 0U, // PMULHWrm 0U, // PMULHWrr 0U, // PMULLDrm 0U, // PMULLDrr 0U, // PMULLWrm 0U, // PMULLWrr 0U, // PMULUDQrm 0U, // PMULUDQrr 0U, // POP16r 0U, // POP16rmm 0U, // POP16rmr 0U, // POP32r 0U, // POP32rmm 0U, // POP32rmr 0U, // POP64r 0U, // POP64rmm 0U, // POP64rmr 0U, // POPA16 0U, // POPA32 0U, // POPCNT16rm 0U, // POPCNT16rr 0U, // POPCNT32rm 0U, // POPCNT32rr 0U, // POPCNT64rm 0U, // POPCNT64rr 0U, // POPDS16 0U, // POPDS32 0U, // POPES16 0U, // POPES32 0U, // POPF16 0U, // POPF32 0U, // POPF64 0U, // POPFS16 0U, // POPFS32 0U, // POPFS64 0U, // POPGS16 0U, // POPGS32 0U, // POPGS64 0U, // POPSS16 0U, // POPSS32 0U, // PORrm 0U, // PORrr 0U, // PREFETCH 0U, // PREFETCHNTA 0U, // PREFETCHT0 0U, // PREFETCHT1 0U, // PREFETCHT2 0U, // PREFETCHW 0U, // PREFETCHWT1 0U, // PSADBWrm 0U, // PSADBWrr 0U, // PSHUFBrm 0U, // PSHUFBrr 0U, // PSHUFDmi 32U, // PSHUFDri 0U, // PSHUFHWmi 32U, // PSHUFHWri 0U, // PSHUFLWmi 32U, // PSHUFLWri 0U, // PSIGNBrm 0U, // PSIGNBrr 0U, // PSIGNDrm 0U, // PSIGNDrr 0U, // PSIGNWrm 0U, // PSIGNWrr 0U, // PSLLDQri 0U, // PSLLDri 0U, // PSLLDrm 0U, // PSLLDrr 0U, // PSLLQri 0U, // PSLLQrm 0U, // PSLLQrr 0U, // PSLLWri 0U, // PSLLWrm 0U, // PSLLWrr 0U, // PSRADri 0U, // PSRADrm 0U, // PSRADrr 0U, // PSRAWri 0U, // PSRAWrm 0U, // PSRAWrr 0U, // PSRLDQri 0U, // PSRLDri 0U, // PSRLDrm 0U, // PSRLDrr 0U, // PSRLQri 0U, // PSRLQrm 0U, // PSRLQrr 0U, // PSRLWri 0U, // PSRLWrm 0U, // PSRLWrr 0U, // PSUBBrm 0U, // PSUBBrr 0U, // PSUBDrm 0U, // PSUBDrr 0U, // PSUBQrm 0U, // PSUBQrr 0U, // PSUBSBrm 0U, // PSUBSBrr 0U, // PSUBSWrm 0U, // PSUBSWrr 0U, // PSUBUSBrm 0U, // PSUBUSBrr 0U, // PSUBUSWrm 0U, // PSUBUSWrr 0U, // PSUBWrm 0U, // PSUBWrr 0U, // PSWAPDrm 0U, // PSWAPDrr 0U, // PTESTrm 0U, // PTESTrr 0U, // PTWRITE64m 0U, // PTWRITE64r 0U, // PTWRITEm 0U, // PTWRITEr 0U, // PUNPCKHBWrm 0U, // PUNPCKHBWrr 0U, // PUNPCKHDQrm 0U, // PUNPCKHDQrr 0U, // PUNPCKHQDQrm 0U, // PUNPCKHQDQrr 0U, // PUNPCKHWDrm 0U, // PUNPCKHWDrr 0U, // PUNPCKLBWrm 0U, // PUNPCKLBWrr 0U, // PUNPCKLDQrm 0U, // PUNPCKLDQrr 0U, // PUNPCKLQDQrm 0U, // PUNPCKLQDQrr 0U, // PUNPCKLWDrm 0U, // PUNPCKLWDrr 0U, // PUSH16i8 0U, // PUSH16r 0U, // PUSH16rmm 0U, // PUSH16rmr 0U, // PUSH32i8 0U, // PUSH32r 0U, // PUSH32rmm 0U, // PUSH32rmr 0U, // PUSH64i32 0U, // PUSH64i8 0U, // PUSH64r 0U, // PUSH64rmm 0U, // PUSH64rmr 0U, // PUSHA16 0U, // PUSHA32 0U, // PUSHCS16 0U, // PUSHCS32 0U, // PUSHDS16 0U, // PUSHDS32 0U, // PUSHES16 0U, // PUSHES32 0U, // PUSHF16 0U, // PUSHF32 0U, // PUSHF64 0U, // PUSHFS16 0U, // PUSHFS32 0U, // PUSHFS64 0U, // PUSHGS16 0U, // PUSHGS32 0U, // PUSHGS64 0U, // PUSHSS16 0U, // PUSHSS32 0U, // PUSHi16 0U, // PUSHi32 0U, // PXORrm 0U, // PXORrr 0U, // RCL16m1 0U, // RCL16mCL 0U, // RCL16mi 0U, // RCL16r1 0U, // RCL16rCL 0U, // RCL16ri 0U, // RCL32m1 0U, // RCL32mCL 0U, // RCL32mi 0U, // RCL32r1 0U, // RCL32rCL 0U, // RCL32ri 0U, // RCL64m1 0U, // RCL64mCL 0U, // RCL64mi 0U, // RCL64r1 0U, // RCL64rCL 0U, // RCL64ri 0U, // RCL8m1 0U, // RCL8mCL 0U, // RCL8mi 0U, // RCL8r1 0U, // RCL8rCL 0U, // RCL8ri 0U, // RCPPSm 0U, // RCPPSr 0U, // RCPSSm 0U, // RCPSSm_Int 0U, // RCPSSr 0U, // RCPSSr_Int 0U, // RCR16m1 0U, // RCR16mCL 0U, // RCR16mi 0U, // RCR16r1 0U, // RCR16rCL 0U, // RCR16ri 0U, // RCR32m1 0U, // RCR32mCL 0U, // RCR32mi 0U, // RCR32r1 0U, // RCR32rCL 0U, // RCR32ri 0U, // RCR64m1 0U, // RCR64mCL 0U, // RCR64mi 0U, // RCR64r1 0U, // RCR64rCL 0U, // RCR64ri 0U, // RCR8m1 0U, // RCR8mCL 0U, // RCR8mi 0U, // RCR8r1 0U, // RCR8rCL 0U, // RCR8ri 0U, // RDFSBASE 0U, // RDFSBASE64 0U, // RDGSBASE 0U, // RDGSBASE64 0U, // RDMSR 0U, // RDPID32 0U, // RDPID64 0U, // RDPKRUr 0U, // RDPMC 0U, // RDRAND16r 0U, // RDRAND32r 0U, // RDRAND64r 0U, // RDSEED16r 0U, // RDSEED32r 0U, // RDSEED64r 0U, // RDSSPD 0U, // RDSSPQ 0U, // RDTSC 0U, // RDTSCP 0U, // REPNE_PREFIX 0U, // REP_PREFIX 0U, // RETIL 0U, // RETIQ 0U, // RETIW 0U, // RETL 0U, // RETQ 0U, // RETW 0U, // REX64_PREFIX 0U, // ROL16m1 0U, // ROL16mCL 0U, // ROL16mi 0U, // ROL16r1 0U, // ROL16rCL 0U, // ROL16ri 0U, // ROL32m1 0U, // ROL32mCL 0U, // ROL32mi 0U, // ROL32r1 0U, // ROL32rCL 0U, // ROL32ri 0U, // ROL64m1 0U, // ROL64mCL 0U, // ROL64mi 0U, // ROL64r1 0U, // ROL64rCL 0U, // ROL64ri 0U, // ROL8m1 0U, // ROL8mCL 0U, // ROL8mi 0U, // ROL8r1 0U, // ROL8rCL 0U, // ROL8ri 0U, // ROR16m1 0U, // ROR16mCL 0U, // ROR16mi 0U, // ROR16r1 0U, // ROR16rCL 0U, // ROR16ri 0U, // ROR32m1 0U, // ROR32mCL 0U, // ROR32mi 0U, // ROR32r1 0U, // ROR32rCL 0U, // ROR32ri 0U, // ROR64m1 0U, // ROR64mCL 0U, // ROR64mi 0U, // ROR64r1 0U, // ROR64rCL 0U, // ROR64ri 0U, // ROR8m1 0U, // ROR8mCL 0U, // ROR8mi 0U, // ROR8r1 0U, // ROR8rCL 0U, // ROR8ri 0U, // RORX32mi 32U, // RORX32ri 0U, // RORX64mi 32U, // RORX64ri 0U, // ROUNDPDm 32U, // ROUNDPDr 0U, // ROUNDPSm 32U, // ROUNDPSr 0U, // ROUNDSDm 192U, // ROUNDSDm_Int 32U, // ROUNDSDr 224U, // ROUNDSDr_Int 0U, // ROUNDSSm 192U, // ROUNDSSm_Int 32U, // ROUNDSSr 224U, // ROUNDSSr_Int 0U, // RSM 0U, // RSQRTPSm 0U, // RSQRTPSr 0U, // RSQRTSSm 0U, // RSQRTSSm_Int 0U, // RSQRTSSr 0U, // RSQRTSSr_Int 0U, // RSTORSSP 0U, // SAHF 0U, // SAL16m1 0U, // SAL16mCL 0U, // SAL16mi 0U, // SAL16r1 0U, // SAL16rCL 0U, // SAL16ri 0U, // SAL32m1 0U, // SAL32mCL 0U, // SAL32mi 0U, // SAL32r1 0U, // SAL32rCL 0U, // SAL32ri 0U, // SAL64m1 0U, // SAL64mCL 0U, // SAL64mi 0U, // SAL64r1 0U, // SAL64rCL 0U, // SAL64ri 0U, // SAL8m1 0U, // SAL8mCL 0U, // SAL8mi 0U, // SAL8r1 0U, // SAL8rCL 0U, // SAL8ri 0U, // SALC 0U, // SAR16m1 0U, // SAR16mCL 0U, // SAR16mi 0U, // SAR16r1 0U, // SAR16rCL 0U, // SAR16ri 0U, // SAR32m1 0U, // SAR32mCL 0U, // SAR32mi 0U, // SAR32r1 0U, // SAR32rCL 0U, // SAR32ri 0U, // SAR64m1 0U, // SAR64mCL 0U, // SAR64mi 0U, // SAR64r1 0U, // SAR64rCL 0U, // SAR64ri 0U, // SAR8m1 0U, // SAR8mCL 0U, // SAR8mi 0U, // SAR8r1 0U, // SAR8rCL 0U, // SAR8ri 160U, // SARX32rm 96U, // SARX32rr 160U, // SARX64rm 96U, // SARX64rr 0U, // SAVEPREVSSP 0U, // SBB16i16 0U, // SBB16mi 0U, // SBB16mi8 0U, // SBB16mr 0U, // SBB16ri 0U, // SBB16ri8 0U, // SBB16rm 0U, // SBB16rr 0U, // SBB16rr_REV 0U, // SBB32i32 0U, // SBB32mi 0U, // SBB32mi8 0U, // SBB32mr 0U, // SBB32ri 0U, // SBB32ri8 0U, // SBB32rm 0U, // SBB32rr 0U, // SBB32rr_REV 0U, // SBB64i32 0U, // SBB64mi32 0U, // SBB64mi8 0U, // SBB64mr 0U, // SBB64ri32 0U, // SBB64ri8 0U, // SBB64rm 0U, // SBB64rr 0U, // SBB64rr_REV 0U, // SBB8i8 0U, // SBB8mi 0U, // SBB8mi8 0U, // SBB8mr 0U, // SBB8ri 0U, // SBB8ri8 0U, // SBB8rm 0U, // SBB8rr 0U, // SBB8rr_REV 0U, // SCASB 0U, // SCASL 0U, // SCASQ 0U, // SCASW 0U, // SETAEm 0U, // SETAEr 0U, // SETAm 0U, // SETAr 0U, // SETBEm 0U, // SETBEr 0U, // SETBm 0U, // SETBr 0U, // SETEm 0U, // SETEr 0U, // SETGEm 0U, // SETGEr 0U, // SETGm 0U, // SETGr 0U, // SETLEm 0U, // SETLEr 0U, // SETLm 0U, // SETLr 0U, // SETNEm 0U, // SETNEr 0U, // SETNOm 0U, // SETNOr 0U, // SETNPm 0U, // SETNPr 0U, // SETNSm 0U, // SETNSr 0U, // SETOm 0U, // SETOr 0U, // SETPm 0U, // SETPr 0U, // SETSSBSY 0U, // SETSm 0U, // SETSr 0U, // SFENCE 0U, // SGDT16m 0U, // SGDT32m 0U, // SGDT64m 0U, // SHA1MSG1rm 0U, // SHA1MSG1rr 0U, // SHA1MSG2rm 0U, // SHA1MSG2rr 0U, // SHA1NEXTErm 0U, // SHA1NEXTErr 192U, // SHA1RNDS4rmi 224U, // SHA1RNDS4rri 0U, // SHA256MSG1rm 0U, // SHA256MSG1rr 0U, // SHA256MSG2rm 0U, // SHA256MSG2rr 1U, // SHA256RNDS2rm 1U, // SHA256RNDS2rr 0U, // SHL16m1 0U, // SHL16mCL 0U, // SHL16mi 0U, // SHL16r1 0U, // SHL16rCL 0U, // SHL16ri 0U, // SHL32m1 0U, // SHL32mCL 0U, // SHL32mi 0U, // SHL32r1 0U, // SHL32rCL 0U, // SHL32ri 0U, // SHL64m1 0U, // SHL64mCL 0U, // SHL64mi 0U, // SHL64r1 0U, // SHL64rCL 0U, // SHL64ri 0U, // SHL8m1 0U, // SHL8mCL 0U, // SHL8mi 0U, // SHL8r1 0U, // SHL8rCL 0U, // SHL8ri 3U, // SHLD16mrCL 0U, // SHLD16mri8 3U, // SHLD16rrCL 224U, // SHLD16rri8 3U, // SHLD32mrCL 0U, // SHLD32mri8 3U, // SHLD32rrCL 224U, // SHLD32rri8 3U, // SHLD64mrCL 0U, // SHLD64mri8 3U, // SHLD64rrCL 224U, // SHLD64rri8 160U, // SHLX32rm 96U, // SHLX32rr 160U, // SHLX64rm 96U, // SHLX64rr 0U, // SHR16m1 0U, // SHR16mCL 0U, // SHR16mi 0U, // SHR16r1 0U, // SHR16rCL 0U, // SHR16ri 0U, // SHR32m1 0U, // SHR32mCL 0U, // SHR32mi 0U, // SHR32r1 0U, // SHR32rCL 0U, // SHR32ri 0U, // SHR64m1 0U, // SHR64mCL 0U, // SHR64mi 0U, // SHR64r1 0U, // SHR64rCL 0U, // SHR64ri 0U, // SHR8m1 0U, // SHR8mCL 0U, // SHR8mi 0U, // SHR8r1 0U, // SHR8rCL 0U, // SHR8ri 3U, // SHRD16mrCL 0U, // SHRD16mri8 3U, // SHRD16rrCL 224U, // SHRD16rri8 3U, // SHRD32mrCL 0U, // SHRD32mri8 3U, // SHRD32rrCL 224U, // SHRD32rri8 3U, // SHRD64mrCL 0U, // SHRD64mri8 3U, // SHRD64rrCL 224U, // SHRD64rri8 160U, // SHRX32rm 96U, // SHRX32rr 160U, // SHRX64rm 96U, // SHRX64rr 192U, // SHUFPDrmi 224U, // SHUFPDrri 192U, // SHUFPSrmi 224U, // SHUFPSrri 0U, // SIDT16m 0U, // SIDT32m 0U, // SIDT64m 0U, // SIN_F 0U, // SIN_Fp32 0U, // SIN_Fp64 0U, // SIN_Fp80 0U, // SKINIT 0U, // SLDT16m 0U, // SLDT16r 0U, // SLDT32r 0U, // SLDT64r 0U, // SLWPCB 0U, // SLWPCB64 0U, // SMSW16m 0U, // SMSW16r 0U, // SMSW32r 0U, // SMSW64r 0U, // SQRTPDm 0U, // SQRTPDr 0U, // SQRTPSm 0U, // SQRTPSr 0U, // SQRTSDm 0U, // SQRTSDm_Int 0U, // SQRTSDr 0U, // SQRTSDr_Int 0U, // SQRTSSm 0U, // SQRTSSm_Int 0U, // SQRTSSr 0U, // SQRTSSr_Int 0U, // SQRT_F 0U, // SQRT_Fp32 0U, // SQRT_Fp64 0U, // SQRT_Fp80 0U, // STAC 0U, // STC 0U, // STD 0U, // STGI 0U, // STI 0U, // STMXCSR 0U, // STOSB 0U, // STOSL 0U, // STOSQ 0U, // STOSW 0U, // STR16r 0U, // STR32r 0U, // STR64r 0U, // STRm 0U, // ST_F32m 0U, // ST_F64m 0U, // ST_FP32m 0U, // ST_FP64m 0U, // ST_FP80m 0U, // ST_FPrr 0U, // ST_Fp32m 0U, // ST_Fp64m 0U, // ST_Fp64m32 0U, // ST_Fp80m32 0U, // ST_Fp80m64 0U, // ST_FpP32m 0U, // ST_FpP64m 0U, // ST_FpP64m32 0U, // ST_FpP80m 0U, // ST_FpP80m32 0U, // ST_FpP80m64 0U, // ST_Frr 0U, // SUB16i16 0U, // SUB16mi 0U, // SUB16mi8 0U, // SUB16mr 0U, // SUB16ri 0U, // SUB16ri8 0U, // SUB16rm 0U, // SUB16rr 0U, // SUB16rr_REV 0U, // SUB32i32 0U, // SUB32mi 0U, // SUB32mi8 0U, // SUB32mr 0U, // SUB32ri 0U, // SUB32ri8 0U, // SUB32rm 0U, // SUB32rr 0U, // SUB32rr_REV 0U, // SUB64i32 0U, // SUB64mi32 0U, // SUB64mi8 0U, // SUB64mr 0U, // SUB64ri32 0U, // SUB64ri8 0U, // SUB64rm 0U, // SUB64rr 0U, // SUB64rr_REV 0U, // SUB8i8 0U, // SUB8mi 0U, // SUB8mi8 0U, // SUB8mr 0U, // SUB8ri 0U, // SUB8ri8 0U, // SUB8rm 0U, // SUB8rr 0U, // SUB8rr_REV 0U, // SUBPDrm 0U, // SUBPDrr 0U, // SUBPSrm 0U, // SUBPSrr 0U, // SUBR_F32m 0U, // SUBR_F64m 0U, // SUBR_FI16m 0U, // SUBR_FI32m 0U, // SUBR_FPrST0 0U, // SUBR_FST0r 0U, // SUBR_Fp32m 0U, // SUBR_Fp64m 0U, // SUBR_Fp64m32 0U, // SUBR_Fp80m32 0U, // SUBR_Fp80m64 0U, // SUBR_FpI16m32 0U, // SUBR_FpI16m64 0U, // SUBR_FpI16m80 0U, // SUBR_FpI32m32 0U, // SUBR_FpI32m64 0U, // SUBR_FpI32m80 0U, // SUBR_FrST0 0U, // SUBSDrm 0U, // SUBSDrm_Int 0U, // SUBSDrr 0U, // SUBSDrr_Int 0U, // SUBSSrm 0U, // SUBSSrm_Int 0U, // SUBSSrr 0U, // SUBSSrr_Int 0U, // SUB_F32m 0U, // SUB_F64m 0U, // SUB_FI16m 0U, // SUB_FI32m 0U, // SUB_FPrST0 0U, // SUB_FST0r 0U, // SUB_Fp32 0U, // SUB_Fp32m 0U, // SUB_Fp64 0U, // SUB_Fp64m 0U, // SUB_Fp64m32 0U, // SUB_Fp80 0U, // SUB_Fp80m32 0U, // SUB_Fp80m64 0U, // SUB_FpI16m32 0U, // SUB_FpI16m64 0U, // SUB_FpI16m80 0U, // SUB_FpI32m32 0U, // SUB_FpI32m64 0U, // SUB_FpI32m80 0U, // SUB_FrST0 0U, // SWAPGS 0U, // SYSCALL 0U, // SYSENTER 0U, // SYSEXIT 0U, // SYSEXIT64 0U, // SYSRET 0U, // SYSRET64 0U, // T1MSKC32rm 0U, // T1MSKC32rr 0U, // T1MSKC64rm 0U, // T1MSKC64rr 0U, // TEST16i16 0U, // TEST16mi 0U, // TEST16mi_alt 0U, // TEST16mr 0U, // TEST16ri 0U, // TEST16ri_alt 0U, // TEST16rr 0U, // TEST32i32 0U, // TEST32mi 0U, // TEST32mi_alt 0U, // TEST32mr 0U, // TEST32ri 0U, // TEST32ri_alt 0U, // TEST32rr 0U, // TEST64i32 0U, // TEST64mi32 0U, // TEST64mi32_alt 0U, // TEST64mr 0U, // TEST64ri32 0U, // TEST64ri32_alt 0U, // TEST64rr 0U, // TEST8i8 0U, // TEST8mi 0U, // TEST8mi_alt 0U, // TEST8mr 0U, // TEST8ri 0U, // TEST8ri_alt 0U, // TEST8rr 0U, // TPAUSE 0U, // TST_F 0U, // TST_Fp32 0U, // TST_Fp64 0U, // TST_Fp80 0U, // TZCNT16rm 0U, // TZCNT16rr 0U, // TZCNT32rm 0U, // TZCNT32rr 0U, // TZCNT64rm 0U, // TZCNT64rr 0U, // TZMSK32rm 0U, // TZMSK32rr 0U, // TZMSK64rm 0U, // TZMSK64rr 0U, // UCOMISDrm 0U, // UCOMISDrm_Int 0U, // UCOMISDrr 0U, // UCOMISDrr_Int 0U, // UCOMISSrm 0U, // UCOMISSrm_Int 0U, // UCOMISSrr 0U, // UCOMISSrr_Int 0U, // UCOM_FIPr 0U, // UCOM_FIr 0U, // UCOM_FPPr 0U, // UCOM_FPr 0U, // UCOM_FpIr32 0U, // UCOM_FpIr64 0U, // UCOM_FpIr80 0U, // UCOM_Fpr32 0U, // UCOM_Fpr64 0U, // UCOM_Fpr80 0U, // UCOM_Fr 0U, // UD0 0U, // UD1 0U, // UD2 0U, // UMONITOR16 0U, // UMONITOR32 0U, // UMONITOR64 0U, // UMWAIT 0U, // UNPCKHPDrm 0U, // UNPCKHPDrr 0U, // UNPCKHPSrm 0U, // UNPCKHPSrr 0U, // UNPCKLPDrm 0U, // UNPCKLPDrr 0U, // UNPCKLPSrm 0U, // UNPCKLPSrr 256U, // V4FMADDPSrm 35108U, // V4FMADDPSrmk 35108U, // V4FMADDPSrmkz 256U, // V4FMADDSSrm 35108U, // V4FMADDSSrmk 35108U, // V4FMADDSSrmkz 256U, // V4FNMADDPSrm 35108U, // V4FNMADDPSrmk 35108U, // V4FNMADDPSrmkz 256U, // V4FNMADDSSrm 35108U, // V4FNMADDSSrmk 35108U, // V4FNMADDSSrmkz 320U, // VADDPDYrm 96U, // VADDPDYrr 352U, // VADDPDZ128rm 4480U, // VADDPDZ128rmb 1116452U, // VADDPDZ128rmbk 1149028U, // VADDPDZ128rmbkz 35108U, // VADDPDZ128rmk 133220U, // VADDPDZ128rmkz 96U, // VADDPDZ128rr 166180U, // VADDPDZ128rrk 198756U, // VADDPDZ128rrkz 320U, // VADDPDZ256rm 6528U, // VADDPDZ256rmb 2165028U, // VADDPDZ256rmbk 2197604U, // VADDPDZ256rmbkz 231716U, // VADDPDZ256rmk 264292U, // VADDPDZ256rmkz 96U, // VADDPDZ256rr 166180U, // VADDPDZ256rrk 198756U, // VADDPDZ256rrkz 416U, // VADDPDZrm 8576U, // VADDPDZrmb 3213604U, // VADDPDZrmbk 3246180U, // VADDPDZrmbkz 297252U, // VADDPDZrmk 329828U, // VADDPDZrmkz 96U, // VADDPDZrr 362592U, // VADDPDZrrb 4360484U, // VADDPDZrrbk 21170276U, // VADDPDZrrbkz 166180U, // VADDPDZrrk 198756U, // VADDPDZrrkz 352U, // VADDPDrm 96U, // VADDPDrr 320U, // VADDPSYrm 96U, // VADDPSYrr 352U, // VADDPSZ128rm 6592U, // VADDPSZ128rmb 2492708U, // VADDPSZ128rmbk 2525284U, // VADDPSZ128rmbkz 35108U, // VADDPSZ128rmk 133220U, // VADDPSZ128rmkz 96U, // VADDPSZ128rr 166180U, // VADDPSZ128rrk 198756U, // VADDPSZ128rrkz 320U, // VADDPSZ256rm 8640U, // VADDPSZ256rmb 3541284U, // VADDPSZ256rmbk 3573860U, // VADDPSZ256rmbkz 231716U, // VADDPSZ256rmk 264292U, // VADDPSZ256rmkz 96U, // VADDPSZ256rr 166180U, // VADDPSZ256rrk 198756U, // VADDPSZ256rrkz 416U, // VADDPSZrm 10688U, // VADDPSZrmb 5638436U, // VADDPSZrmbk 5671012U, // VADDPSZrmbkz 297252U, // VADDPSZrmk 329828U, // VADDPSZrmkz 96U, // VADDPSZrr 362592U, // VADDPSZrrb 4360484U, // VADDPSZrrbk 21170276U, // VADDPSZrrbkz 166180U, // VADDPSZrrk 198756U, // VADDPSZrrkz 352U, // VADDPSrm 96U, // VADDPSrr 384U, // VADDSDZrm 384U, // VADDSDZrm_Int 67876U, // VADDSDZrm_Intk 100452U, // VADDSDZrm_Intkz 96U, // VADDSDZrr 96U, // VADDSDZrr_Int 166180U, // VADDSDZrr_Intk 198756U, // VADDSDZrr_Intkz 362592U, // VADDSDZrrb_Int 4360484U, // VADDSDZrrb_Intk 21170276U, // VADDSDZrrb_Intkz 384U, // VADDSDrm 384U, // VADDSDrm_Int 96U, // VADDSDrr 96U, // VADDSDrr_Int 448U, // VADDSSZrm 448U, // VADDSSZrm_Int 395556U, // VADDSSZrm_Intk 428132U, // VADDSSZrm_Intkz 96U, // VADDSSZrr 96U, // VADDSSZrr_Int 166180U, // VADDSSZrr_Intk 198756U, // VADDSSZrr_Intkz 362592U, // VADDSSZrrb_Int 4360484U, // VADDSSZrrb_Intk 21170276U, // VADDSSZrrb_Intkz 448U, // VADDSSrm 448U, // VADDSSrm_Int 96U, // VADDSSrr 96U, // VADDSSrr_Int 320U, // VADDSUBPDYrm 96U, // VADDSUBPDYrr 352U, // VADDSUBPDrm 96U, // VADDSUBPDrr 320U, // VADDSUBPSYrm 96U, // VADDSUBPSYrr 352U, // VADDSUBPSrm 96U, // VADDSUBPSrr 480U, // VAESDECLASTYrm 96U, // VAESDECLASTYrr 512U, // VAESDECLASTZ128rm 96U, // VAESDECLASTZ128rr 480U, // VAESDECLASTZ256rm 96U, // VAESDECLASTZ256rr 544U, // VAESDECLASTZrm 96U, // VAESDECLASTZrr 512U, // VAESDECLASTrm 96U, // VAESDECLASTrr 480U, // VAESDECYrm 96U, // VAESDECYrr 512U, // VAESDECZ128rm 96U, // VAESDECZ128rr 480U, // VAESDECZ256rm 96U, // VAESDECZ256rr 544U, // VAESDECZrm 96U, // VAESDECZrr 512U, // VAESDECrm 96U, // VAESDECrr 480U, // VAESENCLASTYrm 96U, // VAESENCLASTYrr 512U, // VAESENCLASTZ128rm 96U, // VAESENCLASTZ128rr 480U, // VAESENCLASTZ256rm 96U, // VAESENCLASTZ256rr 544U, // VAESENCLASTZrm 96U, // VAESENCLASTZrr 512U, // VAESENCLASTrm 96U, // VAESENCLASTrr 480U, // VAESENCYrm 96U, // VAESENCYrr 512U, // VAESENCZ128rm 96U, // VAESENCZ128rr 480U, // VAESENCZ256rm 96U, // VAESENCZ256rr 544U, // VAESENCZrm 96U, // VAESENCZrr 512U, // VAESENCrm 96U, // VAESENCrr 0U, // VAESIMCrm 0U, // VAESIMCrr 0U, // VAESKEYGENASSIST128rm 32U, // VAESKEYGENASSIST128rr 471104U, // VALIGNDZ128rmbi 40339748U, // VALIGNDZ128rmbik 57149540U, // VALIGNDZ128rmbikz 461312U, // VALIGNDZ128rmi 38308132U, // VALIGNDZ128rmik 55117924U, // VALIGNDZ128rmikz 624736U, // VALIGNDZ128rri 71469348U, // VALIGNDZ128rrik 88279140U, // VALIGNDZ128rrikz 473152U, // VALIGNDZ256rmbi 41388324U, // VALIGNDZ256rmbik 58198116U, // VALIGNDZ256rmbikz 461280U, // VALIGNDZ256rmi 38406436U, // VALIGNDZ256rmik 55216228U, // VALIGNDZ256rmikz 624736U, // VALIGNDZ256rri 71469348U, // VALIGNDZ256rrik 88279140U, // VALIGNDZ256rrikz 475200U, // VALIGNDZrmbi 42436900U, // VALIGNDZrmbik 59246692U, // VALIGNDZrmbikz 461344U, // VALIGNDZrmi 38471972U, // VALIGNDZrmik 55281764U, // VALIGNDZrmikz 624736U, // VALIGNDZrri 71469348U, // VALIGNDZrrik 88279140U, // VALIGNDZrrikz 477312U, // VALIGNQZ128rmbi 43780388U, // VALIGNQZ128rmbik 60590180U, // VALIGNQZ128rmbikz 461312U, // VALIGNQZ128rmi 38308132U, // VALIGNQZ128rmik 55117924U, // VALIGNQZ128rmikz 624736U, // VALIGNQZ128rri 71469348U, // VALIGNQZ128rrik 88279140U, // VALIGNQZ128rrikz 471168U, // VALIGNQZ256rmbi 40634660U, // VALIGNQZ256rmbik 57444452U, // VALIGNQZ256rmbikz 461280U, // VALIGNQZ256rmi 38406436U, // VALIGNQZ256rmik 55216228U, // VALIGNQZ256rmikz 624736U, // VALIGNQZ256rri 71469348U, // VALIGNQZ256rrik 88279140U, // VALIGNQZ256rrikz 473216U, // VALIGNQZrmbi 41683236U, // VALIGNQZrmbik 58493028U, // VALIGNQZrmbikz 461344U, // VALIGNQZrmi 38471972U, // VALIGNQZrmik 55281764U, // VALIGNQZrmikz 624736U, // VALIGNQZrri 71469348U, // VALIGNQZrrik 88279140U, // VALIGNQZrrikz 320U, // VANDNPDYrm 96U, // VANDNPDYrr 352U, // VANDNPDZ128rm 4480U, // VANDNPDZ128rmb 1116452U, // VANDNPDZ128rmbk 1149028U, // VANDNPDZ128rmbkz 35108U, // VANDNPDZ128rmk 133220U, // VANDNPDZ128rmkz 96U, // VANDNPDZ128rr 166180U, // VANDNPDZ128rrk 198756U, // VANDNPDZ128rrkz 320U, // VANDNPDZ256rm 6528U, // VANDNPDZ256rmb 2165028U, // VANDNPDZ256rmbk 2197604U, // VANDNPDZ256rmbkz 231716U, // VANDNPDZ256rmk 264292U, // VANDNPDZ256rmkz 96U, // VANDNPDZ256rr 166180U, // VANDNPDZ256rrk 198756U, // VANDNPDZ256rrkz 416U, // VANDNPDZrm 8576U, // VANDNPDZrmb 3213604U, // VANDNPDZrmbk 3246180U, // VANDNPDZrmbkz 297252U, // VANDNPDZrmk 329828U, // VANDNPDZrmkz 96U, // VANDNPDZrr 166180U, // VANDNPDZrrk 198756U, // VANDNPDZrrkz 352U, // VANDNPDrm 96U, // VANDNPDrr 320U, // VANDNPSYrm 96U, // VANDNPSYrr 352U, // VANDNPSZ128rm 6592U, // VANDNPSZ128rmb 2492708U, // VANDNPSZ128rmbk 2525284U, // VANDNPSZ128rmbkz 35108U, // VANDNPSZ128rmk 133220U, // VANDNPSZ128rmkz 96U, // VANDNPSZ128rr 166180U, // VANDNPSZ128rrk 198756U, // VANDNPSZ128rrkz 320U, // VANDNPSZ256rm 8640U, // VANDNPSZ256rmb 3541284U, // VANDNPSZ256rmbk 3573860U, // VANDNPSZ256rmbkz 231716U, // VANDNPSZ256rmk 264292U, // VANDNPSZ256rmkz 96U, // VANDNPSZ256rr 166180U, // VANDNPSZ256rrk 198756U, // VANDNPSZ256rrkz 416U, // VANDNPSZrm 10688U, // VANDNPSZrmb 5638436U, // VANDNPSZrmbk 5671012U, // VANDNPSZrmbkz 297252U, // VANDNPSZrmk 329828U, // VANDNPSZrmkz 96U, // VANDNPSZrr 166180U, // VANDNPSZrrk 198756U, // VANDNPSZrrkz 352U, // VANDNPSrm 96U, // VANDNPSrr 320U, // VANDPDYrm 96U, // VANDPDYrr 352U, // VANDPDZ128rm 4480U, // VANDPDZ128rmb 1116452U, // VANDPDZ128rmbk 1149028U, // VANDPDZ128rmbkz 35108U, // VANDPDZ128rmk 133220U, // VANDPDZ128rmkz 96U, // VANDPDZ128rr 166180U, // VANDPDZ128rrk 198756U, // VANDPDZ128rrkz 320U, // VANDPDZ256rm 6528U, // VANDPDZ256rmb 2165028U, // VANDPDZ256rmbk 2197604U, // VANDPDZ256rmbkz 231716U, // VANDPDZ256rmk 264292U, // VANDPDZ256rmkz 96U, // VANDPDZ256rr 166180U, // VANDPDZ256rrk 198756U, // VANDPDZ256rrkz 416U, // VANDPDZrm 8576U, // VANDPDZrmb 3213604U, // VANDPDZrmbk 3246180U, // VANDPDZrmbkz 297252U, // VANDPDZrmk 329828U, // VANDPDZrmkz 96U, // VANDPDZrr 166180U, // VANDPDZrrk 198756U, // VANDPDZrrkz 352U, // VANDPDrm 96U, // VANDPDrr 320U, // VANDPSYrm 96U, // VANDPSYrr 352U, // VANDPSZ128rm 6592U, // VANDPSZ128rmb 2492708U, // VANDPSZ128rmbk 2525284U, // VANDPSZ128rmbkz 35108U, // VANDPSZ128rmk 133220U, // VANDPSZ128rmkz 96U, // VANDPSZ128rr 166180U, // VANDPSZ128rrk 198756U, // VANDPSZ128rrkz 320U, // VANDPSZ256rm 8640U, // VANDPSZ256rmb 3541284U, // VANDPSZ256rmbk 3573860U, // VANDPSZ256rmbkz 231716U, // VANDPSZ256rmk 264292U, // VANDPSZ256rmkz 96U, // VANDPSZ256rr 166180U, // VANDPSZ256rrk 198756U, // VANDPSZ256rrkz 416U, // VANDPSZrm 10688U, // VANDPSZrmb 5638436U, // VANDPSZrmbk 5671012U, // VANDPSZrmbkz 297252U, // VANDPSZrmk 329828U, // VANDPSZrmkz 96U, // VANDPSZrr 166180U, // VANDPSZrrk 198756U, // VANDPSZrrkz 352U, // VANDPSrm 96U, // VANDPSrr 352U, // VBLENDMPDZ128rm 4480U, // VBLENDMPDZ128rmb 1149028U, // VBLENDMPDZ128rmbk 1149028U, // VBLENDMPDZ128rmbkz 133220U, // VBLENDMPDZ128rmk 133220U, // VBLENDMPDZ128rmkz 96U, // VBLENDMPDZ128rr 198756U, // VBLENDMPDZ128rrk 198756U, // VBLENDMPDZ128rrkz 320U, // VBLENDMPDZ256rm 6528U, // VBLENDMPDZ256rmb 2197604U, // VBLENDMPDZ256rmbk 2197604U, // VBLENDMPDZ256rmbkz 264292U, // VBLENDMPDZ256rmk 264292U, // VBLENDMPDZ256rmkz 96U, // VBLENDMPDZ256rr 198756U, // VBLENDMPDZ256rrk 198756U, // VBLENDMPDZ256rrkz 416U, // VBLENDMPDZrm 8576U, // VBLENDMPDZrmb 3246180U, // VBLENDMPDZrmbk 3246180U, // VBLENDMPDZrmbkz 329828U, // VBLENDMPDZrmk 329828U, // VBLENDMPDZrmkz 96U, // VBLENDMPDZrr 198756U, // VBLENDMPDZrrk 198756U, // VBLENDMPDZrrkz 352U, // VBLENDMPSZ128rm 6592U, // VBLENDMPSZ128rmb 2525284U, // VBLENDMPSZ128rmbk 2525284U, // VBLENDMPSZ128rmbkz 133220U, // VBLENDMPSZ128rmk 133220U, // VBLENDMPSZ128rmkz 96U, // VBLENDMPSZ128rr 198756U, // VBLENDMPSZ128rrk 198756U, // VBLENDMPSZ128rrkz 320U, // VBLENDMPSZ256rm 8640U, // VBLENDMPSZ256rmb 3573860U, // VBLENDMPSZ256rmbk 3573860U, // VBLENDMPSZ256rmbkz 264292U, // VBLENDMPSZ256rmk 264292U, // VBLENDMPSZ256rmkz 96U, // VBLENDMPSZ256rr 198756U, // VBLENDMPSZ256rrk 198756U, // VBLENDMPSZ256rrkz 416U, // VBLENDMPSZrm 10688U, // VBLENDMPSZrmb 5671012U, // VBLENDMPSZrmbk 5671012U, // VBLENDMPSZrmbkz 329828U, // VBLENDMPSZrmk 329828U, // VBLENDMPSZrmkz 96U, // VBLENDMPSZrr 198756U, // VBLENDMPSZrrk 198756U, // VBLENDMPSZrrkz 461120U, // VBLENDPDYrmi 624736U, // VBLENDPDYrri 461152U, // VBLENDPDrmi 624736U, // VBLENDPDrri 461120U, // VBLENDPSYrmi 624736U, // VBLENDPSYrri 461152U, // VBLENDPSrmi 624736U, // VBLENDPSrri 854336U, // VBLENDVPDYrm 198752U, // VBLENDVPDYrr 854368U, // VBLENDVPDrm 198752U, // VBLENDVPDrr 854336U, // VBLENDVPSYrm 198752U, // VBLENDVPSYrr 854368U, // VBLENDVPSrm 198752U, // VBLENDVPSrr 0U, // VBROADCASTF128 0U, // VBROADCASTF32X2Z256m 580U, // VBROADCASTF32X2Z256mk 388U, // VBROADCASTF32X2Z256mkz 0U, // VBROADCASTF32X2Z256r 292U, // VBROADCASTF32X2Z256rk 100U, // VBROADCASTF32X2Z256rkz 0U, // VBROADCASTF32X2Zm 580U, // VBROADCASTF32X2Zmk 388U, // VBROADCASTF32X2Zmkz 0U, // VBROADCASTF32X2Zr 292U, // VBROADCASTF32X2Zrk 100U, // VBROADCASTF32X2Zrkz 0U, // VBROADCASTF32X4Z256rm 260U, // VBROADCASTF32X4Z256rmk 356U, // VBROADCASTF32X4Z256rmkz 0U, // VBROADCASTF32X4rm 260U, // VBROADCASTF32X4rmk 356U, // VBROADCASTF32X4rmkz 0U, // VBROADCASTF32X8rm 612U, // VBROADCASTF32X8rmk 324U, // VBROADCASTF32X8rmkz 0U, // VBROADCASTF64X2Z128rm 260U, // VBROADCASTF64X2Z128rmk 356U, // VBROADCASTF64X2Z128rmkz 0U, // VBROADCASTF64X2rm 260U, // VBROADCASTF64X2rmk 356U, // VBROADCASTF64X2rmkz 0U, // VBROADCASTF64X4rm 612U, // VBROADCASTF64X4rmk 324U, // VBROADCASTF64X4rmkz 0U, // VBROADCASTI128 0U, // VBROADCASTI32X2Z128m 644U, // VBROADCASTI32X2Z128mk 132U, // VBROADCASTI32X2Z128mkz 0U, // VBROADCASTI32X2Z128r 292U, // VBROADCASTI32X2Z128rk 100U, // VBROADCASTI32X2Z128rkz 0U, // VBROADCASTI32X2Z256m 644U, // VBROADCASTI32X2Z256mk 132U, // VBROADCASTI32X2Z256mkz 0U, // VBROADCASTI32X2Z256r 292U, // VBROADCASTI32X2Z256rk 100U, // VBROADCASTI32X2Z256rkz 0U, // VBROADCASTI32X2Zm 644U, // VBROADCASTI32X2Zmk 132U, // VBROADCASTI32X2Zmkz 0U, // VBROADCASTI32X2Zr 292U, // VBROADCASTI32X2Zrk 100U, // VBROADCASTI32X2Zrkz 0U, // VBROADCASTI32X4Z256rm 676U, // VBROADCASTI32X4Z256rmk 516U, // VBROADCASTI32X4Z256rmkz 0U, // VBROADCASTI32X4rm 676U, // VBROADCASTI32X4rmk 516U, // VBROADCASTI32X4rmkz 0U, // VBROADCASTI32X8rm 708U, // VBROADCASTI32X8rmk 484U, // VBROADCASTI32X8rmkz 0U, // VBROADCASTI64X2Z128rm 676U, // VBROADCASTI64X2Z128rmk 516U, // VBROADCASTI64X2Z128rmkz 0U, // VBROADCASTI64X2rm 676U, // VBROADCASTI64X2rmk 516U, // VBROADCASTI64X2rmkz 0U, // VBROADCASTI64X4rm 708U, // VBROADCASTI64X4rmk 484U, // VBROADCASTI64X4rmkz 0U, // VBROADCASTSDYrm 0U, // VBROADCASTSDYrr 0U, // VBROADCASTSDZ256m 580U, // VBROADCASTSDZ256mk 388U, // VBROADCASTSDZ256mkz 0U, // VBROADCASTSDZ256r 292U, // VBROADCASTSDZ256rk 100U, // VBROADCASTSDZ256rkz 0U, // VBROADCASTSDZm 580U, // VBROADCASTSDZmk 388U, // VBROADCASTSDZmkz 0U, // VBROADCASTSDZr 292U, // VBROADCASTSDZrk 100U, // VBROADCASTSDZrkz 0U, // VBROADCASTSSYrm 0U, // VBROADCASTSSYrr 0U, // VBROADCASTSSZ128m 740U, // VBROADCASTSSZ128mk 452U, // VBROADCASTSSZ128mkz 0U, // VBROADCASTSSZ128r 292U, // VBROADCASTSSZ128rk 100U, // VBROADCASTSSZ128rkz 0U, // VBROADCASTSSZ256m 740U, // VBROADCASTSSZ256mk 452U, // VBROADCASTSSZ256mkz 0U, // VBROADCASTSSZ256r 292U, // VBROADCASTSSZ256rk 100U, // VBROADCASTSSZ256rkz 0U, // VBROADCASTSSZm 740U, // VBROADCASTSSZmk 452U, // VBROADCASTSSZmkz 0U, // VBROADCASTSSZr 292U, // VBROADCASTSSZrk 100U, // VBROADCASTSSZrkz 0U, // VBROADCASTSSrm 0U, // VBROADCASTSSrr 325U, // VCMPPDYrmi 461120U, // VCMPPDYrmi_alt 101U, // VCMPPDYrri 624736U, // VCMPPDYrri_alt 4485U, // VCMPPDZ128rmbi 477568U, // VCMPPDZ128rmbi_alt 59869284U, // VCMPPDZ128rmbi_altk 773U, // VCMPPDZ128rmbik 357U, // VCMPPDZ128rmi 461152U, // VCMPPDZ128rmi_alt 54659172U, // VCMPPDZ128rmi_altk 6U, // VCMPPDZ128rmik 101U, // VCMPPDZ128rri 624736U, // VCMPPDZ128rri_alt 88279140U, // VCMPPDZ128rri_altk 806U, // VCMPPDZ128rrik 6533U, // VCMPPDZ256rmbi 471424U, // VCMPPDZ256rmbi_alt 56723556U, // VCMPPDZ256rmbi_altk 837U, // VCMPPDZ256rmbik 325U, // VCMPPDZ256rmi 461120U, // VCMPPDZ256rmi_alt 54790244U, // VCMPPDZ256rmi_altk 7U, // VCMPPDZ256rmik 101U, // VCMPPDZ256rri 624736U, // VCMPPDZ256rri_alt 88279140U, // VCMPPDZ256rri_altk 806U, // VCMPPDZ256rrik 8581U, // VCMPPDZrmbi 473472U, // VCMPPDZrmbi_alt 57772132U, // VCMPPDZrmbi_altk 869U, // VCMPPDZrmbik 421U, // VCMPPDZrmi 461216U, // VCMPPDZrmi_alt 54855780U, // VCMPPDZrmi_altk 7U, // VCMPPDZrmik 101U, // VCMPPDZrri 624736U, // VCMPPDZrri_alt 88279140U, // VCMPPDZrri_altk 20581U, // VCMPPDZrrib 645216U, // VCMPPDZrrib_alt 94570596U, // VCMPPDZrrib_altk 902U, // VCMPPDZrribk 806U, // VCMPPDZrrik 357U, // VCMPPDrmi 461152U, // VCMPPDrmi_alt 101U, // VCMPPDrri 624736U, // VCMPPDrri_alt 325U, // VCMPPSYrmi 461120U, // VCMPPSYrmi_alt 101U, // VCMPPSYrri 624736U, // VCMPPSYrri_alt 6597U, // VCMPPSZ128rmbi 471488U, // VCMPPSZ128rmbi_alt 57051236U, // VCMPPSZ128rmbi_altk 840U, // VCMPPSZ128rmbik 357U, // VCMPPSZ128rmi 461152U, // VCMPPSZ128rmi_alt 54659172U, // VCMPPSZ128rmi_altk 6U, // VCMPPSZ128rmik 101U, // VCMPPSZ128rri 624736U, // VCMPPSZ128rri_alt 88279140U, // VCMPPSZ128rri_altk 806U, // VCMPPSZ128rrik 8645U, // VCMPPSZ256rmbi 473536U, // VCMPPSZ256rmbi_alt 58099812U, // VCMPPSZ256rmbi_altk 872U, // VCMPPSZ256rmbik 325U, // VCMPPSZ256rmi 461120U, // VCMPPSZ256rmi_alt 54790244U, // VCMPPSZ256rmi_altk 7U, // VCMPPSZ256rmik 101U, // VCMPPSZ256rri 624736U, // VCMPPSZ256rri_alt 88279140U, // VCMPPSZ256rri_altk 806U, // VCMPPSZ256rrik 10693U, // VCMPPSZrmbi 475584U, // VCMPPSZrmbi_alt 59148388U, // VCMPPSZrmbi_altk 936U, // VCMPPSZrmbik 421U, // VCMPPSZrmi 461216U, // VCMPPSZrmi_alt 54855780U, // VCMPPSZrmi_altk 7U, // VCMPPSZrmik 101U, // VCMPPSZrri 624736U, // VCMPPSZrri_alt 88279140U, // VCMPPSZrri_altk 20581U, // VCMPPSZrrib 645216U, // VCMPPSZrrib_alt 94570596U, // VCMPPSZrrib_altk 902U, // VCMPPSZrribk 806U, // VCMPPSZrrik 357U, // VCMPPSrmi 461152U, // VCMPPSrmi_alt 101U, // VCMPPSrri 624736U, // VCMPPSrri_alt 389U, // VCMPSDZrm 389U, // VCMPSDZrm_Int 805U, // VCMPSDZrm_Intk 461184U, // VCMPSDZrmi_alt 54626404U, // VCMPSDZrmi_altk 101U, // VCMPSDZrr 101U, // VCMPSDZrr_Int 806U, // VCMPSDZrr_Intk 20581U, // VCMPSDZrrb_Int 902U, // VCMPSDZrrb_Intk 645216U, // VCMPSDZrrb_alt 94570596U, // VCMPSDZrrb_altk 624736U, // VCMPSDZrri_alt 88279140U, // VCMPSDZrri_altk 389U, // VCMPSDrm 389U, // VCMPSDrm_Int 461184U, // VCMPSDrm_alt 101U, // VCMPSDrr 101U, // VCMPSDrr_Int 624736U, // VCMPSDrr_alt 453U, // VCMPSSZrm 453U, // VCMPSSZrm_Int 808U, // VCMPSSZrm_Intk 461248U, // VCMPSSZrmi_alt 54954084U, // VCMPSSZrmi_altk 101U, // VCMPSSZrr 101U, // VCMPSSZrr_Int 806U, // VCMPSSZrr_Intk 20581U, // VCMPSSZrrb_Int 902U, // VCMPSSZrrb_Intk 645216U, // VCMPSSZrrb_alt 94570596U, // VCMPSSZrrb_altk 624736U, // VCMPSSZrri_alt 88279140U, // VCMPSSZrri_altk 453U, // VCMPSSrm 453U, // VCMPSSrm_Int 461248U, // VCMPSSrm_alt 101U, // VCMPSSrr 101U, // VCMPSSrr_Int 624736U, // VCMPSSrr_alt 0U, // VCOMISDZrm 0U, // VCOMISDZrm_Int 0U, // VCOMISDZrr 0U, // VCOMISDZrr_Int 8U, // VCOMISDZrrb 0U, // VCOMISDrm 0U, // VCOMISDrm_Int 0U, // VCOMISDrr 0U, // VCOMISDrr_Int 0U, // VCOMISSZrm 0U, // VCOMISSZrm_Int 0U, // VCOMISSZrr 0U, // VCOMISSZrr_Int 8U, // VCOMISSZrrb 0U, // VCOMISSrm 0U, // VCOMISSrm_Int 0U, // VCOMISSrr 0U, // VCOMISSrr_Int 0U, // VCOMPRESSPDZ128mr 164U, // VCOMPRESSPDZ128mrk 0U, // VCOMPRESSPDZ128rr 292U, // VCOMPRESSPDZ128rrk 100U, // VCOMPRESSPDZ128rrkz 0U, // VCOMPRESSPDZ256mr 164U, // VCOMPRESSPDZ256mrk 0U, // VCOMPRESSPDZ256rr 292U, // VCOMPRESSPDZ256rrk 100U, // VCOMPRESSPDZ256rrkz 0U, // VCOMPRESSPDZmr 164U, // VCOMPRESSPDZmrk 0U, // VCOMPRESSPDZrr 292U, // VCOMPRESSPDZrrk 100U, // VCOMPRESSPDZrrkz 0U, // VCOMPRESSPSZ128mr 164U, // VCOMPRESSPSZ128mrk 0U, // VCOMPRESSPSZ128rr 292U, // VCOMPRESSPSZ128rrk 100U, // VCOMPRESSPSZ128rrkz 0U, // VCOMPRESSPSZ256mr 164U, // VCOMPRESSPSZ256mrk 0U, // VCOMPRESSPSZ256rr 292U, // VCOMPRESSPSZ256rrk 100U, // VCOMPRESSPSZ256rrkz 0U, // VCOMPRESSPSZmr 164U, // VCOMPRESSPSZmrk 0U, // VCOMPRESSPSZrr 292U, // VCOMPRESSPSZrrk 100U, // VCOMPRESSPSZrrkz 0U, // VCVTDQ2PDYrm 0U, // VCVTDQ2PDYrr 0U, // VCVTDQ2PDZ128rm 9U, // VCVTDQ2PDZ128rmb 5060U, // VCVTDQ2PDZ128rmbk 4164U, // VCVTDQ2PDZ128rmbkz 644U, // VCVTDQ2PDZ128rmk 132U, // VCVTDQ2PDZ128rmkz 0U, // VCVTDQ2PDZ128rr 292U, // VCVTDQ2PDZ128rrk 100U, // VCVTDQ2PDZ128rrkz 0U, // VCVTDQ2PDZ256rm 9U, // VCVTDQ2PDZ256rmb 7108U, // VCVTDQ2PDZ256rmbk 6212U, // VCVTDQ2PDZ256rmbkz 676U, // VCVTDQ2PDZ256rmk 516U, // VCVTDQ2PDZ256rmkz 0U, // VCVTDQ2PDZ256rr 292U, // VCVTDQ2PDZ256rrk 100U, // VCVTDQ2PDZ256rrkz 0U, // VCVTDQ2PDZrm 10U, // VCVTDQ2PDZrmb 9156U, // VCVTDQ2PDZrmbk 8260U, // VCVTDQ2PDZrmbkz 708U, // VCVTDQ2PDZrmk 484U, // VCVTDQ2PDZrmkz 0U, // VCVTDQ2PDZrr 292U, // VCVTDQ2PDZrrk 100U, // VCVTDQ2PDZrrkz 0U, // VCVTDQ2PDrm 0U, // VCVTDQ2PDrr 0U, // VCVTDQ2PSYrm 0U, // VCVTDQ2PSYrr 0U, // VCVTDQ2PSZ128rm 9U, // VCVTDQ2PSZ128rmb 7108U, // VCVTDQ2PSZ128rmbk 6212U, // VCVTDQ2PSZ128rmbkz 676U, // VCVTDQ2PSZ128rmk 516U, // VCVTDQ2PSZ128rmkz 0U, // VCVTDQ2PSZ128rr 292U, // VCVTDQ2PSZ128rrk 100U, // VCVTDQ2PSZ128rrkz 0U, // VCVTDQ2PSZ256rm 10U, // VCVTDQ2PSZ256rmb 9156U, // VCVTDQ2PSZ256rmbk 8260U, // VCVTDQ2PSZ256rmbkz 708U, // VCVTDQ2PSZ256rmk 484U, // VCVTDQ2PSZ256rmkz 0U, // VCVTDQ2PSZ256rr 292U, // VCVTDQ2PSZ256rrk 100U, // VCVTDQ2PSZ256rrkz 0U, // VCVTDQ2PSZrm 10U, // VCVTDQ2PSZrmb 11204U, // VCVTDQ2PSZrmbk 10308U, // VCVTDQ2PSZrmbkz 996U, // VCVTDQ2PSZrmk 548U, // VCVTDQ2PSZrmkz 0U, // VCVTDQ2PSZrr 1024U, // VCVTDQ2PSZrrb 887076U, // VCVTDQ2PSZrrbk 362596U, // VCVTDQ2PSZrrbkz 292U, // VCVTDQ2PSZrrk 100U, // VCVTDQ2PSZrrkz 0U, // VCVTDQ2PSrm 0U, // VCVTDQ2PSrr 0U, // VCVTPD2DQYrm 0U, // VCVTPD2DQYrr 0U, // VCVTPD2DQZ128rm 9U, // VCVTPD2DQZ128rmb 4676U, // VCVTPD2DQZ128rmbk 4484U, // VCVTPD2DQZ128rmbkz 260U, // VCVTPD2DQZ128rmk 356U, // VCVTPD2DQZ128rmkz 0U, // VCVTPD2DQZ128rr 292U, // VCVTPD2DQZ128rrk 100U, // VCVTPD2DQZ128rrkz 0U, // VCVTPD2DQZ256rm 9U, // VCVTPD2DQZ256rmb 6724U, // VCVTPD2DQZ256rmbk 6532U, // VCVTPD2DQZ256rmbkz 612U, // VCVTPD2DQZ256rmk 324U, // VCVTPD2DQZ256rmkz 0U, // VCVTPD2DQZ256rr 292U, // VCVTPD2DQZ256rrk 100U, // VCVTPD2DQZ256rrkz 0U, // VCVTPD2DQZrm 10U, // VCVTPD2DQZrmb 8772U, // VCVTPD2DQZrmbk 8580U, // VCVTPD2DQZrmbkz 1060U, // VCVTPD2DQZrmk 420U, // VCVTPD2DQZrmkz 0U, // VCVTPD2DQZrr 1024U, // VCVTPD2DQZrrb 887076U, // VCVTPD2DQZrrbk 362596U, // VCVTPD2DQZrrbkz 292U, // VCVTPD2DQZrrk 100U, // VCVTPD2DQZrrkz 0U, // VCVTPD2DQrm 0U, // VCVTPD2DQrr 0U, // VCVTPD2PSYrm 0U, // VCVTPD2PSYrr 0U, // VCVTPD2PSZ128rm 9U, // VCVTPD2PSZ128rmb 4676U, // VCVTPD2PSZ128rmbk 4484U, // VCVTPD2PSZ128rmbkz 260U, // VCVTPD2PSZ128rmk 356U, // VCVTPD2PSZ128rmkz 0U, // VCVTPD2PSZ128rr 292U, // VCVTPD2PSZ128rrk 100U, // VCVTPD2PSZ128rrkz 0U, // VCVTPD2PSZ256rm 9U, // VCVTPD2PSZ256rmb 6724U, // VCVTPD2PSZ256rmbk 6532U, // VCVTPD2PSZ256rmbkz 612U, // VCVTPD2PSZ256rmk 324U, // VCVTPD2PSZ256rmkz 0U, // VCVTPD2PSZ256rr 292U, // VCVTPD2PSZ256rrk 100U, // VCVTPD2PSZ256rrkz 0U, // VCVTPD2PSZrm 10U, // VCVTPD2PSZrmb 8772U, // VCVTPD2PSZrmbk 8580U, // VCVTPD2PSZrmbkz 1060U, // VCVTPD2PSZrmk 420U, // VCVTPD2PSZrmkz 0U, // VCVTPD2PSZrr 1024U, // VCVTPD2PSZrrb 887076U, // VCVTPD2PSZrrbk 362596U, // VCVTPD2PSZrrbkz 292U, // VCVTPD2PSZrrk 100U, // VCVTPD2PSZrrkz 0U, // VCVTPD2PSrm 0U, // VCVTPD2PSrr 0U, // VCVTPD2QQZ128rm 9U, // VCVTPD2QQZ128rmb 4676U, // VCVTPD2QQZ128rmbk 4484U, // VCVTPD2QQZ128rmbkz 260U, // VCVTPD2QQZ128rmk 356U, // VCVTPD2QQZ128rmkz 0U, // VCVTPD2QQZ128rr 292U, // VCVTPD2QQZ128rrk 100U, // VCVTPD2QQZ128rrkz 0U, // VCVTPD2QQZ256rm 9U, // VCVTPD2QQZ256rmb 6724U, // VCVTPD2QQZ256rmbk 6532U, // VCVTPD2QQZ256rmbkz 612U, // VCVTPD2QQZ256rmk 324U, // VCVTPD2QQZ256rmkz 0U, // VCVTPD2QQZ256rr 292U, // VCVTPD2QQZ256rrk 100U, // VCVTPD2QQZ256rrkz 0U, // VCVTPD2QQZrm 10U, // VCVTPD2QQZrmb 8772U, // VCVTPD2QQZrmbk 8580U, // VCVTPD2QQZrmbkz 1060U, // VCVTPD2QQZrmk 420U, // VCVTPD2QQZrmkz 0U, // VCVTPD2QQZrr 1024U, // VCVTPD2QQZrrb 887076U, // VCVTPD2QQZrrbk 362596U, // VCVTPD2QQZrrbkz 292U, // VCVTPD2QQZrrk 100U, // VCVTPD2QQZrrkz 0U, // VCVTPD2UDQZ128rm 9U, // VCVTPD2UDQZ128rmb 4676U, // VCVTPD2UDQZ128rmbk 4484U, // VCVTPD2UDQZ128rmbkz 260U, // VCVTPD2UDQZ128rmk 356U, // VCVTPD2UDQZ128rmkz 0U, // VCVTPD2UDQZ128rr 292U, // VCVTPD2UDQZ128rrk 100U, // VCVTPD2UDQZ128rrkz 0U, // VCVTPD2UDQZ256rm 9U, // VCVTPD2UDQZ256rmb 6724U, // VCVTPD2UDQZ256rmbk 6532U, // VCVTPD2UDQZ256rmbkz 612U, // VCVTPD2UDQZ256rmk 324U, // VCVTPD2UDQZ256rmkz 0U, // VCVTPD2UDQZ256rr 292U, // VCVTPD2UDQZ256rrk 100U, // VCVTPD2UDQZ256rrkz 0U, // VCVTPD2UDQZrm 10U, // VCVTPD2UDQZrmb 8772U, // VCVTPD2UDQZrmbk 8580U, // VCVTPD2UDQZrmbkz 1060U, // VCVTPD2UDQZrmk 420U, // VCVTPD2UDQZrmkz 0U, // VCVTPD2UDQZrr 1024U, // VCVTPD2UDQZrrb 887076U, // VCVTPD2UDQZrrbk 362596U, // VCVTPD2UDQZrrbkz 292U, // VCVTPD2UDQZrrk 100U, // VCVTPD2UDQZrrkz 0U, // VCVTPD2UQQZ128rm 9U, // VCVTPD2UQQZ128rmb 4676U, // VCVTPD2UQQZ128rmbk 4484U, // VCVTPD2UQQZ128rmbkz 260U, // VCVTPD2UQQZ128rmk 356U, // VCVTPD2UQQZ128rmkz 0U, // VCVTPD2UQQZ128rr 292U, // VCVTPD2UQQZ128rrk 100U, // VCVTPD2UQQZ128rrkz 0U, // VCVTPD2UQQZ256rm 9U, // VCVTPD2UQQZ256rmb 6724U, // VCVTPD2UQQZ256rmbk 6532U, // VCVTPD2UQQZ256rmbkz 612U, // VCVTPD2UQQZ256rmk 324U, // VCVTPD2UQQZ256rmkz 0U, // VCVTPD2UQQZ256rr 292U, // VCVTPD2UQQZ256rrk 100U, // VCVTPD2UQQZ256rrkz 0U, // VCVTPD2UQQZrm 10U, // VCVTPD2UQQZrmb 8772U, // VCVTPD2UQQZrmbk 8580U, // VCVTPD2UQQZrmbkz 1060U, // VCVTPD2UQQZrmk 420U, // VCVTPD2UQQZrmkz 0U, // VCVTPD2UQQZrr 1024U, // VCVTPD2UQQZrrb 887076U, // VCVTPD2UQQZrrbk 362596U, // VCVTPD2UQQZrrbkz 292U, // VCVTPD2UQQZrrk 100U, // VCVTPD2UQQZrrkz 0U, // VCVTPH2PSYrm 0U, // VCVTPH2PSYrr 0U, // VCVTPH2PSZ128rm 580U, // VCVTPH2PSZ128rmk 388U, // VCVTPH2PSZ128rmkz 0U, // VCVTPH2PSZ128rr 292U, // VCVTPH2PSZ128rrk 100U, // VCVTPH2PSZ128rrkz 0U, // VCVTPH2PSZ256rm 260U, // VCVTPH2PSZ256rmk 356U, // VCVTPH2PSZ256rmkz 0U, // VCVTPH2PSZ256rr 292U, // VCVTPH2PSZ256rrk 100U, // VCVTPH2PSZ256rrkz 0U, // VCVTPH2PSZrm 612U, // VCVTPH2PSZrmk 324U, // VCVTPH2PSZrmkz 0U, // VCVTPH2PSZrr 8U, // VCVTPH2PSZrrb 20772U, // VCVTPH2PSZrrbk 20580U, // VCVTPH2PSZrrbkz 292U, // VCVTPH2PSZrrk 100U, // VCVTPH2PSZrrkz 0U, // VCVTPH2PSrm 0U, // VCVTPH2PSrr 0U, // VCVTPS2DQYrm 0U, // VCVTPS2DQYrr 0U, // VCVTPS2DQZ128rm 9U, // VCVTPS2DQZ128rmb 6884U, // VCVTPS2DQZ128rmbk 6596U, // VCVTPS2DQZ128rmbkz 260U, // VCVTPS2DQZ128rmk 356U, // VCVTPS2DQZ128rmkz 0U, // VCVTPS2DQZ128rr 292U, // VCVTPS2DQZ128rrk 100U, // VCVTPS2DQZ128rrkz 0U, // VCVTPS2DQZ256rm 10U, // VCVTPS2DQZ256rmb 8932U, // VCVTPS2DQZ256rmbk 8644U, // VCVTPS2DQZ256rmbkz 612U, // VCVTPS2DQZ256rmk 324U, // VCVTPS2DQZ256rmkz 0U, // VCVTPS2DQZ256rr 292U, // VCVTPS2DQZ256rrk 100U, // VCVTPS2DQZ256rrkz 0U, // VCVTPS2DQZrm 10U, // VCVTPS2DQZrmb 10980U, // VCVTPS2DQZrmbk 10692U, // VCVTPS2DQZrmbkz 1060U, // VCVTPS2DQZrmk 420U, // VCVTPS2DQZrmkz 0U, // VCVTPS2DQZrr 1024U, // VCVTPS2DQZrrb 887076U, // VCVTPS2DQZrrbk 362596U, // VCVTPS2DQZrrbkz 292U, // VCVTPS2DQZrrk 100U, // VCVTPS2DQZrrkz 0U, // VCVTPS2DQrm 0U, // VCVTPS2DQrr 0U, // VCVTPS2PDYrm 0U, // VCVTPS2PDYrr 0U, // VCVTPS2PDZ128rm 9U, // VCVTPS2PDZ128rmb 4836U, // VCVTPS2PDZ128rmbk 4548U, // VCVTPS2PDZ128rmbkz 580U, // VCVTPS2PDZ128rmk 388U, // VCVTPS2PDZ128rmkz 0U, // VCVTPS2PDZ128rr 292U, // VCVTPS2PDZ128rrk 100U, // VCVTPS2PDZ128rrkz 0U, // VCVTPS2PDZ256rm 9U, // VCVTPS2PDZ256rmb 6884U, // VCVTPS2PDZ256rmbk 6596U, // VCVTPS2PDZ256rmbkz 260U, // VCVTPS2PDZ256rmk 356U, // VCVTPS2PDZ256rmkz 0U, // VCVTPS2PDZ256rr 292U, // VCVTPS2PDZ256rrk 100U, // VCVTPS2PDZ256rrkz 0U, // VCVTPS2PDZrm 10U, // VCVTPS2PDZrmb 8932U, // VCVTPS2PDZrmbk 8644U, // VCVTPS2PDZrmbkz 612U, // VCVTPS2PDZrmk 324U, // VCVTPS2PDZrmkz 0U, // VCVTPS2PDZrr 8U, // VCVTPS2PDZrrb 20772U, // VCVTPS2PDZrrbk 20580U, // VCVTPS2PDZrrbkz 292U, // VCVTPS2PDZrrk 100U, // VCVTPS2PDZrrkz 0U, // VCVTPS2PDrm 0U, // VCVTPS2PDrr 0U, // VCVTPS2PHYmr 32U, // VCVTPS2PHYrr 0U, // VCVTPS2PHZ128mr 460964U, // VCVTPS2PHZ128mrk 32U, // VCVTPS2PHZ128rr 2340U, // VCVTPS2PHZ128rrk 624740U, // VCVTPS2PHZ128rrkz 0U, // VCVTPS2PHZ256mr 460964U, // VCVTPS2PHZ256mrk 32U, // VCVTPS2PHZ256rr 2340U, // VCVTPS2PHZ256rrk 624740U, // VCVTPS2PHZ256rrkz 0U, // VCVTPS2PHZmr 460964U, // VCVTPS2PHZmrk 32U, // VCVTPS2PHZrr 11U, // VCVTPS2PHZrrb 22820U, // VCVTPS2PHZrrbk 645220U, // VCVTPS2PHZrrbkz 2340U, // VCVTPS2PHZrrk 624740U, // VCVTPS2PHZrrkz 0U, // VCVTPS2PHmr 32U, // VCVTPS2PHrr 0U, // VCVTPS2QQZ128rm 9U, // VCVTPS2QQZ128rmb 4836U, // VCVTPS2QQZ128rmbk 4548U, // VCVTPS2QQZ128rmbkz 580U, // VCVTPS2QQZ128rmk 388U, // VCVTPS2QQZ128rmkz 0U, // VCVTPS2QQZ128rr 292U, // VCVTPS2QQZ128rrk 100U, // VCVTPS2QQZ128rrkz 0U, // VCVTPS2QQZ256rm 9U, // VCVTPS2QQZ256rmb 6884U, // VCVTPS2QQZ256rmbk 6596U, // VCVTPS2QQZ256rmbkz 260U, // VCVTPS2QQZ256rmk 356U, // VCVTPS2QQZ256rmkz 0U, // VCVTPS2QQZ256rr 292U, // VCVTPS2QQZ256rrk 100U, // VCVTPS2QQZ256rrkz 0U, // VCVTPS2QQZrm 10U, // VCVTPS2QQZrmb 8932U, // VCVTPS2QQZrmbk 8644U, // VCVTPS2QQZrmbkz 612U, // VCVTPS2QQZrmk 324U, // VCVTPS2QQZrmkz 0U, // VCVTPS2QQZrr 1024U, // VCVTPS2QQZrrb 887076U, // VCVTPS2QQZrrbk 362596U, // VCVTPS2QQZrrbkz 292U, // VCVTPS2QQZrrk 100U, // VCVTPS2QQZrrkz 0U, // VCVTPS2UDQZ128rm 9U, // VCVTPS2UDQZ128rmb 6884U, // VCVTPS2UDQZ128rmbk 6596U, // VCVTPS2UDQZ128rmbkz 260U, // VCVTPS2UDQZ128rmk 356U, // VCVTPS2UDQZ128rmkz 0U, // VCVTPS2UDQZ128rr 292U, // VCVTPS2UDQZ128rrk 100U, // VCVTPS2UDQZ128rrkz 0U, // VCVTPS2UDQZ256rm 10U, // VCVTPS2UDQZ256rmb 8932U, // VCVTPS2UDQZ256rmbk 8644U, // VCVTPS2UDQZ256rmbkz 612U, // VCVTPS2UDQZ256rmk 324U, // VCVTPS2UDQZ256rmkz 0U, // VCVTPS2UDQZ256rr 292U, // VCVTPS2UDQZ256rrk 100U, // VCVTPS2UDQZ256rrkz 0U, // VCVTPS2UDQZrm 10U, // VCVTPS2UDQZrmb 10980U, // VCVTPS2UDQZrmbk 10692U, // VCVTPS2UDQZrmbkz 1060U, // VCVTPS2UDQZrmk 420U, // VCVTPS2UDQZrmkz 0U, // VCVTPS2UDQZrr 1024U, // VCVTPS2UDQZrrb 887076U, // VCVTPS2UDQZrrbk 362596U, // VCVTPS2UDQZrrbkz 292U, // VCVTPS2UDQZrrk 100U, // VCVTPS2UDQZrrkz 0U, // VCVTPS2UQQZ128rm 9U, // VCVTPS2UQQZ128rmb 4836U, // VCVTPS2UQQZ128rmbk 4548U, // VCVTPS2UQQZ128rmbkz 580U, // VCVTPS2UQQZ128rmk 388U, // VCVTPS2UQQZ128rmkz 0U, // VCVTPS2UQQZ128rr 292U, // VCVTPS2UQQZ128rrk 100U, // VCVTPS2UQQZ128rrkz 0U, // VCVTPS2UQQZ256rm 9U, // VCVTPS2UQQZ256rmb 6884U, // VCVTPS2UQQZ256rmbk 6596U, // VCVTPS2UQQZ256rmbkz 260U, // VCVTPS2UQQZ256rmk 356U, // VCVTPS2UQQZ256rmkz 0U, // VCVTPS2UQQZ256rr 292U, // VCVTPS2UQQZ256rrk 100U, // VCVTPS2UQQZ256rrkz 0U, // VCVTPS2UQQZrm 10U, // VCVTPS2UQQZrmb 8932U, // VCVTPS2UQQZrmbk 8644U, // VCVTPS2UQQZrmbkz 612U, // VCVTPS2UQQZrmk 324U, // VCVTPS2UQQZrmkz 0U, // VCVTPS2UQQZrr 1024U, // VCVTPS2UQQZrrb 887076U, // VCVTPS2UQQZrrbk 362596U, // VCVTPS2UQQZrrbkz 292U, // VCVTPS2UQQZrrk 100U, // VCVTPS2UQQZrrkz 0U, // VCVTQQ2PDZ128rm 9U, // VCVTQQ2PDZ128rmb 4740U, // VCVTQQ2PDZ128rmbk 4228U, // VCVTQQ2PDZ128rmbkz 676U, // VCVTQQ2PDZ128rmk 516U, // VCVTQQ2PDZ128rmkz 0U, // VCVTQQ2PDZ128rr 292U, // VCVTQQ2PDZ128rrk 100U, // VCVTQQ2PDZ128rrkz 0U, // VCVTQQ2PDZ256rm 9U, // VCVTQQ2PDZ256rmb 6788U, // VCVTQQ2PDZ256rmbk 6276U, // VCVTQQ2PDZ256rmbkz 708U, // VCVTQQ2PDZ256rmk 484U, // VCVTQQ2PDZ256rmkz 0U, // VCVTQQ2PDZ256rr 292U, // VCVTQQ2PDZ256rrk 100U, // VCVTQQ2PDZ256rrkz 0U, // VCVTQQ2PDZrm 10U, // VCVTQQ2PDZrmb 8836U, // VCVTQQ2PDZrmbk 8324U, // VCVTQQ2PDZrmbkz 996U, // VCVTQQ2PDZrmk 548U, // VCVTQQ2PDZrmkz 0U, // VCVTQQ2PDZrr 1024U, // VCVTQQ2PDZrrb 887076U, // VCVTQQ2PDZrrbk 362596U, // VCVTQQ2PDZrrbkz 292U, // VCVTQQ2PDZrrk 100U, // VCVTQQ2PDZrrkz 0U, // VCVTQQ2PSZ128rm 9U, // VCVTQQ2PSZ128rmb 4740U, // VCVTQQ2PSZ128rmbk 4228U, // VCVTQQ2PSZ128rmbkz 676U, // VCVTQQ2PSZ128rmk 516U, // VCVTQQ2PSZ128rmkz 0U, // VCVTQQ2PSZ128rr 292U, // VCVTQQ2PSZ128rrk 100U, // VCVTQQ2PSZ128rrkz 0U, // VCVTQQ2PSZ256rm 9U, // VCVTQQ2PSZ256rmb 6788U, // VCVTQQ2PSZ256rmbk 6276U, // VCVTQQ2PSZ256rmbkz 708U, // VCVTQQ2PSZ256rmk 484U, // VCVTQQ2PSZ256rmkz 0U, // VCVTQQ2PSZ256rr 292U, // VCVTQQ2PSZ256rrk 100U, // VCVTQQ2PSZ256rrkz 0U, // VCVTQQ2PSZrm 10U, // VCVTQQ2PSZrmb 8836U, // VCVTQQ2PSZrmbk 8324U, // VCVTQQ2PSZrmbkz 996U, // VCVTQQ2PSZrmk 548U, // VCVTQQ2PSZrmkz 0U, // VCVTQQ2PSZrr 1024U, // VCVTQQ2PSZrrb 887076U, // VCVTQQ2PSZrrbk 362596U, // VCVTQQ2PSZrrbkz 292U, // VCVTQQ2PSZrrk 100U, // VCVTQQ2PSZrrkz 0U, // VCVTSD2SI64Zrm_Int 0U, // VCVTSD2SI64Zrr_Int 1024U, // VCVTSD2SI64Zrrb_Int 0U, // VCVTSD2SI64rm_Int 0U, // VCVTSD2SI64rr_Int 0U, // VCVTSD2SIZrm_Int 0U, // VCVTSD2SIZrr_Int 1024U, // VCVTSD2SIZrrb_Int 0U, // VCVTSD2SIrm_Int 0U, // VCVTSD2SIrr_Int 384U, // VCVTSD2SSZrm 384U, // VCVTSD2SSZrm_Int 67876U, // VCVTSD2SSZrm_Intk 100452U, // VCVTSD2SSZrm_Intkz 96U, // VCVTSD2SSZrr 96U, // VCVTSD2SSZrr_Int 166180U, // VCVTSD2SSZrr_Intk 198756U, // VCVTSD2SSZrr_Intkz 362592U, // VCVTSD2SSZrrb_Int 4360484U, // VCVTSD2SSZrrb_Intk 21170276U, // VCVTSD2SSZrrb_Intkz 384U, // VCVTSD2SSrm 384U, // VCVTSD2SSrm_Int 96U, // VCVTSD2SSrr 96U, // VCVTSD2SSrr_Int 0U, // VCVTSD2USI64Zrm_Int 0U, // VCVTSD2USI64Zrr_Int 1024U, // VCVTSD2USI64Zrrb_Int 0U, // VCVTSD2USIZrm_Int 0U, // VCVTSD2USIZrr_Int 1024U, // VCVTSD2USIZrrb_Int 64U, // VCVTSI2SDZrm 64U, // VCVTSI2SDZrm_Int 96U, // VCVTSI2SDZrr 96U, // VCVTSI2SDZrr_Int 1088U, // VCVTSI2SDZrrb_Int 64U, // VCVTSI2SDrm 64U, // VCVTSI2SDrm_Int 96U, // VCVTSI2SDrr 96U, // VCVTSI2SDrr_Int 64U, // VCVTSI2SSZrm 64U, // VCVTSI2SSZrm_Int 96U, // VCVTSI2SSZrr 96U, // VCVTSI2SSZrr_Int 1088U, // VCVTSI2SSZrrb_Int 64U, // VCVTSI2SSrm 64U, // VCVTSI2SSrm_Int 96U, // VCVTSI2SSrr 96U, // VCVTSI2SSrr_Int 128U, // VCVTSI642SDZrm 128U, // VCVTSI642SDZrm_Int 96U, // VCVTSI642SDZrr 96U, // VCVTSI642SDZrr_Int 1088U, // VCVTSI642SDZrrb_Int 128U, // VCVTSI642SDrm 128U, // VCVTSI642SDrm_Int 96U, // VCVTSI642SDrr 96U, // VCVTSI642SDrr_Int 128U, // VCVTSI642SSZrm 128U, // VCVTSI642SSZrm_Int 96U, // VCVTSI642SSZrr 96U, // VCVTSI642SSZrr_Int 1088U, // VCVTSI642SSZrrb_Int 128U, // VCVTSI642SSrm 128U, // VCVTSI642SSrm_Int 96U, // VCVTSI642SSrr 96U, // VCVTSI642SSrr_Int 448U, // VCVTSS2SDZrm 448U, // VCVTSS2SDZrm_Int 395556U, // VCVTSS2SDZrm_Intk 428132U, // VCVTSS2SDZrm_Intkz 96U, // VCVTSS2SDZrr 96U, // VCVTSS2SDZrr_Int 166180U, // VCVTSS2SDZrr_Intk 198756U, // VCVTSS2SDZrr_Intkz 20576U, // VCVTSS2SDZrrb_Int 11700516U, // VCVTSS2SDZrrb_Intk 11733092U, // VCVTSS2SDZrrb_Intkz 448U, // VCVTSS2SDrm 448U, // VCVTSS2SDrm_Int 96U, // VCVTSS2SDrr 96U, // VCVTSS2SDrr_Int 0U, // VCVTSS2SI64Zrm_Int 0U, // VCVTSS2SI64Zrr_Int 1024U, // VCVTSS2SI64Zrrb_Int 0U, // VCVTSS2SI64rm_Int 0U, // VCVTSS2SI64rr_Int 0U, // VCVTSS2SIZrm_Int 0U, // VCVTSS2SIZrr_Int 1024U, // VCVTSS2SIZrrb_Int 0U, // VCVTSS2SIrm_Int 0U, // VCVTSS2SIrr_Int 0U, // VCVTSS2USI64Zrm_Int 0U, // VCVTSS2USI64Zrr_Int 1024U, // VCVTSS2USI64Zrrb_Int 0U, // VCVTSS2USIZrm_Int 0U, // VCVTSS2USIZrr_Int 1024U, // VCVTSS2USIZrrb_Int 0U, // VCVTTPD2DQYrm 0U, // VCVTTPD2DQYrr 0U, // VCVTTPD2DQZ128rm 9U, // VCVTTPD2DQZ128rmb 4676U, // VCVTTPD2DQZ128rmbk 4484U, // VCVTTPD2DQZ128rmbkz 260U, // VCVTTPD2DQZ128rmk 356U, // VCVTTPD2DQZ128rmkz 0U, // VCVTTPD2DQZ128rr 292U, // VCVTTPD2DQZ128rrk 100U, // VCVTTPD2DQZ128rrkz 0U, // VCVTTPD2DQZ256rm 9U, // VCVTTPD2DQZ256rmb 6724U, // VCVTTPD2DQZ256rmbk 6532U, // VCVTTPD2DQZ256rmbkz 612U, // VCVTTPD2DQZ256rmk 324U, // VCVTTPD2DQZ256rmkz 0U, // VCVTTPD2DQZ256rr 292U, // VCVTTPD2DQZ256rrk 100U, // VCVTTPD2DQZ256rrkz 0U, // VCVTTPD2DQZrm 10U, // VCVTTPD2DQZrmb 8772U, // VCVTTPD2DQZrmbk 8580U, // VCVTTPD2DQZrmbkz 1060U, // VCVTTPD2DQZrmk 420U, // VCVTTPD2DQZrmkz 0U, // VCVTTPD2DQZrr 8U, // VCVTTPD2DQZrrb 20772U, // VCVTTPD2DQZrrbk 20580U, // VCVTTPD2DQZrrbkz 292U, // VCVTTPD2DQZrrk 100U, // VCVTTPD2DQZrrkz 0U, // VCVTTPD2DQrm 0U, // VCVTTPD2DQrr 0U, // VCVTTPD2QQZ128rm 9U, // VCVTTPD2QQZ128rmb 4676U, // VCVTTPD2QQZ128rmbk 4484U, // VCVTTPD2QQZ128rmbkz 260U, // VCVTTPD2QQZ128rmk 356U, // VCVTTPD2QQZ128rmkz 0U, // VCVTTPD2QQZ128rr 292U, // VCVTTPD2QQZ128rrk 100U, // VCVTTPD2QQZ128rrkz 0U, // VCVTTPD2QQZ256rm 9U, // VCVTTPD2QQZ256rmb 6724U, // VCVTTPD2QQZ256rmbk 6532U, // VCVTTPD2QQZ256rmbkz 612U, // VCVTTPD2QQZ256rmk 324U, // VCVTTPD2QQZ256rmkz 0U, // VCVTTPD2QQZ256rr 292U, // VCVTTPD2QQZ256rrk 100U, // VCVTTPD2QQZ256rrkz 0U, // VCVTTPD2QQZrm 10U, // VCVTTPD2QQZrmb 8772U, // VCVTTPD2QQZrmbk 8580U, // VCVTTPD2QQZrmbkz 1060U, // VCVTTPD2QQZrmk 420U, // VCVTTPD2QQZrmkz 0U, // VCVTTPD2QQZrr 8U, // VCVTTPD2QQZrrb 20772U, // VCVTTPD2QQZrrbk 20580U, // VCVTTPD2QQZrrbkz 292U, // VCVTTPD2QQZrrk 100U, // VCVTTPD2QQZrrkz 0U, // VCVTTPD2UDQZ128rm 9U, // VCVTTPD2UDQZ128rmb 4676U, // VCVTTPD2UDQZ128rmbk 4484U, // VCVTTPD2UDQZ128rmbkz 260U, // VCVTTPD2UDQZ128rmk 356U, // VCVTTPD2UDQZ128rmkz 0U, // VCVTTPD2UDQZ128rr 292U, // VCVTTPD2UDQZ128rrk 100U, // VCVTTPD2UDQZ128rrkz 0U, // VCVTTPD2UDQZ256rm 9U, // VCVTTPD2UDQZ256rmb 6724U, // VCVTTPD2UDQZ256rmbk 6532U, // VCVTTPD2UDQZ256rmbkz 612U, // VCVTTPD2UDQZ256rmk 324U, // VCVTTPD2UDQZ256rmkz 0U, // VCVTTPD2UDQZ256rr 292U, // VCVTTPD2UDQZ256rrk 100U, // VCVTTPD2UDQZ256rrkz 0U, // VCVTTPD2UDQZrm 10U, // VCVTTPD2UDQZrmb 8772U, // VCVTTPD2UDQZrmbk 8580U, // VCVTTPD2UDQZrmbkz 1060U, // VCVTTPD2UDQZrmk 420U, // VCVTTPD2UDQZrmkz 0U, // VCVTTPD2UDQZrr 8U, // VCVTTPD2UDQZrrb 20772U, // VCVTTPD2UDQZrrbk 20580U, // VCVTTPD2UDQZrrbkz 292U, // VCVTTPD2UDQZrrk 100U, // VCVTTPD2UDQZrrkz 0U, // VCVTTPD2UQQZ128rm 9U, // VCVTTPD2UQQZ128rmb 4676U, // VCVTTPD2UQQZ128rmbk 4484U, // VCVTTPD2UQQZ128rmbkz 260U, // VCVTTPD2UQQZ128rmk 356U, // VCVTTPD2UQQZ128rmkz 0U, // VCVTTPD2UQQZ128rr 292U, // VCVTTPD2UQQZ128rrk 100U, // VCVTTPD2UQQZ128rrkz 0U, // VCVTTPD2UQQZ256rm 9U, // VCVTTPD2UQQZ256rmb 6724U, // VCVTTPD2UQQZ256rmbk 6532U, // VCVTTPD2UQQZ256rmbkz 612U, // VCVTTPD2UQQZ256rmk 324U, // VCVTTPD2UQQZ256rmkz 0U, // VCVTTPD2UQQZ256rr 292U, // VCVTTPD2UQQZ256rrk 100U, // VCVTTPD2UQQZ256rrkz 0U, // VCVTTPD2UQQZrm 10U, // VCVTTPD2UQQZrmb 8772U, // VCVTTPD2UQQZrmbk 8580U, // VCVTTPD2UQQZrmbkz 1060U, // VCVTTPD2UQQZrmk 420U, // VCVTTPD2UQQZrmkz 0U, // VCVTTPD2UQQZrr 8U, // VCVTTPD2UQQZrrb 20772U, // VCVTTPD2UQQZrrbk 20580U, // VCVTTPD2UQQZrrbkz 292U, // VCVTTPD2UQQZrrk 100U, // VCVTTPD2UQQZrrkz 0U, // VCVTTPS2DQYrm 0U, // VCVTTPS2DQYrr 0U, // VCVTTPS2DQZ128rm 9U, // VCVTTPS2DQZ128rmb 6884U, // VCVTTPS2DQZ128rmbk 6596U, // VCVTTPS2DQZ128rmbkz 260U, // VCVTTPS2DQZ128rmk 356U, // VCVTTPS2DQZ128rmkz 0U, // VCVTTPS2DQZ128rr 292U, // VCVTTPS2DQZ128rrk 100U, // VCVTTPS2DQZ128rrkz 0U, // VCVTTPS2DQZ256rm 10U, // VCVTTPS2DQZ256rmb 8932U, // VCVTTPS2DQZ256rmbk 8644U, // VCVTTPS2DQZ256rmbkz 612U, // VCVTTPS2DQZ256rmk 324U, // VCVTTPS2DQZ256rmkz 0U, // VCVTTPS2DQZ256rr 292U, // VCVTTPS2DQZ256rrk 100U, // VCVTTPS2DQZ256rrkz 0U, // VCVTTPS2DQZrm 10U, // VCVTTPS2DQZrmb 10980U, // VCVTTPS2DQZrmbk 10692U, // VCVTTPS2DQZrmbkz 1060U, // VCVTTPS2DQZrmk 420U, // VCVTTPS2DQZrmkz 0U, // VCVTTPS2DQZrr 8U, // VCVTTPS2DQZrrb 20772U, // VCVTTPS2DQZrrbk 20580U, // VCVTTPS2DQZrrbkz 292U, // VCVTTPS2DQZrrk 100U, // VCVTTPS2DQZrrkz 0U, // VCVTTPS2DQrm 0U, // VCVTTPS2DQrr 0U, // VCVTTPS2QQZ128rm 9U, // VCVTTPS2QQZ128rmb 4836U, // VCVTTPS2QQZ128rmbk 4548U, // VCVTTPS2QQZ128rmbkz 580U, // VCVTTPS2QQZ128rmk 388U, // VCVTTPS2QQZ128rmkz 0U, // VCVTTPS2QQZ128rr 292U, // VCVTTPS2QQZ128rrk 100U, // VCVTTPS2QQZ128rrkz 0U, // VCVTTPS2QQZ256rm 9U, // VCVTTPS2QQZ256rmb 6884U, // VCVTTPS2QQZ256rmbk 6596U, // VCVTTPS2QQZ256rmbkz 260U, // VCVTTPS2QQZ256rmk 356U, // VCVTTPS2QQZ256rmkz 0U, // VCVTTPS2QQZ256rr 292U, // VCVTTPS2QQZ256rrk 100U, // VCVTTPS2QQZ256rrkz 0U, // VCVTTPS2QQZrm 10U, // VCVTTPS2QQZrmb 8932U, // VCVTTPS2QQZrmbk 8644U, // VCVTTPS2QQZrmbkz 612U, // VCVTTPS2QQZrmk 324U, // VCVTTPS2QQZrmkz 0U, // VCVTTPS2QQZrr 8U, // VCVTTPS2QQZrrb 20772U, // VCVTTPS2QQZrrbk 20580U, // VCVTTPS2QQZrrbkz 292U, // VCVTTPS2QQZrrk 100U, // VCVTTPS2QQZrrkz 0U, // VCVTTPS2UDQZ128rm 9U, // VCVTTPS2UDQZ128rmb 6884U, // VCVTTPS2UDQZ128rmbk 6596U, // VCVTTPS2UDQZ128rmbkz 260U, // VCVTTPS2UDQZ128rmk 356U, // VCVTTPS2UDQZ128rmkz 0U, // VCVTTPS2UDQZ128rr 292U, // VCVTTPS2UDQZ128rrk 100U, // VCVTTPS2UDQZ128rrkz 0U, // VCVTTPS2UDQZ256rm 10U, // VCVTTPS2UDQZ256rmb 8932U, // VCVTTPS2UDQZ256rmbk 8644U, // VCVTTPS2UDQZ256rmbkz 612U, // VCVTTPS2UDQZ256rmk 324U, // VCVTTPS2UDQZ256rmkz 0U, // VCVTTPS2UDQZ256rr 292U, // VCVTTPS2UDQZ256rrk 100U, // VCVTTPS2UDQZ256rrkz 0U, // VCVTTPS2UDQZrm 10U, // VCVTTPS2UDQZrmb 10980U, // VCVTTPS2UDQZrmbk 10692U, // VCVTTPS2UDQZrmbkz 1060U, // VCVTTPS2UDQZrmk 420U, // VCVTTPS2UDQZrmkz 0U, // VCVTTPS2UDQZrr 8U, // VCVTTPS2UDQZrrb 20772U, // VCVTTPS2UDQZrrbk 20580U, // VCVTTPS2UDQZrrbkz 292U, // VCVTTPS2UDQZrrk 100U, // VCVTTPS2UDQZrrkz 0U, // VCVTTPS2UQQZ128rm 9U, // VCVTTPS2UQQZ128rmb 4836U, // VCVTTPS2UQQZ128rmbk 4548U, // VCVTTPS2UQQZ128rmbkz 580U, // VCVTTPS2UQQZ128rmk 388U, // VCVTTPS2UQQZ128rmkz 0U, // VCVTTPS2UQQZ128rr 292U, // VCVTTPS2UQQZ128rrk 100U, // VCVTTPS2UQQZ128rrkz 0U, // VCVTTPS2UQQZ256rm 9U, // VCVTTPS2UQQZ256rmb 6884U, // VCVTTPS2UQQZ256rmbk 6596U, // VCVTTPS2UQQZ256rmbkz 260U, // VCVTTPS2UQQZ256rmk 356U, // VCVTTPS2UQQZ256rmkz 0U, // VCVTTPS2UQQZ256rr 292U, // VCVTTPS2UQQZ256rrk 100U, // VCVTTPS2UQQZ256rrkz 0U, // VCVTTPS2UQQZrm 10U, // VCVTTPS2UQQZrmb 8932U, // VCVTTPS2UQQZrmbk 8644U, // VCVTTPS2UQQZrmbkz 612U, // VCVTTPS2UQQZrmk 324U, // VCVTTPS2UQQZrmkz 0U, // VCVTTPS2UQQZrr 8U, // VCVTTPS2UQQZrrb 20772U, // VCVTTPS2UQQZrrbk 20580U, // VCVTTPS2UQQZrrbkz 292U, // VCVTTPS2UQQZrrk 100U, // VCVTTPS2UQQZrrkz 0U, // VCVTTSD2SI64Zrm 0U, // VCVTTSD2SI64Zrm_Int 0U, // VCVTTSD2SI64Zrr 0U, // VCVTTSD2SI64Zrr_Int 8U, // VCVTTSD2SI64Zrrb_Int 0U, // VCVTTSD2SI64rm 0U, // VCVTTSD2SI64rm_Int 0U, // VCVTTSD2SI64rr 0U, // VCVTTSD2SI64rr_Int 0U, // VCVTTSD2SIZrm 0U, // VCVTTSD2SIZrm_Int 0U, // VCVTTSD2SIZrr 0U, // VCVTTSD2SIZrr_Int 8U, // VCVTTSD2SIZrrb_Int 0U, // VCVTTSD2SIrm 0U, // VCVTTSD2SIrm_Int 0U, // VCVTTSD2SIrr 0U, // VCVTTSD2SIrr_Int 0U, // VCVTTSD2USI64Zrm 0U, // VCVTTSD2USI64Zrm_Int 0U, // VCVTTSD2USI64Zrr 0U, // VCVTTSD2USI64Zrr_Int 8U, // VCVTTSD2USI64Zrrb_Int 0U, // VCVTTSD2USIZrm 0U, // VCVTTSD2USIZrm_Int 0U, // VCVTTSD2USIZrr 0U, // VCVTTSD2USIZrr_Int 8U, // VCVTTSD2USIZrrb_Int 0U, // VCVTTSS2SI64Zrm 0U, // VCVTTSS2SI64Zrm_Int 0U, // VCVTTSS2SI64Zrr 0U, // VCVTTSS2SI64Zrr_Int 8U, // VCVTTSS2SI64Zrrb_Int 0U, // VCVTTSS2SI64rm 0U, // VCVTTSS2SI64rm_Int 0U, // VCVTTSS2SI64rr 0U, // VCVTTSS2SI64rr_Int 0U, // VCVTTSS2SIZrm 0U, // VCVTTSS2SIZrm_Int 0U, // VCVTTSS2SIZrr 0U, // VCVTTSS2SIZrr_Int 8U, // VCVTTSS2SIZrrb_Int 0U, // VCVTTSS2SIrm 0U, // VCVTTSS2SIrm_Int 0U, // VCVTTSS2SIrr 0U, // VCVTTSS2SIrr_Int 0U, // VCVTTSS2USI64Zrm 0U, // VCVTTSS2USI64Zrm_Int 0U, // VCVTTSS2USI64Zrr 0U, // VCVTTSS2USI64Zrr_Int 8U, // VCVTTSS2USI64Zrrb_Int 0U, // VCVTTSS2USIZrm 0U, // VCVTTSS2USIZrm_Int 0U, // VCVTTSS2USIZrr 0U, // VCVTTSS2USIZrr_Int 8U, // VCVTTSS2USIZrrb_Int 0U, // VCVTUDQ2PDZ128rm 9U, // VCVTUDQ2PDZ128rmb 5060U, // VCVTUDQ2PDZ128rmbk 4164U, // VCVTUDQ2PDZ128rmbkz 644U, // VCVTUDQ2PDZ128rmk 132U, // VCVTUDQ2PDZ128rmkz 0U, // VCVTUDQ2PDZ128rr 292U, // VCVTUDQ2PDZ128rrk 100U, // VCVTUDQ2PDZ128rrkz 0U, // VCVTUDQ2PDZ256rm 9U, // VCVTUDQ2PDZ256rmb 7108U, // VCVTUDQ2PDZ256rmbk 6212U, // VCVTUDQ2PDZ256rmbkz 676U, // VCVTUDQ2PDZ256rmk 516U, // VCVTUDQ2PDZ256rmkz 0U, // VCVTUDQ2PDZ256rr 292U, // VCVTUDQ2PDZ256rrk 100U, // VCVTUDQ2PDZ256rrkz 0U, // VCVTUDQ2PDZrm 10U, // VCVTUDQ2PDZrmb 9156U, // VCVTUDQ2PDZrmbk 8260U, // VCVTUDQ2PDZrmbkz 708U, // VCVTUDQ2PDZrmk 484U, // VCVTUDQ2PDZrmkz 0U, // VCVTUDQ2PDZrr 292U, // VCVTUDQ2PDZrrk 100U, // VCVTUDQ2PDZrrkz 0U, // VCVTUDQ2PSZ128rm 9U, // VCVTUDQ2PSZ128rmb 7108U, // VCVTUDQ2PSZ128rmbk 6212U, // VCVTUDQ2PSZ128rmbkz 676U, // VCVTUDQ2PSZ128rmk 516U, // VCVTUDQ2PSZ128rmkz 0U, // VCVTUDQ2PSZ128rr 292U, // VCVTUDQ2PSZ128rrk 100U, // VCVTUDQ2PSZ128rrkz 0U, // VCVTUDQ2PSZ256rm 10U, // VCVTUDQ2PSZ256rmb 9156U, // VCVTUDQ2PSZ256rmbk 8260U, // VCVTUDQ2PSZ256rmbkz 708U, // VCVTUDQ2PSZ256rmk 484U, // VCVTUDQ2PSZ256rmkz 0U, // VCVTUDQ2PSZ256rr 292U, // VCVTUDQ2PSZ256rrk 100U, // VCVTUDQ2PSZ256rrkz 0U, // VCVTUDQ2PSZrm 10U, // VCVTUDQ2PSZrmb 11204U, // VCVTUDQ2PSZrmbk 10308U, // VCVTUDQ2PSZrmbkz 996U, // VCVTUDQ2PSZrmk 548U, // VCVTUDQ2PSZrmkz 0U, // VCVTUDQ2PSZrr 1024U, // VCVTUDQ2PSZrrb 887076U, // VCVTUDQ2PSZrrbk 362596U, // VCVTUDQ2PSZrrbkz 292U, // VCVTUDQ2PSZrrk 100U, // VCVTUDQ2PSZrrkz 0U, // VCVTUQQ2PDZ128rm 9U, // VCVTUQQ2PDZ128rmb 4740U, // VCVTUQQ2PDZ128rmbk 4228U, // VCVTUQQ2PDZ128rmbkz 676U, // VCVTUQQ2PDZ128rmk 516U, // VCVTUQQ2PDZ128rmkz 0U, // VCVTUQQ2PDZ128rr 292U, // VCVTUQQ2PDZ128rrk 100U, // VCVTUQQ2PDZ128rrkz 0U, // VCVTUQQ2PDZ256rm 9U, // VCVTUQQ2PDZ256rmb 6788U, // VCVTUQQ2PDZ256rmbk 6276U, // VCVTUQQ2PDZ256rmbkz 708U, // VCVTUQQ2PDZ256rmk 484U, // VCVTUQQ2PDZ256rmkz 0U, // VCVTUQQ2PDZ256rr 292U, // VCVTUQQ2PDZ256rrk 100U, // VCVTUQQ2PDZ256rrkz 0U, // VCVTUQQ2PDZrm 10U, // VCVTUQQ2PDZrmb 8836U, // VCVTUQQ2PDZrmbk 8324U, // VCVTUQQ2PDZrmbkz 996U, // VCVTUQQ2PDZrmk 548U, // VCVTUQQ2PDZrmkz 0U, // VCVTUQQ2PDZrr 1024U, // VCVTUQQ2PDZrrb 887076U, // VCVTUQQ2PDZrrbk 362596U, // VCVTUQQ2PDZrrbkz 292U, // VCVTUQQ2PDZrrk 100U, // VCVTUQQ2PDZrrkz 0U, // VCVTUQQ2PSZ128rm 9U, // VCVTUQQ2PSZ128rmb 4740U, // VCVTUQQ2PSZ128rmbk 4228U, // VCVTUQQ2PSZ128rmbkz 676U, // VCVTUQQ2PSZ128rmk 516U, // VCVTUQQ2PSZ128rmkz 0U, // VCVTUQQ2PSZ128rr 292U, // VCVTUQQ2PSZ128rrk 100U, // VCVTUQQ2PSZ128rrkz 0U, // VCVTUQQ2PSZ256rm 9U, // VCVTUQQ2PSZ256rmb 6788U, // VCVTUQQ2PSZ256rmbk 6276U, // VCVTUQQ2PSZ256rmbkz 708U, // VCVTUQQ2PSZ256rmk 484U, // VCVTUQQ2PSZ256rmkz 0U, // VCVTUQQ2PSZ256rr 292U, // VCVTUQQ2PSZ256rrk 100U, // VCVTUQQ2PSZ256rrkz 0U, // VCVTUQQ2PSZrm 10U, // VCVTUQQ2PSZrmb 8836U, // VCVTUQQ2PSZrmbk 8324U, // VCVTUQQ2PSZrmbkz 996U, // VCVTUQQ2PSZrmk 548U, // VCVTUQQ2PSZrmkz 0U, // VCVTUQQ2PSZrr 1024U, // VCVTUQQ2PSZrrb 887076U, // VCVTUQQ2PSZrrbk 362596U, // VCVTUQQ2PSZrrbkz 292U, // VCVTUQQ2PSZrrk 100U, // VCVTUQQ2PSZrrkz 64U, // VCVTUSI2SDZrm 64U, // VCVTUSI2SDZrm_Int 96U, // VCVTUSI2SDZrr 96U, // VCVTUSI2SDZrr_Int 64U, // VCVTUSI2SSZrm 64U, // VCVTUSI2SSZrm_Int 96U, // VCVTUSI2SSZrr 96U, // VCVTUSI2SSZrr_Int 1088U, // VCVTUSI2SSZrrb_Int 128U, // VCVTUSI642SDZrm 128U, // VCVTUSI642SDZrm_Int 96U, // VCVTUSI642SDZrr 96U, // VCVTUSI642SDZrr_Int 1088U, // VCVTUSI642SDZrrb_Int 128U, // VCVTUSI642SSZrm 128U, // VCVTUSI642SSZrm_Int 96U, // VCVTUSI642SSZrr 96U, // VCVTUSI642SSZrr_Int 1088U, // VCVTUSI642SSZrrb_Int 461312U, // VDBPSADBWZ128rmi 38308132U, // VDBPSADBWZ128rmik 55117924U, // VDBPSADBWZ128rmikz 624736U, // VDBPSADBWZ128rri 71469348U, // VDBPSADBWZ128rrik 88279140U, // VDBPSADBWZ128rrikz 461280U, // VDBPSADBWZ256rmi 38406436U, // VDBPSADBWZ256rmik 55216228U, // VDBPSADBWZ256rmikz 624736U, // VDBPSADBWZ256rri 71469348U, // VDBPSADBWZ256rrik 88279140U, // VDBPSADBWZ256rrikz 461344U, // VDBPSADBWZrmi 38471972U, // VDBPSADBWZrmik 55281764U, // VDBPSADBWZrmikz 624736U, // VDBPSADBWZrri 71469348U, // VDBPSADBWZrrik 88279140U, // VDBPSADBWZrrikz 320U, // VDIVPDYrm 96U, // VDIVPDYrr 352U, // VDIVPDZ128rm 4480U, // VDIVPDZ128rmb 1116452U, // VDIVPDZ128rmbk 1149028U, // VDIVPDZ128rmbkz 35108U, // VDIVPDZ128rmk 133220U, // VDIVPDZ128rmkz 96U, // VDIVPDZ128rr 166180U, // VDIVPDZ128rrk 198756U, // VDIVPDZ128rrkz 320U, // VDIVPDZ256rm 6528U, // VDIVPDZ256rmb 2165028U, // VDIVPDZ256rmbk 2197604U, // VDIVPDZ256rmbkz 231716U, // VDIVPDZ256rmk 264292U, // VDIVPDZ256rmkz 96U, // VDIVPDZ256rr 166180U, // VDIVPDZ256rrk 198756U, // VDIVPDZ256rrkz 416U, // VDIVPDZrm 8576U, // VDIVPDZrmb 3213604U, // VDIVPDZrmbk 3246180U, // VDIVPDZrmbkz 297252U, // VDIVPDZrmk 329828U, // VDIVPDZrmkz 96U, // VDIVPDZrr 362592U, // VDIVPDZrrb 4360484U, // VDIVPDZrrbk 21170276U, // VDIVPDZrrbkz 166180U, // VDIVPDZrrk 198756U, // VDIVPDZrrkz 352U, // VDIVPDrm 96U, // VDIVPDrr 320U, // VDIVPSYrm 96U, // VDIVPSYrr 352U, // VDIVPSZ128rm 6592U, // VDIVPSZ128rmb 2492708U, // VDIVPSZ128rmbk 2525284U, // VDIVPSZ128rmbkz 35108U, // VDIVPSZ128rmk 133220U, // VDIVPSZ128rmkz 96U, // VDIVPSZ128rr 166180U, // VDIVPSZ128rrk 198756U, // VDIVPSZ128rrkz 320U, // VDIVPSZ256rm 8640U, // VDIVPSZ256rmb 3541284U, // VDIVPSZ256rmbk 3573860U, // VDIVPSZ256rmbkz 231716U, // VDIVPSZ256rmk 264292U, // VDIVPSZ256rmkz 96U, // VDIVPSZ256rr 166180U, // VDIVPSZ256rrk 198756U, // VDIVPSZ256rrkz 416U, // VDIVPSZrm 10688U, // VDIVPSZrmb 5638436U, // VDIVPSZrmbk 5671012U, // VDIVPSZrmbkz 297252U, // VDIVPSZrmk 329828U, // VDIVPSZrmkz 96U, // VDIVPSZrr 362592U, // VDIVPSZrrb 4360484U, // VDIVPSZrrbk 21170276U, // VDIVPSZrrbkz 166180U, // VDIVPSZrrk 198756U, // VDIVPSZrrkz 352U, // VDIVPSrm 96U, // VDIVPSrr 384U, // VDIVSDZrm 384U, // VDIVSDZrm_Int 67876U, // VDIVSDZrm_Intk 100452U, // VDIVSDZrm_Intkz 96U, // VDIVSDZrr 96U, // VDIVSDZrr_Int 166180U, // VDIVSDZrr_Intk 198756U, // VDIVSDZrr_Intkz 362592U, // VDIVSDZrrb_Int 4360484U, // VDIVSDZrrb_Intk 21170276U, // VDIVSDZrrb_Intkz 384U, // VDIVSDrm 384U, // VDIVSDrm_Int 96U, // VDIVSDrr 96U, // VDIVSDrr_Int 448U, // VDIVSSZrm 448U, // VDIVSSZrm_Int 395556U, // VDIVSSZrm_Intk 428132U, // VDIVSSZrm_Intkz 96U, // VDIVSSZrr 96U, // VDIVSSZrr_Int 166180U, // VDIVSSZrr_Intk 198756U, // VDIVSSZrr_Intkz 362592U, // VDIVSSZrrb_Int 4360484U, // VDIVSSZrrb_Intk 21170276U, // VDIVSSZrrb_Intkz 448U, // VDIVSSrm 448U, // VDIVSSrm_Int 96U, // VDIVSSrr 96U, // VDIVSSrr_Int 461152U, // VDPPDrmi 624736U, // VDPPDrri 461280U, // VDPPSYrmi 624736U, // VDPPSYrri 461152U, // VDPPSrmi 624736U, // VDPPSrri 0U, // VERRm 0U, // VERRr 0U, // VERWm 0U, // VERWr 0U, // VEXP2PDZm 10U, // VEXP2PDZmb 8772U, // VEXP2PDZmbk 8580U, // VEXP2PDZmbkz 1060U, // VEXP2PDZmk 420U, // VEXP2PDZmkz 0U, // VEXP2PDZr 8U, // VEXP2PDZrb 20772U, // VEXP2PDZrbk 20580U, // VEXP2PDZrbkz 292U, // VEXP2PDZrk 100U, // VEXP2PDZrkz 0U, // VEXP2PSZm 10U, // VEXP2PSZmb 10980U, // VEXP2PSZmbk 10692U, // VEXP2PSZmbkz 1060U, // VEXP2PSZmk 420U, // VEXP2PSZmkz 0U, // VEXP2PSZr 8U, // VEXP2PSZrb 20772U, // VEXP2PSZrbk 20580U, // VEXP2PSZrbkz 292U, // VEXP2PSZrk 100U, // VEXP2PSZrkz 0U, // VEXPANDPDZ128rm 260U, // VEXPANDPDZ128rmk 356U, // VEXPANDPDZ128rmkz 0U, // VEXPANDPDZ128rr 292U, // VEXPANDPDZ128rrk 100U, // VEXPANDPDZ128rrkz 0U, // VEXPANDPDZ256rm 612U, // VEXPANDPDZ256rmk 324U, // VEXPANDPDZ256rmkz 0U, // VEXPANDPDZ256rr 292U, // VEXPANDPDZ256rrk 100U, // VEXPANDPDZ256rrkz 0U, // VEXPANDPDZrm 1060U, // VEXPANDPDZrmk 420U, // VEXPANDPDZrmkz 0U, // VEXPANDPDZrr 292U, // VEXPANDPDZrrk 100U, // VEXPANDPDZrrkz 0U, // VEXPANDPSZ128rm 260U, // VEXPANDPSZ128rmk 356U, // VEXPANDPSZ128rmkz 0U, // VEXPANDPSZ128rr 292U, // VEXPANDPSZ128rrk 100U, // VEXPANDPSZ128rrkz 0U, // VEXPANDPSZ256rm 612U, // VEXPANDPSZ256rmk 324U, // VEXPANDPSZ256rmkz 0U, // VEXPANDPSZ256rr 292U, // VEXPANDPSZ256rrk 100U, // VEXPANDPSZ256rrkz 0U, // VEXPANDPSZrm 1060U, // VEXPANDPSZrmk 420U, // VEXPANDPSZrmkz 0U, // VEXPANDPSZrr 292U, // VEXPANDPSZrrk 100U, // VEXPANDPSZrrkz 0U, // VEXTRACTF128mr 32U, // VEXTRACTF128rr 0U, // VEXTRACTF32x4Z256mr 460964U, // VEXTRACTF32x4Z256mrk 32U, // VEXTRACTF32x4Z256rr 2340U, // VEXTRACTF32x4Z256rrk 624740U, // VEXTRACTF32x4Z256rrkz 0U, // VEXTRACTF32x4Zmr 460964U, // VEXTRACTF32x4Zmrk 32U, // VEXTRACTF32x4Zrr 2340U, // VEXTRACTF32x4Zrrk 624740U, // VEXTRACTF32x4Zrrkz 0U, // VEXTRACTF32x8Zmr 460964U, // VEXTRACTF32x8Zmrk 32U, // VEXTRACTF32x8Zrr 2340U, // VEXTRACTF32x8Zrrk 624740U, // VEXTRACTF32x8Zrrkz 0U, // VEXTRACTF64x2Z256mr 460964U, // VEXTRACTF64x2Z256mrk 32U, // VEXTRACTF64x2Z256rr 2340U, // VEXTRACTF64x2Z256rrk 624740U, // VEXTRACTF64x2Z256rrkz 0U, // VEXTRACTF64x2Zmr 460964U, // VEXTRACTF64x2Zmrk 32U, // VEXTRACTF64x2Zrr 2340U, // VEXTRACTF64x2Zrrk 624740U, // VEXTRACTF64x2Zrrkz 0U, // VEXTRACTF64x4Zmr 460964U, // VEXTRACTF64x4Zmrk 32U, // VEXTRACTF64x4Zrr 2340U, // VEXTRACTF64x4Zrrk 624740U, // VEXTRACTF64x4Zrrkz 0U, // VEXTRACTI128mr 32U, // VEXTRACTI128rr 0U, // VEXTRACTI32x4Z256mr 460964U, // VEXTRACTI32x4Z256mrk 32U, // VEXTRACTI32x4Z256rr 2340U, // VEXTRACTI32x4Z256rrk 624740U, // VEXTRACTI32x4Z256rrkz 0U, // VEXTRACTI32x4Zmr 460964U, // VEXTRACTI32x4Zmrk 32U, // VEXTRACTI32x4Zrr 2340U, // VEXTRACTI32x4Zrrk 624740U, // VEXTRACTI32x4Zrrkz 0U, // VEXTRACTI32x8Zmr 460964U, // VEXTRACTI32x8Zmrk 32U, // VEXTRACTI32x8Zrr 2340U, // VEXTRACTI32x8Zrrk 624740U, // VEXTRACTI32x8Zrrkz 0U, // VEXTRACTI64x2Z256mr 460964U, // VEXTRACTI64x2Z256mrk 32U, // VEXTRACTI64x2Z256rr 2340U, // VEXTRACTI64x2Z256rrk 624740U, // VEXTRACTI64x2Z256rrkz 0U, // VEXTRACTI64x2Zmr 460964U, // VEXTRACTI64x2Zmrk 32U, // VEXTRACTI64x2Zrr 2340U, // VEXTRACTI64x2Zrrk 624740U, // VEXTRACTI64x2Zrrkz 0U, // VEXTRACTI64x4Zmr 460964U, // VEXTRACTI64x4Zmrk 32U, // VEXTRACTI64x4Zrr 2340U, // VEXTRACTI64x4Zrrk 624740U, // VEXTRACTI64x4Zrrkz 0U, // VEXTRACTPSZmr 32U, // VEXTRACTPSZrr 0U, // VEXTRACTPSmr 32U, // VEXTRACTPSrr 936512U, // VFIXUPIMMPDZ128rmbi 43059492U, // VFIXUPIMMPDZ128rmbik 43059492U, // VFIXUPIMMPDZ128rmbikz 919808U, // VFIXUPIMMPDZ128rmi 37783844U, // VFIXUPIMMPDZ128rmik 37783844U, // VFIXUPIMMPDZ128rmikz 2336U, // VFIXUPIMMPDZ128rri 71469348U, // VFIXUPIMMPDZ128rrik 71469348U, // VFIXUPIMMPDZ128rrikz 930368U, // VFIXUPIMMPDZ256rmbi 39913764U, // VFIXUPIMMPDZ256rmbik 39913764U, // VFIXUPIMMPDZ256rmbikz 920160U, // VFIXUPIMMPDZ256rmi 37980452U, // VFIXUPIMMPDZ256rmik 37980452U, // VFIXUPIMMPDZ256rmikz 2336U, // VFIXUPIMMPDZ256rri 71469348U, // VFIXUPIMMPDZ256rrik 71469348U, // VFIXUPIMMPDZ256rrikz 932416U, // VFIXUPIMMPDZrmbi 40962340U, // VFIXUPIMMPDZrmbik 40962340U, // VFIXUPIMMPDZrmbikz 920608U, // VFIXUPIMMPDZrmi 38045988U, // VFIXUPIMMPDZrmik 38045988U, // VFIXUPIMMPDZrmikz 2336U, // VFIXUPIMMPDZrri 22816U, // VFIXUPIMMPDZrrib 77760804U, // VFIXUPIMMPDZrribk 77760804U, // VFIXUPIMMPDZrribkz 71469348U, // VFIXUPIMMPDZrrik 71469348U, // VFIXUPIMMPDZrrikz 930528U, // VFIXUPIMMPSZ128rmbi 40241444U, // VFIXUPIMMPSZ128rmbik 40241444U, // VFIXUPIMMPSZ128rmbikz 919808U, // VFIXUPIMMPSZ128rmi 37783844U, // VFIXUPIMMPSZ128rmik 37783844U, // VFIXUPIMMPSZ128rmikz 2336U, // VFIXUPIMMPSZ128rri 71469348U, // VFIXUPIMMPSZ128rrik 71469348U, // VFIXUPIMMPSZ128rrikz 932576U, // VFIXUPIMMPSZ256rmbi 41290020U, // VFIXUPIMMPSZ256rmbik 41290020U, // VFIXUPIMMPSZ256rmbikz 920160U, // VFIXUPIMMPSZ256rmi 37980452U, // VFIXUPIMMPSZ256rmik 37980452U, // VFIXUPIMMPSZ256rmikz 2336U, // VFIXUPIMMPSZ256rri 71469348U, // VFIXUPIMMPSZ256rrik 71469348U, // VFIXUPIMMPSZ256rrikz 934624U, // VFIXUPIMMPSZrmbi 42338596U, // VFIXUPIMMPSZrmbik 42338596U, // VFIXUPIMMPSZrmbikz 920608U, // VFIXUPIMMPSZrmi 38045988U, // VFIXUPIMMPSZrmik 38045988U, // VFIXUPIMMPSZrmikz 2336U, // VFIXUPIMMPSZrri 22816U, // VFIXUPIMMPSZrrib 77760804U, // VFIXUPIMMPSZrribk 77760804U, // VFIXUPIMMPSZrribkz 71469348U, // VFIXUPIMMPSZrrik 71469348U, // VFIXUPIMMPSZrrikz 920128U, // VFIXUPIMMSDZrmi 37816612U, // VFIXUPIMMSDZrmik 37816612U, // VFIXUPIMMSDZrmikz 2336U, // VFIXUPIMMSDZrri 22816U, // VFIXUPIMMSDZrrib 77760804U, // VFIXUPIMMSDZrribk 77760804U, // VFIXUPIMMSDZrribkz 71469348U, // VFIXUPIMMSDZrrik 71469348U, // VFIXUPIMMSDZrrikz 920288U, // VFIXUPIMMSSZrmi 38144292U, // VFIXUPIMMSSZrmik 38144292U, // VFIXUPIMMSSZrmikz 2336U, // VFIXUPIMMSSZrri 22816U, // VFIXUPIMMSSZrrib 77760804U, // VFIXUPIMMSSZrribk 77760804U, // VFIXUPIMMSSZrribkz 71469348U, // VFIXUPIMMSSZrrik 71469348U, // VFIXUPIMMSSZrrikz 608U, // VFMADD132PDYm 288U, // VFMADD132PDYr 256U, // VFMADD132PDZ128m 4672U, // VFMADD132PDZ128mb 1116452U, // VFMADD132PDZ128mbk 1116452U, // VFMADD132PDZ128mbkz 35108U, // VFMADD132PDZ128mk 35108U, // VFMADD132PDZ128mkz 288U, // VFMADD132PDZ128r 166180U, // VFMADD132PDZ128rk 166180U, // VFMADD132PDZ128rkz 608U, // VFMADD132PDZ256m 6720U, // VFMADD132PDZ256mb 2165028U, // VFMADD132PDZ256mbk 2165028U, // VFMADD132PDZ256mbkz 231716U, // VFMADD132PDZ256mk 231716U, // VFMADD132PDZ256mkz 288U, // VFMADD132PDZ256r 166180U, // VFMADD132PDZ256rk 166180U, // VFMADD132PDZ256rkz 1056U, // VFMADD132PDZm 8768U, // VFMADD132PDZmb 3213604U, // VFMADD132PDZmbk 3213604U, // VFMADD132PDZmbkz 297252U, // VFMADD132PDZmk 297252U, // VFMADD132PDZmkz 288U, // VFMADD132PDZr 887072U, // VFMADD132PDZrb 4360484U, // VFMADD132PDZrbk 4360484U, // VFMADD132PDZrbkz 166180U, // VFMADD132PDZrk 166180U, // VFMADD132PDZrkz 256U, // VFMADD132PDm 288U, // VFMADD132PDr 608U, // VFMADD132PSYm 288U, // VFMADD132PSYr 256U, // VFMADD132PSZ128m 6880U, // VFMADD132PSZ128mb 2492708U, // VFMADD132PSZ128mbk 2492708U, // VFMADD132PSZ128mbkz 35108U, // VFMADD132PSZ128mk 35108U, // VFMADD132PSZ128mkz 288U, // VFMADD132PSZ128r 166180U, // VFMADD132PSZ128rk 166180U, // VFMADD132PSZ128rkz 608U, // VFMADD132PSZ256m 8928U, // VFMADD132PSZ256mb 3541284U, // VFMADD132PSZ256mbk 3541284U, // VFMADD132PSZ256mbkz 231716U, // VFMADD132PSZ256mk 231716U, // VFMADD132PSZ256mkz 288U, // VFMADD132PSZ256r 166180U, // VFMADD132PSZ256rk 166180U, // VFMADD132PSZ256rkz 1056U, // VFMADD132PSZm 10976U, // VFMADD132PSZmb 5638436U, // VFMADD132PSZmbk 5638436U, // VFMADD132PSZmbkz 297252U, // VFMADD132PSZmk 297252U, // VFMADD132PSZmkz 288U, // VFMADD132PSZr 887072U, // VFMADD132PSZrb 4360484U, // VFMADD132PSZrbk 4360484U, // VFMADD132PSZrbkz 166180U, // VFMADD132PSZrk 166180U, // VFMADD132PSZrkz 256U, // VFMADD132PSm 288U, // VFMADD132PSr 576U, // VFMADD132SDZm 576U, // VFMADD132SDZm_Int 67876U, // VFMADD132SDZm_Intk 67876U, // VFMADD132SDZm_Intkz 288U, // VFMADD132SDZr 288U, // VFMADD132SDZr_Int 166180U, // VFMADD132SDZr_Intk 166180U, // VFMADD132SDZr_Intkz 288U, // VFMADD132SDZrb 887072U, // VFMADD132SDZrb_Int 4360484U, // VFMADD132SDZrb_Intk 4360484U, // VFMADD132SDZrb_Intkz 576U, // VFMADD132SDm 576U, // VFMADD132SDm_Int 288U, // VFMADD132SDr 288U, // VFMADD132SDr_Int 736U, // VFMADD132SSZm 736U, // VFMADD132SSZm_Int 395556U, // VFMADD132SSZm_Intk 395556U, // VFMADD132SSZm_Intkz 288U, // VFMADD132SSZr 288U, // VFMADD132SSZr_Int 166180U, // VFMADD132SSZr_Intk 166180U, // VFMADD132SSZr_Intkz 288U, // VFMADD132SSZrb 887072U, // VFMADD132SSZrb_Int 4360484U, // VFMADD132SSZrb_Intk 4360484U, // VFMADD132SSZrb_Intkz 736U, // VFMADD132SSm 736U, // VFMADD132SSm_Int 288U, // VFMADD132SSr 288U, // VFMADD132SSr_Int 608U, // VFMADD213PDYm 288U, // VFMADD213PDYr 256U, // VFMADD213PDZ128m 4672U, // VFMADD213PDZ128mb 1116452U, // VFMADD213PDZ128mbk 1116452U, // VFMADD213PDZ128mbkz 35108U, // VFMADD213PDZ128mk 35108U, // VFMADD213PDZ128mkz 288U, // VFMADD213PDZ128r 166180U, // VFMADD213PDZ128rk 166180U, // VFMADD213PDZ128rkz 608U, // VFMADD213PDZ256m 6720U, // VFMADD213PDZ256mb 2165028U, // VFMADD213PDZ256mbk 2165028U, // VFMADD213PDZ256mbkz 231716U, // VFMADD213PDZ256mk 231716U, // VFMADD213PDZ256mkz 288U, // VFMADD213PDZ256r 166180U, // VFMADD213PDZ256rk 166180U, // VFMADD213PDZ256rkz 1056U, // VFMADD213PDZm 8768U, // VFMADD213PDZmb 3213604U, // VFMADD213PDZmbk 3213604U, // VFMADD213PDZmbkz 297252U, // VFMADD213PDZmk 297252U, // VFMADD213PDZmkz 288U, // VFMADD213PDZr 887072U, // VFMADD213PDZrb 4360484U, // VFMADD213PDZrbk 4360484U, // VFMADD213PDZrbkz 166180U, // VFMADD213PDZrk 166180U, // VFMADD213PDZrkz 256U, // VFMADD213PDm 288U, // VFMADD213PDr 608U, // VFMADD213PSYm 288U, // VFMADD213PSYr 256U, // VFMADD213PSZ128m 6880U, // VFMADD213PSZ128mb 2492708U, // VFMADD213PSZ128mbk 2492708U, // VFMADD213PSZ128mbkz 35108U, // VFMADD213PSZ128mk 35108U, // VFMADD213PSZ128mkz 288U, // VFMADD213PSZ128r 166180U, // VFMADD213PSZ128rk 166180U, // VFMADD213PSZ128rkz 608U, // VFMADD213PSZ256m 8928U, // VFMADD213PSZ256mb 3541284U, // VFMADD213PSZ256mbk 3541284U, // VFMADD213PSZ256mbkz 231716U, // VFMADD213PSZ256mk 231716U, // VFMADD213PSZ256mkz 288U, // VFMADD213PSZ256r 166180U, // VFMADD213PSZ256rk 166180U, // VFMADD213PSZ256rkz 1056U, // VFMADD213PSZm 10976U, // VFMADD213PSZmb 5638436U, // VFMADD213PSZmbk 5638436U, // VFMADD213PSZmbkz 297252U, // VFMADD213PSZmk 297252U, // VFMADD213PSZmkz 288U, // VFMADD213PSZr 887072U, // VFMADD213PSZrb 4360484U, // VFMADD213PSZrbk 4360484U, // VFMADD213PSZrbkz 166180U, // VFMADD213PSZrk 166180U, // VFMADD213PSZrkz 256U, // VFMADD213PSm 288U, // VFMADD213PSr 576U, // VFMADD213SDZm 576U, // VFMADD213SDZm_Int 67876U, // VFMADD213SDZm_Intk 67876U, // VFMADD213SDZm_Intkz 288U, // VFMADD213SDZr 288U, // VFMADD213SDZr_Int 166180U, // VFMADD213SDZr_Intk 166180U, // VFMADD213SDZr_Intkz 288U, // VFMADD213SDZrb 887072U, // VFMADD213SDZrb_Int 4360484U, // VFMADD213SDZrb_Intk 4360484U, // VFMADD213SDZrb_Intkz 576U, // VFMADD213SDm 576U, // VFMADD213SDm_Int 288U, // VFMADD213SDr 288U, // VFMADD213SDr_Int 736U, // VFMADD213SSZm 736U, // VFMADD213SSZm_Int 395556U, // VFMADD213SSZm_Intk 395556U, // VFMADD213SSZm_Intkz 288U, // VFMADD213SSZr 288U, // VFMADD213SSZr_Int 166180U, // VFMADD213SSZr_Intk 166180U, // VFMADD213SSZr_Intkz 288U, // VFMADD213SSZrb 887072U, // VFMADD213SSZrb_Int 4360484U, // VFMADD213SSZrb_Intk 4360484U, // VFMADD213SSZrb_Intkz 736U, // VFMADD213SSm 736U, // VFMADD213SSm_Int 288U, // VFMADD213SSr 288U, // VFMADD213SSr_Int 608U, // VFMADD231PDYm 288U, // VFMADD231PDYr 256U, // VFMADD231PDZ128m 4672U, // VFMADD231PDZ128mb 1116452U, // VFMADD231PDZ128mbk 1116452U, // VFMADD231PDZ128mbkz 35108U, // VFMADD231PDZ128mk 35108U, // VFMADD231PDZ128mkz 288U, // VFMADD231PDZ128r 166180U, // VFMADD231PDZ128rk 166180U, // VFMADD231PDZ128rkz 608U, // VFMADD231PDZ256m 6720U, // VFMADD231PDZ256mb 2165028U, // VFMADD231PDZ256mbk 2165028U, // VFMADD231PDZ256mbkz 231716U, // VFMADD231PDZ256mk 231716U, // VFMADD231PDZ256mkz 288U, // VFMADD231PDZ256r 166180U, // VFMADD231PDZ256rk 166180U, // VFMADD231PDZ256rkz 1056U, // VFMADD231PDZm 8768U, // VFMADD231PDZmb 3213604U, // VFMADD231PDZmbk 3213604U, // VFMADD231PDZmbkz 297252U, // VFMADD231PDZmk 297252U, // VFMADD231PDZmkz 288U, // VFMADD231PDZr 887072U, // VFMADD231PDZrb 4360484U, // VFMADD231PDZrbk 4360484U, // VFMADD231PDZrbkz 166180U, // VFMADD231PDZrk 166180U, // VFMADD231PDZrkz 256U, // VFMADD231PDm 288U, // VFMADD231PDr 608U, // VFMADD231PSYm 288U, // VFMADD231PSYr 256U, // VFMADD231PSZ128m 6880U, // VFMADD231PSZ128mb 2492708U, // VFMADD231PSZ128mbk 2492708U, // VFMADD231PSZ128mbkz 35108U, // VFMADD231PSZ128mk 35108U, // VFMADD231PSZ128mkz 288U, // VFMADD231PSZ128r 166180U, // VFMADD231PSZ128rk 166180U, // VFMADD231PSZ128rkz 608U, // VFMADD231PSZ256m 8928U, // VFMADD231PSZ256mb 3541284U, // VFMADD231PSZ256mbk 3541284U, // VFMADD231PSZ256mbkz 231716U, // VFMADD231PSZ256mk 231716U, // VFMADD231PSZ256mkz 288U, // VFMADD231PSZ256r 166180U, // VFMADD231PSZ256rk 166180U, // VFMADD231PSZ256rkz 1056U, // VFMADD231PSZm 10976U, // VFMADD231PSZmb 5638436U, // VFMADD231PSZmbk 5638436U, // VFMADD231PSZmbkz 297252U, // VFMADD231PSZmk 297252U, // VFMADD231PSZmkz 288U, // VFMADD231PSZr 887072U, // VFMADD231PSZrb 4360484U, // VFMADD231PSZrbk 4360484U, // VFMADD231PSZrbkz 166180U, // VFMADD231PSZrk 166180U, // VFMADD231PSZrkz 256U, // VFMADD231PSm 288U, // VFMADD231PSr 576U, // VFMADD231SDZm 576U, // VFMADD231SDZm_Int 67876U, // VFMADD231SDZm_Intk 67876U, // VFMADD231SDZm_Intkz 288U, // VFMADD231SDZr 288U, // VFMADD231SDZr_Int 166180U, // VFMADD231SDZr_Intk 166180U, // VFMADD231SDZr_Intkz 288U, // VFMADD231SDZrb 887072U, // VFMADD231SDZrb_Int 4360484U, // VFMADD231SDZrb_Intk 4360484U, // VFMADD231SDZrb_Intkz 576U, // VFMADD231SDm 576U, // VFMADD231SDm_Int 288U, // VFMADD231SDr 288U, // VFMADD231SDr_Int 736U, // VFMADD231SSZm 736U, // VFMADD231SSZm_Int 395556U, // VFMADD231SSZm_Intk 395556U, // VFMADD231SSZm_Intkz 288U, // VFMADD231SSZr 288U, // VFMADD231SSZr_Int 166180U, // VFMADD231SSZr_Intk 166180U, // VFMADD231SSZr_Intkz 288U, // VFMADD231SSZrb 887072U, // VFMADD231SSZrb_Int 4360484U, // VFMADD231SSZrb_Intk 4360484U, // VFMADD231SSZrb_Intkz 736U, // VFMADD231SSm 736U, // VFMADD231SSm_Int 288U, // VFMADD231SSr 288U, // VFMADD231SSr_Int 854336U, // VFMADDPD4Ymr 264288U, // VFMADDPD4Yrm 198752U, // VFMADDPD4Yrr 198752U, // VFMADDPD4Yrr_REV 854368U, // VFMADDPD4mr 133216U, // VFMADDPD4rm 198752U, // VFMADDPD4rr 198752U, // VFMADDPD4rr_REV 854336U, // VFMADDPS4Ymr 264288U, // VFMADDPS4Yrm 198752U, // VFMADDPS4Yrr 198752U, // VFMADDPS4Yrr_REV 854368U, // VFMADDPS4mr 133216U, // VFMADDPS4rm 198752U, // VFMADDPS4rr 198752U, // VFMADDPS4rr_REV 854400U, // VFMADDSD4mr 854400U, // VFMADDSD4mr_Int 100448U, // VFMADDSD4rm 100448U, // VFMADDSD4rm_Int 198752U, // VFMADDSD4rr 198752U, // VFMADDSD4rr_Int 198752U, // VFMADDSD4rr_Int_REV 198752U, // VFMADDSD4rr_REV 854464U, // VFMADDSS4mr 854464U, // VFMADDSS4mr_Int 428128U, // VFMADDSS4rm 428128U, // VFMADDSS4rm_Int 198752U, // VFMADDSS4rr 198752U, // VFMADDSS4rr_Int 198752U, // VFMADDSS4rr_Int_REV 198752U, // VFMADDSS4rr_REV 608U, // VFMADDSUB132PDYm 288U, // VFMADDSUB132PDYr 256U, // VFMADDSUB132PDZ128m 4672U, // VFMADDSUB132PDZ128mb 1116452U, // VFMADDSUB132PDZ128mbk 1116452U, // VFMADDSUB132PDZ128mbkz 35108U, // VFMADDSUB132PDZ128mk 35108U, // VFMADDSUB132PDZ128mkz 288U, // VFMADDSUB132PDZ128r 166180U, // VFMADDSUB132PDZ128rk 166180U, // VFMADDSUB132PDZ128rkz 608U, // VFMADDSUB132PDZ256m 6720U, // VFMADDSUB132PDZ256mb 2165028U, // VFMADDSUB132PDZ256mbk 2165028U, // VFMADDSUB132PDZ256mbkz 231716U, // VFMADDSUB132PDZ256mk 231716U, // VFMADDSUB132PDZ256mkz 288U, // VFMADDSUB132PDZ256r 166180U, // VFMADDSUB132PDZ256rk 166180U, // VFMADDSUB132PDZ256rkz 1056U, // VFMADDSUB132PDZm 8768U, // VFMADDSUB132PDZmb 3213604U, // VFMADDSUB132PDZmbk 3213604U, // VFMADDSUB132PDZmbkz 297252U, // VFMADDSUB132PDZmk 297252U, // VFMADDSUB132PDZmkz 288U, // VFMADDSUB132PDZr 887072U, // VFMADDSUB132PDZrb 4360484U, // VFMADDSUB132PDZrbk 4360484U, // VFMADDSUB132PDZrbkz 166180U, // VFMADDSUB132PDZrk 166180U, // VFMADDSUB132PDZrkz 256U, // VFMADDSUB132PDm 288U, // VFMADDSUB132PDr 608U, // VFMADDSUB132PSYm 288U, // VFMADDSUB132PSYr 256U, // VFMADDSUB132PSZ128m 6880U, // VFMADDSUB132PSZ128mb 2492708U, // VFMADDSUB132PSZ128mbk 2492708U, // VFMADDSUB132PSZ128mbkz 35108U, // VFMADDSUB132PSZ128mk 35108U, // VFMADDSUB132PSZ128mkz 288U, // VFMADDSUB132PSZ128r 166180U, // VFMADDSUB132PSZ128rk 166180U, // VFMADDSUB132PSZ128rkz 608U, // VFMADDSUB132PSZ256m 8928U, // VFMADDSUB132PSZ256mb 3541284U, // VFMADDSUB132PSZ256mbk 3541284U, // VFMADDSUB132PSZ256mbkz 231716U, // VFMADDSUB132PSZ256mk 231716U, // VFMADDSUB132PSZ256mkz 288U, // VFMADDSUB132PSZ256r 166180U, // VFMADDSUB132PSZ256rk 166180U, // VFMADDSUB132PSZ256rkz 1056U, // VFMADDSUB132PSZm 10976U, // VFMADDSUB132PSZmb 5638436U, // VFMADDSUB132PSZmbk 5638436U, // VFMADDSUB132PSZmbkz 297252U, // VFMADDSUB132PSZmk 297252U, // VFMADDSUB132PSZmkz 288U, // VFMADDSUB132PSZr 887072U, // VFMADDSUB132PSZrb 4360484U, // VFMADDSUB132PSZrbk 4360484U, // VFMADDSUB132PSZrbkz 166180U, // VFMADDSUB132PSZrk 166180U, // VFMADDSUB132PSZrkz 256U, // VFMADDSUB132PSm 288U, // VFMADDSUB132PSr 608U, // VFMADDSUB213PDYm 288U, // VFMADDSUB213PDYr 256U, // VFMADDSUB213PDZ128m 4672U, // VFMADDSUB213PDZ128mb 1116452U, // VFMADDSUB213PDZ128mbk 1116452U, // VFMADDSUB213PDZ128mbkz 35108U, // VFMADDSUB213PDZ128mk 35108U, // VFMADDSUB213PDZ128mkz 288U, // VFMADDSUB213PDZ128r 166180U, // VFMADDSUB213PDZ128rk 166180U, // VFMADDSUB213PDZ128rkz 608U, // VFMADDSUB213PDZ256m 6720U, // VFMADDSUB213PDZ256mb 2165028U, // VFMADDSUB213PDZ256mbk 2165028U, // VFMADDSUB213PDZ256mbkz 231716U, // VFMADDSUB213PDZ256mk 231716U, // VFMADDSUB213PDZ256mkz 288U, // VFMADDSUB213PDZ256r 166180U, // VFMADDSUB213PDZ256rk 166180U, // VFMADDSUB213PDZ256rkz 1056U, // VFMADDSUB213PDZm 8768U, // VFMADDSUB213PDZmb 3213604U, // VFMADDSUB213PDZmbk 3213604U, // VFMADDSUB213PDZmbkz 297252U, // VFMADDSUB213PDZmk 297252U, // VFMADDSUB213PDZmkz 288U, // VFMADDSUB213PDZr 887072U, // VFMADDSUB213PDZrb 4360484U, // VFMADDSUB213PDZrbk 4360484U, // VFMADDSUB213PDZrbkz 166180U, // VFMADDSUB213PDZrk 166180U, // VFMADDSUB213PDZrkz 256U, // VFMADDSUB213PDm 288U, // VFMADDSUB213PDr 608U, // VFMADDSUB213PSYm 288U, // VFMADDSUB213PSYr 256U, // VFMADDSUB213PSZ128m 6880U, // VFMADDSUB213PSZ128mb 2492708U, // VFMADDSUB213PSZ128mbk 2492708U, // VFMADDSUB213PSZ128mbkz 35108U, // VFMADDSUB213PSZ128mk 35108U, // VFMADDSUB213PSZ128mkz 288U, // VFMADDSUB213PSZ128r 166180U, // VFMADDSUB213PSZ128rk 166180U, // VFMADDSUB213PSZ128rkz 608U, // VFMADDSUB213PSZ256m 8928U, // VFMADDSUB213PSZ256mb 3541284U, // VFMADDSUB213PSZ256mbk 3541284U, // VFMADDSUB213PSZ256mbkz 231716U, // VFMADDSUB213PSZ256mk 231716U, // VFMADDSUB213PSZ256mkz 288U, // VFMADDSUB213PSZ256r 166180U, // VFMADDSUB213PSZ256rk 166180U, // VFMADDSUB213PSZ256rkz 1056U, // VFMADDSUB213PSZm 10976U, // VFMADDSUB213PSZmb 5638436U, // VFMADDSUB213PSZmbk 5638436U, // VFMADDSUB213PSZmbkz 297252U, // VFMADDSUB213PSZmk 297252U, // VFMADDSUB213PSZmkz 288U, // VFMADDSUB213PSZr 887072U, // VFMADDSUB213PSZrb 4360484U, // VFMADDSUB213PSZrbk 4360484U, // VFMADDSUB213PSZrbkz 166180U, // VFMADDSUB213PSZrk 166180U, // VFMADDSUB213PSZrkz 256U, // VFMADDSUB213PSm 288U, // VFMADDSUB213PSr 608U, // VFMADDSUB231PDYm 288U, // VFMADDSUB231PDYr 256U, // VFMADDSUB231PDZ128m 4672U, // VFMADDSUB231PDZ128mb 1116452U, // VFMADDSUB231PDZ128mbk 1116452U, // VFMADDSUB231PDZ128mbkz 35108U, // VFMADDSUB231PDZ128mk 35108U, // VFMADDSUB231PDZ128mkz 288U, // VFMADDSUB231PDZ128r 166180U, // VFMADDSUB231PDZ128rk 166180U, // VFMADDSUB231PDZ128rkz 608U, // VFMADDSUB231PDZ256m 6720U, // VFMADDSUB231PDZ256mb 2165028U, // VFMADDSUB231PDZ256mbk 2165028U, // VFMADDSUB231PDZ256mbkz 231716U, // VFMADDSUB231PDZ256mk 231716U, // VFMADDSUB231PDZ256mkz 288U, // VFMADDSUB231PDZ256r 166180U, // VFMADDSUB231PDZ256rk 166180U, // VFMADDSUB231PDZ256rkz 1056U, // VFMADDSUB231PDZm 8768U, // VFMADDSUB231PDZmb 3213604U, // VFMADDSUB231PDZmbk 3213604U, // VFMADDSUB231PDZmbkz 297252U, // VFMADDSUB231PDZmk 297252U, // VFMADDSUB231PDZmkz 288U, // VFMADDSUB231PDZr 887072U, // VFMADDSUB231PDZrb 4360484U, // VFMADDSUB231PDZrbk 4360484U, // VFMADDSUB231PDZrbkz 166180U, // VFMADDSUB231PDZrk 166180U, // VFMADDSUB231PDZrkz 256U, // VFMADDSUB231PDm 288U, // VFMADDSUB231PDr 608U, // VFMADDSUB231PSYm 288U, // VFMADDSUB231PSYr 256U, // VFMADDSUB231PSZ128m 6880U, // VFMADDSUB231PSZ128mb 2492708U, // VFMADDSUB231PSZ128mbk 2492708U, // VFMADDSUB231PSZ128mbkz 35108U, // VFMADDSUB231PSZ128mk 35108U, // VFMADDSUB231PSZ128mkz 288U, // VFMADDSUB231PSZ128r 166180U, // VFMADDSUB231PSZ128rk 166180U, // VFMADDSUB231PSZ128rkz 608U, // VFMADDSUB231PSZ256m 8928U, // VFMADDSUB231PSZ256mb 3541284U, // VFMADDSUB231PSZ256mbk 3541284U, // VFMADDSUB231PSZ256mbkz 231716U, // VFMADDSUB231PSZ256mk 231716U, // VFMADDSUB231PSZ256mkz 288U, // VFMADDSUB231PSZ256r 166180U, // VFMADDSUB231PSZ256rk 166180U, // VFMADDSUB231PSZ256rkz 1056U, // VFMADDSUB231PSZm 10976U, // VFMADDSUB231PSZmb 5638436U, // VFMADDSUB231PSZmbk 5638436U, // VFMADDSUB231PSZmbkz 297252U, // VFMADDSUB231PSZmk 297252U, // VFMADDSUB231PSZmkz 288U, // VFMADDSUB231PSZr 887072U, // VFMADDSUB231PSZrb 4360484U, // VFMADDSUB231PSZrbk 4360484U, // VFMADDSUB231PSZrbkz 166180U, // VFMADDSUB231PSZrk 166180U, // VFMADDSUB231PSZrkz 256U, // VFMADDSUB231PSm 288U, // VFMADDSUB231PSr 854336U, // VFMADDSUBPD4Ymr 264288U, // VFMADDSUBPD4Yrm 198752U, // VFMADDSUBPD4Yrr 198752U, // VFMADDSUBPD4Yrr_REV 854368U, // VFMADDSUBPD4mr 133216U, // VFMADDSUBPD4rm 198752U, // VFMADDSUBPD4rr 198752U, // VFMADDSUBPD4rr_REV 854336U, // VFMADDSUBPS4Ymr 264288U, // VFMADDSUBPS4Yrm 198752U, // VFMADDSUBPS4Yrr 198752U, // VFMADDSUBPS4Yrr_REV 854368U, // VFMADDSUBPS4mr 133216U, // VFMADDSUBPS4rm 198752U, // VFMADDSUBPS4rr 198752U, // VFMADDSUBPS4rr_REV 608U, // VFMSUB132PDYm 288U, // VFMSUB132PDYr 256U, // VFMSUB132PDZ128m 4672U, // VFMSUB132PDZ128mb 1116452U, // VFMSUB132PDZ128mbk 1116452U, // VFMSUB132PDZ128mbkz 35108U, // VFMSUB132PDZ128mk 35108U, // VFMSUB132PDZ128mkz 288U, // VFMSUB132PDZ128r 166180U, // VFMSUB132PDZ128rk 166180U, // VFMSUB132PDZ128rkz 608U, // VFMSUB132PDZ256m 6720U, // VFMSUB132PDZ256mb 2165028U, // VFMSUB132PDZ256mbk 2165028U, // VFMSUB132PDZ256mbkz 231716U, // VFMSUB132PDZ256mk 231716U, // VFMSUB132PDZ256mkz 288U, // VFMSUB132PDZ256r 166180U, // VFMSUB132PDZ256rk 166180U, // VFMSUB132PDZ256rkz 1056U, // VFMSUB132PDZm 8768U, // VFMSUB132PDZmb 3213604U, // VFMSUB132PDZmbk 3213604U, // VFMSUB132PDZmbkz 297252U, // VFMSUB132PDZmk 297252U, // VFMSUB132PDZmkz 288U, // VFMSUB132PDZr 887072U, // VFMSUB132PDZrb 4360484U, // VFMSUB132PDZrbk 4360484U, // VFMSUB132PDZrbkz 166180U, // VFMSUB132PDZrk 166180U, // VFMSUB132PDZrkz 256U, // VFMSUB132PDm 288U, // VFMSUB132PDr 608U, // VFMSUB132PSYm 288U, // VFMSUB132PSYr 256U, // VFMSUB132PSZ128m 6880U, // VFMSUB132PSZ128mb 2492708U, // VFMSUB132PSZ128mbk 2492708U, // VFMSUB132PSZ128mbkz 35108U, // VFMSUB132PSZ128mk 35108U, // VFMSUB132PSZ128mkz 288U, // VFMSUB132PSZ128r 166180U, // VFMSUB132PSZ128rk 166180U, // VFMSUB132PSZ128rkz 608U, // VFMSUB132PSZ256m 8928U, // VFMSUB132PSZ256mb 3541284U, // VFMSUB132PSZ256mbk 3541284U, // VFMSUB132PSZ256mbkz 231716U, // VFMSUB132PSZ256mk 231716U, // VFMSUB132PSZ256mkz 288U, // VFMSUB132PSZ256r 166180U, // VFMSUB132PSZ256rk 166180U, // VFMSUB132PSZ256rkz 1056U, // VFMSUB132PSZm 10976U, // VFMSUB132PSZmb 5638436U, // VFMSUB132PSZmbk 5638436U, // VFMSUB132PSZmbkz 297252U, // VFMSUB132PSZmk 297252U, // VFMSUB132PSZmkz 288U, // VFMSUB132PSZr 887072U, // VFMSUB132PSZrb 4360484U, // VFMSUB132PSZrbk 4360484U, // VFMSUB132PSZrbkz 166180U, // VFMSUB132PSZrk 166180U, // VFMSUB132PSZrkz 256U, // VFMSUB132PSm 288U, // VFMSUB132PSr 576U, // VFMSUB132SDZm 576U, // VFMSUB132SDZm_Int 67876U, // VFMSUB132SDZm_Intk 67876U, // VFMSUB132SDZm_Intkz 288U, // VFMSUB132SDZr 288U, // VFMSUB132SDZr_Int 166180U, // VFMSUB132SDZr_Intk 166180U, // VFMSUB132SDZr_Intkz 288U, // VFMSUB132SDZrb 887072U, // VFMSUB132SDZrb_Int 4360484U, // VFMSUB132SDZrb_Intk 4360484U, // VFMSUB132SDZrb_Intkz 576U, // VFMSUB132SDm 576U, // VFMSUB132SDm_Int 288U, // VFMSUB132SDr 288U, // VFMSUB132SDr_Int 736U, // VFMSUB132SSZm 736U, // VFMSUB132SSZm_Int 395556U, // VFMSUB132SSZm_Intk 395556U, // VFMSUB132SSZm_Intkz 288U, // VFMSUB132SSZr 288U, // VFMSUB132SSZr_Int 166180U, // VFMSUB132SSZr_Intk 166180U, // VFMSUB132SSZr_Intkz 288U, // VFMSUB132SSZrb 887072U, // VFMSUB132SSZrb_Int 4360484U, // VFMSUB132SSZrb_Intk 4360484U, // VFMSUB132SSZrb_Intkz 736U, // VFMSUB132SSm 736U, // VFMSUB132SSm_Int 288U, // VFMSUB132SSr 288U, // VFMSUB132SSr_Int 608U, // VFMSUB213PDYm 288U, // VFMSUB213PDYr 256U, // VFMSUB213PDZ128m 4672U, // VFMSUB213PDZ128mb 1116452U, // VFMSUB213PDZ128mbk 1116452U, // VFMSUB213PDZ128mbkz 35108U, // VFMSUB213PDZ128mk 35108U, // VFMSUB213PDZ128mkz 288U, // VFMSUB213PDZ128r 166180U, // VFMSUB213PDZ128rk 166180U, // VFMSUB213PDZ128rkz 608U, // VFMSUB213PDZ256m 6720U, // VFMSUB213PDZ256mb 2165028U, // VFMSUB213PDZ256mbk 2165028U, // VFMSUB213PDZ256mbkz 231716U, // VFMSUB213PDZ256mk 231716U, // VFMSUB213PDZ256mkz 288U, // VFMSUB213PDZ256r 166180U, // VFMSUB213PDZ256rk 166180U, // VFMSUB213PDZ256rkz 1056U, // VFMSUB213PDZm 8768U, // VFMSUB213PDZmb 3213604U, // VFMSUB213PDZmbk 3213604U, // VFMSUB213PDZmbkz 297252U, // VFMSUB213PDZmk 297252U, // VFMSUB213PDZmkz 288U, // VFMSUB213PDZr 887072U, // VFMSUB213PDZrb 4360484U, // VFMSUB213PDZrbk 4360484U, // VFMSUB213PDZrbkz 166180U, // VFMSUB213PDZrk 166180U, // VFMSUB213PDZrkz 256U, // VFMSUB213PDm 288U, // VFMSUB213PDr 608U, // VFMSUB213PSYm 288U, // VFMSUB213PSYr 256U, // VFMSUB213PSZ128m 6880U, // VFMSUB213PSZ128mb 2492708U, // VFMSUB213PSZ128mbk 2492708U, // VFMSUB213PSZ128mbkz 35108U, // VFMSUB213PSZ128mk 35108U, // VFMSUB213PSZ128mkz 288U, // VFMSUB213PSZ128r 166180U, // VFMSUB213PSZ128rk 166180U, // VFMSUB213PSZ128rkz 608U, // VFMSUB213PSZ256m 8928U, // VFMSUB213PSZ256mb 3541284U, // VFMSUB213PSZ256mbk 3541284U, // VFMSUB213PSZ256mbkz 231716U, // VFMSUB213PSZ256mk 231716U, // VFMSUB213PSZ256mkz 288U, // VFMSUB213PSZ256r 166180U, // VFMSUB213PSZ256rk 166180U, // VFMSUB213PSZ256rkz 1056U, // VFMSUB213PSZm 10976U, // VFMSUB213PSZmb 5638436U, // VFMSUB213PSZmbk 5638436U, // VFMSUB213PSZmbkz 297252U, // VFMSUB213PSZmk 297252U, // VFMSUB213PSZmkz 288U, // VFMSUB213PSZr 887072U, // VFMSUB213PSZrb 4360484U, // VFMSUB213PSZrbk 4360484U, // VFMSUB213PSZrbkz 166180U, // VFMSUB213PSZrk 166180U, // VFMSUB213PSZrkz 256U, // VFMSUB213PSm 288U, // VFMSUB213PSr 576U, // VFMSUB213SDZm 576U, // VFMSUB213SDZm_Int 67876U, // VFMSUB213SDZm_Intk 67876U, // VFMSUB213SDZm_Intkz 288U, // VFMSUB213SDZr 288U, // VFMSUB213SDZr_Int 166180U, // VFMSUB213SDZr_Intk 166180U, // VFMSUB213SDZr_Intkz 288U, // VFMSUB213SDZrb 887072U, // VFMSUB213SDZrb_Int 4360484U, // VFMSUB213SDZrb_Intk 4360484U, // VFMSUB213SDZrb_Intkz 576U, // VFMSUB213SDm 576U, // VFMSUB213SDm_Int 288U, // VFMSUB213SDr 288U, // VFMSUB213SDr_Int 736U, // VFMSUB213SSZm 736U, // VFMSUB213SSZm_Int 395556U, // VFMSUB213SSZm_Intk 395556U, // VFMSUB213SSZm_Intkz 288U, // VFMSUB213SSZr 288U, // VFMSUB213SSZr_Int 166180U, // VFMSUB213SSZr_Intk 166180U, // VFMSUB213SSZr_Intkz 288U, // VFMSUB213SSZrb 887072U, // VFMSUB213SSZrb_Int 4360484U, // VFMSUB213SSZrb_Intk 4360484U, // VFMSUB213SSZrb_Intkz 736U, // VFMSUB213SSm 736U, // VFMSUB213SSm_Int 288U, // VFMSUB213SSr 288U, // VFMSUB213SSr_Int 608U, // VFMSUB231PDYm 288U, // VFMSUB231PDYr 256U, // VFMSUB231PDZ128m 4672U, // VFMSUB231PDZ128mb 1116452U, // VFMSUB231PDZ128mbk 1116452U, // VFMSUB231PDZ128mbkz 35108U, // VFMSUB231PDZ128mk 35108U, // VFMSUB231PDZ128mkz 288U, // VFMSUB231PDZ128r 166180U, // VFMSUB231PDZ128rk 166180U, // VFMSUB231PDZ128rkz 608U, // VFMSUB231PDZ256m 6720U, // VFMSUB231PDZ256mb 2165028U, // VFMSUB231PDZ256mbk 2165028U, // VFMSUB231PDZ256mbkz 231716U, // VFMSUB231PDZ256mk 231716U, // VFMSUB231PDZ256mkz 288U, // VFMSUB231PDZ256r 166180U, // VFMSUB231PDZ256rk 166180U, // VFMSUB231PDZ256rkz 1056U, // VFMSUB231PDZm 8768U, // VFMSUB231PDZmb 3213604U, // VFMSUB231PDZmbk 3213604U, // VFMSUB231PDZmbkz 297252U, // VFMSUB231PDZmk 297252U, // VFMSUB231PDZmkz 288U, // VFMSUB231PDZr 887072U, // VFMSUB231PDZrb 4360484U, // VFMSUB231PDZrbk 4360484U, // VFMSUB231PDZrbkz 166180U, // VFMSUB231PDZrk 166180U, // VFMSUB231PDZrkz 256U, // VFMSUB231PDm 288U, // VFMSUB231PDr 608U, // VFMSUB231PSYm 288U, // VFMSUB231PSYr 256U, // VFMSUB231PSZ128m 6880U, // VFMSUB231PSZ128mb 2492708U, // VFMSUB231PSZ128mbk 2492708U, // VFMSUB231PSZ128mbkz 35108U, // VFMSUB231PSZ128mk 35108U, // VFMSUB231PSZ128mkz 288U, // VFMSUB231PSZ128r 166180U, // VFMSUB231PSZ128rk 166180U, // VFMSUB231PSZ128rkz 608U, // VFMSUB231PSZ256m 8928U, // VFMSUB231PSZ256mb 3541284U, // VFMSUB231PSZ256mbk 3541284U, // VFMSUB231PSZ256mbkz 231716U, // VFMSUB231PSZ256mk 231716U, // VFMSUB231PSZ256mkz 288U, // VFMSUB231PSZ256r 166180U, // VFMSUB231PSZ256rk 166180U, // VFMSUB231PSZ256rkz 1056U, // VFMSUB231PSZm 10976U, // VFMSUB231PSZmb 5638436U, // VFMSUB231PSZmbk 5638436U, // VFMSUB231PSZmbkz 297252U, // VFMSUB231PSZmk 297252U, // VFMSUB231PSZmkz 288U, // VFMSUB231PSZr 887072U, // VFMSUB231PSZrb 4360484U, // VFMSUB231PSZrbk 4360484U, // VFMSUB231PSZrbkz 166180U, // VFMSUB231PSZrk 166180U, // VFMSUB231PSZrkz 256U, // VFMSUB231PSm 288U, // VFMSUB231PSr 576U, // VFMSUB231SDZm 576U, // VFMSUB231SDZm_Int 67876U, // VFMSUB231SDZm_Intk 67876U, // VFMSUB231SDZm_Intkz 288U, // VFMSUB231SDZr 288U, // VFMSUB231SDZr_Int 166180U, // VFMSUB231SDZr_Intk 166180U, // VFMSUB231SDZr_Intkz 288U, // VFMSUB231SDZrb 887072U, // VFMSUB231SDZrb_Int 4360484U, // VFMSUB231SDZrb_Intk 4360484U, // VFMSUB231SDZrb_Intkz 576U, // VFMSUB231SDm 576U, // VFMSUB231SDm_Int 288U, // VFMSUB231SDr 288U, // VFMSUB231SDr_Int 736U, // VFMSUB231SSZm 736U, // VFMSUB231SSZm_Int 395556U, // VFMSUB231SSZm_Intk 395556U, // VFMSUB231SSZm_Intkz 288U, // VFMSUB231SSZr 288U, // VFMSUB231SSZr_Int 166180U, // VFMSUB231SSZr_Intk 166180U, // VFMSUB231SSZr_Intkz 288U, // VFMSUB231SSZrb 887072U, // VFMSUB231SSZrb_Int 4360484U, // VFMSUB231SSZrb_Intk 4360484U, // VFMSUB231SSZrb_Intkz 736U, // VFMSUB231SSm 736U, // VFMSUB231SSm_Int 288U, // VFMSUB231SSr 288U, // VFMSUB231SSr_Int 608U, // VFMSUBADD132PDYm 288U, // VFMSUBADD132PDYr 256U, // VFMSUBADD132PDZ128m 4672U, // VFMSUBADD132PDZ128mb 1116452U, // VFMSUBADD132PDZ128mbk 1116452U, // VFMSUBADD132PDZ128mbkz 35108U, // VFMSUBADD132PDZ128mk 35108U, // VFMSUBADD132PDZ128mkz 288U, // VFMSUBADD132PDZ128r 166180U, // VFMSUBADD132PDZ128rk 166180U, // VFMSUBADD132PDZ128rkz 608U, // VFMSUBADD132PDZ256m 6720U, // VFMSUBADD132PDZ256mb 2165028U, // VFMSUBADD132PDZ256mbk 2165028U, // VFMSUBADD132PDZ256mbkz 231716U, // VFMSUBADD132PDZ256mk 231716U, // VFMSUBADD132PDZ256mkz 288U, // VFMSUBADD132PDZ256r 166180U, // VFMSUBADD132PDZ256rk 166180U, // VFMSUBADD132PDZ256rkz 1056U, // VFMSUBADD132PDZm 8768U, // VFMSUBADD132PDZmb 3213604U, // VFMSUBADD132PDZmbk 3213604U, // VFMSUBADD132PDZmbkz 297252U, // VFMSUBADD132PDZmk 297252U, // VFMSUBADD132PDZmkz 288U, // VFMSUBADD132PDZr 887072U, // VFMSUBADD132PDZrb 4360484U, // VFMSUBADD132PDZrbk 4360484U, // VFMSUBADD132PDZrbkz 166180U, // VFMSUBADD132PDZrk 166180U, // VFMSUBADD132PDZrkz 256U, // VFMSUBADD132PDm 288U, // VFMSUBADD132PDr 608U, // VFMSUBADD132PSYm 288U, // VFMSUBADD132PSYr 256U, // VFMSUBADD132PSZ128m 6880U, // VFMSUBADD132PSZ128mb 2492708U, // VFMSUBADD132PSZ128mbk 2492708U, // VFMSUBADD132PSZ128mbkz 35108U, // VFMSUBADD132PSZ128mk 35108U, // VFMSUBADD132PSZ128mkz 288U, // VFMSUBADD132PSZ128r 166180U, // VFMSUBADD132PSZ128rk 166180U, // VFMSUBADD132PSZ128rkz 608U, // VFMSUBADD132PSZ256m 8928U, // VFMSUBADD132PSZ256mb 3541284U, // VFMSUBADD132PSZ256mbk 3541284U, // VFMSUBADD132PSZ256mbkz 231716U, // VFMSUBADD132PSZ256mk 231716U, // VFMSUBADD132PSZ256mkz 288U, // VFMSUBADD132PSZ256r 166180U, // VFMSUBADD132PSZ256rk 166180U, // VFMSUBADD132PSZ256rkz 1056U, // VFMSUBADD132PSZm 10976U, // VFMSUBADD132PSZmb 5638436U, // VFMSUBADD132PSZmbk 5638436U, // VFMSUBADD132PSZmbkz 297252U, // VFMSUBADD132PSZmk 297252U, // VFMSUBADD132PSZmkz 288U, // VFMSUBADD132PSZr 887072U, // VFMSUBADD132PSZrb 4360484U, // VFMSUBADD132PSZrbk 4360484U, // VFMSUBADD132PSZrbkz 166180U, // VFMSUBADD132PSZrk 166180U, // VFMSUBADD132PSZrkz 256U, // VFMSUBADD132PSm 288U, // VFMSUBADD132PSr 608U, // VFMSUBADD213PDYm 288U, // VFMSUBADD213PDYr 256U, // VFMSUBADD213PDZ128m 4672U, // VFMSUBADD213PDZ128mb 1116452U, // VFMSUBADD213PDZ128mbk 1116452U, // VFMSUBADD213PDZ128mbkz 35108U, // VFMSUBADD213PDZ128mk 35108U, // VFMSUBADD213PDZ128mkz 288U, // VFMSUBADD213PDZ128r 166180U, // VFMSUBADD213PDZ128rk 166180U, // VFMSUBADD213PDZ128rkz 608U, // VFMSUBADD213PDZ256m 6720U, // VFMSUBADD213PDZ256mb 2165028U, // VFMSUBADD213PDZ256mbk 2165028U, // VFMSUBADD213PDZ256mbkz 231716U, // VFMSUBADD213PDZ256mk 231716U, // VFMSUBADD213PDZ256mkz 288U, // VFMSUBADD213PDZ256r 166180U, // VFMSUBADD213PDZ256rk 166180U, // VFMSUBADD213PDZ256rkz 1056U, // VFMSUBADD213PDZm 8768U, // VFMSUBADD213PDZmb 3213604U, // VFMSUBADD213PDZmbk 3213604U, // VFMSUBADD213PDZmbkz 297252U, // VFMSUBADD213PDZmk 297252U, // VFMSUBADD213PDZmkz 288U, // VFMSUBADD213PDZr 887072U, // VFMSUBADD213PDZrb 4360484U, // VFMSUBADD213PDZrbk 4360484U, // VFMSUBADD213PDZrbkz 166180U, // VFMSUBADD213PDZrk 166180U, // VFMSUBADD213PDZrkz 256U, // VFMSUBADD213PDm 288U, // VFMSUBADD213PDr 608U, // VFMSUBADD213PSYm 288U, // VFMSUBADD213PSYr 256U, // VFMSUBADD213PSZ128m 6880U, // VFMSUBADD213PSZ128mb 2492708U, // VFMSUBADD213PSZ128mbk 2492708U, // VFMSUBADD213PSZ128mbkz 35108U, // VFMSUBADD213PSZ128mk 35108U, // VFMSUBADD213PSZ128mkz 288U, // VFMSUBADD213PSZ128r 166180U, // VFMSUBADD213PSZ128rk 166180U, // VFMSUBADD213PSZ128rkz 608U, // VFMSUBADD213PSZ256m 8928U, // VFMSUBADD213PSZ256mb 3541284U, // VFMSUBADD213PSZ256mbk 3541284U, // VFMSUBADD213PSZ256mbkz 231716U, // VFMSUBADD213PSZ256mk 231716U, // VFMSUBADD213PSZ256mkz 288U, // VFMSUBADD213PSZ256r 166180U, // VFMSUBADD213PSZ256rk 166180U, // VFMSUBADD213PSZ256rkz 1056U, // VFMSUBADD213PSZm 10976U, // VFMSUBADD213PSZmb 5638436U, // VFMSUBADD213PSZmbk 5638436U, // VFMSUBADD213PSZmbkz 297252U, // VFMSUBADD213PSZmk 297252U, // VFMSUBADD213PSZmkz 288U, // VFMSUBADD213PSZr 887072U, // VFMSUBADD213PSZrb 4360484U, // VFMSUBADD213PSZrbk 4360484U, // VFMSUBADD213PSZrbkz 166180U, // VFMSUBADD213PSZrk 166180U, // VFMSUBADD213PSZrkz 256U, // VFMSUBADD213PSm 288U, // VFMSUBADD213PSr 608U, // VFMSUBADD231PDYm 288U, // VFMSUBADD231PDYr 256U, // VFMSUBADD231PDZ128m 4672U, // VFMSUBADD231PDZ128mb 1116452U, // VFMSUBADD231PDZ128mbk 1116452U, // VFMSUBADD231PDZ128mbkz 35108U, // VFMSUBADD231PDZ128mk 35108U, // VFMSUBADD231PDZ128mkz 288U, // VFMSUBADD231PDZ128r 166180U, // VFMSUBADD231PDZ128rk 166180U, // VFMSUBADD231PDZ128rkz 608U, // VFMSUBADD231PDZ256m 6720U, // VFMSUBADD231PDZ256mb 2165028U, // VFMSUBADD231PDZ256mbk 2165028U, // VFMSUBADD231PDZ256mbkz 231716U, // VFMSUBADD231PDZ256mk 231716U, // VFMSUBADD231PDZ256mkz 288U, // VFMSUBADD231PDZ256r 166180U, // VFMSUBADD231PDZ256rk 166180U, // VFMSUBADD231PDZ256rkz 1056U, // VFMSUBADD231PDZm 8768U, // VFMSUBADD231PDZmb 3213604U, // VFMSUBADD231PDZmbk 3213604U, // VFMSUBADD231PDZmbkz 297252U, // VFMSUBADD231PDZmk 297252U, // VFMSUBADD231PDZmkz 288U, // VFMSUBADD231PDZr 887072U, // VFMSUBADD231PDZrb 4360484U, // VFMSUBADD231PDZrbk 4360484U, // VFMSUBADD231PDZrbkz 166180U, // VFMSUBADD231PDZrk 166180U, // VFMSUBADD231PDZrkz 256U, // VFMSUBADD231PDm 288U, // VFMSUBADD231PDr 608U, // VFMSUBADD231PSYm 288U, // VFMSUBADD231PSYr 256U, // VFMSUBADD231PSZ128m 6880U, // VFMSUBADD231PSZ128mb 2492708U, // VFMSUBADD231PSZ128mbk 2492708U, // VFMSUBADD231PSZ128mbkz 35108U, // VFMSUBADD231PSZ128mk 35108U, // VFMSUBADD231PSZ128mkz 288U, // VFMSUBADD231PSZ128r 166180U, // VFMSUBADD231PSZ128rk 166180U, // VFMSUBADD231PSZ128rkz 608U, // VFMSUBADD231PSZ256m 8928U, // VFMSUBADD231PSZ256mb 3541284U, // VFMSUBADD231PSZ256mbk 3541284U, // VFMSUBADD231PSZ256mbkz 231716U, // VFMSUBADD231PSZ256mk 231716U, // VFMSUBADD231PSZ256mkz 288U, // VFMSUBADD231PSZ256r 166180U, // VFMSUBADD231PSZ256rk 166180U, // VFMSUBADD231PSZ256rkz 1056U, // VFMSUBADD231PSZm 10976U, // VFMSUBADD231PSZmb 5638436U, // VFMSUBADD231PSZmbk 5638436U, // VFMSUBADD231PSZmbkz 297252U, // VFMSUBADD231PSZmk 297252U, // VFMSUBADD231PSZmkz 288U, // VFMSUBADD231PSZr 887072U, // VFMSUBADD231PSZrb 4360484U, // VFMSUBADD231PSZrbk 4360484U, // VFMSUBADD231PSZrbkz 166180U, // VFMSUBADD231PSZrk 166180U, // VFMSUBADD231PSZrkz 256U, // VFMSUBADD231PSm 288U, // VFMSUBADD231PSr 854336U, // VFMSUBADDPD4Ymr 264288U, // VFMSUBADDPD4Yrm 198752U, // VFMSUBADDPD4Yrr 198752U, // VFMSUBADDPD4Yrr_REV 854368U, // VFMSUBADDPD4mr 133216U, // VFMSUBADDPD4rm 198752U, // VFMSUBADDPD4rr 198752U, // VFMSUBADDPD4rr_REV 854336U, // VFMSUBADDPS4Ymr 264288U, // VFMSUBADDPS4Yrm 198752U, // VFMSUBADDPS4Yrr 198752U, // VFMSUBADDPS4Yrr_REV 854368U, // VFMSUBADDPS4mr 133216U, // VFMSUBADDPS4rm 198752U, // VFMSUBADDPS4rr 198752U, // VFMSUBADDPS4rr_REV 854336U, // VFMSUBPD4Ymr 264288U, // VFMSUBPD4Yrm 198752U, // VFMSUBPD4Yrr 198752U, // VFMSUBPD4Yrr_REV 854368U, // VFMSUBPD4mr 133216U, // VFMSUBPD4rm 198752U, // VFMSUBPD4rr 198752U, // VFMSUBPD4rr_REV 854336U, // VFMSUBPS4Ymr 264288U, // VFMSUBPS4Yrm 198752U, // VFMSUBPS4Yrr 198752U, // VFMSUBPS4Yrr_REV 854368U, // VFMSUBPS4mr 133216U, // VFMSUBPS4rm 198752U, // VFMSUBPS4rr 198752U, // VFMSUBPS4rr_REV 854400U, // VFMSUBSD4mr 854400U, // VFMSUBSD4mr_Int 100448U, // VFMSUBSD4rm 100448U, // VFMSUBSD4rm_Int 198752U, // VFMSUBSD4rr 198752U, // VFMSUBSD4rr_Int 198752U, // VFMSUBSD4rr_Int_REV 198752U, // VFMSUBSD4rr_REV 854464U, // VFMSUBSS4mr 854464U, // VFMSUBSS4mr_Int 428128U, // VFMSUBSS4rm 428128U, // VFMSUBSS4rm_Int 198752U, // VFMSUBSS4rr 198752U, // VFMSUBSS4rr_Int 198752U, // VFMSUBSS4rr_Int_REV 198752U, // VFMSUBSS4rr_REV 608U, // VFNMADD132PDYm 288U, // VFNMADD132PDYr 256U, // VFNMADD132PDZ128m 4672U, // VFNMADD132PDZ128mb 1116452U, // VFNMADD132PDZ128mbk 1116452U, // VFNMADD132PDZ128mbkz 35108U, // VFNMADD132PDZ128mk 35108U, // VFNMADD132PDZ128mkz 288U, // VFNMADD132PDZ128r 166180U, // VFNMADD132PDZ128rk 166180U, // VFNMADD132PDZ128rkz 608U, // VFNMADD132PDZ256m 6720U, // VFNMADD132PDZ256mb 2165028U, // VFNMADD132PDZ256mbk 2165028U, // VFNMADD132PDZ256mbkz 231716U, // VFNMADD132PDZ256mk 231716U, // VFNMADD132PDZ256mkz 288U, // VFNMADD132PDZ256r 166180U, // VFNMADD132PDZ256rk 166180U, // VFNMADD132PDZ256rkz 1056U, // VFNMADD132PDZm 8768U, // VFNMADD132PDZmb 3213604U, // VFNMADD132PDZmbk 3213604U, // VFNMADD132PDZmbkz 297252U, // VFNMADD132PDZmk 297252U, // VFNMADD132PDZmkz 288U, // VFNMADD132PDZr 887072U, // VFNMADD132PDZrb 4360484U, // VFNMADD132PDZrbk 4360484U, // VFNMADD132PDZrbkz 166180U, // VFNMADD132PDZrk 166180U, // VFNMADD132PDZrkz 256U, // VFNMADD132PDm 288U, // VFNMADD132PDr 608U, // VFNMADD132PSYm 288U, // VFNMADD132PSYr 256U, // VFNMADD132PSZ128m 6880U, // VFNMADD132PSZ128mb 2492708U, // VFNMADD132PSZ128mbk 2492708U, // VFNMADD132PSZ128mbkz 35108U, // VFNMADD132PSZ128mk 35108U, // VFNMADD132PSZ128mkz 288U, // VFNMADD132PSZ128r 166180U, // VFNMADD132PSZ128rk 166180U, // VFNMADD132PSZ128rkz 608U, // VFNMADD132PSZ256m 8928U, // VFNMADD132PSZ256mb 3541284U, // VFNMADD132PSZ256mbk 3541284U, // VFNMADD132PSZ256mbkz 231716U, // VFNMADD132PSZ256mk 231716U, // VFNMADD132PSZ256mkz 288U, // VFNMADD132PSZ256r 166180U, // VFNMADD132PSZ256rk 166180U, // VFNMADD132PSZ256rkz 1056U, // VFNMADD132PSZm 10976U, // VFNMADD132PSZmb 5638436U, // VFNMADD132PSZmbk 5638436U, // VFNMADD132PSZmbkz 297252U, // VFNMADD132PSZmk 297252U, // VFNMADD132PSZmkz 288U, // VFNMADD132PSZr 887072U, // VFNMADD132PSZrb 4360484U, // VFNMADD132PSZrbk 4360484U, // VFNMADD132PSZrbkz 166180U, // VFNMADD132PSZrk 166180U, // VFNMADD132PSZrkz 256U, // VFNMADD132PSm 288U, // VFNMADD132PSr 576U, // VFNMADD132SDZm 576U, // VFNMADD132SDZm_Int 67876U, // VFNMADD132SDZm_Intk 67876U, // VFNMADD132SDZm_Intkz 288U, // VFNMADD132SDZr 288U, // VFNMADD132SDZr_Int 166180U, // VFNMADD132SDZr_Intk 166180U, // VFNMADD132SDZr_Intkz 288U, // VFNMADD132SDZrb 887072U, // VFNMADD132SDZrb_Int 4360484U, // VFNMADD132SDZrb_Intk 4360484U, // VFNMADD132SDZrb_Intkz 576U, // VFNMADD132SDm 576U, // VFNMADD132SDm_Int 288U, // VFNMADD132SDr 288U, // VFNMADD132SDr_Int 736U, // VFNMADD132SSZm 736U, // VFNMADD132SSZm_Int 395556U, // VFNMADD132SSZm_Intk 395556U, // VFNMADD132SSZm_Intkz 288U, // VFNMADD132SSZr 288U, // VFNMADD132SSZr_Int 166180U, // VFNMADD132SSZr_Intk 166180U, // VFNMADD132SSZr_Intkz 288U, // VFNMADD132SSZrb 887072U, // VFNMADD132SSZrb_Int 4360484U, // VFNMADD132SSZrb_Intk 4360484U, // VFNMADD132SSZrb_Intkz 736U, // VFNMADD132SSm 736U, // VFNMADD132SSm_Int 288U, // VFNMADD132SSr 288U, // VFNMADD132SSr_Int 608U, // VFNMADD213PDYm 288U, // VFNMADD213PDYr 256U, // VFNMADD213PDZ128m 4672U, // VFNMADD213PDZ128mb 1116452U, // VFNMADD213PDZ128mbk 1116452U, // VFNMADD213PDZ128mbkz 35108U, // VFNMADD213PDZ128mk 35108U, // VFNMADD213PDZ128mkz 288U, // VFNMADD213PDZ128r 166180U, // VFNMADD213PDZ128rk 166180U, // VFNMADD213PDZ128rkz 608U, // VFNMADD213PDZ256m 6720U, // VFNMADD213PDZ256mb 2165028U, // VFNMADD213PDZ256mbk 2165028U, // VFNMADD213PDZ256mbkz 231716U, // VFNMADD213PDZ256mk 231716U, // VFNMADD213PDZ256mkz 288U, // VFNMADD213PDZ256r 166180U, // VFNMADD213PDZ256rk 166180U, // VFNMADD213PDZ256rkz 1056U, // VFNMADD213PDZm 8768U, // VFNMADD213PDZmb 3213604U, // VFNMADD213PDZmbk 3213604U, // VFNMADD213PDZmbkz 297252U, // VFNMADD213PDZmk 297252U, // VFNMADD213PDZmkz 288U, // VFNMADD213PDZr 887072U, // VFNMADD213PDZrb 4360484U, // VFNMADD213PDZrbk 4360484U, // VFNMADD213PDZrbkz 166180U, // VFNMADD213PDZrk 166180U, // VFNMADD213PDZrkz 256U, // VFNMADD213PDm 288U, // VFNMADD213PDr 608U, // VFNMADD213PSYm 288U, // VFNMADD213PSYr 256U, // VFNMADD213PSZ128m 6880U, // VFNMADD213PSZ128mb 2492708U, // VFNMADD213PSZ128mbk 2492708U, // VFNMADD213PSZ128mbkz 35108U, // VFNMADD213PSZ128mk 35108U, // VFNMADD213PSZ128mkz 288U, // VFNMADD213PSZ128r 166180U, // VFNMADD213PSZ128rk 166180U, // VFNMADD213PSZ128rkz 608U, // VFNMADD213PSZ256m 8928U, // VFNMADD213PSZ256mb 3541284U, // VFNMADD213PSZ256mbk 3541284U, // VFNMADD213PSZ256mbkz 231716U, // VFNMADD213PSZ256mk 231716U, // VFNMADD213PSZ256mkz 288U, // VFNMADD213PSZ256r 166180U, // VFNMADD213PSZ256rk 166180U, // VFNMADD213PSZ256rkz 1056U, // VFNMADD213PSZm 10976U, // VFNMADD213PSZmb 5638436U, // VFNMADD213PSZmbk 5638436U, // VFNMADD213PSZmbkz 297252U, // VFNMADD213PSZmk 297252U, // VFNMADD213PSZmkz 288U, // VFNMADD213PSZr 887072U, // VFNMADD213PSZrb 4360484U, // VFNMADD213PSZrbk 4360484U, // VFNMADD213PSZrbkz 166180U, // VFNMADD213PSZrk 166180U, // VFNMADD213PSZrkz 256U, // VFNMADD213PSm 288U, // VFNMADD213PSr 576U, // VFNMADD213SDZm 576U, // VFNMADD213SDZm_Int 67876U, // VFNMADD213SDZm_Intk 67876U, // VFNMADD213SDZm_Intkz 288U, // VFNMADD213SDZr 288U, // VFNMADD213SDZr_Int 166180U, // VFNMADD213SDZr_Intk 166180U, // VFNMADD213SDZr_Intkz 288U, // VFNMADD213SDZrb 887072U, // VFNMADD213SDZrb_Int 4360484U, // VFNMADD213SDZrb_Intk 4360484U, // VFNMADD213SDZrb_Intkz 576U, // VFNMADD213SDm 576U, // VFNMADD213SDm_Int 288U, // VFNMADD213SDr 288U, // VFNMADD213SDr_Int 736U, // VFNMADD213SSZm 736U, // VFNMADD213SSZm_Int 395556U, // VFNMADD213SSZm_Intk 395556U, // VFNMADD213SSZm_Intkz 288U, // VFNMADD213SSZr 288U, // VFNMADD213SSZr_Int 166180U, // VFNMADD213SSZr_Intk 166180U, // VFNMADD213SSZr_Intkz 288U, // VFNMADD213SSZrb 887072U, // VFNMADD213SSZrb_Int 4360484U, // VFNMADD213SSZrb_Intk 4360484U, // VFNMADD213SSZrb_Intkz 736U, // VFNMADD213SSm 736U, // VFNMADD213SSm_Int 288U, // VFNMADD213SSr 288U, // VFNMADD213SSr_Int 608U, // VFNMADD231PDYm 288U, // VFNMADD231PDYr 256U, // VFNMADD231PDZ128m 4672U, // VFNMADD231PDZ128mb 1116452U, // VFNMADD231PDZ128mbk 1116452U, // VFNMADD231PDZ128mbkz 35108U, // VFNMADD231PDZ128mk 35108U, // VFNMADD231PDZ128mkz 288U, // VFNMADD231PDZ128r 166180U, // VFNMADD231PDZ128rk 166180U, // VFNMADD231PDZ128rkz 608U, // VFNMADD231PDZ256m 6720U, // VFNMADD231PDZ256mb 2165028U, // VFNMADD231PDZ256mbk 2165028U, // VFNMADD231PDZ256mbkz 231716U, // VFNMADD231PDZ256mk 231716U, // VFNMADD231PDZ256mkz 288U, // VFNMADD231PDZ256r 166180U, // VFNMADD231PDZ256rk 166180U, // VFNMADD231PDZ256rkz 1056U, // VFNMADD231PDZm 8768U, // VFNMADD231PDZmb 3213604U, // VFNMADD231PDZmbk 3213604U, // VFNMADD231PDZmbkz 297252U, // VFNMADD231PDZmk 297252U, // VFNMADD231PDZmkz 288U, // VFNMADD231PDZr 887072U, // VFNMADD231PDZrb 4360484U, // VFNMADD231PDZrbk 4360484U, // VFNMADD231PDZrbkz 166180U, // VFNMADD231PDZrk 166180U, // VFNMADD231PDZrkz 256U, // VFNMADD231PDm 288U, // VFNMADD231PDr 608U, // VFNMADD231PSYm 288U, // VFNMADD231PSYr 256U, // VFNMADD231PSZ128m 6880U, // VFNMADD231PSZ128mb 2492708U, // VFNMADD231PSZ128mbk 2492708U, // VFNMADD231PSZ128mbkz 35108U, // VFNMADD231PSZ128mk 35108U, // VFNMADD231PSZ128mkz 288U, // VFNMADD231PSZ128r 166180U, // VFNMADD231PSZ128rk 166180U, // VFNMADD231PSZ128rkz 608U, // VFNMADD231PSZ256m 8928U, // VFNMADD231PSZ256mb 3541284U, // VFNMADD231PSZ256mbk 3541284U, // VFNMADD231PSZ256mbkz 231716U, // VFNMADD231PSZ256mk 231716U, // VFNMADD231PSZ256mkz 288U, // VFNMADD231PSZ256r 166180U, // VFNMADD231PSZ256rk 166180U, // VFNMADD231PSZ256rkz 1056U, // VFNMADD231PSZm 10976U, // VFNMADD231PSZmb 5638436U, // VFNMADD231PSZmbk 5638436U, // VFNMADD231PSZmbkz 297252U, // VFNMADD231PSZmk 297252U, // VFNMADD231PSZmkz 288U, // VFNMADD231PSZr 887072U, // VFNMADD231PSZrb 4360484U, // VFNMADD231PSZrbk 4360484U, // VFNMADD231PSZrbkz 166180U, // VFNMADD231PSZrk 166180U, // VFNMADD231PSZrkz 256U, // VFNMADD231PSm 288U, // VFNMADD231PSr 576U, // VFNMADD231SDZm 576U, // VFNMADD231SDZm_Int 67876U, // VFNMADD231SDZm_Intk 67876U, // VFNMADD231SDZm_Intkz 288U, // VFNMADD231SDZr 288U, // VFNMADD231SDZr_Int 166180U, // VFNMADD231SDZr_Intk 166180U, // VFNMADD231SDZr_Intkz 288U, // VFNMADD231SDZrb 887072U, // VFNMADD231SDZrb_Int 4360484U, // VFNMADD231SDZrb_Intk 4360484U, // VFNMADD231SDZrb_Intkz 576U, // VFNMADD231SDm 576U, // VFNMADD231SDm_Int 288U, // VFNMADD231SDr 288U, // VFNMADD231SDr_Int 736U, // VFNMADD231SSZm 736U, // VFNMADD231SSZm_Int 395556U, // VFNMADD231SSZm_Intk 395556U, // VFNMADD231SSZm_Intkz 288U, // VFNMADD231SSZr 288U, // VFNMADD231SSZr_Int 166180U, // VFNMADD231SSZr_Intk 166180U, // VFNMADD231SSZr_Intkz 288U, // VFNMADD231SSZrb 887072U, // VFNMADD231SSZrb_Int 4360484U, // VFNMADD231SSZrb_Intk 4360484U, // VFNMADD231SSZrb_Intkz 736U, // VFNMADD231SSm 736U, // VFNMADD231SSm_Int 288U, // VFNMADD231SSr 288U, // VFNMADD231SSr_Int 854336U, // VFNMADDPD4Ymr 264288U, // VFNMADDPD4Yrm 198752U, // VFNMADDPD4Yrr 198752U, // VFNMADDPD4Yrr_REV 854368U, // VFNMADDPD4mr 133216U, // VFNMADDPD4rm 198752U, // VFNMADDPD4rr 198752U, // VFNMADDPD4rr_REV 854336U, // VFNMADDPS4Ymr 264288U, // VFNMADDPS4Yrm 198752U, // VFNMADDPS4Yrr 198752U, // VFNMADDPS4Yrr_REV 854368U, // VFNMADDPS4mr 133216U, // VFNMADDPS4rm 198752U, // VFNMADDPS4rr 198752U, // VFNMADDPS4rr_REV 854400U, // VFNMADDSD4mr 854400U, // VFNMADDSD4mr_Int 100448U, // VFNMADDSD4rm 100448U, // VFNMADDSD4rm_Int 198752U, // VFNMADDSD4rr 198752U, // VFNMADDSD4rr_Int 198752U, // VFNMADDSD4rr_Int_REV 198752U, // VFNMADDSD4rr_REV 854464U, // VFNMADDSS4mr 854464U, // VFNMADDSS4mr_Int 428128U, // VFNMADDSS4rm 428128U, // VFNMADDSS4rm_Int 198752U, // VFNMADDSS4rr 198752U, // VFNMADDSS4rr_Int 198752U, // VFNMADDSS4rr_Int_REV 198752U, // VFNMADDSS4rr_REV 608U, // VFNMSUB132PDYm 288U, // VFNMSUB132PDYr 256U, // VFNMSUB132PDZ128m 4672U, // VFNMSUB132PDZ128mb 1116452U, // VFNMSUB132PDZ128mbk 1116452U, // VFNMSUB132PDZ128mbkz 35108U, // VFNMSUB132PDZ128mk 35108U, // VFNMSUB132PDZ128mkz 288U, // VFNMSUB132PDZ128r 166180U, // VFNMSUB132PDZ128rk 166180U, // VFNMSUB132PDZ128rkz 608U, // VFNMSUB132PDZ256m 6720U, // VFNMSUB132PDZ256mb 2165028U, // VFNMSUB132PDZ256mbk 2165028U, // VFNMSUB132PDZ256mbkz 231716U, // VFNMSUB132PDZ256mk 231716U, // VFNMSUB132PDZ256mkz 288U, // VFNMSUB132PDZ256r 166180U, // VFNMSUB132PDZ256rk 166180U, // VFNMSUB132PDZ256rkz 1056U, // VFNMSUB132PDZm 8768U, // VFNMSUB132PDZmb 3213604U, // VFNMSUB132PDZmbk 3213604U, // VFNMSUB132PDZmbkz 297252U, // VFNMSUB132PDZmk 297252U, // VFNMSUB132PDZmkz 288U, // VFNMSUB132PDZr 887072U, // VFNMSUB132PDZrb 4360484U, // VFNMSUB132PDZrbk 4360484U, // VFNMSUB132PDZrbkz 166180U, // VFNMSUB132PDZrk 166180U, // VFNMSUB132PDZrkz 256U, // VFNMSUB132PDm 288U, // VFNMSUB132PDr 608U, // VFNMSUB132PSYm 288U, // VFNMSUB132PSYr 256U, // VFNMSUB132PSZ128m 6880U, // VFNMSUB132PSZ128mb 2492708U, // VFNMSUB132PSZ128mbk 2492708U, // VFNMSUB132PSZ128mbkz 35108U, // VFNMSUB132PSZ128mk 35108U, // VFNMSUB132PSZ128mkz 288U, // VFNMSUB132PSZ128r 166180U, // VFNMSUB132PSZ128rk 166180U, // VFNMSUB132PSZ128rkz 608U, // VFNMSUB132PSZ256m 8928U, // VFNMSUB132PSZ256mb 3541284U, // VFNMSUB132PSZ256mbk 3541284U, // VFNMSUB132PSZ256mbkz 231716U, // VFNMSUB132PSZ256mk 231716U, // VFNMSUB132PSZ256mkz 288U, // VFNMSUB132PSZ256r 166180U, // VFNMSUB132PSZ256rk 166180U, // VFNMSUB132PSZ256rkz 1056U, // VFNMSUB132PSZm 10976U, // VFNMSUB132PSZmb 5638436U, // VFNMSUB132PSZmbk 5638436U, // VFNMSUB132PSZmbkz 297252U, // VFNMSUB132PSZmk 297252U, // VFNMSUB132PSZmkz 288U, // VFNMSUB132PSZr 887072U, // VFNMSUB132PSZrb 4360484U, // VFNMSUB132PSZrbk 4360484U, // VFNMSUB132PSZrbkz 166180U, // VFNMSUB132PSZrk 166180U, // VFNMSUB132PSZrkz 256U, // VFNMSUB132PSm 288U, // VFNMSUB132PSr 576U, // VFNMSUB132SDZm 576U, // VFNMSUB132SDZm_Int 67876U, // VFNMSUB132SDZm_Intk 67876U, // VFNMSUB132SDZm_Intkz 288U, // VFNMSUB132SDZr 288U, // VFNMSUB132SDZr_Int 166180U, // VFNMSUB132SDZr_Intk 166180U, // VFNMSUB132SDZr_Intkz 288U, // VFNMSUB132SDZrb 887072U, // VFNMSUB132SDZrb_Int 4360484U, // VFNMSUB132SDZrb_Intk 4360484U, // VFNMSUB132SDZrb_Intkz 576U, // VFNMSUB132SDm 576U, // VFNMSUB132SDm_Int 288U, // VFNMSUB132SDr 288U, // VFNMSUB132SDr_Int 736U, // VFNMSUB132SSZm 736U, // VFNMSUB132SSZm_Int 395556U, // VFNMSUB132SSZm_Intk 395556U, // VFNMSUB132SSZm_Intkz 288U, // VFNMSUB132SSZr 288U, // VFNMSUB132SSZr_Int 166180U, // VFNMSUB132SSZr_Intk 166180U, // VFNMSUB132SSZr_Intkz 288U, // VFNMSUB132SSZrb 887072U, // VFNMSUB132SSZrb_Int 4360484U, // VFNMSUB132SSZrb_Intk 4360484U, // VFNMSUB132SSZrb_Intkz 736U, // VFNMSUB132SSm 736U, // VFNMSUB132SSm_Int 288U, // VFNMSUB132SSr 288U, // VFNMSUB132SSr_Int 608U, // VFNMSUB213PDYm 288U, // VFNMSUB213PDYr 256U, // VFNMSUB213PDZ128m 4672U, // VFNMSUB213PDZ128mb 1116452U, // VFNMSUB213PDZ128mbk 1116452U, // VFNMSUB213PDZ128mbkz 35108U, // VFNMSUB213PDZ128mk 35108U, // VFNMSUB213PDZ128mkz 288U, // VFNMSUB213PDZ128r 166180U, // VFNMSUB213PDZ128rk 166180U, // VFNMSUB213PDZ128rkz 608U, // VFNMSUB213PDZ256m 6720U, // VFNMSUB213PDZ256mb 2165028U, // VFNMSUB213PDZ256mbk 2165028U, // VFNMSUB213PDZ256mbkz 231716U, // VFNMSUB213PDZ256mk 231716U, // VFNMSUB213PDZ256mkz 288U, // VFNMSUB213PDZ256r 166180U, // VFNMSUB213PDZ256rk 166180U, // VFNMSUB213PDZ256rkz 1056U, // VFNMSUB213PDZm 8768U, // VFNMSUB213PDZmb 3213604U, // VFNMSUB213PDZmbk 3213604U, // VFNMSUB213PDZmbkz 297252U, // VFNMSUB213PDZmk 297252U, // VFNMSUB213PDZmkz 288U, // VFNMSUB213PDZr 887072U, // VFNMSUB213PDZrb 4360484U, // VFNMSUB213PDZrbk 4360484U, // VFNMSUB213PDZrbkz 166180U, // VFNMSUB213PDZrk 166180U, // VFNMSUB213PDZrkz 256U, // VFNMSUB213PDm 288U, // VFNMSUB213PDr 608U, // VFNMSUB213PSYm 288U, // VFNMSUB213PSYr 256U, // VFNMSUB213PSZ128m 6880U, // VFNMSUB213PSZ128mb 2492708U, // VFNMSUB213PSZ128mbk 2492708U, // VFNMSUB213PSZ128mbkz 35108U, // VFNMSUB213PSZ128mk 35108U, // VFNMSUB213PSZ128mkz 288U, // VFNMSUB213PSZ128r 166180U, // VFNMSUB213PSZ128rk 166180U, // VFNMSUB213PSZ128rkz 608U, // VFNMSUB213PSZ256m 8928U, // VFNMSUB213PSZ256mb 3541284U, // VFNMSUB213PSZ256mbk 3541284U, // VFNMSUB213PSZ256mbkz 231716U, // VFNMSUB213PSZ256mk 231716U, // VFNMSUB213PSZ256mkz 288U, // VFNMSUB213PSZ256r 166180U, // VFNMSUB213PSZ256rk 166180U, // VFNMSUB213PSZ256rkz 1056U, // VFNMSUB213PSZm 10976U, // VFNMSUB213PSZmb 5638436U, // VFNMSUB213PSZmbk 5638436U, // VFNMSUB213PSZmbkz 297252U, // VFNMSUB213PSZmk 297252U, // VFNMSUB213PSZmkz 288U, // VFNMSUB213PSZr 887072U, // VFNMSUB213PSZrb 4360484U, // VFNMSUB213PSZrbk 4360484U, // VFNMSUB213PSZrbkz 166180U, // VFNMSUB213PSZrk 166180U, // VFNMSUB213PSZrkz 256U, // VFNMSUB213PSm 288U, // VFNMSUB213PSr 576U, // VFNMSUB213SDZm 576U, // VFNMSUB213SDZm_Int 67876U, // VFNMSUB213SDZm_Intk 67876U, // VFNMSUB213SDZm_Intkz 288U, // VFNMSUB213SDZr 288U, // VFNMSUB213SDZr_Int 166180U, // VFNMSUB213SDZr_Intk 166180U, // VFNMSUB213SDZr_Intkz 288U, // VFNMSUB213SDZrb 887072U, // VFNMSUB213SDZrb_Int 4360484U, // VFNMSUB213SDZrb_Intk 4360484U, // VFNMSUB213SDZrb_Intkz 576U, // VFNMSUB213SDm 576U, // VFNMSUB213SDm_Int 288U, // VFNMSUB213SDr 288U, // VFNMSUB213SDr_Int 736U, // VFNMSUB213SSZm 736U, // VFNMSUB213SSZm_Int 395556U, // VFNMSUB213SSZm_Intk 395556U, // VFNMSUB213SSZm_Intkz 288U, // VFNMSUB213SSZr 288U, // VFNMSUB213SSZr_Int 166180U, // VFNMSUB213SSZr_Intk 166180U, // VFNMSUB213SSZr_Intkz 288U, // VFNMSUB213SSZrb 887072U, // VFNMSUB213SSZrb_Int 4360484U, // VFNMSUB213SSZrb_Intk 4360484U, // VFNMSUB213SSZrb_Intkz 736U, // VFNMSUB213SSm 736U, // VFNMSUB213SSm_Int 288U, // VFNMSUB213SSr 288U, // VFNMSUB213SSr_Int 608U, // VFNMSUB231PDYm 288U, // VFNMSUB231PDYr 256U, // VFNMSUB231PDZ128m 4672U, // VFNMSUB231PDZ128mb 1116452U, // VFNMSUB231PDZ128mbk 1116452U, // VFNMSUB231PDZ128mbkz 35108U, // VFNMSUB231PDZ128mk 35108U, // VFNMSUB231PDZ128mkz 288U, // VFNMSUB231PDZ128r 166180U, // VFNMSUB231PDZ128rk 166180U, // VFNMSUB231PDZ128rkz 608U, // VFNMSUB231PDZ256m 6720U, // VFNMSUB231PDZ256mb 2165028U, // VFNMSUB231PDZ256mbk 2165028U, // VFNMSUB231PDZ256mbkz 231716U, // VFNMSUB231PDZ256mk 231716U, // VFNMSUB231PDZ256mkz 288U, // VFNMSUB231PDZ256r 166180U, // VFNMSUB231PDZ256rk 166180U, // VFNMSUB231PDZ256rkz 1056U, // VFNMSUB231PDZm 8768U, // VFNMSUB231PDZmb 3213604U, // VFNMSUB231PDZmbk 3213604U, // VFNMSUB231PDZmbkz 297252U, // VFNMSUB231PDZmk 297252U, // VFNMSUB231PDZmkz 288U, // VFNMSUB231PDZr 887072U, // VFNMSUB231PDZrb 4360484U, // VFNMSUB231PDZrbk 4360484U, // VFNMSUB231PDZrbkz 166180U, // VFNMSUB231PDZrk 166180U, // VFNMSUB231PDZrkz 256U, // VFNMSUB231PDm 288U, // VFNMSUB231PDr 608U, // VFNMSUB231PSYm 288U, // VFNMSUB231PSYr 256U, // VFNMSUB231PSZ128m 6880U, // VFNMSUB231PSZ128mb 2492708U, // VFNMSUB231PSZ128mbk 2492708U, // VFNMSUB231PSZ128mbkz 35108U, // VFNMSUB231PSZ128mk 35108U, // VFNMSUB231PSZ128mkz 288U, // VFNMSUB231PSZ128r 166180U, // VFNMSUB231PSZ128rk 166180U, // VFNMSUB231PSZ128rkz 608U, // VFNMSUB231PSZ256m 8928U, // VFNMSUB231PSZ256mb 3541284U, // VFNMSUB231PSZ256mbk 3541284U, // VFNMSUB231PSZ256mbkz 231716U, // VFNMSUB231PSZ256mk 231716U, // VFNMSUB231PSZ256mkz 288U, // VFNMSUB231PSZ256r 166180U, // VFNMSUB231PSZ256rk 166180U, // VFNMSUB231PSZ256rkz 1056U, // VFNMSUB231PSZm 10976U, // VFNMSUB231PSZmb 5638436U, // VFNMSUB231PSZmbk 5638436U, // VFNMSUB231PSZmbkz 297252U, // VFNMSUB231PSZmk 297252U, // VFNMSUB231PSZmkz 288U, // VFNMSUB231PSZr 887072U, // VFNMSUB231PSZrb 4360484U, // VFNMSUB231PSZrbk 4360484U, // VFNMSUB231PSZrbkz 166180U, // VFNMSUB231PSZrk 166180U, // VFNMSUB231PSZrkz 256U, // VFNMSUB231PSm 288U, // VFNMSUB231PSr 576U, // VFNMSUB231SDZm 576U, // VFNMSUB231SDZm_Int 67876U, // VFNMSUB231SDZm_Intk 67876U, // VFNMSUB231SDZm_Intkz 288U, // VFNMSUB231SDZr 288U, // VFNMSUB231SDZr_Int 166180U, // VFNMSUB231SDZr_Intk 166180U, // VFNMSUB231SDZr_Intkz 288U, // VFNMSUB231SDZrb 887072U, // VFNMSUB231SDZrb_Int 4360484U, // VFNMSUB231SDZrb_Intk 4360484U, // VFNMSUB231SDZrb_Intkz 576U, // VFNMSUB231SDm 576U, // VFNMSUB231SDm_Int 288U, // VFNMSUB231SDr 288U, // VFNMSUB231SDr_Int 736U, // VFNMSUB231SSZm 736U, // VFNMSUB231SSZm_Int 395556U, // VFNMSUB231SSZm_Intk 395556U, // VFNMSUB231SSZm_Intkz 288U, // VFNMSUB231SSZr 288U, // VFNMSUB231SSZr_Int 166180U, // VFNMSUB231SSZr_Intk 166180U, // VFNMSUB231SSZr_Intkz 288U, // VFNMSUB231SSZrb 887072U, // VFNMSUB231SSZrb_Int 4360484U, // VFNMSUB231SSZrb_Intk 4360484U, // VFNMSUB231SSZrb_Intkz 736U, // VFNMSUB231SSm 736U, // VFNMSUB231SSm_Int 288U, // VFNMSUB231SSr 288U, // VFNMSUB231SSr_Int 854336U, // VFNMSUBPD4Ymr 264288U, // VFNMSUBPD4Yrm 198752U, // VFNMSUBPD4Yrr 198752U, // VFNMSUBPD4Yrr_REV 854368U, // VFNMSUBPD4mr 133216U, // VFNMSUBPD4rm 198752U, // VFNMSUBPD4rr 198752U, // VFNMSUBPD4rr_REV 854336U, // VFNMSUBPS4Ymr 264288U, // VFNMSUBPS4Yrm 198752U, // VFNMSUBPS4Yrr 198752U, // VFNMSUBPS4Yrr_REV 854368U, // VFNMSUBPS4mr 133216U, // VFNMSUBPS4rm 198752U, // VFNMSUBPS4rr 198752U, // VFNMSUBPS4rr_REV 854400U, // VFNMSUBSD4mr 854400U, // VFNMSUBSD4mr_Int 100448U, // VFNMSUBSD4rm 100448U, // VFNMSUBSD4rm_Int 198752U, // VFNMSUBSD4rr 198752U, // VFNMSUBSD4rr_Int 198752U, // VFNMSUBSD4rr_Int_REV 198752U, // VFNMSUBSD4rr_REV 854464U, // VFNMSUBSS4mr 854464U, // VFNMSUBSS4mr_Int 428128U, // VFNMSUBSS4rm 428128U, // VFNMSUBSS4rm_Int 198752U, // VFNMSUBSS4rr 198752U, // VFNMSUBSS4rr_Int 198752U, // VFNMSUBSS4rr_Int_REV 198752U, // VFNMSUBSS4rr_REV 0U, // VFPCLASSPDZ128rm 11U, // VFPCLASSPDZ128rmb 477572U, // VFPCLASSPDZ128rmbk 461156U, // VFPCLASSPDZ128rmk 32U, // VFPCLASSPDZ128rr 624740U, // VFPCLASSPDZ128rrk 0U, // VFPCLASSPDZ256rm 12U, // VFPCLASSPDZ256rmb 471428U, // VFPCLASSPDZ256rmbk 461124U, // VFPCLASSPDZ256rmk 32U, // VFPCLASSPDZ256rr 624740U, // VFPCLASSPDZ256rrk 0U, // VFPCLASSPDZrm 12U, // VFPCLASSPDZrmb 473476U, // VFPCLASSPDZrmbk 461220U, // VFPCLASSPDZrmk 32U, // VFPCLASSPDZrr 624740U, // VFPCLASSPDZrrk 0U, // VFPCLASSPSZ128rm 12U, // VFPCLASSPSZ128rmb 471492U, // VFPCLASSPSZ128rmbk 461156U, // VFPCLASSPSZ128rmk 32U, // VFPCLASSPSZ128rr 624740U, // VFPCLASSPSZ128rrk 0U, // VFPCLASSPSZ256rm 12U, // VFPCLASSPSZ256rmb 473540U, // VFPCLASSPSZ256rmbk 461124U, // VFPCLASSPSZ256rmk 32U, // VFPCLASSPSZ256rr 624740U, // VFPCLASSPSZ256rrk 0U, // VFPCLASSPSZrm 13U, // VFPCLASSPSZrmb 475588U, // VFPCLASSPSZrmbk 461220U, // VFPCLASSPSZrmk 32U, // VFPCLASSPSZrr 624740U, // VFPCLASSPSZrrk 0U, // VFPCLASSSDZrm 461188U, // VFPCLASSSDZrmk 32U, // VFPCLASSSDZrr 624740U, // VFPCLASSSDZrrk 0U, // VFPCLASSSSZrm 461252U, // VFPCLASSSSZrmk 32U, // VFPCLASSSSZrr 624740U, // VFPCLASSSSZrrk 0U, // VFRCZPDYrm 0U, // VFRCZPDYrr 0U, // VFRCZPDrm 0U, // VFRCZPDrr 0U, // VFRCZPSYrm 0U, // VFRCZPSYrr 0U, // VFRCZPSrm 0U, // VFRCZPSrr 0U, // VFRCZSDrm 0U, // VFRCZSDrr 0U, // VFRCZSSrm 0U, // VFRCZSSrr 0U, // VGATHERDPDYrm 13U, // VGATHERDPDZ128rm 14U, // VGATHERDPDZ256rm 14U, // VGATHERDPDZrm 0U, // VGATHERDPDrm 0U, // VGATHERDPSYrm 13U, // VGATHERDPSZ128rm 14U, // VGATHERDPSZ256rm 14U, // VGATHERDPSZrm 0U, // VGATHERDPSrm 0U, // VGATHERPF0DPDm 0U, // VGATHERPF0DPSm 0U, // VGATHERPF0QPDm 0U, // VGATHERPF0QPSm 0U, // VGATHERPF1DPDm 0U, // VGATHERPF1DPSm 0U, // VGATHERPF1QPDm 0U, // VGATHERPF1QPSm 0U, // VGATHERQPDYrm 13U, // VGATHERQPDZ128rm 14U, // VGATHERQPDZ256rm 14U, // VGATHERQPDZrm 0U, // VGATHERQPDrm 0U, // VGATHERQPSYrm 15U, // VGATHERQPSZ128rm 13U, // VGATHERQPSZ256rm 14U, // VGATHERQPSZrm 0U, // VGATHERQPSrm 0U, // VGETEXPPDZ128m 9U, // VGETEXPPDZ128mb 4676U, // VGETEXPPDZ128mbk 4484U, // VGETEXPPDZ128mbkz 260U, // VGETEXPPDZ128mk 356U, // VGETEXPPDZ128mkz 0U, // VGETEXPPDZ128r 292U, // VGETEXPPDZ128rk 100U, // VGETEXPPDZ128rkz 0U, // VGETEXPPDZ256m 9U, // VGETEXPPDZ256mb 6724U, // VGETEXPPDZ256mbk 6532U, // VGETEXPPDZ256mbkz 612U, // VGETEXPPDZ256mk 324U, // VGETEXPPDZ256mkz 0U, // VGETEXPPDZ256r 292U, // VGETEXPPDZ256rk 100U, // VGETEXPPDZ256rkz 0U, // VGETEXPPDZm 10U, // VGETEXPPDZmb 8772U, // VGETEXPPDZmbk 8580U, // VGETEXPPDZmbkz 1060U, // VGETEXPPDZmk 420U, // VGETEXPPDZmkz 0U, // VGETEXPPDZr 8U, // VGETEXPPDZrb 20772U, // VGETEXPPDZrbk 20580U, // VGETEXPPDZrbkz 292U, // VGETEXPPDZrk 100U, // VGETEXPPDZrkz 0U, // VGETEXPPSZ128m 9U, // VGETEXPPSZ128mb 6884U, // VGETEXPPSZ128mbk 6596U, // VGETEXPPSZ128mbkz 260U, // VGETEXPPSZ128mk 356U, // VGETEXPPSZ128mkz 0U, // VGETEXPPSZ128r 292U, // VGETEXPPSZ128rk 100U, // VGETEXPPSZ128rkz 0U, // VGETEXPPSZ256m 10U, // VGETEXPPSZ256mb 8932U, // VGETEXPPSZ256mbk 8644U, // VGETEXPPSZ256mbkz 612U, // VGETEXPPSZ256mk 324U, // VGETEXPPSZ256mkz 0U, // VGETEXPPSZ256r 292U, // VGETEXPPSZ256rk 100U, // VGETEXPPSZ256rkz 0U, // VGETEXPPSZm 10U, // VGETEXPPSZmb 10980U, // VGETEXPPSZmbk 10692U, // VGETEXPPSZmbkz 1060U, // VGETEXPPSZmk 420U, // VGETEXPPSZmkz 0U, // VGETEXPPSZr 8U, // VGETEXPPSZrb 20772U, // VGETEXPPSZrbk 20580U, // VGETEXPPSZrbkz 292U, // VGETEXPPSZrk 100U, // VGETEXPPSZrkz 384U, // VGETEXPSDZm 67876U, // VGETEXPSDZmk 100452U, // VGETEXPSDZmkz 96U, // VGETEXPSDZr 20576U, // VGETEXPSDZrb 11700516U, // VGETEXPSDZrbk 11733092U, // VGETEXPSDZrbkz 166180U, // VGETEXPSDZrk 198756U, // VGETEXPSDZrkz 448U, // VGETEXPSSZm 395556U, // VGETEXPSSZmk 428132U, // VGETEXPSSZmkz 96U, // VGETEXPSSZr 20576U, // VGETEXPSSZrb 11700516U, // VGETEXPSSZrbk 11733092U, // VGETEXPSSZrbkz 166180U, // VGETEXPSSZrk 198756U, // VGETEXPSSZrkz 11U, // VGETMANTPDZ128rmbi 936516U, // VGETMANTPDZ128rmbik 477572U, // VGETMANTPDZ128rmbikz 0U, // VGETMANTPDZ128rmi 919812U, // VGETMANTPDZ128rmik 461156U, // VGETMANTPDZ128rmikz 32U, // VGETMANTPDZ128rri 2340U, // VGETMANTPDZ128rrik 624740U, // VGETMANTPDZ128rrikz 12U, // VGETMANTPDZ256rmbi 930372U, // VGETMANTPDZ256rmbik 471428U, // VGETMANTPDZ256rmbikz 0U, // VGETMANTPDZ256rmi 920164U, // VGETMANTPDZ256rmik 461124U, // VGETMANTPDZ256rmikz 32U, // VGETMANTPDZ256rri 2340U, // VGETMANTPDZ256rrik 624740U, // VGETMANTPDZ256rrikz 12U, // VGETMANTPDZrmbi 932420U, // VGETMANTPDZrmbik 473476U, // VGETMANTPDZrmbikz 0U, // VGETMANTPDZrmi 920612U, // VGETMANTPDZrmik 461220U, // VGETMANTPDZrmikz 32U, // VGETMANTPDZrri 11U, // VGETMANTPDZrrib 22820U, // VGETMANTPDZrribk 645220U, // VGETMANTPDZrribkz 2340U, // VGETMANTPDZrrik 624740U, // VGETMANTPDZrrikz 12U, // VGETMANTPSZ128rmbi 930532U, // VGETMANTPSZ128rmbik 471492U, // VGETMANTPSZ128rmbikz 0U, // VGETMANTPSZ128rmi 919812U, // VGETMANTPSZ128rmik 461156U, // VGETMANTPSZ128rmikz 32U, // VGETMANTPSZ128rri 2340U, // VGETMANTPSZ128rrik 624740U, // VGETMANTPSZ128rrikz 12U, // VGETMANTPSZ256rmbi 932580U, // VGETMANTPSZ256rmbik 473540U, // VGETMANTPSZ256rmbikz 0U, // VGETMANTPSZ256rmi 920164U, // VGETMANTPSZ256rmik 461124U, // VGETMANTPSZ256rmikz 32U, // VGETMANTPSZ256rri 2340U, // VGETMANTPSZ256rrik 624740U, // VGETMANTPSZ256rrikz 13U, // VGETMANTPSZrmbi 934628U, // VGETMANTPSZrmbik 475588U, // VGETMANTPSZrmbikz 0U, // VGETMANTPSZrmi 920612U, // VGETMANTPSZrmik 461220U, // VGETMANTPSZrmikz 32U, // VGETMANTPSZrri 11U, // VGETMANTPSZrrib 22820U, // VGETMANTPSZrribk 645220U, // VGETMANTPSZrribkz 2340U, // VGETMANTPSZrrik 624740U, // VGETMANTPSZrrikz 461184U, // VGETMANTSDZrmi 37816612U, // VGETMANTSDZrmik 54626404U, // VGETMANTSDZrmikz 624736U, // VGETMANTSDZrri 645216U, // VGETMANTSDZrrib 77760804U, // VGETMANTSDZrribk 94570596U, // VGETMANTSDZrribkz 71469348U, // VGETMANTSDZrrik 88279140U, // VGETMANTSDZrrikz 461248U, // VGETMANTSSZrmi 38144292U, // VGETMANTSSZrmik 54954084U, // VGETMANTSSZrmikz 624736U, // VGETMANTSSZrri 645216U, // VGETMANTSSZrrib 77760804U, // VGETMANTSSZrribk 94570596U, // VGETMANTSSZrribkz 71469348U, // VGETMANTSSZrrik 88279140U, // VGETMANTSSZrrikz 461280U, // VGF2P8AFFINEINVQBYrmi 624736U, // VGF2P8AFFINEINVQBYrri 478304U, // VGF2P8AFFINEINVQBZ128rmbi 43944228U, // VGF2P8AFFINEINVQBZ128rmbik 60754020U, // VGF2P8AFFINEINVQBZ128rmbikz 461312U, // VGF2P8AFFINEINVQBZ128rmi 38308132U, // VGF2P8AFFINEINVQBZ128rmik 55117924U, // VGF2P8AFFINEINVQBZ128rmikz 624736U, // VGF2P8AFFINEINVQBZ128rri 71469348U, // VGF2P8AFFINEINVQBZ128rrik 88279140U, // VGF2P8AFFINEINVQBZ128rrikz 472160U, // VGF2P8AFFINEINVQBZ256rmbi 40798500U, // VGF2P8AFFINEINVQBZ256rmbik 57608292U, // VGF2P8AFFINEINVQBZ256rmbikz 461280U, // VGF2P8AFFINEINVQBZ256rmi 38406436U, // VGF2P8AFFINEINVQBZ256rmik 55216228U, // VGF2P8AFFINEINVQBZ256rmikz 624736U, // VGF2P8AFFINEINVQBZ256rri 71469348U, // VGF2P8AFFINEINVQBZ256rrik 88279140U, // VGF2P8AFFINEINVQBZ256rrikz 474208U, // VGF2P8AFFINEINVQBZrmbi 41847076U, // VGF2P8AFFINEINVQBZrmbik 58656868U, // VGF2P8AFFINEINVQBZrmbikz 461344U, // VGF2P8AFFINEINVQBZrmi 38471972U, // VGF2P8AFFINEINVQBZrmik 55281764U, // VGF2P8AFFINEINVQBZrmikz 624736U, // VGF2P8AFFINEINVQBZrri 71469348U, // VGF2P8AFFINEINVQBZrrik 88279140U, // VGF2P8AFFINEINVQBZrrikz 461312U, // VGF2P8AFFINEINVQBrmi 624736U, // VGF2P8AFFINEINVQBrri 461280U, // VGF2P8AFFINEQBYrmi 624736U, // VGF2P8AFFINEQBYrri 478304U, // VGF2P8AFFINEQBZ128rmbi 43944228U, // VGF2P8AFFINEQBZ128rmbik 60754020U, // VGF2P8AFFINEQBZ128rmbikz 461312U, // VGF2P8AFFINEQBZ128rmi 38308132U, // VGF2P8AFFINEQBZ128rmik 55117924U, // VGF2P8AFFINEQBZ128rmikz 624736U, // VGF2P8AFFINEQBZ128rri 71469348U, // VGF2P8AFFINEQBZ128rrik 88279140U, // VGF2P8AFFINEQBZ128rrikz 472160U, // VGF2P8AFFINEQBZ256rmbi 40798500U, // VGF2P8AFFINEQBZ256rmbik 57608292U, // VGF2P8AFFINEQBZ256rmbikz 461280U, // VGF2P8AFFINEQBZ256rmi 38406436U, // VGF2P8AFFINEQBZ256rmik 55216228U, // VGF2P8AFFINEQBZ256rmikz 624736U, // VGF2P8AFFINEQBZ256rri 71469348U, // VGF2P8AFFINEQBZ256rrik 88279140U, // VGF2P8AFFINEQBZ256rrikz 474208U, // VGF2P8AFFINEQBZrmbi 41847076U, // VGF2P8AFFINEQBZrmbik 58656868U, // VGF2P8AFFINEQBZrmbikz 461344U, // VGF2P8AFFINEQBZrmi 38471972U, // VGF2P8AFFINEQBZrmik 55281764U, // VGF2P8AFFINEQBZrmikz 624736U, // VGF2P8AFFINEQBZrri 71469348U, // VGF2P8AFFINEQBZrrik 88279140U, // VGF2P8AFFINEQBZrrikz 461312U, // VGF2P8AFFINEQBrmi 624736U, // VGF2P8AFFINEQBrri 480U, // VGF2P8MULBYrm 96U, // VGF2P8MULBYrr 512U, // VGF2P8MULBZ128rm 559396U, // VGF2P8MULBZ128rmk 591972U, // VGF2P8MULBZ128rmkz 96U, // VGF2P8MULBZ128rr 166180U, // VGF2P8MULBZ128rrk 198756U, // VGF2P8MULBZ128rrkz 480U, // VGF2P8MULBZ256rm 657700U, // VGF2P8MULBZ256rmk 690276U, // VGF2P8MULBZ256rmkz 96U, // VGF2P8MULBZ256rr 166180U, // VGF2P8MULBZ256rrk 198756U, // VGF2P8MULBZ256rrkz 544U, // VGF2P8MULBZrm 723236U, // VGF2P8MULBZrmk 755812U, // VGF2P8MULBZrmkz 96U, // VGF2P8MULBZrr 166180U, // VGF2P8MULBZrrk 198756U, // VGF2P8MULBZrrkz 512U, // VGF2P8MULBrm 96U, // VGF2P8MULBrr 320U, // VHADDPDYrm 96U, // VHADDPDYrr 352U, // VHADDPDrm 96U, // VHADDPDrr 320U, // VHADDPSYrm 96U, // VHADDPSYrr 352U, // VHADDPSrm 96U, // VHADDPSrr 320U, // VHSUBPDYrm 96U, // VHSUBPDYrr 352U, // VHSUBPDrm 96U, // VHSUBPDrr 320U, // VHSUBPSYrm 96U, // VHSUBPSYrr 352U, // VHSUBPSrm 96U, // VHSUBPSrr 461152U, // VINSERTF128rm 624736U, // VINSERTF128rr 461152U, // VINSERTF32x4Z256rm 37783844U, // VINSERTF32x4Z256rmk 54659172U, // VINSERTF32x4Z256rmkz 624736U, // VINSERTF32x4Z256rr 71469348U, // VINSERTF32x4Z256rrk 88279140U, // VINSERTF32x4Z256rrkz 461152U, // VINSERTF32x4Zrm 37783844U, // VINSERTF32x4Zrmk 54659172U, // VINSERTF32x4Zrmkz 624736U, // VINSERTF32x4Zrr 71469348U, // VINSERTF32x4Zrrk 88279140U, // VINSERTF32x4Zrrkz 461120U, // VINSERTF32x8Zrm 37980452U, // VINSERTF32x8Zrmk 54790244U, // VINSERTF32x8Zrmkz 624736U, // VINSERTF32x8Zrr 71469348U, // VINSERTF32x8Zrrk 88279140U, // VINSERTF32x8Zrrkz 461152U, // VINSERTF64x2Z256rm 37783844U, // VINSERTF64x2Z256rmk 54659172U, // VINSERTF64x2Z256rmkz 624736U, // VINSERTF64x2Z256rr 71469348U, // VINSERTF64x2Z256rrk 88279140U, // VINSERTF64x2Z256rrkz 461152U, // VINSERTF64x2Zrm 37783844U, // VINSERTF64x2Zrmk 54659172U, // VINSERTF64x2Zrmkz 624736U, // VINSERTF64x2Zrr 71469348U, // VINSERTF64x2Zrrk 88279140U, // VINSERTF64x2Zrrkz 461120U, // VINSERTF64x4Zrm 37980452U, // VINSERTF64x4Zrmk 54790244U, // VINSERTF64x4Zrmkz 624736U, // VINSERTF64x4Zrr 71469348U, // VINSERTF64x4Zrrk 88279140U, // VINSERTF64x4Zrrkz 461312U, // VINSERTI128rm 624736U, // VINSERTI128rr 461312U, // VINSERTI32x4Z256rm 38308132U, // VINSERTI32x4Z256rmk 55117924U, // VINSERTI32x4Z256rmkz 624736U, // VINSERTI32x4Z256rr 71469348U, // VINSERTI32x4Z256rrk 88279140U, // VINSERTI32x4Z256rrkz 461312U, // VINSERTI32x4Zrm 38308132U, // VINSERTI32x4Zrmk 55117924U, // VINSERTI32x4Zrmkz 624736U, // VINSERTI32x4Zrr 71469348U, // VINSERTI32x4Zrrk 88279140U, // VINSERTI32x4Zrrkz 461280U, // VINSERTI32x8Zrm 38406436U, // VINSERTI32x8Zrmk 55216228U, // VINSERTI32x8Zrmkz 624736U, // VINSERTI32x8Zrr 71469348U, // VINSERTI32x8Zrrk 88279140U, // VINSERTI32x8Zrrkz 461312U, // VINSERTI64x2Z256rm 38308132U, // VINSERTI64x2Z256rmk 55117924U, // VINSERTI64x2Z256rmkz 624736U, // VINSERTI64x2Z256rr 71469348U, // VINSERTI64x2Z256rrk 88279140U, // VINSERTI64x2Z256rrkz 461312U, // VINSERTI64x2Zrm 38308132U, // VINSERTI64x2Zrmk 55117924U, // VINSERTI64x2Zrmkz 624736U, // VINSERTI64x2Zrr 71469348U, // VINSERTI64x2Zrrk 88279140U, // VINSERTI64x2Zrrkz 461280U, // VINSERTI64x4Zrm 38406436U, // VINSERTI64x4Zrmk 55216228U, // VINSERTI64x4Zrmkz 624736U, // VINSERTI64x4Zrr 71469348U, // VINSERTI64x4Zrrk 88279140U, // VINSERTI64x4Zrrkz 461248U, // VINSERTPSZrm 624736U, // VINSERTPSZrr 461248U, // VINSERTPSrm 624736U, // VINSERTPSrr 0U, // VLDDQUYrm 0U, // VLDDQUrm 0U, // VLDMXCSR 0U, // VMASKMOVDQU 0U, // VMASKMOVDQU64 160U, // VMASKMOVPDYmr 320U, // VMASKMOVPDYrm 160U, // VMASKMOVPDmr 352U, // VMASKMOVPDrm 160U, // VMASKMOVPSYmr 320U, // VMASKMOVPSYrm 160U, // VMASKMOVPSmr 352U, // VMASKMOVPSrm 320U, // VMAXCPDYrm 96U, // VMAXCPDYrr 352U, // VMAXCPDZ128rm 4480U, // VMAXCPDZ128rmb 1116452U, // VMAXCPDZ128rmbk 1149028U, // VMAXCPDZ128rmbkz 35108U, // VMAXCPDZ128rmk 133220U, // VMAXCPDZ128rmkz 96U, // VMAXCPDZ128rr 166180U, // VMAXCPDZ128rrk 198756U, // VMAXCPDZ128rrkz 320U, // VMAXCPDZ256rm 6528U, // VMAXCPDZ256rmb 2165028U, // VMAXCPDZ256rmbk 2197604U, // VMAXCPDZ256rmbkz 231716U, // VMAXCPDZ256rmk 264292U, // VMAXCPDZ256rmkz 96U, // VMAXCPDZ256rr 166180U, // VMAXCPDZ256rrk 198756U, // VMAXCPDZ256rrkz 416U, // VMAXCPDZrm 8576U, // VMAXCPDZrmb 3213604U, // VMAXCPDZrmbk 3246180U, // VMAXCPDZrmbkz 297252U, // VMAXCPDZrmk 329828U, // VMAXCPDZrmkz 96U, // VMAXCPDZrr 166180U, // VMAXCPDZrrk 198756U, // VMAXCPDZrrkz 352U, // VMAXCPDrm 96U, // VMAXCPDrr 320U, // VMAXCPSYrm 96U, // VMAXCPSYrr 352U, // VMAXCPSZ128rm 6592U, // VMAXCPSZ128rmb 2492708U, // VMAXCPSZ128rmbk 2525284U, // VMAXCPSZ128rmbkz 35108U, // VMAXCPSZ128rmk 133220U, // VMAXCPSZ128rmkz 96U, // VMAXCPSZ128rr 166180U, // VMAXCPSZ128rrk 198756U, // VMAXCPSZ128rrkz 320U, // VMAXCPSZ256rm 8640U, // VMAXCPSZ256rmb 3541284U, // VMAXCPSZ256rmbk 3573860U, // VMAXCPSZ256rmbkz 231716U, // VMAXCPSZ256rmk 264292U, // VMAXCPSZ256rmkz 96U, // VMAXCPSZ256rr 166180U, // VMAXCPSZ256rrk 198756U, // VMAXCPSZ256rrkz 416U, // VMAXCPSZrm 10688U, // VMAXCPSZrmb 5638436U, // VMAXCPSZrmbk 5671012U, // VMAXCPSZrmbkz 297252U, // VMAXCPSZrmk 329828U, // VMAXCPSZrmkz 96U, // VMAXCPSZrr 166180U, // VMAXCPSZrrk 198756U, // VMAXCPSZrrkz 352U, // VMAXCPSrm 96U, // VMAXCPSrr 384U, // VMAXCSDZrm 96U, // VMAXCSDZrr 384U, // VMAXCSDrm 96U, // VMAXCSDrr 448U, // VMAXCSSZrm 96U, // VMAXCSSZrr 448U, // VMAXCSSrm 96U, // VMAXCSSrr 320U, // VMAXPDYrm 96U, // VMAXPDYrr 352U, // VMAXPDZ128rm 4480U, // VMAXPDZ128rmb 1116452U, // VMAXPDZ128rmbk 1149028U, // VMAXPDZ128rmbkz 35108U, // VMAXPDZ128rmk 133220U, // VMAXPDZ128rmkz 96U, // VMAXPDZ128rr 166180U, // VMAXPDZ128rrk 198756U, // VMAXPDZ128rrkz 320U, // VMAXPDZ256rm 6528U, // VMAXPDZ256rmb 2165028U, // VMAXPDZ256rmbk 2197604U, // VMAXPDZ256rmbkz 231716U, // VMAXPDZ256rmk 264292U, // VMAXPDZ256rmkz 96U, // VMAXPDZ256rr 166180U, // VMAXPDZ256rrk 198756U, // VMAXPDZ256rrkz 416U, // VMAXPDZrm 8576U, // VMAXPDZrmb 3213604U, // VMAXPDZrmbk 3246180U, // VMAXPDZrmbkz 297252U, // VMAXPDZrmk 329828U, // VMAXPDZrmkz 96U, // VMAXPDZrr 20576U, // VMAXPDZrrb 11700516U, // VMAXPDZrrbk 11733092U, // VMAXPDZrrbkz 166180U, // VMAXPDZrrk 198756U, // VMAXPDZrrkz 352U, // VMAXPDrm 96U, // VMAXPDrr 320U, // VMAXPSYrm 96U, // VMAXPSYrr 352U, // VMAXPSZ128rm 6592U, // VMAXPSZ128rmb 2492708U, // VMAXPSZ128rmbk 2525284U, // VMAXPSZ128rmbkz 35108U, // VMAXPSZ128rmk 133220U, // VMAXPSZ128rmkz 96U, // VMAXPSZ128rr 166180U, // VMAXPSZ128rrk 198756U, // VMAXPSZ128rrkz 320U, // VMAXPSZ256rm 8640U, // VMAXPSZ256rmb 3541284U, // VMAXPSZ256rmbk 3573860U, // VMAXPSZ256rmbkz 231716U, // VMAXPSZ256rmk 264292U, // VMAXPSZ256rmkz 96U, // VMAXPSZ256rr 166180U, // VMAXPSZ256rrk 198756U, // VMAXPSZ256rrkz 416U, // VMAXPSZrm 10688U, // VMAXPSZrmb 5638436U, // VMAXPSZrmbk 5671012U, // VMAXPSZrmbkz 297252U, // VMAXPSZrmk 329828U, // VMAXPSZrmkz 96U, // VMAXPSZrr 20576U, // VMAXPSZrrb 11700516U, // VMAXPSZrrbk 11733092U, // VMAXPSZrrbkz 166180U, // VMAXPSZrrk 198756U, // VMAXPSZrrkz 352U, // VMAXPSrm 96U, // VMAXPSrr 384U, // VMAXSDZrm 384U, // VMAXSDZrm_Int 67876U, // VMAXSDZrm_Intk 100452U, // VMAXSDZrm_Intkz 96U, // VMAXSDZrr 96U, // VMAXSDZrr_Int 166180U, // VMAXSDZrr_Intk 198756U, // VMAXSDZrr_Intkz 20576U, // VMAXSDZrrb_Int 11700516U, // VMAXSDZrrb_Intk 11733092U, // VMAXSDZrrb_Intkz 384U, // VMAXSDrm 384U, // VMAXSDrm_Int 96U, // VMAXSDrr 96U, // VMAXSDrr_Int 448U, // VMAXSSZrm 448U, // VMAXSSZrm_Int 395556U, // VMAXSSZrm_Intk 428132U, // VMAXSSZrm_Intkz 96U, // VMAXSSZrr 96U, // VMAXSSZrr_Int 166180U, // VMAXSSZrr_Intk 198756U, // VMAXSSZrr_Intkz 20576U, // VMAXSSZrrb_Int 11700516U, // VMAXSSZrrb_Intk 11733092U, // VMAXSSZrrb_Intkz 448U, // VMAXSSrm 448U, // VMAXSSrm_Int 96U, // VMAXSSrr 96U, // VMAXSSrr_Int 0U, // VMCALL 0U, // VMCLEARm 0U, // VMFUNC 320U, // VMINCPDYrm 96U, // VMINCPDYrr 352U, // VMINCPDZ128rm 4480U, // VMINCPDZ128rmb 1116452U, // VMINCPDZ128rmbk 1149028U, // VMINCPDZ128rmbkz 35108U, // VMINCPDZ128rmk 133220U, // VMINCPDZ128rmkz 96U, // VMINCPDZ128rr 166180U, // VMINCPDZ128rrk 198756U, // VMINCPDZ128rrkz 320U, // VMINCPDZ256rm 6528U, // VMINCPDZ256rmb 2165028U, // VMINCPDZ256rmbk 2197604U, // VMINCPDZ256rmbkz 231716U, // VMINCPDZ256rmk 264292U, // VMINCPDZ256rmkz 96U, // VMINCPDZ256rr 166180U, // VMINCPDZ256rrk 198756U, // VMINCPDZ256rrkz 416U, // VMINCPDZrm 8576U, // VMINCPDZrmb 3213604U, // VMINCPDZrmbk 3246180U, // VMINCPDZrmbkz 297252U, // VMINCPDZrmk 329828U, // VMINCPDZrmkz 96U, // VMINCPDZrr 166180U, // VMINCPDZrrk 198756U, // VMINCPDZrrkz 352U, // VMINCPDrm 96U, // VMINCPDrr 320U, // VMINCPSYrm 96U, // VMINCPSYrr 352U, // VMINCPSZ128rm 6592U, // VMINCPSZ128rmb 2492708U, // VMINCPSZ128rmbk 2525284U, // VMINCPSZ128rmbkz 35108U, // VMINCPSZ128rmk 133220U, // VMINCPSZ128rmkz 96U, // VMINCPSZ128rr 166180U, // VMINCPSZ128rrk 198756U, // VMINCPSZ128rrkz 320U, // VMINCPSZ256rm 8640U, // VMINCPSZ256rmb 3541284U, // VMINCPSZ256rmbk 3573860U, // VMINCPSZ256rmbkz 231716U, // VMINCPSZ256rmk 264292U, // VMINCPSZ256rmkz 96U, // VMINCPSZ256rr 166180U, // VMINCPSZ256rrk 198756U, // VMINCPSZ256rrkz 416U, // VMINCPSZrm 10688U, // VMINCPSZrmb 5638436U, // VMINCPSZrmbk 5671012U, // VMINCPSZrmbkz 297252U, // VMINCPSZrmk 329828U, // VMINCPSZrmkz 96U, // VMINCPSZrr 166180U, // VMINCPSZrrk 198756U, // VMINCPSZrrkz 352U, // VMINCPSrm 96U, // VMINCPSrr 384U, // VMINCSDZrm 96U, // VMINCSDZrr 384U, // VMINCSDrm 96U, // VMINCSDrr 448U, // VMINCSSZrm 96U, // VMINCSSZrr 448U, // VMINCSSrm 96U, // VMINCSSrr 320U, // VMINPDYrm 96U, // VMINPDYrr 352U, // VMINPDZ128rm 4480U, // VMINPDZ128rmb 1116452U, // VMINPDZ128rmbk 1149028U, // VMINPDZ128rmbkz 35108U, // VMINPDZ128rmk 133220U, // VMINPDZ128rmkz 96U, // VMINPDZ128rr 166180U, // VMINPDZ128rrk 198756U, // VMINPDZ128rrkz 320U, // VMINPDZ256rm 6528U, // VMINPDZ256rmb 2165028U, // VMINPDZ256rmbk 2197604U, // VMINPDZ256rmbkz 231716U, // VMINPDZ256rmk 264292U, // VMINPDZ256rmkz 96U, // VMINPDZ256rr 166180U, // VMINPDZ256rrk 198756U, // VMINPDZ256rrkz 416U, // VMINPDZrm 8576U, // VMINPDZrmb 3213604U, // VMINPDZrmbk 3246180U, // VMINPDZrmbkz 297252U, // VMINPDZrmk 329828U, // VMINPDZrmkz 96U, // VMINPDZrr 20576U, // VMINPDZrrb 11700516U, // VMINPDZrrbk 11733092U, // VMINPDZrrbkz 166180U, // VMINPDZrrk 198756U, // VMINPDZrrkz 352U, // VMINPDrm 96U, // VMINPDrr 320U, // VMINPSYrm 96U, // VMINPSYrr 352U, // VMINPSZ128rm 6592U, // VMINPSZ128rmb 2492708U, // VMINPSZ128rmbk 2525284U, // VMINPSZ128rmbkz 35108U, // VMINPSZ128rmk 133220U, // VMINPSZ128rmkz 96U, // VMINPSZ128rr 166180U, // VMINPSZ128rrk 198756U, // VMINPSZ128rrkz 320U, // VMINPSZ256rm 8640U, // VMINPSZ256rmb 3541284U, // VMINPSZ256rmbk 3573860U, // VMINPSZ256rmbkz 231716U, // VMINPSZ256rmk 264292U, // VMINPSZ256rmkz 96U, // VMINPSZ256rr 166180U, // VMINPSZ256rrk 198756U, // VMINPSZ256rrkz 416U, // VMINPSZrm 10688U, // VMINPSZrmb 5638436U, // VMINPSZrmbk 5671012U, // VMINPSZrmbkz 297252U, // VMINPSZrmk 329828U, // VMINPSZrmkz 96U, // VMINPSZrr 20576U, // VMINPSZrrb 11700516U, // VMINPSZrrbk 11733092U, // VMINPSZrrbkz 166180U, // VMINPSZrrk 198756U, // VMINPSZrrkz 352U, // VMINPSrm 96U, // VMINPSrr 384U, // VMINSDZrm 384U, // VMINSDZrm_Int 67876U, // VMINSDZrm_Intk 100452U, // VMINSDZrm_Intkz 96U, // VMINSDZrr 96U, // VMINSDZrr_Int 166180U, // VMINSDZrr_Intk 198756U, // VMINSDZrr_Intkz 20576U, // VMINSDZrrb_Int 11700516U, // VMINSDZrrb_Intk 11733092U, // VMINSDZrrb_Intkz 384U, // VMINSDrm 384U, // VMINSDrm_Int 96U, // VMINSDrr 96U, // VMINSDrr_Int 448U, // VMINSSZrm 448U, // VMINSSZrm_Int 395556U, // VMINSSZrm_Intk 428132U, // VMINSSZrm_Intkz 96U, // VMINSSZrr 96U, // VMINSSZrr_Int 166180U, // VMINSSZrr_Intk 198756U, // VMINSSZrr_Intkz 20576U, // VMINSSZrrb_Int 11700516U, // VMINSSZrrb_Intk 11733092U, // VMINSSZrrb_Intkz 448U, // VMINSSrm 448U, // VMINSSrm_Int 96U, // VMINSSrr 96U, // VMINSSrr_Int 0U, // VMLAUNCH 0U, // VMLOAD32 0U, // VMLOAD64 0U, // VMMCALL 0U, // VMOV64toPQIZrm 0U, // VMOV64toPQIZrr 0U, // VMOV64toPQIrm 0U, // VMOV64toPQIrr 0U, // VMOV64toSDZrm 0U, // VMOV64toSDZrr 0U, // VMOV64toSDrm 0U, // VMOV64toSDrr 0U, // VMOVAPDYmr 0U, // VMOVAPDYrm 0U, // VMOVAPDYrr 0U, // VMOVAPDYrr_REV 0U, // VMOVAPDZ128mr 164U, // VMOVAPDZ128mrk 0U, // VMOVAPDZ128rm 260U, // VMOVAPDZ128rmk 356U, // VMOVAPDZ128rmkz 0U, // VMOVAPDZ128rr 0U, // VMOVAPDZ128rr_REV 292U, // VMOVAPDZ128rrk 100U, // VMOVAPDZ128rrk_REV 100U, // VMOVAPDZ128rrkz 100U, // VMOVAPDZ128rrkz_REV 0U, // VMOVAPDZ256mr 164U, // VMOVAPDZ256mrk 0U, // VMOVAPDZ256rm 612U, // VMOVAPDZ256rmk 324U, // VMOVAPDZ256rmkz 0U, // VMOVAPDZ256rr 0U, // VMOVAPDZ256rr_REV 292U, // VMOVAPDZ256rrk 100U, // VMOVAPDZ256rrk_REV 100U, // VMOVAPDZ256rrkz 100U, // VMOVAPDZ256rrkz_REV 0U, // VMOVAPDZmr 164U, // VMOVAPDZmrk 0U, // VMOVAPDZrm 1060U, // VMOVAPDZrmk 420U, // VMOVAPDZrmkz 0U, // VMOVAPDZrr 0U, // VMOVAPDZrr_REV 292U, // VMOVAPDZrrk 100U, // VMOVAPDZrrk_REV 100U, // VMOVAPDZrrkz 100U, // VMOVAPDZrrkz_REV 0U, // VMOVAPDmr 0U, // VMOVAPDrm 0U, // VMOVAPDrr 0U, // VMOVAPDrr_REV 0U, // VMOVAPSYmr 0U, // VMOVAPSYrm 0U, // VMOVAPSYrr 0U, // VMOVAPSYrr_REV 0U, // VMOVAPSZ128mr 164U, // VMOVAPSZ128mrk 0U, // VMOVAPSZ128rm 260U, // VMOVAPSZ128rmk 356U, // VMOVAPSZ128rmkz 0U, // VMOVAPSZ128rr 0U, // VMOVAPSZ128rr_REV 292U, // VMOVAPSZ128rrk 100U, // VMOVAPSZ128rrk_REV 100U, // VMOVAPSZ128rrkz 100U, // VMOVAPSZ128rrkz_REV 0U, // VMOVAPSZ256mr 164U, // VMOVAPSZ256mrk 0U, // VMOVAPSZ256rm 612U, // VMOVAPSZ256rmk 324U, // VMOVAPSZ256rmkz 0U, // VMOVAPSZ256rr 0U, // VMOVAPSZ256rr_REV 292U, // VMOVAPSZ256rrk 100U, // VMOVAPSZ256rrk_REV 100U, // VMOVAPSZ256rrkz 100U, // VMOVAPSZ256rrkz_REV 0U, // VMOVAPSZmr 164U, // VMOVAPSZmrk 0U, // VMOVAPSZrm 1060U, // VMOVAPSZrmk 420U, // VMOVAPSZrmkz 0U, // VMOVAPSZrr 0U, // VMOVAPSZrr_REV 292U, // VMOVAPSZrrk 100U, // VMOVAPSZrrk_REV 100U, // VMOVAPSZrrkz 100U, // VMOVAPSZrrkz_REV 0U, // VMOVAPSmr 0U, // VMOVAPSrm 0U, // VMOVAPSrr 0U, // VMOVAPSrr_REV 0U, // VMOVDDUPYrm 0U, // VMOVDDUPYrr 0U, // VMOVDDUPZ128rm 580U, // VMOVDDUPZ128rmk 388U, // VMOVDDUPZ128rmkz 0U, // VMOVDDUPZ128rr 292U, // VMOVDDUPZ128rrk 100U, // VMOVDDUPZ128rrkz 0U, // VMOVDDUPZ256rm 612U, // VMOVDDUPZ256rmk 324U, // VMOVDDUPZ256rmkz 0U, // VMOVDDUPZ256rr 292U, // VMOVDDUPZ256rrk 100U, // VMOVDDUPZ256rrkz 0U, // VMOVDDUPZrm 1060U, // VMOVDDUPZrmk 420U, // VMOVDDUPZrmkz 0U, // VMOVDDUPZrr 292U, // VMOVDDUPZrrk 100U, // VMOVDDUPZrrkz 0U, // VMOVDDUPrm 0U, // VMOVDDUPrr 0U, // VMOVDI2PDIZrm 0U, // VMOVDI2PDIZrr 0U, // VMOVDI2PDIrm 0U, // VMOVDI2PDIrr 0U, // VMOVDI2SSZrm 0U, // VMOVDI2SSZrr 0U, // VMOVDI2SSrm 0U, // VMOVDI2SSrr 0U, // VMOVDQA32Z128mr 164U, // VMOVDQA32Z128mrk 0U, // VMOVDQA32Z128rm 676U, // VMOVDQA32Z128rmk 516U, // VMOVDQA32Z128rmkz 0U, // VMOVDQA32Z128rr 0U, // VMOVDQA32Z128rr_REV 292U, // VMOVDQA32Z128rrk 100U, // VMOVDQA32Z128rrk_REV 100U, // VMOVDQA32Z128rrkz 100U, // VMOVDQA32Z128rrkz_REV 0U, // VMOVDQA32Z256mr 164U, // VMOVDQA32Z256mrk 0U, // VMOVDQA32Z256rm 708U, // VMOVDQA32Z256rmk 484U, // VMOVDQA32Z256rmkz 0U, // VMOVDQA32Z256rr 0U, // VMOVDQA32Z256rr_REV 292U, // VMOVDQA32Z256rrk 100U, // VMOVDQA32Z256rrk_REV 100U, // VMOVDQA32Z256rrkz 100U, // VMOVDQA32Z256rrkz_REV 0U, // VMOVDQA32Zmr 164U, // VMOVDQA32Zmrk 0U, // VMOVDQA32Zrm 996U, // VMOVDQA32Zrmk 548U, // VMOVDQA32Zrmkz 0U, // VMOVDQA32Zrr 0U, // VMOVDQA32Zrr_REV 292U, // VMOVDQA32Zrrk 100U, // VMOVDQA32Zrrk_REV 100U, // VMOVDQA32Zrrkz 100U, // VMOVDQA32Zrrkz_REV 0U, // VMOVDQA64Z128mr 164U, // VMOVDQA64Z128mrk 0U, // VMOVDQA64Z128rm 676U, // VMOVDQA64Z128rmk 516U, // VMOVDQA64Z128rmkz 0U, // VMOVDQA64Z128rr 0U, // VMOVDQA64Z128rr_REV 292U, // VMOVDQA64Z128rrk 100U, // VMOVDQA64Z128rrk_REV 100U, // VMOVDQA64Z128rrkz 100U, // VMOVDQA64Z128rrkz_REV 0U, // VMOVDQA64Z256mr 164U, // VMOVDQA64Z256mrk 0U, // VMOVDQA64Z256rm 708U, // VMOVDQA64Z256rmk 484U, // VMOVDQA64Z256rmkz 0U, // VMOVDQA64Z256rr 0U, // VMOVDQA64Z256rr_REV 292U, // VMOVDQA64Z256rrk 100U, // VMOVDQA64Z256rrk_REV 100U, // VMOVDQA64Z256rrkz 100U, // VMOVDQA64Z256rrkz_REV 0U, // VMOVDQA64Zmr 164U, // VMOVDQA64Zmrk 0U, // VMOVDQA64Zrm 996U, // VMOVDQA64Zrmk 548U, // VMOVDQA64Zrmkz 0U, // VMOVDQA64Zrr 0U, // VMOVDQA64Zrr_REV 292U, // VMOVDQA64Zrrk 100U, // VMOVDQA64Zrrk_REV 100U, // VMOVDQA64Zrrkz 100U, // VMOVDQA64Zrrkz_REV 0U, // VMOVDQAYmr 0U, // VMOVDQAYrm 0U, // VMOVDQAYrr 0U, // VMOVDQAYrr_REV 0U, // VMOVDQAmr 0U, // VMOVDQArm 0U, // VMOVDQArr 0U, // VMOVDQArr_REV 0U, // VMOVDQU16Z128mr 164U, // VMOVDQU16Z128mrk 0U, // VMOVDQU16Z128rm 676U, // VMOVDQU16Z128rmk 516U, // VMOVDQU16Z128rmkz 0U, // VMOVDQU16Z128rr 0U, // VMOVDQU16Z128rr_REV 292U, // VMOVDQU16Z128rrk 100U, // VMOVDQU16Z128rrk_REV 100U, // VMOVDQU16Z128rrkz 100U, // VMOVDQU16Z128rrkz_REV 0U, // VMOVDQU16Z256mr 164U, // VMOVDQU16Z256mrk 0U, // VMOVDQU16Z256rm 708U, // VMOVDQU16Z256rmk 484U, // VMOVDQU16Z256rmkz 0U, // VMOVDQU16Z256rr 0U, // VMOVDQU16Z256rr_REV 292U, // VMOVDQU16Z256rrk 100U, // VMOVDQU16Z256rrk_REV 100U, // VMOVDQU16Z256rrkz 100U, // VMOVDQU16Z256rrkz_REV 0U, // VMOVDQU16Zmr 164U, // VMOVDQU16Zmrk 0U, // VMOVDQU16Zrm 996U, // VMOVDQU16Zrmk 548U, // VMOVDQU16Zrmkz 0U, // VMOVDQU16Zrr 0U, // VMOVDQU16Zrr_REV 292U, // VMOVDQU16Zrrk 100U, // VMOVDQU16Zrrk_REV 100U, // VMOVDQU16Zrrkz 100U, // VMOVDQU16Zrrkz_REV 0U, // VMOVDQU32Z128mr 164U, // VMOVDQU32Z128mrk 0U, // VMOVDQU32Z128rm 676U, // VMOVDQU32Z128rmk 516U, // VMOVDQU32Z128rmkz 0U, // VMOVDQU32Z128rr 0U, // VMOVDQU32Z128rr_REV 292U, // VMOVDQU32Z128rrk 100U, // VMOVDQU32Z128rrk_REV 100U, // VMOVDQU32Z128rrkz 100U, // VMOVDQU32Z128rrkz_REV 0U, // VMOVDQU32Z256mr 164U, // VMOVDQU32Z256mrk 0U, // VMOVDQU32Z256rm 708U, // VMOVDQU32Z256rmk 484U, // VMOVDQU32Z256rmkz 0U, // VMOVDQU32Z256rr 0U, // VMOVDQU32Z256rr_REV 292U, // VMOVDQU32Z256rrk 100U, // VMOVDQU32Z256rrk_REV 100U, // VMOVDQU32Z256rrkz 100U, // VMOVDQU32Z256rrkz_REV 0U, // VMOVDQU32Zmr 164U, // VMOVDQU32Zmrk 0U, // VMOVDQU32Zrm 996U, // VMOVDQU32Zrmk 548U, // VMOVDQU32Zrmkz 0U, // VMOVDQU32Zrr 0U, // VMOVDQU32Zrr_REV 292U, // VMOVDQU32Zrrk 100U, // VMOVDQU32Zrrk_REV 100U, // VMOVDQU32Zrrkz 100U, // VMOVDQU32Zrrkz_REV 0U, // VMOVDQU64Z128mr 164U, // VMOVDQU64Z128mrk 0U, // VMOVDQU64Z128rm 676U, // VMOVDQU64Z128rmk 516U, // VMOVDQU64Z128rmkz 0U, // VMOVDQU64Z128rr 0U, // VMOVDQU64Z128rr_REV 292U, // VMOVDQU64Z128rrk 100U, // VMOVDQU64Z128rrk_REV 100U, // VMOVDQU64Z128rrkz 100U, // VMOVDQU64Z128rrkz_REV 0U, // VMOVDQU64Z256mr 164U, // VMOVDQU64Z256mrk 0U, // VMOVDQU64Z256rm 708U, // VMOVDQU64Z256rmk 484U, // VMOVDQU64Z256rmkz 0U, // VMOVDQU64Z256rr 0U, // VMOVDQU64Z256rr_REV 292U, // VMOVDQU64Z256rrk 100U, // VMOVDQU64Z256rrk_REV 100U, // VMOVDQU64Z256rrkz 100U, // VMOVDQU64Z256rrkz_REV 0U, // VMOVDQU64Zmr 164U, // VMOVDQU64Zmrk 0U, // VMOVDQU64Zrm 996U, // VMOVDQU64Zrmk 548U, // VMOVDQU64Zrmkz 0U, // VMOVDQU64Zrr 0U, // VMOVDQU64Zrr_REV 292U, // VMOVDQU64Zrrk 100U, // VMOVDQU64Zrrk_REV 100U, // VMOVDQU64Zrrkz 100U, // VMOVDQU64Zrrkz_REV 0U, // VMOVDQU8Z128mr 164U, // VMOVDQU8Z128mrk 0U, // VMOVDQU8Z128rm 676U, // VMOVDQU8Z128rmk 516U, // VMOVDQU8Z128rmkz 0U, // VMOVDQU8Z128rr 0U, // VMOVDQU8Z128rr_REV 292U, // VMOVDQU8Z128rrk 100U, // VMOVDQU8Z128rrk_REV 100U, // VMOVDQU8Z128rrkz 100U, // VMOVDQU8Z128rrkz_REV 0U, // VMOVDQU8Z256mr 164U, // VMOVDQU8Z256mrk 0U, // VMOVDQU8Z256rm 708U, // VMOVDQU8Z256rmk 484U, // VMOVDQU8Z256rmkz 0U, // VMOVDQU8Z256rr 0U, // VMOVDQU8Z256rr_REV 292U, // VMOVDQU8Z256rrk 100U, // VMOVDQU8Z256rrk_REV 100U, // VMOVDQU8Z256rrkz 100U, // VMOVDQU8Z256rrkz_REV 0U, // VMOVDQU8Zmr 164U, // VMOVDQU8Zmrk 0U, // VMOVDQU8Zrm 996U, // VMOVDQU8Zrmk 548U, // VMOVDQU8Zrmkz 0U, // VMOVDQU8Zrr 0U, // VMOVDQU8Zrr_REV 292U, // VMOVDQU8Zrrk 100U, // VMOVDQU8Zrrk_REV 100U, // VMOVDQU8Zrrkz 100U, // VMOVDQU8Zrrkz_REV 0U, // VMOVDQUYmr 0U, // VMOVDQUYrm 0U, // VMOVDQUYrr 0U, // VMOVDQUYrr_REV 0U, // VMOVDQUmr 0U, // VMOVDQUrm 0U, // VMOVDQUrr 0U, // VMOVDQUrr_REV 96U, // VMOVHLPSZrr 96U, // VMOVHLPSrr 0U, // VMOVHPDZ128mr 384U, // VMOVHPDZ128rm 0U, // VMOVHPDmr 384U, // VMOVHPDrm 0U, // VMOVHPSZ128mr 384U, // VMOVHPSZ128rm 0U, // VMOVHPSmr 384U, // VMOVHPSrm 96U, // VMOVLHPSZrr 96U, // VMOVLHPSrr 0U, // VMOVLPDZ128mr 384U, // VMOVLPDZ128rm 0U, // VMOVLPDmr 384U, // VMOVLPDrm 0U, // VMOVLPSZ128mr 384U, // VMOVLPSZ128rm 0U, // VMOVLPSmr 384U, // VMOVLPSrm 0U, // VMOVMSKPDYrr 0U, // VMOVMSKPDrr 0U, // VMOVMSKPSYrr 0U, // VMOVMSKPSrr 0U, // VMOVNTDQAYrm 0U, // VMOVNTDQAZ128rm 0U, // VMOVNTDQAZ256rm 0U, // VMOVNTDQAZrm 0U, // VMOVNTDQArm 0U, // VMOVNTDQYmr 0U, // VMOVNTDQZ128mr 0U, // VMOVNTDQZ256mr 0U, // VMOVNTDQZmr 0U, // VMOVNTDQmr 0U, // VMOVNTPDYmr 0U, // VMOVNTPDZ128mr 0U, // VMOVNTPDZ256mr 0U, // VMOVNTPDZmr 0U, // VMOVNTPDmr 0U, // VMOVNTPSYmr 0U, // VMOVNTPSZ128mr 0U, // VMOVNTPSZ256mr 0U, // VMOVNTPSZmr 0U, // VMOVNTPSmr 0U, // VMOVPDI2DIZmr 0U, // VMOVPDI2DIZrr 0U, // VMOVPDI2DImr 0U, // VMOVPDI2DIrr 0U, // VMOVPQI2QIZmr 0U, // VMOVPQI2QIZrr 0U, // VMOVPQI2QImr 0U, // VMOVPQI2QIrr 0U, // VMOVPQIto64Zmr 0U, // VMOVPQIto64Zrr 0U, // VMOVPQIto64mr 0U, // VMOVPQIto64rr 0U, // VMOVQI2PQIZrm 0U, // VMOVQI2PQIrm 0U, // VMOVSDZmr 164U, // VMOVSDZmrk 0U, // VMOVSDZrm 580U, // VMOVSDZrmk 388U, // VMOVSDZrmkz 96U, // VMOVSDZrr 96U, // VMOVSDZrr_REV 166180U, // VMOVSDZrrk 166180U, // VMOVSDZrrk_REV 198756U, // VMOVSDZrrkz 198756U, // VMOVSDZrrkz_REV 0U, // VMOVSDmr 0U, // VMOVSDrm 96U, // VMOVSDrr 96U, // VMOVSDrr_REV 0U, // VMOVSDto64Zmr 0U, // VMOVSDto64Zrr 0U, // VMOVSDto64mr 0U, // VMOVSDto64rr 0U, // VMOVSHDUPYrm 0U, // VMOVSHDUPYrr 0U, // VMOVSHDUPZ128rm 260U, // VMOVSHDUPZ128rmk 356U, // VMOVSHDUPZ128rmkz 0U, // VMOVSHDUPZ128rr 292U, // VMOVSHDUPZ128rrk 100U, // VMOVSHDUPZ128rrkz 0U, // VMOVSHDUPZ256rm 612U, // VMOVSHDUPZ256rmk 324U, // VMOVSHDUPZ256rmkz 0U, // VMOVSHDUPZ256rr 292U, // VMOVSHDUPZ256rrk 100U, // VMOVSHDUPZ256rrkz 0U, // VMOVSHDUPZrm 1060U, // VMOVSHDUPZrmk 420U, // VMOVSHDUPZrmkz 0U, // VMOVSHDUPZrr 292U, // VMOVSHDUPZrrk 100U, // VMOVSHDUPZrrkz 0U, // VMOVSHDUPrm 0U, // VMOVSHDUPrr 0U, // VMOVSLDUPYrm 0U, // VMOVSLDUPYrr 0U, // VMOVSLDUPZ128rm 260U, // VMOVSLDUPZ128rmk 356U, // VMOVSLDUPZ128rmkz 0U, // VMOVSLDUPZ128rr 292U, // VMOVSLDUPZ128rrk 100U, // VMOVSLDUPZ128rrkz 0U, // VMOVSLDUPZ256rm 612U, // VMOVSLDUPZ256rmk 324U, // VMOVSLDUPZ256rmkz 0U, // VMOVSLDUPZ256rr 292U, // VMOVSLDUPZ256rrk 100U, // VMOVSLDUPZ256rrkz 0U, // VMOVSLDUPZrm 1060U, // VMOVSLDUPZrmk 420U, // VMOVSLDUPZrmkz 0U, // VMOVSLDUPZrr 292U, // VMOVSLDUPZrrk 100U, // VMOVSLDUPZrrkz 0U, // VMOVSLDUPrm 0U, // VMOVSLDUPrr 0U, // VMOVSS2DIZmr 0U, // VMOVSS2DIZrr 0U, // VMOVSS2DImr 0U, // VMOVSS2DIrr 0U, // VMOVSSZmr 164U, // VMOVSSZmrk 0U, // VMOVSSZrm 740U, // VMOVSSZrmk 452U, // VMOVSSZrmkz 96U, // VMOVSSZrr 96U, // VMOVSSZrr_REV 166180U, // VMOVSSZrrk 166180U, // VMOVSSZrrk_REV 198756U, // VMOVSSZrrkz 198756U, // VMOVSSZrrkz_REV 0U, // VMOVSSmr 0U, // VMOVSSrm 96U, // VMOVSSrr 96U, // VMOVSSrr_REV 0U, // VMOVUPDYmr 0U, // VMOVUPDYrm 0U, // VMOVUPDYrr 0U, // VMOVUPDYrr_REV 0U, // VMOVUPDZ128mr 164U, // VMOVUPDZ128mrk 0U, // VMOVUPDZ128rm 260U, // VMOVUPDZ128rmk 356U, // VMOVUPDZ128rmkz 0U, // VMOVUPDZ128rr 0U, // VMOVUPDZ128rr_REV 292U, // VMOVUPDZ128rrk 100U, // VMOVUPDZ128rrk_REV 100U, // VMOVUPDZ128rrkz 100U, // VMOVUPDZ128rrkz_REV 0U, // VMOVUPDZ256mr 164U, // VMOVUPDZ256mrk 0U, // VMOVUPDZ256rm 612U, // VMOVUPDZ256rmk 324U, // VMOVUPDZ256rmkz 0U, // VMOVUPDZ256rr 0U, // VMOVUPDZ256rr_REV 292U, // VMOVUPDZ256rrk 100U, // VMOVUPDZ256rrk_REV 100U, // VMOVUPDZ256rrkz 100U, // VMOVUPDZ256rrkz_REV 0U, // VMOVUPDZmr 164U, // VMOVUPDZmrk 0U, // VMOVUPDZrm 1060U, // VMOVUPDZrmk 420U, // VMOVUPDZrmkz 0U, // VMOVUPDZrr 0U, // VMOVUPDZrr_REV 292U, // VMOVUPDZrrk 100U, // VMOVUPDZrrk_REV 100U, // VMOVUPDZrrkz 100U, // VMOVUPDZrrkz_REV 0U, // VMOVUPDmr 0U, // VMOVUPDrm 0U, // VMOVUPDrr 0U, // VMOVUPDrr_REV 0U, // VMOVUPSYmr 0U, // VMOVUPSYrm 0U, // VMOVUPSYrr 0U, // VMOVUPSYrr_REV 0U, // VMOVUPSZ128mr 164U, // VMOVUPSZ128mrk 0U, // VMOVUPSZ128rm 260U, // VMOVUPSZ128rmk 356U, // VMOVUPSZ128rmkz 0U, // VMOVUPSZ128rr 0U, // VMOVUPSZ128rr_REV 292U, // VMOVUPSZ128rrk 100U, // VMOVUPSZ128rrk_REV 100U, // VMOVUPSZ128rrkz 100U, // VMOVUPSZ128rrkz_REV 0U, // VMOVUPSZ256mr 164U, // VMOVUPSZ256mrk 0U, // VMOVUPSZ256rm 612U, // VMOVUPSZ256rmk 324U, // VMOVUPSZ256rmkz 0U, // VMOVUPSZ256rr 0U, // VMOVUPSZ256rr_REV 292U, // VMOVUPSZ256rrk 100U, // VMOVUPSZ256rrk_REV 100U, // VMOVUPSZ256rrkz 100U, // VMOVUPSZ256rrkz_REV 0U, // VMOVUPSZmr 164U, // VMOVUPSZmrk 0U, // VMOVUPSZrm 1060U, // VMOVUPSZrmk 420U, // VMOVUPSZrmkz 0U, // VMOVUPSZrr 0U, // VMOVUPSZrr_REV 292U, // VMOVUPSZrrk 100U, // VMOVUPSZrrk_REV 100U, // VMOVUPSZrrkz 100U, // VMOVUPSZrrkz_REV 0U, // VMOVUPSmr 0U, // VMOVUPSrm 0U, // VMOVUPSrr 0U, // VMOVUPSrr_REV 0U, // VMOVZPQILo2PQIZrr 0U, // VMOVZPQILo2PQIrr 461280U, // VMPSADBWYrmi 624736U, // VMPSADBWYrri 461312U, // VMPSADBWrmi 624736U, // VMPSADBWrri 0U, // VMPTRLDm 0U, // VMPTRSTm 0U, // VMREAD32mr 0U, // VMREAD32rr 0U, // VMREAD64mr 0U, // VMREAD64rr 0U, // VMRESUME 0U, // VMRUN32 0U, // VMRUN64 0U, // VMSAVE32 0U, // VMSAVE64 320U, // VMULPDYrm 96U, // VMULPDYrr 352U, // VMULPDZ128rm 4480U, // VMULPDZ128rmb 1116452U, // VMULPDZ128rmbk 1149028U, // VMULPDZ128rmbkz 35108U, // VMULPDZ128rmk 133220U, // VMULPDZ128rmkz 96U, // VMULPDZ128rr 166180U, // VMULPDZ128rrk 198756U, // VMULPDZ128rrkz 320U, // VMULPDZ256rm 6528U, // VMULPDZ256rmb 2165028U, // VMULPDZ256rmbk 2197604U, // VMULPDZ256rmbkz 231716U, // VMULPDZ256rmk 264292U, // VMULPDZ256rmkz 96U, // VMULPDZ256rr 166180U, // VMULPDZ256rrk 198756U, // VMULPDZ256rrkz 416U, // VMULPDZrm 8576U, // VMULPDZrmb 3213604U, // VMULPDZrmbk 3246180U, // VMULPDZrmbkz 297252U, // VMULPDZrmk 329828U, // VMULPDZrmkz 96U, // VMULPDZrr 362592U, // VMULPDZrrb 4360484U, // VMULPDZrrbk 21170276U, // VMULPDZrrbkz 166180U, // VMULPDZrrk 198756U, // VMULPDZrrkz 352U, // VMULPDrm 96U, // VMULPDrr 320U, // VMULPSYrm 96U, // VMULPSYrr 352U, // VMULPSZ128rm 6592U, // VMULPSZ128rmb 2492708U, // VMULPSZ128rmbk 2525284U, // VMULPSZ128rmbkz 35108U, // VMULPSZ128rmk 133220U, // VMULPSZ128rmkz 96U, // VMULPSZ128rr 166180U, // VMULPSZ128rrk 198756U, // VMULPSZ128rrkz 320U, // VMULPSZ256rm 8640U, // VMULPSZ256rmb 3541284U, // VMULPSZ256rmbk 3573860U, // VMULPSZ256rmbkz 231716U, // VMULPSZ256rmk 264292U, // VMULPSZ256rmkz 96U, // VMULPSZ256rr 166180U, // VMULPSZ256rrk 198756U, // VMULPSZ256rrkz 416U, // VMULPSZrm 10688U, // VMULPSZrmb 5638436U, // VMULPSZrmbk 5671012U, // VMULPSZrmbkz 297252U, // VMULPSZrmk 329828U, // VMULPSZrmkz 96U, // VMULPSZrr 362592U, // VMULPSZrrb 4360484U, // VMULPSZrrbk 21170276U, // VMULPSZrrbkz 166180U, // VMULPSZrrk 198756U, // VMULPSZrrkz 352U, // VMULPSrm 96U, // VMULPSrr 384U, // VMULSDZrm 384U, // VMULSDZrm_Int 67876U, // VMULSDZrm_Intk 100452U, // VMULSDZrm_Intkz 96U, // VMULSDZrr 96U, // VMULSDZrr_Int 166180U, // VMULSDZrr_Intk 198756U, // VMULSDZrr_Intkz 362592U, // VMULSDZrrb_Int 4360484U, // VMULSDZrrb_Intk 21170276U, // VMULSDZrrb_Intkz 384U, // VMULSDrm 384U, // VMULSDrm_Int 96U, // VMULSDrr 96U, // VMULSDrr_Int 448U, // VMULSSZrm 448U, // VMULSSZrm_Int 395556U, // VMULSSZrm_Intk 428132U, // VMULSSZrm_Intkz 96U, // VMULSSZrr 96U, // VMULSSZrr_Int 166180U, // VMULSSZrr_Intk 198756U, // VMULSSZrr_Intkz 362592U, // VMULSSZrrb_Int 4360484U, // VMULSSZrrb_Intk 21170276U, // VMULSSZrrb_Intkz 448U, // VMULSSrm 448U, // VMULSSrm_Int 96U, // VMULSSrr 96U, // VMULSSrr_Int 0U, // VMWRITE32rm 0U, // VMWRITE32rr 0U, // VMWRITE64rm 0U, // VMWRITE64rr 0U, // VMXOFF 0U, // VMXON 320U, // VORPDYrm 96U, // VORPDYrr 352U, // VORPDZ128rm 4480U, // VORPDZ128rmb 1116452U, // VORPDZ128rmbk 1149028U, // VORPDZ128rmbkz 35108U, // VORPDZ128rmk 133220U, // VORPDZ128rmkz 96U, // VORPDZ128rr 166180U, // VORPDZ128rrk 198756U, // VORPDZ128rrkz 320U, // VORPDZ256rm 6528U, // VORPDZ256rmb 2165028U, // VORPDZ256rmbk 2197604U, // VORPDZ256rmbkz 231716U, // VORPDZ256rmk 264292U, // VORPDZ256rmkz 96U, // VORPDZ256rr 166180U, // VORPDZ256rrk 198756U, // VORPDZ256rrkz 416U, // VORPDZrm 8576U, // VORPDZrmb 3213604U, // VORPDZrmbk 3246180U, // VORPDZrmbkz 297252U, // VORPDZrmk 329828U, // VORPDZrmkz 96U, // VORPDZrr 166180U, // VORPDZrrk 198756U, // VORPDZrrkz 352U, // VORPDrm 96U, // VORPDrr 320U, // VORPSYrm 96U, // VORPSYrr 352U, // VORPSZ128rm 6592U, // VORPSZ128rmb 2492708U, // VORPSZ128rmbk 2525284U, // VORPSZ128rmbkz 35108U, // VORPSZ128rmk 133220U, // VORPSZ128rmkz 96U, // VORPSZ128rr 166180U, // VORPSZ128rrk 198756U, // VORPSZ128rrkz 320U, // VORPSZ256rm 8640U, // VORPSZ256rmb 3541284U, // VORPSZ256rmbk 3573860U, // VORPSZ256rmbkz 231716U, // VORPSZ256rmk 264292U, // VORPSZ256rmkz 96U, // VORPSZ256rr 166180U, // VORPSZ256rrk 198756U, // VORPSZ256rrkz 416U, // VORPSZrm 10688U, // VORPSZrmb 5638436U, // VORPSZrmbk 5671012U, // VORPSZrmbkz 297252U, // VORPSZrmk 329828U, // VORPSZrmkz 96U, // VORPSZrr 166180U, // VORPSZrrk 198756U, // VORPSZrrkz 352U, // VORPSrm 96U, // VORPSrr 256U, // VP4DPWSSDSrm 35108U, // VP4DPWSSDSrmk 35108U, // VP4DPWSSDSrmkz 256U, // VP4DPWSSDrm 35108U, // VP4DPWSSDrmk 35108U, // VP4DPWSSDrmkz 0U, // VPABSBYrm 0U, // VPABSBYrr 0U, // VPABSBZ128rm 676U, // VPABSBZ128rmk 516U, // VPABSBZ128rmkz 0U, // VPABSBZ128rr 292U, // VPABSBZ128rrk 100U, // VPABSBZ128rrkz 0U, // VPABSBZ256rm 708U, // VPABSBZ256rmk 484U, // VPABSBZ256rmkz 0U, // VPABSBZ256rr 292U, // VPABSBZ256rrk 100U, // VPABSBZ256rrkz 0U, // VPABSBZrm 996U, // VPABSBZrmk 548U, // VPABSBZrmkz 0U, // VPABSBZrr 292U, // VPABSBZrrk 100U, // VPABSBZrrkz 0U, // VPABSBrm 0U, // VPABSBrr 0U, // VPABSDYrm 0U, // VPABSDYrr 0U, // VPABSDZ128rm 9U, // VPABSDZ128rmb 7108U, // VPABSDZ128rmbk 6212U, // VPABSDZ128rmbkz 676U, // VPABSDZ128rmk 516U, // VPABSDZ128rmkz 0U, // VPABSDZ128rr 292U, // VPABSDZ128rrk 100U, // VPABSDZ128rrkz 0U, // VPABSDZ256rm 10U, // VPABSDZ256rmb 9156U, // VPABSDZ256rmbk 8260U, // VPABSDZ256rmbkz 708U, // VPABSDZ256rmk 484U, // VPABSDZ256rmkz 0U, // VPABSDZ256rr 292U, // VPABSDZ256rrk 100U, // VPABSDZ256rrkz 0U, // VPABSDZrm 10U, // VPABSDZrmb 11204U, // VPABSDZrmbk 10308U, // VPABSDZrmbkz 996U, // VPABSDZrmk 548U, // VPABSDZrmkz 0U, // VPABSDZrr 292U, // VPABSDZrrk 100U, // VPABSDZrrkz 0U, // VPABSDrm 0U, // VPABSDrr 0U, // VPABSQZ128rm 9U, // VPABSQZ128rmb 4740U, // VPABSQZ128rmbk 4228U, // VPABSQZ128rmbkz 676U, // VPABSQZ128rmk 516U, // VPABSQZ128rmkz 0U, // VPABSQZ128rr 292U, // VPABSQZ128rrk 100U, // VPABSQZ128rrkz 0U, // VPABSQZ256rm 9U, // VPABSQZ256rmb 6788U, // VPABSQZ256rmbk 6276U, // VPABSQZ256rmbkz 708U, // VPABSQZ256rmk 484U, // VPABSQZ256rmkz 0U, // VPABSQZ256rr 292U, // VPABSQZ256rrk 100U, // VPABSQZ256rrkz 0U, // VPABSQZrm 10U, // VPABSQZrmb 8836U, // VPABSQZrmbk 8324U, // VPABSQZrmbkz 996U, // VPABSQZrmk 548U, // VPABSQZrmkz 0U, // VPABSQZrr 292U, // VPABSQZrrk 100U, // VPABSQZrrkz 0U, // VPABSWYrm 0U, // VPABSWYrr 0U, // VPABSWZ128rm 676U, // VPABSWZ128rmk 516U, // VPABSWZ128rmkz 0U, // VPABSWZ128rr 292U, // VPABSWZ128rrk 100U, // VPABSWZ128rrkz 0U, // VPABSWZ256rm 708U, // VPABSWZ256rmk 484U, // VPABSWZ256rmkz 0U, // VPABSWZ256rr 292U, // VPABSWZ256rrk 100U, // VPABSWZ256rrkz 0U, // VPABSWZrm 996U, // VPABSWZrmk 548U, // VPABSWZrmkz 0U, // VPABSWZrr 292U, // VPABSWZrrk 100U, // VPABSWZrrkz 0U, // VPABSWrm 0U, // VPABSWrr 480U, // VPACKSSDWYrm 96U, // VPACKSSDWYrr 512U, // VPACKSSDWZ128rm 6208U, // VPACKSSDWZ128rmb 2591012U, // VPACKSSDWZ128rmbk 2623588U, // VPACKSSDWZ128rmbkz 559396U, // VPACKSSDWZ128rmk 591972U, // VPACKSSDWZ128rmkz 96U, // VPACKSSDWZ128rr 166180U, // VPACKSSDWZ128rrk 198756U, // VPACKSSDWZ128rrkz 480U, // VPACKSSDWZ256rm 8256U, // VPACKSSDWZ256rmb 3639588U, // VPACKSSDWZ256rmbk 3672164U, // VPACKSSDWZ256rmbkz 657700U, // VPACKSSDWZ256rmk 690276U, // VPACKSSDWZ256rmkz 96U, // VPACKSSDWZ256rr 166180U, // VPACKSSDWZ256rrk 198756U, // VPACKSSDWZ256rrkz 544U, // VPACKSSDWZrm 10304U, // VPACKSSDWZrmb 5736740U, // VPACKSSDWZrmbk 5769316U, // VPACKSSDWZrmbkz 723236U, // VPACKSSDWZrmk 755812U, // VPACKSSDWZrmkz 96U, // VPACKSSDWZrr 166180U, // VPACKSSDWZrrk 198756U, // VPACKSSDWZrrkz 512U, // VPACKSSDWrm 96U, // VPACKSSDWrr 480U, // VPACKSSWBYrm 96U, // VPACKSSWBYrr 512U, // VPACKSSWBZ128rm 559396U, // VPACKSSWBZ128rmk 591972U, // VPACKSSWBZ128rmkz 96U, // VPACKSSWBZ128rr 166180U, // VPACKSSWBZ128rrk 198756U, // VPACKSSWBZ128rrkz 480U, // VPACKSSWBZ256rm 657700U, // VPACKSSWBZ256rmk 690276U, // VPACKSSWBZ256rmkz 96U, // VPACKSSWBZ256rr 166180U, // VPACKSSWBZ256rrk 198756U, // VPACKSSWBZ256rrkz 544U, // VPACKSSWBZrm 723236U, // VPACKSSWBZrmk 755812U, // VPACKSSWBZrmkz 96U, // VPACKSSWBZrr 166180U, // VPACKSSWBZrrk 198756U, // VPACKSSWBZrrkz 512U, // VPACKSSWBrm 96U, // VPACKSSWBrr 480U, // VPACKUSDWYrm 96U, // VPACKUSDWYrr 512U, // VPACKUSDWZ128rm 6208U, // VPACKUSDWZ128rmb 2591012U, // VPACKUSDWZ128rmbk 2623588U, // VPACKUSDWZ128rmbkz 559396U, // VPACKUSDWZ128rmk 591972U, // VPACKUSDWZ128rmkz 96U, // VPACKUSDWZ128rr 166180U, // VPACKUSDWZ128rrk 198756U, // VPACKUSDWZ128rrkz 480U, // VPACKUSDWZ256rm 8256U, // VPACKUSDWZ256rmb 3639588U, // VPACKUSDWZ256rmbk 3672164U, // VPACKUSDWZ256rmbkz 657700U, // VPACKUSDWZ256rmk 690276U, // VPACKUSDWZ256rmkz 96U, // VPACKUSDWZ256rr 166180U, // VPACKUSDWZ256rrk 198756U, // VPACKUSDWZ256rrkz 544U, // VPACKUSDWZrm 10304U, // VPACKUSDWZrmb 5736740U, // VPACKUSDWZrmbk 5769316U, // VPACKUSDWZrmbkz 723236U, // VPACKUSDWZrmk 755812U, // VPACKUSDWZrmkz 96U, // VPACKUSDWZrr 166180U, // VPACKUSDWZrrk 198756U, // VPACKUSDWZrrkz 512U, // VPACKUSDWrm 96U, // VPACKUSDWrr 480U, // VPACKUSWBYrm 96U, // VPACKUSWBYrr 512U, // VPACKUSWBZ128rm 559396U, // VPACKUSWBZ128rmk 591972U, // VPACKUSWBZ128rmkz 96U, // VPACKUSWBZ128rr 166180U, // VPACKUSWBZ128rrk 198756U, // VPACKUSWBZ128rrkz 480U, // VPACKUSWBZ256rm 657700U, // VPACKUSWBZ256rmk 690276U, // VPACKUSWBZ256rmkz 96U, // VPACKUSWBZ256rr 166180U, // VPACKUSWBZ256rrk 198756U, // VPACKUSWBZ256rrkz 544U, // VPACKUSWBZrm 723236U, // VPACKUSWBZrmk 755812U, // VPACKUSWBZrmkz 96U, // VPACKUSWBZrr 166180U, // VPACKUSWBZrrk 198756U, // VPACKUSWBZrrkz 512U, // VPACKUSWBrm 96U, // VPACKUSWBrr 480U, // VPADDBYrm 96U, // VPADDBYrr 512U, // VPADDBZ128rm 559396U, // VPADDBZ128rmk 591972U, // VPADDBZ128rmkz 96U, // VPADDBZ128rr 166180U, // VPADDBZ128rrk 198756U, // VPADDBZ128rrkz 480U, // VPADDBZ256rm 657700U, // VPADDBZ256rmk 690276U, // VPADDBZ256rmkz 96U, // VPADDBZ256rr 166180U, // VPADDBZ256rrk 198756U, // VPADDBZ256rrkz 544U, // VPADDBZrm 723236U, // VPADDBZrmk 755812U, // VPADDBZrmkz 96U, // VPADDBZrr 166180U, // VPADDBZrrk 198756U, // VPADDBZrrkz 512U, // VPADDBrm 96U, // VPADDBrr 480U, // VPADDDYrm 96U, // VPADDDYrr 512U, // VPADDDZ128rm 6208U, // VPADDDZ128rmb 2591012U, // VPADDDZ128rmbk 2623588U, // VPADDDZ128rmbkz 559396U, // VPADDDZ128rmk 591972U, // VPADDDZ128rmkz 96U, // VPADDDZ128rr 166180U, // VPADDDZ128rrk 198756U, // VPADDDZ128rrkz 480U, // VPADDDZ256rm 8256U, // VPADDDZ256rmb 3639588U, // VPADDDZ256rmbk 3672164U, // VPADDDZ256rmbkz 657700U, // VPADDDZ256rmk 690276U, // VPADDDZ256rmkz 96U, // VPADDDZ256rr 166180U, // VPADDDZ256rrk 198756U, // VPADDDZ256rrkz 544U, // VPADDDZrm 10304U, // VPADDDZrmb 5736740U, // VPADDDZrmbk 5769316U, // VPADDDZrmbkz 723236U, // VPADDDZrmk 755812U, // VPADDDZrmkz 96U, // VPADDDZrr 166180U, // VPADDDZrrk 198756U, // VPADDDZrrkz 512U, // VPADDDrm 96U, // VPADDDrr 480U, // VPADDQYrm 96U, // VPADDQYrr 512U, // VPADDQZ128rm 4224U, // VPADDQZ128rmb 1837348U, // VPADDQZ128rmbk 1869924U, // VPADDQZ128rmbkz 559396U, // VPADDQZ128rmk 591972U, // VPADDQZ128rmkz 96U, // VPADDQZ128rr 166180U, // VPADDQZ128rrk 198756U, // VPADDQZ128rrkz 480U, // VPADDQZ256rm 6272U, // VPADDQZ256rmb 2885924U, // VPADDQZ256rmbk 2918500U, // VPADDQZ256rmbkz 657700U, // VPADDQZ256rmk 690276U, // VPADDQZ256rmkz 96U, // VPADDQZ256rr 166180U, // VPADDQZ256rrk 198756U, // VPADDQZ256rrkz 544U, // VPADDQZrm 8320U, // VPADDQZrmb 3934500U, // VPADDQZrmbk 3967076U, // VPADDQZrmbkz 723236U, // VPADDQZrmk 755812U, // VPADDQZrmkz 96U, // VPADDQZrr 166180U, // VPADDQZrrk 198756U, // VPADDQZrrkz 512U, // VPADDQrm 96U, // VPADDQrr 480U, // VPADDSBYrm 96U, // VPADDSBYrr 512U, // VPADDSBZ128rm 559396U, // VPADDSBZ128rmk 591972U, // VPADDSBZ128rmkz 96U, // VPADDSBZ128rr 166180U, // VPADDSBZ128rrk 198756U, // VPADDSBZ128rrkz 480U, // VPADDSBZ256rm 657700U, // VPADDSBZ256rmk 690276U, // VPADDSBZ256rmkz 96U, // VPADDSBZ256rr 166180U, // VPADDSBZ256rrk 198756U, // VPADDSBZ256rrkz 544U, // VPADDSBZrm 723236U, // VPADDSBZrmk 755812U, // VPADDSBZrmkz 96U, // VPADDSBZrr 166180U, // VPADDSBZrrk 198756U, // VPADDSBZrrkz 512U, // VPADDSBrm 96U, // VPADDSBrr 480U, // VPADDSWYrm 96U, // VPADDSWYrr 512U, // VPADDSWZ128rm 559396U, // VPADDSWZ128rmk 591972U, // VPADDSWZ128rmkz 96U, // VPADDSWZ128rr 166180U, // VPADDSWZ128rrk 198756U, // VPADDSWZ128rrkz 480U, // VPADDSWZ256rm 657700U, // VPADDSWZ256rmk 690276U, // VPADDSWZ256rmkz 96U, // VPADDSWZ256rr 166180U, // VPADDSWZ256rrk 198756U, // VPADDSWZ256rrkz 544U, // VPADDSWZrm 723236U, // VPADDSWZrmk 755812U, // VPADDSWZrmkz 96U, // VPADDSWZrr 166180U, // VPADDSWZrrk 198756U, // VPADDSWZrrkz 512U, // VPADDSWrm 96U, // VPADDSWrr 480U, // VPADDUSBYrm 96U, // VPADDUSBYrr 512U, // VPADDUSBZ128rm 559396U, // VPADDUSBZ128rmk 591972U, // VPADDUSBZ128rmkz 96U, // VPADDUSBZ128rr 166180U, // VPADDUSBZ128rrk 198756U, // VPADDUSBZ128rrkz 480U, // VPADDUSBZ256rm 657700U, // VPADDUSBZ256rmk 690276U, // VPADDUSBZ256rmkz 96U, // VPADDUSBZ256rr 166180U, // VPADDUSBZ256rrk 198756U, // VPADDUSBZ256rrkz 544U, // VPADDUSBZrm 723236U, // VPADDUSBZrmk 755812U, // VPADDUSBZrmkz 96U, // VPADDUSBZrr 166180U, // VPADDUSBZrrk 198756U, // VPADDUSBZrrkz 512U, // VPADDUSBrm 96U, // VPADDUSBrr 480U, // VPADDUSWYrm 96U, // VPADDUSWYrr 512U, // VPADDUSWZ128rm 559396U, // VPADDUSWZ128rmk 591972U, // VPADDUSWZ128rmkz 96U, // VPADDUSWZ128rr 166180U, // VPADDUSWZ128rrk 198756U, // VPADDUSWZ128rrkz 480U, // VPADDUSWZ256rm 657700U, // VPADDUSWZ256rmk 690276U, // VPADDUSWZ256rmkz 96U, // VPADDUSWZ256rr 166180U, // VPADDUSWZ256rrk 198756U, // VPADDUSWZ256rrkz 544U, // VPADDUSWZrm 723236U, // VPADDUSWZrmk 755812U, // VPADDUSWZrmkz 96U, // VPADDUSWZrr 166180U, // VPADDUSWZrrk 198756U, // VPADDUSWZrrkz 512U, // VPADDUSWrm 96U, // VPADDUSWrr 480U, // VPADDWYrm 96U, // VPADDWYrr 512U, // VPADDWZ128rm 559396U, // VPADDWZ128rmk 591972U, // VPADDWZ128rmkz 96U, // VPADDWZ128rr 166180U, // VPADDWZ128rrk 198756U, // VPADDWZ128rrkz 480U, // VPADDWZ256rm 657700U, // VPADDWZ256rmk 690276U, // VPADDWZ256rmkz 96U, // VPADDWZ256rr 166180U, // VPADDWZ256rrk 198756U, // VPADDWZ256rrkz 544U, // VPADDWZrm 723236U, // VPADDWZrmk 755812U, // VPADDWZrmkz 96U, // VPADDWZrr 166180U, // VPADDWZrrk 198756U, // VPADDWZrrkz 512U, // VPADDWrm 96U, // VPADDWrr 461280U, // VPALIGNRYrmi 624736U, // VPALIGNRYrri 461312U, // VPALIGNRZ128rmi 38308132U, // VPALIGNRZ128rmik 55117924U, // VPALIGNRZ128rmikz 624736U, // VPALIGNRZ128rri 71469348U, // VPALIGNRZ128rrik 88279140U, // VPALIGNRZ128rrikz 461280U, // VPALIGNRZ256rmi 38406436U, // VPALIGNRZ256rmik 55216228U, // VPALIGNRZ256rmikz 624736U, // VPALIGNRZ256rri 71469348U, // VPALIGNRZ256rrik 88279140U, // VPALIGNRZ256rrikz 461344U, // VPALIGNRZrmi 38471972U, // VPALIGNRZrmik 55281764U, // VPALIGNRZrmikz 624736U, // VPALIGNRZrri 71469348U, // VPALIGNRZrrik 88279140U, // VPALIGNRZrrikz 461312U, // VPALIGNRrmi 624736U, // VPALIGNRrri 512U, // VPANDDZ128rm 6208U, // VPANDDZ128rmb 2591012U, // VPANDDZ128rmbk 2623588U, // VPANDDZ128rmbkz 559396U, // VPANDDZ128rmk 591972U, // VPANDDZ128rmkz 96U, // VPANDDZ128rr 166180U, // VPANDDZ128rrk 198756U, // VPANDDZ128rrkz 480U, // VPANDDZ256rm 8256U, // VPANDDZ256rmb 3639588U, // VPANDDZ256rmbk 3672164U, // VPANDDZ256rmbkz 657700U, // VPANDDZ256rmk 690276U, // VPANDDZ256rmkz 96U, // VPANDDZ256rr 166180U, // VPANDDZ256rrk 198756U, // VPANDDZ256rrkz 544U, // VPANDDZrm 10304U, // VPANDDZrmb 5736740U, // VPANDDZrmbk 5769316U, // VPANDDZrmbkz 723236U, // VPANDDZrmk 755812U, // VPANDDZrmkz 96U, // VPANDDZrr 166180U, // VPANDDZrrk 198756U, // VPANDDZrrkz 512U, // VPANDNDZ128rm 6208U, // VPANDNDZ128rmb 2591012U, // VPANDNDZ128rmbk 2623588U, // VPANDNDZ128rmbkz 559396U, // VPANDNDZ128rmk 591972U, // VPANDNDZ128rmkz 96U, // VPANDNDZ128rr 166180U, // VPANDNDZ128rrk 198756U, // VPANDNDZ128rrkz 480U, // VPANDNDZ256rm 8256U, // VPANDNDZ256rmb 3639588U, // VPANDNDZ256rmbk 3672164U, // VPANDNDZ256rmbkz 657700U, // VPANDNDZ256rmk 690276U, // VPANDNDZ256rmkz 96U, // VPANDNDZ256rr 166180U, // VPANDNDZ256rrk 198756U, // VPANDNDZ256rrkz 544U, // VPANDNDZrm 10304U, // VPANDNDZrmb 5736740U, // VPANDNDZrmbk 5769316U, // VPANDNDZrmbkz 723236U, // VPANDNDZrmk 755812U, // VPANDNDZrmkz 96U, // VPANDNDZrr 166180U, // VPANDNDZrrk 198756U, // VPANDNDZrrkz 512U, // VPANDNQZ128rm 4224U, // VPANDNQZ128rmb 1837348U, // VPANDNQZ128rmbk 1869924U, // VPANDNQZ128rmbkz 559396U, // VPANDNQZ128rmk 591972U, // VPANDNQZ128rmkz 96U, // VPANDNQZ128rr 166180U, // VPANDNQZ128rrk 198756U, // VPANDNQZ128rrkz 480U, // VPANDNQZ256rm 6272U, // VPANDNQZ256rmb 2885924U, // VPANDNQZ256rmbk 2918500U, // VPANDNQZ256rmbkz 657700U, // VPANDNQZ256rmk 690276U, // VPANDNQZ256rmkz 96U, // VPANDNQZ256rr 166180U, // VPANDNQZ256rrk 198756U, // VPANDNQZ256rrkz 544U, // VPANDNQZrm 8320U, // VPANDNQZrmb 3934500U, // VPANDNQZrmbk 3967076U, // VPANDNQZrmbkz 723236U, // VPANDNQZrmk 755812U, // VPANDNQZrmkz 96U, // VPANDNQZrr 166180U, // VPANDNQZrrk 198756U, // VPANDNQZrrkz 480U, // VPANDNYrm 96U, // VPANDNYrr 512U, // VPANDNrm 96U, // VPANDNrr 512U, // VPANDQZ128rm 4224U, // VPANDQZ128rmb 1837348U, // VPANDQZ128rmbk 1869924U, // VPANDQZ128rmbkz 559396U, // VPANDQZ128rmk 591972U, // VPANDQZ128rmkz 96U, // VPANDQZ128rr 166180U, // VPANDQZ128rrk 198756U, // VPANDQZ128rrkz 480U, // VPANDQZ256rm 6272U, // VPANDQZ256rmb 2885924U, // VPANDQZ256rmbk 2918500U, // VPANDQZ256rmbkz 657700U, // VPANDQZ256rmk 690276U, // VPANDQZ256rmkz 96U, // VPANDQZ256rr 166180U, // VPANDQZ256rrk 198756U, // VPANDQZ256rrkz 544U, // VPANDQZrm 8320U, // VPANDQZrmb 3934500U, // VPANDQZrmbk 3967076U, // VPANDQZrmbkz 723236U, // VPANDQZrmk 755812U, // VPANDQZrmkz 96U, // VPANDQZrr 166180U, // VPANDQZrrk 198756U, // VPANDQZrrkz 480U, // VPANDYrm 96U, // VPANDYrr 512U, // VPANDrm 96U, // VPANDrr 480U, // VPAVGBYrm 96U, // VPAVGBYrr 512U, // VPAVGBZ128rm 559396U, // VPAVGBZ128rmk 591972U, // VPAVGBZ128rmkz 96U, // VPAVGBZ128rr 166180U, // VPAVGBZ128rrk 198756U, // VPAVGBZ128rrkz 480U, // VPAVGBZ256rm 657700U, // VPAVGBZ256rmk 690276U, // VPAVGBZ256rmkz 96U, // VPAVGBZ256rr 166180U, // VPAVGBZ256rrk 198756U, // VPAVGBZ256rrkz 544U, // VPAVGBZrm 723236U, // VPAVGBZrmk 755812U, // VPAVGBZrmkz 96U, // VPAVGBZrr 166180U, // VPAVGBZrrk 198756U, // VPAVGBZrrkz 512U, // VPAVGBrm 96U, // VPAVGBrr 480U, // VPAVGWYrm 96U, // VPAVGWYrr 512U, // VPAVGWZ128rm 559396U, // VPAVGWZ128rmk 591972U, // VPAVGWZ128rmkz 96U, // VPAVGWZ128rr 166180U, // VPAVGWZ128rrk 198756U, // VPAVGWZ128rrkz 480U, // VPAVGWZ256rm 657700U, // VPAVGWZ256rmk 690276U, // VPAVGWZ256rmkz 96U, // VPAVGWZ256rr 166180U, // VPAVGWZ256rrk 198756U, // VPAVGWZ256rrkz 544U, // VPAVGWZrm 723236U, // VPAVGWZrmk 755812U, // VPAVGWZrmkz 96U, // VPAVGWZrr 166180U, // VPAVGWZrrk 198756U, // VPAVGWZrrkz 512U, // VPAVGWrm 96U, // VPAVGWrr 461280U, // VPBLENDDYrmi 624736U, // VPBLENDDYrri 461312U, // VPBLENDDrmi 624736U, // VPBLENDDrri 512U, // VPBLENDMBZ128rm 591972U, // VPBLENDMBZ128rmk 591972U, // VPBLENDMBZ128rmkz 96U, // VPBLENDMBZ128rr 198756U, // VPBLENDMBZ128rrk 198756U, // VPBLENDMBZ128rrkz 480U, // VPBLENDMBZ256rm 690276U, // VPBLENDMBZ256rmk 690276U, // VPBLENDMBZ256rmkz 96U, // VPBLENDMBZ256rr 198756U, // VPBLENDMBZ256rrk 198756U, // VPBLENDMBZ256rrkz 544U, // VPBLENDMBZrm 755812U, // VPBLENDMBZrmk 755812U, // VPBLENDMBZrmkz 96U, // VPBLENDMBZrr 198756U, // VPBLENDMBZrrk 198756U, // VPBLENDMBZrrkz 512U, // VPBLENDMDZ128rm 6208U, // VPBLENDMDZ128rmb 2623588U, // VPBLENDMDZ128rmbk 2623588U, // VPBLENDMDZ128rmbkz 591972U, // VPBLENDMDZ128rmk 591972U, // VPBLENDMDZ128rmkz 96U, // VPBLENDMDZ128rr 198756U, // VPBLENDMDZ128rrk 198756U, // VPBLENDMDZ128rrkz 480U, // VPBLENDMDZ256rm 8256U, // VPBLENDMDZ256rmb 3672164U, // VPBLENDMDZ256rmbk 3672164U, // VPBLENDMDZ256rmbkz 690276U, // VPBLENDMDZ256rmk 690276U, // VPBLENDMDZ256rmkz 96U, // VPBLENDMDZ256rr 198756U, // VPBLENDMDZ256rrk 198756U, // VPBLENDMDZ256rrkz 544U, // VPBLENDMDZrm 10304U, // VPBLENDMDZrmb 5769316U, // VPBLENDMDZrmbk 5769316U, // VPBLENDMDZrmbkz 755812U, // VPBLENDMDZrmk 755812U, // VPBLENDMDZrmkz 96U, // VPBLENDMDZrr 198756U, // VPBLENDMDZrrk 198756U, // VPBLENDMDZrrkz 512U, // VPBLENDMQZ128rm 4224U, // VPBLENDMQZ128rmb 1869924U, // VPBLENDMQZ128rmbk 1869924U, // VPBLENDMQZ128rmbkz 591972U, // VPBLENDMQZ128rmk 591972U, // VPBLENDMQZ128rmkz 96U, // VPBLENDMQZ128rr 198756U, // VPBLENDMQZ128rrk 198756U, // VPBLENDMQZ128rrkz 480U, // VPBLENDMQZ256rm 6272U, // VPBLENDMQZ256rmb 2918500U, // VPBLENDMQZ256rmbk 2918500U, // VPBLENDMQZ256rmbkz 690276U, // VPBLENDMQZ256rmk 690276U, // VPBLENDMQZ256rmkz 96U, // VPBLENDMQZ256rr 198756U, // VPBLENDMQZ256rrk 198756U, // VPBLENDMQZ256rrkz 544U, // VPBLENDMQZrm 8320U, // VPBLENDMQZrmb 3967076U, // VPBLENDMQZrmbk 3967076U, // VPBLENDMQZrmbkz 755812U, // VPBLENDMQZrmk 755812U, // VPBLENDMQZrmkz 96U, // VPBLENDMQZrr 198756U, // VPBLENDMQZrrk 198756U, // VPBLENDMQZrrkz 512U, // VPBLENDMWZ128rm 591972U, // VPBLENDMWZ128rmk 591972U, // VPBLENDMWZ128rmkz 96U, // VPBLENDMWZ128rr 198756U, // VPBLENDMWZ128rrk 198756U, // VPBLENDMWZ128rrkz 480U, // VPBLENDMWZ256rm 690276U, // VPBLENDMWZ256rmk 690276U, // VPBLENDMWZ256rmkz 96U, // VPBLENDMWZ256rr 198756U, // VPBLENDMWZ256rrk 198756U, // VPBLENDMWZ256rrkz 544U, // VPBLENDMWZrm 755812U, // VPBLENDMWZrmk 755812U, // VPBLENDMWZrmkz 96U, // VPBLENDMWZrr 198756U, // VPBLENDMWZrrk 198756U, // VPBLENDMWZrrkz 854496U, // VPBLENDVBYrm 198752U, // VPBLENDVBYrr 854528U, // VPBLENDVBrm 198752U, // VPBLENDVBrr 461280U, // VPBLENDWYrmi 624736U, // VPBLENDWYrri 461312U, // VPBLENDWrmi 624736U, // VPBLENDWrri 0U, // VPBROADCASTBYrm 0U, // VPBROADCASTBYrr 0U, // VPBROADCASTBZ128m 1156U, // VPBROADCASTBZ128mk 1124U, // VPBROADCASTBZ128mkz 0U, // VPBROADCASTBZ128r 292U, // VPBROADCASTBZ128rk 100U, // VPBROADCASTBZ128rkz 0U, // VPBROADCASTBZ256m 1156U, // VPBROADCASTBZ256mk 1124U, // VPBROADCASTBZ256mkz 0U, // VPBROADCASTBZ256r 292U, // VPBROADCASTBZ256rk 100U, // VPBROADCASTBZ256rkz 0U, // VPBROADCASTBZm 1156U, // VPBROADCASTBZmk 1124U, // VPBROADCASTBZmkz 0U, // VPBROADCASTBZr 292U, // VPBROADCASTBZrk 100U, // VPBROADCASTBZrkz 0U, // VPBROADCASTBrZ128r 292U, // VPBROADCASTBrZ128rk 100U, // VPBROADCASTBrZ128rkz 0U, // VPBROADCASTBrZ256r 292U, // VPBROADCASTBrZ256rk 100U, // VPBROADCASTBrZ256rkz 0U, // VPBROADCASTBrZr 292U, // VPBROADCASTBrZrk 100U, // VPBROADCASTBrZrkz 0U, // VPBROADCASTBrm 0U, // VPBROADCASTBrr 0U, // VPBROADCASTDYrm 0U, // VPBROADCASTDYrr 0U, // VPBROADCASTDZ128m 964U, // VPBROADCASTDZ128mk 68U, // VPBROADCASTDZ128mkz 0U, // VPBROADCASTDZ128r 292U, // VPBROADCASTDZ128rk 100U, // VPBROADCASTDZ128rkz 0U, // VPBROADCASTDZ256m 964U, // VPBROADCASTDZ256mk 68U, // VPBROADCASTDZ256mkz 0U, // VPBROADCASTDZ256r 292U, // VPBROADCASTDZ256rk 100U, // VPBROADCASTDZ256rkz 0U, // VPBROADCASTDZm 964U, // VPBROADCASTDZmk 68U, // VPBROADCASTDZmkz 0U, // VPBROADCASTDZr 292U, // VPBROADCASTDZrk 100U, // VPBROADCASTDZrkz 0U, // VPBROADCASTDrZ128r 292U, // VPBROADCASTDrZ128rk 100U, // VPBROADCASTDrZ128rkz 0U, // VPBROADCASTDrZ256r 292U, // VPBROADCASTDrZ256rk 100U, // VPBROADCASTDrZ256rkz 0U, // VPBROADCASTDrZr 292U, // VPBROADCASTDrZrk 100U, // VPBROADCASTDrZrkz 0U, // VPBROADCASTDrm 0U, // VPBROADCASTDrr 0U, // VPBROADCASTMB2QZ128rr 0U, // VPBROADCASTMB2QZ256rr 0U, // VPBROADCASTMB2QZrr 0U, // VPBROADCASTMW2DZ128rr 0U, // VPBROADCASTMW2DZ256rr 0U, // VPBROADCASTMW2DZrr 0U, // VPBROADCASTQYrm 0U, // VPBROADCASTQYrr 0U, // VPBROADCASTQZ128m 644U, // VPBROADCASTQZ128mk 132U, // VPBROADCASTQZ128mkz 0U, // VPBROADCASTQZ128r 292U, // VPBROADCASTQZ128rk 100U, // VPBROADCASTQZ128rkz 0U, // VPBROADCASTQZ256m 644U, // VPBROADCASTQZ256mk 132U, // VPBROADCASTQZ256mkz 0U, // VPBROADCASTQZ256r 292U, // VPBROADCASTQZ256rk 100U, // VPBROADCASTQZ256rkz 0U, // VPBROADCASTQZm 644U, // VPBROADCASTQZmk 132U, // VPBROADCASTQZmkz 0U, // VPBROADCASTQZr 292U, // VPBROADCASTQZrk 100U, // VPBROADCASTQZrkz 0U, // VPBROADCASTQrZ128r 292U, // VPBROADCASTQrZ128rk 100U, // VPBROADCASTQrZ128rkz 0U, // VPBROADCASTQrZ256r 292U, // VPBROADCASTQrZ256rk 100U, // VPBROADCASTQrZ256rkz 0U, // VPBROADCASTQrZr 292U, // VPBROADCASTQrZrk 100U, // VPBROADCASTQrZrkz 0U, // VPBROADCASTQrm 0U, // VPBROADCASTQrr 0U, // VPBROADCASTWYrm 0U, // VPBROADCASTWYrr 0U, // VPBROADCASTWZ128m 1188U, // VPBROADCASTWZ128mk 1220U, // VPBROADCASTWZ128mkz 0U, // VPBROADCASTWZ128r 292U, // VPBROADCASTWZ128rk 100U, // VPBROADCASTWZ128rkz 0U, // VPBROADCASTWZ256m 1188U, // VPBROADCASTWZ256mk 1220U, // VPBROADCASTWZ256mkz 0U, // VPBROADCASTWZ256r 292U, // VPBROADCASTWZ256rk 100U, // VPBROADCASTWZ256rkz 0U, // VPBROADCASTWZm 1188U, // VPBROADCASTWZmk 1220U, // VPBROADCASTWZmkz 0U, // VPBROADCASTWZr 292U, // VPBROADCASTWZrk 100U, // VPBROADCASTWZrkz 0U, // VPBROADCASTWrZ128r 292U, // VPBROADCASTWrZ128rk 100U, // VPBROADCASTWrZ128rkz 0U, // VPBROADCASTWrZ256r 292U, // VPBROADCASTWrZ256rk 100U, // VPBROADCASTWrZ256rkz 0U, // VPBROADCASTWrZr 292U, // VPBROADCASTWrZrk 100U, // VPBROADCASTWrZrkz 0U, // VPBROADCASTWrm 0U, // VPBROADCASTWrr 461280U, // VPCLMULQDQYrm 624736U, // VPCLMULQDQYrr 461312U, // VPCLMULQDQZ128rm 624736U, // VPCLMULQDQZ128rr 461280U, // VPCLMULQDQZ256rm 624736U, // VPCLMULQDQZ256rr 461344U, // VPCLMULQDQZrm 624736U, // VPCLMULQDQZrr 461312U, // VPCLMULQDQrm 624736U, // VPCLMULQDQrr 854496U, // VPCMOVYrmr 690272U, // VPCMOVYrrm 198752U, // VPCMOVYrrr 198752U, // VPCMOVYrrr_REV 854528U, // VPCMOVrmr 591968U, // VPCMOVrrm 198752U, // VPCMOVrrr 198752U, // VPCMOVrrr_REV 517U, // VPCMPBZ128rmi 461312U, // VPCMPBZ128rmi_alt 15U, // VPCMPBZ128rmik 55117924U, // VPCMPBZ128rmik_alt 101U, // VPCMPBZ128rri 624736U, // VPCMPBZ128rri_alt 806U, // VPCMPBZ128rrik 88279140U, // VPCMPBZ128rrik_alt 485U, // VPCMPBZ256rmi 461280U, // VPCMPBZ256rmi_alt 16U, // VPCMPBZ256rmik 55216228U, // VPCMPBZ256rmik_alt 101U, // VPCMPBZ256rri 624736U, // VPCMPBZ256rri_alt 806U, // VPCMPBZ256rrik 88279140U, // VPCMPBZ256rrik_alt 549U, // VPCMPBZrmi 461344U, // VPCMPBZrmi_alt 16U, // VPCMPBZrmik 55281764U, // VPCMPBZrmik_alt 101U, // VPCMPBZrri 624736U, // VPCMPBZrri_alt 806U, // VPCMPBZrrik 88279140U, // VPCMPBZrrik_alt 517U, // VPCMPDZ128rmi 461312U, // VPCMPDZ128rmi_alt 6213U, // VPCMPDZ128rmib 471104U, // VPCMPDZ128rmib_alt 849U, // VPCMPDZ128rmibk 57149540U, // VPCMPDZ128rmibk_alt 15U, // VPCMPDZ128rmik 55117924U, // VPCMPDZ128rmik_alt 101U, // VPCMPDZ128rri 624736U, // VPCMPDZ128rri_alt 806U, // VPCMPDZ128rrik 88279140U, // VPCMPDZ128rrik_alt 485U, // VPCMPDZ256rmi 461280U, // VPCMPDZ256rmi_alt 8261U, // VPCMPDZ256rmib 473152U, // VPCMPDZ256rmib_alt 881U, // VPCMPDZ256rmibk 58198116U, // VPCMPDZ256rmibk_alt 16U, // VPCMPDZ256rmik 55216228U, // VPCMPDZ256rmik_alt 101U, // VPCMPDZ256rri 624736U, // VPCMPDZ256rri_alt 806U, // VPCMPDZ256rrik 88279140U, // VPCMPDZ256rrik_alt 549U, // VPCMPDZrmi 461344U, // VPCMPDZrmi_alt 10309U, // VPCMPDZrmib 475200U, // VPCMPDZrmib_alt 945U, // VPCMPDZrmibk 59246692U, // VPCMPDZrmibk_alt 16U, // VPCMPDZrmik 55281764U, // VPCMPDZrmik_alt 101U, // VPCMPDZrri 624736U, // VPCMPDZrri_alt 806U, // VPCMPDZrrik 88279140U, // VPCMPDZrrik_alt 480U, // VPCMPEQBYrm 96U, // VPCMPEQBYrr 512U, // VPCMPEQBZ128rm 591972U, // VPCMPEQBZ128rmk 96U, // VPCMPEQBZ128rr 198756U, // VPCMPEQBZ128rrk 480U, // VPCMPEQBZ256rm 690276U, // VPCMPEQBZ256rmk 96U, // VPCMPEQBZ256rr 198756U, // VPCMPEQBZ256rrk 544U, // VPCMPEQBZrm 755812U, // VPCMPEQBZrmk 96U, // VPCMPEQBZrr 198756U, // VPCMPEQBZrrk 512U, // VPCMPEQBrm 96U, // VPCMPEQBrr 480U, // VPCMPEQDYrm 96U, // VPCMPEQDYrr 512U, // VPCMPEQDZ128rm 6208U, // VPCMPEQDZ128rmb 2623588U, // VPCMPEQDZ128rmbk 591972U, // VPCMPEQDZ128rmk 96U, // VPCMPEQDZ128rr 198756U, // VPCMPEQDZ128rrk 480U, // VPCMPEQDZ256rm 8256U, // VPCMPEQDZ256rmb 3672164U, // VPCMPEQDZ256rmbk 690276U, // VPCMPEQDZ256rmk 96U, // VPCMPEQDZ256rr 198756U, // VPCMPEQDZ256rrk 544U, // VPCMPEQDZrm 10304U, // VPCMPEQDZrmb 5769316U, // VPCMPEQDZrmbk 755812U, // VPCMPEQDZrmk 96U, // VPCMPEQDZrr 198756U, // VPCMPEQDZrrk 512U, // VPCMPEQDrm 96U, // VPCMPEQDrr 480U, // VPCMPEQQYrm 96U, // VPCMPEQQYrr 512U, // VPCMPEQQZ128rm 4224U, // VPCMPEQQZ128rmb 1869924U, // VPCMPEQQZ128rmbk 591972U, // VPCMPEQQZ128rmk 96U, // VPCMPEQQZ128rr 198756U, // VPCMPEQQZ128rrk 480U, // VPCMPEQQZ256rm 6272U, // VPCMPEQQZ256rmb 2918500U, // VPCMPEQQZ256rmbk 690276U, // VPCMPEQQZ256rmk 96U, // VPCMPEQQZ256rr 198756U, // VPCMPEQQZ256rrk 544U, // VPCMPEQQZrm 8320U, // VPCMPEQQZrmb 3967076U, // VPCMPEQQZrmbk 755812U, // VPCMPEQQZrmk 96U, // VPCMPEQQZrr 198756U, // VPCMPEQQZrrk 512U, // VPCMPEQQrm 96U, // VPCMPEQQrr 480U, // VPCMPEQWYrm 96U, // VPCMPEQWYrr 512U, // VPCMPEQWZ128rm 591972U, // VPCMPEQWZ128rmk 96U, // VPCMPEQWZ128rr 198756U, // VPCMPEQWZ128rrk 480U, // VPCMPEQWZ256rm 690276U, // VPCMPEQWZ256rmk 96U, // VPCMPEQWZ256rr 198756U, // VPCMPEQWZ256rrk 544U, // VPCMPEQWZrm 755812U, // VPCMPEQWZrmk 96U, // VPCMPEQWZrr 198756U, // VPCMPEQWZrrk 512U, // VPCMPEQWrm 96U, // VPCMPEQWrr 0U, // VPCMPESTRIrm 32U, // VPCMPESTRIrr 0U, // VPCMPESTRMrm 32U, // VPCMPESTRMrr 480U, // VPCMPGTBYrm 96U, // VPCMPGTBYrr 512U, // VPCMPGTBZ128rm 591972U, // VPCMPGTBZ128rmk 96U, // VPCMPGTBZ128rr 198756U, // VPCMPGTBZ128rrk 480U, // VPCMPGTBZ256rm 690276U, // VPCMPGTBZ256rmk 96U, // VPCMPGTBZ256rr 198756U, // VPCMPGTBZ256rrk 544U, // VPCMPGTBZrm 755812U, // VPCMPGTBZrmk 96U, // VPCMPGTBZrr 198756U, // VPCMPGTBZrrk 512U, // VPCMPGTBrm 96U, // VPCMPGTBrr 480U, // VPCMPGTDYrm 96U, // VPCMPGTDYrr 512U, // VPCMPGTDZ128rm 6208U, // VPCMPGTDZ128rmb 2623588U, // VPCMPGTDZ128rmbk 591972U, // VPCMPGTDZ128rmk 96U, // VPCMPGTDZ128rr 198756U, // VPCMPGTDZ128rrk 480U, // VPCMPGTDZ256rm 8256U, // VPCMPGTDZ256rmb 3672164U, // VPCMPGTDZ256rmbk 690276U, // VPCMPGTDZ256rmk 96U, // VPCMPGTDZ256rr 198756U, // VPCMPGTDZ256rrk 544U, // VPCMPGTDZrm 10304U, // VPCMPGTDZrmb 5769316U, // VPCMPGTDZrmbk 755812U, // VPCMPGTDZrmk 96U, // VPCMPGTDZrr 198756U, // VPCMPGTDZrrk 512U, // VPCMPGTDrm 96U, // VPCMPGTDrr 480U, // VPCMPGTQYrm 96U, // VPCMPGTQYrr 512U, // VPCMPGTQZ128rm 4224U, // VPCMPGTQZ128rmb 1869924U, // VPCMPGTQZ128rmbk 591972U, // VPCMPGTQZ128rmk 96U, // VPCMPGTQZ128rr 198756U, // VPCMPGTQZ128rrk 480U, // VPCMPGTQZ256rm 6272U, // VPCMPGTQZ256rmb 2918500U, // VPCMPGTQZ256rmbk 690276U, // VPCMPGTQZ256rmk 96U, // VPCMPGTQZ256rr 198756U, // VPCMPGTQZ256rrk 544U, // VPCMPGTQZrm 8320U, // VPCMPGTQZrmb 3967076U, // VPCMPGTQZrmbk 755812U, // VPCMPGTQZrmk 96U, // VPCMPGTQZrr 198756U, // VPCMPGTQZrrk 512U, // VPCMPGTQrm 96U, // VPCMPGTQrr 480U, // VPCMPGTWYrm 96U, // VPCMPGTWYrr 512U, // VPCMPGTWZ128rm 591972U, // VPCMPGTWZ128rmk 96U, // VPCMPGTWZ128rr 198756U, // VPCMPGTWZ128rrk 480U, // VPCMPGTWZ256rm 690276U, // VPCMPGTWZ256rmk 96U, // VPCMPGTWZ256rr 198756U, // VPCMPGTWZ256rrk 544U, // VPCMPGTWZrm 755812U, // VPCMPGTWZrmk 96U, // VPCMPGTWZrr 198756U, // VPCMPGTWZrrk 512U, // VPCMPGTWrm 96U, // VPCMPGTWrr 0U, // VPCMPISTRIrm 32U, // VPCMPISTRIrr 0U, // VPCMPISTRMrm 32U, // VPCMPISTRMrr 517U, // VPCMPQZ128rmi 461312U, // VPCMPQZ128rmi_alt 4229U, // VPCMPQZ128rmib 477312U, // VPCMPQZ128rmib_alt 785U, // VPCMPQZ128rmibk 60590180U, // VPCMPQZ128rmibk_alt 15U, // VPCMPQZ128rmik 55117924U, // VPCMPQZ128rmik_alt 101U, // VPCMPQZ128rri 624736U, // VPCMPQZ128rri_alt 806U, // VPCMPQZ128rrik 88279140U, // VPCMPQZ128rrik_alt 485U, // VPCMPQZ256rmi 461280U, // VPCMPQZ256rmi_alt 6277U, // VPCMPQZ256rmib 471168U, // VPCMPQZ256rmib_alt 849U, // VPCMPQZ256rmibk 57444452U, // VPCMPQZ256rmibk_alt 16U, // VPCMPQZ256rmik 55216228U, // VPCMPQZ256rmik_alt 101U, // VPCMPQZ256rri 624736U, // VPCMPQZ256rri_alt 806U, // VPCMPQZ256rrik 88279140U, // VPCMPQZ256rrik_alt 549U, // VPCMPQZrmi 461344U, // VPCMPQZrmi_alt 8325U, // VPCMPQZrmib 473216U, // VPCMPQZrmib_alt 881U, // VPCMPQZrmibk 58493028U, // VPCMPQZrmibk_alt 16U, // VPCMPQZrmik 55281764U, // VPCMPQZrmik_alt 101U, // VPCMPQZrri 624736U, // VPCMPQZrri_alt 806U, // VPCMPQZrrik 88279140U, // VPCMPQZrrik_alt 517U, // VPCMPUBZ128rmi 461312U, // VPCMPUBZ128rmi_alt 15U, // VPCMPUBZ128rmik 55117924U, // VPCMPUBZ128rmik_alt 101U, // VPCMPUBZ128rri 624736U, // VPCMPUBZ128rri_alt 806U, // VPCMPUBZ128rrik 88279140U, // VPCMPUBZ128rrik_alt 485U, // VPCMPUBZ256rmi 461280U, // VPCMPUBZ256rmi_alt 16U, // VPCMPUBZ256rmik 55216228U, // VPCMPUBZ256rmik_alt 101U, // VPCMPUBZ256rri 624736U, // VPCMPUBZ256rri_alt 806U, // VPCMPUBZ256rrik 88279140U, // VPCMPUBZ256rrik_alt 549U, // VPCMPUBZrmi 461344U, // VPCMPUBZrmi_alt 16U, // VPCMPUBZrmik 55281764U, // VPCMPUBZrmik_alt 101U, // VPCMPUBZrri 624736U, // VPCMPUBZrri_alt 806U, // VPCMPUBZrrik 88279140U, // VPCMPUBZrrik_alt 517U, // VPCMPUDZ128rmi 461312U, // VPCMPUDZ128rmi_alt 6213U, // VPCMPUDZ128rmib 471104U, // VPCMPUDZ128rmib_alt 849U, // VPCMPUDZ128rmibk 57149540U, // VPCMPUDZ128rmibk_alt 15U, // VPCMPUDZ128rmik 55117924U, // VPCMPUDZ128rmik_alt 101U, // VPCMPUDZ128rri 624736U, // VPCMPUDZ128rri_alt 806U, // VPCMPUDZ128rrik 88279140U, // VPCMPUDZ128rrik_alt 485U, // VPCMPUDZ256rmi 461280U, // VPCMPUDZ256rmi_alt 8261U, // VPCMPUDZ256rmib 473152U, // VPCMPUDZ256rmib_alt 881U, // VPCMPUDZ256rmibk 58198116U, // VPCMPUDZ256rmibk_alt 16U, // VPCMPUDZ256rmik 55216228U, // VPCMPUDZ256rmik_alt 101U, // VPCMPUDZ256rri 624736U, // VPCMPUDZ256rri_alt 806U, // VPCMPUDZ256rrik 88279140U, // VPCMPUDZ256rrik_alt 549U, // VPCMPUDZrmi 461344U, // VPCMPUDZrmi_alt 10309U, // VPCMPUDZrmib 475200U, // VPCMPUDZrmib_alt 945U, // VPCMPUDZrmibk 59246692U, // VPCMPUDZrmibk_alt 16U, // VPCMPUDZrmik 55281764U, // VPCMPUDZrmik_alt 101U, // VPCMPUDZrri 624736U, // VPCMPUDZrri_alt 806U, // VPCMPUDZrrik 88279140U, // VPCMPUDZrrik_alt 517U, // VPCMPUQZ128rmi 461312U, // VPCMPUQZ128rmi_alt 4229U, // VPCMPUQZ128rmib 477312U, // VPCMPUQZ128rmib_alt 785U, // VPCMPUQZ128rmibk 60590180U, // VPCMPUQZ128rmibk_alt 15U, // VPCMPUQZ128rmik 55117924U, // VPCMPUQZ128rmik_alt 101U, // VPCMPUQZ128rri 624736U, // VPCMPUQZ128rri_alt 806U, // VPCMPUQZ128rrik 88279140U, // VPCMPUQZ128rrik_alt 485U, // VPCMPUQZ256rmi 461280U, // VPCMPUQZ256rmi_alt 6277U, // VPCMPUQZ256rmib 471168U, // VPCMPUQZ256rmib_alt 849U, // VPCMPUQZ256rmibk 57444452U, // VPCMPUQZ256rmibk_alt 16U, // VPCMPUQZ256rmik 55216228U, // VPCMPUQZ256rmik_alt 101U, // VPCMPUQZ256rri 624736U, // VPCMPUQZ256rri_alt 806U, // VPCMPUQZ256rrik 88279140U, // VPCMPUQZ256rrik_alt 549U, // VPCMPUQZrmi 461344U, // VPCMPUQZrmi_alt 8325U, // VPCMPUQZrmib 473216U, // VPCMPUQZrmib_alt 881U, // VPCMPUQZrmibk 58493028U, // VPCMPUQZrmibk_alt 16U, // VPCMPUQZrmik 55281764U, // VPCMPUQZrmik_alt 101U, // VPCMPUQZrri 624736U, // VPCMPUQZrri_alt 806U, // VPCMPUQZrrik 88279140U, // VPCMPUQZrrik_alt 517U, // VPCMPUWZ128rmi 461312U, // VPCMPUWZ128rmi_alt 15U, // VPCMPUWZ128rmik 55117924U, // VPCMPUWZ128rmik_alt 101U, // VPCMPUWZ128rri 624736U, // VPCMPUWZ128rri_alt 806U, // VPCMPUWZ128rrik 88279140U, // VPCMPUWZ128rrik_alt 485U, // VPCMPUWZ256rmi 461280U, // VPCMPUWZ256rmi_alt 16U, // VPCMPUWZ256rmik 55216228U, // VPCMPUWZ256rmik_alt 101U, // VPCMPUWZ256rri 624736U, // VPCMPUWZ256rri_alt 806U, // VPCMPUWZ256rrik 88279140U, // VPCMPUWZ256rrik_alt 549U, // VPCMPUWZrmi 461344U, // VPCMPUWZrmi_alt 16U, // VPCMPUWZrmik 55281764U, // VPCMPUWZrmik_alt 101U, // VPCMPUWZrri 624736U, // VPCMPUWZrri_alt 806U, // VPCMPUWZrrik 88279140U, // VPCMPUWZrrik_alt 517U, // VPCMPWZ128rmi 461312U, // VPCMPWZ128rmi_alt 15U, // VPCMPWZ128rmik 55117924U, // VPCMPWZ128rmik_alt 101U, // VPCMPWZ128rri 624736U, // VPCMPWZ128rri_alt 806U, // VPCMPWZ128rrik 88279140U, // VPCMPWZ128rrik_alt 485U, // VPCMPWZ256rmi 461280U, // VPCMPWZ256rmi_alt 16U, // VPCMPWZ256rmik 55216228U, // VPCMPWZ256rmik_alt 101U, // VPCMPWZ256rri 624736U, // VPCMPWZ256rri_alt 806U, // VPCMPWZ256rrik 88279140U, // VPCMPWZ256rrik_alt 549U, // VPCMPWZrmi 461344U, // VPCMPWZrmi_alt 16U, // VPCMPWZrmik 55281764U, // VPCMPWZrmik_alt 101U, // VPCMPWZrri 624736U, // VPCMPWZrri_alt 806U, // VPCMPWZrrik 88279140U, // VPCMPWZrrik_alt 517U, // VPCOMBmi 461312U, // VPCOMBmi_alt 101U, // VPCOMBri 624736U, // VPCOMBri_alt 517U, // VPCOMDmi 461312U, // VPCOMDmi_alt 101U, // VPCOMDri 624736U, // VPCOMDri_alt 0U, // VPCOMPRESSBZ128mr 164U, // VPCOMPRESSBZ128mrk 0U, // VPCOMPRESSBZ128rr 292U, // VPCOMPRESSBZ128rrk 100U, // VPCOMPRESSBZ128rrkz 0U, // VPCOMPRESSBZ256mr 164U, // VPCOMPRESSBZ256mrk 0U, // VPCOMPRESSBZ256rr 292U, // VPCOMPRESSBZ256rrk 100U, // VPCOMPRESSBZ256rrkz 0U, // VPCOMPRESSBZmr 164U, // VPCOMPRESSBZmrk 0U, // VPCOMPRESSBZrr 292U, // VPCOMPRESSBZrrk 100U, // VPCOMPRESSBZrrkz 0U, // VPCOMPRESSDZ128mr 164U, // VPCOMPRESSDZ128mrk 0U, // VPCOMPRESSDZ128rr 292U, // VPCOMPRESSDZ128rrk 100U, // VPCOMPRESSDZ128rrkz 0U, // VPCOMPRESSDZ256mr 164U, // VPCOMPRESSDZ256mrk 0U, // VPCOMPRESSDZ256rr 292U, // VPCOMPRESSDZ256rrk 100U, // VPCOMPRESSDZ256rrkz 0U, // VPCOMPRESSDZmr 164U, // VPCOMPRESSDZmrk 0U, // VPCOMPRESSDZrr 292U, // VPCOMPRESSDZrrk 100U, // VPCOMPRESSDZrrkz 0U, // VPCOMPRESSQZ128mr 164U, // VPCOMPRESSQZ128mrk 0U, // VPCOMPRESSQZ128rr 292U, // VPCOMPRESSQZ128rrk 100U, // VPCOMPRESSQZ128rrkz 0U, // VPCOMPRESSQZ256mr 164U, // VPCOMPRESSQZ256mrk 0U, // VPCOMPRESSQZ256rr 292U, // VPCOMPRESSQZ256rrk 100U, // VPCOMPRESSQZ256rrkz 0U, // VPCOMPRESSQZmr 164U, // VPCOMPRESSQZmrk 0U, // VPCOMPRESSQZrr 292U, // VPCOMPRESSQZrrk 100U, // VPCOMPRESSQZrrkz 0U, // VPCOMPRESSWZ128mr 164U, // VPCOMPRESSWZ128mrk 0U, // VPCOMPRESSWZ128rr 292U, // VPCOMPRESSWZ128rrk 100U, // VPCOMPRESSWZ128rrkz 0U, // VPCOMPRESSWZ256mr 164U, // VPCOMPRESSWZ256mrk 0U, // VPCOMPRESSWZ256rr 292U, // VPCOMPRESSWZ256rrk 100U, // VPCOMPRESSWZ256rrkz 0U, // VPCOMPRESSWZmr 164U, // VPCOMPRESSWZmrk 0U, // VPCOMPRESSWZrr 292U, // VPCOMPRESSWZrrk 100U, // VPCOMPRESSWZrrkz 517U, // VPCOMQmi 461312U, // VPCOMQmi_alt 101U, // VPCOMQri 624736U, // VPCOMQri_alt 517U, // VPCOMUBmi 461312U, // VPCOMUBmi_alt 101U, // VPCOMUBri 624736U, // VPCOMUBri_alt 517U, // VPCOMUDmi 461312U, // VPCOMUDmi_alt 101U, // VPCOMUDri 624736U, // VPCOMUDri_alt 517U, // VPCOMUQmi 461312U, // VPCOMUQmi_alt 101U, // VPCOMUQri 624736U, // VPCOMUQri_alt 517U, // VPCOMUWmi 461312U, // VPCOMUWmi_alt 101U, // VPCOMUWri 624736U, // VPCOMUWri_alt 517U, // VPCOMWmi 461312U, // VPCOMWmi_alt 101U, // VPCOMWri 624736U, // VPCOMWri_alt 0U, // VPCONFLICTDZ128rm 9U, // VPCONFLICTDZ128rmb 7108U, // VPCONFLICTDZ128rmbk 6212U, // VPCONFLICTDZ128rmbkz 676U, // VPCONFLICTDZ128rmk 516U, // VPCONFLICTDZ128rmkz 0U, // VPCONFLICTDZ128rr 292U, // VPCONFLICTDZ128rrk 100U, // VPCONFLICTDZ128rrkz 0U, // VPCONFLICTDZ256rm 10U, // VPCONFLICTDZ256rmb 9156U, // VPCONFLICTDZ256rmbk 8260U, // VPCONFLICTDZ256rmbkz 708U, // VPCONFLICTDZ256rmk 484U, // VPCONFLICTDZ256rmkz 0U, // VPCONFLICTDZ256rr 292U, // VPCONFLICTDZ256rrk 100U, // VPCONFLICTDZ256rrkz 0U, // VPCONFLICTDZrm 10U, // VPCONFLICTDZrmb 11204U, // VPCONFLICTDZrmbk 10308U, // VPCONFLICTDZrmbkz 996U, // VPCONFLICTDZrmk 548U, // VPCONFLICTDZrmkz 0U, // VPCONFLICTDZrr 292U, // VPCONFLICTDZrrk 100U, // VPCONFLICTDZrrkz 0U, // VPCONFLICTQZ128rm 9U, // VPCONFLICTQZ128rmb 4740U, // VPCONFLICTQZ128rmbk 4228U, // VPCONFLICTQZ128rmbkz 676U, // VPCONFLICTQZ128rmk 516U, // VPCONFLICTQZ128rmkz 0U, // VPCONFLICTQZ128rr 292U, // VPCONFLICTQZ128rrk 100U, // VPCONFLICTQZ128rrkz 0U, // VPCONFLICTQZ256rm 9U, // VPCONFLICTQZ256rmb 6788U, // VPCONFLICTQZ256rmbk 6276U, // VPCONFLICTQZ256rmbkz 708U, // VPCONFLICTQZ256rmk 484U, // VPCONFLICTQZ256rmkz 0U, // VPCONFLICTQZ256rr 292U, // VPCONFLICTQZ256rrk 100U, // VPCONFLICTQZ256rrkz 0U, // VPCONFLICTQZrm 10U, // VPCONFLICTQZrmb 8836U, // VPCONFLICTQZrmbk 8324U, // VPCONFLICTQZrmbkz 996U, // VPCONFLICTQZrmk 548U, // VPCONFLICTQZrmkz 0U, // VPCONFLICTQZrr 292U, // VPCONFLICTQZrrk 100U, // VPCONFLICTQZrrkz 672U, // VPDPBUSDSZ128m 7104U, // VPDPBUSDSZ128mb 2591012U, // VPDPBUSDSZ128mbk 2591012U, // VPDPBUSDSZ128mbkz 559396U, // VPDPBUSDSZ128mk 559396U, // VPDPBUSDSZ128mkz 288U, // VPDPBUSDSZ128r 166180U, // VPDPBUSDSZ128rk 166180U, // VPDPBUSDSZ128rkz 704U, // VPDPBUSDSZ256m 9152U, // VPDPBUSDSZ256mb 3639588U, // VPDPBUSDSZ256mbk 3639588U, // VPDPBUSDSZ256mbkz 657700U, // VPDPBUSDSZ256mk 657700U, // VPDPBUSDSZ256mkz 288U, // VPDPBUSDSZ256r 166180U, // VPDPBUSDSZ256rk 166180U, // VPDPBUSDSZ256rkz 992U, // VPDPBUSDSZm 11200U, // VPDPBUSDSZmb 5736740U, // VPDPBUSDSZmbk 5736740U, // VPDPBUSDSZmbkz 723236U, // VPDPBUSDSZmk 723236U, // VPDPBUSDSZmkz 288U, // VPDPBUSDSZr 166180U, // VPDPBUSDSZrk 166180U, // VPDPBUSDSZrkz 672U, // VPDPBUSDZ128m 7104U, // VPDPBUSDZ128mb 2591012U, // VPDPBUSDZ128mbk 2591012U, // VPDPBUSDZ128mbkz 559396U, // VPDPBUSDZ128mk 559396U, // VPDPBUSDZ128mkz 288U, // VPDPBUSDZ128r 166180U, // VPDPBUSDZ128rk 166180U, // VPDPBUSDZ128rkz 704U, // VPDPBUSDZ256m 9152U, // VPDPBUSDZ256mb 3639588U, // VPDPBUSDZ256mbk 3639588U, // VPDPBUSDZ256mbkz 657700U, // VPDPBUSDZ256mk 657700U, // VPDPBUSDZ256mkz 288U, // VPDPBUSDZ256r 166180U, // VPDPBUSDZ256rk 166180U, // VPDPBUSDZ256rkz 992U, // VPDPBUSDZm 11200U, // VPDPBUSDZmb 5736740U, // VPDPBUSDZmbk 5736740U, // VPDPBUSDZmbkz 723236U, // VPDPBUSDZmk 723236U, // VPDPBUSDZmkz 288U, // VPDPBUSDZr 166180U, // VPDPBUSDZrk 166180U, // VPDPBUSDZrkz 672U, // VPDPWSSDSZ128m 7104U, // VPDPWSSDSZ128mb 2591012U, // VPDPWSSDSZ128mbk 2591012U, // VPDPWSSDSZ128mbkz 559396U, // VPDPWSSDSZ128mk 559396U, // VPDPWSSDSZ128mkz 288U, // VPDPWSSDSZ128r 166180U, // VPDPWSSDSZ128rk 166180U, // VPDPWSSDSZ128rkz 704U, // VPDPWSSDSZ256m 9152U, // VPDPWSSDSZ256mb 3639588U, // VPDPWSSDSZ256mbk 3639588U, // VPDPWSSDSZ256mbkz 657700U, // VPDPWSSDSZ256mk 657700U, // VPDPWSSDSZ256mkz 288U, // VPDPWSSDSZ256r 166180U, // VPDPWSSDSZ256rk 166180U, // VPDPWSSDSZ256rkz 992U, // VPDPWSSDSZm 11200U, // VPDPWSSDSZmb 5736740U, // VPDPWSSDSZmbk 5736740U, // VPDPWSSDSZmbkz 723236U, // VPDPWSSDSZmk 723236U, // VPDPWSSDSZmkz 288U, // VPDPWSSDSZr 166180U, // VPDPWSSDSZrk 166180U, // VPDPWSSDSZrkz 672U, // VPDPWSSDZ128m 7104U, // VPDPWSSDZ128mb 2591012U, // VPDPWSSDZ128mbk 2591012U, // VPDPWSSDZ128mbkz 559396U, // VPDPWSSDZ128mk 559396U, // VPDPWSSDZ128mkz 288U, // VPDPWSSDZ128r 166180U, // VPDPWSSDZ128rk 166180U, // VPDPWSSDZ128rkz 704U, // VPDPWSSDZ256m 9152U, // VPDPWSSDZ256mb 3639588U, // VPDPWSSDZ256mbk 3639588U, // VPDPWSSDZ256mbkz 657700U, // VPDPWSSDZ256mk 657700U, // VPDPWSSDZ256mkz 288U, // VPDPWSSDZ256r 166180U, // VPDPWSSDZ256rk 166180U, // VPDPWSSDZ256rkz 992U, // VPDPWSSDZm 11200U, // VPDPWSSDZmb 5736740U, // VPDPWSSDZmbk 5736740U, // VPDPWSSDZmbkz 723236U, // VPDPWSSDZmk 723236U, // VPDPWSSDZmkz 288U, // VPDPWSSDZr 166180U, // VPDPWSSDZrk 166180U, // VPDPWSSDZrkz 461120U, // VPERM2F128rm 624736U, // VPERM2F128rr 461120U, // VPERM2I128rm 624736U, // VPERM2I128rr 512U, // VPERMBZ128rm 559396U, // VPERMBZ128rmk 591972U, // VPERMBZ128rmkz 96U, // VPERMBZ128rr 166180U, // VPERMBZ128rrk 198756U, // VPERMBZ128rrkz 480U, // VPERMBZ256rm 657700U, // VPERMBZ256rmk 690276U, // VPERMBZ256rmkz 96U, // VPERMBZ256rr 166180U, // VPERMBZ256rrk 198756U, // VPERMBZ256rrkz 544U, // VPERMBZrm 723236U, // VPERMBZrmk 755812U, // VPERMBZrmkz 96U, // VPERMBZrr 166180U, // VPERMBZrrk 198756U, // VPERMBZrrkz 480U, // VPERMDYrm 96U, // VPERMDYrr 480U, // VPERMDZ256rm 8256U, // VPERMDZ256rmb 3639588U, // VPERMDZ256rmbk 3672164U, // VPERMDZ256rmbkz 657700U, // VPERMDZ256rmk 690276U, // VPERMDZ256rmkz 96U, // VPERMDZ256rr 166180U, // VPERMDZ256rrk 198756U, // VPERMDZ256rrkz 544U, // VPERMDZrm 10304U, // VPERMDZrmb 5736740U, // VPERMDZrmbk 5769316U, // VPERMDZrmbkz 723236U, // VPERMDZrmk 755812U, // VPERMDZrmkz 96U, // VPERMDZrr 166180U, // VPERMDZrrk 198756U, // VPERMDZrrkz 672U, // VPERMI2B128rm 559396U, // VPERMI2B128rmk 559396U, // VPERMI2B128rmkz 288U, // VPERMI2B128rr 166180U, // VPERMI2B128rrk 166180U, // VPERMI2B128rrkz 704U, // VPERMI2B256rm 657700U, // VPERMI2B256rmk 657700U, // VPERMI2B256rmkz 288U, // VPERMI2B256rr 166180U, // VPERMI2B256rrk 166180U, // VPERMI2B256rrkz 992U, // VPERMI2Brm 723236U, // VPERMI2Brmk 723236U, // VPERMI2Brmkz 288U, // VPERMI2Brr 166180U, // VPERMI2Brrk 166180U, // VPERMI2Brrkz 672U, // VPERMI2D128rm 7104U, // VPERMI2D128rmb 2591012U, // VPERMI2D128rmbk 2591012U, // VPERMI2D128rmbkz 559396U, // VPERMI2D128rmk 559396U, // VPERMI2D128rmkz 288U, // VPERMI2D128rr 166180U, // VPERMI2D128rrk 166180U, // VPERMI2D128rrkz 704U, // VPERMI2D256rm 9152U, // VPERMI2D256rmb 3639588U, // VPERMI2D256rmbk 3639588U, // VPERMI2D256rmbkz 657700U, // VPERMI2D256rmk 657700U, // VPERMI2D256rmkz 288U, // VPERMI2D256rr 166180U, // VPERMI2D256rrk 166180U, // VPERMI2D256rrkz 992U, // VPERMI2Drm 11200U, // VPERMI2Drmb 5736740U, // VPERMI2Drmbk 5736740U, // VPERMI2Drmbkz 723236U, // VPERMI2Drmk 723236U, // VPERMI2Drmkz 288U, // VPERMI2Drr 166180U, // VPERMI2Drrk 166180U, // VPERMI2Drrkz 256U, // VPERMI2PD128rm 4672U, // VPERMI2PD128rmb 1116452U, // VPERMI2PD128rmbk 1116452U, // VPERMI2PD128rmbkz 35108U, // VPERMI2PD128rmk 35108U, // VPERMI2PD128rmkz 288U, // VPERMI2PD128rr 166180U, // VPERMI2PD128rrk 166180U, // VPERMI2PD128rrkz 608U, // VPERMI2PD256rm 6720U, // VPERMI2PD256rmb 2165028U, // VPERMI2PD256rmbk 2165028U, // VPERMI2PD256rmbkz 231716U, // VPERMI2PD256rmk 231716U, // VPERMI2PD256rmkz 288U, // VPERMI2PD256rr 166180U, // VPERMI2PD256rrk 166180U, // VPERMI2PD256rrkz 1056U, // VPERMI2PDrm 8768U, // VPERMI2PDrmb 3213604U, // VPERMI2PDrmbk 3213604U, // VPERMI2PDrmbkz 297252U, // VPERMI2PDrmk 297252U, // VPERMI2PDrmkz 288U, // VPERMI2PDrr 166180U, // VPERMI2PDrrk 166180U, // VPERMI2PDrrkz 256U, // VPERMI2PS128rm 6880U, // VPERMI2PS128rmb 2492708U, // VPERMI2PS128rmbk 2492708U, // VPERMI2PS128rmbkz 35108U, // VPERMI2PS128rmk 35108U, // VPERMI2PS128rmkz 288U, // VPERMI2PS128rr 166180U, // VPERMI2PS128rrk 166180U, // VPERMI2PS128rrkz 608U, // VPERMI2PS256rm 8928U, // VPERMI2PS256rmb 3541284U, // VPERMI2PS256rmbk 3541284U, // VPERMI2PS256rmbkz 231716U, // VPERMI2PS256rmk 231716U, // VPERMI2PS256rmkz 288U, // VPERMI2PS256rr 166180U, // VPERMI2PS256rrk 166180U, // VPERMI2PS256rrkz 1056U, // VPERMI2PSrm 10976U, // VPERMI2PSrmb 5638436U, // VPERMI2PSrmbk 5638436U, // VPERMI2PSrmbkz 297252U, // VPERMI2PSrmk 297252U, // VPERMI2PSrmkz 288U, // VPERMI2PSrr 166180U, // VPERMI2PSrrk 166180U, // VPERMI2PSrrkz 672U, // VPERMI2Q128rm 4736U, // VPERMI2Q128rmb 1837348U, // VPERMI2Q128rmbk 1837348U, // VPERMI2Q128rmbkz 559396U, // VPERMI2Q128rmk 559396U, // VPERMI2Q128rmkz 288U, // VPERMI2Q128rr 166180U, // VPERMI2Q128rrk 166180U, // VPERMI2Q128rrkz 704U, // VPERMI2Q256rm 6784U, // VPERMI2Q256rmb 2885924U, // VPERMI2Q256rmbk 2885924U, // VPERMI2Q256rmbkz 657700U, // VPERMI2Q256rmk 657700U, // VPERMI2Q256rmkz 288U, // VPERMI2Q256rr 166180U, // VPERMI2Q256rrk 166180U, // VPERMI2Q256rrkz 992U, // VPERMI2Qrm 8832U, // VPERMI2Qrmb 3934500U, // VPERMI2Qrmbk 3934500U, // VPERMI2Qrmbkz 723236U, // VPERMI2Qrmk 723236U, // VPERMI2Qrmkz 288U, // VPERMI2Qrr 166180U, // VPERMI2Qrrk 166180U, // VPERMI2Qrrkz 672U, // VPERMI2W128rm 559396U, // VPERMI2W128rmk 559396U, // VPERMI2W128rmkz 288U, // VPERMI2W128rr 166180U, // VPERMI2W128rrk 166180U, // VPERMI2W128rrkz 704U, // VPERMI2W256rm 657700U, // VPERMI2W256rmk 657700U, // VPERMI2W256rmkz 288U, // VPERMI2W256rr 166180U, // VPERMI2W256rrk 166180U, // VPERMI2W256rrkz 992U, // VPERMI2Wrm 723236U, // VPERMI2Wrmk 723236U, // VPERMI2Wrmkz 288U, // VPERMI2Wrr 166180U, // VPERMI2Wrrk 166180U, // VPERMI2Wrrkz 55380288U, // VPERMIL2PDYmr 55216224U, // VPERMIL2PDYrm 88279136U, // VPERMIL2PDYrr 88279136U, // VPERMIL2PDYrr_REV 55380320U, // VPERMIL2PDmr 55117920U, // VPERMIL2PDrm 88279136U, // VPERMIL2PDrr 88279136U, // VPERMIL2PDrr_REV 55380288U, // VPERMIL2PSYmr 55216224U, // VPERMIL2PSYrm 88279136U, // VPERMIL2PSYrr 88279136U, // VPERMIL2PSYrr_REV 55380320U, // VPERMIL2PSmr 55117920U, // VPERMIL2PSrm 88279136U, // VPERMIL2PSrr 88279136U, // VPERMIL2PSrr_REV 0U, // VPERMILPDYmi 32U, // VPERMILPDYri 480U, // VPERMILPDYrm 96U, // VPERMILPDYrr 11U, // VPERMILPDZ128mbi 936516U, // VPERMILPDZ128mbik 477572U, // VPERMILPDZ128mbikz 0U, // VPERMILPDZ128mi 919812U, // VPERMILPDZ128mik 461156U, // VPERMILPDZ128mikz 32U, // VPERMILPDZ128ri 2340U, // VPERMILPDZ128rik 624740U, // VPERMILPDZ128rikz 512U, // VPERMILPDZ128rm 4480U, // VPERMILPDZ128rmb 1116452U, // VPERMILPDZ128rmbk 1149028U, // VPERMILPDZ128rmbkz 559396U, // VPERMILPDZ128rmk 591972U, // VPERMILPDZ128rmkz 96U, // VPERMILPDZ128rr 166180U, // VPERMILPDZ128rrk 198756U, // VPERMILPDZ128rrkz 12U, // VPERMILPDZ256mbi 930372U, // VPERMILPDZ256mbik 471428U, // VPERMILPDZ256mbikz 0U, // VPERMILPDZ256mi 920164U, // VPERMILPDZ256mik 461124U, // VPERMILPDZ256mikz 32U, // VPERMILPDZ256ri 2340U, // VPERMILPDZ256rik 624740U, // VPERMILPDZ256rikz 480U, // VPERMILPDZ256rm 6528U, // VPERMILPDZ256rmb 2165028U, // VPERMILPDZ256rmbk 2197604U, // VPERMILPDZ256rmbkz 657700U, // VPERMILPDZ256rmk 690276U, // VPERMILPDZ256rmkz 96U, // VPERMILPDZ256rr 166180U, // VPERMILPDZ256rrk 198756U, // VPERMILPDZ256rrkz 12U, // VPERMILPDZmbi 932420U, // VPERMILPDZmbik 473476U, // VPERMILPDZmbikz 0U, // VPERMILPDZmi 920612U, // VPERMILPDZmik 461220U, // VPERMILPDZmikz 32U, // VPERMILPDZri 2340U, // VPERMILPDZrik 624740U, // VPERMILPDZrikz 544U, // VPERMILPDZrm 8576U, // VPERMILPDZrmb 3213604U, // VPERMILPDZrmbk 3246180U, // VPERMILPDZrmbkz 723236U, // VPERMILPDZrmk 755812U, // VPERMILPDZrmkz 96U, // VPERMILPDZrr 166180U, // VPERMILPDZrrk 198756U, // VPERMILPDZrrkz 0U, // VPERMILPDmi 32U, // VPERMILPDri 512U, // VPERMILPDrm 96U, // VPERMILPDrr 0U, // VPERMILPSYmi 32U, // VPERMILPSYri 480U, // VPERMILPSYrm 96U, // VPERMILPSYrr 12U, // VPERMILPSZ128mbi 930532U, // VPERMILPSZ128mbik 471492U, // VPERMILPSZ128mbikz 0U, // VPERMILPSZ128mi 919812U, // VPERMILPSZ128mik 461156U, // VPERMILPSZ128mikz 32U, // VPERMILPSZ128ri 2340U, // VPERMILPSZ128rik 624740U, // VPERMILPSZ128rikz 512U, // VPERMILPSZ128rm 6592U, // VPERMILPSZ128rmb 2492708U, // VPERMILPSZ128rmbk 2525284U, // VPERMILPSZ128rmbkz 559396U, // VPERMILPSZ128rmk 591972U, // VPERMILPSZ128rmkz 96U, // VPERMILPSZ128rr 166180U, // VPERMILPSZ128rrk 198756U, // VPERMILPSZ128rrkz 12U, // VPERMILPSZ256mbi 932580U, // VPERMILPSZ256mbik 473540U, // VPERMILPSZ256mbikz 0U, // VPERMILPSZ256mi 920164U, // VPERMILPSZ256mik 461124U, // VPERMILPSZ256mikz 32U, // VPERMILPSZ256ri 2340U, // VPERMILPSZ256rik 624740U, // VPERMILPSZ256rikz 480U, // VPERMILPSZ256rm 8640U, // VPERMILPSZ256rmb 3541284U, // VPERMILPSZ256rmbk 3573860U, // VPERMILPSZ256rmbkz 657700U, // VPERMILPSZ256rmk 690276U, // VPERMILPSZ256rmkz 96U, // VPERMILPSZ256rr 166180U, // VPERMILPSZ256rrk 198756U, // VPERMILPSZ256rrkz 13U, // VPERMILPSZmbi 934628U, // VPERMILPSZmbik 475588U, // VPERMILPSZmbikz 0U, // VPERMILPSZmi 920612U, // VPERMILPSZmik 461220U, // VPERMILPSZmikz 32U, // VPERMILPSZri 2340U, // VPERMILPSZrik 624740U, // VPERMILPSZrikz 544U, // VPERMILPSZrm 10688U, // VPERMILPSZrmb 5638436U, // VPERMILPSZrmbk 5671012U, // VPERMILPSZrmbkz 723236U, // VPERMILPSZrmk 755812U, // VPERMILPSZrmkz 96U, // VPERMILPSZrr 166180U, // VPERMILPSZrrk 198756U, // VPERMILPSZrrkz 0U, // VPERMILPSmi 32U, // VPERMILPSri 512U, // VPERMILPSrm 96U, // VPERMILPSrr 0U, // VPERMPDYmi 32U, // VPERMPDYri 12U, // VPERMPDZ256mbi 930372U, // VPERMPDZ256mbik 471428U, // VPERMPDZ256mbikz 0U, // VPERMPDZ256mi 920164U, // VPERMPDZ256mik 461124U, // VPERMPDZ256mikz 32U, // VPERMPDZ256ri 2340U, // VPERMPDZ256rik 624740U, // VPERMPDZ256rikz 320U, // VPERMPDZ256rm 6528U, // VPERMPDZ256rmb 2165028U, // VPERMPDZ256rmbk 2197604U, // VPERMPDZ256rmbkz 231716U, // VPERMPDZ256rmk 264292U, // VPERMPDZ256rmkz 96U, // VPERMPDZ256rr 166180U, // VPERMPDZ256rrk 198756U, // VPERMPDZ256rrkz 12U, // VPERMPDZmbi 932420U, // VPERMPDZmbik 473476U, // VPERMPDZmbikz 0U, // VPERMPDZmi 920612U, // VPERMPDZmik 461220U, // VPERMPDZmikz 32U, // VPERMPDZri 2340U, // VPERMPDZrik 624740U, // VPERMPDZrikz 416U, // VPERMPDZrm 8576U, // VPERMPDZrmb 3213604U, // VPERMPDZrmbk 3246180U, // VPERMPDZrmbkz 297252U, // VPERMPDZrmk 329828U, // VPERMPDZrmkz 96U, // VPERMPDZrr 166180U, // VPERMPDZrrk 198756U, // VPERMPDZrrkz 320U, // VPERMPSYrm 96U, // VPERMPSYrr 320U, // VPERMPSZ256rm 8640U, // VPERMPSZ256rmb 3541284U, // VPERMPSZ256rmbk 3573860U, // VPERMPSZ256rmbkz 231716U, // VPERMPSZ256rmk 264292U, // VPERMPSZ256rmkz 96U, // VPERMPSZ256rr 166180U, // VPERMPSZ256rrk 198756U, // VPERMPSZ256rrkz 416U, // VPERMPSZrm 10688U, // VPERMPSZrmb 5638436U, // VPERMPSZrmbk 5671012U, // VPERMPSZrmbkz 297252U, // VPERMPSZrmk 329828U, // VPERMPSZrmkz 96U, // VPERMPSZrr 166180U, // VPERMPSZrrk 198756U, // VPERMPSZrrkz 0U, // VPERMQYmi 32U, // VPERMQYri 12U, // VPERMQZ256mbi 930436U, // VPERMQZ256mbik 471172U, // VPERMQZ256mbikz 0U, // VPERMQZ256mi 920260U, // VPERMQZ256mik 461284U, // VPERMQZ256mikz 32U, // VPERMQZ256ri 2340U, // VPERMQZ256rik 624740U, // VPERMQZ256rikz 480U, // VPERMQZ256rm 6272U, // VPERMQZ256rmb 2885924U, // VPERMQZ256rmbk 2918500U, // VPERMQZ256rmbkz 657700U, // VPERMQZ256rmk 690276U, // VPERMQZ256rmkz 96U, // VPERMQZ256rr 166180U, // VPERMQZ256rrk 198756U, // VPERMQZ256rrkz 12U, // VPERMQZmbi 932484U, // VPERMQZmbik 473220U, // VPERMQZmbikz 0U, // VPERMQZmi 920548U, // VPERMQZmik 461348U, // VPERMQZmikz 32U, // VPERMQZri 2340U, // VPERMQZrik 624740U, // VPERMQZrikz 544U, // VPERMQZrm 8320U, // VPERMQZrmb 3934500U, // VPERMQZrmbk 3967076U, // VPERMQZrmbkz 723236U, // VPERMQZrmk 755812U, // VPERMQZrmkz 96U, // VPERMQZrr 166180U, // VPERMQZrrk 198756U, // VPERMQZrrkz 672U, // VPERMT2B128rm 559396U, // VPERMT2B128rmk 559396U, // VPERMT2B128rmkz 288U, // VPERMT2B128rr 166180U, // VPERMT2B128rrk 166180U, // VPERMT2B128rrkz 704U, // VPERMT2B256rm 657700U, // VPERMT2B256rmk 657700U, // VPERMT2B256rmkz 288U, // VPERMT2B256rr 166180U, // VPERMT2B256rrk 166180U, // VPERMT2B256rrkz 992U, // VPERMT2Brm 723236U, // VPERMT2Brmk 723236U, // VPERMT2Brmkz 288U, // VPERMT2Brr 166180U, // VPERMT2Brrk 166180U, // VPERMT2Brrkz 672U, // VPERMT2D128rm 7104U, // VPERMT2D128rmb 2591012U, // VPERMT2D128rmbk 2591012U, // VPERMT2D128rmbkz 559396U, // VPERMT2D128rmk 559396U, // VPERMT2D128rmkz 288U, // VPERMT2D128rr 166180U, // VPERMT2D128rrk 166180U, // VPERMT2D128rrkz 704U, // VPERMT2D256rm 9152U, // VPERMT2D256rmb 3639588U, // VPERMT2D256rmbk 3639588U, // VPERMT2D256rmbkz 657700U, // VPERMT2D256rmk 657700U, // VPERMT2D256rmkz 288U, // VPERMT2D256rr 166180U, // VPERMT2D256rrk 166180U, // VPERMT2D256rrkz 992U, // VPERMT2Drm 11200U, // VPERMT2Drmb 5736740U, // VPERMT2Drmbk 5736740U, // VPERMT2Drmbkz 723236U, // VPERMT2Drmk 723236U, // VPERMT2Drmkz 288U, // VPERMT2Drr 166180U, // VPERMT2Drrk 166180U, // VPERMT2Drrkz 256U, // VPERMT2PD128rm 4672U, // VPERMT2PD128rmb 1116452U, // VPERMT2PD128rmbk 1116452U, // VPERMT2PD128rmbkz 35108U, // VPERMT2PD128rmk 35108U, // VPERMT2PD128rmkz 288U, // VPERMT2PD128rr 166180U, // VPERMT2PD128rrk 166180U, // VPERMT2PD128rrkz 608U, // VPERMT2PD256rm 6720U, // VPERMT2PD256rmb 2165028U, // VPERMT2PD256rmbk 2165028U, // VPERMT2PD256rmbkz 231716U, // VPERMT2PD256rmk 231716U, // VPERMT2PD256rmkz 288U, // VPERMT2PD256rr 166180U, // VPERMT2PD256rrk 166180U, // VPERMT2PD256rrkz 1056U, // VPERMT2PDrm 8768U, // VPERMT2PDrmb 3213604U, // VPERMT2PDrmbk 3213604U, // VPERMT2PDrmbkz 297252U, // VPERMT2PDrmk 297252U, // VPERMT2PDrmkz 288U, // VPERMT2PDrr 166180U, // VPERMT2PDrrk 166180U, // VPERMT2PDrrkz 256U, // VPERMT2PS128rm 6880U, // VPERMT2PS128rmb 2492708U, // VPERMT2PS128rmbk 2492708U, // VPERMT2PS128rmbkz 35108U, // VPERMT2PS128rmk 35108U, // VPERMT2PS128rmkz 288U, // VPERMT2PS128rr 166180U, // VPERMT2PS128rrk 166180U, // VPERMT2PS128rrkz 608U, // VPERMT2PS256rm 8928U, // VPERMT2PS256rmb 3541284U, // VPERMT2PS256rmbk 3541284U, // VPERMT2PS256rmbkz 231716U, // VPERMT2PS256rmk 231716U, // VPERMT2PS256rmkz 288U, // VPERMT2PS256rr 166180U, // VPERMT2PS256rrk 166180U, // VPERMT2PS256rrkz 1056U, // VPERMT2PSrm 10976U, // VPERMT2PSrmb 5638436U, // VPERMT2PSrmbk 5638436U, // VPERMT2PSrmbkz 297252U, // VPERMT2PSrmk 297252U, // VPERMT2PSrmkz 288U, // VPERMT2PSrr 166180U, // VPERMT2PSrrk 166180U, // VPERMT2PSrrkz 672U, // VPERMT2Q128rm 4736U, // VPERMT2Q128rmb 1837348U, // VPERMT2Q128rmbk 1837348U, // VPERMT2Q128rmbkz 559396U, // VPERMT2Q128rmk 559396U, // VPERMT2Q128rmkz 288U, // VPERMT2Q128rr 166180U, // VPERMT2Q128rrk 166180U, // VPERMT2Q128rrkz 704U, // VPERMT2Q256rm 6784U, // VPERMT2Q256rmb 2885924U, // VPERMT2Q256rmbk 2885924U, // VPERMT2Q256rmbkz 657700U, // VPERMT2Q256rmk 657700U, // VPERMT2Q256rmkz 288U, // VPERMT2Q256rr 166180U, // VPERMT2Q256rrk 166180U, // VPERMT2Q256rrkz 992U, // VPERMT2Qrm 8832U, // VPERMT2Qrmb 3934500U, // VPERMT2Qrmbk 3934500U, // VPERMT2Qrmbkz 723236U, // VPERMT2Qrmk 723236U, // VPERMT2Qrmkz 288U, // VPERMT2Qrr 166180U, // VPERMT2Qrrk 166180U, // VPERMT2Qrrkz 672U, // VPERMT2W128rm 559396U, // VPERMT2W128rmk 559396U, // VPERMT2W128rmkz 288U, // VPERMT2W128rr 166180U, // VPERMT2W128rrk 166180U, // VPERMT2W128rrkz 704U, // VPERMT2W256rm 657700U, // VPERMT2W256rmk 657700U, // VPERMT2W256rmkz 288U, // VPERMT2W256rr 166180U, // VPERMT2W256rrk 166180U, // VPERMT2W256rrkz 992U, // VPERMT2Wrm 723236U, // VPERMT2Wrmk 723236U, // VPERMT2Wrmkz 288U, // VPERMT2Wrr 166180U, // VPERMT2Wrrk 166180U, // VPERMT2Wrrkz 512U, // VPERMWZ128rm 559396U, // VPERMWZ128rmk 591972U, // VPERMWZ128rmkz 96U, // VPERMWZ128rr 166180U, // VPERMWZ128rrk 198756U, // VPERMWZ128rrkz 480U, // VPERMWZ256rm 657700U, // VPERMWZ256rmk 690276U, // VPERMWZ256rmkz 96U, // VPERMWZ256rr 166180U, // VPERMWZ256rrk 198756U, // VPERMWZ256rrkz 544U, // VPERMWZrm 723236U, // VPERMWZrmk 755812U, // VPERMWZrmkz 96U, // VPERMWZrr 166180U, // VPERMWZrrk 198756U, // VPERMWZrrkz 0U, // VPEXPANDBZ128rm 676U, // VPEXPANDBZ128rmk 516U, // VPEXPANDBZ128rmkz 0U, // VPEXPANDBZ128rr 292U, // VPEXPANDBZ128rrk 100U, // VPEXPANDBZ128rrkz 0U, // VPEXPANDBZ256rm 708U, // VPEXPANDBZ256rmk 484U, // VPEXPANDBZ256rmkz 0U, // VPEXPANDBZ256rr 292U, // VPEXPANDBZ256rrk 100U, // VPEXPANDBZ256rrkz 0U, // VPEXPANDBZrm 996U, // VPEXPANDBZrmk 548U, // VPEXPANDBZrmkz 0U, // VPEXPANDBZrr 292U, // VPEXPANDBZrrk 100U, // VPEXPANDBZrrkz 0U, // VPEXPANDDZ128rm 676U, // VPEXPANDDZ128rmk 516U, // VPEXPANDDZ128rmkz 0U, // VPEXPANDDZ128rr 292U, // VPEXPANDDZ128rrk 100U, // VPEXPANDDZ128rrkz 0U, // VPEXPANDDZ256rm 708U, // VPEXPANDDZ256rmk 484U, // VPEXPANDDZ256rmkz 0U, // VPEXPANDDZ256rr 292U, // VPEXPANDDZ256rrk 100U, // VPEXPANDDZ256rrkz 0U, // VPEXPANDDZrm 996U, // VPEXPANDDZrmk 548U, // VPEXPANDDZrmkz 0U, // VPEXPANDDZrr 292U, // VPEXPANDDZrrk 100U, // VPEXPANDDZrrkz 0U, // VPEXPANDQZ128rm 676U, // VPEXPANDQZ128rmk 516U, // VPEXPANDQZ128rmkz 0U, // VPEXPANDQZ128rr 292U, // VPEXPANDQZ128rrk 100U, // VPEXPANDQZ128rrkz 0U, // VPEXPANDQZ256rm 708U, // VPEXPANDQZ256rmk 484U, // VPEXPANDQZ256rmkz 0U, // VPEXPANDQZ256rr 292U, // VPEXPANDQZ256rrk 100U, // VPEXPANDQZ256rrkz 0U, // VPEXPANDQZrm 996U, // VPEXPANDQZrmk 548U, // VPEXPANDQZrmkz 0U, // VPEXPANDQZrr 292U, // VPEXPANDQZrrk 100U, // VPEXPANDQZrrkz 0U, // VPEXPANDWZ128rm 676U, // VPEXPANDWZ128rmk 516U, // VPEXPANDWZ128rmkz 0U, // VPEXPANDWZ128rr 292U, // VPEXPANDWZ128rrk 100U, // VPEXPANDWZ128rrkz 0U, // VPEXPANDWZ256rm 708U, // VPEXPANDWZ256rmk 484U, // VPEXPANDWZ256rmkz 0U, // VPEXPANDWZ256rr 292U, // VPEXPANDWZ256rrk 100U, // VPEXPANDWZ256rrkz 0U, // VPEXPANDWZrm 996U, // VPEXPANDWZrmk 548U, // VPEXPANDWZrmkz 0U, // VPEXPANDWZrr 292U, // VPEXPANDWZrrk 100U, // VPEXPANDWZrrkz 0U, // VPEXTRBZmr 32U, // VPEXTRBZrr 0U, // VPEXTRBmr 32U, // VPEXTRBrr 0U, // VPEXTRDZmr 32U, // VPEXTRDZrr 0U, // VPEXTRDmr 32U, // VPEXTRDrr 0U, // VPEXTRQZmr 32U, // VPEXTRQZrr 0U, // VPEXTRQmr 32U, // VPEXTRQrr 0U, // VPEXTRWZmr 32U, // VPEXTRWZrr 32U, // VPEXTRWZrr_REV 0U, // VPEXTRWmr 32U, // VPEXTRWrr 32U, // VPEXTRWrr_REV 0U, // VPGATHERDDYrm 13U, // VPGATHERDDZ128rm 14U, // VPGATHERDDZ256rm 14U, // VPGATHERDDZrm 0U, // VPGATHERDDrm 0U, // VPGATHERDQYrm 13U, // VPGATHERDQZ128rm 14U, // VPGATHERDQZ256rm 14U, // VPGATHERDQZrm 0U, // VPGATHERDQrm 0U, // VPGATHERQDYrm 15U, // VPGATHERQDZ128rm 13U, // VPGATHERQDZ256rm 14U, // VPGATHERQDZrm 0U, // VPGATHERQDrm 0U, // VPGATHERQQYrm 13U, // VPGATHERQQZ128rm 14U, // VPGATHERQQZ256rm 14U, // VPGATHERQQZrm 0U, // VPGATHERQQrm 0U, // VPHADDBDrm 0U, // VPHADDBDrr 0U, // VPHADDBQrm 0U, // VPHADDBQrr 0U, // VPHADDBWrm 0U, // VPHADDBWrr 0U, // VPHADDDQrm 0U, // VPHADDDQrr 480U, // VPHADDDYrm 96U, // VPHADDDYrr 512U, // VPHADDDrm 96U, // VPHADDDrr 480U, // VPHADDSWYrm 96U, // VPHADDSWYrr 512U, // VPHADDSWrm 96U, // VPHADDSWrr 0U, // VPHADDUBDrm 0U, // VPHADDUBDrr 0U, // VPHADDUBQrm 0U, // VPHADDUBQrr 0U, // VPHADDUBWrm 0U, // VPHADDUBWrr 0U, // VPHADDUDQrm 0U, // VPHADDUDQrr 0U, // VPHADDUWDrm 0U, // VPHADDUWDrr 0U, // VPHADDUWQrm 0U, // VPHADDUWQrr 0U, // VPHADDWDrm 0U, // VPHADDWDrr 0U, // VPHADDWQrm 0U, // VPHADDWQrr 480U, // VPHADDWYrm 96U, // VPHADDWYrr 512U, // VPHADDWrm 96U, // VPHADDWrr 0U, // VPHMINPOSUWrm 0U, // VPHMINPOSUWrr 0U, // VPHSUBBWrm 0U, // VPHSUBBWrr 0U, // VPHSUBDQrm 0U, // VPHSUBDQrr 480U, // VPHSUBDYrm 96U, // VPHSUBDYrr 512U, // VPHSUBDrm 96U, // VPHSUBDrr 480U, // VPHSUBSWYrm 96U, // VPHSUBSWYrr 512U, // VPHSUBSWrm 96U, // VPHSUBSWrr 0U, // VPHSUBWDrm 0U, // VPHSUBWDrr 480U, // VPHSUBWYrm 96U, // VPHSUBWYrr 512U, // VPHSUBWrm 96U, // VPHSUBWrr 461920U, // VPINSRBZrm 624736U, // VPINSRBZrr 461920U, // VPINSRBrm 624736U, // VPINSRBrr 460864U, // VPINSRDZrm 624736U, // VPINSRDZrr 460864U, // VPINSRDrm 624736U, // VPINSRDrr 460928U, // VPINSRQZrm 624736U, // VPINSRQZrr 460928U, // VPINSRQrm 624736U, // VPINSRQrr 462016U, // VPINSRWZrm 624736U, // VPINSRWZrr 462016U, // VPINSRWrm 624736U, // VPINSRWrr 0U, // VPLZCNTDZ128rm 9U, // VPLZCNTDZ128rmb 7108U, // VPLZCNTDZ128rmbk 6212U, // VPLZCNTDZ128rmbkz 676U, // VPLZCNTDZ128rmk 516U, // VPLZCNTDZ128rmkz 0U, // VPLZCNTDZ128rr 292U, // VPLZCNTDZ128rrk 100U, // VPLZCNTDZ128rrkz 0U, // VPLZCNTDZ256rm 10U, // VPLZCNTDZ256rmb 9156U, // VPLZCNTDZ256rmbk 8260U, // VPLZCNTDZ256rmbkz 708U, // VPLZCNTDZ256rmk 484U, // VPLZCNTDZ256rmkz 0U, // VPLZCNTDZ256rr 292U, // VPLZCNTDZ256rrk 100U, // VPLZCNTDZ256rrkz 0U, // VPLZCNTDZrm 10U, // VPLZCNTDZrmb 11204U, // VPLZCNTDZrmbk 10308U, // VPLZCNTDZrmbkz 996U, // VPLZCNTDZrmk 548U, // VPLZCNTDZrmkz 0U, // VPLZCNTDZrr 292U, // VPLZCNTDZrrk 100U, // VPLZCNTDZrrkz 0U, // VPLZCNTQZ128rm 9U, // VPLZCNTQZ128rmb 4740U, // VPLZCNTQZ128rmbk 4228U, // VPLZCNTQZ128rmbkz 676U, // VPLZCNTQZ128rmk 516U, // VPLZCNTQZ128rmkz 0U, // VPLZCNTQZ128rr 292U, // VPLZCNTQZ128rrk 100U, // VPLZCNTQZ128rrkz 0U, // VPLZCNTQZ256rm 9U, // VPLZCNTQZ256rmb 6788U, // VPLZCNTQZ256rmbk 6276U, // VPLZCNTQZ256rmbkz 708U, // VPLZCNTQZ256rmk 484U, // VPLZCNTQZ256rmkz 0U, // VPLZCNTQZ256rr 292U, // VPLZCNTQZ256rrk 100U, // VPLZCNTQZ256rrkz 0U, // VPLZCNTQZrm 10U, // VPLZCNTQZrmb 8836U, // VPLZCNTQZrmbk 8324U, // VPLZCNTQZrmbkz 996U, // VPLZCNTQZrmk 548U, // VPLZCNTQZrmkz 0U, // VPLZCNTQZrr 292U, // VPLZCNTQZrrk 100U, // VPLZCNTQZrrkz 854528U, // VPMACSDDrm 198752U, // VPMACSDDrr 854528U, // VPMACSDQHrm 198752U, // VPMACSDQHrr 854528U, // VPMACSDQLrm 198752U, // VPMACSDQLrr 854528U, // VPMACSSDDrm 198752U, // VPMACSSDDrr 854528U, // VPMACSSDQHrm 198752U, // VPMACSSDQHrr 854528U, // VPMACSSDQLrm 198752U, // VPMACSSDQLrr 854528U, // VPMACSSWDrm 198752U, // VPMACSSWDrr 854528U, // VPMACSSWWrm 198752U, // VPMACSSWWrr 854528U, // VPMACSWDrm 198752U, // VPMACSWDrr 854528U, // VPMACSWWrm 198752U, // VPMACSWWrr 854528U, // VPMADCSSWDrm 198752U, // VPMADCSSWDrr 854528U, // VPMADCSWDrm 198752U, // VPMADCSWDrr 672U, // VPMADD52HUQZ128m 4736U, // VPMADD52HUQZ128mb 1837348U, // VPMADD52HUQZ128mbk 1837348U, // VPMADD52HUQZ128mbkz 559396U, // VPMADD52HUQZ128mk 559396U, // VPMADD52HUQZ128mkz 288U, // VPMADD52HUQZ128r 166180U, // VPMADD52HUQZ128rk 166180U, // VPMADD52HUQZ128rkz 704U, // VPMADD52HUQZ256m 6784U, // VPMADD52HUQZ256mb 2885924U, // VPMADD52HUQZ256mbk 2885924U, // VPMADD52HUQZ256mbkz 657700U, // VPMADD52HUQZ256mk 657700U, // VPMADD52HUQZ256mkz 288U, // VPMADD52HUQZ256r 166180U, // VPMADD52HUQZ256rk 166180U, // VPMADD52HUQZ256rkz 992U, // VPMADD52HUQZm 8832U, // VPMADD52HUQZmb 3934500U, // VPMADD52HUQZmbk 3934500U, // VPMADD52HUQZmbkz 723236U, // VPMADD52HUQZmk 723236U, // VPMADD52HUQZmkz 288U, // VPMADD52HUQZr 166180U, // VPMADD52HUQZrk 166180U, // VPMADD52HUQZrkz 672U, // VPMADD52LUQZ128m 4736U, // VPMADD52LUQZ128mb 1837348U, // VPMADD52LUQZ128mbk 1837348U, // VPMADD52LUQZ128mbkz 559396U, // VPMADD52LUQZ128mk 559396U, // VPMADD52LUQZ128mkz 288U, // VPMADD52LUQZ128r 166180U, // VPMADD52LUQZ128rk 166180U, // VPMADD52LUQZ128rkz 704U, // VPMADD52LUQZ256m 6784U, // VPMADD52LUQZ256mb 2885924U, // VPMADD52LUQZ256mbk 2885924U, // VPMADD52LUQZ256mbkz 657700U, // VPMADD52LUQZ256mk 657700U, // VPMADD52LUQZ256mkz 288U, // VPMADD52LUQZ256r 166180U, // VPMADD52LUQZ256rk 166180U, // VPMADD52LUQZ256rkz 992U, // VPMADD52LUQZm 8832U, // VPMADD52LUQZmb 3934500U, // VPMADD52LUQZmbk 3934500U, // VPMADD52LUQZmbkz 723236U, // VPMADD52LUQZmk 723236U, // VPMADD52LUQZmkz 288U, // VPMADD52LUQZr 166180U, // VPMADD52LUQZrk 166180U, // VPMADD52LUQZrkz 480U, // VPMADDUBSWYrm 96U, // VPMADDUBSWYrr 512U, // VPMADDUBSWZ128rm 559396U, // VPMADDUBSWZ128rmk 591972U, // VPMADDUBSWZ128rmkz 96U, // VPMADDUBSWZ128rr 166180U, // VPMADDUBSWZ128rrk 198756U, // VPMADDUBSWZ128rrkz 480U, // VPMADDUBSWZ256rm 657700U, // VPMADDUBSWZ256rmk 690276U, // VPMADDUBSWZ256rmkz 96U, // VPMADDUBSWZ256rr 166180U, // VPMADDUBSWZ256rrk 198756U, // VPMADDUBSWZ256rrkz 544U, // VPMADDUBSWZrm 723236U, // VPMADDUBSWZrmk 755812U, // VPMADDUBSWZrmkz 96U, // VPMADDUBSWZrr 166180U, // VPMADDUBSWZrrk 198756U, // VPMADDUBSWZrrkz 512U, // VPMADDUBSWrm 96U, // VPMADDUBSWrr 480U, // VPMADDWDYrm 96U, // VPMADDWDYrr 512U, // VPMADDWDZ128rm 559396U, // VPMADDWDZ128rmk 591972U, // VPMADDWDZ128rmkz 96U, // VPMADDWDZ128rr 166180U, // VPMADDWDZ128rrk 198756U, // VPMADDWDZ128rrkz 480U, // VPMADDWDZ256rm 657700U, // VPMADDWDZ256rmk 690276U, // VPMADDWDZ256rmkz 96U, // VPMADDWDZ256rr 166180U, // VPMADDWDZ256rrk 198756U, // VPMADDWDZ256rrkz 544U, // VPMADDWDZrm 723236U, // VPMADDWDZrmk 755812U, // VPMADDWDZrmkz 96U, // VPMADDWDZrr 166180U, // VPMADDWDZrrk 198756U, // VPMADDWDZrrkz 512U, // VPMADDWDrm 96U, // VPMADDWDrr 160U, // VPMASKMOVDYmr 480U, // VPMASKMOVDYrm 160U, // VPMASKMOVDmr 512U, // VPMASKMOVDrm 160U, // VPMASKMOVQYmr 480U, // VPMASKMOVQYrm 160U, // VPMASKMOVQmr 512U, // VPMASKMOVQrm 480U, // VPMAXSBYrm 96U, // VPMAXSBYrr 512U, // VPMAXSBZ128rm 559396U, // VPMAXSBZ128rmk 591972U, // VPMAXSBZ128rmkz 96U, // VPMAXSBZ128rr 166180U, // VPMAXSBZ128rrk 198756U, // VPMAXSBZ128rrkz 480U, // VPMAXSBZ256rm 657700U, // VPMAXSBZ256rmk 690276U, // VPMAXSBZ256rmkz 96U, // VPMAXSBZ256rr 166180U, // VPMAXSBZ256rrk 198756U, // VPMAXSBZ256rrkz 544U, // VPMAXSBZrm 723236U, // VPMAXSBZrmk 755812U, // VPMAXSBZrmkz 96U, // VPMAXSBZrr 166180U, // VPMAXSBZrrk 198756U, // VPMAXSBZrrkz 512U, // VPMAXSBrm 96U, // VPMAXSBrr 480U, // VPMAXSDYrm 96U, // VPMAXSDYrr 512U, // VPMAXSDZ128rm 6208U, // VPMAXSDZ128rmb 2591012U, // VPMAXSDZ128rmbk 2623588U, // VPMAXSDZ128rmbkz 559396U, // VPMAXSDZ128rmk 591972U, // VPMAXSDZ128rmkz 96U, // VPMAXSDZ128rr 166180U, // VPMAXSDZ128rrk 198756U, // VPMAXSDZ128rrkz 480U, // VPMAXSDZ256rm 8256U, // VPMAXSDZ256rmb 3639588U, // VPMAXSDZ256rmbk 3672164U, // VPMAXSDZ256rmbkz 657700U, // VPMAXSDZ256rmk 690276U, // VPMAXSDZ256rmkz 96U, // VPMAXSDZ256rr 166180U, // VPMAXSDZ256rrk 198756U, // VPMAXSDZ256rrkz 544U, // VPMAXSDZrm 10304U, // VPMAXSDZrmb 5736740U, // VPMAXSDZrmbk 5769316U, // VPMAXSDZrmbkz 723236U, // VPMAXSDZrmk 755812U, // VPMAXSDZrmkz 96U, // VPMAXSDZrr 166180U, // VPMAXSDZrrk 198756U, // VPMAXSDZrrkz 512U, // VPMAXSDrm 96U, // VPMAXSDrr 512U, // VPMAXSQZ128rm 4224U, // VPMAXSQZ128rmb 1837348U, // VPMAXSQZ128rmbk 1869924U, // VPMAXSQZ128rmbkz 559396U, // VPMAXSQZ128rmk 591972U, // VPMAXSQZ128rmkz 96U, // VPMAXSQZ128rr 166180U, // VPMAXSQZ128rrk 198756U, // VPMAXSQZ128rrkz 480U, // VPMAXSQZ256rm 6272U, // VPMAXSQZ256rmb 2885924U, // VPMAXSQZ256rmbk 2918500U, // VPMAXSQZ256rmbkz 657700U, // VPMAXSQZ256rmk 690276U, // VPMAXSQZ256rmkz 96U, // VPMAXSQZ256rr 166180U, // VPMAXSQZ256rrk 198756U, // VPMAXSQZ256rrkz 544U, // VPMAXSQZrm 8320U, // VPMAXSQZrmb 3934500U, // VPMAXSQZrmbk 3967076U, // VPMAXSQZrmbkz 723236U, // VPMAXSQZrmk 755812U, // VPMAXSQZrmkz 96U, // VPMAXSQZrr 166180U, // VPMAXSQZrrk 198756U, // VPMAXSQZrrkz 480U, // VPMAXSWYrm 96U, // VPMAXSWYrr 512U, // VPMAXSWZ128rm 559396U, // VPMAXSWZ128rmk 591972U, // VPMAXSWZ128rmkz 96U, // VPMAXSWZ128rr 166180U, // VPMAXSWZ128rrk 198756U, // VPMAXSWZ128rrkz 480U, // VPMAXSWZ256rm 657700U, // VPMAXSWZ256rmk 690276U, // VPMAXSWZ256rmkz 96U, // VPMAXSWZ256rr 166180U, // VPMAXSWZ256rrk 198756U, // VPMAXSWZ256rrkz 544U, // VPMAXSWZrm 723236U, // VPMAXSWZrmk 755812U, // VPMAXSWZrmkz 96U, // VPMAXSWZrr 166180U, // VPMAXSWZrrk 198756U, // VPMAXSWZrrkz 512U, // VPMAXSWrm 96U, // VPMAXSWrr 480U, // VPMAXUBYrm 96U, // VPMAXUBYrr 512U, // VPMAXUBZ128rm 559396U, // VPMAXUBZ128rmk 591972U, // VPMAXUBZ128rmkz 96U, // VPMAXUBZ128rr 166180U, // VPMAXUBZ128rrk 198756U, // VPMAXUBZ128rrkz 480U, // VPMAXUBZ256rm 657700U, // VPMAXUBZ256rmk 690276U, // VPMAXUBZ256rmkz 96U, // VPMAXUBZ256rr 166180U, // VPMAXUBZ256rrk 198756U, // VPMAXUBZ256rrkz 544U, // VPMAXUBZrm 723236U, // VPMAXUBZrmk 755812U, // VPMAXUBZrmkz 96U, // VPMAXUBZrr 166180U, // VPMAXUBZrrk 198756U, // VPMAXUBZrrkz 512U, // VPMAXUBrm 96U, // VPMAXUBrr 480U, // VPMAXUDYrm 96U, // VPMAXUDYrr 512U, // VPMAXUDZ128rm 6208U, // VPMAXUDZ128rmb 2591012U, // VPMAXUDZ128rmbk 2623588U, // VPMAXUDZ128rmbkz 559396U, // VPMAXUDZ128rmk 591972U, // VPMAXUDZ128rmkz 96U, // VPMAXUDZ128rr 166180U, // VPMAXUDZ128rrk 198756U, // VPMAXUDZ128rrkz 480U, // VPMAXUDZ256rm 8256U, // VPMAXUDZ256rmb 3639588U, // VPMAXUDZ256rmbk 3672164U, // VPMAXUDZ256rmbkz 657700U, // VPMAXUDZ256rmk 690276U, // VPMAXUDZ256rmkz 96U, // VPMAXUDZ256rr 166180U, // VPMAXUDZ256rrk 198756U, // VPMAXUDZ256rrkz 544U, // VPMAXUDZrm 10304U, // VPMAXUDZrmb 5736740U, // VPMAXUDZrmbk 5769316U, // VPMAXUDZrmbkz 723236U, // VPMAXUDZrmk 755812U, // VPMAXUDZrmkz 96U, // VPMAXUDZrr 166180U, // VPMAXUDZrrk 198756U, // VPMAXUDZrrkz 512U, // VPMAXUDrm 96U, // VPMAXUDrr 512U, // VPMAXUQZ128rm 4224U, // VPMAXUQZ128rmb 1837348U, // VPMAXUQZ128rmbk 1869924U, // VPMAXUQZ128rmbkz 559396U, // VPMAXUQZ128rmk 591972U, // VPMAXUQZ128rmkz 96U, // VPMAXUQZ128rr 166180U, // VPMAXUQZ128rrk 198756U, // VPMAXUQZ128rrkz 480U, // VPMAXUQZ256rm 6272U, // VPMAXUQZ256rmb 2885924U, // VPMAXUQZ256rmbk 2918500U, // VPMAXUQZ256rmbkz 657700U, // VPMAXUQZ256rmk 690276U, // VPMAXUQZ256rmkz 96U, // VPMAXUQZ256rr 166180U, // VPMAXUQZ256rrk 198756U, // VPMAXUQZ256rrkz 544U, // VPMAXUQZrm 8320U, // VPMAXUQZrmb 3934500U, // VPMAXUQZrmbk 3967076U, // VPMAXUQZrmbkz 723236U, // VPMAXUQZrmk 755812U, // VPMAXUQZrmkz 96U, // VPMAXUQZrr 166180U, // VPMAXUQZrrk 198756U, // VPMAXUQZrrkz 480U, // VPMAXUWYrm 96U, // VPMAXUWYrr 512U, // VPMAXUWZ128rm 559396U, // VPMAXUWZ128rmk 591972U, // VPMAXUWZ128rmkz 96U, // VPMAXUWZ128rr 166180U, // VPMAXUWZ128rrk 198756U, // VPMAXUWZ128rrkz 480U, // VPMAXUWZ256rm 657700U, // VPMAXUWZ256rmk 690276U, // VPMAXUWZ256rmkz 96U, // VPMAXUWZ256rr 166180U, // VPMAXUWZ256rrk 198756U, // VPMAXUWZ256rrkz 544U, // VPMAXUWZrm 723236U, // VPMAXUWZrmk 755812U, // VPMAXUWZrmkz 96U, // VPMAXUWZrr 166180U, // VPMAXUWZrrk 198756U, // VPMAXUWZrrkz 512U, // VPMAXUWrm 96U, // VPMAXUWrr 480U, // VPMINSBYrm 96U, // VPMINSBYrr 512U, // VPMINSBZ128rm 559396U, // VPMINSBZ128rmk 591972U, // VPMINSBZ128rmkz 96U, // VPMINSBZ128rr 166180U, // VPMINSBZ128rrk 198756U, // VPMINSBZ128rrkz 480U, // VPMINSBZ256rm 657700U, // VPMINSBZ256rmk 690276U, // VPMINSBZ256rmkz 96U, // VPMINSBZ256rr 166180U, // VPMINSBZ256rrk 198756U, // VPMINSBZ256rrkz 544U, // VPMINSBZrm 723236U, // VPMINSBZrmk 755812U, // VPMINSBZrmkz 96U, // VPMINSBZrr 166180U, // VPMINSBZrrk 198756U, // VPMINSBZrrkz 512U, // VPMINSBrm 96U, // VPMINSBrr 480U, // VPMINSDYrm 96U, // VPMINSDYrr 512U, // VPMINSDZ128rm 6208U, // VPMINSDZ128rmb 2591012U, // VPMINSDZ128rmbk 2623588U, // VPMINSDZ128rmbkz 559396U, // VPMINSDZ128rmk 591972U, // VPMINSDZ128rmkz 96U, // VPMINSDZ128rr 166180U, // VPMINSDZ128rrk 198756U, // VPMINSDZ128rrkz 480U, // VPMINSDZ256rm 8256U, // VPMINSDZ256rmb 3639588U, // VPMINSDZ256rmbk 3672164U, // VPMINSDZ256rmbkz 657700U, // VPMINSDZ256rmk 690276U, // VPMINSDZ256rmkz 96U, // VPMINSDZ256rr 166180U, // VPMINSDZ256rrk 198756U, // VPMINSDZ256rrkz 544U, // VPMINSDZrm 10304U, // VPMINSDZrmb 5736740U, // VPMINSDZrmbk 5769316U, // VPMINSDZrmbkz 723236U, // VPMINSDZrmk 755812U, // VPMINSDZrmkz 96U, // VPMINSDZrr 166180U, // VPMINSDZrrk 198756U, // VPMINSDZrrkz 512U, // VPMINSDrm 96U, // VPMINSDrr 512U, // VPMINSQZ128rm 4224U, // VPMINSQZ128rmb 1837348U, // VPMINSQZ128rmbk 1869924U, // VPMINSQZ128rmbkz 559396U, // VPMINSQZ128rmk 591972U, // VPMINSQZ128rmkz 96U, // VPMINSQZ128rr 166180U, // VPMINSQZ128rrk 198756U, // VPMINSQZ128rrkz 480U, // VPMINSQZ256rm 6272U, // VPMINSQZ256rmb 2885924U, // VPMINSQZ256rmbk 2918500U, // VPMINSQZ256rmbkz 657700U, // VPMINSQZ256rmk 690276U, // VPMINSQZ256rmkz 96U, // VPMINSQZ256rr 166180U, // VPMINSQZ256rrk 198756U, // VPMINSQZ256rrkz 544U, // VPMINSQZrm 8320U, // VPMINSQZrmb 3934500U, // VPMINSQZrmbk 3967076U, // VPMINSQZrmbkz 723236U, // VPMINSQZrmk 755812U, // VPMINSQZrmkz 96U, // VPMINSQZrr 166180U, // VPMINSQZrrk 198756U, // VPMINSQZrrkz 480U, // VPMINSWYrm 96U, // VPMINSWYrr 512U, // VPMINSWZ128rm 559396U, // VPMINSWZ128rmk 591972U, // VPMINSWZ128rmkz 96U, // VPMINSWZ128rr 166180U, // VPMINSWZ128rrk 198756U, // VPMINSWZ128rrkz 480U, // VPMINSWZ256rm 657700U, // VPMINSWZ256rmk 690276U, // VPMINSWZ256rmkz 96U, // VPMINSWZ256rr 166180U, // VPMINSWZ256rrk 198756U, // VPMINSWZ256rrkz 544U, // VPMINSWZrm 723236U, // VPMINSWZrmk 755812U, // VPMINSWZrmkz 96U, // VPMINSWZrr 166180U, // VPMINSWZrrk 198756U, // VPMINSWZrrkz 512U, // VPMINSWrm 96U, // VPMINSWrr 480U, // VPMINUBYrm 96U, // VPMINUBYrr 512U, // VPMINUBZ128rm 559396U, // VPMINUBZ128rmk 591972U, // VPMINUBZ128rmkz 96U, // VPMINUBZ128rr 166180U, // VPMINUBZ128rrk 198756U, // VPMINUBZ128rrkz 480U, // VPMINUBZ256rm 657700U, // VPMINUBZ256rmk 690276U, // VPMINUBZ256rmkz 96U, // VPMINUBZ256rr 166180U, // VPMINUBZ256rrk 198756U, // VPMINUBZ256rrkz 544U, // VPMINUBZrm 723236U, // VPMINUBZrmk 755812U, // VPMINUBZrmkz 96U, // VPMINUBZrr 166180U, // VPMINUBZrrk 198756U, // VPMINUBZrrkz 512U, // VPMINUBrm 96U, // VPMINUBrr 480U, // VPMINUDYrm 96U, // VPMINUDYrr 512U, // VPMINUDZ128rm 6208U, // VPMINUDZ128rmb 2591012U, // VPMINUDZ128rmbk 2623588U, // VPMINUDZ128rmbkz 559396U, // VPMINUDZ128rmk 591972U, // VPMINUDZ128rmkz 96U, // VPMINUDZ128rr 166180U, // VPMINUDZ128rrk 198756U, // VPMINUDZ128rrkz 480U, // VPMINUDZ256rm 8256U, // VPMINUDZ256rmb 3639588U, // VPMINUDZ256rmbk 3672164U, // VPMINUDZ256rmbkz 657700U, // VPMINUDZ256rmk 690276U, // VPMINUDZ256rmkz 96U, // VPMINUDZ256rr 166180U, // VPMINUDZ256rrk 198756U, // VPMINUDZ256rrkz 544U, // VPMINUDZrm 10304U, // VPMINUDZrmb 5736740U, // VPMINUDZrmbk 5769316U, // VPMINUDZrmbkz 723236U, // VPMINUDZrmk 755812U, // VPMINUDZrmkz 96U, // VPMINUDZrr 166180U, // VPMINUDZrrk 198756U, // VPMINUDZrrkz 512U, // VPMINUDrm 96U, // VPMINUDrr 512U, // VPMINUQZ128rm 4224U, // VPMINUQZ128rmb 1837348U, // VPMINUQZ128rmbk 1869924U, // VPMINUQZ128rmbkz 559396U, // VPMINUQZ128rmk 591972U, // VPMINUQZ128rmkz 96U, // VPMINUQZ128rr 166180U, // VPMINUQZ128rrk 198756U, // VPMINUQZ128rrkz 480U, // VPMINUQZ256rm 6272U, // VPMINUQZ256rmb 2885924U, // VPMINUQZ256rmbk 2918500U, // VPMINUQZ256rmbkz 657700U, // VPMINUQZ256rmk 690276U, // VPMINUQZ256rmkz 96U, // VPMINUQZ256rr 166180U, // VPMINUQZ256rrk 198756U, // VPMINUQZ256rrkz 544U, // VPMINUQZrm 8320U, // VPMINUQZrmb 3934500U, // VPMINUQZrmbk 3967076U, // VPMINUQZrmbkz 723236U, // VPMINUQZrmk 755812U, // VPMINUQZrmkz 96U, // VPMINUQZrr 166180U, // VPMINUQZrrk 198756U, // VPMINUQZrrkz 480U, // VPMINUWYrm 96U, // VPMINUWYrr 512U, // VPMINUWZ128rm 559396U, // VPMINUWZ128rmk 591972U, // VPMINUWZ128rmkz 96U, // VPMINUWZ128rr 166180U, // VPMINUWZ128rrk 198756U, // VPMINUWZ128rrkz 480U, // VPMINUWZ256rm 657700U, // VPMINUWZ256rmk 690276U, // VPMINUWZ256rmkz 96U, // VPMINUWZ256rr 166180U, // VPMINUWZ256rrk 198756U, // VPMINUWZ256rrkz 544U, // VPMINUWZrm 723236U, // VPMINUWZrmk 755812U, // VPMINUWZrmkz 96U, // VPMINUWZrr 166180U, // VPMINUWZrrk 198756U, // VPMINUWZrrkz 512U, // VPMINUWrm 96U, // VPMINUWrr 0U, // VPMOVB2MZ128rr 0U, // VPMOVB2MZ256rr 0U, // VPMOVB2MZrr 0U, // VPMOVD2MZ128rr 0U, // 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100U, // VPMOVZXBDZ128rrkz 0U, // VPMOVZXBDZ256rm 644U, // VPMOVZXBDZ256rmk 132U, // VPMOVZXBDZ256rmkz 0U, // VPMOVZXBDZ256rr 292U, // VPMOVZXBDZ256rrk 100U, // VPMOVZXBDZ256rrkz 0U, // VPMOVZXBDZrm 676U, // VPMOVZXBDZrmk 516U, // VPMOVZXBDZrmkz 0U, // VPMOVZXBDZrr 292U, // VPMOVZXBDZrrk 100U, // VPMOVZXBDZrrkz 0U, // VPMOVZXBDrm 0U, // VPMOVZXBDrr 0U, // VPMOVZXBQYrm 0U, // VPMOVZXBQYrr 0U, // VPMOVZXBQZ128rm 1188U, // VPMOVZXBQZ128rmk 1220U, // VPMOVZXBQZ128rmkz 0U, // VPMOVZXBQZ128rr 292U, // VPMOVZXBQZ128rrk 100U, // VPMOVZXBQZ128rrkz 0U, // VPMOVZXBQZ256rm 964U, // VPMOVZXBQZ256rmk 68U, // VPMOVZXBQZ256rmkz 0U, // VPMOVZXBQZ256rr 292U, // VPMOVZXBQZ256rrk 100U, // VPMOVZXBQZ256rrkz 0U, // VPMOVZXBQZrm 644U, // VPMOVZXBQZrmk 132U, // VPMOVZXBQZrmkz 0U, // VPMOVZXBQZrr 292U, // VPMOVZXBQZrrk 100U, // VPMOVZXBQZrrkz 0U, // VPMOVZXBQrm 0U, // VPMOVZXBQrr 0U, // VPMOVZXBWYrm 0U, // VPMOVZXBWYrr 0U, // VPMOVZXBWZ128rm 644U, // VPMOVZXBWZ128rmk 132U, // VPMOVZXBWZ128rmkz 0U, // VPMOVZXBWZ128rr 292U, // VPMOVZXBWZ128rrk 100U, // VPMOVZXBWZ128rrkz 0U, // VPMOVZXBWZ256rm 676U, // VPMOVZXBWZ256rmk 516U, // VPMOVZXBWZ256rmkz 0U, // VPMOVZXBWZ256rr 292U, // VPMOVZXBWZ256rrk 100U, // VPMOVZXBWZ256rrkz 0U, // VPMOVZXBWZrm 708U, // VPMOVZXBWZrmk 484U, // VPMOVZXBWZrmkz 0U, // VPMOVZXBWZrr 292U, // VPMOVZXBWZrrk 100U, // VPMOVZXBWZrrkz 0U, // VPMOVZXBWrm 0U, // VPMOVZXBWrr 0U, // VPMOVZXDQYrm 0U, // VPMOVZXDQYrr 0U, // VPMOVZXDQZ128rm 644U, // VPMOVZXDQZ128rmk 132U, // VPMOVZXDQZ128rmkz 0U, // VPMOVZXDQZ128rr 292U, // VPMOVZXDQZ128rrk 100U, // VPMOVZXDQZ128rrkz 0U, // VPMOVZXDQZ256rm 676U, // VPMOVZXDQZ256rmk 516U, // VPMOVZXDQZ256rmkz 0U, // VPMOVZXDQZ256rr 292U, // VPMOVZXDQZ256rrk 100U, // VPMOVZXDQZ256rrkz 0U, // VPMOVZXDQZrm 708U, // VPMOVZXDQZrmk 484U, // VPMOVZXDQZrmkz 0U, // VPMOVZXDQZrr 292U, // VPMOVZXDQZrrk 100U, // VPMOVZXDQZrrkz 0U, // VPMOVZXDQrm 0U, // VPMOVZXDQrr 0U, // VPMOVZXWDYrm 0U, // VPMOVZXWDYrr 0U, // VPMOVZXWDZ128rm 644U, // VPMOVZXWDZ128rmk 132U, // VPMOVZXWDZ128rmkz 0U, // VPMOVZXWDZ128rr 292U, // VPMOVZXWDZ128rrk 100U, // VPMOVZXWDZ128rrkz 0U, // VPMOVZXWDZ256rm 676U, // VPMOVZXWDZ256rmk 516U, // VPMOVZXWDZ256rmkz 0U, // VPMOVZXWDZ256rr 292U, // VPMOVZXWDZ256rrk 100U, // VPMOVZXWDZ256rrkz 0U, // VPMOVZXWDZrm 708U, // VPMOVZXWDZrmk 484U, // VPMOVZXWDZrmkz 0U, // VPMOVZXWDZrr 292U, // VPMOVZXWDZrrk 100U, // VPMOVZXWDZrrkz 0U, // VPMOVZXWDrm 0U, // VPMOVZXWDrr 0U, // VPMOVZXWQYrm 0U, // VPMOVZXWQYrr 0U, // VPMOVZXWQZ128rm 964U, // VPMOVZXWQZ128rmk 68U, // VPMOVZXWQZ128rmkz 0U, // VPMOVZXWQZ128rr 292U, // VPMOVZXWQZ128rrk 100U, // VPMOVZXWQZ128rrkz 0U, // VPMOVZXWQZ256rm 644U, // VPMOVZXWQZ256rmk 132U, // VPMOVZXWQZ256rmkz 0U, // VPMOVZXWQZ256rr 292U, // VPMOVZXWQZ256rrk 100U, // VPMOVZXWQZ256rrkz 0U, // VPMOVZXWQZrm 676U, // VPMOVZXWQZrmk 516U, // VPMOVZXWQZrmkz 0U, // VPMOVZXWQZrr 292U, // VPMOVZXWQZrrk 100U, // VPMOVZXWQZrrkz 0U, // VPMOVZXWQrm 0U, // VPMOVZXWQrr 480U, // VPMULDQYrm 96U, // VPMULDQYrr 512U, // VPMULDQZ128rm 4224U, // VPMULDQZ128rmb 1837348U, // VPMULDQZ128rmbk 1869924U, // VPMULDQZ128rmbkz 559396U, // VPMULDQZ128rmk 591972U, // VPMULDQZ128rmkz 96U, // VPMULDQZ128rr 166180U, // VPMULDQZ128rrk 198756U, // VPMULDQZ128rrkz 480U, // VPMULDQZ256rm 6272U, // VPMULDQZ256rmb 2885924U, // VPMULDQZ256rmbk 2918500U, // VPMULDQZ256rmbkz 657700U, // VPMULDQZ256rmk 690276U, // VPMULDQZ256rmkz 96U, // VPMULDQZ256rr 166180U, // VPMULDQZ256rrk 198756U, // VPMULDQZ256rrkz 544U, // VPMULDQZrm 8320U, // VPMULDQZrmb 3934500U, // VPMULDQZrmbk 3967076U, // VPMULDQZrmbkz 723236U, // VPMULDQZrmk 755812U, // VPMULDQZrmkz 96U, // VPMULDQZrr 166180U, // VPMULDQZrrk 198756U, // VPMULDQZrrkz 512U, // VPMULDQrm 96U, // VPMULDQrr 480U, // VPMULHRSWYrm 96U, // VPMULHRSWYrr 512U, // VPMULHRSWZ128rm 559396U, // VPMULHRSWZ128rmk 591972U, // VPMULHRSWZ128rmkz 96U, // VPMULHRSWZ128rr 166180U, // VPMULHRSWZ128rrk 198756U, // VPMULHRSWZ128rrkz 480U, // VPMULHRSWZ256rm 657700U, // VPMULHRSWZ256rmk 690276U, // VPMULHRSWZ256rmkz 96U, // VPMULHRSWZ256rr 166180U, // VPMULHRSWZ256rrk 198756U, // VPMULHRSWZ256rrkz 544U, // VPMULHRSWZrm 723236U, // VPMULHRSWZrmk 755812U, // VPMULHRSWZrmkz 96U, // VPMULHRSWZrr 166180U, // VPMULHRSWZrrk 198756U, // VPMULHRSWZrrkz 512U, // VPMULHRSWrm 96U, // VPMULHRSWrr 480U, // VPMULHUWYrm 96U, // VPMULHUWYrr 512U, // VPMULHUWZ128rm 559396U, // VPMULHUWZ128rmk 591972U, // VPMULHUWZ128rmkz 96U, // VPMULHUWZ128rr 166180U, // VPMULHUWZ128rrk 198756U, // VPMULHUWZ128rrkz 480U, // VPMULHUWZ256rm 657700U, // VPMULHUWZ256rmk 690276U, // VPMULHUWZ256rmkz 96U, // VPMULHUWZ256rr 166180U, // VPMULHUWZ256rrk 198756U, // VPMULHUWZ256rrkz 544U, // VPMULHUWZrm 723236U, // VPMULHUWZrmk 755812U, // VPMULHUWZrmkz 96U, // VPMULHUWZrr 166180U, // VPMULHUWZrrk 198756U, // VPMULHUWZrrkz 512U, // VPMULHUWrm 96U, // VPMULHUWrr 480U, // VPMULHWYrm 96U, // VPMULHWYrr 512U, // VPMULHWZ128rm 559396U, // VPMULHWZ128rmk 591972U, // VPMULHWZ128rmkz 96U, // VPMULHWZ128rr 166180U, // VPMULHWZ128rrk 198756U, // VPMULHWZ128rrkz 480U, // VPMULHWZ256rm 657700U, // VPMULHWZ256rmk 690276U, // VPMULHWZ256rmkz 96U, // VPMULHWZ256rr 166180U, // VPMULHWZ256rrk 198756U, // VPMULHWZ256rrkz 544U, // VPMULHWZrm 723236U, // VPMULHWZrmk 755812U, // VPMULHWZrmkz 96U, // VPMULHWZrr 166180U, // VPMULHWZrrk 198756U, // VPMULHWZrrkz 512U, // VPMULHWrm 96U, // VPMULHWrr 480U, // VPMULLDYrm 96U, // VPMULLDYrr 512U, // VPMULLDZ128rm 6208U, // VPMULLDZ128rmb 2591012U, // VPMULLDZ128rmbk 2623588U, // VPMULLDZ128rmbkz 559396U, // VPMULLDZ128rmk 591972U, // VPMULLDZ128rmkz 96U, // VPMULLDZ128rr 166180U, // VPMULLDZ128rrk 198756U, // VPMULLDZ128rrkz 480U, // VPMULLDZ256rm 8256U, // VPMULLDZ256rmb 3639588U, // VPMULLDZ256rmbk 3672164U, // VPMULLDZ256rmbkz 657700U, // VPMULLDZ256rmk 690276U, // VPMULLDZ256rmkz 96U, // VPMULLDZ256rr 166180U, // VPMULLDZ256rrk 198756U, // VPMULLDZ256rrkz 544U, // VPMULLDZrm 10304U, // VPMULLDZrmb 5736740U, // VPMULLDZrmbk 5769316U, // VPMULLDZrmbkz 723236U, // VPMULLDZrmk 755812U, // VPMULLDZrmkz 96U, // VPMULLDZrr 166180U, // VPMULLDZrrk 198756U, // VPMULLDZrrkz 512U, // VPMULLDrm 96U, // VPMULLDrr 512U, // VPMULLQZ128rm 4224U, // VPMULLQZ128rmb 1837348U, // VPMULLQZ128rmbk 1869924U, // VPMULLQZ128rmbkz 559396U, // VPMULLQZ128rmk 591972U, // VPMULLQZ128rmkz 96U, // VPMULLQZ128rr 166180U, // VPMULLQZ128rrk 198756U, // VPMULLQZ128rrkz 480U, // VPMULLQZ256rm 6272U, // VPMULLQZ256rmb 2885924U, // VPMULLQZ256rmbk 2918500U, // VPMULLQZ256rmbkz 657700U, // VPMULLQZ256rmk 690276U, // VPMULLQZ256rmkz 96U, // VPMULLQZ256rr 166180U, // VPMULLQZ256rrk 198756U, // VPMULLQZ256rrkz 544U, // VPMULLQZrm 8320U, // VPMULLQZrmb 3934500U, // VPMULLQZrmbk 3967076U, // VPMULLQZrmbkz 723236U, // VPMULLQZrmk 755812U, // VPMULLQZrmkz 96U, // VPMULLQZrr 166180U, // VPMULLQZrrk 198756U, // VPMULLQZrrkz 480U, // VPMULLWYrm 96U, // VPMULLWYrr 512U, // VPMULLWZ128rm 559396U, // VPMULLWZ128rmk 591972U, // VPMULLWZ128rmkz 96U, // VPMULLWZ128rr 166180U, // VPMULLWZ128rrk 198756U, // VPMULLWZ128rrkz 480U, // VPMULLWZ256rm 657700U, // VPMULLWZ256rmk 690276U, // VPMULLWZ256rmkz 96U, // VPMULLWZ256rr 166180U, // VPMULLWZ256rrk 198756U, // VPMULLWZ256rrkz 544U, // VPMULLWZrm 723236U, // VPMULLWZrmk 755812U, // VPMULLWZrmkz 96U, // VPMULLWZrr 166180U, // VPMULLWZrrk 198756U, // VPMULLWZrrkz 512U, // VPMULLWrm 96U, // VPMULLWrr 512U, // VPMULTISHIFTQBZ128rm 4224U, // VPMULTISHIFTQBZ128rmb 1837348U, // VPMULTISHIFTQBZ128rmbk 1869924U, // VPMULTISHIFTQBZ128rmbkz 559396U, // VPMULTISHIFTQBZ128rmk 591972U, // VPMULTISHIFTQBZ128rmkz 96U, // VPMULTISHIFTQBZ128rr 166180U, // VPMULTISHIFTQBZ128rrk 198756U, // VPMULTISHIFTQBZ128rrkz 480U, // VPMULTISHIFTQBZ256rm 6272U, // VPMULTISHIFTQBZ256rmb 2885924U, // VPMULTISHIFTQBZ256rmbk 2918500U, // VPMULTISHIFTQBZ256rmbkz 657700U, // VPMULTISHIFTQBZ256rmk 690276U, // VPMULTISHIFTQBZ256rmkz 96U, // VPMULTISHIFTQBZ256rr 166180U, // VPMULTISHIFTQBZ256rrk 198756U, // VPMULTISHIFTQBZ256rrkz 544U, // VPMULTISHIFTQBZrm 8320U, // VPMULTISHIFTQBZrmb 3934500U, // VPMULTISHIFTQBZrmbk 3967076U, // VPMULTISHIFTQBZrmbkz 723236U, // VPMULTISHIFTQBZrmk 755812U, // VPMULTISHIFTQBZrmkz 96U, // VPMULTISHIFTQBZrr 166180U, // VPMULTISHIFTQBZrrk 198756U, // VPMULTISHIFTQBZrrkz 480U, // VPMULUDQYrm 96U, // VPMULUDQYrr 512U, // VPMULUDQZ128rm 4224U, // VPMULUDQZ128rmb 1837348U, // VPMULUDQZ128rmbk 1869924U, // VPMULUDQZ128rmbkz 559396U, // VPMULUDQZ128rmk 591972U, // VPMULUDQZ128rmkz 96U, // VPMULUDQZ128rr 166180U, // VPMULUDQZ128rrk 198756U, // VPMULUDQZ128rrkz 480U, // VPMULUDQZ256rm 6272U, // VPMULUDQZ256rmb 2885924U, // VPMULUDQZ256rmbk 2918500U, // VPMULUDQZ256rmbkz 657700U, // VPMULUDQZ256rmk 690276U, // VPMULUDQZ256rmkz 96U, // VPMULUDQZ256rr 166180U, // VPMULUDQZ256rrk 198756U, // VPMULUDQZ256rrkz 544U, // VPMULUDQZrm 8320U, // VPMULUDQZrmb 3934500U, // VPMULUDQZrmbk 3967076U, // VPMULUDQZrmbkz 723236U, // VPMULUDQZrmk 755812U, // VPMULUDQZrmkz 96U, // VPMULUDQZrr 166180U, // VPMULUDQZrrk 198756U, // VPMULUDQZrrkz 512U, // VPMULUDQrm 96U, // VPMULUDQrr 0U, // VPOPCNTBZ128rm 676U, // VPOPCNTBZ128rmk 516U, // VPOPCNTBZ128rmkz 0U, // VPOPCNTBZ128rr 292U, // VPOPCNTBZ128rrk 100U, // VPOPCNTBZ128rrkz 0U, // VPOPCNTBZ256rm 708U, // VPOPCNTBZ256rmk 484U, // VPOPCNTBZ256rmkz 0U, // VPOPCNTBZ256rr 292U, // VPOPCNTBZ256rrk 100U, // VPOPCNTBZ256rrkz 0U, // VPOPCNTBZrm 996U, // VPOPCNTBZrmk 548U, // VPOPCNTBZrmkz 0U, // VPOPCNTBZrr 292U, // VPOPCNTBZrrk 100U, // VPOPCNTBZrrkz 0U, // VPOPCNTDZ128rm 9U, // VPOPCNTDZ128rmb 7108U, // VPOPCNTDZ128rmbk 6212U, // VPOPCNTDZ128rmbkz 676U, // VPOPCNTDZ128rmk 516U, // VPOPCNTDZ128rmkz 0U, // VPOPCNTDZ128rr 292U, // VPOPCNTDZ128rrk 100U, // VPOPCNTDZ128rrkz 0U, // VPOPCNTDZ256rm 10U, // VPOPCNTDZ256rmb 9156U, // VPOPCNTDZ256rmbk 8260U, // VPOPCNTDZ256rmbkz 708U, // VPOPCNTDZ256rmk 484U, // VPOPCNTDZ256rmkz 0U, // VPOPCNTDZ256rr 292U, // VPOPCNTDZ256rrk 100U, // VPOPCNTDZ256rrkz 0U, // VPOPCNTDZrm 10U, // VPOPCNTDZrmb 11204U, // VPOPCNTDZrmbk 10308U, // VPOPCNTDZrmbkz 996U, // VPOPCNTDZrmk 548U, // VPOPCNTDZrmkz 0U, // VPOPCNTDZrr 292U, // VPOPCNTDZrrk 100U, // VPOPCNTDZrrkz 0U, // VPOPCNTQZ128rm 9U, // VPOPCNTQZ128rmb 4740U, // VPOPCNTQZ128rmbk 4228U, // VPOPCNTQZ128rmbkz 676U, // VPOPCNTQZ128rmk 516U, // VPOPCNTQZ128rmkz 0U, // VPOPCNTQZ128rr 292U, // VPOPCNTQZ128rrk 100U, // VPOPCNTQZ128rrkz 0U, // VPOPCNTQZ256rm 9U, // VPOPCNTQZ256rmb 6788U, // VPOPCNTQZ256rmbk 6276U, // VPOPCNTQZ256rmbkz 708U, // VPOPCNTQZ256rmk 484U, // VPOPCNTQZ256rmkz 0U, // VPOPCNTQZ256rr 292U, // VPOPCNTQZ256rrk 100U, // VPOPCNTQZ256rrkz 0U, // VPOPCNTQZrm 10U, // VPOPCNTQZrmb 8836U, // VPOPCNTQZrmbk 8324U, // VPOPCNTQZrmbkz 996U, // VPOPCNTQZrmk 548U, // VPOPCNTQZrmkz 0U, // VPOPCNTQZrr 292U, // VPOPCNTQZrrk 100U, // VPOPCNTQZrrkz 0U, // VPOPCNTWZ128rm 676U, // VPOPCNTWZ128rmk 516U, // VPOPCNTWZ128rmkz 0U, // VPOPCNTWZ128rr 292U, // VPOPCNTWZ128rrk 100U, // VPOPCNTWZ128rrkz 0U, // VPOPCNTWZ256rm 708U, // VPOPCNTWZ256rmk 484U, // VPOPCNTWZ256rmkz 0U, // VPOPCNTWZ256rr 292U, // VPOPCNTWZ256rrk 100U, // VPOPCNTWZ256rrkz 0U, // VPOPCNTWZrm 996U, // VPOPCNTWZrmk 548U, // VPOPCNTWZrmkz 0U, // VPOPCNTWZrr 292U, // VPOPCNTWZrrk 100U, // VPOPCNTWZrrkz 512U, // VPORDZ128rm 6208U, // VPORDZ128rmb 2591012U, // VPORDZ128rmbk 2623588U, // VPORDZ128rmbkz 559396U, // VPORDZ128rmk 591972U, // VPORDZ128rmkz 96U, // VPORDZ128rr 166180U, // VPORDZ128rrk 198756U, // VPORDZ128rrkz 480U, // VPORDZ256rm 8256U, // VPORDZ256rmb 3639588U, // VPORDZ256rmbk 3672164U, // VPORDZ256rmbkz 657700U, // VPORDZ256rmk 690276U, // VPORDZ256rmkz 96U, // VPORDZ256rr 166180U, // VPORDZ256rrk 198756U, // VPORDZ256rrkz 544U, // VPORDZrm 10304U, // VPORDZrmb 5736740U, // VPORDZrmbk 5769316U, // VPORDZrmbkz 723236U, // VPORDZrmk 755812U, // VPORDZrmkz 96U, // VPORDZrr 166180U, // VPORDZrrk 198756U, // VPORDZrrkz 512U, // VPORQZ128rm 4224U, // VPORQZ128rmb 1837348U, // VPORQZ128rmbk 1869924U, // VPORQZ128rmbkz 559396U, // VPORQZ128rmk 591972U, // VPORQZ128rmkz 96U, // VPORQZ128rr 166180U, // VPORQZ128rrk 198756U, // VPORQZ128rrkz 480U, // VPORQZ256rm 6272U, // VPORQZ256rmb 2885924U, // VPORQZ256rmbk 2918500U, // VPORQZ256rmbkz 657700U, // VPORQZ256rmk 690276U, // VPORQZ256rmkz 96U, // VPORQZ256rr 166180U, // VPORQZ256rrk 198756U, // VPORQZ256rrkz 544U, // VPORQZrm 8320U, // VPORQZrmb 3934500U, // VPORQZrmbk 3967076U, // VPORQZrmbkz 723236U, // VPORQZrmk 755812U, // VPORQZrmkz 96U, // VPORQZrr 166180U, // VPORQZrrk 198756U, // VPORQZrrkz 480U, // VPORYrm 96U, // VPORYrr 512U, // VPORrm 96U, // VPORrr 854528U, // VPPERMrmr 591968U, // VPPERMrrm 198752U, // VPPERMrrr 198752U, // VPPERMrrr_REV 12U, // VPROLDZ128mbi 930756U, // VPROLDZ128mbik 471108U, // VPROLDZ128mbikz 0U, // VPROLDZ128mi 920228U, // VPROLDZ128mik 461316U, // VPROLDZ128mikz 32U, // VPROLDZ128ri 2340U, // VPROLDZ128rik 624740U, // VPROLDZ128rikz 12U, // VPROLDZ256mbi 932804U, // VPROLDZ256mbik 473156U, // VPROLDZ256mbikz 0U, // VPROLDZ256mi 920260U, // VPROLDZ256mik 461284U, // VPROLDZ256mikz 32U, // VPROLDZ256ri 2340U, // VPROLDZ256rik 624740U, // VPROLDZ256rikz 13U, // VPROLDZmbi 934852U, // VPROLDZmbik 475204U, // VPROLDZmbikz 0U, // VPROLDZmi 920548U, // VPROLDZmik 461348U, // VPROLDZmikz 32U, // VPROLDZri 2340U, // VPROLDZrik 624740U, // VPROLDZrikz 11U, // VPROLQZ128mbi 936580U, // VPROLQZ128mbik 477316U, // VPROLQZ128mbikz 0U, // VPROLQZ128mi 920228U, // VPROLQZ128mik 461316U, // VPROLQZ128mikz 32U, // VPROLQZ128ri 2340U, // VPROLQZ128rik 624740U, // VPROLQZ128rikz 12U, // VPROLQZ256mbi 930436U, // VPROLQZ256mbik 471172U, // VPROLQZ256mbikz 0U, // VPROLQZ256mi 920260U, // VPROLQZ256mik 461284U, // VPROLQZ256mikz 32U, // VPROLQZ256ri 2340U, // VPROLQZ256rik 624740U, // VPROLQZ256rikz 12U, // VPROLQZmbi 932484U, // VPROLQZmbik 473220U, // VPROLQZmbikz 0U, // VPROLQZmi 920548U, // VPROLQZmik 461348U, // VPROLQZmikz 32U, // VPROLQZri 2340U, // VPROLQZrik 624740U, // VPROLQZrikz 512U, // VPROLVDZ128rm 6208U, // VPROLVDZ128rmb 2591012U, // VPROLVDZ128rmbk 2623588U, // VPROLVDZ128rmbkz 559396U, // VPROLVDZ128rmk 591972U, // VPROLVDZ128rmkz 96U, // VPROLVDZ128rr 166180U, // VPROLVDZ128rrk 198756U, // VPROLVDZ128rrkz 480U, // VPROLVDZ256rm 8256U, // VPROLVDZ256rmb 3639588U, // VPROLVDZ256rmbk 3672164U, // VPROLVDZ256rmbkz 657700U, // VPROLVDZ256rmk 690276U, // VPROLVDZ256rmkz 96U, // VPROLVDZ256rr 166180U, // VPROLVDZ256rrk 198756U, // VPROLVDZ256rrkz 544U, // VPROLVDZrm 10304U, // VPROLVDZrmb 5736740U, // VPROLVDZrmbk 5769316U, // VPROLVDZrmbkz 723236U, // VPROLVDZrmk 755812U, // VPROLVDZrmkz 96U, // VPROLVDZrr 166180U, // VPROLVDZrrk 198756U, // VPROLVDZrrkz 512U, // VPROLVQZ128rm 4224U, // VPROLVQZ128rmb 1837348U, // VPROLVQZ128rmbk 1869924U, // VPROLVQZ128rmbkz 559396U, // VPROLVQZ128rmk 591972U, // VPROLVQZ128rmkz 96U, // VPROLVQZ128rr 166180U, // VPROLVQZ128rrk 198756U, // VPROLVQZ128rrkz 480U, // VPROLVQZ256rm 6272U, // VPROLVQZ256rmb 2885924U, // VPROLVQZ256rmbk 2918500U, // VPROLVQZ256rmbkz 657700U, // VPROLVQZ256rmk 690276U, // VPROLVQZ256rmkz 96U, // VPROLVQZ256rr 166180U, // VPROLVQZ256rrk 198756U, // VPROLVQZ256rrkz 544U, // VPROLVQZrm 8320U, // VPROLVQZrmb 3934500U, // VPROLVQZrmbk 3967076U, // VPROLVQZrmbkz 723236U, // VPROLVQZrmk 755812U, // VPROLVQZrmkz 96U, // VPROLVQZrr 166180U, // VPROLVQZrrk 198756U, // VPROLVQZrrkz 12U, // VPRORDZ128mbi 930756U, // VPRORDZ128mbik 471108U, // VPRORDZ128mbikz 0U, // VPRORDZ128mi 920228U, // VPRORDZ128mik 461316U, // VPRORDZ128mikz 32U, // VPRORDZ128ri 2340U, // VPRORDZ128rik 624740U, // VPRORDZ128rikz 12U, // VPRORDZ256mbi 932804U, // VPRORDZ256mbik 473156U, // VPRORDZ256mbikz 0U, // VPRORDZ256mi 920260U, // VPRORDZ256mik 461284U, // VPRORDZ256mikz 32U, // VPRORDZ256ri 2340U, // VPRORDZ256rik 624740U, // VPRORDZ256rikz 13U, // VPRORDZmbi 934852U, // VPRORDZmbik 475204U, // VPRORDZmbikz 0U, // VPRORDZmi 920548U, // VPRORDZmik 461348U, // VPRORDZmikz 32U, // VPRORDZri 2340U, // VPRORDZrik 624740U, // VPRORDZrikz 11U, // VPRORQZ128mbi 936580U, // VPRORQZ128mbik 477316U, // VPRORQZ128mbikz 0U, // VPRORQZ128mi 920228U, // VPRORQZ128mik 461316U, // VPRORQZ128mikz 32U, // VPRORQZ128ri 2340U, // VPRORQZ128rik 624740U, // VPRORQZ128rikz 12U, // VPRORQZ256mbi 930436U, // VPRORQZ256mbik 471172U, // VPRORQZ256mbikz 0U, // VPRORQZ256mi 920260U, // VPRORQZ256mik 461284U, // VPRORQZ256mikz 32U, // VPRORQZ256ri 2340U, // VPRORQZ256rik 624740U, // VPRORQZ256rikz 12U, // VPRORQZmbi 932484U, // VPRORQZmbik 473220U, // VPRORQZmbikz 0U, // VPRORQZmi 920548U, // VPRORQZmik 461348U, // VPRORQZmikz 32U, // VPRORQZri 2340U, // VPRORQZrik 624740U, // VPRORQZrikz 512U, // VPRORVDZ128rm 6208U, // VPRORVDZ128rmb 2591012U, // VPRORVDZ128rmbk 2623588U, // VPRORVDZ128rmbkz 559396U, // VPRORVDZ128rmk 591972U, // VPRORVDZ128rmkz 96U, // VPRORVDZ128rr 166180U, // VPRORVDZ128rrk 198756U, // VPRORVDZ128rrkz 480U, // VPRORVDZ256rm 8256U, // VPRORVDZ256rmb 3639588U, // VPRORVDZ256rmbk 3672164U, // VPRORVDZ256rmbkz 657700U, // VPRORVDZ256rmk 690276U, // VPRORVDZ256rmkz 96U, // VPRORVDZ256rr 166180U, // VPRORVDZ256rrk 198756U, // VPRORVDZ256rrkz 544U, // VPRORVDZrm 10304U, // VPRORVDZrmb 5736740U, // VPRORVDZrmbk 5769316U, // VPRORVDZrmbkz 723236U, // VPRORVDZrmk 755812U, // VPRORVDZrmkz 96U, // VPRORVDZrr 166180U, // VPRORVDZrrk 198756U, // VPRORVDZrrkz 512U, // VPRORVQZ128rm 4224U, // VPRORVQZ128rmb 1837348U, // VPRORVQZ128rmbk 1869924U, // VPRORVQZ128rmbkz 559396U, // VPRORVQZ128rmk 591972U, // VPRORVQZ128rmkz 96U, // VPRORVQZ128rr 166180U, // VPRORVQZ128rrk 198756U, // VPRORVQZ128rrkz 480U, // VPRORVQZ256rm 6272U, // VPRORVQZ256rmb 2885924U, // VPRORVQZ256rmbk 2918500U, // VPRORVQZ256rmbkz 657700U, // VPRORVQZ256rmk 690276U, // VPRORVQZ256rmkz 96U, // VPRORVQZ256rr 166180U, // VPRORVQZ256rrk 198756U, // VPRORVQZ256rrkz 544U, // VPRORVQZrm 8320U, // VPRORVQZrmb 3934500U, // VPRORVQZrmbk 3967076U, // VPRORVQZrmbkz 723236U, // VPRORVQZrmk 755812U, // VPRORVQZrmkz 96U, // VPRORVQZrr 166180U, // VPRORVQZrrk 198756U, // VPRORVQZrrkz 0U, // VPROTBmi 160U, // VPROTBmr 32U, // VPROTBri 512U, // VPROTBrm 96U, // VPROTBrr 96U, // VPROTBrr_REV 0U, // VPROTDmi 160U, // VPROTDmr 32U, // VPROTDri 512U, // VPROTDrm 96U, // VPROTDrr 96U, // VPROTDrr_REV 0U, // VPROTQmi 160U, // VPROTQmr 32U, // VPROTQri 512U, // VPROTQrm 96U, // VPROTQrr 96U, // VPROTQrr_REV 0U, // VPROTWmi 160U, // VPROTWmr 32U, // VPROTWri 512U, // VPROTWrm 96U, // VPROTWrr 96U, // VPROTWrr_REV 480U, // VPSADBWYrm 96U, // VPSADBWYrr 512U, // VPSADBWZ128rm 96U, // VPSADBWZ128rr 480U, // VPSADBWZ256rm 96U, // VPSADBWZ256rr 544U, // VPSADBWZrm 96U, // VPSADBWZrr 512U, // VPSADBWrm 96U, // VPSADBWrr 0U, // VPSCATTERDDZ128mr 0U, // VPSCATTERDDZ256mr 0U, // VPSCATTERDDZmr 0U, // VPSCATTERDQZ128mr 0U, // VPSCATTERDQZ256mr 0U, // VPSCATTERDQZmr 0U, // VPSCATTERQDZ128mr 0U, // VPSCATTERQDZ256mr 0U, // VPSCATTERQDZmr 0U, // VPSCATTERQQZ128mr 0U, // VPSCATTERQQZ256mr 0U, // VPSCATTERQQZmr 160U, // VPSHABmr 512U, // VPSHABrm 96U, // VPSHABrr 96U, // VPSHABrr_REV 160U, // VPSHADmr 512U, // VPSHADrm 96U, // VPSHADrr 96U, // VPSHADrr_REV 160U, // VPSHAQmr 512U, // VPSHAQrm 96U, // VPSHAQrr 96U, // VPSHAQrr_REV 160U, // VPSHAWmr 512U, // VPSHAWrm 96U, // VPSHAWrr 96U, // VPSHAWrr_REV 160U, // VPSHLBmr 512U, // VPSHLBrm 96U, // VPSHLBrr 96U, // VPSHLBrr_REV 471104U, // VPSHLDDZ128rmbi 40339748U, // VPSHLDDZ128rmbik 57149540U, // VPSHLDDZ128rmbikz 461312U, // VPSHLDDZ128rmi 38308132U, // VPSHLDDZ128rmik 55117924U, // VPSHLDDZ128rmikz 624736U, // VPSHLDDZ128rri 71469348U, // VPSHLDDZ128rrik 88279140U, // VPSHLDDZ128rrikz 473152U, // VPSHLDDZ256rmbi 41388324U, // VPSHLDDZ256rmbik 58198116U, // VPSHLDDZ256rmbikz 461280U, // VPSHLDDZ256rmi 38406436U, // VPSHLDDZ256rmik 55216228U, // VPSHLDDZ256rmikz 624736U, // VPSHLDDZ256rri 71469348U, // VPSHLDDZ256rrik 88279140U, // VPSHLDDZ256rrikz 475200U, // VPSHLDDZrmbi 42436900U, // VPSHLDDZrmbik 59246692U, // VPSHLDDZrmbikz 461344U, // VPSHLDDZrmi 38471972U, // VPSHLDDZrmik 55281764U, // VPSHLDDZrmikz 624736U, // VPSHLDDZrri 71469348U, // VPSHLDDZrrik 88279140U, // VPSHLDDZrrikz 477312U, // VPSHLDQZ128rmbi 43780388U, // VPSHLDQZ128rmbik 60590180U, // VPSHLDQZ128rmbikz 461312U, // VPSHLDQZ128rmi 38308132U, // VPSHLDQZ128rmik 55117924U, // VPSHLDQZ128rmikz 624736U, // VPSHLDQZ128rri 71469348U, // VPSHLDQZ128rrik 88279140U, // VPSHLDQZ128rrikz 471168U, // VPSHLDQZ256rmbi 40634660U, // VPSHLDQZ256rmbik 57444452U, // VPSHLDQZ256rmbikz 461280U, // VPSHLDQZ256rmi 38406436U, // VPSHLDQZ256rmik 55216228U, // VPSHLDQZ256rmikz 624736U, // VPSHLDQZ256rri 71469348U, // VPSHLDQZ256rrik 88279140U, // VPSHLDQZ256rrikz 473216U, // VPSHLDQZrmbi 41683236U, // VPSHLDQZrmbik 58493028U, // VPSHLDQZrmbikz 461344U, // VPSHLDQZrmi 38471972U, // VPSHLDQZrmik 55281764U, // VPSHLDQZrmikz 624736U, // VPSHLDQZrri 71469348U, // VPSHLDQZrrik 88279140U, // VPSHLDQZrrikz 672U, // VPSHLDVDZ128m 7104U, // VPSHLDVDZ128mb 2591012U, // VPSHLDVDZ128mbk 2591012U, // VPSHLDVDZ128mbkz 559396U, // VPSHLDVDZ128mk 559396U, // VPSHLDVDZ128mkz 288U, // VPSHLDVDZ128r 166180U, // VPSHLDVDZ128rk 166180U, // VPSHLDVDZ128rkz 704U, // VPSHLDVDZ256m 9152U, // VPSHLDVDZ256mb 3639588U, // VPSHLDVDZ256mbk 3639588U, // VPSHLDVDZ256mbkz 657700U, // VPSHLDVDZ256mk 657700U, // VPSHLDVDZ256mkz 288U, // VPSHLDVDZ256r 166180U, // VPSHLDVDZ256rk 166180U, // VPSHLDVDZ256rkz 992U, // VPSHLDVDZm 11200U, // VPSHLDVDZmb 5736740U, // VPSHLDVDZmbk 5736740U, // VPSHLDVDZmbkz 723236U, // VPSHLDVDZmk 723236U, // VPSHLDVDZmkz 288U, // VPSHLDVDZr 166180U, // VPSHLDVDZrk 166180U, // VPSHLDVDZrkz 672U, // VPSHLDVQZ128m 4736U, // VPSHLDVQZ128mb 1837348U, // VPSHLDVQZ128mbk 1837348U, // VPSHLDVQZ128mbkz 559396U, // VPSHLDVQZ128mk 559396U, // VPSHLDVQZ128mkz 288U, // VPSHLDVQZ128r 166180U, // VPSHLDVQZ128rk 166180U, // VPSHLDVQZ128rkz 704U, // VPSHLDVQZ256m 6784U, // VPSHLDVQZ256mb 2885924U, // VPSHLDVQZ256mbk 2885924U, // VPSHLDVQZ256mbkz 657700U, // VPSHLDVQZ256mk 657700U, // VPSHLDVQZ256mkz 288U, // VPSHLDVQZ256r 166180U, // VPSHLDVQZ256rk 166180U, // VPSHLDVQZ256rkz 992U, // VPSHLDVQZm 8832U, // VPSHLDVQZmb 3934500U, // VPSHLDVQZmbk 3934500U, // VPSHLDVQZmbkz 723236U, // VPSHLDVQZmk 723236U, // VPSHLDVQZmkz 288U, // VPSHLDVQZr 166180U, // VPSHLDVQZrk 166180U, // VPSHLDVQZrkz 672U, // VPSHLDVWZ128m 559396U, // VPSHLDVWZ128mk 559396U, // VPSHLDVWZ128mkz 288U, // VPSHLDVWZ128r 166180U, // VPSHLDVWZ128rk 166180U, // VPSHLDVWZ128rkz 704U, // VPSHLDVWZ256m 657700U, // VPSHLDVWZ256mk 657700U, // VPSHLDVWZ256mkz 288U, // VPSHLDVWZ256r 166180U, // VPSHLDVWZ256rk 166180U, // VPSHLDVWZ256rkz 992U, // VPSHLDVWZm 723236U, // VPSHLDVWZmk 723236U, // VPSHLDVWZmkz 288U, // VPSHLDVWZr 166180U, // VPSHLDVWZrk 166180U, // VPSHLDVWZrkz 461312U, // VPSHLDWZ128rmi 38308132U, // VPSHLDWZ128rmik 55117924U, // VPSHLDWZ128rmikz 624736U, // VPSHLDWZ128rri 71469348U, // VPSHLDWZ128rrik 88279140U, // VPSHLDWZ128rrikz 461280U, // VPSHLDWZ256rmi 38406436U, // VPSHLDWZ256rmik 55216228U, // VPSHLDWZ256rmikz 624736U, // VPSHLDWZ256rri 71469348U, // VPSHLDWZ256rrik 88279140U, // VPSHLDWZ256rrikz 461344U, // VPSHLDWZrmi 38471972U, // VPSHLDWZrmik 55281764U, // VPSHLDWZrmikz 624736U, // VPSHLDWZrri 71469348U, // VPSHLDWZrrik 88279140U, // VPSHLDWZrrikz 160U, // VPSHLDmr 512U, // VPSHLDrm 96U, // VPSHLDrr 96U, // VPSHLDrr_REV 160U, // VPSHLQmr 512U, // VPSHLQrm 96U, // VPSHLQrr 96U, // VPSHLQrr_REV 160U, // VPSHLWmr 512U, // VPSHLWrm 96U, // VPSHLWrr 96U, // VPSHLWrr_REV 471104U, // VPSHRDDZ128rmbi 40339748U, // VPSHRDDZ128rmbik 57149540U, // VPSHRDDZ128rmbikz 461312U, // VPSHRDDZ128rmi 38308132U, // VPSHRDDZ128rmik 55117924U, // VPSHRDDZ128rmikz 624736U, // VPSHRDDZ128rri 71469348U, // VPSHRDDZ128rrik 88279140U, // VPSHRDDZ128rrikz 473152U, // VPSHRDDZ256rmbi 41388324U, // VPSHRDDZ256rmbik 58198116U, // VPSHRDDZ256rmbikz 461280U, // VPSHRDDZ256rmi 38406436U, // VPSHRDDZ256rmik 55216228U, // VPSHRDDZ256rmikz 624736U, // VPSHRDDZ256rri 71469348U, // VPSHRDDZ256rrik 88279140U, // VPSHRDDZ256rrikz 475200U, // VPSHRDDZrmbi 42436900U, // VPSHRDDZrmbik 59246692U, // VPSHRDDZrmbikz 461344U, // VPSHRDDZrmi 38471972U, // VPSHRDDZrmik 55281764U, // VPSHRDDZrmikz 624736U, // VPSHRDDZrri 71469348U, // VPSHRDDZrrik 88279140U, // VPSHRDDZrrikz 477312U, // VPSHRDQZ128rmbi 43780388U, // VPSHRDQZ128rmbik 60590180U, // VPSHRDQZ128rmbikz 461312U, // VPSHRDQZ128rmi 38308132U, // VPSHRDQZ128rmik 55117924U, // VPSHRDQZ128rmikz 624736U, // VPSHRDQZ128rri 71469348U, // VPSHRDQZ128rrik 88279140U, // VPSHRDQZ128rrikz 471168U, // VPSHRDQZ256rmbi 40634660U, // VPSHRDQZ256rmbik 57444452U, // VPSHRDQZ256rmbikz 461280U, // VPSHRDQZ256rmi 38406436U, // VPSHRDQZ256rmik 55216228U, // VPSHRDQZ256rmikz 624736U, // VPSHRDQZ256rri 71469348U, // VPSHRDQZ256rrik 88279140U, // VPSHRDQZ256rrikz 473216U, // VPSHRDQZrmbi 41683236U, // VPSHRDQZrmbik 58493028U, // VPSHRDQZrmbikz 461344U, // VPSHRDQZrmi 38471972U, // VPSHRDQZrmik 55281764U, // VPSHRDQZrmikz 624736U, // VPSHRDQZrri 71469348U, // VPSHRDQZrrik 88279140U, // VPSHRDQZrrikz 672U, // VPSHRDVDZ128m 7104U, // VPSHRDVDZ128mb 2591012U, // VPSHRDVDZ128mbk 2591012U, // VPSHRDVDZ128mbkz 559396U, // VPSHRDVDZ128mk 559396U, // VPSHRDVDZ128mkz 288U, // VPSHRDVDZ128r 166180U, // VPSHRDVDZ128rk 166180U, // VPSHRDVDZ128rkz 704U, // VPSHRDVDZ256m 9152U, // VPSHRDVDZ256mb 3639588U, // VPSHRDVDZ256mbk 3639588U, // VPSHRDVDZ256mbkz 657700U, // VPSHRDVDZ256mk 657700U, // VPSHRDVDZ256mkz 288U, // VPSHRDVDZ256r 166180U, // VPSHRDVDZ256rk 166180U, // VPSHRDVDZ256rkz 992U, // VPSHRDVDZm 11200U, // VPSHRDVDZmb 5736740U, // VPSHRDVDZmbk 5736740U, // VPSHRDVDZmbkz 723236U, // VPSHRDVDZmk 723236U, // VPSHRDVDZmkz 288U, // VPSHRDVDZr 166180U, // VPSHRDVDZrk 166180U, // VPSHRDVDZrkz 672U, // VPSHRDVQZ128m 4736U, // VPSHRDVQZ128mb 1837348U, // VPSHRDVQZ128mbk 1837348U, // VPSHRDVQZ128mbkz 559396U, // VPSHRDVQZ128mk 559396U, // VPSHRDVQZ128mkz 288U, // VPSHRDVQZ128r 166180U, // VPSHRDVQZ128rk 166180U, // VPSHRDVQZ128rkz 704U, // VPSHRDVQZ256m 6784U, // VPSHRDVQZ256mb 2885924U, // VPSHRDVQZ256mbk 2885924U, // VPSHRDVQZ256mbkz 657700U, // VPSHRDVQZ256mk 657700U, // VPSHRDVQZ256mkz 288U, // VPSHRDVQZ256r 166180U, // VPSHRDVQZ256rk 166180U, // VPSHRDVQZ256rkz 992U, // VPSHRDVQZm 8832U, // VPSHRDVQZmb 3934500U, // VPSHRDVQZmbk 3934500U, // VPSHRDVQZmbkz 723236U, // VPSHRDVQZmk 723236U, // VPSHRDVQZmkz 288U, // VPSHRDVQZr 166180U, // VPSHRDVQZrk 166180U, // VPSHRDVQZrkz 672U, // VPSHRDVWZ128m 559396U, // VPSHRDVWZ128mk 559396U, // VPSHRDVWZ128mkz 288U, // VPSHRDVWZ128r 166180U, // VPSHRDVWZ128rk 166180U, // VPSHRDVWZ128rkz 704U, // VPSHRDVWZ256m 657700U, // VPSHRDVWZ256mk 657700U, // VPSHRDVWZ256mkz 288U, // VPSHRDVWZ256r 166180U, // VPSHRDVWZ256rk 166180U, // VPSHRDVWZ256rkz 992U, // VPSHRDVWZm 723236U, // VPSHRDVWZmk 723236U, // VPSHRDVWZmkz 288U, // VPSHRDVWZr 166180U, // VPSHRDVWZrk 166180U, // VPSHRDVWZrkz 461312U, // VPSHRDWZ128rmi 38308132U, // VPSHRDWZ128rmik 55117924U, // VPSHRDWZ128rmikz 624736U, // VPSHRDWZ128rri 71469348U, // VPSHRDWZ128rrik 88279140U, // VPSHRDWZ128rrikz 461280U, // VPSHRDWZ256rmi 38406436U, // VPSHRDWZ256rmik 55216228U, // VPSHRDWZ256rmikz 624736U, // VPSHRDWZ256rri 71469348U, // VPSHRDWZ256rrik 88279140U, // VPSHRDWZ256rrikz 461344U, // VPSHRDWZrmi 38471972U, // VPSHRDWZrmik 55281764U, // VPSHRDWZrmikz 624736U, // VPSHRDWZrri 71469348U, // VPSHRDWZrrik 88279140U, // VPSHRDWZrrikz 512U, // VPSHUFBITQMBZ128rm 591972U, // VPSHUFBITQMBZ128rmk 96U, // VPSHUFBITQMBZ128rr 198756U, // VPSHUFBITQMBZ128rrk 480U, // VPSHUFBITQMBZ256rm 690276U, // VPSHUFBITQMBZ256rmk 96U, // VPSHUFBITQMBZ256rr 198756U, // VPSHUFBITQMBZ256rrk 544U, // VPSHUFBITQMBZrm 755812U, // VPSHUFBITQMBZrmk 96U, // VPSHUFBITQMBZrr 198756U, // VPSHUFBITQMBZrrk 480U, // VPSHUFBYrm 96U, // VPSHUFBYrr 512U, // VPSHUFBZ128rm 559396U, // VPSHUFBZ128rmk 591972U, // VPSHUFBZ128rmkz 96U, // VPSHUFBZ128rr 166180U, // VPSHUFBZ128rrk 198756U, // VPSHUFBZ128rrkz 480U, // VPSHUFBZ256rm 657700U, // VPSHUFBZ256rmk 690276U, // VPSHUFBZ256rmkz 96U, // VPSHUFBZ256rr 166180U, // VPSHUFBZ256rrk 198756U, // VPSHUFBZ256rrkz 544U, // VPSHUFBZrm 723236U, // VPSHUFBZrmk 755812U, // VPSHUFBZrmkz 96U, // VPSHUFBZrr 166180U, // VPSHUFBZrrk 198756U, // VPSHUFBZrrkz 512U, // VPSHUFBrm 96U, // VPSHUFBrr 0U, // VPSHUFDYmi 32U, // VPSHUFDYri 12U, // VPSHUFDZ128mbi 930756U, // VPSHUFDZ128mbik 471108U, // VPSHUFDZ128mbikz 0U, // VPSHUFDZ128mi 920228U, // VPSHUFDZ128mik 461316U, // VPSHUFDZ128mikz 32U, // VPSHUFDZ128ri 2340U, // VPSHUFDZ128rik 624740U, // VPSHUFDZ128rikz 12U, // VPSHUFDZ256mbi 932804U, // VPSHUFDZ256mbik 473156U, // VPSHUFDZ256mbikz 0U, // VPSHUFDZ256mi 920260U, // VPSHUFDZ256mik 461284U, // VPSHUFDZ256mikz 32U, // VPSHUFDZ256ri 2340U, // VPSHUFDZ256rik 624740U, // VPSHUFDZ256rikz 13U, // VPSHUFDZmbi 934852U, // VPSHUFDZmbik 475204U, // VPSHUFDZmbikz 0U, // VPSHUFDZmi 920548U, // VPSHUFDZmik 461348U, // VPSHUFDZmikz 32U, // VPSHUFDZri 2340U, // VPSHUFDZrik 624740U, // VPSHUFDZrikz 0U, // VPSHUFDmi 32U, // VPSHUFDri 0U, // VPSHUFHWYmi 32U, // VPSHUFHWYri 0U, // VPSHUFHWZ128mi 920228U, // VPSHUFHWZ128mik 461316U, // VPSHUFHWZ128mikz 32U, // VPSHUFHWZ128ri 2340U, // VPSHUFHWZ128rik 624740U, // VPSHUFHWZ128rikz 0U, // VPSHUFHWZ256mi 920260U, // VPSHUFHWZ256mik 461284U, // VPSHUFHWZ256mikz 32U, // VPSHUFHWZ256ri 2340U, // VPSHUFHWZ256rik 624740U, // VPSHUFHWZ256rikz 0U, // VPSHUFHWZmi 920548U, // VPSHUFHWZmik 461348U, // VPSHUFHWZmikz 32U, // VPSHUFHWZri 2340U, // VPSHUFHWZrik 624740U, // VPSHUFHWZrikz 0U, // VPSHUFHWmi 32U, // VPSHUFHWri 0U, // VPSHUFLWYmi 32U, // VPSHUFLWYri 0U, // VPSHUFLWZ128mi 920228U, // VPSHUFLWZ128mik 461316U, // VPSHUFLWZ128mikz 32U, // VPSHUFLWZ128ri 2340U, // VPSHUFLWZ128rik 624740U, // VPSHUFLWZ128rikz 0U, // VPSHUFLWZ256mi 920260U, // VPSHUFLWZ256mik 461284U, // VPSHUFLWZ256mikz 32U, // VPSHUFLWZ256ri 2340U, // VPSHUFLWZ256rik 624740U, // VPSHUFLWZ256rikz 0U, // VPSHUFLWZmi 920548U, // VPSHUFLWZmik 461348U, // VPSHUFLWZmikz 32U, // VPSHUFLWZri 2340U, // VPSHUFLWZrik 624740U, // VPSHUFLWZrikz 0U, // VPSHUFLWmi 32U, // VPSHUFLWri 480U, // VPSIGNBYrm 96U, // VPSIGNBYrr 512U, // VPSIGNBrm 96U, // VPSIGNBrr 480U, // VPSIGNDYrm 96U, // VPSIGNDYrr 512U, // VPSIGNDrm 96U, // VPSIGNDrr 480U, // VPSIGNWYrm 96U, // VPSIGNWYrr 512U, // VPSIGNWrm 96U, // VPSIGNWrr 32U, // VPSLLDQYri 0U, // VPSLLDQZ128rm 32U, // VPSLLDQZ128rr 0U, // VPSLLDQZ256rm 32U, // VPSLLDQZ256rr 0U, // VPSLLDQZrm 32U, // VPSLLDQZrr 32U, // VPSLLDQri 32U, // VPSLLDYri 512U, // VPSLLDYrm 96U, // VPSLLDYrr 12U, // VPSLLDZ128mbi 930756U, // VPSLLDZ128mbik 471108U, // VPSLLDZ128mbikz 0U, // VPSLLDZ128mi 920228U, // VPSLLDZ128mik 461316U, // VPSLLDZ128mikz 32U, // VPSLLDZ128ri 2340U, // VPSLLDZ128rik 624740U, // VPSLLDZ128rikz 512U, // VPSLLDZ128rm 559396U, // VPSLLDZ128rmk 591972U, // VPSLLDZ128rmkz 96U, // VPSLLDZ128rr 166180U, // VPSLLDZ128rrk 198756U, // VPSLLDZ128rrkz 12U, // VPSLLDZ256mbi 932804U, // VPSLLDZ256mbik 473156U, // VPSLLDZ256mbikz 0U, // VPSLLDZ256mi 920260U, // VPSLLDZ256mik 461284U, // VPSLLDZ256mikz 32U, // VPSLLDZ256ri 2340U, // VPSLLDZ256rik 624740U, // VPSLLDZ256rikz 512U, // VPSLLDZ256rm 559396U, // VPSLLDZ256rmk 591972U, // VPSLLDZ256rmkz 96U, // VPSLLDZ256rr 166180U, // VPSLLDZ256rrk 198756U, // VPSLLDZ256rrkz 13U, // VPSLLDZmbi 934852U, // VPSLLDZmbik 475204U, // VPSLLDZmbikz 0U, // VPSLLDZmi 920548U, // VPSLLDZmik 461348U, // VPSLLDZmikz 32U, // VPSLLDZri 2340U, // VPSLLDZrik 624740U, // VPSLLDZrikz 512U, // VPSLLDZrm 559396U, // VPSLLDZrmk 591972U, // VPSLLDZrmkz 96U, // VPSLLDZrr 166180U, // VPSLLDZrrk 198756U, // VPSLLDZrrkz 32U, // VPSLLDri 512U, // VPSLLDrm 96U, // VPSLLDrr 32U, // VPSLLQYri 512U, // VPSLLQYrm 96U, // VPSLLQYrr 11U, // VPSLLQZ128mbi 936580U, // VPSLLQZ128mbik 477316U, // VPSLLQZ128mbikz 0U, // VPSLLQZ128mi 920228U, // VPSLLQZ128mik 461316U, // VPSLLQZ128mikz 32U, // VPSLLQZ128ri 2340U, // VPSLLQZ128rik 624740U, // VPSLLQZ128rikz 512U, // VPSLLQZ128rm 559396U, // VPSLLQZ128rmk 591972U, // VPSLLQZ128rmkz 96U, // VPSLLQZ128rr 166180U, // VPSLLQZ128rrk 198756U, // VPSLLQZ128rrkz 12U, // VPSLLQZ256mbi 930436U, // VPSLLQZ256mbik 471172U, // VPSLLQZ256mbikz 0U, // VPSLLQZ256mi 920260U, // VPSLLQZ256mik 461284U, // VPSLLQZ256mikz 32U, // VPSLLQZ256ri 2340U, // VPSLLQZ256rik 624740U, // VPSLLQZ256rikz 512U, // VPSLLQZ256rm 559396U, // VPSLLQZ256rmk 591972U, // VPSLLQZ256rmkz 96U, // VPSLLQZ256rr 166180U, // VPSLLQZ256rrk 198756U, // VPSLLQZ256rrkz 12U, // VPSLLQZmbi 932484U, // VPSLLQZmbik 473220U, // VPSLLQZmbikz 0U, // VPSLLQZmi 920548U, // VPSLLQZmik 461348U, // VPSLLQZmikz 32U, // VPSLLQZri 2340U, // VPSLLQZrik 624740U, // VPSLLQZrikz 512U, // VPSLLQZrm 559396U, // VPSLLQZrmk 591972U, // VPSLLQZrmkz 96U, // VPSLLQZrr 166180U, // VPSLLQZrrk 198756U, // VPSLLQZrrkz 32U, // VPSLLQri 512U, // VPSLLQrm 96U, // VPSLLQrr 480U, // VPSLLVDYrm 96U, // VPSLLVDYrr 512U, // VPSLLVDZ128rm 6208U, // VPSLLVDZ128rmb 2591012U, // VPSLLVDZ128rmbk 2623588U, // VPSLLVDZ128rmbkz 559396U, // VPSLLVDZ128rmk 591972U, // VPSLLVDZ128rmkz 96U, // VPSLLVDZ128rr 166180U, // VPSLLVDZ128rrk 198756U, // VPSLLVDZ128rrkz 480U, // VPSLLVDZ256rm 8256U, // VPSLLVDZ256rmb 3639588U, // VPSLLVDZ256rmbk 3672164U, // VPSLLVDZ256rmbkz 657700U, // VPSLLVDZ256rmk 690276U, // VPSLLVDZ256rmkz 96U, // VPSLLVDZ256rr 166180U, // VPSLLVDZ256rrk 198756U, // VPSLLVDZ256rrkz 544U, // VPSLLVDZrm 10304U, // VPSLLVDZrmb 5736740U, // VPSLLVDZrmbk 5769316U, // VPSLLVDZrmbkz 723236U, // VPSLLVDZrmk 755812U, // VPSLLVDZrmkz 96U, // VPSLLVDZrr 166180U, // VPSLLVDZrrk 198756U, // VPSLLVDZrrkz 512U, // VPSLLVDrm 96U, // VPSLLVDrr 480U, // VPSLLVQYrm 96U, // VPSLLVQYrr 512U, // VPSLLVQZ128rm 4224U, // VPSLLVQZ128rmb 1837348U, // VPSLLVQZ128rmbk 1869924U, // VPSLLVQZ128rmbkz 559396U, // VPSLLVQZ128rmk 591972U, // VPSLLVQZ128rmkz 96U, // VPSLLVQZ128rr 166180U, // VPSLLVQZ128rrk 198756U, // VPSLLVQZ128rrkz 480U, // VPSLLVQZ256rm 6272U, // VPSLLVQZ256rmb 2885924U, // VPSLLVQZ256rmbk 2918500U, // VPSLLVQZ256rmbkz 657700U, // VPSLLVQZ256rmk 690276U, // VPSLLVQZ256rmkz 96U, // VPSLLVQZ256rr 166180U, // VPSLLVQZ256rrk 198756U, // VPSLLVQZ256rrkz 544U, // VPSLLVQZrm 8320U, // VPSLLVQZrmb 3934500U, // VPSLLVQZrmbk 3967076U, // VPSLLVQZrmbkz 723236U, // VPSLLVQZrmk 755812U, // VPSLLVQZrmkz 96U, // VPSLLVQZrr 166180U, // VPSLLVQZrrk 198756U, // VPSLLVQZrrkz 512U, // VPSLLVQrm 96U, // VPSLLVQrr 512U, // VPSLLVWZ128rm 559396U, // VPSLLVWZ128rmk 591972U, // VPSLLVWZ128rmkz 96U, // VPSLLVWZ128rr 166180U, // VPSLLVWZ128rrk 198756U, // VPSLLVWZ128rrkz 480U, // VPSLLVWZ256rm 657700U, // VPSLLVWZ256rmk 690276U, // VPSLLVWZ256rmkz 96U, // VPSLLVWZ256rr 166180U, // VPSLLVWZ256rrk 198756U, // VPSLLVWZ256rrkz 544U, // VPSLLVWZrm 723236U, // VPSLLVWZrmk 755812U, // VPSLLVWZrmkz 96U, // VPSLLVWZrr 166180U, // VPSLLVWZrrk 198756U, // VPSLLVWZrrkz 32U, // VPSLLWYri 512U, // VPSLLWYrm 96U, // VPSLLWYrr 0U, // VPSLLWZ128mi 920228U, // VPSLLWZ128mik 461316U, // VPSLLWZ128mikz 32U, // VPSLLWZ128ri 2340U, // VPSLLWZ128rik 624740U, // VPSLLWZ128rikz 512U, // VPSLLWZ128rm 559396U, // VPSLLWZ128rmk 591972U, // VPSLLWZ128rmkz 96U, // VPSLLWZ128rr 166180U, // VPSLLWZ128rrk 198756U, // VPSLLWZ128rrkz 0U, // VPSLLWZ256mi 920260U, // VPSLLWZ256mik 461284U, // VPSLLWZ256mikz 32U, // VPSLLWZ256ri 2340U, // VPSLLWZ256rik 624740U, // VPSLLWZ256rikz 512U, // VPSLLWZ256rm 559396U, // VPSLLWZ256rmk 591972U, // VPSLLWZ256rmkz 96U, // VPSLLWZ256rr 166180U, // VPSLLWZ256rrk 198756U, // VPSLLWZ256rrkz 0U, // VPSLLWZmi 920548U, // VPSLLWZmik 461348U, // VPSLLWZmikz 32U, // VPSLLWZri 2340U, // VPSLLWZrik 624740U, // VPSLLWZrikz 512U, // VPSLLWZrm 559396U, // VPSLLWZrmk 591972U, // VPSLLWZrmkz 96U, // VPSLLWZrr 166180U, // VPSLLWZrrk 198756U, // VPSLLWZrrkz 32U, // VPSLLWri 512U, // VPSLLWrm 96U, // VPSLLWrr 32U, // VPSRADYri 512U, // VPSRADYrm 96U, // VPSRADYrr 12U, // VPSRADZ128mbi 930756U, // VPSRADZ128mbik 471108U, // VPSRADZ128mbikz 0U, // VPSRADZ128mi 920228U, // VPSRADZ128mik 461316U, // VPSRADZ128mikz 32U, // VPSRADZ128ri 2340U, // VPSRADZ128rik 624740U, // VPSRADZ128rikz 512U, // VPSRADZ128rm 559396U, // VPSRADZ128rmk 591972U, // VPSRADZ128rmkz 96U, // VPSRADZ128rr 166180U, // VPSRADZ128rrk 198756U, // VPSRADZ128rrkz 12U, // VPSRADZ256mbi 932804U, // VPSRADZ256mbik 473156U, // VPSRADZ256mbikz 0U, // VPSRADZ256mi 920260U, // VPSRADZ256mik 461284U, // VPSRADZ256mikz 32U, // VPSRADZ256ri 2340U, // VPSRADZ256rik 624740U, // VPSRADZ256rikz 512U, // VPSRADZ256rm 559396U, // VPSRADZ256rmk 591972U, // VPSRADZ256rmkz 96U, // VPSRADZ256rr 166180U, // VPSRADZ256rrk 198756U, // VPSRADZ256rrkz 13U, // VPSRADZmbi 934852U, // VPSRADZmbik 475204U, // VPSRADZmbikz 0U, // VPSRADZmi 920548U, // VPSRADZmik 461348U, // VPSRADZmikz 32U, // VPSRADZri 2340U, // VPSRADZrik 624740U, // VPSRADZrikz 512U, // VPSRADZrm 559396U, // VPSRADZrmk 591972U, // VPSRADZrmkz 96U, // VPSRADZrr 166180U, // VPSRADZrrk 198756U, // VPSRADZrrkz 32U, // VPSRADri 512U, // VPSRADrm 96U, // VPSRADrr 11U, // VPSRAQZ128mbi 936580U, // VPSRAQZ128mbik 477316U, // VPSRAQZ128mbikz 0U, // VPSRAQZ128mi 920228U, // VPSRAQZ128mik 461316U, // VPSRAQZ128mikz 32U, // VPSRAQZ128ri 2340U, // VPSRAQZ128rik 624740U, // VPSRAQZ128rikz 512U, // VPSRAQZ128rm 559396U, // VPSRAQZ128rmk 591972U, // VPSRAQZ128rmkz 96U, // VPSRAQZ128rr 166180U, // VPSRAQZ128rrk 198756U, // VPSRAQZ128rrkz 12U, // VPSRAQZ256mbi 930436U, // VPSRAQZ256mbik 471172U, // VPSRAQZ256mbikz 0U, // VPSRAQZ256mi 920260U, // VPSRAQZ256mik 461284U, // VPSRAQZ256mikz 32U, // VPSRAQZ256ri 2340U, // VPSRAQZ256rik 624740U, // VPSRAQZ256rikz 512U, // VPSRAQZ256rm 559396U, // VPSRAQZ256rmk 591972U, // VPSRAQZ256rmkz 96U, // VPSRAQZ256rr 166180U, // VPSRAQZ256rrk 198756U, // VPSRAQZ256rrkz 12U, // VPSRAQZmbi 932484U, // VPSRAQZmbik 473220U, // VPSRAQZmbikz 0U, // VPSRAQZmi 920548U, // VPSRAQZmik 461348U, // VPSRAQZmikz 32U, // VPSRAQZri 2340U, // VPSRAQZrik 624740U, // VPSRAQZrikz 512U, // VPSRAQZrm 559396U, // VPSRAQZrmk 591972U, // VPSRAQZrmkz 96U, // VPSRAQZrr 166180U, // VPSRAQZrrk 198756U, // VPSRAQZrrkz 480U, // VPSRAVDYrm 96U, // VPSRAVDYrr 512U, // VPSRAVDZ128rm 6208U, // VPSRAVDZ128rmb 2591012U, // VPSRAVDZ128rmbk 2623588U, // VPSRAVDZ128rmbkz 559396U, // VPSRAVDZ128rmk 591972U, // VPSRAVDZ128rmkz 96U, // VPSRAVDZ128rr 166180U, // VPSRAVDZ128rrk 198756U, // VPSRAVDZ128rrkz 480U, // VPSRAVDZ256rm 8256U, // VPSRAVDZ256rmb 3639588U, // VPSRAVDZ256rmbk 3672164U, // VPSRAVDZ256rmbkz 657700U, // VPSRAVDZ256rmk 690276U, // VPSRAVDZ256rmkz 96U, // VPSRAVDZ256rr 166180U, // VPSRAVDZ256rrk 198756U, // VPSRAVDZ256rrkz 544U, // VPSRAVDZrm 10304U, // VPSRAVDZrmb 5736740U, // VPSRAVDZrmbk 5769316U, // VPSRAVDZrmbkz 723236U, // VPSRAVDZrmk 755812U, // VPSRAVDZrmkz 96U, // VPSRAVDZrr 166180U, // VPSRAVDZrrk 198756U, // VPSRAVDZrrkz 512U, // VPSRAVDrm 96U, // VPSRAVDrr 512U, // VPSRAVQZ128rm 4224U, // VPSRAVQZ128rmb 1837348U, // VPSRAVQZ128rmbk 1869924U, // VPSRAVQZ128rmbkz 559396U, // VPSRAVQZ128rmk 591972U, // VPSRAVQZ128rmkz 96U, // VPSRAVQZ128rr 166180U, // VPSRAVQZ128rrk 198756U, // VPSRAVQZ128rrkz 480U, // VPSRAVQZ256rm 6272U, // VPSRAVQZ256rmb 2885924U, // VPSRAVQZ256rmbk 2918500U, // VPSRAVQZ256rmbkz 657700U, // VPSRAVQZ256rmk 690276U, // VPSRAVQZ256rmkz 96U, // VPSRAVQZ256rr 166180U, // VPSRAVQZ256rrk 198756U, // VPSRAVQZ256rrkz 544U, // VPSRAVQZrm 8320U, // VPSRAVQZrmb 3934500U, // VPSRAVQZrmbk 3967076U, // VPSRAVQZrmbkz 723236U, // VPSRAVQZrmk 755812U, // VPSRAVQZrmkz 96U, // VPSRAVQZrr 166180U, // VPSRAVQZrrk 198756U, // VPSRAVQZrrkz 512U, // VPSRAVWZ128rm 559396U, // VPSRAVWZ128rmk 591972U, // VPSRAVWZ128rmkz 96U, // VPSRAVWZ128rr 166180U, // VPSRAVWZ128rrk 198756U, // VPSRAVWZ128rrkz 480U, // VPSRAVWZ256rm 657700U, // VPSRAVWZ256rmk 690276U, // VPSRAVWZ256rmkz 96U, // VPSRAVWZ256rr 166180U, // VPSRAVWZ256rrk 198756U, // VPSRAVWZ256rrkz 544U, // VPSRAVWZrm 723236U, // VPSRAVWZrmk 755812U, // VPSRAVWZrmkz 96U, // VPSRAVWZrr 166180U, // VPSRAVWZrrk 198756U, // VPSRAVWZrrkz 32U, // VPSRAWYri 512U, // VPSRAWYrm 96U, // VPSRAWYrr 0U, // VPSRAWZ128mi 920228U, // VPSRAWZ128mik 461316U, // VPSRAWZ128mikz 32U, // VPSRAWZ128ri 2340U, // VPSRAWZ128rik 624740U, // VPSRAWZ128rikz 512U, // VPSRAWZ128rm 559396U, // VPSRAWZ128rmk 591972U, // VPSRAWZ128rmkz 96U, // VPSRAWZ128rr 166180U, // VPSRAWZ128rrk 198756U, // VPSRAWZ128rrkz 0U, // VPSRAWZ256mi 920260U, // VPSRAWZ256mik 461284U, // VPSRAWZ256mikz 32U, // VPSRAWZ256ri 2340U, // VPSRAWZ256rik 624740U, // VPSRAWZ256rikz 512U, // VPSRAWZ256rm 559396U, // VPSRAWZ256rmk 591972U, // VPSRAWZ256rmkz 96U, // VPSRAWZ256rr 166180U, // VPSRAWZ256rrk 198756U, // VPSRAWZ256rrkz 0U, // VPSRAWZmi 920548U, // VPSRAWZmik 461348U, // VPSRAWZmikz 32U, // VPSRAWZri 2340U, // VPSRAWZrik 624740U, // VPSRAWZrikz 512U, // VPSRAWZrm 559396U, // VPSRAWZrmk 591972U, // VPSRAWZrmkz 96U, // VPSRAWZrr 166180U, // VPSRAWZrrk 198756U, // VPSRAWZrrkz 32U, // VPSRAWri 512U, // VPSRAWrm 96U, // VPSRAWrr 32U, // VPSRLDQYri 0U, // VPSRLDQZ128rm 32U, // VPSRLDQZ128rr 0U, // VPSRLDQZ256rm 32U, // VPSRLDQZ256rr 0U, // VPSRLDQZrm 32U, // VPSRLDQZrr 32U, // VPSRLDQri 32U, // VPSRLDYri 512U, // VPSRLDYrm 96U, // VPSRLDYrr 12U, // VPSRLDZ128mbi 930756U, // VPSRLDZ128mbik 471108U, // VPSRLDZ128mbikz 0U, // VPSRLDZ128mi 920228U, // VPSRLDZ128mik 461316U, // VPSRLDZ128mikz 32U, // VPSRLDZ128ri 2340U, // VPSRLDZ128rik 624740U, // VPSRLDZ128rikz 512U, // VPSRLDZ128rm 559396U, // VPSRLDZ128rmk 591972U, // VPSRLDZ128rmkz 96U, // VPSRLDZ128rr 166180U, // VPSRLDZ128rrk 198756U, // VPSRLDZ128rrkz 12U, // VPSRLDZ256mbi 932804U, // VPSRLDZ256mbik 473156U, // VPSRLDZ256mbikz 0U, // VPSRLDZ256mi 920260U, // VPSRLDZ256mik 461284U, // VPSRLDZ256mikz 32U, // VPSRLDZ256ri 2340U, // VPSRLDZ256rik 624740U, // VPSRLDZ256rikz 512U, // VPSRLDZ256rm 559396U, // VPSRLDZ256rmk 591972U, // VPSRLDZ256rmkz 96U, // VPSRLDZ256rr 166180U, // VPSRLDZ256rrk 198756U, // VPSRLDZ256rrkz 13U, // VPSRLDZmbi 934852U, // VPSRLDZmbik 475204U, // VPSRLDZmbikz 0U, // VPSRLDZmi 920548U, // VPSRLDZmik 461348U, // VPSRLDZmikz 32U, // VPSRLDZri 2340U, // VPSRLDZrik 624740U, // VPSRLDZrikz 512U, // VPSRLDZrm 559396U, // VPSRLDZrmk 591972U, // VPSRLDZrmkz 96U, // VPSRLDZrr 166180U, // VPSRLDZrrk 198756U, // VPSRLDZrrkz 32U, // VPSRLDri 512U, // VPSRLDrm 96U, // VPSRLDrr 32U, // VPSRLQYri 512U, // VPSRLQYrm 96U, // VPSRLQYrr 11U, // VPSRLQZ128mbi 936580U, // VPSRLQZ128mbik 477316U, // VPSRLQZ128mbikz 0U, // VPSRLQZ128mi 920228U, // VPSRLQZ128mik 461316U, // VPSRLQZ128mikz 32U, // VPSRLQZ128ri 2340U, // VPSRLQZ128rik 624740U, // VPSRLQZ128rikz 512U, // VPSRLQZ128rm 559396U, // VPSRLQZ128rmk 591972U, // VPSRLQZ128rmkz 96U, // VPSRLQZ128rr 166180U, // VPSRLQZ128rrk 198756U, // VPSRLQZ128rrkz 12U, // VPSRLQZ256mbi 930436U, // VPSRLQZ256mbik 471172U, // VPSRLQZ256mbikz 0U, // VPSRLQZ256mi 920260U, // VPSRLQZ256mik 461284U, // VPSRLQZ256mikz 32U, // VPSRLQZ256ri 2340U, // VPSRLQZ256rik 624740U, // VPSRLQZ256rikz 512U, // VPSRLQZ256rm 559396U, // VPSRLQZ256rmk 591972U, // VPSRLQZ256rmkz 96U, // VPSRLQZ256rr 166180U, // VPSRLQZ256rrk 198756U, // VPSRLQZ256rrkz 12U, // VPSRLQZmbi 932484U, // VPSRLQZmbik 473220U, // VPSRLQZmbikz 0U, // VPSRLQZmi 920548U, // VPSRLQZmik 461348U, // VPSRLQZmikz 32U, // VPSRLQZri 2340U, // VPSRLQZrik 624740U, // VPSRLQZrikz 512U, // VPSRLQZrm 559396U, // VPSRLQZrmk 591972U, // VPSRLQZrmkz 96U, // VPSRLQZrr 166180U, // VPSRLQZrrk 198756U, // VPSRLQZrrkz 32U, // VPSRLQri 512U, // VPSRLQrm 96U, // VPSRLQrr 480U, // VPSRLVDYrm 96U, // VPSRLVDYrr 512U, // VPSRLVDZ128rm 6208U, // VPSRLVDZ128rmb 2591012U, // VPSRLVDZ128rmbk 2623588U, // VPSRLVDZ128rmbkz 559396U, // VPSRLVDZ128rmk 591972U, // VPSRLVDZ128rmkz 96U, // VPSRLVDZ128rr 166180U, // VPSRLVDZ128rrk 198756U, // VPSRLVDZ128rrkz 480U, // VPSRLVDZ256rm 8256U, // VPSRLVDZ256rmb 3639588U, // VPSRLVDZ256rmbk 3672164U, // VPSRLVDZ256rmbkz 657700U, // VPSRLVDZ256rmk 690276U, // VPSRLVDZ256rmkz 96U, // VPSRLVDZ256rr 166180U, // VPSRLVDZ256rrk 198756U, // VPSRLVDZ256rrkz 544U, // VPSRLVDZrm 10304U, // VPSRLVDZrmb 5736740U, // VPSRLVDZrmbk 5769316U, // VPSRLVDZrmbkz 723236U, // VPSRLVDZrmk 755812U, // VPSRLVDZrmkz 96U, // VPSRLVDZrr 166180U, // VPSRLVDZrrk 198756U, // VPSRLVDZrrkz 512U, // VPSRLVDrm 96U, // VPSRLVDrr 480U, // VPSRLVQYrm 96U, // VPSRLVQYrr 512U, // VPSRLVQZ128rm 4224U, // VPSRLVQZ128rmb 1837348U, // VPSRLVQZ128rmbk 1869924U, // VPSRLVQZ128rmbkz 559396U, // VPSRLVQZ128rmk 591972U, // VPSRLVQZ128rmkz 96U, // VPSRLVQZ128rr 166180U, // VPSRLVQZ128rrk 198756U, // VPSRLVQZ128rrkz 480U, // VPSRLVQZ256rm 6272U, // VPSRLVQZ256rmb 2885924U, // VPSRLVQZ256rmbk 2918500U, // VPSRLVQZ256rmbkz 657700U, // VPSRLVQZ256rmk 690276U, // VPSRLVQZ256rmkz 96U, // VPSRLVQZ256rr 166180U, // VPSRLVQZ256rrk 198756U, // VPSRLVQZ256rrkz 544U, // VPSRLVQZrm 8320U, // VPSRLVQZrmb 3934500U, // VPSRLVQZrmbk 3967076U, // VPSRLVQZrmbkz 723236U, // VPSRLVQZrmk 755812U, // VPSRLVQZrmkz 96U, // VPSRLVQZrr 166180U, // VPSRLVQZrrk 198756U, // VPSRLVQZrrkz 512U, // VPSRLVQrm 96U, // VPSRLVQrr 512U, // VPSRLVWZ128rm 559396U, // VPSRLVWZ128rmk 591972U, // VPSRLVWZ128rmkz 96U, // VPSRLVWZ128rr 166180U, // VPSRLVWZ128rrk 198756U, // VPSRLVWZ128rrkz 480U, // VPSRLVWZ256rm 657700U, // VPSRLVWZ256rmk 690276U, // VPSRLVWZ256rmkz 96U, // VPSRLVWZ256rr 166180U, // VPSRLVWZ256rrk 198756U, // VPSRLVWZ256rrkz 544U, // VPSRLVWZrm 723236U, // VPSRLVWZrmk 755812U, // VPSRLVWZrmkz 96U, // VPSRLVWZrr 166180U, // VPSRLVWZrrk 198756U, // VPSRLVWZrrkz 32U, // VPSRLWYri 512U, // VPSRLWYrm 96U, // VPSRLWYrr 0U, // VPSRLWZ128mi 920228U, // VPSRLWZ128mik 461316U, // VPSRLWZ128mikz 32U, // VPSRLWZ128ri 2340U, // VPSRLWZ128rik 624740U, // VPSRLWZ128rikz 512U, // VPSRLWZ128rm 559396U, // VPSRLWZ128rmk 591972U, // VPSRLWZ128rmkz 96U, // VPSRLWZ128rr 166180U, // VPSRLWZ128rrk 198756U, // VPSRLWZ128rrkz 0U, // VPSRLWZ256mi 920260U, // VPSRLWZ256mik 461284U, // VPSRLWZ256mikz 32U, // VPSRLWZ256ri 2340U, // VPSRLWZ256rik 624740U, // VPSRLWZ256rikz 512U, // VPSRLWZ256rm 559396U, // VPSRLWZ256rmk 591972U, // VPSRLWZ256rmkz 96U, // VPSRLWZ256rr 166180U, // VPSRLWZ256rrk 198756U, // VPSRLWZ256rrkz 0U, // VPSRLWZmi 920548U, // VPSRLWZmik 461348U, // VPSRLWZmikz 32U, // VPSRLWZri 2340U, // VPSRLWZrik 624740U, // VPSRLWZrikz 512U, // VPSRLWZrm 559396U, // VPSRLWZrmk 591972U, // VPSRLWZrmkz 96U, // VPSRLWZrr 166180U, // VPSRLWZrrk 198756U, // VPSRLWZrrkz 32U, // VPSRLWri 512U, // VPSRLWrm 96U, // VPSRLWrr 480U, // VPSUBBYrm 96U, // VPSUBBYrr 512U, // VPSUBBZ128rm 559396U, // VPSUBBZ128rmk 591972U, // VPSUBBZ128rmkz 96U, // VPSUBBZ128rr 166180U, // VPSUBBZ128rrk 198756U, // VPSUBBZ128rrkz 480U, // VPSUBBZ256rm 657700U, // VPSUBBZ256rmk 690276U, // VPSUBBZ256rmkz 96U, // VPSUBBZ256rr 166180U, // VPSUBBZ256rrk 198756U, // VPSUBBZ256rrkz 544U, // VPSUBBZrm 723236U, // VPSUBBZrmk 755812U, // VPSUBBZrmkz 96U, // VPSUBBZrr 166180U, // VPSUBBZrrk 198756U, // VPSUBBZrrkz 512U, // VPSUBBrm 96U, // VPSUBBrr 480U, // VPSUBDYrm 96U, // VPSUBDYrr 512U, // VPSUBDZ128rm 6208U, // VPSUBDZ128rmb 2591012U, // VPSUBDZ128rmbk 2623588U, // VPSUBDZ128rmbkz 559396U, // VPSUBDZ128rmk 591972U, // VPSUBDZ128rmkz 96U, // VPSUBDZ128rr 166180U, // VPSUBDZ128rrk 198756U, // VPSUBDZ128rrkz 480U, // VPSUBDZ256rm 8256U, // VPSUBDZ256rmb 3639588U, // VPSUBDZ256rmbk 3672164U, // VPSUBDZ256rmbkz 657700U, // VPSUBDZ256rmk 690276U, // VPSUBDZ256rmkz 96U, // VPSUBDZ256rr 166180U, // VPSUBDZ256rrk 198756U, // VPSUBDZ256rrkz 544U, // VPSUBDZrm 10304U, // VPSUBDZrmb 5736740U, // VPSUBDZrmbk 5769316U, // VPSUBDZrmbkz 723236U, // VPSUBDZrmk 755812U, // VPSUBDZrmkz 96U, // VPSUBDZrr 166180U, // VPSUBDZrrk 198756U, // VPSUBDZrrkz 512U, // VPSUBDrm 96U, // VPSUBDrr 480U, // VPSUBQYrm 96U, // VPSUBQYrr 512U, // VPSUBQZ128rm 4224U, // VPSUBQZ128rmb 1837348U, // VPSUBQZ128rmbk 1869924U, // VPSUBQZ128rmbkz 559396U, // VPSUBQZ128rmk 591972U, // VPSUBQZ128rmkz 96U, // VPSUBQZ128rr 166180U, // VPSUBQZ128rrk 198756U, // VPSUBQZ128rrkz 480U, // VPSUBQZ256rm 6272U, // VPSUBQZ256rmb 2885924U, // VPSUBQZ256rmbk 2918500U, // VPSUBQZ256rmbkz 657700U, // VPSUBQZ256rmk 690276U, // VPSUBQZ256rmkz 96U, // VPSUBQZ256rr 166180U, // VPSUBQZ256rrk 198756U, // VPSUBQZ256rrkz 544U, // VPSUBQZrm 8320U, // VPSUBQZrmb 3934500U, // VPSUBQZrmbk 3967076U, // VPSUBQZrmbkz 723236U, // VPSUBQZrmk 755812U, // VPSUBQZrmkz 96U, // VPSUBQZrr 166180U, // VPSUBQZrrk 198756U, // VPSUBQZrrkz 512U, // VPSUBQrm 96U, // VPSUBQrr 480U, // VPSUBSBYrm 96U, // VPSUBSBYrr 512U, // VPSUBSBZ128rm 559396U, // VPSUBSBZ128rmk 591972U, // VPSUBSBZ128rmkz 96U, // VPSUBSBZ128rr 166180U, // VPSUBSBZ128rrk 198756U, // VPSUBSBZ128rrkz 480U, // VPSUBSBZ256rm 657700U, // VPSUBSBZ256rmk 690276U, // VPSUBSBZ256rmkz 96U, // VPSUBSBZ256rr 166180U, // VPSUBSBZ256rrk 198756U, // VPSUBSBZ256rrkz 544U, // VPSUBSBZrm 723236U, // VPSUBSBZrmk 755812U, // VPSUBSBZrmkz 96U, // VPSUBSBZrr 166180U, // VPSUBSBZrrk 198756U, // VPSUBSBZrrkz 512U, // VPSUBSBrm 96U, // VPSUBSBrr 480U, // VPSUBSWYrm 96U, // VPSUBSWYrr 512U, // VPSUBSWZ128rm 559396U, // VPSUBSWZ128rmk 591972U, // VPSUBSWZ128rmkz 96U, // VPSUBSWZ128rr 166180U, // VPSUBSWZ128rrk 198756U, // VPSUBSWZ128rrkz 480U, // VPSUBSWZ256rm 657700U, // VPSUBSWZ256rmk 690276U, // VPSUBSWZ256rmkz 96U, // VPSUBSWZ256rr 166180U, // VPSUBSWZ256rrk 198756U, // VPSUBSWZ256rrkz 544U, // VPSUBSWZrm 723236U, // VPSUBSWZrmk 755812U, // VPSUBSWZrmkz 96U, // VPSUBSWZrr 166180U, // VPSUBSWZrrk 198756U, // VPSUBSWZrrkz 512U, // VPSUBSWrm 96U, // VPSUBSWrr 480U, // VPSUBUSBYrm 96U, // VPSUBUSBYrr 512U, // VPSUBUSBZ128rm 559396U, // VPSUBUSBZ128rmk 591972U, // VPSUBUSBZ128rmkz 96U, // VPSUBUSBZ128rr 166180U, // VPSUBUSBZ128rrk 198756U, // VPSUBUSBZ128rrkz 480U, // VPSUBUSBZ256rm 657700U, // VPSUBUSBZ256rmk 690276U, // VPSUBUSBZ256rmkz 96U, // VPSUBUSBZ256rr 166180U, // VPSUBUSBZ256rrk 198756U, // VPSUBUSBZ256rrkz 544U, // VPSUBUSBZrm 723236U, // VPSUBUSBZrmk 755812U, // VPSUBUSBZrmkz 96U, // VPSUBUSBZrr 166180U, // VPSUBUSBZrrk 198756U, // VPSUBUSBZrrkz 512U, // VPSUBUSBrm 96U, // VPSUBUSBrr 480U, // VPSUBUSWYrm 96U, // VPSUBUSWYrr 512U, // VPSUBUSWZ128rm 559396U, // VPSUBUSWZ128rmk 591972U, // VPSUBUSWZ128rmkz 96U, // VPSUBUSWZ128rr 166180U, // VPSUBUSWZ128rrk 198756U, // VPSUBUSWZ128rrkz 480U, // VPSUBUSWZ256rm 657700U, // VPSUBUSWZ256rmk 690276U, // VPSUBUSWZ256rmkz 96U, // VPSUBUSWZ256rr 166180U, // VPSUBUSWZ256rrk 198756U, // VPSUBUSWZ256rrkz 544U, // VPSUBUSWZrm 723236U, // VPSUBUSWZrmk 755812U, // VPSUBUSWZrmkz 96U, // VPSUBUSWZrr 166180U, // VPSUBUSWZrrk 198756U, // VPSUBUSWZrrkz 512U, // VPSUBUSWrm 96U, // VPSUBUSWrr 480U, // VPSUBWYrm 96U, // VPSUBWYrr 512U, // VPSUBWZ128rm 559396U, // VPSUBWZ128rmk 591972U, // VPSUBWZ128rmkz 96U, // VPSUBWZ128rr 166180U, // VPSUBWZ128rrk 198756U, // VPSUBWZ128rrkz 480U, // VPSUBWZ256rm 657700U, // VPSUBWZ256rmk 690276U, // VPSUBWZ256rmkz 96U, // VPSUBWZ256rr 166180U, // VPSUBWZ256rrk 198756U, // VPSUBWZ256rrkz 544U, // VPSUBWZrm 723236U, // VPSUBWZrmk 755812U, // VPSUBWZrmkz 96U, // VPSUBWZrr 166180U, // VPSUBWZrrk 198756U, // VPSUBWZrrkz 512U, // VPSUBWrm 96U, // VPSUBWrr 930752U, // VPTERNLOGDZ128rmbi 40339748U, // VPTERNLOGDZ128rmbik 40339748U, // VPTERNLOGDZ128rmbikz 920224U, // VPTERNLOGDZ128rmi 38308132U, // VPTERNLOGDZ128rmik 38308132U, // VPTERNLOGDZ128rmikz 2336U, // VPTERNLOGDZ128rri 71469348U, // VPTERNLOGDZ128rrik 71469348U, // VPTERNLOGDZ128rrikz 932800U, // VPTERNLOGDZ256rmbi 41388324U, // VPTERNLOGDZ256rmbik 41388324U, // VPTERNLOGDZ256rmbikz 920256U, // VPTERNLOGDZ256rmi 38406436U, // VPTERNLOGDZ256rmik 38406436U, // VPTERNLOGDZ256rmikz 2336U, // VPTERNLOGDZ256rri 71469348U, // VPTERNLOGDZ256rrik 71469348U, // VPTERNLOGDZ256rrikz 934848U, // VPTERNLOGDZrmbi 42436900U, // VPTERNLOGDZrmbik 42436900U, // VPTERNLOGDZrmbikz 920544U, // VPTERNLOGDZrmi 38471972U, // VPTERNLOGDZrmik 38471972U, // VPTERNLOGDZrmikz 2336U, // VPTERNLOGDZrri 71469348U, // VPTERNLOGDZrrik 71469348U, // VPTERNLOGDZrrikz 936576U, // VPTERNLOGQZ128rmbi 43780388U, // VPTERNLOGQZ128rmbik 43780388U, // VPTERNLOGQZ128rmbikz 920224U, // VPTERNLOGQZ128rmi 38308132U, // VPTERNLOGQZ128rmik 38308132U, // VPTERNLOGQZ128rmikz 2336U, // VPTERNLOGQZ128rri 71469348U, // VPTERNLOGQZ128rrik 71469348U, // VPTERNLOGQZ128rrikz 930432U, // VPTERNLOGQZ256rmbi 40634660U, // VPTERNLOGQZ256rmbik 40634660U, // VPTERNLOGQZ256rmbikz 920256U, // VPTERNLOGQZ256rmi 38406436U, // VPTERNLOGQZ256rmik 38406436U, // VPTERNLOGQZ256rmikz 2336U, // VPTERNLOGQZ256rri 71469348U, // VPTERNLOGQZ256rrik 71469348U, // VPTERNLOGQZ256rrikz 932480U, // VPTERNLOGQZrmbi 41683236U, // VPTERNLOGQZrmbik 41683236U, // VPTERNLOGQZrmbikz 920544U, // VPTERNLOGQZrmi 38471972U, // VPTERNLOGQZrmik 38471972U, // VPTERNLOGQZrmikz 2336U, // VPTERNLOGQZrri 71469348U, // VPTERNLOGQZrrik 71469348U, // VPTERNLOGQZrrikz 512U, // VPTESTMBZ128rm 591972U, // VPTESTMBZ128rmk 96U, // VPTESTMBZ128rr 198756U, // VPTESTMBZ128rrk 480U, // VPTESTMBZ256rm 690276U, // VPTESTMBZ256rmk 96U, // VPTESTMBZ256rr 198756U, // VPTESTMBZ256rrk 544U, // VPTESTMBZrm 755812U, // VPTESTMBZrmk 96U, // VPTESTMBZrr 198756U, // VPTESTMBZrrk 512U, // VPTESTMDZ128rm 6208U, // VPTESTMDZ128rmb 2623588U, // VPTESTMDZ128rmbk 591972U, // VPTESTMDZ128rmk 96U, // VPTESTMDZ128rr 198756U, // VPTESTMDZ128rrk 480U, // VPTESTMDZ256rm 8256U, // VPTESTMDZ256rmb 3672164U, // VPTESTMDZ256rmbk 690276U, // VPTESTMDZ256rmk 96U, // VPTESTMDZ256rr 198756U, // VPTESTMDZ256rrk 544U, // VPTESTMDZrm 10304U, // VPTESTMDZrmb 5769316U, // VPTESTMDZrmbk 755812U, // VPTESTMDZrmk 96U, // VPTESTMDZrr 198756U, // VPTESTMDZrrk 512U, // VPTESTMQZ128rm 4224U, // VPTESTMQZ128rmb 1869924U, // VPTESTMQZ128rmbk 591972U, // VPTESTMQZ128rmk 96U, // VPTESTMQZ128rr 198756U, // VPTESTMQZ128rrk 480U, // VPTESTMQZ256rm 6272U, // VPTESTMQZ256rmb 2918500U, // VPTESTMQZ256rmbk 690276U, // VPTESTMQZ256rmk 96U, // VPTESTMQZ256rr 198756U, // VPTESTMQZ256rrk 544U, // VPTESTMQZrm 8320U, // VPTESTMQZrmb 3967076U, // VPTESTMQZrmbk 755812U, // VPTESTMQZrmk 96U, // VPTESTMQZrr 198756U, // VPTESTMQZrrk 512U, // VPTESTMWZ128rm 591972U, // VPTESTMWZ128rmk 96U, // VPTESTMWZ128rr 198756U, // VPTESTMWZ128rrk 480U, // VPTESTMWZ256rm 690276U, // VPTESTMWZ256rmk 96U, // VPTESTMWZ256rr 198756U, // VPTESTMWZ256rrk 544U, // VPTESTMWZrm 755812U, // VPTESTMWZrmk 96U, // VPTESTMWZrr 198756U, // VPTESTMWZrrk 512U, // VPTESTNMBZ128rm 591972U, // VPTESTNMBZ128rmk 96U, // VPTESTNMBZ128rr 198756U, // VPTESTNMBZ128rrk 480U, // VPTESTNMBZ256rm 690276U, // VPTESTNMBZ256rmk 96U, // VPTESTNMBZ256rr 198756U, // VPTESTNMBZ256rrk 544U, // VPTESTNMBZrm 755812U, // VPTESTNMBZrmk 96U, // VPTESTNMBZrr 198756U, // VPTESTNMBZrrk 512U, // VPTESTNMDZ128rm 6208U, // VPTESTNMDZ128rmb 2623588U, // VPTESTNMDZ128rmbk 591972U, // VPTESTNMDZ128rmk 96U, // VPTESTNMDZ128rr 198756U, // VPTESTNMDZ128rrk 480U, // VPTESTNMDZ256rm 8256U, // VPTESTNMDZ256rmb 3672164U, // VPTESTNMDZ256rmbk 690276U, // VPTESTNMDZ256rmk 96U, // VPTESTNMDZ256rr 198756U, // VPTESTNMDZ256rrk 544U, // VPTESTNMDZrm 10304U, // VPTESTNMDZrmb 5769316U, // VPTESTNMDZrmbk 755812U, // VPTESTNMDZrmk 96U, // VPTESTNMDZrr 198756U, // VPTESTNMDZrrk 512U, // VPTESTNMQZ128rm 4224U, // VPTESTNMQZ128rmb 1869924U, // VPTESTNMQZ128rmbk 591972U, // VPTESTNMQZ128rmk 96U, // VPTESTNMQZ128rr 198756U, // VPTESTNMQZ128rrk 480U, // VPTESTNMQZ256rm 6272U, // VPTESTNMQZ256rmb 2918500U, // VPTESTNMQZ256rmbk 690276U, // VPTESTNMQZ256rmk 96U, // VPTESTNMQZ256rr 198756U, // VPTESTNMQZ256rrk 544U, // VPTESTNMQZrm 8320U, // VPTESTNMQZrmb 3967076U, // VPTESTNMQZrmbk 755812U, // VPTESTNMQZrmk 96U, // VPTESTNMQZrr 198756U, // VPTESTNMQZrrk 512U, // VPTESTNMWZ128rm 591972U, // VPTESTNMWZ128rmk 96U, // VPTESTNMWZ128rr 198756U, // VPTESTNMWZ128rrk 480U, // VPTESTNMWZ256rm 690276U, // VPTESTNMWZ256rmk 96U, // VPTESTNMWZ256rr 198756U, // VPTESTNMWZ256rrk 544U, // VPTESTNMWZrm 755812U, // VPTESTNMWZrmk 96U, // VPTESTNMWZrr 198756U, // VPTESTNMWZrrk 0U, // VPTESTYrm 0U, // VPTESTYrr 0U, // VPTESTrm 0U, // VPTESTrr 480U, // VPUNPCKHBWYrm 96U, // VPUNPCKHBWYrr 512U, // VPUNPCKHBWZ128rm 559396U, // VPUNPCKHBWZ128rmk 591972U, // VPUNPCKHBWZ128rmkz 96U, // VPUNPCKHBWZ128rr 166180U, // VPUNPCKHBWZ128rrk 198756U, // VPUNPCKHBWZ128rrkz 480U, // VPUNPCKHBWZ256rm 657700U, // VPUNPCKHBWZ256rmk 690276U, // VPUNPCKHBWZ256rmkz 96U, // VPUNPCKHBWZ256rr 166180U, // VPUNPCKHBWZ256rrk 198756U, // VPUNPCKHBWZ256rrkz 544U, // VPUNPCKHBWZrm 723236U, // VPUNPCKHBWZrmk 755812U, // VPUNPCKHBWZrmkz 96U, // VPUNPCKHBWZrr 166180U, // VPUNPCKHBWZrrk 198756U, // VPUNPCKHBWZrrkz 512U, // VPUNPCKHBWrm 96U, // VPUNPCKHBWrr 480U, // VPUNPCKHDQYrm 96U, // VPUNPCKHDQYrr 512U, // VPUNPCKHDQZ128rm 6208U, // VPUNPCKHDQZ128rmb 2591012U, // VPUNPCKHDQZ128rmbk 2623588U, // VPUNPCKHDQZ128rmbkz 559396U, // VPUNPCKHDQZ128rmk 591972U, // VPUNPCKHDQZ128rmkz 96U, // VPUNPCKHDQZ128rr 166180U, // VPUNPCKHDQZ128rrk 198756U, // VPUNPCKHDQZ128rrkz 480U, // VPUNPCKHDQZ256rm 8256U, // VPUNPCKHDQZ256rmb 3639588U, // VPUNPCKHDQZ256rmbk 3672164U, // VPUNPCKHDQZ256rmbkz 657700U, // VPUNPCKHDQZ256rmk 690276U, // VPUNPCKHDQZ256rmkz 96U, // VPUNPCKHDQZ256rr 166180U, // VPUNPCKHDQZ256rrk 198756U, // VPUNPCKHDQZ256rrkz 544U, // VPUNPCKHDQZrm 10304U, // VPUNPCKHDQZrmb 5736740U, // VPUNPCKHDQZrmbk 5769316U, // VPUNPCKHDQZrmbkz 723236U, // VPUNPCKHDQZrmk 755812U, // VPUNPCKHDQZrmkz 96U, // VPUNPCKHDQZrr 166180U, // VPUNPCKHDQZrrk 198756U, // VPUNPCKHDQZrrkz 512U, // VPUNPCKHDQrm 96U, // VPUNPCKHDQrr 480U, // VPUNPCKHQDQYrm 96U, // VPUNPCKHQDQYrr 512U, // VPUNPCKHQDQZ128rm 4224U, // VPUNPCKHQDQZ128rmb 1837348U, // VPUNPCKHQDQZ128rmbk 1869924U, // VPUNPCKHQDQZ128rmbkz 559396U, // VPUNPCKHQDQZ128rmk 591972U, // VPUNPCKHQDQZ128rmkz 96U, // VPUNPCKHQDQZ128rr 166180U, // VPUNPCKHQDQZ128rrk 198756U, // VPUNPCKHQDQZ128rrkz 480U, // VPUNPCKHQDQZ256rm 6272U, // VPUNPCKHQDQZ256rmb 2885924U, // VPUNPCKHQDQZ256rmbk 2918500U, // VPUNPCKHQDQZ256rmbkz 657700U, // VPUNPCKHQDQZ256rmk 690276U, // VPUNPCKHQDQZ256rmkz 96U, // VPUNPCKHQDQZ256rr 166180U, // VPUNPCKHQDQZ256rrk 198756U, // VPUNPCKHQDQZ256rrkz 544U, // VPUNPCKHQDQZrm 8320U, // VPUNPCKHQDQZrmb 3934500U, // VPUNPCKHQDQZrmbk 3967076U, // VPUNPCKHQDQZrmbkz 723236U, // VPUNPCKHQDQZrmk 755812U, // VPUNPCKHQDQZrmkz 96U, // VPUNPCKHQDQZrr 166180U, // VPUNPCKHQDQZrrk 198756U, // VPUNPCKHQDQZrrkz 512U, // VPUNPCKHQDQrm 96U, // VPUNPCKHQDQrr 480U, // VPUNPCKHWDYrm 96U, // VPUNPCKHWDYrr 512U, // VPUNPCKHWDZ128rm 559396U, // VPUNPCKHWDZ128rmk 591972U, // VPUNPCKHWDZ128rmkz 96U, // VPUNPCKHWDZ128rr 166180U, // VPUNPCKHWDZ128rrk 198756U, // VPUNPCKHWDZ128rrkz 480U, // VPUNPCKHWDZ256rm 657700U, // VPUNPCKHWDZ256rmk 690276U, // VPUNPCKHWDZ256rmkz 96U, // VPUNPCKHWDZ256rr 166180U, // VPUNPCKHWDZ256rrk 198756U, // VPUNPCKHWDZ256rrkz 544U, // VPUNPCKHWDZrm 723236U, // VPUNPCKHWDZrmk 755812U, // VPUNPCKHWDZrmkz 96U, // VPUNPCKHWDZrr 166180U, // VPUNPCKHWDZrrk 198756U, // VPUNPCKHWDZrrkz 512U, // VPUNPCKHWDrm 96U, // VPUNPCKHWDrr 480U, // VPUNPCKLBWYrm 96U, // VPUNPCKLBWYrr 512U, // VPUNPCKLBWZ128rm 559396U, // VPUNPCKLBWZ128rmk 591972U, // VPUNPCKLBWZ128rmkz 96U, // VPUNPCKLBWZ128rr 166180U, // VPUNPCKLBWZ128rrk 198756U, // VPUNPCKLBWZ128rrkz 480U, // VPUNPCKLBWZ256rm 657700U, // VPUNPCKLBWZ256rmk 690276U, // VPUNPCKLBWZ256rmkz 96U, // VPUNPCKLBWZ256rr 166180U, // VPUNPCKLBWZ256rrk 198756U, // VPUNPCKLBWZ256rrkz 544U, // VPUNPCKLBWZrm 723236U, // VPUNPCKLBWZrmk 755812U, // VPUNPCKLBWZrmkz 96U, // VPUNPCKLBWZrr 166180U, // VPUNPCKLBWZrrk 198756U, // VPUNPCKLBWZrrkz 512U, // VPUNPCKLBWrm 96U, // VPUNPCKLBWrr 480U, // VPUNPCKLDQYrm 96U, // VPUNPCKLDQYrr 512U, // VPUNPCKLDQZ128rm 6208U, // VPUNPCKLDQZ128rmb 2591012U, // VPUNPCKLDQZ128rmbk 2623588U, // VPUNPCKLDQZ128rmbkz 559396U, // VPUNPCKLDQZ128rmk 591972U, // VPUNPCKLDQZ128rmkz 96U, // VPUNPCKLDQZ128rr 166180U, // VPUNPCKLDQZ128rrk 198756U, // VPUNPCKLDQZ128rrkz 480U, // VPUNPCKLDQZ256rm 8256U, // VPUNPCKLDQZ256rmb 3639588U, // VPUNPCKLDQZ256rmbk 3672164U, // VPUNPCKLDQZ256rmbkz 657700U, // VPUNPCKLDQZ256rmk 690276U, // VPUNPCKLDQZ256rmkz 96U, // VPUNPCKLDQZ256rr 166180U, // VPUNPCKLDQZ256rrk 198756U, // VPUNPCKLDQZ256rrkz 544U, // VPUNPCKLDQZrm 10304U, // VPUNPCKLDQZrmb 5736740U, // VPUNPCKLDQZrmbk 5769316U, // VPUNPCKLDQZrmbkz 723236U, // VPUNPCKLDQZrmk 755812U, // VPUNPCKLDQZrmkz 96U, // VPUNPCKLDQZrr 166180U, // VPUNPCKLDQZrrk 198756U, // VPUNPCKLDQZrrkz 512U, // VPUNPCKLDQrm 96U, // VPUNPCKLDQrr 480U, // VPUNPCKLQDQYrm 96U, // VPUNPCKLQDQYrr 512U, // VPUNPCKLQDQZ128rm 4224U, // VPUNPCKLQDQZ128rmb 1837348U, // VPUNPCKLQDQZ128rmbk 1869924U, // VPUNPCKLQDQZ128rmbkz 559396U, // VPUNPCKLQDQZ128rmk 591972U, // VPUNPCKLQDQZ128rmkz 96U, // VPUNPCKLQDQZ128rr 166180U, // VPUNPCKLQDQZ128rrk 198756U, // VPUNPCKLQDQZ128rrkz 480U, // VPUNPCKLQDQZ256rm 6272U, // VPUNPCKLQDQZ256rmb 2885924U, // VPUNPCKLQDQZ256rmbk 2918500U, // VPUNPCKLQDQZ256rmbkz 657700U, // VPUNPCKLQDQZ256rmk 690276U, // VPUNPCKLQDQZ256rmkz 96U, // VPUNPCKLQDQZ256rr 166180U, // VPUNPCKLQDQZ256rrk 198756U, // VPUNPCKLQDQZ256rrkz 544U, // VPUNPCKLQDQZrm 8320U, // VPUNPCKLQDQZrmb 3934500U, // VPUNPCKLQDQZrmbk 3967076U, // VPUNPCKLQDQZrmbkz 723236U, // VPUNPCKLQDQZrmk 755812U, // VPUNPCKLQDQZrmkz 96U, // VPUNPCKLQDQZrr 166180U, // VPUNPCKLQDQZrrk 198756U, // VPUNPCKLQDQZrrkz 512U, // VPUNPCKLQDQrm 96U, // VPUNPCKLQDQrr 480U, // VPUNPCKLWDYrm 96U, // VPUNPCKLWDYrr 512U, // VPUNPCKLWDZ128rm 559396U, // VPUNPCKLWDZ128rmk 591972U, // VPUNPCKLWDZ128rmkz 96U, // VPUNPCKLWDZ128rr 166180U, // VPUNPCKLWDZ128rrk 198756U, // VPUNPCKLWDZ128rrkz 480U, // VPUNPCKLWDZ256rm 657700U, // VPUNPCKLWDZ256rmk 690276U, // VPUNPCKLWDZ256rmkz 96U, // VPUNPCKLWDZ256rr 166180U, // VPUNPCKLWDZ256rrk 198756U, // VPUNPCKLWDZ256rrkz 544U, // VPUNPCKLWDZrm 723236U, // VPUNPCKLWDZrmk 755812U, // VPUNPCKLWDZrmkz 96U, // VPUNPCKLWDZrr 166180U, // VPUNPCKLWDZrrk 198756U, // VPUNPCKLWDZrrkz 512U, // VPUNPCKLWDrm 96U, // VPUNPCKLWDrr 512U, // VPXORDZ128rm 6208U, // VPXORDZ128rmb 2591012U, // VPXORDZ128rmbk 2623588U, // VPXORDZ128rmbkz 559396U, // VPXORDZ128rmk 591972U, // VPXORDZ128rmkz 96U, // VPXORDZ128rr 166180U, // VPXORDZ128rrk 198756U, // VPXORDZ128rrkz 480U, // VPXORDZ256rm 8256U, // VPXORDZ256rmb 3639588U, // VPXORDZ256rmbk 3672164U, // VPXORDZ256rmbkz 657700U, // VPXORDZ256rmk 690276U, // VPXORDZ256rmkz 96U, // VPXORDZ256rr 166180U, // VPXORDZ256rrk 198756U, // VPXORDZ256rrkz 544U, // VPXORDZrm 10304U, // VPXORDZrmb 5736740U, // VPXORDZrmbk 5769316U, // VPXORDZrmbkz 723236U, // VPXORDZrmk 755812U, // VPXORDZrmkz 96U, // VPXORDZrr 166180U, // VPXORDZrrk 198756U, // VPXORDZrrkz 512U, // VPXORQZ128rm 4224U, // VPXORQZ128rmb 1837348U, // VPXORQZ128rmbk 1869924U, // VPXORQZ128rmbkz 559396U, // VPXORQZ128rmk 591972U, // VPXORQZ128rmkz 96U, // VPXORQZ128rr 166180U, // VPXORQZ128rrk 198756U, // VPXORQZ128rrkz 480U, // VPXORQZ256rm 6272U, // VPXORQZ256rmb 2885924U, // VPXORQZ256rmbk 2918500U, // VPXORQZ256rmbkz 657700U, // VPXORQZ256rmk 690276U, // VPXORQZ256rmkz 96U, // VPXORQZ256rr 166180U, // VPXORQZ256rrk 198756U, // VPXORQZ256rrkz 544U, // VPXORQZrm 8320U, // VPXORQZrmb 3934500U, // VPXORQZrmbk 3967076U, // VPXORQZrmbkz 723236U, // VPXORQZrmk 755812U, // VPXORQZrmkz 96U, // VPXORQZrr 166180U, // VPXORQZrrk 198756U, // VPXORQZrrkz 480U, // VPXORYrm 96U, // VPXORYrr 512U, // VPXORrm 96U, // VPXORrr 477568U, // VRANGEPDZ128rmbi 43059492U, // VRANGEPDZ128rmbik 59869284U, // VRANGEPDZ128rmbikz 461152U, // VRANGEPDZ128rmi 37783844U, // VRANGEPDZ128rmik 54659172U, // VRANGEPDZ128rmikz 624736U, // VRANGEPDZ128rri 71469348U, // VRANGEPDZ128rrik 88279140U, // VRANGEPDZ128rrikz 471424U, // VRANGEPDZ256rmbi 39913764U, // VRANGEPDZ256rmbik 56723556U, // VRANGEPDZ256rmbikz 461120U, // VRANGEPDZ256rmi 37980452U, // VRANGEPDZ256rmik 54790244U, // VRANGEPDZ256rmikz 624736U, // VRANGEPDZ256rri 71469348U, // VRANGEPDZ256rrik 88279140U, // VRANGEPDZ256rrikz 473472U, // VRANGEPDZrmbi 40962340U, // VRANGEPDZrmbik 57772132U, // VRANGEPDZrmbikz 461216U, // VRANGEPDZrmi 38045988U, // VRANGEPDZrmik 54855780U, // VRANGEPDZrmikz 624736U, // VRANGEPDZrri 645216U, // VRANGEPDZrrib 77760804U, // VRANGEPDZrribk 94570596U, // VRANGEPDZrribkz 71469348U, // VRANGEPDZrrik 88279140U, // VRANGEPDZrrikz 471488U, // VRANGEPSZ128rmbi 40241444U, // VRANGEPSZ128rmbik 57051236U, // VRANGEPSZ128rmbikz 461152U, // VRANGEPSZ128rmi 37783844U, // VRANGEPSZ128rmik 54659172U, // VRANGEPSZ128rmikz 624736U, // VRANGEPSZ128rri 71469348U, // VRANGEPSZ128rrik 88279140U, // VRANGEPSZ128rrikz 473536U, // VRANGEPSZ256rmbi 41290020U, // VRANGEPSZ256rmbik 58099812U, // VRANGEPSZ256rmbikz 461120U, // VRANGEPSZ256rmi 37980452U, // VRANGEPSZ256rmik 54790244U, // VRANGEPSZ256rmikz 624736U, // VRANGEPSZ256rri 71469348U, // VRANGEPSZ256rrik 88279140U, // VRANGEPSZ256rrikz 475584U, // VRANGEPSZrmbi 42338596U, // VRANGEPSZrmbik 59148388U, // VRANGEPSZrmbikz 461216U, // VRANGEPSZrmi 38045988U, // VRANGEPSZrmik 54855780U, // VRANGEPSZrmikz 624736U, // VRANGEPSZrri 645216U, // VRANGEPSZrrib 77760804U, // VRANGEPSZrribk 94570596U, // VRANGEPSZrribkz 71469348U, // VRANGEPSZrrik 88279140U, // VRANGEPSZrrikz 461184U, // VRANGESDZrmi 37816612U, // VRANGESDZrmik 54626404U, // VRANGESDZrmikz 624736U, // VRANGESDZrri 645216U, // VRANGESDZrrib 77760804U, // VRANGESDZrribk 94570596U, // VRANGESDZrribkz 71469348U, // VRANGESDZrrik 88279140U, // VRANGESDZrrikz 461248U, // VRANGESSZrmi 38144292U, // VRANGESSZrmik 54954084U, // VRANGESSZrmikz 624736U, // VRANGESSZrri 645216U, // VRANGESSZrrib 77760804U, // VRANGESSZrribk 94570596U, // VRANGESSZrribkz 71469348U, // VRANGESSZrrik 88279140U, // VRANGESSZrrikz 0U, // VRCP14PDZ128m 9U, // VRCP14PDZ128mb 4676U, // VRCP14PDZ128mbk 4484U, // VRCP14PDZ128mbkz 260U, // VRCP14PDZ128mk 356U, // VRCP14PDZ128mkz 0U, // VRCP14PDZ128r 292U, // VRCP14PDZ128rk 100U, // VRCP14PDZ128rkz 0U, // VRCP14PDZ256m 9U, // VRCP14PDZ256mb 6724U, // VRCP14PDZ256mbk 6532U, // VRCP14PDZ256mbkz 612U, // VRCP14PDZ256mk 324U, // VRCP14PDZ256mkz 0U, // VRCP14PDZ256r 292U, // VRCP14PDZ256rk 100U, // VRCP14PDZ256rkz 0U, // VRCP14PDZm 10U, // VRCP14PDZmb 8772U, // VRCP14PDZmbk 8580U, // VRCP14PDZmbkz 1060U, // VRCP14PDZmk 420U, // VRCP14PDZmkz 0U, // VRCP14PDZr 292U, // VRCP14PDZrk 100U, // VRCP14PDZrkz 0U, // VRCP14PSZ128m 9U, // VRCP14PSZ128mb 6884U, // VRCP14PSZ128mbk 6596U, // VRCP14PSZ128mbkz 260U, // VRCP14PSZ128mk 356U, // VRCP14PSZ128mkz 0U, // VRCP14PSZ128r 292U, // VRCP14PSZ128rk 100U, // VRCP14PSZ128rkz 0U, // VRCP14PSZ256m 10U, // VRCP14PSZ256mb 8932U, // VRCP14PSZ256mbk 8644U, // VRCP14PSZ256mbkz 612U, // VRCP14PSZ256mk 324U, // VRCP14PSZ256mkz 0U, // VRCP14PSZ256r 292U, // VRCP14PSZ256rk 100U, // VRCP14PSZ256rkz 0U, // VRCP14PSZm 10U, // VRCP14PSZmb 10980U, // VRCP14PSZmbk 10692U, // VRCP14PSZmbkz 1060U, // VRCP14PSZmk 420U, // VRCP14PSZmkz 0U, // VRCP14PSZr 292U, // VRCP14PSZrk 100U, // VRCP14PSZrkz 384U, // VRCP14SDZrm 67876U, // VRCP14SDZrmk 100452U, // VRCP14SDZrmkz 96U, // VRCP14SDZrr 166180U, // VRCP14SDZrrk 198756U, // VRCP14SDZrrkz 448U, // VRCP14SSZrm 395556U, // VRCP14SSZrmk 428132U, // VRCP14SSZrmkz 96U, // VRCP14SSZrr 166180U, // VRCP14SSZrrk 198756U, // VRCP14SSZrrkz 0U, // VRCP28PDZm 10U, // VRCP28PDZmb 8772U, // VRCP28PDZmbk 8580U, // VRCP28PDZmbkz 1060U, // VRCP28PDZmk 420U, // VRCP28PDZmkz 0U, // VRCP28PDZr 8U, // VRCP28PDZrb 20772U, // VRCP28PDZrbk 20580U, // VRCP28PDZrbkz 292U, // VRCP28PDZrk 100U, // VRCP28PDZrkz 0U, // VRCP28PSZm 10U, // VRCP28PSZmb 10980U, // VRCP28PSZmbk 10692U, // VRCP28PSZmbkz 1060U, // VRCP28PSZmk 420U, // VRCP28PSZmkz 0U, // VRCP28PSZr 8U, // VRCP28PSZrb 20772U, // VRCP28PSZrbk 20580U, // VRCP28PSZrbkz 292U, // VRCP28PSZrk 100U, // VRCP28PSZrkz 384U, // VRCP28SDZm 67876U, // VRCP28SDZmk 100452U, // VRCP28SDZmkz 96U, // VRCP28SDZr 20576U, // VRCP28SDZrb 11700516U, // VRCP28SDZrbk 11733092U, // VRCP28SDZrbkz 166180U, // VRCP28SDZrk 198756U, // VRCP28SDZrkz 448U, // VRCP28SSZm 395556U, // VRCP28SSZmk 428132U, // VRCP28SSZmkz 96U, // VRCP28SSZr 20576U, // VRCP28SSZrb 11700516U, // VRCP28SSZrbk 11733092U, // VRCP28SSZrbkz 166180U, // VRCP28SSZrk 198756U, // VRCP28SSZrkz 0U, // VRCPPSYm 0U, // VRCPPSYr 0U, // VRCPPSm 0U, // VRCPPSr 448U, // VRCPSSm 448U, // VRCPSSm_Int 96U, // VRCPSSr 96U, // VRCPSSr_Int 11U, // VREDUCEPDZ128rmbi 936516U, // VREDUCEPDZ128rmbik 477572U, // VREDUCEPDZ128rmbikz 0U, // VREDUCEPDZ128rmi 919812U, // VREDUCEPDZ128rmik 461156U, // VREDUCEPDZ128rmikz 32U, // VREDUCEPDZ128rri 2340U, // VREDUCEPDZ128rrik 624740U, // VREDUCEPDZ128rrikz 12U, // VREDUCEPDZ256rmbi 930372U, // VREDUCEPDZ256rmbik 471428U, // VREDUCEPDZ256rmbikz 0U, // VREDUCEPDZ256rmi 920164U, // VREDUCEPDZ256rmik 461124U, // VREDUCEPDZ256rmikz 32U, // VREDUCEPDZ256rri 2340U, // VREDUCEPDZ256rrik 624740U, // VREDUCEPDZ256rrikz 12U, // VREDUCEPDZrmbi 932420U, // VREDUCEPDZrmbik 473476U, // VREDUCEPDZrmbikz 0U, // VREDUCEPDZrmi 920612U, // VREDUCEPDZrmik 461220U, // VREDUCEPDZrmikz 32U, // VREDUCEPDZrri 11U, // VREDUCEPDZrrib 22820U, // VREDUCEPDZrribk 645220U, // VREDUCEPDZrribkz 2340U, // VREDUCEPDZrrik 624740U, // VREDUCEPDZrrikz 12U, // VREDUCEPSZ128rmbi 930532U, // VREDUCEPSZ128rmbik 471492U, // VREDUCEPSZ128rmbikz 0U, // VREDUCEPSZ128rmi 919812U, // VREDUCEPSZ128rmik 461156U, // VREDUCEPSZ128rmikz 32U, // VREDUCEPSZ128rri 2340U, // VREDUCEPSZ128rrik 624740U, // VREDUCEPSZ128rrikz 12U, // VREDUCEPSZ256rmbi 932580U, // VREDUCEPSZ256rmbik 473540U, // VREDUCEPSZ256rmbikz 0U, // VREDUCEPSZ256rmi 920164U, // VREDUCEPSZ256rmik 461124U, // VREDUCEPSZ256rmikz 32U, // VREDUCEPSZ256rri 2340U, // VREDUCEPSZ256rrik 624740U, // VREDUCEPSZ256rrikz 13U, // VREDUCEPSZrmbi 934628U, // VREDUCEPSZrmbik 475588U, // VREDUCEPSZrmbikz 0U, // VREDUCEPSZrmi 920612U, // VREDUCEPSZrmik 461220U, // VREDUCEPSZrmikz 32U, // VREDUCEPSZrri 11U, // VREDUCEPSZrrib 22820U, // VREDUCEPSZrribk 645220U, // VREDUCEPSZrribkz 2340U, // VREDUCEPSZrrik 624740U, // VREDUCEPSZrrikz 461184U, // VREDUCESDZrmi 37816612U, // VREDUCESDZrmik 54626404U, // VREDUCESDZrmikz 624736U, // VREDUCESDZrri 645216U, // VREDUCESDZrrib 77760804U, // VREDUCESDZrribk 94570596U, // VREDUCESDZrribkz 71469348U, // VREDUCESDZrrik 88279140U, // VREDUCESDZrrikz 461248U, // VREDUCESSZrmi 38144292U, // VREDUCESSZrmik 54954084U, // VREDUCESSZrmikz 624736U, // VREDUCESSZrri 645216U, // VREDUCESSZrrib 77760804U, // VREDUCESSZrribk 94570596U, // VREDUCESSZrribkz 71469348U, // VREDUCESSZrrik 88279140U, // VREDUCESSZrrikz 11U, // VRNDSCALEPDZ128rmbi 936516U, // VRNDSCALEPDZ128rmbik 477572U, // VRNDSCALEPDZ128rmbikz 0U, // VRNDSCALEPDZ128rmi 919812U, // VRNDSCALEPDZ128rmik 461156U, // VRNDSCALEPDZ128rmikz 32U, // VRNDSCALEPDZ128rri 2340U, // VRNDSCALEPDZ128rrik 624740U, // VRNDSCALEPDZ128rrikz 12U, // VRNDSCALEPDZ256rmbi 930372U, // VRNDSCALEPDZ256rmbik 471428U, // VRNDSCALEPDZ256rmbikz 0U, // VRNDSCALEPDZ256rmi 920164U, // VRNDSCALEPDZ256rmik 461124U, // VRNDSCALEPDZ256rmikz 32U, // VRNDSCALEPDZ256rri 2340U, // VRNDSCALEPDZ256rrik 624740U, // VRNDSCALEPDZ256rrikz 12U, // VRNDSCALEPDZrmbi 932420U, // VRNDSCALEPDZrmbik 473476U, // VRNDSCALEPDZrmbikz 0U, // VRNDSCALEPDZrmi 920612U, // VRNDSCALEPDZrmik 461220U, // VRNDSCALEPDZrmikz 32U, // VRNDSCALEPDZrri 11U, // VRNDSCALEPDZrrib 22820U, // VRNDSCALEPDZrribk 645220U, // VRNDSCALEPDZrribkz 2340U, // VRNDSCALEPDZrrik 624740U, // VRNDSCALEPDZrrikz 12U, // VRNDSCALEPSZ128rmbi 930532U, // VRNDSCALEPSZ128rmbik 471492U, // VRNDSCALEPSZ128rmbikz 0U, // VRNDSCALEPSZ128rmi 919812U, // VRNDSCALEPSZ128rmik 461156U, // VRNDSCALEPSZ128rmikz 32U, // VRNDSCALEPSZ128rri 2340U, // VRNDSCALEPSZ128rrik 624740U, // VRNDSCALEPSZ128rrikz 12U, // VRNDSCALEPSZ256rmbi 932580U, // VRNDSCALEPSZ256rmbik 473540U, // VRNDSCALEPSZ256rmbikz 0U, // VRNDSCALEPSZ256rmi 920164U, // VRNDSCALEPSZ256rmik 461124U, // VRNDSCALEPSZ256rmikz 32U, // VRNDSCALEPSZ256rri 2340U, // VRNDSCALEPSZ256rrik 624740U, // VRNDSCALEPSZ256rrikz 13U, // VRNDSCALEPSZrmbi 934628U, // VRNDSCALEPSZrmbik 475588U, // VRNDSCALEPSZrmbikz 0U, // VRNDSCALEPSZrmi 920612U, // VRNDSCALEPSZrmik 461220U, // VRNDSCALEPSZrmikz 32U, // VRNDSCALEPSZrri 11U, // VRNDSCALEPSZrrib 22820U, // VRNDSCALEPSZrribk 645220U, // VRNDSCALEPSZrribkz 2340U, // VRNDSCALEPSZrrik 624740U, // VRNDSCALEPSZrrikz 461184U, // VRNDSCALESDZm 461184U, // VRNDSCALESDZm_Int 37816612U, // VRNDSCALESDZm_Intk 54626404U, // VRNDSCALESDZm_Intkz 624736U, // VRNDSCALESDZr 624736U, // VRNDSCALESDZr_Int 71469348U, // VRNDSCALESDZr_Intk 88279140U, // VRNDSCALESDZr_Intkz 645216U, // VRNDSCALESDZrb_Int 77760804U, // VRNDSCALESDZrb_Intk 94570596U, // VRNDSCALESDZrb_Intkz 461248U, // VRNDSCALESSZm 461248U, // VRNDSCALESSZm_Int 38144292U, // VRNDSCALESSZm_Intk 54954084U, // VRNDSCALESSZm_Intkz 624736U, // VRNDSCALESSZr 624736U, // VRNDSCALESSZr_Int 71469348U, // VRNDSCALESSZr_Intk 88279140U, // VRNDSCALESSZr_Intkz 645216U, // VRNDSCALESSZrb_Int 77760804U, // VRNDSCALESSZrb_Intk 94570596U, // VRNDSCALESSZrb_Intkz 0U, // VROUNDPDYm 32U, // VROUNDPDYr 0U, // VROUNDPDm 32U, // VROUNDPDr 0U, // VROUNDPSYm 32U, // VROUNDPSYr 0U, // VROUNDPSm 32U, // VROUNDPSr 461184U, // VROUNDSDm 461184U, // VROUNDSDm_Int 624736U, // VROUNDSDr 624736U, // VROUNDSDr_Int 461248U, // VROUNDSSm 461248U, // VROUNDSSm_Int 624736U, // VROUNDSSr 624736U, // VROUNDSSr_Int 0U, // VRSQRT14PDZ128m 9U, // VRSQRT14PDZ128mb 4676U, // VRSQRT14PDZ128mbk 4484U, // VRSQRT14PDZ128mbkz 260U, // VRSQRT14PDZ128mk 356U, // VRSQRT14PDZ128mkz 0U, // VRSQRT14PDZ128r 292U, // VRSQRT14PDZ128rk 100U, // VRSQRT14PDZ128rkz 0U, // VRSQRT14PDZ256m 9U, // VRSQRT14PDZ256mb 6724U, // VRSQRT14PDZ256mbk 6532U, // VRSQRT14PDZ256mbkz 612U, // VRSQRT14PDZ256mk 324U, // VRSQRT14PDZ256mkz 0U, // VRSQRT14PDZ256r 292U, // VRSQRT14PDZ256rk 100U, // VRSQRT14PDZ256rkz 0U, // VRSQRT14PDZm 10U, // VRSQRT14PDZmb 8772U, // VRSQRT14PDZmbk 8580U, // VRSQRT14PDZmbkz 1060U, // VRSQRT14PDZmk 420U, // VRSQRT14PDZmkz 0U, // VRSQRT14PDZr 292U, // VRSQRT14PDZrk 100U, // VRSQRT14PDZrkz 0U, // VRSQRT14PSZ128m 9U, // VRSQRT14PSZ128mb 6884U, // VRSQRT14PSZ128mbk 6596U, // VRSQRT14PSZ128mbkz 260U, // VRSQRT14PSZ128mk 356U, // VRSQRT14PSZ128mkz 0U, // VRSQRT14PSZ128r 292U, // VRSQRT14PSZ128rk 100U, // VRSQRT14PSZ128rkz 0U, // VRSQRT14PSZ256m 10U, // VRSQRT14PSZ256mb 8932U, // VRSQRT14PSZ256mbk 8644U, // VRSQRT14PSZ256mbkz 612U, // VRSQRT14PSZ256mk 324U, // VRSQRT14PSZ256mkz 0U, // VRSQRT14PSZ256r 292U, // VRSQRT14PSZ256rk 100U, // VRSQRT14PSZ256rkz 0U, // VRSQRT14PSZm 10U, // VRSQRT14PSZmb 10980U, // VRSQRT14PSZmbk 10692U, // VRSQRT14PSZmbkz 1060U, // VRSQRT14PSZmk 420U, // VRSQRT14PSZmkz 0U, // VRSQRT14PSZr 292U, // VRSQRT14PSZrk 100U, // VRSQRT14PSZrkz 384U, // VRSQRT14SDZrm 67876U, // VRSQRT14SDZrmk 100452U, // VRSQRT14SDZrmkz 96U, // VRSQRT14SDZrr 166180U, // VRSQRT14SDZrrk 198756U, // VRSQRT14SDZrrkz 448U, // VRSQRT14SSZrm 395556U, // VRSQRT14SSZrmk 428132U, // VRSQRT14SSZrmkz 96U, // VRSQRT14SSZrr 166180U, // VRSQRT14SSZrrk 198756U, // VRSQRT14SSZrrkz 0U, // VRSQRT28PDZm 10U, // VRSQRT28PDZmb 8772U, // VRSQRT28PDZmbk 8580U, // VRSQRT28PDZmbkz 1060U, // VRSQRT28PDZmk 420U, // VRSQRT28PDZmkz 0U, // VRSQRT28PDZr 8U, // VRSQRT28PDZrb 20772U, // VRSQRT28PDZrbk 20580U, // VRSQRT28PDZrbkz 292U, // VRSQRT28PDZrk 100U, // VRSQRT28PDZrkz 0U, // VRSQRT28PSZm 10U, // VRSQRT28PSZmb 10980U, // VRSQRT28PSZmbk 10692U, // VRSQRT28PSZmbkz 1060U, // VRSQRT28PSZmk 420U, // VRSQRT28PSZmkz 0U, // VRSQRT28PSZr 8U, // VRSQRT28PSZrb 20772U, // VRSQRT28PSZrbk 20580U, // VRSQRT28PSZrbkz 292U, // VRSQRT28PSZrk 100U, // VRSQRT28PSZrkz 384U, // VRSQRT28SDZm 67876U, // VRSQRT28SDZmk 100452U, // VRSQRT28SDZmkz 96U, // VRSQRT28SDZr 20576U, // VRSQRT28SDZrb 11700516U, // VRSQRT28SDZrbk 11733092U, // VRSQRT28SDZrbkz 166180U, // VRSQRT28SDZrk 198756U, // VRSQRT28SDZrkz 448U, // VRSQRT28SSZm 395556U, // VRSQRT28SSZmk 428132U, // VRSQRT28SSZmkz 96U, // VRSQRT28SSZr 20576U, // VRSQRT28SSZrb 11700516U, // VRSQRT28SSZrbk 11733092U, // VRSQRT28SSZrbkz 166180U, // VRSQRT28SSZrk 198756U, // VRSQRT28SSZrkz 0U, // VRSQRTPSYm 0U, // VRSQRTPSYr 0U, // VRSQRTPSm 0U, // VRSQRTPSr 448U, // VRSQRTSSm 448U, // VRSQRTSSm_Int 96U, // VRSQRTSSr 96U, // VRSQRTSSr_Int 352U, // VSCALEFPDZ128rm 4480U, // VSCALEFPDZ128rmb 1116452U, // VSCALEFPDZ128rmbk 1149028U, // VSCALEFPDZ128rmbkz 35108U, // VSCALEFPDZ128rmk 133220U, // VSCALEFPDZ128rmkz 96U, // VSCALEFPDZ128rr 166180U, // VSCALEFPDZ128rrk 198756U, // VSCALEFPDZ128rrkz 320U, // VSCALEFPDZ256rm 6528U, // VSCALEFPDZ256rmb 2165028U, // VSCALEFPDZ256rmbk 2197604U, // VSCALEFPDZ256rmbkz 231716U, // VSCALEFPDZ256rmk 264292U, // VSCALEFPDZ256rmkz 96U, // VSCALEFPDZ256rr 166180U, // VSCALEFPDZ256rrk 198756U, // VSCALEFPDZ256rrkz 416U, // VSCALEFPDZrm 8576U, // VSCALEFPDZrmb 3213604U, // VSCALEFPDZrmbk 3246180U, // VSCALEFPDZrmbkz 297252U, // VSCALEFPDZrmk 329828U, // VSCALEFPDZrmkz 96U, // VSCALEFPDZrr 362592U, // VSCALEFPDZrrb 4360484U, // VSCALEFPDZrrbk 21170276U, // VSCALEFPDZrrbkz 166180U, // VSCALEFPDZrrk 198756U, // VSCALEFPDZrrkz 352U, // VSCALEFPSZ128rm 6592U, // VSCALEFPSZ128rmb 2492708U, // VSCALEFPSZ128rmbk 2525284U, // VSCALEFPSZ128rmbkz 35108U, // VSCALEFPSZ128rmk 133220U, // VSCALEFPSZ128rmkz 96U, // VSCALEFPSZ128rr 166180U, // VSCALEFPSZ128rrk 198756U, // VSCALEFPSZ128rrkz 320U, // VSCALEFPSZ256rm 8640U, // VSCALEFPSZ256rmb 3541284U, // VSCALEFPSZ256rmbk 3573860U, // VSCALEFPSZ256rmbkz 231716U, // VSCALEFPSZ256rmk 264292U, // VSCALEFPSZ256rmkz 96U, // VSCALEFPSZ256rr 166180U, // VSCALEFPSZ256rrk 198756U, // VSCALEFPSZ256rrkz 416U, // VSCALEFPSZrm 10688U, // VSCALEFPSZrmb 5638436U, // VSCALEFPSZrmbk 5671012U, // VSCALEFPSZrmbkz 297252U, // VSCALEFPSZrmk 329828U, // VSCALEFPSZrmkz 96U, // VSCALEFPSZrr 362592U, // VSCALEFPSZrrb 4360484U, // VSCALEFPSZrrbk 21170276U, // VSCALEFPSZrrbkz 166180U, // VSCALEFPSZrrk 198756U, // VSCALEFPSZrrkz 384U, // VSCALEFSDZrm 67876U, // VSCALEFSDZrmk 100452U, // VSCALEFSDZrmkz 96U, // VSCALEFSDZrr 362592U, // VSCALEFSDZrrb_Int 4360484U, // VSCALEFSDZrrb_Intk 21170276U, // VSCALEFSDZrrb_Intkz 166180U, // VSCALEFSDZrrk 198756U, // VSCALEFSDZrrkz 448U, // VSCALEFSSZrm 395556U, // VSCALEFSSZrmk 428132U, // VSCALEFSSZrmkz 96U, // VSCALEFSSZrr 362592U, // VSCALEFSSZrrb_Int 4360484U, // VSCALEFSSZrrb_Intk 21170276U, // VSCALEFSSZrrb_Intkz 166180U, // VSCALEFSSZrrk 198756U, // VSCALEFSSZrrkz 0U, // VSCATTERDPDZ128mr 0U, // VSCATTERDPDZ256mr 0U, // VSCATTERDPDZmr 0U, // VSCATTERDPSZ128mr 0U, // VSCATTERDPSZ256mr 0U, // VSCATTERDPSZmr 0U, // VSCATTERPF0DPDm 0U, // VSCATTERPF0DPSm 0U, // VSCATTERPF0QPDm 0U, // VSCATTERPF0QPSm 0U, // VSCATTERPF1DPDm 0U, // VSCATTERPF1DPSm 0U, // VSCATTERPF1QPDm 0U, // VSCATTERPF1QPSm 0U, // VSCATTERQPDZ128mr 0U, // VSCATTERQPDZ256mr 0U, // VSCATTERQPDZmr 0U, // VSCATTERQPSZ128mr 0U, // VSCATTERQPSZ256mr 0U, // VSCATTERQPSZmr 473536U, // VSHUFF32X4Z256rmbi 41290020U, // VSHUFF32X4Z256rmbik 58099812U, // VSHUFF32X4Z256rmbikz 461120U, // VSHUFF32X4Z256rmi 37980452U, // VSHUFF32X4Z256rmik 54790244U, // VSHUFF32X4Z256rmikz 624736U, // VSHUFF32X4Z256rri 71469348U, // VSHUFF32X4Z256rrik 88279140U, // VSHUFF32X4Z256rrikz 475584U, // VSHUFF32X4Zrmbi 42338596U, // VSHUFF32X4Zrmbik 59148388U, // VSHUFF32X4Zrmbikz 461216U, // VSHUFF32X4Zrmi 38045988U, // VSHUFF32X4Zrmik 54855780U, // VSHUFF32X4Zrmikz 624736U, // VSHUFF32X4Zrri 71469348U, // VSHUFF32X4Zrrik 88279140U, // VSHUFF32X4Zrrikz 471424U, // VSHUFF64X2Z256rmbi 39913764U, // VSHUFF64X2Z256rmbik 56723556U, // VSHUFF64X2Z256rmbikz 461120U, // VSHUFF64X2Z256rmi 37980452U, // VSHUFF64X2Z256rmik 54790244U, // VSHUFF64X2Z256rmikz 624736U, // VSHUFF64X2Z256rri 71469348U, // VSHUFF64X2Z256rrik 88279140U, // VSHUFF64X2Z256rrikz 473472U, // VSHUFF64X2Zrmbi 40962340U, // VSHUFF64X2Zrmbik 57772132U, // VSHUFF64X2Zrmbikz 461216U, // VSHUFF64X2Zrmi 38045988U, // VSHUFF64X2Zrmik 54855780U, // VSHUFF64X2Zrmikz 624736U, // VSHUFF64X2Zrri 71469348U, // VSHUFF64X2Zrrik 88279140U, // VSHUFF64X2Zrrikz 473152U, // VSHUFI32X4Z256rmbi 41388324U, // VSHUFI32X4Z256rmbik 58198116U, // VSHUFI32X4Z256rmbikz 461280U, // VSHUFI32X4Z256rmi 38406436U, // VSHUFI32X4Z256rmik 55216228U, // VSHUFI32X4Z256rmikz 624736U, // VSHUFI32X4Z256rri 71469348U, // VSHUFI32X4Z256rrik 88279140U, // VSHUFI32X4Z256rrikz 475200U, // VSHUFI32X4Zrmbi 42436900U, // VSHUFI32X4Zrmbik 59246692U, // VSHUFI32X4Zrmbikz 461344U, // VSHUFI32X4Zrmi 38471972U, // VSHUFI32X4Zrmik 55281764U, // VSHUFI32X4Zrmikz 624736U, // VSHUFI32X4Zrri 71469348U, // VSHUFI32X4Zrrik 88279140U, // VSHUFI32X4Zrrikz 471168U, // VSHUFI64X2Z256rmbi 40634660U, // VSHUFI64X2Z256rmbik 57444452U, // VSHUFI64X2Z256rmbikz 461280U, // VSHUFI64X2Z256rmi 38406436U, // VSHUFI64X2Z256rmik 55216228U, // VSHUFI64X2Z256rmikz 624736U, // VSHUFI64X2Z256rri 71469348U, // VSHUFI64X2Z256rrik 88279140U, // VSHUFI64X2Z256rrikz 473216U, // VSHUFI64X2Zrmbi 41683236U, // VSHUFI64X2Zrmbik 58493028U, // VSHUFI64X2Zrmbikz 461344U, // VSHUFI64X2Zrmi 38471972U, // VSHUFI64X2Zrmik 55281764U, // VSHUFI64X2Zrmikz 624736U, // VSHUFI64X2Zrri 71469348U, // VSHUFI64X2Zrrik 88279140U, // VSHUFI64X2Zrrikz 461120U, // VSHUFPDYrmi 624736U, // VSHUFPDYrri 477568U, // VSHUFPDZ128rmbi 43059492U, // VSHUFPDZ128rmbik 59869284U, // VSHUFPDZ128rmbikz 461152U, // VSHUFPDZ128rmi 37783844U, // VSHUFPDZ128rmik 54659172U, // VSHUFPDZ128rmikz 624736U, // VSHUFPDZ128rri 71469348U, // VSHUFPDZ128rrik 88279140U, // VSHUFPDZ128rrikz 471424U, // VSHUFPDZ256rmbi 39913764U, // VSHUFPDZ256rmbik 56723556U, // VSHUFPDZ256rmbikz 461120U, // VSHUFPDZ256rmi 37980452U, // VSHUFPDZ256rmik 54790244U, // VSHUFPDZ256rmikz 624736U, // VSHUFPDZ256rri 71469348U, // VSHUFPDZ256rrik 88279140U, // VSHUFPDZ256rrikz 473472U, // VSHUFPDZrmbi 40962340U, // VSHUFPDZrmbik 57772132U, // VSHUFPDZrmbikz 461216U, // VSHUFPDZrmi 38045988U, // VSHUFPDZrmik 54855780U, // VSHUFPDZrmikz 624736U, // VSHUFPDZrri 71469348U, // VSHUFPDZrrik 88279140U, // VSHUFPDZrrikz 461152U, // VSHUFPDrmi 624736U, // VSHUFPDrri 461120U, // VSHUFPSYrmi 624736U, // VSHUFPSYrri 471488U, // VSHUFPSZ128rmbi 40241444U, // VSHUFPSZ128rmbik 57051236U, // VSHUFPSZ128rmbikz 461152U, // VSHUFPSZ128rmi 37783844U, // VSHUFPSZ128rmik 54659172U, // VSHUFPSZ128rmikz 624736U, // VSHUFPSZ128rri 71469348U, // VSHUFPSZ128rrik 88279140U, // VSHUFPSZ128rrikz 473536U, // VSHUFPSZ256rmbi 41290020U, // VSHUFPSZ256rmbik 58099812U, // VSHUFPSZ256rmbikz 461120U, // VSHUFPSZ256rmi 37980452U, // VSHUFPSZ256rmik 54790244U, // VSHUFPSZ256rmikz 624736U, // VSHUFPSZ256rri 71469348U, // VSHUFPSZ256rrik 88279140U, // VSHUFPSZ256rrikz 475584U, // VSHUFPSZrmbi 42338596U, // VSHUFPSZrmbik 59148388U, // VSHUFPSZrmbikz 461216U, // VSHUFPSZrmi 38045988U, // VSHUFPSZrmik 54855780U, // VSHUFPSZrmikz 624736U, // VSHUFPSZrri 71469348U, // VSHUFPSZrrik 88279140U, // VSHUFPSZrrikz 461152U, // VSHUFPSrmi 624736U, // VSHUFPSrri 0U, // VSQRTPDYm 0U, // VSQRTPDYr 0U, // VSQRTPDZ128m 9U, // VSQRTPDZ128mb 4676U, // VSQRTPDZ128mbk 4484U, // VSQRTPDZ128mbkz 260U, // VSQRTPDZ128mk 356U, // VSQRTPDZ128mkz 0U, // VSQRTPDZ128r 292U, // VSQRTPDZ128rk 100U, // VSQRTPDZ128rkz 0U, // VSQRTPDZ256m 9U, // VSQRTPDZ256mb 6724U, // VSQRTPDZ256mbk 6532U, // VSQRTPDZ256mbkz 612U, // VSQRTPDZ256mk 324U, // VSQRTPDZ256mkz 0U, // VSQRTPDZ256r 292U, // VSQRTPDZ256rk 100U, // VSQRTPDZ256rkz 0U, // VSQRTPDZm 10U, // VSQRTPDZmb 8772U, // VSQRTPDZmbk 8580U, // VSQRTPDZmbkz 1060U, // VSQRTPDZmk 420U, // VSQRTPDZmkz 0U, // VSQRTPDZr 1024U, // VSQRTPDZrb 887076U, // VSQRTPDZrbk 362596U, // VSQRTPDZrbkz 292U, // VSQRTPDZrk 100U, // VSQRTPDZrkz 0U, // VSQRTPDm 0U, // VSQRTPDr 0U, // VSQRTPSYm 0U, // VSQRTPSYr 0U, // VSQRTPSZ128m 9U, // VSQRTPSZ128mb 6884U, // VSQRTPSZ128mbk 6596U, // VSQRTPSZ128mbkz 260U, // VSQRTPSZ128mk 356U, // VSQRTPSZ128mkz 0U, // VSQRTPSZ128r 292U, // VSQRTPSZ128rk 100U, // VSQRTPSZ128rkz 0U, // VSQRTPSZ256m 10U, // VSQRTPSZ256mb 8932U, // VSQRTPSZ256mbk 8644U, // VSQRTPSZ256mbkz 612U, // VSQRTPSZ256mk 324U, // VSQRTPSZ256mkz 0U, // VSQRTPSZ256r 292U, // VSQRTPSZ256rk 100U, // VSQRTPSZ256rkz 0U, // VSQRTPSZm 10U, // VSQRTPSZmb 10980U, // VSQRTPSZmbk 10692U, // VSQRTPSZmbkz 1060U, // VSQRTPSZmk 420U, // VSQRTPSZmkz 0U, // VSQRTPSZr 1024U, // VSQRTPSZrb 887076U, // VSQRTPSZrbk 362596U, // VSQRTPSZrbkz 292U, // VSQRTPSZrk 100U, // VSQRTPSZrkz 0U, // VSQRTPSm 0U, // VSQRTPSr 384U, // VSQRTSDZm 384U, // VSQRTSDZm_Int 67876U, // VSQRTSDZm_Intk 100452U, // VSQRTSDZm_Intkz 96U, // VSQRTSDZr 96U, // VSQRTSDZr_Int 166180U, // VSQRTSDZr_Intk 198756U, // VSQRTSDZr_Intkz 362592U, // VSQRTSDZrb_Int 4360484U, // VSQRTSDZrb_Intk 21170276U, // VSQRTSDZrb_Intkz 384U, // VSQRTSDm 384U, // VSQRTSDm_Int 96U, // VSQRTSDr 96U, // VSQRTSDr_Int 448U, // VSQRTSSZm 448U, // VSQRTSSZm_Int 395556U, // VSQRTSSZm_Intk 428132U, // VSQRTSSZm_Intkz 96U, // VSQRTSSZr 96U, // VSQRTSSZr_Int 166180U, // VSQRTSSZr_Intk 198756U, // VSQRTSSZr_Intkz 362592U, // VSQRTSSZrb_Int 4360484U, // VSQRTSSZrb_Intk 21170276U, // VSQRTSSZrb_Intkz 448U, // VSQRTSSm 448U, // VSQRTSSm_Int 96U, // VSQRTSSr 96U, // VSQRTSSr_Int 0U, // VSTMXCSR 320U, // VSUBPDYrm 96U, // VSUBPDYrr 352U, // VSUBPDZ128rm 4480U, // VSUBPDZ128rmb 1116452U, // VSUBPDZ128rmbk 1149028U, // VSUBPDZ128rmbkz 35108U, // VSUBPDZ128rmk 133220U, // VSUBPDZ128rmkz 96U, // VSUBPDZ128rr 166180U, // VSUBPDZ128rrk 198756U, // VSUBPDZ128rrkz 320U, // VSUBPDZ256rm 6528U, // VSUBPDZ256rmb 2165028U, // VSUBPDZ256rmbk 2197604U, // VSUBPDZ256rmbkz 231716U, // VSUBPDZ256rmk 264292U, // VSUBPDZ256rmkz 96U, // VSUBPDZ256rr 166180U, // VSUBPDZ256rrk 198756U, // VSUBPDZ256rrkz 416U, // VSUBPDZrm 8576U, // VSUBPDZrmb 3213604U, // VSUBPDZrmbk 3246180U, // VSUBPDZrmbkz 297252U, // VSUBPDZrmk 329828U, // VSUBPDZrmkz 96U, // VSUBPDZrr 362592U, // VSUBPDZrrb 4360484U, // VSUBPDZrrbk 21170276U, // VSUBPDZrrbkz 166180U, // VSUBPDZrrk 198756U, // VSUBPDZrrkz 352U, // VSUBPDrm 96U, // VSUBPDrr 320U, // VSUBPSYrm 96U, // VSUBPSYrr 352U, // VSUBPSZ128rm 6592U, // VSUBPSZ128rmb 2492708U, // VSUBPSZ128rmbk 2525284U, // VSUBPSZ128rmbkz 35108U, // VSUBPSZ128rmk 133220U, // VSUBPSZ128rmkz 96U, // VSUBPSZ128rr 166180U, // VSUBPSZ128rrk 198756U, // VSUBPSZ128rrkz 320U, // VSUBPSZ256rm 8640U, // VSUBPSZ256rmb 3541284U, // VSUBPSZ256rmbk 3573860U, // VSUBPSZ256rmbkz 231716U, // VSUBPSZ256rmk 264292U, // VSUBPSZ256rmkz 96U, // VSUBPSZ256rr 166180U, // VSUBPSZ256rrk 198756U, // VSUBPSZ256rrkz 416U, // VSUBPSZrm 10688U, // VSUBPSZrmb 5638436U, // VSUBPSZrmbk 5671012U, // VSUBPSZrmbkz 297252U, // VSUBPSZrmk 329828U, // VSUBPSZrmkz 96U, // VSUBPSZrr 362592U, // VSUBPSZrrb 4360484U, // VSUBPSZrrbk 21170276U, // VSUBPSZrrbkz 166180U, // VSUBPSZrrk 198756U, // VSUBPSZrrkz 352U, // VSUBPSrm 96U, // VSUBPSrr 384U, // VSUBSDZrm 384U, // VSUBSDZrm_Int 67876U, // VSUBSDZrm_Intk 100452U, // VSUBSDZrm_Intkz 96U, // VSUBSDZrr 96U, // VSUBSDZrr_Int 166180U, // VSUBSDZrr_Intk 198756U, // VSUBSDZrr_Intkz 362592U, // VSUBSDZrrb_Int 4360484U, // VSUBSDZrrb_Intk 21170276U, // VSUBSDZrrb_Intkz 384U, // VSUBSDrm 384U, // VSUBSDrm_Int 96U, // VSUBSDrr 96U, // VSUBSDrr_Int 448U, // VSUBSSZrm 448U, // VSUBSSZrm_Int 395556U, // VSUBSSZrm_Intk 428132U, // VSUBSSZrm_Intkz 96U, // VSUBSSZrr 96U, // VSUBSSZrr_Int 166180U, // VSUBSSZrr_Intk 198756U, // VSUBSSZrr_Intkz 362592U, // VSUBSSZrrb_Int 4360484U, // VSUBSSZrrb_Intk 21170276U, // VSUBSSZrrb_Intkz 448U, // VSUBSSrm 448U, // VSUBSSrm_Int 96U, // VSUBSSrr 96U, // VSUBSSrr_Int 0U, // VTESTPDYrm 0U, // VTESTPDYrr 0U, // VTESTPDrm 0U, // VTESTPDrr 0U, // VTESTPSYrm 0U, // VTESTPSYrr 0U, // VTESTPSrm 0U, // VTESTPSrr 0U, // VUCOMISDZrm 0U, // VUCOMISDZrm_Int 0U, // VUCOMISDZrr 0U, // VUCOMISDZrr_Int 8U, // VUCOMISDZrrb 0U, // VUCOMISDrm 0U, // VUCOMISDrm_Int 0U, // VUCOMISDrr 0U, // VUCOMISDrr_Int 0U, // VUCOMISSZrm 0U, // VUCOMISSZrm_Int 0U, // VUCOMISSZrr 0U, // VUCOMISSZrr_Int 8U, // VUCOMISSZrrb 0U, // VUCOMISSrm 0U, // VUCOMISSrm_Int 0U, // VUCOMISSrr 0U, // VUCOMISSrr_Int 320U, // VUNPCKHPDYrm 96U, // VUNPCKHPDYrr 352U, // VUNPCKHPDZ128rm 4480U, // VUNPCKHPDZ128rmb 1116452U, // VUNPCKHPDZ128rmbk 1149028U, // VUNPCKHPDZ128rmbkz 35108U, // VUNPCKHPDZ128rmk 133220U, // VUNPCKHPDZ128rmkz 96U, // VUNPCKHPDZ128rr 166180U, // VUNPCKHPDZ128rrk 198756U, // VUNPCKHPDZ128rrkz 320U, // VUNPCKHPDZ256rm 6528U, // VUNPCKHPDZ256rmb 2165028U, // VUNPCKHPDZ256rmbk 2197604U, // VUNPCKHPDZ256rmbkz 231716U, // VUNPCKHPDZ256rmk 264292U, // VUNPCKHPDZ256rmkz 96U, // VUNPCKHPDZ256rr 166180U, // VUNPCKHPDZ256rrk 198756U, // VUNPCKHPDZ256rrkz 416U, // VUNPCKHPDZrm 8576U, // VUNPCKHPDZrmb 3213604U, // VUNPCKHPDZrmbk 3246180U, // VUNPCKHPDZrmbkz 297252U, // VUNPCKHPDZrmk 329828U, // VUNPCKHPDZrmkz 96U, // VUNPCKHPDZrr 166180U, // VUNPCKHPDZrrk 198756U, // VUNPCKHPDZrrkz 352U, // VUNPCKHPDrm 96U, // VUNPCKHPDrr 320U, // VUNPCKHPSYrm 96U, // VUNPCKHPSYrr 352U, // VUNPCKHPSZ128rm 6592U, // VUNPCKHPSZ128rmb 2492708U, // VUNPCKHPSZ128rmbk 2525284U, // VUNPCKHPSZ128rmbkz 35108U, // VUNPCKHPSZ128rmk 133220U, // VUNPCKHPSZ128rmkz 96U, // VUNPCKHPSZ128rr 166180U, // VUNPCKHPSZ128rrk 198756U, // VUNPCKHPSZ128rrkz 320U, // VUNPCKHPSZ256rm 8640U, // VUNPCKHPSZ256rmb 3541284U, // VUNPCKHPSZ256rmbk 3573860U, // VUNPCKHPSZ256rmbkz 231716U, // VUNPCKHPSZ256rmk 264292U, // VUNPCKHPSZ256rmkz 96U, // VUNPCKHPSZ256rr 166180U, // VUNPCKHPSZ256rrk 198756U, // VUNPCKHPSZ256rrkz 416U, // VUNPCKHPSZrm 10688U, // VUNPCKHPSZrmb 5638436U, // VUNPCKHPSZrmbk 5671012U, // VUNPCKHPSZrmbkz 297252U, // VUNPCKHPSZrmk 329828U, // VUNPCKHPSZrmkz 96U, // VUNPCKHPSZrr 166180U, // VUNPCKHPSZrrk 198756U, // VUNPCKHPSZrrkz 352U, // VUNPCKHPSrm 96U, // VUNPCKHPSrr 320U, // VUNPCKLPDYrm 96U, // VUNPCKLPDYrr 352U, // VUNPCKLPDZ128rm 4480U, // VUNPCKLPDZ128rmb 1116452U, // VUNPCKLPDZ128rmbk 1149028U, // VUNPCKLPDZ128rmbkz 35108U, // VUNPCKLPDZ128rmk 133220U, // VUNPCKLPDZ128rmkz 96U, // VUNPCKLPDZ128rr 166180U, // VUNPCKLPDZ128rrk 198756U, // VUNPCKLPDZ128rrkz 320U, // VUNPCKLPDZ256rm 6528U, // VUNPCKLPDZ256rmb 2165028U, // VUNPCKLPDZ256rmbk 2197604U, // VUNPCKLPDZ256rmbkz 231716U, // VUNPCKLPDZ256rmk 264292U, // VUNPCKLPDZ256rmkz 96U, // VUNPCKLPDZ256rr 166180U, // VUNPCKLPDZ256rrk 198756U, // VUNPCKLPDZ256rrkz 416U, // VUNPCKLPDZrm 8576U, // VUNPCKLPDZrmb 3213604U, // VUNPCKLPDZrmbk 3246180U, // VUNPCKLPDZrmbkz 297252U, // VUNPCKLPDZrmk 329828U, // VUNPCKLPDZrmkz 96U, // VUNPCKLPDZrr 166180U, // VUNPCKLPDZrrk 198756U, // VUNPCKLPDZrrkz 352U, // VUNPCKLPDrm 96U, // VUNPCKLPDrr 320U, // VUNPCKLPSYrm 96U, // VUNPCKLPSYrr 352U, // VUNPCKLPSZ128rm 6592U, // VUNPCKLPSZ128rmb 2492708U, // VUNPCKLPSZ128rmbk 2525284U, // VUNPCKLPSZ128rmbkz 35108U, // VUNPCKLPSZ128rmk 133220U, // VUNPCKLPSZ128rmkz 96U, // VUNPCKLPSZ128rr 166180U, // VUNPCKLPSZ128rrk 198756U, // VUNPCKLPSZ128rrkz 320U, // VUNPCKLPSZ256rm 8640U, // VUNPCKLPSZ256rmb 3541284U, // VUNPCKLPSZ256rmbk 3573860U, // VUNPCKLPSZ256rmbkz 231716U, // VUNPCKLPSZ256rmk 264292U, // VUNPCKLPSZ256rmkz 96U, // VUNPCKLPSZ256rr 166180U, // VUNPCKLPSZ256rrk 198756U, // VUNPCKLPSZ256rrkz 416U, // VUNPCKLPSZrm 10688U, // VUNPCKLPSZrmb 5638436U, // VUNPCKLPSZrmbk 5671012U, // VUNPCKLPSZrmbkz 297252U, // VUNPCKLPSZrmk 329828U, // VUNPCKLPSZrmkz 96U, // VUNPCKLPSZrr 166180U, // VUNPCKLPSZrrk 198756U, // VUNPCKLPSZrrkz 352U, // VUNPCKLPSrm 96U, // VUNPCKLPSrr 320U, // VXORPDYrm 96U, // VXORPDYrr 352U, // VXORPDZ128rm 4480U, // VXORPDZ128rmb 1116452U, // VXORPDZ128rmbk 1149028U, // VXORPDZ128rmbkz 35108U, // VXORPDZ128rmk 133220U, // VXORPDZ128rmkz 96U, // VXORPDZ128rr 166180U, // VXORPDZ128rrk 198756U, // VXORPDZ128rrkz 320U, // VXORPDZ256rm 6528U, // VXORPDZ256rmb 2165028U, // VXORPDZ256rmbk 2197604U, // VXORPDZ256rmbkz 231716U, // VXORPDZ256rmk 264292U, // VXORPDZ256rmkz 96U, // VXORPDZ256rr 166180U, // VXORPDZ256rrk 198756U, // VXORPDZ256rrkz 416U, // VXORPDZrm 8576U, // VXORPDZrmb 3213604U, // VXORPDZrmbk 3246180U, // VXORPDZrmbkz 297252U, // VXORPDZrmk 329828U, // VXORPDZrmkz 96U, // VXORPDZrr 166180U, // VXORPDZrrk 198756U, // VXORPDZrrkz 352U, // VXORPDrm 96U, // VXORPDrr 320U, // VXORPSYrm 96U, // VXORPSYrr 352U, // VXORPSZ128rm 6592U, // VXORPSZ128rmb 2492708U, // VXORPSZ128rmbk 2525284U, // VXORPSZ128rmbkz 35108U, // VXORPSZ128rmk 133220U, // VXORPSZ128rmkz 96U, // VXORPSZ128rr 166180U, // VXORPSZ128rrk 198756U, // VXORPSZ128rrkz 320U, // VXORPSZ256rm 8640U, // VXORPSZ256rmb 3541284U, // VXORPSZ256rmbk 3573860U, // VXORPSZ256rmbkz 231716U, // VXORPSZ256rmk 264292U, // VXORPSZ256rmkz 96U, // VXORPSZ256rr 166180U, // VXORPSZ256rrk 198756U, // VXORPSZ256rrkz 416U, // VXORPSZrm 10688U, // VXORPSZrmb 5638436U, // VXORPSZrmbk 5671012U, // VXORPSZrmbkz 297252U, // VXORPSZrmk 329828U, // VXORPSZrmkz 96U, // VXORPSZrr 166180U, // VXORPSZrrk 198756U, // VXORPSZrrkz 352U, // VXORPSrm 96U, // VXORPSrr 0U, // VZEROALL 0U, // VZEROUPPER 0U, // WAIT 0U, // WBINVD 0U, // WBNOINVD 0U, // WRFSBASE 0U, // WRFSBASE64 0U, // WRGSBASE 0U, // WRGSBASE64 0U, // WRMSR 0U, // WRPKRUr 0U, // WRSSD 0U, // WRSSQ 0U, // WRUSSD 0U, // WRUSSQ 0U, // XABORT 0U, // XACQUIRE_PREFIX 0U, // XADD16rm 0U, // XADD16rr 0U, // XADD32rm 0U, // XADD32rr 0U, // XADD64rm 0U, // XADD64rr 0U, // XADD8rm 0U, // XADD8rr 0U, // XBEGIN_2 0U, // XBEGIN_4 0U, // XCHG16ar 0U, // XCHG16rm 0U, // XCHG16rr 0U, // XCHG32ar 0U, // XCHG32rm 0U, // XCHG32rr 0U, // XCHG64ar 0U, // XCHG64rm 0U, // XCHG64rr 0U, // XCHG8rm 0U, // XCHG8rr 0U, // XCH_F 0U, // XCRYPTCBC 0U, // XCRYPTCFB 0U, // XCRYPTCTR 0U, // XCRYPTECB 0U, // XCRYPTOFB 0U, // XEND 0U, // XGETBV 0U, // XLAT 0U, // XOR16i16 0U, // XOR16mi 0U, // XOR16mi8 0U, // XOR16mr 0U, // XOR16ri 0U, // XOR16ri8 0U, // XOR16rm 0U, // XOR16rr 0U, // XOR16rr_REV 0U, // XOR32i32 0U, // XOR32mi 0U, // XOR32mi8 0U, // XOR32mr 0U, // XOR32ri 0U, // XOR32ri8 0U, // XOR32rm 0U, // XOR32rr 0U, // XOR32rr_REV 0U, // XOR64i32 0U, // XOR64mi32 0U, // XOR64mi8 0U, // XOR64mr 0U, // XOR64ri32 0U, // XOR64ri8 0U, // XOR64rm 0U, // XOR64rr 0U, // XOR64rr_REV 0U, // XOR8i8 0U, // XOR8mi 0U, // XOR8mi8 0U, // XOR8mr 0U, // XOR8ri 0U, // XOR8ri8 0U, // XOR8rm 0U, // XOR8rr 0U, // XOR8rr_REV 0U, // XORPDrm 0U, // XORPDrr 0U, // XORPSrm 0U, // XORPSrr 0U, // XRELEASE_PREFIX 0U, // XRSTOR 0U, // XRSTOR64 0U, // XRSTORS 0U, // XRSTORS64 0U, // XSAVE 0U, // XSAVE64 0U, // XSAVEC 0U, // XSAVEC64 0U, // XSAVEOPT 0U, // XSAVEOPT64 0U, // XSAVES 0U, // XSAVES64 0U, // XSETBV 0U, // XSHA1 0U, // XSHA256 0U, // XSTORE 0U, // XTEST }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint64_t Bits = 0; Bits |= (uint64_t)OpInfo0[opcode] << 0; Bits |= (uint64_t)OpInfo1[opcode] << 32; #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 16383)-1); #endif // Fragment 0 encoded into 6 bits for 52 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 63)); switch ((Bits >> 14) & 63) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // AAD8i8, AAM8i8, ADC16i16, ADC16rr_REV, ADC32i32, ADC32rr_REV, ADC64i32... printOperand(MI, 0, O); break; case 2: // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, ADD_FI16m, AND... printi16mem(MI, 0, O); break; case 3: // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... printOperand(MI, 1, O); break; case 4: // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, ADD_FI32m, AND... printi32mem(MI, 0, O); break; case 5: // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... printi64mem(MI, 0, O); break; case 6: // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... printi8mem(MI, 0, O); break; case 7: // ADD_F32m, DIVR_F32m, DIV_F32m, EXTRACTPSmr, FCOM32m, FCOMP32m, FLDENVm... printf32mem(MI, 0, O); break; case 8: // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MOVHPDmr, M... printf64mem(MI, 0, O); break; case 9: // BNDMOV64mr, CMPXCHG16B, MOVDQAmr, MOVDQUmr, VEXTRACTI128mr, VEXTRACTI3... printi128mem(MI, 0, O); break; case 10: // BNDSTXmr printanymem(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 11: // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... printPCRelImm(MI, 0, O); return; break; case 12: // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSDrm_Int, CMPSSrm, CMPSSrm_Int, VCMPPD... printSSEAVXCC(MI, 7, O); break; case 13: // CMPPDrri, CMPPSrri, CMPSDrr, CMPSDrr_Int, CMPSSrr, CMPSSrr_Int, VCMPPD... printSSEAVXCC(MI, 3, O); break; case 14: // CMPSB printSrcIdx8(MI, 1, O); SStream_concat0(O, ", "); printDstIdx8(MI, 0, O); return; break; case 15: // CMPSL printSrcIdx32(MI, 1, O); SStream_concat0(O, ", "); printDstIdx32(MI, 0, O); return; break; case 16: // CMPSQ printSrcIdx64(MI, 1, O); SStream_concat0(O, ", "); printDstIdx64(MI, 0, O); return; break; case 17: // CMPSW printSrcIdx16(MI, 1, O); SStream_concat0(O, ", "); printDstIdx16(MI, 0, O); return; break; case 18: // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR... printopaquemem(MI, 0, O); return; break; case 19: // FBLDm, FBSTPm, LD_F80m, ST_FP80m printf80mem(MI, 0, O); return; break; case 20: // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir printU8Imm(MI, 0, O); break; case 21: // INSB, MOVSB, SCASB, STOSB printDstIdx8(MI, 0, O); break; case 22: // INSL, MOVSL, SCASL, STOSL printDstIdx32(MI, 0, O); break; case 23: // INSW, MOVSW, SCASW, STOSW printDstIdx16(MI, 0, O); break; case 24: // LODSB, OUTSB printSrcIdx8(MI, 0, O); return; break; case 25: // LODSL, OUTSL printSrcIdx32(MI, 0, O); return; break; case 26: // LODSQ printSrcIdx64(MI, 0, O); return; break; case 27: // LODSW, OUTSW printSrcIdx16(MI, 0, O); return; break; case 28: // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a printMemOffs16(MI, 0, O); break; case 29: // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a printMemOffs32(MI, 0, O); break; case 30: // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a printMemOffs64(MI, 0, O); break; case 31: // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a printMemOffs8(MI, 0, O); break; case 32: // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVNTPDmr, MOVNTPSmr, MOVUPDmr, MOVUPSm... printf128mem(MI, 0, O); break; case 33: // MOVSQ, SCASQ, STOSQ printDstIdx64(MI, 0, O); break; case 34: // VCMPPDZ128rmbik, VCMPPDZ128rmik, VCMPPDZ256rmbik, VCMPPDZ256rmik, VCMP... printSSEAVXCC(MI, 8, O); break; case 35: // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrribk, VCMPPDZrrik, VCMPPSZ128r... printSSEAVXCC(MI, 4, O); break; case 36: // VCOMPRESSPDZ256mr, VCOMPRESSPDZ256mrk, VCOMPRESSPSZ256mr, VCOMPRESSPSZ... printf256mem(MI, 0, O); break; case 37: // VCOMPRESSPDZmr, VCOMPRESSPDZmrk, VCOMPRESSPSZmr, VCOMPRESSPSZmrk, VMOV... printf512mem(MI, 0, O); break; case 38: // VEXTRACTI32x8Zmr, VEXTRACTI32x8Zmrk, VEXTRACTI64x4Zmr, VEXTRACTI64x4Zm... printi256mem(MI, 0, O); break; case 39: // VMOVDQA32Zmr, VMOVDQA32Zmrk, VMOVDQA64Zmr, VMOVDQA64Zmrk, VMOVDQU16Zmr... printi512mem(MI, 0, O); break; case 40: // VPCOMBmi, VPCOMDmi, VPCOMQmi, VPCOMUBmi, VPCOMUDmi, VPCOMUQmi, VPCOMUW... printXOPCC(MI, 7, O); break; case 41: // VPCOMBri, VPCOMDri, VPCOMQri, VPCOMUBri, VPCOMUDri, VPCOMUQri, VPCOMUW... printXOPCC(MI, 3, O); break; case 42: // VPSCATTERDDZ128mr, VPSCATTERDQZ128mr, VPSCATTERQDZ256mr, VPSCATTERQQZ1... printi128mem(MI, 1, O); SStream_concat0(O, " {"); printOperand(MI, 6, O); SStream_concat0(O, "}, "); printOperand(MI, 7, O); return; break; case 43: // VPSCATTERDDZ256mr, VPSCATTERDQZ256mr, VPSCATTERQDZmr, VPSCATTERQQZ256m... printi256mem(MI, 1, O); SStream_concat0(O, " {"); printOperand(MI, 6, O); SStream_concat0(O, "}, "); printOperand(MI, 7, O); return; break; case 44: // VPSCATTERDDZmr, VPSCATTERDQZmr, VPSCATTERQQZmr, VSCATTERDPDZmr, VSCATT... printi512mem(MI, 1, O); SStream_concat0(O, " {"); printOperand(MI, 6, O); SStream_concat0(O, "}, "); printOperand(MI, 7, O); return; break; case 45: // VPSCATTERQDZ128mr, VSCATTERQPSZ128mr printi64mem(MI, 1, O); SStream_concat0(O, " {"); printOperand(MI, 6, O); SStream_concat0(O, "}, "); printOperand(MI, 7, O); return; break; case 46: // XADD16rm, XCHG16rm printi16mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 47: // XADD16rr, XADD32rr, XADD64rr, XADD8rr printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 48: // XADD32rm, XCHG32rm printi32mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 49: // XADD64rm, XCHG64rm printi64mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 50: // XADD8rm, XCHG8rm printi8mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 51: // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; } // Fragment 1 encoded into 5 bits for 25 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 20) & 31)); switch ((Bits >> 20) & 31) { default: // unreachable case 0: // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... return; break; case 1: // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... SStream_concat0(O, ", "); break; case 2: // ADD_FrST0, DIVR_FrST0, DIV_FrST0, FPNCEST0r, MUL_FrST0, SUBR_FrST0, SU... SStream_concat0(O, ", st(0)"); op_addReg(MI, X86_REG_ST0); return; break; case 3: // CMPPDrmi, CMPPDrri, VCMPPDYrmi, VCMPPDYrri, VCMPPDZ128rmbi, VCMPPDZ128... SStream_concat0(O, "pd\t"); printOperand(MI, 0, O); break; case 4: // CMPPSrmi, CMPPSrri, VCMPPSYrmi, VCMPPSYrri, VCMPPSZ128rmbi, VCMPPSZ128... SStream_concat0(O, "ps\t"); printOperand(MI, 0, O); break; case 5: // CMPSDrm, CMPSDrm_Int, CMPSDrr, CMPSDrr_Int, VCMPSDZrm, VCMPSDZrm_Int, ... SStream_concat0(O, "sd\t"); printOperand(MI, 0, O); break; case 6: // CMPSSrm, CMPSSrm_Int, CMPSSrr, CMPSSrr_Int, VCMPSSZrm, VCMPSSZrm_Int, ... SStream_concat0(O, "ss\t"); printOperand(MI, 0, O); break; case 7: // FARJMP16i, FARJMP32i SStream_concat0(O, ":"); printOperand(MI, 0, O); return; break; case 8: // INSB, INSL, INSW SStream_concat0(O, ", dx"); op_addReg(MI, X86_REG_DX); return; break; case 9: // MOV16o16a, MOV16o32a, MOV16o64a, OUT16ir, STOSW, XCHG16ar SStream_concat0(O, ", ax"); op_addReg(MI, X86_REG_AX); return; break; case 10: // MOV32o16a, MOV32o32a, MOV32o64a, OUT32ir, STOSL, XCHG32ar SStream_concat0(O, ", eax"); op_addReg(MI, X86_REG_EAX); return; break; case 11: // MOV64o32a, MOV64o64a, STOSQ, XCHG64ar SStream_concat0(O, ", rax"); op_addReg(MI, X86_REG_RAX); return; break; case 12: // MOV8o16a, MOV8o32a, MOV8o64a, OUT8ir, STOSB SStream_concat0(O, ", al"); op_addReg(MI, X86_REG_AL); return; break; case 13: // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R... SStream_concat0(O, ", cl"); op_addReg(MI, X86_REG_CL); return; break; case 14: // RCL16r1, RCL32r1, RCL64r1, RCL8r1, RCR16m1, RCR16r1, RCR32m1, RCR32r1,... SStream_concat0(O, ", 1"); op_addImm(MI, 1); return; break; case 15: // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... SStream_concat0(O, " {"); break; case 16: // VGATHERPF0DPDm, VGATHERPF0DPSm, VGATHERPF0QPDm, VGATHERPF0QPSm, VGATHE... SStream_concat0(O, "}, "); break; case 17: // VPCMPBZ128rmi, VPCMPBZ128rmik, VPCMPBZ128rri, VPCMPBZ128rrik, VPCMPBZ2... SStream_concat0(O, "b\t"); printOperand(MI, 0, O); break; case 18: // VPCMPDZ128rmi, VPCMPDZ128rmib, VPCMPDZ128rmibk, VPCMPDZ128rmik, VPCMPD... SStream_concat0(O, "d\t"); printOperand(MI, 0, O); break; case 19: // VPCMPQZ128rmi, VPCMPQZ128rmib, VPCMPQZ128rmibk, VPCMPQZ128rmik, VPCMPQ... SStream_concat0(O, "q\t"); printOperand(MI, 0, O); break; case 20: // VPCMPUBZ128rmi, VPCMPUBZ128rmik, VPCMPUBZ128rri, VPCMPUBZ128rrik, VPCM... SStream_concat0(O, "ub\t"); printOperand(MI, 0, O); break; case 21: // VPCMPUDZ128rmi, VPCMPUDZ128rmib, VPCMPUDZ128rmibk, VPCMPUDZ128rmik, VP... SStream_concat0(O, "ud\t"); printOperand(MI, 0, O); break; case 22: // VPCMPUQZ128rmi, VPCMPUQZ128rmib, VPCMPUQZ128rmibk, VPCMPUQZ128rmik, VP... SStream_concat0(O, "uq\t"); printOperand(MI, 0, O); break; case 23: // VPCMPUWZ128rmi, VPCMPUWZ128rmik, VPCMPUWZ128rri, VPCMPUWZ128rrik, VPCM... SStream_concat0(O, "uw\t"); printOperand(MI, 0, O); break; case 24: // VPCMPWZ128rmi, VPCMPWZ128rmik, VPCMPWZ128rri, VPCMPWZ128rrik, VPCMPWZ2... SStream_concat0(O, "w\t"); printOperand(MI, 0, O); break; } // Fragment 2 encoded into 6 bits for 38 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 25) & 63)); switch ((Bits >> 25) & 63) { default: // unreachable case 0: // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... printOperand(MI, 5, O); break; case 1: // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... printOperand(MI, 2, O); break; case 2: // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... printi16mem(MI, 2, O); break; case 3: // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, CMOVA32rm, CMOVAE32rm, ... printi32mem(MI, 2, O); break; case 4: // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, CMOVA64rm, CMOVAE64rm, ... printi64mem(MI, 2, O); break; case 5: // ADC8rm, ADD8rm, AND8rm, CRC32r32m8, CRC32r64m8, OR8rm, PINSRBrm, SBB8r... printi8mem(MI, 2, O); break; case 6: // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,... printf128mem(MI, 2, O); break; case 7: // ADDSDrm, ADDSDrm_Int, CMPSDrm_alt, CVTSD2SSrm_Int, DIVSDrm, DIVSDrm_In... printf64mem(MI, 2, O); break; case 8: // ADDSSrm, ADDSSrm_Int, CMPSSrm_alt, CVTSS2SDrm_Int, DIVSSrm, DIVSSrm_In... printf32mem(MI, 2, O); break; case 9: // AESDECLASTrm, AESDECrm, AESENCLASTrm, AESENCrm, GF2P8AFFINEINVQBrmi, G... printi128mem(MI, 2, O); break; case 10: // AESIMCrm, AESKEYGENASSIST128rm, BNDMOV64rm, CVTDQ2PSrm, INVEPT32, INVE... printi128mem(MI, 1, O); break; case 11: // AESIMCrr, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr... printOperand(MI, 1, O); break; case 12: // BEXTR32rm, BEXTRI32mi, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, B... printi32mem(MI, 1, O); break; case 13: // BEXTR64rm, BEXTRI64mi, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, B... printi64mem(MI, 1, O); break; case 14: // BNDCL32rm, BNDCL64rm, BNDCN32rm, BNDCN64rm, BNDCU32rm, BNDCU64rm, BNDL... printanymem(MI, 1, O); return; break; case 15: // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, KMOVWkm, LAR16rm, LA... printi16mem(MI, 1, O); break; case 16: // CMP8rm, KMOVBkm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32... printi8mem(MI, 1, O); return; break; case 17: // CMPPDrmi, CMPPDrri, CMPPSrmi, CMPPSrri, CMPSDrm, CMPSDrm_Int, CMPSDrr,... SStream_concat0(O, ", "); break; case 18: // COMISDrm, COMISDrm_Int, CVTPS2PDrm, CVTSD2SI64rm_Int, CVTSD2SIrm_Int, ... printf64mem(MI, 1, O); break; case 19: // COMISSrm, COMISSrm_Int, CVTSS2SDrm, CVTSS2SI64rm_Int, CVTSS2SIrm_Int, ... printf32mem(MI, 1, O); break; case 20: // CVTPD2DQrm, CVTPD2PSrm, CVTPS2DQrm, CVTTPD2DQrm, CVTTPS2DQrm, MMX_CVTP... printf128mem(MI, 1, O); break; case 21: // EXTRQI, MMX_PSLLDri, MMX_PSLLQri, MMX_PSLLWri, MMX_PSRADri, MMX_PSRAWr... printU8Imm(MI, 2, O); break; case 22: // FARCALL16i, FARCALL32i, NOOP19rr printOperand(MI, 0, O); return; break; case 23: // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... printopaquemem(MI, 1, O); return; break; case 24: // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64, VCVTDQ2PSZrm, VCVTQQ2PDZrm, VCV... printi512mem(MI, 1, O); break; case 25: // MOVSB printSrcIdx8(MI, 1, O); return; break; case 26: // MOVSL printSrcIdx32(MI, 1, O); return; break; case 27: // MOVSQ printSrcIdx64(MI, 1, O); return; break; case 28: // MOVSW printSrcIdx16(MI, 1, O); return; break; case 29: // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... printU8Imm(MI, 5, O); return; break; case 30: // VBROADCASTF32X8rm, VBROADCASTF64X4rm, VCVTPD2DQYrm, VCVTPD2DQZ256rm, V... printf256mem(MI, 1, O); break; case 31: // VBROADCASTI32X8rm, VBROADCASTI64X4rm, VCVTDQ2PDZrm, VCVTDQ2PSYrm, VCVT... printi256mem(MI, 1, O); break; case 32: // VCMPPDZ128rmbik, VCMPPDZ128rmik, VCMPPDZ128rrik, VCMPPDZ256rmbik, VCMP... SStream_concat0(O, " {"); printOperand(MI, 1, O); SStream_concat0(O, "}, "); printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 33: // VCVTPD2DQZrm, VCVTPD2PSZrm, VCVTPD2QQZrm, VCVTPD2UDQZrm, VCVTPD2UQQZrm... printf512mem(MI, 1, O); break; case 34: // VGATHERDPDYrm, VGATHERDPSYrm, VGATHERQPDYrm, VPGATHERDDYrm, VPGATHERDQ... printi256mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 8, O); return; break; case 35: // VGATHERDPDZ128rm, VGATHERDPDZ256rm, VGATHERDPDZrm, VGATHERDPSZ128rm, V... printOperand(MI, 3, O); SStream_concat0(O, "}, "); break; case 36: // VGATHERDPDrm, VGATHERDPSrm, VGATHERQPDrm, VGATHERQPSYrm, VPGATHERDDrm,... printi128mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 8, O); return; break; case 37: // VGATHERQPSrm, VPGATHERQDrm printi64mem(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 8, O); return; break; } // Fragment 3 encoded into 6 bits for 36 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 31) & 63)); switch ((Bits >> 31) & 63) { default: // unreachable case 0: // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... return; break; case 1: // AESKEYGENASSIST128rm, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr, ANDN64... SStream_concat0(O, ", "); break; case 2: // BLENDVPDrm0, BLENDVPDrr0, BLENDVPSrm0, BLENDVPSrr0, PBLENDVBrm0, PBLEN... SStream_concat0(O, ", xmm0"); return; break; case 3: // CMPPDrmi, CMPPSrmi printf128mem(MI, 2, O); return; break; case 4: // CMPPDrri, CMPPSrri, CMPSDrr, CMPSDrr_Int, CMPSSrr, CMPSSrr_Int printOperand(MI, 2, O); return; break; case 5: // CMPSDrm, CMPSDrm_Int printf64mem(MI, 2, O); return; break; case 6: // CMPSSrm, CMPSSrm_Int printf32mem(MI, 2, O); return; break; case 7: // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHLD64mrCL, SHLD64rrCL... SStream_concat0(O, ", cl"); op_addReg(MI, X86_REG_CL); return; break; case 8: // V4FMADDPSrmk, V4FMADDSSrmk, V4FNMADDPSrmk, V4FNMADDSSrmk, VADDPDZ128rm... SStream_concat0(O, "}, "); break; case 9: // V4FMADDPSrmkz, V4FMADDSSrmkz, V4FNMADDPSrmkz, V4FNMADDSSrmkz, VADDPDZ1... SStream_concat0(O, "} {z}, "); op_addAvxZeroOpmask(MI); break; case 10: // VCMPPDYrmi, VCMPPDYrri, VCMPPDZ128rmbi, VCMPPDZ128rmi, VCMPPDZ128rri, ... printOperand(MI, 1, O); SStream_concat0(O, ", "); break; case 11: // VCMPPDZ128rmbik, VCMPPDZ256rmbik, VCMPPDZrmbik, VCMPSDZrm_Intk printf64mem(MI, 3, O); break; case 12: // VCMPPDZ128rmik, VCMPPSZ128rmik printf128mem(MI, 3, O); return; break; case 13: // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrribk, VCMPPDZrrik, VCMPPSZ128r... printOperand(MI, 3, O); break; case 14: // VCMPPDZ256rmik, VCMPPSZ256rmik printf256mem(MI, 3, O); return; break; case 15: // VCMPPDZrmik, VCMPPSZrmik printf512mem(MI, 3, O); return; break; case 16: // VCMPPSZ128rmbik, VCMPPSZ256rmbik, VCMPPSZrmbik, VCMPSSZrm_Intk printf32mem(MI, 3, O); break; case 17: // VCOMISDZrrb, VCOMISSZrrb, VCVTPH2PSZrrb, VCVTPS2PDZrrb, VCVTTPD2DQZrrb... SStream_concat0(O, ", {sae}"); op_addAvxSae(MI); return; break; case 18: // VCVTDQ2PDZ128rmb, VCVTPD2DQZ128rmb, VCVTPD2PSZ128rmb, VCVTPD2QQZ128rmb... SStream_concat0(O, "{1to2}"); return; break; case 19: // VCVTDQ2PDZ256rmb, VCVTDQ2PSZ128rmb, VCVTPD2DQZ256rmb, VCVTPD2PSZ256rmb... SStream_concat0(O, "{1to4}"); return; break; case 20: // VCVTDQ2PDZrmb, VCVTDQ2PSZ256rmb, VCVTPD2DQZrmb, VCVTPD2PSZrmb, VCVTPD2... SStream_concat0(O, "{1to8}"); return; break; case 21: // VCVTDQ2PSZrmb, VCVTPS2DQZrmb, VCVTPS2UDQZrmb, VCVTTPS2DQZrmb, VCVTTPS2... SStream_concat0(O, "{1to16}"); return; break; case 22: // VCVTPS2PHZrrb, VGETMANTPDZrrib, VGETMANTPSZrrib, VREDUCEPDZrrib, VREDU... SStream_concat0(O, ", {sae}, "); op_addAvxSae(MI); printU8Imm(MI, 2, O); return; break; case 23: // VFPCLASSPDZ128rmb, VGETMANTPDZ128rmbi, VPERMILPDZ128mbi, VPROLQZ128mbi... SStream_concat0(O, "{1to2}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_2); printU8Imm(MI, 6, O); return; break; case 24: // VFPCLASSPDZ256rmb, VFPCLASSPSZ128rmb, VGETMANTPDZ256rmbi, VGETMANTPSZ1... SStream_concat0(O, "{1to4}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_4); printU8Imm(MI, 6, O); return; break; case 25: // VFPCLASSPDZrmb, VFPCLASSPSZ256rmb, VGETMANTPDZrmbi, VGETMANTPSZ256rmbi... SStream_concat0(O, "{1to8}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_8); printU8Imm(MI, 6, O); return; break; case 26: // VFPCLASSPSZrmb, VGETMANTPSZrmbi, VPERMILPSZmbi, VPROLDZmbi, VPRORDZmbi... SStream_concat0(O, "{1to16}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_16); printU8Imm(MI, 6, O); return; break; case 27: // VGATHERDPDZ128rm, VGATHERDPSZ128rm, VGATHERQPDZ128rm, VGATHERQPSZ256rm... printi128mem(MI, 4, O); return; break; case 28: // VGATHERDPDZ256rm, VGATHERDPSZ256rm, VGATHERQPDZ256rm, VGATHERQPSZrm, V... printi256mem(MI, 4, O); return; break; case 29: // VGATHERDPDZrm, VGATHERDPSZrm, VGATHERQPDZrm, VPGATHERDDZrm, VPGATHERDQ... printi512mem(MI, 4, O); return; break; case 30: // VGATHERQPSZ128rm, VPGATHERQDZ128rm printi64mem(MI, 4, O); return; break; case 31: // VPCMPBZ128rmik, VPCMPDZ128rmik, VPCMPQZ128rmik, VPCMPUBZ128rmik, VPCMP... printi128mem(MI, 3, O); return; break; case 32: // VPCMPBZ256rmik, VPCMPDZ256rmik, VPCMPQZ256rmik, VPCMPUBZ256rmik, VPCMP... printi256mem(MI, 3, O); return; break; case 33: // VPCMPBZrmik, VPCMPDZrmik, VPCMPQZrmik, VPCMPUBZrmik, VPCMPUDZrmik, VPC... printi512mem(MI, 3, O); return; break; case 34: // VPCMPDZ128rmibk, VPCMPDZ256rmibk, VPCMPDZrmibk, VPCMPUDZ128rmibk, VPCM... printi32mem(MI, 3, O); break; case 35: // VPCMPQZ128rmibk, VPCMPQZ256rmibk, VPCMPQZrmibk, VPCMPUQZ128rmibk, VPCM... printi64mem(MI, 3, O); break; } // Fragment 4 encoded into 6 bits for 39 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 37) & 63)); switch ((Bits >> 37) & 63) { default: // unreachable case 0: // AESKEYGENASSIST128rm, EXTRACTPSmr, MMX_PSHUFWmi, PCMPESTRIrm, PCMPESTR... printU8Imm(MI, 6, O); return; break; case 1: // AESKEYGENASSIST128rr, EXTRACTPSrr, KSHIFTLBri, KSHIFTLDri, KSHIFTLQri,... printU8Imm(MI, 2, O); return; break; case 2: // ANDN32rm, MULX32rm, PDEP32rm, PEXT32rm, VALIGNDZ128rmbi, VALIGNDZ256rm... printi32mem(MI, 2, O); break; case 3: // ANDN32rr, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32ri, BEXTRI64ri, BZHI... printOperand(MI, 2, O); break; case 4: // ANDN64rm, MULX64rm, PDEP64rm, PEXT64rm, VALIGNQZ128rmbi, VALIGNQZ256rm... printi64mem(MI, 2, O); break; case 5: // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... printOperand(MI, 6, O); break; case 6: // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, CMPSDrm_alt, CMPSS... printU8Imm(MI, 7, O); return; break; case 7: // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... printU8Imm(MI, 3, O); break; case 8: // V4FMADDPSrm, V4FMADDSSrm, V4FNMADDPSrm, V4FNMADDSSrm, VBROADCASTF32X4Z... printf128mem(MI, 3, O); break; case 9: // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... printOperand(MI, 3, O); break; case 10: // VADDPDYrm, VADDPDZ256rm, VADDPSYrm, VADDPSZ256rm, VADDSUBPDYrm, VADDSU... printf256mem(MI, 2, O); break; case 11: // VADDPDZ128rm, VADDPDrm, VADDPSZ128rm, VADDPSrm, VADDSUBPDrm, VADDSUBPS... printf128mem(MI, 2, O); break; case 12: // VADDPDZ128rmb, VADDPDZ256rmb, VADDPDZrmb, VADDSDZrm, VADDSDZrm_Int, VA... printf64mem(MI, 2, O); break; case 13: // VADDPDZrm, VADDPSZrm, VANDNPDZrm, VANDNPSZrm, VANDPDZrm, VANDPSZrm, VB... printf512mem(MI, 2, O); break; case 14: // VADDPSZ128rmb, VADDPSZ256rmb, VADDPSZrmb, VADDSSZrm, VADDSSZrm_Int, VA... printf32mem(MI, 2, O); break; case 15: // VAESDECLASTYrm, VAESDECLASTZ256rm, VAESDECYrm, VAESDECZ256rm, VAESENCL... printi256mem(MI, 2, O); break; case 16: // VAESDECLASTZ128rm, VAESDECLASTrm, VAESDECZ128rm, VAESDECrm, VAESENCLAS... printi128mem(MI, 2, O); break; case 17: // VAESDECLASTZrm, VAESDECZrm, VAESENCLASTZrm, VAESENCZrm, VALIGNDZrmi, V... printi512mem(MI, 2, O); break; case 18: // VBROADCASTF32X2Z256mk, VBROADCASTF32X2Zmk, VBROADCASTSDZ256mk, VBROADC... printf64mem(MI, 3, O); break; case 19: // VBROADCASTF32X8rmk, VBROADCASTF64X4rmk, VCVTPD2DQZ256rmk, VCVTPD2PSZ25... printf256mem(MI, 3, O); break; case 20: // VBROADCASTI32X2Z128mk, VBROADCASTI32X2Z256mk, VBROADCASTI32X2Zmk, VCVT... printi64mem(MI, 3, O); break; case 21: // VBROADCASTI32X4Z256rmk, VBROADCASTI32X4rmk, VBROADCASTI64X2Z128rmk, VB... printi128mem(MI, 3, O); break; case 22: // VBROADCASTI32X8rmk, VBROADCASTI64X4rmk, VCVTDQ2PDZrmk, VCVTDQ2PSZ256rm... printi256mem(MI, 3, O); break; case 23: // VBROADCASTSSZ128mk, VBROADCASTSSZ256mk, VBROADCASTSSZmk, VCVTPS2DQZ128... printf32mem(MI, 3, O); break; case 24: // VCMPPDZ128rmbik, VPCMPQZ128rmibk, VPCMPUQZ128rmibk SStream_concat0(O, "{1to2}"); return; break; case 25: // VCMPPDZ128rrik, VCMPPDZ256rrik, VCMPPDZrrik, VCMPPSZ128rrik, VCMPPSZ25... return; break; case 26: // VCMPPDZ256rmbik, VCMPPSZ128rmbik, VPCMPDZ128rmibk, VPCMPQZ256rmibk, VP... SStream_concat0(O, "{1to4}"); return; break; case 27: // VCMPPDZrmbik, VCMPPSZ256rmbik, VPCMPDZ256rmibk, VPCMPQZrmibk, VPCMPUDZ... SStream_concat0(O, "{1to8}"); return; break; case 28: // VCMPPDZrribk, VCMPPSZrribk, VCMPSDZrrb_Intk, VCMPSSZrrb_Intk SStream_concat0(O, ", {sae}"); op_addAvxSae(MI); return; break; case 29: // VCMPPSZrmbik, VPCMPDZrmibk, VPCMPUDZrmibk SStream_concat0(O, "{1to16}"); return; break; case 30: // VCVTDQ2PDZ128rmbk, VCVTDQ2PDZ256rmbk, VCVTDQ2PDZrmbk, VCVTDQ2PSZ128rmb... printi32mem(MI, 3, O); break; case 31: // VCVTDQ2PSZrmk, VCVTQQ2PDZrmk, VCVTQQ2PSZrmk, VCVTUDQ2PSZrmk, VCVTUQQ2P... printi512mem(MI, 3, O); break; case 32: // VCVTDQ2PSZrrb, VCVTPD2DQZrrb, VCVTPD2PSZrrb, VCVTPD2QQZrrb, VCVTPD2UDQ... printRoundingControl(MI, 2, O); return; break; case 33: // VCVTPD2DQZrmk, VCVTPD2PSZrmk, VCVTPD2QQZrmk, VCVTPD2UDQZrmk, VCVTPD2UQ... printf512mem(MI, 3, O); break; case 34: // VCVTSI2SDZrrb_Int, VCVTSI2SSZrrb_Int, VCVTSI642SDZrrb_Int, VCVTSI642SS... printRoundingControl(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; case 35: // VGF2P8AFFINEINVQBZ128rmbi, VGF2P8AFFINEINVQBZ256rmbi, VGF2P8AFFINEINVQ... printi8mem(MI, 2, O); break; case 36: // VPBROADCASTBZ128mk, VPBROADCASTBZ256mk, VPBROADCASTBZmk printi8mem(MI, 3, O); return; break; case 37: // VPBROADCASTWZ128mk, VPBROADCASTWZ256mk, VPBROADCASTWZmk, VPMOVSXBQZ128... printi16mem(MI, 3, O); return; break; case 38: // VPBROADCASTWZ128mkz, VPBROADCASTWZ256mkz, VPBROADCASTWZmkz, VPINSRWZrm... printi16mem(MI, 2, O); break; } // Fragment 5 encoded into 4 bits for 12 unique commands. // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 43) & 15)); switch ((Bits >> 43) & 15) { default: // unreachable case 0: // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR64r... return; break; case 1: // INSERTQI, V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4... SStream_concat0(O, ", "); break; case 2: // VADDPDZ128rmb, VANDNPDZ128rmb, VANDPDZ128rmb, VBLENDMPDZ128rmb, VCMPPD... SStream_concat0(O, "{1to2}"); return; break; case 3: // VADDPDZ256rmb, VADDPSZ128rmb, VANDNPDZ256rmb, VANDNPSZ128rmb, VANDPDZ2... SStream_concat0(O, "{1to4}"); return; break; case 4: // VADDPDZrmb, VADDPSZ256rmb, VANDNPDZrmb, VANDNPSZ256rmb, VANDPDZrmb, VA... SStream_concat0(O, "{1to8}"); return; break; case 5: // VADDPSZrmb, VANDNPSZrmb, VANDPSZrmb, VBLENDMPSZrmb, VCMPPSZrmbi, VCVTD... SStream_concat0(O, "{1to16}"); return; break; case 6: // VALIGNDZ128rmbi, VALIGNQZ256rmbi, VCMPPDZ256rmbi_alt, VCMPPSZ128rmbi_a... SStream_concat0(O, "{1to4}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_4); break; case 7: // VALIGNDZ256rmbi, VALIGNQZrmbi, VCMPPDZrmbi_alt, VCMPPSZ256rmbi_alt, VF... SStream_concat0(O, "{1to8}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_8); break; case 8: // VALIGNDZrmbi, VCMPPSZrmbi_alt, VFIXUPIMMPSZrmbi, VFPCLASSPSZrmbk, VGET... SStream_concat0(O, "{1to16}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_16); break; case 9: // VALIGNQZ128rmbi, VCMPPDZ128rmbi_alt, VFIXUPIMMPDZ128rmbi, VFPCLASSPDZ1... SStream_concat0(O, "{1to2}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_2); break; case 10: // VCMPPDZrrib, VCMPPSZrrib, VCMPSDZrrb_Int, VCMPSSZrrb_Int, VCVTPH2PSZrr... SStream_concat0(O, ", {sae}"); op_addAvxSae(MI); return; break; case 11: // VCMPPDZrrib_alt, VCMPPSZrrib_alt, VCMPSDZrrb_alt, VCMPSSZrrb_alt, VCVT... SStream_concat0(O, ", {sae}, "); op_addAvxSae(MI); break; } // Fragment 6 encoded into 5 bits for 31 unique commands. // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 31)); switch ((Bits >> 47) & 31) { default: // unreachable case 0: // INSERTQI, VCVTPS2PHZ128rrk, VCVTPS2PHZ256rrk, VCVTPS2PHZrrbk, VCVTPS2P... printU8Imm(MI, 4, O); return; break; case 1: // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... printf128mem(MI, 4, O); break; case 2: // VADDPDZ128rmbk, VADDPDZ256rmbk, VADDPDZrmbk, VADDSDZrm_Intk, VANDNPDZ1... printf64mem(MI, 4, O); break; case 3: // VADDPDZ128rmbkz, VADDPDZ256rmbkz, VADDPDZrmbkz, VADDSDZrm_Intkz, VANDN... printf64mem(MI, 3, O); break; case 4: // VADDPDZ128rmkz, VADDPSZ128rmkz, VANDNPDZ128rmkz, VANDNPSZ128rmkz, VAND... printf128mem(MI, 3, O); break; case 5: // VADDPDZ128rrk, VADDPDZ256rrk, VADDPDZrrbk, VADDPDZrrk, VADDPSZ128rrk, ... printOperand(MI, 4, O); break; case 6: // VADDPDZ128rrkz, VADDPDZ256rrkz, VADDPDZrrbkz, VADDPDZrrkz, VADDPSZ128r... printOperand(MI, 3, O); break; case 7: // VADDPDZ256rmk, VADDPSZ256rmk, VANDNPDZ256rmk, VANDNPSZ256rmk, VANDPDZ2... printf256mem(MI, 4, O); break; case 8: // VADDPDZ256rmkz, VADDPSZ256rmkz, VANDNPDZ256rmkz, VANDNPSZ256rmkz, VAND... printf256mem(MI, 3, O); break; case 9: // VADDPDZrmk, VADDPSZrmk, VANDNPDZrmk, VANDNPSZrmk, VANDPDZrmk, VANDPSZr... printf512mem(MI, 4, O); break; case 10: // VADDPDZrmkz, VADDPSZrmkz, VANDNPDZrmkz, VANDNPSZrmkz, VANDPDZrmkz, VAN... printf512mem(MI, 3, O); break; case 11: // VADDPDZrrb, VADDPSZrrb, VADDSDZrrb_Int, VADDSSZrrb_Int, VCVTDQ2PSZrrbk... printRoundingControl(MI, 3, O); return; break; case 12: // VADDPSZ128rmbk, VADDPSZ256rmbk, VADDPSZrmbk, VADDSSZrm_Intk, VANDNPSZ1... printf32mem(MI, 4, O); break; case 13: // VADDPSZ128rmbkz, VADDPSZ256rmbkz, VADDPSZrmbkz, VADDSSZrm_Intkz, VANDN... printf32mem(MI, 3, O); break; case 14: // VALIGNDZ128rmbi, VALIGNDZ128rmi, VALIGNDZ256rmbi, VALIGNDZ256rmi, VALI... printU8Imm(MI, 7, O); return; break; case 15: // VALIGNDZ128rmbik, VALIGNDZ256rmbik, VALIGNDZrmbik, VPACKSSDWZ128rmbk, ... printi32mem(MI, 4, O); break; case 16: // VALIGNDZ128rmbikz, VALIGNDZ256rmbikz, VALIGNDZrmbikz, VPACKSSDWZ128rmb... printi32mem(MI, 3, O); break; case 17: // VALIGNDZ128rmik, VALIGNQZ128rmik, VDBPSADBWZ128rmik, VGF2P8AFFINEINVQB... printi128mem(MI, 4, O); break; case 18: // VALIGNDZ128rmikz, VALIGNQZ128rmikz, VDBPSADBWZ128rmikz, VGF2P8AFFINEIN... printi128mem(MI, 3, O); break; case 19: // VALIGNDZ128rri, VALIGNDZ256rri, VALIGNDZrri, VALIGNQZ128rri, VALIGNQZ2... printU8Imm(MI, 3, O); return; break; case 20: // VALIGNDZ256rmik, VALIGNQZ256rmik, VDBPSADBWZ256rmik, VGF2P8AFFINEINVQB... printi256mem(MI, 4, O); break; case 21: // VALIGNDZ256rmikz, VALIGNQZ256rmikz, VDBPSADBWZ256rmikz, VGF2P8AFFINEIN... printi256mem(MI, 3, O); break; case 22: // VALIGNDZrmik, VALIGNQZrmik, VDBPSADBWZrmik, VGF2P8AFFINEINVQBZrmik, VG... printi512mem(MI, 4, O); break; case 23: // VALIGNDZrmikz, VALIGNQZrmikz, VDBPSADBWZrmikz, VGF2P8AFFINEINVQBZrmikz... printi512mem(MI, 3, O); break; case 24: // VALIGNQZ128rmbik, VALIGNQZ256rmbik, VALIGNQZrmbik, VPADDQZ128rmbk, VPA... printi64mem(MI, 4, O); break; case 25: // VALIGNQZ128rmbikz, VALIGNQZ256rmbikz, VALIGNQZrmbikz, VPADDQZ128rmbkz,... printi64mem(MI, 3, O); break; case 26: // VBLENDVPDYrm, VBLENDVPDrm, VBLENDVPSYrm, VBLENDVPSrm, VFMADDPD4Ymr, VF... printOperand(MI, 7, O); break; case 27: // VCVTDQ2PSZrrbk, VCVTPD2DQZrrbk, VCVTPD2PSZrrbk, VCVTPD2QQZrrbk, VCVTPD... printRoundingControl(MI, 4, O); return; break; case 28: // VFIXUPIMMPDZ128rmbi, VFIXUPIMMPDZ128rmi, VFIXUPIMMPDZ256rmbi, VFIXUPIM... printU8Imm(MI, 8, O); return; break; case 29: // VGF2P8AFFINEINVQBZ128rmbik, VGF2P8AFFINEINVQBZ256rmbik, VGF2P8AFFINEIN... printi8mem(MI, 4, O); break; case 30: // VGF2P8AFFINEINVQBZ128rmbikz, VGF2P8AFFINEINVQBZ256rmbikz, VGF2P8AFFINE... printi8mem(MI, 3, O); break; } // Fragment 7 encoded into 4 bits for 12 unique commands. // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 52) & 15)); switch ((Bits >> 52) & 15) { default: // unreachable case 0: // V4FMADDPSrmk, V4FMADDPSrmkz, V4FMADDSSrmk, V4FMADDSSrmkz, V4FNMADDPSrm... return; break; case 1: // VADDPDZ128rmbk, VADDPDZ128rmbkz, VANDNPDZ128rmbk, VANDNPDZ128rmbkz, VA... SStream_concat0(O, "{1to2}"); return; break; case 2: // VADDPDZ256rmbk, VADDPDZ256rmbkz, VADDPSZ128rmbk, VADDPSZ128rmbkz, VAND... SStream_concat0(O, "{1to4}"); return; break; case 3: // VADDPDZrmbk, VADDPDZrmbkz, VADDPSZ256rmbk, VADDPSZ256rmbkz, VANDNPDZrm... SStream_concat0(O, "{1to8}"); return; break; case 4: // VADDPDZrrbk, VADDPDZrrbkz, VADDPSZrrbk, VADDPSZrrbkz, VADDSDZrrb_Intk,... SStream_concat0(O, ", "); break; case 5: // VADDPSZrmbk, VADDPSZrmbkz, VANDNPSZrmbk, VANDNPSZrmbkz, VANDPSZrmbk, V... SStream_concat0(O, "{1to16}"); return; break; case 6: // VALIGNDZ128rmbik, VALIGNDZ128rmbikz, VALIGNQZ256rmbik, VALIGNQZ256rmbi... SStream_concat0(O, "{1to4}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_4); break; case 7: // VALIGNDZ256rmbik, VALIGNDZ256rmbikz, VALIGNQZrmbik, VALIGNQZrmbikz, VC... SStream_concat0(O, "{1to8}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_8); break; case 8: // VALIGNDZrmbik, VALIGNDZrmbikz, VCMPPSZrmbi_altk, VFIXUPIMMPSZrmbik, VF... SStream_concat0(O, "{1to16}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_16); break; case 9: // VALIGNQZ128rmbik, VALIGNQZ128rmbikz, VCMPPDZ128rmbi_altk, VFIXUPIMMPDZ... SStream_concat0(O, "{1to2}, "); op_addAvxBroadcast(MI, X86_AVX_BCAST_2); break; case 10: // VCMPPDZrrib_altk, VCMPPSZrrib_altk, VCMPSDZrrb_altk, VCMPSSZrrb_altk, ... SStream_concat0(O, ", {sae}, "); op_addAvxSae(MI); break; case 11: // VCVTSS2SDZrrb_Intk, VCVTSS2SDZrrb_Intkz, VGETEXPSDZrbk, VGETEXPSDZrbkz... SStream_concat0(O, ", {sae}"); op_addAvxSae(MI); return; break; } // Fragment 8 encoded into 3 bits for 6 unique commands. // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 56) & 7)); switch ((Bits >> 56) & 7) { default: // unreachable case 0: // VADDPDZrrbk, VADDPSZrrbk, VADDSDZrrb_Intk, VADDSSZrrb_Intk, VCVTSD2SSZ... printRoundingControl(MI, 5, O); return; break; case 1: // VADDPDZrrbkz, VADDPSZrrbkz, VADDSDZrrb_Intkz, VADDSSZrrb_Intkz, VCVTSD... printRoundingControl(MI, 4, O); return; break; case 2: // VALIGNDZ128rmbik, VALIGNDZ128rmik, VALIGNDZ256rmbik, VALIGNDZ256rmik, ... printU8Imm(MI, 9, O); return; break; case 3: // VALIGNDZ128rmbikz, VALIGNDZ128rmikz, VALIGNDZ256rmbikz, VALIGNDZ256rmi... printU8Imm(MI, 8, O); return; break; case 4: // VALIGNDZ128rrik, VALIGNDZ256rrik, VALIGNDZrrik, VALIGNQZ128rrik, VALIG... printU8Imm(MI, 5, O); return; break; case 5: // VALIGNDZ128rrikz, VALIGNDZ256rrikz, VALIGNDZrrikz, VALIGNQZ128rrikz, V... printU8Imm(MI, 4, O); return; break; } } capstone-sys-0.15.0/capstone/arch/X86/X86GenAsmWriter1_reduce.inc000064400000000000000000002145510072674642500224750ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, /* 10 */ 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, /* 19 */ 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, /* 29 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, /* 39 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, /* 50 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, /* 62 */ 'l', 'e', 'a', 9, 0, /* 67 */ 'j', 'a', 9, 0, /* 71 */ 's', 'e', 't', 'a', 9, 0, /* 77 */ 'c', 'm', 'o', 'v', 'a', 9, 0, /* 84 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, /* 95 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, /* 107 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, /* 118 */ 's', 'b', 'b', 9, 0, /* 123 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 131 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 139 */ 'j', 'b', 9, 0, /* 143 */ 'i', 'n', 's', 'b', 9, 0, /* 149 */ 's', 't', 'o', 's', 'b', 9, 0, /* 156 */ 'c', 'm', 'p', 's', 'b', 9, 0, /* 163 */ 'm', 'o', 'v', 's', 'b', 9, 0, /* 170 */ 's', 'e', 't', 'b', 9, 0, /* 176 */ 's', 'u', 'b', 9, 0, /* 181 */ 'c', 'm', 'o', 'v', 'b', 9, 0, /* 188 */ 'c', 'l', 'w', 'b', 9, 0, /* 194 */ 'a', 'd', 'c', 9, 0, /* 199 */ 'd', 'e', 'c', 9, 0, /* 204 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, /* 212 */ 'b', 'l', 'c', 'i', 'c', 9, 0, /* 219 */ 'b', 'l', 's', 'i', 'c', 9, 0, /* 226 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, /* 234 */ 'i', 'n', 'c', 9, 0, /* 239 */ 'b', 't', 'c', 9, 0, /* 244 */ 'a', 'a', 'd', 9, 0, /* 249 */ 'v', 'm', 'r', 'e', 'a', 'd', 9, 0, /* 257 */ 'x', 'a', 'd', 'd', 9, 0, /* 263 */ 'r', 'd', 's', 'e', 'e', 'd', 9, 0, /* 271 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, /* 280 */ 'r', 'd', 'p', 'i', 'd', 9, 0, /* 287 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, /* 296 */ 's', 'h', 'l', 'd', 9, 0, /* 302 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, /* 311 */ 'r', 'd', 'r', 'a', 'n', 'd', 9, 0, /* 319 */ 'b', 'o', 'u', 'n', 'd', 9, 0, /* 326 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, /* 335 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, /* 343 */ 's', 'h', 'r', 'd', 9, 0, /* 349 */ 'i', 'n', 's', 'd', 9, 0, /* 355 */ 's', 't', 'o', 's', 'd', 9, 0, /* 362 */ 'c', 'm', 'p', 's', 'd', 9, 0, /* 369 */ 'w', 'r', 's', 's', 'd', 9, 0, /* 376 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, /* 384 */ 'm', 'o', 'v', 's', 'd', 9, 0, /* 391 */ 'm', 'o', 'v', 's', 'x', 'd', 9, 0, /* 399 */ 'j', 'a', 'e', 9, 0, /* 404 */ 's', 'e', 't', 'a', 'e', 9, 0, /* 411 */ 'c', 'm', 'o', 'v', 'a', 'e', 9, 0, /* 419 */ 'j', 'b', 'e', 9, 0, /* 424 */ 's', 'e', 't', 'b', 'e', 9, 0, /* 431 */ 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, /* 439 */ 'j', 'g', 'e', 9, 0, /* 444 */ 's', 'e', 't', 'g', 'e', 9, 0, /* 451 */ 'c', 'm', 'o', 'v', 'g', 'e', 9, 0, /* 459 */ 'j', 'e', 9, 0, /* 463 */ 'j', 'l', 'e', 9, 0, /* 468 */ 's', 'e', 't', 'l', 'e', 9, 0, /* 475 */ 'c', 'm', 'o', 'v', 'l', 'e', 9, 0, /* 483 */ 'j', 'n', 'e', 9, 0, /* 488 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, /* 496 */ 's', 'e', 't', 'n', 'e', 9, 0, /* 503 */ 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, /* 511 */ 'l', 'o', 'o', 'p', 'e', 9, 0, /* 518 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 9, 0, /* 528 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 9, 0, /* 538 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 9, 0, /* 548 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 9, 0, /* 558 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, /* 566 */ 's', 'e', 't', 'e', 9, 0, /* 572 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 9, 0, /* 581 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 9, 0, /* 590 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, /* 600 */ 'x', 's', 'a', 'v', 'e', 9, 0, /* 607 */ 'c', 'm', 'o', 'v', 'e', 9, 0, /* 614 */ 'b', 's', 'f', 9, 0, /* 619 */ 'r', 'e', 't', 'f', 9, 0, /* 625 */ 'n', 'e', 'g', 9, 0, /* 630 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 9, 0, /* 639 */ 'j', 'g', 9, 0, /* 643 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, /* 651 */ 's', 'e', 't', 'g', 9, 0, /* 657 */ 'c', 'm', 'o', 'v', 'g', 9, 0, /* 664 */ 'p', 'u', 's', 'h', 9, 0, /* 670 */ 'b', 'l', 'c', 'i', 9, 0, /* 676 */ 'b', 'z', 'h', 'i', 9, 0, /* 682 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, /* 691 */ 'b', 'l', 's', 'i', 9, 0, /* 697 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, /* 705 */ 'b', 'l', 's', 'm', 's', 'k', 9, 0, /* 713 */ 't', 'z', 'm', 's', 'k', 9, 0, /* 720 */ 's', 'a', 'l', 9, 0, /* 725 */ 'l', 'w', 'p', 'v', 'a', 'l', 9, 0, /* 733 */ 'r', 'c', 'l', 9, 0, /* 738 */ 's', 'h', 'l', 9, 0, /* 743 */ 'j', 'l', 9, 0, /* 747 */ 'l', 'c', 'a', 'l', 'l', 9, 0, /* 754 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, /* 763 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, /* 772 */ 'r', 'o', 'l', 9, 0, /* 777 */ 'a', 'r', 'p', 'l', 9, 0, /* 783 */ 'l', 's', 'l', 9, 0, /* 788 */ 's', 'e', 't', 'l', 9, 0, /* 794 */ 'i', 'm', 'u', 'l', 9, 0, /* 800 */ 'c', 'm', 'o', 'v', 'l', 9, 0, /* 807 */ 'a', 'a', 'm', 9, 0, /* 812 */ 'a', 'n', 'd', 'n', 9, 0, /* 818 */ 'v', 'm', 'x', 'o', 'n', 9, 0, /* 825 */ 'j', 'o', 9, 0, /* 829 */ 'j', 'n', 'o', 9, 0, /* 834 */ 's', 'e', 't', 'n', 'o', 9, 0, /* 841 */ 'c', 'm', 'o', 'v', 'n', 'o', 9, 0, /* 849 */ 's', 'e', 't', 'o', 9, 0, /* 855 */ 'c', 'm', 'o', 'v', 'o', 9, 0, /* 862 */ 'b', 's', 'w', 'a', 'p', 9, 0, /* 869 */ 'p', 'd', 'e', 'p', 9, 0, /* 875 */ 'j', 'p', 9, 0, /* 879 */ 'c', 'm', 'p', 9, 0, /* 884 */ 'l', 'j', 'm', 'p', 9, 0, /* 890 */ 'j', 'n', 'p', 9, 0, /* 895 */ 's', 'e', 't', 'n', 'p', 9, 0, /* 902 */ 'c', 'm', 'o', 'v', 'n', 'p', 9, 0, /* 910 */ 'n', 'o', 'p', 9, 0, /* 915 */ 'l', 'o', 'o', 'p', 9, 0, /* 921 */ 'p', 'o', 'p', 9, 0, /* 926 */ 'r', 's', 't', 'o', 'r', 's', 's', 'p', 9, 0, /* 936 */ 's', 'e', 't', 'p', 9, 0, /* 942 */ 'c', 'm', 'o', 'v', 'p', 9, 0, /* 949 */ 'r', 'e', 't', 'f', 'q', 9, 0, /* 956 */ 'i', 'n', 'c', 's', 's', 'p', 'q', 9, 0, /* 965 */ 'r', 'd', 's', 's', 'p', 'q', 9, 0, /* 973 */ 's', 't', 'o', 's', 'q', 9, 0, /* 980 */ 'c', 'm', 'p', 's', 'q', 9, 0, /* 987 */ 'w', 'r', 's', 's', 'q', 9, 0, /* 994 */ 'w', 'r', 'u', 's', 's', 'q', 9, 0, /* 1002 */ 'm', 'o', 'v', 's', 'q', 9, 0, /* 1009 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, /* 1018 */ 'l', 'a', 'r', 9, 0, /* 1023 */ 's', 'a', 'r', 9, 0, /* 1028 */ 'r', 'c', 'r', 9, 0, /* 1033 */ 'e', 'n', 't', 'e', 'r', 9, 0, /* 1040 */ 's', 'h', 'r', 9, 0, /* 1045 */ 'r', 'o', 'r', 9, 0, /* 1050 */ 'u', 'm', 'o', 'n', 'i', 't', 'o', 'r', 9, 0, /* 1060 */ 'x', 'r', 's', 't', 'o', 'r', 9, 0, /* 1068 */ 'x', 'o', 'r', 9, 0, /* 1073 */ 'v', 'e', 'r', 'r', 9, 0, /* 1079 */ 'b', 's', 'r', 9, 0, /* 1084 */ 'b', 'l', 's', 'r', 9, 0, /* 1090 */ 'b', 't', 'r', 9, 0, /* 1095 */ 'l', 't', 'r', 9, 0, /* 1100 */ 's', 't', 'r', 9, 0, /* 1105 */ 'b', 'e', 'x', 't', 'r', 9, 0, /* 1112 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 0, /* 1120 */ 'b', 'l', 'c', 's', 9, 0, /* 1126 */ 'l', 'd', 's', 9, 0, /* 1131 */ 'l', 'e', 's', 9, 0, /* 1136 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, /* 1144 */ 'l', 'f', 's', 9, 0, /* 1149 */ 'l', 'g', 's', 9, 0, /* 1154 */ 'j', 's', 9, 0, /* 1158 */ 'l', 'w', 'p', 'i', 'n', 's', 9, 0, /* 1166 */ 'j', 'n', 's', 9, 0, /* 1171 */ 's', 'e', 't', 'n', 's', 9, 0, /* 1178 */ 'c', 'm', 'o', 'v', 'n', 's', 9, 0, /* 1186 */ 'x', 'r', 's', 't', 'o', 'r', 's', 9, 0, /* 1195 */ 'l', 's', 's', 9, 0, /* 1200 */ 'b', 't', 's', 9, 0, /* 1205 */ 's', 'e', 't', 's', 9, 0, /* 1211 */ 'c', 'm', 'o', 'v', 's', 9, 0, /* 1218 */ 'b', 't', 9, 0, /* 1222 */ 'l', 'g', 'd', 't', 9, 0, /* 1228 */ 's', 'g', 'd', 't', 9, 0, /* 1234 */ 'l', 'i', 'd', 't', 9, 0, /* 1240 */ 's', 'i', 'd', 't', 9, 0, /* 1246 */ 'l', 'l', 'd', 't', 9, 0, /* 1252 */ 's', 'l', 'd', 't', 9, 0, /* 1258 */ 'r', 'e', 't', 9, 0, /* 1263 */ 'u', 'm', 'w', 'a', 'i', 't', 9, 0, /* 1271 */ 'l', 'z', 'c', 'n', 't', 9, 0, /* 1278 */ 't', 'z', 'c', 'n', 't', 9, 0, /* 1285 */ 'i', 'n', 't', 9, 0, /* 1290 */ 'n', 'o', 't', 9, 0, /* 1295 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, /* 1303 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, /* 1313 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 'o', 'p', 't', 9, 0, /* 1325 */ 't', 'e', 's', 't', 9, 0, /* 1331 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, /* 1340 */ 'o', 'u', 't', 9, 0, /* 1345 */ 'p', 'e', 'x', 't', 9, 0, /* 1351 */ 'i', 'd', 'i', 'v', 9, 0, /* 1357 */ 'm', 'o', 'v', 9, 0, /* 1362 */ 'v', 'e', 'r', 'w', 9, 0, /* 1368 */ 'l', 'm', 's', 'w', 9, 0, /* 1374 */ 's', 'm', 's', 'w', 9, 0, /* 1380 */ 'i', 'n', 's', 'w', 9, 0, /* 1386 */ 's', 't', 'o', 's', 'w', 9, 0, /* 1393 */ 'c', 'm', 'p', 's', 'w', 9, 0, /* 1400 */ 'm', 'o', 'v', 's', 'w', 9, 0, /* 1407 */ 'a', 'd', 'c', 'x', 9, 0, /* 1413 */ 's', 'h', 'l', 'x', 9, 0, /* 1419 */ 'm', 'u', 'l', 'x', 9, 0, /* 1425 */ 'a', 'd', 'o', 'x', 9, 0, /* 1431 */ 's', 'a', 'r', 'x', 9, 0, /* 1437 */ 's', 'h', 'r', 'x', 9, 0, /* 1443 */ 'r', 'o', 'r', 'x', 9, 0, /* 1449 */ 'm', 'o', 'v', 's', 'x', 9, 0, /* 1456 */ 'm', 'o', 'v', 'z', 'x', 9, 0, /* 1463 */ 'c', 'l', 'r', 's', 's', 'b', 's', 'y', 9, 0, /* 1473 */ 'j', 'e', 'c', 'x', 'z', 9, 0, /* 1480 */ 'j', 'c', 'x', 'z', 9, 0, /* 1486 */ 'j', 'r', 'c', 'x', 'z', 9, 0, /* 1493 */ 's', 'b', 'b', 9, 'a', 'l', ',', 32, 0, /* 1502 */ 's', 'c', 'a', 's', 'b', 9, 'a', 'l', ',', 32, 0, /* 1513 */ 'l', 'o', 'd', 's', 'b', 9, 'a', 'l', ',', 32, 0, /* 1524 */ 's', 'u', 'b', 9, 'a', 'l', ',', 32, 0, /* 1533 */ 'a', 'd', 'c', 9, 'a', 'l', ',', 32, 0, /* 1542 */ 'a', 'd', 'd', 9, 'a', 'l', ',', 32, 0, /* 1551 */ 'a', 'n', 'd', 9, 'a', 'l', ',', 32, 0, /* 1560 */ 'i', 'n', 9, 'a', 'l', ',', 32, 0, /* 1568 */ 'c', 'm', 'p', 9, 'a', 'l', ',', 32, 0, /* 1577 */ 'x', 'o', 'r', 9, 'a', 'l', ',', 32, 0, /* 1586 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'a', 'l', ',', 32, 0, /* 1598 */ 't', 'e', 's', 't', 9, 'a', 'l', ',', 32, 0, /* 1608 */ 'm', 'o', 'v', 9, 'a', 'l', ',', 32, 0, /* 1617 */ 's', 'b', 'b', 9, 'a', 'x', ',', 32, 0, /* 1626 */ 's', 'u', 'b', 9, 'a', 'x', ',', 32, 0, /* 1635 */ 'a', 'd', 'c', 9, 'a', 'x', ',', 32, 0, /* 1644 */ 'a', 'd', 'd', 9, 'a', 'x', ',', 32, 0, /* 1653 */ 'a', 'n', 'd', 9, 'a', 'x', ',', 32, 0, /* 1662 */ 'i', 'n', 9, 'a', 'x', ',', 32, 0, /* 1670 */ 'c', 'm', 'p', 9, 'a', 'x', ',', 32, 0, /* 1679 */ 'x', 'o', 'r', 9, 'a', 'x', ',', 32, 0, /* 1688 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'a', 'x', ',', 32, 0, /* 1700 */ 't', 'e', 's', 't', 9, 'a', 'x', ',', 32, 0, /* 1710 */ 'm', 'o', 'v', 9, 'a', 'x', ',', 32, 0, /* 1719 */ 's', 'c', 'a', 's', 'w', 9, 'a', 'x', ',', 32, 0, /* 1730 */ 'l', 'o', 'd', 's', 'w', 9, 'a', 'x', ',', 32, 0, /* 1741 */ 's', 'b', 'b', 9, 'e', 'a', 'x', ',', 32, 0, /* 1751 */ 's', 'u', 'b', 9, 'e', 'a', 'x', ',', 32, 0, /* 1761 */ 'a', 'd', 'c', 9, 'e', 'a', 'x', ',', 32, 0, /* 1771 */ 'a', 'd', 'd', 9, 'e', 'a', 'x', ',', 32, 0, /* 1781 */ 'a', 'n', 'd', 9, 'e', 'a', 'x', ',', 32, 0, /* 1791 */ 's', 'c', 'a', 's', 'd', 9, 'e', 'a', 'x', ',', 32, 0, /* 1803 */ 'l', 'o', 'd', 's', 'd', 9, 'e', 'a', 'x', ',', 32, 0, /* 1815 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 0, /* 1824 */ 'c', 'm', 'p', 9, 'e', 'a', 'x', ',', 32, 0, /* 1834 */ 'x', 'o', 'r', 9, 'e', 'a', 'x', ',', 32, 0, /* 1844 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'e', 'a', 'x', ',', 32, 0, /* 1857 */ 't', 'e', 's', 't', 9, 'e', 'a', 'x', ',', 32, 0, /* 1868 */ 'm', 'o', 'v', 9, 'e', 'a', 'x', ',', 32, 0, /* 1878 */ 's', 'b', 'b', 9, 'r', 'a', 'x', ',', 32, 0, /* 1888 */ 's', 'u', 'b', 9, 'r', 'a', 'x', ',', 32, 0, /* 1898 */ 'a', 'd', 'c', 9, 'r', 'a', 'x', ',', 32, 0, /* 1908 */ 'a', 'd', 'd', 9, 'r', 'a', 'x', ',', 32, 0, /* 1918 */ 'a', 'n', 'd', 9, 'r', 'a', 'x', ',', 32, 0, /* 1928 */ 'c', 'm', 'p', 9, 'r', 'a', 'x', ',', 32, 0, /* 1938 */ 's', 'c', 'a', 's', 'q', 9, 'r', 'a', 'x', ',', 32, 0, /* 1950 */ 'l', 'o', 'd', 's', 'q', 9, 'r', 'a', 'x', ',', 32, 0, /* 1962 */ 'x', 'o', 'r', 9, 'r', 'a', 'x', ',', 32, 0, /* 1972 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 'r', 'a', 'x', ',', 32, 0, /* 1985 */ 't', 'e', 's', 't', 9, 'r', 'a', 'x', ',', 32, 0, /* 1996 */ 'm', 'o', 'v', 9, 'r', 'a', 'x', ',', 32, 0, /* 2006 */ 'o', 'u', 't', 's', 'b', 9, 'd', 'x', ',', 32, 0, /* 2017 */ 'o', 'u', 't', 's', 'd', 9, 'd', 'x', ',', 32, 0, /* 2028 */ 'o', 'u', 't', 's', 'w', 9, 'd', 'x', ',', 32, 0, /* 2039 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, /* 2070 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 2094 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, /* 2119 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, /* 2142 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, /* 2165 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, /* 2187 */ 'u', 'd', '0', 0, /* 2191 */ 'x', 's', 'h', 'a', '1', 0, /* 2197 */ 'u', 'd', '1', 0, /* 2201 */ 'i', 'n', 't', '1', 0, /* 2206 */ 'e', 'n', 'd', 'b', 'r', '3', '2', 0, /* 2214 */ 'u', 'd', '2', 0, /* 2218 */ 'i', 'n', 't', '3', 0, /* 2223 */ 'e', 'n', 'd', 'b', 'r', '6', '4', 0, /* 2231 */ 'r', 'e', 'x', '6', '4', 0, /* 2237 */ 'd', 'a', 't', 'a', '1', '6', 0, /* 2244 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, /* 2252 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 2265 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 2272 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 2282 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, /* 2292 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 2307 */ 'a', 'a', 'a', 0, /* 2311 */ 'd', 'a', 'a', 0, /* 2315 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, /* 2325 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, /* 2335 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, /* 2345 */ 'x', 'l', 'a', 't', 'b', 0, /* 2351 */ 'c', 'l', 'a', 'c', 0, /* 2356 */ 's', 't', 'a', 'c', 0, /* 2361 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, /* 2371 */ 'g', 'e', 't', 's', 'e', 'c', 0, /* 2378 */ 's', 'a', 'l', 'c', 0, /* 2383 */ 'c', 'l', 'c', 0, /* 2387 */ 'c', 'm', 'c', 0, /* 2391 */ 'r', 'd', 'p', 'm', 'c', 0, /* 2397 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, /* 2404 */ 'r', 'd', 't', 's', 'c', 0, /* 2410 */ 's', 't', 'c', 0, /* 2414 */ 'p', 'u', 's', 'h', 'f', 'd', 0, /* 2421 */ 'p', 'o', 'p', 'f', 'd', 0, /* 2427 */ 'c', 'p', 'u', 'i', 'd', 0, /* 2433 */ 'c', 'l', 'd', 0, /* 2437 */ 'i', 'r', 'e', 't', 'd', 0, /* 2443 */ 's', 't', 'd', 0, /* 2447 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, /* 2454 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, /* 2463 */ 'c', 'w', 'd', 0, /* 2467 */ 'c', 'w', 'd', 'e', 0, /* 2472 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, /* 2481 */ 'r', 'e', 'p', 'n', 'e', 0, /* 2487 */ 'c', 'd', 'q', 'e', 0, /* 2492 */ 'x', 's', 't', 'o', 'r', 'e', 0, /* 2499 */ 'l', 'e', 'a', 'v', 'e', 0, /* 2505 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, /* 2512 */ 'l', 'a', 'h', 'f', 0, /* 2517 */ 's', 'a', 'h', 'f', 0, /* 2522 */ 'p', 'u', 's', 'h', 'f', 0, /* 2528 */ 'p', 'o', 'p', 'f', 0, /* 2533 */ 'r', 'e', 't', 'f', 0, /* 2538 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, /* 2546 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, /* 2555 */ 'c', 'l', 'g', 'i', 0, /* 2560 */ 's', 't', 'g', 'i', 0, /* 2565 */ 'c', 'l', 'i', 0, /* 2569 */ 's', 't', 'i', 0, /* 2573 */ 'l', 'o', 'c', 'k', 0, /* 2578 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'l', 0, /* 2589 */ 'p', 'u', 's', 'h', 'a', 'l', 0, /* 2596 */ 'p', 'o', 'p', 'a', 'l', 0, /* 2602 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 2616 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, /* 2624 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, /* 2631 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, /* 2639 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, /* 2647 */ 'f', 's', 'e', 't', 'p', 'm', 0, /* 2654 */ 'r', 's', 'm', 0, /* 2658 */ 'c', 'q', 'o', 0, /* 2662 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, /* 2669 */ 'i', 'n', 't', 'o', 0, /* 2674 */ 'r', 'd', 't', 's', 'c', 'p', 0, /* 2681 */ 'r', 'e', 'p', 0, /* 2685 */ 'n', 'o', 'p', 0, /* 2689 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, /* 2701 */ 'c', 'd', 'q', 0, /* 2705 */ 'p', 'u', 's', 'h', 'f', 'q', 0, /* 2712 */ 'p', 'o', 'p', 'f', 'q', 0, /* 2718 */ 'r', 'e', 't', 'f', 'q', 0, /* 2724 */ 'i', 'r', 'e', 't', 'q', 0, /* 2730 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, /* 2738 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, /* 2747 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, /* 2756 */ 'r', 'd', 'm', 's', 'r', 0, /* 2762 */ 'w', 'r', 'm', 's', 'r', 0, /* 2768 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, /* 2778 */ 'a', 'a', 's', 0, /* 2782 */ 'd', 'a', 's', 0, /* 2786 */ 'p', 'u', 's', 'h', 9, 'c', 's', 0, /* 2794 */ 'p', 'u', 's', 'h', 9, 'd', 's', 0, /* 2802 */ 'p', 'o', 'p', 9, 'd', 's', 0, /* 2809 */ 'p', 'u', 's', 'h', 9, 'e', 's', 0, /* 2817 */ 'p', 'o', 'p', 9, 'e', 's', 0, /* 2824 */ 'p', 'u', 's', 'h', 9, 'f', 's', 0, /* 2832 */ 'p', 'o', 'p', 9, 'f', 's', 0, /* 2839 */ 'p', 'u', 's', 'h', 9, 'g', 's', 0, /* 2847 */ 'p', 'o', 'p', 9, 'g', 's', 0, /* 2854 */ 's', 'w', 'a', 'p', 'g', 's', 0, /* 2861 */ 'p', 'u', 's', 'h', 9, 's', 's', 0, /* 2869 */ 'p', 'o', 'p', 9, 's', 's', 0, /* 2876 */ 'c', 'l', 't', 's', 0, /* 2881 */ 'i', 'r', 'e', 't', 0, /* 2886 */ 's', 'y', 's', 'r', 'e', 't', 0, /* 2893 */ 's', 'y', 's', 'e', 'x', 'i', 't', 0, /* 2901 */ 'h', 'l', 't', 0, /* 2905 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, /* 2912 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, /* 2919 */ 'x', 'g', 'e', 't', 'b', 'v', 0, /* 2926 */ 'x', 's', 'e', 't', 'b', 'v', 0, /* 2933 */ 'p', 'u', 's', 'h', 'a', 'w', 0, /* 2940 */ 'p', 'o', 'p', 'a', 'w', 0, /* 2946 */ 'c', 'b', 'w', 0, /* 2950 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'x', 0, /* 2961 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'e', 'a', 'x', 0, /* 2972 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'e', 'a', 'x', 0, /* 2983 */ 'v', 'm', 'r', 'u', 'n', 9, 'e', 'a', 'x', 0, /* 2993 */ 's', 'k', 'i', 'n', 'i', 't', 9, 'e', 'a', 'x', 0, /* 3004 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'e', 'a', 'x', 0, /* 3016 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'r', 'a', 'x', 0, /* 3027 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'r', 'a', 'x', 0, /* 3038 */ 'v', 'm', 'r', 'u', 'n', 9, 'r', 'a', 'x', 0, /* 3048 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'e', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, /* 3065 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'r', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, /* 3082 */ 'i', 'n', 9, 'a', 'l', ',', 32, 'd', 'x', 0, /* 3092 */ 'i', 'n', 9, 'a', 'x', ',', 32, 'd', 'x', 0, /* 3102 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 'd', 'x', 0, /* 3113 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, /* 3122 */ 'm', 'w', 'a', 'i', 't', 'x', 0, /* 3129 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 2273U, // DBG_VALUE 2283U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 2266U, // BUNDLE 2293U, // LIFETIME_START 2253U, // LIFETIME_END 0U, // STACKMAP 2603U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 2120U, // PATCHABLE_FUNCTION_ENTER 2040U, // PATCHABLE_RET 2166U, // PATCHABLE_FUNCTION_EXIT 2143U, // PATCHABLE_TAIL_CALL 2095U, // PATCHABLE_EVENT_CALL 2071U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 2308U, // AAA 4341U, // AAD8i8 4904U, // AAM8i8 2779U, // AAS 5732U, // ADC16i16 270531U, // ADC16mi 270531U, // ADC16mi8 270531U, // ADC16mr 4468931U, // ADC16ri 4468931U, // ADC16ri8 8663235U, // ADC16rm 4468931U, // ADC16rr 4460739U, // ADC16rr_REV 5858U, // ADC32i32 278723U, // ADC32mi 278723U, // ADC32mi8 278723U, // ADC32mr 4468931U, // ADC32ri 4468931U, // ADC32ri8 12857539U, // ADC32rm 4468931U, // ADC32rr 4460739U, // ADC32rr_REV 5995U, // ADC64i32 282819U, // ADC64mi32 282819U, // ADC64mi8 282819U, // ADC64mr 4468931U, // ADC64ri32 4468931U, // ADC64ri8 17051843U, // ADC64rm 4468931U, // ADC64rr 4460739U, // ADC64rr_REV 5630U, // ADC8i8 286915U, // ADC8mi 286915U, // ADC8mi8 286915U, // ADC8mr 4468931U, // ADC8ri 4468931U, // ADC8ri8 21246147U, // ADC8rm 4468931U, // ADC8rr 4460739U, // ADC8rr_REV 12850560U, // ADCX32rm 4461952U, // ADCX32rr 17044864U, // ADCX64rm 4461952U, // ADCX64rr 5741U, // ADD16i16 270595U, // ADD16mi 270595U, // ADD16mi8 270595U, // ADD16mr 4468995U, // ADD16ri 4468995U, // ADD16ri8 8663299U, // ADD16rm 4468995U, // ADD16rr 4460803U, // ADD16rr_REV 5868U, // ADD32i32 278787U, // ADD32mi 278787U, // ADD32mi8 278787U, // ADD32mr 4468995U, // ADD32ri 4468995U, // ADD32ri8 12857603U, // ADD32rm 4468995U, // ADD32rr 4460803U, // ADD32rr_REV 6005U, // ADD64i32 282883U, // ADD64mi32 282883U, // ADD64mi8 282883U, // ADD64mr 4468995U, // ADD64ri32 4468995U, // ADD64ri8 17051907U, // ADD64rm 4468995U, // ADD64rr 4460803U, // ADD64rr_REV 5639U, // ADD8i8 286979U, // ADD8mi 286979U, // ADD8mi8 286979U, // ADD8mr 4468995U, // ADD8ri 4468995U, // ADD8ri8 21246211U, // ADD8rm 4468995U, // ADD8rr 4460803U, // ADD8rr_REV 12850578U, // ADOX32rm 4461970U, // ADOX32rr 17044882U, // ADOX64rm 4461970U, // ADOX64rr 5750U, // AND16i16 270651U, // AND16mi 270651U, // AND16mi8 270651U, // AND16mr 4469051U, // AND16ri 4469051U, // AND16ri8 8663355U, // AND16rm 4469051U, // AND16rr 4460859U, // AND16rr_REV 5878U, // AND32i32 278843U, // AND32mi 278843U, // AND32mi8 278843U, // AND32mr 4469051U, // AND32ri 4469051U, // AND32ri8 12857659U, // AND32rm 4469051U, // AND32rr 4460859U, // AND32rr_REV 6015U, // AND64i32 282939U, // AND64mi32 282939U, // AND64mi8 282939U, // AND64mr 4469051U, // AND64ri32 4469051U, // AND64ri8 17051963U, // AND64rm 4469051U, // AND64rr 4460859U, // AND64rr_REV 5648U, // AND8i8 287035U, // AND8mi 287035U, // AND8mi8 287035U, // AND8mr 4469051U, // AND8ri 4469051U, // AND8ri8 21246267U, // AND8rm 4469051U, // AND8rr 4460859U, // AND8rr_REV 159650605U, // ANDN32rm 696521517U, // ANDN32rr 1233392429U, // ANDN64rm 696521517U, // ANDN64rr 271114U, // ARPL16mr 25432842U, // ARPL16rr 1774457938U, // BEXTR32rm 696521810U, // BEXTR32rr 1778652242U, // BEXTR64rm 696521810U, // BEXTR64rr 1774457938U, // BEXTRI32mi 696521810U, // BEXTRI32ri 1778652242U, // BEXTRI64mi 696521810U, // BEXTRI64ri 29627123U, // BLCFILL32rm 25432819U, // BLCFILL32rr 33821427U, // BLCFILL64rm 25432819U, // BLCFILL64rr 29627039U, // BLCI32rm 25432735U, // BLCI32rr 33821343U, // BLCI64rm 25432735U, // BLCI64rr 29626581U, // BLCIC32rm 25432277U, // BLCIC32rr 33820885U, // BLCIC64rm 25432277U, // BLCIC64rr 29627066U, // BLCMSK32rm 25432762U, // BLCMSK32rr 33821370U, // BLCMSK64rm 25432762U, // BLCMSK64rr 29627489U, // BLCS32rm 25433185U, // BLCS32rr 33821793U, // BLCS64rm 25433185U, // BLCS64rr 29627132U, // BLSFILL32rm 25432828U, // BLSFILL32rr 33821436U, // BLSFILL64rm 25432828U, // BLSFILL64rr 29627060U, // BLSI32rm 25432756U, // BLSI32rr 33821364U, // BLSI64rm 25432756U, // BLSI64rr 29626588U, // BLSIC32rm 25432284U, // BLSIC32rr 33820892U, // BLSIC64rm 25432284U, // BLSIC64rr 29627074U, // BLSMSK32rm 25432770U, // BLSMSK32rr 33821378U, // BLSMSK64rm 25432770U, // BLSMSK64rr 29627453U, // BLSR32rm 25433149U, // BLSR32rr 33821757U, // BLSR64rm 25433149U, // BLSR64rr 29626688U, // BOUNDS16rm 33820992U, // BOUNDS32rm 38015591U, // BSF16rm 25432679U, // BSF16rr 29626983U, // BSF32rm 25432679U, // BSF32rr 33821287U, // BSF64rm 25432679U, // BSF64rr 38016056U, // BSR16rm 25433144U, // BSR16rr 29627448U, // BSR32rm 25433144U, // BSR32rr 33821752U, // BSR64rm 25433144U, // BSR64rr 4959U, // BSWAP16r_BAD 4959U, // BSWAP32r 4959U, // BSWAP64r 271555U, // BT16mi8 271555U, // BT16mr 25433283U, // BT16ri8 25433283U, // BT16rr 279747U, // BT32mi8 279747U, // BT32mr 25433283U, // BT32ri8 25433283U, // BT32rr 283843U, // BT64mi8 283843U, // BT64mr 25433283U, // BT64ri8 25433283U, // BT64rr 270576U, // BTC16mi8 270576U, // BTC16mr 4468976U, // BTC16ri8 4468976U, // BTC16rr 278768U, // BTC32mi8 278768U, // BTC32mr 4468976U, // BTC32ri8 4468976U, // BTC32rr 282864U, // BTC64mi8 282864U, // BTC64mr 4468976U, // BTC64ri8 4468976U, // BTC64rr 271427U, // BTR16mi8 271427U, // BTR16mr 4469827U, // BTR16ri8 4469827U, // BTR16rr 279619U, // BTR32mi8 279619U, // BTR32mr 4469827U, // BTR32ri8 4469827U, // BTR32rr 283715U, // BTR64mi8 283715U, // BTR64mr 4469827U, // BTR64ri8 4469827U, // BTR64rr 271537U, // BTS16mi8 271537U, // BTS16mr 4469937U, // BTS16ri8 4469937U, // BTS16rr 279729U, // BTS32mi8 279729U, // BTS32mr 4469937U, // BTS32ri8 4469937U, // BTS32rr 283825U, // BTS64mi8 283825U, // BTS64mr 4469937U, // BTS64ri8 4469937U, // BTS64rr 1774457509U, // BZHI32rm 696521381U, // BZHI32rr 1778651813U, // BZHI64rm 696521381U, // BZHI64rr 8941U, // CALL16m 8941U, // CALL16m_NT 4845U, // CALL16r 4845U, // CALL16r_NT 17133U, // CALL32m 17133U, // CALL32m_NT 4845U, // CALL32r 4845U, // CALL32r_NT 21229U, // CALL64m 21229U, // CALL64m_NT 29421U, // CALL64pcrel32 4845U, // CALL64r 4845U, // CALL64r_NT 29421U, // CALLpcrel16 29421U, // CALLpcrel32 2947U, // CBW 2702U, // CDQ 2488U, // CDQE 2352U, // CLAC 2384U, // CLC 2434U, // CLD 25167U, // CLDEMOTE 25890U, // CLFLUSHOPT 2556U, // CLGI 2566U, // CLI 17848U, // CLRSSBSY 2877U, // CLTS 24765U, // CLWB 2663U, // CLZEROr 2388U, // CMC 8654926U, // CMOVA16rm 4460622U, // CMOVA16rr 12849230U, // CMOVA32rm 4460622U, // CMOVA32rr 17043534U, // CMOVA64rm 4460622U, // CMOVA64rr 8655260U, // CMOVAE16rm 4460956U, // CMOVAE16rr 12849564U, // CMOVAE32rm 4460956U, // CMOVAE32rr 17043868U, // CMOVAE64rm 4460956U, // CMOVAE64rr 8655030U, // CMOVB16rm 4460726U, // CMOVB16rr 12849334U, // CMOVB32rm 4460726U, // CMOVB32rr 17043638U, // CMOVB64rm 4460726U, // CMOVB64rr 8655280U, // CMOVBE16rm 4460976U, // CMOVBE16rr 12849584U, // CMOVBE32rm 4460976U, // CMOVBE32rr 17043888U, // CMOVBE64rm 4460976U, // CMOVBE64rr 8655456U, // CMOVE16rm 4461152U, // CMOVE16rr 12849760U, // CMOVE32rm 4461152U, // CMOVE32rr 17044064U, // CMOVE64rm 4461152U, // CMOVE64rr 8655506U, // CMOVG16rm 4461202U, // CMOVG16rr 12849810U, // CMOVG32rm 4461202U, // CMOVG32rr 17044114U, // CMOVG64rm 4461202U, // CMOVG64rr 8655300U, // CMOVGE16rm 4460996U, // CMOVGE16rr 12849604U, // CMOVGE32rm 4460996U, // CMOVGE32rr 17043908U, // CMOVGE64rm 4460996U, // CMOVGE64rr 8655649U, // CMOVL16rm 4461345U, // CMOVL16rr 12849953U, // CMOVL32rm 4461345U, // CMOVL32rr 17044257U, // CMOVL64rm 4461345U, // CMOVL64rr 8655324U, // CMOVLE16rm 4461020U, // CMOVLE16rr 12849628U, // CMOVLE32rm 4461020U, // CMOVLE32rr 17043932U, // CMOVLE64rm 4461020U, // CMOVLE64rr 8655352U, // CMOVNE16rm 4461048U, // CMOVNE16rr 12849656U, // CMOVNE32rm 4461048U, // CMOVNE32rr 17043960U, // CMOVNE64rm 4461048U, // CMOVNE64rr 8655690U, // CMOVNO16rm 4461386U, // CMOVNO16rr 12849994U, // CMOVNO32rm 4461386U, // CMOVNO32rr 17044298U, // CMOVNO64rm 4461386U, // CMOVNO64rr 8655751U, // CMOVNP16rm 4461447U, // CMOVNP16rr 12850055U, // CMOVNP32rm 4461447U, // CMOVNP32rr 17044359U, // CMOVNP64rm 4461447U, // CMOVNP64rr 8656027U, // CMOVNS16rm 4461723U, // CMOVNS16rr 12850331U, // CMOVNS32rm 4461723U, // CMOVNS32rr 17044635U, // CMOVNS64rm 4461723U, // CMOVNS64rr 8655704U, // CMOVO16rm 4461400U, // CMOVO16rr 12850008U, // CMOVO32rm 4461400U, // CMOVO32rr 17044312U, // CMOVO64rm 4461400U, // CMOVO64rr 8655791U, // CMOVP16rm 4461487U, // CMOVP16rr 12850095U, // CMOVP32rm 4461487U, // CMOVP32rr 17044399U, // CMOVP64rm 4461487U, // CMOVP64rr 8656060U, // CMOVS16rm 4461756U, // CMOVS16rr 12850364U, // CMOVS32rm 4461756U, // CMOVS32rr 17044668U, // CMOVS64rm 4461756U, // CMOVS64rr 5767U, // CMP16i16 271216U, // CMP16mi 271216U, // CMP16mi8 271216U, // CMP16mr 25432944U, // CMP16ri 25432944U, // CMP16ri8 38015856U, // CMP16rm 25432944U, // CMP16rr 25432944U, // CMP16rr_REV 5921U, // CMP32i32 279408U, // CMP32mi 279408U, // CMP32mi8 279408U, // CMP32mr 25432944U, // CMP32ri 25432944U, // CMP32ri8 29627248U, // CMP32rm 25432944U, // CMP32rr 25432944U, // CMP32rr_REV 6025U, // CMP64i32 283504U, // CMP64mi32 283504U, // CMP64mi8 283504U, // CMP64mr 25432944U, // CMP64ri32 25432944U, // CMP64ri8 33821552U, // CMP64rm 25432944U, // CMP64rr 25432944U, // CMP64rr_REV 5665U, // CMP8i8 287600U, // CMP8mi 287600U, // CMP8mi8 287600U, // CMP8mr 25432944U, // CMP8ri 25432944U, // CMP8ri8 42210160U, // CMP8rm 25432944U, // CMP8rr 25432944U, // CMP8rr_REV 32925U, // CMPSB 37227U, // CMPSL 41941U, // CMPSQ 46450U, // CMPSW 49248U, // CMPXCHG16B 270967U, // CMPXCHG16rm 25432695U, // CMPXCHG16rr 279159U, // CMPXCHG32rm 25432695U, // CMPXCHG32rr 283255U, // CMPXCHG64rm 25432695U, // CMPXCHG64rr 20588U, // CMPXCHG8B 287351U, // CMPXCHG8rm 25432695U, // CMPXCHG8rr 2428U, // CPUID 2659U, // CQO 2464U, // CWD 2468U, // CWDE 2312U, // DAA 2783U, // DAS 2238U, // DATA16_PREFIX 8392U, // DEC16m 4296U, // DEC16r 4296U, // DEC16r_alt 16584U, // DEC32m 4296U, // DEC32r 4296U, // DEC32r_alt 20680U, // DEC64m 4296U, // DEC64r 24776U, // DEC8m 4296U, // DEC8r 9545U, // DIV16m 5449U, // DIV16r 17737U, // DIV32m 5449U, // DIV32r 21833U, // DIV64m 5449U, // DIV64r 25929U, // DIV8m 5449U, // DIV8r 2207U, // ENDBR32 2224U, // ENDBR64 25433098U, // ENTER 46412524U, // FARCALL16i 53996U, // FARCALL16m 46412524U, // FARCALL32i 53997U, // FARCALL32m 53996U, // FARCALL64 537461U, // FARJMP16i 54133U, // FARJMP16m 537461U, // FARJMP32i 54134U, // FARJMP32m 54133U, // FARJMP64 2648U, // FSETPM 2372U, // GETSEC 2902U, // HLT 9544U, // IDIV16m 5448U, // IDIV16r 17736U, // IDIV32m 5448U, // IDIV32r 21832U, // IDIV64m 5448U, // IDIV64r 25928U, // IDIV8m 5448U, // IDIV8r 8987U, // IMUL16m 4891U, // IMUL16r 8655643U, // IMUL16rm 1782846235U, // IMUL16rmi 1782846235U, // IMUL16rmi8 4461339U, // IMUL16rr 696521499U, // IMUL16rri 696521499U, // IMUL16rri8 17179U, // IMUL32m 4891U, // IMUL32r 12849947U, // IMUL32rm 1774457627U, // IMUL32rmi 1774457627U, // IMUL32rmi8 4461339U, // IMUL32rr 696521499U, // IMUL32rri 696521499U, // IMUL32rri8 21275U, // IMUL64m 4891U, // IMUL64r 17044251U, // IMUL64rm 1778651931U, // IMUL64rmi32 1778651931U, // IMUL64rmi8 4461339U, // IMUL64rr 696521499U, // IMUL64rri32 696521499U, // IMUL64rri8 25371U, // IMUL8m 4891U, // IMUL8r 59007U, // IN16ri 3093U, // IN16rr 59160U, // IN32ri 3103U, // IN32rr 58905U, // IN8ri 3083U, // IN8rr 8427U, // INC16m 4331U, // INC16r 4331U, // INC16r_alt 16619U, // INC32m 4331U, // INC32r 4331U, // INC32r_alt 20715U, // INC64m 4331U, // INC64r 24811U, // INC8m 4331U, // INC8r 4423U, // INCSSPD 5053U, // INCSSPQ 848016U, // INSB 852318U, // INSL 857445U, // INSW 58630U, // INT 2202U, // INT1 2219U, // INT3 2670U, // INTO 2450U, // INVD 50599184U, // INVEPT32 50599184U, // INVEPT64 25220U, // INVLPG 3049U, // INVLPGA32 3066U, // INVLPGA64 50598160U, // INVPCID32 50598160U, // INVPCID64 50598176U, // INVVPID32 50598176U, // INVVPID64 2882U, // IRET16 2438U, // IRET32 2725U, // IRET64 29072U, // JAE_1 29072U, // JAE_2 29072U, // JAE_4 28740U, // JA_1 28740U, // JA_2 28740U, // JA_4 29092U, // JBE_1 29092U, // JBE_2 29092U, // JBE_4 28812U, // JB_1 28812U, // JB_2 28812U, // JB_4 30153U, // JCXZ 30146U, // JECXZ 29132U, // JE_1 29132U, // JE_2 29132U, // JE_4 29112U, // JGE_1 29112U, // JGE_2 29112U, // JGE_4 29312U, // JG_1 29312U, // JG_2 29312U, // JG_4 29136U, // JLE_1 29136U, // JLE_2 29136U, // JLE_4 29416U, // JL_1 29416U, // JL_2 29416U, // JL_4 9078U, // JMP16m 9078U, // JMP16m_NT 4982U, // JMP16r 4982U, // JMP16r_NT 17270U, // JMP32m 17270U, // JMP32m_NT 4982U, // JMP32r 4982U, // JMP32r_NT 21366U, // JMP64m 21366U, // JMP64m_NT 4982U, // JMP64r 4982U, // JMP64r_NT 29558U, // JMP_1 29558U, // JMP_2 29558U, // JMP_4 29156U, // JNE_1 29156U, // JNE_2 29156U, // JNE_4 29502U, // JNO_1 29502U, // JNO_2 29502U, // JNO_4 29563U, // JNP_1 29563U, // JNP_2 29563U, // JNP_4 29839U, // JNS_1 29839U, // JNS_2 29839U, // JNS_4 29498U, // JO_1 29498U, // JO_2 29498U, // JO_4 29548U, // JP_1 29548U, // JP_2 29548U, // JP_4 30159U, // JRCXZ 29827U, // JS_1 29827U, // JS_2 29827U, // JS_4 2513U, // LAHF 38015995U, // LAR16rm 25433083U, // LAR16rr 38015995U, // LAR32rm 25433083U, // LAR32rr 38015995U, // LAR64rm 25433083U, // LAR64rr 54793319U, // LDS16rm 54793319U, // LDS32rm 58986559U, // LEA16r 58986559U, // LEA32r 58986559U, // LEA64_32r 58986559U, // LEA64r 2500U, // LEAVE 2500U, // LEAVE64 54793324U, // LES16rm 54793324U, // LES32rm 54793337U, // LFS16rm 54793337U, // LFS32rm 54793337U, // LFS64rm 54471U, // LGDT16m 54471U, // LGDT32m 54471U, // LGDT64m 54793342U, // LGS16rm 54793342U, // LGS32rm 54793342U, // LGS64rm 54483U, // LIDT16m 54483U, // LIDT32m 54483U, // LIDT64m 9439U, // LLDT16m 5343U, // LLDT16r 4220U, // LLWPCB 4220U, // LLWPCB64 9561U, // LMSW16m 5465U, // LMSW16r 2574U, // LOCK_PREFIX 75242U, // LODSB 79628U, // LODSL 83871U, // LODSQ 87747U, // LODSW 29588U, // LOOP 29184U, // LOOPE 29161U, // LOOPNE 4716U, // LRETIL 5046U, // LRETIQ 4716U, // LRETIW 2534U, // LRETL 2719U, // LRETQ 2534U, // LRETW 38015760U, // LSL16rm 25432848U, // LSL16rr 38015760U, // LSL32rm 25432848U, // LSL32rr 38015760U, // LSL64rm 25432848U, // LSL64rr 54793388U, // LSS16rm 54793388U, // LSS32rm 54793388U, // LSS64rm 9288U, // LTRm 5192U, // LTRr 1774457991U, // LWPINS32rmi 696521863U, // LWPINS32rri 1774457991U, // LWPINS64rmi 696521863U, // LWPINS64rri 1774457558U, // LWPVAL32rmi 696521430U, // LWPVAL32rri 1774457558U, // LWPVAL64rmi 696521430U, // LWPVAL64rri 38016248U, // LZCNT16rm 25433336U, // LZCNT16rr 29627640U, // LZCNT32rm 25433336U, // LZCNT32rr 33821944U, // LZCNT64rm 25433336U, // LZCNT64rr 3114U, // MONITORXrrr 2640U, // MONTMUL 91823U, // MOV16ao16 91823U, // MOV16ao32 91801U, // MOV16ao64 271694U, // MOV16mi 271694U, // MOV16mr 271694U, // MOV16ms 1140046U, // MOV16o16a 1140046U, // MOV16o32a 1139801U, // MOV16o64a 25433422U, // MOV16ri 25433422U, // MOV16ri_alt 38016334U, // MOV16rm 25433422U, // MOV16rr 25433422U, // MOV16rr_REV 25433422U, // MOV16rs 38016334U, // MOV16sm 25433422U, // MOV16sr 96077U, // MOV32ao16 96077U, // MOV32ao32 96053U, // MOV32ao64 25433422U, // MOV32cr 25433422U, // MOV32dr 279886U, // MOV32mi 279886U, // MOV32mr 1406286U, // MOV32o16a 1406286U, // MOV32o32a 1406041U, // MOV32o64a 25433422U, // MOV32rc 25433422U, // MOV32rd 25433422U, // MOV32ri 25433422U, // MOV32ri_alt 29627726U, // MOV32rm 25433422U, // MOV32rr 25433422U, // MOV32rr_REV 25433422U, // MOV32rs 25433422U, // MOV32sr 100301U, // MOV64ao32 100277U, // MOV64ao64 25433422U, // MOV64cr 25433422U, // MOV64dr 283982U, // MOV64mi32 283982U, // MOV64mr 1672526U, // MOV64o32a 1672281U, // MOV64o64a 25433422U, // MOV64rc 25433422U, // MOV64rd 25433177U, // MOV64ri 25433422U, // MOV64ri32 33822030U, // MOV64rm 25433422U, // MOV64rr 25433422U, // MOV64rr_REV 25433422U, // MOV64rs 25433422U, // MOV64sr 104009U, // MOV8ao16 104009U, // MOV8ao32 103987U, // MOV8ao64 288078U, // MOV8mi 288078U, // MOV8mr 288078U, // MOV8mr_NOREX 1938766U, // MOV8o16a 1938766U, // MOV8o32a 1938521U, // MOV8o64a 25433422U, // MOV8ri 25433422U, // MOV8ri_alt 42210638U, // MOV8rm 42210638U, // MOV8rm_NOREX 25433422U, // MOV8rr 25433422U, // MOV8rr_NOREX 25433422U, // MOV8rr_REV 270769U, // MOVBE16mr 38015409U, // MOVBE16rm 278961U, // MOVBE32mr 29626801U, // MOVBE32rm 283057U, // MOVBE64mr 33821105U, // MOVBE64rm 63180885U, // MOVDIR64B16 63180885U, // MOVDIR64B32 63180885U, // MOVDIR64B64 279211U, // MOVDIRI32 283307U, // MOVDIRI64 67432612U, // MOVSB 71631233U, // MOVSL 75867115U, // MOVSQ 80024953U, // MOVSW 38016426U, // MOVSX16rm16 42210730U, // MOVSX16rm8 25433514U, // MOVSX16rr16 25433514U, // MOVSX16rr8 38016426U, // MOVSX32rm16 42210730U, // MOVSX32rm8 42210730U, // MOVSX32rm8_NOREX 25433514U, // MOVSX32rr16 25433514U, // MOVSX32rr8 25433514U, // MOVSX32rr8_NOREX 38016426U, // MOVSX64rm16 29626760U, // MOVSX64rm32 42210730U, // MOVSX64rm8 25433514U, // MOVSX64rr16 25432456U, // MOVSX64rr32 25433514U, // MOVSX64rr8 38016433U, // MOVZX16rm16 42210737U, // MOVZX16rm8 25433521U, // MOVZX16rr16 25433521U, // MOVZX16rr8 38016433U, // MOVZX32rm16 42210737U, // MOVZX32rm8 42210737U, // MOVZX32rm8_NOREX 25433521U, // MOVZX32rr16 25433521U, // MOVZX32rr8 25433521U, // MOVZX32rr8_NOREX 38016433U, // MOVZX64rm16 42210737U, // MOVZX64rm8 25433521U, // MOVZX64rr16 25433521U, // MOVZX64rr8 8988U, // MUL16m 4892U, // MUL16r 17180U, // MUL32m 4892U, // MUL32r 21276U, // MUL64m 4892U, // MUL64r 25372U, // MUL8m 4892U, // MUL8r 159651212U, // MULX32rm 696522124U, // MULX32rr 1233393036U, // MULX64rm 696522124U, // MULX64rr 3123U, // MWAITXrrr 8818U, // NEG16m 4722U, // NEG16r 17010U, // NEG32m 4722U, // NEG32r 21106U, // NEG64m 4722U, // NEG64r 25202U, // NEG8m 4722U, // NEG8r 2686U, // NOOP 9103U, // NOOP18_16m4 9103U, // NOOP18_16m5 9103U, // NOOP18_16m6 9103U, // NOOP18_16m7 5007U, // NOOP18_16r4 5007U, // NOOP18_16r5 5007U, // NOOP18_16r6 5007U, // NOOP18_16r7 17295U, // NOOP18_m4 17295U, // NOOP18_m5 17295U, // NOOP18_m6 17295U, // NOOP18_m7 5007U, // NOOP18_r4 5007U, // NOOP18_r5 5007U, // NOOP18_r6 5007U, // NOOP18_r7 46412687U, // NOOP19rr 17295U, // NOOPL 17295U, // NOOPL_19 17295U, // NOOPL_1d 17295U, // NOOPL_1e 5007U, // NOOPLr 21391U, // NOOPQ 5007U, // NOOPQr 9103U, // NOOPW 9103U, // NOOPW_19 9103U, // NOOPW_1c 9103U, // NOOPW_1d 9103U, // NOOPW_1e 5007U, // NOOPWr 9483U, // NOT16m 5387U, // NOT16r 17675U, // NOT32m 5387U, // NOT32r 21771U, // NOT64m 5387U, // NOT64r 25867U, // NOT8m 5387U, // NOT8r 5777U, // OR16i16 271383U, // OR16mi 271383U, // OR16mi8 271383U, // OR16mr 4469783U, // OR16ri 4469783U, // OR16ri8 8664087U, // OR16rm 4469783U, // OR16rr 4461591U, // OR16rr_REV 5932U, // OR32i32 279575U, // OR32mi 279575U, // OR32mi8 279575U, // OR32mr 4469783U, // OR32ri 4469783U, // OR32ri8 12858391U, // OR32rm 4469783U, // OR32rr 4461591U, // OR32rr_REV 6060U, // OR64i32 283671U, // OR64mi32 283671U, // OR64mi8 283671U, // OR64mr 4469783U, // OR64ri32 4469783U, // OR64ri8 17052695U, // OR64rm 4469783U, // OR64rr 4461591U, // OR64rr_REV 5675U, // OR8i8 287767U, // OR8mi 287767U, // OR8mi8 287767U, // OR8mr 4469783U, // OR8ri 4469783U, // OR8ri8 21246999U, // OR8rm 4469783U, // OR8rr 4461591U, // OR8rr_REV 1107261U, // OUT16ir 2951U, // OUT16rr 1369405U, // OUT32ir 3005U, // OUT32rr 1893693U, // OUT8ir 2579U, // OUT8rr 75735U, // OUTSB 79842U, // OUTSL 88045U, // OUTSW 2539U, // PCONFIG 159650662U, // PDEP32rm 696521574U, // PDEP32rr 1233392486U, // PDEP64rm 696521574U, // PDEP64rr 159651138U, // PEXT32rm 696522050U, // PEXT32rr 1233392962U, // PEXT64rm 696522050U, // PEXT64rr 5018U, // POP16r 9114U, // POP16rmm 5018U, // POP16rmr 5018U, // POP32r 17306U, // POP32rmm 5018U, // POP32rmr 5018U, // POP64r 21402U, // POP64rmm 5018U, // POP64rmr 2941U, // POPA16 2597U, // POPA32 2803U, // POPDS16 2803U, // POPDS32 2818U, // POPES16 2818U, // POPES32 2529U, // POPF16 2422U, // POPF32 2713U, // POPF64 2833U, // POPFS16 2833U, // POPFS32 2833U, // POPFS64 2848U, // POPGS16 2848U, // POPGS32 2848U, // POPGS64 2870U, // POPSS16 2870U, // POPSS32 21062U, // PTWRITE64m 4678U, // PTWRITE64r 16966U, // PTWRITEm 4678U, // PTWRITEr 4761U, // PUSH16i8 4761U, // PUSH16r 8857U, // PUSH16rmm 4761U, // PUSH16rmr 4761U, // PUSH32i8 4761U, // PUSH32r 17049U, // PUSH32rmm 4761U, // PUSH32rmr 4761U, // PUSH64i32 4761U, // PUSH64i8 4761U, // PUSH64r 21145U, // PUSH64rmm 4761U, // PUSH64rmr 2934U, // PUSHA16 2590U, // PUSHA32 2787U, // PUSHCS16 2787U, // PUSHCS32 2795U, // PUSHDS16 2795U, // PUSHDS32 2810U, // PUSHES16 2810U, // PUSHES32 2523U, // PUSHF16 2415U, // PUSHF32 2706U, // PUSHF64 2825U, // PUSHFS16 2825U, // PUSHFS32 2825U, // PUSHFS64 2840U, // PUSHGS16 2840U, // PUSHGS32 2840U, // PUSHGS64 2862U, // PUSHSS16 2862U, // PUSHSS32 4761U, // PUSHi16 4761U, // PUSHi32 8926U, // RCL16m1 2106078U, // RCL16mCL 84157150U, // RCL16mi 2364126U, // RCL16r1 2101982U, // RCL16rCL 88347358U, // RCL16ri 17118U, // RCL32m1 2114270U, // RCL32mCL 84165342U, // RCL32mi 2364126U, // RCL32r1 2101982U, // RCL32rCL 88347358U, // RCL32ri 21214U, // RCL64m1 2118366U, // RCL64mCL 84169438U, // RCL64mi 2364126U, // RCL64r1 2101982U, // RCL64rCL 88347358U, // RCL64ri 25310U, // RCL8m1 2122462U, // RCL8mCL 84173534U, // RCL8mi 2364126U, // RCL8r1 2101982U, // RCL8rCL 88347358U, // RCL8ri 2368517U, // RCR16m1 2106373U, // RCR16mCL 84157445U, // RCR16mi 2364421U, // RCR16r1 2102277U, // RCR16rCL 88347653U, // RCR16ri 2376709U, // RCR32m1 2114565U, // RCR32mCL 84165637U, // RCR32mi 2364421U, // RCR32r1 2102277U, // RCR32rCL 88347653U, // RCR32ri 2380805U, // RCR64m1 2118661U, // RCR64mCL 84169733U, // RCR64mi 2364421U, // RCR64r1 2102277U, // RCR64rCL 88347653U, // RCR64ri 2384901U, // RCR8m1 2122757U, // RCR8mCL 84173829U, // RCR8mi 2364421U, // RCR8r1 2102277U, // RCR8rCL 88347653U, // RCR8ri 4615U, // RDFSBASE 4615U, // RDFSBASE64 4635U, // RDGSBASE 4635U, // RDGSBASE64 2757U, // RDMSR 4377U, // RDPID32 4377U, // RDPID64 2906U, // RDPKRUr 2392U, // RDPMC 4408U, // RDRAND16r 4408U, // RDRAND32r 4408U, // RDRAND64r 4360U, // RDSEED16r 4360U, // RDSEED32r 4360U, // RDSEED64r 4432U, // RDSSPD 5062U, // RDSSPQ 2405U, // RDTSC 2675U, // RDTSCP 2482U, // REPNE_PREFIX 2682U, // REP_PREFIX 5355U, // RETIL 5355U, // RETIQ 5355U, // RETIW 2883U, // RETL 2883U, // RETQ 2883U, // RETW 2232U, // REX64_PREFIX 2368261U, // ROL16m1 2106117U, // ROL16mCL 84157189U, // ROL16mi 2364165U, // ROL16r1 2102021U, // ROL16rCL 88347397U, // ROL16ri 2376453U, // ROL32m1 2114309U, // ROL32mCL 84165381U, // ROL32mi 2364165U, // ROL32r1 2102021U, // ROL32rCL 88347397U, // ROL32ri 2380549U, // ROL64m1 2118405U, // ROL64mCL 84169477U, // ROL64mi 2364165U, // ROL64r1 2102021U, // ROL64rCL 88347397U, // ROL64ri 2384645U, // ROL8m1 2122501U, // ROL8mCL 84173573U, // ROL8mi 2364165U, // ROL8r1 2102021U, // ROL8rCL 88347397U, // ROL8ri 2368534U, // ROR16m1 2106390U, // ROR16mCL 84157462U, // ROR16mi 2364438U, // ROR16r1 2102294U, // ROR16rCL 88347670U, // ROR16ri 2376726U, // ROR32m1 2114582U, // ROR32mCL 84165654U, // ROR32mi 2364438U, // ROR32r1 2102294U, // ROR32rCL 88347670U, // ROR32ri 2380822U, // ROR64m1 2118678U, // ROR64mCL 84169750U, // ROR64mi 2364438U, // ROR64r1 2102294U, // ROR64rCL 88347670U, // ROR64ri 2384918U, // ROR8m1 2122774U, // ROR8mCL 84173846U, // ROR8mi 2364438U, // ROR8r1 2102294U, // ROR8rCL 88347670U, // ROR8ri 2311329188U, // RORX32mi 2844005796U, // RORX32ri 2315523492U, // RORX64mi 2844005796U, // RORX64ri 2655U, // RSM 17311U, // RSTORSSP 2518U, // SAHF 2368209U, // SAL16m1 2106065U, // SAL16mCL 271057U, // SAL16mi 2364113U, // SAL16r1 2101969U, // SAL16rCL 4461265U, // SAL16ri 2376401U, // SAL32m1 2114257U, // SAL32mCL 279249U, // SAL32mi 2364113U, // SAL32r1 2101969U, // SAL32rCL 4461265U, // SAL32ri 2380497U, // SAL64m1 2118353U, // SAL64mCL 283345U, // SAL64mi 2364113U, // SAL64r1 2101969U, // SAL64rCL 4461265U, // SAL64ri 2384593U, // SAL8m1 2122449U, // SAL8mCL 287441U, // SAL8mi 2364113U, // SAL8r1 2101969U, // SAL8rCL 4461265U, // SAL8ri 2379U, // SALC 2368512U, // SAR16m1 2106368U, // SAR16mCL 84157440U, // SAR16mi 2364416U, // SAR16r1 2102272U, // SAR16rCL 88347648U, // SAR16ri 2376704U, // SAR32m1 2114560U, // SAR32mCL 84165632U, // SAR32mi 2364416U, // SAR32r1 2102272U, // SAR32rCL 88347648U, // SAR32ri 2380800U, // SAR64m1 2118656U, // SAR64mCL 84169728U, // SAR64mi 2364416U, // SAR64r1 2102272U, // SAR64rCL 88347648U, // SAR64ri 2384896U, // SAR8m1 2122752U, // SAR8mCL 84173824U, // SAR8mi 2364416U, // SAR8r1 2102272U, // SAR8rCL 88347648U, // SAR8ri 1774458264U, // SARX32rm 696522136U, // SARX32rr 1778652568U, // SARX64rm 696522136U, // SARX64rr 2690U, // SAVEPREVSSP 5714U, // SBB16i16 270455U, // SBB16mi 270455U, // SBB16mi8 270455U, // SBB16mr 4468855U, // SBB16ri 4468855U, // SBB16ri8 8663159U, // SBB16rm 4468855U, // SBB16rr 4460663U, // SBB16rr_REV 5838U, // SBB32i32 278647U, // SBB32mi 278647U, // SBB32mi8 278647U, // SBB32mr 4468855U, // SBB32ri 4468855U, // SBB32ri8 12857463U, // SBB32rm 4468855U, // SBB32rr 4460663U, // SBB32rr_REV 5975U, // SBB64i32 282743U, // SBB64mi32 282743U, // SBB64mi8 282743U, // SBB64mr 4468855U, // SBB64ri32 4468855U, // SBB64ri8 17051767U, // SBB64rm 4468855U, // SBB64rr 4460663U, // SBB64rr_REV 5590U, // SBB8i8 286839U, // SBB8mi 286839U, // SBB8mi8 286839U, // SBB8mr 4468855U, // SBB8ri 4468855U, // SBB8ri8 21246071U, // SBB8rm 4468855U, // SBB8rr 4460663U, // SBB8rr_REV 62943U, // SCASB 67328U, // SCASL 108435U, // SCASQ 71352U, // SCASW 24981U, // SETAEm 4501U, // SETAEr 24648U, // SETAm 4168U, // SETAr 25001U, // SETBEm 4521U, // SETBEr 24747U, // SETBm 4267U, // SETBr 25143U, // SETEm 4663U, // SETEr 25021U, // SETGEm 4541U, // SETGEr 25228U, // SETGm 4748U, // SETGr 25045U, // SETLEm 4565U, // SETLEr 25365U, // SETLm 4885U, // SETLr 25073U, // SETNEm 4593U, // SETNEr 25411U, // SETNOm 4931U, // SETNOr 25472U, // SETNPm 4992U, // SETNPr 25748U, // SETNSm 5268U, // SETNSr 25426U, // SETOm 4946U, // SETOr 25513U, // SETPm 5033U, // SETPr 3130U, // SETSSBSY 25782U, // SETSm 5302U, // SETSr 54477U, // SGDT16m 54477U, // SGDT32m 54477U, // SGDT64m 2368227U, // SHL16m1 2106083U, // SHL16mCL 84157155U, // SHL16mi 2364131U, // SHL16r1 2101987U, // SHL16rCL 88347363U, // SHL16ri 2376419U, // SHL32m1 2114275U, // SHL32mCL 84165347U, // SHL32mi 2364131U, // SHL32r1 2101987U, // SHL32rCL 88347363U, // SHL32ri 2380515U, // SHL64m1 2118371U, // SHL64mCL 84169443U, // SHL64mi 2364131U, // SHL64r1 2101987U, // SHL64rCL 88347363U, // SHL64ri 2384611U, // SHL8m1 2122467U, // SHL8mCL 84173539U, // SHL8mi 2364131U, // SHL8r1 2101987U, // SHL8rCL 88347363U, // SHL8ri 268706089U, // SHLD16mrCL 2281972009U, // SHLD16mri8 272896297U, // SHLD16rrCL 3359904041U, // SHLD16rri8 268714281U, // SHLD32mrCL 2281980201U, // SHLD32mri8 272896297U, // SHLD32rrCL 3359904041U, // SHLD32rri8 268718377U, // SHLD64mrCL 2281984297U, // SHLD64mri8 272896297U, // SHLD64rrCL 3359904041U, // SHLD64rri8 1774458246U, // SHLX32rm 696522118U, // SHLX32rr 1778652550U, // SHLX64rm 696522118U, // SHLX64rr 2368529U, // SHR16m1 2106385U, // SHR16mCL 84157457U, // SHR16mi 2364433U, // SHR16r1 2102289U, // SHR16rCL 88347665U, // SHR16ri 2376721U, // SHR32m1 2114577U, // SHR32mCL 84165649U, // SHR32mi 2364433U, // SHR32r1 2102289U, // SHR32rCL 88347665U, // SHR32ri 2380817U, // SHR64m1 2118673U, // SHR64mCL 84169745U, // SHR64mi 2364433U, // SHR64r1 2102289U, // SHR64rCL 88347665U, // SHR64ri 2384913U, // SHR8m1 2122769U, // SHR8mCL 84173841U, // SHR8mi 2364433U, // SHR8r1 2102289U, // SHR8rCL 88347665U, // SHR8ri 268706136U, // SHRD16mrCL 2281972056U, // SHRD16mri8 272896344U, // SHRD16rrCL 3359904088U, // SHRD16rri8 268714328U, // SHRD32mrCL 2281980248U, // SHRD32mri8 272896344U, // SHRD32rrCL 3359904088U, // SHRD32rri8 268718424U, // SHRD64mrCL 2281984344U, // SHRD64mri8 272896344U, // SHRD64rrCL 3359904088U, // SHRD64rri8 1774458270U, // SHRX32rm 696522142U, // SHRX32rr 1778652574U, // SHRX64rm 696522142U, // SHRX64rr 54489U, // SIDT16m 54489U, // SIDT32m 54489U, // SIDT64m 2994U, // SKINIT 9445U, // SLDT16m 5349U, // SLDT16r 5349U, // SLDT32r 5349U, // SLDT64r 4228U, // SLWPCB 4228U, // SLWPCB64 9567U, // SMSW16m 5471U, // SMSW16r 5471U, // SMSW32r 5471U, // SMSW64r 2357U, // STAC 2411U, // STC 2444U, // STD 2561U, // STGI 2570U, // STI 1896598U, // STOSB 1376612U, // STOSL 1680334U, // STOSQ 1119595U, // STOSW 5197U, // STR16r 5197U, // STR32r 5197U, // STR64r 9293U, // STRm 5723U, // SUB16i16 270513U, // SUB16mi 270513U, // SUB16mi8 270513U, // SUB16mr 4468913U, // SUB16ri 4468913U, // SUB16ri8 8663217U, // SUB16rm 4468913U, // SUB16rr 4460721U, // SUB16rr_REV 5848U, // SUB32i32 278705U, // SUB32mi 278705U, // SUB32mi8 278705U, // SUB32mr 4468913U, // SUB32ri 4468913U, // SUB32ri8 12857521U, // SUB32rm 4468913U, // SUB32rr 4460721U, // SUB32rr_REV 5985U, // SUB64i32 282801U, // SUB64mi32 282801U, // SUB64mi8 282801U, // SUB64mr 4468913U, // SUB64ri32 4468913U, // SUB64ri8 17051825U, // SUB64rm 4468913U, // SUB64rr 4460721U, // SUB64rr_REV 5621U, // SUB8i8 286897U, // SUB8mi 286897U, // SUB8mi8 286897U, // SUB8mr 4468913U, // SUB8ri 4468913U, // SUB8ri8 21246129U, // SUB8rm 4468913U, // SUB8rr 4460721U, // SUB8rr_REV 2855U, // SWAPGS 2632U, // SYSCALL 2748U, // SYSENTER 2894U, // SYSEXIT 2739U, // SYSEXIT64 2887U, // SYSRET 2731U, // SYSRET64 29626595U, // T1MSKC32rm 25432291U, // T1MSKC32rr 33820899U, // T1MSKC64rm 25432291U, // T1MSKC64rr 5797U, // TEST16i16 271662U, // TEST16mi 271662U, // TEST16mi_alt 271662U, // TEST16mr 25433390U, // TEST16ri 25433390U, // TEST16ri_alt 25433390U, // TEST16rr 5954U, // TEST32i32 279854U, // TEST32mi 279854U, // TEST32mi_alt 279854U, // TEST32mr 25433390U, // TEST32ri 25433390U, // TEST32ri_alt 25433390U, // TEST32rr 6082U, // TEST64i32 283950U, // TEST64mi32 283950U, // TEST64mi32_alt 283950U, // TEST64mr 25433390U, // TEST64ri32 25433390U, // TEST64ri32_alt 25433390U, // TEST64rr 5695U, // TEST8i8 288046U, // TEST8mi 288046U, // TEST8mi_alt 288046U, // TEST8mr 25433390U, // TEST8ri 25433390U, // TEST8ri_alt 25433390U, // TEST8rr 4655U, // TPAUSE 38016255U, // TZCNT16rm 25433343U, // TZCNT16rr 29627647U, // TZCNT32rm 25433343U, // TZCNT32rr 33821951U, // TZCNT64rm 25433343U, // TZCNT64rr 29627082U, // TZMSK32rm 25432778U, // TZMSK32rr 33821386U, // TZMSK64rm 25432778U, // TZMSK64rr 2188U, // UD0 2198U, // UD1 2215U, // UD2 5147U, // UMONITOR16 5147U, // UMONITOR32 5147U, // UMONITOR64 5360U, // UMWAIT 9266U, // VERRm 5170U, // VERRr 9555U, // VERWm 5459U, // VERWr 2625U, // VMCALL 21490U, // VMCLEARm 2398U, // VMFUNC 2547U, // VMLAUNCH 2962U, // VMLOAD32 3017U, // VMLOAD64 2617U, // VMMCALL 20783U, // VMPTRLDm 21812U, // VMPTRSTm 278778U, // VMREAD32mr 25432314U, // VMREAD32rr 282874U, // VMREAD64mr 25432314U, // VMREAD64rr 2473U, // VMRESUME 2984U, // VMRUN32 3039U, // VMRUN64 2973U, // VMSAVE32 3028U, // VMSAVE64 29626941U, // VMWRITE32rm 25432637U, // VMWRITE32rr 33821245U, // VMWRITE64rm 25432637U, // VMWRITE64rr 2506U, // VMXOFF 21299U, // VMXON 2448U, // WBINVD 2455U, // WBNOINVD 4625U, // WRFSBASE 4625U, // WRFSBASE64 4645U, // WRGSBASE 4645U, // WRGSBASE64 2763U, // WRMSR 2913U, // WRPKRUr 278898U, // WRSSD 283612U, // WRSSQ 278905U, // WRUSSD 283619U, // WRUSSQ 110850U, // XADD16rm 114946U, // XADD16rr 119042U, // XADD32rm 114946U, // XADD32rr 123138U, // XADD64rm 114946U, // XADD64rr 127234U, // XADD8rm 114946U, // XADD8rr 1061498U, // XCHG16ar 111226U, // XCHG16rm 131706U, // XCHG16rr 1323642U, // XCHG32ar 119418U, // XCHG32rm 131706U, // XCHG32rr 1585786U, // XCHG64ar 123514U, // XCHG64rm 131706U, // XCHG64rr 127610U, // XCHG8rm 131706U, // XCHG8rr 2362U, // XCRYPTCBC 2326U, // XCRYPTCFB 2769U, // XCRYPTCTR 2316U, // XCRYPTECB 2336U, // XCRYPTOFB 2920U, // XGETBV 2346U, // XLAT 5776U, // XOR16i16 271405U, // XOR16mi 271405U, // XOR16mi8 271405U, // XOR16mr 4469805U, // XOR16ri 4469805U, // XOR16ri8 8664109U, // XOR16rm 4469805U, // XOR16rr 4461613U, // XOR16rr_REV 5931U, // XOR32i32 279597U, // XOR32mi 279597U, // XOR32mi8 279597U, // XOR32mr 4469805U, // XOR32ri 4469805U, // XOR32ri8 12858413U, // XOR32rm 4469805U, // XOR32rr 4461613U, // XOR32rr_REV 6059U, // XOR64i32 283693U, // XOR64mi32 283693U, // XOR64mi8 283693U, // XOR64mr 4469805U, // XOR64ri32 4469805U, // XOR64ri8 17052717U, // XOR64rm 4469805U, // XOR64rr 4461613U, // XOR64rr_REV 5674U, // XOR8i8 287789U, // XOR8mi 287789U, // XOR8mi8 287789U, // XOR8mr 4469805U, // XOR8ri 4469805U, // XOR8ri8 21247021U, // XOR8rm 4469805U, // XOR8rr 4461613U, // XOR8rr_REV 54309U, // XRSTOR 53268U, // XRSTOR64 54435U, // XRSTORS 53288U, // XRSTORS64 53849U, // XSAVE 53259U, // XSAVE64 53453U, // XSAVEC 53249U, // XSAVEC64 54552U, // XSAVEOPT 53299U, // XSAVEOPT64 54385U, // XSAVES 53278U, // XSAVES64 2927U, // XSETBV 2192U, // XSHA1 2245U, // XSHA256 2493U, // XSTORE }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint32_t Bits = 0; Bits |= OpInfo0[opcode] << 0; SStream_concat0(O, AsmStrs+(Bits & 4095)-1); // Fragment 0 encoded into 6 bits for 33 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 63)); switch ((Bits >> 12) & 63) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // AAD8i8, AAM8i8, ADC16i16, ADC16rr_REV, ADC32i32, ADC32rr_REV, ADC64i32... printOperand(MI, 0, O); break; case 2: // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... printi16mem(MI, 0, O); break; case 3: // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... printOperand(MI, 1, O); break; case 4: // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... printi32mem(MI, 0, O); break; case 5: // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... printi64mem(MI, 0, O); break; case 6: // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... printi8mem(MI, 0, O); break; case 7: // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... printPCRelImm(MI, 0, O); return; break; case 8: // CMPSB printSrcIdx8(MI, 1, O); SStream_concat0(O, ", "); printDstIdx8(MI, 0, O); return; break; case 9: // CMPSL printSrcIdx32(MI, 1, O); SStream_concat0(O, ", "); printDstIdx32(MI, 0, O); return; break; case 10: // CMPSQ printSrcIdx64(MI, 1, O); SStream_concat0(O, ", "); printDstIdx64(MI, 0, O); return; break; case 11: // CMPSW printSrcIdx16(MI, 1, O); SStream_concat0(O, ", "); printDstIdx16(MI, 0, O); return; break; case 12: // CMPXCHG16B printi128mem(MI, 0, O); return; break; case 13: // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, LGD... printopaquemem(MI, 0, O); return; break; case 14: // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir printU8Imm(MI, 0, O); break; case 15: // INSB, MOVSB, SCASB, STOSB printDstIdx8(MI, 0, O); break; case 16: // INSL, MOVSL, SCASL, STOSL printDstIdx32(MI, 0, O); break; case 17: // INSW, MOVSW, SCASW, STOSW printDstIdx16(MI, 0, O); break; case 18: // LODSB, OUTSB printSrcIdx8(MI, 0, O); return; break; case 19: // LODSL, OUTSL printSrcIdx32(MI, 0, O); return; break; case 20: // LODSQ printSrcIdx64(MI, 0, O); return; break; case 21: // LODSW, OUTSW printSrcIdx16(MI, 0, O); return; break; case 22: // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a printMemOffs16(MI, 0, O); break; case 23: // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a printMemOffs32(MI, 0, O); break; case 24: // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a printMemOffs64(MI, 0, O); break; case 25: // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a printMemOffs8(MI, 0, O); break; case 26: // MOVSQ, SCASQ, STOSQ printDstIdx64(MI, 0, O); break; case 27: // XADD16rm, XCHG16rm printi16mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 28: // XADD16rr, XADD32rr, XADD64rr, XADD8rr printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 29: // XADD32rm, XCHG32rm printi32mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 30: // XADD64rm, XCHG64rm printi64mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 31: // XADD8rm, XCHG8rm printi8mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 32: // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; } // Fragment 1 encoded into 4 bits for 10 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 18) & 15)); switch ((Bits >> 18) & 15) { default: // unreachable case 0: // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... return; break; case 1: // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... SStream_concat0(O, ", "); break; case 2: // FARJMP16i, FARJMP32i SStream_concat0(O, ":"); printOperand(MI, 0, O); return; break; case 3: // INSB, INSL, INSW SStream_concat0(O, ", dx"); op_addReg(MI, X86_REG_DX); return; break; case 4: // MOV16o16a, MOV16o32a, MOV16o64a, OUT16ir, STOSW, XCHG16ar SStream_concat0(O, ", ax"); op_addReg(MI, X86_REG_AX); return; break; case 5: // MOV32o16a, MOV32o32a, MOV32o64a, OUT32ir, STOSL, XCHG32ar SStream_concat0(O, ", eax"); op_addReg(MI, X86_REG_EAX); return; break; case 6: // MOV64o32a, MOV64o64a, STOSQ, XCHG64ar SStream_concat0(O, ", rax"); op_addReg(MI, X86_REG_RAX); return; break; case 7: // MOV8o16a, MOV8o32a, MOV8o64a, OUT8ir, STOSB SStream_concat0(O, ", al"); op_addReg(MI, X86_REG_AL); return; break; case 8: // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R... SStream_concat0(O, ", cl"); op_addReg(MI, X86_REG_CL); return; break; case 9: // RCL16r1, RCL32r1, RCL64r1, RCL8r1, RCR16m1, RCR16r1, RCR32m1, RCR32r1,... SStream_concat0(O, ", 1"); op_addImm(MI, 1); return; break; } // Fragment 2 encoded into 5 bits for 22 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 22) & 31)); switch ((Bits >> 22) & 31) { default: // unreachable case 0: // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... printOperand(MI, 5, O); break; case 1: // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... printOperand(MI, 2, O); break; case 2: // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... printi16mem(MI, 2, O); return; break; case 3: // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, CMOVA32rm, CMOVAE32rm, ... printi32mem(MI, 2, O); return; break; case 4: // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, CMOVA64rm, CMOVAE64rm, ... printi64mem(MI, 2, O); return; break; case 5: // ADC8rm, ADD8rm, AND8rm, OR8rm, SBB8rm, SUB8rm, XOR8rm printi8mem(MI, 2, O); return; break; case 6: // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, ARPL16rr, BEXTR32rr, BEXTR64rr... printOperand(MI, 1, O); break; case 7: // BEXTR32rm, BEXTRI32mi, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, B... printi32mem(MI, 1, O); break; case 8: // BEXTR64rm, BEXTRI64mi, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, B... printi64mem(MI, 1, O); break; case 9: // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, LAR16rm, LAR32rm, LA... printi16mem(MI, 1, O); break; case 10: // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32rm8_NOREX... printi8mem(MI, 1, O); return; break; case 11: // FARCALL16i, FARCALL32i, NOOP19rr printOperand(MI, 0, O); return; break; case 12: // INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPID32, INVVPID64 printi128mem(MI, 1, O); return; break; case 13: // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... printopaquemem(MI, 1, O); return; break; case 14: // LEA16r, LEA32r, LEA64_32r, LEA64r printanymem(MI, 1, O); return; break; case 15: // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64 printi512mem(MI, 1, O); return; break; case 16: // MOVSB printSrcIdx8(MI, 1, O); return; break; case 17: // MOVSL printSrcIdx32(MI, 1, O); return; break; case 18: // MOVSQ printSrcIdx64(MI, 1, O); return; break; case 19: // MOVSW printSrcIdx16(MI, 1, O); return; break; case 20: // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... printU8Imm(MI, 5, O); return; break; case 21: // RCL16ri, RCL32ri, RCL64ri, RCL8ri, RCR16ri, RCR32ri, RCR64ri, RCR8ri, ... printU8Imm(MI, 2, O); return; break; } // Fragment 3 encoded into 2 bits for 3 unique commands. // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 27) & 3)); switch ((Bits >> 27) & 3) { default: // unreachable case 0: // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, A... return; break; case 1: // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR64r... SStream_concat0(O, ", "); break; case 2: // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHLD64mrCL, SHLD64rrCL... SStream_concat0(O, ", cl"); op_addReg(MI, X86_REG_CL); return; break; } // Fragment 4 encoded into 3 bits for 7 unique commands. // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 29) & 7)); switch ((Bits >> 29) & 7) { default: // unreachable case 0: // ANDN32rm, MULX32rm, PDEP32rm, PEXT32rm printi32mem(MI, 2, O); return; break; case 1: // ANDN32rr, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32ri, BEXTRI64ri, BZHI... printOperand(MI, 2, O); return; break; case 2: // ANDN64rm, MULX64rm, PDEP64rm, PEXT64rm printi64mem(MI, 2, O); return; break; case 3: // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... printOperand(MI, 6, O); return; break; case 4: // RORX32mi, RORX64mi, SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SH... printU8Imm(MI, 6, O); return; break; case 5: // RORX32ri, RORX64ri printU8Imm(MI, 2, O); return; break; case 6: // SHLD16rri8, SHLD32rri8, SHLD64rri8, SHRD16rri8, SHRD32rri8, SHRD64rri8 printU8Imm(MI, 3, O); return; break; } } capstone-sys-0.15.0/capstone/arch/X86/X86GenAsmWriter_reduce.inc000064400000000000000000002530710072674642500224140ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'x', 's', 'a', 'v', 'e', 'c', '6', '4', 9, 0, /* 10 */ 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, /* 19 */ 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, /* 29 */ 'x', 's', 'a', 'v', 'e', 's', '6', '4', 9, 0, /* 39 */ 'x', 'r', 's', 't', 'o', 'r', 's', '6', '4', 9, 0, /* 50 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, /* 62 */ 'j', 'a', 9, 0, /* 66 */ 's', 'e', 't', 'a', 9, 0, /* 72 */ 'm', 'o', 'v', 'd', 'i', 'r', '6', '4', 'b', 9, 0, /* 83 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, /* 95 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, /* 106 */ 's', 'b', 'b', 'b', 9, 0, /* 112 */ 's', 'u', 'b', 'b', 9, 0, /* 118 */ 'a', 'd', 'c', 'b', 9, 0, /* 124 */ 'd', 'e', 'c', 'b', 9, 0, /* 130 */ 'i', 'n', 'c', 'b', 9, 0, /* 136 */ 'l', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 144 */ 's', 'l', 'w', 'p', 'c', 'b', 9, 0, /* 152 */ 'x', 'a', 'd', 'd', 'b', 9, 0, /* 159 */ 'a', 'n', 'd', 'b', 9, 0, /* 165 */ 'n', 'e', 'g', 'b', 9, 0, /* 171 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'b', 9, 0, /* 181 */ 'j', 'b', 9, 0, /* 185 */ 's', 'a', 'l', 'b', 9, 0, /* 191 */ 'r', 'c', 'l', 'b', 9, 0, /* 197 */ 's', 'h', 'l', 'b', 9, 0, /* 203 */ 'r', 'o', 'l', 'b', 9, 0, /* 209 */ 'i', 'm', 'u', 'l', 'b', 9, 0, /* 216 */ 'i', 'n', 'b', 9, 0, /* 221 */ 'c', 'm', 'p', 'b', 9, 0, /* 227 */ 's', 'a', 'r', 'b', 9, 0, /* 233 */ 'r', 'c', 'r', 'b', 9, 0, /* 239 */ 's', 'h', 'r', 'b', 9, 0, /* 245 */ 'r', 'o', 'r', 'b', 9, 0, /* 251 */ 'x', 'o', 'r', 'b', 9, 0, /* 257 */ 's', 'c', 'a', 's', 'b', 9, 0, /* 264 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, 0, /* 273 */ 'l', 'o', 'd', 's', 'b', 9, 0, /* 280 */ 'c', 'm', 'p', 's', 'b', 9, 0, /* 287 */ 'o', 'u', 't', 's', 'b', 9, 0, /* 294 */ 'm', 'o', 'v', 's', 'b', 9, 0, /* 301 */ 's', 'e', 't', 'b', 9, 0, /* 307 */ 'n', 'o', 't', 'b', 9, 0, /* 313 */ 't', 'e', 's', 't', 'b', 9, 0, /* 320 */ 'i', 'd', 'i', 'v', 'b', 9, 0, /* 327 */ 'm', 'o', 'v', 'b', 9, 0, /* 333 */ 'c', 'l', 'w', 'b', 9, 0, /* 339 */ 'x', 's', 'a', 'v', 'e', 'c', 9, 0, /* 347 */ 'a', 'a', 'd', 9, 0, /* 352 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, /* 361 */ 'r', 'd', 'p', 'i', 'd', 9, 0, /* 368 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, /* 377 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, /* 386 */ 'b', 'o', 'u', 'n', 'd', 9, 0, /* 393 */ 'i', 'n', 'c', 's', 's', 'p', 'd', 9, 0, /* 402 */ 'r', 'd', 's', 's', 'p', 'd', 9, 0, /* 410 */ 'w', 'r', 's', 's', 'd', 9, 0, /* 417 */ 'w', 'r', 'u', 's', 's', 'd', 9, 0, /* 425 */ 'j', 'a', 'e', 9, 0, /* 430 */ 's', 'e', 't', 'a', 'e', 9, 0, /* 437 */ 'j', 'b', 'e', 9, 0, /* 442 */ 's', 'e', 't', 'b', 'e', 9, 0, /* 449 */ 'j', 'g', 'e', 9, 0, /* 454 */ 's', 'e', 't', 'g', 'e', 9, 0, /* 461 */ 'j', 'e', 9, 0, /* 465 */ 'j', 'l', 'e', 9, 0, /* 470 */ 's', 'e', 't', 'l', 'e', 9, 0, /* 477 */ 'j', 'n', 'e', 9, 0, /* 482 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, /* 490 */ 's', 'e', 't', 'n', 'e', 9, 0, /* 497 */ 'l', 'o', 'o', 'p', 'e', 9, 0, /* 504 */ 't', 'p', 'a', 'u', 's', 'e', 9, 0, /* 512 */ 's', 'e', 't', 'e', 9, 0, /* 518 */ 'c', 'l', 'd', 'e', 'm', 'o', 't', 'e', 9, 0, /* 528 */ 'x', 's', 'a', 'v', 'e', 9, 0, /* 535 */ 'j', 'g', 9, 0, /* 539 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, /* 547 */ 's', 'e', 't', 'g', 9, 0, /* 553 */ 'm', 'o', 'v', 'd', 'i', 'r', 'i', 9, 0, /* 562 */ 'l', 'e', 'a', 'l', 9, 0, /* 568 */ 'c', 'm', 'o', 'v', 'a', 'l', 9, 0, /* 576 */ 'l', 'w', 'p', 'v', 'a', 'l', 9, 0, /* 584 */ 's', 'b', 'b', 'l', 9, 0, /* 590 */ 'm', 'o', 'v', 's', 'b', 'l', 9, 0, /* 598 */ 's', 'u', 'b', 'l', 9, 0, /* 604 */ 'c', 'm', 'o', 'v', 'b', 'l', 9, 0, /* 612 */ 'm', 'o', 'v', 'z', 'b', 'l', 9, 0, /* 620 */ 'a', 'd', 'c', 'l', 9, 0, /* 626 */ 'd', 'e', 'c', 'l', 9, 0, /* 632 */ 'b', 'l', 'c', 'i', 'c', 'l', 9, 0, /* 640 */ 'b', 'l', 's', 'i', 'c', 'l', 9, 0, /* 648 */ 't', '1', 'm', 's', 'k', 'c', 'l', 9, 0, /* 657 */ 'i', 'n', 'c', 'l', 9, 0, /* 663 */ 'b', 't', 'c', 'l', 9, 0, /* 669 */ 'v', 'm', 'r', 'e', 'a', 'd', 'l', 9, 0, /* 678 */ 'x', 'a', 'd', 'd', 'l', 9, 0, /* 685 */ 'r', 'd', 's', 'e', 'e', 'd', 'l', 9, 0, /* 694 */ 's', 'h', 'l', 'd', 'l', 9, 0, /* 701 */ 'r', 'd', 'r', 'a', 'n', 'd', 'l', 9, 0, /* 710 */ 's', 'h', 'r', 'd', 'l', 9, 0, /* 717 */ 'c', 'm', 'o', 'v', 'a', 'e', 'l', 9, 0, /* 726 */ 'c', 'm', 'o', 'v', 'b', 'e', 'l', 9, 0, /* 735 */ 'c', 'm', 'o', 'v', 'g', 'e', 'l', 9, 0, /* 744 */ 'c', 'm', 'o', 'v', 'l', 'e', 'l', 9, 0, /* 753 */ 'c', 'm', 'o', 'v', 'n', 'e', 'l', 9, 0, /* 762 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 773 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 784 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 795 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, /* 806 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, /* 816 */ 'p', 't', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, /* 826 */ 'c', 'm', 'o', 'v', 'e', 'l', 9, 0, /* 834 */ 'b', 's', 'f', 'l', 9, 0, /* 840 */ 'n', 'e', 'g', 'l', 9, 0, /* 846 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'l', 9, 0, /* 856 */ 'c', 'm', 'o', 'v', 'g', 'l', 9, 0, /* 864 */ 'p', 'u', 's', 'h', 'l', 9, 0, /* 871 */ 'b', 'l', 'c', 'i', 'l', 9, 0, /* 878 */ 'b', 'z', 'h', 'i', 'l', 9, 0, /* 885 */ 'b', 'l', 's', 'i', 'l', 9, 0, /* 892 */ 'j', 'l', 9, 0, /* 896 */ 'b', 'l', 'c', 'm', 's', 'k', 'l', 9, 0, /* 905 */ 'b', 'l', 's', 'm', 's', 'k', 'l', 9, 0, /* 914 */ 't', 'z', 'm', 's', 'k', 'l', 9, 0, /* 922 */ 's', 'a', 'l', 'l', 9, 0, /* 928 */ 'r', 'c', 'l', 'l', 9, 0, /* 934 */ 's', 'h', 'l', 'l', 9, 0, /* 940 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, 0, /* 948 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 'l', 9, 0, /* 958 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 'l', 9, 0, /* 968 */ 'r', 'o', 'l', 'l', 9, 0, /* 974 */ 'l', 's', 'l', 'l', 9, 0, /* 980 */ 'i', 'm', 'u', 'l', 'l', 9, 0, /* 987 */ 'c', 'm', 'o', 'v', 'l', 'l', 9, 0, /* 995 */ 'a', 'n', 'd', 'n', 'l', 9, 0, /* 1002 */ 'i', 'n', 'l', 9, 0, /* 1007 */ 'c', 'm', 'o', 'v', 'n', 'o', 'l', 9, 0, /* 1016 */ 'c', 'm', 'o', 'v', 'o', 'l', 9, 0, /* 1024 */ 'b', 's', 'w', 'a', 'p', 'l', 9, 0, /* 1032 */ 'p', 'd', 'e', 'p', 'l', 9, 0, /* 1039 */ 'c', 'm', 'p', 'l', 9, 0, /* 1045 */ 'l', 'j', 'm', 'p', 'l', 9, 0, /* 1052 */ 'c', 'm', 'o', 'v', 'n', 'p', 'l', 9, 0, /* 1061 */ 'n', 'o', 'p', 'l', 9, 0, /* 1067 */ 'p', 'o', 'p', 'l', 9, 0, /* 1073 */ 'a', 'r', 'p', 'l', 9, 0, /* 1079 */ 'c', 'm', 'o', 'v', 'p', 'l', 9, 0, /* 1087 */ 'l', 'a', 'r', 'l', 9, 0, /* 1093 */ 's', 'a', 'r', 'l', 9, 0, /* 1099 */ 'r', 'c', 'r', 'l', 9, 0, /* 1105 */ 's', 'h', 'r', 'l', 9, 0, /* 1111 */ 'r', 'o', 'r', 'l', 9, 0, /* 1117 */ 'x', 'o', 'r', 'l', 9, 0, /* 1123 */ 'b', 's', 'r', 'l', 9, 0, /* 1129 */ 'b', 'l', 's', 'r', 'l', 9, 0, /* 1136 */ 'b', 't', 'r', 'l', 9, 0, /* 1142 */ 's', 't', 'r', 'l', 9, 0, /* 1148 */ 'b', 'e', 'x', 't', 'r', 'l', 9, 0, /* 1156 */ 's', 'c', 'a', 's', 'l', 9, 0, /* 1163 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, 0, /* 1172 */ 'b', 'l', 'c', 's', 'l', 9, 0, /* 1179 */ 'l', 'd', 's', 'l', 9, 0, /* 1185 */ 'l', 'o', 'd', 's', 'l', 9, 0, /* 1192 */ 'l', 'e', 's', 'l', 9, 0, /* 1198 */ 'l', 'f', 's', 'l', 9, 0, /* 1204 */ 'l', 'g', 's', 'l', 9, 0, /* 1210 */ 'c', 'm', 'o', 'v', 'n', 's', 'l', 9, 0, /* 1219 */ 'c', 'm', 'p', 's', 'l', 9, 0, /* 1226 */ 'l', 's', 's', 'l', 9, 0, /* 1232 */ 'b', 't', 's', 'l', 9, 0, /* 1238 */ 'o', 'u', 't', 's', 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2247 */ 'n', 'o', 't', 'q', 9, 0, /* 2253 */ 't', 'e', 's', 't', 'q', 9, 0, /* 2260 */ 'p', 'e', 'x', 't', 'q', 9, 0, /* 2267 */ 'i', 'd', 'i', 'v', 'q', 9, 0, /* 2274 */ 'm', 'o', 'v', 'q', 9, 0, /* 2280 */ 's', 'm', 's', 'w', 'q', 9, 0, /* 2287 */ 'm', 'o', 'v', 's', 'w', 'q', 9, 0, /* 2295 */ 'm', 'o', 'v', 'z', 'w', 'q', 9, 0, /* 2303 */ 'a', 'd', 'c', 'x', 'q', 9, 0, /* 2310 */ 's', 'h', 'l', 'x', 'q', 9, 0, /* 2317 */ 'm', 'u', 'l', 'x', 'q', 9, 0, /* 2324 */ 'a', 'd', 'o', 'x', 'q', 9, 0, /* 2331 */ 's', 'a', 'r', 'x', 'q', 9, 0, /* 2338 */ 's', 'h', 'r', 'x', 'q', 9, 0, /* 2345 */ 'r', 'o', 'r', 'x', 'q', 9, 0, /* 2352 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, /* 2361 */ 'e', 'n', 't', 'e', 'r', 9, 0, /* 2368 */ 'u', 'm', 'o', 'n', 'i', 't', 'o', 'r', 9, 0, /* 2378 */ 'x', 'r', 's', 't', 'o', 'r', 9, 0, /* 2386 */ 'v', 'e', 'r', 'r', 9, 0, /* 2392 */ 'x', 's', 'a', 'v', 'e', 's', 9, 0, /* 2400 */ 'l', 'g', 's', 9, 0, /* 2405 */ 'j', 's', 9, 0, /* 2409 */ 'l', 'w', 'p', 'i', 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3436 */ 's', 'h', 'r', 'w', 9, '$', '1', ',', 32, 0, /* 3446 */ 'r', 'o', 'r', 'w', 9, '$', '1', ',', 32, 0, /* 3456 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 3470 */ 's', 't', 'o', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 3482 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 3493 */ 'm', 'o', 'v', 'b', 9, '%', 'a', 'l', ',', 32, 0, /* 3504 */ 's', 'a', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3515 */ 'r', 'c', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3526 */ 's', 'h', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3537 */ 'r', 'o', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3548 */ 's', 'a', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3559 */ 'r', 'c', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3570 */ 's', 'h', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3581 */ 'r', 'o', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, /* 3592 */ 's', 'h', 'l', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3604 */ 's', 'h', 'r', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3616 */ 's', 'a', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3627 */ 'r', 'c', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3638 */ 's', 'h', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3649 */ 'r', 'o', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3660 */ 's', 'a', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3671 */ 'r', 'c', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3682 */ 's', 'h', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3693 */ 'r', 'o', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, /* 3704 */ 's', 'h', 'l', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3716 */ 's', 'h', 'r', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3728 */ 's', 'a', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3739 */ 'r', 'c', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3750 */ 's', 'h', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3761 */ 'r', 'o', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3772 */ 's', 'a', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3783 */ 'r', 'c', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, /* 3794 */ 's', 'h', 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0, /* 4507 */ 's', 't', 'a', 'c', 0, /* 4512 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, /* 4522 */ 'g', 'e', 't', 's', 'e', 'c', 0, /* 4529 */ 's', 'a', 'l', 'c', 0, /* 4534 */ 'c', 'l', 'c', 0, /* 4538 */ 'c', 'm', 'c', 0, /* 4542 */ 'r', 'd', 'p', 'm', 'c', 0, /* 4548 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, /* 4555 */ 'r', 'd', 't', 's', 'c', 0, /* 4561 */ 's', 't', 'c', 0, /* 4565 */ 'c', 'p', 'u', 'i', 'd', 0, /* 4571 */ 'c', 'l', 'd', 0, /* 4575 */ 'c', 'l', 't', 'd', 0, /* 4580 */ 's', 't', 'd', 0, /* 4584 */ 'c', 'w', 't', 'd', 0, /* 4589 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, /* 4596 */ 'w', 'b', 'n', 'o', 'i', 'n', 'v', 'd', 0, /* 4605 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, /* 4614 */ 'r', 'e', 'p', 'n', 'e', 0, /* 4620 */ 'x', 's', 't', 'o', 'r', 'e', 0, /* 4627 */ 'l', 'e', 'a', 'v', 'e', 0, /* 4633 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, /* 4640 */ 'l', 'a', 'h', 'f', 0, /* 4645 */ 's', 'a', 'h', 'f', 0, /* 4650 */ 'p', 'c', 'o', 'n', 'f', 'i', 'g', 0, /* 4658 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, /* 4667 */ 'c', 'l', 'g', 'i', 0, /* 4672 */ 's', 't', 'g', 'i', 0, /* 4677 */ 'c', 'l', 'i', 0, /* 4681 */ 's', 't', 'i', 0, /* 4685 */ 'l', 'o', 'c', 'k', 0, /* 4690 */ 'i', 'n', 'b', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'l', 0, /* 4703 */ 'p', 'u', 's', 'h', 'a', 'l', 0, /* 4710 */ 'p', 'o', 'p', 'a', 'l', 0, /* 4716 */ 'p', 'u', 's', 'h', 'f', 'l', 0, /* 4723 */ 'p', 'o', 'p', 'f', 'l', 0, /* 4729 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, /* 4743 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, /* 4751 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, /* 4758 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, /* 4766 */ 'i', 'r', 'e', 't', 'l', 0, /* 4772 */ 'l', 'r', 'e', 't', 'l', 0, /* 4778 */ 's', 'y', 's', 'r', 'e', 't', 'l', 0, /* 4786 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'l', 0, /* 4795 */ 'c', 'w', 't', 'l', 0, /* 4800 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, /* 4808 */ 'f', 's', 'e', 't', 'p', 'm', 0, /* 4815 */ 'r', 's', 'm', 0, /* 4819 */ 'c', 'l', 'z', 'e', 'r', 'o', 0, /* 4826 */ 'i', 'n', 't', 'o', 0, /* 4831 */ 'c', 'q', 't', 'o', 0, /* 4836 */ 'r', 'd', 't', 's', 'c', 'p', 0, /* 4843 */ 'r', 'e', 'p', 0, /* 4847 */ 'n', 'o', 'p', 0, /* 4851 */ 's', 'a', 'v', 'e', 'p', 'r', 'e', 'v', 's', 's', 'p', 0, /* 4863 */ 'p', 'u', 's', 'h', 'f', 'q', 0, /* 4870 */ 'p', 'o', 'p', 'f', 'q', 0, /* 4876 */ 'i', 'r', 'e', 't', 'q', 0, /* 4882 */ 'l', 'r', 'e', 't', 'q', 0, /* 4888 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, /* 4896 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, /* 4905 */ 'c', 'l', 't', 'q', 0, /* 4910 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, /* 4919 */ 'r', 'd', 'm', 's', 'r', 0, /* 4925 */ 'w', 'r', 'm', 's', 'r', 0, /* 4931 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, /* 4941 */ 'a', 'a', 's', 0, /* 4945 */ 'd', 'a', 's', 0, /* 4949 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'c', 's', 0, /* 4959 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'c', 's', 0, /* 4969 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'd', 's', 0, /* 4979 */ 'p', 'o', 'p', 'l', 9, '%', 'd', 's', 0, /* 4988 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'd', 's', 0, /* 4998 */ 'p', 'o', 'p', 'w', 9, '%', 'd', 's', 0, /* 5007 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'e', 's', 0, /* 5017 */ 'p', 'o', 'p', 'l', 9, '%', 'e', 's', 0, /* 5026 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'e', 's', 0, /* 5036 */ 'p', 'o', 'p', 'w', 9, '%', 'e', 's', 0, /* 5045 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'f', 's', 0, /* 5055 */ 'p', 'o', 'p', 'l', 9, '%', 'f', 's', 0, /* 5064 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'f', 's', 0, /* 5074 */ 'p', 'o', 'p', 'q', 9, '%', 'f', 's', 0, /* 5083 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'f', 's', 0, /* 5093 */ 'p', 'o', 'p', 'w', 9, '%', 'f', 's', 0, /* 5102 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'g', 's', 0, /* 5112 */ 'p', 'o', 'p', 'l', 9, '%', 'g', 's', 0, /* 5121 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'g', 's', 0, /* 5131 */ 'p', 'o', 'p', 'q', 9, '%', 'g', 's', 0, /* 5140 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'g', 's', 0, /* 5150 */ 'p', 'o', 'p', 'w', 9, '%', 'g', 's', 0, /* 5159 */ 's', 'w', 'a', 'p', 'g', 's', 0, /* 5166 */ 'p', 'u', 's', 'h', 'l', 9, '%', 's', 's', 0, /* 5176 */ 'p', 'o', 'p', 'l', 9, '%', 's', 's', 0, /* 5185 */ 'p', 'u', 's', 'h', 'w', 9, '%', 's', 's', 0, /* 5195 */ 'p', 'o', 'p', 'w', 9, '%', 's', 's', 0, /* 5204 */ 'c', 'l', 't', 's', 0, /* 5209 */ 'h', 'l', 't', 0, /* 5213 */ 'r', 'd', 'p', 'k', 'r', 'u', 0, /* 5220 */ 'w', 'r', 'p', 'k', 'r', 'u', 0, /* 5227 */ 'x', 'g', 'e', 't', 'b', 'v', 0, /* 5234 */ 'x', 's', 'e', 't', 'b', 'v', 0, /* 5241 */ 'p', 'u', 's', 'h', 'a', 'w', 0, /* 5248 */ 'p', 'o', 'p', 'a', 'w', 0, /* 5254 */ 'p', 'u', 's', 'h', 'f', 'w', 0, /* 5261 */ 'p', 'o', 'p', 'f', 'w', 0, /* 5267 */ 'c', 'b', 't', 'w', 0, /* 5272 */ 'i', 'r', 'e', 't', 'w', 0, /* 5278 */ 'l', 'r', 'e', 't', 'w', 0, /* 5284 */ 'i', 'n', 'w', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'x', 0, /* 5297 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'e', 'a', 'x', 0, /* 5309 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'e', 'a', 'x', 0, /* 5321 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'e', 'a', 'x', 0, /* 5332 */ 's', 'k', 'i', 'n', 'i', 't', 9, '%', 'e', 'a', 'x', 0, /* 5344 */ 'i', 'n', 'l', 9, '%', 'd', 'x', ',', 32, '%', 'e', 'a', 'x', 0, /* 5358 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'r', 'a', 'x', 0, /* 5370 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'r', 'a', 'x', 0, /* 5382 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'r', 'a', 'x', 0, /* 5393 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, /* 5412 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'r', 'a', 'x', ',', 32, '%', 'e', 'c', 'x', 0, /* 5431 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, '%', 'd', 'x', 0, /* 5445 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, '%', 'd', 'x', 0, /* 5459 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'd', 'x', 0, /* 5474 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 'x', 0, /* 5483 */ 'm', 'w', 'a', 'i', 't', 'x', 0, /* 5490 */ 's', 'e', 't', 's', 's', 'b', 's', 'y', 0, }; #endif static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 4424U, // DBG_VALUE 4434U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 4417U, // BUNDLE 4444U, // LIFETIME_START 4404U, // LIFETIME_END 0U, // STACKMAP 4730U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // LOCAL_ESCAPE 0U, // FAULTING_OP 0U, // PATCHABLE_OP 4271U, // PATCHABLE_FUNCTION_ENTER 4191U, // PATCHABLE_RET 4317U, // PATCHABLE_FUNCTION_EXIT 4294U, // PATCHABLE_TAIL_CALL 4246U, // PATCHABLE_EVENT_CALL 4222U, // PATCHABLE_TYPED_EVENT_CALL 0U, // ICALL_BRANCH_FUNNEL 0U, // G_ADD 0U, // G_SUB 0U, // G_MUL 0U, // G_SDIV 0U, // G_UDIV 0U, // G_SREM 0U, // G_UREM 0U, // G_AND 0U, // G_OR 0U, // G_XOR 0U, // G_IMPLICIT_DEF 0U, // G_PHI 0U, // G_FRAME_INDEX 0U, // G_GLOBAL_VALUE 0U, // G_EXTRACT 0U, // G_UNMERGE_VALUES 0U, // G_INSERT 0U, // G_MERGE_VALUES 0U, // G_PTRTOINT 0U, // G_INTTOPTR 0U, // G_BITCAST 0U, // G_LOAD 0U, // G_SEXTLOAD 0U, // G_ZEXTLOAD 0U, // G_STORE 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 0U, // G_ATOMIC_CMPXCHG 0U, // G_ATOMICRMW_XCHG 0U, // G_ATOMICRMW_ADD 0U, // G_ATOMICRMW_SUB 0U, // G_ATOMICRMW_AND 0U, // G_ATOMICRMW_NAND 0U, // G_ATOMICRMW_OR 0U, // G_ATOMICRMW_XOR 0U, // G_ATOMICRMW_MAX 0U, // G_ATOMICRMW_MIN 0U, // G_ATOMICRMW_UMAX 0U, // G_ATOMICRMW_UMIN 0U, // G_BRCOND 0U, // G_BRINDIRECT 0U, // G_INTRINSIC 0U, // G_INTRINSIC_W_SIDE_EFFECTS 0U, // G_ANYEXT 0U, // G_TRUNC 0U, // G_CONSTANT 0U, // G_FCONSTANT 0U, // G_VASTART 0U, // G_VAARG 0U, // G_SEXT 0U, // G_ZEXT 0U, // G_SHL 0U, // G_LSHR 0U, // G_ASHR 0U, // G_ICMP 0U, // G_FCMP 0U, // G_SELECT 0U, // G_UADDE 0U, // G_USUBE 0U, // G_SADDO 0U, // G_SSUBO 0U, // G_UMULO 0U, // G_SMULO 0U, // G_UMULH 0U, // G_SMULH 0U, // G_FADD 0U, // G_FSUB 0U, // G_FMUL 0U, // G_FMA 0U, // G_FDIV 0U, // G_FREM 0U, // G_FPOW 0U, // G_FEXP 0U, // G_FEXP2 0U, // G_FLOG 0U, // G_FLOG2 0U, // G_FNEG 0U, // G_FPEXT 0U, // G_FPTRUNC 0U, // G_FPTOSI 0U, // G_FPTOUI 0U, // G_SITOFP 0U, // G_UITOFP 0U, // G_FABS 0U, // G_GEP 0U, // G_PTR_MASK 0U, // G_BR 0U, // G_INSERT_VECTOR_ELT 0U, // G_EXTRACT_VECTOR_ELT 0U, // G_SHUFFLE_VECTOR 0U, // G_BSWAP 0U, // G_ADDRSPACE_CAST 0U, // G_BLOCK_ADDR 4459U, // AAA 8540U, // AAD8i8 9620U, // AAM8i8 4942U, // AAS 535027U, // ADC16i16 1067507U, // ADC16mi 1067507U, // ADC16mi8 1067507U, // ADC16mr 1599987U, // ADC16ri 1599987U, // ADC16ri8 1608179U, // ADC16rm 1599987U, // ADC16rr 2124275U, // ADC16rr_REV 2630253U, // ADC32i32 3162733U, // ADC32mi 3162733U, // ADC32mi8 3162733U, // ADC32mr 1598061U, // ADC32ri 1598061U, // ADC32ri8 1614445U, // ADC32rm 1598061U, // ADC32rr 2122349U, // ADC32rr_REV 3679768U, // ADC64i32 4212248U, // ADC64mi32 4212248U, // ADC64mi8 4212248U, // ADC64mr 1599000U, // ADC64ri32 1599000U, // ADC64ri8 1623576U, // ADC64rm 1599000U, // ADC64rr 2123288U, // ADC64rr_REV 4726903U, // ADC8i8 5259383U, // ADC8mi 5259383U, // ADC8mi8 5259383U, // ADC8mr 1597559U, // ADC8ri 1597559U, // ADC8ri8 57463U, // ADC8rm 1597559U, // ADC8rr 2121847U, // ADC8rr_REV 2139491U, // ADCX32rm 2123107U, // ADCX32rr 2148608U, // ADCX64rm 2124032U, // ADCX64rr 535052U, // ADD16i16 1067532U, // ADD16mi 1067532U, // ADD16mi8 1067532U, // ADD16mr 1600012U, // ADD16ri 1600012U, // ADD16ri8 1608204U, // ADD16rm 1600012U, // ADD16rr 2124300U, // ADD16rr_REV 2630312U, // ADD32i32 3162792U, // ADD32mi 3162792U, // ADD32mi8 3162792U, // ADD32mr 1598120U, // ADD32ri 1598120U, // ADD32ri8 1614504U, // ADD32rm 1598120U, // ADD32rr 2122408U, // ADD32rr_REV 3679827U, // ADD64i32 4212307U, // ADD64mi32 4212307U, // ADD64mi8 4212307U, // ADD64mr 1599059U, // ADD64ri32 1599059U, // ADD64ri8 1623635U, // ADD64rm 1599059U, // ADD64rr 2123347U, // ADD64rr_REV 4726938U, // ADD8i8 5259418U, // ADD8mi 5259418U, // ADD8mi8 5259418U, // ADD8mr 1597594U, // ADD8ri 1597594U, // ADD8ri8 57498U, // ADD8rm 1597594U, // ADD8rr 2121882U, // ADD8rr_REV 2139512U, // ADOX32rm 2123128U, // ADOX32rr 2148629U, // ADOX64rm 2124053U, // ADOX64rr 535077U, // AND16i16 1067557U, // AND16mi 1067557U, // AND16mi8 1067557U, // AND16mr 1600037U, // AND16ri 1600037U, // AND16ri8 1608229U, // AND16rm 1600037U, // AND16rr 2124325U, // AND16rr_REV 2630337U, // AND32i32 3162817U, // AND32mi 3162817U, // AND32mi8 3162817U, // AND32mr 1598145U, // AND32ri 1598145U, // AND32ri8 1614529U, // AND32rm 1598145U, // AND32rr 2122433U, // AND32rr_REV 3679852U, // AND64i32 4212332U, // AND64mi32 4212332U, // AND64mi8 4212332U, // AND64mr 1599084U, // AND64ri32 1599084U, // AND64ri8 1623660U, // AND64rm 1599084U, // AND64rr 2123372U, // AND64rr_REV 4726944U, // AND8i8 5259424U, // AND8mi 5259424U, // AND8mi8 5259424U, // AND8mr 1597600U, // AND8ri 1597600U, // AND8ri8 57504U, // AND8rm 1597600U, // AND8rr 2121888U, // AND8rr_REV 18392036U, // ANDN32rm 18375652U, // ANDN32rr 18401170U, // ANDN64rm 18376594U, // ANDN64rr 1066034U, // ARPL16mr 39388210U, // ARPL16rr 6366333U, // BEXTR32rm 18375805U, // BEXTR32rr 6891562U, // BEXTR64rm 18376746U, // BEXTR64rr 6366333U, // BEXTRI32mi 18375805U, // BEXTRI32ri 6891562U, // BEXTRI64mi 18376746U, // BEXTRI64ri 82869U, // BLCFILL32rm 39388085U, // BLCFILL32rr 91995U, // BLCFILL64rm 39389019U, // BLCFILL64rr 82792U, // BLCI32rm 39388008U, // BLCI32rr 91923U, // BLCI64rm 39388947U, // BLCI64rr 82553U, // BLCIC32rm 39387769U, // BLCIC32rr 91684U, // BLCIC64rm 39388708U, // BLCIC64rr 82817U, // BLCMSK32rm 39388033U, // BLCMSK32rr 91944U, // BLCMSK64rm 39388968U, // BLCMSK64rr 83093U, // BLCS32rm 39388309U, // BLCS32rr 92226U, // BLCS64rm 39389250U, // BLCS64rr 82879U, // BLSFILL32rm 39388095U, // BLSFILL32rr 92005U, // BLSFILL64rm 39389029U, // BLSFILL64rr 82806U, // BLSI32rm 39388022U, // BLSI32rr 91937U, // BLSI64rm 39388961U, // BLSI64rr 82561U, // BLSIC32rm 39387777U, // BLSIC32rr 91692U, // BLSIC64rm 39388716U, // BLSIC64rr 82826U, // BLSMSK32rm 39388042U, // BLSMSK32rr 91953U, // BLSMSK64rm 39388977U, // BLSMSK64rr 83050U, // BLSR32rm 39388266U, // BLSR32rr 92183U, // BLSR64rm 39389207U, // BLSR64rr 56107395U, // BOUNDS16rm 72884611U, // BOUNDS32rm 100967U, // BSF16rm 39389799U, // BSF16rr 82755U, // BSF32rm 39387971U, // BSF32rr 91886U, // BSF64rm 39388910U, // BSF64rr 101171U, // BSR16rm 39390003U, // BSR16rr 83044U, // BSR32rm 39388260U, // BSR32rr 92177U, // BSR64rm 39389201U, // BSR64rr 10967U, // BSWAP16r_BAD 9217U, // BSWAP32r 10154U, // BSWAP64r 1067941U, // BT16mi8 1067941U, // BT16mr 39390117U, // BT16ri8 39390117U, // BT16rr 3163366U, // BT32mi8 3163366U, // BT32mr 39388390U, // BT32ri8 39388390U, // BT32rr 4212873U, // BT64mi8 4212873U, // BT64mr 39389321U, // BT64ri8 39389321U, // BT64rr 1067525U, // BTC16mi8 1067525U, // BTC16mr 1600005U, // BTC16ri8 1600005U, // BTC16rr 3162776U, // BTC32mi8 3162776U, // BTC32mr 1598104U, // BTC32ri8 1598104U, // BTC32rr 4212291U, // BTC64mi8 4212291U, // BTC64mr 1599043U, // BTC64ri8 1599043U, // BTC64rr 1067833U, // BTR16mi8 1067833U, // BTR16mr 1600313U, // BTR16ri8 1600313U, // BTR16rr 3163249U, // BTR32mi8 3163249U, // BTR32mr 1598577U, // BTR32ri8 1598577U, // BTR32rr 4212766U, // BTR64mi8 4212766U, // BTR64mr 1599518U, // BTR64ri8 1599518U, // BTR64rr 1067920U, // BTS16mi8 1067920U, // BTS16mr 1600400U, // BTS16ri8 1600400U, // BTS16rr 3163345U, // BTS32mi8 3163345U, // BTS32mr 1598673U, // BTS32ri8 1598673U, // BTS32rr 4212859U, // BTS64mi8 4212859U, // BTS64mr 1599611U, // BTS64ri8 1599611U, // BTS64rr 6366063U, // BZHI32rm 18375535U, // BZHI32rr 6891290U, // BZHI64rm 18376474U, // BZHI64rr 110671U, // CALL16m 110671U, // CALL16m_NT 12367U, // CALL16r 12367U, // CALL16r_NT 118829U, // CALL32m 118829U, // CALL32m_NT 12333U, // CALL32r 12333U, // CALL32r_NT 127038U, // CALL64m 127038U, // CALL64m_NT 132948U, // CALL64pcrel32 12350U, // CALL64r 12350U, // CALL64r_NT 133791U, // CALLpcrel16 132014U, // CALLpcrel32 5268U, // CBW 4576U, // CDQ 4906U, // CDQE 4503U, // CLAC 4535U, // CLC 4572U, // CLD 139783U, // CLDEMOTE 141740U, // CLFLUSHOPT 4668U, // CLGI 4678U, // CLI 117795U, // CLRSSBSY 5205U, // CLTS 139598U, // CLWB 4820U, // CLZEROr 4539U, // CMC 2132423U, // CMOVA16rm 2124231U, // CMOVA16rr 2138681U, // CMOVA32rm 2122297U, // CMOVA32rr 2147820U, // CMOVA64rm 2123244U, // CMOVA64rr 2132530U, // CMOVAE16rm 2124338U, // CMOVAE16rr 2138830U, // CMOVAE32rm 2122446U, // CMOVAE32rr 2147961U, // CMOVAE64rm 2123385U, // CMOVAE64rr 2132451U, // CMOVB16rm 2124259U, // CMOVB16rr 2138717U, // CMOVB32rm 2122333U, // CMOVB32rr 2147848U, // CMOVB64rm 2123272U, // CMOVB64rr 2132539U, // CMOVBE16rm 2124347U, // CMOVBE16rr 2138839U, // CMOVBE32rm 2122455U, // CMOVBE32rr 2147970U, // CMOVBE64rm 2123394U, // CMOVBE64rr 2132575U, // CMOVE16rm 2124383U, // CMOVE16rr 2138939U, // CMOVE32rm 2122555U, // CMOVE32rr 2148070U, // CMOVE64rm 2123494U, // CMOVE64rr 2132605U, // CMOVG16rm 2124413U, // CMOVG16rr 2138969U, // CMOVG32rm 2122585U, // CMOVG32rr 2148100U, // CMOVG64rm 2123524U, // CMOVG64rr 2132548U, // CMOVGE16rm 2124356U, // CMOVGE16rr 2138848U, // CMOVGE32rm 2122464U, // CMOVGE32rr 2147979U, // CMOVGE64rm 2123403U, // CMOVGE64rr 2132665U, // CMOVL16rm 2124473U, // CMOVL16rr 2139100U, // CMOVL32rm 2122716U, // CMOVL32rr 2148234U, // CMOVL64rm 2123658U, // CMOVL64rr 2132557U, // CMOVLE16rm 2124365U, // CMOVLE16rr 2138857U, // CMOVLE32rm 2122473U, // CMOVLE32rr 2147988U, // CMOVLE64rm 2123412U, // CMOVLE64rr 2132566U, // CMOVNE16rm 2124374U, // CMOVNE16rr 2138866U, // CMOVNE32rm 2122482U, // CMOVNE32rr 2147997U, // CMOVNE64rm 2123421U, // CMOVNE64rr 2132678U, // CMOVNO16rm 2124486U, // CMOVNO16rr 2139120U, // CMOVNO32rm 2122736U, // CMOVNO32rr 2148249U, // CMOVNO64rm 2123673U, // CMOVNO64rr 2132716U, // CMOVNP16rm 2124524U, // CMOVNP16rr 2139165U, // CMOVNP32rm 2122781U, // CMOVNP32rr 2148287U, // CMOVNP64rm 2123711U, // CMOVNP64rr 2132858U, // CMOVNS16rm 2124666U, // CMOVNS16rr 2139323U, // CMOVNS32rm 2122939U, // CMOVNS32rr 2148438U, // CMOVNS64rm 2123862U, // CMOVNS64rr 2132687U, // CMOVO16rm 2124495U, // CMOVO16rr 2139129U, // CMOVO32rm 2122745U, // CMOVO32rr 2148258U, // CMOVO64rm 2123682U, // CMOVO64rr 2132737U, // CMOVP16rm 2124545U, // CMOVP16rr 2139192U, // CMOVP32rm 2122808U, // CMOVP32rr 2148325U, // CMOVP64rm 2123749U, // CMOVP64rr 2132893U, // CMOVS16rm 2124701U, // CMOVS16rr 2139358U, // CMOVS32rm 2122974U, // CMOVS32rr 2148481U, // CMOVS64rm 2123905U, // CMOVS64rr 535263U, // CMP16i16 1067743U, // CMP16mi 1067743U, // CMP16mi8 1067743U, // CMP16mr 39389919U, // CMP16ri 39389919U, // CMP16ri8 101087U, // CMP16rm 39389919U, // CMP16rr 39389919U, // CMP16rr_REV 2630672U, // CMP32i32 3163152U, // CMP32mi 3163152U, // CMP32mi8 3163152U, // CMP32mr 39388176U, // CMP32ri 39388176U, // CMP32ri8 82960U, // CMP32rm 39388176U, // CMP32rr 39388176U, // CMP32rr_REV 3680185U, // CMP64i32 4212665U, // CMP64mi32 4212665U, // CMP64mi8 4212665U, // CMP64mr 39389113U, // CMP64ri32 39389113U, // CMP64ri8 92089U, // CMP64rm 39389113U, // CMP64rr 39389113U, // CMP64rr_REV 4727006U, // CMP8i8 5259486U, // CMP8mi 5259486U, // CMP8mi8 5259486U, // CMP8mr 39387358U, // CMP8ri 39387358U, // CMP8ri8 147678U, // CMP8rm 39387358U, // CMP8rr 39387358U, // CMP8rr_REV 89809177U, // CMPSB 106595524U, // CMPSL 123381855U, // CMPSQ 140168067U, // CMPSW 188500U, // CMPXCHG16B 1067635U, // CMPXCHG16rm 39389811U, // CMPXCHG16rr 3162959U, // CMPXCHG32rm 39387983U, // CMPXCHG32rr 4212474U, // CMPXCHG64rm 39388922U, // CMPXCHG64rr 122976U, // CMPXCHG8B 5259436U, // CMPXCHG8rm 39387308U, // CMPXCHG8rr 4566U, // CPUID 4832U, // CQO 4585U, // CWD 4796U, // CWDE 4463U, // DAA 4946U, // DAS 4389U, // DATA16_PREFIX 109049U, // DEC16m 10745U, // DEC16r 10745U, // DEC16r_alt 115315U, // DEC32m 8819U, // DEC32r 8819U, // DEC32r_alt 124446U, // DEC64m 9758U, // DEC64r 139389U, // DEC8m 8317U, // DEC8r 109561U, // DIV16m 11257U, // DIV16r 116032U, // DIV32m 9536U, // DIV32r 125149U, // DIV64m 10461U, // DIV64r 139586U, // DIV8m 8514U, // DIV8r 4358U, // ENDBR32 4375U, // ENDBR64 156772666U, // ENTER 39389854U, // FARCALL16i 200782U, // FARCALL16m 39388077U, // FARCALL32i 200748U, // FARCALL32m 200765U, // FARCALL64 7408357U, // FARJMP16i 200791U, // FARJMP16m 7406614U, // FARJMP32i 200757U, // FARJMP32m 200774U, // FARJMP64 4809U, // FSETPM 4523U, // GETSEC 5210U, // HLT 109560U, // IDIV16m 11256U, // IDIV16r 116031U, // IDIV32m 9535U, // IDIV32r 125148U, // IDIV64m 10460U, // IDIV64r 139585U, // IDIV8m 8513U, // IDIV8r 109234U, // IMUL16m 10930U, // IMUL16r 2132658U, // IMUL16rm 7940786U, // IMUL16rmi 7940786U, // IMUL16rmi8 2124466U, // IMUL16rr 18377394U, // IMUL16rri 18377394U, // IMUL16rri8 115669U, // IMUL32m 9173U, // IMUL32r 2139093U, // IMUL32rm 6366165U, // IMUL32rmi 6366165U, // IMUL32rmi8 2122709U, // IMUL32rr 18375637U, // IMUL32rri 18375637U, // IMUL32rri8 124803U, // IMUL64m 10115U, // IMUL64r 2148227U, // IMUL64rm 6891395U, // IMUL64rmi32 6891395U, // IMUL64rmi8 2123651U, // IMUL64rr 18376579U, // IMUL64rri32 18376579U, // IMUL64rri8 139474U, // IMUL8m 8402U, // IMUL8r 731841U, // IN16ri 5285U, // IN16rr 2827243U, // IN32ri 5345U, // IN32rr 4923609U, // IN8ri 4691U, // IN8rr 109055U, // INC16m 10751U, // INC16r 10751U, // INC16r_alt 115346U, // INC32m 8850U, // INC32r 8850U, // INC32r_alt 124477U, // INC64m 9789U, // INC64r 139395U, // INC8m 8323U, // INC8r 8586U, // INCSSPD 10196U, // INCSSPQ 159755U, // INSB 167958U, // INSL 184353U, // INSW 207253U, // INT 4353U, // INT1 4370U, // INT3 4827U, // INTO 4592U, // INVD 215450U, // INVEPT32 215450U, // INVEPT64 139804U, // INVLPG 5394U, // INVLPGA32 5413U, // INVLPGA64 213345U, // INVPCID32 213345U, // INVPCID64 213361U, // INVVPID32 213361U, // INVVPID64 5273U, // IRET16 4767U, // IRET32 4877U, // IRET64 131498U, // JAE_1 131498U, // JAE_2 131498U, // JAE_4 131135U, // JA_1 131135U, // JA_2 131135U, // JA_4 131510U, // JBE_1 131510U, // JBE_2 131510U, // JBE_4 131254U, // JB_1 131254U, // JB_2 131254U, // JB_4 134196U, // JCXZ 134189U, // JECXZ 131534U, // JE_1 131534U, // JE_2 131534U, // JE_4 131522U, // JGE_1 131522U, // JGE_2 131522U, // JGE_4 131608U, // JG_1 131608U, // JG_2 131608U, // JG_4 131538U, // JLE_1 131538U, // JLE_2 131538U, // JLE_4 131965U, // JL_1 131965U, // JL_2 131965U, // JL_4 110680U, // JMP16m 110680U, // JMP16m_NT 12376U, // JMP16r 12376U, // JMP16r_NT 118838U, // JMP32m 118838U, // JMP32m_NT 12342U, // JMP32r 12342U, // JMP32r_NT 127047U, // JMP64m 127047U, // JMP64m_NT 12359U, // JMP64r 12359U, // JMP64r_NT 132538U, // JMP_1 132538U, // JMP_2 132538U, // JMP_4 131550U, // JNE_1 131550U, // JNE_2 131550U, // JNE_4 132516U, // JNO_1 132516U, // JNO_2 132516U, // JNO_4 132543U, // JNP_1 132543U, // JNP_2 132543U, // JNP_4 133490U, // JNS_1 133490U, // JNS_2 133490U, // JNS_4 132512U, // JO_1 132512U, // JO_2 132512U, // JO_4 132534U, // JP_1 132534U, // JP_2 132534U, // JP_4 134202U, // JRCXZ 133478U, // JS_1 133478U, // JS_2 133478U, // JS_4 4641U, // LAHF 101129U, // LAR16rm 39389961U, // LAR16rr 99392U, // LAR32rm 39388224U, // LAR32rr 100333U, // LAR64rm 39389165U, // LAR64rr 224091U, // LDS16rm 222364U, // LDS32rm 231873U, // LEA16r 229939U, // LEA32r 229939U, // LEA64_32r 230886U, // LEA64r 4628U, // LEAVE 4628U, // LEAVE64 224104U, // LES16rm 222377U, // LES32rm 224110U, // LFS16rm 222383U, // LFS32rm 223312U, // LFS64rm 199594U, // LGDT16m 197867U, // LGDT32m 198798U, // LGDT64m 224116U, // LGS16rm 222389U, // LGS32rm 223585U, // LGS64rm 199608U, // LIDT16m 197881U, // LIDT32m 198812U, // LIDT64m 109510U, // LLDT16m 11206U, // LLDT16r 8329U, // LLWPCB 8329U, // LLWPCB64 109573U, // LMSW16m 11269U, // LMSW16r 4686U, // LOCK_PREFIX 4956434U, // LODSB 2868386U, // LODSL 256073U, // LODSQ 789345U, // LODSW 132560U, // LOOP 131570U, // LOOPE 131555U, // LOOPNE 9486U, // LRETIL 10417U, // LRETIQ 11220U, // LRETIW 4773U, // LRETL 4883U, // LRETQ 5279U, // LRETW 101036U, // LSL16rm 39389868U, // LSL16rr 99279U, // LSL32rm 39388111U, // LSL32rr 100213U, // LSL64rm 39389045U, // LSL64rr 224138U, // LSS16rm 222411U, // LSS32rm 223334U, // LSS64rm 109375U, // LTRm 11071U, // LTRr 6367594U, // LWPINS32rmi 18377066U, // LWPINS32rri 6367594U, // LWPINS64rmi 18377066U, // LWPINS64rri 6365761U, // LWPVAL32rmi 18375233U, // LWPVAL32rri 6365761U, // LWPVAL64rmi 18375233U, // LWPVAL64rri 101339U, // LZCNT16rm 39390171U, // LZCNT16rr 83227U, // LZCNT32rm 39388443U, // LZCNT32rr 92344U, // LZCNT64rm 39389368U, // LZCNT64rr 5475U, // MONITORXrrr 4801U, // MONTMUL 797695U, // MOV16ao16 797695U, // MOV16ao32 797522U, // MOV16ao64 1068031U, // MOV16mi 1068031U, // MOV16mr 1068031U, // MOV16ms 274314U, // MOV16o16a 274314U, // MOV16o32a 274277U, // MOV16o64a 39390207U, // MOV16ri 39390207U, // MOV16ri_alt 101375U, // MOV16rm 39390207U, // MOV16rr 39390207U, // MOV16rr_REV 39390207U, // MOV16rs 101375U, // MOV16sm 39390207U, // MOV16sr 2901318U, // MOV32ao16 2901318U, // MOV32ao32 2901132U, // MOV32ao64 39388486U, // MOV32cr 39388486U, // MOV32dr 3163462U, // MOV32mi 3163462U, // MOV32mr 282570U, // MOV32o16a 282570U, // MOV32o32a 282530U, // MOV32o64a 39388486U, // MOV32rc 39388486U, // MOV32rd 39388486U, // MOV32ri 39388486U, // MOV32ri_alt 83270U, // MOV32rm 39388486U, // MOV32rr 39388486U, // MOV32rr_REV 39388486U, // MOV32rs 39388486U, // MOV32sr 3959011U, // MOV64ao32 3958841U, // MOV64ao64 39389411U, // MOV64cr 39389411U, // MOV64dr 4212963U, // MOV64mi32 4212963U, // MOV64mr 290815U, // MOV64o32a 290787U, // MOV64o64a 39389411U, // MOV64rc 39389411U, // MOV64rd 39389241U, // MOV64ri 39389411U, // MOV64ri32 92387U, // MOV64rm 39389411U, // MOV64rr 39389411U, // MOV64rr_REV 39389411U, // MOV64rs 39389411U, // MOV64sr 5013832U, // MOV8ao16 5013832U, // MOV8ao32 5013769U, // MOV8ao64 5259592U, // MOV8mi 5259592U, // MOV8mr 5259592U, // MOV8mr_NOREX 298406U, // MOV8o16a 298406U, // MOV8o32a 298369U, // MOV8o64a 39387464U, // MOV8ri 39387464U, // MOV8ri_alt 147784U, // MOV8rm 147784U, // MOV8rm_NOREX 39387464U, // MOV8rr 39387464U, // MOV8rr_NOREX 39387464U, // MOV8rr_REV 1067580U, // MOVBE16mr 100924U, // MOVBE16rm 3162840U, // MOVBE32mr 82648U, // MOVBE32rm 4212355U, // MOVBE64mr 91779U, // MOVBE64rm 303177U, // MOVDIR64B16 303177U, // MOVDIR64B32 303177U, // MOVDIR64B64 3162666U, // MOVDIRI32 4211242U, // MOVDIRI64 311591U, // MOVSB 320735U, // MOVSL 329858U, // MOVSQ 338846U, // MOVSW 101395U, // MOVSX16rm16 149973U, // MOVSX16rm8 39390227U, // MOVSX16rr16 39389653U, // MOVSX16rr8 99667U, // MOVSX32rm16 148047U, // MOVSX32rm8 148047U, // MOVSX32rm8_NOREX 39388499U, // MOVSX32rr16 39387727U, // MOVSX32rr8 39387727U, // MOVSX32rr8_NOREX 100592U, // MOVSX64rm16 83835U, // MOVSX64rm32 148986U, // MOVSX64rm8 39389424U, // MOVSX64rr16 39389051U, // MOVSX64rr32 39388666U, // MOVSX64rr8 101403U, // MOVZX16rm16 149995U, // MOVZX16rm8 39390235U, // MOVZX16rr16 39389675U, // MOVZX16rr8 99675U, // MOVZX32rm16 148069U, // MOVZX32rm8 148069U, // MOVZX32rm8_NOREX 39388507U, // MOVZX32rr16 39387749U, // MOVZX32rr8 39387749U, // MOVZX32rr8_NOREX 100600U, // MOVZX64rm16 149008U, // MOVZX64rm8 39389432U, // MOVZX64rr16 39388688U, // MOVZX64rr8 109235U, // MUL16m 10931U, // MUL16r 115670U, // MUL32m 9174U, // MUL32r 124804U, // MUL64m 10116U, // MUL64r 139475U, // MUL8m 8403U, // MUL8r 18392433U, // MULX32rm 18376049U, // MULX32rr 18401550U, // MULX64rm 18376974U, // MULX64rr 5484U, // MWAITXrrr 109165U, // NEG16m 10861U, // NEG16r 115529U, // NEG32m 9033U, // NEG32r 124660U, // NEG64m 9972U, // NEG64r 139430U, // NEG8m 8358U, // NEG8r 4848U, // NOOP 109301U, // NOOP18_16m4 109301U, // NOOP18_16m5 109301U, // NOOP18_16m6 109301U, // NOOP18_16m7 10997U, // NOOP18_16r4 10997U, // NOOP18_16r5 10997U, // NOOP18_16r6 10997U, // NOOP18_16r7 115750U, // NOOP18_m4 115750U, // NOOP18_m5 115750U, // NOOP18_m6 115750U, // NOOP18_m7 9254U, // NOOP18_r4 9254U, // NOOP18_r5 9254U, // NOOP18_r6 9254U, // NOOP18_r7 156771787U, // NOOP19rr 115750U, // NOOPL 115750U, // NOOPL_19 115750U, // NOOPL_1d 115750U, // NOOPL_1e 9254U, // NOOPLr 124872U, // NOOPQ 10184U, // NOOPQr 109301U, // NOOPW 109301U, // NOOPW_19 109301U, // NOOPW_1c 109301U, // NOOPW_1d 109301U, // NOOPW_1e 10997U, // NOOPWr 109547U, // NOT16m 11243U, // NOT16r 116011U, // NOT32m 9515U, // NOT32r 125128U, // NOT64m 10440U, // NOT64r 139572U, // NOT8m 8500U, // NOT8r 535336U, // OR16i16 1067816U, // OR16mi 1067816U, // OR16mi8 1067816U, // OR16mr 1600296U, // OR16ri 1600296U, // OR16ri8 1608488U, // OR16rm 1600296U, // OR16rr 2124584U, // OR16rr_REV 2630745U, // OR32i32 3163225U, // OR32mi 3163225U, // OR32mi8 3163225U, // OR32mr 1598553U, // OR32ri 1598553U, // OR32ri8 1614937U, // OR32rm 1598553U, // OR32rr 2122841U, // OR32rr_REV 3680262U, // OR64i32 4212742U, // OR64mi32 4212742U, // OR64mi8 4212742U, // OR64mr 1599494U, // OR64ri32 1599494U, // OR64ri8 1624070U, // OR64rm 1599494U, // OR64rr 2123782U, // OR64rr_REV 4727031U, // OR8i8 5259511U, // OR8mi 5259511U, // OR8mi8 5259511U, // OR8mr 1597687U, // OR8ri 1597687U, // OR8ri8 57591U, // OR8rm 1597687U, // OR8rr 2121975U, // OR8rr_REV 208767U, // OUT16ir 5446U, // OUT16rr 208830U, // OUT32ir 5460U, // OUT32rr 208283U, // OUT8ir 5432U, // OUT8rr 8626464U, // OUTSB 8635607U, // OUTSL 8653718U, // OUTSW 4651U, // PCONFIG 18392073U, // PDEP32rm 18375689U, // PDEP32rr 18401202U, // PDEP64rm 18376626U, // PDEP64rr 18392376U, // PEXT32rm 18375992U, // PEXT32rr 18401493U, // PEXT64rm 18376917U, // PEXT64rr 11003U, // POP16r 109307U, // POP16rmm 11003U, // POP16rmr 9260U, // POP32r 115756U, // POP32rmm 9260U, // POP32rmr 10190U, // POP64r 124878U, // POP64rmm 10190U, // POP64rmr 5249U, // POPA16 4711U, // POPA32 4999U, // POPDS16 4980U, // POPDS32 5037U, // POPES16 5018U, // POPES32 5262U, // POPF16 4724U, // POPF32 4871U, // POPF64 5094U, // POPFS16 5056U, // POPFS32 5075U, // POPFS64 5151U, // POPGS16 5113U, // POPGS32 5132U, // POPGS64 5196U, // POPSS16 5177U, // POPSS32 124636U, // PTWRITE64m 9948U, // PTWRITE64r 115505U, // PTWRITEm 9009U, // PTWRITEr 10885U, // PUSH16i8 10885U, // PUSH16r 109189U, // PUSH16rmm 10885U, // PUSH16rmr 9057U, // PUSH32i8 9057U, // PUSH32r 115553U, // PUSH32rmm 9057U, // PUSH32rmr 9996U, // PUSH64i32 9996U, // PUSH64i8 9996U, // PUSH64r 124684U, // PUSH64rmm 9996U, // PUSH64rmr 5242U, // PUSHA16 4704U, // PUSHA32 4960U, // PUSHCS16 4950U, // PUSHCS32 4989U, // PUSHDS16 4970U, // PUSHDS32 5027U, // PUSHES16 5008U, // PUSHES32 5255U, // PUSHF16 4717U, // PUSHF32 4864U, // PUSHF64 5084U, // PUSHFS16 5046U, // PUSHFS32 5065U, // PUSHFS64 5141U, // PUSHGS16 5103U, // PUSHGS32 5122U, // PUSHGS64 5186U, // PUSHSS16 5167U, // PUSHSS32 10885U, // PUSHi16 9057U, // PUSHi32 109202U, // RCL16m1 110348U, // RCL16mCL 1395346U, // RCL16mi 11579U, // RCL16r1 12044U, // RCL16rCL 2452114U, // RCL16ri 115617U, // RCL32m1 118316U, // RCL32mCL 3490721U, // RCL32mi 11419U, // RCL32r1 11820U, // RCL32rCL 2450337U, // RCL32ri 124744U, // RCL64m1 126620U, // RCL64mCL 4540232U, // RCL64mi 11499U, // RCL64r1 11932U, // RCL64rCL 2451272U, // RCL64ri 139456U, // RCL8m1 142780U, // RCL8mCL 5587136U, // RCL8mi 11339U, // RCL8r1 11708U, // RCL8rCL 2449600U, // RCL8ri 109923U, // RCR16m1 110392U, // RCR16mCL 1395477U, // RCR16mi 11619U, // RCR16r1 12088U, // RCR16rCL 2452245U, // RCR16ri 117955U, // RCR32m1 118360U, // RCR32mCL 3490892U, // RCR32mi 11459U, // RCR32r1 11864U, // RCR32rCL 2450508U, // RCR32ri 126227U, // RCR64m1 126664U, // RCR64mCL 4540409U, // RCR64mi 11539U, // RCR64r1 11976U, // RCR64rCL 2451449U, // RCR64ri 142451U, // RCR8m1 142824U, // RCR8mCL 5587178U, // RCR8mi 11379U, // RCR8r1 11752U, // RCR8rCL 2449642U, // RCR8ri 8955U, // RDFSBASE 9894U, // RDFSBASE64 8977U, // RDGSBASE 9916U, // RDGSBASE64 4920U, // RDMSR 8554U, // RDPID32 8554U, // RDPID64 5214U, // RDPKRUr 4543U, // RDPMC 10786U, // RDRAND16r 8894U, // RDRAND32r 9833U, // RDRAND64r 10770U, // RDSEED16r 8878U, // RDSEED32r 9817U, // RDSEED64r 8595U, // RDSSPD 10205U, // RDSSPQ 4556U, // RDTSC 4837U, // RDTSCP 4615U, // REPNE_PREFIX 4844U, // REP_PREFIX 9487U, // RETIL 10418U, // RETIQ 11221U, // RETIW 4768U, // RETL 4878U, // RETQ 5274U, // RETW 4383U, // REX64_PREFIX 109222U, // ROL16m1 110370U, // ROL16mCL 1395366U, // ROL16mi 11599U, // ROL16r1 12066U, // ROL16rCL 2452134U, // ROL16ri 115657U, // ROL32m1 118338U, // ROL32mCL 3490761U, // ROL32mi 11439U, // ROL32r1 11842U, // ROL32rCL 2450377U, // ROL32ri 124783U, // ROL64m1 126642U, // ROL64mCL 4540271U, // ROL64mi 11519U, // ROL64r1 11954U, // ROL64rCL 2451311U, // ROL64ri 139468U, // ROL8m1 142802U, // ROL8mCL 5587148U, // ROL8mi 11359U, // ROL8r1 11730U, // ROL8rCL 2449612U, // ROL8ri 109351U, // ROR16m1 110414U, // ROR16mCL 1395495U, // ROR16mi 11639U, // ROR16r1 12110U, // ROR16rCL 2452263U, // ROR16ri 115800U, // ROR32m1 118382U, // ROR32mCL 3490904U, // ROR32mi 11479U, // ROR32r1 11886U, // ROR32rCL 2450520U, // ROR32ri 124933U, // ROR64m1 126686U, // ROR64mCL 4540421U, // ROR64mi 11559U, // ROR64r1 11998U, // ROR64rCL 2451461U, // ROR64ri 139510U, // ROR8m1 142846U, // ROR8mCL 5587190U, // ROR8mi 11399U, // ROR8r1 11774U, // ROR8rCL 2449654U, // ROR8ri 6653325U, // RORX32mi 18703757U, // RORX32ri 7178538U, // RORX64mi 18704682U, // RORX64ri 4816U, // RSM 116182U, // RSTORSSP 4646U, // SAHF 109196U, // SAL16m1 110337U, // SAL16mCL 1067660U, // SAL16mi 11569U, // SAL16r1 12033U, // SAL16rCL 2124428U, // SAL16ri 115611U, // SAL32m1 118305U, // SAL32mCL 3163035U, // SAL32mi 11409U, // SAL32r1 11809U, // SAL32rCL 2122651U, // SAL32ri 124738U, // SAL64m1 126609U, // SAL64mCL 4212546U, // SAL64mi 11489U, // SAL64r1 11921U, // SAL64rCL 2123586U, // SAL64ri 139450U, // SAL8m1 142769U, // SAL8mCL 5259450U, // SAL8mi 11329U, // SAL8r1 11697U, // SAL8rCL 2121914U, // SAL8ri 4530U, // SALC 109327U, // SAR16m1 110381U, // SAR16mCL 1395471U, // SAR16mi 11609U, // SAR16r1 12077U, // SAR16rCL 2452239U, // SAR16ri 115782U, // SAR32m1 118349U, // SAR32mCL 3490886U, // SAR32mi 11449U, // SAR32r1 11853U, // SAR32rCL 2450502U, // SAR32ri 124915U, // SAR64m1 126653U, // SAR64mCL 4540403U, // SAR64mi 11529U, // SAR64r1 11965U, // SAR64rCL 2451443U, // SAR64ri 139492U, // SAR8m1 142813U, // SAR8mCL 5587172U, // SAR8mi 11369U, // SAR8r1 11741U, // SAR8rCL 2449636U, // SAR8ri 6366591U, // SARX32rm 18376063U, // SARX32rr 6891804U, // SARX64rm 18376988U, // SARX64rr 4852U, // SAVEPREVSSP 534991U, // SBB16i16 1067471U, // SBB16mi 1067471U, // SBB16mi8 1067471U, // SBB16mr 1599951U, // SBB16ri 1599951U, // SBB16ri8 1608143U, // SBB16rm 1599951U, // SBB16rr 2124239U, // SBB16rr_REV 2630217U, // SBB32i32 3162697U, // SBB32mi 3162697U, // SBB32mi8 3162697U, // SBB32mr 1598025U, // SBB32ri 1598025U, // SBB32ri8 1614409U, // SBB32rm 1598025U, // SBB32rr 2122313U, // SBB32rr_REV 3679732U, // SBB64i32 4212212U, // SBB64mi32 4212212U, // SBB64mi8 4212212U, // SBB64mr 1598964U, // SBB64ri32 1598964U, // SBB64ri8 1623540U, // SBB64rm 1598964U, // SBB64rr 2123252U, // SBB64rr_REV 4726891U, // SBB8i8 5259371U, // SBB8mi 5259371U, // SBB8mi8 5259371U, // SBB8mr 1597547U, // SBB8ri 1597547U, // SBB8ri8 57451U, // SBB8rm 1597547U, // SBB8rr 2121835U, // SBB8rr_REV 4874498U, // SCASB 2786437U, // SCASL 3844146U, // SCASQ 707403U, // SCASW 139695U, // SETAEm 8623U, // SETAEr 139331U, // SETAm 8259U, // SETAr 139707U, // SETBEm 8635U, // SETBEr 139566U, // SETBm 8494U, // SETBr 139777U, // SETEm 8705U, // SETEr 139719U, // SETGEm 8647U, // SETGEr 139812U, // SETGm 8740U, // SETGr 139735U, // SETLEm 8663U, // SETLEr 140565U, // SETLm 9493U, // SETLr 139755U, // SETNEm 8683U, // SETNEr 140713U, // SETNOm 9641U, // SETNOr 140740U, // SETNPm 9668U, // SETNPr 141687U, // SETNSm 10615U, // SETNSr 140720U, // SETOm 9648U, // SETOr 140768U, // SETPm 9696U, // SETPr 5491U, // SETSSBSY 141703U, // SETSm 10631U, // SETSr 199601U, // SGDT16m 197874U, // SGDT32m 198805U, // SGDT64m 109208U, // SHL16m1 110359U, // SHL16mCL 1395352U, // SHL16mi 11589U, // SHL16r1 12055U, // SHL16rCL 2452120U, // SHL16ri 115623U, // SHL32m1 118327U, // SHL32mCL 3490727U, // SHL32mi 11429U, // SHL32r1 11831U, // SHL32rCL 2450343U, // SHL32ri 124750U, // SHL64m1 126631U, // SHL64mCL 4540238U, // SHL64mi 11509U, // SHL64r1 11943U, // SHL64rCL 2451278U, // SHL64ri 139462U, // SHL8m1 142791U, // SHL8mCL 5587142U, // SHL8mi 11349U, // SHL8r1 11719U, // SHL8rCL 2449606U, // SHL8ri 1068777U, // SHLD16mrCL 177048091U, // SHLD16mri8 2125545U, // SHLD16rrCL 371227U, // SHLD16rri8 3165705U, // SHLD32mrCL 193823415U, // SHLD32mri8 2125321U, // SHLD32rrCL 369335U, // SHLD32rri8 4214393U, // SHLD64mrCL 210601570U, // SHLD64mri8 2125433U, // SHLD64rrCL 370274U, // SHLD64rri8 6366570U, // SHLX32rm 18376042U, // SHLX32rr 6891783U, // SHLX64rm 18376967U, // SHLX64rr 109345U, // SHR16m1 110403U, // SHR16mCL 1395489U, // SHR16mi 11629U, // SHR16r1 12099U, // SHR16rCL 2452257U, // SHR16ri 115794U, // SHR32m1 118371U, // SHR32mCL 3490898U, // SHR32mi 11469U, // SHR32r1 11875U, // SHR32rCL 2450514U, // SHR32ri 124927U, // SHR64m1 126675U, // SHR64mCL 4540415U, // SHR64mi 11549U, // SHR64r1 11987U, // SHR64rCL 2451455U, // SHR64ri 139504U, // SHR8m1 142835U, // SHR8mCL 5587184U, // SHR8mi 11389U, // SHR8r1 11763U, // SHR8rCL 2449648U, // SHR8ri 1068789U, // SHRD16mrCL 177048107U, // SHRD16mri8 2125557U, // SHRD16rrCL 371243U, // SHRD16rri8 3165717U, // SHRD32mrCL 193823431U, // SHRD32mri8 2125333U, // SHRD32rrCL 369351U, // SHRD32rri8 4214405U, // SHRD64mrCL 210601586U, // SHRD64mri8 2125445U, // SHRD64rrCL 370290U, // SHRD64rri8 6366598U, // SHRX32rm 18376070U, // SHRX32rr 6891811U, // SHRX64rm 18376995U, // SHRX64rr 199615U, // SIDT16m 197888U, // SIDT32m 198819U, // SIDT64m 5333U, // SKINIT 109517U, // SLDT16m 11213U, // SLDT16r 9479U, // SLDT32r 10410U, // SLDT64r 8337U, // SLWPCB 8337U, // SLWPCB64 109580U, // SMSW16m 11276U, // SMSW16r 9548U, // SMSW32r 10473U, // SMSW64r 4508U, // STAC 4562U, // STC 4581U, // STD 4673U, // STGI 4682U, // STI 159119U, // STOSB 167857U, // STOSL 176114U, // STOSQ 184179U, // STOSW 11077U, // STR16r 9335U, // STR32r 10276U, // STR64r 109381U, // STRm 535005U, // SUB16i16 1067485U, // SUB16mi 1067485U, // SUB16mi8 1067485U, // SUB16mr 1599965U, // SUB16ri 1599965U, // SUB16ri8 1608157U, // SUB16rm 1599965U, // SUB16rr 2124253U, // SUB16rr_REV 2630231U, // SUB32i32 3162711U, // SUB32mi 3162711U, // SUB32mi8 3162711U, // SUB32mr 1598039U, // SUB32ri 1598039U, // SUB32ri8 1614423U, // SUB32rm 1598039U, // SUB32rr 2122327U, // SUB32rr_REV 3679746U, // SUB64i32 4212226U, // SUB64mi32 4212226U, // SUB64mi8 4212226U, // SUB64mr 1598978U, // SUB64ri32 1598978U, // SUB64ri8 1623554U, // SUB64rm 1598978U, // SUB64rr 2123266U, // SUB64rr_REV 4726897U, // SUB8i8 5259377U, // SUB8mi 5259377U, // SUB8mi8 5259377U, // SUB8mr 1597553U, // SUB8ri 1597553U, // SUB8ri8 57457U, // SUB8rm 1597553U, // SUB8rr 2121841U, // SUB8rr_REV 5160U, // SWAPGS 4759U, // SYSCALL 4911U, // SYSENTER 4787U, // SYSEXIT 4897U, // SYSEXIT64 4779U, // SYSRET 4889U, // SYSRET64 82569U, // T1MSKC32rm 39387785U, // T1MSKC32rr 91700U, // T1MSKC64rm 39388724U, // T1MSKC64rr 535537U, // TEST16i16 1068017U, // TEST16mi 1068017U, // TEST16mi_alt 1068017U, // TEST16mr 39390193U, // TEST16ri 39390193U, // TEST16ri_alt 39390193U, // TEST16rr 2630961U, // TEST32i32 3163441U, // TEST32mi 3163441U, // TEST32mi_alt 3163441U, // TEST32mr 39388465U, // TEST32ri 39388465U, // TEST32ri_alt 39388465U, // TEST32rr 3680462U, // TEST64i32 4212942U, // TEST64mi32 4212942U, // TEST64mi32_alt 4212942U, // TEST64mr 39389390U, // TEST64ri32 39389390U, // TEST64ri32_alt 39389390U, // TEST64rr 4727098U, // TEST8i8 5259578U, // TEST8mi 5259578U, // TEST8mi_alt 5259578U, // TEST8mr 39387450U, // TEST8ri 39387450U, // TEST8ri_alt 39387450U, // TEST8rr 8697U, // TPAUSE 101347U, // TZCNT16rm 39390179U, // TZCNT16rr 83235U, // TZCNT32rm 39388451U, // TZCNT32rr 92352U, // TZCNT64rm 39389376U, // TZCNT64rr 82835U, // TZMSK32rm 39388051U, // TZMSK32rr 91962U, // TZMSK64rm 39388986U, // TZMSK64rr 4339U, // UD0 4349U, // UD1 4366U, // UD2 10561U, // UMONITOR16 10561U, // UMONITOR32 10561U, // UMONITOR64 10637U, // UMWAIT 108883U, // VERRm 10579U, // VERRr 109339U, // VERWm 11035U, // VERWr 4752U, // VMCALL 125233U, // VMCLEARm 4549U, // VMFUNC 4659U, // VMLAUNCH 5298U, // VMLOAD32 5359U, // VMLOAD64 4744U, // VMMCALL 123258U, // VMPTRLDm 125368U, // VMPTRSTm 3162782U, // VMREAD32mr 39387806U, // VMREAD32rr 4212297U, // VMREAD64mr 39388745U, // VMREAD64rr 4606U, // VMRESUME 5322U, // VMRUN32 5383U, // VMRUN64 5310U, // VMSAVE32 5371U, // VMSAVE64 82727U, // VMWRITE32rm 39387943U, // VMWRITE32rr 91858U, // VMWRITE64rm 39388882U, // VMWRITE64rr 4634U, // VMXOFF 124313U, // VMXON 4590U, // WBINVD 4597U, // WBNOINVD 8966U, // WRFSBASE 9905U, // WRFSBASE64 8988U, // WRGSBASE 9927U, // WRGSBASE64 4926U, // WRMSR 5221U, // WRPKRUr 3162523U, // WRSSD 4212844U, // WRSSQ 3162530U, // WRUSSD 4212851U, // WRUSSQ 223939083U, // XADD16rm 379403U, // XADD16rr 240714407U, // XADD32rm 377511U, // XADD32rr 257492562U, // XADD64rm 378450U, // XADD64rr 274268313U, // XADD8rm 376985U, // XADD8rr 69465U, // XCHG16ar 223939190U, // XCHG16rm 9464438U, // XCHG16rr 69525U, // XCHG32ar 240714578U, // XCHG32rm 9462610U, // XCHG32rr 69590U, // XCHG64ar 257492733U, // XCHG64rm 9463549U, // XCHG64rr 274268335U, // XCHG8rm 9461935U, // XCHG8rr 4513U, // XCRYPTCBC 4477U, // XCRYPTCFB 4932U, // XCRYPTCTR 4467U, // XCRYPTECB 4487U, // XCRYPTOFB 5228U, // XGETBV 4497U, // XLAT 535341U, // XOR16i16 1067821U, // XOR16mi 1067821U, // XOR16mi8 1067821U, // XOR16mr 1600301U, // XOR16ri 1600301U, // XOR16ri8 1608493U, // XOR16rm 1600301U, // XOR16rr 2124589U, // XOR16rr_REV 2630750U, // XOR32i32 3163230U, // XOR32mi 3163230U, // XOR32mi8 3163230U, // XOR32mr 1598558U, // XOR32ri 1598558U, // XOR32ri8 1614942U, // XOR32rm 1598558U, // XOR32rr 2122846U, // XOR32rr_REV 3680267U, // XOR64i32 4212747U, // XOR64mi32 4212747U, // XOR64mi8 4212747U, // XOR64mr 1599499U, // XOR64ri32 1599499U, // XOR64ri8 1624075U, // XOR64rm 1599499U, // XOR64rr 2123787U, // XOR64rr_REV 4727036U, // XOR8i8 5259516U, // XOR8mi 5259516U, // XOR8mi8 5259516U, // XOR8mr 1597692U, // XOR8ri 1597692U, // XOR8ri8 57596U, // XOR8rm 1597692U, // XOR8rr 2121980U, // XOR8rr_REV 198987U, // XRSTOR 196628U, // XRSTOR64 199038U, // XRSTORS 196648U, // XRSTORS64 197137U, // XSAVE 196619U, // XSAVE64 196948U, // XSAVEC 196609U, // XSAVEC64 199074U, // XSAVEOPT 196659U, // XSAVEOPT64 199001U, // XSAVES 196638U, // XSAVES64 5235U, // XSETBV 4343U, // XSHA1 4396U, // XSHA256 4621U, // XSTORE }; unsigned int opcode = MCInst_getOpcode(MI); // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. uint32_t Bits = 0; Bits |= OpInfo0[opcode] << 0; SStream_concat0(O, AsmStrs+(Bits & 8191)-1); // Fragment 0 encoded into 6 bits for 47 unique commands. // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 13) & 63)); switch ((Bits >> 13) & 63) { default: // unreachable case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... printOperand(MI, 0, O); break; case 2: // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... printOperand(MI, 5, O); SStream_concat0(O, ", "); break; case 3: // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... printOperand(MI, 2, O); SStream_concat0(O, ", "); break; case 4: // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... printi16mem(MI, 2, O); SStream_concat0(O, ", "); break; case 5: // ADC32rm, ADCX32rm, ADD32rm, ADOX32rm, AND32rm, ANDN32rm, CMOVA32rm, CM... printi32mem(MI, 2, O); SStream_concat0(O, ", "); break; case 6: // ADC64rm, ADCX64rm, ADD64rm, ADOX64rm, AND64rm, ANDN64rm, CMOVA64rm, CM... printi64mem(MI, 2, O); SStream_concat0(O, ", "); break; case 7: // ADC8rm, ADD8rm, AND8rm, OR8rm, SBB8rm, SUB8rm, XOR8rm printi8mem(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; case 8: // ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCIC32rr, BLC... printOperand(MI, 1, O); break; case 9: // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... printOperand(MI, 6, O); SStream_concat0(O, ", "); break; case 10: // BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, BLCS32rm, BLSFILL32rm, B... printi32mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 11: // BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, BLCS64rm, BLSFILL64rm, B... printi64mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 12: // BSF16rm, BSR16rm, CMP16rm, LAR16rm, LAR32rm, LAR64rm, LSL16rm, LSL32rm... printi16mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 13: // CALL16m, CALL16m_NT, DEC16m, DIV16m, IDIV16m, IMUL16m, INC16m, JMP16m,... printi16mem(MI, 0, O); return; break; case 14: // CALL32m, CALL32m_NT, CLRSSBSY, DEC32m, DIV32m, IDIV32m, IMUL32m, INC32... printi32mem(MI, 0, O); return; break; case 15: // CALL64m, CALL64m_NT, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, IMUL64m, INC6... printi64mem(MI, 0, O); return; break; case 16: // CALL64pcrel32, CALLpcrel16, CALLpcrel32, JAE_1, JAE_2, JAE_4, JA_1, JA... printPCRelImm(MI, 0, O); return; break; case 17: // CLDEMOTE, CLFLUSHOPT, CLWB, DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, INVLP... printi8mem(MI, 0, O); return; break; case 18: // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX32rm8_NOREX... printi8mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 19: // CMPSB, INSB, SCASB, STOSB printDstIdx8(MI, 0, O); break; case 20: // CMPSL, INSL, SCASL, STOSL printDstIdx32(MI, 0, O); break; case 21: // CMPSQ, SCASQ, STOSQ printDstIdx64(MI, 0, O); break; case 22: // CMPSW, INSW, SCASW, STOSW printDstIdx16(MI, 0, O); break; case 23: // CMPXCHG16B printi128mem(MI, 0, O); return; break; case 24: // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, LGD... printopaquemem(MI, 0, O); return; break; case 25: // IN16ri, IN32ri, IN8ri, INT, OUT16ir, OUT32ir, OUT8ir printU8Imm(MI, 0, O); break; case 26: // INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPID32, INVVPID64 printi128mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 27: // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... printopaquemem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 28: // LEA16r, LEA32r, LEA64_32r, LEA64r printanymem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 29: // LODSB, OUTSB printSrcIdx8(MI, 0, O); break; case 30: // LODSL, OUTSL printSrcIdx32(MI, 0, O); break; case 31: // LODSQ printSrcIdx64(MI, 0, O); SStream_concat0(O, ", %rax"); op_addReg(MI, X86_REG_RAX); return; break; case 32: // LODSW, OUTSW printSrcIdx16(MI, 0, O); break; case 33: // MOV16ao16, MOV16ao32, MOV16ao64, MOV16o16a, MOV16o32a, MOV16o64a printMemOffs16(MI, 0, O); break; case 34: // MOV32ao16, MOV32ao32, MOV32ao64, MOV32o16a, MOV32o32a, MOV32o64a printMemOffs32(MI, 0, O); break; case 35: // MOV64ao32, MOV64ao64, MOV64o32a, MOV64o64a printMemOffs64(MI, 0, O); break; case 36: // MOV8ao16, MOV8ao32, MOV8ao64, MOV8o16a, MOV8o32a, MOV8o64a printMemOffs8(MI, 0, O); break; case 37: // MOVDIR64B16, MOVDIR64B32, MOVDIR64B64 printi512mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 38: // MOVSB printSrcIdx8(MI, 1, O); SStream_concat0(O, ", "); printDstIdx8(MI, 0, O); return; break; case 39: // MOVSL printSrcIdx32(MI, 1, O); SStream_concat0(O, ", "); printDstIdx32(MI, 0, O); return; break; case 40: // MOVSQ printSrcIdx64(MI, 1, O); SStream_concat0(O, ", "); printDstIdx64(MI, 0, O); return; break; case 41: // MOVSW printSrcIdx16(MI, 1, O); SStream_concat0(O, ", "); printDstIdx16(MI, 0, O); return; break; case 42: // RCL16mi, RCL32mi, RCL64mi, RCL8mi, RCR16mi, RCR32mi, RCR64mi, RCR8mi, ... printU8Imm(MI, 5, O); SStream_concat0(O, ", "); break; case 43: // RCL16ri, RCL32ri, RCL64ri, RCL8ri, RCR16ri, RCR32ri, RCR64ri, RCR8ri, ... printU8Imm(MI, 2, O); SStream_concat0(O, ", "); break; case 44: // RORX32mi, RORX64mi, SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SH... printU8Imm(MI, 6, O); SStream_concat0(O, ", "); break; case 45: // SHLD16rri8, SHLD32rri8, SHLD64rri8, SHRD16rri8, SHRD32rri8, SHRD64rri8 printU8Imm(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 46: // XADD16rr, XADD32rr, XADD64rr, XADD8rr printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 2, O); return; break; } // Fragment 1 encoded into 5 bits for 19 unique commands. // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 31)); switch ((Bits >> 19) & 31) { default: // unreachable case 0: // AAD8i8, AAM8i8, BSWAP16r_BAD, BSWAP32r, BSWAP64r, CALL16r, CALL16r_NT,... return; break; case 1: // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, LODSW, MOV16ao16, MOV1... SStream_concat0(O, ", %ax"); op_addReg(MI, X86_REG_AX); return; break; case 2: // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... printi16mem(MI, 0, O); return; break; case 3: // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... printOperand(MI, 1, O); break; case 4: // ADC16rr_REV, ADC32rr_REV, ADC64rr_REV, ADC8rr_REV, ADCX32rm, ADCX32rr,... printOperand(MI, 0, O); return; break; case 5: // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, LODSL, MOV32ao16, MOV3... SStream_concat0(O, ", %eax"); op_addReg(MI, X86_REG_EAX); return; break; case 6: // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... printi32mem(MI, 0, O); return; break; case 7: // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64ao32, MOV64ao64, OR64i32,... SStream_concat0(O, ", %rax"); op_addReg(MI, X86_REG_RAX); return; break; case 8: // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... printi64mem(MI, 0, O); return; break; case 9: // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, LODSB, MOV8ao16, MOV8ao32, MOV8... SStream_concat0(O, ", %al"); op_addReg(MI, X86_REG_AL); return; break; case 10: // ADC8mi, ADC8mi8, ADC8mr, ADD8mi, ADD8mi8, ADD8mr, AND8mi, AND8mi8, AND... printi8mem(MI, 0, O); return; break; case 11: // ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCIC32rr, BLC... SStream_concat0(O, ", "); break; case 12: // BEXTR32rm, BEXTRI32mi, BZHI32rm, IMUL32rmi, IMUL32rmi8, LWPINS32rmi, L... printi32mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 13: // BEXTR64rm, BEXTRI64mi, BZHI64rm, IMUL64rmi32, IMUL64rmi8, RORX64mi, SA... printi64mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 14: // FARJMP16i, FARJMP32i SStream_concat0(O, ":"); printOperand(MI, 0, O); return; break; case 15: // IMUL16rmi, IMUL16rmi8 printi16mem(MI, 1, O); SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 16: // OUTSB, OUTSL, OUTSW SStream_concat0(O, ", %dx"); op_addReg(MI, X86_REG_DX); return; break; case 17: // SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SHRD32mri8, SHRD64mri8 printOperand(MI, 5, O); SStream_concat0(O, ", "); break; case 18: // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr printOperand(MI, 3, O); return; break; } // Fragment 2 encoded into 5 bits for 17 unique commands. // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 31)); switch ((Bits >> 24) & 31) { default: // unreachable case 0: // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... return; break; case 1: // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32... SStream_concat0(O, ", "); printOperand(MI, 0, O); return; break; case 2: // ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI64rr, BLCIC32rr, BLC... printOperand(MI, 0, O); return; break; case 3: // BOUNDS16rm printi32mem(MI, 1, O); return; break; case 4: // BOUNDS32rm printi64mem(MI, 1, O); return; break; case 5: // CMPSB printSrcIdx8(MI, 1, O); return; break; case 6: // CMPSL printSrcIdx32(MI, 1, O); return; break; case 7: // CMPSQ printSrcIdx64(MI, 1, O); return; break; case 8: // CMPSW printSrcIdx16(MI, 1, O); return; break; case 9: // ENTER, NOOP19rr printOperand(MI, 1, O); return; break; case 10: // SHLD16mri8, SHRD16mri8 printi16mem(MI, 0, O); return; break; case 11: // SHLD32mri8, SHRD32mri8 printi32mem(MI, 0, O); return; break; case 12: // SHLD64mri8, SHRD64mri8 printi64mem(MI, 0, O); return; break; case 13: // XADD16rm, XCHG16rm printi16mem(MI, 2, O); return; break; case 14: // XADD32rm, XCHG32rm printi32mem(MI, 2, O); return; break; case 15: // XADD64rm, XCHG64rm printi64mem(MI, 2, O); return; break; case 16: // XADD8rm, XCHG8rm printi8mem(MI, 2, O); return; break; } } capstone-sys-0.15.0/capstone/arch/X86/X86GenDisassemblerTables.inc000064400000000000000000102000130072674642500227050ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * X86 Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ static const struct OperandSpecifier x86OperandSets[][6] = { { /* 0 */ { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 1 */ { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 2 */ { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 3 */ { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 4 */ { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 5 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 6 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 7 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 8 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 9 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 10 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 11 */ { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 12 */ { ENCODING_RM, TYPE_M }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 13 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 14 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 15 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 16 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 17 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 18 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 19 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 20 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 21 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 22 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 23 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 24 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 25 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 26 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 27 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 28 */ { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 29 */ { ENCODING_FP, TYPE_ST }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 30 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 31 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 32 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 33 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 34 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 35 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 36 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 37 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 38 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 39 */ { ENCODING_RM, TYPE_R16 }, { ENCODING_REG, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 40 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 41 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 42 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 43 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 44 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 45 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 46 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 47 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 48 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 49 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 50 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 51 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 52 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 53 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 54 */ { ENCODING_REG, TYPE_BNDR }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 55 */ { ENCODING_REG, TYPE_BNDR }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 56 */ { ENCODING_REG, TYPE_BNDR }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 57 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_BNDR }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 58 */ { ENCODING_REG, TYPE_BNDR }, { ENCODING_RM, TYPE_BNDR }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 59 */ { ENCODING_RM, TYPE_BNDR }, { ENCODING_REG, TYPE_BNDR }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 60 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 61 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 62 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 63 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 64 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_Rv, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 65 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RO, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 66 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 67 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 68 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 69 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 70 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 71 */ { ENCODING_ID, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 72 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 73 */ { ENCODING_IW, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 74 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 75 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 76 */ { ENCODING_RM, TYPE_R8 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 77 */ { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 78 */ { ENCODING_RM, TYPE_R8 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 79 */ { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 80 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM3 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 81 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_IMM3 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 82 */ { ENCODING_DI, TYPE_DSTIDX }, { ENCODING_SI, TYPE_SRCIDX }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 83 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 84 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 85 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 86 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 87 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 88 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 89 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 90 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 91 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 92 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 93 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 94 */ { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 95 */ { ENCODING_IW, TYPE_IMM }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 96 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 97 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 98 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 99 */ { ENCODING_Iv, TYPE_IMM }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 100 */ { ENCODING_Iv, TYPE_IMM }, { ENCODING_IW, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 101 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 102 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 103 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 104 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 105 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 106 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 107 */ { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 108 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 109 */ { ENCODING_DI, TYPE_DSTIDX }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 110 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 111 */ { ENCODING_IB, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 112 */ { ENCODING_Iv, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 113 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_VK }, { ENCODING_RM, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 114 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 115 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 116 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 117 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 118 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 119 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 120 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 121 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM, TYPE_VK }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 122 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 123 */ { ENCODING_RM, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 124 */ { ENCODING_SI, TYPE_SRCIDX }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 125 */ { ENCODING_IW, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 126 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 127 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 128 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 129 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 130 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 131 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 132 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 133 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 134 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 135 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 136 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 137 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 138 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 139 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 140 */ { ENCODING_RM, TYPE_MM64 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 141 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 142 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 143 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 144 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 145 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 146 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 147 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 148 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 149 */ { ENCODING_REG, TYPE_MM64 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 150 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_MM64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 151 */ { ENCODING_Ia, TYPE_MOFFS }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 152 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 153 */ { ENCODING_Rv, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 154 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 155 */ { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 156 */ { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 157 */ { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 158 */ { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 159 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 160 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 161 */ { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 162 */ { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 163 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 164 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 165 */ { ENCODING_RO, TYPE_R64 }, { ENCODING_IO, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 166 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 167 */ { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 168 */ { ENCODING_RB, TYPE_R8 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 169 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 170 */ { ENCODING_RM, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 171 */ { ENCODING_REG, TYPE_R16 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 172 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 173 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 174 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 175 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 176 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 177 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 178 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 179 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 180 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 181 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 182 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_R32 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 183 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 184 */ { ENCODING_Rv, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 185 */ { ENCODING_RO, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 186 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 187 */ { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 188 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 189 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 190 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 191 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 192 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 193 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 194 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 195 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 196 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_Rv }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 197 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 198 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 199 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 200 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 201 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 202 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 203 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 204 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 205 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 206 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 207 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 208 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 209 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 210 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 211 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 212 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 213 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 214 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 215 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 216 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 217 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 218 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 219 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 220 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 221 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 222 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 223 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 224 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 225 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 226 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 227 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 228 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 229 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 230 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 231 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, }, { /* 232 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 233 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 234 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 235 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 236 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 237 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 238 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 239 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 240 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 241 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 242 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 243 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 244 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 245 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 246 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 247 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, }, { /* 248 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 249 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 250 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 251 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 252 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 253 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, }, { /* 254 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 255 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 256 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 257 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 258 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 259 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, }, { /* 260 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 261 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 262 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 263 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 264 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 265 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 266 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 267 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 268 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 269 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 270 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 271 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 272 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 273 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 274 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 275 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 276 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 277 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 278 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 279 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 280 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 281 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 282 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 283 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 284 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 285 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 286 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 287 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 288 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 289 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 290 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 291 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 292 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 293 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 294 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 295 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 296 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 297 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 298 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 299 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 300 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 301 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 302 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 303 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 304 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 305 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 306 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 307 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 308 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 309 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 310 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 311 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 312 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 313 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 314 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 315 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 316 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 317 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 318 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 319 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 320 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 321 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 322 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 323 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 324 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 325 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 326 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 327 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 328 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 329 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 330 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 331 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 332 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 333 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 334 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 335 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 336 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 337 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 338 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 339 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 340 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 341 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 342 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 343 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 344 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 345 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 346 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 347 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 348 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 349 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 350 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 351 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 352 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 353 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 354 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 355 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 356 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 357 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 358 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 359 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 360 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 361 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 362 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 363 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 364 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 365 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 366 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 367 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 368 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 369 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 370 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 371 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 372 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 373 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 374 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 375 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 376 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_IMM5 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 377 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 378 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 379 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 380 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 381 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 382 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 383 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 384 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 385 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 386 */ { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 387 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 388 */ { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 389 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 390 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 391 */ { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 392 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 393 */ { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 394 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 395 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 396 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 397 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 398 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 399 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 400 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 401 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 402 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 403 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 404 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 405 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 406 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 407 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 408 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 409 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 410 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 411 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 412 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 413 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 414 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 415 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 416 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 417 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 418 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 419 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 420 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 421 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 422 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 423 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 424 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 425 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 426 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 427 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 428 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 429 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 430 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 431 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 432 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 433 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 434 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 435 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 436 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 437 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 438 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 439 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 440 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 441 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 442 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 443 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 444 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 445 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 446 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 447 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 448 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 449 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 450 */ { ENCODING_RM, TYPE_XMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 451 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 452 */ { ENCODING_RM_CD8, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 453 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 454 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 455 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 456 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 457 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 458 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 459 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 460 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 461 */ { ENCODING_RM_CD32, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 462 */ { ENCODING_RM_CD32, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 463 */ { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 464 */ { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 465 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 466 */ { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 467 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 468 */ { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 469 */ { ENCODING_RM, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 470 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 471 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 472 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_YMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 473 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 474 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 475 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 476 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 477 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 478 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 479 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 480 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_R32 }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 481 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 482 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 483 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_R64 }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 484 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 485 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 486 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 487 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 488 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 489 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 490 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 491 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 492 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 493 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 494 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 495 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 496 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 497 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 498 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 499 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 500 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 501 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 502 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 503 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 504 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 505 */ { ENCODING_RM_CD4, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 506 */ { ENCODING_RM_CD16, TYPE_R32 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 507 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 508 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 509 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 510 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 511 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 512 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 513 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 514 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 515 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 516 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 517 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 518 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 519 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 520 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 521 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 522 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 523 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 524 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 525 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 526 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 527 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 528 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 529 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 530 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 531 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 532 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 533 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 534 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 535 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 536 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 537 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 538 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 539 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 540 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 541 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 542 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 543 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 544 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 545 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 546 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 547 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IRC, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 548 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_IB, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 549 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_IB, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 550 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_IB, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 551 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_IB, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 552 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 553 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 554 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 555 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 556 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 557 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 558 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 559 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 560 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 561 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 562 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 563 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 564 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 565 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 566 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 567 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 568 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 569 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 570 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 571 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 572 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP4 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VSIB, TYPE_MVSIBX }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 573 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD8, TYPE_MVSIBX }, { ENCODING_NONE, TYPE_NONE }, }, { /* 574 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD8, TYPE_MVSIBX }, { ENCODING_NONE, TYPE_NONE }, }, { /* 575 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD8, TYPE_MVSIBY }, { ENCODING_NONE, TYPE_NONE }, }, { /* 576 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP4 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VSIB, TYPE_MVSIBX }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 577 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP4 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_VSIB, TYPE_MVSIBY }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 578 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBX }, { ENCODING_NONE, TYPE_NONE }, }, { /* 579 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBY }, { ENCODING_NONE, TYPE_NONE }, }, { /* 580 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, { ENCODING_NONE, TYPE_NONE }, }, { /* 581 */ { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBY }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 582 */ { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 583 */ { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD8, TYPE_MVSIBZ }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 584 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD8, TYPE_MVSIBY }, { ENCODING_NONE, TYPE_NONE }, }, { /* 585 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD8, TYPE_MVSIBZ }, { ENCODING_NONE, TYPE_NONE }, }, { /* 586 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP4 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_VSIB, TYPE_MVSIBY }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 587 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBY }, { ENCODING_NONE, TYPE_NONE }, }, { /* 588 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, { ENCODING_NONE, TYPE_NONE }, }, { /* 589 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 590 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 591 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 592 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 593 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 594 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 595 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 596 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 597 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 598 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 599 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 600 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 601 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 602 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 603 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 604 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 605 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 606 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 607 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 608 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 609 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 610 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 611 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 612 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 613 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 614 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 615 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 616 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 617 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 618 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 619 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 620 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 621 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 622 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 623 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 624 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 625 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 626 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 627 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 628 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 629 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 630 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 631 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 632 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 633 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 634 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 635 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 636 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 637 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 638 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 639 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 640 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 641 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 642 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 643 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 644 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 645 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 646 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 647 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 648 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 649 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 650 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 651 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 652 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 653 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 654 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 655 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 656 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 657 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 658 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 659 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, }, { /* 660 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 661 */ { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 662 */ { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 663 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 664 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 665 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 666 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 667 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 668 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 669 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 670 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 671 */ { ENCODING_RM, TYPE_YMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 672 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 673 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 674 */ { ENCODING_RM_CD32, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 675 */ { ENCODING_RM_CD32, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 676 */ { ENCODING_RM_CD64, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 677 */ { ENCODING_RM_CD64, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 678 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 679 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 680 */ { ENCODING_RM_CD16, TYPE_R32 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 681 */ { ENCODING_RM_CD16, TYPE_R64 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 682 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 683 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 684 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 685 */ { ENCODING_RM, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 686 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 687 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 688 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 689 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 690 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 691 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 692 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 693 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 694 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 695 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 696 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 697 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 698 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 699 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 700 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 701 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 702 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 703 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 704 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 705 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_VK }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 706 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 707 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 708 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 709 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 710 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 711 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 712 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 713 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 714 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 715 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 716 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 717 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 718 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 719 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 720 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 721 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 722 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 723 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 724 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 725 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 726 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 727 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 728 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 729 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 730 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 731 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 732 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 733 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 734 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 735 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 736 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 737 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 738 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 739 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 740 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 741 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 742 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 743 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 744 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 745 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 746 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 747 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 748 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 749 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 750 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 751 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 752 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 753 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 754 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 755 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 756 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 757 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 758 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 759 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 760 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 761 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 762 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 763 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 764 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 765 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 766 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 767 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 768 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 769 */ { ENCODING_REG, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 770 */ { ENCODING_REG, TYPE_VK }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_AVX512ICC }, { ENCODING_NONE, TYPE_NONE }, }, { /* 771 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM3 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 772 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_IMM3 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 773 */ { ENCODING_RM, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 774 */ { ENCODING_RM, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 775 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 776 */ { ENCODING_RM, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 777 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 778 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 779 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 780 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 781 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 782 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 783 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 784 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_IB, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 785 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 786 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_IB, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 787 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 788 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_IB, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 789 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 790 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_IB, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 791 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 792 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 793 */ { ENCODING_RM_CD16, TYPE_R64 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 794 */ { ENCODING_RM_CD2, TYPE_M }, { ENCODING_REG, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 795 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 796 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_R32 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 797 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_R32 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 798 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 799 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 800 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD2, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 801 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 802 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 803 */ { ENCODING_REG, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 804 */ { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 805 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 806 */ { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 807 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 808 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 809 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 810 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 811 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 812 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 813 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 814 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 815 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 816 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 817 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 818 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 819 */ { ENCODING_RM_CD16, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 820 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 821 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 822 */ { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 823 */ { ENCODING_RM_CD32, TYPE_M }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 824 */ { ENCODING_RM_CD32, TYPE_M }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 825 */ { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 826 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 827 */ { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 828 */ { ENCODING_RM_CD2, TYPE_XMM }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 829 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD2, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 830 */ { ENCODING_RM_CD2, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 831 */ { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 832 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 833 */ { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 834 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 835 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 836 */ { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 837 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 838 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 839 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 840 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 841 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 842 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 843 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 844 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 845 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM_CD2, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 846 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 847 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD2, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 848 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 849 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 850 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 851 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 852 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 853 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 854 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 855 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 856 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 857 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 858 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 859 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 860 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 861 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 862 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 863 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 864 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 865 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 866 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 867 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 868 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 869 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 870 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 871 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD32, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 872 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 873 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 874 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD4, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 875 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 876 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 877 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 878 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 879 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 880 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD64, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 881 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 882 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 883 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 884 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 885 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 886 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 887 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 888 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 889 */ { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_RM_CD8, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 890 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 891 */ { ENCODING_REG, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_VVVV, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 892 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD4, TYPE_MVSIBX }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 893 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD4, TYPE_MVSIBY }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 894 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 895 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD8, TYPE_MVSIBX }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 896 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD8, TYPE_MVSIBX }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 897 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD8, TYPE_MVSIBY }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 898 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD4, TYPE_MVSIBY }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 899 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD4, TYPE_MVSIBZ }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 900 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD8, TYPE_MVSIBY }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_YMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 901 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_VSIB_CD8, TYPE_MVSIBZ }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 902 */ { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_YMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 903 */ { ENCODING_VVVV, TYPE_XMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 904 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 905 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 906 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, }, { /* 907 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 908 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 909 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 910 */ { ENCODING_REG, TYPE_YMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_YMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 911 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 912 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 913 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 914 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, }, { /* 915 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD16, TYPE_XMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 916 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 917 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD8, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 918 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 919 */ { ENCODING_REG, TYPE_ZMM }, { ENCODING_WRITEMASK, TYPE_VK }, { ENCODING_VVVV, TYPE_ZMM }, { ENCODING_RM_CD4, TYPE_ZMM }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, }, { /* 920 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 921 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 922 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 923 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 924 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 925 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, }; static const struct InstructionSpecifier x86DisassemblerInstrSpecifiers[15285] = { { /* 0 */ 0, /* */ }, { /* 1 */ 0, /* */ }, { /* 2 */ 0, /* */ }, { /* 3 */ 0, /* */ }, { /* 4 */ 0, /* */ }, { /* 5 */ 0, /* */ }, { /* 6 */ 0, /* */ }, { /* 7 */ 0, /* */ }, { /* 8 */ 0, /* */ }, { /* 9 */ 0, /* */ }, { /* 10 */ 0, /* */ }, { /* 11 */ 0, /* */ }, { /* 12 */ 0, /* */ }, { /* 13 */ 0, /* */ }, { /* 14 */ 0, /* */ }, { /* 15 */ 0, /* */ }, { /* 16 */ 0, /* */ }, { /* 17 */ 0, /* */ }, { /* 18 */ 0, /* */ }, { /* 19 */ 0, /* */ }, { /* 20 */ 0, /* */ }, { /* 21 */ 0, /* */ }, { /* 22 */ 0, /* */ }, { /* 23 */ 0, /* */ }, { /* 24 */ 0, /* */ }, { /* 25 */ 0, /* */ }, { /* 26 */ 0, /* */ }, { /* 27 */ 0, /* */ }, { /* 28 */ 0, /* */ }, { /* 29 */ 0, /* */ }, { /* 30 */ 0, /* */ }, { /* 31 */ 0, /* */ }, { /* 32 */ 0, /* */ }, { /* 33 */ 0, /* */ }, { /* 34 */ 0, /* */ }, { /* 35 */ 0, /* */ }, { /* 36 */ 0, /* */ }, { /* 37 */ 0, /* */ }, { /* 38 */ 0, /* */ }, { /* 39 */ 0, /* */ }, { /* 40 */ 0, /* */ }, { /* 41 */ 0, /* */ }, { /* 42 */ 0, /* */ }, { /* 43 */ 0, /* */ }, { /* 44 */ 0, /* */ }, { /* 45 */ 0, /* */ }, { /* 46 */ 0, /* */ }, { /* 47 */ 0, /* */ }, { /* 48 */ 0, /* */ }, { /* 49 */ 0, /* */ }, { /* 50 */ 0, /* */ }, { /* 51 */ 0, /* */ }, { /* 52 */ 0, /* */ }, { /* 53 */ 0, /* */ }, { /* 54 */ 0, /* */ }, { /* 55 */ 0, /* */ }, { /* 56 */ 0, /* */ }, { /* 57 */ 0, /* */ }, { /* 58 */ 0, /* */ }, { /* 59 */ 0, /* */ }, { /* 60 */ 0, /* */ }, { /* 61 */ 0, /* */ }, { /* 62 */ 0, /* */ }, { /* 63 */ 0, /* */ }, { /* 64 */ 0, /* */ }, { /* 65 */ 0, /* */ }, { /* 66 */ 0, /* */ }, { /* 67 */ 0, /* */ }, { /* 68 */ 0, /* */ }, { /* 69 */ 0, /* */ }, { /* 70 */ 0, /* */ }, { /* 71 */ 0, /* */ }, { /* 72 */ 0, /* */ }, { /* 73 */ 0, /* */ }, { /* 74 */ 0, /* */ }, { /* 75 */ 0, /* */ }, { /* 76 */ 0, /* */ }, { /* 77 */ 0, /* */ }, { /* 78 */ 0, /* */ }, { /* 79 */ 0, /* */ }, { /* 80 */ 0, /* */ }, { /* 81 */ 0, /* */ }, { /* 82 */ 0, /* */ }, { /* 83 */ 0, /* */ }, { /* 84 */ 0, /* */ }, { /* 85 */ 0, /* */ }, { /* 86 */ 0, /* */ }, { /* 87 */ 0, /* */ }, { /* 88 */ 0, /* */ }, { /* 89 */ 0, /* */ }, { /* 90 */ 0, /* */ }, { /* 91 */ 0, /* */ }, { /* 92 */ 0, /* */ }, { /* 93 */ 0, /* */ }, { /* 94 */ 0, /* */ }, { /* 95 */ 0, /* */ }, { /* 96 */ 0, /* */ }, { /* 97 */ 0, /* */ }, { /* 98 */ 0, /* */ }, { /* 99 */ 0, /* */ }, { /* 100 */ 0, /* */ }, { /* 101 */ 0, /* */ }, { /* 102 */ 0, /* */ }, { /* 103 */ 0, /* */ }, { /* 104 */ 0, /* */ }, { /* 105 */ 0, /* */ }, { /* 106 */ 0, /* */ }, { /* 107 */ 0, /* */ }, { /* 108 */ 0, /* */ }, { /* 109 */ 0, /* */ }, { /* 110 */ 0, /* */ }, { /* 111 */ 0, /* */ }, { /* 112 */ 0, /* */ }, { /* 113 */ 0, /* */ }, { /* 114 */ 0, /* */ }, { /* 115 */ 0, /* */ }, { /* 116 */ 0, /* */ }, { /* 117 */ 0, /* */ }, { /* 118 */ 0, /* */ }, { /* 119 */ 0, /* */ }, { /* 120 */ 0, /* */ }, { /* 121 */ 0, /* */ }, { /* 122 */ 0, /* */ }, { /* 123 */ 0, /* */ }, { /* 124 */ 0, /* */ }, { /* 125 */ 0, /* */ }, { /* 126 */ 0, /* */ }, { /* 127 */ 0, /* */ }, { /* 128 */ 0, /* */ }, { /* 129 */ 0, /* */ }, { /* 130 */ 0, /* */ }, { /* 131 */ 0, /* */ }, { /* 132 */ 0, /* */ }, { /* 133 */ 0, /* */ }, { /* 134 */ 0, /* */ }, { /* 135 */ 0, /* */ }, { /* 136 */ 0, /* */ }, { /* 137 */ 0, /* */ }, { /* 138 */ 0, /* */ }, { /* 139 */ 0, /* */ }, { /* 140 */ 0, /* */ }, { /* 141 */ 0, /* */ }, { /* 142 */ 0, /* */ }, { /* 143 */ 0, /* */ }, { /* 144 */ 0, /* */ }, { /* 145 */ 0, /* */ }, { /* 146 */ 0, /* AAA */ }, { /* 147 */ 1, /* AAD8i8 */ }, { /* 148 */ 1, /* AAM8i8 */ }, { /* 149 */ 0, /* AAS */ }, { /* 150 */ 0, /* ABS_F */ }, { /* 151 */ 0, /* */ }, { /* 152 */ 0, /* */ }, { /* 153 */ 0, /* */ }, { /* 154 */ 2, /* ADC16i16 */ }, { /* 155 */ 3, /* ADC16mi */ }, { /* 156 */ 4, /* ADC16mi8 */ }, { /* 157 */ 5, /* ADC16mr */ }, { /* 158 */ 6, /* ADC16ri */ }, { /* 159 */ 7, /* ADC16ri8 */ }, { /* 160 */ 8, /* ADC16rm */ }, { /* 161 */ 9, /* ADC16rr */ }, { /* 162 */ 10, /* ADC16rr_REV */ }, { /* 163 */ 2, /* ADC32i32 */ }, { /* 164 */ 3, /* ADC32mi */ }, { /* 165 */ 4, /* ADC32mi8 */ }, { /* 166 */ 5, /* ADC32mr */ }, { /* 167 */ 6, /* ADC32ri */ }, { /* 168 */ 7, /* ADC32ri8 */ }, { /* 169 */ 8, /* ADC32rm */ }, { /* 170 */ 9, /* ADC32rr */ }, { /* 171 */ 10, /* ADC32rr_REV */ }, { /* 172 */ 11, /* ADC64i32 */ }, { /* 173 */ 12, /* ADC64mi32 */ }, { /* 174 */ 4, /* ADC64mi8 */ }, { /* 175 */ 13, /* ADC64mr */ }, { /* 176 */ 14, /* ADC64ri32 */ }, { /* 177 */ 15, /* ADC64ri8 */ }, { /* 178 */ 16, /* ADC64rm */ }, { /* 179 */ 17, /* ADC64rr */ }, { /* 180 */ 18, /* ADC64rr_REV */ }, { /* 181 */ 1, /* ADC8i8 */ }, { /* 182 */ 4, /* ADC8mi */ }, { /* 183 */ 4, /* ADC8mi8 */ }, { /* 184 */ 19, /* ADC8mr */ }, { /* 185 */ 20, /* ADC8ri */ }, { /* 186 */ 20, /* ADC8ri8 */ }, { /* 187 */ 21, /* ADC8rm */ }, { /* 188 */ 22, /* ADC8rr */ }, { /* 189 */ 23, /* ADC8rr_REV */ }, { /* 190 */ 24, /* ADCX32rm */ }, { /* 191 */ 25, /* ADCX32rr */ }, { /* 192 */ 16, /* ADCX64rm */ }, { /* 193 */ 18, /* ADCX64rr */ }, { /* 194 */ 2, /* ADD16i16 */ }, { /* 195 */ 3, /* ADD16mi */ }, { /* 196 */ 4, /* ADD16mi8 */ }, { /* 197 */ 5, /* ADD16mr */ }, { /* 198 */ 6, /* ADD16ri */ }, { /* 199 */ 7, /* ADD16ri8 */ }, { /* 200 */ 8, /* ADD16rm */ }, { /* 201 */ 9, /* ADD16rr */ }, { /* 202 */ 10, /* ADD16rr_REV */ }, { /* 203 */ 2, /* ADD32i32 */ }, { /* 204 */ 3, /* ADD32mi */ }, { /* 205 */ 4, /* ADD32mi8 */ }, { /* 206 */ 5, /* ADD32mr */ }, { /* 207 */ 6, /* ADD32ri */ }, { /* 208 */ 7, /* ADD32ri8 */ }, { /* 209 */ 8, /* ADD32rm */ }, { /* 210 */ 9, /* ADD32rr */ }, { /* 211 */ 10, /* ADD32rr_REV */ }, { /* 212 */ 11, /* ADD64i32 */ }, { /* 213 */ 12, /* ADD64mi32 */ }, { /* 214 */ 4, /* ADD64mi8 */ }, { /* 215 */ 13, /* ADD64mr */ }, { /* 216 */ 14, /* ADD64ri32 */ }, { /* 217 */ 15, /* ADD64ri8 */ }, { /* 218 */ 16, /* ADD64rm */ }, { /* 219 */ 17, /* ADD64rr */ }, { /* 220 */ 18, /* ADD64rr_REV */ }, { /* 221 */ 1, /* ADD8i8 */ }, { /* 222 */ 4, /* ADD8mi */ }, { /* 223 */ 4, /* ADD8mi8 */ }, { /* 224 */ 19, /* ADD8mr */ }, { /* 225 */ 20, /* ADD8ri */ }, { /* 226 */ 20, /* ADD8ri8 */ }, { /* 227 */ 21, /* ADD8rm */ }, { /* 228 */ 22, /* ADD8rr */ }, { /* 229 */ 23, /* ADD8rr_REV */ }, { /* 230 */ 26, /* ADDPDrm */ }, { /* 231 */ 27, /* ADDPDrr */ }, { /* 232 */ 26, /* ADDPSrm */ }, { /* 233 */ 27, /* ADDPSrr */ }, { /* 234 */ 26, /* ADDSDrm */ }, { /* 235 */ 0, /* */ }, { /* 236 */ 27, /* ADDSDrr */ }, { /* 237 */ 0, /* */ }, { /* 238 */ 26, /* ADDSSrm */ }, { /* 239 */ 0, /* */ }, { /* 240 */ 27, /* ADDSSrr */ }, { /* 241 */ 0, /* */ }, { /* 242 */ 26, /* ADDSUBPDrm */ }, { /* 243 */ 27, /* ADDSUBPDrr */ }, { /* 244 */ 26, /* ADDSUBPSrm */ }, { /* 245 */ 27, /* ADDSUBPSrr */ }, { /* 246 */ 28, /* ADD_F32m */ }, { /* 247 */ 28, /* ADD_F64m */ }, { /* 248 */ 28, /* ADD_FI16m */ }, { /* 249 */ 28, /* ADD_FI32m */ }, { /* 250 */ 29, /* ADD_FPrST0 */ }, { /* 251 */ 29, /* ADD_FST0r */ }, { /* 252 */ 0, /* */ }, { /* 253 */ 0, /* */ }, { /* 254 */ 0, /* */ }, { /* 255 */ 0, /* */ }, { /* 256 */ 0, /* */ }, { /* 257 */ 0, /* */ }, { /* 258 */ 0, /* */ }, { /* 259 */ 0, /* */ }, { /* 260 */ 0, /* */ }, { /* 261 */ 0, /* */ }, { /* 262 */ 0, /* */ }, { /* 263 */ 0, /* */ }, { /* 264 */ 0, /* */ }, { /* 265 */ 0, /* */ }, { /* 266 */ 29, /* ADD_FrST0 */ }, { /* 267 */ 24, /* ADOX32rm */ }, { /* 268 */ 25, /* ADOX32rr */ }, { /* 269 */ 16, /* ADOX64rm */ }, { /* 270 */ 18, /* ADOX64rr */ }, { /* 271 */ 26, /* AESDECLASTrm */ }, { /* 272 */ 27, /* AESDECLASTrr */ }, { /* 273 */ 26, /* AESDECrm */ }, { /* 274 */ 27, /* AESDECrr */ }, { /* 275 */ 26, /* AESENCLASTrm */ }, { /* 276 */ 27, /* AESENCLASTrr */ }, { /* 277 */ 26, /* AESENCrm */ }, { /* 278 */ 27, /* AESENCrr */ }, { /* 279 */ 30, /* AESIMCrm */ }, { /* 280 */ 31, /* AESIMCrr */ }, { /* 281 */ 32, /* AESKEYGENASSIST128rm */ }, { /* 282 */ 33, /* AESKEYGENASSIST128rr */ }, { /* 283 */ 2, /* AND16i16 */ }, { /* 284 */ 3, /* AND16mi */ }, { /* 285 */ 4, /* AND16mi8 */ }, { /* 286 */ 5, /* AND16mr */ }, { /* 287 */ 6, /* AND16ri */ }, { /* 288 */ 7, /* AND16ri8 */ }, { /* 289 */ 8, /* AND16rm */ }, { /* 290 */ 9, /* AND16rr */ }, { /* 291 */ 10, /* AND16rr_REV */ }, { /* 292 */ 2, /* AND32i32 */ }, { /* 293 */ 3, /* AND32mi */ }, { /* 294 */ 4, /* AND32mi8 */ }, { /* 295 */ 5, /* AND32mr */ }, { /* 296 */ 6, /* AND32ri */ }, { /* 297 */ 7, /* AND32ri8 */ }, { /* 298 */ 8, /* AND32rm */ }, { /* 299 */ 9, /* AND32rr */ }, { /* 300 */ 10, /* AND32rr_REV */ }, { /* 301 */ 11, /* AND64i32 */ }, { /* 302 */ 12, /* AND64mi32 */ }, { /* 303 */ 4, /* AND64mi8 */ }, { /* 304 */ 13, /* AND64mr */ }, { /* 305 */ 14, /* AND64ri32 */ }, { /* 306 */ 15, /* AND64ri8 */ }, { /* 307 */ 16, /* AND64rm */ }, { /* 308 */ 17, /* AND64rr */ }, { /* 309 */ 18, /* AND64rr_REV */ }, { /* 310 */ 1, /* AND8i8 */ }, { /* 311 */ 4, /* AND8mi */ }, { /* 312 */ 4, /* AND8mi8 */ }, { /* 313 */ 19, /* AND8mr */ }, { /* 314 */ 20, /* AND8ri */ }, { /* 315 */ 20, /* AND8ri8 */ }, { /* 316 */ 21, /* AND8rm */ }, { /* 317 */ 22, /* AND8rr */ }, { /* 318 */ 23, /* AND8rr_REV */ }, { /* 319 */ 34, /* ANDN32rm */ }, { /* 320 */ 35, /* ANDN32rr */ }, { /* 321 */ 36, /* ANDN64rm */ }, { /* 322 */ 37, /* ANDN64rr */ }, { /* 323 */ 26, /* ANDNPDrm */ }, { /* 324 */ 27, /* ANDNPDrr */ }, { /* 325 */ 26, /* ANDNPSrm */ }, { /* 326 */ 27, /* ANDNPSrr */ }, { /* 327 */ 26, /* ANDPDrm */ }, { /* 328 */ 27, /* ANDPDrr */ }, { /* 329 */ 26, /* ANDPSrm */ }, { /* 330 */ 27, /* ANDPSrr */ }, { /* 331 */ 38, /* ARPL16mr */ }, { /* 332 */ 39, /* ARPL16rr */ }, { /* 333 */ 40, /* BEXTR32rm */ }, { /* 334 */ 41, /* BEXTR32rr */ }, { /* 335 */ 42, /* BEXTR64rm */ }, { /* 336 */ 43, /* BEXTR64rr */ }, { /* 337 */ 44, /* BEXTRI32mi */ }, { /* 338 */ 45, /* BEXTRI32ri */ }, { /* 339 */ 46, /* BEXTRI64mi */ }, { /* 340 */ 47, /* BEXTRI64ri */ }, { /* 341 */ 48, /* BLCFILL32rm */ }, { /* 342 */ 49, /* BLCFILL32rr */ }, { /* 343 */ 50, /* BLCFILL64rm */ }, { /* 344 */ 51, /* BLCFILL64rr */ }, { /* 345 */ 48, /* BLCI32rm */ }, { /* 346 */ 49, /* BLCI32rr */ }, { /* 347 */ 50, /* BLCI64rm */ }, { /* 348 */ 51, /* BLCI64rr */ }, { /* 349 */ 48, /* BLCIC32rm */ }, { /* 350 */ 49, /* BLCIC32rr */ }, { /* 351 */ 50, /* BLCIC64rm */ }, { /* 352 */ 51, /* BLCIC64rr */ }, { /* 353 */ 48, /* BLCMSK32rm */ }, { /* 354 */ 49, /* BLCMSK32rr */ }, { /* 355 */ 50, /* BLCMSK64rm */ }, { /* 356 */ 51, /* BLCMSK64rr */ }, { /* 357 */ 48, /* BLCS32rm */ }, { /* 358 */ 49, /* BLCS32rr */ }, { /* 359 */ 50, /* BLCS64rm */ }, { /* 360 */ 51, /* BLCS64rr */ }, { /* 361 */ 52, /* BLENDPDrmi */ }, { /* 362 */ 53, /* BLENDPDrri */ }, { /* 363 */ 52, /* BLENDPSrmi */ }, { /* 364 */ 53, /* BLENDPSrri */ }, { /* 365 */ 26, /* BLENDVPDrm0 */ }, { /* 366 */ 27, /* BLENDVPDrr0 */ }, { /* 367 */ 26, /* BLENDVPSrm0 */ }, { /* 368 */ 27, /* BLENDVPSrr0 */ }, { /* 369 */ 48, /* BLSFILL32rm */ }, { /* 370 */ 49, /* BLSFILL32rr */ }, { /* 371 */ 50, /* BLSFILL64rm */ }, { /* 372 */ 51, /* BLSFILL64rr */ }, { /* 373 */ 48, /* BLSI32rm */ }, { /* 374 */ 49, /* BLSI32rr */ }, { /* 375 */ 50, /* BLSI64rm */ }, { /* 376 */ 51, /* BLSI64rr */ }, { /* 377 */ 48, /* BLSIC32rm */ }, { /* 378 */ 49, /* BLSIC32rr */ }, { /* 379 */ 50, /* BLSIC64rm */ }, { /* 380 */ 51, /* BLSIC64rr */ }, { /* 381 */ 48, /* BLSMSK32rm */ }, { /* 382 */ 49, /* BLSMSK32rr */ }, { /* 383 */ 50, /* BLSMSK64rm */ }, { /* 384 */ 51, /* BLSMSK64rr */ }, { /* 385 */ 48, /* BLSR32rm */ }, { /* 386 */ 49, /* BLSR32rr */ }, { /* 387 */ 50, /* BLSR64rm */ }, { /* 388 */ 51, /* BLSR64rr */ }, { /* 389 */ 54, /* BNDCL32rm */ }, { /* 390 */ 55, /* BNDCL32rr */ }, { /* 391 */ 54, /* BNDCL64rm */ }, { /* 392 */ 56, /* BNDCL64rr */ }, { /* 393 */ 54, /* BNDCN32rm */ }, { /* 394 */ 55, /* BNDCN32rr */ }, { /* 395 */ 54, /* BNDCN64rm */ }, { /* 396 */ 56, /* BNDCN64rr */ }, { /* 397 */ 54, /* BNDCU32rm */ }, { /* 398 */ 55, /* BNDCU32rr */ }, { /* 399 */ 54, /* BNDCU64rm */ }, { /* 400 */ 56, /* BNDCU64rr */ }, { /* 401 */ 54, /* BNDLDXrm */ }, { /* 402 */ 54, /* BNDMK32rm */ }, { /* 403 */ 54, /* BNDMK64rm */ }, { /* 404 */ 57, /* BNDMOV32mr */ }, { /* 405 */ 54, /* BNDMOV32rm */ }, { /* 406 */ 57, /* BNDMOV64mr */ }, { /* 407 */ 54, /* BNDMOV64rm */ }, { /* 408 */ 58, /* BNDMOVrr */ }, { /* 409 */ 59, /* BNDMOVrr_REV */ }, { /* 410 */ 57, /* BNDSTXmr */ }, { /* 411 */ 60, /* BOUNDS16rm */ }, { /* 412 */ 60, /* BOUNDS32rm */ }, { /* 413 */ 60, /* BSF16rm */ }, { /* 414 */ 61, /* BSF16rr */ }, { /* 415 */ 60, /* BSF32rm */ }, { /* 416 */ 61, /* BSF32rr */ }, { /* 417 */ 62, /* BSF64rm */ }, { /* 418 */ 63, /* BSF64rr */ }, { /* 419 */ 60, /* BSR16rm */ }, { /* 420 */ 61, /* BSR16rr */ }, { /* 421 */ 60, /* BSR32rm */ }, { /* 422 */ 61, /* BSR32rr */ }, { /* 423 */ 62, /* BSR64rm */ }, { /* 424 */ 63, /* BSR64rr */ }, { /* 425 */ 64, /* BSWAP16r_BAD */ }, { /* 426 */ 64, /* BSWAP32r */ }, { /* 427 */ 65, /* BSWAP64r */ }, { /* 428 */ 4, /* BT16mi8 */ }, { /* 429 */ 5, /* BT16mr */ }, { /* 430 */ 66, /* BT16ri8 */ }, { /* 431 */ 67, /* BT16rr */ }, { /* 432 */ 4, /* BT32mi8 */ }, { /* 433 */ 5, /* BT32mr */ }, { /* 434 */ 66, /* BT32ri8 */ }, { /* 435 */ 67, /* BT32rr */ }, { /* 436 */ 4, /* BT64mi8 */ }, { /* 437 */ 13, /* BT64mr */ }, { /* 438 */ 68, /* BT64ri8 */ }, { /* 439 */ 69, /* BT64rr */ }, { /* 440 */ 4, /* BTC16mi8 */ }, { /* 441 */ 5, /* BTC16mr */ }, { /* 442 */ 7, /* BTC16ri8 */ }, { /* 443 */ 9, /* BTC16rr */ }, { /* 444 */ 4, /* BTC32mi8 */ }, { /* 445 */ 5, /* BTC32mr */ }, { /* 446 */ 7, /* BTC32ri8 */ }, { /* 447 */ 9, /* BTC32rr */ }, { /* 448 */ 4, /* BTC64mi8 */ }, { /* 449 */ 13, /* BTC64mr */ }, { /* 450 */ 15, /* BTC64ri8 */ }, { /* 451 */ 17, /* BTC64rr */ }, { /* 452 */ 4, /* BTR16mi8 */ }, { /* 453 */ 5, /* BTR16mr */ }, { /* 454 */ 7, /* BTR16ri8 */ }, { /* 455 */ 9, /* BTR16rr */ }, { /* 456 */ 4, /* BTR32mi8 */ }, { /* 457 */ 5, /* BTR32mr */ }, { /* 458 */ 7, /* BTR32ri8 */ }, { /* 459 */ 9, /* BTR32rr */ }, { /* 460 */ 4, /* BTR64mi8 */ }, { /* 461 */ 13, /* BTR64mr */ }, { /* 462 */ 15, /* BTR64ri8 */ }, { /* 463 */ 17, /* BTR64rr */ }, { /* 464 */ 4, /* BTS16mi8 */ }, { /* 465 */ 5, /* BTS16mr */ }, { /* 466 */ 7, /* BTS16ri8 */ }, { /* 467 */ 9, /* BTS16rr */ }, { /* 468 */ 4, /* BTS32mi8 */ }, { /* 469 */ 5, /* BTS32mr */ }, { /* 470 */ 7, /* BTS32ri8 */ }, { /* 471 */ 9, /* BTS32rr */ }, { /* 472 */ 4, /* BTS64mi8 */ }, { /* 473 */ 13, /* BTS64mr */ }, { /* 474 */ 15, /* BTS64ri8 */ }, { /* 475 */ 17, /* BTS64rr */ }, { /* 476 */ 40, /* BZHI32rm */ }, { /* 477 */ 41, /* BZHI32rr */ }, { /* 478 */ 42, /* BZHI64rm */ }, { /* 479 */ 43, /* BZHI64rr */ }, { /* 480 */ 28, /* CALL16m */ }, { /* 481 */ 0, /* */ }, { /* 482 */ 70, /* CALL16r */ }, { /* 483 */ 0, /* */ }, { /* 484 */ 28, /* CALL32m */ }, { /* 485 */ 0, /* */ }, { /* 486 */ 70, /* CALL32r */ }, { /* 487 */ 0, /* */ }, { /* 488 */ 28, /* CALL64m */ }, { /* 489 */ 0, /* */ }, { /* 490 */ 71, /* CALL64pcrel32 */ }, { /* 491 */ 72, /* CALL64r */ }, { /* 492 */ 0, /* */ }, { /* 493 */ 73, /* CALLpcrel16 */ }, { /* 494 */ 71, /* CALLpcrel32 */ }, { /* 495 */ 0, /* CBW */ }, { /* 496 */ 0, /* CDQ */ }, { /* 497 */ 0, /* CDQE */ }, { /* 498 */ 0, /* CHS_F */ }, { /* 499 */ 0, /* */ }, { /* 500 */ 0, /* */ }, { /* 501 */ 0, /* */ }, { /* 502 */ 0, /* CLAC */ }, { /* 503 */ 0, /* CLC */ }, { /* 504 */ 0, /* CLD */ }, { /* 505 */ 28, /* CLDEMOTE */ }, { /* 506 */ 28, /* CLFLUSH */ }, { /* 507 */ 28, /* CLFLUSHOPT */ }, { /* 508 */ 0, /* CLGI */ }, { /* 509 */ 0, /* CLI */ }, { /* 510 */ 28, /* CLRSSBSY */ }, { /* 511 */ 0, /* CLTS */ }, { /* 512 */ 28, /* CLWB */ }, { /* 513 */ 0, /* CLZEROr */ }, { /* 514 */ 0, /* CMC */ }, { /* 515 */ 8, /* CMOVA16rm */ }, { /* 516 */ 10, /* CMOVA16rr */ }, { /* 517 */ 8, /* CMOVA32rm */ }, { /* 518 */ 10, /* CMOVA32rr */ }, { /* 519 */ 16, /* CMOVA64rm */ }, { /* 520 */ 18, /* CMOVA64rr */ }, { /* 521 */ 8, /* CMOVAE16rm */ }, { /* 522 */ 10, /* CMOVAE16rr */ }, { /* 523 */ 8, /* CMOVAE32rm */ }, { /* 524 */ 10, /* CMOVAE32rr */ }, { /* 525 */ 16, /* CMOVAE64rm */ }, { /* 526 */ 18, /* CMOVAE64rr */ }, { /* 527 */ 8, /* CMOVB16rm */ }, { /* 528 */ 10, /* CMOVB16rr */ }, { /* 529 */ 8, /* CMOVB32rm */ }, { /* 530 */ 10, /* CMOVB32rr */ }, { /* 531 */ 16, /* CMOVB64rm */ }, { /* 532 */ 18, /* CMOVB64rr */ }, { /* 533 */ 8, /* CMOVBE16rm */ }, { /* 534 */ 10, /* CMOVBE16rr */ }, { /* 535 */ 8, /* CMOVBE32rm */ }, { /* 536 */ 10, /* CMOVBE32rr */ }, { /* 537 */ 16, /* CMOVBE64rm */ }, { /* 538 */ 18, /* CMOVBE64rr */ }, { /* 539 */ 29, /* CMOVBE_F */ }, { /* 540 */ 0, /* */ }, { /* 541 */ 0, /* */ }, { /* 542 */ 0, /* */ }, { /* 543 */ 29, /* CMOVB_F */ }, { /* 544 */ 0, /* */ }, { /* 545 */ 0, /* */ }, { /* 546 */ 0, /* */ }, { /* 547 */ 8, /* CMOVE16rm */ }, { /* 548 */ 10, /* CMOVE16rr */ }, { /* 549 */ 8, /* CMOVE32rm */ }, { /* 550 */ 10, /* CMOVE32rr */ }, { /* 551 */ 16, /* CMOVE64rm */ }, { /* 552 */ 18, /* CMOVE64rr */ }, { /* 553 */ 29, /* CMOVE_F */ }, { /* 554 */ 0, /* */ }, { /* 555 */ 0, /* */ }, { /* 556 */ 0, /* */ }, { /* 557 */ 8, /* CMOVG16rm */ }, { /* 558 */ 10, /* CMOVG16rr */ }, { /* 559 */ 8, /* CMOVG32rm */ }, { /* 560 */ 10, /* CMOVG32rr */ }, { /* 561 */ 16, /* CMOVG64rm */ }, { /* 562 */ 18, /* CMOVG64rr */ }, { /* 563 */ 8, /* CMOVGE16rm */ }, { /* 564 */ 10, /* CMOVGE16rr */ }, { /* 565 */ 8, /* CMOVGE32rm */ }, { /* 566 */ 10, /* CMOVGE32rr */ }, { /* 567 */ 16, /* CMOVGE64rm */ }, { /* 568 */ 18, /* CMOVGE64rr */ }, { /* 569 */ 8, /* CMOVL16rm */ }, { /* 570 */ 10, /* CMOVL16rr */ }, { /* 571 */ 8, /* CMOVL32rm */ }, { /* 572 */ 10, /* CMOVL32rr */ }, { /* 573 */ 16, /* CMOVL64rm */ }, { /* 574 */ 18, /* CMOVL64rr */ }, { /* 575 */ 8, /* CMOVLE16rm */ }, { /* 576 */ 10, /* CMOVLE16rr */ }, { /* 577 */ 8, /* CMOVLE32rm */ }, { /* 578 */ 10, /* CMOVLE32rr */ }, { /* 579 */ 16, /* CMOVLE64rm */ }, { /* 580 */ 18, /* CMOVLE64rr */ }, { /* 581 */ 29, /* CMOVNBE_F */ }, { /* 582 */ 0, /* */ }, { /* 583 */ 0, /* */ }, { /* 584 */ 0, /* */ }, { /* 585 */ 29, /* CMOVNB_F */ }, { /* 586 */ 0, /* */ }, { /* 587 */ 0, /* */ }, { /* 588 */ 0, /* */ }, { /* 589 */ 8, /* CMOVNE16rm */ }, { /* 590 */ 10, /* CMOVNE16rr */ }, { /* 591 */ 8, /* CMOVNE32rm */ }, { /* 592 */ 10, /* CMOVNE32rr */ }, { /* 593 */ 16, /* CMOVNE64rm */ }, { /* 594 */ 18, /* CMOVNE64rr */ }, { /* 595 */ 29, /* CMOVNE_F */ }, { /* 596 */ 0, /* */ }, { /* 597 */ 0, /* */ }, { /* 598 */ 0, /* */ }, { /* 599 */ 8, /* CMOVNO16rm */ }, { /* 600 */ 10, /* CMOVNO16rr */ }, { /* 601 */ 8, /* CMOVNO32rm */ }, { /* 602 */ 10, /* CMOVNO32rr */ }, { /* 603 */ 16, /* CMOVNO64rm */ }, { /* 604 */ 18, /* CMOVNO64rr */ }, { /* 605 */ 8, /* CMOVNP16rm */ }, { /* 606 */ 10, /* CMOVNP16rr */ }, { /* 607 */ 8, /* CMOVNP32rm */ }, { /* 608 */ 10, /* CMOVNP32rr */ }, { /* 609 */ 16, /* CMOVNP64rm */ }, { /* 610 */ 18, /* CMOVNP64rr */ }, { /* 611 */ 29, /* CMOVNP_F */ }, { /* 612 */ 0, /* */ }, { /* 613 */ 0, /* */ }, { /* 614 */ 0, /* */ }, { /* 615 */ 8, /* CMOVNS16rm */ }, { /* 616 */ 10, /* CMOVNS16rr */ }, { /* 617 */ 8, /* CMOVNS32rm */ }, { /* 618 */ 10, /* CMOVNS32rr */ }, { /* 619 */ 16, /* CMOVNS64rm */ }, { /* 620 */ 18, /* CMOVNS64rr */ }, { /* 621 */ 8, /* CMOVO16rm */ }, { /* 622 */ 10, /* CMOVO16rr */ }, { /* 623 */ 8, /* CMOVO32rm */ }, { /* 624 */ 10, /* CMOVO32rr */ }, { /* 625 */ 16, /* CMOVO64rm */ }, { /* 626 */ 18, /* CMOVO64rr */ }, { /* 627 */ 8, /* CMOVP16rm */ }, { /* 628 */ 10, /* CMOVP16rr */ }, { /* 629 */ 8, /* CMOVP32rm */ }, { /* 630 */ 10, /* CMOVP32rr */ }, { /* 631 */ 16, /* CMOVP64rm */ }, { /* 632 */ 18, /* CMOVP64rr */ }, { /* 633 */ 29, /* CMOVP_F */ }, { /* 634 */ 0, /* */ }, { /* 635 */ 0, /* */ }, { /* 636 */ 0, /* */ }, { /* 637 */ 8, /* CMOVS16rm */ }, { /* 638 */ 10, /* CMOVS16rr */ }, { /* 639 */ 8, /* CMOVS32rm */ }, { /* 640 */ 10, /* CMOVS32rr */ }, { /* 641 */ 16, /* CMOVS64rm */ }, { /* 642 */ 18, /* CMOVS64rr */ }, { /* 643 */ 2, /* CMP16i16 */ }, { /* 644 */ 3, /* CMP16mi */ }, { /* 645 */ 4, /* CMP16mi8 */ }, { /* 646 */ 5, /* CMP16mr */ }, { /* 647 */ 74, /* CMP16ri */ }, { /* 648 */ 66, /* CMP16ri8 */ }, { /* 649 */ 60, /* CMP16rm */ }, { /* 650 */ 67, /* CMP16rr */ }, { /* 651 */ 61, /* CMP16rr_REV */ }, { /* 652 */ 2, /* CMP32i32 */ }, { /* 653 */ 3, /* CMP32mi */ }, { /* 654 */ 4, /* CMP32mi8 */ }, { /* 655 */ 5, /* CMP32mr */ }, { /* 656 */ 74, /* CMP32ri */ }, { /* 657 */ 66, /* CMP32ri8 */ }, { /* 658 */ 60, /* CMP32rm */ }, { /* 659 */ 67, /* CMP32rr */ }, { /* 660 */ 61, /* CMP32rr_REV */ }, { /* 661 */ 11, /* CMP64i32 */ }, { /* 662 */ 12, /* CMP64mi32 */ }, { /* 663 */ 4, /* CMP64mi8 */ }, { /* 664 */ 13, /* CMP64mr */ }, { /* 665 */ 75, /* CMP64ri32 */ }, { /* 666 */ 68, /* CMP64ri8 */ }, { /* 667 */ 62, /* CMP64rm */ }, { /* 668 */ 69, /* CMP64rr */ }, { /* 669 */ 63, /* CMP64rr_REV */ }, { /* 670 */ 1, /* CMP8i8 */ }, { /* 671 */ 4, /* CMP8mi */ }, { /* 672 */ 4, /* CMP8mi8 */ }, { /* 673 */ 19, /* CMP8mr */ }, { /* 674 */ 76, /* CMP8ri */ }, { /* 675 */ 76, /* CMP8ri8 */ }, { /* 676 */ 77, /* CMP8rm */ }, { /* 677 */ 78, /* CMP8rr */ }, { /* 678 */ 79, /* CMP8rr_REV */ }, { /* 679 */ 80, /* CMPPDrmi */ }, { /* 680 */ 0, /* */ }, { /* 681 */ 81, /* CMPPDrri */ }, { /* 682 */ 0, /* */ }, { /* 683 */ 80, /* CMPPSrmi */ }, { /* 684 */ 0, /* */ }, { /* 685 */ 81, /* CMPPSrri */ }, { /* 686 */ 0, /* */ }, { /* 687 */ 82, /* CMPSB */ }, { /* 688 */ 80, /* CMPSDrm */ }, { /* 689 */ 0, /* */ }, { /* 690 */ 0, /* */ }, { /* 691 */ 81, /* CMPSDrr */ }, { /* 692 */ 0, /* */ }, { /* 693 */ 0, /* */ }, { /* 694 */ 82, /* CMPSL */ }, { /* 695 */ 82, /* CMPSQ */ }, { /* 696 */ 80, /* CMPSSrm */ }, { /* 697 */ 0, /* */ }, { /* 698 */ 0, /* */ }, { /* 699 */ 81, /* CMPSSrr */ }, { /* 700 */ 0, /* */ }, { /* 701 */ 0, /* */ }, { /* 702 */ 82, /* CMPSW */ }, { /* 703 */ 28, /* CMPXCHG16B */ }, { /* 704 */ 5, /* CMPXCHG16rm */ }, { /* 705 */ 67, /* CMPXCHG16rr */ }, { /* 706 */ 5, /* CMPXCHG32rm */ }, { /* 707 */ 67, /* CMPXCHG32rr */ }, { /* 708 */ 13, /* CMPXCHG64rm */ }, { /* 709 */ 69, /* CMPXCHG64rr */ }, { /* 710 */ 28, /* CMPXCHG8B */ }, { /* 711 */ 19, /* CMPXCHG8rm */ }, { /* 712 */ 78, /* CMPXCHG8rr */ }, { /* 713 */ 30, /* COMISDrm */ }, { /* 714 */ 0, /* */ }, { /* 715 */ 31, /* COMISDrr */ }, { /* 716 */ 0, /* */ }, { /* 717 */ 30, /* COMISSrm */ }, { /* 718 */ 0, /* */ }, { /* 719 */ 31, /* COMISSrr */ }, { /* 720 */ 0, /* */ }, { /* 721 */ 29, /* COMP_FST0r */ }, { /* 722 */ 29, /* COM_FIPr */ }, { /* 723 */ 29, /* COM_FIr */ }, { /* 724 */ 29, /* COM_FST0r */ }, { /* 725 */ 0, /* COS_F */ }, { /* 726 */ 0, /* */ }, { /* 727 */ 0, /* */ }, { /* 728 */ 0, /* */ }, { /* 729 */ 0, /* CPUID */ }, { /* 730 */ 0, /* CQO */ }, { /* 731 */ 24, /* CRC32r32m16 */ }, { /* 732 */ 8, /* CRC32r32m32 */ }, { /* 733 */ 24, /* CRC32r32m8 */ }, { /* 734 */ 83, /* CRC32r32r16 */ }, { /* 735 */ 10, /* CRC32r32r32 */ }, { /* 736 */ 84, /* CRC32r32r8 */ }, { /* 737 */ 16, /* CRC32r64m64 */ }, { /* 738 */ 16, /* CRC32r64m8 */ }, { /* 739 */ 18, /* CRC32r64r64 */ }, { /* 740 */ 85, /* CRC32r64r8 */ }, { /* 741 */ 30, /* CVTDQ2PDrm */ }, { /* 742 */ 31, /* CVTDQ2PDrr */ }, { /* 743 */ 30, /* CVTDQ2PSrm */ }, { /* 744 */ 31, /* CVTDQ2PSrr */ }, { /* 745 */ 30, /* CVTPD2DQrm */ }, { /* 746 */ 31, /* CVTPD2DQrr */ }, { /* 747 */ 30, /* CVTPD2PSrm */ }, { /* 748 */ 31, /* CVTPD2PSrr */ }, { /* 749 */ 30, /* CVTPS2DQrm */ }, { /* 750 */ 31, /* CVTPS2DQrr */ }, { /* 751 */ 30, /* CVTPS2PDrm */ }, { /* 752 */ 31, /* CVTPS2PDrr */ }, { /* 753 */ 62, /* CVTSD2SI64rm_Int */ }, { /* 754 */ 86, /* CVTSD2SI64rr_Int */ }, { /* 755 */ 87, /* CVTSD2SIrm_Int */ }, { /* 756 */ 88, /* CVTSD2SIrr_Int */ }, { /* 757 */ 30, /* CVTSD2SSrm */ }, { /* 758 */ 0, /* */ }, { /* 759 */ 31, /* CVTSD2SSrr */ }, { /* 760 */ 0, /* */ }, { /* 761 */ 30, /* CVTSI2SDrm */ }, { /* 762 */ 0, /* */ }, { /* 763 */ 89, /* CVTSI2SDrr */ }, { /* 764 */ 0, /* */ }, { /* 765 */ 30, /* CVTSI2SSrm */ }, { /* 766 */ 0, /* */ }, { /* 767 */ 89, /* CVTSI2SSrr */ }, { /* 768 */ 0, /* */ }, { /* 769 */ 30, /* CVTSI642SDrm */ }, { /* 770 */ 0, /* */ }, { /* 771 */ 90, /* CVTSI642SDrr */ }, { /* 772 */ 0, /* */ }, { /* 773 */ 30, /* CVTSI642SSrm */ }, { /* 774 */ 0, /* */ }, { /* 775 */ 90, /* CVTSI642SSrr */ }, { /* 776 */ 0, /* */ }, { /* 777 */ 30, /* CVTSS2SDrm */ }, { /* 778 */ 0, /* */ }, { /* 779 */ 31, /* CVTSS2SDrr */ }, { /* 780 */ 0, /* */ }, { /* 781 */ 62, /* CVTSS2SI64rm_Int */ }, { /* 782 */ 86, /* CVTSS2SI64rr_Int */ }, { /* 783 */ 87, /* CVTSS2SIrm_Int */ }, { /* 784 */ 88, /* CVTSS2SIrr_Int */ }, { /* 785 */ 30, /* CVTTPD2DQrm */ }, { /* 786 */ 31, /* CVTTPD2DQrr */ }, { /* 787 */ 30, /* CVTTPS2DQrm */ }, { /* 788 */ 31, /* CVTTPS2DQrr */ }, { /* 789 */ 62, /* CVTTSD2SI64rm */ }, { /* 790 */ 0, /* */ }, { /* 791 */ 86, /* CVTTSD2SI64rr */ }, { /* 792 */ 0, /* */ }, { /* 793 */ 87, /* CVTTSD2SIrm */ }, { /* 794 */ 0, /* */ }, { /* 795 */ 88, /* CVTTSD2SIrr */ }, { /* 796 */ 0, /* */ }, { /* 797 */ 62, /* CVTTSS2SI64rm */ }, { /* 798 */ 0, /* */ }, { /* 799 */ 86, /* CVTTSS2SI64rr */ }, { /* 800 */ 0, /* */ }, { /* 801 */ 87, /* CVTTSS2SIrm */ }, { /* 802 */ 0, /* */ }, { /* 803 */ 88, /* CVTTSS2SIrr */ }, { /* 804 */ 0, /* */ }, { /* 805 */ 0, /* CWD */ }, { /* 806 */ 0, /* CWDE */ }, { /* 807 */ 0, /* DAA */ }, { /* 808 */ 0, /* DAS */ }, { /* 809 */ 0, /* DATA16_PREFIX */ }, { /* 810 */ 28, /* DEC16m */ }, { /* 811 */ 91, /* DEC16r */ }, { /* 812 */ 64, /* DEC16r_alt */ }, { /* 813 */ 28, /* DEC32m */ }, { /* 814 */ 91, /* DEC32r */ }, { /* 815 */ 64, /* DEC32r_alt */ }, { /* 816 */ 28, /* DEC64m */ }, { /* 817 */ 92, /* DEC64r */ }, { /* 818 */ 28, /* DEC8m */ }, { /* 819 */ 93, /* DEC8r */ }, { /* 820 */ 28, /* DIV16m */ }, { /* 821 */ 70, /* DIV16r */ }, { /* 822 */ 28, /* DIV32m */ }, { /* 823 */ 70, /* DIV32r */ }, { /* 824 */ 28, /* DIV64m */ }, { /* 825 */ 72, /* DIV64r */ }, { /* 826 */ 28, /* DIV8m */ }, { /* 827 */ 94, /* DIV8r */ }, { /* 828 */ 26, /* DIVPDrm */ }, { /* 829 */ 27, /* DIVPDrr */ }, { /* 830 */ 26, /* DIVPSrm */ }, { /* 831 */ 27, /* DIVPSrr */ }, { /* 832 */ 28, /* DIVR_F32m */ }, { /* 833 */ 28, /* DIVR_F64m */ }, { /* 834 */ 28, /* DIVR_FI16m */ }, { /* 835 */ 28, /* DIVR_FI32m */ }, { /* 836 */ 29, /* DIVR_FPrST0 */ }, { /* 837 */ 29, /* DIVR_FST0r */ }, { /* 838 */ 0, /* */ }, { /* 839 */ 0, /* */ }, { /* 840 */ 0, /* */ }, { /* 841 */ 0, /* */ }, { /* 842 */ 0, /* */ }, { /* 843 */ 0, /* */ }, { /* 844 */ 0, /* */ }, { /* 845 */ 0, /* */ }, { /* 846 */ 0, /* */ }, { /* 847 */ 0, /* */ }, { /* 848 */ 0, /* */ }, { /* 849 */ 29, /* DIVR_FrST0 */ }, { /* 850 */ 26, /* DIVSDrm */ }, { /* 851 */ 0, /* */ }, { /* 852 */ 27, /* DIVSDrr */ }, { /* 853 */ 0, /* */ }, { /* 854 */ 26, /* DIVSSrm */ }, { /* 855 */ 0, /* */ }, { /* 856 */ 27, /* DIVSSrr */ }, { /* 857 */ 0, /* */ }, { /* 858 */ 28, /* DIV_F32m */ }, { /* 859 */ 28, /* DIV_F64m */ }, { /* 860 */ 28, /* DIV_FI16m */ }, { /* 861 */ 28, /* DIV_FI32m */ }, { /* 862 */ 29, /* DIV_FPrST0 */ }, { /* 863 */ 29, /* DIV_FST0r */ }, { /* 864 */ 0, /* */ }, { /* 865 */ 0, /* */ }, { /* 866 */ 0, /* */ }, { /* 867 */ 0, /* */ }, { /* 868 */ 0, /* */ }, { /* 869 */ 0, /* */ }, { /* 870 */ 0, /* */ }, { /* 871 */ 0, /* */ }, { /* 872 */ 0, /* */ }, { /* 873 */ 0, /* */ }, { /* 874 */ 0, /* */ }, { /* 875 */ 0, /* */ }, { /* 876 */ 0, /* */ }, { /* 877 */ 0, /* */ }, { /* 878 */ 29, /* DIV_FrST0 */ }, { /* 879 */ 52, /* DPPDrmi */ }, { /* 880 */ 53, /* DPPDrri */ }, { /* 881 */ 52, /* DPPSrmi */ }, { /* 882 */ 53, /* DPPSrri */ }, { /* 883 */ 0, /* ENCLS */ }, { /* 884 */ 0, /* ENCLU */ }, { /* 885 */ 0, /* ENCLV */ }, { /* 886 */ 0, /* ENDBR32 */ }, { /* 887 */ 0, /* ENDBR64 */ }, { /* 888 */ 95, /* ENTER */ }, { /* 889 */ 96, /* EXTRACTPSmr */ }, { /* 890 */ 97, /* EXTRACTPSrr */ }, { /* 891 */ 27, /* EXTRQ */ }, { /* 892 */ 98, /* EXTRQI */ }, { /* 893 */ 0, /* F2XM1 */ }, { /* 894 */ 99, /* FARCALL16i */ }, { /* 895 */ 28, /* FARCALL16m */ }, { /* 896 */ 100, /* FARCALL32i */ }, { /* 897 */ 28, /* FARCALL32m */ }, { /* 898 */ 28, /* FARCALL64 */ }, { /* 899 */ 99, /* FARJMP16i */ }, { /* 900 */ 28, /* FARJMP16m */ }, { /* 901 */ 100, /* FARJMP32i */ }, { /* 902 */ 28, /* FARJMP32m */ }, { /* 903 */ 28, /* FARJMP64 */ }, { /* 904 */ 28, /* FBLDm */ }, { /* 905 */ 28, /* FBSTPm */ }, { /* 906 */ 28, /* FCOM32m */ }, { /* 907 */ 28, /* FCOM64m */ }, { /* 908 */ 28, /* FCOMP32m */ }, { /* 909 */ 28, /* FCOMP64m */ }, { /* 910 */ 0, /* FCOMPP */ }, { /* 911 */ 0, /* FDECSTP */ }, { /* 912 */ 0, /* FDISI8087_NOP */ }, { /* 913 */ 0, /* FEMMS */ }, { /* 914 */ 0, /* FENI8087_NOP */ }, { /* 915 */ 29, /* FFREE */ }, { /* 916 */ 29, /* FFREEP */ }, { /* 917 */ 28, /* FICOM16m */ }, { /* 918 */ 28, /* FICOM32m */ }, { /* 919 */ 28, /* FICOMP16m */ }, { /* 920 */ 28, /* FICOMP32m */ }, { /* 921 */ 0, /* FINCSTP */ }, { /* 922 */ 28, /* FLDCW16m */ }, { /* 923 */ 28, /* FLDENVm */ }, { /* 924 */ 0, /* FLDL2E */ }, { /* 925 */ 0, /* FLDL2T */ }, { /* 926 */ 0, /* FLDLG2 */ }, { /* 927 */ 0, /* FLDLN2 */ }, { /* 928 */ 0, /* FLDPI */ }, { /* 929 */ 0, /* FNCLEX */ }, { /* 930 */ 0, /* FNINIT */ }, { /* 931 */ 0, /* FNOP */ }, { /* 932 */ 28, /* FNSTCW16m */ }, { /* 933 */ 0, /* FNSTSW16r */ }, { /* 934 */ 28, /* FNSTSWm */ }, { /* 935 */ 0, /* FPATAN */ }, { /* 936 */ 29, /* FPNCEST0r */ }, { /* 937 */ 0, /* FPREM */ }, { /* 938 */ 0, /* FPREM1 */ }, { /* 939 */ 0, /* FPTAN */ }, { /* 940 */ 0, /* FRNDINT */ }, { /* 941 */ 28, /* FRSTORm */ }, { /* 942 */ 28, /* FSAVEm */ }, { /* 943 */ 0, /* FSCALE */ }, { /* 944 */ 0, /* FSETPM */ }, { /* 945 */ 0, /* FSINCOS */ }, { /* 946 */ 28, /* FSTENVm */ }, { /* 947 */ 0, /* FXAM */ }, { /* 948 */ 28, /* FXRSTOR */ }, { /* 949 */ 28, /* FXRSTOR64 */ }, { /* 950 */ 28, /* FXSAVE */ }, { /* 951 */ 28, /* FXSAVE64 */ }, { /* 952 */ 0, /* FXTRACT */ }, { /* 953 */ 0, /* FYL2X */ }, { /* 954 */ 0, /* FYL2XP1 */ }, { /* 955 */ 0, /* GETSEC */ }, { /* 956 */ 52, /* GF2P8AFFINEINVQBrmi */ }, { /* 957 */ 53, /* GF2P8AFFINEINVQBrri */ }, { /* 958 */ 52, /* GF2P8AFFINEQBrmi */ }, { /* 959 */ 53, /* GF2P8AFFINEQBrri */ }, { /* 960 */ 26, /* GF2P8MULBrm */ }, { /* 961 */ 27, /* GF2P8MULBrr */ }, { /* 962 */ 26, /* HADDPDrm */ }, { /* 963 */ 27, /* HADDPDrr */ }, { /* 964 */ 26, /* HADDPSrm */ }, { /* 965 */ 27, /* HADDPSrr */ }, { /* 966 */ 0, /* HLT */ }, { /* 967 */ 26, /* HSUBPDrm */ }, { /* 968 */ 27, /* HSUBPDrr */ }, { /* 969 */ 26, /* HSUBPSrm */ }, { /* 970 */ 27, /* HSUBPSrr */ }, { /* 971 */ 28, /* IDIV16m */ }, { /* 972 */ 70, /* IDIV16r */ }, { /* 973 */ 28, /* IDIV32m */ }, { /* 974 */ 70, /* IDIV32r */ }, { /* 975 */ 28, /* IDIV64m */ }, { /* 976 */ 72, /* IDIV64r */ }, { /* 977 */ 28, /* IDIV8m */ }, { /* 978 */ 94, /* IDIV8r */ }, { /* 979 */ 28, /* ILD_F16m */ }, { /* 980 */ 28, /* ILD_F32m */ }, { /* 981 */ 28, /* ILD_F64m */ }, { /* 982 */ 0, /* */ }, { /* 983 */ 0, /* */ }, { /* 984 */ 0, /* */ }, { /* 985 */ 0, /* */ }, { /* 986 */ 0, /* */ }, { /* 987 */ 0, /* */ }, { /* 988 */ 0, /* */ }, { /* 989 */ 0, /* */ }, { /* 990 */ 0, /* */ }, { /* 991 */ 28, /* IMUL16m */ }, { /* 992 */ 70, /* IMUL16r */ }, { /* 993 */ 8, /* IMUL16rm */ }, { /* 994 */ 101, /* IMUL16rmi */ }, { /* 995 */ 102, /* IMUL16rmi8 */ }, { /* 996 */ 10, /* IMUL16rr */ }, { /* 997 */ 103, /* IMUL16rri */ }, { /* 998 */ 104, /* IMUL16rri8 */ }, { /* 999 */ 28, /* IMUL32m */ }, { /* 1000 */ 70, /* IMUL32r */ }, { /* 1001 */ 8, /* IMUL32rm */ }, { /* 1002 */ 101, /* IMUL32rmi */ }, { /* 1003 */ 102, /* IMUL32rmi8 */ }, { /* 1004 */ 10, /* IMUL32rr */ }, { /* 1005 */ 103, /* IMUL32rri */ }, { /* 1006 */ 104, /* IMUL32rri8 */ }, { /* 1007 */ 28, /* IMUL64m */ }, { /* 1008 */ 72, /* IMUL64r */ }, { /* 1009 */ 16, /* IMUL64rm */ }, { /* 1010 */ 46, /* IMUL64rmi32 */ }, { /* 1011 */ 105, /* IMUL64rmi8 */ }, { /* 1012 */ 18, /* IMUL64rr */ }, { /* 1013 */ 47, /* IMUL64rri32 */ }, { /* 1014 */ 106, /* IMUL64rri8 */ }, { /* 1015 */ 28, /* IMUL8m */ }, { /* 1016 */ 94, /* IMUL8r */ }, { /* 1017 */ 107, /* IN16ri */ }, { /* 1018 */ 0, /* IN16rr */ }, { /* 1019 */ 107, /* IN32ri */ }, { /* 1020 */ 0, /* IN32rr */ }, { /* 1021 */ 107, /* IN8ri */ }, { /* 1022 */ 0, /* IN8rr */ }, { /* 1023 */ 28, /* INC16m */ }, { /* 1024 */ 91, /* INC16r */ }, { /* 1025 */ 64, /* INC16r_alt */ }, { /* 1026 */ 28, /* INC32m */ }, { /* 1027 */ 91, /* INC32r */ }, { /* 1028 */ 64, /* INC32r_alt */ }, { /* 1029 */ 28, /* INC64m */ }, { /* 1030 */ 92, /* INC64r */ }, { /* 1031 */ 28, /* INC8m */ }, { /* 1032 */ 93, /* INC8r */ }, { /* 1033 */ 108, /* INCSSPD */ }, { /* 1034 */ 72, /* INCSSPQ */ }, { /* 1035 */ 109, /* INSB */ }, { /* 1036 */ 52, /* INSERTPSrm */ }, { /* 1037 */ 53, /* INSERTPSrr */ }, { /* 1038 */ 27, /* INSERTQ */ }, { /* 1039 */ 110, /* INSERTQI */ }, { /* 1040 */ 109, /* INSL */ }, { /* 1041 */ 109, /* INSW */ }, { /* 1042 */ 107, /* INT */ }, { /* 1043 */ 0, /* INT1 */ }, { /* 1044 */ 0, /* INT3 */ }, { /* 1045 */ 0, /* INTO */ }, { /* 1046 */ 0, /* INVD */ }, { /* 1047 */ 87, /* INVEPT32 */ }, { /* 1048 */ 62, /* INVEPT64 */ }, { /* 1049 */ 28, /* INVLPG */ }, { /* 1050 */ 0, /* INVLPGA32 */ }, { /* 1051 */ 0, /* INVLPGA64 */ }, { /* 1052 */ 87, /* INVPCID32 */ }, { /* 1053 */ 62, /* INVPCID64 */ }, { /* 1054 */ 87, /* INVVPID32 */ }, { /* 1055 */ 62, /* INVVPID64 */ }, { /* 1056 */ 0, /* IRET16 */ }, { /* 1057 */ 0, /* IRET32 */ }, { /* 1058 */ 0, /* IRET64 */ }, { /* 1059 */ 28, /* ISTT_FP16m */ }, { /* 1060 */ 28, /* ISTT_FP32m */ }, { /* 1061 */ 28, /* ISTT_FP64m */ }, { /* 1062 */ 0, /* */ }, { /* 1063 */ 0, /* */ }, { /* 1064 */ 0, /* */ }, { /* 1065 */ 0, /* */ }, { /* 1066 */ 0, /* */ }, { /* 1067 */ 0, /* */ }, { /* 1068 */ 0, /* */ }, { /* 1069 */ 0, /* */ }, { /* 1070 */ 0, /* */ }, { /* 1071 */ 28, /* IST_F16m */ }, { /* 1072 */ 28, /* IST_F32m */ }, { /* 1073 */ 28, /* IST_FP16m */ }, { /* 1074 */ 28, /* IST_FP32m */ }, { /* 1075 */ 28, /* IST_FP64m */ }, { /* 1076 */ 0, /* */ }, { /* 1077 */ 0, /* */ }, { /* 1078 */ 0, /* */ }, { /* 1079 */ 0, /* */ }, { /* 1080 */ 0, /* */ }, { /* 1081 */ 0, /* */ }, { /* 1082 */ 0, /* */ }, { /* 1083 */ 0, /* */ }, { /* 1084 */ 0, /* */ }, { /* 1085 */ 111, /* JAE_1 */ }, { /* 1086 */ 112, /* JAE_2 */ }, { /* 1087 */ 112, /* JAE_4 */ }, { /* 1088 */ 111, /* JA_1 */ }, { /* 1089 */ 112, /* JA_2 */ }, { /* 1090 */ 112, /* JA_4 */ }, { /* 1091 */ 111, /* JBE_1 */ }, { /* 1092 */ 112, /* JBE_2 */ }, { /* 1093 */ 112, /* JBE_4 */ }, { /* 1094 */ 111, /* JB_1 */ }, { /* 1095 */ 112, /* JB_2 */ }, { /* 1096 */ 112, /* JB_4 */ }, { /* 1097 */ 111, /* JCXZ */ }, { /* 1098 */ 111, /* JECXZ */ }, { /* 1099 */ 111, /* JE_1 */ }, { /* 1100 */ 112, /* JE_2 */ }, { /* 1101 */ 112, /* JE_4 */ }, { /* 1102 */ 111, /* JGE_1 */ }, { /* 1103 */ 112, /* JGE_2 */ }, { /* 1104 */ 112, /* JGE_4 */ }, { /* 1105 */ 111, /* JG_1 */ }, { /* 1106 */ 112, /* JG_2 */ }, { /* 1107 */ 112, /* JG_4 */ }, { /* 1108 */ 111, /* JLE_1 */ }, { /* 1109 */ 112, /* JLE_2 */ }, { /* 1110 */ 112, /* JLE_4 */ }, { /* 1111 */ 111, /* JL_1 */ }, { /* 1112 */ 112, /* JL_2 */ }, { /* 1113 */ 112, /* JL_4 */ }, { /* 1114 */ 28, /* JMP16m */ }, { /* 1115 */ 0, /* */ }, { /* 1116 */ 70, /* JMP16r */ }, { /* 1117 */ 0, /* */ }, { /* 1118 */ 28, /* JMP32m */ }, { /* 1119 */ 0, /* */ }, { /* 1120 */ 70, /* JMP32r */ }, { /* 1121 */ 0, /* */ }, { /* 1122 */ 28, /* JMP64m */ }, { /* 1123 */ 0, /* */ }, { /* 1124 */ 72, /* JMP64r */ }, { /* 1125 */ 0, /* */ }, { /* 1126 */ 111, /* JMP_1 */ }, { /* 1127 */ 112, /* JMP_2 */ }, { /* 1128 */ 112, /* JMP_4 */ }, { /* 1129 */ 111, /* JNE_1 */ }, { /* 1130 */ 112, /* JNE_2 */ }, { /* 1131 */ 112, /* JNE_4 */ }, { /* 1132 */ 111, /* JNO_1 */ }, { /* 1133 */ 112, /* JNO_2 */ }, { /* 1134 */ 112, /* JNO_4 */ }, { /* 1135 */ 111, /* JNP_1 */ }, { /* 1136 */ 112, /* JNP_2 */ }, { /* 1137 */ 112, /* JNP_4 */ }, { /* 1138 */ 111, /* JNS_1 */ }, { /* 1139 */ 112, /* JNS_2 */ }, { /* 1140 */ 112, /* JNS_4 */ }, { /* 1141 */ 111, /* JO_1 */ }, { /* 1142 */ 112, /* JO_2 */ }, { /* 1143 */ 112, /* JO_4 */ }, { /* 1144 */ 111, /* JP_1 */ }, { /* 1145 */ 112, /* JP_2 */ }, { /* 1146 */ 112, /* JP_4 */ }, { /* 1147 */ 111, /* JRCXZ */ }, { /* 1148 */ 111, /* JS_1 */ }, { /* 1149 */ 112, /* JS_2 */ }, { /* 1150 */ 112, /* JS_4 */ }, { /* 1151 */ 113, /* KADDBrr */ }, { /* 1152 */ 113, /* KADDDrr */ }, { /* 1153 */ 113, /* KADDQrr */ }, { /* 1154 */ 113, /* KADDWrr */ }, { /* 1155 */ 113, /* KANDBrr */ }, { /* 1156 */ 113, /* KANDDrr */ }, { /* 1157 */ 113, /* KANDNBrr */ }, { /* 1158 */ 113, /* KANDNDrr */ }, { /* 1159 */ 113, /* KANDNQrr */ }, { /* 1160 */ 113, /* KANDNWrr */ }, { /* 1161 */ 113, /* KANDQrr */ }, { /* 1162 */ 113, /* KANDWrr */ }, { /* 1163 */ 114, /* KMOVBkk */ }, { /* 1164 */ 115, /* KMOVBkm */ }, { /* 1165 */ 116, /* KMOVBkr */ }, { /* 1166 */ 117, /* KMOVBmk */ }, { /* 1167 */ 118, /* KMOVBrk */ }, { /* 1168 */ 114, /* KMOVDkk */ }, { /* 1169 */ 115, /* KMOVDkm */ }, { /* 1170 */ 116, /* KMOVDkr */ }, { /* 1171 */ 117, /* KMOVDmk */ }, { /* 1172 */ 118, /* KMOVDrk */ }, { /* 1173 */ 114, /* KMOVQkk */ }, { /* 1174 */ 115, /* KMOVQkm */ }, { /* 1175 */ 119, /* KMOVQkr */ }, { /* 1176 */ 117, /* KMOVQmk */ }, { /* 1177 */ 120, /* KMOVQrk */ }, { /* 1178 */ 114, /* KMOVWkk */ }, { /* 1179 */ 115, /* KMOVWkm */ }, { /* 1180 */ 116, /* KMOVWkr */ }, { /* 1181 */ 117, /* KMOVWmk */ }, { /* 1182 */ 118, /* KMOVWrk */ }, { /* 1183 */ 114, /* KNOTBrr */ }, { /* 1184 */ 114, /* KNOTDrr */ }, { /* 1185 */ 114, /* KNOTQrr */ }, { /* 1186 */ 114, /* KNOTWrr */ }, { /* 1187 */ 113, /* KORBrr */ }, { /* 1188 */ 113, /* KORDrr */ }, { /* 1189 */ 113, /* KORQrr */ }, { /* 1190 */ 114, /* KORTESTBrr */ }, { /* 1191 */ 114, /* KORTESTDrr */ }, { /* 1192 */ 114, /* KORTESTQrr */ }, { /* 1193 */ 114, /* KORTESTWrr */ }, { /* 1194 */ 113, /* KORWrr */ }, { /* 1195 */ 121, /* KSHIFTLBri */ }, { /* 1196 */ 121, /* KSHIFTLDri */ }, { /* 1197 */ 121, /* KSHIFTLQri */ }, { /* 1198 */ 121, /* KSHIFTLWri */ }, { /* 1199 */ 121, /* KSHIFTRBri */ }, { /* 1200 */ 121, /* KSHIFTRDri */ }, { /* 1201 */ 121, /* KSHIFTRQri */ }, { /* 1202 */ 121, /* KSHIFTRWri */ }, { /* 1203 */ 114, /* KTESTBrr */ }, { /* 1204 */ 114, /* KTESTDrr */ }, { /* 1205 */ 114, /* KTESTQrr */ }, { /* 1206 */ 114, /* KTESTWrr */ }, { /* 1207 */ 113, /* KUNPCKBWrr */ }, { /* 1208 */ 113, /* KUNPCKDQrr */ }, { /* 1209 */ 113, /* KUNPCKWDrr */ }, { /* 1210 */ 113, /* KXNORBrr */ }, { /* 1211 */ 113, /* KXNORDrr */ }, { /* 1212 */ 113, /* KXNORQrr */ }, { /* 1213 */ 113, /* KXNORWrr */ }, { /* 1214 */ 113, /* KXORBrr */ }, { /* 1215 */ 113, /* KXORDrr */ }, { /* 1216 */ 113, /* KXORQrr */ }, { /* 1217 */ 113, /* KXORWrr */ }, { /* 1218 */ 0, /* LAHF */ }, { /* 1219 */ 60, /* LAR16rm */ }, { /* 1220 */ 61, /* LAR16rr */ }, { /* 1221 */ 60, /* LAR32rm */ }, { /* 1222 */ 61, /* LAR32rr */ }, { /* 1223 */ 62, /* LAR64rm */ }, { /* 1224 */ 122, /* LAR64rr */ }, { /* 1225 */ 30, /* LDDQUrm */ }, { /* 1226 */ 28, /* LDMXCSR */ }, { /* 1227 */ 60, /* LDS16rm */ }, { /* 1228 */ 60, /* LDS32rm */ }, { /* 1229 */ 0, /* LD_F0 */ }, { /* 1230 */ 0, /* LD_F1 */ }, { /* 1231 */ 28, /* LD_F32m */ }, { /* 1232 */ 28, /* LD_F64m */ }, { /* 1233 */ 28, /* LD_F80m */ }, { /* 1234 */ 0, /* */ }, { /* 1235 */ 0, /* */ }, { /* 1236 */ 0, /* */ }, { /* 1237 */ 0, /* */ }, { /* 1238 */ 0, /* */ }, { /* 1239 */ 0, /* */ }, { /* 1240 */ 0, /* */ }, { /* 1241 */ 0, /* */ }, { /* 1242 */ 0, /* */ }, { /* 1243 */ 0, /* */ }, { /* 1244 */ 0, /* */ }, { /* 1245 */ 0, /* */ }, { /* 1246 */ 29, /* LD_Frr */ }, { /* 1247 */ 60, /* LEA16r */ }, { /* 1248 */ 60, /* LEA32r */ }, { /* 1249 */ 60, /* LEA64_32r */ }, { /* 1250 */ 62, /* LEA64r */ }, { /* 1251 */ 0, /* LEAVE */ }, { /* 1252 */ 0, /* LEAVE64 */ }, { /* 1253 */ 60, /* LES16rm */ }, { /* 1254 */ 60, /* LES32rm */ }, { /* 1255 */ 0, /* LFENCE */ }, { /* 1256 */ 60, /* LFS16rm */ }, { /* 1257 */ 60, /* LFS32rm */ }, { /* 1258 */ 62, /* LFS64rm */ }, { /* 1259 */ 28, /* LGDT16m */ }, { /* 1260 */ 28, /* LGDT32m */ }, { /* 1261 */ 28, /* LGDT64m */ }, { /* 1262 */ 60, /* LGS16rm */ }, { /* 1263 */ 60, /* LGS32rm */ }, { /* 1264 */ 62, /* LGS64rm */ }, { /* 1265 */ 28, /* LIDT16m */ }, { /* 1266 */ 28, /* LIDT32m */ }, { /* 1267 */ 28, /* LIDT64m */ }, { /* 1268 */ 28, /* LLDT16m */ }, { /* 1269 */ 123, /* LLDT16r */ }, { /* 1270 */ 108, /* LLWPCB */ }, { /* 1271 */ 72, /* LLWPCB64 */ }, { /* 1272 */ 28, /* LMSW16m */ }, { /* 1273 */ 123, /* LMSW16r */ }, { /* 1274 */ 0, /* LOCK_PREFIX */ }, { /* 1275 */ 124, /* LODSB */ }, { /* 1276 */ 124, /* LODSL */ }, { /* 1277 */ 124, /* LODSQ */ }, { /* 1278 */ 124, /* LODSW */ }, { /* 1279 */ 111, /* LOOP */ }, { /* 1280 */ 111, /* LOOPE */ }, { /* 1281 */ 111, /* LOOPNE */ }, { /* 1282 */ 125, /* LRETIL */ }, { /* 1283 */ 125, /* LRETIQ */ }, { /* 1284 */ 2, /* LRETIW */ }, { /* 1285 */ 0, /* LRETL */ }, { /* 1286 */ 0, /* LRETQ */ }, { /* 1287 */ 0, /* LRETW */ }, { /* 1288 */ 60, /* LSL16rm */ }, { /* 1289 */ 61, /* LSL16rr */ }, { /* 1290 */ 60, /* LSL32rm */ }, { /* 1291 */ 61, /* LSL32rr */ }, { /* 1292 */ 62, /* LSL64rm */ }, { /* 1293 */ 122, /* LSL64rr */ }, { /* 1294 */ 60, /* LSS16rm */ }, { /* 1295 */ 60, /* LSS32rm */ }, { /* 1296 */ 62, /* LSS64rm */ }, { /* 1297 */ 28, /* LTRm */ }, { /* 1298 */ 123, /* LTRr */ }, { /* 1299 */ 126, /* LWPINS32rmi */ }, { /* 1300 */ 127, /* LWPINS32rri */ }, { /* 1301 */ 128, /* LWPINS64rmi */ }, { /* 1302 */ 129, /* LWPINS64rri */ }, { /* 1303 */ 126, /* LWPVAL32rmi */ }, { /* 1304 */ 127, /* LWPVAL32rri */ }, { /* 1305 */ 128, /* LWPVAL64rmi */ }, { /* 1306 */ 129, /* LWPVAL64rri */ }, { /* 1307 */ 60, /* LZCNT16rm */ }, { /* 1308 */ 61, /* LZCNT16rr */ }, { /* 1309 */ 60, /* LZCNT32rm */ }, { /* 1310 */ 61, /* LZCNT32rr */ }, { /* 1311 */ 62, /* LZCNT64rm */ }, { /* 1312 */ 63, /* LZCNT64rr */ }, { /* 1313 */ 31, /* MASKMOVDQU */ }, { /* 1314 */ 31, /* MASKMOVDQU64 */ }, { /* 1315 */ 0, /* */ }, { /* 1316 */ 0, /* */ }, { /* 1317 */ 0, /* */ }, { /* 1318 */ 0, /* */ }, { /* 1319 */ 0, /* */ }, { /* 1320 */ 0, /* */ }, { /* 1321 */ 0, /* */ }, { /* 1322 */ 0, /* */ }, { /* 1323 */ 26, /* MAXPDrm */ }, { /* 1324 */ 27, /* MAXPDrr */ }, { /* 1325 */ 26, /* MAXPSrm */ }, { /* 1326 */ 27, /* MAXPSrr */ }, { /* 1327 */ 26, /* MAXSDrm */ }, { /* 1328 */ 0, /* */ }, { /* 1329 */ 27, /* MAXSDrr */ }, { /* 1330 */ 0, /* */ }, { /* 1331 */ 26, /* MAXSSrm */ }, { /* 1332 */ 0, /* */ }, { /* 1333 */ 27, /* MAXSSrr */ }, { /* 1334 */ 0, /* */ }, { /* 1335 */ 0, /* MFENCE */ }, { /* 1336 */ 0, /* */ }, { /* 1337 */ 0, /* */ }, { /* 1338 */ 0, /* */ }, { /* 1339 */ 0, /* */ }, { /* 1340 */ 0, /* */ }, { /* 1341 */ 0, /* */ }, { /* 1342 */ 0, /* */ }, { /* 1343 */ 0, /* */ }, { /* 1344 */ 26, /* MINPDrm */ }, { /* 1345 */ 27, /* MINPDrr */ }, { /* 1346 */ 26, /* MINPSrm */ }, { /* 1347 */ 27, /* MINPSrr */ }, { /* 1348 */ 26, /* MINSDrm */ }, { /* 1349 */ 0, /* */ }, { /* 1350 */ 27, /* MINSDrr */ }, { /* 1351 */ 0, /* */ }, { /* 1352 */ 26, /* MINSSrm */ }, { /* 1353 */ 0, /* */ }, { /* 1354 */ 27, /* MINSSrr */ }, { /* 1355 */ 0, /* */ }, { /* 1356 */ 130, /* MMX_CVTPD2PIirm */ }, { /* 1357 */ 131, /* MMX_CVTPD2PIirr */ }, { /* 1358 */ 30, /* MMX_CVTPI2PDirm */ }, { /* 1359 */ 132, /* MMX_CVTPI2PDirr */ }, { /* 1360 */ 26, /* MMX_CVTPI2PSirm */ }, { /* 1361 */ 133, /* MMX_CVTPI2PSirr */ }, { /* 1362 */ 130, /* MMX_CVTPS2PIirm */ }, { /* 1363 */ 131, /* MMX_CVTPS2PIirr */ }, { /* 1364 */ 130, /* MMX_CVTTPD2PIirm */ }, { /* 1365 */ 131, /* MMX_CVTTPD2PIirr */ }, { /* 1366 */ 130, /* MMX_CVTTPS2PIirm */ }, { /* 1367 */ 131, /* MMX_CVTTPS2PIirr */ }, { /* 1368 */ 0, /* MMX_EMMS */ }, { /* 1369 */ 134, /* MMX_MASKMOVQ */ }, { /* 1370 */ 134, /* MMX_MASKMOVQ64 */ }, { /* 1371 */ 135, /* MMX_MOVD64from64rm */ }, { /* 1372 */ 136, /* MMX_MOVD64from64rr */ }, { /* 1373 */ 137, /* MMX_MOVD64grr */ }, { /* 1374 */ 135, /* MMX_MOVD64mr */ }, { /* 1375 */ 130, /* MMX_MOVD64rm */ }, { /* 1376 */ 138, /* MMX_MOVD64rr */ }, { /* 1377 */ 130, /* MMX_MOVD64to64rm */ }, { /* 1378 */ 139, /* MMX_MOVD64to64rr */ }, { /* 1379 */ 131, /* MMX_MOVDQ2Qrr */ }, { /* 1380 */ 0, /* */ }, { /* 1381 */ 135, /* MMX_MOVNTQmr */ }, { /* 1382 */ 132, /* MMX_MOVQ2DQrr */ }, { /* 1383 */ 0, /* */ }, { /* 1384 */ 135, /* MMX_MOVQ64mr */ }, { /* 1385 */ 130, /* MMX_MOVQ64rm */ }, { /* 1386 */ 134, /* MMX_MOVQ64rr */ }, { /* 1387 */ 140, /* MMX_MOVQ64rr_REV */ }, { /* 1388 */ 130, /* MMX_PABSBrm */ }, { /* 1389 */ 134, /* MMX_PABSBrr */ }, { /* 1390 */ 130, /* MMX_PABSDrm */ }, { /* 1391 */ 134, /* MMX_PABSDrr */ }, { /* 1392 */ 130, /* MMX_PABSWrm */ }, { /* 1393 */ 134, /* MMX_PABSWrr */ }, { /* 1394 */ 141, /* MMX_PACKSSDWirm */ }, { /* 1395 */ 142, /* MMX_PACKSSDWirr */ }, { /* 1396 */ 141, /* MMX_PACKSSWBirm */ }, { /* 1397 */ 142, /* MMX_PACKSSWBirr */ }, { /* 1398 */ 141, /* MMX_PACKUSWBirm */ }, { /* 1399 */ 142, /* MMX_PACKUSWBirr */ }, { /* 1400 */ 141, /* MMX_PADDBirm */ }, { /* 1401 */ 142, /* MMX_PADDBirr */ }, { /* 1402 */ 141, /* MMX_PADDDirm */ }, { /* 1403 */ 142, /* MMX_PADDDirr */ }, { /* 1404 */ 141, /* MMX_PADDQirm */ }, { /* 1405 */ 142, /* MMX_PADDQirr */ }, { /* 1406 */ 141, /* MMX_PADDSBirm */ }, { /* 1407 */ 142, /* MMX_PADDSBirr */ }, { /* 1408 */ 141, /* MMX_PADDSWirm */ }, { /* 1409 */ 142, /* MMX_PADDSWirr */ }, { /* 1410 */ 141, /* MMX_PADDUSBirm */ }, { /* 1411 */ 142, /* MMX_PADDUSBirr */ }, { /* 1412 */ 141, /* MMX_PADDUSWirm */ }, { /* 1413 */ 142, /* MMX_PADDUSWirr */ }, { /* 1414 */ 141, /* MMX_PADDWirm */ }, { /* 1415 */ 142, /* MMX_PADDWirr */ }, { /* 1416 */ 143, /* MMX_PALIGNRrmi */ }, { /* 1417 */ 144, /* MMX_PALIGNRrri */ }, { /* 1418 */ 141, /* MMX_PANDNirm */ }, { /* 1419 */ 142, /* MMX_PANDNirr */ }, { /* 1420 */ 141, /* MMX_PANDirm */ }, { /* 1421 */ 142, /* MMX_PANDirr */ }, { /* 1422 */ 141, /* MMX_PAVGBirm */ }, { /* 1423 */ 142, /* MMX_PAVGBirr */ }, { /* 1424 */ 141, /* MMX_PAVGWirm */ }, { /* 1425 */ 142, /* MMX_PAVGWirr */ }, { /* 1426 */ 141, /* MMX_PCMPEQBirm */ }, { /* 1427 */ 142, /* MMX_PCMPEQBirr */ }, { /* 1428 */ 141, /* MMX_PCMPEQDirm */ }, { /* 1429 */ 142, /* MMX_PCMPEQDirr */ }, { /* 1430 */ 141, /* MMX_PCMPEQWirm */ }, { /* 1431 */ 142, /* MMX_PCMPEQWirr */ }, { /* 1432 */ 141, /* MMX_PCMPGTBirm */ }, { /* 1433 */ 142, /* MMX_PCMPGTBirr */ }, { /* 1434 */ 141, /* MMX_PCMPGTDirm */ }, { /* 1435 */ 142, /* MMX_PCMPGTDirr */ }, { /* 1436 */ 141, /* MMX_PCMPGTWirm */ }, { /* 1437 */ 142, /* MMX_PCMPGTWirr */ }, { /* 1438 */ 145, /* MMX_PEXTRWrr */ }, { /* 1439 */ 141, /* MMX_PHADDDrm */ }, { /* 1440 */ 142, /* MMX_PHADDDrr */ }, { /* 1441 */ 141, /* MMX_PHADDSWrm */ }, { /* 1442 */ 142, /* MMX_PHADDSWrr */ }, { /* 1443 */ 141, /* MMX_PHADDWrm */ }, { /* 1444 */ 142, /* MMX_PHADDWrr */ }, { /* 1445 */ 141, /* MMX_PHSUBDrm */ }, { /* 1446 */ 142, /* MMX_PHSUBDrr */ }, { /* 1447 */ 141, /* MMX_PHSUBSWrm */ }, { /* 1448 */ 142, /* MMX_PHSUBSWrr */ }, { /* 1449 */ 141, /* MMX_PHSUBWrm */ }, { /* 1450 */ 142, /* MMX_PHSUBWrr */ }, { /* 1451 */ 143, /* MMX_PINSRWrm */ }, { /* 1452 */ 146, /* MMX_PINSRWrr */ }, { /* 1453 */ 141, /* MMX_PMADDUBSWrm */ }, { /* 1454 */ 142, /* MMX_PMADDUBSWrr */ }, { /* 1455 */ 141, /* MMX_PMADDWDirm */ }, { /* 1456 */ 142, /* MMX_PMADDWDirr */ }, { /* 1457 */ 141, /* MMX_PMAXSWirm */ }, { /* 1458 */ 142, /* MMX_PMAXSWirr */ }, { /* 1459 */ 141, /* MMX_PMAXUBirm */ }, { /* 1460 */ 142, /* MMX_PMAXUBirr */ }, { /* 1461 */ 141, /* MMX_PMINSWirm */ }, { /* 1462 */ 142, /* MMX_PMINSWirr */ }, { /* 1463 */ 141, /* MMX_PMINUBirm */ }, { /* 1464 */ 142, /* MMX_PMINUBirr */ }, { /* 1465 */ 147, /* MMX_PMOVMSKBrr */ }, { /* 1466 */ 141, /* MMX_PMULHRSWrm */ }, { /* 1467 */ 142, /* MMX_PMULHRSWrr */ }, { /* 1468 */ 141, /* MMX_PMULHUWirm */ }, { /* 1469 */ 142, /* MMX_PMULHUWirr */ }, { /* 1470 */ 141, /* MMX_PMULHWirm */ }, { /* 1471 */ 142, /* MMX_PMULHWirr */ }, { /* 1472 */ 141, /* MMX_PMULLWirm */ }, { /* 1473 */ 142, /* MMX_PMULLWirr */ }, { /* 1474 */ 141, /* MMX_PMULUDQirm */ }, { /* 1475 */ 142, /* MMX_PMULUDQirr */ }, { /* 1476 */ 141, /* MMX_PORirm */ }, { /* 1477 */ 142, /* MMX_PORirr */ }, { /* 1478 */ 141, /* MMX_PSADBWirm */ }, { /* 1479 */ 142, /* MMX_PSADBWirr */ }, { /* 1480 */ 141, /* MMX_PSHUFBrm */ }, { /* 1481 */ 142, /* MMX_PSHUFBrr */ }, { /* 1482 */ 148, /* MMX_PSHUFWmi */ }, { /* 1483 */ 149, /* MMX_PSHUFWri */ }, { /* 1484 */ 141, /* MMX_PSIGNBrm */ }, { /* 1485 */ 142, /* MMX_PSIGNBrr */ }, { /* 1486 */ 141, /* MMX_PSIGNDrm */ }, { /* 1487 */ 142, /* MMX_PSIGNDrr */ }, { /* 1488 */ 141, /* MMX_PSIGNWrm */ }, { /* 1489 */ 142, /* MMX_PSIGNWrr */ }, { /* 1490 */ 150, /* MMX_PSLLDri */ }, { /* 1491 */ 141, /* MMX_PSLLDrm */ }, { /* 1492 */ 142, /* MMX_PSLLDrr */ }, { /* 1493 */ 150, /* MMX_PSLLQri */ }, { /* 1494 */ 141, /* MMX_PSLLQrm */ }, { /* 1495 */ 142, /* MMX_PSLLQrr */ }, { /* 1496 */ 150, /* MMX_PSLLWri */ }, { /* 1497 */ 141, /* MMX_PSLLWrm */ }, { /* 1498 */ 142, /* MMX_PSLLWrr */ }, { /* 1499 */ 150, /* MMX_PSRADri */ }, { /* 1500 */ 141, /* MMX_PSRADrm */ }, { /* 1501 */ 142, /* MMX_PSRADrr */ }, { /* 1502 */ 150, /* MMX_PSRAWri */ }, { /* 1503 */ 141, /* MMX_PSRAWrm */ }, { /* 1504 */ 142, /* MMX_PSRAWrr */ }, { /* 1505 */ 150, /* MMX_PSRLDri */ }, { /* 1506 */ 141, /* MMX_PSRLDrm */ }, { /* 1507 */ 142, /* MMX_PSRLDrr */ }, { /* 1508 */ 150, /* MMX_PSRLQri */ }, { /* 1509 */ 141, /* MMX_PSRLQrm */ }, { /* 1510 */ 142, /* MMX_PSRLQrr */ }, { /* 1511 */ 150, /* MMX_PSRLWri */ }, { /* 1512 */ 141, /* MMX_PSRLWrm */ }, { /* 1513 */ 142, /* MMX_PSRLWrr */ }, { /* 1514 */ 141, /* MMX_PSUBBirm */ }, { /* 1515 */ 142, /* MMX_PSUBBirr */ }, { /* 1516 */ 141, /* MMX_PSUBDirm */ }, { /* 1517 */ 142, /* MMX_PSUBDirr */ }, { /* 1518 */ 141, /* MMX_PSUBQirm */ }, { /* 1519 */ 142, /* MMX_PSUBQirr */ }, { /* 1520 */ 141, /* MMX_PSUBSBirm */ }, { /* 1521 */ 142, /* MMX_PSUBSBirr */ }, { /* 1522 */ 141, /* MMX_PSUBSWirm */ }, { /* 1523 */ 142, /* MMX_PSUBSWirr */ }, { /* 1524 */ 141, /* MMX_PSUBUSBirm */ }, { /* 1525 */ 142, /* MMX_PSUBUSBirr */ }, { /* 1526 */ 141, /* MMX_PSUBUSWirm */ }, { /* 1527 */ 142, /* MMX_PSUBUSWirr */ }, { /* 1528 */ 141, /* MMX_PSUBWirm */ }, { /* 1529 */ 142, /* MMX_PSUBWirr */ }, { /* 1530 */ 141, /* MMX_PUNPCKHBWirm */ }, { /* 1531 */ 142, /* MMX_PUNPCKHBWirr */ }, { /* 1532 */ 141, /* MMX_PUNPCKHDQirm */ }, { /* 1533 */ 142, /* MMX_PUNPCKHDQirr */ }, { /* 1534 */ 141, /* MMX_PUNPCKHWDirm */ }, { /* 1535 */ 142, /* MMX_PUNPCKHWDirr */ }, { /* 1536 */ 141, /* MMX_PUNPCKLBWirm */ }, { /* 1537 */ 142, /* MMX_PUNPCKLBWirr */ }, { /* 1538 */ 141, /* MMX_PUNPCKLDQirm */ }, { /* 1539 */ 142, /* MMX_PUNPCKLDQirr */ }, { /* 1540 */ 141, /* MMX_PUNPCKLWDirm */ }, { /* 1541 */ 142, /* MMX_PUNPCKLWDirr */ }, { /* 1542 */ 141, /* MMX_PXORirm */ }, { /* 1543 */ 142, /* MMX_PXORirr */ }, { /* 1544 */ 0, /* MONITORXrrr */ }, { /* 1545 */ 0, /* MONITORrrr */ }, { /* 1546 */ 0, /* MONTMUL */ }, { /* 1547 */ 151, /* MOV16ao16 */ }, { /* 1548 */ 151, /* MOV16ao32 */ }, { /* 1549 */ 151, /* MOV16ao64 */ }, { /* 1550 */ 3, /* MOV16mi */ }, { /* 1551 */ 5, /* MOV16mr */ }, { /* 1552 */ 152, /* MOV16ms */ }, { /* 1553 */ 151, /* MOV16o16a */ }, { /* 1554 */ 151, /* MOV16o32a */ }, { /* 1555 */ 151, /* MOV16o64a */ }, { /* 1556 */ 153, /* MOV16ri */ }, { /* 1557 */ 74, /* MOV16ri_alt */ }, { /* 1558 */ 60, /* MOV16rm */ }, { /* 1559 */ 67, /* MOV16rr */ }, { /* 1560 */ 61, /* MOV16rr_REV */ }, { /* 1561 */ 154, /* MOV16rs */ }, { /* 1562 */ 155, /* MOV16sm */ }, { /* 1563 */ 156, /* MOV16sr */ }, { /* 1564 */ 151, /* MOV32ao16 */ }, { /* 1565 */ 151, /* MOV32ao32 */ }, { /* 1566 */ 151, /* MOV32ao64 */ }, { /* 1567 */ 157, /* MOV32cr */ }, { /* 1568 */ 158, /* MOV32dr */ }, { /* 1569 */ 3, /* MOV32mi */ }, { /* 1570 */ 5, /* MOV32mr */ }, { /* 1571 */ 151, /* MOV32o16a */ }, { /* 1572 */ 151, /* MOV32o32a */ }, { /* 1573 */ 151, /* MOV32o64a */ }, { /* 1574 */ 159, /* MOV32rc */ }, { /* 1575 */ 160, /* MOV32rd */ }, { /* 1576 */ 153, /* MOV32ri */ }, { /* 1577 */ 74, /* MOV32ri_alt */ }, { /* 1578 */ 60, /* MOV32rm */ }, { /* 1579 */ 67, /* MOV32rr */ }, { /* 1580 */ 61, /* MOV32rr_REV */ }, { /* 1581 */ 154, /* MOV32rs */ }, { /* 1582 */ 156, /* MOV32sr */ }, { /* 1583 */ 151, /* MOV64ao32 */ }, { /* 1584 */ 151, /* MOV64ao64 */ }, { /* 1585 */ 161, /* MOV64cr */ }, { /* 1586 */ 162, /* MOV64dr */ }, { /* 1587 */ 12, /* MOV64mi32 */ }, { /* 1588 */ 13, /* MOV64mr */ }, { /* 1589 */ 151, /* MOV64o32a */ }, { /* 1590 */ 151, /* MOV64o64a */ }, { /* 1591 */ 163, /* MOV64rc */ }, { /* 1592 */ 164, /* MOV64rd */ }, { /* 1593 */ 165, /* MOV64ri */ }, { /* 1594 */ 75, /* MOV64ri32 */ }, { /* 1595 */ 62, /* MOV64rm */ }, { /* 1596 */ 69, /* MOV64rr */ }, { /* 1597 */ 63, /* MOV64rr_REV */ }, { /* 1598 */ 166, /* MOV64rs */ }, { /* 1599 */ 167, /* MOV64sr */ }, { /* 1600 */ 30, /* MOV64toPQIrm */ }, { /* 1601 */ 90, /* MOV64toPQIrr */ }, { /* 1602 */ 0, /* */ }, { /* 1603 */ 0, /* */ }, { /* 1604 */ 151, /* MOV8ao16 */ }, { /* 1605 */ 151, /* MOV8ao32 */ }, { /* 1606 */ 151, /* MOV8ao64 */ }, { /* 1607 */ 4, /* MOV8mi */ }, { /* 1608 */ 19, /* MOV8mr */ }, { /* 1609 */ 0, /* */ }, { /* 1610 */ 151, /* MOV8o16a */ }, { /* 1611 */ 151, /* MOV8o32a */ }, { /* 1612 */ 151, /* MOV8o64a */ }, { /* 1613 */ 168, /* MOV8ri */ }, { /* 1614 */ 76, /* MOV8ri_alt */ }, { /* 1615 */ 77, /* MOV8rm */ }, { /* 1616 */ 0, /* */ }, { /* 1617 */ 78, /* MOV8rr */ }, { /* 1618 */ 0, /* */ }, { /* 1619 */ 79, /* MOV8rr_REV */ }, { /* 1620 */ 169, /* MOVAPDmr */ }, { /* 1621 */ 30, /* MOVAPDrm */ }, { /* 1622 */ 31, /* MOVAPDrr */ }, { /* 1623 */ 170, /* MOVAPDrr_REV */ }, { /* 1624 */ 169, /* MOVAPSmr */ }, { /* 1625 */ 30, /* MOVAPSrm */ }, { /* 1626 */ 31, /* MOVAPSrr */ }, { /* 1627 */ 170, /* MOVAPSrr_REV */ }, { /* 1628 */ 5, /* MOVBE16mr */ }, { /* 1629 */ 60, /* MOVBE16rm */ }, { /* 1630 */ 5, /* MOVBE32mr */ }, { /* 1631 */ 60, /* MOVBE32rm */ }, { /* 1632 */ 13, /* MOVBE64mr */ }, { /* 1633 */ 62, /* MOVBE64rm */ }, { /* 1634 */ 30, /* MOVDDUPrm */ }, { /* 1635 */ 31, /* MOVDDUPrr */ }, { /* 1636 */ 30, /* MOVDI2PDIrm */ }, { /* 1637 */ 89, /* MOVDI2PDIrr */ }, { /* 1638 */ 0, /* */ }, { /* 1639 */ 0, /* */ }, { /* 1640 */ 171, /* MOVDIR64B16 */ }, { /* 1641 */ 87, /* MOVDIR64B32 */ }, { /* 1642 */ 62, /* MOVDIR64B64 */ }, { /* 1643 */ 172, /* MOVDIRI32 */ }, { /* 1644 */ 13, /* MOVDIRI64 */ }, { /* 1645 */ 169, /* MOVDQAmr */ }, { /* 1646 */ 30, /* MOVDQArm */ }, { /* 1647 */ 31, /* MOVDQArr */ }, { /* 1648 */ 170, /* MOVDQArr_REV */ }, { /* 1649 */ 169, /* MOVDQUmr */ }, { /* 1650 */ 30, /* MOVDQUrm */ }, { /* 1651 */ 31, /* MOVDQUrr */ }, { /* 1652 */ 170, /* MOVDQUrr_REV */ }, { /* 1653 */ 27, /* MOVHLPSrr */ }, { /* 1654 */ 169, /* MOVHPDmr */ }, { /* 1655 */ 26, /* MOVHPDrm */ }, { /* 1656 */ 169, /* MOVHPSmr */ }, { /* 1657 */ 26, /* MOVHPSrm */ }, { /* 1658 */ 27, /* MOVLHPSrr */ }, { /* 1659 */ 169, /* MOVLPDmr */ }, { /* 1660 */ 26, /* MOVLPDrm */ }, { /* 1661 */ 169, /* MOVLPSmr */ }, { /* 1662 */ 26, /* MOVLPSrm */ }, { /* 1663 */ 88, /* MOVMSKPDrr */ }, { /* 1664 */ 88, /* MOVMSKPSrr */ }, { /* 1665 */ 30, /* MOVNTDQArm */ }, { /* 1666 */ 169, /* MOVNTDQmr */ }, { /* 1667 */ 13, /* MOVNTI_64mr */ }, { /* 1668 */ 172, /* MOVNTImr */ }, { /* 1669 */ 169, /* MOVNTPDmr */ }, { /* 1670 */ 169, /* MOVNTPSmr */ }, { /* 1671 */ 169, /* MOVNTSD */ }, { /* 1672 */ 169, /* MOVNTSS */ }, { /* 1673 */ 169, /* MOVPDI2DImr */ }, { /* 1674 */ 173, /* MOVPDI2DIrr */ }, { /* 1675 */ 169, /* MOVPQI2QImr */ }, { /* 1676 */ 170, /* MOVPQI2QIrr */ }, { /* 1677 */ 169, /* MOVPQIto64mr */ }, { /* 1678 */ 174, /* MOVPQIto64rr */ }, { /* 1679 */ 30, /* MOVQI2PQIrm */ }, { /* 1680 */ 82, /* MOVSB */ }, { /* 1681 */ 169, /* MOVSDmr */ }, { /* 1682 */ 30, /* MOVSDrm */ }, { /* 1683 */ 27, /* MOVSDrr */ }, { /* 1684 */ 175, /* MOVSDrr_REV */ }, { /* 1685 */ 0, /* */ }, { /* 1686 */ 0, /* */ }, { /* 1687 */ 30, /* MOVSHDUPrm */ }, { /* 1688 */ 31, /* MOVSHDUPrr */ }, { /* 1689 */ 82, /* MOVSL */ }, { /* 1690 */ 30, /* MOVSLDUPrm */ }, { /* 1691 */ 31, /* MOVSLDUPrr */ }, { /* 1692 */ 82, /* MOVSQ */ }, { /* 1693 */ 0, /* */ }, { /* 1694 */ 0, /* */ }, { /* 1695 */ 169, /* MOVSSmr */ }, { /* 1696 */ 30, /* MOVSSrm */ }, { /* 1697 */ 27, /* MOVSSrr */ }, { /* 1698 */ 175, /* MOVSSrr_REV */ }, { /* 1699 */ 82, /* MOVSW */ }, { /* 1700 */ 60, /* MOVSX16rm16 */ }, { /* 1701 */ 60, /* MOVSX16rm8 */ }, { /* 1702 */ 61, /* MOVSX16rr16 */ }, { /* 1703 */ 176, /* MOVSX16rr8 */ }, { /* 1704 */ 60, /* MOVSX32rm16 */ }, { /* 1705 */ 60, /* MOVSX32rm8 */ }, { /* 1706 */ 0, /* */ }, { /* 1707 */ 177, /* MOVSX32rr16 */ }, { /* 1708 */ 176, /* MOVSX32rr8 */ }, { /* 1709 */ 0, /* */ }, { /* 1710 */ 62, /* MOVSX64rm16 */ }, { /* 1711 */ 62, /* MOVSX64rm32 */ }, { /* 1712 */ 62, /* MOVSX64rm8 */ }, { /* 1713 */ 178, /* MOVSX64rr16 */ }, { /* 1714 */ 122, /* MOVSX64rr32 */ }, { /* 1715 */ 179, /* MOVSX64rr8 */ }, { /* 1716 */ 169, /* MOVUPDmr */ }, { /* 1717 */ 30, /* MOVUPDrm */ }, { /* 1718 */ 31, /* MOVUPDrr */ }, { /* 1719 */ 170, /* MOVUPDrr_REV */ }, { /* 1720 */ 169, /* MOVUPSmr */ }, { /* 1721 */ 30, /* MOVUPSrm */ }, { /* 1722 */ 31, /* MOVUPSrr */ }, { /* 1723 */ 170, /* MOVUPSrr_REV */ }, { /* 1724 */ 31, /* MOVZPQILo2PQIrr */ }, { /* 1725 */ 60, /* MOVZX16rm16 */ }, { /* 1726 */ 60, /* MOVZX16rm8 */ }, { /* 1727 */ 61, /* MOVZX16rr16 */ }, { /* 1728 */ 176, /* MOVZX16rr8 */ }, { /* 1729 */ 60, /* MOVZX32rm16 */ }, { /* 1730 */ 60, /* MOVZX32rm8 */ }, { /* 1731 */ 0, /* */ }, { /* 1732 */ 177, /* MOVZX32rr16 */ }, { /* 1733 */ 176, /* MOVZX32rr8 */ }, { /* 1734 */ 0, /* */ }, { /* 1735 */ 62, /* MOVZX64rm16 */ }, { /* 1736 */ 62, /* MOVZX64rm8 */ }, { /* 1737 */ 178, /* MOVZX64rr16 */ }, { /* 1738 */ 179, /* MOVZX64rr8 */ }, { /* 1739 */ 52, /* MPSADBWrmi */ }, { /* 1740 */ 53, /* MPSADBWrri */ }, { /* 1741 */ 28, /* MUL16m */ }, { /* 1742 */ 70, /* MUL16r */ }, { /* 1743 */ 28, /* MUL32m */ }, { /* 1744 */ 70, /* MUL32r */ }, { /* 1745 */ 28, /* MUL64m */ }, { /* 1746 */ 72, /* MUL64r */ }, { /* 1747 */ 28, /* MUL8m */ }, { /* 1748 */ 94, /* MUL8r */ }, { /* 1749 */ 26, /* MULPDrm */ }, { /* 1750 */ 27, /* MULPDrr */ }, { /* 1751 */ 26, /* MULPSrm */ }, { /* 1752 */ 27, /* MULPSrr */ }, { /* 1753 */ 26, /* MULSDrm */ }, { /* 1754 */ 0, /* */ }, { /* 1755 */ 27, /* MULSDrr */ }, { /* 1756 */ 0, /* */ }, { /* 1757 */ 26, /* MULSSrm */ }, { /* 1758 */ 0, /* */ }, { /* 1759 */ 27, /* MULSSrr */ }, { /* 1760 */ 0, /* */ }, { /* 1761 */ 34, /* MULX32rm */ }, { /* 1762 */ 35, /* MULX32rr */ }, { /* 1763 */ 36, /* MULX64rm */ }, { /* 1764 */ 37, /* MULX64rr */ }, { /* 1765 */ 28, /* MUL_F32m */ }, { /* 1766 */ 28, /* MUL_F64m */ }, { /* 1767 */ 28, /* MUL_FI16m */ }, { /* 1768 */ 28, /* MUL_FI32m */ }, { /* 1769 */ 29, /* MUL_FPrST0 */ }, { /* 1770 */ 29, /* MUL_FST0r */ }, { /* 1771 */ 0, /* */ }, { /* 1772 */ 0, /* */ }, { /* 1773 */ 0, /* */ }, { /* 1774 */ 0, /* */ }, { /* 1775 */ 0, /* */ }, { /* 1776 */ 0, /* */ }, { /* 1777 */ 0, /* */ }, { /* 1778 */ 0, /* */ }, { /* 1779 */ 0, /* */ }, { /* 1780 */ 0, /* */ }, { /* 1781 */ 0, /* */ }, { /* 1782 */ 0, /* */ }, { /* 1783 */ 0, /* */ }, { /* 1784 */ 0, /* */ }, { /* 1785 */ 29, /* MUL_FrST0 */ }, { /* 1786 */ 0, /* MWAITXrrr */ }, { /* 1787 */ 0, /* MWAITrr */ }, { /* 1788 */ 28, /* NEG16m */ }, { /* 1789 */ 91, /* NEG16r */ }, { /* 1790 */ 28, /* NEG32m */ }, { /* 1791 */ 91, /* NEG32r */ }, { /* 1792 */ 28, /* NEG64m */ }, { /* 1793 */ 92, /* NEG64r */ }, { /* 1794 */ 28, /* NEG8m */ }, { /* 1795 */ 93, /* NEG8r */ }, { /* 1796 */ 0, /* NOOP */ }, { /* 1797 */ 28, /* NOOP18_16m4 */ }, { /* 1798 */ 28, /* NOOP18_16m5 */ }, { /* 1799 */ 28, /* NOOP18_16m6 */ }, { /* 1800 */ 28, /* NOOP18_16m7 */ }, { /* 1801 */ 70, /* NOOP18_16r4 */ }, { /* 1802 */ 70, /* NOOP18_16r5 */ }, { /* 1803 */ 70, /* NOOP18_16r6 */ }, { /* 1804 */ 70, /* NOOP18_16r7 */ }, { /* 1805 */ 28, /* NOOP18_m4 */ }, { /* 1806 */ 28, /* NOOP18_m5 */ }, { /* 1807 */ 28, /* NOOP18_m6 */ }, { /* 1808 */ 28, /* NOOP18_m7 */ }, { /* 1809 */ 70, /* NOOP18_r4 */ }, { /* 1810 */ 70, /* NOOP18_r5 */ }, { /* 1811 */ 70, /* NOOP18_r6 */ }, { /* 1812 */ 70, /* NOOP18_r7 */ }, { /* 1813 */ 61, /* NOOP19rr */ }, { /* 1814 */ 28, /* NOOPL */ }, { /* 1815 */ 28, /* NOOPL_19 */ }, { /* 1816 */ 28, /* NOOPL_1d */ }, { /* 1817 */ 28, /* NOOPL_1e */ }, { /* 1818 */ 70, /* NOOPLr */ }, { /* 1819 */ 28, /* NOOPQ */ }, { /* 1820 */ 72, /* NOOPQr */ }, { /* 1821 */ 28, /* NOOPW */ }, { /* 1822 */ 28, /* NOOPW_19 */ }, { /* 1823 */ 28, /* NOOPW_1c */ }, { /* 1824 */ 28, /* NOOPW_1d */ }, { /* 1825 */ 28, /* NOOPW_1e */ }, { /* 1826 */ 70, /* NOOPWr */ }, { /* 1827 */ 28, /* NOT16m */ }, { /* 1828 */ 91, /* NOT16r */ }, { /* 1829 */ 28, /* NOT32m */ }, { /* 1830 */ 91, /* NOT32r */ }, { /* 1831 */ 28, /* NOT64m */ }, { /* 1832 */ 92, /* NOT64r */ }, { /* 1833 */ 28, /* NOT8m */ }, { /* 1834 */ 93, /* NOT8r */ }, { /* 1835 */ 2, /* OR16i16 */ }, { /* 1836 */ 3, /* OR16mi */ }, { /* 1837 */ 4, /* OR16mi8 */ }, { /* 1838 */ 5, /* OR16mr */ }, { /* 1839 */ 6, /* OR16ri */ }, { /* 1840 */ 7, /* OR16ri8 */ }, { /* 1841 */ 8, /* OR16rm */ }, { /* 1842 */ 9, /* OR16rr */ }, { /* 1843 */ 10, /* OR16rr_REV */ }, { /* 1844 */ 2, /* OR32i32 */ }, { /* 1845 */ 3, /* OR32mi */ }, { /* 1846 */ 4, /* OR32mi8 */ }, { /* 1847 */ 5, /* OR32mr */ }, { /* 1848 */ 6, /* OR32ri */ }, { /* 1849 */ 7, /* OR32ri8 */ }, { /* 1850 */ 8, /* OR32rm */ }, { /* 1851 */ 9, /* OR32rr */ }, { /* 1852 */ 10, /* OR32rr_REV */ }, { /* 1853 */ 11, /* OR64i32 */ }, { /* 1854 */ 12, /* OR64mi32 */ }, { /* 1855 */ 4, /* OR64mi8 */ }, { /* 1856 */ 13, /* OR64mr */ }, { /* 1857 */ 14, /* OR64ri32 */ }, { /* 1858 */ 15, /* OR64ri8 */ }, { /* 1859 */ 16, /* OR64rm */ }, { /* 1860 */ 17, /* OR64rr */ }, { /* 1861 */ 18, /* OR64rr_REV */ }, { /* 1862 */ 1, /* OR8i8 */ }, { /* 1863 */ 4, /* OR8mi */ }, { /* 1864 */ 4, /* OR8mi8 */ }, { /* 1865 */ 19, /* OR8mr */ }, { /* 1866 */ 20, /* OR8ri */ }, { /* 1867 */ 20, /* OR8ri8 */ }, { /* 1868 */ 21, /* OR8rm */ }, { /* 1869 */ 22, /* OR8rr */ }, { /* 1870 */ 23, /* OR8rr_REV */ }, { /* 1871 */ 26, /* ORPDrm */ }, { /* 1872 */ 27, /* ORPDrr */ }, { /* 1873 */ 26, /* ORPSrm */ }, { /* 1874 */ 27, /* ORPSrr */ }, { /* 1875 */ 107, /* OUT16ir */ }, { /* 1876 */ 0, /* OUT16rr */ }, { /* 1877 */ 107, /* OUT32ir */ }, { /* 1878 */ 0, /* OUT32rr */ }, { /* 1879 */ 107, /* OUT8ir */ }, { /* 1880 */ 0, /* OUT8rr */ }, { /* 1881 */ 124, /* OUTSB */ }, { /* 1882 */ 124, /* OUTSL */ }, { /* 1883 */ 124, /* OUTSW */ }, { /* 1884 */ 30, /* PABSBrm */ }, { /* 1885 */ 31, /* PABSBrr */ }, { /* 1886 */ 30, /* PABSDrm */ }, { /* 1887 */ 31, /* PABSDrr */ }, { /* 1888 */ 30, /* PABSWrm */ }, { /* 1889 */ 31, /* PABSWrr */ }, { /* 1890 */ 26, /* PACKSSDWrm */ }, { /* 1891 */ 27, /* PACKSSDWrr */ }, { /* 1892 */ 26, /* PACKSSWBrm */ }, { /* 1893 */ 27, /* PACKSSWBrr */ }, { /* 1894 */ 26, /* PACKUSDWrm */ }, { /* 1895 */ 27, /* PACKUSDWrr */ }, { /* 1896 */ 26, /* PACKUSWBrm */ }, { /* 1897 */ 27, /* PACKUSWBrr */ }, { /* 1898 */ 26, /* PADDBrm */ }, { /* 1899 */ 27, /* PADDBrr */ }, { /* 1900 */ 26, /* PADDDrm */ }, { /* 1901 */ 27, /* PADDDrr */ }, { /* 1902 */ 26, /* PADDQrm */ }, { /* 1903 */ 27, /* PADDQrr */ }, { /* 1904 */ 26, /* PADDSBrm */ }, { /* 1905 */ 27, /* PADDSBrr */ }, { /* 1906 */ 26, /* PADDSWrm */ }, { /* 1907 */ 27, /* PADDSWrr */ }, { /* 1908 */ 26, /* PADDUSBrm */ }, { /* 1909 */ 27, /* PADDUSBrr */ }, { /* 1910 */ 26, /* PADDUSWrm */ }, { /* 1911 */ 27, /* PADDUSWrr */ }, { /* 1912 */ 26, /* PADDWrm */ }, { /* 1913 */ 27, /* PADDWrr */ }, { /* 1914 */ 52, /* PALIGNRrmi */ }, { /* 1915 */ 53, /* PALIGNRrri */ }, { /* 1916 */ 26, /* PANDNrm */ }, { /* 1917 */ 27, /* PANDNrr */ }, { /* 1918 */ 26, /* PANDrm */ }, { /* 1919 */ 27, /* PANDrr */ }, { /* 1920 */ 0, /* PAUSE */ }, { /* 1921 */ 26, /* PAVGBrm */ }, { /* 1922 */ 27, /* PAVGBrr */ }, { /* 1923 */ 141, /* PAVGUSBrm */ }, { /* 1924 */ 142, /* PAVGUSBrr */ }, { /* 1925 */ 26, /* PAVGWrm */ }, { /* 1926 */ 27, /* PAVGWrr */ }, { /* 1927 */ 26, /* PBLENDVBrm0 */ }, { /* 1928 */ 27, /* PBLENDVBrr0 */ }, { /* 1929 */ 52, /* PBLENDWrmi */ }, { /* 1930 */ 53, /* PBLENDWrri */ }, { /* 1931 */ 52, /* PCLMULQDQrm */ }, { /* 1932 */ 53, /* PCLMULQDQrr */ }, { /* 1933 */ 26, /* PCMPEQBrm */ }, { /* 1934 */ 27, /* PCMPEQBrr */ }, { /* 1935 */ 26, /* PCMPEQDrm */ }, { /* 1936 */ 27, /* PCMPEQDrr */ }, { /* 1937 */ 26, /* PCMPEQQrm */ }, { /* 1938 */ 27, /* PCMPEQQrr */ }, { /* 1939 */ 26, /* PCMPEQWrm */ }, { /* 1940 */ 27, /* PCMPEQWrr */ }, { /* 1941 */ 32, /* PCMPESTRIrm */ }, { /* 1942 */ 33, /* PCMPESTRIrr */ }, { /* 1943 */ 32, /* PCMPESTRMrm */ }, { /* 1944 */ 33, /* PCMPESTRMrr */ }, { /* 1945 */ 26, /* PCMPGTBrm */ }, { /* 1946 */ 27, /* PCMPGTBrr */ }, { /* 1947 */ 26, /* PCMPGTDrm */ }, { /* 1948 */ 27, /* PCMPGTDrr */ }, { /* 1949 */ 26, /* PCMPGTQrm */ }, { /* 1950 */ 27, /* PCMPGTQrr */ }, { /* 1951 */ 26, /* PCMPGTWrm */ }, { /* 1952 */ 27, /* PCMPGTWrr */ }, { /* 1953 */ 32, /* PCMPISTRIrm */ }, { /* 1954 */ 33, /* PCMPISTRIrr */ }, { /* 1955 */ 32, /* PCMPISTRMrm */ }, { /* 1956 */ 33, /* PCMPISTRMrr */ }, { /* 1957 */ 0, /* PCONFIG */ }, { /* 1958 */ 34, /* PDEP32rm */ }, { /* 1959 */ 35, /* PDEP32rr */ }, { /* 1960 */ 36, /* PDEP64rm */ }, { /* 1961 */ 37, /* PDEP64rr */ }, { /* 1962 */ 34, /* PEXT32rm */ }, { /* 1963 */ 35, /* PEXT32rr */ }, { /* 1964 */ 36, /* PEXT64rm */ }, { /* 1965 */ 37, /* PEXT64rr */ }, { /* 1966 */ 96, /* PEXTRBmr */ }, { /* 1967 */ 97, /* PEXTRBrr */ }, { /* 1968 */ 96, /* PEXTRDmr */ }, { /* 1969 */ 97, /* PEXTRDrr */ }, { /* 1970 */ 96, /* PEXTRQmr */ }, { /* 1971 */ 180, /* PEXTRQrr */ }, { /* 1972 */ 96, /* PEXTRWmr */ }, { /* 1973 */ 181, /* PEXTRWrr */ }, { /* 1974 */ 97, /* PEXTRWrr_REV */ }, { /* 1975 */ 130, /* PF2IDrm */ }, { /* 1976 */ 134, /* PF2IDrr */ }, { /* 1977 */ 130, /* PF2IWrm */ }, { /* 1978 */ 134, /* PF2IWrr */ }, { /* 1979 */ 141, /* PFACCrm */ }, { /* 1980 */ 142, /* PFACCrr */ }, { /* 1981 */ 141, /* PFADDrm */ }, { /* 1982 */ 142, /* PFADDrr */ }, { /* 1983 */ 141, /* PFCMPEQrm */ }, { /* 1984 */ 142, /* PFCMPEQrr */ }, { /* 1985 */ 141, /* PFCMPGErm */ }, { /* 1986 */ 142, /* PFCMPGErr */ }, { /* 1987 */ 141, /* PFCMPGTrm */ }, { /* 1988 */ 142, /* PFCMPGTrr */ }, { /* 1989 */ 141, /* PFMAXrm */ }, { /* 1990 */ 142, /* PFMAXrr */ }, { /* 1991 */ 141, /* PFMINrm */ }, { /* 1992 */ 142, /* PFMINrr */ }, { /* 1993 */ 141, /* PFMULrm */ }, { /* 1994 */ 142, /* PFMULrr */ }, { /* 1995 */ 141, /* PFNACCrm */ }, { /* 1996 */ 142, /* PFNACCrr */ }, { /* 1997 */ 141, /* PFPNACCrm */ }, { /* 1998 */ 142, /* PFPNACCrr */ }, { /* 1999 */ 141, /* PFRCPIT1rm */ }, { /* 2000 */ 142, /* PFRCPIT1rr */ }, { /* 2001 */ 141, /* PFRCPIT2rm */ }, { /* 2002 */ 142, /* PFRCPIT2rr */ }, { /* 2003 */ 130, /* PFRCPrm */ }, { /* 2004 */ 134, /* PFRCPrr */ }, { /* 2005 */ 141, /* PFRSQIT1rm */ }, { /* 2006 */ 142, /* PFRSQIT1rr */ }, { /* 2007 */ 130, /* PFRSQRTrm */ }, { /* 2008 */ 134, /* PFRSQRTrr */ }, { /* 2009 */ 141, /* PFSUBRrm */ }, { /* 2010 */ 142, /* PFSUBRrr */ }, { /* 2011 */ 141, /* PFSUBrm */ }, { /* 2012 */ 142, /* PFSUBrr */ }, { /* 2013 */ 26, /* PHADDDrm */ }, { /* 2014 */ 27, /* PHADDDrr */ }, { /* 2015 */ 26, /* PHADDSWrm */ }, { /* 2016 */ 27, /* PHADDSWrr */ }, { /* 2017 */ 26, /* PHADDWrm */ }, { /* 2018 */ 27, /* PHADDWrr */ }, { /* 2019 */ 30, /* PHMINPOSUWrm */ }, { /* 2020 */ 31, /* PHMINPOSUWrr */ }, { /* 2021 */ 26, /* PHSUBDrm */ }, { /* 2022 */ 27, /* PHSUBDrr */ }, { /* 2023 */ 26, /* PHSUBSWrm */ }, { /* 2024 */ 27, /* PHSUBSWrr */ }, { /* 2025 */ 26, /* PHSUBWrm */ }, { /* 2026 */ 27, /* PHSUBWrr */ }, { /* 2027 */ 130, /* PI2FDrm */ }, { /* 2028 */ 134, /* PI2FDrr */ }, { /* 2029 */ 130, /* PI2FWrm */ }, { /* 2030 */ 134, /* PI2FWrr */ }, { /* 2031 */ 52, /* PINSRBrm */ }, { /* 2032 */ 182, /* PINSRBrr */ }, { /* 2033 */ 52, /* PINSRDrm */ }, { /* 2034 */ 182, /* PINSRDrr */ }, { /* 2035 */ 52, /* PINSRQrm */ }, { /* 2036 */ 183, /* PINSRQrr */ }, { /* 2037 */ 52, /* PINSRWrm */ }, { /* 2038 */ 182, /* PINSRWrr */ }, { /* 2039 */ 26, /* PMADDUBSWrm */ }, { /* 2040 */ 27, /* PMADDUBSWrr */ }, { /* 2041 */ 26, /* PMADDWDrm */ }, { /* 2042 */ 27, /* PMADDWDrr */ }, { /* 2043 */ 26, /* PMAXSBrm */ }, { /* 2044 */ 27, /* PMAXSBrr */ }, { /* 2045 */ 26, /* PMAXSDrm */ }, { /* 2046 */ 27, /* PMAXSDrr */ }, { /* 2047 */ 26, /* PMAXSWrm */ }, { /* 2048 */ 27, /* PMAXSWrr */ }, { /* 2049 */ 26, /* PMAXUBrm */ }, { /* 2050 */ 27, /* PMAXUBrr */ }, { /* 2051 */ 26, /* PMAXUDrm */ }, { /* 2052 */ 27, /* PMAXUDrr */ }, { /* 2053 */ 26, /* PMAXUWrm */ }, { /* 2054 */ 27, /* PMAXUWrr */ }, { /* 2055 */ 26, /* PMINSBrm */ }, { /* 2056 */ 27, /* PMINSBrr */ }, { /* 2057 */ 26, /* PMINSDrm */ }, { /* 2058 */ 27, /* PMINSDrr */ }, { /* 2059 */ 26, /* PMINSWrm */ }, { /* 2060 */ 27, /* PMINSWrr */ }, { /* 2061 */ 26, /* PMINUBrm */ }, { /* 2062 */ 27, /* PMINUBrr */ }, { /* 2063 */ 26, /* PMINUDrm */ }, { /* 2064 */ 27, /* PMINUDrr */ }, { /* 2065 */ 26, /* PMINUWrm */ }, { /* 2066 */ 27, /* PMINUWrr */ }, { /* 2067 */ 88, /* PMOVMSKBrr */ }, { /* 2068 */ 30, /* PMOVSXBDrm */ }, { /* 2069 */ 31, /* PMOVSXBDrr */ }, { /* 2070 */ 30, /* PMOVSXBQrm */ }, { /* 2071 */ 31, /* PMOVSXBQrr */ }, { /* 2072 */ 30, /* PMOVSXBWrm */ }, { /* 2073 */ 31, /* PMOVSXBWrr */ }, { /* 2074 */ 30, /* PMOVSXDQrm */ }, { /* 2075 */ 31, /* PMOVSXDQrr */ }, { /* 2076 */ 30, /* PMOVSXWDrm */ }, { /* 2077 */ 31, /* PMOVSXWDrr */ }, { /* 2078 */ 30, /* PMOVSXWQrm */ }, { /* 2079 */ 31, /* PMOVSXWQrr */ }, { /* 2080 */ 30, /* PMOVZXBDrm */ }, { /* 2081 */ 31, /* PMOVZXBDrr */ }, { /* 2082 */ 30, /* PMOVZXBQrm */ }, { /* 2083 */ 31, /* PMOVZXBQrr */ }, { /* 2084 */ 30, /* PMOVZXBWrm */ }, { /* 2085 */ 31, /* PMOVZXBWrr */ }, { /* 2086 */ 30, /* PMOVZXDQrm */ }, { /* 2087 */ 31, /* PMOVZXDQrr */ }, { /* 2088 */ 30, /* PMOVZXWDrm */ }, { /* 2089 */ 31, /* PMOVZXWDrr */ }, { /* 2090 */ 30, /* PMOVZXWQrm */ }, { /* 2091 */ 31, /* PMOVZXWQrr */ }, { /* 2092 */ 26, /* PMULDQrm */ }, { /* 2093 */ 27, /* PMULDQrr */ }, { /* 2094 */ 26, /* PMULHRSWrm */ }, { /* 2095 */ 27, /* PMULHRSWrr */ }, { /* 2096 */ 141, /* PMULHRWrm */ }, { /* 2097 */ 142, /* PMULHRWrr */ }, { /* 2098 */ 26, /* PMULHUWrm */ }, { /* 2099 */ 27, /* PMULHUWrr */ }, { /* 2100 */ 26, /* PMULHWrm */ }, { /* 2101 */ 27, /* PMULHWrr */ }, { /* 2102 */ 26, /* PMULLDrm */ }, { /* 2103 */ 27, /* PMULLDrr */ }, { /* 2104 */ 26, /* PMULLWrm */ }, { /* 2105 */ 27, /* PMULLWrr */ }, { /* 2106 */ 26, /* PMULUDQrm */ }, { /* 2107 */ 27, /* PMULUDQrr */ }, { /* 2108 */ 184, /* POP16r */ }, { /* 2109 */ 28, /* POP16rmm */ }, { /* 2110 */ 70, /* POP16rmr */ }, { /* 2111 */ 184, /* POP32r */ }, { /* 2112 */ 28, /* POP32rmm */ }, { /* 2113 */ 70, /* POP32rmr */ }, { /* 2114 */ 185, /* POP64r */ }, { /* 2115 */ 28, /* POP64rmm */ }, { /* 2116 */ 72, /* POP64rmr */ }, { /* 2117 */ 0, /* POPA16 */ }, { /* 2118 */ 0, /* POPA32 */ }, { /* 2119 */ 60, /* POPCNT16rm */ }, { /* 2120 */ 61, /* POPCNT16rr */ }, { /* 2121 */ 60, /* POPCNT32rm */ }, { /* 2122 */ 61, /* POPCNT32rr */ }, { /* 2123 */ 62, /* POPCNT64rm */ }, { /* 2124 */ 63, /* POPCNT64rr */ }, { /* 2125 */ 0, /* POPDS16 */ }, { /* 2126 */ 0, /* POPDS32 */ }, { /* 2127 */ 0, /* POPES16 */ }, { /* 2128 */ 0, /* POPES32 */ }, { /* 2129 */ 0, /* POPF16 */ }, { /* 2130 */ 0, /* POPF32 */ }, { /* 2131 */ 0, /* POPF64 */ }, { /* 2132 */ 0, /* POPFS16 */ }, { /* 2133 */ 0, /* POPFS32 */ }, { /* 2134 */ 0, /* POPFS64 */ }, { /* 2135 */ 0, /* POPGS16 */ }, { /* 2136 */ 0, /* POPGS32 */ }, { /* 2137 */ 0, /* POPGS64 */ }, { /* 2138 */ 0, /* POPSS16 */ }, { /* 2139 */ 0, /* POPSS32 */ }, { /* 2140 */ 26, /* PORrm */ }, { /* 2141 */ 27, /* PORrr */ }, { /* 2142 */ 28, /* PREFETCH */ }, { /* 2143 */ 28, /* PREFETCHNTA */ }, { /* 2144 */ 28, /* PREFETCHT0 */ }, { /* 2145 */ 28, /* PREFETCHT1 */ }, { /* 2146 */ 28, /* PREFETCHT2 */ }, { /* 2147 */ 28, /* PREFETCHW */ }, { /* 2148 */ 28, /* PREFETCHWT1 */ }, { /* 2149 */ 26, /* PSADBWrm */ }, { /* 2150 */ 27, /* PSADBWrr */ }, { /* 2151 */ 26, /* PSHUFBrm */ }, { /* 2152 */ 27, /* PSHUFBrr */ }, { /* 2153 */ 32, /* PSHUFDmi */ }, { /* 2154 */ 33, /* PSHUFDri */ }, { /* 2155 */ 32, /* PSHUFHWmi */ }, { /* 2156 */ 33, /* PSHUFHWri */ }, { /* 2157 */ 32, /* PSHUFLWmi */ }, { /* 2158 */ 33, /* PSHUFLWri */ }, { /* 2159 */ 26, /* PSIGNBrm */ }, { /* 2160 */ 27, /* PSIGNBrr */ }, { /* 2161 */ 26, /* PSIGNDrm */ }, { /* 2162 */ 27, /* PSIGNDrr */ }, { /* 2163 */ 26, /* PSIGNWrm */ }, { /* 2164 */ 27, /* PSIGNWrr */ }, { /* 2165 */ 186, /* PSLLDQri */ }, { /* 2166 */ 186, /* PSLLDri */ }, { /* 2167 */ 26, /* PSLLDrm */ }, { /* 2168 */ 27, /* PSLLDrr */ }, { /* 2169 */ 186, /* PSLLQri */ }, { /* 2170 */ 26, /* PSLLQrm */ }, { /* 2171 */ 27, /* PSLLQrr */ }, { /* 2172 */ 186, /* PSLLWri */ }, { /* 2173 */ 26, /* PSLLWrm */ }, { /* 2174 */ 27, /* PSLLWrr */ }, { /* 2175 */ 186, /* PSRADri */ }, { /* 2176 */ 26, /* PSRADrm */ }, { /* 2177 */ 27, /* PSRADrr */ }, { /* 2178 */ 186, /* PSRAWri */ }, { /* 2179 */ 26, /* PSRAWrm */ }, { /* 2180 */ 27, /* PSRAWrr */ }, { /* 2181 */ 186, /* PSRLDQri */ }, { /* 2182 */ 186, /* PSRLDri */ }, { /* 2183 */ 26, /* PSRLDrm */ }, { /* 2184 */ 27, /* PSRLDrr */ }, { /* 2185 */ 186, /* PSRLQri */ }, { /* 2186 */ 26, /* PSRLQrm */ }, { /* 2187 */ 27, /* PSRLQrr */ }, { /* 2188 */ 186, /* PSRLWri */ }, { /* 2189 */ 26, /* PSRLWrm */ }, { /* 2190 */ 27, /* PSRLWrr */ }, { /* 2191 */ 26, /* PSUBBrm */ }, { /* 2192 */ 27, /* PSUBBrr */ }, { /* 2193 */ 26, /* PSUBDrm */ }, { /* 2194 */ 27, /* PSUBDrr */ }, { /* 2195 */ 26, /* PSUBQrm */ }, { /* 2196 */ 27, /* PSUBQrr */ }, { /* 2197 */ 26, /* PSUBSBrm */ }, { /* 2198 */ 27, /* PSUBSBrr */ }, { /* 2199 */ 26, /* PSUBSWrm */ }, { /* 2200 */ 27, /* PSUBSWrr */ }, { /* 2201 */ 26, /* PSUBUSBrm */ }, { /* 2202 */ 27, /* PSUBUSBrr */ }, { /* 2203 */ 26, /* PSUBUSWrm */ }, { /* 2204 */ 27, /* PSUBUSWrr */ }, { /* 2205 */ 26, /* PSUBWrm */ }, { /* 2206 */ 27, /* PSUBWrr */ }, { /* 2207 */ 130, /* PSWAPDrm */ }, { /* 2208 */ 134, /* PSWAPDrr */ }, { /* 2209 */ 30, /* PTESTrm */ }, { /* 2210 */ 31, /* PTESTrr */ }, { /* 2211 */ 28, /* PTWRITE64m */ }, { /* 2212 */ 72, /* PTWRITE64r */ }, { /* 2213 */ 28, /* PTWRITEm */ }, { /* 2214 */ 108, /* PTWRITEr */ }, { /* 2215 */ 26, /* PUNPCKHBWrm */ }, { /* 2216 */ 27, /* PUNPCKHBWrr */ }, { /* 2217 */ 26, /* PUNPCKHDQrm */ }, { /* 2218 */ 27, /* PUNPCKHDQrr */ }, { /* 2219 */ 26, /* PUNPCKHQDQrm */ }, { /* 2220 */ 27, /* PUNPCKHQDQrr */ }, { /* 2221 */ 26, /* PUNPCKHWDrm */ }, { /* 2222 */ 27, /* PUNPCKHWDrr */ }, { /* 2223 */ 26, /* PUNPCKLBWrm */ }, { /* 2224 */ 27, /* PUNPCKLBWrr */ }, { /* 2225 */ 26, /* PUNPCKLDQrm */ }, { /* 2226 */ 27, /* PUNPCKLDQrr */ }, { /* 2227 */ 26, /* PUNPCKLQDQrm */ }, { /* 2228 */ 27, /* PUNPCKLQDQrr */ }, { /* 2229 */ 26, /* PUNPCKLWDrm */ }, { /* 2230 */ 27, /* PUNPCKLWDrr */ }, { /* 2231 */ 1, /* PUSH16i8 */ }, { /* 2232 */ 184, /* PUSH16r */ }, { /* 2233 */ 28, /* PUSH16rmm */ }, { /* 2234 */ 70, /* PUSH16rmr */ }, { /* 2235 */ 1, /* PUSH32i8 */ }, { /* 2236 */ 184, /* PUSH32r */ }, { /* 2237 */ 28, /* PUSH32rmm */ }, { /* 2238 */ 70, /* PUSH32rmr */ }, { /* 2239 */ 11, /* PUSH64i32 */ }, { /* 2240 */ 1, /* PUSH64i8 */ }, { /* 2241 */ 185, /* PUSH64r */ }, { /* 2242 */ 28, /* PUSH64rmm */ }, { /* 2243 */ 72, /* PUSH64rmr */ }, { /* 2244 */ 0, /* PUSHA16 */ }, { /* 2245 */ 0, /* PUSHA32 */ }, { /* 2246 */ 0, /* PUSHCS16 */ }, { /* 2247 */ 0, /* PUSHCS32 */ }, { /* 2248 */ 0, /* PUSHDS16 */ }, { /* 2249 */ 0, /* PUSHDS32 */ }, { /* 2250 */ 0, /* PUSHES16 */ }, { /* 2251 */ 0, /* PUSHES32 */ }, { /* 2252 */ 0, /* PUSHF16 */ }, { /* 2253 */ 0, /* PUSHF32 */ }, { /* 2254 */ 0, /* PUSHF64 */ }, { /* 2255 */ 0, /* PUSHFS16 */ }, { /* 2256 */ 0, /* PUSHFS32 */ }, { /* 2257 */ 0, /* PUSHFS64 */ }, { /* 2258 */ 0, /* PUSHGS16 */ }, { /* 2259 */ 0, /* PUSHGS32 */ }, { /* 2260 */ 0, /* PUSHGS64 */ }, { /* 2261 */ 0, /* PUSHSS16 */ }, { /* 2262 */ 0, /* PUSHSS32 */ }, { /* 2263 */ 2, /* PUSHi16 */ }, { /* 2264 */ 2, /* PUSHi32 */ }, { /* 2265 */ 26, /* PXORrm */ }, { /* 2266 */ 27, /* PXORrr */ }, { /* 2267 */ 28, /* RCL16m1 */ }, { /* 2268 */ 28, /* RCL16mCL */ }, { /* 2269 */ 187, /* RCL16mi */ }, { /* 2270 */ 91, /* RCL16r1 */ }, { /* 2271 */ 91, /* RCL16rCL */ }, { /* 2272 */ 188, /* RCL16ri */ }, { /* 2273 */ 28, /* RCL32m1 */ }, { /* 2274 */ 28, /* RCL32mCL */ }, { /* 2275 */ 187, /* RCL32mi */ }, { /* 2276 */ 91, /* RCL32r1 */ }, { /* 2277 */ 91, /* RCL32rCL */ }, { /* 2278 */ 188, /* RCL32ri */ }, { /* 2279 */ 28, /* RCL64m1 */ }, { /* 2280 */ 28, /* RCL64mCL */ }, { /* 2281 */ 187, /* RCL64mi */ }, { /* 2282 */ 92, /* RCL64r1 */ }, { /* 2283 */ 92, /* RCL64rCL */ }, { /* 2284 */ 189, /* RCL64ri */ }, { /* 2285 */ 28, /* RCL8m1 */ }, { /* 2286 */ 28, /* RCL8mCL */ }, { /* 2287 */ 187, /* RCL8mi */ }, { /* 2288 */ 93, /* RCL8r1 */ }, { /* 2289 */ 93, /* RCL8rCL */ }, { /* 2290 */ 190, /* RCL8ri */ }, { /* 2291 */ 30, /* RCPPSm */ }, { /* 2292 */ 31, /* RCPPSr */ }, { /* 2293 */ 30, /* RCPSSm */ }, { /* 2294 */ 0, /* */ }, { /* 2295 */ 31, /* RCPSSr */ }, { /* 2296 */ 0, /* */ }, { /* 2297 */ 28, /* RCR16m1 */ }, { /* 2298 */ 28, /* RCR16mCL */ }, { /* 2299 */ 187, /* RCR16mi */ }, { /* 2300 */ 91, /* RCR16r1 */ }, { /* 2301 */ 91, /* RCR16rCL */ }, { /* 2302 */ 188, /* RCR16ri */ }, { /* 2303 */ 28, /* RCR32m1 */ }, { /* 2304 */ 28, /* RCR32mCL */ }, { /* 2305 */ 187, /* RCR32mi */ }, { /* 2306 */ 91, /* RCR32r1 */ }, { /* 2307 */ 91, /* RCR32rCL */ }, { /* 2308 */ 188, /* RCR32ri */ }, { /* 2309 */ 28, /* RCR64m1 */ }, { /* 2310 */ 28, /* RCR64mCL */ }, { /* 2311 */ 187, /* RCR64mi */ }, { /* 2312 */ 92, /* RCR64r1 */ }, { /* 2313 */ 92, /* RCR64rCL */ }, { /* 2314 */ 189, /* RCR64ri */ }, { /* 2315 */ 28, /* RCR8m1 */ }, { /* 2316 */ 28, /* RCR8mCL */ }, { /* 2317 */ 187, /* RCR8mi */ }, { /* 2318 */ 93, /* RCR8r1 */ }, { /* 2319 */ 93, /* RCR8rCL */ }, { /* 2320 */ 190, /* RCR8ri */ }, { /* 2321 */ 108, /* RDFSBASE */ }, { /* 2322 */ 72, /* RDFSBASE64 */ }, { /* 2323 */ 108, /* RDGSBASE */ }, { /* 2324 */ 72, /* RDGSBASE64 */ }, { /* 2325 */ 0, /* RDMSR */ }, { /* 2326 */ 108, /* RDPID32 */ }, { /* 2327 */ 72, /* RDPID64 */ }, { /* 2328 */ 0, /* RDPKRUr */ }, { /* 2329 */ 0, /* RDPMC */ }, { /* 2330 */ 70, /* RDRAND16r */ }, { /* 2331 */ 70, /* RDRAND32r */ }, { /* 2332 */ 72, /* RDRAND64r */ }, { /* 2333 */ 70, /* RDSEED16r */ }, { /* 2334 */ 70, /* RDSEED32r */ }, { /* 2335 */ 72, /* RDSEED64r */ }, { /* 2336 */ 191, /* RDSSPD */ }, { /* 2337 */ 92, /* RDSSPQ */ }, { /* 2338 */ 0, /* RDTSC */ }, { /* 2339 */ 0, /* RDTSCP */ }, { /* 2340 */ 0, /* REPNE_PREFIX */ }, { /* 2341 */ 0, /* REP_PREFIX */ }, { /* 2342 */ 125, /* RETIL */ }, { /* 2343 */ 125, /* RETIQ */ }, { /* 2344 */ 2, /* RETIW */ }, { /* 2345 */ 0, /* RETL */ }, { /* 2346 */ 0, /* RETQ */ }, { /* 2347 */ 0, /* RETW */ }, { /* 2348 */ 0, /* REX64_PREFIX */ }, { /* 2349 */ 28, /* ROL16m1 */ }, { /* 2350 */ 28, /* ROL16mCL */ }, { /* 2351 */ 187, /* ROL16mi */ }, { /* 2352 */ 91, /* ROL16r1 */ }, { /* 2353 */ 91, /* ROL16rCL */ }, { /* 2354 */ 188, /* ROL16ri */ }, { /* 2355 */ 28, /* ROL32m1 */ }, { /* 2356 */ 28, /* ROL32mCL */ }, { /* 2357 */ 187, /* ROL32mi */ }, { /* 2358 */ 91, /* ROL32r1 */ }, { /* 2359 */ 91, /* ROL32rCL */ }, { /* 2360 */ 188, /* ROL32ri */ }, { /* 2361 */ 28, /* ROL64m1 */ }, { /* 2362 */ 28, /* ROL64mCL */ }, { /* 2363 */ 187, /* ROL64mi */ }, { /* 2364 */ 92, /* ROL64r1 */ }, { /* 2365 */ 92, /* ROL64rCL */ }, { /* 2366 */ 189, /* ROL64ri */ }, { /* 2367 */ 28, /* ROL8m1 */ }, { /* 2368 */ 28, /* ROL8mCL */ }, { /* 2369 */ 187, /* ROL8mi */ }, { /* 2370 */ 93, /* ROL8r1 */ }, { /* 2371 */ 93, /* ROL8rCL */ }, { /* 2372 */ 190, /* ROL8ri */ }, { /* 2373 */ 28, /* ROR16m1 */ }, { /* 2374 */ 28, /* ROR16mCL */ }, { /* 2375 */ 187, /* ROR16mi */ }, { /* 2376 */ 91, /* ROR16r1 */ }, { /* 2377 */ 91, /* ROR16rCL */ }, { /* 2378 */ 188, /* ROR16ri */ }, { /* 2379 */ 28, /* ROR32m1 */ }, { /* 2380 */ 28, /* ROR32mCL */ }, { /* 2381 */ 187, /* ROR32mi */ }, { /* 2382 */ 91, /* ROR32r1 */ }, { /* 2383 */ 91, /* ROR32rCL */ }, { /* 2384 */ 188, /* ROR32ri */ }, { /* 2385 */ 28, /* ROR64m1 */ }, { /* 2386 */ 28, /* ROR64mCL */ }, { /* 2387 */ 187, /* ROR64mi */ }, { /* 2388 */ 92, /* ROR64r1 */ }, { /* 2389 */ 92, /* ROR64rCL */ }, { /* 2390 */ 189, /* ROR64ri */ }, { /* 2391 */ 28, /* ROR8m1 */ }, { /* 2392 */ 28, /* ROR8mCL */ }, { /* 2393 */ 187, /* ROR8mi */ }, { /* 2394 */ 93, /* ROR8r1 */ }, { /* 2395 */ 93, /* ROR8rCL */ }, { /* 2396 */ 190, /* ROR8ri */ }, { /* 2397 */ 192, /* RORX32mi */ }, { /* 2398 */ 193, /* RORX32ri */ }, { /* 2399 */ 194, /* RORX64mi */ }, { /* 2400 */ 195, /* RORX64ri */ }, { /* 2401 */ 32, /* ROUNDPDm */ }, { /* 2402 */ 33, /* ROUNDPDr */ }, { /* 2403 */ 32, /* ROUNDPSm */ }, { /* 2404 */ 33, /* ROUNDPSr */ }, { /* 2405 */ 32, /* ROUNDSDm */ }, { /* 2406 */ 0, /* */ }, { /* 2407 */ 33, /* ROUNDSDr */ }, { /* 2408 */ 0, /* */ }, { /* 2409 */ 32, /* ROUNDSSm */ }, { /* 2410 */ 0, /* */ }, { /* 2411 */ 33, /* ROUNDSSr */ }, { /* 2412 */ 0, /* */ }, { /* 2413 */ 0, /* RSM */ }, { /* 2414 */ 30, /* RSQRTPSm */ }, { /* 2415 */ 31, /* RSQRTPSr */ }, { /* 2416 */ 30, /* RSQRTSSm */ }, { /* 2417 */ 0, /* */ }, { /* 2418 */ 31, /* RSQRTSSr */ }, { /* 2419 */ 0, /* */ }, { /* 2420 */ 28, /* RSTORSSP */ }, { /* 2421 */ 0, /* SAHF */ }, { /* 2422 */ 28, /* SAL16m1 */ }, { /* 2423 */ 28, /* SAL16mCL */ }, { /* 2424 */ 4, /* SAL16mi */ }, { /* 2425 */ 91, /* SAL16r1 */ }, { /* 2426 */ 91, /* SAL16rCL */ }, { /* 2427 */ 7, /* SAL16ri */ }, { /* 2428 */ 28, /* SAL32m1 */ }, { /* 2429 */ 28, /* SAL32mCL */ }, { /* 2430 */ 4, /* SAL32mi */ }, { /* 2431 */ 91, /* SAL32r1 */ }, { /* 2432 */ 91, /* SAL32rCL */ }, { /* 2433 */ 7, /* SAL32ri */ }, { /* 2434 */ 28, /* SAL64m1 */ }, { /* 2435 */ 28, /* SAL64mCL */ }, { /* 2436 */ 4, /* SAL64mi */ }, { /* 2437 */ 92, /* SAL64r1 */ }, { /* 2438 */ 92, /* SAL64rCL */ }, { /* 2439 */ 15, /* SAL64ri */ }, { /* 2440 */ 28, /* SAL8m1 */ }, { /* 2441 */ 28, /* SAL8mCL */ }, { /* 2442 */ 4, /* SAL8mi */ }, { /* 2443 */ 93, /* SAL8r1 */ }, { /* 2444 */ 93, /* SAL8rCL */ }, { /* 2445 */ 20, /* SAL8ri */ }, { /* 2446 */ 0, /* SALC */ }, { /* 2447 */ 28, /* SAR16m1 */ }, { /* 2448 */ 28, /* SAR16mCL */ }, { /* 2449 */ 187, /* SAR16mi */ }, { /* 2450 */ 91, /* SAR16r1 */ }, { /* 2451 */ 91, /* SAR16rCL */ }, { /* 2452 */ 188, /* SAR16ri */ }, { /* 2453 */ 28, /* SAR32m1 */ }, { /* 2454 */ 28, /* SAR32mCL */ }, { /* 2455 */ 187, /* SAR32mi */ }, { /* 2456 */ 91, /* SAR32r1 */ }, { /* 2457 */ 91, /* SAR32rCL */ }, { /* 2458 */ 188, /* SAR32ri */ }, { /* 2459 */ 28, /* SAR64m1 */ }, { /* 2460 */ 28, /* SAR64mCL */ }, { /* 2461 */ 187, /* SAR64mi */ }, { /* 2462 */ 92, /* SAR64r1 */ }, { /* 2463 */ 92, /* SAR64rCL */ }, { /* 2464 */ 189, /* SAR64ri */ }, { /* 2465 */ 28, /* SAR8m1 */ }, { /* 2466 */ 28, /* SAR8mCL */ }, { /* 2467 */ 187, /* SAR8mi */ }, { /* 2468 */ 93, /* SAR8r1 */ }, { /* 2469 */ 93, /* SAR8rCL */ }, { /* 2470 */ 190, /* SAR8ri */ }, { /* 2471 */ 40, /* SARX32rm */ }, { /* 2472 */ 41, /* SARX32rr */ }, { /* 2473 */ 42, /* SARX64rm */ }, { /* 2474 */ 43, /* SARX64rr */ }, { /* 2475 */ 0, /* SAVEPREVSSP */ }, { /* 2476 */ 2, /* SBB16i16 */ }, { /* 2477 */ 3, /* SBB16mi */ }, { /* 2478 */ 4, /* SBB16mi8 */ }, { /* 2479 */ 5, /* SBB16mr */ }, { /* 2480 */ 6, /* SBB16ri */ }, { /* 2481 */ 7, /* SBB16ri8 */ }, { /* 2482 */ 8, /* SBB16rm */ }, { /* 2483 */ 9, /* SBB16rr */ }, { /* 2484 */ 10, /* SBB16rr_REV */ }, { /* 2485 */ 2, /* SBB32i32 */ }, { /* 2486 */ 3, /* SBB32mi */ }, { /* 2487 */ 4, /* SBB32mi8 */ }, { /* 2488 */ 5, /* SBB32mr */ }, { /* 2489 */ 6, /* SBB32ri */ }, { /* 2490 */ 7, /* SBB32ri8 */ }, { /* 2491 */ 8, /* SBB32rm */ }, { /* 2492 */ 9, /* SBB32rr */ }, { /* 2493 */ 10, /* SBB32rr_REV */ }, { /* 2494 */ 11, /* SBB64i32 */ }, { /* 2495 */ 12, /* SBB64mi32 */ }, { /* 2496 */ 4, /* SBB64mi8 */ }, { /* 2497 */ 13, /* SBB64mr */ }, { /* 2498 */ 14, /* SBB64ri32 */ }, { /* 2499 */ 15, /* SBB64ri8 */ }, { /* 2500 */ 16, /* SBB64rm */ }, { /* 2501 */ 17, /* SBB64rr */ }, { /* 2502 */ 18, /* SBB64rr_REV */ }, { /* 2503 */ 1, /* SBB8i8 */ }, { /* 2504 */ 4, /* SBB8mi */ }, { /* 2505 */ 4, /* SBB8mi8 */ }, { /* 2506 */ 19, /* SBB8mr */ }, { /* 2507 */ 20, /* SBB8ri */ }, { /* 2508 */ 20, /* SBB8ri8 */ }, { /* 2509 */ 21, /* SBB8rm */ }, { /* 2510 */ 22, /* SBB8rr */ }, { /* 2511 */ 23, /* SBB8rr_REV */ }, { /* 2512 */ 109, /* SCASB */ }, { /* 2513 */ 109, /* SCASL */ }, { /* 2514 */ 109, /* SCASQ */ }, { /* 2515 */ 109, /* SCASW */ }, { /* 2516 */ 28, /* SETAEm */ }, { /* 2517 */ 94, /* SETAEr */ }, { /* 2518 */ 28, /* SETAm */ }, { /* 2519 */ 94, /* SETAr */ }, { /* 2520 */ 28, /* SETBEm */ }, { /* 2521 */ 94, /* SETBEr */ }, { /* 2522 */ 28, /* SETBm */ }, { /* 2523 */ 94, /* SETBr */ }, { /* 2524 */ 28, /* SETEm */ }, { /* 2525 */ 94, /* SETEr */ }, { /* 2526 */ 28, /* SETGEm */ }, { /* 2527 */ 94, /* SETGEr */ }, { /* 2528 */ 28, /* SETGm */ }, { /* 2529 */ 94, /* SETGr */ }, { /* 2530 */ 28, /* SETLEm */ }, { /* 2531 */ 94, /* SETLEr */ }, { /* 2532 */ 28, /* SETLm */ }, { /* 2533 */ 94, /* SETLr */ }, { /* 2534 */ 28, /* SETNEm */ }, { /* 2535 */ 94, /* SETNEr */ }, { /* 2536 */ 28, /* SETNOm */ }, { /* 2537 */ 94, /* SETNOr */ }, { /* 2538 */ 28, /* SETNPm */ }, { /* 2539 */ 94, /* SETNPr */ }, { /* 2540 */ 28, /* SETNSm */ }, { /* 2541 */ 94, /* SETNSr */ }, { /* 2542 */ 28, /* SETOm */ }, { /* 2543 */ 94, /* SETOr */ }, { /* 2544 */ 28, /* SETPm */ }, { /* 2545 */ 94, /* SETPr */ }, { /* 2546 */ 0, /* SETSSBSY */ }, { /* 2547 */ 28, /* SETSm */ }, { /* 2548 */ 94, /* SETSr */ }, { /* 2549 */ 0, /* SFENCE */ }, { /* 2550 */ 28, /* SGDT16m */ }, { /* 2551 */ 28, /* SGDT32m */ }, { /* 2552 */ 28, /* SGDT64m */ }, { /* 2553 */ 26, /* SHA1MSG1rm */ }, { /* 2554 */ 27, /* SHA1MSG1rr */ }, { /* 2555 */ 26, /* SHA1MSG2rm */ }, { /* 2556 */ 27, /* SHA1MSG2rr */ }, { /* 2557 */ 26, /* SHA1NEXTErm */ }, { /* 2558 */ 27, /* SHA1NEXTErr */ }, { /* 2559 */ 52, /* SHA1RNDS4rmi */ }, { /* 2560 */ 53, /* SHA1RNDS4rri */ }, { /* 2561 */ 26, /* SHA256MSG1rm */ }, { /* 2562 */ 27, /* SHA256MSG1rr */ }, { /* 2563 */ 26, /* SHA256MSG2rm */ }, { /* 2564 */ 27, /* SHA256MSG2rr */ }, { /* 2565 */ 26, /* SHA256RNDS2rm */ }, { /* 2566 */ 27, /* SHA256RNDS2rr */ }, { /* 2567 */ 28, /* SHL16m1 */ }, { /* 2568 */ 28, /* SHL16mCL */ }, { /* 2569 */ 187, /* SHL16mi */ }, { /* 2570 */ 91, /* SHL16r1 */ }, { /* 2571 */ 91, /* SHL16rCL */ }, { /* 2572 */ 188, /* SHL16ri */ }, { /* 2573 */ 28, /* SHL32m1 */ }, { /* 2574 */ 28, /* SHL32mCL */ }, { /* 2575 */ 187, /* SHL32mi */ }, { /* 2576 */ 91, /* SHL32r1 */ }, { /* 2577 */ 91, /* SHL32rCL */ }, { /* 2578 */ 188, /* SHL32ri */ }, { /* 2579 */ 28, /* SHL64m1 */ }, { /* 2580 */ 28, /* SHL64mCL */ }, { /* 2581 */ 187, /* SHL64mi */ }, { /* 2582 */ 92, /* SHL64r1 */ }, { /* 2583 */ 92, /* SHL64rCL */ }, { /* 2584 */ 189, /* SHL64ri */ }, { /* 2585 */ 28, /* SHL8m1 */ }, { /* 2586 */ 28, /* SHL8mCL */ }, { /* 2587 */ 187, /* SHL8mi */ }, { /* 2588 */ 93, /* SHL8r1 */ }, { /* 2589 */ 93, /* SHL8rCL */ }, { /* 2590 */ 190, /* SHL8ri */ }, { /* 2591 */ 5, /* SHLD16mrCL */ }, { /* 2592 */ 196, /* SHLD16mri8 */ }, { /* 2593 */ 9, /* SHLD16rrCL */ }, { /* 2594 */ 197, /* SHLD16rri8 */ }, { /* 2595 */ 5, /* SHLD32mrCL */ }, { /* 2596 */ 196, /* SHLD32mri8 */ }, { /* 2597 */ 9, /* SHLD32rrCL */ }, { /* 2598 */ 197, /* SHLD32rri8 */ }, { /* 2599 */ 13, /* SHLD64mrCL */ }, { /* 2600 */ 198, /* SHLD64mri8 */ }, { /* 2601 */ 17, /* SHLD64rrCL */ }, { /* 2602 */ 199, /* SHLD64rri8 */ }, { /* 2603 */ 40, /* SHLX32rm */ }, { /* 2604 */ 41, /* SHLX32rr */ }, { /* 2605 */ 42, /* SHLX64rm */ }, { /* 2606 */ 43, /* SHLX64rr */ }, { /* 2607 */ 28, /* SHR16m1 */ }, { /* 2608 */ 28, /* SHR16mCL */ }, { /* 2609 */ 187, /* SHR16mi */ }, { /* 2610 */ 91, /* SHR16r1 */ }, { /* 2611 */ 91, /* SHR16rCL */ }, { /* 2612 */ 188, /* SHR16ri */ }, { /* 2613 */ 28, /* SHR32m1 */ }, { /* 2614 */ 28, /* SHR32mCL */ }, { /* 2615 */ 187, /* SHR32mi */ }, { /* 2616 */ 91, /* SHR32r1 */ }, { /* 2617 */ 91, /* SHR32rCL */ }, { /* 2618 */ 188, /* SHR32ri */ }, { /* 2619 */ 28, /* SHR64m1 */ }, { /* 2620 */ 28, /* SHR64mCL */ }, { /* 2621 */ 187, /* SHR64mi */ }, { /* 2622 */ 92, /* SHR64r1 */ }, { /* 2623 */ 92, /* SHR64rCL */ }, { /* 2624 */ 189, /* SHR64ri */ }, { /* 2625 */ 28, /* SHR8m1 */ }, { /* 2626 */ 28, /* SHR8mCL */ }, { /* 2627 */ 187, /* SHR8mi */ }, { /* 2628 */ 93, /* SHR8r1 */ }, { /* 2629 */ 93, /* SHR8rCL */ }, { /* 2630 */ 190, /* SHR8ri */ }, { /* 2631 */ 5, /* SHRD16mrCL */ }, { /* 2632 */ 196, /* SHRD16mri8 */ }, { /* 2633 */ 9, /* SHRD16rrCL */ }, { /* 2634 */ 197, /* SHRD16rri8 */ }, { /* 2635 */ 5, /* SHRD32mrCL */ }, { /* 2636 */ 196, /* SHRD32mri8 */ }, { /* 2637 */ 9, /* SHRD32rrCL */ }, { /* 2638 */ 197, /* SHRD32rri8 */ }, { /* 2639 */ 13, /* SHRD64mrCL */ }, { /* 2640 */ 198, /* SHRD64mri8 */ }, { /* 2641 */ 17, /* SHRD64rrCL */ }, { /* 2642 */ 199, /* SHRD64rri8 */ }, { /* 2643 */ 40, /* SHRX32rm */ }, { /* 2644 */ 41, /* SHRX32rr */ }, { /* 2645 */ 42, /* SHRX64rm */ }, { /* 2646 */ 43, /* SHRX64rr */ }, { /* 2647 */ 52, /* SHUFPDrmi */ }, { /* 2648 */ 53, /* SHUFPDrri */ }, { /* 2649 */ 52, /* SHUFPSrmi */ }, { /* 2650 */ 53, /* SHUFPSrri */ }, { /* 2651 */ 28, /* SIDT16m */ }, { /* 2652 */ 28, /* SIDT32m */ }, { /* 2653 */ 28, /* SIDT64m */ }, { /* 2654 */ 0, /* SIN_F */ }, { /* 2655 */ 0, /* */ }, { /* 2656 */ 0, /* */ }, { /* 2657 */ 0, /* */ }, { /* 2658 */ 0, /* SKINIT */ }, { /* 2659 */ 28, /* SLDT16m */ }, { /* 2660 */ 70, /* SLDT16r */ }, { /* 2661 */ 70, /* SLDT32r */ }, { /* 2662 */ 72, /* SLDT64r */ }, { /* 2663 */ 108, /* SLWPCB */ }, { /* 2664 */ 72, /* SLWPCB64 */ }, { /* 2665 */ 28, /* SMSW16m */ }, { /* 2666 */ 70, /* SMSW16r */ }, { /* 2667 */ 70, /* SMSW32r */ }, { /* 2668 */ 72, /* SMSW64r */ }, { /* 2669 */ 30, /* SQRTPDm */ }, { /* 2670 */ 31, /* SQRTPDr */ }, { /* 2671 */ 30, /* SQRTPSm */ }, { /* 2672 */ 31, /* SQRTPSr */ }, { /* 2673 */ 30, /* SQRTSDm */ }, { /* 2674 */ 0, /* */ }, { /* 2675 */ 31, /* SQRTSDr */ }, { /* 2676 */ 0, /* */ }, { /* 2677 */ 30, /* SQRTSSm */ }, { /* 2678 */ 0, /* */ }, { /* 2679 */ 31, /* SQRTSSr */ }, { /* 2680 */ 0, /* */ }, { /* 2681 */ 0, /* SQRT_F */ }, { /* 2682 */ 0, /* */ }, { /* 2683 */ 0, /* */ }, { /* 2684 */ 0, /* */ }, { /* 2685 */ 0, /* STAC */ }, { /* 2686 */ 0, /* STC */ }, { /* 2687 */ 0, /* STD */ }, { /* 2688 */ 0, /* STGI */ }, { /* 2689 */ 0, /* STI */ }, { /* 2690 */ 28, /* STMXCSR */ }, { /* 2691 */ 109, /* STOSB */ }, { /* 2692 */ 109, /* STOSL */ }, { /* 2693 */ 109, /* STOSQ */ }, { /* 2694 */ 109, /* STOSW */ }, { /* 2695 */ 70, /* STR16r */ }, { /* 2696 */ 70, /* STR32r */ }, { /* 2697 */ 72, /* STR64r */ }, { /* 2698 */ 28, /* STRm */ }, { /* 2699 */ 28, /* ST_F32m */ }, { /* 2700 */ 28, /* ST_F64m */ }, { /* 2701 */ 28, /* ST_FP32m */ }, { /* 2702 */ 28, /* ST_FP64m */ }, { /* 2703 */ 28, /* ST_FP80m */ }, { /* 2704 */ 29, /* ST_FPrr */ }, { /* 2705 */ 0, /* */ }, { /* 2706 */ 0, /* */ }, { /* 2707 */ 0, /* */ }, { /* 2708 */ 0, /* */ }, { /* 2709 */ 0, /* */ }, { /* 2710 */ 0, /* */ }, { /* 2711 */ 0, /* */ }, { /* 2712 */ 0, /* */ }, { /* 2713 */ 0, /* */ }, { /* 2714 */ 0, /* */ }, { /* 2715 */ 0, /* */ }, { /* 2716 */ 29, /* ST_Frr */ }, { /* 2717 */ 2, /* SUB16i16 */ }, { /* 2718 */ 3, /* SUB16mi */ }, { /* 2719 */ 4, /* SUB16mi8 */ }, { /* 2720 */ 5, /* SUB16mr */ }, { /* 2721 */ 6, /* SUB16ri */ }, { /* 2722 */ 7, /* SUB16ri8 */ }, { /* 2723 */ 8, /* SUB16rm */ }, { /* 2724 */ 9, /* SUB16rr */ }, { /* 2725 */ 10, /* SUB16rr_REV */ }, { /* 2726 */ 2, /* SUB32i32 */ }, { /* 2727 */ 3, /* SUB32mi */ }, { /* 2728 */ 4, /* SUB32mi8 */ }, { /* 2729 */ 5, /* SUB32mr */ }, { /* 2730 */ 6, /* SUB32ri */ }, { /* 2731 */ 7, /* SUB32ri8 */ }, { /* 2732 */ 8, /* SUB32rm */ }, { /* 2733 */ 9, /* SUB32rr */ }, { /* 2734 */ 10, /* SUB32rr_REV */ }, { /* 2735 */ 11, /* SUB64i32 */ }, { /* 2736 */ 12, /* SUB64mi32 */ }, { /* 2737 */ 4, /* SUB64mi8 */ }, { /* 2738 */ 13, /* SUB64mr */ }, { /* 2739 */ 14, /* SUB64ri32 */ }, { /* 2740 */ 15, /* SUB64ri8 */ }, { /* 2741 */ 16, /* SUB64rm */ }, { /* 2742 */ 17, /* SUB64rr */ }, { /* 2743 */ 18, /* SUB64rr_REV */ }, { /* 2744 */ 1, /* SUB8i8 */ }, { /* 2745 */ 4, /* SUB8mi */ }, { /* 2746 */ 4, /* SUB8mi8 */ }, { /* 2747 */ 19, /* SUB8mr */ }, { /* 2748 */ 20, /* SUB8ri */ }, { /* 2749 */ 20, /* SUB8ri8 */ }, { /* 2750 */ 21, /* SUB8rm */ }, { /* 2751 */ 22, /* SUB8rr */ }, { /* 2752 */ 23, /* SUB8rr_REV */ }, { /* 2753 */ 26, /* SUBPDrm */ }, { /* 2754 */ 27, /* SUBPDrr */ }, { /* 2755 */ 26, /* SUBPSrm */ }, { /* 2756 */ 27, /* SUBPSrr */ }, { /* 2757 */ 28, /* SUBR_F32m */ }, { /* 2758 */ 28, /* SUBR_F64m */ }, { /* 2759 */ 28, /* SUBR_FI16m */ }, { /* 2760 */ 28, /* SUBR_FI32m */ }, { /* 2761 */ 29, /* SUBR_FPrST0 */ }, { /* 2762 */ 29, /* SUBR_FST0r */ }, { /* 2763 */ 0, /* */ }, { /* 2764 */ 0, /* */ }, { /* 2765 */ 0, /* */ }, { /* 2766 */ 0, /* */ }, { /* 2767 */ 0, /* */ }, { /* 2768 */ 0, /* */ }, { /* 2769 */ 0, /* */ }, { /* 2770 */ 0, /* */ }, { /* 2771 */ 0, /* */ }, { /* 2772 */ 0, /* */ }, { /* 2773 */ 0, /* */ }, { /* 2774 */ 29, /* SUBR_FrST0 */ }, { /* 2775 */ 26, /* SUBSDrm */ }, { /* 2776 */ 0, /* */ }, { /* 2777 */ 27, /* SUBSDrr */ }, { /* 2778 */ 0, /* */ }, { /* 2779 */ 26, /* SUBSSrm */ }, { /* 2780 */ 0, /* */ }, { /* 2781 */ 27, /* SUBSSrr */ }, { /* 2782 */ 0, /* */ }, { /* 2783 */ 28, /* SUB_F32m */ }, { /* 2784 */ 28, /* SUB_F64m */ }, { /* 2785 */ 28, /* SUB_FI16m */ }, { /* 2786 */ 28, /* SUB_FI32m */ }, { /* 2787 */ 29, /* SUB_FPrST0 */ }, { /* 2788 */ 29, /* SUB_FST0r */ }, { /* 2789 */ 0, /* */ }, { /* 2790 */ 0, /* */ }, { /* 2791 */ 0, /* */ }, { /* 2792 */ 0, /* */ }, { /* 2793 */ 0, /* */ }, { /* 2794 */ 0, /* */ }, { /* 2795 */ 0, /* */ }, { /* 2796 */ 0, /* */ }, { /* 2797 */ 0, /* */ }, { /* 2798 */ 0, /* */ }, { /* 2799 */ 0, /* */ }, { /* 2800 */ 0, /* */ }, { /* 2801 */ 0, /* */ }, { /* 2802 */ 0, /* */ }, { /* 2803 */ 29, /* SUB_FrST0 */ }, { /* 2804 */ 0, /* SWAPGS */ }, { /* 2805 */ 0, /* SYSCALL */ }, { /* 2806 */ 0, /* SYSENTER */ }, { /* 2807 */ 0, /* SYSEXIT */ }, { /* 2808 */ 0, /* SYSEXIT64 */ }, { /* 2809 */ 0, /* SYSRET */ }, { /* 2810 */ 0, /* SYSRET64 */ }, { /* 2811 */ 48, /* T1MSKC32rm */ }, { /* 2812 */ 49, /* T1MSKC32rr */ }, { /* 2813 */ 50, /* T1MSKC64rm */ }, { /* 2814 */ 51, /* T1MSKC64rr */ }, { /* 2815 */ 2, /* TEST16i16 */ }, { /* 2816 */ 3, /* TEST16mi */ }, { /* 2817 */ 3, /* TEST16mi_alt */ }, { /* 2818 */ 5, /* TEST16mr */ }, { /* 2819 */ 74, /* TEST16ri */ }, { /* 2820 */ 74, /* TEST16ri_alt */ }, { /* 2821 */ 67, /* TEST16rr */ }, { /* 2822 */ 2, /* TEST32i32 */ }, { /* 2823 */ 3, /* TEST32mi */ }, { /* 2824 */ 3, /* TEST32mi_alt */ }, { /* 2825 */ 5, /* TEST32mr */ }, { /* 2826 */ 74, /* TEST32ri */ }, { /* 2827 */ 74, /* TEST32ri_alt */ }, { /* 2828 */ 67, /* TEST32rr */ }, { /* 2829 */ 11, /* TEST64i32 */ }, { /* 2830 */ 12, /* TEST64mi32 */ }, { /* 2831 */ 12, /* TEST64mi32_alt */ }, { /* 2832 */ 13, /* TEST64mr */ }, { /* 2833 */ 75, /* TEST64ri32 */ }, { /* 2834 */ 75, /* TEST64ri32_alt */ }, { /* 2835 */ 69, /* TEST64rr */ }, { /* 2836 */ 1, /* TEST8i8 */ }, { /* 2837 */ 4, /* TEST8mi */ }, { /* 2838 */ 4, /* TEST8mi_alt */ }, { /* 2839 */ 19, /* TEST8mr */ }, { /* 2840 */ 76, /* TEST8ri */ }, { /* 2841 */ 76, /* TEST8ri_alt */ }, { /* 2842 */ 78, /* TEST8rr */ }, { /* 2843 */ 108, /* TPAUSE */ }, { /* 2844 */ 0, /* TST_F */ }, { /* 2845 */ 0, /* */ }, { /* 2846 */ 0, /* */ }, { /* 2847 */ 0, /* */ }, { /* 2848 */ 60, /* TZCNT16rm */ }, { /* 2849 */ 61, /* TZCNT16rr */ }, { /* 2850 */ 60, /* TZCNT32rm */ }, { /* 2851 */ 61, /* TZCNT32rr */ }, { /* 2852 */ 62, /* TZCNT64rm */ }, { /* 2853 */ 63, /* TZCNT64rr */ }, { /* 2854 */ 48, /* TZMSK32rm */ }, { /* 2855 */ 49, /* TZMSK32rr */ }, { /* 2856 */ 50, /* TZMSK64rm */ }, { /* 2857 */ 51, /* TZMSK64rr */ }, { /* 2858 */ 30, /* UCOMISDrm */ }, { /* 2859 */ 0, /* */ }, { /* 2860 */ 31, /* UCOMISDrr */ }, { /* 2861 */ 0, /* */ }, { /* 2862 */ 30, /* UCOMISSrm */ }, { /* 2863 */ 0, /* */ }, { /* 2864 */ 31, /* UCOMISSrr */ }, { /* 2865 */ 0, /* */ }, { /* 2866 */ 29, /* UCOM_FIPr */ }, { /* 2867 */ 29, /* UCOM_FIr */ }, { /* 2868 */ 0, /* UCOM_FPPr */ }, { /* 2869 */ 29, /* UCOM_FPr */ }, { /* 2870 */ 0, /* */ }, { /* 2871 */ 0, /* */ }, { /* 2872 */ 0, /* */ }, { /* 2873 */ 0, /* */ }, { /* 2874 */ 0, /* */ }, { /* 2875 */ 0, /* */ }, { /* 2876 */ 29, /* UCOM_Fr */ }, { /* 2877 */ 0, /* UD0 */ }, { /* 2878 */ 0, /* UD1 */ }, { /* 2879 */ 0, /* UD2 */ }, { /* 2880 */ 123, /* UMONITOR16 */ }, { /* 2881 */ 108, /* UMONITOR32 */ }, { /* 2882 */ 72, /* UMONITOR64 */ }, { /* 2883 */ 108, /* UMWAIT */ }, { /* 2884 */ 26, /* UNPCKHPDrm */ }, { /* 2885 */ 27, /* UNPCKHPDrr */ }, { /* 2886 */ 26, /* UNPCKHPSrm */ }, { /* 2887 */ 27, /* UNPCKHPSrr */ }, { /* 2888 */ 26, /* UNPCKLPDrm */ }, { /* 2889 */ 27, /* UNPCKLPDrr */ }, { /* 2890 */ 26, /* UNPCKLPSrm */ }, { /* 2891 */ 27, /* UNPCKLPSrr */ }, { /* 2892 */ 200, /* V4FMADDPSrm */ }, { /* 2893 */ 201, /* V4FMADDPSrmk */ }, { /* 2894 */ 201, /* V4FMADDPSrmkz */ }, { /* 2895 */ 202, /* V4FMADDSSrm */ }, { /* 2896 */ 203, /* V4FMADDSSrmk */ }, { /* 2897 */ 203, /* V4FMADDSSrmkz */ }, { /* 2898 */ 200, /* V4FNMADDPSrm */ }, { /* 2899 */ 201, /* V4FNMADDPSrmk */ }, { /* 2900 */ 201, /* V4FNMADDPSrmkz */ }, { /* 2901 */ 202, /* V4FNMADDSSrm */ }, { /* 2902 */ 203, /* V4FNMADDSSrmk */ }, { /* 2903 */ 203, /* V4FNMADDSSrmkz */ }, { /* 2904 */ 204, /* VADDPDYrm */ }, { /* 2905 */ 205, /* VADDPDYrr */ }, { /* 2906 */ 206, /* VADDPDZ128rm */ }, { /* 2907 */ 207, /* VADDPDZ128rmb */ }, { /* 2908 */ 208, /* VADDPDZ128rmbk */ }, { /* 2909 */ 209, /* VADDPDZ128rmbkz */ }, { /* 2910 */ 203, /* VADDPDZ128rmk */ }, { /* 2911 */ 210, /* VADDPDZ128rmkz */ }, { /* 2912 */ 211, /* VADDPDZ128rr */ }, { /* 2913 */ 212, /* VADDPDZ128rrk */ }, { /* 2914 */ 213, /* VADDPDZ128rrkz */ }, { /* 2915 */ 214, /* VADDPDZ256rm */ }, { /* 2916 */ 215, /* VADDPDZ256rmb */ }, { /* 2917 */ 216, /* VADDPDZ256rmbk */ }, { /* 2918 */ 217, /* VADDPDZ256rmbkz */ }, { /* 2919 */ 218, /* VADDPDZ256rmk */ }, { /* 2920 */ 219, /* VADDPDZ256rmkz */ }, { /* 2921 */ 220, /* VADDPDZ256rr */ }, { /* 2922 */ 221, /* VADDPDZ256rrk */ }, { /* 2923 */ 222, /* VADDPDZ256rrkz */ }, { /* 2924 */ 223, /* VADDPDZrm */ }, { /* 2925 */ 224, /* VADDPDZrmb */ }, { /* 2926 */ 225, /* VADDPDZrmbk */ }, { /* 2927 */ 226, /* VADDPDZrmbkz */ }, { /* 2928 */ 227, /* VADDPDZrmk */ }, { /* 2929 */ 228, /* VADDPDZrmkz */ }, { /* 2930 */ 229, /* VADDPDZrr */ }, { /* 2931 */ 230, /* VADDPDZrrb */ }, { /* 2932 */ 231, /* VADDPDZrrbk */ }, { /* 2933 */ 232, /* VADDPDZrrbkz */ }, { /* 2934 */ 233, /* VADDPDZrrk */ }, { /* 2935 */ 234, /* VADDPDZrrkz */ }, { /* 2936 */ 235, /* VADDPDrm */ }, { /* 2937 */ 236, /* VADDPDrr */ }, { /* 2938 */ 204, /* VADDPSYrm */ }, { /* 2939 */ 205, /* VADDPSYrr */ }, { /* 2940 */ 206, /* VADDPSZ128rm */ }, { /* 2941 */ 237, /* VADDPSZ128rmb */ }, { /* 2942 */ 238, /* VADDPSZ128rmbk */ }, { /* 2943 */ 239, /* VADDPSZ128rmbkz */ }, { /* 2944 */ 203, /* VADDPSZ128rmk */ }, { /* 2945 */ 210, /* VADDPSZ128rmkz */ }, { /* 2946 */ 211, /* VADDPSZ128rr */ }, { /* 2947 */ 212, /* VADDPSZ128rrk */ }, { /* 2948 */ 213, /* VADDPSZ128rrkz */ }, { /* 2949 */ 214, /* VADDPSZ256rm */ }, { /* 2950 */ 240, /* VADDPSZ256rmb */ }, { /* 2951 */ 241, /* VADDPSZ256rmbk */ }, { /* 2952 */ 242, /* VADDPSZ256rmbkz */ }, { /* 2953 */ 218, /* VADDPSZ256rmk */ }, { /* 2954 */ 219, /* VADDPSZ256rmkz */ }, { /* 2955 */ 220, /* VADDPSZ256rr */ }, { /* 2956 */ 221, /* VADDPSZ256rrk */ }, { /* 2957 */ 222, /* VADDPSZ256rrkz */ }, { /* 2958 */ 223, /* VADDPSZrm */ }, { /* 2959 */ 243, /* VADDPSZrmb */ }, { /* 2960 */ 244, /* VADDPSZrmbk */ }, { /* 2961 */ 245, /* VADDPSZrmbkz */ }, { /* 2962 */ 227, /* VADDPSZrmk */ }, { /* 2963 */ 228, /* VADDPSZrmkz */ }, { /* 2964 */ 229, /* VADDPSZrr */ }, { /* 2965 */ 246, /* VADDPSZrrb */ }, { /* 2966 */ 247, /* VADDPSZrrbk */ }, { /* 2967 */ 248, /* VADDPSZrrbkz */ }, { /* 2968 */ 233, /* VADDPSZrrk */ }, { /* 2969 */ 234, /* VADDPSZrrkz */ }, { /* 2970 */ 235, /* VADDPSrm */ }, { /* 2971 */ 236, /* VADDPSrr */ }, { /* 2972 */ 0, /* */ }, { /* 2973 */ 207, /* VADDSDZrm_Int */ }, { /* 2974 */ 208, /* VADDSDZrm_Intk */ }, { /* 2975 */ 209, /* VADDSDZrm_Intkz */ }, { /* 2976 */ 0, /* */ }, { /* 2977 */ 249, /* VADDSDZrr_Int */ }, { /* 2978 */ 250, /* VADDSDZrr_Intk */ }, { /* 2979 */ 251, /* VADDSDZrr_Intkz */ }, { /* 2980 */ 252, /* VADDSDZrrb_Int */ }, { /* 2981 */ 253, /* VADDSDZrrb_Intk */ }, { /* 2982 */ 254, /* VADDSDZrrb_Intkz */ }, { /* 2983 */ 235, /* VADDSDrm */ }, { /* 2984 */ 0, /* */ }, { /* 2985 */ 236, /* VADDSDrr */ }, { /* 2986 */ 0, /* */ }, { /* 2987 */ 0, /* */ }, { /* 2988 */ 237, /* VADDSSZrm_Int */ }, { /* 2989 */ 238, /* VADDSSZrm_Intk */ }, { /* 2990 */ 239, /* VADDSSZrm_Intkz */ }, { /* 2991 */ 0, /* */ }, { /* 2992 */ 255, /* VADDSSZrr_Int */ }, { /* 2993 */ 256, /* VADDSSZrr_Intk */ }, { /* 2994 */ 257, /* VADDSSZrr_Intkz */ }, { /* 2995 */ 258, /* VADDSSZrrb_Int */ }, { /* 2996 */ 259, /* VADDSSZrrb_Intk */ }, { /* 2997 */ 260, /* VADDSSZrrb_Intkz */ }, { /* 2998 */ 235, /* VADDSSrm */ }, { /* 2999 */ 0, /* */ }, { /* 3000 */ 236, /* VADDSSrr */ }, { /* 3001 */ 0, /* */ }, { /* 3002 */ 204, /* VADDSUBPDYrm */ }, { /* 3003 */ 205, /* VADDSUBPDYrr */ }, { /* 3004 */ 235, /* VADDSUBPDrm */ }, { /* 3005 */ 236, /* VADDSUBPDrr */ }, { /* 3006 */ 204, /* VADDSUBPSYrm */ }, { /* 3007 */ 205, /* VADDSUBPSYrr */ }, { /* 3008 */ 235, /* VADDSUBPSrm */ }, { /* 3009 */ 236, /* VADDSUBPSrr */ }, { /* 3010 */ 204, /* VAESDECLASTYrm */ }, { /* 3011 */ 205, /* VAESDECLASTYrr */ }, { /* 3012 */ 206, /* VAESDECLASTZ128rm */ }, { /* 3013 */ 211, /* VAESDECLASTZ128rr */ }, { /* 3014 */ 214, /* VAESDECLASTZ256rm */ }, { /* 3015 */ 220, /* VAESDECLASTZ256rr */ }, { /* 3016 */ 223, /* VAESDECLASTZrm */ }, { /* 3017 */ 229, /* VAESDECLASTZrr */ }, { /* 3018 */ 235, /* VAESDECLASTrm */ }, { /* 3019 */ 236, /* VAESDECLASTrr */ }, { /* 3020 */ 204, /* VAESDECYrm */ }, { /* 3021 */ 205, /* VAESDECYrr */ }, { /* 3022 */ 206, /* VAESDECZ128rm */ }, { /* 3023 */ 211, /* VAESDECZ128rr */ }, { /* 3024 */ 214, /* VAESDECZ256rm */ }, { /* 3025 */ 220, /* VAESDECZ256rr */ }, { /* 3026 */ 223, /* VAESDECZrm */ }, { /* 3027 */ 229, /* VAESDECZrr */ }, { /* 3028 */ 235, /* VAESDECrm */ }, { /* 3029 */ 236, /* VAESDECrr */ }, { /* 3030 */ 204, /* VAESENCLASTYrm */ }, { /* 3031 */ 205, /* VAESENCLASTYrr */ }, { /* 3032 */ 206, /* VAESENCLASTZ128rm */ }, { /* 3033 */ 211, /* VAESENCLASTZ128rr */ }, { /* 3034 */ 214, /* VAESENCLASTZ256rm */ }, { /* 3035 */ 220, /* VAESENCLASTZ256rr */ }, { /* 3036 */ 223, /* VAESENCLASTZrm */ }, { /* 3037 */ 229, /* VAESENCLASTZrr */ }, { /* 3038 */ 235, /* VAESENCLASTrm */ }, { /* 3039 */ 236, /* VAESENCLASTrr */ }, { /* 3040 */ 204, /* VAESENCYrm */ }, { /* 3041 */ 205, /* VAESENCYrr */ }, { /* 3042 */ 206, /* VAESENCZ128rm */ }, { /* 3043 */ 211, /* VAESENCZ128rr */ }, { /* 3044 */ 214, /* VAESENCZ256rm */ }, { /* 3045 */ 220, /* VAESENCZ256rr */ }, { /* 3046 */ 223, /* VAESENCZrm */ }, { /* 3047 */ 229, /* VAESENCZrr */ }, { /* 3048 */ 235, /* VAESENCrm */ }, { /* 3049 */ 236, /* VAESENCrr */ }, { /* 3050 */ 30, /* VAESIMCrm */ }, { /* 3051 */ 31, /* VAESIMCrr */ }, { /* 3052 */ 32, /* VAESKEYGENASSIST128rm */ }, { /* 3053 */ 33, /* VAESKEYGENASSIST128rr */ }, { /* 3054 */ 261, /* VALIGNDZ128rmbi */ }, { /* 3055 */ 262, /* VALIGNDZ128rmbik */ }, { /* 3056 */ 263, /* VALIGNDZ128rmbikz */ }, { /* 3057 */ 264, /* VALIGNDZ128rmi */ }, { /* 3058 */ 265, /* VALIGNDZ128rmik */ }, { /* 3059 */ 266, /* VALIGNDZ128rmikz */ }, { /* 3060 */ 267, /* VALIGNDZ128rri */ }, { /* 3061 */ 268, /* VALIGNDZ128rrik */ }, { /* 3062 */ 269, /* VALIGNDZ128rrikz */ }, { /* 3063 */ 270, /* VALIGNDZ256rmbi */ }, { /* 3064 */ 271, /* VALIGNDZ256rmbik */ }, { /* 3065 */ 272, /* VALIGNDZ256rmbikz */ }, { /* 3066 */ 273, /* VALIGNDZ256rmi */ }, { /* 3067 */ 274, /* VALIGNDZ256rmik */ }, { /* 3068 */ 275, /* VALIGNDZ256rmikz */ }, { /* 3069 */ 276, /* VALIGNDZ256rri */ }, { /* 3070 */ 277, /* VALIGNDZ256rrik */ }, { /* 3071 */ 278, /* VALIGNDZ256rrikz */ }, { /* 3072 */ 279, /* VALIGNDZrmbi */ }, { /* 3073 */ 280, /* VALIGNDZrmbik */ }, { /* 3074 */ 281, /* VALIGNDZrmbikz */ }, { /* 3075 */ 282, /* VALIGNDZrmi */ }, { /* 3076 */ 283, /* VALIGNDZrmik */ }, { /* 3077 */ 284, /* VALIGNDZrmikz */ }, { /* 3078 */ 285, /* VALIGNDZrri */ }, { /* 3079 */ 286, /* VALIGNDZrrik */ }, { /* 3080 */ 287, /* VALIGNDZrrikz */ }, { /* 3081 */ 288, /* VALIGNQZ128rmbi */ }, { /* 3082 */ 289, /* VALIGNQZ128rmbik */ }, { /* 3083 */ 290, /* VALIGNQZ128rmbikz */ }, { /* 3084 */ 264, /* VALIGNQZ128rmi */ }, { /* 3085 */ 265, /* VALIGNQZ128rmik */ }, { /* 3086 */ 266, /* VALIGNQZ128rmikz */ }, { /* 3087 */ 267, /* VALIGNQZ128rri */ }, { /* 3088 */ 268, /* VALIGNQZ128rrik */ }, { /* 3089 */ 269, /* VALIGNQZ128rrikz */ }, { /* 3090 */ 291, /* VALIGNQZ256rmbi */ }, { /* 3091 */ 292, /* VALIGNQZ256rmbik */ }, { /* 3092 */ 293, /* VALIGNQZ256rmbikz */ }, { /* 3093 */ 273, /* VALIGNQZ256rmi */ }, { /* 3094 */ 274, /* VALIGNQZ256rmik */ }, { /* 3095 */ 275, /* VALIGNQZ256rmikz */ }, { /* 3096 */ 276, /* VALIGNQZ256rri */ }, { /* 3097 */ 277, /* VALIGNQZ256rrik */ }, { /* 3098 */ 278, /* VALIGNQZ256rrikz */ }, { /* 3099 */ 294, /* VALIGNQZrmbi */ }, { /* 3100 */ 295, /* VALIGNQZrmbik */ }, { /* 3101 */ 296, /* VALIGNQZrmbikz */ }, { /* 3102 */ 282, /* VALIGNQZrmi */ }, { /* 3103 */ 283, /* VALIGNQZrmik */ }, { /* 3104 */ 284, /* VALIGNQZrmikz */ }, { /* 3105 */ 285, /* VALIGNQZrri */ }, { /* 3106 */ 286, /* VALIGNQZrrik */ }, { /* 3107 */ 287, /* VALIGNQZrrikz */ }, { /* 3108 */ 204, /* VANDNPDYrm */ }, { /* 3109 */ 205, /* VANDNPDYrr */ }, { /* 3110 */ 206, /* VANDNPDZ128rm */ }, { /* 3111 */ 207, /* VANDNPDZ128rmb */ }, { /* 3112 */ 208, /* VANDNPDZ128rmbk */ }, { /* 3113 */ 209, /* VANDNPDZ128rmbkz */ }, { /* 3114 */ 203, /* VANDNPDZ128rmk */ }, { /* 3115 */ 210, /* VANDNPDZ128rmkz */ }, { /* 3116 */ 211, /* VANDNPDZ128rr */ }, { /* 3117 */ 212, /* VANDNPDZ128rrk */ }, { /* 3118 */ 213, /* VANDNPDZ128rrkz */ }, { /* 3119 */ 214, /* VANDNPDZ256rm */ }, { /* 3120 */ 215, /* VANDNPDZ256rmb */ }, { /* 3121 */ 216, /* VANDNPDZ256rmbk */ }, { /* 3122 */ 217, /* VANDNPDZ256rmbkz */ }, { /* 3123 */ 218, /* VANDNPDZ256rmk */ }, { /* 3124 */ 219, /* VANDNPDZ256rmkz */ }, { /* 3125 */ 220, /* VANDNPDZ256rr */ }, { /* 3126 */ 221, /* VANDNPDZ256rrk */ }, { /* 3127 */ 222, /* VANDNPDZ256rrkz */ }, { /* 3128 */ 223, /* VANDNPDZrm */ }, { /* 3129 */ 224, /* VANDNPDZrmb */ }, { /* 3130 */ 225, /* VANDNPDZrmbk */ }, { /* 3131 */ 226, /* VANDNPDZrmbkz */ }, { /* 3132 */ 227, /* VANDNPDZrmk */ }, { /* 3133 */ 228, /* VANDNPDZrmkz */ }, { /* 3134 */ 229, /* VANDNPDZrr */ }, { /* 3135 */ 233, /* VANDNPDZrrk */ }, { /* 3136 */ 234, /* VANDNPDZrrkz */ }, { /* 3137 */ 235, /* VANDNPDrm */ }, { /* 3138 */ 236, /* VANDNPDrr */ }, { /* 3139 */ 204, /* VANDNPSYrm */ }, { /* 3140 */ 205, /* VANDNPSYrr */ }, { /* 3141 */ 206, /* VANDNPSZ128rm */ }, { /* 3142 */ 237, /* VANDNPSZ128rmb */ }, { /* 3143 */ 238, /* VANDNPSZ128rmbk */ }, { /* 3144 */ 239, /* VANDNPSZ128rmbkz */ }, { /* 3145 */ 203, /* VANDNPSZ128rmk */ }, { /* 3146 */ 210, /* VANDNPSZ128rmkz */ }, { /* 3147 */ 211, /* VANDNPSZ128rr */ }, { /* 3148 */ 212, /* VANDNPSZ128rrk */ }, { /* 3149 */ 213, /* VANDNPSZ128rrkz */ }, { /* 3150 */ 214, /* VANDNPSZ256rm */ }, { /* 3151 */ 240, /* VANDNPSZ256rmb */ }, { /* 3152 */ 241, /* VANDNPSZ256rmbk */ }, { /* 3153 */ 242, /* VANDNPSZ256rmbkz */ }, { /* 3154 */ 218, /* VANDNPSZ256rmk */ }, { /* 3155 */ 219, /* VANDNPSZ256rmkz */ }, { /* 3156 */ 220, /* VANDNPSZ256rr */ }, { /* 3157 */ 221, /* VANDNPSZ256rrk */ }, { /* 3158 */ 222, /* VANDNPSZ256rrkz */ }, { /* 3159 */ 223, /* VANDNPSZrm */ }, { /* 3160 */ 243, /* VANDNPSZrmb */ }, { /* 3161 */ 244, /* VANDNPSZrmbk */ }, { /* 3162 */ 245, /* VANDNPSZrmbkz */ }, { /* 3163 */ 227, /* VANDNPSZrmk */ }, { /* 3164 */ 228, /* VANDNPSZrmkz */ }, { /* 3165 */ 229, /* VANDNPSZrr */ }, { /* 3166 */ 233, /* VANDNPSZrrk */ }, { /* 3167 */ 234, /* VANDNPSZrrkz */ }, { /* 3168 */ 235, /* VANDNPSrm */ }, { /* 3169 */ 236, /* VANDNPSrr */ }, { /* 3170 */ 204, /* VANDPDYrm */ }, { /* 3171 */ 205, /* VANDPDYrr */ }, { /* 3172 */ 206, /* VANDPDZ128rm */ }, { /* 3173 */ 207, /* VANDPDZ128rmb */ }, { /* 3174 */ 208, /* VANDPDZ128rmbk */ }, { /* 3175 */ 209, /* VANDPDZ128rmbkz */ }, { /* 3176 */ 203, /* VANDPDZ128rmk */ }, { /* 3177 */ 210, /* VANDPDZ128rmkz */ }, { /* 3178 */ 211, /* VANDPDZ128rr */ }, { /* 3179 */ 212, /* VANDPDZ128rrk */ }, { /* 3180 */ 213, /* VANDPDZ128rrkz */ }, { /* 3181 */ 214, /* VANDPDZ256rm */ }, { /* 3182 */ 215, /* VANDPDZ256rmb */ }, { /* 3183 */ 216, /* VANDPDZ256rmbk */ }, { /* 3184 */ 217, /* VANDPDZ256rmbkz */ }, { /* 3185 */ 218, /* VANDPDZ256rmk */ }, { /* 3186 */ 219, /* VANDPDZ256rmkz */ }, { /* 3187 */ 220, /* VANDPDZ256rr */ }, { /* 3188 */ 221, /* VANDPDZ256rrk */ }, { /* 3189 */ 222, /* VANDPDZ256rrkz */ }, { /* 3190 */ 223, /* VANDPDZrm */ }, { /* 3191 */ 224, /* VANDPDZrmb */ }, { /* 3192 */ 225, /* VANDPDZrmbk */ }, { /* 3193 */ 226, /* VANDPDZrmbkz */ }, { /* 3194 */ 227, /* VANDPDZrmk */ }, { /* 3195 */ 228, /* VANDPDZrmkz */ }, { /* 3196 */ 229, /* VANDPDZrr */ }, { /* 3197 */ 233, /* VANDPDZrrk */ }, { /* 3198 */ 234, /* VANDPDZrrkz */ }, { /* 3199 */ 235, /* VANDPDrm */ }, { /* 3200 */ 236, /* VANDPDrr */ }, { /* 3201 */ 204, /* VANDPSYrm */ }, { /* 3202 */ 205, /* VANDPSYrr */ }, { /* 3203 */ 206, /* VANDPSZ128rm */ }, { /* 3204 */ 237, /* VANDPSZ128rmb */ }, { /* 3205 */ 238, /* VANDPSZ128rmbk */ }, { /* 3206 */ 239, /* VANDPSZ128rmbkz */ }, { /* 3207 */ 203, /* VANDPSZ128rmk */ }, { /* 3208 */ 210, /* VANDPSZ128rmkz */ }, { /* 3209 */ 211, /* VANDPSZ128rr */ }, { /* 3210 */ 212, /* VANDPSZ128rrk */ }, { /* 3211 */ 213, /* VANDPSZ128rrkz */ }, { /* 3212 */ 214, /* VANDPSZ256rm */ }, { /* 3213 */ 240, /* VANDPSZ256rmb */ }, { /* 3214 */ 241, /* VANDPSZ256rmbk */ }, { /* 3215 */ 242, /* VANDPSZ256rmbkz */ }, { /* 3216 */ 218, /* VANDPSZ256rmk */ }, { /* 3217 */ 219, /* VANDPSZ256rmkz */ }, { /* 3218 */ 220, /* VANDPSZ256rr */ }, { /* 3219 */ 221, /* VANDPSZ256rrk */ }, { /* 3220 */ 222, /* VANDPSZ256rrkz */ }, { /* 3221 */ 223, /* VANDPSZrm */ }, { /* 3222 */ 243, /* VANDPSZrmb */ }, { /* 3223 */ 244, /* VANDPSZrmbk */ }, { /* 3224 */ 245, /* VANDPSZrmbkz */ }, { /* 3225 */ 227, /* VANDPSZrmk */ }, { /* 3226 */ 228, /* VANDPSZrmkz */ }, { /* 3227 */ 229, /* VANDPSZrr */ }, { /* 3228 */ 233, /* VANDPSZrrk */ }, { /* 3229 */ 234, /* VANDPSZrrkz */ }, { /* 3230 */ 235, /* VANDPSrm */ }, { /* 3231 */ 236, /* VANDPSrr */ }, { /* 3232 */ 206, /* VBLENDMPDZ128rm */ }, { /* 3233 */ 207, /* VBLENDMPDZ128rmb */ }, { /* 3234 */ 209, /* VBLENDMPDZ128rmbk */ }, { /* 3235 */ 209, /* VBLENDMPDZ128rmbkz */ }, { /* 3236 */ 210, /* VBLENDMPDZ128rmk */ }, { /* 3237 */ 210, /* VBLENDMPDZ128rmkz */ }, { /* 3238 */ 211, /* VBLENDMPDZ128rr */ }, { /* 3239 */ 213, /* VBLENDMPDZ128rrk */ }, { /* 3240 */ 213, /* VBLENDMPDZ128rrkz */ }, { /* 3241 */ 214, /* VBLENDMPDZ256rm */ }, { /* 3242 */ 215, /* VBLENDMPDZ256rmb */ }, { /* 3243 */ 217, /* VBLENDMPDZ256rmbk */ }, { /* 3244 */ 217, /* VBLENDMPDZ256rmbkz */ }, { /* 3245 */ 219, /* VBLENDMPDZ256rmk */ }, { /* 3246 */ 219, /* VBLENDMPDZ256rmkz */ }, { /* 3247 */ 220, /* VBLENDMPDZ256rr */ }, { /* 3248 */ 222, /* VBLENDMPDZ256rrk */ }, { /* 3249 */ 222, /* VBLENDMPDZ256rrkz */ }, { /* 3250 */ 223, /* VBLENDMPDZrm */ }, { /* 3251 */ 224, /* VBLENDMPDZrmb */ }, { /* 3252 */ 226, /* VBLENDMPDZrmbk */ }, { /* 3253 */ 226, /* VBLENDMPDZrmbkz */ }, { /* 3254 */ 228, /* VBLENDMPDZrmk */ }, { /* 3255 */ 228, /* VBLENDMPDZrmkz */ }, { /* 3256 */ 229, /* VBLENDMPDZrr */ }, { /* 3257 */ 234, /* VBLENDMPDZrrk */ }, { /* 3258 */ 234, /* VBLENDMPDZrrkz */ }, { /* 3259 */ 206, /* VBLENDMPSZ128rm */ }, { /* 3260 */ 237, /* VBLENDMPSZ128rmb */ }, { /* 3261 */ 239, /* VBLENDMPSZ128rmbk */ }, { /* 3262 */ 239, /* VBLENDMPSZ128rmbkz */ }, { /* 3263 */ 210, /* VBLENDMPSZ128rmk */ }, { /* 3264 */ 210, /* VBLENDMPSZ128rmkz */ }, { /* 3265 */ 211, /* VBLENDMPSZ128rr */ }, { /* 3266 */ 213, /* VBLENDMPSZ128rrk */ }, { /* 3267 */ 213, /* VBLENDMPSZ128rrkz */ }, { /* 3268 */ 214, /* VBLENDMPSZ256rm */ }, { /* 3269 */ 240, /* VBLENDMPSZ256rmb */ }, { /* 3270 */ 242, /* VBLENDMPSZ256rmbk */ }, { /* 3271 */ 242, /* VBLENDMPSZ256rmbkz */ }, { /* 3272 */ 219, /* VBLENDMPSZ256rmk */ }, { /* 3273 */ 219, /* VBLENDMPSZ256rmkz */ }, { /* 3274 */ 220, /* VBLENDMPSZ256rr */ }, { /* 3275 */ 222, /* VBLENDMPSZ256rrk */ }, { /* 3276 */ 222, /* VBLENDMPSZ256rrkz */ }, { /* 3277 */ 223, /* VBLENDMPSZrm */ }, { /* 3278 */ 243, /* VBLENDMPSZrmb */ }, { /* 3279 */ 245, /* VBLENDMPSZrmbk */ }, { /* 3280 */ 245, /* VBLENDMPSZrmbkz */ }, { /* 3281 */ 228, /* VBLENDMPSZrmk */ }, { /* 3282 */ 228, /* VBLENDMPSZrmkz */ }, { /* 3283 */ 229, /* VBLENDMPSZrr */ }, { /* 3284 */ 234, /* VBLENDMPSZrrk */ }, { /* 3285 */ 234, /* VBLENDMPSZrrkz */ }, { /* 3286 */ 297, /* VBLENDPDYrmi */ }, { /* 3287 */ 298, /* VBLENDPDYrri */ }, { /* 3288 */ 299, /* VBLENDPDrmi */ }, { /* 3289 */ 300, /* VBLENDPDrri */ }, { /* 3290 */ 297, /* VBLENDPSYrmi */ }, { /* 3291 */ 298, /* VBLENDPSYrri */ }, { /* 3292 */ 299, /* VBLENDPSrmi */ }, { /* 3293 */ 300, /* VBLENDPSrri */ }, { /* 3294 */ 301, /* VBLENDVPDYrm */ }, { /* 3295 */ 302, /* VBLENDVPDYrr */ }, { /* 3296 */ 303, /* VBLENDVPDrm */ }, { /* 3297 */ 304, /* VBLENDVPDrr */ }, { /* 3298 */ 301, /* VBLENDVPSYrm */ }, { /* 3299 */ 302, /* VBLENDVPSYrr */ }, { /* 3300 */ 303, /* VBLENDVPSrm */ }, { /* 3301 */ 304, /* VBLENDVPSrr */ }, { /* 3302 */ 305, /* VBROADCASTF128 */ }, { /* 3303 */ 306, /* VBROADCASTF32X2Z256m */ }, { /* 3304 */ 307, /* VBROADCASTF32X2Z256mk */ }, { /* 3305 */ 308, /* VBROADCASTF32X2Z256mkz */ }, { /* 3306 */ 309, /* VBROADCASTF32X2Z256r */ }, { /* 3307 */ 310, /* VBROADCASTF32X2Z256rk */ }, { /* 3308 */ 311, /* VBROADCASTF32X2Z256rkz */ }, { /* 3309 */ 312, /* VBROADCASTF32X2Zm */ }, { /* 3310 */ 313, /* VBROADCASTF32X2Zmk */ }, { /* 3311 */ 314, /* VBROADCASTF32X2Zmkz */ }, { /* 3312 */ 315, /* VBROADCASTF32X2Zr */ }, { /* 3313 */ 316, /* VBROADCASTF32X2Zrk */ }, { /* 3314 */ 317, /* VBROADCASTF32X2Zrkz */ }, { /* 3315 */ 318, /* VBROADCASTF32X4Z256rm */ }, { /* 3316 */ 319, /* VBROADCASTF32X4Z256rmk */ }, { /* 3317 */ 320, /* VBROADCASTF32X4Z256rmkz */ }, { /* 3318 */ 321, /* VBROADCASTF32X4rm */ }, { /* 3319 */ 322, /* VBROADCASTF32X4rmk */ }, { /* 3320 */ 323, /* VBROADCASTF32X4rmkz */ }, { /* 3321 */ 324, /* VBROADCASTF32X8rm */ }, { /* 3322 */ 325, /* VBROADCASTF32X8rmk */ }, { /* 3323 */ 326, /* VBROADCASTF32X8rmkz */ }, { /* 3324 */ 318, /* VBROADCASTF64X2Z128rm */ }, { /* 3325 */ 319, /* VBROADCASTF64X2Z128rmk */ }, { /* 3326 */ 320, /* VBROADCASTF64X2Z128rmkz */ }, { /* 3327 */ 321, /* VBROADCASTF64X2rm */ }, { /* 3328 */ 322, /* VBROADCASTF64X2rmk */ }, { /* 3329 */ 323, /* VBROADCASTF64X2rmkz */ }, { /* 3330 */ 324, /* VBROADCASTF64X4rm */ }, { /* 3331 */ 325, /* VBROADCASTF64X4rmk */ }, { /* 3332 */ 326, /* VBROADCASTF64X4rmkz */ }, { /* 3333 */ 305, /* VBROADCASTI128 */ }, { /* 3334 */ 327, /* VBROADCASTI32X2Z128m */ }, { /* 3335 */ 328, /* VBROADCASTI32X2Z128mk */ }, { /* 3336 */ 329, /* VBROADCASTI32X2Z128mkz */ }, { /* 3337 */ 330, /* VBROADCASTI32X2Z128r */ }, { /* 3338 */ 331, /* VBROADCASTI32X2Z128rk */ }, { /* 3339 */ 332, /* VBROADCASTI32X2Z128rkz */ }, { /* 3340 */ 306, /* VBROADCASTI32X2Z256m */ }, { /* 3341 */ 307, /* VBROADCASTI32X2Z256mk */ }, { /* 3342 */ 308, /* VBROADCASTI32X2Z256mkz */ }, { /* 3343 */ 309, /* VBROADCASTI32X2Z256r */ }, { /* 3344 */ 310, /* VBROADCASTI32X2Z256rk */ }, { /* 3345 */ 311, /* VBROADCASTI32X2Z256rkz */ }, { /* 3346 */ 312, /* VBROADCASTI32X2Zm */ }, { /* 3347 */ 313, /* VBROADCASTI32X2Zmk */ }, { /* 3348 */ 314, /* VBROADCASTI32X2Zmkz */ }, { /* 3349 */ 315, /* VBROADCASTI32X2Zr */ }, { /* 3350 */ 316, /* VBROADCASTI32X2Zrk */ }, { /* 3351 */ 317, /* VBROADCASTI32X2Zrkz */ }, { /* 3352 */ 318, /* VBROADCASTI32X4Z256rm */ }, { /* 3353 */ 319, /* VBROADCASTI32X4Z256rmk */ }, { /* 3354 */ 320, /* VBROADCASTI32X4Z256rmkz */ }, { /* 3355 */ 321, /* VBROADCASTI32X4rm */ }, { /* 3356 */ 322, /* VBROADCASTI32X4rmk */ }, { /* 3357 */ 323, /* VBROADCASTI32X4rmkz */ }, { /* 3358 */ 324, /* VBROADCASTI32X8rm */ }, { /* 3359 */ 325, /* VBROADCASTI32X8rmk */ }, { /* 3360 */ 326, /* VBROADCASTI32X8rmkz */ }, { /* 3361 */ 318, /* VBROADCASTI64X2Z128rm */ }, { /* 3362 */ 319, /* VBROADCASTI64X2Z128rmk */ }, { /* 3363 */ 320, /* VBROADCASTI64X2Z128rmkz */ }, { /* 3364 */ 321, /* VBROADCASTI64X2rm */ }, { /* 3365 */ 322, /* VBROADCASTI64X2rmk */ }, { /* 3366 */ 323, /* VBROADCASTI64X2rmkz */ }, { /* 3367 */ 324, /* VBROADCASTI64X4rm */ }, { /* 3368 */ 325, /* VBROADCASTI64X4rmk */ }, { /* 3369 */ 326, /* VBROADCASTI64X4rmkz */ }, { /* 3370 */ 305, /* VBROADCASTSDYrm */ }, { /* 3371 */ 333, /* VBROADCASTSDYrr */ }, { /* 3372 */ 306, /* VBROADCASTSDZ256m */ }, { /* 3373 */ 307, /* VBROADCASTSDZ256mk */ }, { /* 3374 */ 308, /* VBROADCASTSDZ256mkz */ }, { /* 3375 */ 309, /* VBROADCASTSDZ256r */ }, { /* 3376 */ 310, /* VBROADCASTSDZ256rk */ }, { /* 3377 */ 311, /* VBROADCASTSDZ256rkz */ }, { /* 3378 */ 312, /* VBROADCASTSDZm */ }, { /* 3379 */ 313, /* VBROADCASTSDZmk */ }, { /* 3380 */ 314, /* VBROADCASTSDZmkz */ }, { /* 3381 */ 315, /* VBROADCASTSDZr */ }, { /* 3382 */ 316, /* VBROADCASTSDZrk */ }, { /* 3383 */ 317, /* VBROADCASTSDZrkz */ }, { /* 3384 */ 305, /* VBROADCASTSSYrm */ }, { /* 3385 */ 333, /* VBROADCASTSSYrr */ }, { /* 3386 */ 334, /* VBROADCASTSSZ128m */ }, { /* 3387 */ 335, /* VBROADCASTSSZ128mk */ }, { /* 3388 */ 336, /* VBROADCASTSSZ128mkz */ }, { /* 3389 */ 330, /* VBROADCASTSSZ128r */ }, { /* 3390 */ 331, /* VBROADCASTSSZ128rk */ }, { /* 3391 */ 332, /* VBROADCASTSSZ128rkz */ }, { /* 3392 */ 337, /* VBROADCASTSSZ256m */ }, { /* 3393 */ 338, /* VBROADCASTSSZ256mk */ }, { /* 3394 */ 339, /* VBROADCASTSSZ256mkz */ }, { /* 3395 */ 309, /* VBROADCASTSSZ256r */ }, { /* 3396 */ 310, /* VBROADCASTSSZ256rk */ }, { /* 3397 */ 311, /* VBROADCASTSSZ256rkz */ }, { /* 3398 */ 340, /* VBROADCASTSSZm */ }, { /* 3399 */ 341, /* VBROADCASTSSZmk */ }, { /* 3400 */ 342, /* VBROADCASTSSZmkz */ }, { /* 3401 */ 315, /* VBROADCASTSSZr */ }, { /* 3402 */ 316, /* VBROADCASTSSZrk */ }, { /* 3403 */ 317, /* VBROADCASTSSZrkz */ }, { /* 3404 */ 30, /* VBROADCASTSSrm */ }, { /* 3405 */ 31, /* VBROADCASTSSrr */ }, { /* 3406 */ 343, /* VCMPPDYrmi */ }, { /* 3407 */ 0, /* */ }, { /* 3408 */ 344, /* VCMPPDYrri */ }, { /* 3409 */ 0, /* */ }, { /* 3410 */ 345, /* VCMPPDZ128rmbi */ }, { /* 3411 */ 0, /* */ }, { /* 3412 */ 0, /* */ }, { /* 3413 */ 346, /* VCMPPDZ128rmbik */ }, { /* 3414 */ 347, /* VCMPPDZ128rmi */ }, { /* 3415 */ 0, /* */ }, { /* 3416 */ 0, /* */ }, { /* 3417 */ 348, /* VCMPPDZ128rmik */ }, { /* 3418 */ 349, /* VCMPPDZ128rri */ }, { /* 3419 */ 0, /* */ }, { /* 3420 */ 0, /* */ }, { /* 3421 */ 350, /* VCMPPDZ128rrik */ }, { /* 3422 */ 351, /* VCMPPDZ256rmbi */ }, { /* 3423 */ 0, /* */ }, { /* 3424 */ 0, /* */ }, { /* 3425 */ 352, /* VCMPPDZ256rmbik */ }, { /* 3426 */ 353, /* VCMPPDZ256rmi */ }, { /* 3427 */ 0, /* */ }, { /* 3428 */ 0, /* */ }, { /* 3429 */ 354, /* VCMPPDZ256rmik */ }, { /* 3430 */ 355, /* VCMPPDZ256rri */ }, { /* 3431 */ 0, /* */ }, { /* 3432 */ 0, /* */ }, { /* 3433 */ 356, /* VCMPPDZ256rrik */ }, { /* 3434 */ 357, /* VCMPPDZrmbi */ }, { /* 3435 */ 0, /* */ }, { /* 3436 */ 0, /* */ }, { /* 3437 */ 358, /* VCMPPDZrmbik */ }, { /* 3438 */ 359, /* VCMPPDZrmi */ }, { /* 3439 */ 0, /* */ }, { /* 3440 */ 0, /* */ }, { /* 3441 */ 360, /* VCMPPDZrmik */ }, { /* 3442 */ 361, /* VCMPPDZrri */ }, { /* 3443 */ 0, /* */ }, { /* 3444 */ 0, /* */ }, { /* 3445 */ 362, /* VCMPPDZrrib */ }, { /* 3446 */ 0, /* */ }, { /* 3447 */ 0, /* */ }, { /* 3448 */ 363, /* VCMPPDZrribk */ }, { /* 3449 */ 364, /* VCMPPDZrrik */ }, { /* 3450 */ 365, /* VCMPPDrmi */ }, { /* 3451 */ 0, /* */ }, { /* 3452 */ 366, /* VCMPPDrri */ }, { /* 3453 */ 0, /* */ }, { /* 3454 */ 343, /* VCMPPSYrmi */ }, { /* 3455 */ 0, /* */ }, { /* 3456 */ 344, /* VCMPPSYrri */ }, { /* 3457 */ 0, /* */ }, { /* 3458 */ 367, /* VCMPPSZ128rmbi */ }, { /* 3459 */ 0, /* */ }, { /* 3460 */ 0, /* */ }, { /* 3461 */ 368, /* VCMPPSZ128rmbik */ }, { /* 3462 */ 347, /* VCMPPSZ128rmi */ }, { /* 3463 */ 0, /* */ }, { /* 3464 */ 0, /* */ }, { /* 3465 */ 348, /* VCMPPSZ128rmik */ }, { /* 3466 */ 349, /* VCMPPSZ128rri */ }, { /* 3467 */ 0, /* */ }, { /* 3468 */ 0, /* */ }, { /* 3469 */ 350, /* VCMPPSZ128rrik */ }, { /* 3470 */ 369, /* VCMPPSZ256rmbi */ }, { /* 3471 */ 0, /* */ }, { /* 3472 */ 0, /* */ }, { /* 3473 */ 370, /* VCMPPSZ256rmbik */ }, { /* 3474 */ 353, /* VCMPPSZ256rmi */ }, { /* 3475 */ 0, /* */ }, { /* 3476 */ 0, /* */ }, { /* 3477 */ 354, /* VCMPPSZ256rmik */ }, { /* 3478 */ 355, /* VCMPPSZ256rri */ }, { /* 3479 */ 0, /* */ }, { /* 3480 */ 0, /* */ }, { /* 3481 */ 356, /* VCMPPSZ256rrik */ }, { /* 3482 */ 371, /* VCMPPSZrmbi */ }, { /* 3483 */ 0, /* */ }, { /* 3484 */ 0, /* */ }, { /* 3485 */ 372, /* VCMPPSZrmbik */ }, { /* 3486 */ 359, /* VCMPPSZrmi */ }, { /* 3487 */ 0, /* */ }, { /* 3488 */ 0, /* */ }, { /* 3489 */ 360, /* VCMPPSZrmik */ }, { /* 3490 */ 361, /* VCMPPSZrri */ }, { /* 3491 */ 0, /* */ }, { /* 3492 */ 0, /* */ }, { /* 3493 */ 373, /* VCMPPSZrrib */ }, { /* 3494 */ 0, /* */ }, { /* 3495 */ 0, /* */ }, { /* 3496 */ 374, /* VCMPPSZrribk */ }, { /* 3497 */ 364, /* VCMPPSZrrik */ }, { /* 3498 */ 365, /* VCMPPSrmi */ }, { /* 3499 */ 0, /* */ }, { /* 3500 */ 366, /* VCMPPSrri */ }, { /* 3501 */ 0, /* */ }, { /* 3502 */ 0, /* */ }, { /* 3503 */ 345, /* VCMPSDZrm_Int */ }, { /* 3504 */ 346, /* VCMPSDZrm_Intk */ }, { /* 3505 */ 0, /* */ }, { /* 3506 */ 0, /* */ }, { /* 3507 */ 0, /* */ }, { /* 3508 */ 349, /* VCMPSDZrr_Int */ }, { /* 3509 */ 350, /* VCMPSDZrr_Intk */ }, { /* 3510 */ 375, /* VCMPSDZrrb_Int */ }, { /* 3511 */ 376, /* VCMPSDZrrb_Intk */ }, { /* 3512 */ 0, /* */ }, { /* 3513 */ 0, /* */ }, { /* 3514 */ 0, /* */ }, { /* 3515 */ 0, /* */ }, { /* 3516 */ 365, /* VCMPSDrm */ }, { /* 3517 */ 0, /* */ }, { /* 3518 */ 0, /* */ }, { /* 3519 */ 366, /* VCMPSDrr */ }, { /* 3520 */ 0, /* */ }, { /* 3521 */ 0, /* */ }, { /* 3522 */ 0, /* */ }, { /* 3523 */ 367, /* VCMPSSZrm_Int */ }, { /* 3524 */ 368, /* VCMPSSZrm_Intk */ }, { /* 3525 */ 0, /* */ }, { /* 3526 */ 0, /* */ }, { /* 3527 */ 0, /* */ }, { /* 3528 */ 349, /* VCMPSSZrr_Int */ }, { /* 3529 */ 350, /* VCMPSSZrr_Intk */ }, { /* 3530 */ 375, /* VCMPSSZrrb_Int */ }, { /* 3531 */ 376, /* VCMPSSZrrb_Intk */ }, { /* 3532 */ 0, /* */ }, { /* 3533 */ 0, /* */ }, { /* 3534 */ 0, /* */ }, { /* 3535 */ 0, /* */ }, { /* 3536 */ 365, /* VCMPSSrm */ }, { /* 3537 */ 0, /* */ }, { /* 3538 */ 0, /* */ }, { /* 3539 */ 366, /* VCMPSSrr */ }, { /* 3540 */ 0, /* */ }, { /* 3541 */ 0, /* */ }, { /* 3542 */ 327, /* VCOMISDZrm */ }, { /* 3543 */ 0, /* */ }, { /* 3544 */ 377, /* VCOMISDZrr */ }, { /* 3545 */ 0, /* */ }, { /* 3546 */ 377, /* VCOMISDZrrb */ }, { /* 3547 */ 30, /* VCOMISDrm */ }, { /* 3548 */ 0, /* */ }, { /* 3549 */ 31, /* VCOMISDrr */ }, { /* 3550 */ 0, /* */ }, { /* 3551 */ 334, /* VCOMISSZrm */ }, { /* 3552 */ 0, /* */ }, { /* 3553 */ 378, /* VCOMISSZrr */ }, { /* 3554 */ 0, /* */ }, { /* 3555 */ 378, /* VCOMISSZrrb */ }, { /* 3556 */ 30, /* VCOMISSrm */ }, { /* 3557 */ 0, /* */ }, { /* 3558 */ 31, /* VCOMISSrr */ }, { /* 3559 */ 0, /* */ }, { /* 3560 */ 379, /* VCOMPRESSPDZ128mr */ }, { /* 3561 */ 380, /* VCOMPRESSPDZ128mrk */ }, { /* 3562 */ 381, /* VCOMPRESSPDZ128rr */ }, { /* 3563 */ 382, /* VCOMPRESSPDZ128rrk */ }, { /* 3564 */ 383, /* VCOMPRESSPDZ128rrkz */ }, { /* 3565 */ 384, /* VCOMPRESSPDZ256mr */ }, { /* 3566 */ 385, /* VCOMPRESSPDZ256mrk */ }, { /* 3567 */ 386, /* VCOMPRESSPDZ256rr */ }, { /* 3568 */ 387, /* VCOMPRESSPDZ256rrk */ }, { /* 3569 */ 388, /* VCOMPRESSPDZ256rrkz */ }, { /* 3570 */ 389, /* VCOMPRESSPDZmr */ }, { /* 3571 */ 390, /* VCOMPRESSPDZmrk */ }, { /* 3572 */ 391, /* VCOMPRESSPDZrr */ }, { /* 3573 */ 392, /* VCOMPRESSPDZrrk */ }, { /* 3574 */ 393, /* VCOMPRESSPDZrrkz */ }, { /* 3575 */ 394, /* VCOMPRESSPSZ128mr */ }, { /* 3576 */ 395, /* VCOMPRESSPSZ128mrk */ }, { /* 3577 */ 381, /* VCOMPRESSPSZ128rr */ }, { /* 3578 */ 382, /* VCOMPRESSPSZ128rrk */ }, { /* 3579 */ 383, /* VCOMPRESSPSZ128rrkz */ }, { /* 3580 */ 396, /* VCOMPRESSPSZ256mr */ }, { /* 3581 */ 397, /* VCOMPRESSPSZ256mrk */ }, { /* 3582 */ 386, /* VCOMPRESSPSZ256rr */ }, { /* 3583 */ 387, /* VCOMPRESSPSZ256rrk */ }, { /* 3584 */ 388, /* VCOMPRESSPSZ256rrkz */ }, { /* 3585 */ 398, /* VCOMPRESSPSZmr */ }, { /* 3586 */ 399, /* VCOMPRESSPSZmrk */ }, { /* 3587 */ 391, /* VCOMPRESSPSZrr */ }, { /* 3588 */ 392, /* VCOMPRESSPSZrrk */ }, { /* 3589 */ 393, /* VCOMPRESSPSZrrkz */ }, { /* 3590 */ 305, /* VCVTDQ2PDYrm */ }, { /* 3591 */ 333, /* VCVTDQ2PDYrr */ }, { /* 3592 */ 327, /* VCVTDQ2PDZ128rm */ }, { /* 3593 */ 334, /* VCVTDQ2PDZ128rmb */ }, { /* 3594 */ 335, /* VCVTDQ2PDZ128rmbk */ }, { /* 3595 */ 336, /* VCVTDQ2PDZ128rmbkz */ }, { /* 3596 */ 328, /* VCVTDQ2PDZ128rmk */ }, { /* 3597 */ 329, /* VCVTDQ2PDZ128rmkz */ }, { /* 3598 */ 377, /* VCVTDQ2PDZ128rr */ }, { /* 3599 */ 400, /* VCVTDQ2PDZ128rrk */ }, { /* 3600 */ 401, /* VCVTDQ2PDZ128rrkz */ }, { /* 3601 */ 318, /* VCVTDQ2PDZ256rm */ }, { /* 3602 */ 337, /* VCVTDQ2PDZ256rmb */ }, { /* 3603 */ 338, /* VCVTDQ2PDZ256rmbk */ }, { /* 3604 */ 339, /* VCVTDQ2PDZ256rmbkz */ }, { /* 3605 */ 319, /* VCVTDQ2PDZ256rmk */ }, { /* 3606 */ 320, /* VCVTDQ2PDZ256rmkz */ }, { /* 3607 */ 402, /* VCVTDQ2PDZ256rr */ }, { /* 3608 */ 403, /* VCVTDQ2PDZ256rrk */ }, { /* 3609 */ 404, /* VCVTDQ2PDZ256rrkz */ }, { /* 3610 */ 324, /* VCVTDQ2PDZrm */ }, { /* 3611 */ 340, /* VCVTDQ2PDZrmb */ }, { /* 3612 */ 341, /* VCVTDQ2PDZrmbk */ }, { /* 3613 */ 342, /* VCVTDQ2PDZrmbkz */ }, { /* 3614 */ 325, /* VCVTDQ2PDZrmk */ }, { /* 3615 */ 326, /* VCVTDQ2PDZrmkz */ }, { /* 3616 */ 405, /* VCVTDQ2PDZrr */ }, { /* 3617 */ 406, /* VCVTDQ2PDZrrk */ }, { /* 3618 */ 407, /* VCVTDQ2PDZrrkz */ }, { /* 3619 */ 30, /* VCVTDQ2PDrm */ }, { /* 3620 */ 31, /* VCVTDQ2PDrr */ }, { /* 3621 */ 305, /* VCVTDQ2PSYrm */ }, { /* 3622 */ 408, /* VCVTDQ2PSYrr */ }, { /* 3623 */ 409, /* VCVTDQ2PSZ128rm */ }, { /* 3624 */ 334, /* VCVTDQ2PSZ128rmb */ }, { /* 3625 */ 335, /* VCVTDQ2PSZ128rmbk */ }, { /* 3626 */ 336, /* VCVTDQ2PSZ128rmbkz */ }, { /* 3627 */ 410, /* VCVTDQ2PSZ128rmk */ }, { /* 3628 */ 411, /* VCVTDQ2PSZ128rmkz */ }, { /* 3629 */ 330, /* VCVTDQ2PSZ128rr */ }, { /* 3630 */ 331, /* VCVTDQ2PSZ128rrk */ }, { /* 3631 */ 332, /* VCVTDQ2PSZ128rrkz */ }, { /* 3632 */ 412, /* VCVTDQ2PSZ256rm */ }, { /* 3633 */ 337, /* VCVTDQ2PSZ256rmb */ }, { /* 3634 */ 338, /* VCVTDQ2PSZ256rmbk */ }, { /* 3635 */ 339, /* VCVTDQ2PSZ256rmbkz */ }, { /* 3636 */ 413, /* VCVTDQ2PSZ256rmk */ }, { /* 3637 */ 414, /* VCVTDQ2PSZ256rmkz */ }, { /* 3638 */ 415, /* VCVTDQ2PSZ256rr */ }, { /* 3639 */ 416, /* VCVTDQ2PSZ256rrk */ }, { /* 3640 */ 417, /* VCVTDQ2PSZ256rrkz */ }, { /* 3641 */ 418, /* VCVTDQ2PSZrm */ }, { /* 3642 */ 340, /* VCVTDQ2PSZrmb */ }, { /* 3643 */ 341, /* VCVTDQ2PSZrmbk */ }, { /* 3644 */ 342, /* VCVTDQ2PSZrmbkz */ }, { /* 3645 */ 419, /* VCVTDQ2PSZrmk */ }, { /* 3646 */ 420, /* VCVTDQ2PSZrmkz */ }, { /* 3647 */ 421, /* VCVTDQ2PSZrr */ }, { /* 3648 */ 422, /* VCVTDQ2PSZrrb */ }, { /* 3649 */ 423, /* VCVTDQ2PSZrrbk */ }, { /* 3650 */ 424, /* VCVTDQ2PSZrrbkz */ }, { /* 3651 */ 425, /* VCVTDQ2PSZrrk */ }, { /* 3652 */ 426, /* VCVTDQ2PSZrrkz */ }, { /* 3653 */ 30, /* VCVTDQ2PSrm */ }, { /* 3654 */ 31, /* VCVTDQ2PSrr */ }, { /* 3655 */ 30, /* VCVTPD2DQYrm */ }, { /* 3656 */ 427, /* VCVTPD2DQYrr */ }, { /* 3657 */ 409, /* VCVTPD2DQZ128rm */ }, { /* 3658 */ 327, /* VCVTPD2DQZ128rmb */ }, { /* 3659 */ 328, /* VCVTPD2DQZ128rmbk */ }, { /* 3660 */ 329, /* VCVTPD2DQZ128rmbkz */ }, { /* 3661 */ 410, /* VCVTPD2DQZ128rmk */ }, { /* 3662 */ 411, /* VCVTPD2DQZ128rmkz */ }, { /* 3663 */ 330, /* VCVTPD2DQZ128rr */ }, { /* 3664 */ 331, /* VCVTPD2DQZ128rrk */ }, { /* 3665 */ 332, /* VCVTPD2DQZ128rrkz */ }, { /* 3666 */ 428, /* VCVTPD2DQZ256rm */ }, { /* 3667 */ 327, /* VCVTPD2DQZ256rmb */ }, { /* 3668 */ 328, /* VCVTPD2DQZ256rmbk */ }, { /* 3669 */ 329, /* VCVTPD2DQZ256rmbkz */ }, { /* 3670 */ 429, /* VCVTPD2DQZ256rmk */ }, { /* 3671 */ 430, /* VCVTPD2DQZ256rmkz */ }, { /* 3672 */ 431, /* VCVTPD2DQZ256rr */ }, { /* 3673 */ 432, /* VCVTPD2DQZ256rrk */ }, { /* 3674 */ 433, /* VCVTPD2DQZ256rrkz */ }, { /* 3675 */ 434, /* VCVTPD2DQZrm */ }, { /* 3676 */ 306, /* VCVTPD2DQZrmb */ }, { /* 3677 */ 307, /* VCVTPD2DQZrmbk */ }, { /* 3678 */ 308, /* VCVTPD2DQZrmbkz */ }, { /* 3679 */ 435, /* VCVTPD2DQZrmk */ }, { /* 3680 */ 436, /* VCVTPD2DQZrmkz */ }, { /* 3681 */ 437, /* VCVTPD2DQZrr */ }, { /* 3682 */ 438, /* VCVTPD2DQZrrb */ }, { /* 3683 */ 439, /* VCVTPD2DQZrrbk */ }, { /* 3684 */ 440, /* VCVTPD2DQZrrbkz */ }, { /* 3685 */ 441, /* VCVTPD2DQZrrk */ }, { /* 3686 */ 442, /* VCVTPD2DQZrrkz */ }, { /* 3687 */ 30, /* VCVTPD2DQrm */ }, { /* 3688 */ 31, /* VCVTPD2DQrr */ }, { /* 3689 */ 30, /* VCVTPD2PSYrm */ }, { /* 3690 */ 427, /* VCVTPD2PSYrr */ }, { /* 3691 */ 409, /* VCVTPD2PSZ128rm */ }, { /* 3692 */ 327, /* VCVTPD2PSZ128rmb */ }, { /* 3693 */ 328, /* VCVTPD2PSZ128rmbk */ }, { /* 3694 */ 329, /* VCVTPD2PSZ128rmbkz */ }, { /* 3695 */ 410, /* VCVTPD2PSZ128rmk */ }, { /* 3696 */ 411, /* VCVTPD2PSZ128rmkz */ }, { /* 3697 */ 330, /* VCVTPD2PSZ128rr */ }, { /* 3698 */ 331, /* VCVTPD2PSZ128rrk */ }, { /* 3699 */ 332, /* VCVTPD2PSZ128rrkz */ }, { /* 3700 */ 428, /* VCVTPD2PSZ256rm */ }, { /* 3701 */ 327, /* VCVTPD2PSZ256rmb */ }, { /* 3702 */ 328, /* VCVTPD2PSZ256rmbk */ }, { /* 3703 */ 329, /* VCVTPD2PSZ256rmbkz */ }, { /* 3704 */ 429, /* VCVTPD2PSZ256rmk */ }, { /* 3705 */ 430, /* VCVTPD2PSZ256rmkz */ }, { /* 3706 */ 431, /* VCVTPD2PSZ256rr */ }, { /* 3707 */ 432, /* VCVTPD2PSZ256rrk */ }, { /* 3708 */ 433, /* VCVTPD2PSZ256rrkz */ }, { /* 3709 */ 434, /* VCVTPD2PSZrm */ }, { /* 3710 */ 306, /* VCVTPD2PSZrmb */ }, { /* 3711 */ 307, /* VCVTPD2PSZrmbk */ }, { /* 3712 */ 308, /* VCVTPD2PSZrmbkz */ }, { /* 3713 */ 435, /* VCVTPD2PSZrmk */ }, { /* 3714 */ 436, /* VCVTPD2PSZrmkz */ }, { /* 3715 */ 437, /* VCVTPD2PSZrr */ }, { /* 3716 */ 438, /* VCVTPD2PSZrrb */ }, { /* 3717 */ 439, /* VCVTPD2PSZrrbk */ }, { /* 3718 */ 440, /* VCVTPD2PSZrrbkz */ }, { /* 3719 */ 441, /* VCVTPD2PSZrrk */ }, { /* 3720 */ 442, /* VCVTPD2PSZrrkz */ }, { /* 3721 */ 30, /* VCVTPD2PSrm */ }, { /* 3722 */ 31, /* VCVTPD2PSrr */ }, { /* 3723 */ 409, /* VCVTPD2QQZ128rm */ }, { /* 3724 */ 327, /* VCVTPD2QQZ128rmb */ }, { /* 3725 */ 328, /* VCVTPD2QQZ128rmbk */ }, { /* 3726 */ 329, /* VCVTPD2QQZ128rmbkz */ }, { /* 3727 */ 410, /* VCVTPD2QQZ128rmk */ }, { /* 3728 */ 411, /* VCVTPD2QQZ128rmkz */ }, { /* 3729 */ 330, /* VCVTPD2QQZ128rr */ }, { /* 3730 */ 331, /* VCVTPD2QQZ128rrk */ }, { /* 3731 */ 332, /* VCVTPD2QQZ128rrkz */ }, { /* 3732 */ 412, /* VCVTPD2QQZ256rm */ }, { /* 3733 */ 306, /* VCVTPD2QQZ256rmb */ }, { /* 3734 */ 307, /* VCVTPD2QQZ256rmbk */ }, { /* 3735 */ 308, /* VCVTPD2QQZ256rmbkz */ }, { /* 3736 */ 413, /* VCVTPD2QQZ256rmk */ }, { /* 3737 */ 414, /* VCVTPD2QQZ256rmkz */ }, { /* 3738 */ 415, /* VCVTPD2QQZ256rr */ }, { /* 3739 */ 416, /* VCVTPD2QQZ256rrk */ }, { /* 3740 */ 417, /* VCVTPD2QQZ256rrkz */ }, { /* 3741 */ 418, /* VCVTPD2QQZrm */ }, { /* 3742 */ 312, /* VCVTPD2QQZrmb */ }, { /* 3743 */ 313, /* VCVTPD2QQZrmbk */ }, { /* 3744 */ 314, /* VCVTPD2QQZrmbkz */ }, { /* 3745 */ 419, /* VCVTPD2QQZrmk */ }, { /* 3746 */ 420, /* VCVTPD2QQZrmkz */ }, { /* 3747 */ 421, /* VCVTPD2QQZrr */ }, { /* 3748 */ 443, /* VCVTPD2QQZrrb */ }, { /* 3749 */ 444, /* VCVTPD2QQZrrbk */ }, { /* 3750 */ 445, /* VCVTPD2QQZrrbkz */ }, { /* 3751 */ 425, /* VCVTPD2QQZrrk */ }, { /* 3752 */ 426, /* VCVTPD2QQZrrkz */ }, { /* 3753 */ 409, /* VCVTPD2UDQZ128rm */ }, { /* 3754 */ 327, /* VCVTPD2UDQZ128rmb */ }, { /* 3755 */ 328, /* VCVTPD2UDQZ128rmbk */ }, { /* 3756 */ 329, /* VCVTPD2UDQZ128rmbkz */ }, { /* 3757 */ 410, /* VCVTPD2UDQZ128rmk */ }, { /* 3758 */ 411, /* VCVTPD2UDQZ128rmkz */ }, { /* 3759 */ 330, /* VCVTPD2UDQZ128rr */ }, { /* 3760 */ 331, /* VCVTPD2UDQZ128rrk */ }, { /* 3761 */ 332, /* VCVTPD2UDQZ128rrkz */ }, { /* 3762 */ 428, /* VCVTPD2UDQZ256rm */ }, { /* 3763 */ 327, /* VCVTPD2UDQZ256rmb */ }, { /* 3764 */ 328, /* VCVTPD2UDQZ256rmbk */ }, { /* 3765 */ 329, /* VCVTPD2UDQZ256rmbkz */ }, { /* 3766 */ 429, /* VCVTPD2UDQZ256rmk */ }, { /* 3767 */ 430, /* VCVTPD2UDQZ256rmkz */ }, { /* 3768 */ 431, /* VCVTPD2UDQZ256rr */ }, { /* 3769 */ 432, /* VCVTPD2UDQZ256rrk */ }, { /* 3770 */ 433, /* VCVTPD2UDQZ256rrkz */ }, { /* 3771 */ 434, /* VCVTPD2UDQZrm */ }, { /* 3772 */ 306, /* VCVTPD2UDQZrmb */ }, { /* 3773 */ 307, /* VCVTPD2UDQZrmbk */ }, { /* 3774 */ 308, /* VCVTPD2UDQZrmbkz */ }, { /* 3775 */ 435, /* VCVTPD2UDQZrmk */ }, { /* 3776 */ 436, /* VCVTPD2UDQZrmkz */ }, { /* 3777 */ 437, /* VCVTPD2UDQZrr */ }, { /* 3778 */ 438, /* VCVTPD2UDQZrrb */ }, { /* 3779 */ 439, /* VCVTPD2UDQZrrbk */ }, { /* 3780 */ 440, /* VCVTPD2UDQZrrbkz */ }, { /* 3781 */ 441, /* VCVTPD2UDQZrrk */ }, { /* 3782 */ 442, /* VCVTPD2UDQZrrkz */ }, { /* 3783 */ 409, /* VCVTPD2UQQZ128rm */ }, { /* 3784 */ 327, /* VCVTPD2UQQZ128rmb */ }, { /* 3785 */ 328, /* VCVTPD2UQQZ128rmbk */ }, { /* 3786 */ 329, /* VCVTPD2UQQZ128rmbkz */ }, { /* 3787 */ 410, /* VCVTPD2UQQZ128rmk */ }, { /* 3788 */ 411, /* VCVTPD2UQQZ128rmkz */ }, { /* 3789 */ 330, /* VCVTPD2UQQZ128rr */ }, { /* 3790 */ 331, /* VCVTPD2UQQZ128rrk */ }, { /* 3791 */ 332, /* VCVTPD2UQQZ128rrkz */ }, { /* 3792 */ 412, /* VCVTPD2UQQZ256rm */ }, { /* 3793 */ 306, /* VCVTPD2UQQZ256rmb */ }, { /* 3794 */ 307, /* VCVTPD2UQQZ256rmbk */ }, { /* 3795 */ 308, /* VCVTPD2UQQZ256rmbkz */ }, { /* 3796 */ 413, /* VCVTPD2UQQZ256rmk */ }, { /* 3797 */ 414, /* VCVTPD2UQQZ256rmkz */ }, { /* 3798 */ 415, /* VCVTPD2UQQZ256rr */ }, { /* 3799 */ 416, /* VCVTPD2UQQZ256rrk */ }, { /* 3800 */ 417, /* VCVTPD2UQQZ256rrkz */ }, { /* 3801 */ 418, /* VCVTPD2UQQZrm */ }, { /* 3802 */ 312, /* VCVTPD2UQQZrmb */ }, { /* 3803 */ 313, /* VCVTPD2UQQZrmbk */ }, { /* 3804 */ 314, /* VCVTPD2UQQZrmbkz */ }, { /* 3805 */ 419, /* VCVTPD2UQQZrmk */ }, { /* 3806 */ 420, /* VCVTPD2UQQZrmkz */ }, { /* 3807 */ 421, /* VCVTPD2UQQZrr */ }, { /* 3808 */ 443, /* VCVTPD2UQQZrrb */ }, { /* 3809 */ 444, /* VCVTPD2UQQZrrbk */ }, { /* 3810 */ 445, /* VCVTPD2UQQZrrbkz */ }, { /* 3811 */ 425, /* VCVTPD2UQQZrrk */ }, { /* 3812 */ 426, /* VCVTPD2UQQZrrkz */ }, { /* 3813 */ 305, /* VCVTPH2PSYrm */ }, { /* 3814 */ 333, /* VCVTPH2PSYrr */ }, { /* 3815 */ 327, /* VCVTPH2PSZ128rm */ }, { /* 3816 */ 328, /* VCVTPH2PSZ128rmk */ }, { /* 3817 */ 329, /* VCVTPH2PSZ128rmkz */ }, { /* 3818 */ 377, /* VCVTPH2PSZ128rr */ }, { /* 3819 */ 400, /* VCVTPH2PSZ128rrk */ }, { /* 3820 */ 401, /* VCVTPH2PSZ128rrkz */ }, { /* 3821 */ 318, /* VCVTPH2PSZ256rm */ }, { /* 3822 */ 319, /* VCVTPH2PSZ256rmk */ }, { /* 3823 */ 320, /* VCVTPH2PSZ256rmkz */ }, { /* 3824 */ 402, /* VCVTPH2PSZ256rr */ }, { /* 3825 */ 403, /* VCVTPH2PSZ256rrk */ }, { /* 3826 */ 404, /* VCVTPH2PSZ256rrkz */ }, { /* 3827 */ 324, /* VCVTPH2PSZrm */ }, { /* 3828 */ 325, /* VCVTPH2PSZrmk */ }, { /* 3829 */ 326, /* VCVTPH2PSZrmkz */ }, { /* 3830 */ 405, /* VCVTPH2PSZrr */ }, { /* 3831 */ 446, /* VCVTPH2PSZrrb */ }, { /* 3832 */ 447, /* VCVTPH2PSZrrbk */ }, { /* 3833 */ 448, /* VCVTPH2PSZrrbkz */ }, { /* 3834 */ 406, /* VCVTPH2PSZrrk */ }, { /* 3835 */ 407, /* VCVTPH2PSZrrkz */ }, { /* 3836 */ 30, /* VCVTPH2PSrm */ }, { /* 3837 */ 31, /* VCVTPH2PSrr */ }, { /* 3838 */ 305, /* VCVTPS2DQYrm */ }, { /* 3839 */ 408, /* VCVTPS2DQYrr */ }, { /* 3840 */ 409, /* VCVTPS2DQZ128rm */ }, { /* 3841 */ 334, /* VCVTPS2DQZ128rmb */ }, { /* 3842 */ 335, /* VCVTPS2DQZ128rmbk */ }, { /* 3843 */ 336, /* VCVTPS2DQZ128rmbkz */ }, { /* 3844 */ 410, /* VCVTPS2DQZ128rmk */ }, { /* 3845 */ 411, /* VCVTPS2DQZ128rmkz */ }, { /* 3846 */ 330, /* VCVTPS2DQZ128rr */ }, { /* 3847 */ 331, /* VCVTPS2DQZ128rrk */ }, { /* 3848 */ 332, /* VCVTPS2DQZ128rrkz */ }, { /* 3849 */ 412, /* VCVTPS2DQZ256rm */ }, { /* 3850 */ 337, /* VCVTPS2DQZ256rmb */ }, { /* 3851 */ 338, /* VCVTPS2DQZ256rmbk */ }, { /* 3852 */ 339, /* VCVTPS2DQZ256rmbkz */ }, { /* 3853 */ 413, /* VCVTPS2DQZ256rmk */ }, { /* 3854 */ 414, /* VCVTPS2DQZ256rmkz */ }, { /* 3855 */ 415, /* VCVTPS2DQZ256rr */ }, { /* 3856 */ 416, /* VCVTPS2DQZ256rrk */ }, { /* 3857 */ 417, /* VCVTPS2DQZ256rrkz */ }, { /* 3858 */ 418, /* VCVTPS2DQZrm */ }, { /* 3859 */ 340, /* VCVTPS2DQZrmb */ }, { /* 3860 */ 341, /* VCVTPS2DQZrmbk */ }, { /* 3861 */ 342, /* VCVTPS2DQZrmbkz */ }, { /* 3862 */ 419, /* VCVTPS2DQZrmk */ }, { /* 3863 */ 420, /* VCVTPS2DQZrmkz */ }, { /* 3864 */ 421, /* VCVTPS2DQZrr */ }, { /* 3865 */ 422, /* VCVTPS2DQZrrb */ }, { /* 3866 */ 423, /* VCVTPS2DQZrrbk */ }, { /* 3867 */ 424, /* VCVTPS2DQZrrbkz */ }, { /* 3868 */ 425, /* VCVTPS2DQZrrk */ }, { /* 3869 */ 426, /* VCVTPS2DQZrrkz */ }, { /* 3870 */ 30, /* VCVTPS2DQrm */ }, { /* 3871 */ 31, /* VCVTPS2DQrr */ }, { /* 3872 */ 305, /* VCVTPS2PDYrm */ }, { /* 3873 */ 333, /* VCVTPS2PDYrr */ }, { /* 3874 */ 327, /* VCVTPS2PDZ128rm */ }, { /* 3875 */ 334, /* VCVTPS2PDZ128rmb */ }, { /* 3876 */ 335, /* VCVTPS2PDZ128rmbk */ }, { /* 3877 */ 336, /* VCVTPS2PDZ128rmbkz */ }, { /* 3878 */ 328, /* VCVTPS2PDZ128rmk */ }, { /* 3879 */ 329, /* VCVTPS2PDZ128rmkz */ }, { /* 3880 */ 377, /* VCVTPS2PDZ128rr */ }, { /* 3881 */ 400, /* VCVTPS2PDZ128rrk */ }, { /* 3882 */ 401, /* VCVTPS2PDZ128rrkz */ }, { /* 3883 */ 318, /* VCVTPS2PDZ256rm */ }, { /* 3884 */ 337, /* VCVTPS2PDZ256rmb */ }, { /* 3885 */ 338, /* VCVTPS2PDZ256rmbk */ }, { /* 3886 */ 339, /* VCVTPS2PDZ256rmbkz */ }, { /* 3887 */ 319, /* VCVTPS2PDZ256rmk */ }, { /* 3888 */ 320, /* VCVTPS2PDZ256rmkz */ }, { /* 3889 */ 402, /* VCVTPS2PDZ256rr */ }, { /* 3890 */ 403, /* VCVTPS2PDZ256rrk */ }, { /* 3891 */ 404, /* VCVTPS2PDZ256rrkz */ }, { /* 3892 */ 324, /* VCVTPS2PDZrm */ }, { /* 3893 */ 340, /* VCVTPS2PDZrmb */ }, { /* 3894 */ 341, /* VCVTPS2PDZrmbk */ }, { /* 3895 */ 342, /* VCVTPS2PDZrmbkz */ }, { /* 3896 */ 325, /* VCVTPS2PDZrmk */ }, { /* 3897 */ 326, /* VCVTPS2PDZrmkz */ }, { /* 3898 */ 405, /* VCVTPS2PDZrr */ }, { /* 3899 */ 446, /* VCVTPS2PDZrrb */ }, { /* 3900 */ 447, /* VCVTPS2PDZrrbk */ }, { /* 3901 */ 448, /* VCVTPS2PDZrrbkz */ }, { /* 3902 */ 406, /* VCVTPS2PDZrrk */ }, { /* 3903 */ 407, /* VCVTPS2PDZrrkz */ }, { /* 3904 */ 30, /* VCVTPS2PDrm */ }, { /* 3905 */ 31, /* VCVTPS2PDrr */ }, { /* 3906 */ 449, /* VCVTPS2PHYmr */ }, { /* 3907 */ 450, /* VCVTPS2PHYrr */ }, { /* 3908 */ 451, /* VCVTPS2PHZ128mr */ }, { /* 3909 */ 452, /* VCVTPS2PHZ128mrk */ }, { /* 3910 */ 453, /* VCVTPS2PHZ128rr */ }, { /* 3911 */ 454, /* VCVTPS2PHZ128rrk */ }, { /* 3912 */ 455, /* VCVTPS2PHZ128rrkz */ }, { /* 3913 */ 456, /* VCVTPS2PHZ256mr */ }, { /* 3914 */ 457, /* VCVTPS2PHZ256mrk */ }, { /* 3915 */ 458, /* VCVTPS2PHZ256rr */ }, { /* 3916 */ 459, /* VCVTPS2PHZ256rrk */ }, { /* 3917 */ 460, /* VCVTPS2PHZ256rrkz */ }, { /* 3918 */ 461, /* VCVTPS2PHZmr */ }, { /* 3919 */ 462, /* VCVTPS2PHZmrk */ }, { /* 3920 */ 463, /* VCVTPS2PHZrr */ }, { /* 3921 */ 464, /* VCVTPS2PHZrrb */ }, { /* 3922 */ 465, /* VCVTPS2PHZrrbk */ }, { /* 3923 */ 466, /* VCVTPS2PHZrrbkz */ }, { /* 3924 */ 467, /* VCVTPS2PHZrrk */ }, { /* 3925 */ 468, /* VCVTPS2PHZrrkz */ }, { /* 3926 */ 96, /* VCVTPS2PHmr */ }, { /* 3927 */ 469, /* VCVTPS2PHrr */ }, { /* 3928 */ 327, /* VCVTPS2QQZ128rm */ }, { /* 3929 */ 334, /* VCVTPS2QQZ128rmb */ }, { /* 3930 */ 335, /* VCVTPS2QQZ128rmbk */ }, { /* 3931 */ 336, /* VCVTPS2QQZ128rmbkz */ }, { /* 3932 */ 328, /* VCVTPS2QQZ128rmk */ }, { /* 3933 */ 329, /* VCVTPS2QQZ128rmkz */ }, { /* 3934 */ 377, /* VCVTPS2QQZ128rr */ }, { /* 3935 */ 400, /* VCVTPS2QQZ128rrk */ }, { /* 3936 */ 401, /* VCVTPS2QQZ128rrkz */ }, { /* 3937 */ 318, /* VCVTPS2QQZ256rm */ }, { /* 3938 */ 337, /* VCVTPS2QQZ256rmb */ }, { /* 3939 */ 338, /* VCVTPS2QQZ256rmbk */ }, { /* 3940 */ 339, /* VCVTPS2QQZ256rmbkz */ }, { /* 3941 */ 319, /* VCVTPS2QQZ256rmk */ }, { /* 3942 */ 320, /* VCVTPS2QQZ256rmkz */ }, { /* 3943 */ 402, /* VCVTPS2QQZ256rr */ }, { /* 3944 */ 403, /* VCVTPS2QQZ256rrk */ }, { /* 3945 */ 404, /* VCVTPS2QQZ256rrkz */ }, { /* 3946 */ 324, /* VCVTPS2QQZrm */ }, { /* 3947 */ 340, /* VCVTPS2QQZrmb */ }, { /* 3948 */ 341, /* VCVTPS2QQZrmbk */ }, { /* 3949 */ 342, /* VCVTPS2QQZrmbkz */ }, { /* 3950 */ 325, /* VCVTPS2QQZrmk */ }, { /* 3951 */ 326, /* VCVTPS2QQZrmkz */ }, { /* 3952 */ 405, /* VCVTPS2QQZrr */ }, { /* 3953 */ 470, /* VCVTPS2QQZrrb */ }, { /* 3954 */ 471, /* VCVTPS2QQZrrbk */ }, { /* 3955 */ 472, /* VCVTPS2QQZrrbkz */ }, { /* 3956 */ 406, /* VCVTPS2QQZrrk */ }, { /* 3957 */ 407, /* VCVTPS2QQZrrkz */ }, { /* 3958 */ 409, /* VCVTPS2UDQZ128rm */ }, { /* 3959 */ 334, /* VCVTPS2UDQZ128rmb */ }, { /* 3960 */ 335, /* VCVTPS2UDQZ128rmbk */ }, { /* 3961 */ 336, /* VCVTPS2UDQZ128rmbkz */ }, { /* 3962 */ 410, /* VCVTPS2UDQZ128rmk */ }, { /* 3963 */ 411, /* VCVTPS2UDQZ128rmkz */ }, { /* 3964 */ 330, /* VCVTPS2UDQZ128rr */ }, { /* 3965 */ 331, /* VCVTPS2UDQZ128rrk */ }, { /* 3966 */ 332, /* VCVTPS2UDQZ128rrkz */ }, { /* 3967 */ 412, /* VCVTPS2UDQZ256rm */ }, { /* 3968 */ 337, /* VCVTPS2UDQZ256rmb */ }, { /* 3969 */ 338, /* VCVTPS2UDQZ256rmbk */ }, { /* 3970 */ 339, /* VCVTPS2UDQZ256rmbkz */ }, { /* 3971 */ 413, /* VCVTPS2UDQZ256rmk */ }, { /* 3972 */ 414, /* VCVTPS2UDQZ256rmkz */ }, { /* 3973 */ 415, /* VCVTPS2UDQZ256rr */ }, { /* 3974 */ 416, /* VCVTPS2UDQZ256rrk */ }, { /* 3975 */ 417, /* VCVTPS2UDQZ256rrkz */ }, { /* 3976 */ 418, /* VCVTPS2UDQZrm */ }, { /* 3977 */ 340, /* VCVTPS2UDQZrmb */ }, { /* 3978 */ 341, /* VCVTPS2UDQZrmbk */ }, { /* 3979 */ 342, /* VCVTPS2UDQZrmbkz */ }, { /* 3980 */ 419, /* VCVTPS2UDQZrmk */ }, { /* 3981 */ 420, /* VCVTPS2UDQZrmkz */ }, { /* 3982 */ 421, /* VCVTPS2UDQZrr */ }, { /* 3983 */ 422, /* VCVTPS2UDQZrrb */ }, { /* 3984 */ 423, /* VCVTPS2UDQZrrbk */ }, { /* 3985 */ 424, /* VCVTPS2UDQZrrbkz */ }, { /* 3986 */ 425, /* VCVTPS2UDQZrrk */ }, { /* 3987 */ 426, /* VCVTPS2UDQZrrkz */ }, { /* 3988 */ 327, /* VCVTPS2UQQZ128rm */ }, { /* 3989 */ 334, /* VCVTPS2UQQZ128rmb */ }, { /* 3990 */ 335, /* VCVTPS2UQQZ128rmbk */ }, { /* 3991 */ 336, /* VCVTPS2UQQZ128rmbkz */ }, { /* 3992 */ 328, /* VCVTPS2UQQZ128rmk */ }, { /* 3993 */ 329, /* VCVTPS2UQQZ128rmkz */ }, { /* 3994 */ 377, /* VCVTPS2UQQZ128rr */ }, { /* 3995 */ 400, /* VCVTPS2UQQZ128rrk */ }, { /* 3996 */ 401, /* VCVTPS2UQQZ128rrkz */ }, { /* 3997 */ 318, /* VCVTPS2UQQZ256rm */ }, { /* 3998 */ 337, /* VCVTPS2UQQZ256rmb */ }, { /* 3999 */ 338, /* VCVTPS2UQQZ256rmbk */ }, { /* 4000 */ 339, /* VCVTPS2UQQZ256rmbkz */ }, { /* 4001 */ 319, /* VCVTPS2UQQZ256rmk */ }, { /* 4002 */ 320, /* VCVTPS2UQQZ256rmkz */ }, { /* 4003 */ 402, /* VCVTPS2UQQZ256rr */ }, { /* 4004 */ 403, /* VCVTPS2UQQZ256rrk */ }, { /* 4005 */ 404, /* VCVTPS2UQQZ256rrkz */ }, { /* 4006 */ 324, /* VCVTPS2UQQZrm */ }, { /* 4007 */ 340, /* VCVTPS2UQQZrmb */ }, { /* 4008 */ 341, /* VCVTPS2UQQZrmbk */ }, { /* 4009 */ 342, /* VCVTPS2UQQZrmbkz */ }, { /* 4010 */ 325, /* VCVTPS2UQQZrmk */ }, { /* 4011 */ 326, /* VCVTPS2UQQZrmkz */ }, { /* 4012 */ 405, /* VCVTPS2UQQZrr */ }, { /* 4013 */ 470, /* VCVTPS2UQQZrrb */ }, { /* 4014 */ 471, /* VCVTPS2UQQZrrbk */ }, { /* 4015 */ 472, /* VCVTPS2UQQZrrbkz */ }, { /* 4016 */ 406, /* VCVTPS2UQQZrrk */ }, { /* 4017 */ 407, /* VCVTPS2UQQZrrkz */ }, { /* 4018 */ 409, /* VCVTQQ2PDZ128rm */ }, { /* 4019 */ 327, /* VCVTQQ2PDZ128rmb */ }, { /* 4020 */ 328, /* VCVTQQ2PDZ128rmbk */ }, { /* 4021 */ 329, /* VCVTQQ2PDZ128rmbkz */ }, { /* 4022 */ 410, /* VCVTQQ2PDZ128rmk */ }, { /* 4023 */ 411, /* VCVTQQ2PDZ128rmkz */ }, { /* 4024 */ 330, /* VCVTQQ2PDZ128rr */ }, { /* 4025 */ 331, /* VCVTQQ2PDZ128rrk */ }, { /* 4026 */ 332, /* VCVTQQ2PDZ128rrkz */ }, { /* 4027 */ 412, /* VCVTQQ2PDZ256rm */ }, { /* 4028 */ 306, /* VCVTQQ2PDZ256rmb */ }, { /* 4029 */ 307, /* VCVTQQ2PDZ256rmbk */ }, { /* 4030 */ 308, /* VCVTQQ2PDZ256rmbkz */ }, { /* 4031 */ 413, /* VCVTQQ2PDZ256rmk */ }, { /* 4032 */ 414, /* VCVTQQ2PDZ256rmkz */ }, { /* 4033 */ 415, /* VCVTQQ2PDZ256rr */ }, { /* 4034 */ 416, /* VCVTQQ2PDZ256rrk */ }, { /* 4035 */ 417, /* VCVTQQ2PDZ256rrkz */ }, { /* 4036 */ 418, /* VCVTQQ2PDZrm */ }, { /* 4037 */ 312, /* VCVTQQ2PDZrmb */ }, { /* 4038 */ 313, /* VCVTQQ2PDZrmbk */ }, { /* 4039 */ 314, /* VCVTQQ2PDZrmbkz */ }, { /* 4040 */ 419, /* VCVTQQ2PDZrmk */ }, { /* 4041 */ 420, /* VCVTQQ2PDZrmkz */ }, { /* 4042 */ 421, /* VCVTQQ2PDZrr */ }, { /* 4043 */ 443, /* VCVTQQ2PDZrrb */ }, { /* 4044 */ 444, /* VCVTQQ2PDZrrbk */ }, { /* 4045 */ 445, /* VCVTQQ2PDZrrbkz */ }, { /* 4046 */ 425, /* VCVTQQ2PDZrrk */ }, { /* 4047 */ 426, /* VCVTQQ2PDZrrkz */ }, { /* 4048 */ 409, /* VCVTQQ2PSZ128rm */ }, { /* 4049 */ 327, /* VCVTQQ2PSZ128rmb */ }, { /* 4050 */ 328, /* VCVTQQ2PSZ128rmbk */ }, { /* 4051 */ 329, /* VCVTQQ2PSZ128rmbkz */ }, { /* 4052 */ 410, /* VCVTQQ2PSZ128rmk */ }, { /* 4053 */ 411, /* VCVTQQ2PSZ128rmkz */ }, { /* 4054 */ 330, /* VCVTQQ2PSZ128rr */ }, { /* 4055 */ 331, /* VCVTQQ2PSZ128rrk */ }, { /* 4056 */ 332, /* VCVTQQ2PSZ128rrkz */ }, { /* 4057 */ 428, /* VCVTQQ2PSZ256rm */ }, { /* 4058 */ 327, /* VCVTQQ2PSZ256rmb */ }, { /* 4059 */ 328, /* VCVTQQ2PSZ256rmbk */ }, { /* 4060 */ 329, /* VCVTQQ2PSZ256rmbkz */ }, { /* 4061 */ 429, /* VCVTQQ2PSZ256rmk */ }, { /* 4062 */ 430, /* VCVTQQ2PSZ256rmkz */ }, { /* 4063 */ 431, /* VCVTQQ2PSZ256rr */ }, { /* 4064 */ 432, /* VCVTQQ2PSZ256rrk */ }, { /* 4065 */ 433, /* VCVTQQ2PSZ256rrkz */ }, { /* 4066 */ 434, /* VCVTQQ2PSZrm */ }, { /* 4067 */ 306, /* VCVTQQ2PSZrmb */ }, { /* 4068 */ 307, /* VCVTQQ2PSZrmbk */ }, { /* 4069 */ 308, /* VCVTQQ2PSZrmbkz */ }, { /* 4070 */ 435, /* VCVTQQ2PSZrmk */ }, { /* 4071 */ 436, /* VCVTQQ2PSZrmkz */ }, { /* 4072 */ 437, /* VCVTQQ2PSZrr */ }, { /* 4073 */ 438, /* VCVTQQ2PSZrrb */ }, { /* 4074 */ 439, /* VCVTQQ2PSZrrbk */ }, { /* 4075 */ 440, /* VCVTQQ2PSZrrbkz */ }, { /* 4076 */ 441, /* VCVTQQ2PSZrrk */ }, { /* 4077 */ 442, /* VCVTQQ2PSZrrkz */ }, { /* 4078 */ 473, /* VCVTSD2SI64Zrm_Int */ }, { /* 4079 */ 474, /* VCVTSD2SI64Zrr_Int */ }, { /* 4080 */ 475, /* VCVTSD2SI64Zrrb_Int */ }, { /* 4081 */ 62, /* VCVTSD2SI64rm_Int */ }, { /* 4082 */ 86, /* VCVTSD2SI64rr_Int */ }, { /* 4083 */ 476, /* VCVTSD2SIZrm_Int */ }, { /* 4084 */ 477, /* VCVTSD2SIZrr_Int */ }, { /* 4085 */ 478, /* VCVTSD2SIZrrb_Int */ }, { /* 4086 */ 87, /* VCVTSD2SIrm_Int */ }, { /* 4087 */ 88, /* VCVTSD2SIrr_Int */ }, { /* 4088 */ 0, /* */ }, { /* 4089 */ 207, /* VCVTSD2SSZrm_Int */ }, { /* 4090 */ 208, /* VCVTSD2SSZrm_Intk */ }, { /* 4091 */ 209, /* VCVTSD2SSZrm_Intkz */ }, { /* 4092 */ 0, /* */ }, { /* 4093 */ 249, /* VCVTSD2SSZrr_Int */ }, { /* 4094 */ 250, /* VCVTSD2SSZrr_Intk */ }, { /* 4095 */ 251, /* VCVTSD2SSZrr_Intkz */ }, { /* 4096 */ 252, /* VCVTSD2SSZrrb_Int */ }, { /* 4097 */ 253, /* VCVTSD2SSZrrb_Intk */ }, { /* 4098 */ 254, /* VCVTSD2SSZrrb_Intkz */ }, { /* 4099 */ 235, /* VCVTSD2SSrm */ }, { /* 4100 */ 0, /* */ }, { /* 4101 */ 236, /* VCVTSD2SSrr */ }, { /* 4102 */ 0, /* */ }, { /* 4103 */ 473, /* VCVTSD2USI64Zrm_Int */ }, { /* 4104 */ 474, /* VCVTSD2USI64Zrr_Int */ }, { /* 4105 */ 475, /* VCVTSD2USI64Zrrb_Int */ }, { /* 4106 */ 476, /* VCVTSD2USIZrm_Int */ }, { /* 4107 */ 477, /* VCVTSD2USIZrr_Int */ }, { /* 4108 */ 478, /* VCVTSD2USIZrrb_Int */ }, { /* 4109 */ 237, /* VCVTSI2SDZrm */ }, { /* 4110 */ 0, /* */ }, { /* 4111 */ 479, /* VCVTSI2SDZrr */ }, { /* 4112 */ 0, /* */ }, { /* 4113 */ 480, /* VCVTSI2SDZrrb_Int */ }, { /* 4114 */ 235, /* VCVTSI2SDrm */ }, { /* 4115 */ 0, /* */ }, { /* 4116 */ 481, /* VCVTSI2SDrr */ }, { /* 4117 */ 0, /* */ }, { /* 4118 */ 237, /* VCVTSI2SSZrm */ }, { /* 4119 */ 0, /* */ }, { /* 4120 */ 479, /* VCVTSI2SSZrr */ }, { /* 4121 */ 0, /* */ }, { /* 4122 */ 480, /* VCVTSI2SSZrrb_Int */ }, { /* 4123 */ 235, /* VCVTSI2SSrm */ }, { /* 4124 */ 0, /* */ }, { /* 4125 */ 481, /* VCVTSI2SSrr */ }, { /* 4126 */ 0, /* */ }, { /* 4127 */ 207, /* VCVTSI642SDZrm */ }, { /* 4128 */ 0, /* */ }, { /* 4129 */ 482, /* VCVTSI642SDZrr */ }, { /* 4130 */ 0, /* */ }, { /* 4131 */ 483, /* VCVTSI642SDZrrb_Int */ }, { /* 4132 */ 235, /* VCVTSI642SDrm */ }, { /* 4133 */ 0, /* */ }, { /* 4134 */ 484, /* VCVTSI642SDrr */ }, { /* 4135 */ 0, /* */ }, { /* 4136 */ 207, /* VCVTSI642SSZrm */ }, { /* 4137 */ 0, /* */ }, { /* 4138 */ 482, /* VCVTSI642SSZrr */ }, { /* 4139 */ 0, /* */ }, { /* 4140 */ 483, /* VCVTSI642SSZrrb_Int */ }, { /* 4141 */ 235, /* VCVTSI642SSrm */ }, { /* 4142 */ 0, /* */ }, { /* 4143 */ 484, /* VCVTSI642SSrr */ }, { /* 4144 */ 0, /* */ }, { /* 4145 */ 0, /* */ }, { /* 4146 */ 237, /* VCVTSS2SDZrm_Int */ }, { /* 4147 */ 238, /* VCVTSS2SDZrm_Intk */ }, { /* 4148 */ 239, /* VCVTSS2SDZrm_Intkz */ }, { /* 4149 */ 0, /* */ }, { /* 4150 */ 255, /* VCVTSS2SDZrr_Int */ }, { /* 4151 */ 256, /* VCVTSS2SDZrr_Intk */ }, { /* 4152 */ 257, /* VCVTSS2SDZrr_Intkz */ }, { /* 4153 */ 255, /* VCVTSS2SDZrrb_Int */ }, { /* 4154 */ 256, /* VCVTSS2SDZrrb_Intk */ }, { /* 4155 */ 257, /* VCVTSS2SDZrrb_Intkz */ }, { /* 4156 */ 235, /* VCVTSS2SDrm */ }, { /* 4157 */ 0, /* */ }, { /* 4158 */ 236, /* VCVTSS2SDrr */ }, { /* 4159 */ 0, /* */ }, { /* 4160 */ 485, /* VCVTSS2SI64Zrm_Int */ }, { /* 4161 */ 486, /* VCVTSS2SI64Zrr_Int */ }, { /* 4162 */ 487, /* VCVTSS2SI64Zrrb_Int */ }, { /* 4163 */ 62, /* VCVTSS2SI64rm_Int */ }, { /* 4164 */ 86, /* VCVTSS2SI64rr_Int */ }, { /* 4165 */ 488, /* VCVTSS2SIZrm_Int */ }, { /* 4166 */ 489, /* VCVTSS2SIZrr_Int */ }, { /* 4167 */ 490, /* VCVTSS2SIZrrb_Int */ }, { /* 4168 */ 87, /* VCVTSS2SIrm_Int */ }, { /* 4169 */ 88, /* VCVTSS2SIrr_Int */ }, { /* 4170 */ 485, /* VCVTSS2USI64Zrm_Int */ }, { /* 4171 */ 486, /* VCVTSS2USI64Zrr_Int */ }, { /* 4172 */ 487, /* VCVTSS2USI64Zrrb_Int */ }, { /* 4173 */ 488, /* VCVTSS2USIZrm_Int */ }, { /* 4174 */ 489, /* VCVTSS2USIZrr_Int */ }, { /* 4175 */ 490, /* VCVTSS2USIZrrb_Int */ }, { /* 4176 */ 30, /* VCVTTPD2DQYrm */ }, { /* 4177 */ 427, /* VCVTTPD2DQYrr */ }, { /* 4178 */ 409, /* VCVTTPD2DQZ128rm */ }, { /* 4179 */ 327, /* VCVTTPD2DQZ128rmb */ }, { /* 4180 */ 328, /* VCVTTPD2DQZ128rmbk */ }, { /* 4181 */ 329, /* VCVTTPD2DQZ128rmbkz */ }, { /* 4182 */ 410, /* VCVTTPD2DQZ128rmk */ }, { /* 4183 */ 411, /* VCVTTPD2DQZ128rmkz */ }, { /* 4184 */ 330, /* VCVTTPD2DQZ128rr */ }, { /* 4185 */ 331, /* VCVTTPD2DQZ128rrk */ }, { /* 4186 */ 332, /* VCVTTPD2DQZ128rrkz */ }, { /* 4187 */ 428, /* VCVTTPD2DQZ256rm */ }, { /* 4188 */ 327, /* VCVTTPD2DQZ256rmb */ }, { /* 4189 */ 328, /* VCVTTPD2DQZ256rmbk */ }, { /* 4190 */ 329, /* VCVTTPD2DQZ256rmbkz */ }, { /* 4191 */ 429, /* VCVTTPD2DQZ256rmk */ }, { /* 4192 */ 430, /* VCVTTPD2DQZ256rmkz */ }, { /* 4193 */ 431, /* VCVTTPD2DQZ256rr */ }, { /* 4194 */ 432, /* VCVTTPD2DQZ256rrk */ }, { /* 4195 */ 433, /* VCVTTPD2DQZ256rrkz */ }, { /* 4196 */ 434, /* VCVTTPD2DQZrm */ }, { /* 4197 */ 306, /* VCVTTPD2DQZrmb */ }, { /* 4198 */ 307, /* VCVTTPD2DQZrmbk */ }, { /* 4199 */ 308, /* VCVTTPD2DQZrmbkz */ }, { /* 4200 */ 435, /* VCVTTPD2DQZrmk */ }, { /* 4201 */ 436, /* VCVTTPD2DQZrmkz */ }, { /* 4202 */ 437, /* VCVTTPD2DQZrr */ }, { /* 4203 */ 491, /* VCVTTPD2DQZrrb */ }, { /* 4204 */ 492, /* VCVTTPD2DQZrrbk */ }, { /* 4205 */ 493, /* VCVTTPD2DQZrrbkz */ }, { /* 4206 */ 441, /* VCVTTPD2DQZrrk */ }, { /* 4207 */ 442, /* VCVTTPD2DQZrrkz */ }, { /* 4208 */ 30, /* VCVTTPD2DQrm */ }, { /* 4209 */ 31, /* VCVTTPD2DQrr */ }, { /* 4210 */ 409, /* VCVTTPD2QQZ128rm */ }, { /* 4211 */ 327, /* VCVTTPD2QQZ128rmb */ }, { /* 4212 */ 328, /* VCVTTPD2QQZ128rmbk */ }, { /* 4213 */ 329, /* VCVTTPD2QQZ128rmbkz */ }, { /* 4214 */ 410, /* VCVTTPD2QQZ128rmk */ }, { /* 4215 */ 411, /* VCVTTPD2QQZ128rmkz */ }, { /* 4216 */ 330, /* VCVTTPD2QQZ128rr */ }, { /* 4217 */ 331, /* VCVTTPD2QQZ128rrk */ }, { /* 4218 */ 332, /* VCVTTPD2QQZ128rrkz */ }, { /* 4219 */ 412, /* VCVTTPD2QQZ256rm */ }, { /* 4220 */ 306, /* VCVTTPD2QQZ256rmb */ }, { /* 4221 */ 307, /* VCVTTPD2QQZ256rmbk */ }, { /* 4222 */ 308, /* VCVTTPD2QQZ256rmbkz */ }, { /* 4223 */ 413, /* VCVTTPD2QQZ256rmk */ }, { /* 4224 */ 414, /* VCVTTPD2QQZ256rmkz */ }, { /* 4225 */ 415, /* VCVTTPD2QQZ256rr */ }, { /* 4226 */ 416, /* VCVTTPD2QQZ256rrk */ }, { /* 4227 */ 417, /* VCVTTPD2QQZ256rrkz */ }, { /* 4228 */ 418, /* VCVTTPD2QQZrm */ }, { /* 4229 */ 312, /* VCVTTPD2QQZrmb */ }, { /* 4230 */ 313, /* VCVTTPD2QQZrmbk */ }, { /* 4231 */ 314, /* VCVTTPD2QQZrmbkz */ }, { /* 4232 */ 419, /* VCVTTPD2QQZrmk */ }, { /* 4233 */ 420, /* VCVTTPD2QQZrmkz */ }, { /* 4234 */ 421, /* VCVTTPD2QQZrr */ }, { /* 4235 */ 494, /* VCVTTPD2QQZrrb */ }, { /* 4236 */ 495, /* VCVTTPD2QQZrrbk */ }, { /* 4237 */ 496, /* VCVTTPD2QQZrrbkz */ }, { /* 4238 */ 425, /* VCVTTPD2QQZrrk */ }, { /* 4239 */ 426, /* VCVTTPD2QQZrrkz */ }, { /* 4240 */ 409, /* VCVTTPD2UDQZ128rm */ }, { /* 4241 */ 327, /* VCVTTPD2UDQZ128rmb */ }, { /* 4242 */ 328, /* VCVTTPD2UDQZ128rmbk */ }, { /* 4243 */ 329, /* VCVTTPD2UDQZ128rmbkz */ }, { /* 4244 */ 410, /* VCVTTPD2UDQZ128rmk */ }, { /* 4245 */ 411, /* VCVTTPD2UDQZ128rmkz */ }, { /* 4246 */ 330, /* VCVTTPD2UDQZ128rr */ }, { /* 4247 */ 331, /* VCVTTPD2UDQZ128rrk */ }, { /* 4248 */ 332, /* VCVTTPD2UDQZ128rrkz */ }, { /* 4249 */ 428, /* VCVTTPD2UDQZ256rm */ }, { /* 4250 */ 327, /* VCVTTPD2UDQZ256rmb */ }, { /* 4251 */ 328, /* VCVTTPD2UDQZ256rmbk */ }, { /* 4252 */ 329, /* VCVTTPD2UDQZ256rmbkz */ }, { /* 4253 */ 429, /* VCVTTPD2UDQZ256rmk */ }, { /* 4254 */ 430, /* VCVTTPD2UDQZ256rmkz */ }, { /* 4255 */ 431, /* VCVTTPD2UDQZ256rr */ }, { /* 4256 */ 432, /* VCVTTPD2UDQZ256rrk */ }, { /* 4257 */ 433, /* VCVTTPD2UDQZ256rrkz */ }, { /* 4258 */ 434, /* VCVTTPD2UDQZrm */ }, { /* 4259 */ 306, /* VCVTTPD2UDQZrmb */ }, { /* 4260 */ 307, /* VCVTTPD2UDQZrmbk */ }, { /* 4261 */ 308, /* VCVTTPD2UDQZrmbkz */ }, { /* 4262 */ 435, /* VCVTTPD2UDQZrmk */ }, { /* 4263 */ 436, /* VCVTTPD2UDQZrmkz */ }, { /* 4264 */ 437, /* VCVTTPD2UDQZrr */ }, { /* 4265 */ 491, /* VCVTTPD2UDQZrrb */ }, { /* 4266 */ 492, /* VCVTTPD2UDQZrrbk */ }, { /* 4267 */ 493, /* VCVTTPD2UDQZrrbkz */ }, { /* 4268 */ 441, /* VCVTTPD2UDQZrrk */ }, { /* 4269 */ 442, /* VCVTTPD2UDQZrrkz */ }, { /* 4270 */ 409, /* VCVTTPD2UQQZ128rm */ }, { /* 4271 */ 327, /* VCVTTPD2UQQZ128rmb */ }, { /* 4272 */ 328, /* VCVTTPD2UQQZ128rmbk */ }, { /* 4273 */ 329, /* VCVTTPD2UQQZ128rmbkz */ }, { /* 4274 */ 410, /* VCVTTPD2UQQZ128rmk */ }, { /* 4275 */ 411, /* VCVTTPD2UQQZ128rmkz */ }, { /* 4276 */ 330, /* VCVTTPD2UQQZ128rr */ }, { /* 4277 */ 331, /* VCVTTPD2UQQZ128rrk */ }, { /* 4278 */ 332, /* VCVTTPD2UQQZ128rrkz */ }, { /* 4279 */ 412, /* VCVTTPD2UQQZ256rm */ }, { /* 4280 */ 306, /* VCVTTPD2UQQZ256rmb */ }, { /* 4281 */ 307, /* VCVTTPD2UQQZ256rmbk */ }, { /* 4282 */ 308, /* VCVTTPD2UQQZ256rmbkz */ }, { /* 4283 */ 413, /* VCVTTPD2UQQZ256rmk */ }, { /* 4284 */ 414, /* VCVTTPD2UQQZ256rmkz */ }, { /* 4285 */ 415, /* VCVTTPD2UQQZ256rr */ }, { /* 4286 */ 416, /* VCVTTPD2UQQZ256rrk */ }, { /* 4287 */ 417, /* VCVTTPD2UQQZ256rrkz */ }, { /* 4288 */ 418, /* VCVTTPD2UQQZrm */ }, { /* 4289 */ 312, /* VCVTTPD2UQQZrmb */ }, { /* 4290 */ 313, /* VCVTTPD2UQQZrmbk */ }, { /* 4291 */ 314, /* VCVTTPD2UQQZrmbkz */ }, { /* 4292 */ 419, /* VCVTTPD2UQQZrmk */ }, { /* 4293 */ 420, /* VCVTTPD2UQQZrmkz */ }, { /* 4294 */ 421, /* VCVTTPD2UQQZrr */ }, { /* 4295 */ 494, /* VCVTTPD2UQQZrrb */ }, { /* 4296 */ 495, /* VCVTTPD2UQQZrrbk */ }, { /* 4297 */ 496, /* VCVTTPD2UQQZrrbkz */ }, { /* 4298 */ 425, /* VCVTTPD2UQQZrrk */ }, { /* 4299 */ 426, /* VCVTTPD2UQQZrrkz */ }, { /* 4300 */ 305, /* VCVTTPS2DQYrm */ }, { /* 4301 */ 408, /* VCVTTPS2DQYrr */ }, { /* 4302 */ 409, /* VCVTTPS2DQZ128rm */ }, { /* 4303 */ 334, /* VCVTTPS2DQZ128rmb */ }, { /* 4304 */ 335, /* VCVTTPS2DQZ128rmbk */ }, { /* 4305 */ 336, /* VCVTTPS2DQZ128rmbkz */ }, { /* 4306 */ 410, /* VCVTTPS2DQZ128rmk */ }, { /* 4307 */ 411, /* VCVTTPS2DQZ128rmkz */ }, { /* 4308 */ 330, /* VCVTTPS2DQZ128rr */ }, { /* 4309 */ 331, /* VCVTTPS2DQZ128rrk */ }, { /* 4310 */ 332, /* VCVTTPS2DQZ128rrkz */ }, { /* 4311 */ 412, /* VCVTTPS2DQZ256rm */ }, { /* 4312 */ 337, /* VCVTTPS2DQZ256rmb */ }, { /* 4313 */ 338, /* VCVTTPS2DQZ256rmbk */ }, { /* 4314 */ 339, /* VCVTTPS2DQZ256rmbkz */ }, { /* 4315 */ 413, /* VCVTTPS2DQZ256rmk */ }, { /* 4316 */ 414, /* VCVTTPS2DQZ256rmkz */ }, { /* 4317 */ 415, /* VCVTTPS2DQZ256rr */ }, { /* 4318 */ 416, /* VCVTTPS2DQZ256rrk */ }, { /* 4319 */ 417, /* VCVTTPS2DQZ256rrkz */ }, { /* 4320 */ 418, /* VCVTTPS2DQZrm */ }, { /* 4321 */ 340, /* VCVTTPS2DQZrmb */ }, { /* 4322 */ 341, /* VCVTTPS2DQZrmbk */ }, { /* 4323 */ 342, /* VCVTTPS2DQZrmbkz */ }, { /* 4324 */ 419, /* VCVTTPS2DQZrmk */ }, { /* 4325 */ 420, /* VCVTTPS2DQZrmkz */ }, { /* 4326 */ 421, /* VCVTTPS2DQZrr */ }, { /* 4327 */ 497, /* VCVTTPS2DQZrrb */ }, { /* 4328 */ 498, /* VCVTTPS2DQZrrbk */ }, { /* 4329 */ 499, /* VCVTTPS2DQZrrbkz */ }, { /* 4330 */ 425, /* VCVTTPS2DQZrrk */ }, { /* 4331 */ 426, /* VCVTTPS2DQZrrkz */ }, { /* 4332 */ 30, /* VCVTTPS2DQrm */ }, { /* 4333 */ 31, /* VCVTTPS2DQrr */ }, { /* 4334 */ 327, /* VCVTTPS2QQZ128rm */ }, { /* 4335 */ 334, /* VCVTTPS2QQZ128rmb */ }, { /* 4336 */ 335, /* VCVTTPS2QQZ128rmbk */ }, { /* 4337 */ 336, /* VCVTTPS2QQZ128rmbkz */ }, { /* 4338 */ 328, /* VCVTTPS2QQZ128rmk */ }, { /* 4339 */ 329, /* VCVTTPS2QQZ128rmkz */ }, { /* 4340 */ 377, /* VCVTTPS2QQZ128rr */ }, { /* 4341 */ 400, /* VCVTTPS2QQZ128rrk */ }, { /* 4342 */ 401, /* VCVTTPS2QQZ128rrkz */ }, { /* 4343 */ 318, /* VCVTTPS2QQZ256rm */ }, { /* 4344 */ 337, /* VCVTTPS2QQZ256rmb */ }, { /* 4345 */ 338, /* VCVTTPS2QQZ256rmbk */ }, { /* 4346 */ 339, /* VCVTTPS2QQZ256rmbkz */ }, { /* 4347 */ 319, /* VCVTTPS2QQZ256rmk */ }, { /* 4348 */ 320, /* VCVTTPS2QQZ256rmkz */ }, { /* 4349 */ 402, /* VCVTTPS2QQZ256rr */ }, { /* 4350 */ 403, /* VCVTTPS2QQZ256rrk */ }, { /* 4351 */ 404, /* VCVTTPS2QQZ256rrkz */ }, { /* 4352 */ 324, /* VCVTTPS2QQZrm */ }, { /* 4353 */ 340, /* VCVTTPS2QQZrmb */ }, { /* 4354 */ 341, /* VCVTTPS2QQZrmbk */ }, { /* 4355 */ 342, /* VCVTTPS2QQZrmbkz */ }, { /* 4356 */ 325, /* VCVTTPS2QQZrmk */ }, { /* 4357 */ 326, /* VCVTTPS2QQZrmkz */ }, { /* 4358 */ 405, /* VCVTTPS2QQZrr */ }, { /* 4359 */ 446, /* VCVTTPS2QQZrrb */ }, { /* 4360 */ 447, /* VCVTTPS2QQZrrbk */ }, { /* 4361 */ 448, /* VCVTTPS2QQZrrbkz */ }, { /* 4362 */ 406, /* VCVTTPS2QQZrrk */ }, { /* 4363 */ 407, /* VCVTTPS2QQZrrkz */ }, { /* 4364 */ 409, /* VCVTTPS2UDQZ128rm */ }, { /* 4365 */ 334, /* VCVTTPS2UDQZ128rmb */ }, { /* 4366 */ 335, /* VCVTTPS2UDQZ128rmbk */ }, { /* 4367 */ 336, /* VCVTTPS2UDQZ128rmbkz */ }, { /* 4368 */ 410, /* VCVTTPS2UDQZ128rmk */ }, { /* 4369 */ 411, /* VCVTTPS2UDQZ128rmkz */ }, { /* 4370 */ 330, /* VCVTTPS2UDQZ128rr */ }, { /* 4371 */ 331, /* VCVTTPS2UDQZ128rrk */ }, { /* 4372 */ 332, /* VCVTTPS2UDQZ128rrkz */ }, { /* 4373 */ 412, /* VCVTTPS2UDQZ256rm */ }, { /* 4374 */ 337, /* VCVTTPS2UDQZ256rmb */ }, { /* 4375 */ 338, /* VCVTTPS2UDQZ256rmbk */ }, { /* 4376 */ 339, /* VCVTTPS2UDQZ256rmbkz */ }, { /* 4377 */ 413, /* VCVTTPS2UDQZ256rmk */ }, { /* 4378 */ 414, /* VCVTTPS2UDQZ256rmkz */ }, { /* 4379 */ 415, /* VCVTTPS2UDQZ256rr */ }, { /* 4380 */ 416, /* VCVTTPS2UDQZ256rrk */ }, { /* 4381 */ 417, /* VCVTTPS2UDQZ256rrkz */ }, { /* 4382 */ 418, /* VCVTTPS2UDQZrm */ }, { /* 4383 */ 340, /* VCVTTPS2UDQZrmb */ }, { /* 4384 */ 341, /* VCVTTPS2UDQZrmbk */ }, { /* 4385 */ 342, /* VCVTTPS2UDQZrmbkz */ }, { /* 4386 */ 419, /* VCVTTPS2UDQZrmk */ }, { /* 4387 */ 420, /* VCVTTPS2UDQZrmkz */ }, { /* 4388 */ 421, /* VCVTTPS2UDQZrr */ }, { /* 4389 */ 497, /* VCVTTPS2UDQZrrb */ }, { /* 4390 */ 498, /* VCVTTPS2UDQZrrbk */ }, { /* 4391 */ 499, /* VCVTTPS2UDQZrrbkz */ }, { /* 4392 */ 425, /* VCVTTPS2UDQZrrk */ }, { /* 4393 */ 426, /* VCVTTPS2UDQZrrkz */ }, { /* 4394 */ 327, /* VCVTTPS2UQQZ128rm */ }, { /* 4395 */ 334, /* VCVTTPS2UQQZ128rmb */ }, { /* 4396 */ 335, /* VCVTTPS2UQQZ128rmbk */ }, { /* 4397 */ 336, /* VCVTTPS2UQQZ128rmbkz */ }, { /* 4398 */ 328, /* VCVTTPS2UQQZ128rmk */ }, { /* 4399 */ 329, /* VCVTTPS2UQQZ128rmkz */ }, { /* 4400 */ 377, /* VCVTTPS2UQQZ128rr */ }, { /* 4401 */ 400, /* VCVTTPS2UQQZ128rrk */ }, { /* 4402 */ 401, /* VCVTTPS2UQQZ128rrkz */ }, { /* 4403 */ 318, /* VCVTTPS2UQQZ256rm */ }, { /* 4404 */ 337, /* VCVTTPS2UQQZ256rmb */ }, { /* 4405 */ 338, /* VCVTTPS2UQQZ256rmbk */ }, { /* 4406 */ 339, /* VCVTTPS2UQQZ256rmbkz */ }, { /* 4407 */ 319, /* VCVTTPS2UQQZ256rmk */ }, { /* 4408 */ 320, /* VCVTTPS2UQQZ256rmkz */ }, { /* 4409 */ 402, /* VCVTTPS2UQQZ256rr */ }, { /* 4410 */ 403, /* VCVTTPS2UQQZ256rrk */ }, { /* 4411 */ 404, /* VCVTTPS2UQQZ256rrkz */ }, { /* 4412 */ 324, /* VCVTTPS2UQQZrm */ }, { /* 4413 */ 340, /* VCVTTPS2UQQZrmb */ }, { /* 4414 */ 341, /* VCVTTPS2UQQZrmbk */ }, { /* 4415 */ 342, /* VCVTTPS2UQQZrmbkz */ }, { /* 4416 */ 325, /* VCVTTPS2UQQZrmk */ }, { /* 4417 */ 326, /* VCVTTPS2UQQZrmkz */ }, { /* 4418 */ 405, /* VCVTTPS2UQQZrr */ }, { /* 4419 */ 446, /* VCVTTPS2UQQZrrb */ }, { /* 4420 */ 447, /* VCVTTPS2UQQZrrbk */ }, { /* 4421 */ 448, /* VCVTTPS2UQQZrrbkz */ }, { /* 4422 */ 406, /* VCVTTPS2UQQZrrk */ }, { /* 4423 */ 407, /* VCVTTPS2UQQZrrkz */ }, { /* 4424 */ 0, /* */ }, { /* 4425 */ 473, /* VCVTTSD2SI64Zrm_Int */ }, { /* 4426 */ 0, /* */ }, { /* 4427 */ 474, /* VCVTTSD2SI64Zrr_Int */ }, { /* 4428 */ 474, /* VCVTTSD2SI64Zrrb_Int */ }, { /* 4429 */ 62, /* VCVTTSD2SI64rm */ }, { /* 4430 */ 0, /* */ }, { /* 4431 */ 86, /* VCVTTSD2SI64rr */ }, { /* 4432 */ 0, /* */ }, { /* 4433 */ 0, /* */ }, { /* 4434 */ 476, /* VCVTTSD2SIZrm_Int */ }, { /* 4435 */ 0, /* */ }, { /* 4436 */ 477, /* VCVTTSD2SIZrr_Int */ }, { /* 4437 */ 477, /* VCVTTSD2SIZrrb_Int */ }, { /* 4438 */ 87, /* VCVTTSD2SIrm */ }, { /* 4439 */ 0, /* */ }, { /* 4440 */ 88, /* VCVTTSD2SIrr */ }, { /* 4441 */ 0, /* */ }, { /* 4442 */ 0, /* */ }, { /* 4443 */ 473, /* VCVTTSD2USI64Zrm_Int */ }, { /* 4444 */ 0, /* */ }, { /* 4445 */ 474, /* VCVTTSD2USI64Zrr_Int */ }, { /* 4446 */ 474, /* VCVTTSD2USI64Zrrb_Int */ }, { /* 4447 */ 0, /* */ }, { /* 4448 */ 476, /* VCVTTSD2USIZrm_Int */ }, { /* 4449 */ 0, /* */ }, { /* 4450 */ 477, /* VCVTTSD2USIZrr_Int */ }, { /* 4451 */ 477, /* VCVTTSD2USIZrrb_Int */ }, { /* 4452 */ 0, /* */ }, { /* 4453 */ 485, /* VCVTTSS2SI64Zrm_Int */ }, { /* 4454 */ 0, /* */ }, { /* 4455 */ 486, /* VCVTTSS2SI64Zrr_Int */ }, { /* 4456 */ 486, /* VCVTTSS2SI64Zrrb_Int */ }, { /* 4457 */ 62, /* VCVTTSS2SI64rm */ }, { /* 4458 */ 0, /* */ }, { /* 4459 */ 86, /* VCVTTSS2SI64rr */ }, { /* 4460 */ 0, /* */ }, { /* 4461 */ 0, /* */ }, { /* 4462 */ 488, /* VCVTTSS2SIZrm_Int */ }, { /* 4463 */ 0, /* */ }, { /* 4464 */ 489, /* VCVTTSS2SIZrr_Int */ }, { /* 4465 */ 489, /* VCVTTSS2SIZrrb_Int */ }, { /* 4466 */ 87, /* VCVTTSS2SIrm */ }, { /* 4467 */ 0, /* */ }, { /* 4468 */ 88, /* VCVTTSS2SIrr */ }, { /* 4469 */ 0, /* */ }, { /* 4470 */ 0, /* */ }, { /* 4471 */ 485, /* VCVTTSS2USI64Zrm_Int */ }, { /* 4472 */ 0, /* */ }, { /* 4473 */ 486, /* VCVTTSS2USI64Zrr_Int */ }, { /* 4474 */ 486, /* VCVTTSS2USI64Zrrb_Int */ }, { /* 4475 */ 0, /* */ }, { /* 4476 */ 488, /* VCVTTSS2USIZrm_Int */ }, { /* 4477 */ 0, /* */ }, { /* 4478 */ 489, /* VCVTTSS2USIZrr_Int */ }, { /* 4479 */ 489, /* VCVTTSS2USIZrrb_Int */ }, { /* 4480 */ 327, /* VCVTUDQ2PDZ128rm */ }, { /* 4481 */ 334, /* VCVTUDQ2PDZ128rmb */ }, { /* 4482 */ 335, /* VCVTUDQ2PDZ128rmbk */ }, { /* 4483 */ 336, /* VCVTUDQ2PDZ128rmbkz */ }, { /* 4484 */ 328, /* VCVTUDQ2PDZ128rmk */ }, { /* 4485 */ 329, /* VCVTUDQ2PDZ128rmkz */ }, { /* 4486 */ 377, /* VCVTUDQ2PDZ128rr */ }, { /* 4487 */ 400, /* VCVTUDQ2PDZ128rrk */ }, { /* 4488 */ 401, /* VCVTUDQ2PDZ128rrkz */ }, { /* 4489 */ 318, /* VCVTUDQ2PDZ256rm */ }, { /* 4490 */ 337, /* VCVTUDQ2PDZ256rmb */ }, { /* 4491 */ 338, /* VCVTUDQ2PDZ256rmbk */ }, { /* 4492 */ 339, /* VCVTUDQ2PDZ256rmbkz */ }, { /* 4493 */ 319, /* VCVTUDQ2PDZ256rmk */ }, { /* 4494 */ 320, /* VCVTUDQ2PDZ256rmkz */ }, { /* 4495 */ 402, /* VCVTUDQ2PDZ256rr */ }, { /* 4496 */ 403, /* VCVTUDQ2PDZ256rrk */ }, { /* 4497 */ 404, /* VCVTUDQ2PDZ256rrkz */ }, { /* 4498 */ 324, /* VCVTUDQ2PDZrm */ }, { /* 4499 */ 340, /* VCVTUDQ2PDZrmb */ }, { /* 4500 */ 341, /* VCVTUDQ2PDZrmbk */ }, { /* 4501 */ 342, /* VCVTUDQ2PDZrmbkz */ }, { /* 4502 */ 325, /* VCVTUDQ2PDZrmk */ }, { /* 4503 */ 326, /* VCVTUDQ2PDZrmkz */ }, { /* 4504 */ 405, /* VCVTUDQ2PDZrr */ }, { /* 4505 */ 406, /* VCVTUDQ2PDZrrk */ }, { /* 4506 */ 407, /* VCVTUDQ2PDZrrkz */ }, { /* 4507 */ 409, /* VCVTUDQ2PSZ128rm */ }, { /* 4508 */ 334, /* VCVTUDQ2PSZ128rmb */ }, { /* 4509 */ 335, /* VCVTUDQ2PSZ128rmbk */ }, { /* 4510 */ 336, /* VCVTUDQ2PSZ128rmbkz */ }, { /* 4511 */ 410, /* VCVTUDQ2PSZ128rmk */ }, { /* 4512 */ 411, /* VCVTUDQ2PSZ128rmkz */ }, { /* 4513 */ 330, /* VCVTUDQ2PSZ128rr */ }, { /* 4514 */ 331, /* VCVTUDQ2PSZ128rrk */ }, { /* 4515 */ 332, /* VCVTUDQ2PSZ128rrkz */ }, { /* 4516 */ 412, /* VCVTUDQ2PSZ256rm */ }, { /* 4517 */ 337, /* VCVTUDQ2PSZ256rmb */ }, { /* 4518 */ 338, /* VCVTUDQ2PSZ256rmbk */ }, { /* 4519 */ 339, /* VCVTUDQ2PSZ256rmbkz */ }, { /* 4520 */ 413, /* VCVTUDQ2PSZ256rmk */ }, { /* 4521 */ 414, /* VCVTUDQ2PSZ256rmkz */ }, { /* 4522 */ 415, /* VCVTUDQ2PSZ256rr */ }, { /* 4523 */ 416, /* VCVTUDQ2PSZ256rrk */ }, { /* 4524 */ 417, /* VCVTUDQ2PSZ256rrkz */ }, { /* 4525 */ 418, /* VCVTUDQ2PSZrm */ }, { /* 4526 */ 340, /* VCVTUDQ2PSZrmb */ }, { /* 4527 */ 341, /* VCVTUDQ2PSZrmbk */ }, { /* 4528 */ 342, /* VCVTUDQ2PSZrmbkz */ }, { /* 4529 */ 419, /* VCVTUDQ2PSZrmk */ }, { /* 4530 */ 420, /* VCVTUDQ2PSZrmkz */ }, { /* 4531 */ 421, /* VCVTUDQ2PSZrr */ }, { /* 4532 */ 422, /* VCVTUDQ2PSZrrb */ }, { /* 4533 */ 423, /* VCVTUDQ2PSZrrbk */ }, { /* 4534 */ 424, /* VCVTUDQ2PSZrrbkz */ }, { /* 4535 */ 425, /* VCVTUDQ2PSZrrk */ }, { /* 4536 */ 426, /* VCVTUDQ2PSZrrkz */ }, { /* 4537 */ 409, /* VCVTUQQ2PDZ128rm */ }, { /* 4538 */ 327, /* VCVTUQQ2PDZ128rmb */ }, { /* 4539 */ 328, /* VCVTUQQ2PDZ128rmbk */ }, { /* 4540 */ 329, /* VCVTUQQ2PDZ128rmbkz */ }, { /* 4541 */ 410, /* VCVTUQQ2PDZ128rmk */ }, { /* 4542 */ 411, /* VCVTUQQ2PDZ128rmkz */ }, { /* 4543 */ 330, /* VCVTUQQ2PDZ128rr */ }, { /* 4544 */ 331, /* VCVTUQQ2PDZ128rrk */ }, { /* 4545 */ 332, /* VCVTUQQ2PDZ128rrkz */ }, { /* 4546 */ 412, /* VCVTUQQ2PDZ256rm */ }, { /* 4547 */ 306, /* VCVTUQQ2PDZ256rmb */ }, { /* 4548 */ 307, /* VCVTUQQ2PDZ256rmbk */ }, { /* 4549 */ 308, /* VCVTUQQ2PDZ256rmbkz */ }, { /* 4550 */ 413, /* VCVTUQQ2PDZ256rmk */ }, { /* 4551 */ 414, /* VCVTUQQ2PDZ256rmkz */ }, { /* 4552 */ 415, /* VCVTUQQ2PDZ256rr */ }, { /* 4553 */ 416, /* VCVTUQQ2PDZ256rrk */ }, { /* 4554 */ 417, /* VCVTUQQ2PDZ256rrkz */ }, { /* 4555 */ 418, /* VCVTUQQ2PDZrm */ }, { /* 4556 */ 312, /* VCVTUQQ2PDZrmb */ }, { /* 4557 */ 313, /* VCVTUQQ2PDZrmbk */ }, { /* 4558 */ 314, /* VCVTUQQ2PDZrmbkz */ }, { /* 4559 */ 419, /* VCVTUQQ2PDZrmk */ }, { /* 4560 */ 420, /* VCVTUQQ2PDZrmkz */ }, { /* 4561 */ 421, /* VCVTUQQ2PDZrr */ }, { /* 4562 */ 443, /* VCVTUQQ2PDZrrb */ }, { /* 4563 */ 444, /* VCVTUQQ2PDZrrbk */ }, { /* 4564 */ 445, /* VCVTUQQ2PDZrrbkz */ }, { /* 4565 */ 425, /* VCVTUQQ2PDZrrk */ }, { /* 4566 */ 426, /* VCVTUQQ2PDZrrkz */ }, { /* 4567 */ 409, /* VCVTUQQ2PSZ128rm */ }, { /* 4568 */ 327, /* VCVTUQQ2PSZ128rmb */ }, { /* 4569 */ 328, /* VCVTUQQ2PSZ128rmbk */ }, { /* 4570 */ 329, /* VCVTUQQ2PSZ128rmbkz */ }, { /* 4571 */ 410, /* VCVTUQQ2PSZ128rmk */ }, { /* 4572 */ 411, /* VCVTUQQ2PSZ128rmkz */ }, { /* 4573 */ 330, /* VCVTUQQ2PSZ128rr */ }, { /* 4574 */ 331, /* VCVTUQQ2PSZ128rrk */ }, { /* 4575 */ 332, /* VCVTUQQ2PSZ128rrkz */ }, { /* 4576 */ 428, /* VCVTUQQ2PSZ256rm */ }, { /* 4577 */ 327, /* VCVTUQQ2PSZ256rmb */ }, { /* 4578 */ 328, /* VCVTUQQ2PSZ256rmbk */ }, { /* 4579 */ 329, /* VCVTUQQ2PSZ256rmbkz */ }, { /* 4580 */ 429, /* VCVTUQQ2PSZ256rmk */ }, { /* 4581 */ 430, /* VCVTUQQ2PSZ256rmkz */ }, { /* 4582 */ 431, /* VCVTUQQ2PSZ256rr */ }, { /* 4583 */ 432, /* VCVTUQQ2PSZ256rrk */ }, { /* 4584 */ 433, /* VCVTUQQ2PSZ256rrkz */ }, { /* 4585 */ 434, /* VCVTUQQ2PSZrm */ }, { /* 4586 */ 306, /* VCVTUQQ2PSZrmb */ }, { /* 4587 */ 307, /* VCVTUQQ2PSZrmbk */ }, { /* 4588 */ 308, /* VCVTUQQ2PSZrmbkz */ }, { /* 4589 */ 435, /* VCVTUQQ2PSZrmk */ }, { /* 4590 */ 436, /* VCVTUQQ2PSZrmkz */ }, { /* 4591 */ 437, /* VCVTUQQ2PSZrr */ }, { /* 4592 */ 438, /* VCVTUQQ2PSZrrb */ }, { /* 4593 */ 439, /* VCVTUQQ2PSZrrbk */ }, { /* 4594 */ 440, /* VCVTUQQ2PSZrrbkz */ }, { /* 4595 */ 441, /* VCVTUQQ2PSZrrk */ }, { /* 4596 */ 442, /* VCVTUQQ2PSZrrkz */ }, { /* 4597 */ 237, /* VCVTUSI2SDZrm */ }, { /* 4598 */ 0, /* */ }, { /* 4599 */ 479, /* VCVTUSI2SDZrr */ }, { /* 4600 */ 0, /* */ }, { /* 4601 */ 237, /* VCVTUSI2SSZrm */ }, { /* 4602 */ 0, /* */ }, { /* 4603 */ 479, /* VCVTUSI2SSZrr */ }, { /* 4604 */ 0, /* */ }, { /* 4605 */ 480, /* VCVTUSI2SSZrrb_Int */ }, { /* 4606 */ 207, /* VCVTUSI642SDZrm */ }, { /* 4607 */ 0, /* */ }, { /* 4608 */ 482, /* VCVTUSI642SDZrr */ }, { /* 4609 */ 0, /* */ }, { /* 4610 */ 483, /* VCVTUSI642SDZrrb_Int */ }, { /* 4611 */ 207, /* VCVTUSI642SSZrm */ }, { /* 4612 */ 0, /* */ }, { /* 4613 */ 482, /* VCVTUSI642SSZrr */ }, { /* 4614 */ 0, /* */ }, { /* 4615 */ 483, /* VCVTUSI642SSZrrb_Int */ }, { /* 4616 */ 264, /* VDBPSADBWZ128rmi */ }, { /* 4617 */ 265, /* VDBPSADBWZ128rmik */ }, { /* 4618 */ 266, /* VDBPSADBWZ128rmikz */ }, { /* 4619 */ 267, /* VDBPSADBWZ128rri */ }, { /* 4620 */ 268, /* VDBPSADBWZ128rrik */ }, { /* 4621 */ 269, /* VDBPSADBWZ128rrikz */ }, { /* 4622 */ 273, /* VDBPSADBWZ256rmi */ }, { /* 4623 */ 274, /* VDBPSADBWZ256rmik */ }, { /* 4624 */ 275, /* VDBPSADBWZ256rmikz */ }, { /* 4625 */ 276, /* VDBPSADBWZ256rri */ }, { /* 4626 */ 277, /* VDBPSADBWZ256rrik */ }, { /* 4627 */ 278, /* VDBPSADBWZ256rrikz */ }, { /* 4628 */ 282, /* VDBPSADBWZrmi */ }, { /* 4629 */ 283, /* VDBPSADBWZrmik */ }, { /* 4630 */ 284, /* VDBPSADBWZrmikz */ }, { /* 4631 */ 285, /* VDBPSADBWZrri */ }, { /* 4632 */ 286, /* VDBPSADBWZrrik */ }, { /* 4633 */ 287, /* VDBPSADBWZrrikz */ }, { /* 4634 */ 204, /* VDIVPDYrm */ }, { /* 4635 */ 205, /* VDIVPDYrr */ }, { /* 4636 */ 206, /* VDIVPDZ128rm */ }, { /* 4637 */ 207, /* VDIVPDZ128rmb */ }, { /* 4638 */ 208, /* VDIVPDZ128rmbk */ }, { /* 4639 */ 209, /* VDIVPDZ128rmbkz */ }, { /* 4640 */ 203, /* VDIVPDZ128rmk */ }, { /* 4641 */ 210, /* VDIVPDZ128rmkz */ }, { /* 4642 */ 211, /* VDIVPDZ128rr */ }, { /* 4643 */ 212, /* VDIVPDZ128rrk */ }, { /* 4644 */ 213, /* VDIVPDZ128rrkz */ }, { /* 4645 */ 214, /* VDIVPDZ256rm */ }, { /* 4646 */ 215, /* VDIVPDZ256rmb */ }, { /* 4647 */ 216, /* VDIVPDZ256rmbk */ }, { /* 4648 */ 217, /* VDIVPDZ256rmbkz */ }, { /* 4649 */ 218, /* VDIVPDZ256rmk */ }, { /* 4650 */ 219, /* VDIVPDZ256rmkz */ }, { /* 4651 */ 220, /* VDIVPDZ256rr */ }, { /* 4652 */ 221, /* VDIVPDZ256rrk */ }, { /* 4653 */ 222, /* VDIVPDZ256rrkz */ }, { /* 4654 */ 223, /* VDIVPDZrm */ }, { /* 4655 */ 224, /* VDIVPDZrmb */ }, { /* 4656 */ 225, /* VDIVPDZrmbk */ }, { /* 4657 */ 226, /* VDIVPDZrmbkz */ }, { /* 4658 */ 227, /* VDIVPDZrmk */ }, { /* 4659 */ 228, /* VDIVPDZrmkz */ }, { /* 4660 */ 229, /* VDIVPDZrr */ }, { /* 4661 */ 230, /* VDIVPDZrrb */ }, { /* 4662 */ 231, /* VDIVPDZrrbk */ }, { /* 4663 */ 232, /* VDIVPDZrrbkz */ }, { /* 4664 */ 233, /* VDIVPDZrrk */ }, { /* 4665 */ 234, /* VDIVPDZrrkz */ }, { /* 4666 */ 235, /* VDIVPDrm */ }, { /* 4667 */ 236, /* VDIVPDrr */ }, { /* 4668 */ 204, /* VDIVPSYrm */ }, { /* 4669 */ 205, /* VDIVPSYrr */ }, { /* 4670 */ 206, /* VDIVPSZ128rm */ }, { /* 4671 */ 237, /* VDIVPSZ128rmb */ }, { /* 4672 */ 238, /* VDIVPSZ128rmbk */ }, { /* 4673 */ 239, /* VDIVPSZ128rmbkz */ }, { /* 4674 */ 203, /* VDIVPSZ128rmk */ }, { /* 4675 */ 210, /* VDIVPSZ128rmkz */ }, { /* 4676 */ 211, /* VDIVPSZ128rr */ }, { /* 4677 */ 212, /* VDIVPSZ128rrk */ }, { /* 4678 */ 213, /* VDIVPSZ128rrkz */ }, { /* 4679 */ 214, /* VDIVPSZ256rm */ }, { /* 4680 */ 240, /* VDIVPSZ256rmb */ }, { /* 4681 */ 241, /* VDIVPSZ256rmbk */ }, { /* 4682 */ 242, /* VDIVPSZ256rmbkz */ }, { /* 4683 */ 218, /* VDIVPSZ256rmk */ }, { /* 4684 */ 219, /* VDIVPSZ256rmkz */ }, { /* 4685 */ 220, /* VDIVPSZ256rr */ }, { /* 4686 */ 221, /* VDIVPSZ256rrk */ }, { /* 4687 */ 222, /* VDIVPSZ256rrkz */ }, { /* 4688 */ 223, /* VDIVPSZrm */ }, { /* 4689 */ 243, /* VDIVPSZrmb */ }, { /* 4690 */ 244, /* VDIVPSZrmbk */ }, { /* 4691 */ 245, /* VDIVPSZrmbkz */ }, { /* 4692 */ 227, /* VDIVPSZrmk */ }, { /* 4693 */ 228, /* VDIVPSZrmkz */ }, { /* 4694 */ 229, /* VDIVPSZrr */ }, { /* 4695 */ 246, /* VDIVPSZrrb */ }, { /* 4696 */ 247, /* VDIVPSZrrbk */ }, { /* 4697 */ 248, /* VDIVPSZrrbkz */ }, { /* 4698 */ 233, /* VDIVPSZrrk */ }, { /* 4699 */ 234, /* VDIVPSZrrkz */ }, { /* 4700 */ 235, /* VDIVPSrm */ }, { /* 4701 */ 236, /* VDIVPSrr */ }, { /* 4702 */ 0, /* */ }, { /* 4703 */ 207, /* VDIVSDZrm_Int */ }, { /* 4704 */ 208, /* VDIVSDZrm_Intk */ }, { /* 4705 */ 209, /* VDIVSDZrm_Intkz */ }, { /* 4706 */ 0, /* */ }, { /* 4707 */ 249, /* VDIVSDZrr_Int */ }, { /* 4708 */ 250, /* VDIVSDZrr_Intk */ }, { /* 4709 */ 251, /* VDIVSDZrr_Intkz */ }, { /* 4710 */ 252, /* VDIVSDZrrb_Int */ }, { /* 4711 */ 253, /* VDIVSDZrrb_Intk */ }, { /* 4712 */ 254, /* VDIVSDZrrb_Intkz */ }, { /* 4713 */ 235, /* VDIVSDrm */ }, { /* 4714 */ 0, /* */ }, { /* 4715 */ 236, /* VDIVSDrr */ }, { /* 4716 */ 0, /* */ }, { /* 4717 */ 0, /* */ }, { /* 4718 */ 237, /* VDIVSSZrm_Int */ }, { /* 4719 */ 238, /* VDIVSSZrm_Intk */ }, { /* 4720 */ 239, /* VDIVSSZrm_Intkz */ }, { /* 4721 */ 0, /* */ }, { /* 4722 */ 255, /* VDIVSSZrr_Int */ }, { /* 4723 */ 256, /* VDIVSSZrr_Intk */ }, { /* 4724 */ 257, /* VDIVSSZrr_Intkz */ }, { /* 4725 */ 258, /* VDIVSSZrrb_Int */ }, { /* 4726 */ 259, /* VDIVSSZrrb_Intk */ }, { /* 4727 */ 260, /* VDIVSSZrrb_Intkz */ }, { /* 4728 */ 235, /* VDIVSSrm */ }, { /* 4729 */ 0, /* */ }, { /* 4730 */ 236, /* VDIVSSrr */ }, { /* 4731 */ 0, /* */ }, { /* 4732 */ 299, /* VDPPDrmi */ }, { /* 4733 */ 300, /* VDPPDrri */ }, { /* 4734 */ 297, /* VDPPSYrmi */ }, { /* 4735 */ 298, /* VDPPSYrri */ }, { /* 4736 */ 299, /* VDPPSrmi */ }, { /* 4737 */ 300, /* VDPPSrri */ }, { /* 4738 */ 28, /* VERRm */ }, { /* 4739 */ 123, /* VERRr */ }, { /* 4740 */ 28, /* VERWm */ }, { /* 4741 */ 123, /* VERWr */ }, { /* 4742 */ 418, /* VEXP2PDZm */ }, { /* 4743 */ 312, /* VEXP2PDZmb */ }, { /* 4744 */ 313, /* VEXP2PDZmbk */ }, { /* 4745 */ 314, /* VEXP2PDZmbkz */ }, { /* 4746 */ 419, /* VEXP2PDZmk */ }, { /* 4747 */ 420, /* VEXP2PDZmkz */ }, { /* 4748 */ 421, /* VEXP2PDZr */ }, { /* 4749 */ 494, /* VEXP2PDZrb */ }, { /* 4750 */ 495, /* VEXP2PDZrbk */ }, { /* 4751 */ 496, /* VEXP2PDZrbkz */ }, { /* 4752 */ 425, /* VEXP2PDZrk */ }, { /* 4753 */ 426, /* VEXP2PDZrkz */ }, { /* 4754 */ 418, /* VEXP2PSZm */ }, { /* 4755 */ 340, /* VEXP2PSZmb */ }, { /* 4756 */ 341, /* VEXP2PSZmbk */ }, { /* 4757 */ 342, /* VEXP2PSZmbkz */ }, { /* 4758 */ 419, /* VEXP2PSZmk */ }, { /* 4759 */ 420, /* VEXP2PSZmkz */ }, { /* 4760 */ 421, /* VEXP2PSZr */ }, { /* 4761 */ 497, /* VEXP2PSZrb */ }, { /* 4762 */ 498, /* VEXP2PSZrbk */ }, { /* 4763 */ 499, /* VEXP2PSZrbkz */ }, { /* 4764 */ 425, /* VEXP2PSZrk */ }, { /* 4765 */ 426, /* VEXP2PSZrkz */ }, { /* 4766 */ 327, /* VEXPANDPDZ128rm */ }, { /* 4767 */ 328, /* VEXPANDPDZ128rmk */ }, { /* 4768 */ 329, /* VEXPANDPDZ128rmkz */ }, { /* 4769 */ 330, /* VEXPANDPDZ128rr */ }, { /* 4770 */ 331, /* VEXPANDPDZ128rrk */ }, { /* 4771 */ 332, /* VEXPANDPDZ128rrkz */ }, { /* 4772 */ 306, /* VEXPANDPDZ256rm */ }, { /* 4773 */ 307, /* VEXPANDPDZ256rmk */ }, { /* 4774 */ 308, /* VEXPANDPDZ256rmkz */ }, { /* 4775 */ 415, /* VEXPANDPDZ256rr */ }, { /* 4776 */ 416, /* VEXPANDPDZ256rrk */ }, { /* 4777 */ 417, /* VEXPANDPDZ256rrkz */ }, { /* 4778 */ 312, /* VEXPANDPDZrm */ }, { /* 4779 */ 313, /* VEXPANDPDZrmk */ }, { /* 4780 */ 314, /* VEXPANDPDZrmkz */ }, { /* 4781 */ 421, /* VEXPANDPDZrr */ }, { /* 4782 */ 425, /* VEXPANDPDZrrk */ }, { /* 4783 */ 426, /* VEXPANDPDZrrkz */ }, { /* 4784 */ 334, /* VEXPANDPSZ128rm */ }, { /* 4785 */ 335, /* VEXPANDPSZ128rmk */ }, { /* 4786 */ 336, /* VEXPANDPSZ128rmkz */ }, { /* 4787 */ 330, /* VEXPANDPSZ128rr */ }, { /* 4788 */ 331, /* VEXPANDPSZ128rrk */ }, { /* 4789 */ 332, /* VEXPANDPSZ128rrkz */ }, { /* 4790 */ 337, /* VEXPANDPSZ256rm */ }, { /* 4791 */ 338, /* VEXPANDPSZ256rmk */ }, { /* 4792 */ 339, /* VEXPANDPSZ256rmkz */ }, { /* 4793 */ 415, /* VEXPANDPSZ256rr */ }, { /* 4794 */ 416, /* VEXPANDPSZ256rrk */ }, { /* 4795 */ 417, /* VEXPANDPSZ256rrkz */ }, { /* 4796 */ 340, /* VEXPANDPSZrm */ }, { /* 4797 */ 341, /* VEXPANDPSZrmk */ }, { /* 4798 */ 342, /* VEXPANDPSZrmkz */ }, { /* 4799 */ 421, /* VEXPANDPSZrr */ }, { /* 4800 */ 425, /* VEXPANDPSZrrk */ }, { /* 4801 */ 426, /* VEXPANDPSZrrkz */ }, { /* 4802 */ 449, /* VEXTRACTF128mr */ }, { /* 4803 */ 450, /* VEXTRACTF128rr */ }, { /* 4804 */ 456, /* VEXTRACTF32x4Z256mr */ }, { /* 4805 */ 457, /* VEXTRACTF32x4Z256mrk */ }, { /* 4806 */ 458, /* VEXTRACTF32x4Z256rr */ }, { /* 4807 */ 459, /* VEXTRACTF32x4Z256rrk */ }, { /* 4808 */ 460, /* VEXTRACTF32x4Z256rrkz */ }, { /* 4809 */ 500, /* VEXTRACTF32x4Zmr */ }, { /* 4810 */ 501, /* VEXTRACTF32x4Zmrk */ }, { /* 4811 */ 502, /* VEXTRACTF32x4Zrr */ }, { /* 4812 */ 503, /* VEXTRACTF32x4Zrrk */ }, { /* 4813 */ 504, /* VEXTRACTF32x4Zrrkz */ }, { /* 4814 */ 461, /* VEXTRACTF32x8Zmr */ }, { /* 4815 */ 462, /* VEXTRACTF32x8Zmrk */ }, { /* 4816 */ 463, /* VEXTRACTF32x8Zrr */ }, { /* 4817 */ 467, /* VEXTRACTF32x8Zrrk */ }, { /* 4818 */ 468, /* VEXTRACTF32x8Zrrkz */ }, { /* 4819 */ 456, /* VEXTRACTF64x2Z256mr */ }, { /* 4820 */ 457, /* VEXTRACTF64x2Z256mrk */ }, { /* 4821 */ 458, /* VEXTRACTF64x2Z256rr */ }, { /* 4822 */ 459, /* VEXTRACTF64x2Z256rrk */ }, { /* 4823 */ 460, /* VEXTRACTF64x2Z256rrkz */ }, { /* 4824 */ 500, /* VEXTRACTF64x2Zmr */ }, { /* 4825 */ 501, /* VEXTRACTF64x2Zmrk */ }, { /* 4826 */ 502, /* VEXTRACTF64x2Zrr */ }, { /* 4827 */ 503, /* VEXTRACTF64x2Zrrk */ }, { /* 4828 */ 504, /* VEXTRACTF64x2Zrrkz */ }, { /* 4829 */ 461, /* VEXTRACTF64x4Zmr */ }, { /* 4830 */ 462, /* VEXTRACTF64x4Zmrk */ }, { /* 4831 */ 463, /* VEXTRACTF64x4Zrr */ }, { /* 4832 */ 467, /* VEXTRACTF64x4Zrrk */ }, { /* 4833 */ 468, /* VEXTRACTF64x4Zrrkz */ }, { /* 4834 */ 449, /* VEXTRACTI128mr */ }, { /* 4835 */ 450, /* VEXTRACTI128rr */ }, { /* 4836 */ 456, /* VEXTRACTI32x4Z256mr */ }, { /* 4837 */ 457, /* VEXTRACTI32x4Z256mrk */ }, { /* 4838 */ 458, /* VEXTRACTI32x4Z256rr */ }, { /* 4839 */ 459, /* VEXTRACTI32x4Z256rrk */ }, { /* 4840 */ 460, /* VEXTRACTI32x4Z256rrkz */ }, { /* 4841 */ 500, /* VEXTRACTI32x4Zmr */ }, { /* 4842 */ 501, /* VEXTRACTI32x4Zmrk */ }, { /* 4843 */ 502, /* VEXTRACTI32x4Zrr */ }, { /* 4844 */ 503, /* VEXTRACTI32x4Zrrk */ }, { /* 4845 */ 504, /* VEXTRACTI32x4Zrrkz */ }, { /* 4846 */ 461, /* VEXTRACTI32x8Zmr */ }, { /* 4847 */ 462, /* VEXTRACTI32x8Zmrk */ }, { /* 4848 */ 463, /* VEXTRACTI32x8Zrr */ }, { /* 4849 */ 467, /* VEXTRACTI32x8Zrrk */ }, { /* 4850 */ 468, /* VEXTRACTI32x8Zrrkz */ }, { /* 4851 */ 456, /* VEXTRACTI64x2Z256mr */ }, { /* 4852 */ 457, /* VEXTRACTI64x2Z256mrk */ }, { /* 4853 */ 458, /* VEXTRACTI64x2Z256rr */ }, { /* 4854 */ 459, /* VEXTRACTI64x2Z256rrk */ }, { /* 4855 */ 460, /* VEXTRACTI64x2Z256rrkz */ }, { /* 4856 */ 500, /* VEXTRACTI64x2Zmr */ }, { /* 4857 */ 501, /* VEXTRACTI64x2Zmrk */ }, { /* 4858 */ 502, /* VEXTRACTI64x2Zrr */ }, { /* 4859 */ 503, /* VEXTRACTI64x2Zrrk */ }, { /* 4860 */ 504, /* VEXTRACTI64x2Zrrkz */ }, { /* 4861 */ 461, /* VEXTRACTI64x4Zmr */ }, { /* 4862 */ 462, /* VEXTRACTI64x4Zmrk */ }, { /* 4863 */ 463, /* VEXTRACTI64x4Zrr */ }, { /* 4864 */ 467, /* VEXTRACTI64x4Zrrk */ }, { /* 4865 */ 468, /* VEXTRACTI64x4Zrrkz */ }, { /* 4866 */ 505, /* VEXTRACTPSZmr */ }, { /* 4867 */ 506, /* VEXTRACTPSZrr */ }, { /* 4868 */ 96, /* VEXTRACTPSmr */ }, { /* 4869 */ 97, /* VEXTRACTPSrr */ }, { /* 4870 */ 507, /* VFIXUPIMMPDZ128rmbi */ }, { /* 4871 */ 289, /* VFIXUPIMMPDZ128rmbik */ }, { /* 4872 */ 289, /* VFIXUPIMMPDZ128rmbikz */ }, { /* 4873 */ 508, /* VFIXUPIMMPDZ128rmi */ }, { /* 4874 */ 265, /* VFIXUPIMMPDZ128rmik */ }, { /* 4875 */ 265, /* VFIXUPIMMPDZ128rmikz */ }, { /* 4876 */ 509, /* VFIXUPIMMPDZ128rri */ }, { /* 4877 */ 268, /* VFIXUPIMMPDZ128rrik */ }, { /* 4878 */ 268, /* VFIXUPIMMPDZ128rrikz */ }, { /* 4879 */ 510, /* VFIXUPIMMPDZ256rmbi */ }, { /* 4880 */ 292, /* VFIXUPIMMPDZ256rmbik */ }, { /* 4881 */ 292, /* VFIXUPIMMPDZ256rmbikz */ }, { /* 4882 */ 511, /* VFIXUPIMMPDZ256rmi */ }, { /* 4883 */ 274, /* VFIXUPIMMPDZ256rmik */ }, { /* 4884 */ 274, /* VFIXUPIMMPDZ256rmikz */ }, { /* 4885 */ 512, /* VFIXUPIMMPDZ256rri */ }, { /* 4886 */ 277, /* VFIXUPIMMPDZ256rrik */ }, { /* 4887 */ 277, /* VFIXUPIMMPDZ256rrikz */ }, { /* 4888 */ 513, /* VFIXUPIMMPDZrmbi */ }, { /* 4889 */ 295, /* VFIXUPIMMPDZrmbik */ }, { /* 4890 */ 295, /* VFIXUPIMMPDZrmbikz */ }, { /* 4891 */ 514, /* VFIXUPIMMPDZrmi */ }, { /* 4892 */ 283, /* VFIXUPIMMPDZrmik */ }, { /* 4893 */ 283, /* VFIXUPIMMPDZrmikz */ }, { /* 4894 */ 515, /* VFIXUPIMMPDZrri */ }, { /* 4895 */ 516, /* VFIXUPIMMPDZrrib */ }, { /* 4896 */ 517, /* VFIXUPIMMPDZrribk */ }, { /* 4897 */ 517, /* VFIXUPIMMPDZrribkz */ }, { /* 4898 */ 286, /* VFIXUPIMMPDZrrik */ }, { /* 4899 */ 286, /* VFIXUPIMMPDZrrikz */ }, { /* 4900 */ 518, /* VFIXUPIMMPSZ128rmbi */ }, { /* 4901 */ 262, /* VFIXUPIMMPSZ128rmbik */ }, { /* 4902 */ 262, /* VFIXUPIMMPSZ128rmbikz */ }, { /* 4903 */ 508, /* VFIXUPIMMPSZ128rmi */ }, { /* 4904 */ 265, /* VFIXUPIMMPSZ128rmik */ }, { /* 4905 */ 265, /* VFIXUPIMMPSZ128rmikz */ }, { /* 4906 */ 509, /* VFIXUPIMMPSZ128rri */ }, { /* 4907 */ 268, /* VFIXUPIMMPSZ128rrik */ }, { /* 4908 */ 268, /* VFIXUPIMMPSZ128rrikz */ }, { /* 4909 */ 519, /* VFIXUPIMMPSZ256rmbi */ }, { /* 4910 */ 271, /* VFIXUPIMMPSZ256rmbik */ }, { /* 4911 */ 271, /* VFIXUPIMMPSZ256rmbikz */ }, { /* 4912 */ 511, /* VFIXUPIMMPSZ256rmi */ }, { /* 4913 */ 274, /* VFIXUPIMMPSZ256rmik */ }, { /* 4914 */ 274, /* VFIXUPIMMPSZ256rmikz */ }, { /* 4915 */ 512, /* VFIXUPIMMPSZ256rri */ }, { /* 4916 */ 277, /* VFIXUPIMMPSZ256rrik */ }, { /* 4917 */ 277, /* VFIXUPIMMPSZ256rrikz */ }, { /* 4918 */ 520, /* VFIXUPIMMPSZrmbi */ }, { /* 4919 */ 280, /* VFIXUPIMMPSZrmbik */ }, { /* 4920 */ 280, /* VFIXUPIMMPSZrmbikz */ }, { /* 4921 */ 514, /* VFIXUPIMMPSZrmi */ }, { /* 4922 */ 283, /* VFIXUPIMMPSZrmik */ }, { /* 4923 */ 283, /* VFIXUPIMMPSZrmikz */ }, { /* 4924 */ 515, /* VFIXUPIMMPSZrri */ }, { /* 4925 */ 521, /* VFIXUPIMMPSZrrib */ }, { /* 4926 */ 522, /* VFIXUPIMMPSZrribk */ }, { /* 4927 */ 522, /* VFIXUPIMMPSZrribkz */ }, { /* 4928 */ 286, /* VFIXUPIMMPSZrrik */ }, { /* 4929 */ 286, /* VFIXUPIMMPSZrrikz */ }, { /* 4930 */ 507, /* VFIXUPIMMSDZrmi */ }, { /* 4931 */ 289, /* VFIXUPIMMSDZrmik */ }, { /* 4932 */ 289, /* VFIXUPIMMSDZrmikz */ }, { /* 4933 */ 523, /* VFIXUPIMMSDZrri */ }, { /* 4934 */ 523, /* VFIXUPIMMSDZrrib */ }, { /* 4935 */ 524, /* VFIXUPIMMSDZrribk */ }, { /* 4936 */ 524, /* VFIXUPIMMSDZrribkz */ }, { /* 4937 */ 524, /* VFIXUPIMMSDZrrik */ }, { /* 4938 */ 524, /* VFIXUPIMMSDZrrikz */ }, { /* 4939 */ 518, /* VFIXUPIMMSSZrmi */ }, { /* 4940 */ 262, /* VFIXUPIMMSSZrmik */ }, { /* 4941 */ 262, /* VFIXUPIMMSSZrmikz */ }, { /* 4942 */ 525, /* VFIXUPIMMSSZrri */ }, { /* 4943 */ 525, /* VFIXUPIMMSSZrrib */ }, { /* 4944 */ 526, /* VFIXUPIMMSSZrribk */ }, { /* 4945 */ 526, /* VFIXUPIMMSSZrribkz */ }, { /* 4946 */ 526, /* VFIXUPIMMSSZrrik */ }, { /* 4947 */ 526, /* VFIXUPIMMSSZrrikz */ }, { /* 4948 */ 527, /* VFMADD132PDYm */ }, { /* 4949 */ 528, /* VFMADD132PDYr */ }, { /* 4950 */ 202, /* VFMADD132PDZ128m */ }, { /* 4951 */ 529, /* VFMADD132PDZ128mb */ }, { /* 4952 */ 208, /* VFMADD132PDZ128mbk */ }, { /* 4953 */ 208, /* VFMADD132PDZ128mbkz */ }, { /* 4954 */ 203, /* VFMADD132PDZ128mk */ }, { /* 4955 */ 203, /* VFMADD132PDZ128mkz */ }, { /* 4956 */ 530, /* VFMADD132PDZ128r */ }, { /* 4957 */ 212, /* VFMADD132PDZ128rk */ }, { /* 4958 */ 212, /* VFMADD132PDZ128rkz */ }, { /* 4959 */ 531, /* VFMADD132PDZ256m */ }, { /* 4960 */ 532, /* VFMADD132PDZ256mb */ }, { /* 4961 */ 216, /* VFMADD132PDZ256mbk */ }, { /* 4962 */ 216, /* VFMADD132PDZ256mbkz */ }, { /* 4963 */ 218, /* VFMADD132PDZ256mk */ }, { /* 4964 */ 218, /* VFMADD132PDZ256mkz */ }, { /* 4965 */ 533, /* VFMADD132PDZ256r */ }, { /* 4966 */ 221, /* VFMADD132PDZ256rk */ }, { /* 4967 */ 221, /* VFMADD132PDZ256rkz */ }, { /* 4968 */ 534, /* VFMADD132PDZm */ }, { /* 4969 */ 535, /* VFMADD132PDZmb */ }, { /* 4970 */ 225, /* VFMADD132PDZmbk */ }, { /* 4971 */ 225, /* VFMADD132PDZmbkz */ }, { /* 4972 */ 227, /* VFMADD132PDZmk */ }, { /* 4973 */ 227, /* VFMADD132PDZmkz */ }, { /* 4974 */ 536, /* VFMADD132PDZr */ }, { /* 4975 */ 537, /* VFMADD132PDZrb */ }, { /* 4976 */ 231, /* VFMADD132PDZrbk */ }, { /* 4977 */ 231, /* VFMADD132PDZrbkz */ }, { /* 4978 */ 233, /* VFMADD132PDZrk */ }, { /* 4979 */ 233, /* VFMADD132PDZrkz */ }, { /* 4980 */ 538, /* VFMADD132PDm */ }, { /* 4981 */ 539, /* VFMADD132PDr */ }, { /* 4982 */ 527, /* VFMADD132PSYm */ }, { /* 4983 */ 528, /* VFMADD132PSYr */ }, { /* 4984 */ 202, /* VFMADD132PSZ128m */ }, { /* 4985 */ 540, /* VFMADD132PSZ128mb */ }, { /* 4986 */ 238, /* VFMADD132PSZ128mbk */ }, { /* 4987 */ 238, /* VFMADD132PSZ128mbkz */ }, { /* 4988 */ 203, /* VFMADD132PSZ128mk */ }, { /* 4989 */ 203, /* VFMADD132PSZ128mkz */ }, { /* 4990 */ 530, /* VFMADD132PSZ128r */ }, { /* 4991 */ 212, /* VFMADD132PSZ128rk */ }, { /* 4992 */ 212, /* VFMADD132PSZ128rkz */ }, { /* 4993 */ 531, /* VFMADD132PSZ256m */ }, { /* 4994 */ 541, /* VFMADD132PSZ256mb */ }, { /* 4995 */ 241, /* VFMADD132PSZ256mbk */ }, { /* 4996 */ 241, /* VFMADD132PSZ256mbkz */ }, { /* 4997 */ 218, /* VFMADD132PSZ256mk */ }, { /* 4998 */ 218, /* VFMADD132PSZ256mkz */ }, { /* 4999 */ 533, /* VFMADD132PSZ256r */ }, { /* 5000 */ 221, /* VFMADD132PSZ256rk */ }, { /* 5001 */ 221, /* VFMADD132PSZ256rkz */ }, { /* 5002 */ 534, /* VFMADD132PSZm */ }, { /* 5003 */ 542, /* VFMADD132PSZmb */ }, { /* 5004 */ 244, /* VFMADD132PSZmbk */ }, { /* 5005 */ 244, /* VFMADD132PSZmbkz */ }, { /* 5006 */ 227, /* VFMADD132PSZmk */ }, { /* 5007 */ 227, /* VFMADD132PSZmkz */ }, { /* 5008 */ 536, /* VFMADD132PSZr */ }, { /* 5009 */ 543, /* VFMADD132PSZrb */ }, { /* 5010 */ 247, /* VFMADD132PSZrbk */ }, { /* 5011 */ 247, /* VFMADD132PSZrbkz */ }, { /* 5012 */ 233, /* VFMADD132PSZrk */ }, { /* 5013 */ 233, /* VFMADD132PSZrkz */ }, { /* 5014 */ 538, /* VFMADD132PSm */ }, { /* 5015 */ 539, /* VFMADD132PSr */ }, { /* 5016 */ 0, /* */ }, { /* 5017 */ 529, /* VFMADD132SDZm_Int */ }, { /* 5018 */ 208, /* VFMADD132SDZm_Intk */ }, { /* 5019 */ 208, /* VFMADD132SDZm_Intkz */ }, { /* 5020 */ 0, /* */ }, { /* 5021 */ 544, /* VFMADD132SDZr_Int */ }, { /* 5022 */ 250, /* VFMADD132SDZr_Intk */ }, { /* 5023 */ 250, /* VFMADD132SDZr_Intkz */ }, { /* 5024 */ 0, /* */ }, { /* 5025 */ 545, /* VFMADD132SDZrb_Int */ }, { /* 5026 */ 253, /* VFMADD132SDZrb_Intk */ }, { /* 5027 */ 253, /* VFMADD132SDZrb_Intkz */ }, { /* 5028 */ 538, /* VFMADD132SDm */ }, { /* 5029 */ 0, /* */ }, { /* 5030 */ 539, /* VFMADD132SDr */ }, { /* 5031 */ 0, /* */ }, { /* 5032 */ 0, /* */ }, { /* 5033 */ 540, /* VFMADD132SSZm_Int */ }, { /* 5034 */ 238, /* VFMADD132SSZm_Intk */ }, { /* 5035 */ 238, /* VFMADD132SSZm_Intkz */ }, { /* 5036 */ 0, /* */ }, { /* 5037 */ 546, /* VFMADD132SSZr_Int */ }, { /* 5038 */ 256, /* VFMADD132SSZr_Intk */ }, { /* 5039 */ 256, /* VFMADD132SSZr_Intkz */ }, { /* 5040 */ 0, /* */ }, { /* 5041 */ 547, /* VFMADD132SSZrb_Int */ }, { /* 5042 */ 259, /* VFMADD132SSZrb_Intk */ }, { /* 5043 */ 259, /* VFMADD132SSZrb_Intkz */ }, { /* 5044 */ 538, /* VFMADD132SSm */ }, { /* 5045 */ 0, /* */ }, { /* 5046 */ 539, /* VFMADD132SSr */ }, { /* 5047 */ 0, /* */ }, { /* 5048 */ 527, /* VFMADD213PDYm */ }, { /* 5049 */ 528, /* VFMADD213PDYr */ }, { /* 5050 */ 202, /* VFMADD213PDZ128m */ }, { /* 5051 */ 529, /* VFMADD213PDZ128mb */ }, { /* 5052 */ 208, /* VFMADD213PDZ128mbk */ }, { /* 5053 */ 208, /* VFMADD213PDZ128mbkz */ }, { /* 5054 */ 203, /* VFMADD213PDZ128mk */ }, { /* 5055 */ 203, /* VFMADD213PDZ128mkz */ }, { /* 5056 */ 530, /* VFMADD213PDZ128r */ }, { /* 5057 */ 212, /* VFMADD213PDZ128rk */ }, { /* 5058 */ 212, /* VFMADD213PDZ128rkz */ }, { /* 5059 */ 531, /* VFMADD213PDZ256m */ }, { /* 5060 */ 532, /* VFMADD213PDZ256mb */ }, { /* 5061 */ 216, /* VFMADD213PDZ256mbk */ }, { /* 5062 */ 216, /* VFMADD213PDZ256mbkz */ }, { /* 5063 */ 218, /* VFMADD213PDZ256mk */ }, { /* 5064 */ 218, /* VFMADD213PDZ256mkz */ }, { /* 5065 */ 533, /* VFMADD213PDZ256r */ }, { /* 5066 */ 221, /* VFMADD213PDZ256rk */ }, { /* 5067 */ 221, /* VFMADD213PDZ256rkz */ }, { /* 5068 */ 534, /* VFMADD213PDZm */ }, { /* 5069 */ 535, /* VFMADD213PDZmb */ }, { /* 5070 */ 225, /* VFMADD213PDZmbk */ }, { /* 5071 */ 225, /* VFMADD213PDZmbkz */ }, { /* 5072 */ 227, /* VFMADD213PDZmk */ }, { /* 5073 */ 227, /* VFMADD213PDZmkz */ }, { /* 5074 */ 536, /* VFMADD213PDZr */ }, { /* 5075 */ 537, /* VFMADD213PDZrb */ }, { /* 5076 */ 231, /* VFMADD213PDZrbk */ }, { /* 5077 */ 231, /* VFMADD213PDZrbkz */ }, { /* 5078 */ 233, /* VFMADD213PDZrk */ }, { /* 5079 */ 233, /* VFMADD213PDZrkz */ }, { /* 5080 */ 538, /* VFMADD213PDm */ }, { /* 5081 */ 539, /* VFMADD213PDr */ }, { /* 5082 */ 527, /* VFMADD213PSYm */ }, { /* 5083 */ 528, /* VFMADD213PSYr */ }, { /* 5084 */ 202, /* VFMADD213PSZ128m */ }, { /* 5085 */ 540, /* VFMADD213PSZ128mb */ }, { /* 5086 */ 238, /* VFMADD213PSZ128mbk */ }, { /* 5087 */ 238, /* VFMADD213PSZ128mbkz */ }, { /* 5088 */ 203, /* VFMADD213PSZ128mk */ }, { /* 5089 */ 203, /* VFMADD213PSZ128mkz */ }, { /* 5090 */ 530, /* VFMADD213PSZ128r */ }, { /* 5091 */ 212, /* VFMADD213PSZ128rk */ }, { /* 5092 */ 212, /* VFMADD213PSZ128rkz */ }, { /* 5093 */ 531, /* VFMADD213PSZ256m */ }, { /* 5094 */ 541, /* VFMADD213PSZ256mb */ }, { /* 5095 */ 241, /* VFMADD213PSZ256mbk */ }, { /* 5096 */ 241, /* VFMADD213PSZ256mbkz */ }, { /* 5097 */ 218, /* VFMADD213PSZ256mk */ }, { /* 5098 */ 218, /* VFMADD213PSZ256mkz */ }, { /* 5099 */ 533, /* VFMADD213PSZ256r */ }, { /* 5100 */ 221, /* VFMADD213PSZ256rk */ }, { /* 5101 */ 221, /* VFMADD213PSZ256rkz */ }, { /* 5102 */ 534, /* VFMADD213PSZm */ }, { /* 5103 */ 542, /* VFMADD213PSZmb */ }, { /* 5104 */ 244, /* VFMADD213PSZmbk */ }, { /* 5105 */ 244, /* VFMADD213PSZmbkz */ }, { /* 5106 */ 227, /* VFMADD213PSZmk */ }, { /* 5107 */ 227, /* VFMADD213PSZmkz */ }, { /* 5108 */ 536, /* VFMADD213PSZr */ }, { /* 5109 */ 543, /* VFMADD213PSZrb */ }, { /* 5110 */ 247, /* VFMADD213PSZrbk */ }, { /* 5111 */ 247, /* VFMADD213PSZrbkz */ }, { /* 5112 */ 233, /* VFMADD213PSZrk */ }, { /* 5113 */ 233, /* VFMADD213PSZrkz */ }, { /* 5114 */ 538, /* VFMADD213PSm */ }, { /* 5115 */ 539, /* VFMADD213PSr */ }, { /* 5116 */ 0, /* */ }, { /* 5117 */ 529, /* VFMADD213SDZm_Int */ }, { /* 5118 */ 208, /* VFMADD213SDZm_Intk */ }, { /* 5119 */ 208, /* VFMADD213SDZm_Intkz */ }, { /* 5120 */ 0, /* */ }, { /* 5121 */ 544, /* VFMADD213SDZr_Int */ }, { /* 5122 */ 250, /* VFMADD213SDZr_Intk */ }, { /* 5123 */ 250, /* VFMADD213SDZr_Intkz */ }, { /* 5124 */ 0, /* */ }, { /* 5125 */ 545, /* VFMADD213SDZrb_Int */ }, { /* 5126 */ 253, /* VFMADD213SDZrb_Intk */ }, { /* 5127 */ 253, /* VFMADD213SDZrb_Intkz */ }, { /* 5128 */ 538, /* VFMADD213SDm */ }, { /* 5129 */ 0, /* */ }, { /* 5130 */ 539, /* VFMADD213SDr */ }, { /* 5131 */ 0, /* */ }, { /* 5132 */ 0, /* */ }, { /* 5133 */ 540, /* VFMADD213SSZm_Int */ }, { /* 5134 */ 238, /* VFMADD213SSZm_Intk */ }, { /* 5135 */ 238, /* VFMADD213SSZm_Intkz */ }, { /* 5136 */ 0, /* */ }, { /* 5137 */ 546, /* VFMADD213SSZr_Int */ }, { /* 5138 */ 256, /* VFMADD213SSZr_Intk */ }, { /* 5139 */ 256, /* VFMADD213SSZr_Intkz */ }, { /* 5140 */ 0, /* */ }, { /* 5141 */ 547, /* VFMADD213SSZrb_Int */ }, { /* 5142 */ 259, /* VFMADD213SSZrb_Intk */ }, { /* 5143 */ 259, /* VFMADD213SSZrb_Intkz */ }, { /* 5144 */ 538, /* VFMADD213SSm */ }, { /* 5145 */ 0, /* */ }, { /* 5146 */ 539, /* VFMADD213SSr */ }, { /* 5147 */ 0, /* */ }, { /* 5148 */ 527, /* VFMADD231PDYm */ }, { /* 5149 */ 528, /* VFMADD231PDYr */ }, { /* 5150 */ 202, /* VFMADD231PDZ128m */ }, { /* 5151 */ 529, /* VFMADD231PDZ128mb */ }, { /* 5152 */ 208, /* VFMADD231PDZ128mbk */ }, { /* 5153 */ 208, /* VFMADD231PDZ128mbkz */ }, { /* 5154 */ 203, /* VFMADD231PDZ128mk */ }, { /* 5155 */ 203, /* VFMADD231PDZ128mkz */ }, { /* 5156 */ 530, /* VFMADD231PDZ128r */ }, { /* 5157 */ 212, /* VFMADD231PDZ128rk */ }, { /* 5158 */ 212, /* VFMADD231PDZ128rkz */ }, { /* 5159 */ 531, /* VFMADD231PDZ256m */ }, { /* 5160 */ 532, /* VFMADD231PDZ256mb */ }, { /* 5161 */ 216, /* VFMADD231PDZ256mbk */ }, { /* 5162 */ 216, /* VFMADD231PDZ256mbkz */ }, { /* 5163 */ 218, /* VFMADD231PDZ256mk */ }, { /* 5164 */ 218, /* VFMADD231PDZ256mkz */ }, { /* 5165 */ 533, /* VFMADD231PDZ256r */ }, { /* 5166 */ 221, /* VFMADD231PDZ256rk */ }, { /* 5167 */ 221, /* VFMADD231PDZ256rkz */ }, { /* 5168 */ 534, /* VFMADD231PDZm */ }, { /* 5169 */ 535, /* VFMADD231PDZmb */ }, { /* 5170 */ 225, /* VFMADD231PDZmbk */ }, { /* 5171 */ 225, /* VFMADD231PDZmbkz */ }, { /* 5172 */ 227, /* VFMADD231PDZmk */ }, { /* 5173 */ 227, /* VFMADD231PDZmkz */ }, { /* 5174 */ 536, /* VFMADD231PDZr */ }, { /* 5175 */ 537, /* VFMADD231PDZrb */ }, { /* 5176 */ 231, /* VFMADD231PDZrbk */ }, { /* 5177 */ 231, /* VFMADD231PDZrbkz */ }, { /* 5178 */ 233, /* VFMADD231PDZrk */ }, { /* 5179 */ 233, /* VFMADD231PDZrkz */ }, { /* 5180 */ 538, /* VFMADD231PDm */ }, { /* 5181 */ 539, /* VFMADD231PDr */ }, { /* 5182 */ 527, /* VFMADD231PSYm */ }, { /* 5183 */ 528, /* VFMADD231PSYr */ }, { /* 5184 */ 202, /* VFMADD231PSZ128m */ }, { /* 5185 */ 540, /* VFMADD231PSZ128mb */ }, { /* 5186 */ 238, /* VFMADD231PSZ128mbk */ }, { /* 5187 */ 238, /* VFMADD231PSZ128mbkz */ }, { /* 5188 */ 203, /* VFMADD231PSZ128mk */ }, { /* 5189 */ 203, /* VFMADD231PSZ128mkz */ }, { /* 5190 */ 530, /* VFMADD231PSZ128r */ }, { /* 5191 */ 212, /* VFMADD231PSZ128rk */ }, { /* 5192 */ 212, /* VFMADD231PSZ128rkz */ }, { /* 5193 */ 531, /* VFMADD231PSZ256m */ }, { /* 5194 */ 541, /* VFMADD231PSZ256mb */ }, { /* 5195 */ 241, /* VFMADD231PSZ256mbk */ }, { /* 5196 */ 241, /* VFMADD231PSZ256mbkz */ }, { /* 5197 */ 218, /* VFMADD231PSZ256mk */ }, { /* 5198 */ 218, /* VFMADD231PSZ256mkz */ }, { /* 5199 */ 533, /* VFMADD231PSZ256r */ }, { /* 5200 */ 221, /* VFMADD231PSZ256rk */ }, { /* 5201 */ 221, /* VFMADD231PSZ256rkz */ }, { /* 5202 */ 534, /* VFMADD231PSZm */ }, { /* 5203 */ 542, /* VFMADD231PSZmb */ }, { /* 5204 */ 244, /* VFMADD231PSZmbk */ }, { /* 5205 */ 244, /* VFMADD231PSZmbkz */ }, { /* 5206 */ 227, /* VFMADD231PSZmk */ }, { /* 5207 */ 227, /* VFMADD231PSZmkz */ }, { /* 5208 */ 536, /* VFMADD231PSZr */ }, { /* 5209 */ 543, /* VFMADD231PSZrb */ }, { /* 5210 */ 247, /* VFMADD231PSZrbk */ }, { /* 5211 */ 247, /* VFMADD231PSZrbkz */ }, { /* 5212 */ 233, /* VFMADD231PSZrk */ }, { /* 5213 */ 233, /* VFMADD231PSZrkz */ }, { /* 5214 */ 538, /* VFMADD231PSm */ }, { /* 5215 */ 539, /* VFMADD231PSr */ }, { /* 5216 */ 0, /* */ }, { /* 5217 */ 529, /* VFMADD231SDZm_Int */ }, { /* 5218 */ 208, /* VFMADD231SDZm_Intk */ }, { /* 5219 */ 208, /* VFMADD231SDZm_Intkz */ }, { /* 5220 */ 0, /* */ }, { /* 5221 */ 544, /* VFMADD231SDZr_Int */ }, { /* 5222 */ 250, /* VFMADD231SDZr_Intk */ }, { /* 5223 */ 250, /* VFMADD231SDZr_Intkz */ }, { /* 5224 */ 0, /* */ }, { /* 5225 */ 545, /* VFMADD231SDZrb_Int */ }, { /* 5226 */ 253, /* VFMADD231SDZrb_Intk */ }, { /* 5227 */ 253, /* VFMADD231SDZrb_Intkz */ }, { /* 5228 */ 538, /* VFMADD231SDm */ }, { /* 5229 */ 0, /* */ }, { /* 5230 */ 539, /* VFMADD231SDr */ }, { /* 5231 */ 0, /* */ }, { /* 5232 */ 0, /* */ }, { /* 5233 */ 540, /* VFMADD231SSZm_Int */ }, { /* 5234 */ 238, /* VFMADD231SSZm_Intk */ }, { /* 5235 */ 238, /* VFMADD231SSZm_Intkz */ }, { /* 5236 */ 0, /* */ }, { /* 5237 */ 546, /* VFMADD231SSZr_Int */ }, { /* 5238 */ 256, /* VFMADD231SSZr_Intk */ }, { /* 5239 */ 256, /* VFMADD231SSZr_Intkz */ }, { /* 5240 */ 0, /* */ }, { /* 5241 */ 547, /* VFMADD231SSZrb_Int */ }, { /* 5242 */ 259, /* VFMADD231SSZrb_Intk */ }, { /* 5243 */ 259, /* VFMADD231SSZrb_Intkz */ }, { /* 5244 */ 538, /* VFMADD231SSm */ }, { /* 5245 */ 0, /* */ }, { /* 5246 */ 539, /* VFMADD231SSr */ }, { /* 5247 */ 0, /* */ }, { /* 5248 */ 301, /* VFMADDPD4Ymr */ }, { /* 5249 */ 548, /* VFMADDPD4Yrm */ }, { /* 5250 */ 549, /* VFMADDPD4Yrr */ }, { /* 5251 */ 302, /* VFMADDPD4Yrr_REV */ }, { /* 5252 */ 303, /* VFMADDPD4mr */ }, { /* 5253 */ 550, /* VFMADDPD4rm */ }, { /* 5254 */ 551, /* VFMADDPD4rr */ }, { /* 5255 */ 304, /* VFMADDPD4rr_REV */ }, { /* 5256 */ 301, /* VFMADDPS4Ymr */ }, { /* 5257 */ 548, /* VFMADDPS4Yrm */ }, { /* 5258 */ 549, /* VFMADDPS4Yrr */ }, { /* 5259 */ 302, /* VFMADDPS4Yrr_REV */ }, { /* 5260 */ 303, /* VFMADDPS4mr */ }, { /* 5261 */ 550, /* VFMADDPS4rm */ }, { /* 5262 */ 551, /* VFMADDPS4rr */ }, { /* 5263 */ 304, /* VFMADDPS4rr_REV */ }, { /* 5264 */ 303, /* VFMADDSD4mr */ }, { /* 5265 */ 0, /* */ }, { /* 5266 */ 550, /* VFMADDSD4rm */ }, { /* 5267 */ 0, /* */ }, { /* 5268 */ 551, /* VFMADDSD4rr */ }, { /* 5269 */ 0, /* */ }, { /* 5270 */ 0, /* */ }, { /* 5271 */ 304, /* VFMADDSD4rr_REV */ }, { /* 5272 */ 303, /* VFMADDSS4mr */ }, { /* 5273 */ 0, /* */ }, { /* 5274 */ 550, /* VFMADDSS4rm */ }, { /* 5275 */ 0, /* */ }, { /* 5276 */ 551, /* VFMADDSS4rr */ }, { /* 5277 */ 0, /* */ }, { /* 5278 */ 0, /* */ }, { /* 5279 */ 304, /* VFMADDSS4rr_REV */ }, { /* 5280 */ 527, /* VFMADDSUB132PDYm */ }, { /* 5281 */ 528, /* VFMADDSUB132PDYr */ }, { /* 5282 */ 202, /* VFMADDSUB132PDZ128m */ }, { /* 5283 */ 529, /* VFMADDSUB132PDZ128mb */ }, { /* 5284 */ 208, /* VFMADDSUB132PDZ128mbk */ }, { /* 5285 */ 208, /* VFMADDSUB132PDZ128mbkz */ }, { /* 5286 */ 203, /* VFMADDSUB132PDZ128mk */ }, { /* 5287 */ 203, /* VFMADDSUB132PDZ128mkz */ }, { /* 5288 */ 530, /* VFMADDSUB132PDZ128r */ }, { /* 5289 */ 212, /* VFMADDSUB132PDZ128rk */ }, { /* 5290 */ 212, /* VFMADDSUB132PDZ128rkz */ }, { /* 5291 */ 531, /* VFMADDSUB132PDZ256m */ }, { /* 5292 */ 532, /* VFMADDSUB132PDZ256mb */ }, { /* 5293 */ 216, /* VFMADDSUB132PDZ256mbk */ }, { /* 5294 */ 216, /* VFMADDSUB132PDZ256mbkz */ }, { /* 5295 */ 218, /* VFMADDSUB132PDZ256mk */ }, { /* 5296 */ 218, /* VFMADDSUB132PDZ256mkz */ }, { /* 5297 */ 533, /* VFMADDSUB132PDZ256r */ }, { /* 5298 */ 221, /* VFMADDSUB132PDZ256rk */ }, { /* 5299 */ 221, /* VFMADDSUB132PDZ256rkz */ }, { /* 5300 */ 534, /* VFMADDSUB132PDZm */ }, { /* 5301 */ 535, /* VFMADDSUB132PDZmb */ }, { /* 5302 */ 225, /* VFMADDSUB132PDZmbk */ }, { /* 5303 */ 225, /* VFMADDSUB132PDZmbkz */ }, { /* 5304 */ 227, /* VFMADDSUB132PDZmk */ }, { /* 5305 */ 227, /* VFMADDSUB132PDZmkz */ }, { /* 5306 */ 536, /* VFMADDSUB132PDZr */ }, { /* 5307 */ 537, /* VFMADDSUB132PDZrb */ }, { /* 5308 */ 231, /* VFMADDSUB132PDZrbk */ }, { /* 5309 */ 231, /* VFMADDSUB132PDZrbkz */ }, { /* 5310 */ 233, /* VFMADDSUB132PDZrk */ }, { /* 5311 */ 233, /* VFMADDSUB132PDZrkz */ }, { /* 5312 */ 538, /* VFMADDSUB132PDm */ }, { /* 5313 */ 539, /* VFMADDSUB132PDr */ }, { /* 5314 */ 527, /* VFMADDSUB132PSYm */ }, { /* 5315 */ 528, /* VFMADDSUB132PSYr */ }, { /* 5316 */ 202, /* VFMADDSUB132PSZ128m */ }, { /* 5317 */ 540, /* VFMADDSUB132PSZ128mb */ }, { /* 5318 */ 238, /* VFMADDSUB132PSZ128mbk */ }, { /* 5319 */ 238, /* VFMADDSUB132PSZ128mbkz */ }, { /* 5320 */ 203, /* VFMADDSUB132PSZ128mk */ }, { /* 5321 */ 203, /* VFMADDSUB132PSZ128mkz */ }, { /* 5322 */ 530, /* VFMADDSUB132PSZ128r */ }, { /* 5323 */ 212, /* VFMADDSUB132PSZ128rk */ }, { /* 5324 */ 212, /* VFMADDSUB132PSZ128rkz */ }, { /* 5325 */ 531, /* VFMADDSUB132PSZ256m */ }, { /* 5326 */ 541, /* VFMADDSUB132PSZ256mb */ }, { /* 5327 */ 241, /* VFMADDSUB132PSZ256mbk */ }, { /* 5328 */ 241, /* VFMADDSUB132PSZ256mbkz */ }, { /* 5329 */ 218, /* VFMADDSUB132PSZ256mk */ }, { /* 5330 */ 218, /* VFMADDSUB132PSZ256mkz */ }, { /* 5331 */ 533, /* VFMADDSUB132PSZ256r */ }, { /* 5332 */ 221, /* VFMADDSUB132PSZ256rk */ }, { /* 5333 */ 221, /* VFMADDSUB132PSZ256rkz */ }, { /* 5334 */ 534, /* VFMADDSUB132PSZm */ }, { /* 5335 */ 542, /* VFMADDSUB132PSZmb */ }, { /* 5336 */ 244, /* VFMADDSUB132PSZmbk */ }, { /* 5337 */ 244, /* VFMADDSUB132PSZmbkz */ }, { /* 5338 */ 227, /* VFMADDSUB132PSZmk */ }, { /* 5339 */ 227, /* VFMADDSUB132PSZmkz */ }, { /* 5340 */ 536, /* VFMADDSUB132PSZr */ }, { /* 5341 */ 543, /* VFMADDSUB132PSZrb */ }, { /* 5342 */ 247, /* VFMADDSUB132PSZrbk */ }, { /* 5343 */ 247, /* VFMADDSUB132PSZrbkz */ }, { /* 5344 */ 233, /* VFMADDSUB132PSZrk */ }, { /* 5345 */ 233, /* VFMADDSUB132PSZrkz */ }, { /* 5346 */ 538, /* VFMADDSUB132PSm */ }, { /* 5347 */ 539, /* VFMADDSUB132PSr */ }, { /* 5348 */ 527, /* VFMADDSUB213PDYm */ }, { /* 5349 */ 528, /* VFMADDSUB213PDYr */ }, { /* 5350 */ 202, /* VFMADDSUB213PDZ128m */ }, { /* 5351 */ 529, /* VFMADDSUB213PDZ128mb */ }, { /* 5352 */ 208, /* VFMADDSUB213PDZ128mbk */ }, { /* 5353 */ 208, /* VFMADDSUB213PDZ128mbkz */ }, { /* 5354 */ 203, /* VFMADDSUB213PDZ128mk */ }, { /* 5355 */ 203, /* VFMADDSUB213PDZ128mkz */ }, { /* 5356 */ 530, /* VFMADDSUB213PDZ128r */ }, { /* 5357 */ 212, /* VFMADDSUB213PDZ128rk */ }, { /* 5358 */ 212, /* VFMADDSUB213PDZ128rkz */ }, { /* 5359 */ 531, /* VFMADDSUB213PDZ256m */ }, { /* 5360 */ 532, /* VFMADDSUB213PDZ256mb */ }, { /* 5361 */ 216, /* VFMADDSUB213PDZ256mbk */ }, { /* 5362 */ 216, /* VFMADDSUB213PDZ256mbkz */ }, { /* 5363 */ 218, /* VFMADDSUB213PDZ256mk */ }, { /* 5364 */ 218, /* VFMADDSUB213PDZ256mkz */ }, { /* 5365 */ 533, /* VFMADDSUB213PDZ256r */ }, { /* 5366 */ 221, /* VFMADDSUB213PDZ256rk */ }, { /* 5367 */ 221, /* VFMADDSUB213PDZ256rkz */ }, { /* 5368 */ 534, /* VFMADDSUB213PDZm */ }, { /* 5369 */ 535, /* VFMADDSUB213PDZmb */ }, { /* 5370 */ 225, /* VFMADDSUB213PDZmbk */ }, { /* 5371 */ 225, /* VFMADDSUB213PDZmbkz */ }, { /* 5372 */ 227, /* VFMADDSUB213PDZmk */ }, { /* 5373 */ 227, /* VFMADDSUB213PDZmkz */ }, { /* 5374 */ 536, /* VFMADDSUB213PDZr */ }, { /* 5375 */ 537, /* VFMADDSUB213PDZrb */ }, { /* 5376 */ 231, /* VFMADDSUB213PDZrbk */ }, { /* 5377 */ 231, /* VFMADDSUB213PDZrbkz */ }, { /* 5378 */ 233, /* VFMADDSUB213PDZrk */ }, { /* 5379 */ 233, /* VFMADDSUB213PDZrkz */ }, { /* 5380 */ 538, /* VFMADDSUB213PDm */ }, { /* 5381 */ 539, /* VFMADDSUB213PDr */ }, { /* 5382 */ 527, /* VFMADDSUB213PSYm */ }, { /* 5383 */ 528, /* VFMADDSUB213PSYr */ }, { /* 5384 */ 202, /* VFMADDSUB213PSZ128m */ }, { /* 5385 */ 540, /* VFMADDSUB213PSZ128mb */ }, { /* 5386 */ 238, /* VFMADDSUB213PSZ128mbk */ }, { /* 5387 */ 238, /* VFMADDSUB213PSZ128mbkz */ }, { /* 5388 */ 203, /* VFMADDSUB213PSZ128mk */ }, { /* 5389 */ 203, /* VFMADDSUB213PSZ128mkz */ }, { /* 5390 */ 530, /* VFMADDSUB213PSZ128r */ }, { /* 5391 */ 212, /* VFMADDSUB213PSZ128rk */ }, { /* 5392 */ 212, /* VFMADDSUB213PSZ128rkz */ }, { /* 5393 */ 531, /* VFMADDSUB213PSZ256m */ }, { /* 5394 */ 541, /* VFMADDSUB213PSZ256mb */ }, { /* 5395 */ 241, /* VFMADDSUB213PSZ256mbk */ }, { /* 5396 */ 241, /* VFMADDSUB213PSZ256mbkz */ }, { /* 5397 */ 218, /* VFMADDSUB213PSZ256mk */ }, { /* 5398 */ 218, /* VFMADDSUB213PSZ256mkz */ }, { /* 5399 */ 533, /* VFMADDSUB213PSZ256r */ }, { /* 5400 */ 221, /* VFMADDSUB213PSZ256rk */ }, { /* 5401 */ 221, /* VFMADDSUB213PSZ256rkz */ }, { /* 5402 */ 534, /* VFMADDSUB213PSZm */ }, { /* 5403 */ 542, /* VFMADDSUB213PSZmb */ }, { /* 5404 */ 244, /* VFMADDSUB213PSZmbk */ }, { /* 5405 */ 244, /* VFMADDSUB213PSZmbkz */ }, { /* 5406 */ 227, /* VFMADDSUB213PSZmk */ }, { /* 5407 */ 227, /* VFMADDSUB213PSZmkz */ }, { /* 5408 */ 536, /* VFMADDSUB213PSZr */ }, { /* 5409 */ 543, /* VFMADDSUB213PSZrb */ }, { /* 5410 */ 247, /* VFMADDSUB213PSZrbk */ }, { /* 5411 */ 247, /* VFMADDSUB213PSZrbkz */ }, { /* 5412 */ 233, /* VFMADDSUB213PSZrk */ }, { /* 5413 */ 233, /* VFMADDSUB213PSZrkz */ }, { /* 5414 */ 538, /* VFMADDSUB213PSm */ }, { /* 5415 */ 539, /* VFMADDSUB213PSr */ }, { /* 5416 */ 527, /* VFMADDSUB231PDYm */ }, { /* 5417 */ 528, /* VFMADDSUB231PDYr */ }, { /* 5418 */ 202, /* VFMADDSUB231PDZ128m */ }, { /* 5419 */ 529, /* VFMADDSUB231PDZ128mb */ }, { /* 5420 */ 208, /* VFMADDSUB231PDZ128mbk */ }, { /* 5421 */ 208, /* VFMADDSUB231PDZ128mbkz */ }, { /* 5422 */ 203, /* VFMADDSUB231PDZ128mk */ }, { /* 5423 */ 203, /* VFMADDSUB231PDZ128mkz */ }, { /* 5424 */ 530, /* VFMADDSUB231PDZ128r */ }, { /* 5425 */ 212, /* VFMADDSUB231PDZ128rk */ }, { /* 5426 */ 212, /* VFMADDSUB231PDZ128rkz */ }, { /* 5427 */ 531, /* VFMADDSUB231PDZ256m */ }, { /* 5428 */ 532, /* VFMADDSUB231PDZ256mb */ }, { /* 5429 */ 216, /* VFMADDSUB231PDZ256mbk */ }, { /* 5430 */ 216, /* VFMADDSUB231PDZ256mbkz */ }, { /* 5431 */ 218, /* VFMADDSUB231PDZ256mk */ }, { /* 5432 */ 218, /* VFMADDSUB231PDZ256mkz */ }, { /* 5433 */ 533, /* VFMADDSUB231PDZ256r */ }, { /* 5434 */ 221, /* VFMADDSUB231PDZ256rk */ }, { /* 5435 */ 221, /* VFMADDSUB231PDZ256rkz */ }, { /* 5436 */ 534, /* VFMADDSUB231PDZm */ }, { /* 5437 */ 535, /* VFMADDSUB231PDZmb */ }, { /* 5438 */ 225, /* VFMADDSUB231PDZmbk */ }, { /* 5439 */ 225, /* VFMADDSUB231PDZmbkz */ }, { /* 5440 */ 227, /* VFMADDSUB231PDZmk */ }, { /* 5441 */ 227, /* VFMADDSUB231PDZmkz */ }, { /* 5442 */ 536, /* VFMADDSUB231PDZr */ }, { /* 5443 */ 537, /* VFMADDSUB231PDZrb */ }, { /* 5444 */ 231, /* VFMADDSUB231PDZrbk */ }, { /* 5445 */ 231, /* VFMADDSUB231PDZrbkz */ }, { /* 5446 */ 233, /* VFMADDSUB231PDZrk */ }, { /* 5447 */ 233, /* VFMADDSUB231PDZrkz */ }, { /* 5448 */ 538, /* VFMADDSUB231PDm */ }, { /* 5449 */ 539, /* VFMADDSUB231PDr */ }, { /* 5450 */ 527, /* VFMADDSUB231PSYm */ }, { /* 5451 */ 528, /* VFMADDSUB231PSYr */ }, { /* 5452 */ 202, /* VFMADDSUB231PSZ128m */ }, { /* 5453 */ 540, /* VFMADDSUB231PSZ128mb */ }, { /* 5454 */ 238, /* VFMADDSUB231PSZ128mbk */ }, { /* 5455 */ 238, /* VFMADDSUB231PSZ128mbkz */ }, { /* 5456 */ 203, /* VFMADDSUB231PSZ128mk */ }, { /* 5457 */ 203, /* VFMADDSUB231PSZ128mkz */ }, { /* 5458 */ 530, /* VFMADDSUB231PSZ128r */ }, { /* 5459 */ 212, /* VFMADDSUB231PSZ128rk */ }, { /* 5460 */ 212, /* VFMADDSUB231PSZ128rkz */ }, { /* 5461 */ 531, /* VFMADDSUB231PSZ256m */ }, { /* 5462 */ 541, /* VFMADDSUB231PSZ256mb */ }, { /* 5463 */ 241, /* VFMADDSUB231PSZ256mbk */ }, { /* 5464 */ 241, /* VFMADDSUB231PSZ256mbkz */ }, { /* 5465 */ 218, /* VFMADDSUB231PSZ256mk */ }, { /* 5466 */ 218, /* VFMADDSUB231PSZ256mkz */ }, { /* 5467 */ 533, /* VFMADDSUB231PSZ256r */ }, { /* 5468 */ 221, /* VFMADDSUB231PSZ256rk */ }, { /* 5469 */ 221, /* VFMADDSUB231PSZ256rkz */ }, { /* 5470 */ 534, /* VFMADDSUB231PSZm */ }, { /* 5471 */ 542, /* VFMADDSUB231PSZmb */ }, { /* 5472 */ 244, /* VFMADDSUB231PSZmbk */ }, { /* 5473 */ 244, /* VFMADDSUB231PSZmbkz */ }, { /* 5474 */ 227, /* VFMADDSUB231PSZmk */ }, { /* 5475 */ 227, /* VFMADDSUB231PSZmkz */ }, { /* 5476 */ 536, /* VFMADDSUB231PSZr */ }, { /* 5477 */ 543, /* VFMADDSUB231PSZrb */ }, { /* 5478 */ 247, /* VFMADDSUB231PSZrbk */ }, { /* 5479 */ 247, /* VFMADDSUB231PSZrbkz */ }, { /* 5480 */ 233, /* VFMADDSUB231PSZrk */ }, { /* 5481 */ 233, /* VFMADDSUB231PSZrkz */ }, { /* 5482 */ 538, /* VFMADDSUB231PSm */ }, { /* 5483 */ 539, /* VFMADDSUB231PSr */ }, { /* 5484 */ 301, /* VFMADDSUBPD4Ymr */ }, { /* 5485 */ 548, /* VFMADDSUBPD4Yrm */ }, { /* 5486 */ 549, /* VFMADDSUBPD4Yrr */ }, { /* 5487 */ 302, /* VFMADDSUBPD4Yrr_REV */ }, { /* 5488 */ 303, /* VFMADDSUBPD4mr */ }, { /* 5489 */ 550, /* VFMADDSUBPD4rm */ }, { /* 5490 */ 551, /* VFMADDSUBPD4rr */ }, { /* 5491 */ 304, /* VFMADDSUBPD4rr_REV */ }, { /* 5492 */ 301, /* VFMADDSUBPS4Ymr */ }, { /* 5493 */ 548, /* VFMADDSUBPS4Yrm */ }, { /* 5494 */ 549, /* VFMADDSUBPS4Yrr */ }, { /* 5495 */ 302, /* VFMADDSUBPS4Yrr_REV */ }, { /* 5496 */ 303, /* VFMADDSUBPS4mr */ }, { /* 5497 */ 550, /* VFMADDSUBPS4rm */ }, { /* 5498 */ 551, /* VFMADDSUBPS4rr */ }, { /* 5499 */ 304, /* VFMADDSUBPS4rr_REV */ }, { /* 5500 */ 527, /* VFMSUB132PDYm */ }, { /* 5501 */ 528, /* VFMSUB132PDYr */ }, { /* 5502 */ 202, /* VFMSUB132PDZ128m */ }, { /* 5503 */ 529, /* VFMSUB132PDZ128mb */ }, { /* 5504 */ 208, /* VFMSUB132PDZ128mbk */ }, { /* 5505 */ 208, /* VFMSUB132PDZ128mbkz */ }, { /* 5506 */ 203, /* VFMSUB132PDZ128mk */ }, { /* 5507 */ 203, /* VFMSUB132PDZ128mkz */ }, { /* 5508 */ 530, /* VFMSUB132PDZ128r */ }, { /* 5509 */ 212, /* VFMSUB132PDZ128rk */ }, { /* 5510 */ 212, /* VFMSUB132PDZ128rkz */ }, { /* 5511 */ 531, /* VFMSUB132PDZ256m */ }, { /* 5512 */ 532, /* VFMSUB132PDZ256mb */ }, { /* 5513 */ 216, /* VFMSUB132PDZ256mbk */ }, { /* 5514 */ 216, /* VFMSUB132PDZ256mbkz */ }, { /* 5515 */ 218, /* VFMSUB132PDZ256mk */ }, { /* 5516 */ 218, /* VFMSUB132PDZ256mkz */ }, { /* 5517 */ 533, /* VFMSUB132PDZ256r */ }, { /* 5518 */ 221, /* VFMSUB132PDZ256rk */ }, { /* 5519 */ 221, /* VFMSUB132PDZ256rkz */ }, { /* 5520 */ 534, /* VFMSUB132PDZm */ }, { /* 5521 */ 535, /* VFMSUB132PDZmb */ }, { /* 5522 */ 225, /* VFMSUB132PDZmbk */ }, { /* 5523 */ 225, /* VFMSUB132PDZmbkz */ }, { /* 5524 */ 227, /* VFMSUB132PDZmk */ }, { /* 5525 */ 227, /* VFMSUB132PDZmkz */ }, { /* 5526 */ 536, /* VFMSUB132PDZr */ }, { /* 5527 */ 537, /* VFMSUB132PDZrb */ }, { /* 5528 */ 231, /* VFMSUB132PDZrbk */ }, { /* 5529 */ 231, /* VFMSUB132PDZrbkz */ }, { /* 5530 */ 233, /* VFMSUB132PDZrk */ }, { /* 5531 */ 233, /* VFMSUB132PDZrkz */ }, { /* 5532 */ 538, /* VFMSUB132PDm */ }, { /* 5533 */ 539, /* VFMSUB132PDr */ }, { /* 5534 */ 527, /* VFMSUB132PSYm */ }, { /* 5535 */ 528, /* VFMSUB132PSYr */ }, { /* 5536 */ 202, /* VFMSUB132PSZ128m */ }, { /* 5537 */ 540, /* VFMSUB132PSZ128mb */ }, { /* 5538 */ 238, /* VFMSUB132PSZ128mbk */ }, { /* 5539 */ 238, /* VFMSUB132PSZ128mbkz */ }, { /* 5540 */ 203, /* VFMSUB132PSZ128mk */ }, { /* 5541 */ 203, /* VFMSUB132PSZ128mkz */ }, { /* 5542 */ 530, /* VFMSUB132PSZ128r */ }, { /* 5543 */ 212, /* VFMSUB132PSZ128rk */ }, { /* 5544 */ 212, /* VFMSUB132PSZ128rkz */ }, { /* 5545 */ 531, /* VFMSUB132PSZ256m */ }, { /* 5546 */ 541, /* VFMSUB132PSZ256mb */ }, { /* 5547 */ 241, /* VFMSUB132PSZ256mbk */ }, { /* 5548 */ 241, /* VFMSUB132PSZ256mbkz */ }, { /* 5549 */ 218, /* VFMSUB132PSZ256mk */ }, { /* 5550 */ 218, /* VFMSUB132PSZ256mkz */ }, { /* 5551 */ 533, /* VFMSUB132PSZ256r */ }, { /* 5552 */ 221, /* VFMSUB132PSZ256rk */ }, { /* 5553 */ 221, /* VFMSUB132PSZ256rkz */ }, { /* 5554 */ 534, /* VFMSUB132PSZm */ }, { /* 5555 */ 542, /* VFMSUB132PSZmb */ }, { /* 5556 */ 244, /* VFMSUB132PSZmbk */ }, { /* 5557 */ 244, /* VFMSUB132PSZmbkz */ }, { /* 5558 */ 227, /* VFMSUB132PSZmk */ }, { /* 5559 */ 227, /* VFMSUB132PSZmkz */ }, { /* 5560 */ 536, /* VFMSUB132PSZr */ }, { /* 5561 */ 543, /* VFMSUB132PSZrb */ }, { /* 5562 */ 247, /* VFMSUB132PSZrbk */ }, { /* 5563 */ 247, /* VFMSUB132PSZrbkz */ }, { /* 5564 */ 233, /* VFMSUB132PSZrk */ }, { /* 5565 */ 233, /* VFMSUB132PSZrkz */ }, { /* 5566 */ 538, /* VFMSUB132PSm */ }, { /* 5567 */ 539, /* VFMSUB132PSr */ }, { /* 5568 */ 0, /* */ }, { /* 5569 */ 529, /* VFMSUB132SDZm_Int */ }, { /* 5570 */ 208, /* VFMSUB132SDZm_Intk */ }, { /* 5571 */ 208, /* VFMSUB132SDZm_Intkz */ }, { /* 5572 */ 0, /* */ }, { /* 5573 */ 544, /* VFMSUB132SDZr_Int */ }, { /* 5574 */ 250, /* VFMSUB132SDZr_Intk */ }, { /* 5575 */ 250, /* VFMSUB132SDZr_Intkz */ }, { /* 5576 */ 0, /* */ }, { /* 5577 */ 545, /* VFMSUB132SDZrb_Int */ }, { /* 5578 */ 253, /* VFMSUB132SDZrb_Intk */ }, { /* 5579 */ 253, /* VFMSUB132SDZrb_Intkz */ }, { /* 5580 */ 538, /* VFMSUB132SDm */ }, { /* 5581 */ 0, /* */ }, { /* 5582 */ 539, /* VFMSUB132SDr */ }, { /* 5583 */ 0, /* */ }, { /* 5584 */ 0, /* */ }, { /* 5585 */ 540, /* VFMSUB132SSZm_Int */ }, { /* 5586 */ 238, /* VFMSUB132SSZm_Intk */ }, { /* 5587 */ 238, /* VFMSUB132SSZm_Intkz */ }, { /* 5588 */ 0, /* */ }, { /* 5589 */ 546, /* VFMSUB132SSZr_Int */ }, { /* 5590 */ 256, /* VFMSUB132SSZr_Intk */ }, { /* 5591 */ 256, /* VFMSUB132SSZr_Intkz */ }, { /* 5592 */ 0, /* */ }, { /* 5593 */ 547, /* VFMSUB132SSZrb_Int */ }, { /* 5594 */ 259, /* VFMSUB132SSZrb_Intk */ }, { /* 5595 */ 259, /* VFMSUB132SSZrb_Intkz */ }, { /* 5596 */ 538, /* VFMSUB132SSm */ }, { /* 5597 */ 0, /* */ }, { /* 5598 */ 539, /* VFMSUB132SSr */ }, { /* 5599 */ 0, /* */ }, { /* 5600 */ 527, /* VFMSUB213PDYm */ }, { /* 5601 */ 528, /* VFMSUB213PDYr */ }, { /* 5602 */ 202, /* VFMSUB213PDZ128m */ }, { /* 5603 */ 529, /* VFMSUB213PDZ128mb */ }, { /* 5604 */ 208, /* VFMSUB213PDZ128mbk */ }, { /* 5605 */ 208, /* VFMSUB213PDZ128mbkz */ }, { /* 5606 */ 203, /* VFMSUB213PDZ128mk */ }, { /* 5607 */ 203, /* VFMSUB213PDZ128mkz */ }, { /* 5608 */ 530, /* VFMSUB213PDZ128r */ }, { /* 5609 */ 212, /* VFMSUB213PDZ128rk */ }, { /* 5610 */ 212, /* VFMSUB213PDZ128rkz */ }, { /* 5611 */ 531, /* VFMSUB213PDZ256m */ }, { /* 5612 */ 532, /* VFMSUB213PDZ256mb */ }, { /* 5613 */ 216, /* VFMSUB213PDZ256mbk */ }, { /* 5614 */ 216, /* VFMSUB213PDZ256mbkz */ }, { /* 5615 */ 218, /* VFMSUB213PDZ256mk */ }, { /* 5616 */ 218, /* VFMSUB213PDZ256mkz */ }, { /* 5617 */ 533, /* VFMSUB213PDZ256r */ }, { /* 5618 */ 221, /* VFMSUB213PDZ256rk */ }, { /* 5619 */ 221, /* VFMSUB213PDZ256rkz */ }, { /* 5620 */ 534, /* VFMSUB213PDZm */ }, { /* 5621 */ 535, /* VFMSUB213PDZmb */ }, { /* 5622 */ 225, /* VFMSUB213PDZmbk */ }, { /* 5623 */ 225, /* VFMSUB213PDZmbkz */ }, { /* 5624 */ 227, /* VFMSUB213PDZmk */ }, { /* 5625 */ 227, /* VFMSUB213PDZmkz */ }, { /* 5626 */ 536, /* VFMSUB213PDZr */ }, { /* 5627 */ 537, /* VFMSUB213PDZrb */ }, { /* 5628 */ 231, /* VFMSUB213PDZrbk */ }, { /* 5629 */ 231, /* VFMSUB213PDZrbkz */ }, { /* 5630 */ 233, /* VFMSUB213PDZrk */ }, { /* 5631 */ 233, /* VFMSUB213PDZrkz */ }, { /* 5632 */ 538, /* VFMSUB213PDm */ }, { /* 5633 */ 539, /* VFMSUB213PDr */ }, { /* 5634 */ 527, /* VFMSUB213PSYm */ }, { /* 5635 */ 528, /* VFMSUB213PSYr */ }, { /* 5636 */ 202, /* VFMSUB213PSZ128m */ }, { /* 5637 */ 540, /* VFMSUB213PSZ128mb */ }, { /* 5638 */ 238, /* VFMSUB213PSZ128mbk */ }, { /* 5639 */ 238, /* VFMSUB213PSZ128mbkz */ }, { /* 5640 */ 203, /* VFMSUB213PSZ128mk */ }, { /* 5641 */ 203, /* VFMSUB213PSZ128mkz */ }, { /* 5642 */ 530, /* VFMSUB213PSZ128r */ }, { /* 5643 */ 212, /* VFMSUB213PSZ128rk */ }, { /* 5644 */ 212, /* VFMSUB213PSZ128rkz */ }, { /* 5645 */ 531, /* VFMSUB213PSZ256m */ }, { /* 5646 */ 541, /* VFMSUB213PSZ256mb */ }, { /* 5647 */ 241, /* VFMSUB213PSZ256mbk */ }, { /* 5648 */ 241, /* VFMSUB213PSZ256mbkz */ }, { /* 5649 */ 218, /* VFMSUB213PSZ256mk */ }, { /* 5650 */ 218, /* VFMSUB213PSZ256mkz */ }, { /* 5651 */ 533, /* VFMSUB213PSZ256r */ }, { /* 5652 */ 221, /* VFMSUB213PSZ256rk */ }, { /* 5653 */ 221, /* VFMSUB213PSZ256rkz */ }, { /* 5654 */ 534, /* VFMSUB213PSZm */ }, { /* 5655 */ 542, /* VFMSUB213PSZmb */ }, { /* 5656 */ 244, /* VFMSUB213PSZmbk */ }, { /* 5657 */ 244, /* VFMSUB213PSZmbkz */ }, { /* 5658 */ 227, /* VFMSUB213PSZmk */ }, { /* 5659 */ 227, /* VFMSUB213PSZmkz */ }, { /* 5660 */ 536, /* VFMSUB213PSZr */ }, { /* 5661 */ 543, /* VFMSUB213PSZrb */ }, { /* 5662 */ 247, /* VFMSUB213PSZrbk */ }, { /* 5663 */ 247, /* VFMSUB213PSZrbkz */ }, { /* 5664 */ 233, /* VFMSUB213PSZrk */ }, { /* 5665 */ 233, /* VFMSUB213PSZrkz */ }, { /* 5666 */ 538, /* VFMSUB213PSm */ }, { /* 5667 */ 539, /* VFMSUB213PSr */ }, { /* 5668 */ 0, /* */ }, { /* 5669 */ 529, /* VFMSUB213SDZm_Int */ }, { /* 5670 */ 208, /* VFMSUB213SDZm_Intk */ }, { /* 5671 */ 208, /* VFMSUB213SDZm_Intkz */ }, { /* 5672 */ 0, /* */ }, { /* 5673 */ 544, /* VFMSUB213SDZr_Int */ }, { /* 5674 */ 250, /* VFMSUB213SDZr_Intk */ }, { /* 5675 */ 250, /* VFMSUB213SDZr_Intkz */ }, { /* 5676 */ 0, /* */ }, { /* 5677 */ 545, /* VFMSUB213SDZrb_Int */ }, { /* 5678 */ 253, /* VFMSUB213SDZrb_Intk */ }, { /* 5679 */ 253, /* VFMSUB213SDZrb_Intkz */ }, { /* 5680 */ 538, /* VFMSUB213SDm */ }, { /* 5681 */ 0, /* */ }, { /* 5682 */ 539, /* VFMSUB213SDr */ }, { /* 5683 */ 0, /* */ }, { /* 5684 */ 0, /* */ }, { /* 5685 */ 540, /* VFMSUB213SSZm_Int */ }, { /* 5686 */ 238, /* VFMSUB213SSZm_Intk */ }, { /* 5687 */ 238, /* VFMSUB213SSZm_Intkz */ }, { /* 5688 */ 0, /* */ }, { /* 5689 */ 546, /* VFMSUB213SSZr_Int */ }, { /* 5690 */ 256, /* VFMSUB213SSZr_Intk */ }, { /* 5691 */ 256, /* VFMSUB213SSZr_Intkz */ }, { /* 5692 */ 0, /* */ }, { /* 5693 */ 547, /* VFMSUB213SSZrb_Int */ }, { /* 5694 */ 259, /* VFMSUB213SSZrb_Intk */ }, { /* 5695 */ 259, /* VFMSUB213SSZrb_Intkz */ }, { /* 5696 */ 538, /* VFMSUB213SSm */ }, { /* 5697 */ 0, /* */ }, { /* 5698 */ 539, /* VFMSUB213SSr */ }, { /* 5699 */ 0, /* */ }, { /* 5700 */ 527, /* VFMSUB231PDYm */ }, { /* 5701 */ 528, /* VFMSUB231PDYr */ }, { /* 5702 */ 202, /* VFMSUB231PDZ128m */ }, { /* 5703 */ 529, /* VFMSUB231PDZ128mb */ }, { /* 5704 */ 208, /* VFMSUB231PDZ128mbk */ }, { /* 5705 */ 208, /* VFMSUB231PDZ128mbkz */ }, { /* 5706 */ 203, /* VFMSUB231PDZ128mk */ }, { /* 5707 */ 203, /* VFMSUB231PDZ128mkz */ }, { /* 5708 */ 530, /* VFMSUB231PDZ128r */ }, { /* 5709 */ 212, /* VFMSUB231PDZ128rk */ }, { /* 5710 */ 212, /* VFMSUB231PDZ128rkz */ }, { /* 5711 */ 531, /* VFMSUB231PDZ256m */ }, { /* 5712 */ 532, /* VFMSUB231PDZ256mb */ }, { /* 5713 */ 216, /* VFMSUB231PDZ256mbk */ }, { /* 5714 */ 216, /* VFMSUB231PDZ256mbkz */ }, { /* 5715 */ 218, /* VFMSUB231PDZ256mk */ }, { /* 5716 */ 218, /* VFMSUB231PDZ256mkz */ }, { /* 5717 */ 533, /* VFMSUB231PDZ256r */ }, { /* 5718 */ 221, /* VFMSUB231PDZ256rk */ }, { /* 5719 */ 221, /* VFMSUB231PDZ256rkz */ }, { /* 5720 */ 534, /* VFMSUB231PDZm */ }, { /* 5721 */ 535, /* VFMSUB231PDZmb */ }, { /* 5722 */ 225, /* VFMSUB231PDZmbk */ }, { /* 5723 */ 225, /* VFMSUB231PDZmbkz */ }, { /* 5724 */ 227, /* VFMSUB231PDZmk */ }, { /* 5725 */ 227, /* VFMSUB231PDZmkz */ }, { /* 5726 */ 536, /* VFMSUB231PDZr */ }, { /* 5727 */ 537, /* VFMSUB231PDZrb */ }, { /* 5728 */ 231, /* VFMSUB231PDZrbk */ }, { /* 5729 */ 231, /* VFMSUB231PDZrbkz */ }, { /* 5730 */ 233, /* VFMSUB231PDZrk */ }, { /* 5731 */ 233, /* VFMSUB231PDZrkz */ }, { /* 5732 */ 538, /* VFMSUB231PDm */ }, { /* 5733 */ 539, /* VFMSUB231PDr */ }, { /* 5734 */ 527, /* VFMSUB231PSYm */ }, { /* 5735 */ 528, /* VFMSUB231PSYr */ }, { /* 5736 */ 202, /* VFMSUB231PSZ128m */ }, { /* 5737 */ 540, /* VFMSUB231PSZ128mb */ }, { /* 5738 */ 238, /* VFMSUB231PSZ128mbk */ }, { /* 5739 */ 238, /* VFMSUB231PSZ128mbkz */ }, { /* 5740 */ 203, /* VFMSUB231PSZ128mk */ }, { /* 5741 */ 203, /* VFMSUB231PSZ128mkz */ }, { /* 5742 */ 530, /* VFMSUB231PSZ128r */ }, { /* 5743 */ 212, /* VFMSUB231PSZ128rk */ }, { /* 5744 */ 212, /* VFMSUB231PSZ128rkz */ }, { /* 5745 */ 531, /* VFMSUB231PSZ256m */ }, { /* 5746 */ 541, /* VFMSUB231PSZ256mb */ }, { /* 5747 */ 241, /* VFMSUB231PSZ256mbk */ }, { /* 5748 */ 241, /* VFMSUB231PSZ256mbkz */ }, { /* 5749 */ 218, /* VFMSUB231PSZ256mk */ }, { /* 5750 */ 218, /* VFMSUB231PSZ256mkz */ }, { /* 5751 */ 533, /* VFMSUB231PSZ256r */ }, { /* 5752 */ 221, /* VFMSUB231PSZ256rk */ }, { /* 5753 */ 221, /* VFMSUB231PSZ256rkz */ }, { /* 5754 */ 534, /* VFMSUB231PSZm */ }, { /* 5755 */ 542, /* VFMSUB231PSZmb */ }, { /* 5756 */ 244, /* VFMSUB231PSZmbk */ }, { /* 5757 */ 244, /* VFMSUB231PSZmbkz */ }, { /* 5758 */ 227, /* VFMSUB231PSZmk */ }, { /* 5759 */ 227, /* VFMSUB231PSZmkz */ }, { /* 5760 */ 536, /* VFMSUB231PSZr */ }, { /* 5761 */ 543, /* VFMSUB231PSZrb */ }, { /* 5762 */ 247, /* VFMSUB231PSZrbk */ }, { /* 5763 */ 247, /* VFMSUB231PSZrbkz */ }, { /* 5764 */ 233, /* VFMSUB231PSZrk */ }, { /* 5765 */ 233, /* VFMSUB231PSZrkz */ }, { /* 5766 */ 538, /* VFMSUB231PSm */ }, { /* 5767 */ 539, /* VFMSUB231PSr */ }, { /* 5768 */ 0, /* */ }, { /* 5769 */ 529, /* VFMSUB231SDZm_Int */ }, { /* 5770 */ 208, /* VFMSUB231SDZm_Intk */ }, { /* 5771 */ 208, /* VFMSUB231SDZm_Intkz */ }, { /* 5772 */ 0, /* */ }, { /* 5773 */ 544, /* VFMSUB231SDZr_Int */ }, { /* 5774 */ 250, /* VFMSUB231SDZr_Intk */ }, { /* 5775 */ 250, /* VFMSUB231SDZr_Intkz */ }, { /* 5776 */ 0, /* */ }, { /* 5777 */ 545, /* VFMSUB231SDZrb_Int */ }, { /* 5778 */ 253, /* VFMSUB231SDZrb_Intk */ }, { /* 5779 */ 253, /* VFMSUB231SDZrb_Intkz */ }, { /* 5780 */ 538, /* VFMSUB231SDm */ }, { /* 5781 */ 0, /* */ }, { /* 5782 */ 539, /* VFMSUB231SDr */ }, { /* 5783 */ 0, /* */ }, { /* 5784 */ 0, /* */ }, { /* 5785 */ 540, /* VFMSUB231SSZm_Int */ }, { /* 5786 */ 238, /* VFMSUB231SSZm_Intk */ }, { /* 5787 */ 238, /* VFMSUB231SSZm_Intkz */ }, { /* 5788 */ 0, /* */ }, { /* 5789 */ 546, /* VFMSUB231SSZr_Int */ }, { /* 5790 */ 256, /* VFMSUB231SSZr_Intk */ }, { /* 5791 */ 256, /* VFMSUB231SSZr_Intkz */ }, { /* 5792 */ 0, /* */ }, { /* 5793 */ 547, /* VFMSUB231SSZrb_Int */ }, { /* 5794 */ 259, /* VFMSUB231SSZrb_Intk */ }, { /* 5795 */ 259, /* VFMSUB231SSZrb_Intkz */ }, { /* 5796 */ 538, /* VFMSUB231SSm */ }, { /* 5797 */ 0, /* */ }, { /* 5798 */ 539, /* VFMSUB231SSr */ }, { /* 5799 */ 0, /* */ }, { /* 5800 */ 527, /* VFMSUBADD132PDYm */ }, { /* 5801 */ 528, /* VFMSUBADD132PDYr */ }, { /* 5802 */ 202, /* VFMSUBADD132PDZ128m */ }, { /* 5803 */ 529, /* VFMSUBADD132PDZ128mb */ }, { /* 5804 */ 208, /* VFMSUBADD132PDZ128mbk */ }, { /* 5805 */ 208, /* VFMSUBADD132PDZ128mbkz */ }, { /* 5806 */ 203, /* VFMSUBADD132PDZ128mk */ }, { /* 5807 */ 203, /* VFMSUBADD132PDZ128mkz */ }, { /* 5808 */ 530, /* VFMSUBADD132PDZ128r */ }, { /* 5809 */ 212, /* VFMSUBADD132PDZ128rk */ }, { /* 5810 */ 212, /* VFMSUBADD132PDZ128rkz */ }, { /* 5811 */ 531, /* VFMSUBADD132PDZ256m */ }, { /* 5812 */ 532, /* VFMSUBADD132PDZ256mb */ }, { /* 5813 */ 216, /* VFMSUBADD132PDZ256mbk */ }, { /* 5814 */ 216, /* VFMSUBADD132PDZ256mbkz */ }, { /* 5815 */ 218, /* VFMSUBADD132PDZ256mk */ }, { /* 5816 */ 218, /* VFMSUBADD132PDZ256mkz */ }, { /* 5817 */ 533, /* VFMSUBADD132PDZ256r */ }, { /* 5818 */ 221, /* VFMSUBADD132PDZ256rk */ }, { /* 5819 */ 221, /* VFMSUBADD132PDZ256rkz */ }, { /* 5820 */ 534, /* VFMSUBADD132PDZm */ }, { /* 5821 */ 535, /* VFMSUBADD132PDZmb */ }, { /* 5822 */ 225, /* VFMSUBADD132PDZmbk */ }, { /* 5823 */ 225, /* VFMSUBADD132PDZmbkz */ }, { /* 5824 */ 227, /* VFMSUBADD132PDZmk */ }, { /* 5825 */ 227, /* VFMSUBADD132PDZmkz */ }, { /* 5826 */ 536, /* VFMSUBADD132PDZr */ }, { /* 5827 */ 537, /* VFMSUBADD132PDZrb */ }, { /* 5828 */ 231, /* VFMSUBADD132PDZrbk */ }, { /* 5829 */ 231, /* VFMSUBADD132PDZrbkz */ }, { /* 5830 */ 233, /* VFMSUBADD132PDZrk */ }, { /* 5831 */ 233, /* VFMSUBADD132PDZrkz */ }, { /* 5832 */ 538, /* VFMSUBADD132PDm */ }, { /* 5833 */ 539, /* VFMSUBADD132PDr */ }, { /* 5834 */ 527, /* VFMSUBADD132PSYm */ }, { /* 5835 */ 528, /* VFMSUBADD132PSYr */ }, { /* 5836 */ 202, /* VFMSUBADD132PSZ128m */ }, { /* 5837 */ 540, /* VFMSUBADD132PSZ128mb */ }, { /* 5838 */ 238, /* VFMSUBADD132PSZ128mbk */ }, { /* 5839 */ 238, /* VFMSUBADD132PSZ128mbkz */ }, { /* 5840 */ 203, /* VFMSUBADD132PSZ128mk */ }, { /* 5841 */ 203, /* VFMSUBADD132PSZ128mkz */ }, { /* 5842 */ 530, /* VFMSUBADD132PSZ128r */ }, { /* 5843 */ 212, /* VFMSUBADD132PSZ128rk */ }, { /* 5844 */ 212, /* VFMSUBADD132PSZ128rkz */ }, { /* 5845 */ 531, /* VFMSUBADD132PSZ256m */ }, { /* 5846 */ 541, /* VFMSUBADD132PSZ256mb */ }, { /* 5847 */ 241, /* VFMSUBADD132PSZ256mbk */ }, { /* 5848 */ 241, /* VFMSUBADD132PSZ256mbkz */ }, { /* 5849 */ 218, /* VFMSUBADD132PSZ256mk */ }, { /* 5850 */ 218, /* VFMSUBADD132PSZ256mkz */ }, { /* 5851 */ 533, /* VFMSUBADD132PSZ256r */ }, { /* 5852 */ 221, /* VFMSUBADD132PSZ256rk */ }, { /* 5853 */ 221, /* VFMSUBADD132PSZ256rkz */ }, { /* 5854 */ 534, /* VFMSUBADD132PSZm */ }, { /* 5855 */ 542, /* VFMSUBADD132PSZmb */ }, { /* 5856 */ 244, /* VFMSUBADD132PSZmbk */ }, { /* 5857 */ 244, /* VFMSUBADD132PSZmbkz */ }, { /* 5858 */ 227, /* VFMSUBADD132PSZmk */ }, { /* 5859 */ 227, /* VFMSUBADD132PSZmkz */ }, { /* 5860 */ 536, /* VFMSUBADD132PSZr */ }, { /* 5861 */ 543, /* VFMSUBADD132PSZrb */ }, { /* 5862 */ 247, /* VFMSUBADD132PSZrbk */ }, { /* 5863 */ 247, /* VFMSUBADD132PSZrbkz */ }, { /* 5864 */ 233, /* VFMSUBADD132PSZrk */ }, { /* 5865 */ 233, /* VFMSUBADD132PSZrkz */ }, { /* 5866 */ 538, /* VFMSUBADD132PSm */ }, { /* 5867 */ 539, /* VFMSUBADD132PSr */ }, { /* 5868 */ 527, /* VFMSUBADD213PDYm */ }, { /* 5869 */ 528, /* VFMSUBADD213PDYr */ }, { /* 5870 */ 202, /* VFMSUBADD213PDZ128m */ }, { /* 5871 */ 529, /* VFMSUBADD213PDZ128mb */ }, { /* 5872 */ 208, /* VFMSUBADD213PDZ128mbk */ }, { /* 5873 */ 208, /* VFMSUBADD213PDZ128mbkz */ }, { /* 5874 */ 203, /* VFMSUBADD213PDZ128mk */ }, { /* 5875 */ 203, /* VFMSUBADD213PDZ128mkz */ }, { /* 5876 */ 530, /* VFMSUBADD213PDZ128r */ }, { /* 5877 */ 212, /* VFMSUBADD213PDZ128rk */ }, { /* 5878 */ 212, /* VFMSUBADD213PDZ128rkz */ }, { /* 5879 */ 531, /* VFMSUBADD213PDZ256m */ }, { /* 5880 */ 532, /* VFMSUBADD213PDZ256mb */ }, { /* 5881 */ 216, /* VFMSUBADD213PDZ256mbk */ }, { /* 5882 */ 216, /* VFMSUBADD213PDZ256mbkz */ }, { /* 5883 */ 218, /* VFMSUBADD213PDZ256mk */ }, { /* 5884 */ 218, /* VFMSUBADD213PDZ256mkz */ }, { /* 5885 */ 533, /* VFMSUBADD213PDZ256r */ }, { /* 5886 */ 221, /* VFMSUBADD213PDZ256rk */ }, { /* 5887 */ 221, /* VFMSUBADD213PDZ256rkz */ }, { /* 5888 */ 534, /* VFMSUBADD213PDZm */ }, { /* 5889 */ 535, /* VFMSUBADD213PDZmb */ }, { /* 5890 */ 225, /* VFMSUBADD213PDZmbk */ }, { /* 5891 */ 225, /* VFMSUBADD213PDZmbkz */ }, { /* 5892 */ 227, /* VFMSUBADD213PDZmk */ }, { /* 5893 */ 227, /* VFMSUBADD213PDZmkz */ }, { /* 5894 */ 536, /* VFMSUBADD213PDZr */ }, { /* 5895 */ 537, /* VFMSUBADD213PDZrb */ }, { /* 5896 */ 231, /* VFMSUBADD213PDZrbk */ }, { /* 5897 */ 231, /* VFMSUBADD213PDZrbkz */ }, { /* 5898 */ 233, /* VFMSUBADD213PDZrk */ }, { /* 5899 */ 233, /* VFMSUBADD213PDZrkz */ }, { /* 5900 */ 538, /* VFMSUBADD213PDm */ }, { /* 5901 */ 539, /* VFMSUBADD213PDr */ }, { /* 5902 */ 527, /* VFMSUBADD213PSYm */ }, { /* 5903 */ 528, /* VFMSUBADD213PSYr */ }, { /* 5904 */ 202, /* VFMSUBADD213PSZ128m */ }, { /* 5905 */ 540, /* VFMSUBADD213PSZ128mb */ }, { /* 5906 */ 238, /* VFMSUBADD213PSZ128mbk */ }, { /* 5907 */ 238, /* VFMSUBADD213PSZ128mbkz */ }, { /* 5908 */ 203, /* VFMSUBADD213PSZ128mk */ }, { /* 5909 */ 203, /* VFMSUBADD213PSZ128mkz */ }, { /* 5910 */ 530, /* VFMSUBADD213PSZ128r */ }, { /* 5911 */ 212, /* VFMSUBADD213PSZ128rk */ }, { /* 5912 */ 212, /* VFMSUBADD213PSZ128rkz */ }, { /* 5913 */ 531, /* VFMSUBADD213PSZ256m */ }, { /* 5914 */ 541, /* VFMSUBADD213PSZ256mb */ }, { /* 5915 */ 241, /* VFMSUBADD213PSZ256mbk */ }, { /* 5916 */ 241, /* VFMSUBADD213PSZ256mbkz */ }, { /* 5917 */ 218, /* VFMSUBADD213PSZ256mk */ }, { /* 5918 */ 218, /* VFMSUBADD213PSZ256mkz */ }, { /* 5919 */ 533, /* VFMSUBADD213PSZ256r */ }, { /* 5920 */ 221, /* VFMSUBADD213PSZ256rk */ }, { /* 5921 */ 221, /* VFMSUBADD213PSZ256rkz */ }, { /* 5922 */ 534, /* VFMSUBADD213PSZm */ }, { /* 5923 */ 542, /* VFMSUBADD213PSZmb */ }, { /* 5924 */ 244, /* VFMSUBADD213PSZmbk */ }, { /* 5925 */ 244, /* VFMSUBADD213PSZmbkz */ }, { /* 5926 */ 227, /* VFMSUBADD213PSZmk */ }, { /* 5927 */ 227, /* VFMSUBADD213PSZmkz */ }, { /* 5928 */ 536, /* VFMSUBADD213PSZr */ }, { /* 5929 */ 543, /* VFMSUBADD213PSZrb */ }, { /* 5930 */ 247, /* VFMSUBADD213PSZrbk */ }, { /* 5931 */ 247, /* VFMSUBADD213PSZrbkz */ }, { /* 5932 */ 233, /* VFMSUBADD213PSZrk */ }, { /* 5933 */ 233, /* VFMSUBADD213PSZrkz */ }, { /* 5934 */ 538, /* VFMSUBADD213PSm */ }, { /* 5935 */ 539, /* VFMSUBADD213PSr */ }, { /* 5936 */ 527, /* VFMSUBADD231PDYm */ }, { /* 5937 */ 528, /* VFMSUBADD231PDYr */ }, { /* 5938 */ 202, /* VFMSUBADD231PDZ128m */ }, { /* 5939 */ 529, /* VFMSUBADD231PDZ128mb */ }, { /* 5940 */ 208, /* VFMSUBADD231PDZ128mbk */ }, { /* 5941 */ 208, /* VFMSUBADD231PDZ128mbkz */ }, { /* 5942 */ 203, /* VFMSUBADD231PDZ128mk */ }, { /* 5943 */ 203, /* VFMSUBADD231PDZ128mkz */ }, { /* 5944 */ 530, /* VFMSUBADD231PDZ128r */ }, { /* 5945 */ 212, /* VFMSUBADD231PDZ128rk */ }, { /* 5946 */ 212, /* VFMSUBADD231PDZ128rkz */ }, { /* 5947 */ 531, /* VFMSUBADD231PDZ256m */ }, { /* 5948 */ 532, /* VFMSUBADD231PDZ256mb */ }, { /* 5949 */ 216, /* VFMSUBADD231PDZ256mbk */ }, { /* 5950 */ 216, /* VFMSUBADD231PDZ256mbkz */ }, { /* 5951 */ 218, /* VFMSUBADD231PDZ256mk */ }, { /* 5952 */ 218, /* VFMSUBADD231PDZ256mkz */ }, { /* 5953 */ 533, /* VFMSUBADD231PDZ256r */ }, { /* 5954 */ 221, /* VFMSUBADD231PDZ256rk */ }, { /* 5955 */ 221, /* VFMSUBADD231PDZ256rkz */ }, { /* 5956 */ 534, /* VFMSUBADD231PDZm */ }, { /* 5957 */ 535, /* VFMSUBADD231PDZmb */ }, { /* 5958 */ 225, /* VFMSUBADD231PDZmbk */ }, { /* 5959 */ 225, /* VFMSUBADD231PDZmbkz */ }, { /* 5960 */ 227, /* VFMSUBADD231PDZmk */ }, { /* 5961 */ 227, /* VFMSUBADD231PDZmkz */ }, { /* 5962 */ 536, /* VFMSUBADD231PDZr */ }, { /* 5963 */ 537, /* VFMSUBADD231PDZrb */ }, { /* 5964 */ 231, /* VFMSUBADD231PDZrbk */ }, { /* 5965 */ 231, /* VFMSUBADD231PDZrbkz */ }, { /* 5966 */ 233, /* VFMSUBADD231PDZrk */ }, { /* 5967 */ 233, /* VFMSUBADD231PDZrkz */ }, { /* 5968 */ 538, /* VFMSUBADD231PDm */ }, { /* 5969 */ 539, /* VFMSUBADD231PDr */ }, { /* 5970 */ 527, /* VFMSUBADD231PSYm */ }, { /* 5971 */ 528, /* VFMSUBADD231PSYr */ }, { /* 5972 */ 202, /* VFMSUBADD231PSZ128m */ }, { /* 5973 */ 540, /* VFMSUBADD231PSZ128mb */ }, { /* 5974 */ 238, /* VFMSUBADD231PSZ128mbk */ }, { /* 5975 */ 238, /* VFMSUBADD231PSZ128mbkz */ }, { /* 5976 */ 203, /* VFMSUBADD231PSZ128mk */ }, { /* 5977 */ 203, /* VFMSUBADD231PSZ128mkz */ }, { /* 5978 */ 530, /* VFMSUBADD231PSZ128r */ }, { /* 5979 */ 212, /* VFMSUBADD231PSZ128rk */ }, { /* 5980 */ 212, /* VFMSUBADD231PSZ128rkz */ }, { /* 5981 */ 531, /* VFMSUBADD231PSZ256m */ }, { /* 5982 */ 541, /* VFMSUBADD231PSZ256mb */ }, { /* 5983 */ 241, /* VFMSUBADD231PSZ256mbk */ }, { /* 5984 */ 241, /* VFMSUBADD231PSZ256mbkz */ }, { /* 5985 */ 218, /* VFMSUBADD231PSZ256mk */ }, { /* 5986 */ 218, /* VFMSUBADD231PSZ256mkz */ }, { /* 5987 */ 533, /* VFMSUBADD231PSZ256r */ }, { /* 5988 */ 221, /* VFMSUBADD231PSZ256rk */ }, { /* 5989 */ 221, /* VFMSUBADD231PSZ256rkz */ }, { /* 5990 */ 534, /* VFMSUBADD231PSZm */ }, { /* 5991 */ 542, /* VFMSUBADD231PSZmb */ }, { /* 5992 */ 244, /* VFMSUBADD231PSZmbk */ }, { /* 5993 */ 244, /* VFMSUBADD231PSZmbkz */ }, { /* 5994 */ 227, /* VFMSUBADD231PSZmk */ }, { /* 5995 */ 227, /* VFMSUBADD231PSZmkz */ }, { /* 5996 */ 536, /* VFMSUBADD231PSZr */ }, { /* 5997 */ 543, /* VFMSUBADD231PSZrb */ }, { /* 5998 */ 247, /* VFMSUBADD231PSZrbk */ }, { /* 5999 */ 247, /* VFMSUBADD231PSZrbkz */ }, { /* 6000 */ 233, /* VFMSUBADD231PSZrk */ }, { /* 6001 */ 233, /* VFMSUBADD231PSZrkz */ }, { /* 6002 */ 538, /* VFMSUBADD231PSm */ }, { /* 6003 */ 539, /* VFMSUBADD231PSr */ }, { /* 6004 */ 301, /* VFMSUBADDPD4Ymr */ }, { /* 6005 */ 548, /* VFMSUBADDPD4Yrm */ }, { /* 6006 */ 549, /* VFMSUBADDPD4Yrr */ }, { /* 6007 */ 302, /* VFMSUBADDPD4Yrr_REV */ }, { /* 6008 */ 303, /* VFMSUBADDPD4mr */ }, { /* 6009 */ 550, /* VFMSUBADDPD4rm */ }, { /* 6010 */ 551, /* VFMSUBADDPD4rr */ }, { /* 6011 */ 304, /* VFMSUBADDPD4rr_REV */ }, { /* 6012 */ 301, /* VFMSUBADDPS4Ymr */ }, { /* 6013 */ 548, /* VFMSUBADDPS4Yrm */ }, { /* 6014 */ 549, /* VFMSUBADDPS4Yrr */ }, { /* 6015 */ 302, /* VFMSUBADDPS4Yrr_REV */ }, { /* 6016 */ 303, /* VFMSUBADDPS4mr */ }, { /* 6017 */ 550, /* VFMSUBADDPS4rm */ }, { /* 6018 */ 551, /* VFMSUBADDPS4rr */ }, { /* 6019 */ 304, /* VFMSUBADDPS4rr_REV */ }, { /* 6020 */ 301, /* VFMSUBPD4Ymr */ }, { /* 6021 */ 548, /* VFMSUBPD4Yrm */ }, { /* 6022 */ 549, /* VFMSUBPD4Yrr */ }, { /* 6023 */ 302, /* VFMSUBPD4Yrr_REV */ }, { /* 6024 */ 303, /* VFMSUBPD4mr */ }, { /* 6025 */ 550, /* VFMSUBPD4rm */ }, { /* 6026 */ 551, /* VFMSUBPD4rr */ }, { /* 6027 */ 304, /* VFMSUBPD4rr_REV */ }, { /* 6028 */ 301, /* VFMSUBPS4Ymr */ }, { /* 6029 */ 548, /* VFMSUBPS4Yrm */ }, { /* 6030 */ 549, /* VFMSUBPS4Yrr */ }, { /* 6031 */ 302, /* VFMSUBPS4Yrr_REV */ }, { /* 6032 */ 303, /* VFMSUBPS4mr */ }, { /* 6033 */ 550, /* VFMSUBPS4rm */ }, { /* 6034 */ 551, /* VFMSUBPS4rr */ }, { /* 6035 */ 304, /* VFMSUBPS4rr_REV */ }, { /* 6036 */ 303, /* VFMSUBSD4mr */ }, { /* 6037 */ 0, /* */ }, { /* 6038 */ 550, /* VFMSUBSD4rm */ }, { /* 6039 */ 0, /* */ }, { /* 6040 */ 551, /* VFMSUBSD4rr */ }, { /* 6041 */ 0, /* */ }, { /* 6042 */ 0, /* */ }, { /* 6043 */ 304, /* VFMSUBSD4rr_REV */ }, { /* 6044 */ 303, /* VFMSUBSS4mr */ }, { /* 6045 */ 0, /* */ }, { /* 6046 */ 550, /* VFMSUBSS4rm */ }, { /* 6047 */ 0, /* */ }, { /* 6048 */ 551, /* VFMSUBSS4rr */ }, { /* 6049 */ 0, /* */ }, { /* 6050 */ 0, /* */ }, { /* 6051 */ 304, /* VFMSUBSS4rr_REV */ }, { /* 6052 */ 527, /* VFNMADD132PDYm */ }, { /* 6053 */ 528, /* VFNMADD132PDYr */ }, { /* 6054 */ 202, /* VFNMADD132PDZ128m */ }, { /* 6055 */ 529, /* VFNMADD132PDZ128mb */ }, { /* 6056 */ 208, /* VFNMADD132PDZ128mbk */ }, { /* 6057 */ 208, /* VFNMADD132PDZ128mbkz */ }, { /* 6058 */ 203, /* VFNMADD132PDZ128mk */ }, { /* 6059 */ 203, /* VFNMADD132PDZ128mkz */ }, { /* 6060 */ 530, /* VFNMADD132PDZ128r */ }, { /* 6061 */ 212, /* VFNMADD132PDZ128rk */ }, { /* 6062 */ 212, /* VFNMADD132PDZ128rkz */ }, { /* 6063 */ 531, /* VFNMADD132PDZ256m */ }, { /* 6064 */ 532, /* VFNMADD132PDZ256mb */ }, { /* 6065 */ 216, /* VFNMADD132PDZ256mbk */ }, { /* 6066 */ 216, /* VFNMADD132PDZ256mbkz */ }, { /* 6067 */ 218, /* VFNMADD132PDZ256mk */ }, { /* 6068 */ 218, /* VFNMADD132PDZ256mkz */ }, { /* 6069 */ 533, /* VFNMADD132PDZ256r */ }, { /* 6070 */ 221, /* VFNMADD132PDZ256rk */ }, { /* 6071 */ 221, /* VFNMADD132PDZ256rkz */ }, { /* 6072 */ 534, /* VFNMADD132PDZm */ }, { /* 6073 */ 535, /* VFNMADD132PDZmb */ }, { /* 6074 */ 225, /* VFNMADD132PDZmbk */ }, { /* 6075 */ 225, /* VFNMADD132PDZmbkz */ }, { /* 6076 */ 227, /* VFNMADD132PDZmk */ }, { /* 6077 */ 227, /* VFNMADD132PDZmkz */ }, { /* 6078 */ 536, /* VFNMADD132PDZr */ }, { /* 6079 */ 537, /* VFNMADD132PDZrb */ }, { /* 6080 */ 231, /* VFNMADD132PDZrbk */ }, { /* 6081 */ 231, /* VFNMADD132PDZrbkz */ }, { /* 6082 */ 233, /* VFNMADD132PDZrk */ }, { /* 6083 */ 233, /* VFNMADD132PDZrkz */ }, { /* 6084 */ 538, /* VFNMADD132PDm */ }, { /* 6085 */ 539, /* VFNMADD132PDr */ }, { /* 6086 */ 527, /* VFNMADD132PSYm */ }, { /* 6087 */ 528, /* VFNMADD132PSYr */ }, { /* 6088 */ 202, /* VFNMADD132PSZ128m */ }, { /* 6089 */ 540, /* VFNMADD132PSZ128mb */ }, { /* 6090 */ 238, /* VFNMADD132PSZ128mbk */ }, { /* 6091 */ 238, /* VFNMADD132PSZ128mbkz */ }, { /* 6092 */ 203, /* VFNMADD132PSZ128mk */ }, { /* 6093 */ 203, /* VFNMADD132PSZ128mkz */ }, { /* 6094 */ 530, /* VFNMADD132PSZ128r */ }, { /* 6095 */ 212, /* VFNMADD132PSZ128rk */ }, { /* 6096 */ 212, /* VFNMADD132PSZ128rkz */ }, { /* 6097 */ 531, /* VFNMADD132PSZ256m */ }, { /* 6098 */ 541, /* VFNMADD132PSZ256mb */ }, { /* 6099 */ 241, /* VFNMADD132PSZ256mbk */ }, { /* 6100 */ 241, /* VFNMADD132PSZ256mbkz */ }, { /* 6101 */ 218, /* VFNMADD132PSZ256mk */ }, { /* 6102 */ 218, /* VFNMADD132PSZ256mkz */ }, { /* 6103 */ 533, /* VFNMADD132PSZ256r */ }, { /* 6104 */ 221, /* VFNMADD132PSZ256rk */ }, { /* 6105 */ 221, /* VFNMADD132PSZ256rkz */ }, { /* 6106 */ 534, /* VFNMADD132PSZm */ }, { /* 6107 */ 542, /* VFNMADD132PSZmb */ }, { /* 6108 */ 244, /* VFNMADD132PSZmbk */ }, { /* 6109 */ 244, /* VFNMADD132PSZmbkz */ }, { /* 6110 */ 227, /* VFNMADD132PSZmk */ }, { /* 6111 */ 227, /* VFNMADD132PSZmkz */ }, { /* 6112 */ 536, /* VFNMADD132PSZr */ }, { /* 6113 */ 543, /* VFNMADD132PSZrb */ }, { /* 6114 */ 247, /* VFNMADD132PSZrbk */ }, { /* 6115 */ 247, /* VFNMADD132PSZrbkz */ }, { /* 6116 */ 233, /* VFNMADD132PSZrk */ }, { /* 6117 */ 233, /* VFNMADD132PSZrkz */ }, { /* 6118 */ 538, /* VFNMADD132PSm */ }, { /* 6119 */ 539, /* VFNMADD132PSr */ }, { /* 6120 */ 0, /* */ }, { /* 6121 */ 529, /* VFNMADD132SDZm_Int */ }, { /* 6122 */ 208, /* VFNMADD132SDZm_Intk */ }, { /* 6123 */ 208, /* VFNMADD132SDZm_Intkz */ }, { /* 6124 */ 0, /* */ }, { /* 6125 */ 544, /* VFNMADD132SDZr_Int */ }, { /* 6126 */ 250, /* VFNMADD132SDZr_Intk */ }, { /* 6127 */ 250, /* VFNMADD132SDZr_Intkz */ }, { /* 6128 */ 0, /* */ }, { /* 6129 */ 545, /* VFNMADD132SDZrb_Int */ }, { /* 6130 */ 253, /* VFNMADD132SDZrb_Intk */ }, { /* 6131 */ 253, /* VFNMADD132SDZrb_Intkz */ }, { /* 6132 */ 538, /* VFNMADD132SDm */ }, { /* 6133 */ 0, /* */ }, { /* 6134 */ 539, /* VFNMADD132SDr */ }, { /* 6135 */ 0, /* */ }, { /* 6136 */ 0, /* */ }, { /* 6137 */ 540, /* VFNMADD132SSZm_Int */ }, { /* 6138 */ 238, /* VFNMADD132SSZm_Intk */ }, { /* 6139 */ 238, /* VFNMADD132SSZm_Intkz */ }, { /* 6140 */ 0, /* */ }, { /* 6141 */ 546, /* VFNMADD132SSZr_Int */ }, { /* 6142 */ 256, /* VFNMADD132SSZr_Intk */ }, { /* 6143 */ 256, /* VFNMADD132SSZr_Intkz */ }, { /* 6144 */ 0, /* */ }, { /* 6145 */ 547, /* VFNMADD132SSZrb_Int */ }, { /* 6146 */ 259, /* VFNMADD132SSZrb_Intk */ }, { /* 6147 */ 259, /* VFNMADD132SSZrb_Intkz */ }, { /* 6148 */ 538, /* VFNMADD132SSm */ }, { /* 6149 */ 0, /* */ }, { /* 6150 */ 539, /* VFNMADD132SSr */ }, { /* 6151 */ 0, /* */ }, { /* 6152 */ 527, /* VFNMADD213PDYm */ }, { /* 6153 */ 528, /* VFNMADD213PDYr */ }, { /* 6154 */ 202, /* VFNMADD213PDZ128m */ }, { /* 6155 */ 529, /* VFNMADD213PDZ128mb */ }, { /* 6156 */ 208, /* VFNMADD213PDZ128mbk */ }, { /* 6157 */ 208, /* VFNMADD213PDZ128mbkz */ }, { /* 6158 */ 203, /* VFNMADD213PDZ128mk */ }, { /* 6159 */ 203, /* VFNMADD213PDZ128mkz */ }, { /* 6160 */ 530, /* VFNMADD213PDZ128r */ }, { /* 6161 */ 212, /* VFNMADD213PDZ128rk */ }, { /* 6162 */ 212, /* VFNMADD213PDZ128rkz */ }, { /* 6163 */ 531, /* VFNMADD213PDZ256m */ }, { /* 6164 */ 532, /* VFNMADD213PDZ256mb */ }, { /* 6165 */ 216, /* VFNMADD213PDZ256mbk */ }, { /* 6166 */ 216, /* VFNMADD213PDZ256mbkz */ }, { /* 6167 */ 218, /* VFNMADD213PDZ256mk */ }, { /* 6168 */ 218, /* VFNMADD213PDZ256mkz */ }, { /* 6169 */ 533, /* VFNMADD213PDZ256r */ }, { /* 6170 */ 221, /* VFNMADD213PDZ256rk */ }, { /* 6171 */ 221, /* VFNMADD213PDZ256rkz */ }, { /* 6172 */ 534, /* VFNMADD213PDZm */ }, { /* 6173 */ 535, /* VFNMADD213PDZmb */ }, { /* 6174 */ 225, /* VFNMADD213PDZmbk */ }, { /* 6175 */ 225, /* VFNMADD213PDZmbkz */ }, { /* 6176 */ 227, /* VFNMADD213PDZmk */ }, { /* 6177 */ 227, /* VFNMADD213PDZmkz */ }, { /* 6178 */ 536, /* VFNMADD213PDZr */ }, { /* 6179 */ 537, /* VFNMADD213PDZrb */ }, { /* 6180 */ 231, /* VFNMADD213PDZrbk */ }, { /* 6181 */ 231, /* VFNMADD213PDZrbkz */ }, { /* 6182 */ 233, /* VFNMADD213PDZrk */ }, { /* 6183 */ 233, /* VFNMADD213PDZrkz */ }, { /* 6184 */ 538, /* VFNMADD213PDm */ }, { /* 6185 */ 539, /* VFNMADD213PDr */ }, { /* 6186 */ 527, /* VFNMADD213PSYm */ }, { /* 6187 */ 528, /* VFNMADD213PSYr */ }, { /* 6188 */ 202, /* VFNMADD213PSZ128m */ }, { /* 6189 */ 540, /* VFNMADD213PSZ128mb */ }, { /* 6190 */ 238, /* VFNMADD213PSZ128mbk */ }, { /* 6191 */ 238, /* VFNMADD213PSZ128mbkz */ }, { /* 6192 */ 203, /* VFNMADD213PSZ128mk */ }, { /* 6193 */ 203, /* VFNMADD213PSZ128mkz */ }, { /* 6194 */ 530, /* VFNMADD213PSZ128r */ }, { /* 6195 */ 212, /* VFNMADD213PSZ128rk */ }, { /* 6196 */ 212, /* VFNMADD213PSZ128rkz */ }, { /* 6197 */ 531, /* VFNMADD213PSZ256m */ }, { /* 6198 */ 541, /* VFNMADD213PSZ256mb */ }, { /* 6199 */ 241, /* VFNMADD213PSZ256mbk */ }, { /* 6200 */ 241, /* VFNMADD213PSZ256mbkz */ }, { /* 6201 */ 218, /* VFNMADD213PSZ256mk */ }, { /* 6202 */ 218, /* VFNMADD213PSZ256mkz */ }, { /* 6203 */ 533, /* VFNMADD213PSZ256r */ }, { /* 6204 */ 221, /* VFNMADD213PSZ256rk */ }, { /* 6205 */ 221, /* VFNMADD213PSZ256rkz */ }, { /* 6206 */ 534, /* VFNMADD213PSZm */ }, { /* 6207 */ 542, /* VFNMADD213PSZmb */ }, { /* 6208 */ 244, /* VFNMADD213PSZmbk */ }, { /* 6209 */ 244, /* VFNMADD213PSZmbkz */ }, { /* 6210 */ 227, /* VFNMADD213PSZmk */ }, { /* 6211 */ 227, /* VFNMADD213PSZmkz */ }, { /* 6212 */ 536, /* VFNMADD213PSZr */ }, { /* 6213 */ 543, /* VFNMADD213PSZrb */ }, { /* 6214 */ 247, /* VFNMADD213PSZrbk */ }, { /* 6215 */ 247, /* VFNMADD213PSZrbkz */ }, { /* 6216 */ 233, /* VFNMADD213PSZrk */ }, { /* 6217 */ 233, /* VFNMADD213PSZrkz */ }, { /* 6218 */ 538, /* VFNMADD213PSm */ }, { /* 6219 */ 539, /* VFNMADD213PSr */ }, { /* 6220 */ 0, /* */ }, { /* 6221 */ 529, /* VFNMADD213SDZm_Int */ }, { /* 6222 */ 208, /* VFNMADD213SDZm_Intk */ }, { /* 6223 */ 208, /* VFNMADD213SDZm_Intkz */ }, { /* 6224 */ 0, /* */ }, { /* 6225 */ 544, /* VFNMADD213SDZr_Int */ }, { /* 6226 */ 250, /* VFNMADD213SDZr_Intk */ }, { /* 6227 */ 250, /* VFNMADD213SDZr_Intkz */ }, { /* 6228 */ 0, /* */ }, { /* 6229 */ 545, /* VFNMADD213SDZrb_Int */ }, { /* 6230 */ 253, /* VFNMADD213SDZrb_Intk */ }, { /* 6231 */ 253, /* VFNMADD213SDZrb_Intkz */ }, { /* 6232 */ 538, /* VFNMADD213SDm */ }, { /* 6233 */ 0, /* */ }, { /* 6234 */ 539, /* VFNMADD213SDr */ }, { /* 6235 */ 0, /* */ }, { /* 6236 */ 0, /* */ }, { /* 6237 */ 540, /* VFNMADD213SSZm_Int */ }, { /* 6238 */ 238, /* VFNMADD213SSZm_Intk */ }, { /* 6239 */ 238, /* VFNMADD213SSZm_Intkz */ }, { /* 6240 */ 0, /* */ }, { /* 6241 */ 546, /* VFNMADD213SSZr_Int */ }, { /* 6242 */ 256, /* VFNMADD213SSZr_Intk */ }, { /* 6243 */ 256, /* VFNMADD213SSZr_Intkz */ }, { /* 6244 */ 0, /* */ }, { /* 6245 */ 547, /* VFNMADD213SSZrb_Int */ }, { /* 6246 */ 259, /* VFNMADD213SSZrb_Intk */ }, { /* 6247 */ 259, /* VFNMADD213SSZrb_Intkz */ }, { /* 6248 */ 538, /* VFNMADD213SSm */ }, { /* 6249 */ 0, /* */ }, { /* 6250 */ 539, /* VFNMADD213SSr */ }, { /* 6251 */ 0, /* */ }, { /* 6252 */ 527, /* VFNMADD231PDYm */ }, { /* 6253 */ 528, /* VFNMADD231PDYr */ }, { /* 6254 */ 202, /* VFNMADD231PDZ128m */ }, { /* 6255 */ 529, /* VFNMADD231PDZ128mb */ }, { /* 6256 */ 208, /* VFNMADD231PDZ128mbk */ }, { /* 6257 */ 208, /* VFNMADD231PDZ128mbkz */ }, { /* 6258 */ 203, /* VFNMADD231PDZ128mk */ }, { /* 6259 */ 203, /* VFNMADD231PDZ128mkz */ }, { /* 6260 */ 530, /* VFNMADD231PDZ128r */ }, { /* 6261 */ 212, /* VFNMADD231PDZ128rk */ }, { /* 6262 */ 212, /* VFNMADD231PDZ128rkz */ }, { /* 6263 */ 531, /* VFNMADD231PDZ256m */ }, { /* 6264 */ 532, /* VFNMADD231PDZ256mb */ }, { /* 6265 */ 216, /* VFNMADD231PDZ256mbk */ }, { /* 6266 */ 216, /* VFNMADD231PDZ256mbkz */ }, { /* 6267 */ 218, /* VFNMADD231PDZ256mk */ }, { /* 6268 */ 218, /* VFNMADD231PDZ256mkz */ }, { /* 6269 */ 533, /* VFNMADD231PDZ256r */ }, { /* 6270 */ 221, /* VFNMADD231PDZ256rk */ }, { /* 6271 */ 221, /* VFNMADD231PDZ256rkz */ }, { /* 6272 */ 534, /* VFNMADD231PDZm */ }, { /* 6273 */ 535, /* VFNMADD231PDZmb */ }, { /* 6274 */ 225, /* VFNMADD231PDZmbk */ }, { /* 6275 */ 225, /* VFNMADD231PDZmbkz */ }, { /* 6276 */ 227, /* VFNMADD231PDZmk */ }, { /* 6277 */ 227, /* VFNMADD231PDZmkz */ }, { /* 6278 */ 536, /* VFNMADD231PDZr */ }, { /* 6279 */ 537, /* VFNMADD231PDZrb */ }, { /* 6280 */ 231, /* VFNMADD231PDZrbk */ }, { /* 6281 */ 231, /* VFNMADD231PDZrbkz */ }, { /* 6282 */ 233, /* VFNMADD231PDZrk */ }, { /* 6283 */ 233, /* VFNMADD231PDZrkz */ }, { /* 6284 */ 538, /* VFNMADD231PDm */ }, { /* 6285 */ 539, /* VFNMADD231PDr */ }, { /* 6286 */ 527, /* VFNMADD231PSYm */ }, { /* 6287 */ 528, /* VFNMADD231PSYr */ }, { /* 6288 */ 202, /* VFNMADD231PSZ128m */ }, { /* 6289 */ 540, /* VFNMADD231PSZ128mb */ }, { /* 6290 */ 238, /* VFNMADD231PSZ128mbk */ }, { /* 6291 */ 238, /* VFNMADD231PSZ128mbkz */ }, { /* 6292 */ 203, /* VFNMADD231PSZ128mk */ }, { /* 6293 */ 203, /* VFNMADD231PSZ128mkz */ }, { /* 6294 */ 530, /* VFNMADD231PSZ128r */ }, { /* 6295 */ 212, /* VFNMADD231PSZ128rk */ }, { /* 6296 */ 212, /* VFNMADD231PSZ128rkz */ }, { /* 6297 */ 531, /* VFNMADD231PSZ256m */ }, { /* 6298 */ 541, /* VFNMADD231PSZ256mb */ }, { /* 6299 */ 241, /* VFNMADD231PSZ256mbk */ }, { /* 6300 */ 241, /* VFNMADD231PSZ256mbkz */ }, { /* 6301 */ 218, /* VFNMADD231PSZ256mk */ }, { /* 6302 */ 218, /* VFNMADD231PSZ256mkz */ }, { /* 6303 */ 533, /* VFNMADD231PSZ256r */ }, { /* 6304 */ 221, /* VFNMADD231PSZ256rk */ }, { /* 6305 */ 221, /* VFNMADD231PSZ256rkz */ }, { /* 6306 */ 534, /* VFNMADD231PSZm */ }, { /* 6307 */ 542, /* VFNMADD231PSZmb */ }, { /* 6308 */ 244, /* VFNMADD231PSZmbk */ }, { /* 6309 */ 244, /* VFNMADD231PSZmbkz */ }, { /* 6310 */ 227, /* VFNMADD231PSZmk */ }, { /* 6311 */ 227, /* VFNMADD231PSZmkz */ }, { /* 6312 */ 536, /* VFNMADD231PSZr */ }, { /* 6313 */ 543, /* VFNMADD231PSZrb */ }, { /* 6314 */ 247, /* VFNMADD231PSZrbk */ }, { /* 6315 */ 247, /* VFNMADD231PSZrbkz */ }, { /* 6316 */ 233, /* VFNMADD231PSZrk */ }, { /* 6317 */ 233, /* VFNMADD231PSZrkz */ }, { /* 6318 */ 538, /* VFNMADD231PSm */ }, { /* 6319 */ 539, /* VFNMADD231PSr */ }, { /* 6320 */ 0, /* */ }, { /* 6321 */ 529, /* VFNMADD231SDZm_Int */ }, { /* 6322 */ 208, /* VFNMADD231SDZm_Intk */ }, { /* 6323 */ 208, /* VFNMADD231SDZm_Intkz */ }, { /* 6324 */ 0, /* */ }, { /* 6325 */ 544, /* VFNMADD231SDZr_Int */ }, { /* 6326 */ 250, /* VFNMADD231SDZr_Intk */ }, { /* 6327 */ 250, /* VFNMADD231SDZr_Intkz */ }, { /* 6328 */ 0, /* */ }, { /* 6329 */ 545, /* VFNMADD231SDZrb_Int */ }, { /* 6330 */ 253, /* VFNMADD231SDZrb_Intk */ }, { /* 6331 */ 253, /* VFNMADD231SDZrb_Intkz */ }, { /* 6332 */ 538, /* VFNMADD231SDm */ }, { /* 6333 */ 0, /* */ }, { /* 6334 */ 539, /* VFNMADD231SDr */ }, { /* 6335 */ 0, /* */ }, { /* 6336 */ 0, /* */ }, { /* 6337 */ 540, /* VFNMADD231SSZm_Int */ }, { /* 6338 */ 238, /* VFNMADD231SSZm_Intk */ }, { /* 6339 */ 238, /* VFNMADD231SSZm_Intkz */ }, { /* 6340 */ 0, /* */ }, { /* 6341 */ 546, /* VFNMADD231SSZr_Int */ }, { /* 6342 */ 256, /* VFNMADD231SSZr_Intk */ }, { /* 6343 */ 256, /* VFNMADD231SSZr_Intkz */ }, { /* 6344 */ 0, /* */ }, { /* 6345 */ 547, /* VFNMADD231SSZrb_Int */ }, { /* 6346 */ 259, /* VFNMADD231SSZrb_Intk */ }, { /* 6347 */ 259, /* VFNMADD231SSZrb_Intkz */ }, { /* 6348 */ 538, /* VFNMADD231SSm */ }, { /* 6349 */ 0, /* */ }, { /* 6350 */ 539, /* VFNMADD231SSr */ }, { /* 6351 */ 0, /* */ }, { /* 6352 */ 301, /* VFNMADDPD4Ymr */ }, { /* 6353 */ 548, /* VFNMADDPD4Yrm */ }, { /* 6354 */ 549, /* VFNMADDPD4Yrr */ }, { /* 6355 */ 302, /* VFNMADDPD4Yrr_REV */ }, { /* 6356 */ 303, /* VFNMADDPD4mr */ }, { /* 6357 */ 550, /* VFNMADDPD4rm */ }, { /* 6358 */ 551, /* VFNMADDPD4rr */ }, { /* 6359 */ 304, /* VFNMADDPD4rr_REV */ }, { /* 6360 */ 301, /* VFNMADDPS4Ymr */ }, { /* 6361 */ 548, /* VFNMADDPS4Yrm */ }, { /* 6362 */ 549, /* VFNMADDPS4Yrr */ }, { /* 6363 */ 302, /* VFNMADDPS4Yrr_REV */ }, { /* 6364 */ 303, /* VFNMADDPS4mr */ }, { /* 6365 */ 550, /* VFNMADDPS4rm */ }, { /* 6366 */ 551, /* VFNMADDPS4rr */ }, { /* 6367 */ 304, /* VFNMADDPS4rr_REV */ }, { /* 6368 */ 303, /* VFNMADDSD4mr */ }, { /* 6369 */ 0, /* */ }, { /* 6370 */ 550, /* VFNMADDSD4rm */ }, { /* 6371 */ 0, /* */ }, { /* 6372 */ 551, /* VFNMADDSD4rr */ }, { /* 6373 */ 0, /* */ }, { /* 6374 */ 0, /* */ }, { /* 6375 */ 304, /* VFNMADDSD4rr_REV */ }, { /* 6376 */ 303, /* VFNMADDSS4mr */ }, { /* 6377 */ 0, /* */ }, { /* 6378 */ 550, /* VFNMADDSS4rm */ }, { /* 6379 */ 0, /* */ }, { /* 6380 */ 551, /* VFNMADDSS4rr */ }, { /* 6381 */ 0, /* */ }, { /* 6382 */ 0, /* */ }, { /* 6383 */ 304, /* VFNMADDSS4rr_REV */ }, { /* 6384 */ 527, /* VFNMSUB132PDYm */ }, { /* 6385 */ 528, /* VFNMSUB132PDYr */ }, { /* 6386 */ 202, /* VFNMSUB132PDZ128m */ }, { /* 6387 */ 529, /* VFNMSUB132PDZ128mb */ }, { /* 6388 */ 208, /* VFNMSUB132PDZ128mbk */ }, { /* 6389 */ 208, /* VFNMSUB132PDZ128mbkz */ }, { /* 6390 */ 203, /* VFNMSUB132PDZ128mk */ }, { /* 6391 */ 203, /* VFNMSUB132PDZ128mkz */ }, { /* 6392 */ 530, /* VFNMSUB132PDZ128r */ }, { /* 6393 */ 212, /* VFNMSUB132PDZ128rk */ }, { /* 6394 */ 212, /* VFNMSUB132PDZ128rkz */ }, { /* 6395 */ 531, /* VFNMSUB132PDZ256m */ }, { /* 6396 */ 532, /* VFNMSUB132PDZ256mb */ }, { /* 6397 */ 216, /* VFNMSUB132PDZ256mbk */ }, { /* 6398 */ 216, /* VFNMSUB132PDZ256mbkz */ }, { /* 6399 */ 218, /* VFNMSUB132PDZ256mk */ }, { /* 6400 */ 218, /* VFNMSUB132PDZ256mkz */ }, { /* 6401 */ 533, /* VFNMSUB132PDZ256r */ }, { /* 6402 */ 221, /* VFNMSUB132PDZ256rk */ }, { /* 6403 */ 221, /* VFNMSUB132PDZ256rkz */ }, { /* 6404 */ 534, /* VFNMSUB132PDZm */ }, { /* 6405 */ 535, /* VFNMSUB132PDZmb */ }, { /* 6406 */ 225, /* VFNMSUB132PDZmbk */ }, { /* 6407 */ 225, /* VFNMSUB132PDZmbkz */ }, { /* 6408 */ 227, /* VFNMSUB132PDZmk */ }, { /* 6409 */ 227, /* VFNMSUB132PDZmkz */ }, { /* 6410 */ 536, /* VFNMSUB132PDZr */ }, { /* 6411 */ 537, /* VFNMSUB132PDZrb */ }, { /* 6412 */ 231, /* VFNMSUB132PDZrbk */ }, { /* 6413 */ 231, /* VFNMSUB132PDZrbkz */ }, { /* 6414 */ 233, /* VFNMSUB132PDZrk */ }, { /* 6415 */ 233, /* VFNMSUB132PDZrkz */ }, { /* 6416 */ 538, /* VFNMSUB132PDm */ }, { /* 6417 */ 539, /* VFNMSUB132PDr */ }, { /* 6418 */ 527, /* VFNMSUB132PSYm */ }, { /* 6419 */ 528, /* VFNMSUB132PSYr */ }, { /* 6420 */ 202, /* VFNMSUB132PSZ128m */ }, { /* 6421 */ 540, /* VFNMSUB132PSZ128mb */ }, { /* 6422 */ 238, /* VFNMSUB132PSZ128mbk */ }, { /* 6423 */ 238, /* VFNMSUB132PSZ128mbkz */ }, { /* 6424 */ 203, /* VFNMSUB132PSZ128mk */ }, { /* 6425 */ 203, /* VFNMSUB132PSZ128mkz */ }, { /* 6426 */ 530, /* VFNMSUB132PSZ128r */ }, { /* 6427 */ 212, /* VFNMSUB132PSZ128rk */ }, { /* 6428 */ 212, /* VFNMSUB132PSZ128rkz */ }, { /* 6429 */ 531, /* VFNMSUB132PSZ256m */ }, { /* 6430 */ 541, /* VFNMSUB132PSZ256mb */ }, { /* 6431 */ 241, /* VFNMSUB132PSZ256mbk */ }, { /* 6432 */ 241, /* VFNMSUB132PSZ256mbkz */ }, { /* 6433 */ 218, /* VFNMSUB132PSZ256mk */ }, { /* 6434 */ 218, /* VFNMSUB132PSZ256mkz */ }, { /* 6435 */ 533, /* VFNMSUB132PSZ256r */ }, { /* 6436 */ 221, /* VFNMSUB132PSZ256rk */ }, { /* 6437 */ 221, /* VFNMSUB132PSZ256rkz */ }, { /* 6438 */ 534, /* VFNMSUB132PSZm */ }, { /* 6439 */ 542, /* VFNMSUB132PSZmb */ }, { /* 6440 */ 244, /* VFNMSUB132PSZmbk */ }, { /* 6441 */ 244, /* VFNMSUB132PSZmbkz */ }, { /* 6442 */ 227, /* VFNMSUB132PSZmk */ }, { /* 6443 */ 227, /* VFNMSUB132PSZmkz */ }, { /* 6444 */ 536, /* VFNMSUB132PSZr */ }, { /* 6445 */ 543, /* VFNMSUB132PSZrb */ }, { /* 6446 */ 247, /* VFNMSUB132PSZrbk */ }, { /* 6447 */ 247, /* VFNMSUB132PSZrbkz */ }, { /* 6448 */ 233, /* VFNMSUB132PSZrk */ }, { /* 6449 */ 233, /* VFNMSUB132PSZrkz */ }, { /* 6450 */ 538, /* VFNMSUB132PSm */ }, { /* 6451 */ 539, /* VFNMSUB132PSr */ }, { /* 6452 */ 0, /* */ }, { /* 6453 */ 529, /* VFNMSUB132SDZm_Int */ }, { /* 6454 */ 208, /* VFNMSUB132SDZm_Intk */ }, { /* 6455 */ 208, /* VFNMSUB132SDZm_Intkz */ }, { /* 6456 */ 0, /* */ }, { /* 6457 */ 544, /* VFNMSUB132SDZr_Int */ }, { /* 6458 */ 250, /* VFNMSUB132SDZr_Intk */ }, { /* 6459 */ 250, /* VFNMSUB132SDZr_Intkz */ }, { /* 6460 */ 0, /* */ }, { /* 6461 */ 545, /* VFNMSUB132SDZrb_Int */ }, { /* 6462 */ 253, /* VFNMSUB132SDZrb_Intk */ }, { /* 6463 */ 253, /* VFNMSUB132SDZrb_Intkz */ }, { /* 6464 */ 538, /* VFNMSUB132SDm */ }, { /* 6465 */ 0, /* */ }, { /* 6466 */ 539, /* VFNMSUB132SDr */ }, { /* 6467 */ 0, /* */ }, { /* 6468 */ 0, /* */ }, { /* 6469 */ 540, /* VFNMSUB132SSZm_Int */ }, { /* 6470 */ 238, /* VFNMSUB132SSZm_Intk */ }, { /* 6471 */ 238, /* VFNMSUB132SSZm_Intkz */ }, { /* 6472 */ 0, /* */ }, { /* 6473 */ 546, /* VFNMSUB132SSZr_Int */ }, { /* 6474 */ 256, /* VFNMSUB132SSZr_Intk */ }, { /* 6475 */ 256, /* VFNMSUB132SSZr_Intkz */ }, { /* 6476 */ 0, /* */ }, { /* 6477 */ 547, /* VFNMSUB132SSZrb_Int */ }, { /* 6478 */ 259, /* VFNMSUB132SSZrb_Intk */ }, { /* 6479 */ 259, /* VFNMSUB132SSZrb_Intkz */ }, { /* 6480 */ 538, /* VFNMSUB132SSm */ }, { /* 6481 */ 0, /* */ }, { /* 6482 */ 539, /* VFNMSUB132SSr */ }, { /* 6483 */ 0, /* */ }, { /* 6484 */ 527, /* VFNMSUB213PDYm */ }, { /* 6485 */ 528, /* VFNMSUB213PDYr */ }, { /* 6486 */ 202, /* VFNMSUB213PDZ128m */ }, { /* 6487 */ 529, /* VFNMSUB213PDZ128mb */ }, { /* 6488 */ 208, /* VFNMSUB213PDZ128mbk */ }, { /* 6489 */ 208, /* VFNMSUB213PDZ128mbkz */ }, { /* 6490 */ 203, /* VFNMSUB213PDZ128mk */ }, { /* 6491 */ 203, /* VFNMSUB213PDZ128mkz */ }, { /* 6492 */ 530, /* VFNMSUB213PDZ128r */ }, { /* 6493 */ 212, /* VFNMSUB213PDZ128rk */ }, { /* 6494 */ 212, /* VFNMSUB213PDZ128rkz */ }, { /* 6495 */ 531, /* VFNMSUB213PDZ256m */ }, { /* 6496 */ 532, /* VFNMSUB213PDZ256mb */ }, { /* 6497 */ 216, /* VFNMSUB213PDZ256mbk */ }, { /* 6498 */ 216, /* VFNMSUB213PDZ256mbkz */ }, { /* 6499 */ 218, /* VFNMSUB213PDZ256mk */ }, { /* 6500 */ 218, /* VFNMSUB213PDZ256mkz */ }, { /* 6501 */ 533, /* VFNMSUB213PDZ256r */ }, { /* 6502 */ 221, /* VFNMSUB213PDZ256rk */ }, { /* 6503 */ 221, /* VFNMSUB213PDZ256rkz */ }, { /* 6504 */ 534, /* VFNMSUB213PDZm */ }, { /* 6505 */ 535, /* VFNMSUB213PDZmb */ }, { /* 6506 */ 225, /* VFNMSUB213PDZmbk */ }, { /* 6507 */ 225, /* VFNMSUB213PDZmbkz */ }, { /* 6508 */ 227, /* VFNMSUB213PDZmk */ }, { /* 6509 */ 227, /* VFNMSUB213PDZmkz */ }, { /* 6510 */ 536, /* VFNMSUB213PDZr */ }, { /* 6511 */ 537, /* VFNMSUB213PDZrb */ }, { /* 6512 */ 231, /* VFNMSUB213PDZrbk */ }, { /* 6513 */ 231, /* VFNMSUB213PDZrbkz */ }, { /* 6514 */ 233, /* VFNMSUB213PDZrk */ }, { /* 6515 */ 233, /* VFNMSUB213PDZrkz */ }, { /* 6516 */ 538, /* VFNMSUB213PDm */ }, { /* 6517 */ 539, /* VFNMSUB213PDr */ }, { /* 6518 */ 527, /* VFNMSUB213PSYm */ }, { /* 6519 */ 528, /* VFNMSUB213PSYr */ }, { /* 6520 */ 202, /* VFNMSUB213PSZ128m */ }, { /* 6521 */ 540, /* VFNMSUB213PSZ128mb */ }, { /* 6522 */ 238, /* VFNMSUB213PSZ128mbk */ }, { /* 6523 */ 238, /* VFNMSUB213PSZ128mbkz */ }, { /* 6524 */ 203, /* VFNMSUB213PSZ128mk */ }, { /* 6525 */ 203, /* VFNMSUB213PSZ128mkz */ }, { /* 6526 */ 530, /* VFNMSUB213PSZ128r */ }, { /* 6527 */ 212, /* VFNMSUB213PSZ128rk */ }, { /* 6528 */ 212, /* VFNMSUB213PSZ128rkz */ }, { /* 6529 */ 531, /* VFNMSUB213PSZ256m */ }, { /* 6530 */ 541, /* VFNMSUB213PSZ256mb */ }, { /* 6531 */ 241, /* VFNMSUB213PSZ256mbk */ }, { /* 6532 */ 241, /* VFNMSUB213PSZ256mbkz */ }, { /* 6533 */ 218, /* VFNMSUB213PSZ256mk */ }, { /* 6534 */ 218, /* VFNMSUB213PSZ256mkz */ }, { /* 6535 */ 533, /* VFNMSUB213PSZ256r */ }, { /* 6536 */ 221, /* VFNMSUB213PSZ256rk */ }, { /* 6537 */ 221, /* VFNMSUB213PSZ256rkz */ }, { /* 6538 */ 534, /* VFNMSUB213PSZm */ }, { /* 6539 */ 542, /* VFNMSUB213PSZmb */ }, { /* 6540 */ 244, /* VFNMSUB213PSZmbk */ }, { /* 6541 */ 244, /* VFNMSUB213PSZmbkz */ }, { /* 6542 */ 227, /* VFNMSUB213PSZmk */ }, { /* 6543 */ 227, /* VFNMSUB213PSZmkz */ }, { /* 6544 */ 536, /* VFNMSUB213PSZr */ }, { /* 6545 */ 543, /* VFNMSUB213PSZrb */ }, { /* 6546 */ 247, /* VFNMSUB213PSZrbk */ }, { /* 6547 */ 247, /* VFNMSUB213PSZrbkz */ }, { /* 6548 */ 233, /* VFNMSUB213PSZrk */ }, { /* 6549 */ 233, /* VFNMSUB213PSZrkz */ }, { /* 6550 */ 538, /* VFNMSUB213PSm */ }, { /* 6551 */ 539, /* VFNMSUB213PSr */ }, { /* 6552 */ 0, /* */ }, { /* 6553 */ 529, /* VFNMSUB213SDZm_Int */ }, { /* 6554 */ 208, /* VFNMSUB213SDZm_Intk */ }, { /* 6555 */ 208, /* VFNMSUB213SDZm_Intkz */ }, { /* 6556 */ 0, /* */ }, { /* 6557 */ 544, /* VFNMSUB213SDZr_Int */ }, { /* 6558 */ 250, /* VFNMSUB213SDZr_Intk */ }, { /* 6559 */ 250, /* VFNMSUB213SDZr_Intkz */ }, { /* 6560 */ 0, /* */ }, { /* 6561 */ 545, /* VFNMSUB213SDZrb_Int */ }, { /* 6562 */ 253, /* VFNMSUB213SDZrb_Intk */ }, { /* 6563 */ 253, /* VFNMSUB213SDZrb_Intkz */ }, { /* 6564 */ 538, /* VFNMSUB213SDm */ }, { /* 6565 */ 0, /* */ }, { /* 6566 */ 539, /* VFNMSUB213SDr */ }, { /* 6567 */ 0, /* */ }, { /* 6568 */ 0, /* */ }, { /* 6569 */ 540, /* VFNMSUB213SSZm_Int */ }, { /* 6570 */ 238, /* VFNMSUB213SSZm_Intk */ }, { /* 6571 */ 238, /* VFNMSUB213SSZm_Intkz */ }, { /* 6572 */ 0, /* */ }, { /* 6573 */ 546, /* VFNMSUB213SSZr_Int */ }, { /* 6574 */ 256, /* VFNMSUB213SSZr_Intk */ }, { /* 6575 */ 256, /* VFNMSUB213SSZr_Intkz */ }, { /* 6576 */ 0, /* */ }, { /* 6577 */ 547, /* VFNMSUB213SSZrb_Int */ }, { /* 6578 */ 259, /* VFNMSUB213SSZrb_Intk */ }, { /* 6579 */ 259, /* VFNMSUB213SSZrb_Intkz */ }, { /* 6580 */ 538, /* VFNMSUB213SSm */ }, { /* 6581 */ 0, /* */ }, { /* 6582 */ 539, /* VFNMSUB213SSr */ }, { /* 6583 */ 0, /* */ }, { /* 6584 */ 527, /* VFNMSUB231PDYm */ }, { /* 6585 */ 528, /* VFNMSUB231PDYr */ }, { /* 6586 */ 202, /* VFNMSUB231PDZ128m */ }, { /* 6587 */ 529, /* VFNMSUB231PDZ128mb */ }, { /* 6588 */ 208, /* VFNMSUB231PDZ128mbk */ }, { /* 6589 */ 208, /* VFNMSUB231PDZ128mbkz */ }, { /* 6590 */ 203, /* VFNMSUB231PDZ128mk */ }, { /* 6591 */ 203, /* VFNMSUB231PDZ128mkz */ }, { /* 6592 */ 530, /* VFNMSUB231PDZ128r */ }, { /* 6593 */ 212, /* VFNMSUB231PDZ128rk */ }, { /* 6594 */ 212, /* VFNMSUB231PDZ128rkz */ }, { /* 6595 */ 531, /* VFNMSUB231PDZ256m */ }, { /* 6596 */ 532, /* VFNMSUB231PDZ256mb */ }, { /* 6597 */ 216, /* VFNMSUB231PDZ256mbk */ }, { /* 6598 */ 216, /* VFNMSUB231PDZ256mbkz */ }, { /* 6599 */ 218, /* VFNMSUB231PDZ256mk */ }, { /* 6600 */ 218, /* VFNMSUB231PDZ256mkz */ }, { /* 6601 */ 533, /* VFNMSUB231PDZ256r */ }, { /* 6602 */ 221, /* VFNMSUB231PDZ256rk */ }, { /* 6603 */ 221, /* VFNMSUB231PDZ256rkz */ }, { /* 6604 */ 534, /* VFNMSUB231PDZm */ }, { /* 6605 */ 535, /* VFNMSUB231PDZmb */ }, { /* 6606 */ 225, /* VFNMSUB231PDZmbk */ }, { /* 6607 */ 225, /* VFNMSUB231PDZmbkz */ }, { /* 6608 */ 227, /* VFNMSUB231PDZmk */ }, { /* 6609 */ 227, /* VFNMSUB231PDZmkz */ }, { /* 6610 */ 536, /* VFNMSUB231PDZr */ }, { /* 6611 */ 537, /* VFNMSUB231PDZrb */ }, { /* 6612 */ 231, /* VFNMSUB231PDZrbk */ }, { /* 6613 */ 231, /* VFNMSUB231PDZrbkz */ }, { /* 6614 */ 233, /* VFNMSUB231PDZrk */ }, { /* 6615 */ 233, /* VFNMSUB231PDZrkz */ }, { /* 6616 */ 538, /* VFNMSUB231PDm */ }, { /* 6617 */ 539, /* VFNMSUB231PDr */ }, { /* 6618 */ 527, /* VFNMSUB231PSYm */ }, { /* 6619 */ 528, /* VFNMSUB231PSYr */ }, { /* 6620 */ 202, /* VFNMSUB231PSZ128m */ }, { /* 6621 */ 540, /* VFNMSUB231PSZ128mb */ }, { /* 6622 */ 238, /* VFNMSUB231PSZ128mbk */ }, { /* 6623 */ 238, /* VFNMSUB231PSZ128mbkz */ }, { /* 6624 */ 203, /* VFNMSUB231PSZ128mk */ }, { /* 6625 */ 203, /* VFNMSUB231PSZ128mkz */ }, { /* 6626 */ 530, /* VFNMSUB231PSZ128r */ }, { /* 6627 */ 212, /* VFNMSUB231PSZ128rk */ }, { /* 6628 */ 212, /* VFNMSUB231PSZ128rkz */ }, { /* 6629 */ 531, /* VFNMSUB231PSZ256m */ }, { /* 6630 */ 541, /* VFNMSUB231PSZ256mb */ }, { /* 6631 */ 241, /* VFNMSUB231PSZ256mbk */ }, { /* 6632 */ 241, /* VFNMSUB231PSZ256mbkz */ }, { /* 6633 */ 218, /* VFNMSUB231PSZ256mk */ }, { /* 6634 */ 218, /* VFNMSUB231PSZ256mkz */ }, { /* 6635 */ 533, /* VFNMSUB231PSZ256r */ }, { /* 6636 */ 221, /* VFNMSUB231PSZ256rk */ }, { /* 6637 */ 221, /* VFNMSUB231PSZ256rkz */ }, { /* 6638 */ 534, /* VFNMSUB231PSZm */ }, { /* 6639 */ 542, /* VFNMSUB231PSZmb */ }, { /* 6640 */ 244, /* VFNMSUB231PSZmbk */ }, { /* 6641 */ 244, /* VFNMSUB231PSZmbkz */ }, { /* 6642 */ 227, /* VFNMSUB231PSZmk */ }, { /* 6643 */ 227, /* VFNMSUB231PSZmkz */ }, { /* 6644 */ 536, /* VFNMSUB231PSZr */ }, { /* 6645 */ 543, /* VFNMSUB231PSZrb */ }, { /* 6646 */ 247, /* VFNMSUB231PSZrbk */ }, { /* 6647 */ 247, /* VFNMSUB231PSZrbkz */ }, { /* 6648 */ 233, /* VFNMSUB231PSZrk */ }, { /* 6649 */ 233, /* VFNMSUB231PSZrkz */ }, { /* 6650 */ 538, /* VFNMSUB231PSm */ }, { /* 6651 */ 539, /* VFNMSUB231PSr */ }, { /* 6652 */ 0, /* */ }, { /* 6653 */ 529, /* VFNMSUB231SDZm_Int */ }, { /* 6654 */ 208, /* VFNMSUB231SDZm_Intk */ }, { /* 6655 */ 208, /* VFNMSUB231SDZm_Intkz */ }, { /* 6656 */ 0, /* */ }, { /* 6657 */ 544, /* VFNMSUB231SDZr_Int */ }, { /* 6658 */ 250, /* VFNMSUB231SDZr_Intk */ }, { /* 6659 */ 250, /* VFNMSUB231SDZr_Intkz */ }, { /* 6660 */ 0, /* */ }, { /* 6661 */ 545, /* VFNMSUB231SDZrb_Int */ }, { /* 6662 */ 253, /* VFNMSUB231SDZrb_Intk */ }, { /* 6663 */ 253, /* VFNMSUB231SDZrb_Intkz */ }, { /* 6664 */ 538, /* VFNMSUB231SDm */ }, { /* 6665 */ 0, /* */ }, { /* 6666 */ 539, /* VFNMSUB231SDr */ }, { /* 6667 */ 0, /* */ }, { /* 6668 */ 0, /* */ }, { /* 6669 */ 540, /* VFNMSUB231SSZm_Int */ }, { /* 6670 */ 238, /* VFNMSUB231SSZm_Intk */ }, { /* 6671 */ 238, /* VFNMSUB231SSZm_Intkz */ }, { /* 6672 */ 0, /* */ }, { /* 6673 */ 546, /* VFNMSUB231SSZr_Int */ }, { /* 6674 */ 256, /* VFNMSUB231SSZr_Intk */ }, { /* 6675 */ 256, /* VFNMSUB231SSZr_Intkz */ }, { /* 6676 */ 0, /* */ }, { /* 6677 */ 547, /* VFNMSUB231SSZrb_Int */ }, { /* 6678 */ 259, /* VFNMSUB231SSZrb_Intk */ }, { /* 6679 */ 259, /* VFNMSUB231SSZrb_Intkz */ }, { /* 6680 */ 538, /* VFNMSUB231SSm */ }, { /* 6681 */ 0, /* */ }, { /* 6682 */ 539, /* VFNMSUB231SSr */ }, { /* 6683 */ 0, /* */ }, { /* 6684 */ 301, /* VFNMSUBPD4Ymr */ }, { /* 6685 */ 548, /* VFNMSUBPD4Yrm */ }, { /* 6686 */ 549, /* VFNMSUBPD4Yrr */ }, { /* 6687 */ 302, /* VFNMSUBPD4Yrr_REV */ }, { /* 6688 */ 303, /* VFNMSUBPD4mr */ }, { /* 6689 */ 550, /* VFNMSUBPD4rm */ }, { /* 6690 */ 551, /* VFNMSUBPD4rr */ }, { /* 6691 */ 304, /* VFNMSUBPD4rr_REV */ }, { /* 6692 */ 301, /* VFNMSUBPS4Ymr */ }, { /* 6693 */ 548, /* VFNMSUBPS4Yrm */ }, { /* 6694 */ 549, /* VFNMSUBPS4Yrr */ }, { /* 6695 */ 302, /* VFNMSUBPS4Yrr_REV */ }, { /* 6696 */ 303, /* VFNMSUBPS4mr */ }, { /* 6697 */ 550, /* VFNMSUBPS4rm */ }, { /* 6698 */ 551, /* VFNMSUBPS4rr */ }, { /* 6699 */ 304, /* VFNMSUBPS4rr_REV */ }, { /* 6700 */ 303, /* VFNMSUBSD4mr */ }, { /* 6701 */ 0, /* */ }, { /* 6702 */ 550, /* VFNMSUBSD4rm */ }, { /* 6703 */ 0, /* */ }, { /* 6704 */ 551, /* VFNMSUBSD4rr */ }, { /* 6705 */ 0, /* */ }, { /* 6706 */ 0, /* */ }, { /* 6707 */ 304, /* VFNMSUBSD4rr_REV */ }, { /* 6708 */ 303, /* VFNMSUBSS4mr */ }, { /* 6709 */ 0, /* */ }, { /* 6710 */ 550, /* VFNMSUBSS4rm */ }, { /* 6711 */ 0, /* */ }, { /* 6712 */ 551, /* VFNMSUBSS4rr */ }, { /* 6713 */ 0, /* */ }, { /* 6714 */ 0, /* */ }, { /* 6715 */ 304, /* VFNMSUBSS4rr_REV */ }, { /* 6716 */ 552, /* VFPCLASSPDZ128rm */ }, { /* 6717 */ 553, /* VFPCLASSPDZ128rmb */ }, { /* 6718 */ 554, /* VFPCLASSPDZ128rmbk */ }, { /* 6719 */ 555, /* VFPCLASSPDZ128rmk */ }, { /* 6720 */ 556, /* VFPCLASSPDZ128rr */ }, { /* 6721 */ 557, /* VFPCLASSPDZ128rrk */ }, { /* 6722 */ 558, /* VFPCLASSPDZ256rm */ }, { /* 6723 */ 553, /* VFPCLASSPDZ256rmb */ }, { /* 6724 */ 554, /* VFPCLASSPDZ256rmbk */ }, { /* 6725 */ 559, /* VFPCLASSPDZ256rmk */ }, { /* 6726 */ 560, /* VFPCLASSPDZ256rr */ }, { /* 6727 */ 561, /* VFPCLASSPDZ256rrk */ }, { /* 6728 */ 562, /* VFPCLASSPDZrm */ }, { /* 6729 */ 553, /* VFPCLASSPDZrmb */ }, { /* 6730 */ 554, /* VFPCLASSPDZrmbk */ }, { /* 6731 */ 563, /* VFPCLASSPDZrmk */ }, { /* 6732 */ 564, /* VFPCLASSPDZrr */ }, { /* 6733 */ 565, /* VFPCLASSPDZrrk */ }, { /* 6734 */ 552, /* VFPCLASSPSZ128rm */ }, { /* 6735 */ 566, /* VFPCLASSPSZ128rmb */ }, { /* 6736 */ 567, /* VFPCLASSPSZ128rmbk */ }, { /* 6737 */ 555, /* VFPCLASSPSZ128rmk */ }, { /* 6738 */ 556, /* VFPCLASSPSZ128rr */ }, { /* 6739 */ 557, /* VFPCLASSPSZ128rrk */ }, { /* 6740 */ 558, /* VFPCLASSPSZ256rm */ }, { /* 6741 */ 566, /* VFPCLASSPSZ256rmb */ }, { /* 6742 */ 567, /* VFPCLASSPSZ256rmbk */ }, { /* 6743 */ 559, /* VFPCLASSPSZ256rmk */ }, { /* 6744 */ 560, /* VFPCLASSPSZ256rr */ }, { /* 6745 */ 561, /* VFPCLASSPSZ256rrk */ }, { /* 6746 */ 562, /* VFPCLASSPSZrm */ }, { /* 6747 */ 566, /* VFPCLASSPSZrmb */ }, { /* 6748 */ 567, /* VFPCLASSPSZrmbk */ }, { /* 6749 */ 563, /* VFPCLASSPSZrmk */ }, { /* 6750 */ 564, /* VFPCLASSPSZrr */ }, { /* 6751 */ 565, /* VFPCLASSPSZrrk */ }, { /* 6752 */ 553, /* VFPCLASSSDZrm */ }, { /* 6753 */ 554, /* VFPCLASSSDZrmk */ }, { /* 6754 */ 568, /* VFPCLASSSDZrr */ }, { /* 6755 */ 569, /* VFPCLASSSDZrrk */ }, { /* 6756 */ 566, /* VFPCLASSSSZrm */ }, { /* 6757 */ 567, /* VFPCLASSSSZrmk */ }, { /* 6758 */ 570, /* VFPCLASSSSZrr */ }, { /* 6759 */ 571, /* VFPCLASSSSZrrk */ }, { /* 6760 */ 305, /* VFRCZPDYrm */ }, { /* 6761 */ 408, /* VFRCZPDYrr */ }, { /* 6762 */ 30, /* VFRCZPDrm */ }, { /* 6763 */ 31, /* VFRCZPDrr */ }, { /* 6764 */ 305, /* VFRCZPSYrm */ }, { /* 6765 */ 408, /* VFRCZPSYrr */ }, { /* 6766 */ 30, /* VFRCZPSrm */ }, { /* 6767 */ 31, /* VFRCZPSrr */ }, { /* 6768 */ 30, /* VFRCZSDrm */ }, { /* 6769 */ 31, /* VFRCZSDrr */ }, { /* 6770 */ 30, /* VFRCZSSrm */ }, { /* 6771 */ 31, /* VFRCZSSrr */ }, { /* 6772 */ 572, /* VGATHERDPDYrm */ }, { /* 6773 */ 573, /* VGATHERDPDZ128rm */ }, { /* 6774 */ 574, /* VGATHERDPDZ256rm */ }, { /* 6775 */ 575, /* VGATHERDPDZrm */ }, { /* 6776 */ 576, /* VGATHERDPDrm */ }, { /* 6777 */ 577, /* VGATHERDPSYrm */ }, { /* 6778 */ 578, /* VGATHERDPSZ128rm */ }, { /* 6779 */ 579, /* VGATHERDPSZ256rm */ }, { /* 6780 */ 580, /* VGATHERDPSZrm */ }, { /* 6781 */ 576, /* VGATHERDPSrm */ }, { /* 6782 */ 581, /* VGATHERPF0DPDm */ }, { /* 6783 */ 582, /* VGATHERPF0DPSm */ }, { /* 6784 */ 583, /* VGATHERPF0QPDm */ }, { /* 6785 */ 583, /* VGATHERPF0QPSm */ }, { /* 6786 */ 581, /* VGATHERPF1DPDm */ }, { /* 6787 */ 582, /* VGATHERPF1DPSm */ }, { /* 6788 */ 583, /* VGATHERPF1QPDm */ }, { /* 6789 */ 583, /* VGATHERPF1QPSm */ }, { /* 6790 */ 577, /* VGATHERQPDYrm */ }, { /* 6791 */ 573, /* VGATHERQPDZ128rm */ }, { /* 6792 */ 584, /* VGATHERQPDZ256rm */ }, { /* 6793 */ 585, /* VGATHERQPDZrm */ }, { /* 6794 */ 576, /* VGATHERQPDrm */ }, { /* 6795 */ 586, /* VGATHERQPSYrm */ }, { /* 6796 */ 578, /* VGATHERQPSZ128rm */ }, { /* 6797 */ 587, /* VGATHERQPSZ256rm */ }, { /* 6798 */ 588, /* VGATHERQPSZrm */ }, { /* 6799 */ 576, /* VGATHERQPSrm */ }, { /* 6800 */ 409, /* VGETEXPPDZ128m */ }, { /* 6801 */ 327, /* VGETEXPPDZ128mb */ }, { /* 6802 */ 328, /* VGETEXPPDZ128mbk */ }, { /* 6803 */ 329, /* VGETEXPPDZ128mbkz */ }, { /* 6804 */ 410, /* VGETEXPPDZ128mk */ }, { /* 6805 */ 411, /* VGETEXPPDZ128mkz */ }, { /* 6806 */ 330, /* VGETEXPPDZ128r */ }, { /* 6807 */ 331, /* VGETEXPPDZ128rk */ }, { /* 6808 */ 332, /* VGETEXPPDZ128rkz */ }, { /* 6809 */ 412, /* VGETEXPPDZ256m */ }, { /* 6810 */ 306, /* VGETEXPPDZ256mb */ }, { /* 6811 */ 307, /* VGETEXPPDZ256mbk */ }, { /* 6812 */ 308, /* VGETEXPPDZ256mbkz */ }, { /* 6813 */ 413, /* VGETEXPPDZ256mk */ }, { /* 6814 */ 414, /* VGETEXPPDZ256mkz */ }, { /* 6815 */ 415, /* VGETEXPPDZ256r */ }, { /* 6816 */ 416, /* VGETEXPPDZ256rk */ }, { /* 6817 */ 417, /* VGETEXPPDZ256rkz */ }, { /* 6818 */ 418, /* VGETEXPPDZm */ }, { /* 6819 */ 312, /* VGETEXPPDZmb */ }, { /* 6820 */ 313, /* VGETEXPPDZmbk */ }, { /* 6821 */ 314, /* VGETEXPPDZmbkz */ }, { /* 6822 */ 419, /* VGETEXPPDZmk */ }, { /* 6823 */ 420, /* VGETEXPPDZmkz */ }, { /* 6824 */ 421, /* VGETEXPPDZr */ }, { /* 6825 */ 494, /* VGETEXPPDZrb */ }, { /* 6826 */ 495, /* VGETEXPPDZrbk */ }, { /* 6827 */ 496, /* VGETEXPPDZrbkz */ }, { /* 6828 */ 425, /* VGETEXPPDZrk */ }, { /* 6829 */ 426, /* VGETEXPPDZrkz */ }, { /* 6830 */ 409, /* VGETEXPPSZ128m */ }, { /* 6831 */ 334, /* VGETEXPPSZ128mb */ }, { /* 6832 */ 335, /* VGETEXPPSZ128mbk */ }, { /* 6833 */ 336, /* VGETEXPPSZ128mbkz */ }, { /* 6834 */ 410, /* VGETEXPPSZ128mk */ }, { /* 6835 */ 411, /* VGETEXPPSZ128mkz */ }, { /* 6836 */ 330, /* VGETEXPPSZ128r */ }, { /* 6837 */ 331, /* VGETEXPPSZ128rk */ }, { /* 6838 */ 332, /* VGETEXPPSZ128rkz */ }, { /* 6839 */ 412, /* VGETEXPPSZ256m */ }, { /* 6840 */ 337, /* VGETEXPPSZ256mb */ }, { /* 6841 */ 338, /* VGETEXPPSZ256mbk */ }, { /* 6842 */ 339, /* VGETEXPPSZ256mbkz */ }, { /* 6843 */ 413, /* VGETEXPPSZ256mk */ }, { /* 6844 */ 414, /* VGETEXPPSZ256mkz */ }, { /* 6845 */ 415, /* VGETEXPPSZ256r */ }, { /* 6846 */ 416, /* VGETEXPPSZ256rk */ }, { /* 6847 */ 417, /* VGETEXPPSZ256rkz */ }, { /* 6848 */ 418, /* VGETEXPPSZm */ }, { /* 6849 */ 340, /* VGETEXPPSZmb */ }, { /* 6850 */ 341, /* VGETEXPPSZmbk */ }, { /* 6851 */ 342, /* VGETEXPPSZmbkz */ }, { /* 6852 */ 419, /* VGETEXPPSZmk */ }, { /* 6853 */ 420, /* VGETEXPPSZmkz */ }, { /* 6854 */ 421, /* VGETEXPPSZr */ }, { /* 6855 */ 497, /* VGETEXPPSZrb */ }, { /* 6856 */ 498, /* VGETEXPPSZrbk */ }, { /* 6857 */ 499, /* VGETEXPPSZrbkz */ }, { /* 6858 */ 425, /* VGETEXPPSZrk */ }, { /* 6859 */ 426, /* VGETEXPPSZrkz */ }, { /* 6860 */ 207, /* VGETEXPSDZm */ }, { /* 6861 */ 208, /* VGETEXPSDZmk */ }, { /* 6862 */ 209, /* VGETEXPSDZmkz */ }, { /* 6863 */ 249, /* VGETEXPSDZr */ }, { /* 6864 */ 249, /* VGETEXPSDZrb */ }, { /* 6865 */ 250, /* VGETEXPSDZrbk */ }, { /* 6866 */ 251, /* VGETEXPSDZrbkz */ }, { /* 6867 */ 250, /* VGETEXPSDZrk */ }, { /* 6868 */ 251, /* VGETEXPSDZrkz */ }, { /* 6869 */ 237, /* VGETEXPSSZm */ }, { /* 6870 */ 238, /* VGETEXPSSZmk */ }, { /* 6871 */ 239, /* VGETEXPSSZmkz */ }, { /* 6872 */ 255, /* VGETEXPSSZr */ }, { /* 6873 */ 255, /* VGETEXPSSZrb */ }, { /* 6874 */ 256, /* VGETEXPSSZrbk */ }, { /* 6875 */ 257, /* VGETEXPSSZrbkz */ }, { /* 6876 */ 256, /* VGETEXPSSZrk */ }, { /* 6877 */ 257, /* VGETEXPSSZrkz */ }, { /* 6878 */ 589, /* VGETMANTPDZ128rmbi */ }, { /* 6879 */ 590, /* VGETMANTPDZ128rmbik */ }, { /* 6880 */ 591, /* VGETMANTPDZ128rmbikz */ }, { /* 6881 */ 592, /* VGETMANTPDZ128rmi */ }, { /* 6882 */ 593, /* VGETMANTPDZ128rmik */ }, { /* 6883 */ 594, /* VGETMANTPDZ128rmikz */ }, { /* 6884 */ 595, /* VGETMANTPDZ128rri */ }, { /* 6885 */ 596, /* VGETMANTPDZ128rrik */ }, { /* 6886 */ 597, /* VGETMANTPDZ128rrikz */ }, { /* 6887 */ 598, /* VGETMANTPDZ256rmbi */ }, { /* 6888 */ 599, /* VGETMANTPDZ256rmbik */ }, { /* 6889 */ 600, /* VGETMANTPDZ256rmbikz */ }, { /* 6890 */ 601, /* VGETMANTPDZ256rmi */ }, { /* 6891 */ 602, /* VGETMANTPDZ256rmik */ }, { /* 6892 */ 603, /* VGETMANTPDZ256rmikz */ }, { /* 6893 */ 604, /* VGETMANTPDZ256rri */ }, { /* 6894 */ 605, /* VGETMANTPDZ256rrik */ }, { /* 6895 */ 606, /* VGETMANTPDZ256rrikz */ }, { /* 6896 */ 607, /* VGETMANTPDZrmbi */ }, { /* 6897 */ 608, /* VGETMANTPDZrmbik */ }, { /* 6898 */ 609, /* VGETMANTPDZrmbikz */ }, { /* 6899 */ 610, /* VGETMANTPDZrmi */ }, { /* 6900 */ 611, /* VGETMANTPDZrmik */ }, { /* 6901 */ 612, /* VGETMANTPDZrmikz */ }, { /* 6902 */ 613, /* VGETMANTPDZrri */ }, { /* 6903 */ 614, /* VGETMANTPDZrrib */ }, { /* 6904 */ 615, /* VGETMANTPDZrribk */ }, { /* 6905 */ 616, /* VGETMANTPDZrribkz */ }, { /* 6906 */ 617, /* VGETMANTPDZrrik */ }, { /* 6907 */ 618, /* VGETMANTPDZrrikz */ }, { /* 6908 */ 619, /* VGETMANTPSZ128rmbi */ }, { /* 6909 */ 620, /* VGETMANTPSZ128rmbik */ }, { /* 6910 */ 621, /* VGETMANTPSZ128rmbikz */ }, { /* 6911 */ 592, /* VGETMANTPSZ128rmi */ }, { /* 6912 */ 593, /* VGETMANTPSZ128rmik */ }, { /* 6913 */ 594, /* VGETMANTPSZ128rmikz */ }, { /* 6914 */ 595, /* VGETMANTPSZ128rri */ }, { /* 6915 */ 596, /* VGETMANTPSZ128rrik */ }, { /* 6916 */ 597, /* VGETMANTPSZ128rrikz */ }, { /* 6917 */ 622, /* VGETMANTPSZ256rmbi */ }, { /* 6918 */ 623, /* VGETMANTPSZ256rmbik */ }, { /* 6919 */ 624, /* VGETMANTPSZ256rmbikz */ }, { /* 6920 */ 601, /* VGETMANTPSZ256rmi */ }, { /* 6921 */ 602, /* VGETMANTPSZ256rmik */ }, { /* 6922 */ 603, /* VGETMANTPSZ256rmikz */ }, { /* 6923 */ 604, /* VGETMANTPSZ256rri */ }, { /* 6924 */ 605, /* VGETMANTPSZ256rrik */ }, { /* 6925 */ 606, /* VGETMANTPSZ256rrikz */ }, { /* 6926 */ 625, /* VGETMANTPSZrmbi */ }, { /* 6927 */ 626, /* VGETMANTPSZrmbik */ }, { /* 6928 */ 627, /* VGETMANTPSZrmbikz */ }, { /* 6929 */ 610, /* VGETMANTPSZrmi */ }, { /* 6930 */ 611, /* VGETMANTPSZrmik */ }, { /* 6931 */ 612, /* VGETMANTPSZrmikz */ }, { /* 6932 */ 613, /* VGETMANTPSZrri */ }, { /* 6933 */ 628, /* VGETMANTPSZrrib */ }, { /* 6934 */ 629, /* VGETMANTPSZrribk */ }, { /* 6935 */ 630, /* VGETMANTPSZrribkz */ }, { /* 6936 */ 617, /* VGETMANTPSZrrik */ }, { /* 6937 */ 618, /* VGETMANTPSZrrikz */ }, { /* 6938 */ 288, /* VGETMANTSDZrmi */ }, { /* 6939 */ 289, /* VGETMANTSDZrmik */ }, { /* 6940 */ 290, /* VGETMANTSDZrmikz */ }, { /* 6941 */ 631, /* VGETMANTSDZrri */ }, { /* 6942 */ 631, /* VGETMANTSDZrrib */ }, { /* 6943 */ 524, /* VGETMANTSDZrribk */ }, { /* 6944 */ 632, /* VGETMANTSDZrribkz */ }, { /* 6945 */ 524, /* VGETMANTSDZrrik */ }, { /* 6946 */ 632, /* VGETMANTSDZrrikz */ }, { /* 6947 */ 261, /* VGETMANTSSZrmi */ }, { /* 6948 */ 262, /* VGETMANTSSZrmik */ }, { /* 6949 */ 263, /* VGETMANTSSZrmikz */ }, { /* 6950 */ 633, /* VGETMANTSSZrri */ }, { /* 6951 */ 633, /* VGETMANTSSZrrib */ }, { /* 6952 */ 526, /* VGETMANTSSZrribk */ }, { /* 6953 */ 634, /* VGETMANTSSZrribkz */ }, { /* 6954 */ 526, /* VGETMANTSSZrrik */ }, { /* 6955 */ 634, /* VGETMANTSSZrrikz */ }, { /* 6956 */ 297, /* VGF2P8AFFINEINVQBYrmi */ }, { /* 6957 */ 298, /* VGF2P8AFFINEINVQBYrri */ }, { /* 6958 */ 299, /* VGF2P8AFFINEINVQBZ128rmbi */ }, { /* 6959 */ 635, /* VGF2P8AFFINEINVQBZ128rmbik */ }, { /* 6960 */ 636, /* VGF2P8AFFINEINVQBZ128rmbikz */ }, { /* 6961 */ 264, /* VGF2P8AFFINEINVQBZ128rmi */ }, { /* 6962 */ 265, /* VGF2P8AFFINEINVQBZ128rmik */ }, { /* 6963 */ 266, /* VGF2P8AFFINEINVQBZ128rmikz */ }, { /* 6964 */ 267, /* VGF2P8AFFINEINVQBZ128rri */ }, { /* 6965 */ 268, /* VGF2P8AFFINEINVQBZ128rrik */ }, { /* 6966 */ 269, /* VGF2P8AFFINEINVQBZ128rrikz */ }, { /* 6967 */ 297, /* VGF2P8AFFINEINVQBZ256rmbi */ }, { /* 6968 */ 637, /* VGF2P8AFFINEINVQBZ256rmbik */ }, { /* 6969 */ 638, /* VGF2P8AFFINEINVQBZ256rmbikz */ }, { /* 6970 */ 273, /* VGF2P8AFFINEINVQBZ256rmi */ }, { /* 6971 */ 274, /* VGF2P8AFFINEINVQBZ256rmik */ }, { /* 6972 */ 275, /* VGF2P8AFFINEINVQBZ256rmikz */ }, { /* 6973 */ 276, /* VGF2P8AFFINEINVQBZ256rri */ }, { /* 6974 */ 277, /* VGF2P8AFFINEINVQBZ256rrik */ }, { /* 6975 */ 278, /* VGF2P8AFFINEINVQBZ256rrikz */ }, { /* 6976 */ 639, /* VGF2P8AFFINEINVQBZrmbi */ }, { /* 6977 */ 640, /* VGF2P8AFFINEINVQBZrmbik */ }, { /* 6978 */ 641, /* VGF2P8AFFINEINVQBZrmbikz */ }, { /* 6979 */ 282, /* VGF2P8AFFINEINVQBZrmi */ }, { /* 6980 */ 283, /* VGF2P8AFFINEINVQBZrmik */ }, { /* 6981 */ 284, /* VGF2P8AFFINEINVQBZrmikz */ }, { /* 6982 */ 285, /* VGF2P8AFFINEINVQBZrri */ }, { /* 6983 */ 286, /* VGF2P8AFFINEINVQBZrrik */ }, { /* 6984 */ 287, /* VGF2P8AFFINEINVQBZrrikz */ }, { /* 6985 */ 299, /* VGF2P8AFFINEINVQBrmi */ }, { /* 6986 */ 300, /* VGF2P8AFFINEINVQBrri */ }, { /* 6987 */ 297, /* VGF2P8AFFINEQBYrmi */ }, { /* 6988 */ 298, /* VGF2P8AFFINEQBYrri */ }, { /* 6989 */ 299, /* VGF2P8AFFINEQBZ128rmbi */ }, { /* 6990 */ 635, /* VGF2P8AFFINEQBZ128rmbik */ }, { /* 6991 */ 636, /* VGF2P8AFFINEQBZ128rmbikz */ }, { /* 6992 */ 264, /* VGF2P8AFFINEQBZ128rmi */ }, { /* 6993 */ 265, /* VGF2P8AFFINEQBZ128rmik */ }, { /* 6994 */ 266, /* VGF2P8AFFINEQBZ128rmikz */ }, { /* 6995 */ 267, /* VGF2P8AFFINEQBZ128rri */ }, { /* 6996 */ 268, /* VGF2P8AFFINEQBZ128rrik */ }, { /* 6997 */ 269, /* VGF2P8AFFINEQBZ128rrikz */ }, { /* 6998 */ 297, /* VGF2P8AFFINEQBZ256rmbi */ }, { /* 6999 */ 637, /* VGF2P8AFFINEQBZ256rmbik */ }, { /* 7000 */ 638, /* VGF2P8AFFINEQBZ256rmbikz */ }, { /* 7001 */ 273, /* VGF2P8AFFINEQBZ256rmi */ }, { /* 7002 */ 274, /* VGF2P8AFFINEQBZ256rmik */ }, { /* 7003 */ 275, /* VGF2P8AFFINEQBZ256rmikz */ }, { /* 7004 */ 276, /* VGF2P8AFFINEQBZ256rri */ }, { /* 7005 */ 277, /* VGF2P8AFFINEQBZ256rrik */ }, { /* 7006 */ 278, /* VGF2P8AFFINEQBZ256rrikz */ }, { /* 7007 */ 639, /* VGF2P8AFFINEQBZrmbi */ }, { /* 7008 */ 640, /* VGF2P8AFFINEQBZrmbik */ }, { /* 7009 */ 641, /* VGF2P8AFFINEQBZrmbikz */ }, { /* 7010 */ 282, /* VGF2P8AFFINEQBZrmi */ }, { /* 7011 */ 283, /* VGF2P8AFFINEQBZrmik */ }, { /* 7012 */ 284, /* VGF2P8AFFINEQBZrmikz */ }, { /* 7013 */ 285, /* VGF2P8AFFINEQBZrri */ }, { /* 7014 */ 286, /* VGF2P8AFFINEQBZrrik */ }, { /* 7015 */ 287, /* VGF2P8AFFINEQBZrrikz */ }, { /* 7016 */ 299, /* VGF2P8AFFINEQBrmi */ }, { /* 7017 */ 300, /* VGF2P8AFFINEQBrri */ }, { /* 7018 */ 204, /* VGF2P8MULBYrm */ }, { /* 7019 */ 205, /* VGF2P8MULBYrr */ }, { /* 7020 */ 206, /* VGF2P8MULBZ128rm */ }, { /* 7021 */ 203, /* VGF2P8MULBZ128rmk */ }, { /* 7022 */ 210, /* VGF2P8MULBZ128rmkz */ }, { /* 7023 */ 211, /* VGF2P8MULBZ128rr */ }, { /* 7024 */ 212, /* VGF2P8MULBZ128rrk */ }, { /* 7025 */ 213, /* VGF2P8MULBZ128rrkz */ }, { /* 7026 */ 214, /* VGF2P8MULBZ256rm */ }, { /* 7027 */ 218, /* VGF2P8MULBZ256rmk */ }, { /* 7028 */ 219, /* VGF2P8MULBZ256rmkz */ }, { /* 7029 */ 220, /* VGF2P8MULBZ256rr */ }, { /* 7030 */ 221, /* VGF2P8MULBZ256rrk */ }, { /* 7031 */ 222, /* VGF2P8MULBZ256rrkz */ }, { /* 7032 */ 223, /* VGF2P8MULBZrm */ }, { /* 7033 */ 227, /* VGF2P8MULBZrmk */ }, { /* 7034 */ 228, /* VGF2P8MULBZrmkz */ }, { /* 7035 */ 229, /* VGF2P8MULBZrr */ }, { /* 7036 */ 233, /* VGF2P8MULBZrrk */ }, { /* 7037 */ 234, /* VGF2P8MULBZrrkz */ }, { /* 7038 */ 235, /* VGF2P8MULBrm */ }, { /* 7039 */ 236, /* VGF2P8MULBrr */ }, { /* 7040 */ 204, /* VHADDPDYrm */ }, { /* 7041 */ 205, /* VHADDPDYrr */ }, { /* 7042 */ 235, /* VHADDPDrm */ }, { /* 7043 */ 236, /* VHADDPDrr */ }, { /* 7044 */ 204, /* VHADDPSYrm */ }, { /* 7045 */ 205, /* VHADDPSYrr */ }, { /* 7046 */ 235, /* VHADDPSrm */ }, { /* 7047 */ 236, /* VHADDPSrr */ }, { /* 7048 */ 204, /* VHSUBPDYrm */ }, { /* 7049 */ 205, /* VHSUBPDYrr */ }, { /* 7050 */ 235, /* VHSUBPDrm */ }, { /* 7051 */ 236, /* VHSUBPDrr */ }, { /* 7052 */ 204, /* VHSUBPSYrm */ }, { /* 7053 */ 205, /* VHSUBPSYrr */ }, { /* 7054 */ 235, /* VHSUBPSrm */ }, { /* 7055 */ 236, /* VHSUBPSrr */ }, { /* 7056 */ 297, /* VINSERTF128rm */ }, { /* 7057 */ 642, /* VINSERTF128rr */ }, { /* 7058 */ 643, /* VINSERTF32x4Z256rm */ }, { /* 7059 */ 644, /* VINSERTF32x4Z256rmk */ }, { /* 7060 */ 645, /* VINSERTF32x4Z256rmkz */ }, { /* 7061 */ 646, /* VINSERTF32x4Z256rr */ }, { /* 7062 */ 647, /* VINSERTF32x4Z256rrk */ }, { /* 7063 */ 648, /* VINSERTF32x4Z256rrkz */ }, { /* 7064 */ 649, /* VINSERTF32x4Zrm */ }, { /* 7065 */ 650, /* VINSERTF32x4Zrmk */ }, { /* 7066 */ 651, /* VINSERTF32x4Zrmkz */ }, { /* 7067 */ 652, /* VINSERTF32x4Zrr */ }, { /* 7068 */ 653, /* VINSERTF32x4Zrrk */ }, { /* 7069 */ 654, /* VINSERTF32x4Zrrkz */ }, { /* 7070 */ 655, /* VINSERTF32x8Zrm */ }, { /* 7071 */ 656, /* VINSERTF32x8Zrmk */ }, { /* 7072 */ 657, /* VINSERTF32x8Zrmkz */ }, { /* 7073 */ 658, /* VINSERTF32x8Zrr */ }, { /* 7074 */ 659, /* VINSERTF32x8Zrrk */ }, { /* 7075 */ 660, /* VINSERTF32x8Zrrkz */ }, { /* 7076 */ 643, /* VINSERTF64x2Z256rm */ }, { /* 7077 */ 644, /* VINSERTF64x2Z256rmk */ }, { /* 7078 */ 645, /* VINSERTF64x2Z256rmkz */ }, { /* 7079 */ 646, /* VINSERTF64x2Z256rr */ }, { /* 7080 */ 647, /* VINSERTF64x2Z256rrk */ }, { /* 7081 */ 648, /* VINSERTF64x2Z256rrkz */ }, { /* 7082 */ 649, /* VINSERTF64x2Zrm */ }, { /* 7083 */ 650, /* VINSERTF64x2Zrmk */ }, { /* 7084 */ 651, /* VINSERTF64x2Zrmkz */ }, { /* 7085 */ 652, /* VINSERTF64x2Zrr */ }, { /* 7086 */ 653, /* VINSERTF64x2Zrrk */ }, { /* 7087 */ 654, /* VINSERTF64x2Zrrkz */ }, { /* 7088 */ 655, /* VINSERTF64x4Zrm */ }, { /* 7089 */ 656, /* VINSERTF64x4Zrmk */ }, { /* 7090 */ 657, /* VINSERTF64x4Zrmkz */ }, { /* 7091 */ 658, /* VINSERTF64x4Zrr */ }, { /* 7092 */ 659, /* VINSERTF64x4Zrrk */ }, { /* 7093 */ 660, /* VINSERTF64x4Zrrkz */ }, { /* 7094 */ 297, /* VINSERTI128rm */ }, { /* 7095 */ 642, /* VINSERTI128rr */ }, { /* 7096 */ 643, /* VINSERTI32x4Z256rm */ }, { /* 7097 */ 644, /* VINSERTI32x4Z256rmk */ }, { /* 7098 */ 645, /* VINSERTI32x4Z256rmkz */ }, { /* 7099 */ 646, /* VINSERTI32x4Z256rr */ }, { /* 7100 */ 647, /* VINSERTI32x4Z256rrk */ }, { /* 7101 */ 648, /* VINSERTI32x4Z256rrkz */ }, { /* 7102 */ 649, /* VINSERTI32x4Zrm */ }, { /* 7103 */ 650, /* VINSERTI32x4Zrmk */ }, { /* 7104 */ 651, /* VINSERTI32x4Zrmkz */ }, { /* 7105 */ 652, /* VINSERTI32x4Zrr */ }, { /* 7106 */ 653, /* VINSERTI32x4Zrrk */ }, { /* 7107 */ 654, /* VINSERTI32x4Zrrkz */ }, { /* 7108 */ 655, /* VINSERTI32x8Zrm */ }, { /* 7109 */ 656, /* VINSERTI32x8Zrmk */ }, { /* 7110 */ 657, /* VINSERTI32x8Zrmkz */ }, { /* 7111 */ 658, /* VINSERTI32x8Zrr */ }, { /* 7112 */ 659, /* VINSERTI32x8Zrrk */ }, { /* 7113 */ 660, /* VINSERTI32x8Zrrkz */ }, { /* 7114 */ 643, /* VINSERTI64x2Z256rm */ }, { /* 7115 */ 644, /* VINSERTI64x2Z256rmk */ }, { /* 7116 */ 645, /* VINSERTI64x2Z256rmkz */ }, { /* 7117 */ 646, /* VINSERTI64x2Z256rr */ }, { /* 7118 */ 647, /* VINSERTI64x2Z256rrk */ }, { /* 7119 */ 648, /* VINSERTI64x2Z256rrkz */ }, { /* 7120 */ 649, /* VINSERTI64x2Zrm */ }, { /* 7121 */ 650, /* VINSERTI64x2Zrmk */ }, { /* 7122 */ 651, /* VINSERTI64x2Zrmkz */ }, { /* 7123 */ 652, /* VINSERTI64x2Zrr */ }, { /* 7124 */ 653, /* VINSERTI64x2Zrrk */ }, { /* 7125 */ 654, /* VINSERTI64x2Zrrkz */ }, { /* 7126 */ 655, /* VINSERTI64x4Zrm */ }, { /* 7127 */ 656, /* VINSERTI64x4Zrmk */ }, { /* 7128 */ 657, /* VINSERTI64x4Zrmkz */ }, { /* 7129 */ 658, /* VINSERTI64x4Zrr */ }, { /* 7130 */ 659, /* VINSERTI64x4Zrrk */ }, { /* 7131 */ 660, /* VINSERTI64x4Zrrkz */ }, { /* 7132 */ 261, /* VINSERTPSZrm */ }, { /* 7133 */ 267, /* VINSERTPSZrr */ }, { /* 7134 */ 299, /* VINSERTPSrm */ }, { /* 7135 */ 300, /* VINSERTPSrr */ }, { /* 7136 */ 305, /* VLDDQUYrm */ }, { /* 7137 */ 30, /* VLDDQUrm */ }, { /* 7138 */ 28, /* VLDMXCSR */ }, { /* 7139 */ 31, /* VMASKMOVDQU */ }, { /* 7140 */ 0, /* */ }, { /* 7141 */ 661, /* VMASKMOVPDYmr */ }, { /* 7142 */ 204, /* VMASKMOVPDYrm */ }, { /* 7143 */ 662, /* VMASKMOVPDmr */ }, { /* 7144 */ 235, /* VMASKMOVPDrm */ }, { /* 7145 */ 661, /* VMASKMOVPSYmr */ }, { /* 7146 */ 204, /* VMASKMOVPSYrm */ }, { /* 7147 */ 662, /* VMASKMOVPSmr */ }, { /* 7148 */ 235, /* VMASKMOVPSrm */ }, { /* 7149 */ 0, /* */ }, { /* 7150 */ 0, /* */ }, { /* 7151 */ 0, /* */ }, { /* 7152 */ 0, /* */ }, { /* 7153 */ 0, /* */ }, { /* 7154 */ 0, /* */ }, { /* 7155 */ 0, /* */ }, { /* 7156 */ 0, /* */ }, { /* 7157 */ 0, /* */ }, { /* 7158 */ 0, /* */ }, { /* 7159 */ 0, /* */ }, { /* 7160 */ 0, /* */ }, { /* 7161 */ 0, /* */ }, { /* 7162 */ 0, /* */ }, { /* 7163 */ 0, /* */ }, { /* 7164 */ 0, /* */ }, { /* 7165 */ 0, /* */ }, { /* 7166 */ 0, /* */ }, { /* 7167 */ 0, /* */ }, { /* 7168 */ 0, /* */ }, { /* 7169 */ 0, /* */ }, { /* 7170 */ 0, /* */ }, { /* 7171 */ 0, /* */ }, { /* 7172 */ 0, /* */ }, { /* 7173 */ 0, /* */ }, { /* 7174 */ 0, /* */ }, { /* 7175 */ 0, /* */ }, { /* 7176 */ 0, /* */ }, { /* 7177 */ 0, /* */ }, { /* 7178 */ 0, /* */ }, { /* 7179 */ 0, /* */ }, { /* 7180 */ 0, /* */ }, { /* 7181 */ 0, /* */ }, { /* 7182 */ 0, /* */ }, { /* 7183 */ 0, /* */ }, { /* 7184 */ 0, /* */ }, { /* 7185 */ 0, /* */ }, { /* 7186 */ 0, /* */ }, { /* 7187 */ 0, /* */ }, { /* 7188 */ 0, /* */ }, { /* 7189 */ 0, /* */ }, { /* 7190 */ 0, /* */ }, { /* 7191 */ 0, /* */ }, { /* 7192 */ 0, /* */ }, { /* 7193 */ 0, /* */ }, { /* 7194 */ 0, /* */ }, { /* 7195 */ 0, /* */ }, { /* 7196 */ 0, /* */ }, { /* 7197 */ 0, /* */ }, { /* 7198 */ 0, /* */ }, { /* 7199 */ 0, /* */ }, { /* 7200 */ 0, /* */ }, { /* 7201 */ 0, /* */ }, { /* 7202 */ 0, /* */ }, { /* 7203 */ 0, /* */ }, { /* 7204 */ 0, /* */ }, { /* 7205 */ 0, /* */ }, { /* 7206 */ 0, /* */ }, { /* 7207 */ 0, /* */ }, { /* 7208 */ 0, /* */ }, { /* 7209 */ 0, /* */ }, { /* 7210 */ 0, /* */ }, { /* 7211 */ 0, /* */ }, { /* 7212 */ 0, /* */ }, { /* 7213 */ 0, /* */ }, { /* 7214 */ 0, /* */ }, { /* 7215 */ 0, /* */ }, { /* 7216 */ 0, /* */ }, { /* 7217 */ 0, /* */ }, { /* 7218 */ 0, /* */ }, { /* 7219 */ 204, /* VMAXPDYrm */ }, { /* 7220 */ 205, /* VMAXPDYrr */ }, { /* 7221 */ 206, /* VMAXPDZ128rm */ }, { /* 7222 */ 207, /* VMAXPDZ128rmb */ }, { /* 7223 */ 208, /* VMAXPDZ128rmbk */ }, { /* 7224 */ 209, /* VMAXPDZ128rmbkz */ }, { /* 7225 */ 203, /* VMAXPDZ128rmk */ }, { /* 7226 */ 210, /* VMAXPDZ128rmkz */ }, { /* 7227 */ 211, /* VMAXPDZ128rr */ }, { /* 7228 */ 212, /* VMAXPDZ128rrk */ }, { /* 7229 */ 213, /* VMAXPDZ128rrkz */ }, { /* 7230 */ 214, /* VMAXPDZ256rm */ }, { /* 7231 */ 215, /* VMAXPDZ256rmb */ }, { /* 7232 */ 216, /* VMAXPDZ256rmbk */ }, { /* 7233 */ 217, /* VMAXPDZ256rmbkz */ }, { /* 7234 */ 218, /* VMAXPDZ256rmk */ }, { /* 7235 */ 219, /* VMAXPDZ256rmkz */ }, { /* 7236 */ 220, /* VMAXPDZ256rr */ }, { /* 7237 */ 221, /* VMAXPDZ256rrk */ }, { /* 7238 */ 222, /* VMAXPDZ256rrkz */ }, { /* 7239 */ 223, /* VMAXPDZrm */ }, { /* 7240 */ 224, /* VMAXPDZrmb */ }, { /* 7241 */ 225, /* VMAXPDZrmbk */ }, { /* 7242 */ 226, /* VMAXPDZrmbkz */ }, { /* 7243 */ 227, /* VMAXPDZrmk */ }, { /* 7244 */ 228, /* VMAXPDZrmkz */ }, { /* 7245 */ 229, /* VMAXPDZrr */ }, { /* 7246 */ 663, /* VMAXPDZrrb */ }, { /* 7247 */ 664, /* VMAXPDZrrbk */ }, { /* 7248 */ 665, /* VMAXPDZrrbkz */ }, { /* 7249 */ 233, /* VMAXPDZrrk */ }, { /* 7250 */ 234, /* VMAXPDZrrkz */ }, { /* 7251 */ 235, /* VMAXPDrm */ }, { /* 7252 */ 236, /* VMAXPDrr */ }, { /* 7253 */ 204, /* VMAXPSYrm */ }, { /* 7254 */ 205, /* VMAXPSYrr */ }, { /* 7255 */ 206, /* VMAXPSZ128rm */ }, { /* 7256 */ 237, /* VMAXPSZ128rmb */ }, { /* 7257 */ 238, /* VMAXPSZ128rmbk */ }, { /* 7258 */ 239, /* VMAXPSZ128rmbkz */ }, { /* 7259 */ 203, /* VMAXPSZ128rmk */ }, { /* 7260 */ 210, /* VMAXPSZ128rmkz */ }, { /* 7261 */ 211, /* VMAXPSZ128rr */ }, { /* 7262 */ 212, /* VMAXPSZ128rrk */ }, { /* 7263 */ 213, /* VMAXPSZ128rrkz */ }, { /* 7264 */ 214, /* VMAXPSZ256rm */ }, { /* 7265 */ 240, /* VMAXPSZ256rmb */ }, { /* 7266 */ 241, /* VMAXPSZ256rmbk */ }, { /* 7267 */ 242, /* VMAXPSZ256rmbkz */ }, { /* 7268 */ 218, /* VMAXPSZ256rmk */ }, { /* 7269 */ 219, /* VMAXPSZ256rmkz */ }, { /* 7270 */ 220, /* VMAXPSZ256rr */ }, { /* 7271 */ 221, /* VMAXPSZ256rrk */ }, { /* 7272 */ 222, /* VMAXPSZ256rrkz */ }, { /* 7273 */ 223, /* VMAXPSZrm */ }, { /* 7274 */ 243, /* VMAXPSZrmb */ }, { /* 7275 */ 244, /* VMAXPSZrmbk */ }, { /* 7276 */ 245, /* VMAXPSZrmbkz */ }, { /* 7277 */ 227, /* VMAXPSZrmk */ }, { /* 7278 */ 228, /* VMAXPSZrmkz */ }, { /* 7279 */ 229, /* VMAXPSZrr */ }, { /* 7280 */ 666, /* VMAXPSZrrb */ }, { /* 7281 */ 667, /* VMAXPSZrrbk */ }, { /* 7282 */ 668, /* VMAXPSZrrbkz */ }, { /* 7283 */ 233, /* VMAXPSZrrk */ }, { /* 7284 */ 234, /* VMAXPSZrrkz */ }, { /* 7285 */ 235, /* VMAXPSrm */ }, { /* 7286 */ 236, /* VMAXPSrr */ }, { /* 7287 */ 0, /* */ }, { /* 7288 */ 207, /* VMAXSDZrm_Int */ }, { /* 7289 */ 208, /* VMAXSDZrm_Intk */ }, { /* 7290 */ 209, /* VMAXSDZrm_Intkz */ }, { /* 7291 */ 0, /* */ }, { /* 7292 */ 249, /* VMAXSDZrr_Int */ }, { /* 7293 */ 250, /* VMAXSDZrr_Intk */ }, { /* 7294 */ 251, /* VMAXSDZrr_Intkz */ }, { /* 7295 */ 249, /* VMAXSDZrrb_Int */ }, { /* 7296 */ 250, /* VMAXSDZrrb_Intk */ }, { /* 7297 */ 251, /* VMAXSDZrrb_Intkz */ }, { /* 7298 */ 235, /* VMAXSDrm */ }, { /* 7299 */ 0, /* */ }, { /* 7300 */ 236, /* VMAXSDrr */ }, { /* 7301 */ 0, /* */ }, { /* 7302 */ 0, /* */ }, { /* 7303 */ 237, /* VMAXSSZrm_Int */ }, { /* 7304 */ 238, /* VMAXSSZrm_Intk */ }, { /* 7305 */ 239, /* VMAXSSZrm_Intkz */ }, { /* 7306 */ 0, /* */ }, { /* 7307 */ 255, /* VMAXSSZrr_Int */ }, { /* 7308 */ 256, /* VMAXSSZrr_Intk */ }, { /* 7309 */ 257, /* VMAXSSZrr_Intkz */ }, { /* 7310 */ 255, /* VMAXSSZrrb_Int */ }, { /* 7311 */ 256, /* VMAXSSZrrb_Intk */ }, { /* 7312 */ 257, /* VMAXSSZrrb_Intkz */ }, { /* 7313 */ 235, /* VMAXSSrm */ }, { /* 7314 */ 0, /* */ }, { /* 7315 */ 236, /* VMAXSSrr */ }, { /* 7316 */ 0, /* */ }, { /* 7317 */ 0, /* VMCALL */ }, { /* 7318 */ 28, /* VMCLEARm */ }, { /* 7319 */ 0, /* VMFUNC */ }, { /* 7320 */ 0, /* */ }, { /* 7321 */ 0, /* */ }, { /* 7322 */ 0, /* */ }, { /* 7323 */ 0, /* */ }, { /* 7324 */ 0, /* */ }, { /* 7325 */ 0, /* */ }, { /* 7326 */ 0, /* */ }, { /* 7327 */ 0, /* */ }, { /* 7328 */ 0, /* */ }, { /* 7329 */ 0, /* */ }, { /* 7330 */ 0, /* */ }, { /* 7331 */ 0, /* */ }, { /* 7332 */ 0, /* */ }, { /* 7333 */ 0, /* */ }, { /* 7334 */ 0, /* */ }, { /* 7335 */ 0, /* */ }, { /* 7336 */ 0, /* */ }, { /* 7337 */ 0, /* */ }, { /* 7338 */ 0, /* */ }, { /* 7339 */ 0, /* */ }, { /* 7340 */ 0, /* */ }, { /* 7341 */ 0, /* */ }, { /* 7342 */ 0, /* */ }, { /* 7343 */ 0, /* */ }, { /* 7344 */ 0, /* */ }, { /* 7345 */ 0, /* */ }, { /* 7346 */ 0, /* */ }, { /* 7347 */ 0, /* */ }, { /* 7348 */ 0, /* */ }, { /* 7349 */ 0, /* */ }, { /* 7350 */ 0, /* */ }, { /* 7351 */ 0, /* */ }, { /* 7352 */ 0, /* */ }, { /* 7353 */ 0, /* */ }, { /* 7354 */ 0, /* */ }, { /* 7355 */ 0, /* */ }, { /* 7356 */ 0, /* */ }, { /* 7357 */ 0, /* */ }, { /* 7358 */ 0, /* */ }, { /* 7359 */ 0, /* */ }, { /* 7360 */ 0, /* */ }, { /* 7361 */ 0, /* */ }, { /* 7362 */ 0, /* */ }, { /* 7363 */ 0, /* */ }, { /* 7364 */ 0, /* */ }, { /* 7365 */ 0, /* */ }, { /* 7366 */ 0, /* */ }, { /* 7367 */ 0, /* */ }, { /* 7368 */ 0, /* */ }, { /* 7369 */ 0, /* */ }, { /* 7370 */ 0, /* */ }, { /* 7371 */ 0, /* */ }, { /* 7372 */ 0, /* */ }, { /* 7373 */ 0, /* */ }, { /* 7374 */ 0, /* */ }, { /* 7375 */ 0, /* */ }, { /* 7376 */ 0, /* */ }, { /* 7377 */ 0, /* */ }, { /* 7378 */ 0, /* */ }, { /* 7379 */ 0, /* */ }, { /* 7380 */ 0, /* */ }, { /* 7381 */ 0, /* */ }, { /* 7382 */ 0, /* */ }, { /* 7383 */ 0, /* */ }, { /* 7384 */ 0, /* */ }, { /* 7385 */ 0, /* */ }, { /* 7386 */ 0, /* */ }, { /* 7387 */ 0, /* */ }, { /* 7388 */ 0, /* */ }, { /* 7389 */ 0, /* */ }, { /* 7390 */ 204, /* VMINPDYrm */ }, { /* 7391 */ 205, /* VMINPDYrr */ }, { /* 7392 */ 206, /* VMINPDZ128rm */ }, { /* 7393 */ 207, /* VMINPDZ128rmb */ }, { /* 7394 */ 208, /* VMINPDZ128rmbk */ }, { /* 7395 */ 209, /* VMINPDZ128rmbkz */ }, { /* 7396 */ 203, /* VMINPDZ128rmk */ }, { /* 7397 */ 210, /* VMINPDZ128rmkz */ }, { /* 7398 */ 211, /* VMINPDZ128rr */ }, { /* 7399 */ 212, /* VMINPDZ128rrk */ }, { /* 7400 */ 213, /* VMINPDZ128rrkz */ }, { /* 7401 */ 214, /* VMINPDZ256rm */ }, { /* 7402 */ 215, /* VMINPDZ256rmb */ }, { /* 7403 */ 216, /* VMINPDZ256rmbk */ }, { /* 7404 */ 217, /* VMINPDZ256rmbkz */ }, { /* 7405 */ 218, /* VMINPDZ256rmk */ }, { /* 7406 */ 219, /* VMINPDZ256rmkz */ }, { /* 7407 */ 220, /* VMINPDZ256rr */ }, { /* 7408 */ 221, /* VMINPDZ256rrk */ }, { /* 7409 */ 222, /* VMINPDZ256rrkz */ }, { /* 7410 */ 223, /* VMINPDZrm */ }, { /* 7411 */ 224, /* VMINPDZrmb */ }, { /* 7412 */ 225, /* VMINPDZrmbk */ }, { /* 7413 */ 226, /* VMINPDZrmbkz */ }, { /* 7414 */ 227, /* VMINPDZrmk */ }, { /* 7415 */ 228, /* VMINPDZrmkz */ }, { /* 7416 */ 229, /* VMINPDZrr */ }, { /* 7417 */ 663, /* VMINPDZrrb */ }, { /* 7418 */ 664, /* VMINPDZrrbk */ }, { /* 7419 */ 665, /* VMINPDZrrbkz */ }, { /* 7420 */ 233, /* VMINPDZrrk */ }, { /* 7421 */ 234, /* VMINPDZrrkz */ }, { /* 7422 */ 235, /* VMINPDrm */ }, { /* 7423 */ 236, /* VMINPDrr */ }, { /* 7424 */ 204, /* VMINPSYrm */ }, { /* 7425 */ 205, /* VMINPSYrr */ }, { /* 7426 */ 206, /* VMINPSZ128rm */ }, { /* 7427 */ 237, /* VMINPSZ128rmb */ }, { /* 7428 */ 238, /* VMINPSZ128rmbk */ }, { /* 7429 */ 239, /* VMINPSZ128rmbkz */ }, { /* 7430 */ 203, /* VMINPSZ128rmk */ }, { /* 7431 */ 210, /* VMINPSZ128rmkz */ }, { /* 7432 */ 211, /* VMINPSZ128rr */ }, { /* 7433 */ 212, /* VMINPSZ128rrk */ }, { /* 7434 */ 213, /* VMINPSZ128rrkz */ }, { /* 7435 */ 214, /* VMINPSZ256rm */ }, { /* 7436 */ 240, /* VMINPSZ256rmb */ }, { /* 7437 */ 241, /* VMINPSZ256rmbk */ }, { /* 7438 */ 242, /* VMINPSZ256rmbkz */ }, { /* 7439 */ 218, /* VMINPSZ256rmk */ }, { /* 7440 */ 219, /* VMINPSZ256rmkz */ }, { /* 7441 */ 220, /* VMINPSZ256rr */ }, { /* 7442 */ 221, /* VMINPSZ256rrk */ }, { /* 7443 */ 222, /* VMINPSZ256rrkz */ }, { /* 7444 */ 223, /* VMINPSZrm */ }, { /* 7445 */ 243, /* VMINPSZrmb */ }, { /* 7446 */ 244, /* VMINPSZrmbk */ }, { /* 7447 */ 245, /* VMINPSZrmbkz */ }, { /* 7448 */ 227, /* VMINPSZrmk */ }, { /* 7449 */ 228, /* VMINPSZrmkz */ }, { /* 7450 */ 229, /* VMINPSZrr */ }, { /* 7451 */ 666, /* VMINPSZrrb */ }, { /* 7452 */ 667, /* VMINPSZrrbk */ }, { /* 7453 */ 668, /* VMINPSZrrbkz */ }, { /* 7454 */ 233, /* VMINPSZrrk */ }, { /* 7455 */ 234, /* VMINPSZrrkz */ }, { /* 7456 */ 235, /* VMINPSrm */ }, { /* 7457 */ 236, /* VMINPSrr */ }, { /* 7458 */ 0, /* */ }, { /* 7459 */ 207, /* VMINSDZrm_Int */ }, { /* 7460 */ 208, /* VMINSDZrm_Intk */ }, { /* 7461 */ 209, /* VMINSDZrm_Intkz */ }, { /* 7462 */ 0, /* */ }, { /* 7463 */ 249, /* VMINSDZrr_Int */ }, { /* 7464 */ 250, /* VMINSDZrr_Intk */ }, { /* 7465 */ 251, /* VMINSDZrr_Intkz */ }, { /* 7466 */ 249, /* VMINSDZrrb_Int */ }, { /* 7467 */ 250, /* VMINSDZrrb_Intk */ }, { /* 7468 */ 251, /* VMINSDZrrb_Intkz */ }, { /* 7469 */ 235, /* VMINSDrm */ }, { /* 7470 */ 0, /* */ }, { /* 7471 */ 236, /* VMINSDrr */ }, { /* 7472 */ 0, /* */ }, { /* 7473 */ 0, /* */ }, { /* 7474 */ 237, /* VMINSSZrm_Int */ }, { /* 7475 */ 238, /* VMINSSZrm_Intk */ }, { /* 7476 */ 239, /* VMINSSZrm_Intkz */ }, { /* 7477 */ 0, /* */ }, { /* 7478 */ 255, /* VMINSSZrr_Int */ }, { /* 7479 */ 256, /* VMINSSZrr_Intk */ }, { /* 7480 */ 257, /* VMINSSZrr_Intkz */ }, { /* 7481 */ 255, /* VMINSSZrrb_Int */ }, { /* 7482 */ 256, /* VMINSSZrrb_Intk */ }, { /* 7483 */ 257, /* VMINSSZrrb_Intkz */ }, { /* 7484 */ 235, /* VMINSSrm */ }, { /* 7485 */ 0, /* */ }, { /* 7486 */ 236, /* VMINSSrr */ }, { /* 7487 */ 0, /* */ }, { /* 7488 */ 0, /* VMLAUNCH */ }, { /* 7489 */ 0, /* VMLOAD32 */ }, { /* 7490 */ 0, /* VMLOAD64 */ }, { /* 7491 */ 0, /* VMMCALL */ }, { /* 7492 */ 327, /* VMOV64toPQIZrm */ }, { /* 7493 */ 669, /* VMOV64toPQIZrr */ }, { /* 7494 */ 30, /* VMOV64toPQIrm */ }, { /* 7495 */ 90, /* VMOV64toPQIrr */ }, { /* 7496 */ 0, /* */ }, { /* 7497 */ 0, /* */ }, { /* 7498 */ 0, /* */ }, { /* 7499 */ 0, /* */ }, { /* 7500 */ 670, /* VMOVAPDYmr */ }, { /* 7501 */ 305, /* VMOVAPDYrm */ }, { /* 7502 */ 408, /* VMOVAPDYrr */ }, { /* 7503 */ 671, /* VMOVAPDYrr_REV */ }, { /* 7504 */ 672, /* VMOVAPDZ128mr */ }, { /* 7505 */ 673, /* VMOVAPDZ128mrk */ }, { /* 7506 */ 409, /* VMOVAPDZ128rm */ }, { /* 7507 */ 410, /* VMOVAPDZ128rmk */ }, { /* 7508 */ 411, /* VMOVAPDZ128rmkz */ }, { /* 7509 */ 330, /* VMOVAPDZ128rr */ }, { /* 7510 */ 381, /* VMOVAPDZ128rr_REV */ }, { /* 7511 */ 331, /* VMOVAPDZ128rrk */ }, { /* 7512 */ 383, /* VMOVAPDZ128rrk_REV */ }, { /* 7513 */ 332, /* VMOVAPDZ128rrkz */ }, { /* 7514 */ 383, /* VMOVAPDZ128rrkz_REV */ }, { /* 7515 */ 674, /* VMOVAPDZ256mr */ }, { /* 7516 */ 675, /* VMOVAPDZ256mrk */ }, { /* 7517 */ 412, /* VMOVAPDZ256rm */ }, { /* 7518 */ 413, /* VMOVAPDZ256rmk */ }, { /* 7519 */ 414, /* VMOVAPDZ256rmkz */ }, { /* 7520 */ 415, /* VMOVAPDZ256rr */ }, { /* 7521 */ 386, /* VMOVAPDZ256rr_REV */ }, { /* 7522 */ 416, /* VMOVAPDZ256rrk */ }, { /* 7523 */ 388, /* VMOVAPDZ256rrk_REV */ }, { /* 7524 */ 417, /* VMOVAPDZ256rrkz */ }, { /* 7525 */ 388, /* VMOVAPDZ256rrkz_REV */ }, { /* 7526 */ 676, /* VMOVAPDZmr */ }, { /* 7527 */ 677, /* VMOVAPDZmrk */ }, { /* 7528 */ 418, /* VMOVAPDZrm */ }, { /* 7529 */ 419, /* VMOVAPDZrmk */ }, { /* 7530 */ 420, /* VMOVAPDZrmkz */ }, { /* 7531 */ 421, /* VMOVAPDZrr */ }, { /* 7532 */ 391, /* VMOVAPDZrr_REV */ }, { /* 7533 */ 425, /* VMOVAPDZrrk */ }, { /* 7534 */ 393, /* VMOVAPDZrrk_REV */ }, { /* 7535 */ 426, /* VMOVAPDZrrkz */ }, { /* 7536 */ 393, /* VMOVAPDZrrkz_REV */ }, { /* 7537 */ 169, /* VMOVAPDmr */ }, { /* 7538 */ 30, /* VMOVAPDrm */ }, { /* 7539 */ 31, /* VMOVAPDrr */ }, { /* 7540 */ 170, /* VMOVAPDrr_REV */ }, { /* 7541 */ 670, /* VMOVAPSYmr */ }, { /* 7542 */ 305, /* VMOVAPSYrm */ }, { /* 7543 */ 408, /* VMOVAPSYrr */ }, { /* 7544 */ 671, /* VMOVAPSYrr_REV */ }, { /* 7545 */ 672, /* VMOVAPSZ128mr */ }, { /* 7546 */ 673, /* VMOVAPSZ128mrk */ }, { /* 7547 */ 409, /* VMOVAPSZ128rm */ }, { /* 7548 */ 410, /* VMOVAPSZ128rmk */ }, { /* 7549 */ 411, /* VMOVAPSZ128rmkz */ }, { /* 7550 */ 330, /* VMOVAPSZ128rr */ }, { /* 7551 */ 381, /* VMOVAPSZ128rr_REV */ }, { /* 7552 */ 331, /* VMOVAPSZ128rrk */ }, { /* 7553 */ 383, /* VMOVAPSZ128rrk_REV */ }, { /* 7554 */ 332, /* VMOVAPSZ128rrkz */ }, { /* 7555 */ 383, /* VMOVAPSZ128rrkz_REV */ }, { /* 7556 */ 674, /* VMOVAPSZ256mr */ }, { /* 7557 */ 675, /* VMOVAPSZ256mrk */ }, { /* 7558 */ 412, /* VMOVAPSZ256rm */ }, { /* 7559 */ 413, /* VMOVAPSZ256rmk */ }, { /* 7560 */ 414, /* VMOVAPSZ256rmkz */ }, { /* 7561 */ 415, /* VMOVAPSZ256rr */ }, { /* 7562 */ 386, /* VMOVAPSZ256rr_REV */ }, { /* 7563 */ 416, /* VMOVAPSZ256rrk */ }, { /* 7564 */ 388, /* VMOVAPSZ256rrk_REV */ }, { /* 7565 */ 417, /* VMOVAPSZ256rrkz */ }, { /* 7566 */ 388, /* VMOVAPSZ256rrkz_REV */ }, { /* 7567 */ 676, /* VMOVAPSZmr */ }, { /* 7568 */ 677, /* VMOVAPSZmrk */ }, { /* 7569 */ 418, /* VMOVAPSZrm */ }, { /* 7570 */ 419, /* VMOVAPSZrmk */ }, { /* 7571 */ 420, /* VMOVAPSZrmkz */ }, { /* 7572 */ 421, /* VMOVAPSZrr */ }, { /* 7573 */ 391, /* VMOVAPSZrr_REV */ }, { /* 7574 */ 425, /* VMOVAPSZrrk */ }, { /* 7575 */ 393, /* VMOVAPSZrrk_REV */ }, { /* 7576 */ 426, /* VMOVAPSZrrkz */ }, { /* 7577 */ 393, /* VMOVAPSZrrkz_REV */ }, { /* 7578 */ 169, /* VMOVAPSmr */ }, { /* 7579 */ 30, /* VMOVAPSrm */ }, { /* 7580 */ 31, /* VMOVAPSrr */ }, { /* 7581 */ 170, /* VMOVAPSrr_REV */ }, { /* 7582 */ 305, /* VMOVDDUPYrm */ }, { /* 7583 */ 408, /* VMOVDDUPYrr */ }, { /* 7584 */ 327, /* VMOVDDUPZ128rm */ }, { /* 7585 */ 328, /* VMOVDDUPZ128rmk */ }, { /* 7586 */ 329, /* VMOVDDUPZ128rmkz */ }, { /* 7587 */ 330, /* VMOVDDUPZ128rr */ }, { /* 7588 */ 331, /* VMOVDDUPZ128rrk */ }, { /* 7589 */ 332, /* VMOVDDUPZ128rrkz */ }, { /* 7590 */ 412, /* VMOVDDUPZ256rm */ }, { /* 7591 */ 413, /* VMOVDDUPZ256rmk */ }, { /* 7592 */ 414, /* VMOVDDUPZ256rmkz */ }, { /* 7593 */ 415, /* VMOVDDUPZ256rr */ }, { /* 7594 */ 416, /* VMOVDDUPZ256rrk */ }, { /* 7595 */ 417, /* VMOVDDUPZ256rrkz */ }, { /* 7596 */ 418, /* VMOVDDUPZrm */ }, { /* 7597 */ 419, /* VMOVDDUPZrmk */ }, { /* 7598 */ 420, /* VMOVDDUPZrmkz */ }, { /* 7599 */ 421, /* VMOVDDUPZrr */ }, { /* 7600 */ 425, /* VMOVDDUPZrrk */ }, { /* 7601 */ 426, /* VMOVDDUPZrrkz */ }, { /* 7602 */ 30, /* VMOVDDUPrm */ }, { /* 7603 */ 31, /* VMOVDDUPrr */ }, { /* 7604 */ 334, /* VMOVDI2PDIZrm */ }, { /* 7605 */ 678, /* VMOVDI2PDIZrr */ }, { /* 7606 */ 30, /* VMOVDI2PDIrm */ }, { /* 7607 */ 89, /* VMOVDI2PDIrr */ }, { /* 7608 */ 0, /* */ }, { /* 7609 */ 0, /* */ }, { /* 7610 */ 0, /* */ }, { /* 7611 */ 0, /* */ }, { /* 7612 */ 672, /* VMOVDQA32Z128mr */ }, { /* 7613 */ 673, /* VMOVDQA32Z128mrk */ }, { /* 7614 */ 409, /* VMOVDQA32Z128rm */ }, { /* 7615 */ 410, /* VMOVDQA32Z128rmk */ }, { /* 7616 */ 411, /* VMOVDQA32Z128rmkz */ }, { /* 7617 */ 330, /* VMOVDQA32Z128rr */ }, { /* 7618 */ 381, /* VMOVDQA32Z128rr_REV */ }, { /* 7619 */ 331, /* VMOVDQA32Z128rrk */ }, { /* 7620 */ 383, /* VMOVDQA32Z128rrk_REV */ }, { /* 7621 */ 332, /* VMOVDQA32Z128rrkz */ }, { /* 7622 */ 383, /* VMOVDQA32Z128rrkz_REV */ }, { /* 7623 */ 674, /* VMOVDQA32Z256mr */ }, { /* 7624 */ 675, /* VMOVDQA32Z256mrk */ }, { /* 7625 */ 412, /* VMOVDQA32Z256rm */ }, { /* 7626 */ 413, /* VMOVDQA32Z256rmk */ }, { /* 7627 */ 414, /* VMOVDQA32Z256rmkz */ }, { /* 7628 */ 415, /* VMOVDQA32Z256rr */ }, { /* 7629 */ 386, /* VMOVDQA32Z256rr_REV */ }, { /* 7630 */ 416, /* VMOVDQA32Z256rrk */ }, { /* 7631 */ 388, /* VMOVDQA32Z256rrk_REV */ }, { /* 7632 */ 417, /* VMOVDQA32Z256rrkz */ }, { /* 7633 */ 388, /* VMOVDQA32Z256rrkz_REV */ }, { /* 7634 */ 676, /* VMOVDQA32Zmr */ }, { /* 7635 */ 677, /* VMOVDQA32Zmrk */ }, { /* 7636 */ 418, /* VMOVDQA32Zrm */ }, { /* 7637 */ 419, /* VMOVDQA32Zrmk */ }, { /* 7638 */ 420, /* VMOVDQA32Zrmkz */ }, { /* 7639 */ 421, /* VMOVDQA32Zrr */ }, { /* 7640 */ 391, /* VMOVDQA32Zrr_REV */ }, { /* 7641 */ 425, /* VMOVDQA32Zrrk */ }, { /* 7642 */ 393, /* VMOVDQA32Zrrk_REV */ }, { /* 7643 */ 426, /* VMOVDQA32Zrrkz */ }, { /* 7644 */ 393, /* VMOVDQA32Zrrkz_REV */ }, { /* 7645 */ 672, /* VMOVDQA64Z128mr */ }, { /* 7646 */ 673, /* VMOVDQA64Z128mrk */ }, { /* 7647 */ 409, /* VMOVDQA64Z128rm */ }, { /* 7648 */ 410, /* VMOVDQA64Z128rmk */ }, { /* 7649 */ 411, /* VMOVDQA64Z128rmkz */ }, { /* 7650 */ 330, /* VMOVDQA64Z128rr */ }, { /* 7651 */ 381, /* VMOVDQA64Z128rr_REV */ }, { /* 7652 */ 331, /* VMOVDQA64Z128rrk */ }, { /* 7653 */ 383, /* VMOVDQA64Z128rrk_REV */ }, { /* 7654 */ 332, /* VMOVDQA64Z128rrkz */ }, { /* 7655 */ 383, /* VMOVDQA64Z128rrkz_REV */ }, { /* 7656 */ 674, /* VMOVDQA64Z256mr */ }, { /* 7657 */ 675, /* VMOVDQA64Z256mrk */ }, { /* 7658 */ 412, /* VMOVDQA64Z256rm */ }, { /* 7659 */ 413, /* VMOVDQA64Z256rmk */ }, { /* 7660 */ 414, /* VMOVDQA64Z256rmkz */ }, { /* 7661 */ 415, /* VMOVDQA64Z256rr */ }, { /* 7662 */ 386, /* VMOVDQA64Z256rr_REV */ }, { /* 7663 */ 416, /* VMOVDQA64Z256rrk */ }, { /* 7664 */ 388, /* VMOVDQA64Z256rrk_REV */ }, { /* 7665 */ 417, /* VMOVDQA64Z256rrkz */ }, { /* 7666 */ 388, /* VMOVDQA64Z256rrkz_REV */ }, { /* 7667 */ 676, /* VMOVDQA64Zmr */ }, { /* 7668 */ 677, /* VMOVDQA64Zmrk */ }, { /* 7669 */ 418, /* VMOVDQA64Zrm */ }, { /* 7670 */ 419, /* VMOVDQA64Zrmk */ }, { /* 7671 */ 420, /* VMOVDQA64Zrmkz */ }, { /* 7672 */ 421, /* VMOVDQA64Zrr */ }, { /* 7673 */ 391, /* VMOVDQA64Zrr_REV */ }, { /* 7674 */ 425, /* VMOVDQA64Zrrk */ }, { /* 7675 */ 393, /* VMOVDQA64Zrrk_REV */ }, { /* 7676 */ 426, /* VMOVDQA64Zrrkz */ }, { /* 7677 */ 393, /* VMOVDQA64Zrrkz_REV */ }, { /* 7678 */ 670, /* VMOVDQAYmr */ }, { /* 7679 */ 305, /* VMOVDQAYrm */ }, { /* 7680 */ 408, /* VMOVDQAYrr */ }, { /* 7681 */ 671, /* VMOVDQAYrr_REV */ }, { /* 7682 */ 169, /* VMOVDQAmr */ }, { /* 7683 */ 30, /* VMOVDQArm */ }, { /* 7684 */ 31, /* VMOVDQArr */ }, { /* 7685 */ 170, /* VMOVDQArr_REV */ }, { /* 7686 */ 672, /* VMOVDQU16Z128mr */ }, { /* 7687 */ 673, /* VMOVDQU16Z128mrk */ }, { /* 7688 */ 409, /* VMOVDQU16Z128rm */ }, { /* 7689 */ 410, /* VMOVDQU16Z128rmk */ }, { /* 7690 */ 411, /* VMOVDQU16Z128rmkz */ }, { /* 7691 */ 330, /* VMOVDQU16Z128rr */ }, { /* 7692 */ 381, /* VMOVDQU16Z128rr_REV */ }, { /* 7693 */ 331, /* VMOVDQU16Z128rrk */ }, { /* 7694 */ 383, /* VMOVDQU16Z128rrk_REV */ }, { /* 7695 */ 332, /* VMOVDQU16Z128rrkz */ }, { /* 7696 */ 383, /* VMOVDQU16Z128rrkz_REV */ }, { /* 7697 */ 674, /* VMOVDQU16Z256mr */ }, { /* 7698 */ 675, /* VMOVDQU16Z256mrk */ }, { /* 7699 */ 412, /* VMOVDQU16Z256rm */ }, { /* 7700 */ 413, /* VMOVDQU16Z256rmk */ }, { /* 7701 */ 414, /* VMOVDQU16Z256rmkz */ }, { /* 7702 */ 415, /* VMOVDQU16Z256rr */ }, { /* 7703 */ 386, /* VMOVDQU16Z256rr_REV */ }, { /* 7704 */ 416, /* VMOVDQU16Z256rrk */ }, { /* 7705 */ 388, /* VMOVDQU16Z256rrk_REV */ }, { /* 7706 */ 417, /* VMOVDQU16Z256rrkz */ }, { /* 7707 */ 388, /* VMOVDQU16Z256rrkz_REV */ }, { /* 7708 */ 676, /* VMOVDQU16Zmr */ }, { /* 7709 */ 677, /* VMOVDQU16Zmrk */ }, { /* 7710 */ 418, /* VMOVDQU16Zrm */ }, { /* 7711 */ 419, /* VMOVDQU16Zrmk */ }, { /* 7712 */ 420, /* VMOVDQU16Zrmkz */ }, { /* 7713 */ 421, /* VMOVDQU16Zrr */ }, { /* 7714 */ 391, /* VMOVDQU16Zrr_REV */ }, { /* 7715 */ 425, /* VMOVDQU16Zrrk */ }, { /* 7716 */ 393, /* VMOVDQU16Zrrk_REV */ }, { /* 7717 */ 426, /* VMOVDQU16Zrrkz */ }, { /* 7718 */ 393, /* VMOVDQU16Zrrkz_REV */ }, { /* 7719 */ 672, /* VMOVDQU32Z128mr */ }, { /* 7720 */ 673, /* VMOVDQU32Z128mrk */ }, { /* 7721 */ 409, /* VMOVDQU32Z128rm */ }, { /* 7722 */ 410, /* VMOVDQU32Z128rmk */ }, { /* 7723 */ 411, /* VMOVDQU32Z128rmkz */ }, { /* 7724 */ 330, /* VMOVDQU32Z128rr */ }, { /* 7725 */ 381, /* VMOVDQU32Z128rr_REV */ }, { /* 7726 */ 331, /* VMOVDQU32Z128rrk */ }, { /* 7727 */ 383, /* VMOVDQU32Z128rrk_REV */ }, { /* 7728 */ 332, /* VMOVDQU32Z128rrkz */ }, { /* 7729 */ 383, /* VMOVDQU32Z128rrkz_REV */ }, { /* 7730 */ 674, /* VMOVDQU32Z256mr */ }, { /* 7731 */ 675, /* VMOVDQU32Z256mrk */ }, { /* 7732 */ 412, /* VMOVDQU32Z256rm */ }, { /* 7733 */ 413, /* VMOVDQU32Z256rmk */ }, { /* 7734 */ 414, /* VMOVDQU32Z256rmkz */ }, { /* 7735 */ 415, /* VMOVDQU32Z256rr */ }, { /* 7736 */ 386, /* VMOVDQU32Z256rr_REV */ }, { /* 7737 */ 416, /* VMOVDQU32Z256rrk */ }, { /* 7738 */ 388, /* VMOVDQU32Z256rrk_REV */ }, { /* 7739 */ 417, /* VMOVDQU32Z256rrkz */ }, { /* 7740 */ 388, /* VMOVDQU32Z256rrkz_REV */ }, { /* 7741 */ 676, /* VMOVDQU32Zmr */ }, { /* 7742 */ 677, /* VMOVDQU32Zmrk */ }, { /* 7743 */ 418, /* VMOVDQU32Zrm */ }, { /* 7744 */ 419, /* VMOVDQU32Zrmk */ }, { /* 7745 */ 420, /* VMOVDQU32Zrmkz */ }, { /* 7746 */ 421, /* VMOVDQU32Zrr */ }, { /* 7747 */ 391, /* VMOVDQU32Zrr_REV */ }, { /* 7748 */ 425, /* VMOVDQU32Zrrk */ }, { /* 7749 */ 393, /* VMOVDQU32Zrrk_REV */ }, { /* 7750 */ 426, /* VMOVDQU32Zrrkz */ }, { /* 7751 */ 393, /* VMOVDQU32Zrrkz_REV */ }, { /* 7752 */ 672, /* VMOVDQU64Z128mr */ }, { /* 7753 */ 673, /* VMOVDQU64Z128mrk */ }, { /* 7754 */ 409, /* VMOVDQU64Z128rm */ }, { /* 7755 */ 410, /* VMOVDQU64Z128rmk */ }, { /* 7756 */ 411, /* VMOVDQU64Z128rmkz */ }, { /* 7757 */ 330, /* VMOVDQU64Z128rr */ }, { /* 7758 */ 381, /* VMOVDQU64Z128rr_REV */ }, { /* 7759 */ 331, /* VMOVDQU64Z128rrk */ }, { /* 7760 */ 383, /* VMOVDQU64Z128rrk_REV */ }, { /* 7761 */ 332, /* VMOVDQU64Z128rrkz */ }, { /* 7762 */ 383, /* VMOVDQU64Z128rrkz_REV */ }, { /* 7763 */ 674, /* VMOVDQU64Z256mr */ }, { /* 7764 */ 675, /* VMOVDQU64Z256mrk */ }, { /* 7765 */ 412, /* VMOVDQU64Z256rm */ }, { /* 7766 */ 413, /* VMOVDQU64Z256rmk */ }, { /* 7767 */ 414, /* VMOVDQU64Z256rmkz */ }, { /* 7768 */ 415, /* VMOVDQU64Z256rr */ }, { /* 7769 */ 386, /* VMOVDQU64Z256rr_REV */ }, { /* 7770 */ 416, /* VMOVDQU64Z256rrk */ }, { /* 7771 */ 388, /* VMOVDQU64Z256rrk_REV */ }, { /* 7772 */ 417, /* VMOVDQU64Z256rrkz */ }, { /* 7773 */ 388, /* VMOVDQU64Z256rrkz_REV */ }, { /* 7774 */ 676, /* VMOVDQU64Zmr */ }, { /* 7775 */ 677, /* VMOVDQU64Zmrk */ }, { /* 7776 */ 418, /* VMOVDQU64Zrm */ }, { /* 7777 */ 419, /* VMOVDQU64Zrmk */ }, { /* 7778 */ 420, /* VMOVDQU64Zrmkz */ }, { /* 7779 */ 421, /* VMOVDQU64Zrr */ }, { /* 7780 */ 391, /* VMOVDQU64Zrr_REV */ }, { /* 7781 */ 425, /* VMOVDQU64Zrrk */ }, { /* 7782 */ 393, /* VMOVDQU64Zrrk_REV */ }, { /* 7783 */ 426, /* VMOVDQU64Zrrkz */ }, { /* 7784 */ 393, /* VMOVDQU64Zrrkz_REV */ }, { /* 7785 */ 672, /* VMOVDQU8Z128mr */ }, { /* 7786 */ 673, /* VMOVDQU8Z128mrk */ }, { /* 7787 */ 409, /* VMOVDQU8Z128rm */ }, { /* 7788 */ 410, /* VMOVDQU8Z128rmk */ }, { /* 7789 */ 411, /* VMOVDQU8Z128rmkz */ }, { /* 7790 */ 330, /* VMOVDQU8Z128rr */ }, { /* 7791 */ 381, /* VMOVDQU8Z128rr_REV */ }, { /* 7792 */ 331, /* VMOVDQU8Z128rrk */ }, { /* 7793 */ 383, /* VMOVDQU8Z128rrk_REV */ }, { /* 7794 */ 332, /* VMOVDQU8Z128rrkz */ }, { /* 7795 */ 383, /* VMOVDQU8Z128rrkz_REV */ }, { /* 7796 */ 674, /* VMOVDQU8Z256mr */ }, { /* 7797 */ 675, /* VMOVDQU8Z256mrk */ }, { /* 7798 */ 412, /* VMOVDQU8Z256rm */ }, { /* 7799 */ 413, /* VMOVDQU8Z256rmk */ }, { /* 7800 */ 414, /* VMOVDQU8Z256rmkz */ }, { /* 7801 */ 415, /* VMOVDQU8Z256rr */ }, { /* 7802 */ 386, /* VMOVDQU8Z256rr_REV */ }, { /* 7803 */ 416, /* VMOVDQU8Z256rrk */ }, { /* 7804 */ 388, /* VMOVDQU8Z256rrk_REV */ }, { /* 7805 */ 417, /* VMOVDQU8Z256rrkz */ }, { /* 7806 */ 388, /* VMOVDQU8Z256rrkz_REV */ }, { /* 7807 */ 676, /* VMOVDQU8Zmr */ }, { /* 7808 */ 677, /* VMOVDQU8Zmrk */ }, { /* 7809 */ 418, /* VMOVDQU8Zrm */ }, { /* 7810 */ 419, /* VMOVDQU8Zrmk */ }, { /* 7811 */ 420, /* VMOVDQU8Zrmkz */ }, { /* 7812 */ 421, /* VMOVDQU8Zrr */ }, { /* 7813 */ 391, /* VMOVDQU8Zrr_REV */ }, { /* 7814 */ 425, /* VMOVDQU8Zrrk */ }, { /* 7815 */ 393, /* VMOVDQU8Zrrk_REV */ }, { /* 7816 */ 426, /* VMOVDQU8Zrrkz */ }, { /* 7817 */ 393, /* VMOVDQU8Zrrkz_REV */ }, { /* 7818 */ 670, /* VMOVDQUYmr */ }, { /* 7819 */ 305, /* VMOVDQUYrm */ }, { /* 7820 */ 408, /* VMOVDQUYrr */ }, { /* 7821 */ 671, /* VMOVDQUYrr_REV */ }, { /* 7822 */ 169, /* VMOVDQUmr */ }, { /* 7823 */ 30, /* VMOVDQUrm */ }, { /* 7824 */ 31, /* VMOVDQUrr */ }, { /* 7825 */ 170, /* VMOVDQUrr_REV */ }, { /* 7826 */ 211, /* VMOVHLPSZrr */ }, { /* 7827 */ 236, /* VMOVHLPSrr */ }, { /* 7828 */ 379, /* VMOVHPDZ128mr */ }, { /* 7829 */ 207, /* VMOVHPDZ128rm */ }, { /* 7830 */ 169, /* VMOVHPDmr */ }, { /* 7831 */ 235, /* VMOVHPDrm */ }, { /* 7832 */ 379, /* VMOVHPSZ128mr */ }, { /* 7833 */ 207, /* VMOVHPSZ128rm */ }, { /* 7834 */ 169, /* VMOVHPSmr */ }, { /* 7835 */ 235, /* VMOVHPSrm */ }, { /* 7836 */ 211, /* VMOVLHPSZrr */ }, { /* 7837 */ 236, /* VMOVLHPSrr */ }, { /* 7838 */ 379, /* VMOVLPDZ128mr */ }, { /* 7839 */ 207, /* VMOVLPDZ128rm */ }, { /* 7840 */ 169, /* VMOVLPDmr */ }, { /* 7841 */ 235, /* VMOVLPDrm */ }, { /* 7842 */ 379, /* VMOVLPSZ128mr */ }, { /* 7843 */ 207, /* VMOVLPSZ128rm */ }, { /* 7844 */ 169, /* VMOVLPSmr */ }, { /* 7845 */ 235, /* VMOVLPSrm */ }, { /* 7846 */ 679, /* VMOVMSKPDYrr */ }, { /* 7847 */ 88, /* VMOVMSKPDrr */ }, { /* 7848 */ 679, /* VMOVMSKPSYrr */ }, { /* 7849 */ 88, /* VMOVMSKPSrr */ }, { /* 7850 */ 305, /* VMOVNTDQAYrm */ }, { /* 7851 */ 409, /* VMOVNTDQAZ128rm */ }, { /* 7852 */ 412, /* VMOVNTDQAZ256rm */ }, { /* 7853 */ 418, /* VMOVNTDQAZrm */ }, { /* 7854 */ 30, /* VMOVNTDQArm */ }, { /* 7855 */ 670, /* VMOVNTDQYmr */ }, { /* 7856 */ 672, /* VMOVNTDQZ128mr */ }, { /* 7857 */ 674, /* VMOVNTDQZ256mr */ }, { /* 7858 */ 676, /* VMOVNTDQZmr */ }, { /* 7859 */ 169, /* VMOVNTDQmr */ }, { /* 7860 */ 670, /* VMOVNTPDYmr */ }, { /* 7861 */ 672, /* VMOVNTPDZ128mr */ }, { /* 7862 */ 674, /* VMOVNTPDZ256mr */ }, { /* 7863 */ 676, /* VMOVNTPDZmr */ }, { /* 7864 */ 169, /* VMOVNTPDmr */ }, { /* 7865 */ 670, /* VMOVNTPSYmr */ }, { /* 7866 */ 672, /* VMOVNTPSZ128mr */ }, { /* 7867 */ 674, /* VMOVNTPSZ256mr */ }, { /* 7868 */ 676, /* VMOVNTPSZmr */ }, { /* 7869 */ 169, /* VMOVNTPSmr */ }, { /* 7870 */ 394, /* VMOVPDI2DIZmr */ }, { /* 7871 */ 680, /* VMOVPDI2DIZrr */ }, { /* 7872 */ 169, /* VMOVPDI2DImr */ }, { /* 7873 */ 173, /* VMOVPDI2DIrr */ }, { /* 7874 */ 379, /* VMOVPQI2QIZmr */ }, { /* 7875 */ 381, /* VMOVPQI2QIZrr */ }, { /* 7876 */ 169, /* VMOVPQI2QImr */ }, { /* 7877 */ 170, /* VMOVPQI2QIrr */ }, { /* 7878 */ 672, /* VMOVPQIto64Zmr */ }, { /* 7879 */ 681, /* VMOVPQIto64Zrr */ }, { /* 7880 */ 169, /* VMOVPQIto64mr */ }, { /* 7881 */ 174, /* VMOVPQIto64rr */ }, { /* 7882 */ 327, /* VMOVQI2PQIZrm */ }, { /* 7883 */ 30, /* VMOVQI2PQIrm */ }, { /* 7884 */ 379, /* VMOVSDZmr */ }, { /* 7885 */ 380, /* VMOVSDZmrk */ }, { /* 7886 */ 327, /* VMOVSDZrm */ }, { /* 7887 */ 328, /* VMOVSDZrmk */ }, { /* 7888 */ 329, /* VMOVSDZrmkz */ }, { /* 7889 */ 249, /* VMOVSDZrr */ }, { /* 7890 */ 682, /* VMOVSDZrr_REV */ }, { /* 7891 */ 250, /* VMOVSDZrrk */ }, { /* 7892 */ 683, /* VMOVSDZrrk_REV */ }, { /* 7893 */ 251, /* VMOVSDZrrkz */ }, { /* 7894 */ 684, /* VMOVSDZrrkz_REV */ }, { /* 7895 */ 169, /* VMOVSDmr */ }, { /* 7896 */ 30, /* VMOVSDrm */ }, { /* 7897 */ 236, /* VMOVSDrr */ }, { /* 7898 */ 685, /* VMOVSDrr_REV */ }, { /* 7899 */ 0, /* */ }, { /* 7900 */ 0, /* */ }, { /* 7901 */ 0, /* */ }, { /* 7902 */ 0, /* */ }, { /* 7903 */ 305, /* VMOVSHDUPYrm */ }, { /* 7904 */ 408, /* VMOVSHDUPYrr */ }, { /* 7905 */ 409, /* VMOVSHDUPZ128rm */ }, { /* 7906 */ 410, /* VMOVSHDUPZ128rmk */ }, { /* 7907 */ 411, /* VMOVSHDUPZ128rmkz */ }, { /* 7908 */ 330, /* VMOVSHDUPZ128rr */ }, { /* 7909 */ 331, /* VMOVSHDUPZ128rrk */ }, { /* 7910 */ 332, /* VMOVSHDUPZ128rrkz */ }, { /* 7911 */ 412, /* VMOVSHDUPZ256rm */ }, { /* 7912 */ 413, /* VMOVSHDUPZ256rmk */ }, { /* 7913 */ 414, /* VMOVSHDUPZ256rmkz */ }, { /* 7914 */ 415, /* VMOVSHDUPZ256rr */ }, { /* 7915 */ 416, /* VMOVSHDUPZ256rrk */ }, { /* 7916 */ 417, /* VMOVSHDUPZ256rrkz */ }, { /* 7917 */ 418, /* VMOVSHDUPZrm */ }, { /* 7918 */ 419, /* VMOVSHDUPZrmk */ }, { /* 7919 */ 420, /* VMOVSHDUPZrmkz */ }, { /* 7920 */ 421, /* VMOVSHDUPZrr */ }, { /* 7921 */ 425, /* VMOVSHDUPZrrk */ }, { /* 7922 */ 426, /* VMOVSHDUPZrrkz */ }, { /* 7923 */ 30, /* VMOVSHDUPrm */ }, { /* 7924 */ 31, /* VMOVSHDUPrr */ }, { /* 7925 */ 305, /* VMOVSLDUPYrm */ }, { /* 7926 */ 408, /* VMOVSLDUPYrr */ }, { /* 7927 */ 409, /* VMOVSLDUPZ128rm */ }, { /* 7928 */ 410, /* VMOVSLDUPZ128rmk */ }, { /* 7929 */ 411, /* VMOVSLDUPZ128rmkz */ }, { /* 7930 */ 330, /* VMOVSLDUPZ128rr */ }, { /* 7931 */ 331, /* VMOVSLDUPZ128rrk */ }, { /* 7932 */ 332, /* VMOVSLDUPZ128rrkz */ }, { /* 7933 */ 412, /* VMOVSLDUPZ256rm */ }, { /* 7934 */ 413, /* VMOVSLDUPZ256rmk */ }, { /* 7935 */ 414, /* VMOVSLDUPZ256rmkz */ }, { /* 7936 */ 415, /* VMOVSLDUPZ256rr */ }, { /* 7937 */ 416, /* VMOVSLDUPZ256rrk */ }, { /* 7938 */ 417, /* VMOVSLDUPZ256rrkz */ }, { /* 7939 */ 418, /* VMOVSLDUPZrm */ }, { /* 7940 */ 419, /* VMOVSLDUPZrmk */ }, { /* 7941 */ 420, /* VMOVSLDUPZrmkz */ }, { /* 7942 */ 421, /* VMOVSLDUPZrr */ }, { /* 7943 */ 425, /* VMOVSLDUPZrrk */ }, { /* 7944 */ 426, /* VMOVSLDUPZrrkz */ }, { /* 7945 */ 30, /* VMOVSLDUPrm */ }, { /* 7946 */ 31, /* VMOVSLDUPrr */ }, { /* 7947 */ 0, /* */ }, { /* 7948 */ 0, /* */ }, { /* 7949 */ 0, /* */ }, { /* 7950 */ 0, /* */ }, { /* 7951 */ 394, /* VMOVSSZmr */ }, { /* 7952 */ 395, /* VMOVSSZmrk */ }, { /* 7953 */ 334, /* VMOVSSZrm */ }, { /* 7954 */ 335, /* VMOVSSZrmk */ }, { /* 7955 */ 336, /* VMOVSSZrmkz */ }, { /* 7956 */ 255, /* VMOVSSZrr */ }, { /* 7957 */ 682, /* VMOVSSZrr_REV */ }, { /* 7958 */ 256, /* VMOVSSZrrk */ }, { /* 7959 */ 683, /* VMOVSSZrrk_REV */ }, { /* 7960 */ 257, /* VMOVSSZrrkz */ }, { /* 7961 */ 684, /* VMOVSSZrrkz_REV */ }, { /* 7962 */ 169, /* VMOVSSmr */ }, { /* 7963 */ 30, /* VMOVSSrm */ }, { /* 7964 */ 236, /* VMOVSSrr */ }, { /* 7965 */ 685, /* VMOVSSrr_REV */ }, { /* 7966 */ 670, /* VMOVUPDYmr */ }, { /* 7967 */ 305, /* VMOVUPDYrm */ }, { /* 7968 */ 408, /* VMOVUPDYrr */ }, { /* 7969 */ 671, /* VMOVUPDYrr_REV */ }, { /* 7970 */ 672, /* VMOVUPDZ128mr */ }, { /* 7971 */ 673, /* VMOVUPDZ128mrk */ }, { /* 7972 */ 409, /* VMOVUPDZ128rm */ }, { /* 7973 */ 410, /* VMOVUPDZ128rmk */ }, { /* 7974 */ 411, /* VMOVUPDZ128rmkz */ }, { /* 7975 */ 330, /* VMOVUPDZ128rr */ }, { /* 7976 */ 381, /* VMOVUPDZ128rr_REV */ }, { /* 7977 */ 331, /* VMOVUPDZ128rrk */ }, { /* 7978 */ 383, /* VMOVUPDZ128rrk_REV */ }, { /* 7979 */ 332, /* VMOVUPDZ128rrkz */ }, { /* 7980 */ 383, /* VMOVUPDZ128rrkz_REV */ }, { /* 7981 */ 674, /* VMOVUPDZ256mr */ }, { /* 7982 */ 675, /* VMOVUPDZ256mrk */ }, { /* 7983 */ 412, /* VMOVUPDZ256rm */ }, { /* 7984 */ 413, /* VMOVUPDZ256rmk */ }, { /* 7985 */ 414, /* VMOVUPDZ256rmkz */ }, { /* 7986 */ 415, /* VMOVUPDZ256rr */ }, { /* 7987 */ 386, /* VMOVUPDZ256rr_REV */ }, { /* 7988 */ 416, /* VMOVUPDZ256rrk */ }, { /* 7989 */ 388, /* VMOVUPDZ256rrk_REV */ }, { /* 7990 */ 417, /* VMOVUPDZ256rrkz */ }, { /* 7991 */ 388, /* VMOVUPDZ256rrkz_REV */ }, { /* 7992 */ 676, /* VMOVUPDZmr */ }, { /* 7993 */ 677, /* VMOVUPDZmrk */ }, { /* 7994 */ 418, /* VMOVUPDZrm */ }, { /* 7995 */ 419, /* VMOVUPDZrmk */ }, { /* 7996 */ 420, /* VMOVUPDZrmkz */ }, { /* 7997 */ 421, /* VMOVUPDZrr */ }, { /* 7998 */ 391, /* VMOVUPDZrr_REV */ }, { /* 7999 */ 425, /* VMOVUPDZrrk */ }, { /* 8000 */ 393, /* VMOVUPDZrrk_REV */ }, { /* 8001 */ 426, /* VMOVUPDZrrkz */ }, { /* 8002 */ 393, /* VMOVUPDZrrkz_REV */ }, { /* 8003 */ 169, /* VMOVUPDmr */ }, { /* 8004 */ 30, /* VMOVUPDrm */ }, { /* 8005 */ 31, /* VMOVUPDrr */ }, { /* 8006 */ 170, /* VMOVUPDrr_REV */ }, { /* 8007 */ 670, /* VMOVUPSYmr */ }, { /* 8008 */ 305, /* VMOVUPSYrm */ }, { /* 8009 */ 408, /* VMOVUPSYrr */ }, { /* 8010 */ 671, /* VMOVUPSYrr_REV */ }, { /* 8011 */ 672, /* VMOVUPSZ128mr */ }, { /* 8012 */ 673, /* VMOVUPSZ128mrk */ }, { /* 8013 */ 409, /* VMOVUPSZ128rm */ }, { /* 8014 */ 410, /* VMOVUPSZ128rmk */ }, { /* 8015 */ 411, /* VMOVUPSZ128rmkz */ }, { /* 8016 */ 330, /* VMOVUPSZ128rr */ }, { /* 8017 */ 381, /* VMOVUPSZ128rr_REV */ }, { /* 8018 */ 331, /* VMOVUPSZ128rrk */ }, { /* 8019 */ 383, /* VMOVUPSZ128rrk_REV */ }, { /* 8020 */ 332, /* VMOVUPSZ128rrkz */ }, { /* 8021 */ 383, /* VMOVUPSZ128rrkz_REV */ }, { /* 8022 */ 674, /* VMOVUPSZ256mr */ }, { /* 8023 */ 675, /* VMOVUPSZ256mrk */ }, { /* 8024 */ 412, /* VMOVUPSZ256rm */ }, { /* 8025 */ 413, /* VMOVUPSZ256rmk */ }, { /* 8026 */ 414, /* VMOVUPSZ256rmkz */ }, { /* 8027 */ 415, /* VMOVUPSZ256rr */ }, { /* 8028 */ 386, /* VMOVUPSZ256rr_REV */ }, { /* 8029 */ 416, /* VMOVUPSZ256rrk */ }, { /* 8030 */ 388, /* VMOVUPSZ256rrk_REV */ }, { /* 8031 */ 417, /* VMOVUPSZ256rrkz */ }, { /* 8032 */ 388, /* VMOVUPSZ256rrkz_REV */ }, { /* 8033 */ 676, /* VMOVUPSZmr */ }, { /* 8034 */ 677, /* VMOVUPSZmrk */ }, { /* 8035 */ 418, /* VMOVUPSZrm */ }, { /* 8036 */ 419, /* VMOVUPSZrmk */ }, { /* 8037 */ 420, /* VMOVUPSZrmkz */ }, { /* 8038 */ 421, /* VMOVUPSZrr */ }, { /* 8039 */ 391, /* VMOVUPSZrr_REV */ }, { /* 8040 */ 425, /* VMOVUPSZrrk */ }, { /* 8041 */ 393, /* VMOVUPSZrrk_REV */ }, { /* 8042 */ 426, /* VMOVUPSZrrkz */ }, { /* 8043 */ 393, /* VMOVUPSZrrkz_REV */ }, { /* 8044 */ 169, /* VMOVUPSmr */ }, { /* 8045 */ 30, /* VMOVUPSrm */ }, { /* 8046 */ 31, /* VMOVUPSrr */ }, { /* 8047 */ 170, /* VMOVUPSrr_REV */ }, { /* 8048 */ 330, /* VMOVZPQILo2PQIZrr */ }, { /* 8049 */ 31, /* VMOVZPQILo2PQIrr */ }, { /* 8050 */ 297, /* VMPSADBWYrmi */ }, { /* 8051 */ 298, /* VMPSADBWYrri */ }, { /* 8052 */ 299, /* VMPSADBWrmi */ }, { /* 8053 */ 300, /* VMPSADBWrri */ }, { /* 8054 */ 28, /* VMPTRLDm */ }, { /* 8055 */ 28, /* VMPTRSTm */ }, { /* 8056 */ 172, /* VMREAD32mr */ }, { /* 8057 */ 686, /* VMREAD32rr */ }, { /* 8058 */ 13, /* VMREAD64mr */ }, { /* 8059 */ 69, /* VMREAD64rr */ }, { /* 8060 */ 0, /* VMRESUME */ }, { /* 8061 */ 0, /* VMRUN32 */ }, { /* 8062 */ 0, /* VMRUN64 */ }, { /* 8063 */ 0, /* VMSAVE32 */ }, { /* 8064 */ 0, /* VMSAVE64 */ }, { /* 8065 */ 204, /* VMULPDYrm */ }, { /* 8066 */ 205, /* VMULPDYrr */ }, { /* 8067 */ 206, /* VMULPDZ128rm */ }, { /* 8068 */ 207, /* VMULPDZ128rmb */ }, { /* 8069 */ 208, /* VMULPDZ128rmbk */ }, { /* 8070 */ 209, /* VMULPDZ128rmbkz */ }, { /* 8071 */ 203, /* VMULPDZ128rmk */ }, { /* 8072 */ 210, /* VMULPDZ128rmkz */ }, { /* 8073 */ 211, /* VMULPDZ128rr */ }, { /* 8074 */ 212, /* VMULPDZ128rrk */ }, { /* 8075 */ 213, /* VMULPDZ128rrkz */ }, { /* 8076 */ 214, /* VMULPDZ256rm */ }, { /* 8077 */ 215, /* VMULPDZ256rmb */ }, { /* 8078 */ 216, /* VMULPDZ256rmbk */ }, { /* 8079 */ 217, /* VMULPDZ256rmbkz */ }, { /* 8080 */ 218, /* VMULPDZ256rmk */ }, { /* 8081 */ 219, /* VMULPDZ256rmkz */ }, { /* 8082 */ 220, /* VMULPDZ256rr */ }, { /* 8083 */ 221, /* VMULPDZ256rrk */ }, { /* 8084 */ 222, /* VMULPDZ256rrkz */ }, { /* 8085 */ 223, /* VMULPDZrm */ }, { /* 8086 */ 224, /* VMULPDZrmb */ }, { /* 8087 */ 225, /* VMULPDZrmbk */ }, { /* 8088 */ 226, /* VMULPDZrmbkz */ }, { /* 8089 */ 227, /* VMULPDZrmk */ }, { /* 8090 */ 228, /* VMULPDZrmkz */ }, { /* 8091 */ 229, /* VMULPDZrr */ }, { /* 8092 */ 230, /* VMULPDZrrb */ }, { /* 8093 */ 231, /* VMULPDZrrbk */ }, { /* 8094 */ 232, /* VMULPDZrrbkz */ }, { /* 8095 */ 233, /* VMULPDZrrk */ }, { /* 8096 */ 234, /* VMULPDZrrkz */ }, { /* 8097 */ 235, /* VMULPDrm */ }, { /* 8098 */ 236, /* VMULPDrr */ }, { /* 8099 */ 204, /* VMULPSYrm */ }, { /* 8100 */ 205, /* VMULPSYrr */ }, { /* 8101 */ 206, /* VMULPSZ128rm */ }, { /* 8102 */ 237, /* VMULPSZ128rmb */ }, { /* 8103 */ 238, /* VMULPSZ128rmbk */ }, { /* 8104 */ 239, /* VMULPSZ128rmbkz */ }, { /* 8105 */ 203, /* VMULPSZ128rmk */ }, { /* 8106 */ 210, /* VMULPSZ128rmkz */ }, { /* 8107 */ 211, /* VMULPSZ128rr */ }, { /* 8108 */ 212, /* VMULPSZ128rrk */ }, { /* 8109 */ 213, /* VMULPSZ128rrkz */ }, { /* 8110 */ 214, /* VMULPSZ256rm */ }, { /* 8111 */ 240, /* VMULPSZ256rmb */ }, { /* 8112 */ 241, /* VMULPSZ256rmbk */ }, { /* 8113 */ 242, /* VMULPSZ256rmbkz */ }, { /* 8114 */ 218, /* VMULPSZ256rmk */ }, { /* 8115 */ 219, /* VMULPSZ256rmkz */ }, { /* 8116 */ 220, /* VMULPSZ256rr */ }, { /* 8117 */ 221, /* VMULPSZ256rrk */ }, { /* 8118 */ 222, /* VMULPSZ256rrkz */ }, { /* 8119 */ 223, /* VMULPSZrm */ }, { /* 8120 */ 243, /* VMULPSZrmb */ }, { /* 8121 */ 244, /* VMULPSZrmbk */ }, { /* 8122 */ 245, /* VMULPSZrmbkz */ }, { /* 8123 */ 227, /* VMULPSZrmk */ }, { /* 8124 */ 228, /* VMULPSZrmkz */ }, { /* 8125 */ 229, /* VMULPSZrr */ }, { /* 8126 */ 246, /* VMULPSZrrb */ }, { /* 8127 */ 247, /* VMULPSZrrbk */ }, { /* 8128 */ 248, /* VMULPSZrrbkz */ }, { /* 8129 */ 233, /* VMULPSZrrk */ }, { /* 8130 */ 234, /* VMULPSZrrkz */ }, { /* 8131 */ 235, /* VMULPSrm */ }, { /* 8132 */ 236, /* VMULPSrr */ }, { /* 8133 */ 0, /* */ }, { /* 8134 */ 207, /* VMULSDZrm_Int */ }, { /* 8135 */ 208, /* VMULSDZrm_Intk */ }, { /* 8136 */ 209, /* VMULSDZrm_Intkz */ }, { /* 8137 */ 0, /* */ }, { /* 8138 */ 249, /* VMULSDZrr_Int */ }, { /* 8139 */ 250, /* VMULSDZrr_Intk */ }, { /* 8140 */ 251, /* VMULSDZrr_Intkz */ }, { /* 8141 */ 252, /* VMULSDZrrb_Int */ }, { /* 8142 */ 253, /* VMULSDZrrb_Intk */ }, { /* 8143 */ 254, /* VMULSDZrrb_Intkz */ }, { /* 8144 */ 235, /* VMULSDrm */ }, { /* 8145 */ 0, /* */ }, { /* 8146 */ 236, /* VMULSDrr */ }, { /* 8147 */ 0, /* */ }, { /* 8148 */ 0, /* */ }, { /* 8149 */ 237, /* VMULSSZrm_Int */ }, { /* 8150 */ 238, /* VMULSSZrm_Intk */ }, { /* 8151 */ 239, /* VMULSSZrm_Intkz */ }, { /* 8152 */ 0, /* */ }, { /* 8153 */ 255, /* VMULSSZrr_Int */ }, { /* 8154 */ 256, /* VMULSSZrr_Intk */ }, { /* 8155 */ 257, /* VMULSSZrr_Intkz */ }, { /* 8156 */ 258, /* VMULSSZrrb_Int */ }, { /* 8157 */ 259, /* VMULSSZrrb_Intk */ }, { /* 8158 */ 260, /* VMULSSZrrb_Intkz */ }, { /* 8159 */ 235, /* VMULSSrm */ }, { /* 8160 */ 0, /* */ }, { /* 8161 */ 236, /* VMULSSrr */ }, { /* 8162 */ 0, /* */ }, { /* 8163 */ 87, /* VMWRITE32rm */ }, { /* 8164 */ 687, /* VMWRITE32rr */ }, { /* 8165 */ 62, /* VMWRITE64rm */ }, { /* 8166 */ 63, /* VMWRITE64rr */ }, { /* 8167 */ 0, /* VMXOFF */ }, { /* 8168 */ 28, /* VMXON */ }, { /* 8169 */ 204, /* VORPDYrm */ }, { /* 8170 */ 205, /* VORPDYrr */ }, { /* 8171 */ 206, /* VORPDZ128rm */ }, { /* 8172 */ 207, /* VORPDZ128rmb */ }, { /* 8173 */ 208, /* VORPDZ128rmbk */ }, { /* 8174 */ 209, /* VORPDZ128rmbkz */ }, { /* 8175 */ 203, /* VORPDZ128rmk */ }, { /* 8176 */ 210, /* VORPDZ128rmkz */ }, { /* 8177 */ 211, /* VORPDZ128rr */ }, { /* 8178 */ 212, /* VORPDZ128rrk */ }, { /* 8179 */ 213, /* VORPDZ128rrkz */ }, { /* 8180 */ 214, /* VORPDZ256rm */ }, { /* 8181 */ 215, /* VORPDZ256rmb */ }, { /* 8182 */ 216, /* VORPDZ256rmbk */ }, { /* 8183 */ 217, /* VORPDZ256rmbkz */ }, { /* 8184 */ 218, /* VORPDZ256rmk */ }, { /* 8185 */ 219, /* VORPDZ256rmkz */ }, { /* 8186 */ 220, /* VORPDZ256rr */ }, { /* 8187 */ 221, /* VORPDZ256rrk */ }, { /* 8188 */ 222, /* VORPDZ256rrkz */ }, { /* 8189 */ 223, /* VORPDZrm */ }, { /* 8190 */ 224, /* VORPDZrmb */ }, { /* 8191 */ 225, /* VORPDZrmbk */ }, { /* 8192 */ 226, /* VORPDZrmbkz */ }, { /* 8193 */ 227, /* VORPDZrmk */ }, { /* 8194 */ 228, /* VORPDZrmkz */ }, { /* 8195 */ 229, /* VORPDZrr */ }, { /* 8196 */ 233, /* VORPDZrrk */ }, { /* 8197 */ 234, /* VORPDZrrkz */ }, { /* 8198 */ 235, /* VORPDrm */ }, { /* 8199 */ 236, /* VORPDrr */ }, { /* 8200 */ 204, /* VORPSYrm */ }, { /* 8201 */ 205, /* VORPSYrr */ }, { /* 8202 */ 206, /* VORPSZ128rm */ }, { /* 8203 */ 237, /* VORPSZ128rmb */ }, { /* 8204 */ 238, /* VORPSZ128rmbk */ }, { /* 8205 */ 239, /* VORPSZ128rmbkz */ }, { /* 8206 */ 203, /* VORPSZ128rmk */ }, { /* 8207 */ 210, /* VORPSZ128rmkz */ }, { /* 8208 */ 211, /* VORPSZ128rr */ }, { /* 8209 */ 212, /* VORPSZ128rrk */ }, { /* 8210 */ 213, /* VORPSZ128rrkz */ }, { /* 8211 */ 214, /* VORPSZ256rm */ }, { /* 8212 */ 240, /* VORPSZ256rmb */ }, { /* 8213 */ 241, /* VORPSZ256rmbk */ }, { /* 8214 */ 242, /* VORPSZ256rmbkz */ }, { /* 8215 */ 218, /* VORPSZ256rmk */ }, { /* 8216 */ 219, /* VORPSZ256rmkz */ }, { /* 8217 */ 220, /* VORPSZ256rr */ }, { /* 8218 */ 221, /* VORPSZ256rrk */ }, { /* 8219 */ 222, /* VORPSZ256rrkz */ }, { /* 8220 */ 223, /* VORPSZrm */ }, { /* 8221 */ 243, /* VORPSZrmb */ }, { /* 8222 */ 244, /* VORPSZrmbk */ }, { /* 8223 */ 245, /* VORPSZrmbkz */ }, { /* 8224 */ 227, /* VORPSZrmk */ }, { /* 8225 */ 228, /* VORPSZrmkz */ }, { /* 8226 */ 229, /* VORPSZrr */ }, { /* 8227 */ 233, /* VORPSZrrk */ }, { /* 8228 */ 234, /* VORPSZrrkz */ }, { /* 8229 */ 235, /* VORPSrm */ }, { /* 8230 */ 236, /* VORPSrr */ }, { /* 8231 */ 200, /* VP4DPWSSDSrm */ }, { /* 8232 */ 201, /* VP4DPWSSDSrmk */ }, { /* 8233 */ 201, /* VP4DPWSSDSrmkz */ }, { /* 8234 */ 200, /* VP4DPWSSDrm */ }, { /* 8235 */ 201, /* VP4DPWSSDrmk */ }, { /* 8236 */ 201, /* VP4DPWSSDrmkz */ }, { /* 8237 */ 305, /* VPABSBYrm */ }, { /* 8238 */ 408, /* VPABSBYrr */ }, { /* 8239 */ 409, /* VPABSBZ128rm */ }, { /* 8240 */ 410, /* VPABSBZ128rmk */ }, { /* 8241 */ 411, /* VPABSBZ128rmkz */ }, { /* 8242 */ 330, /* VPABSBZ128rr */ }, { /* 8243 */ 331, /* VPABSBZ128rrk */ }, { /* 8244 */ 332, /* VPABSBZ128rrkz */ }, { /* 8245 */ 412, /* VPABSBZ256rm */ }, { /* 8246 */ 413, /* VPABSBZ256rmk */ }, { /* 8247 */ 414, /* VPABSBZ256rmkz */ }, { /* 8248 */ 415, /* VPABSBZ256rr */ }, { /* 8249 */ 416, /* VPABSBZ256rrk */ }, { /* 8250 */ 417, /* VPABSBZ256rrkz */ }, { /* 8251 */ 418, /* VPABSBZrm */ }, { /* 8252 */ 419, /* VPABSBZrmk */ }, { /* 8253 */ 420, /* VPABSBZrmkz */ }, { /* 8254 */ 421, /* VPABSBZrr */ }, { /* 8255 */ 425, /* VPABSBZrrk */ }, { /* 8256 */ 426, /* VPABSBZrrkz */ }, { /* 8257 */ 30, /* VPABSBrm */ }, { /* 8258 */ 31, /* VPABSBrr */ }, { /* 8259 */ 305, /* VPABSDYrm */ }, { /* 8260 */ 408, /* VPABSDYrr */ }, { /* 8261 */ 409, /* VPABSDZ128rm */ }, { /* 8262 */ 334, /* VPABSDZ128rmb */ }, { /* 8263 */ 335, /* VPABSDZ128rmbk */ }, { /* 8264 */ 336, /* VPABSDZ128rmbkz */ }, { /* 8265 */ 410, /* VPABSDZ128rmk */ }, { /* 8266 */ 411, /* VPABSDZ128rmkz */ }, { /* 8267 */ 330, /* VPABSDZ128rr */ }, { /* 8268 */ 331, /* VPABSDZ128rrk */ }, { /* 8269 */ 332, /* VPABSDZ128rrkz */ }, { /* 8270 */ 412, /* VPABSDZ256rm */ }, { /* 8271 */ 337, /* VPABSDZ256rmb */ }, { /* 8272 */ 338, /* VPABSDZ256rmbk */ }, { /* 8273 */ 339, /* VPABSDZ256rmbkz */ }, { /* 8274 */ 413, /* VPABSDZ256rmk */ }, { /* 8275 */ 414, /* VPABSDZ256rmkz */ }, { /* 8276 */ 415, /* VPABSDZ256rr */ }, { /* 8277 */ 416, /* VPABSDZ256rrk */ }, { /* 8278 */ 417, /* VPABSDZ256rrkz */ }, { /* 8279 */ 418, /* VPABSDZrm */ }, { /* 8280 */ 340, /* VPABSDZrmb */ }, { /* 8281 */ 341, /* VPABSDZrmbk */ }, { /* 8282 */ 342, /* VPABSDZrmbkz */ }, { /* 8283 */ 419, /* VPABSDZrmk */ }, { /* 8284 */ 420, /* VPABSDZrmkz */ }, { /* 8285 */ 421, /* VPABSDZrr */ }, { /* 8286 */ 425, /* VPABSDZrrk */ }, { /* 8287 */ 426, /* VPABSDZrrkz */ }, { /* 8288 */ 30, /* VPABSDrm */ }, { /* 8289 */ 31, /* VPABSDrr */ }, { /* 8290 */ 409, /* VPABSQZ128rm */ }, { /* 8291 */ 327, /* VPABSQZ128rmb */ }, { /* 8292 */ 328, /* VPABSQZ128rmbk */ }, { /* 8293 */ 329, /* VPABSQZ128rmbkz */ }, { /* 8294 */ 410, /* VPABSQZ128rmk */ }, { /* 8295 */ 411, /* VPABSQZ128rmkz */ }, { /* 8296 */ 330, /* VPABSQZ128rr */ }, { /* 8297 */ 331, /* VPABSQZ128rrk */ }, { /* 8298 */ 332, /* VPABSQZ128rrkz */ }, { /* 8299 */ 412, /* VPABSQZ256rm */ }, { /* 8300 */ 306, /* VPABSQZ256rmb */ }, { /* 8301 */ 307, /* VPABSQZ256rmbk */ }, { /* 8302 */ 308, /* VPABSQZ256rmbkz */ }, { /* 8303 */ 413, /* VPABSQZ256rmk */ }, { /* 8304 */ 414, /* VPABSQZ256rmkz */ }, { /* 8305 */ 415, /* VPABSQZ256rr */ }, { /* 8306 */ 416, /* VPABSQZ256rrk */ }, { /* 8307 */ 417, /* VPABSQZ256rrkz */ }, { /* 8308 */ 418, /* VPABSQZrm */ }, { /* 8309 */ 312, /* VPABSQZrmb */ }, { /* 8310 */ 313, /* VPABSQZrmbk */ }, { /* 8311 */ 314, /* VPABSQZrmbkz */ }, { /* 8312 */ 419, /* VPABSQZrmk */ }, { /* 8313 */ 420, /* VPABSQZrmkz */ }, { /* 8314 */ 421, /* VPABSQZrr */ }, { /* 8315 */ 425, /* VPABSQZrrk */ }, { /* 8316 */ 426, /* VPABSQZrrkz */ }, { /* 8317 */ 305, /* VPABSWYrm */ }, { /* 8318 */ 408, /* VPABSWYrr */ }, { /* 8319 */ 409, /* VPABSWZ128rm */ }, { /* 8320 */ 410, /* VPABSWZ128rmk */ }, { /* 8321 */ 411, /* VPABSWZ128rmkz */ }, { /* 8322 */ 330, /* VPABSWZ128rr */ }, { /* 8323 */ 331, /* VPABSWZ128rrk */ }, { /* 8324 */ 332, /* VPABSWZ128rrkz */ }, { /* 8325 */ 412, /* VPABSWZ256rm */ }, { /* 8326 */ 413, /* VPABSWZ256rmk */ }, { /* 8327 */ 414, /* VPABSWZ256rmkz */ }, { /* 8328 */ 415, /* VPABSWZ256rr */ }, { /* 8329 */ 416, /* VPABSWZ256rrk */ }, { /* 8330 */ 417, /* VPABSWZ256rrkz */ }, { /* 8331 */ 418, /* VPABSWZrm */ }, { /* 8332 */ 419, /* VPABSWZrmk */ }, { /* 8333 */ 420, /* VPABSWZrmkz */ }, { /* 8334 */ 421, /* VPABSWZrr */ }, { /* 8335 */ 425, /* VPABSWZrrk */ }, { /* 8336 */ 426, /* VPABSWZrrkz */ }, { /* 8337 */ 30, /* VPABSWrm */ }, { /* 8338 */ 31, /* VPABSWrr */ }, { /* 8339 */ 204, /* VPACKSSDWYrm */ }, { /* 8340 */ 205, /* VPACKSSDWYrr */ }, { /* 8341 */ 206, /* VPACKSSDWZ128rm */ }, { /* 8342 */ 237, /* VPACKSSDWZ128rmb */ }, { /* 8343 */ 238, /* VPACKSSDWZ128rmbk */ }, { /* 8344 */ 239, /* VPACKSSDWZ128rmbkz */ }, { /* 8345 */ 203, /* VPACKSSDWZ128rmk */ }, { /* 8346 */ 210, /* VPACKSSDWZ128rmkz */ }, { /* 8347 */ 211, /* VPACKSSDWZ128rr */ }, { /* 8348 */ 212, /* VPACKSSDWZ128rrk */ }, { /* 8349 */ 213, /* VPACKSSDWZ128rrkz */ }, { /* 8350 */ 214, /* VPACKSSDWZ256rm */ }, { /* 8351 */ 240, /* VPACKSSDWZ256rmb */ }, { /* 8352 */ 241, /* VPACKSSDWZ256rmbk */ }, { /* 8353 */ 242, /* VPACKSSDWZ256rmbkz */ }, { /* 8354 */ 218, /* VPACKSSDWZ256rmk */ }, { /* 8355 */ 219, /* VPACKSSDWZ256rmkz */ }, { /* 8356 */ 220, /* VPACKSSDWZ256rr */ }, { /* 8357 */ 221, /* VPACKSSDWZ256rrk */ }, { /* 8358 */ 222, /* VPACKSSDWZ256rrkz */ }, { /* 8359 */ 223, /* VPACKSSDWZrm */ }, { /* 8360 */ 243, /* VPACKSSDWZrmb */ }, { /* 8361 */ 244, /* VPACKSSDWZrmbk */ }, { /* 8362 */ 245, /* VPACKSSDWZrmbkz */ }, { /* 8363 */ 227, /* VPACKSSDWZrmk */ }, { /* 8364 */ 228, /* VPACKSSDWZrmkz */ }, { /* 8365 */ 229, /* VPACKSSDWZrr */ }, { /* 8366 */ 233, /* VPACKSSDWZrrk */ }, { /* 8367 */ 234, /* VPACKSSDWZrrkz */ }, { /* 8368 */ 235, /* VPACKSSDWrm */ }, { /* 8369 */ 236, /* VPACKSSDWrr */ }, { /* 8370 */ 204, /* VPACKSSWBYrm */ }, { /* 8371 */ 205, /* VPACKSSWBYrr */ }, { /* 8372 */ 206, /* VPACKSSWBZ128rm */ }, { /* 8373 */ 203, /* VPACKSSWBZ128rmk */ }, { /* 8374 */ 210, /* VPACKSSWBZ128rmkz */ }, { /* 8375 */ 211, /* VPACKSSWBZ128rr */ }, { /* 8376 */ 212, /* VPACKSSWBZ128rrk */ }, { /* 8377 */ 213, /* VPACKSSWBZ128rrkz */ }, { /* 8378 */ 214, /* VPACKSSWBZ256rm */ }, { /* 8379 */ 218, /* VPACKSSWBZ256rmk */ }, { /* 8380 */ 219, /* VPACKSSWBZ256rmkz */ }, { /* 8381 */ 220, /* VPACKSSWBZ256rr */ }, { /* 8382 */ 221, /* VPACKSSWBZ256rrk */ }, { /* 8383 */ 222, /* VPACKSSWBZ256rrkz */ }, { /* 8384 */ 223, /* VPACKSSWBZrm */ }, { /* 8385 */ 227, /* VPACKSSWBZrmk */ }, { /* 8386 */ 228, /* VPACKSSWBZrmkz */ }, { /* 8387 */ 229, /* VPACKSSWBZrr */ }, { /* 8388 */ 233, /* VPACKSSWBZrrk */ }, { /* 8389 */ 234, /* VPACKSSWBZrrkz */ }, { /* 8390 */ 235, /* VPACKSSWBrm */ }, { /* 8391 */ 236, /* VPACKSSWBrr */ }, { /* 8392 */ 204, /* VPACKUSDWYrm */ }, { /* 8393 */ 205, /* VPACKUSDWYrr */ }, { /* 8394 */ 206, /* VPACKUSDWZ128rm */ }, { /* 8395 */ 237, /* VPACKUSDWZ128rmb */ }, { /* 8396 */ 238, /* VPACKUSDWZ128rmbk */ }, { /* 8397 */ 239, /* VPACKUSDWZ128rmbkz */ }, { /* 8398 */ 203, /* VPACKUSDWZ128rmk */ }, { /* 8399 */ 210, /* VPACKUSDWZ128rmkz */ }, { /* 8400 */ 211, /* VPACKUSDWZ128rr */ }, { /* 8401 */ 212, /* VPACKUSDWZ128rrk */ }, { /* 8402 */ 213, /* VPACKUSDWZ128rrkz */ }, { /* 8403 */ 214, /* VPACKUSDWZ256rm */ }, { /* 8404 */ 240, /* VPACKUSDWZ256rmb */ }, { /* 8405 */ 241, /* VPACKUSDWZ256rmbk */ }, { /* 8406 */ 242, /* VPACKUSDWZ256rmbkz */ }, { /* 8407 */ 218, /* VPACKUSDWZ256rmk */ }, { /* 8408 */ 219, /* VPACKUSDWZ256rmkz */ }, { /* 8409 */ 220, /* VPACKUSDWZ256rr */ }, { /* 8410 */ 221, /* VPACKUSDWZ256rrk */ }, { /* 8411 */ 222, /* VPACKUSDWZ256rrkz */ }, { /* 8412 */ 223, /* VPACKUSDWZrm */ }, { /* 8413 */ 243, /* VPACKUSDWZrmb */ }, { /* 8414 */ 244, /* VPACKUSDWZrmbk */ }, { /* 8415 */ 245, /* VPACKUSDWZrmbkz */ }, { /* 8416 */ 227, /* VPACKUSDWZrmk */ }, { /* 8417 */ 228, /* VPACKUSDWZrmkz */ }, { /* 8418 */ 229, /* VPACKUSDWZrr */ }, { /* 8419 */ 233, /* VPACKUSDWZrrk */ }, { /* 8420 */ 234, /* VPACKUSDWZrrkz */ }, { /* 8421 */ 235, /* VPACKUSDWrm */ }, { /* 8422 */ 236, /* VPACKUSDWrr */ }, { /* 8423 */ 204, /* VPACKUSWBYrm */ }, { /* 8424 */ 205, /* VPACKUSWBYrr */ }, { /* 8425 */ 206, /* VPACKUSWBZ128rm */ }, { /* 8426 */ 203, /* VPACKUSWBZ128rmk */ }, { /* 8427 */ 210, /* VPACKUSWBZ128rmkz */ }, { /* 8428 */ 211, /* VPACKUSWBZ128rr */ }, { /* 8429 */ 212, /* VPACKUSWBZ128rrk */ }, { /* 8430 */ 213, /* VPACKUSWBZ128rrkz */ }, { /* 8431 */ 214, /* VPACKUSWBZ256rm */ }, { /* 8432 */ 218, /* VPACKUSWBZ256rmk */ }, { /* 8433 */ 219, /* VPACKUSWBZ256rmkz */ }, { /* 8434 */ 220, /* VPACKUSWBZ256rr */ }, { /* 8435 */ 221, /* VPACKUSWBZ256rrk */ }, { /* 8436 */ 222, /* VPACKUSWBZ256rrkz */ }, { /* 8437 */ 223, /* VPACKUSWBZrm */ }, { /* 8438 */ 227, /* VPACKUSWBZrmk */ }, { /* 8439 */ 228, /* VPACKUSWBZrmkz */ }, { /* 8440 */ 229, /* VPACKUSWBZrr */ }, { /* 8441 */ 233, /* VPACKUSWBZrrk */ }, { /* 8442 */ 234, /* VPACKUSWBZrrkz */ }, { /* 8443 */ 235, /* VPACKUSWBrm */ }, { /* 8444 */ 236, /* VPACKUSWBrr */ }, { /* 8445 */ 204, /* VPADDBYrm */ }, { /* 8446 */ 205, /* VPADDBYrr */ }, { /* 8447 */ 206, /* VPADDBZ128rm */ }, { /* 8448 */ 203, /* VPADDBZ128rmk */ }, { /* 8449 */ 210, /* VPADDBZ128rmkz */ }, { /* 8450 */ 211, /* VPADDBZ128rr */ }, { /* 8451 */ 212, /* VPADDBZ128rrk */ }, { /* 8452 */ 213, /* VPADDBZ128rrkz */ }, { /* 8453 */ 214, /* VPADDBZ256rm */ }, { /* 8454 */ 218, /* VPADDBZ256rmk */ }, { /* 8455 */ 219, /* VPADDBZ256rmkz */ }, { /* 8456 */ 220, /* VPADDBZ256rr */ }, { /* 8457 */ 221, /* VPADDBZ256rrk */ }, { /* 8458 */ 222, /* VPADDBZ256rrkz */ }, { /* 8459 */ 223, /* VPADDBZrm */ }, { /* 8460 */ 227, /* VPADDBZrmk */ }, { /* 8461 */ 228, /* VPADDBZrmkz */ }, { /* 8462 */ 229, /* VPADDBZrr */ }, { /* 8463 */ 233, /* VPADDBZrrk */ }, { /* 8464 */ 234, /* VPADDBZrrkz */ }, { /* 8465 */ 235, /* VPADDBrm */ }, { /* 8466 */ 236, /* VPADDBrr */ }, { /* 8467 */ 204, /* VPADDDYrm */ }, { /* 8468 */ 205, /* VPADDDYrr */ }, { /* 8469 */ 206, /* VPADDDZ128rm */ }, { /* 8470 */ 237, /* VPADDDZ128rmb */ }, { /* 8471 */ 238, /* VPADDDZ128rmbk */ }, { /* 8472 */ 239, /* VPADDDZ128rmbkz */ }, { /* 8473 */ 203, /* VPADDDZ128rmk */ }, { /* 8474 */ 210, /* VPADDDZ128rmkz */ }, { /* 8475 */ 211, /* VPADDDZ128rr */ }, { /* 8476 */ 212, /* VPADDDZ128rrk */ }, { /* 8477 */ 213, /* VPADDDZ128rrkz */ }, { /* 8478 */ 214, /* VPADDDZ256rm */ }, { /* 8479 */ 240, /* VPADDDZ256rmb */ }, { /* 8480 */ 241, /* VPADDDZ256rmbk */ }, { /* 8481 */ 242, /* VPADDDZ256rmbkz */ }, { /* 8482 */ 218, /* VPADDDZ256rmk */ }, { /* 8483 */ 219, /* VPADDDZ256rmkz */ }, { /* 8484 */ 220, /* VPADDDZ256rr */ }, { /* 8485 */ 221, /* VPADDDZ256rrk */ }, { /* 8486 */ 222, /* VPADDDZ256rrkz */ }, { /* 8487 */ 223, /* VPADDDZrm */ }, { /* 8488 */ 243, /* VPADDDZrmb */ }, { /* 8489 */ 244, /* VPADDDZrmbk */ }, { /* 8490 */ 245, /* VPADDDZrmbkz */ }, { /* 8491 */ 227, /* VPADDDZrmk */ }, { /* 8492 */ 228, /* VPADDDZrmkz */ }, { /* 8493 */ 229, /* VPADDDZrr */ }, { /* 8494 */ 233, /* VPADDDZrrk */ }, { /* 8495 */ 234, /* VPADDDZrrkz */ }, { /* 8496 */ 235, /* VPADDDrm */ }, { /* 8497 */ 236, /* VPADDDrr */ }, { /* 8498 */ 204, /* VPADDQYrm */ }, { /* 8499 */ 205, /* VPADDQYrr */ }, { /* 8500 */ 206, /* VPADDQZ128rm */ }, { /* 8501 */ 207, /* VPADDQZ128rmb */ }, { /* 8502 */ 208, /* VPADDQZ128rmbk */ }, { /* 8503 */ 209, /* VPADDQZ128rmbkz */ }, { /* 8504 */ 203, /* VPADDQZ128rmk */ }, { /* 8505 */ 210, /* VPADDQZ128rmkz */ }, { /* 8506 */ 211, /* VPADDQZ128rr */ }, { /* 8507 */ 212, /* VPADDQZ128rrk */ }, { /* 8508 */ 213, /* VPADDQZ128rrkz */ }, { /* 8509 */ 214, /* VPADDQZ256rm */ }, { /* 8510 */ 215, /* VPADDQZ256rmb */ }, { /* 8511 */ 216, /* VPADDQZ256rmbk */ }, { /* 8512 */ 217, /* VPADDQZ256rmbkz */ }, { /* 8513 */ 218, /* VPADDQZ256rmk */ }, { /* 8514 */ 219, /* VPADDQZ256rmkz */ }, { /* 8515 */ 220, /* VPADDQZ256rr */ }, { /* 8516 */ 221, /* VPADDQZ256rrk */ }, { /* 8517 */ 222, /* VPADDQZ256rrkz */ }, { /* 8518 */ 223, /* VPADDQZrm */ }, { /* 8519 */ 224, /* VPADDQZrmb */ }, { /* 8520 */ 225, /* VPADDQZrmbk */ }, { /* 8521 */ 226, /* VPADDQZrmbkz */ }, { /* 8522 */ 227, /* VPADDQZrmk */ }, { /* 8523 */ 228, /* VPADDQZrmkz */ }, { /* 8524 */ 229, /* VPADDQZrr */ }, { /* 8525 */ 233, /* VPADDQZrrk */ }, { /* 8526 */ 234, /* VPADDQZrrkz */ }, { /* 8527 */ 235, /* VPADDQrm */ }, { /* 8528 */ 236, /* VPADDQrr */ }, { /* 8529 */ 204, /* VPADDSBYrm */ }, { /* 8530 */ 205, /* VPADDSBYrr */ }, { /* 8531 */ 206, /* VPADDSBZ128rm */ }, { /* 8532 */ 203, /* VPADDSBZ128rmk */ }, { /* 8533 */ 210, /* VPADDSBZ128rmkz */ }, { /* 8534 */ 211, /* VPADDSBZ128rr */ }, { /* 8535 */ 212, /* VPADDSBZ128rrk */ }, { /* 8536 */ 213, /* VPADDSBZ128rrkz */ }, { /* 8537 */ 214, /* VPADDSBZ256rm */ }, { /* 8538 */ 218, /* VPADDSBZ256rmk */ }, { /* 8539 */ 219, /* VPADDSBZ256rmkz */ }, { /* 8540 */ 220, /* VPADDSBZ256rr */ }, { /* 8541 */ 221, /* VPADDSBZ256rrk */ }, { /* 8542 */ 222, /* VPADDSBZ256rrkz */ }, { /* 8543 */ 223, /* VPADDSBZrm */ }, { /* 8544 */ 227, /* VPADDSBZrmk */ }, { /* 8545 */ 228, /* VPADDSBZrmkz */ }, { /* 8546 */ 229, /* VPADDSBZrr */ }, { /* 8547 */ 233, /* VPADDSBZrrk */ }, { /* 8548 */ 234, /* VPADDSBZrrkz */ }, { /* 8549 */ 235, /* VPADDSBrm */ }, { /* 8550 */ 236, /* VPADDSBrr */ }, { /* 8551 */ 204, /* VPADDSWYrm */ }, { /* 8552 */ 205, /* VPADDSWYrr */ }, { /* 8553 */ 206, /* VPADDSWZ128rm */ }, { /* 8554 */ 203, /* VPADDSWZ128rmk */ }, { /* 8555 */ 210, /* VPADDSWZ128rmkz */ }, { /* 8556 */ 211, /* VPADDSWZ128rr */ }, { /* 8557 */ 212, /* VPADDSWZ128rrk */ }, { /* 8558 */ 213, /* VPADDSWZ128rrkz */ }, { /* 8559 */ 214, /* VPADDSWZ256rm */ }, { /* 8560 */ 218, /* VPADDSWZ256rmk */ }, { /* 8561 */ 219, /* VPADDSWZ256rmkz */ }, { /* 8562 */ 220, /* VPADDSWZ256rr */ }, { /* 8563 */ 221, /* VPADDSWZ256rrk */ }, { /* 8564 */ 222, /* VPADDSWZ256rrkz */ }, { /* 8565 */ 223, /* VPADDSWZrm */ }, { /* 8566 */ 227, /* VPADDSWZrmk */ }, { /* 8567 */ 228, /* VPADDSWZrmkz */ }, { /* 8568 */ 229, /* VPADDSWZrr */ }, { /* 8569 */ 233, /* VPADDSWZrrk */ }, { /* 8570 */ 234, /* VPADDSWZrrkz */ }, { /* 8571 */ 235, /* VPADDSWrm */ }, { /* 8572 */ 236, /* VPADDSWrr */ }, { /* 8573 */ 204, /* VPADDUSBYrm */ }, { /* 8574 */ 205, /* VPADDUSBYrr */ }, { /* 8575 */ 206, /* VPADDUSBZ128rm */ }, { /* 8576 */ 203, /* VPADDUSBZ128rmk */ }, { /* 8577 */ 210, /* VPADDUSBZ128rmkz */ }, { /* 8578 */ 211, /* VPADDUSBZ128rr */ }, { /* 8579 */ 212, /* VPADDUSBZ128rrk */ }, { /* 8580 */ 213, /* VPADDUSBZ128rrkz */ }, { /* 8581 */ 214, /* VPADDUSBZ256rm */ }, { /* 8582 */ 218, /* VPADDUSBZ256rmk */ }, { /* 8583 */ 219, /* VPADDUSBZ256rmkz */ }, { /* 8584 */ 220, /* VPADDUSBZ256rr */ }, { /* 8585 */ 221, /* VPADDUSBZ256rrk */ }, { /* 8586 */ 222, /* VPADDUSBZ256rrkz */ }, { /* 8587 */ 223, /* VPADDUSBZrm */ }, { /* 8588 */ 227, /* VPADDUSBZrmk */ }, { /* 8589 */ 228, /* VPADDUSBZrmkz */ }, { /* 8590 */ 229, /* VPADDUSBZrr */ }, { /* 8591 */ 233, /* VPADDUSBZrrk */ }, { /* 8592 */ 234, /* VPADDUSBZrrkz */ }, { /* 8593 */ 235, /* VPADDUSBrm */ }, { /* 8594 */ 236, /* VPADDUSBrr */ }, { /* 8595 */ 204, /* VPADDUSWYrm */ }, { /* 8596 */ 205, /* VPADDUSWYrr */ }, { /* 8597 */ 206, /* VPADDUSWZ128rm */ }, { /* 8598 */ 203, /* VPADDUSWZ128rmk */ }, { /* 8599 */ 210, /* VPADDUSWZ128rmkz */ }, { /* 8600 */ 211, /* VPADDUSWZ128rr */ }, { /* 8601 */ 212, /* VPADDUSWZ128rrk */ }, { /* 8602 */ 213, /* VPADDUSWZ128rrkz */ }, { /* 8603 */ 214, /* VPADDUSWZ256rm */ }, { /* 8604 */ 218, /* VPADDUSWZ256rmk */ }, { /* 8605 */ 219, /* VPADDUSWZ256rmkz */ }, { /* 8606 */ 220, /* VPADDUSWZ256rr */ }, { /* 8607 */ 221, /* VPADDUSWZ256rrk */ }, { /* 8608 */ 222, /* VPADDUSWZ256rrkz */ }, { /* 8609 */ 223, /* VPADDUSWZrm */ }, { /* 8610 */ 227, /* VPADDUSWZrmk */ }, { /* 8611 */ 228, /* VPADDUSWZrmkz */ }, { /* 8612 */ 229, /* VPADDUSWZrr */ }, { /* 8613 */ 233, /* VPADDUSWZrrk */ }, { /* 8614 */ 234, /* VPADDUSWZrrkz */ }, { /* 8615 */ 235, /* VPADDUSWrm */ }, { /* 8616 */ 236, /* VPADDUSWrr */ }, { /* 8617 */ 204, /* VPADDWYrm */ }, { /* 8618 */ 205, /* VPADDWYrr */ }, { /* 8619 */ 206, /* VPADDWZ128rm */ }, { /* 8620 */ 203, /* VPADDWZ128rmk */ }, { /* 8621 */ 210, /* VPADDWZ128rmkz */ }, { /* 8622 */ 211, /* VPADDWZ128rr */ }, { /* 8623 */ 212, /* VPADDWZ128rrk */ }, { /* 8624 */ 213, /* VPADDWZ128rrkz */ }, { /* 8625 */ 214, /* VPADDWZ256rm */ }, { /* 8626 */ 218, /* VPADDWZ256rmk */ }, { /* 8627 */ 219, /* VPADDWZ256rmkz */ }, { /* 8628 */ 220, /* VPADDWZ256rr */ }, { /* 8629 */ 221, /* VPADDWZ256rrk */ }, { /* 8630 */ 222, /* VPADDWZ256rrkz */ }, { /* 8631 */ 223, /* VPADDWZrm */ }, { /* 8632 */ 227, /* VPADDWZrmk */ }, { /* 8633 */ 228, /* VPADDWZrmkz */ }, { /* 8634 */ 229, /* VPADDWZrr */ }, { /* 8635 */ 233, /* VPADDWZrrk */ }, { /* 8636 */ 234, /* VPADDWZrrkz */ }, { /* 8637 */ 235, /* VPADDWrm */ }, { /* 8638 */ 236, /* VPADDWrr */ }, { /* 8639 */ 297, /* VPALIGNRYrmi */ }, { /* 8640 */ 298, /* VPALIGNRYrri */ }, { /* 8641 */ 264, /* VPALIGNRZ128rmi */ }, { /* 8642 */ 265, /* VPALIGNRZ128rmik */ }, { /* 8643 */ 266, /* VPALIGNRZ128rmikz */ }, { /* 8644 */ 267, /* VPALIGNRZ128rri */ }, { /* 8645 */ 268, /* VPALIGNRZ128rrik */ }, { /* 8646 */ 269, /* VPALIGNRZ128rrikz */ }, { /* 8647 */ 273, /* VPALIGNRZ256rmi */ }, { /* 8648 */ 274, /* VPALIGNRZ256rmik */ }, { /* 8649 */ 275, /* VPALIGNRZ256rmikz */ }, { /* 8650 */ 276, /* VPALIGNRZ256rri */ }, { /* 8651 */ 277, /* VPALIGNRZ256rrik */ }, { /* 8652 */ 278, /* VPALIGNRZ256rrikz */ }, { /* 8653 */ 282, /* VPALIGNRZrmi */ }, { /* 8654 */ 283, /* VPALIGNRZrmik */ }, { /* 8655 */ 284, /* VPALIGNRZrmikz */ }, { /* 8656 */ 285, /* VPALIGNRZrri */ }, { /* 8657 */ 286, /* VPALIGNRZrrik */ }, { /* 8658 */ 287, /* VPALIGNRZrrikz */ }, { /* 8659 */ 299, /* VPALIGNRrmi */ }, { /* 8660 */ 300, /* VPALIGNRrri */ }, { /* 8661 */ 206, /* VPANDDZ128rm */ }, { /* 8662 */ 237, /* VPANDDZ128rmb */ }, { /* 8663 */ 238, /* VPANDDZ128rmbk */ }, { /* 8664 */ 239, /* VPANDDZ128rmbkz */ }, { /* 8665 */ 203, /* VPANDDZ128rmk */ }, { /* 8666 */ 210, /* VPANDDZ128rmkz */ }, { /* 8667 */ 211, /* VPANDDZ128rr */ }, { /* 8668 */ 212, /* VPANDDZ128rrk */ }, { /* 8669 */ 213, /* VPANDDZ128rrkz */ }, { /* 8670 */ 214, /* VPANDDZ256rm */ }, { /* 8671 */ 240, /* VPANDDZ256rmb */ }, { /* 8672 */ 241, /* VPANDDZ256rmbk */ }, { /* 8673 */ 242, /* VPANDDZ256rmbkz */ }, { /* 8674 */ 218, /* VPANDDZ256rmk */ }, { /* 8675 */ 219, /* VPANDDZ256rmkz */ }, { /* 8676 */ 220, /* VPANDDZ256rr */ }, { /* 8677 */ 221, /* VPANDDZ256rrk */ }, { /* 8678 */ 222, /* VPANDDZ256rrkz */ }, { /* 8679 */ 223, /* VPANDDZrm */ }, { /* 8680 */ 243, /* VPANDDZrmb */ }, { /* 8681 */ 244, /* VPANDDZrmbk */ }, { /* 8682 */ 245, /* VPANDDZrmbkz */ }, { /* 8683 */ 227, /* VPANDDZrmk */ }, { /* 8684 */ 228, /* VPANDDZrmkz */ }, { /* 8685 */ 229, /* VPANDDZrr */ }, { /* 8686 */ 233, /* VPANDDZrrk */ }, { /* 8687 */ 234, /* VPANDDZrrkz */ }, { /* 8688 */ 206, /* VPANDNDZ128rm */ }, { /* 8689 */ 237, /* VPANDNDZ128rmb */ }, { /* 8690 */ 238, /* VPANDNDZ128rmbk */ }, { /* 8691 */ 239, /* VPANDNDZ128rmbkz */ }, { /* 8692 */ 203, /* VPANDNDZ128rmk */ }, { /* 8693 */ 210, /* VPANDNDZ128rmkz */ }, { /* 8694 */ 211, /* VPANDNDZ128rr */ }, { /* 8695 */ 212, /* VPANDNDZ128rrk */ }, { /* 8696 */ 213, /* VPANDNDZ128rrkz */ }, { /* 8697 */ 214, /* VPANDNDZ256rm */ }, { /* 8698 */ 240, /* VPANDNDZ256rmb */ }, { /* 8699 */ 241, /* VPANDNDZ256rmbk */ }, { /* 8700 */ 242, /* VPANDNDZ256rmbkz */ }, { /* 8701 */ 218, /* VPANDNDZ256rmk */ }, { /* 8702 */ 219, /* VPANDNDZ256rmkz */ }, { /* 8703 */ 220, /* VPANDNDZ256rr */ }, { /* 8704 */ 221, /* VPANDNDZ256rrk */ }, { /* 8705 */ 222, /* VPANDNDZ256rrkz */ }, { /* 8706 */ 223, /* VPANDNDZrm */ }, { /* 8707 */ 243, /* VPANDNDZrmb */ }, { /* 8708 */ 244, /* VPANDNDZrmbk */ }, { /* 8709 */ 245, /* VPANDNDZrmbkz */ }, { /* 8710 */ 227, /* VPANDNDZrmk */ }, { /* 8711 */ 228, /* VPANDNDZrmkz */ }, { /* 8712 */ 229, /* VPANDNDZrr */ }, { /* 8713 */ 233, /* VPANDNDZrrk */ }, { /* 8714 */ 234, /* VPANDNDZrrkz */ }, { /* 8715 */ 206, /* VPANDNQZ128rm */ }, { /* 8716 */ 207, /* VPANDNQZ128rmb */ }, { /* 8717 */ 208, /* VPANDNQZ128rmbk */ }, { /* 8718 */ 209, /* VPANDNQZ128rmbkz */ }, { /* 8719 */ 203, /* VPANDNQZ128rmk */ }, { /* 8720 */ 210, /* VPANDNQZ128rmkz */ }, { /* 8721 */ 211, /* VPANDNQZ128rr */ }, { /* 8722 */ 212, /* VPANDNQZ128rrk */ }, { /* 8723 */ 213, /* VPANDNQZ128rrkz */ }, { /* 8724 */ 214, /* VPANDNQZ256rm */ }, { /* 8725 */ 215, /* VPANDNQZ256rmb */ }, { /* 8726 */ 216, /* VPANDNQZ256rmbk */ }, { /* 8727 */ 217, /* VPANDNQZ256rmbkz */ }, { /* 8728 */ 218, /* VPANDNQZ256rmk */ }, { /* 8729 */ 219, /* VPANDNQZ256rmkz */ }, { /* 8730 */ 220, /* VPANDNQZ256rr */ }, { /* 8731 */ 221, /* VPANDNQZ256rrk */ }, { /* 8732 */ 222, /* VPANDNQZ256rrkz */ }, { /* 8733 */ 223, /* VPANDNQZrm */ }, { /* 8734 */ 224, /* VPANDNQZrmb */ }, { /* 8735 */ 225, /* VPANDNQZrmbk */ }, { /* 8736 */ 226, /* VPANDNQZrmbkz */ }, { /* 8737 */ 227, /* VPANDNQZrmk */ }, { /* 8738 */ 228, /* VPANDNQZrmkz */ }, { /* 8739 */ 229, /* VPANDNQZrr */ }, { /* 8740 */ 233, /* VPANDNQZrrk */ }, { /* 8741 */ 234, /* VPANDNQZrrkz */ }, { /* 8742 */ 204, /* VPANDNYrm */ }, { /* 8743 */ 205, /* VPANDNYrr */ }, { /* 8744 */ 235, /* VPANDNrm */ }, { /* 8745 */ 236, /* VPANDNrr */ }, { /* 8746 */ 206, /* VPANDQZ128rm */ }, { /* 8747 */ 207, /* VPANDQZ128rmb */ }, { /* 8748 */ 208, /* VPANDQZ128rmbk */ }, { /* 8749 */ 209, /* VPANDQZ128rmbkz */ }, { /* 8750 */ 203, /* VPANDQZ128rmk */ }, { /* 8751 */ 210, /* VPANDQZ128rmkz */ }, { /* 8752 */ 211, /* VPANDQZ128rr */ }, { /* 8753 */ 212, /* VPANDQZ128rrk */ }, { /* 8754 */ 213, /* VPANDQZ128rrkz */ }, { /* 8755 */ 214, /* VPANDQZ256rm */ }, { /* 8756 */ 215, /* VPANDQZ256rmb */ }, { /* 8757 */ 216, /* VPANDQZ256rmbk */ }, { /* 8758 */ 217, /* VPANDQZ256rmbkz */ }, { /* 8759 */ 218, /* VPANDQZ256rmk */ }, { /* 8760 */ 219, /* VPANDQZ256rmkz */ }, { /* 8761 */ 220, /* VPANDQZ256rr */ }, { /* 8762 */ 221, /* VPANDQZ256rrk */ }, { /* 8763 */ 222, /* VPANDQZ256rrkz */ }, { /* 8764 */ 223, /* VPANDQZrm */ }, { /* 8765 */ 224, /* VPANDQZrmb */ }, { /* 8766 */ 225, /* VPANDQZrmbk */ }, { /* 8767 */ 226, /* VPANDQZrmbkz */ }, { /* 8768 */ 227, /* VPANDQZrmk */ }, { /* 8769 */ 228, /* VPANDQZrmkz */ }, { /* 8770 */ 229, /* VPANDQZrr */ }, { /* 8771 */ 233, /* VPANDQZrrk */ }, { /* 8772 */ 234, /* VPANDQZrrkz */ }, { /* 8773 */ 204, /* VPANDYrm */ }, { /* 8774 */ 205, /* VPANDYrr */ }, { /* 8775 */ 235, /* VPANDrm */ }, { /* 8776 */ 236, /* VPANDrr */ }, { /* 8777 */ 204, /* VPAVGBYrm */ }, { /* 8778 */ 205, /* VPAVGBYrr */ }, { /* 8779 */ 206, /* VPAVGBZ128rm */ }, { /* 8780 */ 203, /* VPAVGBZ128rmk */ }, { /* 8781 */ 210, /* VPAVGBZ128rmkz */ }, { /* 8782 */ 211, /* VPAVGBZ128rr */ }, { /* 8783 */ 212, /* VPAVGBZ128rrk */ }, { /* 8784 */ 213, /* VPAVGBZ128rrkz */ }, { /* 8785 */ 214, /* VPAVGBZ256rm */ }, { /* 8786 */ 218, /* VPAVGBZ256rmk */ }, { /* 8787 */ 219, /* VPAVGBZ256rmkz */ }, { /* 8788 */ 220, /* VPAVGBZ256rr */ }, { /* 8789 */ 221, /* VPAVGBZ256rrk */ }, { /* 8790 */ 222, /* VPAVGBZ256rrkz */ }, { /* 8791 */ 223, /* VPAVGBZrm */ }, { /* 8792 */ 227, /* VPAVGBZrmk */ }, { /* 8793 */ 228, /* VPAVGBZrmkz */ }, { /* 8794 */ 229, /* VPAVGBZrr */ }, { /* 8795 */ 233, /* VPAVGBZrrk */ }, { /* 8796 */ 234, /* VPAVGBZrrkz */ }, { /* 8797 */ 235, /* VPAVGBrm */ }, { /* 8798 */ 236, /* VPAVGBrr */ }, { /* 8799 */ 204, /* VPAVGWYrm */ }, { /* 8800 */ 205, /* VPAVGWYrr */ }, { /* 8801 */ 206, /* VPAVGWZ128rm */ }, { /* 8802 */ 203, /* VPAVGWZ128rmk */ }, { /* 8803 */ 210, /* VPAVGWZ128rmkz */ }, { /* 8804 */ 211, /* VPAVGWZ128rr */ }, { /* 8805 */ 212, /* VPAVGWZ128rrk */ }, { /* 8806 */ 213, /* VPAVGWZ128rrkz */ }, { /* 8807 */ 214, /* VPAVGWZ256rm */ }, { /* 8808 */ 218, /* VPAVGWZ256rmk */ }, { /* 8809 */ 219, /* VPAVGWZ256rmkz */ }, { /* 8810 */ 220, /* VPAVGWZ256rr */ }, { /* 8811 */ 221, /* VPAVGWZ256rrk */ }, { /* 8812 */ 222, /* VPAVGWZ256rrkz */ }, { /* 8813 */ 223, /* VPAVGWZrm */ }, { /* 8814 */ 227, /* VPAVGWZrmk */ }, { /* 8815 */ 228, /* VPAVGWZrmkz */ }, { /* 8816 */ 229, /* VPAVGWZrr */ }, { /* 8817 */ 233, /* VPAVGWZrrk */ }, { /* 8818 */ 234, /* VPAVGWZrrkz */ }, { /* 8819 */ 235, /* VPAVGWrm */ }, { /* 8820 */ 236, /* VPAVGWrr */ }, { /* 8821 */ 297, /* VPBLENDDYrmi */ }, { /* 8822 */ 298, /* VPBLENDDYrri */ }, { /* 8823 */ 299, /* VPBLENDDrmi */ }, { /* 8824 */ 300, /* VPBLENDDrri */ }, { /* 8825 */ 206, /* VPBLENDMBZ128rm */ }, { /* 8826 */ 210, /* VPBLENDMBZ128rmk */ }, { /* 8827 */ 210, /* VPBLENDMBZ128rmkz */ }, { /* 8828 */ 211, /* VPBLENDMBZ128rr */ }, { /* 8829 */ 213, /* VPBLENDMBZ128rrk */ }, { /* 8830 */ 213, /* VPBLENDMBZ128rrkz */ }, { /* 8831 */ 214, /* VPBLENDMBZ256rm */ }, { /* 8832 */ 219, /* VPBLENDMBZ256rmk */ }, { /* 8833 */ 219, /* VPBLENDMBZ256rmkz */ }, { /* 8834 */ 220, /* VPBLENDMBZ256rr */ }, { /* 8835 */ 222, /* VPBLENDMBZ256rrk */ }, { /* 8836 */ 222, /* VPBLENDMBZ256rrkz */ }, { /* 8837 */ 223, /* VPBLENDMBZrm */ }, { /* 8838 */ 228, /* VPBLENDMBZrmk */ }, { /* 8839 */ 228, /* VPBLENDMBZrmkz */ }, { /* 8840 */ 229, /* VPBLENDMBZrr */ }, { /* 8841 */ 234, /* VPBLENDMBZrrk */ }, { /* 8842 */ 234, /* VPBLENDMBZrrkz */ }, { /* 8843 */ 206, /* VPBLENDMDZ128rm */ }, { /* 8844 */ 237, /* VPBLENDMDZ128rmb */ }, { /* 8845 */ 239, /* VPBLENDMDZ128rmbk */ }, { /* 8846 */ 239, /* VPBLENDMDZ128rmbkz */ }, { /* 8847 */ 210, /* VPBLENDMDZ128rmk */ }, { /* 8848 */ 210, /* VPBLENDMDZ128rmkz */ }, { /* 8849 */ 211, /* VPBLENDMDZ128rr */ }, { /* 8850 */ 213, /* VPBLENDMDZ128rrk */ }, { /* 8851 */ 213, /* VPBLENDMDZ128rrkz */ }, { /* 8852 */ 214, /* VPBLENDMDZ256rm */ }, { /* 8853 */ 240, /* VPBLENDMDZ256rmb */ }, { /* 8854 */ 242, /* VPBLENDMDZ256rmbk */ }, { /* 8855 */ 242, /* VPBLENDMDZ256rmbkz */ }, { /* 8856 */ 219, /* VPBLENDMDZ256rmk */ }, { /* 8857 */ 219, /* VPBLENDMDZ256rmkz */ }, { /* 8858 */ 220, /* VPBLENDMDZ256rr */ }, { /* 8859 */ 222, /* VPBLENDMDZ256rrk */ }, { /* 8860 */ 222, /* VPBLENDMDZ256rrkz */ }, { /* 8861 */ 223, /* VPBLENDMDZrm */ }, { /* 8862 */ 243, /* VPBLENDMDZrmb */ }, { /* 8863 */ 245, /* VPBLENDMDZrmbk */ }, { /* 8864 */ 245, /* VPBLENDMDZrmbkz */ }, { /* 8865 */ 228, /* VPBLENDMDZrmk */ }, { /* 8866 */ 228, /* VPBLENDMDZrmkz */ }, { /* 8867 */ 229, /* VPBLENDMDZrr */ }, { /* 8868 */ 234, /* VPBLENDMDZrrk */ }, { /* 8869 */ 234, /* VPBLENDMDZrrkz */ }, { /* 8870 */ 206, /* VPBLENDMQZ128rm */ }, { /* 8871 */ 207, /* VPBLENDMQZ128rmb */ }, { /* 8872 */ 209, /* VPBLENDMQZ128rmbk */ }, { /* 8873 */ 209, /* VPBLENDMQZ128rmbkz */ }, { /* 8874 */ 210, /* VPBLENDMQZ128rmk */ }, { /* 8875 */ 210, /* VPBLENDMQZ128rmkz */ }, { /* 8876 */ 211, /* VPBLENDMQZ128rr */ }, { /* 8877 */ 213, /* VPBLENDMQZ128rrk */ }, { /* 8878 */ 213, /* VPBLENDMQZ128rrkz */ }, { /* 8879 */ 214, /* VPBLENDMQZ256rm */ }, { /* 8880 */ 215, /* VPBLENDMQZ256rmb */ }, { /* 8881 */ 217, /* VPBLENDMQZ256rmbk */ }, { /* 8882 */ 217, /* VPBLENDMQZ256rmbkz */ }, { /* 8883 */ 219, /* VPBLENDMQZ256rmk */ }, { /* 8884 */ 219, /* VPBLENDMQZ256rmkz */ }, { /* 8885 */ 220, /* VPBLENDMQZ256rr */ }, { /* 8886 */ 222, /* VPBLENDMQZ256rrk */ }, { /* 8887 */ 222, /* VPBLENDMQZ256rrkz */ }, { /* 8888 */ 223, /* VPBLENDMQZrm */ }, { /* 8889 */ 224, /* VPBLENDMQZrmb */ }, { /* 8890 */ 226, /* VPBLENDMQZrmbk */ }, { /* 8891 */ 226, /* VPBLENDMQZrmbkz */ }, { /* 8892 */ 228, /* VPBLENDMQZrmk */ }, { /* 8893 */ 228, /* VPBLENDMQZrmkz */ }, { /* 8894 */ 229, /* VPBLENDMQZrr */ }, { /* 8895 */ 234, /* VPBLENDMQZrrk */ }, { /* 8896 */ 234, /* VPBLENDMQZrrkz */ }, { /* 8897 */ 206, /* VPBLENDMWZ128rm */ }, { /* 8898 */ 210, /* VPBLENDMWZ128rmk */ }, { /* 8899 */ 210, /* VPBLENDMWZ128rmkz */ }, { /* 8900 */ 211, /* VPBLENDMWZ128rr */ }, { /* 8901 */ 213, /* VPBLENDMWZ128rrk */ }, { /* 8902 */ 213, /* VPBLENDMWZ128rrkz */ }, { /* 8903 */ 214, /* VPBLENDMWZ256rm */ }, { /* 8904 */ 219, /* VPBLENDMWZ256rmk */ }, { /* 8905 */ 219, /* VPBLENDMWZ256rmkz */ }, { /* 8906 */ 220, /* VPBLENDMWZ256rr */ }, { /* 8907 */ 222, /* VPBLENDMWZ256rrk */ }, { /* 8908 */ 222, /* VPBLENDMWZ256rrkz */ }, { /* 8909 */ 223, /* VPBLENDMWZrm */ }, { /* 8910 */ 228, /* VPBLENDMWZrmk */ }, { /* 8911 */ 228, /* VPBLENDMWZrmkz */ }, { /* 8912 */ 229, /* VPBLENDMWZrr */ }, { /* 8913 */ 234, /* VPBLENDMWZrrk */ }, { /* 8914 */ 234, /* VPBLENDMWZrrkz */ }, { /* 8915 */ 301, /* VPBLENDVBYrm */ }, { /* 8916 */ 302, /* VPBLENDVBYrr */ }, { /* 8917 */ 303, /* VPBLENDVBrm */ }, { /* 8918 */ 304, /* VPBLENDVBrr */ }, { /* 8919 */ 297, /* VPBLENDWYrmi */ }, { /* 8920 */ 298, /* VPBLENDWYrri */ }, { /* 8921 */ 299, /* VPBLENDWrmi */ }, { /* 8922 */ 300, /* VPBLENDWrri */ }, { /* 8923 */ 305, /* VPBROADCASTBYrm */ }, { /* 8924 */ 333, /* VPBROADCASTBYrr */ }, { /* 8925 */ 30, /* VPBROADCASTBZ128m */ }, { /* 8926 */ 688, /* VPBROADCASTBZ128mk */ }, { /* 8927 */ 689, /* VPBROADCASTBZ128mkz */ }, { /* 8928 */ 330, /* VPBROADCASTBZ128r */ }, { /* 8929 */ 331, /* VPBROADCASTBZ128rk */ }, { /* 8930 */ 332, /* VPBROADCASTBZ128rkz */ }, { /* 8931 */ 305, /* VPBROADCASTBZ256m */ }, { /* 8932 */ 690, /* VPBROADCASTBZ256mk */ }, { /* 8933 */ 691, /* VPBROADCASTBZ256mkz */ }, { /* 8934 */ 309, /* VPBROADCASTBZ256r */ }, { /* 8935 */ 310, /* VPBROADCASTBZ256rk */ }, { /* 8936 */ 311, /* VPBROADCASTBZ256rkz */ }, { /* 8937 */ 692, /* VPBROADCASTBZm */ }, { /* 8938 */ 693, /* VPBROADCASTBZmk */ }, { /* 8939 */ 694, /* VPBROADCASTBZmkz */ }, { /* 8940 */ 315, /* VPBROADCASTBZr */ }, { /* 8941 */ 316, /* VPBROADCASTBZrk */ }, { /* 8942 */ 317, /* VPBROADCASTBZrkz */ }, { /* 8943 */ 678, /* VPBROADCASTBrZ128r */ }, { /* 8944 */ 695, /* VPBROADCASTBrZ128rk */ }, { /* 8945 */ 696, /* VPBROADCASTBrZ128rkz */ }, { /* 8946 */ 697, /* VPBROADCASTBrZ256r */ }, { /* 8947 */ 698, /* VPBROADCASTBrZ256rk */ }, { /* 8948 */ 699, /* VPBROADCASTBrZ256rkz */ }, { /* 8949 */ 700, /* VPBROADCASTBrZr */ }, { /* 8950 */ 701, /* VPBROADCASTBrZrk */ }, { /* 8951 */ 702, /* VPBROADCASTBrZrkz */ }, { /* 8952 */ 30, /* VPBROADCASTBrm */ }, { /* 8953 */ 31, /* VPBROADCASTBrr */ }, { /* 8954 */ 305, /* VPBROADCASTDYrm */ }, { /* 8955 */ 333, /* VPBROADCASTDYrr */ }, { /* 8956 */ 334, /* VPBROADCASTDZ128m */ }, { /* 8957 */ 335, /* VPBROADCASTDZ128mk */ }, { /* 8958 */ 336, /* VPBROADCASTDZ128mkz */ }, { /* 8959 */ 330, /* VPBROADCASTDZ128r */ }, { /* 8960 */ 331, /* VPBROADCASTDZ128rk */ }, { /* 8961 */ 332, /* VPBROADCASTDZ128rkz */ }, { /* 8962 */ 337, /* VPBROADCASTDZ256m */ }, { /* 8963 */ 338, /* VPBROADCASTDZ256mk */ }, { /* 8964 */ 339, /* VPBROADCASTDZ256mkz */ }, { /* 8965 */ 309, /* VPBROADCASTDZ256r */ }, { /* 8966 */ 310, /* VPBROADCASTDZ256rk */ }, { /* 8967 */ 311, /* VPBROADCASTDZ256rkz */ }, { /* 8968 */ 340, /* VPBROADCASTDZm */ }, { /* 8969 */ 341, /* VPBROADCASTDZmk */ }, { /* 8970 */ 342, /* VPBROADCASTDZmkz */ }, { /* 8971 */ 315, /* VPBROADCASTDZr */ }, { /* 8972 */ 316, /* VPBROADCASTDZrk */ }, { /* 8973 */ 317, /* VPBROADCASTDZrkz */ }, { /* 8974 */ 678, /* VPBROADCASTDrZ128r */ }, { /* 8975 */ 695, /* VPBROADCASTDrZ128rk */ }, { /* 8976 */ 696, /* VPBROADCASTDrZ128rkz */ }, { /* 8977 */ 697, /* VPBROADCASTDrZ256r */ }, { /* 8978 */ 698, /* VPBROADCASTDrZ256rk */ }, { /* 8979 */ 699, /* VPBROADCASTDrZ256rkz */ }, { /* 8980 */ 700, /* VPBROADCASTDrZr */ }, { /* 8981 */ 701, /* VPBROADCASTDrZrk */ }, { /* 8982 */ 702, /* VPBROADCASTDrZrkz */ }, { /* 8983 */ 30, /* VPBROADCASTDrm */ }, { /* 8984 */ 31, /* VPBROADCASTDrr */ }, { /* 8985 */ 703, /* VPBROADCASTMB2QZ128rr */ }, { /* 8986 */ 704, /* VPBROADCASTMB2QZ256rr */ }, { /* 8987 */ 705, /* VPBROADCASTMB2QZrr */ }, { /* 8988 */ 703, /* VPBROADCASTMW2DZ128rr */ }, { /* 8989 */ 704, /* VPBROADCASTMW2DZ256rr */ }, { /* 8990 */ 705, /* VPBROADCASTMW2DZrr */ }, { /* 8991 */ 305, /* VPBROADCASTQYrm */ }, { /* 8992 */ 333, /* VPBROADCASTQYrr */ }, { /* 8993 */ 327, /* VPBROADCASTQZ128m */ }, { /* 8994 */ 328, /* VPBROADCASTQZ128mk */ }, { /* 8995 */ 329, /* VPBROADCASTQZ128mkz */ }, { /* 8996 */ 330, /* VPBROADCASTQZ128r */ }, { /* 8997 */ 331, /* VPBROADCASTQZ128rk */ }, { /* 8998 */ 332, /* VPBROADCASTQZ128rkz */ }, { /* 8999 */ 306, /* VPBROADCASTQZ256m */ }, { /* 9000 */ 307, /* VPBROADCASTQZ256mk */ }, { /* 9001 */ 308, /* VPBROADCASTQZ256mkz */ }, { /* 9002 */ 309, /* VPBROADCASTQZ256r */ }, { /* 9003 */ 310, /* VPBROADCASTQZ256rk */ }, { /* 9004 */ 311, /* VPBROADCASTQZ256rkz */ }, { /* 9005 */ 312, /* VPBROADCASTQZm */ }, { /* 9006 */ 313, /* VPBROADCASTQZmk */ }, { /* 9007 */ 314, /* VPBROADCASTQZmkz */ }, { /* 9008 */ 315, /* VPBROADCASTQZr */ }, { /* 9009 */ 316, /* VPBROADCASTQZrk */ }, { /* 9010 */ 317, /* VPBROADCASTQZrkz */ }, { /* 9011 */ 669, /* VPBROADCASTQrZ128r */ }, { /* 9012 */ 706, /* VPBROADCASTQrZ128rk */ }, { /* 9013 */ 707, /* VPBROADCASTQrZ128rkz */ }, { /* 9014 */ 708, /* VPBROADCASTQrZ256r */ }, { /* 9015 */ 709, /* VPBROADCASTQrZ256rk */ }, { /* 9016 */ 710, /* VPBROADCASTQrZ256rkz */ }, { /* 9017 */ 711, /* VPBROADCASTQrZr */ }, { /* 9018 */ 712, /* VPBROADCASTQrZrk */ }, { /* 9019 */ 713, /* VPBROADCASTQrZrkz */ }, { /* 9020 */ 30, /* VPBROADCASTQrm */ }, { /* 9021 */ 31, /* VPBROADCASTQrr */ }, { /* 9022 */ 305, /* VPBROADCASTWYrm */ }, { /* 9023 */ 333, /* VPBROADCASTWYrr */ }, { /* 9024 */ 714, /* VPBROADCASTWZ128m */ }, { /* 9025 */ 715, /* VPBROADCASTWZ128mk */ }, { /* 9026 */ 716, /* VPBROADCASTWZ128mkz */ }, { /* 9027 */ 330, /* VPBROADCASTWZ128r */ }, { /* 9028 */ 331, /* VPBROADCASTWZ128rk */ }, { /* 9029 */ 332, /* VPBROADCASTWZ128rkz */ }, { /* 9030 */ 717, /* VPBROADCASTWZ256m */ }, { /* 9031 */ 718, /* VPBROADCASTWZ256mk */ }, { /* 9032 */ 719, /* VPBROADCASTWZ256mkz */ }, { /* 9033 */ 309, /* VPBROADCASTWZ256r */ }, { /* 9034 */ 310, /* VPBROADCASTWZ256rk */ }, { /* 9035 */ 311, /* VPBROADCASTWZ256rkz */ }, { /* 9036 */ 720, /* VPBROADCASTWZm */ }, { /* 9037 */ 721, /* VPBROADCASTWZmk */ }, { /* 9038 */ 722, /* VPBROADCASTWZmkz */ }, { /* 9039 */ 315, /* VPBROADCASTWZr */ }, { /* 9040 */ 316, /* VPBROADCASTWZrk */ }, { /* 9041 */ 317, /* VPBROADCASTWZrkz */ }, { /* 9042 */ 678, /* VPBROADCASTWrZ128r */ }, { /* 9043 */ 695, /* VPBROADCASTWrZ128rk */ }, { /* 9044 */ 696, /* VPBROADCASTWrZ128rkz */ }, { /* 9045 */ 697, /* VPBROADCASTWrZ256r */ }, { /* 9046 */ 698, /* VPBROADCASTWrZ256rk */ }, { /* 9047 */ 699, /* VPBROADCASTWrZ256rkz */ }, { /* 9048 */ 700, /* VPBROADCASTWrZr */ }, { /* 9049 */ 701, /* VPBROADCASTWrZrk */ }, { /* 9050 */ 702, /* VPBROADCASTWrZrkz */ }, { /* 9051 */ 30, /* VPBROADCASTWrm */ }, { /* 9052 */ 31, /* VPBROADCASTWrr */ }, { /* 9053 */ 297, /* VPCLMULQDQYrm */ }, { /* 9054 */ 298, /* VPCLMULQDQYrr */ }, { /* 9055 */ 264, /* VPCLMULQDQZ128rm */ }, { /* 9056 */ 267, /* VPCLMULQDQZ128rr */ }, { /* 9057 */ 273, /* VPCLMULQDQZ256rm */ }, { /* 9058 */ 276, /* VPCLMULQDQZ256rr */ }, { /* 9059 */ 282, /* VPCLMULQDQZrm */ }, { /* 9060 */ 285, /* VPCLMULQDQZrr */ }, { /* 9061 */ 299, /* VPCLMULQDQrm */ }, { /* 9062 */ 300, /* VPCLMULQDQrr */ }, { /* 9063 */ 301, /* VPCMOVYrmr */ }, { /* 9064 */ 548, /* VPCMOVYrrm */ }, { /* 9065 */ 302, /* VPCMOVYrrr */ }, { /* 9066 */ 549, /* VPCMOVYrrr_REV */ }, { /* 9067 */ 303, /* VPCMOVrmr */ }, { /* 9068 */ 550, /* VPCMOVrrm */ }, { /* 9069 */ 304, /* VPCMOVrrr */ }, { /* 9070 */ 551, /* VPCMOVrrr_REV */ }, { /* 9071 */ 723, /* VPCMPBZ128rmi */ }, { /* 9072 */ 0, /* */ }, { /* 9073 */ 724, /* VPCMPBZ128rmik */ }, { /* 9074 */ 0, /* */ }, { /* 9075 */ 725, /* VPCMPBZ128rri */ }, { /* 9076 */ 0, /* */ }, { /* 9077 */ 726, /* VPCMPBZ128rrik */ }, { /* 9078 */ 0, /* */ }, { /* 9079 */ 727, /* VPCMPBZ256rmi */ }, { /* 9080 */ 0, /* */ }, { /* 9081 */ 728, /* VPCMPBZ256rmik */ }, { /* 9082 */ 0, /* */ }, { /* 9083 */ 729, /* VPCMPBZ256rri */ }, { /* 9084 */ 0, /* */ }, { /* 9085 */ 730, /* VPCMPBZ256rrik */ }, { /* 9086 */ 0, /* */ }, { /* 9087 */ 731, /* VPCMPBZrmi */ }, { /* 9088 */ 0, /* */ }, { /* 9089 */ 732, /* VPCMPBZrmik */ }, { /* 9090 */ 0, /* */ }, { /* 9091 */ 733, /* VPCMPBZrri */ }, { /* 9092 */ 0, /* */ }, { /* 9093 */ 734, /* VPCMPBZrrik */ }, { /* 9094 */ 0, /* */ }, { /* 9095 */ 723, /* VPCMPDZ128rmi */ }, { /* 9096 */ 0, /* */ }, { /* 9097 */ 735, /* VPCMPDZ128rmib */ }, { /* 9098 */ 0, /* */ }, { /* 9099 */ 736, /* VPCMPDZ128rmibk */ }, { /* 9100 */ 0, /* */ }, { /* 9101 */ 724, /* VPCMPDZ128rmik */ }, { /* 9102 */ 0, /* */ }, { /* 9103 */ 725, /* VPCMPDZ128rri */ }, { /* 9104 */ 0, /* */ }, { /* 9105 */ 726, /* VPCMPDZ128rrik */ }, { /* 9106 */ 0, /* */ }, { /* 9107 */ 727, /* VPCMPDZ256rmi */ }, { /* 9108 */ 0, /* */ }, { /* 9109 */ 737, /* VPCMPDZ256rmib */ }, { /* 9110 */ 0, /* */ }, { /* 9111 */ 738, /* VPCMPDZ256rmibk */ }, { /* 9112 */ 0, /* */ }, { /* 9113 */ 728, /* VPCMPDZ256rmik */ }, { /* 9114 */ 0, /* */ }, { /* 9115 */ 729, /* VPCMPDZ256rri */ }, { /* 9116 */ 0, /* */ }, { /* 9117 */ 730, /* VPCMPDZ256rrik */ }, { /* 9118 */ 0, /* */ }, { /* 9119 */ 731, /* VPCMPDZrmi */ }, { /* 9120 */ 0, /* */ }, { /* 9121 */ 739, /* VPCMPDZrmib */ }, { /* 9122 */ 0, /* */ }, { /* 9123 */ 740, /* VPCMPDZrmibk */ }, { /* 9124 */ 0, /* */ }, { /* 9125 */ 732, /* VPCMPDZrmik */ }, { /* 9126 */ 0, /* */ }, { /* 9127 */ 733, /* VPCMPDZrri */ }, { /* 9128 */ 0, /* */ }, { /* 9129 */ 734, /* VPCMPDZrrik */ }, { /* 9130 */ 0, /* */ }, { /* 9131 */ 204, /* VPCMPEQBYrm */ }, { /* 9132 */ 205, /* VPCMPEQBYrr */ }, { /* 9133 */ 741, /* VPCMPEQBZ128rm */ }, { /* 9134 */ 742, /* VPCMPEQBZ128rmk */ }, { /* 9135 */ 743, /* VPCMPEQBZ128rr */ }, { /* 9136 */ 744, /* VPCMPEQBZ128rrk */ }, { /* 9137 */ 745, /* VPCMPEQBZ256rm */ }, { /* 9138 */ 746, /* VPCMPEQBZ256rmk */ }, { /* 9139 */ 747, /* VPCMPEQBZ256rr */ }, { /* 9140 */ 748, /* VPCMPEQBZ256rrk */ }, { /* 9141 */ 749, /* VPCMPEQBZrm */ }, { /* 9142 */ 750, /* VPCMPEQBZrmk */ }, { /* 9143 */ 751, /* VPCMPEQBZrr */ }, { /* 9144 */ 752, /* VPCMPEQBZrrk */ }, { /* 9145 */ 235, /* VPCMPEQBrm */ }, { /* 9146 */ 236, /* VPCMPEQBrr */ }, { /* 9147 */ 204, /* VPCMPEQDYrm */ }, { /* 9148 */ 205, /* VPCMPEQDYrr */ }, { /* 9149 */ 741, /* VPCMPEQDZ128rm */ }, { /* 9150 */ 753, /* VPCMPEQDZ128rmb */ }, { /* 9151 */ 754, /* VPCMPEQDZ128rmbk */ }, { /* 9152 */ 742, /* VPCMPEQDZ128rmk */ }, { /* 9153 */ 743, /* VPCMPEQDZ128rr */ }, { /* 9154 */ 744, /* VPCMPEQDZ128rrk */ }, { /* 9155 */ 745, /* VPCMPEQDZ256rm */ }, { /* 9156 */ 755, /* VPCMPEQDZ256rmb */ }, { /* 9157 */ 756, /* VPCMPEQDZ256rmbk */ }, { /* 9158 */ 746, /* VPCMPEQDZ256rmk */ }, { /* 9159 */ 747, /* VPCMPEQDZ256rr */ }, { /* 9160 */ 748, /* VPCMPEQDZ256rrk */ }, { /* 9161 */ 749, /* VPCMPEQDZrm */ }, { /* 9162 */ 757, /* VPCMPEQDZrmb */ }, { /* 9163 */ 758, /* VPCMPEQDZrmbk */ }, { /* 9164 */ 750, /* VPCMPEQDZrmk */ }, { /* 9165 */ 751, /* VPCMPEQDZrr */ }, { /* 9166 */ 752, /* VPCMPEQDZrrk */ }, { /* 9167 */ 235, /* VPCMPEQDrm */ }, { /* 9168 */ 236, /* VPCMPEQDrr */ }, { /* 9169 */ 204, /* VPCMPEQQYrm */ }, { /* 9170 */ 205, /* VPCMPEQQYrr */ }, { /* 9171 */ 741, /* VPCMPEQQZ128rm */ }, { /* 9172 */ 759, /* VPCMPEQQZ128rmb */ }, { /* 9173 */ 760, /* VPCMPEQQZ128rmbk */ }, { /* 9174 */ 742, /* VPCMPEQQZ128rmk */ }, { /* 9175 */ 743, /* VPCMPEQQZ128rr */ }, { /* 9176 */ 744, /* VPCMPEQQZ128rrk */ }, { /* 9177 */ 745, /* VPCMPEQQZ256rm */ }, { /* 9178 */ 761, /* VPCMPEQQZ256rmb */ }, { /* 9179 */ 762, /* VPCMPEQQZ256rmbk */ }, { /* 9180 */ 746, /* VPCMPEQQZ256rmk */ }, { /* 9181 */ 747, /* VPCMPEQQZ256rr */ }, { /* 9182 */ 748, /* VPCMPEQQZ256rrk */ }, { /* 9183 */ 749, /* VPCMPEQQZrm */ }, { /* 9184 */ 763, /* VPCMPEQQZrmb */ }, { /* 9185 */ 764, /* VPCMPEQQZrmbk */ }, { /* 9186 */ 750, /* VPCMPEQQZrmk */ }, { /* 9187 */ 751, /* VPCMPEQQZrr */ }, { /* 9188 */ 752, /* VPCMPEQQZrrk */ }, { /* 9189 */ 235, /* VPCMPEQQrm */ }, { /* 9190 */ 236, /* VPCMPEQQrr */ }, { /* 9191 */ 204, /* VPCMPEQWYrm */ }, { /* 9192 */ 205, /* VPCMPEQWYrr */ }, { /* 9193 */ 741, /* VPCMPEQWZ128rm */ }, { /* 9194 */ 742, /* VPCMPEQWZ128rmk */ }, { /* 9195 */ 743, /* VPCMPEQWZ128rr */ }, { /* 9196 */ 744, /* VPCMPEQWZ128rrk */ }, { /* 9197 */ 745, /* VPCMPEQWZ256rm */ }, { /* 9198 */ 746, /* VPCMPEQWZ256rmk */ }, { /* 9199 */ 747, /* VPCMPEQWZ256rr */ }, { /* 9200 */ 748, /* VPCMPEQWZ256rrk */ }, { /* 9201 */ 749, /* VPCMPEQWZrm */ }, { /* 9202 */ 750, /* VPCMPEQWZrmk */ }, { /* 9203 */ 751, /* VPCMPEQWZrr */ }, { /* 9204 */ 752, /* VPCMPEQWZrrk */ }, { /* 9205 */ 235, /* VPCMPEQWrm */ }, { /* 9206 */ 236, /* VPCMPEQWrr */ }, { /* 9207 */ 32, /* VPCMPESTRIrm */ }, { /* 9208 */ 33, /* VPCMPESTRIrr */ }, { /* 9209 */ 32, /* VPCMPESTRMrm */ }, { /* 9210 */ 33, /* VPCMPESTRMrr */ }, { /* 9211 */ 204, /* VPCMPGTBYrm */ }, { /* 9212 */ 205, /* VPCMPGTBYrr */ }, { /* 9213 */ 741, /* VPCMPGTBZ128rm */ }, { /* 9214 */ 742, /* VPCMPGTBZ128rmk */ }, { /* 9215 */ 743, /* VPCMPGTBZ128rr */ }, { /* 9216 */ 744, /* VPCMPGTBZ128rrk */ }, { /* 9217 */ 745, /* VPCMPGTBZ256rm */ }, { /* 9218 */ 746, /* VPCMPGTBZ256rmk */ }, { /* 9219 */ 747, /* VPCMPGTBZ256rr */ }, { /* 9220 */ 748, /* VPCMPGTBZ256rrk */ }, { /* 9221 */ 749, /* VPCMPGTBZrm */ }, { /* 9222 */ 750, /* VPCMPGTBZrmk */ }, { /* 9223 */ 751, /* VPCMPGTBZrr */ }, { /* 9224 */ 752, /* VPCMPGTBZrrk */ }, { /* 9225 */ 235, /* VPCMPGTBrm */ }, { /* 9226 */ 236, /* VPCMPGTBrr */ }, { /* 9227 */ 204, /* VPCMPGTDYrm */ }, { /* 9228 */ 205, /* VPCMPGTDYrr */ }, { /* 9229 */ 741, /* VPCMPGTDZ128rm */ }, { /* 9230 */ 753, /* VPCMPGTDZ128rmb */ }, { /* 9231 */ 754, /* VPCMPGTDZ128rmbk */ }, { /* 9232 */ 742, /* VPCMPGTDZ128rmk */ }, { /* 9233 */ 743, /* VPCMPGTDZ128rr */ }, { /* 9234 */ 744, /* VPCMPGTDZ128rrk */ }, { /* 9235 */ 745, /* VPCMPGTDZ256rm */ }, { /* 9236 */ 755, /* VPCMPGTDZ256rmb */ }, { /* 9237 */ 756, /* VPCMPGTDZ256rmbk */ }, { /* 9238 */ 746, /* VPCMPGTDZ256rmk */ }, { /* 9239 */ 747, /* VPCMPGTDZ256rr */ }, { /* 9240 */ 748, /* VPCMPGTDZ256rrk */ }, { /* 9241 */ 749, /* VPCMPGTDZrm */ }, { /* 9242 */ 757, /* VPCMPGTDZrmb */ }, { /* 9243 */ 758, /* VPCMPGTDZrmbk */ }, { /* 9244 */ 750, /* VPCMPGTDZrmk */ }, { /* 9245 */ 751, /* VPCMPGTDZrr */ }, { /* 9246 */ 752, /* VPCMPGTDZrrk */ }, { /* 9247 */ 235, /* VPCMPGTDrm */ }, { /* 9248 */ 236, /* VPCMPGTDrr */ }, { /* 9249 */ 204, /* VPCMPGTQYrm */ }, { /* 9250 */ 205, /* VPCMPGTQYrr */ }, { /* 9251 */ 741, /* VPCMPGTQZ128rm */ }, { /* 9252 */ 759, /* VPCMPGTQZ128rmb */ }, { /* 9253 */ 760, /* VPCMPGTQZ128rmbk */ }, { /* 9254 */ 742, /* VPCMPGTQZ128rmk */ }, { /* 9255 */ 743, /* VPCMPGTQZ128rr */ }, { /* 9256 */ 744, /* VPCMPGTQZ128rrk */ }, { /* 9257 */ 745, /* VPCMPGTQZ256rm */ }, { /* 9258 */ 761, /* VPCMPGTQZ256rmb */ }, { /* 9259 */ 762, /* VPCMPGTQZ256rmbk */ }, { /* 9260 */ 746, /* VPCMPGTQZ256rmk */ }, { /* 9261 */ 747, /* VPCMPGTQZ256rr */ }, { /* 9262 */ 748, /* VPCMPGTQZ256rrk */ }, { /* 9263 */ 749, /* VPCMPGTQZrm */ }, { /* 9264 */ 763, /* VPCMPGTQZrmb */ }, { /* 9265 */ 764, /* VPCMPGTQZrmbk */ }, { /* 9266 */ 750, /* VPCMPGTQZrmk */ }, { /* 9267 */ 751, /* VPCMPGTQZrr */ }, { /* 9268 */ 752, /* VPCMPGTQZrrk */ }, { /* 9269 */ 235, /* VPCMPGTQrm */ }, { /* 9270 */ 236, /* VPCMPGTQrr */ }, { /* 9271 */ 204, /* VPCMPGTWYrm */ }, { /* 9272 */ 205, /* VPCMPGTWYrr */ }, { /* 9273 */ 741, /* VPCMPGTWZ128rm */ }, { /* 9274 */ 742, /* VPCMPGTWZ128rmk */ }, { /* 9275 */ 743, /* VPCMPGTWZ128rr */ }, { /* 9276 */ 744, /* VPCMPGTWZ128rrk */ }, { /* 9277 */ 745, /* VPCMPGTWZ256rm */ }, { /* 9278 */ 746, /* VPCMPGTWZ256rmk */ }, { /* 9279 */ 747, /* VPCMPGTWZ256rr */ }, { /* 9280 */ 748, /* VPCMPGTWZ256rrk */ }, { /* 9281 */ 749, /* VPCMPGTWZrm */ }, { /* 9282 */ 750, /* VPCMPGTWZrmk */ }, { /* 9283 */ 751, /* VPCMPGTWZrr */ }, { /* 9284 */ 752, /* VPCMPGTWZrrk */ }, { /* 9285 */ 235, /* VPCMPGTWrm */ }, { /* 9286 */ 236, /* VPCMPGTWrr */ }, { /* 9287 */ 32, /* VPCMPISTRIrm */ }, { /* 9288 */ 33, /* VPCMPISTRIrr */ }, { /* 9289 */ 32, /* VPCMPISTRMrm */ }, { /* 9290 */ 33, /* VPCMPISTRMrr */ }, { /* 9291 */ 723, /* VPCMPQZ128rmi */ }, { /* 9292 */ 0, /* */ }, { /* 9293 */ 765, /* VPCMPQZ128rmib */ }, { /* 9294 */ 0, /* */ }, { /* 9295 */ 766, /* VPCMPQZ128rmibk */ }, { /* 9296 */ 0, /* */ }, { /* 9297 */ 724, /* VPCMPQZ128rmik */ }, { /* 9298 */ 0, /* */ }, { /* 9299 */ 725, /* VPCMPQZ128rri */ }, { /* 9300 */ 0, /* */ }, { /* 9301 */ 726, /* VPCMPQZ128rrik */ }, { /* 9302 */ 0, /* */ }, { /* 9303 */ 727, /* VPCMPQZ256rmi */ }, { /* 9304 */ 0, /* */ }, { /* 9305 */ 767, /* VPCMPQZ256rmib */ }, { /* 9306 */ 0, /* */ }, { /* 9307 */ 768, /* VPCMPQZ256rmibk */ }, { /* 9308 */ 0, /* */ }, { /* 9309 */ 728, /* VPCMPQZ256rmik */ }, { /* 9310 */ 0, /* */ }, { /* 9311 */ 729, /* VPCMPQZ256rri */ }, { /* 9312 */ 0, /* */ }, { /* 9313 */ 730, /* VPCMPQZ256rrik */ }, { /* 9314 */ 0, /* */ }, { /* 9315 */ 731, /* VPCMPQZrmi */ }, { /* 9316 */ 0, /* */ }, { /* 9317 */ 769, /* VPCMPQZrmib */ }, { /* 9318 */ 0, /* */ }, { /* 9319 */ 770, /* VPCMPQZrmibk */ }, { /* 9320 */ 0, /* */ }, { /* 9321 */ 732, /* VPCMPQZrmik */ }, { /* 9322 */ 0, /* */ }, { /* 9323 */ 733, /* VPCMPQZrri */ }, { /* 9324 */ 0, /* */ }, { /* 9325 */ 734, /* VPCMPQZrrik */ }, { /* 9326 */ 0, /* */ }, { /* 9327 */ 723, /* VPCMPUBZ128rmi */ }, { /* 9328 */ 0, /* */ }, { /* 9329 */ 724, /* VPCMPUBZ128rmik */ }, { /* 9330 */ 0, /* */ }, { /* 9331 */ 725, /* VPCMPUBZ128rri */ }, { /* 9332 */ 0, /* */ }, { /* 9333 */ 726, /* VPCMPUBZ128rrik */ }, { /* 9334 */ 0, /* */ }, { /* 9335 */ 727, /* VPCMPUBZ256rmi */ }, { /* 9336 */ 0, /* */ }, { /* 9337 */ 728, /* VPCMPUBZ256rmik */ }, { /* 9338 */ 0, /* */ }, { /* 9339 */ 729, /* VPCMPUBZ256rri */ }, { /* 9340 */ 0, /* */ }, { /* 9341 */ 730, /* VPCMPUBZ256rrik */ }, { /* 9342 */ 0, /* */ }, { /* 9343 */ 731, /* VPCMPUBZrmi */ }, { /* 9344 */ 0, /* */ }, { /* 9345 */ 732, /* VPCMPUBZrmik */ }, { /* 9346 */ 0, /* */ }, { /* 9347 */ 733, /* VPCMPUBZrri */ }, { /* 9348 */ 0, /* */ }, { /* 9349 */ 734, /* VPCMPUBZrrik */ }, { /* 9350 */ 0, /* */ }, { /* 9351 */ 723, /* VPCMPUDZ128rmi */ }, { /* 9352 */ 0, /* */ }, { /* 9353 */ 735, /* VPCMPUDZ128rmib */ }, { /* 9354 */ 0, /* */ }, { /* 9355 */ 736, /* VPCMPUDZ128rmibk */ }, { /* 9356 */ 0, /* */ }, { /* 9357 */ 724, /* VPCMPUDZ128rmik */ }, { /* 9358 */ 0, /* */ }, { /* 9359 */ 725, /* VPCMPUDZ128rri */ }, { /* 9360 */ 0, /* */ }, { /* 9361 */ 726, /* VPCMPUDZ128rrik */ }, { /* 9362 */ 0, /* */ }, { /* 9363 */ 727, /* VPCMPUDZ256rmi */ }, { /* 9364 */ 0, /* */ }, { /* 9365 */ 737, /* VPCMPUDZ256rmib */ }, { /* 9366 */ 0, /* */ }, { /* 9367 */ 738, /* VPCMPUDZ256rmibk */ }, { /* 9368 */ 0, /* */ }, { /* 9369 */ 728, /* VPCMPUDZ256rmik */ }, { /* 9370 */ 0, /* */ }, { /* 9371 */ 729, /* VPCMPUDZ256rri */ }, { /* 9372 */ 0, /* */ }, { /* 9373 */ 730, /* VPCMPUDZ256rrik */ }, { /* 9374 */ 0, /* */ }, { /* 9375 */ 731, /* VPCMPUDZrmi */ }, { /* 9376 */ 0, /* */ }, { /* 9377 */ 739, /* VPCMPUDZrmib */ }, { /* 9378 */ 0, /* */ }, { /* 9379 */ 740, /* VPCMPUDZrmibk */ }, { /* 9380 */ 0, /* */ }, { /* 9381 */ 732, /* VPCMPUDZrmik */ }, { /* 9382 */ 0, /* */ }, { /* 9383 */ 733, /* VPCMPUDZrri */ }, { /* 9384 */ 0, /* */ }, { /* 9385 */ 734, /* VPCMPUDZrrik */ }, { /* 9386 */ 0, /* */ }, { /* 9387 */ 723, /* VPCMPUQZ128rmi */ }, { /* 9388 */ 0, /* */ }, { /* 9389 */ 765, /* VPCMPUQZ128rmib */ }, { /* 9390 */ 0, /* */ }, { /* 9391 */ 766, /* VPCMPUQZ128rmibk */ }, { /* 9392 */ 0, /* */ }, { /* 9393 */ 724, /* VPCMPUQZ128rmik */ }, { /* 9394 */ 0, /* */ }, { /* 9395 */ 725, /* VPCMPUQZ128rri */ }, { /* 9396 */ 0, /* */ }, { /* 9397 */ 726, /* VPCMPUQZ128rrik */ }, { /* 9398 */ 0, /* */ }, { /* 9399 */ 727, /* VPCMPUQZ256rmi */ }, { /* 9400 */ 0, /* */ }, { /* 9401 */ 767, /* VPCMPUQZ256rmib */ }, { /* 9402 */ 0, /* */ }, { /* 9403 */ 768, /* VPCMPUQZ256rmibk */ }, { /* 9404 */ 0, /* */ }, { /* 9405 */ 728, /* VPCMPUQZ256rmik */ }, { /* 9406 */ 0, /* */ }, { /* 9407 */ 729, /* VPCMPUQZ256rri */ }, { /* 9408 */ 0, /* */ }, { /* 9409 */ 730, /* VPCMPUQZ256rrik */ }, { /* 9410 */ 0, /* */ }, { /* 9411 */ 731, /* VPCMPUQZrmi */ }, { /* 9412 */ 0, /* */ }, { /* 9413 */ 769, /* VPCMPUQZrmib */ }, { /* 9414 */ 0, /* */ }, { /* 9415 */ 770, /* VPCMPUQZrmibk */ }, { /* 9416 */ 0, /* */ }, { /* 9417 */ 732, /* VPCMPUQZrmik */ }, { /* 9418 */ 0, /* */ }, { /* 9419 */ 733, /* VPCMPUQZrri */ }, { /* 9420 */ 0, /* */ }, { /* 9421 */ 734, /* VPCMPUQZrrik */ }, { /* 9422 */ 0, /* */ }, { /* 9423 */ 723, /* VPCMPUWZ128rmi */ }, { /* 9424 */ 0, /* */ }, { /* 9425 */ 724, /* VPCMPUWZ128rmik */ }, { /* 9426 */ 0, /* */ }, { /* 9427 */ 725, /* VPCMPUWZ128rri */ }, { /* 9428 */ 0, /* */ }, { /* 9429 */ 726, /* VPCMPUWZ128rrik */ }, { /* 9430 */ 0, /* */ }, { /* 9431 */ 727, /* VPCMPUWZ256rmi */ }, { /* 9432 */ 0, /* */ }, { /* 9433 */ 728, /* VPCMPUWZ256rmik */ }, { /* 9434 */ 0, /* */ }, { /* 9435 */ 729, /* VPCMPUWZ256rri */ }, { /* 9436 */ 0, /* */ }, { /* 9437 */ 730, /* VPCMPUWZ256rrik */ }, { /* 9438 */ 0, /* */ }, { /* 9439 */ 731, /* VPCMPUWZrmi */ }, { /* 9440 */ 0, /* */ }, { /* 9441 */ 732, /* VPCMPUWZrmik */ }, { /* 9442 */ 0, /* */ }, { /* 9443 */ 733, /* VPCMPUWZrri */ }, { /* 9444 */ 0, /* */ }, { /* 9445 */ 734, /* VPCMPUWZrrik */ }, { /* 9446 */ 0, /* */ }, { /* 9447 */ 723, /* VPCMPWZ128rmi */ }, { /* 9448 */ 0, /* */ }, { /* 9449 */ 724, /* VPCMPWZ128rmik */ }, { /* 9450 */ 0, /* */ }, { /* 9451 */ 725, /* VPCMPWZ128rri */ }, { /* 9452 */ 0, /* */ }, { /* 9453 */ 726, /* VPCMPWZ128rrik */ }, { /* 9454 */ 0, /* */ }, { /* 9455 */ 727, /* VPCMPWZ256rmi */ }, { /* 9456 */ 0, /* */ }, { /* 9457 */ 728, /* VPCMPWZ256rmik */ }, { /* 9458 */ 0, /* */ }, { /* 9459 */ 729, /* VPCMPWZ256rri */ }, { /* 9460 */ 0, /* */ }, { /* 9461 */ 730, /* VPCMPWZ256rrik */ }, { /* 9462 */ 0, /* */ }, { /* 9463 */ 731, /* VPCMPWZrmi */ }, { /* 9464 */ 0, /* */ }, { /* 9465 */ 732, /* VPCMPWZrmik */ }, { /* 9466 */ 0, /* */ }, { /* 9467 */ 733, /* VPCMPWZrri */ }, { /* 9468 */ 0, /* */ }, { /* 9469 */ 734, /* VPCMPWZrrik */ }, { /* 9470 */ 0, /* */ }, { /* 9471 */ 771, /* VPCOMBmi */ }, { /* 9472 */ 0, /* */ }, { /* 9473 */ 772, /* VPCOMBri */ }, { /* 9474 */ 0, /* */ }, { /* 9475 */ 771, /* VPCOMDmi */ }, { /* 9476 */ 0, /* */ }, { /* 9477 */ 772, /* VPCOMDri */ }, { /* 9478 */ 0, /* */ }, { /* 9479 */ 169, /* VPCOMPRESSBZ128mr */ }, { /* 9480 */ 773, /* VPCOMPRESSBZ128mrk */ }, { /* 9481 */ 381, /* VPCOMPRESSBZ128rr */ }, { /* 9482 */ 382, /* VPCOMPRESSBZ128rrk */ }, { /* 9483 */ 383, /* VPCOMPRESSBZ128rrkz */ }, { /* 9484 */ 670, /* VPCOMPRESSBZ256mr */ }, { /* 9485 */ 774, /* VPCOMPRESSBZ256mrk */ }, { /* 9486 */ 386, /* VPCOMPRESSBZ256rr */ }, { /* 9487 */ 387, /* VPCOMPRESSBZ256rrk */ }, { /* 9488 */ 388, /* VPCOMPRESSBZ256rrkz */ }, { /* 9489 */ 775, /* VPCOMPRESSBZmr */ }, { /* 9490 */ 776, /* VPCOMPRESSBZmrk */ }, { /* 9491 */ 391, /* VPCOMPRESSBZrr */ }, { /* 9492 */ 392, /* VPCOMPRESSBZrrk */ }, { /* 9493 */ 393, /* VPCOMPRESSBZrrkz */ }, { /* 9494 */ 394, /* VPCOMPRESSDZ128mr */ }, { /* 9495 */ 395, /* VPCOMPRESSDZ128mrk */ }, { /* 9496 */ 381, /* VPCOMPRESSDZ128rr */ }, { /* 9497 */ 382, /* VPCOMPRESSDZ128rrk */ }, { /* 9498 */ 383, /* VPCOMPRESSDZ128rrkz */ }, { /* 9499 */ 396, /* VPCOMPRESSDZ256mr */ }, { /* 9500 */ 397, /* VPCOMPRESSDZ256mrk */ }, { /* 9501 */ 386, /* VPCOMPRESSDZ256rr */ }, { /* 9502 */ 387, /* VPCOMPRESSDZ256rrk */ }, { /* 9503 */ 388, /* VPCOMPRESSDZ256rrkz */ }, { /* 9504 */ 398, /* VPCOMPRESSDZmr */ }, { /* 9505 */ 399, /* VPCOMPRESSDZmrk */ }, { /* 9506 */ 391, /* VPCOMPRESSDZrr */ }, { /* 9507 */ 392, /* VPCOMPRESSDZrrk */ }, { /* 9508 */ 393, /* VPCOMPRESSDZrrkz */ }, { /* 9509 */ 379, /* VPCOMPRESSQZ128mr */ }, { /* 9510 */ 380, /* VPCOMPRESSQZ128mrk */ }, { /* 9511 */ 381, /* VPCOMPRESSQZ128rr */ }, { /* 9512 */ 382, /* VPCOMPRESSQZ128rrk */ }, { /* 9513 */ 383, /* VPCOMPRESSQZ128rrkz */ }, { /* 9514 */ 384, /* VPCOMPRESSQZ256mr */ }, { /* 9515 */ 385, /* VPCOMPRESSQZ256mrk */ }, { /* 9516 */ 386, /* VPCOMPRESSQZ256rr */ }, { /* 9517 */ 387, /* VPCOMPRESSQZ256rrk */ }, { /* 9518 */ 388, /* VPCOMPRESSQZ256rrkz */ }, { /* 9519 */ 389, /* VPCOMPRESSQZmr */ }, { /* 9520 */ 390, /* VPCOMPRESSQZmrk */ }, { /* 9521 */ 391, /* VPCOMPRESSQZrr */ }, { /* 9522 */ 392, /* VPCOMPRESSQZrrk */ }, { /* 9523 */ 393, /* VPCOMPRESSQZrrkz */ }, { /* 9524 */ 777, /* VPCOMPRESSWZ128mr */ }, { /* 9525 */ 778, /* VPCOMPRESSWZ128mrk */ }, { /* 9526 */ 381, /* VPCOMPRESSWZ128rr */ }, { /* 9527 */ 382, /* VPCOMPRESSWZ128rrk */ }, { /* 9528 */ 383, /* VPCOMPRESSWZ128rrkz */ }, { /* 9529 */ 779, /* VPCOMPRESSWZ256mr */ }, { /* 9530 */ 780, /* VPCOMPRESSWZ256mrk */ }, { /* 9531 */ 386, /* VPCOMPRESSWZ256rr */ }, { /* 9532 */ 387, /* VPCOMPRESSWZ256rrk */ }, { /* 9533 */ 388, /* VPCOMPRESSWZ256rrkz */ }, { /* 9534 */ 781, /* VPCOMPRESSWZmr */ }, { /* 9535 */ 782, /* VPCOMPRESSWZmrk */ }, { /* 9536 */ 391, /* VPCOMPRESSWZrr */ }, { /* 9537 */ 392, /* VPCOMPRESSWZrrk */ }, { /* 9538 */ 393, /* VPCOMPRESSWZrrkz */ }, { /* 9539 */ 771, /* VPCOMQmi */ }, { /* 9540 */ 0, /* */ }, { /* 9541 */ 772, /* VPCOMQri */ }, { /* 9542 */ 0, /* */ }, { /* 9543 */ 771, /* VPCOMUBmi */ }, { /* 9544 */ 0, /* */ }, { /* 9545 */ 772, /* VPCOMUBri */ }, { /* 9546 */ 0, /* */ }, { /* 9547 */ 771, /* VPCOMUDmi */ }, { /* 9548 */ 0, /* */ }, { /* 9549 */ 772, /* VPCOMUDri */ }, { /* 9550 */ 0, /* */ }, { /* 9551 */ 771, /* VPCOMUQmi */ }, { /* 9552 */ 0, /* */ }, { /* 9553 */ 772, /* VPCOMUQri */ }, { /* 9554 */ 0, /* */ }, { /* 9555 */ 771, /* VPCOMUWmi */ }, { /* 9556 */ 0, /* */ }, { /* 9557 */ 772, /* VPCOMUWri */ }, { /* 9558 */ 0, /* */ }, { /* 9559 */ 771, /* VPCOMWmi */ }, { /* 9560 */ 0, /* */ }, { /* 9561 */ 772, /* VPCOMWri */ }, { /* 9562 */ 0, /* */ }, { /* 9563 */ 409, /* VPCONFLICTDZ128rm */ }, { /* 9564 */ 334, /* VPCONFLICTDZ128rmb */ }, { /* 9565 */ 335, /* VPCONFLICTDZ128rmbk */ }, { /* 9566 */ 336, /* VPCONFLICTDZ128rmbkz */ }, { /* 9567 */ 410, /* VPCONFLICTDZ128rmk */ }, { /* 9568 */ 411, /* VPCONFLICTDZ128rmkz */ }, { /* 9569 */ 330, /* VPCONFLICTDZ128rr */ }, { /* 9570 */ 331, /* VPCONFLICTDZ128rrk */ }, { /* 9571 */ 332, /* VPCONFLICTDZ128rrkz */ }, { /* 9572 */ 412, /* VPCONFLICTDZ256rm */ }, { /* 9573 */ 337, /* VPCONFLICTDZ256rmb */ }, { /* 9574 */ 338, /* VPCONFLICTDZ256rmbk */ }, { /* 9575 */ 339, /* VPCONFLICTDZ256rmbkz */ }, { /* 9576 */ 413, /* VPCONFLICTDZ256rmk */ }, { /* 9577 */ 414, /* VPCONFLICTDZ256rmkz */ }, { /* 9578 */ 415, /* VPCONFLICTDZ256rr */ }, { /* 9579 */ 416, /* VPCONFLICTDZ256rrk */ }, { /* 9580 */ 417, /* VPCONFLICTDZ256rrkz */ }, { /* 9581 */ 418, /* VPCONFLICTDZrm */ }, { /* 9582 */ 340, /* VPCONFLICTDZrmb */ }, { /* 9583 */ 341, /* VPCONFLICTDZrmbk */ }, { /* 9584 */ 342, /* VPCONFLICTDZrmbkz */ }, { /* 9585 */ 419, /* VPCONFLICTDZrmk */ }, { /* 9586 */ 420, /* VPCONFLICTDZrmkz */ }, { /* 9587 */ 421, /* VPCONFLICTDZrr */ }, { /* 9588 */ 425, /* VPCONFLICTDZrrk */ }, { /* 9589 */ 426, /* VPCONFLICTDZrrkz */ }, { /* 9590 */ 409, /* VPCONFLICTQZ128rm */ }, { /* 9591 */ 327, /* VPCONFLICTQZ128rmb */ }, { /* 9592 */ 328, /* VPCONFLICTQZ128rmbk */ }, { /* 9593 */ 329, /* VPCONFLICTQZ128rmbkz */ }, { /* 9594 */ 410, /* VPCONFLICTQZ128rmk */ }, { /* 9595 */ 411, /* VPCONFLICTQZ128rmkz */ }, { /* 9596 */ 330, /* VPCONFLICTQZ128rr */ }, { /* 9597 */ 331, /* VPCONFLICTQZ128rrk */ }, { /* 9598 */ 332, /* VPCONFLICTQZ128rrkz */ }, { /* 9599 */ 412, /* VPCONFLICTQZ256rm */ }, { /* 9600 */ 306, /* VPCONFLICTQZ256rmb */ }, { /* 9601 */ 307, /* VPCONFLICTQZ256rmbk */ }, { /* 9602 */ 308, /* VPCONFLICTQZ256rmbkz */ }, { /* 9603 */ 413, /* VPCONFLICTQZ256rmk */ }, { /* 9604 */ 414, /* VPCONFLICTQZ256rmkz */ }, { /* 9605 */ 415, /* VPCONFLICTQZ256rr */ }, { /* 9606 */ 416, /* VPCONFLICTQZ256rrk */ }, { /* 9607 */ 417, /* VPCONFLICTQZ256rrkz */ }, { /* 9608 */ 418, /* VPCONFLICTQZrm */ }, { /* 9609 */ 312, /* VPCONFLICTQZrmb */ }, { /* 9610 */ 313, /* VPCONFLICTQZrmbk */ }, { /* 9611 */ 314, /* VPCONFLICTQZrmbkz */ }, { /* 9612 */ 419, /* VPCONFLICTQZrmk */ }, { /* 9613 */ 420, /* VPCONFLICTQZrmkz */ }, { /* 9614 */ 421, /* VPCONFLICTQZrr */ }, { /* 9615 */ 425, /* VPCONFLICTQZrrk */ }, { /* 9616 */ 426, /* VPCONFLICTQZrrkz */ }, { /* 9617 */ 202, /* VPDPBUSDSZ128m */ }, { /* 9618 */ 540, /* VPDPBUSDSZ128mb */ }, { /* 9619 */ 238, /* VPDPBUSDSZ128mbk */ }, { /* 9620 */ 238, /* VPDPBUSDSZ128mbkz */ }, { /* 9621 */ 203, /* VPDPBUSDSZ128mk */ }, { /* 9622 */ 203, /* VPDPBUSDSZ128mkz */ }, { /* 9623 */ 530, /* VPDPBUSDSZ128r */ }, { /* 9624 */ 212, /* VPDPBUSDSZ128rk */ }, { /* 9625 */ 212, /* VPDPBUSDSZ128rkz */ }, { /* 9626 */ 531, /* VPDPBUSDSZ256m */ }, { /* 9627 */ 541, /* VPDPBUSDSZ256mb */ }, { /* 9628 */ 241, /* VPDPBUSDSZ256mbk */ }, { /* 9629 */ 241, /* VPDPBUSDSZ256mbkz */ }, { /* 9630 */ 218, /* VPDPBUSDSZ256mk */ }, { /* 9631 */ 218, /* VPDPBUSDSZ256mkz */ }, { /* 9632 */ 533, /* VPDPBUSDSZ256r */ }, { /* 9633 */ 221, /* VPDPBUSDSZ256rk */ }, { /* 9634 */ 221, /* VPDPBUSDSZ256rkz */ }, { /* 9635 */ 534, /* VPDPBUSDSZm */ }, { /* 9636 */ 542, /* VPDPBUSDSZmb */ }, { /* 9637 */ 244, /* VPDPBUSDSZmbk */ }, { /* 9638 */ 244, /* VPDPBUSDSZmbkz */ }, { /* 9639 */ 227, /* VPDPBUSDSZmk */ }, { /* 9640 */ 227, /* VPDPBUSDSZmkz */ }, { /* 9641 */ 536, /* VPDPBUSDSZr */ }, { /* 9642 */ 233, /* VPDPBUSDSZrk */ }, { /* 9643 */ 233, /* VPDPBUSDSZrkz */ }, { /* 9644 */ 202, /* VPDPBUSDZ128m */ }, { /* 9645 */ 540, /* VPDPBUSDZ128mb */ }, { /* 9646 */ 238, /* VPDPBUSDZ128mbk */ }, { /* 9647 */ 238, /* VPDPBUSDZ128mbkz */ }, { /* 9648 */ 203, /* VPDPBUSDZ128mk */ }, { /* 9649 */ 203, /* VPDPBUSDZ128mkz */ }, { /* 9650 */ 530, /* VPDPBUSDZ128r */ }, { /* 9651 */ 212, /* VPDPBUSDZ128rk */ }, { /* 9652 */ 212, /* VPDPBUSDZ128rkz */ }, { /* 9653 */ 531, /* VPDPBUSDZ256m */ }, { /* 9654 */ 541, /* VPDPBUSDZ256mb */ }, { /* 9655 */ 241, /* VPDPBUSDZ256mbk */ }, { /* 9656 */ 241, /* VPDPBUSDZ256mbkz */ }, { /* 9657 */ 218, /* VPDPBUSDZ256mk */ }, { /* 9658 */ 218, /* VPDPBUSDZ256mkz */ }, { /* 9659 */ 533, /* VPDPBUSDZ256r */ }, { /* 9660 */ 221, /* VPDPBUSDZ256rk */ }, { /* 9661 */ 221, /* VPDPBUSDZ256rkz */ }, { /* 9662 */ 534, /* VPDPBUSDZm */ }, { /* 9663 */ 542, /* VPDPBUSDZmb */ }, { /* 9664 */ 244, /* VPDPBUSDZmbk */ }, { /* 9665 */ 244, /* VPDPBUSDZmbkz */ }, { /* 9666 */ 227, /* VPDPBUSDZmk */ }, { /* 9667 */ 227, /* VPDPBUSDZmkz */ }, { /* 9668 */ 536, /* VPDPBUSDZr */ }, { /* 9669 */ 233, /* VPDPBUSDZrk */ }, { /* 9670 */ 233, /* VPDPBUSDZrkz */ }, { /* 9671 */ 202, /* VPDPWSSDSZ128m */ }, { /* 9672 */ 540, /* VPDPWSSDSZ128mb */ }, { /* 9673 */ 238, /* VPDPWSSDSZ128mbk */ }, { /* 9674 */ 238, /* VPDPWSSDSZ128mbkz */ }, { /* 9675 */ 203, /* VPDPWSSDSZ128mk */ }, { /* 9676 */ 203, /* VPDPWSSDSZ128mkz */ }, { /* 9677 */ 530, /* VPDPWSSDSZ128r */ }, { /* 9678 */ 212, /* VPDPWSSDSZ128rk */ }, { /* 9679 */ 212, /* VPDPWSSDSZ128rkz */ }, { /* 9680 */ 531, /* VPDPWSSDSZ256m */ }, { /* 9681 */ 541, /* VPDPWSSDSZ256mb */ }, { /* 9682 */ 241, /* VPDPWSSDSZ256mbk */ }, { /* 9683 */ 241, /* VPDPWSSDSZ256mbkz */ }, { /* 9684 */ 218, /* VPDPWSSDSZ256mk */ }, { /* 9685 */ 218, /* VPDPWSSDSZ256mkz */ }, { /* 9686 */ 533, /* VPDPWSSDSZ256r */ }, { /* 9687 */ 221, /* VPDPWSSDSZ256rk */ }, { /* 9688 */ 221, /* VPDPWSSDSZ256rkz */ }, { /* 9689 */ 534, /* VPDPWSSDSZm */ }, { /* 9690 */ 542, /* VPDPWSSDSZmb */ }, { /* 9691 */ 244, /* VPDPWSSDSZmbk */ }, { /* 9692 */ 244, /* VPDPWSSDSZmbkz */ }, { /* 9693 */ 227, /* VPDPWSSDSZmk */ }, { /* 9694 */ 227, /* VPDPWSSDSZmkz */ }, { /* 9695 */ 536, /* VPDPWSSDSZr */ }, { /* 9696 */ 233, /* VPDPWSSDSZrk */ }, { /* 9697 */ 233, /* VPDPWSSDSZrkz */ }, { /* 9698 */ 202, /* VPDPWSSDZ128m */ }, { /* 9699 */ 540, /* VPDPWSSDZ128mb */ }, { /* 9700 */ 238, /* VPDPWSSDZ128mbk */ }, { /* 9701 */ 238, /* VPDPWSSDZ128mbkz */ }, { /* 9702 */ 203, /* VPDPWSSDZ128mk */ }, { /* 9703 */ 203, /* VPDPWSSDZ128mkz */ }, { /* 9704 */ 530, /* VPDPWSSDZ128r */ }, { /* 9705 */ 212, /* VPDPWSSDZ128rk */ }, { /* 9706 */ 212, /* VPDPWSSDZ128rkz */ }, { /* 9707 */ 531, /* VPDPWSSDZ256m */ }, { /* 9708 */ 541, /* VPDPWSSDZ256mb */ }, { /* 9709 */ 241, /* VPDPWSSDZ256mbk */ }, { /* 9710 */ 241, /* VPDPWSSDZ256mbkz */ }, { /* 9711 */ 218, /* VPDPWSSDZ256mk */ }, { /* 9712 */ 218, /* VPDPWSSDZ256mkz */ }, { /* 9713 */ 533, /* VPDPWSSDZ256r */ }, { /* 9714 */ 221, /* VPDPWSSDZ256rk */ }, { /* 9715 */ 221, /* VPDPWSSDZ256rkz */ }, { /* 9716 */ 534, /* VPDPWSSDZm */ }, { /* 9717 */ 542, /* VPDPWSSDZmb */ }, { /* 9718 */ 244, /* VPDPWSSDZmbk */ }, { /* 9719 */ 244, /* VPDPWSSDZmbkz */ }, { /* 9720 */ 227, /* VPDPWSSDZmk */ }, { /* 9721 */ 227, /* VPDPWSSDZmkz */ }, { /* 9722 */ 536, /* VPDPWSSDZr */ }, { /* 9723 */ 233, /* VPDPWSSDZrk */ }, { /* 9724 */ 233, /* VPDPWSSDZrkz */ }, { /* 9725 */ 297, /* VPERM2F128rm */ }, { /* 9726 */ 298, /* VPERM2F128rr */ }, { /* 9727 */ 297, /* VPERM2I128rm */ }, { /* 9728 */ 298, /* VPERM2I128rr */ }, { /* 9729 */ 206, /* VPERMBZ128rm */ }, { /* 9730 */ 203, /* VPERMBZ128rmk */ }, { /* 9731 */ 210, /* VPERMBZ128rmkz */ }, { /* 9732 */ 211, /* VPERMBZ128rr */ }, { /* 9733 */ 212, /* VPERMBZ128rrk */ }, { /* 9734 */ 213, /* VPERMBZ128rrkz */ }, { /* 9735 */ 214, /* VPERMBZ256rm */ }, { /* 9736 */ 218, /* VPERMBZ256rmk */ }, { /* 9737 */ 219, /* VPERMBZ256rmkz */ }, { /* 9738 */ 220, /* VPERMBZ256rr */ }, { /* 9739 */ 221, /* VPERMBZ256rrk */ }, { /* 9740 */ 222, /* VPERMBZ256rrkz */ }, { /* 9741 */ 223, /* VPERMBZrm */ }, { /* 9742 */ 227, /* VPERMBZrmk */ }, { /* 9743 */ 228, /* VPERMBZrmkz */ }, { /* 9744 */ 229, /* VPERMBZrr */ }, { /* 9745 */ 233, /* VPERMBZrrk */ }, { /* 9746 */ 234, /* VPERMBZrrkz */ }, { /* 9747 */ 204, /* VPERMDYrm */ }, { /* 9748 */ 205, /* VPERMDYrr */ }, { /* 9749 */ 214, /* VPERMDZ256rm */ }, { /* 9750 */ 240, /* VPERMDZ256rmb */ }, { /* 9751 */ 241, /* VPERMDZ256rmbk */ }, { /* 9752 */ 242, /* VPERMDZ256rmbkz */ }, { /* 9753 */ 218, /* VPERMDZ256rmk */ }, { /* 9754 */ 219, /* VPERMDZ256rmkz */ }, { /* 9755 */ 220, /* VPERMDZ256rr */ }, { /* 9756 */ 221, /* VPERMDZ256rrk */ }, { /* 9757 */ 222, /* VPERMDZ256rrkz */ }, { /* 9758 */ 223, /* VPERMDZrm */ }, { /* 9759 */ 243, /* VPERMDZrmb */ }, { /* 9760 */ 244, /* VPERMDZrmbk */ }, { /* 9761 */ 245, /* VPERMDZrmbkz */ }, { /* 9762 */ 227, /* VPERMDZrmk */ }, { /* 9763 */ 228, /* VPERMDZrmkz */ }, { /* 9764 */ 229, /* VPERMDZrr */ }, { /* 9765 */ 233, /* VPERMDZrrk */ }, { /* 9766 */ 234, /* VPERMDZrrkz */ }, { /* 9767 */ 202, /* VPERMI2B128rm */ }, { /* 9768 */ 203, /* VPERMI2B128rmk */ }, { /* 9769 */ 203, /* VPERMI2B128rmkz */ }, { /* 9770 */ 530, /* VPERMI2B128rr */ }, { /* 9771 */ 212, /* VPERMI2B128rrk */ }, { /* 9772 */ 212, /* VPERMI2B128rrkz */ }, { /* 9773 */ 531, /* VPERMI2B256rm */ }, { /* 9774 */ 218, /* VPERMI2B256rmk */ }, { /* 9775 */ 218, /* VPERMI2B256rmkz */ }, { /* 9776 */ 533, /* VPERMI2B256rr */ }, { /* 9777 */ 221, /* VPERMI2B256rrk */ }, { /* 9778 */ 221, /* VPERMI2B256rrkz */ }, { /* 9779 */ 534, /* VPERMI2Brm */ }, { /* 9780 */ 227, /* VPERMI2Brmk */ }, { /* 9781 */ 227, /* VPERMI2Brmkz */ }, { /* 9782 */ 536, /* VPERMI2Brr */ }, { /* 9783 */ 233, /* VPERMI2Brrk */ }, { /* 9784 */ 233, /* VPERMI2Brrkz */ }, { /* 9785 */ 202, /* VPERMI2D128rm */ }, { /* 9786 */ 540, /* VPERMI2D128rmb */ }, { /* 9787 */ 238, /* VPERMI2D128rmbk */ }, { /* 9788 */ 238, /* VPERMI2D128rmbkz */ }, { /* 9789 */ 203, /* VPERMI2D128rmk */ }, { /* 9790 */ 203, /* VPERMI2D128rmkz */ }, { /* 9791 */ 530, /* VPERMI2D128rr */ }, { /* 9792 */ 212, /* VPERMI2D128rrk */ }, { /* 9793 */ 212, /* VPERMI2D128rrkz */ }, { /* 9794 */ 531, /* VPERMI2D256rm */ }, { /* 9795 */ 541, /* VPERMI2D256rmb */ }, { /* 9796 */ 241, /* VPERMI2D256rmbk */ }, { /* 9797 */ 241, /* VPERMI2D256rmbkz */ }, { /* 9798 */ 218, /* VPERMI2D256rmk */ }, { /* 9799 */ 218, /* VPERMI2D256rmkz */ }, { /* 9800 */ 533, /* VPERMI2D256rr */ }, { /* 9801 */ 221, /* VPERMI2D256rrk */ }, { /* 9802 */ 221, /* VPERMI2D256rrkz */ }, { /* 9803 */ 534, /* VPERMI2Drm */ }, { /* 9804 */ 542, /* VPERMI2Drmb */ }, { /* 9805 */ 244, /* VPERMI2Drmbk */ }, { /* 9806 */ 244, /* VPERMI2Drmbkz */ }, { /* 9807 */ 227, /* VPERMI2Drmk */ }, { /* 9808 */ 227, /* VPERMI2Drmkz */ }, { /* 9809 */ 536, /* VPERMI2Drr */ }, { /* 9810 */ 233, /* VPERMI2Drrk */ }, { /* 9811 */ 233, /* VPERMI2Drrkz */ }, { /* 9812 */ 202, /* VPERMI2PD128rm */ }, { /* 9813 */ 529, /* VPERMI2PD128rmb */ }, { /* 9814 */ 208, /* VPERMI2PD128rmbk */ }, { /* 9815 */ 208, /* VPERMI2PD128rmbkz */ }, { /* 9816 */ 203, /* VPERMI2PD128rmk */ }, { /* 9817 */ 203, /* VPERMI2PD128rmkz */ }, { /* 9818 */ 530, /* VPERMI2PD128rr */ }, { /* 9819 */ 212, /* VPERMI2PD128rrk */ }, { /* 9820 */ 212, /* VPERMI2PD128rrkz */ }, { /* 9821 */ 531, /* VPERMI2PD256rm */ }, { /* 9822 */ 532, /* VPERMI2PD256rmb */ }, { /* 9823 */ 216, /* VPERMI2PD256rmbk */ }, { /* 9824 */ 216, /* VPERMI2PD256rmbkz */ }, { /* 9825 */ 218, /* VPERMI2PD256rmk */ }, { /* 9826 */ 218, /* VPERMI2PD256rmkz */ }, { /* 9827 */ 533, /* VPERMI2PD256rr */ }, { /* 9828 */ 221, /* VPERMI2PD256rrk */ }, { /* 9829 */ 221, /* VPERMI2PD256rrkz */ }, { /* 9830 */ 534, /* VPERMI2PDrm */ }, { /* 9831 */ 535, /* VPERMI2PDrmb */ }, { /* 9832 */ 225, /* VPERMI2PDrmbk */ }, { /* 9833 */ 225, /* VPERMI2PDrmbkz */ }, { /* 9834 */ 227, /* VPERMI2PDrmk */ }, { /* 9835 */ 227, /* VPERMI2PDrmkz */ }, { /* 9836 */ 536, /* VPERMI2PDrr */ }, { /* 9837 */ 233, /* VPERMI2PDrrk */ }, { /* 9838 */ 233, /* VPERMI2PDrrkz */ }, { /* 9839 */ 202, /* VPERMI2PS128rm */ }, { /* 9840 */ 540, /* VPERMI2PS128rmb */ }, { /* 9841 */ 238, /* VPERMI2PS128rmbk */ }, { /* 9842 */ 238, /* VPERMI2PS128rmbkz */ }, { /* 9843 */ 203, /* VPERMI2PS128rmk */ }, { /* 9844 */ 203, /* VPERMI2PS128rmkz */ }, { /* 9845 */ 530, /* VPERMI2PS128rr */ }, { /* 9846 */ 212, /* VPERMI2PS128rrk */ }, { /* 9847 */ 212, /* VPERMI2PS128rrkz */ }, { /* 9848 */ 531, /* VPERMI2PS256rm */ }, { /* 9849 */ 541, /* VPERMI2PS256rmb */ }, { /* 9850 */ 241, /* VPERMI2PS256rmbk */ }, { /* 9851 */ 241, /* VPERMI2PS256rmbkz */ }, { /* 9852 */ 218, /* VPERMI2PS256rmk */ }, { /* 9853 */ 218, /* VPERMI2PS256rmkz */ }, { /* 9854 */ 533, /* VPERMI2PS256rr */ }, { /* 9855 */ 221, /* VPERMI2PS256rrk */ }, { /* 9856 */ 221, /* VPERMI2PS256rrkz */ }, { /* 9857 */ 534, /* VPERMI2PSrm */ }, { /* 9858 */ 542, /* VPERMI2PSrmb */ }, { /* 9859 */ 244, /* VPERMI2PSrmbk */ }, { /* 9860 */ 244, /* VPERMI2PSrmbkz */ }, { /* 9861 */ 227, /* VPERMI2PSrmk */ }, { /* 9862 */ 227, /* VPERMI2PSrmkz */ }, { /* 9863 */ 536, /* VPERMI2PSrr */ }, { /* 9864 */ 233, /* VPERMI2PSrrk */ }, { /* 9865 */ 233, /* VPERMI2PSrrkz */ }, { /* 9866 */ 202, /* VPERMI2Q128rm */ }, { /* 9867 */ 529, /* VPERMI2Q128rmb */ }, { /* 9868 */ 208, /* VPERMI2Q128rmbk */ }, { /* 9869 */ 208, /* VPERMI2Q128rmbkz */ }, { /* 9870 */ 203, /* VPERMI2Q128rmk */ }, { /* 9871 */ 203, /* VPERMI2Q128rmkz */ }, { /* 9872 */ 530, /* VPERMI2Q128rr */ }, { /* 9873 */ 212, /* VPERMI2Q128rrk */ }, { /* 9874 */ 212, /* VPERMI2Q128rrkz */ }, { /* 9875 */ 531, /* VPERMI2Q256rm */ }, { /* 9876 */ 532, /* VPERMI2Q256rmb */ }, { /* 9877 */ 216, /* VPERMI2Q256rmbk */ }, { /* 9878 */ 216, /* VPERMI2Q256rmbkz */ }, { /* 9879 */ 218, /* VPERMI2Q256rmk */ }, { /* 9880 */ 218, /* VPERMI2Q256rmkz */ }, { /* 9881 */ 533, /* VPERMI2Q256rr */ }, { /* 9882 */ 221, /* VPERMI2Q256rrk */ }, { /* 9883 */ 221, /* VPERMI2Q256rrkz */ }, { /* 9884 */ 534, /* VPERMI2Qrm */ }, { /* 9885 */ 535, /* VPERMI2Qrmb */ }, { /* 9886 */ 225, /* VPERMI2Qrmbk */ }, { /* 9887 */ 225, /* VPERMI2Qrmbkz */ }, { /* 9888 */ 227, /* VPERMI2Qrmk */ }, { /* 9889 */ 227, /* VPERMI2Qrmkz */ }, { /* 9890 */ 536, /* VPERMI2Qrr */ }, { /* 9891 */ 233, /* VPERMI2Qrrk */ }, { /* 9892 */ 233, /* VPERMI2Qrrkz */ }, { /* 9893 */ 202, /* VPERMI2W128rm */ }, { /* 9894 */ 203, /* VPERMI2W128rmk */ }, { /* 9895 */ 203, /* VPERMI2W128rmkz */ }, { /* 9896 */ 530, /* VPERMI2W128rr */ }, { /* 9897 */ 212, /* VPERMI2W128rrk */ }, { /* 9898 */ 212, /* VPERMI2W128rrkz */ }, { /* 9899 */ 531, /* VPERMI2W256rm */ }, { /* 9900 */ 218, /* VPERMI2W256rmk */ }, { /* 9901 */ 218, /* VPERMI2W256rmkz */ }, { /* 9902 */ 533, /* VPERMI2W256rr */ }, { /* 9903 */ 221, /* VPERMI2W256rrk */ }, { /* 9904 */ 221, /* VPERMI2W256rrkz */ }, { /* 9905 */ 534, /* VPERMI2Wrm */ }, { /* 9906 */ 227, /* VPERMI2Wrmk */ }, { /* 9907 */ 227, /* VPERMI2Wrmkz */ }, { /* 9908 */ 536, /* VPERMI2Wrr */ }, { /* 9909 */ 233, /* VPERMI2Wrrk */ }, { /* 9910 */ 233, /* VPERMI2Wrrkz */ }, { /* 9911 */ 783, /* VPERMIL2PDYmr */ }, { /* 9912 */ 784, /* VPERMIL2PDYrm */ }, { /* 9913 */ 785, /* VPERMIL2PDYrr */ }, { /* 9914 */ 786, /* VPERMIL2PDYrr_REV */ }, { /* 9915 */ 787, /* VPERMIL2PDmr */ }, { /* 9916 */ 788, /* VPERMIL2PDrm */ }, { /* 9917 */ 789, /* VPERMIL2PDrr */ }, { /* 9918 */ 790, /* VPERMIL2PDrr_REV */ }, { /* 9919 */ 783, /* VPERMIL2PSYmr */ }, { /* 9920 */ 784, /* VPERMIL2PSYrm */ }, { /* 9921 */ 785, /* VPERMIL2PSYrr */ }, { /* 9922 */ 786, /* VPERMIL2PSYrr_REV */ }, { /* 9923 */ 787, /* VPERMIL2PSmr */ }, { /* 9924 */ 788, /* VPERMIL2PSrm */ }, { /* 9925 */ 789, /* VPERMIL2PSrr */ }, { /* 9926 */ 790, /* VPERMIL2PSrr_REV */ }, { /* 9927 */ 791, /* VPERMILPDYmi */ }, { /* 9928 */ 792, /* VPERMILPDYri */ }, { /* 9929 */ 204, /* VPERMILPDYrm */ }, { /* 9930 */ 205, /* VPERMILPDYrr */ }, { /* 9931 */ 589, /* VPERMILPDZ128mbi */ }, { /* 9932 */ 590, /* VPERMILPDZ128mbik */ }, { /* 9933 */ 591, /* VPERMILPDZ128mbikz */ }, { /* 9934 */ 592, /* VPERMILPDZ128mi */ }, { /* 9935 */ 593, /* VPERMILPDZ128mik */ }, { /* 9936 */ 594, /* VPERMILPDZ128mikz */ }, { /* 9937 */ 595, /* VPERMILPDZ128ri */ }, { /* 9938 */ 596, /* VPERMILPDZ128rik */ }, { /* 9939 */ 597, /* VPERMILPDZ128rikz */ }, { /* 9940 */ 206, /* VPERMILPDZ128rm */ }, { /* 9941 */ 207, /* VPERMILPDZ128rmb */ }, { /* 9942 */ 208, /* VPERMILPDZ128rmbk */ }, { /* 9943 */ 209, /* VPERMILPDZ128rmbkz */ }, { /* 9944 */ 203, /* VPERMILPDZ128rmk */ }, { /* 9945 */ 210, /* VPERMILPDZ128rmkz */ }, { /* 9946 */ 211, /* VPERMILPDZ128rr */ }, { /* 9947 */ 212, /* VPERMILPDZ128rrk */ }, { /* 9948 */ 213, /* VPERMILPDZ128rrkz */ }, { /* 9949 */ 598, /* VPERMILPDZ256mbi */ }, { /* 9950 */ 599, /* VPERMILPDZ256mbik */ }, { /* 9951 */ 600, /* VPERMILPDZ256mbikz */ }, { /* 9952 */ 601, /* VPERMILPDZ256mi */ }, { /* 9953 */ 602, /* VPERMILPDZ256mik */ }, { /* 9954 */ 603, /* VPERMILPDZ256mikz */ }, { /* 9955 */ 604, /* VPERMILPDZ256ri */ }, { /* 9956 */ 605, /* VPERMILPDZ256rik */ }, { /* 9957 */ 606, /* VPERMILPDZ256rikz */ }, { /* 9958 */ 214, /* VPERMILPDZ256rm */ }, { /* 9959 */ 215, /* VPERMILPDZ256rmb */ }, { /* 9960 */ 216, /* VPERMILPDZ256rmbk */ }, { /* 9961 */ 217, /* VPERMILPDZ256rmbkz */ }, { /* 9962 */ 218, /* VPERMILPDZ256rmk */ }, { /* 9963 */ 219, /* VPERMILPDZ256rmkz */ }, { /* 9964 */ 220, /* VPERMILPDZ256rr */ }, { /* 9965 */ 221, /* VPERMILPDZ256rrk */ }, { /* 9966 */ 222, /* VPERMILPDZ256rrkz */ }, { /* 9967 */ 607, /* VPERMILPDZmbi */ }, { /* 9968 */ 608, /* VPERMILPDZmbik */ }, { /* 9969 */ 609, /* VPERMILPDZmbikz */ }, { /* 9970 */ 610, /* VPERMILPDZmi */ }, { /* 9971 */ 611, /* VPERMILPDZmik */ }, { /* 9972 */ 612, /* VPERMILPDZmikz */ }, { /* 9973 */ 613, /* VPERMILPDZri */ }, { /* 9974 */ 617, /* VPERMILPDZrik */ }, { /* 9975 */ 618, /* VPERMILPDZrikz */ }, { /* 9976 */ 223, /* VPERMILPDZrm */ }, { /* 9977 */ 224, /* VPERMILPDZrmb */ }, { /* 9978 */ 225, /* VPERMILPDZrmbk */ }, { /* 9979 */ 226, /* VPERMILPDZrmbkz */ }, { /* 9980 */ 227, /* VPERMILPDZrmk */ }, { /* 9981 */ 228, /* VPERMILPDZrmkz */ }, { /* 9982 */ 229, /* VPERMILPDZrr */ }, { /* 9983 */ 233, /* VPERMILPDZrrk */ }, { /* 9984 */ 234, /* VPERMILPDZrrkz */ }, { /* 9985 */ 32, /* VPERMILPDmi */ }, { /* 9986 */ 33, /* VPERMILPDri */ }, { /* 9987 */ 235, /* VPERMILPDrm */ }, { /* 9988 */ 236, /* VPERMILPDrr */ }, { /* 9989 */ 791, /* VPERMILPSYmi */ }, { /* 9990 */ 792, /* VPERMILPSYri */ }, { /* 9991 */ 204, /* VPERMILPSYrm */ }, { /* 9992 */ 205, /* VPERMILPSYrr */ }, { /* 9993 */ 619, /* VPERMILPSZ128mbi */ }, { /* 9994 */ 620, /* VPERMILPSZ128mbik */ }, { /* 9995 */ 621, /* VPERMILPSZ128mbikz */ }, { /* 9996 */ 592, /* VPERMILPSZ128mi */ }, { /* 9997 */ 593, /* VPERMILPSZ128mik */ }, { /* 9998 */ 594, /* VPERMILPSZ128mikz */ }, { /* 9999 */ 595, /* VPERMILPSZ128ri */ }, { /* 10000 */ 596, /* VPERMILPSZ128rik */ }, { /* 10001 */ 597, /* VPERMILPSZ128rikz */ }, { /* 10002 */ 206, /* VPERMILPSZ128rm */ }, { /* 10003 */ 237, /* VPERMILPSZ128rmb */ }, { /* 10004 */ 238, /* VPERMILPSZ128rmbk */ }, { /* 10005 */ 239, /* VPERMILPSZ128rmbkz */ }, { /* 10006 */ 203, /* VPERMILPSZ128rmk */ }, { /* 10007 */ 210, /* VPERMILPSZ128rmkz */ }, { /* 10008 */ 211, /* VPERMILPSZ128rr */ }, { /* 10009 */ 212, /* VPERMILPSZ128rrk */ }, { /* 10010 */ 213, /* VPERMILPSZ128rrkz */ }, { /* 10011 */ 622, /* VPERMILPSZ256mbi */ }, { /* 10012 */ 623, /* VPERMILPSZ256mbik */ }, { /* 10013 */ 624, /* VPERMILPSZ256mbikz */ }, { /* 10014 */ 601, /* VPERMILPSZ256mi */ }, { /* 10015 */ 602, /* VPERMILPSZ256mik */ }, { /* 10016 */ 603, /* VPERMILPSZ256mikz */ }, { /* 10017 */ 604, /* VPERMILPSZ256ri */ }, { /* 10018 */ 605, /* VPERMILPSZ256rik */ }, { /* 10019 */ 606, /* VPERMILPSZ256rikz */ }, { /* 10020 */ 214, /* VPERMILPSZ256rm */ }, { /* 10021 */ 240, /* VPERMILPSZ256rmb */ }, { /* 10022 */ 241, /* VPERMILPSZ256rmbk */ }, { /* 10023 */ 242, /* VPERMILPSZ256rmbkz */ }, { /* 10024 */ 218, /* VPERMILPSZ256rmk */ }, { /* 10025 */ 219, /* VPERMILPSZ256rmkz */ }, { /* 10026 */ 220, /* VPERMILPSZ256rr */ }, { /* 10027 */ 221, /* VPERMILPSZ256rrk */ }, { /* 10028 */ 222, /* VPERMILPSZ256rrkz */ }, { /* 10029 */ 625, /* VPERMILPSZmbi */ }, { /* 10030 */ 626, /* VPERMILPSZmbik */ }, { /* 10031 */ 627, /* VPERMILPSZmbikz */ }, { /* 10032 */ 610, /* VPERMILPSZmi */ }, { /* 10033 */ 611, /* VPERMILPSZmik */ }, { /* 10034 */ 612, /* VPERMILPSZmikz */ }, { /* 10035 */ 613, /* VPERMILPSZri */ }, { /* 10036 */ 617, /* VPERMILPSZrik */ }, { /* 10037 */ 618, /* VPERMILPSZrikz */ }, { /* 10038 */ 223, /* VPERMILPSZrm */ }, { /* 10039 */ 243, /* VPERMILPSZrmb */ }, { /* 10040 */ 244, /* VPERMILPSZrmbk */ }, { /* 10041 */ 245, /* VPERMILPSZrmbkz */ }, { /* 10042 */ 227, /* VPERMILPSZrmk */ }, { /* 10043 */ 228, /* VPERMILPSZrmkz */ }, { /* 10044 */ 229, /* VPERMILPSZrr */ }, { /* 10045 */ 233, /* VPERMILPSZrrk */ }, { /* 10046 */ 234, /* VPERMILPSZrrkz */ }, { /* 10047 */ 32, /* VPERMILPSmi */ }, { /* 10048 */ 33, /* VPERMILPSri */ }, { /* 10049 */ 235, /* VPERMILPSrm */ }, { /* 10050 */ 236, /* VPERMILPSrr */ }, { /* 10051 */ 791, /* VPERMPDYmi */ }, { /* 10052 */ 792, /* VPERMPDYri */ }, { /* 10053 */ 598, /* VPERMPDZ256mbi */ }, { /* 10054 */ 599, /* VPERMPDZ256mbik */ }, { /* 10055 */ 600, /* VPERMPDZ256mbikz */ }, { /* 10056 */ 601, /* VPERMPDZ256mi */ }, { /* 10057 */ 602, /* VPERMPDZ256mik */ }, { /* 10058 */ 603, /* VPERMPDZ256mikz */ }, { /* 10059 */ 604, /* VPERMPDZ256ri */ }, { /* 10060 */ 605, /* VPERMPDZ256rik */ }, { /* 10061 */ 606, /* VPERMPDZ256rikz */ }, { /* 10062 */ 214, /* VPERMPDZ256rm */ }, { /* 10063 */ 215, /* VPERMPDZ256rmb */ }, { /* 10064 */ 216, /* VPERMPDZ256rmbk */ }, { /* 10065 */ 217, /* VPERMPDZ256rmbkz */ }, { /* 10066 */ 218, /* VPERMPDZ256rmk */ }, { /* 10067 */ 219, /* VPERMPDZ256rmkz */ }, { /* 10068 */ 220, /* VPERMPDZ256rr */ }, { /* 10069 */ 221, /* VPERMPDZ256rrk */ }, { /* 10070 */ 222, /* VPERMPDZ256rrkz */ }, { /* 10071 */ 607, /* VPERMPDZmbi */ }, { /* 10072 */ 608, /* VPERMPDZmbik */ }, { /* 10073 */ 609, /* VPERMPDZmbikz */ }, { /* 10074 */ 610, /* VPERMPDZmi */ }, { /* 10075 */ 611, /* VPERMPDZmik */ }, { /* 10076 */ 612, /* VPERMPDZmikz */ }, { /* 10077 */ 613, /* VPERMPDZri */ }, { /* 10078 */ 617, /* VPERMPDZrik */ }, { /* 10079 */ 618, /* VPERMPDZrikz */ }, { /* 10080 */ 223, /* VPERMPDZrm */ }, { /* 10081 */ 224, /* VPERMPDZrmb */ }, { /* 10082 */ 225, /* VPERMPDZrmbk */ }, { /* 10083 */ 226, /* VPERMPDZrmbkz */ }, { /* 10084 */ 227, /* VPERMPDZrmk */ }, { /* 10085 */ 228, /* VPERMPDZrmkz */ }, { /* 10086 */ 229, /* VPERMPDZrr */ }, { /* 10087 */ 233, /* VPERMPDZrrk */ }, { /* 10088 */ 234, /* VPERMPDZrrkz */ }, { /* 10089 */ 204, /* VPERMPSYrm */ }, { /* 10090 */ 205, /* VPERMPSYrr */ }, { /* 10091 */ 214, /* VPERMPSZ256rm */ }, { /* 10092 */ 240, /* VPERMPSZ256rmb */ }, { /* 10093 */ 241, /* VPERMPSZ256rmbk */ }, { /* 10094 */ 242, /* VPERMPSZ256rmbkz */ }, { /* 10095 */ 218, /* VPERMPSZ256rmk */ }, { /* 10096 */ 219, /* VPERMPSZ256rmkz */ }, { /* 10097 */ 220, /* VPERMPSZ256rr */ }, { /* 10098 */ 221, /* VPERMPSZ256rrk */ }, { /* 10099 */ 222, /* VPERMPSZ256rrkz */ }, { /* 10100 */ 223, /* VPERMPSZrm */ }, { /* 10101 */ 243, /* VPERMPSZrmb */ }, { /* 10102 */ 244, /* VPERMPSZrmbk */ }, { /* 10103 */ 245, /* VPERMPSZrmbkz */ }, { /* 10104 */ 227, /* VPERMPSZrmk */ }, { /* 10105 */ 228, /* VPERMPSZrmkz */ }, { /* 10106 */ 229, /* VPERMPSZrr */ }, { /* 10107 */ 233, /* VPERMPSZrrk */ }, { /* 10108 */ 234, /* VPERMPSZrrkz */ }, { /* 10109 */ 791, /* VPERMQYmi */ }, { /* 10110 */ 792, /* VPERMQYri */ }, { /* 10111 */ 598, /* VPERMQZ256mbi */ }, { /* 10112 */ 599, /* VPERMQZ256mbik */ }, { /* 10113 */ 600, /* VPERMQZ256mbikz */ }, { /* 10114 */ 601, /* VPERMQZ256mi */ }, { /* 10115 */ 602, /* VPERMQZ256mik */ }, { /* 10116 */ 603, /* VPERMQZ256mikz */ }, { /* 10117 */ 604, /* VPERMQZ256ri */ }, { /* 10118 */ 605, /* VPERMQZ256rik */ }, { /* 10119 */ 606, /* VPERMQZ256rikz */ }, { /* 10120 */ 214, /* VPERMQZ256rm */ }, { /* 10121 */ 215, /* VPERMQZ256rmb */ }, { /* 10122 */ 216, /* VPERMQZ256rmbk */ }, { /* 10123 */ 217, /* VPERMQZ256rmbkz */ }, { /* 10124 */ 218, /* VPERMQZ256rmk */ }, { /* 10125 */ 219, /* VPERMQZ256rmkz */ }, { /* 10126 */ 220, /* VPERMQZ256rr */ }, { /* 10127 */ 221, /* VPERMQZ256rrk */ }, { /* 10128 */ 222, /* VPERMQZ256rrkz */ }, { /* 10129 */ 607, /* VPERMQZmbi */ }, { /* 10130 */ 608, /* VPERMQZmbik */ }, { /* 10131 */ 609, /* VPERMQZmbikz */ }, { /* 10132 */ 610, /* VPERMQZmi */ }, { /* 10133 */ 611, /* VPERMQZmik */ }, { /* 10134 */ 612, /* VPERMQZmikz */ }, { /* 10135 */ 613, /* VPERMQZri */ }, { /* 10136 */ 617, /* VPERMQZrik */ }, { /* 10137 */ 618, /* VPERMQZrikz */ }, { /* 10138 */ 223, /* VPERMQZrm */ }, { /* 10139 */ 224, /* VPERMQZrmb */ }, { /* 10140 */ 225, /* VPERMQZrmbk */ }, { /* 10141 */ 226, /* VPERMQZrmbkz */ }, { /* 10142 */ 227, /* VPERMQZrmk */ }, { /* 10143 */ 228, /* VPERMQZrmkz */ }, { /* 10144 */ 229, /* VPERMQZrr */ }, { /* 10145 */ 233, /* VPERMQZrrk */ }, { /* 10146 */ 234, /* VPERMQZrrkz */ }, { /* 10147 */ 202, /* VPERMT2B128rm */ }, { /* 10148 */ 203, /* VPERMT2B128rmk */ }, { /* 10149 */ 203, /* VPERMT2B128rmkz */ }, { /* 10150 */ 530, /* VPERMT2B128rr */ }, { /* 10151 */ 212, /* VPERMT2B128rrk */ }, { /* 10152 */ 212, /* VPERMT2B128rrkz */ }, { /* 10153 */ 531, /* VPERMT2B256rm */ }, { /* 10154 */ 218, /* VPERMT2B256rmk */ }, { /* 10155 */ 218, /* VPERMT2B256rmkz */ }, { /* 10156 */ 533, /* VPERMT2B256rr */ }, { /* 10157 */ 221, /* VPERMT2B256rrk */ }, { /* 10158 */ 221, /* VPERMT2B256rrkz */ }, { /* 10159 */ 534, /* VPERMT2Brm */ }, { /* 10160 */ 227, /* VPERMT2Brmk */ }, { /* 10161 */ 227, /* VPERMT2Brmkz */ }, { /* 10162 */ 536, /* VPERMT2Brr */ }, { /* 10163 */ 233, /* VPERMT2Brrk */ }, { /* 10164 */ 233, /* VPERMT2Brrkz */ }, { /* 10165 */ 202, /* VPERMT2D128rm */ }, { /* 10166 */ 540, /* VPERMT2D128rmb */ }, { /* 10167 */ 238, /* VPERMT2D128rmbk */ }, { /* 10168 */ 238, /* VPERMT2D128rmbkz */ }, { /* 10169 */ 203, /* VPERMT2D128rmk */ }, { /* 10170 */ 203, /* VPERMT2D128rmkz */ }, { /* 10171 */ 530, /* VPERMT2D128rr */ }, { /* 10172 */ 212, /* VPERMT2D128rrk */ }, { /* 10173 */ 212, /* VPERMT2D128rrkz */ }, { /* 10174 */ 531, /* VPERMT2D256rm */ }, { /* 10175 */ 541, /* VPERMT2D256rmb */ }, { /* 10176 */ 241, /* VPERMT2D256rmbk */ }, { /* 10177 */ 241, /* VPERMT2D256rmbkz */ }, { /* 10178 */ 218, /* VPERMT2D256rmk */ }, { /* 10179 */ 218, /* VPERMT2D256rmkz */ }, { /* 10180 */ 533, /* VPERMT2D256rr */ }, { /* 10181 */ 221, /* VPERMT2D256rrk */ }, { /* 10182 */ 221, /* VPERMT2D256rrkz */ }, { /* 10183 */ 534, /* VPERMT2Drm */ }, { /* 10184 */ 542, /* VPERMT2Drmb */ }, { /* 10185 */ 244, /* VPERMT2Drmbk */ }, { /* 10186 */ 244, /* VPERMT2Drmbkz */ }, { /* 10187 */ 227, /* VPERMT2Drmk */ }, { /* 10188 */ 227, /* VPERMT2Drmkz */ }, { /* 10189 */ 536, /* VPERMT2Drr */ }, { /* 10190 */ 233, /* VPERMT2Drrk */ }, { /* 10191 */ 233, /* VPERMT2Drrkz */ }, { /* 10192 */ 202, /* VPERMT2PD128rm */ }, { /* 10193 */ 529, /* VPERMT2PD128rmb */ }, { /* 10194 */ 208, /* VPERMT2PD128rmbk */ }, { /* 10195 */ 208, /* VPERMT2PD128rmbkz */ }, { /* 10196 */ 203, /* VPERMT2PD128rmk */ }, { /* 10197 */ 203, /* VPERMT2PD128rmkz */ }, { /* 10198 */ 530, /* VPERMT2PD128rr */ }, { /* 10199 */ 212, /* VPERMT2PD128rrk */ }, { /* 10200 */ 212, /* VPERMT2PD128rrkz */ }, { /* 10201 */ 531, /* VPERMT2PD256rm */ }, { /* 10202 */ 532, /* VPERMT2PD256rmb */ }, { /* 10203 */ 216, /* VPERMT2PD256rmbk */ }, { /* 10204 */ 216, /* VPERMT2PD256rmbkz */ }, { /* 10205 */ 218, /* VPERMT2PD256rmk */ }, { /* 10206 */ 218, /* VPERMT2PD256rmkz */ }, { /* 10207 */ 533, /* VPERMT2PD256rr */ }, { /* 10208 */ 221, /* VPERMT2PD256rrk */ }, { /* 10209 */ 221, /* VPERMT2PD256rrkz */ }, { /* 10210 */ 534, /* VPERMT2PDrm */ }, { /* 10211 */ 535, /* VPERMT2PDrmb */ }, { /* 10212 */ 225, /* VPERMT2PDrmbk */ }, { /* 10213 */ 225, /* VPERMT2PDrmbkz */ }, { /* 10214 */ 227, /* VPERMT2PDrmk */ }, { /* 10215 */ 227, /* VPERMT2PDrmkz */ }, { /* 10216 */ 536, /* VPERMT2PDrr */ }, { /* 10217 */ 233, /* VPERMT2PDrrk */ }, { /* 10218 */ 233, /* VPERMT2PDrrkz */ }, { /* 10219 */ 202, /* VPERMT2PS128rm */ }, { /* 10220 */ 540, /* VPERMT2PS128rmb */ }, { /* 10221 */ 238, /* VPERMT2PS128rmbk */ }, { /* 10222 */ 238, /* VPERMT2PS128rmbkz */ }, { /* 10223 */ 203, /* VPERMT2PS128rmk */ }, { /* 10224 */ 203, /* VPERMT2PS128rmkz */ }, { /* 10225 */ 530, /* VPERMT2PS128rr */ }, { /* 10226 */ 212, /* VPERMT2PS128rrk */ }, { /* 10227 */ 212, /* VPERMT2PS128rrkz */ }, { /* 10228 */ 531, /* VPERMT2PS256rm */ }, { /* 10229 */ 541, /* VPERMT2PS256rmb */ }, { /* 10230 */ 241, /* VPERMT2PS256rmbk */ }, { /* 10231 */ 241, /* VPERMT2PS256rmbkz */ }, { /* 10232 */ 218, /* VPERMT2PS256rmk */ }, { /* 10233 */ 218, /* VPERMT2PS256rmkz */ }, { /* 10234 */ 533, /* VPERMT2PS256rr */ }, { /* 10235 */ 221, /* VPERMT2PS256rrk */ }, { /* 10236 */ 221, /* VPERMT2PS256rrkz */ }, { /* 10237 */ 534, /* VPERMT2PSrm */ }, { /* 10238 */ 542, /* VPERMT2PSrmb */ }, { /* 10239 */ 244, /* VPERMT2PSrmbk */ }, { /* 10240 */ 244, /* VPERMT2PSrmbkz */ }, { /* 10241 */ 227, /* VPERMT2PSrmk */ }, { /* 10242 */ 227, /* VPERMT2PSrmkz */ }, { /* 10243 */ 536, /* VPERMT2PSrr */ }, { /* 10244 */ 233, /* VPERMT2PSrrk */ }, { /* 10245 */ 233, /* VPERMT2PSrrkz */ }, { /* 10246 */ 202, /* VPERMT2Q128rm */ }, { /* 10247 */ 529, /* VPERMT2Q128rmb */ }, { /* 10248 */ 208, /* VPERMT2Q128rmbk */ }, { /* 10249 */ 208, /* VPERMT2Q128rmbkz */ }, { /* 10250 */ 203, /* VPERMT2Q128rmk */ }, { /* 10251 */ 203, /* VPERMT2Q128rmkz */ }, { /* 10252 */ 530, /* VPERMT2Q128rr */ }, { /* 10253 */ 212, /* VPERMT2Q128rrk */ }, { /* 10254 */ 212, /* VPERMT2Q128rrkz */ }, { /* 10255 */ 531, /* VPERMT2Q256rm */ }, { /* 10256 */ 532, /* VPERMT2Q256rmb */ }, { /* 10257 */ 216, /* VPERMT2Q256rmbk */ }, { /* 10258 */ 216, /* VPERMT2Q256rmbkz */ }, { /* 10259 */ 218, /* VPERMT2Q256rmk */ }, { /* 10260 */ 218, /* VPERMT2Q256rmkz */ }, { /* 10261 */ 533, /* VPERMT2Q256rr */ }, { /* 10262 */ 221, /* VPERMT2Q256rrk */ }, { /* 10263 */ 221, /* VPERMT2Q256rrkz */ }, { /* 10264 */ 534, /* VPERMT2Qrm */ }, { /* 10265 */ 535, /* VPERMT2Qrmb */ }, { /* 10266 */ 225, /* VPERMT2Qrmbk */ }, { /* 10267 */ 225, /* VPERMT2Qrmbkz */ }, { /* 10268 */ 227, /* VPERMT2Qrmk */ }, { /* 10269 */ 227, /* VPERMT2Qrmkz */ }, { /* 10270 */ 536, /* VPERMT2Qrr */ }, { /* 10271 */ 233, /* VPERMT2Qrrk */ }, { /* 10272 */ 233, /* VPERMT2Qrrkz */ }, { /* 10273 */ 202, /* VPERMT2W128rm */ }, { /* 10274 */ 203, /* VPERMT2W128rmk */ }, { /* 10275 */ 203, /* VPERMT2W128rmkz */ }, { /* 10276 */ 530, /* VPERMT2W128rr */ }, { /* 10277 */ 212, /* VPERMT2W128rrk */ }, { /* 10278 */ 212, /* VPERMT2W128rrkz */ }, { /* 10279 */ 531, /* VPERMT2W256rm */ }, { /* 10280 */ 218, /* VPERMT2W256rmk */ }, { /* 10281 */ 218, /* VPERMT2W256rmkz */ }, { /* 10282 */ 533, /* VPERMT2W256rr */ }, { /* 10283 */ 221, /* VPERMT2W256rrk */ }, { /* 10284 */ 221, /* VPERMT2W256rrkz */ }, { /* 10285 */ 534, /* VPERMT2Wrm */ }, { /* 10286 */ 227, /* VPERMT2Wrmk */ }, { /* 10287 */ 227, /* VPERMT2Wrmkz */ }, { /* 10288 */ 536, /* VPERMT2Wrr */ }, { /* 10289 */ 233, /* VPERMT2Wrrk */ }, { /* 10290 */ 233, /* VPERMT2Wrrkz */ }, { /* 10291 */ 206, /* VPERMWZ128rm */ }, { /* 10292 */ 203, /* VPERMWZ128rmk */ }, { /* 10293 */ 210, /* VPERMWZ128rmkz */ }, { /* 10294 */ 211, /* VPERMWZ128rr */ }, { /* 10295 */ 212, /* VPERMWZ128rrk */ }, { /* 10296 */ 213, /* VPERMWZ128rrkz */ }, { /* 10297 */ 214, /* VPERMWZ256rm */ }, { /* 10298 */ 218, /* VPERMWZ256rmk */ }, { /* 10299 */ 219, /* VPERMWZ256rmkz */ }, { /* 10300 */ 220, /* VPERMWZ256rr */ }, { /* 10301 */ 221, /* VPERMWZ256rrk */ }, { /* 10302 */ 222, /* VPERMWZ256rrkz */ }, { /* 10303 */ 223, /* VPERMWZrm */ }, { /* 10304 */ 227, /* VPERMWZrmk */ }, { /* 10305 */ 228, /* VPERMWZrmkz */ }, { /* 10306 */ 229, /* VPERMWZrr */ }, { /* 10307 */ 233, /* VPERMWZrrk */ }, { /* 10308 */ 234, /* VPERMWZrrkz */ }, { /* 10309 */ 30, /* VPEXPANDBZ128rm */ }, { /* 10310 */ 688, /* VPEXPANDBZ128rmk */ }, { /* 10311 */ 689, /* VPEXPANDBZ128rmkz */ }, { /* 10312 */ 330, /* VPEXPANDBZ128rr */ }, { /* 10313 */ 331, /* VPEXPANDBZ128rrk */ }, { /* 10314 */ 332, /* VPEXPANDBZ128rrkz */ }, { /* 10315 */ 305, /* VPEXPANDBZ256rm */ }, { /* 10316 */ 690, /* VPEXPANDBZ256rmk */ }, { /* 10317 */ 691, /* VPEXPANDBZ256rmkz */ }, { /* 10318 */ 415, /* VPEXPANDBZ256rr */ }, { /* 10319 */ 416, /* VPEXPANDBZ256rrk */ }, { /* 10320 */ 417, /* VPEXPANDBZ256rrkz */ }, { /* 10321 */ 692, /* VPEXPANDBZrm */ }, { /* 10322 */ 693, /* VPEXPANDBZrmk */ }, { /* 10323 */ 694, /* VPEXPANDBZrmkz */ }, { /* 10324 */ 421, /* VPEXPANDBZrr */ }, { /* 10325 */ 425, /* VPEXPANDBZrrk */ }, { /* 10326 */ 426, /* VPEXPANDBZrrkz */ }, { /* 10327 */ 334, /* VPEXPANDDZ128rm */ }, { /* 10328 */ 335, /* VPEXPANDDZ128rmk */ }, { /* 10329 */ 336, /* VPEXPANDDZ128rmkz */ }, { /* 10330 */ 330, /* VPEXPANDDZ128rr */ }, { /* 10331 */ 331, /* VPEXPANDDZ128rrk */ }, { /* 10332 */ 332, /* VPEXPANDDZ128rrkz */ }, { /* 10333 */ 337, /* VPEXPANDDZ256rm */ }, { /* 10334 */ 338, /* VPEXPANDDZ256rmk */ }, { /* 10335 */ 339, /* VPEXPANDDZ256rmkz */ }, { /* 10336 */ 415, /* VPEXPANDDZ256rr */ }, { /* 10337 */ 416, /* VPEXPANDDZ256rrk */ }, { /* 10338 */ 417, /* VPEXPANDDZ256rrkz */ }, { /* 10339 */ 340, /* VPEXPANDDZrm */ }, { /* 10340 */ 341, /* VPEXPANDDZrmk */ }, { /* 10341 */ 342, /* VPEXPANDDZrmkz */ }, { /* 10342 */ 421, /* VPEXPANDDZrr */ }, { /* 10343 */ 425, /* VPEXPANDDZrrk */ }, { /* 10344 */ 426, /* VPEXPANDDZrrkz */ }, { /* 10345 */ 327, /* VPEXPANDQZ128rm */ }, { /* 10346 */ 328, /* VPEXPANDQZ128rmk */ }, { /* 10347 */ 329, /* VPEXPANDQZ128rmkz */ }, { /* 10348 */ 330, /* VPEXPANDQZ128rr */ }, { /* 10349 */ 331, /* VPEXPANDQZ128rrk */ }, { /* 10350 */ 332, /* VPEXPANDQZ128rrkz */ }, { /* 10351 */ 306, /* VPEXPANDQZ256rm */ }, { /* 10352 */ 307, /* VPEXPANDQZ256rmk */ }, { /* 10353 */ 308, /* VPEXPANDQZ256rmkz */ }, { /* 10354 */ 415, /* VPEXPANDQZ256rr */ }, { /* 10355 */ 416, /* VPEXPANDQZ256rrk */ }, { /* 10356 */ 417, /* VPEXPANDQZ256rrkz */ }, { /* 10357 */ 312, /* VPEXPANDQZrm */ }, { /* 10358 */ 313, /* VPEXPANDQZrmk */ }, { /* 10359 */ 314, /* VPEXPANDQZrmkz */ }, { /* 10360 */ 421, /* VPEXPANDQZrr */ }, { /* 10361 */ 425, /* VPEXPANDQZrrk */ }, { /* 10362 */ 426, /* VPEXPANDQZrrkz */ }, { /* 10363 */ 714, /* VPEXPANDWZ128rm */ }, { /* 10364 */ 715, /* VPEXPANDWZ128rmk */ }, { /* 10365 */ 716, /* VPEXPANDWZ128rmkz */ }, { /* 10366 */ 330, /* VPEXPANDWZ128rr */ }, { /* 10367 */ 331, /* VPEXPANDWZ128rrk */ }, { /* 10368 */ 332, /* VPEXPANDWZ128rrkz */ }, { /* 10369 */ 717, /* VPEXPANDWZ256rm */ }, { /* 10370 */ 718, /* VPEXPANDWZ256rmk */ }, { /* 10371 */ 719, /* VPEXPANDWZ256rmkz */ }, { /* 10372 */ 415, /* VPEXPANDWZ256rr */ }, { /* 10373 */ 416, /* VPEXPANDWZ256rrk */ }, { /* 10374 */ 417, /* VPEXPANDWZ256rrkz */ }, { /* 10375 */ 720, /* VPEXPANDWZrm */ }, { /* 10376 */ 721, /* VPEXPANDWZrmk */ }, { /* 10377 */ 722, /* VPEXPANDWZrmkz */ }, { /* 10378 */ 421, /* VPEXPANDWZrr */ }, { /* 10379 */ 425, /* VPEXPANDWZrrk */ }, { /* 10380 */ 426, /* VPEXPANDWZrrkz */ }, { /* 10381 */ 96, /* VPEXTRBZmr */ }, { /* 10382 */ 506, /* VPEXTRBZrr */ }, { /* 10383 */ 96, /* VPEXTRBmr */ }, { /* 10384 */ 97, /* VPEXTRBrr */ }, { /* 10385 */ 505, /* VPEXTRDZmr */ }, { /* 10386 */ 506, /* VPEXTRDZrr */ }, { /* 10387 */ 96, /* VPEXTRDmr */ }, { /* 10388 */ 97, /* VPEXTRDrr */ }, { /* 10389 */ 451, /* VPEXTRQZmr */ }, { /* 10390 */ 793, /* VPEXTRQZrr */ }, { /* 10391 */ 96, /* VPEXTRQmr */ }, { /* 10392 */ 180, /* VPEXTRQrr */ }, { /* 10393 */ 794, /* VPEXTRWZmr */ }, { /* 10394 */ 795, /* VPEXTRWZrr */ }, { /* 10395 */ 506, /* VPEXTRWZrr_REV */ }, { /* 10396 */ 96, /* VPEXTRWmr */ }, { /* 10397 */ 181, /* VPEXTRWrr */ }, { /* 10398 */ 97, /* VPEXTRWrr_REV */ }, { /* 10399 */ 577, /* VPGATHERDDYrm */ }, { /* 10400 */ 578, /* VPGATHERDDZ128rm */ }, { /* 10401 */ 579, /* VPGATHERDDZ256rm */ }, { /* 10402 */ 580, /* VPGATHERDDZrm */ }, { /* 10403 */ 576, /* VPGATHERDDrm */ }, { /* 10404 */ 572, /* VPGATHERDQYrm */ }, { /* 10405 */ 573, /* VPGATHERDQZ128rm */ }, { /* 10406 */ 574, /* VPGATHERDQZ256rm */ }, { /* 10407 */ 575, /* VPGATHERDQZrm */ }, { /* 10408 */ 576, /* VPGATHERDQrm */ }, { /* 10409 */ 586, /* VPGATHERQDYrm */ }, { /* 10410 */ 578, /* VPGATHERQDZ128rm */ }, { /* 10411 */ 587, /* VPGATHERQDZ256rm */ }, { /* 10412 */ 588, /* VPGATHERQDZrm */ }, { /* 10413 */ 576, /* VPGATHERQDrm */ }, { /* 10414 */ 577, /* VPGATHERQQYrm */ }, { /* 10415 */ 573, /* VPGATHERQQZ128rm */ }, { /* 10416 */ 584, /* VPGATHERQQZ256rm */ }, { /* 10417 */ 585, /* VPGATHERQQZrm */ }, { /* 10418 */ 576, /* VPGATHERQQrm */ }, { /* 10419 */ 30, /* VPHADDBDrm */ }, { /* 10420 */ 31, /* VPHADDBDrr */ }, { /* 10421 */ 30, /* VPHADDBQrm */ }, { /* 10422 */ 31, /* VPHADDBQrr */ }, { /* 10423 */ 30, /* VPHADDBWrm */ }, { /* 10424 */ 31, /* VPHADDBWrr */ }, { /* 10425 */ 30, /* VPHADDDQrm */ }, { /* 10426 */ 31, /* VPHADDDQrr */ }, { /* 10427 */ 204, /* VPHADDDYrm */ }, { /* 10428 */ 205, /* VPHADDDYrr */ }, { /* 10429 */ 235, /* VPHADDDrm */ }, { /* 10430 */ 236, /* VPHADDDrr */ }, { /* 10431 */ 204, /* VPHADDSWYrm */ }, { /* 10432 */ 205, /* VPHADDSWYrr */ }, { /* 10433 */ 235, /* VPHADDSWrm */ }, { /* 10434 */ 236, /* VPHADDSWrr */ }, { /* 10435 */ 30, /* VPHADDUBDrm */ }, { /* 10436 */ 31, /* VPHADDUBDrr */ }, { /* 10437 */ 30, /* VPHADDUBQrm */ }, { /* 10438 */ 31, /* VPHADDUBQrr */ }, { /* 10439 */ 30, /* VPHADDUBWrm */ }, { /* 10440 */ 31, /* VPHADDUBWrr */ }, { /* 10441 */ 30, /* VPHADDUDQrm */ }, { /* 10442 */ 31, /* VPHADDUDQrr */ }, { /* 10443 */ 30, /* VPHADDUWDrm */ }, { /* 10444 */ 31, /* VPHADDUWDrr */ }, { /* 10445 */ 30, /* VPHADDUWQrm */ }, { /* 10446 */ 31, /* VPHADDUWQrr */ }, { /* 10447 */ 30, /* VPHADDWDrm */ }, { /* 10448 */ 31, /* VPHADDWDrr */ }, { /* 10449 */ 30, /* VPHADDWQrm */ }, { /* 10450 */ 31, /* VPHADDWQrr */ }, { /* 10451 */ 204, /* VPHADDWYrm */ }, { /* 10452 */ 205, /* VPHADDWYrr */ }, { /* 10453 */ 235, /* VPHADDWrm */ }, { /* 10454 */ 236, /* VPHADDWrr */ }, { /* 10455 */ 30, /* VPHMINPOSUWrm */ }, { /* 10456 */ 31, /* VPHMINPOSUWrr */ }, { /* 10457 */ 30, /* VPHSUBBWrm */ }, { /* 10458 */ 31, /* VPHSUBBWrr */ }, { /* 10459 */ 30, /* VPHSUBDQrm */ }, { /* 10460 */ 31, /* VPHSUBDQrr */ }, { /* 10461 */ 204, /* VPHSUBDYrm */ }, { /* 10462 */ 205, /* VPHSUBDYrr */ }, { /* 10463 */ 235, /* VPHSUBDrm */ }, { /* 10464 */ 236, /* VPHSUBDrr */ }, { /* 10465 */ 204, /* VPHSUBSWYrm */ }, { /* 10466 */ 205, /* VPHSUBSWYrr */ }, { /* 10467 */ 235, /* VPHSUBSWrm */ }, { /* 10468 */ 236, /* VPHSUBSWrr */ }, { /* 10469 */ 30, /* VPHSUBWDrm */ }, { /* 10470 */ 31, /* VPHSUBWDrr */ }, { /* 10471 */ 204, /* VPHSUBWYrm */ }, { /* 10472 */ 205, /* VPHSUBWYrr */ }, { /* 10473 */ 235, /* VPHSUBWrm */ }, { /* 10474 */ 236, /* VPHSUBWrr */ }, { /* 10475 */ 299, /* VPINSRBZrm */ }, { /* 10476 */ 796, /* VPINSRBZrr */ }, { /* 10477 */ 299, /* VPINSRBrm */ }, { /* 10478 */ 797, /* VPINSRBrr */ }, { /* 10479 */ 261, /* VPINSRDZrm */ }, { /* 10480 */ 796, /* VPINSRDZrr */ }, { /* 10481 */ 299, /* VPINSRDrm */ }, { /* 10482 */ 797, /* VPINSRDrr */ }, { /* 10483 */ 288, /* VPINSRQZrm */ }, { /* 10484 */ 798, /* VPINSRQZrr */ }, { /* 10485 */ 299, /* VPINSRQrm */ }, { /* 10486 */ 799, /* VPINSRQrr */ }, { /* 10487 */ 800, /* VPINSRWZrm */ }, { /* 10488 */ 796, /* VPINSRWZrr */ }, { /* 10489 */ 299, /* VPINSRWrm */ }, { /* 10490 */ 797, /* VPINSRWrr */ }, { /* 10491 */ 409, /* VPLZCNTDZ128rm */ }, { /* 10492 */ 334, /* VPLZCNTDZ128rmb */ }, { /* 10493 */ 335, /* VPLZCNTDZ128rmbk */ }, { /* 10494 */ 336, /* VPLZCNTDZ128rmbkz */ }, { /* 10495 */ 410, /* VPLZCNTDZ128rmk */ }, { /* 10496 */ 411, /* VPLZCNTDZ128rmkz */ }, { /* 10497 */ 330, /* VPLZCNTDZ128rr */ }, { /* 10498 */ 331, /* VPLZCNTDZ128rrk */ }, { /* 10499 */ 332, /* VPLZCNTDZ128rrkz */ }, { /* 10500 */ 412, /* VPLZCNTDZ256rm */ }, { /* 10501 */ 337, /* VPLZCNTDZ256rmb */ }, { /* 10502 */ 338, /* VPLZCNTDZ256rmbk */ }, { /* 10503 */ 339, /* VPLZCNTDZ256rmbkz */ }, { /* 10504 */ 413, /* VPLZCNTDZ256rmk */ }, { /* 10505 */ 414, /* VPLZCNTDZ256rmkz */ }, { /* 10506 */ 415, /* VPLZCNTDZ256rr */ }, { /* 10507 */ 416, /* VPLZCNTDZ256rrk */ }, { /* 10508 */ 417, /* VPLZCNTDZ256rrkz */ }, { /* 10509 */ 418, /* VPLZCNTDZrm */ }, { /* 10510 */ 340, /* VPLZCNTDZrmb */ }, { /* 10511 */ 341, /* VPLZCNTDZrmbk */ }, { /* 10512 */ 342, /* VPLZCNTDZrmbkz */ }, { /* 10513 */ 419, /* VPLZCNTDZrmk */ }, { /* 10514 */ 420, /* VPLZCNTDZrmkz */ }, { /* 10515 */ 421, /* VPLZCNTDZrr */ }, { /* 10516 */ 425, /* VPLZCNTDZrrk */ }, { /* 10517 */ 426, /* VPLZCNTDZrrkz */ }, { /* 10518 */ 409, /* VPLZCNTQZ128rm */ }, { /* 10519 */ 327, /* VPLZCNTQZ128rmb */ }, { /* 10520 */ 328, /* VPLZCNTQZ128rmbk */ }, { /* 10521 */ 329, /* VPLZCNTQZ128rmbkz */ }, { /* 10522 */ 410, /* VPLZCNTQZ128rmk */ }, { /* 10523 */ 411, /* VPLZCNTQZ128rmkz */ }, { /* 10524 */ 330, /* VPLZCNTQZ128rr */ }, { /* 10525 */ 331, /* VPLZCNTQZ128rrk */ }, { /* 10526 */ 332, /* VPLZCNTQZ128rrkz */ }, { /* 10527 */ 412, /* VPLZCNTQZ256rm */ }, { /* 10528 */ 306, /* VPLZCNTQZ256rmb */ }, { /* 10529 */ 307, /* VPLZCNTQZ256rmbk */ }, { /* 10530 */ 308, /* VPLZCNTQZ256rmbkz */ }, { /* 10531 */ 413, /* VPLZCNTQZ256rmk */ }, { /* 10532 */ 414, /* VPLZCNTQZ256rmkz */ }, { /* 10533 */ 415, /* VPLZCNTQZ256rr */ }, { /* 10534 */ 416, /* VPLZCNTQZ256rrk */ }, { /* 10535 */ 417, /* VPLZCNTQZ256rrkz */ }, { /* 10536 */ 418, /* VPLZCNTQZrm */ }, { /* 10537 */ 312, /* VPLZCNTQZrmb */ }, { /* 10538 */ 313, /* VPLZCNTQZrmbk */ }, { /* 10539 */ 314, /* VPLZCNTQZrmbkz */ }, { /* 10540 */ 419, /* VPLZCNTQZrmk */ }, { /* 10541 */ 420, /* VPLZCNTQZrmkz */ }, { /* 10542 */ 421, /* VPLZCNTQZrr */ }, { /* 10543 */ 425, /* VPLZCNTQZrrk */ }, { /* 10544 */ 426, /* VPLZCNTQZrrkz */ }, { /* 10545 */ 303, /* VPMACSDDrm */ }, { /* 10546 */ 304, /* VPMACSDDrr */ }, { /* 10547 */ 303, /* VPMACSDQHrm */ }, { /* 10548 */ 304, /* VPMACSDQHrr */ }, { /* 10549 */ 303, /* VPMACSDQLrm */ }, { /* 10550 */ 304, /* VPMACSDQLrr */ }, { /* 10551 */ 303, /* VPMACSSDDrm */ }, { /* 10552 */ 304, /* VPMACSSDDrr */ }, { /* 10553 */ 303, /* VPMACSSDQHrm */ }, { /* 10554 */ 304, /* VPMACSSDQHrr */ }, { /* 10555 */ 303, /* VPMACSSDQLrm */ }, { /* 10556 */ 304, /* VPMACSSDQLrr */ }, { /* 10557 */ 303, /* VPMACSSWDrm */ }, { /* 10558 */ 304, /* VPMACSSWDrr */ }, { /* 10559 */ 303, /* VPMACSSWWrm */ }, { /* 10560 */ 304, /* VPMACSSWWrr */ }, { /* 10561 */ 303, /* VPMACSWDrm */ }, { /* 10562 */ 304, /* VPMACSWDrr */ }, { /* 10563 */ 303, /* VPMACSWWrm */ }, { /* 10564 */ 304, /* VPMACSWWrr */ }, { /* 10565 */ 303, /* VPMADCSSWDrm */ }, { /* 10566 */ 304, /* VPMADCSSWDrr */ }, { /* 10567 */ 303, /* VPMADCSWDrm */ }, { /* 10568 */ 304, /* VPMADCSWDrr */ }, { /* 10569 */ 202, /* VPMADD52HUQZ128m */ }, { /* 10570 */ 529, /* VPMADD52HUQZ128mb */ }, { /* 10571 */ 208, /* VPMADD52HUQZ128mbk */ }, { /* 10572 */ 208, /* VPMADD52HUQZ128mbkz */ }, { /* 10573 */ 203, /* VPMADD52HUQZ128mk */ }, { /* 10574 */ 203, /* VPMADD52HUQZ128mkz */ }, { /* 10575 */ 530, /* VPMADD52HUQZ128r */ }, { /* 10576 */ 212, /* VPMADD52HUQZ128rk */ }, { /* 10577 */ 212, /* VPMADD52HUQZ128rkz */ }, { /* 10578 */ 531, /* VPMADD52HUQZ256m */ }, { /* 10579 */ 532, /* VPMADD52HUQZ256mb */ }, { /* 10580 */ 216, /* VPMADD52HUQZ256mbk */ }, { /* 10581 */ 216, /* VPMADD52HUQZ256mbkz */ }, { /* 10582 */ 218, /* VPMADD52HUQZ256mk */ }, { /* 10583 */ 218, /* VPMADD52HUQZ256mkz */ }, { /* 10584 */ 533, /* VPMADD52HUQZ256r */ }, { /* 10585 */ 221, /* VPMADD52HUQZ256rk */ }, { /* 10586 */ 221, /* VPMADD52HUQZ256rkz */ }, { /* 10587 */ 534, /* VPMADD52HUQZm */ }, { /* 10588 */ 535, /* VPMADD52HUQZmb */ }, { /* 10589 */ 225, /* VPMADD52HUQZmbk */ }, { /* 10590 */ 225, /* VPMADD52HUQZmbkz */ }, { /* 10591 */ 227, /* VPMADD52HUQZmk */ }, { /* 10592 */ 227, /* VPMADD52HUQZmkz */ }, { /* 10593 */ 536, /* VPMADD52HUQZr */ }, { /* 10594 */ 233, /* VPMADD52HUQZrk */ }, { /* 10595 */ 233, /* VPMADD52HUQZrkz */ }, { /* 10596 */ 202, /* VPMADD52LUQZ128m */ }, { /* 10597 */ 529, /* VPMADD52LUQZ128mb */ }, { /* 10598 */ 208, /* VPMADD52LUQZ128mbk */ }, { /* 10599 */ 208, /* VPMADD52LUQZ128mbkz */ }, { /* 10600 */ 203, /* VPMADD52LUQZ128mk */ }, { /* 10601 */ 203, /* VPMADD52LUQZ128mkz */ }, { /* 10602 */ 530, /* VPMADD52LUQZ128r */ }, { /* 10603 */ 212, /* VPMADD52LUQZ128rk */ }, { /* 10604 */ 212, /* VPMADD52LUQZ128rkz */ }, { /* 10605 */ 531, /* VPMADD52LUQZ256m */ }, { /* 10606 */ 532, /* VPMADD52LUQZ256mb */ }, { /* 10607 */ 216, /* VPMADD52LUQZ256mbk */ }, { /* 10608 */ 216, /* VPMADD52LUQZ256mbkz */ }, { /* 10609 */ 218, /* VPMADD52LUQZ256mk */ }, { /* 10610 */ 218, /* VPMADD52LUQZ256mkz */ }, { /* 10611 */ 533, /* VPMADD52LUQZ256r */ }, { /* 10612 */ 221, /* VPMADD52LUQZ256rk */ }, { /* 10613 */ 221, /* VPMADD52LUQZ256rkz */ }, { /* 10614 */ 534, /* VPMADD52LUQZm */ }, { /* 10615 */ 535, /* VPMADD52LUQZmb */ }, { /* 10616 */ 225, /* VPMADD52LUQZmbk */ }, { /* 10617 */ 225, /* VPMADD52LUQZmbkz */ }, { /* 10618 */ 227, /* VPMADD52LUQZmk */ }, { /* 10619 */ 227, /* VPMADD52LUQZmkz */ }, { /* 10620 */ 536, /* VPMADD52LUQZr */ }, { /* 10621 */ 233, /* VPMADD52LUQZrk */ }, { /* 10622 */ 233, /* VPMADD52LUQZrkz */ }, { /* 10623 */ 204, /* VPMADDUBSWYrm */ }, { /* 10624 */ 205, /* VPMADDUBSWYrr */ }, { /* 10625 */ 206, /* VPMADDUBSWZ128rm */ }, { /* 10626 */ 203, /* VPMADDUBSWZ128rmk */ }, { /* 10627 */ 210, /* VPMADDUBSWZ128rmkz */ }, { /* 10628 */ 211, /* VPMADDUBSWZ128rr */ }, { /* 10629 */ 212, /* VPMADDUBSWZ128rrk */ }, { /* 10630 */ 213, /* VPMADDUBSWZ128rrkz */ }, { /* 10631 */ 214, /* VPMADDUBSWZ256rm */ }, { /* 10632 */ 218, /* VPMADDUBSWZ256rmk */ }, { /* 10633 */ 219, /* VPMADDUBSWZ256rmkz */ }, { /* 10634 */ 220, /* VPMADDUBSWZ256rr */ }, { /* 10635 */ 221, /* VPMADDUBSWZ256rrk */ }, { /* 10636 */ 222, /* VPMADDUBSWZ256rrkz */ }, { /* 10637 */ 223, /* VPMADDUBSWZrm */ }, { /* 10638 */ 227, /* VPMADDUBSWZrmk */ }, { /* 10639 */ 228, /* VPMADDUBSWZrmkz */ }, { /* 10640 */ 229, /* VPMADDUBSWZrr */ }, { /* 10641 */ 233, /* VPMADDUBSWZrrk */ }, { /* 10642 */ 234, /* VPMADDUBSWZrrkz */ }, { /* 10643 */ 235, /* VPMADDUBSWrm */ }, { /* 10644 */ 236, /* VPMADDUBSWrr */ }, { /* 10645 */ 204, /* VPMADDWDYrm */ }, { /* 10646 */ 205, /* VPMADDWDYrr */ }, { /* 10647 */ 206, /* VPMADDWDZ128rm */ }, { /* 10648 */ 203, /* VPMADDWDZ128rmk */ }, { /* 10649 */ 210, /* VPMADDWDZ128rmkz */ }, { /* 10650 */ 211, /* VPMADDWDZ128rr */ }, { /* 10651 */ 212, /* VPMADDWDZ128rrk */ }, { /* 10652 */ 213, /* VPMADDWDZ128rrkz */ }, { /* 10653 */ 214, /* VPMADDWDZ256rm */ }, { /* 10654 */ 218, /* VPMADDWDZ256rmk */ }, { /* 10655 */ 219, /* VPMADDWDZ256rmkz */ }, { /* 10656 */ 220, /* VPMADDWDZ256rr */ }, { /* 10657 */ 221, /* VPMADDWDZ256rrk */ }, { /* 10658 */ 222, /* VPMADDWDZ256rrkz */ }, { /* 10659 */ 223, /* VPMADDWDZrm */ }, { /* 10660 */ 227, /* VPMADDWDZrmk */ }, { /* 10661 */ 228, /* VPMADDWDZrmkz */ }, { /* 10662 */ 229, /* VPMADDWDZrr */ }, { /* 10663 */ 233, /* VPMADDWDZrrk */ }, { /* 10664 */ 234, /* VPMADDWDZrrkz */ }, { /* 10665 */ 235, /* VPMADDWDrm */ }, { /* 10666 */ 236, /* VPMADDWDrr */ }, { /* 10667 */ 661, /* VPMASKMOVDYmr */ }, { /* 10668 */ 204, /* VPMASKMOVDYrm */ }, { /* 10669 */ 662, /* VPMASKMOVDmr */ }, { /* 10670 */ 235, /* VPMASKMOVDrm */ }, { /* 10671 */ 661, /* VPMASKMOVQYmr */ }, { /* 10672 */ 204, /* VPMASKMOVQYrm */ }, { /* 10673 */ 662, /* VPMASKMOVQmr */ }, { /* 10674 */ 235, /* VPMASKMOVQrm */ }, { /* 10675 */ 204, /* VPMAXSBYrm */ }, { /* 10676 */ 205, /* VPMAXSBYrr */ }, { /* 10677 */ 206, /* VPMAXSBZ128rm */ }, { /* 10678 */ 203, /* VPMAXSBZ128rmk */ }, { /* 10679 */ 210, /* VPMAXSBZ128rmkz */ }, { /* 10680 */ 211, /* VPMAXSBZ128rr */ }, { /* 10681 */ 212, /* VPMAXSBZ128rrk */ }, { /* 10682 */ 213, /* VPMAXSBZ128rrkz */ }, { /* 10683 */ 214, /* VPMAXSBZ256rm */ }, { /* 10684 */ 218, /* VPMAXSBZ256rmk */ }, { /* 10685 */ 219, /* VPMAXSBZ256rmkz */ }, { /* 10686 */ 220, /* VPMAXSBZ256rr */ }, { /* 10687 */ 221, /* VPMAXSBZ256rrk */ }, { /* 10688 */ 222, /* VPMAXSBZ256rrkz */ }, { /* 10689 */ 223, /* VPMAXSBZrm */ }, { /* 10690 */ 227, /* VPMAXSBZrmk */ }, { /* 10691 */ 228, /* VPMAXSBZrmkz */ }, { /* 10692 */ 229, /* VPMAXSBZrr */ }, { /* 10693 */ 233, /* VPMAXSBZrrk */ }, { /* 10694 */ 234, /* VPMAXSBZrrkz */ }, { /* 10695 */ 235, /* VPMAXSBrm */ }, { /* 10696 */ 236, /* VPMAXSBrr */ }, { /* 10697 */ 204, /* VPMAXSDYrm */ }, { /* 10698 */ 205, /* VPMAXSDYrr */ }, { /* 10699 */ 206, /* VPMAXSDZ128rm */ }, { /* 10700 */ 237, /* VPMAXSDZ128rmb */ }, { /* 10701 */ 238, /* VPMAXSDZ128rmbk */ }, { /* 10702 */ 239, /* VPMAXSDZ128rmbkz */ }, { /* 10703 */ 203, /* VPMAXSDZ128rmk */ }, { /* 10704 */ 210, /* VPMAXSDZ128rmkz */ }, { /* 10705 */ 211, /* VPMAXSDZ128rr */ }, { /* 10706 */ 212, /* VPMAXSDZ128rrk */ }, { /* 10707 */ 213, /* VPMAXSDZ128rrkz */ }, { /* 10708 */ 214, /* VPMAXSDZ256rm */ }, { /* 10709 */ 240, /* VPMAXSDZ256rmb */ }, { /* 10710 */ 241, /* VPMAXSDZ256rmbk */ }, { /* 10711 */ 242, /* VPMAXSDZ256rmbkz */ }, { /* 10712 */ 218, /* VPMAXSDZ256rmk */ }, { /* 10713 */ 219, /* VPMAXSDZ256rmkz */ }, { /* 10714 */ 220, /* VPMAXSDZ256rr */ }, { /* 10715 */ 221, /* VPMAXSDZ256rrk */ }, { /* 10716 */ 222, /* VPMAXSDZ256rrkz */ }, { /* 10717 */ 223, /* VPMAXSDZrm */ }, { /* 10718 */ 243, /* VPMAXSDZrmb */ }, { /* 10719 */ 244, /* VPMAXSDZrmbk */ }, { /* 10720 */ 245, /* VPMAXSDZrmbkz */ }, { /* 10721 */ 227, /* VPMAXSDZrmk */ }, { /* 10722 */ 228, /* VPMAXSDZrmkz */ }, { /* 10723 */ 229, /* VPMAXSDZrr */ }, { /* 10724 */ 233, /* VPMAXSDZrrk */ }, { /* 10725 */ 234, /* VPMAXSDZrrkz */ }, { /* 10726 */ 235, /* VPMAXSDrm */ }, { /* 10727 */ 236, /* VPMAXSDrr */ }, { /* 10728 */ 206, /* VPMAXSQZ128rm */ }, { /* 10729 */ 207, /* VPMAXSQZ128rmb */ }, { /* 10730 */ 208, /* VPMAXSQZ128rmbk */ }, { /* 10731 */ 209, /* VPMAXSQZ128rmbkz */ }, { /* 10732 */ 203, /* VPMAXSQZ128rmk */ }, { /* 10733 */ 210, /* VPMAXSQZ128rmkz */ }, { /* 10734 */ 211, /* VPMAXSQZ128rr */ }, { /* 10735 */ 212, /* VPMAXSQZ128rrk */ }, { /* 10736 */ 213, /* VPMAXSQZ128rrkz */ }, { /* 10737 */ 214, /* VPMAXSQZ256rm */ }, { /* 10738 */ 215, /* VPMAXSQZ256rmb */ }, { /* 10739 */ 216, /* VPMAXSQZ256rmbk */ }, { /* 10740 */ 217, /* VPMAXSQZ256rmbkz */ }, { /* 10741 */ 218, /* VPMAXSQZ256rmk */ }, { /* 10742 */ 219, /* VPMAXSQZ256rmkz */ }, { /* 10743 */ 220, /* VPMAXSQZ256rr */ }, { /* 10744 */ 221, /* VPMAXSQZ256rrk */ }, { /* 10745 */ 222, /* VPMAXSQZ256rrkz */ }, { /* 10746 */ 223, /* VPMAXSQZrm */ }, { /* 10747 */ 224, /* VPMAXSQZrmb */ }, { /* 10748 */ 225, /* VPMAXSQZrmbk */ }, { /* 10749 */ 226, /* VPMAXSQZrmbkz */ }, { /* 10750 */ 227, /* VPMAXSQZrmk */ }, { /* 10751 */ 228, /* VPMAXSQZrmkz */ }, { /* 10752 */ 229, /* VPMAXSQZrr */ }, { /* 10753 */ 233, /* VPMAXSQZrrk */ }, { /* 10754 */ 234, /* VPMAXSQZrrkz */ }, { /* 10755 */ 204, /* VPMAXSWYrm */ }, { /* 10756 */ 205, /* VPMAXSWYrr */ }, { /* 10757 */ 206, /* VPMAXSWZ128rm */ }, { /* 10758 */ 203, /* VPMAXSWZ128rmk */ }, { /* 10759 */ 210, /* VPMAXSWZ128rmkz */ }, { /* 10760 */ 211, /* VPMAXSWZ128rr */ }, { /* 10761 */ 212, /* VPMAXSWZ128rrk */ }, { /* 10762 */ 213, /* VPMAXSWZ128rrkz */ }, { /* 10763 */ 214, /* VPMAXSWZ256rm */ }, { /* 10764 */ 218, /* VPMAXSWZ256rmk */ }, { /* 10765 */ 219, /* VPMAXSWZ256rmkz */ }, { /* 10766 */ 220, /* VPMAXSWZ256rr */ }, { /* 10767 */ 221, /* VPMAXSWZ256rrk */ }, { /* 10768 */ 222, /* VPMAXSWZ256rrkz */ }, { /* 10769 */ 223, /* VPMAXSWZrm */ }, { /* 10770 */ 227, /* VPMAXSWZrmk */ }, { /* 10771 */ 228, /* VPMAXSWZrmkz */ }, { /* 10772 */ 229, /* VPMAXSWZrr */ }, { /* 10773 */ 233, /* VPMAXSWZrrk */ }, { /* 10774 */ 234, /* VPMAXSWZrrkz */ }, { /* 10775 */ 235, /* VPMAXSWrm */ }, { /* 10776 */ 236, /* VPMAXSWrr */ }, { /* 10777 */ 204, /* VPMAXUBYrm */ }, { /* 10778 */ 205, /* VPMAXUBYrr */ }, { /* 10779 */ 206, /* VPMAXUBZ128rm */ }, { /* 10780 */ 203, /* VPMAXUBZ128rmk */ }, { /* 10781 */ 210, /* VPMAXUBZ128rmkz */ }, { /* 10782 */ 211, /* VPMAXUBZ128rr */ }, { /* 10783 */ 212, /* VPMAXUBZ128rrk */ }, { /* 10784 */ 213, /* VPMAXUBZ128rrkz */ }, { /* 10785 */ 214, /* VPMAXUBZ256rm */ }, { /* 10786 */ 218, /* VPMAXUBZ256rmk */ }, { /* 10787 */ 219, /* VPMAXUBZ256rmkz */ }, { /* 10788 */ 220, /* VPMAXUBZ256rr */ }, { /* 10789 */ 221, /* VPMAXUBZ256rrk */ }, { /* 10790 */ 222, /* VPMAXUBZ256rrkz */ }, { /* 10791 */ 223, /* VPMAXUBZrm */ }, { /* 10792 */ 227, /* VPMAXUBZrmk */ }, { /* 10793 */ 228, /* VPMAXUBZrmkz */ }, { /* 10794 */ 229, /* VPMAXUBZrr */ }, { /* 10795 */ 233, /* VPMAXUBZrrk */ }, { /* 10796 */ 234, /* VPMAXUBZrrkz */ }, { /* 10797 */ 235, /* VPMAXUBrm */ }, { /* 10798 */ 236, /* VPMAXUBrr */ }, { /* 10799 */ 204, /* VPMAXUDYrm */ }, { /* 10800 */ 205, /* VPMAXUDYrr */ }, { /* 10801 */ 206, /* VPMAXUDZ128rm */ }, { /* 10802 */ 237, /* VPMAXUDZ128rmb */ }, { /* 10803 */ 238, /* VPMAXUDZ128rmbk */ }, { /* 10804 */ 239, /* VPMAXUDZ128rmbkz */ }, { /* 10805 */ 203, /* VPMAXUDZ128rmk */ }, { /* 10806 */ 210, /* VPMAXUDZ128rmkz */ }, { /* 10807 */ 211, /* VPMAXUDZ128rr */ }, { /* 10808 */ 212, /* VPMAXUDZ128rrk */ }, { /* 10809 */ 213, /* VPMAXUDZ128rrkz */ }, { /* 10810 */ 214, /* VPMAXUDZ256rm */ }, { /* 10811 */ 240, /* VPMAXUDZ256rmb */ }, { /* 10812 */ 241, /* VPMAXUDZ256rmbk */ }, { /* 10813 */ 242, /* VPMAXUDZ256rmbkz */ }, { /* 10814 */ 218, /* VPMAXUDZ256rmk */ }, { /* 10815 */ 219, /* VPMAXUDZ256rmkz */ }, { /* 10816 */ 220, /* VPMAXUDZ256rr */ }, { /* 10817 */ 221, /* VPMAXUDZ256rrk */ }, { /* 10818 */ 222, /* VPMAXUDZ256rrkz */ }, { /* 10819 */ 223, /* VPMAXUDZrm */ }, { /* 10820 */ 243, /* VPMAXUDZrmb */ }, { /* 10821 */ 244, /* VPMAXUDZrmbk */ }, { /* 10822 */ 245, /* VPMAXUDZrmbkz */ }, { /* 10823 */ 227, /* VPMAXUDZrmk */ }, { /* 10824 */ 228, /* VPMAXUDZrmkz */ }, { /* 10825 */ 229, /* VPMAXUDZrr */ }, { /* 10826 */ 233, /* VPMAXUDZrrk */ }, { /* 10827 */ 234, /* VPMAXUDZrrkz */ }, { /* 10828 */ 235, /* VPMAXUDrm */ }, { /* 10829 */ 236, /* VPMAXUDrr */ }, { /* 10830 */ 206, /* VPMAXUQZ128rm */ }, { /* 10831 */ 207, /* VPMAXUQZ128rmb */ }, { /* 10832 */ 208, /* VPMAXUQZ128rmbk */ }, { /* 10833 */ 209, /* VPMAXUQZ128rmbkz */ }, { /* 10834 */ 203, /* VPMAXUQZ128rmk */ }, { /* 10835 */ 210, /* VPMAXUQZ128rmkz */ }, { /* 10836 */ 211, /* VPMAXUQZ128rr */ }, { /* 10837 */ 212, /* VPMAXUQZ128rrk */ }, { /* 10838 */ 213, /* VPMAXUQZ128rrkz */ }, { /* 10839 */ 214, /* VPMAXUQZ256rm */ }, { /* 10840 */ 215, /* VPMAXUQZ256rmb */ }, { /* 10841 */ 216, /* VPMAXUQZ256rmbk */ }, { /* 10842 */ 217, /* VPMAXUQZ256rmbkz */ }, { /* 10843 */ 218, /* VPMAXUQZ256rmk */ }, { /* 10844 */ 219, /* VPMAXUQZ256rmkz */ }, { /* 10845 */ 220, /* VPMAXUQZ256rr */ }, { /* 10846 */ 221, /* VPMAXUQZ256rrk */ }, { /* 10847 */ 222, /* VPMAXUQZ256rrkz */ }, { /* 10848 */ 223, /* VPMAXUQZrm */ }, { /* 10849 */ 224, /* VPMAXUQZrmb */ }, { /* 10850 */ 225, /* VPMAXUQZrmbk */ }, { /* 10851 */ 226, /* VPMAXUQZrmbkz */ }, { /* 10852 */ 227, /* VPMAXUQZrmk */ }, { /* 10853 */ 228, /* VPMAXUQZrmkz */ }, { /* 10854 */ 229, /* VPMAXUQZrr */ }, { /* 10855 */ 233, /* VPMAXUQZrrk */ }, { /* 10856 */ 234, /* VPMAXUQZrrkz */ }, { /* 10857 */ 204, /* VPMAXUWYrm */ }, { /* 10858 */ 205, /* VPMAXUWYrr */ }, { /* 10859 */ 206, /* VPMAXUWZ128rm */ }, { /* 10860 */ 203, /* VPMAXUWZ128rmk */ }, { /* 10861 */ 210, /* VPMAXUWZ128rmkz */ }, { /* 10862 */ 211, /* VPMAXUWZ128rr */ }, { /* 10863 */ 212, /* VPMAXUWZ128rrk */ }, { /* 10864 */ 213, /* VPMAXUWZ128rrkz */ }, { /* 10865 */ 214, /* VPMAXUWZ256rm */ }, { /* 10866 */ 218, /* VPMAXUWZ256rmk */ }, { /* 10867 */ 219, /* VPMAXUWZ256rmkz */ }, { /* 10868 */ 220, /* VPMAXUWZ256rr */ }, { /* 10869 */ 221, /* VPMAXUWZ256rrk */ }, { /* 10870 */ 222, /* VPMAXUWZ256rrkz */ }, { /* 10871 */ 223, /* VPMAXUWZrm */ }, { /* 10872 */ 227, /* VPMAXUWZrmk */ }, { /* 10873 */ 228, /* VPMAXUWZrmkz */ }, { /* 10874 */ 229, /* VPMAXUWZrr */ }, { /* 10875 */ 233, /* VPMAXUWZrrk */ }, { /* 10876 */ 234, /* VPMAXUWZrrkz */ }, { /* 10877 */ 235, /* VPMAXUWrm */ }, { /* 10878 */ 236, /* VPMAXUWrr */ }, { /* 10879 */ 204, /* VPMINSBYrm */ }, { /* 10880 */ 205, /* VPMINSBYrr */ }, { /* 10881 */ 206, /* VPMINSBZ128rm */ }, { /* 10882 */ 203, /* VPMINSBZ128rmk */ }, { /* 10883 */ 210, /* VPMINSBZ128rmkz */ }, { /* 10884 */ 211, /* VPMINSBZ128rr */ }, { /* 10885 */ 212, /* VPMINSBZ128rrk */ }, { /* 10886 */ 213, /* VPMINSBZ128rrkz */ }, { /* 10887 */ 214, /* VPMINSBZ256rm */ }, { /* 10888 */ 218, /* VPMINSBZ256rmk */ }, { /* 10889 */ 219, /* VPMINSBZ256rmkz */ }, { /* 10890 */ 220, /* VPMINSBZ256rr */ }, { /* 10891 */ 221, /* VPMINSBZ256rrk */ }, { /* 10892 */ 222, /* VPMINSBZ256rrkz */ }, { /* 10893 */ 223, /* VPMINSBZrm */ }, { /* 10894 */ 227, /* VPMINSBZrmk */ }, { /* 10895 */ 228, /* VPMINSBZrmkz */ }, { /* 10896 */ 229, /* VPMINSBZrr */ }, { /* 10897 */ 233, /* VPMINSBZrrk */ }, { /* 10898 */ 234, /* VPMINSBZrrkz */ }, { /* 10899 */ 235, /* VPMINSBrm */ }, { /* 10900 */ 236, /* VPMINSBrr */ }, { /* 10901 */ 204, /* VPMINSDYrm */ }, { /* 10902 */ 205, /* VPMINSDYrr */ }, { /* 10903 */ 206, /* VPMINSDZ128rm */ }, { /* 10904 */ 237, /* VPMINSDZ128rmb */ }, { /* 10905 */ 238, /* VPMINSDZ128rmbk */ }, { /* 10906 */ 239, /* VPMINSDZ128rmbkz */ }, { /* 10907 */ 203, /* VPMINSDZ128rmk */ }, { /* 10908 */ 210, /* VPMINSDZ128rmkz */ }, { /* 10909 */ 211, /* VPMINSDZ128rr */ }, { /* 10910 */ 212, /* VPMINSDZ128rrk */ }, { /* 10911 */ 213, /* VPMINSDZ128rrkz */ }, { /* 10912 */ 214, /* VPMINSDZ256rm */ }, { /* 10913 */ 240, /* VPMINSDZ256rmb */ }, { /* 10914 */ 241, /* VPMINSDZ256rmbk */ }, { /* 10915 */ 242, /* VPMINSDZ256rmbkz */ }, { /* 10916 */ 218, /* VPMINSDZ256rmk */ }, { /* 10917 */ 219, /* VPMINSDZ256rmkz */ }, { /* 10918 */ 220, /* VPMINSDZ256rr */ }, { /* 10919 */ 221, /* VPMINSDZ256rrk */ }, { /* 10920 */ 222, /* VPMINSDZ256rrkz */ }, { /* 10921 */ 223, /* VPMINSDZrm */ }, { /* 10922 */ 243, /* VPMINSDZrmb */ }, { /* 10923 */ 244, /* VPMINSDZrmbk */ }, { /* 10924 */ 245, /* VPMINSDZrmbkz */ }, { /* 10925 */ 227, /* VPMINSDZrmk */ }, { /* 10926 */ 228, /* VPMINSDZrmkz */ }, { /* 10927 */ 229, /* VPMINSDZrr */ }, { /* 10928 */ 233, /* VPMINSDZrrk */ }, { /* 10929 */ 234, /* VPMINSDZrrkz */ }, { /* 10930 */ 235, /* VPMINSDrm */ }, { /* 10931 */ 236, /* VPMINSDrr */ }, { /* 10932 */ 206, /* VPMINSQZ128rm */ }, { /* 10933 */ 207, /* VPMINSQZ128rmb */ }, { /* 10934 */ 208, /* VPMINSQZ128rmbk */ }, { /* 10935 */ 209, /* VPMINSQZ128rmbkz */ }, { /* 10936 */ 203, /* VPMINSQZ128rmk */ }, { /* 10937 */ 210, /* VPMINSQZ128rmkz */ }, { /* 10938 */ 211, /* VPMINSQZ128rr */ }, { /* 10939 */ 212, /* VPMINSQZ128rrk */ }, { /* 10940 */ 213, /* VPMINSQZ128rrkz */ }, { /* 10941 */ 214, /* VPMINSQZ256rm */ }, { /* 10942 */ 215, /* VPMINSQZ256rmb */ }, { /* 10943 */ 216, /* VPMINSQZ256rmbk */ }, { /* 10944 */ 217, /* VPMINSQZ256rmbkz */ }, { /* 10945 */ 218, /* VPMINSQZ256rmk */ }, { /* 10946 */ 219, /* VPMINSQZ256rmkz */ }, { /* 10947 */ 220, /* VPMINSQZ256rr */ }, { /* 10948 */ 221, /* VPMINSQZ256rrk */ }, { /* 10949 */ 222, /* VPMINSQZ256rrkz */ }, { /* 10950 */ 223, /* VPMINSQZrm */ }, { /* 10951 */ 224, /* VPMINSQZrmb */ }, { /* 10952 */ 225, /* VPMINSQZrmbk */ }, { /* 10953 */ 226, /* VPMINSQZrmbkz */ }, { /* 10954 */ 227, /* VPMINSQZrmk */ }, { /* 10955 */ 228, /* VPMINSQZrmkz */ }, { /* 10956 */ 229, /* VPMINSQZrr */ }, { /* 10957 */ 233, /* VPMINSQZrrk */ }, { /* 10958 */ 234, /* VPMINSQZrrkz */ }, { /* 10959 */ 204, /* VPMINSWYrm */ }, { /* 10960 */ 205, /* VPMINSWYrr */ }, { /* 10961 */ 206, /* VPMINSWZ128rm */ }, { /* 10962 */ 203, /* VPMINSWZ128rmk */ }, { /* 10963 */ 210, /* VPMINSWZ128rmkz */ }, { /* 10964 */ 211, /* VPMINSWZ128rr */ }, { /* 10965 */ 212, /* VPMINSWZ128rrk */ }, { /* 10966 */ 213, /* VPMINSWZ128rrkz */ }, { /* 10967 */ 214, /* VPMINSWZ256rm */ }, { /* 10968 */ 218, /* VPMINSWZ256rmk */ }, { /* 10969 */ 219, /* VPMINSWZ256rmkz */ }, { /* 10970 */ 220, /* VPMINSWZ256rr */ }, { /* 10971 */ 221, /* VPMINSWZ256rrk */ }, { /* 10972 */ 222, /* VPMINSWZ256rrkz */ }, { /* 10973 */ 223, /* VPMINSWZrm */ }, { /* 10974 */ 227, /* VPMINSWZrmk */ }, { /* 10975 */ 228, /* VPMINSWZrmkz */ }, { /* 10976 */ 229, /* VPMINSWZrr */ }, { /* 10977 */ 233, /* VPMINSWZrrk */ }, { /* 10978 */ 234, /* VPMINSWZrrkz */ }, { /* 10979 */ 235, /* VPMINSWrm */ }, { /* 10980 */ 236, /* VPMINSWrr */ }, { /* 10981 */ 204, /* VPMINUBYrm */ }, { /* 10982 */ 205, /* VPMINUBYrr */ }, { /* 10983 */ 206, /* VPMINUBZ128rm */ }, { /* 10984 */ 203, /* VPMINUBZ128rmk */ }, { /* 10985 */ 210, /* VPMINUBZ128rmkz */ }, { /* 10986 */ 211, /* VPMINUBZ128rr */ }, { /* 10987 */ 212, /* VPMINUBZ128rrk */ }, { /* 10988 */ 213, /* VPMINUBZ128rrkz */ }, { /* 10989 */ 214, /* VPMINUBZ256rm */ }, { /* 10990 */ 218, /* VPMINUBZ256rmk */ }, { /* 10991 */ 219, /* VPMINUBZ256rmkz */ }, { /* 10992 */ 220, /* VPMINUBZ256rr */ }, { /* 10993 */ 221, /* VPMINUBZ256rrk */ }, { /* 10994 */ 222, /* VPMINUBZ256rrkz */ }, { /* 10995 */ 223, /* VPMINUBZrm */ }, { /* 10996 */ 227, /* VPMINUBZrmk */ }, { /* 10997 */ 228, /* VPMINUBZrmkz */ }, { /* 10998 */ 229, /* VPMINUBZrr */ }, { /* 10999 */ 233, /* VPMINUBZrrk */ }, { /* 11000 */ 234, /* VPMINUBZrrkz */ }, { /* 11001 */ 235, /* VPMINUBrm */ }, { /* 11002 */ 236, /* VPMINUBrr */ }, { /* 11003 */ 204, /* VPMINUDYrm */ }, { /* 11004 */ 205, /* VPMINUDYrr */ }, { /* 11005 */ 206, /* VPMINUDZ128rm */ }, { /* 11006 */ 237, /* VPMINUDZ128rmb */ }, { /* 11007 */ 238, /* VPMINUDZ128rmbk */ }, { /* 11008 */ 239, /* VPMINUDZ128rmbkz */ }, { /* 11009 */ 203, /* VPMINUDZ128rmk */ }, { /* 11010 */ 210, /* VPMINUDZ128rmkz */ }, { /* 11011 */ 211, /* VPMINUDZ128rr */ }, { /* 11012 */ 212, /* VPMINUDZ128rrk */ }, { /* 11013 */ 213, /* VPMINUDZ128rrkz */ }, { /* 11014 */ 214, /* VPMINUDZ256rm */ }, { /* 11015 */ 240, /* VPMINUDZ256rmb */ }, { /* 11016 */ 241, /* VPMINUDZ256rmbk */ }, { /* 11017 */ 242, /* VPMINUDZ256rmbkz */ }, { /* 11018 */ 218, /* VPMINUDZ256rmk */ }, { /* 11019 */ 219, /* VPMINUDZ256rmkz */ }, { /* 11020 */ 220, /* VPMINUDZ256rr */ }, { /* 11021 */ 221, /* VPMINUDZ256rrk */ }, { /* 11022 */ 222, /* VPMINUDZ256rrkz */ }, { /* 11023 */ 223, /* VPMINUDZrm */ }, { /* 11024 */ 243, /* VPMINUDZrmb */ }, { /* 11025 */ 244, /* VPMINUDZrmbk */ }, { /* 11026 */ 245, /* VPMINUDZrmbkz */ }, { /* 11027 */ 227, /* VPMINUDZrmk */ }, { /* 11028 */ 228, /* VPMINUDZrmkz */ }, { /* 11029 */ 229, /* VPMINUDZrr */ }, { /* 11030 */ 233, /* VPMINUDZrrk */ }, { /* 11031 */ 234, /* VPMINUDZrrkz */ }, { /* 11032 */ 235, /* VPMINUDrm */ }, { /* 11033 */ 236, /* VPMINUDrr */ }, { /* 11034 */ 206, /* VPMINUQZ128rm */ }, { /* 11035 */ 207, /* VPMINUQZ128rmb */ }, { /* 11036 */ 208, /* VPMINUQZ128rmbk */ }, { /* 11037 */ 209, /* VPMINUQZ128rmbkz */ }, { /* 11038 */ 203, /* VPMINUQZ128rmk */ }, { /* 11039 */ 210, /* VPMINUQZ128rmkz */ }, { /* 11040 */ 211, /* VPMINUQZ128rr */ }, { /* 11041 */ 212, /* VPMINUQZ128rrk */ }, { /* 11042 */ 213, /* VPMINUQZ128rrkz */ }, { /* 11043 */ 214, /* VPMINUQZ256rm */ }, { /* 11044 */ 215, /* VPMINUQZ256rmb */ }, { /* 11045 */ 216, /* VPMINUQZ256rmbk */ }, { /* 11046 */ 217, /* VPMINUQZ256rmbkz */ }, { /* 11047 */ 218, /* VPMINUQZ256rmk */ }, { /* 11048 */ 219, /* VPMINUQZ256rmkz */ }, { /* 11049 */ 220, /* VPMINUQZ256rr */ }, { /* 11050 */ 221, /* VPMINUQZ256rrk */ }, { /* 11051 */ 222, /* VPMINUQZ256rrkz */ }, { /* 11052 */ 223, /* VPMINUQZrm */ }, { /* 11053 */ 224, /* VPMINUQZrmb */ }, { /* 11054 */ 225, /* VPMINUQZrmbk */ }, { /* 11055 */ 226, /* VPMINUQZrmbkz */ }, { /* 11056 */ 227, /* VPMINUQZrmk */ }, { /* 11057 */ 228, /* VPMINUQZrmkz */ }, { /* 11058 */ 229, /* VPMINUQZrr */ }, { /* 11059 */ 233, /* VPMINUQZrrk */ }, { /* 11060 */ 234, /* VPMINUQZrrkz */ }, { /* 11061 */ 204, /* VPMINUWYrm */ }, { /* 11062 */ 205, /* VPMINUWYrr */ }, { /* 11063 */ 206, /* VPMINUWZ128rm */ }, { /* 11064 */ 203, /* VPMINUWZ128rmk */ }, { /* 11065 */ 210, /* VPMINUWZ128rmkz */ }, { /* 11066 */ 211, /* VPMINUWZ128rr */ }, { /* 11067 */ 212, /* VPMINUWZ128rrk */ }, { /* 11068 */ 213, /* VPMINUWZ128rrkz */ }, { /* 11069 */ 214, /* VPMINUWZ256rm */ }, { /* 11070 */ 218, /* VPMINUWZ256rmk */ }, { /* 11071 */ 219, /* VPMINUWZ256rmkz */ }, { /* 11072 */ 220, /* VPMINUWZ256rr */ }, { /* 11073 */ 221, /* VPMINUWZ256rrk */ }, { /* 11074 */ 222, /* VPMINUWZ256rrkz */ }, { /* 11075 */ 223, /* VPMINUWZrm */ }, { /* 11076 */ 227, /* VPMINUWZrmk */ }, { /* 11077 */ 228, /* VPMINUWZrmkz */ }, { /* 11078 */ 229, /* VPMINUWZrr */ }, { /* 11079 */ 233, /* VPMINUWZrrk */ }, { /* 11080 */ 234, /* VPMINUWZrrkz */ }, { /* 11081 */ 235, /* VPMINUWrm */ }, { /* 11082 */ 236, /* VPMINUWrr */ }, { /* 11083 */ 801, /* VPMOVB2MZ128rr */ }, { /* 11084 */ 802, /* VPMOVB2MZ256rr */ }, { /* 11085 */ 803, /* VPMOVB2MZrr */ }, { /* 11086 */ 801, /* VPMOVD2MZ128rr */ }, { /* 11087 */ 802, /* VPMOVD2MZ256rr */ }, { /* 11088 */ 803, /* VPMOVD2MZrr */ }, { /* 11089 */ 394, /* VPMOVDBZ128mr */ }, { /* 11090 */ 395, /* VPMOVDBZ128mrk */ }, { /* 11091 */ 804, /* VPMOVDBZ128rr */ }, { /* 11092 */ 805, /* VPMOVDBZ128rrk */ }, { /* 11093 */ 806, /* VPMOVDBZ128rrkz */ }, { /* 11094 */ 384, /* VPMOVDBZ256mr */ }, { /* 11095 */ 385, /* VPMOVDBZ256mrk */ }, { /* 11096 */ 807, /* VPMOVDBZ256rr */ }, { /* 11097 */ 808, /* VPMOVDBZ256rrk */ }, { /* 11098 */ 809, /* VPMOVDBZ256rrkz */ }, { /* 11099 */ 810, /* VPMOVDBZmr */ }, { /* 11100 */ 811, /* VPMOVDBZmrk */ }, { /* 11101 */ 812, /* VPMOVDBZrr */ }, { /* 11102 */ 813, /* VPMOVDBZrrk */ }, { /* 11103 */ 814, /* VPMOVDBZrrkz */ }, { /* 11104 */ 379, /* VPMOVDWZ128mr */ }, { /* 11105 */ 380, /* VPMOVDWZ128mrk */ }, { /* 11106 */ 815, /* VPMOVDWZ128rr */ }, { /* 11107 */ 816, /* VPMOVDWZ128rrk */ }, { /* 11108 */ 817, /* VPMOVDWZ128rrkz */ }, { /* 11109 */ 818, /* VPMOVDWZ256mr */ }, { /* 11110 */ 819, /* VPMOVDWZ256mrk */ }, { /* 11111 */ 820, /* VPMOVDWZ256rr */ }, { /* 11112 */ 821, /* VPMOVDWZ256rrk */ }, { /* 11113 */ 822, /* VPMOVDWZ256rrkz */ }, { /* 11114 */ 823, /* VPMOVDWZmr */ }, { /* 11115 */ 824, /* VPMOVDWZmrk */ }, { /* 11116 */ 825, /* VPMOVDWZrr */ }, { /* 11117 */ 826, /* VPMOVDWZrrk */ }, { /* 11118 */ 827, /* VPMOVDWZrrkz */ }, { /* 11119 */ 703, /* VPMOVM2BZ128rr */ }, { /* 11120 */ 704, /* VPMOVM2BZ256rr */ }, { /* 11121 */ 705, /* VPMOVM2BZrr */ }, { /* 11122 */ 703, /* VPMOVM2DZ128rr */ }, { /* 11123 */ 704, /* VPMOVM2DZ256rr */ }, { /* 11124 */ 705, /* VPMOVM2DZrr */ }, { /* 11125 */ 703, /* VPMOVM2QZ128rr */ }, { /* 11126 */ 704, /* VPMOVM2QZ256rr */ }, { /* 11127 */ 705, /* VPMOVM2QZrr */ }, { /* 11128 */ 703, /* VPMOVM2WZ128rr */ }, { /* 11129 */ 704, /* VPMOVM2WZ256rr */ }, { /* 11130 */ 705, /* VPMOVM2WZrr */ }, { /* 11131 */ 679, /* VPMOVMSKBYrr */ }, { /* 11132 */ 88, /* VPMOVMSKBrr */ }, { /* 11133 */ 801, /* VPMOVQ2MZ128rr */ }, { /* 11134 */ 802, /* VPMOVQ2MZ256rr */ }, { /* 11135 */ 803, /* VPMOVQ2MZrr */ }, { /* 11136 */ 777, /* VPMOVQBZ128mr */ }, { /* 11137 */ 778, /* VPMOVQBZ128mrk */ }, { /* 11138 */ 828, /* VPMOVQBZ128rr */ }, { /* 11139 */ 829, /* VPMOVQBZ128rrk */ }, { /* 11140 */ 830, /* VPMOVQBZ128rrkz */ }, { /* 11141 */ 396, /* VPMOVQBZ256mr */ }, { /* 11142 */ 397, /* VPMOVQBZ256mrk */ }, { /* 11143 */ 831, /* VPMOVQBZ256rr */ }, { /* 11144 */ 832, /* VPMOVQBZ256rrk */ }, { /* 11145 */ 833, /* VPMOVQBZ256rrkz */ }, { /* 11146 */ 389, /* VPMOVQBZmr */ }, { /* 11147 */ 390, /* VPMOVQBZmrk */ }, { /* 11148 */ 834, /* VPMOVQBZrr */ }, { /* 11149 */ 835, /* VPMOVQBZrrk */ }, { /* 11150 */ 836, /* VPMOVQBZrrkz */ }, { /* 11151 */ 379, /* VPMOVQDZ128mr */ }, { /* 11152 */ 380, /* VPMOVQDZ128mrk */ }, { /* 11153 */ 815, /* VPMOVQDZ128rr */ }, { /* 11154 */ 816, /* VPMOVQDZ128rrk */ }, { /* 11155 */ 817, /* VPMOVQDZ128rrkz */ }, { /* 11156 */ 818, /* VPMOVQDZ256mr */ }, { /* 11157 */ 819, /* VPMOVQDZ256mrk */ }, { /* 11158 */ 820, /* VPMOVQDZ256rr */ }, { /* 11159 */ 821, /* VPMOVQDZ256rrk */ }, { /* 11160 */ 822, /* VPMOVQDZ256rrkz */ }, { /* 11161 */ 823, /* VPMOVQDZmr */ }, { /* 11162 */ 824, /* VPMOVQDZmrk */ }, { /* 11163 */ 825, /* VPMOVQDZrr */ }, { /* 11164 */ 826, /* VPMOVQDZrrk */ }, { /* 11165 */ 827, /* VPMOVQDZrrkz */ }, { /* 11166 */ 394, /* VPMOVQWZ128mr */ }, { /* 11167 */ 395, /* VPMOVQWZ128mrk */ }, { /* 11168 */ 804, /* VPMOVQWZ128rr */ }, { /* 11169 */ 805, /* VPMOVQWZ128rrk */ }, { /* 11170 */ 806, /* VPMOVQWZ128rrkz */ }, { /* 11171 */ 384, /* VPMOVQWZ256mr */ }, { /* 11172 */ 385, /* VPMOVQWZ256mrk */ }, { /* 11173 */ 807, /* VPMOVQWZ256rr */ }, { /* 11174 */ 808, /* VPMOVQWZ256rrk */ }, { /* 11175 */ 809, /* VPMOVQWZ256rrkz */ }, { /* 11176 */ 810, /* VPMOVQWZmr */ }, { /* 11177 */ 811, /* VPMOVQWZmrk */ }, { /* 11178 */ 812, /* VPMOVQWZrr */ }, { /* 11179 */ 813, /* VPMOVQWZrrk */ }, { /* 11180 */ 814, /* VPMOVQWZrrkz */ }, { /* 11181 */ 394, /* VPMOVSDBZ128mr */ }, { /* 11182 */ 395, /* VPMOVSDBZ128mrk */ }, { /* 11183 */ 804, /* VPMOVSDBZ128rr */ }, { /* 11184 */ 805, /* VPMOVSDBZ128rrk */ }, { /* 11185 */ 806, /* VPMOVSDBZ128rrkz */ }, { /* 11186 */ 384, /* VPMOVSDBZ256mr */ }, { /* 11187 */ 385, /* VPMOVSDBZ256mrk */ }, { /* 11188 */ 807, /* VPMOVSDBZ256rr */ }, { /* 11189 */ 808, /* VPMOVSDBZ256rrk */ }, { /* 11190 */ 809, /* VPMOVSDBZ256rrkz */ }, { /* 11191 */ 810, /* VPMOVSDBZmr */ }, { /* 11192 */ 811, /* VPMOVSDBZmrk */ }, { /* 11193 */ 812, /* VPMOVSDBZrr */ }, { /* 11194 */ 813, /* VPMOVSDBZrrk */ }, { /* 11195 */ 814, /* VPMOVSDBZrrkz */ }, { /* 11196 */ 379, /* VPMOVSDWZ128mr */ }, { /* 11197 */ 380, /* VPMOVSDWZ128mrk */ }, { /* 11198 */ 815, /* VPMOVSDWZ128rr */ }, { /* 11199 */ 816, /* VPMOVSDWZ128rrk */ }, { /* 11200 */ 817, /* VPMOVSDWZ128rrkz */ }, { /* 11201 */ 818, /* VPMOVSDWZ256mr */ }, { /* 11202 */ 819, /* VPMOVSDWZ256mrk */ }, { /* 11203 */ 820, /* VPMOVSDWZ256rr */ }, { /* 11204 */ 821, /* VPMOVSDWZ256rrk */ }, { /* 11205 */ 822, /* VPMOVSDWZ256rrkz */ }, { /* 11206 */ 823, /* VPMOVSDWZmr */ }, { /* 11207 */ 824, /* VPMOVSDWZmrk */ }, { /* 11208 */ 825, /* VPMOVSDWZrr */ }, { /* 11209 */ 826, /* VPMOVSDWZrrk */ }, { /* 11210 */ 827, /* VPMOVSDWZrrkz */ }, { /* 11211 */ 777, /* VPMOVSQBZ128mr */ }, { /* 11212 */ 778, /* VPMOVSQBZ128mrk */ }, { /* 11213 */ 828, /* VPMOVSQBZ128rr */ }, { /* 11214 */ 829, /* VPMOVSQBZ128rrk */ }, { /* 11215 */ 830, /* VPMOVSQBZ128rrkz */ }, { /* 11216 */ 396, /* VPMOVSQBZ256mr */ }, { /* 11217 */ 397, /* VPMOVSQBZ256mrk */ }, { /* 11218 */ 831, /* VPMOVSQBZ256rr */ }, { /* 11219 */ 832, /* VPMOVSQBZ256rrk */ }, { /* 11220 */ 833, /* VPMOVSQBZ256rrkz */ }, { /* 11221 */ 389, /* VPMOVSQBZmr */ }, { /* 11222 */ 390, /* VPMOVSQBZmrk */ }, { /* 11223 */ 834, /* VPMOVSQBZrr */ }, { /* 11224 */ 835, /* VPMOVSQBZrrk */ }, { /* 11225 */ 836, /* VPMOVSQBZrrkz */ }, { /* 11226 */ 379, /* VPMOVSQDZ128mr */ }, { /* 11227 */ 380, /* VPMOVSQDZ128mrk */ }, { /* 11228 */ 815, /* VPMOVSQDZ128rr */ }, { /* 11229 */ 816, /* VPMOVSQDZ128rrk */ }, { /* 11230 */ 817, /* VPMOVSQDZ128rrkz */ }, { /* 11231 */ 818, /* VPMOVSQDZ256mr */ }, { /* 11232 */ 819, /* VPMOVSQDZ256mrk */ }, { /* 11233 */ 820, /* VPMOVSQDZ256rr */ }, { /* 11234 */ 821, /* VPMOVSQDZ256rrk */ }, { /* 11235 */ 822, /* VPMOVSQDZ256rrkz */ }, { /* 11236 */ 823, /* VPMOVSQDZmr */ }, { /* 11237 */ 824, /* VPMOVSQDZmrk */ }, { /* 11238 */ 825, /* VPMOVSQDZrr */ }, { /* 11239 */ 826, /* VPMOVSQDZrrk */ }, { /* 11240 */ 827, /* VPMOVSQDZrrkz */ }, { /* 11241 */ 394, /* VPMOVSQWZ128mr */ }, { /* 11242 */ 395, /* VPMOVSQWZ128mrk */ }, { /* 11243 */ 804, /* VPMOVSQWZ128rr */ }, { /* 11244 */ 805, /* VPMOVSQWZ128rrk */ }, { /* 11245 */ 806, /* VPMOVSQWZ128rrkz */ }, { /* 11246 */ 384, /* VPMOVSQWZ256mr */ }, { /* 11247 */ 385, /* VPMOVSQWZ256mrk */ }, { /* 11248 */ 807, /* VPMOVSQWZ256rr */ }, { /* 11249 */ 808, /* VPMOVSQWZ256rrk */ }, { /* 11250 */ 809, /* VPMOVSQWZ256rrkz */ }, { /* 11251 */ 810, /* VPMOVSQWZmr */ }, { /* 11252 */ 811, /* VPMOVSQWZmrk */ }, { /* 11253 */ 812, /* VPMOVSQWZrr */ }, { /* 11254 */ 813, /* VPMOVSQWZrrk */ }, { /* 11255 */ 814, /* VPMOVSQWZrrkz */ }, { /* 11256 */ 379, /* VPMOVSWBZ128mr */ }, { /* 11257 */ 380, /* VPMOVSWBZ128mrk */ }, { /* 11258 */ 815, /* VPMOVSWBZ128rr */ }, { /* 11259 */ 816, /* VPMOVSWBZ128rrk */ }, { /* 11260 */ 817, /* VPMOVSWBZ128rrkz */ }, { /* 11261 */ 818, /* VPMOVSWBZ256mr */ }, { /* 11262 */ 819, /* VPMOVSWBZ256mrk */ }, { /* 11263 */ 820, /* VPMOVSWBZ256rr */ }, { /* 11264 */ 821, /* VPMOVSWBZ256rrk */ }, { /* 11265 */ 822, /* VPMOVSWBZ256rrkz */ }, { /* 11266 */ 823, /* VPMOVSWBZmr */ }, { /* 11267 */ 824, /* VPMOVSWBZmrk */ }, { /* 11268 */ 825, /* VPMOVSWBZrr */ }, { /* 11269 */ 826, /* VPMOVSWBZrrk */ }, { /* 11270 */ 827, /* VPMOVSWBZrrkz */ }, { /* 11271 */ 305, /* VPMOVSXBDYrm */ }, { /* 11272 */ 333, /* VPMOVSXBDYrr */ }, { /* 11273 */ 334, /* VPMOVSXBDZ128rm */ }, { /* 11274 */ 335, /* VPMOVSXBDZ128rmk */ }, { /* 11275 */ 336, /* VPMOVSXBDZ128rmkz */ }, { /* 11276 */ 378, /* VPMOVSXBDZ128rr */ }, { /* 11277 */ 837, /* VPMOVSXBDZ128rrk */ }, { /* 11278 */ 838, /* VPMOVSXBDZ128rrkz */ }, { /* 11279 */ 306, /* VPMOVSXBDZ256rm */ }, { /* 11280 */ 307, /* VPMOVSXBDZ256rmk */ }, { /* 11281 */ 308, /* VPMOVSXBDZ256rmkz */ }, { /* 11282 */ 839, /* VPMOVSXBDZ256rr */ }, { /* 11283 */ 840, /* VPMOVSXBDZ256rrk */ }, { /* 11284 */ 841, /* VPMOVSXBDZ256rrkz */ }, { /* 11285 */ 321, /* VPMOVSXBDZrm */ }, { /* 11286 */ 322, /* VPMOVSXBDZrmk */ }, { /* 11287 */ 323, /* VPMOVSXBDZrmkz */ }, { /* 11288 */ 842, /* VPMOVSXBDZrr */ }, { /* 11289 */ 843, /* VPMOVSXBDZrrk */ }, { /* 11290 */ 844, /* VPMOVSXBDZrrkz */ }, { /* 11291 */ 30, /* VPMOVSXBDrm */ }, { /* 11292 */ 31, /* VPMOVSXBDrr */ }, { /* 11293 */ 305, /* VPMOVSXBQYrm */ }, { /* 11294 */ 333, /* VPMOVSXBQYrr */ }, { /* 11295 */ 714, /* VPMOVSXBQZ128rm */ }, { /* 11296 */ 715, /* VPMOVSXBQZ128rmk */ }, { /* 11297 */ 716, /* VPMOVSXBQZ128rmkz */ }, { /* 11298 */ 845, /* VPMOVSXBQZ128rr */ }, { /* 11299 */ 846, /* VPMOVSXBQZ128rrk */ }, { /* 11300 */ 847, /* VPMOVSXBQZ128rrkz */ }, { /* 11301 */ 337, /* VPMOVSXBQZ256rm */ }, { /* 11302 */ 338, /* VPMOVSXBQZ256rmk */ }, { /* 11303 */ 339, /* VPMOVSXBQZ256rmkz */ }, { /* 11304 */ 848, /* VPMOVSXBQZ256rr */ }, { /* 11305 */ 849, /* VPMOVSXBQZ256rrk */ }, { /* 11306 */ 850, /* VPMOVSXBQZ256rrkz */ }, { /* 11307 */ 312, /* VPMOVSXBQZrm */ }, { /* 11308 */ 313, /* VPMOVSXBQZrmk */ }, { /* 11309 */ 314, /* VPMOVSXBQZrmkz */ }, { /* 11310 */ 851, /* VPMOVSXBQZrr */ }, { /* 11311 */ 852, /* VPMOVSXBQZrrk */ }, { /* 11312 */ 853, /* VPMOVSXBQZrrkz */ }, { /* 11313 */ 30, /* VPMOVSXBQrm */ }, { /* 11314 */ 31, /* VPMOVSXBQrr */ }, { /* 11315 */ 305, /* VPMOVSXBWYrm */ }, { /* 11316 */ 333, /* VPMOVSXBWYrr */ }, { /* 11317 */ 327, /* VPMOVSXBWZ128rm */ }, { /* 11318 */ 328, /* VPMOVSXBWZ128rmk */ }, { /* 11319 */ 329, /* VPMOVSXBWZ128rmkz */ }, { /* 11320 */ 377, /* VPMOVSXBWZ128rr */ }, { /* 11321 */ 400, /* VPMOVSXBWZ128rrk */ }, { /* 11322 */ 401, /* VPMOVSXBWZ128rrkz */ }, { /* 11323 */ 318, /* VPMOVSXBWZ256rm */ }, { /* 11324 */ 319, /* VPMOVSXBWZ256rmk */ }, { /* 11325 */ 320, /* VPMOVSXBWZ256rmkz */ }, { /* 11326 */ 402, /* VPMOVSXBWZ256rr */ }, { /* 11327 */ 403, /* VPMOVSXBWZ256rrk */ }, { /* 11328 */ 404, /* VPMOVSXBWZ256rrkz */ }, { /* 11329 */ 324, /* VPMOVSXBWZrm */ }, { /* 11330 */ 325, /* VPMOVSXBWZrmk */ }, { /* 11331 */ 326, /* VPMOVSXBWZrmkz */ }, { /* 11332 */ 405, /* VPMOVSXBWZrr */ }, { /* 11333 */ 406, /* VPMOVSXBWZrrk */ }, { /* 11334 */ 407, /* VPMOVSXBWZrrkz */ }, { /* 11335 */ 30, /* VPMOVSXBWrm */ }, { /* 11336 */ 31, /* VPMOVSXBWrr */ }, { /* 11337 */ 305, /* VPMOVSXDQYrm */ }, { /* 11338 */ 333, /* VPMOVSXDQYrr */ }, { /* 11339 */ 327, /* VPMOVSXDQZ128rm */ }, { /* 11340 */ 328, /* VPMOVSXDQZ128rmk */ }, { /* 11341 */ 329, /* VPMOVSXDQZ128rmkz */ }, { /* 11342 */ 377, /* VPMOVSXDQZ128rr */ }, { /* 11343 */ 400, /* VPMOVSXDQZ128rrk */ }, { /* 11344 */ 401, /* VPMOVSXDQZ128rrkz */ }, { /* 11345 */ 318, /* VPMOVSXDQZ256rm */ }, { /* 11346 */ 319, /* VPMOVSXDQZ256rmk */ }, { /* 11347 */ 320, /* VPMOVSXDQZ256rmkz */ }, { /* 11348 */ 402, /* VPMOVSXDQZ256rr */ }, { /* 11349 */ 403, /* VPMOVSXDQZ256rrk */ }, { /* 11350 */ 404, /* VPMOVSXDQZ256rrkz */ }, { /* 11351 */ 324, /* VPMOVSXDQZrm */ }, { /* 11352 */ 325, /* VPMOVSXDQZrmk */ }, { /* 11353 */ 326, /* VPMOVSXDQZrmkz */ }, { /* 11354 */ 405, /* VPMOVSXDQZrr */ }, { /* 11355 */ 406, /* VPMOVSXDQZrrk */ }, { /* 11356 */ 407, /* VPMOVSXDQZrrkz */ }, { /* 11357 */ 30, /* VPMOVSXDQrm */ }, { /* 11358 */ 31, /* VPMOVSXDQrr */ }, { /* 11359 */ 305, /* VPMOVSXWDYrm */ }, { /* 11360 */ 333, /* VPMOVSXWDYrr */ }, { /* 11361 */ 327, /* VPMOVSXWDZ128rm */ }, { /* 11362 */ 328, /* VPMOVSXWDZ128rmk */ }, { /* 11363 */ 329, /* VPMOVSXWDZ128rmkz */ }, { /* 11364 */ 377, /* VPMOVSXWDZ128rr */ }, { /* 11365 */ 400, /* VPMOVSXWDZ128rrk */ }, { /* 11366 */ 401, /* VPMOVSXWDZ128rrkz */ }, { /* 11367 */ 318, /* VPMOVSXWDZ256rm */ }, { /* 11368 */ 319, /* VPMOVSXWDZ256rmk */ }, { /* 11369 */ 320, /* VPMOVSXWDZ256rmkz */ }, { /* 11370 */ 402, /* VPMOVSXWDZ256rr */ }, { /* 11371 */ 403, /* VPMOVSXWDZ256rrk */ }, { /* 11372 */ 404, /* VPMOVSXWDZ256rrkz */ }, { /* 11373 */ 324, /* VPMOVSXWDZrm */ }, { /* 11374 */ 325, /* VPMOVSXWDZrmk */ }, { /* 11375 */ 326, /* VPMOVSXWDZrmkz */ }, { /* 11376 */ 405, /* VPMOVSXWDZrr */ }, { /* 11377 */ 406, /* VPMOVSXWDZrrk */ }, { /* 11378 */ 407, /* VPMOVSXWDZrrkz */ }, { /* 11379 */ 30, /* VPMOVSXWDrm */ }, { /* 11380 */ 31, /* VPMOVSXWDrr */ }, { /* 11381 */ 305, /* VPMOVSXWQYrm */ }, { /* 11382 */ 333, /* VPMOVSXWQYrr */ }, { /* 11383 */ 334, /* VPMOVSXWQZ128rm */ }, { /* 11384 */ 335, /* VPMOVSXWQZ128rmk */ }, { /* 11385 */ 336, /* VPMOVSXWQZ128rmkz */ }, { /* 11386 */ 378, /* VPMOVSXWQZ128rr */ }, { /* 11387 */ 837, /* VPMOVSXWQZ128rrk */ }, { /* 11388 */ 838, /* VPMOVSXWQZ128rrkz */ }, { /* 11389 */ 306, /* VPMOVSXWQZ256rm */ }, { /* 11390 */ 307, /* VPMOVSXWQZ256rmk */ }, { /* 11391 */ 308, /* VPMOVSXWQZ256rmkz */ }, { /* 11392 */ 839, /* VPMOVSXWQZ256rr */ }, { /* 11393 */ 840, /* VPMOVSXWQZ256rrk */ }, { /* 11394 */ 841, /* VPMOVSXWQZ256rrkz */ }, { /* 11395 */ 321, /* VPMOVSXWQZrm */ }, { /* 11396 */ 322, /* VPMOVSXWQZrmk */ }, { /* 11397 */ 323, /* VPMOVSXWQZrmkz */ }, { /* 11398 */ 842, /* VPMOVSXWQZrr */ }, { /* 11399 */ 843, /* VPMOVSXWQZrrk */ }, { /* 11400 */ 844, /* VPMOVSXWQZrrkz */ }, { /* 11401 */ 30, /* VPMOVSXWQrm */ }, { /* 11402 */ 31, /* VPMOVSXWQrr */ }, { /* 11403 */ 394, /* VPMOVUSDBZ128mr */ }, { /* 11404 */ 395, /* VPMOVUSDBZ128mrk */ }, { /* 11405 */ 804, /* VPMOVUSDBZ128rr */ }, { /* 11406 */ 805, /* VPMOVUSDBZ128rrk */ }, { /* 11407 */ 806, /* VPMOVUSDBZ128rrkz */ }, { /* 11408 */ 384, /* VPMOVUSDBZ256mr */ }, { /* 11409 */ 385, /* VPMOVUSDBZ256mrk */ }, { /* 11410 */ 807, /* VPMOVUSDBZ256rr */ }, { /* 11411 */ 808, /* VPMOVUSDBZ256rrk */ }, { /* 11412 */ 809, /* VPMOVUSDBZ256rrkz */ }, { /* 11413 */ 810, /* VPMOVUSDBZmr */ }, { /* 11414 */ 811, /* VPMOVUSDBZmrk */ }, { /* 11415 */ 812, /* VPMOVUSDBZrr */ }, { /* 11416 */ 813, /* VPMOVUSDBZrrk */ }, { /* 11417 */ 814, /* VPMOVUSDBZrrkz */ }, { /* 11418 */ 379, /* VPMOVUSDWZ128mr */ }, { /* 11419 */ 380, /* VPMOVUSDWZ128mrk */ }, { /* 11420 */ 815, /* VPMOVUSDWZ128rr */ }, { /* 11421 */ 816, /* VPMOVUSDWZ128rrk */ }, { /* 11422 */ 817, /* VPMOVUSDWZ128rrkz */ }, { /* 11423 */ 818, /* VPMOVUSDWZ256mr */ }, { /* 11424 */ 819, /* VPMOVUSDWZ256mrk */ }, { /* 11425 */ 820, /* VPMOVUSDWZ256rr */ }, { /* 11426 */ 821, /* VPMOVUSDWZ256rrk */ }, { /* 11427 */ 822, /* VPMOVUSDWZ256rrkz */ }, { /* 11428 */ 823, /* VPMOVUSDWZmr */ }, { /* 11429 */ 824, /* VPMOVUSDWZmrk */ }, { /* 11430 */ 825, /* VPMOVUSDWZrr */ }, { /* 11431 */ 826, /* VPMOVUSDWZrrk */ }, { /* 11432 */ 827, /* VPMOVUSDWZrrkz */ }, { /* 11433 */ 777, /* VPMOVUSQBZ128mr */ }, { /* 11434 */ 778, /* VPMOVUSQBZ128mrk */ }, { /* 11435 */ 828, /* VPMOVUSQBZ128rr */ }, { /* 11436 */ 829, /* VPMOVUSQBZ128rrk */ }, { /* 11437 */ 830, /* VPMOVUSQBZ128rrkz */ }, { /* 11438 */ 396, /* VPMOVUSQBZ256mr */ }, { /* 11439 */ 397, /* VPMOVUSQBZ256mrk */ }, { /* 11440 */ 831, /* VPMOVUSQBZ256rr */ }, { /* 11441 */ 832, /* VPMOVUSQBZ256rrk */ }, { /* 11442 */ 833, /* VPMOVUSQBZ256rrkz */ }, { /* 11443 */ 389, /* VPMOVUSQBZmr */ }, { /* 11444 */ 390, /* VPMOVUSQBZmrk */ }, { /* 11445 */ 834, /* VPMOVUSQBZrr */ }, { /* 11446 */ 835, /* VPMOVUSQBZrrk */ }, { /* 11447 */ 836, /* VPMOVUSQBZrrkz */ }, { /* 11448 */ 379, /* VPMOVUSQDZ128mr */ }, { /* 11449 */ 380, /* VPMOVUSQDZ128mrk */ }, { /* 11450 */ 815, /* VPMOVUSQDZ128rr */ }, { /* 11451 */ 816, /* VPMOVUSQDZ128rrk */ }, { /* 11452 */ 817, /* VPMOVUSQDZ128rrkz */ }, { /* 11453 */ 818, /* VPMOVUSQDZ256mr */ }, { /* 11454 */ 819, /* VPMOVUSQDZ256mrk */ }, { /* 11455 */ 820, /* VPMOVUSQDZ256rr */ }, { /* 11456 */ 821, /* VPMOVUSQDZ256rrk */ }, { /* 11457 */ 822, /* VPMOVUSQDZ256rrkz */ }, { /* 11458 */ 823, /* VPMOVUSQDZmr */ }, { /* 11459 */ 824, /* VPMOVUSQDZmrk */ }, { /* 11460 */ 825, /* VPMOVUSQDZrr */ }, { /* 11461 */ 826, /* VPMOVUSQDZrrk */ }, { /* 11462 */ 827, /* VPMOVUSQDZrrkz */ }, { /* 11463 */ 394, /* VPMOVUSQWZ128mr */ }, { /* 11464 */ 395, /* VPMOVUSQWZ128mrk */ }, { /* 11465 */ 804, /* VPMOVUSQWZ128rr */ }, { /* 11466 */ 805, /* VPMOVUSQWZ128rrk */ }, { /* 11467 */ 806, /* VPMOVUSQWZ128rrkz */ }, { /* 11468 */ 384, /* VPMOVUSQWZ256mr */ }, { /* 11469 */ 385, /* VPMOVUSQWZ256mrk */ }, { /* 11470 */ 807, /* VPMOVUSQWZ256rr */ }, { /* 11471 */ 808, /* VPMOVUSQWZ256rrk */ }, { /* 11472 */ 809, /* VPMOVUSQWZ256rrkz */ }, { /* 11473 */ 810, /* VPMOVUSQWZmr */ }, { /* 11474 */ 811, /* VPMOVUSQWZmrk */ }, { /* 11475 */ 812, /* VPMOVUSQWZrr */ }, { /* 11476 */ 813, /* VPMOVUSQWZrrk */ }, { /* 11477 */ 814, /* VPMOVUSQWZrrkz */ }, { /* 11478 */ 379, /* VPMOVUSWBZ128mr */ }, { /* 11479 */ 380, /* VPMOVUSWBZ128mrk */ }, { /* 11480 */ 815, /* VPMOVUSWBZ128rr */ }, { /* 11481 */ 816, /* VPMOVUSWBZ128rrk */ }, { /* 11482 */ 817, /* VPMOVUSWBZ128rrkz */ }, { /* 11483 */ 818, /* VPMOVUSWBZ256mr */ }, { /* 11484 */ 819, /* VPMOVUSWBZ256mrk */ }, { /* 11485 */ 820, /* VPMOVUSWBZ256rr */ }, { /* 11486 */ 821, /* VPMOVUSWBZ256rrk */ }, { /* 11487 */ 822, /* VPMOVUSWBZ256rrkz */ }, { /* 11488 */ 823, /* VPMOVUSWBZmr */ }, { /* 11489 */ 824, /* VPMOVUSWBZmrk */ }, { /* 11490 */ 825, /* VPMOVUSWBZrr */ }, { /* 11491 */ 826, /* VPMOVUSWBZrrk */ }, { /* 11492 */ 827, /* VPMOVUSWBZrrkz */ }, { /* 11493 */ 801, /* VPMOVW2MZ128rr */ }, { /* 11494 */ 802, /* VPMOVW2MZ256rr */ }, { /* 11495 */ 803, /* VPMOVW2MZrr */ }, { /* 11496 */ 379, /* VPMOVWBZ128mr */ }, { /* 11497 */ 380, /* VPMOVWBZ128mrk */ }, { /* 11498 */ 815, /* VPMOVWBZ128rr */ }, { /* 11499 */ 816, /* VPMOVWBZ128rrk */ }, { /* 11500 */ 817, /* VPMOVWBZ128rrkz */ }, { /* 11501 */ 818, /* VPMOVWBZ256mr */ }, { /* 11502 */ 819, /* VPMOVWBZ256mrk */ }, { /* 11503 */ 820, /* VPMOVWBZ256rr */ }, { /* 11504 */ 821, /* VPMOVWBZ256rrk */ }, { /* 11505 */ 822, /* VPMOVWBZ256rrkz */ }, { /* 11506 */ 823, /* VPMOVWBZmr */ }, { /* 11507 */ 824, /* VPMOVWBZmrk */ }, { /* 11508 */ 825, /* VPMOVWBZrr */ }, { /* 11509 */ 826, /* VPMOVWBZrrk */ }, { /* 11510 */ 827, /* VPMOVWBZrrkz */ }, { /* 11511 */ 305, /* VPMOVZXBDYrm */ }, { /* 11512 */ 333, /* VPMOVZXBDYrr */ }, { /* 11513 */ 334, /* VPMOVZXBDZ128rm */ }, { /* 11514 */ 335, /* VPMOVZXBDZ128rmk */ }, { /* 11515 */ 336, /* VPMOVZXBDZ128rmkz */ }, { /* 11516 */ 378, /* VPMOVZXBDZ128rr */ }, { /* 11517 */ 837, /* VPMOVZXBDZ128rrk */ }, { /* 11518 */ 838, /* VPMOVZXBDZ128rrkz */ }, { /* 11519 */ 306, /* VPMOVZXBDZ256rm */ }, { /* 11520 */ 307, /* VPMOVZXBDZ256rmk */ }, { /* 11521 */ 308, /* VPMOVZXBDZ256rmkz */ }, { /* 11522 */ 839, /* VPMOVZXBDZ256rr */ }, { /* 11523 */ 840, /* VPMOVZXBDZ256rrk */ }, { /* 11524 */ 841, /* VPMOVZXBDZ256rrkz */ }, { /* 11525 */ 321, /* VPMOVZXBDZrm */ }, { /* 11526 */ 322, /* VPMOVZXBDZrmk */ }, { /* 11527 */ 323, /* VPMOVZXBDZrmkz */ }, { /* 11528 */ 842, /* VPMOVZXBDZrr */ }, { /* 11529 */ 843, /* VPMOVZXBDZrrk */ }, { /* 11530 */ 844, /* VPMOVZXBDZrrkz */ }, { /* 11531 */ 30, /* VPMOVZXBDrm */ }, { /* 11532 */ 31, /* VPMOVZXBDrr */ }, { /* 11533 */ 305, /* VPMOVZXBQYrm */ }, { /* 11534 */ 333, /* VPMOVZXBQYrr */ }, { /* 11535 */ 714, /* VPMOVZXBQZ128rm */ }, { /* 11536 */ 715, /* VPMOVZXBQZ128rmk */ }, { /* 11537 */ 716, /* VPMOVZXBQZ128rmkz */ }, { /* 11538 */ 845, /* VPMOVZXBQZ128rr */ }, { /* 11539 */ 846, /* VPMOVZXBQZ128rrk */ }, { /* 11540 */ 847, /* VPMOVZXBQZ128rrkz */ }, { /* 11541 */ 337, /* VPMOVZXBQZ256rm */ }, { /* 11542 */ 338, /* VPMOVZXBQZ256rmk */ }, { /* 11543 */ 339, /* VPMOVZXBQZ256rmkz */ }, { /* 11544 */ 848, /* VPMOVZXBQZ256rr */ }, { /* 11545 */ 849, /* VPMOVZXBQZ256rrk */ }, { /* 11546 */ 850, /* VPMOVZXBQZ256rrkz */ }, { /* 11547 */ 312, /* VPMOVZXBQZrm */ }, { /* 11548 */ 313, /* VPMOVZXBQZrmk */ }, { /* 11549 */ 314, /* VPMOVZXBQZrmkz */ }, { /* 11550 */ 851, /* VPMOVZXBQZrr */ }, { /* 11551 */ 852, /* VPMOVZXBQZrrk */ }, { /* 11552 */ 853, /* VPMOVZXBQZrrkz */ }, { /* 11553 */ 30, /* VPMOVZXBQrm */ }, { /* 11554 */ 31, /* VPMOVZXBQrr */ }, { /* 11555 */ 305, /* VPMOVZXBWYrm */ }, { /* 11556 */ 333, /* VPMOVZXBWYrr */ }, { /* 11557 */ 327, /* VPMOVZXBWZ128rm */ }, { /* 11558 */ 328, /* VPMOVZXBWZ128rmk */ }, { /* 11559 */ 329, /* VPMOVZXBWZ128rmkz */ }, { /* 11560 */ 377, /* VPMOVZXBWZ128rr */ }, { /* 11561 */ 400, /* VPMOVZXBWZ128rrk */ }, { /* 11562 */ 401, /* VPMOVZXBWZ128rrkz */ }, { /* 11563 */ 318, /* VPMOVZXBWZ256rm */ }, { /* 11564 */ 319, /* VPMOVZXBWZ256rmk */ }, { /* 11565 */ 320, /* VPMOVZXBWZ256rmkz */ }, { /* 11566 */ 402, /* VPMOVZXBWZ256rr */ }, { /* 11567 */ 403, /* VPMOVZXBWZ256rrk */ }, { /* 11568 */ 404, /* VPMOVZXBWZ256rrkz */ }, { /* 11569 */ 324, /* VPMOVZXBWZrm */ }, { /* 11570 */ 325, /* VPMOVZXBWZrmk */ }, { /* 11571 */ 326, /* VPMOVZXBWZrmkz */ }, { /* 11572 */ 405, /* VPMOVZXBWZrr */ }, { /* 11573 */ 406, /* VPMOVZXBWZrrk */ }, { /* 11574 */ 407, /* VPMOVZXBWZrrkz */ }, { /* 11575 */ 30, /* VPMOVZXBWrm */ }, { /* 11576 */ 31, /* VPMOVZXBWrr */ }, { /* 11577 */ 305, /* VPMOVZXDQYrm */ }, { /* 11578 */ 333, /* VPMOVZXDQYrr */ }, { /* 11579 */ 327, /* VPMOVZXDQZ128rm */ }, { /* 11580 */ 328, /* VPMOVZXDQZ128rmk */ }, { /* 11581 */ 329, /* VPMOVZXDQZ128rmkz */ }, { /* 11582 */ 377, /* VPMOVZXDQZ128rr */ }, { /* 11583 */ 400, /* VPMOVZXDQZ128rrk */ }, { /* 11584 */ 401, /* VPMOVZXDQZ128rrkz */ }, { /* 11585 */ 318, /* VPMOVZXDQZ256rm */ }, { /* 11586 */ 319, /* VPMOVZXDQZ256rmk */ }, { /* 11587 */ 320, /* VPMOVZXDQZ256rmkz */ }, { /* 11588 */ 402, /* VPMOVZXDQZ256rr */ }, { /* 11589 */ 403, /* VPMOVZXDQZ256rrk */ }, { /* 11590 */ 404, /* VPMOVZXDQZ256rrkz */ }, { /* 11591 */ 324, /* VPMOVZXDQZrm */ }, { /* 11592 */ 325, /* VPMOVZXDQZrmk */ }, { /* 11593 */ 326, /* VPMOVZXDQZrmkz */ }, { /* 11594 */ 405, /* VPMOVZXDQZrr */ }, { /* 11595 */ 406, /* VPMOVZXDQZrrk */ }, { /* 11596 */ 407, /* VPMOVZXDQZrrkz */ }, { /* 11597 */ 30, /* VPMOVZXDQrm */ }, { /* 11598 */ 31, /* VPMOVZXDQrr */ }, { /* 11599 */ 305, /* VPMOVZXWDYrm */ }, { /* 11600 */ 333, /* VPMOVZXWDYrr */ }, { /* 11601 */ 327, /* VPMOVZXWDZ128rm */ }, { /* 11602 */ 328, /* VPMOVZXWDZ128rmk */ }, { /* 11603 */ 329, /* VPMOVZXWDZ128rmkz */ }, { /* 11604 */ 377, /* VPMOVZXWDZ128rr */ }, { /* 11605 */ 400, /* VPMOVZXWDZ128rrk */ }, { /* 11606 */ 401, /* VPMOVZXWDZ128rrkz */ }, { /* 11607 */ 318, /* VPMOVZXWDZ256rm */ }, { /* 11608 */ 319, /* VPMOVZXWDZ256rmk */ }, { /* 11609 */ 320, /* VPMOVZXWDZ256rmkz */ }, { /* 11610 */ 402, /* VPMOVZXWDZ256rr */ }, { /* 11611 */ 403, /* VPMOVZXWDZ256rrk */ }, { /* 11612 */ 404, /* VPMOVZXWDZ256rrkz */ }, { /* 11613 */ 324, /* VPMOVZXWDZrm */ }, { /* 11614 */ 325, /* VPMOVZXWDZrmk */ }, { /* 11615 */ 326, /* VPMOVZXWDZrmkz */ }, { /* 11616 */ 405, /* VPMOVZXWDZrr */ }, { /* 11617 */ 406, /* VPMOVZXWDZrrk */ }, { /* 11618 */ 407, /* VPMOVZXWDZrrkz */ }, { /* 11619 */ 30, /* VPMOVZXWDrm */ }, { /* 11620 */ 31, /* VPMOVZXWDrr */ }, { /* 11621 */ 305, /* VPMOVZXWQYrm */ }, { /* 11622 */ 333, /* VPMOVZXWQYrr */ }, { /* 11623 */ 334, /* VPMOVZXWQZ128rm */ }, { /* 11624 */ 335, /* VPMOVZXWQZ128rmk */ }, { /* 11625 */ 336, /* VPMOVZXWQZ128rmkz */ }, { /* 11626 */ 378, /* VPMOVZXWQZ128rr */ }, { /* 11627 */ 837, /* VPMOVZXWQZ128rrk */ }, { /* 11628 */ 838, /* VPMOVZXWQZ128rrkz */ }, { /* 11629 */ 306, /* VPMOVZXWQZ256rm */ }, { /* 11630 */ 307, /* VPMOVZXWQZ256rmk */ }, { /* 11631 */ 308, /* VPMOVZXWQZ256rmkz */ }, { /* 11632 */ 839, /* VPMOVZXWQZ256rr */ }, { /* 11633 */ 840, /* VPMOVZXWQZ256rrk */ }, { /* 11634 */ 841, /* VPMOVZXWQZ256rrkz */ }, { /* 11635 */ 321, /* VPMOVZXWQZrm */ }, { /* 11636 */ 322, /* VPMOVZXWQZrmk */ }, { /* 11637 */ 323, /* VPMOVZXWQZrmkz */ }, { /* 11638 */ 842, /* VPMOVZXWQZrr */ }, { /* 11639 */ 843, /* VPMOVZXWQZrrk */ }, { /* 11640 */ 844, /* VPMOVZXWQZrrkz */ }, { /* 11641 */ 30, /* VPMOVZXWQrm */ }, { /* 11642 */ 31, /* VPMOVZXWQrr */ }, { /* 11643 */ 204, /* VPMULDQYrm */ }, { /* 11644 */ 205, /* VPMULDQYrr */ }, { /* 11645 */ 206, /* VPMULDQZ128rm */ }, { /* 11646 */ 207, /* VPMULDQZ128rmb */ }, { /* 11647 */ 208, /* VPMULDQZ128rmbk */ }, { /* 11648 */ 209, /* VPMULDQZ128rmbkz */ }, { /* 11649 */ 203, /* VPMULDQZ128rmk */ }, { /* 11650 */ 210, /* VPMULDQZ128rmkz */ }, { /* 11651 */ 211, /* VPMULDQZ128rr */ }, { /* 11652 */ 212, /* VPMULDQZ128rrk */ }, { /* 11653 */ 213, /* VPMULDQZ128rrkz */ }, { /* 11654 */ 214, /* VPMULDQZ256rm */ }, { /* 11655 */ 215, /* VPMULDQZ256rmb */ }, { /* 11656 */ 216, /* VPMULDQZ256rmbk */ }, { /* 11657 */ 217, /* VPMULDQZ256rmbkz */ }, { /* 11658 */ 218, /* VPMULDQZ256rmk */ }, { /* 11659 */ 219, /* VPMULDQZ256rmkz */ }, { /* 11660 */ 220, /* VPMULDQZ256rr */ }, { /* 11661 */ 221, /* VPMULDQZ256rrk */ }, { /* 11662 */ 222, /* VPMULDQZ256rrkz */ }, { /* 11663 */ 223, /* VPMULDQZrm */ }, { /* 11664 */ 224, /* VPMULDQZrmb */ }, { /* 11665 */ 225, /* VPMULDQZrmbk */ }, { /* 11666 */ 226, /* VPMULDQZrmbkz */ }, { /* 11667 */ 227, /* VPMULDQZrmk */ }, { /* 11668 */ 228, /* VPMULDQZrmkz */ }, { /* 11669 */ 229, /* VPMULDQZrr */ }, { /* 11670 */ 233, /* VPMULDQZrrk */ }, { /* 11671 */ 234, /* VPMULDQZrrkz */ }, { /* 11672 */ 235, /* VPMULDQrm */ }, { /* 11673 */ 236, /* VPMULDQrr */ }, { /* 11674 */ 204, /* VPMULHRSWYrm */ }, { /* 11675 */ 205, /* VPMULHRSWYrr */ }, { /* 11676 */ 206, /* VPMULHRSWZ128rm */ }, { /* 11677 */ 203, /* VPMULHRSWZ128rmk */ }, { /* 11678 */ 210, /* VPMULHRSWZ128rmkz */ }, { /* 11679 */ 211, /* VPMULHRSWZ128rr */ }, { /* 11680 */ 212, /* VPMULHRSWZ128rrk */ }, { /* 11681 */ 213, /* VPMULHRSWZ128rrkz */ }, { /* 11682 */ 214, /* VPMULHRSWZ256rm */ }, { /* 11683 */ 218, /* VPMULHRSWZ256rmk */ }, { /* 11684 */ 219, /* VPMULHRSWZ256rmkz */ }, { /* 11685 */ 220, /* VPMULHRSWZ256rr */ }, { /* 11686 */ 221, /* VPMULHRSWZ256rrk */ }, { /* 11687 */ 222, /* VPMULHRSWZ256rrkz */ }, { /* 11688 */ 223, /* VPMULHRSWZrm */ }, { /* 11689 */ 227, /* VPMULHRSWZrmk */ }, { /* 11690 */ 228, /* VPMULHRSWZrmkz */ }, { /* 11691 */ 229, /* VPMULHRSWZrr */ }, { /* 11692 */ 233, /* VPMULHRSWZrrk */ }, { /* 11693 */ 234, /* VPMULHRSWZrrkz */ }, { /* 11694 */ 235, /* VPMULHRSWrm */ }, { /* 11695 */ 236, /* VPMULHRSWrr */ }, { /* 11696 */ 204, /* VPMULHUWYrm */ }, { /* 11697 */ 205, /* VPMULHUWYrr */ }, { /* 11698 */ 206, /* VPMULHUWZ128rm */ }, { /* 11699 */ 203, /* VPMULHUWZ128rmk */ }, { /* 11700 */ 210, /* VPMULHUWZ128rmkz */ }, { /* 11701 */ 211, /* VPMULHUWZ128rr */ }, { /* 11702 */ 212, /* VPMULHUWZ128rrk */ }, { /* 11703 */ 213, /* VPMULHUWZ128rrkz */ }, { /* 11704 */ 214, /* VPMULHUWZ256rm */ }, { /* 11705 */ 218, /* VPMULHUWZ256rmk */ }, { /* 11706 */ 219, /* VPMULHUWZ256rmkz */ }, { /* 11707 */ 220, /* VPMULHUWZ256rr */ }, { /* 11708 */ 221, /* VPMULHUWZ256rrk */ }, { /* 11709 */ 222, /* VPMULHUWZ256rrkz */ }, { /* 11710 */ 223, /* VPMULHUWZrm */ }, { /* 11711 */ 227, /* VPMULHUWZrmk */ }, { /* 11712 */ 228, /* VPMULHUWZrmkz */ }, { /* 11713 */ 229, /* VPMULHUWZrr */ }, { /* 11714 */ 233, /* VPMULHUWZrrk */ }, { /* 11715 */ 234, /* VPMULHUWZrrkz */ }, { /* 11716 */ 235, /* VPMULHUWrm */ }, { /* 11717 */ 236, /* VPMULHUWrr */ }, { /* 11718 */ 204, /* VPMULHWYrm */ }, { /* 11719 */ 205, /* VPMULHWYrr */ }, { /* 11720 */ 206, /* VPMULHWZ128rm */ }, { /* 11721 */ 203, /* VPMULHWZ128rmk */ }, { /* 11722 */ 210, /* VPMULHWZ128rmkz */ }, { /* 11723 */ 211, /* VPMULHWZ128rr */ }, { /* 11724 */ 212, /* VPMULHWZ128rrk */ }, { /* 11725 */ 213, /* VPMULHWZ128rrkz */ }, { /* 11726 */ 214, /* VPMULHWZ256rm */ }, { /* 11727 */ 218, /* VPMULHWZ256rmk */ }, { /* 11728 */ 219, /* VPMULHWZ256rmkz */ }, { /* 11729 */ 220, /* VPMULHWZ256rr */ }, { /* 11730 */ 221, /* VPMULHWZ256rrk */ }, { /* 11731 */ 222, /* VPMULHWZ256rrkz */ }, { /* 11732 */ 223, /* VPMULHWZrm */ }, { /* 11733 */ 227, /* VPMULHWZrmk */ }, { /* 11734 */ 228, /* VPMULHWZrmkz */ }, { /* 11735 */ 229, /* VPMULHWZrr */ }, { /* 11736 */ 233, /* VPMULHWZrrk */ }, { /* 11737 */ 234, /* VPMULHWZrrkz */ }, { /* 11738 */ 235, /* VPMULHWrm */ }, { /* 11739 */ 236, /* VPMULHWrr */ }, { /* 11740 */ 204, /* VPMULLDYrm */ }, { /* 11741 */ 205, /* VPMULLDYrr */ }, { /* 11742 */ 206, /* VPMULLDZ128rm */ }, { /* 11743 */ 237, /* VPMULLDZ128rmb */ }, { /* 11744 */ 238, /* VPMULLDZ128rmbk */ }, { /* 11745 */ 239, /* VPMULLDZ128rmbkz */ }, { /* 11746 */ 203, /* VPMULLDZ128rmk */ }, { /* 11747 */ 210, /* VPMULLDZ128rmkz */ }, { /* 11748 */ 211, /* VPMULLDZ128rr */ }, { /* 11749 */ 212, /* VPMULLDZ128rrk */ }, { /* 11750 */ 213, /* VPMULLDZ128rrkz */ }, { /* 11751 */ 214, /* VPMULLDZ256rm */ }, { /* 11752 */ 240, /* VPMULLDZ256rmb */ }, { /* 11753 */ 241, /* VPMULLDZ256rmbk */ }, { /* 11754 */ 242, /* VPMULLDZ256rmbkz */ }, { /* 11755 */ 218, /* VPMULLDZ256rmk */ }, { /* 11756 */ 219, /* VPMULLDZ256rmkz */ }, { /* 11757 */ 220, /* VPMULLDZ256rr */ }, { /* 11758 */ 221, /* VPMULLDZ256rrk */ }, { /* 11759 */ 222, /* VPMULLDZ256rrkz */ }, { /* 11760 */ 223, /* VPMULLDZrm */ }, { /* 11761 */ 243, /* VPMULLDZrmb */ }, { /* 11762 */ 244, /* VPMULLDZrmbk */ }, { /* 11763 */ 245, /* VPMULLDZrmbkz */ }, { /* 11764 */ 227, /* VPMULLDZrmk */ }, { /* 11765 */ 228, /* VPMULLDZrmkz */ }, { /* 11766 */ 229, /* VPMULLDZrr */ }, { /* 11767 */ 233, /* VPMULLDZrrk */ }, { /* 11768 */ 234, /* VPMULLDZrrkz */ }, { /* 11769 */ 235, /* VPMULLDrm */ }, { /* 11770 */ 236, /* VPMULLDrr */ }, { /* 11771 */ 206, /* VPMULLQZ128rm */ }, { /* 11772 */ 207, /* VPMULLQZ128rmb */ }, { /* 11773 */ 208, /* VPMULLQZ128rmbk */ }, { /* 11774 */ 209, /* VPMULLQZ128rmbkz */ }, { /* 11775 */ 203, /* VPMULLQZ128rmk */ }, { /* 11776 */ 210, /* VPMULLQZ128rmkz */ }, { /* 11777 */ 211, /* VPMULLQZ128rr */ }, { /* 11778 */ 212, /* VPMULLQZ128rrk */ }, { /* 11779 */ 213, /* VPMULLQZ128rrkz */ }, { /* 11780 */ 214, /* VPMULLQZ256rm */ }, { /* 11781 */ 215, /* VPMULLQZ256rmb */ }, { /* 11782 */ 216, /* VPMULLQZ256rmbk */ }, { /* 11783 */ 217, /* VPMULLQZ256rmbkz */ }, { /* 11784 */ 218, /* VPMULLQZ256rmk */ }, { /* 11785 */ 219, /* VPMULLQZ256rmkz */ }, { /* 11786 */ 220, /* VPMULLQZ256rr */ }, { /* 11787 */ 221, /* VPMULLQZ256rrk */ }, { /* 11788 */ 222, /* VPMULLQZ256rrkz */ }, { /* 11789 */ 223, /* VPMULLQZrm */ }, { /* 11790 */ 224, /* VPMULLQZrmb */ }, { /* 11791 */ 225, /* VPMULLQZrmbk */ }, { /* 11792 */ 226, /* VPMULLQZrmbkz */ }, { /* 11793 */ 227, /* VPMULLQZrmk */ }, { /* 11794 */ 228, /* VPMULLQZrmkz */ }, { /* 11795 */ 229, /* VPMULLQZrr */ }, { /* 11796 */ 233, /* VPMULLQZrrk */ }, { /* 11797 */ 234, /* VPMULLQZrrkz */ }, { /* 11798 */ 204, /* VPMULLWYrm */ }, { /* 11799 */ 205, /* VPMULLWYrr */ }, { /* 11800 */ 206, /* VPMULLWZ128rm */ }, { /* 11801 */ 203, /* VPMULLWZ128rmk */ }, { /* 11802 */ 210, /* VPMULLWZ128rmkz */ }, { /* 11803 */ 211, /* VPMULLWZ128rr */ }, { /* 11804 */ 212, /* VPMULLWZ128rrk */ }, { /* 11805 */ 213, /* VPMULLWZ128rrkz */ }, { /* 11806 */ 214, /* VPMULLWZ256rm */ }, { /* 11807 */ 218, /* VPMULLWZ256rmk */ }, { /* 11808 */ 219, /* VPMULLWZ256rmkz */ }, { /* 11809 */ 220, /* VPMULLWZ256rr */ }, { /* 11810 */ 221, /* VPMULLWZ256rrk */ }, { /* 11811 */ 222, /* VPMULLWZ256rrkz */ }, { /* 11812 */ 223, /* VPMULLWZrm */ }, { /* 11813 */ 227, /* VPMULLWZrmk */ }, { /* 11814 */ 228, /* VPMULLWZrmkz */ }, { /* 11815 */ 229, /* VPMULLWZrr */ }, { /* 11816 */ 233, /* VPMULLWZrrk */ }, { /* 11817 */ 234, /* VPMULLWZrrkz */ }, { /* 11818 */ 235, /* VPMULLWrm */ }, { /* 11819 */ 236, /* VPMULLWrr */ }, { /* 11820 */ 206, /* VPMULTISHIFTQBZ128rm */ }, { /* 11821 */ 207, /* VPMULTISHIFTQBZ128rmb */ }, { /* 11822 */ 208, /* VPMULTISHIFTQBZ128rmbk */ }, { /* 11823 */ 209, /* VPMULTISHIFTQBZ128rmbkz */ }, { /* 11824 */ 203, /* VPMULTISHIFTQBZ128rmk */ }, { /* 11825 */ 210, /* VPMULTISHIFTQBZ128rmkz */ }, { /* 11826 */ 211, /* VPMULTISHIFTQBZ128rr */ }, { /* 11827 */ 212, /* VPMULTISHIFTQBZ128rrk */ }, { /* 11828 */ 213, /* VPMULTISHIFTQBZ128rrkz */ }, { /* 11829 */ 214, /* VPMULTISHIFTQBZ256rm */ }, { /* 11830 */ 215, /* VPMULTISHIFTQBZ256rmb */ }, { /* 11831 */ 216, /* VPMULTISHIFTQBZ256rmbk */ }, { /* 11832 */ 217, /* VPMULTISHIFTQBZ256rmbkz */ }, { /* 11833 */ 218, /* VPMULTISHIFTQBZ256rmk */ }, { /* 11834 */ 219, /* VPMULTISHIFTQBZ256rmkz */ }, { /* 11835 */ 220, /* VPMULTISHIFTQBZ256rr */ }, { /* 11836 */ 221, /* VPMULTISHIFTQBZ256rrk */ }, { /* 11837 */ 222, /* VPMULTISHIFTQBZ256rrkz */ }, { /* 11838 */ 223, /* VPMULTISHIFTQBZrm */ }, { /* 11839 */ 224, /* VPMULTISHIFTQBZrmb */ }, { /* 11840 */ 225, /* VPMULTISHIFTQBZrmbk */ }, { /* 11841 */ 226, /* VPMULTISHIFTQBZrmbkz */ }, { /* 11842 */ 227, /* VPMULTISHIFTQBZrmk */ }, { /* 11843 */ 228, /* VPMULTISHIFTQBZrmkz */ }, { /* 11844 */ 229, /* VPMULTISHIFTQBZrr */ }, { /* 11845 */ 233, /* VPMULTISHIFTQBZrrk */ }, { /* 11846 */ 234, /* VPMULTISHIFTQBZrrkz */ }, { /* 11847 */ 204, /* VPMULUDQYrm */ }, { /* 11848 */ 205, /* VPMULUDQYrr */ }, { /* 11849 */ 206, /* VPMULUDQZ128rm */ }, { /* 11850 */ 207, /* VPMULUDQZ128rmb */ }, { /* 11851 */ 208, /* VPMULUDQZ128rmbk */ }, { /* 11852 */ 209, /* VPMULUDQZ128rmbkz */ }, { /* 11853 */ 203, /* VPMULUDQZ128rmk */ }, { /* 11854 */ 210, /* VPMULUDQZ128rmkz */ }, { /* 11855 */ 211, /* VPMULUDQZ128rr */ }, { /* 11856 */ 212, /* VPMULUDQZ128rrk */ }, { /* 11857 */ 213, /* VPMULUDQZ128rrkz */ }, { /* 11858 */ 214, /* VPMULUDQZ256rm */ }, { /* 11859 */ 215, /* VPMULUDQZ256rmb */ }, { /* 11860 */ 216, /* VPMULUDQZ256rmbk */ }, { /* 11861 */ 217, /* VPMULUDQZ256rmbkz */ }, { /* 11862 */ 218, /* VPMULUDQZ256rmk */ }, { /* 11863 */ 219, /* VPMULUDQZ256rmkz */ }, { /* 11864 */ 220, /* VPMULUDQZ256rr */ }, { /* 11865 */ 221, /* VPMULUDQZ256rrk */ }, { /* 11866 */ 222, /* VPMULUDQZ256rrkz */ }, { /* 11867 */ 223, /* VPMULUDQZrm */ }, { /* 11868 */ 224, /* VPMULUDQZrmb */ }, { /* 11869 */ 225, /* VPMULUDQZrmbk */ }, { /* 11870 */ 226, /* VPMULUDQZrmbkz */ }, { /* 11871 */ 227, /* VPMULUDQZrmk */ }, { /* 11872 */ 228, /* VPMULUDQZrmkz */ }, { /* 11873 */ 229, /* VPMULUDQZrr */ }, { /* 11874 */ 233, /* VPMULUDQZrrk */ }, { /* 11875 */ 234, /* VPMULUDQZrrkz */ }, { /* 11876 */ 235, /* VPMULUDQrm */ }, { /* 11877 */ 236, /* VPMULUDQrr */ }, { /* 11878 */ 409, /* VPOPCNTBZ128rm */ }, { /* 11879 */ 410, /* VPOPCNTBZ128rmk */ }, { /* 11880 */ 411, /* VPOPCNTBZ128rmkz */ }, { /* 11881 */ 330, /* VPOPCNTBZ128rr */ }, { /* 11882 */ 331, /* VPOPCNTBZ128rrk */ }, { /* 11883 */ 332, /* VPOPCNTBZ128rrkz */ }, { /* 11884 */ 412, /* VPOPCNTBZ256rm */ }, { /* 11885 */ 413, /* VPOPCNTBZ256rmk */ }, { /* 11886 */ 414, /* VPOPCNTBZ256rmkz */ }, { /* 11887 */ 415, /* VPOPCNTBZ256rr */ }, { /* 11888 */ 416, /* VPOPCNTBZ256rrk */ }, { /* 11889 */ 417, /* VPOPCNTBZ256rrkz */ }, { /* 11890 */ 418, /* VPOPCNTBZrm */ }, { /* 11891 */ 419, /* VPOPCNTBZrmk */ }, { /* 11892 */ 420, /* VPOPCNTBZrmkz */ }, { /* 11893 */ 421, /* VPOPCNTBZrr */ }, { /* 11894 */ 425, /* VPOPCNTBZrrk */ }, { /* 11895 */ 426, /* VPOPCNTBZrrkz */ }, { /* 11896 */ 409, /* VPOPCNTDZ128rm */ }, { /* 11897 */ 334, /* VPOPCNTDZ128rmb */ }, { /* 11898 */ 335, /* VPOPCNTDZ128rmbk */ }, { /* 11899 */ 336, /* VPOPCNTDZ128rmbkz */ }, { /* 11900 */ 410, /* VPOPCNTDZ128rmk */ }, { /* 11901 */ 411, /* VPOPCNTDZ128rmkz */ }, { /* 11902 */ 330, /* VPOPCNTDZ128rr */ }, { /* 11903 */ 331, /* VPOPCNTDZ128rrk */ }, { /* 11904 */ 332, /* VPOPCNTDZ128rrkz */ }, { /* 11905 */ 412, /* VPOPCNTDZ256rm */ }, { /* 11906 */ 337, /* VPOPCNTDZ256rmb */ }, { /* 11907 */ 338, /* VPOPCNTDZ256rmbk */ }, { /* 11908 */ 339, /* VPOPCNTDZ256rmbkz */ }, { /* 11909 */ 413, /* VPOPCNTDZ256rmk */ }, { /* 11910 */ 414, /* VPOPCNTDZ256rmkz */ }, { /* 11911 */ 415, /* VPOPCNTDZ256rr */ }, { /* 11912 */ 416, /* VPOPCNTDZ256rrk */ }, { /* 11913 */ 417, /* VPOPCNTDZ256rrkz */ }, { /* 11914 */ 418, /* VPOPCNTDZrm */ }, { /* 11915 */ 340, /* VPOPCNTDZrmb */ }, { /* 11916 */ 341, /* VPOPCNTDZrmbk */ }, { /* 11917 */ 342, /* VPOPCNTDZrmbkz */ }, { /* 11918 */ 419, /* VPOPCNTDZrmk */ }, { /* 11919 */ 420, /* VPOPCNTDZrmkz */ }, { /* 11920 */ 421, /* VPOPCNTDZrr */ }, { /* 11921 */ 425, /* VPOPCNTDZrrk */ }, { /* 11922 */ 426, /* VPOPCNTDZrrkz */ }, { /* 11923 */ 409, /* VPOPCNTQZ128rm */ }, { /* 11924 */ 327, /* VPOPCNTQZ128rmb */ }, { /* 11925 */ 328, /* VPOPCNTQZ128rmbk */ }, { /* 11926 */ 329, /* VPOPCNTQZ128rmbkz */ }, { /* 11927 */ 410, /* VPOPCNTQZ128rmk */ }, { /* 11928 */ 411, /* VPOPCNTQZ128rmkz */ }, { /* 11929 */ 330, /* VPOPCNTQZ128rr */ }, { /* 11930 */ 331, /* VPOPCNTQZ128rrk */ }, { /* 11931 */ 332, /* VPOPCNTQZ128rrkz */ }, { /* 11932 */ 412, /* VPOPCNTQZ256rm */ }, { /* 11933 */ 306, /* VPOPCNTQZ256rmb */ }, { /* 11934 */ 307, /* VPOPCNTQZ256rmbk */ }, { /* 11935 */ 308, /* VPOPCNTQZ256rmbkz */ }, { /* 11936 */ 413, /* VPOPCNTQZ256rmk */ }, { /* 11937 */ 414, /* VPOPCNTQZ256rmkz */ }, { /* 11938 */ 415, /* VPOPCNTQZ256rr */ }, { /* 11939 */ 416, /* VPOPCNTQZ256rrk */ }, { /* 11940 */ 417, /* VPOPCNTQZ256rrkz */ }, { /* 11941 */ 418, /* VPOPCNTQZrm */ }, { /* 11942 */ 312, /* VPOPCNTQZrmb */ }, { /* 11943 */ 313, /* VPOPCNTQZrmbk */ }, { /* 11944 */ 314, /* VPOPCNTQZrmbkz */ }, { /* 11945 */ 419, /* VPOPCNTQZrmk */ }, { /* 11946 */ 420, /* VPOPCNTQZrmkz */ }, { /* 11947 */ 421, /* VPOPCNTQZrr */ }, { /* 11948 */ 425, /* VPOPCNTQZrrk */ }, { /* 11949 */ 426, /* VPOPCNTQZrrkz */ }, { /* 11950 */ 409, /* VPOPCNTWZ128rm */ }, { /* 11951 */ 410, /* VPOPCNTWZ128rmk */ }, { /* 11952 */ 411, /* VPOPCNTWZ128rmkz */ }, { /* 11953 */ 330, /* VPOPCNTWZ128rr */ }, { /* 11954 */ 331, /* VPOPCNTWZ128rrk */ }, { /* 11955 */ 332, /* VPOPCNTWZ128rrkz */ }, { /* 11956 */ 412, /* VPOPCNTWZ256rm */ }, { /* 11957 */ 413, /* VPOPCNTWZ256rmk */ }, { /* 11958 */ 414, /* VPOPCNTWZ256rmkz */ }, { /* 11959 */ 415, /* VPOPCNTWZ256rr */ }, { /* 11960 */ 416, /* VPOPCNTWZ256rrk */ }, { /* 11961 */ 417, /* VPOPCNTWZ256rrkz */ }, { /* 11962 */ 418, /* VPOPCNTWZrm */ }, { /* 11963 */ 419, /* VPOPCNTWZrmk */ }, { /* 11964 */ 420, /* VPOPCNTWZrmkz */ }, { /* 11965 */ 421, /* VPOPCNTWZrr */ }, { /* 11966 */ 425, /* VPOPCNTWZrrk */ }, { /* 11967 */ 426, /* VPOPCNTWZrrkz */ }, { /* 11968 */ 206, /* VPORDZ128rm */ }, { /* 11969 */ 237, /* VPORDZ128rmb */ }, { /* 11970 */ 238, /* VPORDZ128rmbk */ }, { /* 11971 */ 239, /* VPORDZ128rmbkz */ }, { /* 11972 */ 203, /* VPORDZ128rmk */ }, { /* 11973 */ 210, /* VPORDZ128rmkz */ }, { /* 11974 */ 211, /* VPORDZ128rr */ }, { /* 11975 */ 212, /* VPORDZ128rrk */ }, { /* 11976 */ 213, /* VPORDZ128rrkz */ }, { /* 11977 */ 214, /* VPORDZ256rm */ }, { /* 11978 */ 240, /* VPORDZ256rmb */ }, { /* 11979 */ 241, /* VPORDZ256rmbk */ }, { /* 11980 */ 242, /* VPORDZ256rmbkz */ }, { /* 11981 */ 218, /* VPORDZ256rmk */ }, { /* 11982 */ 219, /* VPORDZ256rmkz */ }, { /* 11983 */ 220, /* VPORDZ256rr */ }, { /* 11984 */ 221, /* VPORDZ256rrk */ }, { /* 11985 */ 222, /* VPORDZ256rrkz */ }, { /* 11986 */ 223, /* VPORDZrm */ }, { /* 11987 */ 243, /* VPORDZrmb */ }, { /* 11988 */ 244, /* VPORDZrmbk */ }, { /* 11989 */ 245, /* VPORDZrmbkz */ }, { /* 11990 */ 227, /* VPORDZrmk */ }, { /* 11991 */ 228, /* VPORDZrmkz */ }, { /* 11992 */ 229, /* VPORDZrr */ }, { /* 11993 */ 233, /* VPORDZrrk */ }, { /* 11994 */ 234, /* VPORDZrrkz */ }, { /* 11995 */ 206, /* VPORQZ128rm */ }, { /* 11996 */ 207, /* VPORQZ128rmb */ }, { /* 11997 */ 208, /* VPORQZ128rmbk */ }, { /* 11998 */ 209, /* VPORQZ128rmbkz */ }, { /* 11999 */ 203, /* VPORQZ128rmk */ }, { /* 12000 */ 210, /* VPORQZ128rmkz */ }, { /* 12001 */ 211, /* VPORQZ128rr */ }, { /* 12002 */ 212, /* VPORQZ128rrk */ }, { /* 12003 */ 213, /* VPORQZ128rrkz */ }, { /* 12004 */ 214, /* VPORQZ256rm */ }, { /* 12005 */ 215, /* VPORQZ256rmb */ }, { /* 12006 */ 216, /* VPORQZ256rmbk */ }, { /* 12007 */ 217, /* VPORQZ256rmbkz */ }, { /* 12008 */ 218, /* VPORQZ256rmk */ }, { /* 12009 */ 219, /* VPORQZ256rmkz */ }, { /* 12010 */ 220, /* VPORQZ256rr */ }, { /* 12011 */ 221, /* VPORQZ256rrk */ }, { /* 12012 */ 222, /* VPORQZ256rrkz */ }, { /* 12013 */ 223, /* VPORQZrm */ }, { /* 12014 */ 224, /* VPORQZrmb */ }, { /* 12015 */ 225, /* VPORQZrmbk */ }, { /* 12016 */ 226, /* VPORQZrmbkz */ }, { /* 12017 */ 227, /* VPORQZrmk */ }, { /* 12018 */ 228, /* VPORQZrmkz */ }, { /* 12019 */ 229, /* VPORQZrr */ }, { /* 12020 */ 233, /* VPORQZrrk */ }, { /* 12021 */ 234, /* VPORQZrrkz */ }, { /* 12022 */ 204, /* VPORYrm */ }, { /* 12023 */ 205, /* VPORYrr */ }, { /* 12024 */ 235, /* VPORrm */ }, { /* 12025 */ 236, /* VPORrr */ }, { /* 12026 */ 303, /* VPPERMrmr */ }, { /* 12027 */ 550, /* VPPERMrrm */ }, { /* 12028 */ 304, /* VPPERMrrr */ }, { /* 12029 */ 551, /* VPPERMrrr_REV */ }, { /* 12030 */ 854, /* VPROLDZ128mbi */ }, { /* 12031 */ 855, /* VPROLDZ128mbik */ }, { /* 12032 */ 856, /* VPROLDZ128mbikz */ }, { /* 12033 */ 857, /* VPROLDZ128mi */ }, { /* 12034 */ 858, /* VPROLDZ128mik */ }, { /* 12035 */ 859, /* VPROLDZ128mikz */ }, { /* 12036 */ 860, /* VPROLDZ128ri */ }, { /* 12037 */ 861, /* VPROLDZ128rik */ }, { /* 12038 */ 862, /* VPROLDZ128rikz */ }, { /* 12039 */ 863, /* VPROLDZ256mbi */ }, { /* 12040 */ 864, /* VPROLDZ256mbik */ }, { /* 12041 */ 865, /* VPROLDZ256mbikz */ }, { /* 12042 */ 866, /* VPROLDZ256mi */ }, { /* 12043 */ 867, /* VPROLDZ256mik */ }, { /* 12044 */ 868, /* VPROLDZ256mikz */ }, { /* 12045 */ 869, /* VPROLDZ256ri */ }, { /* 12046 */ 870, /* VPROLDZ256rik */ }, { /* 12047 */ 871, /* VPROLDZ256rikz */ }, { /* 12048 */ 872, /* VPROLDZmbi */ }, { /* 12049 */ 873, /* VPROLDZmbik */ }, { /* 12050 */ 874, /* VPROLDZmbikz */ }, { /* 12051 */ 875, /* VPROLDZmi */ }, { /* 12052 */ 876, /* VPROLDZmik */ }, { /* 12053 */ 877, /* VPROLDZmikz */ }, { /* 12054 */ 878, /* VPROLDZri */ }, { /* 12055 */ 879, /* VPROLDZrik */ }, { /* 12056 */ 880, /* VPROLDZrikz */ }, { /* 12057 */ 881, /* VPROLQZ128mbi */ }, { /* 12058 */ 882, /* VPROLQZ128mbik */ }, { /* 12059 */ 883, /* VPROLQZ128mbikz */ }, { /* 12060 */ 857, /* VPROLQZ128mi */ }, { /* 12061 */ 858, /* VPROLQZ128mik */ }, { /* 12062 */ 859, /* VPROLQZ128mikz */ }, { /* 12063 */ 860, /* VPROLQZ128ri */ }, { /* 12064 */ 861, /* VPROLQZ128rik */ }, { /* 12065 */ 862, /* VPROLQZ128rikz */ }, { /* 12066 */ 884, /* VPROLQZ256mbi */ }, { /* 12067 */ 885, /* VPROLQZ256mbik */ }, { /* 12068 */ 886, /* VPROLQZ256mbikz */ }, { /* 12069 */ 866, /* VPROLQZ256mi */ }, { /* 12070 */ 867, /* VPROLQZ256mik */ }, { /* 12071 */ 868, /* VPROLQZ256mikz */ }, { /* 12072 */ 869, /* VPROLQZ256ri */ }, { /* 12073 */ 870, /* VPROLQZ256rik */ }, { /* 12074 */ 871, /* VPROLQZ256rikz */ }, { /* 12075 */ 887, /* VPROLQZmbi */ }, { /* 12076 */ 888, /* VPROLQZmbik */ }, { /* 12077 */ 889, /* VPROLQZmbikz */ }, { /* 12078 */ 875, /* VPROLQZmi */ }, { /* 12079 */ 876, /* VPROLQZmik */ }, { /* 12080 */ 877, /* VPROLQZmikz */ }, { /* 12081 */ 878, /* VPROLQZri */ }, { /* 12082 */ 879, /* VPROLQZrik */ }, { /* 12083 */ 880, /* VPROLQZrikz */ }, { /* 12084 */ 206, /* VPROLVDZ128rm */ }, { /* 12085 */ 237, /* VPROLVDZ128rmb */ }, { /* 12086 */ 238, /* VPROLVDZ128rmbk */ }, { /* 12087 */ 239, /* VPROLVDZ128rmbkz */ }, { /* 12088 */ 203, /* VPROLVDZ128rmk */ }, { /* 12089 */ 210, /* VPROLVDZ128rmkz */ }, { /* 12090 */ 211, /* VPROLVDZ128rr */ }, { /* 12091 */ 212, /* VPROLVDZ128rrk */ }, { /* 12092 */ 213, /* VPROLVDZ128rrkz */ }, { /* 12093 */ 214, /* VPROLVDZ256rm */ }, { /* 12094 */ 240, /* VPROLVDZ256rmb */ }, { /* 12095 */ 241, /* VPROLVDZ256rmbk */ }, { /* 12096 */ 242, /* VPROLVDZ256rmbkz */ }, { /* 12097 */ 218, /* VPROLVDZ256rmk */ }, { /* 12098 */ 219, /* VPROLVDZ256rmkz */ }, { /* 12099 */ 220, /* VPROLVDZ256rr */ }, { /* 12100 */ 221, /* VPROLVDZ256rrk */ }, { /* 12101 */ 222, /* VPROLVDZ256rrkz */ }, { /* 12102 */ 223, /* VPROLVDZrm */ }, { /* 12103 */ 243, /* VPROLVDZrmb */ }, { /* 12104 */ 244, /* VPROLVDZrmbk */ }, { /* 12105 */ 245, /* VPROLVDZrmbkz */ }, { /* 12106 */ 227, /* VPROLVDZrmk */ }, { /* 12107 */ 228, /* VPROLVDZrmkz */ }, { /* 12108 */ 229, /* VPROLVDZrr */ }, { /* 12109 */ 233, /* VPROLVDZrrk */ }, { /* 12110 */ 234, /* VPROLVDZrrkz */ }, { /* 12111 */ 206, /* VPROLVQZ128rm */ }, { /* 12112 */ 207, /* VPROLVQZ128rmb */ }, { /* 12113 */ 208, /* VPROLVQZ128rmbk */ }, { /* 12114 */ 209, /* VPROLVQZ128rmbkz */ }, { /* 12115 */ 203, /* VPROLVQZ128rmk */ }, { /* 12116 */ 210, /* VPROLVQZ128rmkz */ }, { /* 12117 */ 211, /* VPROLVQZ128rr */ }, { /* 12118 */ 212, /* VPROLVQZ128rrk */ }, { /* 12119 */ 213, /* VPROLVQZ128rrkz */ }, { /* 12120 */ 214, /* VPROLVQZ256rm */ }, { /* 12121 */ 215, /* VPROLVQZ256rmb */ }, { /* 12122 */ 216, /* VPROLVQZ256rmbk */ }, { /* 12123 */ 217, /* VPROLVQZ256rmbkz */ }, { /* 12124 */ 218, /* VPROLVQZ256rmk */ }, { /* 12125 */ 219, /* VPROLVQZ256rmkz */ }, { /* 12126 */ 220, /* VPROLVQZ256rr */ }, { /* 12127 */ 221, /* VPROLVQZ256rrk */ }, { /* 12128 */ 222, /* VPROLVQZ256rrkz */ }, { /* 12129 */ 223, /* VPROLVQZrm */ }, { /* 12130 */ 224, /* VPROLVQZrmb */ }, { /* 12131 */ 225, /* VPROLVQZrmbk */ }, { /* 12132 */ 226, /* VPROLVQZrmbkz */ }, { /* 12133 */ 227, /* VPROLVQZrmk */ }, { /* 12134 */ 228, /* VPROLVQZrmkz */ }, { /* 12135 */ 229, /* VPROLVQZrr */ }, { /* 12136 */ 233, /* VPROLVQZrrk */ }, { /* 12137 */ 234, /* VPROLVQZrrkz */ }, { /* 12138 */ 854, /* VPRORDZ128mbi */ }, { /* 12139 */ 855, /* VPRORDZ128mbik */ }, { /* 12140 */ 856, /* VPRORDZ128mbikz */ }, { /* 12141 */ 857, /* VPRORDZ128mi */ }, { /* 12142 */ 858, /* VPRORDZ128mik */ }, { /* 12143 */ 859, /* VPRORDZ128mikz */ }, { /* 12144 */ 860, /* VPRORDZ128ri */ }, { /* 12145 */ 861, /* VPRORDZ128rik */ }, { /* 12146 */ 862, /* VPRORDZ128rikz */ }, { /* 12147 */ 863, /* VPRORDZ256mbi */ }, { /* 12148 */ 864, /* VPRORDZ256mbik */ }, { /* 12149 */ 865, /* VPRORDZ256mbikz */ }, { /* 12150 */ 866, /* VPRORDZ256mi */ }, { /* 12151 */ 867, /* VPRORDZ256mik */ }, { /* 12152 */ 868, /* VPRORDZ256mikz */ }, { /* 12153 */ 869, /* VPRORDZ256ri */ }, { /* 12154 */ 870, /* VPRORDZ256rik */ }, { /* 12155 */ 871, /* VPRORDZ256rikz */ }, { /* 12156 */ 872, /* VPRORDZmbi */ }, { /* 12157 */ 873, /* VPRORDZmbik */ }, { /* 12158 */ 874, /* VPRORDZmbikz */ }, { /* 12159 */ 875, /* VPRORDZmi */ }, { /* 12160 */ 876, /* VPRORDZmik */ }, { /* 12161 */ 877, /* VPRORDZmikz */ }, { /* 12162 */ 878, /* VPRORDZri */ }, { /* 12163 */ 879, /* VPRORDZrik */ }, { /* 12164 */ 880, /* VPRORDZrikz */ }, { /* 12165 */ 881, /* VPRORQZ128mbi */ }, { /* 12166 */ 882, /* VPRORQZ128mbik */ }, { /* 12167 */ 883, /* VPRORQZ128mbikz */ }, { /* 12168 */ 857, /* VPRORQZ128mi */ }, { /* 12169 */ 858, /* VPRORQZ128mik */ }, { /* 12170 */ 859, /* VPRORQZ128mikz */ }, { /* 12171 */ 860, /* VPRORQZ128ri */ }, { /* 12172 */ 861, /* VPRORQZ128rik */ }, { /* 12173 */ 862, /* VPRORQZ128rikz */ }, { /* 12174 */ 884, /* VPRORQZ256mbi */ }, { /* 12175 */ 885, /* VPRORQZ256mbik */ }, { /* 12176 */ 886, /* VPRORQZ256mbikz */ }, { /* 12177 */ 866, /* VPRORQZ256mi */ }, { /* 12178 */ 867, /* VPRORQZ256mik */ }, { /* 12179 */ 868, /* VPRORQZ256mikz */ }, { /* 12180 */ 869, /* VPRORQZ256ri */ }, { /* 12181 */ 870, /* VPRORQZ256rik */ }, { /* 12182 */ 871, /* VPRORQZ256rikz */ }, { /* 12183 */ 887, /* VPRORQZmbi */ }, { /* 12184 */ 888, /* VPRORQZmbik */ }, { /* 12185 */ 889, /* VPRORQZmbikz */ }, { /* 12186 */ 875, /* VPRORQZmi */ }, { /* 12187 */ 876, /* VPRORQZmik */ }, { /* 12188 */ 877, /* VPRORQZmikz */ }, { /* 12189 */ 878, /* VPRORQZri */ }, { /* 12190 */ 879, /* VPRORQZrik */ }, { /* 12191 */ 880, /* VPRORQZrikz */ }, { /* 12192 */ 206, /* VPRORVDZ128rm */ }, { /* 12193 */ 237, /* VPRORVDZ128rmb */ }, { /* 12194 */ 238, /* VPRORVDZ128rmbk */ }, { /* 12195 */ 239, /* VPRORVDZ128rmbkz */ }, { /* 12196 */ 203, /* VPRORVDZ128rmk */ }, { /* 12197 */ 210, /* VPRORVDZ128rmkz */ }, { /* 12198 */ 211, /* VPRORVDZ128rr */ }, { /* 12199 */ 212, /* VPRORVDZ128rrk */ }, { /* 12200 */ 213, /* VPRORVDZ128rrkz */ }, { /* 12201 */ 214, /* VPRORVDZ256rm */ }, { /* 12202 */ 240, /* VPRORVDZ256rmb */ }, { /* 12203 */ 241, /* VPRORVDZ256rmbk */ }, { /* 12204 */ 242, /* VPRORVDZ256rmbkz */ }, { /* 12205 */ 218, /* VPRORVDZ256rmk */ }, { /* 12206 */ 219, /* VPRORVDZ256rmkz */ }, { /* 12207 */ 220, /* VPRORVDZ256rr */ }, { /* 12208 */ 221, /* VPRORVDZ256rrk */ }, { /* 12209 */ 222, /* VPRORVDZ256rrkz */ }, { /* 12210 */ 223, /* VPRORVDZrm */ }, { /* 12211 */ 243, /* VPRORVDZrmb */ }, { /* 12212 */ 244, /* VPRORVDZrmbk */ }, { /* 12213 */ 245, /* VPRORVDZrmbkz */ }, { /* 12214 */ 227, /* VPRORVDZrmk */ }, { /* 12215 */ 228, /* VPRORVDZrmkz */ }, { /* 12216 */ 229, /* VPRORVDZrr */ }, { /* 12217 */ 233, /* VPRORVDZrrk */ }, { /* 12218 */ 234, /* VPRORVDZrrkz */ }, { /* 12219 */ 206, /* VPRORVQZ128rm */ }, { /* 12220 */ 207, /* VPRORVQZ128rmb */ }, { /* 12221 */ 208, /* VPRORVQZ128rmbk */ }, { /* 12222 */ 209, /* VPRORVQZ128rmbkz */ }, { /* 12223 */ 203, /* VPRORVQZ128rmk */ }, { /* 12224 */ 210, /* VPRORVQZ128rmkz */ }, { /* 12225 */ 211, /* VPRORVQZ128rr */ }, { /* 12226 */ 212, /* VPRORVQZ128rrk */ }, { /* 12227 */ 213, /* VPRORVQZ128rrkz */ }, { /* 12228 */ 214, /* VPRORVQZ256rm */ }, { /* 12229 */ 215, /* VPRORVQZ256rmb */ }, { /* 12230 */ 216, /* VPRORVQZ256rmbk */ }, { /* 12231 */ 217, /* VPRORVQZ256rmbkz */ }, { /* 12232 */ 218, /* VPRORVQZ256rmk */ }, { /* 12233 */ 219, /* VPRORVQZ256rmkz */ }, { /* 12234 */ 220, /* VPRORVQZ256rr */ }, { /* 12235 */ 221, /* VPRORVQZ256rrk */ }, { /* 12236 */ 222, /* VPRORVQZ256rrkz */ }, { /* 12237 */ 223, /* VPRORVQZrm */ }, { /* 12238 */ 224, /* VPRORVQZrmb */ }, { /* 12239 */ 225, /* VPRORVQZrmbk */ }, { /* 12240 */ 226, /* VPRORVQZrmbkz */ }, { /* 12241 */ 227, /* VPRORVQZrmk */ }, { /* 12242 */ 228, /* VPRORVQZrmkz */ }, { /* 12243 */ 229, /* VPRORVQZrr */ }, { /* 12244 */ 233, /* VPRORVQZrrk */ }, { /* 12245 */ 234, /* VPRORVQZrrkz */ }, { /* 12246 */ 32, /* VPROTBmi */ }, { /* 12247 */ 890, /* VPROTBmr */ }, { /* 12248 */ 33, /* VPROTBri */ }, { /* 12249 */ 235, /* VPROTBrm */ }, { /* 12250 */ 891, /* VPROTBrr */ }, { /* 12251 */ 236, /* VPROTBrr_REV */ }, { /* 12252 */ 32, /* VPROTDmi */ }, { /* 12253 */ 890, /* VPROTDmr */ }, { /* 12254 */ 33, /* VPROTDri */ }, { /* 12255 */ 235, /* VPROTDrm */ }, { /* 12256 */ 891, /* VPROTDrr */ }, { /* 12257 */ 236, /* VPROTDrr_REV */ }, { /* 12258 */ 32, /* VPROTQmi */ }, { /* 12259 */ 890, /* VPROTQmr */ }, { /* 12260 */ 33, /* VPROTQri */ }, { /* 12261 */ 235, /* VPROTQrm */ }, { /* 12262 */ 891, /* VPROTQrr */ }, { /* 12263 */ 236, /* VPROTQrr_REV */ }, { /* 12264 */ 32, /* VPROTWmi */ }, { /* 12265 */ 890, /* VPROTWmr */ }, { /* 12266 */ 33, /* VPROTWri */ }, { /* 12267 */ 235, /* VPROTWrm */ }, { /* 12268 */ 891, /* VPROTWrr */ }, { /* 12269 */ 236, /* VPROTWrr_REV */ }, { /* 12270 */ 204, /* VPSADBWYrm */ }, { /* 12271 */ 205, /* VPSADBWYrr */ }, { /* 12272 */ 206, /* VPSADBWZ128rm */ }, { /* 12273 */ 211, /* VPSADBWZ128rr */ }, { /* 12274 */ 214, /* VPSADBWZ256rm */ }, { /* 12275 */ 220, /* VPSADBWZ256rr */ }, { /* 12276 */ 223, /* VPSADBWZrm */ }, { /* 12277 */ 229, /* VPSADBWZrr */ }, { /* 12278 */ 235, /* VPSADBWrm */ }, { /* 12279 */ 236, /* VPSADBWrr */ }, { /* 12280 */ 892, /* VPSCATTERDDZ128mr */ }, { /* 12281 */ 893, /* VPSCATTERDDZ256mr */ }, { /* 12282 */ 894, /* VPSCATTERDDZmr */ }, { /* 12283 */ 895, /* VPSCATTERDQZ128mr */ }, { /* 12284 */ 896, /* VPSCATTERDQZ256mr */ }, { /* 12285 */ 897, /* VPSCATTERDQZmr */ }, { /* 12286 */ 892, /* VPSCATTERQDZ128mr */ }, { /* 12287 */ 898, /* VPSCATTERQDZ256mr */ }, { /* 12288 */ 899, /* VPSCATTERQDZmr */ }, { /* 12289 */ 895, /* VPSCATTERQQZ128mr */ }, { /* 12290 */ 900, /* VPSCATTERQQZ256mr */ }, { /* 12291 */ 901, /* VPSCATTERQQZmr */ }, { /* 12292 */ 890, /* VPSHABmr */ }, { /* 12293 */ 235, /* VPSHABrm */ }, { /* 12294 */ 891, /* VPSHABrr */ }, { /* 12295 */ 236, /* VPSHABrr_REV */ }, { /* 12296 */ 890, /* VPSHADmr */ }, { /* 12297 */ 235, /* VPSHADrm */ }, { /* 12298 */ 891, /* VPSHADrr */ }, { /* 12299 */ 236, /* VPSHADrr_REV */ }, { /* 12300 */ 890, /* VPSHAQmr */ }, { /* 12301 */ 235, /* VPSHAQrm */ }, { /* 12302 */ 891, /* VPSHAQrr */ }, { /* 12303 */ 236, /* VPSHAQrr_REV */ }, { /* 12304 */ 890, /* VPSHAWmr */ }, { /* 12305 */ 235, /* VPSHAWrm */ }, { /* 12306 */ 891, /* VPSHAWrr */ }, { /* 12307 */ 236, /* VPSHAWrr_REV */ }, { /* 12308 */ 890, /* VPSHLBmr */ }, { /* 12309 */ 235, /* VPSHLBrm */ }, { /* 12310 */ 891, /* VPSHLBrr */ }, { /* 12311 */ 236, /* VPSHLBrr_REV */ }, { /* 12312 */ 261, /* VPSHLDDZ128rmbi */ }, { /* 12313 */ 262, /* VPSHLDDZ128rmbik */ }, { /* 12314 */ 263, /* VPSHLDDZ128rmbikz */ }, { /* 12315 */ 264, /* VPSHLDDZ128rmi */ }, { /* 12316 */ 265, /* VPSHLDDZ128rmik */ }, { /* 12317 */ 266, /* VPSHLDDZ128rmikz */ }, { /* 12318 */ 267, /* VPSHLDDZ128rri */ }, { /* 12319 */ 268, /* VPSHLDDZ128rrik */ }, { /* 12320 */ 269, /* VPSHLDDZ128rrikz */ }, { /* 12321 */ 270, /* VPSHLDDZ256rmbi */ }, { /* 12322 */ 271, /* VPSHLDDZ256rmbik */ }, { /* 12323 */ 272, /* VPSHLDDZ256rmbikz */ }, { /* 12324 */ 273, /* VPSHLDDZ256rmi */ }, { /* 12325 */ 274, /* VPSHLDDZ256rmik */ }, { /* 12326 */ 275, /* VPSHLDDZ256rmikz */ }, { /* 12327 */ 276, /* VPSHLDDZ256rri */ }, { /* 12328 */ 277, /* VPSHLDDZ256rrik */ }, { /* 12329 */ 278, /* VPSHLDDZ256rrikz */ }, { /* 12330 */ 279, /* VPSHLDDZrmbi */ }, { /* 12331 */ 280, /* VPSHLDDZrmbik */ }, { /* 12332 */ 281, /* VPSHLDDZrmbikz */ }, { /* 12333 */ 282, /* VPSHLDDZrmi */ }, { /* 12334 */ 283, /* VPSHLDDZrmik */ }, { /* 12335 */ 284, /* VPSHLDDZrmikz */ }, { /* 12336 */ 285, /* VPSHLDDZrri */ }, { /* 12337 */ 286, /* VPSHLDDZrrik */ }, { /* 12338 */ 287, /* VPSHLDDZrrikz */ }, { /* 12339 */ 288, /* VPSHLDQZ128rmbi */ }, { /* 12340 */ 289, /* VPSHLDQZ128rmbik */ }, { /* 12341 */ 290, /* VPSHLDQZ128rmbikz */ }, { /* 12342 */ 264, /* VPSHLDQZ128rmi */ }, { /* 12343 */ 265, /* VPSHLDQZ128rmik */ }, { /* 12344 */ 266, /* VPSHLDQZ128rmikz */ }, { /* 12345 */ 267, /* VPSHLDQZ128rri */ }, { /* 12346 */ 268, /* VPSHLDQZ128rrik */ }, { /* 12347 */ 269, /* VPSHLDQZ128rrikz */ }, { /* 12348 */ 291, /* VPSHLDQZ256rmbi */ }, { /* 12349 */ 292, /* VPSHLDQZ256rmbik */ }, { /* 12350 */ 293, /* VPSHLDQZ256rmbikz */ }, { /* 12351 */ 273, /* VPSHLDQZ256rmi */ }, { /* 12352 */ 274, /* VPSHLDQZ256rmik */ }, { /* 12353 */ 275, /* VPSHLDQZ256rmikz */ }, { /* 12354 */ 276, /* VPSHLDQZ256rri */ }, { /* 12355 */ 277, /* VPSHLDQZ256rrik */ }, { /* 12356 */ 278, /* VPSHLDQZ256rrikz */ }, { /* 12357 */ 294, /* VPSHLDQZrmbi */ }, { /* 12358 */ 295, /* VPSHLDQZrmbik */ }, { /* 12359 */ 296, /* VPSHLDQZrmbikz */ }, { /* 12360 */ 282, /* VPSHLDQZrmi */ }, { /* 12361 */ 283, /* VPSHLDQZrmik */ }, { /* 12362 */ 284, /* VPSHLDQZrmikz */ }, { /* 12363 */ 285, /* VPSHLDQZrri */ }, { /* 12364 */ 286, /* VPSHLDQZrrik */ }, { /* 12365 */ 287, /* VPSHLDQZrrikz */ }, { /* 12366 */ 202, /* VPSHLDVDZ128m */ }, { /* 12367 */ 540, /* VPSHLDVDZ128mb */ }, { /* 12368 */ 238, /* VPSHLDVDZ128mbk */ }, { /* 12369 */ 238, /* VPSHLDVDZ128mbkz */ }, { /* 12370 */ 203, /* VPSHLDVDZ128mk */ }, { /* 12371 */ 203, /* VPSHLDVDZ128mkz */ }, { /* 12372 */ 530, /* VPSHLDVDZ128r */ }, { /* 12373 */ 212, /* VPSHLDVDZ128rk */ }, { /* 12374 */ 212, /* VPSHLDVDZ128rkz */ }, { /* 12375 */ 531, /* VPSHLDVDZ256m */ }, { /* 12376 */ 541, /* VPSHLDVDZ256mb */ }, { /* 12377 */ 241, /* VPSHLDVDZ256mbk */ }, { /* 12378 */ 241, /* VPSHLDVDZ256mbkz */ }, { /* 12379 */ 218, /* VPSHLDVDZ256mk */ }, { /* 12380 */ 218, /* VPSHLDVDZ256mkz */ }, { /* 12381 */ 533, /* VPSHLDVDZ256r */ }, { /* 12382 */ 221, /* VPSHLDVDZ256rk */ }, { /* 12383 */ 221, /* VPSHLDVDZ256rkz */ }, { /* 12384 */ 534, /* VPSHLDVDZm */ }, { /* 12385 */ 542, /* VPSHLDVDZmb */ }, { /* 12386 */ 244, /* VPSHLDVDZmbk */ }, { /* 12387 */ 244, /* VPSHLDVDZmbkz */ }, { /* 12388 */ 227, /* VPSHLDVDZmk */ }, { /* 12389 */ 227, /* VPSHLDVDZmkz */ }, { /* 12390 */ 536, /* VPSHLDVDZr */ }, { /* 12391 */ 233, /* VPSHLDVDZrk */ }, { /* 12392 */ 233, /* VPSHLDVDZrkz */ }, { /* 12393 */ 202, /* VPSHLDVQZ128m */ }, { /* 12394 */ 529, /* VPSHLDVQZ128mb */ }, { /* 12395 */ 208, /* VPSHLDVQZ128mbk */ }, { /* 12396 */ 208, /* VPSHLDVQZ128mbkz */ }, { /* 12397 */ 203, /* VPSHLDVQZ128mk */ }, { /* 12398 */ 203, /* VPSHLDVQZ128mkz */ }, { /* 12399 */ 530, /* VPSHLDVQZ128r */ }, { /* 12400 */ 212, /* VPSHLDVQZ128rk */ }, { /* 12401 */ 212, /* VPSHLDVQZ128rkz */ }, { /* 12402 */ 531, /* VPSHLDVQZ256m */ }, { /* 12403 */ 532, /* VPSHLDVQZ256mb */ }, { /* 12404 */ 216, /* VPSHLDVQZ256mbk */ }, { /* 12405 */ 216, /* VPSHLDVQZ256mbkz */ }, { /* 12406 */ 218, /* VPSHLDVQZ256mk */ }, { /* 12407 */ 218, /* VPSHLDVQZ256mkz */ }, { /* 12408 */ 533, /* VPSHLDVQZ256r */ }, { /* 12409 */ 221, /* VPSHLDVQZ256rk */ }, { /* 12410 */ 221, /* VPSHLDVQZ256rkz */ }, { /* 12411 */ 534, /* VPSHLDVQZm */ }, { /* 12412 */ 535, /* VPSHLDVQZmb */ }, { /* 12413 */ 225, /* VPSHLDVQZmbk */ }, { /* 12414 */ 225, /* VPSHLDVQZmbkz */ }, { /* 12415 */ 227, /* VPSHLDVQZmk */ }, { /* 12416 */ 227, /* VPSHLDVQZmkz */ }, { /* 12417 */ 536, /* VPSHLDVQZr */ }, { /* 12418 */ 233, /* VPSHLDVQZrk */ }, { /* 12419 */ 233, /* VPSHLDVQZrkz */ }, { /* 12420 */ 202, /* VPSHLDVWZ128m */ }, { /* 12421 */ 203, /* VPSHLDVWZ128mk */ }, { /* 12422 */ 203, /* VPSHLDVWZ128mkz */ }, { /* 12423 */ 530, /* VPSHLDVWZ128r */ }, { /* 12424 */ 212, /* VPSHLDVWZ128rk */ }, { /* 12425 */ 212, /* VPSHLDVWZ128rkz */ }, { /* 12426 */ 531, /* VPSHLDVWZ256m */ }, { /* 12427 */ 218, /* VPSHLDVWZ256mk */ }, { /* 12428 */ 218, /* VPSHLDVWZ256mkz */ }, { /* 12429 */ 533, /* VPSHLDVWZ256r */ }, { /* 12430 */ 221, /* VPSHLDVWZ256rk */ }, { /* 12431 */ 221, /* VPSHLDVWZ256rkz */ }, { /* 12432 */ 534, /* VPSHLDVWZm */ }, { /* 12433 */ 227, /* VPSHLDVWZmk */ }, { /* 12434 */ 227, /* VPSHLDVWZmkz */ }, { /* 12435 */ 536, /* VPSHLDVWZr */ }, { /* 12436 */ 233, /* VPSHLDVWZrk */ }, { /* 12437 */ 233, /* VPSHLDVWZrkz */ }, { /* 12438 */ 264, /* VPSHLDWZ128rmi */ }, { /* 12439 */ 265, /* VPSHLDWZ128rmik */ }, { /* 12440 */ 266, /* VPSHLDWZ128rmikz */ }, { /* 12441 */ 267, /* VPSHLDWZ128rri */ }, { /* 12442 */ 268, /* VPSHLDWZ128rrik */ }, { /* 12443 */ 269, /* VPSHLDWZ128rrikz */ }, { /* 12444 */ 273, /* VPSHLDWZ256rmi */ }, { /* 12445 */ 274, /* VPSHLDWZ256rmik */ }, { /* 12446 */ 275, /* VPSHLDWZ256rmikz */ }, { /* 12447 */ 276, /* VPSHLDWZ256rri */ }, { /* 12448 */ 277, /* VPSHLDWZ256rrik */ }, { /* 12449 */ 278, /* VPSHLDWZ256rrikz */ }, { /* 12450 */ 282, /* VPSHLDWZrmi */ }, { /* 12451 */ 283, /* VPSHLDWZrmik */ }, { /* 12452 */ 284, /* VPSHLDWZrmikz */ }, { /* 12453 */ 285, /* VPSHLDWZrri */ }, { /* 12454 */ 286, /* VPSHLDWZrrik */ }, { /* 12455 */ 287, /* VPSHLDWZrrikz */ }, { /* 12456 */ 890, /* VPSHLDmr */ }, { /* 12457 */ 235, /* VPSHLDrm */ }, { /* 12458 */ 891, /* VPSHLDrr */ }, { /* 12459 */ 236, /* VPSHLDrr_REV */ }, { /* 12460 */ 890, /* VPSHLQmr */ }, { /* 12461 */ 235, /* VPSHLQrm */ }, { /* 12462 */ 891, /* VPSHLQrr */ }, { /* 12463 */ 236, /* VPSHLQrr_REV */ }, { /* 12464 */ 890, /* VPSHLWmr */ }, { /* 12465 */ 235, /* VPSHLWrm */ }, { /* 12466 */ 891, /* VPSHLWrr */ }, { /* 12467 */ 236, /* VPSHLWrr_REV */ }, { /* 12468 */ 261, /* VPSHRDDZ128rmbi */ }, { /* 12469 */ 262, /* VPSHRDDZ128rmbik */ }, { /* 12470 */ 263, /* VPSHRDDZ128rmbikz */ }, { /* 12471 */ 264, /* VPSHRDDZ128rmi */ }, { /* 12472 */ 265, /* VPSHRDDZ128rmik */ }, { /* 12473 */ 266, /* VPSHRDDZ128rmikz */ }, { /* 12474 */ 267, /* VPSHRDDZ128rri */ }, { /* 12475 */ 268, /* VPSHRDDZ128rrik */ }, { /* 12476 */ 269, /* VPSHRDDZ128rrikz */ }, { /* 12477 */ 270, /* VPSHRDDZ256rmbi */ }, { /* 12478 */ 271, /* VPSHRDDZ256rmbik */ }, { /* 12479 */ 272, /* VPSHRDDZ256rmbikz */ }, { /* 12480 */ 273, /* VPSHRDDZ256rmi */ }, { /* 12481 */ 274, /* VPSHRDDZ256rmik */ }, { /* 12482 */ 275, /* VPSHRDDZ256rmikz */ }, { /* 12483 */ 276, /* VPSHRDDZ256rri */ }, { /* 12484 */ 277, /* VPSHRDDZ256rrik */ }, { /* 12485 */ 278, /* VPSHRDDZ256rrikz */ }, { /* 12486 */ 279, /* VPSHRDDZrmbi */ }, { /* 12487 */ 280, /* VPSHRDDZrmbik */ }, { /* 12488 */ 281, /* VPSHRDDZrmbikz */ }, { /* 12489 */ 282, /* VPSHRDDZrmi */ }, { /* 12490 */ 283, /* VPSHRDDZrmik */ }, { /* 12491 */ 284, /* VPSHRDDZrmikz */ }, { /* 12492 */ 285, /* VPSHRDDZrri */ }, { /* 12493 */ 286, /* VPSHRDDZrrik */ }, { /* 12494 */ 287, /* VPSHRDDZrrikz */ }, { /* 12495 */ 288, /* VPSHRDQZ128rmbi */ }, { /* 12496 */ 289, /* VPSHRDQZ128rmbik */ }, { /* 12497 */ 290, /* VPSHRDQZ128rmbikz */ }, { /* 12498 */ 264, /* VPSHRDQZ128rmi */ }, { /* 12499 */ 265, /* VPSHRDQZ128rmik */ }, { /* 12500 */ 266, /* VPSHRDQZ128rmikz */ }, { /* 12501 */ 267, /* VPSHRDQZ128rri */ }, { /* 12502 */ 268, /* VPSHRDQZ128rrik */ }, { /* 12503 */ 269, /* VPSHRDQZ128rrikz */ }, { /* 12504 */ 291, /* VPSHRDQZ256rmbi */ }, { /* 12505 */ 292, /* VPSHRDQZ256rmbik */ }, { /* 12506 */ 293, /* VPSHRDQZ256rmbikz */ }, { /* 12507 */ 273, /* VPSHRDQZ256rmi */ }, { /* 12508 */ 274, /* VPSHRDQZ256rmik */ }, { /* 12509 */ 275, /* VPSHRDQZ256rmikz */ }, { /* 12510 */ 276, /* VPSHRDQZ256rri */ }, { /* 12511 */ 277, /* VPSHRDQZ256rrik */ }, { /* 12512 */ 278, /* VPSHRDQZ256rrikz */ }, { /* 12513 */ 294, /* VPSHRDQZrmbi */ }, { /* 12514 */ 295, /* VPSHRDQZrmbik */ }, { /* 12515 */ 296, /* VPSHRDQZrmbikz */ }, { /* 12516 */ 282, /* VPSHRDQZrmi */ }, { /* 12517 */ 283, /* VPSHRDQZrmik */ }, { /* 12518 */ 284, /* VPSHRDQZrmikz */ }, { /* 12519 */ 285, /* VPSHRDQZrri */ }, { /* 12520 */ 286, /* VPSHRDQZrrik */ }, { /* 12521 */ 287, /* VPSHRDQZrrikz */ }, { /* 12522 */ 202, /* VPSHRDVDZ128m */ }, { /* 12523 */ 540, /* VPSHRDVDZ128mb */ }, { /* 12524 */ 238, /* VPSHRDVDZ128mbk */ }, { /* 12525 */ 238, /* VPSHRDVDZ128mbkz */ }, { /* 12526 */ 203, /* VPSHRDVDZ128mk */ }, { /* 12527 */ 203, /* VPSHRDVDZ128mkz */ }, { /* 12528 */ 530, /* VPSHRDVDZ128r */ }, { /* 12529 */ 212, /* VPSHRDVDZ128rk */ }, { /* 12530 */ 212, /* VPSHRDVDZ128rkz */ }, { /* 12531 */ 531, /* VPSHRDVDZ256m */ }, { /* 12532 */ 541, /* VPSHRDVDZ256mb */ }, { /* 12533 */ 241, /* VPSHRDVDZ256mbk */ }, { /* 12534 */ 241, /* VPSHRDVDZ256mbkz */ }, { /* 12535 */ 218, /* VPSHRDVDZ256mk */ }, { /* 12536 */ 218, /* VPSHRDVDZ256mkz */ }, { /* 12537 */ 533, /* VPSHRDVDZ256r */ }, { /* 12538 */ 221, /* VPSHRDVDZ256rk */ }, { /* 12539 */ 221, /* VPSHRDVDZ256rkz */ }, { /* 12540 */ 534, /* VPSHRDVDZm */ }, { /* 12541 */ 542, /* VPSHRDVDZmb */ }, { /* 12542 */ 244, /* VPSHRDVDZmbk */ }, { /* 12543 */ 244, /* VPSHRDVDZmbkz */ }, { /* 12544 */ 227, /* VPSHRDVDZmk */ }, { /* 12545 */ 227, /* VPSHRDVDZmkz */ }, { /* 12546 */ 536, /* VPSHRDVDZr */ }, { /* 12547 */ 233, /* VPSHRDVDZrk */ }, { /* 12548 */ 233, /* VPSHRDVDZrkz */ }, { /* 12549 */ 202, /* VPSHRDVQZ128m */ }, { /* 12550 */ 529, /* VPSHRDVQZ128mb */ }, { /* 12551 */ 208, /* VPSHRDVQZ128mbk */ }, { /* 12552 */ 208, /* VPSHRDVQZ128mbkz */ }, { /* 12553 */ 203, /* VPSHRDVQZ128mk */ }, { /* 12554 */ 203, /* VPSHRDVQZ128mkz */ }, { /* 12555 */ 530, /* VPSHRDVQZ128r */ }, { /* 12556 */ 212, /* VPSHRDVQZ128rk */ }, { /* 12557 */ 212, /* VPSHRDVQZ128rkz */ }, { /* 12558 */ 531, /* VPSHRDVQZ256m */ }, { /* 12559 */ 532, /* VPSHRDVQZ256mb */ }, { /* 12560 */ 216, /* VPSHRDVQZ256mbk */ }, { /* 12561 */ 216, /* VPSHRDVQZ256mbkz */ }, { /* 12562 */ 218, /* VPSHRDVQZ256mk */ }, { /* 12563 */ 218, /* VPSHRDVQZ256mkz */ }, { /* 12564 */ 533, /* VPSHRDVQZ256r */ }, { /* 12565 */ 221, /* VPSHRDVQZ256rk */ }, { /* 12566 */ 221, /* VPSHRDVQZ256rkz */ }, { /* 12567 */ 534, /* VPSHRDVQZm */ }, { /* 12568 */ 535, /* VPSHRDVQZmb */ }, { /* 12569 */ 225, /* VPSHRDVQZmbk */ }, { /* 12570 */ 225, /* VPSHRDVQZmbkz */ }, { /* 12571 */ 227, /* VPSHRDVQZmk */ }, { /* 12572 */ 227, /* VPSHRDVQZmkz */ }, { /* 12573 */ 536, /* VPSHRDVQZr */ }, { /* 12574 */ 233, /* VPSHRDVQZrk */ }, { /* 12575 */ 233, /* VPSHRDVQZrkz */ }, { /* 12576 */ 202, /* VPSHRDVWZ128m */ }, { /* 12577 */ 203, /* VPSHRDVWZ128mk */ }, { /* 12578 */ 203, /* VPSHRDVWZ128mkz */ }, { /* 12579 */ 530, /* VPSHRDVWZ128r */ }, { /* 12580 */ 212, /* VPSHRDVWZ128rk */ }, { /* 12581 */ 212, /* VPSHRDVWZ128rkz */ }, { /* 12582 */ 531, /* VPSHRDVWZ256m */ }, { /* 12583 */ 218, /* VPSHRDVWZ256mk */ }, { /* 12584 */ 218, /* VPSHRDVWZ256mkz */ }, { /* 12585 */ 533, /* VPSHRDVWZ256r */ }, { /* 12586 */ 221, /* VPSHRDVWZ256rk */ }, { /* 12587 */ 221, /* VPSHRDVWZ256rkz */ }, { /* 12588 */ 534, /* VPSHRDVWZm */ }, { /* 12589 */ 227, /* VPSHRDVWZmk */ }, { /* 12590 */ 227, /* VPSHRDVWZmkz */ }, { /* 12591 */ 536, /* VPSHRDVWZr */ }, { /* 12592 */ 233, /* VPSHRDVWZrk */ }, { /* 12593 */ 233, /* VPSHRDVWZrkz */ }, { /* 12594 */ 264, /* VPSHRDWZ128rmi */ }, { /* 12595 */ 265, /* VPSHRDWZ128rmik */ }, { /* 12596 */ 266, /* VPSHRDWZ128rmikz */ }, { /* 12597 */ 267, /* VPSHRDWZ128rri */ }, { /* 12598 */ 268, /* VPSHRDWZ128rrik */ }, { /* 12599 */ 269, /* VPSHRDWZ128rrikz */ }, { /* 12600 */ 273, /* VPSHRDWZ256rmi */ }, { /* 12601 */ 274, /* VPSHRDWZ256rmik */ }, { /* 12602 */ 275, /* VPSHRDWZ256rmikz */ }, { /* 12603 */ 276, /* VPSHRDWZ256rri */ }, { /* 12604 */ 277, /* VPSHRDWZ256rrik */ }, { /* 12605 */ 278, /* VPSHRDWZ256rrikz */ }, { /* 12606 */ 282, /* VPSHRDWZrmi */ }, { /* 12607 */ 283, /* VPSHRDWZrmik */ }, { /* 12608 */ 284, /* VPSHRDWZrmikz */ }, { /* 12609 */ 285, /* VPSHRDWZrri */ }, { /* 12610 */ 286, /* VPSHRDWZrrik */ }, { /* 12611 */ 287, /* VPSHRDWZrrikz */ }, { /* 12612 */ 741, /* VPSHUFBITQMBZ128rm */ }, { /* 12613 */ 742, /* VPSHUFBITQMBZ128rmk */ }, { /* 12614 */ 743, /* VPSHUFBITQMBZ128rr */ }, { /* 12615 */ 744, /* VPSHUFBITQMBZ128rrk */ }, { /* 12616 */ 745, /* VPSHUFBITQMBZ256rm */ }, { /* 12617 */ 746, /* VPSHUFBITQMBZ256rmk */ }, { /* 12618 */ 747, /* VPSHUFBITQMBZ256rr */ }, { /* 12619 */ 748, /* VPSHUFBITQMBZ256rrk */ }, { /* 12620 */ 749, /* VPSHUFBITQMBZrm */ }, { /* 12621 */ 750, /* VPSHUFBITQMBZrmk */ }, { /* 12622 */ 751, /* VPSHUFBITQMBZrr */ }, { /* 12623 */ 752, /* VPSHUFBITQMBZrrk */ }, { /* 12624 */ 204, /* VPSHUFBYrm */ }, { /* 12625 */ 205, /* VPSHUFBYrr */ }, { /* 12626 */ 206, /* VPSHUFBZ128rm */ }, { /* 12627 */ 203, /* VPSHUFBZ128rmk */ }, { /* 12628 */ 210, /* VPSHUFBZ128rmkz */ }, { /* 12629 */ 211, /* VPSHUFBZ128rr */ }, { /* 12630 */ 212, /* VPSHUFBZ128rrk */ }, { /* 12631 */ 213, /* VPSHUFBZ128rrkz */ }, { /* 12632 */ 214, /* VPSHUFBZ256rm */ }, { /* 12633 */ 218, /* VPSHUFBZ256rmk */ }, { /* 12634 */ 219, /* VPSHUFBZ256rmkz */ }, { /* 12635 */ 220, /* VPSHUFBZ256rr */ }, { /* 12636 */ 221, /* VPSHUFBZ256rrk */ }, { /* 12637 */ 222, /* VPSHUFBZ256rrkz */ }, { /* 12638 */ 223, /* VPSHUFBZrm */ }, { /* 12639 */ 227, /* VPSHUFBZrmk */ }, { /* 12640 */ 228, /* VPSHUFBZrmkz */ }, { /* 12641 */ 229, /* VPSHUFBZrr */ }, { /* 12642 */ 233, /* VPSHUFBZrrk */ }, { /* 12643 */ 234, /* VPSHUFBZrrkz */ }, { /* 12644 */ 235, /* VPSHUFBrm */ }, { /* 12645 */ 236, /* VPSHUFBrr */ }, { /* 12646 */ 791, /* VPSHUFDYmi */ }, { /* 12647 */ 792, /* VPSHUFDYri */ }, { /* 12648 */ 619, /* VPSHUFDZ128mbi */ }, { /* 12649 */ 620, /* VPSHUFDZ128mbik */ }, { /* 12650 */ 621, /* VPSHUFDZ128mbikz */ }, { /* 12651 */ 592, /* VPSHUFDZ128mi */ }, { /* 12652 */ 593, /* VPSHUFDZ128mik */ }, { /* 12653 */ 594, /* VPSHUFDZ128mikz */ }, { /* 12654 */ 595, /* VPSHUFDZ128ri */ }, { /* 12655 */ 596, /* VPSHUFDZ128rik */ }, { /* 12656 */ 597, /* VPSHUFDZ128rikz */ }, { /* 12657 */ 622, /* VPSHUFDZ256mbi */ }, { /* 12658 */ 623, /* VPSHUFDZ256mbik */ }, { /* 12659 */ 624, /* VPSHUFDZ256mbikz */ }, { /* 12660 */ 601, /* VPSHUFDZ256mi */ }, { /* 12661 */ 602, /* VPSHUFDZ256mik */ }, { /* 12662 */ 603, /* VPSHUFDZ256mikz */ }, { /* 12663 */ 604, /* VPSHUFDZ256ri */ }, { /* 12664 */ 605, /* VPSHUFDZ256rik */ }, { /* 12665 */ 606, /* VPSHUFDZ256rikz */ }, { /* 12666 */ 625, /* VPSHUFDZmbi */ }, { /* 12667 */ 626, /* VPSHUFDZmbik */ }, { /* 12668 */ 627, /* VPSHUFDZmbikz */ }, { /* 12669 */ 610, /* VPSHUFDZmi */ }, { /* 12670 */ 611, /* VPSHUFDZmik */ }, { /* 12671 */ 612, /* VPSHUFDZmikz */ }, { /* 12672 */ 613, /* VPSHUFDZri */ }, { /* 12673 */ 617, /* VPSHUFDZrik */ }, { /* 12674 */ 618, /* VPSHUFDZrikz */ }, { /* 12675 */ 32, /* VPSHUFDmi */ }, { /* 12676 */ 33, /* VPSHUFDri */ }, { /* 12677 */ 791, /* VPSHUFHWYmi */ }, { /* 12678 */ 792, /* VPSHUFHWYri */ }, { /* 12679 */ 592, /* VPSHUFHWZ128mi */ }, { /* 12680 */ 593, /* VPSHUFHWZ128mik */ }, { /* 12681 */ 594, /* VPSHUFHWZ128mikz */ }, { /* 12682 */ 595, /* VPSHUFHWZ128ri */ }, { /* 12683 */ 596, /* VPSHUFHWZ128rik */ }, { /* 12684 */ 597, /* VPSHUFHWZ128rikz */ }, { /* 12685 */ 601, /* VPSHUFHWZ256mi */ }, { /* 12686 */ 602, /* VPSHUFHWZ256mik */ }, { /* 12687 */ 603, /* VPSHUFHWZ256mikz */ }, { /* 12688 */ 604, /* VPSHUFHWZ256ri */ }, { /* 12689 */ 605, /* VPSHUFHWZ256rik */ }, { /* 12690 */ 606, /* VPSHUFHWZ256rikz */ }, { /* 12691 */ 610, /* VPSHUFHWZmi */ }, { /* 12692 */ 611, /* VPSHUFHWZmik */ }, { /* 12693 */ 612, /* VPSHUFHWZmikz */ }, { /* 12694 */ 613, /* VPSHUFHWZri */ }, { /* 12695 */ 617, /* VPSHUFHWZrik */ }, { /* 12696 */ 618, /* VPSHUFHWZrikz */ }, { /* 12697 */ 32, /* VPSHUFHWmi */ }, { /* 12698 */ 33, /* VPSHUFHWri */ }, { /* 12699 */ 791, /* VPSHUFLWYmi */ }, { /* 12700 */ 792, /* VPSHUFLWYri */ }, { /* 12701 */ 592, /* VPSHUFLWZ128mi */ }, { /* 12702 */ 593, /* VPSHUFLWZ128mik */ }, { /* 12703 */ 594, /* VPSHUFLWZ128mikz */ }, { /* 12704 */ 595, /* VPSHUFLWZ128ri */ }, { /* 12705 */ 596, /* VPSHUFLWZ128rik */ }, { /* 12706 */ 597, /* VPSHUFLWZ128rikz */ }, { /* 12707 */ 601, /* VPSHUFLWZ256mi */ }, { /* 12708 */ 602, /* VPSHUFLWZ256mik */ }, { /* 12709 */ 603, /* VPSHUFLWZ256mikz */ }, { /* 12710 */ 604, /* VPSHUFLWZ256ri */ }, { /* 12711 */ 605, /* VPSHUFLWZ256rik */ }, { /* 12712 */ 606, /* VPSHUFLWZ256rikz */ }, { /* 12713 */ 610, /* VPSHUFLWZmi */ }, { /* 12714 */ 611, /* VPSHUFLWZmik */ }, { /* 12715 */ 612, /* VPSHUFLWZmikz */ }, { /* 12716 */ 613, /* VPSHUFLWZri */ }, { /* 12717 */ 617, /* VPSHUFLWZrik */ }, { /* 12718 */ 618, /* VPSHUFLWZrikz */ }, { /* 12719 */ 32, /* VPSHUFLWmi */ }, { /* 12720 */ 33, /* VPSHUFLWri */ }, { /* 12721 */ 204, /* VPSIGNBYrm */ }, { /* 12722 */ 205, /* VPSIGNBYrr */ }, { /* 12723 */ 235, /* VPSIGNBrm */ }, { /* 12724 */ 236, /* VPSIGNBrr */ }, { /* 12725 */ 204, /* VPSIGNDYrm */ }, { /* 12726 */ 205, /* VPSIGNDYrr */ }, { /* 12727 */ 235, /* VPSIGNDrm */ }, { /* 12728 */ 236, /* VPSIGNDrr */ }, { /* 12729 */ 204, /* VPSIGNWYrm */ }, { /* 12730 */ 205, /* VPSIGNWYrr */ }, { /* 12731 */ 235, /* VPSIGNWrm */ }, { /* 12732 */ 236, /* VPSIGNWrr */ }, { /* 12733 */ 902, /* VPSLLDQYri */ }, { /* 12734 */ 857, /* VPSLLDQZ128rm */ }, { /* 12735 */ 860, /* VPSLLDQZ128rr */ }, { /* 12736 */ 866, /* VPSLLDQZ256rm */ }, { /* 12737 */ 869, /* VPSLLDQZ256rr */ }, { /* 12738 */ 875, /* VPSLLDQZrm */ }, { /* 12739 */ 878, /* VPSLLDQZrr */ }, { /* 12740 */ 903, /* VPSLLDQri */ }, { /* 12741 */ 902, /* VPSLLDYri */ }, { /* 12742 */ 204, /* VPSLLDYrm */ }, { /* 12743 */ 904, /* VPSLLDYrr */ }, { /* 12744 */ 854, /* VPSLLDZ128mbi */ }, { /* 12745 */ 855, /* VPSLLDZ128mbik */ }, { /* 12746 */ 856, /* VPSLLDZ128mbikz */ }, { /* 12747 */ 857, /* VPSLLDZ128mi */ }, { /* 12748 */ 858, /* VPSLLDZ128mik */ }, { /* 12749 */ 859, /* VPSLLDZ128mikz */ }, { /* 12750 */ 860, /* VPSLLDZ128ri */ }, { /* 12751 */ 861, /* VPSLLDZ128rik */ }, { /* 12752 */ 862, /* VPSLLDZ128rikz */ }, { /* 12753 */ 206, /* VPSLLDZ128rm */ }, { /* 12754 */ 203, /* VPSLLDZ128rmk */ }, { /* 12755 */ 210, /* VPSLLDZ128rmkz */ }, { /* 12756 */ 211, /* VPSLLDZ128rr */ }, { /* 12757 */ 212, /* VPSLLDZ128rrk */ }, { /* 12758 */ 213, /* VPSLLDZ128rrkz */ }, { /* 12759 */ 863, /* VPSLLDZ256mbi */ }, { /* 12760 */ 864, /* VPSLLDZ256mbik */ }, { /* 12761 */ 865, /* VPSLLDZ256mbikz */ }, { /* 12762 */ 866, /* VPSLLDZ256mi */ }, { /* 12763 */ 867, /* VPSLLDZ256mik */ }, { /* 12764 */ 868, /* VPSLLDZ256mikz */ }, { /* 12765 */ 869, /* VPSLLDZ256ri */ }, { /* 12766 */ 870, /* VPSLLDZ256rik */ }, { /* 12767 */ 871, /* VPSLLDZ256rikz */ }, { /* 12768 */ 905, /* VPSLLDZ256rm */ }, { /* 12769 */ 906, /* VPSLLDZ256rmk */ }, { /* 12770 */ 907, /* VPSLLDZ256rmkz */ }, { /* 12771 */ 908, /* VPSLLDZ256rr */ }, { /* 12772 */ 909, /* VPSLLDZ256rrk */ }, { /* 12773 */ 910, /* VPSLLDZ256rrkz */ }, { /* 12774 */ 872, /* VPSLLDZmbi */ }, { /* 12775 */ 873, /* VPSLLDZmbik */ }, { /* 12776 */ 874, /* VPSLLDZmbikz */ }, { /* 12777 */ 875, /* VPSLLDZmi */ }, { /* 12778 */ 876, /* VPSLLDZmik */ }, { /* 12779 */ 877, /* VPSLLDZmikz */ }, { /* 12780 */ 878, /* VPSLLDZri */ }, { /* 12781 */ 879, /* VPSLLDZrik */ }, { /* 12782 */ 880, /* VPSLLDZrikz */ }, { /* 12783 */ 911, /* VPSLLDZrm */ }, { /* 12784 */ 201, /* VPSLLDZrmk */ }, { /* 12785 */ 912, /* VPSLLDZrmkz */ }, { /* 12786 */ 913, /* VPSLLDZrr */ }, { /* 12787 */ 914, /* VPSLLDZrrk */ }, { /* 12788 */ 915, /* VPSLLDZrrkz */ }, { /* 12789 */ 903, /* VPSLLDri */ }, { /* 12790 */ 235, /* VPSLLDrm */ }, { /* 12791 */ 236, /* VPSLLDrr */ }, { /* 12792 */ 902, /* VPSLLQYri */ }, { /* 12793 */ 204, /* VPSLLQYrm */ }, { /* 12794 */ 904, /* VPSLLQYrr */ }, { /* 12795 */ 881, /* VPSLLQZ128mbi */ }, { /* 12796 */ 882, /* VPSLLQZ128mbik */ }, { /* 12797 */ 883, /* VPSLLQZ128mbikz */ }, { /* 12798 */ 857, /* VPSLLQZ128mi */ }, { /* 12799 */ 858, /* VPSLLQZ128mik */ }, { /* 12800 */ 859, /* VPSLLQZ128mikz */ }, { /* 12801 */ 860, /* VPSLLQZ128ri */ }, { /* 12802 */ 861, /* VPSLLQZ128rik */ }, { /* 12803 */ 862, /* VPSLLQZ128rikz */ }, { /* 12804 */ 206, /* VPSLLQZ128rm */ }, { /* 12805 */ 203, /* VPSLLQZ128rmk */ }, { /* 12806 */ 210, /* VPSLLQZ128rmkz */ }, { /* 12807 */ 211, /* VPSLLQZ128rr */ }, { /* 12808 */ 212, /* VPSLLQZ128rrk */ }, { /* 12809 */ 213, /* VPSLLQZ128rrkz */ }, { /* 12810 */ 884, /* VPSLLQZ256mbi */ }, { /* 12811 */ 885, /* VPSLLQZ256mbik */ }, { /* 12812 */ 886, /* VPSLLQZ256mbikz */ }, { /* 12813 */ 866, /* VPSLLQZ256mi */ }, { /* 12814 */ 867, /* VPSLLQZ256mik */ }, { /* 12815 */ 868, /* VPSLLQZ256mikz */ }, { /* 12816 */ 869, /* VPSLLQZ256ri */ }, { /* 12817 */ 870, /* VPSLLQZ256rik */ }, { /* 12818 */ 871, /* VPSLLQZ256rikz */ }, { /* 12819 */ 905, /* VPSLLQZ256rm */ }, { /* 12820 */ 906, /* VPSLLQZ256rmk */ }, { /* 12821 */ 907, /* VPSLLQZ256rmkz */ }, { /* 12822 */ 908, /* VPSLLQZ256rr */ }, { /* 12823 */ 909, /* VPSLLQZ256rrk */ }, { /* 12824 */ 910, /* VPSLLQZ256rrkz */ }, { /* 12825 */ 887, /* VPSLLQZmbi */ }, { /* 12826 */ 888, /* VPSLLQZmbik */ }, { /* 12827 */ 889, /* VPSLLQZmbikz */ }, { /* 12828 */ 875, /* VPSLLQZmi */ }, { /* 12829 */ 876, /* VPSLLQZmik */ }, { /* 12830 */ 877, /* VPSLLQZmikz */ }, { /* 12831 */ 878, /* VPSLLQZri */ }, { /* 12832 */ 879, /* VPSLLQZrik */ }, { /* 12833 */ 880, /* VPSLLQZrikz */ }, { /* 12834 */ 911, /* VPSLLQZrm */ }, { /* 12835 */ 201, /* VPSLLQZrmk */ }, { /* 12836 */ 912, /* VPSLLQZrmkz */ }, { /* 12837 */ 913, /* VPSLLQZrr */ }, { /* 12838 */ 914, /* VPSLLQZrrk */ }, { /* 12839 */ 915, /* VPSLLQZrrkz */ }, { /* 12840 */ 903, /* VPSLLQri */ }, { /* 12841 */ 235, /* VPSLLQrm */ }, { /* 12842 */ 236, /* VPSLLQrr */ }, { /* 12843 */ 204, /* VPSLLVDYrm */ }, { /* 12844 */ 205, /* VPSLLVDYrr */ }, { /* 12845 */ 206, /* VPSLLVDZ128rm */ }, { /* 12846 */ 237, /* VPSLLVDZ128rmb */ }, { /* 12847 */ 238, /* VPSLLVDZ128rmbk */ }, { /* 12848 */ 239, /* VPSLLVDZ128rmbkz */ }, { /* 12849 */ 203, /* VPSLLVDZ128rmk */ }, { /* 12850 */ 210, /* VPSLLVDZ128rmkz */ }, { /* 12851 */ 211, /* VPSLLVDZ128rr */ }, { /* 12852 */ 212, /* VPSLLVDZ128rrk */ }, { /* 12853 */ 213, /* VPSLLVDZ128rrkz */ }, { /* 12854 */ 214, /* VPSLLVDZ256rm */ }, { /* 12855 */ 240, /* VPSLLVDZ256rmb */ }, { /* 12856 */ 241, /* VPSLLVDZ256rmbk */ }, { /* 12857 */ 242, /* VPSLLVDZ256rmbkz */ }, { /* 12858 */ 218, /* VPSLLVDZ256rmk */ }, { /* 12859 */ 219, /* VPSLLVDZ256rmkz */ }, { /* 12860 */ 220, /* VPSLLVDZ256rr */ }, { /* 12861 */ 221, /* VPSLLVDZ256rrk */ }, { /* 12862 */ 222, /* VPSLLVDZ256rrkz */ }, { /* 12863 */ 223, /* VPSLLVDZrm */ }, { /* 12864 */ 243, /* VPSLLVDZrmb */ }, { /* 12865 */ 244, /* VPSLLVDZrmbk */ }, { /* 12866 */ 245, /* VPSLLVDZrmbkz */ }, { /* 12867 */ 227, /* VPSLLVDZrmk */ }, { /* 12868 */ 228, /* VPSLLVDZrmkz */ }, { /* 12869 */ 229, /* VPSLLVDZrr */ }, { /* 12870 */ 233, /* VPSLLVDZrrk */ }, { /* 12871 */ 234, /* VPSLLVDZrrkz */ }, { /* 12872 */ 235, /* VPSLLVDrm */ }, { /* 12873 */ 236, /* VPSLLVDrr */ }, { /* 12874 */ 204, /* VPSLLVQYrm */ }, { /* 12875 */ 205, /* VPSLLVQYrr */ }, { /* 12876 */ 206, /* VPSLLVQZ128rm */ }, { /* 12877 */ 207, /* VPSLLVQZ128rmb */ }, { /* 12878 */ 208, /* VPSLLVQZ128rmbk */ }, { /* 12879 */ 209, /* VPSLLVQZ128rmbkz */ }, { /* 12880 */ 203, /* VPSLLVQZ128rmk */ }, { /* 12881 */ 210, /* VPSLLVQZ128rmkz */ }, { /* 12882 */ 211, /* VPSLLVQZ128rr */ }, { /* 12883 */ 212, /* VPSLLVQZ128rrk */ }, { /* 12884 */ 213, /* VPSLLVQZ128rrkz */ }, { /* 12885 */ 214, /* VPSLLVQZ256rm */ }, { /* 12886 */ 215, /* VPSLLVQZ256rmb */ }, { /* 12887 */ 216, /* VPSLLVQZ256rmbk */ }, { /* 12888 */ 217, /* VPSLLVQZ256rmbkz */ }, { /* 12889 */ 218, /* VPSLLVQZ256rmk */ }, { /* 12890 */ 219, /* VPSLLVQZ256rmkz */ }, { /* 12891 */ 220, /* VPSLLVQZ256rr */ }, { /* 12892 */ 221, /* VPSLLVQZ256rrk */ }, { /* 12893 */ 222, /* VPSLLVQZ256rrkz */ }, { /* 12894 */ 223, /* VPSLLVQZrm */ }, { /* 12895 */ 224, /* VPSLLVQZrmb */ }, { /* 12896 */ 225, /* VPSLLVQZrmbk */ }, { /* 12897 */ 226, /* VPSLLVQZrmbkz */ }, { /* 12898 */ 227, /* VPSLLVQZrmk */ }, { /* 12899 */ 228, /* VPSLLVQZrmkz */ }, { /* 12900 */ 229, /* VPSLLVQZrr */ }, { /* 12901 */ 233, /* VPSLLVQZrrk */ }, { /* 12902 */ 234, /* VPSLLVQZrrkz */ }, { /* 12903 */ 235, /* VPSLLVQrm */ }, { /* 12904 */ 236, /* VPSLLVQrr */ }, { /* 12905 */ 206, /* VPSLLVWZ128rm */ }, { /* 12906 */ 203, /* VPSLLVWZ128rmk */ }, { /* 12907 */ 210, /* VPSLLVWZ128rmkz */ }, { /* 12908 */ 211, /* VPSLLVWZ128rr */ }, { /* 12909 */ 212, /* VPSLLVWZ128rrk */ }, { /* 12910 */ 213, /* VPSLLVWZ128rrkz */ }, { /* 12911 */ 214, /* VPSLLVWZ256rm */ }, { /* 12912 */ 218, /* VPSLLVWZ256rmk */ }, { /* 12913 */ 219, /* VPSLLVWZ256rmkz */ }, { /* 12914 */ 220, /* VPSLLVWZ256rr */ }, { /* 12915 */ 221, /* VPSLLVWZ256rrk */ }, { /* 12916 */ 222, /* VPSLLVWZ256rrkz */ }, { /* 12917 */ 223, /* VPSLLVWZrm */ }, { /* 12918 */ 227, /* VPSLLVWZrmk */ }, { /* 12919 */ 228, /* VPSLLVWZrmkz */ }, { /* 12920 */ 229, /* VPSLLVWZrr */ }, { /* 12921 */ 233, /* VPSLLVWZrrk */ }, { /* 12922 */ 234, /* VPSLLVWZrrkz */ }, { /* 12923 */ 902, /* VPSLLWYri */ }, { /* 12924 */ 204, /* VPSLLWYrm */ }, { /* 12925 */ 904, /* VPSLLWYrr */ }, { /* 12926 */ 857, /* VPSLLWZ128mi */ }, { /* 12927 */ 858, /* VPSLLWZ128mik */ }, { /* 12928 */ 859, /* VPSLLWZ128mikz */ }, { /* 12929 */ 860, /* VPSLLWZ128ri */ }, { /* 12930 */ 861, /* VPSLLWZ128rik */ }, { /* 12931 */ 862, /* VPSLLWZ128rikz */ }, { /* 12932 */ 206, /* VPSLLWZ128rm */ }, { /* 12933 */ 203, /* VPSLLWZ128rmk */ }, { /* 12934 */ 210, /* VPSLLWZ128rmkz */ }, { /* 12935 */ 211, /* VPSLLWZ128rr */ }, { /* 12936 */ 212, /* VPSLLWZ128rrk */ }, { /* 12937 */ 213, /* VPSLLWZ128rrkz */ }, { /* 12938 */ 866, /* VPSLLWZ256mi */ }, { /* 12939 */ 867, /* VPSLLWZ256mik */ }, { /* 12940 */ 868, /* VPSLLWZ256mikz */ }, { /* 12941 */ 869, /* VPSLLWZ256ri */ }, { /* 12942 */ 870, /* VPSLLWZ256rik */ }, { /* 12943 */ 871, /* VPSLLWZ256rikz */ }, { /* 12944 */ 905, /* VPSLLWZ256rm */ }, { /* 12945 */ 906, /* VPSLLWZ256rmk */ }, { /* 12946 */ 907, /* VPSLLWZ256rmkz */ }, { /* 12947 */ 908, /* VPSLLWZ256rr */ }, { /* 12948 */ 909, /* VPSLLWZ256rrk */ }, { /* 12949 */ 910, /* VPSLLWZ256rrkz */ }, { /* 12950 */ 875, /* VPSLLWZmi */ }, { /* 12951 */ 876, /* VPSLLWZmik */ }, { /* 12952 */ 877, /* VPSLLWZmikz */ }, { /* 12953 */ 878, /* VPSLLWZri */ }, { /* 12954 */ 879, /* VPSLLWZrik */ }, { /* 12955 */ 880, /* VPSLLWZrikz */ }, { /* 12956 */ 911, /* VPSLLWZrm */ }, { /* 12957 */ 201, /* VPSLLWZrmk */ }, { /* 12958 */ 912, /* VPSLLWZrmkz */ }, { /* 12959 */ 913, /* VPSLLWZrr */ }, { /* 12960 */ 914, /* VPSLLWZrrk */ }, { /* 12961 */ 915, /* VPSLLWZrrkz */ }, { /* 12962 */ 903, /* VPSLLWri */ }, { /* 12963 */ 235, /* VPSLLWrm */ }, { /* 12964 */ 236, /* VPSLLWrr */ }, { /* 12965 */ 902, /* VPSRADYri */ }, { /* 12966 */ 204, /* VPSRADYrm */ }, { /* 12967 */ 904, /* VPSRADYrr */ }, { /* 12968 */ 854, /* VPSRADZ128mbi */ }, { /* 12969 */ 855, /* VPSRADZ128mbik */ }, { /* 12970 */ 856, /* VPSRADZ128mbikz */ }, { /* 12971 */ 857, /* VPSRADZ128mi */ }, { /* 12972 */ 858, /* VPSRADZ128mik */ }, { /* 12973 */ 859, /* VPSRADZ128mikz */ }, { /* 12974 */ 860, /* VPSRADZ128ri */ }, { /* 12975 */ 861, /* VPSRADZ128rik */ }, { /* 12976 */ 862, /* VPSRADZ128rikz */ }, { /* 12977 */ 206, /* VPSRADZ128rm */ }, { /* 12978 */ 203, /* VPSRADZ128rmk */ }, { /* 12979 */ 210, /* VPSRADZ128rmkz */ }, { /* 12980 */ 211, /* VPSRADZ128rr */ }, { /* 12981 */ 212, /* VPSRADZ128rrk */ }, { /* 12982 */ 213, /* VPSRADZ128rrkz */ }, { /* 12983 */ 863, /* VPSRADZ256mbi */ }, { /* 12984 */ 864, /* VPSRADZ256mbik */ }, { /* 12985 */ 865, /* VPSRADZ256mbikz */ }, { /* 12986 */ 866, /* VPSRADZ256mi */ }, { /* 12987 */ 867, /* VPSRADZ256mik */ }, { /* 12988 */ 868, /* VPSRADZ256mikz */ }, { /* 12989 */ 869, /* VPSRADZ256ri */ }, { /* 12990 */ 870, /* VPSRADZ256rik */ }, { /* 12991 */ 871, /* VPSRADZ256rikz */ }, { /* 12992 */ 905, /* VPSRADZ256rm */ }, { /* 12993 */ 906, /* VPSRADZ256rmk */ }, { /* 12994 */ 907, /* VPSRADZ256rmkz */ }, { /* 12995 */ 908, /* VPSRADZ256rr */ }, { /* 12996 */ 909, /* VPSRADZ256rrk */ }, { /* 12997 */ 910, /* VPSRADZ256rrkz */ }, { /* 12998 */ 872, /* VPSRADZmbi */ }, { /* 12999 */ 873, /* VPSRADZmbik */ }, { /* 13000 */ 874, /* VPSRADZmbikz */ }, { /* 13001 */ 875, /* VPSRADZmi */ }, { /* 13002 */ 876, /* VPSRADZmik */ }, { /* 13003 */ 877, /* VPSRADZmikz */ }, { /* 13004 */ 878, /* VPSRADZri */ }, { /* 13005 */ 879, /* VPSRADZrik */ }, { /* 13006 */ 880, /* VPSRADZrikz */ }, { /* 13007 */ 911, /* VPSRADZrm */ }, { /* 13008 */ 201, /* VPSRADZrmk */ }, { /* 13009 */ 912, /* VPSRADZrmkz */ }, { /* 13010 */ 913, /* VPSRADZrr */ }, { /* 13011 */ 914, /* VPSRADZrrk */ }, { /* 13012 */ 915, /* VPSRADZrrkz */ }, { /* 13013 */ 903, /* VPSRADri */ }, { /* 13014 */ 235, /* VPSRADrm */ }, { /* 13015 */ 236, /* VPSRADrr */ }, { /* 13016 */ 881, /* VPSRAQZ128mbi */ }, { /* 13017 */ 882, /* VPSRAQZ128mbik */ }, { /* 13018 */ 883, /* VPSRAQZ128mbikz */ }, { /* 13019 */ 857, /* VPSRAQZ128mi */ }, { /* 13020 */ 858, /* VPSRAQZ128mik */ }, { /* 13021 */ 859, /* VPSRAQZ128mikz */ }, { /* 13022 */ 860, /* VPSRAQZ128ri */ }, { /* 13023 */ 861, /* VPSRAQZ128rik */ }, { /* 13024 */ 862, /* VPSRAQZ128rikz */ }, { /* 13025 */ 206, /* VPSRAQZ128rm */ }, { /* 13026 */ 203, /* VPSRAQZ128rmk */ }, { /* 13027 */ 210, /* VPSRAQZ128rmkz */ }, { /* 13028 */ 211, /* VPSRAQZ128rr */ }, { /* 13029 */ 212, /* VPSRAQZ128rrk */ }, { /* 13030 */ 213, /* VPSRAQZ128rrkz */ }, { /* 13031 */ 884, /* VPSRAQZ256mbi */ }, { /* 13032 */ 885, /* VPSRAQZ256mbik */ }, { /* 13033 */ 886, /* VPSRAQZ256mbikz */ }, { /* 13034 */ 866, /* VPSRAQZ256mi */ }, { /* 13035 */ 867, /* VPSRAQZ256mik */ }, { /* 13036 */ 868, /* VPSRAQZ256mikz */ }, { /* 13037 */ 869, /* VPSRAQZ256ri */ }, { /* 13038 */ 870, /* VPSRAQZ256rik */ }, { /* 13039 */ 871, /* VPSRAQZ256rikz */ }, { /* 13040 */ 905, /* VPSRAQZ256rm */ }, { /* 13041 */ 906, /* VPSRAQZ256rmk */ }, { /* 13042 */ 907, /* VPSRAQZ256rmkz */ }, { /* 13043 */ 908, /* VPSRAQZ256rr */ }, { /* 13044 */ 909, /* VPSRAQZ256rrk */ }, { /* 13045 */ 910, /* VPSRAQZ256rrkz */ }, { /* 13046 */ 887, /* VPSRAQZmbi */ }, { /* 13047 */ 888, /* VPSRAQZmbik */ }, { /* 13048 */ 889, /* VPSRAQZmbikz */ }, { /* 13049 */ 875, /* VPSRAQZmi */ }, { /* 13050 */ 876, /* VPSRAQZmik */ }, { /* 13051 */ 877, /* VPSRAQZmikz */ }, { /* 13052 */ 878, /* VPSRAQZri */ }, { /* 13053 */ 879, /* VPSRAQZrik */ }, { /* 13054 */ 880, /* VPSRAQZrikz */ }, { /* 13055 */ 911, /* VPSRAQZrm */ }, { /* 13056 */ 201, /* VPSRAQZrmk */ }, { /* 13057 */ 912, /* VPSRAQZrmkz */ }, { /* 13058 */ 913, /* VPSRAQZrr */ }, { /* 13059 */ 914, /* VPSRAQZrrk */ }, { /* 13060 */ 915, /* VPSRAQZrrkz */ }, { /* 13061 */ 204, /* VPSRAVDYrm */ }, { /* 13062 */ 205, /* VPSRAVDYrr */ }, { /* 13063 */ 206, /* VPSRAVDZ128rm */ }, { /* 13064 */ 237, /* VPSRAVDZ128rmb */ }, { /* 13065 */ 238, /* VPSRAVDZ128rmbk */ }, { /* 13066 */ 239, /* VPSRAVDZ128rmbkz */ }, { /* 13067 */ 203, /* VPSRAVDZ128rmk */ }, { /* 13068 */ 210, /* VPSRAVDZ128rmkz */ }, { /* 13069 */ 211, /* VPSRAVDZ128rr */ }, { /* 13070 */ 212, /* VPSRAVDZ128rrk */ }, { /* 13071 */ 213, /* VPSRAVDZ128rrkz */ }, { /* 13072 */ 214, /* VPSRAVDZ256rm */ }, { /* 13073 */ 240, /* VPSRAVDZ256rmb */ }, { /* 13074 */ 241, /* VPSRAVDZ256rmbk */ }, { /* 13075 */ 242, /* VPSRAVDZ256rmbkz */ }, { /* 13076 */ 218, /* VPSRAVDZ256rmk */ }, { /* 13077 */ 219, /* VPSRAVDZ256rmkz */ }, { /* 13078 */ 220, /* VPSRAVDZ256rr */ }, { /* 13079 */ 221, /* VPSRAVDZ256rrk */ }, { /* 13080 */ 222, /* VPSRAVDZ256rrkz */ }, { /* 13081 */ 223, /* VPSRAVDZrm */ }, { /* 13082 */ 243, /* VPSRAVDZrmb */ }, { /* 13083 */ 244, /* VPSRAVDZrmbk */ }, { /* 13084 */ 245, /* VPSRAVDZrmbkz */ }, { /* 13085 */ 227, /* VPSRAVDZrmk */ }, { /* 13086 */ 228, /* VPSRAVDZrmkz */ }, { /* 13087 */ 229, /* VPSRAVDZrr */ }, { /* 13088 */ 233, /* VPSRAVDZrrk */ }, { /* 13089 */ 234, /* VPSRAVDZrrkz */ }, { /* 13090 */ 235, /* VPSRAVDrm */ }, { /* 13091 */ 236, /* VPSRAVDrr */ }, { /* 13092 */ 206, /* VPSRAVQZ128rm */ }, { /* 13093 */ 207, /* VPSRAVQZ128rmb */ }, { /* 13094 */ 208, /* VPSRAVQZ128rmbk */ }, { /* 13095 */ 209, /* VPSRAVQZ128rmbkz */ }, { /* 13096 */ 203, /* VPSRAVQZ128rmk */ }, { /* 13097 */ 210, /* VPSRAVQZ128rmkz */ }, { /* 13098 */ 211, /* VPSRAVQZ128rr */ }, { /* 13099 */ 212, /* VPSRAVQZ128rrk */ }, { /* 13100 */ 213, /* VPSRAVQZ128rrkz */ }, { /* 13101 */ 214, /* VPSRAVQZ256rm */ }, { /* 13102 */ 215, /* VPSRAVQZ256rmb */ }, { /* 13103 */ 216, /* VPSRAVQZ256rmbk */ }, { /* 13104 */ 217, /* VPSRAVQZ256rmbkz */ }, { /* 13105 */ 218, /* VPSRAVQZ256rmk */ }, { /* 13106 */ 219, /* VPSRAVQZ256rmkz */ }, { /* 13107 */ 220, /* VPSRAVQZ256rr */ }, { /* 13108 */ 221, /* VPSRAVQZ256rrk */ }, { /* 13109 */ 222, /* VPSRAVQZ256rrkz */ }, { /* 13110 */ 223, /* VPSRAVQZrm */ }, { /* 13111 */ 224, /* VPSRAVQZrmb */ }, { /* 13112 */ 225, /* VPSRAVQZrmbk */ }, { /* 13113 */ 226, /* VPSRAVQZrmbkz */ }, { /* 13114 */ 227, /* VPSRAVQZrmk */ }, { /* 13115 */ 228, /* VPSRAVQZrmkz */ }, { /* 13116 */ 229, /* VPSRAVQZrr */ }, { /* 13117 */ 233, /* VPSRAVQZrrk */ }, { /* 13118 */ 234, /* VPSRAVQZrrkz */ }, { /* 13119 */ 206, /* VPSRAVWZ128rm */ }, { /* 13120 */ 203, /* VPSRAVWZ128rmk */ }, { /* 13121 */ 210, /* VPSRAVWZ128rmkz */ }, { /* 13122 */ 211, /* VPSRAVWZ128rr */ }, { /* 13123 */ 212, /* VPSRAVWZ128rrk */ }, { /* 13124 */ 213, /* VPSRAVWZ128rrkz */ }, { /* 13125 */ 214, /* VPSRAVWZ256rm */ }, { /* 13126 */ 218, /* VPSRAVWZ256rmk */ }, { /* 13127 */ 219, /* VPSRAVWZ256rmkz */ }, { /* 13128 */ 220, /* VPSRAVWZ256rr */ }, { /* 13129 */ 221, /* VPSRAVWZ256rrk */ }, { /* 13130 */ 222, /* VPSRAVWZ256rrkz */ }, { /* 13131 */ 223, /* VPSRAVWZrm */ }, { /* 13132 */ 227, /* VPSRAVWZrmk */ }, { /* 13133 */ 228, /* VPSRAVWZrmkz */ }, { /* 13134 */ 229, /* VPSRAVWZrr */ }, { /* 13135 */ 233, /* VPSRAVWZrrk */ }, { /* 13136 */ 234, /* VPSRAVWZrrkz */ }, { /* 13137 */ 902, /* VPSRAWYri */ }, { /* 13138 */ 204, /* VPSRAWYrm */ }, { /* 13139 */ 904, /* VPSRAWYrr */ }, { /* 13140 */ 857, /* VPSRAWZ128mi */ }, { /* 13141 */ 858, /* VPSRAWZ128mik */ }, { /* 13142 */ 859, /* VPSRAWZ128mikz */ }, { /* 13143 */ 860, /* VPSRAWZ128ri */ }, { /* 13144 */ 861, /* VPSRAWZ128rik */ }, { /* 13145 */ 862, /* VPSRAWZ128rikz */ }, { /* 13146 */ 206, /* VPSRAWZ128rm */ }, { /* 13147 */ 203, /* VPSRAWZ128rmk */ }, { /* 13148 */ 210, /* VPSRAWZ128rmkz */ }, { /* 13149 */ 211, /* VPSRAWZ128rr */ }, { /* 13150 */ 212, /* VPSRAWZ128rrk */ }, { /* 13151 */ 213, /* VPSRAWZ128rrkz */ }, { /* 13152 */ 866, /* VPSRAWZ256mi */ }, { /* 13153 */ 867, /* VPSRAWZ256mik */ }, { /* 13154 */ 868, /* VPSRAWZ256mikz */ }, { /* 13155 */ 869, /* VPSRAWZ256ri */ }, { /* 13156 */ 870, /* VPSRAWZ256rik */ }, { /* 13157 */ 871, /* VPSRAWZ256rikz */ }, { /* 13158 */ 905, /* VPSRAWZ256rm */ }, { /* 13159 */ 906, /* VPSRAWZ256rmk */ }, { /* 13160 */ 907, /* VPSRAWZ256rmkz */ }, { /* 13161 */ 908, /* VPSRAWZ256rr */ }, { /* 13162 */ 909, /* VPSRAWZ256rrk */ }, { /* 13163 */ 910, /* VPSRAWZ256rrkz */ }, { /* 13164 */ 875, /* VPSRAWZmi */ }, { /* 13165 */ 876, /* VPSRAWZmik */ }, { /* 13166 */ 877, /* VPSRAWZmikz */ }, { /* 13167 */ 878, /* VPSRAWZri */ }, { /* 13168 */ 879, /* VPSRAWZrik */ }, { /* 13169 */ 880, /* VPSRAWZrikz */ }, { /* 13170 */ 911, /* VPSRAWZrm */ }, { /* 13171 */ 201, /* VPSRAWZrmk */ }, { /* 13172 */ 912, /* VPSRAWZrmkz */ }, { /* 13173 */ 913, /* VPSRAWZrr */ }, { /* 13174 */ 914, /* VPSRAWZrrk */ }, { /* 13175 */ 915, /* VPSRAWZrrkz */ }, { /* 13176 */ 903, /* VPSRAWri */ }, { /* 13177 */ 235, /* VPSRAWrm */ }, { /* 13178 */ 236, /* VPSRAWrr */ }, { /* 13179 */ 902, /* VPSRLDQYri */ }, { /* 13180 */ 857, /* VPSRLDQZ128rm */ }, { /* 13181 */ 860, /* VPSRLDQZ128rr */ }, { /* 13182 */ 866, /* VPSRLDQZ256rm */ }, { /* 13183 */ 869, /* VPSRLDQZ256rr */ }, { /* 13184 */ 875, /* VPSRLDQZrm */ }, { /* 13185 */ 878, /* VPSRLDQZrr */ }, { /* 13186 */ 903, /* VPSRLDQri */ }, { /* 13187 */ 902, /* VPSRLDYri */ }, { /* 13188 */ 204, /* VPSRLDYrm */ }, { /* 13189 */ 904, /* VPSRLDYrr */ }, { /* 13190 */ 854, /* VPSRLDZ128mbi */ }, { /* 13191 */ 855, /* VPSRLDZ128mbik */ }, { /* 13192 */ 856, /* VPSRLDZ128mbikz */ }, { /* 13193 */ 857, /* VPSRLDZ128mi */ }, { /* 13194 */ 858, /* VPSRLDZ128mik */ }, { /* 13195 */ 859, /* VPSRLDZ128mikz */ }, { /* 13196 */ 860, /* VPSRLDZ128ri */ }, { /* 13197 */ 861, /* VPSRLDZ128rik */ }, { /* 13198 */ 862, /* VPSRLDZ128rikz */ }, { /* 13199 */ 206, /* VPSRLDZ128rm */ }, { /* 13200 */ 203, /* VPSRLDZ128rmk */ }, { /* 13201 */ 210, /* VPSRLDZ128rmkz */ }, { /* 13202 */ 211, /* VPSRLDZ128rr */ }, { /* 13203 */ 212, /* VPSRLDZ128rrk */ }, { /* 13204 */ 213, /* VPSRLDZ128rrkz */ }, { /* 13205 */ 863, /* VPSRLDZ256mbi */ }, { /* 13206 */ 864, /* VPSRLDZ256mbik */ }, { /* 13207 */ 865, /* VPSRLDZ256mbikz */ }, { /* 13208 */ 866, /* VPSRLDZ256mi */ }, { /* 13209 */ 867, /* VPSRLDZ256mik */ }, { /* 13210 */ 868, /* VPSRLDZ256mikz */ }, { /* 13211 */ 869, /* VPSRLDZ256ri */ }, { /* 13212 */ 870, /* VPSRLDZ256rik */ }, { /* 13213 */ 871, /* VPSRLDZ256rikz */ }, { /* 13214 */ 905, /* VPSRLDZ256rm */ }, { /* 13215 */ 906, /* VPSRLDZ256rmk */ }, { /* 13216 */ 907, /* VPSRLDZ256rmkz */ }, { /* 13217 */ 908, /* VPSRLDZ256rr */ }, { /* 13218 */ 909, /* VPSRLDZ256rrk */ }, { /* 13219 */ 910, /* VPSRLDZ256rrkz */ }, { /* 13220 */ 872, /* VPSRLDZmbi */ }, { /* 13221 */ 873, /* VPSRLDZmbik */ }, { /* 13222 */ 874, /* VPSRLDZmbikz */ }, { /* 13223 */ 875, /* VPSRLDZmi */ }, { /* 13224 */ 876, /* VPSRLDZmik */ }, { /* 13225 */ 877, /* VPSRLDZmikz */ }, { /* 13226 */ 878, /* VPSRLDZri */ }, { /* 13227 */ 879, /* VPSRLDZrik */ }, { /* 13228 */ 880, /* VPSRLDZrikz */ }, { /* 13229 */ 911, /* VPSRLDZrm */ }, { /* 13230 */ 201, /* VPSRLDZrmk */ }, { /* 13231 */ 912, /* VPSRLDZrmkz */ }, { /* 13232 */ 913, /* VPSRLDZrr */ }, { /* 13233 */ 914, /* VPSRLDZrrk */ }, { /* 13234 */ 915, /* VPSRLDZrrkz */ }, { /* 13235 */ 903, /* VPSRLDri */ }, { /* 13236 */ 235, /* VPSRLDrm */ }, { /* 13237 */ 236, /* VPSRLDrr */ }, { /* 13238 */ 902, /* VPSRLQYri */ }, { /* 13239 */ 204, /* VPSRLQYrm */ }, { /* 13240 */ 904, /* VPSRLQYrr */ }, { /* 13241 */ 881, /* VPSRLQZ128mbi */ }, { /* 13242 */ 882, /* VPSRLQZ128mbik */ }, { /* 13243 */ 883, /* VPSRLQZ128mbikz */ }, { /* 13244 */ 857, /* VPSRLQZ128mi */ }, { /* 13245 */ 858, /* VPSRLQZ128mik */ }, { /* 13246 */ 859, /* VPSRLQZ128mikz */ }, { /* 13247 */ 860, /* VPSRLQZ128ri */ }, { /* 13248 */ 861, /* VPSRLQZ128rik */ }, { /* 13249 */ 862, /* VPSRLQZ128rikz */ }, { /* 13250 */ 206, /* VPSRLQZ128rm */ }, { /* 13251 */ 203, /* VPSRLQZ128rmk */ }, { /* 13252 */ 210, /* VPSRLQZ128rmkz */ }, { /* 13253 */ 211, /* VPSRLQZ128rr */ }, { /* 13254 */ 212, /* VPSRLQZ128rrk */ }, { /* 13255 */ 213, /* VPSRLQZ128rrkz */ }, { /* 13256 */ 884, /* VPSRLQZ256mbi */ }, { /* 13257 */ 885, /* VPSRLQZ256mbik */ }, { /* 13258 */ 886, /* VPSRLQZ256mbikz */ }, { /* 13259 */ 866, /* VPSRLQZ256mi */ }, { /* 13260 */ 867, /* VPSRLQZ256mik */ }, { /* 13261 */ 868, /* VPSRLQZ256mikz */ }, { /* 13262 */ 869, /* VPSRLQZ256ri */ }, { /* 13263 */ 870, /* VPSRLQZ256rik */ }, { /* 13264 */ 871, /* VPSRLQZ256rikz */ }, { /* 13265 */ 905, /* VPSRLQZ256rm */ }, { /* 13266 */ 906, /* VPSRLQZ256rmk */ }, { /* 13267 */ 907, /* VPSRLQZ256rmkz */ }, { /* 13268 */ 908, /* VPSRLQZ256rr */ }, { /* 13269 */ 909, /* VPSRLQZ256rrk */ }, { /* 13270 */ 910, /* VPSRLQZ256rrkz */ }, { /* 13271 */ 887, /* VPSRLQZmbi */ }, { /* 13272 */ 888, /* VPSRLQZmbik */ }, { /* 13273 */ 889, /* VPSRLQZmbikz */ }, { /* 13274 */ 875, /* VPSRLQZmi */ }, { /* 13275 */ 876, /* VPSRLQZmik */ }, { /* 13276 */ 877, /* VPSRLQZmikz */ }, { /* 13277 */ 878, /* VPSRLQZri */ }, { /* 13278 */ 879, /* VPSRLQZrik */ }, { /* 13279 */ 880, /* VPSRLQZrikz */ }, { /* 13280 */ 911, /* VPSRLQZrm */ }, { /* 13281 */ 201, /* VPSRLQZrmk */ }, { /* 13282 */ 912, /* VPSRLQZrmkz */ }, { /* 13283 */ 913, /* VPSRLQZrr */ }, { /* 13284 */ 914, /* VPSRLQZrrk */ }, { /* 13285 */ 915, /* VPSRLQZrrkz */ }, { /* 13286 */ 903, /* VPSRLQri */ }, { /* 13287 */ 235, /* VPSRLQrm */ }, { /* 13288 */ 236, /* VPSRLQrr */ }, { /* 13289 */ 204, /* VPSRLVDYrm */ }, { /* 13290 */ 205, /* VPSRLVDYrr */ }, { /* 13291 */ 206, /* VPSRLVDZ128rm */ }, { /* 13292 */ 237, /* VPSRLVDZ128rmb */ }, { /* 13293 */ 238, /* VPSRLVDZ128rmbk */ }, { /* 13294 */ 239, /* VPSRLVDZ128rmbkz */ }, { /* 13295 */ 203, /* VPSRLVDZ128rmk */ }, { /* 13296 */ 210, /* VPSRLVDZ128rmkz */ }, { /* 13297 */ 211, /* VPSRLVDZ128rr */ }, { /* 13298 */ 212, /* VPSRLVDZ128rrk */ }, { /* 13299 */ 213, /* VPSRLVDZ128rrkz */ }, { /* 13300 */ 214, /* VPSRLVDZ256rm */ }, { /* 13301 */ 240, /* VPSRLVDZ256rmb */ }, { /* 13302 */ 241, /* VPSRLVDZ256rmbk */ }, { /* 13303 */ 242, /* VPSRLVDZ256rmbkz */ }, { /* 13304 */ 218, /* VPSRLVDZ256rmk */ }, { /* 13305 */ 219, /* VPSRLVDZ256rmkz */ }, { /* 13306 */ 220, /* VPSRLVDZ256rr */ }, { /* 13307 */ 221, /* VPSRLVDZ256rrk */ }, { /* 13308 */ 222, /* VPSRLVDZ256rrkz */ }, { /* 13309 */ 223, /* VPSRLVDZrm */ }, { /* 13310 */ 243, /* VPSRLVDZrmb */ }, { /* 13311 */ 244, /* VPSRLVDZrmbk */ }, { /* 13312 */ 245, /* VPSRLVDZrmbkz */ }, { /* 13313 */ 227, /* VPSRLVDZrmk */ }, { /* 13314 */ 228, /* VPSRLVDZrmkz */ }, { /* 13315 */ 229, /* VPSRLVDZrr */ }, { /* 13316 */ 233, /* VPSRLVDZrrk */ }, { /* 13317 */ 234, /* VPSRLVDZrrkz */ }, { /* 13318 */ 235, /* VPSRLVDrm */ }, { /* 13319 */ 236, /* VPSRLVDrr */ }, { /* 13320 */ 204, /* VPSRLVQYrm */ }, { /* 13321 */ 205, /* VPSRLVQYrr */ }, { /* 13322 */ 206, /* VPSRLVQZ128rm */ }, { /* 13323 */ 207, /* VPSRLVQZ128rmb */ }, { /* 13324 */ 208, /* VPSRLVQZ128rmbk */ }, { /* 13325 */ 209, /* VPSRLVQZ128rmbkz */ }, { /* 13326 */ 203, /* VPSRLVQZ128rmk */ }, { /* 13327 */ 210, /* VPSRLVQZ128rmkz */ }, { /* 13328 */ 211, /* VPSRLVQZ128rr */ }, { /* 13329 */ 212, /* VPSRLVQZ128rrk */ }, { /* 13330 */ 213, /* VPSRLVQZ128rrkz */ }, { /* 13331 */ 214, /* VPSRLVQZ256rm */ }, { /* 13332 */ 215, /* VPSRLVQZ256rmb */ }, { /* 13333 */ 216, /* VPSRLVQZ256rmbk */ }, { /* 13334 */ 217, /* VPSRLVQZ256rmbkz */ }, { /* 13335 */ 218, /* VPSRLVQZ256rmk */ }, { /* 13336 */ 219, /* VPSRLVQZ256rmkz */ }, { /* 13337 */ 220, /* VPSRLVQZ256rr */ }, { /* 13338 */ 221, /* VPSRLVQZ256rrk */ }, { /* 13339 */ 222, /* VPSRLVQZ256rrkz */ }, { /* 13340 */ 223, /* VPSRLVQZrm */ }, { /* 13341 */ 224, /* VPSRLVQZrmb */ }, { /* 13342 */ 225, /* VPSRLVQZrmbk */ }, { /* 13343 */ 226, /* VPSRLVQZrmbkz */ }, { /* 13344 */ 227, /* VPSRLVQZrmk */ }, { /* 13345 */ 228, /* VPSRLVQZrmkz */ }, { /* 13346 */ 229, /* VPSRLVQZrr */ }, { /* 13347 */ 233, /* VPSRLVQZrrk */ }, { /* 13348 */ 234, /* VPSRLVQZrrkz */ }, { /* 13349 */ 235, /* VPSRLVQrm */ }, { /* 13350 */ 236, /* VPSRLVQrr */ }, { /* 13351 */ 206, /* VPSRLVWZ128rm */ }, { /* 13352 */ 203, /* VPSRLVWZ128rmk */ }, { /* 13353 */ 210, /* VPSRLVWZ128rmkz */ }, { /* 13354 */ 211, /* VPSRLVWZ128rr */ }, { /* 13355 */ 212, /* VPSRLVWZ128rrk */ }, { /* 13356 */ 213, /* VPSRLVWZ128rrkz */ }, { /* 13357 */ 214, /* VPSRLVWZ256rm */ }, { /* 13358 */ 218, /* VPSRLVWZ256rmk */ }, { /* 13359 */ 219, /* VPSRLVWZ256rmkz */ }, { /* 13360 */ 220, /* VPSRLVWZ256rr */ }, { /* 13361 */ 221, /* VPSRLVWZ256rrk */ }, { /* 13362 */ 222, /* VPSRLVWZ256rrkz */ }, { /* 13363 */ 223, /* VPSRLVWZrm */ }, { /* 13364 */ 227, /* VPSRLVWZrmk */ }, { /* 13365 */ 228, /* VPSRLVWZrmkz */ }, { /* 13366 */ 229, /* VPSRLVWZrr */ }, { /* 13367 */ 233, /* VPSRLVWZrrk */ }, { /* 13368 */ 234, /* VPSRLVWZrrkz */ }, { /* 13369 */ 902, /* VPSRLWYri */ }, { /* 13370 */ 204, /* VPSRLWYrm */ }, { /* 13371 */ 904, /* VPSRLWYrr */ }, { /* 13372 */ 857, /* VPSRLWZ128mi */ }, { /* 13373 */ 858, /* VPSRLWZ128mik */ }, { /* 13374 */ 859, /* VPSRLWZ128mikz */ }, { /* 13375 */ 860, /* VPSRLWZ128ri */ }, { /* 13376 */ 861, /* VPSRLWZ128rik */ }, { /* 13377 */ 862, /* VPSRLWZ128rikz */ }, { /* 13378 */ 206, /* VPSRLWZ128rm */ }, { /* 13379 */ 203, /* VPSRLWZ128rmk */ }, { /* 13380 */ 210, /* VPSRLWZ128rmkz */ }, { /* 13381 */ 211, /* VPSRLWZ128rr */ }, { /* 13382 */ 212, /* VPSRLWZ128rrk */ }, { /* 13383 */ 213, /* VPSRLWZ128rrkz */ }, { /* 13384 */ 866, /* VPSRLWZ256mi */ }, { /* 13385 */ 867, /* VPSRLWZ256mik */ }, { /* 13386 */ 868, /* VPSRLWZ256mikz */ }, { /* 13387 */ 869, /* VPSRLWZ256ri */ }, { /* 13388 */ 870, /* VPSRLWZ256rik */ }, { /* 13389 */ 871, /* VPSRLWZ256rikz */ }, { /* 13390 */ 905, /* VPSRLWZ256rm */ }, { /* 13391 */ 906, /* VPSRLWZ256rmk */ }, { /* 13392 */ 907, /* VPSRLWZ256rmkz */ }, { /* 13393 */ 908, /* VPSRLWZ256rr */ }, { /* 13394 */ 909, /* VPSRLWZ256rrk */ }, { /* 13395 */ 910, /* VPSRLWZ256rrkz */ }, { /* 13396 */ 875, /* VPSRLWZmi */ }, { /* 13397 */ 876, /* VPSRLWZmik */ }, { /* 13398 */ 877, /* VPSRLWZmikz */ }, { /* 13399 */ 878, /* VPSRLWZri */ }, { /* 13400 */ 879, /* VPSRLWZrik */ }, { /* 13401 */ 880, /* VPSRLWZrikz */ }, { /* 13402 */ 911, /* VPSRLWZrm */ }, { /* 13403 */ 201, /* VPSRLWZrmk */ }, { /* 13404 */ 912, /* VPSRLWZrmkz */ }, { /* 13405 */ 913, /* VPSRLWZrr */ }, { /* 13406 */ 914, /* VPSRLWZrrk */ }, { /* 13407 */ 915, /* VPSRLWZrrkz */ }, { /* 13408 */ 903, /* VPSRLWri */ }, { /* 13409 */ 235, /* VPSRLWrm */ }, { /* 13410 */ 236, /* VPSRLWrr */ }, { /* 13411 */ 204, /* VPSUBBYrm */ }, { /* 13412 */ 205, /* VPSUBBYrr */ }, { /* 13413 */ 206, /* VPSUBBZ128rm */ }, { /* 13414 */ 203, /* VPSUBBZ128rmk */ }, { /* 13415 */ 210, /* VPSUBBZ128rmkz */ }, { /* 13416 */ 211, /* VPSUBBZ128rr */ }, { /* 13417 */ 212, /* VPSUBBZ128rrk */ }, { /* 13418 */ 213, /* VPSUBBZ128rrkz */ }, { /* 13419 */ 214, /* VPSUBBZ256rm */ }, { /* 13420 */ 218, /* VPSUBBZ256rmk */ }, { /* 13421 */ 219, /* VPSUBBZ256rmkz */ }, { /* 13422 */ 220, /* VPSUBBZ256rr */ }, { /* 13423 */ 221, /* VPSUBBZ256rrk */ }, { /* 13424 */ 222, /* VPSUBBZ256rrkz */ }, { /* 13425 */ 223, /* VPSUBBZrm */ }, { /* 13426 */ 227, /* VPSUBBZrmk */ }, { /* 13427 */ 228, /* VPSUBBZrmkz */ }, { /* 13428 */ 229, /* VPSUBBZrr */ }, { /* 13429 */ 233, /* VPSUBBZrrk */ }, { /* 13430 */ 234, /* VPSUBBZrrkz */ }, { /* 13431 */ 235, /* VPSUBBrm */ }, { /* 13432 */ 236, /* VPSUBBrr */ }, { /* 13433 */ 204, /* VPSUBDYrm */ }, { /* 13434 */ 205, /* VPSUBDYrr */ }, { /* 13435 */ 206, /* VPSUBDZ128rm */ }, { /* 13436 */ 237, /* VPSUBDZ128rmb */ }, { /* 13437 */ 238, /* VPSUBDZ128rmbk */ }, { /* 13438 */ 239, /* VPSUBDZ128rmbkz */ }, { /* 13439 */ 203, /* VPSUBDZ128rmk */ }, { /* 13440 */ 210, /* VPSUBDZ128rmkz */ }, { /* 13441 */ 211, /* VPSUBDZ128rr */ }, { /* 13442 */ 212, /* VPSUBDZ128rrk */ }, { /* 13443 */ 213, /* VPSUBDZ128rrkz */ }, { /* 13444 */ 214, /* VPSUBDZ256rm */ }, { /* 13445 */ 240, /* VPSUBDZ256rmb */ }, { /* 13446 */ 241, /* VPSUBDZ256rmbk */ }, { /* 13447 */ 242, /* VPSUBDZ256rmbkz */ }, { /* 13448 */ 218, /* VPSUBDZ256rmk */ }, { /* 13449 */ 219, /* VPSUBDZ256rmkz */ }, { /* 13450 */ 220, /* VPSUBDZ256rr */ }, { /* 13451 */ 221, /* VPSUBDZ256rrk */ }, { /* 13452 */ 222, /* VPSUBDZ256rrkz */ }, { /* 13453 */ 223, /* VPSUBDZrm */ }, { /* 13454 */ 243, /* VPSUBDZrmb */ }, { /* 13455 */ 244, /* VPSUBDZrmbk */ }, { /* 13456 */ 245, /* VPSUBDZrmbkz */ }, { /* 13457 */ 227, /* VPSUBDZrmk */ }, { /* 13458 */ 228, /* VPSUBDZrmkz */ }, { /* 13459 */ 229, /* VPSUBDZrr */ }, { /* 13460 */ 233, /* VPSUBDZrrk */ }, { /* 13461 */ 234, /* VPSUBDZrrkz */ }, { /* 13462 */ 235, /* VPSUBDrm */ }, { /* 13463 */ 236, /* VPSUBDrr */ }, { /* 13464 */ 204, /* VPSUBQYrm */ }, { /* 13465 */ 205, /* VPSUBQYrr */ }, { /* 13466 */ 206, /* VPSUBQZ128rm */ }, { /* 13467 */ 207, /* VPSUBQZ128rmb */ }, { /* 13468 */ 208, /* VPSUBQZ128rmbk */ }, { /* 13469 */ 209, /* VPSUBQZ128rmbkz */ }, { /* 13470 */ 203, /* VPSUBQZ128rmk */ }, { /* 13471 */ 210, /* VPSUBQZ128rmkz */ }, { /* 13472 */ 211, /* VPSUBQZ128rr */ }, { /* 13473 */ 212, /* VPSUBQZ128rrk */ }, { /* 13474 */ 213, /* VPSUBQZ128rrkz */ }, { /* 13475 */ 214, /* VPSUBQZ256rm */ }, { /* 13476 */ 215, /* VPSUBQZ256rmb */ }, { /* 13477 */ 216, /* VPSUBQZ256rmbk */ }, { /* 13478 */ 217, /* VPSUBQZ256rmbkz */ }, { /* 13479 */ 218, /* VPSUBQZ256rmk */ }, { /* 13480 */ 219, /* VPSUBQZ256rmkz */ }, { /* 13481 */ 220, /* VPSUBQZ256rr */ }, { /* 13482 */ 221, /* VPSUBQZ256rrk */ }, { /* 13483 */ 222, /* VPSUBQZ256rrkz */ }, { /* 13484 */ 223, /* VPSUBQZrm */ }, { /* 13485 */ 224, /* VPSUBQZrmb */ }, { /* 13486 */ 225, /* VPSUBQZrmbk */ }, { /* 13487 */ 226, /* VPSUBQZrmbkz */ }, { /* 13488 */ 227, /* VPSUBQZrmk */ }, { /* 13489 */ 228, /* VPSUBQZrmkz */ }, { /* 13490 */ 229, /* VPSUBQZrr */ }, { /* 13491 */ 233, /* VPSUBQZrrk */ }, { /* 13492 */ 234, /* VPSUBQZrrkz */ }, { /* 13493 */ 235, /* VPSUBQrm */ }, { /* 13494 */ 236, /* VPSUBQrr */ }, { /* 13495 */ 204, /* VPSUBSBYrm */ }, { /* 13496 */ 205, /* VPSUBSBYrr */ }, { /* 13497 */ 206, /* VPSUBSBZ128rm */ }, { /* 13498 */ 203, /* VPSUBSBZ128rmk */ }, { /* 13499 */ 210, /* VPSUBSBZ128rmkz */ }, { /* 13500 */ 211, /* VPSUBSBZ128rr */ }, { /* 13501 */ 212, /* VPSUBSBZ128rrk */ }, { /* 13502 */ 213, /* VPSUBSBZ128rrkz */ }, { /* 13503 */ 214, /* VPSUBSBZ256rm */ }, { /* 13504 */ 218, /* VPSUBSBZ256rmk */ }, { /* 13505 */ 219, /* VPSUBSBZ256rmkz */ }, { /* 13506 */ 220, /* VPSUBSBZ256rr */ }, { /* 13507 */ 221, /* VPSUBSBZ256rrk */ }, { /* 13508 */ 222, /* VPSUBSBZ256rrkz */ }, { /* 13509 */ 223, /* VPSUBSBZrm */ }, { /* 13510 */ 227, /* VPSUBSBZrmk */ }, { /* 13511 */ 228, /* VPSUBSBZrmkz */ }, { /* 13512 */ 229, /* VPSUBSBZrr */ }, { /* 13513 */ 233, /* VPSUBSBZrrk */ }, { /* 13514 */ 234, /* VPSUBSBZrrkz */ }, { /* 13515 */ 235, /* VPSUBSBrm */ }, { /* 13516 */ 236, /* VPSUBSBrr */ }, { /* 13517 */ 204, /* VPSUBSWYrm */ }, { /* 13518 */ 205, /* VPSUBSWYrr */ }, { /* 13519 */ 206, /* VPSUBSWZ128rm */ }, { /* 13520 */ 203, /* VPSUBSWZ128rmk */ }, { /* 13521 */ 210, /* VPSUBSWZ128rmkz */ }, { /* 13522 */ 211, /* VPSUBSWZ128rr */ }, { /* 13523 */ 212, /* VPSUBSWZ128rrk */ }, { /* 13524 */ 213, /* VPSUBSWZ128rrkz */ }, { /* 13525 */ 214, /* VPSUBSWZ256rm */ }, { /* 13526 */ 218, /* VPSUBSWZ256rmk */ }, { /* 13527 */ 219, /* VPSUBSWZ256rmkz */ }, { /* 13528 */ 220, /* VPSUBSWZ256rr */ }, { /* 13529 */ 221, /* VPSUBSWZ256rrk */ }, { /* 13530 */ 222, /* VPSUBSWZ256rrkz */ }, { /* 13531 */ 223, /* VPSUBSWZrm */ }, { /* 13532 */ 227, /* VPSUBSWZrmk */ }, { /* 13533 */ 228, /* VPSUBSWZrmkz */ }, { /* 13534 */ 229, /* VPSUBSWZrr */ }, { /* 13535 */ 233, /* VPSUBSWZrrk */ }, { /* 13536 */ 234, /* VPSUBSWZrrkz */ }, { /* 13537 */ 235, /* VPSUBSWrm */ }, { /* 13538 */ 236, /* VPSUBSWrr */ }, { /* 13539 */ 204, /* VPSUBUSBYrm */ }, { /* 13540 */ 205, /* VPSUBUSBYrr */ }, { /* 13541 */ 206, /* VPSUBUSBZ128rm */ }, { /* 13542 */ 203, /* VPSUBUSBZ128rmk */ }, { /* 13543 */ 210, /* VPSUBUSBZ128rmkz */ }, { /* 13544 */ 211, /* VPSUBUSBZ128rr */ }, { /* 13545 */ 212, /* VPSUBUSBZ128rrk */ }, { /* 13546 */ 213, /* VPSUBUSBZ128rrkz */ }, { /* 13547 */ 214, /* VPSUBUSBZ256rm */ }, { /* 13548 */ 218, /* VPSUBUSBZ256rmk */ }, { /* 13549 */ 219, /* VPSUBUSBZ256rmkz */ }, { /* 13550 */ 220, /* VPSUBUSBZ256rr */ }, { /* 13551 */ 221, /* VPSUBUSBZ256rrk */ }, { /* 13552 */ 222, /* VPSUBUSBZ256rrkz */ }, { /* 13553 */ 223, /* VPSUBUSBZrm */ }, { /* 13554 */ 227, /* VPSUBUSBZrmk */ }, { /* 13555 */ 228, /* VPSUBUSBZrmkz */ }, { /* 13556 */ 229, /* VPSUBUSBZrr */ }, { /* 13557 */ 233, /* VPSUBUSBZrrk */ }, { /* 13558 */ 234, /* VPSUBUSBZrrkz */ }, { /* 13559 */ 235, /* VPSUBUSBrm */ }, { /* 13560 */ 236, /* VPSUBUSBrr */ }, { /* 13561 */ 204, /* VPSUBUSWYrm */ }, { /* 13562 */ 205, /* VPSUBUSWYrr */ }, { /* 13563 */ 206, /* VPSUBUSWZ128rm */ }, { /* 13564 */ 203, /* VPSUBUSWZ128rmk */ }, { /* 13565 */ 210, /* VPSUBUSWZ128rmkz */ }, { /* 13566 */ 211, /* VPSUBUSWZ128rr */ }, { /* 13567 */ 212, /* VPSUBUSWZ128rrk */ }, { /* 13568 */ 213, /* VPSUBUSWZ128rrkz */ }, { /* 13569 */ 214, /* VPSUBUSWZ256rm */ }, { /* 13570 */ 218, /* VPSUBUSWZ256rmk */ }, { /* 13571 */ 219, /* VPSUBUSWZ256rmkz */ }, { /* 13572 */ 220, /* VPSUBUSWZ256rr */ }, { /* 13573 */ 221, /* VPSUBUSWZ256rrk */ }, { /* 13574 */ 222, /* VPSUBUSWZ256rrkz */ }, { /* 13575 */ 223, /* VPSUBUSWZrm */ }, { /* 13576 */ 227, /* VPSUBUSWZrmk */ }, { /* 13577 */ 228, /* VPSUBUSWZrmkz */ }, { /* 13578 */ 229, /* VPSUBUSWZrr */ }, { /* 13579 */ 233, /* VPSUBUSWZrrk */ }, { /* 13580 */ 234, /* VPSUBUSWZrrkz */ }, { /* 13581 */ 235, /* VPSUBUSWrm */ }, { /* 13582 */ 236, /* VPSUBUSWrr */ }, { /* 13583 */ 204, /* VPSUBWYrm */ }, { /* 13584 */ 205, /* VPSUBWYrr */ }, { /* 13585 */ 206, /* VPSUBWZ128rm */ }, { /* 13586 */ 203, /* VPSUBWZ128rmk */ }, { /* 13587 */ 210, /* VPSUBWZ128rmkz */ }, { /* 13588 */ 211, /* VPSUBWZ128rr */ }, { /* 13589 */ 212, /* VPSUBWZ128rrk */ }, { /* 13590 */ 213, /* VPSUBWZ128rrkz */ }, { /* 13591 */ 214, /* VPSUBWZ256rm */ }, { /* 13592 */ 218, /* VPSUBWZ256rmk */ }, { /* 13593 */ 219, /* VPSUBWZ256rmkz */ }, { /* 13594 */ 220, /* VPSUBWZ256rr */ }, { /* 13595 */ 221, /* VPSUBWZ256rrk */ }, { /* 13596 */ 222, /* VPSUBWZ256rrkz */ }, { /* 13597 */ 223, /* VPSUBWZrm */ }, { /* 13598 */ 227, /* VPSUBWZrmk */ }, { /* 13599 */ 228, /* VPSUBWZrmkz */ }, { /* 13600 */ 229, /* VPSUBWZrr */ }, { /* 13601 */ 233, /* VPSUBWZrrk */ }, { /* 13602 */ 234, /* VPSUBWZrrkz */ }, { /* 13603 */ 235, /* VPSUBWrm */ }, { /* 13604 */ 236, /* VPSUBWrr */ }, { /* 13605 */ 518, /* VPTERNLOGDZ128rmbi */ }, { /* 13606 */ 262, /* VPTERNLOGDZ128rmbik */ }, { /* 13607 */ 262, /* VPTERNLOGDZ128rmbikz */ }, { /* 13608 */ 508, /* VPTERNLOGDZ128rmi */ }, { /* 13609 */ 265, /* VPTERNLOGDZ128rmik */ }, { /* 13610 */ 265, /* VPTERNLOGDZ128rmikz */ }, { /* 13611 */ 509, /* VPTERNLOGDZ128rri */ }, { /* 13612 */ 268, /* VPTERNLOGDZ128rrik */ }, { /* 13613 */ 268, /* VPTERNLOGDZ128rrikz */ }, { /* 13614 */ 519, /* VPTERNLOGDZ256rmbi */ }, { /* 13615 */ 271, /* VPTERNLOGDZ256rmbik */ }, { /* 13616 */ 271, /* VPTERNLOGDZ256rmbikz */ }, { /* 13617 */ 511, /* VPTERNLOGDZ256rmi */ }, { /* 13618 */ 274, /* VPTERNLOGDZ256rmik */ }, { /* 13619 */ 274, /* VPTERNLOGDZ256rmikz */ }, { /* 13620 */ 512, /* VPTERNLOGDZ256rri */ }, { /* 13621 */ 277, /* VPTERNLOGDZ256rrik */ }, { /* 13622 */ 277, /* VPTERNLOGDZ256rrikz */ }, { /* 13623 */ 520, /* VPTERNLOGDZrmbi */ }, { /* 13624 */ 280, /* VPTERNLOGDZrmbik */ }, { /* 13625 */ 280, /* VPTERNLOGDZrmbikz */ }, { /* 13626 */ 514, /* VPTERNLOGDZrmi */ }, { /* 13627 */ 283, /* VPTERNLOGDZrmik */ }, { /* 13628 */ 283, /* VPTERNLOGDZrmikz */ }, { /* 13629 */ 515, /* VPTERNLOGDZrri */ }, { /* 13630 */ 286, /* VPTERNLOGDZrrik */ }, { /* 13631 */ 286, /* VPTERNLOGDZrrikz */ }, { /* 13632 */ 507, /* VPTERNLOGQZ128rmbi */ }, { /* 13633 */ 289, /* VPTERNLOGQZ128rmbik */ }, { /* 13634 */ 289, /* VPTERNLOGQZ128rmbikz */ }, { /* 13635 */ 508, /* VPTERNLOGQZ128rmi */ }, { /* 13636 */ 265, /* VPTERNLOGQZ128rmik */ }, { /* 13637 */ 265, /* VPTERNLOGQZ128rmikz */ }, { /* 13638 */ 509, /* VPTERNLOGQZ128rri */ }, { /* 13639 */ 268, /* VPTERNLOGQZ128rrik */ }, { /* 13640 */ 268, /* VPTERNLOGQZ128rrikz */ }, { /* 13641 */ 510, /* VPTERNLOGQZ256rmbi */ }, { /* 13642 */ 292, /* VPTERNLOGQZ256rmbik */ }, { /* 13643 */ 292, /* VPTERNLOGQZ256rmbikz */ }, { /* 13644 */ 511, /* VPTERNLOGQZ256rmi */ }, { /* 13645 */ 274, /* VPTERNLOGQZ256rmik */ }, { /* 13646 */ 274, /* VPTERNLOGQZ256rmikz */ }, { /* 13647 */ 512, /* VPTERNLOGQZ256rri */ }, { /* 13648 */ 277, /* VPTERNLOGQZ256rrik */ }, { /* 13649 */ 277, /* VPTERNLOGQZ256rrikz */ }, { /* 13650 */ 513, /* VPTERNLOGQZrmbi */ }, { /* 13651 */ 295, /* VPTERNLOGQZrmbik */ }, { /* 13652 */ 295, /* VPTERNLOGQZrmbikz */ }, { /* 13653 */ 514, /* VPTERNLOGQZrmi */ }, { /* 13654 */ 283, /* VPTERNLOGQZrmik */ }, { /* 13655 */ 283, /* VPTERNLOGQZrmikz */ }, { /* 13656 */ 515, /* VPTERNLOGQZrri */ }, { /* 13657 */ 286, /* VPTERNLOGQZrrik */ }, { /* 13658 */ 286, /* VPTERNLOGQZrrikz */ }, { /* 13659 */ 741, /* VPTESTMBZ128rm */ }, { /* 13660 */ 742, /* VPTESTMBZ128rmk */ }, { /* 13661 */ 743, /* VPTESTMBZ128rr */ }, { /* 13662 */ 744, /* VPTESTMBZ128rrk */ }, { /* 13663 */ 745, /* VPTESTMBZ256rm */ }, { /* 13664 */ 746, /* VPTESTMBZ256rmk */ }, { /* 13665 */ 747, /* VPTESTMBZ256rr */ }, { /* 13666 */ 748, /* VPTESTMBZ256rrk */ }, { /* 13667 */ 749, /* VPTESTMBZrm */ }, { /* 13668 */ 750, /* VPTESTMBZrmk */ }, { /* 13669 */ 751, /* VPTESTMBZrr */ }, { /* 13670 */ 752, /* VPTESTMBZrrk */ }, { /* 13671 */ 741, /* VPTESTMDZ128rm */ }, { /* 13672 */ 753, /* VPTESTMDZ128rmb */ }, { /* 13673 */ 754, /* VPTESTMDZ128rmbk */ }, { /* 13674 */ 742, /* VPTESTMDZ128rmk */ }, { /* 13675 */ 743, /* VPTESTMDZ128rr */ }, { /* 13676 */ 744, /* VPTESTMDZ128rrk */ }, { /* 13677 */ 745, /* VPTESTMDZ256rm */ }, { /* 13678 */ 755, /* VPTESTMDZ256rmb */ }, { /* 13679 */ 756, /* VPTESTMDZ256rmbk */ }, { /* 13680 */ 746, /* VPTESTMDZ256rmk */ }, { /* 13681 */ 747, /* VPTESTMDZ256rr */ }, { /* 13682 */ 748, /* VPTESTMDZ256rrk */ }, { /* 13683 */ 749, /* VPTESTMDZrm */ }, { /* 13684 */ 757, /* VPTESTMDZrmb */ }, { /* 13685 */ 758, /* VPTESTMDZrmbk */ }, { /* 13686 */ 750, /* VPTESTMDZrmk */ }, { /* 13687 */ 751, /* VPTESTMDZrr */ }, { /* 13688 */ 752, /* VPTESTMDZrrk */ }, { /* 13689 */ 741, /* VPTESTMQZ128rm */ }, { /* 13690 */ 759, /* VPTESTMQZ128rmb */ }, { /* 13691 */ 760, /* VPTESTMQZ128rmbk */ }, { /* 13692 */ 742, /* VPTESTMQZ128rmk */ }, { /* 13693 */ 743, /* VPTESTMQZ128rr */ }, { /* 13694 */ 744, /* VPTESTMQZ128rrk */ }, { /* 13695 */ 745, /* VPTESTMQZ256rm */ }, { /* 13696 */ 761, /* VPTESTMQZ256rmb */ }, { /* 13697 */ 762, /* VPTESTMQZ256rmbk */ }, { /* 13698 */ 746, /* VPTESTMQZ256rmk */ }, { /* 13699 */ 747, /* VPTESTMQZ256rr */ }, { /* 13700 */ 748, /* VPTESTMQZ256rrk */ }, { /* 13701 */ 749, /* VPTESTMQZrm */ }, { /* 13702 */ 763, /* VPTESTMQZrmb */ }, { /* 13703 */ 764, /* VPTESTMQZrmbk */ }, { /* 13704 */ 750, /* VPTESTMQZrmk */ }, { /* 13705 */ 751, /* VPTESTMQZrr */ }, { /* 13706 */ 752, /* VPTESTMQZrrk */ }, { /* 13707 */ 741, /* VPTESTMWZ128rm */ }, { /* 13708 */ 742, /* VPTESTMWZ128rmk */ }, { /* 13709 */ 743, /* VPTESTMWZ128rr */ }, { /* 13710 */ 744, /* VPTESTMWZ128rrk */ }, { /* 13711 */ 745, /* VPTESTMWZ256rm */ }, { /* 13712 */ 746, /* VPTESTMWZ256rmk */ }, { /* 13713 */ 747, /* VPTESTMWZ256rr */ }, { /* 13714 */ 748, /* VPTESTMWZ256rrk */ }, { /* 13715 */ 749, /* VPTESTMWZrm */ }, { /* 13716 */ 750, /* VPTESTMWZrmk */ }, { /* 13717 */ 751, /* VPTESTMWZrr */ }, { /* 13718 */ 752, /* VPTESTMWZrrk */ }, { /* 13719 */ 741, /* VPTESTNMBZ128rm */ }, { /* 13720 */ 742, /* VPTESTNMBZ128rmk */ }, { /* 13721 */ 743, /* VPTESTNMBZ128rr */ }, { /* 13722 */ 744, /* VPTESTNMBZ128rrk */ }, { /* 13723 */ 745, /* VPTESTNMBZ256rm */ }, { /* 13724 */ 746, /* VPTESTNMBZ256rmk */ }, { /* 13725 */ 747, /* VPTESTNMBZ256rr */ }, { /* 13726 */ 748, /* VPTESTNMBZ256rrk */ }, { /* 13727 */ 749, /* VPTESTNMBZrm */ }, { /* 13728 */ 750, /* VPTESTNMBZrmk */ }, { /* 13729 */ 751, /* VPTESTNMBZrr */ }, { /* 13730 */ 752, /* VPTESTNMBZrrk */ }, { /* 13731 */ 741, /* VPTESTNMDZ128rm */ }, { /* 13732 */ 753, /* VPTESTNMDZ128rmb */ }, { /* 13733 */ 754, /* VPTESTNMDZ128rmbk */ }, { /* 13734 */ 742, /* VPTESTNMDZ128rmk */ }, { /* 13735 */ 743, /* VPTESTNMDZ128rr */ }, { /* 13736 */ 744, /* VPTESTNMDZ128rrk */ }, { /* 13737 */ 745, /* VPTESTNMDZ256rm */ }, { /* 13738 */ 755, /* VPTESTNMDZ256rmb */ }, { /* 13739 */ 756, /* VPTESTNMDZ256rmbk */ }, { /* 13740 */ 746, /* VPTESTNMDZ256rmk */ }, { /* 13741 */ 747, /* VPTESTNMDZ256rr */ }, { /* 13742 */ 748, /* VPTESTNMDZ256rrk */ }, { /* 13743 */ 749, /* VPTESTNMDZrm */ }, { /* 13744 */ 757, /* VPTESTNMDZrmb */ }, { /* 13745 */ 758, /* VPTESTNMDZrmbk */ }, { /* 13746 */ 750, /* VPTESTNMDZrmk */ }, { /* 13747 */ 751, /* VPTESTNMDZrr */ }, { /* 13748 */ 752, /* VPTESTNMDZrrk */ }, { /* 13749 */ 741, /* VPTESTNMQZ128rm */ }, { /* 13750 */ 759, /* VPTESTNMQZ128rmb */ }, { /* 13751 */ 760, /* VPTESTNMQZ128rmbk */ }, { /* 13752 */ 742, /* VPTESTNMQZ128rmk */ }, { /* 13753 */ 743, /* VPTESTNMQZ128rr */ }, { /* 13754 */ 744, /* VPTESTNMQZ128rrk */ }, { /* 13755 */ 745, /* VPTESTNMQZ256rm */ }, { /* 13756 */ 761, /* VPTESTNMQZ256rmb */ }, { /* 13757 */ 762, /* VPTESTNMQZ256rmbk */ }, { /* 13758 */ 746, /* VPTESTNMQZ256rmk */ }, { /* 13759 */ 747, /* VPTESTNMQZ256rr */ }, { /* 13760 */ 748, /* VPTESTNMQZ256rrk */ }, { /* 13761 */ 749, /* VPTESTNMQZrm */ }, { /* 13762 */ 763, /* VPTESTNMQZrmb */ }, { /* 13763 */ 764, /* VPTESTNMQZrmbk */ }, { /* 13764 */ 750, /* VPTESTNMQZrmk */ }, { /* 13765 */ 751, /* VPTESTNMQZrr */ }, { /* 13766 */ 752, /* VPTESTNMQZrrk */ }, { /* 13767 */ 741, /* VPTESTNMWZ128rm */ }, { /* 13768 */ 742, /* VPTESTNMWZ128rmk */ }, { /* 13769 */ 743, /* VPTESTNMWZ128rr */ }, { /* 13770 */ 744, /* VPTESTNMWZ128rrk */ }, { /* 13771 */ 745, /* VPTESTNMWZ256rm */ }, { /* 13772 */ 746, /* VPTESTNMWZ256rmk */ }, { /* 13773 */ 747, /* VPTESTNMWZ256rr */ }, { /* 13774 */ 748, /* VPTESTNMWZ256rrk */ }, { /* 13775 */ 749, /* VPTESTNMWZrm */ }, { /* 13776 */ 750, /* VPTESTNMWZrmk */ }, { /* 13777 */ 751, /* VPTESTNMWZrr */ }, { /* 13778 */ 752, /* VPTESTNMWZrrk */ }, { /* 13779 */ 305, /* VPTESTYrm */ }, { /* 13780 */ 408, /* VPTESTYrr */ }, { /* 13781 */ 30, /* VPTESTrm */ }, { /* 13782 */ 31, /* VPTESTrr */ }, { /* 13783 */ 204, /* VPUNPCKHBWYrm */ }, { /* 13784 */ 205, /* VPUNPCKHBWYrr */ }, { /* 13785 */ 206, /* VPUNPCKHBWZ128rm */ }, { /* 13786 */ 203, /* VPUNPCKHBWZ128rmk */ }, { /* 13787 */ 210, /* VPUNPCKHBWZ128rmkz */ }, { /* 13788 */ 211, /* VPUNPCKHBWZ128rr */ }, { /* 13789 */ 212, /* VPUNPCKHBWZ128rrk */ }, { /* 13790 */ 213, /* VPUNPCKHBWZ128rrkz */ }, { /* 13791 */ 214, /* VPUNPCKHBWZ256rm */ }, { /* 13792 */ 218, /* VPUNPCKHBWZ256rmk */ }, { /* 13793 */ 219, /* VPUNPCKHBWZ256rmkz */ }, { /* 13794 */ 220, /* VPUNPCKHBWZ256rr */ }, { /* 13795 */ 221, /* VPUNPCKHBWZ256rrk */ }, { /* 13796 */ 222, /* VPUNPCKHBWZ256rrkz */ }, { /* 13797 */ 223, /* VPUNPCKHBWZrm */ }, { /* 13798 */ 227, /* VPUNPCKHBWZrmk */ }, { /* 13799 */ 228, /* VPUNPCKHBWZrmkz */ }, { /* 13800 */ 229, /* VPUNPCKHBWZrr */ }, { /* 13801 */ 233, /* VPUNPCKHBWZrrk */ }, { /* 13802 */ 234, /* VPUNPCKHBWZrrkz */ }, { /* 13803 */ 235, /* VPUNPCKHBWrm */ }, { /* 13804 */ 236, /* VPUNPCKHBWrr */ }, { /* 13805 */ 204, /* VPUNPCKHDQYrm */ }, { /* 13806 */ 205, /* VPUNPCKHDQYrr */ }, { /* 13807 */ 206, /* VPUNPCKHDQZ128rm */ }, { /* 13808 */ 237, /* VPUNPCKHDQZ128rmb */ }, { /* 13809 */ 238, /* VPUNPCKHDQZ128rmbk */ }, { /* 13810 */ 239, /* VPUNPCKHDQZ128rmbkz */ }, { /* 13811 */ 203, /* VPUNPCKHDQZ128rmk */ }, { /* 13812 */ 210, /* VPUNPCKHDQZ128rmkz */ }, { /* 13813 */ 211, /* VPUNPCKHDQZ128rr */ }, { /* 13814 */ 212, /* VPUNPCKHDQZ128rrk */ }, { /* 13815 */ 213, /* VPUNPCKHDQZ128rrkz */ }, { /* 13816 */ 214, /* VPUNPCKHDQZ256rm */ }, { /* 13817 */ 240, /* VPUNPCKHDQZ256rmb */ }, { /* 13818 */ 241, /* VPUNPCKHDQZ256rmbk */ }, { /* 13819 */ 242, /* VPUNPCKHDQZ256rmbkz */ }, { /* 13820 */ 218, /* VPUNPCKHDQZ256rmk */ }, { /* 13821 */ 219, /* VPUNPCKHDQZ256rmkz */ }, { /* 13822 */ 220, /* VPUNPCKHDQZ256rr */ }, { /* 13823 */ 221, /* VPUNPCKHDQZ256rrk */ }, { /* 13824 */ 222, /* VPUNPCKHDQZ256rrkz */ }, { /* 13825 */ 223, /* VPUNPCKHDQZrm */ }, { /* 13826 */ 243, /* VPUNPCKHDQZrmb */ }, { /* 13827 */ 244, /* VPUNPCKHDQZrmbk */ }, { /* 13828 */ 245, /* VPUNPCKHDQZrmbkz */ }, { /* 13829 */ 227, /* VPUNPCKHDQZrmk */ }, { /* 13830 */ 228, /* VPUNPCKHDQZrmkz */ }, { /* 13831 */ 229, /* VPUNPCKHDQZrr */ }, { /* 13832 */ 233, /* VPUNPCKHDQZrrk */ }, { /* 13833 */ 234, /* VPUNPCKHDQZrrkz */ }, { /* 13834 */ 235, /* VPUNPCKHDQrm */ }, { /* 13835 */ 236, /* VPUNPCKHDQrr */ }, { /* 13836 */ 204, /* VPUNPCKHQDQYrm */ }, { /* 13837 */ 205, /* VPUNPCKHQDQYrr */ }, { /* 13838 */ 206, /* VPUNPCKHQDQZ128rm */ }, { /* 13839 */ 207, /* VPUNPCKHQDQZ128rmb */ }, { /* 13840 */ 208, /* VPUNPCKHQDQZ128rmbk */ }, { /* 13841 */ 209, /* VPUNPCKHQDQZ128rmbkz */ }, { /* 13842 */ 203, /* VPUNPCKHQDQZ128rmk */ }, { /* 13843 */ 210, /* VPUNPCKHQDQZ128rmkz */ }, { /* 13844 */ 211, /* VPUNPCKHQDQZ128rr */ }, { /* 13845 */ 212, /* VPUNPCKHQDQZ128rrk */ }, { /* 13846 */ 213, /* VPUNPCKHQDQZ128rrkz */ }, { /* 13847 */ 214, /* VPUNPCKHQDQZ256rm */ }, { /* 13848 */ 215, /* VPUNPCKHQDQZ256rmb */ }, { /* 13849 */ 216, /* VPUNPCKHQDQZ256rmbk */ }, { /* 13850 */ 217, /* VPUNPCKHQDQZ256rmbkz */ }, { /* 13851 */ 218, /* VPUNPCKHQDQZ256rmk */ }, { /* 13852 */ 219, /* VPUNPCKHQDQZ256rmkz */ }, { /* 13853 */ 220, /* VPUNPCKHQDQZ256rr */ }, { /* 13854 */ 221, /* VPUNPCKHQDQZ256rrk */ }, { /* 13855 */ 222, /* VPUNPCKHQDQZ256rrkz */ }, { /* 13856 */ 223, /* VPUNPCKHQDQZrm */ }, { /* 13857 */ 224, /* VPUNPCKHQDQZrmb */ }, { /* 13858 */ 225, /* VPUNPCKHQDQZrmbk */ }, { /* 13859 */ 226, /* VPUNPCKHQDQZrmbkz */ }, { /* 13860 */ 227, /* VPUNPCKHQDQZrmk */ }, { /* 13861 */ 228, /* VPUNPCKHQDQZrmkz */ }, { /* 13862 */ 229, /* VPUNPCKHQDQZrr */ }, { /* 13863 */ 233, /* VPUNPCKHQDQZrrk */ }, { /* 13864 */ 234, /* VPUNPCKHQDQZrrkz */ }, { /* 13865 */ 235, /* VPUNPCKHQDQrm */ }, { /* 13866 */ 236, /* VPUNPCKHQDQrr */ }, { /* 13867 */ 204, /* VPUNPCKHWDYrm */ }, { /* 13868 */ 205, /* VPUNPCKHWDYrr */ }, { /* 13869 */ 206, /* VPUNPCKHWDZ128rm */ }, { /* 13870 */ 203, /* VPUNPCKHWDZ128rmk */ }, { /* 13871 */ 210, /* VPUNPCKHWDZ128rmkz */ }, { /* 13872 */ 211, /* VPUNPCKHWDZ128rr */ }, { /* 13873 */ 212, /* VPUNPCKHWDZ128rrk */ }, { /* 13874 */ 213, /* VPUNPCKHWDZ128rrkz */ }, { /* 13875 */ 214, /* VPUNPCKHWDZ256rm */ }, { /* 13876 */ 218, /* VPUNPCKHWDZ256rmk */ }, { /* 13877 */ 219, /* VPUNPCKHWDZ256rmkz */ }, { /* 13878 */ 220, /* VPUNPCKHWDZ256rr */ }, { /* 13879 */ 221, /* VPUNPCKHWDZ256rrk */ }, { /* 13880 */ 222, /* VPUNPCKHWDZ256rrkz */ }, { /* 13881 */ 223, /* VPUNPCKHWDZrm */ }, { /* 13882 */ 227, /* VPUNPCKHWDZrmk */ }, { /* 13883 */ 228, /* VPUNPCKHWDZrmkz */ }, { /* 13884 */ 229, /* VPUNPCKHWDZrr */ }, { /* 13885 */ 233, /* VPUNPCKHWDZrrk */ }, { /* 13886 */ 234, /* VPUNPCKHWDZrrkz */ }, { /* 13887 */ 235, /* VPUNPCKHWDrm */ }, { /* 13888 */ 236, /* VPUNPCKHWDrr */ }, { /* 13889 */ 204, /* VPUNPCKLBWYrm */ }, { /* 13890 */ 205, /* VPUNPCKLBWYrr */ }, { /* 13891 */ 206, /* VPUNPCKLBWZ128rm */ }, { /* 13892 */ 203, /* VPUNPCKLBWZ128rmk */ }, { /* 13893 */ 210, /* VPUNPCKLBWZ128rmkz */ }, { /* 13894 */ 211, /* VPUNPCKLBWZ128rr */ }, { /* 13895 */ 212, /* VPUNPCKLBWZ128rrk */ }, { /* 13896 */ 213, /* VPUNPCKLBWZ128rrkz */ }, { /* 13897 */ 214, /* VPUNPCKLBWZ256rm */ }, { /* 13898 */ 218, /* VPUNPCKLBWZ256rmk */ }, { /* 13899 */ 219, /* VPUNPCKLBWZ256rmkz */ }, { /* 13900 */ 220, /* VPUNPCKLBWZ256rr */ }, { /* 13901 */ 221, /* VPUNPCKLBWZ256rrk */ }, { /* 13902 */ 222, /* VPUNPCKLBWZ256rrkz */ }, { /* 13903 */ 223, /* VPUNPCKLBWZrm */ }, { /* 13904 */ 227, /* VPUNPCKLBWZrmk */ }, { /* 13905 */ 228, /* VPUNPCKLBWZrmkz */ }, { /* 13906 */ 229, /* VPUNPCKLBWZrr */ }, { /* 13907 */ 233, /* VPUNPCKLBWZrrk */ }, { /* 13908 */ 234, /* VPUNPCKLBWZrrkz */ }, { /* 13909 */ 235, /* VPUNPCKLBWrm */ }, { /* 13910 */ 236, /* VPUNPCKLBWrr */ }, { /* 13911 */ 204, /* VPUNPCKLDQYrm */ }, { /* 13912 */ 205, /* VPUNPCKLDQYrr */ }, { /* 13913 */ 206, /* VPUNPCKLDQZ128rm */ }, { /* 13914 */ 237, /* VPUNPCKLDQZ128rmb */ }, { /* 13915 */ 238, /* VPUNPCKLDQZ128rmbk */ }, { /* 13916 */ 239, /* VPUNPCKLDQZ128rmbkz */ }, { /* 13917 */ 203, /* VPUNPCKLDQZ128rmk */ }, { /* 13918 */ 210, /* VPUNPCKLDQZ128rmkz */ }, { /* 13919 */ 211, /* VPUNPCKLDQZ128rr */ }, { /* 13920 */ 212, /* VPUNPCKLDQZ128rrk */ }, { /* 13921 */ 213, /* VPUNPCKLDQZ128rrkz */ }, { /* 13922 */ 214, /* VPUNPCKLDQZ256rm */ }, { /* 13923 */ 240, /* VPUNPCKLDQZ256rmb */ }, { /* 13924 */ 241, /* VPUNPCKLDQZ256rmbk */ }, { /* 13925 */ 242, /* VPUNPCKLDQZ256rmbkz */ }, { /* 13926 */ 218, /* VPUNPCKLDQZ256rmk */ }, { /* 13927 */ 219, /* VPUNPCKLDQZ256rmkz */ }, { /* 13928 */ 220, /* VPUNPCKLDQZ256rr */ }, { /* 13929 */ 221, /* VPUNPCKLDQZ256rrk */ }, { /* 13930 */ 222, /* VPUNPCKLDQZ256rrkz */ }, { /* 13931 */ 223, /* VPUNPCKLDQZrm */ }, { /* 13932 */ 243, /* VPUNPCKLDQZrmb */ }, { /* 13933 */ 244, /* VPUNPCKLDQZrmbk */ }, { /* 13934 */ 245, /* VPUNPCKLDQZrmbkz */ }, { /* 13935 */ 227, /* VPUNPCKLDQZrmk */ }, { /* 13936 */ 228, /* VPUNPCKLDQZrmkz */ }, { /* 13937 */ 229, /* VPUNPCKLDQZrr */ }, { /* 13938 */ 233, /* VPUNPCKLDQZrrk */ }, { /* 13939 */ 234, /* VPUNPCKLDQZrrkz */ }, { /* 13940 */ 235, /* VPUNPCKLDQrm */ }, { /* 13941 */ 236, /* VPUNPCKLDQrr */ }, { /* 13942 */ 204, /* VPUNPCKLQDQYrm */ }, { /* 13943 */ 205, /* VPUNPCKLQDQYrr */ }, { /* 13944 */ 206, /* VPUNPCKLQDQZ128rm */ }, { /* 13945 */ 207, /* VPUNPCKLQDQZ128rmb */ }, { /* 13946 */ 208, /* VPUNPCKLQDQZ128rmbk */ }, { /* 13947 */ 209, /* VPUNPCKLQDQZ128rmbkz */ }, { /* 13948 */ 203, /* VPUNPCKLQDQZ128rmk */ }, { /* 13949 */ 210, /* VPUNPCKLQDQZ128rmkz */ }, { /* 13950 */ 211, /* VPUNPCKLQDQZ128rr */ }, { /* 13951 */ 212, /* VPUNPCKLQDQZ128rrk */ }, { /* 13952 */ 213, /* VPUNPCKLQDQZ128rrkz */ }, { /* 13953 */ 214, /* VPUNPCKLQDQZ256rm */ }, { /* 13954 */ 215, /* VPUNPCKLQDQZ256rmb */ }, { /* 13955 */ 216, /* VPUNPCKLQDQZ256rmbk */ }, { /* 13956 */ 217, /* VPUNPCKLQDQZ256rmbkz */ }, { /* 13957 */ 218, /* VPUNPCKLQDQZ256rmk */ }, { /* 13958 */ 219, /* VPUNPCKLQDQZ256rmkz */ }, { /* 13959 */ 220, /* VPUNPCKLQDQZ256rr */ }, { /* 13960 */ 221, /* VPUNPCKLQDQZ256rrk */ }, { /* 13961 */ 222, /* VPUNPCKLQDQZ256rrkz */ }, { /* 13962 */ 223, /* VPUNPCKLQDQZrm */ }, { /* 13963 */ 224, /* VPUNPCKLQDQZrmb */ }, { /* 13964 */ 225, /* VPUNPCKLQDQZrmbk */ }, { /* 13965 */ 226, /* VPUNPCKLQDQZrmbkz */ }, { /* 13966 */ 227, /* VPUNPCKLQDQZrmk */ }, { /* 13967 */ 228, /* VPUNPCKLQDQZrmkz */ }, { /* 13968 */ 229, /* VPUNPCKLQDQZrr */ }, { /* 13969 */ 233, /* VPUNPCKLQDQZrrk */ }, { /* 13970 */ 234, /* VPUNPCKLQDQZrrkz */ }, { /* 13971 */ 235, /* VPUNPCKLQDQrm */ }, { /* 13972 */ 236, /* VPUNPCKLQDQrr */ }, { /* 13973 */ 204, /* VPUNPCKLWDYrm */ }, { /* 13974 */ 205, /* VPUNPCKLWDYrr */ }, { /* 13975 */ 206, /* VPUNPCKLWDZ128rm */ }, { /* 13976 */ 203, /* VPUNPCKLWDZ128rmk */ }, { /* 13977 */ 210, /* VPUNPCKLWDZ128rmkz */ }, { /* 13978 */ 211, /* VPUNPCKLWDZ128rr */ }, { /* 13979 */ 212, /* VPUNPCKLWDZ128rrk */ }, { /* 13980 */ 213, /* VPUNPCKLWDZ128rrkz */ }, { /* 13981 */ 214, /* VPUNPCKLWDZ256rm */ }, { /* 13982 */ 218, /* VPUNPCKLWDZ256rmk */ }, { /* 13983 */ 219, /* VPUNPCKLWDZ256rmkz */ }, { /* 13984 */ 220, /* VPUNPCKLWDZ256rr */ }, { /* 13985 */ 221, /* VPUNPCKLWDZ256rrk */ }, { /* 13986 */ 222, /* VPUNPCKLWDZ256rrkz */ }, { /* 13987 */ 223, /* VPUNPCKLWDZrm */ }, { /* 13988 */ 227, /* VPUNPCKLWDZrmk */ }, { /* 13989 */ 228, /* VPUNPCKLWDZrmkz */ }, { /* 13990 */ 229, /* VPUNPCKLWDZrr */ }, { /* 13991 */ 233, /* VPUNPCKLWDZrrk */ }, { /* 13992 */ 234, /* VPUNPCKLWDZrrkz */ }, { /* 13993 */ 235, /* VPUNPCKLWDrm */ }, { /* 13994 */ 236, /* VPUNPCKLWDrr */ }, { /* 13995 */ 206, /* VPXORDZ128rm */ }, { /* 13996 */ 237, /* VPXORDZ128rmb */ }, { /* 13997 */ 238, /* VPXORDZ128rmbk */ }, { /* 13998 */ 239, /* VPXORDZ128rmbkz */ }, { /* 13999 */ 203, /* VPXORDZ128rmk */ }, { /* 14000 */ 210, /* VPXORDZ128rmkz */ }, { /* 14001 */ 211, /* VPXORDZ128rr */ }, { /* 14002 */ 212, /* VPXORDZ128rrk */ }, { /* 14003 */ 213, /* VPXORDZ128rrkz */ }, { /* 14004 */ 214, /* VPXORDZ256rm */ }, { /* 14005 */ 240, /* VPXORDZ256rmb */ }, { /* 14006 */ 241, /* VPXORDZ256rmbk */ }, { /* 14007 */ 242, /* VPXORDZ256rmbkz */ }, { /* 14008 */ 218, /* VPXORDZ256rmk */ }, { /* 14009 */ 219, /* VPXORDZ256rmkz */ }, { /* 14010 */ 220, /* VPXORDZ256rr */ }, { /* 14011 */ 221, /* VPXORDZ256rrk */ }, { /* 14012 */ 222, /* VPXORDZ256rrkz */ }, { /* 14013 */ 223, /* VPXORDZrm */ }, { /* 14014 */ 243, /* VPXORDZrmb */ }, { /* 14015 */ 244, /* VPXORDZrmbk */ }, { /* 14016 */ 245, /* VPXORDZrmbkz */ }, { /* 14017 */ 227, /* VPXORDZrmk */ }, { /* 14018 */ 228, /* VPXORDZrmkz */ }, { /* 14019 */ 229, /* VPXORDZrr */ }, { /* 14020 */ 233, /* VPXORDZrrk */ }, { /* 14021 */ 234, /* VPXORDZrrkz */ }, { /* 14022 */ 206, /* VPXORQZ128rm */ }, { /* 14023 */ 207, /* VPXORQZ128rmb */ }, { /* 14024 */ 208, /* VPXORQZ128rmbk */ }, { /* 14025 */ 209, /* VPXORQZ128rmbkz */ }, { /* 14026 */ 203, /* VPXORQZ128rmk */ }, { /* 14027 */ 210, /* VPXORQZ128rmkz */ }, { /* 14028 */ 211, /* VPXORQZ128rr */ }, { /* 14029 */ 212, /* VPXORQZ128rrk */ }, { /* 14030 */ 213, /* VPXORQZ128rrkz */ }, { /* 14031 */ 214, /* VPXORQZ256rm */ }, { /* 14032 */ 215, /* VPXORQZ256rmb */ }, { /* 14033 */ 216, /* VPXORQZ256rmbk */ }, { /* 14034 */ 217, /* VPXORQZ256rmbkz */ }, { /* 14035 */ 218, /* VPXORQZ256rmk */ }, { /* 14036 */ 219, /* VPXORQZ256rmkz */ }, { /* 14037 */ 220, /* VPXORQZ256rr */ }, { /* 14038 */ 221, /* VPXORQZ256rrk */ }, { /* 14039 */ 222, /* VPXORQZ256rrkz */ }, { /* 14040 */ 223, /* VPXORQZrm */ }, { /* 14041 */ 224, /* VPXORQZrmb */ }, { /* 14042 */ 225, /* VPXORQZrmbk */ }, { /* 14043 */ 226, /* VPXORQZrmbkz */ }, { /* 14044 */ 227, /* VPXORQZrmk */ }, { /* 14045 */ 228, /* VPXORQZrmkz */ }, { /* 14046 */ 229, /* VPXORQZrr */ }, { /* 14047 */ 233, /* VPXORQZrrk */ }, { /* 14048 */ 234, /* VPXORQZrrkz */ }, { /* 14049 */ 204, /* VPXORYrm */ }, { /* 14050 */ 205, /* VPXORYrr */ }, { /* 14051 */ 235, /* VPXORrm */ }, { /* 14052 */ 236, /* VPXORrr */ }, { /* 14053 */ 288, /* VRANGEPDZ128rmbi */ }, { /* 14054 */ 289, /* VRANGEPDZ128rmbik */ }, { /* 14055 */ 290, /* VRANGEPDZ128rmbikz */ }, { /* 14056 */ 264, /* VRANGEPDZ128rmi */ }, { /* 14057 */ 265, /* VRANGEPDZ128rmik */ }, { /* 14058 */ 266, /* VRANGEPDZ128rmikz */ }, { /* 14059 */ 267, /* VRANGEPDZ128rri */ }, { /* 14060 */ 268, /* VRANGEPDZ128rrik */ }, { /* 14061 */ 269, /* VRANGEPDZ128rrikz */ }, { /* 14062 */ 291, /* VRANGEPDZ256rmbi */ }, { /* 14063 */ 292, /* VRANGEPDZ256rmbik */ }, { /* 14064 */ 293, /* VRANGEPDZ256rmbikz */ }, { /* 14065 */ 273, /* VRANGEPDZ256rmi */ }, { /* 14066 */ 274, /* VRANGEPDZ256rmik */ }, { /* 14067 */ 275, /* VRANGEPDZ256rmikz */ }, { /* 14068 */ 276, /* VRANGEPDZ256rri */ }, { /* 14069 */ 277, /* VRANGEPDZ256rrik */ }, { /* 14070 */ 278, /* VRANGEPDZ256rrikz */ }, { /* 14071 */ 294, /* VRANGEPDZrmbi */ }, { /* 14072 */ 295, /* VRANGEPDZrmbik */ }, { /* 14073 */ 296, /* VRANGEPDZrmbikz */ }, { /* 14074 */ 282, /* VRANGEPDZrmi */ }, { /* 14075 */ 283, /* VRANGEPDZrmik */ }, { /* 14076 */ 284, /* VRANGEPDZrmikz */ }, { /* 14077 */ 285, /* VRANGEPDZrri */ }, { /* 14078 */ 916, /* VRANGEPDZrrib */ }, { /* 14079 */ 517, /* VRANGEPDZrribk */ }, { /* 14080 */ 917, /* VRANGEPDZrribkz */ }, { /* 14081 */ 286, /* VRANGEPDZrrik */ }, { /* 14082 */ 287, /* VRANGEPDZrrikz */ }, { /* 14083 */ 261, /* VRANGEPSZ128rmbi */ }, { /* 14084 */ 262, /* VRANGEPSZ128rmbik */ }, { /* 14085 */ 263, /* VRANGEPSZ128rmbikz */ }, { /* 14086 */ 264, /* VRANGEPSZ128rmi */ }, { /* 14087 */ 265, /* VRANGEPSZ128rmik */ }, { /* 14088 */ 266, /* VRANGEPSZ128rmikz */ }, { /* 14089 */ 267, /* VRANGEPSZ128rri */ }, { /* 14090 */ 268, /* VRANGEPSZ128rrik */ }, { /* 14091 */ 269, /* VRANGEPSZ128rrikz */ }, { /* 14092 */ 270, /* VRANGEPSZ256rmbi */ }, { /* 14093 */ 271, /* VRANGEPSZ256rmbik */ }, { /* 14094 */ 272, /* VRANGEPSZ256rmbikz */ }, { /* 14095 */ 273, /* VRANGEPSZ256rmi */ }, { /* 14096 */ 274, /* VRANGEPSZ256rmik */ }, { /* 14097 */ 275, /* VRANGEPSZ256rmikz */ }, { /* 14098 */ 276, /* VRANGEPSZ256rri */ }, { /* 14099 */ 277, /* VRANGEPSZ256rrik */ }, { /* 14100 */ 278, /* VRANGEPSZ256rrikz */ }, { /* 14101 */ 279, /* VRANGEPSZrmbi */ }, { /* 14102 */ 280, /* VRANGEPSZrmbik */ }, { /* 14103 */ 281, /* VRANGEPSZrmbikz */ }, { /* 14104 */ 282, /* VRANGEPSZrmi */ }, { /* 14105 */ 283, /* VRANGEPSZrmik */ }, { /* 14106 */ 284, /* VRANGEPSZrmikz */ }, { /* 14107 */ 285, /* VRANGEPSZrri */ }, { /* 14108 */ 918, /* VRANGEPSZrrib */ }, { /* 14109 */ 522, /* VRANGEPSZrribk */ }, { /* 14110 */ 919, /* VRANGEPSZrribkz */ }, { /* 14111 */ 286, /* VRANGEPSZrrik */ }, { /* 14112 */ 287, /* VRANGEPSZrrikz */ }, { /* 14113 */ 288, /* VRANGESDZrmi */ }, { /* 14114 */ 289, /* VRANGESDZrmik */ }, { /* 14115 */ 290, /* VRANGESDZrmikz */ }, { /* 14116 */ 631, /* VRANGESDZrri */ }, { /* 14117 */ 631, /* VRANGESDZrrib */ }, { /* 14118 */ 524, /* VRANGESDZrribk */ }, { /* 14119 */ 632, /* VRANGESDZrribkz */ }, { /* 14120 */ 524, /* VRANGESDZrrik */ }, { /* 14121 */ 632, /* VRANGESDZrrikz */ }, { /* 14122 */ 261, /* VRANGESSZrmi */ }, { /* 14123 */ 262, /* VRANGESSZrmik */ }, { /* 14124 */ 263, /* VRANGESSZrmikz */ }, { /* 14125 */ 633, /* VRANGESSZrri */ }, { /* 14126 */ 633, /* VRANGESSZrrib */ }, { /* 14127 */ 526, /* VRANGESSZrribk */ }, { /* 14128 */ 634, /* VRANGESSZrribkz */ }, { /* 14129 */ 526, /* VRANGESSZrrik */ }, { /* 14130 */ 634, /* VRANGESSZrrikz */ }, { /* 14131 */ 409, /* VRCP14PDZ128m */ }, { /* 14132 */ 327, /* VRCP14PDZ128mb */ }, { /* 14133 */ 328, /* VRCP14PDZ128mbk */ }, { /* 14134 */ 329, /* VRCP14PDZ128mbkz */ }, { /* 14135 */ 410, /* VRCP14PDZ128mk */ }, { /* 14136 */ 411, /* VRCP14PDZ128mkz */ }, { /* 14137 */ 330, /* VRCP14PDZ128r */ }, { /* 14138 */ 331, /* VRCP14PDZ128rk */ }, { /* 14139 */ 332, /* VRCP14PDZ128rkz */ }, { /* 14140 */ 412, /* VRCP14PDZ256m */ }, { /* 14141 */ 306, /* VRCP14PDZ256mb */ }, { /* 14142 */ 307, /* VRCP14PDZ256mbk */ }, { /* 14143 */ 308, /* VRCP14PDZ256mbkz */ }, { /* 14144 */ 413, /* VRCP14PDZ256mk */ }, { /* 14145 */ 414, /* VRCP14PDZ256mkz */ }, { /* 14146 */ 415, /* VRCP14PDZ256r */ }, { /* 14147 */ 416, /* VRCP14PDZ256rk */ }, { /* 14148 */ 417, /* VRCP14PDZ256rkz */ }, { /* 14149 */ 418, /* VRCP14PDZm */ }, { /* 14150 */ 312, /* VRCP14PDZmb */ }, { /* 14151 */ 313, /* VRCP14PDZmbk */ }, { /* 14152 */ 314, /* VRCP14PDZmbkz */ }, { /* 14153 */ 419, /* VRCP14PDZmk */ }, { /* 14154 */ 420, /* VRCP14PDZmkz */ }, { /* 14155 */ 421, /* VRCP14PDZr */ }, { /* 14156 */ 425, /* VRCP14PDZrk */ }, { /* 14157 */ 426, /* VRCP14PDZrkz */ }, { /* 14158 */ 409, /* VRCP14PSZ128m */ }, { /* 14159 */ 334, /* VRCP14PSZ128mb */ }, { /* 14160 */ 335, /* VRCP14PSZ128mbk */ }, { /* 14161 */ 336, /* VRCP14PSZ128mbkz */ }, { /* 14162 */ 410, /* VRCP14PSZ128mk */ }, { /* 14163 */ 411, /* VRCP14PSZ128mkz */ }, { /* 14164 */ 330, /* VRCP14PSZ128r */ }, { /* 14165 */ 331, /* VRCP14PSZ128rk */ }, { /* 14166 */ 332, /* VRCP14PSZ128rkz */ }, { /* 14167 */ 412, /* VRCP14PSZ256m */ }, { /* 14168 */ 337, /* VRCP14PSZ256mb */ }, { /* 14169 */ 338, /* VRCP14PSZ256mbk */ }, { /* 14170 */ 339, /* VRCP14PSZ256mbkz */ }, { /* 14171 */ 413, /* VRCP14PSZ256mk */ }, { /* 14172 */ 414, /* VRCP14PSZ256mkz */ }, { /* 14173 */ 415, /* VRCP14PSZ256r */ }, { /* 14174 */ 416, /* VRCP14PSZ256rk */ }, { /* 14175 */ 417, /* VRCP14PSZ256rkz */ }, { /* 14176 */ 418, /* VRCP14PSZm */ }, { /* 14177 */ 340, /* VRCP14PSZmb */ }, { /* 14178 */ 341, /* VRCP14PSZmbk */ }, { /* 14179 */ 342, /* VRCP14PSZmbkz */ }, { /* 14180 */ 419, /* VRCP14PSZmk */ }, { /* 14181 */ 420, /* VRCP14PSZmkz */ }, { /* 14182 */ 421, /* VRCP14PSZr */ }, { /* 14183 */ 425, /* VRCP14PSZrk */ }, { /* 14184 */ 426, /* VRCP14PSZrkz */ }, { /* 14185 */ 207, /* VRCP14SDZrm */ }, { /* 14186 */ 208, /* VRCP14SDZrmk */ }, { /* 14187 */ 209, /* VRCP14SDZrmkz */ }, { /* 14188 */ 249, /* VRCP14SDZrr */ }, { /* 14189 */ 250, /* VRCP14SDZrrk */ }, { /* 14190 */ 251, /* VRCP14SDZrrkz */ }, { /* 14191 */ 237, /* VRCP14SSZrm */ }, { /* 14192 */ 238, /* VRCP14SSZrmk */ }, { /* 14193 */ 239, /* VRCP14SSZrmkz */ }, { /* 14194 */ 255, /* VRCP14SSZrr */ }, { /* 14195 */ 256, /* VRCP14SSZrrk */ }, { /* 14196 */ 257, /* VRCP14SSZrrkz */ }, { /* 14197 */ 418, /* VRCP28PDZm */ }, { /* 14198 */ 312, /* VRCP28PDZmb */ }, { /* 14199 */ 313, /* VRCP28PDZmbk */ }, { /* 14200 */ 314, /* VRCP28PDZmbkz */ }, { /* 14201 */ 419, /* VRCP28PDZmk */ }, { /* 14202 */ 420, /* VRCP28PDZmkz */ }, { /* 14203 */ 421, /* VRCP28PDZr */ }, { /* 14204 */ 494, /* VRCP28PDZrb */ }, { /* 14205 */ 495, /* VRCP28PDZrbk */ }, { /* 14206 */ 496, /* VRCP28PDZrbkz */ }, { /* 14207 */ 425, /* VRCP28PDZrk */ }, { /* 14208 */ 426, /* VRCP28PDZrkz */ }, { /* 14209 */ 418, /* VRCP28PSZm */ }, { /* 14210 */ 340, /* VRCP28PSZmb */ }, { /* 14211 */ 341, /* VRCP28PSZmbk */ }, { /* 14212 */ 342, /* VRCP28PSZmbkz */ }, { /* 14213 */ 419, /* VRCP28PSZmk */ }, { /* 14214 */ 420, /* VRCP28PSZmkz */ }, { /* 14215 */ 421, /* VRCP28PSZr */ }, { /* 14216 */ 497, /* VRCP28PSZrb */ }, { /* 14217 */ 498, /* VRCP28PSZrbk */ }, { /* 14218 */ 499, /* VRCP28PSZrbkz */ }, { /* 14219 */ 425, /* VRCP28PSZrk */ }, { /* 14220 */ 426, /* VRCP28PSZrkz */ }, { /* 14221 */ 207, /* VRCP28SDZm */ }, { /* 14222 */ 208, /* VRCP28SDZmk */ }, { /* 14223 */ 209, /* VRCP28SDZmkz */ }, { /* 14224 */ 249, /* VRCP28SDZr */ }, { /* 14225 */ 249, /* VRCP28SDZrb */ }, { /* 14226 */ 250, /* VRCP28SDZrbk */ }, { /* 14227 */ 251, /* VRCP28SDZrbkz */ }, { /* 14228 */ 250, /* VRCP28SDZrk */ }, { /* 14229 */ 251, /* VRCP28SDZrkz */ }, { /* 14230 */ 237, /* VRCP28SSZm */ }, { /* 14231 */ 238, /* VRCP28SSZmk */ }, { /* 14232 */ 239, /* VRCP28SSZmkz */ }, { /* 14233 */ 255, /* VRCP28SSZr */ }, { /* 14234 */ 255, /* VRCP28SSZrb */ }, { /* 14235 */ 256, /* VRCP28SSZrbk */ }, { /* 14236 */ 257, /* VRCP28SSZrbkz */ }, { /* 14237 */ 256, /* VRCP28SSZrk */ }, { /* 14238 */ 257, /* VRCP28SSZrkz */ }, { /* 14239 */ 305, /* VRCPPSYm */ }, { /* 14240 */ 408, /* VRCPPSYr */ }, { /* 14241 */ 30, /* VRCPPSm */ }, { /* 14242 */ 31, /* VRCPPSr */ }, { /* 14243 */ 235, /* VRCPSSm */ }, { /* 14244 */ 0, /* */ }, { /* 14245 */ 236, /* VRCPSSr */ }, { /* 14246 */ 0, /* */ }, { /* 14247 */ 589, /* VREDUCEPDZ128rmbi */ }, { /* 14248 */ 590, /* VREDUCEPDZ128rmbik */ }, { /* 14249 */ 591, /* VREDUCEPDZ128rmbikz */ }, { /* 14250 */ 592, /* VREDUCEPDZ128rmi */ }, { /* 14251 */ 593, /* VREDUCEPDZ128rmik */ }, { /* 14252 */ 594, /* VREDUCEPDZ128rmikz */ }, { /* 14253 */ 595, /* VREDUCEPDZ128rri */ }, { /* 14254 */ 596, /* VREDUCEPDZ128rrik */ }, { /* 14255 */ 597, /* VREDUCEPDZ128rrikz */ }, { /* 14256 */ 598, /* VREDUCEPDZ256rmbi */ }, { /* 14257 */ 599, /* VREDUCEPDZ256rmbik */ }, { /* 14258 */ 600, /* VREDUCEPDZ256rmbikz */ }, { /* 14259 */ 601, /* VREDUCEPDZ256rmi */ }, { /* 14260 */ 602, /* VREDUCEPDZ256rmik */ }, { /* 14261 */ 603, /* VREDUCEPDZ256rmikz */ }, { /* 14262 */ 604, /* VREDUCEPDZ256rri */ }, { /* 14263 */ 605, /* VREDUCEPDZ256rrik */ }, { /* 14264 */ 606, /* VREDUCEPDZ256rrikz */ }, { /* 14265 */ 607, /* VREDUCEPDZrmbi */ }, { /* 14266 */ 608, /* VREDUCEPDZrmbik */ }, { /* 14267 */ 609, /* VREDUCEPDZrmbikz */ }, { /* 14268 */ 610, /* VREDUCEPDZrmi */ }, { /* 14269 */ 611, /* VREDUCEPDZrmik */ }, { /* 14270 */ 612, /* VREDUCEPDZrmikz */ }, { /* 14271 */ 613, /* VREDUCEPDZrri */ }, { /* 14272 */ 614, /* VREDUCEPDZrrib */ }, { /* 14273 */ 615, /* VREDUCEPDZrribk */ }, { /* 14274 */ 616, /* VREDUCEPDZrribkz */ }, { /* 14275 */ 617, /* VREDUCEPDZrrik */ }, { /* 14276 */ 618, /* VREDUCEPDZrrikz */ }, { /* 14277 */ 619, /* VREDUCEPSZ128rmbi */ }, { /* 14278 */ 620, /* VREDUCEPSZ128rmbik */ }, { /* 14279 */ 621, /* VREDUCEPSZ128rmbikz */ }, { /* 14280 */ 592, /* VREDUCEPSZ128rmi */ }, { /* 14281 */ 593, /* VREDUCEPSZ128rmik */ }, { /* 14282 */ 594, /* VREDUCEPSZ128rmikz */ }, { /* 14283 */ 595, /* VREDUCEPSZ128rri */ }, { /* 14284 */ 596, /* VREDUCEPSZ128rrik */ }, { /* 14285 */ 597, /* VREDUCEPSZ128rrikz */ }, { /* 14286 */ 622, /* VREDUCEPSZ256rmbi */ }, { /* 14287 */ 623, /* VREDUCEPSZ256rmbik */ }, { /* 14288 */ 624, /* VREDUCEPSZ256rmbikz */ }, { /* 14289 */ 601, /* VREDUCEPSZ256rmi */ }, { /* 14290 */ 602, /* VREDUCEPSZ256rmik */ }, { /* 14291 */ 603, /* VREDUCEPSZ256rmikz */ }, { /* 14292 */ 604, /* VREDUCEPSZ256rri */ }, { /* 14293 */ 605, /* VREDUCEPSZ256rrik */ }, { /* 14294 */ 606, /* VREDUCEPSZ256rrikz */ }, { /* 14295 */ 625, /* VREDUCEPSZrmbi */ }, { /* 14296 */ 626, /* VREDUCEPSZrmbik */ }, { /* 14297 */ 627, /* VREDUCEPSZrmbikz */ }, { /* 14298 */ 610, /* VREDUCEPSZrmi */ }, { /* 14299 */ 611, /* VREDUCEPSZrmik */ }, { /* 14300 */ 612, /* VREDUCEPSZrmikz */ }, { /* 14301 */ 613, /* VREDUCEPSZrri */ }, { /* 14302 */ 628, /* VREDUCEPSZrrib */ }, { /* 14303 */ 629, /* VREDUCEPSZrribk */ }, { /* 14304 */ 630, /* VREDUCEPSZrribkz */ }, { /* 14305 */ 617, /* VREDUCEPSZrrik */ }, { /* 14306 */ 618, /* VREDUCEPSZrrikz */ }, { /* 14307 */ 288, /* VREDUCESDZrmi */ }, { /* 14308 */ 289, /* VREDUCESDZrmik */ }, { /* 14309 */ 290, /* VREDUCESDZrmikz */ }, { /* 14310 */ 631, /* VREDUCESDZrri */ }, { /* 14311 */ 631, /* VREDUCESDZrrib */ }, { /* 14312 */ 524, /* VREDUCESDZrribk */ }, { /* 14313 */ 632, /* VREDUCESDZrribkz */ }, { /* 14314 */ 524, /* VREDUCESDZrrik */ }, { /* 14315 */ 632, /* VREDUCESDZrrikz */ }, { /* 14316 */ 261, /* VREDUCESSZrmi */ }, { /* 14317 */ 262, /* VREDUCESSZrmik */ }, { /* 14318 */ 263, /* VREDUCESSZrmikz */ }, { /* 14319 */ 633, /* VREDUCESSZrri */ }, { /* 14320 */ 633, /* VREDUCESSZrrib */ }, { /* 14321 */ 526, /* VREDUCESSZrribk */ }, { /* 14322 */ 634, /* VREDUCESSZrribkz */ }, { /* 14323 */ 526, /* VREDUCESSZrrik */ }, { /* 14324 */ 634, /* VREDUCESSZrrikz */ }, { /* 14325 */ 589, /* VRNDSCALEPDZ128rmbi */ }, { /* 14326 */ 590, /* VRNDSCALEPDZ128rmbik */ }, { /* 14327 */ 591, /* VRNDSCALEPDZ128rmbikz */ }, { /* 14328 */ 592, /* VRNDSCALEPDZ128rmi */ }, { /* 14329 */ 593, /* VRNDSCALEPDZ128rmik */ }, { /* 14330 */ 594, /* VRNDSCALEPDZ128rmikz */ }, { /* 14331 */ 595, /* VRNDSCALEPDZ128rri */ }, { /* 14332 */ 596, /* VRNDSCALEPDZ128rrik */ }, { /* 14333 */ 597, /* VRNDSCALEPDZ128rrikz */ }, { /* 14334 */ 598, /* VRNDSCALEPDZ256rmbi */ }, { /* 14335 */ 599, /* VRNDSCALEPDZ256rmbik */ }, { /* 14336 */ 600, /* VRNDSCALEPDZ256rmbikz */ }, { /* 14337 */ 601, /* VRNDSCALEPDZ256rmi */ }, { /* 14338 */ 602, /* VRNDSCALEPDZ256rmik */ }, { /* 14339 */ 603, /* VRNDSCALEPDZ256rmikz */ }, { /* 14340 */ 604, /* VRNDSCALEPDZ256rri */ }, { /* 14341 */ 605, /* VRNDSCALEPDZ256rrik */ }, { /* 14342 */ 606, /* VRNDSCALEPDZ256rrikz */ }, { /* 14343 */ 607, /* VRNDSCALEPDZrmbi */ }, { /* 14344 */ 608, /* VRNDSCALEPDZrmbik */ }, { /* 14345 */ 609, /* VRNDSCALEPDZrmbikz */ }, { /* 14346 */ 610, /* VRNDSCALEPDZrmi */ }, { /* 14347 */ 611, /* VRNDSCALEPDZrmik */ }, { /* 14348 */ 612, /* VRNDSCALEPDZrmikz */ }, { /* 14349 */ 613, /* VRNDSCALEPDZrri */ }, { /* 14350 */ 614, /* VRNDSCALEPDZrrib */ }, { /* 14351 */ 615, /* VRNDSCALEPDZrribk */ }, { /* 14352 */ 616, /* VRNDSCALEPDZrribkz */ }, { /* 14353 */ 617, /* VRNDSCALEPDZrrik */ }, { /* 14354 */ 618, /* VRNDSCALEPDZrrikz */ }, { /* 14355 */ 619, /* VRNDSCALEPSZ128rmbi */ }, { /* 14356 */ 620, /* VRNDSCALEPSZ128rmbik */ }, { /* 14357 */ 621, /* VRNDSCALEPSZ128rmbikz */ }, { /* 14358 */ 592, /* VRNDSCALEPSZ128rmi */ }, { /* 14359 */ 593, /* VRNDSCALEPSZ128rmik */ }, { /* 14360 */ 594, /* VRNDSCALEPSZ128rmikz */ }, { /* 14361 */ 595, /* VRNDSCALEPSZ128rri */ }, { /* 14362 */ 596, /* VRNDSCALEPSZ128rrik */ }, { /* 14363 */ 597, /* VRNDSCALEPSZ128rrikz */ }, { /* 14364 */ 622, /* VRNDSCALEPSZ256rmbi */ }, { /* 14365 */ 623, /* VRNDSCALEPSZ256rmbik */ }, { /* 14366 */ 624, /* VRNDSCALEPSZ256rmbikz */ }, { /* 14367 */ 601, /* VRNDSCALEPSZ256rmi */ }, { /* 14368 */ 602, /* VRNDSCALEPSZ256rmik */ }, { /* 14369 */ 603, /* VRNDSCALEPSZ256rmikz */ }, { /* 14370 */ 604, /* VRNDSCALEPSZ256rri */ }, { /* 14371 */ 605, /* VRNDSCALEPSZ256rrik */ }, { /* 14372 */ 606, /* VRNDSCALEPSZ256rrikz */ }, { /* 14373 */ 625, /* VRNDSCALEPSZrmbi */ }, { /* 14374 */ 626, /* VRNDSCALEPSZrmbik */ }, { /* 14375 */ 627, /* VRNDSCALEPSZrmbikz */ }, { /* 14376 */ 610, /* VRNDSCALEPSZrmi */ }, { /* 14377 */ 611, /* VRNDSCALEPSZrmik */ }, { /* 14378 */ 612, /* VRNDSCALEPSZrmikz */ }, { /* 14379 */ 613, /* VRNDSCALEPSZrri */ }, { /* 14380 */ 628, /* VRNDSCALEPSZrrib */ }, { /* 14381 */ 629, /* VRNDSCALEPSZrribk */ }, { /* 14382 */ 630, /* VRNDSCALEPSZrribkz */ }, { /* 14383 */ 617, /* VRNDSCALEPSZrrik */ }, { /* 14384 */ 618, /* VRNDSCALEPSZrrikz */ }, { /* 14385 */ 0, /* */ }, { /* 14386 */ 288, /* VRNDSCALESDZm_Int */ }, { /* 14387 */ 289, /* VRNDSCALESDZm_Intk */ }, { /* 14388 */ 290, /* VRNDSCALESDZm_Intkz */ }, { /* 14389 */ 0, /* */ }, { /* 14390 */ 631, /* VRNDSCALESDZr_Int */ }, { /* 14391 */ 524, /* VRNDSCALESDZr_Intk */ }, { /* 14392 */ 632, /* VRNDSCALESDZr_Intkz */ }, { /* 14393 */ 631, /* VRNDSCALESDZrb_Int */ }, { /* 14394 */ 524, /* VRNDSCALESDZrb_Intk */ }, { /* 14395 */ 632, /* VRNDSCALESDZrb_Intkz */ }, { /* 14396 */ 0, /* */ }, { /* 14397 */ 261, /* VRNDSCALESSZm_Int */ }, { /* 14398 */ 262, /* VRNDSCALESSZm_Intk */ }, { /* 14399 */ 263, /* VRNDSCALESSZm_Intkz */ }, { /* 14400 */ 0, /* */ }, { /* 14401 */ 633, /* VRNDSCALESSZr_Int */ }, { /* 14402 */ 526, /* VRNDSCALESSZr_Intk */ }, { /* 14403 */ 634, /* VRNDSCALESSZr_Intkz */ }, { /* 14404 */ 633, /* VRNDSCALESSZrb_Int */ }, { /* 14405 */ 526, /* VRNDSCALESSZrb_Intk */ }, { /* 14406 */ 634, /* VRNDSCALESSZrb_Intkz */ }, { /* 14407 */ 791, /* VROUNDPDYm */ }, { /* 14408 */ 792, /* VROUNDPDYr */ }, { /* 14409 */ 32, /* VROUNDPDm */ }, { /* 14410 */ 33, /* VROUNDPDr */ }, { /* 14411 */ 791, /* VROUNDPSYm */ }, { /* 14412 */ 792, /* VROUNDPSYr */ }, { /* 14413 */ 32, /* VROUNDPSm */ }, { /* 14414 */ 33, /* VROUNDPSr */ }, { /* 14415 */ 299, /* VROUNDSDm */ }, { /* 14416 */ 0, /* */ }, { /* 14417 */ 300, /* VROUNDSDr */ }, { /* 14418 */ 0, /* */ }, { /* 14419 */ 299, /* VROUNDSSm */ }, { /* 14420 */ 0, /* */ }, { /* 14421 */ 300, /* VROUNDSSr */ }, { /* 14422 */ 0, /* */ }, { /* 14423 */ 409, /* VRSQRT14PDZ128m */ }, { /* 14424 */ 327, /* VRSQRT14PDZ128mb */ }, { /* 14425 */ 328, /* VRSQRT14PDZ128mbk */ }, { /* 14426 */ 329, /* VRSQRT14PDZ128mbkz */ }, { /* 14427 */ 410, /* VRSQRT14PDZ128mk */ }, { /* 14428 */ 411, /* VRSQRT14PDZ128mkz */ }, { /* 14429 */ 330, /* VRSQRT14PDZ128r */ }, { /* 14430 */ 331, /* VRSQRT14PDZ128rk */ }, { /* 14431 */ 332, /* VRSQRT14PDZ128rkz */ }, { /* 14432 */ 412, /* VRSQRT14PDZ256m */ }, { /* 14433 */ 306, /* VRSQRT14PDZ256mb */ }, { /* 14434 */ 307, /* VRSQRT14PDZ256mbk */ }, { /* 14435 */ 308, /* VRSQRT14PDZ256mbkz */ }, { /* 14436 */ 413, /* VRSQRT14PDZ256mk */ }, { /* 14437 */ 414, /* VRSQRT14PDZ256mkz */ }, { /* 14438 */ 415, /* VRSQRT14PDZ256r */ }, { /* 14439 */ 416, /* VRSQRT14PDZ256rk */ }, { /* 14440 */ 417, /* VRSQRT14PDZ256rkz */ }, { /* 14441 */ 418, /* VRSQRT14PDZm */ }, { /* 14442 */ 312, /* VRSQRT14PDZmb */ }, { /* 14443 */ 313, /* VRSQRT14PDZmbk */ }, { /* 14444 */ 314, /* VRSQRT14PDZmbkz */ }, { /* 14445 */ 419, /* VRSQRT14PDZmk */ }, { /* 14446 */ 420, /* VRSQRT14PDZmkz */ }, { /* 14447 */ 421, /* VRSQRT14PDZr */ }, { /* 14448 */ 425, /* VRSQRT14PDZrk */ }, { /* 14449 */ 426, /* VRSQRT14PDZrkz */ }, { /* 14450 */ 409, /* VRSQRT14PSZ128m */ }, { /* 14451 */ 334, /* VRSQRT14PSZ128mb */ }, { /* 14452 */ 335, /* VRSQRT14PSZ128mbk */ }, { /* 14453 */ 336, /* VRSQRT14PSZ128mbkz */ }, { /* 14454 */ 410, /* VRSQRT14PSZ128mk */ }, { /* 14455 */ 411, /* VRSQRT14PSZ128mkz */ }, { /* 14456 */ 330, /* VRSQRT14PSZ128r */ }, { /* 14457 */ 331, /* VRSQRT14PSZ128rk */ }, { /* 14458 */ 332, /* VRSQRT14PSZ128rkz */ }, { /* 14459 */ 412, /* VRSQRT14PSZ256m */ }, { /* 14460 */ 337, /* VRSQRT14PSZ256mb */ }, { /* 14461 */ 338, /* VRSQRT14PSZ256mbk */ }, { /* 14462 */ 339, /* VRSQRT14PSZ256mbkz */ }, { /* 14463 */ 413, /* VRSQRT14PSZ256mk */ }, { /* 14464 */ 414, /* VRSQRT14PSZ256mkz */ }, { /* 14465 */ 415, /* VRSQRT14PSZ256r */ }, { /* 14466 */ 416, /* VRSQRT14PSZ256rk */ }, { /* 14467 */ 417, /* VRSQRT14PSZ256rkz */ }, { /* 14468 */ 418, /* VRSQRT14PSZm */ }, { /* 14469 */ 340, /* VRSQRT14PSZmb */ }, { /* 14470 */ 341, /* VRSQRT14PSZmbk */ }, { /* 14471 */ 342, /* VRSQRT14PSZmbkz */ }, { /* 14472 */ 419, /* VRSQRT14PSZmk */ }, { /* 14473 */ 420, /* VRSQRT14PSZmkz */ }, { /* 14474 */ 421, /* VRSQRT14PSZr */ }, { /* 14475 */ 425, /* VRSQRT14PSZrk */ }, { /* 14476 */ 426, /* VRSQRT14PSZrkz */ }, { /* 14477 */ 207, /* VRSQRT14SDZrm */ }, { /* 14478 */ 208, /* VRSQRT14SDZrmk */ }, { /* 14479 */ 209, /* VRSQRT14SDZrmkz */ }, { /* 14480 */ 249, /* VRSQRT14SDZrr */ }, { /* 14481 */ 250, /* VRSQRT14SDZrrk */ }, { /* 14482 */ 251, /* VRSQRT14SDZrrkz */ }, { /* 14483 */ 237, /* VRSQRT14SSZrm */ }, { /* 14484 */ 238, /* VRSQRT14SSZrmk */ }, { /* 14485 */ 239, /* VRSQRT14SSZrmkz */ }, { /* 14486 */ 255, /* VRSQRT14SSZrr */ }, { /* 14487 */ 256, /* VRSQRT14SSZrrk */ }, { /* 14488 */ 257, /* VRSQRT14SSZrrkz */ }, { /* 14489 */ 418, /* VRSQRT28PDZm */ }, { /* 14490 */ 312, /* VRSQRT28PDZmb */ }, { /* 14491 */ 313, /* VRSQRT28PDZmbk */ }, { /* 14492 */ 314, /* VRSQRT28PDZmbkz */ }, { /* 14493 */ 419, /* VRSQRT28PDZmk */ }, { /* 14494 */ 420, /* VRSQRT28PDZmkz */ }, { /* 14495 */ 421, /* VRSQRT28PDZr */ }, { /* 14496 */ 494, /* VRSQRT28PDZrb */ }, { /* 14497 */ 495, /* VRSQRT28PDZrbk */ }, { /* 14498 */ 496, /* VRSQRT28PDZrbkz */ }, { /* 14499 */ 425, /* VRSQRT28PDZrk */ }, { /* 14500 */ 426, /* VRSQRT28PDZrkz */ }, { /* 14501 */ 418, /* VRSQRT28PSZm */ }, { /* 14502 */ 340, /* VRSQRT28PSZmb */ }, { /* 14503 */ 341, /* VRSQRT28PSZmbk */ }, { /* 14504 */ 342, /* VRSQRT28PSZmbkz */ }, { /* 14505 */ 419, /* VRSQRT28PSZmk */ }, { /* 14506 */ 420, /* VRSQRT28PSZmkz */ }, { /* 14507 */ 421, /* VRSQRT28PSZr */ }, { /* 14508 */ 497, /* VRSQRT28PSZrb */ }, { /* 14509 */ 498, /* VRSQRT28PSZrbk */ }, { /* 14510 */ 499, /* VRSQRT28PSZrbkz */ }, { /* 14511 */ 425, /* VRSQRT28PSZrk */ }, { /* 14512 */ 426, /* VRSQRT28PSZrkz */ }, { /* 14513 */ 207, /* VRSQRT28SDZm */ }, { /* 14514 */ 208, /* VRSQRT28SDZmk */ }, { /* 14515 */ 209, /* VRSQRT28SDZmkz */ }, { /* 14516 */ 249, /* VRSQRT28SDZr */ }, { /* 14517 */ 249, /* VRSQRT28SDZrb */ }, { /* 14518 */ 250, /* VRSQRT28SDZrbk */ }, { /* 14519 */ 251, /* VRSQRT28SDZrbkz */ }, { /* 14520 */ 250, /* VRSQRT28SDZrk */ }, { /* 14521 */ 251, /* VRSQRT28SDZrkz */ }, { /* 14522 */ 237, /* VRSQRT28SSZm */ }, { /* 14523 */ 238, /* VRSQRT28SSZmk */ }, { /* 14524 */ 239, /* VRSQRT28SSZmkz */ }, { /* 14525 */ 255, /* VRSQRT28SSZr */ }, { /* 14526 */ 255, /* VRSQRT28SSZrb */ }, { /* 14527 */ 256, /* VRSQRT28SSZrbk */ }, { /* 14528 */ 257, /* VRSQRT28SSZrbkz */ }, { /* 14529 */ 256, /* VRSQRT28SSZrk */ }, { /* 14530 */ 257, /* VRSQRT28SSZrkz */ }, { /* 14531 */ 305, /* VRSQRTPSYm */ }, { /* 14532 */ 408, /* VRSQRTPSYr */ }, { /* 14533 */ 30, /* VRSQRTPSm */ }, { /* 14534 */ 31, /* VRSQRTPSr */ }, { /* 14535 */ 235, /* VRSQRTSSm */ }, { /* 14536 */ 0, /* */ }, { /* 14537 */ 236, /* VRSQRTSSr */ }, { /* 14538 */ 0, /* */ }, { /* 14539 */ 206, /* VSCALEFPDZ128rm */ }, { /* 14540 */ 207, /* VSCALEFPDZ128rmb */ }, { /* 14541 */ 208, /* VSCALEFPDZ128rmbk */ }, { /* 14542 */ 209, /* VSCALEFPDZ128rmbkz */ }, { /* 14543 */ 203, /* VSCALEFPDZ128rmk */ }, { /* 14544 */ 210, /* VSCALEFPDZ128rmkz */ }, { /* 14545 */ 211, /* VSCALEFPDZ128rr */ }, { /* 14546 */ 212, /* VSCALEFPDZ128rrk */ }, { /* 14547 */ 213, /* VSCALEFPDZ128rrkz */ }, { /* 14548 */ 214, /* VSCALEFPDZ256rm */ }, { /* 14549 */ 215, /* VSCALEFPDZ256rmb */ }, { /* 14550 */ 216, /* VSCALEFPDZ256rmbk */ }, { /* 14551 */ 217, /* VSCALEFPDZ256rmbkz */ }, { /* 14552 */ 218, /* VSCALEFPDZ256rmk */ }, { /* 14553 */ 219, /* VSCALEFPDZ256rmkz */ }, { /* 14554 */ 220, /* VSCALEFPDZ256rr */ }, { /* 14555 */ 221, /* VSCALEFPDZ256rrk */ }, { /* 14556 */ 222, /* VSCALEFPDZ256rrkz */ }, { /* 14557 */ 223, /* VSCALEFPDZrm */ }, { /* 14558 */ 224, /* VSCALEFPDZrmb */ }, { /* 14559 */ 225, /* VSCALEFPDZrmbk */ }, { /* 14560 */ 226, /* VSCALEFPDZrmbkz */ }, { /* 14561 */ 227, /* VSCALEFPDZrmk */ }, { /* 14562 */ 228, /* VSCALEFPDZrmkz */ }, { /* 14563 */ 229, /* VSCALEFPDZrr */ }, { /* 14564 */ 230, /* VSCALEFPDZrrb */ }, { /* 14565 */ 231, /* VSCALEFPDZrrbk */ }, { /* 14566 */ 232, /* VSCALEFPDZrrbkz */ }, { /* 14567 */ 233, /* VSCALEFPDZrrk */ }, { /* 14568 */ 234, /* VSCALEFPDZrrkz */ }, { /* 14569 */ 206, /* VSCALEFPSZ128rm */ }, { /* 14570 */ 237, /* VSCALEFPSZ128rmb */ }, { /* 14571 */ 238, /* VSCALEFPSZ128rmbk */ }, { /* 14572 */ 239, /* VSCALEFPSZ128rmbkz */ }, { /* 14573 */ 203, /* VSCALEFPSZ128rmk */ }, { /* 14574 */ 210, /* VSCALEFPSZ128rmkz */ }, { /* 14575 */ 211, /* VSCALEFPSZ128rr */ }, { /* 14576 */ 212, /* VSCALEFPSZ128rrk */ }, { /* 14577 */ 213, /* VSCALEFPSZ128rrkz */ }, { /* 14578 */ 214, /* VSCALEFPSZ256rm */ }, { /* 14579 */ 240, /* VSCALEFPSZ256rmb */ }, { /* 14580 */ 241, /* VSCALEFPSZ256rmbk */ }, { /* 14581 */ 242, /* VSCALEFPSZ256rmbkz */ }, { /* 14582 */ 218, /* VSCALEFPSZ256rmk */ }, { /* 14583 */ 219, /* VSCALEFPSZ256rmkz */ }, { /* 14584 */ 220, /* VSCALEFPSZ256rr */ }, { /* 14585 */ 221, /* VSCALEFPSZ256rrk */ }, { /* 14586 */ 222, /* VSCALEFPSZ256rrkz */ }, { /* 14587 */ 223, /* VSCALEFPSZrm */ }, { /* 14588 */ 243, /* VSCALEFPSZrmb */ }, { /* 14589 */ 244, /* VSCALEFPSZrmbk */ }, { /* 14590 */ 245, /* VSCALEFPSZrmbkz */ }, { /* 14591 */ 227, /* VSCALEFPSZrmk */ }, { /* 14592 */ 228, /* VSCALEFPSZrmkz */ }, { /* 14593 */ 229, /* VSCALEFPSZrr */ }, { /* 14594 */ 246, /* VSCALEFPSZrrb */ }, { /* 14595 */ 247, /* VSCALEFPSZrrbk */ }, { /* 14596 */ 248, /* VSCALEFPSZrrbkz */ }, { /* 14597 */ 233, /* VSCALEFPSZrrk */ }, { /* 14598 */ 234, /* VSCALEFPSZrrkz */ }, { /* 14599 */ 207, /* VSCALEFSDZrm */ }, { /* 14600 */ 208, /* VSCALEFSDZrmk */ }, { /* 14601 */ 209, /* VSCALEFSDZrmkz */ }, { /* 14602 */ 249, /* VSCALEFSDZrr */ }, { /* 14603 */ 252, /* VSCALEFSDZrrb_Int */ }, { /* 14604 */ 253, /* VSCALEFSDZrrb_Intk */ }, { /* 14605 */ 254, /* VSCALEFSDZrrb_Intkz */ }, { /* 14606 */ 250, /* VSCALEFSDZrrk */ }, { /* 14607 */ 251, /* VSCALEFSDZrrkz */ }, { /* 14608 */ 237, /* VSCALEFSSZrm */ }, { /* 14609 */ 238, /* VSCALEFSSZrmk */ }, { /* 14610 */ 239, /* VSCALEFSSZrmkz */ }, { /* 14611 */ 255, /* VSCALEFSSZrr */ }, { /* 14612 */ 258, /* VSCALEFSSZrrb_Int */ }, { /* 14613 */ 259, /* VSCALEFSSZrrb_Intk */ }, { /* 14614 */ 260, /* VSCALEFSSZrrb_Intkz */ }, { /* 14615 */ 256, /* VSCALEFSSZrrk */ }, { /* 14616 */ 257, /* VSCALEFSSZrrkz */ }, { /* 14617 */ 895, /* VSCATTERDPDZ128mr */ }, { /* 14618 */ 896, /* VSCATTERDPDZ256mr */ }, { /* 14619 */ 897, /* VSCATTERDPDZmr */ }, { /* 14620 */ 892, /* VSCATTERDPSZ128mr */ }, { /* 14621 */ 893, /* VSCATTERDPSZ256mr */ }, { /* 14622 */ 894, /* VSCATTERDPSZmr */ }, { /* 14623 */ 581, /* VSCATTERPF0DPDm */ }, { /* 14624 */ 582, /* VSCATTERPF0DPSm */ }, { /* 14625 */ 583, /* VSCATTERPF0QPDm */ }, { /* 14626 */ 583, /* VSCATTERPF0QPSm */ }, { /* 14627 */ 581, /* VSCATTERPF1DPDm */ }, { /* 14628 */ 582, /* VSCATTERPF1DPSm */ }, { /* 14629 */ 583, /* VSCATTERPF1QPDm */ }, { /* 14630 */ 583, /* VSCATTERPF1QPSm */ }, { /* 14631 */ 895, /* VSCATTERQPDZ128mr */ }, { /* 14632 */ 900, /* VSCATTERQPDZ256mr */ }, { /* 14633 */ 901, /* VSCATTERQPDZmr */ }, { /* 14634 */ 892, /* VSCATTERQPSZ128mr */ }, { /* 14635 */ 898, /* VSCATTERQPSZ256mr */ }, { /* 14636 */ 899, /* VSCATTERQPSZmr */ }, { /* 14637 */ 270, /* VSHUFF32X4Z256rmbi */ }, { /* 14638 */ 271, /* VSHUFF32X4Z256rmbik */ }, { /* 14639 */ 272, /* VSHUFF32X4Z256rmbikz */ }, { /* 14640 */ 273, /* VSHUFF32X4Z256rmi */ }, { /* 14641 */ 274, /* VSHUFF32X4Z256rmik */ }, { /* 14642 */ 275, /* VSHUFF32X4Z256rmikz */ }, { /* 14643 */ 276, /* VSHUFF32X4Z256rri */ }, { /* 14644 */ 277, /* VSHUFF32X4Z256rrik */ }, { /* 14645 */ 278, /* VSHUFF32X4Z256rrikz */ }, { /* 14646 */ 279, /* VSHUFF32X4Zrmbi */ }, { /* 14647 */ 280, /* VSHUFF32X4Zrmbik */ }, { /* 14648 */ 281, /* VSHUFF32X4Zrmbikz */ }, { /* 14649 */ 282, /* VSHUFF32X4Zrmi */ }, { /* 14650 */ 283, /* VSHUFF32X4Zrmik */ }, { /* 14651 */ 284, /* VSHUFF32X4Zrmikz */ }, { /* 14652 */ 285, /* VSHUFF32X4Zrri */ }, { /* 14653 */ 286, /* VSHUFF32X4Zrrik */ }, { /* 14654 */ 287, /* VSHUFF32X4Zrrikz */ }, { /* 14655 */ 291, /* VSHUFF64X2Z256rmbi */ }, { /* 14656 */ 292, /* VSHUFF64X2Z256rmbik */ }, { /* 14657 */ 293, /* VSHUFF64X2Z256rmbikz */ }, { /* 14658 */ 273, /* VSHUFF64X2Z256rmi */ }, { /* 14659 */ 274, /* VSHUFF64X2Z256rmik */ }, { /* 14660 */ 275, /* VSHUFF64X2Z256rmikz */ }, { /* 14661 */ 276, /* VSHUFF64X2Z256rri */ }, { /* 14662 */ 277, /* VSHUFF64X2Z256rrik */ }, { /* 14663 */ 278, /* VSHUFF64X2Z256rrikz */ }, { /* 14664 */ 294, /* VSHUFF64X2Zrmbi */ }, { /* 14665 */ 295, /* VSHUFF64X2Zrmbik */ }, { /* 14666 */ 296, /* VSHUFF64X2Zrmbikz */ }, { /* 14667 */ 282, /* VSHUFF64X2Zrmi */ }, { /* 14668 */ 283, /* VSHUFF64X2Zrmik */ }, { /* 14669 */ 284, /* VSHUFF64X2Zrmikz */ }, { /* 14670 */ 285, /* VSHUFF64X2Zrri */ }, { /* 14671 */ 286, /* VSHUFF64X2Zrrik */ }, { /* 14672 */ 287, /* VSHUFF64X2Zrrikz */ }, { /* 14673 */ 270, /* VSHUFI32X4Z256rmbi */ }, { /* 14674 */ 271, /* VSHUFI32X4Z256rmbik */ }, { /* 14675 */ 272, /* VSHUFI32X4Z256rmbikz */ }, { /* 14676 */ 273, /* VSHUFI32X4Z256rmi */ }, { /* 14677 */ 274, /* VSHUFI32X4Z256rmik */ }, { /* 14678 */ 275, /* VSHUFI32X4Z256rmikz */ }, { /* 14679 */ 276, /* VSHUFI32X4Z256rri */ }, { /* 14680 */ 277, /* VSHUFI32X4Z256rrik */ }, { /* 14681 */ 278, /* VSHUFI32X4Z256rrikz */ }, { /* 14682 */ 279, /* VSHUFI32X4Zrmbi */ }, { /* 14683 */ 280, /* VSHUFI32X4Zrmbik */ }, { /* 14684 */ 281, /* VSHUFI32X4Zrmbikz */ }, { /* 14685 */ 282, /* VSHUFI32X4Zrmi */ }, { /* 14686 */ 283, /* VSHUFI32X4Zrmik */ }, { /* 14687 */ 284, /* VSHUFI32X4Zrmikz */ }, { /* 14688 */ 285, /* VSHUFI32X4Zrri */ }, { /* 14689 */ 286, /* VSHUFI32X4Zrrik */ }, { /* 14690 */ 287, /* VSHUFI32X4Zrrikz */ }, { /* 14691 */ 291, /* VSHUFI64X2Z256rmbi */ }, { /* 14692 */ 292, /* VSHUFI64X2Z256rmbik */ }, { /* 14693 */ 293, /* VSHUFI64X2Z256rmbikz */ }, { /* 14694 */ 273, /* VSHUFI64X2Z256rmi */ }, { /* 14695 */ 274, /* VSHUFI64X2Z256rmik */ }, { /* 14696 */ 275, /* VSHUFI64X2Z256rmikz */ }, { /* 14697 */ 276, /* VSHUFI64X2Z256rri */ }, { /* 14698 */ 277, /* VSHUFI64X2Z256rrik */ }, { /* 14699 */ 278, /* VSHUFI64X2Z256rrikz */ }, { /* 14700 */ 294, /* VSHUFI64X2Zrmbi */ }, { /* 14701 */ 295, /* VSHUFI64X2Zrmbik */ }, { /* 14702 */ 296, /* VSHUFI64X2Zrmbikz */ }, { /* 14703 */ 282, /* VSHUFI64X2Zrmi */ }, { /* 14704 */ 283, /* VSHUFI64X2Zrmik */ }, { /* 14705 */ 284, /* VSHUFI64X2Zrmikz */ }, { /* 14706 */ 285, /* VSHUFI64X2Zrri */ }, { /* 14707 */ 286, /* VSHUFI64X2Zrrik */ }, { /* 14708 */ 287, /* VSHUFI64X2Zrrikz */ }, { /* 14709 */ 297, /* VSHUFPDYrmi */ }, { /* 14710 */ 298, /* VSHUFPDYrri */ }, { /* 14711 */ 288, /* VSHUFPDZ128rmbi */ }, { /* 14712 */ 289, /* VSHUFPDZ128rmbik */ }, { /* 14713 */ 290, /* VSHUFPDZ128rmbikz */ }, { /* 14714 */ 264, /* VSHUFPDZ128rmi */ }, { /* 14715 */ 265, /* VSHUFPDZ128rmik */ }, { /* 14716 */ 266, /* VSHUFPDZ128rmikz */ }, { /* 14717 */ 267, /* VSHUFPDZ128rri */ }, { /* 14718 */ 268, /* VSHUFPDZ128rrik */ }, { /* 14719 */ 269, /* VSHUFPDZ128rrikz */ }, { /* 14720 */ 291, /* VSHUFPDZ256rmbi */ }, { /* 14721 */ 292, /* VSHUFPDZ256rmbik */ }, { /* 14722 */ 293, /* VSHUFPDZ256rmbikz */ }, { /* 14723 */ 273, /* VSHUFPDZ256rmi */ }, { /* 14724 */ 274, /* VSHUFPDZ256rmik */ }, { /* 14725 */ 275, /* VSHUFPDZ256rmikz */ }, { /* 14726 */ 276, /* VSHUFPDZ256rri */ }, { /* 14727 */ 277, /* VSHUFPDZ256rrik */ }, { /* 14728 */ 278, /* VSHUFPDZ256rrikz */ }, { /* 14729 */ 294, /* VSHUFPDZrmbi */ }, { /* 14730 */ 295, /* VSHUFPDZrmbik */ }, { /* 14731 */ 296, /* VSHUFPDZrmbikz */ }, { /* 14732 */ 282, /* VSHUFPDZrmi */ }, { /* 14733 */ 283, /* VSHUFPDZrmik */ }, { /* 14734 */ 284, /* VSHUFPDZrmikz */ }, { /* 14735 */ 285, /* VSHUFPDZrri */ }, { /* 14736 */ 286, /* VSHUFPDZrrik */ }, { /* 14737 */ 287, /* VSHUFPDZrrikz */ }, { /* 14738 */ 299, /* VSHUFPDrmi */ }, { /* 14739 */ 300, /* VSHUFPDrri */ }, { /* 14740 */ 297, /* VSHUFPSYrmi */ }, { /* 14741 */ 298, /* VSHUFPSYrri */ }, { /* 14742 */ 261, /* VSHUFPSZ128rmbi */ }, { /* 14743 */ 262, /* VSHUFPSZ128rmbik */ }, { /* 14744 */ 263, /* VSHUFPSZ128rmbikz */ }, { /* 14745 */ 264, /* VSHUFPSZ128rmi */ }, { /* 14746 */ 265, /* VSHUFPSZ128rmik */ }, { /* 14747 */ 266, /* VSHUFPSZ128rmikz */ }, { /* 14748 */ 267, /* VSHUFPSZ128rri */ }, { /* 14749 */ 268, /* VSHUFPSZ128rrik */ }, { /* 14750 */ 269, /* VSHUFPSZ128rrikz */ }, { /* 14751 */ 270, /* VSHUFPSZ256rmbi */ }, { /* 14752 */ 271, /* VSHUFPSZ256rmbik */ }, { /* 14753 */ 272, /* VSHUFPSZ256rmbikz */ }, { /* 14754 */ 273, /* VSHUFPSZ256rmi */ }, { /* 14755 */ 274, /* VSHUFPSZ256rmik */ }, { /* 14756 */ 275, /* VSHUFPSZ256rmikz */ }, { /* 14757 */ 276, /* VSHUFPSZ256rri */ }, { /* 14758 */ 277, /* VSHUFPSZ256rrik */ }, { /* 14759 */ 278, /* VSHUFPSZ256rrikz */ }, { /* 14760 */ 279, /* VSHUFPSZrmbi */ }, { /* 14761 */ 280, /* VSHUFPSZrmbik */ }, { /* 14762 */ 281, /* VSHUFPSZrmbikz */ }, { /* 14763 */ 282, /* VSHUFPSZrmi */ }, { /* 14764 */ 283, /* VSHUFPSZrmik */ }, { /* 14765 */ 284, /* VSHUFPSZrmikz */ }, { /* 14766 */ 285, /* VSHUFPSZrri */ }, { /* 14767 */ 286, /* VSHUFPSZrrik */ }, { /* 14768 */ 287, /* VSHUFPSZrrikz */ }, { /* 14769 */ 299, /* VSHUFPSrmi */ }, { /* 14770 */ 300, /* VSHUFPSrri */ }, { /* 14771 */ 305, /* VSQRTPDYm */ }, { /* 14772 */ 408, /* VSQRTPDYr */ }, { /* 14773 */ 409, /* VSQRTPDZ128m */ }, { /* 14774 */ 327, /* VSQRTPDZ128mb */ }, { /* 14775 */ 328, /* VSQRTPDZ128mbk */ }, { /* 14776 */ 329, /* VSQRTPDZ128mbkz */ }, { /* 14777 */ 410, /* VSQRTPDZ128mk */ }, { /* 14778 */ 411, /* VSQRTPDZ128mkz */ }, { /* 14779 */ 330, /* VSQRTPDZ128r */ }, { /* 14780 */ 331, /* VSQRTPDZ128rk */ }, { /* 14781 */ 332, /* VSQRTPDZ128rkz */ }, { /* 14782 */ 412, /* VSQRTPDZ256m */ }, { /* 14783 */ 306, /* VSQRTPDZ256mb */ }, { /* 14784 */ 307, /* VSQRTPDZ256mbk */ }, { /* 14785 */ 308, /* VSQRTPDZ256mbkz */ }, { /* 14786 */ 413, /* VSQRTPDZ256mk */ }, { /* 14787 */ 414, /* VSQRTPDZ256mkz */ }, { /* 14788 */ 415, /* VSQRTPDZ256r */ }, { /* 14789 */ 416, /* VSQRTPDZ256rk */ }, { /* 14790 */ 417, /* VSQRTPDZ256rkz */ }, { /* 14791 */ 418, /* VSQRTPDZm */ }, { /* 14792 */ 312, /* VSQRTPDZmb */ }, { /* 14793 */ 313, /* VSQRTPDZmbk */ }, { /* 14794 */ 314, /* VSQRTPDZmbkz */ }, { /* 14795 */ 419, /* VSQRTPDZmk */ }, { /* 14796 */ 420, /* VSQRTPDZmkz */ }, { /* 14797 */ 421, /* VSQRTPDZr */ }, { /* 14798 */ 443, /* VSQRTPDZrb */ }, { /* 14799 */ 444, /* VSQRTPDZrbk */ }, { /* 14800 */ 445, /* VSQRTPDZrbkz */ }, { /* 14801 */ 425, /* VSQRTPDZrk */ }, { /* 14802 */ 426, /* VSQRTPDZrkz */ }, { /* 14803 */ 30, /* VSQRTPDm */ }, { /* 14804 */ 31, /* VSQRTPDr */ }, { /* 14805 */ 305, /* VSQRTPSYm */ }, { /* 14806 */ 408, /* VSQRTPSYr */ }, { /* 14807 */ 409, /* VSQRTPSZ128m */ }, { /* 14808 */ 334, /* VSQRTPSZ128mb */ }, { /* 14809 */ 335, /* VSQRTPSZ128mbk */ }, { /* 14810 */ 336, /* VSQRTPSZ128mbkz */ }, { /* 14811 */ 410, /* VSQRTPSZ128mk */ }, { /* 14812 */ 411, /* VSQRTPSZ128mkz */ }, { /* 14813 */ 330, /* VSQRTPSZ128r */ }, { /* 14814 */ 331, /* VSQRTPSZ128rk */ }, { /* 14815 */ 332, /* VSQRTPSZ128rkz */ }, { /* 14816 */ 412, /* VSQRTPSZ256m */ }, { /* 14817 */ 337, /* VSQRTPSZ256mb */ }, { /* 14818 */ 338, /* VSQRTPSZ256mbk */ }, { /* 14819 */ 339, /* VSQRTPSZ256mbkz */ }, { /* 14820 */ 413, /* VSQRTPSZ256mk */ }, { /* 14821 */ 414, /* VSQRTPSZ256mkz */ }, { /* 14822 */ 415, /* VSQRTPSZ256r */ }, { /* 14823 */ 416, /* VSQRTPSZ256rk */ }, { /* 14824 */ 417, /* VSQRTPSZ256rkz */ }, { /* 14825 */ 418, /* VSQRTPSZm */ }, { /* 14826 */ 340, /* VSQRTPSZmb */ }, { /* 14827 */ 341, /* VSQRTPSZmbk */ }, { /* 14828 */ 342, /* VSQRTPSZmbkz */ }, { /* 14829 */ 419, /* VSQRTPSZmk */ }, { /* 14830 */ 420, /* VSQRTPSZmkz */ }, { /* 14831 */ 421, /* VSQRTPSZr */ }, { /* 14832 */ 422, /* VSQRTPSZrb */ }, { /* 14833 */ 423, /* VSQRTPSZrbk */ }, { /* 14834 */ 424, /* VSQRTPSZrbkz */ }, { /* 14835 */ 425, /* VSQRTPSZrk */ }, { /* 14836 */ 426, /* VSQRTPSZrkz */ }, { /* 14837 */ 30, /* VSQRTPSm */ }, { /* 14838 */ 31, /* VSQRTPSr */ }, { /* 14839 */ 0, /* */ }, { /* 14840 */ 207, /* VSQRTSDZm_Int */ }, { /* 14841 */ 208, /* VSQRTSDZm_Intk */ }, { /* 14842 */ 209, /* VSQRTSDZm_Intkz */ }, { /* 14843 */ 0, /* */ }, { /* 14844 */ 249, /* VSQRTSDZr_Int */ }, { /* 14845 */ 250, /* VSQRTSDZr_Intk */ }, { /* 14846 */ 251, /* VSQRTSDZr_Intkz */ }, { /* 14847 */ 252, /* VSQRTSDZrb_Int */ }, { /* 14848 */ 253, /* VSQRTSDZrb_Intk */ }, { /* 14849 */ 254, /* VSQRTSDZrb_Intkz */ }, { /* 14850 */ 235, /* VSQRTSDm */ }, { /* 14851 */ 0, /* */ }, { /* 14852 */ 236, /* VSQRTSDr */ }, { /* 14853 */ 0, /* */ }, { /* 14854 */ 0, /* */ }, { /* 14855 */ 237, /* VSQRTSSZm_Int */ }, { /* 14856 */ 238, /* VSQRTSSZm_Intk */ }, { /* 14857 */ 239, /* VSQRTSSZm_Intkz */ }, { /* 14858 */ 0, /* */ }, { /* 14859 */ 255, /* VSQRTSSZr_Int */ }, { /* 14860 */ 256, /* VSQRTSSZr_Intk */ }, { /* 14861 */ 257, /* VSQRTSSZr_Intkz */ }, { /* 14862 */ 258, /* VSQRTSSZrb_Int */ }, { /* 14863 */ 259, /* VSQRTSSZrb_Intk */ }, { /* 14864 */ 260, /* VSQRTSSZrb_Intkz */ }, { /* 14865 */ 235, /* VSQRTSSm */ }, { /* 14866 */ 0, /* */ }, { /* 14867 */ 236, /* VSQRTSSr */ }, { /* 14868 */ 0, /* */ }, { /* 14869 */ 28, /* VSTMXCSR */ }, { /* 14870 */ 204, /* VSUBPDYrm */ }, { /* 14871 */ 205, /* VSUBPDYrr */ }, { /* 14872 */ 206, /* VSUBPDZ128rm */ }, { /* 14873 */ 207, /* VSUBPDZ128rmb */ }, { /* 14874 */ 208, /* VSUBPDZ128rmbk */ }, { /* 14875 */ 209, /* VSUBPDZ128rmbkz */ }, { /* 14876 */ 203, /* VSUBPDZ128rmk */ }, { /* 14877 */ 210, /* VSUBPDZ128rmkz */ }, { /* 14878 */ 211, /* VSUBPDZ128rr */ }, { /* 14879 */ 212, /* VSUBPDZ128rrk */ }, { /* 14880 */ 213, /* VSUBPDZ128rrkz */ }, { /* 14881 */ 214, /* VSUBPDZ256rm */ }, { /* 14882 */ 215, /* VSUBPDZ256rmb */ }, { /* 14883 */ 216, /* VSUBPDZ256rmbk */ }, { /* 14884 */ 217, /* VSUBPDZ256rmbkz */ }, { /* 14885 */ 218, /* VSUBPDZ256rmk */ }, { /* 14886 */ 219, /* VSUBPDZ256rmkz */ }, { /* 14887 */ 220, /* VSUBPDZ256rr */ }, { /* 14888 */ 221, /* VSUBPDZ256rrk */ }, { /* 14889 */ 222, /* VSUBPDZ256rrkz */ }, { /* 14890 */ 223, /* VSUBPDZrm */ }, { /* 14891 */ 224, /* VSUBPDZrmb */ }, { /* 14892 */ 225, /* VSUBPDZrmbk */ }, { /* 14893 */ 226, /* VSUBPDZrmbkz */ }, { /* 14894 */ 227, /* VSUBPDZrmk */ }, { /* 14895 */ 228, /* VSUBPDZrmkz */ }, { /* 14896 */ 229, /* VSUBPDZrr */ }, { /* 14897 */ 230, /* VSUBPDZrrb */ }, { /* 14898 */ 231, /* VSUBPDZrrbk */ }, { /* 14899 */ 232, /* VSUBPDZrrbkz */ }, { /* 14900 */ 233, /* VSUBPDZrrk */ }, { /* 14901 */ 234, /* VSUBPDZrrkz */ }, { /* 14902 */ 235, /* VSUBPDrm */ }, { /* 14903 */ 236, /* VSUBPDrr */ }, { /* 14904 */ 204, /* VSUBPSYrm */ }, { /* 14905 */ 205, /* VSUBPSYrr */ }, { /* 14906 */ 206, /* VSUBPSZ128rm */ }, { /* 14907 */ 237, /* VSUBPSZ128rmb */ }, { /* 14908 */ 238, /* VSUBPSZ128rmbk */ }, { /* 14909 */ 239, /* VSUBPSZ128rmbkz */ }, { /* 14910 */ 203, /* VSUBPSZ128rmk */ }, { /* 14911 */ 210, /* VSUBPSZ128rmkz */ }, { /* 14912 */ 211, /* VSUBPSZ128rr */ }, { /* 14913 */ 212, /* VSUBPSZ128rrk */ }, { /* 14914 */ 213, /* VSUBPSZ128rrkz */ }, { /* 14915 */ 214, /* VSUBPSZ256rm */ }, { /* 14916 */ 240, /* VSUBPSZ256rmb */ }, { /* 14917 */ 241, /* VSUBPSZ256rmbk */ }, { /* 14918 */ 242, /* VSUBPSZ256rmbkz */ }, { /* 14919 */ 218, /* VSUBPSZ256rmk */ }, { /* 14920 */ 219, /* VSUBPSZ256rmkz */ }, { /* 14921 */ 220, /* VSUBPSZ256rr */ }, { /* 14922 */ 221, /* VSUBPSZ256rrk */ }, { /* 14923 */ 222, /* VSUBPSZ256rrkz */ }, { /* 14924 */ 223, /* VSUBPSZrm */ }, { /* 14925 */ 243, /* VSUBPSZrmb */ }, { /* 14926 */ 244, /* VSUBPSZrmbk */ }, { /* 14927 */ 245, /* VSUBPSZrmbkz */ }, { /* 14928 */ 227, /* VSUBPSZrmk */ }, { /* 14929 */ 228, /* VSUBPSZrmkz */ }, { /* 14930 */ 229, /* VSUBPSZrr */ }, { /* 14931 */ 246, /* VSUBPSZrrb */ }, { /* 14932 */ 247, /* VSUBPSZrrbk */ }, { /* 14933 */ 248, /* VSUBPSZrrbkz */ }, { /* 14934 */ 233, /* VSUBPSZrrk */ }, { /* 14935 */ 234, /* VSUBPSZrrkz */ }, { /* 14936 */ 235, /* VSUBPSrm */ }, { /* 14937 */ 236, /* VSUBPSrr */ }, { /* 14938 */ 0, /* */ }, { /* 14939 */ 207, /* VSUBSDZrm_Int */ }, { /* 14940 */ 208, /* VSUBSDZrm_Intk */ }, { /* 14941 */ 209, /* VSUBSDZrm_Intkz */ }, { /* 14942 */ 0, /* */ }, { /* 14943 */ 249, /* VSUBSDZrr_Int */ }, { /* 14944 */ 250, /* VSUBSDZrr_Intk */ }, { /* 14945 */ 251, /* VSUBSDZrr_Intkz */ }, { /* 14946 */ 252, /* VSUBSDZrrb_Int */ }, { /* 14947 */ 253, /* VSUBSDZrrb_Intk */ }, { /* 14948 */ 254, /* VSUBSDZrrb_Intkz */ }, { /* 14949 */ 235, /* VSUBSDrm */ }, { /* 14950 */ 0, /* */ }, { /* 14951 */ 236, /* VSUBSDrr */ }, { /* 14952 */ 0, /* */ }, { /* 14953 */ 0, /* */ }, { /* 14954 */ 237, /* VSUBSSZrm_Int */ }, { /* 14955 */ 238, /* VSUBSSZrm_Intk */ }, { /* 14956 */ 239, /* VSUBSSZrm_Intkz */ }, { /* 14957 */ 0, /* */ }, { /* 14958 */ 255, /* VSUBSSZrr_Int */ }, { /* 14959 */ 256, /* VSUBSSZrr_Intk */ }, { /* 14960 */ 257, /* VSUBSSZrr_Intkz */ }, { /* 14961 */ 258, /* VSUBSSZrrb_Int */ }, { /* 14962 */ 259, /* VSUBSSZrrb_Intk */ }, { /* 14963 */ 260, /* VSUBSSZrrb_Intkz */ }, { /* 14964 */ 235, /* VSUBSSrm */ }, { /* 14965 */ 0, /* */ }, { /* 14966 */ 236, /* VSUBSSrr */ }, { /* 14967 */ 0, /* */ }, { /* 14968 */ 305, /* VTESTPDYrm */ }, { /* 14969 */ 408, /* VTESTPDYrr */ }, { /* 14970 */ 30, /* VTESTPDrm */ }, { /* 14971 */ 31, /* VTESTPDrr */ }, { /* 14972 */ 305, /* VTESTPSYrm */ }, { /* 14973 */ 408, /* VTESTPSYrr */ }, { /* 14974 */ 30, /* VTESTPSrm */ }, { /* 14975 */ 31, /* VTESTPSrr */ }, { /* 14976 */ 327, /* VUCOMISDZrm */ }, { /* 14977 */ 0, /* */ }, { /* 14978 */ 377, /* VUCOMISDZrr */ }, { /* 14979 */ 0, /* */ }, { /* 14980 */ 377, /* VUCOMISDZrrb */ }, { /* 14981 */ 30, /* VUCOMISDrm */ }, { /* 14982 */ 0, /* */ }, { /* 14983 */ 31, /* VUCOMISDrr */ }, { /* 14984 */ 0, /* */ }, { /* 14985 */ 334, /* VUCOMISSZrm */ }, { /* 14986 */ 0, /* */ }, { /* 14987 */ 378, /* VUCOMISSZrr */ }, { /* 14988 */ 0, /* */ }, { /* 14989 */ 378, /* VUCOMISSZrrb */ }, { /* 14990 */ 30, /* VUCOMISSrm */ }, { /* 14991 */ 0, /* */ }, { /* 14992 */ 31, /* VUCOMISSrr */ }, { /* 14993 */ 0, /* */ }, { /* 14994 */ 204, /* VUNPCKHPDYrm */ }, { /* 14995 */ 205, /* VUNPCKHPDYrr */ }, { /* 14996 */ 206, /* VUNPCKHPDZ128rm */ }, { /* 14997 */ 207, /* VUNPCKHPDZ128rmb */ }, { /* 14998 */ 208, /* VUNPCKHPDZ128rmbk */ }, { /* 14999 */ 209, /* VUNPCKHPDZ128rmbkz */ }, { /* 15000 */ 203, /* VUNPCKHPDZ128rmk */ }, { /* 15001 */ 210, /* VUNPCKHPDZ128rmkz */ }, { /* 15002 */ 211, /* VUNPCKHPDZ128rr */ }, { /* 15003 */ 212, /* VUNPCKHPDZ128rrk */ }, { /* 15004 */ 213, /* VUNPCKHPDZ128rrkz */ }, { /* 15005 */ 214, /* VUNPCKHPDZ256rm */ }, { /* 15006 */ 215, /* VUNPCKHPDZ256rmb */ }, { /* 15007 */ 216, /* VUNPCKHPDZ256rmbk */ }, { /* 15008 */ 217, /* VUNPCKHPDZ256rmbkz */ }, { /* 15009 */ 218, /* VUNPCKHPDZ256rmk */ }, { /* 15010 */ 219, /* VUNPCKHPDZ256rmkz */ }, { /* 15011 */ 220, /* VUNPCKHPDZ256rr */ }, { /* 15012 */ 221, /* VUNPCKHPDZ256rrk */ }, { /* 15013 */ 222, /* VUNPCKHPDZ256rrkz */ }, { /* 15014 */ 223, /* VUNPCKHPDZrm */ }, { /* 15015 */ 224, /* VUNPCKHPDZrmb */ }, { /* 15016 */ 225, /* VUNPCKHPDZrmbk */ }, { /* 15017 */ 226, /* VUNPCKHPDZrmbkz */ }, { /* 15018 */ 227, /* VUNPCKHPDZrmk */ }, { /* 15019 */ 228, /* VUNPCKHPDZrmkz */ }, { /* 15020 */ 229, /* VUNPCKHPDZrr */ }, { /* 15021 */ 233, /* VUNPCKHPDZrrk */ }, { /* 15022 */ 234, /* VUNPCKHPDZrrkz */ }, { /* 15023 */ 235, /* VUNPCKHPDrm */ }, { /* 15024 */ 236, /* VUNPCKHPDrr */ }, { /* 15025 */ 204, /* VUNPCKHPSYrm */ }, { /* 15026 */ 205, /* VUNPCKHPSYrr */ }, { /* 15027 */ 206, /* VUNPCKHPSZ128rm */ }, { /* 15028 */ 237, /* VUNPCKHPSZ128rmb */ }, { /* 15029 */ 238, /* VUNPCKHPSZ128rmbk */ }, { /* 15030 */ 239, /* VUNPCKHPSZ128rmbkz */ }, { /* 15031 */ 203, /* VUNPCKHPSZ128rmk */ }, { /* 15032 */ 210, /* VUNPCKHPSZ128rmkz */ }, { /* 15033 */ 211, /* VUNPCKHPSZ128rr */ }, { /* 15034 */ 212, /* VUNPCKHPSZ128rrk */ }, { /* 15035 */ 213, /* VUNPCKHPSZ128rrkz */ }, { /* 15036 */ 214, /* VUNPCKHPSZ256rm */ }, { /* 15037 */ 240, /* VUNPCKHPSZ256rmb */ }, { /* 15038 */ 241, /* VUNPCKHPSZ256rmbk */ }, { /* 15039 */ 242, /* VUNPCKHPSZ256rmbkz */ }, { /* 15040 */ 218, /* VUNPCKHPSZ256rmk */ }, { /* 15041 */ 219, /* VUNPCKHPSZ256rmkz */ }, { /* 15042 */ 220, /* VUNPCKHPSZ256rr */ }, { /* 15043 */ 221, /* VUNPCKHPSZ256rrk */ }, { /* 15044 */ 222, /* VUNPCKHPSZ256rrkz */ }, { /* 15045 */ 223, /* VUNPCKHPSZrm */ }, { /* 15046 */ 243, /* VUNPCKHPSZrmb */ }, { /* 15047 */ 244, /* VUNPCKHPSZrmbk */ }, { /* 15048 */ 245, /* VUNPCKHPSZrmbkz */ }, { /* 15049 */ 227, /* VUNPCKHPSZrmk */ }, { /* 15050 */ 228, /* VUNPCKHPSZrmkz */ }, { /* 15051 */ 229, /* VUNPCKHPSZrr */ }, { /* 15052 */ 233, /* VUNPCKHPSZrrk */ }, { /* 15053 */ 234, /* VUNPCKHPSZrrkz */ }, { /* 15054 */ 235, /* VUNPCKHPSrm */ }, { /* 15055 */ 236, /* VUNPCKHPSrr */ }, { /* 15056 */ 204, /* VUNPCKLPDYrm */ }, { /* 15057 */ 205, /* VUNPCKLPDYrr */ }, { /* 15058 */ 206, /* VUNPCKLPDZ128rm */ }, { /* 15059 */ 207, /* VUNPCKLPDZ128rmb */ }, { /* 15060 */ 208, /* VUNPCKLPDZ128rmbk */ }, { /* 15061 */ 209, /* VUNPCKLPDZ128rmbkz */ }, { /* 15062 */ 203, /* VUNPCKLPDZ128rmk */ }, { /* 15063 */ 210, /* VUNPCKLPDZ128rmkz */ }, { /* 15064 */ 211, /* VUNPCKLPDZ128rr */ }, { /* 15065 */ 212, /* VUNPCKLPDZ128rrk */ }, { /* 15066 */ 213, /* VUNPCKLPDZ128rrkz */ }, { /* 15067 */ 214, /* VUNPCKLPDZ256rm */ }, { /* 15068 */ 215, /* VUNPCKLPDZ256rmb */ }, { /* 15069 */ 216, /* VUNPCKLPDZ256rmbk */ }, { /* 15070 */ 217, /* VUNPCKLPDZ256rmbkz */ }, { /* 15071 */ 218, /* VUNPCKLPDZ256rmk */ }, { /* 15072 */ 219, /* VUNPCKLPDZ256rmkz */ }, { /* 15073 */ 220, /* VUNPCKLPDZ256rr */ }, { /* 15074 */ 221, /* VUNPCKLPDZ256rrk */ }, { /* 15075 */ 222, /* VUNPCKLPDZ256rrkz */ }, { /* 15076 */ 223, /* VUNPCKLPDZrm */ }, { /* 15077 */ 224, /* VUNPCKLPDZrmb */ }, { /* 15078 */ 225, /* VUNPCKLPDZrmbk */ }, { /* 15079 */ 226, /* VUNPCKLPDZrmbkz */ }, { /* 15080 */ 227, /* VUNPCKLPDZrmk */ }, { /* 15081 */ 228, /* VUNPCKLPDZrmkz */ }, { /* 15082 */ 229, /* VUNPCKLPDZrr */ }, { /* 15083 */ 233, /* VUNPCKLPDZrrk */ }, { /* 15084 */ 234, /* VUNPCKLPDZrrkz */ }, { /* 15085 */ 235, /* VUNPCKLPDrm */ }, { /* 15086 */ 236, /* VUNPCKLPDrr */ }, { /* 15087 */ 204, /* VUNPCKLPSYrm */ }, { /* 15088 */ 205, /* VUNPCKLPSYrr */ }, { /* 15089 */ 206, /* VUNPCKLPSZ128rm */ }, { /* 15090 */ 237, /* VUNPCKLPSZ128rmb */ }, { /* 15091 */ 238, /* VUNPCKLPSZ128rmbk */ }, { /* 15092 */ 239, /* VUNPCKLPSZ128rmbkz */ }, { /* 15093 */ 203, /* VUNPCKLPSZ128rmk */ }, { /* 15094 */ 210, /* VUNPCKLPSZ128rmkz */ }, { /* 15095 */ 211, /* VUNPCKLPSZ128rr */ }, { /* 15096 */ 212, /* VUNPCKLPSZ128rrk */ }, { /* 15097 */ 213, /* VUNPCKLPSZ128rrkz */ }, { /* 15098 */ 214, /* VUNPCKLPSZ256rm */ }, { /* 15099 */ 240, /* VUNPCKLPSZ256rmb */ }, { /* 15100 */ 241, /* VUNPCKLPSZ256rmbk */ }, { /* 15101 */ 242, /* VUNPCKLPSZ256rmbkz */ }, { /* 15102 */ 218, /* VUNPCKLPSZ256rmk */ }, { /* 15103 */ 219, /* VUNPCKLPSZ256rmkz */ }, { /* 15104 */ 220, /* VUNPCKLPSZ256rr */ }, { /* 15105 */ 221, /* VUNPCKLPSZ256rrk */ }, { /* 15106 */ 222, /* VUNPCKLPSZ256rrkz */ }, { /* 15107 */ 223, /* VUNPCKLPSZrm */ }, { /* 15108 */ 243, /* VUNPCKLPSZrmb */ }, { /* 15109 */ 244, /* VUNPCKLPSZrmbk */ }, { /* 15110 */ 245, /* VUNPCKLPSZrmbkz */ }, { /* 15111 */ 227, /* VUNPCKLPSZrmk */ }, { /* 15112 */ 228, /* VUNPCKLPSZrmkz */ }, { /* 15113 */ 229, /* VUNPCKLPSZrr */ }, { /* 15114 */ 233, /* VUNPCKLPSZrrk */ }, { /* 15115 */ 234, /* VUNPCKLPSZrrkz */ }, { /* 15116 */ 235, /* VUNPCKLPSrm */ }, { /* 15117 */ 236, /* VUNPCKLPSrr */ }, { /* 15118 */ 204, /* VXORPDYrm */ }, { /* 15119 */ 205, /* VXORPDYrr */ }, { /* 15120 */ 206, /* VXORPDZ128rm */ }, { /* 15121 */ 207, /* VXORPDZ128rmb */ }, { /* 15122 */ 208, /* VXORPDZ128rmbk */ }, { /* 15123 */ 209, /* VXORPDZ128rmbkz */ }, { /* 15124 */ 203, /* VXORPDZ128rmk */ }, { /* 15125 */ 210, /* VXORPDZ128rmkz */ }, { /* 15126 */ 211, /* VXORPDZ128rr */ }, { /* 15127 */ 212, /* VXORPDZ128rrk */ }, { /* 15128 */ 213, /* VXORPDZ128rrkz */ }, { /* 15129 */ 214, /* VXORPDZ256rm */ }, { /* 15130 */ 215, /* VXORPDZ256rmb */ }, { /* 15131 */ 216, /* VXORPDZ256rmbk */ }, { /* 15132 */ 217, /* VXORPDZ256rmbkz */ }, { /* 15133 */ 218, /* VXORPDZ256rmk */ }, { /* 15134 */ 219, /* VXORPDZ256rmkz */ }, { /* 15135 */ 220, /* VXORPDZ256rr */ }, { /* 15136 */ 221, /* VXORPDZ256rrk */ }, { /* 15137 */ 222, /* VXORPDZ256rrkz */ }, { /* 15138 */ 223, /* VXORPDZrm */ }, { /* 15139 */ 224, /* VXORPDZrmb */ }, { /* 15140 */ 225, /* VXORPDZrmbk */ }, { /* 15141 */ 226, /* VXORPDZrmbkz */ }, { /* 15142 */ 227, /* VXORPDZrmk */ }, { /* 15143 */ 228, /* VXORPDZrmkz */ }, { /* 15144 */ 229, /* VXORPDZrr */ }, { /* 15145 */ 233, /* VXORPDZrrk */ }, { /* 15146 */ 234, /* VXORPDZrrkz */ }, { /* 15147 */ 235, /* VXORPDrm */ }, { /* 15148 */ 236, /* VXORPDrr */ }, { /* 15149 */ 204, /* VXORPSYrm */ }, { /* 15150 */ 205, /* VXORPSYrr */ }, { /* 15151 */ 206, /* VXORPSZ128rm */ }, { /* 15152 */ 237, /* VXORPSZ128rmb */ }, { /* 15153 */ 238, /* VXORPSZ128rmbk */ }, { /* 15154 */ 239, /* VXORPSZ128rmbkz */ }, { /* 15155 */ 203, /* VXORPSZ128rmk */ }, { /* 15156 */ 210, /* VXORPSZ128rmkz */ }, { /* 15157 */ 211, /* VXORPSZ128rr */ }, { /* 15158 */ 212, /* VXORPSZ128rrk */ }, { /* 15159 */ 213, /* VXORPSZ128rrkz */ }, { /* 15160 */ 214, /* VXORPSZ256rm */ }, { /* 15161 */ 240, /* VXORPSZ256rmb */ }, { /* 15162 */ 241, /* VXORPSZ256rmbk */ }, { /* 15163 */ 242, /* VXORPSZ256rmbkz */ }, { /* 15164 */ 218, /* VXORPSZ256rmk */ }, { /* 15165 */ 219, /* VXORPSZ256rmkz */ }, { /* 15166 */ 220, /* VXORPSZ256rr */ }, { /* 15167 */ 221, /* VXORPSZ256rrk */ }, { /* 15168 */ 222, /* VXORPSZ256rrkz */ }, { /* 15169 */ 223, /* VXORPSZrm */ }, { /* 15170 */ 243, /* VXORPSZrmb */ }, { /* 15171 */ 244, /* VXORPSZrmbk */ }, { /* 15172 */ 245, /* VXORPSZrmbkz */ }, { /* 15173 */ 227, /* VXORPSZrmk */ }, { /* 15174 */ 228, /* VXORPSZrmkz */ }, { /* 15175 */ 229, /* VXORPSZrr */ }, { /* 15176 */ 233, /* VXORPSZrrk */ }, { /* 15177 */ 234, /* VXORPSZrrkz */ }, { /* 15178 */ 235, /* VXORPSrm */ }, { /* 15179 */ 236, /* VXORPSrr */ }, { /* 15180 */ 0, /* VZEROALL */ }, { /* 15181 */ 0, /* VZEROUPPER */ }, { /* 15182 */ 0, /* WAIT */ }, { /* 15183 */ 0, /* WBINVD */ }, { /* 15184 */ 0, /* WBNOINVD */ }, { /* 15185 */ 108, /* WRFSBASE */ }, { /* 15186 */ 72, /* WRFSBASE64 */ }, { /* 15187 */ 108, /* WRGSBASE */ }, { /* 15188 */ 72, /* WRGSBASE64 */ }, { /* 15189 */ 0, /* WRMSR */ }, { /* 15190 */ 0, /* WRPKRUr */ }, { /* 15191 */ 172, /* WRSSD */ }, { /* 15192 */ 13, /* WRSSQ */ }, { /* 15193 */ 172, /* WRUSSD */ }, { /* 15194 */ 13, /* WRUSSQ */ }, { /* 15195 */ 1, /* XABORT */ }, { /* 15196 */ 0, /* */ }, { /* 15197 */ 8, /* XADD16rm */ }, { /* 15198 */ 920, /* XADD16rr */ }, { /* 15199 */ 8, /* XADD32rm */ }, { /* 15200 */ 920, /* XADD32rr */ }, { /* 15201 */ 16, /* XADD64rm */ }, { /* 15202 */ 921, /* XADD64rr */ }, { /* 15203 */ 21, /* XADD8rm */ }, { /* 15204 */ 922, /* XADD8rr */ }, { /* 15205 */ 112, /* XBEGIN_2 */ }, { /* 15206 */ 112, /* XBEGIN_4 */ }, { /* 15207 */ 64, /* XCHG16ar */ }, { /* 15208 */ 8, /* XCHG16rm */ }, { /* 15209 */ 923, /* XCHG16rr */ }, { /* 15210 */ 64, /* XCHG32ar */ }, { /* 15211 */ 8, /* XCHG32rm */ }, { /* 15212 */ 923, /* XCHG32rr */ }, { /* 15213 */ 65, /* XCHG64ar */ }, { /* 15214 */ 16, /* XCHG64rm */ }, { /* 15215 */ 924, /* XCHG64rr */ }, { /* 15216 */ 21, /* XCHG8rm */ }, { /* 15217 */ 925, /* XCHG8rr */ }, { /* 15218 */ 29, /* XCH_F */ }, { /* 15219 */ 0, /* XCRYPTCBC */ }, { /* 15220 */ 0, /* XCRYPTCFB */ }, { /* 15221 */ 0, /* XCRYPTCTR */ }, { /* 15222 */ 0, /* XCRYPTECB */ }, { /* 15223 */ 0, /* XCRYPTOFB */ }, { /* 15224 */ 0, /* XEND */ }, { /* 15225 */ 0, /* XGETBV */ }, { /* 15226 */ 0, /* XLAT */ }, { /* 15227 */ 2, /* XOR16i16 */ }, { /* 15228 */ 3, /* XOR16mi */ }, { /* 15229 */ 4, /* XOR16mi8 */ }, { /* 15230 */ 5, /* XOR16mr */ }, { /* 15231 */ 6, /* XOR16ri */ }, { /* 15232 */ 7, /* XOR16ri8 */ }, { /* 15233 */ 8, /* XOR16rm */ }, { /* 15234 */ 9, /* XOR16rr */ }, { /* 15235 */ 10, /* XOR16rr_REV */ }, { /* 15236 */ 2, /* XOR32i32 */ }, { /* 15237 */ 3, /* XOR32mi */ }, { /* 15238 */ 4, /* XOR32mi8 */ }, { /* 15239 */ 5, /* XOR32mr */ }, { /* 15240 */ 6, /* XOR32ri */ }, { /* 15241 */ 7, /* XOR32ri8 */ }, { /* 15242 */ 8, /* XOR32rm */ }, { /* 15243 */ 9, /* XOR32rr */ }, { /* 15244 */ 10, /* XOR32rr_REV */ }, { /* 15245 */ 11, /* XOR64i32 */ }, { /* 15246 */ 12, /* XOR64mi32 */ }, { /* 15247 */ 4, /* XOR64mi8 */ }, { /* 15248 */ 13, /* XOR64mr */ }, { /* 15249 */ 14, /* XOR64ri32 */ }, { /* 15250 */ 15, /* XOR64ri8 */ }, { /* 15251 */ 16, /* XOR64rm */ }, { /* 15252 */ 17, /* XOR64rr */ }, { /* 15253 */ 18, /* XOR64rr_REV */ }, { /* 15254 */ 1, /* XOR8i8 */ }, { /* 15255 */ 4, /* XOR8mi */ }, { /* 15256 */ 4, /* XOR8mi8 */ }, { /* 15257 */ 19, /* XOR8mr */ }, { /* 15258 */ 20, /* XOR8ri */ }, { /* 15259 */ 20, /* XOR8ri8 */ }, { /* 15260 */ 21, /* XOR8rm */ }, { /* 15261 */ 22, /* XOR8rr */ }, { /* 15262 */ 23, /* XOR8rr_REV */ }, { /* 15263 */ 26, /* XORPDrm */ }, { /* 15264 */ 27, /* XORPDrr */ }, { /* 15265 */ 26, /* XORPSrm */ }, { /* 15266 */ 27, /* XORPSrr */ }, { /* 15267 */ 0, /* */ }, { /* 15268 */ 28, /* XRSTOR */ }, { /* 15269 */ 28, /* XRSTOR64 */ }, { /* 15270 */ 28, /* XRSTORS */ }, { /* 15271 */ 28, /* XRSTORS64 */ }, { /* 15272 */ 28, /* XSAVE */ }, { /* 15273 */ 28, /* XSAVE64 */ }, { /* 15274 */ 28, /* XSAVEC */ }, { /* 15275 */ 28, /* XSAVEC64 */ }, { /* 15276 */ 28, /* XSAVEOPT */ }, { /* 15277 */ 28, /* XSAVEOPT64 */ }, { /* 15278 */ 28, /* XSAVES */ }, { /* 15279 */ 28, /* XSAVES64 */ }, { /* 15280 */ 0, /* XSETBV */ }, { /* 15281 */ 0, /* XSHA1 */ }, { /* 15282 */ 0, /* XSHA256 */ }, { /* 15283 */ 0, /* XSTORE */ }, { /* 15284 */ 0, /* XTEST */ }, }; static const uint8_t x86DisassemblerContexts[16384] = { IC, /* 0 */ IC_64BIT, /* 1 */ IC_XS, /* 2 */ IC_64BIT_XS, /* 3 */ IC_XD, /* 4 */ IC_64BIT_XD, /* 5 */ IC_XS, /* 6 */ IC_64BIT_XS, /* 7 */ IC, /* 8 */ IC_64BIT_REXW, /* 9 */ IC_XS, /* 10 */ IC_64BIT_REXW_XS, /* 11 */ IC_XD, /* 12 */ IC_64BIT_REXW_XD, /* 13 */ IC_XS, /* 14 */ IC_64BIT_REXW_XS, /* 15 */ IC_OPSIZE, /* 16 */ IC_64BIT_OPSIZE, /* 17 */ IC_XS_OPSIZE, /* 18 */ IC_64BIT_XS_OPSIZE, /* 19 */ IC_XD_OPSIZE, /* 20 */ IC_64BIT_XD_OPSIZE, /* 21 */ IC_XS_OPSIZE, /* 22 */ IC_64BIT_XD_OPSIZE, /* 23 */ IC_OPSIZE, /* 24 */ IC_64BIT_REXW_OPSIZE, /* 25 */ IC_XS_OPSIZE, /* 26 */ IC_64BIT_REXW_XS, /* 27 */ IC_XD_OPSIZE, /* 28 */ IC_64BIT_REXW_XD, /* 29 */ IC_XS_OPSIZE, /* 30 */ IC_64BIT_REXW_XS, /* 31 */ IC_ADSIZE, /* 32 */ IC_64BIT_ADSIZE, /* 33 */ IC_XS_ADSIZE, /* 34 */ IC_64BIT_XS_ADSIZE, /* 35 */ IC_XD_ADSIZE, /* 36 */ IC_64BIT_XD_ADSIZE, /* 37 */ IC_XS_ADSIZE, /* 38 */ IC_64BIT_XD_ADSIZE, /* 39 */ IC_ADSIZE, /* 40 */ IC_64BIT_REXW_ADSIZE, /* 41 */ IC_XS_ADSIZE, /* 42 */ IC_64BIT_REXW_XS, /* 43 */ IC_XD_ADSIZE, /* 44 */ IC_64BIT_REXW_XD, /* 45 */ IC_XS_ADSIZE, /* 46 */ IC_64BIT_REXW_XS, /* 47 */ IC_OPSIZE_ADSIZE, /* 48 */ IC_64BIT_OPSIZE_ADSIZE, /* 49 */ IC_XS_OPSIZE, /* 50 */ IC_64BIT_XS_OPSIZE, /* 51 */ IC_XD_OPSIZE, /* 52 */ IC_64BIT_XD_OPSIZE, /* 53 */ IC_XS_OPSIZE, /* 54 */ IC_64BIT_XD_OPSIZE, /* 55 */ IC_OPSIZE_ADSIZE, /* 56 */ IC_64BIT_REXW_OPSIZE, /* 57 */ IC_XS_OPSIZE, /* 58 */ IC_64BIT_REXW_XS, /* 59 */ IC_XD_OPSIZE, /* 60 */ IC_64BIT_REXW_XD, /* 61 */ IC_XS_OPSIZE, /* 62 */ IC_64BIT_REXW_XS, /* 63 */ IC_VEX, /* 64 */ IC_VEX, /* 65 */ IC_VEX_XS, /* 66 */ IC_VEX_XS, /* 67 */ IC_VEX_XD, /* 68 */ IC_VEX_XD, /* 69 */ IC_VEX_XD, /* 70 */ IC_VEX_XD, /* 71 */ IC_VEX_W, /* 72 */ IC_VEX_W, /* 73 */ IC_VEX_W_XS, /* 74 */ IC_VEX_W_XS, /* 75 */ IC_VEX_W_XD, /* 76 */ IC_VEX_W_XD, /* 77 */ IC_VEX_W_XD, /* 78 */ IC_VEX_W_XD, /* 79 */ IC_VEX_OPSIZE, /* 80 */ IC_VEX_OPSIZE, /* 81 */ IC_VEX_OPSIZE, /* 82 */ IC_VEX_OPSIZE, /* 83 */ IC_VEX_OPSIZE, /* 84 */ IC_VEX_OPSIZE, /* 85 */ IC_VEX_OPSIZE, /* 86 */ IC_VEX_OPSIZE, /* 87 */ IC_VEX_W_OPSIZE, /* 88 */ IC_VEX_W_OPSIZE, /* 89 */ IC_VEX_W_OPSIZE, /* 90 */ IC_VEX_W_OPSIZE, /* 91 */ IC_VEX_W_OPSIZE, /* 92 */ IC_VEX_W_OPSIZE, /* 93 */ IC_VEX_W_OPSIZE, /* 94 */ IC_VEX_W_OPSIZE, /* 95 */ IC_VEX, /* 96 */ IC_VEX, /* 97 */ IC_VEX_XS, /* 98 */ IC_VEX_XS, /* 99 */ IC_VEX_XD, /* 100 */ IC_VEX_XD, /* 101 */ IC_VEX_XD, /* 102 */ IC_VEX_XD, /* 103 */ IC_VEX_W, /* 104 */ IC_VEX_W, /* 105 */ IC_VEX_W_XS, /* 106 */ IC_VEX_W_XS, /* 107 */ IC_VEX_W_XD, /* 108 */ IC_VEX_W_XD, /* 109 */ IC_VEX_W_XD, /* 110 */ IC_VEX_W_XD, /* 111 */ IC_VEX_OPSIZE, /* 112 */ IC_VEX_OPSIZE, /* 113 */ IC_VEX_OPSIZE, /* 114 */ IC_VEX_OPSIZE, /* 115 */ IC_VEX_OPSIZE, /* 116 */ IC_VEX_OPSIZE, /* 117 */ IC_VEX_OPSIZE, /* 118 */ IC_VEX_OPSIZE, /* 119 */ IC_VEX_W_OPSIZE, /* 120 */ IC_VEX_W_OPSIZE, /* 121 */ IC_VEX_W_OPSIZE, /* 122 */ IC_VEX_W_OPSIZE, /* 123 */ IC_VEX_W_OPSIZE, /* 124 */ IC_VEX_W_OPSIZE, /* 125 */ IC_VEX_W_OPSIZE, /* 126 */ IC_VEX_W_OPSIZE, /* 127 */ IC_VEX_L, /* 128 */ IC_VEX_L, /* 129 */ IC_VEX_L_XS, /* 130 */ IC_VEX_L_XS, /* 131 */ IC_VEX_L_XD, /* 132 */ IC_VEX_L_XD, /* 133 */ IC_VEX_L_XD, /* 134 */ IC_VEX_L_XD, /* 135 */ IC_VEX_L_W, /* 136 */ IC_VEX_L_W, /* 137 */ IC_VEX_L_W_XS, /* 138 */ IC_VEX_L_W_XS, /* 139 */ IC_VEX_L_W_XD, /* 140 */ IC_VEX_L_W_XD, /* 141 */ IC_VEX_L_W_XD, /* 142 */ IC_VEX_L_W_XD, /* 143 */ IC_VEX_L_OPSIZE, /* 144 */ IC_VEX_L_OPSIZE, /* 145 */ IC_VEX_L_OPSIZE, /* 146 */ IC_VEX_L_OPSIZE, /* 147 */ IC_VEX_L_OPSIZE, /* 148 */ IC_VEX_L_OPSIZE, /* 149 */ IC_VEX_L_OPSIZE, /* 150 */ IC_VEX_L_OPSIZE, /* 151 */ IC_VEX_L_W_OPSIZE, /* 152 */ IC_VEX_L_W_OPSIZE, /* 153 */ IC_VEX_L_W_OPSIZE, /* 154 */ IC_VEX_L_W_OPSIZE, /* 155 */ IC_VEX_L_W_OPSIZE, /* 156 */ IC_VEX_L_W_OPSIZE, /* 157 */ IC_VEX_L_W_OPSIZE, /* 158 */ IC_VEX_L_W_OPSIZE, /* 159 */ IC_VEX_L, /* 160 */ IC_VEX_L, /* 161 */ IC_VEX_L_XS, /* 162 */ IC_VEX_L_XS, /* 163 */ IC_VEX_L_XD, /* 164 */ IC_VEX_L_XD, /* 165 */ IC_VEX_L_XD, /* 166 */ IC_VEX_L_XD, /* 167 */ IC_VEX_L_W, /* 168 */ IC_VEX_L_W, /* 169 */ IC_VEX_L_W_XS, /* 170 */ IC_VEX_L_W_XS, /* 171 */ IC_VEX_L_W_XD, /* 172 */ IC_VEX_L_W_XD, /* 173 */ IC_VEX_L_W_XD, /* 174 */ IC_VEX_L_W_XD, /* 175 */ IC_VEX_L_OPSIZE, /* 176 */ IC_VEX_L_OPSIZE, /* 177 */ IC_VEX_L_OPSIZE, /* 178 */ IC_VEX_L_OPSIZE, /* 179 */ IC_VEX_L_OPSIZE, /* 180 */ IC_VEX_L_OPSIZE, /* 181 */ IC_VEX_L_OPSIZE, /* 182 */ IC_VEX_L_OPSIZE, /* 183 */ IC_VEX_L_W_OPSIZE, /* 184 */ IC_VEX_L_W_OPSIZE, /* 185 */ IC_VEX_L_W_OPSIZE, /* 186 */ IC_VEX_L_W_OPSIZE, /* 187 */ IC_VEX_L_W_OPSIZE, /* 188 */ IC_VEX_L_W_OPSIZE, /* 189 */ IC_VEX_L_W_OPSIZE, /* 190 */ IC_VEX_L_W_OPSIZE, /* 191 */ IC_VEX_L, /* 192 */ IC_VEX_L, /* 193 */ IC_VEX_L_XS, /* 194 */ IC_VEX_L_XS, /* 195 */ IC_VEX_L_XD, /* 196 */ IC_VEX_L_XD, /* 197 */ IC_VEX_L_XD, /* 198 */ IC_VEX_L_XD, /* 199 */ IC_VEX_L_W, /* 200 */ IC_VEX_L_W, /* 201 */ IC_VEX_L_W_XS, /* 202 */ IC_VEX_L_W_XS, /* 203 */ IC_VEX_L_W_XD, /* 204 */ IC_VEX_L_W_XD, /* 205 */ IC_VEX_L_W_XD, /* 206 */ IC_VEX_L_W_XD, /* 207 */ IC_VEX_L_OPSIZE, /* 208 */ IC_VEX_L_OPSIZE, /* 209 */ IC_VEX_L_OPSIZE, /* 210 */ IC_VEX_L_OPSIZE, /* 211 */ IC_VEX_L_OPSIZE, /* 212 */ IC_VEX_L_OPSIZE, /* 213 */ IC_VEX_L_OPSIZE, /* 214 */ IC_VEX_L_OPSIZE, /* 215 */ IC_VEX_L_W_OPSIZE, /* 216 */ IC_VEX_L_W_OPSIZE, /* 217 */ IC_VEX_L_W_OPSIZE, /* 218 */ IC_VEX_L_W_OPSIZE, /* 219 */ IC_VEX_L_W_OPSIZE, /* 220 */ IC_VEX_L_W_OPSIZE, /* 221 */ IC_VEX_L_W_OPSIZE, /* 222 */ IC_VEX_L_W_OPSIZE, /* 223 */ IC_VEX_L, /* 224 */ IC_VEX_L, /* 225 */ IC_VEX_L_XS, /* 226 */ IC_VEX_L_XS, /* 227 */ IC_VEX_L_XD, /* 228 */ IC_VEX_L_XD, /* 229 */ IC_VEX_L_XD, /* 230 */ IC_VEX_L_XD, /* 231 */ IC_VEX_L_W, /* 232 */ IC_VEX_L_W, /* 233 */ IC_VEX_L_W_XS, /* 234 */ IC_VEX_L_W_XS, /* 235 */ IC_VEX_L_W_XD, /* 236 */ IC_VEX_L_W_XD, /* 237 */ IC_VEX_L_W_XD, /* 238 */ IC_VEX_L_W_XD, /* 239 */ IC_VEX_L_OPSIZE, /* 240 */ IC_VEX_L_OPSIZE, /* 241 */ IC_VEX_L_OPSIZE, /* 242 */ IC_VEX_L_OPSIZE, /* 243 */ IC_VEX_L_OPSIZE, /* 244 */ IC_VEX_L_OPSIZE, /* 245 */ IC_VEX_L_OPSIZE, /* 246 */ IC_VEX_L_OPSIZE, /* 247 */ IC_VEX_L_W_OPSIZE, /* 248 */ IC_VEX_L_W_OPSIZE, /* 249 */ IC_VEX_L_W_OPSIZE, /* 250 */ IC_VEX_L_W_OPSIZE, /* 251 */ IC_VEX_L_W_OPSIZE, /* 252 */ IC_VEX_L_W_OPSIZE, /* 253 */ IC_VEX_L_W_OPSIZE, /* 254 */ IC_VEX_L_W_OPSIZE, /* 255 */ IC_EVEX, /* 256 */ IC_EVEX, /* 257 */ IC_EVEX_XS, /* 258 */ IC_EVEX_XS, /* 259 */ IC_EVEX_XD, /* 260 */ IC_EVEX_XD, /* 261 */ IC_EVEX_XD, /* 262 */ IC_EVEX_XD, /* 263 */ IC_EVEX_W, /* 264 */ IC_EVEX_W, /* 265 */ IC_EVEX_W_XS, /* 266 */ IC_EVEX_W_XS, /* 267 */ IC_EVEX_W_XD, /* 268 */ IC_EVEX_W_XD, /* 269 */ IC_EVEX_W_XD, /* 270 */ IC_EVEX_W_XD, /* 271 */ IC_EVEX_OPSIZE, /* 272 */ IC_EVEX_OPSIZE, /* 273 */ IC_EVEX_OPSIZE, /* 274 */ IC_EVEX_OPSIZE, /* 275 */ IC_EVEX_OPSIZE, /* 276 */ IC_EVEX_OPSIZE, /* 277 */ IC_EVEX_OPSIZE, /* 278 */ IC_EVEX_OPSIZE, /* 279 */ IC_EVEX_W_OPSIZE, /* 280 */ IC_EVEX_W_OPSIZE, /* 281 */ IC_EVEX_W_OPSIZE, /* 282 */ IC_EVEX_W_OPSIZE, /* 283 */ IC_EVEX_W_OPSIZE, /* 284 */ IC_EVEX_W_OPSIZE, /* 285 */ IC_EVEX_W_OPSIZE, /* 286 */ IC_EVEX_W_OPSIZE, /* 287 */ IC_EVEX, /* 288 */ IC_EVEX, /* 289 */ IC_EVEX_XS, /* 290 */ IC_EVEX_XS, /* 291 */ IC_EVEX_XD, /* 292 */ IC_EVEX_XD, /* 293 */ IC_EVEX_XD, /* 294 */ IC_EVEX_XD, /* 295 */ IC_EVEX_W, /* 296 */ IC_EVEX_W, /* 297 */ IC_EVEX_W_XS, /* 298 */ IC_EVEX_W_XS, /* 299 */ IC_EVEX_W_XD, /* 300 */ IC_EVEX_W_XD, /* 301 */ IC_EVEX_W_XD, /* 302 */ IC_EVEX_W_XD, /* 303 */ IC_EVEX_OPSIZE, /* 304 */ IC_EVEX_OPSIZE, /* 305 */ IC_EVEX_OPSIZE, /* 306 */ IC_EVEX_OPSIZE, /* 307 */ IC_EVEX_OPSIZE, /* 308 */ IC_EVEX_OPSIZE, /* 309 */ IC_EVEX_OPSIZE, /* 310 */ IC_EVEX_OPSIZE, /* 311 */ IC_EVEX_W_OPSIZE, /* 312 */ IC_EVEX_W_OPSIZE, /* 313 */ IC_EVEX_W_OPSIZE, /* 314 */ IC_EVEX_W_OPSIZE, /* 315 */ IC_EVEX_W_OPSIZE, /* 316 */ IC_EVEX_W_OPSIZE, /* 317 */ IC_EVEX_W_OPSIZE, /* 318 */ IC_EVEX_W_OPSIZE, /* 319 */ IC_EVEX, /* 320 */ IC_EVEX, /* 321 */ IC_EVEX_XS, /* 322 */ IC_EVEX_XS, /* 323 */ IC_EVEX_XD, /* 324 */ IC_EVEX_XD, /* 325 */ IC_EVEX_XD, /* 326 */ IC_EVEX_XD, /* 327 */ IC_EVEX_W, /* 328 */ IC_EVEX_W, /* 329 */ IC_EVEX_W_XS, /* 330 */ IC_EVEX_W_XS, /* 331 */ IC_EVEX_W_XD, /* 332 */ IC_EVEX_W_XD, /* 333 */ IC_EVEX_W_XD, /* 334 */ IC_EVEX_W_XD, /* 335 */ IC_EVEX_OPSIZE, /* 336 */ IC_EVEX_OPSIZE, /* 337 */ IC_EVEX_OPSIZE, /* 338 */ IC_EVEX_OPSIZE, /* 339 */ IC_EVEX_OPSIZE, /* 340 */ IC_EVEX_OPSIZE, /* 341 */ IC_EVEX_OPSIZE, /* 342 */ IC_EVEX_OPSIZE, /* 343 */ IC_EVEX_W_OPSIZE, /* 344 */ IC_EVEX_W_OPSIZE, /* 345 */ IC_EVEX_W_OPSIZE, /* 346 */ IC_EVEX_W_OPSIZE, /* 347 */ IC_EVEX_W_OPSIZE, /* 348 */ IC_EVEX_W_OPSIZE, /* 349 */ IC_EVEX_W_OPSIZE, /* 350 */ IC_EVEX_W_OPSIZE, /* 351 */ IC_EVEX, /* 352 */ IC_EVEX, /* 353 */ IC_EVEX_XS, /* 354 */ IC_EVEX_XS, /* 355 */ IC_EVEX_XD, /* 356 */ IC_EVEX_XD, /* 357 */ IC_EVEX_XD, /* 358 */ IC_EVEX_XD, /* 359 */ IC_EVEX_W, /* 360 */ IC_EVEX_W, /* 361 */ IC_EVEX_W_XS, /* 362 */ IC_EVEX_W_XS, /* 363 */ IC_EVEX_W_XD, /* 364 */ IC_EVEX_W_XD, /* 365 */ IC_EVEX_W_XD, /* 366 */ IC_EVEX_W_XD, /* 367 */ IC_EVEX_OPSIZE, /* 368 */ IC_EVEX_OPSIZE, /* 369 */ IC_EVEX_OPSIZE, /* 370 */ IC_EVEX_OPSIZE, /* 371 */ IC_EVEX_OPSIZE, /* 372 */ IC_EVEX_OPSIZE, /* 373 */ IC_EVEX_OPSIZE, /* 374 */ IC_EVEX_OPSIZE, /* 375 */ IC_EVEX_W_OPSIZE, /* 376 */ IC_EVEX_W_OPSIZE, /* 377 */ IC_EVEX_W_OPSIZE, /* 378 */ IC_EVEX_W_OPSIZE, /* 379 */ IC_EVEX_W_OPSIZE, /* 380 */ IC_EVEX_W_OPSIZE, /* 381 */ IC_EVEX_W_OPSIZE, /* 382 */ IC_EVEX_W_OPSIZE, /* 383 */ IC_EVEX, /* 384 */ IC_EVEX, /* 385 */ IC_EVEX_XS, /* 386 */ IC_EVEX_XS, /* 387 */ IC_EVEX_XD, /* 388 */ IC_EVEX_XD, /* 389 */ IC_EVEX_XD, /* 390 */ IC_EVEX_XD, /* 391 */ IC_EVEX_W, /* 392 */ IC_EVEX_W, /* 393 */ IC_EVEX_W_XS, /* 394 */ IC_EVEX_W_XS, /* 395 */ IC_EVEX_W_XD, /* 396 */ IC_EVEX_W_XD, /* 397 */ IC_EVEX_W_XD, /* 398 */ IC_EVEX_W_XD, /* 399 */ IC_EVEX_OPSIZE, /* 400 */ IC_EVEX_OPSIZE, /* 401 */ IC_EVEX_OPSIZE, /* 402 */ IC_EVEX_OPSIZE, /* 403 */ IC_EVEX_OPSIZE, /* 404 */ IC_EVEX_OPSIZE, /* 405 */ IC_EVEX_OPSIZE, /* 406 */ IC_EVEX_OPSIZE, /* 407 */ IC_EVEX_W_OPSIZE, /* 408 */ IC_EVEX_W_OPSIZE, /* 409 */ IC_EVEX_W_OPSIZE, /* 410 */ IC_EVEX_W_OPSIZE, /* 411 */ IC_EVEX_W_OPSIZE, /* 412 */ IC_EVEX_W_OPSIZE, /* 413 */ IC_EVEX_W_OPSIZE, /* 414 */ IC_EVEX_W_OPSIZE, /* 415 */ IC_EVEX, /* 416 */ IC_EVEX, /* 417 */ IC_EVEX_XS, /* 418 */ IC_EVEX_XS, /* 419 */ IC_EVEX_XD, /* 420 */ IC_EVEX_XD, /* 421 */ IC_EVEX_XD, /* 422 */ IC_EVEX_XD, /* 423 */ IC_EVEX_W, /* 424 */ IC_EVEX_W, /* 425 */ IC_EVEX_W_XS, /* 426 */ IC_EVEX_W_XS, /* 427 */ IC_EVEX_W_XD, /* 428 */ IC_EVEX_W_XD, /* 429 */ IC_EVEX_W_XD, /* 430 */ IC_EVEX_W_XD, /* 431 */ IC_EVEX_OPSIZE, /* 432 */ IC_EVEX_OPSIZE, /* 433 */ IC_EVEX_OPSIZE, /* 434 */ IC_EVEX_OPSIZE, /* 435 */ IC_EVEX_OPSIZE, /* 436 */ IC_EVEX_OPSIZE, /* 437 */ IC_EVEX_OPSIZE, /* 438 */ IC_EVEX_OPSIZE, /* 439 */ IC_EVEX_W_OPSIZE, /* 440 */ IC_EVEX_W_OPSIZE, /* 441 */ IC_EVEX_W_OPSIZE, /* 442 */ IC_EVEX_W_OPSIZE, /* 443 */ IC_EVEX_W_OPSIZE, /* 444 */ IC_EVEX_W_OPSIZE, /* 445 */ IC_EVEX_W_OPSIZE, /* 446 */ IC_EVEX_W_OPSIZE, /* 447 */ IC_EVEX, /* 448 */ IC_EVEX, /* 449 */ IC_EVEX_XS, /* 450 */ IC_EVEX_XS, /* 451 */ IC_EVEX_XD, /* 452 */ IC_EVEX_XD, /* 453 */ IC_EVEX_XD, /* 454 */ IC_EVEX_XD, /* 455 */ IC_EVEX_W, /* 456 */ IC_EVEX_W, /* 457 */ IC_EVEX_W_XS, /* 458 */ IC_EVEX_W_XS, /* 459 */ IC_EVEX_W_XD, /* 460 */ IC_EVEX_W_XD, /* 461 */ IC_EVEX_W_XD, /* 462 */ IC_EVEX_W_XD, /* 463 */ IC_EVEX_OPSIZE, /* 464 */ IC_EVEX_OPSIZE, /* 465 */ IC_EVEX_OPSIZE, /* 466 */ IC_EVEX_OPSIZE, /* 467 */ IC_EVEX_OPSIZE, /* 468 */ IC_EVEX_OPSIZE, /* 469 */ IC_EVEX_OPSIZE, /* 470 */ IC_EVEX_OPSIZE, /* 471 */ IC_EVEX_W_OPSIZE, /* 472 */ IC_EVEX_W_OPSIZE, /* 473 */ IC_EVEX_W_OPSIZE, /* 474 */ IC_EVEX_W_OPSIZE, /* 475 */ IC_EVEX_W_OPSIZE, /* 476 */ IC_EVEX_W_OPSIZE, /* 477 */ IC_EVEX_W_OPSIZE, /* 478 */ IC_EVEX_W_OPSIZE, /* 479 */ IC_EVEX, /* 480 */ IC_EVEX, /* 481 */ IC_EVEX_XS, /* 482 */ IC_EVEX_XS, /* 483 */ IC_EVEX_XD, /* 484 */ IC_EVEX_XD, /* 485 */ IC_EVEX_XD, /* 486 */ IC_EVEX_XD, /* 487 */ IC_EVEX_W, /* 488 */ IC_EVEX_W, /* 489 */ IC_EVEX_W_XS, /* 490 */ IC_EVEX_W_XS, /* 491 */ IC_EVEX_W_XD, /* 492 */ IC_EVEX_W_XD, /* 493 */ IC_EVEX_W_XD, /* 494 */ IC_EVEX_W_XD, /* 495 */ IC_EVEX_OPSIZE, /* 496 */ IC_EVEX_OPSIZE, /* 497 */ IC_EVEX_OPSIZE, /* 498 */ IC_EVEX_OPSIZE, /* 499 */ IC_EVEX_OPSIZE, /* 500 */ IC_EVEX_OPSIZE, /* 501 */ IC_EVEX_OPSIZE, /* 502 */ IC_EVEX_OPSIZE, /* 503 */ IC_EVEX_W_OPSIZE, /* 504 */ IC_EVEX_W_OPSIZE, /* 505 */ IC_EVEX_W_OPSIZE, /* 506 */ IC_EVEX_W_OPSIZE, /* 507 */ IC_EVEX_W_OPSIZE, /* 508 */ IC_EVEX_W_OPSIZE, /* 509 */ IC_EVEX_W_OPSIZE, /* 510 */ IC_EVEX_W_OPSIZE, /* 511 */ IC, /* 512 */ IC_64BIT, /* 513 */ IC_XS, /* 514 */ IC_64BIT_XS, /* 515 */ IC_XD, /* 516 */ IC_64BIT_XD, /* 517 */ IC_XS, /* 518 */ IC_64BIT_XS, /* 519 */ IC, /* 520 */ IC_64BIT_REXW, /* 521 */ IC_XS, /* 522 */ IC_64BIT_REXW_XS, /* 523 */ IC_XD, /* 524 */ IC_64BIT_REXW_XD, /* 525 */ IC_XS, /* 526 */ IC_64BIT_REXW_XS, /* 527 */ IC_OPSIZE, /* 528 */ IC_64BIT_OPSIZE, /* 529 */ IC_XS_OPSIZE, /* 530 */ IC_64BIT_XS_OPSIZE, /* 531 */ IC_XD_OPSIZE, /* 532 */ IC_64BIT_XD_OPSIZE, /* 533 */ IC_XS_OPSIZE, /* 534 */ IC_64BIT_XD_OPSIZE, /* 535 */ IC_OPSIZE, /* 536 */ IC_64BIT_REXW_OPSIZE, /* 537 */ IC_XS_OPSIZE, /* 538 */ IC_64BIT_REXW_XS, /* 539 */ IC_XD_OPSIZE, /* 540 */ IC_64BIT_REXW_XD, /* 541 */ IC_XS_OPSIZE, /* 542 */ IC_64BIT_REXW_XS, /* 543 */ IC_ADSIZE, /* 544 */ IC_64BIT_ADSIZE, /* 545 */ IC_XS_ADSIZE, /* 546 */ IC_64BIT_XS_ADSIZE, /* 547 */ IC_XD_ADSIZE, /* 548 */ IC_64BIT_XD_ADSIZE, /* 549 */ IC_XS_ADSIZE, /* 550 */ IC_64BIT_XD_ADSIZE, /* 551 */ IC_ADSIZE, /* 552 */ IC_64BIT_REXW_ADSIZE, /* 553 */ IC_XS_ADSIZE, /* 554 */ IC_64BIT_REXW_XS, /* 555 */ IC_XD_ADSIZE, /* 556 */ IC_64BIT_REXW_XD, /* 557 */ IC_XS_ADSIZE, /* 558 */ IC_64BIT_REXW_XS, /* 559 */ IC_OPSIZE_ADSIZE, /* 560 */ IC_64BIT_OPSIZE_ADSIZE, /* 561 */ IC_XS_OPSIZE, /* 562 */ IC_64BIT_XS_OPSIZE, /* 563 */ IC_XD_OPSIZE, /* 564 */ IC_64BIT_XD_OPSIZE, /* 565 */ IC_XS_OPSIZE, /* 566 */ IC_64BIT_XD_OPSIZE, /* 567 */ IC_OPSIZE_ADSIZE, /* 568 */ IC_64BIT_REXW_OPSIZE, /* 569 */ IC_XS_OPSIZE, /* 570 */ IC_64BIT_REXW_XS, /* 571 */ IC_XD_OPSIZE, /* 572 */ IC_64BIT_REXW_XD, /* 573 */ IC_XS_OPSIZE, /* 574 */ IC_64BIT_REXW_XS, /* 575 */ IC_VEX, /* 576 */ IC_VEX, /* 577 */ IC_VEX_XS, /* 578 */ IC_VEX_XS, /* 579 */ IC_VEX_XD, /* 580 */ IC_VEX_XD, /* 581 */ IC_VEX_XD, /* 582 */ IC_VEX_XD, /* 583 */ IC_VEX_W, /* 584 */ IC_VEX_W, /* 585 */ IC_VEX_W_XS, /* 586 */ IC_VEX_W_XS, /* 587 */ IC_VEX_W_XD, /* 588 */ IC_VEX_W_XD, /* 589 */ IC_VEX_W_XD, /* 590 */ IC_VEX_W_XD, /* 591 */ IC_VEX_OPSIZE, /* 592 */ IC_VEX_OPSIZE, /* 593 */ IC_VEX_OPSIZE, /* 594 */ IC_VEX_OPSIZE, /* 595 */ IC_VEX_OPSIZE, /* 596 */ IC_VEX_OPSIZE, /* 597 */ IC_VEX_OPSIZE, /* 598 */ IC_VEX_OPSIZE, /* 599 */ IC_VEX_W_OPSIZE, /* 600 */ IC_VEX_W_OPSIZE, /* 601 */ IC_VEX_W_OPSIZE, /* 602 */ IC_VEX_W_OPSIZE, /* 603 */ IC_VEX_W_OPSIZE, /* 604 */ IC_VEX_W_OPSIZE, /* 605 */ IC_VEX_W_OPSIZE, /* 606 */ IC_VEX_W_OPSIZE, /* 607 */ IC_VEX, /* 608 */ IC_VEX, /* 609 */ IC_VEX_XS, /* 610 */ IC_VEX_XS, /* 611 */ IC_VEX_XD, /* 612 */ IC_VEX_XD, /* 613 */ IC_VEX_XD, /* 614 */ IC_VEX_XD, /* 615 */ IC_VEX_W, /* 616 */ IC_VEX_W, /* 617 */ IC_VEX_W_XS, /* 618 */ IC_VEX_W_XS, /* 619 */ IC_VEX_W_XD, /* 620 */ IC_VEX_W_XD, /* 621 */ IC_VEX_W_XD, /* 622 */ IC_VEX_W_XD, /* 623 */ IC_VEX_OPSIZE, /* 624 */ IC_VEX_OPSIZE, /* 625 */ IC_VEX_OPSIZE, /* 626 */ IC_VEX_OPSIZE, /* 627 */ IC_VEX_OPSIZE, /* 628 */ IC_VEX_OPSIZE, /* 629 */ IC_VEX_OPSIZE, /* 630 */ IC_VEX_OPSIZE, /* 631 */ IC_VEX_W_OPSIZE, /* 632 */ IC_VEX_W_OPSIZE, /* 633 */ IC_VEX_W_OPSIZE, /* 634 */ IC_VEX_W_OPSIZE, /* 635 */ IC_VEX_W_OPSIZE, /* 636 */ IC_VEX_W_OPSIZE, /* 637 */ IC_VEX_W_OPSIZE, /* 638 */ IC_VEX_W_OPSIZE, /* 639 */ IC_VEX_L, /* 640 */ IC_VEX_L, /* 641 */ IC_VEX_L_XS, /* 642 */ IC_VEX_L_XS, /* 643 */ IC_VEX_L_XD, /* 644 */ IC_VEX_L_XD, /* 645 */ IC_VEX_L_XD, /* 646 */ IC_VEX_L_XD, /* 647 */ IC_VEX_L_W, /* 648 */ IC_VEX_L_W, /* 649 */ IC_VEX_L_W_XS, /* 650 */ IC_VEX_L_W_XS, /* 651 */ IC_VEX_L_W_XD, /* 652 */ IC_VEX_L_W_XD, /* 653 */ IC_VEX_L_W_XD, /* 654 */ IC_VEX_L_W_XD, /* 655 */ IC_VEX_L_OPSIZE, /* 656 */ IC_VEX_L_OPSIZE, /* 657 */ IC_VEX_L_OPSIZE, /* 658 */ IC_VEX_L_OPSIZE, /* 659 */ IC_VEX_L_OPSIZE, /* 660 */ IC_VEX_L_OPSIZE, /* 661 */ IC_VEX_L_OPSIZE, /* 662 */ IC_VEX_L_OPSIZE, /* 663 */ IC_VEX_L_W_OPSIZE, /* 664 */ IC_VEX_L_W_OPSIZE, /* 665 */ IC_VEX_L_W_OPSIZE, /* 666 */ IC_VEX_L_W_OPSIZE, /* 667 */ IC_VEX_L_W_OPSIZE, /* 668 */ IC_VEX_L_W_OPSIZE, /* 669 */ IC_VEX_L_W_OPSIZE, /* 670 */ IC_VEX_L_W_OPSIZE, /* 671 */ IC_VEX_L, /* 672 */ IC_VEX_L, /* 673 */ IC_VEX_L_XS, /* 674 */ IC_VEX_L_XS, /* 675 */ IC_VEX_L_XD, /* 676 */ IC_VEX_L_XD, /* 677 */ IC_VEX_L_XD, /* 678 */ IC_VEX_L_XD, /* 679 */ IC_VEX_L_W, /* 680 */ IC_VEX_L_W, /* 681 */ IC_VEX_L_W_XS, /* 682 */ IC_VEX_L_W_XS, /* 683 */ IC_VEX_L_W_XD, /* 684 */ IC_VEX_L_W_XD, /* 685 */ IC_VEX_L_W_XD, /* 686 */ IC_VEX_L_W_XD, /* 687 */ IC_VEX_L_OPSIZE, /* 688 */ IC_VEX_L_OPSIZE, /* 689 */ IC_VEX_L_OPSIZE, /* 690 */ IC_VEX_L_OPSIZE, /* 691 */ IC_VEX_L_OPSIZE, /* 692 */ IC_VEX_L_OPSIZE, /* 693 */ IC_VEX_L_OPSIZE, /* 694 */ IC_VEX_L_OPSIZE, /* 695 */ IC_VEX_L_W_OPSIZE, /* 696 */ IC_VEX_L_W_OPSIZE, /* 697 */ IC_VEX_L_W_OPSIZE, /* 698 */ IC_VEX_L_W_OPSIZE, /* 699 */ IC_VEX_L_W_OPSIZE, /* 700 */ IC_VEX_L_W_OPSIZE, /* 701 */ IC_VEX_L_W_OPSIZE, /* 702 */ IC_VEX_L_W_OPSIZE, /* 703 */ IC_VEX_L, /* 704 */ IC_VEX_L, /* 705 */ IC_VEX_L_XS, /* 706 */ IC_VEX_L_XS, /* 707 */ IC_VEX_L_XD, /* 708 */ IC_VEX_L_XD, /* 709 */ IC_VEX_L_XD, /* 710 */ IC_VEX_L_XD, /* 711 */ IC_VEX_L_W, /* 712 */ IC_VEX_L_W, /* 713 */ IC_VEX_L_W_XS, /* 714 */ IC_VEX_L_W_XS, /* 715 */ IC_VEX_L_W_XD, /* 716 */ IC_VEX_L_W_XD, /* 717 */ IC_VEX_L_W_XD, /* 718 */ IC_VEX_L_W_XD, /* 719 */ IC_VEX_L_OPSIZE, /* 720 */ IC_VEX_L_OPSIZE, /* 721 */ IC_VEX_L_OPSIZE, /* 722 */ IC_VEX_L_OPSIZE, /* 723 */ IC_VEX_L_OPSIZE, /* 724 */ IC_VEX_L_OPSIZE, /* 725 */ IC_VEX_L_OPSIZE, /* 726 */ IC_VEX_L_OPSIZE, /* 727 */ IC_VEX_L_W_OPSIZE, /* 728 */ IC_VEX_L_W_OPSIZE, /* 729 */ IC_VEX_L_W_OPSIZE, /* 730 */ IC_VEX_L_W_OPSIZE, /* 731 */ IC_VEX_L_W_OPSIZE, /* 732 */ IC_VEX_L_W_OPSIZE, /* 733 */ IC_VEX_L_W_OPSIZE, /* 734 */ IC_VEX_L_W_OPSIZE, /* 735 */ IC_VEX_L, /* 736 */ IC_VEX_L, /* 737 */ IC_VEX_L_XS, /* 738 */ IC_VEX_L_XS, /* 739 */ IC_VEX_L_XD, /* 740 */ IC_VEX_L_XD, /* 741 */ IC_VEX_L_XD, /* 742 */ IC_VEX_L_XD, /* 743 */ IC_VEX_L_W, /* 744 */ IC_VEX_L_W, /* 745 */ IC_VEX_L_W_XS, /* 746 */ IC_VEX_L_W_XS, /* 747 */ IC_VEX_L_W_XD, /* 748 */ IC_VEX_L_W_XD, /* 749 */ IC_VEX_L_W_XD, /* 750 */ IC_VEX_L_W_XD, /* 751 */ IC_VEX_L_OPSIZE, /* 752 */ IC_VEX_L_OPSIZE, /* 753 */ IC_VEX_L_OPSIZE, /* 754 */ IC_VEX_L_OPSIZE, /* 755 */ IC_VEX_L_OPSIZE, /* 756 */ IC_VEX_L_OPSIZE, /* 757 */ IC_VEX_L_OPSIZE, /* 758 */ IC_VEX_L_OPSIZE, /* 759 */ IC_VEX_L_W_OPSIZE, /* 760 */ IC_VEX_L_W_OPSIZE, /* 761 */ IC_VEX_L_W_OPSIZE, /* 762 */ IC_VEX_L_W_OPSIZE, /* 763 */ IC_VEX_L_W_OPSIZE, /* 764 */ IC_VEX_L_W_OPSIZE, /* 765 */ IC_VEX_L_W_OPSIZE, /* 766 */ IC_VEX_L_W_OPSIZE, /* 767 */ IC_EVEX_L, /* 768 */ IC_EVEX_L, /* 769 */ IC_EVEX_L_XS, /* 770 */ IC_EVEX_L_XS, /* 771 */ IC_EVEX_L_XD, /* 772 */ IC_EVEX_L_XD, /* 773 */ IC_EVEX_L_XD, /* 774 */ IC_EVEX_L_XD, /* 775 */ IC_EVEX_L_W, /* 776 */ IC_EVEX_L_W, /* 777 */ IC_EVEX_L_W_XS, /* 778 */ IC_EVEX_L_W_XS, /* 779 */ IC_EVEX_L_W_XD, /* 780 */ IC_EVEX_L_W_XD, /* 781 */ IC_EVEX_L_W_XD, /* 782 */ IC_EVEX_L_W_XD, /* 783 */ IC_EVEX_L_OPSIZE, /* 784 */ IC_EVEX_L_OPSIZE, /* 785 */ IC_EVEX_L_OPSIZE, /* 786 */ IC_EVEX_L_OPSIZE, /* 787 */ IC_EVEX_L_OPSIZE, /* 788 */ IC_EVEX_L_OPSIZE, /* 789 */ IC_EVEX_L_OPSIZE, /* 790 */ IC_EVEX_L_OPSIZE, /* 791 */ IC_EVEX_L_W_OPSIZE, /* 792 */ IC_EVEX_L_W_OPSIZE, /* 793 */ IC_EVEX_L_W_OPSIZE, /* 794 */ IC_EVEX_L_W_OPSIZE, /* 795 */ IC_EVEX_L_W_OPSIZE, /* 796 */ IC_EVEX_L_W_OPSIZE, /* 797 */ IC_EVEX_L_W_OPSIZE, /* 798 */ IC_EVEX_L_W_OPSIZE, /* 799 */ IC_EVEX_L, /* 800 */ IC_EVEX_L, /* 801 */ IC_EVEX_L_XS, /* 802 */ IC_EVEX_L_XS, /* 803 */ IC_EVEX_L_XD, /* 804 */ IC_EVEX_L_XD, /* 805 */ IC_EVEX_L_XD, /* 806 */ IC_EVEX_L_XD, /* 807 */ IC_EVEX_L_W, /* 808 */ IC_EVEX_L_W, /* 809 */ IC_EVEX_L_W_XS, /* 810 */ IC_EVEX_L_W_XS, /* 811 */ IC_EVEX_L_W_XD, /* 812 */ IC_EVEX_L_W_XD, /* 813 */ IC_EVEX_L_W_XD, /* 814 */ IC_EVEX_L_W_XD, /* 815 */ IC_EVEX_L_OPSIZE, /* 816 */ IC_EVEX_L_OPSIZE, /* 817 */ IC_EVEX_L_OPSIZE, /* 818 */ IC_EVEX_L_OPSIZE, /* 819 */ IC_EVEX_L_OPSIZE, /* 820 */ IC_EVEX_L_OPSIZE, /* 821 */ IC_EVEX_L_OPSIZE, /* 822 */ IC_EVEX_L_OPSIZE, /* 823 */ IC_EVEX_L_W_OPSIZE, /* 824 */ IC_EVEX_L_W_OPSIZE, /* 825 */ IC_EVEX_L_W_OPSIZE, /* 826 */ IC_EVEX_L_W_OPSIZE, /* 827 */ IC_EVEX_L_W_OPSIZE, /* 828 */ IC_EVEX_L_W_OPSIZE, /* 829 */ IC_EVEX_L_W_OPSIZE, /* 830 */ IC_EVEX_L_W_OPSIZE, /* 831 */ IC_EVEX_L, /* 832 */ IC_EVEX_L, /* 833 */ IC_EVEX_L_XS, /* 834 */ IC_EVEX_L_XS, /* 835 */ IC_EVEX_L_XD, /* 836 */ IC_EVEX_L_XD, /* 837 */ IC_EVEX_L_XD, /* 838 */ IC_EVEX_L_XD, /* 839 */ IC_EVEX_L_W, /* 840 */ IC_EVEX_L_W, /* 841 */ IC_EVEX_L_W_XS, /* 842 */ IC_EVEX_L_W_XS, /* 843 */ IC_EVEX_L_W_XD, /* 844 */ IC_EVEX_L_W_XD, /* 845 */ IC_EVEX_L_W_XD, /* 846 */ IC_EVEX_L_W_XD, /* 847 */ IC_EVEX_L_OPSIZE, /* 848 */ IC_EVEX_L_OPSIZE, /* 849 */ IC_EVEX_L_OPSIZE, /* 850 */ IC_EVEX_L_OPSIZE, /* 851 */ IC_EVEX_L_OPSIZE, /* 852 */ IC_EVEX_L_OPSIZE, /* 853 */ IC_EVEX_L_OPSIZE, /* 854 */ IC_EVEX_L_OPSIZE, /* 855 */ IC_EVEX_L_W_OPSIZE, /* 856 */ IC_EVEX_L_W_OPSIZE, /* 857 */ IC_EVEX_L_W_OPSIZE, /* 858 */ IC_EVEX_L_W_OPSIZE, /* 859 */ IC_EVEX_L_W_OPSIZE, /* 860 */ IC_EVEX_L_W_OPSIZE, /* 861 */ IC_EVEX_L_W_OPSIZE, /* 862 */ IC_EVEX_L_W_OPSIZE, /* 863 */ IC_EVEX_L, /* 864 */ IC_EVEX_L, /* 865 */ IC_EVEX_L_XS, /* 866 */ IC_EVEX_L_XS, /* 867 */ IC_EVEX_L_XD, /* 868 */ IC_EVEX_L_XD, /* 869 */ IC_EVEX_L_XD, /* 870 */ IC_EVEX_L_XD, /* 871 */ IC_EVEX_L_W, /* 872 */ IC_EVEX_L_W, /* 873 */ IC_EVEX_L_W_XS, /* 874 */ IC_EVEX_L_W_XS, /* 875 */ IC_EVEX_L_W_XD, /* 876 */ IC_EVEX_L_W_XD, /* 877 */ IC_EVEX_L_W_XD, /* 878 */ IC_EVEX_L_W_XD, /* 879 */ IC_EVEX_L_OPSIZE, /* 880 */ IC_EVEX_L_OPSIZE, /* 881 */ IC_EVEX_L_OPSIZE, /* 882 */ IC_EVEX_L_OPSIZE, /* 883 */ IC_EVEX_L_OPSIZE, /* 884 */ IC_EVEX_L_OPSIZE, /* 885 */ IC_EVEX_L_OPSIZE, /* 886 */ IC_EVEX_L_OPSIZE, /* 887 */ IC_EVEX_L_W_OPSIZE, /* 888 */ IC_EVEX_L_W_OPSIZE, /* 889 */ IC_EVEX_L_W_OPSIZE, /* 890 */ IC_EVEX_L_W_OPSIZE, /* 891 */ IC_EVEX_L_W_OPSIZE, /* 892 */ IC_EVEX_L_W_OPSIZE, /* 893 */ IC_EVEX_L_W_OPSIZE, /* 894 */ IC_EVEX_L_W_OPSIZE, /* 895 */ IC_EVEX_L, /* 896 */ IC_EVEX_L, /* 897 */ IC_EVEX_L_XS, /* 898 */ IC_EVEX_L_XS, /* 899 */ IC_EVEX_L_XD, /* 900 */ IC_EVEX_L_XD, /* 901 */ IC_EVEX_L_XD, /* 902 */ IC_EVEX_L_XD, /* 903 */ IC_EVEX_L_W, /* 904 */ IC_EVEX_L_W, /* 905 */ IC_EVEX_L_W_XS, /* 906 */ IC_EVEX_L_W_XS, /* 907 */ IC_EVEX_L_W_XD, /* 908 */ IC_EVEX_L_W_XD, /* 909 */ IC_EVEX_L_W_XD, /* 910 */ IC_EVEX_L_W_XD, /* 911 */ IC_EVEX_L_OPSIZE, /* 912 */ IC_EVEX_L_OPSIZE, /* 913 */ IC_EVEX_L_OPSIZE, /* 914 */ IC_EVEX_L_OPSIZE, /* 915 */ IC_EVEX_L_OPSIZE, /* 916 */ IC_EVEX_L_OPSIZE, /* 917 */ IC_EVEX_L_OPSIZE, /* 918 */ IC_EVEX_L_OPSIZE, /* 919 */ IC_EVEX_L_W_OPSIZE, /* 920 */ IC_EVEX_L_W_OPSIZE, /* 921 */ IC_EVEX_L_W_OPSIZE, /* 922 */ IC_EVEX_L_W_OPSIZE, /* 923 */ IC_EVEX_L_W_OPSIZE, /* 924 */ IC_EVEX_L_W_OPSIZE, /* 925 */ IC_EVEX_L_W_OPSIZE, /* 926 */ IC_EVEX_L_W_OPSIZE, /* 927 */ IC_EVEX_L, /* 928 */ IC_EVEX_L, /* 929 */ IC_EVEX_L_XS, /* 930 */ IC_EVEX_L_XS, /* 931 */ IC_EVEX_L_XD, /* 932 */ IC_EVEX_L_XD, /* 933 */ IC_EVEX_L_XD, /* 934 */ IC_EVEX_L_XD, /* 935 */ IC_EVEX_L_W, /* 936 */ IC_EVEX_L_W, /* 937 */ IC_EVEX_L_W_XS, /* 938 */ IC_EVEX_L_W_XS, /* 939 */ IC_EVEX_L_W_XD, /* 940 */ IC_EVEX_L_W_XD, /* 941 */ IC_EVEX_L_W_XD, /* 942 */ IC_EVEX_L_W_XD, /* 943 */ IC_EVEX_L_OPSIZE, /* 944 */ IC_EVEX_L_OPSIZE, /* 945 */ IC_EVEX_L_OPSIZE, /* 946 */ IC_EVEX_L_OPSIZE, /* 947 */ IC_EVEX_L_OPSIZE, /* 948 */ IC_EVEX_L_OPSIZE, /* 949 */ IC_EVEX_L_OPSIZE, /* 950 */ IC_EVEX_L_OPSIZE, /* 951 */ IC_EVEX_L_W_OPSIZE, /* 952 */ IC_EVEX_L_W_OPSIZE, /* 953 */ IC_EVEX_L_W_OPSIZE, /* 954 */ IC_EVEX_L_W_OPSIZE, /* 955 */ IC_EVEX_L_W_OPSIZE, /* 956 */ IC_EVEX_L_W_OPSIZE, /* 957 */ IC_EVEX_L_W_OPSIZE, /* 958 */ IC_EVEX_L_W_OPSIZE, /* 959 */ IC_EVEX_L, /* 960 */ IC_EVEX_L, /* 961 */ IC_EVEX_L_XS, /* 962 */ IC_EVEX_L_XS, /* 963 */ IC_EVEX_L_XD, /* 964 */ IC_EVEX_L_XD, /* 965 */ IC_EVEX_L_XD, /* 966 */ IC_EVEX_L_XD, /* 967 */ IC_EVEX_L_W, /* 968 */ IC_EVEX_L_W, /* 969 */ IC_EVEX_L_W_XS, /* 970 */ IC_EVEX_L_W_XS, /* 971 */ IC_EVEX_L_W_XD, /* 972 */ IC_EVEX_L_W_XD, /* 973 */ IC_EVEX_L_W_XD, /* 974 */ IC_EVEX_L_W_XD, /* 975 */ IC_EVEX_L_OPSIZE, /* 976 */ IC_EVEX_L_OPSIZE, /* 977 */ IC_EVEX_L_OPSIZE, /* 978 */ IC_EVEX_L_OPSIZE, /* 979 */ IC_EVEX_L_OPSIZE, /* 980 */ IC_EVEX_L_OPSIZE, /* 981 */ IC_EVEX_L_OPSIZE, /* 982 */ IC_EVEX_L_OPSIZE, /* 983 */ IC_EVEX_L_W_OPSIZE, /* 984 */ IC_EVEX_L_W_OPSIZE, /* 985 */ IC_EVEX_L_W_OPSIZE, /* 986 */ IC_EVEX_L_W_OPSIZE, /* 987 */ IC_EVEX_L_W_OPSIZE, /* 988 */ IC_EVEX_L_W_OPSIZE, /* 989 */ IC_EVEX_L_W_OPSIZE, /* 990 */ IC_EVEX_L_W_OPSIZE, /* 991 */ IC_EVEX_L, /* 992 */ IC_EVEX_L, /* 993 */ IC_EVEX_L_XS, /* 994 */ IC_EVEX_L_XS, /* 995 */ IC_EVEX_L_XD, /* 996 */ IC_EVEX_L_XD, /* 997 */ IC_EVEX_L_XD, /* 998 */ IC_EVEX_L_XD, /* 999 */ IC_EVEX_L_W, /* 1000 */ IC_EVEX_L_W, /* 1001 */ IC_EVEX_L_W_XS, /* 1002 */ IC_EVEX_L_W_XS, /* 1003 */ IC_EVEX_L_W_XD, /* 1004 */ IC_EVEX_L_W_XD, /* 1005 */ IC_EVEX_L_W_XD, /* 1006 */ IC_EVEX_L_W_XD, /* 1007 */ IC_EVEX_L_OPSIZE, /* 1008 */ IC_EVEX_L_OPSIZE, /* 1009 */ IC_EVEX_L_OPSIZE, /* 1010 */ IC_EVEX_L_OPSIZE, /* 1011 */ IC_EVEX_L_OPSIZE, /* 1012 */ IC_EVEX_L_OPSIZE, /* 1013 */ IC_EVEX_L_OPSIZE, /* 1014 */ IC_EVEX_L_OPSIZE, /* 1015 */ IC_EVEX_L_W_OPSIZE, /* 1016 */ IC_EVEX_L_W_OPSIZE, /* 1017 */ IC_EVEX_L_W_OPSIZE, /* 1018 */ IC_EVEX_L_W_OPSIZE, /* 1019 */ IC_EVEX_L_W_OPSIZE, /* 1020 */ IC_EVEX_L_W_OPSIZE, /* 1021 */ IC_EVEX_L_W_OPSIZE, /* 1022 */ IC_EVEX_L_W_OPSIZE, /* 1023 */ IC, /* 1024 */ IC_64BIT, /* 1025 */ IC_XS, /* 1026 */ IC_64BIT_XS, /* 1027 */ IC_XD, /* 1028 */ IC_64BIT_XD, /* 1029 */ IC_XS, /* 1030 */ IC_64BIT_XS, /* 1031 */ IC, /* 1032 */ IC_64BIT_REXW, /* 1033 */ IC_XS, /* 1034 */ IC_64BIT_REXW_XS, /* 1035 */ IC_XD, /* 1036 */ IC_64BIT_REXW_XD, /* 1037 */ IC_XS, /* 1038 */ IC_64BIT_REXW_XS, /* 1039 */ IC_OPSIZE, /* 1040 */ IC_64BIT_OPSIZE, /* 1041 */ IC_XS_OPSIZE, /* 1042 */ IC_64BIT_XS_OPSIZE, /* 1043 */ IC_XD_OPSIZE, /* 1044 */ IC_64BIT_XD_OPSIZE, /* 1045 */ IC_XS_OPSIZE, /* 1046 */ IC_64BIT_XD_OPSIZE, /* 1047 */ IC_OPSIZE, /* 1048 */ IC_64BIT_REXW_OPSIZE, /* 1049 */ IC_XS_OPSIZE, /* 1050 */ IC_64BIT_REXW_XS, /* 1051 */ IC_XD_OPSIZE, /* 1052 */ IC_64BIT_REXW_XD, /* 1053 */ IC_XS_OPSIZE, /* 1054 */ IC_64BIT_REXW_XS, /* 1055 */ IC_ADSIZE, /* 1056 */ IC_64BIT_ADSIZE, /* 1057 */ IC_XS_ADSIZE, /* 1058 */ IC_64BIT_XS_ADSIZE, /* 1059 */ IC_XD_ADSIZE, /* 1060 */ IC_64BIT_XD_ADSIZE, /* 1061 */ IC_XS_ADSIZE, /* 1062 */ IC_64BIT_XD_ADSIZE, /* 1063 */ IC_ADSIZE, /* 1064 */ IC_64BIT_REXW_ADSIZE, /* 1065 */ IC_XS_ADSIZE, /* 1066 */ IC_64BIT_REXW_XS, /* 1067 */ IC_XD_ADSIZE, /* 1068 */ IC_64BIT_REXW_XD, /* 1069 */ IC_XS_ADSIZE, /* 1070 */ IC_64BIT_REXW_XS, /* 1071 */ IC_OPSIZE_ADSIZE, /* 1072 */ IC_64BIT_OPSIZE_ADSIZE, /* 1073 */ IC_XS_OPSIZE, /* 1074 */ IC_64BIT_XS_OPSIZE, /* 1075 */ IC_XD_OPSIZE, /* 1076 */ IC_64BIT_XD_OPSIZE, /* 1077 */ IC_XS_OPSIZE, /* 1078 */ IC_64BIT_XD_OPSIZE, /* 1079 */ IC_OPSIZE_ADSIZE, /* 1080 */ IC_64BIT_REXW_OPSIZE, /* 1081 */ IC_XS_OPSIZE, /* 1082 */ IC_64BIT_REXW_XS, /* 1083 */ IC_XD_OPSIZE, /* 1084 */ IC_64BIT_REXW_XD, /* 1085 */ IC_XS_OPSIZE, /* 1086 */ IC_64BIT_REXW_XS, /* 1087 */ IC_VEX, /* 1088 */ IC_VEX, /* 1089 */ IC_VEX_XS, /* 1090 */ IC_VEX_XS, /* 1091 */ IC_VEX_XD, /* 1092 */ IC_VEX_XD, /* 1093 */ IC_VEX_XD, /* 1094 */ IC_VEX_XD, /* 1095 */ IC_VEX_W, /* 1096 */ IC_VEX_W, /* 1097 */ IC_VEX_W_XS, /* 1098 */ IC_VEX_W_XS, /* 1099 */ IC_VEX_W_XD, /* 1100 */ IC_VEX_W_XD, /* 1101 */ IC_VEX_W_XD, /* 1102 */ IC_VEX_W_XD, /* 1103 */ IC_VEX_OPSIZE, /* 1104 */ IC_VEX_OPSIZE, /* 1105 */ IC_VEX_OPSIZE, /* 1106 */ IC_VEX_OPSIZE, /* 1107 */ IC_VEX_OPSIZE, /* 1108 */ IC_VEX_OPSIZE, /* 1109 */ IC_VEX_OPSIZE, /* 1110 */ IC_VEX_OPSIZE, /* 1111 */ IC_VEX_W_OPSIZE, /* 1112 */ IC_VEX_W_OPSIZE, /* 1113 */ IC_VEX_W_OPSIZE, /* 1114 */ IC_VEX_W_OPSIZE, /* 1115 */ IC_VEX_W_OPSIZE, /* 1116 */ IC_VEX_W_OPSIZE, /* 1117 */ IC_VEX_W_OPSIZE, /* 1118 */ IC_VEX_W_OPSIZE, /* 1119 */ IC_VEX, /* 1120 */ IC_VEX, /* 1121 */ IC_VEX_XS, /* 1122 */ IC_VEX_XS, /* 1123 */ IC_VEX_XD, /* 1124 */ IC_VEX_XD, /* 1125 */ IC_VEX_XD, /* 1126 */ IC_VEX_XD, /* 1127 */ IC_VEX_W, /* 1128 */ IC_VEX_W, /* 1129 */ IC_VEX_W_XS, /* 1130 */ IC_VEX_W_XS, /* 1131 */ IC_VEX_W_XD, /* 1132 */ IC_VEX_W_XD, /* 1133 */ IC_VEX_W_XD, /* 1134 */ IC_VEX_W_XD, /* 1135 */ IC_VEX_OPSIZE, /* 1136 */ IC_VEX_OPSIZE, /* 1137 */ IC_VEX_OPSIZE, /* 1138 */ IC_VEX_OPSIZE, /* 1139 */ IC_VEX_OPSIZE, /* 1140 */ IC_VEX_OPSIZE, /* 1141 */ IC_VEX_OPSIZE, /* 1142 */ IC_VEX_OPSIZE, /* 1143 */ IC_VEX_W_OPSIZE, /* 1144 */ IC_VEX_W_OPSIZE, /* 1145 */ IC_VEX_W_OPSIZE, /* 1146 */ IC_VEX_W_OPSIZE, /* 1147 */ IC_VEX_W_OPSIZE, /* 1148 */ IC_VEX_W_OPSIZE, /* 1149 */ IC_VEX_W_OPSIZE, /* 1150 */ IC_VEX_W_OPSIZE, /* 1151 */ IC_VEX_L, /* 1152 */ IC_VEX_L, /* 1153 */ IC_VEX_L_XS, /* 1154 */ IC_VEX_L_XS, /* 1155 */ IC_VEX_L_XD, /* 1156 */ IC_VEX_L_XD, /* 1157 */ IC_VEX_L_XD, /* 1158 */ IC_VEX_L_XD, /* 1159 */ IC_VEX_L_W, /* 1160 */ IC_VEX_L_W, /* 1161 */ IC_VEX_L_W_XS, /* 1162 */ IC_VEX_L_W_XS, /* 1163 */ IC_VEX_L_W_XD, /* 1164 */ IC_VEX_L_W_XD, /* 1165 */ IC_VEX_L_W_XD, /* 1166 */ IC_VEX_L_W_XD, /* 1167 */ IC_VEX_L_OPSIZE, /* 1168 */ IC_VEX_L_OPSIZE, /* 1169 */ IC_VEX_L_OPSIZE, /* 1170 */ IC_VEX_L_OPSIZE, /* 1171 */ IC_VEX_L_OPSIZE, /* 1172 */ IC_VEX_L_OPSIZE, /* 1173 */ IC_VEX_L_OPSIZE, /* 1174 */ IC_VEX_L_OPSIZE, /* 1175 */ IC_VEX_L_W_OPSIZE, /* 1176 */ IC_VEX_L_W_OPSIZE, /* 1177 */ IC_VEX_L_W_OPSIZE, /* 1178 */ IC_VEX_L_W_OPSIZE, /* 1179 */ IC_VEX_L_W_OPSIZE, /* 1180 */ IC_VEX_L_W_OPSIZE, /* 1181 */ IC_VEX_L_W_OPSIZE, /* 1182 */ IC_VEX_L_W_OPSIZE, /* 1183 */ IC_VEX_L, /* 1184 */ IC_VEX_L, /* 1185 */ IC_VEX_L_XS, /* 1186 */ IC_VEX_L_XS, /* 1187 */ IC_VEX_L_XD, /* 1188 */ IC_VEX_L_XD, /* 1189 */ IC_VEX_L_XD, /* 1190 */ IC_VEX_L_XD, /* 1191 */ IC_VEX_L_W, /* 1192 */ IC_VEX_L_W, /* 1193 */ IC_VEX_L_W_XS, /* 1194 */ IC_VEX_L_W_XS, /* 1195 */ IC_VEX_L_W_XD, /* 1196 */ IC_VEX_L_W_XD, /* 1197 */ IC_VEX_L_W_XD, /* 1198 */ IC_VEX_L_W_XD, /* 1199 */ IC_VEX_L_OPSIZE, /* 1200 */ IC_VEX_L_OPSIZE, /* 1201 */ IC_VEX_L_OPSIZE, /* 1202 */ IC_VEX_L_OPSIZE, /* 1203 */ IC_VEX_L_OPSIZE, /* 1204 */ IC_VEX_L_OPSIZE, /* 1205 */ IC_VEX_L_OPSIZE, /* 1206 */ IC_VEX_L_OPSIZE, /* 1207 */ IC_VEX_L_W_OPSIZE, /* 1208 */ IC_VEX_L_W_OPSIZE, /* 1209 */ IC_VEX_L_W_OPSIZE, /* 1210 */ IC_VEX_L_W_OPSIZE, /* 1211 */ IC_VEX_L_W_OPSIZE, /* 1212 */ IC_VEX_L_W_OPSIZE, /* 1213 */ IC_VEX_L_W_OPSIZE, /* 1214 */ IC_VEX_L_W_OPSIZE, /* 1215 */ IC_VEX_L, /* 1216 */ IC_VEX_L, /* 1217 */ IC_VEX_L_XS, /* 1218 */ IC_VEX_L_XS, /* 1219 */ IC_VEX_L_XD, /* 1220 */ IC_VEX_L_XD, /* 1221 */ IC_VEX_L_XD, /* 1222 */ IC_VEX_L_XD, /* 1223 */ IC_VEX_L_W, /* 1224 */ IC_VEX_L_W, /* 1225 */ IC_VEX_L_W_XS, /* 1226 */ IC_VEX_L_W_XS, /* 1227 */ IC_VEX_L_W_XD, /* 1228 */ IC_VEX_L_W_XD, /* 1229 */ IC_VEX_L_W_XD, /* 1230 */ IC_VEX_L_W_XD, /* 1231 */ IC_VEX_L_OPSIZE, /* 1232 */ IC_VEX_L_OPSIZE, /* 1233 */ IC_VEX_L_OPSIZE, /* 1234 */ IC_VEX_L_OPSIZE, /* 1235 */ IC_VEX_L_OPSIZE, /* 1236 */ IC_VEX_L_OPSIZE, /* 1237 */ IC_VEX_L_OPSIZE, /* 1238 */ IC_VEX_L_OPSIZE, /* 1239 */ IC_VEX_L_W_OPSIZE, /* 1240 */ IC_VEX_L_W_OPSIZE, /* 1241 */ IC_VEX_L_W_OPSIZE, /* 1242 */ IC_VEX_L_W_OPSIZE, /* 1243 */ IC_VEX_L_W_OPSIZE, /* 1244 */ IC_VEX_L_W_OPSIZE, /* 1245 */ IC_VEX_L_W_OPSIZE, /* 1246 */ IC_VEX_L_W_OPSIZE, /* 1247 */ IC_VEX_L, /* 1248 */ IC_VEX_L, /* 1249 */ IC_VEX_L_XS, /* 1250 */ IC_VEX_L_XS, /* 1251 */ IC_VEX_L_XD, /* 1252 */ IC_VEX_L_XD, /* 1253 */ IC_VEX_L_XD, /* 1254 */ IC_VEX_L_XD, /* 1255 */ IC_VEX_L_W, /* 1256 */ IC_VEX_L_W, /* 1257 */ IC_VEX_L_W_XS, /* 1258 */ IC_VEX_L_W_XS, /* 1259 */ IC_VEX_L_W_XD, /* 1260 */ IC_VEX_L_W_XD, /* 1261 */ IC_VEX_L_W_XD, /* 1262 */ IC_VEX_L_W_XD, /* 1263 */ IC_VEX_L_OPSIZE, /* 1264 */ IC_VEX_L_OPSIZE, /* 1265 */ IC_VEX_L_OPSIZE, /* 1266 */ IC_VEX_L_OPSIZE, /* 1267 */ IC_VEX_L_OPSIZE, /* 1268 */ IC_VEX_L_OPSIZE, /* 1269 */ IC_VEX_L_OPSIZE, /* 1270 */ IC_VEX_L_OPSIZE, /* 1271 */ IC_VEX_L_W_OPSIZE, /* 1272 */ IC_VEX_L_W_OPSIZE, /* 1273 */ IC_VEX_L_W_OPSIZE, /* 1274 */ IC_VEX_L_W_OPSIZE, /* 1275 */ IC_VEX_L_W_OPSIZE, /* 1276 */ IC_VEX_L_W_OPSIZE, /* 1277 */ IC_VEX_L_W_OPSIZE, /* 1278 */ IC_VEX_L_W_OPSIZE, /* 1279 */ IC_EVEX_L2, /* 1280 */ IC_EVEX_L2, /* 1281 */ IC_EVEX_L2_XS, /* 1282 */ IC_EVEX_L2_XS, /* 1283 */ IC_EVEX_L2_XD, /* 1284 */ IC_EVEX_L2_XD, /* 1285 */ IC_EVEX_L2_XD, /* 1286 */ IC_EVEX_L2_XD, /* 1287 */ IC_EVEX_L2_W, /* 1288 */ IC_EVEX_L2_W, /* 1289 */ IC_EVEX_L2_W_XS, /* 1290 */ IC_EVEX_L2_W_XS, /* 1291 */ IC_EVEX_L2_W_XD, /* 1292 */ IC_EVEX_L2_W_XD, /* 1293 */ IC_EVEX_L2_W_XD, /* 1294 */ IC_EVEX_L2_W_XD, /* 1295 */ IC_EVEX_L2_OPSIZE, /* 1296 */ IC_EVEX_L2_OPSIZE, /* 1297 */ IC_EVEX_L2_OPSIZE, /* 1298 */ IC_EVEX_L2_OPSIZE, /* 1299 */ IC_EVEX_L2_OPSIZE, /* 1300 */ IC_EVEX_L2_OPSIZE, /* 1301 */ IC_EVEX_L2_OPSIZE, /* 1302 */ IC_EVEX_L2_OPSIZE, /* 1303 */ IC_EVEX_L2_W_OPSIZE, /* 1304 */ IC_EVEX_L2_W_OPSIZE, /* 1305 */ IC_EVEX_L2_W_OPSIZE, /* 1306 */ IC_EVEX_L2_W_OPSIZE, /* 1307 */ IC_EVEX_L2_W_OPSIZE, /* 1308 */ IC_EVEX_L2_W_OPSIZE, /* 1309 */ IC_EVEX_L2_W_OPSIZE, /* 1310 */ IC_EVEX_L2_W_OPSIZE, /* 1311 */ IC_EVEX_L2, /* 1312 */ IC_EVEX_L2, /* 1313 */ IC_EVEX_L2_XS, /* 1314 */ IC_EVEX_L2_XS, /* 1315 */ IC_EVEX_L2_XD, /* 1316 */ IC_EVEX_L2_XD, /* 1317 */ IC_EVEX_L2_XD, /* 1318 */ IC_EVEX_L2_XD, /* 1319 */ IC_EVEX_L2_W, /* 1320 */ IC_EVEX_L2_W, /* 1321 */ IC_EVEX_L2_W_XS, /* 1322 */ IC_EVEX_L2_W_XS, /* 1323 */ IC_EVEX_L2_W_XD, /* 1324 */ IC_EVEX_L2_W_XD, /* 1325 */ IC_EVEX_L2_W_XD, /* 1326 */ IC_EVEX_L2_W_XD, /* 1327 */ IC_EVEX_L2_OPSIZE, /* 1328 */ IC_EVEX_L2_OPSIZE, /* 1329 */ IC_EVEX_L2_OPSIZE, /* 1330 */ IC_EVEX_L2_OPSIZE, /* 1331 */ IC_EVEX_L2_OPSIZE, /* 1332 */ IC_EVEX_L2_OPSIZE, /* 1333 */ IC_EVEX_L2_OPSIZE, /* 1334 */ IC_EVEX_L2_OPSIZE, /* 1335 */ IC_EVEX_L2_W_OPSIZE, /* 1336 */ IC_EVEX_L2_W_OPSIZE, /* 1337 */ IC_EVEX_L2_W_OPSIZE, /* 1338 */ IC_EVEX_L2_W_OPSIZE, /* 1339 */ IC_EVEX_L2_W_OPSIZE, /* 1340 */ IC_EVEX_L2_W_OPSIZE, /* 1341 */ IC_EVEX_L2_W_OPSIZE, /* 1342 */ IC_EVEX_L2_W_OPSIZE, /* 1343 */ IC_EVEX_L2, /* 1344 */ IC_EVEX_L2, /* 1345 */ IC_EVEX_L2_XS, /* 1346 */ IC_EVEX_L2_XS, /* 1347 */ IC_EVEX_L2_XD, /* 1348 */ IC_EVEX_L2_XD, /* 1349 */ IC_EVEX_L2_XD, /* 1350 */ IC_EVEX_L2_XD, /* 1351 */ IC_EVEX_L2_W, /* 1352 */ IC_EVEX_L2_W, /* 1353 */ IC_EVEX_L2_W_XS, /* 1354 */ IC_EVEX_L2_W_XS, /* 1355 */ IC_EVEX_L2_W_XD, /* 1356 */ IC_EVEX_L2_W_XD, /* 1357 */ IC_EVEX_L2_W_XD, /* 1358 */ IC_EVEX_L2_W_XD, /* 1359 */ IC_EVEX_L2_OPSIZE, /* 1360 */ IC_EVEX_L2_OPSIZE, /* 1361 */ IC_EVEX_L2_OPSIZE, /* 1362 */ IC_EVEX_L2_OPSIZE, /* 1363 */ IC_EVEX_L2_OPSIZE, /* 1364 */ IC_EVEX_L2_OPSIZE, /* 1365 */ IC_EVEX_L2_OPSIZE, /* 1366 */ IC_EVEX_L2_OPSIZE, /* 1367 */ IC_EVEX_L2_W_OPSIZE, /* 1368 */ IC_EVEX_L2_W_OPSIZE, /* 1369 */ IC_EVEX_L2_W_OPSIZE, /* 1370 */ IC_EVEX_L2_W_OPSIZE, /* 1371 */ IC_EVEX_L2_W_OPSIZE, /* 1372 */ IC_EVEX_L2_W_OPSIZE, /* 1373 */ IC_EVEX_L2_W_OPSIZE, /* 1374 */ IC_EVEX_L2_W_OPSIZE, /* 1375 */ IC_EVEX_L2, /* 1376 */ IC_EVEX_L2, /* 1377 */ IC_EVEX_L2_XS, /* 1378 */ IC_EVEX_L2_XS, /* 1379 */ IC_EVEX_L2_XD, /* 1380 */ IC_EVEX_L2_XD, /* 1381 */ IC_EVEX_L2_XD, /* 1382 */ IC_EVEX_L2_XD, /* 1383 */ IC_EVEX_L2_W, /* 1384 */ IC_EVEX_L2_W, /* 1385 */ IC_EVEX_L2_W_XS, /* 1386 */ IC_EVEX_L2_W_XS, /* 1387 */ IC_EVEX_L2_W_XD, /* 1388 */ IC_EVEX_L2_W_XD, /* 1389 */ IC_EVEX_L2_W_XD, /* 1390 */ IC_EVEX_L2_W_XD, /* 1391 */ IC_EVEX_L2_OPSIZE, /* 1392 */ IC_EVEX_L2_OPSIZE, /* 1393 */ IC_EVEX_L2_OPSIZE, /* 1394 */ IC_EVEX_L2_OPSIZE, /* 1395 */ IC_EVEX_L2_OPSIZE, /* 1396 */ IC_EVEX_L2_OPSIZE, /* 1397 */ IC_EVEX_L2_OPSIZE, /* 1398 */ IC_EVEX_L2_OPSIZE, /* 1399 */ IC_EVEX_L2_W_OPSIZE, /* 1400 */ IC_EVEX_L2_W_OPSIZE, /* 1401 */ IC_EVEX_L2_W_OPSIZE, /* 1402 */ IC_EVEX_L2_W_OPSIZE, /* 1403 */ IC_EVEX_L2_W_OPSIZE, /* 1404 */ IC_EVEX_L2_W_OPSIZE, /* 1405 */ IC_EVEX_L2_W_OPSIZE, /* 1406 */ IC_EVEX_L2_W_OPSIZE, /* 1407 */ IC_EVEX_L2, /* 1408 */ IC_EVEX_L2, /* 1409 */ IC_EVEX_L2_XS, /* 1410 */ IC_EVEX_L2_XS, /* 1411 */ IC_EVEX_L2_XD, /* 1412 */ IC_EVEX_L2_XD, /* 1413 */ IC_EVEX_L2_XD, /* 1414 */ IC_EVEX_L2_XD, /* 1415 */ IC_EVEX_L2_W, /* 1416 */ IC_EVEX_L2_W, /* 1417 */ IC_EVEX_L2_W_XS, /* 1418 */ IC_EVEX_L2_W_XS, /* 1419 */ IC_EVEX_L2_W_XD, /* 1420 */ IC_EVEX_L2_W_XD, /* 1421 */ IC_EVEX_L2_W_XD, /* 1422 */ IC_EVEX_L2_W_XD, /* 1423 */ IC_EVEX_L2_OPSIZE, /* 1424 */ IC_EVEX_L2_OPSIZE, /* 1425 */ IC_EVEX_L2_OPSIZE, /* 1426 */ IC_EVEX_L2_OPSIZE, /* 1427 */ IC_EVEX_L2_OPSIZE, /* 1428 */ IC_EVEX_L2_OPSIZE, /* 1429 */ IC_EVEX_L2_OPSIZE, /* 1430 */ IC_EVEX_L2_OPSIZE, /* 1431 */ IC_EVEX_L2_W_OPSIZE, /* 1432 */ IC_EVEX_L2_W_OPSIZE, /* 1433 */ IC_EVEX_L2_W_OPSIZE, /* 1434 */ IC_EVEX_L2_W_OPSIZE, /* 1435 */ IC_EVEX_L2_W_OPSIZE, /* 1436 */ IC_EVEX_L2_W_OPSIZE, /* 1437 */ IC_EVEX_L2_W_OPSIZE, /* 1438 */ IC_EVEX_L2_W_OPSIZE, /* 1439 */ IC_EVEX_L2, /* 1440 */ IC_EVEX_L2, /* 1441 */ IC_EVEX_L2_XS, /* 1442 */ IC_EVEX_L2_XS, /* 1443 */ IC_EVEX_L2_XD, /* 1444 */ IC_EVEX_L2_XD, /* 1445 */ IC_EVEX_L2_XD, /* 1446 */ IC_EVEX_L2_XD, /* 1447 */ IC_EVEX_L2_W, /* 1448 */ IC_EVEX_L2_W, /* 1449 */ IC_EVEX_L2_W_XS, /* 1450 */ IC_EVEX_L2_W_XS, /* 1451 */ IC_EVEX_L2_W_XD, /* 1452 */ IC_EVEX_L2_W_XD, /* 1453 */ IC_EVEX_L2_W_XD, /* 1454 */ IC_EVEX_L2_W_XD, /* 1455 */ IC_EVEX_L2_OPSIZE, /* 1456 */ IC_EVEX_L2_OPSIZE, /* 1457 */ IC_EVEX_L2_OPSIZE, /* 1458 */ IC_EVEX_L2_OPSIZE, /* 1459 */ IC_EVEX_L2_OPSIZE, /* 1460 */ IC_EVEX_L2_OPSIZE, /* 1461 */ IC_EVEX_L2_OPSIZE, /* 1462 */ IC_EVEX_L2_OPSIZE, /* 1463 */ IC_EVEX_L2_W_OPSIZE, /* 1464 */ IC_EVEX_L2_W_OPSIZE, /* 1465 */ IC_EVEX_L2_W_OPSIZE, /* 1466 */ IC_EVEX_L2_W_OPSIZE, /* 1467 */ IC_EVEX_L2_W_OPSIZE, /* 1468 */ IC_EVEX_L2_W_OPSIZE, /* 1469 */ IC_EVEX_L2_W_OPSIZE, /* 1470 */ IC_EVEX_L2_W_OPSIZE, /* 1471 */ IC_EVEX_L2, /* 1472 */ IC_EVEX_L2, /* 1473 */ IC_EVEX_L2_XS, /* 1474 */ IC_EVEX_L2_XS, /* 1475 */ IC_EVEX_L2_XD, /* 1476 */ IC_EVEX_L2_XD, /* 1477 */ IC_EVEX_L2_XD, /* 1478 */ IC_EVEX_L2_XD, /* 1479 */ IC_EVEX_L2_W, /* 1480 */ IC_EVEX_L2_W, /* 1481 */ IC_EVEX_L2_W_XS, /* 1482 */ IC_EVEX_L2_W_XS, /* 1483 */ IC_EVEX_L2_W_XD, /* 1484 */ IC_EVEX_L2_W_XD, /* 1485 */ IC_EVEX_L2_W_XD, /* 1486 */ IC_EVEX_L2_W_XD, /* 1487 */ IC_EVEX_L2_OPSIZE, /* 1488 */ IC_EVEX_L2_OPSIZE, /* 1489 */ IC_EVEX_L2_OPSIZE, /* 1490 */ IC_EVEX_L2_OPSIZE, /* 1491 */ IC_EVEX_L2_OPSIZE, /* 1492 */ IC_EVEX_L2_OPSIZE, /* 1493 */ IC_EVEX_L2_OPSIZE, /* 1494 */ IC_EVEX_L2_OPSIZE, /* 1495 */ IC_EVEX_L2_W_OPSIZE, /* 1496 */ IC_EVEX_L2_W_OPSIZE, /* 1497 */ IC_EVEX_L2_W_OPSIZE, /* 1498 */ IC_EVEX_L2_W_OPSIZE, /* 1499 */ IC_EVEX_L2_W_OPSIZE, /* 1500 */ IC_EVEX_L2_W_OPSIZE, /* 1501 */ IC_EVEX_L2_W_OPSIZE, /* 1502 */ IC_EVEX_L2_W_OPSIZE, /* 1503 */ IC_EVEX_L2, /* 1504 */ IC_EVEX_L2, /* 1505 */ IC_EVEX_L2_XS, /* 1506 */ IC_EVEX_L2_XS, /* 1507 */ IC_EVEX_L2_XD, /* 1508 */ IC_EVEX_L2_XD, /* 1509 */ IC_EVEX_L2_XD, /* 1510 */ IC_EVEX_L2_XD, /* 1511 */ IC_EVEX_L2_W, /* 1512 */ IC_EVEX_L2_W, /* 1513 */ IC_EVEX_L2_W_XS, /* 1514 */ IC_EVEX_L2_W_XS, /* 1515 */ IC_EVEX_L2_W_XD, /* 1516 */ IC_EVEX_L2_W_XD, /* 1517 */ IC_EVEX_L2_W_XD, /* 1518 */ IC_EVEX_L2_W_XD, /* 1519 */ IC_EVEX_L2_OPSIZE, /* 1520 */ IC_EVEX_L2_OPSIZE, /* 1521 */ IC_EVEX_L2_OPSIZE, /* 1522 */ IC_EVEX_L2_OPSIZE, /* 1523 */ IC_EVEX_L2_OPSIZE, /* 1524 */ IC_EVEX_L2_OPSIZE, /* 1525 */ IC_EVEX_L2_OPSIZE, /* 1526 */ IC_EVEX_L2_OPSIZE, /* 1527 */ IC_EVEX_L2_W_OPSIZE, /* 1528 */ IC_EVEX_L2_W_OPSIZE, /* 1529 */ IC_EVEX_L2_W_OPSIZE, /* 1530 */ IC_EVEX_L2_W_OPSIZE, /* 1531 */ IC_EVEX_L2_W_OPSIZE, /* 1532 */ IC_EVEX_L2_W_OPSIZE, /* 1533 */ IC_EVEX_L2_W_OPSIZE, /* 1534 */ IC_EVEX_L2_W_OPSIZE, /* 1535 */ IC, /* 1536 */ IC_64BIT, /* 1537 */ IC_XS, /* 1538 */ IC_64BIT_XS, /* 1539 */ IC_XD, /* 1540 */ IC_64BIT_XD, /* 1541 */ IC_XS, /* 1542 */ IC_64BIT_XS, /* 1543 */ IC, /* 1544 */ IC_64BIT_REXW, /* 1545 */ IC_XS, /* 1546 */ IC_64BIT_REXW_XS, /* 1547 */ IC_XD, /* 1548 */ IC_64BIT_REXW_XD, /* 1549 */ IC_XS, /* 1550 */ IC_64BIT_REXW_XS, /* 1551 */ IC_OPSIZE, /* 1552 */ IC_64BIT_OPSIZE, /* 1553 */ IC_XS_OPSIZE, /* 1554 */ IC_64BIT_XS_OPSIZE, /* 1555 */ IC_XD_OPSIZE, /* 1556 */ IC_64BIT_XD_OPSIZE, /* 1557 */ IC_XS_OPSIZE, /* 1558 */ IC_64BIT_XD_OPSIZE, /* 1559 */ IC_OPSIZE, /* 1560 */ IC_64BIT_REXW_OPSIZE, /* 1561 */ IC_XS_OPSIZE, /* 1562 */ IC_64BIT_REXW_XS, /* 1563 */ IC_XD_OPSIZE, /* 1564 */ IC_64BIT_REXW_XD, /* 1565 */ IC_XS_OPSIZE, /* 1566 */ IC_64BIT_REXW_XS, /* 1567 */ IC_ADSIZE, /* 1568 */ IC_64BIT_ADSIZE, /* 1569 */ IC_XS_ADSIZE, /* 1570 */ IC_64BIT_XS_ADSIZE, /* 1571 */ IC_XD_ADSIZE, /* 1572 */ IC_64BIT_XD_ADSIZE, /* 1573 */ IC_XS_ADSIZE, /* 1574 */ IC_64BIT_XD_ADSIZE, /* 1575 */ IC_ADSIZE, /* 1576 */ IC_64BIT_REXW_ADSIZE, /* 1577 */ IC_XS_ADSIZE, /* 1578 */ IC_64BIT_REXW_XS, /* 1579 */ IC_XD_ADSIZE, /* 1580 */ IC_64BIT_REXW_XD, /* 1581 */ IC_XS_ADSIZE, /* 1582 */ IC_64BIT_REXW_XS, /* 1583 */ IC_OPSIZE_ADSIZE, /* 1584 */ IC_64BIT_OPSIZE_ADSIZE, /* 1585 */ IC_XS_OPSIZE, /* 1586 */ IC_64BIT_XS_OPSIZE, /* 1587 */ IC_XD_OPSIZE, /* 1588 */ IC_64BIT_XD_OPSIZE, /* 1589 */ IC_XS_OPSIZE, /* 1590 */ IC_64BIT_XD_OPSIZE, /* 1591 */ IC_OPSIZE_ADSIZE, /* 1592 */ IC_64BIT_REXW_OPSIZE, /* 1593 */ IC_XS_OPSIZE, /* 1594 */ IC_64BIT_REXW_XS, /* 1595 */ IC_XD_OPSIZE, /* 1596 */ IC_64BIT_REXW_XD, /* 1597 */ IC_XS_OPSIZE, /* 1598 */ IC_64BIT_REXW_XS, /* 1599 */ IC_VEX, /* 1600 */ IC_VEX, /* 1601 */ IC_VEX_XS, /* 1602 */ IC_VEX_XS, /* 1603 */ IC_VEX_XD, /* 1604 */ IC_VEX_XD, /* 1605 */ IC_VEX_XD, /* 1606 */ IC_VEX_XD, /* 1607 */ IC_VEX_W, /* 1608 */ IC_VEX_W, /* 1609 */ IC_VEX_W_XS, /* 1610 */ IC_VEX_W_XS, /* 1611 */ IC_VEX_W_XD, /* 1612 */ IC_VEX_W_XD, /* 1613 */ IC_VEX_W_XD, /* 1614 */ IC_VEX_W_XD, /* 1615 */ IC_VEX_OPSIZE, /* 1616 */ IC_VEX_OPSIZE, /* 1617 */ IC_VEX_OPSIZE, /* 1618 */ IC_VEX_OPSIZE, /* 1619 */ IC_VEX_OPSIZE, /* 1620 */ IC_VEX_OPSIZE, /* 1621 */ IC_VEX_OPSIZE, /* 1622 */ IC_VEX_OPSIZE, /* 1623 */ IC_VEX_W_OPSIZE, /* 1624 */ IC_VEX_W_OPSIZE, /* 1625 */ IC_VEX_W_OPSIZE, /* 1626 */ IC_VEX_W_OPSIZE, /* 1627 */ IC_VEX_W_OPSIZE, /* 1628 */ IC_VEX_W_OPSIZE, /* 1629 */ IC_VEX_W_OPSIZE, /* 1630 */ IC_VEX_W_OPSIZE, /* 1631 */ IC_VEX, /* 1632 */ IC_VEX, /* 1633 */ IC_VEX_XS, /* 1634 */ IC_VEX_XS, /* 1635 */ IC_VEX_XD, /* 1636 */ IC_VEX_XD, /* 1637 */ IC_VEX_XD, /* 1638 */ IC_VEX_XD, /* 1639 */ IC_VEX_W, /* 1640 */ IC_VEX_W, /* 1641 */ IC_VEX_W_XS, /* 1642 */ IC_VEX_W_XS, /* 1643 */ IC_VEX_W_XD, /* 1644 */ IC_VEX_W_XD, /* 1645 */ IC_VEX_W_XD, /* 1646 */ IC_VEX_W_XD, /* 1647 */ IC_VEX_OPSIZE, /* 1648 */ IC_VEX_OPSIZE, /* 1649 */ IC_VEX_OPSIZE, /* 1650 */ IC_VEX_OPSIZE, /* 1651 */ IC_VEX_OPSIZE, /* 1652 */ IC_VEX_OPSIZE, /* 1653 */ IC_VEX_OPSIZE, /* 1654 */ IC_VEX_OPSIZE, /* 1655 */ IC_VEX_W_OPSIZE, /* 1656 */ IC_VEX_W_OPSIZE, /* 1657 */ IC_VEX_W_OPSIZE, /* 1658 */ IC_VEX_W_OPSIZE, /* 1659 */ IC_VEX_W_OPSIZE, /* 1660 */ IC_VEX_W_OPSIZE, /* 1661 */ IC_VEX_W_OPSIZE, /* 1662 */ IC_VEX_W_OPSIZE, /* 1663 */ IC_VEX_L, /* 1664 */ IC_VEX_L, /* 1665 */ IC_VEX_L_XS, /* 1666 */ IC_VEX_L_XS, /* 1667 */ IC_VEX_L_XD, /* 1668 */ IC_VEX_L_XD, /* 1669 */ IC_VEX_L_XD, /* 1670 */ IC_VEX_L_XD, /* 1671 */ IC_VEX_L_W, /* 1672 */ IC_VEX_L_W, /* 1673 */ IC_VEX_L_W_XS, /* 1674 */ IC_VEX_L_W_XS, /* 1675 */ IC_VEX_L_W_XD, /* 1676 */ IC_VEX_L_W_XD, /* 1677 */ IC_VEX_L_W_XD, /* 1678 */ IC_VEX_L_W_XD, /* 1679 */ IC_VEX_L_OPSIZE, /* 1680 */ IC_VEX_L_OPSIZE, /* 1681 */ IC_VEX_L_OPSIZE, /* 1682 */ IC_VEX_L_OPSIZE, /* 1683 */ IC_VEX_L_OPSIZE, /* 1684 */ IC_VEX_L_OPSIZE, /* 1685 */ IC_VEX_L_OPSIZE, /* 1686 */ IC_VEX_L_OPSIZE, /* 1687 */ IC_VEX_L_W_OPSIZE, /* 1688 */ IC_VEX_L_W_OPSIZE, /* 1689 */ IC_VEX_L_W_OPSIZE, /* 1690 */ IC_VEX_L_W_OPSIZE, /* 1691 */ IC_VEX_L_W_OPSIZE, /* 1692 */ IC_VEX_L_W_OPSIZE, /* 1693 */ IC_VEX_L_W_OPSIZE, /* 1694 */ IC_VEX_L_W_OPSIZE, /* 1695 */ IC_VEX_L, /* 1696 */ IC_VEX_L, /* 1697 */ IC_VEX_L_XS, /* 1698 */ IC_VEX_L_XS, /* 1699 */ IC_VEX_L_XD, /* 1700 */ IC_VEX_L_XD, /* 1701 */ IC_VEX_L_XD, /* 1702 */ IC_VEX_L_XD, /* 1703 */ IC_VEX_L_W, /* 1704 */ IC_VEX_L_W, /* 1705 */ IC_VEX_L_W_XS, /* 1706 */ IC_VEX_L_W_XS, /* 1707 */ IC_VEX_L_W_XD, /* 1708 */ IC_VEX_L_W_XD, /* 1709 */ IC_VEX_L_W_XD, /* 1710 */ IC_VEX_L_W_XD, /* 1711 */ IC_VEX_L_OPSIZE, /* 1712 */ IC_VEX_L_OPSIZE, /* 1713 */ IC_VEX_L_OPSIZE, /* 1714 */ IC_VEX_L_OPSIZE, /* 1715 */ IC_VEX_L_OPSIZE, /* 1716 */ IC_VEX_L_OPSIZE, /* 1717 */ IC_VEX_L_OPSIZE, /* 1718 */ IC_VEX_L_OPSIZE, /* 1719 */ IC_VEX_L_W_OPSIZE, /* 1720 */ IC_VEX_L_W_OPSIZE, /* 1721 */ IC_VEX_L_W_OPSIZE, /* 1722 */ IC_VEX_L_W_OPSIZE, /* 1723 */ IC_VEX_L_W_OPSIZE, /* 1724 */ IC_VEX_L_W_OPSIZE, /* 1725 */ IC_VEX_L_W_OPSIZE, /* 1726 */ IC_VEX_L_W_OPSIZE, /* 1727 */ IC_VEX_L, /* 1728 */ IC_VEX_L, /* 1729 */ IC_VEX_L_XS, /* 1730 */ IC_VEX_L_XS, /* 1731 */ IC_VEX_L_XD, /* 1732 */ IC_VEX_L_XD, /* 1733 */ IC_VEX_L_XD, /* 1734 */ IC_VEX_L_XD, /* 1735 */ IC_VEX_L_W, /* 1736 */ IC_VEX_L_W, /* 1737 */ IC_VEX_L_W_XS, /* 1738 */ IC_VEX_L_W_XS, /* 1739 */ IC_VEX_L_W_XD, /* 1740 */ IC_VEX_L_W_XD, /* 1741 */ IC_VEX_L_W_XD, /* 1742 */ IC_VEX_L_W_XD, /* 1743 */ IC_VEX_L_OPSIZE, /* 1744 */ IC_VEX_L_OPSIZE, /* 1745 */ IC_VEX_L_OPSIZE, /* 1746 */ IC_VEX_L_OPSIZE, /* 1747 */ IC_VEX_L_OPSIZE, /* 1748 */ IC_VEX_L_OPSIZE, /* 1749 */ IC_VEX_L_OPSIZE, /* 1750 */ IC_VEX_L_OPSIZE, /* 1751 */ IC_VEX_L_W_OPSIZE, /* 1752 */ IC_VEX_L_W_OPSIZE, /* 1753 */ IC_VEX_L_W_OPSIZE, /* 1754 */ IC_VEX_L_W_OPSIZE, /* 1755 */ IC_VEX_L_W_OPSIZE, /* 1756 */ IC_VEX_L_W_OPSIZE, /* 1757 */ IC_VEX_L_W_OPSIZE, /* 1758 */ IC_VEX_L_W_OPSIZE, /* 1759 */ IC_VEX_L, /* 1760 */ IC_VEX_L, /* 1761 */ IC_VEX_L_XS, /* 1762 */ IC_VEX_L_XS, /* 1763 */ IC_VEX_L_XD, /* 1764 */ IC_VEX_L_XD, /* 1765 */ IC_VEX_L_XD, /* 1766 */ IC_VEX_L_XD, /* 1767 */ IC_VEX_L_W, /* 1768 */ IC_VEX_L_W, /* 1769 */ IC_VEX_L_W_XS, /* 1770 */ IC_VEX_L_W_XS, /* 1771 */ IC_VEX_L_W_XD, /* 1772 */ IC_VEX_L_W_XD, /* 1773 */ IC_VEX_L_W_XD, /* 1774 */ IC_VEX_L_W_XD, /* 1775 */ IC_VEX_L_OPSIZE, /* 1776 */ IC_VEX_L_OPSIZE, /* 1777 */ IC_VEX_L_OPSIZE, /* 1778 */ IC_VEX_L_OPSIZE, /* 1779 */ IC_VEX_L_OPSIZE, /* 1780 */ IC_VEX_L_OPSIZE, /* 1781 */ IC_VEX_L_OPSIZE, /* 1782 */ IC_VEX_L_OPSIZE, /* 1783 */ IC_VEX_L_W_OPSIZE, /* 1784 */ IC_VEX_L_W_OPSIZE, /* 1785 */ IC_VEX_L_W_OPSIZE, /* 1786 */ IC_VEX_L_W_OPSIZE, /* 1787 */ IC_VEX_L_W_OPSIZE, /* 1788 */ IC_VEX_L_W_OPSIZE, /* 1789 */ IC_VEX_L_W_OPSIZE, /* 1790 */ IC_VEX_L_W_OPSIZE, /* 1791 */ IC_EVEX_L2, /* 1792 */ IC_EVEX_L2, /* 1793 */ IC_EVEX_L2_XS, /* 1794 */ IC_EVEX_L2_XS, /* 1795 */ IC_EVEX_L2_XD, /* 1796 */ IC_EVEX_L2_XD, /* 1797 */ IC_EVEX_L2_XD, /* 1798 */ IC_EVEX_L2_XD, /* 1799 */ IC_EVEX_L2_W, /* 1800 */ IC_EVEX_L2_W, /* 1801 */ IC_EVEX_L2_W_XS, /* 1802 */ IC_EVEX_L2_W_XS, /* 1803 */ IC_EVEX_L2_W_XD, /* 1804 */ IC_EVEX_L2_W_XD, /* 1805 */ IC_EVEX_L2_W_XD, /* 1806 */ IC_EVEX_L2_W_XD, /* 1807 */ IC_EVEX_L2_OPSIZE, /* 1808 */ IC_EVEX_L2_OPSIZE, /* 1809 */ IC_EVEX_L2_OPSIZE, /* 1810 */ IC_EVEX_L2_OPSIZE, /* 1811 */ IC_EVEX_L2_OPSIZE, /* 1812 */ IC_EVEX_L2_OPSIZE, /* 1813 */ IC_EVEX_L2_OPSIZE, /* 1814 */ IC_EVEX_L2_OPSIZE, /* 1815 */ IC_EVEX_L2_W_OPSIZE, /* 1816 */ IC_EVEX_L2_W_OPSIZE, /* 1817 */ IC_EVEX_L2_W_OPSIZE, /* 1818 */ IC_EVEX_L2_W_OPSIZE, /* 1819 */ IC_EVEX_L2_W_OPSIZE, /* 1820 */ IC_EVEX_L2_W_OPSIZE, /* 1821 */ IC_EVEX_L2_W_OPSIZE, /* 1822 */ IC_EVEX_L2_W_OPSIZE, /* 1823 */ IC_EVEX_L2, /* 1824 */ IC_EVEX_L2, /* 1825 */ IC_EVEX_L2_XS, /* 1826 */ IC_EVEX_L2_XS, /* 1827 */ IC_EVEX_L2_XD, /* 1828 */ IC_EVEX_L2_XD, /* 1829 */ IC_EVEX_L2_XD, /* 1830 */ IC_EVEX_L2_XD, /* 1831 */ IC_EVEX_L2_W, /* 1832 */ IC_EVEX_L2_W, /* 1833 */ IC_EVEX_L2_W_XS, /* 1834 */ IC_EVEX_L2_W_XS, /* 1835 */ IC_EVEX_L2_W_XD, /* 1836 */ IC_EVEX_L2_W_XD, /* 1837 */ IC_EVEX_L2_W_XD, /* 1838 */ IC_EVEX_L2_W_XD, /* 1839 */ IC_EVEX_L2_OPSIZE, /* 1840 */ IC_EVEX_L2_OPSIZE, /* 1841 */ IC_EVEX_L2_OPSIZE, /* 1842 */ IC_EVEX_L2_OPSIZE, /* 1843 */ IC_EVEX_L2_OPSIZE, /* 1844 */ IC_EVEX_L2_OPSIZE, /* 1845 */ IC_EVEX_L2_OPSIZE, /* 1846 */ IC_EVEX_L2_OPSIZE, /* 1847 */ IC_EVEX_L2_W_OPSIZE, /* 1848 */ IC_EVEX_L2_W_OPSIZE, /* 1849 */ IC_EVEX_L2_W_OPSIZE, /* 1850 */ IC_EVEX_L2_W_OPSIZE, /* 1851 */ IC_EVEX_L2_W_OPSIZE, /* 1852 */ IC_EVEX_L2_W_OPSIZE, /* 1853 */ IC_EVEX_L2_W_OPSIZE, /* 1854 */ IC_EVEX_L2_W_OPSIZE, /* 1855 */ IC_EVEX_L2, /* 1856 */ IC_EVEX_L2, /* 1857 */ IC_EVEX_L2_XS, /* 1858 */ IC_EVEX_L2_XS, /* 1859 */ IC_EVEX_L2_XD, /* 1860 */ IC_EVEX_L2_XD, /* 1861 */ IC_EVEX_L2_XD, /* 1862 */ IC_EVEX_L2_XD, /* 1863 */ IC_EVEX_L2_W, /* 1864 */ IC_EVEX_L2_W, /* 1865 */ IC_EVEX_L2_W_XS, /* 1866 */ IC_EVEX_L2_W_XS, /* 1867 */ IC_EVEX_L2_W_XD, /* 1868 */ IC_EVEX_L2_W_XD, /* 1869 */ IC_EVEX_L2_W_XD, /* 1870 */ IC_EVEX_L2_W_XD, /* 1871 */ IC_EVEX_L2_OPSIZE, /* 1872 */ IC_EVEX_L2_OPSIZE, /* 1873 */ IC_EVEX_L2_OPSIZE, /* 1874 */ IC_EVEX_L2_OPSIZE, /* 1875 */ IC_EVEX_L2_OPSIZE, /* 1876 */ IC_EVEX_L2_OPSIZE, /* 1877 */ IC_EVEX_L2_OPSIZE, /* 1878 */ IC_EVEX_L2_OPSIZE, /* 1879 */ IC_EVEX_L2_W_OPSIZE, /* 1880 */ IC_EVEX_L2_W_OPSIZE, /* 1881 */ IC_EVEX_L2_W_OPSIZE, /* 1882 */ IC_EVEX_L2_W_OPSIZE, /* 1883 */ IC_EVEX_L2_W_OPSIZE, /* 1884 */ IC_EVEX_L2_W_OPSIZE, /* 1885 */ IC_EVEX_L2_W_OPSIZE, /* 1886 */ IC_EVEX_L2_W_OPSIZE, /* 1887 */ IC_EVEX_L2, /* 1888 */ IC_EVEX_L2, /* 1889 */ IC_EVEX_L2_XS, /* 1890 */ IC_EVEX_L2_XS, /* 1891 */ IC_EVEX_L2_XD, /* 1892 */ IC_EVEX_L2_XD, /* 1893 */ IC_EVEX_L2_XD, /* 1894 */ IC_EVEX_L2_XD, /* 1895 */ IC_EVEX_L2_W, /* 1896 */ IC_EVEX_L2_W, /* 1897 */ IC_EVEX_L2_W_XS, /* 1898 */ IC_EVEX_L2_W_XS, /* 1899 */ IC_EVEX_L2_W_XD, /* 1900 */ IC_EVEX_L2_W_XD, /* 1901 */ IC_EVEX_L2_W_XD, /* 1902 */ IC_EVEX_L2_W_XD, /* 1903 */ IC_EVEX_L2_OPSIZE, /* 1904 */ IC_EVEX_L2_OPSIZE, /* 1905 */ IC_EVEX_L2_OPSIZE, /* 1906 */ IC_EVEX_L2_OPSIZE, /* 1907 */ IC_EVEX_L2_OPSIZE, /* 1908 */ IC_EVEX_L2_OPSIZE, /* 1909 */ IC_EVEX_L2_OPSIZE, /* 1910 */ IC_EVEX_L2_OPSIZE, /* 1911 */ IC_EVEX_L2_W_OPSIZE, /* 1912 */ IC_EVEX_L2_W_OPSIZE, /* 1913 */ IC_EVEX_L2_W_OPSIZE, /* 1914 */ IC_EVEX_L2_W_OPSIZE, /* 1915 */ IC_EVEX_L2_W_OPSIZE, /* 1916 */ IC_EVEX_L2_W_OPSIZE, /* 1917 */ IC_EVEX_L2_W_OPSIZE, /* 1918 */ IC_EVEX_L2_W_OPSIZE, /* 1919 */ IC_EVEX_L2, /* 1920 */ IC_EVEX_L2, /* 1921 */ IC_EVEX_L2_XS, /* 1922 */ IC_EVEX_L2_XS, /* 1923 */ IC_EVEX_L2_XD, /* 1924 */ IC_EVEX_L2_XD, /* 1925 */ IC_EVEX_L2_XD, /* 1926 */ IC_EVEX_L2_XD, /* 1927 */ IC_EVEX_L2_W, /* 1928 */ IC_EVEX_L2_W, /* 1929 */ IC_EVEX_L2_W_XS, /* 1930 */ IC_EVEX_L2_W_XS, /* 1931 */ IC_EVEX_L2_W_XD, /* 1932 */ IC_EVEX_L2_W_XD, /* 1933 */ IC_EVEX_L2_W_XD, /* 1934 */ IC_EVEX_L2_W_XD, /* 1935 */ IC_EVEX_L2_OPSIZE, /* 1936 */ IC_EVEX_L2_OPSIZE, /* 1937 */ IC_EVEX_L2_OPSIZE, /* 1938 */ IC_EVEX_L2_OPSIZE, /* 1939 */ IC_EVEX_L2_OPSIZE, /* 1940 */ IC_EVEX_L2_OPSIZE, /* 1941 */ IC_EVEX_L2_OPSIZE, /* 1942 */ IC_EVEX_L2_OPSIZE, /* 1943 */ IC_EVEX_L2_W_OPSIZE, /* 1944 */ IC_EVEX_L2_W_OPSIZE, /* 1945 */ IC_EVEX_L2_W_OPSIZE, /* 1946 */ IC_EVEX_L2_W_OPSIZE, /* 1947 */ IC_EVEX_L2_W_OPSIZE, /* 1948 */ IC_EVEX_L2_W_OPSIZE, /* 1949 */ IC_EVEX_L2_W_OPSIZE, /* 1950 */ IC_EVEX_L2_W_OPSIZE, /* 1951 */ IC_EVEX_L2, /* 1952 */ IC_EVEX_L2, /* 1953 */ IC_EVEX_L2_XS, /* 1954 */ IC_EVEX_L2_XS, /* 1955 */ IC_EVEX_L2_XD, /* 1956 */ IC_EVEX_L2_XD, /* 1957 */ IC_EVEX_L2_XD, /* 1958 */ IC_EVEX_L2_XD, /* 1959 */ IC_EVEX_L2_W, /* 1960 */ IC_EVEX_L2_W, /* 1961 */ IC_EVEX_L2_W_XS, /* 1962 */ IC_EVEX_L2_W_XS, /* 1963 */ IC_EVEX_L2_W_XD, /* 1964 */ IC_EVEX_L2_W_XD, /* 1965 */ IC_EVEX_L2_W_XD, /* 1966 */ IC_EVEX_L2_W_XD, /* 1967 */ IC_EVEX_L2_OPSIZE, /* 1968 */ IC_EVEX_L2_OPSIZE, /* 1969 */ IC_EVEX_L2_OPSIZE, /* 1970 */ IC_EVEX_L2_OPSIZE, /* 1971 */ IC_EVEX_L2_OPSIZE, /* 1972 */ IC_EVEX_L2_OPSIZE, /* 1973 */ IC_EVEX_L2_OPSIZE, /* 1974 */ IC_EVEX_L2_OPSIZE, /* 1975 */ IC_EVEX_L2_W_OPSIZE, /* 1976 */ IC_EVEX_L2_W_OPSIZE, /* 1977 */ IC_EVEX_L2_W_OPSIZE, /* 1978 */ IC_EVEX_L2_W_OPSIZE, /* 1979 */ IC_EVEX_L2_W_OPSIZE, /* 1980 */ IC_EVEX_L2_W_OPSIZE, /* 1981 */ IC_EVEX_L2_W_OPSIZE, /* 1982 */ IC_EVEX_L2_W_OPSIZE, /* 1983 */ IC_EVEX_L2, /* 1984 */ IC_EVEX_L2, /* 1985 */ IC_EVEX_L2_XS, /* 1986 */ IC_EVEX_L2_XS, /* 1987 */ IC_EVEX_L2_XD, /* 1988 */ IC_EVEX_L2_XD, /* 1989 */ IC_EVEX_L2_XD, /* 1990 */ IC_EVEX_L2_XD, /* 1991 */ IC_EVEX_L2_W, /* 1992 */ IC_EVEX_L2_W, /* 1993 */ IC_EVEX_L2_W_XS, /* 1994 */ IC_EVEX_L2_W_XS, /* 1995 */ IC_EVEX_L2_W_XD, /* 1996 */ IC_EVEX_L2_W_XD, /* 1997 */ IC_EVEX_L2_W_XD, /* 1998 */ IC_EVEX_L2_W_XD, /* 1999 */ IC_EVEX_L2_OPSIZE, /* 2000 */ IC_EVEX_L2_OPSIZE, /* 2001 */ IC_EVEX_L2_OPSIZE, /* 2002 */ IC_EVEX_L2_OPSIZE, /* 2003 */ IC_EVEX_L2_OPSIZE, /* 2004 */ IC_EVEX_L2_OPSIZE, /* 2005 */ IC_EVEX_L2_OPSIZE, /* 2006 */ IC_EVEX_L2_OPSIZE, /* 2007 */ IC_EVEX_L2_W_OPSIZE, /* 2008 */ IC_EVEX_L2_W_OPSIZE, /* 2009 */ IC_EVEX_L2_W_OPSIZE, /* 2010 */ IC_EVEX_L2_W_OPSIZE, /* 2011 */ IC_EVEX_L2_W_OPSIZE, /* 2012 */ IC_EVEX_L2_W_OPSIZE, /* 2013 */ IC_EVEX_L2_W_OPSIZE, /* 2014 */ IC_EVEX_L2_W_OPSIZE, /* 2015 */ IC_EVEX_L2, /* 2016 */ IC_EVEX_L2, /* 2017 */ IC_EVEX_L2_XS, /* 2018 */ IC_EVEX_L2_XS, /* 2019 */ IC_EVEX_L2_XD, /* 2020 */ IC_EVEX_L2_XD, /* 2021 */ IC_EVEX_L2_XD, /* 2022 */ IC_EVEX_L2_XD, /* 2023 */ IC_EVEX_L2_W, /* 2024 */ IC_EVEX_L2_W, /* 2025 */ IC_EVEX_L2_W_XS, /* 2026 */ IC_EVEX_L2_W_XS, /* 2027 */ IC_EVEX_L2_W_XD, /* 2028 */ IC_EVEX_L2_W_XD, /* 2029 */ IC_EVEX_L2_W_XD, /* 2030 */ IC_EVEX_L2_W_XD, /* 2031 */ IC_EVEX_L2_OPSIZE, /* 2032 */ IC_EVEX_L2_OPSIZE, /* 2033 */ IC_EVEX_L2_OPSIZE, /* 2034 */ IC_EVEX_L2_OPSIZE, /* 2035 */ IC_EVEX_L2_OPSIZE, /* 2036 */ IC_EVEX_L2_OPSIZE, /* 2037 */ IC_EVEX_L2_OPSIZE, /* 2038 */ IC_EVEX_L2_OPSIZE, /* 2039 */ IC_EVEX_L2_W_OPSIZE, /* 2040 */ IC_EVEX_L2_W_OPSIZE, /* 2041 */ IC_EVEX_L2_W_OPSIZE, /* 2042 */ IC_EVEX_L2_W_OPSIZE, /* 2043 */ IC_EVEX_L2_W_OPSIZE, /* 2044 */ IC_EVEX_L2_W_OPSIZE, /* 2045 */ IC_EVEX_L2_W_OPSIZE, /* 2046 */ IC_EVEX_L2_W_OPSIZE, /* 2047 */ IC, /* 2048 */ IC_64BIT, /* 2049 */ IC_XS, /* 2050 */ IC_64BIT_XS, /* 2051 */ IC_XD, /* 2052 */ IC_64BIT_XD, /* 2053 */ IC_XS, /* 2054 */ IC_64BIT_XS, /* 2055 */ IC, /* 2056 */ IC_64BIT_REXW, /* 2057 */ IC_XS, /* 2058 */ IC_64BIT_REXW_XS, /* 2059 */ IC_XD, /* 2060 */ IC_64BIT_REXW_XD, /* 2061 */ IC_XS, /* 2062 */ IC_64BIT_REXW_XS, /* 2063 */ IC_OPSIZE, /* 2064 */ IC_64BIT_OPSIZE, /* 2065 */ IC_XS_OPSIZE, /* 2066 */ IC_64BIT_XS_OPSIZE, /* 2067 */ IC_XD_OPSIZE, /* 2068 */ IC_64BIT_XD_OPSIZE, /* 2069 */ IC_XS_OPSIZE, /* 2070 */ IC_64BIT_XD_OPSIZE, /* 2071 */ IC_OPSIZE, /* 2072 */ IC_64BIT_REXW_OPSIZE, /* 2073 */ IC_XS_OPSIZE, /* 2074 */ IC_64BIT_REXW_XS, /* 2075 */ IC_XD_OPSIZE, /* 2076 */ IC_64BIT_REXW_XD, /* 2077 */ IC_XS_OPSIZE, /* 2078 */ IC_64BIT_REXW_XS, /* 2079 */ IC_ADSIZE, /* 2080 */ IC_64BIT_ADSIZE, /* 2081 */ IC_XS_ADSIZE, /* 2082 */ IC_64BIT_XS_ADSIZE, /* 2083 */ IC_XD_ADSIZE, /* 2084 */ IC_64BIT_XD_ADSIZE, /* 2085 */ IC_XS_ADSIZE, /* 2086 */ IC_64BIT_XD_ADSIZE, /* 2087 */ IC_ADSIZE, /* 2088 */ IC_64BIT_REXW_ADSIZE, /* 2089 */ IC_XS_ADSIZE, /* 2090 */ IC_64BIT_REXW_XS, /* 2091 */ IC_XD_ADSIZE, /* 2092 */ IC_64BIT_REXW_XD, /* 2093 */ IC_XS_ADSIZE, /* 2094 */ IC_64BIT_REXW_XS, /* 2095 */ IC_OPSIZE_ADSIZE, /* 2096 */ IC_64BIT_OPSIZE_ADSIZE, /* 2097 */ IC_XS_OPSIZE, /* 2098 */ IC_64BIT_XS_OPSIZE, /* 2099 */ IC_XD_OPSIZE, /* 2100 */ IC_64BIT_XD_OPSIZE, /* 2101 */ IC_XS_OPSIZE, /* 2102 */ IC_64BIT_XD_OPSIZE, /* 2103 */ IC_OPSIZE_ADSIZE, /* 2104 */ IC_64BIT_REXW_OPSIZE, /* 2105 */ IC_XS_OPSIZE, /* 2106 */ IC_64BIT_REXW_XS, /* 2107 */ IC_XD_OPSIZE, /* 2108 */ IC_64BIT_REXW_XD, /* 2109 */ IC_XS_OPSIZE, /* 2110 */ IC_64BIT_REXW_XS, /* 2111 */ IC_VEX, /* 2112 */ IC_VEX, /* 2113 */ IC_VEX_XS, /* 2114 */ IC_VEX_XS, /* 2115 */ IC_VEX_XD, /* 2116 */ IC_VEX_XD, /* 2117 */ IC_VEX_XD, /* 2118 */ IC_VEX_XD, /* 2119 */ IC_VEX_W, /* 2120 */ IC_VEX_W, /* 2121 */ IC_VEX_W_XS, /* 2122 */ IC_VEX_W_XS, /* 2123 */ IC_VEX_W_XD, /* 2124 */ IC_VEX_W_XD, /* 2125 */ IC_VEX_W_XD, /* 2126 */ IC_VEX_W_XD, /* 2127 */ IC_VEX_OPSIZE, /* 2128 */ IC_VEX_OPSIZE, /* 2129 */ IC_VEX_OPSIZE, /* 2130 */ IC_VEX_OPSIZE, /* 2131 */ IC_VEX_OPSIZE, /* 2132 */ IC_VEX_OPSIZE, /* 2133 */ IC_VEX_OPSIZE, /* 2134 */ IC_VEX_OPSIZE, /* 2135 */ IC_VEX_W_OPSIZE, /* 2136 */ IC_VEX_W_OPSIZE, /* 2137 */ IC_VEX_W_OPSIZE, /* 2138 */ IC_VEX_W_OPSIZE, /* 2139 */ IC_VEX_W_OPSIZE, /* 2140 */ IC_VEX_W_OPSIZE, /* 2141 */ IC_VEX_W_OPSIZE, /* 2142 */ IC_VEX_W_OPSIZE, /* 2143 */ IC_VEX, /* 2144 */ IC_VEX, /* 2145 */ IC_VEX_XS, /* 2146 */ IC_VEX_XS, /* 2147 */ IC_VEX_XD, /* 2148 */ IC_VEX_XD, /* 2149 */ IC_VEX_XD, /* 2150 */ IC_VEX_XD, /* 2151 */ IC_VEX_W, /* 2152 */ IC_VEX_W, /* 2153 */ IC_VEX_W_XS, /* 2154 */ IC_VEX_W_XS, /* 2155 */ IC_VEX_W_XD, /* 2156 */ IC_VEX_W_XD, /* 2157 */ IC_VEX_W_XD, /* 2158 */ IC_VEX_W_XD, /* 2159 */ IC_VEX_OPSIZE, /* 2160 */ IC_VEX_OPSIZE, /* 2161 */ IC_VEX_OPSIZE, /* 2162 */ IC_VEX_OPSIZE, /* 2163 */ IC_VEX_OPSIZE, /* 2164 */ IC_VEX_OPSIZE, /* 2165 */ IC_VEX_OPSIZE, /* 2166 */ IC_VEX_OPSIZE, /* 2167 */ IC_VEX_W_OPSIZE, /* 2168 */ IC_VEX_W_OPSIZE, /* 2169 */ IC_VEX_W_OPSIZE, /* 2170 */ IC_VEX_W_OPSIZE, /* 2171 */ IC_VEX_W_OPSIZE, /* 2172 */ IC_VEX_W_OPSIZE, /* 2173 */ IC_VEX_W_OPSIZE, /* 2174 */ IC_VEX_W_OPSIZE, /* 2175 */ IC_VEX_L, /* 2176 */ IC_VEX_L, /* 2177 */ IC_VEX_L_XS, /* 2178 */ IC_VEX_L_XS, /* 2179 */ IC_VEX_L_XD, /* 2180 */ IC_VEX_L_XD, /* 2181 */ IC_VEX_L_XD, /* 2182 */ IC_VEX_L_XD, /* 2183 */ IC_VEX_L_W, /* 2184 */ IC_VEX_L_W, /* 2185 */ IC_VEX_L_W_XS, /* 2186 */ IC_VEX_L_W_XS, /* 2187 */ IC_VEX_L_W_XD, /* 2188 */ IC_VEX_L_W_XD, /* 2189 */ IC_VEX_L_W_XD, /* 2190 */ IC_VEX_L_W_XD, /* 2191 */ IC_VEX_L_OPSIZE, /* 2192 */ IC_VEX_L_OPSIZE, /* 2193 */ IC_VEX_L_OPSIZE, /* 2194 */ IC_VEX_L_OPSIZE, /* 2195 */ IC_VEX_L_OPSIZE, /* 2196 */ IC_VEX_L_OPSIZE, /* 2197 */ IC_VEX_L_OPSIZE, /* 2198 */ IC_VEX_L_OPSIZE, /* 2199 */ IC_VEX_L_W_OPSIZE, /* 2200 */ IC_VEX_L_W_OPSIZE, /* 2201 */ IC_VEX_L_W_OPSIZE, /* 2202 */ IC_VEX_L_W_OPSIZE, /* 2203 */ IC_VEX_L_W_OPSIZE, /* 2204 */ IC_VEX_L_W_OPSIZE, /* 2205 */ IC_VEX_L_W_OPSIZE, /* 2206 */ IC_VEX_L_W_OPSIZE, /* 2207 */ IC_VEX_L, /* 2208 */ IC_VEX_L, /* 2209 */ IC_VEX_L_XS, /* 2210 */ IC_VEX_L_XS, /* 2211 */ IC_VEX_L_XD, /* 2212 */ IC_VEX_L_XD, /* 2213 */ IC_VEX_L_XD, /* 2214 */ IC_VEX_L_XD, /* 2215 */ IC_VEX_L_W, /* 2216 */ IC_VEX_L_W, /* 2217 */ IC_VEX_L_W_XS, /* 2218 */ IC_VEX_L_W_XS, /* 2219 */ IC_VEX_L_W_XD, /* 2220 */ IC_VEX_L_W_XD, /* 2221 */ IC_VEX_L_W_XD, /* 2222 */ IC_VEX_L_W_XD, /* 2223 */ IC_VEX_L_OPSIZE, /* 2224 */ IC_VEX_L_OPSIZE, /* 2225 */ IC_VEX_L_OPSIZE, /* 2226 */ IC_VEX_L_OPSIZE, /* 2227 */ IC_VEX_L_OPSIZE, /* 2228 */ IC_VEX_L_OPSIZE, /* 2229 */ IC_VEX_L_OPSIZE, /* 2230 */ IC_VEX_L_OPSIZE, /* 2231 */ IC_VEX_L_W_OPSIZE, /* 2232 */ IC_VEX_L_W_OPSIZE, /* 2233 */ IC_VEX_L_W_OPSIZE, /* 2234 */ IC_VEX_L_W_OPSIZE, /* 2235 */ IC_VEX_L_W_OPSIZE, /* 2236 */ IC_VEX_L_W_OPSIZE, /* 2237 */ IC_VEX_L_W_OPSIZE, /* 2238 */ IC_VEX_L_W_OPSIZE, /* 2239 */ IC_VEX_L, /* 2240 */ IC_VEX_L, /* 2241 */ IC_VEX_L_XS, /* 2242 */ IC_VEX_L_XS, /* 2243 */ IC_VEX_L_XD, /* 2244 */ IC_VEX_L_XD, /* 2245 */ IC_VEX_L_XD, /* 2246 */ IC_VEX_L_XD, /* 2247 */ IC_VEX_L_W, /* 2248 */ IC_VEX_L_W, /* 2249 */ IC_VEX_L_W_XS, /* 2250 */ IC_VEX_L_W_XS, /* 2251 */ IC_VEX_L_W_XD, /* 2252 */ IC_VEX_L_W_XD, /* 2253 */ IC_VEX_L_W_XD, /* 2254 */ IC_VEX_L_W_XD, /* 2255 */ IC_VEX_L_OPSIZE, /* 2256 */ IC_VEX_L_OPSIZE, /* 2257 */ IC_VEX_L_OPSIZE, /* 2258 */ IC_VEX_L_OPSIZE, /* 2259 */ IC_VEX_L_OPSIZE, /* 2260 */ IC_VEX_L_OPSIZE, /* 2261 */ IC_VEX_L_OPSIZE, /* 2262 */ IC_VEX_L_OPSIZE, /* 2263 */ IC_VEX_L_W_OPSIZE, /* 2264 */ IC_VEX_L_W_OPSIZE, /* 2265 */ IC_VEX_L_W_OPSIZE, /* 2266 */ IC_VEX_L_W_OPSIZE, /* 2267 */ IC_VEX_L_W_OPSIZE, /* 2268 */ IC_VEX_L_W_OPSIZE, /* 2269 */ IC_VEX_L_W_OPSIZE, /* 2270 */ IC_VEX_L_W_OPSIZE, /* 2271 */ IC_VEX_L, /* 2272 */ IC_VEX_L, /* 2273 */ IC_VEX_L_XS, /* 2274 */ IC_VEX_L_XS, /* 2275 */ IC_VEX_L_XD, /* 2276 */ IC_VEX_L_XD, /* 2277 */ IC_VEX_L_XD, /* 2278 */ IC_VEX_L_XD, /* 2279 */ IC_VEX_L_W, /* 2280 */ IC_VEX_L_W, /* 2281 */ IC_VEX_L_W_XS, /* 2282 */ IC_VEX_L_W_XS, /* 2283 */ IC_VEX_L_W_XD, /* 2284 */ IC_VEX_L_W_XD, /* 2285 */ IC_VEX_L_W_XD, /* 2286 */ IC_VEX_L_W_XD, /* 2287 */ IC_VEX_L_OPSIZE, /* 2288 */ IC_VEX_L_OPSIZE, /* 2289 */ IC_VEX_L_OPSIZE, /* 2290 */ IC_VEX_L_OPSIZE, /* 2291 */ IC_VEX_L_OPSIZE, /* 2292 */ IC_VEX_L_OPSIZE, /* 2293 */ IC_VEX_L_OPSIZE, /* 2294 */ IC_VEX_L_OPSIZE, /* 2295 */ IC_VEX_L_W_OPSIZE, /* 2296 */ IC_VEX_L_W_OPSIZE, /* 2297 */ IC_VEX_L_W_OPSIZE, /* 2298 */ IC_VEX_L_W_OPSIZE, /* 2299 */ IC_VEX_L_W_OPSIZE, /* 2300 */ IC_VEX_L_W_OPSIZE, /* 2301 */ IC_VEX_L_W_OPSIZE, /* 2302 */ IC_VEX_L_W_OPSIZE, /* 2303 */ IC_EVEX_K, /* 2304 */ IC_EVEX_K, /* 2305 */ IC_EVEX_XS_K, /* 2306 */ IC_EVEX_XS_K, /* 2307 */ IC_EVEX_XD_K, /* 2308 */ IC_EVEX_XD_K, /* 2309 */ IC_EVEX_XD_K, /* 2310 */ IC_EVEX_XD_K, /* 2311 */ IC_EVEX_W_K, /* 2312 */ IC_EVEX_W_K, /* 2313 */ IC_EVEX_W_XS_K, /* 2314 */ IC_EVEX_W_XS_K, /* 2315 */ IC_EVEX_W_XD_K, /* 2316 */ IC_EVEX_W_XD_K, /* 2317 */ IC_EVEX_W_XD_K, /* 2318 */ IC_EVEX_W_XD_K, /* 2319 */ IC_EVEX_OPSIZE_K, /* 2320 */ IC_EVEX_OPSIZE_K, /* 2321 */ IC_EVEX_OPSIZE_K, /* 2322 */ IC_EVEX_OPSIZE_K, /* 2323 */ IC_EVEX_OPSIZE_K, /* 2324 */ IC_EVEX_OPSIZE_K, /* 2325 */ IC_EVEX_OPSIZE_K, /* 2326 */ IC_EVEX_OPSIZE_K, /* 2327 */ IC_EVEX_W_OPSIZE_K, /* 2328 */ IC_EVEX_W_OPSIZE_K, /* 2329 */ IC_EVEX_W_OPSIZE_K, /* 2330 */ IC_EVEX_W_OPSIZE_K, /* 2331 */ IC_EVEX_W_OPSIZE_K, /* 2332 */ IC_EVEX_W_OPSIZE_K, /* 2333 */ IC_EVEX_W_OPSIZE_K, /* 2334 */ IC_EVEX_W_OPSIZE_K, /* 2335 */ IC_EVEX_K, /* 2336 */ IC_EVEX_K, /* 2337 */ IC_EVEX_XS_K, /* 2338 */ IC_EVEX_XS_K, /* 2339 */ IC_EVEX_XD_K, /* 2340 */ IC_EVEX_XD_K, /* 2341 */ IC_EVEX_XD_K, /* 2342 */ IC_EVEX_XD_K, /* 2343 */ IC_EVEX_W_K, /* 2344 */ IC_EVEX_W_K, /* 2345 */ IC_EVEX_W_XS_K, /* 2346 */ IC_EVEX_W_XS_K, /* 2347 */ IC_EVEX_W_XD_K, /* 2348 */ IC_EVEX_W_XD_K, /* 2349 */ IC_EVEX_W_XD_K, /* 2350 */ IC_EVEX_W_XD_K, /* 2351 */ IC_EVEX_OPSIZE_K, /* 2352 */ IC_EVEX_OPSIZE_K, /* 2353 */ IC_EVEX_OPSIZE_K, /* 2354 */ IC_EVEX_OPSIZE_K, /* 2355 */ IC_EVEX_OPSIZE_K, /* 2356 */ IC_EVEX_OPSIZE_K, /* 2357 */ IC_EVEX_OPSIZE_K, /* 2358 */ IC_EVEX_OPSIZE_K, /* 2359 */ IC_EVEX_W_OPSIZE_K, /* 2360 */ IC_EVEX_W_OPSIZE_K, /* 2361 */ IC_EVEX_W_OPSIZE_K, /* 2362 */ IC_EVEX_W_OPSIZE_K, /* 2363 */ IC_EVEX_W_OPSIZE_K, /* 2364 */ IC_EVEX_W_OPSIZE_K, /* 2365 */ IC_EVEX_W_OPSIZE_K, /* 2366 */ IC_EVEX_W_OPSIZE_K, /* 2367 */ IC_EVEX_K, /* 2368 */ IC_EVEX_K, /* 2369 */ IC_EVEX_XS_K, /* 2370 */ IC_EVEX_XS_K, /* 2371 */ IC_EVEX_XD_K, /* 2372 */ IC_EVEX_XD_K, /* 2373 */ IC_EVEX_XD_K, /* 2374 */ IC_EVEX_XD_K, /* 2375 */ IC_EVEX_W_K, /* 2376 */ IC_EVEX_W_K, /* 2377 */ IC_EVEX_W_XS_K, /* 2378 */ IC_EVEX_W_XS_K, /* 2379 */ IC_EVEX_W_XD_K, /* 2380 */ IC_EVEX_W_XD_K, /* 2381 */ IC_EVEX_W_XD_K, /* 2382 */ IC_EVEX_W_XD_K, /* 2383 */ IC_EVEX_OPSIZE_K, /* 2384 */ IC_EVEX_OPSIZE_K, /* 2385 */ IC_EVEX_OPSIZE_K, /* 2386 */ IC_EVEX_OPSIZE_K, /* 2387 */ IC_EVEX_OPSIZE_K, /* 2388 */ IC_EVEX_OPSIZE_K, /* 2389 */ IC_EVEX_OPSIZE_K, /* 2390 */ IC_EVEX_OPSIZE_K, /* 2391 */ IC_EVEX_W_OPSIZE_K, /* 2392 */ IC_EVEX_W_OPSIZE_K, /* 2393 */ IC_EVEX_W_OPSIZE_K, /* 2394 */ IC_EVEX_W_OPSIZE_K, /* 2395 */ IC_EVEX_W_OPSIZE_K, /* 2396 */ IC_EVEX_W_OPSIZE_K, /* 2397 */ IC_EVEX_W_OPSIZE_K, /* 2398 */ IC_EVEX_W_OPSIZE_K, /* 2399 */ IC_EVEX_K, /* 2400 */ IC_EVEX_K, /* 2401 */ IC_EVEX_XS_K, /* 2402 */ IC_EVEX_XS_K, /* 2403 */ IC_EVEX_XD_K, /* 2404 */ IC_EVEX_XD_K, /* 2405 */ IC_EVEX_XD_K, /* 2406 */ IC_EVEX_XD_K, /* 2407 */ IC_EVEX_W_K, /* 2408 */ IC_EVEX_W_K, /* 2409 */ IC_EVEX_W_XS_K, /* 2410 */ IC_EVEX_W_XS_K, /* 2411 */ IC_EVEX_W_XD_K, /* 2412 */ IC_EVEX_W_XD_K, /* 2413 */ IC_EVEX_W_XD_K, /* 2414 */ IC_EVEX_W_XD_K, /* 2415 */ IC_EVEX_OPSIZE_K, /* 2416 */ IC_EVEX_OPSIZE_K, /* 2417 */ IC_EVEX_OPSIZE_K, /* 2418 */ IC_EVEX_OPSIZE_K, /* 2419 */ IC_EVEX_OPSIZE_K, /* 2420 */ IC_EVEX_OPSIZE_K, /* 2421 */ IC_EVEX_OPSIZE_K, /* 2422 */ IC_EVEX_OPSIZE_K, /* 2423 */ IC_EVEX_W_OPSIZE_K, /* 2424 */ IC_EVEX_W_OPSIZE_K, /* 2425 */ IC_EVEX_W_OPSIZE_K, /* 2426 */ IC_EVEX_W_OPSIZE_K, /* 2427 */ IC_EVEX_W_OPSIZE_K, /* 2428 */ IC_EVEX_W_OPSIZE_K, /* 2429 */ IC_EVEX_W_OPSIZE_K, /* 2430 */ IC_EVEX_W_OPSIZE_K, /* 2431 */ IC_EVEX_K, /* 2432 */ IC_EVEX_K, /* 2433 */ IC_EVEX_XS_K, /* 2434 */ IC_EVEX_XS_K, /* 2435 */ IC_EVEX_XD_K, /* 2436 */ IC_EVEX_XD_K, /* 2437 */ IC_EVEX_XD_K, /* 2438 */ IC_EVEX_XD_K, /* 2439 */ IC_EVEX_W_K, /* 2440 */ IC_EVEX_W_K, /* 2441 */ IC_EVEX_W_XS_K, /* 2442 */ IC_EVEX_W_XS_K, /* 2443 */ IC_EVEX_W_XD_K, /* 2444 */ IC_EVEX_W_XD_K, /* 2445 */ IC_EVEX_W_XD_K, /* 2446 */ IC_EVEX_W_XD_K, /* 2447 */ IC_EVEX_OPSIZE_K, /* 2448 */ IC_EVEX_OPSIZE_K, /* 2449 */ IC_EVEX_OPSIZE_K, /* 2450 */ IC_EVEX_OPSIZE_K, /* 2451 */ IC_EVEX_OPSIZE_K, /* 2452 */ IC_EVEX_OPSIZE_K, /* 2453 */ IC_EVEX_OPSIZE_K, /* 2454 */ IC_EVEX_OPSIZE_K, /* 2455 */ IC_EVEX_W_OPSIZE_K, /* 2456 */ IC_EVEX_W_OPSIZE_K, /* 2457 */ IC_EVEX_W_OPSIZE_K, /* 2458 */ IC_EVEX_W_OPSIZE_K, /* 2459 */ IC_EVEX_W_OPSIZE_K, /* 2460 */ IC_EVEX_W_OPSIZE_K, /* 2461 */ IC_EVEX_W_OPSIZE_K, /* 2462 */ IC_EVEX_W_OPSIZE_K, /* 2463 */ IC_EVEX_K, /* 2464 */ IC_EVEX_K, /* 2465 */ IC_EVEX_XS_K, /* 2466 */ IC_EVEX_XS_K, /* 2467 */ IC_EVEX_XD_K, /* 2468 */ IC_EVEX_XD_K, /* 2469 */ IC_EVEX_XD_K, /* 2470 */ IC_EVEX_XD_K, /* 2471 */ IC_EVEX_W_K, /* 2472 */ IC_EVEX_W_K, /* 2473 */ IC_EVEX_W_XS_K, /* 2474 */ IC_EVEX_W_XS_K, /* 2475 */ IC_EVEX_W_XD_K, /* 2476 */ IC_EVEX_W_XD_K, /* 2477 */ IC_EVEX_W_XD_K, /* 2478 */ IC_EVEX_W_XD_K, /* 2479 */ IC_EVEX_OPSIZE_K, /* 2480 */ IC_EVEX_OPSIZE_K, /* 2481 */ IC_EVEX_OPSIZE_K, /* 2482 */ IC_EVEX_OPSIZE_K, /* 2483 */ IC_EVEX_OPSIZE_K, /* 2484 */ IC_EVEX_OPSIZE_K, /* 2485 */ IC_EVEX_OPSIZE_K, /* 2486 */ IC_EVEX_OPSIZE_K, /* 2487 */ IC_EVEX_W_OPSIZE_K, /* 2488 */ IC_EVEX_W_OPSIZE_K, /* 2489 */ IC_EVEX_W_OPSIZE_K, /* 2490 */ IC_EVEX_W_OPSIZE_K, /* 2491 */ IC_EVEX_W_OPSIZE_K, /* 2492 */ IC_EVEX_W_OPSIZE_K, /* 2493 */ IC_EVEX_W_OPSIZE_K, /* 2494 */ IC_EVEX_W_OPSIZE_K, /* 2495 */ IC_EVEX_K, /* 2496 */ IC_EVEX_K, /* 2497 */ IC_EVEX_XS_K, /* 2498 */ IC_EVEX_XS_K, /* 2499 */ IC_EVEX_XD_K, /* 2500 */ IC_EVEX_XD_K, /* 2501 */ IC_EVEX_XD_K, /* 2502 */ IC_EVEX_XD_K, /* 2503 */ IC_EVEX_W_K, /* 2504 */ IC_EVEX_W_K, /* 2505 */ IC_EVEX_W_XS_K, /* 2506 */ IC_EVEX_W_XS_K, /* 2507 */ IC_EVEX_W_XD_K, /* 2508 */ IC_EVEX_W_XD_K, /* 2509 */ IC_EVEX_W_XD_K, /* 2510 */ IC_EVEX_W_XD_K, /* 2511 */ IC_EVEX_OPSIZE_K, /* 2512 */ IC_EVEX_OPSIZE_K, /* 2513 */ IC_EVEX_OPSIZE_K, /* 2514 */ IC_EVEX_OPSIZE_K, /* 2515 */ IC_EVEX_OPSIZE_K, /* 2516 */ IC_EVEX_OPSIZE_K, /* 2517 */ IC_EVEX_OPSIZE_K, /* 2518 */ IC_EVEX_OPSIZE_K, /* 2519 */ IC_EVEX_W_OPSIZE_K, /* 2520 */ IC_EVEX_W_OPSIZE_K, /* 2521 */ IC_EVEX_W_OPSIZE_K, /* 2522 */ IC_EVEX_W_OPSIZE_K, /* 2523 */ IC_EVEX_W_OPSIZE_K, /* 2524 */ IC_EVEX_W_OPSIZE_K, /* 2525 */ IC_EVEX_W_OPSIZE_K, /* 2526 */ IC_EVEX_W_OPSIZE_K, /* 2527 */ IC_EVEX_K, /* 2528 */ IC_EVEX_K, /* 2529 */ IC_EVEX_XS_K, /* 2530 */ IC_EVEX_XS_K, /* 2531 */ IC_EVEX_XD_K, /* 2532 */ IC_EVEX_XD_K, /* 2533 */ IC_EVEX_XD_K, /* 2534 */ IC_EVEX_XD_K, /* 2535 */ IC_EVEX_W_K, /* 2536 */ IC_EVEX_W_K, /* 2537 */ IC_EVEX_W_XS_K, /* 2538 */ IC_EVEX_W_XS_K, /* 2539 */ IC_EVEX_W_XD_K, /* 2540 */ IC_EVEX_W_XD_K, /* 2541 */ IC_EVEX_W_XD_K, /* 2542 */ IC_EVEX_W_XD_K, /* 2543 */ IC_EVEX_OPSIZE_K, /* 2544 */ IC_EVEX_OPSIZE_K, /* 2545 */ IC_EVEX_OPSIZE_K, /* 2546 */ IC_EVEX_OPSIZE_K, /* 2547 */ IC_EVEX_OPSIZE_K, /* 2548 */ IC_EVEX_OPSIZE_K, /* 2549 */ IC_EVEX_OPSIZE_K, /* 2550 */ IC_EVEX_OPSIZE_K, /* 2551 */ IC_EVEX_W_OPSIZE_K, /* 2552 */ IC_EVEX_W_OPSIZE_K, /* 2553 */ IC_EVEX_W_OPSIZE_K, /* 2554 */ IC_EVEX_W_OPSIZE_K, /* 2555 */ IC_EVEX_W_OPSIZE_K, /* 2556 */ IC_EVEX_W_OPSIZE_K, /* 2557 */ IC_EVEX_W_OPSIZE_K, /* 2558 */ IC_EVEX_W_OPSIZE_K, /* 2559 */ IC, /* 2560 */ IC_64BIT, /* 2561 */ IC_XS, /* 2562 */ IC_64BIT_XS, /* 2563 */ IC_XD, /* 2564 */ IC_64BIT_XD, /* 2565 */ IC_XS, /* 2566 */ IC_64BIT_XS, /* 2567 */ IC, /* 2568 */ IC_64BIT_REXW, /* 2569 */ IC_XS, /* 2570 */ IC_64BIT_REXW_XS, /* 2571 */ IC_XD, /* 2572 */ IC_64BIT_REXW_XD, /* 2573 */ IC_XS, /* 2574 */ IC_64BIT_REXW_XS, /* 2575 */ IC_OPSIZE, /* 2576 */ IC_64BIT_OPSIZE, /* 2577 */ IC_XS_OPSIZE, /* 2578 */ IC_64BIT_XS_OPSIZE, /* 2579 */ IC_XD_OPSIZE, /* 2580 */ IC_64BIT_XD_OPSIZE, /* 2581 */ IC_XS_OPSIZE, /* 2582 */ IC_64BIT_XD_OPSIZE, /* 2583 */ IC_OPSIZE, /* 2584 */ IC_64BIT_REXW_OPSIZE, /* 2585 */ IC_XS_OPSIZE, /* 2586 */ IC_64BIT_REXW_XS, /* 2587 */ IC_XD_OPSIZE, /* 2588 */ IC_64BIT_REXW_XD, /* 2589 */ IC_XS_OPSIZE, /* 2590 */ IC_64BIT_REXW_XS, /* 2591 */ IC_ADSIZE, /* 2592 */ IC_64BIT_ADSIZE, /* 2593 */ IC_XS_ADSIZE, /* 2594 */ IC_64BIT_XS_ADSIZE, /* 2595 */ IC_XD_ADSIZE, /* 2596 */ IC_64BIT_XD_ADSIZE, /* 2597 */ IC_XS_ADSIZE, /* 2598 */ IC_64BIT_XD_ADSIZE, /* 2599 */ IC_ADSIZE, /* 2600 */ IC_64BIT_REXW_ADSIZE, /* 2601 */ IC_XS_ADSIZE, /* 2602 */ IC_64BIT_REXW_XS, /* 2603 */ IC_XD_ADSIZE, /* 2604 */ IC_64BIT_REXW_XD, /* 2605 */ IC_XS_ADSIZE, /* 2606 */ IC_64BIT_REXW_XS, /* 2607 */ IC_OPSIZE_ADSIZE, /* 2608 */ IC_64BIT_OPSIZE_ADSIZE, /* 2609 */ IC_XS_OPSIZE, /* 2610 */ IC_64BIT_XS_OPSIZE, /* 2611 */ IC_XD_OPSIZE, /* 2612 */ IC_64BIT_XD_OPSIZE, /* 2613 */ IC_XS_OPSIZE, /* 2614 */ IC_64BIT_XD_OPSIZE, /* 2615 */ IC_OPSIZE_ADSIZE, /* 2616 */ IC_64BIT_REXW_OPSIZE, /* 2617 */ IC_XS_OPSIZE, /* 2618 */ IC_64BIT_REXW_XS, /* 2619 */ IC_XD_OPSIZE, /* 2620 */ IC_64BIT_REXW_XD, /* 2621 */ IC_XS_OPSIZE, /* 2622 */ IC_64BIT_REXW_XS, /* 2623 */ IC_VEX, /* 2624 */ IC_VEX, /* 2625 */ IC_VEX_XS, /* 2626 */ IC_VEX_XS, /* 2627 */ IC_VEX_XD, /* 2628 */ IC_VEX_XD, /* 2629 */ IC_VEX_XD, /* 2630 */ IC_VEX_XD, /* 2631 */ IC_VEX_W, /* 2632 */ IC_VEX_W, /* 2633 */ IC_VEX_W_XS, /* 2634 */ IC_VEX_W_XS, /* 2635 */ IC_VEX_W_XD, /* 2636 */ IC_VEX_W_XD, /* 2637 */ IC_VEX_W_XD, /* 2638 */ IC_VEX_W_XD, /* 2639 */ IC_VEX_OPSIZE, /* 2640 */ IC_VEX_OPSIZE, /* 2641 */ IC_VEX_OPSIZE, /* 2642 */ IC_VEX_OPSIZE, /* 2643 */ IC_VEX_OPSIZE, /* 2644 */ IC_VEX_OPSIZE, /* 2645 */ IC_VEX_OPSIZE, /* 2646 */ IC_VEX_OPSIZE, /* 2647 */ IC_VEX_W_OPSIZE, /* 2648 */ IC_VEX_W_OPSIZE, /* 2649 */ IC_VEX_W_OPSIZE, /* 2650 */ IC_VEX_W_OPSIZE, /* 2651 */ IC_VEX_W_OPSIZE, /* 2652 */ IC_VEX_W_OPSIZE, /* 2653 */ IC_VEX_W_OPSIZE, /* 2654 */ IC_VEX_W_OPSIZE, /* 2655 */ IC_VEX, /* 2656 */ IC_VEX, /* 2657 */ IC_VEX_XS, /* 2658 */ IC_VEX_XS, /* 2659 */ IC_VEX_XD, /* 2660 */ IC_VEX_XD, /* 2661 */ IC_VEX_XD, /* 2662 */ IC_VEX_XD, /* 2663 */ IC_VEX_W, /* 2664 */ IC_VEX_W, /* 2665 */ IC_VEX_W_XS, /* 2666 */ IC_VEX_W_XS, /* 2667 */ IC_VEX_W_XD, /* 2668 */ IC_VEX_W_XD, /* 2669 */ IC_VEX_W_XD, /* 2670 */ IC_VEX_W_XD, /* 2671 */ IC_VEX_OPSIZE, /* 2672 */ IC_VEX_OPSIZE, /* 2673 */ IC_VEX_OPSIZE, /* 2674 */ IC_VEX_OPSIZE, /* 2675 */ IC_VEX_OPSIZE, /* 2676 */ IC_VEX_OPSIZE, /* 2677 */ IC_VEX_OPSIZE, /* 2678 */ IC_VEX_OPSIZE, /* 2679 */ IC_VEX_W_OPSIZE, /* 2680 */ IC_VEX_W_OPSIZE, /* 2681 */ IC_VEX_W_OPSIZE, /* 2682 */ IC_VEX_W_OPSIZE, /* 2683 */ IC_VEX_W_OPSIZE, /* 2684 */ IC_VEX_W_OPSIZE, /* 2685 */ IC_VEX_W_OPSIZE, /* 2686 */ IC_VEX_W_OPSIZE, /* 2687 */ IC_VEX_L, /* 2688 */ IC_VEX_L, /* 2689 */ IC_VEX_L_XS, /* 2690 */ IC_VEX_L_XS, /* 2691 */ IC_VEX_L_XD, /* 2692 */ IC_VEX_L_XD, /* 2693 */ IC_VEX_L_XD, /* 2694 */ IC_VEX_L_XD, /* 2695 */ IC_VEX_L_W, /* 2696 */ IC_VEX_L_W, /* 2697 */ IC_VEX_L_W_XS, /* 2698 */ IC_VEX_L_W_XS, /* 2699 */ IC_VEX_L_W_XD, /* 2700 */ IC_VEX_L_W_XD, /* 2701 */ IC_VEX_L_W_XD, /* 2702 */ IC_VEX_L_W_XD, /* 2703 */ IC_VEX_L_OPSIZE, /* 2704 */ IC_VEX_L_OPSIZE, /* 2705 */ IC_VEX_L_OPSIZE, /* 2706 */ IC_VEX_L_OPSIZE, /* 2707 */ IC_VEX_L_OPSIZE, /* 2708 */ IC_VEX_L_OPSIZE, /* 2709 */ IC_VEX_L_OPSIZE, /* 2710 */ IC_VEX_L_OPSIZE, /* 2711 */ IC_VEX_L_W_OPSIZE, /* 2712 */ IC_VEX_L_W_OPSIZE, /* 2713 */ IC_VEX_L_W_OPSIZE, /* 2714 */ IC_VEX_L_W_OPSIZE, /* 2715 */ IC_VEX_L_W_OPSIZE, /* 2716 */ IC_VEX_L_W_OPSIZE, /* 2717 */ IC_VEX_L_W_OPSIZE, /* 2718 */ IC_VEX_L_W_OPSIZE, /* 2719 */ IC_VEX_L, /* 2720 */ IC_VEX_L, /* 2721 */ IC_VEX_L_XS, /* 2722 */ IC_VEX_L_XS, /* 2723 */ IC_VEX_L_XD, /* 2724 */ IC_VEX_L_XD, /* 2725 */ IC_VEX_L_XD, /* 2726 */ IC_VEX_L_XD, /* 2727 */ IC_VEX_L_W, /* 2728 */ IC_VEX_L_W, /* 2729 */ IC_VEX_L_W_XS, /* 2730 */ IC_VEX_L_W_XS, /* 2731 */ IC_VEX_L_W_XD, /* 2732 */ IC_VEX_L_W_XD, /* 2733 */ IC_VEX_L_W_XD, /* 2734 */ IC_VEX_L_W_XD, /* 2735 */ IC_VEX_L_OPSIZE, /* 2736 */ IC_VEX_L_OPSIZE, /* 2737 */ IC_VEX_L_OPSIZE, /* 2738 */ IC_VEX_L_OPSIZE, /* 2739 */ IC_VEX_L_OPSIZE, /* 2740 */ IC_VEX_L_OPSIZE, /* 2741 */ IC_VEX_L_OPSIZE, /* 2742 */ IC_VEX_L_OPSIZE, /* 2743 */ IC_VEX_L_W_OPSIZE, /* 2744 */ IC_VEX_L_W_OPSIZE, /* 2745 */ IC_VEX_L_W_OPSIZE, /* 2746 */ IC_VEX_L_W_OPSIZE, /* 2747 */ IC_VEX_L_W_OPSIZE, /* 2748 */ IC_VEX_L_W_OPSIZE, /* 2749 */ IC_VEX_L_W_OPSIZE, /* 2750 */ IC_VEX_L_W_OPSIZE, /* 2751 */ IC_VEX_L, /* 2752 */ IC_VEX_L, /* 2753 */ IC_VEX_L_XS, /* 2754 */ IC_VEX_L_XS, /* 2755 */ IC_VEX_L_XD, /* 2756 */ IC_VEX_L_XD, /* 2757 */ IC_VEX_L_XD, /* 2758 */ IC_VEX_L_XD, /* 2759 */ IC_VEX_L_W, /* 2760 */ IC_VEX_L_W, /* 2761 */ IC_VEX_L_W_XS, /* 2762 */ IC_VEX_L_W_XS, /* 2763 */ IC_VEX_L_W_XD, /* 2764 */ IC_VEX_L_W_XD, /* 2765 */ IC_VEX_L_W_XD, /* 2766 */ IC_VEX_L_W_XD, /* 2767 */ IC_VEX_L_OPSIZE, /* 2768 */ IC_VEX_L_OPSIZE, /* 2769 */ IC_VEX_L_OPSIZE, /* 2770 */ IC_VEX_L_OPSIZE, /* 2771 */ IC_VEX_L_OPSIZE, /* 2772 */ IC_VEX_L_OPSIZE, /* 2773 */ IC_VEX_L_OPSIZE, /* 2774 */ IC_VEX_L_OPSIZE, /* 2775 */ IC_VEX_L_W_OPSIZE, /* 2776 */ IC_VEX_L_W_OPSIZE, /* 2777 */ IC_VEX_L_W_OPSIZE, /* 2778 */ IC_VEX_L_W_OPSIZE, /* 2779 */ IC_VEX_L_W_OPSIZE, /* 2780 */ IC_VEX_L_W_OPSIZE, /* 2781 */ IC_VEX_L_W_OPSIZE, /* 2782 */ IC_VEX_L_W_OPSIZE, /* 2783 */ IC_VEX_L, /* 2784 */ IC_VEX_L, /* 2785 */ IC_VEX_L_XS, /* 2786 */ IC_VEX_L_XS, /* 2787 */ IC_VEX_L_XD, /* 2788 */ IC_VEX_L_XD, /* 2789 */ IC_VEX_L_XD, /* 2790 */ IC_VEX_L_XD, /* 2791 */ IC_VEX_L_W, /* 2792 */ IC_VEX_L_W, /* 2793 */ IC_VEX_L_W_XS, /* 2794 */ IC_VEX_L_W_XS, /* 2795 */ IC_VEX_L_W_XD, /* 2796 */ IC_VEX_L_W_XD, /* 2797 */ IC_VEX_L_W_XD, /* 2798 */ IC_VEX_L_W_XD, /* 2799 */ IC_VEX_L_OPSIZE, /* 2800 */ IC_VEX_L_OPSIZE, /* 2801 */ IC_VEX_L_OPSIZE, /* 2802 */ IC_VEX_L_OPSIZE, /* 2803 */ IC_VEX_L_OPSIZE, /* 2804 */ IC_VEX_L_OPSIZE, /* 2805 */ IC_VEX_L_OPSIZE, /* 2806 */ IC_VEX_L_OPSIZE, /* 2807 */ IC_VEX_L_W_OPSIZE, /* 2808 */ IC_VEX_L_W_OPSIZE, /* 2809 */ IC_VEX_L_W_OPSIZE, /* 2810 */ IC_VEX_L_W_OPSIZE, /* 2811 */ IC_VEX_L_W_OPSIZE, /* 2812 */ IC_VEX_L_W_OPSIZE, /* 2813 */ IC_VEX_L_W_OPSIZE, /* 2814 */ IC_VEX_L_W_OPSIZE, /* 2815 */ IC_EVEX_L_K, /* 2816 */ IC_EVEX_L_K, /* 2817 */ IC_EVEX_L_XS_K, /* 2818 */ IC_EVEX_L_XS_K, /* 2819 */ IC_EVEX_L_XD_K, /* 2820 */ IC_EVEX_L_XD_K, /* 2821 */ IC_EVEX_L_XD_K, /* 2822 */ IC_EVEX_L_XD_K, /* 2823 */ IC_EVEX_L_W_K, /* 2824 */ IC_EVEX_L_W_K, /* 2825 */ IC_EVEX_L_W_XS_K, /* 2826 */ IC_EVEX_L_W_XS_K, /* 2827 */ IC_EVEX_L_W_XD_K, /* 2828 */ IC_EVEX_L_W_XD_K, /* 2829 */ IC_EVEX_L_W_XD_K, /* 2830 */ IC_EVEX_L_W_XD_K, /* 2831 */ IC_EVEX_L_OPSIZE_K, /* 2832 */ IC_EVEX_L_OPSIZE_K, /* 2833 */ IC_EVEX_L_OPSIZE_K, /* 2834 */ IC_EVEX_L_OPSIZE_K, /* 2835 */ IC_EVEX_L_OPSIZE_K, /* 2836 */ IC_EVEX_L_OPSIZE_K, /* 2837 */ IC_EVEX_L_OPSIZE_K, /* 2838 */ IC_EVEX_L_OPSIZE_K, /* 2839 */ IC_EVEX_L_W_OPSIZE_K, /* 2840 */ IC_EVEX_L_W_OPSIZE_K, /* 2841 */ IC_EVEX_L_W_OPSIZE_K, /* 2842 */ IC_EVEX_L_W_OPSIZE_K, /* 2843 */ IC_EVEX_L_W_OPSIZE_K, /* 2844 */ IC_EVEX_L_W_OPSIZE_K, /* 2845 */ IC_EVEX_L_W_OPSIZE_K, /* 2846 */ IC_EVEX_L_W_OPSIZE_K, /* 2847 */ IC_EVEX_L_K, /* 2848 */ IC_EVEX_L_K, /* 2849 */ IC_EVEX_L_XS_K, /* 2850 */ IC_EVEX_L_XS_K, /* 2851 */ IC_EVEX_L_XD_K, /* 2852 */ IC_EVEX_L_XD_K, /* 2853 */ IC_EVEX_L_XD_K, /* 2854 */ IC_EVEX_L_XD_K, /* 2855 */ IC_EVEX_L_W_K, /* 2856 */ IC_EVEX_L_W_K, /* 2857 */ IC_EVEX_L_W_XS_K, /* 2858 */ IC_EVEX_L_W_XS_K, /* 2859 */ IC_EVEX_L_W_XD_K, /* 2860 */ IC_EVEX_L_W_XD_K, /* 2861 */ IC_EVEX_L_W_XD_K, /* 2862 */ IC_EVEX_L_W_XD_K, /* 2863 */ IC_EVEX_L_OPSIZE_K, /* 2864 */ IC_EVEX_L_OPSIZE_K, /* 2865 */ IC_EVEX_L_OPSIZE_K, /* 2866 */ IC_EVEX_L_OPSIZE_K, /* 2867 */ IC_EVEX_L_OPSIZE_K, /* 2868 */ IC_EVEX_L_OPSIZE_K, /* 2869 */ IC_EVEX_L_OPSIZE_K, /* 2870 */ IC_EVEX_L_OPSIZE_K, /* 2871 */ IC_EVEX_L_W_OPSIZE_K, /* 2872 */ IC_EVEX_L_W_OPSIZE_K, /* 2873 */ IC_EVEX_L_W_OPSIZE_K, /* 2874 */ IC_EVEX_L_W_OPSIZE_K, /* 2875 */ IC_EVEX_L_W_OPSIZE_K, /* 2876 */ IC_EVEX_L_W_OPSIZE_K, /* 2877 */ IC_EVEX_L_W_OPSIZE_K, /* 2878 */ IC_EVEX_L_W_OPSIZE_K, /* 2879 */ IC_EVEX_L_K, /* 2880 */ IC_EVEX_L_K, /* 2881 */ IC_EVEX_L_XS_K, /* 2882 */ IC_EVEX_L_XS_K, /* 2883 */ IC_EVEX_L_XD_K, /* 2884 */ IC_EVEX_L_XD_K, /* 2885 */ IC_EVEX_L_XD_K, /* 2886 */ IC_EVEX_L_XD_K, /* 2887 */ IC_EVEX_L_W_K, /* 2888 */ IC_EVEX_L_W_K, /* 2889 */ IC_EVEX_L_W_XS_K, /* 2890 */ IC_EVEX_L_W_XS_K, /* 2891 */ IC_EVEX_L_W_XD_K, /* 2892 */ IC_EVEX_L_W_XD_K, /* 2893 */ IC_EVEX_L_W_XD_K, /* 2894 */ IC_EVEX_L_W_XD_K, /* 2895 */ IC_EVEX_L_OPSIZE_K, /* 2896 */ IC_EVEX_L_OPSIZE_K, /* 2897 */ IC_EVEX_L_OPSIZE_K, /* 2898 */ IC_EVEX_L_OPSIZE_K, /* 2899 */ IC_EVEX_L_OPSIZE_K, /* 2900 */ IC_EVEX_L_OPSIZE_K, /* 2901 */ IC_EVEX_L_OPSIZE_K, /* 2902 */ IC_EVEX_L_OPSIZE_K, /* 2903 */ IC_EVEX_L_W_OPSIZE_K, /* 2904 */ IC_EVEX_L_W_OPSIZE_K, /* 2905 */ IC_EVEX_L_W_OPSIZE_K, /* 2906 */ IC_EVEX_L_W_OPSIZE_K, /* 2907 */ IC_EVEX_L_W_OPSIZE_K, /* 2908 */ IC_EVEX_L_W_OPSIZE_K, /* 2909 */ IC_EVEX_L_W_OPSIZE_K, /* 2910 */ IC_EVEX_L_W_OPSIZE_K, /* 2911 */ IC_EVEX_L_K, /* 2912 */ IC_EVEX_L_K, /* 2913 */ IC_EVEX_L_XS_K, /* 2914 */ IC_EVEX_L_XS_K, /* 2915 */ IC_EVEX_L_XD_K, /* 2916 */ IC_EVEX_L_XD_K, /* 2917 */ IC_EVEX_L_XD_K, /* 2918 */ IC_EVEX_L_XD_K, /* 2919 */ IC_EVEX_L_W_K, /* 2920 */ IC_EVEX_L_W_K, /* 2921 */ IC_EVEX_L_W_XS_K, /* 2922 */ IC_EVEX_L_W_XS_K, /* 2923 */ IC_EVEX_L_W_XD_K, /* 2924 */ IC_EVEX_L_W_XD_K, /* 2925 */ IC_EVEX_L_W_XD_K, /* 2926 */ IC_EVEX_L_W_XD_K, /* 2927 */ IC_EVEX_L_OPSIZE_K, /* 2928 */ IC_EVEX_L_OPSIZE_K, /* 2929 */ IC_EVEX_L_OPSIZE_K, /* 2930 */ IC_EVEX_L_OPSIZE_K, /* 2931 */ IC_EVEX_L_OPSIZE_K, /* 2932 */ IC_EVEX_L_OPSIZE_K, /* 2933 */ IC_EVEX_L_OPSIZE_K, /* 2934 */ IC_EVEX_L_OPSIZE_K, /* 2935 */ IC_EVEX_L_W_OPSIZE_K, /* 2936 */ IC_EVEX_L_W_OPSIZE_K, /* 2937 */ IC_EVEX_L_W_OPSIZE_K, /* 2938 */ IC_EVEX_L_W_OPSIZE_K, /* 2939 */ IC_EVEX_L_W_OPSIZE_K, /* 2940 */ IC_EVEX_L_W_OPSIZE_K, /* 2941 */ IC_EVEX_L_W_OPSIZE_K, /* 2942 */ IC_EVEX_L_W_OPSIZE_K, /* 2943 */ IC_EVEX_L_K, /* 2944 */ IC_EVEX_L_K, /* 2945 */ IC_EVEX_L_XS_K, /* 2946 */ IC_EVEX_L_XS_K, /* 2947 */ IC_EVEX_L_XD_K, /* 2948 */ IC_EVEX_L_XD_K, /* 2949 */ IC_EVEX_L_XD_K, /* 2950 */ IC_EVEX_L_XD_K, /* 2951 */ IC_EVEX_L_W_K, /* 2952 */ IC_EVEX_L_W_K, /* 2953 */ IC_EVEX_L_W_XS_K, /* 2954 */ IC_EVEX_L_W_XS_K, /* 2955 */ IC_EVEX_L_W_XD_K, /* 2956 */ IC_EVEX_L_W_XD_K, /* 2957 */ IC_EVEX_L_W_XD_K, /* 2958 */ IC_EVEX_L_W_XD_K, /* 2959 */ IC_EVEX_L_OPSIZE_K, /* 2960 */ IC_EVEX_L_OPSIZE_K, /* 2961 */ IC_EVEX_L_OPSIZE_K, /* 2962 */ IC_EVEX_L_OPSIZE_K, /* 2963 */ IC_EVEX_L_OPSIZE_K, /* 2964 */ IC_EVEX_L_OPSIZE_K, /* 2965 */ IC_EVEX_L_OPSIZE_K, /* 2966 */ IC_EVEX_L_OPSIZE_K, /* 2967 */ IC_EVEX_L_W_OPSIZE_K, /* 2968 */ IC_EVEX_L_W_OPSIZE_K, /* 2969 */ IC_EVEX_L_W_OPSIZE_K, /* 2970 */ IC_EVEX_L_W_OPSIZE_K, /* 2971 */ IC_EVEX_L_W_OPSIZE_K, /* 2972 */ IC_EVEX_L_W_OPSIZE_K, /* 2973 */ IC_EVEX_L_W_OPSIZE_K, /* 2974 */ IC_EVEX_L_W_OPSIZE_K, /* 2975 */ IC_EVEX_L_K, /* 2976 */ IC_EVEX_L_K, /* 2977 */ IC_EVEX_L_XS_K, /* 2978 */ IC_EVEX_L_XS_K, /* 2979 */ IC_EVEX_L_XD_K, /* 2980 */ IC_EVEX_L_XD_K, /* 2981 */ IC_EVEX_L_XD_K, /* 2982 */ IC_EVEX_L_XD_K, /* 2983 */ IC_EVEX_L_W_K, /* 2984 */ IC_EVEX_L_W_K, /* 2985 */ IC_EVEX_L_W_XS_K, /* 2986 */ IC_EVEX_L_W_XS_K, /* 2987 */ IC_EVEX_L_W_XD_K, /* 2988 */ IC_EVEX_L_W_XD_K, /* 2989 */ IC_EVEX_L_W_XD_K, /* 2990 */ IC_EVEX_L_W_XD_K, /* 2991 */ IC_EVEX_L_OPSIZE_K, /* 2992 */ IC_EVEX_L_OPSIZE_K, /* 2993 */ IC_EVEX_L_OPSIZE_K, /* 2994 */ IC_EVEX_L_OPSIZE_K, /* 2995 */ IC_EVEX_L_OPSIZE_K, /* 2996 */ IC_EVEX_L_OPSIZE_K, /* 2997 */ IC_EVEX_L_OPSIZE_K, /* 2998 */ IC_EVEX_L_OPSIZE_K, /* 2999 */ IC_EVEX_L_W_OPSIZE_K, /* 3000 */ IC_EVEX_L_W_OPSIZE_K, /* 3001 */ IC_EVEX_L_W_OPSIZE_K, /* 3002 */ IC_EVEX_L_W_OPSIZE_K, /* 3003 */ IC_EVEX_L_W_OPSIZE_K, /* 3004 */ IC_EVEX_L_W_OPSIZE_K, /* 3005 */ IC_EVEX_L_W_OPSIZE_K, /* 3006 */ IC_EVEX_L_W_OPSIZE_K, /* 3007 */ IC_EVEX_L_K, /* 3008 */ IC_EVEX_L_K, /* 3009 */ IC_EVEX_L_XS_K, /* 3010 */ IC_EVEX_L_XS_K, /* 3011 */ IC_EVEX_L_XD_K, /* 3012 */ IC_EVEX_L_XD_K, /* 3013 */ IC_EVEX_L_XD_K, /* 3014 */ IC_EVEX_L_XD_K, /* 3015 */ IC_EVEX_L_W_K, /* 3016 */ IC_EVEX_L_W_K, /* 3017 */ IC_EVEX_L_W_XS_K, /* 3018 */ IC_EVEX_L_W_XS_K, /* 3019 */ IC_EVEX_L_W_XD_K, /* 3020 */ IC_EVEX_L_W_XD_K, /* 3021 */ IC_EVEX_L_W_XD_K, /* 3022 */ IC_EVEX_L_W_XD_K, /* 3023 */ IC_EVEX_L_OPSIZE_K, /* 3024 */ IC_EVEX_L_OPSIZE_K, /* 3025 */ IC_EVEX_L_OPSIZE_K, /* 3026 */ IC_EVEX_L_OPSIZE_K, /* 3027 */ IC_EVEX_L_OPSIZE_K, /* 3028 */ IC_EVEX_L_OPSIZE_K, /* 3029 */ IC_EVEX_L_OPSIZE_K, /* 3030 */ IC_EVEX_L_OPSIZE_K, /* 3031 */ IC_EVEX_L_W_OPSIZE_K, /* 3032 */ IC_EVEX_L_W_OPSIZE_K, /* 3033 */ IC_EVEX_L_W_OPSIZE_K, /* 3034 */ IC_EVEX_L_W_OPSIZE_K, /* 3035 */ IC_EVEX_L_W_OPSIZE_K, /* 3036 */ IC_EVEX_L_W_OPSIZE_K, /* 3037 */ IC_EVEX_L_W_OPSIZE_K, /* 3038 */ IC_EVEX_L_W_OPSIZE_K, /* 3039 */ IC_EVEX_L_K, /* 3040 */ IC_EVEX_L_K, /* 3041 */ IC_EVEX_L_XS_K, /* 3042 */ IC_EVEX_L_XS_K, /* 3043 */ IC_EVEX_L_XD_K, /* 3044 */ IC_EVEX_L_XD_K, /* 3045 */ IC_EVEX_L_XD_K, /* 3046 */ IC_EVEX_L_XD_K, /* 3047 */ IC_EVEX_L_W_K, /* 3048 */ IC_EVEX_L_W_K, /* 3049 */ IC_EVEX_L_W_XS_K, /* 3050 */ IC_EVEX_L_W_XS_K, /* 3051 */ IC_EVEX_L_W_XD_K, /* 3052 */ IC_EVEX_L_W_XD_K, /* 3053 */ IC_EVEX_L_W_XD_K, /* 3054 */ IC_EVEX_L_W_XD_K, /* 3055 */ IC_EVEX_L_OPSIZE_K, /* 3056 */ IC_EVEX_L_OPSIZE_K, /* 3057 */ IC_EVEX_L_OPSIZE_K, /* 3058 */ IC_EVEX_L_OPSIZE_K, /* 3059 */ IC_EVEX_L_OPSIZE_K, /* 3060 */ IC_EVEX_L_OPSIZE_K, /* 3061 */ IC_EVEX_L_OPSIZE_K, /* 3062 */ IC_EVEX_L_OPSIZE_K, /* 3063 */ IC_EVEX_L_W_OPSIZE_K, /* 3064 */ IC_EVEX_L_W_OPSIZE_K, /* 3065 */ IC_EVEX_L_W_OPSIZE_K, /* 3066 */ IC_EVEX_L_W_OPSIZE_K, /* 3067 */ IC_EVEX_L_W_OPSIZE_K, /* 3068 */ IC_EVEX_L_W_OPSIZE_K, /* 3069 */ IC_EVEX_L_W_OPSIZE_K, /* 3070 */ IC_EVEX_L_W_OPSIZE_K, /* 3071 */ IC, /* 3072 */ IC_64BIT, /* 3073 */ IC_XS, /* 3074 */ IC_64BIT_XS, /* 3075 */ IC_XD, /* 3076 */ IC_64BIT_XD, /* 3077 */ IC_XS, /* 3078 */ IC_64BIT_XS, /* 3079 */ IC, /* 3080 */ IC_64BIT_REXW, /* 3081 */ IC_XS, /* 3082 */ IC_64BIT_REXW_XS, /* 3083 */ IC_XD, /* 3084 */ IC_64BIT_REXW_XD, /* 3085 */ IC_XS, /* 3086 */ IC_64BIT_REXW_XS, /* 3087 */ IC_OPSIZE, /* 3088 */ IC_64BIT_OPSIZE, /* 3089 */ IC_XS_OPSIZE, /* 3090 */ IC_64BIT_XS_OPSIZE, /* 3091 */ IC_XD_OPSIZE, /* 3092 */ IC_64BIT_XD_OPSIZE, /* 3093 */ IC_XS_OPSIZE, /* 3094 */ IC_64BIT_XD_OPSIZE, /* 3095 */ IC_OPSIZE, /* 3096 */ IC_64BIT_REXW_OPSIZE, /* 3097 */ IC_XS_OPSIZE, /* 3098 */ IC_64BIT_REXW_XS, /* 3099 */ IC_XD_OPSIZE, /* 3100 */ IC_64BIT_REXW_XD, /* 3101 */ IC_XS_OPSIZE, /* 3102 */ IC_64BIT_REXW_XS, /* 3103 */ IC_ADSIZE, /* 3104 */ IC_64BIT_ADSIZE, /* 3105 */ IC_XS_ADSIZE, /* 3106 */ IC_64BIT_XS_ADSIZE, /* 3107 */ IC_XD_ADSIZE, /* 3108 */ IC_64BIT_XD_ADSIZE, /* 3109 */ IC_XS_ADSIZE, /* 3110 */ IC_64BIT_XD_ADSIZE, /* 3111 */ IC_ADSIZE, /* 3112 */ IC_64BIT_REXW_ADSIZE, /* 3113 */ IC_XS_ADSIZE, /* 3114 */ IC_64BIT_REXW_XS, /* 3115 */ IC_XD_ADSIZE, /* 3116 */ IC_64BIT_REXW_XD, /* 3117 */ IC_XS_ADSIZE, /* 3118 */ IC_64BIT_REXW_XS, /* 3119 */ IC_OPSIZE_ADSIZE, /* 3120 */ IC_64BIT_OPSIZE_ADSIZE, /* 3121 */ IC_XS_OPSIZE, /* 3122 */ IC_64BIT_XS_OPSIZE, /* 3123 */ IC_XD_OPSIZE, /* 3124 */ IC_64BIT_XD_OPSIZE, /* 3125 */ IC_XS_OPSIZE, /* 3126 */ IC_64BIT_XD_OPSIZE, /* 3127 */ IC_OPSIZE_ADSIZE, /* 3128 */ IC_64BIT_REXW_OPSIZE, /* 3129 */ IC_XS_OPSIZE, /* 3130 */ IC_64BIT_REXW_XS, /* 3131 */ IC_XD_OPSIZE, /* 3132 */ IC_64BIT_REXW_XD, /* 3133 */ IC_XS_OPSIZE, /* 3134 */ IC_64BIT_REXW_XS, /* 3135 */ IC_VEX, /* 3136 */ IC_VEX, /* 3137 */ IC_VEX_XS, /* 3138 */ IC_VEX_XS, /* 3139 */ IC_VEX_XD, /* 3140 */ IC_VEX_XD, /* 3141 */ IC_VEX_XD, /* 3142 */ IC_VEX_XD, /* 3143 */ IC_VEX_W, /* 3144 */ IC_VEX_W, /* 3145 */ IC_VEX_W_XS, /* 3146 */ IC_VEX_W_XS, /* 3147 */ IC_VEX_W_XD, /* 3148 */ IC_VEX_W_XD, /* 3149 */ IC_VEX_W_XD, /* 3150 */ IC_VEX_W_XD, /* 3151 */ IC_VEX_OPSIZE, /* 3152 */ IC_VEX_OPSIZE, /* 3153 */ IC_VEX_OPSIZE, /* 3154 */ IC_VEX_OPSIZE, /* 3155 */ IC_VEX_OPSIZE, /* 3156 */ IC_VEX_OPSIZE, /* 3157 */ IC_VEX_OPSIZE, /* 3158 */ IC_VEX_OPSIZE, /* 3159 */ IC_VEX_W_OPSIZE, /* 3160 */ IC_VEX_W_OPSIZE, /* 3161 */ IC_VEX_W_OPSIZE, /* 3162 */ IC_VEX_W_OPSIZE, /* 3163 */ IC_VEX_W_OPSIZE, /* 3164 */ IC_VEX_W_OPSIZE, /* 3165 */ IC_VEX_W_OPSIZE, /* 3166 */ IC_VEX_W_OPSIZE, /* 3167 */ IC_VEX, /* 3168 */ IC_VEX, /* 3169 */ IC_VEX_XS, /* 3170 */ IC_VEX_XS, /* 3171 */ IC_VEX_XD, /* 3172 */ IC_VEX_XD, /* 3173 */ IC_VEX_XD, /* 3174 */ IC_VEX_XD, /* 3175 */ IC_VEX_W, /* 3176 */ IC_VEX_W, /* 3177 */ IC_VEX_W_XS, /* 3178 */ IC_VEX_W_XS, /* 3179 */ IC_VEX_W_XD, /* 3180 */ IC_VEX_W_XD, /* 3181 */ IC_VEX_W_XD, /* 3182 */ IC_VEX_W_XD, /* 3183 */ IC_VEX_OPSIZE, /* 3184 */ IC_VEX_OPSIZE, /* 3185 */ IC_VEX_OPSIZE, /* 3186 */ IC_VEX_OPSIZE, /* 3187 */ IC_VEX_OPSIZE, /* 3188 */ IC_VEX_OPSIZE, /* 3189 */ IC_VEX_OPSIZE, /* 3190 */ IC_VEX_OPSIZE, /* 3191 */ IC_VEX_W_OPSIZE, /* 3192 */ IC_VEX_W_OPSIZE, /* 3193 */ IC_VEX_W_OPSIZE, /* 3194 */ IC_VEX_W_OPSIZE, /* 3195 */ IC_VEX_W_OPSIZE, /* 3196 */ IC_VEX_W_OPSIZE, /* 3197 */ IC_VEX_W_OPSIZE, /* 3198 */ IC_VEX_W_OPSIZE, /* 3199 */ IC_VEX_L, /* 3200 */ IC_VEX_L, /* 3201 */ IC_VEX_L_XS, /* 3202 */ IC_VEX_L_XS, /* 3203 */ IC_VEX_L_XD, /* 3204 */ IC_VEX_L_XD, /* 3205 */ IC_VEX_L_XD, /* 3206 */ IC_VEX_L_XD, /* 3207 */ IC_VEX_L_W, /* 3208 */ IC_VEX_L_W, /* 3209 */ IC_VEX_L_W_XS, /* 3210 */ IC_VEX_L_W_XS, /* 3211 */ IC_VEX_L_W_XD, /* 3212 */ IC_VEX_L_W_XD, /* 3213 */ IC_VEX_L_W_XD, /* 3214 */ IC_VEX_L_W_XD, /* 3215 */ IC_VEX_L_OPSIZE, /* 3216 */ IC_VEX_L_OPSIZE, /* 3217 */ IC_VEX_L_OPSIZE, /* 3218 */ IC_VEX_L_OPSIZE, /* 3219 */ IC_VEX_L_OPSIZE, /* 3220 */ IC_VEX_L_OPSIZE, /* 3221 */ IC_VEX_L_OPSIZE, /* 3222 */ IC_VEX_L_OPSIZE, /* 3223 */ IC_VEX_L_W_OPSIZE, /* 3224 */ IC_VEX_L_W_OPSIZE, /* 3225 */ IC_VEX_L_W_OPSIZE, /* 3226 */ IC_VEX_L_W_OPSIZE, /* 3227 */ IC_VEX_L_W_OPSIZE, /* 3228 */ IC_VEX_L_W_OPSIZE, /* 3229 */ IC_VEX_L_W_OPSIZE, /* 3230 */ IC_VEX_L_W_OPSIZE, /* 3231 */ IC_VEX_L, /* 3232 */ IC_VEX_L, /* 3233 */ IC_VEX_L_XS, /* 3234 */ IC_VEX_L_XS, /* 3235 */ IC_VEX_L_XD, /* 3236 */ IC_VEX_L_XD, /* 3237 */ IC_VEX_L_XD, /* 3238 */ IC_VEX_L_XD, /* 3239 */ IC_VEX_L_W, /* 3240 */ IC_VEX_L_W, /* 3241 */ IC_VEX_L_W_XS, /* 3242 */ IC_VEX_L_W_XS, /* 3243 */ IC_VEX_L_W_XD, /* 3244 */ IC_VEX_L_W_XD, /* 3245 */ IC_VEX_L_W_XD, /* 3246 */ IC_VEX_L_W_XD, /* 3247 */ IC_VEX_L_OPSIZE, /* 3248 */ IC_VEX_L_OPSIZE, /* 3249 */ IC_VEX_L_OPSIZE, /* 3250 */ IC_VEX_L_OPSIZE, /* 3251 */ IC_VEX_L_OPSIZE, /* 3252 */ IC_VEX_L_OPSIZE, /* 3253 */ IC_VEX_L_OPSIZE, /* 3254 */ IC_VEX_L_OPSIZE, /* 3255 */ IC_VEX_L_W_OPSIZE, /* 3256 */ IC_VEX_L_W_OPSIZE, /* 3257 */ IC_VEX_L_W_OPSIZE, /* 3258 */ IC_VEX_L_W_OPSIZE, /* 3259 */ IC_VEX_L_W_OPSIZE, /* 3260 */ IC_VEX_L_W_OPSIZE, /* 3261 */ IC_VEX_L_W_OPSIZE, /* 3262 */ IC_VEX_L_W_OPSIZE, /* 3263 */ IC_VEX_L, /* 3264 */ IC_VEX_L, /* 3265 */ IC_VEX_L_XS, /* 3266 */ IC_VEX_L_XS, /* 3267 */ IC_VEX_L_XD, /* 3268 */ IC_VEX_L_XD, /* 3269 */ IC_VEX_L_XD, /* 3270 */ IC_VEX_L_XD, /* 3271 */ IC_VEX_L_W, /* 3272 */ IC_VEX_L_W, /* 3273 */ IC_VEX_L_W_XS, /* 3274 */ IC_VEX_L_W_XS, /* 3275 */ IC_VEX_L_W_XD, /* 3276 */ IC_VEX_L_W_XD, /* 3277 */ IC_VEX_L_W_XD, /* 3278 */ IC_VEX_L_W_XD, /* 3279 */ IC_VEX_L_OPSIZE, /* 3280 */ IC_VEX_L_OPSIZE, /* 3281 */ IC_VEX_L_OPSIZE, /* 3282 */ IC_VEX_L_OPSIZE, /* 3283 */ IC_VEX_L_OPSIZE, /* 3284 */ IC_VEX_L_OPSIZE, /* 3285 */ IC_VEX_L_OPSIZE, /* 3286 */ IC_VEX_L_OPSIZE, /* 3287 */ IC_VEX_L_W_OPSIZE, /* 3288 */ IC_VEX_L_W_OPSIZE, /* 3289 */ IC_VEX_L_W_OPSIZE, /* 3290 */ IC_VEX_L_W_OPSIZE, /* 3291 */ IC_VEX_L_W_OPSIZE, /* 3292 */ IC_VEX_L_W_OPSIZE, /* 3293 */ IC_VEX_L_W_OPSIZE, /* 3294 */ IC_VEX_L_W_OPSIZE, /* 3295 */ IC_VEX_L, /* 3296 */ IC_VEX_L, /* 3297 */ IC_VEX_L_XS, /* 3298 */ IC_VEX_L_XS, /* 3299 */ IC_VEX_L_XD, /* 3300 */ IC_VEX_L_XD, /* 3301 */ IC_VEX_L_XD, /* 3302 */ IC_VEX_L_XD, /* 3303 */ IC_VEX_L_W, /* 3304 */ IC_VEX_L_W, /* 3305 */ IC_VEX_L_W_XS, /* 3306 */ IC_VEX_L_W_XS, /* 3307 */ IC_VEX_L_W_XD, /* 3308 */ IC_VEX_L_W_XD, /* 3309 */ IC_VEX_L_W_XD, /* 3310 */ IC_VEX_L_W_XD, /* 3311 */ IC_VEX_L_OPSIZE, /* 3312 */ IC_VEX_L_OPSIZE, /* 3313 */ IC_VEX_L_OPSIZE, /* 3314 */ IC_VEX_L_OPSIZE, /* 3315 */ IC_VEX_L_OPSIZE, /* 3316 */ IC_VEX_L_OPSIZE, /* 3317 */ IC_VEX_L_OPSIZE, /* 3318 */ IC_VEX_L_OPSIZE, /* 3319 */ IC_VEX_L_W_OPSIZE, /* 3320 */ IC_VEX_L_W_OPSIZE, /* 3321 */ IC_VEX_L_W_OPSIZE, /* 3322 */ IC_VEX_L_W_OPSIZE, /* 3323 */ IC_VEX_L_W_OPSIZE, /* 3324 */ IC_VEX_L_W_OPSIZE, /* 3325 */ IC_VEX_L_W_OPSIZE, /* 3326 */ IC_VEX_L_W_OPSIZE, /* 3327 */ IC_EVEX_L2_K, /* 3328 */ IC_EVEX_L2_K, /* 3329 */ IC_EVEX_L2_XS_K, /* 3330 */ IC_EVEX_L2_XS_K, /* 3331 */ IC_EVEX_L2_XD_K, /* 3332 */ IC_EVEX_L2_XD_K, /* 3333 */ IC_EVEX_L2_XD_K, /* 3334 */ IC_EVEX_L2_XD_K, /* 3335 */ IC_EVEX_L2_W_K, /* 3336 */ IC_EVEX_L2_W_K, /* 3337 */ IC_EVEX_L2_W_XS_K, /* 3338 */ IC_EVEX_L2_W_XS_K, /* 3339 */ IC_EVEX_L2_W_XD_K, /* 3340 */ IC_EVEX_L2_W_XD_K, /* 3341 */ IC_EVEX_L2_W_XD_K, /* 3342 */ IC_EVEX_L2_W_XD_K, /* 3343 */ IC_EVEX_L2_OPSIZE_K, /* 3344 */ IC_EVEX_L2_OPSIZE_K, /* 3345 */ IC_EVEX_L2_OPSIZE_K, /* 3346 */ IC_EVEX_L2_OPSIZE_K, /* 3347 */ IC_EVEX_L2_OPSIZE_K, /* 3348 */ IC_EVEX_L2_OPSIZE_K, /* 3349 */ IC_EVEX_L2_OPSIZE_K, /* 3350 */ IC_EVEX_L2_OPSIZE_K, /* 3351 */ IC_EVEX_L2_W_OPSIZE_K, /* 3352 */ IC_EVEX_L2_W_OPSIZE_K, /* 3353 */ IC_EVEX_L2_W_OPSIZE_K, /* 3354 */ IC_EVEX_L2_W_OPSIZE_K, /* 3355 */ IC_EVEX_L2_W_OPSIZE_K, /* 3356 */ IC_EVEX_L2_W_OPSIZE_K, /* 3357 */ IC_EVEX_L2_W_OPSIZE_K, /* 3358 */ IC_EVEX_L2_W_OPSIZE_K, /* 3359 */ IC_EVEX_L2_K, /* 3360 */ IC_EVEX_L2_K, /* 3361 */ IC_EVEX_L2_XS_K, /* 3362 */ IC_EVEX_L2_XS_K, /* 3363 */ IC_EVEX_L2_XD_K, /* 3364 */ IC_EVEX_L2_XD_K, /* 3365 */ IC_EVEX_L2_XD_K, /* 3366 */ IC_EVEX_L2_XD_K, /* 3367 */ IC_EVEX_L2_W_K, /* 3368 */ IC_EVEX_L2_W_K, /* 3369 */ IC_EVEX_L2_W_XS_K, /* 3370 */ IC_EVEX_L2_W_XS_K, /* 3371 */ IC_EVEX_L2_W_XD_K, /* 3372 */ IC_EVEX_L2_W_XD_K, /* 3373 */ IC_EVEX_L2_W_XD_K, /* 3374 */ IC_EVEX_L2_W_XD_K, /* 3375 */ IC_EVEX_L2_OPSIZE_K, /* 3376 */ IC_EVEX_L2_OPSIZE_K, /* 3377 */ IC_EVEX_L2_OPSIZE_K, /* 3378 */ IC_EVEX_L2_OPSIZE_K, /* 3379 */ IC_EVEX_L2_OPSIZE_K, /* 3380 */ IC_EVEX_L2_OPSIZE_K, /* 3381 */ IC_EVEX_L2_OPSIZE_K, /* 3382 */ IC_EVEX_L2_OPSIZE_K, /* 3383 */ IC_EVEX_L2_W_OPSIZE_K, /* 3384 */ IC_EVEX_L2_W_OPSIZE_K, /* 3385 */ IC_EVEX_L2_W_OPSIZE_K, /* 3386 */ IC_EVEX_L2_W_OPSIZE_K, /* 3387 */ IC_EVEX_L2_W_OPSIZE_K, /* 3388 */ IC_EVEX_L2_W_OPSIZE_K, /* 3389 */ IC_EVEX_L2_W_OPSIZE_K, /* 3390 */ IC_EVEX_L2_W_OPSIZE_K, /* 3391 */ IC_EVEX_L2_K, /* 3392 */ IC_EVEX_L2_K, /* 3393 */ IC_EVEX_L2_XS_K, /* 3394 */ IC_EVEX_L2_XS_K, /* 3395 */ IC_EVEX_L2_XD_K, /* 3396 */ IC_EVEX_L2_XD_K, /* 3397 */ IC_EVEX_L2_XD_K, /* 3398 */ IC_EVEX_L2_XD_K, /* 3399 */ IC_EVEX_L2_W_K, /* 3400 */ IC_EVEX_L2_W_K, /* 3401 */ IC_EVEX_L2_W_XS_K, /* 3402 */ IC_EVEX_L2_W_XS_K, /* 3403 */ IC_EVEX_L2_W_XD_K, /* 3404 */ IC_EVEX_L2_W_XD_K, /* 3405 */ IC_EVEX_L2_W_XD_K, /* 3406 */ IC_EVEX_L2_W_XD_K, /* 3407 */ IC_EVEX_L2_OPSIZE_K, /* 3408 */ IC_EVEX_L2_OPSIZE_K, /* 3409 */ IC_EVEX_L2_OPSIZE_K, /* 3410 */ IC_EVEX_L2_OPSIZE_K, /* 3411 */ IC_EVEX_L2_OPSIZE_K, /* 3412 */ IC_EVEX_L2_OPSIZE_K, /* 3413 */ IC_EVEX_L2_OPSIZE_K, /* 3414 */ IC_EVEX_L2_OPSIZE_K, /* 3415 */ IC_EVEX_L2_W_OPSIZE_K, /* 3416 */ IC_EVEX_L2_W_OPSIZE_K, /* 3417 */ IC_EVEX_L2_W_OPSIZE_K, /* 3418 */ IC_EVEX_L2_W_OPSIZE_K, /* 3419 */ IC_EVEX_L2_W_OPSIZE_K, /* 3420 */ IC_EVEX_L2_W_OPSIZE_K, /* 3421 */ IC_EVEX_L2_W_OPSIZE_K, /* 3422 */ IC_EVEX_L2_W_OPSIZE_K, /* 3423 */ IC_EVEX_L2_K, /* 3424 */ IC_EVEX_L2_K, /* 3425 */ IC_EVEX_L2_XS_K, /* 3426 */ IC_EVEX_L2_XS_K, /* 3427 */ IC_EVEX_L2_XD_K, /* 3428 */ IC_EVEX_L2_XD_K, /* 3429 */ IC_EVEX_L2_XD_K, /* 3430 */ IC_EVEX_L2_XD_K, /* 3431 */ IC_EVEX_L2_W_K, /* 3432 */ IC_EVEX_L2_W_K, /* 3433 */ IC_EVEX_L2_W_XS_K, /* 3434 */ IC_EVEX_L2_W_XS_K, /* 3435 */ IC_EVEX_L2_W_XD_K, /* 3436 */ IC_EVEX_L2_W_XD_K, /* 3437 */ IC_EVEX_L2_W_XD_K, /* 3438 */ IC_EVEX_L2_W_XD_K, /* 3439 */ IC_EVEX_L2_OPSIZE_K, /* 3440 */ IC_EVEX_L2_OPSIZE_K, /* 3441 */ IC_EVEX_L2_OPSIZE_K, /* 3442 */ IC_EVEX_L2_OPSIZE_K, /* 3443 */ IC_EVEX_L2_OPSIZE_K, /* 3444 */ IC_EVEX_L2_OPSIZE_K, /* 3445 */ IC_EVEX_L2_OPSIZE_K, /* 3446 */ IC_EVEX_L2_OPSIZE_K, /* 3447 */ IC_EVEX_L2_W_OPSIZE_K, /* 3448 */ IC_EVEX_L2_W_OPSIZE_K, /* 3449 */ IC_EVEX_L2_W_OPSIZE_K, /* 3450 */ IC_EVEX_L2_W_OPSIZE_K, /* 3451 */ IC_EVEX_L2_W_OPSIZE_K, /* 3452 */ IC_EVEX_L2_W_OPSIZE_K, /* 3453 */ IC_EVEX_L2_W_OPSIZE_K, /* 3454 */ IC_EVEX_L2_W_OPSIZE_K, /* 3455 */ IC_EVEX_L2_K, /* 3456 */ IC_EVEX_L2_K, /* 3457 */ IC_EVEX_L2_XS_K, /* 3458 */ IC_EVEX_L2_XS_K, /* 3459 */ IC_EVEX_L2_XD_K, /* 3460 */ IC_EVEX_L2_XD_K, /* 3461 */ IC_EVEX_L2_XD_K, /* 3462 */ IC_EVEX_L2_XD_K, /* 3463 */ IC_EVEX_L2_W_K, /* 3464 */ IC_EVEX_L2_W_K, /* 3465 */ IC_EVEX_L2_W_XS_K, /* 3466 */ IC_EVEX_L2_W_XS_K, /* 3467 */ IC_EVEX_L2_W_XD_K, /* 3468 */ IC_EVEX_L2_W_XD_K, /* 3469 */ IC_EVEX_L2_W_XD_K, /* 3470 */ IC_EVEX_L2_W_XD_K, /* 3471 */ IC_EVEX_L2_OPSIZE_K, /* 3472 */ IC_EVEX_L2_OPSIZE_K, /* 3473 */ IC_EVEX_L2_OPSIZE_K, /* 3474 */ IC_EVEX_L2_OPSIZE_K, /* 3475 */ IC_EVEX_L2_OPSIZE_K, /* 3476 */ IC_EVEX_L2_OPSIZE_K, /* 3477 */ IC_EVEX_L2_OPSIZE_K, /* 3478 */ IC_EVEX_L2_OPSIZE_K, /* 3479 */ IC_EVEX_L2_W_OPSIZE_K, /* 3480 */ IC_EVEX_L2_W_OPSIZE_K, /* 3481 */ IC_EVEX_L2_W_OPSIZE_K, /* 3482 */ IC_EVEX_L2_W_OPSIZE_K, /* 3483 */ IC_EVEX_L2_W_OPSIZE_K, /* 3484 */ IC_EVEX_L2_W_OPSIZE_K, /* 3485 */ IC_EVEX_L2_W_OPSIZE_K, /* 3486 */ IC_EVEX_L2_W_OPSIZE_K, /* 3487 */ IC_EVEX_L2_K, /* 3488 */ IC_EVEX_L2_K, /* 3489 */ IC_EVEX_L2_XS_K, /* 3490 */ IC_EVEX_L2_XS_K, /* 3491 */ IC_EVEX_L2_XD_K, /* 3492 */ IC_EVEX_L2_XD_K, /* 3493 */ IC_EVEX_L2_XD_K, /* 3494 */ IC_EVEX_L2_XD_K, /* 3495 */ IC_EVEX_L2_W_K, /* 3496 */ IC_EVEX_L2_W_K, /* 3497 */ IC_EVEX_L2_W_XS_K, /* 3498 */ IC_EVEX_L2_W_XS_K, /* 3499 */ IC_EVEX_L2_W_XD_K, /* 3500 */ IC_EVEX_L2_W_XD_K, /* 3501 */ IC_EVEX_L2_W_XD_K, /* 3502 */ IC_EVEX_L2_W_XD_K, /* 3503 */ IC_EVEX_L2_OPSIZE_K, /* 3504 */ IC_EVEX_L2_OPSIZE_K, /* 3505 */ IC_EVEX_L2_OPSIZE_K, /* 3506 */ IC_EVEX_L2_OPSIZE_K, /* 3507 */ IC_EVEX_L2_OPSIZE_K, /* 3508 */ IC_EVEX_L2_OPSIZE_K, /* 3509 */ IC_EVEX_L2_OPSIZE_K, /* 3510 */ IC_EVEX_L2_OPSIZE_K, /* 3511 */ IC_EVEX_L2_W_OPSIZE_K, /* 3512 */ IC_EVEX_L2_W_OPSIZE_K, /* 3513 */ IC_EVEX_L2_W_OPSIZE_K, /* 3514 */ IC_EVEX_L2_W_OPSIZE_K, /* 3515 */ IC_EVEX_L2_W_OPSIZE_K, /* 3516 */ IC_EVEX_L2_W_OPSIZE_K, /* 3517 */ IC_EVEX_L2_W_OPSIZE_K, /* 3518 */ IC_EVEX_L2_W_OPSIZE_K, /* 3519 */ IC_EVEX_L2_K, /* 3520 */ IC_EVEX_L2_K, /* 3521 */ IC_EVEX_L2_XS_K, /* 3522 */ IC_EVEX_L2_XS_K, /* 3523 */ IC_EVEX_L2_XD_K, /* 3524 */ IC_EVEX_L2_XD_K, /* 3525 */ IC_EVEX_L2_XD_K, /* 3526 */ IC_EVEX_L2_XD_K, /* 3527 */ IC_EVEX_L2_W_K, /* 3528 */ IC_EVEX_L2_W_K, /* 3529 */ IC_EVEX_L2_W_XS_K, /* 3530 */ IC_EVEX_L2_W_XS_K, /* 3531 */ IC_EVEX_L2_W_XD_K, /* 3532 */ IC_EVEX_L2_W_XD_K, /* 3533 */ IC_EVEX_L2_W_XD_K, /* 3534 */ IC_EVEX_L2_W_XD_K, /* 3535 */ IC_EVEX_L2_OPSIZE_K, /* 3536 */ IC_EVEX_L2_OPSIZE_K, /* 3537 */ IC_EVEX_L2_OPSIZE_K, /* 3538 */ IC_EVEX_L2_OPSIZE_K, /* 3539 */ IC_EVEX_L2_OPSIZE_K, /* 3540 */ IC_EVEX_L2_OPSIZE_K, /* 3541 */ IC_EVEX_L2_OPSIZE_K, /* 3542 */ IC_EVEX_L2_OPSIZE_K, /* 3543 */ IC_EVEX_L2_W_OPSIZE_K, /* 3544 */ IC_EVEX_L2_W_OPSIZE_K, /* 3545 */ IC_EVEX_L2_W_OPSIZE_K, /* 3546 */ IC_EVEX_L2_W_OPSIZE_K, /* 3547 */ IC_EVEX_L2_W_OPSIZE_K, /* 3548 */ IC_EVEX_L2_W_OPSIZE_K, /* 3549 */ IC_EVEX_L2_W_OPSIZE_K, /* 3550 */ IC_EVEX_L2_W_OPSIZE_K, /* 3551 */ IC_EVEX_L2_K, /* 3552 */ IC_EVEX_L2_K, /* 3553 */ IC_EVEX_L2_XS_K, /* 3554 */ IC_EVEX_L2_XS_K, /* 3555 */ IC_EVEX_L2_XD_K, /* 3556 */ IC_EVEX_L2_XD_K, /* 3557 */ IC_EVEX_L2_XD_K, /* 3558 */ IC_EVEX_L2_XD_K, /* 3559 */ IC_EVEX_L2_W_K, /* 3560 */ IC_EVEX_L2_W_K, /* 3561 */ IC_EVEX_L2_W_XS_K, /* 3562 */ IC_EVEX_L2_W_XS_K, /* 3563 */ IC_EVEX_L2_W_XD_K, /* 3564 */ IC_EVEX_L2_W_XD_K, /* 3565 */ IC_EVEX_L2_W_XD_K, /* 3566 */ IC_EVEX_L2_W_XD_K, /* 3567 */ IC_EVEX_L2_OPSIZE_K, /* 3568 */ IC_EVEX_L2_OPSIZE_K, /* 3569 */ IC_EVEX_L2_OPSIZE_K, /* 3570 */ IC_EVEX_L2_OPSIZE_K, /* 3571 */ IC_EVEX_L2_OPSIZE_K, /* 3572 */ IC_EVEX_L2_OPSIZE_K, /* 3573 */ IC_EVEX_L2_OPSIZE_K, /* 3574 */ IC_EVEX_L2_OPSIZE_K, /* 3575 */ IC_EVEX_L2_W_OPSIZE_K, /* 3576 */ IC_EVEX_L2_W_OPSIZE_K, /* 3577 */ IC_EVEX_L2_W_OPSIZE_K, /* 3578 */ IC_EVEX_L2_W_OPSIZE_K, /* 3579 */ IC_EVEX_L2_W_OPSIZE_K, /* 3580 */ IC_EVEX_L2_W_OPSIZE_K, /* 3581 */ IC_EVEX_L2_W_OPSIZE_K, /* 3582 */ IC_EVEX_L2_W_OPSIZE_K, /* 3583 */ IC, /* 3584 */ IC_64BIT, /* 3585 */ IC_XS, /* 3586 */ IC_64BIT_XS, /* 3587 */ IC_XD, /* 3588 */ IC_64BIT_XD, /* 3589 */ IC_XS, /* 3590 */ IC_64BIT_XS, /* 3591 */ IC, /* 3592 */ IC_64BIT_REXW, /* 3593 */ IC_XS, /* 3594 */ IC_64BIT_REXW_XS, /* 3595 */ IC_XD, /* 3596 */ IC_64BIT_REXW_XD, /* 3597 */ IC_XS, /* 3598 */ IC_64BIT_REXW_XS, /* 3599 */ IC_OPSIZE, /* 3600 */ IC_64BIT_OPSIZE, /* 3601 */ IC_XS_OPSIZE, /* 3602 */ IC_64BIT_XS_OPSIZE, /* 3603 */ IC_XD_OPSIZE, /* 3604 */ IC_64BIT_XD_OPSIZE, /* 3605 */ IC_XS_OPSIZE, /* 3606 */ IC_64BIT_XD_OPSIZE, /* 3607 */ IC_OPSIZE, /* 3608 */ IC_64BIT_REXW_OPSIZE, /* 3609 */ IC_XS_OPSIZE, /* 3610 */ IC_64BIT_REXW_XS, /* 3611 */ IC_XD_OPSIZE, /* 3612 */ IC_64BIT_REXW_XD, /* 3613 */ IC_XS_OPSIZE, /* 3614 */ IC_64BIT_REXW_XS, /* 3615 */ IC_ADSIZE, /* 3616 */ IC_64BIT_ADSIZE, /* 3617 */ IC_XS_ADSIZE, /* 3618 */ IC_64BIT_XS_ADSIZE, /* 3619 */ IC_XD_ADSIZE, /* 3620 */ IC_64BIT_XD_ADSIZE, /* 3621 */ IC_XS_ADSIZE, /* 3622 */ IC_64BIT_XD_ADSIZE, /* 3623 */ IC_ADSIZE, /* 3624 */ IC_64BIT_REXW_ADSIZE, /* 3625 */ IC_XS_ADSIZE, /* 3626 */ IC_64BIT_REXW_XS, /* 3627 */ IC_XD_ADSIZE, /* 3628 */ IC_64BIT_REXW_XD, /* 3629 */ IC_XS_ADSIZE, /* 3630 */ IC_64BIT_REXW_XS, /* 3631 */ IC_OPSIZE_ADSIZE, /* 3632 */ IC_64BIT_OPSIZE_ADSIZE, /* 3633 */ IC_XS_OPSIZE, /* 3634 */ IC_64BIT_XS_OPSIZE, /* 3635 */ IC_XD_OPSIZE, /* 3636 */ IC_64BIT_XD_OPSIZE, /* 3637 */ IC_XS_OPSIZE, /* 3638 */ IC_64BIT_XD_OPSIZE, /* 3639 */ IC_OPSIZE_ADSIZE, /* 3640 */ IC_64BIT_REXW_OPSIZE, /* 3641 */ IC_XS_OPSIZE, /* 3642 */ IC_64BIT_REXW_XS, /* 3643 */ IC_XD_OPSIZE, /* 3644 */ IC_64BIT_REXW_XD, /* 3645 */ IC_XS_OPSIZE, /* 3646 */ IC_64BIT_REXW_XS, /* 3647 */ IC_VEX, /* 3648 */ IC_VEX, /* 3649 */ IC_VEX_XS, /* 3650 */ IC_VEX_XS, /* 3651 */ IC_VEX_XD, /* 3652 */ IC_VEX_XD, /* 3653 */ IC_VEX_XD, /* 3654 */ IC_VEX_XD, /* 3655 */ IC_VEX_W, /* 3656 */ IC_VEX_W, /* 3657 */ IC_VEX_W_XS, /* 3658 */ IC_VEX_W_XS, /* 3659 */ IC_VEX_W_XD, /* 3660 */ IC_VEX_W_XD, /* 3661 */ IC_VEX_W_XD, /* 3662 */ IC_VEX_W_XD, /* 3663 */ IC_VEX_OPSIZE, /* 3664 */ IC_VEX_OPSIZE, /* 3665 */ IC_VEX_OPSIZE, /* 3666 */ IC_VEX_OPSIZE, /* 3667 */ IC_VEX_OPSIZE, /* 3668 */ IC_VEX_OPSIZE, /* 3669 */ IC_VEX_OPSIZE, /* 3670 */ IC_VEX_OPSIZE, /* 3671 */ IC_VEX_W_OPSIZE, /* 3672 */ IC_VEX_W_OPSIZE, /* 3673 */ IC_VEX_W_OPSIZE, /* 3674 */ IC_VEX_W_OPSIZE, /* 3675 */ IC_VEX_W_OPSIZE, /* 3676 */ IC_VEX_W_OPSIZE, /* 3677 */ IC_VEX_W_OPSIZE, /* 3678 */ IC_VEX_W_OPSIZE, /* 3679 */ IC_VEX, /* 3680 */ IC_VEX, /* 3681 */ IC_VEX_XS, /* 3682 */ IC_VEX_XS, /* 3683 */ IC_VEX_XD, /* 3684 */ IC_VEX_XD, /* 3685 */ IC_VEX_XD, /* 3686 */ IC_VEX_XD, /* 3687 */ IC_VEX_W, /* 3688 */ IC_VEX_W, /* 3689 */ IC_VEX_W_XS, /* 3690 */ IC_VEX_W_XS, /* 3691 */ IC_VEX_W_XD, /* 3692 */ IC_VEX_W_XD, /* 3693 */ IC_VEX_W_XD, /* 3694 */ IC_VEX_W_XD, /* 3695 */ IC_VEX_OPSIZE, /* 3696 */ IC_VEX_OPSIZE, /* 3697 */ IC_VEX_OPSIZE, /* 3698 */ IC_VEX_OPSIZE, /* 3699 */ IC_VEX_OPSIZE, /* 3700 */ IC_VEX_OPSIZE, /* 3701 */ IC_VEX_OPSIZE, /* 3702 */ IC_VEX_OPSIZE, /* 3703 */ IC_VEX_W_OPSIZE, /* 3704 */ IC_VEX_W_OPSIZE, /* 3705 */ IC_VEX_W_OPSIZE, /* 3706 */ IC_VEX_W_OPSIZE, /* 3707 */ IC_VEX_W_OPSIZE, /* 3708 */ IC_VEX_W_OPSIZE, /* 3709 */ IC_VEX_W_OPSIZE, /* 3710 */ IC_VEX_W_OPSIZE, /* 3711 */ IC_VEX_L, /* 3712 */ IC_VEX_L, /* 3713 */ IC_VEX_L_XS, /* 3714 */ IC_VEX_L_XS, /* 3715 */ IC_VEX_L_XD, /* 3716 */ IC_VEX_L_XD, /* 3717 */ IC_VEX_L_XD, /* 3718 */ IC_VEX_L_XD, /* 3719 */ IC_VEX_L_W, /* 3720 */ IC_VEX_L_W, /* 3721 */ IC_VEX_L_W_XS, /* 3722 */ IC_VEX_L_W_XS, /* 3723 */ IC_VEX_L_W_XD, /* 3724 */ IC_VEX_L_W_XD, /* 3725 */ IC_VEX_L_W_XD, /* 3726 */ IC_VEX_L_W_XD, /* 3727 */ IC_VEX_L_OPSIZE, /* 3728 */ IC_VEX_L_OPSIZE, /* 3729 */ IC_VEX_L_OPSIZE, /* 3730 */ IC_VEX_L_OPSIZE, /* 3731 */ IC_VEX_L_OPSIZE, /* 3732 */ IC_VEX_L_OPSIZE, /* 3733 */ IC_VEX_L_OPSIZE, /* 3734 */ IC_VEX_L_OPSIZE, /* 3735 */ IC_VEX_L_W_OPSIZE, /* 3736 */ IC_VEX_L_W_OPSIZE, /* 3737 */ IC_VEX_L_W_OPSIZE, /* 3738 */ IC_VEX_L_W_OPSIZE, /* 3739 */ IC_VEX_L_W_OPSIZE, /* 3740 */ IC_VEX_L_W_OPSIZE, /* 3741 */ IC_VEX_L_W_OPSIZE, /* 3742 */ IC_VEX_L_W_OPSIZE, /* 3743 */ IC_VEX_L, /* 3744 */ IC_VEX_L, /* 3745 */ IC_VEX_L_XS, /* 3746 */ IC_VEX_L_XS, /* 3747 */ IC_VEX_L_XD, /* 3748 */ IC_VEX_L_XD, /* 3749 */ IC_VEX_L_XD, /* 3750 */ IC_VEX_L_XD, /* 3751 */ IC_VEX_L_W, /* 3752 */ IC_VEX_L_W, /* 3753 */ IC_VEX_L_W_XS, /* 3754 */ IC_VEX_L_W_XS, /* 3755 */ IC_VEX_L_W_XD, /* 3756 */ IC_VEX_L_W_XD, /* 3757 */ IC_VEX_L_W_XD, /* 3758 */ IC_VEX_L_W_XD, /* 3759 */ IC_VEX_L_OPSIZE, /* 3760 */ IC_VEX_L_OPSIZE, /* 3761 */ IC_VEX_L_OPSIZE, /* 3762 */ IC_VEX_L_OPSIZE, /* 3763 */ IC_VEX_L_OPSIZE, /* 3764 */ IC_VEX_L_OPSIZE, /* 3765 */ IC_VEX_L_OPSIZE, /* 3766 */ IC_VEX_L_OPSIZE, /* 3767 */ IC_VEX_L_W_OPSIZE, /* 3768 */ IC_VEX_L_W_OPSIZE, /* 3769 */ IC_VEX_L_W_OPSIZE, /* 3770 */ IC_VEX_L_W_OPSIZE, /* 3771 */ IC_VEX_L_W_OPSIZE, /* 3772 */ IC_VEX_L_W_OPSIZE, /* 3773 */ IC_VEX_L_W_OPSIZE, /* 3774 */ IC_VEX_L_W_OPSIZE, /* 3775 */ IC_VEX_L, /* 3776 */ IC_VEX_L, /* 3777 */ IC_VEX_L_XS, /* 3778 */ IC_VEX_L_XS, /* 3779 */ IC_VEX_L_XD, /* 3780 */ IC_VEX_L_XD, /* 3781 */ IC_VEX_L_XD, /* 3782 */ IC_VEX_L_XD, /* 3783 */ IC_VEX_L_W, /* 3784 */ IC_VEX_L_W, /* 3785 */ IC_VEX_L_W_XS, /* 3786 */ IC_VEX_L_W_XS, /* 3787 */ IC_VEX_L_W_XD, /* 3788 */ IC_VEX_L_W_XD, /* 3789 */ IC_VEX_L_W_XD, /* 3790 */ IC_VEX_L_W_XD, /* 3791 */ IC_VEX_L_OPSIZE, /* 3792 */ IC_VEX_L_OPSIZE, /* 3793 */ IC_VEX_L_OPSIZE, /* 3794 */ IC_VEX_L_OPSIZE, /* 3795 */ IC_VEX_L_OPSIZE, /* 3796 */ IC_VEX_L_OPSIZE, /* 3797 */ IC_VEX_L_OPSIZE, /* 3798 */ IC_VEX_L_OPSIZE, /* 3799 */ IC_VEX_L_W_OPSIZE, /* 3800 */ IC_VEX_L_W_OPSIZE, /* 3801 */ IC_VEX_L_W_OPSIZE, /* 3802 */ IC_VEX_L_W_OPSIZE, /* 3803 */ IC_VEX_L_W_OPSIZE, /* 3804 */ IC_VEX_L_W_OPSIZE, /* 3805 */ IC_VEX_L_W_OPSIZE, /* 3806 */ IC_VEX_L_W_OPSIZE, /* 3807 */ IC_VEX_L, /* 3808 */ IC_VEX_L, /* 3809 */ IC_VEX_L_XS, /* 3810 */ IC_VEX_L_XS, /* 3811 */ IC_VEX_L_XD, /* 3812 */ IC_VEX_L_XD, /* 3813 */ IC_VEX_L_XD, /* 3814 */ IC_VEX_L_XD, /* 3815 */ IC_VEX_L_W, /* 3816 */ IC_VEX_L_W, /* 3817 */ IC_VEX_L_W_XS, /* 3818 */ IC_VEX_L_W_XS, /* 3819 */ IC_VEX_L_W_XD, /* 3820 */ IC_VEX_L_W_XD, /* 3821 */ IC_VEX_L_W_XD, /* 3822 */ IC_VEX_L_W_XD, /* 3823 */ IC_VEX_L_OPSIZE, /* 3824 */ IC_VEX_L_OPSIZE, /* 3825 */ IC_VEX_L_OPSIZE, /* 3826 */ IC_VEX_L_OPSIZE, /* 3827 */ IC_VEX_L_OPSIZE, /* 3828 */ IC_VEX_L_OPSIZE, /* 3829 */ IC_VEX_L_OPSIZE, /* 3830 */ IC_VEX_L_OPSIZE, /* 3831 */ IC_VEX_L_W_OPSIZE, /* 3832 */ IC_VEX_L_W_OPSIZE, /* 3833 */ IC_VEX_L_W_OPSIZE, /* 3834 */ IC_VEX_L_W_OPSIZE, /* 3835 */ IC_VEX_L_W_OPSIZE, /* 3836 */ IC_VEX_L_W_OPSIZE, /* 3837 */ IC_VEX_L_W_OPSIZE, /* 3838 */ IC_VEX_L_W_OPSIZE, /* 3839 */ IC_EVEX_L2_K, /* 3840 */ IC_EVEX_L2_K, /* 3841 */ IC_EVEX_L2_XS_K, /* 3842 */ IC_EVEX_L2_XS_K, /* 3843 */ IC_EVEX_L2_XD_K, /* 3844 */ IC_EVEX_L2_XD_K, /* 3845 */ IC_EVEX_L2_XD_K, /* 3846 */ IC_EVEX_L2_XD_K, /* 3847 */ IC_EVEX_L2_W_K, /* 3848 */ IC_EVEX_L2_W_K, /* 3849 */ IC_EVEX_L2_W_XS_K, /* 3850 */ IC_EVEX_L2_W_XS_K, /* 3851 */ IC_EVEX_L2_W_XD_K, /* 3852 */ IC_EVEX_L2_W_XD_K, /* 3853 */ IC_EVEX_L2_W_XD_K, /* 3854 */ IC_EVEX_L2_W_XD_K, /* 3855 */ IC_EVEX_L2_OPSIZE_K, /* 3856 */ IC_EVEX_L2_OPSIZE_K, /* 3857 */ IC_EVEX_L2_OPSIZE_K, /* 3858 */ IC_EVEX_L2_OPSIZE_K, /* 3859 */ IC_EVEX_L2_OPSIZE_K, /* 3860 */ IC_EVEX_L2_OPSIZE_K, /* 3861 */ IC_EVEX_L2_OPSIZE_K, /* 3862 */ IC_EVEX_L2_OPSIZE_K, /* 3863 */ IC_EVEX_L2_W_OPSIZE_K, /* 3864 */ IC_EVEX_L2_W_OPSIZE_K, /* 3865 */ IC_EVEX_L2_W_OPSIZE_K, /* 3866 */ IC_EVEX_L2_W_OPSIZE_K, /* 3867 */ IC_EVEX_L2_W_OPSIZE_K, /* 3868 */ IC_EVEX_L2_W_OPSIZE_K, /* 3869 */ IC_EVEX_L2_W_OPSIZE_K, /* 3870 */ IC_EVEX_L2_W_OPSIZE_K, /* 3871 */ IC_EVEX_L2_K, /* 3872 */ IC_EVEX_L2_K, /* 3873 */ IC_EVEX_L2_XS_K, /* 3874 */ IC_EVEX_L2_XS_K, /* 3875 */ IC_EVEX_L2_XD_K, /* 3876 */ IC_EVEX_L2_XD_K, /* 3877 */ IC_EVEX_L2_XD_K, /* 3878 */ IC_EVEX_L2_XD_K, /* 3879 */ IC_EVEX_L2_W_K, /* 3880 */ IC_EVEX_L2_W_K, /* 3881 */ IC_EVEX_L2_W_XS_K, /* 3882 */ IC_EVEX_L2_W_XS_K, /* 3883 */ IC_EVEX_L2_W_XD_K, /* 3884 */ IC_EVEX_L2_W_XD_K, /* 3885 */ IC_EVEX_L2_W_XD_K, /* 3886 */ IC_EVEX_L2_W_XD_K, /* 3887 */ IC_EVEX_L2_OPSIZE_K, /* 3888 */ IC_EVEX_L2_OPSIZE_K, /* 3889 */ IC_EVEX_L2_OPSIZE_K, /* 3890 */ IC_EVEX_L2_OPSIZE_K, /* 3891 */ IC_EVEX_L2_OPSIZE_K, /* 3892 */ IC_EVEX_L2_OPSIZE_K, /* 3893 */ IC_EVEX_L2_OPSIZE_K, /* 3894 */ IC_EVEX_L2_OPSIZE_K, /* 3895 */ IC_EVEX_L2_W_OPSIZE_K, /* 3896 */ IC_EVEX_L2_W_OPSIZE_K, /* 3897 */ IC_EVEX_L2_W_OPSIZE_K, /* 3898 */ IC_EVEX_L2_W_OPSIZE_K, /* 3899 */ IC_EVEX_L2_W_OPSIZE_K, /* 3900 */ IC_EVEX_L2_W_OPSIZE_K, /* 3901 */ IC_EVEX_L2_W_OPSIZE_K, /* 3902 */ IC_EVEX_L2_W_OPSIZE_K, /* 3903 */ IC_EVEX_L2_K, /* 3904 */ IC_EVEX_L2_K, /* 3905 */ IC_EVEX_L2_XS_K, /* 3906 */ IC_EVEX_L2_XS_K, /* 3907 */ IC_EVEX_L2_XD_K, /* 3908 */ IC_EVEX_L2_XD_K, /* 3909 */ IC_EVEX_L2_XD_K, /* 3910 */ IC_EVEX_L2_XD_K, /* 3911 */ IC_EVEX_L2_W_K, /* 3912 */ IC_EVEX_L2_W_K, /* 3913 */ IC_EVEX_L2_W_XS_K, /* 3914 */ IC_EVEX_L2_W_XS_K, /* 3915 */ IC_EVEX_L2_W_XD_K, /* 3916 */ IC_EVEX_L2_W_XD_K, /* 3917 */ IC_EVEX_L2_W_XD_K, /* 3918 */ IC_EVEX_L2_W_XD_K, /* 3919 */ IC_EVEX_L2_OPSIZE_K, /* 3920 */ IC_EVEX_L2_OPSIZE_K, /* 3921 */ IC_EVEX_L2_OPSIZE_K, /* 3922 */ IC_EVEX_L2_OPSIZE_K, /* 3923 */ IC_EVEX_L2_OPSIZE_K, /* 3924 */ IC_EVEX_L2_OPSIZE_K, /* 3925 */ IC_EVEX_L2_OPSIZE_K, /* 3926 */ IC_EVEX_L2_OPSIZE_K, /* 3927 */ IC_EVEX_L2_W_OPSIZE_K, /* 3928 */ IC_EVEX_L2_W_OPSIZE_K, /* 3929 */ IC_EVEX_L2_W_OPSIZE_K, /* 3930 */ IC_EVEX_L2_W_OPSIZE_K, /* 3931 */ IC_EVEX_L2_W_OPSIZE_K, /* 3932 */ IC_EVEX_L2_W_OPSIZE_K, /* 3933 */ IC_EVEX_L2_W_OPSIZE_K, /* 3934 */ IC_EVEX_L2_W_OPSIZE_K, /* 3935 */ IC_EVEX_L2_K, /* 3936 */ IC_EVEX_L2_K, /* 3937 */ IC_EVEX_L2_XS_K, /* 3938 */ IC_EVEX_L2_XS_K, /* 3939 */ IC_EVEX_L2_XD_K, /* 3940 */ IC_EVEX_L2_XD_K, /* 3941 */ IC_EVEX_L2_XD_K, /* 3942 */ IC_EVEX_L2_XD_K, /* 3943 */ IC_EVEX_L2_W_K, /* 3944 */ IC_EVEX_L2_W_K, /* 3945 */ IC_EVEX_L2_W_XS_K, /* 3946 */ IC_EVEX_L2_W_XS_K, /* 3947 */ IC_EVEX_L2_W_XD_K, /* 3948 */ IC_EVEX_L2_W_XD_K, /* 3949 */ IC_EVEX_L2_W_XD_K, /* 3950 */ IC_EVEX_L2_W_XD_K, /* 3951 */ IC_EVEX_L2_OPSIZE_K, /* 3952 */ IC_EVEX_L2_OPSIZE_K, /* 3953 */ IC_EVEX_L2_OPSIZE_K, /* 3954 */ IC_EVEX_L2_OPSIZE_K, /* 3955 */ IC_EVEX_L2_OPSIZE_K, /* 3956 */ IC_EVEX_L2_OPSIZE_K, /* 3957 */ IC_EVEX_L2_OPSIZE_K, /* 3958 */ IC_EVEX_L2_OPSIZE_K, /* 3959 */ IC_EVEX_L2_W_OPSIZE_K, /* 3960 */ IC_EVEX_L2_W_OPSIZE_K, /* 3961 */ IC_EVEX_L2_W_OPSIZE_K, /* 3962 */ IC_EVEX_L2_W_OPSIZE_K, /* 3963 */ IC_EVEX_L2_W_OPSIZE_K, /* 3964 */ IC_EVEX_L2_W_OPSIZE_K, /* 3965 */ IC_EVEX_L2_W_OPSIZE_K, /* 3966 */ IC_EVEX_L2_W_OPSIZE_K, /* 3967 */ IC_EVEX_L2_K, /* 3968 */ IC_EVEX_L2_K, /* 3969 */ IC_EVEX_L2_XS_K, /* 3970 */ IC_EVEX_L2_XS_K, /* 3971 */ IC_EVEX_L2_XD_K, /* 3972 */ IC_EVEX_L2_XD_K, /* 3973 */ IC_EVEX_L2_XD_K, /* 3974 */ IC_EVEX_L2_XD_K, /* 3975 */ IC_EVEX_L2_W_K, /* 3976 */ IC_EVEX_L2_W_K, /* 3977 */ IC_EVEX_L2_W_XS_K, /* 3978 */ IC_EVEX_L2_W_XS_K, /* 3979 */ IC_EVEX_L2_W_XD_K, /* 3980 */ IC_EVEX_L2_W_XD_K, /* 3981 */ IC_EVEX_L2_W_XD_K, /* 3982 */ IC_EVEX_L2_W_XD_K, /* 3983 */ IC_EVEX_L2_OPSIZE_K, /* 3984 */ IC_EVEX_L2_OPSIZE_K, /* 3985 */ IC_EVEX_L2_OPSIZE_K, /* 3986 */ IC_EVEX_L2_OPSIZE_K, /* 3987 */ IC_EVEX_L2_OPSIZE_K, /* 3988 */ IC_EVEX_L2_OPSIZE_K, /* 3989 */ IC_EVEX_L2_OPSIZE_K, /* 3990 */ IC_EVEX_L2_OPSIZE_K, /* 3991 */ IC_EVEX_L2_W_OPSIZE_K, /* 3992 */ IC_EVEX_L2_W_OPSIZE_K, /* 3993 */ IC_EVEX_L2_W_OPSIZE_K, /* 3994 */ IC_EVEX_L2_W_OPSIZE_K, /* 3995 */ IC_EVEX_L2_W_OPSIZE_K, /* 3996 */ IC_EVEX_L2_W_OPSIZE_K, /* 3997 */ IC_EVEX_L2_W_OPSIZE_K, /* 3998 */ IC_EVEX_L2_W_OPSIZE_K, /* 3999 */ IC_EVEX_L2_K, /* 4000 */ IC_EVEX_L2_K, /* 4001 */ IC_EVEX_L2_XS_K, /* 4002 */ IC_EVEX_L2_XS_K, /* 4003 */ IC_EVEX_L2_XD_K, /* 4004 */ IC_EVEX_L2_XD_K, /* 4005 */ IC_EVEX_L2_XD_K, /* 4006 */ IC_EVEX_L2_XD_K, /* 4007 */ IC_EVEX_L2_W_K, /* 4008 */ IC_EVEX_L2_W_K, /* 4009 */ IC_EVEX_L2_W_XS_K, /* 4010 */ IC_EVEX_L2_W_XS_K, /* 4011 */ IC_EVEX_L2_W_XD_K, /* 4012 */ IC_EVEX_L2_W_XD_K, /* 4013 */ IC_EVEX_L2_W_XD_K, /* 4014 */ IC_EVEX_L2_W_XD_K, /* 4015 */ IC_EVEX_L2_OPSIZE_K, /* 4016 */ IC_EVEX_L2_OPSIZE_K, /* 4017 */ IC_EVEX_L2_OPSIZE_K, /* 4018 */ IC_EVEX_L2_OPSIZE_K, /* 4019 */ IC_EVEX_L2_OPSIZE_K, /* 4020 */ IC_EVEX_L2_OPSIZE_K, /* 4021 */ IC_EVEX_L2_OPSIZE_K, /* 4022 */ IC_EVEX_L2_OPSIZE_K, /* 4023 */ IC_EVEX_L2_W_OPSIZE_K, /* 4024 */ IC_EVEX_L2_W_OPSIZE_K, /* 4025 */ IC_EVEX_L2_W_OPSIZE_K, /* 4026 */ IC_EVEX_L2_W_OPSIZE_K, /* 4027 */ IC_EVEX_L2_W_OPSIZE_K, /* 4028 */ IC_EVEX_L2_W_OPSIZE_K, /* 4029 */ IC_EVEX_L2_W_OPSIZE_K, /* 4030 */ IC_EVEX_L2_W_OPSIZE_K, /* 4031 */ IC_EVEX_L2_K, /* 4032 */ IC_EVEX_L2_K, /* 4033 */ IC_EVEX_L2_XS_K, /* 4034 */ IC_EVEX_L2_XS_K, /* 4035 */ IC_EVEX_L2_XD_K, /* 4036 */ IC_EVEX_L2_XD_K, /* 4037 */ IC_EVEX_L2_XD_K, /* 4038 */ IC_EVEX_L2_XD_K, /* 4039 */ IC_EVEX_L2_W_K, /* 4040 */ IC_EVEX_L2_W_K, /* 4041 */ IC_EVEX_L2_W_XS_K, /* 4042 */ IC_EVEX_L2_W_XS_K, /* 4043 */ IC_EVEX_L2_W_XD_K, /* 4044 */ IC_EVEX_L2_W_XD_K, /* 4045 */ IC_EVEX_L2_W_XD_K, /* 4046 */ IC_EVEX_L2_W_XD_K, /* 4047 */ IC_EVEX_L2_OPSIZE_K, /* 4048 */ IC_EVEX_L2_OPSIZE_K, /* 4049 */ IC_EVEX_L2_OPSIZE_K, /* 4050 */ IC_EVEX_L2_OPSIZE_K, /* 4051 */ IC_EVEX_L2_OPSIZE_K, /* 4052 */ IC_EVEX_L2_OPSIZE_K, /* 4053 */ IC_EVEX_L2_OPSIZE_K, /* 4054 */ IC_EVEX_L2_OPSIZE_K, /* 4055 */ IC_EVEX_L2_W_OPSIZE_K, /* 4056 */ IC_EVEX_L2_W_OPSIZE_K, /* 4057 */ IC_EVEX_L2_W_OPSIZE_K, /* 4058 */ IC_EVEX_L2_W_OPSIZE_K, /* 4059 */ IC_EVEX_L2_W_OPSIZE_K, /* 4060 */ IC_EVEX_L2_W_OPSIZE_K, /* 4061 */ IC_EVEX_L2_W_OPSIZE_K, /* 4062 */ IC_EVEX_L2_W_OPSIZE_K, /* 4063 */ IC_EVEX_L2_K, /* 4064 */ IC_EVEX_L2_K, /* 4065 */ IC_EVEX_L2_XS_K, /* 4066 */ IC_EVEX_L2_XS_K, /* 4067 */ IC_EVEX_L2_XD_K, /* 4068 */ IC_EVEX_L2_XD_K, /* 4069 */ IC_EVEX_L2_XD_K, /* 4070 */ IC_EVEX_L2_XD_K, /* 4071 */ IC_EVEX_L2_W_K, /* 4072 */ IC_EVEX_L2_W_K, /* 4073 */ IC_EVEX_L2_W_XS_K, /* 4074 */ IC_EVEX_L2_W_XS_K, /* 4075 */ IC_EVEX_L2_W_XD_K, /* 4076 */ IC_EVEX_L2_W_XD_K, /* 4077 */ IC_EVEX_L2_W_XD_K, /* 4078 */ IC_EVEX_L2_W_XD_K, /* 4079 */ IC_EVEX_L2_OPSIZE_K, /* 4080 */ IC_EVEX_L2_OPSIZE_K, /* 4081 */ IC_EVEX_L2_OPSIZE_K, /* 4082 */ IC_EVEX_L2_OPSIZE_K, /* 4083 */ IC_EVEX_L2_OPSIZE_K, /* 4084 */ IC_EVEX_L2_OPSIZE_K, /* 4085 */ IC_EVEX_L2_OPSIZE_K, /* 4086 */ IC_EVEX_L2_OPSIZE_K, /* 4087 */ IC_EVEX_L2_W_OPSIZE_K, /* 4088 */ IC_EVEX_L2_W_OPSIZE_K, /* 4089 */ IC_EVEX_L2_W_OPSIZE_K, /* 4090 */ IC_EVEX_L2_W_OPSIZE_K, /* 4091 */ IC_EVEX_L2_W_OPSIZE_K, /* 4092 */ IC_EVEX_L2_W_OPSIZE_K, /* 4093 */ IC_EVEX_L2_W_OPSIZE_K, /* 4094 */ IC_EVEX_L2_W_OPSIZE_K, /* 4095 */ IC, /* 4096 */ IC_64BIT, /* 4097 */ IC_XS, /* 4098 */ IC_64BIT_XS, /* 4099 */ IC_XD, /* 4100 */ IC_64BIT_XD, /* 4101 */ IC_XS, /* 4102 */ IC_64BIT_XS, /* 4103 */ IC, /* 4104 */ IC_64BIT_REXW, /* 4105 */ IC_XS, /* 4106 */ IC_64BIT_REXW_XS, /* 4107 */ IC_XD, /* 4108 */ IC_64BIT_REXW_XD, /* 4109 */ IC_XS, /* 4110 */ IC_64BIT_REXW_XS, /* 4111 */ IC_OPSIZE, /* 4112 */ IC_64BIT_OPSIZE, /* 4113 */ IC_XS_OPSIZE, /* 4114 */ IC_64BIT_XS_OPSIZE, /* 4115 */ IC_XD_OPSIZE, /* 4116 */ IC_64BIT_XD_OPSIZE, /* 4117 */ IC_XS_OPSIZE, /* 4118 */ IC_64BIT_XD_OPSIZE, /* 4119 */ IC_OPSIZE, /* 4120 */ IC_64BIT_REXW_OPSIZE, /* 4121 */ IC_XS_OPSIZE, /* 4122 */ IC_64BIT_REXW_XS, /* 4123 */ IC_XD_OPSIZE, /* 4124 */ IC_64BIT_REXW_XD, /* 4125 */ IC_XS_OPSIZE, /* 4126 */ IC_64BIT_REXW_XS, /* 4127 */ IC_ADSIZE, /* 4128 */ IC_64BIT_ADSIZE, /* 4129 */ IC_XS_ADSIZE, /* 4130 */ IC_64BIT_XS_ADSIZE, /* 4131 */ IC_XD_ADSIZE, /* 4132 */ IC_64BIT_XD_ADSIZE, /* 4133 */ IC_XS_ADSIZE, /* 4134 */ IC_64BIT_XD_ADSIZE, /* 4135 */ IC_ADSIZE, /* 4136 */ IC_64BIT_REXW_ADSIZE, /* 4137 */ IC_XS_ADSIZE, /* 4138 */ IC_64BIT_REXW_XS, /* 4139 */ IC_XD_ADSIZE, /* 4140 */ IC_64BIT_REXW_XD, /* 4141 */ IC_XS_ADSIZE, /* 4142 */ IC_64BIT_REXW_XS, /* 4143 */ IC_OPSIZE_ADSIZE, /* 4144 */ IC_64BIT_OPSIZE_ADSIZE, /* 4145 */ IC_XS_OPSIZE, /* 4146 */ IC_64BIT_XS_OPSIZE, /* 4147 */ IC_XD_OPSIZE, /* 4148 */ IC_64BIT_XD_OPSIZE, /* 4149 */ IC_XS_OPSIZE, /* 4150 */ IC_64BIT_XD_OPSIZE, /* 4151 */ IC_OPSIZE_ADSIZE, /* 4152 */ IC_64BIT_REXW_OPSIZE, /* 4153 */ IC_XS_OPSIZE, /* 4154 */ IC_64BIT_REXW_XS, /* 4155 */ IC_XD_OPSIZE, /* 4156 */ IC_64BIT_REXW_XD, /* 4157 */ IC_XS_OPSIZE, /* 4158 */ IC_64BIT_REXW_XS, /* 4159 */ IC_VEX, /* 4160 */ IC_VEX, /* 4161 */ IC_VEX_XS, /* 4162 */ IC_VEX_XS, /* 4163 */ IC_VEX_XD, /* 4164 */ IC_VEX_XD, /* 4165 */ IC_VEX_XD, /* 4166 */ IC_VEX_XD, /* 4167 */ IC_VEX_W, /* 4168 */ IC_VEX_W, /* 4169 */ IC_VEX_W_XS, /* 4170 */ IC_VEX_W_XS, /* 4171 */ IC_VEX_W_XD, /* 4172 */ IC_VEX_W_XD, /* 4173 */ IC_VEX_W_XD, /* 4174 */ IC_VEX_W_XD, /* 4175 */ IC_VEX_OPSIZE, /* 4176 */ IC_VEX_OPSIZE, /* 4177 */ IC_VEX_OPSIZE, /* 4178 */ IC_VEX_OPSIZE, /* 4179 */ IC_VEX_OPSIZE, /* 4180 */ IC_VEX_OPSIZE, /* 4181 */ IC_VEX_OPSIZE, /* 4182 */ IC_VEX_OPSIZE, /* 4183 */ IC_VEX_W_OPSIZE, /* 4184 */ IC_VEX_W_OPSIZE, /* 4185 */ IC_VEX_W_OPSIZE, /* 4186 */ IC_VEX_W_OPSIZE, /* 4187 */ IC_VEX_W_OPSIZE, /* 4188 */ IC_VEX_W_OPSIZE, /* 4189 */ IC_VEX_W_OPSIZE, /* 4190 */ IC_VEX_W_OPSIZE, /* 4191 */ IC_VEX, /* 4192 */ IC_VEX, /* 4193 */ IC_VEX_XS, /* 4194 */ IC_VEX_XS, /* 4195 */ IC_VEX_XD, /* 4196 */ IC_VEX_XD, /* 4197 */ IC_VEX_XD, /* 4198 */ IC_VEX_XD, /* 4199 */ IC_VEX_W, /* 4200 */ IC_VEX_W, /* 4201 */ IC_VEX_W_XS, /* 4202 */ IC_VEX_W_XS, /* 4203 */ IC_VEX_W_XD, /* 4204 */ IC_VEX_W_XD, /* 4205 */ IC_VEX_W_XD, /* 4206 */ IC_VEX_W_XD, /* 4207 */ IC_VEX_OPSIZE, /* 4208 */ IC_VEX_OPSIZE, /* 4209 */ IC_VEX_OPSIZE, /* 4210 */ IC_VEX_OPSIZE, /* 4211 */ IC_VEX_OPSIZE, /* 4212 */ IC_VEX_OPSIZE, /* 4213 */ IC_VEX_OPSIZE, /* 4214 */ IC_VEX_OPSIZE, /* 4215 */ IC_VEX_W_OPSIZE, /* 4216 */ IC_VEX_W_OPSIZE, /* 4217 */ IC_VEX_W_OPSIZE, /* 4218 */ IC_VEX_W_OPSIZE, /* 4219 */ IC_VEX_W_OPSIZE, /* 4220 */ IC_VEX_W_OPSIZE, /* 4221 */ IC_VEX_W_OPSIZE, /* 4222 */ IC_VEX_W_OPSIZE, /* 4223 */ IC_VEX_L, /* 4224 */ IC_VEX_L, /* 4225 */ IC_VEX_L_XS, /* 4226 */ IC_VEX_L_XS, /* 4227 */ IC_VEX_L_XD, /* 4228 */ IC_VEX_L_XD, /* 4229 */ IC_VEX_L_XD, /* 4230 */ IC_VEX_L_XD, /* 4231 */ IC_VEX_L_W, /* 4232 */ IC_VEX_L_W, /* 4233 */ IC_VEX_L_W_XS, /* 4234 */ IC_VEX_L_W_XS, /* 4235 */ IC_VEX_L_W_XD, /* 4236 */ IC_VEX_L_W_XD, /* 4237 */ IC_VEX_L_W_XD, /* 4238 */ IC_VEX_L_W_XD, /* 4239 */ IC_VEX_L_OPSIZE, /* 4240 */ IC_VEX_L_OPSIZE, /* 4241 */ IC_VEX_L_OPSIZE, /* 4242 */ IC_VEX_L_OPSIZE, /* 4243 */ IC_VEX_L_OPSIZE, /* 4244 */ IC_VEX_L_OPSIZE, /* 4245 */ IC_VEX_L_OPSIZE, /* 4246 */ IC_VEX_L_OPSIZE, /* 4247 */ IC_VEX_L_W_OPSIZE, /* 4248 */ IC_VEX_L_W_OPSIZE, /* 4249 */ IC_VEX_L_W_OPSIZE, /* 4250 */ IC_VEX_L_W_OPSIZE, /* 4251 */ IC_VEX_L_W_OPSIZE, /* 4252 */ IC_VEX_L_W_OPSIZE, /* 4253 */ IC_VEX_L_W_OPSIZE, /* 4254 */ IC_VEX_L_W_OPSIZE, /* 4255 */ IC_VEX_L, /* 4256 */ IC_VEX_L, /* 4257 */ IC_VEX_L_XS, /* 4258 */ IC_VEX_L_XS, /* 4259 */ IC_VEX_L_XD, /* 4260 */ IC_VEX_L_XD, /* 4261 */ IC_VEX_L_XD, /* 4262 */ IC_VEX_L_XD, /* 4263 */ IC_VEX_L_W, /* 4264 */ IC_VEX_L_W, /* 4265 */ IC_VEX_L_W_XS, /* 4266 */ IC_VEX_L_W_XS, /* 4267 */ IC_VEX_L_W_XD, /* 4268 */ IC_VEX_L_W_XD, /* 4269 */ IC_VEX_L_W_XD, /* 4270 */ IC_VEX_L_W_XD, /* 4271 */ IC_VEX_L_OPSIZE, /* 4272 */ IC_VEX_L_OPSIZE, /* 4273 */ IC_VEX_L_OPSIZE, /* 4274 */ IC_VEX_L_OPSIZE, /* 4275 */ IC_VEX_L_OPSIZE, /* 4276 */ IC_VEX_L_OPSIZE, /* 4277 */ IC_VEX_L_OPSIZE, /* 4278 */ IC_VEX_L_OPSIZE, /* 4279 */ IC_VEX_L_W_OPSIZE, /* 4280 */ IC_VEX_L_W_OPSIZE, /* 4281 */ IC_VEX_L_W_OPSIZE, /* 4282 */ IC_VEX_L_W_OPSIZE, /* 4283 */ IC_VEX_L_W_OPSIZE, /* 4284 */ IC_VEX_L_W_OPSIZE, /* 4285 */ IC_VEX_L_W_OPSIZE, /* 4286 */ IC_VEX_L_W_OPSIZE, /* 4287 */ IC_VEX_L, /* 4288 */ IC_VEX_L, /* 4289 */ IC_VEX_L_XS, /* 4290 */ IC_VEX_L_XS, /* 4291 */ IC_VEX_L_XD, /* 4292 */ IC_VEX_L_XD, /* 4293 */ IC_VEX_L_XD, /* 4294 */ IC_VEX_L_XD, /* 4295 */ IC_VEX_L_W, /* 4296 */ IC_VEX_L_W, /* 4297 */ IC_VEX_L_W_XS, /* 4298 */ IC_VEX_L_W_XS, /* 4299 */ IC_VEX_L_W_XD, /* 4300 */ IC_VEX_L_W_XD, /* 4301 */ IC_VEX_L_W_XD, /* 4302 */ IC_VEX_L_W_XD, /* 4303 */ IC_VEX_L_OPSIZE, /* 4304 */ IC_VEX_L_OPSIZE, /* 4305 */ IC_VEX_L_OPSIZE, /* 4306 */ IC_VEX_L_OPSIZE, /* 4307 */ IC_VEX_L_OPSIZE, /* 4308 */ IC_VEX_L_OPSIZE, /* 4309 */ IC_VEX_L_OPSIZE, /* 4310 */ IC_VEX_L_OPSIZE, /* 4311 */ IC_VEX_L_W_OPSIZE, /* 4312 */ IC_VEX_L_W_OPSIZE, /* 4313 */ IC_VEX_L_W_OPSIZE, /* 4314 */ IC_VEX_L_W_OPSIZE, /* 4315 */ IC_VEX_L_W_OPSIZE, /* 4316 */ IC_VEX_L_W_OPSIZE, /* 4317 */ IC_VEX_L_W_OPSIZE, /* 4318 */ IC_VEX_L_W_OPSIZE, /* 4319 */ IC_VEX_L, /* 4320 */ IC_VEX_L, /* 4321 */ IC_VEX_L_XS, /* 4322 */ IC_VEX_L_XS, /* 4323 */ IC_VEX_L_XD, /* 4324 */ IC_VEX_L_XD, /* 4325 */ IC_VEX_L_XD, /* 4326 */ IC_VEX_L_XD, /* 4327 */ IC_VEX_L_W, /* 4328 */ IC_VEX_L_W, /* 4329 */ IC_VEX_L_W_XS, /* 4330 */ IC_VEX_L_W_XS, /* 4331 */ IC_VEX_L_W_XD, /* 4332 */ IC_VEX_L_W_XD, /* 4333 */ IC_VEX_L_W_XD, /* 4334 */ IC_VEX_L_W_XD, /* 4335 */ IC_VEX_L_OPSIZE, /* 4336 */ IC_VEX_L_OPSIZE, /* 4337 */ IC_VEX_L_OPSIZE, /* 4338 */ IC_VEX_L_OPSIZE, /* 4339 */ IC_VEX_L_OPSIZE, /* 4340 */ IC_VEX_L_OPSIZE, /* 4341 */ IC_VEX_L_OPSIZE, /* 4342 */ IC_VEX_L_OPSIZE, /* 4343 */ IC_VEX_L_W_OPSIZE, /* 4344 */ IC_VEX_L_W_OPSIZE, /* 4345 */ IC_VEX_L_W_OPSIZE, /* 4346 */ IC_VEX_L_W_OPSIZE, /* 4347 */ IC_VEX_L_W_OPSIZE, /* 4348 */ IC_VEX_L_W_OPSIZE, /* 4349 */ IC_VEX_L_W_OPSIZE, /* 4350 */ IC_VEX_L_W_OPSIZE, /* 4351 */ IC_EVEX_KZ, /* 4352 */ IC_EVEX_KZ, /* 4353 */ IC_EVEX_XS_KZ, /* 4354 */ IC_EVEX_XS_KZ, /* 4355 */ IC_EVEX_XD_KZ, /* 4356 */ IC_EVEX_XD_KZ, /* 4357 */ IC_EVEX_XD_KZ, /* 4358 */ IC_EVEX_XD_KZ, /* 4359 */ IC_EVEX_W_KZ, /* 4360 */ IC_EVEX_W_KZ, /* 4361 */ IC_EVEX_W_XS_KZ, /* 4362 */ IC_EVEX_W_XS_KZ, /* 4363 */ IC_EVEX_W_XD_KZ, /* 4364 */ IC_EVEX_W_XD_KZ, /* 4365 */ IC_EVEX_W_XD_KZ, /* 4366 */ IC_EVEX_W_XD_KZ, /* 4367 */ IC_EVEX_OPSIZE_KZ, /* 4368 */ IC_EVEX_OPSIZE_KZ, /* 4369 */ IC_EVEX_OPSIZE_KZ, /* 4370 */ IC_EVEX_OPSIZE_KZ, /* 4371 */ IC_EVEX_OPSIZE_KZ, /* 4372 */ IC_EVEX_OPSIZE_KZ, /* 4373 */ IC_EVEX_OPSIZE_KZ, /* 4374 */ IC_EVEX_OPSIZE_KZ, /* 4375 */ IC_EVEX_W_OPSIZE_KZ, /* 4376 */ IC_EVEX_W_OPSIZE_KZ, /* 4377 */ IC_EVEX_W_OPSIZE_KZ, /* 4378 */ IC_EVEX_W_OPSIZE_KZ, /* 4379 */ IC_EVEX_W_OPSIZE_KZ, /* 4380 */ IC_EVEX_W_OPSIZE_KZ, /* 4381 */ IC_EVEX_W_OPSIZE_KZ, /* 4382 */ IC_EVEX_W_OPSIZE_KZ, /* 4383 */ IC_EVEX_KZ, /* 4384 */ IC_EVEX_KZ, /* 4385 */ IC_EVEX_XS_KZ, /* 4386 */ IC_EVEX_XS_KZ, /* 4387 */ IC_EVEX_XD_KZ, /* 4388 */ IC_EVEX_XD_KZ, /* 4389 */ IC_EVEX_XD_KZ, /* 4390 */ IC_EVEX_XD_KZ, /* 4391 */ IC_EVEX_W_KZ, /* 4392 */ IC_EVEX_W_KZ, /* 4393 */ IC_EVEX_W_XS_KZ, /* 4394 */ IC_EVEX_W_XS_KZ, /* 4395 */ IC_EVEX_W_XD_KZ, /* 4396 */ IC_EVEX_W_XD_KZ, /* 4397 */ IC_EVEX_W_XD_KZ, /* 4398 */ IC_EVEX_W_XD_KZ, /* 4399 */ IC_EVEX_OPSIZE_KZ, /* 4400 */ IC_EVEX_OPSIZE_KZ, /* 4401 */ IC_EVEX_OPSIZE_KZ, /* 4402 */ IC_EVEX_OPSIZE_KZ, /* 4403 */ IC_EVEX_OPSIZE_KZ, /* 4404 */ IC_EVEX_OPSIZE_KZ, /* 4405 */ IC_EVEX_OPSIZE_KZ, /* 4406 */ IC_EVEX_OPSIZE_KZ, /* 4407 */ IC_EVEX_W_OPSIZE_KZ, /* 4408 */ IC_EVEX_W_OPSIZE_KZ, /* 4409 */ IC_EVEX_W_OPSIZE_KZ, /* 4410 */ IC_EVEX_W_OPSIZE_KZ, /* 4411 */ IC_EVEX_W_OPSIZE_KZ, /* 4412 */ IC_EVEX_W_OPSIZE_KZ, /* 4413 */ IC_EVEX_W_OPSIZE_KZ, /* 4414 */ IC_EVEX_W_OPSIZE_KZ, /* 4415 */ IC_EVEX_KZ, /* 4416 */ IC_EVEX_KZ, /* 4417 */ IC_EVEX_XS_KZ, /* 4418 */ IC_EVEX_XS_KZ, /* 4419 */ IC_EVEX_XD_KZ, /* 4420 */ IC_EVEX_XD_KZ, /* 4421 */ IC_EVEX_XD_KZ, /* 4422 */ IC_EVEX_XD_KZ, /* 4423 */ IC_EVEX_W_KZ, /* 4424 */ IC_EVEX_W_KZ, /* 4425 */ IC_EVEX_W_XS_KZ, /* 4426 */ IC_EVEX_W_XS_KZ, /* 4427 */ IC_EVEX_W_XD_KZ, /* 4428 */ IC_EVEX_W_XD_KZ, /* 4429 */ IC_EVEX_W_XD_KZ, /* 4430 */ IC_EVEX_W_XD_KZ, /* 4431 */ IC_EVEX_OPSIZE_KZ, /* 4432 */ IC_EVEX_OPSIZE_KZ, /* 4433 */ IC_EVEX_OPSIZE_KZ, /* 4434 */ IC_EVEX_OPSIZE_KZ, /* 4435 */ IC_EVEX_OPSIZE_KZ, /* 4436 */ IC_EVEX_OPSIZE_KZ, /* 4437 */ IC_EVEX_OPSIZE_KZ, /* 4438 */ IC_EVEX_OPSIZE_KZ, /* 4439 */ IC_EVEX_W_OPSIZE_KZ, /* 4440 */ IC_EVEX_W_OPSIZE_KZ, /* 4441 */ IC_EVEX_W_OPSIZE_KZ, /* 4442 */ IC_EVEX_W_OPSIZE_KZ, /* 4443 */ IC_EVEX_W_OPSIZE_KZ, /* 4444 */ IC_EVEX_W_OPSIZE_KZ, /* 4445 */ IC_EVEX_W_OPSIZE_KZ, /* 4446 */ IC_EVEX_W_OPSIZE_KZ, /* 4447 */ IC_EVEX_KZ, /* 4448 */ IC_EVEX_KZ, /* 4449 */ IC_EVEX_XS_KZ, /* 4450 */ IC_EVEX_XS_KZ, /* 4451 */ IC_EVEX_XD_KZ, /* 4452 */ IC_EVEX_XD_KZ, /* 4453 */ IC_EVEX_XD_KZ, /* 4454 */ IC_EVEX_XD_KZ, /* 4455 */ IC_EVEX_W_KZ, /* 4456 */ IC_EVEX_W_KZ, /* 4457 */ IC_EVEX_W_XS_KZ, /* 4458 */ IC_EVEX_W_XS_KZ, /* 4459 */ IC_EVEX_W_XD_KZ, /* 4460 */ IC_EVEX_W_XD_KZ, /* 4461 */ IC_EVEX_W_XD_KZ, /* 4462 */ IC_EVEX_W_XD_KZ, /* 4463 */ IC_EVEX_OPSIZE_KZ, /* 4464 */ IC_EVEX_OPSIZE_KZ, /* 4465 */ IC_EVEX_OPSIZE_KZ, /* 4466 */ IC_EVEX_OPSIZE_KZ, /* 4467 */ IC_EVEX_OPSIZE_KZ, /* 4468 */ IC_EVEX_OPSIZE_KZ, /* 4469 */ IC_EVEX_OPSIZE_KZ, /* 4470 */ IC_EVEX_OPSIZE_KZ, /* 4471 */ IC_EVEX_W_OPSIZE_KZ, /* 4472 */ IC_EVEX_W_OPSIZE_KZ, /* 4473 */ IC_EVEX_W_OPSIZE_KZ, /* 4474 */ IC_EVEX_W_OPSIZE_KZ, /* 4475 */ IC_EVEX_W_OPSIZE_KZ, /* 4476 */ IC_EVEX_W_OPSIZE_KZ, /* 4477 */ IC_EVEX_W_OPSIZE_KZ, /* 4478 */ IC_EVEX_W_OPSIZE_KZ, /* 4479 */ IC_EVEX_KZ, /* 4480 */ IC_EVEX_KZ, /* 4481 */ IC_EVEX_XS_KZ, /* 4482 */ IC_EVEX_XS_KZ, /* 4483 */ IC_EVEX_XD_KZ, /* 4484 */ IC_EVEX_XD_KZ, /* 4485 */ IC_EVEX_XD_KZ, /* 4486 */ IC_EVEX_XD_KZ, /* 4487 */ IC_EVEX_W_KZ, /* 4488 */ IC_EVEX_W_KZ, /* 4489 */ IC_EVEX_W_XS_KZ, /* 4490 */ IC_EVEX_W_XS_KZ, /* 4491 */ IC_EVEX_W_XD_KZ, /* 4492 */ IC_EVEX_W_XD_KZ, /* 4493 */ IC_EVEX_W_XD_KZ, /* 4494 */ IC_EVEX_W_XD_KZ, /* 4495 */ IC_EVEX_OPSIZE_KZ, /* 4496 */ IC_EVEX_OPSIZE_KZ, /* 4497 */ IC_EVEX_OPSIZE_KZ, /* 4498 */ IC_EVEX_OPSIZE_KZ, /* 4499 */ IC_EVEX_OPSIZE_KZ, /* 4500 */ IC_EVEX_OPSIZE_KZ, /* 4501 */ IC_EVEX_OPSIZE_KZ, /* 4502 */ IC_EVEX_OPSIZE_KZ, /* 4503 */ IC_EVEX_W_OPSIZE_KZ, /* 4504 */ IC_EVEX_W_OPSIZE_KZ, /* 4505 */ IC_EVEX_W_OPSIZE_KZ, /* 4506 */ IC_EVEX_W_OPSIZE_KZ, /* 4507 */ IC_EVEX_W_OPSIZE_KZ, /* 4508 */ IC_EVEX_W_OPSIZE_KZ, /* 4509 */ IC_EVEX_W_OPSIZE_KZ, /* 4510 */ IC_EVEX_W_OPSIZE_KZ, /* 4511 */ IC_EVEX_KZ, /* 4512 */ IC_EVEX_KZ, /* 4513 */ IC_EVEX_XS_KZ, /* 4514 */ IC_EVEX_XS_KZ, /* 4515 */ IC_EVEX_XD_KZ, /* 4516 */ IC_EVEX_XD_KZ, /* 4517 */ IC_EVEX_XD_KZ, /* 4518 */ IC_EVEX_XD_KZ, /* 4519 */ IC_EVEX_W_KZ, /* 4520 */ IC_EVEX_W_KZ, /* 4521 */ IC_EVEX_W_XS_KZ, /* 4522 */ IC_EVEX_W_XS_KZ, /* 4523 */ IC_EVEX_W_XD_KZ, /* 4524 */ IC_EVEX_W_XD_KZ, /* 4525 */ IC_EVEX_W_XD_KZ, /* 4526 */ IC_EVEX_W_XD_KZ, /* 4527 */ IC_EVEX_OPSIZE_KZ, /* 4528 */ IC_EVEX_OPSIZE_KZ, /* 4529 */ IC_EVEX_OPSIZE_KZ, /* 4530 */ IC_EVEX_OPSIZE_KZ, /* 4531 */ IC_EVEX_OPSIZE_KZ, /* 4532 */ IC_EVEX_OPSIZE_KZ, /* 4533 */ IC_EVEX_OPSIZE_KZ, /* 4534 */ IC_EVEX_OPSIZE_KZ, /* 4535 */ IC_EVEX_W_OPSIZE_KZ, /* 4536 */ IC_EVEX_W_OPSIZE_KZ, /* 4537 */ IC_EVEX_W_OPSIZE_KZ, /* 4538 */ IC_EVEX_W_OPSIZE_KZ, /* 4539 */ IC_EVEX_W_OPSIZE_KZ, /* 4540 */ IC_EVEX_W_OPSIZE_KZ, /* 4541 */ IC_EVEX_W_OPSIZE_KZ, /* 4542 */ IC_EVEX_W_OPSIZE_KZ, /* 4543 */ IC_EVEX_KZ, /* 4544 */ IC_EVEX_KZ, /* 4545 */ IC_EVEX_XS_KZ, /* 4546 */ IC_EVEX_XS_KZ, /* 4547 */ IC_EVEX_XD_KZ, /* 4548 */ IC_EVEX_XD_KZ, /* 4549 */ IC_EVEX_XD_KZ, /* 4550 */ IC_EVEX_XD_KZ, /* 4551 */ IC_EVEX_W_KZ, /* 4552 */ IC_EVEX_W_KZ, /* 4553 */ IC_EVEX_W_XS_KZ, /* 4554 */ IC_EVEX_W_XS_KZ, /* 4555 */ IC_EVEX_W_XD_KZ, /* 4556 */ IC_EVEX_W_XD_KZ, /* 4557 */ IC_EVEX_W_XD_KZ, /* 4558 */ IC_EVEX_W_XD_KZ, /* 4559 */ IC_EVEX_OPSIZE_KZ, /* 4560 */ IC_EVEX_OPSIZE_KZ, /* 4561 */ IC_EVEX_OPSIZE_KZ, /* 4562 */ IC_EVEX_OPSIZE_KZ, /* 4563 */ IC_EVEX_OPSIZE_KZ, /* 4564 */ IC_EVEX_OPSIZE_KZ, /* 4565 */ IC_EVEX_OPSIZE_KZ, /* 4566 */ IC_EVEX_OPSIZE_KZ, /* 4567 */ IC_EVEX_W_OPSIZE_KZ, /* 4568 */ IC_EVEX_W_OPSIZE_KZ, /* 4569 */ IC_EVEX_W_OPSIZE_KZ, /* 4570 */ IC_EVEX_W_OPSIZE_KZ, /* 4571 */ IC_EVEX_W_OPSIZE_KZ, /* 4572 */ IC_EVEX_W_OPSIZE_KZ, /* 4573 */ IC_EVEX_W_OPSIZE_KZ, /* 4574 */ IC_EVEX_W_OPSIZE_KZ, /* 4575 */ IC_EVEX_KZ, /* 4576 */ IC_EVEX_KZ, /* 4577 */ IC_EVEX_XS_KZ, /* 4578 */ IC_EVEX_XS_KZ, /* 4579 */ IC_EVEX_XD_KZ, /* 4580 */ IC_EVEX_XD_KZ, /* 4581 */ IC_EVEX_XD_KZ, /* 4582 */ IC_EVEX_XD_KZ, /* 4583 */ IC_EVEX_W_KZ, /* 4584 */ IC_EVEX_W_KZ, /* 4585 */ IC_EVEX_W_XS_KZ, /* 4586 */ IC_EVEX_W_XS_KZ, /* 4587 */ IC_EVEX_W_XD_KZ, /* 4588 */ IC_EVEX_W_XD_KZ, /* 4589 */ IC_EVEX_W_XD_KZ, /* 4590 */ IC_EVEX_W_XD_KZ, /* 4591 */ IC_EVEX_OPSIZE_KZ, /* 4592 */ IC_EVEX_OPSIZE_KZ, /* 4593 */ IC_EVEX_OPSIZE_KZ, /* 4594 */ IC_EVEX_OPSIZE_KZ, /* 4595 */ IC_EVEX_OPSIZE_KZ, /* 4596 */ IC_EVEX_OPSIZE_KZ, /* 4597 */ IC_EVEX_OPSIZE_KZ, /* 4598 */ IC_EVEX_OPSIZE_KZ, /* 4599 */ IC_EVEX_W_OPSIZE_KZ, /* 4600 */ IC_EVEX_W_OPSIZE_KZ, /* 4601 */ IC_EVEX_W_OPSIZE_KZ, /* 4602 */ IC_EVEX_W_OPSIZE_KZ, /* 4603 */ IC_EVEX_W_OPSIZE_KZ, /* 4604 */ IC_EVEX_W_OPSIZE_KZ, /* 4605 */ IC_EVEX_W_OPSIZE_KZ, /* 4606 */ IC_EVEX_W_OPSIZE_KZ, /* 4607 */ IC, /* 4608 */ IC_64BIT, /* 4609 */ IC_XS, /* 4610 */ IC_64BIT_XS, /* 4611 */ IC_XD, /* 4612 */ IC_64BIT_XD, /* 4613 */ IC_XS, /* 4614 */ IC_64BIT_XS, /* 4615 */ IC, /* 4616 */ IC_64BIT_REXW, /* 4617 */ IC_XS, /* 4618 */ IC_64BIT_REXW_XS, /* 4619 */ IC_XD, /* 4620 */ IC_64BIT_REXW_XD, /* 4621 */ IC_XS, /* 4622 */ IC_64BIT_REXW_XS, /* 4623 */ IC_OPSIZE, /* 4624 */ IC_64BIT_OPSIZE, /* 4625 */ IC_XS_OPSIZE, /* 4626 */ IC_64BIT_XS_OPSIZE, /* 4627 */ IC_XD_OPSIZE, /* 4628 */ IC_64BIT_XD_OPSIZE, /* 4629 */ IC_XS_OPSIZE, /* 4630 */ IC_64BIT_XD_OPSIZE, /* 4631 */ IC_OPSIZE, /* 4632 */ IC_64BIT_REXW_OPSIZE, /* 4633 */ IC_XS_OPSIZE, /* 4634 */ IC_64BIT_REXW_XS, /* 4635 */ IC_XD_OPSIZE, /* 4636 */ IC_64BIT_REXW_XD, /* 4637 */ IC_XS_OPSIZE, /* 4638 */ IC_64BIT_REXW_XS, /* 4639 */ IC_ADSIZE, /* 4640 */ IC_64BIT_ADSIZE, /* 4641 */ IC_XS_ADSIZE, /* 4642 */ IC_64BIT_XS_ADSIZE, /* 4643 */ IC_XD_ADSIZE, /* 4644 */ IC_64BIT_XD_ADSIZE, /* 4645 */ IC_XS_ADSIZE, /* 4646 */ IC_64BIT_XD_ADSIZE, /* 4647 */ IC_ADSIZE, /* 4648 */ IC_64BIT_REXW_ADSIZE, /* 4649 */ IC_XS_ADSIZE, /* 4650 */ IC_64BIT_REXW_XS, /* 4651 */ IC_XD_ADSIZE, /* 4652 */ IC_64BIT_REXW_XD, /* 4653 */ IC_XS_ADSIZE, /* 4654 */ IC_64BIT_REXW_XS, /* 4655 */ IC_OPSIZE_ADSIZE, /* 4656 */ IC_64BIT_OPSIZE_ADSIZE, /* 4657 */ IC_XS_OPSIZE, /* 4658 */ IC_64BIT_XS_OPSIZE, /* 4659 */ IC_XD_OPSIZE, /* 4660 */ IC_64BIT_XD_OPSIZE, /* 4661 */ IC_XS_OPSIZE, /* 4662 */ IC_64BIT_XD_OPSIZE, /* 4663 */ IC_OPSIZE_ADSIZE, /* 4664 */ IC_64BIT_REXW_OPSIZE, /* 4665 */ IC_XS_OPSIZE, /* 4666 */ IC_64BIT_REXW_XS, /* 4667 */ IC_XD_OPSIZE, /* 4668 */ IC_64BIT_REXW_XD, /* 4669 */ IC_XS_OPSIZE, /* 4670 */ IC_64BIT_REXW_XS, /* 4671 */ IC_VEX, /* 4672 */ IC_VEX, /* 4673 */ IC_VEX_XS, /* 4674 */ IC_VEX_XS, /* 4675 */ IC_VEX_XD, /* 4676 */ IC_VEX_XD, /* 4677 */ IC_VEX_XD, /* 4678 */ IC_VEX_XD, /* 4679 */ IC_VEX_W, /* 4680 */ IC_VEX_W, /* 4681 */ IC_VEX_W_XS, /* 4682 */ IC_VEX_W_XS, /* 4683 */ IC_VEX_W_XD, /* 4684 */ IC_VEX_W_XD, /* 4685 */ IC_VEX_W_XD, /* 4686 */ IC_VEX_W_XD, /* 4687 */ IC_VEX_OPSIZE, /* 4688 */ IC_VEX_OPSIZE, /* 4689 */ IC_VEX_OPSIZE, /* 4690 */ IC_VEX_OPSIZE, /* 4691 */ IC_VEX_OPSIZE, /* 4692 */ IC_VEX_OPSIZE, /* 4693 */ IC_VEX_OPSIZE, /* 4694 */ IC_VEX_OPSIZE, /* 4695 */ IC_VEX_W_OPSIZE, /* 4696 */ IC_VEX_W_OPSIZE, /* 4697 */ IC_VEX_W_OPSIZE, /* 4698 */ IC_VEX_W_OPSIZE, /* 4699 */ IC_VEX_W_OPSIZE, /* 4700 */ IC_VEX_W_OPSIZE, /* 4701 */ IC_VEX_W_OPSIZE, /* 4702 */ IC_VEX_W_OPSIZE, /* 4703 */ IC_VEX, /* 4704 */ IC_VEX, /* 4705 */ IC_VEX_XS, /* 4706 */ IC_VEX_XS, /* 4707 */ IC_VEX_XD, /* 4708 */ IC_VEX_XD, /* 4709 */ IC_VEX_XD, /* 4710 */ IC_VEX_XD, /* 4711 */ IC_VEX_W, /* 4712 */ IC_VEX_W, /* 4713 */ IC_VEX_W_XS, /* 4714 */ IC_VEX_W_XS, /* 4715 */ IC_VEX_W_XD, /* 4716 */ IC_VEX_W_XD, /* 4717 */ IC_VEX_W_XD, /* 4718 */ IC_VEX_W_XD, /* 4719 */ IC_VEX_OPSIZE, /* 4720 */ IC_VEX_OPSIZE, /* 4721 */ IC_VEX_OPSIZE, /* 4722 */ IC_VEX_OPSIZE, /* 4723 */ IC_VEX_OPSIZE, /* 4724 */ IC_VEX_OPSIZE, /* 4725 */ IC_VEX_OPSIZE, /* 4726 */ IC_VEX_OPSIZE, /* 4727 */ IC_VEX_W_OPSIZE, /* 4728 */ IC_VEX_W_OPSIZE, /* 4729 */ IC_VEX_W_OPSIZE, /* 4730 */ IC_VEX_W_OPSIZE, /* 4731 */ IC_VEX_W_OPSIZE, /* 4732 */ IC_VEX_W_OPSIZE, /* 4733 */ IC_VEX_W_OPSIZE, /* 4734 */ IC_VEX_W_OPSIZE, /* 4735 */ IC_VEX_L, /* 4736 */ IC_VEX_L, /* 4737 */ IC_VEX_L_XS, /* 4738 */ IC_VEX_L_XS, /* 4739 */ IC_VEX_L_XD, /* 4740 */ IC_VEX_L_XD, /* 4741 */ IC_VEX_L_XD, /* 4742 */ IC_VEX_L_XD, /* 4743 */ IC_VEX_L_W, /* 4744 */ IC_VEX_L_W, /* 4745 */ IC_VEX_L_W_XS, /* 4746 */ IC_VEX_L_W_XS, /* 4747 */ IC_VEX_L_W_XD, /* 4748 */ IC_VEX_L_W_XD, /* 4749 */ IC_VEX_L_W_XD, /* 4750 */ IC_VEX_L_W_XD, /* 4751 */ IC_VEX_L_OPSIZE, /* 4752 */ IC_VEX_L_OPSIZE, /* 4753 */ IC_VEX_L_OPSIZE, /* 4754 */ IC_VEX_L_OPSIZE, /* 4755 */ IC_VEX_L_OPSIZE, /* 4756 */ IC_VEX_L_OPSIZE, /* 4757 */ IC_VEX_L_OPSIZE, /* 4758 */ IC_VEX_L_OPSIZE, /* 4759 */ IC_VEX_L_W_OPSIZE, /* 4760 */ IC_VEX_L_W_OPSIZE, /* 4761 */ IC_VEX_L_W_OPSIZE, /* 4762 */ IC_VEX_L_W_OPSIZE, /* 4763 */ IC_VEX_L_W_OPSIZE, /* 4764 */ IC_VEX_L_W_OPSIZE, /* 4765 */ IC_VEX_L_W_OPSIZE, /* 4766 */ IC_VEX_L_W_OPSIZE, /* 4767 */ IC_VEX_L, /* 4768 */ IC_VEX_L, /* 4769 */ IC_VEX_L_XS, /* 4770 */ IC_VEX_L_XS, /* 4771 */ IC_VEX_L_XD, /* 4772 */ IC_VEX_L_XD, /* 4773 */ IC_VEX_L_XD, /* 4774 */ IC_VEX_L_XD, /* 4775 */ IC_VEX_L_W, /* 4776 */ IC_VEX_L_W, /* 4777 */ IC_VEX_L_W_XS, /* 4778 */ IC_VEX_L_W_XS, /* 4779 */ IC_VEX_L_W_XD, /* 4780 */ IC_VEX_L_W_XD, /* 4781 */ IC_VEX_L_W_XD, /* 4782 */ IC_VEX_L_W_XD, /* 4783 */ IC_VEX_L_OPSIZE, /* 4784 */ IC_VEX_L_OPSIZE, /* 4785 */ IC_VEX_L_OPSIZE, /* 4786 */ IC_VEX_L_OPSIZE, /* 4787 */ IC_VEX_L_OPSIZE, /* 4788 */ IC_VEX_L_OPSIZE, /* 4789 */ IC_VEX_L_OPSIZE, /* 4790 */ IC_VEX_L_OPSIZE, /* 4791 */ IC_VEX_L_W_OPSIZE, /* 4792 */ IC_VEX_L_W_OPSIZE, /* 4793 */ IC_VEX_L_W_OPSIZE, /* 4794 */ IC_VEX_L_W_OPSIZE, /* 4795 */ IC_VEX_L_W_OPSIZE, /* 4796 */ IC_VEX_L_W_OPSIZE, /* 4797 */ IC_VEX_L_W_OPSIZE, /* 4798 */ IC_VEX_L_W_OPSIZE, /* 4799 */ IC_VEX_L, /* 4800 */ IC_VEX_L, /* 4801 */ IC_VEX_L_XS, /* 4802 */ IC_VEX_L_XS, /* 4803 */ IC_VEX_L_XD, /* 4804 */ IC_VEX_L_XD, /* 4805 */ IC_VEX_L_XD, /* 4806 */ IC_VEX_L_XD, /* 4807 */ IC_VEX_L_W, /* 4808 */ IC_VEX_L_W, /* 4809 */ IC_VEX_L_W_XS, /* 4810 */ IC_VEX_L_W_XS, /* 4811 */ IC_VEX_L_W_XD, /* 4812 */ IC_VEX_L_W_XD, /* 4813 */ IC_VEX_L_W_XD, /* 4814 */ IC_VEX_L_W_XD, /* 4815 */ IC_VEX_L_OPSIZE, /* 4816 */ IC_VEX_L_OPSIZE, /* 4817 */ IC_VEX_L_OPSIZE, /* 4818 */ IC_VEX_L_OPSIZE, /* 4819 */ IC_VEX_L_OPSIZE, /* 4820 */ IC_VEX_L_OPSIZE, /* 4821 */ IC_VEX_L_OPSIZE, /* 4822 */ IC_VEX_L_OPSIZE, /* 4823 */ IC_VEX_L_W_OPSIZE, /* 4824 */ IC_VEX_L_W_OPSIZE, /* 4825 */ IC_VEX_L_W_OPSIZE, /* 4826 */ IC_VEX_L_W_OPSIZE, /* 4827 */ IC_VEX_L_W_OPSIZE, /* 4828 */ IC_VEX_L_W_OPSIZE, /* 4829 */ IC_VEX_L_W_OPSIZE, /* 4830 */ IC_VEX_L_W_OPSIZE, /* 4831 */ IC_VEX_L, /* 4832 */ IC_VEX_L, /* 4833 */ IC_VEX_L_XS, /* 4834 */ IC_VEX_L_XS, /* 4835 */ IC_VEX_L_XD, /* 4836 */ IC_VEX_L_XD, /* 4837 */ IC_VEX_L_XD, /* 4838 */ IC_VEX_L_XD, /* 4839 */ IC_VEX_L_W, /* 4840 */ IC_VEX_L_W, /* 4841 */ IC_VEX_L_W_XS, /* 4842 */ IC_VEX_L_W_XS, /* 4843 */ IC_VEX_L_W_XD, /* 4844 */ IC_VEX_L_W_XD, /* 4845 */ IC_VEX_L_W_XD, /* 4846 */ IC_VEX_L_W_XD, /* 4847 */ IC_VEX_L_OPSIZE, /* 4848 */ IC_VEX_L_OPSIZE, /* 4849 */ IC_VEX_L_OPSIZE, /* 4850 */ IC_VEX_L_OPSIZE, /* 4851 */ IC_VEX_L_OPSIZE, /* 4852 */ IC_VEX_L_OPSIZE, /* 4853 */ IC_VEX_L_OPSIZE, /* 4854 */ IC_VEX_L_OPSIZE, /* 4855 */ IC_VEX_L_W_OPSIZE, /* 4856 */ IC_VEX_L_W_OPSIZE, /* 4857 */ IC_VEX_L_W_OPSIZE, /* 4858 */ IC_VEX_L_W_OPSIZE, /* 4859 */ IC_VEX_L_W_OPSIZE, /* 4860 */ IC_VEX_L_W_OPSIZE, /* 4861 */ IC_VEX_L_W_OPSIZE, /* 4862 */ IC_VEX_L_W_OPSIZE, /* 4863 */ IC_EVEX_L_KZ, /* 4864 */ IC_EVEX_L_KZ, /* 4865 */ IC_EVEX_L_XS_KZ, /* 4866 */ IC_EVEX_L_XS_KZ, /* 4867 */ IC_EVEX_L_XD_KZ, /* 4868 */ IC_EVEX_L_XD_KZ, /* 4869 */ IC_EVEX_L_XD_KZ, /* 4870 */ IC_EVEX_L_XD_KZ, /* 4871 */ IC_EVEX_L_W_KZ, /* 4872 */ IC_EVEX_L_W_KZ, /* 4873 */ IC_EVEX_L_W_XS_KZ, /* 4874 */ IC_EVEX_L_W_XS_KZ, /* 4875 */ IC_EVEX_L_W_XD_KZ, /* 4876 */ IC_EVEX_L_W_XD_KZ, /* 4877 */ IC_EVEX_L_W_XD_KZ, /* 4878 */ IC_EVEX_L_W_XD_KZ, /* 4879 */ IC_EVEX_L_OPSIZE_KZ, /* 4880 */ IC_EVEX_L_OPSIZE_KZ, /* 4881 */ IC_EVEX_L_OPSIZE_KZ, /* 4882 */ IC_EVEX_L_OPSIZE_KZ, /* 4883 */ IC_EVEX_L_OPSIZE_KZ, /* 4884 */ IC_EVEX_L_OPSIZE_KZ, /* 4885 */ IC_EVEX_L_OPSIZE_KZ, /* 4886 */ IC_EVEX_L_OPSIZE_KZ, /* 4887 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4888 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4889 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4890 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4891 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4892 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4893 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4894 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4895 */ IC_EVEX_L_KZ, /* 4896 */ IC_EVEX_L_KZ, /* 4897 */ IC_EVEX_L_XS_KZ, /* 4898 */ IC_EVEX_L_XS_KZ, /* 4899 */ IC_EVEX_L_XD_KZ, /* 4900 */ IC_EVEX_L_XD_KZ, /* 4901 */ IC_EVEX_L_XD_KZ, /* 4902 */ IC_EVEX_L_XD_KZ, /* 4903 */ IC_EVEX_L_W_KZ, /* 4904 */ IC_EVEX_L_W_KZ, /* 4905 */ IC_EVEX_L_W_XS_KZ, /* 4906 */ IC_EVEX_L_W_XS_KZ, /* 4907 */ IC_EVEX_L_W_XD_KZ, /* 4908 */ IC_EVEX_L_W_XD_KZ, /* 4909 */ IC_EVEX_L_W_XD_KZ, /* 4910 */ IC_EVEX_L_W_XD_KZ, /* 4911 */ IC_EVEX_L_OPSIZE_KZ, /* 4912 */ IC_EVEX_L_OPSIZE_KZ, /* 4913 */ IC_EVEX_L_OPSIZE_KZ, /* 4914 */ IC_EVEX_L_OPSIZE_KZ, /* 4915 */ IC_EVEX_L_OPSIZE_KZ, /* 4916 */ IC_EVEX_L_OPSIZE_KZ, /* 4917 */ IC_EVEX_L_OPSIZE_KZ, /* 4918 */ IC_EVEX_L_OPSIZE_KZ, /* 4919 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4920 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4921 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4922 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4923 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4924 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4925 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4926 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4927 */ IC_EVEX_L_KZ, /* 4928 */ IC_EVEX_L_KZ, /* 4929 */ IC_EVEX_L_XS_KZ, /* 4930 */ IC_EVEX_L_XS_KZ, /* 4931 */ IC_EVEX_L_XD_KZ, /* 4932 */ IC_EVEX_L_XD_KZ, /* 4933 */ IC_EVEX_L_XD_KZ, /* 4934 */ IC_EVEX_L_XD_KZ, /* 4935 */ IC_EVEX_L_W_KZ, /* 4936 */ IC_EVEX_L_W_KZ, /* 4937 */ IC_EVEX_L_W_XS_KZ, /* 4938 */ IC_EVEX_L_W_XS_KZ, /* 4939 */ IC_EVEX_L_W_XD_KZ, /* 4940 */ IC_EVEX_L_W_XD_KZ, /* 4941 */ IC_EVEX_L_W_XD_KZ, /* 4942 */ IC_EVEX_L_W_XD_KZ, /* 4943 */ IC_EVEX_L_OPSIZE_KZ, /* 4944 */ IC_EVEX_L_OPSIZE_KZ, /* 4945 */ IC_EVEX_L_OPSIZE_KZ, /* 4946 */ IC_EVEX_L_OPSIZE_KZ, /* 4947 */ IC_EVEX_L_OPSIZE_KZ, /* 4948 */ IC_EVEX_L_OPSIZE_KZ, /* 4949 */ IC_EVEX_L_OPSIZE_KZ, /* 4950 */ IC_EVEX_L_OPSIZE_KZ, /* 4951 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4952 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4953 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4954 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4955 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4956 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4957 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4958 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4959 */ IC_EVEX_L_KZ, /* 4960 */ IC_EVEX_L_KZ, /* 4961 */ IC_EVEX_L_XS_KZ, /* 4962 */ IC_EVEX_L_XS_KZ, /* 4963 */ IC_EVEX_L_XD_KZ, /* 4964 */ IC_EVEX_L_XD_KZ, /* 4965 */ IC_EVEX_L_XD_KZ, /* 4966 */ IC_EVEX_L_XD_KZ, /* 4967 */ IC_EVEX_L_W_KZ, /* 4968 */ IC_EVEX_L_W_KZ, /* 4969 */ IC_EVEX_L_W_XS_KZ, /* 4970 */ IC_EVEX_L_W_XS_KZ, /* 4971 */ IC_EVEX_L_W_XD_KZ, /* 4972 */ IC_EVEX_L_W_XD_KZ, /* 4973 */ IC_EVEX_L_W_XD_KZ, /* 4974 */ IC_EVEX_L_W_XD_KZ, /* 4975 */ IC_EVEX_L_OPSIZE_KZ, /* 4976 */ IC_EVEX_L_OPSIZE_KZ, /* 4977 */ IC_EVEX_L_OPSIZE_KZ, /* 4978 */ IC_EVEX_L_OPSIZE_KZ, /* 4979 */ IC_EVEX_L_OPSIZE_KZ, /* 4980 */ IC_EVEX_L_OPSIZE_KZ, /* 4981 */ IC_EVEX_L_OPSIZE_KZ, /* 4982 */ IC_EVEX_L_OPSIZE_KZ, /* 4983 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4984 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4985 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4986 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4987 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4988 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4989 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4990 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4991 */ IC_EVEX_L_KZ, /* 4992 */ IC_EVEX_L_KZ, /* 4993 */ IC_EVEX_L_XS_KZ, /* 4994 */ IC_EVEX_L_XS_KZ, /* 4995 */ IC_EVEX_L_XD_KZ, /* 4996 */ IC_EVEX_L_XD_KZ, /* 4997 */ IC_EVEX_L_XD_KZ, /* 4998 */ IC_EVEX_L_XD_KZ, /* 4999 */ IC_EVEX_L_W_KZ, /* 5000 */ IC_EVEX_L_W_KZ, /* 5001 */ IC_EVEX_L_W_XS_KZ, /* 5002 */ IC_EVEX_L_W_XS_KZ, /* 5003 */ IC_EVEX_L_W_XD_KZ, /* 5004 */ IC_EVEX_L_W_XD_KZ, /* 5005 */ IC_EVEX_L_W_XD_KZ, /* 5006 */ IC_EVEX_L_W_XD_KZ, /* 5007 */ IC_EVEX_L_OPSIZE_KZ, /* 5008 */ IC_EVEX_L_OPSIZE_KZ, /* 5009 */ IC_EVEX_L_OPSIZE_KZ, /* 5010 */ IC_EVEX_L_OPSIZE_KZ, /* 5011 */ IC_EVEX_L_OPSIZE_KZ, /* 5012 */ IC_EVEX_L_OPSIZE_KZ, /* 5013 */ IC_EVEX_L_OPSIZE_KZ, /* 5014 */ IC_EVEX_L_OPSIZE_KZ, /* 5015 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5016 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5017 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5018 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5019 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5020 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5021 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5022 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5023 */ IC_EVEX_L_KZ, /* 5024 */ IC_EVEX_L_KZ, /* 5025 */ IC_EVEX_L_XS_KZ, /* 5026 */ IC_EVEX_L_XS_KZ, /* 5027 */ IC_EVEX_L_XD_KZ, /* 5028 */ IC_EVEX_L_XD_KZ, /* 5029 */ IC_EVEX_L_XD_KZ, /* 5030 */ IC_EVEX_L_XD_KZ, /* 5031 */ IC_EVEX_L_W_KZ, /* 5032 */ IC_EVEX_L_W_KZ, /* 5033 */ IC_EVEX_L_W_XS_KZ, /* 5034 */ IC_EVEX_L_W_XS_KZ, /* 5035 */ IC_EVEX_L_W_XD_KZ, /* 5036 */ IC_EVEX_L_W_XD_KZ, /* 5037 */ IC_EVEX_L_W_XD_KZ, /* 5038 */ IC_EVEX_L_W_XD_KZ, /* 5039 */ IC_EVEX_L_OPSIZE_KZ, /* 5040 */ IC_EVEX_L_OPSIZE_KZ, /* 5041 */ IC_EVEX_L_OPSIZE_KZ, /* 5042 */ IC_EVEX_L_OPSIZE_KZ, /* 5043 */ IC_EVEX_L_OPSIZE_KZ, /* 5044 */ IC_EVEX_L_OPSIZE_KZ, /* 5045 */ IC_EVEX_L_OPSIZE_KZ, /* 5046 */ IC_EVEX_L_OPSIZE_KZ, /* 5047 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5048 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5049 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5050 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5051 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5052 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5053 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5054 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5055 */ IC_EVEX_L_KZ, /* 5056 */ IC_EVEX_L_KZ, /* 5057 */ IC_EVEX_L_XS_KZ, /* 5058 */ IC_EVEX_L_XS_KZ, /* 5059 */ IC_EVEX_L_XD_KZ, /* 5060 */ IC_EVEX_L_XD_KZ, /* 5061 */ IC_EVEX_L_XD_KZ, /* 5062 */ IC_EVEX_L_XD_KZ, /* 5063 */ IC_EVEX_L_W_KZ, /* 5064 */ IC_EVEX_L_W_KZ, /* 5065 */ IC_EVEX_L_W_XS_KZ, /* 5066 */ IC_EVEX_L_W_XS_KZ, /* 5067 */ IC_EVEX_L_W_XD_KZ, /* 5068 */ IC_EVEX_L_W_XD_KZ, /* 5069 */ IC_EVEX_L_W_XD_KZ, /* 5070 */ IC_EVEX_L_W_XD_KZ, /* 5071 */ IC_EVEX_L_OPSIZE_KZ, /* 5072 */ IC_EVEX_L_OPSIZE_KZ, /* 5073 */ IC_EVEX_L_OPSIZE_KZ, /* 5074 */ IC_EVEX_L_OPSIZE_KZ, /* 5075 */ IC_EVEX_L_OPSIZE_KZ, /* 5076 */ IC_EVEX_L_OPSIZE_KZ, /* 5077 */ IC_EVEX_L_OPSIZE_KZ, /* 5078 */ IC_EVEX_L_OPSIZE_KZ, /* 5079 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5080 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5081 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5082 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5083 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5084 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5085 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5086 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5087 */ IC_EVEX_L_KZ, /* 5088 */ IC_EVEX_L_KZ, /* 5089 */ IC_EVEX_L_XS_KZ, /* 5090 */ IC_EVEX_L_XS_KZ, /* 5091 */ IC_EVEX_L_XD_KZ, /* 5092 */ IC_EVEX_L_XD_KZ, /* 5093 */ IC_EVEX_L_XD_KZ, /* 5094 */ IC_EVEX_L_XD_KZ, /* 5095 */ IC_EVEX_L_W_KZ, /* 5096 */ IC_EVEX_L_W_KZ, /* 5097 */ IC_EVEX_L_W_XS_KZ, /* 5098 */ IC_EVEX_L_W_XS_KZ, /* 5099 */ IC_EVEX_L_W_XD_KZ, /* 5100 */ IC_EVEX_L_W_XD_KZ, /* 5101 */ IC_EVEX_L_W_XD_KZ, /* 5102 */ IC_EVEX_L_W_XD_KZ, /* 5103 */ IC_EVEX_L_OPSIZE_KZ, /* 5104 */ IC_EVEX_L_OPSIZE_KZ, /* 5105 */ IC_EVEX_L_OPSIZE_KZ, /* 5106 */ IC_EVEX_L_OPSIZE_KZ, /* 5107 */ IC_EVEX_L_OPSIZE_KZ, /* 5108 */ IC_EVEX_L_OPSIZE_KZ, /* 5109 */ IC_EVEX_L_OPSIZE_KZ, /* 5110 */ IC_EVEX_L_OPSIZE_KZ, /* 5111 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5112 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5113 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5114 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5115 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5116 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5117 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5118 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5119 */ IC, /* 5120 */ IC_64BIT, /* 5121 */ IC_XS, /* 5122 */ IC_64BIT_XS, /* 5123 */ IC_XD, /* 5124 */ IC_64BIT_XD, /* 5125 */ IC_XS, /* 5126 */ IC_64BIT_XS, /* 5127 */ IC, /* 5128 */ IC_64BIT_REXW, /* 5129 */ IC_XS, /* 5130 */ IC_64BIT_REXW_XS, /* 5131 */ IC_XD, /* 5132 */ IC_64BIT_REXW_XD, /* 5133 */ IC_XS, /* 5134 */ IC_64BIT_REXW_XS, /* 5135 */ IC_OPSIZE, /* 5136 */ IC_64BIT_OPSIZE, /* 5137 */ IC_XS_OPSIZE, /* 5138 */ IC_64BIT_XS_OPSIZE, /* 5139 */ IC_XD_OPSIZE, /* 5140 */ IC_64BIT_XD_OPSIZE, /* 5141 */ IC_XS_OPSIZE, /* 5142 */ IC_64BIT_XD_OPSIZE, /* 5143 */ IC_OPSIZE, /* 5144 */ IC_64BIT_REXW_OPSIZE, /* 5145 */ IC_XS_OPSIZE, /* 5146 */ IC_64BIT_REXW_XS, /* 5147 */ IC_XD_OPSIZE, /* 5148 */ IC_64BIT_REXW_XD, /* 5149 */ IC_XS_OPSIZE, /* 5150 */ IC_64BIT_REXW_XS, /* 5151 */ IC_ADSIZE, /* 5152 */ IC_64BIT_ADSIZE, /* 5153 */ IC_XS_ADSIZE, /* 5154 */ IC_64BIT_XS_ADSIZE, /* 5155 */ IC_XD_ADSIZE, /* 5156 */ IC_64BIT_XD_ADSIZE, /* 5157 */ IC_XS_ADSIZE, /* 5158 */ IC_64BIT_XD_ADSIZE, /* 5159 */ IC_ADSIZE, /* 5160 */ IC_64BIT_REXW_ADSIZE, /* 5161 */ IC_XS_ADSIZE, /* 5162 */ IC_64BIT_REXW_XS, /* 5163 */ IC_XD_ADSIZE, /* 5164 */ IC_64BIT_REXW_XD, /* 5165 */ IC_XS_ADSIZE, /* 5166 */ IC_64BIT_REXW_XS, /* 5167 */ IC_OPSIZE_ADSIZE, /* 5168 */ IC_64BIT_OPSIZE_ADSIZE, /* 5169 */ IC_XS_OPSIZE, /* 5170 */ IC_64BIT_XS_OPSIZE, /* 5171 */ IC_XD_OPSIZE, /* 5172 */ IC_64BIT_XD_OPSIZE, /* 5173 */ IC_XS_OPSIZE, /* 5174 */ IC_64BIT_XD_OPSIZE, /* 5175 */ IC_OPSIZE_ADSIZE, /* 5176 */ IC_64BIT_REXW_OPSIZE, /* 5177 */ IC_XS_OPSIZE, /* 5178 */ IC_64BIT_REXW_XS, /* 5179 */ IC_XD_OPSIZE, /* 5180 */ IC_64BIT_REXW_XD, /* 5181 */ IC_XS_OPSIZE, /* 5182 */ IC_64BIT_REXW_XS, /* 5183 */ IC_VEX, /* 5184 */ IC_VEX, /* 5185 */ IC_VEX_XS, /* 5186 */ IC_VEX_XS, /* 5187 */ IC_VEX_XD, /* 5188 */ IC_VEX_XD, /* 5189 */ IC_VEX_XD, /* 5190 */ IC_VEX_XD, /* 5191 */ IC_VEX_W, /* 5192 */ IC_VEX_W, /* 5193 */ IC_VEX_W_XS, /* 5194 */ IC_VEX_W_XS, /* 5195 */ IC_VEX_W_XD, /* 5196 */ IC_VEX_W_XD, /* 5197 */ IC_VEX_W_XD, /* 5198 */ IC_VEX_W_XD, /* 5199 */ IC_VEX_OPSIZE, /* 5200 */ IC_VEX_OPSIZE, /* 5201 */ IC_VEX_OPSIZE, /* 5202 */ IC_VEX_OPSIZE, /* 5203 */ IC_VEX_OPSIZE, /* 5204 */ IC_VEX_OPSIZE, /* 5205 */ IC_VEX_OPSIZE, /* 5206 */ IC_VEX_OPSIZE, /* 5207 */ IC_VEX_W_OPSIZE, /* 5208 */ IC_VEX_W_OPSIZE, /* 5209 */ IC_VEX_W_OPSIZE, /* 5210 */ IC_VEX_W_OPSIZE, /* 5211 */ IC_VEX_W_OPSIZE, /* 5212 */ IC_VEX_W_OPSIZE, /* 5213 */ IC_VEX_W_OPSIZE, /* 5214 */ IC_VEX_W_OPSIZE, /* 5215 */ IC_VEX, /* 5216 */ IC_VEX, /* 5217 */ IC_VEX_XS, /* 5218 */ IC_VEX_XS, /* 5219 */ IC_VEX_XD, /* 5220 */ IC_VEX_XD, /* 5221 */ IC_VEX_XD, /* 5222 */ IC_VEX_XD, /* 5223 */ IC_VEX_W, /* 5224 */ IC_VEX_W, /* 5225 */ IC_VEX_W_XS, /* 5226 */ IC_VEX_W_XS, /* 5227 */ IC_VEX_W_XD, /* 5228 */ IC_VEX_W_XD, /* 5229 */ IC_VEX_W_XD, /* 5230 */ IC_VEX_W_XD, /* 5231 */ IC_VEX_OPSIZE, /* 5232 */ IC_VEX_OPSIZE, /* 5233 */ IC_VEX_OPSIZE, /* 5234 */ IC_VEX_OPSIZE, /* 5235 */ IC_VEX_OPSIZE, /* 5236 */ IC_VEX_OPSIZE, /* 5237 */ IC_VEX_OPSIZE, /* 5238 */ IC_VEX_OPSIZE, /* 5239 */ IC_VEX_W_OPSIZE, /* 5240 */ IC_VEX_W_OPSIZE, /* 5241 */ IC_VEX_W_OPSIZE, /* 5242 */ IC_VEX_W_OPSIZE, /* 5243 */ IC_VEX_W_OPSIZE, /* 5244 */ IC_VEX_W_OPSIZE, /* 5245 */ IC_VEX_W_OPSIZE, /* 5246 */ IC_VEX_W_OPSIZE, /* 5247 */ IC_VEX_L, /* 5248 */ IC_VEX_L, /* 5249 */ IC_VEX_L_XS, /* 5250 */ IC_VEX_L_XS, /* 5251 */ IC_VEX_L_XD, /* 5252 */ IC_VEX_L_XD, /* 5253 */ IC_VEX_L_XD, /* 5254 */ IC_VEX_L_XD, /* 5255 */ IC_VEX_L_W, /* 5256 */ IC_VEX_L_W, /* 5257 */ IC_VEX_L_W_XS, /* 5258 */ IC_VEX_L_W_XS, /* 5259 */ IC_VEX_L_W_XD, /* 5260 */ IC_VEX_L_W_XD, /* 5261 */ IC_VEX_L_W_XD, /* 5262 */ IC_VEX_L_W_XD, /* 5263 */ IC_VEX_L_OPSIZE, /* 5264 */ IC_VEX_L_OPSIZE, /* 5265 */ IC_VEX_L_OPSIZE, /* 5266 */ IC_VEX_L_OPSIZE, /* 5267 */ IC_VEX_L_OPSIZE, /* 5268 */ IC_VEX_L_OPSIZE, /* 5269 */ IC_VEX_L_OPSIZE, /* 5270 */ IC_VEX_L_OPSIZE, /* 5271 */ IC_VEX_L_W_OPSIZE, /* 5272 */ IC_VEX_L_W_OPSIZE, /* 5273 */ IC_VEX_L_W_OPSIZE, /* 5274 */ IC_VEX_L_W_OPSIZE, /* 5275 */ IC_VEX_L_W_OPSIZE, /* 5276 */ IC_VEX_L_W_OPSIZE, /* 5277 */ IC_VEX_L_W_OPSIZE, /* 5278 */ IC_VEX_L_W_OPSIZE, /* 5279 */ IC_VEX_L, /* 5280 */ IC_VEX_L, /* 5281 */ IC_VEX_L_XS, /* 5282 */ IC_VEX_L_XS, /* 5283 */ IC_VEX_L_XD, /* 5284 */ IC_VEX_L_XD, /* 5285 */ IC_VEX_L_XD, /* 5286 */ IC_VEX_L_XD, /* 5287 */ IC_VEX_L_W, /* 5288 */ IC_VEX_L_W, /* 5289 */ IC_VEX_L_W_XS, /* 5290 */ IC_VEX_L_W_XS, /* 5291 */ IC_VEX_L_W_XD, /* 5292 */ IC_VEX_L_W_XD, /* 5293 */ IC_VEX_L_W_XD, /* 5294 */ IC_VEX_L_W_XD, /* 5295 */ IC_VEX_L_OPSIZE, /* 5296 */ IC_VEX_L_OPSIZE, /* 5297 */ IC_VEX_L_OPSIZE, /* 5298 */ IC_VEX_L_OPSIZE, /* 5299 */ IC_VEX_L_OPSIZE, /* 5300 */ IC_VEX_L_OPSIZE, /* 5301 */ IC_VEX_L_OPSIZE, /* 5302 */ IC_VEX_L_OPSIZE, /* 5303 */ IC_VEX_L_W_OPSIZE, /* 5304 */ IC_VEX_L_W_OPSIZE, /* 5305 */ IC_VEX_L_W_OPSIZE, /* 5306 */ IC_VEX_L_W_OPSIZE, /* 5307 */ IC_VEX_L_W_OPSIZE, /* 5308 */ IC_VEX_L_W_OPSIZE, /* 5309 */ IC_VEX_L_W_OPSIZE, /* 5310 */ IC_VEX_L_W_OPSIZE, /* 5311 */ IC_VEX_L, /* 5312 */ IC_VEX_L, /* 5313 */ IC_VEX_L_XS, /* 5314 */ IC_VEX_L_XS, /* 5315 */ IC_VEX_L_XD, /* 5316 */ IC_VEX_L_XD, /* 5317 */ IC_VEX_L_XD, /* 5318 */ IC_VEX_L_XD, /* 5319 */ IC_VEX_L_W, /* 5320 */ IC_VEX_L_W, /* 5321 */ IC_VEX_L_W_XS, /* 5322 */ IC_VEX_L_W_XS, /* 5323 */ IC_VEX_L_W_XD, /* 5324 */ IC_VEX_L_W_XD, /* 5325 */ IC_VEX_L_W_XD, /* 5326 */ IC_VEX_L_W_XD, /* 5327 */ IC_VEX_L_OPSIZE, /* 5328 */ IC_VEX_L_OPSIZE, /* 5329 */ IC_VEX_L_OPSIZE, /* 5330 */ IC_VEX_L_OPSIZE, /* 5331 */ IC_VEX_L_OPSIZE, /* 5332 */ IC_VEX_L_OPSIZE, /* 5333 */ IC_VEX_L_OPSIZE, /* 5334 */ IC_VEX_L_OPSIZE, /* 5335 */ IC_VEX_L_W_OPSIZE, /* 5336 */ IC_VEX_L_W_OPSIZE, /* 5337 */ IC_VEX_L_W_OPSIZE, /* 5338 */ IC_VEX_L_W_OPSIZE, /* 5339 */ IC_VEX_L_W_OPSIZE, /* 5340 */ IC_VEX_L_W_OPSIZE, /* 5341 */ IC_VEX_L_W_OPSIZE, /* 5342 */ IC_VEX_L_W_OPSIZE, /* 5343 */ IC_VEX_L, /* 5344 */ IC_VEX_L, /* 5345 */ IC_VEX_L_XS, /* 5346 */ IC_VEX_L_XS, /* 5347 */ IC_VEX_L_XD, /* 5348 */ IC_VEX_L_XD, /* 5349 */ IC_VEX_L_XD, /* 5350 */ IC_VEX_L_XD, /* 5351 */ IC_VEX_L_W, /* 5352 */ IC_VEX_L_W, /* 5353 */ IC_VEX_L_W_XS, /* 5354 */ IC_VEX_L_W_XS, /* 5355 */ IC_VEX_L_W_XD, /* 5356 */ IC_VEX_L_W_XD, /* 5357 */ IC_VEX_L_W_XD, /* 5358 */ IC_VEX_L_W_XD, /* 5359 */ IC_VEX_L_OPSIZE, /* 5360 */ IC_VEX_L_OPSIZE, /* 5361 */ IC_VEX_L_OPSIZE, /* 5362 */ IC_VEX_L_OPSIZE, /* 5363 */ IC_VEX_L_OPSIZE, /* 5364 */ IC_VEX_L_OPSIZE, /* 5365 */ IC_VEX_L_OPSIZE, /* 5366 */ IC_VEX_L_OPSIZE, /* 5367 */ IC_VEX_L_W_OPSIZE, /* 5368 */ IC_VEX_L_W_OPSIZE, /* 5369 */ IC_VEX_L_W_OPSIZE, /* 5370 */ IC_VEX_L_W_OPSIZE, /* 5371 */ IC_VEX_L_W_OPSIZE, /* 5372 */ IC_VEX_L_W_OPSIZE, /* 5373 */ IC_VEX_L_W_OPSIZE, /* 5374 */ IC_VEX_L_W_OPSIZE, /* 5375 */ IC_EVEX_L2_KZ, /* 5376 */ IC_EVEX_L2_KZ, /* 5377 */ IC_EVEX_L2_XS_KZ, /* 5378 */ IC_EVEX_L2_XS_KZ, /* 5379 */ IC_EVEX_L2_XD_KZ, /* 5380 */ IC_EVEX_L2_XD_KZ, /* 5381 */ IC_EVEX_L2_XD_KZ, /* 5382 */ IC_EVEX_L2_XD_KZ, /* 5383 */ IC_EVEX_L2_W_KZ, /* 5384 */ IC_EVEX_L2_W_KZ, /* 5385 */ IC_EVEX_L2_W_XS_KZ, /* 5386 */ IC_EVEX_L2_W_XS_KZ, /* 5387 */ IC_EVEX_L2_W_XD_KZ, /* 5388 */ IC_EVEX_L2_W_XD_KZ, /* 5389 */ IC_EVEX_L2_W_XD_KZ, /* 5390 */ IC_EVEX_L2_W_XD_KZ, /* 5391 */ IC_EVEX_L2_OPSIZE_KZ, /* 5392 */ IC_EVEX_L2_OPSIZE_KZ, /* 5393 */ IC_EVEX_L2_OPSIZE_KZ, /* 5394 */ IC_EVEX_L2_OPSIZE_KZ, /* 5395 */ IC_EVEX_L2_OPSIZE_KZ, /* 5396 */ IC_EVEX_L2_OPSIZE_KZ, /* 5397 */ IC_EVEX_L2_OPSIZE_KZ, /* 5398 */ IC_EVEX_L2_OPSIZE_KZ, /* 5399 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5400 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5401 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5402 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5403 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5404 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5405 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5406 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5407 */ IC_EVEX_L2_KZ, /* 5408 */ IC_EVEX_L2_KZ, /* 5409 */ IC_EVEX_L2_XS_KZ, /* 5410 */ IC_EVEX_L2_XS_KZ, /* 5411 */ IC_EVEX_L2_XD_KZ, /* 5412 */ IC_EVEX_L2_XD_KZ, /* 5413 */ IC_EVEX_L2_XD_KZ, /* 5414 */ IC_EVEX_L2_XD_KZ, /* 5415 */ IC_EVEX_L2_W_KZ, /* 5416 */ IC_EVEX_L2_W_KZ, /* 5417 */ IC_EVEX_L2_W_XS_KZ, /* 5418 */ IC_EVEX_L2_W_XS_KZ, /* 5419 */ IC_EVEX_L2_W_XD_KZ, /* 5420 */ IC_EVEX_L2_W_XD_KZ, /* 5421 */ IC_EVEX_L2_W_XD_KZ, /* 5422 */ IC_EVEX_L2_W_XD_KZ, /* 5423 */ IC_EVEX_L2_OPSIZE_KZ, /* 5424 */ IC_EVEX_L2_OPSIZE_KZ, /* 5425 */ IC_EVEX_L2_OPSIZE_KZ, /* 5426 */ IC_EVEX_L2_OPSIZE_KZ, /* 5427 */ IC_EVEX_L2_OPSIZE_KZ, /* 5428 */ IC_EVEX_L2_OPSIZE_KZ, /* 5429 */ IC_EVEX_L2_OPSIZE_KZ, /* 5430 */ IC_EVEX_L2_OPSIZE_KZ, /* 5431 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5432 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5433 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5434 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5435 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5436 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5437 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5438 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5439 */ IC_EVEX_L2_KZ, /* 5440 */ IC_EVEX_L2_KZ, /* 5441 */ IC_EVEX_L2_XS_KZ, /* 5442 */ IC_EVEX_L2_XS_KZ, /* 5443 */ IC_EVEX_L2_XD_KZ, /* 5444 */ IC_EVEX_L2_XD_KZ, /* 5445 */ IC_EVEX_L2_XD_KZ, /* 5446 */ IC_EVEX_L2_XD_KZ, /* 5447 */ IC_EVEX_L2_W_KZ, /* 5448 */ IC_EVEX_L2_W_KZ, /* 5449 */ IC_EVEX_L2_W_XS_KZ, /* 5450 */ IC_EVEX_L2_W_XS_KZ, /* 5451 */ IC_EVEX_L2_W_XD_KZ, /* 5452 */ IC_EVEX_L2_W_XD_KZ, /* 5453 */ IC_EVEX_L2_W_XD_KZ, /* 5454 */ IC_EVEX_L2_W_XD_KZ, /* 5455 */ IC_EVEX_L2_OPSIZE_KZ, /* 5456 */ IC_EVEX_L2_OPSIZE_KZ, /* 5457 */ IC_EVEX_L2_OPSIZE_KZ, /* 5458 */ IC_EVEX_L2_OPSIZE_KZ, /* 5459 */ IC_EVEX_L2_OPSIZE_KZ, /* 5460 */ IC_EVEX_L2_OPSIZE_KZ, /* 5461 */ IC_EVEX_L2_OPSIZE_KZ, /* 5462 */ IC_EVEX_L2_OPSIZE_KZ, /* 5463 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5464 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5465 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5466 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5467 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5468 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5469 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5470 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5471 */ IC_EVEX_L2_KZ, /* 5472 */ IC_EVEX_L2_KZ, /* 5473 */ IC_EVEX_L2_XS_KZ, /* 5474 */ IC_EVEX_L2_XS_KZ, /* 5475 */ IC_EVEX_L2_XD_KZ, /* 5476 */ IC_EVEX_L2_XD_KZ, /* 5477 */ IC_EVEX_L2_XD_KZ, /* 5478 */ IC_EVEX_L2_XD_KZ, /* 5479 */ IC_EVEX_L2_W_KZ, /* 5480 */ IC_EVEX_L2_W_KZ, /* 5481 */ IC_EVEX_L2_W_XS_KZ, /* 5482 */ IC_EVEX_L2_W_XS_KZ, /* 5483 */ IC_EVEX_L2_W_XD_KZ, /* 5484 */ IC_EVEX_L2_W_XD_KZ, /* 5485 */ IC_EVEX_L2_W_XD_KZ, /* 5486 */ IC_EVEX_L2_W_XD_KZ, /* 5487 */ IC_EVEX_L2_OPSIZE_KZ, /* 5488 */ IC_EVEX_L2_OPSIZE_KZ, /* 5489 */ IC_EVEX_L2_OPSIZE_KZ, /* 5490 */ IC_EVEX_L2_OPSIZE_KZ, /* 5491 */ IC_EVEX_L2_OPSIZE_KZ, /* 5492 */ IC_EVEX_L2_OPSIZE_KZ, /* 5493 */ IC_EVEX_L2_OPSIZE_KZ, /* 5494 */ IC_EVEX_L2_OPSIZE_KZ, /* 5495 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5496 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5497 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5498 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5499 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5500 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5501 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5502 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5503 */ IC_EVEX_L2_KZ, /* 5504 */ IC_EVEX_L2_KZ, /* 5505 */ IC_EVEX_L2_XS_KZ, /* 5506 */ IC_EVEX_L2_XS_KZ, /* 5507 */ IC_EVEX_L2_XD_KZ, /* 5508 */ IC_EVEX_L2_XD_KZ, /* 5509 */ IC_EVEX_L2_XD_KZ, /* 5510 */ IC_EVEX_L2_XD_KZ, /* 5511 */ IC_EVEX_L2_W_KZ, /* 5512 */ IC_EVEX_L2_W_KZ, /* 5513 */ IC_EVEX_L2_W_XS_KZ, /* 5514 */ IC_EVEX_L2_W_XS_KZ, /* 5515 */ IC_EVEX_L2_W_XD_KZ, /* 5516 */ IC_EVEX_L2_W_XD_KZ, /* 5517 */ IC_EVEX_L2_W_XD_KZ, /* 5518 */ IC_EVEX_L2_W_XD_KZ, /* 5519 */ IC_EVEX_L2_OPSIZE_KZ, /* 5520 */ IC_EVEX_L2_OPSIZE_KZ, /* 5521 */ IC_EVEX_L2_OPSIZE_KZ, /* 5522 */ IC_EVEX_L2_OPSIZE_KZ, /* 5523 */ IC_EVEX_L2_OPSIZE_KZ, /* 5524 */ IC_EVEX_L2_OPSIZE_KZ, /* 5525 */ IC_EVEX_L2_OPSIZE_KZ, /* 5526 */ IC_EVEX_L2_OPSIZE_KZ, /* 5527 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5528 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5529 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5530 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5531 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5532 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5533 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5534 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5535 */ IC_EVEX_L2_KZ, /* 5536 */ IC_EVEX_L2_KZ, /* 5537 */ IC_EVEX_L2_XS_KZ, /* 5538 */ IC_EVEX_L2_XS_KZ, /* 5539 */ IC_EVEX_L2_XD_KZ, /* 5540 */ IC_EVEX_L2_XD_KZ, /* 5541 */ IC_EVEX_L2_XD_KZ, /* 5542 */ IC_EVEX_L2_XD_KZ, /* 5543 */ IC_EVEX_L2_W_KZ, /* 5544 */ IC_EVEX_L2_W_KZ, /* 5545 */ IC_EVEX_L2_W_XS_KZ, /* 5546 */ IC_EVEX_L2_W_XS_KZ, /* 5547 */ IC_EVEX_L2_W_XD_KZ, /* 5548 */ IC_EVEX_L2_W_XD_KZ, /* 5549 */ IC_EVEX_L2_W_XD_KZ, /* 5550 */ IC_EVEX_L2_W_XD_KZ, /* 5551 */ IC_EVEX_L2_OPSIZE_KZ, /* 5552 */ IC_EVEX_L2_OPSIZE_KZ, /* 5553 */ IC_EVEX_L2_OPSIZE_KZ, /* 5554 */ IC_EVEX_L2_OPSIZE_KZ, /* 5555 */ IC_EVEX_L2_OPSIZE_KZ, /* 5556 */ IC_EVEX_L2_OPSIZE_KZ, /* 5557 */ IC_EVEX_L2_OPSIZE_KZ, /* 5558 */ IC_EVEX_L2_OPSIZE_KZ, /* 5559 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5560 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5561 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5562 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5563 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5564 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5565 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5566 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5567 */ IC_EVEX_L2_KZ, /* 5568 */ IC_EVEX_L2_KZ, /* 5569 */ IC_EVEX_L2_XS_KZ, /* 5570 */ IC_EVEX_L2_XS_KZ, /* 5571 */ IC_EVEX_L2_XD_KZ, /* 5572 */ IC_EVEX_L2_XD_KZ, /* 5573 */ IC_EVEX_L2_XD_KZ, /* 5574 */ IC_EVEX_L2_XD_KZ, /* 5575 */ IC_EVEX_L2_W_KZ, /* 5576 */ IC_EVEX_L2_W_KZ, /* 5577 */ IC_EVEX_L2_W_XS_KZ, /* 5578 */ IC_EVEX_L2_W_XS_KZ, /* 5579 */ IC_EVEX_L2_W_XD_KZ, /* 5580 */ IC_EVEX_L2_W_XD_KZ, /* 5581 */ IC_EVEX_L2_W_XD_KZ, /* 5582 */ IC_EVEX_L2_W_XD_KZ, /* 5583 */ IC_EVEX_L2_OPSIZE_KZ, /* 5584 */ IC_EVEX_L2_OPSIZE_KZ, /* 5585 */ IC_EVEX_L2_OPSIZE_KZ, /* 5586 */ IC_EVEX_L2_OPSIZE_KZ, /* 5587 */ IC_EVEX_L2_OPSIZE_KZ, /* 5588 */ IC_EVEX_L2_OPSIZE_KZ, /* 5589 */ IC_EVEX_L2_OPSIZE_KZ, /* 5590 */ IC_EVEX_L2_OPSIZE_KZ, /* 5591 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5592 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5593 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5594 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5595 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5596 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5597 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5598 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5599 */ IC_EVEX_L2_KZ, /* 5600 */ IC_EVEX_L2_KZ, /* 5601 */ IC_EVEX_L2_XS_KZ, /* 5602 */ IC_EVEX_L2_XS_KZ, /* 5603 */ IC_EVEX_L2_XD_KZ, /* 5604 */ IC_EVEX_L2_XD_KZ, /* 5605 */ IC_EVEX_L2_XD_KZ, /* 5606 */ IC_EVEX_L2_XD_KZ, /* 5607 */ IC_EVEX_L2_W_KZ, /* 5608 */ IC_EVEX_L2_W_KZ, /* 5609 */ IC_EVEX_L2_W_XS_KZ, /* 5610 */ IC_EVEX_L2_W_XS_KZ, /* 5611 */ IC_EVEX_L2_W_XD_KZ, /* 5612 */ IC_EVEX_L2_W_XD_KZ, /* 5613 */ IC_EVEX_L2_W_XD_KZ, /* 5614 */ IC_EVEX_L2_W_XD_KZ, /* 5615 */ IC_EVEX_L2_OPSIZE_KZ, /* 5616 */ IC_EVEX_L2_OPSIZE_KZ, /* 5617 */ IC_EVEX_L2_OPSIZE_KZ, /* 5618 */ IC_EVEX_L2_OPSIZE_KZ, /* 5619 */ IC_EVEX_L2_OPSIZE_KZ, /* 5620 */ IC_EVEX_L2_OPSIZE_KZ, /* 5621 */ IC_EVEX_L2_OPSIZE_KZ, /* 5622 */ IC_EVEX_L2_OPSIZE_KZ, /* 5623 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5624 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5625 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5626 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5627 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5628 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5629 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5630 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5631 */ IC, /* 5632 */ IC_64BIT, /* 5633 */ IC_XS, /* 5634 */ IC_64BIT_XS, /* 5635 */ IC_XD, /* 5636 */ IC_64BIT_XD, /* 5637 */ IC_XS, /* 5638 */ IC_64BIT_XS, /* 5639 */ IC, /* 5640 */ IC_64BIT_REXW, /* 5641 */ IC_XS, /* 5642 */ IC_64BIT_REXW_XS, /* 5643 */ IC_XD, /* 5644 */ IC_64BIT_REXW_XD, /* 5645 */ IC_XS, /* 5646 */ IC_64BIT_REXW_XS, /* 5647 */ IC_OPSIZE, /* 5648 */ IC_64BIT_OPSIZE, /* 5649 */ IC_XS_OPSIZE, /* 5650 */ IC_64BIT_XS_OPSIZE, /* 5651 */ IC_XD_OPSIZE, /* 5652 */ IC_64BIT_XD_OPSIZE, /* 5653 */ IC_XS_OPSIZE, /* 5654 */ IC_64BIT_XD_OPSIZE, /* 5655 */ IC_OPSIZE, /* 5656 */ IC_64BIT_REXW_OPSIZE, /* 5657 */ IC_XS_OPSIZE, /* 5658 */ IC_64BIT_REXW_XS, /* 5659 */ IC_XD_OPSIZE, /* 5660 */ IC_64BIT_REXW_XD, /* 5661 */ IC_XS_OPSIZE, /* 5662 */ IC_64BIT_REXW_XS, /* 5663 */ IC_ADSIZE, /* 5664 */ IC_64BIT_ADSIZE, /* 5665 */ IC_XS_ADSIZE, /* 5666 */ IC_64BIT_XS_ADSIZE, /* 5667 */ IC_XD_ADSIZE, /* 5668 */ IC_64BIT_XD_ADSIZE, /* 5669 */ IC_XS_ADSIZE, /* 5670 */ IC_64BIT_XD_ADSIZE, /* 5671 */ IC_ADSIZE, /* 5672 */ IC_64BIT_REXW_ADSIZE, /* 5673 */ IC_XS_ADSIZE, /* 5674 */ IC_64BIT_REXW_XS, /* 5675 */ IC_XD_ADSIZE, /* 5676 */ IC_64BIT_REXW_XD, /* 5677 */ IC_XS_ADSIZE, /* 5678 */ IC_64BIT_REXW_XS, /* 5679 */ IC_OPSIZE_ADSIZE, /* 5680 */ IC_64BIT_OPSIZE_ADSIZE, /* 5681 */ IC_XS_OPSIZE, /* 5682 */ IC_64BIT_XS_OPSIZE, /* 5683 */ IC_XD_OPSIZE, /* 5684 */ IC_64BIT_XD_OPSIZE, /* 5685 */ IC_XS_OPSIZE, /* 5686 */ IC_64BIT_XD_OPSIZE, /* 5687 */ IC_OPSIZE_ADSIZE, /* 5688 */ IC_64BIT_REXW_OPSIZE, /* 5689 */ IC_XS_OPSIZE, /* 5690 */ IC_64BIT_REXW_XS, /* 5691 */ IC_XD_OPSIZE, /* 5692 */ IC_64BIT_REXW_XD, /* 5693 */ IC_XS_OPSIZE, /* 5694 */ IC_64BIT_REXW_XS, /* 5695 */ IC_VEX, /* 5696 */ IC_VEX, /* 5697 */ IC_VEX_XS, /* 5698 */ IC_VEX_XS, /* 5699 */ IC_VEX_XD, /* 5700 */ IC_VEX_XD, /* 5701 */ IC_VEX_XD, /* 5702 */ IC_VEX_XD, /* 5703 */ IC_VEX_W, /* 5704 */ IC_VEX_W, /* 5705 */ IC_VEX_W_XS, /* 5706 */ IC_VEX_W_XS, /* 5707 */ IC_VEX_W_XD, /* 5708 */ IC_VEX_W_XD, /* 5709 */ IC_VEX_W_XD, /* 5710 */ IC_VEX_W_XD, /* 5711 */ IC_VEX_OPSIZE, /* 5712 */ IC_VEX_OPSIZE, /* 5713 */ IC_VEX_OPSIZE, /* 5714 */ IC_VEX_OPSIZE, /* 5715 */ IC_VEX_OPSIZE, /* 5716 */ IC_VEX_OPSIZE, /* 5717 */ IC_VEX_OPSIZE, /* 5718 */ IC_VEX_OPSIZE, /* 5719 */ IC_VEX_W_OPSIZE, /* 5720 */ IC_VEX_W_OPSIZE, /* 5721 */ IC_VEX_W_OPSIZE, /* 5722 */ IC_VEX_W_OPSIZE, /* 5723 */ IC_VEX_W_OPSIZE, /* 5724 */ IC_VEX_W_OPSIZE, /* 5725 */ IC_VEX_W_OPSIZE, /* 5726 */ IC_VEX_W_OPSIZE, /* 5727 */ IC_VEX, /* 5728 */ IC_VEX, /* 5729 */ IC_VEX_XS, /* 5730 */ IC_VEX_XS, /* 5731 */ IC_VEX_XD, /* 5732 */ IC_VEX_XD, /* 5733 */ IC_VEX_XD, /* 5734 */ IC_VEX_XD, /* 5735 */ IC_VEX_W, /* 5736 */ IC_VEX_W, /* 5737 */ IC_VEX_W_XS, /* 5738 */ IC_VEX_W_XS, /* 5739 */ IC_VEX_W_XD, /* 5740 */ IC_VEX_W_XD, /* 5741 */ IC_VEX_W_XD, /* 5742 */ IC_VEX_W_XD, /* 5743 */ IC_VEX_OPSIZE, /* 5744 */ IC_VEX_OPSIZE, /* 5745 */ IC_VEX_OPSIZE, /* 5746 */ IC_VEX_OPSIZE, /* 5747 */ IC_VEX_OPSIZE, /* 5748 */ IC_VEX_OPSIZE, /* 5749 */ IC_VEX_OPSIZE, /* 5750 */ IC_VEX_OPSIZE, /* 5751 */ IC_VEX_W_OPSIZE, /* 5752 */ IC_VEX_W_OPSIZE, /* 5753 */ IC_VEX_W_OPSIZE, /* 5754 */ IC_VEX_W_OPSIZE, /* 5755 */ IC_VEX_W_OPSIZE, /* 5756 */ IC_VEX_W_OPSIZE, /* 5757 */ IC_VEX_W_OPSIZE, /* 5758 */ IC_VEX_W_OPSIZE, /* 5759 */ IC_VEX_L, /* 5760 */ IC_VEX_L, /* 5761 */ IC_VEX_L_XS, /* 5762 */ IC_VEX_L_XS, /* 5763 */ IC_VEX_L_XD, /* 5764 */ IC_VEX_L_XD, /* 5765 */ IC_VEX_L_XD, /* 5766 */ IC_VEX_L_XD, /* 5767 */ IC_VEX_L_W, /* 5768 */ IC_VEX_L_W, /* 5769 */ IC_VEX_L_W_XS, /* 5770 */ IC_VEX_L_W_XS, /* 5771 */ IC_VEX_L_W_XD, /* 5772 */ IC_VEX_L_W_XD, /* 5773 */ IC_VEX_L_W_XD, /* 5774 */ IC_VEX_L_W_XD, /* 5775 */ IC_VEX_L_OPSIZE, /* 5776 */ IC_VEX_L_OPSIZE, /* 5777 */ IC_VEX_L_OPSIZE, /* 5778 */ IC_VEX_L_OPSIZE, /* 5779 */ IC_VEX_L_OPSIZE, /* 5780 */ IC_VEX_L_OPSIZE, /* 5781 */ IC_VEX_L_OPSIZE, /* 5782 */ IC_VEX_L_OPSIZE, /* 5783 */ IC_VEX_L_W_OPSIZE, /* 5784 */ IC_VEX_L_W_OPSIZE, /* 5785 */ IC_VEX_L_W_OPSIZE, /* 5786 */ IC_VEX_L_W_OPSIZE, /* 5787 */ IC_VEX_L_W_OPSIZE, /* 5788 */ IC_VEX_L_W_OPSIZE, /* 5789 */ IC_VEX_L_W_OPSIZE, /* 5790 */ IC_VEX_L_W_OPSIZE, /* 5791 */ IC_VEX_L, /* 5792 */ IC_VEX_L, /* 5793 */ IC_VEX_L_XS, /* 5794 */ IC_VEX_L_XS, /* 5795 */ IC_VEX_L_XD, /* 5796 */ IC_VEX_L_XD, /* 5797 */ IC_VEX_L_XD, /* 5798 */ IC_VEX_L_XD, /* 5799 */ IC_VEX_L_W, /* 5800 */ IC_VEX_L_W, /* 5801 */ IC_VEX_L_W_XS, /* 5802 */ IC_VEX_L_W_XS, /* 5803 */ IC_VEX_L_W_XD, /* 5804 */ IC_VEX_L_W_XD, /* 5805 */ IC_VEX_L_W_XD, /* 5806 */ IC_VEX_L_W_XD, /* 5807 */ IC_VEX_L_OPSIZE, /* 5808 */ IC_VEX_L_OPSIZE, /* 5809 */ IC_VEX_L_OPSIZE, /* 5810 */ IC_VEX_L_OPSIZE, /* 5811 */ IC_VEX_L_OPSIZE, /* 5812 */ IC_VEX_L_OPSIZE, /* 5813 */ IC_VEX_L_OPSIZE, /* 5814 */ IC_VEX_L_OPSIZE, /* 5815 */ IC_VEX_L_W_OPSIZE, /* 5816 */ IC_VEX_L_W_OPSIZE, /* 5817 */ IC_VEX_L_W_OPSIZE, /* 5818 */ IC_VEX_L_W_OPSIZE, /* 5819 */ IC_VEX_L_W_OPSIZE, /* 5820 */ IC_VEX_L_W_OPSIZE, /* 5821 */ IC_VEX_L_W_OPSIZE, /* 5822 */ IC_VEX_L_W_OPSIZE, /* 5823 */ IC_VEX_L, /* 5824 */ IC_VEX_L, /* 5825 */ IC_VEX_L_XS, /* 5826 */ IC_VEX_L_XS, /* 5827 */ IC_VEX_L_XD, /* 5828 */ IC_VEX_L_XD, /* 5829 */ IC_VEX_L_XD, /* 5830 */ IC_VEX_L_XD, /* 5831 */ IC_VEX_L_W, /* 5832 */ IC_VEX_L_W, /* 5833 */ IC_VEX_L_W_XS, /* 5834 */ IC_VEX_L_W_XS, /* 5835 */ IC_VEX_L_W_XD, /* 5836 */ IC_VEX_L_W_XD, /* 5837 */ IC_VEX_L_W_XD, /* 5838 */ IC_VEX_L_W_XD, /* 5839 */ IC_VEX_L_OPSIZE, /* 5840 */ IC_VEX_L_OPSIZE, /* 5841 */ IC_VEX_L_OPSIZE, /* 5842 */ IC_VEX_L_OPSIZE, /* 5843 */ IC_VEX_L_OPSIZE, /* 5844 */ IC_VEX_L_OPSIZE, /* 5845 */ IC_VEX_L_OPSIZE, /* 5846 */ IC_VEX_L_OPSIZE, /* 5847 */ IC_VEX_L_W_OPSIZE, /* 5848 */ IC_VEX_L_W_OPSIZE, /* 5849 */ IC_VEX_L_W_OPSIZE, /* 5850 */ IC_VEX_L_W_OPSIZE, /* 5851 */ IC_VEX_L_W_OPSIZE, /* 5852 */ IC_VEX_L_W_OPSIZE, /* 5853 */ IC_VEX_L_W_OPSIZE, /* 5854 */ IC_VEX_L_W_OPSIZE, /* 5855 */ IC_VEX_L, /* 5856 */ IC_VEX_L, /* 5857 */ IC_VEX_L_XS, /* 5858 */ IC_VEX_L_XS, /* 5859 */ IC_VEX_L_XD, /* 5860 */ IC_VEX_L_XD, /* 5861 */ IC_VEX_L_XD, /* 5862 */ IC_VEX_L_XD, /* 5863 */ IC_VEX_L_W, /* 5864 */ IC_VEX_L_W, /* 5865 */ IC_VEX_L_W_XS, /* 5866 */ IC_VEX_L_W_XS, /* 5867 */ IC_VEX_L_W_XD, /* 5868 */ IC_VEX_L_W_XD, /* 5869 */ IC_VEX_L_W_XD, /* 5870 */ IC_VEX_L_W_XD, /* 5871 */ IC_VEX_L_OPSIZE, /* 5872 */ IC_VEX_L_OPSIZE, /* 5873 */ IC_VEX_L_OPSIZE, /* 5874 */ IC_VEX_L_OPSIZE, /* 5875 */ IC_VEX_L_OPSIZE, /* 5876 */ IC_VEX_L_OPSIZE, /* 5877 */ IC_VEX_L_OPSIZE, /* 5878 */ IC_VEX_L_OPSIZE, /* 5879 */ IC_VEX_L_W_OPSIZE, /* 5880 */ IC_VEX_L_W_OPSIZE, /* 5881 */ IC_VEX_L_W_OPSIZE, /* 5882 */ IC_VEX_L_W_OPSIZE, /* 5883 */ IC_VEX_L_W_OPSIZE, /* 5884 */ IC_VEX_L_W_OPSIZE, /* 5885 */ IC_VEX_L_W_OPSIZE, /* 5886 */ IC_VEX_L_W_OPSIZE, /* 5887 */ IC_EVEX_L2_KZ, /* 5888 */ IC_EVEX_L2_KZ, /* 5889 */ IC_EVEX_L2_XS_KZ, /* 5890 */ IC_EVEX_L2_XS_KZ, /* 5891 */ IC_EVEX_L2_XD_KZ, /* 5892 */ IC_EVEX_L2_XD_KZ, /* 5893 */ IC_EVEX_L2_XD_KZ, /* 5894 */ IC_EVEX_L2_XD_KZ, /* 5895 */ IC_EVEX_L2_W_KZ, /* 5896 */ IC_EVEX_L2_W_KZ, /* 5897 */ IC_EVEX_L2_W_XS_KZ, /* 5898 */ IC_EVEX_L2_W_XS_KZ, /* 5899 */ IC_EVEX_L2_W_XD_KZ, /* 5900 */ IC_EVEX_L2_W_XD_KZ, /* 5901 */ IC_EVEX_L2_W_XD_KZ, /* 5902 */ IC_EVEX_L2_W_XD_KZ, /* 5903 */ IC_EVEX_L2_OPSIZE_KZ, /* 5904 */ IC_EVEX_L2_OPSIZE_KZ, /* 5905 */ IC_EVEX_L2_OPSIZE_KZ, /* 5906 */ IC_EVEX_L2_OPSIZE_KZ, /* 5907 */ IC_EVEX_L2_OPSIZE_KZ, /* 5908 */ IC_EVEX_L2_OPSIZE_KZ, /* 5909 */ IC_EVEX_L2_OPSIZE_KZ, /* 5910 */ IC_EVEX_L2_OPSIZE_KZ, /* 5911 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5912 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5913 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5914 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5915 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5916 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5917 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5918 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5919 */ IC_EVEX_L2_KZ, /* 5920 */ IC_EVEX_L2_KZ, /* 5921 */ IC_EVEX_L2_XS_KZ, /* 5922 */ IC_EVEX_L2_XS_KZ, /* 5923 */ IC_EVEX_L2_XD_KZ, /* 5924 */ IC_EVEX_L2_XD_KZ, /* 5925 */ IC_EVEX_L2_XD_KZ, /* 5926 */ IC_EVEX_L2_XD_KZ, /* 5927 */ IC_EVEX_L2_W_KZ, /* 5928 */ IC_EVEX_L2_W_KZ, /* 5929 */ IC_EVEX_L2_W_XS_KZ, /* 5930 */ IC_EVEX_L2_W_XS_KZ, /* 5931 */ IC_EVEX_L2_W_XD_KZ, /* 5932 */ IC_EVEX_L2_W_XD_KZ, /* 5933 */ IC_EVEX_L2_W_XD_KZ, /* 5934 */ IC_EVEX_L2_W_XD_KZ, /* 5935 */ IC_EVEX_L2_OPSIZE_KZ, /* 5936 */ IC_EVEX_L2_OPSIZE_KZ, /* 5937 */ IC_EVEX_L2_OPSIZE_KZ, /* 5938 */ IC_EVEX_L2_OPSIZE_KZ, /* 5939 */ IC_EVEX_L2_OPSIZE_KZ, /* 5940 */ IC_EVEX_L2_OPSIZE_KZ, /* 5941 */ IC_EVEX_L2_OPSIZE_KZ, /* 5942 */ IC_EVEX_L2_OPSIZE_KZ, /* 5943 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5944 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5945 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5946 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5947 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5948 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5949 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5950 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5951 */ IC_EVEX_L2_KZ, /* 5952 */ IC_EVEX_L2_KZ, /* 5953 */ IC_EVEX_L2_XS_KZ, /* 5954 */ IC_EVEX_L2_XS_KZ, /* 5955 */ IC_EVEX_L2_XD_KZ, /* 5956 */ IC_EVEX_L2_XD_KZ, /* 5957 */ IC_EVEX_L2_XD_KZ, /* 5958 */ IC_EVEX_L2_XD_KZ, /* 5959 */ IC_EVEX_L2_W_KZ, /* 5960 */ IC_EVEX_L2_W_KZ, /* 5961 */ IC_EVEX_L2_W_XS_KZ, /* 5962 */ IC_EVEX_L2_W_XS_KZ, /* 5963 */ IC_EVEX_L2_W_XD_KZ, /* 5964 */ IC_EVEX_L2_W_XD_KZ, /* 5965 */ IC_EVEX_L2_W_XD_KZ, /* 5966 */ IC_EVEX_L2_W_XD_KZ, /* 5967 */ IC_EVEX_L2_OPSIZE_KZ, /* 5968 */ IC_EVEX_L2_OPSIZE_KZ, /* 5969 */ IC_EVEX_L2_OPSIZE_KZ, /* 5970 */ IC_EVEX_L2_OPSIZE_KZ, /* 5971 */ IC_EVEX_L2_OPSIZE_KZ, /* 5972 */ IC_EVEX_L2_OPSIZE_KZ, /* 5973 */ IC_EVEX_L2_OPSIZE_KZ, /* 5974 */ IC_EVEX_L2_OPSIZE_KZ, /* 5975 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5976 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5977 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5978 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5979 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5980 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5981 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5982 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5983 */ IC_EVEX_L2_KZ, /* 5984 */ IC_EVEX_L2_KZ, /* 5985 */ IC_EVEX_L2_XS_KZ, /* 5986 */ IC_EVEX_L2_XS_KZ, /* 5987 */ IC_EVEX_L2_XD_KZ, /* 5988 */ IC_EVEX_L2_XD_KZ, /* 5989 */ IC_EVEX_L2_XD_KZ, /* 5990 */ IC_EVEX_L2_XD_KZ, /* 5991 */ IC_EVEX_L2_W_KZ, /* 5992 */ IC_EVEX_L2_W_KZ, /* 5993 */ IC_EVEX_L2_W_XS_KZ, /* 5994 */ IC_EVEX_L2_W_XS_KZ, /* 5995 */ IC_EVEX_L2_W_XD_KZ, /* 5996 */ IC_EVEX_L2_W_XD_KZ, /* 5997 */ IC_EVEX_L2_W_XD_KZ, /* 5998 */ IC_EVEX_L2_W_XD_KZ, /* 5999 */ IC_EVEX_L2_OPSIZE_KZ, /* 6000 */ IC_EVEX_L2_OPSIZE_KZ, /* 6001 */ IC_EVEX_L2_OPSIZE_KZ, /* 6002 */ IC_EVEX_L2_OPSIZE_KZ, /* 6003 */ IC_EVEX_L2_OPSIZE_KZ, /* 6004 */ IC_EVEX_L2_OPSIZE_KZ, /* 6005 */ IC_EVEX_L2_OPSIZE_KZ, /* 6006 */ IC_EVEX_L2_OPSIZE_KZ, /* 6007 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6008 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6009 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6010 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6011 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6012 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6013 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6014 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6015 */ IC_EVEX_L2_KZ, /* 6016 */ IC_EVEX_L2_KZ, /* 6017 */ IC_EVEX_L2_XS_KZ, /* 6018 */ IC_EVEX_L2_XS_KZ, /* 6019 */ IC_EVEX_L2_XD_KZ, /* 6020 */ IC_EVEX_L2_XD_KZ, /* 6021 */ IC_EVEX_L2_XD_KZ, /* 6022 */ IC_EVEX_L2_XD_KZ, /* 6023 */ IC_EVEX_L2_W_KZ, /* 6024 */ IC_EVEX_L2_W_KZ, /* 6025 */ IC_EVEX_L2_W_XS_KZ, /* 6026 */ IC_EVEX_L2_W_XS_KZ, /* 6027 */ IC_EVEX_L2_W_XD_KZ, /* 6028 */ IC_EVEX_L2_W_XD_KZ, /* 6029 */ IC_EVEX_L2_W_XD_KZ, /* 6030 */ IC_EVEX_L2_W_XD_KZ, /* 6031 */ IC_EVEX_L2_OPSIZE_KZ, /* 6032 */ IC_EVEX_L2_OPSIZE_KZ, /* 6033 */ IC_EVEX_L2_OPSIZE_KZ, /* 6034 */ IC_EVEX_L2_OPSIZE_KZ, /* 6035 */ IC_EVEX_L2_OPSIZE_KZ, /* 6036 */ IC_EVEX_L2_OPSIZE_KZ, /* 6037 */ IC_EVEX_L2_OPSIZE_KZ, /* 6038 */ IC_EVEX_L2_OPSIZE_KZ, /* 6039 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6040 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6041 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6042 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6043 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6044 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6045 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6046 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6047 */ IC_EVEX_L2_KZ, /* 6048 */ IC_EVEX_L2_KZ, /* 6049 */ IC_EVEX_L2_XS_KZ, /* 6050 */ IC_EVEX_L2_XS_KZ, /* 6051 */ IC_EVEX_L2_XD_KZ, /* 6052 */ IC_EVEX_L2_XD_KZ, /* 6053 */ IC_EVEX_L2_XD_KZ, /* 6054 */ IC_EVEX_L2_XD_KZ, /* 6055 */ IC_EVEX_L2_W_KZ, /* 6056 */ IC_EVEX_L2_W_KZ, /* 6057 */ IC_EVEX_L2_W_XS_KZ, /* 6058 */ IC_EVEX_L2_W_XS_KZ, /* 6059 */ IC_EVEX_L2_W_XD_KZ, /* 6060 */ IC_EVEX_L2_W_XD_KZ, /* 6061 */ IC_EVEX_L2_W_XD_KZ, /* 6062 */ IC_EVEX_L2_W_XD_KZ, /* 6063 */ IC_EVEX_L2_OPSIZE_KZ, /* 6064 */ IC_EVEX_L2_OPSIZE_KZ, /* 6065 */ IC_EVEX_L2_OPSIZE_KZ, /* 6066 */ IC_EVEX_L2_OPSIZE_KZ, /* 6067 */ IC_EVEX_L2_OPSIZE_KZ, /* 6068 */ IC_EVEX_L2_OPSIZE_KZ, /* 6069 */ IC_EVEX_L2_OPSIZE_KZ, /* 6070 */ IC_EVEX_L2_OPSIZE_KZ, /* 6071 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6072 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6073 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6074 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6075 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6076 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6077 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6078 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6079 */ IC_EVEX_L2_KZ, /* 6080 */ IC_EVEX_L2_KZ, /* 6081 */ IC_EVEX_L2_XS_KZ, /* 6082 */ IC_EVEX_L2_XS_KZ, /* 6083 */ IC_EVEX_L2_XD_KZ, /* 6084 */ IC_EVEX_L2_XD_KZ, /* 6085 */ IC_EVEX_L2_XD_KZ, /* 6086 */ IC_EVEX_L2_XD_KZ, /* 6087 */ IC_EVEX_L2_W_KZ, /* 6088 */ IC_EVEX_L2_W_KZ, /* 6089 */ IC_EVEX_L2_W_XS_KZ, /* 6090 */ IC_EVEX_L2_W_XS_KZ, /* 6091 */ IC_EVEX_L2_W_XD_KZ, /* 6092 */ IC_EVEX_L2_W_XD_KZ, /* 6093 */ IC_EVEX_L2_W_XD_KZ, /* 6094 */ IC_EVEX_L2_W_XD_KZ, /* 6095 */ IC_EVEX_L2_OPSIZE_KZ, /* 6096 */ IC_EVEX_L2_OPSIZE_KZ, /* 6097 */ IC_EVEX_L2_OPSIZE_KZ, /* 6098 */ IC_EVEX_L2_OPSIZE_KZ, /* 6099 */ IC_EVEX_L2_OPSIZE_KZ, /* 6100 */ IC_EVEX_L2_OPSIZE_KZ, /* 6101 */ IC_EVEX_L2_OPSIZE_KZ, /* 6102 */ IC_EVEX_L2_OPSIZE_KZ, /* 6103 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6104 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6105 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6106 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6107 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6108 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6109 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6110 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6111 */ IC_EVEX_L2_KZ, /* 6112 */ IC_EVEX_L2_KZ, /* 6113 */ IC_EVEX_L2_XS_KZ, /* 6114 */ IC_EVEX_L2_XS_KZ, /* 6115 */ IC_EVEX_L2_XD_KZ, /* 6116 */ IC_EVEX_L2_XD_KZ, /* 6117 */ IC_EVEX_L2_XD_KZ, /* 6118 */ IC_EVEX_L2_XD_KZ, /* 6119 */ IC_EVEX_L2_W_KZ, /* 6120 */ IC_EVEX_L2_W_KZ, /* 6121 */ IC_EVEX_L2_W_XS_KZ, /* 6122 */ IC_EVEX_L2_W_XS_KZ, /* 6123 */ IC_EVEX_L2_W_XD_KZ, /* 6124 */ IC_EVEX_L2_W_XD_KZ, /* 6125 */ IC_EVEX_L2_W_XD_KZ, /* 6126 */ IC_EVEX_L2_W_XD_KZ, /* 6127 */ IC_EVEX_L2_OPSIZE_KZ, /* 6128 */ IC_EVEX_L2_OPSIZE_KZ, /* 6129 */ IC_EVEX_L2_OPSIZE_KZ, /* 6130 */ IC_EVEX_L2_OPSIZE_KZ, /* 6131 */ IC_EVEX_L2_OPSIZE_KZ, /* 6132 */ IC_EVEX_L2_OPSIZE_KZ, /* 6133 */ IC_EVEX_L2_OPSIZE_KZ, /* 6134 */ IC_EVEX_L2_OPSIZE_KZ, /* 6135 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6136 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6137 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6138 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6139 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6140 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6141 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6142 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6143 */ IC, /* 6144 */ IC_64BIT, /* 6145 */ IC_XS, /* 6146 */ IC_64BIT_XS, /* 6147 */ IC_XD, /* 6148 */ IC_64BIT_XD, /* 6149 */ IC_XS, /* 6150 */ IC_64BIT_XS, /* 6151 */ IC, /* 6152 */ IC_64BIT_REXW, /* 6153 */ IC_XS, /* 6154 */ IC_64BIT_REXW_XS, /* 6155 */ IC_XD, /* 6156 */ IC_64BIT_REXW_XD, /* 6157 */ IC_XS, /* 6158 */ IC_64BIT_REXW_XS, /* 6159 */ IC_OPSIZE, /* 6160 */ IC_64BIT_OPSIZE, /* 6161 */ IC_XS_OPSIZE, /* 6162 */ IC_64BIT_XS_OPSIZE, /* 6163 */ IC_XD_OPSIZE, /* 6164 */ IC_64BIT_XD_OPSIZE, /* 6165 */ IC_XS_OPSIZE, /* 6166 */ IC_64BIT_XD_OPSIZE, /* 6167 */ IC_OPSIZE, /* 6168 */ IC_64BIT_REXW_OPSIZE, /* 6169 */ IC_XS_OPSIZE, /* 6170 */ IC_64BIT_REXW_XS, /* 6171 */ IC_XD_OPSIZE, /* 6172 */ IC_64BIT_REXW_XD, /* 6173 */ IC_XS_OPSIZE, /* 6174 */ IC_64BIT_REXW_XS, /* 6175 */ IC_ADSIZE, /* 6176 */ IC_64BIT_ADSIZE, /* 6177 */ IC_XS_ADSIZE, /* 6178 */ IC_64BIT_XS_ADSIZE, /* 6179 */ IC_XD_ADSIZE, /* 6180 */ IC_64BIT_XD_ADSIZE, /* 6181 */ IC_XS_ADSIZE, /* 6182 */ IC_64BIT_XD_ADSIZE, /* 6183 */ IC_ADSIZE, /* 6184 */ IC_64BIT_REXW_ADSIZE, /* 6185 */ IC_XS_ADSIZE, /* 6186 */ IC_64BIT_REXW_XS, /* 6187 */ IC_XD_ADSIZE, /* 6188 */ IC_64BIT_REXW_XD, /* 6189 */ IC_XS_ADSIZE, /* 6190 */ IC_64BIT_REXW_XS, /* 6191 */ IC_OPSIZE_ADSIZE, /* 6192 */ IC_64BIT_OPSIZE_ADSIZE, /* 6193 */ IC_XS_OPSIZE, /* 6194 */ IC_64BIT_XS_OPSIZE, /* 6195 */ IC_XD_OPSIZE, /* 6196 */ IC_64BIT_XD_OPSIZE, /* 6197 */ IC_XS_OPSIZE, /* 6198 */ IC_64BIT_XD_OPSIZE, /* 6199 */ IC_OPSIZE_ADSIZE, /* 6200 */ IC_64BIT_REXW_OPSIZE, /* 6201 */ IC_XS_OPSIZE, /* 6202 */ IC_64BIT_REXW_XS, /* 6203 */ IC_XD_OPSIZE, /* 6204 */ IC_64BIT_REXW_XD, /* 6205 */ IC_XS_OPSIZE, /* 6206 */ IC_64BIT_REXW_XS, /* 6207 */ IC_VEX, /* 6208 */ IC_VEX, /* 6209 */ IC_VEX_XS, /* 6210 */ IC_VEX_XS, /* 6211 */ IC_VEX_XD, /* 6212 */ IC_VEX_XD, /* 6213 */ IC_VEX_XD, /* 6214 */ IC_VEX_XD, /* 6215 */ IC_VEX_W, /* 6216 */ IC_VEX_W, /* 6217 */ IC_VEX_W_XS, /* 6218 */ IC_VEX_W_XS, /* 6219 */ IC_VEX_W_XD, /* 6220 */ IC_VEX_W_XD, /* 6221 */ IC_VEX_W_XD, /* 6222 */ IC_VEX_W_XD, /* 6223 */ IC_VEX_OPSIZE, /* 6224 */ IC_VEX_OPSIZE, /* 6225 */ IC_VEX_OPSIZE, /* 6226 */ IC_VEX_OPSIZE, /* 6227 */ IC_VEX_OPSIZE, /* 6228 */ IC_VEX_OPSIZE, /* 6229 */ IC_VEX_OPSIZE, /* 6230 */ IC_VEX_OPSIZE, /* 6231 */ IC_VEX_W_OPSIZE, /* 6232 */ IC_VEX_W_OPSIZE, /* 6233 */ IC_VEX_W_OPSIZE, /* 6234 */ IC_VEX_W_OPSIZE, /* 6235 */ IC_VEX_W_OPSIZE, /* 6236 */ IC_VEX_W_OPSIZE, /* 6237 */ IC_VEX_W_OPSIZE, /* 6238 */ IC_VEX_W_OPSIZE, /* 6239 */ IC_VEX, /* 6240 */ IC_VEX, /* 6241 */ IC_VEX_XS, /* 6242 */ IC_VEX_XS, /* 6243 */ IC_VEX_XD, /* 6244 */ IC_VEX_XD, /* 6245 */ IC_VEX_XD, /* 6246 */ IC_VEX_XD, /* 6247 */ IC_VEX_W, /* 6248 */ IC_VEX_W, /* 6249 */ IC_VEX_W_XS, /* 6250 */ IC_VEX_W_XS, /* 6251 */ IC_VEX_W_XD, /* 6252 */ IC_VEX_W_XD, /* 6253 */ IC_VEX_W_XD, /* 6254 */ IC_VEX_W_XD, /* 6255 */ IC_VEX_OPSIZE, /* 6256 */ IC_VEX_OPSIZE, /* 6257 */ IC_VEX_OPSIZE, /* 6258 */ IC_VEX_OPSIZE, /* 6259 */ IC_VEX_OPSIZE, /* 6260 */ IC_VEX_OPSIZE, /* 6261 */ IC_VEX_OPSIZE, /* 6262 */ IC_VEX_OPSIZE, /* 6263 */ IC_VEX_W_OPSIZE, /* 6264 */ IC_VEX_W_OPSIZE, /* 6265 */ IC_VEX_W_OPSIZE, /* 6266 */ IC_VEX_W_OPSIZE, /* 6267 */ IC_VEX_W_OPSIZE, /* 6268 */ IC_VEX_W_OPSIZE, /* 6269 */ IC_VEX_W_OPSIZE, /* 6270 */ IC_VEX_W_OPSIZE, /* 6271 */ IC_VEX_L, /* 6272 */ IC_VEX_L, /* 6273 */ IC_VEX_L_XS, /* 6274 */ IC_VEX_L_XS, /* 6275 */ IC_VEX_L_XD, /* 6276 */ IC_VEX_L_XD, /* 6277 */ IC_VEX_L_XD, /* 6278 */ IC_VEX_L_XD, /* 6279 */ IC_VEX_L_W, /* 6280 */ IC_VEX_L_W, /* 6281 */ IC_VEX_L_W_XS, /* 6282 */ IC_VEX_L_W_XS, /* 6283 */ IC_VEX_L_W_XD, /* 6284 */ IC_VEX_L_W_XD, /* 6285 */ IC_VEX_L_W_XD, /* 6286 */ IC_VEX_L_W_XD, /* 6287 */ IC_VEX_L_OPSIZE, /* 6288 */ IC_VEX_L_OPSIZE, /* 6289 */ IC_VEX_L_OPSIZE, /* 6290 */ IC_VEX_L_OPSIZE, /* 6291 */ IC_VEX_L_OPSIZE, /* 6292 */ IC_VEX_L_OPSIZE, /* 6293 */ IC_VEX_L_OPSIZE, /* 6294 */ IC_VEX_L_OPSIZE, /* 6295 */ IC_VEX_L_W_OPSIZE, /* 6296 */ IC_VEX_L_W_OPSIZE, /* 6297 */ IC_VEX_L_W_OPSIZE, /* 6298 */ IC_VEX_L_W_OPSIZE, /* 6299 */ IC_VEX_L_W_OPSIZE, /* 6300 */ IC_VEX_L_W_OPSIZE, /* 6301 */ IC_VEX_L_W_OPSIZE, /* 6302 */ IC_VEX_L_W_OPSIZE, /* 6303 */ IC_VEX_L, /* 6304 */ IC_VEX_L, /* 6305 */ IC_VEX_L_XS, /* 6306 */ IC_VEX_L_XS, /* 6307 */ IC_VEX_L_XD, /* 6308 */ IC_VEX_L_XD, /* 6309 */ IC_VEX_L_XD, /* 6310 */ IC_VEX_L_XD, /* 6311 */ IC_VEX_L_W, /* 6312 */ IC_VEX_L_W, /* 6313 */ IC_VEX_L_W_XS, /* 6314 */ IC_VEX_L_W_XS, /* 6315 */ IC_VEX_L_W_XD, /* 6316 */ IC_VEX_L_W_XD, /* 6317 */ IC_VEX_L_W_XD, /* 6318 */ IC_VEX_L_W_XD, /* 6319 */ IC_VEX_L_OPSIZE, /* 6320 */ IC_VEX_L_OPSIZE, /* 6321 */ IC_VEX_L_OPSIZE, /* 6322 */ IC_VEX_L_OPSIZE, /* 6323 */ IC_VEX_L_OPSIZE, /* 6324 */ IC_VEX_L_OPSIZE, /* 6325 */ IC_VEX_L_OPSIZE, /* 6326 */ IC_VEX_L_OPSIZE, /* 6327 */ IC_VEX_L_W_OPSIZE, /* 6328 */ IC_VEX_L_W_OPSIZE, /* 6329 */ IC_VEX_L_W_OPSIZE, /* 6330 */ IC_VEX_L_W_OPSIZE, /* 6331 */ IC_VEX_L_W_OPSIZE, /* 6332 */ IC_VEX_L_W_OPSIZE, /* 6333 */ IC_VEX_L_W_OPSIZE, /* 6334 */ IC_VEX_L_W_OPSIZE, /* 6335 */ IC_VEX_L, /* 6336 */ IC_VEX_L, /* 6337 */ IC_VEX_L_XS, /* 6338 */ IC_VEX_L_XS, /* 6339 */ IC_VEX_L_XD, /* 6340 */ IC_VEX_L_XD, /* 6341 */ IC_VEX_L_XD, /* 6342 */ IC_VEX_L_XD, /* 6343 */ IC_VEX_L_W, /* 6344 */ IC_VEX_L_W, /* 6345 */ IC_VEX_L_W_XS, /* 6346 */ IC_VEX_L_W_XS, /* 6347 */ IC_VEX_L_W_XD, /* 6348 */ IC_VEX_L_W_XD, /* 6349 */ IC_VEX_L_W_XD, /* 6350 */ IC_VEX_L_W_XD, /* 6351 */ IC_VEX_L_OPSIZE, /* 6352 */ IC_VEX_L_OPSIZE, /* 6353 */ IC_VEX_L_OPSIZE, /* 6354 */ IC_VEX_L_OPSIZE, /* 6355 */ IC_VEX_L_OPSIZE, /* 6356 */ IC_VEX_L_OPSIZE, /* 6357 */ IC_VEX_L_OPSIZE, /* 6358 */ IC_VEX_L_OPSIZE, /* 6359 */ IC_VEX_L_W_OPSIZE, /* 6360 */ IC_VEX_L_W_OPSIZE, /* 6361 */ IC_VEX_L_W_OPSIZE, /* 6362 */ IC_VEX_L_W_OPSIZE, /* 6363 */ IC_VEX_L_W_OPSIZE, /* 6364 */ IC_VEX_L_W_OPSIZE, /* 6365 */ IC_VEX_L_W_OPSIZE, /* 6366 */ IC_VEX_L_W_OPSIZE, /* 6367 */ IC_VEX_L, /* 6368 */ IC_VEX_L, /* 6369 */ IC_VEX_L_XS, /* 6370 */ IC_VEX_L_XS, /* 6371 */ IC_VEX_L_XD, /* 6372 */ IC_VEX_L_XD, /* 6373 */ IC_VEX_L_XD, /* 6374 */ IC_VEX_L_XD, /* 6375 */ IC_VEX_L_W, /* 6376 */ IC_VEX_L_W, /* 6377 */ IC_VEX_L_W_XS, /* 6378 */ IC_VEX_L_W_XS, /* 6379 */ IC_VEX_L_W_XD, /* 6380 */ IC_VEX_L_W_XD, /* 6381 */ IC_VEX_L_W_XD, /* 6382 */ IC_VEX_L_W_XD, /* 6383 */ IC_VEX_L_OPSIZE, /* 6384 */ IC_VEX_L_OPSIZE, /* 6385 */ IC_VEX_L_OPSIZE, /* 6386 */ IC_VEX_L_OPSIZE, /* 6387 */ IC_VEX_L_OPSIZE, /* 6388 */ IC_VEX_L_OPSIZE, /* 6389 */ IC_VEX_L_OPSIZE, /* 6390 */ IC_VEX_L_OPSIZE, /* 6391 */ IC_VEX_L_W_OPSIZE, /* 6392 */ IC_VEX_L_W_OPSIZE, /* 6393 */ IC_VEX_L_W_OPSIZE, /* 6394 */ IC_VEX_L_W_OPSIZE, /* 6395 */ IC_VEX_L_W_OPSIZE, /* 6396 */ IC_VEX_L_W_OPSIZE, /* 6397 */ IC_VEX_L_W_OPSIZE, /* 6398 */ IC_VEX_L_W_OPSIZE, /* 6399 */ IC_EVEX_KZ, /* 6400 */ IC_EVEX_KZ, /* 6401 */ IC_EVEX_XS_KZ, /* 6402 */ IC_EVEX_XS_KZ, /* 6403 */ IC_EVEX_XD_KZ, /* 6404 */ IC_EVEX_XD_KZ, /* 6405 */ IC_EVEX_XD_KZ, /* 6406 */ IC_EVEX_XD_KZ, /* 6407 */ IC_EVEX_W_KZ, /* 6408 */ IC_EVEX_W_KZ, /* 6409 */ IC_EVEX_W_XS_KZ, /* 6410 */ IC_EVEX_W_XS_KZ, /* 6411 */ IC_EVEX_W_XD_KZ, /* 6412 */ IC_EVEX_W_XD_KZ, /* 6413 */ IC_EVEX_W_XD_KZ, /* 6414 */ IC_EVEX_W_XD_KZ, /* 6415 */ IC_EVEX_OPSIZE_KZ, /* 6416 */ IC_EVEX_OPSIZE_KZ, /* 6417 */ IC_EVEX_OPSIZE_KZ, /* 6418 */ IC_EVEX_OPSIZE_KZ, /* 6419 */ IC_EVEX_OPSIZE_KZ, /* 6420 */ IC_EVEX_OPSIZE_KZ, /* 6421 */ IC_EVEX_OPSIZE_KZ, /* 6422 */ IC_EVEX_OPSIZE_KZ, /* 6423 */ IC_EVEX_W_OPSIZE_KZ, /* 6424 */ IC_EVEX_W_OPSIZE_KZ, /* 6425 */ IC_EVEX_W_OPSIZE_KZ, /* 6426 */ IC_EVEX_W_OPSIZE_KZ, /* 6427 */ IC_EVEX_W_OPSIZE_KZ, /* 6428 */ IC_EVEX_W_OPSIZE_KZ, /* 6429 */ IC_EVEX_W_OPSIZE_KZ, /* 6430 */ IC_EVEX_W_OPSIZE_KZ, /* 6431 */ IC_EVEX_KZ, /* 6432 */ IC_EVEX_KZ, /* 6433 */ IC_EVEX_XS_KZ, /* 6434 */ IC_EVEX_XS_KZ, /* 6435 */ IC_EVEX_XD_KZ, /* 6436 */ IC_EVEX_XD_KZ, /* 6437 */ IC_EVEX_XD_KZ, /* 6438 */ IC_EVEX_XD_KZ, /* 6439 */ IC_EVEX_W_KZ, /* 6440 */ IC_EVEX_W_KZ, /* 6441 */ IC_EVEX_W_XS_KZ, /* 6442 */ IC_EVEX_W_XS_KZ, /* 6443 */ IC_EVEX_W_XD_KZ, /* 6444 */ IC_EVEX_W_XD_KZ, /* 6445 */ IC_EVEX_W_XD_KZ, /* 6446 */ IC_EVEX_W_XD_KZ, /* 6447 */ IC_EVEX_OPSIZE_KZ, /* 6448 */ IC_EVEX_OPSIZE_KZ, /* 6449 */ IC_EVEX_OPSIZE_KZ, /* 6450 */ IC_EVEX_OPSIZE_KZ, /* 6451 */ IC_EVEX_OPSIZE_KZ, /* 6452 */ IC_EVEX_OPSIZE_KZ, /* 6453 */ IC_EVEX_OPSIZE_KZ, /* 6454 */ IC_EVEX_OPSIZE_KZ, /* 6455 */ IC_EVEX_W_OPSIZE_KZ, /* 6456 */ IC_EVEX_W_OPSIZE_KZ, /* 6457 */ IC_EVEX_W_OPSIZE_KZ, /* 6458 */ IC_EVEX_W_OPSIZE_KZ, /* 6459 */ IC_EVEX_W_OPSIZE_KZ, /* 6460 */ IC_EVEX_W_OPSIZE_KZ, /* 6461 */ IC_EVEX_W_OPSIZE_KZ, /* 6462 */ IC_EVEX_W_OPSIZE_KZ, /* 6463 */ IC_EVEX_KZ, /* 6464 */ IC_EVEX_KZ, /* 6465 */ IC_EVEX_XS_KZ, /* 6466 */ IC_EVEX_XS_KZ, /* 6467 */ IC_EVEX_XD_KZ, /* 6468 */ IC_EVEX_XD_KZ, /* 6469 */ IC_EVEX_XD_KZ, /* 6470 */ IC_EVEX_XD_KZ, /* 6471 */ IC_EVEX_W_KZ, /* 6472 */ IC_EVEX_W_KZ, /* 6473 */ IC_EVEX_W_XS_KZ, /* 6474 */ IC_EVEX_W_XS_KZ, /* 6475 */ IC_EVEX_W_XD_KZ, /* 6476 */ IC_EVEX_W_XD_KZ, /* 6477 */ IC_EVEX_W_XD_KZ, /* 6478 */ IC_EVEX_W_XD_KZ, /* 6479 */ IC_EVEX_OPSIZE_KZ, /* 6480 */ IC_EVEX_OPSIZE_KZ, /* 6481 */ IC_EVEX_OPSIZE_KZ, /* 6482 */ IC_EVEX_OPSIZE_KZ, /* 6483 */ IC_EVEX_OPSIZE_KZ, /* 6484 */ IC_EVEX_OPSIZE_KZ, /* 6485 */ IC_EVEX_OPSIZE_KZ, /* 6486 */ IC_EVEX_OPSIZE_KZ, /* 6487 */ IC_EVEX_W_OPSIZE_KZ, /* 6488 */ IC_EVEX_W_OPSIZE_KZ, /* 6489 */ IC_EVEX_W_OPSIZE_KZ, /* 6490 */ IC_EVEX_W_OPSIZE_KZ, /* 6491 */ IC_EVEX_W_OPSIZE_KZ, /* 6492 */ IC_EVEX_W_OPSIZE_KZ, /* 6493 */ IC_EVEX_W_OPSIZE_KZ, /* 6494 */ IC_EVEX_W_OPSIZE_KZ, /* 6495 */ IC_EVEX_KZ, /* 6496 */ IC_EVEX_KZ, /* 6497 */ IC_EVEX_XS_KZ, /* 6498 */ IC_EVEX_XS_KZ, /* 6499 */ IC_EVEX_XD_KZ, /* 6500 */ IC_EVEX_XD_KZ, /* 6501 */ IC_EVEX_XD_KZ, /* 6502 */ IC_EVEX_XD_KZ, /* 6503 */ IC_EVEX_W_KZ, /* 6504 */ IC_EVEX_W_KZ, /* 6505 */ IC_EVEX_W_XS_KZ, /* 6506 */ IC_EVEX_W_XS_KZ, /* 6507 */ IC_EVEX_W_XD_KZ, /* 6508 */ IC_EVEX_W_XD_KZ, /* 6509 */ IC_EVEX_W_XD_KZ, /* 6510 */ IC_EVEX_W_XD_KZ, /* 6511 */ IC_EVEX_OPSIZE_KZ, /* 6512 */ IC_EVEX_OPSIZE_KZ, /* 6513 */ IC_EVEX_OPSIZE_KZ, /* 6514 */ IC_EVEX_OPSIZE_KZ, /* 6515 */ IC_EVEX_OPSIZE_KZ, /* 6516 */ IC_EVEX_OPSIZE_KZ, /* 6517 */ IC_EVEX_OPSIZE_KZ, /* 6518 */ IC_EVEX_OPSIZE_KZ, /* 6519 */ IC_EVEX_W_OPSIZE_KZ, /* 6520 */ IC_EVEX_W_OPSIZE_KZ, /* 6521 */ IC_EVEX_W_OPSIZE_KZ, /* 6522 */ IC_EVEX_W_OPSIZE_KZ, /* 6523 */ IC_EVEX_W_OPSIZE_KZ, /* 6524 */ IC_EVEX_W_OPSIZE_KZ, /* 6525 */ IC_EVEX_W_OPSIZE_KZ, /* 6526 */ IC_EVEX_W_OPSIZE_KZ, /* 6527 */ IC_EVEX_KZ, /* 6528 */ IC_EVEX_KZ, /* 6529 */ IC_EVEX_XS_KZ, /* 6530 */ IC_EVEX_XS_KZ, /* 6531 */ IC_EVEX_XD_KZ, /* 6532 */ IC_EVEX_XD_KZ, /* 6533 */ IC_EVEX_XD_KZ, /* 6534 */ IC_EVEX_XD_KZ, /* 6535 */ IC_EVEX_W_KZ, /* 6536 */ IC_EVEX_W_KZ, /* 6537 */ IC_EVEX_W_XS_KZ, /* 6538 */ IC_EVEX_W_XS_KZ, /* 6539 */ IC_EVEX_W_XD_KZ, /* 6540 */ IC_EVEX_W_XD_KZ, /* 6541 */ IC_EVEX_W_XD_KZ, /* 6542 */ IC_EVEX_W_XD_KZ, /* 6543 */ IC_EVEX_OPSIZE_KZ, /* 6544 */ IC_EVEX_OPSIZE_KZ, /* 6545 */ IC_EVEX_OPSIZE_KZ, /* 6546 */ IC_EVEX_OPSIZE_KZ, /* 6547 */ IC_EVEX_OPSIZE_KZ, /* 6548 */ IC_EVEX_OPSIZE_KZ, /* 6549 */ IC_EVEX_OPSIZE_KZ, /* 6550 */ IC_EVEX_OPSIZE_KZ, /* 6551 */ IC_EVEX_W_OPSIZE_KZ, /* 6552 */ IC_EVEX_W_OPSIZE_KZ, /* 6553 */ IC_EVEX_W_OPSIZE_KZ, /* 6554 */ IC_EVEX_W_OPSIZE_KZ, /* 6555 */ IC_EVEX_W_OPSIZE_KZ, /* 6556 */ IC_EVEX_W_OPSIZE_KZ, /* 6557 */ IC_EVEX_W_OPSIZE_KZ, /* 6558 */ IC_EVEX_W_OPSIZE_KZ, /* 6559 */ IC_EVEX_KZ, /* 6560 */ IC_EVEX_KZ, /* 6561 */ IC_EVEX_XS_KZ, /* 6562 */ IC_EVEX_XS_KZ, /* 6563 */ IC_EVEX_XD_KZ, /* 6564 */ IC_EVEX_XD_KZ, /* 6565 */ IC_EVEX_XD_KZ, /* 6566 */ IC_EVEX_XD_KZ, /* 6567 */ IC_EVEX_W_KZ, /* 6568 */ IC_EVEX_W_KZ, /* 6569 */ IC_EVEX_W_XS_KZ, /* 6570 */ IC_EVEX_W_XS_KZ, /* 6571 */ IC_EVEX_W_XD_KZ, /* 6572 */ IC_EVEX_W_XD_KZ, /* 6573 */ IC_EVEX_W_XD_KZ, /* 6574 */ IC_EVEX_W_XD_KZ, /* 6575 */ IC_EVEX_OPSIZE_KZ, /* 6576 */ IC_EVEX_OPSIZE_KZ, /* 6577 */ IC_EVEX_OPSIZE_KZ, /* 6578 */ IC_EVEX_OPSIZE_KZ, /* 6579 */ IC_EVEX_OPSIZE_KZ, /* 6580 */ IC_EVEX_OPSIZE_KZ, /* 6581 */ IC_EVEX_OPSIZE_KZ, /* 6582 */ IC_EVEX_OPSIZE_KZ, /* 6583 */ IC_EVEX_W_OPSIZE_KZ, /* 6584 */ IC_EVEX_W_OPSIZE_KZ, /* 6585 */ IC_EVEX_W_OPSIZE_KZ, /* 6586 */ IC_EVEX_W_OPSIZE_KZ, /* 6587 */ IC_EVEX_W_OPSIZE_KZ, /* 6588 */ IC_EVEX_W_OPSIZE_KZ, /* 6589 */ IC_EVEX_W_OPSIZE_KZ, /* 6590 */ IC_EVEX_W_OPSIZE_KZ, /* 6591 */ IC_EVEX_KZ, /* 6592 */ IC_EVEX_KZ, /* 6593 */ IC_EVEX_XS_KZ, /* 6594 */ IC_EVEX_XS_KZ, /* 6595 */ IC_EVEX_XD_KZ, /* 6596 */ IC_EVEX_XD_KZ, /* 6597 */ IC_EVEX_XD_KZ, /* 6598 */ IC_EVEX_XD_KZ, /* 6599 */ IC_EVEX_W_KZ, /* 6600 */ IC_EVEX_W_KZ, /* 6601 */ IC_EVEX_W_XS_KZ, /* 6602 */ IC_EVEX_W_XS_KZ, /* 6603 */ IC_EVEX_W_XD_KZ, /* 6604 */ IC_EVEX_W_XD_KZ, /* 6605 */ IC_EVEX_W_XD_KZ, /* 6606 */ IC_EVEX_W_XD_KZ, /* 6607 */ IC_EVEX_OPSIZE_KZ, /* 6608 */ IC_EVEX_OPSIZE_KZ, /* 6609 */ IC_EVEX_OPSIZE_KZ, /* 6610 */ IC_EVEX_OPSIZE_KZ, /* 6611 */ IC_EVEX_OPSIZE_KZ, /* 6612 */ IC_EVEX_OPSIZE_KZ, /* 6613 */ IC_EVEX_OPSIZE_KZ, /* 6614 */ IC_EVEX_OPSIZE_KZ, /* 6615 */ IC_EVEX_W_OPSIZE_KZ, /* 6616 */ IC_EVEX_W_OPSIZE_KZ, /* 6617 */ IC_EVEX_W_OPSIZE_KZ, /* 6618 */ IC_EVEX_W_OPSIZE_KZ, /* 6619 */ IC_EVEX_W_OPSIZE_KZ, /* 6620 */ IC_EVEX_W_OPSIZE_KZ, /* 6621 */ IC_EVEX_W_OPSIZE_KZ, /* 6622 */ IC_EVEX_W_OPSIZE_KZ, /* 6623 */ IC_EVEX_KZ, /* 6624 */ IC_EVEX_KZ, /* 6625 */ IC_EVEX_XS_KZ, /* 6626 */ IC_EVEX_XS_KZ, /* 6627 */ IC_EVEX_XD_KZ, /* 6628 */ IC_EVEX_XD_KZ, /* 6629 */ IC_EVEX_XD_KZ, /* 6630 */ IC_EVEX_XD_KZ, /* 6631 */ IC_EVEX_W_KZ, /* 6632 */ IC_EVEX_W_KZ, /* 6633 */ IC_EVEX_W_XS_KZ, /* 6634 */ IC_EVEX_W_XS_KZ, /* 6635 */ IC_EVEX_W_XD_KZ, /* 6636 */ IC_EVEX_W_XD_KZ, /* 6637 */ IC_EVEX_W_XD_KZ, /* 6638 */ IC_EVEX_W_XD_KZ, /* 6639 */ IC_EVEX_OPSIZE_KZ, /* 6640 */ IC_EVEX_OPSIZE_KZ, /* 6641 */ IC_EVEX_OPSIZE_KZ, /* 6642 */ IC_EVEX_OPSIZE_KZ, /* 6643 */ IC_EVEX_OPSIZE_KZ, /* 6644 */ IC_EVEX_OPSIZE_KZ, /* 6645 */ IC_EVEX_OPSIZE_KZ, /* 6646 */ IC_EVEX_OPSIZE_KZ, /* 6647 */ IC_EVEX_W_OPSIZE_KZ, /* 6648 */ IC_EVEX_W_OPSIZE_KZ, /* 6649 */ IC_EVEX_W_OPSIZE_KZ, /* 6650 */ IC_EVEX_W_OPSIZE_KZ, /* 6651 */ IC_EVEX_W_OPSIZE_KZ, /* 6652 */ IC_EVEX_W_OPSIZE_KZ, /* 6653 */ IC_EVEX_W_OPSIZE_KZ, /* 6654 */ IC_EVEX_W_OPSIZE_KZ, /* 6655 */ IC, /* 6656 */ IC_64BIT, /* 6657 */ IC_XS, /* 6658 */ IC_64BIT_XS, /* 6659 */ IC_XD, /* 6660 */ IC_64BIT_XD, /* 6661 */ IC_XS, /* 6662 */ IC_64BIT_XS, /* 6663 */ IC, /* 6664 */ IC_64BIT_REXW, /* 6665 */ IC_XS, /* 6666 */ IC_64BIT_REXW_XS, /* 6667 */ IC_XD, /* 6668 */ IC_64BIT_REXW_XD, /* 6669 */ IC_XS, /* 6670 */ IC_64BIT_REXW_XS, /* 6671 */ IC_OPSIZE, /* 6672 */ IC_64BIT_OPSIZE, /* 6673 */ IC_XS_OPSIZE, /* 6674 */ IC_64BIT_XS_OPSIZE, /* 6675 */ IC_XD_OPSIZE, /* 6676 */ IC_64BIT_XD_OPSIZE, /* 6677 */ IC_XS_OPSIZE, /* 6678 */ IC_64BIT_XD_OPSIZE, /* 6679 */ IC_OPSIZE, /* 6680 */ IC_64BIT_REXW_OPSIZE, /* 6681 */ IC_XS_OPSIZE, /* 6682 */ IC_64BIT_REXW_XS, /* 6683 */ IC_XD_OPSIZE, /* 6684 */ IC_64BIT_REXW_XD, /* 6685 */ IC_XS_OPSIZE, /* 6686 */ IC_64BIT_REXW_XS, /* 6687 */ IC_ADSIZE, /* 6688 */ IC_64BIT_ADSIZE, /* 6689 */ IC_XS_ADSIZE, /* 6690 */ IC_64BIT_XS_ADSIZE, /* 6691 */ IC_XD_ADSIZE, /* 6692 */ IC_64BIT_XD_ADSIZE, /* 6693 */ IC_XS_ADSIZE, /* 6694 */ IC_64BIT_XD_ADSIZE, /* 6695 */ IC_ADSIZE, /* 6696 */ IC_64BIT_REXW_ADSIZE, /* 6697 */ IC_XS_ADSIZE, /* 6698 */ IC_64BIT_REXW_XS, /* 6699 */ IC_XD_ADSIZE, /* 6700 */ IC_64BIT_REXW_XD, /* 6701 */ IC_XS_ADSIZE, /* 6702 */ IC_64BIT_REXW_XS, /* 6703 */ IC_OPSIZE_ADSIZE, /* 6704 */ IC_64BIT_OPSIZE_ADSIZE, /* 6705 */ IC_XS_OPSIZE, /* 6706 */ IC_64BIT_XS_OPSIZE, /* 6707 */ IC_XD_OPSIZE, /* 6708 */ IC_64BIT_XD_OPSIZE, /* 6709 */ IC_XS_OPSIZE, /* 6710 */ IC_64BIT_XD_OPSIZE, /* 6711 */ IC_OPSIZE_ADSIZE, /* 6712 */ IC_64BIT_REXW_OPSIZE, /* 6713 */ IC_XS_OPSIZE, /* 6714 */ IC_64BIT_REXW_XS, /* 6715 */ IC_XD_OPSIZE, /* 6716 */ IC_64BIT_REXW_XD, /* 6717 */ IC_XS_OPSIZE, /* 6718 */ IC_64BIT_REXW_XS, /* 6719 */ IC_VEX, /* 6720 */ IC_VEX, /* 6721 */ IC_VEX_XS, /* 6722 */ IC_VEX_XS, /* 6723 */ IC_VEX_XD, /* 6724 */ IC_VEX_XD, /* 6725 */ IC_VEX_XD, /* 6726 */ IC_VEX_XD, /* 6727 */ IC_VEX_W, /* 6728 */ IC_VEX_W, /* 6729 */ IC_VEX_W_XS, /* 6730 */ IC_VEX_W_XS, /* 6731 */ IC_VEX_W_XD, /* 6732 */ IC_VEX_W_XD, /* 6733 */ IC_VEX_W_XD, /* 6734 */ IC_VEX_W_XD, /* 6735 */ IC_VEX_OPSIZE, /* 6736 */ IC_VEX_OPSIZE, /* 6737 */ IC_VEX_OPSIZE, /* 6738 */ IC_VEX_OPSIZE, /* 6739 */ IC_VEX_OPSIZE, /* 6740 */ IC_VEX_OPSIZE, /* 6741 */ IC_VEX_OPSIZE, /* 6742 */ IC_VEX_OPSIZE, /* 6743 */ IC_VEX_W_OPSIZE, /* 6744 */ IC_VEX_W_OPSIZE, /* 6745 */ IC_VEX_W_OPSIZE, /* 6746 */ IC_VEX_W_OPSIZE, /* 6747 */ IC_VEX_W_OPSIZE, /* 6748 */ IC_VEX_W_OPSIZE, /* 6749 */ IC_VEX_W_OPSIZE, /* 6750 */ IC_VEX_W_OPSIZE, /* 6751 */ IC_VEX, /* 6752 */ IC_VEX, /* 6753 */ IC_VEX_XS, /* 6754 */ IC_VEX_XS, /* 6755 */ IC_VEX_XD, /* 6756 */ IC_VEX_XD, /* 6757 */ IC_VEX_XD, /* 6758 */ IC_VEX_XD, /* 6759 */ IC_VEX_W, /* 6760 */ IC_VEX_W, /* 6761 */ IC_VEX_W_XS, /* 6762 */ IC_VEX_W_XS, /* 6763 */ IC_VEX_W_XD, /* 6764 */ IC_VEX_W_XD, /* 6765 */ IC_VEX_W_XD, /* 6766 */ IC_VEX_W_XD, /* 6767 */ IC_VEX_OPSIZE, /* 6768 */ IC_VEX_OPSIZE, /* 6769 */ IC_VEX_OPSIZE, /* 6770 */ IC_VEX_OPSIZE, /* 6771 */ IC_VEX_OPSIZE, /* 6772 */ IC_VEX_OPSIZE, /* 6773 */ IC_VEX_OPSIZE, /* 6774 */ IC_VEX_OPSIZE, /* 6775 */ IC_VEX_W_OPSIZE, /* 6776 */ IC_VEX_W_OPSIZE, /* 6777 */ IC_VEX_W_OPSIZE, /* 6778 */ IC_VEX_W_OPSIZE, /* 6779 */ IC_VEX_W_OPSIZE, /* 6780 */ IC_VEX_W_OPSIZE, /* 6781 */ IC_VEX_W_OPSIZE, /* 6782 */ IC_VEX_W_OPSIZE, /* 6783 */ IC_VEX_L, /* 6784 */ IC_VEX_L, /* 6785 */ IC_VEX_L_XS, /* 6786 */ IC_VEX_L_XS, /* 6787 */ IC_VEX_L_XD, /* 6788 */ IC_VEX_L_XD, /* 6789 */ IC_VEX_L_XD, /* 6790 */ IC_VEX_L_XD, /* 6791 */ IC_VEX_L_W, /* 6792 */ IC_VEX_L_W, /* 6793 */ IC_VEX_L_W_XS, /* 6794 */ IC_VEX_L_W_XS, /* 6795 */ IC_VEX_L_W_XD, /* 6796 */ IC_VEX_L_W_XD, /* 6797 */ IC_VEX_L_W_XD, /* 6798 */ IC_VEX_L_W_XD, /* 6799 */ IC_VEX_L_OPSIZE, /* 6800 */ IC_VEX_L_OPSIZE, /* 6801 */ IC_VEX_L_OPSIZE, /* 6802 */ IC_VEX_L_OPSIZE, /* 6803 */ IC_VEX_L_OPSIZE, /* 6804 */ IC_VEX_L_OPSIZE, /* 6805 */ IC_VEX_L_OPSIZE, /* 6806 */ IC_VEX_L_OPSIZE, /* 6807 */ IC_VEX_L_W_OPSIZE, /* 6808 */ IC_VEX_L_W_OPSIZE, /* 6809 */ IC_VEX_L_W_OPSIZE, /* 6810 */ IC_VEX_L_W_OPSIZE, /* 6811 */ IC_VEX_L_W_OPSIZE, /* 6812 */ IC_VEX_L_W_OPSIZE, /* 6813 */ IC_VEX_L_W_OPSIZE, /* 6814 */ IC_VEX_L_W_OPSIZE, /* 6815 */ IC_VEX_L, /* 6816 */ IC_VEX_L, /* 6817 */ IC_VEX_L_XS, /* 6818 */ IC_VEX_L_XS, /* 6819 */ IC_VEX_L_XD, /* 6820 */ IC_VEX_L_XD, /* 6821 */ IC_VEX_L_XD, /* 6822 */ IC_VEX_L_XD, /* 6823 */ IC_VEX_L_W, /* 6824 */ IC_VEX_L_W, /* 6825 */ IC_VEX_L_W_XS, /* 6826 */ IC_VEX_L_W_XS, /* 6827 */ IC_VEX_L_W_XD, /* 6828 */ IC_VEX_L_W_XD, /* 6829 */ IC_VEX_L_W_XD, /* 6830 */ IC_VEX_L_W_XD, /* 6831 */ IC_VEX_L_OPSIZE, /* 6832 */ IC_VEX_L_OPSIZE, /* 6833 */ IC_VEX_L_OPSIZE, /* 6834 */ IC_VEX_L_OPSIZE, /* 6835 */ IC_VEX_L_OPSIZE, /* 6836 */ IC_VEX_L_OPSIZE, /* 6837 */ IC_VEX_L_OPSIZE, /* 6838 */ IC_VEX_L_OPSIZE, /* 6839 */ IC_VEX_L_W_OPSIZE, /* 6840 */ IC_VEX_L_W_OPSIZE, /* 6841 */ IC_VEX_L_W_OPSIZE, /* 6842 */ IC_VEX_L_W_OPSIZE, /* 6843 */ IC_VEX_L_W_OPSIZE, /* 6844 */ IC_VEX_L_W_OPSIZE, /* 6845 */ IC_VEX_L_W_OPSIZE, /* 6846 */ IC_VEX_L_W_OPSIZE, /* 6847 */ IC_VEX_L, /* 6848 */ IC_VEX_L, /* 6849 */ IC_VEX_L_XS, /* 6850 */ IC_VEX_L_XS, /* 6851 */ IC_VEX_L_XD, /* 6852 */ IC_VEX_L_XD, /* 6853 */ IC_VEX_L_XD, /* 6854 */ IC_VEX_L_XD, /* 6855 */ IC_VEX_L_W, /* 6856 */ IC_VEX_L_W, /* 6857 */ IC_VEX_L_W_XS, /* 6858 */ IC_VEX_L_W_XS, /* 6859 */ IC_VEX_L_W_XD, /* 6860 */ IC_VEX_L_W_XD, /* 6861 */ IC_VEX_L_W_XD, /* 6862 */ IC_VEX_L_W_XD, /* 6863 */ IC_VEX_L_OPSIZE, /* 6864 */ IC_VEX_L_OPSIZE, /* 6865 */ IC_VEX_L_OPSIZE, /* 6866 */ IC_VEX_L_OPSIZE, /* 6867 */ IC_VEX_L_OPSIZE, /* 6868 */ IC_VEX_L_OPSIZE, /* 6869 */ IC_VEX_L_OPSIZE, /* 6870 */ IC_VEX_L_OPSIZE, /* 6871 */ IC_VEX_L_W_OPSIZE, /* 6872 */ IC_VEX_L_W_OPSIZE, /* 6873 */ IC_VEX_L_W_OPSIZE, /* 6874 */ IC_VEX_L_W_OPSIZE, /* 6875 */ IC_VEX_L_W_OPSIZE, /* 6876 */ IC_VEX_L_W_OPSIZE, /* 6877 */ IC_VEX_L_W_OPSIZE, /* 6878 */ IC_VEX_L_W_OPSIZE, /* 6879 */ IC_VEX_L, /* 6880 */ IC_VEX_L, /* 6881 */ IC_VEX_L_XS, /* 6882 */ IC_VEX_L_XS, /* 6883 */ IC_VEX_L_XD, /* 6884 */ IC_VEX_L_XD, /* 6885 */ IC_VEX_L_XD, /* 6886 */ IC_VEX_L_XD, /* 6887 */ IC_VEX_L_W, /* 6888 */ IC_VEX_L_W, /* 6889 */ IC_VEX_L_W_XS, /* 6890 */ IC_VEX_L_W_XS, /* 6891 */ IC_VEX_L_W_XD, /* 6892 */ IC_VEX_L_W_XD, /* 6893 */ IC_VEX_L_W_XD, /* 6894 */ IC_VEX_L_W_XD, /* 6895 */ IC_VEX_L_OPSIZE, /* 6896 */ IC_VEX_L_OPSIZE, /* 6897 */ IC_VEX_L_OPSIZE, /* 6898 */ IC_VEX_L_OPSIZE, /* 6899 */ IC_VEX_L_OPSIZE, /* 6900 */ IC_VEX_L_OPSIZE, /* 6901 */ IC_VEX_L_OPSIZE, /* 6902 */ IC_VEX_L_OPSIZE, /* 6903 */ IC_VEX_L_W_OPSIZE, /* 6904 */ IC_VEX_L_W_OPSIZE, /* 6905 */ IC_VEX_L_W_OPSIZE, /* 6906 */ IC_VEX_L_W_OPSIZE, /* 6907 */ IC_VEX_L_W_OPSIZE, /* 6908 */ IC_VEX_L_W_OPSIZE, /* 6909 */ IC_VEX_L_W_OPSIZE, /* 6910 */ IC_VEX_L_W_OPSIZE, /* 6911 */ IC_EVEX_L_KZ, /* 6912 */ IC_EVEX_L_KZ, /* 6913 */ IC_EVEX_L_XS_KZ, /* 6914 */ IC_EVEX_L_XS_KZ, /* 6915 */ IC_EVEX_L_XD_KZ, /* 6916 */ IC_EVEX_L_XD_KZ, /* 6917 */ IC_EVEX_L_XD_KZ, /* 6918 */ IC_EVEX_L_XD_KZ, /* 6919 */ IC_EVEX_L_W_KZ, /* 6920 */ IC_EVEX_L_W_KZ, /* 6921 */ IC_EVEX_L_W_XS_KZ, /* 6922 */ IC_EVEX_L_W_XS_KZ, /* 6923 */ IC_EVEX_L_W_XD_KZ, /* 6924 */ IC_EVEX_L_W_XD_KZ, /* 6925 */ IC_EVEX_L_W_XD_KZ, /* 6926 */ IC_EVEX_L_W_XD_KZ, /* 6927 */ IC_EVEX_L_OPSIZE_KZ, /* 6928 */ IC_EVEX_L_OPSIZE_KZ, /* 6929 */ IC_EVEX_L_OPSIZE_KZ, /* 6930 */ IC_EVEX_L_OPSIZE_KZ, /* 6931 */ IC_EVEX_L_OPSIZE_KZ, /* 6932 */ IC_EVEX_L_OPSIZE_KZ, /* 6933 */ IC_EVEX_L_OPSIZE_KZ, /* 6934 */ IC_EVEX_L_OPSIZE_KZ, /* 6935 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6936 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6937 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6938 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6939 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6940 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6941 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6942 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6943 */ IC_EVEX_L_KZ, /* 6944 */ IC_EVEX_L_KZ, /* 6945 */ IC_EVEX_L_XS_KZ, /* 6946 */ IC_EVEX_L_XS_KZ, /* 6947 */ IC_EVEX_L_XD_KZ, /* 6948 */ IC_EVEX_L_XD_KZ, /* 6949 */ IC_EVEX_L_XD_KZ, /* 6950 */ IC_EVEX_L_XD_KZ, /* 6951 */ IC_EVEX_L_W_KZ, /* 6952 */ IC_EVEX_L_W_KZ, /* 6953 */ IC_EVEX_L_W_XS_KZ, /* 6954 */ IC_EVEX_L_W_XS_KZ, /* 6955 */ IC_EVEX_L_W_XD_KZ, /* 6956 */ IC_EVEX_L_W_XD_KZ, /* 6957 */ IC_EVEX_L_W_XD_KZ, /* 6958 */ IC_EVEX_L_W_XD_KZ, /* 6959 */ IC_EVEX_L_OPSIZE_KZ, /* 6960 */ IC_EVEX_L_OPSIZE_KZ, /* 6961 */ IC_EVEX_L_OPSIZE_KZ, /* 6962 */ IC_EVEX_L_OPSIZE_KZ, /* 6963 */ IC_EVEX_L_OPSIZE_KZ, /* 6964 */ IC_EVEX_L_OPSIZE_KZ, /* 6965 */ IC_EVEX_L_OPSIZE_KZ, /* 6966 */ IC_EVEX_L_OPSIZE_KZ, /* 6967 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6968 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6969 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6970 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6971 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6972 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6973 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6974 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6975 */ IC_EVEX_L_KZ, /* 6976 */ IC_EVEX_L_KZ, /* 6977 */ IC_EVEX_L_XS_KZ, /* 6978 */ IC_EVEX_L_XS_KZ, /* 6979 */ IC_EVEX_L_XD_KZ, /* 6980 */ IC_EVEX_L_XD_KZ, /* 6981 */ IC_EVEX_L_XD_KZ, /* 6982 */ IC_EVEX_L_XD_KZ, /* 6983 */ IC_EVEX_L_W_KZ, /* 6984 */ IC_EVEX_L_W_KZ, /* 6985 */ IC_EVEX_L_W_XS_KZ, /* 6986 */ IC_EVEX_L_W_XS_KZ, /* 6987 */ IC_EVEX_L_W_XD_KZ, /* 6988 */ IC_EVEX_L_W_XD_KZ, /* 6989 */ IC_EVEX_L_W_XD_KZ, /* 6990 */ IC_EVEX_L_W_XD_KZ, /* 6991 */ IC_EVEX_L_OPSIZE_KZ, /* 6992 */ IC_EVEX_L_OPSIZE_KZ, /* 6993 */ IC_EVEX_L_OPSIZE_KZ, /* 6994 */ IC_EVEX_L_OPSIZE_KZ, /* 6995 */ IC_EVEX_L_OPSIZE_KZ, /* 6996 */ IC_EVEX_L_OPSIZE_KZ, /* 6997 */ IC_EVEX_L_OPSIZE_KZ, /* 6998 */ IC_EVEX_L_OPSIZE_KZ, /* 6999 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7000 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7001 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7002 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7003 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7004 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7005 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7006 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7007 */ IC_EVEX_L_KZ, /* 7008 */ IC_EVEX_L_KZ, /* 7009 */ IC_EVEX_L_XS_KZ, /* 7010 */ IC_EVEX_L_XS_KZ, /* 7011 */ IC_EVEX_L_XD_KZ, /* 7012 */ IC_EVEX_L_XD_KZ, /* 7013 */ IC_EVEX_L_XD_KZ, /* 7014 */ IC_EVEX_L_XD_KZ, /* 7015 */ IC_EVEX_L_W_KZ, /* 7016 */ IC_EVEX_L_W_KZ, /* 7017 */ IC_EVEX_L_W_XS_KZ, /* 7018 */ IC_EVEX_L_W_XS_KZ, /* 7019 */ IC_EVEX_L_W_XD_KZ, /* 7020 */ IC_EVEX_L_W_XD_KZ, /* 7021 */ IC_EVEX_L_W_XD_KZ, /* 7022 */ IC_EVEX_L_W_XD_KZ, /* 7023 */ IC_EVEX_L_OPSIZE_KZ, /* 7024 */ IC_EVEX_L_OPSIZE_KZ, /* 7025 */ IC_EVEX_L_OPSIZE_KZ, /* 7026 */ IC_EVEX_L_OPSIZE_KZ, /* 7027 */ IC_EVEX_L_OPSIZE_KZ, /* 7028 */ IC_EVEX_L_OPSIZE_KZ, /* 7029 */ IC_EVEX_L_OPSIZE_KZ, /* 7030 */ IC_EVEX_L_OPSIZE_KZ, /* 7031 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7032 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7033 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7034 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7035 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7036 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7037 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7038 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7039 */ IC_EVEX_L_KZ, /* 7040 */ IC_EVEX_L_KZ, /* 7041 */ IC_EVEX_L_XS_KZ, /* 7042 */ IC_EVEX_L_XS_KZ, /* 7043 */ IC_EVEX_L_XD_KZ, /* 7044 */ IC_EVEX_L_XD_KZ, /* 7045 */ IC_EVEX_L_XD_KZ, /* 7046 */ IC_EVEX_L_XD_KZ, /* 7047 */ IC_EVEX_L_W_KZ, /* 7048 */ IC_EVEX_L_W_KZ, /* 7049 */ IC_EVEX_L_W_XS_KZ, /* 7050 */ IC_EVEX_L_W_XS_KZ, /* 7051 */ IC_EVEX_L_W_XD_KZ, /* 7052 */ IC_EVEX_L_W_XD_KZ, /* 7053 */ IC_EVEX_L_W_XD_KZ, /* 7054 */ IC_EVEX_L_W_XD_KZ, /* 7055 */ IC_EVEX_L_OPSIZE_KZ, /* 7056 */ IC_EVEX_L_OPSIZE_KZ, /* 7057 */ IC_EVEX_L_OPSIZE_KZ, /* 7058 */ IC_EVEX_L_OPSIZE_KZ, /* 7059 */ IC_EVEX_L_OPSIZE_KZ, /* 7060 */ IC_EVEX_L_OPSIZE_KZ, /* 7061 */ IC_EVEX_L_OPSIZE_KZ, /* 7062 */ IC_EVEX_L_OPSIZE_KZ, /* 7063 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7064 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7065 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7066 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7067 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7068 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7069 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7070 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7071 */ IC_EVEX_L_KZ, /* 7072 */ IC_EVEX_L_KZ, /* 7073 */ IC_EVEX_L_XS_KZ, /* 7074 */ IC_EVEX_L_XS_KZ, /* 7075 */ IC_EVEX_L_XD_KZ, /* 7076 */ IC_EVEX_L_XD_KZ, /* 7077 */ IC_EVEX_L_XD_KZ, /* 7078 */ IC_EVEX_L_XD_KZ, /* 7079 */ IC_EVEX_L_W_KZ, /* 7080 */ IC_EVEX_L_W_KZ, /* 7081 */ IC_EVEX_L_W_XS_KZ, /* 7082 */ IC_EVEX_L_W_XS_KZ, /* 7083 */ IC_EVEX_L_W_XD_KZ, /* 7084 */ IC_EVEX_L_W_XD_KZ, /* 7085 */ IC_EVEX_L_W_XD_KZ, /* 7086 */ IC_EVEX_L_W_XD_KZ, /* 7087 */ IC_EVEX_L_OPSIZE_KZ, /* 7088 */ IC_EVEX_L_OPSIZE_KZ, /* 7089 */ IC_EVEX_L_OPSIZE_KZ, /* 7090 */ IC_EVEX_L_OPSIZE_KZ, /* 7091 */ IC_EVEX_L_OPSIZE_KZ, /* 7092 */ IC_EVEX_L_OPSIZE_KZ, /* 7093 */ IC_EVEX_L_OPSIZE_KZ, /* 7094 */ IC_EVEX_L_OPSIZE_KZ, /* 7095 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7096 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7097 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7098 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7099 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7100 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7101 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7102 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7103 */ IC_EVEX_L_KZ, /* 7104 */ IC_EVEX_L_KZ, /* 7105 */ IC_EVEX_L_XS_KZ, /* 7106 */ IC_EVEX_L_XS_KZ, /* 7107 */ IC_EVEX_L_XD_KZ, /* 7108 */ IC_EVEX_L_XD_KZ, /* 7109 */ IC_EVEX_L_XD_KZ, /* 7110 */ IC_EVEX_L_XD_KZ, /* 7111 */ IC_EVEX_L_W_KZ, /* 7112 */ IC_EVEX_L_W_KZ, /* 7113 */ IC_EVEX_L_W_XS_KZ, /* 7114 */ IC_EVEX_L_W_XS_KZ, /* 7115 */ IC_EVEX_L_W_XD_KZ, /* 7116 */ IC_EVEX_L_W_XD_KZ, /* 7117 */ IC_EVEX_L_W_XD_KZ, /* 7118 */ IC_EVEX_L_W_XD_KZ, /* 7119 */ IC_EVEX_L_OPSIZE_KZ, /* 7120 */ IC_EVEX_L_OPSIZE_KZ, /* 7121 */ IC_EVEX_L_OPSIZE_KZ, /* 7122 */ IC_EVEX_L_OPSIZE_KZ, /* 7123 */ IC_EVEX_L_OPSIZE_KZ, /* 7124 */ IC_EVEX_L_OPSIZE_KZ, /* 7125 */ IC_EVEX_L_OPSIZE_KZ, /* 7126 */ IC_EVEX_L_OPSIZE_KZ, /* 7127 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7128 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7129 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7130 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7131 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7132 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7133 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7134 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7135 */ IC_EVEX_L_KZ, /* 7136 */ IC_EVEX_L_KZ, /* 7137 */ IC_EVEX_L_XS_KZ, /* 7138 */ IC_EVEX_L_XS_KZ, /* 7139 */ IC_EVEX_L_XD_KZ, /* 7140 */ IC_EVEX_L_XD_KZ, /* 7141 */ IC_EVEX_L_XD_KZ, /* 7142 */ IC_EVEX_L_XD_KZ, /* 7143 */ IC_EVEX_L_W_KZ, /* 7144 */ IC_EVEX_L_W_KZ, /* 7145 */ IC_EVEX_L_W_XS_KZ, /* 7146 */ IC_EVEX_L_W_XS_KZ, /* 7147 */ IC_EVEX_L_W_XD_KZ, /* 7148 */ IC_EVEX_L_W_XD_KZ, /* 7149 */ IC_EVEX_L_W_XD_KZ, /* 7150 */ IC_EVEX_L_W_XD_KZ, /* 7151 */ IC_EVEX_L_OPSIZE_KZ, /* 7152 */ IC_EVEX_L_OPSIZE_KZ, /* 7153 */ IC_EVEX_L_OPSIZE_KZ, /* 7154 */ IC_EVEX_L_OPSIZE_KZ, /* 7155 */ IC_EVEX_L_OPSIZE_KZ, /* 7156 */ IC_EVEX_L_OPSIZE_KZ, /* 7157 */ IC_EVEX_L_OPSIZE_KZ, /* 7158 */ IC_EVEX_L_OPSIZE_KZ, /* 7159 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7160 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7161 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7162 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7163 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7164 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7165 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7166 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7167 */ IC, /* 7168 */ IC_64BIT, /* 7169 */ IC_XS, /* 7170 */ IC_64BIT_XS, /* 7171 */ IC_XD, /* 7172 */ IC_64BIT_XD, /* 7173 */ IC_XS, /* 7174 */ IC_64BIT_XS, /* 7175 */ IC, /* 7176 */ IC_64BIT_REXW, /* 7177 */ IC_XS, /* 7178 */ IC_64BIT_REXW_XS, /* 7179 */ IC_XD, /* 7180 */ IC_64BIT_REXW_XD, /* 7181 */ IC_XS, /* 7182 */ IC_64BIT_REXW_XS, /* 7183 */ IC_OPSIZE, /* 7184 */ IC_64BIT_OPSIZE, /* 7185 */ IC_XS_OPSIZE, /* 7186 */ IC_64BIT_XS_OPSIZE, /* 7187 */ IC_XD_OPSIZE, /* 7188 */ IC_64BIT_XD_OPSIZE, /* 7189 */ IC_XS_OPSIZE, /* 7190 */ IC_64BIT_XD_OPSIZE, /* 7191 */ IC_OPSIZE, /* 7192 */ IC_64BIT_REXW_OPSIZE, /* 7193 */ IC_XS_OPSIZE, /* 7194 */ IC_64BIT_REXW_XS, /* 7195 */ IC_XD_OPSIZE, /* 7196 */ IC_64BIT_REXW_XD, /* 7197 */ IC_XS_OPSIZE, /* 7198 */ IC_64BIT_REXW_XS, /* 7199 */ IC_ADSIZE, /* 7200 */ IC_64BIT_ADSIZE, /* 7201 */ IC_XS_ADSIZE, /* 7202 */ IC_64BIT_XS_ADSIZE, /* 7203 */ IC_XD_ADSIZE, /* 7204 */ IC_64BIT_XD_ADSIZE, /* 7205 */ IC_XS_ADSIZE, /* 7206 */ IC_64BIT_XD_ADSIZE, /* 7207 */ IC_ADSIZE, /* 7208 */ IC_64BIT_REXW_ADSIZE, /* 7209 */ IC_XS_ADSIZE, /* 7210 */ IC_64BIT_REXW_XS, /* 7211 */ IC_XD_ADSIZE, /* 7212 */ IC_64BIT_REXW_XD, /* 7213 */ IC_XS_ADSIZE, /* 7214 */ IC_64BIT_REXW_XS, /* 7215 */ IC_OPSIZE_ADSIZE, /* 7216 */ IC_64BIT_OPSIZE_ADSIZE, /* 7217 */ IC_XS_OPSIZE, /* 7218 */ IC_64BIT_XS_OPSIZE, /* 7219 */ IC_XD_OPSIZE, /* 7220 */ IC_64BIT_XD_OPSIZE, /* 7221 */ IC_XS_OPSIZE, /* 7222 */ IC_64BIT_XD_OPSIZE, /* 7223 */ IC_OPSIZE_ADSIZE, /* 7224 */ IC_64BIT_REXW_OPSIZE, /* 7225 */ IC_XS_OPSIZE, /* 7226 */ IC_64BIT_REXW_XS, /* 7227 */ IC_XD_OPSIZE, /* 7228 */ IC_64BIT_REXW_XD, /* 7229 */ IC_XS_OPSIZE, /* 7230 */ IC_64BIT_REXW_XS, /* 7231 */ IC_VEX, /* 7232 */ IC_VEX, /* 7233 */ IC_VEX_XS, /* 7234 */ IC_VEX_XS, /* 7235 */ IC_VEX_XD, /* 7236 */ IC_VEX_XD, /* 7237 */ IC_VEX_XD, /* 7238 */ IC_VEX_XD, /* 7239 */ IC_VEX_W, /* 7240 */ IC_VEX_W, /* 7241 */ IC_VEX_W_XS, /* 7242 */ IC_VEX_W_XS, /* 7243 */ IC_VEX_W_XD, /* 7244 */ IC_VEX_W_XD, /* 7245 */ IC_VEX_W_XD, /* 7246 */ IC_VEX_W_XD, /* 7247 */ IC_VEX_OPSIZE, /* 7248 */ IC_VEX_OPSIZE, /* 7249 */ IC_VEX_OPSIZE, /* 7250 */ IC_VEX_OPSIZE, /* 7251 */ IC_VEX_OPSIZE, /* 7252 */ IC_VEX_OPSIZE, /* 7253 */ IC_VEX_OPSIZE, /* 7254 */ IC_VEX_OPSIZE, /* 7255 */ IC_VEX_W_OPSIZE, /* 7256 */ IC_VEX_W_OPSIZE, /* 7257 */ IC_VEX_W_OPSIZE, /* 7258 */ IC_VEX_W_OPSIZE, /* 7259 */ IC_VEX_W_OPSIZE, /* 7260 */ IC_VEX_W_OPSIZE, /* 7261 */ IC_VEX_W_OPSIZE, /* 7262 */ IC_VEX_W_OPSIZE, /* 7263 */ IC_VEX, /* 7264 */ IC_VEX, /* 7265 */ IC_VEX_XS, /* 7266 */ IC_VEX_XS, /* 7267 */ IC_VEX_XD, /* 7268 */ IC_VEX_XD, /* 7269 */ IC_VEX_XD, /* 7270 */ IC_VEX_XD, /* 7271 */ IC_VEX_W, /* 7272 */ IC_VEX_W, /* 7273 */ IC_VEX_W_XS, /* 7274 */ IC_VEX_W_XS, /* 7275 */ IC_VEX_W_XD, /* 7276 */ IC_VEX_W_XD, /* 7277 */ IC_VEX_W_XD, /* 7278 */ IC_VEX_W_XD, /* 7279 */ IC_VEX_OPSIZE, /* 7280 */ IC_VEX_OPSIZE, /* 7281 */ IC_VEX_OPSIZE, /* 7282 */ IC_VEX_OPSIZE, /* 7283 */ IC_VEX_OPSIZE, /* 7284 */ IC_VEX_OPSIZE, /* 7285 */ IC_VEX_OPSIZE, /* 7286 */ IC_VEX_OPSIZE, /* 7287 */ IC_VEX_W_OPSIZE, /* 7288 */ IC_VEX_W_OPSIZE, /* 7289 */ IC_VEX_W_OPSIZE, /* 7290 */ IC_VEX_W_OPSIZE, /* 7291 */ IC_VEX_W_OPSIZE, /* 7292 */ IC_VEX_W_OPSIZE, /* 7293 */ IC_VEX_W_OPSIZE, /* 7294 */ IC_VEX_W_OPSIZE, /* 7295 */ IC_VEX_L, /* 7296 */ IC_VEX_L, /* 7297 */ IC_VEX_L_XS, /* 7298 */ IC_VEX_L_XS, /* 7299 */ IC_VEX_L_XD, /* 7300 */ IC_VEX_L_XD, /* 7301 */ IC_VEX_L_XD, /* 7302 */ IC_VEX_L_XD, /* 7303 */ IC_VEX_L_W, /* 7304 */ IC_VEX_L_W, /* 7305 */ IC_VEX_L_W_XS, /* 7306 */ IC_VEX_L_W_XS, /* 7307 */ IC_VEX_L_W_XD, /* 7308 */ IC_VEX_L_W_XD, /* 7309 */ IC_VEX_L_W_XD, /* 7310 */ IC_VEX_L_W_XD, /* 7311 */ IC_VEX_L_OPSIZE, /* 7312 */ IC_VEX_L_OPSIZE, /* 7313 */ IC_VEX_L_OPSIZE, /* 7314 */ IC_VEX_L_OPSIZE, /* 7315 */ IC_VEX_L_OPSIZE, /* 7316 */ IC_VEX_L_OPSIZE, /* 7317 */ IC_VEX_L_OPSIZE, /* 7318 */ IC_VEX_L_OPSIZE, /* 7319 */ IC_VEX_L_W_OPSIZE, /* 7320 */ IC_VEX_L_W_OPSIZE, /* 7321 */ IC_VEX_L_W_OPSIZE, /* 7322 */ IC_VEX_L_W_OPSIZE, /* 7323 */ IC_VEX_L_W_OPSIZE, /* 7324 */ IC_VEX_L_W_OPSIZE, /* 7325 */ IC_VEX_L_W_OPSIZE, /* 7326 */ IC_VEX_L_W_OPSIZE, /* 7327 */ IC_VEX_L, /* 7328 */ IC_VEX_L, /* 7329 */ IC_VEX_L_XS, /* 7330 */ IC_VEX_L_XS, /* 7331 */ IC_VEX_L_XD, /* 7332 */ IC_VEX_L_XD, /* 7333 */ IC_VEX_L_XD, /* 7334 */ IC_VEX_L_XD, /* 7335 */ IC_VEX_L_W, /* 7336 */ IC_VEX_L_W, /* 7337 */ IC_VEX_L_W_XS, /* 7338 */ IC_VEX_L_W_XS, /* 7339 */ IC_VEX_L_W_XD, /* 7340 */ IC_VEX_L_W_XD, /* 7341 */ IC_VEX_L_W_XD, /* 7342 */ IC_VEX_L_W_XD, /* 7343 */ IC_VEX_L_OPSIZE, /* 7344 */ IC_VEX_L_OPSIZE, /* 7345 */ IC_VEX_L_OPSIZE, /* 7346 */ IC_VEX_L_OPSIZE, /* 7347 */ IC_VEX_L_OPSIZE, /* 7348 */ IC_VEX_L_OPSIZE, /* 7349 */ IC_VEX_L_OPSIZE, /* 7350 */ IC_VEX_L_OPSIZE, /* 7351 */ IC_VEX_L_W_OPSIZE, /* 7352 */ IC_VEX_L_W_OPSIZE, /* 7353 */ IC_VEX_L_W_OPSIZE, /* 7354 */ IC_VEX_L_W_OPSIZE, /* 7355 */ IC_VEX_L_W_OPSIZE, /* 7356 */ IC_VEX_L_W_OPSIZE, /* 7357 */ IC_VEX_L_W_OPSIZE, /* 7358 */ IC_VEX_L_W_OPSIZE, /* 7359 */ IC_VEX_L, /* 7360 */ IC_VEX_L, /* 7361 */ IC_VEX_L_XS, /* 7362 */ IC_VEX_L_XS, /* 7363 */ IC_VEX_L_XD, /* 7364 */ IC_VEX_L_XD, /* 7365 */ IC_VEX_L_XD, /* 7366 */ IC_VEX_L_XD, /* 7367 */ IC_VEX_L_W, /* 7368 */ IC_VEX_L_W, /* 7369 */ IC_VEX_L_W_XS, /* 7370 */ IC_VEX_L_W_XS, /* 7371 */ IC_VEX_L_W_XD, /* 7372 */ IC_VEX_L_W_XD, /* 7373 */ IC_VEX_L_W_XD, /* 7374 */ IC_VEX_L_W_XD, /* 7375 */ IC_VEX_L_OPSIZE, /* 7376 */ IC_VEX_L_OPSIZE, /* 7377 */ IC_VEX_L_OPSIZE, /* 7378 */ IC_VEX_L_OPSIZE, /* 7379 */ IC_VEX_L_OPSIZE, /* 7380 */ IC_VEX_L_OPSIZE, /* 7381 */ IC_VEX_L_OPSIZE, /* 7382 */ IC_VEX_L_OPSIZE, /* 7383 */ IC_VEX_L_W_OPSIZE, /* 7384 */ IC_VEX_L_W_OPSIZE, /* 7385 */ IC_VEX_L_W_OPSIZE, /* 7386 */ IC_VEX_L_W_OPSIZE, /* 7387 */ IC_VEX_L_W_OPSIZE, /* 7388 */ IC_VEX_L_W_OPSIZE, /* 7389 */ IC_VEX_L_W_OPSIZE, /* 7390 */ IC_VEX_L_W_OPSIZE, /* 7391 */ IC_VEX_L, /* 7392 */ IC_VEX_L, /* 7393 */ IC_VEX_L_XS, /* 7394 */ IC_VEX_L_XS, /* 7395 */ IC_VEX_L_XD, /* 7396 */ IC_VEX_L_XD, /* 7397 */ IC_VEX_L_XD, /* 7398 */ IC_VEX_L_XD, /* 7399 */ IC_VEX_L_W, /* 7400 */ IC_VEX_L_W, /* 7401 */ IC_VEX_L_W_XS, /* 7402 */ IC_VEX_L_W_XS, /* 7403 */ IC_VEX_L_W_XD, /* 7404 */ IC_VEX_L_W_XD, /* 7405 */ IC_VEX_L_W_XD, /* 7406 */ IC_VEX_L_W_XD, /* 7407 */ IC_VEX_L_OPSIZE, /* 7408 */ IC_VEX_L_OPSIZE, /* 7409 */ IC_VEX_L_OPSIZE, /* 7410 */ IC_VEX_L_OPSIZE, /* 7411 */ IC_VEX_L_OPSIZE, /* 7412 */ IC_VEX_L_OPSIZE, /* 7413 */ IC_VEX_L_OPSIZE, /* 7414 */ IC_VEX_L_OPSIZE, /* 7415 */ IC_VEX_L_W_OPSIZE, /* 7416 */ IC_VEX_L_W_OPSIZE, /* 7417 */ IC_VEX_L_W_OPSIZE, /* 7418 */ IC_VEX_L_W_OPSIZE, /* 7419 */ IC_VEX_L_W_OPSIZE, /* 7420 */ IC_VEX_L_W_OPSIZE, /* 7421 */ IC_VEX_L_W_OPSIZE, /* 7422 */ IC_VEX_L_W_OPSIZE, /* 7423 */ IC_EVEX_L2_KZ, /* 7424 */ IC_EVEX_L2_KZ, /* 7425 */ IC_EVEX_L2_XS_KZ, /* 7426 */ IC_EVEX_L2_XS_KZ, /* 7427 */ IC_EVEX_L2_XD_KZ, /* 7428 */ IC_EVEX_L2_XD_KZ, /* 7429 */ IC_EVEX_L2_XD_KZ, /* 7430 */ IC_EVEX_L2_XD_KZ, /* 7431 */ IC_EVEX_L2_W_KZ, /* 7432 */ IC_EVEX_L2_W_KZ, /* 7433 */ IC_EVEX_L2_W_XS_KZ, /* 7434 */ IC_EVEX_L2_W_XS_KZ, /* 7435 */ IC_EVEX_L2_W_XD_KZ, /* 7436 */ IC_EVEX_L2_W_XD_KZ, /* 7437 */ IC_EVEX_L2_W_XD_KZ, /* 7438 */ IC_EVEX_L2_W_XD_KZ, /* 7439 */ IC_EVEX_L2_OPSIZE_KZ, /* 7440 */ IC_EVEX_L2_OPSIZE_KZ, /* 7441 */ IC_EVEX_L2_OPSIZE_KZ, /* 7442 */ IC_EVEX_L2_OPSIZE_KZ, /* 7443 */ IC_EVEX_L2_OPSIZE_KZ, /* 7444 */ IC_EVEX_L2_OPSIZE_KZ, /* 7445 */ IC_EVEX_L2_OPSIZE_KZ, /* 7446 */ IC_EVEX_L2_OPSIZE_KZ, /* 7447 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7448 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7449 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7450 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7451 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7452 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7453 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7454 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7455 */ IC_EVEX_L2_KZ, /* 7456 */ IC_EVEX_L2_KZ, /* 7457 */ IC_EVEX_L2_XS_KZ, /* 7458 */ IC_EVEX_L2_XS_KZ, /* 7459 */ IC_EVEX_L2_XD_KZ, /* 7460 */ IC_EVEX_L2_XD_KZ, /* 7461 */ IC_EVEX_L2_XD_KZ, /* 7462 */ IC_EVEX_L2_XD_KZ, /* 7463 */ IC_EVEX_L2_W_KZ, /* 7464 */ IC_EVEX_L2_W_KZ, /* 7465 */ IC_EVEX_L2_W_XS_KZ, /* 7466 */ IC_EVEX_L2_W_XS_KZ, /* 7467 */ IC_EVEX_L2_W_XD_KZ, /* 7468 */ IC_EVEX_L2_W_XD_KZ, /* 7469 */ IC_EVEX_L2_W_XD_KZ, /* 7470 */ IC_EVEX_L2_W_XD_KZ, /* 7471 */ IC_EVEX_L2_OPSIZE_KZ, /* 7472 */ IC_EVEX_L2_OPSIZE_KZ, /* 7473 */ IC_EVEX_L2_OPSIZE_KZ, /* 7474 */ IC_EVEX_L2_OPSIZE_KZ, /* 7475 */ IC_EVEX_L2_OPSIZE_KZ, /* 7476 */ IC_EVEX_L2_OPSIZE_KZ, /* 7477 */ IC_EVEX_L2_OPSIZE_KZ, /* 7478 */ IC_EVEX_L2_OPSIZE_KZ, /* 7479 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7480 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7481 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7482 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7483 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7484 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7485 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7486 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7487 */ IC_EVEX_L2_KZ, /* 7488 */ IC_EVEX_L2_KZ, /* 7489 */ IC_EVEX_L2_XS_KZ, /* 7490 */ IC_EVEX_L2_XS_KZ, /* 7491 */ IC_EVEX_L2_XD_KZ, /* 7492 */ IC_EVEX_L2_XD_KZ, /* 7493 */ IC_EVEX_L2_XD_KZ, /* 7494 */ IC_EVEX_L2_XD_KZ, /* 7495 */ IC_EVEX_L2_W_KZ, /* 7496 */ IC_EVEX_L2_W_KZ, /* 7497 */ IC_EVEX_L2_W_XS_KZ, /* 7498 */ IC_EVEX_L2_W_XS_KZ, /* 7499 */ IC_EVEX_L2_W_XD_KZ, /* 7500 */ IC_EVEX_L2_W_XD_KZ, /* 7501 */ IC_EVEX_L2_W_XD_KZ, /* 7502 */ IC_EVEX_L2_W_XD_KZ, /* 7503 */ IC_EVEX_L2_OPSIZE_KZ, /* 7504 */ IC_EVEX_L2_OPSIZE_KZ, /* 7505 */ IC_EVEX_L2_OPSIZE_KZ, /* 7506 */ IC_EVEX_L2_OPSIZE_KZ, /* 7507 */ IC_EVEX_L2_OPSIZE_KZ, /* 7508 */ IC_EVEX_L2_OPSIZE_KZ, /* 7509 */ IC_EVEX_L2_OPSIZE_KZ, /* 7510 */ IC_EVEX_L2_OPSIZE_KZ, /* 7511 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7512 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7513 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7514 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7515 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7516 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7517 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7518 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7519 */ IC_EVEX_L2_KZ, /* 7520 */ IC_EVEX_L2_KZ, /* 7521 */ IC_EVEX_L2_XS_KZ, /* 7522 */ IC_EVEX_L2_XS_KZ, /* 7523 */ IC_EVEX_L2_XD_KZ, /* 7524 */ IC_EVEX_L2_XD_KZ, /* 7525 */ IC_EVEX_L2_XD_KZ, /* 7526 */ IC_EVEX_L2_XD_KZ, /* 7527 */ IC_EVEX_L2_W_KZ, /* 7528 */ IC_EVEX_L2_W_KZ, /* 7529 */ IC_EVEX_L2_W_XS_KZ, /* 7530 */ IC_EVEX_L2_W_XS_KZ, /* 7531 */ IC_EVEX_L2_W_XD_KZ, /* 7532 */ IC_EVEX_L2_W_XD_KZ, /* 7533 */ IC_EVEX_L2_W_XD_KZ, /* 7534 */ IC_EVEX_L2_W_XD_KZ, /* 7535 */ IC_EVEX_L2_OPSIZE_KZ, /* 7536 */ IC_EVEX_L2_OPSIZE_KZ, /* 7537 */ IC_EVEX_L2_OPSIZE_KZ, /* 7538 */ IC_EVEX_L2_OPSIZE_KZ, /* 7539 */ IC_EVEX_L2_OPSIZE_KZ, /* 7540 */ IC_EVEX_L2_OPSIZE_KZ, /* 7541 */ IC_EVEX_L2_OPSIZE_KZ, /* 7542 */ IC_EVEX_L2_OPSIZE_KZ, /* 7543 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7544 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7545 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7546 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7547 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7548 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7549 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7550 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7551 */ IC_EVEX_L2_KZ, /* 7552 */ IC_EVEX_L2_KZ, /* 7553 */ IC_EVEX_L2_XS_KZ, /* 7554 */ IC_EVEX_L2_XS_KZ, /* 7555 */ IC_EVEX_L2_XD_KZ, /* 7556 */ IC_EVEX_L2_XD_KZ, /* 7557 */ IC_EVEX_L2_XD_KZ, /* 7558 */ IC_EVEX_L2_XD_KZ, /* 7559 */ IC_EVEX_L2_W_KZ, /* 7560 */ IC_EVEX_L2_W_KZ, /* 7561 */ IC_EVEX_L2_W_XS_KZ, /* 7562 */ IC_EVEX_L2_W_XS_KZ, /* 7563 */ IC_EVEX_L2_W_XD_KZ, /* 7564 */ IC_EVEX_L2_W_XD_KZ, /* 7565 */ IC_EVEX_L2_W_XD_KZ, /* 7566 */ IC_EVEX_L2_W_XD_KZ, /* 7567 */ IC_EVEX_L2_OPSIZE_KZ, /* 7568 */ IC_EVEX_L2_OPSIZE_KZ, /* 7569 */ IC_EVEX_L2_OPSIZE_KZ, /* 7570 */ IC_EVEX_L2_OPSIZE_KZ, /* 7571 */ IC_EVEX_L2_OPSIZE_KZ, /* 7572 */ IC_EVEX_L2_OPSIZE_KZ, /* 7573 */ IC_EVEX_L2_OPSIZE_KZ, /* 7574 */ IC_EVEX_L2_OPSIZE_KZ, /* 7575 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7576 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7577 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7578 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7579 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7580 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7581 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7582 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7583 */ IC_EVEX_L2_KZ, /* 7584 */ IC_EVEX_L2_KZ, /* 7585 */ IC_EVEX_L2_XS_KZ, /* 7586 */ IC_EVEX_L2_XS_KZ, /* 7587 */ IC_EVEX_L2_XD_KZ, /* 7588 */ IC_EVEX_L2_XD_KZ, /* 7589 */ IC_EVEX_L2_XD_KZ, /* 7590 */ IC_EVEX_L2_XD_KZ, /* 7591 */ IC_EVEX_L2_W_KZ, /* 7592 */ IC_EVEX_L2_W_KZ, /* 7593 */ IC_EVEX_L2_W_XS_KZ, /* 7594 */ IC_EVEX_L2_W_XS_KZ, /* 7595 */ IC_EVEX_L2_W_XD_KZ, /* 7596 */ IC_EVEX_L2_W_XD_KZ, /* 7597 */ IC_EVEX_L2_W_XD_KZ, /* 7598 */ IC_EVEX_L2_W_XD_KZ, /* 7599 */ IC_EVEX_L2_OPSIZE_KZ, /* 7600 */ IC_EVEX_L2_OPSIZE_KZ, /* 7601 */ IC_EVEX_L2_OPSIZE_KZ, /* 7602 */ IC_EVEX_L2_OPSIZE_KZ, /* 7603 */ IC_EVEX_L2_OPSIZE_KZ, /* 7604 */ IC_EVEX_L2_OPSIZE_KZ, /* 7605 */ IC_EVEX_L2_OPSIZE_KZ, /* 7606 */ IC_EVEX_L2_OPSIZE_KZ, /* 7607 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7608 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7609 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7610 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7611 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7612 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7613 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7614 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7615 */ IC_EVEX_L2_KZ, /* 7616 */ IC_EVEX_L2_KZ, /* 7617 */ IC_EVEX_L2_XS_KZ, /* 7618 */ IC_EVEX_L2_XS_KZ, /* 7619 */ IC_EVEX_L2_XD_KZ, /* 7620 */ IC_EVEX_L2_XD_KZ, /* 7621 */ IC_EVEX_L2_XD_KZ, /* 7622 */ IC_EVEX_L2_XD_KZ, /* 7623 */ IC_EVEX_L2_W_KZ, /* 7624 */ IC_EVEX_L2_W_KZ, /* 7625 */ IC_EVEX_L2_W_XS_KZ, /* 7626 */ IC_EVEX_L2_W_XS_KZ, /* 7627 */ IC_EVEX_L2_W_XD_KZ, /* 7628 */ IC_EVEX_L2_W_XD_KZ, /* 7629 */ IC_EVEX_L2_W_XD_KZ, /* 7630 */ IC_EVEX_L2_W_XD_KZ, /* 7631 */ IC_EVEX_L2_OPSIZE_KZ, /* 7632 */ IC_EVEX_L2_OPSIZE_KZ, /* 7633 */ IC_EVEX_L2_OPSIZE_KZ, /* 7634 */ IC_EVEX_L2_OPSIZE_KZ, /* 7635 */ IC_EVEX_L2_OPSIZE_KZ, /* 7636 */ IC_EVEX_L2_OPSIZE_KZ, /* 7637 */ IC_EVEX_L2_OPSIZE_KZ, /* 7638 */ IC_EVEX_L2_OPSIZE_KZ, /* 7639 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7640 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7641 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7642 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7643 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7644 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7645 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7646 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7647 */ IC_EVEX_L2_KZ, /* 7648 */ IC_EVEX_L2_KZ, /* 7649 */ IC_EVEX_L2_XS_KZ, /* 7650 */ IC_EVEX_L2_XS_KZ, /* 7651 */ IC_EVEX_L2_XD_KZ, /* 7652 */ IC_EVEX_L2_XD_KZ, /* 7653 */ IC_EVEX_L2_XD_KZ, /* 7654 */ IC_EVEX_L2_XD_KZ, /* 7655 */ IC_EVEX_L2_W_KZ, /* 7656 */ IC_EVEX_L2_W_KZ, /* 7657 */ IC_EVEX_L2_W_XS_KZ, /* 7658 */ IC_EVEX_L2_W_XS_KZ, /* 7659 */ IC_EVEX_L2_W_XD_KZ, /* 7660 */ IC_EVEX_L2_W_XD_KZ, /* 7661 */ IC_EVEX_L2_W_XD_KZ, /* 7662 */ IC_EVEX_L2_W_XD_KZ, /* 7663 */ IC_EVEX_L2_OPSIZE_KZ, /* 7664 */ IC_EVEX_L2_OPSIZE_KZ, /* 7665 */ IC_EVEX_L2_OPSIZE_KZ, /* 7666 */ IC_EVEX_L2_OPSIZE_KZ, /* 7667 */ IC_EVEX_L2_OPSIZE_KZ, /* 7668 */ IC_EVEX_L2_OPSIZE_KZ, /* 7669 */ IC_EVEX_L2_OPSIZE_KZ, /* 7670 */ IC_EVEX_L2_OPSIZE_KZ, /* 7671 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7672 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7673 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7674 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7675 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7676 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7677 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7678 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7679 */ IC, /* 7680 */ IC_64BIT, /* 7681 */ IC_XS, /* 7682 */ IC_64BIT_XS, /* 7683 */ IC_XD, /* 7684 */ IC_64BIT_XD, /* 7685 */ IC_XS, /* 7686 */ IC_64BIT_XS, /* 7687 */ IC, /* 7688 */ IC_64BIT_REXW, /* 7689 */ IC_XS, /* 7690 */ IC_64BIT_REXW_XS, /* 7691 */ IC_XD, /* 7692 */ IC_64BIT_REXW_XD, /* 7693 */ IC_XS, /* 7694 */ IC_64BIT_REXW_XS, /* 7695 */ IC_OPSIZE, /* 7696 */ IC_64BIT_OPSIZE, /* 7697 */ IC_XS_OPSIZE, /* 7698 */ IC_64BIT_XS_OPSIZE, /* 7699 */ IC_XD_OPSIZE, /* 7700 */ IC_64BIT_XD_OPSIZE, /* 7701 */ IC_XS_OPSIZE, /* 7702 */ IC_64BIT_XD_OPSIZE, /* 7703 */ IC_OPSIZE, /* 7704 */ IC_64BIT_REXW_OPSIZE, /* 7705 */ IC_XS_OPSIZE, /* 7706 */ IC_64BIT_REXW_XS, /* 7707 */ IC_XD_OPSIZE, /* 7708 */ IC_64BIT_REXW_XD, /* 7709 */ IC_XS_OPSIZE, /* 7710 */ IC_64BIT_REXW_XS, /* 7711 */ IC_ADSIZE, /* 7712 */ IC_64BIT_ADSIZE, /* 7713 */ IC_XS_ADSIZE, /* 7714 */ IC_64BIT_XS_ADSIZE, /* 7715 */ IC_XD_ADSIZE, /* 7716 */ IC_64BIT_XD_ADSIZE, /* 7717 */ IC_XS_ADSIZE, /* 7718 */ IC_64BIT_XD_ADSIZE, /* 7719 */ IC_ADSIZE, /* 7720 */ IC_64BIT_REXW_ADSIZE, /* 7721 */ IC_XS_ADSIZE, /* 7722 */ IC_64BIT_REXW_XS, /* 7723 */ IC_XD_ADSIZE, /* 7724 */ IC_64BIT_REXW_XD, /* 7725 */ IC_XS_ADSIZE, /* 7726 */ IC_64BIT_REXW_XS, /* 7727 */ IC_OPSIZE_ADSIZE, /* 7728 */ IC_64BIT_OPSIZE_ADSIZE, /* 7729 */ IC_XS_OPSIZE, /* 7730 */ IC_64BIT_XS_OPSIZE, /* 7731 */ IC_XD_OPSIZE, /* 7732 */ IC_64BIT_XD_OPSIZE, /* 7733 */ IC_XS_OPSIZE, /* 7734 */ IC_64BIT_XD_OPSIZE, /* 7735 */ IC_OPSIZE_ADSIZE, /* 7736 */ IC_64BIT_REXW_OPSIZE, /* 7737 */ IC_XS_OPSIZE, /* 7738 */ IC_64BIT_REXW_XS, /* 7739 */ IC_XD_OPSIZE, /* 7740 */ IC_64BIT_REXW_XD, /* 7741 */ IC_XS_OPSIZE, /* 7742 */ IC_64BIT_REXW_XS, /* 7743 */ IC_VEX, /* 7744 */ IC_VEX, /* 7745 */ IC_VEX_XS, /* 7746 */ IC_VEX_XS, /* 7747 */ IC_VEX_XD, /* 7748 */ IC_VEX_XD, /* 7749 */ IC_VEX_XD, /* 7750 */ IC_VEX_XD, /* 7751 */ IC_VEX_W, /* 7752 */ IC_VEX_W, /* 7753 */ IC_VEX_W_XS, /* 7754 */ IC_VEX_W_XS, /* 7755 */ IC_VEX_W_XD, /* 7756 */ IC_VEX_W_XD, /* 7757 */ IC_VEX_W_XD, /* 7758 */ IC_VEX_W_XD, /* 7759 */ IC_VEX_OPSIZE, /* 7760 */ IC_VEX_OPSIZE, /* 7761 */ IC_VEX_OPSIZE, /* 7762 */ IC_VEX_OPSIZE, /* 7763 */ IC_VEX_OPSIZE, /* 7764 */ IC_VEX_OPSIZE, /* 7765 */ IC_VEX_OPSIZE, /* 7766 */ IC_VEX_OPSIZE, /* 7767 */ IC_VEX_W_OPSIZE, /* 7768 */ IC_VEX_W_OPSIZE, /* 7769 */ IC_VEX_W_OPSIZE, /* 7770 */ IC_VEX_W_OPSIZE, /* 7771 */ IC_VEX_W_OPSIZE, /* 7772 */ IC_VEX_W_OPSIZE, /* 7773 */ IC_VEX_W_OPSIZE, /* 7774 */ IC_VEX_W_OPSIZE, /* 7775 */ IC_VEX, /* 7776 */ IC_VEX, /* 7777 */ IC_VEX_XS, /* 7778 */ IC_VEX_XS, /* 7779 */ IC_VEX_XD, /* 7780 */ IC_VEX_XD, /* 7781 */ IC_VEX_XD, /* 7782 */ IC_VEX_XD, /* 7783 */ IC_VEX_W, /* 7784 */ IC_VEX_W, /* 7785 */ IC_VEX_W_XS, /* 7786 */ IC_VEX_W_XS, /* 7787 */ IC_VEX_W_XD, /* 7788 */ IC_VEX_W_XD, /* 7789 */ IC_VEX_W_XD, /* 7790 */ IC_VEX_W_XD, /* 7791 */ IC_VEX_OPSIZE, /* 7792 */ IC_VEX_OPSIZE, /* 7793 */ IC_VEX_OPSIZE, /* 7794 */ IC_VEX_OPSIZE, /* 7795 */ IC_VEX_OPSIZE, /* 7796 */ IC_VEX_OPSIZE, /* 7797 */ IC_VEX_OPSIZE, /* 7798 */ IC_VEX_OPSIZE, /* 7799 */ IC_VEX_W_OPSIZE, /* 7800 */ IC_VEX_W_OPSIZE, /* 7801 */ IC_VEX_W_OPSIZE, /* 7802 */ IC_VEX_W_OPSIZE, /* 7803 */ IC_VEX_W_OPSIZE, /* 7804 */ IC_VEX_W_OPSIZE, /* 7805 */ IC_VEX_W_OPSIZE, /* 7806 */ IC_VEX_W_OPSIZE, /* 7807 */ IC_VEX_L, /* 7808 */ IC_VEX_L, /* 7809 */ IC_VEX_L_XS, /* 7810 */ IC_VEX_L_XS, /* 7811 */ IC_VEX_L_XD, /* 7812 */ IC_VEX_L_XD, /* 7813 */ IC_VEX_L_XD, /* 7814 */ IC_VEX_L_XD, /* 7815 */ IC_VEX_L_W, /* 7816 */ IC_VEX_L_W, /* 7817 */ IC_VEX_L_W_XS, /* 7818 */ IC_VEX_L_W_XS, /* 7819 */ IC_VEX_L_W_XD, /* 7820 */ IC_VEX_L_W_XD, /* 7821 */ IC_VEX_L_W_XD, /* 7822 */ IC_VEX_L_W_XD, /* 7823 */ IC_VEX_L_OPSIZE, /* 7824 */ IC_VEX_L_OPSIZE, /* 7825 */ IC_VEX_L_OPSIZE, /* 7826 */ IC_VEX_L_OPSIZE, /* 7827 */ IC_VEX_L_OPSIZE, /* 7828 */ IC_VEX_L_OPSIZE, /* 7829 */ IC_VEX_L_OPSIZE, /* 7830 */ IC_VEX_L_OPSIZE, /* 7831 */ IC_VEX_L_W_OPSIZE, /* 7832 */ IC_VEX_L_W_OPSIZE, /* 7833 */ IC_VEX_L_W_OPSIZE, /* 7834 */ IC_VEX_L_W_OPSIZE, /* 7835 */ IC_VEX_L_W_OPSIZE, /* 7836 */ IC_VEX_L_W_OPSIZE, /* 7837 */ IC_VEX_L_W_OPSIZE, /* 7838 */ IC_VEX_L_W_OPSIZE, /* 7839 */ IC_VEX_L, /* 7840 */ IC_VEX_L, /* 7841 */ IC_VEX_L_XS, /* 7842 */ IC_VEX_L_XS, /* 7843 */ IC_VEX_L_XD, /* 7844 */ IC_VEX_L_XD, /* 7845 */ IC_VEX_L_XD, /* 7846 */ IC_VEX_L_XD, /* 7847 */ IC_VEX_L_W, /* 7848 */ IC_VEX_L_W, /* 7849 */ IC_VEX_L_W_XS, /* 7850 */ IC_VEX_L_W_XS, /* 7851 */ IC_VEX_L_W_XD, /* 7852 */ IC_VEX_L_W_XD, /* 7853 */ IC_VEX_L_W_XD, /* 7854 */ IC_VEX_L_W_XD, /* 7855 */ IC_VEX_L_OPSIZE, /* 7856 */ IC_VEX_L_OPSIZE, /* 7857 */ IC_VEX_L_OPSIZE, /* 7858 */ IC_VEX_L_OPSIZE, /* 7859 */ IC_VEX_L_OPSIZE, /* 7860 */ IC_VEX_L_OPSIZE, /* 7861 */ IC_VEX_L_OPSIZE, /* 7862 */ IC_VEX_L_OPSIZE, /* 7863 */ IC_VEX_L_W_OPSIZE, /* 7864 */ IC_VEX_L_W_OPSIZE, /* 7865 */ IC_VEX_L_W_OPSIZE, /* 7866 */ IC_VEX_L_W_OPSIZE, /* 7867 */ IC_VEX_L_W_OPSIZE, /* 7868 */ IC_VEX_L_W_OPSIZE, /* 7869 */ IC_VEX_L_W_OPSIZE, /* 7870 */ IC_VEX_L_W_OPSIZE, /* 7871 */ IC_VEX_L, /* 7872 */ IC_VEX_L, /* 7873 */ IC_VEX_L_XS, /* 7874 */ IC_VEX_L_XS, /* 7875 */ IC_VEX_L_XD, /* 7876 */ IC_VEX_L_XD, /* 7877 */ IC_VEX_L_XD, /* 7878 */ IC_VEX_L_XD, /* 7879 */ IC_VEX_L_W, /* 7880 */ IC_VEX_L_W, /* 7881 */ IC_VEX_L_W_XS, /* 7882 */ IC_VEX_L_W_XS, /* 7883 */ IC_VEX_L_W_XD, /* 7884 */ IC_VEX_L_W_XD, /* 7885 */ IC_VEX_L_W_XD, /* 7886 */ IC_VEX_L_W_XD, /* 7887 */ IC_VEX_L_OPSIZE, /* 7888 */ IC_VEX_L_OPSIZE, /* 7889 */ IC_VEX_L_OPSIZE, /* 7890 */ IC_VEX_L_OPSIZE, /* 7891 */ IC_VEX_L_OPSIZE, /* 7892 */ IC_VEX_L_OPSIZE, /* 7893 */ IC_VEX_L_OPSIZE, /* 7894 */ IC_VEX_L_OPSIZE, /* 7895 */ IC_VEX_L_W_OPSIZE, /* 7896 */ IC_VEX_L_W_OPSIZE, /* 7897 */ IC_VEX_L_W_OPSIZE, /* 7898 */ IC_VEX_L_W_OPSIZE, /* 7899 */ IC_VEX_L_W_OPSIZE, /* 7900 */ IC_VEX_L_W_OPSIZE, /* 7901 */ IC_VEX_L_W_OPSIZE, /* 7902 */ IC_VEX_L_W_OPSIZE, /* 7903 */ IC_VEX_L, /* 7904 */ IC_VEX_L, /* 7905 */ IC_VEX_L_XS, /* 7906 */ IC_VEX_L_XS, /* 7907 */ IC_VEX_L_XD, /* 7908 */ IC_VEX_L_XD, /* 7909 */ IC_VEX_L_XD, /* 7910 */ IC_VEX_L_XD, /* 7911 */ IC_VEX_L_W, /* 7912 */ IC_VEX_L_W, /* 7913 */ IC_VEX_L_W_XS, /* 7914 */ IC_VEX_L_W_XS, /* 7915 */ IC_VEX_L_W_XD, /* 7916 */ IC_VEX_L_W_XD, /* 7917 */ IC_VEX_L_W_XD, /* 7918 */ IC_VEX_L_W_XD, /* 7919 */ IC_VEX_L_OPSIZE, /* 7920 */ IC_VEX_L_OPSIZE, /* 7921 */ IC_VEX_L_OPSIZE, /* 7922 */ IC_VEX_L_OPSIZE, /* 7923 */ IC_VEX_L_OPSIZE, /* 7924 */ IC_VEX_L_OPSIZE, /* 7925 */ IC_VEX_L_OPSIZE, /* 7926 */ IC_VEX_L_OPSIZE, /* 7927 */ IC_VEX_L_W_OPSIZE, /* 7928 */ IC_VEX_L_W_OPSIZE, /* 7929 */ IC_VEX_L_W_OPSIZE, /* 7930 */ IC_VEX_L_W_OPSIZE, /* 7931 */ IC_VEX_L_W_OPSIZE, /* 7932 */ IC_VEX_L_W_OPSIZE, /* 7933 */ IC_VEX_L_W_OPSIZE, /* 7934 */ IC_VEX_L_W_OPSIZE, /* 7935 */ IC_EVEX_L2_KZ, /* 7936 */ IC_EVEX_L2_KZ, /* 7937 */ IC_EVEX_L2_XS_KZ, /* 7938 */ IC_EVEX_L2_XS_KZ, /* 7939 */ IC_EVEX_L2_XD_KZ, /* 7940 */ IC_EVEX_L2_XD_KZ, /* 7941 */ IC_EVEX_L2_XD_KZ, /* 7942 */ IC_EVEX_L2_XD_KZ, /* 7943 */ IC_EVEX_L2_W_KZ, /* 7944 */ IC_EVEX_L2_W_KZ, /* 7945 */ IC_EVEX_L2_W_XS_KZ, /* 7946 */ IC_EVEX_L2_W_XS_KZ, /* 7947 */ IC_EVEX_L2_W_XD_KZ, /* 7948 */ IC_EVEX_L2_W_XD_KZ, /* 7949 */ IC_EVEX_L2_W_XD_KZ, /* 7950 */ IC_EVEX_L2_W_XD_KZ, /* 7951 */ IC_EVEX_L2_OPSIZE_KZ, /* 7952 */ IC_EVEX_L2_OPSIZE_KZ, /* 7953 */ IC_EVEX_L2_OPSIZE_KZ, /* 7954 */ IC_EVEX_L2_OPSIZE_KZ, /* 7955 */ IC_EVEX_L2_OPSIZE_KZ, /* 7956 */ IC_EVEX_L2_OPSIZE_KZ, /* 7957 */ IC_EVEX_L2_OPSIZE_KZ, /* 7958 */ IC_EVEX_L2_OPSIZE_KZ, /* 7959 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7960 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7961 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7962 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7963 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7964 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7965 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7966 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7967 */ IC_EVEX_L2_KZ, /* 7968 */ IC_EVEX_L2_KZ, /* 7969 */ IC_EVEX_L2_XS_KZ, /* 7970 */ IC_EVEX_L2_XS_KZ, /* 7971 */ IC_EVEX_L2_XD_KZ, /* 7972 */ IC_EVEX_L2_XD_KZ, /* 7973 */ IC_EVEX_L2_XD_KZ, /* 7974 */ IC_EVEX_L2_XD_KZ, /* 7975 */ IC_EVEX_L2_W_KZ, /* 7976 */ IC_EVEX_L2_W_KZ, /* 7977 */ IC_EVEX_L2_W_XS_KZ, /* 7978 */ IC_EVEX_L2_W_XS_KZ, /* 7979 */ IC_EVEX_L2_W_XD_KZ, /* 7980 */ IC_EVEX_L2_W_XD_KZ, /* 7981 */ IC_EVEX_L2_W_XD_KZ, /* 7982 */ IC_EVEX_L2_W_XD_KZ, /* 7983 */ IC_EVEX_L2_OPSIZE_KZ, /* 7984 */ IC_EVEX_L2_OPSIZE_KZ, /* 7985 */ IC_EVEX_L2_OPSIZE_KZ, /* 7986 */ IC_EVEX_L2_OPSIZE_KZ, /* 7987 */ IC_EVEX_L2_OPSIZE_KZ, /* 7988 */ IC_EVEX_L2_OPSIZE_KZ, /* 7989 */ IC_EVEX_L2_OPSIZE_KZ, /* 7990 */ IC_EVEX_L2_OPSIZE_KZ, /* 7991 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7992 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7993 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7994 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7995 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7996 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7997 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7998 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7999 */ IC_EVEX_L2_KZ, /* 8000 */ IC_EVEX_L2_KZ, /* 8001 */ IC_EVEX_L2_XS_KZ, /* 8002 */ IC_EVEX_L2_XS_KZ, /* 8003 */ IC_EVEX_L2_XD_KZ, /* 8004 */ IC_EVEX_L2_XD_KZ, /* 8005 */ IC_EVEX_L2_XD_KZ, /* 8006 */ IC_EVEX_L2_XD_KZ, /* 8007 */ IC_EVEX_L2_W_KZ, /* 8008 */ IC_EVEX_L2_W_KZ, /* 8009 */ IC_EVEX_L2_W_XS_KZ, /* 8010 */ IC_EVEX_L2_W_XS_KZ, /* 8011 */ IC_EVEX_L2_W_XD_KZ, /* 8012 */ IC_EVEX_L2_W_XD_KZ, /* 8013 */ IC_EVEX_L2_W_XD_KZ, /* 8014 */ IC_EVEX_L2_W_XD_KZ, /* 8015 */ IC_EVEX_L2_OPSIZE_KZ, /* 8016 */ IC_EVEX_L2_OPSIZE_KZ, /* 8017 */ IC_EVEX_L2_OPSIZE_KZ, /* 8018 */ IC_EVEX_L2_OPSIZE_KZ, /* 8019 */ IC_EVEX_L2_OPSIZE_KZ, /* 8020 */ IC_EVEX_L2_OPSIZE_KZ, /* 8021 */ IC_EVEX_L2_OPSIZE_KZ, /* 8022 */ IC_EVEX_L2_OPSIZE_KZ, /* 8023 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8024 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8025 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8026 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8027 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8028 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8029 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8030 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8031 */ IC_EVEX_L2_KZ, /* 8032 */ IC_EVEX_L2_KZ, /* 8033 */ IC_EVEX_L2_XS_KZ, /* 8034 */ IC_EVEX_L2_XS_KZ, /* 8035 */ IC_EVEX_L2_XD_KZ, /* 8036 */ IC_EVEX_L2_XD_KZ, /* 8037 */ IC_EVEX_L2_XD_KZ, /* 8038 */ IC_EVEX_L2_XD_KZ, /* 8039 */ IC_EVEX_L2_W_KZ, /* 8040 */ IC_EVEX_L2_W_KZ, /* 8041 */ IC_EVEX_L2_W_XS_KZ, /* 8042 */ IC_EVEX_L2_W_XS_KZ, /* 8043 */ IC_EVEX_L2_W_XD_KZ, /* 8044 */ IC_EVEX_L2_W_XD_KZ, /* 8045 */ IC_EVEX_L2_W_XD_KZ, /* 8046 */ IC_EVEX_L2_W_XD_KZ, /* 8047 */ IC_EVEX_L2_OPSIZE_KZ, /* 8048 */ IC_EVEX_L2_OPSIZE_KZ, /* 8049 */ IC_EVEX_L2_OPSIZE_KZ, /* 8050 */ IC_EVEX_L2_OPSIZE_KZ, /* 8051 */ IC_EVEX_L2_OPSIZE_KZ, /* 8052 */ IC_EVEX_L2_OPSIZE_KZ, /* 8053 */ IC_EVEX_L2_OPSIZE_KZ, /* 8054 */ IC_EVEX_L2_OPSIZE_KZ, /* 8055 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8056 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8057 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8058 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8059 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8060 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8061 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8062 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8063 */ IC_EVEX_L2_KZ, /* 8064 */ IC_EVEX_L2_KZ, /* 8065 */ IC_EVEX_L2_XS_KZ, /* 8066 */ IC_EVEX_L2_XS_KZ, /* 8067 */ IC_EVEX_L2_XD_KZ, /* 8068 */ IC_EVEX_L2_XD_KZ, /* 8069 */ IC_EVEX_L2_XD_KZ, /* 8070 */ IC_EVEX_L2_XD_KZ, /* 8071 */ IC_EVEX_L2_W_KZ, /* 8072 */ IC_EVEX_L2_W_KZ, /* 8073 */ IC_EVEX_L2_W_XS_KZ, /* 8074 */ IC_EVEX_L2_W_XS_KZ, /* 8075 */ IC_EVEX_L2_W_XD_KZ, /* 8076 */ IC_EVEX_L2_W_XD_KZ, /* 8077 */ IC_EVEX_L2_W_XD_KZ, /* 8078 */ IC_EVEX_L2_W_XD_KZ, /* 8079 */ IC_EVEX_L2_OPSIZE_KZ, /* 8080 */ IC_EVEX_L2_OPSIZE_KZ, /* 8081 */ IC_EVEX_L2_OPSIZE_KZ, /* 8082 */ IC_EVEX_L2_OPSIZE_KZ, /* 8083 */ IC_EVEX_L2_OPSIZE_KZ, /* 8084 */ IC_EVEX_L2_OPSIZE_KZ, /* 8085 */ IC_EVEX_L2_OPSIZE_KZ, /* 8086 */ IC_EVEX_L2_OPSIZE_KZ, /* 8087 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8088 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8089 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8090 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8091 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8092 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8093 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8094 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8095 */ IC_EVEX_L2_KZ, /* 8096 */ IC_EVEX_L2_KZ, /* 8097 */ IC_EVEX_L2_XS_KZ, /* 8098 */ IC_EVEX_L2_XS_KZ, /* 8099 */ IC_EVEX_L2_XD_KZ, /* 8100 */ IC_EVEX_L2_XD_KZ, /* 8101 */ IC_EVEX_L2_XD_KZ, /* 8102 */ IC_EVEX_L2_XD_KZ, /* 8103 */ IC_EVEX_L2_W_KZ, /* 8104 */ IC_EVEX_L2_W_KZ, /* 8105 */ IC_EVEX_L2_W_XS_KZ, /* 8106 */ IC_EVEX_L2_W_XS_KZ, /* 8107 */ IC_EVEX_L2_W_XD_KZ, /* 8108 */ IC_EVEX_L2_W_XD_KZ, /* 8109 */ IC_EVEX_L2_W_XD_KZ, /* 8110 */ IC_EVEX_L2_W_XD_KZ, /* 8111 */ IC_EVEX_L2_OPSIZE_KZ, /* 8112 */ IC_EVEX_L2_OPSIZE_KZ, /* 8113 */ IC_EVEX_L2_OPSIZE_KZ, /* 8114 */ IC_EVEX_L2_OPSIZE_KZ, /* 8115 */ IC_EVEX_L2_OPSIZE_KZ, /* 8116 */ IC_EVEX_L2_OPSIZE_KZ, /* 8117 */ IC_EVEX_L2_OPSIZE_KZ, /* 8118 */ IC_EVEX_L2_OPSIZE_KZ, /* 8119 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8120 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8121 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8122 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8123 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8124 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8125 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8126 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8127 */ IC_EVEX_L2_KZ, /* 8128 */ IC_EVEX_L2_KZ, /* 8129 */ IC_EVEX_L2_XS_KZ, /* 8130 */ IC_EVEX_L2_XS_KZ, /* 8131 */ IC_EVEX_L2_XD_KZ, /* 8132 */ IC_EVEX_L2_XD_KZ, /* 8133 */ IC_EVEX_L2_XD_KZ, /* 8134 */ IC_EVEX_L2_XD_KZ, /* 8135 */ IC_EVEX_L2_W_KZ, /* 8136 */ IC_EVEX_L2_W_KZ, /* 8137 */ IC_EVEX_L2_W_XS_KZ, /* 8138 */ IC_EVEX_L2_W_XS_KZ, /* 8139 */ IC_EVEX_L2_W_XD_KZ, /* 8140 */ IC_EVEX_L2_W_XD_KZ, /* 8141 */ IC_EVEX_L2_W_XD_KZ, /* 8142 */ IC_EVEX_L2_W_XD_KZ, /* 8143 */ IC_EVEX_L2_OPSIZE_KZ, /* 8144 */ IC_EVEX_L2_OPSIZE_KZ, /* 8145 */ IC_EVEX_L2_OPSIZE_KZ, /* 8146 */ IC_EVEX_L2_OPSIZE_KZ, /* 8147 */ IC_EVEX_L2_OPSIZE_KZ, /* 8148 */ IC_EVEX_L2_OPSIZE_KZ, /* 8149 */ IC_EVEX_L2_OPSIZE_KZ, /* 8150 */ IC_EVEX_L2_OPSIZE_KZ, /* 8151 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8152 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8153 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8154 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8155 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8156 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8157 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8158 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8159 */ IC_EVEX_L2_KZ, /* 8160 */ IC_EVEX_L2_KZ, /* 8161 */ IC_EVEX_L2_XS_KZ, /* 8162 */ IC_EVEX_L2_XS_KZ, /* 8163 */ IC_EVEX_L2_XD_KZ, /* 8164 */ IC_EVEX_L2_XD_KZ, /* 8165 */ IC_EVEX_L2_XD_KZ, /* 8166 */ IC_EVEX_L2_XD_KZ, /* 8167 */ IC_EVEX_L2_W_KZ, /* 8168 */ IC_EVEX_L2_W_KZ, /* 8169 */ IC_EVEX_L2_W_XS_KZ, /* 8170 */ IC_EVEX_L2_W_XS_KZ, /* 8171 */ IC_EVEX_L2_W_XD_KZ, /* 8172 */ IC_EVEX_L2_W_XD_KZ, /* 8173 */ IC_EVEX_L2_W_XD_KZ, /* 8174 */ IC_EVEX_L2_W_XD_KZ, /* 8175 */ IC_EVEX_L2_OPSIZE_KZ, /* 8176 */ IC_EVEX_L2_OPSIZE_KZ, /* 8177 */ IC_EVEX_L2_OPSIZE_KZ, /* 8178 */ IC_EVEX_L2_OPSIZE_KZ, /* 8179 */ IC_EVEX_L2_OPSIZE_KZ, /* 8180 */ IC_EVEX_L2_OPSIZE_KZ, /* 8181 */ IC_EVEX_L2_OPSIZE_KZ, /* 8182 */ IC_EVEX_L2_OPSIZE_KZ, /* 8183 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8184 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8185 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8186 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8187 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8188 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8189 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8190 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8191 */ IC, /* 8192 */ IC_64BIT, /* 8193 */ IC_XS, /* 8194 */ IC_64BIT_XS, /* 8195 */ IC_XD, /* 8196 */ IC_64BIT_XD, /* 8197 */ IC_XS, /* 8198 */ IC_64BIT_XS, /* 8199 */ IC, /* 8200 */ IC_64BIT_REXW, /* 8201 */ IC_XS, /* 8202 */ IC_64BIT_REXW_XS, /* 8203 */ IC_XD, /* 8204 */ IC_64BIT_REXW_XD, /* 8205 */ IC_XS, /* 8206 */ IC_64BIT_REXW_XS, /* 8207 */ IC_OPSIZE, /* 8208 */ IC_64BIT_OPSIZE, /* 8209 */ IC_XS_OPSIZE, /* 8210 */ IC_64BIT_XS_OPSIZE, /* 8211 */ IC_XD_OPSIZE, /* 8212 */ IC_64BIT_XD_OPSIZE, /* 8213 */ IC_XS_OPSIZE, /* 8214 */ IC_64BIT_XD_OPSIZE, /* 8215 */ IC_OPSIZE, /* 8216 */ IC_64BIT_REXW_OPSIZE, /* 8217 */ IC_XS_OPSIZE, /* 8218 */ IC_64BIT_REXW_XS, /* 8219 */ IC_XD_OPSIZE, /* 8220 */ IC_64BIT_REXW_XD, /* 8221 */ IC_XS_OPSIZE, /* 8222 */ IC_64BIT_REXW_XS, /* 8223 */ IC_ADSIZE, /* 8224 */ IC_64BIT_ADSIZE, /* 8225 */ IC_XS_ADSIZE, /* 8226 */ IC_64BIT_XS_ADSIZE, /* 8227 */ IC_XD_ADSIZE, /* 8228 */ IC_64BIT_XD_ADSIZE, /* 8229 */ IC_XS_ADSIZE, /* 8230 */ IC_64BIT_XD_ADSIZE, /* 8231 */ IC_ADSIZE, /* 8232 */ IC_64BIT_REXW_ADSIZE, /* 8233 */ IC_XS_ADSIZE, /* 8234 */ IC_64BIT_REXW_XS, /* 8235 */ IC_XD_ADSIZE, /* 8236 */ IC_64BIT_REXW_XD, /* 8237 */ IC_XS_ADSIZE, /* 8238 */ IC_64BIT_REXW_XS, /* 8239 */ IC_OPSIZE_ADSIZE, /* 8240 */ IC_64BIT_OPSIZE_ADSIZE, /* 8241 */ IC_XS_OPSIZE, /* 8242 */ IC_64BIT_XS_OPSIZE, /* 8243 */ IC_XD_OPSIZE, /* 8244 */ IC_64BIT_XD_OPSIZE, /* 8245 */ IC_XS_OPSIZE, /* 8246 */ IC_64BIT_XD_OPSIZE, /* 8247 */ IC_OPSIZE_ADSIZE, /* 8248 */ IC_64BIT_REXW_OPSIZE, /* 8249 */ IC_XS_OPSIZE, /* 8250 */ IC_64BIT_REXW_XS, /* 8251 */ IC_XD_OPSIZE, /* 8252 */ IC_64BIT_REXW_XD, /* 8253 */ IC_XS_OPSIZE, /* 8254 */ IC_64BIT_REXW_XS, /* 8255 */ IC_VEX, /* 8256 */ IC_VEX, /* 8257 */ IC_VEX_XS, /* 8258 */ IC_VEX_XS, /* 8259 */ IC_VEX_XD, /* 8260 */ IC_VEX_XD, /* 8261 */ IC_VEX_XD, /* 8262 */ IC_VEX_XD, /* 8263 */ IC_VEX_W, /* 8264 */ IC_VEX_W, /* 8265 */ IC_VEX_W_XS, /* 8266 */ IC_VEX_W_XS, /* 8267 */ IC_VEX_W_XD, /* 8268 */ IC_VEX_W_XD, /* 8269 */ IC_VEX_W_XD, /* 8270 */ IC_VEX_W_XD, /* 8271 */ IC_VEX_OPSIZE, /* 8272 */ IC_VEX_OPSIZE, /* 8273 */ IC_VEX_OPSIZE, /* 8274 */ IC_VEX_OPSIZE, /* 8275 */ IC_VEX_OPSIZE, /* 8276 */ IC_VEX_OPSIZE, /* 8277 */ IC_VEX_OPSIZE, /* 8278 */ IC_VEX_OPSIZE, /* 8279 */ IC_VEX_W_OPSIZE, /* 8280 */ IC_VEX_W_OPSIZE, /* 8281 */ IC_VEX_W_OPSIZE, /* 8282 */ IC_VEX_W_OPSIZE, /* 8283 */ IC_VEX_W_OPSIZE, /* 8284 */ IC_VEX_W_OPSIZE, /* 8285 */ IC_VEX_W_OPSIZE, /* 8286 */ IC_VEX_W_OPSIZE, /* 8287 */ IC_VEX, /* 8288 */ IC_VEX, /* 8289 */ IC_VEX_XS, /* 8290 */ IC_VEX_XS, /* 8291 */ IC_VEX_XD, /* 8292 */ IC_VEX_XD, /* 8293 */ IC_VEX_XD, /* 8294 */ IC_VEX_XD, /* 8295 */ IC_VEX_W, /* 8296 */ IC_VEX_W, /* 8297 */ IC_VEX_W_XS, /* 8298 */ IC_VEX_W_XS, /* 8299 */ IC_VEX_W_XD, /* 8300 */ IC_VEX_W_XD, /* 8301 */ IC_VEX_W_XD, /* 8302 */ IC_VEX_W_XD, /* 8303 */ IC_VEX_OPSIZE, /* 8304 */ IC_VEX_OPSIZE, /* 8305 */ IC_VEX_OPSIZE, /* 8306 */ IC_VEX_OPSIZE, /* 8307 */ IC_VEX_OPSIZE, /* 8308 */ IC_VEX_OPSIZE, /* 8309 */ IC_VEX_OPSIZE, /* 8310 */ IC_VEX_OPSIZE, /* 8311 */ IC_VEX_W_OPSIZE, /* 8312 */ IC_VEX_W_OPSIZE, /* 8313 */ IC_VEX_W_OPSIZE, /* 8314 */ IC_VEX_W_OPSIZE, /* 8315 */ IC_VEX_W_OPSIZE, /* 8316 */ IC_VEX_W_OPSIZE, /* 8317 */ IC_VEX_W_OPSIZE, /* 8318 */ IC_VEX_W_OPSIZE, /* 8319 */ IC_VEX_L, /* 8320 */ IC_VEX_L, /* 8321 */ IC_VEX_L_XS, /* 8322 */ IC_VEX_L_XS, /* 8323 */ IC_VEX_L_XD, /* 8324 */ IC_VEX_L_XD, /* 8325 */ IC_VEX_L_XD, /* 8326 */ IC_VEX_L_XD, /* 8327 */ IC_VEX_L_W, /* 8328 */ IC_VEX_L_W, /* 8329 */ IC_VEX_L_W_XS, /* 8330 */ IC_VEX_L_W_XS, /* 8331 */ IC_VEX_L_W_XD, /* 8332 */ IC_VEX_L_W_XD, /* 8333 */ IC_VEX_L_W_XD, /* 8334 */ IC_VEX_L_W_XD, /* 8335 */ IC_VEX_L_OPSIZE, /* 8336 */ IC_VEX_L_OPSIZE, /* 8337 */ IC_VEX_L_OPSIZE, /* 8338 */ IC_VEX_L_OPSIZE, /* 8339 */ IC_VEX_L_OPSIZE, /* 8340 */ IC_VEX_L_OPSIZE, /* 8341 */ IC_VEX_L_OPSIZE, /* 8342 */ IC_VEX_L_OPSIZE, /* 8343 */ IC_VEX_L_W_OPSIZE, /* 8344 */ IC_VEX_L_W_OPSIZE, /* 8345 */ IC_VEX_L_W_OPSIZE, /* 8346 */ IC_VEX_L_W_OPSIZE, /* 8347 */ IC_VEX_L_W_OPSIZE, /* 8348 */ IC_VEX_L_W_OPSIZE, /* 8349 */ IC_VEX_L_W_OPSIZE, /* 8350 */ IC_VEX_L_W_OPSIZE, /* 8351 */ IC_VEX_L, /* 8352 */ IC_VEX_L, /* 8353 */ IC_VEX_L_XS, /* 8354 */ IC_VEX_L_XS, /* 8355 */ IC_VEX_L_XD, /* 8356 */ IC_VEX_L_XD, /* 8357 */ IC_VEX_L_XD, /* 8358 */ IC_VEX_L_XD, /* 8359 */ IC_VEX_L_W, /* 8360 */ IC_VEX_L_W, /* 8361 */ IC_VEX_L_W_XS, /* 8362 */ IC_VEX_L_W_XS, /* 8363 */ IC_VEX_L_W_XD, /* 8364 */ IC_VEX_L_W_XD, /* 8365 */ IC_VEX_L_W_XD, /* 8366 */ IC_VEX_L_W_XD, /* 8367 */ IC_VEX_L_OPSIZE, /* 8368 */ IC_VEX_L_OPSIZE, /* 8369 */ IC_VEX_L_OPSIZE, /* 8370 */ IC_VEX_L_OPSIZE, /* 8371 */ IC_VEX_L_OPSIZE, /* 8372 */ IC_VEX_L_OPSIZE, /* 8373 */ IC_VEX_L_OPSIZE, /* 8374 */ IC_VEX_L_OPSIZE, /* 8375 */ IC_VEX_L_W_OPSIZE, /* 8376 */ IC_VEX_L_W_OPSIZE, /* 8377 */ IC_VEX_L_W_OPSIZE, /* 8378 */ IC_VEX_L_W_OPSIZE, /* 8379 */ IC_VEX_L_W_OPSIZE, /* 8380 */ IC_VEX_L_W_OPSIZE, /* 8381 */ IC_VEX_L_W_OPSIZE, /* 8382 */ IC_VEX_L_W_OPSIZE, /* 8383 */ IC_VEX_L, /* 8384 */ IC_VEX_L, /* 8385 */ IC_VEX_L_XS, /* 8386 */ IC_VEX_L_XS, /* 8387 */ IC_VEX_L_XD, /* 8388 */ IC_VEX_L_XD, /* 8389 */ IC_VEX_L_XD, /* 8390 */ IC_VEX_L_XD, /* 8391 */ IC_VEX_L_W, /* 8392 */ IC_VEX_L_W, /* 8393 */ IC_VEX_L_W_XS, /* 8394 */ IC_VEX_L_W_XS, /* 8395 */ IC_VEX_L_W_XD, /* 8396 */ IC_VEX_L_W_XD, /* 8397 */ IC_VEX_L_W_XD, /* 8398 */ IC_VEX_L_W_XD, /* 8399 */ IC_VEX_L_OPSIZE, /* 8400 */ IC_VEX_L_OPSIZE, /* 8401 */ IC_VEX_L_OPSIZE, /* 8402 */ IC_VEX_L_OPSIZE, /* 8403 */ IC_VEX_L_OPSIZE, /* 8404 */ IC_VEX_L_OPSIZE, /* 8405 */ IC_VEX_L_OPSIZE, /* 8406 */ IC_VEX_L_OPSIZE, /* 8407 */ IC_VEX_L_W_OPSIZE, /* 8408 */ IC_VEX_L_W_OPSIZE, /* 8409 */ IC_VEX_L_W_OPSIZE, /* 8410 */ IC_VEX_L_W_OPSIZE, /* 8411 */ IC_VEX_L_W_OPSIZE, /* 8412 */ IC_VEX_L_W_OPSIZE, /* 8413 */ IC_VEX_L_W_OPSIZE, /* 8414 */ IC_VEX_L_W_OPSIZE, /* 8415 */ IC_VEX_L, /* 8416 */ IC_VEX_L, /* 8417 */ IC_VEX_L_XS, /* 8418 */ IC_VEX_L_XS, /* 8419 */ IC_VEX_L_XD, /* 8420 */ IC_VEX_L_XD, /* 8421 */ IC_VEX_L_XD, /* 8422 */ IC_VEX_L_XD, /* 8423 */ IC_VEX_L_W, /* 8424 */ IC_VEX_L_W, /* 8425 */ IC_VEX_L_W_XS, /* 8426 */ IC_VEX_L_W_XS, /* 8427 */ IC_VEX_L_W_XD, /* 8428 */ IC_VEX_L_W_XD, /* 8429 */ IC_VEX_L_W_XD, /* 8430 */ IC_VEX_L_W_XD, /* 8431 */ IC_VEX_L_OPSIZE, /* 8432 */ IC_VEX_L_OPSIZE, /* 8433 */ IC_VEX_L_OPSIZE, /* 8434 */ IC_VEX_L_OPSIZE, /* 8435 */ IC_VEX_L_OPSIZE, /* 8436 */ IC_VEX_L_OPSIZE, /* 8437 */ IC_VEX_L_OPSIZE, /* 8438 */ IC_VEX_L_OPSIZE, /* 8439 */ IC_VEX_L_W_OPSIZE, /* 8440 */ IC_VEX_L_W_OPSIZE, /* 8441 */ IC_VEX_L_W_OPSIZE, /* 8442 */ IC_VEX_L_W_OPSIZE, /* 8443 */ IC_VEX_L_W_OPSIZE, /* 8444 */ IC_VEX_L_W_OPSIZE, /* 8445 */ IC_VEX_L_W_OPSIZE, /* 8446 */ IC_VEX_L_W_OPSIZE, /* 8447 */ IC_EVEX_B, /* 8448 */ IC_EVEX_B, /* 8449 */ IC_EVEX_XS_B, /* 8450 */ IC_EVEX_XS_B, /* 8451 */ IC_EVEX_XD_B, /* 8452 */ IC_EVEX_XD_B, /* 8453 */ IC_EVEX_XD_B, /* 8454 */ IC_EVEX_XD_B, /* 8455 */ IC_EVEX_W_B, /* 8456 */ IC_EVEX_W_B, /* 8457 */ IC_EVEX_W_XS_B, /* 8458 */ IC_EVEX_W_XS_B, /* 8459 */ IC_EVEX_W_XD_B, /* 8460 */ IC_EVEX_W_XD_B, /* 8461 */ IC_EVEX_W_XD_B, /* 8462 */ IC_EVEX_W_XD_B, /* 8463 */ IC_EVEX_OPSIZE_B, /* 8464 */ IC_EVEX_OPSIZE_B, /* 8465 */ IC_EVEX_OPSIZE_B, /* 8466 */ IC_EVEX_OPSIZE_B, /* 8467 */ IC_EVEX_OPSIZE_B, /* 8468 */ IC_EVEX_OPSIZE_B, /* 8469 */ IC_EVEX_OPSIZE_B, /* 8470 */ IC_EVEX_OPSIZE_B, /* 8471 */ IC_EVEX_W_OPSIZE_B, /* 8472 */ IC_EVEX_W_OPSIZE_B, /* 8473 */ IC_EVEX_W_OPSIZE_B, /* 8474 */ IC_EVEX_W_OPSIZE_B, /* 8475 */ IC_EVEX_W_OPSIZE_B, /* 8476 */ IC_EVEX_W_OPSIZE_B, /* 8477 */ IC_EVEX_W_OPSIZE_B, /* 8478 */ IC_EVEX_W_OPSIZE_B, /* 8479 */ IC_EVEX_B, /* 8480 */ IC_EVEX_B, /* 8481 */ IC_EVEX_XS_B, /* 8482 */ IC_EVEX_XS_B, /* 8483 */ IC_EVEX_XD_B, /* 8484 */ IC_EVEX_XD_B, /* 8485 */ IC_EVEX_XD_B, /* 8486 */ IC_EVEX_XD_B, /* 8487 */ IC_EVEX_W_B, /* 8488 */ IC_EVEX_W_B, /* 8489 */ IC_EVEX_W_XS_B, /* 8490 */ IC_EVEX_W_XS_B, /* 8491 */ IC_EVEX_W_XD_B, /* 8492 */ IC_EVEX_W_XD_B, /* 8493 */ IC_EVEX_W_XD_B, /* 8494 */ IC_EVEX_W_XD_B, /* 8495 */ IC_EVEX_OPSIZE_B, /* 8496 */ IC_EVEX_OPSIZE_B, /* 8497 */ IC_EVEX_OPSIZE_B, /* 8498 */ IC_EVEX_OPSIZE_B, /* 8499 */ IC_EVEX_OPSIZE_B, /* 8500 */ IC_EVEX_OPSIZE_B, /* 8501 */ IC_EVEX_OPSIZE_B, /* 8502 */ IC_EVEX_OPSIZE_B, /* 8503 */ IC_EVEX_W_OPSIZE_B, /* 8504 */ IC_EVEX_W_OPSIZE_B, /* 8505 */ IC_EVEX_W_OPSIZE_B, /* 8506 */ IC_EVEX_W_OPSIZE_B, /* 8507 */ IC_EVEX_W_OPSIZE_B, /* 8508 */ IC_EVEX_W_OPSIZE_B, /* 8509 */ IC_EVEX_W_OPSIZE_B, /* 8510 */ IC_EVEX_W_OPSIZE_B, /* 8511 */ IC_EVEX_B, /* 8512 */ IC_EVEX_B, /* 8513 */ IC_EVEX_XS_B, /* 8514 */ IC_EVEX_XS_B, /* 8515 */ IC_EVEX_XD_B, /* 8516 */ IC_EVEX_XD_B, /* 8517 */ IC_EVEX_XD_B, /* 8518 */ IC_EVEX_XD_B, /* 8519 */ IC_EVEX_W_B, /* 8520 */ IC_EVEX_W_B, /* 8521 */ IC_EVEX_W_XS_B, /* 8522 */ IC_EVEX_W_XS_B, /* 8523 */ IC_EVEX_W_XD_B, /* 8524 */ IC_EVEX_W_XD_B, /* 8525 */ IC_EVEX_W_XD_B, /* 8526 */ IC_EVEX_W_XD_B, /* 8527 */ IC_EVEX_OPSIZE_B, /* 8528 */ IC_EVEX_OPSIZE_B, /* 8529 */ IC_EVEX_OPSIZE_B, /* 8530 */ IC_EVEX_OPSIZE_B, /* 8531 */ IC_EVEX_OPSIZE_B, /* 8532 */ IC_EVEX_OPSIZE_B, /* 8533 */ IC_EVEX_OPSIZE_B, /* 8534 */ IC_EVEX_OPSIZE_B, /* 8535 */ IC_EVEX_W_OPSIZE_B, /* 8536 */ IC_EVEX_W_OPSIZE_B, /* 8537 */ IC_EVEX_W_OPSIZE_B, /* 8538 */ IC_EVEX_W_OPSIZE_B, /* 8539 */ IC_EVEX_W_OPSIZE_B, /* 8540 */ IC_EVEX_W_OPSIZE_B, /* 8541 */ IC_EVEX_W_OPSIZE_B, /* 8542 */ IC_EVEX_W_OPSIZE_B, /* 8543 */ IC_EVEX_B, /* 8544 */ IC_EVEX_B, /* 8545 */ IC_EVEX_XS_B, /* 8546 */ IC_EVEX_XS_B, /* 8547 */ IC_EVEX_XD_B, /* 8548 */ IC_EVEX_XD_B, /* 8549 */ IC_EVEX_XD_B, /* 8550 */ IC_EVEX_XD_B, /* 8551 */ IC_EVEX_W_B, /* 8552 */ IC_EVEX_W_B, /* 8553 */ IC_EVEX_W_XS_B, /* 8554 */ IC_EVEX_W_XS_B, /* 8555 */ IC_EVEX_W_XD_B, /* 8556 */ IC_EVEX_W_XD_B, /* 8557 */ IC_EVEX_W_XD_B, /* 8558 */ IC_EVEX_W_XD_B, /* 8559 */ IC_EVEX_OPSIZE_B, /* 8560 */ IC_EVEX_OPSIZE_B, /* 8561 */ IC_EVEX_OPSIZE_B, /* 8562 */ IC_EVEX_OPSIZE_B, /* 8563 */ IC_EVEX_OPSIZE_B, /* 8564 */ IC_EVEX_OPSIZE_B, /* 8565 */ IC_EVEX_OPSIZE_B, /* 8566 */ IC_EVEX_OPSIZE_B, /* 8567 */ IC_EVEX_W_OPSIZE_B, /* 8568 */ IC_EVEX_W_OPSIZE_B, /* 8569 */ IC_EVEX_W_OPSIZE_B, /* 8570 */ IC_EVEX_W_OPSIZE_B, /* 8571 */ IC_EVEX_W_OPSIZE_B, /* 8572 */ IC_EVEX_W_OPSIZE_B, /* 8573 */ IC_EVEX_W_OPSIZE_B, /* 8574 */ IC_EVEX_W_OPSIZE_B, /* 8575 */ IC_EVEX_B, /* 8576 */ IC_EVEX_B, /* 8577 */ IC_EVEX_XS_B, /* 8578 */ IC_EVEX_XS_B, /* 8579 */ IC_EVEX_XD_B, /* 8580 */ IC_EVEX_XD_B, /* 8581 */ IC_EVEX_XD_B, /* 8582 */ IC_EVEX_XD_B, /* 8583 */ IC_EVEX_W_B, /* 8584 */ IC_EVEX_W_B, /* 8585 */ IC_EVEX_W_XS_B, /* 8586 */ IC_EVEX_W_XS_B, /* 8587 */ IC_EVEX_W_XD_B, /* 8588 */ IC_EVEX_W_XD_B, /* 8589 */ IC_EVEX_W_XD_B, /* 8590 */ IC_EVEX_W_XD_B, /* 8591 */ IC_EVEX_OPSIZE_B, /* 8592 */ IC_EVEX_OPSIZE_B, /* 8593 */ IC_EVEX_OPSIZE_B, /* 8594 */ IC_EVEX_OPSIZE_B, /* 8595 */ IC_EVEX_OPSIZE_B, /* 8596 */ IC_EVEX_OPSIZE_B, /* 8597 */ IC_EVEX_OPSIZE_B, /* 8598 */ IC_EVEX_OPSIZE_B, /* 8599 */ IC_EVEX_W_OPSIZE_B, /* 8600 */ IC_EVEX_W_OPSIZE_B, /* 8601 */ IC_EVEX_W_OPSIZE_B, /* 8602 */ IC_EVEX_W_OPSIZE_B, /* 8603 */ IC_EVEX_W_OPSIZE_B, /* 8604 */ IC_EVEX_W_OPSIZE_B, /* 8605 */ IC_EVEX_W_OPSIZE_B, /* 8606 */ IC_EVEX_W_OPSIZE_B, /* 8607 */ IC_EVEX_B, /* 8608 */ IC_EVEX_B, /* 8609 */ IC_EVEX_XS_B, /* 8610 */ IC_EVEX_XS_B, /* 8611 */ IC_EVEX_XD_B, /* 8612 */ IC_EVEX_XD_B, /* 8613 */ IC_EVEX_XD_B, /* 8614 */ IC_EVEX_XD_B, /* 8615 */ IC_EVEX_W_B, /* 8616 */ IC_EVEX_W_B, /* 8617 */ IC_EVEX_W_XS_B, /* 8618 */ IC_EVEX_W_XS_B, /* 8619 */ IC_EVEX_W_XD_B, /* 8620 */ IC_EVEX_W_XD_B, /* 8621 */ IC_EVEX_W_XD_B, /* 8622 */ IC_EVEX_W_XD_B, /* 8623 */ IC_EVEX_OPSIZE_B, /* 8624 */ IC_EVEX_OPSIZE_B, /* 8625 */ IC_EVEX_OPSIZE_B, /* 8626 */ IC_EVEX_OPSIZE_B, /* 8627 */ IC_EVEX_OPSIZE_B, /* 8628 */ IC_EVEX_OPSIZE_B, /* 8629 */ IC_EVEX_OPSIZE_B, /* 8630 */ IC_EVEX_OPSIZE_B, /* 8631 */ IC_EVEX_W_OPSIZE_B, /* 8632 */ IC_EVEX_W_OPSIZE_B, /* 8633 */ IC_EVEX_W_OPSIZE_B, /* 8634 */ IC_EVEX_W_OPSIZE_B, /* 8635 */ IC_EVEX_W_OPSIZE_B, /* 8636 */ IC_EVEX_W_OPSIZE_B, /* 8637 */ IC_EVEX_W_OPSIZE_B, /* 8638 */ IC_EVEX_W_OPSIZE_B, /* 8639 */ IC_EVEX_B, /* 8640 */ IC_EVEX_B, /* 8641 */ IC_EVEX_XS_B, /* 8642 */ IC_EVEX_XS_B, /* 8643 */ IC_EVEX_XD_B, /* 8644 */ IC_EVEX_XD_B, /* 8645 */ IC_EVEX_XD_B, /* 8646 */ IC_EVEX_XD_B, /* 8647 */ IC_EVEX_W_B, /* 8648 */ IC_EVEX_W_B, /* 8649 */ IC_EVEX_W_XS_B, /* 8650 */ IC_EVEX_W_XS_B, /* 8651 */ IC_EVEX_W_XD_B, /* 8652 */ IC_EVEX_W_XD_B, /* 8653 */ IC_EVEX_W_XD_B, /* 8654 */ IC_EVEX_W_XD_B, /* 8655 */ IC_EVEX_OPSIZE_B, /* 8656 */ IC_EVEX_OPSIZE_B, /* 8657 */ IC_EVEX_OPSIZE_B, /* 8658 */ IC_EVEX_OPSIZE_B, /* 8659 */ IC_EVEX_OPSIZE_B, /* 8660 */ IC_EVEX_OPSIZE_B, /* 8661 */ IC_EVEX_OPSIZE_B, /* 8662 */ IC_EVEX_OPSIZE_B, /* 8663 */ IC_EVEX_W_OPSIZE_B, /* 8664 */ IC_EVEX_W_OPSIZE_B, /* 8665 */ IC_EVEX_W_OPSIZE_B, /* 8666 */ IC_EVEX_W_OPSIZE_B, /* 8667 */ IC_EVEX_W_OPSIZE_B, /* 8668 */ IC_EVEX_W_OPSIZE_B, /* 8669 */ IC_EVEX_W_OPSIZE_B, /* 8670 */ IC_EVEX_W_OPSIZE_B, /* 8671 */ IC_EVEX_B, /* 8672 */ IC_EVEX_B, /* 8673 */ IC_EVEX_XS_B, /* 8674 */ IC_EVEX_XS_B, /* 8675 */ IC_EVEX_XD_B, /* 8676 */ IC_EVEX_XD_B, /* 8677 */ IC_EVEX_XD_B, /* 8678 */ IC_EVEX_XD_B, /* 8679 */ IC_EVEX_W_B, /* 8680 */ IC_EVEX_W_B, /* 8681 */ IC_EVEX_W_XS_B, /* 8682 */ IC_EVEX_W_XS_B, /* 8683 */ IC_EVEX_W_XD_B, /* 8684 */ IC_EVEX_W_XD_B, /* 8685 */ IC_EVEX_W_XD_B, /* 8686 */ IC_EVEX_W_XD_B, /* 8687 */ IC_EVEX_OPSIZE_B, /* 8688 */ IC_EVEX_OPSIZE_B, /* 8689 */ IC_EVEX_OPSIZE_B, /* 8690 */ IC_EVEX_OPSIZE_B, /* 8691 */ IC_EVEX_OPSIZE_B, /* 8692 */ IC_EVEX_OPSIZE_B, /* 8693 */ IC_EVEX_OPSIZE_B, /* 8694 */ IC_EVEX_OPSIZE_B, /* 8695 */ IC_EVEX_W_OPSIZE_B, /* 8696 */ IC_EVEX_W_OPSIZE_B, /* 8697 */ IC_EVEX_W_OPSIZE_B, /* 8698 */ IC_EVEX_W_OPSIZE_B, /* 8699 */ IC_EVEX_W_OPSIZE_B, /* 8700 */ IC_EVEX_W_OPSIZE_B, /* 8701 */ IC_EVEX_W_OPSIZE_B, /* 8702 */ IC_EVEX_W_OPSIZE_B, /* 8703 */ IC, /* 8704 */ IC_64BIT, /* 8705 */ IC_XS, /* 8706 */ IC_64BIT_XS, /* 8707 */ IC_XD, /* 8708 */ IC_64BIT_XD, /* 8709 */ IC_XS, /* 8710 */ IC_64BIT_XS, /* 8711 */ IC, /* 8712 */ IC_64BIT_REXW, /* 8713 */ IC_XS, /* 8714 */ IC_64BIT_REXW_XS, /* 8715 */ IC_XD, /* 8716 */ IC_64BIT_REXW_XD, /* 8717 */ IC_XS, /* 8718 */ IC_64BIT_REXW_XS, /* 8719 */ IC_OPSIZE, /* 8720 */ IC_64BIT_OPSIZE, /* 8721 */ IC_XS_OPSIZE, /* 8722 */ IC_64BIT_XS_OPSIZE, /* 8723 */ IC_XD_OPSIZE, /* 8724 */ IC_64BIT_XD_OPSIZE, /* 8725 */ IC_XS_OPSIZE, /* 8726 */ IC_64BIT_XD_OPSIZE, /* 8727 */ IC_OPSIZE, /* 8728 */ IC_64BIT_REXW_OPSIZE, /* 8729 */ IC_XS_OPSIZE, /* 8730 */ IC_64BIT_REXW_XS, /* 8731 */ IC_XD_OPSIZE, /* 8732 */ IC_64BIT_REXW_XD, /* 8733 */ IC_XS_OPSIZE, /* 8734 */ IC_64BIT_REXW_XS, /* 8735 */ IC_ADSIZE, /* 8736 */ IC_64BIT_ADSIZE, /* 8737 */ IC_XS_ADSIZE, /* 8738 */ IC_64BIT_XS_ADSIZE, /* 8739 */ IC_XD_ADSIZE, /* 8740 */ IC_64BIT_XD_ADSIZE, /* 8741 */ IC_XS_ADSIZE, /* 8742 */ IC_64BIT_XD_ADSIZE, /* 8743 */ IC_ADSIZE, /* 8744 */ IC_64BIT_REXW_ADSIZE, /* 8745 */ IC_XS_ADSIZE, /* 8746 */ IC_64BIT_REXW_XS, /* 8747 */ IC_XD_ADSIZE, /* 8748 */ IC_64BIT_REXW_XD, /* 8749 */ IC_XS_ADSIZE, /* 8750 */ IC_64BIT_REXW_XS, /* 8751 */ IC_OPSIZE_ADSIZE, /* 8752 */ IC_64BIT_OPSIZE_ADSIZE, /* 8753 */ IC_XS_OPSIZE, /* 8754 */ IC_64BIT_XS_OPSIZE, /* 8755 */ IC_XD_OPSIZE, /* 8756 */ IC_64BIT_XD_OPSIZE, /* 8757 */ IC_XS_OPSIZE, /* 8758 */ IC_64BIT_XD_OPSIZE, /* 8759 */ IC_OPSIZE_ADSIZE, /* 8760 */ IC_64BIT_REXW_OPSIZE, /* 8761 */ IC_XS_OPSIZE, /* 8762 */ IC_64BIT_REXW_XS, /* 8763 */ IC_XD_OPSIZE, /* 8764 */ IC_64BIT_REXW_XD, /* 8765 */ IC_XS_OPSIZE, /* 8766 */ IC_64BIT_REXW_XS, /* 8767 */ IC_VEX, /* 8768 */ IC_VEX, /* 8769 */ IC_VEX_XS, /* 8770 */ IC_VEX_XS, /* 8771 */ IC_VEX_XD, /* 8772 */ IC_VEX_XD, /* 8773 */ IC_VEX_XD, /* 8774 */ IC_VEX_XD, /* 8775 */ IC_VEX_W, /* 8776 */ IC_VEX_W, /* 8777 */ IC_VEX_W_XS, /* 8778 */ IC_VEX_W_XS, /* 8779 */ IC_VEX_W_XD, /* 8780 */ IC_VEX_W_XD, /* 8781 */ IC_VEX_W_XD, /* 8782 */ IC_VEX_W_XD, /* 8783 */ IC_VEX_OPSIZE, /* 8784 */ IC_VEX_OPSIZE, /* 8785 */ IC_VEX_OPSIZE, /* 8786 */ IC_VEX_OPSIZE, /* 8787 */ IC_VEX_OPSIZE, /* 8788 */ IC_VEX_OPSIZE, /* 8789 */ IC_VEX_OPSIZE, /* 8790 */ IC_VEX_OPSIZE, /* 8791 */ IC_VEX_W_OPSIZE, /* 8792 */ IC_VEX_W_OPSIZE, /* 8793 */ IC_VEX_W_OPSIZE, /* 8794 */ IC_VEX_W_OPSIZE, /* 8795 */ IC_VEX_W_OPSIZE, /* 8796 */ IC_VEX_W_OPSIZE, /* 8797 */ IC_VEX_W_OPSIZE, /* 8798 */ IC_VEX_W_OPSIZE, /* 8799 */ IC_VEX, /* 8800 */ IC_VEX, /* 8801 */ IC_VEX_XS, /* 8802 */ IC_VEX_XS, /* 8803 */ IC_VEX_XD, /* 8804 */ IC_VEX_XD, /* 8805 */ IC_VEX_XD, /* 8806 */ IC_VEX_XD, /* 8807 */ IC_VEX_W, /* 8808 */ IC_VEX_W, /* 8809 */ IC_VEX_W_XS, /* 8810 */ IC_VEX_W_XS, /* 8811 */ IC_VEX_W_XD, /* 8812 */ IC_VEX_W_XD, /* 8813 */ IC_VEX_W_XD, /* 8814 */ IC_VEX_W_XD, /* 8815 */ IC_VEX_OPSIZE, /* 8816 */ IC_VEX_OPSIZE, /* 8817 */ IC_VEX_OPSIZE, /* 8818 */ IC_VEX_OPSIZE, /* 8819 */ IC_VEX_OPSIZE, /* 8820 */ IC_VEX_OPSIZE, /* 8821 */ IC_VEX_OPSIZE, /* 8822 */ IC_VEX_OPSIZE, /* 8823 */ IC_VEX_W_OPSIZE, /* 8824 */ IC_VEX_W_OPSIZE, /* 8825 */ IC_VEX_W_OPSIZE, /* 8826 */ IC_VEX_W_OPSIZE, /* 8827 */ IC_VEX_W_OPSIZE, /* 8828 */ IC_VEX_W_OPSIZE, /* 8829 */ IC_VEX_W_OPSIZE, /* 8830 */ IC_VEX_W_OPSIZE, /* 8831 */ IC_VEX_L, /* 8832 */ IC_VEX_L, /* 8833 */ IC_VEX_L_XS, /* 8834 */ IC_VEX_L_XS, /* 8835 */ IC_VEX_L_XD, /* 8836 */ IC_VEX_L_XD, /* 8837 */ IC_VEX_L_XD, /* 8838 */ IC_VEX_L_XD, /* 8839 */ IC_VEX_L_W, /* 8840 */ IC_VEX_L_W, /* 8841 */ IC_VEX_L_W_XS, /* 8842 */ IC_VEX_L_W_XS, /* 8843 */ IC_VEX_L_W_XD, /* 8844 */ IC_VEX_L_W_XD, /* 8845 */ IC_VEX_L_W_XD, /* 8846 */ IC_VEX_L_W_XD, /* 8847 */ IC_VEX_L_OPSIZE, /* 8848 */ IC_VEX_L_OPSIZE, /* 8849 */ IC_VEX_L_OPSIZE, /* 8850 */ IC_VEX_L_OPSIZE, /* 8851 */ IC_VEX_L_OPSIZE, /* 8852 */ IC_VEX_L_OPSIZE, /* 8853 */ IC_VEX_L_OPSIZE, /* 8854 */ IC_VEX_L_OPSIZE, /* 8855 */ IC_VEX_L_W_OPSIZE, /* 8856 */ IC_VEX_L_W_OPSIZE, /* 8857 */ IC_VEX_L_W_OPSIZE, /* 8858 */ IC_VEX_L_W_OPSIZE, /* 8859 */ IC_VEX_L_W_OPSIZE, /* 8860 */ IC_VEX_L_W_OPSIZE, /* 8861 */ IC_VEX_L_W_OPSIZE, /* 8862 */ IC_VEX_L_W_OPSIZE, /* 8863 */ IC_VEX_L, /* 8864 */ IC_VEX_L, /* 8865 */ IC_VEX_L_XS, /* 8866 */ IC_VEX_L_XS, /* 8867 */ IC_VEX_L_XD, /* 8868 */ IC_VEX_L_XD, /* 8869 */ IC_VEX_L_XD, /* 8870 */ IC_VEX_L_XD, /* 8871 */ IC_VEX_L_W, /* 8872 */ IC_VEX_L_W, /* 8873 */ IC_VEX_L_W_XS, /* 8874 */ IC_VEX_L_W_XS, /* 8875 */ IC_VEX_L_W_XD, /* 8876 */ IC_VEX_L_W_XD, /* 8877 */ IC_VEX_L_W_XD, /* 8878 */ IC_VEX_L_W_XD, /* 8879 */ IC_VEX_L_OPSIZE, /* 8880 */ IC_VEX_L_OPSIZE, /* 8881 */ IC_VEX_L_OPSIZE, /* 8882 */ IC_VEX_L_OPSIZE, /* 8883 */ IC_VEX_L_OPSIZE, /* 8884 */ IC_VEX_L_OPSIZE, /* 8885 */ IC_VEX_L_OPSIZE, /* 8886 */ IC_VEX_L_OPSIZE, /* 8887 */ IC_VEX_L_W_OPSIZE, /* 8888 */ IC_VEX_L_W_OPSIZE, /* 8889 */ IC_VEX_L_W_OPSIZE, /* 8890 */ IC_VEX_L_W_OPSIZE, /* 8891 */ IC_VEX_L_W_OPSIZE, /* 8892 */ IC_VEX_L_W_OPSIZE, /* 8893 */ IC_VEX_L_W_OPSIZE, /* 8894 */ IC_VEX_L_W_OPSIZE, /* 8895 */ IC_VEX_L, /* 8896 */ IC_VEX_L, /* 8897 */ IC_VEX_L_XS, /* 8898 */ IC_VEX_L_XS, /* 8899 */ IC_VEX_L_XD, /* 8900 */ IC_VEX_L_XD, /* 8901 */ IC_VEX_L_XD, /* 8902 */ IC_VEX_L_XD, /* 8903 */ IC_VEX_L_W, /* 8904 */ IC_VEX_L_W, /* 8905 */ IC_VEX_L_W_XS, /* 8906 */ IC_VEX_L_W_XS, /* 8907 */ IC_VEX_L_W_XD, /* 8908 */ IC_VEX_L_W_XD, /* 8909 */ IC_VEX_L_W_XD, /* 8910 */ IC_VEX_L_W_XD, /* 8911 */ IC_VEX_L_OPSIZE, /* 8912 */ IC_VEX_L_OPSIZE, /* 8913 */ IC_VEX_L_OPSIZE, /* 8914 */ IC_VEX_L_OPSIZE, /* 8915 */ IC_VEX_L_OPSIZE, /* 8916 */ IC_VEX_L_OPSIZE, /* 8917 */ IC_VEX_L_OPSIZE, /* 8918 */ IC_VEX_L_OPSIZE, /* 8919 */ IC_VEX_L_W_OPSIZE, /* 8920 */ IC_VEX_L_W_OPSIZE, /* 8921 */ IC_VEX_L_W_OPSIZE, /* 8922 */ IC_VEX_L_W_OPSIZE, /* 8923 */ IC_VEX_L_W_OPSIZE, /* 8924 */ IC_VEX_L_W_OPSIZE, /* 8925 */ IC_VEX_L_W_OPSIZE, /* 8926 */ IC_VEX_L_W_OPSIZE, /* 8927 */ IC_VEX_L, /* 8928 */ IC_VEX_L, /* 8929 */ IC_VEX_L_XS, /* 8930 */ IC_VEX_L_XS, /* 8931 */ IC_VEX_L_XD, /* 8932 */ IC_VEX_L_XD, /* 8933 */ IC_VEX_L_XD, /* 8934 */ IC_VEX_L_XD, /* 8935 */ IC_VEX_L_W, /* 8936 */ IC_VEX_L_W, /* 8937 */ IC_VEX_L_W_XS, /* 8938 */ IC_VEX_L_W_XS, /* 8939 */ IC_VEX_L_W_XD, /* 8940 */ IC_VEX_L_W_XD, /* 8941 */ IC_VEX_L_W_XD, /* 8942 */ IC_VEX_L_W_XD, /* 8943 */ IC_VEX_L_OPSIZE, /* 8944 */ IC_VEX_L_OPSIZE, /* 8945 */ IC_VEX_L_OPSIZE, /* 8946 */ IC_VEX_L_OPSIZE, /* 8947 */ IC_VEX_L_OPSIZE, /* 8948 */ IC_VEX_L_OPSIZE, /* 8949 */ IC_VEX_L_OPSIZE, /* 8950 */ IC_VEX_L_OPSIZE, /* 8951 */ IC_VEX_L_W_OPSIZE, /* 8952 */ IC_VEX_L_W_OPSIZE, /* 8953 */ IC_VEX_L_W_OPSIZE, /* 8954 */ IC_VEX_L_W_OPSIZE, /* 8955 */ IC_VEX_L_W_OPSIZE, /* 8956 */ IC_VEX_L_W_OPSIZE, /* 8957 */ IC_VEX_L_W_OPSIZE, /* 8958 */ IC_VEX_L_W_OPSIZE, /* 8959 */ IC_EVEX_L_B, /* 8960 */ IC_EVEX_L_B, /* 8961 */ IC_EVEX_L_XS_B, /* 8962 */ IC_EVEX_L_XS_B, /* 8963 */ IC_EVEX_L_XD_B, /* 8964 */ IC_EVEX_L_XD_B, /* 8965 */ IC_EVEX_L_XD_B, /* 8966 */ IC_EVEX_L_XD_B, /* 8967 */ IC_EVEX_L_W_B, /* 8968 */ IC_EVEX_L_W_B, /* 8969 */ IC_EVEX_L_W_XS_B, /* 8970 */ IC_EVEX_L_W_XS_B, /* 8971 */ IC_EVEX_L_W_XD_B, /* 8972 */ IC_EVEX_L_W_XD_B, /* 8973 */ IC_EVEX_L_W_XD_B, /* 8974 */ IC_EVEX_L_W_XD_B, /* 8975 */ IC_EVEX_L_OPSIZE_B, /* 8976 */ IC_EVEX_L_OPSIZE_B, /* 8977 */ IC_EVEX_L_OPSIZE_B, /* 8978 */ IC_EVEX_L_OPSIZE_B, /* 8979 */ IC_EVEX_L_OPSIZE_B, /* 8980 */ IC_EVEX_L_OPSIZE_B, /* 8981 */ IC_EVEX_L_OPSIZE_B, /* 8982 */ IC_EVEX_L_OPSIZE_B, /* 8983 */ IC_EVEX_L_W_OPSIZE_B, /* 8984 */ IC_EVEX_L_W_OPSIZE_B, /* 8985 */ IC_EVEX_L_W_OPSIZE_B, /* 8986 */ IC_EVEX_L_W_OPSIZE_B, /* 8987 */ IC_EVEX_L_W_OPSIZE_B, /* 8988 */ IC_EVEX_L_W_OPSIZE_B, /* 8989 */ IC_EVEX_L_W_OPSIZE_B, /* 8990 */ IC_EVEX_L_W_OPSIZE_B, /* 8991 */ IC_EVEX_L_B, /* 8992 */ IC_EVEX_L_B, /* 8993 */ IC_EVEX_L_XS_B, /* 8994 */ IC_EVEX_L_XS_B, /* 8995 */ IC_EVEX_L_XD_B, /* 8996 */ IC_EVEX_L_XD_B, /* 8997 */ IC_EVEX_L_XD_B, /* 8998 */ IC_EVEX_L_XD_B, /* 8999 */ IC_EVEX_L_W_B, /* 9000 */ IC_EVEX_L_W_B, /* 9001 */ IC_EVEX_L_W_XS_B, /* 9002 */ IC_EVEX_L_W_XS_B, /* 9003 */ IC_EVEX_L_W_XD_B, /* 9004 */ IC_EVEX_L_W_XD_B, /* 9005 */ IC_EVEX_L_W_XD_B, /* 9006 */ IC_EVEX_L_W_XD_B, /* 9007 */ IC_EVEX_L_OPSIZE_B, /* 9008 */ IC_EVEX_L_OPSIZE_B, /* 9009 */ IC_EVEX_L_OPSIZE_B, /* 9010 */ IC_EVEX_L_OPSIZE_B, /* 9011 */ IC_EVEX_L_OPSIZE_B, /* 9012 */ IC_EVEX_L_OPSIZE_B, /* 9013 */ IC_EVEX_L_OPSIZE_B, /* 9014 */ IC_EVEX_L_OPSIZE_B, /* 9015 */ IC_EVEX_L_W_OPSIZE_B, /* 9016 */ IC_EVEX_L_W_OPSIZE_B, /* 9017 */ IC_EVEX_L_W_OPSIZE_B, /* 9018 */ IC_EVEX_L_W_OPSIZE_B, /* 9019 */ IC_EVEX_L_W_OPSIZE_B, /* 9020 */ IC_EVEX_L_W_OPSIZE_B, /* 9021 */ IC_EVEX_L_W_OPSIZE_B, /* 9022 */ IC_EVEX_L_W_OPSIZE_B, /* 9023 */ IC_EVEX_L_B, /* 9024 */ IC_EVEX_L_B, /* 9025 */ IC_EVEX_L_XS_B, /* 9026 */ IC_EVEX_L_XS_B, /* 9027 */ IC_EVEX_L_XD_B, /* 9028 */ IC_EVEX_L_XD_B, /* 9029 */ IC_EVEX_L_XD_B, /* 9030 */ IC_EVEX_L_XD_B, /* 9031 */ IC_EVEX_L_W_B, /* 9032 */ IC_EVEX_L_W_B, /* 9033 */ IC_EVEX_L_W_XS_B, /* 9034 */ IC_EVEX_L_W_XS_B, /* 9035 */ IC_EVEX_L_W_XD_B, /* 9036 */ IC_EVEX_L_W_XD_B, /* 9037 */ IC_EVEX_L_W_XD_B, /* 9038 */ IC_EVEX_L_W_XD_B, /* 9039 */ IC_EVEX_L_OPSIZE_B, /* 9040 */ IC_EVEX_L_OPSIZE_B, /* 9041 */ IC_EVEX_L_OPSIZE_B, /* 9042 */ IC_EVEX_L_OPSIZE_B, /* 9043 */ IC_EVEX_L_OPSIZE_B, /* 9044 */ IC_EVEX_L_OPSIZE_B, /* 9045 */ IC_EVEX_L_OPSIZE_B, /* 9046 */ IC_EVEX_L_OPSIZE_B, /* 9047 */ IC_EVEX_L_W_OPSIZE_B, /* 9048 */ IC_EVEX_L_W_OPSIZE_B, /* 9049 */ IC_EVEX_L_W_OPSIZE_B, /* 9050 */ IC_EVEX_L_W_OPSIZE_B, /* 9051 */ IC_EVEX_L_W_OPSIZE_B, /* 9052 */ IC_EVEX_L_W_OPSIZE_B, /* 9053 */ IC_EVEX_L_W_OPSIZE_B, /* 9054 */ IC_EVEX_L_W_OPSIZE_B, /* 9055 */ IC_EVEX_L_B, /* 9056 */ IC_EVEX_L_B, /* 9057 */ IC_EVEX_L_XS_B, /* 9058 */ IC_EVEX_L_XS_B, /* 9059 */ IC_EVEX_L_XD_B, /* 9060 */ IC_EVEX_L_XD_B, /* 9061 */ IC_EVEX_L_XD_B, /* 9062 */ IC_EVEX_L_XD_B, /* 9063 */ IC_EVEX_L_W_B, /* 9064 */ IC_EVEX_L_W_B, /* 9065 */ IC_EVEX_L_W_XS_B, /* 9066 */ IC_EVEX_L_W_XS_B, /* 9067 */ IC_EVEX_L_W_XD_B, /* 9068 */ IC_EVEX_L_W_XD_B, /* 9069 */ IC_EVEX_L_W_XD_B, /* 9070 */ IC_EVEX_L_W_XD_B, /* 9071 */ IC_EVEX_L_OPSIZE_B, /* 9072 */ IC_EVEX_L_OPSIZE_B, /* 9073 */ IC_EVEX_L_OPSIZE_B, /* 9074 */ IC_EVEX_L_OPSIZE_B, /* 9075 */ IC_EVEX_L_OPSIZE_B, /* 9076 */ IC_EVEX_L_OPSIZE_B, /* 9077 */ IC_EVEX_L_OPSIZE_B, /* 9078 */ IC_EVEX_L_OPSIZE_B, /* 9079 */ IC_EVEX_L_W_OPSIZE_B, /* 9080 */ IC_EVEX_L_W_OPSIZE_B, /* 9081 */ IC_EVEX_L_W_OPSIZE_B, /* 9082 */ IC_EVEX_L_W_OPSIZE_B, /* 9083 */ IC_EVEX_L_W_OPSIZE_B, /* 9084 */ IC_EVEX_L_W_OPSIZE_B, /* 9085 */ IC_EVEX_L_W_OPSIZE_B, /* 9086 */ IC_EVEX_L_W_OPSIZE_B, /* 9087 */ IC_EVEX_L_B, /* 9088 */ IC_EVEX_L_B, /* 9089 */ IC_EVEX_L_XS_B, /* 9090 */ IC_EVEX_L_XS_B, /* 9091 */ IC_EVEX_L_XD_B, /* 9092 */ IC_EVEX_L_XD_B, /* 9093 */ IC_EVEX_L_XD_B, /* 9094 */ IC_EVEX_L_XD_B, /* 9095 */ IC_EVEX_L_W_B, /* 9096 */ IC_EVEX_L_W_B, /* 9097 */ IC_EVEX_L_W_XS_B, /* 9098 */ IC_EVEX_L_W_XS_B, /* 9099 */ IC_EVEX_L_W_XD_B, /* 9100 */ IC_EVEX_L_W_XD_B, /* 9101 */ IC_EVEX_L_W_XD_B, /* 9102 */ IC_EVEX_L_W_XD_B, /* 9103 */ IC_EVEX_L_OPSIZE_B, /* 9104 */ IC_EVEX_L_OPSIZE_B, /* 9105 */ IC_EVEX_L_OPSIZE_B, /* 9106 */ IC_EVEX_L_OPSIZE_B, /* 9107 */ IC_EVEX_L_OPSIZE_B, /* 9108 */ IC_EVEX_L_OPSIZE_B, /* 9109 */ IC_EVEX_L_OPSIZE_B, /* 9110 */ IC_EVEX_L_OPSIZE_B, /* 9111 */ IC_EVEX_L_W_OPSIZE_B, /* 9112 */ IC_EVEX_L_W_OPSIZE_B, /* 9113 */ IC_EVEX_L_W_OPSIZE_B, /* 9114 */ IC_EVEX_L_W_OPSIZE_B, /* 9115 */ IC_EVEX_L_W_OPSIZE_B, /* 9116 */ IC_EVEX_L_W_OPSIZE_B, /* 9117 */ IC_EVEX_L_W_OPSIZE_B, /* 9118 */ IC_EVEX_L_W_OPSIZE_B, /* 9119 */ IC_EVEX_L_B, /* 9120 */ IC_EVEX_L_B, /* 9121 */ IC_EVEX_L_XS_B, /* 9122 */ IC_EVEX_L_XS_B, /* 9123 */ IC_EVEX_L_XD_B, /* 9124 */ IC_EVEX_L_XD_B, /* 9125 */ IC_EVEX_L_XD_B, /* 9126 */ IC_EVEX_L_XD_B, /* 9127 */ IC_EVEX_L_W_B, /* 9128 */ IC_EVEX_L_W_B, /* 9129 */ IC_EVEX_L_W_XS_B, /* 9130 */ IC_EVEX_L_W_XS_B, /* 9131 */ IC_EVEX_L_W_XD_B, /* 9132 */ IC_EVEX_L_W_XD_B, /* 9133 */ IC_EVEX_L_W_XD_B, /* 9134 */ IC_EVEX_L_W_XD_B, /* 9135 */ IC_EVEX_L_OPSIZE_B, /* 9136 */ IC_EVEX_L_OPSIZE_B, /* 9137 */ IC_EVEX_L_OPSIZE_B, /* 9138 */ IC_EVEX_L_OPSIZE_B, /* 9139 */ IC_EVEX_L_OPSIZE_B, /* 9140 */ IC_EVEX_L_OPSIZE_B, /* 9141 */ IC_EVEX_L_OPSIZE_B, /* 9142 */ IC_EVEX_L_OPSIZE_B, /* 9143 */ IC_EVEX_L_W_OPSIZE_B, /* 9144 */ IC_EVEX_L_W_OPSIZE_B, /* 9145 */ IC_EVEX_L_W_OPSIZE_B, /* 9146 */ IC_EVEX_L_W_OPSIZE_B, /* 9147 */ IC_EVEX_L_W_OPSIZE_B, /* 9148 */ IC_EVEX_L_W_OPSIZE_B, /* 9149 */ IC_EVEX_L_W_OPSIZE_B, /* 9150 */ IC_EVEX_L_W_OPSIZE_B, /* 9151 */ IC_EVEX_L_B, /* 9152 */ IC_EVEX_L_B, /* 9153 */ IC_EVEX_L_XS_B, /* 9154 */ IC_EVEX_L_XS_B, /* 9155 */ IC_EVEX_L_XD_B, /* 9156 */ IC_EVEX_L_XD_B, /* 9157 */ IC_EVEX_L_XD_B, /* 9158 */ IC_EVEX_L_XD_B, /* 9159 */ IC_EVEX_L_W_B, /* 9160 */ IC_EVEX_L_W_B, /* 9161 */ IC_EVEX_L_W_XS_B, /* 9162 */ IC_EVEX_L_W_XS_B, /* 9163 */ IC_EVEX_L_W_XD_B, /* 9164 */ IC_EVEX_L_W_XD_B, /* 9165 */ IC_EVEX_L_W_XD_B, /* 9166 */ IC_EVEX_L_W_XD_B, /* 9167 */ IC_EVEX_L_OPSIZE_B, /* 9168 */ IC_EVEX_L_OPSIZE_B, /* 9169 */ IC_EVEX_L_OPSIZE_B, /* 9170 */ IC_EVEX_L_OPSIZE_B, /* 9171 */ IC_EVEX_L_OPSIZE_B, /* 9172 */ IC_EVEX_L_OPSIZE_B, /* 9173 */ IC_EVEX_L_OPSIZE_B, /* 9174 */ IC_EVEX_L_OPSIZE_B, /* 9175 */ IC_EVEX_L_W_OPSIZE_B, /* 9176 */ IC_EVEX_L_W_OPSIZE_B, /* 9177 */ IC_EVEX_L_W_OPSIZE_B, /* 9178 */ IC_EVEX_L_W_OPSIZE_B, /* 9179 */ IC_EVEX_L_W_OPSIZE_B, /* 9180 */ IC_EVEX_L_W_OPSIZE_B, /* 9181 */ IC_EVEX_L_W_OPSIZE_B, /* 9182 */ IC_EVEX_L_W_OPSIZE_B, /* 9183 */ IC_EVEX_L_B, /* 9184 */ IC_EVEX_L_B, /* 9185 */ IC_EVEX_L_XS_B, /* 9186 */ IC_EVEX_L_XS_B, /* 9187 */ IC_EVEX_L_XD_B, /* 9188 */ IC_EVEX_L_XD_B, /* 9189 */ IC_EVEX_L_XD_B, /* 9190 */ IC_EVEX_L_XD_B, /* 9191 */ IC_EVEX_L_W_B, /* 9192 */ IC_EVEX_L_W_B, /* 9193 */ IC_EVEX_L_W_XS_B, /* 9194 */ IC_EVEX_L_W_XS_B, /* 9195 */ IC_EVEX_L_W_XD_B, /* 9196 */ IC_EVEX_L_W_XD_B, /* 9197 */ IC_EVEX_L_W_XD_B, /* 9198 */ IC_EVEX_L_W_XD_B, /* 9199 */ IC_EVEX_L_OPSIZE_B, /* 9200 */ IC_EVEX_L_OPSIZE_B, /* 9201 */ IC_EVEX_L_OPSIZE_B, /* 9202 */ IC_EVEX_L_OPSIZE_B, /* 9203 */ IC_EVEX_L_OPSIZE_B, /* 9204 */ IC_EVEX_L_OPSIZE_B, /* 9205 */ IC_EVEX_L_OPSIZE_B, /* 9206 */ IC_EVEX_L_OPSIZE_B, /* 9207 */ IC_EVEX_L_W_OPSIZE_B, /* 9208 */ IC_EVEX_L_W_OPSIZE_B, /* 9209 */ IC_EVEX_L_W_OPSIZE_B, /* 9210 */ IC_EVEX_L_W_OPSIZE_B, /* 9211 */ IC_EVEX_L_W_OPSIZE_B, /* 9212 */ IC_EVEX_L_W_OPSIZE_B, /* 9213 */ IC_EVEX_L_W_OPSIZE_B, /* 9214 */ IC_EVEX_L_W_OPSIZE_B, /* 9215 */ IC, /* 9216 */ IC_64BIT, /* 9217 */ IC_XS, /* 9218 */ IC_64BIT_XS, /* 9219 */ IC_XD, /* 9220 */ IC_64BIT_XD, /* 9221 */ IC_XS, /* 9222 */ IC_64BIT_XS, /* 9223 */ IC, /* 9224 */ IC_64BIT_REXW, /* 9225 */ IC_XS, /* 9226 */ IC_64BIT_REXW_XS, /* 9227 */ IC_XD, /* 9228 */ IC_64BIT_REXW_XD, /* 9229 */ IC_XS, /* 9230 */ IC_64BIT_REXW_XS, /* 9231 */ IC_OPSIZE, /* 9232 */ IC_64BIT_OPSIZE, /* 9233 */ IC_XS_OPSIZE, /* 9234 */ IC_64BIT_XS_OPSIZE, /* 9235 */ IC_XD_OPSIZE, /* 9236 */ IC_64BIT_XD_OPSIZE, /* 9237 */ IC_XS_OPSIZE, /* 9238 */ IC_64BIT_XD_OPSIZE, /* 9239 */ IC_OPSIZE, /* 9240 */ IC_64BIT_REXW_OPSIZE, /* 9241 */ IC_XS_OPSIZE, /* 9242 */ IC_64BIT_REXW_XS, /* 9243 */ IC_XD_OPSIZE, /* 9244 */ IC_64BIT_REXW_XD, /* 9245 */ IC_XS_OPSIZE, /* 9246 */ IC_64BIT_REXW_XS, /* 9247 */ IC_ADSIZE, /* 9248 */ IC_64BIT_ADSIZE, /* 9249 */ IC_XS_ADSIZE, /* 9250 */ IC_64BIT_XS_ADSIZE, /* 9251 */ IC_XD_ADSIZE, /* 9252 */ IC_64BIT_XD_ADSIZE, /* 9253 */ IC_XS_ADSIZE, /* 9254 */ IC_64BIT_XD_ADSIZE, /* 9255 */ IC_ADSIZE, /* 9256 */ IC_64BIT_REXW_ADSIZE, /* 9257 */ IC_XS_ADSIZE, /* 9258 */ IC_64BIT_REXW_XS, /* 9259 */ IC_XD_ADSIZE, /* 9260 */ IC_64BIT_REXW_XD, /* 9261 */ IC_XS_ADSIZE, /* 9262 */ IC_64BIT_REXW_XS, /* 9263 */ IC_OPSIZE_ADSIZE, /* 9264 */ IC_64BIT_OPSIZE_ADSIZE, /* 9265 */ IC_XS_OPSIZE, /* 9266 */ IC_64BIT_XS_OPSIZE, /* 9267 */ IC_XD_OPSIZE, /* 9268 */ IC_64BIT_XD_OPSIZE, /* 9269 */ IC_XS_OPSIZE, /* 9270 */ IC_64BIT_XD_OPSIZE, /* 9271 */ IC_OPSIZE_ADSIZE, /* 9272 */ IC_64BIT_REXW_OPSIZE, /* 9273 */ IC_XS_OPSIZE, /* 9274 */ IC_64BIT_REXW_XS, /* 9275 */ IC_XD_OPSIZE, /* 9276 */ IC_64BIT_REXW_XD, /* 9277 */ IC_XS_OPSIZE, /* 9278 */ IC_64BIT_REXW_XS, /* 9279 */ IC_VEX, /* 9280 */ IC_VEX, /* 9281 */ IC_VEX_XS, /* 9282 */ IC_VEX_XS, /* 9283 */ IC_VEX_XD, /* 9284 */ IC_VEX_XD, /* 9285 */ IC_VEX_XD, /* 9286 */ IC_VEX_XD, /* 9287 */ IC_VEX_W, /* 9288 */ IC_VEX_W, /* 9289 */ IC_VEX_W_XS, /* 9290 */ IC_VEX_W_XS, /* 9291 */ IC_VEX_W_XD, /* 9292 */ IC_VEX_W_XD, /* 9293 */ IC_VEX_W_XD, /* 9294 */ IC_VEX_W_XD, /* 9295 */ IC_VEX_OPSIZE, /* 9296 */ IC_VEX_OPSIZE, /* 9297 */ IC_VEX_OPSIZE, /* 9298 */ IC_VEX_OPSIZE, /* 9299 */ IC_VEX_OPSIZE, /* 9300 */ IC_VEX_OPSIZE, /* 9301 */ IC_VEX_OPSIZE, /* 9302 */ IC_VEX_OPSIZE, /* 9303 */ IC_VEX_W_OPSIZE, /* 9304 */ IC_VEX_W_OPSIZE, /* 9305 */ IC_VEX_W_OPSIZE, /* 9306 */ IC_VEX_W_OPSIZE, /* 9307 */ IC_VEX_W_OPSIZE, /* 9308 */ IC_VEX_W_OPSIZE, /* 9309 */ IC_VEX_W_OPSIZE, /* 9310 */ IC_VEX_W_OPSIZE, /* 9311 */ IC_VEX, /* 9312 */ IC_VEX, /* 9313 */ IC_VEX_XS, /* 9314 */ IC_VEX_XS, /* 9315 */ IC_VEX_XD, /* 9316 */ IC_VEX_XD, /* 9317 */ IC_VEX_XD, /* 9318 */ IC_VEX_XD, /* 9319 */ IC_VEX_W, /* 9320 */ IC_VEX_W, /* 9321 */ IC_VEX_W_XS, /* 9322 */ IC_VEX_W_XS, /* 9323 */ IC_VEX_W_XD, /* 9324 */ IC_VEX_W_XD, /* 9325 */ IC_VEX_W_XD, /* 9326 */ IC_VEX_W_XD, /* 9327 */ IC_VEX_OPSIZE, /* 9328 */ IC_VEX_OPSIZE, /* 9329 */ IC_VEX_OPSIZE, /* 9330 */ IC_VEX_OPSIZE, /* 9331 */ IC_VEX_OPSIZE, /* 9332 */ IC_VEX_OPSIZE, /* 9333 */ IC_VEX_OPSIZE, /* 9334 */ IC_VEX_OPSIZE, /* 9335 */ IC_VEX_W_OPSIZE, /* 9336 */ IC_VEX_W_OPSIZE, /* 9337 */ IC_VEX_W_OPSIZE, /* 9338 */ IC_VEX_W_OPSIZE, /* 9339 */ IC_VEX_W_OPSIZE, /* 9340 */ IC_VEX_W_OPSIZE, /* 9341 */ IC_VEX_W_OPSIZE, /* 9342 */ IC_VEX_W_OPSIZE, /* 9343 */ IC_VEX_L, /* 9344 */ IC_VEX_L, /* 9345 */ IC_VEX_L_XS, /* 9346 */ IC_VEX_L_XS, /* 9347 */ IC_VEX_L_XD, /* 9348 */ IC_VEX_L_XD, /* 9349 */ IC_VEX_L_XD, /* 9350 */ IC_VEX_L_XD, /* 9351 */ IC_VEX_L_W, /* 9352 */ IC_VEX_L_W, /* 9353 */ IC_VEX_L_W_XS, /* 9354 */ IC_VEX_L_W_XS, /* 9355 */ IC_VEX_L_W_XD, /* 9356 */ IC_VEX_L_W_XD, /* 9357 */ IC_VEX_L_W_XD, /* 9358 */ IC_VEX_L_W_XD, /* 9359 */ IC_VEX_L_OPSIZE, /* 9360 */ IC_VEX_L_OPSIZE, /* 9361 */ IC_VEX_L_OPSIZE, /* 9362 */ IC_VEX_L_OPSIZE, /* 9363 */ IC_VEX_L_OPSIZE, /* 9364 */ IC_VEX_L_OPSIZE, /* 9365 */ IC_VEX_L_OPSIZE, /* 9366 */ IC_VEX_L_OPSIZE, /* 9367 */ IC_VEX_L_W_OPSIZE, /* 9368 */ IC_VEX_L_W_OPSIZE, /* 9369 */ IC_VEX_L_W_OPSIZE, /* 9370 */ IC_VEX_L_W_OPSIZE, /* 9371 */ IC_VEX_L_W_OPSIZE, /* 9372 */ IC_VEX_L_W_OPSIZE, /* 9373 */ IC_VEX_L_W_OPSIZE, /* 9374 */ IC_VEX_L_W_OPSIZE, /* 9375 */ IC_VEX_L, /* 9376 */ IC_VEX_L, /* 9377 */ IC_VEX_L_XS, /* 9378 */ IC_VEX_L_XS, /* 9379 */ IC_VEX_L_XD, /* 9380 */ IC_VEX_L_XD, /* 9381 */ IC_VEX_L_XD, /* 9382 */ IC_VEX_L_XD, /* 9383 */ IC_VEX_L_W, /* 9384 */ IC_VEX_L_W, /* 9385 */ IC_VEX_L_W_XS, /* 9386 */ IC_VEX_L_W_XS, /* 9387 */ IC_VEX_L_W_XD, /* 9388 */ IC_VEX_L_W_XD, /* 9389 */ IC_VEX_L_W_XD, /* 9390 */ IC_VEX_L_W_XD, /* 9391 */ IC_VEX_L_OPSIZE, /* 9392 */ IC_VEX_L_OPSIZE, /* 9393 */ IC_VEX_L_OPSIZE, /* 9394 */ IC_VEX_L_OPSIZE, /* 9395 */ IC_VEX_L_OPSIZE, /* 9396 */ IC_VEX_L_OPSIZE, /* 9397 */ IC_VEX_L_OPSIZE, /* 9398 */ IC_VEX_L_OPSIZE, /* 9399 */ IC_VEX_L_W_OPSIZE, /* 9400 */ IC_VEX_L_W_OPSIZE, /* 9401 */ IC_VEX_L_W_OPSIZE, /* 9402 */ IC_VEX_L_W_OPSIZE, /* 9403 */ IC_VEX_L_W_OPSIZE, /* 9404 */ IC_VEX_L_W_OPSIZE, /* 9405 */ IC_VEX_L_W_OPSIZE, /* 9406 */ IC_VEX_L_W_OPSIZE, /* 9407 */ IC_VEX_L, /* 9408 */ IC_VEX_L, /* 9409 */ IC_VEX_L_XS, /* 9410 */ IC_VEX_L_XS, /* 9411 */ IC_VEX_L_XD, /* 9412 */ IC_VEX_L_XD, /* 9413 */ IC_VEX_L_XD, /* 9414 */ IC_VEX_L_XD, /* 9415 */ IC_VEX_L_W, /* 9416 */ IC_VEX_L_W, /* 9417 */ IC_VEX_L_W_XS, /* 9418 */ IC_VEX_L_W_XS, /* 9419 */ IC_VEX_L_W_XD, /* 9420 */ IC_VEX_L_W_XD, /* 9421 */ IC_VEX_L_W_XD, /* 9422 */ IC_VEX_L_W_XD, /* 9423 */ IC_VEX_L_OPSIZE, /* 9424 */ IC_VEX_L_OPSIZE, /* 9425 */ IC_VEX_L_OPSIZE, /* 9426 */ IC_VEX_L_OPSIZE, /* 9427 */ IC_VEX_L_OPSIZE, /* 9428 */ IC_VEX_L_OPSIZE, /* 9429 */ IC_VEX_L_OPSIZE, /* 9430 */ IC_VEX_L_OPSIZE, /* 9431 */ IC_VEX_L_W_OPSIZE, /* 9432 */ IC_VEX_L_W_OPSIZE, /* 9433 */ IC_VEX_L_W_OPSIZE, /* 9434 */ IC_VEX_L_W_OPSIZE, /* 9435 */ IC_VEX_L_W_OPSIZE, /* 9436 */ IC_VEX_L_W_OPSIZE, /* 9437 */ IC_VEX_L_W_OPSIZE, /* 9438 */ IC_VEX_L_W_OPSIZE, /* 9439 */ IC_VEX_L, /* 9440 */ IC_VEX_L, /* 9441 */ IC_VEX_L_XS, /* 9442 */ IC_VEX_L_XS, /* 9443 */ IC_VEX_L_XD, /* 9444 */ IC_VEX_L_XD, /* 9445 */ IC_VEX_L_XD, /* 9446 */ IC_VEX_L_XD, /* 9447 */ IC_VEX_L_W, /* 9448 */ IC_VEX_L_W, /* 9449 */ IC_VEX_L_W_XS, /* 9450 */ IC_VEX_L_W_XS, /* 9451 */ IC_VEX_L_W_XD, /* 9452 */ IC_VEX_L_W_XD, /* 9453 */ IC_VEX_L_W_XD, /* 9454 */ IC_VEX_L_W_XD, /* 9455 */ IC_VEX_L_OPSIZE, /* 9456 */ IC_VEX_L_OPSIZE, /* 9457 */ IC_VEX_L_OPSIZE, /* 9458 */ IC_VEX_L_OPSIZE, /* 9459 */ IC_VEX_L_OPSIZE, /* 9460 */ IC_VEX_L_OPSIZE, /* 9461 */ IC_VEX_L_OPSIZE, /* 9462 */ IC_VEX_L_OPSIZE, /* 9463 */ IC_VEX_L_W_OPSIZE, /* 9464 */ IC_VEX_L_W_OPSIZE, /* 9465 */ IC_VEX_L_W_OPSIZE, /* 9466 */ IC_VEX_L_W_OPSIZE, /* 9467 */ IC_VEX_L_W_OPSIZE, /* 9468 */ IC_VEX_L_W_OPSIZE, /* 9469 */ IC_VEX_L_W_OPSIZE, /* 9470 */ IC_VEX_L_W_OPSIZE, /* 9471 */ IC_EVEX_L2_B, /* 9472 */ IC_EVEX_L2_B, /* 9473 */ IC_EVEX_L2_XS_B, /* 9474 */ IC_EVEX_L2_XS_B, /* 9475 */ IC_EVEX_L2_XD_B, /* 9476 */ IC_EVEX_L2_XD_B, /* 9477 */ IC_EVEX_L2_XD_B, /* 9478 */ IC_EVEX_L2_XD_B, /* 9479 */ IC_EVEX_L2_W_B, /* 9480 */ IC_EVEX_L2_W_B, /* 9481 */ IC_EVEX_L2_W_XS_B, /* 9482 */ IC_EVEX_L2_W_XS_B, /* 9483 */ IC_EVEX_L2_W_XD_B, /* 9484 */ IC_EVEX_L2_W_XD_B, /* 9485 */ IC_EVEX_L2_W_XD_B, /* 9486 */ IC_EVEX_L2_W_XD_B, /* 9487 */ IC_EVEX_L2_OPSIZE_B, /* 9488 */ IC_EVEX_L2_OPSIZE_B, /* 9489 */ IC_EVEX_L2_OPSIZE_B, /* 9490 */ IC_EVEX_L2_OPSIZE_B, /* 9491 */ IC_EVEX_L2_OPSIZE_B, /* 9492 */ IC_EVEX_L2_OPSIZE_B, /* 9493 */ IC_EVEX_L2_OPSIZE_B, /* 9494 */ IC_EVEX_L2_OPSIZE_B, /* 9495 */ IC_EVEX_L2_W_OPSIZE_B, /* 9496 */ IC_EVEX_L2_W_OPSIZE_B, /* 9497 */ IC_EVEX_L2_W_OPSIZE_B, /* 9498 */ IC_EVEX_L2_W_OPSIZE_B, /* 9499 */ IC_EVEX_L2_W_OPSIZE_B, /* 9500 */ IC_EVEX_L2_W_OPSIZE_B, /* 9501 */ IC_EVEX_L2_W_OPSIZE_B, /* 9502 */ IC_EVEX_L2_W_OPSIZE_B, /* 9503 */ IC_EVEX_L2_B, /* 9504 */ IC_EVEX_L2_B, /* 9505 */ IC_EVEX_L2_XS_B, /* 9506 */ IC_EVEX_L2_XS_B, /* 9507 */ IC_EVEX_L2_XD_B, /* 9508 */ IC_EVEX_L2_XD_B, /* 9509 */ IC_EVEX_L2_XD_B, /* 9510 */ IC_EVEX_L2_XD_B, /* 9511 */ IC_EVEX_L2_W_B, /* 9512 */ IC_EVEX_L2_W_B, /* 9513 */ IC_EVEX_L2_W_XS_B, /* 9514 */ IC_EVEX_L2_W_XS_B, /* 9515 */ IC_EVEX_L2_W_XD_B, /* 9516 */ IC_EVEX_L2_W_XD_B, /* 9517 */ IC_EVEX_L2_W_XD_B, /* 9518 */ IC_EVEX_L2_W_XD_B, /* 9519 */ IC_EVEX_L2_OPSIZE_B, /* 9520 */ IC_EVEX_L2_OPSIZE_B, /* 9521 */ IC_EVEX_L2_OPSIZE_B, /* 9522 */ IC_EVEX_L2_OPSIZE_B, /* 9523 */ IC_EVEX_L2_OPSIZE_B, /* 9524 */ IC_EVEX_L2_OPSIZE_B, /* 9525 */ IC_EVEX_L2_OPSIZE_B, /* 9526 */ IC_EVEX_L2_OPSIZE_B, /* 9527 */ IC_EVEX_L2_W_OPSIZE_B, /* 9528 */ IC_EVEX_L2_W_OPSIZE_B, /* 9529 */ IC_EVEX_L2_W_OPSIZE_B, /* 9530 */ IC_EVEX_L2_W_OPSIZE_B, /* 9531 */ IC_EVEX_L2_W_OPSIZE_B, /* 9532 */ IC_EVEX_L2_W_OPSIZE_B, /* 9533 */ IC_EVEX_L2_W_OPSIZE_B, /* 9534 */ IC_EVEX_L2_W_OPSIZE_B, /* 9535 */ IC_EVEX_L2_B, /* 9536 */ IC_EVEX_L2_B, /* 9537 */ IC_EVEX_L2_XS_B, /* 9538 */ IC_EVEX_L2_XS_B, /* 9539 */ IC_EVEX_L2_XD_B, /* 9540 */ IC_EVEX_L2_XD_B, /* 9541 */ IC_EVEX_L2_XD_B, /* 9542 */ IC_EVEX_L2_XD_B, /* 9543 */ IC_EVEX_L2_W_B, /* 9544 */ IC_EVEX_L2_W_B, /* 9545 */ IC_EVEX_L2_W_XS_B, /* 9546 */ IC_EVEX_L2_W_XS_B, /* 9547 */ IC_EVEX_L2_W_XD_B, /* 9548 */ IC_EVEX_L2_W_XD_B, /* 9549 */ IC_EVEX_L2_W_XD_B, /* 9550 */ IC_EVEX_L2_W_XD_B, /* 9551 */ IC_EVEX_L2_OPSIZE_B, /* 9552 */ IC_EVEX_L2_OPSIZE_B, /* 9553 */ IC_EVEX_L2_OPSIZE_B, /* 9554 */ IC_EVEX_L2_OPSIZE_B, /* 9555 */ IC_EVEX_L2_OPSIZE_B, /* 9556 */ IC_EVEX_L2_OPSIZE_B, /* 9557 */ IC_EVEX_L2_OPSIZE_B, /* 9558 */ IC_EVEX_L2_OPSIZE_B, /* 9559 */ IC_EVEX_L2_W_OPSIZE_B, /* 9560 */ IC_EVEX_L2_W_OPSIZE_B, /* 9561 */ IC_EVEX_L2_W_OPSIZE_B, /* 9562 */ IC_EVEX_L2_W_OPSIZE_B, /* 9563 */ IC_EVEX_L2_W_OPSIZE_B, /* 9564 */ IC_EVEX_L2_W_OPSIZE_B, /* 9565 */ IC_EVEX_L2_W_OPSIZE_B, /* 9566 */ IC_EVEX_L2_W_OPSIZE_B, /* 9567 */ IC_EVEX_L2_B, /* 9568 */ IC_EVEX_L2_B, /* 9569 */ IC_EVEX_L2_XS_B, /* 9570 */ IC_EVEX_L2_XS_B, /* 9571 */ IC_EVEX_L2_XD_B, /* 9572 */ IC_EVEX_L2_XD_B, /* 9573 */ IC_EVEX_L2_XD_B, /* 9574 */ IC_EVEX_L2_XD_B, /* 9575 */ IC_EVEX_L2_W_B, /* 9576 */ IC_EVEX_L2_W_B, /* 9577 */ IC_EVEX_L2_W_XS_B, /* 9578 */ IC_EVEX_L2_W_XS_B, /* 9579 */ IC_EVEX_L2_W_XD_B, /* 9580 */ IC_EVEX_L2_W_XD_B, /* 9581 */ IC_EVEX_L2_W_XD_B, /* 9582 */ IC_EVEX_L2_W_XD_B, /* 9583 */ IC_EVEX_L2_OPSIZE_B, /* 9584 */ IC_EVEX_L2_OPSIZE_B, /* 9585 */ IC_EVEX_L2_OPSIZE_B, /* 9586 */ IC_EVEX_L2_OPSIZE_B, /* 9587 */ IC_EVEX_L2_OPSIZE_B, /* 9588 */ IC_EVEX_L2_OPSIZE_B, /* 9589 */ IC_EVEX_L2_OPSIZE_B, /* 9590 */ IC_EVEX_L2_OPSIZE_B, /* 9591 */ IC_EVEX_L2_W_OPSIZE_B, /* 9592 */ IC_EVEX_L2_W_OPSIZE_B, /* 9593 */ IC_EVEX_L2_W_OPSIZE_B, /* 9594 */ IC_EVEX_L2_W_OPSIZE_B, /* 9595 */ IC_EVEX_L2_W_OPSIZE_B, /* 9596 */ IC_EVEX_L2_W_OPSIZE_B, /* 9597 */ IC_EVEX_L2_W_OPSIZE_B, /* 9598 */ IC_EVEX_L2_W_OPSIZE_B, /* 9599 */ IC_EVEX_L2_B, /* 9600 */ IC_EVEX_L2_B, /* 9601 */ IC_EVEX_L2_XS_B, /* 9602 */ IC_EVEX_L2_XS_B, /* 9603 */ IC_EVEX_L2_XD_B, /* 9604 */ IC_EVEX_L2_XD_B, /* 9605 */ IC_EVEX_L2_XD_B, /* 9606 */ IC_EVEX_L2_XD_B, /* 9607 */ IC_EVEX_L2_W_B, /* 9608 */ IC_EVEX_L2_W_B, /* 9609 */ IC_EVEX_L2_W_XS_B, /* 9610 */ IC_EVEX_L2_W_XS_B, /* 9611 */ IC_EVEX_L2_W_XD_B, /* 9612 */ IC_EVEX_L2_W_XD_B, /* 9613 */ IC_EVEX_L2_W_XD_B, /* 9614 */ IC_EVEX_L2_W_XD_B, /* 9615 */ IC_EVEX_L2_OPSIZE_B, /* 9616 */ IC_EVEX_L2_OPSIZE_B, /* 9617 */ IC_EVEX_L2_OPSIZE_B, /* 9618 */ IC_EVEX_L2_OPSIZE_B, /* 9619 */ IC_EVEX_L2_OPSIZE_B, /* 9620 */ IC_EVEX_L2_OPSIZE_B, /* 9621 */ IC_EVEX_L2_OPSIZE_B, /* 9622 */ IC_EVEX_L2_OPSIZE_B, /* 9623 */ IC_EVEX_L2_W_OPSIZE_B, /* 9624 */ IC_EVEX_L2_W_OPSIZE_B, /* 9625 */ IC_EVEX_L2_W_OPSIZE_B, /* 9626 */ IC_EVEX_L2_W_OPSIZE_B, /* 9627 */ IC_EVEX_L2_W_OPSIZE_B, /* 9628 */ IC_EVEX_L2_W_OPSIZE_B, /* 9629 */ IC_EVEX_L2_W_OPSIZE_B, /* 9630 */ IC_EVEX_L2_W_OPSIZE_B, /* 9631 */ IC_EVEX_L2_B, /* 9632 */ IC_EVEX_L2_B, /* 9633 */ IC_EVEX_L2_XS_B, /* 9634 */ IC_EVEX_L2_XS_B, /* 9635 */ IC_EVEX_L2_XD_B, /* 9636 */ IC_EVEX_L2_XD_B, /* 9637 */ IC_EVEX_L2_XD_B, /* 9638 */ IC_EVEX_L2_XD_B, /* 9639 */ IC_EVEX_L2_W_B, /* 9640 */ IC_EVEX_L2_W_B, /* 9641 */ IC_EVEX_L2_W_XS_B, /* 9642 */ IC_EVEX_L2_W_XS_B, /* 9643 */ IC_EVEX_L2_W_XD_B, /* 9644 */ IC_EVEX_L2_W_XD_B, /* 9645 */ IC_EVEX_L2_W_XD_B, /* 9646 */ IC_EVEX_L2_W_XD_B, /* 9647 */ IC_EVEX_L2_OPSIZE_B, /* 9648 */ IC_EVEX_L2_OPSIZE_B, /* 9649 */ IC_EVEX_L2_OPSIZE_B, /* 9650 */ IC_EVEX_L2_OPSIZE_B, /* 9651 */ IC_EVEX_L2_OPSIZE_B, /* 9652 */ IC_EVEX_L2_OPSIZE_B, /* 9653 */ IC_EVEX_L2_OPSIZE_B, /* 9654 */ IC_EVEX_L2_OPSIZE_B, /* 9655 */ IC_EVEX_L2_W_OPSIZE_B, /* 9656 */ IC_EVEX_L2_W_OPSIZE_B, /* 9657 */ IC_EVEX_L2_W_OPSIZE_B, /* 9658 */ IC_EVEX_L2_W_OPSIZE_B, /* 9659 */ IC_EVEX_L2_W_OPSIZE_B, /* 9660 */ IC_EVEX_L2_W_OPSIZE_B, /* 9661 */ IC_EVEX_L2_W_OPSIZE_B, /* 9662 */ IC_EVEX_L2_W_OPSIZE_B, /* 9663 */ IC_EVEX_L2_B, /* 9664 */ IC_EVEX_L2_B, /* 9665 */ IC_EVEX_L2_XS_B, /* 9666 */ IC_EVEX_L2_XS_B, /* 9667 */ IC_EVEX_L2_XD_B, /* 9668 */ IC_EVEX_L2_XD_B, /* 9669 */ IC_EVEX_L2_XD_B, /* 9670 */ IC_EVEX_L2_XD_B, /* 9671 */ IC_EVEX_L2_W_B, /* 9672 */ IC_EVEX_L2_W_B, /* 9673 */ IC_EVEX_L2_W_XS_B, /* 9674 */ IC_EVEX_L2_W_XS_B, /* 9675 */ IC_EVEX_L2_W_XD_B, /* 9676 */ IC_EVEX_L2_W_XD_B, /* 9677 */ IC_EVEX_L2_W_XD_B, /* 9678 */ IC_EVEX_L2_W_XD_B, /* 9679 */ IC_EVEX_L2_OPSIZE_B, /* 9680 */ IC_EVEX_L2_OPSIZE_B, /* 9681 */ IC_EVEX_L2_OPSIZE_B, /* 9682 */ IC_EVEX_L2_OPSIZE_B, /* 9683 */ IC_EVEX_L2_OPSIZE_B, /* 9684 */ IC_EVEX_L2_OPSIZE_B, /* 9685 */ IC_EVEX_L2_OPSIZE_B, /* 9686 */ IC_EVEX_L2_OPSIZE_B, /* 9687 */ IC_EVEX_L2_W_OPSIZE_B, /* 9688 */ IC_EVEX_L2_W_OPSIZE_B, /* 9689 */ IC_EVEX_L2_W_OPSIZE_B, /* 9690 */ IC_EVEX_L2_W_OPSIZE_B, /* 9691 */ IC_EVEX_L2_W_OPSIZE_B, /* 9692 */ IC_EVEX_L2_W_OPSIZE_B, /* 9693 */ IC_EVEX_L2_W_OPSIZE_B, /* 9694 */ IC_EVEX_L2_W_OPSIZE_B, /* 9695 */ IC_EVEX_L2_B, /* 9696 */ IC_EVEX_L2_B, /* 9697 */ IC_EVEX_L2_XS_B, /* 9698 */ IC_EVEX_L2_XS_B, /* 9699 */ IC_EVEX_L2_XD_B, /* 9700 */ IC_EVEX_L2_XD_B, /* 9701 */ IC_EVEX_L2_XD_B, /* 9702 */ IC_EVEX_L2_XD_B, /* 9703 */ IC_EVEX_L2_W_B, /* 9704 */ IC_EVEX_L2_W_B, /* 9705 */ IC_EVEX_L2_W_XS_B, /* 9706 */ IC_EVEX_L2_W_XS_B, /* 9707 */ IC_EVEX_L2_W_XD_B, /* 9708 */ IC_EVEX_L2_W_XD_B, /* 9709 */ IC_EVEX_L2_W_XD_B, /* 9710 */ IC_EVEX_L2_W_XD_B, /* 9711 */ IC_EVEX_L2_OPSIZE_B, /* 9712 */ IC_EVEX_L2_OPSIZE_B, /* 9713 */ IC_EVEX_L2_OPSIZE_B, /* 9714 */ IC_EVEX_L2_OPSIZE_B, /* 9715 */ IC_EVEX_L2_OPSIZE_B, /* 9716 */ IC_EVEX_L2_OPSIZE_B, /* 9717 */ IC_EVEX_L2_OPSIZE_B, /* 9718 */ IC_EVEX_L2_OPSIZE_B, /* 9719 */ IC_EVEX_L2_W_OPSIZE_B, /* 9720 */ IC_EVEX_L2_W_OPSIZE_B, /* 9721 */ IC_EVEX_L2_W_OPSIZE_B, /* 9722 */ IC_EVEX_L2_W_OPSIZE_B, /* 9723 */ IC_EVEX_L2_W_OPSIZE_B, /* 9724 */ IC_EVEX_L2_W_OPSIZE_B, /* 9725 */ IC_EVEX_L2_W_OPSIZE_B, /* 9726 */ IC_EVEX_L2_W_OPSIZE_B, /* 9727 */ IC, /* 9728 */ IC_64BIT, /* 9729 */ IC_XS, /* 9730 */ IC_64BIT_XS, /* 9731 */ IC_XD, /* 9732 */ IC_64BIT_XD, /* 9733 */ IC_XS, /* 9734 */ IC_64BIT_XS, /* 9735 */ IC, /* 9736 */ IC_64BIT_REXW, /* 9737 */ IC_XS, /* 9738 */ IC_64BIT_REXW_XS, /* 9739 */ IC_XD, /* 9740 */ IC_64BIT_REXW_XD, /* 9741 */ IC_XS, /* 9742 */ IC_64BIT_REXW_XS, /* 9743 */ IC_OPSIZE, /* 9744 */ IC_64BIT_OPSIZE, /* 9745 */ IC_XS_OPSIZE, /* 9746 */ IC_64BIT_XS_OPSIZE, /* 9747 */ IC_XD_OPSIZE, /* 9748 */ IC_64BIT_XD_OPSIZE, /* 9749 */ IC_XS_OPSIZE, /* 9750 */ IC_64BIT_XD_OPSIZE, /* 9751 */ IC_OPSIZE, /* 9752 */ IC_64BIT_REXW_OPSIZE, /* 9753 */ IC_XS_OPSIZE, /* 9754 */ IC_64BIT_REXW_XS, /* 9755 */ IC_XD_OPSIZE, /* 9756 */ IC_64BIT_REXW_XD, /* 9757 */ IC_XS_OPSIZE, /* 9758 */ IC_64BIT_REXW_XS, /* 9759 */ IC_ADSIZE, /* 9760 */ IC_64BIT_ADSIZE, /* 9761 */ IC_XS_ADSIZE, /* 9762 */ IC_64BIT_XS_ADSIZE, /* 9763 */ IC_XD_ADSIZE, /* 9764 */ IC_64BIT_XD_ADSIZE, /* 9765 */ IC_XS_ADSIZE, /* 9766 */ IC_64BIT_XD_ADSIZE, /* 9767 */ IC_ADSIZE, /* 9768 */ IC_64BIT_REXW_ADSIZE, /* 9769 */ IC_XS_ADSIZE, /* 9770 */ IC_64BIT_REXW_XS, /* 9771 */ IC_XD_ADSIZE, /* 9772 */ IC_64BIT_REXW_XD, /* 9773 */ IC_XS_ADSIZE, /* 9774 */ IC_64BIT_REXW_XS, /* 9775 */ IC_OPSIZE_ADSIZE, /* 9776 */ IC_64BIT_OPSIZE_ADSIZE, /* 9777 */ IC_XS_OPSIZE, /* 9778 */ IC_64BIT_XS_OPSIZE, /* 9779 */ IC_XD_OPSIZE, /* 9780 */ IC_64BIT_XD_OPSIZE, /* 9781 */ IC_XS_OPSIZE, /* 9782 */ IC_64BIT_XD_OPSIZE, /* 9783 */ IC_OPSIZE_ADSIZE, /* 9784 */ IC_64BIT_REXW_OPSIZE, /* 9785 */ IC_XS_OPSIZE, /* 9786 */ IC_64BIT_REXW_XS, /* 9787 */ IC_XD_OPSIZE, /* 9788 */ IC_64BIT_REXW_XD, /* 9789 */ IC_XS_OPSIZE, /* 9790 */ IC_64BIT_REXW_XS, /* 9791 */ IC_VEX, /* 9792 */ IC_VEX, /* 9793 */ IC_VEX_XS, /* 9794 */ IC_VEX_XS, /* 9795 */ IC_VEX_XD, /* 9796 */ IC_VEX_XD, /* 9797 */ IC_VEX_XD, /* 9798 */ IC_VEX_XD, /* 9799 */ IC_VEX_W, /* 9800 */ IC_VEX_W, /* 9801 */ IC_VEX_W_XS, /* 9802 */ IC_VEX_W_XS, /* 9803 */ IC_VEX_W_XD, /* 9804 */ IC_VEX_W_XD, /* 9805 */ IC_VEX_W_XD, /* 9806 */ IC_VEX_W_XD, /* 9807 */ IC_VEX_OPSIZE, /* 9808 */ IC_VEX_OPSIZE, /* 9809 */ IC_VEX_OPSIZE, /* 9810 */ IC_VEX_OPSIZE, /* 9811 */ IC_VEX_OPSIZE, /* 9812 */ IC_VEX_OPSIZE, /* 9813 */ IC_VEX_OPSIZE, /* 9814 */ IC_VEX_OPSIZE, /* 9815 */ IC_VEX_W_OPSIZE, /* 9816 */ IC_VEX_W_OPSIZE, /* 9817 */ IC_VEX_W_OPSIZE, /* 9818 */ IC_VEX_W_OPSIZE, /* 9819 */ IC_VEX_W_OPSIZE, /* 9820 */ IC_VEX_W_OPSIZE, /* 9821 */ IC_VEX_W_OPSIZE, /* 9822 */ IC_VEX_W_OPSIZE, /* 9823 */ IC_VEX, /* 9824 */ IC_VEX, /* 9825 */ IC_VEX_XS, /* 9826 */ IC_VEX_XS, /* 9827 */ IC_VEX_XD, /* 9828 */ IC_VEX_XD, /* 9829 */ IC_VEX_XD, /* 9830 */ IC_VEX_XD, /* 9831 */ IC_VEX_W, /* 9832 */ IC_VEX_W, /* 9833 */ IC_VEX_W_XS, /* 9834 */ IC_VEX_W_XS, /* 9835 */ IC_VEX_W_XD, /* 9836 */ IC_VEX_W_XD, /* 9837 */ IC_VEX_W_XD, /* 9838 */ IC_VEX_W_XD, /* 9839 */ IC_VEX_OPSIZE, /* 9840 */ IC_VEX_OPSIZE, /* 9841 */ IC_VEX_OPSIZE, /* 9842 */ IC_VEX_OPSIZE, /* 9843 */ IC_VEX_OPSIZE, /* 9844 */ IC_VEX_OPSIZE, /* 9845 */ IC_VEX_OPSIZE, /* 9846 */ IC_VEX_OPSIZE, /* 9847 */ IC_VEX_W_OPSIZE, /* 9848 */ IC_VEX_W_OPSIZE, /* 9849 */ IC_VEX_W_OPSIZE, /* 9850 */ IC_VEX_W_OPSIZE, /* 9851 */ IC_VEX_W_OPSIZE, /* 9852 */ IC_VEX_W_OPSIZE, /* 9853 */ IC_VEX_W_OPSIZE, /* 9854 */ IC_VEX_W_OPSIZE, /* 9855 */ IC_VEX_L, /* 9856 */ IC_VEX_L, /* 9857 */ IC_VEX_L_XS, /* 9858 */ IC_VEX_L_XS, /* 9859 */ IC_VEX_L_XD, /* 9860 */ IC_VEX_L_XD, /* 9861 */ IC_VEX_L_XD, /* 9862 */ IC_VEX_L_XD, /* 9863 */ IC_VEX_L_W, /* 9864 */ IC_VEX_L_W, /* 9865 */ IC_VEX_L_W_XS, /* 9866 */ IC_VEX_L_W_XS, /* 9867 */ IC_VEX_L_W_XD, /* 9868 */ IC_VEX_L_W_XD, /* 9869 */ IC_VEX_L_W_XD, /* 9870 */ IC_VEX_L_W_XD, /* 9871 */ IC_VEX_L_OPSIZE, /* 9872 */ IC_VEX_L_OPSIZE, /* 9873 */ IC_VEX_L_OPSIZE, /* 9874 */ IC_VEX_L_OPSIZE, /* 9875 */ IC_VEX_L_OPSIZE, /* 9876 */ IC_VEX_L_OPSIZE, /* 9877 */ IC_VEX_L_OPSIZE, /* 9878 */ IC_VEX_L_OPSIZE, /* 9879 */ IC_VEX_L_W_OPSIZE, /* 9880 */ IC_VEX_L_W_OPSIZE, /* 9881 */ IC_VEX_L_W_OPSIZE, /* 9882 */ IC_VEX_L_W_OPSIZE, /* 9883 */ IC_VEX_L_W_OPSIZE, /* 9884 */ IC_VEX_L_W_OPSIZE, /* 9885 */ IC_VEX_L_W_OPSIZE, /* 9886 */ IC_VEX_L_W_OPSIZE, /* 9887 */ IC_VEX_L, /* 9888 */ IC_VEX_L, /* 9889 */ IC_VEX_L_XS, /* 9890 */ IC_VEX_L_XS, /* 9891 */ IC_VEX_L_XD, /* 9892 */ IC_VEX_L_XD, /* 9893 */ IC_VEX_L_XD, /* 9894 */ IC_VEX_L_XD, /* 9895 */ IC_VEX_L_W, /* 9896 */ IC_VEX_L_W, /* 9897 */ IC_VEX_L_W_XS, /* 9898 */ IC_VEX_L_W_XS, /* 9899 */ IC_VEX_L_W_XD, /* 9900 */ IC_VEX_L_W_XD, /* 9901 */ IC_VEX_L_W_XD, /* 9902 */ IC_VEX_L_W_XD, /* 9903 */ IC_VEX_L_OPSIZE, /* 9904 */ IC_VEX_L_OPSIZE, /* 9905 */ IC_VEX_L_OPSIZE, /* 9906 */ IC_VEX_L_OPSIZE, /* 9907 */ IC_VEX_L_OPSIZE, /* 9908 */ IC_VEX_L_OPSIZE, /* 9909 */ IC_VEX_L_OPSIZE, /* 9910 */ IC_VEX_L_OPSIZE, /* 9911 */ IC_VEX_L_W_OPSIZE, /* 9912 */ IC_VEX_L_W_OPSIZE, /* 9913 */ IC_VEX_L_W_OPSIZE, /* 9914 */ IC_VEX_L_W_OPSIZE, /* 9915 */ IC_VEX_L_W_OPSIZE, /* 9916 */ IC_VEX_L_W_OPSIZE, /* 9917 */ IC_VEX_L_W_OPSIZE, /* 9918 */ IC_VEX_L_W_OPSIZE, /* 9919 */ IC_VEX_L, /* 9920 */ IC_VEX_L, /* 9921 */ IC_VEX_L_XS, /* 9922 */ IC_VEX_L_XS, /* 9923 */ IC_VEX_L_XD, /* 9924 */ IC_VEX_L_XD, /* 9925 */ IC_VEX_L_XD, /* 9926 */ IC_VEX_L_XD, /* 9927 */ IC_VEX_L_W, /* 9928 */ IC_VEX_L_W, /* 9929 */ IC_VEX_L_W_XS, /* 9930 */ IC_VEX_L_W_XS, /* 9931 */ IC_VEX_L_W_XD, /* 9932 */ IC_VEX_L_W_XD, /* 9933 */ IC_VEX_L_W_XD, /* 9934 */ IC_VEX_L_W_XD, /* 9935 */ IC_VEX_L_OPSIZE, /* 9936 */ IC_VEX_L_OPSIZE, /* 9937 */ IC_VEX_L_OPSIZE, /* 9938 */ IC_VEX_L_OPSIZE, /* 9939 */ IC_VEX_L_OPSIZE, /* 9940 */ IC_VEX_L_OPSIZE, /* 9941 */ IC_VEX_L_OPSIZE, /* 9942 */ IC_VEX_L_OPSIZE, /* 9943 */ IC_VEX_L_W_OPSIZE, /* 9944 */ IC_VEX_L_W_OPSIZE, /* 9945 */ IC_VEX_L_W_OPSIZE, /* 9946 */ IC_VEX_L_W_OPSIZE, /* 9947 */ IC_VEX_L_W_OPSIZE, /* 9948 */ IC_VEX_L_W_OPSIZE, /* 9949 */ IC_VEX_L_W_OPSIZE, /* 9950 */ IC_VEX_L_W_OPSIZE, /* 9951 */ IC_VEX_L, /* 9952 */ IC_VEX_L, /* 9953 */ IC_VEX_L_XS, /* 9954 */ IC_VEX_L_XS, /* 9955 */ IC_VEX_L_XD, /* 9956 */ IC_VEX_L_XD, /* 9957 */ IC_VEX_L_XD, /* 9958 */ IC_VEX_L_XD, /* 9959 */ IC_VEX_L_W, /* 9960 */ IC_VEX_L_W, /* 9961 */ IC_VEX_L_W_XS, /* 9962 */ IC_VEX_L_W_XS, /* 9963 */ IC_VEX_L_W_XD, /* 9964 */ IC_VEX_L_W_XD, /* 9965 */ IC_VEX_L_W_XD, /* 9966 */ IC_VEX_L_W_XD, /* 9967 */ IC_VEX_L_OPSIZE, /* 9968 */ IC_VEX_L_OPSIZE, /* 9969 */ IC_VEX_L_OPSIZE, /* 9970 */ IC_VEX_L_OPSIZE, /* 9971 */ IC_VEX_L_OPSIZE, /* 9972 */ IC_VEX_L_OPSIZE, /* 9973 */ IC_VEX_L_OPSIZE, /* 9974 */ IC_VEX_L_OPSIZE, /* 9975 */ IC_VEX_L_W_OPSIZE, /* 9976 */ IC_VEX_L_W_OPSIZE, /* 9977 */ IC_VEX_L_W_OPSIZE, /* 9978 */ IC_VEX_L_W_OPSIZE, /* 9979 */ IC_VEX_L_W_OPSIZE, /* 9980 */ IC_VEX_L_W_OPSIZE, /* 9981 */ IC_VEX_L_W_OPSIZE, /* 9982 */ IC_VEX_L_W_OPSIZE, /* 9983 */ IC_EVEX_L2_B, /* 9984 */ IC_EVEX_L2_B, /* 9985 */ IC_EVEX_L2_XS_B, /* 9986 */ IC_EVEX_L2_XS_B, /* 9987 */ IC_EVEX_L2_XD_B, /* 9988 */ IC_EVEX_L2_XD_B, /* 9989 */ IC_EVEX_L2_XD_B, /* 9990 */ IC_EVEX_L2_XD_B, /* 9991 */ IC_EVEX_L2_W_B, /* 9992 */ IC_EVEX_L2_W_B, /* 9993 */ IC_EVEX_L2_W_XS_B, /* 9994 */ IC_EVEX_L2_W_XS_B, /* 9995 */ IC_EVEX_L2_W_XD_B, /* 9996 */ IC_EVEX_L2_W_XD_B, /* 9997 */ IC_EVEX_L2_W_XD_B, /* 9998 */ IC_EVEX_L2_W_XD_B, /* 9999 */ IC_EVEX_L2_OPSIZE_B, /* 10000 */ IC_EVEX_L2_OPSIZE_B, /* 10001 */ IC_EVEX_L2_OPSIZE_B, /* 10002 */ IC_EVEX_L2_OPSIZE_B, /* 10003 */ IC_EVEX_L2_OPSIZE_B, /* 10004 */ IC_EVEX_L2_OPSIZE_B, /* 10005 */ IC_EVEX_L2_OPSIZE_B, /* 10006 */ IC_EVEX_L2_OPSIZE_B, /* 10007 */ IC_EVEX_L2_W_OPSIZE_B, /* 10008 */ IC_EVEX_L2_W_OPSIZE_B, /* 10009 */ IC_EVEX_L2_W_OPSIZE_B, /* 10010 */ IC_EVEX_L2_W_OPSIZE_B, /* 10011 */ IC_EVEX_L2_W_OPSIZE_B, /* 10012 */ IC_EVEX_L2_W_OPSIZE_B, /* 10013 */ IC_EVEX_L2_W_OPSIZE_B, /* 10014 */ IC_EVEX_L2_W_OPSIZE_B, /* 10015 */ IC_EVEX_L2_B, /* 10016 */ IC_EVEX_L2_B, /* 10017 */ IC_EVEX_L2_XS_B, /* 10018 */ IC_EVEX_L2_XS_B, /* 10019 */ IC_EVEX_L2_XD_B, /* 10020 */ IC_EVEX_L2_XD_B, /* 10021 */ IC_EVEX_L2_XD_B, /* 10022 */ IC_EVEX_L2_XD_B, /* 10023 */ IC_EVEX_L2_W_B, /* 10024 */ IC_EVEX_L2_W_B, /* 10025 */ IC_EVEX_L2_W_XS_B, /* 10026 */ IC_EVEX_L2_W_XS_B, /* 10027 */ IC_EVEX_L2_W_XD_B, /* 10028 */ IC_EVEX_L2_W_XD_B, /* 10029 */ IC_EVEX_L2_W_XD_B, /* 10030 */ IC_EVEX_L2_W_XD_B, /* 10031 */ IC_EVEX_L2_OPSIZE_B, /* 10032 */ IC_EVEX_L2_OPSIZE_B, /* 10033 */ IC_EVEX_L2_OPSIZE_B, /* 10034 */ IC_EVEX_L2_OPSIZE_B, /* 10035 */ IC_EVEX_L2_OPSIZE_B, /* 10036 */ IC_EVEX_L2_OPSIZE_B, /* 10037 */ IC_EVEX_L2_OPSIZE_B, /* 10038 */ IC_EVEX_L2_OPSIZE_B, /* 10039 */ IC_EVEX_L2_W_OPSIZE_B, /* 10040 */ IC_EVEX_L2_W_OPSIZE_B, /* 10041 */ IC_EVEX_L2_W_OPSIZE_B, /* 10042 */ IC_EVEX_L2_W_OPSIZE_B, /* 10043 */ IC_EVEX_L2_W_OPSIZE_B, /* 10044 */ IC_EVEX_L2_W_OPSIZE_B, /* 10045 */ IC_EVEX_L2_W_OPSIZE_B, /* 10046 */ IC_EVEX_L2_W_OPSIZE_B, /* 10047 */ IC_EVEX_L2_B, /* 10048 */ IC_EVEX_L2_B, /* 10049 */ IC_EVEX_L2_XS_B, /* 10050 */ IC_EVEX_L2_XS_B, /* 10051 */ IC_EVEX_L2_XD_B, /* 10052 */ IC_EVEX_L2_XD_B, /* 10053 */ IC_EVEX_L2_XD_B, /* 10054 */ IC_EVEX_L2_XD_B, /* 10055 */ IC_EVEX_L2_W_B, /* 10056 */ IC_EVEX_L2_W_B, /* 10057 */ IC_EVEX_L2_W_XS_B, /* 10058 */ IC_EVEX_L2_W_XS_B, /* 10059 */ IC_EVEX_L2_W_XD_B, /* 10060 */ IC_EVEX_L2_W_XD_B, /* 10061 */ IC_EVEX_L2_W_XD_B, /* 10062 */ IC_EVEX_L2_W_XD_B, /* 10063 */ IC_EVEX_L2_OPSIZE_B, /* 10064 */ IC_EVEX_L2_OPSIZE_B, /* 10065 */ IC_EVEX_L2_OPSIZE_B, /* 10066 */ IC_EVEX_L2_OPSIZE_B, /* 10067 */ IC_EVEX_L2_OPSIZE_B, /* 10068 */ IC_EVEX_L2_OPSIZE_B, /* 10069 */ IC_EVEX_L2_OPSIZE_B, /* 10070 */ IC_EVEX_L2_OPSIZE_B, /* 10071 */ IC_EVEX_L2_W_OPSIZE_B, /* 10072 */ IC_EVEX_L2_W_OPSIZE_B, /* 10073 */ IC_EVEX_L2_W_OPSIZE_B, /* 10074 */ IC_EVEX_L2_W_OPSIZE_B, /* 10075 */ IC_EVEX_L2_W_OPSIZE_B, /* 10076 */ IC_EVEX_L2_W_OPSIZE_B, /* 10077 */ IC_EVEX_L2_W_OPSIZE_B, /* 10078 */ IC_EVEX_L2_W_OPSIZE_B, /* 10079 */ IC_EVEX_L2_B, /* 10080 */ IC_EVEX_L2_B, /* 10081 */ IC_EVEX_L2_XS_B, /* 10082 */ IC_EVEX_L2_XS_B, /* 10083 */ IC_EVEX_L2_XD_B, /* 10084 */ IC_EVEX_L2_XD_B, /* 10085 */ IC_EVEX_L2_XD_B, /* 10086 */ IC_EVEX_L2_XD_B, /* 10087 */ IC_EVEX_L2_W_B, /* 10088 */ IC_EVEX_L2_W_B, /* 10089 */ IC_EVEX_L2_W_XS_B, /* 10090 */ IC_EVEX_L2_W_XS_B, /* 10091 */ IC_EVEX_L2_W_XD_B, /* 10092 */ IC_EVEX_L2_W_XD_B, /* 10093 */ IC_EVEX_L2_W_XD_B, /* 10094 */ IC_EVEX_L2_W_XD_B, /* 10095 */ IC_EVEX_L2_OPSIZE_B, /* 10096 */ IC_EVEX_L2_OPSIZE_B, /* 10097 */ IC_EVEX_L2_OPSIZE_B, /* 10098 */ IC_EVEX_L2_OPSIZE_B, /* 10099 */ IC_EVEX_L2_OPSIZE_B, /* 10100 */ IC_EVEX_L2_OPSIZE_B, /* 10101 */ IC_EVEX_L2_OPSIZE_B, /* 10102 */ IC_EVEX_L2_OPSIZE_B, /* 10103 */ IC_EVEX_L2_W_OPSIZE_B, /* 10104 */ IC_EVEX_L2_W_OPSIZE_B, /* 10105 */ IC_EVEX_L2_W_OPSIZE_B, /* 10106 */ IC_EVEX_L2_W_OPSIZE_B, /* 10107 */ IC_EVEX_L2_W_OPSIZE_B, /* 10108 */ IC_EVEX_L2_W_OPSIZE_B, /* 10109 */ IC_EVEX_L2_W_OPSIZE_B, /* 10110 */ IC_EVEX_L2_W_OPSIZE_B, /* 10111 */ IC_EVEX_L2_B, /* 10112 */ IC_EVEX_L2_B, /* 10113 */ IC_EVEX_L2_XS_B, /* 10114 */ IC_EVEX_L2_XS_B, /* 10115 */ IC_EVEX_L2_XD_B, /* 10116 */ IC_EVEX_L2_XD_B, /* 10117 */ IC_EVEX_L2_XD_B, /* 10118 */ IC_EVEX_L2_XD_B, /* 10119 */ IC_EVEX_L2_W_B, /* 10120 */ IC_EVEX_L2_W_B, /* 10121 */ IC_EVEX_L2_W_XS_B, /* 10122 */ IC_EVEX_L2_W_XS_B, /* 10123 */ IC_EVEX_L2_W_XD_B, /* 10124 */ IC_EVEX_L2_W_XD_B, /* 10125 */ IC_EVEX_L2_W_XD_B, /* 10126 */ IC_EVEX_L2_W_XD_B, /* 10127 */ IC_EVEX_L2_OPSIZE_B, /* 10128 */ IC_EVEX_L2_OPSIZE_B, /* 10129 */ IC_EVEX_L2_OPSIZE_B, /* 10130 */ IC_EVEX_L2_OPSIZE_B, /* 10131 */ IC_EVEX_L2_OPSIZE_B, /* 10132 */ IC_EVEX_L2_OPSIZE_B, /* 10133 */ IC_EVEX_L2_OPSIZE_B, /* 10134 */ IC_EVEX_L2_OPSIZE_B, /* 10135 */ IC_EVEX_L2_W_OPSIZE_B, /* 10136 */ IC_EVEX_L2_W_OPSIZE_B, /* 10137 */ IC_EVEX_L2_W_OPSIZE_B, /* 10138 */ IC_EVEX_L2_W_OPSIZE_B, /* 10139 */ IC_EVEX_L2_W_OPSIZE_B, /* 10140 */ IC_EVEX_L2_W_OPSIZE_B, /* 10141 */ IC_EVEX_L2_W_OPSIZE_B, /* 10142 */ IC_EVEX_L2_W_OPSIZE_B, /* 10143 */ IC_EVEX_L2_B, /* 10144 */ IC_EVEX_L2_B, /* 10145 */ IC_EVEX_L2_XS_B, /* 10146 */ IC_EVEX_L2_XS_B, /* 10147 */ IC_EVEX_L2_XD_B, /* 10148 */ IC_EVEX_L2_XD_B, /* 10149 */ IC_EVEX_L2_XD_B, /* 10150 */ IC_EVEX_L2_XD_B, /* 10151 */ IC_EVEX_L2_W_B, /* 10152 */ IC_EVEX_L2_W_B, /* 10153 */ IC_EVEX_L2_W_XS_B, /* 10154 */ IC_EVEX_L2_W_XS_B, /* 10155 */ IC_EVEX_L2_W_XD_B, /* 10156 */ IC_EVEX_L2_W_XD_B, /* 10157 */ IC_EVEX_L2_W_XD_B, /* 10158 */ IC_EVEX_L2_W_XD_B, /* 10159 */ IC_EVEX_L2_OPSIZE_B, /* 10160 */ IC_EVEX_L2_OPSIZE_B, /* 10161 */ IC_EVEX_L2_OPSIZE_B, /* 10162 */ IC_EVEX_L2_OPSIZE_B, /* 10163 */ IC_EVEX_L2_OPSIZE_B, /* 10164 */ IC_EVEX_L2_OPSIZE_B, /* 10165 */ IC_EVEX_L2_OPSIZE_B, /* 10166 */ IC_EVEX_L2_OPSIZE_B, /* 10167 */ IC_EVEX_L2_W_OPSIZE_B, /* 10168 */ IC_EVEX_L2_W_OPSIZE_B, /* 10169 */ IC_EVEX_L2_W_OPSIZE_B, /* 10170 */ IC_EVEX_L2_W_OPSIZE_B, /* 10171 */ IC_EVEX_L2_W_OPSIZE_B, /* 10172 */ IC_EVEX_L2_W_OPSIZE_B, /* 10173 */ IC_EVEX_L2_W_OPSIZE_B, /* 10174 */ IC_EVEX_L2_W_OPSIZE_B, /* 10175 */ IC_EVEX_L2_B, /* 10176 */ IC_EVEX_L2_B, /* 10177 */ IC_EVEX_L2_XS_B, /* 10178 */ IC_EVEX_L2_XS_B, /* 10179 */ IC_EVEX_L2_XD_B, /* 10180 */ IC_EVEX_L2_XD_B, /* 10181 */ IC_EVEX_L2_XD_B, /* 10182 */ IC_EVEX_L2_XD_B, /* 10183 */ IC_EVEX_L2_W_B, /* 10184 */ IC_EVEX_L2_W_B, /* 10185 */ IC_EVEX_L2_W_XS_B, /* 10186 */ IC_EVEX_L2_W_XS_B, /* 10187 */ IC_EVEX_L2_W_XD_B, /* 10188 */ IC_EVEX_L2_W_XD_B, /* 10189 */ IC_EVEX_L2_W_XD_B, /* 10190 */ IC_EVEX_L2_W_XD_B, /* 10191 */ IC_EVEX_L2_OPSIZE_B, /* 10192 */ IC_EVEX_L2_OPSIZE_B, /* 10193 */ IC_EVEX_L2_OPSIZE_B, /* 10194 */ IC_EVEX_L2_OPSIZE_B, /* 10195 */ IC_EVEX_L2_OPSIZE_B, /* 10196 */ IC_EVEX_L2_OPSIZE_B, /* 10197 */ IC_EVEX_L2_OPSIZE_B, /* 10198 */ IC_EVEX_L2_OPSIZE_B, /* 10199 */ IC_EVEX_L2_W_OPSIZE_B, /* 10200 */ IC_EVEX_L2_W_OPSIZE_B, /* 10201 */ IC_EVEX_L2_W_OPSIZE_B, /* 10202 */ IC_EVEX_L2_W_OPSIZE_B, /* 10203 */ IC_EVEX_L2_W_OPSIZE_B, /* 10204 */ IC_EVEX_L2_W_OPSIZE_B, /* 10205 */ IC_EVEX_L2_W_OPSIZE_B, /* 10206 */ IC_EVEX_L2_W_OPSIZE_B, /* 10207 */ IC_EVEX_L2_B, /* 10208 */ IC_EVEX_L2_B, /* 10209 */ IC_EVEX_L2_XS_B, /* 10210 */ IC_EVEX_L2_XS_B, /* 10211 */ IC_EVEX_L2_XD_B, /* 10212 */ IC_EVEX_L2_XD_B, /* 10213 */ IC_EVEX_L2_XD_B, /* 10214 */ IC_EVEX_L2_XD_B, /* 10215 */ IC_EVEX_L2_W_B, /* 10216 */ IC_EVEX_L2_W_B, /* 10217 */ IC_EVEX_L2_W_XS_B, /* 10218 */ IC_EVEX_L2_W_XS_B, /* 10219 */ IC_EVEX_L2_W_XD_B, /* 10220 */ IC_EVEX_L2_W_XD_B, /* 10221 */ IC_EVEX_L2_W_XD_B, /* 10222 */ IC_EVEX_L2_W_XD_B, /* 10223 */ IC_EVEX_L2_OPSIZE_B, /* 10224 */ IC_EVEX_L2_OPSIZE_B, /* 10225 */ IC_EVEX_L2_OPSIZE_B, /* 10226 */ IC_EVEX_L2_OPSIZE_B, /* 10227 */ IC_EVEX_L2_OPSIZE_B, /* 10228 */ IC_EVEX_L2_OPSIZE_B, /* 10229 */ IC_EVEX_L2_OPSIZE_B, /* 10230 */ IC_EVEX_L2_OPSIZE_B, /* 10231 */ IC_EVEX_L2_W_OPSIZE_B, /* 10232 */ IC_EVEX_L2_W_OPSIZE_B, /* 10233 */ IC_EVEX_L2_W_OPSIZE_B, /* 10234 */ IC_EVEX_L2_W_OPSIZE_B, /* 10235 */ IC_EVEX_L2_W_OPSIZE_B, /* 10236 */ IC_EVEX_L2_W_OPSIZE_B, /* 10237 */ IC_EVEX_L2_W_OPSIZE_B, /* 10238 */ IC_EVEX_L2_W_OPSIZE_B, /* 10239 */ IC, /* 10240 */ IC_64BIT, /* 10241 */ IC_XS, /* 10242 */ IC_64BIT_XS, /* 10243 */ IC_XD, /* 10244 */ IC_64BIT_XD, /* 10245 */ IC_XS, /* 10246 */ IC_64BIT_XS, /* 10247 */ IC, /* 10248 */ IC_64BIT_REXW, /* 10249 */ IC_XS, /* 10250 */ IC_64BIT_REXW_XS, /* 10251 */ IC_XD, /* 10252 */ IC_64BIT_REXW_XD, /* 10253 */ IC_XS, /* 10254 */ IC_64BIT_REXW_XS, /* 10255 */ IC_OPSIZE, /* 10256 */ IC_64BIT_OPSIZE, /* 10257 */ IC_XS_OPSIZE, /* 10258 */ IC_64BIT_XS_OPSIZE, /* 10259 */ IC_XD_OPSIZE, /* 10260 */ IC_64BIT_XD_OPSIZE, /* 10261 */ IC_XS_OPSIZE, /* 10262 */ IC_64BIT_XD_OPSIZE, /* 10263 */ IC_OPSIZE, /* 10264 */ IC_64BIT_REXW_OPSIZE, /* 10265 */ IC_XS_OPSIZE, /* 10266 */ IC_64BIT_REXW_XS, /* 10267 */ IC_XD_OPSIZE, /* 10268 */ IC_64BIT_REXW_XD, /* 10269 */ IC_XS_OPSIZE, /* 10270 */ IC_64BIT_REXW_XS, /* 10271 */ IC_ADSIZE, /* 10272 */ IC_64BIT_ADSIZE, /* 10273 */ IC_XS_ADSIZE, /* 10274 */ IC_64BIT_XS_ADSIZE, /* 10275 */ IC_XD_ADSIZE, /* 10276 */ IC_64BIT_XD_ADSIZE, /* 10277 */ IC_XS_ADSIZE, /* 10278 */ IC_64BIT_XD_ADSIZE, /* 10279 */ IC_ADSIZE, /* 10280 */ IC_64BIT_REXW_ADSIZE, /* 10281 */ IC_XS_ADSIZE, /* 10282 */ IC_64BIT_REXW_XS, /* 10283 */ IC_XD_ADSIZE, /* 10284 */ IC_64BIT_REXW_XD, /* 10285 */ IC_XS_ADSIZE, /* 10286 */ IC_64BIT_REXW_XS, /* 10287 */ IC_OPSIZE_ADSIZE, /* 10288 */ IC_64BIT_OPSIZE_ADSIZE, /* 10289 */ IC_XS_OPSIZE, /* 10290 */ IC_64BIT_XS_OPSIZE, /* 10291 */ IC_XD_OPSIZE, /* 10292 */ IC_64BIT_XD_OPSIZE, /* 10293 */ IC_XS_OPSIZE, /* 10294 */ IC_64BIT_XD_OPSIZE, /* 10295 */ IC_OPSIZE_ADSIZE, /* 10296 */ IC_64BIT_REXW_OPSIZE, /* 10297 */ IC_XS_OPSIZE, /* 10298 */ IC_64BIT_REXW_XS, /* 10299 */ IC_XD_OPSIZE, /* 10300 */ IC_64BIT_REXW_XD, /* 10301 */ IC_XS_OPSIZE, /* 10302 */ IC_64BIT_REXW_XS, /* 10303 */ IC_VEX, /* 10304 */ IC_VEX, /* 10305 */ IC_VEX_XS, /* 10306 */ IC_VEX_XS, /* 10307 */ IC_VEX_XD, /* 10308 */ IC_VEX_XD, /* 10309 */ IC_VEX_XD, /* 10310 */ IC_VEX_XD, /* 10311 */ IC_VEX_W, /* 10312 */ IC_VEX_W, /* 10313 */ IC_VEX_W_XS, /* 10314 */ IC_VEX_W_XS, /* 10315 */ IC_VEX_W_XD, /* 10316 */ IC_VEX_W_XD, /* 10317 */ IC_VEX_W_XD, /* 10318 */ IC_VEX_W_XD, /* 10319 */ IC_VEX_OPSIZE, /* 10320 */ IC_VEX_OPSIZE, /* 10321 */ IC_VEX_OPSIZE, /* 10322 */ IC_VEX_OPSIZE, /* 10323 */ IC_VEX_OPSIZE, /* 10324 */ IC_VEX_OPSIZE, /* 10325 */ IC_VEX_OPSIZE, /* 10326 */ IC_VEX_OPSIZE, /* 10327 */ IC_VEX_W_OPSIZE, /* 10328 */ IC_VEX_W_OPSIZE, /* 10329 */ IC_VEX_W_OPSIZE, /* 10330 */ IC_VEX_W_OPSIZE, /* 10331 */ IC_VEX_W_OPSIZE, /* 10332 */ IC_VEX_W_OPSIZE, /* 10333 */ IC_VEX_W_OPSIZE, /* 10334 */ IC_VEX_W_OPSIZE, /* 10335 */ IC_VEX, /* 10336 */ IC_VEX, /* 10337 */ IC_VEX_XS, /* 10338 */ IC_VEX_XS, /* 10339 */ IC_VEX_XD, /* 10340 */ IC_VEX_XD, /* 10341 */ IC_VEX_XD, /* 10342 */ IC_VEX_XD, /* 10343 */ IC_VEX_W, /* 10344 */ IC_VEX_W, /* 10345 */ IC_VEX_W_XS, /* 10346 */ IC_VEX_W_XS, /* 10347 */ IC_VEX_W_XD, /* 10348 */ IC_VEX_W_XD, /* 10349 */ IC_VEX_W_XD, /* 10350 */ IC_VEX_W_XD, /* 10351 */ IC_VEX_OPSIZE, /* 10352 */ IC_VEX_OPSIZE, /* 10353 */ IC_VEX_OPSIZE, /* 10354 */ IC_VEX_OPSIZE, /* 10355 */ IC_VEX_OPSIZE, /* 10356 */ IC_VEX_OPSIZE, /* 10357 */ IC_VEX_OPSIZE, /* 10358 */ IC_VEX_OPSIZE, /* 10359 */ IC_VEX_W_OPSIZE, /* 10360 */ IC_VEX_W_OPSIZE, /* 10361 */ IC_VEX_W_OPSIZE, /* 10362 */ IC_VEX_W_OPSIZE, /* 10363 */ IC_VEX_W_OPSIZE, /* 10364 */ IC_VEX_W_OPSIZE, /* 10365 */ IC_VEX_W_OPSIZE, /* 10366 */ IC_VEX_W_OPSIZE, /* 10367 */ IC_VEX_L, /* 10368 */ IC_VEX_L, /* 10369 */ IC_VEX_L_XS, /* 10370 */ IC_VEX_L_XS, /* 10371 */ IC_VEX_L_XD, /* 10372 */ IC_VEX_L_XD, /* 10373 */ IC_VEX_L_XD, /* 10374 */ IC_VEX_L_XD, /* 10375 */ IC_VEX_L_W, /* 10376 */ IC_VEX_L_W, /* 10377 */ IC_VEX_L_W_XS, /* 10378 */ IC_VEX_L_W_XS, /* 10379 */ IC_VEX_L_W_XD, /* 10380 */ IC_VEX_L_W_XD, /* 10381 */ IC_VEX_L_W_XD, /* 10382 */ IC_VEX_L_W_XD, /* 10383 */ IC_VEX_L_OPSIZE, /* 10384 */ IC_VEX_L_OPSIZE, /* 10385 */ IC_VEX_L_OPSIZE, /* 10386 */ IC_VEX_L_OPSIZE, /* 10387 */ IC_VEX_L_OPSIZE, /* 10388 */ IC_VEX_L_OPSIZE, /* 10389 */ IC_VEX_L_OPSIZE, /* 10390 */ IC_VEX_L_OPSIZE, /* 10391 */ IC_VEX_L_W_OPSIZE, /* 10392 */ IC_VEX_L_W_OPSIZE, /* 10393 */ IC_VEX_L_W_OPSIZE, /* 10394 */ IC_VEX_L_W_OPSIZE, /* 10395 */ IC_VEX_L_W_OPSIZE, /* 10396 */ IC_VEX_L_W_OPSIZE, /* 10397 */ IC_VEX_L_W_OPSIZE, /* 10398 */ IC_VEX_L_W_OPSIZE, /* 10399 */ IC_VEX_L, /* 10400 */ IC_VEX_L, /* 10401 */ IC_VEX_L_XS, /* 10402 */ IC_VEX_L_XS, /* 10403 */ IC_VEX_L_XD, /* 10404 */ IC_VEX_L_XD, /* 10405 */ IC_VEX_L_XD, /* 10406 */ IC_VEX_L_XD, /* 10407 */ IC_VEX_L_W, /* 10408 */ IC_VEX_L_W, /* 10409 */ IC_VEX_L_W_XS, /* 10410 */ IC_VEX_L_W_XS, /* 10411 */ IC_VEX_L_W_XD, /* 10412 */ IC_VEX_L_W_XD, /* 10413 */ IC_VEX_L_W_XD, /* 10414 */ IC_VEX_L_W_XD, /* 10415 */ IC_VEX_L_OPSIZE, /* 10416 */ IC_VEX_L_OPSIZE, /* 10417 */ IC_VEX_L_OPSIZE, /* 10418 */ IC_VEX_L_OPSIZE, /* 10419 */ IC_VEX_L_OPSIZE, /* 10420 */ IC_VEX_L_OPSIZE, /* 10421 */ IC_VEX_L_OPSIZE, /* 10422 */ IC_VEX_L_OPSIZE, /* 10423 */ IC_VEX_L_W_OPSIZE, /* 10424 */ IC_VEX_L_W_OPSIZE, /* 10425 */ IC_VEX_L_W_OPSIZE, /* 10426 */ IC_VEX_L_W_OPSIZE, /* 10427 */ IC_VEX_L_W_OPSIZE, /* 10428 */ IC_VEX_L_W_OPSIZE, /* 10429 */ IC_VEX_L_W_OPSIZE, /* 10430 */ IC_VEX_L_W_OPSIZE, /* 10431 */ IC_VEX_L, /* 10432 */ IC_VEX_L, /* 10433 */ IC_VEX_L_XS, /* 10434 */ IC_VEX_L_XS, /* 10435 */ IC_VEX_L_XD, /* 10436 */ IC_VEX_L_XD, /* 10437 */ IC_VEX_L_XD, /* 10438 */ IC_VEX_L_XD, /* 10439 */ IC_VEX_L_W, /* 10440 */ IC_VEX_L_W, /* 10441 */ IC_VEX_L_W_XS, /* 10442 */ IC_VEX_L_W_XS, /* 10443 */ IC_VEX_L_W_XD, /* 10444 */ IC_VEX_L_W_XD, /* 10445 */ IC_VEX_L_W_XD, /* 10446 */ IC_VEX_L_W_XD, /* 10447 */ IC_VEX_L_OPSIZE, /* 10448 */ IC_VEX_L_OPSIZE, /* 10449 */ IC_VEX_L_OPSIZE, /* 10450 */ IC_VEX_L_OPSIZE, /* 10451 */ IC_VEX_L_OPSIZE, /* 10452 */ IC_VEX_L_OPSIZE, /* 10453 */ IC_VEX_L_OPSIZE, /* 10454 */ IC_VEX_L_OPSIZE, /* 10455 */ IC_VEX_L_W_OPSIZE, /* 10456 */ IC_VEX_L_W_OPSIZE, /* 10457 */ IC_VEX_L_W_OPSIZE, /* 10458 */ IC_VEX_L_W_OPSIZE, /* 10459 */ IC_VEX_L_W_OPSIZE, /* 10460 */ IC_VEX_L_W_OPSIZE, /* 10461 */ IC_VEX_L_W_OPSIZE, /* 10462 */ IC_VEX_L_W_OPSIZE, /* 10463 */ IC_VEX_L, /* 10464 */ IC_VEX_L, /* 10465 */ IC_VEX_L_XS, /* 10466 */ IC_VEX_L_XS, /* 10467 */ IC_VEX_L_XD, /* 10468 */ IC_VEX_L_XD, /* 10469 */ IC_VEX_L_XD, /* 10470 */ IC_VEX_L_XD, /* 10471 */ IC_VEX_L_W, /* 10472 */ IC_VEX_L_W, /* 10473 */ IC_VEX_L_W_XS, /* 10474 */ IC_VEX_L_W_XS, /* 10475 */ IC_VEX_L_W_XD, /* 10476 */ IC_VEX_L_W_XD, /* 10477 */ IC_VEX_L_W_XD, /* 10478 */ IC_VEX_L_W_XD, /* 10479 */ IC_VEX_L_OPSIZE, /* 10480 */ IC_VEX_L_OPSIZE, /* 10481 */ IC_VEX_L_OPSIZE, /* 10482 */ IC_VEX_L_OPSIZE, /* 10483 */ IC_VEX_L_OPSIZE, /* 10484 */ IC_VEX_L_OPSIZE, /* 10485 */ IC_VEX_L_OPSIZE, /* 10486 */ IC_VEX_L_OPSIZE, /* 10487 */ IC_VEX_L_W_OPSIZE, /* 10488 */ IC_VEX_L_W_OPSIZE, /* 10489 */ IC_VEX_L_W_OPSIZE, /* 10490 */ IC_VEX_L_W_OPSIZE, /* 10491 */ IC_VEX_L_W_OPSIZE, /* 10492 */ IC_VEX_L_W_OPSIZE, /* 10493 */ IC_VEX_L_W_OPSIZE, /* 10494 */ IC_VEX_L_W_OPSIZE, /* 10495 */ IC_EVEX_K_B, /* 10496 */ IC_EVEX_K_B, /* 10497 */ IC_EVEX_XS_K_B, /* 10498 */ IC_EVEX_XS_K_B, /* 10499 */ IC_EVEX_XD_K_B, /* 10500 */ IC_EVEX_XD_K_B, /* 10501 */ IC_EVEX_XD_K_B, /* 10502 */ IC_EVEX_XD_K_B, /* 10503 */ IC_EVEX_W_K_B, /* 10504 */ IC_EVEX_W_K_B, /* 10505 */ IC_EVEX_W_XS_K_B, /* 10506 */ IC_EVEX_W_XS_K_B, /* 10507 */ IC_EVEX_W_XD_K_B, /* 10508 */ IC_EVEX_W_XD_K_B, /* 10509 */ IC_EVEX_W_XD_K_B, /* 10510 */ IC_EVEX_W_XD_K_B, /* 10511 */ IC_EVEX_OPSIZE_K_B, /* 10512 */ IC_EVEX_OPSIZE_K_B, /* 10513 */ IC_EVEX_OPSIZE_K_B, /* 10514 */ IC_EVEX_OPSIZE_K_B, /* 10515 */ IC_EVEX_OPSIZE_K_B, /* 10516 */ IC_EVEX_OPSIZE_K_B, /* 10517 */ IC_EVEX_OPSIZE_K_B, /* 10518 */ IC_EVEX_OPSIZE_K_B, /* 10519 */ IC_EVEX_W_OPSIZE_K_B, /* 10520 */ IC_EVEX_W_OPSIZE_K_B, /* 10521 */ IC_EVEX_W_OPSIZE_K_B, /* 10522 */ IC_EVEX_W_OPSIZE_K_B, /* 10523 */ IC_EVEX_W_OPSIZE_K_B, /* 10524 */ IC_EVEX_W_OPSIZE_K_B, /* 10525 */ IC_EVEX_W_OPSIZE_K_B, /* 10526 */ IC_EVEX_W_OPSIZE_K_B, /* 10527 */ IC_EVEX_K_B, /* 10528 */ IC_EVEX_K_B, /* 10529 */ IC_EVEX_XS_K_B, /* 10530 */ IC_EVEX_XS_K_B, /* 10531 */ IC_EVEX_XD_K_B, /* 10532 */ IC_EVEX_XD_K_B, /* 10533 */ IC_EVEX_XD_K_B, /* 10534 */ IC_EVEX_XD_K_B, /* 10535 */ IC_EVEX_W_K_B, /* 10536 */ IC_EVEX_W_K_B, /* 10537 */ IC_EVEX_W_XS_K_B, /* 10538 */ IC_EVEX_W_XS_K_B, /* 10539 */ IC_EVEX_W_XD_K_B, /* 10540 */ IC_EVEX_W_XD_K_B, /* 10541 */ IC_EVEX_W_XD_K_B, /* 10542 */ IC_EVEX_W_XD_K_B, /* 10543 */ IC_EVEX_OPSIZE_K_B, /* 10544 */ IC_EVEX_OPSIZE_K_B, /* 10545 */ IC_EVEX_OPSIZE_K_B, /* 10546 */ IC_EVEX_OPSIZE_K_B, /* 10547 */ IC_EVEX_OPSIZE_K_B, /* 10548 */ IC_EVEX_OPSIZE_K_B, /* 10549 */ IC_EVEX_OPSIZE_K_B, /* 10550 */ IC_EVEX_OPSIZE_K_B, /* 10551 */ IC_EVEX_W_OPSIZE_K_B, /* 10552 */ IC_EVEX_W_OPSIZE_K_B, /* 10553 */ IC_EVEX_W_OPSIZE_K_B, /* 10554 */ IC_EVEX_W_OPSIZE_K_B, /* 10555 */ IC_EVEX_W_OPSIZE_K_B, /* 10556 */ IC_EVEX_W_OPSIZE_K_B, /* 10557 */ IC_EVEX_W_OPSIZE_K_B, /* 10558 */ IC_EVEX_W_OPSIZE_K_B, /* 10559 */ IC_EVEX_K_B, /* 10560 */ IC_EVEX_K_B, /* 10561 */ IC_EVEX_XS_K_B, /* 10562 */ IC_EVEX_XS_K_B, /* 10563 */ IC_EVEX_XD_K_B, /* 10564 */ IC_EVEX_XD_K_B, /* 10565 */ IC_EVEX_XD_K_B, /* 10566 */ IC_EVEX_XD_K_B, /* 10567 */ IC_EVEX_W_K_B, /* 10568 */ IC_EVEX_W_K_B, /* 10569 */ IC_EVEX_W_XS_K_B, /* 10570 */ IC_EVEX_W_XS_K_B, /* 10571 */ IC_EVEX_W_XD_K_B, /* 10572 */ IC_EVEX_W_XD_K_B, /* 10573 */ IC_EVEX_W_XD_K_B, /* 10574 */ IC_EVEX_W_XD_K_B, /* 10575 */ IC_EVEX_OPSIZE_K_B, /* 10576 */ IC_EVEX_OPSIZE_K_B, /* 10577 */ IC_EVEX_OPSIZE_K_B, /* 10578 */ IC_EVEX_OPSIZE_K_B, /* 10579 */ IC_EVEX_OPSIZE_K_B, /* 10580 */ IC_EVEX_OPSIZE_K_B, /* 10581 */ IC_EVEX_OPSIZE_K_B, /* 10582 */ IC_EVEX_OPSIZE_K_B, /* 10583 */ IC_EVEX_W_OPSIZE_K_B, /* 10584 */ IC_EVEX_W_OPSIZE_K_B, /* 10585 */ IC_EVEX_W_OPSIZE_K_B, /* 10586 */ IC_EVEX_W_OPSIZE_K_B, /* 10587 */ IC_EVEX_W_OPSIZE_K_B, /* 10588 */ IC_EVEX_W_OPSIZE_K_B, /* 10589 */ IC_EVEX_W_OPSIZE_K_B, /* 10590 */ IC_EVEX_W_OPSIZE_K_B, /* 10591 */ IC_EVEX_K_B, /* 10592 */ IC_EVEX_K_B, /* 10593 */ IC_EVEX_XS_K_B, /* 10594 */ IC_EVEX_XS_K_B, /* 10595 */ IC_EVEX_XD_K_B, /* 10596 */ IC_EVEX_XD_K_B, /* 10597 */ IC_EVEX_XD_K_B, /* 10598 */ IC_EVEX_XD_K_B, /* 10599 */ IC_EVEX_W_K_B, /* 10600 */ IC_EVEX_W_K_B, /* 10601 */ IC_EVEX_W_XS_K_B, /* 10602 */ IC_EVEX_W_XS_K_B, /* 10603 */ IC_EVEX_W_XD_K_B, /* 10604 */ IC_EVEX_W_XD_K_B, /* 10605 */ IC_EVEX_W_XD_K_B, /* 10606 */ IC_EVEX_W_XD_K_B, /* 10607 */ IC_EVEX_OPSIZE_K_B, /* 10608 */ IC_EVEX_OPSIZE_K_B, /* 10609 */ IC_EVEX_OPSIZE_K_B, /* 10610 */ IC_EVEX_OPSIZE_K_B, /* 10611 */ IC_EVEX_OPSIZE_K_B, /* 10612 */ IC_EVEX_OPSIZE_K_B, /* 10613 */ IC_EVEX_OPSIZE_K_B, /* 10614 */ IC_EVEX_OPSIZE_K_B, /* 10615 */ IC_EVEX_W_OPSIZE_K_B, /* 10616 */ IC_EVEX_W_OPSIZE_K_B, /* 10617 */ IC_EVEX_W_OPSIZE_K_B, /* 10618 */ IC_EVEX_W_OPSIZE_K_B, /* 10619 */ IC_EVEX_W_OPSIZE_K_B, /* 10620 */ IC_EVEX_W_OPSIZE_K_B, /* 10621 */ IC_EVEX_W_OPSIZE_K_B, /* 10622 */ IC_EVEX_W_OPSIZE_K_B, /* 10623 */ IC_EVEX_K_B, /* 10624 */ IC_EVEX_K_B, /* 10625 */ IC_EVEX_XS_K_B, /* 10626 */ IC_EVEX_XS_K_B, /* 10627 */ IC_EVEX_XD_K_B, /* 10628 */ IC_EVEX_XD_K_B, /* 10629 */ IC_EVEX_XD_K_B, /* 10630 */ IC_EVEX_XD_K_B, /* 10631 */ IC_EVEX_W_K_B, /* 10632 */ IC_EVEX_W_K_B, /* 10633 */ IC_EVEX_W_XS_K_B, /* 10634 */ IC_EVEX_W_XS_K_B, /* 10635 */ IC_EVEX_W_XD_K_B, /* 10636 */ IC_EVEX_W_XD_K_B, /* 10637 */ IC_EVEX_W_XD_K_B, /* 10638 */ IC_EVEX_W_XD_K_B, /* 10639 */ IC_EVEX_OPSIZE_K_B, /* 10640 */ IC_EVEX_OPSIZE_K_B, /* 10641 */ IC_EVEX_OPSIZE_K_B, /* 10642 */ IC_EVEX_OPSIZE_K_B, /* 10643 */ IC_EVEX_OPSIZE_K_B, /* 10644 */ IC_EVEX_OPSIZE_K_B, /* 10645 */ IC_EVEX_OPSIZE_K_B, /* 10646 */ IC_EVEX_OPSIZE_K_B, /* 10647 */ IC_EVEX_W_OPSIZE_K_B, /* 10648 */ IC_EVEX_W_OPSIZE_K_B, /* 10649 */ IC_EVEX_W_OPSIZE_K_B, /* 10650 */ IC_EVEX_W_OPSIZE_K_B, /* 10651 */ IC_EVEX_W_OPSIZE_K_B, /* 10652 */ IC_EVEX_W_OPSIZE_K_B, /* 10653 */ IC_EVEX_W_OPSIZE_K_B, /* 10654 */ IC_EVEX_W_OPSIZE_K_B, /* 10655 */ IC_EVEX_K_B, /* 10656 */ IC_EVEX_K_B, /* 10657 */ IC_EVEX_XS_K_B, /* 10658 */ IC_EVEX_XS_K_B, /* 10659 */ IC_EVEX_XD_K_B, /* 10660 */ IC_EVEX_XD_K_B, /* 10661 */ IC_EVEX_XD_K_B, /* 10662 */ IC_EVEX_XD_K_B, /* 10663 */ IC_EVEX_W_K_B, /* 10664 */ IC_EVEX_W_K_B, /* 10665 */ IC_EVEX_W_XS_K_B, /* 10666 */ IC_EVEX_W_XS_K_B, /* 10667 */ IC_EVEX_W_XD_K_B, /* 10668 */ IC_EVEX_W_XD_K_B, /* 10669 */ IC_EVEX_W_XD_K_B, /* 10670 */ IC_EVEX_W_XD_K_B, /* 10671 */ IC_EVEX_OPSIZE_K_B, /* 10672 */ IC_EVEX_OPSIZE_K_B, /* 10673 */ IC_EVEX_OPSIZE_K_B, /* 10674 */ IC_EVEX_OPSIZE_K_B, /* 10675 */ IC_EVEX_OPSIZE_K_B, /* 10676 */ IC_EVEX_OPSIZE_K_B, /* 10677 */ IC_EVEX_OPSIZE_K_B, /* 10678 */ IC_EVEX_OPSIZE_K_B, /* 10679 */ IC_EVEX_W_OPSIZE_K_B, /* 10680 */ IC_EVEX_W_OPSIZE_K_B, /* 10681 */ IC_EVEX_W_OPSIZE_K_B, /* 10682 */ IC_EVEX_W_OPSIZE_K_B, /* 10683 */ IC_EVEX_W_OPSIZE_K_B, /* 10684 */ IC_EVEX_W_OPSIZE_K_B, /* 10685 */ IC_EVEX_W_OPSIZE_K_B, /* 10686 */ IC_EVEX_W_OPSIZE_K_B, /* 10687 */ IC_EVEX_K_B, /* 10688 */ IC_EVEX_K_B, /* 10689 */ IC_EVEX_XS_K_B, /* 10690 */ IC_EVEX_XS_K_B, /* 10691 */ IC_EVEX_XD_K_B, /* 10692 */ IC_EVEX_XD_K_B, /* 10693 */ IC_EVEX_XD_K_B, /* 10694 */ IC_EVEX_XD_K_B, /* 10695 */ IC_EVEX_W_K_B, /* 10696 */ IC_EVEX_W_K_B, /* 10697 */ IC_EVEX_W_XS_K_B, /* 10698 */ IC_EVEX_W_XS_K_B, /* 10699 */ IC_EVEX_W_XD_K_B, /* 10700 */ IC_EVEX_W_XD_K_B, /* 10701 */ IC_EVEX_W_XD_K_B, /* 10702 */ IC_EVEX_W_XD_K_B, /* 10703 */ IC_EVEX_OPSIZE_K_B, /* 10704 */ IC_EVEX_OPSIZE_K_B, /* 10705 */ IC_EVEX_OPSIZE_K_B, /* 10706 */ IC_EVEX_OPSIZE_K_B, /* 10707 */ IC_EVEX_OPSIZE_K_B, /* 10708 */ IC_EVEX_OPSIZE_K_B, /* 10709 */ IC_EVEX_OPSIZE_K_B, /* 10710 */ IC_EVEX_OPSIZE_K_B, /* 10711 */ IC_EVEX_W_OPSIZE_K_B, /* 10712 */ IC_EVEX_W_OPSIZE_K_B, /* 10713 */ IC_EVEX_W_OPSIZE_K_B, /* 10714 */ IC_EVEX_W_OPSIZE_K_B, /* 10715 */ IC_EVEX_W_OPSIZE_K_B, /* 10716 */ IC_EVEX_W_OPSIZE_K_B, /* 10717 */ IC_EVEX_W_OPSIZE_K_B, /* 10718 */ IC_EVEX_W_OPSIZE_K_B, /* 10719 */ IC_EVEX_K_B, /* 10720 */ IC_EVEX_K_B, /* 10721 */ IC_EVEX_XS_K_B, /* 10722 */ IC_EVEX_XS_K_B, /* 10723 */ IC_EVEX_XD_K_B, /* 10724 */ IC_EVEX_XD_K_B, /* 10725 */ IC_EVEX_XD_K_B, /* 10726 */ IC_EVEX_XD_K_B, /* 10727 */ IC_EVEX_W_K_B, /* 10728 */ IC_EVEX_W_K_B, /* 10729 */ IC_EVEX_W_XS_K_B, /* 10730 */ IC_EVEX_W_XS_K_B, /* 10731 */ IC_EVEX_W_XD_K_B, /* 10732 */ IC_EVEX_W_XD_K_B, /* 10733 */ IC_EVEX_W_XD_K_B, /* 10734 */ IC_EVEX_W_XD_K_B, /* 10735 */ IC_EVEX_OPSIZE_K_B, /* 10736 */ IC_EVEX_OPSIZE_K_B, /* 10737 */ IC_EVEX_OPSIZE_K_B, /* 10738 */ IC_EVEX_OPSIZE_K_B, /* 10739 */ IC_EVEX_OPSIZE_K_B, /* 10740 */ IC_EVEX_OPSIZE_K_B, /* 10741 */ IC_EVEX_OPSIZE_K_B, /* 10742 */ IC_EVEX_OPSIZE_K_B, /* 10743 */ IC_EVEX_W_OPSIZE_K_B, /* 10744 */ IC_EVEX_W_OPSIZE_K_B, /* 10745 */ IC_EVEX_W_OPSIZE_K_B, /* 10746 */ IC_EVEX_W_OPSIZE_K_B, /* 10747 */ IC_EVEX_W_OPSIZE_K_B, /* 10748 */ IC_EVEX_W_OPSIZE_K_B, /* 10749 */ IC_EVEX_W_OPSIZE_K_B, /* 10750 */ IC_EVEX_W_OPSIZE_K_B, /* 10751 */ IC, /* 10752 */ IC_64BIT, /* 10753 */ IC_XS, /* 10754 */ IC_64BIT_XS, /* 10755 */ IC_XD, /* 10756 */ IC_64BIT_XD, /* 10757 */ IC_XS, /* 10758 */ IC_64BIT_XS, /* 10759 */ IC, /* 10760 */ IC_64BIT_REXW, /* 10761 */ IC_XS, /* 10762 */ IC_64BIT_REXW_XS, /* 10763 */ IC_XD, /* 10764 */ IC_64BIT_REXW_XD, /* 10765 */ IC_XS, /* 10766 */ IC_64BIT_REXW_XS, /* 10767 */ IC_OPSIZE, /* 10768 */ IC_64BIT_OPSIZE, /* 10769 */ IC_XS_OPSIZE, /* 10770 */ IC_64BIT_XS_OPSIZE, /* 10771 */ IC_XD_OPSIZE, /* 10772 */ IC_64BIT_XD_OPSIZE, /* 10773 */ IC_XS_OPSIZE, /* 10774 */ IC_64BIT_XD_OPSIZE, /* 10775 */ IC_OPSIZE, /* 10776 */ IC_64BIT_REXW_OPSIZE, /* 10777 */ IC_XS_OPSIZE, /* 10778 */ IC_64BIT_REXW_XS, /* 10779 */ IC_XD_OPSIZE, /* 10780 */ IC_64BIT_REXW_XD, /* 10781 */ IC_XS_OPSIZE, /* 10782 */ IC_64BIT_REXW_XS, /* 10783 */ IC_ADSIZE, /* 10784 */ IC_64BIT_ADSIZE, /* 10785 */ IC_XS_ADSIZE, /* 10786 */ IC_64BIT_XS_ADSIZE, /* 10787 */ IC_XD_ADSIZE, /* 10788 */ IC_64BIT_XD_ADSIZE, /* 10789 */ IC_XS_ADSIZE, /* 10790 */ IC_64BIT_XD_ADSIZE, /* 10791 */ IC_ADSIZE, /* 10792 */ IC_64BIT_REXW_ADSIZE, /* 10793 */ IC_XS_ADSIZE, /* 10794 */ IC_64BIT_REXW_XS, /* 10795 */ IC_XD_ADSIZE, /* 10796 */ IC_64BIT_REXW_XD, /* 10797 */ IC_XS_ADSIZE, /* 10798 */ IC_64BIT_REXW_XS, /* 10799 */ IC_OPSIZE_ADSIZE, /* 10800 */ IC_64BIT_OPSIZE_ADSIZE, /* 10801 */ IC_XS_OPSIZE, /* 10802 */ IC_64BIT_XS_OPSIZE, /* 10803 */ IC_XD_OPSIZE, /* 10804 */ IC_64BIT_XD_OPSIZE, /* 10805 */ IC_XS_OPSIZE, /* 10806 */ IC_64BIT_XD_OPSIZE, /* 10807 */ IC_OPSIZE_ADSIZE, /* 10808 */ IC_64BIT_REXW_OPSIZE, /* 10809 */ IC_XS_OPSIZE, /* 10810 */ IC_64BIT_REXW_XS, /* 10811 */ IC_XD_OPSIZE, /* 10812 */ IC_64BIT_REXW_XD, /* 10813 */ IC_XS_OPSIZE, /* 10814 */ IC_64BIT_REXW_XS, /* 10815 */ IC_VEX, /* 10816 */ IC_VEX, /* 10817 */ IC_VEX_XS, /* 10818 */ IC_VEX_XS, /* 10819 */ IC_VEX_XD, /* 10820 */ IC_VEX_XD, /* 10821 */ IC_VEX_XD, /* 10822 */ IC_VEX_XD, /* 10823 */ IC_VEX_W, /* 10824 */ IC_VEX_W, /* 10825 */ IC_VEX_W_XS, /* 10826 */ IC_VEX_W_XS, /* 10827 */ IC_VEX_W_XD, /* 10828 */ IC_VEX_W_XD, /* 10829 */ IC_VEX_W_XD, /* 10830 */ IC_VEX_W_XD, /* 10831 */ IC_VEX_OPSIZE, /* 10832 */ IC_VEX_OPSIZE, /* 10833 */ IC_VEX_OPSIZE, /* 10834 */ IC_VEX_OPSIZE, /* 10835 */ IC_VEX_OPSIZE, /* 10836 */ IC_VEX_OPSIZE, /* 10837 */ IC_VEX_OPSIZE, /* 10838 */ IC_VEX_OPSIZE, /* 10839 */ IC_VEX_W_OPSIZE, /* 10840 */ IC_VEX_W_OPSIZE, /* 10841 */ IC_VEX_W_OPSIZE, /* 10842 */ IC_VEX_W_OPSIZE, /* 10843 */ IC_VEX_W_OPSIZE, /* 10844 */ IC_VEX_W_OPSIZE, /* 10845 */ IC_VEX_W_OPSIZE, /* 10846 */ IC_VEX_W_OPSIZE, /* 10847 */ IC_VEX, /* 10848 */ IC_VEX, /* 10849 */ IC_VEX_XS, /* 10850 */ IC_VEX_XS, /* 10851 */ IC_VEX_XD, /* 10852 */ IC_VEX_XD, /* 10853 */ IC_VEX_XD, /* 10854 */ IC_VEX_XD, /* 10855 */ IC_VEX_W, /* 10856 */ IC_VEX_W, /* 10857 */ IC_VEX_W_XS, /* 10858 */ IC_VEX_W_XS, /* 10859 */ IC_VEX_W_XD, /* 10860 */ IC_VEX_W_XD, /* 10861 */ IC_VEX_W_XD, /* 10862 */ IC_VEX_W_XD, /* 10863 */ IC_VEX_OPSIZE, /* 10864 */ IC_VEX_OPSIZE, /* 10865 */ IC_VEX_OPSIZE, /* 10866 */ IC_VEX_OPSIZE, /* 10867 */ IC_VEX_OPSIZE, /* 10868 */ IC_VEX_OPSIZE, /* 10869 */ IC_VEX_OPSIZE, /* 10870 */ IC_VEX_OPSIZE, /* 10871 */ IC_VEX_W_OPSIZE, /* 10872 */ IC_VEX_W_OPSIZE, /* 10873 */ IC_VEX_W_OPSIZE, /* 10874 */ IC_VEX_W_OPSIZE, /* 10875 */ IC_VEX_W_OPSIZE, /* 10876 */ IC_VEX_W_OPSIZE, /* 10877 */ IC_VEX_W_OPSIZE, /* 10878 */ IC_VEX_W_OPSIZE, /* 10879 */ IC_VEX_L, /* 10880 */ IC_VEX_L, /* 10881 */ IC_VEX_L_XS, /* 10882 */ IC_VEX_L_XS, /* 10883 */ IC_VEX_L_XD, /* 10884 */ IC_VEX_L_XD, /* 10885 */ IC_VEX_L_XD, /* 10886 */ IC_VEX_L_XD, /* 10887 */ IC_VEX_L_W, /* 10888 */ IC_VEX_L_W, /* 10889 */ IC_VEX_L_W_XS, /* 10890 */ IC_VEX_L_W_XS, /* 10891 */ IC_VEX_L_W_XD, /* 10892 */ IC_VEX_L_W_XD, /* 10893 */ IC_VEX_L_W_XD, /* 10894 */ IC_VEX_L_W_XD, /* 10895 */ IC_VEX_L_OPSIZE, /* 10896 */ IC_VEX_L_OPSIZE, /* 10897 */ IC_VEX_L_OPSIZE, /* 10898 */ IC_VEX_L_OPSIZE, /* 10899 */ IC_VEX_L_OPSIZE, /* 10900 */ IC_VEX_L_OPSIZE, /* 10901 */ IC_VEX_L_OPSIZE, /* 10902 */ IC_VEX_L_OPSIZE, /* 10903 */ IC_VEX_L_W_OPSIZE, /* 10904 */ IC_VEX_L_W_OPSIZE, /* 10905 */ IC_VEX_L_W_OPSIZE, /* 10906 */ IC_VEX_L_W_OPSIZE, /* 10907 */ IC_VEX_L_W_OPSIZE, /* 10908 */ IC_VEX_L_W_OPSIZE, /* 10909 */ IC_VEX_L_W_OPSIZE, /* 10910 */ IC_VEX_L_W_OPSIZE, /* 10911 */ IC_VEX_L, /* 10912 */ IC_VEX_L, /* 10913 */ IC_VEX_L_XS, /* 10914 */ IC_VEX_L_XS, /* 10915 */ IC_VEX_L_XD, /* 10916 */ IC_VEX_L_XD, /* 10917 */ IC_VEX_L_XD, /* 10918 */ IC_VEX_L_XD, /* 10919 */ IC_VEX_L_W, /* 10920 */ IC_VEX_L_W, /* 10921 */ IC_VEX_L_W_XS, /* 10922 */ IC_VEX_L_W_XS, /* 10923 */ IC_VEX_L_W_XD, /* 10924 */ IC_VEX_L_W_XD, /* 10925 */ IC_VEX_L_W_XD, /* 10926 */ IC_VEX_L_W_XD, /* 10927 */ IC_VEX_L_OPSIZE, /* 10928 */ IC_VEX_L_OPSIZE, /* 10929 */ IC_VEX_L_OPSIZE, /* 10930 */ IC_VEX_L_OPSIZE, /* 10931 */ IC_VEX_L_OPSIZE, /* 10932 */ IC_VEX_L_OPSIZE, /* 10933 */ IC_VEX_L_OPSIZE, /* 10934 */ IC_VEX_L_OPSIZE, /* 10935 */ IC_VEX_L_W_OPSIZE, /* 10936 */ IC_VEX_L_W_OPSIZE, /* 10937 */ IC_VEX_L_W_OPSIZE, /* 10938 */ IC_VEX_L_W_OPSIZE, /* 10939 */ IC_VEX_L_W_OPSIZE, /* 10940 */ IC_VEX_L_W_OPSIZE, /* 10941 */ IC_VEX_L_W_OPSIZE, /* 10942 */ IC_VEX_L_W_OPSIZE, /* 10943 */ IC_VEX_L, /* 10944 */ IC_VEX_L, /* 10945 */ IC_VEX_L_XS, /* 10946 */ IC_VEX_L_XS, /* 10947 */ IC_VEX_L_XD, /* 10948 */ IC_VEX_L_XD, /* 10949 */ IC_VEX_L_XD, /* 10950 */ IC_VEX_L_XD, /* 10951 */ IC_VEX_L_W, /* 10952 */ IC_VEX_L_W, /* 10953 */ IC_VEX_L_W_XS, /* 10954 */ IC_VEX_L_W_XS, /* 10955 */ IC_VEX_L_W_XD, /* 10956 */ IC_VEX_L_W_XD, /* 10957 */ IC_VEX_L_W_XD, /* 10958 */ IC_VEX_L_W_XD, /* 10959 */ IC_VEX_L_OPSIZE, /* 10960 */ IC_VEX_L_OPSIZE, /* 10961 */ IC_VEX_L_OPSIZE, /* 10962 */ IC_VEX_L_OPSIZE, /* 10963 */ IC_VEX_L_OPSIZE, /* 10964 */ IC_VEX_L_OPSIZE, /* 10965 */ IC_VEX_L_OPSIZE, /* 10966 */ IC_VEX_L_OPSIZE, /* 10967 */ IC_VEX_L_W_OPSIZE, /* 10968 */ IC_VEX_L_W_OPSIZE, /* 10969 */ IC_VEX_L_W_OPSIZE, /* 10970 */ IC_VEX_L_W_OPSIZE, /* 10971 */ IC_VEX_L_W_OPSIZE, /* 10972 */ IC_VEX_L_W_OPSIZE, /* 10973 */ IC_VEX_L_W_OPSIZE, /* 10974 */ IC_VEX_L_W_OPSIZE, /* 10975 */ IC_VEX_L, /* 10976 */ IC_VEX_L, /* 10977 */ IC_VEX_L_XS, /* 10978 */ IC_VEX_L_XS, /* 10979 */ IC_VEX_L_XD, /* 10980 */ IC_VEX_L_XD, /* 10981 */ IC_VEX_L_XD, /* 10982 */ IC_VEX_L_XD, /* 10983 */ IC_VEX_L_W, /* 10984 */ IC_VEX_L_W, /* 10985 */ IC_VEX_L_W_XS, /* 10986 */ IC_VEX_L_W_XS, /* 10987 */ IC_VEX_L_W_XD, /* 10988 */ IC_VEX_L_W_XD, /* 10989 */ IC_VEX_L_W_XD, /* 10990 */ IC_VEX_L_W_XD, /* 10991 */ IC_VEX_L_OPSIZE, /* 10992 */ IC_VEX_L_OPSIZE, /* 10993 */ IC_VEX_L_OPSIZE, /* 10994 */ IC_VEX_L_OPSIZE, /* 10995 */ IC_VEX_L_OPSIZE, /* 10996 */ IC_VEX_L_OPSIZE, /* 10997 */ IC_VEX_L_OPSIZE, /* 10998 */ IC_VEX_L_OPSIZE, /* 10999 */ IC_VEX_L_W_OPSIZE, /* 11000 */ IC_VEX_L_W_OPSIZE, /* 11001 */ IC_VEX_L_W_OPSIZE, /* 11002 */ IC_VEX_L_W_OPSIZE, /* 11003 */ IC_VEX_L_W_OPSIZE, /* 11004 */ IC_VEX_L_W_OPSIZE, /* 11005 */ IC_VEX_L_W_OPSIZE, /* 11006 */ IC_VEX_L_W_OPSIZE, /* 11007 */ IC_EVEX_L_K_B, /* 11008 */ IC_EVEX_L_K_B, /* 11009 */ IC_EVEX_L_XS_K_B, /* 11010 */ IC_EVEX_L_XS_K_B, /* 11011 */ IC_EVEX_L_XD_K_B, /* 11012 */ IC_EVEX_L_XD_K_B, /* 11013 */ IC_EVEX_L_XD_K_B, /* 11014 */ IC_EVEX_L_XD_K_B, /* 11015 */ IC_EVEX_L_W_K_B, /* 11016 */ IC_EVEX_L_W_K_B, /* 11017 */ IC_EVEX_L_W_XS_K_B, /* 11018 */ IC_EVEX_L_W_XS_K_B, /* 11019 */ IC_EVEX_L_W_XD_K_B, /* 11020 */ IC_EVEX_L_W_XD_K_B, /* 11021 */ IC_EVEX_L_W_XD_K_B, /* 11022 */ IC_EVEX_L_W_XD_K_B, /* 11023 */ IC_EVEX_L_OPSIZE_K_B, /* 11024 */ IC_EVEX_L_OPSIZE_K_B, /* 11025 */ IC_EVEX_L_OPSIZE_K_B, /* 11026 */ IC_EVEX_L_OPSIZE_K_B, /* 11027 */ IC_EVEX_L_OPSIZE_K_B, /* 11028 */ IC_EVEX_L_OPSIZE_K_B, /* 11029 */ IC_EVEX_L_OPSIZE_K_B, /* 11030 */ IC_EVEX_L_OPSIZE_K_B, /* 11031 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11032 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11033 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11034 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11035 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11036 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11037 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11038 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11039 */ IC_EVEX_L_K_B, /* 11040 */ IC_EVEX_L_K_B, /* 11041 */ IC_EVEX_L_XS_K_B, /* 11042 */ IC_EVEX_L_XS_K_B, /* 11043 */ IC_EVEX_L_XD_K_B, /* 11044 */ IC_EVEX_L_XD_K_B, /* 11045 */ IC_EVEX_L_XD_K_B, /* 11046 */ IC_EVEX_L_XD_K_B, /* 11047 */ IC_EVEX_L_W_K_B, /* 11048 */ IC_EVEX_L_W_K_B, /* 11049 */ IC_EVEX_L_W_XS_K_B, /* 11050 */ IC_EVEX_L_W_XS_K_B, /* 11051 */ IC_EVEX_L_W_XD_K_B, /* 11052 */ IC_EVEX_L_W_XD_K_B, /* 11053 */ IC_EVEX_L_W_XD_K_B, /* 11054 */ IC_EVEX_L_W_XD_K_B, /* 11055 */ IC_EVEX_L_OPSIZE_K_B, /* 11056 */ IC_EVEX_L_OPSIZE_K_B, /* 11057 */ IC_EVEX_L_OPSIZE_K_B, /* 11058 */ IC_EVEX_L_OPSIZE_K_B, /* 11059 */ IC_EVEX_L_OPSIZE_K_B, /* 11060 */ IC_EVEX_L_OPSIZE_K_B, /* 11061 */ IC_EVEX_L_OPSIZE_K_B, /* 11062 */ IC_EVEX_L_OPSIZE_K_B, /* 11063 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11064 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11065 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11066 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11067 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11068 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11069 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11070 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11071 */ IC_EVEX_L_K_B, /* 11072 */ IC_EVEX_L_K_B, /* 11073 */ IC_EVEX_L_XS_K_B, /* 11074 */ IC_EVEX_L_XS_K_B, /* 11075 */ IC_EVEX_L_XD_K_B, /* 11076 */ IC_EVEX_L_XD_K_B, /* 11077 */ IC_EVEX_L_XD_K_B, /* 11078 */ IC_EVEX_L_XD_K_B, /* 11079 */ IC_EVEX_L_W_K_B, /* 11080 */ IC_EVEX_L_W_K_B, /* 11081 */ IC_EVEX_L_W_XS_K_B, /* 11082 */ IC_EVEX_L_W_XS_K_B, /* 11083 */ IC_EVEX_L_W_XD_K_B, /* 11084 */ IC_EVEX_L_W_XD_K_B, /* 11085 */ IC_EVEX_L_W_XD_K_B, /* 11086 */ IC_EVEX_L_W_XD_K_B, /* 11087 */ IC_EVEX_L_OPSIZE_K_B, /* 11088 */ IC_EVEX_L_OPSIZE_K_B, /* 11089 */ IC_EVEX_L_OPSIZE_K_B, /* 11090 */ IC_EVEX_L_OPSIZE_K_B, /* 11091 */ IC_EVEX_L_OPSIZE_K_B, /* 11092 */ IC_EVEX_L_OPSIZE_K_B, /* 11093 */ IC_EVEX_L_OPSIZE_K_B, /* 11094 */ IC_EVEX_L_OPSIZE_K_B, /* 11095 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11096 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11097 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11098 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11099 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11100 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11101 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11102 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11103 */ IC_EVEX_L_K_B, /* 11104 */ IC_EVEX_L_K_B, /* 11105 */ IC_EVEX_L_XS_K_B, /* 11106 */ IC_EVEX_L_XS_K_B, /* 11107 */ IC_EVEX_L_XD_K_B, /* 11108 */ IC_EVEX_L_XD_K_B, /* 11109 */ IC_EVEX_L_XD_K_B, /* 11110 */ IC_EVEX_L_XD_K_B, /* 11111 */ IC_EVEX_L_W_K_B, /* 11112 */ IC_EVEX_L_W_K_B, /* 11113 */ IC_EVEX_L_W_XS_K_B, /* 11114 */ IC_EVEX_L_W_XS_K_B, /* 11115 */ IC_EVEX_L_W_XD_K_B, /* 11116 */ IC_EVEX_L_W_XD_K_B, /* 11117 */ IC_EVEX_L_W_XD_K_B, /* 11118 */ IC_EVEX_L_W_XD_K_B, /* 11119 */ IC_EVEX_L_OPSIZE_K_B, /* 11120 */ IC_EVEX_L_OPSIZE_K_B, /* 11121 */ IC_EVEX_L_OPSIZE_K_B, /* 11122 */ IC_EVEX_L_OPSIZE_K_B, /* 11123 */ IC_EVEX_L_OPSIZE_K_B, /* 11124 */ IC_EVEX_L_OPSIZE_K_B, /* 11125 */ IC_EVEX_L_OPSIZE_K_B, /* 11126 */ IC_EVEX_L_OPSIZE_K_B, /* 11127 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11128 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11129 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11130 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11131 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11132 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11133 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11134 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11135 */ IC_EVEX_L_K_B, /* 11136 */ IC_EVEX_L_K_B, /* 11137 */ IC_EVEX_L_XS_K_B, /* 11138 */ IC_EVEX_L_XS_K_B, /* 11139 */ IC_EVEX_L_XD_K_B, /* 11140 */ IC_EVEX_L_XD_K_B, /* 11141 */ IC_EVEX_L_XD_K_B, /* 11142 */ IC_EVEX_L_XD_K_B, /* 11143 */ IC_EVEX_L_W_K_B, /* 11144 */ IC_EVEX_L_W_K_B, /* 11145 */ IC_EVEX_L_W_XS_K_B, /* 11146 */ IC_EVEX_L_W_XS_K_B, /* 11147 */ IC_EVEX_L_W_XD_K_B, /* 11148 */ IC_EVEX_L_W_XD_K_B, /* 11149 */ IC_EVEX_L_W_XD_K_B, /* 11150 */ IC_EVEX_L_W_XD_K_B, /* 11151 */ IC_EVEX_L_OPSIZE_K_B, /* 11152 */ IC_EVEX_L_OPSIZE_K_B, /* 11153 */ IC_EVEX_L_OPSIZE_K_B, /* 11154 */ IC_EVEX_L_OPSIZE_K_B, /* 11155 */ IC_EVEX_L_OPSIZE_K_B, /* 11156 */ IC_EVEX_L_OPSIZE_K_B, /* 11157 */ IC_EVEX_L_OPSIZE_K_B, /* 11158 */ IC_EVEX_L_OPSIZE_K_B, /* 11159 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11160 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11161 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11162 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11163 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11164 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11165 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11166 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11167 */ IC_EVEX_L_K_B, /* 11168 */ IC_EVEX_L_K_B, /* 11169 */ IC_EVEX_L_XS_K_B, /* 11170 */ IC_EVEX_L_XS_K_B, /* 11171 */ IC_EVEX_L_XD_K_B, /* 11172 */ IC_EVEX_L_XD_K_B, /* 11173 */ IC_EVEX_L_XD_K_B, /* 11174 */ IC_EVEX_L_XD_K_B, /* 11175 */ IC_EVEX_L_W_K_B, /* 11176 */ IC_EVEX_L_W_K_B, /* 11177 */ IC_EVEX_L_W_XS_K_B, /* 11178 */ IC_EVEX_L_W_XS_K_B, /* 11179 */ IC_EVEX_L_W_XD_K_B, /* 11180 */ IC_EVEX_L_W_XD_K_B, /* 11181 */ IC_EVEX_L_W_XD_K_B, /* 11182 */ IC_EVEX_L_W_XD_K_B, /* 11183 */ IC_EVEX_L_OPSIZE_K_B, /* 11184 */ IC_EVEX_L_OPSIZE_K_B, /* 11185 */ IC_EVEX_L_OPSIZE_K_B, /* 11186 */ IC_EVEX_L_OPSIZE_K_B, /* 11187 */ IC_EVEX_L_OPSIZE_K_B, /* 11188 */ IC_EVEX_L_OPSIZE_K_B, /* 11189 */ IC_EVEX_L_OPSIZE_K_B, /* 11190 */ IC_EVEX_L_OPSIZE_K_B, /* 11191 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11192 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11193 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11194 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11195 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11196 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11197 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11198 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11199 */ IC_EVEX_L_K_B, /* 11200 */ IC_EVEX_L_K_B, /* 11201 */ IC_EVEX_L_XS_K_B, /* 11202 */ IC_EVEX_L_XS_K_B, /* 11203 */ IC_EVEX_L_XD_K_B, /* 11204 */ IC_EVEX_L_XD_K_B, /* 11205 */ IC_EVEX_L_XD_K_B, /* 11206 */ IC_EVEX_L_XD_K_B, /* 11207 */ IC_EVEX_L_W_K_B, /* 11208 */ IC_EVEX_L_W_K_B, /* 11209 */ IC_EVEX_L_W_XS_K_B, /* 11210 */ IC_EVEX_L_W_XS_K_B, /* 11211 */ IC_EVEX_L_W_XD_K_B, /* 11212 */ IC_EVEX_L_W_XD_K_B, /* 11213 */ IC_EVEX_L_W_XD_K_B, /* 11214 */ IC_EVEX_L_W_XD_K_B, /* 11215 */ IC_EVEX_L_OPSIZE_K_B, /* 11216 */ IC_EVEX_L_OPSIZE_K_B, /* 11217 */ IC_EVEX_L_OPSIZE_K_B, /* 11218 */ IC_EVEX_L_OPSIZE_K_B, /* 11219 */ IC_EVEX_L_OPSIZE_K_B, /* 11220 */ IC_EVEX_L_OPSIZE_K_B, /* 11221 */ IC_EVEX_L_OPSIZE_K_B, /* 11222 */ IC_EVEX_L_OPSIZE_K_B, /* 11223 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11224 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11225 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11226 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11227 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11228 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11229 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11230 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11231 */ IC_EVEX_L_K_B, /* 11232 */ IC_EVEX_L_K_B, /* 11233 */ IC_EVEX_L_XS_K_B, /* 11234 */ IC_EVEX_L_XS_K_B, /* 11235 */ IC_EVEX_L_XD_K_B, /* 11236 */ IC_EVEX_L_XD_K_B, /* 11237 */ IC_EVEX_L_XD_K_B, /* 11238 */ IC_EVEX_L_XD_K_B, /* 11239 */ IC_EVEX_L_W_K_B, /* 11240 */ IC_EVEX_L_W_K_B, /* 11241 */ IC_EVEX_L_W_XS_K_B, /* 11242 */ IC_EVEX_L_W_XS_K_B, /* 11243 */ IC_EVEX_L_W_XD_K_B, /* 11244 */ IC_EVEX_L_W_XD_K_B, /* 11245 */ IC_EVEX_L_W_XD_K_B, /* 11246 */ IC_EVEX_L_W_XD_K_B, /* 11247 */ IC_EVEX_L_OPSIZE_K_B, /* 11248 */ IC_EVEX_L_OPSIZE_K_B, /* 11249 */ IC_EVEX_L_OPSIZE_K_B, /* 11250 */ IC_EVEX_L_OPSIZE_K_B, /* 11251 */ IC_EVEX_L_OPSIZE_K_B, /* 11252 */ IC_EVEX_L_OPSIZE_K_B, /* 11253 */ IC_EVEX_L_OPSIZE_K_B, /* 11254 */ IC_EVEX_L_OPSIZE_K_B, /* 11255 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11256 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11257 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11258 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11259 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11260 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11261 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11262 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11263 */ IC, /* 11264 */ IC_64BIT, /* 11265 */ IC_XS, /* 11266 */ IC_64BIT_XS, /* 11267 */ IC_XD, /* 11268 */ IC_64BIT_XD, /* 11269 */ IC_XS, /* 11270 */ IC_64BIT_XS, /* 11271 */ IC, /* 11272 */ IC_64BIT_REXW, /* 11273 */ IC_XS, /* 11274 */ IC_64BIT_REXW_XS, /* 11275 */ IC_XD, /* 11276 */ IC_64BIT_REXW_XD, /* 11277 */ IC_XS, /* 11278 */ IC_64BIT_REXW_XS, /* 11279 */ IC_OPSIZE, /* 11280 */ IC_64BIT_OPSIZE, /* 11281 */ IC_XS_OPSIZE, /* 11282 */ IC_64BIT_XS_OPSIZE, /* 11283 */ IC_XD_OPSIZE, /* 11284 */ IC_64BIT_XD_OPSIZE, /* 11285 */ IC_XS_OPSIZE, /* 11286 */ IC_64BIT_XD_OPSIZE, /* 11287 */ IC_OPSIZE, /* 11288 */ IC_64BIT_REXW_OPSIZE, /* 11289 */ IC_XS_OPSIZE, /* 11290 */ IC_64BIT_REXW_XS, /* 11291 */ IC_XD_OPSIZE, /* 11292 */ IC_64BIT_REXW_XD, /* 11293 */ IC_XS_OPSIZE, /* 11294 */ IC_64BIT_REXW_XS, /* 11295 */ IC_ADSIZE, /* 11296 */ IC_64BIT_ADSIZE, /* 11297 */ IC_XS_ADSIZE, /* 11298 */ IC_64BIT_XS_ADSIZE, /* 11299 */ IC_XD_ADSIZE, /* 11300 */ IC_64BIT_XD_ADSIZE, /* 11301 */ IC_XS_ADSIZE, /* 11302 */ IC_64BIT_XD_ADSIZE, /* 11303 */ IC_ADSIZE, /* 11304 */ IC_64BIT_REXW_ADSIZE, /* 11305 */ IC_XS_ADSIZE, /* 11306 */ IC_64BIT_REXW_XS, /* 11307 */ IC_XD_ADSIZE, /* 11308 */ IC_64BIT_REXW_XD, /* 11309 */ IC_XS_ADSIZE, /* 11310 */ IC_64BIT_REXW_XS, /* 11311 */ IC_OPSIZE_ADSIZE, /* 11312 */ IC_64BIT_OPSIZE_ADSIZE, /* 11313 */ IC_XS_OPSIZE, /* 11314 */ IC_64BIT_XS_OPSIZE, /* 11315 */ IC_XD_OPSIZE, /* 11316 */ IC_64BIT_XD_OPSIZE, /* 11317 */ IC_XS_OPSIZE, /* 11318 */ IC_64BIT_XD_OPSIZE, /* 11319 */ IC_OPSIZE_ADSIZE, /* 11320 */ IC_64BIT_REXW_OPSIZE, /* 11321 */ IC_XS_OPSIZE, /* 11322 */ IC_64BIT_REXW_XS, /* 11323 */ IC_XD_OPSIZE, /* 11324 */ IC_64BIT_REXW_XD, /* 11325 */ IC_XS_OPSIZE, /* 11326 */ IC_64BIT_REXW_XS, /* 11327 */ IC_VEX, /* 11328 */ IC_VEX, /* 11329 */ IC_VEX_XS, /* 11330 */ IC_VEX_XS, /* 11331 */ IC_VEX_XD, /* 11332 */ IC_VEX_XD, /* 11333 */ IC_VEX_XD, /* 11334 */ IC_VEX_XD, /* 11335 */ IC_VEX_W, /* 11336 */ IC_VEX_W, /* 11337 */ IC_VEX_W_XS, /* 11338 */ IC_VEX_W_XS, /* 11339 */ IC_VEX_W_XD, /* 11340 */ IC_VEX_W_XD, /* 11341 */ IC_VEX_W_XD, /* 11342 */ IC_VEX_W_XD, /* 11343 */ IC_VEX_OPSIZE, /* 11344 */ IC_VEX_OPSIZE, /* 11345 */ IC_VEX_OPSIZE, /* 11346 */ IC_VEX_OPSIZE, /* 11347 */ IC_VEX_OPSIZE, /* 11348 */ IC_VEX_OPSIZE, /* 11349 */ IC_VEX_OPSIZE, /* 11350 */ IC_VEX_OPSIZE, /* 11351 */ IC_VEX_W_OPSIZE, /* 11352 */ IC_VEX_W_OPSIZE, /* 11353 */ IC_VEX_W_OPSIZE, /* 11354 */ IC_VEX_W_OPSIZE, /* 11355 */ IC_VEX_W_OPSIZE, /* 11356 */ IC_VEX_W_OPSIZE, /* 11357 */ IC_VEX_W_OPSIZE, /* 11358 */ IC_VEX_W_OPSIZE, /* 11359 */ IC_VEX, /* 11360 */ IC_VEX, /* 11361 */ IC_VEX_XS, /* 11362 */ IC_VEX_XS, /* 11363 */ IC_VEX_XD, /* 11364 */ IC_VEX_XD, /* 11365 */ IC_VEX_XD, /* 11366 */ IC_VEX_XD, /* 11367 */ IC_VEX_W, /* 11368 */ IC_VEX_W, /* 11369 */ IC_VEX_W_XS, /* 11370 */ IC_VEX_W_XS, /* 11371 */ IC_VEX_W_XD, /* 11372 */ IC_VEX_W_XD, /* 11373 */ IC_VEX_W_XD, /* 11374 */ IC_VEX_W_XD, /* 11375 */ IC_VEX_OPSIZE, /* 11376 */ IC_VEX_OPSIZE, /* 11377 */ IC_VEX_OPSIZE, /* 11378 */ IC_VEX_OPSIZE, /* 11379 */ IC_VEX_OPSIZE, /* 11380 */ IC_VEX_OPSIZE, /* 11381 */ IC_VEX_OPSIZE, /* 11382 */ IC_VEX_OPSIZE, /* 11383 */ IC_VEX_W_OPSIZE, /* 11384 */ IC_VEX_W_OPSIZE, /* 11385 */ IC_VEX_W_OPSIZE, /* 11386 */ IC_VEX_W_OPSIZE, /* 11387 */ IC_VEX_W_OPSIZE, /* 11388 */ IC_VEX_W_OPSIZE, /* 11389 */ IC_VEX_W_OPSIZE, /* 11390 */ IC_VEX_W_OPSIZE, /* 11391 */ IC_VEX_L, /* 11392 */ IC_VEX_L, /* 11393 */ IC_VEX_L_XS, /* 11394 */ IC_VEX_L_XS, /* 11395 */ IC_VEX_L_XD, /* 11396 */ IC_VEX_L_XD, /* 11397 */ IC_VEX_L_XD, /* 11398 */ IC_VEX_L_XD, /* 11399 */ IC_VEX_L_W, /* 11400 */ IC_VEX_L_W, /* 11401 */ IC_VEX_L_W_XS, /* 11402 */ IC_VEX_L_W_XS, /* 11403 */ IC_VEX_L_W_XD, /* 11404 */ IC_VEX_L_W_XD, /* 11405 */ IC_VEX_L_W_XD, /* 11406 */ IC_VEX_L_W_XD, /* 11407 */ IC_VEX_L_OPSIZE, /* 11408 */ IC_VEX_L_OPSIZE, /* 11409 */ IC_VEX_L_OPSIZE, /* 11410 */ IC_VEX_L_OPSIZE, /* 11411 */ IC_VEX_L_OPSIZE, /* 11412 */ IC_VEX_L_OPSIZE, /* 11413 */ IC_VEX_L_OPSIZE, /* 11414 */ IC_VEX_L_OPSIZE, /* 11415 */ IC_VEX_L_W_OPSIZE, /* 11416 */ IC_VEX_L_W_OPSIZE, /* 11417 */ IC_VEX_L_W_OPSIZE, /* 11418 */ IC_VEX_L_W_OPSIZE, /* 11419 */ IC_VEX_L_W_OPSIZE, /* 11420 */ IC_VEX_L_W_OPSIZE, /* 11421 */ IC_VEX_L_W_OPSIZE, /* 11422 */ IC_VEX_L_W_OPSIZE, /* 11423 */ IC_VEX_L, /* 11424 */ IC_VEX_L, /* 11425 */ IC_VEX_L_XS, /* 11426 */ IC_VEX_L_XS, /* 11427 */ IC_VEX_L_XD, /* 11428 */ IC_VEX_L_XD, /* 11429 */ IC_VEX_L_XD, /* 11430 */ IC_VEX_L_XD, /* 11431 */ IC_VEX_L_W, /* 11432 */ IC_VEX_L_W, /* 11433 */ IC_VEX_L_W_XS, /* 11434 */ IC_VEX_L_W_XS, /* 11435 */ IC_VEX_L_W_XD, /* 11436 */ IC_VEX_L_W_XD, /* 11437 */ IC_VEX_L_W_XD, /* 11438 */ IC_VEX_L_W_XD, /* 11439 */ IC_VEX_L_OPSIZE, /* 11440 */ IC_VEX_L_OPSIZE, /* 11441 */ IC_VEX_L_OPSIZE, /* 11442 */ IC_VEX_L_OPSIZE, /* 11443 */ IC_VEX_L_OPSIZE, /* 11444 */ IC_VEX_L_OPSIZE, /* 11445 */ IC_VEX_L_OPSIZE, /* 11446 */ IC_VEX_L_OPSIZE, /* 11447 */ IC_VEX_L_W_OPSIZE, /* 11448 */ IC_VEX_L_W_OPSIZE, /* 11449 */ IC_VEX_L_W_OPSIZE, /* 11450 */ IC_VEX_L_W_OPSIZE, /* 11451 */ IC_VEX_L_W_OPSIZE, /* 11452 */ IC_VEX_L_W_OPSIZE, /* 11453 */ IC_VEX_L_W_OPSIZE, /* 11454 */ IC_VEX_L_W_OPSIZE, /* 11455 */ IC_VEX_L, /* 11456 */ IC_VEX_L, /* 11457 */ IC_VEX_L_XS, /* 11458 */ IC_VEX_L_XS, /* 11459 */ IC_VEX_L_XD, /* 11460 */ IC_VEX_L_XD, /* 11461 */ IC_VEX_L_XD, /* 11462 */ IC_VEX_L_XD, /* 11463 */ IC_VEX_L_W, /* 11464 */ IC_VEX_L_W, /* 11465 */ IC_VEX_L_W_XS, /* 11466 */ IC_VEX_L_W_XS, /* 11467 */ IC_VEX_L_W_XD, /* 11468 */ IC_VEX_L_W_XD, /* 11469 */ IC_VEX_L_W_XD, /* 11470 */ IC_VEX_L_W_XD, /* 11471 */ IC_VEX_L_OPSIZE, /* 11472 */ IC_VEX_L_OPSIZE, /* 11473 */ IC_VEX_L_OPSIZE, /* 11474 */ IC_VEX_L_OPSIZE, /* 11475 */ IC_VEX_L_OPSIZE, /* 11476 */ IC_VEX_L_OPSIZE, /* 11477 */ IC_VEX_L_OPSIZE, /* 11478 */ IC_VEX_L_OPSIZE, /* 11479 */ IC_VEX_L_W_OPSIZE, /* 11480 */ IC_VEX_L_W_OPSIZE, /* 11481 */ IC_VEX_L_W_OPSIZE, /* 11482 */ IC_VEX_L_W_OPSIZE, /* 11483 */ IC_VEX_L_W_OPSIZE, /* 11484 */ IC_VEX_L_W_OPSIZE, /* 11485 */ IC_VEX_L_W_OPSIZE, /* 11486 */ IC_VEX_L_W_OPSIZE, /* 11487 */ IC_VEX_L, /* 11488 */ IC_VEX_L, /* 11489 */ IC_VEX_L_XS, /* 11490 */ IC_VEX_L_XS, /* 11491 */ IC_VEX_L_XD, /* 11492 */ IC_VEX_L_XD, /* 11493 */ IC_VEX_L_XD, /* 11494 */ IC_VEX_L_XD, /* 11495 */ IC_VEX_L_W, /* 11496 */ IC_VEX_L_W, /* 11497 */ IC_VEX_L_W_XS, /* 11498 */ IC_VEX_L_W_XS, /* 11499 */ IC_VEX_L_W_XD, /* 11500 */ IC_VEX_L_W_XD, /* 11501 */ IC_VEX_L_W_XD, /* 11502 */ IC_VEX_L_W_XD, /* 11503 */ IC_VEX_L_OPSIZE, /* 11504 */ IC_VEX_L_OPSIZE, /* 11505 */ IC_VEX_L_OPSIZE, /* 11506 */ IC_VEX_L_OPSIZE, /* 11507 */ IC_VEX_L_OPSIZE, /* 11508 */ IC_VEX_L_OPSIZE, /* 11509 */ IC_VEX_L_OPSIZE, /* 11510 */ IC_VEX_L_OPSIZE, /* 11511 */ IC_VEX_L_W_OPSIZE, /* 11512 */ IC_VEX_L_W_OPSIZE, /* 11513 */ IC_VEX_L_W_OPSIZE, /* 11514 */ IC_VEX_L_W_OPSIZE, /* 11515 */ IC_VEX_L_W_OPSIZE, /* 11516 */ IC_VEX_L_W_OPSIZE, /* 11517 */ IC_VEX_L_W_OPSIZE, /* 11518 */ IC_VEX_L_W_OPSIZE, /* 11519 */ IC_EVEX_L2_K_B, /* 11520 */ IC_EVEX_L2_K_B, /* 11521 */ IC_EVEX_L2_XS_K_B, /* 11522 */ IC_EVEX_L2_XS_K_B, /* 11523 */ IC_EVEX_L2_XD_K_B, /* 11524 */ IC_EVEX_L2_XD_K_B, /* 11525 */ IC_EVEX_L2_XD_K_B, /* 11526 */ IC_EVEX_L2_XD_K_B, /* 11527 */ IC_EVEX_L2_W_K_B, /* 11528 */ IC_EVEX_L2_W_K_B, /* 11529 */ IC_EVEX_L2_W_XS_K_B, /* 11530 */ IC_EVEX_L2_W_XS_K_B, /* 11531 */ IC_EVEX_L2_W_XD_K_B, /* 11532 */ IC_EVEX_L2_W_XD_K_B, /* 11533 */ IC_EVEX_L2_W_XD_K_B, /* 11534 */ IC_EVEX_L2_W_XD_K_B, /* 11535 */ IC_EVEX_L2_OPSIZE_K_B, /* 11536 */ IC_EVEX_L2_OPSIZE_K_B, /* 11537 */ IC_EVEX_L2_OPSIZE_K_B, /* 11538 */ IC_EVEX_L2_OPSIZE_K_B, /* 11539 */ IC_EVEX_L2_OPSIZE_K_B, /* 11540 */ IC_EVEX_L2_OPSIZE_K_B, /* 11541 */ IC_EVEX_L2_OPSIZE_K_B, /* 11542 */ IC_EVEX_L2_OPSIZE_K_B, /* 11543 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11544 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11545 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11546 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11547 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11548 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11549 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11550 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11551 */ IC_EVEX_L2_K_B, /* 11552 */ IC_EVEX_L2_K_B, /* 11553 */ IC_EVEX_L2_XS_K_B, /* 11554 */ IC_EVEX_L2_XS_K_B, /* 11555 */ IC_EVEX_L2_XD_K_B, /* 11556 */ IC_EVEX_L2_XD_K_B, /* 11557 */ IC_EVEX_L2_XD_K_B, /* 11558 */ IC_EVEX_L2_XD_K_B, /* 11559 */ IC_EVEX_L2_W_K_B, /* 11560 */ IC_EVEX_L2_W_K_B, /* 11561 */ IC_EVEX_L2_W_XS_K_B, /* 11562 */ IC_EVEX_L2_W_XS_K_B, /* 11563 */ IC_EVEX_L2_W_XD_K_B, /* 11564 */ IC_EVEX_L2_W_XD_K_B, /* 11565 */ IC_EVEX_L2_W_XD_K_B, /* 11566 */ IC_EVEX_L2_W_XD_K_B, /* 11567 */ IC_EVEX_L2_OPSIZE_K_B, /* 11568 */ IC_EVEX_L2_OPSIZE_K_B, /* 11569 */ IC_EVEX_L2_OPSIZE_K_B, /* 11570 */ IC_EVEX_L2_OPSIZE_K_B, /* 11571 */ IC_EVEX_L2_OPSIZE_K_B, /* 11572 */ IC_EVEX_L2_OPSIZE_K_B, /* 11573 */ IC_EVEX_L2_OPSIZE_K_B, /* 11574 */ IC_EVEX_L2_OPSIZE_K_B, /* 11575 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11576 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11577 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11578 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11579 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11580 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11581 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11582 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11583 */ IC_EVEX_L2_K_B, /* 11584 */ IC_EVEX_L2_K_B, /* 11585 */ IC_EVEX_L2_XS_K_B, /* 11586 */ IC_EVEX_L2_XS_K_B, /* 11587 */ IC_EVEX_L2_XD_K_B, /* 11588 */ IC_EVEX_L2_XD_K_B, /* 11589 */ IC_EVEX_L2_XD_K_B, /* 11590 */ IC_EVEX_L2_XD_K_B, /* 11591 */ IC_EVEX_L2_W_K_B, /* 11592 */ IC_EVEX_L2_W_K_B, /* 11593 */ IC_EVEX_L2_W_XS_K_B, /* 11594 */ IC_EVEX_L2_W_XS_K_B, /* 11595 */ IC_EVEX_L2_W_XD_K_B, /* 11596 */ IC_EVEX_L2_W_XD_K_B, /* 11597 */ IC_EVEX_L2_W_XD_K_B, /* 11598 */ IC_EVEX_L2_W_XD_K_B, /* 11599 */ IC_EVEX_L2_OPSIZE_K_B, /* 11600 */ IC_EVEX_L2_OPSIZE_K_B, /* 11601 */ IC_EVEX_L2_OPSIZE_K_B, /* 11602 */ IC_EVEX_L2_OPSIZE_K_B, /* 11603 */ IC_EVEX_L2_OPSIZE_K_B, /* 11604 */ IC_EVEX_L2_OPSIZE_K_B, /* 11605 */ IC_EVEX_L2_OPSIZE_K_B, /* 11606 */ IC_EVEX_L2_OPSIZE_K_B, /* 11607 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11608 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11609 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11610 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11611 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11612 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11613 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11614 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11615 */ IC_EVEX_L2_K_B, /* 11616 */ IC_EVEX_L2_K_B, /* 11617 */ IC_EVEX_L2_XS_K_B, /* 11618 */ IC_EVEX_L2_XS_K_B, /* 11619 */ IC_EVEX_L2_XD_K_B, /* 11620 */ IC_EVEX_L2_XD_K_B, /* 11621 */ IC_EVEX_L2_XD_K_B, /* 11622 */ IC_EVEX_L2_XD_K_B, /* 11623 */ IC_EVEX_L2_W_K_B, /* 11624 */ IC_EVEX_L2_W_K_B, /* 11625 */ IC_EVEX_L2_W_XS_K_B, /* 11626 */ IC_EVEX_L2_W_XS_K_B, /* 11627 */ IC_EVEX_L2_W_XD_K_B, /* 11628 */ IC_EVEX_L2_W_XD_K_B, /* 11629 */ IC_EVEX_L2_W_XD_K_B, /* 11630 */ IC_EVEX_L2_W_XD_K_B, /* 11631 */ IC_EVEX_L2_OPSIZE_K_B, /* 11632 */ IC_EVEX_L2_OPSIZE_K_B, /* 11633 */ IC_EVEX_L2_OPSIZE_K_B, /* 11634 */ IC_EVEX_L2_OPSIZE_K_B, /* 11635 */ IC_EVEX_L2_OPSIZE_K_B, /* 11636 */ IC_EVEX_L2_OPSIZE_K_B, /* 11637 */ IC_EVEX_L2_OPSIZE_K_B, /* 11638 */ IC_EVEX_L2_OPSIZE_K_B, /* 11639 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11640 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11641 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11642 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11643 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11644 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11645 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11646 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11647 */ IC_EVEX_L2_K_B, /* 11648 */ IC_EVEX_L2_K_B, /* 11649 */ IC_EVEX_L2_XS_K_B, /* 11650 */ IC_EVEX_L2_XS_K_B, /* 11651 */ IC_EVEX_L2_XD_K_B, /* 11652 */ IC_EVEX_L2_XD_K_B, /* 11653 */ IC_EVEX_L2_XD_K_B, /* 11654 */ IC_EVEX_L2_XD_K_B, /* 11655 */ IC_EVEX_L2_W_K_B, /* 11656 */ IC_EVEX_L2_W_K_B, /* 11657 */ IC_EVEX_L2_W_XS_K_B, /* 11658 */ IC_EVEX_L2_W_XS_K_B, /* 11659 */ IC_EVEX_L2_W_XD_K_B, /* 11660 */ IC_EVEX_L2_W_XD_K_B, /* 11661 */ IC_EVEX_L2_W_XD_K_B, /* 11662 */ IC_EVEX_L2_W_XD_K_B, /* 11663 */ IC_EVEX_L2_OPSIZE_K_B, /* 11664 */ IC_EVEX_L2_OPSIZE_K_B, /* 11665 */ IC_EVEX_L2_OPSIZE_K_B, /* 11666 */ IC_EVEX_L2_OPSIZE_K_B, /* 11667 */ IC_EVEX_L2_OPSIZE_K_B, /* 11668 */ IC_EVEX_L2_OPSIZE_K_B, /* 11669 */ IC_EVEX_L2_OPSIZE_K_B, /* 11670 */ IC_EVEX_L2_OPSIZE_K_B, /* 11671 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11672 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11673 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11674 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11675 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11676 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11677 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11678 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11679 */ IC_EVEX_L2_K_B, /* 11680 */ IC_EVEX_L2_K_B, /* 11681 */ IC_EVEX_L2_XS_K_B, /* 11682 */ IC_EVEX_L2_XS_K_B, /* 11683 */ IC_EVEX_L2_XD_K_B, /* 11684 */ IC_EVEX_L2_XD_K_B, /* 11685 */ IC_EVEX_L2_XD_K_B, /* 11686 */ IC_EVEX_L2_XD_K_B, /* 11687 */ IC_EVEX_L2_W_K_B, /* 11688 */ IC_EVEX_L2_W_K_B, /* 11689 */ IC_EVEX_L2_W_XS_K_B, /* 11690 */ IC_EVEX_L2_W_XS_K_B, /* 11691 */ IC_EVEX_L2_W_XD_K_B, /* 11692 */ IC_EVEX_L2_W_XD_K_B, /* 11693 */ IC_EVEX_L2_W_XD_K_B, /* 11694 */ IC_EVEX_L2_W_XD_K_B, /* 11695 */ IC_EVEX_L2_OPSIZE_K_B, /* 11696 */ IC_EVEX_L2_OPSIZE_K_B, /* 11697 */ IC_EVEX_L2_OPSIZE_K_B, /* 11698 */ IC_EVEX_L2_OPSIZE_K_B, /* 11699 */ IC_EVEX_L2_OPSIZE_K_B, /* 11700 */ IC_EVEX_L2_OPSIZE_K_B, /* 11701 */ IC_EVEX_L2_OPSIZE_K_B, /* 11702 */ IC_EVEX_L2_OPSIZE_K_B, /* 11703 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11704 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11705 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11706 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11707 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11708 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11709 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11710 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11711 */ IC_EVEX_L2_K_B, /* 11712 */ IC_EVEX_L2_K_B, /* 11713 */ IC_EVEX_L2_XS_K_B, /* 11714 */ IC_EVEX_L2_XS_K_B, /* 11715 */ IC_EVEX_L2_XD_K_B, /* 11716 */ IC_EVEX_L2_XD_K_B, /* 11717 */ IC_EVEX_L2_XD_K_B, /* 11718 */ IC_EVEX_L2_XD_K_B, /* 11719 */ IC_EVEX_L2_W_K_B, /* 11720 */ IC_EVEX_L2_W_K_B, /* 11721 */ IC_EVEX_L2_W_XS_K_B, /* 11722 */ IC_EVEX_L2_W_XS_K_B, /* 11723 */ IC_EVEX_L2_W_XD_K_B, /* 11724 */ IC_EVEX_L2_W_XD_K_B, /* 11725 */ IC_EVEX_L2_W_XD_K_B, /* 11726 */ IC_EVEX_L2_W_XD_K_B, /* 11727 */ IC_EVEX_L2_OPSIZE_K_B, /* 11728 */ IC_EVEX_L2_OPSIZE_K_B, /* 11729 */ IC_EVEX_L2_OPSIZE_K_B, /* 11730 */ IC_EVEX_L2_OPSIZE_K_B, /* 11731 */ IC_EVEX_L2_OPSIZE_K_B, /* 11732 */ IC_EVEX_L2_OPSIZE_K_B, /* 11733 */ IC_EVEX_L2_OPSIZE_K_B, /* 11734 */ IC_EVEX_L2_OPSIZE_K_B, /* 11735 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11736 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11737 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11738 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11739 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11740 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11741 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11742 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11743 */ IC_EVEX_L2_K_B, /* 11744 */ IC_EVEX_L2_K_B, /* 11745 */ IC_EVEX_L2_XS_K_B, /* 11746 */ IC_EVEX_L2_XS_K_B, /* 11747 */ IC_EVEX_L2_XD_K_B, /* 11748 */ IC_EVEX_L2_XD_K_B, /* 11749 */ IC_EVEX_L2_XD_K_B, /* 11750 */ IC_EVEX_L2_XD_K_B, /* 11751 */ IC_EVEX_L2_W_K_B, /* 11752 */ IC_EVEX_L2_W_K_B, /* 11753 */ IC_EVEX_L2_W_XS_K_B, /* 11754 */ IC_EVEX_L2_W_XS_K_B, /* 11755 */ IC_EVEX_L2_W_XD_K_B, /* 11756 */ IC_EVEX_L2_W_XD_K_B, /* 11757 */ IC_EVEX_L2_W_XD_K_B, /* 11758 */ IC_EVEX_L2_W_XD_K_B, /* 11759 */ IC_EVEX_L2_OPSIZE_K_B, /* 11760 */ IC_EVEX_L2_OPSIZE_K_B, /* 11761 */ IC_EVEX_L2_OPSIZE_K_B, /* 11762 */ IC_EVEX_L2_OPSIZE_K_B, /* 11763 */ IC_EVEX_L2_OPSIZE_K_B, /* 11764 */ IC_EVEX_L2_OPSIZE_K_B, /* 11765 */ IC_EVEX_L2_OPSIZE_K_B, /* 11766 */ IC_EVEX_L2_OPSIZE_K_B, /* 11767 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11768 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11769 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11770 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11771 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11772 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11773 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11774 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11775 */ IC, /* 11776 */ IC_64BIT, /* 11777 */ IC_XS, /* 11778 */ IC_64BIT_XS, /* 11779 */ IC_XD, /* 11780 */ IC_64BIT_XD, /* 11781 */ IC_XS, /* 11782 */ IC_64BIT_XS, /* 11783 */ IC, /* 11784 */ IC_64BIT_REXW, /* 11785 */ IC_XS, /* 11786 */ IC_64BIT_REXW_XS, /* 11787 */ IC_XD, /* 11788 */ IC_64BIT_REXW_XD, /* 11789 */ IC_XS, /* 11790 */ IC_64BIT_REXW_XS, /* 11791 */ IC_OPSIZE, /* 11792 */ IC_64BIT_OPSIZE, /* 11793 */ IC_XS_OPSIZE, /* 11794 */ IC_64BIT_XS_OPSIZE, /* 11795 */ IC_XD_OPSIZE, /* 11796 */ IC_64BIT_XD_OPSIZE, /* 11797 */ IC_XS_OPSIZE, /* 11798 */ IC_64BIT_XD_OPSIZE, /* 11799 */ IC_OPSIZE, /* 11800 */ IC_64BIT_REXW_OPSIZE, /* 11801 */ IC_XS_OPSIZE, /* 11802 */ IC_64BIT_REXW_XS, /* 11803 */ IC_XD_OPSIZE, /* 11804 */ IC_64BIT_REXW_XD, /* 11805 */ IC_XS_OPSIZE, /* 11806 */ IC_64BIT_REXW_XS, /* 11807 */ IC_ADSIZE, /* 11808 */ IC_64BIT_ADSIZE, /* 11809 */ IC_XS_ADSIZE, /* 11810 */ IC_64BIT_XS_ADSIZE, /* 11811 */ IC_XD_ADSIZE, /* 11812 */ IC_64BIT_XD_ADSIZE, /* 11813 */ IC_XS_ADSIZE, /* 11814 */ IC_64BIT_XD_ADSIZE, /* 11815 */ IC_ADSIZE, /* 11816 */ IC_64BIT_REXW_ADSIZE, /* 11817 */ IC_XS_ADSIZE, /* 11818 */ IC_64BIT_REXW_XS, /* 11819 */ IC_XD_ADSIZE, /* 11820 */ IC_64BIT_REXW_XD, /* 11821 */ IC_XS_ADSIZE, /* 11822 */ IC_64BIT_REXW_XS, /* 11823 */ IC_OPSIZE_ADSIZE, /* 11824 */ IC_64BIT_OPSIZE_ADSIZE, /* 11825 */ IC_XS_OPSIZE, /* 11826 */ IC_64BIT_XS_OPSIZE, /* 11827 */ IC_XD_OPSIZE, /* 11828 */ IC_64BIT_XD_OPSIZE, /* 11829 */ IC_XS_OPSIZE, /* 11830 */ IC_64BIT_XD_OPSIZE, /* 11831 */ IC_OPSIZE_ADSIZE, /* 11832 */ IC_64BIT_REXW_OPSIZE, /* 11833 */ IC_XS_OPSIZE, /* 11834 */ IC_64BIT_REXW_XS, /* 11835 */ IC_XD_OPSIZE, /* 11836 */ IC_64BIT_REXW_XD, /* 11837 */ IC_XS_OPSIZE, /* 11838 */ IC_64BIT_REXW_XS, /* 11839 */ IC_VEX, /* 11840 */ IC_VEX, /* 11841 */ IC_VEX_XS, /* 11842 */ IC_VEX_XS, /* 11843 */ IC_VEX_XD, /* 11844 */ IC_VEX_XD, /* 11845 */ IC_VEX_XD, /* 11846 */ IC_VEX_XD, /* 11847 */ IC_VEX_W, /* 11848 */ IC_VEX_W, /* 11849 */ IC_VEX_W_XS, /* 11850 */ IC_VEX_W_XS, /* 11851 */ IC_VEX_W_XD, /* 11852 */ IC_VEX_W_XD, /* 11853 */ IC_VEX_W_XD, /* 11854 */ IC_VEX_W_XD, /* 11855 */ IC_VEX_OPSIZE, /* 11856 */ IC_VEX_OPSIZE, /* 11857 */ IC_VEX_OPSIZE, /* 11858 */ IC_VEX_OPSIZE, /* 11859 */ IC_VEX_OPSIZE, /* 11860 */ IC_VEX_OPSIZE, /* 11861 */ IC_VEX_OPSIZE, /* 11862 */ IC_VEX_OPSIZE, /* 11863 */ IC_VEX_W_OPSIZE, /* 11864 */ IC_VEX_W_OPSIZE, /* 11865 */ IC_VEX_W_OPSIZE, /* 11866 */ IC_VEX_W_OPSIZE, /* 11867 */ IC_VEX_W_OPSIZE, /* 11868 */ IC_VEX_W_OPSIZE, /* 11869 */ IC_VEX_W_OPSIZE, /* 11870 */ IC_VEX_W_OPSIZE, /* 11871 */ IC_VEX, /* 11872 */ IC_VEX, /* 11873 */ IC_VEX_XS, /* 11874 */ IC_VEX_XS, /* 11875 */ IC_VEX_XD, /* 11876 */ IC_VEX_XD, /* 11877 */ IC_VEX_XD, /* 11878 */ IC_VEX_XD, /* 11879 */ IC_VEX_W, /* 11880 */ IC_VEX_W, /* 11881 */ IC_VEX_W_XS, /* 11882 */ IC_VEX_W_XS, /* 11883 */ IC_VEX_W_XD, /* 11884 */ IC_VEX_W_XD, /* 11885 */ IC_VEX_W_XD, /* 11886 */ IC_VEX_W_XD, /* 11887 */ IC_VEX_OPSIZE, /* 11888 */ IC_VEX_OPSIZE, /* 11889 */ IC_VEX_OPSIZE, /* 11890 */ IC_VEX_OPSIZE, /* 11891 */ IC_VEX_OPSIZE, /* 11892 */ IC_VEX_OPSIZE, /* 11893 */ IC_VEX_OPSIZE, /* 11894 */ IC_VEX_OPSIZE, /* 11895 */ IC_VEX_W_OPSIZE, /* 11896 */ IC_VEX_W_OPSIZE, /* 11897 */ IC_VEX_W_OPSIZE, /* 11898 */ IC_VEX_W_OPSIZE, /* 11899 */ IC_VEX_W_OPSIZE, /* 11900 */ IC_VEX_W_OPSIZE, /* 11901 */ IC_VEX_W_OPSIZE, /* 11902 */ IC_VEX_W_OPSIZE, /* 11903 */ IC_VEX_L, /* 11904 */ IC_VEX_L, /* 11905 */ IC_VEX_L_XS, /* 11906 */ IC_VEX_L_XS, /* 11907 */ IC_VEX_L_XD, /* 11908 */ IC_VEX_L_XD, /* 11909 */ IC_VEX_L_XD, /* 11910 */ IC_VEX_L_XD, /* 11911 */ IC_VEX_L_W, /* 11912 */ IC_VEX_L_W, /* 11913 */ IC_VEX_L_W_XS, /* 11914 */ IC_VEX_L_W_XS, /* 11915 */ IC_VEX_L_W_XD, /* 11916 */ IC_VEX_L_W_XD, /* 11917 */ IC_VEX_L_W_XD, /* 11918 */ IC_VEX_L_W_XD, /* 11919 */ IC_VEX_L_OPSIZE, /* 11920 */ IC_VEX_L_OPSIZE, /* 11921 */ IC_VEX_L_OPSIZE, /* 11922 */ IC_VEX_L_OPSIZE, /* 11923 */ IC_VEX_L_OPSIZE, /* 11924 */ IC_VEX_L_OPSIZE, /* 11925 */ IC_VEX_L_OPSIZE, /* 11926 */ IC_VEX_L_OPSIZE, /* 11927 */ IC_VEX_L_W_OPSIZE, /* 11928 */ IC_VEX_L_W_OPSIZE, /* 11929 */ IC_VEX_L_W_OPSIZE, /* 11930 */ IC_VEX_L_W_OPSIZE, /* 11931 */ IC_VEX_L_W_OPSIZE, /* 11932 */ IC_VEX_L_W_OPSIZE, /* 11933 */ IC_VEX_L_W_OPSIZE, /* 11934 */ IC_VEX_L_W_OPSIZE, /* 11935 */ IC_VEX_L, /* 11936 */ IC_VEX_L, /* 11937 */ IC_VEX_L_XS, /* 11938 */ IC_VEX_L_XS, /* 11939 */ IC_VEX_L_XD, /* 11940 */ IC_VEX_L_XD, /* 11941 */ IC_VEX_L_XD, /* 11942 */ IC_VEX_L_XD, /* 11943 */ IC_VEX_L_W, /* 11944 */ IC_VEX_L_W, /* 11945 */ IC_VEX_L_W_XS, /* 11946 */ IC_VEX_L_W_XS, /* 11947 */ IC_VEX_L_W_XD, /* 11948 */ IC_VEX_L_W_XD, /* 11949 */ IC_VEX_L_W_XD, /* 11950 */ IC_VEX_L_W_XD, /* 11951 */ IC_VEX_L_OPSIZE, /* 11952 */ IC_VEX_L_OPSIZE, /* 11953 */ IC_VEX_L_OPSIZE, /* 11954 */ IC_VEX_L_OPSIZE, /* 11955 */ IC_VEX_L_OPSIZE, /* 11956 */ IC_VEX_L_OPSIZE, /* 11957 */ IC_VEX_L_OPSIZE, /* 11958 */ IC_VEX_L_OPSIZE, /* 11959 */ IC_VEX_L_W_OPSIZE, /* 11960 */ IC_VEX_L_W_OPSIZE, /* 11961 */ IC_VEX_L_W_OPSIZE, /* 11962 */ IC_VEX_L_W_OPSIZE, /* 11963 */ IC_VEX_L_W_OPSIZE, /* 11964 */ IC_VEX_L_W_OPSIZE, /* 11965 */ IC_VEX_L_W_OPSIZE, /* 11966 */ IC_VEX_L_W_OPSIZE, /* 11967 */ IC_VEX_L, /* 11968 */ IC_VEX_L, /* 11969 */ IC_VEX_L_XS, /* 11970 */ IC_VEX_L_XS, /* 11971 */ IC_VEX_L_XD, /* 11972 */ IC_VEX_L_XD, /* 11973 */ IC_VEX_L_XD, /* 11974 */ IC_VEX_L_XD, /* 11975 */ IC_VEX_L_W, /* 11976 */ IC_VEX_L_W, /* 11977 */ IC_VEX_L_W_XS, /* 11978 */ IC_VEX_L_W_XS, /* 11979 */ IC_VEX_L_W_XD, /* 11980 */ IC_VEX_L_W_XD, /* 11981 */ IC_VEX_L_W_XD, /* 11982 */ IC_VEX_L_W_XD, /* 11983 */ IC_VEX_L_OPSIZE, /* 11984 */ IC_VEX_L_OPSIZE, /* 11985 */ IC_VEX_L_OPSIZE, /* 11986 */ IC_VEX_L_OPSIZE, /* 11987 */ IC_VEX_L_OPSIZE, /* 11988 */ IC_VEX_L_OPSIZE, /* 11989 */ IC_VEX_L_OPSIZE, /* 11990 */ IC_VEX_L_OPSIZE, /* 11991 */ IC_VEX_L_W_OPSIZE, /* 11992 */ IC_VEX_L_W_OPSIZE, /* 11993 */ IC_VEX_L_W_OPSIZE, /* 11994 */ IC_VEX_L_W_OPSIZE, /* 11995 */ IC_VEX_L_W_OPSIZE, /* 11996 */ IC_VEX_L_W_OPSIZE, /* 11997 */ IC_VEX_L_W_OPSIZE, /* 11998 */ IC_VEX_L_W_OPSIZE, /* 11999 */ IC_VEX_L, /* 12000 */ IC_VEX_L, /* 12001 */ IC_VEX_L_XS, /* 12002 */ IC_VEX_L_XS, /* 12003 */ IC_VEX_L_XD, /* 12004 */ IC_VEX_L_XD, /* 12005 */ IC_VEX_L_XD, /* 12006 */ IC_VEX_L_XD, /* 12007 */ IC_VEX_L_W, /* 12008 */ IC_VEX_L_W, /* 12009 */ IC_VEX_L_W_XS, /* 12010 */ IC_VEX_L_W_XS, /* 12011 */ IC_VEX_L_W_XD, /* 12012 */ IC_VEX_L_W_XD, /* 12013 */ IC_VEX_L_W_XD, /* 12014 */ IC_VEX_L_W_XD, /* 12015 */ IC_VEX_L_OPSIZE, /* 12016 */ IC_VEX_L_OPSIZE, /* 12017 */ IC_VEX_L_OPSIZE, /* 12018 */ IC_VEX_L_OPSIZE, /* 12019 */ IC_VEX_L_OPSIZE, /* 12020 */ IC_VEX_L_OPSIZE, /* 12021 */ IC_VEX_L_OPSIZE, /* 12022 */ IC_VEX_L_OPSIZE, /* 12023 */ IC_VEX_L_W_OPSIZE, /* 12024 */ IC_VEX_L_W_OPSIZE, /* 12025 */ IC_VEX_L_W_OPSIZE, /* 12026 */ IC_VEX_L_W_OPSIZE, /* 12027 */ IC_VEX_L_W_OPSIZE, /* 12028 */ IC_VEX_L_W_OPSIZE, /* 12029 */ IC_VEX_L_W_OPSIZE, /* 12030 */ IC_VEX_L_W_OPSIZE, /* 12031 */ IC_EVEX_L2_K_B, /* 12032 */ IC_EVEX_L2_K_B, /* 12033 */ IC_EVEX_L2_XS_K_B, /* 12034 */ IC_EVEX_L2_XS_K_B, /* 12035 */ IC_EVEX_L2_XD_K_B, /* 12036 */ IC_EVEX_L2_XD_K_B, /* 12037 */ IC_EVEX_L2_XD_K_B, /* 12038 */ IC_EVEX_L2_XD_K_B, /* 12039 */ IC_EVEX_L2_W_K_B, /* 12040 */ IC_EVEX_L2_W_K_B, /* 12041 */ IC_EVEX_L2_W_XS_K_B, /* 12042 */ IC_EVEX_L2_W_XS_K_B, /* 12043 */ IC_EVEX_L2_W_XD_K_B, /* 12044 */ IC_EVEX_L2_W_XD_K_B, /* 12045 */ IC_EVEX_L2_W_XD_K_B, /* 12046 */ IC_EVEX_L2_W_XD_K_B, /* 12047 */ IC_EVEX_L2_OPSIZE_K_B, /* 12048 */ IC_EVEX_L2_OPSIZE_K_B, /* 12049 */ IC_EVEX_L2_OPSIZE_K_B, /* 12050 */ IC_EVEX_L2_OPSIZE_K_B, /* 12051 */ IC_EVEX_L2_OPSIZE_K_B, /* 12052 */ IC_EVEX_L2_OPSIZE_K_B, /* 12053 */ IC_EVEX_L2_OPSIZE_K_B, /* 12054 */ IC_EVEX_L2_OPSIZE_K_B, /* 12055 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12056 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12057 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12058 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12059 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12060 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12061 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12062 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12063 */ IC_EVEX_L2_K_B, /* 12064 */ IC_EVEX_L2_K_B, /* 12065 */ IC_EVEX_L2_XS_K_B, /* 12066 */ IC_EVEX_L2_XS_K_B, /* 12067 */ IC_EVEX_L2_XD_K_B, /* 12068 */ IC_EVEX_L2_XD_K_B, /* 12069 */ IC_EVEX_L2_XD_K_B, /* 12070 */ IC_EVEX_L2_XD_K_B, /* 12071 */ IC_EVEX_L2_W_K_B, /* 12072 */ IC_EVEX_L2_W_K_B, /* 12073 */ IC_EVEX_L2_W_XS_K_B, /* 12074 */ IC_EVEX_L2_W_XS_K_B, /* 12075 */ IC_EVEX_L2_W_XD_K_B, /* 12076 */ IC_EVEX_L2_W_XD_K_B, /* 12077 */ IC_EVEX_L2_W_XD_K_B, /* 12078 */ IC_EVEX_L2_W_XD_K_B, /* 12079 */ IC_EVEX_L2_OPSIZE_K_B, /* 12080 */ IC_EVEX_L2_OPSIZE_K_B, /* 12081 */ IC_EVEX_L2_OPSIZE_K_B, /* 12082 */ IC_EVEX_L2_OPSIZE_K_B, /* 12083 */ IC_EVEX_L2_OPSIZE_K_B, /* 12084 */ IC_EVEX_L2_OPSIZE_K_B, /* 12085 */ IC_EVEX_L2_OPSIZE_K_B, /* 12086 */ IC_EVEX_L2_OPSIZE_K_B, /* 12087 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12088 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12089 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12090 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12091 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12092 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12093 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12094 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12095 */ IC_EVEX_L2_K_B, /* 12096 */ IC_EVEX_L2_K_B, /* 12097 */ IC_EVEX_L2_XS_K_B, /* 12098 */ IC_EVEX_L2_XS_K_B, /* 12099 */ IC_EVEX_L2_XD_K_B, /* 12100 */ IC_EVEX_L2_XD_K_B, /* 12101 */ IC_EVEX_L2_XD_K_B, /* 12102 */ IC_EVEX_L2_XD_K_B, /* 12103 */ IC_EVEX_L2_W_K_B, /* 12104 */ IC_EVEX_L2_W_K_B, /* 12105 */ IC_EVEX_L2_W_XS_K_B, /* 12106 */ IC_EVEX_L2_W_XS_K_B, /* 12107 */ IC_EVEX_L2_W_XD_K_B, /* 12108 */ IC_EVEX_L2_W_XD_K_B, /* 12109 */ IC_EVEX_L2_W_XD_K_B, /* 12110 */ IC_EVEX_L2_W_XD_K_B, /* 12111 */ IC_EVEX_L2_OPSIZE_K_B, /* 12112 */ IC_EVEX_L2_OPSIZE_K_B, /* 12113 */ IC_EVEX_L2_OPSIZE_K_B, /* 12114 */ IC_EVEX_L2_OPSIZE_K_B, /* 12115 */ IC_EVEX_L2_OPSIZE_K_B, /* 12116 */ IC_EVEX_L2_OPSIZE_K_B, /* 12117 */ IC_EVEX_L2_OPSIZE_K_B, /* 12118 */ IC_EVEX_L2_OPSIZE_K_B, /* 12119 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12120 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12121 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12122 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12123 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12124 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12125 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12126 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12127 */ IC_EVEX_L2_K_B, /* 12128 */ IC_EVEX_L2_K_B, /* 12129 */ IC_EVEX_L2_XS_K_B, /* 12130 */ IC_EVEX_L2_XS_K_B, /* 12131 */ IC_EVEX_L2_XD_K_B, /* 12132 */ IC_EVEX_L2_XD_K_B, /* 12133 */ IC_EVEX_L2_XD_K_B, /* 12134 */ IC_EVEX_L2_XD_K_B, /* 12135 */ IC_EVEX_L2_W_K_B, /* 12136 */ IC_EVEX_L2_W_K_B, /* 12137 */ IC_EVEX_L2_W_XS_K_B, /* 12138 */ IC_EVEX_L2_W_XS_K_B, /* 12139 */ IC_EVEX_L2_W_XD_K_B, /* 12140 */ IC_EVEX_L2_W_XD_K_B, /* 12141 */ IC_EVEX_L2_W_XD_K_B, /* 12142 */ IC_EVEX_L2_W_XD_K_B, /* 12143 */ IC_EVEX_L2_OPSIZE_K_B, /* 12144 */ IC_EVEX_L2_OPSIZE_K_B, /* 12145 */ IC_EVEX_L2_OPSIZE_K_B, /* 12146 */ IC_EVEX_L2_OPSIZE_K_B, /* 12147 */ IC_EVEX_L2_OPSIZE_K_B, /* 12148 */ IC_EVEX_L2_OPSIZE_K_B, /* 12149 */ IC_EVEX_L2_OPSIZE_K_B, /* 12150 */ IC_EVEX_L2_OPSIZE_K_B, /* 12151 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12152 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12153 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12154 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12155 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12156 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12157 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12158 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12159 */ IC_EVEX_L2_K_B, /* 12160 */ IC_EVEX_L2_K_B, /* 12161 */ IC_EVEX_L2_XS_K_B, /* 12162 */ IC_EVEX_L2_XS_K_B, /* 12163 */ IC_EVEX_L2_XD_K_B, /* 12164 */ IC_EVEX_L2_XD_K_B, /* 12165 */ IC_EVEX_L2_XD_K_B, /* 12166 */ IC_EVEX_L2_XD_K_B, /* 12167 */ IC_EVEX_L2_W_K_B, /* 12168 */ IC_EVEX_L2_W_K_B, /* 12169 */ IC_EVEX_L2_W_XS_K_B, /* 12170 */ IC_EVEX_L2_W_XS_K_B, /* 12171 */ IC_EVEX_L2_W_XD_K_B, /* 12172 */ IC_EVEX_L2_W_XD_K_B, /* 12173 */ IC_EVEX_L2_W_XD_K_B, /* 12174 */ IC_EVEX_L2_W_XD_K_B, /* 12175 */ IC_EVEX_L2_OPSIZE_K_B, /* 12176 */ IC_EVEX_L2_OPSIZE_K_B, /* 12177 */ IC_EVEX_L2_OPSIZE_K_B, /* 12178 */ IC_EVEX_L2_OPSIZE_K_B, /* 12179 */ IC_EVEX_L2_OPSIZE_K_B, /* 12180 */ IC_EVEX_L2_OPSIZE_K_B, /* 12181 */ IC_EVEX_L2_OPSIZE_K_B, /* 12182 */ IC_EVEX_L2_OPSIZE_K_B, /* 12183 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12184 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12185 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12186 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12187 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12188 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12189 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12190 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12191 */ IC_EVEX_L2_K_B, /* 12192 */ IC_EVEX_L2_K_B, /* 12193 */ IC_EVEX_L2_XS_K_B, /* 12194 */ IC_EVEX_L2_XS_K_B, /* 12195 */ IC_EVEX_L2_XD_K_B, /* 12196 */ IC_EVEX_L2_XD_K_B, /* 12197 */ IC_EVEX_L2_XD_K_B, /* 12198 */ IC_EVEX_L2_XD_K_B, /* 12199 */ IC_EVEX_L2_W_K_B, /* 12200 */ IC_EVEX_L2_W_K_B, /* 12201 */ IC_EVEX_L2_W_XS_K_B, /* 12202 */ IC_EVEX_L2_W_XS_K_B, /* 12203 */ IC_EVEX_L2_W_XD_K_B, /* 12204 */ IC_EVEX_L2_W_XD_K_B, /* 12205 */ IC_EVEX_L2_W_XD_K_B, /* 12206 */ IC_EVEX_L2_W_XD_K_B, /* 12207 */ IC_EVEX_L2_OPSIZE_K_B, /* 12208 */ IC_EVEX_L2_OPSIZE_K_B, /* 12209 */ IC_EVEX_L2_OPSIZE_K_B, /* 12210 */ IC_EVEX_L2_OPSIZE_K_B, /* 12211 */ IC_EVEX_L2_OPSIZE_K_B, /* 12212 */ IC_EVEX_L2_OPSIZE_K_B, /* 12213 */ IC_EVEX_L2_OPSIZE_K_B, /* 12214 */ IC_EVEX_L2_OPSIZE_K_B, /* 12215 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12216 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12217 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12218 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12219 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12220 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12221 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12222 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12223 */ IC_EVEX_L2_K_B, /* 12224 */ IC_EVEX_L2_K_B, /* 12225 */ IC_EVEX_L2_XS_K_B, /* 12226 */ IC_EVEX_L2_XS_K_B, /* 12227 */ IC_EVEX_L2_XD_K_B, /* 12228 */ IC_EVEX_L2_XD_K_B, /* 12229 */ IC_EVEX_L2_XD_K_B, /* 12230 */ IC_EVEX_L2_XD_K_B, /* 12231 */ IC_EVEX_L2_W_K_B, /* 12232 */ IC_EVEX_L2_W_K_B, /* 12233 */ IC_EVEX_L2_W_XS_K_B, /* 12234 */ IC_EVEX_L2_W_XS_K_B, /* 12235 */ IC_EVEX_L2_W_XD_K_B, /* 12236 */ IC_EVEX_L2_W_XD_K_B, /* 12237 */ IC_EVEX_L2_W_XD_K_B, /* 12238 */ IC_EVEX_L2_W_XD_K_B, /* 12239 */ IC_EVEX_L2_OPSIZE_K_B, /* 12240 */ IC_EVEX_L2_OPSIZE_K_B, /* 12241 */ IC_EVEX_L2_OPSIZE_K_B, /* 12242 */ IC_EVEX_L2_OPSIZE_K_B, /* 12243 */ IC_EVEX_L2_OPSIZE_K_B, /* 12244 */ IC_EVEX_L2_OPSIZE_K_B, /* 12245 */ IC_EVEX_L2_OPSIZE_K_B, /* 12246 */ IC_EVEX_L2_OPSIZE_K_B, /* 12247 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12248 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12249 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12250 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12251 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12252 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12253 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12254 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12255 */ IC_EVEX_L2_K_B, /* 12256 */ IC_EVEX_L2_K_B, /* 12257 */ IC_EVEX_L2_XS_K_B, /* 12258 */ IC_EVEX_L2_XS_K_B, /* 12259 */ IC_EVEX_L2_XD_K_B, /* 12260 */ IC_EVEX_L2_XD_K_B, /* 12261 */ IC_EVEX_L2_XD_K_B, /* 12262 */ IC_EVEX_L2_XD_K_B, /* 12263 */ IC_EVEX_L2_W_K_B, /* 12264 */ IC_EVEX_L2_W_K_B, /* 12265 */ IC_EVEX_L2_W_XS_K_B, /* 12266 */ IC_EVEX_L2_W_XS_K_B, /* 12267 */ IC_EVEX_L2_W_XD_K_B, /* 12268 */ IC_EVEX_L2_W_XD_K_B, /* 12269 */ IC_EVEX_L2_W_XD_K_B, /* 12270 */ IC_EVEX_L2_W_XD_K_B, /* 12271 */ IC_EVEX_L2_OPSIZE_K_B, /* 12272 */ IC_EVEX_L2_OPSIZE_K_B, /* 12273 */ IC_EVEX_L2_OPSIZE_K_B, /* 12274 */ IC_EVEX_L2_OPSIZE_K_B, /* 12275 */ IC_EVEX_L2_OPSIZE_K_B, /* 12276 */ IC_EVEX_L2_OPSIZE_K_B, /* 12277 */ IC_EVEX_L2_OPSIZE_K_B, /* 12278 */ IC_EVEX_L2_OPSIZE_K_B, /* 12279 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12280 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12281 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12282 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12283 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12284 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12285 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12286 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12287 */ IC, /* 12288 */ IC_64BIT, /* 12289 */ IC_XS, /* 12290 */ IC_64BIT_XS, /* 12291 */ IC_XD, /* 12292 */ IC_64BIT_XD, /* 12293 */ IC_XS, /* 12294 */ IC_64BIT_XS, /* 12295 */ IC, /* 12296 */ IC_64BIT_REXW, /* 12297 */ IC_XS, /* 12298 */ IC_64BIT_REXW_XS, /* 12299 */ IC_XD, /* 12300 */ IC_64BIT_REXW_XD, /* 12301 */ IC_XS, /* 12302 */ IC_64BIT_REXW_XS, /* 12303 */ IC_OPSIZE, /* 12304 */ IC_64BIT_OPSIZE, /* 12305 */ IC_XS_OPSIZE, /* 12306 */ IC_64BIT_XS_OPSIZE, /* 12307 */ IC_XD_OPSIZE, /* 12308 */ IC_64BIT_XD_OPSIZE, /* 12309 */ IC_XS_OPSIZE, /* 12310 */ IC_64BIT_XD_OPSIZE, /* 12311 */ IC_OPSIZE, /* 12312 */ IC_64BIT_REXW_OPSIZE, /* 12313 */ IC_XS_OPSIZE, /* 12314 */ IC_64BIT_REXW_XS, /* 12315 */ IC_XD_OPSIZE, /* 12316 */ IC_64BIT_REXW_XD, /* 12317 */ IC_XS_OPSIZE, /* 12318 */ IC_64BIT_REXW_XS, /* 12319 */ IC_ADSIZE, /* 12320 */ IC_64BIT_ADSIZE, /* 12321 */ IC_XS_ADSIZE, /* 12322 */ IC_64BIT_XS_ADSIZE, /* 12323 */ IC_XD_ADSIZE, /* 12324 */ IC_64BIT_XD_ADSIZE, /* 12325 */ IC_XS_ADSIZE, /* 12326 */ IC_64BIT_XD_ADSIZE, /* 12327 */ IC_ADSIZE, /* 12328 */ IC_64BIT_REXW_ADSIZE, /* 12329 */ IC_XS_ADSIZE, /* 12330 */ IC_64BIT_REXW_XS, /* 12331 */ IC_XD_ADSIZE, /* 12332 */ IC_64BIT_REXW_XD, /* 12333 */ IC_XS_ADSIZE, /* 12334 */ IC_64BIT_REXW_XS, /* 12335 */ IC_OPSIZE_ADSIZE, /* 12336 */ IC_64BIT_OPSIZE_ADSIZE, /* 12337 */ IC_XS_OPSIZE, /* 12338 */ IC_64BIT_XS_OPSIZE, /* 12339 */ IC_XD_OPSIZE, /* 12340 */ IC_64BIT_XD_OPSIZE, /* 12341 */ IC_XS_OPSIZE, /* 12342 */ IC_64BIT_XD_OPSIZE, /* 12343 */ IC_OPSIZE_ADSIZE, /* 12344 */ IC_64BIT_REXW_OPSIZE, /* 12345 */ IC_XS_OPSIZE, /* 12346 */ IC_64BIT_REXW_XS, /* 12347 */ IC_XD_OPSIZE, /* 12348 */ IC_64BIT_REXW_XD, /* 12349 */ IC_XS_OPSIZE, /* 12350 */ IC_64BIT_REXW_XS, /* 12351 */ IC_VEX, /* 12352 */ IC_VEX, /* 12353 */ IC_VEX_XS, /* 12354 */ IC_VEX_XS, /* 12355 */ IC_VEX_XD, /* 12356 */ IC_VEX_XD, /* 12357 */ IC_VEX_XD, /* 12358 */ IC_VEX_XD, /* 12359 */ IC_VEX_W, /* 12360 */ IC_VEX_W, /* 12361 */ IC_VEX_W_XS, /* 12362 */ IC_VEX_W_XS, /* 12363 */ IC_VEX_W_XD, /* 12364 */ IC_VEX_W_XD, /* 12365 */ IC_VEX_W_XD, /* 12366 */ IC_VEX_W_XD, /* 12367 */ IC_VEX_OPSIZE, /* 12368 */ IC_VEX_OPSIZE, /* 12369 */ IC_VEX_OPSIZE, /* 12370 */ IC_VEX_OPSIZE, /* 12371 */ IC_VEX_OPSIZE, /* 12372 */ IC_VEX_OPSIZE, /* 12373 */ IC_VEX_OPSIZE, /* 12374 */ IC_VEX_OPSIZE, /* 12375 */ IC_VEX_W_OPSIZE, /* 12376 */ IC_VEX_W_OPSIZE, /* 12377 */ IC_VEX_W_OPSIZE, /* 12378 */ IC_VEX_W_OPSIZE, /* 12379 */ IC_VEX_W_OPSIZE, /* 12380 */ IC_VEX_W_OPSIZE, /* 12381 */ IC_VEX_W_OPSIZE, /* 12382 */ IC_VEX_W_OPSIZE, /* 12383 */ IC_VEX, /* 12384 */ IC_VEX, /* 12385 */ IC_VEX_XS, /* 12386 */ IC_VEX_XS, /* 12387 */ IC_VEX_XD, /* 12388 */ IC_VEX_XD, /* 12389 */ IC_VEX_XD, /* 12390 */ IC_VEX_XD, /* 12391 */ IC_VEX_W, /* 12392 */ IC_VEX_W, /* 12393 */ IC_VEX_W_XS, /* 12394 */ IC_VEX_W_XS, /* 12395 */ IC_VEX_W_XD, /* 12396 */ IC_VEX_W_XD, /* 12397 */ IC_VEX_W_XD, /* 12398 */ IC_VEX_W_XD, /* 12399 */ IC_VEX_OPSIZE, /* 12400 */ IC_VEX_OPSIZE, /* 12401 */ IC_VEX_OPSIZE, /* 12402 */ IC_VEX_OPSIZE, /* 12403 */ IC_VEX_OPSIZE, /* 12404 */ IC_VEX_OPSIZE, /* 12405 */ IC_VEX_OPSIZE, /* 12406 */ IC_VEX_OPSIZE, /* 12407 */ IC_VEX_W_OPSIZE, /* 12408 */ IC_VEX_W_OPSIZE, /* 12409 */ IC_VEX_W_OPSIZE, /* 12410 */ IC_VEX_W_OPSIZE, /* 12411 */ IC_VEX_W_OPSIZE, /* 12412 */ IC_VEX_W_OPSIZE, /* 12413 */ IC_VEX_W_OPSIZE, /* 12414 */ IC_VEX_W_OPSIZE, /* 12415 */ IC_VEX_L, /* 12416 */ IC_VEX_L, /* 12417 */ IC_VEX_L_XS, /* 12418 */ IC_VEX_L_XS, /* 12419 */ IC_VEX_L_XD, /* 12420 */ IC_VEX_L_XD, /* 12421 */ IC_VEX_L_XD, /* 12422 */ IC_VEX_L_XD, /* 12423 */ IC_VEX_L_W, /* 12424 */ IC_VEX_L_W, /* 12425 */ IC_VEX_L_W_XS, /* 12426 */ IC_VEX_L_W_XS, /* 12427 */ IC_VEX_L_W_XD, /* 12428 */ IC_VEX_L_W_XD, /* 12429 */ IC_VEX_L_W_XD, /* 12430 */ IC_VEX_L_W_XD, /* 12431 */ IC_VEX_L_OPSIZE, /* 12432 */ IC_VEX_L_OPSIZE, /* 12433 */ IC_VEX_L_OPSIZE, /* 12434 */ IC_VEX_L_OPSIZE, /* 12435 */ IC_VEX_L_OPSIZE, /* 12436 */ IC_VEX_L_OPSIZE, /* 12437 */ IC_VEX_L_OPSIZE, /* 12438 */ IC_VEX_L_OPSIZE, /* 12439 */ IC_VEX_L_W_OPSIZE, /* 12440 */ IC_VEX_L_W_OPSIZE, /* 12441 */ IC_VEX_L_W_OPSIZE, /* 12442 */ IC_VEX_L_W_OPSIZE, /* 12443 */ IC_VEX_L_W_OPSIZE, /* 12444 */ IC_VEX_L_W_OPSIZE, /* 12445 */ IC_VEX_L_W_OPSIZE, /* 12446 */ IC_VEX_L_W_OPSIZE, /* 12447 */ IC_VEX_L, /* 12448 */ IC_VEX_L, /* 12449 */ IC_VEX_L_XS, /* 12450 */ IC_VEX_L_XS, /* 12451 */ IC_VEX_L_XD, /* 12452 */ IC_VEX_L_XD, /* 12453 */ IC_VEX_L_XD, /* 12454 */ IC_VEX_L_XD, /* 12455 */ IC_VEX_L_W, /* 12456 */ IC_VEX_L_W, /* 12457 */ IC_VEX_L_W_XS, /* 12458 */ IC_VEX_L_W_XS, /* 12459 */ IC_VEX_L_W_XD, /* 12460 */ IC_VEX_L_W_XD, /* 12461 */ IC_VEX_L_W_XD, /* 12462 */ IC_VEX_L_W_XD, /* 12463 */ IC_VEX_L_OPSIZE, /* 12464 */ IC_VEX_L_OPSIZE, /* 12465 */ IC_VEX_L_OPSIZE, /* 12466 */ IC_VEX_L_OPSIZE, /* 12467 */ IC_VEX_L_OPSIZE, /* 12468 */ IC_VEX_L_OPSIZE, /* 12469 */ IC_VEX_L_OPSIZE, /* 12470 */ IC_VEX_L_OPSIZE, /* 12471 */ IC_VEX_L_W_OPSIZE, /* 12472 */ IC_VEX_L_W_OPSIZE, /* 12473 */ IC_VEX_L_W_OPSIZE, /* 12474 */ IC_VEX_L_W_OPSIZE, /* 12475 */ IC_VEX_L_W_OPSIZE, /* 12476 */ IC_VEX_L_W_OPSIZE, /* 12477 */ IC_VEX_L_W_OPSIZE, /* 12478 */ IC_VEX_L_W_OPSIZE, /* 12479 */ IC_VEX_L, /* 12480 */ IC_VEX_L, /* 12481 */ IC_VEX_L_XS, /* 12482 */ IC_VEX_L_XS, /* 12483 */ IC_VEX_L_XD, /* 12484 */ IC_VEX_L_XD, /* 12485 */ IC_VEX_L_XD, /* 12486 */ IC_VEX_L_XD, /* 12487 */ IC_VEX_L_W, /* 12488 */ IC_VEX_L_W, /* 12489 */ IC_VEX_L_W_XS, /* 12490 */ IC_VEX_L_W_XS, /* 12491 */ IC_VEX_L_W_XD, /* 12492 */ IC_VEX_L_W_XD, /* 12493 */ IC_VEX_L_W_XD, /* 12494 */ IC_VEX_L_W_XD, /* 12495 */ IC_VEX_L_OPSIZE, /* 12496 */ IC_VEX_L_OPSIZE, /* 12497 */ IC_VEX_L_OPSIZE, /* 12498 */ IC_VEX_L_OPSIZE, /* 12499 */ IC_VEX_L_OPSIZE, /* 12500 */ IC_VEX_L_OPSIZE, /* 12501 */ IC_VEX_L_OPSIZE, /* 12502 */ IC_VEX_L_OPSIZE, /* 12503 */ IC_VEX_L_W_OPSIZE, /* 12504 */ IC_VEX_L_W_OPSIZE, /* 12505 */ IC_VEX_L_W_OPSIZE, /* 12506 */ IC_VEX_L_W_OPSIZE, /* 12507 */ IC_VEX_L_W_OPSIZE, /* 12508 */ IC_VEX_L_W_OPSIZE, /* 12509 */ IC_VEX_L_W_OPSIZE, /* 12510 */ IC_VEX_L_W_OPSIZE, /* 12511 */ IC_VEX_L, /* 12512 */ IC_VEX_L, /* 12513 */ IC_VEX_L_XS, /* 12514 */ IC_VEX_L_XS, /* 12515 */ IC_VEX_L_XD, /* 12516 */ IC_VEX_L_XD, /* 12517 */ IC_VEX_L_XD, /* 12518 */ IC_VEX_L_XD, /* 12519 */ IC_VEX_L_W, /* 12520 */ IC_VEX_L_W, /* 12521 */ IC_VEX_L_W_XS, /* 12522 */ IC_VEX_L_W_XS, /* 12523 */ IC_VEX_L_W_XD, /* 12524 */ IC_VEX_L_W_XD, /* 12525 */ IC_VEX_L_W_XD, /* 12526 */ IC_VEX_L_W_XD, /* 12527 */ IC_VEX_L_OPSIZE, /* 12528 */ IC_VEX_L_OPSIZE, /* 12529 */ IC_VEX_L_OPSIZE, /* 12530 */ IC_VEX_L_OPSIZE, /* 12531 */ IC_VEX_L_OPSIZE, /* 12532 */ IC_VEX_L_OPSIZE, /* 12533 */ IC_VEX_L_OPSIZE, /* 12534 */ IC_VEX_L_OPSIZE, /* 12535 */ IC_VEX_L_W_OPSIZE, /* 12536 */ IC_VEX_L_W_OPSIZE, /* 12537 */ IC_VEX_L_W_OPSIZE, /* 12538 */ IC_VEX_L_W_OPSIZE, /* 12539 */ IC_VEX_L_W_OPSIZE, /* 12540 */ IC_VEX_L_W_OPSIZE, /* 12541 */ IC_VEX_L_W_OPSIZE, /* 12542 */ IC_VEX_L_W_OPSIZE, /* 12543 */ IC_EVEX_KZ_B, /* 12544 */ IC_EVEX_KZ_B, /* 12545 */ IC_EVEX_XS_KZ_B, /* 12546 */ IC_EVEX_XS_KZ_B, /* 12547 */ IC_EVEX_XD_KZ_B, /* 12548 */ IC_EVEX_XD_KZ_B, /* 12549 */ IC_EVEX_XD_KZ_B, /* 12550 */ IC_EVEX_XD_KZ_B, /* 12551 */ IC_EVEX_W_KZ_B, /* 12552 */ IC_EVEX_W_KZ_B, /* 12553 */ IC_EVEX_W_XS_KZ_B, /* 12554 */ IC_EVEX_W_XS_KZ_B, /* 12555 */ IC_EVEX_W_XD_KZ_B, /* 12556 */ IC_EVEX_W_XD_KZ_B, /* 12557 */ IC_EVEX_W_XD_KZ_B, /* 12558 */ IC_EVEX_W_XD_KZ_B, /* 12559 */ IC_EVEX_OPSIZE_KZ_B, /* 12560 */ IC_EVEX_OPSIZE_KZ_B, /* 12561 */ IC_EVEX_OPSIZE_KZ_B, /* 12562 */ IC_EVEX_OPSIZE_KZ_B, /* 12563 */ IC_EVEX_OPSIZE_KZ_B, /* 12564 */ IC_EVEX_OPSIZE_KZ_B, /* 12565 */ IC_EVEX_OPSIZE_KZ_B, /* 12566 */ IC_EVEX_OPSIZE_KZ_B, /* 12567 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12568 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12569 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12570 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12571 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12572 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12573 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12574 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12575 */ IC_EVEX_KZ_B, /* 12576 */ IC_EVEX_KZ_B, /* 12577 */ IC_EVEX_XS_KZ_B, /* 12578 */ IC_EVEX_XS_KZ_B, /* 12579 */ IC_EVEX_XD_KZ_B, /* 12580 */ IC_EVEX_XD_KZ_B, /* 12581 */ IC_EVEX_XD_KZ_B, /* 12582 */ IC_EVEX_XD_KZ_B, /* 12583 */ IC_EVEX_W_KZ_B, /* 12584 */ IC_EVEX_W_KZ_B, /* 12585 */ IC_EVEX_W_XS_KZ_B, /* 12586 */ IC_EVEX_W_XS_KZ_B, /* 12587 */ IC_EVEX_W_XD_KZ_B, /* 12588 */ IC_EVEX_W_XD_KZ_B, /* 12589 */ IC_EVEX_W_XD_KZ_B, /* 12590 */ IC_EVEX_W_XD_KZ_B, /* 12591 */ IC_EVEX_OPSIZE_KZ_B, /* 12592 */ IC_EVEX_OPSIZE_KZ_B, /* 12593 */ IC_EVEX_OPSIZE_KZ_B, /* 12594 */ IC_EVEX_OPSIZE_KZ_B, /* 12595 */ IC_EVEX_OPSIZE_KZ_B, /* 12596 */ IC_EVEX_OPSIZE_KZ_B, /* 12597 */ IC_EVEX_OPSIZE_KZ_B, /* 12598 */ IC_EVEX_OPSIZE_KZ_B, /* 12599 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12600 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12601 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12602 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12603 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12604 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12605 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12606 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12607 */ IC_EVEX_KZ_B, /* 12608 */ IC_EVEX_KZ_B, /* 12609 */ IC_EVEX_XS_KZ_B, /* 12610 */ IC_EVEX_XS_KZ_B, /* 12611 */ IC_EVEX_XD_KZ_B, /* 12612 */ IC_EVEX_XD_KZ_B, /* 12613 */ IC_EVEX_XD_KZ_B, /* 12614 */ IC_EVEX_XD_KZ_B, /* 12615 */ IC_EVEX_W_KZ_B, /* 12616 */ IC_EVEX_W_KZ_B, /* 12617 */ IC_EVEX_W_XS_KZ_B, /* 12618 */ IC_EVEX_W_XS_KZ_B, /* 12619 */ IC_EVEX_W_XD_KZ_B, /* 12620 */ IC_EVEX_W_XD_KZ_B, /* 12621 */ IC_EVEX_W_XD_KZ_B, /* 12622 */ IC_EVEX_W_XD_KZ_B, /* 12623 */ IC_EVEX_OPSIZE_KZ_B, /* 12624 */ IC_EVEX_OPSIZE_KZ_B, /* 12625 */ IC_EVEX_OPSIZE_KZ_B, /* 12626 */ IC_EVEX_OPSIZE_KZ_B, /* 12627 */ IC_EVEX_OPSIZE_KZ_B, /* 12628 */ IC_EVEX_OPSIZE_KZ_B, /* 12629 */ IC_EVEX_OPSIZE_KZ_B, /* 12630 */ IC_EVEX_OPSIZE_KZ_B, /* 12631 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12632 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12633 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12634 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12635 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12636 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12637 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12638 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12639 */ IC_EVEX_KZ_B, /* 12640 */ IC_EVEX_KZ_B, /* 12641 */ IC_EVEX_XS_KZ_B, /* 12642 */ IC_EVEX_XS_KZ_B, /* 12643 */ IC_EVEX_XD_KZ_B, /* 12644 */ IC_EVEX_XD_KZ_B, /* 12645 */ IC_EVEX_XD_KZ_B, /* 12646 */ IC_EVEX_XD_KZ_B, /* 12647 */ IC_EVEX_W_KZ_B, /* 12648 */ IC_EVEX_W_KZ_B, /* 12649 */ IC_EVEX_W_XS_KZ_B, /* 12650 */ IC_EVEX_W_XS_KZ_B, /* 12651 */ IC_EVEX_W_XD_KZ_B, /* 12652 */ IC_EVEX_W_XD_KZ_B, /* 12653 */ IC_EVEX_W_XD_KZ_B, /* 12654 */ IC_EVEX_W_XD_KZ_B, /* 12655 */ IC_EVEX_OPSIZE_KZ_B, /* 12656 */ IC_EVEX_OPSIZE_KZ_B, /* 12657 */ IC_EVEX_OPSIZE_KZ_B, /* 12658 */ IC_EVEX_OPSIZE_KZ_B, /* 12659 */ IC_EVEX_OPSIZE_KZ_B, /* 12660 */ IC_EVEX_OPSIZE_KZ_B, /* 12661 */ IC_EVEX_OPSIZE_KZ_B, /* 12662 */ IC_EVEX_OPSIZE_KZ_B, /* 12663 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12664 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12665 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12666 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12667 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12668 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12669 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12670 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12671 */ IC_EVEX_KZ_B, /* 12672 */ IC_EVEX_KZ_B, /* 12673 */ IC_EVEX_XS_KZ_B, /* 12674 */ IC_EVEX_XS_KZ_B, /* 12675 */ IC_EVEX_XD_KZ_B, /* 12676 */ IC_EVEX_XD_KZ_B, /* 12677 */ IC_EVEX_XD_KZ_B, /* 12678 */ IC_EVEX_XD_KZ_B, /* 12679 */ IC_EVEX_W_KZ_B, /* 12680 */ IC_EVEX_W_KZ_B, /* 12681 */ IC_EVEX_W_XS_KZ_B, /* 12682 */ IC_EVEX_W_XS_KZ_B, /* 12683 */ IC_EVEX_W_XD_KZ_B, /* 12684 */ IC_EVEX_W_XD_KZ_B, /* 12685 */ IC_EVEX_W_XD_KZ_B, /* 12686 */ IC_EVEX_W_XD_KZ_B, /* 12687 */ IC_EVEX_OPSIZE_KZ_B, /* 12688 */ IC_EVEX_OPSIZE_KZ_B, /* 12689 */ IC_EVEX_OPSIZE_KZ_B, /* 12690 */ IC_EVEX_OPSIZE_KZ_B, /* 12691 */ IC_EVEX_OPSIZE_KZ_B, /* 12692 */ IC_EVEX_OPSIZE_KZ_B, /* 12693 */ IC_EVEX_OPSIZE_KZ_B, /* 12694 */ IC_EVEX_OPSIZE_KZ_B, /* 12695 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12696 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12697 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12698 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12699 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12700 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12701 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12702 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12703 */ IC_EVEX_KZ_B, /* 12704 */ IC_EVEX_KZ_B, /* 12705 */ IC_EVEX_XS_KZ_B, /* 12706 */ IC_EVEX_XS_KZ_B, /* 12707 */ IC_EVEX_XD_KZ_B, /* 12708 */ IC_EVEX_XD_KZ_B, /* 12709 */ IC_EVEX_XD_KZ_B, /* 12710 */ IC_EVEX_XD_KZ_B, /* 12711 */ IC_EVEX_W_KZ_B, /* 12712 */ IC_EVEX_W_KZ_B, /* 12713 */ IC_EVEX_W_XS_KZ_B, /* 12714 */ IC_EVEX_W_XS_KZ_B, /* 12715 */ IC_EVEX_W_XD_KZ_B, /* 12716 */ IC_EVEX_W_XD_KZ_B, /* 12717 */ IC_EVEX_W_XD_KZ_B, /* 12718 */ IC_EVEX_W_XD_KZ_B, /* 12719 */ IC_EVEX_OPSIZE_KZ_B, /* 12720 */ IC_EVEX_OPSIZE_KZ_B, /* 12721 */ IC_EVEX_OPSIZE_KZ_B, /* 12722 */ IC_EVEX_OPSIZE_KZ_B, /* 12723 */ IC_EVEX_OPSIZE_KZ_B, /* 12724 */ IC_EVEX_OPSIZE_KZ_B, /* 12725 */ IC_EVEX_OPSIZE_KZ_B, /* 12726 */ IC_EVEX_OPSIZE_KZ_B, /* 12727 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12728 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12729 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12730 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12731 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12732 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12733 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12734 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12735 */ IC_EVEX_KZ_B, /* 12736 */ IC_EVEX_KZ_B, /* 12737 */ IC_EVEX_XS_KZ_B, /* 12738 */ IC_EVEX_XS_KZ_B, /* 12739 */ IC_EVEX_XD_KZ_B, /* 12740 */ IC_EVEX_XD_KZ_B, /* 12741 */ IC_EVEX_XD_KZ_B, /* 12742 */ IC_EVEX_XD_KZ_B, /* 12743 */ IC_EVEX_W_KZ_B, /* 12744 */ IC_EVEX_W_KZ_B, /* 12745 */ IC_EVEX_W_XS_KZ_B, /* 12746 */ IC_EVEX_W_XS_KZ_B, /* 12747 */ IC_EVEX_W_XD_KZ_B, /* 12748 */ IC_EVEX_W_XD_KZ_B, /* 12749 */ IC_EVEX_W_XD_KZ_B, /* 12750 */ IC_EVEX_W_XD_KZ_B, /* 12751 */ IC_EVEX_OPSIZE_KZ_B, /* 12752 */ IC_EVEX_OPSIZE_KZ_B, /* 12753 */ IC_EVEX_OPSIZE_KZ_B, /* 12754 */ IC_EVEX_OPSIZE_KZ_B, /* 12755 */ IC_EVEX_OPSIZE_KZ_B, /* 12756 */ IC_EVEX_OPSIZE_KZ_B, /* 12757 */ IC_EVEX_OPSIZE_KZ_B, /* 12758 */ IC_EVEX_OPSIZE_KZ_B, /* 12759 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12760 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12761 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12762 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12763 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12764 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12765 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12766 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12767 */ IC_EVEX_KZ_B, /* 12768 */ IC_EVEX_KZ_B, /* 12769 */ IC_EVEX_XS_KZ_B, /* 12770 */ IC_EVEX_XS_KZ_B, /* 12771 */ IC_EVEX_XD_KZ_B, /* 12772 */ IC_EVEX_XD_KZ_B, /* 12773 */ IC_EVEX_XD_KZ_B, /* 12774 */ IC_EVEX_XD_KZ_B, /* 12775 */ IC_EVEX_W_KZ_B, /* 12776 */ IC_EVEX_W_KZ_B, /* 12777 */ IC_EVEX_W_XS_KZ_B, /* 12778 */ IC_EVEX_W_XS_KZ_B, /* 12779 */ IC_EVEX_W_XD_KZ_B, /* 12780 */ IC_EVEX_W_XD_KZ_B, /* 12781 */ IC_EVEX_W_XD_KZ_B, /* 12782 */ IC_EVEX_W_XD_KZ_B, /* 12783 */ IC_EVEX_OPSIZE_KZ_B, /* 12784 */ IC_EVEX_OPSIZE_KZ_B, /* 12785 */ IC_EVEX_OPSIZE_KZ_B, /* 12786 */ IC_EVEX_OPSIZE_KZ_B, /* 12787 */ IC_EVEX_OPSIZE_KZ_B, /* 12788 */ IC_EVEX_OPSIZE_KZ_B, /* 12789 */ IC_EVEX_OPSIZE_KZ_B, /* 12790 */ IC_EVEX_OPSIZE_KZ_B, /* 12791 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12792 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12793 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12794 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12795 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12796 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12797 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12798 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12799 */ IC, /* 12800 */ IC_64BIT, /* 12801 */ IC_XS, /* 12802 */ IC_64BIT_XS, /* 12803 */ IC_XD, /* 12804 */ IC_64BIT_XD, /* 12805 */ IC_XS, /* 12806 */ IC_64BIT_XS, /* 12807 */ IC, /* 12808 */ IC_64BIT_REXW, /* 12809 */ IC_XS, /* 12810 */ IC_64BIT_REXW_XS, /* 12811 */ IC_XD, /* 12812 */ IC_64BIT_REXW_XD, /* 12813 */ IC_XS, /* 12814 */ IC_64BIT_REXW_XS, /* 12815 */ IC_OPSIZE, /* 12816 */ IC_64BIT_OPSIZE, /* 12817 */ IC_XS_OPSIZE, /* 12818 */ IC_64BIT_XS_OPSIZE, /* 12819 */ IC_XD_OPSIZE, /* 12820 */ IC_64BIT_XD_OPSIZE, /* 12821 */ IC_XS_OPSIZE, /* 12822 */ IC_64BIT_XD_OPSIZE, /* 12823 */ IC_OPSIZE, /* 12824 */ IC_64BIT_REXW_OPSIZE, /* 12825 */ IC_XS_OPSIZE, /* 12826 */ IC_64BIT_REXW_XS, /* 12827 */ IC_XD_OPSIZE, /* 12828 */ IC_64BIT_REXW_XD, /* 12829 */ IC_XS_OPSIZE, /* 12830 */ IC_64BIT_REXW_XS, /* 12831 */ IC_ADSIZE, /* 12832 */ IC_64BIT_ADSIZE, /* 12833 */ IC_XS_ADSIZE, /* 12834 */ IC_64BIT_XS_ADSIZE, /* 12835 */ IC_XD_ADSIZE, /* 12836 */ IC_64BIT_XD_ADSIZE, /* 12837 */ IC_XS_ADSIZE, /* 12838 */ IC_64BIT_XD_ADSIZE, /* 12839 */ IC_ADSIZE, /* 12840 */ IC_64BIT_REXW_ADSIZE, /* 12841 */ IC_XS_ADSIZE, /* 12842 */ IC_64BIT_REXW_XS, /* 12843 */ IC_XD_ADSIZE, /* 12844 */ IC_64BIT_REXW_XD, /* 12845 */ IC_XS_ADSIZE, /* 12846 */ IC_64BIT_REXW_XS, /* 12847 */ IC_OPSIZE_ADSIZE, /* 12848 */ IC_64BIT_OPSIZE_ADSIZE, /* 12849 */ IC_XS_OPSIZE, /* 12850 */ IC_64BIT_XS_OPSIZE, /* 12851 */ IC_XD_OPSIZE, /* 12852 */ IC_64BIT_XD_OPSIZE, /* 12853 */ IC_XS_OPSIZE, /* 12854 */ IC_64BIT_XD_OPSIZE, /* 12855 */ IC_OPSIZE_ADSIZE, /* 12856 */ IC_64BIT_REXW_OPSIZE, /* 12857 */ IC_XS_OPSIZE, /* 12858 */ IC_64BIT_REXW_XS, /* 12859 */ IC_XD_OPSIZE, /* 12860 */ IC_64BIT_REXW_XD, /* 12861 */ IC_XS_OPSIZE, /* 12862 */ IC_64BIT_REXW_XS, /* 12863 */ IC_VEX, /* 12864 */ IC_VEX, /* 12865 */ IC_VEX_XS, /* 12866 */ IC_VEX_XS, /* 12867 */ IC_VEX_XD, /* 12868 */ IC_VEX_XD, /* 12869 */ IC_VEX_XD, /* 12870 */ IC_VEX_XD, /* 12871 */ IC_VEX_W, /* 12872 */ IC_VEX_W, /* 12873 */ IC_VEX_W_XS, /* 12874 */ IC_VEX_W_XS, /* 12875 */ IC_VEX_W_XD, /* 12876 */ IC_VEX_W_XD, /* 12877 */ IC_VEX_W_XD, /* 12878 */ IC_VEX_W_XD, /* 12879 */ IC_VEX_OPSIZE, /* 12880 */ IC_VEX_OPSIZE, /* 12881 */ IC_VEX_OPSIZE, /* 12882 */ IC_VEX_OPSIZE, /* 12883 */ IC_VEX_OPSIZE, /* 12884 */ IC_VEX_OPSIZE, /* 12885 */ IC_VEX_OPSIZE, /* 12886 */ IC_VEX_OPSIZE, /* 12887 */ IC_VEX_W_OPSIZE, /* 12888 */ IC_VEX_W_OPSIZE, /* 12889 */ IC_VEX_W_OPSIZE, /* 12890 */ IC_VEX_W_OPSIZE, /* 12891 */ IC_VEX_W_OPSIZE, /* 12892 */ IC_VEX_W_OPSIZE, /* 12893 */ IC_VEX_W_OPSIZE, /* 12894 */ IC_VEX_W_OPSIZE, /* 12895 */ IC_VEX, /* 12896 */ IC_VEX, /* 12897 */ IC_VEX_XS, /* 12898 */ IC_VEX_XS, /* 12899 */ IC_VEX_XD, /* 12900 */ IC_VEX_XD, /* 12901 */ IC_VEX_XD, /* 12902 */ IC_VEX_XD, /* 12903 */ IC_VEX_W, /* 12904 */ IC_VEX_W, /* 12905 */ IC_VEX_W_XS, /* 12906 */ IC_VEX_W_XS, /* 12907 */ IC_VEX_W_XD, /* 12908 */ IC_VEX_W_XD, /* 12909 */ IC_VEX_W_XD, /* 12910 */ IC_VEX_W_XD, /* 12911 */ IC_VEX_OPSIZE, /* 12912 */ IC_VEX_OPSIZE, /* 12913 */ IC_VEX_OPSIZE, /* 12914 */ IC_VEX_OPSIZE, /* 12915 */ IC_VEX_OPSIZE, /* 12916 */ IC_VEX_OPSIZE, /* 12917 */ IC_VEX_OPSIZE, /* 12918 */ IC_VEX_OPSIZE, /* 12919 */ IC_VEX_W_OPSIZE, /* 12920 */ IC_VEX_W_OPSIZE, /* 12921 */ IC_VEX_W_OPSIZE, /* 12922 */ IC_VEX_W_OPSIZE, /* 12923 */ IC_VEX_W_OPSIZE, /* 12924 */ IC_VEX_W_OPSIZE, /* 12925 */ IC_VEX_W_OPSIZE, /* 12926 */ IC_VEX_W_OPSIZE, /* 12927 */ IC_VEX_L, /* 12928 */ IC_VEX_L, /* 12929 */ IC_VEX_L_XS, /* 12930 */ IC_VEX_L_XS, /* 12931 */ IC_VEX_L_XD, /* 12932 */ IC_VEX_L_XD, /* 12933 */ IC_VEX_L_XD, /* 12934 */ IC_VEX_L_XD, /* 12935 */ IC_VEX_L_W, /* 12936 */ IC_VEX_L_W, /* 12937 */ IC_VEX_L_W_XS, /* 12938 */ IC_VEX_L_W_XS, /* 12939 */ IC_VEX_L_W_XD, /* 12940 */ IC_VEX_L_W_XD, /* 12941 */ IC_VEX_L_W_XD, /* 12942 */ IC_VEX_L_W_XD, /* 12943 */ IC_VEX_L_OPSIZE, /* 12944 */ IC_VEX_L_OPSIZE, /* 12945 */ IC_VEX_L_OPSIZE, /* 12946 */ IC_VEX_L_OPSIZE, /* 12947 */ IC_VEX_L_OPSIZE, /* 12948 */ IC_VEX_L_OPSIZE, /* 12949 */ IC_VEX_L_OPSIZE, /* 12950 */ IC_VEX_L_OPSIZE, /* 12951 */ IC_VEX_L_W_OPSIZE, /* 12952 */ IC_VEX_L_W_OPSIZE, /* 12953 */ IC_VEX_L_W_OPSIZE, /* 12954 */ IC_VEX_L_W_OPSIZE, /* 12955 */ IC_VEX_L_W_OPSIZE, /* 12956 */ IC_VEX_L_W_OPSIZE, /* 12957 */ IC_VEX_L_W_OPSIZE, /* 12958 */ IC_VEX_L_W_OPSIZE, /* 12959 */ IC_VEX_L, /* 12960 */ IC_VEX_L, /* 12961 */ IC_VEX_L_XS, /* 12962 */ IC_VEX_L_XS, /* 12963 */ IC_VEX_L_XD, /* 12964 */ IC_VEX_L_XD, /* 12965 */ IC_VEX_L_XD, /* 12966 */ IC_VEX_L_XD, /* 12967 */ IC_VEX_L_W, /* 12968 */ IC_VEX_L_W, /* 12969 */ IC_VEX_L_W_XS, /* 12970 */ IC_VEX_L_W_XS, /* 12971 */ IC_VEX_L_W_XD, /* 12972 */ IC_VEX_L_W_XD, /* 12973 */ IC_VEX_L_W_XD, /* 12974 */ IC_VEX_L_W_XD, /* 12975 */ IC_VEX_L_OPSIZE, /* 12976 */ IC_VEX_L_OPSIZE, /* 12977 */ IC_VEX_L_OPSIZE, /* 12978 */ IC_VEX_L_OPSIZE, /* 12979 */ IC_VEX_L_OPSIZE, /* 12980 */ IC_VEX_L_OPSIZE, /* 12981 */ IC_VEX_L_OPSIZE, /* 12982 */ IC_VEX_L_OPSIZE, /* 12983 */ IC_VEX_L_W_OPSIZE, /* 12984 */ IC_VEX_L_W_OPSIZE, /* 12985 */ IC_VEX_L_W_OPSIZE, /* 12986 */ IC_VEX_L_W_OPSIZE, /* 12987 */ IC_VEX_L_W_OPSIZE, /* 12988 */ IC_VEX_L_W_OPSIZE, /* 12989 */ IC_VEX_L_W_OPSIZE, /* 12990 */ IC_VEX_L_W_OPSIZE, /* 12991 */ IC_VEX_L, /* 12992 */ IC_VEX_L, /* 12993 */ IC_VEX_L_XS, /* 12994 */ IC_VEX_L_XS, /* 12995 */ IC_VEX_L_XD, /* 12996 */ IC_VEX_L_XD, /* 12997 */ IC_VEX_L_XD, /* 12998 */ IC_VEX_L_XD, /* 12999 */ IC_VEX_L_W, /* 13000 */ IC_VEX_L_W, /* 13001 */ IC_VEX_L_W_XS, /* 13002 */ IC_VEX_L_W_XS, /* 13003 */ IC_VEX_L_W_XD, /* 13004 */ IC_VEX_L_W_XD, /* 13005 */ IC_VEX_L_W_XD, /* 13006 */ IC_VEX_L_W_XD, /* 13007 */ IC_VEX_L_OPSIZE, /* 13008 */ IC_VEX_L_OPSIZE, /* 13009 */ IC_VEX_L_OPSIZE, /* 13010 */ IC_VEX_L_OPSIZE, /* 13011 */ IC_VEX_L_OPSIZE, /* 13012 */ IC_VEX_L_OPSIZE, /* 13013 */ IC_VEX_L_OPSIZE, /* 13014 */ IC_VEX_L_OPSIZE, /* 13015 */ IC_VEX_L_W_OPSIZE, /* 13016 */ IC_VEX_L_W_OPSIZE, /* 13017 */ IC_VEX_L_W_OPSIZE, /* 13018 */ IC_VEX_L_W_OPSIZE, /* 13019 */ IC_VEX_L_W_OPSIZE, /* 13020 */ IC_VEX_L_W_OPSIZE, /* 13021 */ IC_VEX_L_W_OPSIZE, /* 13022 */ IC_VEX_L_W_OPSIZE, /* 13023 */ IC_VEX_L, /* 13024 */ IC_VEX_L, /* 13025 */ IC_VEX_L_XS, /* 13026 */ IC_VEX_L_XS, /* 13027 */ IC_VEX_L_XD, /* 13028 */ IC_VEX_L_XD, /* 13029 */ IC_VEX_L_XD, /* 13030 */ IC_VEX_L_XD, /* 13031 */ IC_VEX_L_W, /* 13032 */ IC_VEX_L_W, /* 13033 */ IC_VEX_L_W_XS, /* 13034 */ IC_VEX_L_W_XS, /* 13035 */ IC_VEX_L_W_XD, /* 13036 */ IC_VEX_L_W_XD, /* 13037 */ IC_VEX_L_W_XD, /* 13038 */ IC_VEX_L_W_XD, /* 13039 */ IC_VEX_L_OPSIZE, /* 13040 */ IC_VEX_L_OPSIZE, /* 13041 */ IC_VEX_L_OPSIZE, /* 13042 */ IC_VEX_L_OPSIZE, /* 13043 */ IC_VEX_L_OPSIZE, /* 13044 */ IC_VEX_L_OPSIZE, /* 13045 */ IC_VEX_L_OPSIZE, /* 13046 */ IC_VEX_L_OPSIZE, /* 13047 */ IC_VEX_L_W_OPSIZE, /* 13048 */ IC_VEX_L_W_OPSIZE, /* 13049 */ IC_VEX_L_W_OPSIZE, /* 13050 */ IC_VEX_L_W_OPSIZE, /* 13051 */ IC_VEX_L_W_OPSIZE, /* 13052 */ IC_VEX_L_W_OPSIZE, /* 13053 */ IC_VEX_L_W_OPSIZE, /* 13054 */ IC_VEX_L_W_OPSIZE, /* 13055 */ IC_EVEX_L_KZ_B, /* 13056 */ IC_EVEX_L_KZ_B, /* 13057 */ IC_EVEX_L_XS_KZ_B, /* 13058 */ IC_EVEX_L_XS_KZ_B, /* 13059 */ IC_EVEX_L_XD_KZ_B, /* 13060 */ IC_EVEX_L_XD_KZ_B, /* 13061 */ IC_EVEX_L_XD_KZ_B, /* 13062 */ IC_EVEX_L_XD_KZ_B, /* 13063 */ IC_EVEX_L_W_KZ_B, /* 13064 */ IC_EVEX_L_W_KZ_B, /* 13065 */ IC_EVEX_L_W_XS_KZ_B, /* 13066 */ IC_EVEX_L_W_XS_KZ_B, /* 13067 */ IC_EVEX_L_W_XD_KZ_B, /* 13068 */ IC_EVEX_L_W_XD_KZ_B, /* 13069 */ IC_EVEX_L_W_XD_KZ_B, /* 13070 */ IC_EVEX_L_W_XD_KZ_B, /* 13071 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13072 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13073 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13074 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13075 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13076 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13077 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13078 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13079 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13080 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13081 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13082 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13083 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13084 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13085 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13086 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13087 */ IC_EVEX_L_KZ_B, /* 13088 */ IC_EVEX_L_KZ_B, /* 13089 */ IC_EVEX_L_XS_KZ_B, /* 13090 */ IC_EVEX_L_XS_KZ_B, /* 13091 */ IC_EVEX_L_XD_KZ_B, /* 13092 */ IC_EVEX_L_XD_KZ_B, /* 13093 */ IC_EVEX_L_XD_KZ_B, /* 13094 */ IC_EVEX_L_XD_KZ_B, /* 13095 */ IC_EVEX_L_W_KZ_B, /* 13096 */ IC_EVEX_L_W_KZ_B, /* 13097 */ IC_EVEX_L_W_XS_KZ_B, /* 13098 */ IC_EVEX_L_W_XS_KZ_B, /* 13099 */ IC_EVEX_L_W_XD_KZ_B, /* 13100 */ IC_EVEX_L_W_XD_KZ_B, /* 13101 */ IC_EVEX_L_W_XD_KZ_B, /* 13102 */ IC_EVEX_L_W_XD_KZ_B, /* 13103 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13104 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13105 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13106 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13107 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13108 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13109 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13110 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13111 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13112 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13113 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13114 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13115 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13116 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13117 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13118 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13119 */ IC_EVEX_L_KZ_B, /* 13120 */ IC_EVEX_L_KZ_B, /* 13121 */ IC_EVEX_L_XS_KZ_B, /* 13122 */ IC_EVEX_L_XS_KZ_B, /* 13123 */ IC_EVEX_L_XD_KZ_B, /* 13124 */ IC_EVEX_L_XD_KZ_B, /* 13125 */ IC_EVEX_L_XD_KZ_B, /* 13126 */ IC_EVEX_L_XD_KZ_B, /* 13127 */ IC_EVEX_L_W_KZ_B, /* 13128 */ IC_EVEX_L_W_KZ_B, /* 13129 */ IC_EVEX_L_W_XS_KZ_B, /* 13130 */ IC_EVEX_L_W_XS_KZ_B, /* 13131 */ IC_EVEX_L_W_XD_KZ_B, /* 13132 */ IC_EVEX_L_W_XD_KZ_B, /* 13133 */ IC_EVEX_L_W_XD_KZ_B, /* 13134 */ IC_EVEX_L_W_XD_KZ_B, /* 13135 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13136 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13137 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13138 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13139 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13140 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13141 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13142 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13143 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13144 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13145 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13146 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13147 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13148 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13149 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13150 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13151 */ IC_EVEX_L_KZ_B, /* 13152 */ IC_EVEX_L_KZ_B, /* 13153 */ IC_EVEX_L_XS_KZ_B, /* 13154 */ IC_EVEX_L_XS_KZ_B, /* 13155 */ IC_EVEX_L_XD_KZ_B, /* 13156 */ IC_EVEX_L_XD_KZ_B, /* 13157 */ IC_EVEX_L_XD_KZ_B, /* 13158 */ IC_EVEX_L_XD_KZ_B, /* 13159 */ IC_EVEX_L_W_KZ_B, /* 13160 */ IC_EVEX_L_W_KZ_B, /* 13161 */ IC_EVEX_L_W_XS_KZ_B, /* 13162 */ IC_EVEX_L_W_XS_KZ_B, /* 13163 */ IC_EVEX_L_W_XD_KZ_B, /* 13164 */ IC_EVEX_L_W_XD_KZ_B, /* 13165 */ IC_EVEX_L_W_XD_KZ_B, /* 13166 */ IC_EVEX_L_W_XD_KZ_B, /* 13167 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13168 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13169 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13170 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13171 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13172 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13173 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13174 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13175 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13176 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13177 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13178 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13179 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13180 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13181 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13182 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13183 */ IC_EVEX_L_KZ_B, /* 13184 */ IC_EVEX_L_KZ_B, /* 13185 */ IC_EVEX_L_XS_KZ_B, /* 13186 */ IC_EVEX_L_XS_KZ_B, /* 13187 */ IC_EVEX_L_XD_KZ_B, /* 13188 */ IC_EVEX_L_XD_KZ_B, /* 13189 */ IC_EVEX_L_XD_KZ_B, /* 13190 */ IC_EVEX_L_XD_KZ_B, /* 13191 */ IC_EVEX_L_W_KZ_B, /* 13192 */ IC_EVEX_L_W_KZ_B, /* 13193 */ IC_EVEX_L_W_XS_KZ_B, /* 13194 */ IC_EVEX_L_W_XS_KZ_B, /* 13195 */ IC_EVEX_L_W_XD_KZ_B, /* 13196 */ IC_EVEX_L_W_XD_KZ_B, /* 13197 */ IC_EVEX_L_W_XD_KZ_B, /* 13198 */ IC_EVEX_L_W_XD_KZ_B, /* 13199 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13200 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13201 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13202 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13203 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13204 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13205 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13206 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13207 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13208 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13209 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13210 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13211 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13212 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13213 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13214 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13215 */ IC_EVEX_L_KZ_B, /* 13216 */ IC_EVEX_L_KZ_B, /* 13217 */ IC_EVEX_L_XS_KZ_B, /* 13218 */ IC_EVEX_L_XS_KZ_B, /* 13219 */ IC_EVEX_L_XD_KZ_B, /* 13220 */ IC_EVEX_L_XD_KZ_B, /* 13221 */ IC_EVEX_L_XD_KZ_B, /* 13222 */ IC_EVEX_L_XD_KZ_B, /* 13223 */ IC_EVEX_L_W_KZ_B, /* 13224 */ IC_EVEX_L_W_KZ_B, /* 13225 */ IC_EVEX_L_W_XS_KZ_B, /* 13226 */ IC_EVEX_L_W_XS_KZ_B, /* 13227 */ IC_EVEX_L_W_XD_KZ_B, /* 13228 */ IC_EVEX_L_W_XD_KZ_B, /* 13229 */ IC_EVEX_L_W_XD_KZ_B, /* 13230 */ IC_EVEX_L_W_XD_KZ_B, /* 13231 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13232 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13233 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13234 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13235 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13236 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13237 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13238 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13239 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13240 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13241 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13242 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13243 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13244 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13245 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13246 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13247 */ IC_EVEX_L_KZ_B, /* 13248 */ IC_EVEX_L_KZ_B, /* 13249 */ IC_EVEX_L_XS_KZ_B, /* 13250 */ IC_EVEX_L_XS_KZ_B, /* 13251 */ IC_EVEX_L_XD_KZ_B, /* 13252 */ IC_EVEX_L_XD_KZ_B, /* 13253 */ IC_EVEX_L_XD_KZ_B, /* 13254 */ IC_EVEX_L_XD_KZ_B, /* 13255 */ IC_EVEX_L_W_KZ_B, /* 13256 */ IC_EVEX_L_W_KZ_B, /* 13257 */ IC_EVEX_L_W_XS_KZ_B, /* 13258 */ IC_EVEX_L_W_XS_KZ_B, /* 13259 */ IC_EVEX_L_W_XD_KZ_B, /* 13260 */ IC_EVEX_L_W_XD_KZ_B, /* 13261 */ IC_EVEX_L_W_XD_KZ_B, /* 13262 */ IC_EVEX_L_W_XD_KZ_B, /* 13263 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13264 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13265 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13266 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13267 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13268 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13269 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13270 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13271 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13272 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13273 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13274 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13275 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13276 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13277 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13278 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13279 */ IC_EVEX_L_KZ_B, /* 13280 */ IC_EVEX_L_KZ_B, /* 13281 */ IC_EVEX_L_XS_KZ_B, /* 13282 */ IC_EVEX_L_XS_KZ_B, /* 13283 */ IC_EVEX_L_XD_KZ_B, /* 13284 */ IC_EVEX_L_XD_KZ_B, /* 13285 */ IC_EVEX_L_XD_KZ_B, /* 13286 */ IC_EVEX_L_XD_KZ_B, /* 13287 */ IC_EVEX_L_W_KZ_B, /* 13288 */ IC_EVEX_L_W_KZ_B, /* 13289 */ IC_EVEX_L_W_XS_KZ_B, /* 13290 */ IC_EVEX_L_W_XS_KZ_B, /* 13291 */ IC_EVEX_L_W_XD_KZ_B, /* 13292 */ IC_EVEX_L_W_XD_KZ_B, /* 13293 */ IC_EVEX_L_W_XD_KZ_B, /* 13294 */ IC_EVEX_L_W_XD_KZ_B, /* 13295 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13296 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13297 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13298 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13299 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13300 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13301 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13302 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13303 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13304 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13305 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13306 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13307 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13308 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13309 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13310 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13311 */ IC, /* 13312 */ IC_64BIT, /* 13313 */ IC_XS, /* 13314 */ IC_64BIT_XS, /* 13315 */ IC_XD, /* 13316 */ IC_64BIT_XD, /* 13317 */ IC_XS, /* 13318 */ IC_64BIT_XS, /* 13319 */ IC, /* 13320 */ IC_64BIT_REXW, /* 13321 */ IC_XS, /* 13322 */ IC_64BIT_REXW_XS, /* 13323 */ IC_XD, /* 13324 */ IC_64BIT_REXW_XD, /* 13325 */ IC_XS, /* 13326 */ IC_64BIT_REXW_XS, /* 13327 */ IC_OPSIZE, /* 13328 */ IC_64BIT_OPSIZE, /* 13329 */ IC_XS_OPSIZE, /* 13330 */ IC_64BIT_XS_OPSIZE, /* 13331 */ IC_XD_OPSIZE, /* 13332 */ IC_64BIT_XD_OPSIZE, /* 13333 */ IC_XS_OPSIZE, /* 13334 */ IC_64BIT_XD_OPSIZE, /* 13335 */ IC_OPSIZE, /* 13336 */ IC_64BIT_REXW_OPSIZE, /* 13337 */ IC_XS_OPSIZE, /* 13338 */ IC_64BIT_REXW_XS, /* 13339 */ IC_XD_OPSIZE, /* 13340 */ IC_64BIT_REXW_XD, /* 13341 */ IC_XS_OPSIZE, /* 13342 */ IC_64BIT_REXW_XS, /* 13343 */ IC_ADSIZE, /* 13344 */ IC_64BIT_ADSIZE, /* 13345 */ IC_XS_ADSIZE, /* 13346 */ IC_64BIT_XS_ADSIZE, /* 13347 */ IC_XD_ADSIZE, /* 13348 */ IC_64BIT_XD_ADSIZE, /* 13349 */ IC_XS_ADSIZE, /* 13350 */ IC_64BIT_XD_ADSIZE, /* 13351 */ IC_ADSIZE, /* 13352 */ IC_64BIT_REXW_ADSIZE, /* 13353 */ IC_XS_ADSIZE, /* 13354 */ IC_64BIT_REXW_XS, /* 13355 */ IC_XD_ADSIZE, /* 13356 */ IC_64BIT_REXW_XD, /* 13357 */ IC_XS_ADSIZE, /* 13358 */ IC_64BIT_REXW_XS, /* 13359 */ IC_OPSIZE_ADSIZE, /* 13360 */ IC_64BIT_OPSIZE_ADSIZE, /* 13361 */ IC_XS_OPSIZE, /* 13362 */ IC_64BIT_XS_OPSIZE, /* 13363 */ IC_XD_OPSIZE, /* 13364 */ IC_64BIT_XD_OPSIZE, /* 13365 */ IC_XS_OPSIZE, /* 13366 */ IC_64BIT_XD_OPSIZE, /* 13367 */ IC_OPSIZE_ADSIZE, /* 13368 */ IC_64BIT_REXW_OPSIZE, /* 13369 */ IC_XS_OPSIZE, /* 13370 */ IC_64BIT_REXW_XS, /* 13371 */ IC_XD_OPSIZE, /* 13372 */ IC_64BIT_REXW_XD, /* 13373 */ IC_XS_OPSIZE, /* 13374 */ IC_64BIT_REXW_XS, /* 13375 */ IC_VEX, /* 13376 */ IC_VEX, /* 13377 */ IC_VEX_XS, /* 13378 */ IC_VEX_XS, /* 13379 */ IC_VEX_XD, /* 13380 */ IC_VEX_XD, /* 13381 */ IC_VEX_XD, /* 13382 */ IC_VEX_XD, /* 13383 */ IC_VEX_W, /* 13384 */ IC_VEX_W, /* 13385 */ IC_VEX_W_XS, /* 13386 */ IC_VEX_W_XS, /* 13387 */ IC_VEX_W_XD, /* 13388 */ IC_VEX_W_XD, /* 13389 */ IC_VEX_W_XD, /* 13390 */ IC_VEX_W_XD, /* 13391 */ IC_VEX_OPSIZE, /* 13392 */ IC_VEX_OPSIZE, /* 13393 */ IC_VEX_OPSIZE, /* 13394 */ IC_VEX_OPSIZE, /* 13395 */ IC_VEX_OPSIZE, /* 13396 */ IC_VEX_OPSIZE, /* 13397 */ IC_VEX_OPSIZE, /* 13398 */ IC_VEX_OPSIZE, /* 13399 */ IC_VEX_W_OPSIZE, /* 13400 */ IC_VEX_W_OPSIZE, /* 13401 */ IC_VEX_W_OPSIZE, /* 13402 */ IC_VEX_W_OPSIZE, /* 13403 */ IC_VEX_W_OPSIZE, /* 13404 */ IC_VEX_W_OPSIZE, /* 13405 */ IC_VEX_W_OPSIZE, /* 13406 */ IC_VEX_W_OPSIZE, /* 13407 */ IC_VEX, /* 13408 */ IC_VEX, /* 13409 */ IC_VEX_XS, /* 13410 */ IC_VEX_XS, /* 13411 */ IC_VEX_XD, /* 13412 */ IC_VEX_XD, /* 13413 */ IC_VEX_XD, /* 13414 */ IC_VEX_XD, /* 13415 */ IC_VEX_W, /* 13416 */ IC_VEX_W, /* 13417 */ IC_VEX_W_XS, /* 13418 */ IC_VEX_W_XS, /* 13419 */ IC_VEX_W_XD, /* 13420 */ IC_VEX_W_XD, /* 13421 */ IC_VEX_W_XD, /* 13422 */ IC_VEX_W_XD, /* 13423 */ IC_VEX_OPSIZE, /* 13424 */ IC_VEX_OPSIZE, /* 13425 */ IC_VEX_OPSIZE, /* 13426 */ IC_VEX_OPSIZE, /* 13427 */ IC_VEX_OPSIZE, /* 13428 */ IC_VEX_OPSIZE, /* 13429 */ IC_VEX_OPSIZE, /* 13430 */ IC_VEX_OPSIZE, /* 13431 */ IC_VEX_W_OPSIZE, /* 13432 */ IC_VEX_W_OPSIZE, /* 13433 */ IC_VEX_W_OPSIZE, /* 13434 */ IC_VEX_W_OPSIZE, /* 13435 */ IC_VEX_W_OPSIZE, /* 13436 */ IC_VEX_W_OPSIZE, /* 13437 */ IC_VEX_W_OPSIZE, /* 13438 */ IC_VEX_W_OPSIZE, /* 13439 */ IC_VEX_L, /* 13440 */ IC_VEX_L, /* 13441 */ IC_VEX_L_XS, /* 13442 */ IC_VEX_L_XS, /* 13443 */ IC_VEX_L_XD, /* 13444 */ IC_VEX_L_XD, /* 13445 */ IC_VEX_L_XD, /* 13446 */ IC_VEX_L_XD, /* 13447 */ IC_VEX_L_W, /* 13448 */ IC_VEX_L_W, /* 13449 */ IC_VEX_L_W_XS, /* 13450 */ IC_VEX_L_W_XS, /* 13451 */ IC_VEX_L_W_XD, /* 13452 */ IC_VEX_L_W_XD, /* 13453 */ IC_VEX_L_W_XD, /* 13454 */ IC_VEX_L_W_XD, /* 13455 */ IC_VEX_L_OPSIZE, /* 13456 */ IC_VEX_L_OPSIZE, /* 13457 */ IC_VEX_L_OPSIZE, /* 13458 */ IC_VEX_L_OPSIZE, /* 13459 */ IC_VEX_L_OPSIZE, /* 13460 */ IC_VEX_L_OPSIZE, /* 13461 */ IC_VEX_L_OPSIZE, /* 13462 */ IC_VEX_L_OPSIZE, /* 13463 */ IC_VEX_L_W_OPSIZE, /* 13464 */ IC_VEX_L_W_OPSIZE, /* 13465 */ IC_VEX_L_W_OPSIZE, /* 13466 */ IC_VEX_L_W_OPSIZE, /* 13467 */ IC_VEX_L_W_OPSIZE, /* 13468 */ IC_VEX_L_W_OPSIZE, /* 13469 */ IC_VEX_L_W_OPSIZE, /* 13470 */ IC_VEX_L_W_OPSIZE, /* 13471 */ IC_VEX_L, /* 13472 */ IC_VEX_L, /* 13473 */ IC_VEX_L_XS, /* 13474 */ IC_VEX_L_XS, /* 13475 */ IC_VEX_L_XD, /* 13476 */ IC_VEX_L_XD, /* 13477 */ IC_VEX_L_XD, /* 13478 */ IC_VEX_L_XD, /* 13479 */ IC_VEX_L_W, /* 13480 */ IC_VEX_L_W, /* 13481 */ IC_VEX_L_W_XS, /* 13482 */ IC_VEX_L_W_XS, /* 13483 */ IC_VEX_L_W_XD, /* 13484 */ IC_VEX_L_W_XD, /* 13485 */ IC_VEX_L_W_XD, /* 13486 */ IC_VEX_L_W_XD, /* 13487 */ IC_VEX_L_OPSIZE, /* 13488 */ IC_VEX_L_OPSIZE, /* 13489 */ IC_VEX_L_OPSIZE, /* 13490 */ IC_VEX_L_OPSIZE, /* 13491 */ IC_VEX_L_OPSIZE, /* 13492 */ IC_VEX_L_OPSIZE, /* 13493 */ IC_VEX_L_OPSIZE, /* 13494 */ IC_VEX_L_OPSIZE, /* 13495 */ IC_VEX_L_W_OPSIZE, /* 13496 */ IC_VEX_L_W_OPSIZE, /* 13497 */ IC_VEX_L_W_OPSIZE, /* 13498 */ IC_VEX_L_W_OPSIZE, /* 13499 */ IC_VEX_L_W_OPSIZE, /* 13500 */ IC_VEX_L_W_OPSIZE, /* 13501 */ IC_VEX_L_W_OPSIZE, /* 13502 */ IC_VEX_L_W_OPSIZE, /* 13503 */ IC_VEX_L, /* 13504 */ IC_VEX_L, /* 13505 */ IC_VEX_L_XS, /* 13506 */ IC_VEX_L_XS, /* 13507 */ IC_VEX_L_XD, /* 13508 */ IC_VEX_L_XD, /* 13509 */ IC_VEX_L_XD, /* 13510 */ IC_VEX_L_XD, /* 13511 */ IC_VEX_L_W, /* 13512 */ IC_VEX_L_W, /* 13513 */ IC_VEX_L_W_XS, /* 13514 */ IC_VEX_L_W_XS, /* 13515 */ IC_VEX_L_W_XD, /* 13516 */ IC_VEX_L_W_XD, /* 13517 */ IC_VEX_L_W_XD, /* 13518 */ IC_VEX_L_W_XD, /* 13519 */ IC_VEX_L_OPSIZE, /* 13520 */ IC_VEX_L_OPSIZE, /* 13521 */ IC_VEX_L_OPSIZE, /* 13522 */ IC_VEX_L_OPSIZE, /* 13523 */ IC_VEX_L_OPSIZE, /* 13524 */ IC_VEX_L_OPSIZE, /* 13525 */ IC_VEX_L_OPSIZE, /* 13526 */ IC_VEX_L_OPSIZE, /* 13527 */ IC_VEX_L_W_OPSIZE, /* 13528 */ IC_VEX_L_W_OPSIZE, /* 13529 */ IC_VEX_L_W_OPSIZE, /* 13530 */ IC_VEX_L_W_OPSIZE, /* 13531 */ IC_VEX_L_W_OPSIZE, /* 13532 */ IC_VEX_L_W_OPSIZE, /* 13533 */ IC_VEX_L_W_OPSIZE, /* 13534 */ IC_VEX_L_W_OPSIZE, /* 13535 */ IC_VEX_L, /* 13536 */ IC_VEX_L, /* 13537 */ IC_VEX_L_XS, /* 13538 */ IC_VEX_L_XS, /* 13539 */ IC_VEX_L_XD, /* 13540 */ IC_VEX_L_XD, /* 13541 */ IC_VEX_L_XD, /* 13542 */ IC_VEX_L_XD, /* 13543 */ IC_VEX_L_W, /* 13544 */ IC_VEX_L_W, /* 13545 */ IC_VEX_L_W_XS, /* 13546 */ IC_VEX_L_W_XS, /* 13547 */ IC_VEX_L_W_XD, /* 13548 */ IC_VEX_L_W_XD, /* 13549 */ IC_VEX_L_W_XD, /* 13550 */ IC_VEX_L_W_XD, /* 13551 */ IC_VEX_L_OPSIZE, /* 13552 */ IC_VEX_L_OPSIZE, /* 13553 */ IC_VEX_L_OPSIZE, /* 13554 */ IC_VEX_L_OPSIZE, /* 13555 */ IC_VEX_L_OPSIZE, /* 13556 */ IC_VEX_L_OPSIZE, /* 13557 */ IC_VEX_L_OPSIZE, /* 13558 */ IC_VEX_L_OPSIZE, /* 13559 */ IC_VEX_L_W_OPSIZE, /* 13560 */ IC_VEX_L_W_OPSIZE, /* 13561 */ IC_VEX_L_W_OPSIZE, /* 13562 */ IC_VEX_L_W_OPSIZE, /* 13563 */ IC_VEX_L_W_OPSIZE, /* 13564 */ IC_VEX_L_W_OPSIZE, /* 13565 */ IC_VEX_L_W_OPSIZE, /* 13566 */ IC_VEX_L_W_OPSIZE, /* 13567 */ IC_EVEX_L2_KZ_B, /* 13568 */ IC_EVEX_L2_KZ_B, /* 13569 */ IC_EVEX_L2_XS_KZ_B, /* 13570 */ IC_EVEX_L2_XS_KZ_B, /* 13571 */ IC_EVEX_L2_XD_KZ_B, /* 13572 */ IC_EVEX_L2_XD_KZ_B, /* 13573 */ IC_EVEX_L2_XD_KZ_B, /* 13574 */ IC_EVEX_L2_XD_KZ_B, /* 13575 */ IC_EVEX_L2_W_KZ_B, /* 13576 */ IC_EVEX_L2_W_KZ_B, /* 13577 */ IC_EVEX_L2_W_XS_KZ_B, /* 13578 */ IC_EVEX_L2_W_XS_KZ_B, /* 13579 */ IC_EVEX_L2_W_XD_KZ_B, /* 13580 */ IC_EVEX_L2_W_XD_KZ_B, /* 13581 */ IC_EVEX_L2_W_XD_KZ_B, /* 13582 */ IC_EVEX_L2_W_XD_KZ_B, /* 13583 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13584 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13585 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13586 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13587 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13588 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13589 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13590 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13591 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13592 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13593 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13594 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13595 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13596 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13597 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13598 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13599 */ IC_EVEX_L2_KZ_B, /* 13600 */ IC_EVEX_L2_KZ_B, /* 13601 */ IC_EVEX_L2_XS_KZ_B, /* 13602 */ IC_EVEX_L2_XS_KZ_B, /* 13603 */ IC_EVEX_L2_XD_KZ_B, /* 13604 */ IC_EVEX_L2_XD_KZ_B, /* 13605 */ IC_EVEX_L2_XD_KZ_B, /* 13606 */ IC_EVEX_L2_XD_KZ_B, /* 13607 */ IC_EVEX_L2_W_KZ_B, /* 13608 */ IC_EVEX_L2_W_KZ_B, /* 13609 */ IC_EVEX_L2_W_XS_KZ_B, /* 13610 */ IC_EVEX_L2_W_XS_KZ_B, /* 13611 */ IC_EVEX_L2_W_XD_KZ_B, /* 13612 */ IC_EVEX_L2_W_XD_KZ_B, /* 13613 */ IC_EVEX_L2_W_XD_KZ_B, /* 13614 */ IC_EVEX_L2_W_XD_KZ_B, /* 13615 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13616 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13617 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13618 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13619 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13620 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13621 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13622 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13623 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13624 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13625 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13626 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13627 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13628 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13629 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13630 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13631 */ IC_EVEX_L2_KZ_B, /* 13632 */ IC_EVEX_L2_KZ_B, /* 13633 */ IC_EVEX_L2_XS_KZ_B, /* 13634 */ IC_EVEX_L2_XS_KZ_B, /* 13635 */ IC_EVEX_L2_XD_KZ_B, /* 13636 */ IC_EVEX_L2_XD_KZ_B, /* 13637 */ IC_EVEX_L2_XD_KZ_B, /* 13638 */ IC_EVEX_L2_XD_KZ_B, /* 13639 */ IC_EVEX_L2_W_KZ_B, /* 13640 */ IC_EVEX_L2_W_KZ_B, /* 13641 */ IC_EVEX_L2_W_XS_KZ_B, /* 13642 */ IC_EVEX_L2_W_XS_KZ_B, /* 13643 */ IC_EVEX_L2_W_XD_KZ_B, /* 13644 */ IC_EVEX_L2_W_XD_KZ_B, /* 13645 */ IC_EVEX_L2_W_XD_KZ_B, /* 13646 */ IC_EVEX_L2_W_XD_KZ_B, /* 13647 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13648 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13649 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13650 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13651 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13652 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13653 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13654 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13655 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13656 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13657 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13658 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13659 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13660 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13661 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13662 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13663 */ IC_EVEX_L2_KZ_B, /* 13664 */ IC_EVEX_L2_KZ_B, /* 13665 */ IC_EVEX_L2_XS_KZ_B, /* 13666 */ IC_EVEX_L2_XS_KZ_B, /* 13667 */ IC_EVEX_L2_XD_KZ_B, /* 13668 */ IC_EVEX_L2_XD_KZ_B, /* 13669 */ IC_EVEX_L2_XD_KZ_B, /* 13670 */ IC_EVEX_L2_XD_KZ_B, /* 13671 */ IC_EVEX_L2_W_KZ_B, /* 13672 */ IC_EVEX_L2_W_KZ_B, /* 13673 */ IC_EVEX_L2_W_XS_KZ_B, /* 13674 */ IC_EVEX_L2_W_XS_KZ_B, /* 13675 */ IC_EVEX_L2_W_XD_KZ_B, /* 13676 */ IC_EVEX_L2_W_XD_KZ_B, /* 13677 */ IC_EVEX_L2_W_XD_KZ_B, /* 13678 */ IC_EVEX_L2_W_XD_KZ_B, /* 13679 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13680 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13681 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13682 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13683 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13684 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13685 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13686 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13687 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13688 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13689 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13690 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13691 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13692 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13693 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13694 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13695 */ IC_EVEX_L2_KZ_B, /* 13696 */ IC_EVEX_L2_KZ_B, /* 13697 */ IC_EVEX_L2_XS_KZ_B, /* 13698 */ IC_EVEX_L2_XS_KZ_B, /* 13699 */ IC_EVEX_L2_XD_KZ_B, /* 13700 */ IC_EVEX_L2_XD_KZ_B, /* 13701 */ IC_EVEX_L2_XD_KZ_B, /* 13702 */ IC_EVEX_L2_XD_KZ_B, /* 13703 */ IC_EVEX_L2_W_KZ_B, /* 13704 */ IC_EVEX_L2_W_KZ_B, /* 13705 */ IC_EVEX_L2_W_XS_KZ_B, /* 13706 */ IC_EVEX_L2_W_XS_KZ_B, /* 13707 */ IC_EVEX_L2_W_XD_KZ_B, /* 13708 */ IC_EVEX_L2_W_XD_KZ_B, /* 13709 */ IC_EVEX_L2_W_XD_KZ_B, /* 13710 */ IC_EVEX_L2_W_XD_KZ_B, /* 13711 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13712 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13713 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13714 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13715 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13716 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13717 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13718 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13719 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13720 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13721 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13722 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13723 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13724 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13725 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13726 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13727 */ IC_EVEX_L2_KZ_B, /* 13728 */ IC_EVEX_L2_KZ_B, /* 13729 */ IC_EVEX_L2_XS_KZ_B, /* 13730 */ IC_EVEX_L2_XS_KZ_B, /* 13731 */ IC_EVEX_L2_XD_KZ_B, /* 13732 */ IC_EVEX_L2_XD_KZ_B, /* 13733 */ IC_EVEX_L2_XD_KZ_B, /* 13734 */ IC_EVEX_L2_XD_KZ_B, /* 13735 */ IC_EVEX_L2_W_KZ_B, /* 13736 */ IC_EVEX_L2_W_KZ_B, /* 13737 */ IC_EVEX_L2_W_XS_KZ_B, /* 13738 */ IC_EVEX_L2_W_XS_KZ_B, /* 13739 */ IC_EVEX_L2_W_XD_KZ_B, /* 13740 */ IC_EVEX_L2_W_XD_KZ_B, /* 13741 */ IC_EVEX_L2_W_XD_KZ_B, /* 13742 */ IC_EVEX_L2_W_XD_KZ_B, /* 13743 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13744 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13745 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13746 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13747 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13748 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13749 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13750 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13751 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13752 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13753 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13754 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13755 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13756 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13757 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13758 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13759 */ IC_EVEX_L2_KZ_B, /* 13760 */ IC_EVEX_L2_KZ_B, /* 13761 */ IC_EVEX_L2_XS_KZ_B, /* 13762 */ IC_EVEX_L2_XS_KZ_B, /* 13763 */ IC_EVEX_L2_XD_KZ_B, /* 13764 */ IC_EVEX_L2_XD_KZ_B, /* 13765 */ IC_EVEX_L2_XD_KZ_B, /* 13766 */ IC_EVEX_L2_XD_KZ_B, /* 13767 */ IC_EVEX_L2_W_KZ_B, /* 13768 */ IC_EVEX_L2_W_KZ_B, /* 13769 */ IC_EVEX_L2_W_XS_KZ_B, /* 13770 */ IC_EVEX_L2_W_XS_KZ_B, /* 13771 */ IC_EVEX_L2_W_XD_KZ_B, /* 13772 */ IC_EVEX_L2_W_XD_KZ_B, /* 13773 */ IC_EVEX_L2_W_XD_KZ_B, /* 13774 */ IC_EVEX_L2_W_XD_KZ_B, /* 13775 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13776 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13777 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13778 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13779 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13780 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13781 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13782 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13783 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13784 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13785 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13786 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13787 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13788 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13789 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13790 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13791 */ IC_EVEX_L2_KZ_B, /* 13792 */ IC_EVEX_L2_KZ_B, /* 13793 */ IC_EVEX_L2_XS_KZ_B, /* 13794 */ IC_EVEX_L2_XS_KZ_B, /* 13795 */ IC_EVEX_L2_XD_KZ_B, /* 13796 */ IC_EVEX_L2_XD_KZ_B, /* 13797 */ IC_EVEX_L2_XD_KZ_B, /* 13798 */ IC_EVEX_L2_XD_KZ_B, /* 13799 */ IC_EVEX_L2_W_KZ_B, /* 13800 */ IC_EVEX_L2_W_KZ_B, /* 13801 */ IC_EVEX_L2_W_XS_KZ_B, /* 13802 */ IC_EVEX_L2_W_XS_KZ_B, /* 13803 */ IC_EVEX_L2_W_XD_KZ_B, /* 13804 */ IC_EVEX_L2_W_XD_KZ_B, /* 13805 */ IC_EVEX_L2_W_XD_KZ_B, /* 13806 */ IC_EVEX_L2_W_XD_KZ_B, /* 13807 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13808 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13809 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13810 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13811 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13812 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13813 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13814 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13815 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13816 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13817 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13818 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13819 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13820 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13821 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13822 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13823 */ IC, /* 13824 */ IC_64BIT, /* 13825 */ IC_XS, /* 13826 */ IC_64BIT_XS, /* 13827 */ IC_XD, /* 13828 */ IC_64BIT_XD, /* 13829 */ IC_XS, /* 13830 */ IC_64BIT_XS, /* 13831 */ IC, /* 13832 */ IC_64BIT_REXW, /* 13833 */ IC_XS, /* 13834 */ IC_64BIT_REXW_XS, /* 13835 */ IC_XD, /* 13836 */ IC_64BIT_REXW_XD, /* 13837 */ IC_XS, /* 13838 */ IC_64BIT_REXW_XS, /* 13839 */ IC_OPSIZE, /* 13840 */ IC_64BIT_OPSIZE, /* 13841 */ IC_XS_OPSIZE, /* 13842 */ IC_64BIT_XS_OPSIZE, /* 13843 */ IC_XD_OPSIZE, /* 13844 */ IC_64BIT_XD_OPSIZE, /* 13845 */ IC_XS_OPSIZE, /* 13846 */ IC_64BIT_XD_OPSIZE, /* 13847 */ IC_OPSIZE, /* 13848 */ IC_64BIT_REXW_OPSIZE, /* 13849 */ IC_XS_OPSIZE, /* 13850 */ IC_64BIT_REXW_XS, /* 13851 */ IC_XD_OPSIZE, /* 13852 */ IC_64BIT_REXW_XD, /* 13853 */ IC_XS_OPSIZE, /* 13854 */ IC_64BIT_REXW_XS, /* 13855 */ IC_ADSIZE, /* 13856 */ IC_64BIT_ADSIZE, /* 13857 */ IC_XS_ADSIZE, /* 13858 */ IC_64BIT_XS_ADSIZE, /* 13859 */ IC_XD_ADSIZE, /* 13860 */ IC_64BIT_XD_ADSIZE, /* 13861 */ IC_XS_ADSIZE, /* 13862 */ IC_64BIT_XD_ADSIZE, /* 13863 */ IC_ADSIZE, /* 13864 */ IC_64BIT_REXW_ADSIZE, /* 13865 */ IC_XS_ADSIZE, /* 13866 */ IC_64BIT_REXW_XS, /* 13867 */ IC_XD_ADSIZE, /* 13868 */ IC_64BIT_REXW_XD, /* 13869 */ IC_XS_ADSIZE, /* 13870 */ IC_64BIT_REXW_XS, /* 13871 */ IC_OPSIZE_ADSIZE, /* 13872 */ IC_64BIT_OPSIZE_ADSIZE, /* 13873 */ IC_XS_OPSIZE, /* 13874 */ IC_64BIT_XS_OPSIZE, /* 13875 */ IC_XD_OPSIZE, /* 13876 */ IC_64BIT_XD_OPSIZE, /* 13877 */ IC_XS_OPSIZE, /* 13878 */ IC_64BIT_XD_OPSIZE, /* 13879 */ IC_OPSIZE_ADSIZE, /* 13880 */ IC_64BIT_REXW_OPSIZE, /* 13881 */ IC_XS_OPSIZE, /* 13882 */ IC_64BIT_REXW_XS, /* 13883 */ IC_XD_OPSIZE, /* 13884 */ IC_64BIT_REXW_XD, /* 13885 */ IC_XS_OPSIZE, /* 13886 */ IC_64BIT_REXW_XS, /* 13887 */ IC_VEX, /* 13888 */ IC_VEX, /* 13889 */ IC_VEX_XS, /* 13890 */ IC_VEX_XS, /* 13891 */ IC_VEX_XD, /* 13892 */ IC_VEX_XD, /* 13893 */ IC_VEX_XD, /* 13894 */ IC_VEX_XD, /* 13895 */ IC_VEX_W, /* 13896 */ IC_VEX_W, /* 13897 */ IC_VEX_W_XS, /* 13898 */ IC_VEX_W_XS, /* 13899 */ IC_VEX_W_XD, /* 13900 */ IC_VEX_W_XD, /* 13901 */ IC_VEX_W_XD, /* 13902 */ IC_VEX_W_XD, /* 13903 */ IC_VEX_OPSIZE, /* 13904 */ IC_VEX_OPSIZE, /* 13905 */ IC_VEX_OPSIZE, /* 13906 */ IC_VEX_OPSIZE, /* 13907 */ IC_VEX_OPSIZE, /* 13908 */ IC_VEX_OPSIZE, /* 13909 */ IC_VEX_OPSIZE, /* 13910 */ IC_VEX_OPSIZE, /* 13911 */ IC_VEX_W_OPSIZE, /* 13912 */ IC_VEX_W_OPSIZE, /* 13913 */ IC_VEX_W_OPSIZE, /* 13914 */ IC_VEX_W_OPSIZE, /* 13915 */ IC_VEX_W_OPSIZE, /* 13916 */ IC_VEX_W_OPSIZE, /* 13917 */ IC_VEX_W_OPSIZE, /* 13918 */ IC_VEX_W_OPSIZE, /* 13919 */ IC_VEX, /* 13920 */ IC_VEX, /* 13921 */ IC_VEX_XS, /* 13922 */ IC_VEX_XS, /* 13923 */ IC_VEX_XD, /* 13924 */ IC_VEX_XD, /* 13925 */ IC_VEX_XD, /* 13926 */ IC_VEX_XD, /* 13927 */ IC_VEX_W, /* 13928 */ IC_VEX_W, /* 13929 */ IC_VEX_W_XS, /* 13930 */ IC_VEX_W_XS, /* 13931 */ IC_VEX_W_XD, /* 13932 */ IC_VEX_W_XD, /* 13933 */ IC_VEX_W_XD, /* 13934 */ IC_VEX_W_XD, /* 13935 */ IC_VEX_OPSIZE, /* 13936 */ IC_VEX_OPSIZE, /* 13937 */ IC_VEX_OPSIZE, /* 13938 */ IC_VEX_OPSIZE, /* 13939 */ IC_VEX_OPSIZE, /* 13940 */ IC_VEX_OPSIZE, /* 13941 */ IC_VEX_OPSIZE, /* 13942 */ IC_VEX_OPSIZE, /* 13943 */ IC_VEX_W_OPSIZE, /* 13944 */ IC_VEX_W_OPSIZE, /* 13945 */ IC_VEX_W_OPSIZE, /* 13946 */ IC_VEX_W_OPSIZE, /* 13947 */ IC_VEX_W_OPSIZE, /* 13948 */ IC_VEX_W_OPSIZE, /* 13949 */ IC_VEX_W_OPSIZE, /* 13950 */ IC_VEX_W_OPSIZE, /* 13951 */ IC_VEX_L, /* 13952 */ IC_VEX_L, /* 13953 */ IC_VEX_L_XS, /* 13954 */ IC_VEX_L_XS, /* 13955 */ IC_VEX_L_XD, /* 13956 */ IC_VEX_L_XD, /* 13957 */ IC_VEX_L_XD, /* 13958 */ IC_VEX_L_XD, /* 13959 */ IC_VEX_L_W, /* 13960 */ IC_VEX_L_W, /* 13961 */ IC_VEX_L_W_XS, /* 13962 */ IC_VEX_L_W_XS, /* 13963 */ IC_VEX_L_W_XD, /* 13964 */ IC_VEX_L_W_XD, /* 13965 */ IC_VEX_L_W_XD, /* 13966 */ IC_VEX_L_W_XD, /* 13967 */ IC_VEX_L_OPSIZE, /* 13968 */ IC_VEX_L_OPSIZE, /* 13969 */ IC_VEX_L_OPSIZE, /* 13970 */ IC_VEX_L_OPSIZE, /* 13971 */ IC_VEX_L_OPSIZE, /* 13972 */ IC_VEX_L_OPSIZE, /* 13973 */ IC_VEX_L_OPSIZE, /* 13974 */ IC_VEX_L_OPSIZE, /* 13975 */ IC_VEX_L_W_OPSIZE, /* 13976 */ IC_VEX_L_W_OPSIZE, /* 13977 */ IC_VEX_L_W_OPSIZE, /* 13978 */ IC_VEX_L_W_OPSIZE, /* 13979 */ IC_VEX_L_W_OPSIZE, /* 13980 */ IC_VEX_L_W_OPSIZE, /* 13981 */ IC_VEX_L_W_OPSIZE, /* 13982 */ IC_VEX_L_W_OPSIZE, /* 13983 */ IC_VEX_L, /* 13984 */ IC_VEX_L, /* 13985 */ IC_VEX_L_XS, /* 13986 */ IC_VEX_L_XS, /* 13987 */ IC_VEX_L_XD, /* 13988 */ IC_VEX_L_XD, /* 13989 */ IC_VEX_L_XD, /* 13990 */ IC_VEX_L_XD, /* 13991 */ IC_VEX_L_W, /* 13992 */ IC_VEX_L_W, /* 13993 */ IC_VEX_L_W_XS, /* 13994 */ IC_VEX_L_W_XS, /* 13995 */ IC_VEX_L_W_XD, /* 13996 */ IC_VEX_L_W_XD, /* 13997 */ IC_VEX_L_W_XD, /* 13998 */ IC_VEX_L_W_XD, /* 13999 */ IC_VEX_L_OPSIZE, /* 14000 */ IC_VEX_L_OPSIZE, /* 14001 */ IC_VEX_L_OPSIZE, /* 14002 */ IC_VEX_L_OPSIZE, /* 14003 */ IC_VEX_L_OPSIZE, /* 14004 */ IC_VEX_L_OPSIZE, /* 14005 */ IC_VEX_L_OPSIZE, /* 14006 */ IC_VEX_L_OPSIZE, /* 14007 */ IC_VEX_L_W_OPSIZE, /* 14008 */ IC_VEX_L_W_OPSIZE, /* 14009 */ IC_VEX_L_W_OPSIZE, /* 14010 */ IC_VEX_L_W_OPSIZE, /* 14011 */ IC_VEX_L_W_OPSIZE, /* 14012 */ IC_VEX_L_W_OPSIZE, /* 14013 */ IC_VEX_L_W_OPSIZE, /* 14014 */ IC_VEX_L_W_OPSIZE, /* 14015 */ IC_VEX_L, /* 14016 */ IC_VEX_L, /* 14017 */ IC_VEX_L_XS, /* 14018 */ IC_VEX_L_XS, /* 14019 */ IC_VEX_L_XD, /* 14020 */ IC_VEX_L_XD, /* 14021 */ IC_VEX_L_XD, /* 14022 */ IC_VEX_L_XD, /* 14023 */ IC_VEX_L_W, /* 14024 */ IC_VEX_L_W, /* 14025 */ IC_VEX_L_W_XS, /* 14026 */ IC_VEX_L_W_XS, /* 14027 */ IC_VEX_L_W_XD, /* 14028 */ IC_VEX_L_W_XD, /* 14029 */ IC_VEX_L_W_XD, /* 14030 */ IC_VEX_L_W_XD, /* 14031 */ IC_VEX_L_OPSIZE, /* 14032 */ IC_VEX_L_OPSIZE, /* 14033 */ IC_VEX_L_OPSIZE, /* 14034 */ IC_VEX_L_OPSIZE, /* 14035 */ IC_VEX_L_OPSIZE, /* 14036 */ IC_VEX_L_OPSIZE, /* 14037 */ IC_VEX_L_OPSIZE, /* 14038 */ IC_VEX_L_OPSIZE, /* 14039 */ IC_VEX_L_W_OPSIZE, /* 14040 */ IC_VEX_L_W_OPSIZE, /* 14041 */ IC_VEX_L_W_OPSIZE, /* 14042 */ IC_VEX_L_W_OPSIZE, /* 14043 */ IC_VEX_L_W_OPSIZE, /* 14044 */ IC_VEX_L_W_OPSIZE, /* 14045 */ IC_VEX_L_W_OPSIZE, /* 14046 */ IC_VEX_L_W_OPSIZE, /* 14047 */ IC_VEX_L, /* 14048 */ IC_VEX_L, /* 14049 */ IC_VEX_L_XS, /* 14050 */ IC_VEX_L_XS, /* 14051 */ IC_VEX_L_XD, /* 14052 */ IC_VEX_L_XD, /* 14053 */ IC_VEX_L_XD, /* 14054 */ IC_VEX_L_XD, /* 14055 */ IC_VEX_L_W, /* 14056 */ IC_VEX_L_W, /* 14057 */ IC_VEX_L_W_XS, /* 14058 */ IC_VEX_L_W_XS, /* 14059 */ IC_VEX_L_W_XD, /* 14060 */ IC_VEX_L_W_XD, /* 14061 */ IC_VEX_L_W_XD, /* 14062 */ IC_VEX_L_W_XD, /* 14063 */ IC_VEX_L_OPSIZE, /* 14064 */ IC_VEX_L_OPSIZE, /* 14065 */ IC_VEX_L_OPSIZE, /* 14066 */ IC_VEX_L_OPSIZE, /* 14067 */ IC_VEX_L_OPSIZE, /* 14068 */ IC_VEX_L_OPSIZE, /* 14069 */ IC_VEX_L_OPSIZE, /* 14070 */ IC_VEX_L_OPSIZE, /* 14071 */ IC_VEX_L_W_OPSIZE, /* 14072 */ IC_VEX_L_W_OPSIZE, /* 14073 */ IC_VEX_L_W_OPSIZE, /* 14074 */ IC_VEX_L_W_OPSIZE, /* 14075 */ IC_VEX_L_W_OPSIZE, /* 14076 */ IC_VEX_L_W_OPSIZE, /* 14077 */ IC_VEX_L_W_OPSIZE, /* 14078 */ IC_VEX_L_W_OPSIZE, /* 14079 */ IC_EVEX_L2_KZ_B, /* 14080 */ IC_EVEX_L2_KZ_B, /* 14081 */ IC_EVEX_L2_XS_KZ_B, /* 14082 */ IC_EVEX_L2_XS_KZ_B, /* 14083 */ IC_EVEX_L2_XD_KZ_B, /* 14084 */ IC_EVEX_L2_XD_KZ_B, /* 14085 */ IC_EVEX_L2_XD_KZ_B, /* 14086 */ IC_EVEX_L2_XD_KZ_B, /* 14087 */ IC_EVEX_L2_W_KZ_B, /* 14088 */ IC_EVEX_L2_W_KZ_B, /* 14089 */ IC_EVEX_L2_W_XS_KZ_B, /* 14090 */ IC_EVEX_L2_W_XS_KZ_B, /* 14091 */ IC_EVEX_L2_W_XD_KZ_B, /* 14092 */ IC_EVEX_L2_W_XD_KZ_B, /* 14093 */ IC_EVEX_L2_W_XD_KZ_B, /* 14094 */ IC_EVEX_L2_W_XD_KZ_B, /* 14095 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14096 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14097 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14098 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14099 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14100 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14101 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14102 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14103 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14104 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14105 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14106 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14107 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14108 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14109 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14110 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14111 */ IC_EVEX_L2_KZ_B, /* 14112 */ IC_EVEX_L2_KZ_B, /* 14113 */ IC_EVEX_L2_XS_KZ_B, /* 14114 */ IC_EVEX_L2_XS_KZ_B, /* 14115 */ IC_EVEX_L2_XD_KZ_B, /* 14116 */ IC_EVEX_L2_XD_KZ_B, /* 14117 */ IC_EVEX_L2_XD_KZ_B, /* 14118 */ IC_EVEX_L2_XD_KZ_B, /* 14119 */ IC_EVEX_L2_W_KZ_B, /* 14120 */ IC_EVEX_L2_W_KZ_B, /* 14121 */ IC_EVEX_L2_W_XS_KZ_B, /* 14122 */ IC_EVEX_L2_W_XS_KZ_B, /* 14123 */ IC_EVEX_L2_W_XD_KZ_B, /* 14124 */ IC_EVEX_L2_W_XD_KZ_B, /* 14125 */ IC_EVEX_L2_W_XD_KZ_B, /* 14126 */ IC_EVEX_L2_W_XD_KZ_B, /* 14127 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14128 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14129 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14130 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14131 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14132 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14133 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14134 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14135 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14136 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14137 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14138 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14139 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14140 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14141 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14142 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14143 */ IC_EVEX_L2_KZ_B, /* 14144 */ IC_EVEX_L2_KZ_B, /* 14145 */ IC_EVEX_L2_XS_KZ_B, /* 14146 */ IC_EVEX_L2_XS_KZ_B, /* 14147 */ IC_EVEX_L2_XD_KZ_B, /* 14148 */ IC_EVEX_L2_XD_KZ_B, /* 14149 */ IC_EVEX_L2_XD_KZ_B, /* 14150 */ IC_EVEX_L2_XD_KZ_B, /* 14151 */ IC_EVEX_L2_W_KZ_B, /* 14152 */ IC_EVEX_L2_W_KZ_B, /* 14153 */ IC_EVEX_L2_W_XS_KZ_B, /* 14154 */ IC_EVEX_L2_W_XS_KZ_B, /* 14155 */ IC_EVEX_L2_W_XD_KZ_B, /* 14156 */ IC_EVEX_L2_W_XD_KZ_B, /* 14157 */ IC_EVEX_L2_W_XD_KZ_B, /* 14158 */ IC_EVEX_L2_W_XD_KZ_B, /* 14159 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14160 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14161 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14162 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14163 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14164 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14165 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14166 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14167 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14168 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14169 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14170 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14171 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14172 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14173 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14174 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14175 */ IC_EVEX_L2_KZ_B, /* 14176 */ IC_EVEX_L2_KZ_B, /* 14177 */ IC_EVEX_L2_XS_KZ_B, /* 14178 */ IC_EVEX_L2_XS_KZ_B, /* 14179 */ IC_EVEX_L2_XD_KZ_B, /* 14180 */ IC_EVEX_L2_XD_KZ_B, /* 14181 */ IC_EVEX_L2_XD_KZ_B, /* 14182 */ IC_EVEX_L2_XD_KZ_B, /* 14183 */ IC_EVEX_L2_W_KZ_B, /* 14184 */ IC_EVEX_L2_W_KZ_B, /* 14185 */ IC_EVEX_L2_W_XS_KZ_B, /* 14186 */ IC_EVEX_L2_W_XS_KZ_B, /* 14187 */ IC_EVEX_L2_W_XD_KZ_B, /* 14188 */ IC_EVEX_L2_W_XD_KZ_B, /* 14189 */ IC_EVEX_L2_W_XD_KZ_B, /* 14190 */ IC_EVEX_L2_W_XD_KZ_B, /* 14191 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14192 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14193 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14194 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14195 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14196 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14197 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14198 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14199 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14200 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14201 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14202 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14203 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14204 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14205 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14206 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14207 */ IC_EVEX_L2_KZ_B, /* 14208 */ IC_EVEX_L2_KZ_B, /* 14209 */ IC_EVEX_L2_XS_KZ_B, /* 14210 */ IC_EVEX_L2_XS_KZ_B, /* 14211 */ IC_EVEX_L2_XD_KZ_B, /* 14212 */ IC_EVEX_L2_XD_KZ_B, /* 14213 */ IC_EVEX_L2_XD_KZ_B, /* 14214 */ IC_EVEX_L2_XD_KZ_B, /* 14215 */ IC_EVEX_L2_W_KZ_B, /* 14216 */ IC_EVEX_L2_W_KZ_B, /* 14217 */ IC_EVEX_L2_W_XS_KZ_B, /* 14218 */ IC_EVEX_L2_W_XS_KZ_B, /* 14219 */ IC_EVEX_L2_W_XD_KZ_B, /* 14220 */ IC_EVEX_L2_W_XD_KZ_B, /* 14221 */ IC_EVEX_L2_W_XD_KZ_B, /* 14222 */ IC_EVEX_L2_W_XD_KZ_B, /* 14223 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14224 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14225 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14226 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14227 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14228 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14229 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14230 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14231 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14232 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14233 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14234 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14235 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14236 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14237 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14238 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14239 */ IC_EVEX_L2_KZ_B, /* 14240 */ IC_EVEX_L2_KZ_B, /* 14241 */ IC_EVEX_L2_XS_KZ_B, /* 14242 */ IC_EVEX_L2_XS_KZ_B, /* 14243 */ IC_EVEX_L2_XD_KZ_B, /* 14244 */ IC_EVEX_L2_XD_KZ_B, /* 14245 */ IC_EVEX_L2_XD_KZ_B, /* 14246 */ IC_EVEX_L2_XD_KZ_B, /* 14247 */ IC_EVEX_L2_W_KZ_B, /* 14248 */ IC_EVEX_L2_W_KZ_B, /* 14249 */ IC_EVEX_L2_W_XS_KZ_B, /* 14250 */ IC_EVEX_L2_W_XS_KZ_B, /* 14251 */ IC_EVEX_L2_W_XD_KZ_B, /* 14252 */ IC_EVEX_L2_W_XD_KZ_B, /* 14253 */ IC_EVEX_L2_W_XD_KZ_B, /* 14254 */ IC_EVEX_L2_W_XD_KZ_B, /* 14255 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14256 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14257 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14258 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14259 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14260 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14261 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14262 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14263 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14264 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14265 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14266 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14267 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14268 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14269 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14270 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14271 */ IC_EVEX_L2_KZ_B, /* 14272 */ IC_EVEX_L2_KZ_B, /* 14273 */ IC_EVEX_L2_XS_KZ_B, /* 14274 */ IC_EVEX_L2_XS_KZ_B, /* 14275 */ IC_EVEX_L2_XD_KZ_B, /* 14276 */ IC_EVEX_L2_XD_KZ_B, /* 14277 */ IC_EVEX_L2_XD_KZ_B, /* 14278 */ IC_EVEX_L2_XD_KZ_B, /* 14279 */ IC_EVEX_L2_W_KZ_B, /* 14280 */ IC_EVEX_L2_W_KZ_B, /* 14281 */ IC_EVEX_L2_W_XS_KZ_B, /* 14282 */ IC_EVEX_L2_W_XS_KZ_B, /* 14283 */ IC_EVEX_L2_W_XD_KZ_B, /* 14284 */ IC_EVEX_L2_W_XD_KZ_B, /* 14285 */ IC_EVEX_L2_W_XD_KZ_B, /* 14286 */ IC_EVEX_L2_W_XD_KZ_B, /* 14287 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14288 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14289 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14290 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14291 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14292 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14293 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14294 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14295 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14296 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14297 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14298 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14299 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14300 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14301 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14302 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14303 */ IC_EVEX_L2_KZ_B, /* 14304 */ IC_EVEX_L2_KZ_B, /* 14305 */ IC_EVEX_L2_XS_KZ_B, /* 14306 */ IC_EVEX_L2_XS_KZ_B, /* 14307 */ IC_EVEX_L2_XD_KZ_B, /* 14308 */ IC_EVEX_L2_XD_KZ_B, /* 14309 */ IC_EVEX_L2_XD_KZ_B, /* 14310 */ IC_EVEX_L2_XD_KZ_B, /* 14311 */ IC_EVEX_L2_W_KZ_B, /* 14312 */ IC_EVEX_L2_W_KZ_B, /* 14313 */ IC_EVEX_L2_W_XS_KZ_B, /* 14314 */ IC_EVEX_L2_W_XS_KZ_B, /* 14315 */ IC_EVEX_L2_W_XD_KZ_B, /* 14316 */ IC_EVEX_L2_W_XD_KZ_B, /* 14317 */ IC_EVEX_L2_W_XD_KZ_B, /* 14318 */ IC_EVEX_L2_W_XD_KZ_B, /* 14319 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14320 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14321 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14322 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14323 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14324 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14325 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14326 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14327 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14328 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14329 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14330 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14331 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14332 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14333 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14334 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14335 */ IC, /* 14336 */ IC_64BIT, /* 14337 */ IC_XS, /* 14338 */ IC_64BIT_XS, /* 14339 */ IC_XD, /* 14340 */ IC_64BIT_XD, /* 14341 */ IC_XS, /* 14342 */ IC_64BIT_XS, /* 14343 */ IC, /* 14344 */ IC_64BIT_REXW, /* 14345 */ IC_XS, /* 14346 */ IC_64BIT_REXW_XS, /* 14347 */ IC_XD, /* 14348 */ IC_64BIT_REXW_XD, /* 14349 */ IC_XS, /* 14350 */ IC_64BIT_REXW_XS, /* 14351 */ IC_OPSIZE, /* 14352 */ IC_64BIT_OPSIZE, /* 14353 */ IC_XS_OPSIZE, /* 14354 */ IC_64BIT_XS_OPSIZE, /* 14355 */ IC_XD_OPSIZE, /* 14356 */ IC_64BIT_XD_OPSIZE, /* 14357 */ IC_XS_OPSIZE, /* 14358 */ IC_64BIT_XD_OPSIZE, /* 14359 */ IC_OPSIZE, /* 14360 */ IC_64BIT_REXW_OPSIZE, /* 14361 */ IC_XS_OPSIZE, /* 14362 */ IC_64BIT_REXW_XS, /* 14363 */ IC_XD_OPSIZE, /* 14364 */ IC_64BIT_REXW_XD, /* 14365 */ IC_XS_OPSIZE, /* 14366 */ IC_64BIT_REXW_XS, /* 14367 */ IC_ADSIZE, /* 14368 */ IC_64BIT_ADSIZE, /* 14369 */ IC_XS_ADSIZE, /* 14370 */ IC_64BIT_XS_ADSIZE, /* 14371 */ IC_XD_ADSIZE, /* 14372 */ IC_64BIT_XD_ADSIZE, /* 14373 */ IC_XS_ADSIZE, /* 14374 */ IC_64BIT_XD_ADSIZE, /* 14375 */ IC_ADSIZE, /* 14376 */ IC_64BIT_REXW_ADSIZE, /* 14377 */ IC_XS_ADSIZE, /* 14378 */ IC_64BIT_REXW_XS, /* 14379 */ IC_XD_ADSIZE, /* 14380 */ IC_64BIT_REXW_XD, /* 14381 */ IC_XS_ADSIZE, /* 14382 */ IC_64BIT_REXW_XS, /* 14383 */ IC_OPSIZE_ADSIZE, /* 14384 */ IC_64BIT_OPSIZE_ADSIZE, /* 14385 */ IC_XS_OPSIZE, /* 14386 */ IC_64BIT_XS_OPSIZE, /* 14387 */ IC_XD_OPSIZE, /* 14388 */ IC_64BIT_XD_OPSIZE, /* 14389 */ IC_XS_OPSIZE, /* 14390 */ IC_64BIT_XD_OPSIZE, /* 14391 */ IC_OPSIZE_ADSIZE, /* 14392 */ IC_64BIT_REXW_OPSIZE, /* 14393 */ IC_XS_OPSIZE, /* 14394 */ IC_64BIT_REXW_XS, /* 14395 */ IC_XD_OPSIZE, /* 14396 */ IC_64BIT_REXW_XD, /* 14397 */ IC_XS_OPSIZE, /* 14398 */ IC_64BIT_REXW_XS, /* 14399 */ IC_VEX, /* 14400 */ IC_VEX, /* 14401 */ IC_VEX_XS, /* 14402 */ IC_VEX_XS, /* 14403 */ IC_VEX_XD, /* 14404 */ IC_VEX_XD, /* 14405 */ IC_VEX_XD, /* 14406 */ IC_VEX_XD, /* 14407 */ IC_VEX_W, /* 14408 */ IC_VEX_W, /* 14409 */ IC_VEX_W_XS, /* 14410 */ IC_VEX_W_XS, /* 14411 */ IC_VEX_W_XD, /* 14412 */ IC_VEX_W_XD, /* 14413 */ IC_VEX_W_XD, /* 14414 */ IC_VEX_W_XD, /* 14415 */ IC_VEX_OPSIZE, /* 14416 */ IC_VEX_OPSIZE, /* 14417 */ IC_VEX_OPSIZE, /* 14418 */ IC_VEX_OPSIZE, /* 14419 */ IC_VEX_OPSIZE, /* 14420 */ IC_VEX_OPSIZE, /* 14421 */ IC_VEX_OPSIZE, /* 14422 */ IC_VEX_OPSIZE, /* 14423 */ IC_VEX_W_OPSIZE, /* 14424 */ IC_VEX_W_OPSIZE, /* 14425 */ IC_VEX_W_OPSIZE, /* 14426 */ IC_VEX_W_OPSIZE, /* 14427 */ IC_VEX_W_OPSIZE, /* 14428 */ IC_VEX_W_OPSIZE, /* 14429 */ IC_VEX_W_OPSIZE, /* 14430 */ IC_VEX_W_OPSIZE, /* 14431 */ IC_VEX, /* 14432 */ IC_VEX, /* 14433 */ IC_VEX_XS, /* 14434 */ IC_VEX_XS, /* 14435 */ IC_VEX_XD, /* 14436 */ IC_VEX_XD, /* 14437 */ IC_VEX_XD, /* 14438 */ IC_VEX_XD, /* 14439 */ IC_VEX_W, /* 14440 */ IC_VEX_W, /* 14441 */ IC_VEX_W_XS, /* 14442 */ IC_VEX_W_XS, /* 14443 */ IC_VEX_W_XD, /* 14444 */ IC_VEX_W_XD, /* 14445 */ IC_VEX_W_XD, /* 14446 */ IC_VEX_W_XD, /* 14447 */ IC_VEX_OPSIZE, /* 14448 */ IC_VEX_OPSIZE, /* 14449 */ IC_VEX_OPSIZE, /* 14450 */ IC_VEX_OPSIZE, /* 14451 */ IC_VEX_OPSIZE, /* 14452 */ IC_VEX_OPSIZE, /* 14453 */ IC_VEX_OPSIZE, /* 14454 */ IC_VEX_OPSIZE, /* 14455 */ IC_VEX_W_OPSIZE, /* 14456 */ IC_VEX_W_OPSIZE, /* 14457 */ IC_VEX_W_OPSIZE, /* 14458 */ IC_VEX_W_OPSIZE, /* 14459 */ IC_VEX_W_OPSIZE, /* 14460 */ IC_VEX_W_OPSIZE, /* 14461 */ IC_VEX_W_OPSIZE, /* 14462 */ IC_VEX_W_OPSIZE, /* 14463 */ IC_VEX_L, /* 14464 */ IC_VEX_L, /* 14465 */ IC_VEX_L_XS, /* 14466 */ IC_VEX_L_XS, /* 14467 */ IC_VEX_L_XD, /* 14468 */ IC_VEX_L_XD, /* 14469 */ IC_VEX_L_XD, /* 14470 */ IC_VEX_L_XD, /* 14471 */ IC_VEX_L_W, /* 14472 */ IC_VEX_L_W, /* 14473 */ IC_VEX_L_W_XS, /* 14474 */ IC_VEX_L_W_XS, /* 14475 */ IC_VEX_L_W_XD, /* 14476 */ IC_VEX_L_W_XD, /* 14477 */ IC_VEX_L_W_XD, /* 14478 */ IC_VEX_L_W_XD, /* 14479 */ IC_VEX_L_OPSIZE, /* 14480 */ IC_VEX_L_OPSIZE, /* 14481 */ IC_VEX_L_OPSIZE, /* 14482 */ IC_VEX_L_OPSIZE, /* 14483 */ IC_VEX_L_OPSIZE, /* 14484 */ IC_VEX_L_OPSIZE, /* 14485 */ IC_VEX_L_OPSIZE, /* 14486 */ IC_VEX_L_OPSIZE, /* 14487 */ IC_VEX_L_W_OPSIZE, /* 14488 */ IC_VEX_L_W_OPSIZE, /* 14489 */ IC_VEX_L_W_OPSIZE, /* 14490 */ IC_VEX_L_W_OPSIZE, /* 14491 */ IC_VEX_L_W_OPSIZE, /* 14492 */ IC_VEX_L_W_OPSIZE, /* 14493 */ IC_VEX_L_W_OPSIZE, /* 14494 */ IC_VEX_L_W_OPSIZE, /* 14495 */ IC_VEX_L, /* 14496 */ IC_VEX_L, /* 14497 */ IC_VEX_L_XS, /* 14498 */ IC_VEX_L_XS, /* 14499 */ IC_VEX_L_XD, /* 14500 */ IC_VEX_L_XD, /* 14501 */ IC_VEX_L_XD, /* 14502 */ IC_VEX_L_XD, /* 14503 */ IC_VEX_L_W, /* 14504 */ IC_VEX_L_W, /* 14505 */ IC_VEX_L_W_XS, /* 14506 */ IC_VEX_L_W_XS, /* 14507 */ IC_VEX_L_W_XD, /* 14508 */ IC_VEX_L_W_XD, /* 14509 */ IC_VEX_L_W_XD, /* 14510 */ IC_VEX_L_W_XD, /* 14511 */ IC_VEX_L_OPSIZE, /* 14512 */ IC_VEX_L_OPSIZE, /* 14513 */ IC_VEX_L_OPSIZE, /* 14514 */ IC_VEX_L_OPSIZE, /* 14515 */ IC_VEX_L_OPSIZE, /* 14516 */ IC_VEX_L_OPSIZE, /* 14517 */ IC_VEX_L_OPSIZE, /* 14518 */ IC_VEX_L_OPSIZE, /* 14519 */ IC_VEX_L_W_OPSIZE, /* 14520 */ IC_VEX_L_W_OPSIZE, /* 14521 */ IC_VEX_L_W_OPSIZE, /* 14522 */ IC_VEX_L_W_OPSIZE, /* 14523 */ IC_VEX_L_W_OPSIZE, /* 14524 */ IC_VEX_L_W_OPSIZE, /* 14525 */ IC_VEX_L_W_OPSIZE, /* 14526 */ IC_VEX_L_W_OPSIZE, /* 14527 */ IC_VEX_L, /* 14528 */ IC_VEX_L, /* 14529 */ IC_VEX_L_XS, /* 14530 */ IC_VEX_L_XS, /* 14531 */ IC_VEX_L_XD, /* 14532 */ IC_VEX_L_XD, /* 14533 */ IC_VEX_L_XD, /* 14534 */ IC_VEX_L_XD, /* 14535 */ IC_VEX_L_W, /* 14536 */ IC_VEX_L_W, /* 14537 */ IC_VEX_L_W_XS, /* 14538 */ IC_VEX_L_W_XS, /* 14539 */ IC_VEX_L_W_XD, /* 14540 */ IC_VEX_L_W_XD, /* 14541 */ IC_VEX_L_W_XD, /* 14542 */ IC_VEX_L_W_XD, /* 14543 */ IC_VEX_L_OPSIZE, /* 14544 */ IC_VEX_L_OPSIZE, /* 14545 */ IC_VEX_L_OPSIZE, /* 14546 */ IC_VEX_L_OPSIZE, /* 14547 */ IC_VEX_L_OPSIZE, /* 14548 */ IC_VEX_L_OPSIZE, /* 14549 */ IC_VEX_L_OPSIZE, /* 14550 */ IC_VEX_L_OPSIZE, /* 14551 */ IC_VEX_L_W_OPSIZE, /* 14552 */ IC_VEX_L_W_OPSIZE, /* 14553 */ IC_VEX_L_W_OPSIZE, /* 14554 */ IC_VEX_L_W_OPSIZE, /* 14555 */ IC_VEX_L_W_OPSIZE, /* 14556 */ IC_VEX_L_W_OPSIZE, /* 14557 */ IC_VEX_L_W_OPSIZE, /* 14558 */ IC_VEX_L_W_OPSIZE, /* 14559 */ IC_VEX_L, /* 14560 */ IC_VEX_L, /* 14561 */ IC_VEX_L_XS, /* 14562 */ IC_VEX_L_XS, /* 14563 */ IC_VEX_L_XD, /* 14564 */ IC_VEX_L_XD, /* 14565 */ IC_VEX_L_XD, /* 14566 */ IC_VEX_L_XD, /* 14567 */ IC_VEX_L_W, /* 14568 */ IC_VEX_L_W, /* 14569 */ IC_VEX_L_W_XS, /* 14570 */ IC_VEX_L_W_XS, /* 14571 */ IC_VEX_L_W_XD, /* 14572 */ IC_VEX_L_W_XD, /* 14573 */ IC_VEX_L_W_XD, /* 14574 */ IC_VEX_L_W_XD, /* 14575 */ IC_VEX_L_OPSIZE, /* 14576 */ IC_VEX_L_OPSIZE, /* 14577 */ IC_VEX_L_OPSIZE, /* 14578 */ IC_VEX_L_OPSIZE, /* 14579 */ IC_VEX_L_OPSIZE, /* 14580 */ IC_VEX_L_OPSIZE, /* 14581 */ IC_VEX_L_OPSIZE, /* 14582 */ IC_VEX_L_OPSIZE, /* 14583 */ IC_VEX_L_W_OPSIZE, /* 14584 */ IC_VEX_L_W_OPSIZE, /* 14585 */ IC_VEX_L_W_OPSIZE, /* 14586 */ IC_VEX_L_W_OPSIZE, /* 14587 */ IC_VEX_L_W_OPSIZE, /* 14588 */ IC_VEX_L_W_OPSIZE, /* 14589 */ IC_VEX_L_W_OPSIZE, /* 14590 */ IC_VEX_L_W_OPSIZE, /* 14591 */ IC_EVEX_KZ_B, /* 14592 */ IC_EVEX_KZ_B, /* 14593 */ IC_EVEX_XS_KZ_B, /* 14594 */ IC_EVEX_XS_KZ_B, /* 14595 */ IC_EVEX_XD_KZ_B, /* 14596 */ IC_EVEX_XD_KZ_B, /* 14597 */ IC_EVEX_XD_KZ_B, /* 14598 */ IC_EVEX_XD_KZ_B, /* 14599 */ IC_EVEX_W_KZ_B, /* 14600 */ IC_EVEX_W_KZ_B, /* 14601 */ IC_EVEX_W_XS_KZ_B, /* 14602 */ IC_EVEX_W_XS_KZ_B, /* 14603 */ IC_EVEX_W_XD_KZ_B, /* 14604 */ IC_EVEX_W_XD_KZ_B, /* 14605 */ IC_EVEX_W_XD_KZ_B, /* 14606 */ IC_EVEX_W_XD_KZ_B, /* 14607 */ IC_EVEX_OPSIZE_KZ_B, /* 14608 */ IC_EVEX_OPSIZE_KZ_B, /* 14609 */ IC_EVEX_OPSIZE_KZ_B, /* 14610 */ IC_EVEX_OPSIZE_KZ_B, /* 14611 */ IC_EVEX_OPSIZE_KZ_B, /* 14612 */ IC_EVEX_OPSIZE_KZ_B, /* 14613 */ IC_EVEX_OPSIZE_KZ_B, /* 14614 */ IC_EVEX_OPSIZE_KZ_B, /* 14615 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14616 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14617 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14618 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14619 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14620 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14621 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14622 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14623 */ IC_EVEX_KZ_B, /* 14624 */ IC_EVEX_KZ_B, /* 14625 */ IC_EVEX_XS_KZ_B, /* 14626 */ IC_EVEX_XS_KZ_B, /* 14627 */ IC_EVEX_XD_KZ_B, /* 14628 */ IC_EVEX_XD_KZ_B, /* 14629 */ IC_EVEX_XD_KZ_B, /* 14630 */ IC_EVEX_XD_KZ_B, /* 14631 */ IC_EVEX_W_KZ_B, /* 14632 */ IC_EVEX_W_KZ_B, /* 14633 */ IC_EVEX_W_XS_KZ_B, /* 14634 */ IC_EVEX_W_XS_KZ_B, /* 14635 */ IC_EVEX_W_XD_KZ_B, /* 14636 */ IC_EVEX_W_XD_KZ_B, /* 14637 */ IC_EVEX_W_XD_KZ_B, /* 14638 */ IC_EVEX_W_XD_KZ_B, /* 14639 */ IC_EVEX_OPSIZE_KZ_B, /* 14640 */ IC_EVEX_OPSIZE_KZ_B, /* 14641 */ IC_EVEX_OPSIZE_KZ_B, /* 14642 */ IC_EVEX_OPSIZE_KZ_B, /* 14643 */ IC_EVEX_OPSIZE_KZ_B, /* 14644 */ IC_EVEX_OPSIZE_KZ_B, /* 14645 */ IC_EVEX_OPSIZE_KZ_B, /* 14646 */ IC_EVEX_OPSIZE_KZ_B, /* 14647 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14648 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14649 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14650 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14651 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14652 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14653 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14654 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14655 */ IC_EVEX_KZ_B, /* 14656 */ IC_EVEX_KZ_B, /* 14657 */ IC_EVEX_XS_KZ_B, /* 14658 */ IC_EVEX_XS_KZ_B, /* 14659 */ IC_EVEX_XD_KZ_B, /* 14660 */ IC_EVEX_XD_KZ_B, /* 14661 */ IC_EVEX_XD_KZ_B, /* 14662 */ IC_EVEX_XD_KZ_B, /* 14663 */ IC_EVEX_W_KZ_B, /* 14664 */ IC_EVEX_W_KZ_B, /* 14665 */ IC_EVEX_W_XS_KZ_B, /* 14666 */ IC_EVEX_W_XS_KZ_B, /* 14667 */ IC_EVEX_W_XD_KZ_B, /* 14668 */ IC_EVEX_W_XD_KZ_B, /* 14669 */ IC_EVEX_W_XD_KZ_B, /* 14670 */ IC_EVEX_W_XD_KZ_B, /* 14671 */ IC_EVEX_OPSIZE_KZ_B, /* 14672 */ IC_EVEX_OPSIZE_KZ_B, /* 14673 */ IC_EVEX_OPSIZE_KZ_B, /* 14674 */ IC_EVEX_OPSIZE_KZ_B, /* 14675 */ IC_EVEX_OPSIZE_KZ_B, /* 14676 */ IC_EVEX_OPSIZE_KZ_B, /* 14677 */ IC_EVEX_OPSIZE_KZ_B, /* 14678 */ IC_EVEX_OPSIZE_KZ_B, /* 14679 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14680 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14681 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14682 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14683 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14684 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14685 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14686 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14687 */ IC_EVEX_KZ_B, /* 14688 */ IC_EVEX_KZ_B, /* 14689 */ IC_EVEX_XS_KZ_B, /* 14690 */ IC_EVEX_XS_KZ_B, /* 14691 */ IC_EVEX_XD_KZ_B, /* 14692 */ IC_EVEX_XD_KZ_B, /* 14693 */ IC_EVEX_XD_KZ_B, /* 14694 */ IC_EVEX_XD_KZ_B, /* 14695 */ IC_EVEX_W_KZ_B, /* 14696 */ IC_EVEX_W_KZ_B, /* 14697 */ IC_EVEX_W_XS_KZ_B, /* 14698 */ IC_EVEX_W_XS_KZ_B, /* 14699 */ IC_EVEX_W_XD_KZ_B, /* 14700 */ IC_EVEX_W_XD_KZ_B, /* 14701 */ IC_EVEX_W_XD_KZ_B, /* 14702 */ IC_EVEX_W_XD_KZ_B, /* 14703 */ IC_EVEX_OPSIZE_KZ_B, /* 14704 */ IC_EVEX_OPSIZE_KZ_B, /* 14705 */ IC_EVEX_OPSIZE_KZ_B, /* 14706 */ IC_EVEX_OPSIZE_KZ_B, /* 14707 */ IC_EVEX_OPSIZE_KZ_B, /* 14708 */ IC_EVEX_OPSIZE_KZ_B, /* 14709 */ IC_EVEX_OPSIZE_KZ_B, /* 14710 */ IC_EVEX_OPSIZE_KZ_B, /* 14711 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14712 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14713 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14714 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14715 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14716 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14717 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14718 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14719 */ IC_EVEX_KZ_B, /* 14720 */ IC_EVEX_KZ_B, /* 14721 */ IC_EVEX_XS_KZ_B, /* 14722 */ IC_EVEX_XS_KZ_B, /* 14723 */ IC_EVEX_XD_KZ_B, /* 14724 */ IC_EVEX_XD_KZ_B, /* 14725 */ IC_EVEX_XD_KZ_B, /* 14726 */ IC_EVEX_XD_KZ_B, /* 14727 */ IC_EVEX_W_KZ_B, /* 14728 */ IC_EVEX_W_KZ_B, /* 14729 */ IC_EVEX_W_XS_KZ_B, /* 14730 */ IC_EVEX_W_XS_KZ_B, /* 14731 */ IC_EVEX_W_XD_KZ_B, /* 14732 */ IC_EVEX_W_XD_KZ_B, /* 14733 */ IC_EVEX_W_XD_KZ_B, /* 14734 */ IC_EVEX_W_XD_KZ_B, /* 14735 */ IC_EVEX_OPSIZE_KZ_B, /* 14736 */ IC_EVEX_OPSIZE_KZ_B, /* 14737 */ IC_EVEX_OPSIZE_KZ_B, /* 14738 */ IC_EVEX_OPSIZE_KZ_B, /* 14739 */ IC_EVEX_OPSIZE_KZ_B, /* 14740 */ IC_EVEX_OPSIZE_KZ_B, /* 14741 */ IC_EVEX_OPSIZE_KZ_B, /* 14742 */ IC_EVEX_OPSIZE_KZ_B, /* 14743 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14744 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14745 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14746 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14747 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14748 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14749 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14750 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14751 */ IC_EVEX_KZ_B, /* 14752 */ IC_EVEX_KZ_B, /* 14753 */ IC_EVEX_XS_KZ_B, /* 14754 */ IC_EVEX_XS_KZ_B, /* 14755 */ IC_EVEX_XD_KZ_B, /* 14756 */ IC_EVEX_XD_KZ_B, /* 14757 */ IC_EVEX_XD_KZ_B, /* 14758 */ IC_EVEX_XD_KZ_B, /* 14759 */ IC_EVEX_W_KZ_B, /* 14760 */ IC_EVEX_W_KZ_B, /* 14761 */ IC_EVEX_W_XS_KZ_B, /* 14762 */ IC_EVEX_W_XS_KZ_B, /* 14763 */ IC_EVEX_W_XD_KZ_B, /* 14764 */ IC_EVEX_W_XD_KZ_B, /* 14765 */ IC_EVEX_W_XD_KZ_B, /* 14766 */ IC_EVEX_W_XD_KZ_B, /* 14767 */ IC_EVEX_OPSIZE_KZ_B, /* 14768 */ IC_EVEX_OPSIZE_KZ_B, /* 14769 */ IC_EVEX_OPSIZE_KZ_B, /* 14770 */ IC_EVEX_OPSIZE_KZ_B, /* 14771 */ IC_EVEX_OPSIZE_KZ_B, /* 14772 */ IC_EVEX_OPSIZE_KZ_B, /* 14773 */ IC_EVEX_OPSIZE_KZ_B, /* 14774 */ IC_EVEX_OPSIZE_KZ_B, /* 14775 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14776 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14777 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14778 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14779 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14780 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14781 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14782 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14783 */ IC_EVEX_KZ_B, /* 14784 */ IC_EVEX_KZ_B, /* 14785 */ IC_EVEX_XS_KZ_B, /* 14786 */ IC_EVEX_XS_KZ_B, /* 14787 */ IC_EVEX_XD_KZ_B, /* 14788 */ IC_EVEX_XD_KZ_B, /* 14789 */ IC_EVEX_XD_KZ_B, /* 14790 */ IC_EVEX_XD_KZ_B, /* 14791 */ IC_EVEX_W_KZ_B, /* 14792 */ IC_EVEX_W_KZ_B, /* 14793 */ IC_EVEX_W_XS_KZ_B, /* 14794 */ IC_EVEX_W_XS_KZ_B, /* 14795 */ IC_EVEX_W_XD_KZ_B, /* 14796 */ IC_EVEX_W_XD_KZ_B, /* 14797 */ IC_EVEX_W_XD_KZ_B, /* 14798 */ IC_EVEX_W_XD_KZ_B, /* 14799 */ IC_EVEX_OPSIZE_KZ_B, /* 14800 */ IC_EVEX_OPSIZE_KZ_B, /* 14801 */ IC_EVEX_OPSIZE_KZ_B, /* 14802 */ IC_EVEX_OPSIZE_KZ_B, /* 14803 */ IC_EVEX_OPSIZE_KZ_B, /* 14804 */ IC_EVEX_OPSIZE_KZ_B, /* 14805 */ IC_EVEX_OPSIZE_KZ_B, /* 14806 */ IC_EVEX_OPSIZE_KZ_B, /* 14807 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14808 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14809 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14810 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14811 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14812 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14813 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14814 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14815 */ IC_EVEX_KZ_B, /* 14816 */ IC_EVEX_KZ_B, /* 14817 */ IC_EVEX_XS_KZ_B, /* 14818 */ IC_EVEX_XS_KZ_B, /* 14819 */ IC_EVEX_XD_KZ_B, /* 14820 */ IC_EVEX_XD_KZ_B, /* 14821 */ IC_EVEX_XD_KZ_B, /* 14822 */ IC_EVEX_XD_KZ_B, /* 14823 */ IC_EVEX_W_KZ_B, /* 14824 */ IC_EVEX_W_KZ_B, /* 14825 */ IC_EVEX_W_XS_KZ_B, /* 14826 */ IC_EVEX_W_XS_KZ_B, /* 14827 */ IC_EVEX_W_XD_KZ_B, /* 14828 */ IC_EVEX_W_XD_KZ_B, /* 14829 */ IC_EVEX_W_XD_KZ_B, /* 14830 */ IC_EVEX_W_XD_KZ_B, /* 14831 */ IC_EVEX_OPSIZE_KZ_B, /* 14832 */ IC_EVEX_OPSIZE_KZ_B, /* 14833 */ IC_EVEX_OPSIZE_KZ_B, /* 14834 */ IC_EVEX_OPSIZE_KZ_B, /* 14835 */ IC_EVEX_OPSIZE_KZ_B, /* 14836 */ IC_EVEX_OPSIZE_KZ_B, /* 14837 */ IC_EVEX_OPSIZE_KZ_B, /* 14838 */ IC_EVEX_OPSIZE_KZ_B, /* 14839 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14840 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14841 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14842 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14843 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14844 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14845 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14846 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14847 */ IC, /* 14848 */ IC_64BIT, /* 14849 */ IC_XS, /* 14850 */ IC_64BIT_XS, /* 14851 */ IC_XD, /* 14852 */ IC_64BIT_XD, /* 14853 */ IC_XS, /* 14854 */ IC_64BIT_XS, /* 14855 */ IC, /* 14856 */ IC_64BIT_REXW, /* 14857 */ IC_XS, /* 14858 */ IC_64BIT_REXW_XS, /* 14859 */ IC_XD, /* 14860 */ IC_64BIT_REXW_XD, /* 14861 */ IC_XS, /* 14862 */ IC_64BIT_REXW_XS, /* 14863 */ IC_OPSIZE, /* 14864 */ IC_64BIT_OPSIZE, /* 14865 */ IC_XS_OPSIZE, /* 14866 */ IC_64BIT_XS_OPSIZE, /* 14867 */ IC_XD_OPSIZE, /* 14868 */ IC_64BIT_XD_OPSIZE, /* 14869 */ IC_XS_OPSIZE, /* 14870 */ IC_64BIT_XD_OPSIZE, /* 14871 */ IC_OPSIZE, /* 14872 */ IC_64BIT_REXW_OPSIZE, /* 14873 */ IC_XS_OPSIZE, /* 14874 */ IC_64BIT_REXW_XS, /* 14875 */ IC_XD_OPSIZE, /* 14876 */ IC_64BIT_REXW_XD, /* 14877 */ IC_XS_OPSIZE, /* 14878 */ IC_64BIT_REXW_XS, /* 14879 */ IC_ADSIZE, /* 14880 */ IC_64BIT_ADSIZE, /* 14881 */ IC_XS_ADSIZE, /* 14882 */ IC_64BIT_XS_ADSIZE, /* 14883 */ IC_XD_ADSIZE, /* 14884 */ IC_64BIT_XD_ADSIZE, /* 14885 */ IC_XS_ADSIZE, /* 14886 */ IC_64BIT_XD_ADSIZE, /* 14887 */ IC_ADSIZE, /* 14888 */ IC_64BIT_REXW_ADSIZE, /* 14889 */ IC_XS_ADSIZE, /* 14890 */ IC_64BIT_REXW_XS, /* 14891 */ IC_XD_ADSIZE, /* 14892 */ IC_64BIT_REXW_XD, /* 14893 */ IC_XS_ADSIZE, /* 14894 */ IC_64BIT_REXW_XS, /* 14895 */ IC_OPSIZE_ADSIZE, /* 14896 */ IC_64BIT_OPSIZE_ADSIZE, /* 14897 */ IC_XS_OPSIZE, /* 14898 */ IC_64BIT_XS_OPSIZE, /* 14899 */ IC_XD_OPSIZE, /* 14900 */ IC_64BIT_XD_OPSIZE, /* 14901 */ IC_XS_OPSIZE, /* 14902 */ IC_64BIT_XD_OPSIZE, /* 14903 */ IC_OPSIZE_ADSIZE, /* 14904 */ IC_64BIT_REXW_OPSIZE, /* 14905 */ IC_XS_OPSIZE, /* 14906 */ IC_64BIT_REXW_XS, /* 14907 */ IC_XD_OPSIZE, /* 14908 */ IC_64BIT_REXW_XD, /* 14909 */ IC_XS_OPSIZE, /* 14910 */ IC_64BIT_REXW_XS, /* 14911 */ IC_VEX, /* 14912 */ IC_VEX, /* 14913 */ IC_VEX_XS, /* 14914 */ IC_VEX_XS, /* 14915 */ IC_VEX_XD, /* 14916 */ IC_VEX_XD, /* 14917 */ IC_VEX_XD, /* 14918 */ IC_VEX_XD, /* 14919 */ IC_VEX_W, /* 14920 */ IC_VEX_W, /* 14921 */ IC_VEX_W_XS, /* 14922 */ IC_VEX_W_XS, /* 14923 */ IC_VEX_W_XD, /* 14924 */ IC_VEX_W_XD, /* 14925 */ IC_VEX_W_XD, /* 14926 */ IC_VEX_W_XD, /* 14927 */ IC_VEX_OPSIZE, /* 14928 */ IC_VEX_OPSIZE, /* 14929 */ IC_VEX_OPSIZE, /* 14930 */ IC_VEX_OPSIZE, /* 14931 */ IC_VEX_OPSIZE, /* 14932 */ IC_VEX_OPSIZE, /* 14933 */ IC_VEX_OPSIZE, /* 14934 */ IC_VEX_OPSIZE, /* 14935 */ IC_VEX_W_OPSIZE, /* 14936 */ IC_VEX_W_OPSIZE, /* 14937 */ IC_VEX_W_OPSIZE, /* 14938 */ IC_VEX_W_OPSIZE, /* 14939 */ IC_VEX_W_OPSIZE, /* 14940 */ IC_VEX_W_OPSIZE, /* 14941 */ IC_VEX_W_OPSIZE, /* 14942 */ IC_VEX_W_OPSIZE, /* 14943 */ IC_VEX, /* 14944 */ IC_VEX, /* 14945 */ IC_VEX_XS, /* 14946 */ IC_VEX_XS, /* 14947 */ IC_VEX_XD, /* 14948 */ IC_VEX_XD, /* 14949 */ IC_VEX_XD, /* 14950 */ IC_VEX_XD, /* 14951 */ IC_VEX_W, /* 14952 */ IC_VEX_W, /* 14953 */ IC_VEX_W_XS, /* 14954 */ IC_VEX_W_XS, /* 14955 */ IC_VEX_W_XD, /* 14956 */ IC_VEX_W_XD, /* 14957 */ IC_VEX_W_XD, /* 14958 */ IC_VEX_W_XD, /* 14959 */ IC_VEX_OPSIZE, /* 14960 */ IC_VEX_OPSIZE, /* 14961 */ IC_VEX_OPSIZE, /* 14962 */ IC_VEX_OPSIZE, /* 14963 */ IC_VEX_OPSIZE, /* 14964 */ IC_VEX_OPSIZE, /* 14965 */ IC_VEX_OPSIZE, /* 14966 */ IC_VEX_OPSIZE, /* 14967 */ IC_VEX_W_OPSIZE, /* 14968 */ IC_VEX_W_OPSIZE, /* 14969 */ IC_VEX_W_OPSIZE, /* 14970 */ IC_VEX_W_OPSIZE, /* 14971 */ IC_VEX_W_OPSIZE, /* 14972 */ IC_VEX_W_OPSIZE, /* 14973 */ IC_VEX_W_OPSIZE, /* 14974 */ IC_VEX_W_OPSIZE, /* 14975 */ IC_VEX_L, /* 14976 */ IC_VEX_L, /* 14977 */ IC_VEX_L_XS, /* 14978 */ IC_VEX_L_XS, /* 14979 */ IC_VEX_L_XD, /* 14980 */ IC_VEX_L_XD, /* 14981 */ IC_VEX_L_XD, /* 14982 */ IC_VEX_L_XD, /* 14983 */ IC_VEX_L_W, /* 14984 */ IC_VEX_L_W, /* 14985 */ IC_VEX_L_W_XS, /* 14986 */ IC_VEX_L_W_XS, /* 14987 */ IC_VEX_L_W_XD, /* 14988 */ IC_VEX_L_W_XD, /* 14989 */ IC_VEX_L_W_XD, /* 14990 */ IC_VEX_L_W_XD, /* 14991 */ IC_VEX_L_OPSIZE, /* 14992 */ IC_VEX_L_OPSIZE, /* 14993 */ IC_VEX_L_OPSIZE, /* 14994 */ IC_VEX_L_OPSIZE, /* 14995 */ IC_VEX_L_OPSIZE, /* 14996 */ IC_VEX_L_OPSIZE, /* 14997 */ IC_VEX_L_OPSIZE, /* 14998 */ IC_VEX_L_OPSIZE, /* 14999 */ IC_VEX_L_W_OPSIZE, /* 15000 */ IC_VEX_L_W_OPSIZE, /* 15001 */ IC_VEX_L_W_OPSIZE, /* 15002 */ IC_VEX_L_W_OPSIZE, /* 15003 */ IC_VEX_L_W_OPSIZE, /* 15004 */ IC_VEX_L_W_OPSIZE, /* 15005 */ IC_VEX_L_W_OPSIZE, /* 15006 */ IC_VEX_L_W_OPSIZE, /* 15007 */ IC_VEX_L, /* 15008 */ IC_VEX_L, /* 15009 */ IC_VEX_L_XS, /* 15010 */ IC_VEX_L_XS, /* 15011 */ IC_VEX_L_XD, /* 15012 */ IC_VEX_L_XD, /* 15013 */ IC_VEX_L_XD, /* 15014 */ IC_VEX_L_XD, /* 15015 */ IC_VEX_L_W, /* 15016 */ IC_VEX_L_W, /* 15017 */ IC_VEX_L_W_XS, /* 15018 */ IC_VEX_L_W_XS, /* 15019 */ IC_VEX_L_W_XD, /* 15020 */ IC_VEX_L_W_XD, /* 15021 */ IC_VEX_L_W_XD, /* 15022 */ IC_VEX_L_W_XD, /* 15023 */ IC_VEX_L_OPSIZE, /* 15024 */ IC_VEX_L_OPSIZE, /* 15025 */ IC_VEX_L_OPSIZE, /* 15026 */ IC_VEX_L_OPSIZE, /* 15027 */ IC_VEX_L_OPSIZE, /* 15028 */ IC_VEX_L_OPSIZE, /* 15029 */ IC_VEX_L_OPSIZE, /* 15030 */ IC_VEX_L_OPSIZE, /* 15031 */ IC_VEX_L_W_OPSIZE, /* 15032 */ IC_VEX_L_W_OPSIZE, /* 15033 */ IC_VEX_L_W_OPSIZE, /* 15034 */ IC_VEX_L_W_OPSIZE, /* 15035 */ IC_VEX_L_W_OPSIZE, /* 15036 */ IC_VEX_L_W_OPSIZE, /* 15037 */ IC_VEX_L_W_OPSIZE, /* 15038 */ IC_VEX_L_W_OPSIZE, /* 15039 */ IC_VEX_L, /* 15040 */ IC_VEX_L, /* 15041 */ IC_VEX_L_XS, /* 15042 */ IC_VEX_L_XS, /* 15043 */ IC_VEX_L_XD, /* 15044 */ IC_VEX_L_XD, /* 15045 */ IC_VEX_L_XD, /* 15046 */ IC_VEX_L_XD, /* 15047 */ IC_VEX_L_W, /* 15048 */ IC_VEX_L_W, /* 15049 */ IC_VEX_L_W_XS, /* 15050 */ IC_VEX_L_W_XS, /* 15051 */ IC_VEX_L_W_XD, /* 15052 */ IC_VEX_L_W_XD, /* 15053 */ IC_VEX_L_W_XD, /* 15054 */ IC_VEX_L_W_XD, /* 15055 */ IC_VEX_L_OPSIZE, /* 15056 */ IC_VEX_L_OPSIZE, /* 15057 */ IC_VEX_L_OPSIZE, /* 15058 */ IC_VEX_L_OPSIZE, /* 15059 */ IC_VEX_L_OPSIZE, /* 15060 */ IC_VEX_L_OPSIZE, /* 15061 */ IC_VEX_L_OPSIZE, /* 15062 */ IC_VEX_L_OPSIZE, /* 15063 */ IC_VEX_L_W_OPSIZE, /* 15064 */ IC_VEX_L_W_OPSIZE, /* 15065 */ IC_VEX_L_W_OPSIZE, /* 15066 */ IC_VEX_L_W_OPSIZE, /* 15067 */ IC_VEX_L_W_OPSIZE, /* 15068 */ IC_VEX_L_W_OPSIZE, /* 15069 */ IC_VEX_L_W_OPSIZE, /* 15070 */ IC_VEX_L_W_OPSIZE, /* 15071 */ IC_VEX_L, /* 15072 */ IC_VEX_L, /* 15073 */ IC_VEX_L_XS, /* 15074 */ IC_VEX_L_XS, /* 15075 */ IC_VEX_L_XD, /* 15076 */ IC_VEX_L_XD, /* 15077 */ IC_VEX_L_XD, /* 15078 */ IC_VEX_L_XD, /* 15079 */ IC_VEX_L_W, /* 15080 */ IC_VEX_L_W, /* 15081 */ IC_VEX_L_W_XS, /* 15082 */ IC_VEX_L_W_XS, /* 15083 */ IC_VEX_L_W_XD, /* 15084 */ IC_VEX_L_W_XD, /* 15085 */ IC_VEX_L_W_XD, /* 15086 */ IC_VEX_L_W_XD, /* 15087 */ IC_VEX_L_OPSIZE, /* 15088 */ IC_VEX_L_OPSIZE, /* 15089 */ IC_VEX_L_OPSIZE, /* 15090 */ IC_VEX_L_OPSIZE, /* 15091 */ IC_VEX_L_OPSIZE, /* 15092 */ IC_VEX_L_OPSIZE, /* 15093 */ IC_VEX_L_OPSIZE, /* 15094 */ IC_VEX_L_OPSIZE, /* 15095 */ IC_VEX_L_W_OPSIZE, /* 15096 */ IC_VEX_L_W_OPSIZE, /* 15097 */ IC_VEX_L_W_OPSIZE, /* 15098 */ IC_VEX_L_W_OPSIZE, /* 15099 */ IC_VEX_L_W_OPSIZE, /* 15100 */ IC_VEX_L_W_OPSIZE, /* 15101 */ IC_VEX_L_W_OPSIZE, /* 15102 */ IC_VEX_L_W_OPSIZE, /* 15103 */ IC_EVEX_L_KZ_B, /* 15104 */ IC_EVEX_L_KZ_B, /* 15105 */ IC_EVEX_L_XS_KZ_B, /* 15106 */ IC_EVEX_L_XS_KZ_B, /* 15107 */ IC_EVEX_L_XD_KZ_B, /* 15108 */ IC_EVEX_L_XD_KZ_B, /* 15109 */ IC_EVEX_L_XD_KZ_B, /* 15110 */ IC_EVEX_L_XD_KZ_B, /* 15111 */ IC_EVEX_L_W_KZ_B, /* 15112 */ IC_EVEX_L_W_KZ_B, /* 15113 */ IC_EVEX_L_W_XS_KZ_B, /* 15114 */ IC_EVEX_L_W_XS_KZ_B, /* 15115 */ IC_EVEX_L_W_XD_KZ_B, /* 15116 */ IC_EVEX_L_W_XD_KZ_B, /* 15117 */ IC_EVEX_L_W_XD_KZ_B, /* 15118 */ IC_EVEX_L_W_XD_KZ_B, /* 15119 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15120 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15121 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15122 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15123 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15124 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15125 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15126 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15127 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15128 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15129 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15130 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15131 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15132 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15133 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15134 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15135 */ IC_EVEX_L_KZ_B, /* 15136 */ IC_EVEX_L_KZ_B, /* 15137 */ IC_EVEX_L_XS_KZ_B, /* 15138 */ IC_EVEX_L_XS_KZ_B, /* 15139 */ IC_EVEX_L_XD_KZ_B, /* 15140 */ IC_EVEX_L_XD_KZ_B, /* 15141 */ IC_EVEX_L_XD_KZ_B, /* 15142 */ IC_EVEX_L_XD_KZ_B, /* 15143 */ IC_EVEX_L_W_KZ_B, /* 15144 */ IC_EVEX_L_W_KZ_B, /* 15145 */ IC_EVEX_L_W_XS_KZ_B, /* 15146 */ IC_EVEX_L_W_XS_KZ_B, /* 15147 */ IC_EVEX_L_W_XD_KZ_B, /* 15148 */ IC_EVEX_L_W_XD_KZ_B, /* 15149 */ IC_EVEX_L_W_XD_KZ_B, /* 15150 */ IC_EVEX_L_W_XD_KZ_B, /* 15151 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15152 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15153 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15154 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15155 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15156 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15157 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15158 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15159 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15160 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15161 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15162 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15163 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15164 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15165 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15166 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15167 */ IC_EVEX_L_KZ_B, /* 15168 */ IC_EVEX_L_KZ_B, /* 15169 */ IC_EVEX_L_XS_KZ_B, /* 15170 */ IC_EVEX_L_XS_KZ_B, /* 15171 */ IC_EVEX_L_XD_KZ_B, /* 15172 */ IC_EVEX_L_XD_KZ_B, /* 15173 */ IC_EVEX_L_XD_KZ_B, /* 15174 */ IC_EVEX_L_XD_KZ_B, /* 15175 */ IC_EVEX_L_W_KZ_B, /* 15176 */ IC_EVEX_L_W_KZ_B, /* 15177 */ IC_EVEX_L_W_XS_KZ_B, /* 15178 */ IC_EVEX_L_W_XS_KZ_B, /* 15179 */ IC_EVEX_L_W_XD_KZ_B, /* 15180 */ IC_EVEX_L_W_XD_KZ_B, /* 15181 */ IC_EVEX_L_W_XD_KZ_B, /* 15182 */ IC_EVEX_L_W_XD_KZ_B, /* 15183 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15184 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15185 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15186 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15187 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15188 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15189 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15190 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15191 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15192 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15193 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15194 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15195 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15196 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15197 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15198 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15199 */ IC_EVEX_L_KZ_B, /* 15200 */ IC_EVEX_L_KZ_B, /* 15201 */ IC_EVEX_L_XS_KZ_B, /* 15202 */ IC_EVEX_L_XS_KZ_B, /* 15203 */ IC_EVEX_L_XD_KZ_B, /* 15204 */ IC_EVEX_L_XD_KZ_B, /* 15205 */ IC_EVEX_L_XD_KZ_B, /* 15206 */ IC_EVEX_L_XD_KZ_B, /* 15207 */ IC_EVEX_L_W_KZ_B, /* 15208 */ IC_EVEX_L_W_KZ_B, /* 15209 */ IC_EVEX_L_W_XS_KZ_B, /* 15210 */ IC_EVEX_L_W_XS_KZ_B, /* 15211 */ IC_EVEX_L_W_XD_KZ_B, /* 15212 */ IC_EVEX_L_W_XD_KZ_B, /* 15213 */ IC_EVEX_L_W_XD_KZ_B, /* 15214 */ IC_EVEX_L_W_XD_KZ_B, /* 15215 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15216 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15217 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15218 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15219 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15220 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15221 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15222 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15223 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15224 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15225 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15226 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15227 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15228 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15229 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15230 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15231 */ IC_EVEX_L_KZ_B, /* 15232 */ IC_EVEX_L_KZ_B, /* 15233 */ IC_EVEX_L_XS_KZ_B, /* 15234 */ IC_EVEX_L_XS_KZ_B, /* 15235 */ IC_EVEX_L_XD_KZ_B, /* 15236 */ IC_EVEX_L_XD_KZ_B, /* 15237 */ IC_EVEX_L_XD_KZ_B, /* 15238 */ IC_EVEX_L_XD_KZ_B, /* 15239 */ IC_EVEX_L_W_KZ_B, /* 15240 */ IC_EVEX_L_W_KZ_B, /* 15241 */ IC_EVEX_L_W_XS_KZ_B, /* 15242 */ IC_EVEX_L_W_XS_KZ_B, /* 15243 */ IC_EVEX_L_W_XD_KZ_B, /* 15244 */ IC_EVEX_L_W_XD_KZ_B, /* 15245 */ IC_EVEX_L_W_XD_KZ_B, /* 15246 */ IC_EVEX_L_W_XD_KZ_B, /* 15247 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15248 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15249 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15250 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15251 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15252 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15253 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15254 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15255 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15256 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15257 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15258 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15259 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15260 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15261 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15262 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15263 */ IC_EVEX_L_KZ_B, /* 15264 */ IC_EVEX_L_KZ_B, /* 15265 */ IC_EVEX_L_XS_KZ_B, /* 15266 */ IC_EVEX_L_XS_KZ_B, /* 15267 */ IC_EVEX_L_XD_KZ_B, /* 15268 */ IC_EVEX_L_XD_KZ_B, /* 15269 */ IC_EVEX_L_XD_KZ_B, /* 15270 */ IC_EVEX_L_XD_KZ_B, /* 15271 */ IC_EVEX_L_W_KZ_B, /* 15272 */ IC_EVEX_L_W_KZ_B, /* 15273 */ IC_EVEX_L_W_XS_KZ_B, /* 15274 */ IC_EVEX_L_W_XS_KZ_B, /* 15275 */ IC_EVEX_L_W_XD_KZ_B, /* 15276 */ IC_EVEX_L_W_XD_KZ_B, /* 15277 */ IC_EVEX_L_W_XD_KZ_B, /* 15278 */ IC_EVEX_L_W_XD_KZ_B, /* 15279 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15280 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15281 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15282 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15283 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15284 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15285 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15286 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15287 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15288 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15289 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15290 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15291 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15292 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15293 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15294 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15295 */ IC_EVEX_L_KZ_B, /* 15296 */ IC_EVEX_L_KZ_B, /* 15297 */ IC_EVEX_L_XS_KZ_B, /* 15298 */ IC_EVEX_L_XS_KZ_B, /* 15299 */ IC_EVEX_L_XD_KZ_B, /* 15300 */ IC_EVEX_L_XD_KZ_B, /* 15301 */ IC_EVEX_L_XD_KZ_B, /* 15302 */ IC_EVEX_L_XD_KZ_B, /* 15303 */ IC_EVEX_L_W_KZ_B, /* 15304 */ IC_EVEX_L_W_KZ_B, /* 15305 */ IC_EVEX_L_W_XS_KZ_B, /* 15306 */ IC_EVEX_L_W_XS_KZ_B, /* 15307 */ IC_EVEX_L_W_XD_KZ_B, /* 15308 */ IC_EVEX_L_W_XD_KZ_B, /* 15309 */ IC_EVEX_L_W_XD_KZ_B, /* 15310 */ IC_EVEX_L_W_XD_KZ_B, /* 15311 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15312 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15313 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15314 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15315 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15316 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15317 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15318 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15319 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15320 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15321 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15322 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15323 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15324 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15325 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15326 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15327 */ IC_EVEX_L_KZ_B, /* 15328 */ IC_EVEX_L_KZ_B, /* 15329 */ IC_EVEX_L_XS_KZ_B, /* 15330 */ IC_EVEX_L_XS_KZ_B, /* 15331 */ IC_EVEX_L_XD_KZ_B, /* 15332 */ IC_EVEX_L_XD_KZ_B, /* 15333 */ IC_EVEX_L_XD_KZ_B, /* 15334 */ IC_EVEX_L_XD_KZ_B, /* 15335 */ IC_EVEX_L_W_KZ_B, /* 15336 */ IC_EVEX_L_W_KZ_B, /* 15337 */ IC_EVEX_L_W_XS_KZ_B, /* 15338 */ IC_EVEX_L_W_XS_KZ_B, /* 15339 */ IC_EVEX_L_W_XD_KZ_B, /* 15340 */ IC_EVEX_L_W_XD_KZ_B, /* 15341 */ IC_EVEX_L_W_XD_KZ_B, /* 15342 */ IC_EVEX_L_W_XD_KZ_B, /* 15343 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15344 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15345 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15346 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15347 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15348 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15349 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15350 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15351 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15352 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15353 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15354 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15355 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15356 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15357 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15358 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15359 */ IC, /* 15360 */ IC_64BIT, /* 15361 */ IC_XS, /* 15362 */ IC_64BIT_XS, /* 15363 */ IC_XD, /* 15364 */ IC_64BIT_XD, /* 15365 */ IC_XS, /* 15366 */ IC_64BIT_XS, /* 15367 */ IC, /* 15368 */ IC_64BIT_REXW, /* 15369 */ IC_XS, /* 15370 */ IC_64BIT_REXW_XS, /* 15371 */ IC_XD, /* 15372 */ IC_64BIT_REXW_XD, /* 15373 */ IC_XS, /* 15374 */ IC_64BIT_REXW_XS, /* 15375 */ IC_OPSIZE, /* 15376 */ IC_64BIT_OPSIZE, /* 15377 */ IC_XS_OPSIZE, /* 15378 */ IC_64BIT_XS_OPSIZE, /* 15379 */ IC_XD_OPSIZE, /* 15380 */ IC_64BIT_XD_OPSIZE, /* 15381 */ IC_XS_OPSIZE, /* 15382 */ IC_64BIT_XD_OPSIZE, /* 15383 */ IC_OPSIZE, /* 15384 */ IC_64BIT_REXW_OPSIZE, /* 15385 */ IC_XS_OPSIZE, /* 15386 */ IC_64BIT_REXW_XS, /* 15387 */ IC_XD_OPSIZE, /* 15388 */ IC_64BIT_REXW_XD, /* 15389 */ IC_XS_OPSIZE, /* 15390 */ IC_64BIT_REXW_XS, /* 15391 */ IC_ADSIZE, /* 15392 */ IC_64BIT_ADSIZE, /* 15393 */ IC_XS_ADSIZE, /* 15394 */ IC_64BIT_XS_ADSIZE, /* 15395 */ IC_XD_ADSIZE, /* 15396 */ IC_64BIT_XD_ADSIZE, /* 15397 */ IC_XS_ADSIZE, /* 15398 */ IC_64BIT_XD_ADSIZE, /* 15399 */ IC_ADSIZE, /* 15400 */ IC_64BIT_REXW_ADSIZE, /* 15401 */ IC_XS_ADSIZE, /* 15402 */ IC_64BIT_REXW_XS, /* 15403 */ IC_XD_ADSIZE, /* 15404 */ IC_64BIT_REXW_XD, /* 15405 */ IC_XS_ADSIZE, /* 15406 */ IC_64BIT_REXW_XS, /* 15407 */ IC_OPSIZE_ADSIZE, /* 15408 */ IC_64BIT_OPSIZE_ADSIZE, /* 15409 */ IC_XS_OPSIZE, /* 15410 */ IC_64BIT_XS_OPSIZE, /* 15411 */ IC_XD_OPSIZE, /* 15412 */ IC_64BIT_XD_OPSIZE, /* 15413 */ IC_XS_OPSIZE, /* 15414 */ IC_64BIT_XD_OPSIZE, /* 15415 */ IC_OPSIZE_ADSIZE, /* 15416 */ IC_64BIT_REXW_OPSIZE, /* 15417 */ IC_XS_OPSIZE, /* 15418 */ IC_64BIT_REXW_XS, /* 15419 */ IC_XD_OPSIZE, /* 15420 */ IC_64BIT_REXW_XD, /* 15421 */ IC_XS_OPSIZE, /* 15422 */ IC_64BIT_REXW_XS, /* 15423 */ IC_VEX, /* 15424 */ IC_VEX, /* 15425 */ IC_VEX_XS, /* 15426 */ IC_VEX_XS, /* 15427 */ IC_VEX_XD, /* 15428 */ IC_VEX_XD, /* 15429 */ IC_VEX_XD, /* 15430 */ IC_VEX_XD, /* 15431 */ IC_VEX_W, /* 15432 */ IC_VEX_W, /* 15433 */ IC_VEX_W_XS, /* 15434 */ IC_VEX_W_XS, /* 15435 */ IC_VEX_W_XD, /* 15436 */ IC_VEX_W_XD, /* 15437 */ IC_VEX_W_XD, /* 15438 */ IC_VEX_W_XD, /* 15439 */ IC_VEX_OPSIZE, /* 15440 */ IC_VEX_OPSIZE, /* 15441 */ IC_VEX_OPSIZE, /* 15442 */ IC_VEX_OPSIZE, /* 15443 */ IC_VEX_OPSIZE, /* 15444 */ IC_VEX_OPSIZE, /* 15445 */ IC_VEX_OPSIZE, /* 15446 */ IC_VEX_OPSIZE, /* 15447 */ IC_VEX_W_OPSIZE, /* 15448 */ IC_VEX_W_OPSIZE, /* 15449 */ IC_VEX_W_OPSIZE, /* 15450 */ IC_VEX_W_OPSIZE, /* 15451 */ IC_VEX_W_OPSIZE, /* 15452 */ IC_VEX_W_OPSIZE, /* 15453 */ IC_VEX_W_OPSIZE, /* 15454 */ IC_VEX_W_OPSIZE, /* 15455 */ IC_VEX, /* 15456 */ IC_VEX, /* 15457 */ IC_VEX_XS, /* 15458 */ IC_VEX_XS, /* 15459 */ IC_VEX_XD, /* 15460 */ IC_VEX_XD, /* 15461 */ IC_VEX_XD, /* 15462 */ IC_VEX_XD, /* 15463 */ IC_VEX_W, /* 15464 */ IC_VEX_W, /* 15465 */ IC_VEX_W_XS, /* 15466 */ IC_VEX_W_XS, /* 15467 */ IC_VEX_W_XD, /* 15468 */ IC_VEX_W_XD, /* 15469 */ IC_VEX_W_XD, /* 15470 */ IC_VEX_W_XD, /* 15471 */ IC_VEX_OPSIZE, /* 15472 */ IC_VEX_OPSIZE, /* 15473 */ IC_VEX_OPSIZE, /* 15474 */ IC_VEX_OPSIZE, /* 15475 */ IC_VEX_OPSIZE, /* 15476 */ IC_VEX_OPSIZE, /* 15477 */ IC_VEX_OPSIZE, /* 15478 */ IC_VEX_OPSIZE, /* 15479 */ IC_VEX_W_OPSIZE, /* 15480 */ IC_VEX_W_OPSIZE, /* 15481 */ IC_VEX_W_OPSIZE, /* 15482 */ IC_VEX_W_OPSIZE, /* 15483 */ IC_VEX_W_OPSIZE, /* 15484 */ IC_VEX_W_OPSIZE, /* 15485 */ IC_VEX_W_OPSIZE, /* 15486 */ IC_VEX_W_OPSIZE, /* 15487 */ IC_VEX_L, /* 15488 */ IC_VEX_L, /* 15489 */ IC_VEX_L_XS, /* 15490 */ IC_VEX_L_XS, /* 15491 */ IC_VEX_L_XD, /* 15492 */ IC_VEX_L_XD, /* 15493 */ IC_VEX_L_XD, /* 15494 */ IC_VEX_L_XD, /* 15495 */ IC_VEX_L_W, /* 15496 */ IC_VEX_L_W, /* 15497 */ IC_VEX_L_W_XS, /* 15498 */ IC_VEX_L_W_XS, /* 15499 */ IC_VEX_L_W_XD, /* 15500 */ IC_VEX_L_W_XD, /* 15501 */ IC_VEX_L_W_XD, /* 15502 */ IC_VEX_L_W_XD, /* 15503 */ IC_VEX_L_OPSIZE, /* 15504 */ IC_VEX_L_OPSIZE, /* 15505 */ IC_VEX_L_OPSIZE, /* 15506 */ IC_VEX_L_OPSIZE, /* 15507 */ IC_VEX_L_OPSIZE, /* 15508 */ IC_VEX_L_OPSIZE, /* 15509 */ IC_VEX_L_OPSIZE, /* 15510 */ IC_VEX_L_OPSIZE, /* 15511 */ IC_VEX_L_W_OPSIZE, /* 15512 */ IC_VEX_L_W_OPSIZE, /* 15513 */ IC_VEX_L_W_OPSIZE, /* 15514 */ IC_VEX_L_W_OPSIZE, /* 15515 */ IC_VEX_L_W_OPSIZE, /* 15516 */ IC_VEX_L_W_OPSIZE, /* 15517 */ IC_VEX_L_W_OPSIZE, /* 15518 */ IC_VEX_L_W_OPSIZE, /* 15519 */ IC_VEX_L, /* 15520 */ IC_VEX_L, /* 15521 */ IC_VEX_L_XS, /* 15522 */ IC_VEX_L_XS, /* 15523 */ IC_VEX_L_XD, /* 15524 */ IC_VEX_L_XD, /* 15525 */ IC_VEX_L_XD, /* 15526 */ IC_VEX_L_XD, /* 15527 */ IC_VEX_L_W, /* 15528 */ IC_VEX_L_W, /* 15529 */ IC_VEX_L_W_XS, /* 15530 */ IC_VEX_L_W_XS, /* 15531 */ IC_VEX_L_W_XD, /* 15532 */ IC_VEX_L_W_XD, /* 15533 */ IC_VEX_L_W_XD, /* 15534 */ IC_VEX_L_W_XD, /* 15535 */ IC_VEX_L_OPSIZE, /* 15536 */ IC_VEX_L_OPSIZE, /* 15537 */ IC_VEX_L_OPSIZE, /* 15538 */ IC_VEX_L_OPSIZE, /* 15539 */ IC_VEX_L_OPSIZE, /* 15540 */ IC_VEX_L_OPSIZE, /* 15541 */ IC_VEX_L_OPSIZE, /* 15542 */ IC_VEX_L_OPSIZE, /* 15543 */ IC_VEX_L_W_OPSIZE, /* 15544 */ IC_VEX_L_W_OPSIZE, /* 15545 */ IC_VEX_L_W_OPSIZE, /* 15546 */ IC_VEX_L_W_OPSIZE, /* 15547 */ IC_VEX_L_W_OPSIZE, /* 15548 */ IC_VEX_L_W_OPSIZE, /* 15549 */ IC_VEX_L_W_OPSIZE, /* 15550 */ IC_VEX_L_W_OPSIZE, /* 15551 */ IC_VEX_L, /* 15552 */ IC_VEX_L, /* 15553 */ IC_VEX_L_XS, /* 15554 */ IC_VEX_L_XS, /* 15555 */ IC_VEX_L_XD, /* 15556 */ IC_VEX_L_XD, /* 15557 */ IC_VEX_L_XD, /* 15558 */ IC_VEX_L_XD, /* 15559 */ IC_VEX_L_W, /* 15560 */ IC_VEX_L_W, /* 15561 */ IC_VEX_L_W_XS, /* 15562 */ IC_VEX_L_W_XS, /* 15563 */ IC_VEX_L_W_XD, /* 15564 */ IC_VEX_L_W_XD, /* 15565 */ IC_VEX_L_W_XD, /* 15566 */ IC_VEX_L_W_XD, /* 15567 */ IC_VEX_L_OPSIZE, /* 15568 */ IC_VEX_L_OPSIZE, /* 15569 */ IC_VEX_L_OPSIZE, /* 15570 */ IC_VEX_L_OPSIZE, /* 15571 */ IC_VEX_L_OPSIZE, /* 15572 */ IC_VEX_L_OPSIZE, /* 15573 */ IC_VEX_L_OPSIZE, /* 15574 */ IC_VEX_L_OPSIZE, /* 15575 */ IC_VEX_L_W_OPSIZE, /* 15576 */ IC_VEX_L_W_OPSIZE, /* 15577 */ IC_VEX_L_W_OPSIZE, /* 15578 */ IC_VEX_L_W_OPSIZE, /* 15579 */ IC_VEX_L_W_OPSIZE, /* 15580 */ IC_VEX_L_W_OPSIZE, /* 15581 */ IC_VEX_L_W_OPSIZE, /* 15582 */ IC_VEX_L_W_OPSIZE, /* 15583 */ IC_VEX_L, /* 15584 */ IC_VEX_L, /* 15585 */ IC_VEX_L_XS, /* 15586 */ IC_VEX_L_XS, /* 15587 */ IC_VEX_L_XD, /* 15588 */ IC_VEX_L_XD, /* 15589 */ IC_VEX_L_XD, /* 15590 */ IC_VEX_L_XD, /* 15591 */ IC_VEX_L_W, /* 15592 */ IC_VEX_L_W, /* 15593 */ IC_VEX_L_W_XS, /* 15594 */ IC_VEX_L_W_XS, /* 15595 */ IC_VEX_L_W_XD, /* 15596 */ IC_VEX_L_W_XD, /* 15597 */ IC_VEX_L_W_XD, /* 15598 */ IC_VEX_L_W_XD, /* 15599 */ IC_VEX_L_OPSIZE, /* 15600 */ IC_VEX_L_OPSIZE, /* 15601 */ IC_VEX_L_OPSIZE, /* 15602 */ IC_VEX_L_OPSIZE, /* 15603 */ IC_VEX_L_OPSIZE, /* 15604 */ IC_VEX_L_OPSIZE, /* 15605 */ IC_VEX_L_OPSIZE, /* 15606 */ IC_VEX_L_OPSIZE, /* 15607 */ IC_VEX_L_W_OPSIZE, /* 15608 */ IC_VEX_L_W_OPSIZE, /* 15609 */ IC_VEX_L_W_OPSIZE, /* 15610 */ IC_VEX_L_W_OPSIZE, /* 15611 */ IC_VEX_L_W_OPSIZE, /* 15612 */ IC_VEX_L_W_OPSIZE, /* 15613 */ IC_VEX_L_W_OPSIZE, /* 15614 */ IC_VEX_L_W_OPSIZE, /* 15615 */ IC_EVEX_L2_KZ_B, /* 15616 */ IC_EVEX_L2_KZ_B, /* 15617 */ IC_EVEX_L2_XS_KZ_B, /* 15618 */ IC_EVEX_L2_XS_KZ_B, /* 15619 */ IC_EVEX_L2_XD_KZ_B, /* 15620 */ IC_EVEX_L2_XD_KZ_B, /* 15621 */ IC_EVEX_L2_XD_KZ_B, /* 15622 */ IC_EVEX_L2_XD_KZ_B, /* 15623 */ IC_EVEX_L2_W_KZ_B, /* 15624 */ IC_EVEX_L2_W_KZ_B, /* 15625 */ IC_EVEX_L2_W_XS_KZ_B, /* 15626 */ IC_EVEX_L2_W_XS_KZ_B, /* 15627 */ IC_EVEX_L2_W_XD_KZ_B, /* 15628 */ IC_EVEX_L2_W_XD_KZ_B, /* 15629 */ IC_EVEX_L2_W_XD_KZ_B, /* 15630 */ IC_EVEX_L2_W_XD_KZ_B, /* 15631 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15632 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15633 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15634 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15635 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15636 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15637 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15638 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15639 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15640 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15641 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15642 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15643 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15644 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15645 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15646 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15647 */ IC_EVEX_L2_KZ_B, /* 15648 */ IC_EVEX_L2_KZ_B, /* 15649 */ IC_EVEX_L2_XS_KZ_B, /* 15650 */ IC_EVEX_L2_XS_KZ_B, /* 15651 */ IC_EVEX_L2_XD_KZ_B, /* 15652 */ IC_EVEX_L2_XD_KZ_B, /* 15653 */ IC_EVEX_L2_XD_KZ_B, /* 15654 */ IC_EVEX_L2_XD_KZ_B, /* 15655 */ IC_EVEX_L2_W_KZ_B, /* 15656 */ IC_EVEX_L2_W_KZ_B, /* 15657 */ IC_EVEX_L2_W_XS_KZ_B, /* 15658 */ IC_EVEX_L2_W_XS_KZ_B, /* 15659 */ IC_EVEX_L2_W_XD_KZ_B, /* 15660 */ IC_EVEX_L2_W_XD_KZ_B, /* 15661 */ IC_EVEX_L2_W_XD_KZ_B, /* 15662 */ IC_EVEX_L2_W_XD_KZ_B, /* 15663 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15664 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15665 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15666 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15667 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15668 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15669 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15670 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15671 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15672 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15673 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15674 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15675 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15676 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15677 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15678 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15679 */ IC_EVEX_L2_KZ_B, /* 15680 */ IC_EVEX_L2_KZ_B, /* 15681 */ IC_EVEX_L2_XS_KZ_B, /* 15682 */ IC_EVEX_L2_XS_KZ_B, /* 15683 */ IC_EVEX_L2_XD_KZ_B, /* 15684 */ IC_EVEX_L2_XD_KZ_B, /* 15685 */ IC_EVEX_L2_XD_KZ_B, /* 15686 */ IC_EVEX_L2_XD_KZ_B, /* 15687 */ IC_EVEX_L2_W_KZ_B, /* 15688 */ IC_EVEX_L2_W_KZ_B, /* 15689 */ IC_EVEX_L2_W_XS_KZ_B, /* 15690 */ IC_EVEX_L2_W_XS_KZ_B, /* 15691 */ IC_EVEX_L2_W_XD_KZ_B, /* 15692 */ IC_EVEX_L2_W_XD_KZ_B, /* 15693 */ IC_EVEX_L2_W_XD_KZ_B, /* 15694 */ IC_EVEX_L2_W_XD_KZ_B, /* 15695 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15696 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15697 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15698 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15699 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15700 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15701 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15702 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15703 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15704 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15705 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15706 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15707 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15708 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15709 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15710 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15711 */ IC_EVEX_L2_KZ_B, /* 15712 */ IC_EVEX_L2_KZ_B, /* 15713 */ IC_EVEX_L2_XS_KZ_B, /* 15714 */ IC_EVEX_L2_XS_KZ_B, /* 15715 */ IC_EVEX_L2_XD_KZ_B, /* 15716 */ IC_EVEX_L2_XD_KZ_B, /* 15717 */ IC_EVEX_L2_XD_KZ_B, /* 15718 */ IC_EVEX_L2_XD_KZ_B, /* 15719 */ IC_EVEX_L2_W_KZ_B, /* 15720 */ IC_EVEX_L2_W_KZ_B, /* 15721 */ IC_EVEX_L2_W_XS_KZ_B, /* 15722 */ IC_EVEX_L2_W_XS_KZ_B, /* 15723 */ IC_EVEX_L2_W_XD_KZ_B, /* 15724 */ IC_EVEX_L2_W_XD_KZ_B, /* 15725 */ IC_EVEX_L2_W_XD_KZ_B, /* 15726 */ IC_EVEX_L2_W_XD_KZ_B, /* 15727 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15728 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15729 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15730 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15731 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15732 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15733 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15734 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15735 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15736 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15737 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15738 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15739 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15740 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15741 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15742 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15743 */ IC_EVEX_L2_KZ_B, /* 15744 */ IC_EVEX_L2_KZ_B, /* 15745 */ IC_EVEX_L2_XS_KZ_B, /* 15746 */ IC_EVEX_L2_XS_KZ_B, /* 15747 */ IC_EVEX_L2_XD_KZ_B, /* 15748 */ IC_EVEX_L2_XD_KZ_B, /* 15749 */ IC_EVEX_L2_XD_KZ_B, /* 15750 */ IC_EVEX_L2_XD_KZ_B, /* 15751 */ IC_EVEX_L2_W_KZ_B, /* 15752 */ IC_EVEX_L2_W_KZ_B, /* 15753 */ IC_EVEX_L2_W_XS_KZ_B, /* 15754 */ IC_EVEX_L2_W_XS_KZ_B, /* 15755 */ IC_EVEX_L2_W_XD_KZ_B, /* 15756 */ IC_EVEX_L2_W_XD_KZ_B, /* 15757 */ IC_EVEX_L2_W_XD_KZ_B, /* 15758 */ IC_EVEX_L2_W_XD_KZ_B, /* 15759 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15760 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15761 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15762 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15763 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15764 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15765 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15766 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15767 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15768 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15769 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15770 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15771 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15772 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15773 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15774 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15775 */ IC_EVEX_L2_KZ_B, /* 15776 */ IC_EVEX_L2_KZ_B, /* 15777 */ IC_EVEX_L2_XS_KZ_B, /* 15778 */ IC_EVEX_L2_XS_KZ_B, /* 15779 */ IC_EVEX_L2_XD_KZ_B, /* 15780 */ IC_EVEX_L2_XD_KZ_B, /* 15781 */ IC_EVEX_L2_XD_KZ_B, /* 15782 */ IC_EVEX_L2_XD_KZ_B, /* 15783 */ IC_EVEX_L2_W_KZ_B, /* 15784 */ IC_EVEX_L2_W_KZ_B, /* 15785 */ IC_EVEX_L2_W_XS_KZ_B, /* 15786 */ IC_EVEX_L2_W_XS_KZ_B, /* 15787 */ IC_EVEX_L2_W_XD_KZ_B, /* 15788 */ IC_EVEX_L2_W_XD_KZ_B, /* 15789 */ IC_EVEX_L2_W_XD_KZ_B, /* 15790 */ IC_EVEX_L2_W_XD_KZ_B, /* 15791 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15792 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15793 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15794 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15795 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15796 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15797 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15798 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15799 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15800 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15801 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15802 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15803 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15804 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15805 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15806 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15807 */ IC_EVEX_L2_KZ_B, /* 15808 */ IC_EVEX_L2_KZ_B, /* 15809 */ IC_EVEX_L2_XS_KZ_B, /* 15810 */ IC_EVEX_L2_XS_KZ_B, /* 15811 */ IC_EVEX_L2_XD_KZ_B, /* 15812 */ IC_EVEX_L2_XD_KZ_B, /* 15813 */ IC_EVEX_L2_XD_KZ_B, /* 15814 */ IC_EVEX_L2_XD_KZ_B, /* 15815 */ IC_EVEX_L2_W_KZ_B, /* 15816 */ IC_EVEX_L2_W_KZ_B, /* 15817 */ IC_EVEX_L2_W_XS_KZ_B, /* 15818 */ IC_EVEX_L2_W_XS_KZ_B, /* 15819 */ IC_EVEX_L2_W_XD_KZ_B, /* 15820 */ IC_EVEX_L2_W_XD_KZ_B, /* 15821 */ IC_EVEX_L2_W_XD_KZ_B, /* 15822 */ IC_EVEX_L2_W_XD_KZ_B, /* 15823 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15824 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15825 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15826 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15827 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15828 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15829 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15830 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15831 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15832 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15833 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15834 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15835 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15836 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15837 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15838 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15839 */ IC_EVEX_L2_KZ_B, /* 15840 */ IC_EVEX_L2_KZ_B, /* 15841 */ IC_EVEX_L2_XS_KZ_B, /* 15842 */ IC_EVEX_L2_XS_KZ_B, /* 15843 */ IC_EVEX_L2_XD_KZ_B, /* 15844 */ IC_EVEX_L2_XD_KZ_B, /* 15845 */ IC_EVEX_L2_XD_KZ_B, /* 15846 */ IC_EVEX_L2_XD_KZ_B, /* 15847 */ IC_EVEX_L2_W_KZ_B, /* 15848 */ IC_EVEX_L2_W_KZ_B, /* 15849 */ IC_EVEX_L2_W_XS_KZ_B, /* 15850 */ IC_EVEX_L2_W_XS_KZ_B, /* 15851 */ IC_EVEX_L2_W_XD_KZ_B, /* 15852 */ IC_EVEX_L2_W_XD_KZ_B, /* 15853 */ IC_EVEX_L2_W_XD_KZ_B, /* 15854 */ IC_EVEX_L2_W_XD_KZ_B, /* 15855 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15856 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15857 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15858 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15859 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15860 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15861 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15862 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15863 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15864 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15865 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15866 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15867 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15868 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15869 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15870 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15871 */ IC, /* 15872 */ IC_64BIT, /* 15873 */ IC_XS, /* 15874 */ IC_64BIT_XS, /* 15875 */ IC_XD, /* 15876 */ IC_64BIT_XD, /* 15877 */ IC_XS, /* 15878 */ IC_64BIT_XS, /* 15879 */ IC, /* 15880 */ IC_64BIT_REXW, /* 15881 */ IC_XS, /* 15882 */ IC_64BIT_REXW_XS, /* 15883 */ IC_XD, /* 15884 */ IC_64BIT_REXW_XD, /* 15885 */ IC_XS, /* 15886 */ IC_64BIT_REXW_XS, /* 15887 */ IC_OPSIZE, /* 15888 */ IC_64BIT_OPSIZE, /* 15889 */ IC_XS_OPSIZE, /* 15890 */ IC_64BIT_XS_OPSIZE, /* 15891 */ IC_XD_OPSIZE, /* 15892 */ IC_64BIT_XD_OPSIZE, /* 15893 */ IC_XS_OPSIZE, /* 15894 */ IC_64BIT_XD_OPSIZE, /* 15895 */ IC_OPSIZE, /* 15896 */ IC_64BIT_REXW_OPSIZE, /* 15897 */ IC_XS_OPSIZE, /* 15898 */ IC_64BIT_REXW_XS, /* 15899 */ IC_XD_OPSIZE, /* 15900 */ IC_64BIT_REXW_XD, /* 15901 */ IC_XS_OPSIZE, /* 15902 */ IC_64BIT_REXW_XS, /* 15903 */ IC_ADSIZE, /* 15904 */ IC_64BIT_ADSIZE, /* 15905 */ IC_XS_ADSIZE, /* 15906 */ IC_64BIT_XS_ADSIZE, /* 15907 */ IC_XD_ADSIZE, /* 15908 */ IC_64BIT_XD_ADSIZE, /* 15909 */ IC_XS_ADSIZE, /* 15910 */ IC_64BIT_XD_ADSIZE, /* 15911 */ IC_ADSIZE, /* 15912 */ IC_64BIT_REXW_ADSIZE, /* 15913 */ IC_XS_ADSIZE, /* 15914 */ IC_64BIT_REXW_XS, /* 15915 */ IC_XD_ADSIZE, /* 15916 */ IC_64BIT_REXW_XD, /* 15917 */ IC_XS_ADSIZE, /* 15918 */ IC_64BIT_REXW_XS, /* 15919 */ IC_OPSIZE_ADSIZE, /* 15920 */ IC_64BIT_OPSIZE_ADSIZE, /* 15921 */ IC_XS_OPSIZE, /* 15922 */ IC_64BIT_XS_OPSIZE, /* 15923 */ IC_XD_OPSIZE, /* 15924 */ IC_64BIT_XD_OPSIZE, /* 15925 */ IC_XS_OPSIZE, /* 15926 */ IC_64BIT_XD_OPSIZE, /* 15927 */ IC_OPSIZE_ADSIZE, /* 15928 */ IC_64BIT_REXW_OPSIZE, /* 15929 */ IC_XS_OPSIZE, /* 15930 */ IC_64BIT_REXW_XS, /* 15931 */ IC_XD_OPSIZE, /* 15932 */ IC_64BIT_REXW_XD, /* 15933 */ IC_XS_OPSIZE, /* 15934 */ IC_64BIT_REXW_XS, /* 15935 */ IC_VEX, /* 15936 */ IC_VEX, /* 15937 */ IC_VEX_XS, /* 15938 */ IC_VEX_XS, /* 15939 */ IC_VEX_XD, /* 15940 */ IC_VEX_XD, /* 15941 */ IC_VEX_XD, /* 15942 */ IC_VEX_XD, /* 15943 */ IC_VEX_W, /* 15944 */ IC_VEX_W, /* 15945 */ IC_VEX_W_XS, /* 15946 */ IC_VEX_W_XS, /* 15947 */ IC_VEX_W_XD, /* 15948 */ IC_VEX_W_XD, /* 15949 */ IC_VEX_W_XD, /* 15950 */ IC_VEX_W_XD, /* 15951 */ IC_VEX_OPSIZE, /* 15952 */ IC_VEX_OPSIZE, /* 15953 */ IC_VEX_OPSIZE, /* 15954 */ IC_VEX_OPSIZE, /* 15955 */ IC_VEX_OPSIZE, /* 15956 */ IC_VEX_OPSIZE, /* 15957 */ IC_VEX_OPSIZE, /* 15958 */ IC_VEX_OPSIZE, /* 15959 */ IC_VEX_W_OPSIZE, /* 15960 */ IC_VEX_W_OPSIZE, /* 15961 */ IC_VEX_W_OPSIZE, /* 15962 */ IC_VEX_W_OPSIZE, /* 15963 */ IC_VEX_W_OPSIZE, /* 15964 */ IC_VEX_W_OPSIZE, /* 15965 */ IC_VEX_W_OPSIZE, /* 15966 */ IC_VEX_W_OPSIZE, /* 15967 */ IC_VEX, /* 15968 */ IC_VEX, /* 15969 */ IC_VEX_XS, /* 15970 */ IC_VEX_XS, /* 15971 */ IC_VEX_XD, /* 15972 */ IC_VEX_XD, /* 15973 */ IC_VEX_XD, /* 15974 */ IC_VEX_XD, /* 15975 */ IC_VEX_W, /* 15976 */ IC_VEX_W, /* 15977 */ IC_VEX_W_XS, /* 15978 */ IC_VEX_W_XS, /* 15979 */ IC_VEX_W_XD, /* 15980 */ IC_VEX_W_XD, /* 15981 */ IC_VEX_W_XD, /* 15982 */ IC_VEX_W_XD, /* 15983 */ IC_VEX_OPSIZE, /* 15984 */ IC_VEX_OPSIZE, /* 15985 */ IC_VEX_OPSIZE, /* 15986 */ IC_VEX_OPSIZE, /* 15987 */ IC_VEX_OPSIZE, /* 15988 */ IC_VEX_OPSIZE, /* 15989 */ IC_VEX_OPSIZE, /* 15990 */ IC_VEX_OPSIZE, /* 15991 */ IC_VEX_W_OPSIZE, /* 15992 */ IC_VEX_W_OPSIZE, /* 15993 */ IC_VEX_W_OPSIZE, /* 15994 */ IC_VEX_W_OPSIZE, /* 15995 */ IC_VEX_W_OPSIZE, /* 15996 */ IC_VEX_W_OPSIZE, /* 15997 */ IC_VEX_W_OPSIZE, /* 15998 */ IC_VEX_W_OPSIZE, /* 15999 */ IC_VEX_L, /* 16000 */ IC_VEX_L, /* 16001 */ IC_VEX_L_XS, /* 16002 */ IC_VEX_L_XS, /* 16003 */ IC_VEX_L_XD, /* 16004 */ IC_VEX_L_XD, /* 16005 */ IC_VEX_L_XD, /* 16006 */ IC_VEX_L_XD, /* 16007 */ IC_VEX_L_W, /* 16008 */ IC_VEX_L_W, /* 16009 */ IC_VEX_L_W_XS, /* 16010 */ IC_VEX_L_W_XS, /* 16011 */ IC_VEX_L_W_XD, /* 16012 */ IC_VEX_L_W_XD, /* 16013 */ IC_VEX_L_W_XD, /* 16014 */ IC_VEX_L_W_XD, /* 16015 */ IC_VEX_L_OPSIZE, /* 16016 */ IC_VEX_L_OPSIZE, /* 16017 */ IC_VEX_L_OPSIZE, /* 16018 */ IC_VEX_L_OPSIZE, /* 16019 */ IC_VEX_L_OPSIZE, /* 16020 */ IC_VEX_L_OPSIZE, /* 16021 */ IC_VEX_L_OPSIZE, /* 16022 */ IC_VEX_L_OPSIZE, /* 16023 */ IC_VEX_L_W_OPSIZE, /* 16024 */ IC_VEX_L_W_OPSIZE, /* 16025 */ IC_VEX_L_W_OPSIZE, /* 16026 */ IC_VEX_L_W_OPSIZE, /* 16027 */ IC_VEX_L_W_OPSIZE, /* 16028 */ IC_VEX_L_W_OPSIZE, /* 16029 */ IC_VEX_L_W_OPSIZE, /* 16030 */ IC_VEX_L_W_OPSIZE, /* 16031 */ IC_VEX_L, /* 16032 */ IC_VEX_L, /* 16033 */ IC_VEX_L_XS, /* 16034 */ IC_VEX_L_XS, /* 16035 */ IC_VEX_L_XD, /* 16036 */ IC_VEX_L_XD, /* 16037 */ IC_VEX_L_XD, /* 16038 */ IC_VEX_L_XD, /* 16039 */ IC_VEX_L_W, /* 16040 */ IC_VEX_L_W, /* 16041 */ IC_VEX_L_W_XS, /* 16042 */ IC_VEX_L_W_XS, /* 16043 */ IC_VEX_L_W_XD, /* 16044 */ IC_VEX_L_W_XD, /* 16045 */ IC_VEX_L_W_XD, /* 16046 */ IC_VEX_L_W_XD, /* 16047 */ IC_VEX_L_OPSIZE, /* 16048 */ IC_VEX_L_OPSIZE, /* 16049 */ IC_VEX_L_OPSIZE, /* 16050 */ IC_VEX_L_OPSIZE, /* 16051 */ IC_VEX_L_OPSIZE, /* 16052 */ IC_VEX_L_OPSIZE, /* 16053 */ IC_VEX_L_OPSIZE, /* 16054 */ IC_VEX_L_OPSIZE, /* 16055 */ IC_VEX_L_W_OPSIZE, /* 16056 */ IC_VEX_L_W_OPSIZE, /* 16057 */ IC_VEX_L_W_OPSIZE, /* 16058 */ IC_VEX_L_W_OPSIZE, /* 16059 */ IC_VEX_L_W_OPSIZE, /* 16060 */ IC_VEX_L_W_OPSIZE, /* 16061 */ IC_VEX_L_W_OPSIZE, /* 16062 */ IC_VEX_L_W_OPSIZE, /* 16063 */ IC_VEX_L, /* 16064 */ IC_VEX_L, /* 16065 */ IC_VEX_L_XS, /* 16066 */ IC_VEX_L_XS, /* 16067 */ IC_VEX_L_XD, /* 16068 */ IC_VEX_L_XD, /* 16069 */ IC_VEX_L_XD, /* 16070 */ IC_VEX_L_XD, /* 16071 */ IC_VEX_L_W, /* 16072 */ IC_VEX_L_W, /* 16073 */ IC_VEX_L_W_XS, /* 16074 */ IC_VEX_L_W_XS, /* 16075 */ IC_VEX_L_W_XD, /* 16076 */ IC_VEX_L_W_XD, /* 16077 */ IC_VEX_L_W_XD, /* 16078 */ IC_VEX_L_W_XD, /* 16079 */ IC_VEX_L_OPSIZE, /* 16080 */ IC_VEX_L_OPSIZE, /* 16081 */ IC_VEX_L_OPSIZE, /* 16082 */ IC_VEX_L_OPSIZE, /* 16083 */ IC_VEX_L_OPSIZE, /* 16084 */ IC_VEX_L_OPSIZE, /* 16085 */ IC_VEX_L_OPSIZE, /* 16086 */ IC_VEX_L_OPSIZE, /* 16087 */ IC_VEX_L_W_OPSIZE, /* 16088 */ IC_VEX_L_W_OPSIZE, /* 16089 */ IC_VEX_L_W_OPSIZE, /* 16090 */ IC_VEX_L_W_OPSIZE, /* 16091 */ IC_VEX_L_W_OPSIZE, /* 16092 */ IC_VEX_L_W_OPSIZE, /* 16093 */ IC_VEX_L_W_OPSIZE, /* 16094 */ IC_VEX_L_W_OPSIZE, /* 16095 */ IC_VEX_L, /* 16096 */ IC_VEX_L, /* 16097 */ IC_VEX_L_XS, /* 16098 */ IC_VEX_L_XS, /* 16099 */ IC_VEX_L_XD, /* 16100 */ IC_VEX_L_XD, /* 16101 */ IC_VEX_L_XD, /* 16102 */ IC_VEX_L_XD, /* 16103 */ IC_VEX_L_W, /* 16104 */ IC_VEX_L_W, /* 16105 */ IC_VEX_L_W_XS, /* 16106 */ IC_VEX_L_W_XS, /* 16107 */ IC_VEX_L_W_XD, /* 16108 */ IC_VEX_L_W_XD, /* 16109 */ IC_VEX_L_W_XD, /* 16110 */ IC_VEX_L_W_XD, /* 16111 */ IC_VEX_L_OPSIZE, /* 16112 */ IC_VEX_L_OPSIZE, /* 16113 */ IC_VEX_L_OPSIZE, /* 16114 */ IC_VEX_L_OPSIZE, /* 16115 */ IC_VEX_L_OPSIZE, /* 16116 */ IC_VEX_L_OPSIZE, /* 16117 */ IC_VEX_L_OPSIZE, /* 16118 */ IC_VEX_L_OPSIZE, /* 16119 */ IC_VEX_L_W_OPSIZE, /* 16120 */ IC_VEX_L_W_OPSIZE, /* 16121 */ IC_VEX_L_W_OPSIZE, /* 16122 */ IC_VEX_L_W_OPSIZE, /* 16123 */ IC_VEX_L_W_OPSIZE, /* 16124 */ IC_VEX_L_W_OPSIZE, /* 16125 */ IC_VEX_L_W_OPSIZE, /* 16126 */ IC_VEX_L_W_OPSIZE, /* 16127 */ IC_EVEX_L2_KZ_B, /* 16128 */ IC_EVEX_L2_KZ_B, /* 16129 */ IC_EVEX_L2_XS_KZ_B, /* 16130 */ IC_EVEX_L2_XS_KZ_B, /* 16131 */ IC_EVEX_L2_XD_KZ_B, /* 16132 */ IC_EVEX_L2_XD_KZ_B, /* 16133 */ IC_EVEX_L2_XD_KZ_B, /* 16134 */ IC_EVEX_L2_XD_KZ_B, /* 16135 */ IC_EVEX_L2_W_KZ_B, /* 16136 */ IC_EVEX_L2_W_KZ_B, /* 16137 */ IC_EVEX_L2_W_XS_KZ_B, /* 16138 */ IC_EVEX_L2_W_XS_KZ_B, /* 16139 */ IC_EVEX_L2_W_XD_KZ_B, /* 16140 */ IC_EVEX_L2_W_XD_KZ_B, /* 16141 */ IC_EVEX_L2_W_XD_KZ_B, /* 16142 */ IC_EVEX_L2_W_XD_KZ_B, /* 16143 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16144 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16145 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16146 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16147 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16148 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16149 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16150 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16151 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16152 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16153 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16154 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16155 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16156 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16157 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16158 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16159 */ IC_EVEX_L2_KZ_B, /* 16160 */ IC_EVEX_L2_KZ_B, /* 16161 */ IC_EVEX_L2_XS_KZ_B, /* 16162 */ IC_EVEX_L2_XS_KZ_B, /* 16163 */ IC_EVEX_L2_XD_KZ_B, /* 16164 */ IC_EVEX_L2_XD_KZ_B, /* 16165 */ IC_EVEX_L2_XD_KZ_B, /* 16166 */ IC_EVEX_L2_XD_KZ_B, /* 16167 */ IC_EVEX_L2_W_KZ_B, /* 16168 */ IC_EVEX_L2_W_KZ_B, /* 16169 */ IC_EVEX_L2_W_XS_KZ_B, /* 16170 */ IC_EVEX_L2_W_XS_KZ_B, /* 16171 */ IC_EVEX_L2_W_XD_KZ_B, /* 16172 */ IC_EVEX_L2_W_XD_KZ_B, /* 16173 */ IC_EVEX_L2_W_XD_KZ_B, /* 16174 */ IC_EVEX_L2_W_XD_KZ_B, /* 16175 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16176 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16177 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16178 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16179 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16180 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16181 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16182 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16183 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16184 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16185 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16186 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16187 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16188 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16189 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16190 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16191 */ IC_EVEX_L2_KZ_B, /* 16192 */ IC_EVEX_L2_KZ_B, /* 16193 */ IC_EVEX_L2_XS_KZ_B, /* 16194 */ IC_EVEX_L2_XS_KZ_B, /* 16195 */ IC_EVEX_L2_XD_KZ_B, /* 16196 */ IC_EVEX_L2_XD_KZ_B, /* 16197 */ IC_EVEX_L2_XD_KZ_B, /* 16198 */ IC_EVEX_L2_XD_KZ_B, /* 16199 */ IC_EVEX_L2_W_KZ_B, /* 16200 */ IC_EVEX_L2_W_KZ_B, /* 16201 */ IC_EVEX_L2_W_XS_KZ_B, /* 16202 */ IC_EVEX_L2_W_XS_KZ_B, /* 16203 */ IC_EVEX_L2_W_XD_KZ_B, /* 16204 */ IC_EVEX_L2_W_XD_KZ_B, /* 16205 */ IC_EVEX_L2_W_XD_KZ_B, /* 16206 */ IC_EVEX_L2_W_XD_KZ_B, /* 16207 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16208 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16209 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16210 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16211 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16212 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16213 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16214 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16215 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16216 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16217 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16218 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16219 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16220 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16221 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16222 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16223 */ IC_EVEX_L2_KZ_B, /* 16224 */ IC_EVEX_L2_KZ_B, /* 16225 */ IC_EVEX_L2_XS_KZ_B, /* 16226 */ IC_EVEX_L2_XS_KZ_B, /* 16227 */ IC_EVEX_L2_XD_KZ_B, /* 16228 */ IC_EVEX_L2_XD_KZ_B, /* 16229 */ IC_EVEX_L2_XD_KZ_B, /* 16230 */ IC_EVEX_L2_XD_KZ_B, /* 16231 */ IC_EVEX_L2_W_KZ_B, /* 16232 */ IC_EVEX_L2_W_KZ_B, /* 16233 */ IC_EVEX_L2_W_XS_KZ_B, /* 16234 */ IC_EVEX_L2_W_XS_KZ_B, /* 16235 */ IC_EVEX_L2_W_XD_KZ_B, /* 16236 */ IC_EVEX_L2_W_XD_KZ_B, /* 16237 */ IC_EVEX_L2_W_XD_KZ_B, /* 16238 */ IC_EVEX_L2_W_XD_KZ_B, /* 16239 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16240 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16241 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16242 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16243 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16244 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16245 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16246 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16247 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16248 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16249 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16250 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16251 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16252 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16253 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16254 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16255 */ IC_EVEX_L2_KZ_B, /* 16256 */ IC_EVEX_L2_KZ_B, /* 16257 */ IC_EVEX_L2_XS_KZ_B, /* 16258 */ IC_EVEX_L2_XS_KZ_B, /* 16259 */ IC_EVEX_L2_XD_KZ_B, /* 16260 */ IC_EVEX_L2_XD_KZ_B, /* 16261 */ IC_EVEX_L2_XD_KZ_B, /* 16262 */ IC_EVEX_L2_XD_KZ_B, /* 16263 */ IC_EVEX_L2_W_KZ_B, /* 16264 */ IC_EVEX_L2_W_KZ_B, /* 16265 */ IC_EVEX_L2_W_XS_KZ_B, /* 16266 */ IC_EVEX_L2_W_XS_KZ_B, /* 16267 */ IC_EVEX_L2_W_XD_KZ_B, /* 16268 */ IC_EVEX_L2_W_XD_KZ_B, /* 16269 */ IC_EVEX_L2_W_XD_KZ_B, /* 16270 */ IC_EVEX_L2_W_XD_KZ_B, /* 16271 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16272 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16273 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16274 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16275 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16276 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16277 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16278 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16279 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16280 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16281 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16282 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16283 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16284 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16285 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16286 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16287 */ IC_EVEX_L2_KZ_B, /* 16288 */ IC_EVEX_L2_KZ_B, /* 16289 */ IC_EVEX_L2_XS_KZ_B, /* 16290 */ IC_EVEX_L2_XS_KZ_B, /* 16291 */ IC_EVEX_L2_XD_KZ_B, /* 16292 */ IC_EVEX_L2_XD_KZ_B, /* 16293 */ IC_EVEX_L2_XD_KZ_B, /* 16294 */ IC_EVEX_L2_XD_KZ_B, /* 16295 */ IC_EVEX_L2_W_KZ_B, /* 16296 */ IC_EVEX_L2_W_KZ_B, /* 16297 */ IC_EVEX_L2_W_XS_KZ_B, /* 16298 */ IC_EVEX_L2_W_XS_KZ_B, /* 16299 */ IC_EVEX_L2_W_XD_KZ_B, /* 16300 */ IC_EVEX_L2_W_XD_KZ_B, /* 16301 */ IC_EVEX_L2_W_XD_KZ_B, /* 16302 */ IC_EVEX_L2_W_XD_KZ_B, /* 16303 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16304 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16305 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16306 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16307 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16308 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16309 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16310 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16311 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16312 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16313 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16314 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16315 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16316 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16317 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16318 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16319 */ IC_EVEX_L2_KZ_B, /* 16320 */ IC_EVEX_L2_KZ_B, /* 16321 */ IC_EVEX_L2_XS_KZ_B, /* 16322 */ IC_EVEX_L2_XS_KZ_B, /* 16323 */ IC_EVEX_L2_XD_KZ_B, /* 16324 */ IC_EVEX_L2_XD_KZ_B, /* 16325 */ IC_EVEX_L2_XD_KZ_B, /* 16326 */ IC_EVEX_L2_XD_KZ_B, /* 16327 */ IC_EVEX_L2_W_KZ_B, /* 16328 */ IC_EVEX_L2_W_KZ_B, /* 16329 */ IC_EVEX_L2_W_XS_KZ_B, /* 16330 */ IC_EVEX_L2_W_XS_KZ_B, /* 16331 */ IC_EVEX_L2_W_XD_KZ_B, /* 16332 */ IC_EVEX_L2_W_XD_KZ_B, /* 16333 */ IC_EVEX_L2_W_XD_KZ_B, /* 16334 */ IC_EVEX_L2_W_XD_KZ_B, /* 16335 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16336 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16337 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16338 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16339 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16340 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16341 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16342 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16343 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16344 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16345 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16346 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16347 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16348 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16349 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16350 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16351 */ IC_EVEX_L2_KZ_B, /* 16352 */ IC_EVEX_L2_KZ_B, /* 16353 */ IC_EVEX_L2_XS_KZ_B, /* 16354 */ IC_EVEX_L2_XS_KZ_B, /* 16355 */ IC_EVEX_L2_XD_KZ_B, /* 16356 */ IC_EVEX_L2_XD_KZ_B, /* 16357 */ IC_EVEX_L2_XD_KZ_B, /* 16358 */ IC_EVEX_L2_XD_KZ_B, /* 16359 */ IC_EVEX_L2_W_KZ_B, /* 16360 */ IC_EVEX_L2_W_KZ_B, /* 16361 */ IC_EVEX_L2_W_XS_KZ_B, /* 16362 */ IC_EVEX_L2_W_XS_KZ_B, /* 16363 */ IC_EVEX_L2_W_XD_KZ_B, /* 16364 */ IC_EVEX_L2_W_XD_KZ_B, /* 16365 */ IC_EVEX_L2_W_XD_KZ_B, /* 16366 */ IC_EVEX_L2_W_XD_KZ_B, /* 16367 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16368 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16369 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16370 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16371 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16372 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16373 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16374 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16375 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16376 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16377 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16378 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16379 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16380 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16381 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16382 */ IC_EVEX_L2_W_OPSIZE_KZ_B /* 16383 */ }; static const InstrUID modRMTable[] = { /* EmptyTable */ 0x0, /* Table1 */ 0xe0, /* ADD8mr */ 0xe4, /* ADD8rr */ /* Table3 */ 0xce, /* ADD32mr */ 0xd2, /* ADD32rr */ /* Table5 */ 0xe3, /* ADD8rm */ 0xe5, /* ADD8rr_REV */ /* Table7 */ 0xd1, /* ADD32rm */ 0xd3, /* ADD32rr_REV */ /* Table9 */ 0xdd, /* ADD8i8 */ /* Table10 */ 0xcb, /* ADD32i32 */ /* Table11 */ 0x8cb, /* PUSHES32 */ /* Table12 */ 0x850, /* POPES32 */ /* Table13 */ 0x749, /* OR8mr */ 0x74d, /* OR8rr */ /* Table15 */ 0x737, /* OR32mr */ 0x73b, /* OR32rr */ /* Table17 */ 0x74c, /* OR8rm */ 0x74e, /* OR8rr_REV */ /* Table19 */ 0x73a, /* OR32rm */ 0x73c, /* OR32rr_REV */ /* Table21 */ 0x746, /* OR8i8 */ /* Table22 */ 0x734, /* OR32i32 */ /* Table23 */ 0x8c7, /* PUSHCS32 */ /* Table24 */ 0xb8, /* ADC8mr */ 0xbc, /* ADC8rr */ /* Table26 */ 0xa6, /* ADC32mr */ 0xaa, /* ADC32rr */ /* Table28 */ 0xbb, /* ADC8rm */ 0xbd, /* ADC8rr_REV */ /* Table30 */ 0xa9, /* ADC32rm */ 0xab, /* ADC32rr_REV */ /* Table32 */ 0xb5, /* ADC8i8 */ /* Table33 */ 0xa3, /* ADC32i32 */ /* Table34 */ 0x8d6, /* PUSHSS32 */ /* Table35 */ 0x85b, /* POPSS32 */ /* Table36 */ 0x9ca, /* SBB8mr */ 0x9ce, /* SBB8rr */ /* Table38 */ 0x9b8, /* SBB32mr */ 0x9bc, /* SBB32rr */ /* Table40 */ 0x9cd, /* SBB8rm */ 0x9cf, /* SBB8rr_REV */ /* Table42 */ 0x9bb, /* SBB32rm */ 0x9bd, /* SBB32rr_REV */ /* Table44 */ 0x9c7, /* SBB8i8 */ /* Table45 */ 0x9b5, /* SBB32i32 */ /* Table46 */ 0x8c9, /* PUSHDS32 */ /* Table47 */ 0x84e, /* POPDS32 */ /* Table48 */ 0x139, /* AND8mr */ 0x13d, /* AND8rr */ /* Table50 */ 0x127, /* AND32mr */ 0x12b, /* AND32rr */ /* Table52 */ 0x13c, /* AND8rm */ 0x13e, /* AND8rr_REV */ /* Table54 */ 0x12a, /* AND32rm */ 0x12c, /* AND32rr_REV */ /* Table56 */ 0x136, /* AND8i8 */ /* Table57 */ 0x124, /* AND32i32 */ /* Table58 */ 0x327, /* DAA */ /* Table59 */ 0xabb, /* SUB8mr */ 0xabf, /* SUB8rr */ /* Table61 */ 0xaa9, /* SUB32mr */ 0xaad, /* SUB32rr */ /* Table63 */ 0xabe, /* SUB8rm */ 0xac0, /* SUB8rr_REV */ /* Table65 */ 0xaac, /* SUB32rm */ 0xaae, /* SUB32rr_REV */ /* Table67 */ 0xab8, /* SUB8i8 */ /* Table68 */ 0xaa6, /* SUB32i32 */ /* Table69 */ 0x328, /* DAS */ /* Table70 */ 0x3b99, /* XOR8mr */ 0x3b9d, /* XOR8rr */ /* Table72 */ 0x3b87, /* XOR32mr */ 0x3b8b, /* XOR32rr */ /* Table74 */ 0x3b9c, /* XOR8rm */ 0x3b9e, /* XOR8rr_REV */ /* Table76 */ 0x3b8a, /* XOR32rm */ 0x3b8c, /* XOR32rr_REV */ /* Table78 */ 0x3b96, /* XOR8i8 */ /* Table79 */ 0x3b84, /* XOR32i32 */ /* Table80 */ 0x92, /* AAA */ /* Table81 */ 0x2a1, /* CMP8mr */ 0x2a5, /* CMP8rr */ /* Table83 */ 0x28f, /* CMP32mr */ 0x293, /* CMP32rr */ /* Table85 */ 0x2a4, /* CMP8rm */ 0x2a6, /* CMP8rr_REV */ /* Table87 */ 0x292, /* CMP32rm */ 0x294, /* CMP32rr_REV */ /* Table89 */ 0x29e, /* CMP8i8 */ /* Table90 */ 0x28c, /* CMP32i32 */ /* Table91 */ 0x95, /* AAS */ /* Table92 */ 0x404, /* INC32r_alt */ /* Table93 */ 0x32f, /* DEC32r_alt */ /* Table94 */ 0x8bc, /* PUSH32r */ /* Table95 */ 0x83f, /* POP32r */ /* Table96 */ 0x8c5, /* PUSHA32 */ /* Table97 */ 0x846, /* POPA32 */ /* Table98 */ 0x19c, /* BOUNDS32rm */ 0x0, /* */ /* Table100 */ 0x14b, /* ARPL16mr */ 0x14c, /* ARPL16rr */ /* Table102 */ 0x329, /* DATA16_PREFIX */ /* Table103 */ 0x8d8, /* PUSHi32 */ /* Table104 */ 0x3ea, /* IMUL32rmi */ 0x3ed, /* IMUL32rri */ /* Table106 */ 0x8bb, /* PUSH32i8 */ /* Table107 */ 0x3eb, /* IMUL32rmi8 */ 0x3ee, /* IMUL32rri8 */ /* Table109 */ 0x40b, /* INSB */ /* Table110 */ 0x410, /* INSL */ /* Table111 */ 0x759, /* OUTSB */ /* Table112 */ 0x75a, /* OUTSL */ /* Table113 */ 0x475, /* JO_1 */ /* Table114 */ 0x46c, /* JNO_1 */ /* Table115 */ 0x446, /* JB_1 */ /* Table116 */ 0x43d, /* JAE_1 */ /* Table117 */ 0x44b, /* JE_1 */ /* Table118 */ 0x469, /* JNE_1 */ /* Table119 */ 0x443, /* JBE_1 */ /* Table120 */ 0x440, /* JA_1 */ /* Table121 */ 0x47c, /* JS_1 */ /* Table122 */ 0x472, /* JNS_1 */ /* Table123 */ 0x478, /* JP_1 */ /* Table124 */ 0x46f, /* JNP_1 */ /* Table125 */ 0x457, /* JL_1 */ /* Table126 */ 0x44e, /* JGE_1 */ /* Table127 */ 0x454, /* JLE_1 */ /* Table128 */ 0x451, /* JG_1 */ /* Table129 */ 0xde, /* ADD8mi */ 0x747, /* OR8mi */ 0xb6, /* ADC8mi */ 0x9c8, /* SBB8mi */ 0x137, /* AND8mi */ 0xab9, /* SUB8mi */ 0x3b97, /* XOR8mi */ 0x29f, /* CMP8mi */ 0xe1, /* ADD8ri */ 0x74a, /* OR8ri */ 0xb9, /* ADC8ri */ 0x9cb, /* SBB8ri */ 0x13a, /* AND8ri */ 0xabc, /* SUB8ri */ 0x3b9a, /* XOR8ri */ 0x2a2, /* CMP8ri */ /* Table145 */ 0xcc, /* ADD32mi */ 0x735, /* OR32mi */ 0xa4, /* ADC32mi */ 0x9b6, /* SBB32mi */ 0x125, /* AND32mi */ 0xaa7, /* SUB32mi */ 0x3b85, /* XOR32mi */ 0x28d, /* CMP32mi */ 0xcf, /* ADD32ri */ 0x738, /* OR32ri */ 0xa7, /* ADC32ri */ 0x9b9, /* SBB32ri */ 0x128, /* AND32ri */ 0xaaa, /* SUB32ri */ 0x3b88, /* XOR32ri */ 0x290, /* CMP32ri */ /* Table161 */ 0xdf, /* ADD8mi8 */ 0x748, /* OR8mi8 */ 0xb7, /* ADC8mi8 */ 0x9c9, /* SBB8mi8 */ 0x138, /* AND8mi8 */ 0xaba, /* SUB8mi8 */ 0x3b98, /* XOR8mi8 */ 0x2a0, /* CMP8mi8 */ 0xe2, /* ADD8ri8 */ 0x74b, /* OR8ri8 */ 0xba, /* ADC8ri8 */ 0x9cc, /* SBB8ri8 */ 0x13b, /* AND8ri8 */ 0xabd, /* SUB8ri8 */ 0x3b9b, /* XOR8ri8 */ 0x2a3, /* CMP8ri8 */ /* Table177 */ 0xcd, /* ADD32mi8 */ 0x736, /* OR32mi8 */ 0xa5, /* ADC32mi8 */ 0x9b7, /* SBB32mi8 */ 0x126, /* AND32mi8 */ 0xaa8, /* SUB32mi8 */ 0x3b86, /* XOR32mi8 */ 0x28e, /* CMP32mi8 */ 0xd0, /* ADD32ri8 */ 0x739, /* OR32ri8 */ 0xa8, /* ADC32ri8 */ 0x9ba, /* SBB32ri8 */ 0x129, /* AND32ri8 */ 0xaab, /* SUB32ri8 */ 0x3b89, /* XOR32ri8 */ 0x291, /* CMP32ri8 */ /* Table193 */ 0xb17, /* TEST8mr */ 0xb1a, /* TEST8rr */ /* Table195 */ 0xb09, /* TEST32mr */ 0xb0c, /* TEST32rr */ /* Table197 */ 0x3b70, /* XCHG8rm */ 0x3b71, /* XCHG8rr */ /* Table199 */ 0x3b6b, /* XCHG32rm */ 0x3b6c, /* XCHG32rr */ /* Table201 */ 0x648, /* MOV8mr */ 0x651, /* MOV8rr */ /* Table203 */ 0x622, /* MOV32mr */ 0x62b, /* MOV32rr */ /* Table205 */ 0x64f, /* MOV8rm */ 0x653, /* MOV8rr_REV */ /* Table207 */ 0x62a, /* MOV32rm */ 0x62c, /* MOV32rr_REV */ /* Table209 */ 0x610, /* MOV16ms */ 0x62d, /* MOV32rs */ /* Table211 */ 0x4e0, /* LEA32r */ 0x0, /* */ /* Table213 */ 0x61a, /* MOV16sm */ 0x62e, /* MOV32sr */ /* Table215 */ 0x840, /* POP32rmm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x841, /* POP32rmr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table231 */ 0x704, /* NOOP */ /* Table232 */ 0x3b6a, /* XCHG32ar */ /* Table233 */ 0x326, /* CWDE */ /* Table234 */ 0x1f0, /* CDQ */ /* Table235 */ 0x380, /* FARCALL32i */ /* Table236 */ 0x3b4e, /* WAIT */ /* Table237 */ 0x8cd, /* PUSHF32 */ /* Table238 */ 0x852, /* POPF32 */ /* Table239 */ 0x975, /* SAHF */ /* Table240 */ 0x4c2, /* LAHF */ /* Table241 */ 0x645, /* MOV8ao32 */ /* Table242 */ 0x61d, /* MOV32ao32 */ /* Table243 */ 0x64b, /* MOV8o32a */ /* Table244 */ 0x624, /* MOV32o32a */ /* Table245 */ 0x690, /* MOVSB */ /* Table246 */ 0x699, /* MOVSL */ /* Table247 */ 0x2af, /* CMPSB */ /* Table248 */ 0x2b6, /* CMPSL */ /* Table249 */ 0xb14, /* TEST8i8 */ /* Table250 */ 0xb06, /* TEST32i32 */ /* Table251 */ 0xa83, /* STOSB */ /* Table252 */ 0xa84, /* STOSL */ /* Table253 */ 0x4fb, /* LODSB */ /* Table254 */ 0x4fc, /* LODSL */ /* Table255 */ 0x9d0, /* SCASB */ /* Table256 */ 0x9d1, /* SCASL */ /* Table257 */ 0x64d, /* MOV8ri */ /* Table258 */ 0x628, /* MOV32ri */ /* Table259 */ 0x941, /* ROL8mi */ 0x959, /* ROR8mi */ 0x8ef, /* RCL8mi */ 0x90d, /* RCR8mi */ 0xa1b, /* SHL8mi */ 0xa43, /* SHR8mi */ 0x98a, /* SAL8mi */ 0x9a3, /* SAR8mi */ 0x944, /* ROL8ri */ 0x95c, /* ROR8ri */ 0x8f2, /* RCL8ri */ 0x910, /* RCR8ri */ 0xa1e, /* SHL8ri */ 0xa46, /* SHR8ri */ 0x98d, /* SAL8ri */ 0x9a6, /* SAR8ri */ /* Table275 */ 0x935, /* ROL32mi */ 0x94d, /* ROR32mi */ 0x8e3, /* RCL32mi */ 0x901, /* RCR32mi */ 0xa0f, /* SHL32mi */ 0xa37, /* SHR32mi */ 0x97e, /* SAL32mi */ 0x997, /* SAR32mi */ 0x938, /* ROL32ri */ 0x950, /* ROR32ri */ 0x8e6, /* RCL32ri */ 0x904, /* RCR32ri */ 0xa12, /* SHL32ri */ 0xa3a, /* SHR32ri */ 0x981, /* SAL32ri */ 0x99a, /* SAR32ri */ /* Table291 */ 0x926, /* RETIL */ /* Table292 */ 0x929, /* RETL */ /* Table293 */ 0x4e6, /* LES32rm */ 0x0, /* */ /* Table295 */ 0x4cc, /* LDS32rm */ 0x0, /* */ /* Table297 */ 0x647, /* MOV8mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x64e, /* MOV8ri_alt */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b5b, /* XABORT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table369 */ 0x621, /* MOV32mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x629, /* MOV32ri_alt */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b66, /* XBEGIN_4 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table441 */ 0x378, /* ENTER */ /* Table442 */ 0x4e3, /* LEAVE */ /* Table443 */ 0x502, /* LRETIL */ /* Table444 */ 0x505, /* LRETL */ /* Table445 */ 0x414, /* INT3 */ /* Table446 */ 0x412, /* INT */ /* Table447 */ 0x415, /* INTO */ /* Table448 */ 0x421, /* IRET32 */ /* Table449 */ 0x93f, /* ROL8m1 */ 0x957, /* ROR8m1 */ 0x8ed, /* RCL8m1 */ 0x90b, /* RCR8m1 */ 0xa19, /* SHL8m1 */ 0xa41, /* SHR8m1 */ 0x988, /* SAL8m1 */ 0x9a1, /* SAR8m1 */ 0x942, /* ROL8r1 */ 0x95a, /* ROR8r1 */ 0x8f0, /* RCL8r1 */ 0x90e, /* RCR8r1 */ 0xa1c, /* SHL8r1 */ 0xa44, /* SHR8r1 */ 0x98b, /* SAL8r1 */ 0x9a4, /* SAR8r1 */ /* Table465 */ 0x933, /* ROL32m1 */ 0x94b, /* ROR32m1 */ 0x8e1, /* RCL32m1 */ 0x8ff, /* RCR32m1 */ 0xa0d, /* SHL32m1 */ 0xa35, /* SHR32m1 */ 0x97c, /* SAL32m1 */ 0x995, /* SAR32m1 */ 0x936, /* ROL32r1 */ 0x94e, /* ROR32r1 */ 0x8e4, /* RCL32r1 */ 0x902, /* RCR32r1 */ 0xa10, /* SHL32r1 */ 0xa38, /* SHR32r1 */ 0x97f, /* SAL32r1 */ 0x998, /* SAR32r1 */ /* Table481 */ 0x940, /* ROL8mCL */ 0x958, /* ROR8mCL */ 0x8ee, /* RCL8mCL */ 0x90c, /* RCR8mCL */ 0xa1a, /* SHL8mCL */ 0xa42, /* SHR8mCL */ 0x989, /* SAL8mCL */ 0x9a2, /* SAR8mCL */ 0x943, /* ROL8rCL */ 0x95b, /* ROR8rCL */ 0x8f1, /* RCL8rCL */ 0x90f, /* RCR8rCL */ 0xa1d, /* SHL8rCL */ 0xa45, /* SHR8rCL */ 0x98c, /* SAL8rCL */ 0x9a5, /* SAR8rCL */ /* Table497 */ 0x934, /* ROL32mCL */ 0x94c, /* ROR32mCL */ 0x8e2, /* RCL32mCL */ 0x900, /* RCR32mCL */ 0xa0e, /* SHL32mCL */ 0xa36, /* SHR32mCL */ 0x97d, /* SAL32mCL */ 0x996, /* SAR32mCL */ 0x937, /* ROL32rCL */ 0x94f, /* ROR32rCL */ 0x8e5, /* RCL32rCL */ 0x903, /* RCR32rCL */ 0xa11, /* SHL32rCL */ 0xa39, /* SHR32rCL */ 0x980, /* SAL32rCL */ 0x999, /* SAR32rCL */ /* Table513 */ 0x94, /* AAM8i8 */ /* Table514 */ 0x93, /* AAD8i8 */ /* Table515 */ 0x98e, /* SALC */ /* Table516 */ 0x3b7a, /* XLAT */ /* Table517 */ 0xf6, /* ADD_F32m */ 0x6e5, /* MUL_F32m */ 0x38a, /* FCOM32m */ 0x38c, /* FCOMP32m */ 0xadf, /* SUB_F32m */ 0xac5, /* SUBR_F32m */ 0x35a, /* DIV_F32m */ 0x340, /* DIVR_F32m */ 0xfb, /* ADD_FST0r */ 0x6ea, /* MUL_FST0r */ 0x2d4, /* COM_FST0r */ 0x2d1, /* COMP_FST0r */ 0xae4, /* SUB_FST0r */ 0xaca, /* SUBR_FST0r */ 0x35f, /* DIV_FST0r */ 0x345, /* DIVR_FST0r */ /* Table533 */ 0x4cf, /* LD_F32m */ 0x0, /* */ 0xa8b, /* ST_F32m */ 0xa8d, /* ST_FP32m */ 0x39b, /* FLDENVm */ 0x39a, /* FLDCW16m */ 0x3b2, /* FSTENVm */ 0x3a4, /* FNSTCW16m */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x4de, /* LD_Frr */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3b72, /* XCH_F */ 0x3a3, /* FNOP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x3a8, /* FPNCEST0r */ 0x1f2, /* CHS_F */ 0x96, /* ABS_F */ 0x0, /* */ 0x0, /* */ 0xb1c, /* TST_F */ 0x3b3, /* FXAM */ 0x0, /* */ 0x0, /* */ 0x4ce, /* LD_F1 */ 0x39d, /* FLDL2T */ 0x39c, /* FLDL2E */ 0x3a0, /* FLDPI */ 0x39e, /* FLDLG2 */ 0x39f, /* FLDLN2 */ 0x4cd, /* LD_F0 */ 0x0, /* */ 0x37d, /* F2XM1 */ 0x3b9, /* FYL2X */ 0x3ab, /* FPTAN */ 0x3a7, /* FPATAN */ 0x3b8, /* FXTRACT */ 0x3aa, /* FPREM1 */ 0x38f, /* FDECSTP */ 0x399, /* FINCSTP */ 0x3a9, /* FPREM */ 0x3ba, /* FYL2XP1 */ 0xa79, /* SQRT_F */ 0x3b1, /* FSINCOS */ 0x3ac, /* FRNDINT */ 0x3af, /* FSCALE */ 0xa5e, /* SIN_F */ 0x2d5, /* COS_F */ /* Table605 */ 0xf9, /* ADD_FI32m */ 0x6e8, /* MUL_FI32m */ 0x396, /* FICOM32m */ 0x398, /* FICOMP32m */ 0xae2, /* SUB_FI32m */ 0xac8, /* SUBR_FI32m */ 0x35d, /* DIV_FI32m */ 0x343, /* DIVR_FI32m */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x21f, /* CMOVB_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x229, /* CMOVE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x21b, /* CMOVBE_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x279, /* CMOVP_F */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb34, /* UCOM_FPPr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table677 */ 0x3d4, /* ILD_F32m */ 0x424, /* ISTT_FP32m */ 0x430, /* IST_F32m */ 0x432, /* IST_FP32m */ 0x0, /* */ 0x4d1, /* LD_F80m */ 0x0, /* */ 0xa8f, /* ST_FP80m */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x249, /* CMOVNB_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x253, /* CMOVNE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x245, /* CMOVNBE_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x263, /* CMOVNP_F */ 0x392, /* FENI8087_NOP */ 0x390, /* FDISI8087_NOP */ 0x3a1, /* FNCLEX */ 0x3a2, /* FNINIT */ 0x3b0, /* FSETPM */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0xb33, /* UCOM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x2d3, /* COM_FIr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table749 */ 0xf7, /* ADD_F64m */ 0x6e6, /* MUL_F64m */ 0x38b, /* FCOM64m */ 0x38d, /* FCOMP64m */ 0xae0, /* SUB_F64m */ 0xac6, /* SUBR_F64m */ 0x35b, /* DIV_F64m */ 0x341, /* DIVR_F64m */ 0x10a, /* ADD_FrST0 */ 0x6f9, /* MUL_FrST0 */ 0x0, /* */ 0x0, /* */ 0xad6, /* SUBR_FrST0 */ 0xaf3, /* SUB_FrST0 */ 0x351, /* DIVR_FrST0 */ 0x36e, /* DIV_FrST0 */ /* Table765 */ 0x4d0, /* LD_F64m */ 0x425, /* ISTT_FP64m */ 0xa8c, /* ST_F64m */ 0xa8e, /* ST_FP64m */ 0x3ad, /* FRSTORm */ 0x0, /* */ 0x3ae, /* FSAVEm */ 0x3a6, /* FNSTSWm */ 0x393, /* FFREE */ 0x0, /* */ 0xa9c, /* ST_Frr */ 0xa90, /* ST_FPrr */ 0xb3c, /* UCOM_Fr */ 0xb35, /* UCOM_FPr */ 0x0, /* */ 0x0, /* */ /* Table781 */ 0xf8, /* ADD_FI16m */ 0x6e7, /* MUL_FI16m */ 0x395, /* FICOM16m */ 0x397, /* FICOMP16m */ 0xae1, /* SUB_FI16m */ 0xac7, /* SUBR_FI16m */ 0x35c, /* DIV_FI16m */ 0x342, /* DIVR_FI16m */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0xfa, /* ADD_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x6e9, /* MUL_FPrST0 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x38e, /* FCOMPP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xac9, /* SUBR_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0xae3, /* SUB_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x344, /* DIVR_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ 0x35e, /* DIV_FPrST0 */ /* Table853 */ 0x3d3, /* ILD_F16m */ 0x423, /* ISTT_FP16m */ 0x42f, /* IST_F16m */ 0x431, /* IST_FP16m */ 0x388, /* FBLDm */ 0x3d5, /* ILD_F64m */ 0x389, /* FBSTPm */ 0x433, /* IST_FP64m */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x394, /* FFREEP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3a5, /* FNSTSW16r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0xb32, /* UCOM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x2d2, /* COM_FIPr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table925 */ 0x501, /* LOOPNE */ /* Table926 */ 0x500, /* LOOPE */ /* Table927 */ 0x4ff, /* LOOP */ /* Table928 */ 0x44a, /* JECXZ */ /* Table929 */ 0x3fd, /* IN8ri */ /* Table930 */ 0x3fb, /* IN32ri */ /* Table931 */ 0x757, /* OUT8ir */ /* Table932 */ 0x755, /* OUT32ir */ /* Table933 */ 0x1ee, /* CALLpcrel32 */ /* Table934 */ 0x468, /* JMP_4 */ /* Table935 */ 0x385, /* FARJMP32i */ /* Table936 */ 0x466, /* JMP_1 */ /* Table937 */ 0x3fe, /* IN8rr */ /* Table938 */ 0x3fc, /* IN32rr */ /* Table939 */ 0x758, /* OUT8rr */ /* Table940 */ 0x756, /* OUT32rr */ /* Table941 */ 0x4fa, /* LOCK_PREFIX */ /* Table942 */ 0x413, /* INT1 */ /* Table943 */ 0x924, /* REPNE_PREFIX */ /* Table944 */ 0x925, /* REP_PREFIX */ /* Table945 */ 0x3c6, /* HLT */ /* Table946 */ 0x202, /* CMC */ /* Table947 */ 0xb15, /* TEST8mi */ 0xb16, /* TEST8mi_alt */ 0x729, /* NOT8m */ 0x702, /* NEG8m */ 0x6d3, /* MUL8m */ 0x3f7, /* IMUL8m */ 0x33a, /* DIV8m */ 0x3d1, /* IDIV8m */ 0xb18, /* TEST8ri */ 0xb19, /* TEST8ri_alt */ 0x72a, /* NOT8r */ 0x703, /* NEG8r */ 0x6d4, /* MUL8r */ 0x3f8, /* IMUL8r */ 0x33b, /* DIV8r */ 0x3d2, /* IDIV8r */ /* Table963 */ 0xb07, /* TEST32mi */ 0xb08, /* TEST32mi_alt */ 0x725, /* NOT32m */ 0x6fe, /* NEG32m */ 0x6cf, /* MUL32m */ 0x3e7, /* IMUL32m */ 0x336, /* DIV32m */ 0x3cd, /* IDIV32m */ 0xb0a, /* TEST32ri */ 0xb0b, /* TEST32ri_alt */ 0x726, /* NOT32r */ 0x6ff, /* NEG32r */ 0x6d0, /* MUL32r */ 0x3e8, /* IMUL32r */ 0x337, /* DIV32r */ 0x3ce, /* IDIV32r */ /* Table979 */ 0x1f7, /* CLC */ /* Table980 */ 0xa7e, /* STC */ /* Table981 */ 0x1fd, /* CLI */ /* Table982 */ 0xa81, /* STI */ /* Table983 */ 0x1f8, /* CLD */ /* Table984 */ 0xa7f, /* STD */ /* Table985 */ 0x407, /* INC8m */ 0x332, /* DEC8m */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x408, /* INC8r */ 0x333, /* DEC8r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1001 */ 0x402, /* INC32m */ 0x32d, /* DEC32m */ 0x1e4, /* CALL32m */ 0x381, /* FARCALL32m */ 0x45e, /* JMP32m */ 0x386, /* FARJMP32m */ 0x8bd, /* PUSH32rmm */ 0x0, /* */ 0x403, /* INC32r */ 0x32e, /* DEC32r */ 0x1e6, /* CALL32r */ 0x0, /* */ 0x460, /* JMP32r */ 0x0, /* */ 0x8be, /* PUSH32rmr */ 0x0, /* */ /* Table1017 */ 0x92c, /* REX64_PREFIX */ /* Table1018 */ 0x8c1, /* PUSH64r */ /* Table1019 */ 0x842, /* POP64r */ /* Table1020 */ 0x8bf, /* PUSH64i32 */ /* Table1021 */ 0x8c0, /* PUSH64i8 */ /* Table1022 */ 0x4e1, /* LEA64_32r */ 0x0, /* */ /* Table1024 */ 0x843, /* POP64rmm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x844, /* POP64rmr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1040 */ 0x8ce, /* PUSHF64 */ /* Table1041 */ 0x853, /* POPF64 */ /* Table1042 */ 0x646, /* MOV8ao64 */ /* Table1043 */ 0x61e, /* MOV32ao64 */ /* Table1044 */ 0x64c, /* MOV8o64a */ /* Table1045 */ 0x625, /* MOV32o64a */ /* Table1046 */ 0x927, /* RETIQ */ /* Table1047 */ 0x92a, /* RETQ */ /* Table1048 */ 0x4e4, /* LEAVE64 */ /* Table1049 */ 0x47b, /* JRCXZ */ /* Table1050 */ 0x1ea, /* CALL64pcrel32 */ /* Table1051 */ 0x402, /* INC32m */ 0x32d, /* DEC32m */ 0x1e8, /* CALL64m */ 0x381, /* FARCALL32m */ 0x462, /* JMP64m */ 0x386, /* FARJMP32m */ 0x8c2, /* PUSH64rmm */ 0x0, /* */ 0x403, /* INC32r */ 0x32e, /* DEC32r */ 0x1eb, /* CALL64r */ 0x0, /* */ 0x464, /* JMP64r */ 0x0, /* */ 0x8c3, /* PUSH64rmr */ 0x0, /* */ /* Table1067 */ 0xc5, /* ADD16mr */ 0xc9, /* ADD16rr */ /* Table1069 */ 0xc8, /* ADD16rm */ 0xca, /* ADD16rr_REV */ /* Table1071 */ 0xc2, /* ADD16i16 */ /* Table1072 */ 0x8ca, /* PUSHES16 */ /* Table1073 */ 0x84f, /* POPES16 */ /* Table1074 */ 0x72e, /* OR16mr */ 0x732, /* OR16rr */ /* Table1076 */ 0x731, /* OR16rm */ 0x733, /* OR16rr_REV */ /* Table1078 */ 0x72b, /* OR16i16 */ /* Table1079 */ 0x8c6, /* PUSHCS16 */ /* Table1080 */ 0x9d, /* ADC16mr */ 0xa1, /* ADC16rr */ /* Table1082 */ 0xa0, /* ADC16rm */ 0xa2, /* ADC16rr_REV */ /* Table1084 */ 0x9a, /* ADC16i16 */ /* Table1085 */ 0x8d5, /* PUSHSS16 */ /* Table1086 */ 0x85a, /* POPSS16 */ /* Table1087 */ 0x9af, /* SBB16mr */ 0x9b3, /* SBB16rr */ /* Table1089 */ 0x9b2, /* SBB16rm */ 0x9b4, /* SBB16rr_REV */ /* Table1091 */ 0x9ac, /* SBB16i16 */ /* Table1092 */ 0x8c8, /* PUSHDS16 */ /* Table1093 */ 0x84d, /* POPDS16 */ /* Table1094 */ 0x11e, /* AND16mr */ 0x122, /* AND16rr */ /* Table1096 */ 0x121, /* AND16rm */ 0x123, /* AND16rr_REV */ /* Table1098 */ 0x11b, /* AND16i16 */ /* Table1099 */ 0xaa0, /* SUB16mr */ 0xaa4, /* SUB16rr */ /* Table1101 */ 0xaa3, /* SUB16rm */ 0xaa5, /* SUB16rr_REV */ /* Table1103 */ 0xa9d, /* SUB16i16 */ /* Table1104 */ 0x3b7e, /* XOR16mr */ 0x3b82, /* XOR16rr */ /* Table1106 */ 0x3b81, /* XOR16rm */ 0x3b83, /* XOR16rr_REV */ /* Table1108 */ 0x3b7b, /* XOR16i16 */ /* Table1109 */ 0x286, /* CMP16mr */ 0x28a, /* CMP16rr */ /* Table1111 */ 0x289, /* CMP16rm */ 0x28b, /* CMP16rr_REV */ /* Table1113 */ 0x283, /* CMP16i16 */ /* Table1114 */ 0x401, /* INC16r_alt */ /* Table1115 */ 0x32c, /* DEC16r_alt */ /* Table1116 */ 0x8b8, /* PUSH16r */ /* Table1117 */ 0x83c, /* POP16r */ /* Table1118 */ 0x8c4, /* PUSHA16 */ /* Table1119 */ 0x845, /* POPA16 */ /* Table1120 */ 0x19b, /* BOUNDS16rm */ 0x0, /* */ /* Table1122 */ 0x8d7, /* PUSHi16 */ /* Table1123 */ 0x3e2, /* IMUL16rmi */ 0x3e5, /* IMUL16rri */ /* Table1125 */ 0x8b7, /* PUSH16i8 */ /* Table1126 */ 0x3e3, /* IMUL16rmi8 */ 0x3e6, /* IMUL16rri8 */ /* Table1128 */ 0x411, /* INSW */ /* Table1129 */ 0x75b, /* OUTSW */ /* Table1130 */ 0xc3, /* ADD16mi */ 0x72c, /* OR16mi */ 0x9b, /* ADC16mi */ 0x9ad, /* SBB16mi */ 0x11c, /* AND16mi */ 0xa9e, /* SUB16mi */ 0x3b7c, /* XOR16mi */ 0x284, /* CMP16mi */ 0xc6, /* ADD16ri */ 0x72f, /* OR16ri */ 0x9e, /* ADC16ri */ 0x9b0, /* SBB16ri */ 0x11f, /* AND16ri */ 0xaa1, /* SUB16ri */ 0x3b7f, /* XOR16ri */ 0x287, /* CMP16ri */ /* Table1146 */ 0xc4, /* ADD16mi8 */ 0x72d, /* OR16mi8 */ 0x9c, /* ADC16mi8 */ 0x9ae, /* SBB16mi8 */ 0x11d, /* AND16mi8 */ 0xa9f, /* SUB16mi8 */ 0x3b7d, /* XOR16mi8 */ 0x285, /* CMP16mi8 */ 0xc7, /* ADD16ri8 */ 0x730, /* OR16ri8 */ 0x9f, /* ADC16ri8 */ 0x9b1, /* SBB16ri8 */ 0x120, /* AND16ri8 */ 0xaa2, /* SUB16ri8 */ 0x3b80, /* XOR16ri8 */ 0x288, /* CMP16ri8 */ /* Table1162 */ 0xb02, /* TEST16mr */ 0xb05, /* TEST16rr */ /* Table1164 */ 0x3b68, /* XCHG16rm */ 0x3b69, /* XCHG16rr */ /* Table1166 */ 0x60f, /* MOV16mr */ 0x617, /* MOV16rr */ /* Table1168 */ 0x616, /* MOV16rm */ 0x618, /* MOV16rr_REV */ /* Table1170 */ 0x610, /* MOV16ms */ 0x619, /* MOV16rs */ /* Table1172 */ 0x4df, /* LEA16r */ 0x0, /* */ /* Table1174 */ 0x61a, /* MOV16sm */ 0x61b, /* MOV16sr */ /* Table1176 */ 0x83d, /* POP16rmm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x83e, /* POP16rmr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1192 */ 0x3b67, /* XCHG16ar */ /* Table1193 */ 0x1ef, /* CBW */ /* Table1194 */ 0x325, /* CWD */ /* Table1195 */ 0x37e, /* FARCALL16i */ /* Table1196 */ 0x8cc, /* PUSHF16 */ /* Table1197 */ 0x851, /* POPF16 */ /* Table1198 */ 0x60c, /* MOV16ao32 */ /* Table1199 */ 0x612, /* MOV16o32a */ /* Table1200 */ 0x6a3, /* MOVSW */ /* Table1201 */ 0x2be, /* CMPSW */ /* Table1202 */ 0xaff, /* TEST16i16 */ /* Table1203 */ 0xa86, /* STOSW */ /* Table1204 */ 0x4fe, /* LODSW */ /* Table1205 */ 0x9d3, /* SCASW */ /* Table1206 */ 0x614, /* MOV16ri */ /* Table1207 */ 0x92f, /* ROL16mi */ 0x947, /* ROR16mi */ 0x8dd, /* RCL16mi */ 0x8fb, /* RCR16mi */ 0xa09, /* SHL16mi */ 0xa31, /* SHR16mi */ 0x978, /* SAL16mi */ 0x991, /* SAR16mi */ 0x932, /* ROL16ri */ 0x94a, /* ROR16ri */ 0x8e0, /* RCL16ri */ 0x8fe, /* RCR16ri */ 0xa0c, /* SHL16ri */ 0xa34, /* SHR16ri */ 0x97b, /* SAL16ri */ 0x994, /* SAR16ri */ /* Table1223 */ 0x928, /* RETIW */ /* Table1224 */ 0x92b, /* RETW */ /* Table1225 */ 0x4e5, /* LES16rm */ 0x0, /* */ /* Table1227 */ 0x4cb, /* LDS16rm */ 0x0, /* */ /* Table1229 */ 0x60e, /* MOV16mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x615, /* MOV16ri_alt */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b65, /* XBEGIN_2 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1301 */ 0x504, /* LRETIW */ /* Table1302 */ 0x507, /* LRETW */ /* Table1303 */ 0x420, /* IRET16 */ /* Table1304 */ 0x92d, /* ROL16m1 */ 0x945, /* ROR16m1 */ 0x8db, /* RCL16m1 */ 0x8f9, /* RCR16m1 */ 0xa07, /* SHL16m1 */ 0xa2f, /* SHR16m1 */ 0x976, /* SAL16m1 */ 0x98f, /* SAR16m1 */ 0x930, /* ROL16r1 */ 0x948, /* ROR16r1 */ 0x8de, /* RCL16r1 */ 0x8fc, /* RCR16r1 */ 0xa0a, /* SHL16r1 */ 0xa32, /* SHR16r1 */ 0x979, /* SAL16r1 */ 0x992, /* SAR16r1 */ /* Table1320 */ 0x92e, /* ROL16mCL */ 0x946, /* ROR16mCL */ 0x8dc, /* RCL16mCL */ 0x8fa, /* RCR16mCL */ 0xa08, /* SHL16mCL */ 0xa30, /* SHR16mCL */ 0x977, /* SAL16mCL */ 0x990, /* SAR16mCL */ 0x931, /* ROL16rCL */ 0x949, /* ROR16rCL */ 0x8df, /* RCL16rCL */ 0x8fd, /* RCR16rCL */ 0xa0b, /* SHL16rCL */ 0xa33, /* SHR16rCL */ 0x97a, /* SAL16rCL */ 0x993, /* SAR16rCL */ /* Table1336 */ 0x3f9, /* IN16ri */ /* Table1337 */ 0x753, /* OUT16ir */ /* Table1338 */ 0x1ed, /* CALLpcrel16 */ /* Table1339 */ 0x467, /* JMP_2 */ /* Table1340 */ 0x383, /* FARJMP16i */ /* Table1341 */ 0x3fa, /* IN16rr */ /* Table1342 */ 0x754, /* OUT16rr */ /* Table1343 */ 0xb00, /* TEST16mi */ 0xb01, /* TEST16mi_alt */ 0x723, /* NOT16m */ 0x6fc, /* NEG16m */ 0x6cd, /* MUL16m */ 0x3df, /* IMUL16m */ 0x334, /* DIV16m */ 0x3cb, /* IDIV16m */ 0xb03, /* TEST16ri */ 0xb04, /* TEST16ri_alt */ 0x724, /* NOT16r */ 0x6fd, /* NEG16r */ 0x6ce, /* MUL16r */ 0x3e0, /* IMUL16r */ 0x335, /* DIV16r */ 0x3cc, /* IDIV16r */ /* Table1359 */ 0x3ff, /* INC16m */ 0x32a, /* DEC16m */ 0x1e0, /* CALL16m */ 0x37f, /* FARCALL16m */ 0x45a, /* JMP16m */ 0x384, /* FARJMP16m */ 0x8b9, /* PUSH16rmm */ 0x0, /* */ 0x400, /* INC16r */ 0x32b, /* DEC16r */ 0x1e2, /* CALL16r */ 0x0, /* */ 0x45c, /* JMP16r */ 0x0, /* */ 0x8ba, /* PUSH16rmr */ 0x0, /* */ /* Table1375 */ 0x644, /* MOV8ao16 */ /* Table1376 */ 0x61c, /* MOV32ao16 */ /* Table1377 */ 0x64a, /* MOV8o16a */ /* Table1378 */ 0x623, /* MOV32o16a */ /* Table1379 */ 0x449, /* JCXZ */ /* Table1380 */ 0x60b, /* MOV16ao16 */ /* Table1381 */ 0x611, /* MOV16o16a */ /* Table1382 */ 0x780, /* PAUSE */ /* Table1383 */ 0xd7, /* ADD64mr */ 0xdb, /* ADD64rr */ /* Table1385 */ 0xda, /* ADD64rm */ 0xdc, /* ADD64rr_REV */ /* Table1387 */ 0xd4, /* ADD64i32 */ /* Table1388 */ 0x740, /* OR64mr */ 0x744, /* OR64rr */ /* Table1390 */ 0x743, /* OR64rm */ 0x745, /* OR64rr_REV */ /* Table1392 */ 0x73d, /* OR64i32 */ /* Table1393 */ 0xaf, /* ADC64mr */ 0xb3, /* ADC64rr */ /* Table1395 */ 0xb2, /* ADC64rm */ 0xb4, /* ADC64rr_REV */ /* Table1397 */ 0xac, /* ADC64i32 */ /* Table1398 */ 0x9c1, /* SBB64mr */ 0x9c5, /* SBB64rr */ /* Table1400 */ 0x9c4, /* SBB64rm */ 0x9c6, /* SBB64rr_REV */ /* Table1402 */ 0x9be, /* SBB64i32 */ /* Table1403 */ 0x130, /* AND64mr */ 0x134, /* AND64rr */ /* Table1405 */ 0x133, /* AND64rm */ 0x135, /* AND64rr_REV */ /* Table1407 */ 0x12d, /* AND64i32 */ /* Table1408 */ 0xab2, /* SUB64mr */ 0xab6, /* SUB64rr */ /* Table1410 */ 0xab5, /* SUB64rm */ 0xab7, /* SUB64rr_REV */ /* Table1412 */ 0xaaf, /* SUB64i32 */ /* Table1413 */ 0x3b90, /* XOR64mr */ 0x3b94, /* XOR64rr */ /* Table1415 */ 0x3b93, /* XOR64rm */ 0x3b95, /* XOR64rr_REV */ /* Table1417 */ 0x3b8d, /* XOR64i32 */ /* Table1418 */ 0x298, /* CMP64mr */ 0x29c, /* CMP64rr */ /* Table1420 */ 0x29b, /* CMP64rm */ 0x29d, /* CMP64rr_REV */ /* Table1422 */ 0x295, /* CMP64i32 */ /* Table1423 */ 0x6af, /* MOVSX64rm32 */ 0x6b2, /* MOVSX64rr32 */ /* Table1425 */ 0x3f2, /* IMUL64rmi32 */ 0x3f5, /* IMUL64rri32 */ /* Table1427 */ 0x3f3, /* IMUL64rmi8 */ 0x3f6, /* IMUL64rri8 */ /* Table1429 */ 0xd5, /* ADD64mi32 */ 0x73e, /* OR64mi32 */ 0xad, /* ADC64mi32 */ 0x9bf, /* SBB64mi32 */ 0x12e, /* AND64mi32 */ 0xab0, /* SUB64mi32 */ 0x3b8e, /* XOR64mi32 */ 0x296, /* CMP64mi32 */ 0xd8, /* ADD64ri32 */ 0x741, /* OR64ri32 */ 0xb0, /* ADC64ri32 */ 0x9c2, /* SBB64ri32 */ 0x131, /* AND64ri32 */ 0xab3, /* SUB64ri32 */ 0x3b91, /* XOR64ri32 */ 0x299, /* CMP64ri32 */ /* Table1445 */ 0xd6, /* ADD64mi8 */ 0x73f, /* OR64mi8 */ 0xae, /* ADC64mi8 */ 0x9c0, /* SBB64mi8 */ 0x12f, /* AND64mi8 */ 0xab1, /* SUB64mi8 */ 0x3b8f, /* XOR64mi8 */ 0x297, /* CMP64mi8 */ 0xd9, /* ADD64ri8 */ 0x742, /* OR64ri8 */ 0xb1, /* ADC64ri8 */ 0x9c3, /* SBB64ri8 */ 0x132, /* AND64ri8 */ 0xab4, /* SUB64ri8 */ 0x3b92, /* XOR64ri8 */ 0x29a, /* CMP64ri8 */ /* Table1461 */ 0xb10, /* TEST64mr */ 0xb13, /* TEST64rr */ /* Table1463 */ 0x3b6e, /* XCHG64rm */ 0x3b6f, /* XCHG64rr */ /* Table1465 */ 0x634, /* MOV64mr */ 0x63c, /* MOV64rr */ /* Table1467 */ 0x63b, /* MOV64rm */ 0x63d, /* MOV64rr_REV */ /* Table1469 */ 0x610, /* MOV16ms */ 0x63e, /* MOV64rs */ /* Table1471 */ 0x4e2, /* LEA64r */ 0x0, /* */ /* Table1473 */ 0x61a, /* MOV16sm */ 0x63f, /* MOV64sr */ /* Table1475 */ 0x3b6d, /* XCHG64ar */ /* Table1476 */ 0x1f1, /* CDQE */ /* Table1477 */ 0x2da, /* CQO */ /* Table1478 */ 0x630, /* MOV64ao64 */ /* Table1479 */ 0x636, /* MOV64o64a */ /* Table1480 */ 0x69c, /* MOVSQ */ /* Table1481 */ 0x2b7, /* CMPSQ */ /* Table1482 */ 0xb0d, /* TEST64i32 */ /* Table1483 */ 0xa85, /* STOSQ */ /* Table1484 */ 0x4fd, /* LODSQ */ /* Table1485 */ 0x9d2, /* SCASQ */ /* Table1486 */ 0x639, /* MOV64ri */ /* Table1487 */ 0x93b, /* ROL64mi */ 0x953, /* ROR64mi */ 0x8e9, /* RCL64mi */ 0x907, /* RCR64mi */ 0xa15, /* SHL64mi */ 0xa3d, /* SHR64mi */ 0x984, /* SAL64mi */ 0x99d, /* SAR64mi */ 0x93e, /* ROL64ri */ 0x956, /* ROR64ri */ 0x8ec, /* RCL64ri */ 0x90a, /* RCR64ri */ 0xa18, /* SHL64ri */ 0xa40, /* SHR64ri */ 0x987, /* SAL64ri */ 0x9a0, /* SAR64ri */ /* Table1503 */ 0x633, /* MOV64mi32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b66, /* XBEGIN_4 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1575 */ 0x503, /* LRETIQ */ /* Table1576 */ 0x506, /* LRETQ */ /* Table1577 */ 0x422, /* IRET64 */ /* Table1578 */ 0x939, /* ROL64m1 */ 0x951, /* ROR64m1 */ 0x8e7, /* RCL64m1 */ 0x905, /* RCR64m1 */ 0xa13, /* SHL64m1 */ 0xa3b, /* SHR64m1 */ 0x982, /* SAL64m1 */ 0x99b, /* SAR64m1 */ 0x93c, /* ROL64r1 */ 0x954, /* ROR64r1 */ 0x8ea, /* RCL64r1 */ 0x908, /* RCR64r1 */ 0xa16, /* SHL64r1 */ 0xa3e, /* SHR64r1 */ 0x985, /* SAL64r1 */ 0x99e, /* SAR64r1 */ /* Table1594 */ 0x93a, /* ROL64mCL */ 0x952, /* ROR64mCL */ 0x8e8, /* RCL64mCL */ 0x906, /* RCR64mCL */ 0xa14, /* SHL64mCL */ 0xa3c, /* SHR64mCL */ 0x983, /* SAL64mCL */ 0x99c, /* SAR64mCL */ 0x93d, /* ROL64rCL */ 0x955, /* ROR64rCL */ 0x8eb, /* RCL64rCL */ 0x909, /* RCR64rCL */ 0xa17, /* SHL64rCL */ 0xa3f, /* SHR64rCL */ 0x986, /* SAL64rCL */ 0x99f, /* SAR64rCL */ /* Table1610 */ 0xb0e, /* TEST64mi32 */ 0xb0f, /* TEST64mi32_alt */ 0x727, /* NOT64m */ 0x700, /* NEG64m */ 0x6d1, /* MUL64m */ 0x3ef, /* IMUL64m */ 0x338, /* DIV64m */ 0x3cf, /* IDIV64m */ 0xb11, /* TEST64ri32 */ 0xb12, /* TEST64ri32_alt */ 0x728, /* NOT64r */ 0x701, /* NEG64r */ 0x6d2, /* MUL64r */ 0x3f0, /* IMUL64r */ 0x339, /* DIV64r */ 0x3d0, /* IDIV64r */ /* Table1626 */ 0x405, /* INC64m */ 0x330, /* DEC64m */ 0x1e8, /* CALL64m */ 0x382, /* FARCALL64 */ 0x462, /* JMP64m */ 0x387, /* FARJMP64 */ 0x8c2, /* PUSH64rmm */ 0x0, /* */ 0x406, /* INC64r */ 0x331, /* DEC64r */ 0x1eb, /* CALL64r */ 0x0, /* */ 0x464, /* JMP64r */ 0x0, /* */ 0x8c3, /* PUSH64rmr */ 0x0, /* */ /* Table1642 */ 0x62f, /* MOV64ao32 */ /* Table1643 */ 0x635, /* MOV64o32a */ /* Table1644 */ 0x633, /* MOV64mi32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x63a, /* MOV64ri32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b65, /* XBEGIN_2 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1716 */ 0x405, /* INC64m */ 0x330, /* DEC64m */ 0x1e8, /* CALL64m */ 0x382, /* FARCALL64 */ 0x462, /* JMP64m */ 0x387, /* FARJMP64 */ 0x8b9, /* PUSH16rmm */ 0x0, /* */ 0x406, /* INC64r */ 0x331, /* DEC64r */ 0x1eb, /* CALL64r */ 0x0, /* */ 0x464, /* JMP64r */ 0x0, /* */ 0x8ba, /* PUSH16rmr */ 0x0, /* */ /* Table1732 */ 0x60d, /* MOV16ao64 */ /* Table1733 */ 0x613, /* MOV16o64a */ /* Table1734 */ 0x3ff, /* INC16m */ 0x32a, /* DEC16m */ 0x1e8, /* CALL64m */ 0x37f, /* FARCALL16m */ 0x462, /* JMP64m */ 0x384, /* FARJMP16m */ 0x8b9, /* PUSH16rmm */ 0x0, /* */ 0x400, /* INC16r */ 0x32b, /* DEC16r */ 0x1eb, /* CALL64r */ 0x0, /* */ 0x464, /* JMP64r */ 0x0, /* */ 0x8ba, /* PUSH16rmr */ 0x0, /* */ /* Table1750 */ 0xa63, /* SLDT16m */ 0xa8a, /* STRm */ 0x4f4, /* LLDT16m */ 0x511, /* LTRm */ 0x1282, /* VERRm */ 0x1284, /* VERWm */ 0x0, /* */ 0x0, /* */ 0xa65, /* SLDT32r */ 0xa88, /* STR32r */ 0x4f5, /* LLDT16r */ 0x512, /* LTRr */ 0x1283, /* VERRr */ 0x1285, /* VERWr */ 0x0, /* */ 0x0, /* */ /* Table1766 */ 0x9f7, /* SGDT32m */ 0xa5c, /* SIDT32m */ 0x4ec, /* LGDT32m */ 0x4f2, /* LIDT32m */ 0xa69, /* SMSW16m */ 0x0, /* */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7d, /* VMRUN32 */ 0x1d43, /* VMMCALL */ 0x1d41, /* VMLOAD32 */ 0x1f7f, /* VMSAVE32 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41a, /* INVLPGA32 */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1838 */ 0x4c5, /* LAR32rm */ 0x4c6, /* LAR32rr */ /* Table1840 */ 0x50a, /* LSL32rm */ 0x50b, /* LSL32rr */ /* Table1842 */ 0xaf5, /* SYSCALL */ /* Table1843 */ 0x1ff, /* CLTS */ /* Table1844 */ 0xaf9, /* SYSRET */ /* Table1845 */ 0x416, /* INVD */ /* Table1846 */ 0x3b4f, /* WBINVD */ /* Table1847 */ 0xb3f, /* UD2 */ /* Table1848 */ 0x85e, /* PREFETCH */ 0x863, /* PREFETCHW */ 0x864, /* PREFETCHWT1 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1864 */ 0x391, /* FEMMS */ /* Table1865 */ 0x6b9, /* MOVUPSrm */ 0x6ba, /* MOVUPSrr */ /* Table1867 */ 0x6b8, /* MOVUPSmr */ 0x6bb, /* MOVUPSrr_REV */ /* Table1869 */ 0x67e, /* MOVLPSrm */ 0x675, /* MOVHLPSrr */ /* Table1871 */ 0x67d, /* MOVLPSmr */ 0x0, /* */ /* Table1873 */ 0xb4a, /* UNPCKLPSrm */ 0xb4b, /* UNPCKLPSrr */ /* Table1875 */ 0xb46, /* UNPCKHPSrm */ 0xb47, /* UNPCKHPSrr */ /* Table1877 */ 0x679, /* MOVHPSrm */ 0x67a, /* MOVLHPSrr */ /* Table1879 */ 0x678, /* MOVHPSmr */ 0x0, /* */ /* Table1881 */ 0x85f, /* PREFETCHNTA */ 0x860, /* PREFETCHT0 */ 0x861, /* PREFETCHT1 */ 0x862, /* PREFETCHT2 */ 0x70d, /* NOOP18_m4 */ 0x70e, /* NOOP18_m5 */ 0x70f, /* NOOP18_m6 */ 0x710, /* NOOP18_m7 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x711, /* NOOP18_r4 */ 0x712, /* NOOP18_r5 */ 0x713, /* NOOP18_r6 */ 0x714, /* NOOP18_r7 */ /* Table1897 */ 0x717, /* NOOPL_19 */ 0x715, /* NOOP19rr */ /* Table1899 */ 0x191, /* BNDLDXrm */ 0x0, /* */ /* Table1901 */ 0x19a, /* BNDSTXmr */ 0x0, /* */ /* Table1903 */ 0x1f9, /* CLDEMOTE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1919 */ 0x718, /* NOOPL_1d */ 0x0, /* */ /* Table1921 */ 0x719, /* NOOPL_1e */ 0x0, /* */ /* Table1923 */ 0x716, /* NOOPL */ 0x71a, /* NOOPLr */ /* Table1925 */ 0x0, /* */ 0x626, /* MOV32rc */ /* Table1927 */ 0x0, /* */ 0x627, /* MOV32rd */ /* Table1929 */ 0x0, /* */ 0x61f, /* MOV32cr */ /* Table1931 */ 0x0, /* */ 0x620, /* MOV32dr */ /* Table1933 */ 0x659, /* MOVAPSrm */ 0x65a, /* MOVAPSrr */ /* Table1935 */ 0x658, /* MOVAPSmr */ 0x65b, /* MOVAPSrr_REV */ /* Table1937 */ 0x550, /* MMX_CVTPI2PSirm */ 0x551, /* MMX_CVTPI2PSirr */ /* Table1939 */ 0x686, /* MOVNTPSmr */ 0x0, /* */ /* Table1941 */ 0x556, /* MMX_CVTTPS2PIirm */ 0x557, /* MMX_CVTTPS2PIirr */ /* Table1943 */ 0x552, /* MMX_CVTPS2PIirm */ 0x553, /* MMX_CVTPS2PIirr */ /* Table1945 */ 0xb2e, /* UCOMISSrm */ 0xb30, /* UCOMISSrr */ /* Table1947 */ 0x2cd, /* COMISSrm */ 0x2cf, /* COMISSrr */ /* Table1949 */ 0x3b55, /* WRMSR */ /* Table1950 */ 0x922, /* RDTSC */ /* Table1951 */ 0x915, /* RDMSR */ /* Table1952 */ 0x919, /* RDPMC */ /* Table1953 */ 0xaf6, /* SYSENTER */ /* Table1954 */ 0xaf7, /* SYSEXIT */ /* Table1955 */ 0x3bb, /* GETSEC */ /* Table1956 */ 0x26f, /* CMOVO32rm */ 0x270, /* CMOVO32rr */ /* Table1958 */ 0x259, /* CMOVNO32rm */ 0x25a, /* CMOVNO32rr */ /* Table1960 */ 0x211, /* CMOVB32rm */ 0x212, /* CMOVB32rr */ /* Table1962 */ 0x20b, /* CMOVAE32rm */ 0x20c, /* CMOVAE32rr */ /* Table1964 */ 0x225, /* CMOVE32rm */ 0x226, /* CMOVE32rr */ /* Table1966 */ 0x24f, /* CMOVNE32rm */ 0x250, /* CMOVNE32rr */ /* Table1968 */ 0x217, /* CMOVBE32rm */ 0x218, /* CMOVBE32rr */ /* Table1970 */ 0x205, /* CMOVA32rm */ 0x206, /* CMOVA32rr */ /* Table1972 */ 0x27f, /* CMOVS32rm */ 0x280, /* CMOVS32rr */ /* Table1974 */ 0x269, /* CMOVNS32rm */ 0x26a, /* CMOVNS32rr */ /* Table1976 */ 0x275, /* CMOVP32rm */ 0x276, /* CMOVP32rr */ /* Table1978 */ 0x25f, /* CMOVNP32rm */ 0x260, /* CMOVNP32rr */ /* Table1980 */ 0x23b, /* CMOVL32rm */ 0x23c, /* CMOVL32rr */ /* Table1982 */ 0x235, /* CMOVGE32rm */ 0x236, /* CMOVGE32rr */ /* Table1984 */ 0x241, /* CMOVLE32rm */ 0x242, /* CMOVLE32rr */ /* Table1986 */ 0x22f, /* CMOVG32rm */ 0x230, /* CMOVG32rr */ /* Table1988 */ 0x0, /* */ 0x680, /* MOVMSKPSrr */ /* Table1990 */ 0xa6f, /* SQRTPSm */ 0xa70, /* SQRTPSr */ /* Table1992 */ 0x96e, /* RSQRTPSm */ 0x96f, /* RSQRTPSr */ /* Table1994 */ 0x8f3, /* RCPPSm */ 0x8f4, /* RCPPSr */ /* Table1996 */ 0x149, /* ANDPSrm */ 0x14a, /* ANDPSrr */ /* Table1998 */ 0x145, /* ANDNPSrm */ 0x146, /* ANDNPSrr */ /* Table2000 */ 0x751, /* ORPSrm */ 0x752, /* ORPSrr */ /* Table2002 */ 0x3ba1, /* XORPSrm */ 0x3ba2, /* XORPSrr */ /* Table2004 */ 0xe8, /* ADDPSrm */ 0xe9, /* ADDPSrr */ /* Table2006 */ 0x6d7, /* MULPSrm */ 0x6d8, /* MULPSrr */ /* Table2008 */ 0x2ef, /* CVTPS2PDrm */ 0x2f0, /* CVTPS2PDrr */ /* Table2010 */ 0x2e7, /* CVTDQ2PSrm */ 0x2e8, /* CVTDQ2PSrr */ /* Table2012 */ 0xac3, /* SUBPSrm */ 0xac4, /* SUBPSrr */ /* Table2014 */ 0x542, /* MINPSrm */ 0x543, /* MINPSrr */ /* Table2016 */ 0x33e, /* DIVPSrm */ 0x33f, /* DIVPSrr */ /* Table2018 */ 0x52d, /* MAXPSrm */ 0x52e, /* MAXPSrr */ /* Table2020 */ 0x600, /* MMX_PUNPCKLBWirm */ 0x601, /* MMX_PUNPCKLBWirr */ /* Table2022 */ 0x604, /* MMX_PUNPCKLWDirm */ 0x605, /* MMX_PUNPCKLWDirr */ /* Table2024 */ 0x602, /* MMX_PUNPCKLDQirm */ 0x603, /* MMX_PUNPCKLDQirr */ /* Table2026 */ 0x574, /* MMX_PACKSSWBirm */ 0x575, /* MMX_PACKSSWBirr */ /* Table2028 */ 0x598, /* MMX_PCMPGTBirm */ 0x599, /* MMX_PCMPGTBirr */ /* Table2030 */ 0x59c, /* MMX_PCMPGTWirm */ 0x59d, /* MMX_PCMPGTWirr */ /* Table2032 */ 0x59a, /* MMX_PCMPGTDirm */ 0x59b, /* MMX_PCMPGTDirr */ /* Table2034 */ 0x576, /* MMX_PACKUSWBirm */ 0x577, /* MMX_PACKUSWBirr */ /* Table2036 */ 0x5fa, /* MMX_PUNPCKHBWirm */ 0x5fb, /* MMX_PUNPCKHBWirr */ /* Table2038 */ 0x5fe, /* MMX_PUNPCKHWDirm */ 0x5ff, /* MMX_PUNPCKHWDirr */ /* Table2040 */ 0x5fc, /* MMX_PUNPCKHDQirm */ 0x5fd, /* MMX_PUNPCKHDQirr */ /* Table2042 */ 0x572, /* MMX_PACKSSDWirm */ 0x573, /* MMX_PACKSSDWirr */ /* Table2044 */ 0x55f, /* MMX_MOVD64rm */ 0x560, /* MMX_MOVD64rr */ /* Table2046 */ 0x569, /* MMX_MOVQ64rm */ 0x56a, /* MMX_MOVQ64rr */ /* Table2048 */ 0x5ca, /* MMX_PSHUFWmi */ 0x5cb, /* MMX_PSHUFWri */ /* Table2050 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5e7, /* MMX_PSRLWri */ 0x0, /* */ 0x5de, /* MMX_PSRAWri */ 0x0, /* */ 0x5d8, /* MMX_PSLLWri */ 0x0, /* */ /* Table2066 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5e1, /* MMX_PSRLDri */ 0x0, /* */ 0x5db, /* MMX_PSRADri */ 0x0, /* */ 0x5d2, /* MMX_PSLLDri */ 0x0, /* */ /* Table2082 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5e4, /* MMX_PSRLQri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5d5, /* MMX_PSLLQri */ 0x0, /* */ /* Table2098 */ 0x592, /* MMX_PCMPEQBirm */ 0x593, /* MMX_PCMPEQBirr */ /* Table2100 */ 0x596, /* MMX_PCMPEQWirm */ 0x597, /* MMX_PCMPEQWirr */ /* Table2102 */ 0x594, /* MMX_PCMPEQDirm */ 0x595, /* MMX_PCMPEQDirr */ /* Table2104 */ 0x558, /* MMX_EMMS */ /* Table2105 */ 0x1f78, /* VMREAD32mr */ 0x1f79, /* VMREAD32rr */ /* Table2107 */ 0x1fe3, /* VMWRITE32rm */ 0x1fe4, /* VMWRITE32rr */ /* Table2109 */ 0x55e, /* MMX_MOVD64mr */ 0x55d, /* MMX_MOVD64grr */ /* Table2111 */ 0x568, /* MMX_MOVQ64mr */ 0x56b, /* MMX_MOVQ64rr_REV */ /* Table2113 */ 0x477, /* JO_4 */ /* Table2114 */ 0x46e, /* JNO_4 */ /* Table2115 */ 0x448, /* JB_4 */ /* Table2116 */ 0x43f, /* JAE_4 */ /* Table2117 */ 0x44d, /* JE_4 */ /* Table2118 */ 0x46b, /* JNE_4 */ /* Table2119 */ 0x445, /* JBE_4 */ /* Table2120 */ 0x442, /* JA_4 */ /* Table2121 */ 0x47e, /* JS_4 */ /* Table2122 */ 0x474, /* JNS_4 */ /* Table2123 */ 0x47a, /* JP_4 */ /* Table2124 */ 0x471, /* JNP_4 */ /* Table2125 */ 0x459, /* JL_4 */ /* Table2126 */ 0x450, /* JGE_4 */ /* Table2127 */ 0x456, /* JLE_4 */ /* Table2128 */ 0x453, /* JG_4 */ /* Table2129 */ 0x9ee, /* SETOm */ 0x9ef, /* SETOr */ /* Table2131 */ 0x9e8, /* SETNOm */ 0x9e9, /* SETNOr */ /* Table2133 */ 0x9da, /* SETBm */ 0x9db, /* SETBr */ /* Table2135 */ 0x9d4, /* SETAEm */ 0x9d5, /* SETAEr */ /* Table2137 */ 0x9dc, /* SETEm */ 0x9dd, /* SETEr */ /* Table2139 */ 0x9e6, /* SETNEm */ 0x9e7, /* SETNEr */ /* Table2141 */ 0x9d8, /* SETBEm */ 0x9d9, /* SETBEr */ /* Table2143 */ 0x9d6, /* SETAm */ 0x9d7, /* SETAr */ /* Table2145 */ 0x9f3, /* SETSm */ 0x9f4, /* SETSr */ /* Table2147 */ 0x9ec, /* SETNSm */ 0x9ed, /* SETNSr */ /* Table2149 */ 0x9f0, /* SETPm */ 0x9f1, /* SETPr */ /* Table2151 */ 0x9ea, /* SETNPm */ 0x9eb, /* SETNPr */ /* Table2153 */ 0x9e4, /* SETLm */ 0x9e5, /* SETLr */ /* Table2155 */ 0x9de, /* SETGEm */ 0x9df, /* SETGEr */ /* Table2157 */ 0x9e2, /* SETLEm */ 0x9e3, /* SETLEr */ /* Table2159 */ 0x9e0, /* SETGm */ 0x9e1, /* SETGr */ /* Table2161 */ 0x8d0, /* PUSHFS32 */ /* Table2162 */ 0x855, /* POPFS32 */ /* Table2163 */ 0x2d9, /* CPUID */ /* Table2164 */ 0x1b1, /* BT32mr */ 0x1b3, /* BT32rr */ /* Table2166 */ 0xa24, /* SHLD32mri8 */ 0xa26, /* SHLD32rri8 */ /* Table2168 */ 0xa23, /* SHLD32mrCL */ 0xa25, /* SHLD32rrCL */ /* Table2170 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x60a, /* MONTMUL */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3bb1, /* XSHA1 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3bb2, /* XSHA256 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2242 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3bb3, /* XSTORE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b76, /* XCRYPTECB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b73, /* XCRYPTCBC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b75, /* XCRYPTCTR */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b74, /* XCRYPTCFB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b77, /* XCRYPTOFB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2314 */ 0x8d3, /* PUSHGS32 */ /* Table2315 */ 0x858, /* POPGS32 */ /* Table2316 */ 0x96d, /* RSM */ /* Table2317 */ 0x1d5, /* BTS32mr */ 0x1d7, /* BTS32rr */ /* Table2319 */ 0xa4c, /* SHRD32mri8 */ 0xa4e, /* SHRD32rri8 */ /* Table2321 */ 0xa4b, /* SHRD32mrCL */ 0xa4d, /* SHRD32rrCL */ /* Table2323 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x3ba8, /* XSAVE */ 0x3ba4, /* XRSTOR */ 0x3bac, /* XSAVEOPT */ 0x1fa, /* CLFLUSH */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4e7, /* LFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x537, /* MFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2395 */ 0x3e9, /* IMUL32rm */ 0x3ec, /* IMUL32rr */ /* Table2397 */ 0x2c7, /* CMPXCHG8rm */ 0x2c8, /* CMPXCHG8rr */ /* Table2399 */ 0x2c2, /* CMPXCHG32rm */ 0x2c3, /* CMPXCHG32rr */ /* Table2401 */ 0x50f, /* LSS32rm */ 0x0, /* */ /* Table2403 */ 0x1c9, /* BTR32mr */ 0x1cb, /* BTR32rr */ /* Table2405 */ 0x4e9, /* LFS32rm */ 0x0, /* */ /* Table2407 */ 0x4ef, /* LGS32rm */ 0x0, /* */ /* Table2409 */ 0x6c2, /* MOVZX32rm8 */ 0x6c5, /* MOVZX32rr8 */ /* Table2411 */ 0x6c1, /* MOVZX32rm16 */ 0x6c4, /* MOVZX32rr16 */ /* Table2413 */ 0xb3e, /* UD1 */ /* Table2414 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x1b0, /* BT32mi8 */ 0x1d4, /* BTS32mi8 */ 0x1c8, /* BTR32mi8 */ 0x1bc, /* BTC32mi8 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x1b2, /* BT32ri8 */ 0x1d6, /* BTS32ri8 */ 0x1ca, /* BTR32ri8 */ 0x1be, /* BTC32ri8 */ /* Table2430 */ 0x1bd, /* BTC32mr */ 0x1bf, /* BTC32rr */ /* Table2432 */ 0x19f, /* BSF32rm */ 0x1a0, /* BSF32rr */ /* Table2434 */ 0x1a5, /* BSR32rm */ 0x1a6, /* BSR32rr */ /* Table2436 */ 0x6a9, /* MOVSX32rm8 */ 0x6ac, /* MOVSX32rr8 */ /* Table2438 */ 0x6a8, /* MOVSX32rm16 */ 0x6ab, /* MOVSX32rr16 */ /* Table2440 */ 0x3b63, /* XADD8rm */ 0x3b64, /* XADD8rr */ /* Table2442 */ 0x3b5f, /* XADD32rm */ 0x3b60, /* XADD32rr */ /* Table2444 */ 0x2ab, /* CMPPSrmi */ 0x2ad, /* CMPPSrri */ /* Table2446 */ 0x684, /* MOVNTImr */ 0x0, /* */ /* Table2448 */ 0x5ab, /* MMX_PINSRWrm */ 0x5ac, /* MMX_PINSRWrr */ /* Table2450 */ 0x0, /* */ 0x59e, /* MMX_PEXTRWrr */ /* Table2452 */ 0xa59, /* SHUFPSrmi */ 0xa5a, /* SHUFPSrri */ /* Table2454 */ 0x0, /* */ 0x2c6, /* CMPXCHG8B */ 0x0, /* */ 0x3ba6, /* XRSTORS */ 0x3baa, /* XSAVEC */ 0x3bae, /* XSAVES */ 0x1f76, /* VMPTRLDm */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91b, /* RDRAND32r */ 0x91e, /* RDSEED32r */ /* Table2470 */ 0x1aa, /* BSWAP32r */ /* Table2471 */ 0x5e8, /* MMX_PSRLWrm */ 0x5e9, /* MMX_PSRLWrr */ /* Table2473 */ 0x5e2, /* MMX_PSRLDrm */ 0x5e3, /* MMX_PSRLDrr */ /* Table2475 */ 0x5e5, /* MMX_PSRLQrm */ 0x5e6, /* MMX_PSRLQrr */ /* Table2477 */ 0x57c, /* MMX_PADDQirm */ 0x57d, /* MMX_PADDQirr */ /* Table2479 */ 0x5c0, /* MMX_PMULLWirm */ 0x5c1, /* MMX_PMULLWirr */ /* Table2481 */ 0x0, /* */ 0x5b9, /* MMX_PMOVMSKBrr */ /* Table2483 */ 0x5f4, /* MMX_PSUBUSBirm */ 0x5f5, /* MMX_PSUBUSBirr */ /* Table2485 */ 0x5f6, /* MMX_PSUBUSWirm */ 0x5f7, /* MMX_PSUBUSWirr */ /* Table2487 */ 0x5b7, /* MMX_PMINUBirm */ 0x5b8, /* MMX_PMINUBirr */ /* Table2489 */ 0x58c, /* MMX_PANDirm */ 0x58d, /* MMX_PANDirr */ /* Table2491 */ 0x582, /* MMX_PADDUSBirm */ 0x583, /* MMX_PADDUSBirr */ /* Table2493 */ 0x584, /* MMX_PADDUSWirm */ 0x585, /* MMX_PADDUSWirr */ /* Table2495 */ 0x5b3, /* MMX_PMAXUBirm */ 0x5b4, /* MMX_PMAXUBirr */ /* Table2497 */ 0x58a, /* MMX_PANDNirm */ 0x58b, /* MMX_PANDNirr */ /* Table2499 */ 0x58e, /* MMX_PAVGBirm */ 0x58f, /* MMX_PAVGBirr */ /* Table2501 */ 0x5df, /* MMX_PSRAWrm */ 0x5e0, /* MMX_PSRAWrr */ /* Table2503 */ 0x5dc, /* MMX_PSRADrm */ 0x5dd, /* MMX_PSRADrr */ /* Table2505 */ 0x590, /* MMX_PAVGWirm */ 0x591, /* MMX_PAVGWirr */ /* Table2507 */ 0x5bc, /* MMX_PMULHUWirm */ 0x5bd, /* MMX_PMULHUWirr */ /* Table2509 */ 0x5be, /* MMX_PMULHWirm */ 0x5bf, /* MMX_PMULHWirr */ /* Table2511 */ 0x565, /* MMX_MOVNTQmr */ 0x0, /* */ /* Table2513 */ 0x5f0, /* MMX_PSUBSBirm */ 0x5f1, /* MMX_PSUBSBirr */ /* Table2515 */ 0x5f2, /* MMX_PSUBSWirm */ 0x5f3, /* MMX_PSUBSWirr */ /* Table2517 */ 0x5b5, /* MMX_PMINSWirm */ 0x5b6, /* MMX_PMINSWirr */ /* Table2519 */ 0x5c4, /* MMX_PORirm */ 0x5c5, /* MMX_PORirr */ /* Table2521 */ 0x57e, /* MMX_PADDSBirm */ 0x57f, /* MMX_PADDSBirr */ /* Table2523 */ 0x580, /* MMX_PADDSWirm */ 0x581, /* MMX_PADDSWirr */ /* Table2525 */ 0x5b1, /* MMX_PMAXSWirm */ 0x5b2, /* MMX_PMAXSWirr */ /* Table2527 */ 0x606, /* MMX_PXORirm */ 0x607, /* MMX_PXORirr */ /* Table2529 */ 0x5d9, /* MMX_PSLLWrm */ 0x5da, /* MMX_PSLLWrr */ /* Table2531 */ 0x5d3, /* MMX_PSLLDrm */ 0x5d4, /* MMX_PSLLDrr */ /* Table2533 */ 0x5d6, /* MMX_PSLLQrm */ 0x5d7, /* MMX_PSLLQrr */ /* Table2535 */ 0x5c2, /* MMX_PMULUDQirm */ 0x5c3, /* MMX_PMULUDQirr */ /* Table2537 */ 0x5af, /* MMX_PMADDWDirm */ 0x5b0, /* MMX_PMADDWDirr */ /* Table2539 */ 0x5c6, /* MMX_PSADBWirm */ 0x5c7, /* MMX_PSADBWirr */ /* Table2541 */ 0x0, /* */ 0x559, /* MMX_MASKMOVQ */ /* Table2543 */ 0x5ea, /* MMX_PSUBBirm */ 0x5eb, /* MMX_PSUBBirr */ /* Table2545 */ 0x5f8, /* MMX_PSUBWirm */ 0x5f9, /* MMX_PSUBWirr */ /* Table2547 */ 0x5ec, /* MMX_PSUBDirm */ 0x5ed, /* MMX_PSUBDirr */ /* Table2549 */ 0x5ee, /* MMX_PSUBQirm */ 0x5ef, /* MMX_PSUBQirr */ /* Table2551 */ 0x578, /* MMX_PADDBirm */ 0x579, /* MMX_PADDBirr */ /* Table2553 */ 0x586, /* MMX_PADDWirm */ 0x587, /* MMX_PADDWirr */ /* Table2555 */ 0x57a, /* MMX_PADDDirm */ 0x57b, /* MMX_PADDDirr */ /* Table2557 */ 0xb3d, /* UD0 */ /* Table2558 */ 0x9f8, /* SGDT64m */ 0xa5d, /* SIDT64m */ 0x4ed, /* LGDT64m */ 0x4f3, /* LIDT64m */ 0xa69, /* SMSW16m */ 0x0, /* */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7e, /* VMRUN64 */ 0x1d43, /* VMMCALL */ 0x1d42, /* VMLOAD64 */ 0x1f80, /* VMSAVE64 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41b, /* INVLPGA64 */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2630 */ 0x0, /* */ 0x637, /* MOV64rc */ /* Table2632 */ 0x0, /* */ 0x638, /* MOV64rd */ /* Table2634 */ 0x0, /* */ 0x631, /* MOV64cr */ /* Table2636 */ 0x0, /* */ 0x632, /* MOV64dr */ /* Table2638 */ 0x1f7a, /* VMREAD64mr */ 0x1f7b, /* VMREAD64rr */ /* Table2640 */ 0x1fe5, /* VMWRITE64rm */ 0x1fe6, /* VMWRITE64rr */ /* Table2642 */ 0x8d1, /* PUSHFS64 */ /* Table2643 */ 0x856, /* POPFS64 */ /* Table2644 */ 0x8d4, /* PUSHGS64 */ /* Table2645 */ 0x859, /* POPGS64 */ /* Table2646 */ 0x0, /* */ 0x55a, /* MMX_MASKMOVQ64 */ /* Table2648 */ 0xa63, /* SLDT16m */ 0xa8a, /* STRm */ 0x4f4, /* LLDT16m */ 0x511, /* LTRm */ 0x1282, /* VERRm */ 0x1284, /* VERWm */ 0x0, /* */ 0x0, /* */ 0xa64, /* SLDT16r */ 0xa87, /* STR16r */ 0x4f5, /* LLDT16r */ 0x512, /* LTRr */ 0x1283, /* VERRr */ 0x1285, /* VERWr */ 0x0, /* */ 0x0, /* */ /* Table2664 */ 0x9f6, /* SGDT16m */ 0xa5b, /* SIDT16m */ 0x4eb, /* LGDT16m */ 0x4f1, /* LIDT16m */ 0xa69, /* SMSW16m */ 0x0, /* */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7d, /* VMRUN32 */ 0x1d43, /* VMMCALL */ 0x1d41, /* VMLOAD32 */ 0x1f7f, /* VMSAVE32 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41a, /* INVLPGA32 */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2736 */ 0x4c3, /* LAR16rm */ 0x4c4, /* LAR16rr */ /* Table2738 */ 0x508, /* LSL16rm */ 0x509, /* LSL16rr */ /* Table2740 */ 0x6b5, /* MOVUPDrm */ 0x6b6, /* MOVUPDrr */ /* Table2742 */ 0x6b4, /* MOVUPDmr */ 0x6b7, /* MOVUPDrr_REV */ /* Table2744 */ 0x67c, /* MOVLPDrm */ 0x0, /* */ /* Table2746 */ 0x67b, /* MOVLPDmr */ 0x0, /* */ /* Table2748 */ 0xb48, /* UNPCKLPDrm */ 0xb49, /* UNPCKLPDrr */ /* Table2750 */ 0xb44, /* UNPCKHPDrm */ 0xb45, /* UNPCKHPDrr */ /* Table2752 */ 0x677, /* MOVHPDrm */ 0x0, /* */ /* Table2754 */ 0x676, /* MOVHPDmr */ 0x0, /* */ /* Table2756 */ 0x85f, /* PREFETCHNTA */ 0x860, /* PREFETCHT0 */ 0x861, /* PREFETCHT1 */ 0x862, /* PREFETCHT2 */ 0x705, /* NOOP18_16m4 */ 0x706, /* NOOP18_16m5 */ 0x707, /* NOOP18_16m6 */ 0x708, /* NOOP18_16m7 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x709, /* NOOP18_16r4 */ 0x70a, /* NOOP18_16r5 */ 0x70b, /* NOOP18_16r6 */ 0x70c, /* NOOP18_16r7 */ /* Table2772 */ 0x71e, /* NOOPW_19 */ 0x715, /* NOOP19rr */ /* Table2774 */ 0x195, /* BNDMOV32rm */ 0x198, /* BNDMOVrr */ /* Table2776 */ 0x194, /* BNDMOV32mr */ 0x199, /* BNDMOVrr_REV */ /* Table2778 */ 0x71f, /* NOOPW_1c */ 0x0, /* */ /* Table2780 */ 0x720, /* NOOPW_1d */ 0x0, /* */ /* Table2782 */ 0x721, /* NOOPW_1e */ 0x0, /* */ /* Table2784 */ 0x71d, /* NOOPW */ 0x722, /* NOOPWr */ /* Table2786 */ 0x655, /* MOVAPDrm */ 0x656, /* MOVAPDrr */ /* Table2788 */ 0x654, /* MOVAPDmr */ 0x657, /* MOVAPDrr_REV */ /* Table2790 */ 0x54e, /* MMX_CVTPI2PDirm */ 0x54f, /* MMX_CVTPI2PDirr */ /* Table2792 */ 0x685, /* MOVNTPDmr */ 0x0, /* */ /* Table2794 */ 0x554, /* MMX_CVTTPD2PIirm */ 0x555, /* MMX_CVTTPD2PIirr */ /* Table2796 */ 0x54c, /* MMX_CVTPD2PIirm */ 0x54d, /* MMX_CVTPD2PIirr */ /* Table2798 */ 0xb2a, /* UCOMISDrm */ 0xb2c, /* UCOMISDrr */ /* Table2800 */ 0x2c9, /* COMISDrm */ 0x2cb, /* COMISDrr */ /* Table2802 */ 0x26d, /* CMOVO16rm */ 0x26e, /* CMOVO16rr */ /* Table2804 */ 0x257, /* CMOVNO16rm */ 0x258, /* CMOVNO16rr */ /* Table2806 */ 0x20f, /* CMOVB16rm */ 0x210, /* CMOVB16rr */ /* Table2808 */ 0x209, /* CMOVAE16rm */ 0x20a, /* CMOVAE16rr */ /* Table2810 */ 0x223, /* CMOVE16rm */ 0x224, /* CMOVE16rr */ /* Table2812 */ 0x24d, /* CMOVNE16rm */ 0x24e, /* CMOVNE16rr */ /* Table2814 */ 0x215, /* CMOVBE16rm */ 0x216, /* CMOVBE16rr */ /* Table2816 */ 0x203, /* CMOVA16rm */ 0x204, /* CMOVA16rr */ /* Table2818 */ 0x27d, /* CMOVS16rm */ 0x27e, /* CMOVS16rr */ /* Table2820 */ 0x267, /* CMOVNS16rm */ 0x268, /* CMOVNS16rr */ /* Table2822 */ 0x273, /* CMOVP16rm */ 0x274, /* CMOVP16rr */ /* Table2824 */ 0x25d, /* CMOVNP16rm */ 0x25e, /* CMOVNP16rr */ /* Table2826 */ 0x239, /* CMOVL16rm */ 0x23a, /* CMOVL16rr */ /* Table2828 */ 0x233, /* CMOVGE16rm */ 0x234, /* CMOVGE16rr */ /* Table2830 */ 0x23f, /* CMOVLE16rm */ 0x240, /* CMOVLE16rr */ /* Table2832 */ 0x22d, /* CMOVG16rm */ 0x22e, /* CMOVG16rr */ /* Table2834 */ 0x0, /* */ 0x67f, /* MOVMSKPDrr */ /* Table2836 */ 0xa6d, /* SQRTPDm */ 0xa6e, /* SQRTPDr */ /* Table2838 */ 0x147, /* ANDPDrm */ 0x148, /* ANDPDrr */ /* Table2840 */ 0x143, /* ANDNPDrm */ 0x144, /* ANDNPDrr */ /* Table2842 */ 0x74f, /* ORPDrm */ 0x750, /* ORPDrr */ /* Table2844 */ 0x3b9f, /* XORPDrm */ 0x3ba0, /* XORPDrr */ /* Table2846 */ 0xe6, /* ADDPDrm */ 0xe7, /* ADDPDrr */ /* Table2848 */ 0x6d5, /* MULPDrm */ 0x6d6, /* MULPDrr */ /* Table2850 */ 0x2eb, /* CVTPD2PSrm */ 0x2ec, /* CVTPD2PSrr */ /* Table2852 */ 0x2ed, /* CVTPS2DQrm */ 0x2ee, /* CVTPS2DQrr */ /* Table2854 */ 0xac1, /* SUBPDrm */ 0xac2, /* SUBPDrr */ /* Table2856 */ 0x540, /* MINPDrm */ 0x541, /* MINPDrr */ /* Table2858 */ 0x33c, /* DIVPDrm */ 0x33d, /* DIVPDrr */ /* Table2860 */ 0x52b, /* MAXPDrm */ 0x52c, /* MAXPDrr */ /* Table2862 */ 0x8af, /* PUNPCKLBWrm */ 0x8b0, /* PUNPCKLBWrr */ /* Table2864 */ 0x8b5, /* PUNPCKLWDrm */ 0x8b6, /* PUNPCKLWDrr */ /* Table2866 */ 0x8b1, /* PUNPCKLDQrm */ 0x8b2, /* PUNPCKLDQrr */ /* Table2868 */ 0x764, /* PACKSSWBrm */ 0x765, /* PACKSSWBrr */ /* Table2870 */ 0x799, /* PCMPGTBrm */ 0x79a, /* PCMPGTBrr */ /* Table2872 */ 0x79f, /* PCMPGTWrm */ 0x7a0, /* PCMPGTWrr */ /* Table2874 */ 0x79b, /* PCMPGTDrm */ 0x79c, /* PCMPGTDrr */ /* Table2876 */ 0x768, /* PACKUSWBrm */ 0x769, /* PACKUSWBrr */ /* Table2878 */ 0x8a7, /* PUNPCKHBWrm */ 0x8a8, /* PUNPCKHBWrr */ /* Table2880 */ 0x8ad, /* PUNPCKHWDrm */ 0x8ae, /* PUNPCKHWDrr */ /* Table2882 */ 0x8a9, /* PUNPCKHDQrm */ 0x8aa, /* PUNPCKHDQrr */ /* Table2884 */ 0x762, /* PACKSSDWrm */ 0x763, /* PACKSSDWrr */ /* Table2886 */ 0x8b3, /* PUNPCKLQDQrm */ 0x8b4, /* PUNPCKLQDQrr */ /* Table2888 */ 0x8ab, /* PUNPCKHQDQrm */ 0x8ac, /* PUNPCKHQDQrr */ /* Table2890 */ 0x664, /* MOVDI2PDIrm */ 0x665, /* MOVDI2PDIrr */ /* Table2892 */ 0x66e, /* MOVDQArm */ 0x66f, /* MOVDQArr */ /* Table2894 */ 0x869, /* PSHUFDmi */ 0x86a, /* PSHUFDri */ /* Table2896 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x88c, /* PSRLWri */ 0x0, /* */ 0x882, /* PSRAWri */ 0x0, /* */ 0x87c, /* PSLLWri */ 0x0, /* */ /* Table2912 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x886, /* PSRLDri */ 0x0, /* */ 0x87f, /* PSRADri */ 0x0, /* */ 0x876, /* PSLLDri */ 0x0, /* */ /* Table2928 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x889, /* PSRLQri */ 0x885, /* PSRLDQri */ 0x0, /* */ 0x0, /* */ 0x879, /* PSLLQri */ 0x875, /* PSLLDQri */ /* Table2944 */ 0x78d, /* PCMPEQBrm */ 0x78e, /* PCMPEQBrr */ /* Table2946 */ 0x793, /* PCMPEQWrm */ 0x794, /* PCMPEQWrr */ /* Table2948 */ 0x78f, /* PCMPEQDrm */ 0x790, /* PCMPEQDrr */ /* Table2950 */ 0x0, /* */ 0x37c, /* EXTRQI */ /* Table2952 */ 0x0, /* */ 0x37b, /* EXTRQ */ /* Table2954 */ 0x3c2, /* HADDPDrm */ 0x3c3, /* HADDPDrr */ /* Table2956 */ 0x3c7, /* HSUBPDrm */ 0x3c8, /* HSUBPDrr */ /* Table2958 */ 0x689, /* MOVPDI2DImr */ 0x68a, /* MOVPDI2DIrr */ /* Table2960 */ 0x66d, /* MOVDQAmr */ 0x670, /* MOVDQArr_REV */ /* Table2962 */ 0x476, /* JO_2 */ /* Table2963 */ 0x46d, /* JNO_2 */ /* Table2964 */ 0x447, /* JB_2 */ /* Table2965 */ 0x43e, /* JAE_2 */ /* Table2966 */ 0x44c, /* JE_2 */ /* Table2967 */ 0x46a, /* JNE_2 */ /* Table2968 */ 0x444, /* JBE_2 */ /* Table2969 */ 0x441, /* JA_2 */ /* Table2970 */ 0x47d, /* JS_2 */ /* Table2971 */ 0x473, /* JNS_2 */ /* Table2972 */ 0x479, /* JP_2 */ /* Table2973 */ 0x470, /* JNP_2 */ /* Table2974 */ 0x458, /* JL_2 */ /* Table2975 */ 0x44f, /* JGE_2 */ /* Table2976 */ 0x455, /* JLE_2 */ /* Table2977 */ 0x452, /* JG_2 */ /* Table2978 */ 0x8cf, /* PUSHFS16 */ /* Table2979 */ 0x854, /* POPFS16 */ /* Table2980 */ 0x1ad, /* BT16mr */ 0x1af, /* BT16rr */ /* Table2982 */ 0xa20, /* SHLD16mri8 */ 0xa22, /* SHLD16rri8 */ /* Table2984 */ 0xa1f, /* SHLD16mrCL */ 0xa21, /* SHLD16rrCL */ /* Table2986 */ 0x8d2, /* PUSHGS16 */ /* Table2987 */ 0x857, /* POPGS16 */ /* Table2988 */ 0x1d1, /* BTS16mr */ 0x1d3, /* BTS16rr */ /* Table2990 */ 0xa48, /* SHRD16mri8 */ 0xa4a, /* SHRD16rri8 */ /* Table2992 */ 0xa47, /* SHRD16mrCL */ 0xa49, /* SHRD16rrCL */ /* Table2994 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x0, /* */ 0x0, /* */ 0x200, /* CLWB */ 0x1fb, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb1b, /* TPAUSE */ 0x0, /* */ /* Table3010 */ 0x3e1, /* IMUL16rm */ 0x3e4, /* IMUL16rr */ /* Table3012 */ 0x2c0, /* CMPXCHG16rm */ 0x2c1, /* CMPXCHG16rr */ /* Table3014 */ 0x50e, /* LSS16rm */ 0x0, /* */ /* Table3016 */ 0x1c5, /* BTR16mr */ 0x1c7, /* BTR16rr */ /* Table3018 */ 0x4e8, /* LFS16rm */ 0x0, /* */ /* Table3020 */ 0x4ee, /* LGS16rm */ 0x0, /* */ /* Table3022 */ 0x6be, /* MOVZX16rm8 */ 0x6c0, /* MOVZX16rr8 */ /* Table3024 */ 0x6bd, /* MOVZX16rm16 */ 0x6bf, /* MOVZX16rr16 */ /* Table3026 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x1ac, /* BT16mi8 */ 0x1d0, /* BTS16mi8 */ 0x1c4, /* BTR16mi8 */ 0x1b8, /* BTC16mi8 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x1ae, /* BT16ri8 */ 0x1d2, /* BTS16ri8 */ 0x1c6, /* BTR16ri8 */ 0x1ba, /* BTC16ri8 */ /* Table3042 */ 0x1b9, /* BTC16mr */ 0x1bb, /* BTC16rr */ /* Table3044 */ 0x19d, /* BSF16rm */ 0x19e, /* BSF16rr */ /* Table3046 */ 0x1a3, /* BSR16rm */ 0x1a4, /* BSR16rr */ /* Table3048 */ 0x6a5, /* MOVSX16rm8 */ 0x6a7, /* MOVSX16rr8 */ /* Table3050 */ 0x6a4, /* MOVSX16rm16 */ 0x6a6, /* MOVSX16rr16 */ /* Table3052 */ 0x3b5d, /* XADD16rm */ 0x3b5e, /* XADD16rr */ /* Table3054 */ 0x2a7, /* CMPPDrmi */ 0x2a9, /* CMPPDrri */ /* Table3056 */ 0x7f5, /* PINSRWrm */ 0x7f6, /* PINSRWrr */ /* Table3058 */ 0x0, /* */ 0x7b5, /* PEXTRWrr */ /* Table3060 */ 0xa57, /* SHUFPDrmi */ 0xa58, /* SHUFPDrri */ /* Table3062 */ 0x0, /* */ 0x2c6, /* CMPXCHG8B */ 0x0, /* */ 0x3ba6, /* XRSTORS */ 0x3baa, /* XSAVEC */ 0x3bae, /* XSAVES */ 0x1c96, /* VMCLEARm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91a, /* RDRAND16r */ 0x91d, /* RDSEED16r */ /* Table3078 */ 0x1a9, /* BSWAP16r_BAD */ /* Table3079 */ 0xf2, /* ADDSUBPDrm */ 0xf3, /* ADDSUBPDrr */ /* Table3081 */ 0x88d, /* PSRLWrm */ 0x88e, /* PSRLWrr */ /* Table3083 */ 0x887, /* PSRLDrm */ 0x888, /* PSRLDrr */ /* Table3085 */ 0x88a, /* PSRLQrm */ 0x88b, /* PSRLQrr */ /* Table3087 */ 0x76e, /* PADDQrm */ 0x76f, /* PADDQrr */ /* Table3089 */ 0x838, /* PMULLWrm */ 0x839, /* PMULLWrr */ /* Table3091 */ 0x68b, /* MOVPQI2QImr */ 0x68c, /* MOVPQI2QIrr */ /* Table3093 */ 0x0, /* */ 0x813, /* PMOVMSKBrr */ /* Table3095 */ 0x899, /* PSUBUSBrm */ 0x89a, /* PSUBUSBrr */ /* Table3097 */ 0x89b, /* PSUBUSWrm */ 0x89c, /* PSUBUSWrr */ /* Table3099 */ 0x80d, /* PMINUBrm */ 0x80e, /* PMINUBrr */ /* Table3101 */ 0x77e, /* PANDrm */ 0x77f, /* PANDrr */ /* Table3103 */ 0x774, /* PADDUSBrm */ 0x775, /* PADDUSBrr */ /* Table3105 */ 0x776, /* PADDUSWrm */ 0x777, /* PADDUSWrr */ /* Table3107 */ 0x801, /* PMAXUBrm */ 0x802, /* PMAXUBrr */ /* Table3109 */ 0x77c, /* PANDNrm */ 0x77d, /* PANDNrr */ /* Table3111 */ 0x781, /* PAVGBrm */ 0x782, /* PAVGBrr */ /* Table3113 */ 0x883, /* PSRAWrm */ 0x884, /* PSRAWrr */ /* Table3115 */ 0x880, /* PSRADrm */ 0x881, /* PSRADrr */ /* Table3117 */ 0x785, /* PAVGWrm */ 0x786, /* PAVGWrr */ /* Table3119 */ 0x832, /* PMULHUWrm */ 0x833, /* PMULHUWrr */ /* Table3121 */ 0x834, /* PMULHWrm */ 0x835, /* PMULHWrr */ /* Table3123 */ 0x311, /* CVTTPD2DQrm */ 0x312, /* CVTTPD2DQrr */ /* Table3125 */ 0x682, /* MOVNTDQmr */ 0x0, /* */ /* Table3127 */ 0x895, /* PSUBSBrm */ 0x896, /* PSUBSBrr */ /* Table3129 */ 0x897, /* PSUBSWrm */ 0x898, /* PSUBSWrr */ /* Table3131 */ 0x80b, /* PMINSWrm */ 0x80c, /* PMINSWrr */ /* Table3133 */ 0x85c, /* PORrm */ 0x85d, /* PORrr */ /* Table3135 */ 0x770, /* PADDSBrm */ 0x771, /* PADDSBrr */ /* Table3137 */ 0x772, /* PADDSWrm */ 0x773, /* PADDSWrr */ /* Table3139 */ 0x7ff, /* PMAXSWrm */ 0x800, /* PMAXSWrr */ /* Table3141 */ 0x8d9, /* PXORrm */ 0x8da, /* PXORrr */ /* Table3143 */ 0x87d, /* PSLLWrm */ 0x87e, /* PSLLWrr */ /* Table3145 */ 0x877, /* PSLLDrm */ 0x878, /* PSLLDrr */ /* Table3147 */ 0x87a, /* PSLLQrm */ 0x87b, /* PSLLQrr */ /* Table3149 */ 0x83a, /* PMULUDQrm */ 0x83b, /* PMULUDQrr */ /* Table3151 */ 0x7f9, /* PMADDWDrm */ 0x7fa, /* PMADDWDrr */ /* Table3153 */ 0x865, /* PSADBWrm */ 0x866, /* PSADBWrr */ /* Table3155 */ 0x0, /* */ 0x521, /* MASKMOVDQU */ /* Table3157 */ 0x88f, /* PSUBBrm */ 0x890, /* PSUBBrr */ /* Table3159 */ 0x89d, /* PSUBWrm */ 0x89e, /* PSUBWrr */ /* Table3161 */ 0x891, /* PSUBDrm */ 0x892, /* PSUBDrr */ /* Table3163 */ 0x893, /* PSUBQrm */ 0x894, /* PSUBQrr */ /* Table3165 */ 0x76a, /* PADDBrm */ 0x76b, /* PADDBrr */ /* Table3167 */ 0x778, /* PADDWrm */ 0x779, /* PADDWrr */ /* Table3169 */ 0x76c, /* PADDDrm */ 0x76d, /* PADDDrr */ /* Table3171 */ 0x67c, /* MOVLPDrm */ 0x675, /* MOVHLPSrr */ /* Table3173 */ 0x677, /* MOVHPDrm */ 0x67a, /* MOVLHPSrr */ /* Table3175 */ 0x1f78, /* VMREAD32mr */ 0x37c, /* EXTRQI */ /* Table3177 */ 0x1fe3, /* VMWRITE32rm */ 0x37b, /* EXTRQ */ /* Table3179 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x3ba8, /* XSAVE */ 0x3ba4, /* XRSTOR */ 0x200, /* CLWB */ 0x1fb, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4e7, /* LFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3251 */ 0x0, /* */ 0x2c6, /* CMPXCHG8B */ 0x0, /* */ 0x3ba6, /* XRSTORS */ 0x3baa, /* XSAVEC */ 0x3bae, /* XSAVES */ 0x1c96, /* VMCLEARm */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91a, /* RDRAND16r */ 0x91d, /* RDSEED16r */ /* Table3267 */ 0x692, /* MOVSDrm */ 0x693, /* MOVSDrr */ /* Table3269 */ 0x691, /* MOVSDmr */ 0x694, /* MOVSDrr_REV */ /* Table3271 */ 0x662, /* MOVDDUPrm */ 0x663, /* MOVDDUPrr */ /* Table3273 */ 0x18d, /* BNDCU32rm */ 0x18e, /* BNDCU32rr */ /* Table3275 */ 0x189, /* BNDCN32rm */ 0x18a, /* BNDCN32rr */ /* Table3277 */ 0x2f9, /* CVTSI2SDrm */ 0x2fb, /* CVTSI2SDrr */ /* Table3279 */ 0x687, /* MOVNTSD */ 0x0, /* */ /* Table3281 */ 0x319, /* CVTTSD2SIrm */ 0x31b, /* CVTTSD2SIrr */ /* Table3283 */ 0x2f3, /* CVTSD2SIrm_Int */ 0x2f4, /* CVTSD2SIrr_Int */ /* Table3285 */ 0xa71, /* SQRTSDm */ 0xa73, /* SQRTSDr */ /* Table3287 */ 0xea, /* ADDSDrm */ 0xec, /* ADDSDrr */ /* Table3289 */ 0x6d9, /* MULSDrm */ 0x6db, /* MULSDrr */ /* Table3291 */ 0x2f5, /* CVTSD2SSrm */ 0x2f7, /* CVTSD2SSrr */ /* Table3293 */ 0xad7, /* SUBSDrm */ 0xad9, /* SUBSDrr */ /* Table3295 */ 0x544, /* MINSDrm */ 0x546, /* MINSDrr */ /* Table3297 */ 0x352, /* DIVSDrm */ 0x354, /* DIVSDrr */ /* Table3299 */ 0x52f, /* MAXSDrm */ 0x531, /* MAXSDrr */ /* Table3301 */ 0x86d, /* PSHUFLWmi */ 0x86e, /* PSHUFLWri */ /* Table3303 */ 0x0, /* */ 0x40f, /* INSERTQI */ /* Table3305 */ 0x0, /* */ 0x40e, /* INSERTQ */ /* Table3307 */ 0x3c4, /* HADDPSrm */ 0x3c5, /* HADDPSrr */ /* Table3309 */ 0x3c9, /* HSUBPSrm */ 0x3ca, /* HSUBPSrr */ /* Table3311 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb43, /* UMWAIT */ 0x0, /* */ /* Table3327 */ 0x2b0, /* CMPSDrm */ 0x2b3, /* CMPSDrr */ /* Table3329 */ 0x0, /* */ 0x2c6, /* CMPXCHG8B */ 0x0, /* */ 0x3ba6, /* XRSTORS */ 0x3baa, /* XSAVEC */ 0x3bae, /* XSAVES */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3345 */ 0xf4, /* ADDSUBPSrm */ 0xf5, /* ADDSUBPSrr */ /* Table3347 */ 0x0, /* */ 0x563, /* MMX_MOVDQ2Qrr */ /* Table3349 */ 0x2e9, /* CVTPD2DQrm */ 0x2ea, /* CVTPD2DQrr */ /* Table3351 */ 0x4c9, /* LDDQUrm */ 0x0, /* */ /* Table3353 */ 0x9f7, /* SGDT32m */ 0xa5c, /* SIDT32m */ 0x4ec, /* LGDT32m */ 0x4f2, /* LIDT32m */ 0xa69, /* SMSW16m */ 0x974, /* RSTORSSP */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7d, /* VMRUN32 */ 0x1d43, /* VMMCALL */ 0x1d41, /* VMLOAD32 */ 0x1f7f, /* VMSAVE32 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41a, /* INVLPGA32 */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0x9f2, /* SETSSBSY */ 0x0, /* */ 0x9ab, /* SAVEPREVSSP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3425 */ 0x3b50, /* WBNOINVD */ /* Table3426 */ 0x6a0, /* MOVSSrm */ 0x6a1, /* MOVSSrr */ /* Table3428 */ 0x69f, /* MOVSSmr */ 0x6a2, /* MOVSSrr_REV */ /* Table3430 */ 0x69a, /* MOVSLDUPrm */ 0x69b, /* MOVSLDUPrr */ /* Table3432 */ 0x697, /* MOVSHDUPrm */ 0x698, /* MOVSHDUPrr */ /* Table3434 */ 0x185, /* BNDCL32rm */ 0x186, /* BNDCL32rr */ /* Table3436 */ 0x192, /* BNDMK32rm */ 0x0, /* */ /* Table3438 */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x920, /* RDSSPD */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x377, /* ENDBR64 */ 0x376, /* ENDBR32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3510 */ 0x2fd, /* CVTSI2SSrm */ 0x2ff, /* CVTSI2SSrr */ /* Table3512 */ 0x688, /* MOVNTSS */ 0x0, /* */ /* Table3514 */ 0x321, /* CVTTSS2SIrm */ 0x323, /* CVTTSS2SIrr */ /* Table3516 */ 0x30f, /* CVTSS2SIrm_Int */ 0x310, /* CVTSS2SIrr_Int */ /* Table3518 */ 0xa75, /* SQRTSSm */ 0xa77, /* SQRTSSr */ /* Table3520 */ 0x970, /* RSQRTSSm */ 0x972, /* RSQRTSSr */ /* Table3522 */ 0x8f5, /* RCPSSm */ 0x8f7, /* RCPSSr */ /* Table3524 */ 0xee, /* ADDSSrm */ 0xf0, /* ADDSSrr */ /* Table3526 */ 0x6dd, /* MULSSrm */ 0x6df, /* MULSSrr */ /* Table3528 */ 0x309, /* CVTSS2SDrm */ 0x30b, /* CVTSS2SDrr */ /* Table3530 */ 0x313, /* CVTTPS2DQrm */ 0x314, /* CVTTPS2DQrr */ /* Table3532 */ 0xadb, /* SUBSSrm */ 0xadd, /* SUBSSrr */ /* Table3534 */ 0x548, /* MINSSrm */ 0x54a, /* MINSSrr */ /* Table3536 */ 0x356, /* DIVSSrm */ 0x358, /* DIVSSrr */ /* Table3538 */ 0x533, /* MAXSSrm */ 0x535, /* MAXSSrr */ /* Table3540 */ 0x672, /* MOVDQUrm */ 0x673, /* MOVDQUrr */ /* Table3542 */ 0x86b, /* PSHUFHWmi */ 0x86c, /* PSHUFHWri */ /* Table3544 */ 0x68f, /* MOVQI2PQIrm */ 0x6bc, /* MOVZPQILo2PQIrr */ /* Table3546 */ 0x671, /* MOVDQUmr */ 0x674, /* MOVDQUrr_REV */ /* Table3548 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x8a5, /* PTWRITEm */ 0x0, /* */ 0x1fe, /* CLRSSBSY */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x8a6, /* PTWRITEr */ 0x409, /* INCSSPD */ 0xb41, /* UMONITOR32 */ 0x0, /* */ /* Table3564 */ 0x849, /* POPCNT32rm */ 0x84a, /* POPCNT32rr */ /* Table3566 */ 0xb22, /* TZCNT32rm */ 0xb23, /* TZCNT32rr */ /* Table3568 */ 0x51d, /* LZCNT32rm */ 0x51e, /* LZCNT32rr */ /* Table3570 */ 0x2b8, /* CMPSSrm */ 0x2bb, /* CMPSSrr */ /* Table3572 */ 0x0, /* */ 0x2c6, /* CMPXCHG8B */ 0x0, /* */ 0x3ba6, /* XRSTORS */ 0x3baa, /* XSAVEC */ 0x3bae, /* XSAVES */ 0x1fe8, /* VMXON */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x916, /* RDPID32 */ /* Table3588 */ 0x0, /* */ 0x566, /* MMX_MOVQ2DQrr */ /* Table3590 */ 0x2e5, /* CVTDQ2PDrm */ 0x2e6, /* CVTDQ2PDrr */ /* Table3592 */ 0x847, /* POPCNT16rm */ 0x848, /* POPCNT16rr */ /* Table3594 */ 0xb20, /* TZCNT16rm */ 0xb21, /* TZCNT16rr */ /* Table3596 */ 0x51b, /* LZCNT16rm */ 0x51c, /* LZCNT16rr */ /* Table3598 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb40, /* UMONITOR16 */ 0x0, /* */ /* Table3614 */ 0xa63, /* SLDT16m */ 0xa8a, /* STRm */ 0x4f4, /* LLDT16m */ 0x511, /* LTRm */ 0x1282, /* VERRm */ 0x1284, /* VERWm */ 0x0, /* */ 0x0, /* */ 0xa66, /* SLDT64r */ 0xa89, /* STR64r */ 0x4f5, /* LLDT16r */ 0x512, /* LTRr */ 0x1283, /* VERRr */ 0x1285, /* VERWr */ 0x0, /* */ 0x0, /* */ /* Table3630 */ 0x9f8, /* SGDT64m */ 0xa5d, /* SIDT64m */ 0x4ed, /* LGDT64m */ 0x4f3, /* LIDT64m */ 0xa69, /* SMSW16m */ 0x0, /* */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7e, /* VMRUN64 */ 0x1d43, /* VMMCALL */ 0x1d42, /* VMLOAD64 */ 0x1f80, /* VMSAVE64 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41b, /* INVLPGA64 */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3702 */ 0x4c7, /* LAR64rm */ 0x4c8, /* LAR64rr */ /* Table3704 */ 0x50c, /* LSL64rm */ 0x50d, /* LSL64rr */ /* Table3706 */ 0xafa, /* SYSRET64 */ /* Table3707 */ 0x71b, /* NOOPQ */ 0x71c, /* NOOPQr */ /* Table3709 */ 0xaf8, /* SYSEXIT64 */ /* Table3710 */ 0x271, /* CMOVO64rm */ 0x272, /* CMOVO64rr */ /* Table3712 */ 0x25b, /* CMOVNO64rm */ 0x25c, /* CMOVNO64rr */ /* Table3714 */ 0x213, /* CMOVB64rm */ 0x214, /* CMOVB64rr */ /* Table3716 */ 0x20d, /* CMOVAE64rm */ 0x20e, /* CMOVAE64rr */ /* Table3718 */ 0x227, /* CMOVE64rm */ 0x228, /* CMOVE64rr */ /* Table3720 */ 0x251, /* CMOVNE64rm */ 0x252, /* CMOVNE64rr */ /* Table3722 */ 0x219, /* CMOVBE64rm */ 0x21a, /* CMOVBE64rr */ /* Table3724 */ 0x207, /* CMOVA64rm */ 0x208, /* CMOVA64rr */ /* Table3726 */ 0x281, /* CMOVS64rm */ 0x282, /* CMOVS64rr */ /* Table3728 */ 0x26b, /* CMOVNS64rm */ 0x26c, /* CMOVNS64rr */ /* Table3730 */ 0x277, /* CMOVP64rm */ 0x278, /* CMOVP64rr */ /* Table3732 */ 0x261, /* CMOVNP64rm */ 0x262, /* CMOVNP64rr */ /* Table3734 */ 0x23d, /* CMOVL64rm */ 0x23e, /* CMOVL64rr */ /* Table3736 */ 0x237, /* CMOVGE64rm */ 0x238, /* CMOVGE64rr */ /* Table3738 */ 0x243, /* CMOVLE64rm */ 0x244, /* CMOVLE64rr */ /* Table3740 */ 0x231, /* CMOVG64rm */ 0x232, /* CMOVG64rr */ /* Table3742 */ 0x561, /* MMX_MOVD64to64rm */ 0x562, /* MMX_MOVD64to64rr */ /* Table3744 */ 0x55b, /* MMX_MOVD64from64rm */ 0x55c, /* MMX_MOVD64from64rr */ /* Table3746 */ 0x1b5, /* BT64mr */ 0x1b7, /* BT64rr */ /* Table3748 */ 0xa28, /* SHLD64mri8 */ 0xa2a, /* SHLD64rri8 */ /* Table3750 */ 0xa27, /* SHLD64mrCL */ 0xa29, /* SHLD64rrCL */ /* Table3752 */ 0x1d9, /* BTS64mr */ 0x1db, /* BTS64rr */ /* Table3754 */ 0xa50, /* SHRD64mri8 */ 0xa52, /* SHRD64rri8 */ /* Table3756 */ 0xa4f, /* SHRD64mrCL */ 0xa51, /* SHRD64rrCL */ /* Table3758 */ 0x3b7, /* FXSAVE64 */ 0x3b5, /* FXRSTOR64 */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x3ba9, /* XSAVE64 */ 0x3ba5, /* XRSTOR64 */ 0x3bad, /* XSAVEOPT64 */ 0x1fa, /* CLFLUSH */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4e7, /* LFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x537, /* MFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3830 */ 0x3f1, /* IMUL64rm */ 0x3f4, /* IMUL64rr */ /* Table3832 */ 0x2c4, /* CMPXCHG64rm */ 0x2c5, /* CMPXCHG64rr */ /* Table3834 */ 0x510, /* LSS64rm */ 0x0, /* */ /* Table3836 */ 0x1cd, /* BTR64mr */ 0x1cf, /* BTR64rr */ /* Table3838 */ 0x4ea, /* LFS64rm */ 0x0, /* */ /* Table3840 */ 0x4f0, /* LGS64rm */ 0x0, /* */ /* Table3842 */ 0x6c8, /* MOVZX64rm8 */ 0x6ca, /* MOVZX64rr8 */ /* Table3844 */ 0x6c7, /* MOVZX64rm16 */ 0x6c9, /* MOVZX64rr16 */ /* Table3846 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x1b4, /* BT64mi8 */ 0x1d8, /* BTS64mi8 */ 0x1cc, /* BTR64mi8 */ 0x1c0, /* BTC64mi8 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x1b6, /* BT64ri8 */ 0x1da, /* BTS64ri8 */ 0x1ce, /* BTR64ri8 */ 0x1c2, /* BTC64ri8 */ /* Table3862 */ 0x1c1, /* BTC64mr */ 0x1c3, /* BTC64rr */ /* Table3864 */ 0x1a1, /* BSF64rm */ 0x1a2, /* BSF64rr */ /* Table3866 */ 0x1a7, /* BSR64rm */ 0x1a8, /* BSR64rr */ /* Table3868 */ 0x6b0, /* MOVSX64rm8 */ 0x6b3, /* MOVSX64rr8 */ /* Table3870 */ 0x6ae, /* MOVSX64rm16 */ 0x6b1, /* MOVSX64rr16 */ /* Table3872 */ 0x3b61, /* XADD64rm */ 0x3b62, /* XADD64rr */ /* Table3874 */ 0x683, /* MOVNTI_64mr */ 0x0, /* */ /* Table3876 */ 0x0, /* */ 0x2bf, /* CMPXCHG16B */ 0x0, /* */ 0x3ba7, /* XRSTORS64 */ 0x3bab, /* XSAVEC64 */ 0x3baf, /* XSAVES64 */ 0x1f76, /* VMPTRLDm */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91c, /* RDRAND64r */ 0x91f, /* RDSEED64r */ /* Table3892 */ 0x1ab, /* BSWAP64r */ /* Table3893 */ 0x197, /* BNDMOV64rm */ 0x198, /* BNDMOVrr */ /* Table3895 */ 0x196, /* BNDMOV64mr */ 0x199, /* BNDMOVrr_REV */ /* Table3897 */ 0x1f7a, /* VMREAD64mr */ 0x37c, /* EXTRQI */ /* Table3899 */ 0x1fe5, /* VMWRITE64rm */ 0x37b, /* EXTRQ */ /* Table3901 */ 0x3b7, /* FXSAVE64 */ 0x3b5, /* FXRSTOR64 */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x3ba9, /* XSAVE64 */ 0x3ba5, /* XRSTOR64 */ 0x3bad, /* XSAVEOPT64 */ 0x1fb, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4e7, /* LFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3973 */ 0x0, /* */ 0x2bf, /* CMPXCHG16B */ 0x0, /* */ 0x3ba7, /* XRSTORS64 */ 0x3bab, /* XSAVEC64 */ 0x3baf, /* XSAVES64 */ 0x1c96, /* VMCLEARm */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91c, /* RDRAND64r */ 0x91f, /* RDSEED64r */ /* Table3989 */ 0x0, /* */ 0x522, /* MASKMOVDQU64 */ /* Table3991 */ 0x9f8, /* SGDT64m */ 0xa5d, /* SIDT64m */ 0x4ed, /* LGDT64m */ 0x4f3, /* LIDT64m */ 0xa69, /* SMSW16m */ 0x0, /* */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7e, /* VMRUN64 */ 0x1d43, /* VMMCALL */ 0x1d42, /* VMLOAD64 */ 0x1f80, /* VMSAVE64 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41b, /* INVLPGA64 */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0xa6a, /* SMSW16r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4063 */ 0x18f, /* BNDCU64rm */ 0x190, /* BNDCU64rr */ /* Table4065 */ 0x18b, /* BNDCN64rm */ 0x18c, /* BNDCN64rr */ /* Table4067 */ 0x9f8, /* SGDT64m */ 0xa5d, /* SIDT64m */ 0x4ed, /* LGDT64m */ 0x4f3, /* LIDT64m */ 0xa69, /* SMSW16m */ 0x974, /* RSTORSSP */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7e, /* VMRUN64 */ 0x1d43, /* VMMCALL */ 0x1d42, /* VMLOAD64 */ 0x1f80, /* VMSAVE64 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41b, /* INVLPGA64 */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0xa6b, /* SMSW32r */ 0x9f2, /* SETSSBSY */ 0x0, /* */ 0x9ab, /* SAVEPREVSSP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4139 */ 0x187, /* BNDCL64rm */ 0x188, /* BNDCL64rr */ /* Table4141 */ 0x193, /* BNDMK64rm */ 0x0, /* */ /* Table4143 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x8a5, /* PTWRITEm */ 0x0, /* */ 0x1fe, /* CLRSSBSY */ 0x0, /* */ 0x911, /* RDFSBASE */ 0x913, /* RDGSBASE */ 0x3b51, /* WRFSBASE */ 0x3b53, /* WRGSBASE */ 0x8a6, /* PTWRITEr */ 0x409, /* INCSSPD */ 0xb42, /* UMONITOR64 */ 0x0, /* */ /* Table4159 */ 0x0, /* */ 0x2c6, /* CMPXCHG8B */ 0x0, /* */ 0x3ba6, /* XRSTORS */ 0x3baa, /* XSAVEC */ 0x3bae, /* XSAVES */ 0x1fe8, /* VMXON */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x917, /* RDPID64 */ /* Table4175 */ 0x3b6, /* FXSAVE */ 0x3b4, /* FXRSTOR */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x8a5, /* PTWRITEm */ 0x0, /* */ 0x1fe, /* CLRSSBSY */ 0x0, /* */ 0x911, /* RDFSBASE */ 0x913, /* RDGSBASE */ 0x3b51, /* WRFSBASE */ 0x3b53, /* WRGSBASE */ 0x8a6, /* PTWRITEr */ 0x409, /* INCSSPD */ 0xb41, /* UMONITOR32 */ 0x0, /* */ /* Table4191 */ 0x9f8, /* SGDT64m */ 0xa5d, /* SIDT64m */ 0x4ed, /* LGDT64m */ 0x4f3, /* LIDT64m */ 0xa69, /* SMSW16m */ 0x974, /* RSTORSSP */ 0x4f8, /* LMSW16m */ 0x419, /* INVLPG */ 0x375, /* ENCLV */ 0x1c95, /* VMCALL */ 0x1d40, /* VMLAUNCH */ 0x1f7c, /* VMRESUME */ 0x1fe7, /* VMXOFF */ 0x7a5, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x609, /* MONITORrrr */ 0x6fb, /* MWAITrr */ 0x1f6, /* CLAC */ 0xa7d, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x373, /* ENCLS */ 0x3b79, /* XGETBV */ 0x3bb0, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x1c97, /* VMFUNC */ 0x3b78, /* XEND */ 0x3bb4, /* XTEST */ 0x374, /* ENCLU */ 0x1f7e, /* VMRUN64 */ 0x1d43, /* VMMCALL */ 0x1d42, /* VMLOAD64 */ 0x1f80, /* VMSAVE64 */ 0xa80, /* STGI */ 0x1fc, /* CLGI */ 0xa62, /* SKINIT */ 0x41b, /* INVLPGA64 */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0xa6c, /* SMSW64r */ 0x9f2, /* SETSSBSY */ 0x0, /* */ 0x9ab, /* SAVEPREVSSP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x918, /* RDPKRUr */ 0x3b56, /* WRPKRUr */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0x4f9, /* LMSW16r */ 0xaf4, /* SWAPGS */ 0x923, /* RDTSCP */ 0x608, /* MONITORXrrr */ 0x6fa, /* MWAITXrrr */ 0x201, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4263 */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x719, /* NOOPL_1e */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x921, /* RDSSPQ */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x377, /* ENDBR64 */ 0x376, /* ENDBR32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4335 */ 0x305, /* CVTSI642SSrm */ 0x307, /* CVTSI642SSrr */ /* Table4337 */ 0x31d, /* CVTTSS2SI64rm */ 0x31f, /* CVTTSS2SI64rr */ /* Table4339 */ 0x30d, /* CVTSS2SI64rm_Int */ 0x30e, /* CVTSS2SI64rr_Int */ /* Table4341 */ 0x3b7, /* FXSAVE64 */ 0x3b5, /* FXRSTOR64 */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x8a3, /* PTWRITE64m */ 0x3ba4, /* XRSTOR */ 0x1fe, /* CLRSSBSY */ 0x1fa, /* CLFLUSH */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x912, /* RDFSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x914, /* RDGSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b52, /* WRFSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x3b54, /* WRGSBASE64 */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x8a4, /* PTWRITE64r */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0x40a, /* INCSSPQ */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0xb42, /* UMONITOR64 */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4413 */ 0x84b, /* POPCNT64rm */ 0x84c, /* POPCNT64rr */ /* Table4415 */ 0xb24, /* TZCNT64rm */ 0xb25, /* TZCNT64rr */ /* Table4417 */ 0x51f, /* LZCNT64rm */ 0x520, /* LZCNT64rr */ /* Table4419 */ 0x0, /* */ 0x2bf, /* CMPXCHG16B */ 0x0, /* */ 0x3ba7, /* XRSTORS64 */ 0x3bab, /* XSAVEC64 */ 0x3baf, /* XSAVES64 */ 0x1fe8, /* VMXON */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91b, /* RDRAND32r */ 0x917, /* RDPID64 */ /* Table4435 */ 0x301, /* CVTSI642SDrm */ 0x303, /* CVTSI642SDrr */ /* Table4437 */ 0x315, /* CVTTSD2SI64rm */ 0x317, /* CVTTSD2SI64rr */ /* Table4439 */ 0x2f1, /* CVTSD2SI64rm_Int */ 0x2f2, /* CVTSD2SI64rr_Int */ /* Table4441 */ 0x1f7a, /* VMREAD64mr */ 0x40f, /* INSERTQI */ /* Table4443 */ 0x1fe5, /* VMWRITE64rm */ 0x40e, /* INSERTQ */ /* Table4445 */ 0x3b7, /* FXSAVE64 */ 0x3b5, /* FXRSTOR64 */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x3ba8, /* XSAVE */ 0x3ba4, /* XRSTOR */ 0x3bac, /* XSAVEOPT */ 0x1fa, /* CLFLUSH */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4e7, /* LFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0xb43, /* UMWAIT */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4517 */ 0x0, /* */ 0x2bf, /* CMPXCHG16B */ 0x0, /* */ 0x3ba7, /* XRSTORS64 */ 0x3bab, /* XSAVEC64 */ 0x3baf, /* XSAVES64 */ 0x1f76, /* VMPTRLDm */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91b, /* RDRAND32r */ 0x91e, /* RDSEED32r */ /* Table4533 */ 0x640, /* MOV64toPQIrm */ 0x641, /* MOV64toPQIrr */ /* Table4535 */ 0x68d, /* MOVPQIto64mr */ 0x68e, /* MOVPQIto64rr */ /* Table4537 */ 0x3b7, /* FXSAVE64 */ 0x3b5, /* FXRSTOR64 */ 0x4ca, /* LDMXCSR */ 0xa82, /* STMXCSR */ 0x3ba8, /* XSAVE */ 0x3ba4, /* XRSTOR */ 0x200, /* CLWB */ 0x1fb, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4e7, /* LFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0xb1b, /* TPAUSE */ 0x9f5, /* SFENCE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4609 */ 0x0, /* */ 0x2bf, /* CMPXCHG16B */ 0x0, /* */ 0x3ba7, /* XRSTORS64 */ 0x3bab, /* XSAVEC64 */ 0x3baf, /* XSAVES64 */ 0x1c96, /* VMCLEARm */ 0x1f77, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x91a, /* RDRAND16r */ 0x91d, /* RDSEED16r */ /* Table4625 */ 0x1f6d, /* VMOVUPSrm */ 0x1f6e, /* VMOVUPSrr */ /* Table4627 */ 0x1f6c, /* VMOVUPSmr */ 0x1f6f, /* VMOVUPSrr_REV */ /* Table4629 */ 0x1ea5, /* VMOVLPSrm */ 0x1e93, /* VMOVHLPSrr */ /* Table4631 */ 0x1ea4, /* VMOVLPSmr */ 0x0, /* */ /* Table4633 */ 0x3b0c, /* VUNPCKLPSrm */ 0x3b0d, /* VUNPCKLPSrr */ /* Table4635 */ 0x3ace, /* VUNPCKHPSrm */ 0x3acf, /* VUNPCKHPSrr */ /* Table4637 */ 0x1e9b, /* VMOVHPSrm */ 0x1e9d, /* VMOVLHPSrr */ /* Table4639 */ 0x1e9a, /* VMOVHPSmr */ 0x0, /* */ /* Table4641 */ 0x1d9b, /* VMOVAPSrm */ 0x1d9c, /* VMOVAPSrr */ /* Table4643 */ 0x1d9a, /* VMOVAPSmr */ 0x1d9d, /* VMOVAPSrr_REV */ /* Table4645 */ 0x1ebd, /* VMOVNTPSmr */ 0x0, /* */ /* Table4647 */ 0x3a8e, /* VUCOMISSrm */ 0x3a90, /* VUCOMISSrr */ /* Table4649 */ 0xde4, /* VCOMISSrm */ 0xde6, /* VCOMISSrr */ /* Table4651 */ 0x0, /* */ 0x4a2, /* KNOTWrr */ /* Table4653 */ 0x0, /* */ 0x1ea9, /* VMOVMSKPSrr */ /* Table4655 */ 0x39f5, /* VSQRTPSm */ 0x39f6, /* VSQRTPSr */ /* Table4657 */ 0x38c5, /* VRSQRTPSm */ 0x38c6, /* VRSQRTPSr */ /* Table4659 */ 0x37a1, /* VRCPPSm */ 0x37a2, /* VRCPPSr */ /* Table4661 */ 0xc9e, /* VANDPSrm */ 0xc9f, /* VANDPSrr */ /* Table4663 */ 0xc60, /* VANDNPSrm */ 0xc61, /* VANDNPSrr */ /* Table4665 */ 0x2025, /* VORPSrm */ 0x2026, /* VORPSrr */ /* Table4667 */ 0x3b4a, /* VXORPSrm */ 0x3b4b, /* VXORPSrr */ /* Table4669 */ 0xb9a, /* VADDPSrm */ 0xb9b, /* VADDPSrr */ /* Table4671 */ 0x1fc3, /* VMULPSrm */ 0x1fc4, /* VMULPSrr */ /* Table4673 */ 0xf40, /* VCVTPS2PDrm */ 0xf41, /* VCVTPS2PDrr */ /* Table4675 */ 0xe45, /* VCVTDQ2PSrm */ 0xe46, /* VCVTDQ2PSrr */ /* Table4677 */ 0x3a58, /* VSUBPSrm */ 0x3a59, /* VSUBPSrr */ /* Table4679 */ 0x1d20, /* VMINPSrm */ 0x1d21, /* VMINPSrr */ /* Table4681 */ 0x125c, /* VDIVPSrm */ 0x125d, /* VDIVPSrr */ /* Table4683 */ 0x1c75, /* VMAXPSrm */ 0x1c76, /* VMAXPSrr */ /* Table4685 */ 0x3b4d, /* VZEROUPPER */ /* Table4686 */ 0x49b, /* KMOVWkm */ 0x49a, /* KMOVWkk */ /* Table4688 */ 0x49d, /* KMOVWmk */ 0x0, /* */ /* Table4690 */ 0x0, /* */ 0x49c, /* KMOVWkr */ /* Table4692 */ 0x0, /* */ 0x49e, /* KMOVWrk */ /* Table4694 */ 0x0, /* */ 0x4a9, /* KORTESTWrr */ /* Table4696 */ 0x0, /* */ 0x4b6, /* KTESTWrr */ /* Table4698 */ 0x0, /* */ 0x0, /* */ 0x1be2, /* VLDMXCSR */ 0x3a15, /* VSTMXCSR */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table4714 */ 0xdaa, /* VCMPPSrmi */ 0xdac, /* VCMPPSrri */ /* Table4716 */ 0x39b1, /* VSHUFPSrmi */ 0x39b2, /* VSHUFPSrri */ /* Table4718 */ 0x1f1b, /* VMOVSSrm */ 0x1f1c, /* VMOVSSrr */ /* Table4720 */ 0x1f1a, /* VMOVSSmr */ 0x1f1d, /* VMOVSSrr_REV */ /* Table4722 */ 0x1f09, /* VMOVSLDUPrm */ 0x1f0a, /* VMOVSLDUPrr */ /* Table4724 */ 0x1ef3, /* VMOVSHDUPrm */ 0x1ef4, /* VMOVSHDUPrr */ /* Table4726 */ 0x101b, /* VCVTSI2SSrm */ 0x101d, /* VCVTSI2SSrr */ /* Table4728 */ 0x1172, /* VCVTTSS2SIrm */ 0x1174, /* VCVTTSS2SIrr */ /* Table4730 */ 0x1048, /* VCVTSS2SIrm_Int */ 0x1049, /* VCVTSS2SIrr_Int */ /* Table4732 */ 0x3a11, /* VSQRTSSm */ 0x3a13, /* VSQRTSSr */ /* Table4734 */ 0x38c7, /* VRSQRTSSm */ 0x38c9, /* VRSQRTSSr */ /* Table4736 */ 0x37a3, /* VRCPSSm */ 0x37a5, /* VRCPSSr */ /* Table4738 */ 0xbb6, /* VADDSSrm */ 0xbb8, /* VADDSSrr */ /* Table4740 */ 0x1fdf, /* VMULSSrm */ 0x1fe1, /* VMULSSrr */ /* Table4742 */ 0x103c, /* VCVTSS2SDrm */ 0x103e, /* VCVTSS2SDrr */ /* Table4744 */ 0x10ec, /* VCVTTPS2DQrm */ 0x10ed, /* VCVTTPS2DQrr */ /* Table4746 */ 0x3a74, /* VSUBSSrm */ 0x3a76, /* VSUBSSrr */ /* Table4748 */ 0x1d3c, /* VMINSSrm */ 0x1d3e, /* VMINSSrr */ /* Table4750 */ 0x1278, /* VDIVSSrm */ 0x127a, /* VDIVSSrr */ /* Table4752 */ 0x1c91, /* VMAXSSrm */ 0x1c93, /* VMAXSSrr */ /* Table4754 */ 0x1e8f, /* VMOVDQUrm */ 0x1e90, /* VMOVDQUrr */ /* Table4756 */ 0x3199, /* VPSHUFHWmi */ 0x319a, /* VPSHUFHWri */ /* Table4758 */ 0x1ecb, /* VMOVQI2PQIrm */ 0x1f71, /* VMOVZPQILo2PQIrr */ /* Table4760 */ 0x1e8e, /* VMOVDQUmr */ 0x1e91, /* VMOVDQUrr_REV */ /* Table4762 */ 0xdd0, /* VCMPSSrm */ 0xdd3, /* VCMPSSrr */ /* Table4764 */ 0xe23, /* VCVTDQ2PDrm */ 0xe24, /* VCVTDQ2PDrr */ /* Table4766 */ 0x1ed8, /* VMOVSDrm */ 0x1ed9, /* VMOVSDrr */ /* Table4768 */ 0x1ed7, /* VMOVSDmr */ 0x1eda, /* VMOVSDrr_REV */ /* Table4770 */ 0x1db2, /* VMOVDDUPrm */ 0x1db3, /* VMOVDDUPrr */ /* Table4772 */ 0x1012, /* VCVTSI2SDrm */ 0x1014, /* VCVTSI2SDrr */ /* Table4774 */ 0x1156, /* VCVTTSD2SIrm */ 0x1158, /* VCVTTSD2SIrr */ /* Table4776 */ 0xff6, /* VCVTSD2SIrm_Int */ 0xff7, /* VCVTSD2SIrr_Int */ /* Table4778 */ 0x3a02, /* VSQRTSDm */ 0x3a04, /* VSQRTSDr */ /* Table4780 */ 0xba7, /* VADDSDrm */ 0xba9, /* VADDSDrr */ /* Table4782 */ 0x1fd0, /* VMULSDrm */ 0x1fd2, /* VMULSDrr */ /* Table4784 */ 0x1003, /* VCVTSD2SSrm */ 0x1005, /* VCVTSD2SSrr */ /* Table4786 */ 0x3a65, /* VSUBSDrm */ 0x3a67, /* VSUBSDrr */ /* Table4788 */ 0x1d2d, /* VMINSDrm */ 0x1d2f, /* VMINSDrr */ /* Table4790 */ 0x1269, /* VDIVSDrm */ 0x126b, /* VDIVSDrr */ /* Table4792 */ 0x1c82, /* VMAXSDrm */ 0x1c84, /* VMAXSDrr */ /* Table4794 */ 0x31af, /* VPSHUFLWmi */ 0x31b0, /* VPSHUFLWri */ /* Table4796 */ 0x1b86, /* VHADDPSrm */ 0x1b87, /* VHADDPSrr */ /* Table4798 */ 0x1b8e, /* VHSUBPSrm */ 0x1b8f, /* VHSUBPSrr */ /* Table4800 */ 0x0, /* */ 0x492, /* KMOVDkr */ /* Table4802 */ 0x0, /* */ 0x494, /* KMOVDrk */ /* Table4804 */ 0xdbc, /* VCMPSDrm */ 0xdbf, /* VCMPSDrr */ /* Table4806 */ 0xbc0, /* VADDSUBPSrm */ 0xbc1, /* VADDSUBPSrr */ /* Table4808 */ 0xe67, /* VCVTPD2DQrm */ 0xe68, /* VCVTPD2DQrr */ /* Table4810 */ 0x1be1, /* VLDDQUrm */ 0x0, /* */ /* Table4812 */ 0x1f44, /* VMOVUPDrm */ 0x1f45, /* VMOVUPDrr */ /* Table4814 */ 0x1f43, /* VMOVUPDmr */ 0x1f46, /* VMOVUPDrr_REV */ /* Table4816 */ 0x1ea1, /* VMOVLPDrm */ 0x0, /* */ /* Table4818 */ 0x1ea0, /* VMOVLPDmr */ 0x0, /* */ /* Table4820 */ 0x3aed, /* VUNPCKLPDrm */ 0x3aee, /* VUNPCKLPDrr */ /* Table4822 */ 0x3aaf, /* VUNPCKHPDrm */ 0x3ab0, /* VUNPCKHPDrr */ /* Table4824 */ 0x1e97, /* VMOVHPDrm */ 0x0, /* */ /* Table4826 */ 0x1e96, /* VMOVHPDmr */ 0x0, /* */ /* Table4828 */ 0x1d72, /* VMOVAPDrm */ 0x1d73, /* VMOVAPDrr */ /* Table4830 */ 0x1d71, /* VMOVAPDmr */ 0x1d74, /* VMOVAPDrr_REV */ /* Table4832 */ 0x1eb8, /* VMOVNTPDmr */ 0x0, /* */ /* Table4834 */ 0x3a85, /* VUCOMISDrm */ 0x3a87, /* VUCOMISDrr */ /* Table4836 */ 0xddb, /* VCOMISDrm */ 0xddd, /* VCOMISDrr */ /* Table4838 */ 0x0, /* */ 0x49f, /* KNOTBrr */ /* Table4840 */ 0x0, /* */ 0x1ea7, /* VMOVMSKPDrr */ /* Table4842 */ 0x39d3, /* VSQRTPDm */ 0x39d4, /* VSQRTPDr */ /* Table4844 */ 0xc7f, /* VANDPDrm */ 0xc80, /* VANDPDrr */ /* Table4846 */ 0xc41, /* VANDNPDrm */ 0xc42, /* VANDNPDrr */ /* Table4848 */ 0x2006, /* VORPDrm */ 0x2007, /* VORPDrr */ /* Table4850 */ 0x3b2b, /* VXORPDrm */ 0x3b2c, /* VXORPDrr */ /* Table4852 */ 0xb78, /* VADDPDrm */ 0xb79, /* VADDPDrr */ /* Table4854 */ 0x1fa1, /* VMULPDrm */ 0x1fa2, /* VMULPDrr */ /* Table4856 */ 0xe89, /* VCVTPD2PSrm */ 0xe8a, /* VCVTPD2PSrr */ /* Table4858 */ 0xf1e, /* VCVTPS2DQrm */ 0xf1f, /* VCVTPS2DQrr */ /* Table4860 */ 0x3a36, /* VSUBPDrm */ 0x3a37, /* VSUBPDrr */ /* Table4862 */ 0x1cfe, /* VMINPDrm */ 0x1cff, /* VMINPDrr */ /* Table4864 */ 0x123a, /* VDIVPDrm */ 0x123b, /* VDIVPDrr */ /* Table4866 */ 0x1c53, /* VMAXPDrm */ 0x1c54, /* VMAXPDrr */ /* Table4868 */ 0x3655, /* VPUNPCKLBWrm */ 0x3656, /* VPUNPCKLBWrr */ /* Table4870 */ 0x36a9, /* VPUNPCKLWDrm */ 0x36aa, /* VPUNPCKLWDrr */ /* Table4872 */ 0x3674, /* VPUNPCKLDQrm */ 0x3675, /* VPUNPCKLDQrr */ /* Table4874 */ 0x20c6, /* VPACKSSWBrm */ 0x20c7, /* VPACKSSWBrr */ /* Table4876 */ 0x2409, /* VPCMPGTBrm */ 0x240a, /* VPCMPGTBrr */ /* Table4878 */ 0x2445, /* VPCMPGTWrm */ 0x2446, /* VPCMPGTWrr */ /* Table4880 */ 0x241f, /* VPCMPGTDrm */ 0x2420, /* VPCMPGTDrr */ /* Table4882 */ 0x20fb, /* VPACKUSWBrm */ 0x20fc, /* VPACKUSWBrr */ /* Table4884 */ 0x35eb, /* VPUNPCKHBWrm */ 0x35ec, /* VPUNPCKHBWrr */ /* Table4886 */ 0x363f, /* VPUNPCKHWDrm */ 0x3640, /* VPUNPCKHWDrr */ /* Table4888 */ 0x360a, /* VPUNPCKHDQrm */ 0x360b, /* VPUNPCKHDQrr */ /* Table4890 */ 0x20b0, /* VPACKSSDWrm */ 0x20b1, /* VPACKSSDWrr */ /* Table4892 */ 0x3693, /* VPUNPCKLQDQrm */ 0x3694, /* VPUNPCKLQDQrr */ /* Table4894 */ 0x3629, /* VPUNPCKHQDQrm */ 0x362a, /* VPUNPCKHQDQrr */ /* Table4896 */ 0x1db6, /* VMOVDI2PDIrm */ 0x1db7, /* VMOVDI2PDIrr */ /* Table4898 */ 0x1e03, /* VMOVDQArm */ 0x1e04, /* VMOVDQArr */ /* Table4900 */ 0x3183, /* VPSHUFDmi */ 0x3184, /* VPSHUFDri */ /* Table4902 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3460, /* VPSRLWri */ 0x0, /* */ 0x3378, /* VPSRAWri */ 0x0, /* */ 0x32a2, /* VPSLLWri */ 0x0, /* */ /* Table4918 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33b3, /* VPSRLDri */ 0x0, /* */ 0x32d5, /* VPSRADri */ 0x0, /* */ 0x31f5, /* VPSLLDri */ 0x0, /* */ /* Table4934 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33e6, /* VPSRLQri */ 0x3382, /* VPSRLDQri */ 0x0, /* */ 0x0, /* */ 0x3228, /* VPSLLQri */ 0x31c4, /* VPSLLDQri */ /* Table4950 */ 0x23b9, /* VPCMPEQBrm */ 0x23ba, /* VPCMPEQBrr */ /* Table4952 */ 0x23f5, /* VPCMPEQWrm */ 0x23f6, /* VPCMPEQWrr */ /* Table4954 */ 0x23cf, /* VPCMPEQDrm */ 0x23d0, /* VPCMPEQDrr */ /* Table4956 */ 0x1b82, /* VHADDPDrm */ 0x1b83, /* VHADDPDrr */ /* Table4958 */ 0x1b8a, /* VHSUBPDrm */ 0x1b8b, /* VHSUBPDrr */ /* Table4960 */ 0x1ec0, /* VMOVPDI2DImr */ 0x1ec1, /* VMOVPDI2DIrr */ /* Table4962 */ 0x1e02, /* VMOVDQAmr */ 0x1e05, /* VMOVDQArr_REV */ /* Table4964 */ 0x48c, /* KMOVBkm */ 0x48b, /* KMOVBkk */ /* Table4966 */ 0x48e, /* KMOVBmk */ 0x0, /* */ /* Table4968 */ 0x0, /* */ 0x48d, /* KMOVBkr */ /* Table4970 */ 0x0, /* */ 0x48f, /* KMOVBrk */ /* Table4972 */ 0x0, /* */ 0x4a6, /* KORTESTBrr */ /* Table4974 */ 0x0, /* */ 0x4b3, /* KTESTBrr */ /* Table4976 */ 0xd7a, /* VCMPPDrmi */ 0xd7c, /* VCMPPDrri */ /* Table4978 */ 0x28f9, /* VPINSRWrm */ 0x28fa, /* VPINSRWrr */ /* Table4980 */ 0x0, /* */ 0x289d, /* VPEXTRWrr */ /* Table4982 */ 0x3992, /* VSHUFPDrmi */ 0x3993, /* VSHUFPDrri */ /* Table4984 */ 0xbbc, /* VADDSUBPDrm */ 0xbbd, /* VADDSUBPDrr */ /* Table4986 */ 0x3461, /* VPSRLWrm */ 0x3462, /* VPSRLWrr */ /* Table4988 */ 0x33b4, /* VPSRLDrm */ 0x33b5, /* VPSRLDrr */ /* Table4990 */ 0x33e7, /* VPSRLQrm */ 0x33e8, /* VPSRLQrr */ /* Table4992 */ 0x214f, /* VPADDQrm */ 0x2150, /* VPADDQrr */ /* Table4994 */ 0x2e2a, /* VPMULLWrm */ 0x2e2b, /* VPMULLWrr */ /* Table4996 */ 0x1ec4, /* VMOVPQI2QImr */ 0x1ec5, /* VMOVPQI2QIrr */ /* Table4998 */ 0x0, /* */ 0x2b7c, /* VPMOVMSKBrr */ /* Table5000 */ 0x34f7, /* VPSUBUSBrm */ 0x34f8, /* VPSUBUSBrr */ /* Table5002 */ 0x350d, /* VPSUBUSWrm */ 0x350e, /* VPSUBUSWrr */ /* Table5004 */ 0x2af9, /* VPMINUBrm */ 0x2afa, /* VPMINUBrr */ /* Table5006 */ 0x2247, /* VPANDrm */ 0x2248, /* VPANDrr */ /* Table5008 */ 0x2191, /* VPADDUSBrm */ 0x2192, /* VPADDUSBrr */ /* Table5010 */ 0x21a7, /* VPADDUSWrm */ 0x21a8, /* VPADDUSWrr */ /* Table5012 */ 0x2a2d, /* VPMAXUBrm */ 0x2a2e, /* VPMAXUBrr */ /* Table5014 */ 0x2228, /* VPANDNrm */ 0x2229, /* VPANDNrr */ /* Table5016 */ 0x225d, /* VPAVGBrm */ 0x225e, /* VPAVGBrr */ /* Table5018 */ 0x3379, /* VPSRAWrm */ 0x337a, /* VPSRAWrr */ /* Table5020 */ 0x32d6, /* VPSRADrm */ 0x32d7, /* VPSRADrr */ /* Table5022 */ 0x2273, /* VPAVGWrm */ 0x2274, /* VPAVGWrr */ /* Table5024 */ 0x2dc4, /* VPMULHUWrm */ 0x2dc5, /* VPMULHUWrr */ /* Table5026 */ 0x2dda, /* VPMULHWrm */ 0x2ddb, /* VPMULHWrr */ /* Table5028 */ 0x1070, /* VCVTTPD2DQrm */ 0x1071, /* VCVTTPD2DQrr */ /* Table5030 */ 0x1eb3, /* VMOVNTDQmr */ 0x0, /* */ /* Table5032 */ 0x34cb, /* VPSUBSBrm */ 0x34cc, /* VPSUBSBrr */ /* Table5034 */ 0x34e1, /* VPSUBSWrm */ 0x34e2, /* VPSUBSWrr */ /* Table5036 */ 0x2ae3, /* VPMINSWrm */ 0x2ae4, /* VPMINSWrr */ /* Table5038 */ 0x2ef8, /* VPORrm */ 0x2ef9, /* VPORrr */ /* Table5040 */ 0x2165, /* VPADDSBrm */ 0x2166, /* VPADDSBrr */ /* Table5042 */ 0x217b, /* VPADDSWrm */ 0x217c, /* VPADDSWrr */ /* Table5044 */ 0x2a17, /* VPMAXSWrm */ 0x2a18, /* VPMAXSWrr */ /* Table5046 */ 0x36e3, /* VPXORrm */ 0x36e4, /* VPXORrr */ /* Table5048 */ 0x32a3, /* VPSLLWrm */ 0x32a4, /* VPSLLWrr */ /* Table5050 */ 0x31f6, /* VPSLLDrm */ 0x31f7, /* VPSLLDrr */ /* Table5052 */ 0x3229, /* VPSLLQrm */ 0x322a, /* VPSLLQrr */ /* Table5054 */ 0x2e64, /* VPMULUDQrm */ 0x2e65, /* VPMULUDQrr */ /* Table5056 */ 0x29a9, /* VPMADDWDrm */ 0x29aa, /* VPMADDWDrr */ /* Table5058 */ 0x2ff6, /* VPSADBWrm */ 0x2ff7, /* VPSADBWrr */ /* Table5060 */ 0x0, /* */ 0x1be3, /* VMASKMOVDQU */ /* Table5062 */ 0x3477, /* VPSUBBrm */ 0x3478, /* VPSUBBrr */ /* Table5064 */ 0x3523, /* VPSUBWrm */ 0x3524, /* VPSUBWrr */ /* Table5066 */ 0x3496, /* VPSUBDrm */ 0x3497, /* VPSUBDrr */ /* Table5068 */ 0x34b5, /* VPSUBQrm */ 0x34b6, /* VPSUBQrr */ /* Table5070 */ 0x2111, /* VPADDBrm */ 0x2112, /* VPADDBrr */ /* Table5072 */ 0x21bd, /* VPADDWrm */ 0x21be, /* VPADDWrr */ /* Table5074 */ 0x2130, /* VPADDDrm */ 0x2131, /* VPADDDrr */ /* Table5076 */ 0x0, /* */ 0x4a1, /* KNOTQrr */ /* Table5078 */ 0x496, /* KMOVQkm */ 0x495, /* KMOVQkk */ /* Table5080 */ 0x498, /* KMOVQmk */ 0x0, /* */ /* Table5082 */ 0x0, /* */ 0x4a8, /* KORTESTQrr */ /* Table5084 */ 0x0, /* */ 0x4b5, /* KTESTQrr */ /* Table5086 */ 0x102d, /* VCVTSI642SSrm */ 0x102f, /* VCVTSI642SSrr */ /* Table5088 */ 0x1169, /* VCVTTSS2SI64rm */ 0x116b, /* VCVTTSS2SI64rr */ /* Table5090 */ 0x1043, /* VCVTSS2SI64rm_Int */ 0x1044, /* VCVTSS2SI64rr_Int */ /* Table5092 */ 0x1024, /* VCVTSI642SDrm */ 0x1026, /* VCVTSI642SDrr */ /* Table5094 */ 0x114d, /* VCVTTSD2SI64rm */ 0x114f, /* VCVTTSD2SI64rr */ /* Table5096 */ 0xff1, /* VCVTSD2SI64rm_Int */ 0xff2, /* VCVTSD2SI64rr_Int */ /* Table5098 */ 0x0, /* */ 0x497, /* KMOVQkr */ /* Table5100 */ 0x0, /* */ 0x499, /* KMOVQrk */ /* Table5102 */ 0x0, /* */ 0x4a0, /* KNOTDrr */ /* Table5104 */ 0x1d46, /* VMOV64toPQIrm */ 0x1d47, /* VMOV64toPQIrr */ /* Table5106 */ 0x1ec8, /* VMOVPQIto64mr */ 0x1ec9, /* VMOVPQIto64rr */ /* Table5108 */ 0x491, /* KMOVDkm */ 0x490, /* KMOVDkk */ /* Table5110 */ 0x493, /* KMOVDmk */ 0x0, /* */ /* Table5112 */ 0x0, /* */ 0x4a7, /* KORTESTDrr */ /* Table5114 */ 0x0, /* */ 0x4b4, /* KTESTDrr */ /* Table5116 */ 0x1f48, /* VMOVUPSYrm */ 0x1f49, /* VMOVUPSYrr */ /* Table5118 */ 0x1f47, /* VMOVUPSYmr */ 0x1f4a, /* VMOVUPSYrr_REV */ /* Table5120 */ 0x3aef, /* VUNPCKLPSYrm */ 0x3af0, /* VUNPCKLPSYrr */ /* Table5122 */ 0x3ab1, /* VUNPCKHPSYrm */ 0x3ab2, /* VUNPCKHPSYrr */ /* Table5124 */ 0x1d76, /* VMOVAPSYrm */ 0x1d77, /* VMOVAPSYrr */ /* Table5126 */ 0x1d75, /* VMOVAPSYmr */ 0x1d78, /* VMOVAPSYrr_REV */ /* Table5128 */ 0x1eb9, /* VMOVNTPSYmr */ 0x0, /* */ /* Table5130 */ 0x0, /* */ 0x48a, /* KANDWrr */ /* Table5132 */ 0x0, /* */ 0x488, /* KANDNWrr */ /* Table5134 */ 0x0, /* */ 0x4aa, /* KORWrr */ /* Table5136 */ 0x0, /* */ 0x4bd, /* KXNORWrr */ /* Table5138 */ 0x0, /* */ 0x4c1, /* KXORWrr */ /* Table5140 */ 0x0, /* */ 0x482, /* KADDWrr */ /* Table5142 */ 0x0, /* */ 0x4b9, /* KUNPCKWDrr */ /* Table5144 */ 0x0, /* */ 0x1ea8, /* VMOVMSKPSYrr */ /* Table5146 */ 0x39d5, /* VSQRTPSYm */ 0x39d6, /* VSQRTPSYr */ /* Table5148 */ 0x38c3, /* VRSQRTPSYm */ 0x38c4, /* VRSQRTPSYr */ /* Table5150 */ 0x379f, /* VRCPPSYm */ 0x37a0, /* VRCPPSYr */ /* Table5152 */ 0xc81, /* VANDPSYrm */ 0xc82, /* VANDPSYrr */ /* Table5154 */ 0xc43, /* VANDNPSYrm */ 0xc44, /* VANDNPSYrr */ /* Table5156 */ 0x2008, /* VORPSYrm */ 0x2009, /* VORPSYrr */ /* Table5158 */ 0x3b2d, /* VXORPSYrm */ 0x3b2e, /* VXORPSYrr */ /* Table5160 */ 0xb7a, /* VADDPSYrm */ 0xb7b, /* VADDPSYrr */ /* Table5162 */ 0x1fa3, /* VMULPSYrm */ 0x1fa4, /* VMULPSYrr */ /* Table5164 */ 0xf20, /* VCVTPS2PDYrm */ 0xf21, /* VCVTPS2PDYrr */ /* Table5166 */ 0xe25, /* VCVTDQ2PSYrm */ 0xe26, /* VCVTDQ2PSYrr */ /* Table5168 */ 0x3a38, /* VSUBPSYrm */ 0x3a39, /* VSUBPSYrr */ /* Table5170 */ 0x1d00, /* VMINPSYrm */ 0x1d01, /* VMINPSYrr */ /* Table5172 */ 0x123c, /* VDIVPSYrm */ 0x123d, /* VDIVPSYrr */ /* Table5174 */ 0x1c55, /* VMAXPSYrm */ 0x1c56, /* VMAXPSYrr */ /* Table5176 */ 0x3b4c, /* VZEROALL */ /* Table5177 */ 0xd7e, /* VCMPPSYrmi */ 0xd80, /* VCMPPSYrri */ /* Table5179 */ 0x3994, /* VSHUFPSYrmi */ 0x3995, /* VSHUFPSYrri */ /* Table5181 */ 0x1ef5, /* VMOVSLDUPYrm */ 0x1ef6, /* VMOVSLDUPYrr */ /* Table5183 */ 0x1edf, /* VMOVSHDUPYrm */ 0x1ee0, /* VMOVSHDUPYrr */ /* Table5185 */ 0x10cc, /* VCVTTPS2DQYrm */ 0x10cd, /* VCVTTPS2DQYrr */ /* Table5187 */ 0x1e8b, /* VMOVDQUYrm */ 0x1e8c, /* VMOVDQUYrr */ /* Table5189 */ 0x3185, /* VPSHUFHWYmi */ 0x3186, /* VPSHUFHWYri */ /* Table5191 */ 0x1e8a, /* VMOVDQUYmr */ 0x1e8d, /* VMOVDQUYrr_REV */ /* Table5193 */ 0xe06, /* VCVTDQ2PDYrm */ 0xe07, /* VCVTDQ2PDYrr */ /* Table5195 */ 0x1d9e, /* VMOVDDUPYrm */ 0x1d9f, /* VMOVDDUPYrr */ /* Table5197 */ 0x319b, /* VPSHUFLWYmi */ 0x319c, /* VPSHUFLWYri */ /* Table5199 */ 0x1b84, /* VHADDPSYrm */ 0x1b85, /* VHADDPSYrr */ /* Table5201 */ 0x1b8c, /* VHSUBPSYrm */ 0x1b8d, /* VHSUBPSYrr */ /* Table5203 */ 0xbbe, /* VADDSUBPSYrm */ 0xbbf, /* VADDSUBPSYrr */ /* Table5205 */ 0xe47, /* VCVTPD2DQYrm */ 0xe48, /* VCVTPD2DQYrr */ /* Table5207 */ 0x1be0, /* VLDDQUYrm */ 0x0, /* */ /* Table5209 */ 0x1f1f, /* VMOVUPDYrm */ 0x1f20, /* VMOVUPDYrr */ /* Table5211 */ 0x1f1e, /* VMOVUPDYmr */ 0x1f21, /* VMOVUPDYrr_REV */ /* Table5213 */ 0x3ad0, /* VUNPCKLPDYrm */ 0x3ad1, /* VUNPCKLPDYrr */ /* Table5215 */ 0x3a92, /* VUNPCKHPDYrm */ 0x3a93, /* VUNPCKHPDYrr */ /* Table5217 */ 0x1d4d, /* VMOVAPDYrm */ 0x1d4e, /* VMOVAPDYrr */ /* Table5219 */ 0x1d4c, /* VMOVAPDYmr */ 0x1d4f, /* VMOVAPDYrr_REV */ /* Table5221 */ 0x1eb4, /* VMOVNTPDYmr */ 0x0, /* */ /* Table5223 */ 0x0, /* */ 0x483, /* KANDBrr */ /* Table5225 */ 0x0, /* */ 0x485, /* KANDNBrr */ /* Table5227 */ 0x0, /* */ 0x4a3, /* KORBrr */ /* Table5229 */ 0x0, /* */ 0x4ba, /* KXNORBrr */ /* Table5231 */ 0x0, /* */ 0x4be, /* KXORBrr */ /* Table5233 */ 0x0, /* */ 0x47f, /* KADDBrr */ /* Table5235 */ 0x0, /* */ 0x4b7, /* KUNPCKBWrr */ /* Table5237 */ 0x0, /* */ 0x1ea6, /* VMOVMSKPDYrr */ /* Table5239 */ 0x39b3, /* VSQRTPDYm */ 0x39b4, /* VSQRTPDYr */ /* Table5241 */ 0xc62, /* VANDPDYrm */ 0xc63, /* VANDPDYrr */ /* Table5243 */ 0xc24, /* VANDNPDYrm */ 0xc25, /* VANDNPDYrr */ /* Table5245 */ 0x1fe9, /* VORPDYrm */ 0x1fea, /* VORPDYrr */ /* Table5247 */ 0x3b0e, /* VXORPDYrm */ 0x3b0f, /* VXORPDYrr */ /* Table5249 */ 0xb58, /* VADDPDYrm */ 0xb59, /* VADDPDYrr */ /* Table5251 */ 0x1f81, /* VMULPDYrm */ 0x1f82, /* VMULPDYrr */ /* Table5253 */ 0xe69, /* VCVTPD2PSYrm */ 0xe6a, /* VCVTPD2PSYrr */ /* Table5255 */ 0xefe, /* VCVTPS2DQYrm */ 0xeff, /* VCVTPS2DQYrr */ /* Table5257 */ 0x3a16, /* VSUBPDYrm */ 0x3a17, /* VSUBPDYrr */ /* Table5259 */ 0x1cde, /* VMINPDYrm */ 0x1cdf, /* VMINPDYrr */ /* Table5261 */ 0x121a, /* VDIVPDYrm */ 0x121b, /* VDIVPDYrr */ /* Table5263 */ 0x1c33, /* VMAXPDYrm */ 0x1c34, /* VMAXPDYrr */ /* Table5265 */ 0x3641, /* VPUNPCKLBWYrm */ 0x3642, /* VPUNPCKLBWYrr */ /* Table5267 */ 0x3695, /* VPUNPCKLWDYrm */ 0x3696, /* VPUNPCKLWDYrr */ /* Table5269 */ 0x3657, /* VPUNPCKLDQYrm */ 0x3658, /* VPUNPCKLDQYrr */ /* Table5271 */ 0x20b2, /* VPACKSSWBYrm */ 0x20b3, /* VPACKSSWBYrr */ /* Table5273 */ 0x23fb, /* VPCMPGTBYrm */ 0x23fc, /* VPCMPGTBYrr */ /* Table5275 */ 0x2437, /* VPCMPGTWYrm */ 0x2438, /* VPCMPGTWYrr */ /* Table5277 */ 0x240b, /* VPCMPGTDYrm */ 0x240c, /* VPCMPGTDYrr */ /* Table5279 */ 0x20e7, /* VPACKUSWBYrm */ 0x20e8, /* VPACKUSWBYrr */ /* Table5281 */ 0x35d7, /* VPUNPCKHBWYrm */ 0x35d8, /* VPUNPCKHBWYrr */ /* Table5283 */ 0x362b, /* VPUNPCKHWDYrm */ 0x362c, /* VPUNPCKHWDYrr */ /* Table5285 */ 0x35ed, /* VPUNPCKHDQYrm */ 0x35ee, /* VPUNPCKHDQYrr */ /* Table5287 */ 0x2093, /* VPACKSSDWYrm */ 0x2094, /* VPACKSSDWYrr */ /* Table5289 */ 0x3676, /* VPUNPCKLQDQYrm */ 0x3677, /* VPUNPCKLQDQYrr */ /* Table5291 */ 0x360c, /* VPUNPCKHQDQYrm */ 0x360d, /* VPUNPCKHQDQYrr */ /* Table5293 */ 0x1dff, /* VMOVDQAYrm */ 0x1e00, /* VMOVDQAYrr */ /* Table5295 */ 0x3166, /* VPSHUFDYmi */ 0x3167, /* VPSHUFDYri */ /* Table5297 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3439, /* VPSRLWYri */ 0x0, /* */ 0x3351, /* VPSRAWYri */ 0x0, /* */ 0x327b, /* VPSLLWYri */ 0x0, /* */ /* Table5313 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3383, /* VPSRLDYri */ 0x0, /* */ 0x32a5, /* VPSRADYri */ 0x0, /* */ 0x31c5, /* VPSLLDYri */ 0x0, /* */ /* Table5329 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33b6, /* VPSRLQYri */ 0x337b, /* VPSRLDQYri */ 0x0, /* */ 0x0, /* */ 0x31f8, /* VPSLLQYri */ 0x31bd, /* VPSLLDQYri */ /* Table5345 */ 0x23ab, /* VPCMPEQBYrm */ 0x23ac, /* VPCMPEQBYrr */ /* Table5347 */ 0x23e7, /* VPCMPEQWYrm */ 0x23e8, /* VPCMPEQWYrr */ /* Table5349 */ 0x23bb, /* VPCMPEQDYrm */ 0x23bc, /* VPCMPEQDYrr */ /* Table5351 */ 0x1b80, /* VHADDPDYrm */ 0x1b81, /* VHADDPDYrr */ /* Table5353 */ 0x1b88, /* VHSUBPDYrm */ 0x1b89, /* VHSUBPDYrr */ /* Table5355 */ 0x1dfe, /* VMOVDQAYmr */ 0x1e01, /* VMOVDQAYrr_REV */ /* Table5357 */ 0xd4e, /* VCMPPDYrmi */ 0xd50, /* VCMPPDYrri */ /* Table5359 */ 0x3975, /* VSHUFPDYrmi */ 0x3976, /* VSHUFPDYrri */ /* Table5361 */ 0xbba, /* VADDSUBPDYrm */ 0xbbb, /* VADDSUBPDYrr */ /* Table5363 */ 0x343a, /* VPSRLWYrm */ 0x343b, /* VPSRLWYrr */ /* Table5365 */ 0x3384, /* VPSRLDYrm */ 0x3385, /* VPSRLDYrr */ /* Table5367 */ 0x33b7, /* VPSRLQYrm */ 0x33b8, /* VPSRLQYrr */ /* Table5369 */ 0x2132, /* VPADDQYrm */ 0x2133, /* VPADDQYrr */ /* Table5371 */ 0x2e16, /* VPMULLWYrm */ 0x2e17, /* VPMULLWYrr */ /* Table5373 */ 0x0, /* */ 0x2b7b, /* VPMOVMSKBYrr */ /* Table5375 */ 0x34e3, /* VPSUBUSBYrm */ 0x34e4, /* VPSUBUSBYrr */ /* Table5377 */ 0x34f9, /* VPSUBUSWYrm */ 0x34fa, /* VPSUBUSWYrr */ /* Table5379 */ 0x2ae5, /* VPMINUBYrm */ 0x2ae6, /* VPMINUBYrr */ /* Table5381 */ 0x2245, /* VPANDYrm */ 0x2246, /* VPANDYrr */ /* Table5383 */ 0x217d, /* VPADDUSBYrm */ 0x217e, /* VPADDUSBYrr */ /* Table5385 */ 0x2193, /* VPADDUSWYrm */ 0x2194, /* VPADDUSWYrr */ /* Table5387 */ 0x2a19, /* VPMAXUBYrm */ 0x2a1a, /* VPMAXUBYrr */ /* Table5389 */ 0x2226, /* VPANDNYrm */ 0x2227, /* VPANDNYrr */ /* Table5391 */ 0x2249, /* VPAVGBYrm */ 0x224a, /* VPAVGBYrr */ /* Table5393 */ 0x3352, /* VPSRAWYrm */ 0x3353, /* VPSRAWYrr */ /* Table5395 */ 0x32a6, /* VPSRADYrm */ 0x32a7, /* VPSRADYrr */ /* Table5397 */ 0x225f, /* VPAVGWYrm */ 0x2260, /* VPAVGWYrr */ /* Table5399 */ 0x2db0, /* VPMULHUWYrm */ 0x2db1, /* VPMULHUWYrr */ /* Table5401 */ 0x2dc6, /* VPMULHWYrm */ 0x2dc7, /* VPMULHWYrr */ /* Table5403 */ 0x1050, /* VCVTTPD2DQYrm */ 0x1051, /* VCVTTPD2DQYrr */ /* Table5405 */ 0x1eaf, /* VMOVNTDQYmr */ 0x0, /* */ /* Table5407 */ 0x34b7, /* VPSUBSBYrm */ 0x34b8, /* VPSUBSBYrr */ /* Table5409 */ 0x34cd, /* VPSUBSWYrm */ 0x34ce, /* VPSUBSWYrr */ /* Table5411 */ 0x2acf, /* VPMINSWYrm */ 0x2ad0, /* VPMINSWYrr */ /* Table5413 */ 0x2ef6, /* VPORYrm */ 0x2ef7, /* VPORYrr */ /* Table5415 */ 0x2151, /* VPADDSBYrm */ 0x2152, /* VPADDSBYrr */ /* Table5417 */ 0x2167, /* VPADDSWYrm */ 0x2168, /* VPADDSWYrr */ /* Table5419 */ 0x2a03, /* VPMAXSWYrm */ 0x2a04, /* VPMAXSWYrr */ /* Table5421 */ 0x36e1, /* VPXORYrm */ 0x36e2, /* VPXORYrr */ /* Table5423 */ 0x327c, /* VPSLLWYrm */ 0x327d, /* VPSLLWYrr */ /* Table5425 */ 0x31c6, /* VPSLLDYrm */ 0x31c7, /* VPSLLDYrr */ /* Table5427 */ 0x31f9, /* VPSLLQYrm */ 0x31fa, /* VPSLLQYrr */ /* Table5429 */ 0x2e47, /* VPMULUDQYrm */ 0x2e48, /* VPMULUDQYrr */ /* Table5431 */ 0x2995, /* VPMADDWDYrm */ 0x2996, /* VPMADDWDYrr */ /* Table5433 */ 0x2fee, /* VPSADBWYrm */ 0x2fef, /* VPSADBWYrr */ /* Table5435 */ 0x3463, /* VPSUBBYrm */ 0x3464, /* VPSUBBYrr */ /* Table5437 */ 0x350f, /* VPSUBWYrm */ 0x3510, /* VPSUBWYrr */ /* Table5439 */ 0x3479, /* VPSUBDYrm */ 0x347a, /* VPSUBDYrr */ /* Table5441 */ 0x3498, /* VPSUBQYrm */ 0x3499, /* VPSUBQYrr */ /* Table5443 */ 0x20fd, /* VPADDBYrm */ 0x20fe, /* VPADDBYrr */ /* Table5445 */ 0x21a9, /* VPADDWYrm */ 0x21aa, /* VPADDWYrr */ /* Table5447 */ 0x2113, /* VPADDDYrm */ 0x2114, /* VPADDDYrr */ /* Table5449 */ 0x0, /* */ 0x489, /* KANDQrr */ /* Table5451 */ 0x0, /* */ 0x487, /* KANDNQrr */ /* Table5453 */ 0x0, /* */ 0x4a5, /* KORQrr */ /* Table5455 */ 0x0, /* */ 0x4bc, /* KXNORQrr */ /* Table5457 */ 0x0, /* */ 0x4c0, /* KXORQrr */ /* Table5459 */ 0x0, /* */ 0x481, /* KADDQrr */ /* Table5461 */ 0x0, /* */ 0x4b8, /* KUNPCKDQrr */ /* Table5463 */ 0x0, /* */ 0x484, /* KANDDrr */ /* Table5465 */ 0x0, /* */ 0x486, /* KANDNDrr */ /* Table5467 */ 0x0, /* */ 0x4a4, /* KORDrr */ /* Table5469 */ 0x0, /* */ 0x4bb, /* KXNORDrr */ /* Table5471 */ 0x0, /* */ 0x4bf, /* KXORDrr */ /* Table5473 */ 0x0, /* */ 0x480, /* KADDDrr */ /* Table5475 */ 0x1f4d, /* VMOVUPSZ128rm */ 0x1f50, /* VMOVUPSZ128rr */ /* Table5477 */ 0x1f4b, /* VMOVUPSZ128mr */ 0x1f51, /* VMOVUPSZ128rr_REV */ /* Table5479 */ 0x1ea3, /* VMOVLPSZ128rm */ 0x1e92, /* VMOVHLPSZrr */ /* Table5481 */ 0x1ea2, /* VMOVLPSZ128mr */ 0x0, /* */ /* Table5483 */ 0x3af1, /* VUNPCKLPSZ128rm */ 0x3af7, /* VUNPCKLPSZ128rr */ /* Table5485 */ 0x3ab3, /* VUNPCKHPSZ128rm */ 0x3ab9, /* VUNPCKHPSZ128rr */ /* Table5487 */ 0x1e99, /* VMOVHPSZ128rm */ 0x1e9c, /* VMOVLHPSZrr */ /* Table5489 */ 0x1e98, /* VMOVHPSZ128mr */ 0x0, /* */ /* Table5491 */ 0x1d7b, /* VMOVAPSZ128rm */ 0x1d7e, /* VMOVAPSZ128rr */ /* Table5493 */ 0x1d79, /* VMOVAPSZ128mr */ 0x1d7f, /* VMOVAPSZ128rr_REV */ /* Table5495 */ 0x1eba, /* VMOVNTPSZ128mr */ 0x0, /* */ /* Table5497 */ 0x3a89, /* VUCOMISSZrm */ 0x3a8b, /* VUCOMISSZrr */ /* Table5499 */ 0xddf, /* VCOMISSZrm */ 0xde1, /* VCOMISSZrr */ /* Table5501 */ 0x39d7, /* VSQRTPSZ128m */ 0x39dd, /* VSQRTPSZ128r */ /* Table5503 */ 0xc83, /* VANDPSZ128rm */ 0xc89, /* VANDPSZ128rr */ /* Table5505 */ 0xc45, /* VANDNPSZ128rm */ 0xc4b, /* VANDNPSZ128rr */ /* Table5507 */ 0x200a, /* VORPSZ128rm */ 0x2010, /* VORPSZ128rr */ /* Table5509 */ 0x3b2f, /* VXORPSZ128rm */ 0x3b35, /* VXORPSZ128rr */ /* Table5511 */ 0xb7c, /* VADDPSZ128rm */ 0xb82, /* VADDPSZ128rr */ /* Table5513 */ 0x1fa5, /* VMULPSZ128rm */ 0x1fab, /* VMULPSZ128rr */ /* Table5515 */ 0xf22, /* VCVTPS2PDZ128rm */ 0xf28, /* VCVTPS2PDZ128rr */ /* Table5517 */ 0xe27, /* VCVTDQ2PSZ128rm */ 0xe2d, /* VCVTDQ2PSZ128rr */ /* Table5519 */ 0x3a3a, /* VSUBPSZ128rm */ 0x3a40, /* VSUBPSZ128rr */ /* Table5521 */ 0x1d02, /* VMINPSZ128rm */ 0x1d08, /* VMINPSZ128rr */ /* Table5523 */ 0x123e, /* VDIVPSZ128rm */ 0x1244, /* VDIVPSZ128rr */ /* Table5525 */ 0x1c57, /* VMAXPSZ128rm */ 0x1c5d, /* VMAXPSZ128rr */ /* Table5527 */ 0x110c, /* VCVTTPS2UDQZ128rm */ 0x1112, /* VCVTTPS2UDQZ128rr */ /* Table5529 */ 0xf76, /* VCVTPS2UDQZ128rm */ 0xf7c, /* VCVTPS2UDQZ128rr */ /* Table5531 */ 0xd86, /* VCMPPSZ128rmi */ 0xd8a, /* VCMPPSZ128rri */ /* Table5533 */ 0x3999, /* VSHUFPSZ128rmi */ 0x399c, /* VSHUFPSZ128rri */ /* Table5535 */ 0x1f11, /* VMOVSSZrm */ 0x1f14, /* VMOVSSZrr */ /* Table5537 */ 0x1f0f, /* VMOVSSZmr */ 0x1f15, /* VMOVSSZrr_REV */ /* Table5539 */ 0x1ef7, /* VMOVSLDUPZ128rm */ 0x1efa, /* VMOVSLDUPZ128rr */ /* Table5541 */ 0x1ee1, /* VMOVSHDUPZ128rm */ 0x1ee4, /* VMOVSHDUPZ128rr */ /* Table5543 */ 0x1016, /* VCVTSI2SSZrm */ 0x1018, /* VCVTSI2SSZrr */ /* Table5545 */ 0x116e, /* VCVTTSS2SIZrm_Int */ 0x1170, /* VCVTTSS2SIZrr_Int */ /* Table5547 */ 0x1045, /* VCVTSS2SIZrm_Int */ 0x1046, /* VCVTSS2SIZrr_Int */ /* Table5549 */ 0x3a07, /* VSQRTSSZm_Int */ 0x3a0b, /* VSQRTSSZr_Int */ /* Table5551 */ 0xbac, /* VADDSSZrm_Int */ 0xbb0, /* VADDSSZrr_Int */ /* Table5553 */ 0x1fd5, /* VMULSSZrm_Int */ 0x1fd9, /* VMULSSZrr_Int */ /* Table5555 */ 0x1032, /* VCVTSS2SDZrm_Int */ 0x1036, /* VCVTSS2SDZrr_Int */ /* Table5557 */ 0x10ce, /* VCVTTPS2DQZ128rm */ 0x10d4, /* VCVTTPS2DQZ128rr */ /* Table5559 */ 0x3a6a, /* VSUBSSZrm_Int */ 0x3a6e, /* VSUBSSZrr_Int */ /* Table5561 */ 0x1d32, /* VMINSSZrm_Int */ 0x1d36, /* VMINSSZrr_Int */ /* Table5563 */ 0x126e, /* VDIVSSZrm_Int */ 0x1272, /* VDIVSSZrr_Int */ /* Table5565 */ 0x1c87, /* VMAXSSZrm_Int */ 0x1c8b, /* VMAXSSZrr_Int */ /* Table5567 */ 0x1e29, /* VMOVDQU32Z128rm */ 0x1e2c, /* VMOVDQU32Z128rr */ /* Table5569 */ 0x3187, /* VPSHUFHWZ128mi */ 0x318a, /* VPSHUFHWZ128ri */ /* Table5571 */ 0x117c, /* VCVTTSS2USIZrm_Int */ 0x117e, /* VCVTTSS2USIZrr_Int */ /* Table5573 */ 0x104d, /* VCVTSS2USIZrm_Int */ 0x104e, /* VCVTSS2USIZrr_Int */ /* Table5575 */ 0x1180, /* VCVTUDQ2PDZ128rm */ 0x1186, /* VCVTUDQ2PDZ128rr */ /* Table5577 */ 0x11f9, /* VCVTUSI2SSZrm */ 0x11fb, /* VCVTUSI2SSZrr */ /* Table5579 */ 0x1e27, /* VMOVDQU32Z128mr */ 0x1e2d, /* VMOVDQU32Z128rr_REV */ /* Table5581 */ 0xdc3, /* VCMPSSZrm_Int */ 0xdc8, /* VCMPSSZrr_Int */ /* Table5583 */ 0xe08, /* VCVTDQ2PDZ128rm */ 0xe0e, /* VCVTDQ2PDZ128rr */ /* Table5585 */ 0x100d, /* VCVTSI2SDZrm */ 0x100f, /* VCVTSI2SDZrr */ /* Table5587 */ 0x1152, /* VCVTTSD2SIZrm_Int */ 0x1154, /* VCVTTSD2SIZrr_Int */ /* Table5589 */ 0xff3, /* VCVTSD2SIZrm_Int */ 0xff4, /* VCVTSD2SIZrr_Int */ /* Table5591 */ 0x1e6b, /* VMOVDQU8Z128rm */ 0x1e6e, /* VMOVDQU8Z128rr */ /* Table5593 */ 0x319d, /* VPSHUFLWZ128mi */ 0x31a0, /* VPSHUFLWZ128ri */ /* Table5595 */ 0x1160, /* VCVTTSD2USIZrm_Int */ 0x1162, /* VCVTTSD2USIZrr_Int */ /* Table5597 */ 0x100a, /* VCVTSD2USIZrm_Int */ 0x100b, /* VCVTSD2USIZrr_Int */ /* Table5599 */ 0x119b, /* VCVTUDQ2PSZ128rm */ 0x11a1, /* VCVTUDQ2PSZ128rr */ /* Table5601 */ 0x11f5, /* VCVTUSI2SDZrm */ 0x11f7, /* VCVTUSI2SDZrr */ /* Table5603 */ 0x1e69, /* VMOVDQU8Z128mr */ 0x1e6f, /* VMOVDQU8Z128rr_REV */ /* Table5605 */ 0xf00, /* VCVTPS2DQZ128rm */ 0xf06, /* VCVTPS2DQZ128rr */ /* Table5607 */ 0x3643, /* VPUNPCKLBWZ128rm */ 0x3646, /* VPUNPCKLBWZ128rr */ /* Table5609 */ 0x3697, /* VPUNPCKLWDZ128rm */ 0x369a, /* VPUNPCKLWDZ128rr */ /* Table5611 */ 0x3659, /* VPUNPCKLDQZ128rm */ 0x365f, /* VPUNPCKLDQZ128rr */ /* Table5613 */ 0x20b4, /* VPACKSSWBZ128rm */ 0x20b7, /* VPACKSSWBZ128rr */ /* Table5615 */ 0x23fd, /* VPCMPGTBZ128rm */ 0x23ff, /* VPCMPGTBZ128rr */ /* Table5617 */ 0x2439, /* VPCMPGTWZ128rm */ 0x243b, /* VPCMPGTWZ128rr */ /* Table5619 */ 0x240d, /* VPCMPGTDZ128rm */ 0x2411, /* VPCMPGTDZ128rr */ /* Table5621 */ 0x20e9, /* VPACKUSWBZ128rm */ 0x20ec, /* VPACKUSWBZ128rr */ /* Table5623 */ 0x35d9, /* VPUNPCKHBWZ128rm */ 0x35dc, /* VPUNPCKHBWZ128rr */ /* Table5625 */ 0x362d, /* VPUNPCKHWDZ128rm */ 0x3630, /* VPUNPCKHWDZ128rr */ /* Table5627 */ 0x35ef, /* VPUNPCKHDQZ128rm */ 0x35f5, /* VPUNPCKHDQZ128rr */ /* Table5629 */ 0x2095, /* VPACKSSDWZ128rm */ 0x209b, /* VPACKSSDWZ128rr */ /* Table5631 */ 0x1db4, /* VMOVDI2PDIZrm */ 0x1db5, /* VMOVDI2PDIZrr */ /* Table5633 */ 0x1dbe, /* VMOVDQA32Z128rm */ 0x1dc1, /* VMOVDQA32Z128rr */ /* Table5635 */ 0x316b, /* VPSHUFDZ128mi */ 0x316e, /* VPSHUFDZ128ri */ /* Table5637 */ 0x0, /* */ 0x0, /* */ 0x343c, /* VPSRLWZ128mi */ 0x0, /* */ 0x3354, /* VPSRAWZ128mi */ 0x0, /* */ 0x327e, /* VPSLLWZ128mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x343f, /* VPSRLWZ128ri */ 0x0, /* */ 0x3357, /* VPSRAWZ128ri */ 0x0, /* */ 0x3281, /* VPSLLWZ128ri */ 0x0, /* */ /* Table5653 */ 0x2f6d, /* VPRORDZ128mi */ 0x2f01, /* VPROLDZ128mi */ 0x3389, /* VPSRLDZ128mi */ 0x0, /* */ 0x32ab, /* VPSRADZ128mi */ 0x0, /* */ 0x31cb, /* VPSLLDZ128mi */ 0x0, /* */ 0x2f70, /* VPRORDZ128ri */ 0x2f04, /* VPROLDZ128ri */ 0x338c, /* VPSRLDZ128ri */ 0x0, /* */ 0x32ae, /* VPSRADZ128ri */ 0x0, /* */ 0x31ce, /* VPSLLDZ128ri */ 0x0, /* */ /* Table5669 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x337c, /* VPSRLDQZ128rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31be, /* VPSLLDQZ128rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x337d, /* VPSRLDQZ128rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31bf, /* VPSLLDQZ128rr */ /* Table5685 */ 0x23ad, /* VPCMPEQBZ128rm */ 0x23af, /* VPCMPEQBZ128rr */ /* Table5687 */ 0x23e9, /* VPCMPEQWZ128rm */ 0x23eb, /* VPCMPEQWZ128rr */ /* Table5689 */ 0x23bd, /* VPCMPEQDZ128rm */ 0x23c1, /* VPCMPEQDZ128rr */ /* Table5691 */ 0x112a, /* VCVTTPS2UQQZ128rm */ 0x1130, /* VCVTTPS2UQQZ128rr */ /* Table5693 */ 0xf94, /* VCVTPS2UQQZ128rm */ 0xf9a, /* VCVTPS2UQQZ128rr */ /* Table5695 */ 0x10ee, /* VCVTTPS2QQZ128rm */ 0x10f4, /* VCVTTPS2QQZ128rr */ /* Table5697 */ 0xf58, /* VCVTPS2QQZ128rm */ 0xf5e, /* VCVTPS2QQZ128rr */ /* Table5699 */ 0x1ebe, /* VMOVPDI2DIZmr */ 0x1ebf, /* VMOVPDI2DIZrr */ /* Table5701 */ 0x1dbc, /* VMOVDQA32Z128mr */ 0x1dc2, /* VMOVDQA32Z128rr_REV */ /* Table5703 */ 0x28f7, /* VPINSRWZrm */ 0x28f8, /* VPINSRWZrr */ /* Table5705 */ 0x0, /* */ 0x289a, /* VPEXTRWZrr */ /* Table5707 */ 0x3442, /* VPSRLWZ128rm */ 0x3445, /* VPSRLWZ128rr */ /* Table5709 */ 0x338f, /* VPSRLDZ128rm */ 0x3392, /* VPSRLDZ128rr */ /* Table5711 */ 0x2e18, /* VPMULLWZ128rm */ 0x2e1b, /* VPMULLWZ128rr */ /* Table5713 */ 0x34e5, /* VPSUBUSBZ128rm */ 0x34e8, /* VPSUBUSBZ128rr */ /* Table5715 */ 0x34fb, /* VPSUBUSWZ128rm */ 0x34fe, /* VPSUBUSWZ128rr */ /* Table5717 */ 0x2ae7, /* VPMINUBZ128rm */ 0x2aea, /* VPMINUBZ128rr */ /* Table5719 */ 0x21d5, /* VPANDDZ128rm */ 0x21db, /* VPANDDZ128rr */ /* Table5721 */ 0x217f, /* VPADDUSBZ128rm */ 0x2182, /* VPADDUSBZ128rr */ /* Table5723 */ 0x2195, /* VPADDUSWZ128rm */ 0x2198, /* VPADDUSWZ128rr */ /* Table5725 */ 0x2a1b, /* VPMAXUBZ128rm */ 0x2a1e, /* VPMAXUBZ128rr */ /* Table5727 */ 0x21f0, /* VPANDNDZ128rm */ 0x21f6, /* VPANDNDZ128rr */ /* Table5729 */ 0x224b, /* VPAVGBZ128rm */ 0x224e, /* VPAVGBZ128rr */ /* Table5731 */ 0x335a, /* VPSRAWZ128rm */ 0x335d, /* VPSRAWZ128rr */ /* Table5733 */ 0x32b1, /* VPSRADZ128rm */ 0x32b4, /* VPSRADZ128rr */ /* Table5735 */ 0x2261, /* VPAVGWZ128rm */ 0x2264, /* VPAVGWZ128rr */ /* Table5737 */ 0x2db2, /* VPMULHUWZ128rm */ 0x2db5, /* VPMULHUWZ128rr */ /* Table5739 */ 0x2dc8, /* VPMULHWZ128rm */ 0x2dcb, /* VPMULHWZ128rr */ /* Table5741 */ 0x1eb0, /* VMOVNTDQZ128mr */ 0x0, /* */ /* Table5743 */ 0x34b9, /* VPSUBSBZ128rm */ 0x34bc, /* VPSUBSBZ128rr */ /* Table5745 */ 0x34cf, /* VPSUBSWZ128rm */ 0x34d2, /* VPSUBSWZ128rr */ /* Table5747 */ 0x2ad1, /* VPMINSWZ128rm */ 0x2ad4, /* VPMINSWZ128rr */ /* Table5749 */ 0x2ec0, /* VPORDZ128rm */ 0x2ec6, /* VPORDZ128rr */ /* Table5751 */ 0x2153, /* VPADDSBZ128rm */ 0x2156, /* VPADDSBZ128rr */ /* Table5753 */ 0x2169, /* VPADDSWZ128rm */ 0x216c, /* VPADDSWZ128rr */ /* Table5755 */ 0x2a05, /* VPMAXSWZ128rm */ 0x2a08, /* VPMAXSWZ128rr */ /* Table5757 */ 0x36ab, /* VPXORDZ128rm */ 0x36b1, /* VPXORDZ128rr */ /* Table5759 */ 0x3284, /* VPSLLWZ128rm */ 0x3287, /* VPSLLWZ128rr */ /* Table5761 */ 0x31d1, /* VPSLLDZ128rm */ 0x31d4, /* VPSLLDZ128rr */ /* Table5763 */ 0x2997, /* VPMADDWDZ128rm */ 0x299a, /* VPMADDWDZ128rr */ /* Table5765 */ 0x2ff0, /* VPSADBWZ128rm */ 0x2ff1, /* VPSADBWZ128rr */ /* Table5767 */ 0x3465, /* VPSUBBZ128rm */ 0x3468, /* VPSUBBZ128rr */ /* Table5769 */ 0x3511, /* VPSUBWZ128rm */ 0x3514, /* VPSUBWZ128rr */ /* Table5771 */ 0x347b, /* VPSUBDZ128rm */ 0x3481, /* VPSUBDZ128rr */ /* Table5773 */ 0x20ff, /* VPADDBZ128rm */ 0x2102, /* VPADDBZ128rr */ /* Table5775 */ 0x21ab, /* VPADDWZ128rm */ 0x21ae, /* VPADDWZ128rr */ /* Table5777 */ 0x2115, /* VPADDDZ128rm */ 0x211b, /* VPADDDZ128rr */ /* Table5779 */ 0xfd0, /* VCVTQQ2PSZ128rm */ 0xfd6, /* VCVTQQ2PSZ128rr */ /* Table5781 */ 0x1090, /* VCVTTPD2UDQZ128rm */ 0x1096, /* VCVTTPD2UDQZ128rr */ /* Table5783 */ 0xea9, /* VCVTPD2UDQZ128rm */ 0xeaf, /* VCVTPD2UDQZ128rr */ /* Table5785 */ 0x1028, /* VCVTSI642SSZrm */ 0x102a, /* VCVTSI642SSZrr */ /* Table5787 */ 0x1165, /* VCVTTSS2SI64Zrm_Int */ 0x1167, /* VCVTTSS2SI64Zrr_Int */ /* Table5789 */ 0x1040, /* VCVTSS2SI64Zrm_Int */ 0x1041, /* VCVTSS2SI64Zrr_Int */ /* Table5791 */ 0x1e4a, /* VMOVDQU64Z128rm */ 0x1e4d, /* VMOVDQU64Z128rr */ /* Table5793 */ 0x1177, /* VCVTTSS2USI64Zrm_Int */ 0x1179, /* VCVTTSS2USI64Zrr_Int */ /* Table5795 */ 0x104a, /* VCVTSS2USI64Zrm_Int */ 0x104b, /* VCVTSS2USI64Zrr_Int */ /* Table5797 */ 0x11b9, /* VCVTUQQ2PDZ128rm */ 0x11bf, /* VCVTUQQ2PDZ128rr */ /* Table5799 */ 0x1203, /* VCVTUSI642SSZrm */ 0x1205, /* VCVTUSI642SSZrr */ /* Table5801 */ 0x1eca, /* VMOVQI2PQIZrm */ 0x1f70, /* VMOVZPQILo2PQIZrr */ /* Table5803 */ 0x1e48, /* VMOVDQU64Z128mr */ 0x1e4e, /* VMOVDQU64Z128rr_REV */ /* Table5805 */ 0xfb2, /* VCVTQQ2PDZ128rm */ 0xfb8, /* VCVTQQ2PDZ128rr */ /* Table5807 */ 0x1ece, /* VMOVSDZrm */ 0x1ed1, /* VMOVSDZrr */ /* Table5809 */ 0x1ecc, /* VMOVSDZmr */ 0x1ed2, /* VMOVSDZrr_REV */ /* Table5811 */ 0x1da0, /* VMOVDDUPZ128rm */ 0x1da3, /* VMOVDDUPZ128rr */ /* Table5813 */ 0x101f, /* VCVTSI642SDZrm */ 0x1021, /* VCVTSI642SDZrr */ /* Table5815 */ 0x1149, /* VCVTTSD2SI64Zrm_Int */ 0x114b, /* VCVTTSD2SI64Zrr_Int */ /* Table5817 */ 0xfee, /* VCVTSD2SI64Zrm_Int */ 0xfef, /* VCVTSD2SI64Zrr_Int */ /* Table5819 */ 0x39f8, /* VSQRTSDZm_Int */ 0x39fc, /* VSQRTSDZr_Int */ /* Table5821 */ 0xb9d, /* VADDSDZrm_Int */ 0xba1, /* VADDSDZrr_Int */ /* Table5823 */ 0x1fc6, /* VMULSDZrm_Int */ 0x1fca, /* VMULSDZrr_Int */ /* Table5825 */ 0xff9, /* VCVTSD2SSZrm_Int */ 0xffd, /* VCVTSD2SSZrr_Int */ /* Table5827 */ 0x3a5b, /* VSUBSDZrm_Int */ 0x3a5f, /* VSUBSDZrr_Int */ /* Table5829 */ 0x1d23, /* VMINSDZrm_Int */ 0x1d27, /* VMINSDZrr_Int */ /* Table5831 */ 0x125f, /* VDIVSDZrm_Int */ 0x1263, /* VDIVSDZrr_Int */ /* Table5833 */ 0x1c78, /* VMAXSDZrm_Int */ 0x1c7c, /* VMAXSDZrr_Int */ /* Table5835 */ 0x1e08, /* VMOVDQU16Z128rm */ 0x1e0b, /* VMOVDQU16Z128rr */ /* Table5837 */ 0x115b, /* VCVTTSD2USI64Zrm_Int */ 0x115d, /* VCVTTSD2USI64Zrr_Int */ /* Table5839 */ 0x1007, /* VCVTSD2USI64Zrm_Int */ 0x1008, /* VCVTSD2USI64Zrr_Int */ /* Table5841 */ 0x11d7, /* VCVTUQQ2PSZ128rm */ 0x11dd, /* VCVTUQQ2PSZ128rr */ /* Table5843 */ 0x11fe, /* VCVTUSI642SDZrm */ 0x1200, /* VCVTUSI642SDZrr */ /* Table5845 */ 0x1e06, /* VMOVDQU16Z128mr */ 0x1e0c, /* VMOVDQU16Z128rr_REV */ /* Table5847 */ 0xdaf, /* VCMPSDZrm_Int */ 0xdb4, /* VCMPSDZrr_Int */ /* Table5849 */ 0xe49, /* VCVTPD2DQZ128rm */ 0xe4f, /* VCVTPD2DQZ128rr */ /* Table5851 */ 0x1f24, /* VMOVUPDZ128rm */ 0x1f27, /* VMOVUPDZ128rr */ /* Table5853 */ 0x1f22, /* VMOVUPDZ128mr */ 0x1f28, /* VMOVUPDZ128rr_REV */ /* Table5855 */ 0x1e9f, /* VMOVLPDZ128rm */ 0x0, /* */ /* Table5857 */ 0x1e9e, /* VMOVLPDZ128mr */ 0x0, /* */ /* Table5859 */ 0x3ad2, /* VUNPCKLPDZ128rm */ 0x3ad8, /* VUNPCKLPDZ128rr */ /* Table5861 */ 0x3a94, /* VUNPCKHPDZ128rm */ 0x3a9a, /* VUNPCKHPDZ128rr */ /* Table5863 */ 0x1e95, /* VMOVHPDZ128rm */ 0x0, /* */ /* Table5865 */ 0x1e94, /* VMOVHPDZ128mr */ 0x0, /* */ /* Table5867 */ 0x1d52, /* VMOVAPDZ128rm */ 0x1d55, /* VMOVAPDZ128rr */ /* Table5869 */ 0x1d50, /* VMOVAPDZ128mr */ 0x1d56, /* VMOVAPDZ128rr_REV */ /* Table5871 */ 0x1eb5, /* VMOVNTPDZ128mr */ 0x0, /* */ /* Table5873 */ 0x3a80, /* VUCOMISDZrm */ 0x3a82, /* VUCOMISDZrr */ /* Table5875 */ 0xdd6, /* VCOMISDZrm */ 0xdd8, /* VCOMISDZrr */ /* Table5877 */ 0x39b5, /* VSQRTPDZ128m */ 0x39bb, /* VSQRTPDZ128r */ /* Table5879 */ 0xc64, /* VANDPDZ128rm */ 0xc6a, /* VANDPDZ128rr */ /* Table5881 */ 0xc26, /* VANDNPDZ128rm */ 0xc2c, /* VANDNPDZ128rr */ /* Table5883 */ 0x1feb, /* VORPDZ128rm */ 0x1ff1, /* VORPDZ128rr */ /* Table5885 */ 0x3b10, /* VXORPDZ128rm */ 0x3b16, /* VXORPDZ128rr */ /* Table5887 */ 0xb5a, /* VADDPDZ128rm */ 0xb60, /* VADDPDZ128rr */ /* Table5889 */ 0x1f83, /* VMULPDZ128rm */ 0x1f89, /* VMULPDZ128rr */ /* Table5891 */ 0xe6b, /* VCVTPD2PSZ128rm */ 0xe71, /* VCVTPD2PSZ128rr */ /* Table5893 */ 0x3a18, /* VSUBPDZ128rm */ 0x3a1e, /* VSUBPDZ128rr */ /* Table5895 */ 0x1ce0, /* VMINPDZ128rm */ 0x1ce6, /* VMINPDZ128rr */ /* Table5897 */ 0x121c, /* VDIVPDZ128rm */ 0x1222, /* VDIVPDZ128rr */ /* Table5899 */ 0x1c35, /* VMAXPDZ128rm */ 0x1c3b, /* VMAXPDZ128rr */ /* Table5901 */ 0x3678, /* VPUNPCKLQDQZ128rm */ 0x367e, /* VPUNPCKLQDQZ128rr */ /* Table5903 */ 0x360e, /* VPUNPCKHQDQZ128rm */ 0x3614, /* VPUNPCKHQDQZ128rr */ /* Table5905 */ 0x1d44, /* VMOV64toPQIZrm */ 0x1d45, /* VMOV64toPQIZrr */ /* Table5907 */ 0x1ddf, /* VMOVDQA64Z128rm */ 0x1de2, /* VMOVDQA64Z128rr */ /* Table5909 */ 0x2f88, /* VPRORQZ128mi */ 0x2f1c, /* VPROLQZ128mi */ 0x0, /* */ 0x0, /* */ 0x32db, /* VPSRAQZ128mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f8b, /* VPRORQZ128ri */ 0x2f1f, /* VPROLQZ128ri */ 0x0, /* */ 0x0, /* */ 0x32de, /* VPSRAQZ128ri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table5925 */ 0x0, /* */ 0x0, /* */ 0x33bc, /* VPSRLQZ128mi */ 0x337c, /* VPSRLDQZ128rm */ 0x0, /* */ 0x0, /* */ 0x31fe, /* VPSLLQZ128mi */ 0x31be, /* VPSLLDQZ128rm */ 0x0, /* */ 0x0, /* */ 0x33bf, /* VPSRLQZ128ri */ 0x337d, /* VPSRLDQZ128rr */ 0x0, /* */ 0x0, /* */ 0x3201, /* VPSLLQZ128ri */ 0x31bf, /* VPSLLDQZ128rr */ /* Table5941 */ 0x10ae, /* VCVTTPD2UQQZ128rm */ 0x10b4, /* VCVTTPD2UQQZ128rr */ /* Table5943 */ 0xec7, /* VCVTPD2UQQZ128rm */ 0xecd, /* VCVTPD2UQQZ128rr */ /* Table5945 */ 0x1072, /* VCVTTPD2QQZ128rm */ 0x1078, /* VCVTTPD2QQZ128rr */ /* Table5947 */ 0xe8b, /* VCVTPD2QQZ128rm */ 0xe91, /* VCVTPD2QQZ128rr */ /* Table5949 */ 0x1ec6, /* VMOVPQIto64Zmr */ 0x1ec7, /* VMOVPQIto64Zrr */ /* Table5951 */ 0x1ddd, /* VMOVDQA64Z128mr */ 0x1de3, /* VMOVDQA64Z128rr_REV */ /* Table5953 */ 0xd56, /* VCMPPDZ128rmi */ 0xd5a, /* VCMPPDZ128rri */ /* Table5955 */ 0x397a, /* VSHUFPDZ128rmi */ 0x397d, /* VSHUFPDZ128rri */ /* Table5957 */ 0x33c2, /* VPSRLQZ128rm */ 0x33c5, /* VPSRLQZ128rr */ /* Table5959 */ 0x2134, /* VPADDQZ128rm */ 0x213a, /* VPADDQZ128rr */ /* Table5961 */ 0x1ec2, /* VMOVPQI2QIZmr */ 0x1ec3, /* VMOVPQI2QIZrr */ /* Table5963 */ 0x222a, /* VPANDQZ128rm */ 0x2230, /* VPANDQZ128rr */ /* Table5965 */ 0x220b, /* VPANDNQZ128rm */ 0x2211, /* VPANDNQZ128rr */ /* Table5967 */ 0x32e1, /* VPSRAQZ128rm */ 0x32e4, /* VPSRAQZ128rr */ /* Table5969 */ 0x1052, /* VCVTTPD2DQZ128rm */ 0x1058, /* VCVTTPD2DQZ128rr */ /* Table5971 */ 0x2edb, /* VPORQZ128rm */ 0x2ee1, /* VPORQZ128rr */ /* Table5973 */ 0x36c6, /* VPXORQZ128rm */ 0x36cc, /* VPXORQZ128rr */ /* Table5975 */ 0x3204, /* VPSLLQZ128rm */ 0x3207, /* VPSLLQZ128rr */ /* Table5977 */ 0x2e49, /* VPMULUDQZ128rm */ 0x2e4f, /* VPMULUDQZ128rr */ /* Table5979 */ 0x349a, /* VPSUBQZ128rm */ 0x34a0, /* VPSUBQZ128rr */ /* Table5981 */ 0x1f58, /* VMOVUPSZ256rm */ 0x1f5b, /* VMOVUPSZ256rr */ /* Table5983 */ 0x1f56, /* VMOVUPSZ256mr */ 0x1f5c, /* VMOVUPSZ256rr_REV */ /* Table5985 */ 0x3afa, /* VUNPCKLPSZ256rm */ 0x3b00, /* VUNPCKLPSZ256rr */ /* Table5987 */ 0x3abc, /* VUNPCKHPSZ256rm */ 0x3ac2, /* VUNPCKHPSZ256rr */ /* Table5989 */ 0x1d86, /* VMOVAPSZ256rm */ 0x1d89, /* VMOVAPSZ256rr */ /* Table5991 */ 0x1d84, /* VMOVAPSZ256mr */ 0x1d8a, /* VMOVAPSZ256rr_REV */ /* Table5993 */ 0x1ebb, /* VMOVNTPSZ256mr */ 0x0, /* */ /* Table5995 */ 0x39e0, /* VSQRTPSZ256m */ 0x39e6, /* VSQRTPSZ256r */ /* Table5997 */ 0xc8c, /* VANDPSZ256rm */ 0xc92, /* VANDPSZ256rr */ /* Table5999 */ 0xc4e, /* VANDNPSZ256rm */ 0xc54, /* VANDNPSZ256rr */ /* Table6001 */ 0x2013, /* VORPSZ256rm */ 0x2019, /* VORPSZ256rr */ /* Table6003 */ 0x3b38, /* VXORPSZ256rm */ 0x3b3e, /* VXORPSZ256rr */ /* Table6005 */ 0xb85, /* VADDPSZ256rm */ 0xb8b, /* VADDPSZ256rr */ /* Table6007 */ 0x1fae, /* VMULPSZ256rm */ 0x1fb4, /* VMULPSZ256rr */ /* Table6009 */ 0xf2b, /* VCVTPS2PDZ256rm */ 0xf31, /* VCVTPS2PDZ256rr */ /* Table6011 */ 0xe30, /* VCVTDQ2PSZ256rm */ 0xe36, /* VCVTDQ2PSZ256rr */ /* Table6013 */ 0x3a43, /* VSUBPSZ256rm */ 0x3a49, /* VSUBPSZ256rr */ /* Table6015 */ 0x1d0b, /* VMINPSZ256rm */ 0x1d11, /* VMINPSZ256rr */ /* Table6017 */ 0x1247, /* VDIVPSZ256rm */ 0x124d, /* VDIVPSZ256rr */ /* Table6019 */ 0x1c60, /* VMAXPSZ256rm */ 0x1c66, /* VMAXPSZ256rr */ /* Table6021 */ 0x1115, /* VCVTTPS2UDQZ256rm */ 0x111b, /* VCVTTPS2UDQZ256rr */ /* Table6023 */ 0xf7f, /* VCVTPS2UDQZ256rm */ 0xf85, /* VCVTPS2UDQZ256rr */ /* Table6025 */ 0xd92, /* VCMPPSZ256rmi */ 0xd96, /* VCMPPSZ256rri */ /* Table6027 */ 0x39a2, /* VSHUFPSZ256rmi */ 0x39a5, /* VSHUFPSZ256rri */ /* Table6029 */ 0x1efd, /* VMOVSLDUPZ256rm */ 0x1f00, /* VMOVSLDUPZ256rr */ /* Table6031 */ 0x1ee7, /* VMOVSHDUPZ256rm */ 0x1eea, /* VMOVSHDUPZ256rr */ /* Table6033 */ 0x10d7, /* VCVTTPS2DQZ256rm */ 0x10dd, /* VCVTTPS2DQZ256rr */ /* Table6035 */ 0x1e34, /* VMOVDQU32Z256rm */ 0x1e37, /* VMOVDQU32Z256rr */ /* Table6037 */ 0x318d, /* VPSHUFHWZ256mi */ 0x3190, /* VPSHUFHWZ256ri */ /* Table6039 */ 0x1189, /* VCVTUDQ2PDZ256rm */ 0x118f, /* VCVTUDQ2PDZ256rr */ /* Table6041 */ 0x1e32, /* VMOVDQU32Z256mr */ 0x1e38, /* VMOVDQU32Z256rr_REV */ /* Table6043 */ 0xe11, /* VCVTDQ2PDZ256rm */ 0xe17, /* VCVTDQ2PDZ256rr */ /* Table6045 */ 0x1e76, /* VMOVDQU8Z256rm */ 0x1e79, /* VMOVDQU8Z256rr */ /* Table6047 */ 0x31a3, /* VPSHUFLWZ256mi */ 0x31a6, /* VPSHUFLWZ256ri */ /* Table6049 */ 0x11a4, /* VCVTUDQ2PSZ256rm */ 0x11aa, /* VCVTUDQ2PSZ256rr */ /* Table6051 */ 0x1e74, /* VMOVDQU8Z256mr */ 0x1e7a, /* VMOVDQU8Z256rr_REV */ /* Table6053 */ 0xf09, /* VCVTPS2DQZ256rm */ 0xf0f, /* VCVTPS2DQZ256rr */ /* Table6055 */ 0x3649, /* VPUNPCKLBWZ256rm */ 0x364c, /* VPUNPCKLBWZ256rr */ /* Table6057 */ 0x369d, /* VPUNPCKLWDZ256rm */ 0x36a0, /* VPUNPCKLWDZ256rr */ /* Table6059 */ 0x3662, /* VPUNPCKLDQZ256rm */ 0x3668, /* VPUNPCKLDQZ256rr */ /* Table6061 */ 0x20ba, /* VPACKSSWBZ256rm */ 0x20bd, /* VPACKSSWBZ256rr */ /* Table6063 */ 0x2401, /* VPCMPGTBZ256rm */ 0x2403, /* VPCMPGTBZ256rr */ /* Table6065 */ 0x243d, /* VPCMPGTWZ256rm */ 0x243f, /* VPCMPGTWZ256rr */ /* Table6067 */ 0x2413, /* VPCMPGTDZ256rm */ 0x2417, /* VPCMPGTDZ256rr */ /* Table6069 */ 0x20ef, /* VPACKUSWBZ256rm */ 0x20f2, /* VPACKUSWBZ256rr */ /* Table6071 */ 0x35df, /* VPUNPCKHBWZ256rm */ 0x35e2, /* VPUNPCKHBWZ256rr */ /* Table6073 */ 0x3633, /* VPUNPCKHWDZ256rm */ 0x3636, /* VPUNPCKHWDZ256rr */ /* Table6075 */ 0x35f8, /* VPUNPCKHDQZ256rm */ 0x35fe, /* VPUNPCKHDQZ256rr */ /* Table6077 */ 0x209e, /* VPACKSSDWZ256rm */ 0x20a4, /* VPACKSSDWZ256rr */ /* Table6079 */ 0x1dc9, /* VMOVDQA32Z256rm */ 0x1dcc, /* VMOVDQA32Z256rr */ /* Table6081 */ 0x3174, /* VPSHUFDZ256mi */ 0x3177, /* VPSHUFDZ256ri */ /* Table6083 */ 0x0, /* */ 0x0, /* */ 0x3448, /* VPSRLWZ256mi */ 0x0, /* */ 0x3360, /* VPSRAWZ256mi */ 0x0, /* */ 0x328a, /* VPSLLWZ256mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x344b, /* VPSRLWZ256ri */ 0x0, /* */ 0x3363, /* VPSRAWZ256ri */ 0x0, /* */ 0x328d, /* VPSLLWZ256ri */ 0x0, /* */ /* Table6099 */ 0x2f76, /* VPRORDZ256mi */ 0x2f0a, /* VPROLDZ256mi */ 0x3398, /* VPSRLDZ256mi */ 0x0, /* */ 0x32ba, /* VPSRADZ256mi */ 0x0, /* */ 0x31da, /* VPSLLDZ256mi */ 0x0, /* */ 0x2f79, /* VPRORDZ256ri */ 0x2f0d, /* VPROLDZ256ri */ 0x339b, /* VPSRLDZ256ri */ 0x0, /* */ 0x32bd, /* VPSRADZ256ri */ 0x0, /* */ 0x31dd, /* VPSLLDZ256ri */ 0x0, /* */ /* Table6115 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x337e, /* VPSRLDQZ256rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31c0, /* VPSLLDQZ256rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x337f, /* VPSRLDQZ256rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31c1, /* VPSLLDQZ256rr */ /* Table6131 */ 0x23b1, /* VPCMPEQBZ256rm */ 0x23b3, /* VPCMPEQBZ256rr */ /* Table6133 */ 0x23ed, /* VPCMPEQWZ256rm */ 0x23ef, /* VPCMPEQWZ256rr */ /* Table6135 */ 0x23c3, /* VPCMPEQDZ256rm */ 0x23c7, /* VPCMPEQDZ256rr */ /* Table6137 */ 0x1133, /* VCVTTPS2UQQZ256rm */ 0x1139, /* VCVTTPS2UQQZ256rr */ /* Table6139 */ 0xf9d, /* VCVTPS2UQQZ256rm */ 0xfa3, /* VCVTPS2UQQZ256rr */ /* Table6141 */ 0x10f7, /* VCVTTPS2QQZ256rm */ 0x10fd, /* VCVTTPS2QQZ256rr */ /* Table6143 */ 0xf61, /* VCVTPS2QQZ256rm */ 0xf67, /* VCVTPS2QQZ256rr */ /* Table6145 */ 0x1dc7, /* VMOVDQA32Z256mr */ 0x1dcd, /* VMOVDQA32Z256rr_REV */ /* Table6147 */ 0x344e, /* VPSRLWZ256rm */ 0x3451, /* VPSRLWZ256rr */ /* Table6149 */ 0x339e, /* VPSRLDZ256rm */ 0x33a1, /* VPSRLDZ256rr */ /* Table6151 */ 0x2e1e, /* VPMULLWZ256rm */ 0x2e21, /* VPMULLWZ256rr */ /* Table6153 */ 0x34eb, /* VPSUBUSBZ256rm */ 0x34ee, /* VPSUBUSBZ256rr */ /* Table6155 */ 0x3501, /* VPSUBUSWZ256rm */ 0x3504, /* VPSUBUSWZ256rr */ /* Table6157 */ 0x2aed, /* VPMINUBZ256rm */ 0x2af0, /* VPMINUBZ256rr */ /* Table6159 */ 0x21de, /* VPANDDZ256rm */ 0x21e4, /* VPANDDZ256rr */ /* Table6161 */ 0x2185, /* VPADDUSBZ256rm */ 0x2188, /* VPADDUSBZ256rr */ /* Table6163 */ 0x219b, /* VPADDUSWZ256rm */ 0x219e, /* VPADDUSWZ256rr */ /* Table6165 */ 0x2a21, /* VPMAXUBZ256rm */ 0x2a24, /* VPMAXUBZ256rr */ /* Table6167 */ 0x21f9, /* VPANDNDZ256rm */ 0x21ff, /* VPANDNDZ256rr */ /* Table6169 */ 0x2251, /* VPAVGBZ256rm */ 0x2254, /* VPAVGBZ256rr */ /* Table6171 */ 0x3366, /* VPSRAWZ256rm */ 0x3369, /* VPSRAWZ256rr */ /* Table6173 */ 0x32c0, /* VPSRADZ256rm */ 0x32c3, /* VPSRADZ256rr */ /* Table6175 */ 0x2267, /* VPAVGWZ256rm */ 0x226a, /* VPAVGWZ256rr */ /* Table6177 */ 0x2db8, /* VPMULHUWZ256rm */ 0x2dbb, /* VPMULHUWZ256rr */ /* Table6179 */ 0x2dce, /* VPMULHWZ256rm */ 0x2dd1, /* VPMULHWZ256rr */ /* Table6181 */ 0x1eb1, /* VMOVNTDQZ256mr */ 0x0, /* */ /* Table6183 */ 0x34bf, /* VPSUBSBZ256rm */ 0x34c2, /* VPSUBSBZ256rr */ /* Table6185 */ 0x34d5, /* VPSUBSWZ256rm */ 0x34d8, /* VPSUBSWZ256rr */ /* Table6187 */ 0x2ad7, /* VPMINSWZ256rm */ 0x2ada, /* VPMINSWZ256rr */ /* Table6189 */ 0x2ec9, /* VPORDZ256rm */ 0x2ecf, /* VPORDZ256rr */ /* Table6191 */ 0x2159, /* VPADDSBZ256rm */ 0x215c, /* VPADDSBZ256rr */ /* Table6193 */ 0x216f, /* VPADDSWZ256rm */ 0x2172, /* VPADDSWZ256rr */ /* Table6195 */ 0x2a0b, /* VPMAXSWZ256rm */ 0x2a0e, /* VPMAXSWZ256rr */ /* Table6197 */ 0x36b4, /* VPXORDZ256rm */ 0x36ba, /* VPXORDZ256rr */ /* Table6199 */ 0x3290, /* VPSLLWZ256rm */ 0x3293, /* VPSLLWZ256rr */ /* Table6201 */ 0x31e0, /* VPSLLDZ256rm */ 0x31e3, /* VPSLLDZ256rr */ /* Table6203 */ 0x299d, /* VPMADDWDZ256rm */ 0x29a0, /* VPMADDWDZ256rr */ /* Table6205 */ 0x2ff2, /* VPSADBWZ256rm */ 0x2ff3, /* VPSADBWZ256rr */ /* Table6207 */ 0x346b, /* VPSUBBZ256rm */ 0x346e, /* VPSUBBZ256rr */ /* Table6209 */ 0x3517, /* VPSUBWZ256rm */ 0x351a, /* VPSUBWZ256rr */ /* Table6211 */ 0x3484, /* VPSUBDZ256rm */ 0x348a, /* VPSUBDZ256rr */ /* Table6213 */ 0x2105, /* VPADDBZ256rm */ 0x2108, /* VPADDBZ256rr */ /* Table6215 */ 0x21b1, /* VPADDWZ256rm */ 0x21b4, /* VPADDWZ256rr */ /* Table6217 */ 0x211e, /* VPADDDZ256rm */ 0x2124, /* VPADDDZ256rr */ /* Table6219 */ 0xfd9, /* VCVTQQ2PSZ256rm */ 0xfdf, /* VCVTQQ2PSZ256rr */ /* Table6221 */ 0x1099, /* VCVTTPD2UDQZ256rm */ 0x109f, /* VCVTTPD2UDQZ256rr */ /* Table6223 */ 0xeb2, /* VCVTPD2UDQZ256rm */ 0xeb8, /* VCVTPD2UDQZ256rr */ /* Table6225 */ 0x1e55, /* VMOVDQU64Z256rm */ 0x1e58, /* VMOVDQU64Z256rr */ /* Table6227 */ 0x11c2, /* VCVTUQQ2PDZ256rm */ 0x11c8, /* VCVTUQQ2PDZ256rr */ /* Table6229 */ 0x1e53, /* VMOVDQU64Z256mr */ 0x1e59, /* VMOVDQU64Z256rr_REV */ /* Table6231 */ 0xfbb, /* VCVTQQ2PDZ256rm */ 0xfc1, /* VCVTQQ2PDZ256rr */ /* Table6233 */ 0x1da6, /* VMOVDDUPZ256rm */ 0x1da9, /* VMOVDDUPZ256rr */ /* Table6235 */ 0x1e13, /* VMOVDQU16Z256rm */ 0x1e16, /* VMOVDQU16Z256rr */ /* Table6237 */ 0x11e0, /* VCVTUQQ2PSZ256rm */ 0x11e6, /* VCVTUQQ2PSZ256rr */ /* Table6239 */ 0x1e11, /* VMOVDQU16Z256mr */ 0x1e17, /* VMOVDQU16Z256rr_REV */ /* Table6241 */ 0xe52, /* VCVTPD2DQZ256rm */ 0xe58, /* VCVTPD2DQZ256rr */ /* Table6243 */ 0x1f2f, /* VMOVUPDZ256rm */ 0x1f32, /* VMOVUPDZ256rr */ /* Table6245 */ 0x1f2d, /* VMOVUPDZ256mr */ 0x1f33, /* VMOVUPDZ256rr_REV */ /* Table6247 */ 0x3adb, /* VUNPCKLPDZ256rm */ 0x3ae1, /* VUNPCKLPDZ256rr */ /* Table6249 */ 0x3a9d, /* VUNPCKHPDZ256rm */ 0x3aa3, /* VUNPCKHPDZ256rr */ /* Table6251 */ 0x1d5d, /* VMOVAPDZ256rm */ 0x1d60, /* VMOVAPDZ256rr */ /* Table6253 */ 0x1d5b, /* VMOVAPDZ256mr */ 0x1d61, /* VMOVAPDZ256rr_REV */ /* Table6255 */ 0x1eb6, /* VMOVNTPDZ256mr */ 0x0, /* */ /* Table6257 */ 0x39be, /* VSQRTPDZ256m */ 0x39c4, /* VSQRTPDZ256r */ /* Table6259 */ 0xc6d, /* VANDPDZ256rm */ 0xc73, /* VANDPDZ256rr */ /* Table6261 */ 0xc2f, /* VANDNPDZ256rm */ 0xc35, /* VANDNPDZ256rr */ /* Table6263 */ 0x1ff4, /* VORPDZ256rm */ 0x1ffa, /* VORPDZ256rr */ /* Table6265 */ 0x3b19, /* VXORPDZ256rm */ 0x3b1f, /* VXORPDZ256rr */ /* Table6267 */ 0xb63, /* VADDPDZ256rm */ 0xb69, /* VADDPDZ256rr */ /* Table6269 */ 0x1f8c, /* VMULPDZ256rm */ 0x1f92, /* VMULPDZ256rr */ /* Table6271 */ 0xe74, /* VCVTPD2PSZ256rm */ 0xe7a, /* VCVTPD2PSZ256rr */ /* Table6273 */ 0x3a21, /* VSUBPDZ256rm */ 0x3a27, /* VSUBPDZ256rr */ /* Table6275 */ 0x1ce9, /* VMINPDZ256rm */ 0x1cef, /* VMINPDZ256rr */ /* Table6277 */ 0x1225, /* VDIVPDZ256rm */ 0x122b, /* VDIVPDZ256rr */ /* Table6279 */ 0x1c3e, /* VMAXPDZ256rm */ 0x1c44, /* VMAXPDZ256rr */ /* Table6281 */ 0x3681, /* VPUNPCKLQDQZ256rm */ 0x3687, /* VPUNPCKLQDQZ256rr */ /* Table6283 */ 0x3617, /* VPUNPCKHQDQZ256rm */ 0x361d, /* VPUNPCKHQDQZ256rr */ /* Table6285 */ 0x1dea, /* VMOVDQA64Z256rm */ 0x1ded, /* VMOVDQA64Z256rr */ /* Table6287 */ 0x2f91, /* VPRORQZ256mi */ 0x2f25, /* VPROLQZ256mi */ 0x0, /* */ 0x0, /* */ 0x32ea, /* VPSRAQZ256mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f94, /* VPRORQZ256ri */ 0x2f28, /* VPROLQZ256ri */ 0x0, /* */ 0x0, /* */ 0x32ed, /* VPSRAQZ256ri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table6303 */ 0x0, /* */ 0x0, /* */ 0x33cb, /* VPSRLQZ256mi */ 0x337e, /* VPSRLDQZ256rm */ 0x0, /* */ 0x0, /* */ 0x320d, /* VPSLLQZ256mi */ 0x31c0, /* VPSLLDQZ256rm */ 0x0, /* */ 0x0, /* */ 0x33ce, /* VPSRLQZ256ri */ 0x337f, /* VPSRLDQZ256rr */ 0x0, /* */ 0x0, /* */ 0x3210, /* VPSLLQZ256ri */ 0x31c1, /* VPSLLDQZ256rr */ /* Table6319 */ 0x10b7, /* VCVTTPD2UQQZ256rm */ 0x10bd, /* VCVTTPD2UQQZ256rr */ /* Table6321 */ 0xed0, /* VCVTPD2UQQZ256rm */ 0xed6, /* VCVTPD2UQQZ256rr */ /* Table6323 */ 0x107b, /* VCVTTPD2QQZ256rm */ 0x1081, /* VCVTTPD2QQZ256rr */ /* Table6325 */ 0xe94, /* VCVTPD2QQZ256rm */ 0xe9a, /* VCVTPD2QQZ256rr */ /* Table6327 */ 0x1de8, /* VMOVDQA64Z256mr */ 0x1dee, /* VMOVDQA64Z256rr_REV */ /* Table6329 */ 0xd62, /* VCMPPDZ256rmi */ 0xd66, /* VCMPPDZ256rri */ /* Table6331 */ 0x3983, /* VSHUFPDZ256rmi */ 0x3986, /* VSHUFPDZ256rri */ /* Table6333 */ 0x33d1, /* VPSRLQZ256rm */ 0x33d4, /* VPSRLQZ256rr */ /* Table6335 */ 0x213d, /* VPADDQZ256rm */ 0x2143, /* VPADDQZ256rr */ /* Table6337 */ 0x2233, /* VPANDQZ256rm */ 0x2239, /* VPANDQZ256rr */ /* Table6339 */ 0x2214, /* VPANDNQZ256rm */ 0x221a, /* VPANDNQZ256rr */ /* Table6341 */ 0x32f0, /* VPSRAQZ256rm */ 0x32f3, /* VPSRAQZ256rr */ /* Table6343 */ 0x105b, /* VCVTTPD2DQZ256rm */ 0x1061, /* VCVTTPD2DQZ256rr */ /* Table6345 */ 0x2ee4, /* VPORQZ256rm */ 0x2eea, /* VPORQZ256rr */ /* Table6347 */ 0x36cf, /* VPXORQZ256rm */ 0x36d5, /* VPXORQZ256rr */ /* Table6349 */ 0x3213, /* VPSLLQZ256rm */ 0x3216, /* VPSLLQZ256rr */ /* Table6351 */ 0x2e52, /* VPMULUDQZ256rm */ 0x2e58, /* VPMULUDQZ256rr */ /* Table6353 */ 0x34a3, /* VPSUBQZ256rm */ 0x34a9, /* VPSUBQZ256rr */ /* Table6355 */ 0x1f63, /* VMOVUPSZrm */ 0x1f66, /* VMOVUPSZrr */ /* Table6357 */ 0x1f61, /* VMOVUPSZmr */ 0x1f67, /* VMOVUPSZrr_REV */ /* Table6359 */ 0x3b03, /* VUNPCKLPSZrm */ 0x3b09, /* VUNPCKLPSZrr */ /* Table6361 */ 0x3ac5, /* VUNPCKHPSZrm */ 0x3acb, /* VUNPCKHPSZrr */ /* Table6363 */ 0x1d91, /* VMOVAPSZrm */ 0x1d94, /* VMOVAPSZrr */ /* Table6365 */ 0x1d8f, /* VMOVAPSZmr */ 0x1d95, /* VMOVAPSZrr_REV */ /* Table6367 */ 0x1ebc, /* VMOVNTPSZmr */ 0x0, /* */ /* Table6369 */ 0x39e9, /* VSQRTPSZm */ 0x39ef, /* VSQRTPSZr */ /* Table6371 */ 0xc95, /* VANDPSZrm */ 0xc9b, /* VANDPSZrr */ /* Table6373 */ 0xc57, /* VANDNPSZrm */ 0xc5d, /* VANDNPSZrr */ /* Table6375 */ 0x201c, /* VORPSZrm */ 0x2022, /* VORPSZrr */ /* Table6377 */ 0x3b41, /* VXORPSZrm */ 0x3b47, /* VXORPSZrr */ /* Table6379 */ 0xb8e, /* VADDPSZrm */ 0xb94, /* VADDPSZrr */ /* Table6381 */ 0x1fb7, /* VMULPSZrm */ 0x1fbd, /* VMULPSZrr */ /* Table6383 */ 0xf34, /* VCVTPS2PDZrm */ 0xf3a, /* VCVTPS2PDZrr */ /* Table6385 */ 0xe39, /* VCVTDQ2PSZrm */ 0xe3f, /* VCVTDQ2PSZrr */ /* Table6387 */ 0x3a4c, /* VSUBPSZrm */ 0x3a52, /* VSUBPSZrr */ /* Table6389 */ 0x1d14, /* VMINPSZrm */ 0x1d1a, /* VMINPSZrr */ /* Table6391 */ 0x1250, /* VDIVPSZrm */ 0x1256, /* VDIVPSZrr */ /* Table6393 */ 0x1c69, /* VMAXPSZrm */ 0x1c6f, /* VMAXPSZrr */ /* Table6395 */ 0x111e, /* VCVTTPS2UDQZrm */ 0x1124, /* VCVTTPS2UDQZrr */ /* Table6397 */ 0xf88, /* VCVTPS2UDQZrm */ 0xf8e, /* VCVTPS2UDQZrr */ /* Table6399 */ 0xd9e, /* VCMPPSZrmi */ 0xda2, /* VCMPPSZrri */ /* Table6401 */ 0x39ab, /* VSHUFPSZrmi */ 0x39ae, /* VSHUFPSZrri */ /* Table6403 */ 0x1f03, /* VMOVSLDUPZrm */ 0x1f06, /* VMOVSLDUPZrr */ /* Table6405 */ 0x1eed, /* VMOVSHDUPZrm */ 0x1ef0, /* VMOVSHDUPZrr */ /* Table6407 */ 0x10e0, /* VCVTTPS2DQZrm */ 0x10e6, /* VCVTTPS2DQZrr */ /* Table6409 */ 0x1e3f, /* VMOVDQU32Zrm */ 0x1e42, /* VMOVDQU32Zrr */ /* Table6411 */ 0x3193, /* VPSHUFHWZmi */ 0x3196, /* VPSHUFHWZri */ /* Table6413 */ 0x1192, /* VCVTUDQ2PDZrm */ 0x1198, /* VCVTUDQ2PDZrr */ /* Table6415 */ 0x1e3d, /* VMOVDQU32Zmr */ 0x1e43, /* VMOVDQU32Zrr_REV */ /* Table6417 */ 0xe1a, /* VCVTDQ2PDZrm */ 0xe20, /* VCVTDQ2PDZrr */ /* Table6419 */ 0x1e81, /* VMOVDQU8Zrm */ 0x1e84, /* VMOVDQU8Zrr */ /* Table6421 */ 0x31a9, /* VPSHUFLWZmi */ 0x31ac, /* VPSHUFLWZri */ /* Table6423 */ 0x11ad, /* VCVTUDQ2PSZrm */ 0x11b3, /* VCVTUDQ2PSZrr */ /* Table6425 */ 0x1e7f, /* VMOVDQU8Zmr */ 0x1e85, /* VMOVDQU8Zrr_REV */ /* Table6427 */ 0xf12, /* VCVTPS2DQZrm */ 0xf18, /* VCVTPS2DQZrr */ /* Table6429 */ 0x364f, /* VPUNPCKLBWZrm */ 0x3652, /* VPUNPCKLBWZrr */ /* Table6431 */ 0x36a3, /* VPUNPCKLWDZrm */ 0x36a6, /* VPUNPCKLWDZrr */ /* Table6433 */ 0x366b, /* VPUNPCKLDQZrm */ 0x3671, /* VPUNPCKLDQZrr */ /* Table6435 */ 0x20c0, /* VPACKSSWBZrm */ 0x20c3, /* VPACKSSWBZrr */ /* Table6437 */ 0x2405, /* VPCMPGTBZrm */ 0x2407, /* VPCMPGTBZrr */ /* Table6439 */ 0x2441, /* VPCMPGTWZrm */ 0x2443, /* VPCMPGTWZrr */ /* Table6441 */ 0x2419, /* VPCMPGTDZrm */ 0x241d, /* VPCMPGTDZrr */ /* Table6443 */ 0x20f5, /* VPACKUSWBZrm */ 0x20f8, /* VPACKUSWBZrr */ /* Table6445 */ 0x35e5, /* VPUNPCKHBWZrm */ 0x35e8, /* VPUNPCKHBWZrr */ /* Table6447 */ 0x3639, /* VPUNPCKHWDZrm */ 0x363c, /* VPUNPCKHWDZrr */ /* Table6449 */ 0x3601, /* VPUNPCKHDQZrm */ 0x3607, /* VPUNPCKHDQZrr */ /* Table6451 */ 0x20a7, /* VPACKSSDWZrm */ 0x20ad, /* VPACKSSDWZrr */ /* Table6453 */ 0x1dd4, /* VMOVDQA32Zrm */ 0x1dd7, /* VMOVDQA32Zrr */ /* Table6455 */ 0x317d, /* VPSHUFDZmi */ 0x3180, /* VPSHUFDZri */ /* Table6457 */ 0x0, /* */ 0x0, /* */ 0x3454, /* VPSRLWZmi */ 0x0, /* */ 0x336c, /* VPSRAWZmi */ 0x0, /* */ 0x3296, /* VPSLLWZmi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3457, /* VPSRLWZri */ 0x0, /* */ 0x336f, /* VPSRAWZri */ 0x0, /* */ 0x3299, /* VPSLLWZri */ 0x0, /* */ /* Table6473 */ 0x2f7f, /* VPRORDZmi */ 0x2f13, /* VPROLDZmi */ 0x33a7, /* VPSRLDZmi */ 0x0, /* */ 0x32c9, /* VPSRADZmi */ 0x0, /* */ 0x31e9, /* VPSLLDZmi */ 0x0, /* */ 0x2f82, /* VPRORDZri */ 0x2f16, /* VPROLDZri */ 0x33aa, /* VPSRLDZri */ 0x0, /* */ 0x32cc, /* VPSRADZri */ 0x0, /* */ 0x31ec, /* VPSLLDZri */ 0x0, /* */ /* Table6489 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3380, /* VPSRLDQZrm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31c2, /* VPSLLDQZrm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3381, /* VPSRLDQZrr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31c3, /* VPSLLDQZrr */ /* Table6505 */ 0x23b5, /* VPCMPEQBZrm */ 0x23b7, /* VPCMPEQBZrr */ /* Table6507 */ 0x23f1, /* VPCMPEQWZrm */ 0x23f3, /* VPCMPEQWZrr */ /* Table6509 */ 0x23c9, /* VPCMPEQDZrm */ 0x23cd, /* VPCMPEQDZrr */ /* Table6511 */ 0x113c, /* VCVTTPS2UQQZrm */ 0x1142, /* VCVTTPS2UQQZrr */ /* Table6513 */ 0xfa6, /* VCVTPS2UQQZrm */ 0xfac, /* VCVTPS2UQQZrr */ /* Table6515 */ 0x1100, /* VCVTTPS2QQZrm */ 0x1106, /* VCVTTPS2QQZrr */ /* Table6517 */ 0xf6a, /* VCVTPS2QQZrm */ 0xf70, /* VCVTPS2QQZrr */ /* Table6519 */ 0x1dd2, /* VMOVDQA32Zmr */ 0x1dd8, /* VMOVDQA32Zrr_REV */ /* Table6521 */ 0x345a, /* VPSRLWZrm */ 0x345d, /* VPSRLWZrr */ /* Table6523 */ 0x33ad, /* VPSRLDZrm */ 0x33b0, /* VPSRLDZrr */ /* Table6525 */ 0x2e24, /* VPMULLWZrm */ 0x2e27, /* VPMULLWZrr */ /* Table6527 */ 0x34f1, /* VPSUBUSBZrm */ 0x34f4, /* VPSUBUSBZrr */ /* Table6529 */ 0x3507, /* VPSUBUSWZrm */ 0x350a, /* VPSUBUSWZrr */ /* Table6531 */ 0x2af3, /* VPMINUBZrm */ 0x2af6, /* VPMINUBZrr */ /* Table6533 */ 0x21e7, /* VPANDDZrm */ 0x21ed, /* VPANDDZrr */ /* Table6535 */ 0x218b, /* VPADDUSBZrm */ 0x218e, /* VPADDUSBZrr */ /* Table6537 */ 0x21a1, /* VPADDUSWZrm */ 0x21a4, /* VPADDUSWZrr */ /* Table6539 */ 0x2a27, /* VPMAXUBZrm */ 0x2a2a, /* VPMAXUBZrr */ /* Table6541 */ 0x2202, /* VPANDNDZrm */ 0x2208, /* VPANDNDZrr */ /* Table6543 */ 0x2257, /* VPAVGBZrm */ 0x225a, /* VPAVGBZrr */ /* Table6545 */ 0x3372, /* VPSRAWZrm */ 0x3375, /* VPSRAWZrr */ /* Table6547 */ 0x32cf, /* VPSRADZrm */ 0x32d2, /* VPSRADZrr */ /* Table6549 */ 0x226d, /* VPAVGWZrm */ 0x2270, /* VPAVGWZrr */ /* Table6551 */ 0x2dbe, /* VPMULHUWZrm */ 0x2dc1, /* VPMULHUWZrr */ /* Table6553 */ 0x2dd4, /* VPMULHWZrm */ 0x2dd7, /* VPMULHWZrr */ /* Table6555 */ 0x1eb2, /* VMOVNTDQZmr */ 0x0, /* */ /* Table6557 */ 0x34c5, /* VPSUBSBZrm */ 0x34c8, /* VPSUBSBZrr */ /* Table6559 */ 0x34db, /* VPSUBSWZrm */ 0x34de, /* VPSUBSWZrr */ /* Table6561 */ 0x2add, /* VPMINSWZrm */ 0x2ae0, /* VPMINSWZrr */ /* Table6563 */ 0x2ed2, /* VPORDZrm */ 0x2ed8, /* VPORDZrr */ /* Table6565 */ 0x215f, /* VPADDSBZrm */ 0x2162, /* VPADDSBZrr */ /* Table6567 */ 0x2175, /* VPADDSWZrm */ 0x2178, /* VPADDSWZrr */ /* Table6569 */ 0x2a11, /* VPMAXSWZrm */ 0x2a14, /* VPMAXSWZrr */ /* Table6571 */ 0x36bd, /* VPXORDZrm */ 0x36c3, /* VPXORDZrr */ /* Table6573 */ 0x329c, /* VPSLLWZrm */ 0x329f, /* VPSLLWZrr */ /* Table6575 */ 0x31ef, /* VPSLLDZrm */ 0x31f2, /* VPSLLDZrr */ /* Table6577 */ 0x29a3, /* VPMADDWDZrm */ 0x29a6, /* VPMADDWDZrr */ /* Table6579 */ 0x2ff4, /* VPSADBWZrm */ 0x2ff5, /* VPSADBWZrr */ /* Table6581 */ 0x3471, /* VPSUBBZrm */ 0x3474, /* VPSUBBZrr */ /* Table6583 */ 0x351d, /* VPSUBWZrm */ 0x3520, /* VPSUBWZrr */ /* Table6585 */ 0x348d, /* VPSUBDZrm */ 0x3493, /* VPSUBDZrr */ /* Table6587 */ 0x210b, /* VPADDBZrm */ 0x210e, /* VPADDBZrr */ /* Table6589 */ 0x21b7, /* VPADDWZrm */ 0x21ba, /* VPADDWZrr */ /* Table6591 */ 0x2127, /* VPADDDZrm */ 0x212d, /* VPADDDZrr */ /* Table6593 */ 0xfe2, /* VCVTQQ2PSZrm */ 0xfe8, /* VCVTQQ2PSZrr */ /* Table6595 */ 0x10a2, /* VCVTTPD2UDQZrm */ 0x10a8, /* VCVTTPD2UDQZrr */ /* Table6597 */ 0xebb, /* VCVTPD2UDQZrm */ 0xec1, /* VCVTPD2UDQZrr */ /* Table6599 */ 0x1e60, /* VMOVDQU64Zrm */ 0x1e63, /* VMOVDQU64Zrr */ /* Table6601 */ 0x11cb, /* VCVTUQQ2PDZrm */ 0x11d1, /* VCVTUQQ2PDZrr */ /* Table6603 */ 0x1e5e, /* VMOVDQU64Zmr */ 0x1e64, /* VMOVDQU64Zrr_REV */ /* Table6605 */ 0xfc4, /* VCVTQQ2PDZrm */ 0xfca, /* VCVTQQ2PDZrr */ /* Table6607 */ 0x1dac, /* VMOVDDUPZrm */ 0x1daf, /* VMOVDDUPZrr */ /* Table6609 */ 0x1e1e, /* VMOVDQU16Zrm */ 0x1e21, /* VMOVDQU16Zrr */ /* Table6611 */ 0x11e9, /* VCVTUQQ2PSZrm */ 0x11ef, /* VCVTUQQ2PSZrr */ /* Table6613 */ 0x1e1c, /* VMOVDQU16Zmr */ 0x1e22, /* VMOVDQU16Zrr_REV */ /* Table6615 */ 0xe5b, /* VCVTPD2DQZrm */ 0xe61, /* VCVTPD2DQZrr */ /* Table6617 */ 0x1f3a, /* VMOVUPDZrm */ 0x1f3d, /* VMOVUPDZrr */ /* Table6619 */ 0x1f38, /* VMOVUPDZmr */ 0x1f3e, /* VMOVUPDZrr_REV */ /* Table6621 */ 0x3ae4, /* VUNPCKLPDZrm */ 0x3aea, /* VUNPCKLPDZrr */ /* Table6623 */ 0x3aa6, /* VUNPCKHPDZrm */ 0x3aac, /* VUNPCKHPDZrr */ /* Table6625 */ 0x1d68, /* VMOVAPDZrm */ 0x1d6b, /* VMOVAPDZrr */ /* Table6627 */ 0x1d66, /* VMOVAPDZmr */ 0x1d6c, /* VMOVAPDZrr_REV */ /* Table6629 */ 0x1eb7, /* VMOVNTPDZmr */ 0x0, /* */ /* Table6631 */ 0x39c7, /* VSQRTPDZm */ 0x39cd, /* VSQRTPDZr */ /* Table6633 */ 0xc76, /* VANDPDZrm */ 0xc7c, /* VANDPDZrr */ /* Table6635 */ 0xc38, /* VANDNPDZrm */ 0xc3e, /* VANDNPDZrr */ /* Table6637 */ 0x1ffd, /* VORPDZrm */ 0x2003, /* VORPDZrr */ /* Table6639 */ 0x3b22, /* VXORPDZrm */ 0x3b28, /* VXORPDZrr */ /* Table6641 */ 0xb6c, /* VADDPDZrm */ 0xb72, /* VADDPDZrr */ /* Table6643 */ 0x1f95, /* VMULPDZrm */ 0x1f9b, /* VMULPDZrr */ /* Table6645 */ 0xe7d, /* VCVTPD2PSZrm */ 0xe83, /* VCVTPD2PSZrr */ /* Table6647 */ 0x3a2a, /* VSUBPDZrm */ 0x3a30, /* VSUBPDZrr */ /* Table6649 */ 0x1cf2, /* VMINPDZrm */ 0x1cf8, /* VMINPDZrr */ /* Table6651 */ 0x122e, /* VDIVPDZrm */ 0x1234, /* VDIVPDZrr */ /* Table6653 */ 0x1c47, /* VMAXPDZrm */ 0x1c4d, /* VMAXPDZrr */ /* Table6655 */ 0x368a, /* VPUNPCKLQDQZrm */ 0x3690, /* VPUNPCKLQDQZrr */ /* Table6657 */ 0x3620, /* VPUNPCKHQDQZrm */ 0x3626, /* VPUNPCKHQDQZrr */ /* Table6659 */ 0x1df5, /* VMOVDQA64Zrm */ 0x1df8, /* VMOVDQA64Zrr */ /* Table6661 */ 0x2f9a, /* VPRORQZmi */ 0x2f2e, /* VPROLQZmi */ 0x0, /* */ 0x0, /* */ 0x32f9, /* VPSRAQZmi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f9d, /* VPRORQZri */ 0x2f31, /* VPROLQZri */ 0x0, /* */ 0x0, /* */ 0x32fc, /* VPSRAQZri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table6677 */ 0x0, /* */ 0x0, /* */ 0x33da, /* VPSRLQZmi */ 0x3380, /* VPSRLDQZrm */ 0x0, /* */ 0x0, /* */ 0x321c, /* VPSLLQZmi */ 0x31c2, /* VPSLLDQZrm */ 0x0, /* */ 0x0, /* */ 0x33dd, /* VPSRLQZri */ 0x3381, /* VPSRLDQZrr */ 0x0, /* */ 0x0, /* */ 0x321f, /* VPSLLQZri */ 0x31c3, /* VPSLLDQZrr */ /* Table6693 */ 0x10c0, /* VCVTTPD2UQQZrm */ 0x10c6, /* VCVTTPD2UQQZrr */ /* Table6695 */ 0xed9, /* VCVTPD2UQQZrm */ 0xedf, /* VCVTPD2UQQZrr */ /* Table6697 */ 0x1084, /* VCVTTPD2QQZrm */ 0x108a, /* VCVTTPD2QQZrr */ /* Table6699 */ 0xe9d, /* VCVTPD2QQZrm */ 0xea3, /* VCVTPD2QQZrr */ /* Table6701 */ 0x1df3, /* VMOVDQA64Zmr */ 0x1df9, /* VMOVDQA64Zrr_REV */ /* Table6703 */ 0xd6e, /* VCMPPDZrmi */ 0xd72, /* VCMPPDZrri */ /* Table6705 */ 0x398c, /* VSHUFPDZrmi */ 0x398f, /* VSHUFPDZrri */ /* Table6707 */ 0x33e0, /* VPSRLQZrm */ 0x33e3, /* VPSRLQZrr */ /* Table6709 */ 0x2146, /* VPADDQZrm */ 0x214c, /* VPADDQZrr */ /* Table6711 */ 0x223c, /* VPANDQZrm */ 0x2242, /* VPANDQZrr */ /* Table6713 */ 0x221d, /* VPANDNQZrm */ 0x2223, /* VPANDNQZrr */ /* Table6715 */ 0x32ff, /* VPSRAQZrm */ 0x3302, /* VPSRAQZrr */ /* Table6717 */ 0x1064, /* VCVTTPD2DQZrm */ 0x106a, /* VCVTTPD2DQZrr */ /* Table6719 */ 0x2eed, /* VPORQZrm */ 0x2ef3, /* VPORQZrr */ /* Table6721 */ 0x36d8, /* VPXORQZrm */ 0x36de, /* VPXORQZrr */ /* Table6723 */ 0x3222, /* VPSLLQZrm */ 0x3225, /* VPSLLQZrr */ /* Table6725 */ 0x2e5b, /* VPMULUDQZrm */ 0x2e61, /* VPMULUDQZrr */ /* Table6727 */ 0x34ac, /* VPSUBQZrm */ 0x34b2, /* VPSUBQZrr */ /* Table6729 */ 0x1f4e, /* VMOVUPSZ128rmk */ 0x1f52, /* VMOVUPSZ128rrk */ /* Table6731 */ 0x1f4c, /* VMOVUPSZ128mrk */ 0x1f53, /* VMOVUPSZ128rrk_REV */ /* Table6733 */ 0x3af5, /* VUNPCKLPSZ128rmk */ 0x3af8, /* VUNPCKLPSZ128rrk */ /* Table6735 */ 0x3ab7, /* VUNPCKHPSZ128rmk */ 0x3aba, /* VUNPCKHPSZ128rrk */ /* Table6737 */ 0x1d7c, /* VMOVAPSZ128rmk */ 0x1d80, /* VMOVAPSZ128rrk */ /* Table6739 */ 0x1d7a, /* VMOVAPSZ128mrk */ 0x1d81, /* VMOVAPSZ128rrk_REV */ /* Table6741 */ 0x39db, /* VSQRTPSZ128mk */ 0x39de, /* VSQRTPSZ128rk */ /* Table6743 */ 0xc87, /* VANDPSZ128rmk */ 0xc8a, /* VANDPSZ128rrk */ /* Table6745 */ 0xc49, /* VANDNPSZ128rmk */ 0xc4c, /* VANDNPSZ128rrk */ /* Table6747 */ 0x200e, /* VORPSZ128rmk */ 0x2011, /* VORPSZ128rrk */ /* Table6749 */ 0x3b33, /* VXORPSZ128rmk */ 0x3b36, /* VXORPSZ128rrk */ /* Table6751 */ 0xb80, /* VADDPSZ128rmk */ 0xb83, /* VADDPSZ128rrk */ /* Table6753 */ 0x1fa9, /* VMULPSZ128rmk */ 0x1fac, /* VMULPSZ128rrk */ /* Table6755 */ 0xf26, /* VCVTPS2PDZ128rmk */ 0xf29, /* VCVTPS2PDZ128rrk */ /* Table6757 */ 0xe2b, /* VCVTDQ2PSZ128rmk */ 0xe2e, /* VCVTDQ2PSZ128rrk */ /* Table6759 */ 0x3a3e, /* VSUBPSZ128rmk */ 0x3a41, /* VSUBPSZ128rrk */ /* Table6761 */ 0x1d06, /* VMINPSZ128rmk */ 0x1d09, /* VMINPSZ128rrk */ /* Table6763 */ 0x1242, /* VDIVPSZ128rmk */ 0x1245, /* VDIVPSZ128rrk */ /* Table6765 */ 0x1c5b, /* VMAXPSZ128rmk */ 0x1c5e, /* VMAXPSZ128rrk */ /* Table6767 */ 0x1110, /* VCVTTPS2UDQZ128rmk */ 0x1113, /* VCVTTPS2UDQZ128rrk */ /* Table6769 */ 0xf7a, /* VCVTPS2UDQZ128rmk */ 0xf7d, /* VCVTPS2UDQZ128rrk */ /* Table6771 */ 0xd89, /* VCMPPSZ128rmik */ 0xd8d, /* VCMPPSZ128rrik */ /* Table6773 */ 0x399a, /* VSHUFPSZ128rmik */ 0x399d, /* VSHUFPSZ128rrik */ /* Table6775 */ 0x1f12, /* VMOVSSZrmk */ 0x1f16, /* VMOVSSZrrk */ /* Table6777 */ 0x1f10, /* VMOVSSZmrk */ 0x1f17, /* VMOVSSZrrk_REV */ /* Table6779 */ 0x1ef8, /* VMOVSLDUPZ128rmk */ 0x1efb, /* VMOVSLDUPZ128rrk */ /* Table6781 */ 0x1ee2, /* VMOVSHDUPZ128rmk */ 0x1ee5, /* VMOVSHDUPZ128rrk */ /* Table6783 */ 0x3a08, /* VSQRTSSZm_Intk */ 0x3a0c, /* VSQRTSSZr_Intk */ /* Table6785 */ 0xbad, /* VADDSSZrm_Intk */ 0xbb1, /* VADDSSZrr_Intk */ /* Table6787 */ 0x1fd6, /* VMULSSZrm_Intk */ 0x1fda, /* VMULSSZrr_Intk */ /* Table6789 */ 0x1033, /* VCVTSS2SDZrm_Intk */ 0x1037, /* VCVTSS2SDZrr_Intk */ /* Table6791 */ 0x10d2, /* VCVTTPS2DQZ128rmk */ 0x10d5, /* VCVTTPS2DQZ128rrk */ /* Table6793 */ 0x3a6b, /* VSUBSSZrm_Intk */ 0x3a6f, /* VSUBSSZrr_Intk */ /* Table6795 */ 0x1d33, /* VMINSSZrm_Intk */ 0x1d37, /* VMINSSZrr_Intk */ /* Table6797 */ 0x126f, /* VDIVSSZrm_Intk */ 0x1273, /* VDIVSSZrr_Intk */ /* Table6799 */ 0x1c88, /* VMAXSSZrm_Intk */ 0x1c8c, /* VMAXSSZrr_Intk */ /* Table6801 */ 0x1e2a, /* VMOVDQU32Z128rmk */ 0x1e2e, /* VMOVDQU32Z128rrk */ /* Table6803 */ 0x3188, /* VPSHUFHWZ128mik */ 0x318b, /* VPSHUFHWZ128rik */ /* Table6805 */ 0x1184, /* VCVTUDQ2PDZ128rmk */ 0x1187, /* VCVTUDQ2PDZ128rrk */ /* Table6807 */ 0x1e28, /* VMOVDQU32Z128mrk */ 0x1e2f, /* VMOVDQU32Z128rrk_REV */ /* Table6809 */ 0xdc4, /* VCMPSSZrm_Intk */ 0xdc9, /* VCMPSSZrr_Intk */ /* Table6811 */ 0xe0c, /* VCVTDQ2PDZ128rmk */ 0xe0f, /* VCVTDQ2PDZ128rrk */ /* Table6813 */ 0x1e6c, /* VMOVDQU8Z128rmk */ 0x1e70, /* VMOVDQU8Z128rrk */ /* Table6815 */ 0x319e, /* VPSHUFLWZ128mik */ 0x31a1, /* VPSHUFLWZ128rik */ /* Table6817 */ 0x119f, /* VCVTUDQ2PSZ128rmk */ 0x11a2, /* VCVTUDQ2PSZ128rrk */ /* Table6819 */ 0x1e6a, /* VMOVDQU8Z128mrk */ 0x1e71, /* VMOVDQU8Z128rrk_REV */ /* Table6821 */ 0xf04, /* VCVTPS2DQZ128rmk */ 0xf07, /* VCVTPS2DQZ128rrk */ /* Table6823 */ 0x3644, /* VPUNPCKLBWZ128rmk */ 0x3647, /* VPUNPCKLBWZ128rrk */ /* Table6825 */ 0x3698, /* VPUNPCKLWDZ128rmk */ 0x369b, /* VPUNPCKLWDZ128rrk */ /* Table6827 */ 0x365d, /* VPUNPCKLDQZ128rmk */ 0x3660, /* VPUNPCKLDQZ128rrk */ /* Table6829 */ 0x20b5, /* VPACKSSWBZ128rmk */ 0x20b8, /* VPACKSSWBZ128rrk */ /* Table6831 */ 0x23fe, /* VPCMPGTBZ128rmk */ 0x2400, /* VPCMPGTBZ128rrk */ /* Table6833 */ 0x243a, /* VPCMPGTWZ128rmk */ 0x243c, /* VPCMPGTWZ128rrk */ /* Table6835 */ 0x2410, /* VPCMPGTDZ128rmk */ 0x2412, /* VPCMPGTDZ128rrk */ /* Table6837 */ 0x20ea, /* VPACKUSWBZ128rmk */ 0x20ed, /* VPACKUSWBZ128rrk */ /* Table6839 */ 0x35da, /* VPUNPCKHBWZ128rmk */ 0x35dd, /* VPUNPCKHBWZ128rrk */ /* Table6841 */ 0x362e, /* VPUNPCKHWDZ128rmk */ 0x3631, /* VPUNPCKHWDZ128rrk */ /* Table6843 */ 0x35f3, /* VPUNPCKHDQZ128rmk */ 0x35f6, /* VPUNPCKHDQZ128rrk */ /* Table6845 */ 0x2099, /* VPACKSSDWZ128rmk */ 0x209c, /* VPACKSSDWZ128rrk */ /* Table6847 */ 0x1dbf, /* VMOVDQA32Z128rmk */ 0x1dc3, /* VMOVDQA32Z128rrk */ /* Table6849 */ 0x316c, /* VPSHUFDZ128mik */ 0x316f, /* VPSHUFDZ128rik */ /* Table6851 */ 0x0, /* */ 0x0, /* */ 0x343d, /* VPSRLWZ128mik */ 0x0, /* */ 0x3355, /* VPSRAWZ128mik */ 0x0, /* */ 0x327f, /* VPSLLWZ128mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3440, /* VPSRLWZ128rik */ 0x0, /* */ 0x3358, /* VPSRAWZ128rik */ 0x0, /* */ 0x3282, /* VPSLLWZ128rik */ 0x0, /* */ /* Table6867 */ 0x2f6e, /* VPRORDZ128mik */ 0x2f02, /* VPROLDZ128mik */ 0x338a, /* VPSRLDZ128mik */ 0x0, /* */ 0x32ac, /* VPSRADZ128mik */ 0x0, /* */ 0x31cc, /* VPSLLDZ128mik */ 0x0, /* */ 0x2f71, /* VPRORDZ128rik */ 0x2f05, /* VPROLDZ128rik */ 0x338d, /* VPSRLDZ128rik */ 0x0, /* */ 0x32af, /* VPSRADZ128rik */ 0x0, /* */ 0x31cf, /* VPSLLDZ128rik */ 0x0, /* */ /* Table6883 */ 0x23ae, /* VPCMPEQBZ128rmk */ 0x23b0, /* VPCMPEQBZ128rrk */ /* Table6885 */ 0x23ea, /* VPCMPEQWZ128rmk */ 0x23ec, /* VPCMPEQWZ128rrk */ /* Table6887 */ 0x23c0, /* VPCMPEQDZ128rmk */ 0x23c2, /* VPCMPEQDZ128rrk */ /* Table6889 */ 0x112e, /* VCVTTPS2UQQZ128rmk */ 0x1131, /* VCVTTPS2UQQZ128rrk */ /* Table6891 */ 0xf98, /* VCVTPS2UQQZ128rmk */ 0xf9b, /* VCVTPS2UQQZ128rrk */ /* Table6893 */ 0x10f2, /* VCVTTPS2QQZ128rmk */ 0x10f5, /* VCVTTPS2QQZ128rrk */ /* Table6895 */ 0xf5c, /* VCVTPS2QQZ128rmk */ 0xf5f, /* VCVTPS2QQZ128rrk */ /* Table6897 */ 0x1dbd, /* VMOVDQA32Z128mrk */ 0x1dc4, /* VMOVDQA32Z128rrk_REV */ /* Table6899 */ 0x3443, /* VPSRLWZ128rmk */ 0x3446, /* VPSRLWZ128rrk */ /* Table6901 */ 0x3390, /* VPSRLDZ128rmk */ 0x3393, /* VPSRLDZ128rrk */ /* Table6903 */ 0x2e19, /* VPMULLWZ128rmk */ 0x2e1c, /* VPMULLWZ128rrk */ /* Table6905 */ 0x34e6, /* VPSUBUSBZ128rmk */ 0x34e9, /* VPSUBUSBZ128rrk */ /* Table6907 */ 0x34fc, /* VPSUBUSWZ128rmk */ 0x34ff, /* VPSUBUSWZ128rrk */ /* Table6909 */ 0x2ae8, /* VPMINUBZ128rmk */ 0x2aeb, /* VPMINUBZ128rrk */ /* Table6911 */ 0x21d9, /* VPANDDZ128rmk */ 0x21dc, /* VPANDDZ128rrk */ /* Table6913 */ 0x2180, /* VPADDUSBZ128rmk */ 0x2183, /* VPADDUSBZ128rrk */ /* Table6915 */ 0x2196, /* VPADDUSWZ128rmk */ 0x2199, /* VPADDUSWZ128rrk */ /* Table6917 */ 0x2a1c, /* VPMAXUBZ128rmk */ 0x2a1f, /* VPMAXUBZ128rrk */ /* Table6919 */ 0x21f4, /* VPANDNDZ128rmk */ 0x21f7, /* VPANDNDZ128rrk */ /* Table6921 */ 0x224c, /* VPAVGBZ128rmk */ 0x224f, /* VPAVGBZ128rrk */ /* Table6923 */ 0x335b, /* VPSRAWZ128rmk */ 0x335e, /* VPSRAWZ128rrk */ /* Table6925 */ 0x32b2, /* VPSRADZ128rmk */ 0x32b5, /* VPSRADZ128rrk */ /* Table6927 */ 0x2262, /* VPAVGWZ128rmk */ 0x2265, /* VPAVGWZ128rrk */ /* Table6929 */ 0x2db3, /* VPMULHUWZ128rmk */ 0x2db6, /* VPMULHUWZ128rrk */ /* Table6931 */ 0x2dc9, /* VPMULHWZ128rmk */ 0x2dcc, /* VPMULHWZ128rrk */ /* Table6933 */ 0x34ba, /* VPSUBSBZ128rmk */ 0x34bd, /* VPSUBSBZ128rrk */ /* Table6935 */ 0x34d0, /* VPSUBSWZ128rmk */ 0x34d3, /* VPSUBSWZ128rrk */ /* Table6937 */ 0x2ad2, /* VPMINSWZ128rmk */ 0x2ad5, /* VPMINSWZ128rrk */ /* Table6939 */ 0x2ec4, /* VPORDZ128rmk */ 0x2ec7, /* VPORDZ128rrk */ /* Table6941 */ 0x2154, /* VPADDSBZ128rmk */ 0x2157, /* VPADDSBZ128rrk */ /* Table6943 */ 0x216a, /* VPADDSWZ128rmk */ 0x216d, /* VPADDSWZ128rrk */ /* Table6945 */ 0x2a06, /* VPMAXSWZ128rmk */ 0x2a09, /* VPMAXSWZ128rrk */ /* Table6947 */ 0x36af, /* VPXORDZ128rmk */ 0x36b2, /* VPXORDZ128rrk */ /* Table6949 */ 0x3285, /* VPSLLWZ128rmk */ 0x3288, /* VPSLLWZ128rrk */ /* Table6951 */ 0x31d2, /* VPSLLDZ128rmk */ 0x31d5, /* VPSLLDZ128rrk */ /* Table6953 */ 0x2998, /* VPMADDWDZ128rmk */ 0x299b, /* VPMADDWDZ128rrk */ /* Table6955 */ 0x3466, /* VPSUBBZ128rmk */ 0x3469, /* VPSUBBZ128rrk */ /* Table6957 */ 0x3512, /* VPSUBWZ128rmk */ 0x3515, /* VPSUBWZ128rrk */ /* Table6959 */ 0x347f, /* VPSUBDZ128rmk */ 0x3482, /* VPSUBDZ128rrk */ /* Table6961 */ 0x2100, /* VPADDBZ128rmk */ 0x2103, /* VPADDBZ128rrk */ /* Table6963 */ 0x21ac, /* VPADDWZ128rmk */ 0x21af, /* VPADDWZ128rrk */ /* Table6965 */ 0x2119, /* VPADDDZ128rmk */ 0x211c, /* VPADDDZ128rrk */ /* Table6967 */ 0xfd4, /* VCVTQQ2PSZ128rmk */ 0xfd7, /* VCVTQQ2PSZ128rrk */ /* Table6969 */ 0x1094, /* VCVTTPD2UDQZ128rmk */ 0x1097, /* VCVTTPD2UDQZ128rrk */ /* Table6971 */ 0xead, /* VCVTPD2UDQZ128rmk */ 0xeb0, /* VCVTPD2UDQZ128rrk */ /* Table6973 */ 0x1e4b, /* VMOVDQU64Z128rmk */ 0x1e4f, /* VMOVDQU64Z128rrk */ /* Table6975 */ 0x11bd, /* VCVTUQQ2PDZ128rmk */ 0x11c0, /* VCVTUQQ2PDZ128rrk */ /* Table6977 */ 0x1e49, /* VMOVDQU64Z128mrk */ 0x1e50, /* VMOVDQU64Z128rrk_REV */ /* Table6979 */ 0xfb6, /* VCVTQQ2PDZ128rmk */ 0xfb9, /* VCVTQQ2PDZ128rrk */ /* Table6981 */ 0x1ecf, /* VMOVSDZrmk */ 0x1ed3, /* VMOVSDZrrk */ /* Table6983 */ 0x1ecd, /* VMOVSDZmrk */ 0x1ed4, /* VMOVSDZrrk_REV */ /* Table6985 */ 0x1da1, /* VMOVDDUPZ128rmk */ 0x1da4, /* VMOVDDUPZ128rrk */ /* Table6987 */ 0x39f9, /* VSQRTSDZm_Intk */ 0x39fd, /* VSQRTSDZr_Intk */ /* Table6989 */ 0xb9e, /* VADDSDZrm_Intk */ 0xba2, /* VADDSDZrr_Intk */ /* Table6991 */ 0x1fc7, /* VMULSDZrm_Intk */ 0x1fcb, /* VMULSDZrr_Intk */ /* Table6993 */ 0xffa, /* VCVTSD2SSZrm_Intk */ 0xffe, /* VCVTSD2SSZrr_Intk */ /* Table6995 */ 0x3a5c, /* VSUBSDZrm_Intk */ 0x3a60, /* VSUBSDZrr_Intk */ /* Table6997 */ 0x1d24, /* VMINSDZrm_Intk */ 0x1d28, /* VMINSDZrr_Intk */ /* Table6999 */ 0x1260, /* VDIVSDZrm_Intk */ 0x1264, /* VDIVSDZrr_Intk */ /* Table7001 */ 0x1c79, /* VMAXSDZrm_Intk */ 0x1c7d, /* VMAXSDZrr_Intk */ /* Table7003 */ 0x1e09, /* VMOVDQU16Z128rmk */ 0x1e0d, /* VMOVDQU16Z128rrk */ /* Table7005 */ 0x11db, /* VCVTUQQ2PSZ128rmk */ 0x11de, /* VCVTUQQ2PSZ128rrk */ /* Table7007 */ 0x1e07, /* VMOVDQU16Z128mrk */ 0x1e0e, /* VMOVDQU16Z128rrk_REV */ /* Table7009 */ 0xdb0, /* VCMPSDZrm_Intk */ 0xdb5, /* VCMPSDZrr_Intk */ /* Table7011 */ 0xe4d, /* VCVTPD2DQZ128rmk */ 0xe50, /* VCVTPD2DQZ128rrk */ /* Table7013 */ 0x1f25, /* VMOVUPDZ128rmk */ 0x1f29, /* VMOVUPDZ128rrk */ /* Table7015 */ 0x1f23, /* VMOVUPDZ128mrk */ 0x1f2a, /* VMOVUPDZ128rrk_REV */ /* Table7017 */ 0x3ad6, /* VUNPCKLPDZ128rmk */ 0x3ad9, /* VUNPCKLPDZ128rrk */ /* Table7019 */ 0x3a98, /* VUNPCKHPDZ128rmk */ 0x3a9b, /* VUNPCKHPDZ128rrk */ /* Table7021 */ 0x1d53, /* VMOVAPDZ128rmk */ 0x1d57, /* VMOVAPDZ128rrk */ /* Table7023 */ 0x1d51, /* VMOVAPDZ128mrk */ 0x1d58, /* VMOVAPDZ128rrk_REV */ /* Table7025 */ 0x39b9, /* VSQRTPDZ128mk */ 0x39bc, /* VSQRTPDZ128rk */ /* Table7027 */ 0xc68, /* VANDPDZ128rmk */ 0xc6b, /* VANDPDZ128rrk */ /* Table7029 */ 0xc2a, /* VANDNPDZ128rmk */ 0xc2d, /* VANDNPDZ128rrk */ /* Table7031 */ 0x1fef, /* VORPDZ128rmk */ 0x1ff2, /* VORPDZ128rrk */ /* Table7033 */ 0x3b14, /* VXORPDZ128rmk */ 0x3b17, /* VXORPDZ128rrk */ /* Table7035 */ 0xb5e, /* VADDPDZ128rmk */ 0xb61, /* VADDPDZ128rrk */ /* Table7037 */ 0x1f87, /* VMULPDZ128rmk */ 0x1f8a, /* VMULPDZ128rrk */ /* Table7039 */ 0xe6f, /* VCVTPD2PSZ128rmk */ 0xe72, /* VCVTPD2PSZ128rrk */ /* Table7041 */ 0x3a1c, /* VSUBPDZ128rmk */ 0x3a1f, /* VSUBPDZ128rrk */ /* Table7043 */ 0x1ce4, /* VMINPDZ128rmk */ 0x1ce7, /* VMINPDZ128rrk */ /* Table7045 */ 0x1220, /* VDIVPDZ128rmk */ 0x1223, /* VDIVPDZ128rrk */ /* Table7047 */ 0x1c39, /* VMAXPDZ128rmk */ 0x1c3c, /* VMAXPDZ128rrk */ /* Table7049 */ 0x367c, /* VPUNPCKLQDQZ128rmk */ 0x367f, /* VPUNPCKLQDQZ128rrk */ /* Table7051 */ 0x3612, /* VPUNPCKHQDQZ128rmk */ 0x3615, /* VPUNPCKHQDQZ128rrk */ /* Table7053 */ 0x1de0, /* VMOVDQA64Z128rmk */ 0x1de4, /* VMOVDQA64Z128rrk */ /* Table7055 */ 0x2f89, /* VPRORQZ128mik */ 0x2f1d, /* VPROLQZ128mik */ 0x0, /* */ 0x0, /* */ 0x32dc, /* VPSRAQZ128mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f8c, /* VPRORQZ128rik */ 0x2f20, /* VPROLQZ128rik */ 0x0, /* */ 0x0, /* */ 0x32df, /* VPSRAQZ128rik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table7071 */ 0x0, /* */ 0x0, /* */ 0x33bd, /* VPSRLQZ128mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31ff, /* VPSLLQZ128mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33c0, /* VPSRLQZ128rik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3202, /* VPSLLQZ128rik */ 0x0, /* */ /* Table7087 */ 0x10b2, /* VCVTTPD2UQQZ128rmk */ 0x10b5, /* VCVTTPD2UQQZ128rrk */ /* Table7089 */ 0xecb, /* VCVTPD2UQQZ128rmk */ 0xece, /* VCVTPD2UQQZ128rrk */ /* Table7091 */ 0x1076, /* VCVTTPD2QQZ128rmk */ 0x1079, /* VCVTTPD2QQZ128rrk */ /* Table7093 */ 0xe8f, /* VCVTPD2QQZ128rmk */ 0xe92, /* VCVTPD2QQZ128rrk */ /* Table7095 */ 0x1dde, /* VMOVDQA64Z128mrk */ 0x1de5, /* VMOVDQA64Z128rrk_REV */ /* Table7097 */ 0xd59, /* VCMPPDZ128rmik */ 0xd5d, /* VCMPPDZ128rrik */ /* Table7099 */ 0x397b, /* VSHUFPDZ128rmik */ 0x397e, /* VSHUFPDZ128rrik */ /* Table7101 */ 0x33c3, /* VPSRLQZ128rmk */ 0x33c6, /* VPSRLQZ128rrk */ /* Table7103 */ 0x2138, /* VPADDQZ128rmk */ 0x213b, /* VPADDQZ128rrk */ /* Table7105 */ 0x222e, /* VPANDQZ128rmk */ 0x2231, /* VPANDQZ128rrk */ /* Table7107 */ 0x220f, /* VPANDNQZ128rmk */ 0x2212, /* VPANDNQZ128rrk */ /* Table7109 */ 0x32e2, /* VPSRAQZ128rmk */ 0x32e5, /* VPSRAQZ128rrk */ /* Table7111 */ 0x1056, /* VCVTTPD2DQZ128rmk */ 0x1059, /* VCVTTPD2DQZ128rrk */ /* Table7113 */ 0x2edf, /* VPORQZ128rmk */ 0x2ee2, /* VPORQZ128rrk */ /* Table7115 */ 0x36ca, /* VPXORQZ128rmk */ 0x36cd, /* VPXORQZ128rrk */ /* Table7117 */ 0x3205, /* VPSLLQZ128rmk */ 0x3208, /* VPSLLQZ128rrk */ /* Table7119 */ 0x2e4d, /* VPMULUDQZ128rmk */ 0x2e50, /* VPMULUDQZ128rrk */ /* Table7121 */ 0x349e, /* VPSUBQZ128rmk */ 0x34a1, /* VPSUBQZ128rrk */ /* Table7123 */ 0x1f59, /* VMOVUPSZ256rmk */ 0x1f5d, /* VMOVUPSZ256rrk */ /* Table7125 */ 0x1f57, /* VMOVUPSZ256mrk */ 0x1f5e, /* VMOVUPSZ256rrk_REV */ /* Table7127 */ 0x3afe, /* VUNPCKLPSZ256rmk */ 0x3b01, /* VUNPCKLPSZ256rrk */ /* Table7129 */ 0x3ac0, /* VUNPCKHPSZ256rmk */ 0x3ac3, /* VUNPCKHPSZ256rrk */ /* Table7131 */ 0x1d87, /* VMOVAPSZ256rmk */ 0x1d8b, /* VMOVAPSZ256rrk */ /* Table7133 */ 0x1d85, /* VMOVAPSZ256mrk */ 0x1d8c, /* VMOVAPSZ256rrk_REV */ /* Table7135 */ 0x39e4, /* VSQRTPSZ256mk */ 0x39e7, /* VSQRTPSZ256rk */ /* Table7137 */ 0xc90, /* VANDPSZ256rmk */ 0xc93, /* VANDPSZ256rrk */ /* Table7139 */ 0xc52, /* VANDNPSZ256rmk */ 0xc55, /* VANDNPSZ256rrk */ /* Table7141 */ 0x2017, /* VORPSZ256rmk */ 0x201a, /* VORPSZ256rrk */ /* Table7143 */ 0x3b3c, /* VXORPSZ256rmk */ 0x3b3f, /* VXORPSZ256rrk */ /* Table7145 */ 0xb89, /* VADDPSZ256rmk */ 0xb8c, /* VADDPSZ256rrk */ /* Table7147 */ 0x1fb2, /* VMULPSZ256rmk */ 0x1fb5, /* VMULPSZ256rrk */ /* Table7149 */ 0xf2f, /* VCVTPS2PDZ256rmk */ 0xf32, /* VCVTPS2PDZ256rrk */ /* Table7151 */ 0xe34, /* VCVTDQ2PSZ256rmk */ 0xe37, /* VCVTDQ2PSZ256rrk */ /* Table7153 */ 0x3a47, /* VSUBPSZ256rmk */ 0x3a4a, /* VSUBPSZ256rrk */ /* Table7155 */ 0x1d0f, /* VMINPSZ256rmk */ 0x1d12, /* VMINPSZ256rrk */ /* Table7157 */ 0x124b, /* VDIVPSZ256rmk */ 0x124e, /* VDIVPSZ256rrk */ /* Table7159 */ 0x1c64, /* VMAXPSZ256rmk */ 0x1c67, /* VMAXPSZ256rrk */ /* Table7161 */ 0x1119, /* VCVTTPS2UDQZ256rmk */ 0x111c, /* VCVTTPS2UDQZ256rrk */ /* Table7163 */ 0xf83, /* VCVTPS2UDQZ256rmk */ 0xf86, /* VCVTPS2UDQZ256rrk */ /* Table7165 */ 0xd95, /* VCMPPSZ256rmik */ 0xd99, /* VCMPPSZ256rrik */ /* Table7167 */ 0x39a3, /* VSHUFPSZ256rmik */ 0x39a6, /* VSHUFPSZ256rrik */ /* Table7169 */ 0x1efe, /* VMOVSLDUPZ256rmk */ 0x1f01, /* VMOVSLDUPZ256rrk */ /* Table7171 */ 0x1ee8, /* VMOVSHDUPZ256rmk */ 0x1eeb, /* VMOVSHDUPZ256rrk */ /* Table7173 */ 0x10db, /* VCVTTPS2DQZ256rmk */ 0x10de, /* VCVTTPS2DQZ256rrk */ /* Table7175 */ 0x1e35, /* VMOVDQU32Z256rmk */ 0x1e39, /* VMOVDQU32Z256rrk */ /* Table7177 */ 0x318e, /* VPSHUFHWZ256mik */ 0x3191, /* VPSHUFHWZ256rik */ /* Table7179 */ 0x118d, /* VCVTUDQ2PDZ256rmk */ 0x1190, /* VCVTUDQ2PDZ256rrk */ /* Table7181 */ 0x1e33, /* VMOVDQU32Z256mrk */ 0x1e3a, /* VMOVDQU32Z256rrk_REV */ /* Table7183 */ 0xe15, /* VCVTDQ2PDZ256rmk */ 0xe18, /* VCVTDQ2PDZ256rrk */ /* Table7185 */ 0x1e77, /* VMOVDQU8Z256rmk */ 0x1e7b, /* VMOVDQU8Z256rrk */ /* Table7187 */ 0x31a4, /* VPSHUFLWZ256mik */ 0x31a7, /* VPSHUFLWZ256rik */ /* Table7189 */ 0x11a8, /* VCVTUDQ2PSZ256rmk */ 0x11ab, /* VCVTUDQ2PSZ256rrk */ /* Table7191 */ 0x1e75, /* VMOVDQU8Z256mrk */ 0x1e7c, /* VMOVDQU8Z256rrk_REV */ /* Table7193 */ 0xf0d, /* VCVTPS2DQZ256rmk */ 0xf10, /* VCVTPS2DQZ256rrk */ /* Table7195 */ 0x364a, /* VPUNPCKLBWZ256rmk */ 0x364d, /* VPUNPCKLBWZ256rrk */ /* Table7197 */ 0x369e, /* VPUNPCKLWDZ256rmk */ 0x36a1, /* VPUNPCKLWDZ256rrk */ /* Table7199 */ 0x3666, /* VPUNPCKLDQZ256rmk */ 0x3669, /* VPUNPCKLDQZ256rrk */ /* Table7201 */ 0x20bb, /* VPACKSSWBZ256rmk */ 0x20be, /* VPACKSSWBZ256rrk */ /* Table7203 */ 0x2402, /* VPCMPGTBZ256rmk */ 0x2404, /* VPCMPGTBZ256rrk */ /* Table7205 */ 0x243e, /* VPCMPGTWZ256rmk */ 0x2440, /* VPCMPGTWZ256rrk */ /* Table7207 */ 0x2416, /* VPCMPGTDZ256rmk */ 0x2418, /* VPCMPGTDZ256rrk */ /* Table7209 */ 0x20f0, /* VPACKUSWBZ256rmk */ 0x20f3, /* VPACKUSWBZ256rrk */ /* Table7211 */ 0x35e0, /* VPUNPCKHBWZ256rmk */ 0x35e3, /* VPUNPCKHBWZ256rrk */ /* Table7213 */ 0x3634, /* VPUNPCKHWDZ256rmk */ 0x3637, /* VPUNPCKHWDZ256rrk */ /* Table7215 */ 0x35fc, /* VPUNPCKHDQZ256rmk */ 0x35ff, /* VPUNPCKHDQZ256rrk */ /* Table7217 */ 0x20a2, /* VPACKSSDWZ256rmk */ 0x20a5, /* VPACKSSDWZ256rrk */ /* Table7219 */ 0x1dca, /* VMOVDQA32Z256rmk */ 0x1dce, /* VMOVDQA32Z256rrk */ /* Table7221 */ 0x3175, /* VPSHUFDZ256mik */ 0x3178, /* VPSHUFDZ256rik */ /* Table7223 */ 0x0, /* */ 0x0, /* */ 0x3449, /* VPSRLWZ256mik */ 0x0, /* */ 0x3361, /* VPSRAWZ256mik */ 0x0, /* */ 0x328b, /* VPSLLWZ256mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x344c, /* VPSRLWZ256rik */ 0x0, /* */ 0x3364, /* VPSRAWZ256rik */ 0x0, /* */ 0x328e, /* VPSLLWZ256rik */ 0x0, /* */ /* Table7239 */ 0x2f77, /* VPRORDZ256mik */ 0x2f0b, /* VPROLDZ256mik */ 0x3399, /* VPSRLDZ256mik */ 0x0, /* */ 0x32bb, /* VPSRADZ256mik */ 0x0, /* */ 0x31db, /* VPSLLDZ256mik */ 0x0, /* */ 0x2f7a, /* VPRORDZ256rik */ 0x2f0e, /* VPROLDZ256rik */ 0x339c, /* VPSRLDZ256rik */ 0x0, /* */ 0x32be, /* VPSRADZ256rik */ 0x0, /* */ 0x31de, /* VPSLLDZ256rik */ 0x0, /* */ /* Table7255 */ 0x23b2, /* VPCMPEQBZ256rmk */ 0x23b4, /* VPCMPEQBZ256rrk */ /* Table7257 */ 0x23ee, /* VPCMPEQWZ256rmk */ 0x23f0, /* VPCMPEQWZ256rrk */ /* Table7259 */ 0x23c6, /* VPCMPEQDZ256rmk */ 0x23c8, /* VPCMPEQDZ256rrk */ /* Table7261 */ 0x1137, /* VCVTTPS2UQQZ256rmk */ 0x113a, /* VCVTTPS2UQQZ256rrk */ /* Table7263 */ 0xfa1, /* VCVTPS2UQQZ256rmk */ 0xfa4, /* VCVTPS2UQQZ256rrk */ /* Table7265 */ 0x10fb, /* VCVTTPS2QQZ256rmk */ 0x10fe, /* VCVTTPS2QQZ256rrk */ /* Table7267 */ 0xf65, /* VCVTPS2QQZ256rmk */ 0xf68, /* VCVTPS2QQZ256rrk */ /* Table7269 */ 0x1dc8, /* VMOVDQA32Z256mrk */ 0x1dcf, /* VMOVDQA32Z256rrk_REV */ /* Table7271 */ 0x344f, /* VPSRLWZ256rmk */ 0x3452, /* VPSRLWZ256rrk */ /* Table7273 */ 0x339f, /* VPSRLDZ256rmk */ 0x33a2, /* VPSRLDZ256rrk */ /* Table7275 */ 0x2e1f, /* VPMULLWZ256rmk */ 0x2e22, /* VPMULLWZ256rrk */ /* Table7277 */ 0x34ec, /* VPSUBUSBZ256rmk */ 0x34ef, /* VPSUBUSBZ256rrk */ /* Table7279 */ 0x3502, /* VPSUBUSWZ256rmk */ 0x3505, /* VPSUBUSWZ256rrk */ /* Table7281 */ 0x2aee, /* VPMINUBZ256rmk */ 0x2af1, /* VPMINUBZ256rrk */ /* Table7283 */ 0x21e2, /* VPANDDZ256rmk */ 0x21e5, /* VPANDDZ256rrk */ /* Table7285 */ 0x2186, /* VPADDUSBZ256rmk */ 0x2189, /* VPADDUSBZ256rrk */ /* Table7287 */ 0x219c, /* VPADDUSWZ256rmk */ 0x219f, /* VPADDUSWZ256rrk */ /* Table7289 */ 0x2a22, /* VPMAXUBZ256rmk */ 0x2a25, /* VPMAXUBZ256rrk */ /* Table7291 */ 0x21fd, /* VPANDNDZ256rmk */ 0x2200, /* VPANDNDZ256rrk */ /* Table7293 */ 0x2252, /* VPAVGBZ256rmk */ 0x2255, /* VPAVGBZ256rrk */ /* Table7295 */ 0x3367, /* VPSRAWZ256rmk */ 0x336a, /* VPSRAWZ256rrk */ /* Table7297 */ 0x32c1, /* VPSRADZ256rmk */ 0x32c4, /* VPSRADZ256rrk */ /* Table7299 */ 0x2268, /* VPAVGWZ256rmk */ 0x226b, /* VPAVGWZ256rrk */ /* Table7301 */ 0x2db9, /* VPMULHUWZ256rmk */ 0x2dbc, /* VPMULHUWZ256rrk */ /* Table7303 */ 0x2dcf, /* VPMULHWZ256rmk */ 0x2dd2, /* VPMULHWZ256rrk */ /* Table7305 */ 0x34c0, /* VPSUBSBZ256rmk */ 0x34c3, /* VPSUBSBZ256rrk */ /* Table7307 */ 0x34d6, /* VPSUBSWZ256rmk */ 0x34d9, /* VPSUBSWZ256rrk */ /* Table7309 */ 0x2ad8, /* VPMINSWZ256rmk */ 0x2adb, /* VPMINSWZ256rrk */ /* Table7311 */ 0x2ecd, /* VPORDZ256rmk */ 0x2ed0, /* VPORDZ256rrk */ /* Table7313 */ 0x215a, /* VPADDSBZ256rmk */ 0x215d, /* VPADDSBZ256rrk */ /* Table7315 */ 0x2170, /* VPADDSWZ256rmk */ 0x2173, /* VPADDSWZ256rrk */ /* Table7317 */ 0x2a0c, /* VPMAXSWZ256rmk */ 0x2a0f, /* VPMAXSWZ256rrk */ /* Table7319 */ 0x36b8, /* VPXORDZ256rmk */ 0x36bb, /* VPXORDZ256rrk */ /* Table7321 */ 0x3291, /* VPSLLWZ256rmk */ 0x3294, /* VPSLLWZ256rrk */ /* Table7323 */ 0x31e1, /* VPSLLDZ256rmk */ 0x31e4, /* VPSLLDZ256rrk */ /* Table7325 */ 0x299e, /* VPMADDWDZ256rmk */ 0x29a1, /* VPMADDWDZ256rrk */ /* Table7327 */ 0x346c, /* VPSUBBZ256rmk */ 0x346f, /* VPSUBBZ256rrk */ /* Table7329 */ 0x3518, /* VPSUBWZ256rmk */ 0x351b, /* VPSUBWZ256rrk */ /* Table7331 */ 0x3488, /* VPSUBDZ256rmk */ 0x348b, /* VPSUBDZ256rrk */ /* Table7333 */ 0x2106, /* VPADDBZ256rmk */ 0x2109, /* VPADDBZ256rrk */ /* Table7335 */ 0x21b2, /* VPADDWZ256rmk */ 0x21b5, /* VPADDWZ256rrk */ /* Table7337 */ 0x2122, /* VPADDDZ256rmk */ 0x2125, /* VPADDDZ256rrk */ /* Table7339 */ 0xfdd, /* VCVTQQ2PSZ256rmk */ 0xfe0, /* VCVTQQ2PSZ256rrk */ /* Table7341 */ 0x109d, /* VCVTTPD2UDQZ256rmk */ 0x10a0, /* VCVTTPD2UDQZ256rrk */ /* Table7343 */ 0xeb6, /* VCVTPD2UDQZ256rmk */ 0xeb9, /* VCVTPD2UDQZ256rrk */ /* Table7345 */ 0x1e56, /* VMOVDQU64Z256rmk */ 0x1e5a, /* VMOVDQU64Z256rrk */ /* Table7347 */ 0x11c6, /* VCVTUQQ2PDZ256rmk */ 0x11c9, /* VCVTUQQ2PDZ256rrk */ /* Table7349 */ 0x1e54, /* VMOVDQU64Z256mrk */ 0x1e5b, /* VMOVDQU64Z256rrk_REV */ /* Table7351 */ 0xfbf, /* VCVTQQ2PDZ256rmk */ 0xfc2, /* VCVTQQ2PDZ256rrk */ /* Table7353 */ 0x1da7, /* VMOVDDUPZ256rmk */ 0x1daa, /* VMOVDDUPZ256rrk */ /* Table7355 */ 0x1e14, /* VMOVDQU16Z256rmk */ 0x1e18, /* VMOVDQU16Z256rrk */ /* Table7357 */ 0x11e4, /* VCVTUQQ2PSZ256rmk */ 0x11e7, /* VCVTUQQ2PSZ256rrk */ /* Table7359 */ 0x1e12, /* VMOVDQU16Z256mrk */ 0x1e19, /* VMOVDQU16Z256rrk_REV */ /* Table7361 */ 0xe56, /* VCVTPD2DQZ256rmk */ 0xe59, /* VCVTPD2DQZ256rrk */ /* Table7363 */ 0x1f30, /* VMOVUPDZ256rmk */ 0x1f34, /* VMOVUPDZ256rrk */ /* Table7365 */ 0x1f2e, /* VMOVUPDZ256mrk */ 0x1f35, /* VMOVUPDZ256rrk_REV */ /* Table7367 */ 0x3adf, /* VUNPCKLPDZ256rmk */ 0x3ae2, /* VUNPCKLPDZ256rrk */ /* Table7369 */ 0x3aa1, /* VUNPCKHPDZ256rmk */ 0x3aa4, /* VUNPCKHPDZ256rrk */ /* Table7371 */ 0x1d5e, /* VMOVAPDZ256rmk */ 0x1d62, /* VMOVAPDZ256rrk */ /* Table7373 */ 0x1d5c, /* VMOVAPDZ256mrk */ 0x1d63, /* VMOVAPDZ256rrk_REV */ /* Table7375 */ 0x39c2, /* VSQRTPDZ256mk */ 0x39c5, /* VSQRTPDZ256rk */ /* Table7377 */ 0xc71, /* VANDPDZ256rmk */ 0xc74, /* VANDPDZ256rrk */ /* Table7379 */ 0xc33, /* VANDNPDZ256rmk */ 0xc36, /* VANDNPDZ256rrk */ /* Table7381 */ 0x1ff8, /* VORPDZ256rmk */ 0x1ffb, /* VORPDZ256rrk */ /* Table7383 */ 0x3b1d, /* VXORPDZ256rmk */ 0x3b20, /* VXORPDZ256rrk */ /* Table7385 */ 0xb67, /* VADDPDZ256rmk */ 0xb6a, /* VADDPDZ256rrk */ /* Table7387 */ 0x1f90, /* VMULPDZ256rmk */ 0x1f93, /* VMULPDZ256rrk */ /* Table7389 */ 0xe78, /* VCVTPD2PSZ256rmk */ 0xe7b, /* VCVTPD2PSZ256rrk */ /* Table7391 */ 0x3a25, /* VSUBPDZ256rmk */ 0x3a28, /* VSUBPDZ256rrk */ /* Table7393 */ 0x1ced, /* VMINPDZ256rmk */ 0x1cf0, /* VMINPDZ256rrk */ /* Table7395 */ 0x1229, /* VDIVPDZ256rmk */ 0x122c, /* VDIVPDZ256rrk */ /* Table7397 */ 0x1c42, /* VMAXPDZ256rmk */ 0x1c45, /* VMAXPDZ256rrk */ /* Table7399 */ 0x3685, /* VPUNPCKLQDQZ256rmk */ 0x3688, /* VPUNPCKLQDQZ256rrk */ /* Table7401 */ 0x361b, /* VPUNPCKHQDQZ256rmk */ 0x361e, /* VPUNPCKHQDQZ256rrk */ /* Table7403 */ 0x1deb, /* VMOVDQA64Z256rmk */ 0x1def, /* VMOVDQA64Z256rrk */ /* Table7405 */ 0x2f92, /* VPRORQZ256mik */ 0x2f26, /* VPROLQZ256mik */ 0x0, /* */ 0x0, /* */ 0x32eb, /* VPSRAQZ256mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f95, /* VPRORQZ256rik */ 0x2f29, /* VPROLQZ256rik */ 0x0, /* */ 0x0, /* */ 0x32ee, /* VPSRAQZ256rik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table7421 */ 0x0, /* */ 0x0, /* */ 0x33cc, /* VPSRLQZ256mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x320e, /* VPSLLQZ256mik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33cf, /* VPSRLQZ256rik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3211, /* VPSLLQZ256rik */ 0x0, /* */ /* Table7437 */ 0x10bb, /* VCVTTPD2UQQZ256rmk */ 0x10be, /* VCVTTPD2UQQZ256rrk */ /* Table7439 */ 0xed4, /* VCVTPD2UQQZ256rmk */ 0xed7, /* VCVTPD2UQQZ256rrk */ /* Table7441 */ 0x107f, /* VCVTTPD2QQZ256rmk */ 0x1082, /* VCVTTPD2QQZ256rrk */ /* Table7443 */ 0xe98, /* VCVTPD2QQZ256rmk */ 0xe9b, /* VCVTPD2QQZ256rrk */ /* Table7445 */ 0x1de9, /* VMOVDQA64Z256mrk */ 0x1df0, /* VMOVDQA64Z256rrk_REV */ /* Table7447 */ 0xd65, /* VCMPPDZ256rmik */ 0xd69, /* VCMPPDZ256rrik */ /* Table7449 */ 0x3984, /* VSHUFPDZ256rmik */ 0x3987, /* VSHUFPDZ256rrik */ /* Table7451 */ 0x33d2, /* VPSRLQZ256rmk */ 0x33d5, /* VPSRLQZ256rrk */ /* Table7453 */ 0x2141, /* VPADDQZ256rmk */ 0x2144, /* VPADDQZ256rrk */ /* Table7455 */ 0x2237, /* VPANDQZ256rmk */ 0x223a, /* VPANDQZ256rrk */ /* Table7457 */ 0x2218, /* VPANDNQZ256rmk */ 0x221b, /* VPANDNQZ256rrk */ /* Table7459 */ 0x32f1, /* VPSRAQZ256rmk */ 0x32f4, /* VPSRAQZ256rrk */ /* Table7461 */ 0x105f, /* VCVTTPD2DQZ256rmk */ 0x1062, /* VCVTTPD2DQZ256rrk */ /* Table7463 */ 0x2ee8, /* VPORQZ256rmk */ 0x2eeb, /* VPORQZ256rrk */ /* Table7465 */ 0x36d3, /* VPXORQZ256rmk */ 0x36d6, /* VPXORQZ256rrk */ /* Table7467 */ 0x3214, /* VPSLLQZ256rmk */ 0x3217, /* VPSLLQZ256rrk */ /* Table7469 */ 0x2e56, /* VPMULUDQZ256rmk */ 0x2e59, /* VPMULUDQZ256rrk */ /* Table7471 */ 0x34a7, /* VPSUBQZ256rmk */ 0x34aa, /* VPSUBQZ256rrk */ /* Table7473 */ 0x1f64, /* VMOVUPSZrmk */ 0x1f68, /* VMOVUPSZrrk */ /* Table7475 */ 0x1f62, /* VMOVUPSZmrk */ 0x1f69, /* VMOVUPSZrrk_REV */ /* Table7477 */ 0x3b07, /* VUNPCKLPSZrmk */ 0x3b0a, /* VUNPCKLPSZrrk */ /* Table7479 */ 0x3ac9, /* VUNPCKHPSZrmk */ 0x3acc, /* VUNPCKHPSZrrk */ /* Table7481 */ 0x1d92, /* VMOVAPSZrmk */ 0x1d96, /* VMOVAPSZrrk */ /* Table7483 */ 0x1d90, /* VMOVAPSZmrk */ 0x1d97, /* VMOVAPSZrrk_REV */ /* Table7485 */ 0x39ed, /* VSQRTPSZmk */ 0x39f3, /* VSQRTPSZrk */ /* Table7487 */ 0xc99, /* VANDPSZrmk */ 0xc9c, /* VANDPSZrrk */ /* Table7489 */ 0xc5b, /* VANDNPSZrmk */ 0xc5e, /* VANDNPSZrrk */ /* Table7491 */ 0x2020, /* VORPSZrmk */ 0x2023, /* VORPSZrrk */ /* Table7493 */ 0x3b45, /* VXORPSZrmk */ 0x3b48, /* VXORPSZrrk */ /* Table7495 */ 0xb92, /* VADDPSZrmk */ 0xb98, /* VADDPSZrrk */ /* Table7497 */ 0x1fbb, /* VMULPSZrmk */ 0x1fc1, /* VMULPSZrrk */ /* Table7499 */ 0xf38, /* VCVTPS2PDZrmk */ 0xf3e, /* VCVTPS2PDZrrk */ /* Table7501 */ 0xe3d, /* VCVTDQ2PSZrmk */ 0xe43, /* VCVTDQ2PSZrrk */ /* Table7503 */ 0x3a50, /* VSUBPSZrmk */ 0x3a56, /* VSUBPSZrrk */ /* Table7505 */ 0x1d18, /* VMINPSZrmk */ 0x1d1e, /* VMINPSZrrk */ /* Table7507 */ 0x1254, /* VDIVPSZrmk */ 0x125a, /* VDIVPSZrrk */ /* Table7509 */ 0x1c6d, /* VMAXPSZrmk */ 0x1c73, /* VMAXPSZrrk */ /* Table7511 */ 0x1122, /* VCVTTPS2UDQZrmk */ 0x1128, /* VCVTTPS2UDQZrrk */ /* Table7513 */ 0xf8c, /* VCVTPS2UDQZrmk */ 0xf92, /* VCVTPS2UDQZrrk */ /* Table7515 */ 0xda1, /* VCMPPSZrmik */ 0xda9, /* VCMPPSZrrik */ /* Table7517 */ 0x39ac, /* VSHUFPSZrmik */ 0x39af, /* VSHUFPSZrrik */ /* Table7519 */ 0x1f04, /* VMOVSLDUPZrmk */ 0x1f07, /* VMOVSLDUPZrrk */ /* Table7521 */ 0x1eee, /* VMOVSHDUPZrmk */ 0x1ef1, /* VMOVSHDUPZrrk */ /* Table7523 */ 0x10e4, /* VCVTTPS2DQZrmk */ 0x10ea, /* VCVTTPS2DQZrrk */ /* Table7525 */ 0x1e40, /* VMOVDQU32Zrmk */ 0x1e44, /* VMOVDQU32Zrrk */ /* Table7527 */ 0x3194, /* VPSHUFHWZmik */ 0x3197, /* VPSHUFHWZrik */ /* Table7529 */ 0x1196, /* VCVTUDQ2PDZrmk */ 0x1199, /* VCVTUDQ2PDZrrk */ /* Table7531 */ 0x1e3e, /* VMOVDQU32Zmrk */ 0x1e45, /* VMOVDQU32Zrrk_REV */ /* Table7533 */ 0xe1e, /* VCVTDQ2PDZrmk */ 0xe21, /* VCVTDQ2PDZrrk */ /* Table7535 */ 0x1e82, /* VMOVDQU8Zrmk */ 0x1e86, /* VMOVDQU8Zrrk */ /* Table7537 */ 0x31aa, /* VPSHUFLWZmik */ 0x31ad, /* VPSHUFLWZrik */ /* Table7539 */ 0x11b1, /* VCVTUDQ2PSZrmk */ 0x11b7, /* VCVTUDQ2PSZrrk */ /* Table7541 */ 0x1e80, /* VMOVDQU8Zmrk */ 0x1e87, /* VMOVDQU8Zrrk_REV */ /* Table7543 */ 0xf16, /* VCVTPS2DQZrmk */ 0xf1c, /* VCVTPS2DQZrrk */ /* Table7545 */ 0x3650, /* VPUNPCKLBWZrmk */ 0x3653, /* VPUNPCKLBWZrrk */ /* Table7547 */ 0x36a4, /* VPUNPCKLWDZrmk */ 0x36a7, /* VPUNPCKLWDZrrk */ /* Table7549 */ 0x366f, /* VPUNPCKLDQZrmk */ 0x3672, /* VPUNPCKLDQZrrk */ /* Table7551 */ 0x20c1, /* VPACKSSWBZrmk */ 0x20c4, /* VPACKSSWBZrrk */ /* Table7553 */ 0x2406, /* VPCMPGTBZrmk */ 0x2408, /* VPCMPGTBZrrk */ /* Table7555 */ 0x2442, /* VPCMPGTWZrmk */ 0x2444, /* VPCMPGTWZrrk */ /* Table7557 */ 0x241c, /* VPCMPGTDZrmk */ 0x241e, /* VPCMPGTDZrrk */ /* Table7559 */ 0x20f6, /* VPACKUSWBZrmk */ 0x20f9, /* VPACKUSWBZrrk */ /* Table7561 */ 0x35e6, /* VPUNPCKHBWZrmk */ 0x35e9, /* VPUNPCKHBWZrrk */ /* Table7563 */ 0x363a, /* VPUNPCKHWDZrmk */ 0x363d, /* VPUNPCKHWDZrrk */ /* Table7565 */ 0x3605, /* VPUNPCKHDQZrmk */ 0x3608, /* VPUNPCKHDQZrrk */ /* Table7567 */ 0x20ab, /* VPACKSSDWZrmk */ 0x20ae, /* VPACKSSDWZrrk */ /* Table7569 */ 0x1dd5, /* VMOVDQA32Zrmk */ 0x1dd9, /* VMOVDQA32Zrrk */ /* Table7571 */ 0x317e, /* VPSHUFDZmik */ 0x3181, /* VPSHUFDZrik */ /* Table7573 */ 0x0, /* */ 0x0, /* */ 0x3455, /* VPSRLWZmik */ 0x0, /* */ 0x336d, /* VPSRAWZmik */ 0x0, /* */ 0x3297, /* VPSLLWZmik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3458, /* VPSRLWZrik */ 0x0, /* */ 0x3370, /* VPSRAWZrik */ 0x0, /* */ 0x329a, /* VPSLLWZrik */ 0x0, /* */ /* Table7589 */ 0x2f80, /* VPRORDZmik */ 0x2f14, /* VPROLDZmik */ 0x33a8, /* VPSRLDZmik */ 0x0, /* */ 0x32ca, /* VPSRADZmik */ 0x0, /* */ 0x31ea, /* VPSLLDZmik */ 0x0, /* */ 0x2f83, /* VPRORDZrik */ 0x2f17, /* VPROLDZrik */ 0x33ab, /* VPSRLDZrik */ 0x0, /* */ 0x32cd, /* VPSRADZrik */ 0x0, /* */ 0x31ed, /* VPSLLDZrik */ 0x0, /* */ /* Table7605 */ 0x23b6, /* VPCMPEQBZrmk */ 0x23b8, /* VPCMPEQBZrrk */ /* Table7607 */ 0x23f2, /* VPCMPEQWZrmk */ 0x23f4, /* VPCMPEQWZrrk */ /* Table7609 */ 0x23cc, /* VPCMPEQDZrmk */ 0x23ce, /* VPCMPEQDZrrk */ /* Table7611 */ 0x1140, /* VCVTTPS2UQQZrmk */ 0x1146, /* VCVTTPS2UQQZrrk */ /* Table7613 */ 0xfaa, /* VCVTPS2UQQZrmk */ 0xfb0, /* VCVTPS2UQQZrrk */ /* Table7615 */ 0x1104, /* VCVTTPS2QQZrmk */ 0x110a, /* VCVTTPS2QQZrrk */ /* Table7617 */ 0xf6e, /* VCVTPS2QQZrmk */ 0xf74, /* VCVTPS2QQZrrk */ /* Table7619 */ 0x1dd3, /* VMOVDQA32Zmrk */ 0x1dda, /* VMOVDQA32Zrrk_REV */ /* Table7621 */ 0x345b, /* VPSRLWZrmk */ 0x345e, /* VPSRLWZrrk */ /* Table7623 */ 0x33ae, /* VPSRLDZrmk */ 0x33b1, /* VPSRLDZrrk */ /* Table7625 */ 0x2e25, /* VPMULLWZrmk */ 0x2e28, /* VPMULLWZrrk */ /* Table7627 */ 0x34f2, /* VPSUBUSBZrmk */ 0x34f5, /* VPSUBUSBZrrk */ /* Table7629 */ 0x3508, /* VPSUBUSWZrmk */ 0x350b, /* VPSUBUSWZrrk */ /* Table7631 */ 0x2af4, /* VPMINUBZrmk */ 0x2af7, /* VPMINUBZrrk */ /* Table7633 */ 0x21eb, /* VPANDDZrmk */ 0x21ee, /* VPANDDZrrk */ /* Table7635 */ 0x218c, /* VPADDUSBZrmk */ 0x218f, /* VPADDUSBZrrk */ /* Table7637 */ 0x21a2, /* VPADDUSWZrmk */ 0x21a5, /* VPADDUSWZrrk */ /* Table7639 */ 0x2a28, /* VPMAXUBZrmk */ 0x2a2b, /* VPMAXUBZrrk */ /* Table7641 */ 0x2206, /* VPANDNDZrmk */ 0x2209, /* VPANDNDZrrk */ /* Table7643 */ 0x2258, /* VPAVGBZrmk */ 0x225b, /* VPAVGBZrrk */ /* Table7645 */ 0x3373, /* VPSRAWZrmk */ 0x3376, /* VPSRAWZrrk */ /* Table7647 */ 0x32d0, /* VPSRADZrmk */ 0x32d3, /* VPSRADZrrk */ /* Table7649 */ 0x226e, /* VPAVGWZrmk */ 0x2271, /* VPAVGWZrrk */ /* Table7651 */ 0x2dbf, /* VPMULHUWZrmk */ 0x2dc2, /* VPMULHUWZrrk */ /* Table7653 */ 0x2dd5, /* VPMULHWZrmk */ 0x2dd8, /* VPMULHWZrrk */ /* Table7655 */ 0x34c6, /* VPSUBSBZrmk */ 0x34c9, /* VPSUBSBZrrk */ /* Table7657 */ 0x34dc, /* VPSUBSWZrmk */ 0x34df, /* VPSUBSWZrrk */ /* Table7659 */ 0x2ade, /* VPMINSWZrmk */ 0x2ae1, /* VPMINSWZrrk */ /* Table7661 */ 0x2ed6, /* VPORDZrmk */ 0x2ed9, /* VPORDZrrk */ /* Table7663 */ 0x2160, /* VPADDSBZrmk */ 0x2163, /* VPADDSBZrrk */ /* Table7665 */ 0x2176, /* VPADDSWZrmk */ 0x2179, /* VPADDSWZrrk */ /* Table7667 */ 0x2a12, /* VPMAXSWZrmk */ 0x2a15, /* VPMAXSWZrrk */ /* Table7669 */ 0x36c1, /* VPXORDZrmk */ 0x36c4, /* VPXORDZrrk */ /* Table7671 */ 0x329d, /* VPSLLWZrmk */ 0x32a0, /* VPSLLWZrrk */ /* Table7673 */ 0x31f0, /* VPSLLDZrmk */ 0x31f3, /* VPSLLDZrrk */ /* Table7675 */ 0x29a4, /* VPMADDWDZrmk */ 0x29a7, /* VPMADDWDZrrk */ /* Table7677 */ 0x3472, /* VPSUBBZrmk */ 0x3475, /* VPSUBBZrrk */ /* Table7679 */ 0x351e, /* VPSUBWZrmk */ 0x3521, /* VPSUBWZrrk */ /* Table7681 */ 0x3491, /* VPSUBDZrmk */ 0x3494, /* VPSUBDZrrk */ /* Table7683 */ 0x210c, /* VPADDBZrmk */ 0x210f, /* VPADDBZrrk */ /* Table7685 */ 0x21b8, /* VPADDWZrmk */ 0x21bb, /* VPADDWZrrk */ /* Table7687 */ 0x212b, /* VPADDDZrmk */ 0x212e, /* VPADDDZrrk */ /* Table7689 */ 0xfe6, /* VCVTQQ2PSZrmk */ 0xfec, /* VCVTQQ2PSZrrk */ /* Table7691 */ 0x10a6, /* VCVTTPD2UDQZrmk */ 0x10ac, /* VCVTTPD2UDQZrrk */ /* Table7693 */ 0xebf, /* VCVTPD2UDQZrmk */ 0xec5, /* VCVTPD2UDQZrrk */ /* Table7695 */ 0x1e61, /* VMOVDQU64Zrmk */ 0x1e65, /* VMOVDQU64Zrrk */ /* Table7697 */ 0x11cf, /* VCVTUQQ2PDZrmk */ 0x11d5, /* VCVTUQQ2PDZrrk */ /* Table7699 */ 0x1e5f, /* VMOVDQU64Zmrk */ 0x1e66, /* VMOVDQU64Zrrk_REV */ /* Table7701 */ 0xfc8, /* VCVTQQ2PDZrmk */ 0xfce, /* VCVTQQ2PDZrrk */ /* Table7703 */ 0x1dad, /* VMOVDDUPZrmk */ 0x1db0, /* VMOVDDUPZrrk */ /* Table7705 */ 0x1e1f, /* VMOVDQU16Zrmk */ 0x1e23, /* VMOVDQU16Zrrk */ /* Table7707 */ 0x11ed, /* VCVTUQQ2PSZrmk */ 0x11f3, /* VCVTUQQ2PSZrrk */ /* Table7709 */ 0x1e1d, /* VMOVDQU16Zmrk */ 0x1e24, /* VMOVDQU16Zrrk_REV */ /* Table7711 */ 0xe5f, /* VCVTPD2DQZrmk */ 0xe65, /* VCVTPD2DQZrrk */ /* Table7713 */ 0x1f3b, /* VMOVUPDZrmk */ 0x1f3f, /* VMOVUPDZrrk */ /* Table7715 */ 0x1f39, /* VMOVUPDZmrk */ 0x1f40, /* VMOVUPDZrrk_REV */ /* Table7717 */ 0x3ae8, /* VUNPCKLPDZrmk */ 0x3aeb, /* VUNPCKLPDZrrk */ /* Table7719 */ 0x3aaa, /* VUNPCKHPDZrmk */ 0x3aad, /* VUNPCKHPDZrrk */ /* Table7721 */ 0x1d69, /* VMOVAPDZrmk */ 0x1d6d, /* VMOVAPDZrrk */ /* Table7723 */ 0x1d67, /* VMOVAPDZmrk */ 0x1d6e, /* VMOVAPDZrrk_REV */ /* Table7725 */ 0x39cb, /* VSQRTPDZmk */ 0x39d1, /* VSQRTPDZrk */ /* Table7727 */ 0xc7a, /* VANDPDZrmk */ 0xc7d, /* VANDPDZrrk */ /* Table7729 */ 0xc3c, /* VANDNPDZrmk */ 0xc3f, /* VANDNPDZrrk */ /* Table7731 */ 0x2001, /* VORPDZrmk */ 0x2004, /* VORPDZrrk */ /* Table7733 */ 0x3b26, /* VXORPDZrmk */ 0x3b29, /* VXORPDZrrk */ /* Table7735 */ 0xb70, /* VADDPDZrmk */ 0xb76, /* VADDPDZrrk */ /* Table7737 */ 0x1f99, /* VMULPDZrmk */ 0x1f9f, /* VMULPDZrrk */ /* Table7739 */ 0xe81, /* VCVTPD2PSZrmk */ 0xe87, /* VCVTPD2PSZrrk */ /* Table7741 */ 0x3a2e, /* VSUBPDZrmk */ 0x3a34, /* VSUBPDZrrk */ /* Table7743 */ 0x1cf6, /* VMINPDZrmk */ 0x1cfc, /* VMINPDZrrk */ /* Table7745 */ 0x1232, /* VDIVPDZrmk */ 0x1238, /* VDIVPDZrrk */ /* Table7747 */ 0x1c4b, /* VMAXPDZrmk */ 0x1c51, /* VMAXPDZrrk */ /* Table7749 */ 0x368e, /* VPUNPCKLQDQZrmk */ 0x3691, /* VPUNPCKLQDQZrrk */ /* Table7751 */ 0x3624, /* VPUNPCKHQDQZrmk */ 0x3627, /* VPUNPCKHQDQZrrk */ /* Table7753 */ 0x1df6, /* VMOVDQA64Zrmk */ 0x1dfa, /* VMOVDQA64Zrrk */ /* Table7755 */ 0x2f9b, /* VPRORQZmik */ 0x2f2f, /* VPROLQZmik */ 0x0, /* */ 0x0, /* */ 0x32fa, /* VPSRAQZmik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f9e, /* VPRORQZrik */ 0x2f32, /* VPROLQZrik */ 0x0, /* */ 0x0, /* */ 0x32fd, /* VPSRAQZrik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table7771 */ 0x0, /* */ 0x0, /* */ 0x33db, /* VPSRLQZmik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x321d, /* VPSLLQZmik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33de, /* VPSRLQZrik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3220, /* VPSLLQZrik */ 0x0, /* */ /* Table7787 */ 0x10c4, /* VCVTTPD2UQQZrmk */ 0x10ca, /* VCVTTPD2UQQZrrk */ /* Table7789 */ 0xedd, /* VCVTPD2UQQZrmk */ 0xee3, /* VCVTPD2UQQZrrk */ /* Table7791 */ 0x1088, /* VCVTTPD2QQZrmk */ 0x108e, /* VCVTTPD2QQZrrk */ /* Table7793 */ 0xea1, /* VCVTPD2QQZrmk */ 0xea7, /* VCVTPD2QQZrrk */ /* Table7795 */ 0x1df4, /* VMOVDQA64Zmrk */ 0x1dfb, /* VMOVDQA64Zrrk_REV */ /* Table7797 */ 0xd71, /* VCMPPDZrmik */ 0xd79, /* VCMPPDZrrik */ /* Table7799 */ 0x398d, /* VSHUFPDZrmik */ 0x3990, /* VSHUFPDZrrik */ /* Table7801 */ 0x33e1, /* VPSRLQZrmk */ 0x33e4, /* VPSRLQZrrk */ /* Table7803 */ 0x214a, /* VPADDQZrmk */ 0x214d, /* VPADDQZrrk */ /* Table7805 */ 0x2240, /* VPANDQZrmk */ 0x2243, /* VPANDQZrrk */ /* Table7807 */ 0x2221, /* VPANDNQZrmk */ 0x2224, /* VPANDNQZrrk */ /* Table7809 */ 0x3300, /* VPSRAQZrmk */ 0x3303, /* VPSRAQZrrk */ /* Table7811 */ 0x1068, /* VCVTTPD2DQZrmk */ 0x106e, /* VCVTTPD2DQZrrk */ /* Table7813 */ 0x2ef1, /* VPORQZrmk */ 0x2ef4, /* VPORQZrrk */ /* Table7815 */ 0x36dc, /* VPXORQZrmk */ 0x36df, /* VPXORQZrrk */ /* Table7817 */ 0x3223, /* VPSLLQZrmk */ 0x3226, /* VPSLLQZrrk */ /* Table7819 */ 0x2e5f, /* VPMULUDQZrmk */ 0x2e62, /* VPMULUDQZrrk */ /* Table7821 */ 0x34b0, /* VPSUBQZrmk */ 0x34b3, /* VPSUBQZrrk */ /* Table7823 */ 0x3af2, /* VUNPCKLPSZ128rmb */ 0x0, /* */ /* Table7825 */ 0x3ab4, /* VUNPCKHPSZ128rmb */ 0x0, /* */ /* Table7827 */ 0x0, /* */ 0x3a8d, /* VUCOMISSZrrb */ /* Table7829 */ 0x0, /* */ 0xde3, /* VCOMISSZrrb */ /* Table7831 */ 0x39d8, /* VSQRTPSZ128mb */ 0x39f0, /* VSQRTPSZrb */ /* Table7833 */ 0xc84, /* VANDPSZ128rmb */ 0x0, /* */ /* Table7835 */ 0xc46, /* VANDNPSZ128rmb */ 0x0, /* */ /* Table7837 */ 0x200b, /* VORPSZ128rmb */ 0x0, /* */ /* Table7839 */ 0x3b30, /* VXORPSZ128rmb */ 0x0, /* */ /* Table7841 */ 0xb7d, /* VADDPSZ128rmb */ 0xb95, /* VADDPSZrrb */ /* Table7843 */ 0x1fa6, /* VMULPSZ128rmb */ 0x1fbe, /* VMULPSZrrb */ /* Table7845 */ 0xf23, /* VCVTPS2PDZ128rmb */ 0xf3b, /* VCVTPS2PDZrrb */ /* Table7847 */ 0xe28, /* VCVTDQ2PSZ128rmb */ 0xe40, /* VCVTDQ2PSZrrb */ /* Table7849 */ 0x3a3b, /* VSUBPSZ128rmb */ 0x3a53, /* VSUBPSZrrb */ /* Table7851 */ 0x1d03, /* VMINPSZ128rmb */ 0x1d1b, /* VMINPSZrrb */ /* Table7853 */ 0x123f, /* VDIVPSZ128rmb */ 0x1257, /* VDIVPSZrrb */ /* Table7855 */ 0x1c58, /* VMAXPSZ128rmb */ 0x1c70, /* VMAXPSZrrb */ /* Table7857 */ 0x110d, /* VCVTTPS2UDQZ128rmb */ 0x1125, /* VCVTTPS2UDQZrrb */ /* Table7859 */ 0xf77, /* VCVTPS2UDQZ128rmb */ 0xf8f, /* VCVTPS2UDQZrrb */ /* Table7861 */ 0xd82, /* VCMPPSZ128rmbi */ 0xda5, /* VCMPPSZrrib */ /* Table7863 */ 0x3996, /* VSHUFPSZ128rmbi */ 0x0, /* */ /* Table7865 */ 0x0, /* */ 0x101a, /* VCVTSI2SSZrrb_Int */ /* Table7867 */ 0x0, /* */ 0x1171, /* VCVTTSS2SIZrrb_Int */ /* Table7869 */ 0x0, /* */ 0x1047, /* VCVTSS2SIZrrb_Int */ /* Table7871 */ 0x0, /* */ 0x3a0e, /* VSQRTSSZrb_Int */ /* Table7873 */ 0x0, /* */ 0xbb3, /* VADDSSZrrb_Int */ /* Table7875 */ 0x0, /* */ 0x1fdc, /* VMULSSZrrb_Int */ /* Table7877 */ 0x0, /* */ 0x1039, /* VCVTSS2SDZrrb_Int */ /* Table7879 */ 0x10cf, /* VCVTTPS2DQZ128rmb */ 0x10e7, /* VCVTTPS2DQZrrb */ /* Table7881 */ 0x0, /* */ 0x3a71, /* VSUBSSZrrb_Int */ /* Table7883 */ 0x0, /* */ 0x1d39, /* VMINSSZrrb_Int */ /* Table7885 */ 0x0, /* */ 0x1275, /* VDIVSSZrrb_Int */ /* Table7887 */ 0x0, /* */ 0x1c8e, /* VMAXSSZrrb_Int */ /* Table7889 */ 0x0, /* */ 0x117f, /* VCVTTSS2USIZrrb_Int */ /* Table7891 */ 0x0, /* */ 0x104f, /* VCVTSS2USIZrrb_Int */ /* Table7893 */ 0x1181, /* VCVTUDQ2PDZ128rmb */ 0x0, /* */ /* Table7895 */ 0x0, /* */ 0x11fd, /* VCVTUSI2SSZrrb_Int */ /* Table7897 */ 0x0, /* */ 0xdca, /* VCMPSSZrrb_Int */ /* Table7899 */ 0xe09, /* VCVTDQ2PDZ128rmb */ 0x0, /* */ /* Table7901 */ 0x0, /* */ 0x1011, /* VCVTSI2SDZrrb_Int */ /* Table7903 */ 0x0, /* */ 0x1155, /* VCVTTSD2SIZrrb_Int */ /* Table7905 */ 0x0, /* */ 0xff5, /* VCVTSD2SIZrrb_Int */ /* Table7907 */ 0x0, /* */ 0x1163, /* VCVTTSD2USIZrrb_Int */ /* Table7909 */ 0x0, /* */ 0x100c, /* VCVTSD2USIZrrb_Int */ /* Table7911 */ 0x119c, /* VCVTUDQ2PSZ128rmb */ 0x11b4, /* VCVTUDQ2PSZrrb */ /* Table7913 */ 0xf01, /* VCVTPS2DQZ128rmb */ 0xf19, /* VCVTPS2DQZrrb */ /* Table7915 */ 0x365a, /* VPUNPCKLDQZ128rmb */ 0x0, /* */ /* Table7917 */ 0x240e, /* VPCMPGTDZ128rmb */ 0x0, /* */ /* Table7919 */ 0x35f0, /* VPUNPCKHDQZ128rmb */ 0x0, /* */ /* Table7921 */ 0x2096, /* VPACKSSDWZ128rmb */ 0x0, /* */ /* Table7923 */ 0x3168, /* VPSHUFDZ128mbi */ 0x0, /* */ /* Table7925 */ 0x2f6a, /* VPRORDZ128mbi */ 0x2efe, /* VPROLDZ128mbi */ 0x3386, /* VPSRLDZ128mbi */ 0x0, /* */ 0x32a8, /* VPSRADZ128mbi */ 0x0, /* */ 0x31c8, /* VPSLLDZ128mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table7941 */ 0x23be, /* VPCMPEQDZ128rmb */ 0x0, /* */ /* Table7943 */ 0x112b, /* VCVTTPS2UQQZ128rmb */ 0x1143, /* VCVTTPS2UQQZrrb */ /* Table7945 */ 0xf95, /* VCVTPS2UQQZ128rmb */ 0xfad, /* VCVTPS2UQQZrrb */ /* Table7947 */ 0x10ef, /* VCVTTPS2QQZ128rmb */ 0x1107, /* VCVTTPS2QQZrrb */ /* Table7949 */ 0xf59, /* VCVTPS2QQZ128rmb */ 0xf71, /* VCVTPS2QQZrrb */ /* Table7951 */ 0x21d6, /* VPANDDZ128rmb */ 0x0, /* */ /* Table7953 */ 0x21f1, /* VPANDNDZ128rmb */ 0x0, /* */ /* Table7955 */ 0x2ec1, /* VPORDZ128rmb */ 0x0, /* */ /* Table7957 */ 0x36ac, /* VPXORDZ128rmb */ 0x0, /* */ /* Table7959 */ 0x347c, /* VPSUBDZ128rmb */ 0x0, /* */ /* Table7961 */ 0x2116, /* VPADDDZ128rmb */ 0x0, /* */ /* Table7963 */ 0xfd1, /* VCVTQQ2PSZ128rmb */ 0xfe9, /* VCVTQQ2PSZrrb */ /* Table7965 */ 0x1091, /* VCVTTPD2UDQZ128rmb */ 0x10a9, /* VCVTTPD2UDQZrrb */ /* Table7967 */ 0xeaa, /* VCVTPD2UDQZ128rmb */ 0xec2, /* VCVTPD2UDQZrrb */ /* Table7969 */ 0x0, /* */ 0x102c, /* VCVTSI642SSZrrb_Int */ /* Table7971 */ 0x0, /* */ 0x1168, /* VCVTTSS2SI64Zrrb_Int */ /* Table7973 */ 0x0, /* */ 0x1042, /* VCVTSS2SI64Zrrb_Int */ /* Table7975 */ 0x0, /* */ 0x117a, /* VCVTTSS2USI64Zrrb_Int */ /* Table7977 */ 0x0, /* */ 0x104c, /* VCVTSS2USI64Zrrb_Int */ /* Table7979 */ 0x11ba, /* VCVTUQQ2PDZ128rmb */ 0x11d2, /* VCVTUQQ2PDZrrb */ /* Table7981 */ 0x0, /* */ 0x1207, /* VCVTUSI642SSZrrb_Int */ /* Table7983 */ 0xfb3, /* VCVTQQ2PDZ128rmb */ 0xfcb, /* VCVTQQ2PDZrrb */ /* Table7985 */ 0x0, /* */ 0x1023, /* VCVTSI642SDZrrb_Int */ /* Table7987 */ 0x0, /* */ 0x114c, /* VCVTTSD2SI64Zrrb_Int */ /* Table7989 */ 0x0, /* */ 0xff0, /* VCVTSD2SI64Zrrb_Int */ /* Table7991 */ 0x0, /* */ 0x39ff, /* VSQRTSDZrb_Int */ /* Table7993 */ 0x0, /* */ 0xba4, /* VADDSDZrrb_Int */ /* Table7995 */ 0x0, /* */ 0x1fcd, /* VMULSDZrrb_Int */ /* Table7997 */ 0x0, /* */ 0x1000, /* VCVTSD2SSZrrb_Int */ /* Table7999 */ 0x0, /* */ 0x3a62, /* VSUBSDZrrb_Int */ /* Table8001 */ 0x0, /* */ 0x1d2a, /* VMINSDZrrb_Int */ /* Table8003 */ 0x0, /* */ 0x1266, /* VDIVSDZrrb_Int */ /* Table8005 */ 0x0, /* */ 0x1c7f, /* VMAXSDZrrb_Int */ /* Table8007 */ 0x0, /* */ 0x115e, /* VCVTTSD2USI64Zrrb_Int */ /* Table8009 */ 0x0, /* */ 0x1009, /* VCVTSD2USI64Zrrb_Int */ /* Table8011 */ 0x11d8, /* VCVTUQQ2PSZ128rmb */ 0x11f0, /* VCVTUQQ2PSZrrb */ /* Table8013 */ 0x0, /* */ 0x1202, /* VCVTUSI642SDZrrb_Int */ /* Table8015 */ 0x0, /* */ 0xdb6, /* VCMPSDZrrb_Int */ /* Table8017 */ 0xe4a, /* VCVTPD2DQZ128rmb */ 0xe62, /* VCVTPD2DQZrrb */ /* Table8019 */ 0x3ad3, /* VUNPCKLPDZ128rmb */ 0x0, /* */ /* Table8021 */ 0x3a95, /* VUNPCKHPDZ128rmb */ 0x0, /* */ /* Table8023 */ 0x0, /* */ 0x3a84, /* VUCOMISDZrrb */ /* Table8025 */ 0x0, /* */ 0xdda, /* VCOMISDZrrb */ /* Table8027 */ 0x39b6, /* VSQRTPDZ128mb */ 0x39ce, /* VSQRTPDZrb */ /* Table8029 */ 0xc65, /* VANDPDZ128rmb */ 0x0, /* */ /* Table8031 */ 0xc27, /* VANDNPDZ128rmb */ 0x0, /* */ /* Table8033 */ 0x1fec, /* VORPDZ128rmb */ 0x0, /* */ /* Table8035 */ 0x3b11, /* VXORPDZ128rmb */ 0x0, /* */ /* Table8037 */ 0xb5b, /* VADDPDZ128rmb */ 0xb73, /* VADDPDZrrb */ /* Table8039 */ 0x1f84, /* VMULPDZ128rmb */ 0x1f9c, /* VMULPDZrrb */ /* Table8041 */ 0xe6c, /* VCVTPD2PSZ128rmb */ 0xe84, /* VCVTPD2PSZrrb */ /* Table8043 */ 0x3a19, /* VSUBPDZ128rmb */ 0x3a31, /* VSUBPDZrrb */ /* Table8045 */ 0x1ce1, /* VMINPDZ128rmb */ 0x1cf9, /* VMINPDZrrb */ /* Table8047 */ 0x121d, /* VDIVPDZ128rmb */ 0x1235, /* VDIVPDZrrb */ /* Table8049 */ 0x1c36, /* VMAXPDZ128rmb */ 0x1c4e, /* VMAXPDZrrb */ /* Table8051 */ 0x3679, /* VPUNPCKLQDQZ128rmb */ 0x0, /* */ /* Table8053 */ 0x360f, /* VPUNPCKHQDQZ128rmb */ 0x0, /* */ /* Table8055 */ 0x2f85, /* VPRORQZ128mbi */ 0x2f19, /* VPROLQZ128mbi */ 0x0, /* */ 0x0, /* */ 0x32d8, /* VPSRAQZ128mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8071 */ 0x0, /* */ 0x0, /* */ 0x33b9, /* VPSRLQZ128mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31fb, /* VPSLLQZ128mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8087 */ 0x10af, /* VCVTTPD2UQQZ128rmb */ 0x10c7, /* VCVTTPD2UQQZrrb */ /* Table8089 */ 0xec8, /* VCVTPD2UQQZ128rmb */ 0xee0, /* VCVTPD2UQQZrrb */ /* Table8091 */ 0x1073, /* VCVTTPD2QQZ128rmb */ 0x108b, /* VCVTTPD2QQZrrb */ /* Table8093 */ 0xe8c, /* VCVTPD2QQZ128rmb */ 0xea4, /* VCVTPD2QQZrrb */ /* Table8095 */ 0xd52, /* VCMPPDZ128rmbi */ 0xd75, /* VCMPPDZrrib */ /* Table8097 */ 0x3977, /* VSHUFPDZ128rmbi */ 0x0, /* */ /* Table8099 */ 0x2135, /* VPADDQZ128rmb */ 0x0, /* */ /* Table8101 */ 0x222b, /* VPANDQZ128rmb */ 0x0, /* */ /* Table8103 */ 0x220c, /* VPANDNQZ128rmb */ 0x0, /* */ /* Table8105 */ 0x1053, /* VCVTTPD2DQZ128rmb */ 0x106b, /* VCVTTPD2DQZrrb */ /* Table8107 */ 0x2edc, /* VPORQZ128rmb */ 0x0, /* */ /* Table8109 */ 0x36c7, /* VPXORQZ128rmb */ 0x0, /* */ /* Table8111 */ 0x2e4a, /* VPMULUDQZ128rmb */ 0x0, /* */ /* Table8113 */ 0x349b, /* VPSUBQZ128rmb */ 0x0, /* */ /* Table8115 */ 0x3afb, /* VUNPCKLPSZ256rmb */ 0x0, /* */ /* Table8117 */ 0x3abd, /* VUNPCKHPSZ256rmb */ 0x0, /* */ /* Table8119 */ 0x39e1, /* VSQRTPSZ256mb */ 0x39f0, /* VSQRTPSZrb */ /* Table8121 */ 0xc8d, /* VANDPSZ256rmb */ 0x0, /* */ /* Table8123 */ 0xc4f, /* VANDNPSZ256rmb */ 0x0, /* */ /* Table8125 */ 0x2014, /* VORPSZ256rmb */ 0x0, /* */ /* Table8127 */ 0x3b39, /* VXORPSZ256rmb */ 0x0, /* */ /* Table8129 */ 0xb86, /* VADDPSZ256rmb */ 0xb95, /* VADDPSZrrb */ /* Table8131 */ 0x1faf, /* VMULPSZ256rmb */ 0x1fbe, /* VMULPSZrrb */ /* Table8133 */ 0xf2c, /* VCVTPS2PDZ256rmb */ 0xf3b, /* VCVTPS2PDZrrb */ /* Table8135 */ 0xe31, /* VCVTDQ2PSZ256rmb */ 0xe40, /* VCVTDQ2PSZrrb */ /* Table8137 */ 0x3a44, /* VSUBPSZ256rmb */ 0x3a53, /* VSUBPSZrrb */ /* Table8139 */ 0x1d0c, /* VMINPSZ256rmb */ 0x1d1b, /* VMINPSZrrb */ /* Table8141 */ 0x1248, /* VDIVPSZ256rmb */ 0x1257, /* VDIVPSZrrb */ /* Table8143 */ 0x1c61, /* VMAXPSZ256rmb */ 0x1c70, /* VMAXPSZrrb */ /* Table8145 */ 0x1116, /* VCVTTPS2UDQZ256rmb */ 0x1125, /* VCVTTPS2UDQZrrb */ /* Table8147 */ 0xf80, /* VCVTPS2UDQZ256rmb */ 0xf8f, /* VCVTPS2UDQZrrb */ /* Table8149 */ 0xd8e, /* VCMPPSZ256rmbi */ 0xda5, /* VCMPPSZrrib */ /* Table8151 */ 0x399f, /* VSHUFPSZ256rmbi */ 0x0, /* */ /* Table8153 */ 0x10d8, /* VCVTTPS2DQZ256rmb */ 0x10e7, /* VCVTTPS2DQZrrb */ /* Table8155 */ 0x118a, /* VCVTUDQ2PDZ256rmb */ 0x0, /* */ /* Table8157 */ 0xe12, /* VCVTDQ2PDZ256rmb */ 0x0, /* */ /* Table8159 */ 0x11a5, /* VCVTUDQ2PSZ256rmb */ 0x11b4, /* VCVTUDQ2PSZrrb */ /* Table8161 */ 0xf0a, /* VCVTPS2DQZ256rmb */ 0xf19, /* VCVTPS2DQZrrb */ /* Table8163 */ 0x3663, /* VPUNPCKLDQZ256rmb */ 0x0, /* */ /* Table8165 */ 0x2414, /* VPCMPGTDZ256rmb */ 0x0, /* */ /* Table8167 */ 0x35f9, /* VPUNPCKHDQZ256rmb */ 0x0, /* */ /* Table8169 */ 0x209f, /* VPACKSSDWZ256rmb */ 0x0, /* */ /* Table8171 */ 0x3171, /* VPSHUFDZ256mbi */ 0x0, /* */ /* Table8173 */ 0x2f73, /* VPRORDZ256mbi */ 0x2f07, /* VPROLDZ256mbi */ 0x3395, /* VPSRLDZ256mbi */ 0x0, /* */ 0x32b7, /* VPSRADZ256mbi */ 0x0, /* */ 0x31d7, /* VPSLLDZ256mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8189 */ 0x23c4, /* VPCMPEQDZ256rmb */ 0x0, /* */ /* Table8191 */ 0x1134, /* VCVTTPS2UQQZ256rmb */ 0x1143, /* VCVTTPS2UQQZrrb */ /* Table8193 */ 0xf9e, /* VCVTPS2UQQZ256rmb */ 0xfad, /* VCVTPS2UQQZrrb */ /* Table8195 */ 0x10f8, /* VCVTTPS2QQZ256rmb */ 0x1107, /* VCVTTPS2QQZrrb */ /* Table8197 */ 0xf62, /* VCVTPS2QQZ256rmb */ 0xf71, /* VCVTPS2QQZrrb */ /* Table8199 */ 0x21df, /* VPANDDZ256rmb */ 0x0, /* */ /* Table8201 */ 0x21fa, /* VPANDNDZ256rmb */ 0x0, /* */ /* Table8203 */ 0x2eca, /* VPORDZ256rmb */ 0x0, /* */ /* Table8205 */ 0x36b5, /* VPXORDZ256rmb */ 0x0, /* */ /* Table8207 */ 0x3485, /* VPSUBDZ256rmb */ 0x0, /* */ /* Table8209 */ 0x211f, /* VPADDDZ256rmb */ 0x0, /* */ /* Table8211 */ 0xfda, /* VCVTQQ2PSZ256rmb */ 0xfe9, /* VCVTQQ2PSZrrb */ /* Table8213 */ 0x109a, /* VCVTTPD2UDQZ256rmb */ 0x10a9, /* VCVTTPD2UDQZrrb */ /* Table8215 */ 0xeb3, /* VCVTPD2UDQZ256rmb */ 0xec2, /* VCVTPD2UDQZrrb */ /* Table8217 */ 0x11c3, /* VCVTUQQ2PDZ256rmb */ 0x11d2, /* VCVTUQQ2PDZrrb */ /* Table8219 */ 0xfbc, /* VCVTQQ2PDZ256rmb */ 0xfcb, /* VCVTQQ2PDZrrb */ /* Table8221 */ 0x11e1, /* VCVTUQQ2PSZ256rmb */ 0x11f0, /* VCVTUQQ2PSZrrb */ /* Table8223 */ 0xe53, /* VCVTPD2DQZ256rmb */ 0xe62, /* VCVTPD2DQZrrb */ /* Table8225 */ 0x3adc, /* VUNPCKLPDZ256rmb */ 0x0, /* */ /* Table8227 */ 0x3a9e, /* VUNPCKHPDZ256rmb */ 0x0, /* */ /* Table8229 */ 0x39bf, /* VSQRTPDZ256mb */ 0x39ce, /* VSQRTPDZrb */ /* Table8231 */ 0xc6e, /* VANDPDZ256rmb */ 0x0, /* */ /* Table8233 */ 0xc30, /* VANDNPDZ256rmb */ 0x0, /* */ /* Table8235 */ 0x1ff5, /* VORPDZ256rmb */ 0x0, /* */ /* Table8237 */ 0x3b1a, /* VXORPDZ256rmb */ 0x0, /* */ /* Table8239 */ 0xb64, /* VADDPDZ256rmb */ 0xb73, /* VADDPDZrrb */ /* Table8241 */ 0x1f8d, /* VMULPDZ256rmb */ 0x1f9c, /* VMULPDZrrb */ /* Table8243 */ 0xe75, /* VCVTPD2PSZ256rmb */ 0xe84, /* VCVTPD2PSZrrb */ /* Table8245 */ 0x3a22, /* VSUBPDZ256rmb */ 0x3a31, /* VSUBPDZrrb */ /* Table8247 */ 0x1cea, /* VMINPDZ256rmb */ 0x1cf9, /* VMINPDZrrb */ /* Table8249 */ 0x1226, /* VDIVPDZ256rmb */ 0x1235, /* VDIVPDZrrb */ /* Table8251 */ 0x1c3f, /* VMAXPDZ256rmb */ 0x1c4e, /* VMAXPDZrrb */ /* Table8253 */ 0x3682, /* VPUNPCKLQDQZ256rmb */ 0x0, /* */ /* Table8255 */ 0x3618, /* VPUNPCKHQDQZ256rmb */ 0x0, /* */ /* Table8257 */ 0x2f8e, /* VPRORQZ256mbi */ 0x2f22, /* VPROLQZ256mbi */ 0x0, /* */ 0x0, /* */ 0x32e7, /* VPSRAQZ256mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8273 */ 0x0, /* */ 0x0, /* */ 0x33c8, /* VPSRLQZ256mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x320a, /* VPSLLQZ256mbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8289 */ 0x10b8, /* VCVTTPD2UQQZ256rmb */ 0x10c7, /* VCVTTPD2UQQZrrb */ /* Table8291 */ 0xed1, /* VCVTPD2UQQZ256rmb */ 0xee0, /* VCVTPD2UQQZrrb */ /* Table8293 */ 0x107c, /* VCVTTPD2QQZ256rmb */ 0x108b, /* VCVTTPD2QQZrrb */ /* Table8295 */ 0xe95, /* VCVTPD2QQZ256rmb */ 0xea4, /* VCVTPD2QQZrrb */ /* Table8297 */ 0xd5e, /* VCMPPDZ256rmbi */ 0xd75, /* VCMPPDZrrib */ /* Table8299 */ 0x3980, /* VSHUFPDZ256rmbi */ 0x0, /* */ /* Table8301 */ 0x213e, /* VPADDQZ256rmb */ 0x0, /* */ /* Table8303 */ 0x2234, /* VPANDQZ256rmb */ 0x0, /* */ /* Table8305 */ 0x2215, /* VPANDNQZ256rmb */ 0x0, /* */ /* Table8307 */ 0x105c, /* VCVTTPD2DQZ256rmb */ 0x106b, /* VCVTTPD2DQZrrb */ /* Table8309 */ 0x2ee5, /* VPORQZ256rmb */ 0x0, /* */ /* Table8311 */ 0x36d0, /* VPXORQZ256rmb */ 0x0, /* */ /* Table8313 */ 0x2e53, /* VPMULUDQZ256rmb */ 0x0, /* */ /* Table8315 */ 0x34a4, /* VPSUBQZ256rmb */ 0x0, /* */ /* Table8317 */ 0x3b04, /* VUNPCKLPSZrmb */ 0x0, /* */ /* Table8319 */ 0x3ac6, /* VUNPCKHPSZrmb */ 0x0, /* */ /* Table8321 */ 0x39ea, /* VSQRTPSZmb */ 0x39f0, /* VSQRTPSZrb */ /* Table8323 */ 0xc96, /* VANDPSZrmb */ 0x0, /* */ /* Table8325 */ 0xc58, /* VANDNPSZrmb */ 0x0, /* */ /* Table8327 */ 0x201d, /* VORPSZrmb */ 0x0, /* */ /* Table8329 */ 0x3b42, /* VXORPSZrmb */ 0x0, /* */ /* Table8331 */ 0xb8f, /* VADDPSZrmb */ 0xb95, /* VADDPSZrrb */ /* Table8333 */ 0x1fb8, /* VMULPSZrmb */ 0x1fbe, /* VMULPSZrrb */ /* Table8335 */ 0xf35, /* VCVTPS2PDZrmb */ 0xf3b, /* VCVTPS2PDZrrb */ /* Table8337 */ 0xe3a, /* VCVTDQ2PSZrmb */ 0xe40, /* VCVTDQ2PSZrrb */ /* Table8339 */ 0x3a4d, /* VSUBPSZrmb */ 0x3a53, /* VSUBPSZrrb */ /* Table8341 */ 0x1d15, /* VMINPSZrmb */ 0x1d1b, /* VMINPSZrrb */ /* Table8343 */ 0x1251, /* VDIVPSZrmb */ 0x1257, /* VDIVPSZrrb */ /* Table8345 */ 0x1c6a, /* VMAXPSZrmb */ 0x1c70, /* VMAXPSZrrb */ /* Table8347 */ 0x111f, /* VCVTTPS2UDQZrmb */ 0x1125, /* VCVTTPS2UDQZrrb */ /* Table8349 */ 0xf89, /* VCVTPS2UDQZrmb */ 0xf8f, /* VCVTPS2UDQZrrb */ /* Table8351 */ 0xd9a, /* VCMPPSZrmbi */ 0xda5, /* VCMPPSZrrib */ /* Table8353 */ 0x39a8, /* VSHUFPSZrmbi */ 0x0, /* */ /* Table8355 */ 0x10e1, /* VCVTTPS2DQZrmb */ 0x10e7, /* VCVTTPS2DQZrrb */ /* Table8357 */ 0x1193, /* VCVTUDQ2PDZrmb */ 0x0, /* */ /* Table8359 */ 0xe1b, /* VCVTDQ2PDZrmb */ 0x0, /* */ /* Table8361 */ 0x11ae, /* VCVTUDQ2PSZrmb */ 0x11b4, /* VCVTUDQ2PSZrrb */ /* Table8363 */ 0xf13, /* VCVTPS2DQZrmb */ 0xf19, /* VCVTPS2DQZrrb */ /* Table8365 */ 0x366c, /* VPUNPCKLDQZrmb */ 0x0, /* */ /* Table8367 */ 0x241a, /* VPCMPGTDZrmb */ 0x0, /* */ /* Table8369 */ 0x3602, /* VPUNPCKHDQZrmb */ 0x0, /* */ /* Table8371 */ 0x20a8, /* VPACKSSDWZrmb */ 0x0, /* */ /* Table8373 */ 0x317a, /* VPSHUFDZmbi */ 0x0, /* */ /* Table8375 */ 0x2f7c, /* VPRORDZmbi */ 0x2f10, /* VPROLDZmbi */ 0x33a4, /* VPSRLDZmbi */ 0x0, /* */ 0x32c6, /* VPSRADZmbi */ 0x0, /* */ 0x31e6, /* VPSLLDZmbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8391 */ 0x23ca, /* VPCMPEQDZrmb */ 0x0, /* */ /* Table8393 */ 0x113d, /* VCVTTPS2UQQZrmb */ 0x1143, /* VCVTTPS2UQQZrrb */ /* Table8395 */ 0xfa7, /* VCVTPS2UQQZrmb */ 0xfad, /* VCVTPS2UQQZrrb */ /* Table8397 */ 0x1101, /* VCVTTPS2QQZrmb */ 0x1107, /* VCVTTPS2QQZrrb */ /* Table8399 */ 0xf6b, /* VCVTPS2QQZrmb */ 0xf71, /* VCVTPS2QQZrrb */ /* Table8401 */ 0x21e8, /* VPANDDZrmb */ 0x0, /* */ /* Table8403 */ 0x2203, /* VPANDNDZrmb */ 0x0, /* */ /* Table8405 */ 0x2ed3, /* VPORDZrmb */ 0x0, /* */ /* Table8407 */ 0x36be, /* VPXORDZrmb */ 0x0, /* */ /* Table8409 */ 0x348e, /* VPSUBDZrmb */ 0x0, /* */ /* Table8411 */ 0x2128, /* VPADDDZrmb */ 0x0, /* */ /* Table8413 */ 0xfe3, /* VCVTQQ2PSZrmb */ 0xfe9, /* VCVTQQ2PSZrrb */ /* Table8415 */ 0x10a3, /* VCVTTPD2UDQZrmb */ 0x10a9, /* VCVTTPD2UDQZrrb */ /* Table8417 */ 0xebc, /* VCVTPD2UDQZrmb */ 0xec2, /* VCVTPD2UDQZrrb */ /* Table8419 */ 0x11cc, /* VCVTUQQ2PDZrmb */ 0x11d2, /* VCVTUQQ2PDZrrb */ /* Table8421 */ 0xfc5, /* VCVTQQ2PDZrmb */ 0xfcb, /* VCVTQQ2PDZrrb */ /* Table8423 */ 0x11ea, /* VCVTUQQ2PSZrmb */ 0x11f0, /* VCVTUQQ2PSZrrb */ /* Table8425 */ 0xe5c, /* VCVTPD2DQZrmb */ 0xe62, /* VCVTPD2DQZrrb */ /* Table8427 */ 0x3ae5, /* VUNPCKLPDZrmb */ 0x0, /* */ /* Table8429 */ 0x3aa7, /* VUNPCKHPDZrmb */ 0x0, /* */ /* Table8431 */ 0x39c8, /* VSQRTPDZmb */ 0x39ce, /* VSQRTPDZrb */ /* Table8433 */ 0xc77, /* VANDPDZrmb */ 0x0, /* */ /* Table8435 */ 0xc39, /* VANDNPDZrmb */ 0x0, /* */ /* Table8437 */ 0x1ffe, /* VORPDZrmb */ 0x0, /* */ /* Table8439 */ 0x3b23, /* VXORPDZrmb */ 0x0, /* */ /* Table8441 */ 0xb6d, /* VADDPDZrmb */ 0xb73, /* VADDPDZrrb */ /* Table8443 */ 0x1f96, /* VMULPDZrmb */ 0x1f9c, /* VMULPDZrrb */ /* Table8445 */ 0xe7e, /* VCVTPD2PSZrmb */ 0xe84, /* VCVTPD2PSZrrb */ /* Table8447 */ 0x3a2b, /* VSUBPDZrmb */ 0x3a31, /* VSUBPDZrrb */ /* Table8449 */ 0x1cf3, /* VMINPDZrmb */ 0x1cf9, /* VMINPDZrrb */ /* Table8451 */ 0x122f, /* VDIVPDZrmb */ 0x1235, /* VDIVPDZrrb */ /* Table8453 */ 0x1c48, /* VMAXPDZrmb */ 0x1c4e, /* VMAXPDZrrb */ /* Table8455 */ 0x368b, /* VPUNPCKLQDQZrmb */ 0x0, /* */ /* Table8457 */ 0x3621, /* VPUNPCKHQDQZrmb */ 0x0, /* */ /* Table8459 */ 0x2f97, /* VPRORQZmbi */ 0x2f2b, /* VPROLQZmbi */ 0x0, /* */ 0x0, /* */ 0x32f6, /* VPSRAQZmbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8475 */ 0x0, /* */ 0x0, /* */ 0x33d7, /* VPSRLQZmbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3219, /* VPSLLQZmbi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8491 */ 0x10c1, /* VCVTTPD2UQQZrmb */ 0x10c7, /* VCVTTPD2UQQZrrb */ /* Table8493 */ 0xeda, /* VCVTPD2UQQZrmb */ 0xee0, /* VCVTPD2UQQZrrb */ /* Table8495 */ 0x1085, /* VCVTTPD2QQZrmb */ 0x108b, /* VCVTTPD2QQZrrb */ /* Table8497 */ 0xe9e, /* VCVTPD2QQZrmb */ 0xea4, /* VCVTPD2QQZrrb */ /* Table8499 */ 0xd6a, /* VCMPPDZrmbi */ 0xd75, /* VCMPPDZrrib */ /* Table8501 */ 0x3989, /* VSHUFPDZrmbi */ 0x0, /* */ /* Table8503 */ 0x2147, /* VPADDQZrmb */ 0x0, /* */ /* Table8505 */ 0x223d, /* VPANDQZrmb */ 0x0, /* */ /* Table8507 */ 0x221e, /* VPANDNQZrmb */ 0x0, /* */ /* Table8509 */ 0x1065, /* VCVTTPD2DQZrmb */ 0x106b, /* VCVTTPD2DQZrrb */ /* Table8511 */ 0x2eee, /* VPORQZrmb */ 0x0, /* */ /* Table8513 */ 0x36d9, /* VPXORQZrmb */ 0x0, /* */ /* Table8515 */ 0x2e5c, /* VPMULUDQZrmb */ 0x0, /* */ /* Table8517 */ 0x34ad, /* VPSUBQZrmb */ 0x0, /* */ /* Table8519 */ 0x3af3, /* VUNPCKLPSZ128rmbk */ 0x0, /* */ /* Table8521 */ 0x3ab5, /* VUNPCKHPSZ128rmbk */ 0x0, /* */ /* Table8523 */ 0x39d9, /* VSQRTPSZ128mbk */ 0x39f1, /* VSQRTPSZrbk */ /* Table8525 */ 0xc85, /* VANDPSZ128rmbk */ 0x0, /* */ /* Table8527 */ 0xc47, /* VANDNPSZ128rmbk */ 0x0, /* */ /* Table8529 */ 0x200c, /* VORPSZ128rmbk */ 0x0, /* */ /* Table8531 */ 0x3b31, /* VXORPSZ128rmbk */ 0x0, /* */ /* Table8533 */ 0xb7e, /* VADDPSZ128rmbk */ 0xb96, /* VADDPSZrrbk */ /* Table8535 */ 0x1fa7, /* VMULPSZ128rmbk */ 0x1fbf, /* VMULPSZrrbk */ /* Table8537 */ 0xf24, /* VCVTPS2PDZ128rmbk */ 0xf3c, /* VCVTPS2PDZrrbk */ /* Table8539 */ 0xe29, /* VCVTDQ2PSZ128rmbk */ 0xe41, /* VCVTDQ2PSZrrbk */ /* Table8541 */ 0x3a3c, /* VSUBPSZ128rmbk */ 0x3a54, /* VSUBPSZrrbk */ /* Table8543 */ 0x1d04, /* VMINPSZ128rmbk */ 0x1d1c, /* VMINPSZrrbk */ /* Table8545 */ 0x1240, /* VDIVPSZ128rmbk */ 0x1258, /* VDIVPSZrrbk */ /* Table8547 */ 0x1c59, /* VMAXPSZ128rmbk */ 0x1c71, /* VMAXPSZrrbk */ /* Table8549 */ 0x110e, /* VCVTTPS2UDQZ128rmbk */ 0x1126, /* VCVTTPS2UDQZrrbk */ /* Table8551 */ 0xf78, /* VCVTPS2UDQZ128rmbk */ 0xf90, /* VCVTPS2UDQZrrbk */ /* Table8553 */ 0xd85, /* VCMPPSZ128rmbik */ 0xda8, /* VCMPPSZrribk */ /* Table8555 */ 0x3997, /* VSHUFPSZ128rmbik */ 0x0, /* */ /* Table8557 */ 0x0, /* */ 0x3a0f, /* VSQRTSSZrb_Intk */ /* Table8559 */ 0x0, /* */ 0xbb4, /* VADDSSZrrb_Intk */ /* Table8561 */ 0x0, /* */ 0x1fdd, /* VMULSSZrrb_Intk */ /* Table8563 */ 0x0, /* */ 0x103a, /* VCVTSS2SDZrrb_Intk */ /* Table8565 */ 0x10d0, /* VCVTTPS2DQZ128rmbk */ 0x10e8, /* VCVTTPS2DQZrrbk */ /* Table8567 */ 0x0, /* */ 0x3a72, /* VSUBSSZrrb_Intk */ /* Table8569 */ 0x0, /* */ 0x1d3a, /* VMINSSZrrb_Intk */ /* Table8571 */ 0x0, /* */ 0x1276, /* VDIVSSZrrb_Intk */ /* Table8573 */ 0x0, /* */ 0x1c8f, /* VMAXSSZrrb_Intk */ /* Table8575 */ 0x1182, /* VCVTUDQ2PDZ128rmbk */ 0x0, /* */ /* Table8577 */ 0x0, /* */ 0xdcb, /* VCMPSSZrrb_Intk */ /* Table8579 */ 0xe0a, /* VCVTDQ2PDZ128rmbk */ 0x0, /* */ /* Table8581 */ 0x119d, /* VCVTUDQ2PSZ128rmbk */ 0x11b5, /* VCVTUDQ2PSZrrbk */ /* Table8583 */ 0xf02, /* VCVTPS2DQZ128rmbk */ 0xf1a, /* VCVTPS2DQZrrbk */ /* Table8585 */ 0x365b, /* VPUNPCKLDQZ128rmbk */ 0x0, /* */ /* Table8587 */ 0x240f, /* VPCMPGTDZ128rmbk */ 0x0, /* */ /* Table8589 */ 0x35f1, /* VPUNPCKHDQZ128rmbk */ 0x0, /* */ /* Table8591 */ 0x2097, /* VPACKSSDWZ128rmbk */ 0x0, /* */ /* Table8593 */ 0x3169, /* VPSHUFDZ128mbik */ 0x0, /* */ /* Table8595 */ 0x2f6b, /* VPRORDZ128mbik */ 0x2eff, /* VPROLDZ128mbik */ 0x3387, /* VPSRLDZ128mbik */ 0x0, /* */ 0x32a9, /* VPSRADZ128mbik */ 0x0, /* */ 0x31c9, /* VPSLLDZ128mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8611 */ 0x23bf, /* VPCMPEQDZ128rmbk */ 0x0, /* */ /* Table8613 */ 0x112c, /* VCVTTPS2UQQZ128rmbk */ 0x1144, /* VCVTTPS2UQQZrrbk */ /* Table8615 */ 0xf96, /* VCVTPS2UQQZ128rmbk */ 0xfae, /* VCVTPS2UQQZrrbk */ /* Table8617 */ 0x10f0, /* VCVTTPS2QQZ128rmbk */ 0x1108, /* VCVTTPS2QQZrrbk */ /* Table8619 */ 0xf5a, /* VCVTPS2QQZ128rmbk */ 0xf72, /* VCVTPS2QQZrrbk */ /* Table8621 */ 0x21d7, /* VPANDDZ128rmbk */ 0x0, /* */ /* Table8623 */ 0x21f2, /* VPANDNDZ128rmbk */ 0x0, /* */ /* Table8625 */ 0x2ec2, /* VPORDZ128rmbk */ 0x0, /* */ /* Table8627 */ 0x36ad, /* VPXORDZ128rmbk */ 0x0, /* */ /* Table8629 */ 0x347d, /* VPSUBDZ128rmbk */ 0x0, /* */ /* Table8631 */ 0x2117, /* VPADDDZ128rmbk */ 0x0, /* */ /* Table8633 */ 0xfd2, /* VCVTQQ2PSZ128rmbk */ 0xfea, /* VCVTQQ2PSZrrbk */ /* Table8635 */ 0x1092, /* VCVTTPD2UDQZ128rmbk */ 0x10aa, /* VCVTTPD2UDQZrrbk */ /* Table8637 */ 0xeab, /* VCVTPD2UDQZ128rmbk */ 0xec3, /* VCVTPD2UDQZrrbk */ /* Table8639 */ 0x11bb, /* VCVTUQQ2PDZ128rmbk */ 0x11d3, /* VCVTUQQ2PDZrrbk */ /* Table8641 */ 0xfb4, /* VCVTQQ2PDZ128rmbk */ 0xfcc, /* VCVTQQ2PDZrrbk */ /* Table8643 */ 0x0, /* */ 0x3a00, /* VSQRTSDZrb_Intk */ /* Table8645 */ 0x0, /* */ 0xba5, /* VADDSDZrrb_Intk */ /* Table8647 */ 0x0, /* */ 0x1fce, /* VMULSDZrrb_Intk */ /* Table8649 */ 0x0, /* */ 0x1001, /* VCVTSD2SSZrrb_Intk */ /* Table8651 */ 0x0, /* */ 0x3a63, /* VSUBSDZrrb_Intk */ /* Table8653 */ 0x0, /* */ 0x1d2b, /* VMINSDZrrb_Intk */ /* Table8655 */ 0x0, /* */ 0x1267, /* VDIVSDZrrb_Intk */ /* Table8657 */ 0x0, /* */ 0x1c80, /* VMAXSDZrrb_Intk */ /* Table8659 */ 0x11d9, /* VCVTUQQ2PSZ128rmbk */ 0x11f1, /* VCVTUQQ2PSZrrbk */ /* Table8661 */ 0x0, /* */ 0xdb7, /* VCMPSDZrrb_Intk */ /* Table8663 */ 0xe4b, /* VCVTPD2DQZ128rmbk */ 0xe63, /* VCVTPD2DQZrrbk */ /* Table8665 */ 0x3ad4, /* VUNPCKLPDZ128rmbk */ 0x0, /* */ /* Table8667 */ 0x3a96, /* VUNPCKHPDZ128rmbk */ 0x0, /* */ /* Table8669 */ 0x39b7, /* VSQRTPDZ128mbk */ 0x39cf, /* VSQRTPDZrbk */ /* Table8671 */ 0xc66, /* VANDPDZ128rmbk */ 0x0, /* */ /* Table8673 */ 0xc28, /* VANDNPDZ128rmbk */ 0x0, /* */ /* Table8675 */ 0x1fed, /* VORPDZ128rmbk */ 0x0, /* */ /* Table8677 */ 0x3b12, /* VXORPDZ128rmbk */ 0x0, /* */ /* Table8679 */ 0xb5c, /* VADDPDZ128rmbk */ 0xb74, /* VADDPDZrrbk */ /* Table8681 */ 0x1f85, /* VMULPDZ128rmbk */ 0x1f9d, /* VMULPDZrrbk */ /* Table8683 */ 0xe6d, /* VCVTPD2PSZ128rmbk */ 0xe85, /* VCVTPD2PSZrrbk */ /* Table8685 */ 0x3a1a, /* VSUBPDZ128rmbk */ 0x3a32, /* VSUBPDZrrbk */ /* Table8687 */ 0x1ce2, /* VMINPDZ128rmbk */ 0x1cfa, /* VMINPDZrrbk */ /* Table8689 */ 0x121e, /* VDIVPDZ128rmbk */ 0x1236, /* VDIVPDZrrbk */ /* Table8691 */ 0x1c37, /* VMAXPDZ128rmbk */ 0x1c4f, /* VMAXPDZrrbk */ /* Table8693 */ 0x367a, /* VPUNPCKLQDQZ128rmbk */ 0x0, /* */ /* Table8695 */ 0x3610, /* VPUNPCKHQDQZ128rmbk */ 0x0, /* */ /* Table8697 */ 0x2f86, /* VPRORQZ128mbik */ 0x2f1a, /* VPROLQZ128mbik */ 0x0, /* */ 0x0, /* */ 0x32d9, /* VPSRAQZ128mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8713 */ 0x0, /* */ 0x0, /* */ 0x33ba, /* VPSRLQZ128mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31fc, /* VPSLLQZ128mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8729 */ 0x10b0, /* VCVTTPD2UQQZ128rmbk */ 0x10c8, /* VCVTTPD2UQQZrrbk */ /* Table8731 */ 0xec9, /* VCVTPD2UQQZ128rmbk */ 0xee1, /* VCVTPD2UQQZrrbk */ /* Table8733 */ 0x1074, /* VCVTTPD2QQZ128rmbk */ 0x108c, /* VCVTTPD2QQZrrbk */ /* Table8735 */ 0xe8d, /* VCVTPD2QQZ128rmbk */ 0xea5, /* VCVTPD2QQZrrbk */ /* Table8737 */ 0xd55, /* VCMPPDZ128rmbik */ 0xd78, /* VCMPPDZrribk */ /* Table8739 */ 0x3978, /* VSHUFPDZ128rmbik */ 0x0, /* */ /* Table8741 */ 0x2136, /* VPADDQZ128rmbk */ 0x0, /* */ /* Table8743 */ 0x222c, /* VPANDQZ128rmbk */ 0x0, /* */ /* Table8745 */ 0x220d, /* VPANDNQZ128rmbk */ 0x0, /* */ /* Table8747 */ 0x1054, /* VCVTTPD2DQZ128rmbk */ 0x106c, /* VCVTTPD2DQZrrbk */ /* Table8749 */ 0x2edd, /* VPORQZ128rmbk */ 0x0, /* */ /* Table8751 */ 0x36c8, /* VPXORQZ128rmbk */ 0x0, /* */ /* Table8753 */ 0x2e4b, /* VPMULUDQZ128rmbk */ 0x0, /* */ /* Table8755 */ 0x349c, /* VPSUBQZ128rmbk */ 0x0, /* */ /* Table8757 */ 0x3afc, /* VUNPCKLPSZ256rmbk */ 0x0, /* */ /* Table8759 */ 0x3abe, /* VUNPCKHPSZ256rmbk */ 0x0, /* */ /* Table8761 */ 0x39e2, /* VSQRTPSZ256mbk */ 0x39f1, /* VSQRTPSZrbk */ /* Table8763 */ 0xc8e, /* VANDPSZ256rmbk */ 0x0, /* */ /* Table8765 */ 0xc50, /* VANDNPSZ256rmbk */ 0x0, /* */ /* Table8767 */ 0x2015, /* VORPSZ256rmbk */ 0x0, /* */ /* Table8769 */ 0x3b3a, /* VXORPSZ256rmbk */ 0x0, /* */ /* Table8771 */ 0xb87, /* VADDPSZ256rmbk */ 0xb96, /* VADDPSZrrbk */ /* Table8773 */ 0x1fb0, /* VMULPSZ256rmbk */ 0x1fbf, /* VMULPSZrrbk */ /* Table8775 */ 0xf2d, /* VCVTPS2PDZ256rmbk */ 0xf3c, /* VCVTPS2PDZrrbk */ /* Table8777 */ 0xe32, /* VCVTDQ2PSZ256rmbk */ 0xe41, /* VCVTDQ2PSZrrbk */ /* Table8779 */ 0x3a45, /* VSUBPSZ256rmbk */ 0x3a54, /* VSUBPSZrrbk */ /* Table8781 */ 0x1d0d, /* VMINPSZ256rmbk */ 0x1d1c, /* VMINPSZrrbk */ /* Table8783 */ 0x1249, /* VDIVPSZ256rmbk */ 0x1258, /* VDIVPSZrrbk */ /* Table8785 */ 0x1c62, /* VMAXPSZ256rmbk */ 0x1c71, /* VMAXPSZrrbk */ /* Table8787 */ 0x1117, /* VCVTTPS2UDQZ256rmbk */ 0x1126, /* VCVTTPS2UDQZrrbk */ /* Table8789 */ 0xf81, /* VCVTPS2UDQZ256rmbk */ 0xf90, /* VCVTPS2UDQZrrbk */ /* Table8791 */ 0xd91, /* VCMPPSZ256rmbik */ 0xda8, /* VCMPPSZrribk */ /* Table8793 */ 0x39a0, /* VSHUFPSZ256rmbik */ 0x0, /* */ /* Table8795 */ 0x10d9, /* VCVTTPS2DQZ256rmbk */ 0x10e8, /* VCVTTPS2DQZrrbk */ /* Table8797 */ 0x118b, /* VCVTUDQ2PDZ256rmbk */ 0x0, /* */ /* Table8799 */ 0xe13, /* VCVTDQ2PDZ256rmbk */ 0x0, /* */ /* Table8801 */ 0x11a6, /* VCVTUDQ2PSZ256rmbk */ 0x11b5, /* VCVTUDQ2PSZrrbk */ /* Table8803 */ 0xf0b, /* VCVTPS2DQZ256rmbk */ 0xf1a, /* VCVTPS2DQZrrbk */ /* Table8805 */ 0x3664, /* VPUNPCKLDQZ256rmbk */ 0x0, /* */ /* Table8807 */ 0x2415, /* VPCMPGTDZ256rmbk */ 0x0, /* */ /* Table8809 */ 0x35fa, /* VPUNPCKHDQZ256rmbk */ 0x0, /* */ /* Table8811 */ 0x20a0, /* VPACKSSDWZ256rmbk */ 0x0, /* */ /* Table8813 */ 0x3172, /* VPSHUFDZ256mbik */ 0x0, /* */ /* Table8815 */ 0x2f74, /* VPRORDZ256mbik */ 0x2f08, /* VPROLDZ256mbik */ 0x3396, /* VPSRLDZ256mbik */ 0x0, /* */ 0x32b8, /* VPSRADZ256mbik */ 0x0, /* */ 0x31d8, /* VPSLLDZ256mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8831 */ 0x23c5, /* VPCMPEQDZ256rmbk */ 0x0, /* */ /* Table8833 */ 0x1135, /* VCVTTPS2UQQZ256rmbk */ 0x1144, /* VCVTTPS2UQQZrrbk */ /* Table8835 */ 0xf9f, /* VCVTPS2UQQZ256rmbk */ 0xfae, /* VCVTPS2UQQZrrbk */ /* Table8837 */ 0x10f9, /* VCVTTPS2QQZ256rmbk */ 0x1108, /* VCVTTPS2QQZrrbk */ /* Table8839 */ 0xf63, /* VCVTPS2QQZ256rmbk */ 0xf72, /* VCVTPS2QQZrrbk */ /* Table8841 */ 0x21e0, /* VPANDDZ256rmbk */ 0x0, /* */ /* Table8843 */ 0x21fb, /* VPANDNDZ256rmbk */ 0x0, /* */ /* Table8845 */ 0x2ecb, /* VPORDZ256rmbk */ 0x0, /* */ /* Table8847 */ 0x36b6, /* VPXORDZ256rmbk */ 0x0, /* */ /* Table8849 */ 0x3486, /* VPSUBDZ256rmbk */ 0x0, /* */ /* Table8851 */ 0x2120, /* VPADDDZ256rmbk */ 0x0, /* */ /* Table8853 */ 0xfdb, /* VCVTQQ2PSZ256rmbk */ 0xfea, /* VCVTQQ2PSZrrbk */ /* Table8855 */ 0x109b, /* VCVTTPD2UDQZ256rmbk */ 0x10aa, /* VCVTTPD2UDQZrrbk */ /* Table8857 */ 0xeb4, /* VCVTPD2UDQZ256rmbk */ 0xec3, /* VCVTPD2UDQZrrbk */ /* Table8859 */ 0x11c4, /* VCVTUQQ2PDZ256rmbk */ 0x11d3, /* VCVTUQQ2PDZrrbk */ /* Table8861 */ 0xfbd, /* VCVTQQ2PDZ256rmbk */ 0xfcc, /* VCVTQQ2PDZrrbk */ /* Table8863 */ 0x11e2, /* VCVTUQQ2PSZ256rmbk */ 0x11f1, /* VCVTUQQ2PSZrrbk */ /* Table8865 */ 0xe54, /* VCVTPD2DQZ256rmbk */ 0xe63, /* VCVTPD2DQZrrbk */ /* Table8867 */ 0x3add, /* VUNPCKLPDZ256rmbk */ 0x0, /* */ /* Table8869 */ 0x3a9f, /* VUNPCKHPDZ256rmbk */ 0x0, /* */ /* Table8871 */ 0x39c0, /* VSQRTPDZ256mbk */ 0x39cf, /* VSQRTPDZrbk */ /* Table8873 */ 0xc6f, /* VANDPDZ256rmbk */ 0x0, /* */ /* Table8875 */ 0xc31, /* VANDNPDZ256rmbk */ 0x0, /* */ /* Table8877 */ 0x1ff6, /* VORPDZ256rmbk */ 0x0, /* */ /* Table8879 */ 0x3b1b, /* VXORPDZ256rmbk */ 0x0, /* */ /* Table8881 */ 0xb65, /* VADDPDZ256rmbk */ 0xb74, /* VADDPDZrrbk */ /* Table8883 */ 0x1f8e, /* VMULPDZ256rmbk */ 0x1f9d, /* VMULPDZrrbk */ /* Table8885 */ 0xe76, /* VCVTPD2PSZ256rmbk */ 0xe85, /* VCVTPD2PSZrrbk */ /* Table8887 */ 0x3a23, /* VSUBPDZ256rmbk */ 0x3a32, /* VSUBPDZrrbk */ /* Table8889 */ 0x1ceb, /* VMINPDZ256rmbk */ 0x1cfa, /* VMINPDZrrbk */ /* Table8891 */ 0x1227, /* VDIVPDZ256rmbk */ 0x1236, /* VDIVPDZrrbk */ /* Table8893 */ 0x1c40, /* VMAXPDZ256rmbk */ 0x1c4f, /* VMAXPDZrrbk */ /* Table8895 */ 0x3683, /* VPUNPCKLQDQZ256rmbk */ 0x0, /* */ /* Table8897 */ 0x3619, /* VPUNPCKHQDQZ256rmbk */ 0x0, /* */ /* Table8899 */ 0x2f8f, /* VPRORQZ256mbik */ 0x2f23, /* VPROLQZ256mbik */ 0x0, /* */ 0x0, /* */ 0x32e8, /* VPSRAQZ256mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8915 */ 0x0, /* */ 0x0, /* */ 0x33c9, /* VPSRLQZ256mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x320b, /* VPSLLQZ256mbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table8931 */ 0x10b9, /* VCVTTPD2UQQZ256rmbk */ 0x10c8, /* VCVTTPD2UQQZrrbk */ /* Table8933 */ 0xed2, /* VCVTPD2UQQZ256rmbk */ 0xee1, /* VCVTPD2UQQZrrbk */ /* Table8935 */ 0x107d, /* VCVTTPD2QQZ256rmbk */ 0x108c, /* VCVTTPD2QQZrrbk */ /* Table8937 */ 0xe96, /* VCVTPD2QQZ256rmbk */ 0xea5, /* VCVTPD2QQZrrbk */ /* Table8939 */ 0xd61, /* VCMPPDZ256rmbik */ 0xd78, /* VCMPPDZrribk */ /* Table8941 */ 0x3981, /* VSHUFPDZ256rmbik */ 0x0, /* */ /* Table8943 */ 0x213f, /* VPADDQZ256rmbk */ 0x0, /* */ /* Table8945 */ 0x2235, /* VPANDQZ256rmbk */ 0x0, /* */ /* Table8947 */ 0x2216, /* VPANDNQZ256rmbk */ 0x0, /* */ /* Table8949 */ 0x105d, /* VCVTTPD2DQZ256rmbk */ 0x106c, /* VCVTTPD2DQZrrbk */ /* Table8951 */ 0x2ee6, /* VPORQZ256rmbk */ 0x0, /* */ /* Table8953 */ 0x36d1, /* VPXORQZ256rmbk */ 0x0, /* */ /* Table8955 */ 0x2e54, /* VPMULUDQZ256rmbk */ 0x0, /* */ /* Table8957 */ 0x34a5, /* VPSUBQZ256rmbk */ 0x0, /* */ /* Table8959 */ 0x3b05, /* VUNPCKLPSZrmbk */ 0x0, /* */ /* Table8961 */ 0x3ac7, /* VUNPCKHPSZrmbk */ 0x0, /* */ /* Table8963 */ 0x39eb, /* VSQRTPSZmbk */ 0x39f1, /* VSQRTPSZrbk */ /* Table8965 */ 0xc97, /* VANDPSZrmbk */ 0x0, /* */ /* Table8967 */ 0xc59, /* VANDNPSZrmbk */ 0x0, /* */ /* Table8969 */ 0x201e, /* VORPSZrmbk */ 0x0, /* */ /* Table8971 */ 0x3b43, /* VXORPSZrmbk */ 0x0, /* */ /* Table8973 */ 0xb90, /* VADDPSZrmbk */ 0xb96, /* VADDPSZrrbk */ /* Table8975 */ 0x1fb9, /* VMULPSZrmbk */ 0x1fbf, /* VMULPSZrrbk */ /* Table8977 */ 0xf36, /* VCVTPS2PDZrmbk */ 0xf3c, /* VCVTPS2PDZrrbk */ /* Table8979 */ 0xe3b, /* VCVTDQ2PSZrmbk */ 0xe41, /* VCVTDQ2PSZrrbk */ /* Table8981 */ 0x3a4e, /* VSUBPSZrmbk */ 0x3a54, /* VSUBPSZrrbk */ /* Table8983 */ 0x1d16, /* VMINPSZrmbk */ 0x1d1c, /* VMINPSZrrbk */ /* Table8985 */ 0x1252, /* VDIVPSZrmbk */ 0x1258, /* VDIVPSZrrbk */ /* Table8987 */ 0x1c6b, /* VMAXPSZrmbk */ 0x1c71, /* VMAXPSZrrbk */ /* Table8989 */ 0x1120, /* VCVTTPS2UDQZrmbk */ 0x1126, /* VCVTTPS2UDQZrrbk */ /* Table8991 */ 0xf8a, /* VCVTPS2UDQZrmbk */ 0xf90, /* VCVTPS2UDQZrrbk */ /* Table8993 */ 0xd9d, /* VCMPPSZrmbik */ 0xda8, /* VCMPPSZrribk */ /* Table8995 */ 0x39a9, /* VSHUFPSZrmbik */ 0x0, /* */ /* Table8997 */ 0x10e2, /* VCVTTPS2DQZrmbk */ 0x10e8, /* VCVTTPS2DQZrrbk */ /* Table8999 */ 0x1194, /* VCVTUDQ2PDZrmbk */ 0x0, /* */ /* Table9001 */ 0xe1c, /* VCVTDQ2PDZrmbk */ 0x0, /* */ /* Table9003 */ 0x11af, /* VCVTUDQ2PSZrmbk */ 0x11b5, /* VCVTUDQ2PSZrrbk */ /* Table9005 */ 0xf14, /* VCVTPS2DQZrmbk */ 0xf1a, /* VCVTPS2DQZrrbk */ /* Table9007 */ 0x366d, /* VPUNPCKLDQZrmbk */ 0x0, /* */ /* Table9009 */ 0x241b, /* VPCMPGTDZrmbk */ 0x0, /* */ /* Table9011 */ 0x3603, /* VPUNPCKHDQZrmbk */ 0x0, /* */ /* Table9013 */ 0x20a9, /* VPACKSSDWZrmbk */ 0x0, /* */ /* Table9015 */ 0x317b, /* VPSHUFDZmbik */ 0x0, /* */ /* Table9017 */ 0x2f7d, /* VPRORDZmbik */ 0x2f11, /* VPROLDZmbik */ 0x33a5, /* VPSRLDZmbik */ 0x0, /* */ 0x32c7, /* VPSRADZmbik */ 0x0, /* */ 0x31e7, /* VPSLLDZmbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9033 */ 0x23cb, /* VPCMPEQDZrmbk */ 0x0, /* */ /* Table9035 */ 0x113e, /* VCVTTPS2UQQZrmbk */ 0x1144, /* VCVTTPS2UQQZrrbk */ /* Table9037 */ 0xfa8, /* VCVTPS2UQQZrmbk */ 0xfae, /* VCVTPS2UQQZrrbk */ /* Table9039 */ 0x1102, /* VCVTTPS2QQZrmbk */ 0x1108, /* VCVTTPS2QQZrrbk */ /* Table9041 */ 0xf6c, /* VCVTPS2QQZrmbk */ 0xf72, /* VCVTPS2QQZrrbk */ /* Table9043 */ 0x21e9, /* VPANDDZrmbk */ 0x0, /* */ /* Table9045 */ 0x2204, /* VPANDNDZrmbk */ 0x0, /* */ /* Table9047 */ 0x2ed4, /* VPORDZrmbk */ 0x0, /* */ /* Table9049 */ 0x36bf, /* VPXORDZrmbk */ 0x0, /* */ /* Table9051 */ 0x348f, /* VPSUBDZrmbk */ 0x0, /* */ /* Table9053 */ 0x2129, /* VPADDDZrmbk */ 0x0, /* */ /* Table9055 */ 0xfe4, /* VCVTQQ2PSZrmbk */ 0xfea, /* VCVTQQ2PSZrrbk */ /* Table9057 */ 0x10a4, /* VCVTTPD2UDQZrmbk */ 0x10aa, /* VCVTTPD2UDQZrrbk */ /* Table9059 */ 0xebd, /* VCVTPD2UDQZrmbk */ 0xec3, /* VCVTPD2UDQZrrbk */ /* Table9061 */ 0x11cd, /* VCVTUQQ2PDZrmbk */ 0x11d3, /* VCVTUQQ2PDZrrbk */ /* Table9063 */ 0xfc6, /* VCVTQQ2PDZrmbk */ 0xfcc, /* VCVTQQ2PDZrrbk */ /* Table9065 */ 0x11eb, /* VCVTUQQ2PSZrmbk */ 0x11f1, /* VCVTUQQ2PSZrrbk */ /* Table9067 */ 0xe5d, /* VCVTPD2DQZrmbk */ 0xe63, /* VCVTPD2DQZrrbk */ /* Table9069 */ 0x3ae6, /* VUNPCKLPDZrmbk */ 0x0, /* */ /* Table9071 */ 0x3aa8, /* VUNPCKHPDZrmbk */ 0x0, /* */ /* Table9073 */ 0x39c9, /* VSQRTPDZmbk */ 0x39cf, /* VSQRTPDZrbk */ /* Table9075 */ 0xc78, /* VANDPDZrmbk */ 0x0, /* */ /* Table9077 */ 0xc3a, /* VANDNPDZrmbk */ 0x0, /* */ /* Table9079 */ 0x1fff, /* VORPDZrmbk */ 0x0, /* */ /* Table9081 */ 0x3b24, /* VXORPDZrmbk */ 0x0, /* */ /* Table9083 */ 0xb6e, /* VADDPDZrmbk */ 0xb74, /* VADDPDZrrbk */ /* Table9085 */ 0x1f97, /* VMULPDZrmbk */ 0x1f9d, /* VMULPDZrrbk */ /* Table9087 */ 0xe7f, /* VCVTPD2PSZrmbk */ 0xe85, /* VCVTPD2PSZrrbk */ /* Table9089 */ 0x3a2c, /* VSUBPDZrmbk */ 0x3a32, /* VSUBPDZrrbk */ /* Table9091 */ 0x1cf4, /* VMINPDZrmbk */ 0x1cfa, /* VMINPDZrrbk */ /* Table9093 */ 0x1230, /* VDIVPDZrmbk */ 0x1236, /* VDIVPDZrrbk */ /* Table9095 */ 0x1c49, /* VMAXPDZrmbk */ 0x1c4f, /* VMAXPDZrrbk */ /* Table9097 */ 0x368c, /* VPUNPCKLQDQZrmbk */ 0x0, /* */ /* Table9099 */ 0x3622, /* VPUNPCKHQDQZrmbk */ 0x0, /* */ /* Table9101 */ 0x2f98, /* VPRORQZmbik */ 0x2f2c, /* VPROLQZmbik */ 0x0, /* */ 0x0, /* */ 0x32f7, /* VPSRAQZmbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9117 */ 0x0, /* */ 0x0, /* */ 0x33d8, /* VPSRLQZmbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x321a, /* VPSLLQZmbik */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9133 */ 0x10c2, /* VCVTTPD2UQQZrmbk */ 0x10c8, /* VCVTTPD2UQQZrrbk */ /* Table9135 */ 0xedb, /* VCVTPD2UQQZrmbk */ 0xee1, /* VCVTPD2UQQZrrbk */ /* Table9137 */ 0x1086, /* VCVTTPD2QQZrmbk */ 0x108c, /* VCVTTPD2QQZrrbk */ /* Table9139 */ 0xe9f, /* VCVTPD2QQZrmbk */ 0xea5, /* VCVTPD2QQZrrbk */ /* Table9141 */ 0xd6d, /* VCMPPDZrmbik */ 0xd78, /* VCMPPDZrribk */ /* Table9143 */ 0x398a, /* VSHUFPDZrmbik */ 0x0, /* */ /* Table9145 */ 0x2148, /* VPADDQZrmbk */ 0x0, /* */ /* Table9147 */ 0x223e, /* VPANDQZrmbk */ 0x0, /* */ /* Table9149 */ 0x221f, /* VPANDNQZrmbk */ 0x0, /* */ /* Table9151 */ 0x1066, /* VCVTTPD2DQZrmbk */ 0x106c, /* VCVTTPD2DQZrrbk */ /* Table9153 */ 0x2eef, /* VPORQZrmbk */ 0x0, /* */ /* Table9155 */ 0x36da, /* VPXORQZrmbk */ 0x0, /* */ /* Table9157 */ 0x2e5d, /* VPMULUDQZrmbk */ 0x0, /* */ /* Table9159 */ 0x34ae, /* VPSUBQZrmbk */ 0x0, /* */ /* Table9161 */ 0x3af4, /* VUNPCKLPSZ128rmbkz */ 0x0, /* */ /* Table9163 */ 0x3ab6, /* VUNPCKHPSZ128rmbkz */ 0x0, /* */ /* Table9165 */ 0x39da, /* VSQRTPSZ128mbkz */ 0x39f2, /* VSQRTPSZrbkz */ /* Table9167 */ 0xc86, /* VANDPSZ128rmbkz */ 0x0, /* */ /* Table9169 */ 0xc48, /* VANDNPSZ128rmbkz */ 0x0, /* */ /* Table9171 */ 0x200d, /* VORPSZ128rmbkz */ 0x0, /* */ /* Table9173 */ 0x3b32, /* VXORPSZ128rmbkz */ 0x0, /* */ /* Table9175 */ 0xb7f, /* VADDPSZ128rmbkz */ 0xb97, /* VADDPSZrrbkz */ /* Table9177 */ 0x1fa8, /* VMULPSZ128rmbkz */ 0x1fc0, /* VMULPSZrrbkz */ /* Table9179 */ 0xf25, /* VCVTPS2PDZ128rmbkz */ 0xf3d, /* VCVTPS2PDZrrbkz */ /* Table9181 */ 0xe2a, /* VCVTDQ2PSZ128rmbkz */ 0xe42, /* VCVTDQ2PSZrrbkz */ /* Table9183 */ 0x3a3d, /* VSUBPSZ128rmbkz */ 0x3a55, /* VSUBPSZrrbkz */ /* Table9185 */ 0x1d05, /* VMINPSZ128rmbkz */ 0x1d1d, /* VMINPSZrrbkz */ /* Table9187 */ 0x1241, /* VDIVPSZ128rmbkz */ 0x1259, /* VDIVPSZrrbkz */ /* Table9189 */ 0x1c5a, /* VMAXPSZ128rmbkz */ 0x1c72, /* VMAXPSZrrbkz */ /* Table9191 */ 0x110f, /* VCVTTPS2UDQZ128rmbkz */ 0x1127, /* VCVTTPS2UDQZrrbkz */ /* Table9193 */ 0xf79, /* VCVTPS2UDQZ128rmbkz */ 0xf91, /* VCVTPS2UDQZrrbkz */ /* Table9195 */ 0x3998, /* VSHUFPSZ128rmbikz */ 0x0, /* */ /* Table9197 */ 0x0, /* */ 0x3a10, /* VSQRTSSZrb_Intkz */ /* Table9199 */ 0x0, /* */ 0xbb5, /* VADDSSZrrb_Intkz */ /* Table9201 */ 0x0, /* */ 0x1fde, /* VMULSSZrrb_Intkz */ /* Table9203 */ 0x0, /* */ 0x103b, /* VCVTSS2SDZrrb_Intkz */ /* Table9205 */ 0x10d1, /* VCVTTPS2DQZ128rmbkz */ 0x10e9, /* VCVTTPS2DQZrrbkz */ /* Table9207 */ 0x0, /* */ 0x3a73, /* VSUBSSZrrb_Intkz */ /* Table9209 */ 0x0, /* */ 0x1d3b, /* VMINSSZrrb_Intkz */ /* Table9211 */ 0x0, /* */ 0x1277, /* VDIVSSZrrb_Intkz */ /* Table9213 */ 0x0, /* */ 0x1c90, /* VMAXSSZrrb_Intkz */ /* Table9215 */ 0x1183, /* VCVTUDQ2PDZ128rmbkz */ 0x0, /* */ /* Table9217 */ 0xe0b, /* VCVTDQ2PDZ128rmbkz */ 0x0, /* */ /* Table9219 */ 0x119e, /* VCVTUDQ2PSZ128rmbkz */ 0x11b6, /* VCVTUDQ2PSZrrbkz */ /* Table9221 */ 0xf03, /* VCVTPS2DQZ128rmbkz */ 0xf1b, /* VCVTPS2DQZrrbkz */ /* Table9223 */ 0x365c, /* VPUNPCKLDQZ128rmbkz */ 0x0, /* */ /* Table9225 */ 0x35f2, /* VPUNPCKHDQZ128rmbkz */ 0x0, /* */ /* Table9227 */ 0x2098, /* VPACKSSDWZ128rmbkz */ 0x0, /* */ /* Table9229 */ 0x316a, /* VPSHUFDZ128mbikz */ 0x0, /* */ /* Table9231 */ 0x2f6c, /* VPRORDZ128mbikz */ 0x2f00, /* VPROLDZ128mbikz */ 0x3388, /* VPSRLDZ128mbikz */ 0x0, /* */ 0x32aa, /* VPSRADZ128mbikz */ 0x0, /* */ 0x31ca, /* VPSLLDZ128mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9247 */ 0x112d, /* VCVTTPS2UQQZ128rmbkz */ 0x1145, /* VCVTTPS2UQQZrrbkz */ /* Table9249 */ 0xf97, /* VCVTPS2UQQZ128rmbkz */ 0xfaf, /* VCVTPS2UQQZrrbkz */ /* Table9251 */ 0x10f1, /* VCVTTPS2QQZ128rmbkz */ 0x1109, /* VCVTTPS2QQZrrbkz */ /* Table9253 */ 0xf5b, /* VCVTPS2QQZ128rmbkz */ 0xf73, /* VCVTPS2QQZrrbkz */ /* Table9255 */ 0x21d8, /* VPANDDZ128rmbkz */ 0x0, /* */ /* Table9257 */ 0x21f3, /* VPANDNDZ128rmbkz */ 0x0, /* */ /* Table9259 */ 0x2ec3, /* VPORDZ128rmbkz */ 0x0, /* */ /* Table9261 */ 0x36ae, /* VPXORDZ128rmbkz */ 0x0, /* */ /* Table9263 */ 0x347e, /* VPSUBDZ128rmbkz */ 0x0, /* */ /* Table9265 */ 0x2118, /* VPADDDZ128rmbkz */ 0x0, /* */ /* Table9267 */ 0xfd3, /* VCVTQQ2PSZ128rmbkz */ 0xfeb, /* VCVTQQ2PSZrrbkz */ /* Table9269 */ 0x1093, /* VCVTTPD2UDQZ128rmbkz */ 0x10ab, /* VCVTTPD2UDQZrrbkz */ /* Table9271 */ 0xeac, /* VCVTPD2UDQZ128rmbkz */ 0xec4, /* VCVTPD2UDQZrrbkz */ /* Table9273 */ 0x11bc, /* VCVTUQQ2PDZ128rmbkz */ 0x11d4, /* VCVTUQQ2PDZrrbkz */ /* Table9275 */ 0xfb5, /* VCVTQQ2PDZ128rmbkz */ 0xfcd, /* VCVTQQ2PDZrrbkz */ /* Table9277 */ 0x0, /* */ 0x3a01, /* VSQRTSDZrb_Intkz */ /* Table9279 */ 0x0, /* */ 0xba6, /* VADDSDZrrb_Intkz */ /* Table9281 */ 0x0, /* */ 0x1fcf, /* VMULSDZrrb_Intkz */ /* Table9283 */ 0x0, /* */ 0x1002, /* VCVTSD2SSZrrb_Intkz */ /* Table9285 */ 0x0, /* */ 0x3a64, /* VSUBSDZrrb_Intkz */ /* Table9287 */ 0x0, /* */ 0x1d2c, /* VMINSDZrrb_Intkz */ /* Table9289 */ 0x0, /* */ 0x1268, /* VDIVSDZrrb_Intkz */ /* Table9291 */ 0x0, /* */ 0x1c81, /* VMAXSDZrrb_Intkz */ /* Table9293 */ 0x11da, /* VCVTUQQ2PSZ128rmbkz */ 0x11f2, /* VCVTUQQ2PSZrrbkz */ /* Table9295 */ 0xe4c, /* VCVTPD2DQZ128rmbkz */ 0xe64, /* VCVTPD2DQZrrbkz */ /* Table9297 */ 0x3ad5, /* VUNPCKLPDZ128rmbkz */ 0x0, /* */ /* Table9299 */ 0x3a97, /* VUNPCKHPDZ128rmbkz */ 0x0, /* */ /* Table9301 */ 0x39b8, /* VSQRTPDZ128mbkz */ 0x39d0, /* VSQRTPDZrbkz */ /* Table9303 */ 0xc67, /* VANDPDZ128rmbkz */ 0x0, /* */ /* Table9305 */ 0xc29, /* VANDNPDZ128rmbkz */ 0x0, /* */ /* Table9307 */ 0x1fee, /* VORPDZ128rmbkz */ 0x0, /* */ /* Table9309 */ 0x3b13, /* VXORPDZ128rmbkz */ 0x0, /* */ /* Table9311 */ 0xb5d, /* VADDPDZ128rmbkz */ 0xb75, /* VADDPDZrrbkz */ /* Table9313 */ 0x1f86, /* VMULPDZ128rmbkz */ 0x1f9e, /* VMULPDZrrbkz */ /* Table9315 */ 0xe6e, /* VCVTPD2PSZ128rmbkz */ 0xe86, /* VCVTPD2PSZrrbkz */ /* Table9317 */ 0x3a1b, /* VSUBPDZ128rmbkz */ 0x3a33, /* VSUBPDZrrbkz */ /* Table9319 */ 0x1ce3, /* VMINPDZ128rmbkz */ 0x1cfb, /* VMINPDZrrbkz */ /* Table9321 */ 0x121f, /* VDIVPDZ128rmbkz */ 0x1237, /* VDIVPDZrrbkz */ /* Table9323 */ 0x1c38, /* VMAXPDZ128rmbkz */ 0x1c50, /* VMAXPDZrrbkz */ /* Table9325 */ 0x367b, /* VPUNPCKLQDQZ128rmbkz */ 0x0, /* */ /* Table9327 */ 0x3611, /* VPUNPCKHQDQZ128rmbkz */ 0x0, /* */ /* Table9329 */ 0x2f87, /* VPRORQZ128mbikz */ 0x2f1b, /* VPROLQZ128mbikz */ 0x0, /* */ 0x0, /* */ 0x32da, /* VPSRAQZ128mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9345 */ 0x0, /* */ 0x0, /* */ 0x33bb, /* VPSRLQZ128mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31fd, /* VPSLLQZ128mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9361 */ 0x10b1, /* VCVTTPD2UQQZ128rmbkz */ 0x10c9, /* VCVTTPD2UQQZrrbkz */ /* Table9363 */ 0xeca, /* VCVTPD2UQQZ128rmbkz */ 0xee2, /* VCVTPD2UQQZrrbkz */ /* Table9365 */ 0x1075, /* VCVTTPD2QQZ128rmbkz */ 0x108d, /* VCVTTPD2QQZrrbkz */ /* Table9367 */ 0xe8e, /* VCVTPD2QQZ128rmbkz */ 0xea6, /* VCVTPD2QQZrrbkz */ /* Table9369 */ 0x3979, /* VSHUFPDZ128rmbikz */ 0x0, /* */ /* Table9371 */ 0x2137, /* VPADDQZ128rmbkz */ 0x0, /* */ /* Table9373 */ 0x222d, /* VPANDQZ128rmbkz */ 0x0, /* */ /* Table9375 */ 0x220e, /* VPANDNQZ128rmbkz */ 0x0, /* */ /* Table9377 */ 0x1055, /* VCVTTPD2DQZ128rmbkz */ 0x106d, /* VCVTTPD2DQZrrbkz */ /* Table9379 */ 0x2ede, /* VPORQZ128rmbkz */ 0x0, /* */ /* Table9381 */ 0x36c9, /* VPXORQZ128rmbkz */ 0x0, /* */ /* Table9383 */ 0x2e4c, /* VPMULUDQZ128rmbkz */ 0x0, /* */ /* Table9385 */ 0x349d, /* VPSUBQZ128rmbkz */ 0x0, /* */ /* Table9387 */ 0x3afd, /* VUNPCKLPSZ256rmbkz */ 0x0, /* */ /* Table9389 */ 0x3abf, /* VUNPCKHPSZ256rmbkz */ 0x0, /* */ /* Table9391 */ 0x39e3, /* VSQRTPSZ256mbkz */ 0x39f2, /* VSQRTPSZrbkz */ /* Table9393 */ 0xc8f, /* VANDPSZ256rmbkz */ 0x0, /* */ /* Table9395 */ 0xc51, /* VANDNPSZ256rmbkz */ 0x0, /* */ /* Table9397 */ 0x2016, /* VORPSZ256rmbkz */ 0x0, /* */ /* Table9399 */ 0x3b3b, /* VXORPSZ256rmbkz */ 0x0, /* */ /* Table9401 */ 0xb88, /* VADDPSZ256rmbkz */ 0xb97, /* VADDPSZrrbkz */ /* Table9403 */ 0x1fb1, /* VMULPSZ256rmbkz */ 0x1fc0, /* VMULPSZrrbkz */ /* Table9405 */ 0xf2e, /* VCVTPS2PDZ256rmbkz */ 0xf3d, /* VCVTPS2PDZrrbkz */ /* Table9407 */ 0xe33, /* VCVTDQ2PSZ256rmbkz */ 0xe42, /* VCVTDQ2PSZrrbkz */ /* Table9409 */ 0x3a46, /* VSUBPSZ256rmbkz */ 0x3a55, /* VSUBPSZrrbkz */ /* Table9411 */ 0x1d0e, /* VMINPSZ256rmbkz */ 0x1d1d, /* VMINPSZrrbkz */ /* Table9413 */ 0x124a, /* VDIVPSZ256rmbkz */ 0x1259, /* VDIVPSZrrbkz */ /* Table9415 */ 0x1c63, /* VMAXPSZ256rmbkz */ 0x1c72, /* VMAXPSZrrbkz */ /* Table9417 */ 0x1118, /* VCVTTPS2UDQZ256rmbkz */ 0x1127, /* VCVTTPS2UDQZrrbkz */ /* Table9419 */ 0xf82, /* VCVTPS2UDQZ256rmbkz */ 0xf91, /* VCVTPS2UDQZrrbkz */ /* Table9421 */ 0x39a1, /* VSHUFPSZ256rmbikz */ 0x0, /* */ /* Table9423 */ 0x10da, /* VCVTTPS2DQZ256rmbkz */ 0x10e9, /* VCVTTPS2DQZrrbkz */ /* Table9425 */ 0x118c, /* VCVTUDQ2PDZ256rmbkz */ 0x0, /* */ /* Table9427 */ 0xe14, /* VCVTDQ2PDZ256rmbkz */ 0x0, /* */ /* Table9429 */ 0x11a7, /* VCVTUDQ2PSZ256rmbkz */ 0x11b6, /* VCVTUDQ2PSZrrbkz */ /* Table9431 */ 0xf0c, /* VCVTPS2DQZ256rmbkz */ 0xf1b, /* VCVTPS2DQZrrbkz */ /* Table9433 */ 0x3665, /* VPUNPCKLDQZ256rmbkz */ 0x0, /* */ /* Table9435 */ 0x35fb, /* VPUNPCKHDQZ256rmbkz */ 0x0, /* */ /* Table9437 */ 0x20a1, /* VPACKSSDWZ256rmbkz */ 0x0, /* */ /* Table9439 */ 0x3173, /* VPSHUFDZ256mbikz */ 0x0, /* */ /* Table9441 */ 0x2f75, /* VPRORDZ256mbikz */ 0x2f09, /* VPROLDZ256mbikz */ 0x3397, /* VPSRLDZ256mbikz */ 0x0, /* */ 0x32b9, /* VPSRADZ256mbikz */ 0x0, /* */ 0x31d9, /* VPSLLDZ256mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9457 */ 0x1136, /* VCVTTPS2UQQZ256rmbkz */ 0x1145, /* VCVTTPS2UQQZrrbkz */ /* Table9459 */ 0xfa0, /* VCVTPS2UQQZ256rmbkz */ 0xfaf, /* VCVTPS2UQQZrrbkz */ /* Table9461 */ 0x10fa, /* VCVTTPS2QQZ256rmbkz */ 0x1109, /* VCVTTPS2QQZrrbkz */ /* Table9463 */ 0xf64, /* VCVTPS2QQZ256rmbkz */ 0xf73, /* VCVTPS2QQZrrbkz */ /* Table9465 */ 0x21e1, /* VPANDDZ256rmbkz */ 0x0, /* */ /* Table9467 */ 0x21fc, /* VPANDNDZ256rmbkz */ 0x0, /* */ /* Table9469 */ 0x2ecc, /* VPORDZ256rmbkz */ 0x0, /* */ /* Table9471 */ 0x36b7, /* VPXORDZ256rmbkz */ 0x0, /* */ /* Table9473 */ 0x3487, /* VPSUBDZ256rmbkz */ 0x0, /* */ /* Table9475 */ 0x2121, /* VPADDDZ256rmbkz */ 0x0, /* */ /* Table9477 */ 0xfdc, /* VCVTQQ2PSZ256rmbkz */ 0xfeb, /* VCVTQQ2PSZrrbkz */ /* Table9479 */ 0x109c, /* VCVTTPD2UDQZ256rmbkz */ 0x10ab, /* VCVTTPD2UDQZrrbkz */ /* Table9481 */ 0xeb5, /* VCVTPD2UDQZ256rmbkz */ 0xec4, /* VCVTPD2UDQZrrbkz */ /* Table9483 */ 0x11c5, /* VCVTUQQ2PDZ256rmbkz */ 0x11d4, /* VCVTUQQ2PDZrrbkz */ /* Table9485 */ 0xfbe, /* VCVTQQ2PDZ256rmbkz */ 0xfcd, /* VCVTQQ2PDZrrbkz */ /* Table9487 */ 0x11e3, /* VCVTUQQ2PSZ256rmbkz */ 0x11f2, /* VCVTUQQ2PSZrrbkz */ /* Table9489 */ 0xe55, /* VCVTPD2DQZ256rmbkz */ 0xe64, /* VCVTPD2DQZrrbkz */ /* Table9491 */ 0x3ade, /* VUNPCKLPDZ256rmbkz */ 0x0, /* */ /* Table9493 */ 0x3aa0, /* VUNPCKHPDZ256rmbkz */ 0x0, /* */ /* Table9495 */ 0x39c1, /* VSQRTPDZ256mbkz */ 0x39d0, /* VSQRTPDZrbkz */ /* Table9497 */ 0xc70, /* VANDPDZ256rmbkz */ 0x0, /* */ /* Table9499 */ 0xc32, /* VANDNPDZ256rmbkz */ 0x0, /* */ /* Table9501 */ 0x1ff7, /* VORPDZ256rmbkz */ 0x0, /* */ /* Table9503 */ 0x3b1c, /* VXORPDZ256rmbkz */ 0x0, /* */ /* Table9505 */ 0xb66, /* VADDPDZ256rmbkz */ 0xb75, /* VADDPDZrrbkz */ /* Table9507 */ 0x1f8f, /* VMULPDZ256rmbkz */ 0x1f9e, /* VMULPDZrrbkz */ /* Table9509 */ 0xe77, /* VCVTPD2PSZ256rmbkz */ 0xe86, /* VCVTPD2PSZrrbkz */ /* Table9511 */ 0x3a24, /* VSUBPDZ256rmbkz */ 0x3a33, /* VSUBPDZrrbkz */ /* Table9513 */ 0x1cec, /* VMINPDZ256rmbkz */ 0x1cfb, /* VMINPDZrrbkz */ /* Table9515 */ 0x1228, /* VDIVPDZ256rmbkz */ 0x1237, /* VDIVPDZrrbkz */ /* Table9517 */ 0x1c41, /* VMAXPDZ256rmbkz */ 0x1c50, /* VMAXPDZrrbkz */ /* Table9519 */ 0x3684, /* VPUNPCKLQDQZ256rmbkz */ 0x0, /* */ /* Table9521 */ 0x361a, /* VPUNPCKHQDQZ256rmbkz */ 0x0, /* */ /* Table9523 */ 0x2f90, /* VPRORQZ256mbikz */ 0x2f24, /* VPROLQZ256mbikz */ 0x0, /* */ 0x0, /* */ 0x32e9, /* VPSRAQZ256mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9539 */ 0x0, /* */ 0x0, /* */ 0x33ca, /* VPSRLQZ256mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x320c, /* VPSLLQZ256mbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9555 */ 0x10ba, /* VCVTTPD2UQQZ256rmbkz */ 0x10c9, /* VCVTTPD2UQQZrrbkz */ /* Table9557 */ 0xed3, /* VCVTPD2UQQZ256rmbkz */ 0xee2, /* VCVTPD2UQQZrrbkz */ /* Table9559 */ 0x107e, /* VCVTTPD2QQZ256rmbkz */ 0x108d, /* VCVTTPD2QQZrrbkz */ /* Table9561 */ 0xe97, /* VCVTPD2QQZ256rmbkz */ 0xea6, /* VCVTPD2QQZrrbkz */ /* Table9563 */ 0x3982, /* VSHUFPDZ256rmbikz */ 0x0, /* */ /* Table9565 */ 0x2140, /* VPADDQZ256rmbkz */ 0x0, /* */ /* Table9567 */ 0x2236, /* VPANDQZ256rmbkz */ 0x0, /* */ /* Table9569 */ 0x2217, /* VPANDNQZ256rmbkz */ 0x0, /* */ /* Table9571 */ 0x105e, /* VCVTTPD2DQZ256rmbkz */ 0x106d, /* VCVTTPD2DQZrrbkz */ /* Table9573 */ 0x2ee7, /* VPORQZ256rmbkz */ 0x0, /* */ /* Table9575 */ 0x36d2, /* VPXORQZ256rmbkz */ 0x0, /* */ /* Table9577 */ 0x2e55, /* VPMULUDQZ256rmbkz */ 0x0, /* */ /* Table9579 */ 0x34a6, /* VPSUBQZ256rmbkz */ 0x0, /* */ /* Table9581 */ 0x3b06, /* VUNPCKLPSZrmbkz */ 0x0, /* */ /* Table9583 */ 0x3ac8, /* VUNPCKHPSZrmbkz */ 0x0, /* */ /* Table9585 */ 0x39ec, /* VSQRTPSZmbkz */ 0x39f2, /* VSQRTPSZrbkz */ /* Table9587 */ 0xc98, /* VANDPSZrmbkz */ 0x0, /* */ /* Table9589 */ 0xc5a, /* VANDNPSZrmbkz */ 0x0, /* */ /* Table9591 */ 0x201f, /* VORPSZrmbkz */ 0x0, /* */ /* Table9593 */ 0x3b44, /* VXORPSZrmbkz */ 0x0, /* */ /* Table9595 */ 0xb91, /* VADDPSZrmbkz */ 0xb97, /* VADDPSZrrbkz */ /* Table9597 */ 0x1fba, /* VMULPSZrmbkz */ 0x1fc0, /* VMULPSZrrbkz */ /* Table9599 */ 0xf37, /* VCVTPS2PDZrmbkz */ 0xf3d, /* VCVTPS2PDZrrbkz */ /* Table9601 */ 0xe3c, /* VCVTDQ2PSZrmbkz */ 0xe42, /* VCVTDQ2PSZrrbkz */ /* Table9603 */ 0x3a4f, /* VSUBPSZrmbkz */ 0x3a55, /* VSUBPSZrrbkz */ /* Table9605 */ 0x1d17, /* VMINPSZrmbkz */ 0x1d1d, /* VMINPSZrrbkz */ /* Table9607 */ 0x1253, /* VDIVPSZrmbkz */ 0x1259, /* VDIVPSZrrbkz */ /* Table9609 */ 0x1c6c, /* VMAXPSZrmbkz */ 0x1c72, /* VMAXPSZrrbkz */ /* Table9611 */ 0x1121, /* VCVTTPS2UDQZrmbkz */ 0x1127, /* VCVTTPS2UDQZrrbkz */ /* Table9613 */ 0xf8b, /* VCVTPS2UDQZrmbkz */ 0xf91, /* VCVTPS2UDQZrrbkz */ /* Table9615 */ 0x39aa, /* VSHUFPSZrmbikz */ 0x0, /* */ /* Table9617 */ 0x10e3, /* VCVTTPS2DQZrmbkz */ 0x10e9, /* VCVTTPS2DQZrrbkz */ /* Table9619 */ 0x1195, /* VCVTUDQ2PDZrmbkz */ 0x0, /* */ /* Table9621 */ 0xe1d, /* VCVTDQ2PDZrmbkz */ 0x0, /* */ /* Table9623 */ 0x11b0, /* VCVTUDQ2PSZrmbkz */ 0x11b6, /* VCVTUDQ2PSZrrbkz */ /* Table9625 */ 0xf15, /* VCVTPS2DQZrmbkz */ 0xf1b, /* VCVTPS2DQZrrbkz */ /* Table9627 */ 0x366e, /* VPUNPCKLDQZrmbkz */ 0x0, /* */ /* Table9629 */ 0x3604, /* VPUNPCKHDQZrmbkz */ 0x0, /* */ /* Table9631 */ 0x20aa, /* VPACKSSDWZrmbkz */ 0x0, /* */ /* Table9633 */ 0x317c, /* VPSHUFDZmbikz */ 0x0, /* */ /* Table9635 */ 0x2f7e, /* VPRORDZmbikz */ 0x2f12, /* VPROLDZmbikz */ 0x33a6, /* VPSRLDZmbikz */ 0x0, /* */ 0x32c8, /* VPSRADZmbikz */ 0x0, /* */ 0x31e8, /* VPSLLDZmbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9651 */ 0x113f, /* VCVTTPS2UQQZrmbkz */ 0x1145, /* VCVTTPS2UQQZrrbkz */ /* Table9653 */ 0xfa9, /* VCVTPS2UQQZrmbkz */ 0xfaf, /* VCVTPS2UQQZrrbkz */ /* Table9655 */ 0x1103, /* VCVTTPS2QQZrmbkz */ 0x1109, /* VCVTTPS2QQZrrbkz */ /* Table9657 */ 0xf6d, /* VCVTPS2QQZrmbkz */ 0xf73, /* VCVTPS2QQZrrbkz */ /* Table9659 */ 0x21ea, /* VPANDDZrmbkz */ 0x0, /* */ /* Table9661 */ 0x2205, /* VPANDNDZrmbkz */ 0x0, /* */ /* Table9663 */ 0x2ed5, /* VPORDZrmbkz */ 0x0, /* */ /* Table9665 */ 0x36c0, /* VPXORDZrmbkz */ 0x0, /* */ /* Table9667 */ 0x3490, /* VPSUBDZrmbkz */ 0x0, /* */ /* Table9669 */ 0x212a, /* VPADDDZrmbkz */ 0x0, /* */ /* Table9671 */ 0xfe5, /* VCVTQQ2PSZrmbkz */ 0xfeb, /* VCVTQQ2PSZrrbkz */ /* Table9673 */ 0x10a5, /* VCVTTPD2UDQZrmbkz */ 0x10ab, /* VCVTTPD2UDQZrrbkz */ /* Table9675 */ 0xebe, /* VCVTPD2UDQZrmbkz */ 0xec4, /* VCVTPD2UDQZrrbkz */ /* Table9677 */ 0x11ce, /* VCVTUQQ2PDZrmbkz */ 0x11d4, /* VCVTUQQ2PDZrrbkz */ /* Table9679 */ 0xfc7, /* VCVTQQ2PDZrmbkz */ 0xfcd, /* VCVTQQ2PDZrrbkz */ /* Table9681 */ 0x11ec, /* VCVTUQQ2PSZrmbkz */ 0x11f2, /* VCVTUQQ2PSZrrbkz */ /* Table9683 */ 0xe5e, /* VCVTPD2DQZrmbkz */ 0xe64, /* VCVTPD2DQZrrbkz */ /* Table9685 */ 0x3ae7, /* VUNPCKLPDZrmbkz */ 0x0, /* */ /* Table9687 */ 0x3aa9, /* VUNPCKHPDZrmbkz */ 0x0, /* */ /* Table9689 */ 0x39ca, /* VSQRTPDZmbkz */ 0x39d0, /* VSQRTPDZrbkz */ /* Table9691 */ 0xc79, /* VANDPDZrmbkz */ 0x0, /* */ /* Table9693 */ 0xc3b, /* VANDNPDZrmbkz */ 0x0, /* */ /* Table9695 */ 0x2000, /* VORPDZrmbkz */ 0x0, /* */ /* Table9697 */ 0x3b25, /* VXORPDZrmbkz */ 0x0, /* */ /* Table9699 */ 0xb6f, /* VADDPDZrmbkz */ 0xb75, /* VADDPDZrrbkz */ /* Table9701 */ 0x1f98, /* VMULPDZrmbkz */ 0x1f9e, /* VMULPDZrrbkz */ /* Table9703 */ 0xe80, /* VCVTPD2PSZrmbkz */ 0xe86, /* VCVTPD2PSZrrbkz */ /* Table9705 */ 0x3a2d, /* VSUBPDZrmbkz */ 0x3a33, /* VSUBPDZrrbkz */ /* Table9707 */ 0x1cf5, /* VMINPDZrmbkz */ 0x1cfb, /* VMINPDZrrbkz */ /* Table9709 */ 0x1231, /* VDIVPDZrmbkz */ 0x1237, /* VDIVPDZrrbkz */ /* Table9711 */ 0x1c4a, /* VMAXPDZrmbkz */ 0x1c50, /* VMAXPDZrrbkz */ /* Table9713 */ 0x368d, /* VPUNPCKLQDQZrmbkz */ 0x0, /* */ /* Table9715 */ 0x3623, /* VPUNPCKHQDQZrmbkz */ 0x0, /* */ /* Table9717 */ 0x2f99, /* VPRORQZmbikz */ 0x2f2d, /* VPROLQZmbikz */ 0x0, /* */ 0x0, /* */ 0x32f8, /* VPSRAQZmbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9733 */ 0x0, /* */ 0x0, /* */ 0x33d9, /* VPSRLQZmbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x321b, /* VPSLLQZmbikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table9749 */ 0x10c3, /* VCVTTPD2UQQZrmbkz */ 0x10c9, /* VCVTTPD2UQQZrrbkz */ /* Table9751 */ 0xedc, /* VCVTPD2UQQZrmbkz */ 0xee2, /* VCVTPD2UQQZrrbkz */ /* Table9753 */ 0x1087, /* VCVTTPD2QQZrmbkz */ 0x108d, /* VCVTTPD2QQZrrbkz */ /* Table9755 */ 0xea0, /* VCVTPD2QQZrmbkz */ 0xea6, /* VCVTPD2QQZrrbkz */ /* Table9757 */ 0x398b, /* VSHUFPDZrmbikz */ 0x0, /* */ /* Table9759 */ 0x2149, /* VPADDQZrmbkz */ 0x0, /* */ /* Table9761 */ 0x223f, /* VPANDQZrmbkz */ 0x0, /* */ /* Table9763 */ 0x2220, /* VPANDNQZrmbkz */ 0x0, /* */ /* Table9765 */ 0x1067, /* VCVTTPD2DQZrmbkz */ 0x106d, /* VCVTTPD2DQZrrbkz */ /* Table9767 */ 0x2ef0, /* VPORQZrmbkz */ 0x0, /* */ /* Table9769 */ 0x36db, /* VPXORQZrmbkz */ 0x0, /* */ /* Table9771 */ 0x2e5e, /* VPMULUDQZrmbkz */ 0x0, /* */ /* Table9773 */ 0x34af, /* VPSUBQZrmbkz */ 0x0, /* */ /* Table9775 */ 0x1f4f, /* VMOVUPSZ128rmkz */ 0x1f54, /* VMOVUPSZ128rrkz */ /* Table9777 */ 0x0, /* */ 0x1f55, /* VMOVUPSZ128rrkz_REV */ /* Table9779 */ 0x3af6, /* VUNPCKLPSZ128rmkz */ 0x3af9, /* VUNPCKLPSZ128rrkz */ /* Table9781 */ 0x3ab8, /* VUNPCKHPSZ128rmkz */ 0x3abb, /* VUNPCKHPSZ128rrkz */ /* Table9783 */ 0x1d7d, /* VMOVAPSZ128rmkz */ 0x1d82, /* VMOVAPSZ128rrkz */ /* Table9785 */ 0x0, /* */ 0x1d83, /* VMOVAPSZ128rrkz_REV */ /* Table9787 */ 0x39dc, /* VSQRTPSZ128mkz */ 0x39df, /* VSQRTPSZ128rkz */ /* Table9789 */ 0xc88, /* VANDPSZ128rmkz */ 0xc8b, /* VANDPSZ128rrkz */ /* Table9791 */ 0xc4a, /* VANDNPSZ128rmkz */ 0xc4d, /* VANDNPSZ128rrkz */ /* Table9793 */ 0x200f, /* VORPSZ128rmkz */ 0x2012, /* VORPSZ128rrkz */ /* Table9795 */ 0x3b34, /* VXORPSZ128rmkz */ 0x3b37, /* VXORPSZ128rrkz */ /* Table9797 */ 0xb81, /* VADDPSZ128rmkz */ 0xb84, /* VADDPSZ128rrkz */ /* Table9799 */ 0x1faa, /* VMULPSZ128rmkz */ 0x1fad, /* VMULPSZ128rrkz */ /* Table9801 */ 0xf27, /* VCVTPS2PDZ128rmkz */ 0xf2a, /* VCVTPS2PDZ128rrkz */ /* Table9803 */ 0xe2c, /* VCVTDQ2PSZ128rmkz */ 0xe2f, /* VCVTDQ2PSZ128rrkz */ /* Table9805 */ 0x3a3f, /* VSUBPSZ128rmkz */ 0x3a42, /* VSUBPSZ128rrkz */ /* Table9807 */ 0x1d07, /* VMINPSZ128rmkz */ 0x1d0a, /* VMINPSZ128rrkz */ /* Table9809 */ 0x1243, /* VDIVPSZ128rmkz */ 0x1246, /* VDIVPSZ128rrkz */ /* Table9811 */ 0x1c5c, /* VMAXPSZ128rmkz */ 0x1c5f, /* VMAXPSZ128rrkz */ /* Table9813 */ 0x1111, /* VCVTTPS2UDQZ128rmkz */ 0x1114, /* VCVTTPS2UDQZ128rrkz */ /* Table9815 */ 0xf7b, /* VCVTPS2UDQZ128rmkz */ 0xf7e, /* VCVTPS2UDQZ128rrkz */ /* Table9817 */ 0x399b, /* VSHUFPSZ128rmikz */ 0x399e, /* VSHUFPSZ128rrikz */ /* Table9819 */ 0x1f13, /* VMOVSSZrmkz */ 0x1f18, /* VMOVSSZrrkz */ /* Table9821 */ 0x0, /* */ 0x1f19, /* VMOVSSZrrkz_REV */ /* Table9823 */ 0x1ef9, /* VMOVSLDUPZ128rmkz */ 0x1efc, /* VMOVSLDUPZ128rrkz */ /* Table9825 */ 0x1ee3, /* VMOVSHDUPZ128rmkz */ 0x1ee6, /* VMOVSHDUPZ128rrkz */ /* Table9827 */ 0x3a09, /* VSQRTSSZm_Intkz */ 0x3a0d, /* VSQRTSSZr_Intkz */ /* Table9829 */ 0xbae, /* VADDSSZrm_Intkz */ 0xbb2, /* VADDSSZrr_Intkz */ /* Table9831 */ 0x1fd7, /* VMULSSZrm_Intkz */ 0x1fdb, /* VMULSSZrr_Intkz */ /* Table9833 */ 0x1034, /* VCVTSS2SDZrm_Intkz */ 0x1038, /* VCVTSS2SDZrr_Intkz */ /* Table9835 */ 0x10d3, /* VCVTTPS2DQZ128rmkz */ 0x10d6, /* VCVTTPS2DQZ128rrkz */ /* Table9837 */ 0x3a6c, /* VSUBSSZrm_Intkz */ 0x3a70, /* VSUBSSZrr_Intkz */ /* Table9839 */ 0x1d34, /* VMINSSZrm_Intkz */ 0x1d38, /* VMINSSZrr_Intkz */ /* Table9841 */ 0x1270, /* VDIVSSZrm_Intkz */ 0x1274, /* VDIVSSZrr_Intkz */ /* Table9843 */ 0x1c89, /* VMAXSSZrm_Intkz */ 0x1c8d, /* VMAXSSZrr_Intkz */ /* Table9845 */ 0x1e2b, /* VMOVDQU32Z128rmkz */ 0x1e30, /* VMOVDQU32Z128rrkz */ /* Table9847 */ 0x3189, /* VPSHUFHWZ128mikz */ 0x318c, /* VPSHUFHWZ128rikz */ /* Table9849 */ 0x1185, /* VCVTUDQ2PDZ128rmkz */ 0x1188, /* VCVTUDQ2PDZ128rrkz */ /* Table9851 */ 0x0, /* */ 0x1e31, /* VMOVDQU32Z128rrkz_REV */ /* Table9853 */ 0xe0d, /* VCVTDQ2PDZ128rmkz */ 0xe10, /* VCVTDQ2PDZ128rrkz */ /* Table9855 */ 0x1e6d, /* VMOVDQU8Z128rmkz */ 0x1e72, /* VMOVDQU8Z128rrkz */ /* Table9857 */ 0x319f, /* VPSHUFLWZ128mikz */ 0x31a2, /* VPSHUFLWZ128rikz */ /* Table9859 */ 0x11a0, /* VCVTUDQ2PSZ128rmkz */ 0x11a3, /* VCVTUDQ2PSZ128rrkz */ /* Table9861 */ 0x0, /* */ 0x1e73, /* VMOVDQU8Z128rrkz_REV */ /* Table9863 */ 0xf05, /* VCVTPS2DQZ128rmkz */ 0xf08, /* VCVTPS2DQZ128rrkz */ /* Table9865 */ 0x3645, /* VPUNPCKLBWZ128rmkz */ 0x3648, /* VPUNPCKLBWZ128rrkz */ /* Table9867 */ 0x3699, /* VPUNPCKLWDZ128rmkz */ 0x369c, /* VPUNPCKLWDZ128rrkz */ /* Table9869 */ 0x365e, /* VPUNPCKLDQZ128rmkz */ 0x3661, /* VPUNPCKLDQZ128rrkz */ /* Table9871 */ 0x20b6, /* VPACKSSWBZ128rmkz */ 0x20b9, /* VPACKSSWBZ128rrkz */ /* Table9873 */ 0x20eb, /* VPACKUSWBZ128rmkz */ 0x20ee, /* VPACKUSWBZ128rrkz */ /* Table9875 */ 0x35db, /* VPUNPCKHBWZ128rmkz */ 0x35de, /* VPUNPCKHBWZ128rrkz */ /* Table9877 */ 0x362f, /* VPUNPCKHWDZ128rmkz */ 0x3632, /* VPUNPCKHWDZ128rrkz */ /* Table9879 */ 0x35f4, /* VPUNPCKHDQZ128rmkz */ 0x35f7, /* VPUNPCKHDQZ128rrkz */ /* Table9881 */ 0x209a, /* VPACKSSDWZ128rmkz */ 0x209d, /* VPACKSSDWZ128rrkz */ /* Table9883 */ 0x1dc0, /* VMOVDQA32Z128rmkz */ 0x1dc5, /* VMOVDQA32Z128rrkz */ /* Table9885 */ 0x316d, /* VPSHUFDZ128mikz */ 0x3170, /* VPSHUFDZ128rikz */ /* Table9887 */ 0x0, /* */ 0x0, /* */ 0x343e, /* VPSRLWZ128mikz */ 0x0, /* */ 0x3356, /* VPSRAWZ128mikz */ 0x0, /* */ 0x3280, /* VPSLLWZ128mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3441, /* VPSRLWZ128rikz */ 0x0, /* */ 0x3359, /* VPSRAWZ128rikz */ 0x0, /* */ 0x3283, /* VPSLLWZ128rikz */ 0x0, /* */ /* Table9903 */ 0x2f6f, /* VPRORDZ128mikz */ 0x2f03, /* VPROLDZ128mikz */ 0x338b, /* VPSRLDZ128mikz */ 0x0, /* */ 0x32ad, /* VPSRADZ128mikz */ 0x0, /* */ 0x31cd, /* VPSLLDZ128mikz */ 0x0, /* */ 0x2f72, /* VPRORDZ128rikz */ 0x2f06, /* VPROLDZ128rikz */ 0x338e, /* VPSRLDZ128rikz */ 0x0, /* */ 0x32b0, /* VPSRADZ128rikz */ 0x0, /* */ 0x31d0, /* VPSLLDZ128rikz */ 0x0, /* */ /* Table9919 */ 0x112f, /* VCVTTPS2UQQZ128rmkz */ 0x1132, /* VCVTTPS2UQQZ128rrkz */ /* Table9921 */ 0xf99, /* VCVTPS2UQQZ128rmkz */ 0xf9c, /* VCVTPS2UQQZ128rrkz */ /* Table9923 */ 0x10f3, /* VCVTTPS2QQZ128rmkz */ 0x10f6, /* VCVTTPS2QQZ128rrkz */ /* Table9925 */ 0xf5d, /* VCVTPS2QQZ128rmkz */ 0xf60, /* VCVTPS2QQZ128rrkz */ /* Table9927 */ 0x0, /* */ 0x1dc6, /* VMOVDQA32Z128rrkz_REV */ /* Table9929 */ 0x3444, /* VPSRLWZ128rmkz */ 0x3447, /* VPSRLWZ128rrkz */ /* Table9931 */ 0x3391, /* VPSRLDZ128rmkz */ 0x3394, /* VPSRLDZ128rrkz */ /* Table9933 */ 0x2e1a, /* VPMULLWZ128rmkz */ 0x2e1d, /* VPMULLWZ128rrkz */ /* Table9935 */ 0x34e7, /* VPSUBUSBZ128rmkz */ 0x34ea, /* VPSUBUSBZ128rrkz */ /* Table9937 */ 0x34fd, /* VPSUBUSWZ128rmkz */ 0x3500, /* VPSUBUSWZ128rrkz */ /* Table9939 */ 0x2ae9, /* VPMINUBZ128rmkz */ 0x2aec, /* VPMINUBZ128rrkz */ /* Table9941 */ 0x21da, /* VPANDDZ128rmkz */ 0x21dd, /* VPANDDZ128rrkz */ /* Table9943 */ 0x2181, /* VPADDUSBZ128rmkz */ 0x2184, /* VPADDUSBZ128rrkz */ /* Table9945 */ 0x2197, /* VPADDUSWZ128rmkz */ 0x219a, /* VPADDUSWZ128rrkz */ /* Table9947 */ 0x2a1d, /* VPMAXUBZ128rmkz */ 0x2a20, /* VPMAXUBZ128rrkz */ /* Table9949 */ 0x21f5, /* VPANDNDZ128rmkz */ 0x21f8, /* VPANDNDZ128rrkz */ /* Table9951 */ 0x224d, /* VPAVGBZ128rmkz */ 0x2250, /* VPAVGBZ128rrkz */ /* Table9953 */ 0x335c, /* VPSRAWZ128rmkz */ 0x335f, /* VPSRAWZ128rrkz */ /* Table9955 */ 0x32b3, /* VPSRADZ128rmkz */ 0x32b6, /* VPSRADZ128rrkz */ /* Table9957 */ 0x2263, /* VPAVGWZ128rmkz */ 0x2266, /* VPAVGWZ128rrkz */ /* Table9959 */ 0x2db4, /* VPMULHUWZ128rmkz */ 0x2db7, /* VPMULHUWZ128rrkz */ /* Table9961 */ 0x2dca, /* VPMULHWZ128rmkz */ 0x2dcd, /* VPMULHWZ128rrkz */ /* Table9963 */ 0x34bb, /* VPSUBSBZ128rmkz */ 0x34be, /* VPSUBSBZ128rrkz */ /* Table9965 */ 0x34d1, /* VPSUBSWZ128rmkz */ 0x34d4, /* VPSUBSWZ128rrkz */ /* Table9967 */ 0x2ad3, /* VPMINSWZ128rmkz */ 0x2ad6, /* VPMINSWZ128rrkz */ /* Table9969 */ 0x2ec5, /* VPORDZ128rmkz */ 0x2ec8, /* VPORDZ128rrkz */ /* Table9971 */ 0x2155, /* VPADDSBZ128rmkz */ 0x2158, /* VPADDSBZ128rrkz */ /* Table9973 */ 0x216b, /* VPADDSWZ128rmkz */ 0x216e, /* VPADDSWZ128rrkz */ /* Table9975 */ 0x2a07, /* VPMAXSWZ128rmkz */ 0x2a0a, /* VPMAXSWZ128rrkz */ /* Table9977 */ 0x36b0, /* VPXORDZ128rmkz */ 0x36b3, /* VPXORDZ128rrkz */ /* Table9979 */ 0x3286, /* VPSLLWZ128rmkz */ 0x3289, /* VPSLLWZ128rrkz */ /* Table9981 */ 0x31d3, /* VPSLLDZ128rmkz */ 0x31d6, /* VPSLLDZ128rrkz */ /* Table9983 */ 0x2999, /* VPMADDWDZ128rmkz */ 0x299c, /* VPMADDWDZ128rrkz */ /* Table9985 */ 0x3467, /* VPSUBBZ128rmkz */ 0x346a, /* VPSUBBZ128rrkz */ /* Table9987 */ 0x3513, /* VPSUBWZ128rmkz */ 0x3516, /* VPSUBWZ128rrkz */ /* Table9989 */ 0x3480, /* VPSUBDZ128rmkz */ 0x3483, /* VPSUBDZ128rrkz */ /* Table9991 */ 0x2101, /* VPADDBZ128rmkz */ 0x2104, /* VPADDBZ128rrkz */ /* Table9993 */ 0x21ad, /* VPADDWZ128rmkz */ 0x21b0, /* VPADDWZ128rrkz */ /* Table9995 */ 0x211a, /* VPADDDZ128rmkz */ 0x211d, /* VPADDDZ128rrkz */ /* Table9997 */ 0xfd5, /* VCVTQQ2PSZ128rmkz */ 0xfd8, /* VCVTQQ2PSZ128rrkz */ /* Table9999 */ 0x1095, /* VCVTTPD2UDQZ128rmkz */ 0x1098, /* VCVTTPD2UDQZ128rrkz */ /* Table10001 */ 0xeae, /* VCVTPD2UDQZ128rmkz */ 0xeb1, /* VCVTPD2UDQZ128rrkz */ /* Table10003 */ 0x1e4c, /* VMOVDQU64Z128rmkz */ 0x1e51, /* VMOVDQU64Z128rrkz */ /* Table10005 */ 0x11be, /* VCVTUQQ2PDZ128rmkz */ 0x11c1, /* VCVTUQQ2PDZ128rrkz */ /* Table10007 */ 0x0, /* */ 0x1e52, /* VMOVDQU64Z128rrkz_REV */ /* Table10009 */ 0xfb7, /* VCVTQQ2PDZ128rmkz */ 0xfba, /* VCVTQQ2PDZ128rrkz */ /* Table10011 */ 0x1ed0, /* VMOVSDZrmkz */ 0x1ed5, /* VMOVSDZrrkz */ /* Table10013 */ 0x0, /* */ 0x1ed6, /* VMOVSDZrrkz_REV */ /* Table10015 */ 0x1da2, /* VMOVDDUPZ128rmkz */ 0x1da5, /* VMOVDDUPZ128rrkz */ /* Table10017 */ 0x39fa, /* VSQRTSDZm_Intkz */ 0x39fe, /* VSQRTSDZr_Intkz */ /* Table10019 */ 0xb9f, /* VADDSDZrm_Intkz */ 0xba3, /* VADDSDZrr_Intkz */ /* Table10021 */ 0x1fc8, /* VMULSDZrm_Intkz */ 0x1fcc, /* VMULSDZrr_Intkz */ /* Table10023 */ 0xffb, /* VCVTSD2SSZrm_Intkz */ 0xfff, /* VCVTSD2SSZrr_Intkz */ /* Table10025 */ 0x3a5d, /* VSUBSDZrm_Intkz */ 0x3a61, /* VSUBSDZrr_Intkz */ /* Table10027 */ 0x1d25, /* VMINSDZrm_Intkz */ 0x1d29, /* VMINSDZrr_Intkz */ /* Table10029 */ 0x1261, /* VDIVSDZrm_Intkz */ 0x1265, /* VDIVSDZrr_Intkz */ /* Table10031 */ 0x1c7a, /* VMAXSDZrm_Intkz */ 0x1c7e, /* VMAXSDZrr_Intkz */ /* Table10033 */ 0x1e0a, /* VMOVDQU16Z128rmkz */ 0x1e0f, /* VMOVDQU16Z128rrkz */ /* Table10035 */ 0x11dc, /* VCVTUQQ2PSZ128rmkz */ 0x11df, /* VCVTUQQ2PSZ128rrkz */ /* Table10037 */ 0x0, /* */ 0x1e10, /* VMOVDQU16Z128rrkz_REV */ /* Table10039 */ 0xe4e, /* VCVTPD2DQZ128rmkz */ 0xe51, /* VCVTPD2DQZ128rrkz */ /* Table10041 */ 0x1f26, /* VMOVUPDZ128rmkz */ 0x1f2b, /* VMOVUPDZ128rrkz */ /* Table10043 */ 0x0, /* */ 0x1f2c, /* VMOVUPDZ128rrkz_REV */ /* Table10045 */ 0x3ad7, /* VUNPCKLPDZ128rmkz */ 0x3ada, /* VUNPCKLPDZ128rrkz */ /* Table10047 */ 0x3a99, /* VUNPCKHPDZ128rmkz */ 0x3a9c, /* VUNPCKHPDZ128rrkz */ /* Table10049 */ 0x1d54, /* VMOVAPDZ128rmkz */ 0x1d59, /* VMOVAPDZ128rrkz */ /* Table10051 */ 0x0, /* */ 0x1d5a, /* VMOVAPDZ128rrkz_REV */ /* Table10053 */ 0x39ba, /* VSQRTPDZ128mkz */ 0x39bd, /* VSQRTPDZ128rkz */ /* Table10055 */ 0xc69, /* VANDPDZ128rmkz */ 0xc6c, /* VANDPDZ128rrkz */ /* Table10057 */ 0xc2b, /* VANDNPDZ128rmkz */ 0xc2e, /* VANDNPDZ128rrkz */ /* Table10059 */ 0x1ff0, /* VORPDZ128rmkz */ 0x1ff3, /* VORPDZ128rrkz */ /* Table10061 */ 0x3b15, /* VXORPDZ128rmkz */ 0x3b18, /* VXORPDZ128rrkz */ /* Table10063 */ 0xb5f, /* VADDPDZ128rmkz */ 0xb62, /* VADDPDZ128rrkz */ /* Table10065 */ 0x1f88, /* VMULPDZ128rmkz */ 0x1f8b, /* VMULPDZ128rrkz */ /* Table10067 */ 0xe70, /* VCVTPD2PSZ128rmkz */ 0xe73, /* VCVTPD2PSZ128rrkz */ /* Table10069 */ 0x3a1d, /* VSUBPDZ128rmkz */ 0x3a20, /* VSUBPDZ128rrkz */ /* Table10071 */ 0x1ce5, /* VMINPDZ128rmkz */ 0x1ce8, /* VMINPDZ128rrkz */ /* Table10073 */ 0x1221, /* VDIVPDZ128rmkz */ 0x1224, /* VDIVPDZ128rrkz */ /* Table10075 */ 0x1c3a, /* VMAXPDZ128rmkz */ 0x1c3d, /* VMAXPDZ128rrkz */ /* Table10077 */ 0x367d, /* VPUNPCKLQDQZ128rmkz */ 0x3680, /* VPUNPCKLQDQZ128rrkz */ /* Table10079 */ 0x3613, /* VPUNPCKHQDQZ128rmkz */ 0x3616, /* VPUNPCKHQDQZ128rrkz */ /* Table10081 */ 0x1de1, /* VMOVDQA64Z128rmkz */ 0x1de6, /* VMOVDQA64Z128rrkz */ /* Table10083 */ 0x2f8a, /* VPRORQZ128mikz */ 0x2f1e, /* VPROLQZ128mikz */ 0x0, /* */ 0x0, /* */ 0x32dd, /* VPSRAQZ128mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f8d, /* VPRORQZ128rikz */ 0x2f21, /* VPROLQZ128rikz */ 0x0, /* */ 0x0, /* */ 0x32e0, /* VPSRAQZ128rikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table10099 */ 0x0, /* */ 0x0, /* */ 0x33be, /* VPSRLQZ128mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3200, /* VPSLLQZ128mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33c1, /* VPSRLQZ128rikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3203, /* VPSLLQZ128rikz */ 0x0, /* */ /* Table10115 */ 0x10b3, /* VCVTTPD2UQQZ128rmkz */ 0x10b6, /* VCVTTPD2UQQZ128rrkz */ /* Table10117 */ 0xecc, /* VCVTPD2UQQZ128rmkz */ 0xecf, /* VCVTPD2UQQZ128rrkz */ /* Table10119 */ 0x1077, /* VCVTTPD2QQZ128rmkz */ 0x107a, /* VCVTTPD2QQZ128rrkz */ /* Table10121 */ 0xe90, /* VCVTPD2QQZ128rmkz */ 0xe93, /* VCVTPD2QQZ128rrkz */ /* Table10123 */ 0x0, /* */ 0x1de7, /* VMOVDQA64Z128rrkz_REV */ /* Table10125 */ 0x397c, /* VSHUFPDZ128rmikz */ 0x397f, /* VSHUFPDZ128rrikz */ /* Table10127 */ 0x33c4, /* VPSRLQZ128rmkz */ 0x33c7, /* VPSRLQZ128rrkz */ /* Table10129 */ 0x2139, /* VPADDQZ128rmkz */ 0x213c, /* VPADDQZ128rrkz */ /* Table10131 */ 0x222f, /* VPANDQZ128rmkz */ 0x2232, /* VPANDQZ128rrkz */ /* Table10133 */ 0x2210, /* VPANDNQZ128rmkz */ 0x2213, /* VPANDNQZ128rrkz */ /* Table10135 */ 0x32e3, /* VPSRAQZ128rmkz */ 0x32e6, /* VPSRAQZ128rrkz */ /* Table10137 */ 0x1057, /* VCVTTPD2DQZ128rmkz */ 0x105a, /* VCVTTPD2DQZ128rrkz */ /* Table10139 */ 0x2ee0, /* VPORQZ128rmkz */ 0x2ee3, /* VPORQZ128rrkz */ /* Table10141 */ 0x36cb, /* VPXORQZ128rmkz */ 0x36ce, /* VPXORQZ128rrkz */ /* Table10143 */ 0x3206, /* VPSLLQZ128rmkz */ 0x3209, /* VPSLLQZ128rrkz */ /* Table10145 */ 0x2e4e, /* VPMULUDQZ128rmkz */ 0x2e51, /* VPMULUDQZ128rrkz */ /* Table10147 */ 0x349f, /* VPSUBQZ128rmkz */ 0x34a2, /* VPSUBQZ128rrkz */ /* Table10149 */ 0x1f5a, /* VMOVUPSZ256rmkz */ 0x1f5f, /* VMOVUPSZ256rrkz */ /* Table10151 */ 0x0, /* */ 0x1f60, /* VMOVUPSZ256rrkz_REV */ /* Table10153 */ 0x3aff, /* VUNPCKLPSZ256rmkz */ 0x3b02, /* VUNPCKLPSZ256rrkz */ /* Table10155 */ 0x3ac1, /* VUNPCKHPSZ256rmkz */ 0x3ac4, /* VUNPCKHPSZ256rrkz */ /* Table10157 */ 0x1d88, /* VMOVAPSZ256rmkz */ 0x1d8d, /* VMOVAPSZ256rrkz */ /* Table10159 */ 0x0, /* */ 0x1d8e, /* VMOVAPSZ256rrkz_REV */ /* Table10161 */ 0x39e5, /* VSQRTPSZ256mkz */ 0x39e8, /* VSQRTPSZ256rkz */ /* Table10163 */ 0xc91, /* VANDPSZ256rmkz */ 0xc94, /* VANDPSZ256rrkz */ /* Table10165 */ 0xc53, /* VANDNPSZ256rmkz */ 0xc56, /* VANDNPSZ256rrkz */ /* Table10167 */ 0x2018, /* VORPSZ256rmkz */ 0x201b, /* VORPSZ256rrkz */ /* Table10169 */ 0x3b3d, /* VXORPSZ256rmkz */ 0x3b40, /* VXORPSZ256rrkz */ /* Table10171 */ 0xb8a, /* VADDPSZ256rmkz */ 0xb8d, /* VADDPSZ256rrkz */ /* Table10173 */ 0x1fb3, /* VMULPSZ256rmkz */ 0x1fb6, /* VMULPSZ256rrkz */ /* Table10175 */ 0xf30, /* VCVTPS2PDZ256rmkz */ 0xf33, /* VCVTPS2PDZ256rrkz */ /* Table10177 */ 0xe35, /* VCVTDQ2PSZ256rmkz */ 0xe38, /* VCVTDQ2PSZ256rrkz */ /* Table10179 */ 0x3a48, /* VSUBPSZ256rmkz */ 0x3a4b, /* VSUBPSZ256rrkz */ /* Table10181 */ 0x1d10, /* VMINPSZ256rmkz */ 0x1d13, /* VMINPSZ256rrkz */ /* Table10183 */ 0x124c, /* VDIVPSZ256rmkz */ 0x124f, /* VDIVPSZ256rrkz */ /* Table10185 */ 0x1c65, /* VMAXPSZ256rmkz */ 0x1c68, /* VMAXPSZ256rrkz */ /* Table10187 */ 0x111a, /* VCVTTPS2UDQZ256rmkz */ 0x111d, /* VCVTTPS2UDQZ256rrkz */ /* Table10189 */ 0xf84, /* VCVTPS2UDQZ256rmkz */ 0xf87, /* VCVTPS2UDQZ256rrkz */ /* Table10191 */ 0x39a4, /* VSHUFPSZ256rmikz */ 0x39a7, /* VSHUFPSZ256rrikz */ /* Table10193 */ 0x1eff, /* VMOVSLDUPZ256rmkz */ 0x1f02, /* VMOVSLDUPZ256rrkz */ /* Table10195 */ 0x1ee9, /* VMOVSHDUPZ256rmkz */ 0x1eec, /* VMOVSHDUPZ256rrkz */ /* Table10197 */ 0x10dc, /* VCVTTPS2DQZ256rmkz */ 0x10df, /* VCVTTPS2DQZ256rrkz */ /* Table10199 */ 0x1e36, /* VMOVDQU32Z256rmkz */ 0x1e3b, /* VMOVDQU32Z256rrkz */ /* Table10201 */ 0x318f, /* VPSHUFHWZ256mikz */ 0x3192, /* VPSHUFHWZ256rikz */ /* Table10203 */ 0x118e, /* VCVTUDQ2PDZ256rmkz */ 0x1191, /* VCVTUDQ2PDZ256rrkz */ /* Table10205 */ 0x0, /* */ 0x1e3c, /* VMOVDQU32Z256rrkz_REV */ /* Table10207 */ 0xe16, /* VCVTDQ2PDZ256rmkz */ 0xe19, /* VCVTDQ2PDZ256rrkz */ /* Table10209 */ 0x1e78, /* VMOVDQU8Z256rmkz */ 0x1e7d, /* VMOVDQU8Z256rrkz */ /* Table10211 */ 0x31a5, /* VPSHUFLWZ256mikz */ 0x31a8, /* VPSHUFLWZ256rikz */ /* Table10213 */ 0x11a9, /* VCVTUDQ2PSZ256rmkz */ 0x11ac, /* VCVTUDQ2PSZ256rrkz */ /* Table10215 */ 0x0, /* */ 0x1e7e, /* VMOVDQU8Z256rrkz_REV */ /* Table10217 */ 0xf0e, /* VCVTPS2DQZ256rmkz */ 0xf11, /* VCVTPS2DQZ256rrkz */ /* Table10219 */ 0x364b, /* VPUNPCKLBWZ256rmkz */ 0x364e, /* VPUNPCKLBWZ256rrkz */ /* Table10221 */ 0x369f, /* VPUNPCKLWDZ256rmkz */ 0x36a2, /* VPUNPCKLWDZ256rrkz */ /* Table10223 */ 0x3667, /* VPUNPCKLDQZ256rmkz */ 0x366a, /* VPUNPCKLDQZ256rrkz */ /* Table10225 */ 0x20bc, /* VPACKSSWBZ256rmkz */ 0x20bf, /* VPACKSSWBZ256rrkz */ /* Table10227 */ 0x20f1, /* VPACKUSWBZ256rmkz */ 0x20f4, /* VPACKUSWBZ256rrkz */ /* Table10229 */ 0x35e1, /* VPUNPCKHBWZ256rmkz */ 0x35e4, /* VPUNPCKHBWZ256rrkz */ /* Table10231 */ 0x3635, /* VPUNPCKHWDZ256rmkz */ 0x3638, /* VPUNPCKHWDZ256rrkz */ /* Table10233 */ 0x35fd, /* VPUNPCKHDQZ256rmkz */ 0x3600, /* VPUNPCKHDQZ256rrkz */ /* Table10235 */ 0x20a3, /* VPACKSSDWZ256rmkz */ 0x20a6, /* VPACKSSDWZ256rrkz */ /* Table10237 */ 0x1dcb, /* VMOVDQA32Z256rmkz */ 0x1dd0, /* VMOVDQA32Z256rrkz */ /* Table10239 */ 0x3176, /* VPSHUFDZ256mikz */ 0x3179, /* VPSHUFDZ256rikz */ /* Table10241 */ 0x0, /* */ 0x0, /* */ 0x344a, /* VPSRLWZ256mikz */ 0x0, /* */ 0x3362, /* VPSRAWZ256mikz */ 0x0, /* */ 0x328c, /* VPSLLWZ256mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x344d, /* VPSRLWZ256rikz */ 0x0, /* */ 0x3365, /* VPSRAWZ256rikz */ 0x0, /* */ 0x328f, /* VPSLLWZ256rikz */ 0x0, /* */ /* Table10257 */ 0x2f78, /* VPRORDZ256mikz */ 0x2f0c, /* VPROLDZ256mikz */ 0x339a, /* VPSRLDZ256mikz */ 0x0, /* */ 0x32bc, /* VPSRADZ256mikz */ 0x0, /* */ 0x31dc, /* VPSLLDZ256mikz */ 0x0, /* */ 0x2f7b, /* VPRORDZ256rikz */ 0x2f0f, /* VPROLDZ256rikz */ 0x339d, /* VPSRLDZ256rikz */ 0x0, /* */ 0x32bf, /* VPSRADZ256rikz */ 0x0, /* */ 0x31df, /* VPSLLDZ256rikz */ 0x0, /* */ /* Table10273 */ 0x1138, /* VCVTTPS2UQQZ256rmkz */ 0x113b, /* VCVTTPS2UQQZ256rrkz */ /* Table10275 */ 0xfa2, /* VCVTPS2UQQZ256rmkz */ 0xfa5, /* VCVTPS2UQQZ256rrkz */ /* Table10277 */ 0x10fc, /* VCVTTPS2QQZ256rmkz */ 0x10ff, /* VCVTTPS2QQZ256rrkz */ /* Table10279 */ 0xf66, /* VCVTPS2QQZ256rmkz */ 0xf69, /* VCVTPS2QQZ256rrkz */ /* Table10281 */ 0x0, /* */ 0x1dd1, /* VMOVDQA32Z256rrkz_REV */ /* Table10283 */ 0x3450, /* VPSRLWZ256rmkz */ 0x3453, /* VPSRLWZ256rrkz */ /* Table10285 */ 0x33a0, /* VPSRLDZ256rmkz */ 0x33a3, /* VPSRLDZ256rrkz */ /* Table10287 */ 0x2e20, /* VPMULLWZ256rmkz */ 0x2e23, /* VPMULLWZ256rrkz */ /* Table10289 */ 0x34ed, /* VPSUBUSBZ256rmkz */ 0x34f0, /* VPSUBUSBZ256rrkz */ /* Table10291 */ 0x3503, /* VPSUBUSWZ256rmkz */ 0x3506, /* VPSUBUSWZ256rrkz */ /* Table10293 */ 0x2aef, /* VPMINUBZ256rmkz */ 0x2af2, /* VPMINUBZ256rrkz */ /* Table10295 */ 0x21e3, /* VPANDDZ256rmkz */ 0x21e6, /* VPANDDZ256rrkz */ /* Table10297 */ 0x2187, /* VPADDUSBZ256rmkz */ 0x218a, /* VPADDUSBZ256rrkz */ /* Table10299 */ 0x219d, /* VPADDUSWZ256rmkz */ 0x21a0, /* VPADDUSWZ256rrkz */ /* Table10301 */ 0x2a23, /* VPMAXUBZ256rmkz */ 0x2a26, /* VPMAXUBZ256rrkz */ /* Table10303 */ 0x21fe, /* VPANDNDZ256rmkz */ 0x2201, /* VPANDNDZ256rrkz */ /* Table10305 */ 0x2253, /* VPAVGBZ256rmkz */ 0x2256, /* VPAVGBZ256rrkz */ /* Table10307 */ 0x3368, /* VPSRAWZ256rmkz */ 0x336b, /* VPSRAWZ256rrkz */ /* Table10309 */ 0x32c2, /* VPSRADZ256rmkz */ 0x32c5, /* VPSRADZ256rrkz */ /* Table10311 */ 0x2269, /* VPAVGWZ256rmkz */ 0x226c, /* VPAVGWZ256rrkz */ /* Table10313 */ 0x2dba, /* VPMULHUWZ256rmkz */ 0x2dbd, /* VPMULHUWZ256rrkz */ /* Table10315 */ 0x2dd0, /* VPMULHWZ256rmkz */ 0x2dd3, /* VPMULHWZ256rrkz */ /* Table10317 */ 0x34c1, /* VPSUBSBZ256rmkz */ 0x34c4, /* VPSUBSBZ256rrkz */ /* Table10319 */ 0x34d7, /* VPSUBSWZ256rmkz */ 0x34da, /* VPSUBSWZ256rrkz */ /* Table10321 */ 0x2ad9, /* VPMINSWZ256rmkz */ 0x2adc, /* VPMINSWZ256rrkz */ /* Table10323 */ 0x2ece, /* VPORDZ256rmkz */ 0x2ed1, /* VPORDZ256rrkz */ /* Table10325 */ 0x215b, /* VPADDSBZ256rmkz */ 0x215e, /* VPADDSBZ256rrkz */ /* Table10327 */ 0x2171, /* VPADDSWZ256rmkz */ 0x2174, /* VPADDSWZ256rrkz */ /* Table10329 */ 0x2a0d, /* VPMAXSWZ256rmkz */ 0x2a10, /* VPMAXSWZ256rrkz */ /* Table10331 */ 0x36b9, /* VPXORDZ256rmkz */ 0x36bc, /* VPXORDZ256rrkz */ /* Table10333 */ 0x3292, /* VPSLLWZ256rmkz */ 0x3295, /* VPSLLWZ256rrkz */ /* Table10335 */ 0x31e2, /* VPSLLDZ256rmkz */ 0x31e5, /* VPSLLDZ256rrkz */ /* Table10337 */ 0x299f, /* VPMADDWDZ256rmkz */ 0x29a2, /* VPMADDWDZ256rrkz */ /* Table10339 */ 0x346d, /* VPSUBBZ256rmkz */ 0x3470, /* VPSUBBZ256rrkz */ /* Table10341 */ 0x3519, /* VPSUBWZ256rmkz */ 0x351c, /* VPSUBWZ256rrkz */ /* Table10343 */ 0x3489, /* VPSUBDZ256rmkz */ 0x348c, /* VPSUBDZ256rrkz */ /* Table10345 */ 0x2107, /* VPADDBZ256rmkz */ 0x210a, /* VPADDBZ256rrkz */ /* Table10347 */ 0x21b3, /* VPADDWZ256rmkz */ 0x21b6, /* VPADDWZ256rrkz */ /* Table10349 */ 0x2123, /* VPADDDZ256rmkz */ 0x2126, /* VPADDDZ256rrkz */ /* Table10351 */ 0xfde, /* VCVTQQ2PSZ256rmkz */ 0xfe1, /* VCVTQQ2PSZ256rrkz */ /* Table10353 */ 0x109e, /* VCVTTPD2UDQZ256rmkz */ 0x10a1, /* VCVTTPD2UDQZ256rrkz */ /* Table10355 */ 0xeb7, /* VCVTPD2UDQZ256rmkz */ 0xeba, /* VCVTPD2UDQZ256rrkz */ /* Table10357 */ 0x1e57, /* VMOVDQU64Z256rmkz */ 0x1e5c, /* VMOVDQU64Z256rrkz */ /* Table10359 */ 0x11c7, /* VCVTUQQ2PDZ256rmkz */ 0x11ca, /* VCVTUQQ2PDZ256rrkz */ /* Table10361 */ 0x0, /* */ 0x1e5d, /* VMOVDQU64Z256rrkz_REV */ /* Table10363 */ 0xfc0, /* VCVTQQ2PDZ256rmkz */ 0xfc3, /* VCVTQQ2PDZ256rrkz */ /* Table10365 */ 0x1da8, /* VMOVDDUPZ256rmkz */ 0x1dab, /* VMOVDDUPZ256rrkz */ /* Table10367 */ 0x1e15, /* VMOVDQU16Z256rmkz */ 0x1e1a, /* VMOVDQU16Z256rrkz */ /* Table10369 */ 0x11e5, /* VCVTUQQ2PSZ256rmkz */ 0x11e8, /* VCVTUQQ2PSZ256rrkz */ /* Table10371 */ 0x0, /* */ 0x1e1b, /* VMOVDQU16Z256rrkz_REV */ /* Table10373 */ 0xe57, /* VCVTPD2DQZ256rmkz */ 0xe5a, /* VCVTPD2DQZ256rrkz */ /* Table10375 */ 0x1f31, /* VMOVUPDZ256rmkz */ 0x1f36, /* VMOVUPDZ256rrkz */ /* Table10377 */ 0x0, /* */ 0x1f37, /* VMOVUPDZ256rrkz_REV */ /* Table10379 */ 0x3ae0, /* VUNPCKLPDZ256rmkz */ 0x3ae3, /* VUNPCKLPDZ256rrkz */ /* Table10381 */ 0x3aa2, /* VUNPCKHPDZ256rmkz */ 0x3aa5, /* VUNPCKHPDZ256rrkz */ /* Table10383 */ 0x1d5f, /* VMOVAPDZ256rmkz */ 0x1d64, /* VMOVAPDZ256rrkz */ /* Table10385 */ 0x0, /* */ 0x1d65, /* VMOVAPDZ256rrkz_REV */ /* Table10387 */ 0x39c3, /* VSQRTPDZ256mkz */ 0x39c6, /* VSQRTPDZ256rkz */ /* Table10389 */ 0xc72, /* VANDPDZ256rmkz */ 0xc75, /* VANDPDZ256rrkz */ /* Table10391 */ 0xc34, /* VANDNPDZ256rmkz */ 0xc37, /* VANDNPDZ256rrkz */ /* Table10393 */ 0x1ff9, /* VORPDZ256rmkz */ 0x1ffc, /* VORPDZ256rrkz */ /* Table10395 */ 0x3b1e, /* VXORPDZ256rmkz */ 0x3b21, /* VXORPDZ256rrkz */ /* Table10397 */ 0xb68, /* VADDPDZ256rmkz */ 0xb6b, /* VADDPDZ256rrkz */ /* Table10399 */ 0x1f91, /* VMULPDZ256rmkz */ 0x1f94, /* VMULPDZ256rrkz */ /* Table10401 */ 0xe79, /* VCVTPD2PSZ256rmkz */ 0xe7c, /* VCVTPD2PSZ256rrkz */ /* Table10403 */ 0x3a26, /* VSUBPDZ256rmkz */ 0x3a29, /* VSUBPDZ256rrkz */ /* Table10405 */ 0x1cee, /* VMINPDZ256rmkz */ 0x1cf1, /* VMINPDZ256rrkz */ /* Table10407 */ 0x122a, /* VDIVPDZ256rmkz */ 0x122d, /* VDIVPDZ256rrkz */ /* Table10409 */ 0x1c43, /* VMAXPDZ256rmkz */ 0x1c46, /* VMAXPDZ256rrkz */ /* Table10411 */ 0x3686, /* VPUNPCKLQDQZ256rmkz */ 0x3689, /* VPUNPCKLQDQZ256rrkz */ /* Table10413 */ 0x361c, /* VPUNPCKHQDQZ256rmkz */ 0x361f, /* VPUNPCKHQDQZ256rrkz */ /* Table10415 */ 0x1dec, /* VMOVDQA64Z256rmkz */ 0x1df1, /* VMOVDQA64Z256rrkz */ /* Table10417 */ 0x2f93, /* VPRORQZ256mikz */ 0x2f27, /* VPROLQZ256mikz */ 0x0, /* */ 0x0, /* */ 0x32ec, /* VPSRAQZ256mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f96, /* VPRORQZ256rikz */ 0x2f2a, /* VPROLQZ256rikz */ 0x0, /* */ 0x0, /* */ 0x32ef, /* VPSRAQZ256rikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table10433 */ 0x0, /* */ 0x0, /* */ 0x33cd, /* VPSRLQZ256mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x320f, /* VPSLLQZ256mikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33d0, /* VPSRLQZ256rikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3212, /* VPSLLQZ256rikz */ 0x0, /* */ /* Table10449 */ 0x10bc, /* VCVTTPD2UQQZ256rmkz */ 0x10bf, /* VCVTTPD2UQQZ256rrkz */ /* Table10451 */ 0xed5, /* VCVTPD2UQQZ256rmkz */ 0xed8, /* VCVTPD2UQQZ256rrkz */ /* Table10453 */ 0x1080, /* VCVTTPD2QQZ256rmkz */ 0x1083, /* VCVTTPD2QQZ256rrkz */ /* Table10455 */ 0xe99, /* VCVTPD2QQZ256rmkz */ 0xe9c, /* VCVTPD2QQZ256rrkz */ /* Table10457 */ 0x0, /* */ 0x1df2, /* VMOVDQA64Z256rrkz_REV */ /* Table10459 */ 0x3985, /* VSHUFPDZ256rmikz */ 0x3988, /* VSHUFPDZ256rrikz */ /* Table10461 */ 0x33d3, /* VPSRLQZ256rmkz */ 0x33d6, /* VPSRLQZ256rrkz */ /* Table10463 */ 0x2142, /* VPADDQZ256rmkz */ 0x2145, /* VPADDQZ256rrkz */ /* Table10465 */ 0x2238, /* VPANDQZ256rmkz */ 0x223b, /* VPANDQZ256rrkz */ /* Table10467 */ 0x2219, /* VPANDNQZ256rmkz */ 0x221c, /* VPANDNQZ256rrkz */ /* Table10469 */ 0x32f2, /* VPSRAQZ256rmkz */ 0x32f5, /* VPSRAQZ256rrkz */ /* Table10471 */ 0x1060, /* VCVTTPD2DQZ256rmkz */ 0x1063, /* VCVTTPD2DQZ256rrkz */ /* Table10473 */ 0x2ee9, /* VPORQZ256rmkz */ 0x2eec, /* VPORQZ256rrkz */ /* Table10475 */ 0x36d4, /* VPXORQZ256rmkz */ 0x36d7, /* VPXORQZ256rrkz */ /* Table10477 */ 0x3215, /* VPSLLQZ256rmkz */ 0x3218, /* VPSLLQZ256rrkz */ /* Table10479 */ 0x2e57, /* VPMULUDQZ256rmkz */ 0x2e5a, /* VPMULUDQZ256rrkz */ /* Table10481 */ 0x34a8, /* VPSUBQZ256rmkz */ 0x34ab, /* VPSUBQZ256rrkz */ /* Table10483 */ 0x1f65, /* VMOVUPSZrmkz */ 0x1f6a, /* VMOVUPSZrrkz */ /* Table10485 */ 0x0, /* */ 0x1f6b, /* VMOVUPSZrrkz_REV */ /* Table10487 */ 0x3b08, /* VUNPCKLPSZrmkz */ 0x3b0b, /* VUNPCKLPSZrrkz */ /* Table10489 */ 0x3aca, /* VUNPCKHPSZrmkz */ 0x3acd, /* VUNPCKHPSZrrkz */ /* Table10491 */ 0x1d93, /* VMOVAPSZrmkz */ 0x1d98, /* VMOVAPSZrrkz */ /* Table10493 */ 0x0, /* */ 0x1d99, /* VMOVAPSZrrkz_REV */ /* Table10495 */ 0x39ee, /* VSQRTPSZmkz */ 0x39f4, /* VSQRTPSZrkz */ /* Table10497 */ 0xc9a, /* VANDPSZrmkz */ 0xc9d, /* VANDPSZrrkz */ /* Table10499 */ 0xc5c, /* VANDNPSZrmkz */ 0xc5f, /* VANDNPSZrrkz */ /* Table10501 */ 0x2021, /* VORPSZrmkz */ 0x2024, /* VORPSZrrkz */ /* Table10503 */ 0x3b46, /* VXORPSZrmkz */ 0x3b49, /* VXORPSZrrkz */ /* Table10505 */ 0xb93, /* VADDPSZrmkz */ 0xb99, /* VADDPSZrrkz */ /* Table10507 */ 0x1fbc, /* VMULPSZrmkz */ 0x1fc2, /* VMULPSZrrkz */ /* Table10509 */ 0xf39, /* VCVTPS2PDZrmkz */ 0xf3f, /* VCVTPS2PDZrrkz */ /* Table10511 */ 0xe3e, /* VCVTDQ2PSZrmkz */ 0xe44, /* VCVTDQ2PSZrrkz */ /* Table10513 */ 0x3a51, /* VSUBPSZrmkz */ 0x3a57, /* VSUBPSZrrkz */ /* Table10515 */ 0x1d19, /* VMINPSZrmkz */ 0x1d1f, /* VMINPSZrrkz */ /* Table10517 */ 0x1255, /* VDIVPSZrmkz */ 0x125b, /* VDIVPSZrrkz */ /* Table10519 */ 0x1c6e, /* VMAXPSZrmkz */ 0x1c74, /* VMAXPSZrrkz */ /* Table10521 */ 0x1123, /* VCVTTPS2UDQZrmkz */ 0x1129, /* VCVTTPS2UDQZrrkz */ /* Table10523 */ 0xf8d, /* VCVTPS2UDQZrmkz */ 0xf93, /* VCVTPS2UDQZrrkz */ /* Table10525 */ 0x39ad, /* VSHUFPSZrmikz */ 0x39b0, /* VSHUFPSZrrikz */ /* Table10527 */ 0x1f05, /* VMOVSLDUPZrmkz */ 0x1f08, /* VMOVSLDUPZrrkz */ /* Table10529 */ 0x1eef, /* VMOVSHDUPZrmkz */ 0x1ef2, /* VMOVSHDUPZrrkz */ /* Table10531 */ 0x10e5, /* VCVTTPS2DQZrmkz */ 0x10eb, /* VCVTTPS2DQZrrkz */ /* Table10533 */ 0x1e41, /* VMOVDQU32Zrmkz */ 0x1e46, /* VMOVDQU32Zrrkz */ /* Table10535 */ 0x3195, /* VPSHUFHWZmikz */ 0x3198, /* VPSHUFHWZrikz */ /* Table10537 */ 0x1197, /* VCVTUDQ2PDZrmkz */ 0x119a, /* VCVTUDQ2PDZrrkz */ /* Table10539 */ 0x0, /* */ 0x1e47, /* VMOVDQU32Zrrkz_REV */ /* Table10541 */ 0xe1f, /* VCVTDQ2PDZrmkz */ 0xe22, /* VCVTDQ2PDZrrkz */ /* Table10543 */ 0x1e83, /* VMOVDQU8Zrmkz */ 0x1e88, /* VMOVDQU8Zrrkz */ /* Table10545 */ 0x31ab, /* VPSHUFLWZmikz */ 0x31ae, /* VPSHUFLWZrikz */ /* Table10547 */ 0x11b2, /* VCVTUDQ2PSZrmkz */ 0x11b8, /* VCVTUDQ2PSZrrkz */ /* Table10549 */ 0x0, /* */ 0x1e89, /* VMOVDQU8Zrrkz_REV */ /* Table10551 */ 0xf17, /* VCVTPS2DQZrmkz */ 0xf1d, /* VCVTPS2DQZrrkz */ /* Table10553 */ 0x3651, /* VPUNPCKLBWZrmkz */ 0x3654, /* VPUNPCKLBWZrrkz */ /* Table10555 */ 0x36a5, /* VPUNPCKLWDZrmkz */ 0x36a8, /* VPUNPCKLWDZrrkz */ /* Table10557 */ 0x3670, /* VPUNPCKLDQZrmkz */ 0x3673, /* VPUNPCKLDQZrrkz */ /* Table10559 */ 0x20c2, /* VPACKSSWBZrmkz */ 0x20c5, /* VPACKSSWBZrrkz */ /* Table10561 */ 0x20f7, /* VPACKUSWBZrmkz */ 0x20fa, /* VPACKUSWBZrrkz */ /* Table10563 */ 0x35e7, /* VPUNPCKHBWZrmkz */ 0x35ea, /* VPUNPCKHBWZrrkz */ /* Table10565 */ 0x363b, /* VPUNPCKHWDZrmkz */ 0x363e, /* VPUNPCKHWDZrrkz */ /* Table10567 */ 0x3606, /* VPUNPCKHDQZrmkz */ 0x3609, /* VPUNPCKHDQZrrkz */ /* Table10569 */ 0x20ac, /* VPACKSSDWZrmkz */ 0x20af, /* VPACKSSDWZrrkz */ /* Table10571 */ 0x1dd6, /* VMOVDQA32Zrmkz */ 0x1ddb, /* VMOVDQA32Zrrkz */ /* Table10573 */ 0x317f, /* VPSHUFDZmikz */ 0x3182, /* VPSHUFDZrikz */ /* Table10575 */ 0x0, /* */ 0x0, /* */ 0x3456, /* VPSRLWZmikz */ 0x0, /* */ 0x336e, /* VPSRAWZmikz */ 0x0, /* */ 0x3298, /* VPSLLWZmikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3459, /* VPSRLWZrikz */ 0x0, /* */ 0x3371, /* VPSRAWZrikz */ 0x0, /* */ 0x329b, /* VPSLLWZrikz */ 0x0, /* */ /* Table10591 */ 0x2f81, /* VPRORDZmikz */ 0x2f15, /* VPROLDZmikz */ 0x33a9, /* VPSRLDZmikz */ 0x0, /* */ 0x32cb, /* VPSRADZmikz */ 0x0, /* */ 0x31eb, /* VPSLLDZmikz */ 0x0, /* */ 0x2f84, /* VPRORDZrikz */ 0x2f18, /* VPROLDZrikz */ 0x33ac, /* VPSRLDZrikz */ 0x0, /* */ 0x32ce, /* VPSRADZrikz */ 0x0, /* */ 0x31ee, /* VPSLLDZrikz */ 0x0, /* */ /* Table10607 */ 0x1141, /* VCVTTPS2UQQZrmkz */ 0x1147, /* VCVTTPS2UQQZrrkz */ /* Table10609 */ 0xfab, /* VCVTPS2UQQZrmkz */ 0xfb1, /* VCVTPS2UQQZrrkz */ /* Table10611 */ 0x1105, /* VCVTTPS2QQZrmkz */ 0x110b, /* VCVTTPS2QQZrrkz */ /* Table10613 */ 0xf6f, /* VCVTPS2QQZrmkz */ 0xf75, /* VCVTPS2QQZrrkz */ /* Table10615 */ 0x0, /* */ 0x1ddc, /* VMOVDQA32Zrrkz_REV */ /* Table10617 */ 0x345c, /* VPSRLWZrmkz */ 0x345f, /* VPSRLWZrrkz */ /* Table10619 */ 0x33af, /* VPSRLDZrmkz */ 0x33b2, /* VPSRLDZrrkz */ /* Table10621 */ 0x2e26, /* VPMULLWZrmkz */ 0x2e29, /* VPMULLWZrrkz */ /* Table10623 */ 0x34f3, /* VPSUBUSBZrmkz */ 0x34f6, /* VPSUBUSBZrrkz */ /* Table10625 */ 0x3509, /* VPSUBUSWZrmkz */ 0x350c, /* VPSUBUSWZrrkz */ /* Table10627 */ 0x2af5, /* VPMINUBZrmkz */ 0x2af8, /* VPMINUBZrrkz */ /* Table10629 */ 0x21ec, /* VPANDDZrmkz */ 0x21ef, /* VPANDDZrrkz */ /* Table10631 */ 0x218d, /* VPADDUSBZrmkz */ 0x2190, /* VPADDUSBZrrkz */ /* Table10633 */ 0x21a3, /* VPADDUSWZrmkz */ 0x21a6, /* VPADDUSWZrrkz */ /* Table10635 */ 0x2a29, /* VPMAXUBZrmkz */ 0x2a2c, /* VPMAXUBZrrkz */ /* Table10637 */ 0x2207, /* VPANDNDZrmkz */ 0x220a, /* VPANDNDZrrkz */ /* Table10639 */ 0x2259, /* VPAVGBZrmkz */ 0x225c, /* VPAVGBZrrkz */ /* Table10641 */ 0x3374, /* VPSRAWZrmkz */ 0x3377, /* VPSRAWZrrkz */ /* Table10643 */ 0x32d1, /* VPSRADZrmkz */ 0x32d4, /* VPSRADZrrkz */ /* Table10645 */ 0x226f, /* VPAVGWZrmkz */ 0x2272, /* VPAVGWZrrkz */ /* Table10647 */ 0x2dc0, /* VPMULHUWZrmkz */ 0x2dc3, /* VPMULHUWZrrkz */ /* Table10649 */ 0x2dd6, /* VPMULHWZrmkz */ 0x2dd9, /* VPMULHWZrrkz */ /* Table10651 */ 0x34c7, /* VPSUBSBZrmkz */ 0x34ca, /* VPSUBSBZrrkz */ /* Table10653 */ 0x34dd, /* VPSUBSWZrmkz */ 0x34e0, /* VPSUBSWZrrkz */ /* Table10655 */ 0x2adf, /* VPMINSWZrmkz */ 0x2ae2, /* VPMINSWZrrkz */ /* Table10657 */ 0x2ed7, /* VPORDZrmkz */ 0x2eda, /* VPORDZrrkz */ /* Table10659 */ 0x2161, /* VPADDSBZrmkz */ 0x2164, /* VPADDSBZrrkz */ /* Table10661 */ 0x2177, /* VPADDSWZrmkz */ 0x217a, /* VPADDSWZrrkz */ /* Table10663 */ 0x2a13, /* VPMAXSWZrmkz */ 0x2a16, /* VPMAXSWZrrkz */ /* Table10665 */ 0x36c2, /* VPXORDZrmkz */ 0x36c5, /* VPXORDZrrkz */ /* Table10667 */ 0x329e, /* VPSLLWZrmkz */ 0x32a1, /* VPSLLWZrrkz */ /* Table10669 */ 0x31f1, /* VPSLLDZrmkz */ 0x31f4, /* VPSLLDZrrkz */ /* Table10671 */ 0x29a5, /* VPMADDWDZrmkz */ 0x29a8, /* VPMADDWDZrrkz */ /* Table10673 */ 0x3473, /* VPSUBBZrmkz */ 0x3476, /* VPSUBBZrrkz */ /* Table10675 */ 0x351f, /* VPSUBWZrmkz */ 0x3522, /* VPSUBWZrrkz */ /* Table10677 */ 0x3492, /* VPSUBDZrmkz */ 0x3495, /* VPSUBDZrrkz */ /* Table10679 */ 0x210d, /* VPADDBZrmkz */ 0x2110, /* VPADDBZrrkz */ /* Table10681 */ 0x21b9, /* VPADDWZrmkz */ 0x21bc, /* VPADDWZrrkz */ /* Table10683 */ 0x212c, /* VPADDDZrmkz */ 0x212f, /* VPADDDZrrkz */ /* Table10685 */ 0xfe7, /* VCVTQQ2PSZrmkz */ 0xfed, /* VCVTQQ2PSZrrkz */ /* Table10687 */ 0x10a7, /* VCVTTPD2UDQZrmkz */ 0x10ad, /* VCVTTPD2UDQZrrkz */ /* Table10689 */ 0xec0, /* VCVTPD2UDQZrmkz */ 0xec6, /* VCVTPD2UDQZrrkz */ /* Table10691 */ 0x1e62, /* VMOVDQU64Zrmkz */ 0x1e67, /* VMOVDQU64Zrrkz */ /* Table10693 */ 0x11d0, /* VCVTUQQ2PDZrmkz */ 0x11d6, /* VCVTUQQ2PDZrrkz */ /* Table10695 */ 0x0, /* */ 0x1e68, /* VMOVDQU64Zrrkz_REV */ /* Table10697 */ 0xfc9, /* VCVTQQ2PDZrmkz */ 0xfcf, /* VCVTQQ2PDZrrkz */ /* Table10699 */ 0x1dae, /* VMOVDDUPZrmkz */ 0x1db1, /* VMOVDDUPZrrkz */ /* Table10701 */ 0x1e20, /* VMOVDQU16Zrmkz */ 0x1e25, /* VMOVDQU16Zrrkz */ /* Table10703 */ 0x11ee, /* VCVTUQQ2PSZrmkz */ 0x11f4, /* VCVTUQQ2PSZrrkz */ /* Table10705 */ 0x0, /* */ 0x1e26, /* VMOVDQU16Zrrkz_REV */ /* Table10707 */ 0xe60, /* VCVTPD2DQZrmkz */ 0xe66, /* VCVTPD2DQZrrkz */ /* Table10709 */ 0x1f3c, /* VMOVUPDZrmkz */ 0x1f41, /* VMOVUPDZrrkz */ /* Table10711 */ 0x0, /* */ 0x1f42, /* VMOVUPDZrrkz_REV */ /* Table10713 */ 0x3ae9, /* VUNPCKLPDZrmkz */ 0x3aec, /* VUNPCKLPDZrrkz */ /* Table10715 */ 0x3aab, /* VUNPCKHPDZrmkz */ 0x3aae, /* VUNPCKHPDZrrkz */ /* Table10717 */ 0x1d6a, /* VMOVAPDZrmkz */ 0x1d6f, /* VMOVAPDZrrkz */ /* Table10719 */ 0x0, /* */ 0x1d70, /* VMOVAPDZrrkz_REV */ /* Table10721 */ 0x39cc, /* VSQRTPDZmkz */ 0x39d2, /* VSQRTPDZrkz */ /* Table10723 */ 0xc7b, /* VANDPDZrmkz */ 0xc7e, /* VANDPDZrrkz */ /* Table10725 */ 0xc3d, /* VANDNPDZrmkz */ 0xc40, /* VANDNPDZrrkz */ /* Table10727 */ 0x2002, /* VORPDZrmkz */ 0x2005, /* VORPDZrrkz */ /* Table10729 */ 0x3b27, /* VXORPDZrmkz */ 0x3b2a, /* VXORPDZrrkz */ /* Table10731 */ 0xb71, /* VADDPDZrmkz */ 0xb77, /* VADDPDZrrkz */ /* Table10733 */ 0x1f9a, /* VMULPDZrmkz */ 0x1fa0, /* VMULPDZrrkz */ /* Table10735 */ 0xe82, /* VCVTPD2PSZrmkz */ 0xe88, /* VCVTPD2PSZrrkz */ /* Table10737 */ 0x3a2f, /* VSUBPDZrmkz */ 0x3a35, /* VSUBPDZrrkz */ /* Table10739 */ 0x1cf7, /* VMINPDZrmkz */ 0x1cfd, /* VMINPDZrrkz */ /* Table10741 */ 0x1233, /* VDIVPDZrmkz */ 0x1239, /* VDIVPDZrrkz */ /* Table10743 */ 0x1c4c, /* VMAXPDZrmkz */ 0x1c52, /* VMAXPDZrrkz */ /* Table10745 */ 0x368f, /* VPUNPCKLQDQZrmkz */ 0x3692, /* VPUNPCKLQDQZrrkz */ /* Table10747 */ 0x3625, /* VPUNPCKHQDQZrmkz */ 0x3628, /* VPUNPCKHQDQZrrkz */ /* Table10749 */ 0x1df7, /* VMOVDQA64Zrmkz */ 0x1dfc, /* VMOVDQA64Zrrkz */ /* Table10751 */ 0x2f9c, /* VPRORQZmikz */ 0x2f30, /* VPROLQZmikz */ 0x0, /* */ 0x0, /* */ 0x32fb, /* VPSRAQZmikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f9f, /* VPRORQZrikz */ 0x2f33, /* VPROLQZrikz */ 0x0, /* */ 0x0, /* */ 0x32fe, /* VPSRAQZrikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table10767 */ 0x0, /* */ 0x0, /* */ 0x33dc, /* VPSRLQZmikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x321e, /* VPSLLQZmikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33df, /* VPSRLQZrikz */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3221, /* VPSLLQZrikz */ 0x0, /* */ /* Table10783 */ 0x10c5, /* VCVTTPD2UQQZrmkz */ 0x10cb, /* VCVTTPD2UQQZrrkz */ /* Table10785 */ 0xede, /* VCVTPD2UQQZrmkz */ 0xee4, /* VCVTPD2UQQZrrkz */ /* Table10787 */ 0x1089, /* VCVTTPD2QQZrmkz */ 0x108f, /* VCVTTPD2QQZrrkz */ /* Table10789 */ 0xea2, /* VCVTPD2QQZrmkz */ 0xea8, /* VCVTPD2QQZrrkz */ /* Table10791 */ 0x0, /* */ 0x1dfd, /* VMOVDQA64Zrrkz_REV */ /* Table10793 */ 0x398e, /* VSHUFPDZrmikz */ 0x3991, /* VSHUFPDZrrikz */ /* Table10795 */ 0x33e2, /* VPSRLQZrmkz */ 0x33e5, /* VPSRLQZrrkz */ /* Table10797 */ 0x214b, /* VPADDQZrmkz */ 0x214e, /* VPADDQZrrkz */ /* Table10799 */ 0x2241, /* VPANDQZrmkz */ 0x2244, /* VPANDQZrrkz */ /* Table10801 */ 0x2222, /* VPANDNQZrmkz */ 0x2225, /* VPANDNQZrrkz */ /* Table10803 */ 0x3301, /* VPSRAQZrmkz */ 0x3304, /* VPSRAQZrrkz */ /* Table10805 */ 0x1069, /* VCVTTPD2DQZrmkz */ 0x106f, /* VCVTTPD2DQZrrkz */ /* Table10807 */ 0x2ef2, /* VPORQZrmkz */ 0x2ef5, /* VPORQZrrkz */ /* Table10809 */ 0x36dd, /* VPXORQZrmkz */ 0x36e0, /* VPXORQZrrkz */ /* Table10811 */ 0x3224, /* VPSLLQZrmkz */ 0x3227, /* VPSLLQZrrkz */ /* Table10813 */ 0x2e60, /* VPMULUDQZrmkz */ 0x2e63, /* VPMULUDQZrrkz */ /* Table10815 */ 0x34b1, /* VPSUBQZrmkz */ 0x34b4, /* VPSUBQZrrkz */ /* Table10817 */ 0x5c8, /* MMX_PSHUFBrm */ 0x5c9, /* MMX_PSHUFBrr */ /* Table10819 */ 0x5a3, /* MMX_PHADDWrm */ 0x5a4, /* MMX_PHADDWrr */ /* Table10821 */ 0x59f, /* MMX_PHADDDrm */ 0x5a0, /* MMX_PHADDDrr */ /* Table10823 */ 0x5a1, /* MMX_PHADDSWrm */ 0x5a2, /* MMX_PHADDSWrr */ /* Table10825 */ 0x5ad, /* MMX_PMADDUBSWrm */ 0x5ae, /* MMX_PMADDUBSWrr */ /* Table10827 */ 0x5a9, /* MMX_PHSUBWrm */ 0x5aa, /* MMX_PHSUBWrr */ /* Table10829 */ 0x5a5, /* MMX_PHSUBDrm */ 0x5a6, /* MMX_PHSUBDrr */ /* Table10831 */ 0x5a7, /* MMX_PHSUBSWrm */ 0x5a8, /* MMX_PHSUBSWrr */ /* Table10833 */ 0x5cc, /* MMX_PSIGNBrm */ 0x5cd, /* MMX_PSIGNBrr */ /* Table10835 */ 0x5d0, /* MMX_PSIGNWrm */ 0x5d1, /* MMX_PSIGNWrr */ /* Table10837 */ 0x5ce, /* MMX_PSIGNDrm */ 0x5cf, /* MMX_PSIGNDrr */ /* Table10839 */ 0x5ba, /* MMX_PMULHRSWrm */ 0x5bb, /* MMX_PMULHRSWrr */ /* Table10841 */ 0x56c, /* MMX_PABSBrm */ 0x56d, /* MMX_PABSBrr */ /* Table10843 */ 0x570, /* MMX_PABSWrm */ 0x571, /* MMX_PABSWrr */ /* Table10845 */ 0x56e, /* MMX_PABSDrm */ 0x56f, /* MMX_PABSDrr */ /* Table10847 */ 0x9fd, /* SHA1NEXTErm */ 0x9fe, /* SHA1NEXTErr */ /* Table10849 */ 0x9f9, /* SHA1MSG1rm */ 0x9fa, /* SHA1MSG1rr */ /* Table10851 */ 0x9fb, /* SHA1MSG2rm */ 0x9fc, /* SHA1MSG2rr */ /* Table10853 */ 0xa05, /* SHA256RNDS2rm */ 0xa06, /* SHA256RNDS2rr */ /* Table10855 */ 0xa01, /* SHA256MSG1rm */ 0xa02, /* SHA256MSG1rr */ /* Table10857 */ 0xa03, /* SHA256MSG2rm */ 0xa04, /* SHA256MSG2rr */ /* Table10859 */ 0x65f, /* MOVBE32rm */ 0x0, /* */ /* Table10861 */ 0x65e, /* MOVBE32mr */ 0x0, /* */ /* Table10863 */ 0x3b57, /* WRSSD */ 0x0, /* */ /* Table10865 */ 0x66b, /* MOVDIRI32 */ 0x0, /* */ /* Table10867 */ 0x867, /* PSHUFBrm */ 0x868, /* PSHUFBrr */ /* Table10869 */ 0x7e1, /* PHADDWrm */ 0x7e2, /* PHADDWrr */ /* Table10871 */ 0x7dd, /* PHADDDrm */ 0x7de, /* PHADDDrr */ /* Table10873 */ 0x7df, /* PHADDSWrm */ 0x7e0, /* PHADDSWrr */ /* Table10875 */ 0x7f7, /* PMADDUBSWrm */ 0x7f8, /* PMADDUBSWrr */ /* Table10877 */ 0x7e9, /* PHSUBWrm */ 0x7ea, /* PHSUBWrr */ /* Table10879 */ 0x7e5, /* PHSUBDrm */ 0x7e6, /* PHSUBDrr */ /* Table10881 */ 0x7e7, /* PHSUBSWrm */ 0x7e8, /* PHSUBSWrr */ /* Table10883 */ 0x86f, /* PSIGNBrm */ 0x870, /* PSIGNBrr */ /* Table10885 */ 0x873, /* PSIGNWrm */ 0x874, /* PSIGNWrr */ /* Table10887 */ 0x871, /* PSIGNDrm */ 0x872, /* PSIGNDrr */ /* Table10889 */ 0x82e, /* PMULHRSWrm */ 0x82f, /* PMULHRSWrr */ /* Table10891 */ 0x787, /* PBLENDVBrm0 */ 0x788, /* PBLENDVBrr0 */ /* Table10893 */ 0x16f, /* BLENDVPSrm0 */ 0x170, /* BLENDVPSrr0 */ /* Table10895 */ 0x16d, /* BLENDVPDrm0 */ 0x16e, /* BLENDVPDrr0 */ /* Table10897 */ 0x8a1, /* PTESTrm */ 0x8a2, /* PTESTrr */ /* Table10899 */ 0x75c, /* PABSBrm */ 0x75d, /* PABSBrr */ /* Table10901 */ 0x760, /* PABSWrm */ 0x761, /* PABSWrr */ /* Table10903 */ 0x75e, /* PABSDrm */ 0x75f, /* PABSDrr */ /* Table10905 */ 0x818, /* PMOVSXBWrm */ 0x819, /* PMOVSXBWrr */ /* Table10907 */ 0x814, /* PMOVSXBDrm */ 0x815, /* PMOVSXBDrr */ /* Table10909 */ 0x816, /* PMOVSXBQrm */ 0x817, /* PMOVSXBQrr */ /* Table10911 */ 0x81c, /* PMOVSXWDrm */ 0x81d, /* PMOVSXWDrr */ /* Table10913 */ 0x81e, /* PMOVSXWQrm */ 0x81f, /* PMOVSXWQrr */ /* Table10915 */ 0x81a, /* PMOVSXDQrm */ 0x81b, /* PMOVSXDQrr */ /* Table10917 */ 0x82c, /* PMULDQrm */ 0x82d, /* PMULDQrr */ /* Table10919 */ 0x791, /* PCMPEQQrm */ 0x792, /* PCMPEQQrr */ /* Table10921 */ 0x681, /* MOVNTDQArm */ 0x0, /* */ /* Table10923 */ 0x766, /* PACKUSDWrm */ 0x767, /* PACKUSDWrr */ /* Table10925 */ 0x824, /* PMOVZXBWrm */ 0x825, /* PMOVZXBWrr */ /* Table10927 */ 0x820, /* PMOVZXBDrm */ 0x821, /* PMOVZXBDrr */ /* Table10929 */ 0x822, /* PMOVZXBQrm */ 0x823, /* PMOVZXBQrr */ /* Table10931 */ 0x828, /* PMOVZXWDrm */ 0x829, /* PMOVZXWDrr */ /* Table10933 */ 0x82a, /* PMOVZXWQrm */ 0x82b, /* PMOVZXWQrr */ /* Table10935 */ 0x826, /* PMOVZXDQrm */ 0x827, /* PMOVZXDQrr */ /* Table10937 */ 0x79d, /* PCMPGTQrm */ 0x79e, /* PCMPGTQrr */ /* Table10939 */ 0x807, /* PMINSBrm */ 0x808, /* PMINSBrr */ /* Table10941 */ 0x809, /* PMINSDrm */ 0x80a, /* PMINSDrr */ /* Table10943 */ 0x811, /* PMINUWrm */ 0x812, /* PMINUWrr */ /* Table10945 */ 0x80f, /* PMINUDrm */ 0x810, /* PMINUDrr */ /* Table10947 */ 0x7fb, /* PMAXSBrm */ 0x7fc, /* PMAXSBrr */ /* Table10949 */ 0x7fd, /* PMAXSDrm */ 0x7fe, /* PMAXSDrr */ /* Table10951 */ 0x805, /* PMAXUWrm */ 0x806, /* PMAXUWrr */ /* Table10953 */ 0x803, /* PMAXUDrm */ 0x804, /* PMAXUDrr */ /* Table10955 */ 0x836, /* PMULLDrm */ 0x837, /* PMULLDrr */ /* Table10957 */ 0x7e3, /* PHMINPOSUWrm */ 0x7e4, /* PHMINPOSUWrr */ /* Table10959 */ 0x417, /* INVEPT32 */ 0x0, /* */ /* Table10961 */ 0x41e, /* INVVPID32 */ 0x0, /* */ /* Table10963 */ 0x41c, /* INVPCID32 */ 0x0, /* */ /* Table10965 */ 0x3c0, /* GF2P8MULBrm */ 0x3c1, /* GF2P8MULBrr */ /* Table10967 */ 0x117, /* AESIMCrm */ 0x118, /* AESIMCrr */ /* Table10969 */ 0x115, /* AESENCrm */ 0x116, /* AESENCrr */ /* Table10971 */ 0x113, /* AESENCLASTrm */ 0x114, /* AESENCLASTrr */ /* Table10973 */ 0x111, /* AESDECrm */ 0x112, /* AESDECrr */ /* Table10975 */ 0x10f, /* AESDECLASTrm */ 0x110, /* AESDECLASTrr */ /* Table10977 */ 0x65d, /* MOVBE16rm */ 0x0, /* */ /* Table10979 */ 0x65c, /* MOVBE16mr */ 0x0, /* */ /* Table10981 */ 0x3b59, /* WRUSSD */ 0x0, /* */ /* Table10983 */ 0xbe, /* ADCX32rm */ 0xbf, /* ADCX32rr */ /* Table10985 */ 0x669, /* MOVDIR64B32 */ 0x0, /* */ /* Table10987 */ 0x668, /* MOVDIR64B16 */ 0x0, /* */ /* Table10989 */ 0x2dd, /* CRC32r32m8 */ 0x2e0, /* CRC32r32r8 */ /* Table10991 */ 0x2dc, /* CRC32r32m32 */ 0x2df, /* CRC32r32r32 */ /* Table10993 */ 0x10b, /* ADOX32rm */ 0x10c, /* ADOX32rr */ /* Table10995 */ 0x2db, /* CRC32r32m16 */ 0x2de, /* CRC32r32r16 */ /* Table10997 */ 0x661, /* MOVBE64rm */ 0x0, /* */ /* Table10999 */ 0x660, /* MOVBE64mr */ 0x0, /* */ /* Table11001 */ 0x3b58, /* WRSSQ */ 0x0, /* */ /* Table11003 */ 0x66c, /* MOVDIRI64 */ 0x0, /* */ /* Table11005 */ 0x418, /* INVEPT64 */ 0x0, /* */ /* Table11007 */ 0x41f, /* INVVPID64 */ 0x0, /* */ /* Table11009 */ 0x41d, /* INVPCID64 */ 0x0, /* */ /* Table11011 */ 0x3b58, /* WRSSQ */ 0xbf, /* ADCX32rr */ /* Table11013 */ 0x66a, /* MOVDIR64B64 */ 0x0, /* */ /* Table11015 */ 0x10d, /* ADOX64rm */ 0x10e, /* ADOX64rr */ /* Table11017 */ 0x2e2, /* CRC32r64m8 */ 0x2e4, /* CRC32r64r8 */ /* Table11019 */ 0x2e1, /* CRC32r64m64 */ 0x2e3, /* CRC32r64r64 */ /* Table11021 */ 0x3b5a, /* WRUSSQ */ 0x0, /* */ /* Table11023 */ 0xc0, /* ADCX64rm */ 0xc1, /* ADCX64rr */ /* Table11025 */ 0x13f, /* ANDN32rm */ 0x140, /* ANDN32rr */ /* Table11027 */ 0x0, /* */ 0x181, /* BLSR32rm */ 0x17d, /* BLSMSK32rm */ 0x175, /* BLSI32rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x182, /* BLSR32rr */ 0x17e, /* BLSMSK32rr */ 0x176, /* BLSI32rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table11043 */ 0x1dc, /* BZHI32rm */ 0x1dd, /* BZHI32rr */ /* Table11045 */ 0x14d, /* BEXTR32rm */ 0x14e, /* BEXTR32rr */ /* Table11047 */ 0x7aa, /* PEXT32rm */ 0x7ab, /* PEXT32rr */ /* Table11049 */ 0x9a7, /* SARX32rm */ 0x9a8, /* SARX32rr */ /* Table11051 */ 0x7a6, /* PDEP32rm */ 0x7a7, /* PDEP32rr */ /* Table11053 */ 0x6e1, /* MULX32rm */ 0x6e2, /* MULX32rr */ /* Table11055 */ 0xa53, /* SHRX32rm */ 0xa54, /* SHRX32rr */ /* Table11057 */ 0x3164, /* VPSHUFBrm */ 0x3165, /* VPSHUFBrr */ /* Table11059 */ 0x28d5, /* VPHADDWrm */ 0x28d6, /* VPHADDWrr */ /* Table11061 */ 0x28bd, /* VPHADDDrm */ 0x28be, /* VPHADDDrr */ /* Table11063 */ 0x28c1, /* VPHADDSWrm */ 0x28c2, /* VPHADDSWrr */ /* Table11065 */ 0x2993, /* VPMADDUBSWrm */ 0x2994, /* VPMADDUBSWrr */ /* Table11067 */ 0x28e9, /* VPHSUBWrm */ 0x28ea, /* VPHSUBWrr */ /* Table11069 */ 0x28df, /* VPHSUBDrm */ 0x28e0, /* VPHSUBDrr */ /* Table11071 */ 0x28e3, /* VPHSUBSWrm */ 0x28e4, /* VPHSUBSWrr */ /* Table11073 */ 0x31b3, /* VPSIGNBrm */ 0x31b4, /* VPSIGNBrr */ /* Table11075 */ 0x31bb, /* VPSIGNWrm */ 0x31bc, /* VPSIGNWrr */ /* Table11077 */ 0x31b7, /* VPSIGNDrm */ 0x31b8, /* VPSIGNDrr */ /* Table11079 */ 0x2dae, /* VPMULHRSWrm */ 0x2daf, /* VPMULHRSWrr */ /* Table11081 */ 0x2741, /* VPERMILPSrm */ 0x2742, /* VPERMILPSrr */ /* Table11083 */ 0x2703, /* VPERMILPDrm */ 0x2704, /* VPERMILPDrr */ /* Table11085 */ 0x3a7e, /* VTESTPSrm */ 0x3a7f, /* VTESTPSrr */ /* Table11087 */ 0x3a7a, /* VTESTPDrm */ 0x3a7b, /* VTESTPDrr */ /* Table11089 */ 0xefc, /* VCVTPH2PSrm */ 0xefd, /* VCVTPH2PSrr */ /* Table11091 */ 0x35d5, /* VPTESTrm */ 0x35d6, /* VPTESTrr */ /* Table11093 */ 0xd4c, /* VBROADCASTSSrm */ 0xd4d, /* VBROADCASTSSrr */ /* Table11095 */ 0x2041, /* VPABSBrm */ 0x2042, /* VPABSBrr */ /* Table11097 */ 0x2091, /* VPABSWrm */ 0x2092, /* VPABSWrr */ /* Table11099 */ 0x2060, /* VPABSDrm */ 0x2061, /* VPABSDrr */ /* Table11101 */ 0x2c47, /* VPMOVSXBWrm */ 0x2c48, /* VPMOVSXBWrr */ /* Table11103 */ 0x2c1b, /* VPMOVSXBDrm */ 0x2c1c, /* VPMOVSXBDrr */ /* Table11105 */ 0x2c31, /* VPMOVSXBQrm */ 0x2c32, /* VPMOVSXBQrr */ /* Table11107 */ 0x2c73, /* VPMOVSXWDrm */ 0x2c74, /* VPMOVSXWDrr */ /* Table11109 */ 0x2c89, /* VPMOVSXWQrm */ 0x2c8a, /* VPMOVSXWQrr */ /* Table11111 */ 0x2c5d, /* VPMOVSXDQrm */ 0x2c5e, /* VPMOVSXDQrr */ /* Table11113 */ 0x2d98, /* VPMULDQrm */ 0x2d99, /* VPMULDQrr */ /* Table11115 */ 0x23e5, /* VPCMPEQQrm */ 0x23e6, /* VPCMPEQQrr */ /* Table11117 */ 0x1eae, /* VMOVNTDQArm */ 0x0, /* */ /* Table11119 */ 0x20e5, /* VPACKUSDWrm */ 0x20e6, /* VPACKUSDWrr */ /* Table11121 */ 0x1bec, /* VMASKMOVPSrm */ 0x0, /* */ /* Table11123 */ 0x1be8, /* VMASKMOVPDrm */ 0x0, /* */ /* Table11125 */ 0x1beb, /* VMASKMOVPSmr */ 0x0, /* */ /* Table11127 */ 0x1be7, /* VMASKMOVPDmr */ 0x0, /* */ /* Table11129 */ 0x2d37, /* VPMOVZXBWrm */ 0x2d38, /* VPMOVZXBWrr */ /* Table11131 */ 0x2d0b, /* VPMOVZXBDrm */ 0x2d0c, /* VPMOVZXBDrr */ /* Table11133 */ 0x2d21, /* VPMOVZXBQrm */ 0x2d22, /* VPMOVZXBQrr */ /* Table11135 */ 0x2d63, /* VPMOVZXWDrm */ 0x2d64, /* VPMOVZXWDrr */ /* Table11137 */ 0x2d79, /* VPMOVZXWQrm */ 0x2d7a, /* VPMOVZXWQrr */ /* Table11139 */ 0x2d4d, /* VPMOVZXDQrm */ 0x2d4e, /* VPMOVZXDQrr */ /* Table11141 */ 0x2435, /* VPCMPGTQrm */ 0x2436, /* VPCMPGTQrr */ /* Table11143 */ 0x2a93, /* VPMINSBrm */ 0x2a94, /* VPMINSBrr */ /* Table11145 */ 0x2ab2, /* VPMINSDrm */ 0x2ab3, /* VPMINSDrr */ /* Table11147 */ 0x2b49, /* VPMINUWrm */ 0x2b4a, /* VPMINUWrr */ /* Table11149 */ 0x2b18, /* VPMINUDrm */ 0x2b19, /* VPMINUDrr */ /* Table11151 */ 0x29c7, /* VPMAXSBrm */ 0x29c8, /* VPMAXSBrr */ /* Table11153 */ 0x29e6, /* VPMAXSDrm */ 0x29e7, /* VPMAXSDrr */ /* Table11155 */ 0x2a7d, /* VPMAXUWrm */ 0x2a7e, /* VPMAXUWrr */ /* Table11157 */ 0x2a4c, /* VPMAXUDrm */ 0x2a4d, /* VPMAXUDrr */ /* Table11159 */ 0x2df9, /* VPMULLDrm */ 0x2dfa, /* VPMULLDrr */ /* Table11161 */ 0x28d7, /* VPHMINPOSUWrm */ 0x28d8, /* VPHMINPOSUWrr */ /* Table11163 */ 0x3406, /* VPSRLVDrm */ 0x3407, /* VPSRLVDrr */ /* Table11165 */ 0x3322, /* VPSRAVDrm */ 0x3323, /* VPSRAVDrr */ /* Table11167 */ 0x3248, /* VPSLLVDrm */ 0x3249, /* VPSLLVDrr */ /* Table11169 */ 0x2317, /* VPBROADCASTDrm */ 0x2318, /* VPBROADCASTDrr */ /* Table11171 */ 0x233c, /* VPBROADCASTQrm */ 0x233d, /* VPBROADCASTQrr */ /* Table11173 */ 0x22f8, /* VPBROADCASTBrm */ 0x22f9, /* VPBROADCASTBrr */ /* Table11175 */ 0x235b, /* VPBROADCASTWrm */ 0x235c, /* VPBROADCASTWrr */ /* Table11177 */ 0x29ae, /* VPMASKMOVDrm */ 0x0, /* */ /* Table11179 */ 0x29ad, /* VPMASKMOVDmr */ 0x0, /* */ /* Table11181 */ 0x28a3, /* VPGATHERDDrm */ 0x0, /* */ /* Table11183 */ 0x28ad, /* VPGATHERQDrm */ 0x0, /* */ /* Table11185 */ 0x1a7d, /* VGATHERDPSrm */ 0x0, /* */ /* Table11187 */ 0x1a8f, /* VGATHERQPSrm */ 0x0, /* */ /* Table11189 */ 0x14e2, /* VFMADDSUB132PSm */ 0x14e3, /* VFMADDSUB132PSr */ /* Table11191 */ 0x16ea, /* VFMSUBADD132PSm */ 0x16eb, /* VFMSUBADD132PSr */ /* Table11193 */ 0x1396, /* VFMADD132PSm */ 0x1397, /* VFMADD132PSr */ /* Table11195 */ 0x13b4, /* VFMADD132SSm */ 0x13b6, /* VFMADD132SSr */ /* Table11197 */ 0x15be, /* VFMSUB132PSm */ 0x15bf, /* VFMSUB132PSr */ /* Table11199 */ 0x15dc, /* VFMSUB132SSm */ 0x15de, /* VFMSUB132SSr */ /* Table11201 */ 0x17e6, /* VFNMADD132PSm */ 0x17e7, /* VFNMADD132PSr */ /* Table11203 */ 0x1804, /* VFNMADD132SSm */ 0x1806, /* VFNMADD132SSr */ /* Table11205 */ 0x1932, /* VFNMSUB132PSm */ 0x1933, /* VFNMSUB132PSr */ /* Table11207 */ 0x1950, /* VFNMSUB132SSm */ 0x1952, /* VFNMSUB132SSr */ /* Table11209 */ 0x1526, /* VFMADDSUB213PSm */ 0x1527, /* VFMADDSUB213PSr */ /* Table11211 */ 0x172e, /* VFMSUBADD213PSm */ 0x172f, /* VFMSUBADD213PSr */ /* Table11213 */ 0x13fa, /* VFMADD213PSm */ 0x13fb, /* VFMADD213PSr */ /* Table11215 */ 0x1418, /* VFMADD213SSm */ 0x141a, /* VFMADD213SSr */ /* Table11217 */ 0x1622, /* VFMSUB213PSm */ 0x1623, /* VFMSUB213PSr */ /* Table11219 */ 0x1640, /* VFMSUB213SSm */ 0x1642, /* VFMSUB213SSr */ /* Table11221 */ 0x184a, /* VFNMADD213PSm */ 0x184b, /* VFNMADD213PSr */ /* Table11223 */ 0x1868, /* VFNMADD213SSm */ 0x186a, /* VFNMADD213SSr */ /* Table11225 */ 0x1996, /* VFNMSUB213PSm */ 0x1997, /* VFNMSUB213PSr */ /* Table11227 */ 0x19b4, /* VFNMSUB213SSm */ 0x19b6, /* VFNMSUB213SSr */ /* Table11229 */ 0x156a, /* VFMADDSUB231PSm */ 0x156b, /* VFMADDSUB231PSr */ /* Table11231 */ 0x1772, /* VFMSUBADD231PSm */ 0x1773, /* VFMSUBADD231PSr */ /* Table11233 */ 0x145e, /* VFMADD231PSm */ 0x145f, /* VFMADD231PSr */ /* Table11235 */ 0x147c, /* VFMADD231SSm */ 0x147e, /* VFMADD231SSr */ /* Table11237 */ 0x1686, /* VFMSUB231PSm */ 0x1687, /* VFMSUB231PSr */ /* Table11239 */ 0x16a4, /* VFMSUB231SSm */ 0x16a6, /* VFMSUB231SSr */ /* Table11241 */ 0x18ae, /* VFNMADD231PSm */ 0x18af, /* VFNMADD231PSr */ /* Table11243 */ 0x18cc, /* VFNMADD231SSm */ 0x18ce, /* VFNMADD231SSr */ /* Table11245 */ 0x19fa, /* VFNMSUB231PSm */ 0x19fb, /* VFNMSUB231PSr */ /* Table11247 */ 0x1a18, /* VFNMSUB231SSm */ 0x1a1a, /* VFNMSUB231SSr */ /* Table11249 */ 0x1b7e, /* VGF2P8MULBrm */ 0x1b7f, /* VGF2P8MULBrr */ /* Table11251 */ 0xbea, /* VAESIMCrm */ 0xbeb, /* VAESIMCrr */ /* Table11253 */ 0xbe8, /* VAESENCrm */ 0xbe9, /* VAESENCrr */ /* Table11255 */ 0xbde, /* VAESENCLASTrm */ 0xbdf, /* VAESENCLASTrr */ /* Table11257 */ 0xbd4, /* VAESDECrm */ 0xbd5, /* VAESDECrr */ /* Table11259 */ 0xbca, /* VAESDECLASTrm */ 0xbcb, /* VAESDECLASTrr */ /* Table11261 */ 0xa2b, /* SHLX32rm */ 0xa2c, /* SHLX32rr */ /* Table11263 */ 0x141, /* ANDN64rm */ 0x142, /* ANDN64rr */ /* Table11265 */ 0x0, /* */ 0x183, /* BLSR64rm */ 0x17f, /* BLSMSK64rm */ 0x177, /* BLSI64rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x184, /* BLSR64rr */ 0x180, /* BLSMSK64rr */ 0x178, /* BLSI64rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table11281 */ 0x1de, /* BZHI64rm */ 0x1df, /* BZHI64rr */ /* Table11283 */ 0x14f, /* BEXTR64rm */ 0x150, /* BEXTR64rr */ /* Table11285 */ 0x7ac, /* PEXT64rm */ 0x7ad, /* PEXT64rr */ /* Table11287 */ 0x9a9, /* SARX64rm */ 0x9aa, /* SARX64rr */ /* Table11289 */ 0x7a8, /* PDEP64rm */ 0x7a9, /* PDEP64rr */ /* Table11291 */ 0x6e3, /* MULX64rm */ 0x6e4, /* MULX64rr */ /* Table11293 */ 0xa55, /* SHRX64rm */ 0xa56, /* SHRX64rr */ /* Table11295 */ 0x3425, /* VPSRLVQrm */ 0x3426, /* VPSRLVQrr */ /* Table11297 */ 0x3267, /* VPSLLVQrm */ 0x3268, /* VPSLLVQrr */ /* Table11299 */ 0x29b2, /* VPMASKMOVQrm */ 0x0, /* */ /* Table11301 */ 0x29b1, /* VPMASKMOVQmr */ 0x0, /* */ /* Table11303 */ 0x28a8, /* VPGATHERDQrm */ 0x0, /* */ /* Table11305 */ 0x28b2, /* VPGATHERQQrm */ 0x0, /* */ /* Table11307 */ 0x1a78, /* VGATHERDPDrm */ 0x0, /* */ /* Table11309 */ 0x1a8a, /* VGATHERQPDrm */ 0x0, /* */ /* Table11311 */ 0x14c0, /* VFMADDSUB132PDm */ 0x14c1, /* VFMADDSUB132PDr */ /* Table11313 */ 0x16c8, /* VFMSUBADD132PDm */ 0x16c9, /* VFMSUBADD132PDr */ /* Table11315 */ 0x1374, /* VFMADD132PDm */ 0x1375, /* VFMADD132PDr */ /* Table11317 */ 0x13a4, /* VFMADD132SDm */ 0x13a6, /* VFMADD132SDr */ /* Table11319 */ 0x159c, /* VFMSUB132PDm */ 0x159d, /* VFMSUB132PDr */ /* Table11321 */ 0x15cc, /* VFMSUB132SDm */ 0x15ce, /* VFMSUB132SDr */ /* Table11323 */ 0x17c4, /* VFNMADD132PDm */ 0x17c5, /* VFNMADD132PDr */ /* Table11325 */ 0x17f4, /* VFNMADD132SDm */ 0x17f6, /* VFNMADD132SDr */ /* Table11327 */ 0x1910, /* VFNMSUB132PDm */ 0x1911, /* VFNMSUB132PDr */ /* Table11329 */ 0x1940, /* VFNMSUB132SDm */ 0x1942, /* VFNMSUB132SDr */ /* Table11331 */ 0x1504, /* VFMADDSUB213PDm */ 0x1505, /* VFMADDSUB213PDr */ /* Table11333 */ 0x170c, /* VFMSUBADD213PDm */ 0x170d, /* VFMSUBADD213PDr */ /* Table11335 */ 0x13d8, /* VFMADD213PDm */ 0x13d9, /* VFMADD213PDr */ /* Table11337 */ 0x1408, /* VFMADD213SDm */ 0x140a, /* VFMADD213SDr */ /* Table11339 */ 0x1600, /* VFMSUB213PDm */ 0x1601, /* VFMSUB213PDr */ /* Table11341 */ 0x1630, /* VFMSUB213SDm */ 0x1632, /* VFMSUB213SDr */ /* Table11343 */ 0x1828, /* VFNMADD213PDm */ 0x1829, /* VFNMADD213PDr */ /* Table11345 */ 0x1858, /* VFNMADD213SDm */ 0x185a, /* VFNMADD213SDr */ /* Table11347 */ 0x1974, /* VFNMSUB213PDm */ 0x1975, /* VFNMSUB213PDr */ /* Table11349 */ 0x19a4, /* VFNMSUB213SDm */ 0x19a6, /* VFNMSUB213SDr */ /* Table11351 */ 0x1548, /* VFMADDSUB231PDm */ 0x1549, /* VFMADDSUB231PDr */ /* Table11353 */ 0x1750, /* VFMSUBADD231PDm */ 0x1751, /* VFMSUBADD231PDr */ /* Table11355 */ 0x143c, /* VFMADD231PDm */ 0x143d, /* VFMADD231PDr */ /* Table11357 */ 0x146c, /* VFMADD231SDm */ 0x146e, /* VFMADD231SDr */ /* Table11359 */ 0x1664, /* VFMSUB231PDm */ 0x1665, /* VFMSUB231PDr */ /* Table11361 */ 0x1694, /* VFMSUB231SDm */ 0x1696, /* VFMSUB231SDr */ /* Table11363 */ 0x188c, /* VFNMADD231PDm */ 0x188d, /* VFNMADD231PDr */ /* Table11365 */ 0x18bc, /* VFNMADD231SDm */ 0x18be, /* VFNMADD231SDr */ /* Table11367 */ 0x19d8, /* VFNMSUB231PDm */ 0x19d9, /* VFNMSUB231PDr */ /* Table11369 */ 0x1a08, /* VFNMSUB231SDm */ 0x1a0a, /* VFNMSUB231SDr */ /* Table11371 */ 0xa2d, /* SHLX64rm */ 0xa2e, /* SHLX64rr */ /* Table11373 */ 0x3150, /* VPSHUFBYrm */ 0x3151, /* VPSHUFBYrr */ /* Table11375 */ 0x28d3, /* VPHADDWYrm */ 0x28d4, /* VPHADDWYrr */ /* Table11377 */ 0x28bb, /* VPHADDDYrm */ 0x28bc, /* VPHADDDYrr */ /* Table11379 */ 0x28bf, /* VPHADDSWYrm */ 0x28c0, /* VPHADDSWYrr */ /* Table11381 */ 0x297f, /* VPMADDUBSWYrm */ 0x2980, /* VPMADDUBSWYrr */ /* Table11383 */ 0x28e7, /* VPHSUBWYrm */ 0x28e8, /* VPHSUBWYrr */ /* Table11385 */ 0x28dd, /* VPHSUBDYrm */ 0x28de, /* VPHSUBDYrr */ /* Table11387 */ 0x28e1, /* VPHSUBSWYrm */ 0x28e2, /* VPHSUBSWYrr */ /* Table11389 */ 0x31b1, /* VPSIGNBYrm */ 0x31b2, /* VPSIGNBYrr */ /* Table11391 */ 0x31b9, /* VPSIGNWYrm */ 0x31ba, /* VPSIGNWYrr */ /* Table11393 */ 0x31b5, /* VPSIGNDYrm */ 0x31b6, /* VPSIGNDYrr */ /* Table11395 */ 0x2d9a, /* VPMULHRSWYrm */ 0x2d9b, /* VPMULHRSWYrr */ /* Table11397 */ 0x2707, /* VPERMILPSYrm */ 0x2708, /* VPERMILPSYrr */ /* Table11399 */ 0x26c9, /* VPERMILPDYrm */ 0x26ca, /* VPERMILPDYrr */ /* Table11401 */ 0x3a7c, /* VTESTPSYrm */ 0x3a7d, /* VTESTPSYrr */ /* Table11403 */ 0x3a78, /* VTESTPDYrm */ 0x3a79, /* VTESTPDYrr */ /* Table11405 */ 0xee5, /* VCVTPH2PSYrm */ 0xee6, /* VCVTPH2PSYrr */ /* Table11407 */ 0x2769, /* VPERMPSYrm */ 0x276a, /* VPERMPSYrr */ /* Table11409 */ 0x35d3, /* VPTESTYrm */ 0x35d4, /* VPTESTYrr */ /* Table11411 */ 0xd38, /* VBROADCASTSSYrm */ 0xd39, /* VBROADCASTSSYrr */ /* Table11413 */ 0xd2a, /* VBROADCASTSDYrm */ 0xd2b, /* VBROADCASTSDYrr */ /* Table11415 */ 0xce6, /* VBROADCASTF128 */ 0x0, /* */ /* Table11417 */ 0x202d, /* VPABSBYrm */ 0x202e, /* VPABSBYrr */ /* Table11419 */ 0x207d, /* VPABSWYrm */ 0x207e, /* VPABSWYrr */ /* Table11421 */ 0x2043, /* VPABSDYrm */ 0x2044, /* VPABSDYrr */ /* Table11423 */ 0x2c33, /* VPMOVSXBWYrm */ 0x2c34, /* VPMOVSXBWYrr */ /* Table11425 */ 0x2c07, /* VPMOVSXBDYrm */ 0x2c08, /* VPMOVSXBDYrr */ /* Table11427 */ 0x2c1d, /* VPMOVSXBQYrm */ 0x2c1e, /* VPMOVSXBQYrr */ /* Table11429 */ 0x2c5f, /* VPMOVSXWDYrm */ 0x2c60, /* VPMOVSXWDYrr */ /* Table11431 */ 0x2c75, /* VPMOVSXWQYrm */ 0x2c76, /* VPMOVSXWQYrr */ /* Table11433 */ 0x2c49, /* VPMOVSXDQYrm */ 0x2c4a, /* VPMOVSXDQYrr */ /* Table11435 */ 0x2d7b, /* VPMULDQYrm */ 0x2d7c, /* VPMULDQYrr */ /* Table11437 */ 0x23d1, /* VPCMPEQQYrm */ 0x23d2, /* VPCMPEQQYrr */ /* Table11439 */ 0x1eaa, /* VMOVNTDQAYrm */ 0x0, /* */ /* Table11441 */ 0x20c8, /* VPACKUSDWYrm */ 0x20c9, /* VPACKUSDWYrr */ /* Table11443 */ 0x1bea, /* VMASKMOVPSYrm */ 0x0, /* */ /* Table11445 */ 0x1be6, /* VMASKMOVPDYrm */ 0x0, /* */ /* Table11447 */ 0x1be9, /* VMASKMOVPSYmr */ 0x0, /* */ /* Table11449 */ 0x1be5, /* VMASKMOVPDYmr */ 0x0, /* */ /* Table11451 */ 0x2d23, /* VPMOVZXBWYrm */ 0x2d24, /* VPMOVZXBWYrr */ /* Table11453 */ 0x2cf7, /* VPMOVZXBDYrm */ 0x2cf8, /* VPMOVZXBDYrr */ /* Table11455 */ 0x2d0d, /* VPMOVZXBQYrm */ 0x2d0e, /* VPMOVZXBQYrr */ /* Table11457 */ 0x2d4f, /* VPMOVZXWDYrm */ 0x2d50, /* VPMOVZXWDYrr */ /* Table11459 */ 0x2d65, /* VPMOVZXWQYrm */ 0x2d66, /* VPMOVZXWQYrr */ /* Table11461 */ 0x2d39, /* VPMOVZXDQYrm */ 0x2d3a, /* VPMOVZXDQYrr */ /* Table11463 */ 0x2613, /* VPERMDYrm */ 0x2614, /* VPERMDYrr */ /* Table11465 */ 0x2421, /* VPCMPGTQYrm */ 0x2422, /* VPCMPGTQYrr */ /* Table11467 */ 0x2a7f, /* VPMINSBYrm */ 0x2a80, /* VPMINSBYrr */ /* Table11469 */ 0x2a95, /* VPMINSDYrm */ 0x2a96, /* VPMINSDYrr */ /* Table11471 */ 0x2b35, /* VPMINUWYrm */ 0x2b36, /* VPMINUWYrr */ /* Table11473 */ 0x2afb, /* VPMINUDYrm */ 0x2afc, /* VPMINUDYrr */ /* Table11475 */ 0x29b3, /* VPMAXSBYrm */ 0x29b4, /* VPMAXSBYrr */ /* Table11477 */ 0x29c9, /* VPMAXSDYrm */ 0x29ca, /* VPMAXSDYrr */ /* Table11479 */ 0x2a69, /* VPMAXUWYrm */ 0x2a6a, /* VPMAXUWYrr */ /* Table11481 */ 0x2a2f, /* VPMAXUDYrm */ 0x2a30, /* VPMAXUDYrr */ /* Table11483 */ 0x2ddc, /* VPMULLDYrm */ 0x2ddd, /* VPMULLDYrr */ /* Table11485 */ 0x33e9, /* VPSRLVDYrm */ 0x33ea, /* VPSRLVDYrr */ /* Table11487 */ 0x3305, /* VPSRAVDYrm */ 0x3306, /* VPSRAVDYrr */ /* Table11489 */ 0x322b, /* VPSLLVDYrm */ 0x322c, /* VPSLLVDYrr */ /* Table11491 */ 0x22fa, /* VPBROADCASTDYrm */ 0x22fb, /* VPBROADCASTDYrr */ /* Table11493 */ 0x231f, /* VPBROADCASTQYrm */ 0x2320, /* VPBROADCASTQYrr */ /* Table11495 */ 0xd05, /* VBROADCASTI128 */ 0x0, /* */ /* Table11497 */ 0x22db, /* VPBROADCASTBYrm */ 0x22dc, /* VPBROADCASTBYrr */ /* Table11499 */ 0x233e, /* VPBROADCASTWYrm */ 0x233f, /* VPBROADCASTWYrr */ /* Table11501 */ 0x29ac, /* VPMASKMOVDYrm */ 0x0, /* */ /* Table11503 */ 0x29ab, /* VPMASKMOVDYmr */ 0x0, /* */ /* Table11505 */ 0x289f, /* VPGATHERDDYrm */ 0x0, /* */ /* Table11507 */ 0x28a9, /* VPGATHERQDYrm */ 0x0, /* */ /* Table11509 */ 0x1a79, /* VGATHERDPSYrm */ 0x0, /* */ /* Table11511 */ 0x1a8b, /* VGATHERQPSYrm */ 0x0, /* */ /* Table11513 */ 0x14c2, /* VFMADDSUB132PSYm */ 0x14c3, /* VFMADDSUB132PSYr */ /* Table11515 */ 0x16ca, /* VFMSUBADD132PSYm */ 0x16cb, /* VFMSUBADD132PSYr */ /* Table11517 */ 0x1376, /* VFMADD132PSYm */ 0x1377, /* VFMADD132PSYr */ /* Table11519 */ 0x159e, /* VFMSUB132PSYm */ 0x159f, /* VFMSUB132PSYr */ /* Table11521 */ 0x17c6, /* VFNMADD132PSYm */ 0x17c7, /* VFNMADD132PSYr */ /* Table11523 */ 0x1912, /* VFNMSUB132PSYm */ 0x1913, /* VFNMSUB132PSYr */ /* Table11525 */ 0x1506, /* VFMADDSUB213PSYm */ 0x1507, /* VFMADDSUB213PSYr */ /* Table11527 */ 0x170e, /* VFMSUBADD213PSYm */ 0x170f, /* VFMSUBADD213PSYr */ /* Table11529 */ 0x13da, /* VFMADD213PSYm */ 0x13db, /* VFMADD213PSYr */ /* Table11531 */ 0x1602, /* VFMSUB213PSYm */ 0x1603, /* VFMSUB213PSYr */ /* Table11533 */ 0x182a, /* VFNMADD213PSYm */ 0x182b, /* VFNMADD213PSYr */ /* Table11535 */ 0x1976, /* VFNMSUB213PSYm */ 0x1977, /* VFNMSUB213PSYr */ /* Table11537 */ 0x154a, /* VFMADDSUB231PSYm */ 0x154b, /* VFMADDSUB231PSYr */ /* Table11539 */ 0x1752, /* VFMSUBADD231PSYm */ 0x1753, /* VFMSUBADD231PSYr */ /* Table11541 */ 0x143e, /* VFMADD231PSYm */ 0x143f, /* VFMADD231PSYr */ /* Table11543 */ 0x1666, /* VFMSUB231PSYm */ 0x1667, /* VFMSUB231PSYr */ /* Table11545 */ 0x188e, /* VFNMADD231PSYm */ 0x188f, /* VFNMADD231PSYr */ /* Table11547 */ 0x19da, /* VFNMSUB231PSYm */ 0x19db, /* VFNMSUB231PSYr */ /* Table11549 */ 0x1b6a, /* VGF2P8MULBYrm */ 0x1b6b, /* VGF2P8MULBYrr */ /* Table11551 */ 0xbe0, /* VAESENCYrm */ 0xbe1, /* VAESENCYrr */ /* Table11553 */ 0xbd6, /* VAESENCLASTYrm */ 0xbd7, /* VAESENCLASTYrr */ /* Table11555 */ 0xbcc, /* VAESDECYrm */ 0xbcd, /* VAESDECYrr */ /* Table11557 */ 0xbc2, /* VAESDECLASTYrm */ 0xbc3, /* VAESDECLASTYrr */ /* Table11559 */ 0x3408, /* VPSRLVQYrm */ 0x3409, /* VPSRLVQYrr */ /* Table11561 */ 0x324a, /* VPSLLVQYrm */ 0x324b, /* VPSLLVQYrr */ /* Table11563 */ 0x29b0, /* VPMASKMOVQYrm */ 0x0, /* */ /* Table11565 */ 0x29af, /* VPMASKMOVQYmr */ 0x0, /* */ /* Table11567 */ 0x28a4, /* VPGATHERDQYrm */ 0x0, /* */ /* Table11569 */ 0x28ae, /* VPGATHERQQYrm */ 0x0, /* */ /* Table11571 */ 0x1a74, /* VGATHERDPDYrm */ 0x0, /* */ /* Table11573 */ 0x1a86, /* VGATHERQPDYrm */ 0x0, /* */ /* Table11575 */ 0x14a0, /* VFMADDSUB132PDYm */ 0x14a1, /* VFMADDSUB132PDYr */ /* Table11577 */ 0x16a8, /* VFMSUBADD132PDYm */ 0x16a9, /* VFMSUBADD132PDYr */ /* Table11579 */ 0x1354, /* VFMADD132PDYm */ 0x1355, /* VFMADD132PDYr */ /* Table11581 */ 0x157c, /* VFMSUB132PDYm */ 0x157d, /* VFMSUB132PDYr */ /* Table11583 */ 0x17a4, /* VFNMADD132PDYm */ 0x17a5, /* VFNMADD132PDYr */ /* Table11585 */ 0x18f0, /* VFNMSUB132PDYm */ 0x18f1, /* VFNMSUB132PDYr */ /* Table11587 */ 0x14e4, /* VFMADDSUB213PDYm */ 0x14e5, /* VFMADDSUB213PDYr */ /* Table11589 */ 0x16ec, /* VFMSUBADD213PDYm */ 0x16ed, /* VFMSUBADD213PDYr */ /* Table11591 */ 0x13b8, /* VFMADD213PDYm */ 0x13b9, /* VFMADD213PDYr */ /* Table11593 */ 0x15e0, /* VFMSUB213PDYm */ 0x15e1, /* VFMSUB213PDYr */ /* Table11595 */ 0x1808, /* VFNMADD213PDYm */ 0x1809, /* VFNMADD213PDYr */ /* Table11597 */ 0x1954, /* VFNMSUB213PDYm */ 0x1955, /* VFNMSUB213PDYr */ /* Table11599 */ 0x1528, /* VFMADDSUB231PDYm */ 0x1529, /* VFMADDSUB231PDYr */ /* Table11601 */ 0x1730, /* VFMSUBADD231PDYm */ 0x1731, /* VFMSUBADD231PDYr */ /* Table11603 */ 0x141c, /* VFMADD231PDYm */ 0x141d, /* VFMADD231PDYr */ /* Table11605 */ 0x1644, /* VFMSUB231PDYm */ 0x1645, /* VFMSUB231PDYr */ /* Table11607 */ 0x186c, /* VFNMADD231PDYm */ 0x186d, /* VFNMADD231PDYr */ /* Table11609 */ 0x19b8, /* VFNMSUB231PDYm */ 0x19b9, /* VFNMSUB231PDYr */ /* Table11611 */ 0x2cd6, /* VPMOVUSWBZ128mr */ 0x2cd8, /* VPMOVUSWBZ128rr */ /* Table11613 */ 0x2c8b, /* VPMOVUSDBZ128mr */ 0x2c8d, /* VPMOVUSDBZ128rr */ /* Table11615 */ 0x2ca9, /* VPMOVUSQBZ128mr */ 0x2cab, /* VPMOVUSQBZ128rr */ /* Table11617 */ 0x2c9a, /* VPMOVUSDWZ128mr */ 0x2c9c, /* VPMOVUSDWZ128rr */ /* Table11619 */ 0x2cc7, /* VPMOVUSQWZ128mr */ 0x2cc9, /* VPMOVUSQWZ128rr */ /* Table11621 */ 0x2cb8, /* VPMOVUSQDZ128mr */ 0x2cba, /* VPMOVUSQDZ128rr */ /* Table11623 */ 0x2bf8, /* VPMOVSWBZ128mr */ 0x2bfa, /* VPMOVSWBZ128rr */ /* Table11625 */ 0x2bad, /* VPMOVSDBZ128mr */ 0x2baf, /* VPMOVSDBZ128rr */ /* Table11627 */ 0x2bcb, /* VPMOVSQBZ128mr */ 0x2bcd, /* VPMOVSQBZ128rr */ /* Table11629 */ 0x2bbc, /* VPMOVSDWZ128mr */ 0x2bbe, /* VPMOVSDWZ128rr */ /* Table11631 */ 0x2be9, /* VPMOVSQWZ128mr */ 0x2beb, /* VPMOVSQWZ128rr */ /* Table11633 */ 0x2bda, /* VPMOVSQDZ128mr */ 0x2bdc, /* VPMOVSQDZ128rr */ /* Table11635 */ 0x3597, /* VPTESTNMBZ128rm */ 0x3599, /* VPTESTNMBZ128rr */ /* Table11637 */ 0x35a3, /* VPTESTNMDZ128rm */ 0x35a7, /* VPTESTNMDZ128rr */ /* Table11639 */ 0x0, /* */ 0x2b6f, /* VPMOVM2BZ128rr */ /* Table11641 */ 0x0, /* */ 0x2b4b, /* VPMOVB2MZ128rr */ /* Table11643 */ 0x2ce8, /* VPMOVWBZ128mr */ 0x2cea, /* VPMOVWBZ128rr */ /* Table11645 */ 0x2b51, /* VPMOVDBZ128mr */ 0x2b53, /* VPMOVDBZ128rr */ /* Table11647 */ 0x2b80, /* VPMOVQBZ128mr */ 0x2b82, /* VPMOVQBZ128rr */ /* Table11649 */ 0x2b60, /* VPMOVDWZ128mr */ 0x2b62, /* VPMOVDWZ128rr */ /* Table11651 */ 0x2b9e, /* VPMOVQWZ128mr */ 0x2ba0, /* VPMOVQWZ128rr */ /* Table11653 */ 0x2b8f, /* VPMOVQDZ128mr */ 0x2b91, /* VPMOVQDZ128rr */ /* Table11655 */ 0x0, /* */ 0x2b72, /* VPMOVM2DZ128rr */ /* Table11657 */ 0x0, /* */ 0x2b4e, /* VPMOVD2MZ128rr */ /* Table11659 */ 0x0, /* */ 0x231c, /* VPBROADCASTMW2DZ128rr */ /* Table11661 */ 0xb4f, /* V4FMADDSSrm */ 0x0, /* */ /* Table11663 */ 0xb55, /* V4FNMADDSSrm */ 0x0, /* */ /* Table11665 */ 0x3152, /* VPSHUFBZ128rm */ 0x3155, /* VPSHUFBZ128rr */ /* Table11667 */ 0x2981, /* VPMADDUBSWZ128rm */ 0x2984, /* VPMADDUBSWZ128rr */ /* Table11669 */ 0x2d9c, /* VPMULHRSWZ128rm */ 0x2d9f, /* VPMULHRSWZ128rr */ /* Table11671 */ 0x2712, /* VPERMILPSZ128rm */ 0x2718, /* VPERMILPSZ128rr */ /* Table11673 */ 0xee7, /* VCVTPH2PSZ128rm */ 0xeea, /* VCVTPH2PSZ128rr */ /* Table11675 */ 0x2fa0, /* VPRORVDZ128rm */ 0x2fa6, /* VPRORVDZ128rr */ /* Table11677 */ 0x2f34, /* VPROLVDZ128rm */ 0x2f3a, /* VPROLVDZ128rr */ /* Table11679 */ 0xd3a, /* VBROADCASTSSZ128m */ 0xd3d, /* VBROADCASTSSZ128r */ /* Table11681 */ 0x202f, /* VPABSBZ128rm */ 0x2032, /* VPABSBZ128rr */ /* Table11683 */ 0x207f, /* VPABSWZ128rm */ 0x2082, /* VPABSWZ128rr */ /* Table11685 */ 0x2045, /* VPABSDZ128rm */ 0x204b, /* VPABSDZ128rr */ /* Table11687 */ 0x2c35, /* VPMOVSXBWZ128rm */ 0x2c38, /* VPMOVSXBWZ128rr */ /* Table11689 */ 0x2c09, /* VPMOVSXBDZ128rm */ 0x2c0c, /* VPMOVSXBDZ128rr */ /* Table11691 */ 0x2c1f, /* VPMOVSXBQZ128rm */ 0x2c22, /* VPMOVSXBQZ128rr */ /* Table11693 */ 0x2c61, /* VPMOVSXWDZ128rm */ 0x2c64, /* VPMOVSXWDZ128rr */ /* Table11695 */ 0x2c77, /* VPMOVSXWQZ128rm */ 0x2c7a, /* VPMOVSXWQZ128rr */ /* Table11697 */ 0x2c4b, /* VPMOVSXDQZ128rm */ 0x2c4e, /* VPMOVSXDQZ128rr */ /* Table11699 */ 0x355b, /* VPTESTMBZ128rm */ 0x355d, /* VPTESTMBZ128rr */ /* Table11701 */ 0x3567, /* VPTESTMDZ128rm */ 0x356b, /* VPTESTMDZ128rr */ /* Table11703 */ 0x1eab, /* VMOVNTDQAZ128rm */ 0x0, /* */ /* Table11705 */ 0x20ca, /* VPACKUSDWZ128rm */ 0x20d0, /* VPACKUSDWZ128rr */ /* Table11707 */ 0x38e9, /* VSCALEFPSZ128rm */ 0x38ef, /* VSCALEFPSZ128rr */ /* Table11709 */ 0x3910, /* VSCALEFSSZrm */ 0x3913, /* VSCALEFSSZrr */ /* Table11711 */ 0x2d25, /* VPMOVZXBWZ128rm */ 0x2d28, /* VPMOVZXBWZ128rr */ /* Table11713 */ 0x2cf9, /* VPMOVZXBDZ128rm */ 0x2cfc, /* VPMOVZXBDZ128rr */ /* Table11715 */ 0x2d0f, /* VPMOVZXBQZ128rm */ 0x2d12, /* VPMOVZXBQZ128rr */ /* Table11717 */ 0x2d51, /* VPMOVZXWDZ128rm */ 0x2d54, /* VPMOVZXWDZ128rr */ /* Table11719 */ 0x2d67, /* VPMOVZXWQZ128rm */ 0x2d6a, /* VPMOVZXWQZ128rr */ /* Table11721 */ 0x2d3b, /* VPMOVZXDQZ128rm */ 0x2d3e, /* VPMOVZXDQZ128rr */ /* Table11723 */ 0x2a81, /* VPMINSBZ128rm */ 0x2a84, /* VPMINSBZ128rr */ /* Table11725 */ 0x2a97, /* VPMINSDZ128rm */ 0x2a9d, /* VPMINSDZ128rr */ /* Table11727 */ 0x2b37, /* VPMINUWZ128rm */ 0x2b3a, /* VPMINUWZ128rr */ /* Table11729 */ 0x2afd, /* VPMINUDZ128rm */ 0x2b03, /* VPMINUDZ128rr */ /* Table11731 */ 0x29b5, /* VPMAXSBZ128rm */ 0x29b8, /* VPMAXSBZ128rr */ /* Table11733 */ 0x29cb, /* VPMAXSDZ128rm */ 0x29d1, /* VPMAXSDZ128rr */ /* Table11735 */ 0x2a6b, /* VPMAXUWZ128rm */ 0x2a6e, /* VPMAXUWZ128rr */ /* Table11737 */ 0x2a31, /* VPMAXUDZ128rm */ 0x2a37, /* VPMAXUDZ128rr */ /* Table11739 */ 0x2dde, /* VPMULLDZ128rm */ 0x2de4, /* VPMULLDZ128rr */ /* Table11741 */ 0x1aae, /* VGETEXPPSZ128m */ 0x1ab4, /* VGETEXPPSZ128r */ /* Table11743 */ 0x1ad5, /* VGETEXPSSZm */ 0x1ad8, /* VGETEXPSSZr */ /* Table11745 */ 0x28fb, /* VPLZCNTDZ128rm */ 0x2901, /* VPLZCNTDZ128rr */ /* Table11747 */ 0x33eb, /* VPSRLVDZ128rm */ 0x33f1, /* VPSRLVDZ128rr */ /* Table11749 */ 0x3307, /* VPSRAVDZ128rm */ 0x330d, /* VPSRAVDZ128rr */ /* Table11751 */ 0x322d, /* VPSLLVDZ128rm */ 0x3233, /* VPSLLVDZ128rr */ /* Table11753 */ 0x374e, /* VRCP14PSZ128m */ 0x3754, /* VRCP14PSZ128r */ /* Table11755 */ 0x376f, /* VRCP14SSZrm */ 0x3772, /* VRCP14SSZrr */ /* Table11757 */ 0x3872, /* VRSQRT14PSZ128m */ 0x3878, /* VRSQRT14PSZ128r */ /* Table11759 */ 0x3893, /* VRSQRT14SSZrm */ 0x3896, /* VRSQRT14SSZrr */ /* Table11761 */ 0x25ac, /* VPDPBUSDZ128m */ 0x25b2, /* VPDPBUSDZ128r */ /* Table11763 */ 0x2591, /* VPDPBUSDSZ128m */ 0x2597, /* VPDPBUSDSZ128r */ /* Table11765 */ 0x25e2, /* VPDPWSSDZ128m */ 0x25e8, /* VPDPWSSDZ128r */ /* Table11767 */ 0x25c7, /* VPDPWSSDSZ128m */ 0x25cd, /* VPDPWSSDSZ128r */ /* Table11769 */ 0x2e66, /* VPOPCNTBZ128rm */ 0x2e69, /* VPOPCNTBZ128rr */ /* Table11771 */ 0x2e78, /* VPOPCNTDZ128rm */ 0x2e7e, /* VPOPCNTDZ128rr */ /* Table11773 */ 0x22fc, /* VPBROADCASTDZ128m */ 0x22ff, /* VPBROADCASTDZ128r */ /* Table11775 */ 0xd06, /* VBROADCASTI32X2Z128m */ 0xd09, /* VBROADCASTI32X2Z128r */ /* Table11777 */ 0x2845, /* VPEXPANDBZ128rm */ 0x2848, /* VPEXPANDBZ128rr */ /* Table11779 */ 0x2507, /* VPCOMPRESSBZ128mr */ 0x2509, /* VPCOMPRESSBZ128rr */ /* Table11781 */ 0x228b, /* VPBLENDMDZ128rm */ 0x2291, /* VPBLENDMDZ128rr */ /* Table11783 */ 0xcbb, /* VBLENDMPSZ128rm */ 0xcc1, /* VBLENDMPSZ128rr */ /* Table11785 */ 0x2279, /* VPBLENDMBZ128rm */ 0x227c, /* VPBLENDMBZ128rr */ /* Table11787 */ 0x304e, /* VPSHLDVDZ128m */ 0x3054, /* VPSHLDVDZ128r */ /* Table11789 */ 0x30ea, /* VPSHRDVDZ128m */ 0x30f0, /* VPSHRDVDZ128r */ /* Table11791 */ 0x2627, /* VPERMI2B128rm */ 0x262a, /* VPERMI2B128rr */ /* Table11793 */ 0x2639, /* VPERMI2D128rm */ 0x263f, /* VPERMI2D128rr */ /* Table11795 */ 0x266f, /* VPERMI2PS128rm */ 0x2675, /* VPERMI2PS128rr */ /* Table11797 */ 0x22dd, /* VPBROADCASTBZ128m */ 0x22e0, /* VPBROADCASTBZ128r */ /* Table11799 */ 0x2340, /* VPBROADCASTWZ128m */ 0x2343, /* VPBROADCASTWZ128r */ /* Table11801 */ 0x0, /* */ 0x22ef, /* VPBROADCASTBrZ128r */ /* Table11803 */ 0x0, /* */ 0x2352, /* VPBROADCASTWrZ128r */ /* Table11805 */ 0x0, /* */ 0x230e, /* VPBROADCASTDrZ128r */ /* Table11807 */ 0x27a3, /* VPERMT2B128rm */ 0x27a6, /* VPERMT2B128rr */ /* Table11809 */ 0x27b5, /* VPERMT2D128rm */ 0x27bb, /* VPERMT2D128rr */ /* Table11811 */ 0x27eb, /* VPERMT2PS128rm */ 0x27f1, /* VPERMT2PS128rr */ /* Table11813 */ 0x12b0, /* VEXPANDPSZ128rm */ 0x12b3, /* VEXPANDPSZ128rr */ /* Table11815 */ 0x2857, /* VPEXPANDDZ128rm */ 0x285a, /* VPEXPANDDZ128rr */ /* Table11817 */ 0xdf7, /* VCOMPRESSPSZ128mr */ 0xdf9, /* VCOMPRESSPSZ128rr */ /* Table11819 */ 0x2516, /* VPCOMPRESSDZ128mr */ 0x2518, /* VPCOMPRESSDZ128rr */ /* Table11821 */ 0x2601, /* VPERMBZ128rm */ 0x2604, /* VPERMBZ128rr */ /* Table11823 */ 0x3144, /* VPSHUFBITQMBZ128rm */ 0x3146, /* VPSHUFBITQMBZ128rr */ /* Table11825 */ 0x14c4, /* VFMADDSUB132PSZ128m */ 0x14ca, /* VFMADDSUB132PSZ128r */ /* Table11827 */ 0x16cc, /* VFMSUBADD132PSZ128m */ 0x16d2, /* VFMSUBADD132PSZ128r */ /* Table11829 */ 0x1378, /* VFMADD132PSZ128m */ 0x137e, /* VFMADD132PSZ128r */ /* Table11831 */ 0x13a9, /* VFMADD132SSZm_Int */ 0x13ad, /* VFMADD132SSZr_Int */ /* Table11833 */ 0x15a0, /* VFMSUB132PSZ128m */ 0x15a6, /* VFMSUB132PSZ128r */ /* Table11835 */ 0x15d1, /* VFMSUB132SSZm_Int */ 0x15d5, /* VFMSUB132SSZr_Int */ /* Table11837 */ 0x17c8, /* VFNMADD132PSZ128m */ 0x17ce, /* VFNMADD132PSZ128r */ /* Table11839 */ 0x17f9, /* VFNMADD132SSZm_Int */ 0x17fd, /* VFNMADD132SSZr_Int */ /* Table11841 */ 0x1914, /* VFNMSUB132PSZ128m */ 0x191a, /* VFNMSUB132PSZ128r */ /* Table11843 */ 0x1945, /* VFNMSUB132SSZm_Int */ 0x1949, /* VFNMSUB132SSZr_Int */ /* Table11845 */ 0x1508, /* VFMADDSUB213PSZ128m */ 0x150e, /* VFMADDSUB213PSZ128r */ /* Table11847 */ 0x1710, /* VFMSUBADD213PSZ128m */ 0x1716, /* VFMSUBADD213PSZ128r */ /* Table11849 */ 0x13dc, /* VFMADD213PSZ128m */ 0x13e2, /* VFMADD213PSZ128r */ /* Table11851 */ 0x140d, /* VFMADD213SSZm_Int */ 0x1411, /* VFMADD213SSZr_Int */ /* Table11853 */ 0x1604, /* VFMSUB213PSZ128m */ 0x160a, /* VFMSUB213PSZ128r */ /* Table11855 */ 0x1635, /* VFMSUB213SSZm_Int */ 0x1639, /* VFMSUB213SSZr_Int */ /* Table11857 */ 0x182c, /* VFNMADD213PSZ128m */ 0x1832, /* VFNMADD213PSZ128r */ /* Table11859 */ 0x185d, /* VFNMADD213SSZm_Int */ 0x1861, /* VFNMADD213SSZr_Int */ /* Table11861 */ 0x1978, /* VFNMSUB213PSZ128m */ 0x197e, /* VFNMSUB213PSZ128r */ /* Table11863 */ 0x19a9, /* VFNMSUB213SSZm_Int */ 0x19ad, /* VFNMSUB213SSZr_Int */ /* Table11865 */ 0x154c, /* VFMADDSUB231PSZ128m */ 0x1552, /* VFMADDSUB231PSZ128r */ /* Table11867 */ 0x1754, /* VFMSUBADD231PSZ128m */ 0x175a, /* VFMSUBADD231PSZ128r */ /* Table11869 */ 0x1440, /* VFMADD231PSZ128m */ 0x1446, /* VFMADD231PSZ128r */ /* Table11871 */ 0x1471, /* VFMADD231SSZm_Int */ 0x1475, /* VFMADD231SSZr_Int */ /* Table11873 */ 0x1668, /* VFMSUB231PSZ128m */ 0x166e, /* VFMSUB231PSZ128r */ /* Table11875 */ 0x1699, /* VFMSUB231SSZm_Int */ 0x169d, /* VFMSUB231SSZr_Int */ /* Table11877 */ 0x1890, /* VFNMADD231PSZ128m */ 0x1896, /* VFNMADD231PSZ128r */ /* Table11879 */ 0x18c1, /* VFNMADD231SSZm_Int */ 0x18c5, /* VFNMADD231SSZr_Int */ /* Table11881 */ 0x19dc, /* VFNMSUB231PSZ128m */ 0x19e2, /* VFNMSUB231PSZ128r */ /* Table11883 */ 0x1a0d, /* VFNMSUB231SSZm_Int */ 0x1a11, /* VFNMSUB231SSZr_Int */ /* Table11885 */ 0x255b, /* VPCONFLICTDZ128rm */ 0x2561, /* VPCONFLICTDZ128rr */ /* Table11887 */ 0x3796, /* VRCP28SSZm */ 0x3799, /* VRCP28SSZr */ /* Table11889 */ 0x38ba, /* VRSQRT28SSZm */ 0x38bd, /* VRSQRT28SSZr */ /* Table11891 */ 0x1b6c, /* VGF2P8MULBZ128rm */ 0x1b6f, /* VGF2P8MULBZ128rr */ /* Table11893 */ 0xbe2, /* VAESENCZ128rm */ 0xbe3, /* VAESENCZ128rr */ /* Table11895 */ 0xbd8, /* VAESENCLASTZ128rm */ 0xbd9, /* VAESENCLASTZ128rr */ /* Table11897 */ 0xbce, /* VAESDECZ128rm */ 0xbcf, /* VAESDECZ128rr */ /* Table11899 */ 0xbc4, /* VAESDECLASTZ128rm */ 0xbc5, /* VAESDECLASTZ128rr */ /* Table11901 */ 0x35c7, /* VPTESTNMWZ128rm */ 0x35c9, /* VPTESTNMWZ128rr */ /* Table11903 */ 0x35b5, /* VPTESTNMQZ128rm */ 0x35b9, /* VPTESTNMQZ128rr */ /* Table11905 */ 0x0, /* */ 0x2b78, /* VPMOVM2WZ128rr */ /* Table11907 */ 0x0, /* */ 0x2ce5, /* VPMOVW2MZ128rr */ /* Table11909 */ 0x0, /* */ 0x2319, /* VPBROADCASTMB2QZ128rr */ /* Table11911 */ 0x0, /* */ 0x2b75, /* VPMOVM2QZ128rr */ /* Table11913 */ 0x0, /* */ 0x2b7d, /* VPMOVQ2MZ128rr */ /* Table11915 */ 0x26d4, /* VPERMILPDZ128rm */ 0x26da, /* VPERMILPDZ128rr */ /* Table11917 */ 0x3427, /* VPSRLVWZ128rm */ 0x342a, /* VPSRLVWZ128rr */ /* Table11919 */ 0x333f, /* VPSRAVWZ128rm */ 0x3342, /* VPSRAVWZ128rr */ /* Table11921 */ 0x3269, /* VPSLLVWZ128rm */ 0x326c, /* VPSLLVWZ128rr */ /* Table11923 */ 0x2fbb, /* VPRORVQZ128rm */ 0x2fc1, /* VPRORVQZ128rr */ /* Table11925 */ 0x2f4f, /* VPROLVQZ128rm */ 0x2f55, /* VPROLVQZ128rr */ /* Table11927 */ 0x2062, /* VPABSQZ128rm */ 0x2068, /* VPABSQZ128rr */ /* Table11929 */ 0x358b, /* VPTESTMWZ128rm */ 0x358d, /* VPTESTMWZ128rr */ /* Table11931 */ 0x3579, /* VPTESTMQZ128rm */ 0x357d, /* VPTESTMQZ128rr */ /* Table11933 */ 0x2d7d, /* VPMULDQZ128rm */ 0x2d83, /* VPMULDQZ128rr */ /* Table11935 */ 0x23d3, /* VPCMPEQQZ128rm */ 0x23d7, /* VPCMPEQQZ128rr */ /* Table11937 */ 0x38cb, /* VSCALEFPDZ128rm */ 0x38d1, /* VSCALEFPDZ128rr */ /* Table11939 */ 0x3907, /* VSCALEFSDZrm */ 0x390a, /* VSCALEFSDZrr */ /* Table11941 */ 0x2423, /* VPCMPGTQZ128rm */ 0x2427, /* VPCMPGTQZ128rr */ /* Table11943 */ 0x2ab4, /* VPMINSQZ128rm */ 0x2aba, /* VPMINSQZ128rr */ /* Table11945 */ 0x2b1a, /* VPMINUQZ128rm */ 0x2b20, /* VPMINUQZ128rr */ /* Table11947 */ 0x29e8, /* VPMAXSQZ128rm */ 0x29ee, /* VPMAXSQZ128rr */ /* Table11949 */ 0x2a4e, /* VPMAXUQZ128rm */ 0x2a54, /* VPMAXUQZ128rr */ /* Table11951 */ 0x2dfb, /* VPMULLQZ128rm */ 0x2e01, /* VPMULLQZ128rr */ /* Table11953 */ 0x1a90, /* VGETEXPPDZ128m */ 0x1a96, /* VGETEXPPDZ128r */ /* Table11955 */ 0x1acc, /* VGETEXPSDZm */ 0x1acf, /* VGETEXPSDZr */ /* Table11957 */ 0x2916, /* VPLZCNTQZ128rm */ 0x291c, /* VPLZCNTQZ128rr */ /* Table11959 */ 0x340a, /* VPSRLVQZ128rm */ 0x3410, /* VPSRLVQZ128rr */ /* Table11961 */ 0x3324, /* VPSRAVQZ128rm */ 0x332a, /* VPSRAVQZ128rr */ /* Table11963 */ 0x324c, /* VPSLLVQZ128rm */ 0x3252, /* VPSLLVQZ128rr */ /* Table11965 */ 0x3733, /* VRCP14PDZ128m */ 0x3739, /* VRCP14PDZ128r */ /* Table11967 */ 0x3769, /* VRCP14SDZrm */ 0x376c, /* VRCP14SDZrr */ /* Table11969 */ 0x3857, /* VRSQRT14PDZ128m */ 0x385d, /* VRSQRT14PDZ128r */ /* Table11971 */ 0x388d, /* VRSQRT14SDZrm */ 0x3890, /* VRSQRT14SDZrr */ /* Table11973 */ 0x2eae, /* VPOPCNTWZ128rm */ 0x2eb1, /* VPOPCNTWZ128rr */ /* Table11975 */ 0x2e93, /* VPOPCNTQZ128rm */ 0x2e99, /* VPOPCNTQZ128rr */ /* Table11977 */ 0x2321, /* VPBROADCASTQZ128m */ 0x2324, /* VPBROADCASTQZ128r */ /* Table11979 */ 0x287b, /* VPEXPANDWZ128rm */ 0x287e, /* VPEXPANDWZ128rr */ /* Table11981 */ 0x2534, /* VPCOMPRESSWZ128mr */ 0x2536, /* VPCOMPRESSWZ128rr */ /* Table11983 */ 0x22a6, /* VPBLENDMQZ128rm */ 0x22ac, /* VPBLENDMQZ128rr */ /* Table11985 */ 0xca0, /* VBLENDMPDZ128rm */ 0xca6, /* VBLENDMPDZ128rr */ /* Table11987 */ 0x22c1, /* VPBLENDMWZ128rm */ 0x22c4, /* VPBLENDMWZ128rr */ /* Table11989 */ 0x3084, /* VPSHLDVWZ128m */ 0x3087, /* VPSHLDVWZ128r */ /* Table11991 */ 0x3069, /* VPSHLDVQZ128m */ 0x306f, /* VPSHLDVQZ128r */ /* Table11993 */ 0x3120, /* VPSHRDVWZ128m */ 0x3123, /* VPSHRDVWZ128r */ /* Table11995 */ 0x3105, /* VPSHRDVQZ128m */ 0x310b, /* VPSHRDVQZ128r */ /* Table11997 */ 0x26a5, /* VPERMI2W128rm */ 0x26a8, /* VPERMI2W128rr */ /* Table11999 */ 0x268a, /* VPERMI2Q128rm */ 0x2690, /* VPERMI2Q128rr */ /* Table12001 */ 0x2654, /* VPERMI2PD128rm */ 0x265a, /* VPERMI2PD128rr */ /* Table12003 */ 0x0, /* */ 0x2333, /* VPBROADCASTQrZ128r */ /* Table12005 */ 0x2821, /* VPERMT2W128rm */ 0x2824, /* VPERMT2W128rr */ /* Table12007 */ 0x2806, /* VPERMT2Q128rm */ 0x280c, /* VPERMT2Q128rr */ /* Table12009 */ 0x27d0, /* VPERMT2PD128rm */ 0x27d6, /* VPERMT2PD128rr */ /* Table12011 */ 0x2e2c, /* VPMULTISHIFTQBZ128rm */ 0x2e32, /* VPMULTISHIFTQBZ128rr */ /* Table12013 */ 0x129e, /* VEXPANDPDZ128rm */ 0x12a1, /* VEXPANDPDZ128rr */ /* Table12015 */ 0x2869, /* VPEXPANDQZ128rm */ 0x286c, /* VPEXPANDQZ128rr */ /* Table12017 */ 0xde8, /* VCOMPRESSPDZ128mr */ 0xdea, /* VCOMPRESSPDZ128rr */ /* Table12019 */ 0x2525, /* VPCOMPRESSQZ128mr */ 0x2527, /* VPCOMPRESSQZ128rr */ /* Table12021 */ 0x2833, /* VPERMWZ128rm */ 0x2836, /* VPERMWZ128rr */ /* Table12023 */ 0x14a2, /* VFMADDSUB132PDZ128m */ 0x14a8, /* VFMADDSUB132PDZ128r */ /* Table12025 */ 0x16aa, /* VFMSUBADD132PDZ128m */ 0x16b0, /* VFMSUBADD132PDZ128r */ /* Table12027 */ 0x1356, /* VFMADD132PDZ128m */ 0x135c, /* VFMADD132PDZ128r */ /* Table12029 */ 0x1399, /* VFMADD132SDZm_Int */ 0x139d, /* VFMADD132SDZr_Int */ /* Table12031 */ 0x157e, /* VFMSUB132PDZ128m */ 0x1584, /* VFMSUB132PDZ128r */ /* Table12033 */ 0x15c1, /* VFMSUB132SDZm_Int */ 0x15c5, /* VFMSUB132SDZr_Int */ /* Table12035 */ 0x17a6, /* VFNMADD132PDZ128m */ 0x17ac, /* VFNMADD132PDZ128r */ /* Table12037 */ 0x17e9, /* VFNMADD132SDZm_Int */ 0x17ed, /* VFNMADD132SDZr_Int */ /* Table12039 */ 0x18f2, /* VFNMSUB132PDZ128m */ 0x18f8, /* VFNMSUB132PDZ128r */ /* Table12041 */ 0x1935, /* VFNMSUB132SDZm_Int */ 0x1939, /* VFNMSUB132SDZr_Int */ /* Table12043 */ 0x14e6, /* VFMADDSUB213PDZ128m */ 0x14ec, /* VFMADDSUB213PDZ128r */ /* Table12045 */ 0x16ee, /* VFMSUBADD213PDZ128m */ 0x16f4, /* VFMSUBADD213PDZ128r */ /* Table12047 */ 0x13ba, /* VFMADD213PDZ128m */ 0x13c0, /* VFMADD213PDZ128r */ /* Table12049 */ 0x13fd, /* VFMADD213SDZm_Int */ 0x1401, /* VFMADD213SDZr_Int */ /* Table12051 */ 0x15e2, /* VFMSUB213PDZ128m */ 0x15e8, /* VFMSUB213PDZ128r */ /* Table12053 */ 0x1625, /* VFMSUB213SDZm_Int */ 0x1629, /* VFMSUB213SDZr_Int */ /* Table12055 */ 0x180a, /* VFNMADD213PDZ128m */ 0x1810, /* VFNMADD213PDZ128r */ /* Table12057 */ 0x184d, /* VFNMADD213SDZm_Int */ 0x1851, /* VFNMADD213SDZr_Int */ /* Table12059 */ 0x1956, /* VFNMSUB213PDZ128m */ 0x195c, /* VFNMSUB213PDZ128r */ /* Table12061 */ 0x1999, /* VFNMSUB213SDZm_Int */ 0x199d, /* VFNMSUB213SDZr_Int */ /* Table12063 */ 0x2964, /* VPMADD52LUQZ128m */ 0x296a, /* VPMADD52LUQZ128r */ /* Table12065 */ 0x2949, /* VPMADD52HUQZ128m */ 0x294f, /* VPMADD52HUQZ128r */ /* Table12067 */ 0x152a, /* VFMADDSUB231PDZ128m */ 0x1530, /* VFMADDSUB231PDZ128r */ /* Table12069 */ 0x1732, /* VFMSUBADD231PDZ128m */ 0x1738, /* VFMSUBADD231PDZ128r */ /* Table12071 */ 0x141e, /* VFMADD231PDZ128m */ 0x1424, /* VFMADD231PDZ128r */ /* Table12073 */ 0x1461, /* VFMADD231SDZm_Int */ 0x1465, /* VFMADD231SDZr_Int */ /* Table12075 */ 0x1646, /* VFMSUB231PDZ128m */ 0x164c, /* VFMSUB231PDZ128r */ /* Table12077 */ 0x1689, /* VFMSUB231SDZm_Int */ 0x168d, /* VFMSUB231SDZr_Int */ /* Table12079 */ 0x186e, /* VFNMADD231PDZ128m */ 0x1874, /* VFNMADD231PDZ128r */ /* Table12081 */ 0x18b1, /* VFNMADD231SDZm_Int */ 0x18b5, /* VFNMADD231SDZr_Int */ /* Table12083 */ 0x19ba, /* VFNMSUB231PDZ128m */ 0x19c0, /* VFNMSUB231PDZ128r */ /* Table12085 */ 0x19fd, /* VFNMSUB231SDZm_Int */ 0x1a01, /* VFNMSUB231SDZr_Int */ /* Table12087 */ 0x2576, /* VPCONFLICTQZ128rm */ 0x257c, /* VPCONFLICTQZ128rr */ /* Table12089 */ 0x378d, /* VRCP28SDZm */ 0x3790, /* VRCP28SDZr */ /* Table12091 */ 0x38b1, /* VRSQRT28SDZm */ 0x38b4, /* VRSQRT28SDZr */ /* Table12093 */ 0x2cdb, /* VPMOVUSWBZ256mr */ 0x2cdd, /* VPMOVUSWBZ256rr */ /* Table12095 */ 0x2c90, /* VPMOVUSDBZ256mr */ 0x2c92, /* VPMOVUSDBZ256rr */ /* Table12097 */ 0x2cae, /* VPMOVUSQBZ256mr */ 0x2cb0, /* VPMOVUSQBZ256rr */ /* Table12099 */ 0x2c9f, /* VPMOVUSDWZ256mr */ 0x2ca1, /* VPMOVUSDWZ256rr */ /* Table12101 */ 0x2ccc, /* VPMOVUSQWZ256mr */ 0x2cce, /* VPMOVUSQWZ256rr */ /* Table12103 */ 0x2cbd, /* VPMOVUSQDZ256mr */ 0x2cbf, /* VPMOVUSQDZ256rr */ /* Table12105 */ 0x2bfd, /* VPMOVSWBZ256mr */ 0x2bff, /* VPMOVSWBZ256rr */ /* Table12107 */ 0x2bb2, /* VPMOVSDBZ256mr */ 0x2bb4, /* VPMOVSDBZ256rr */ /* Table12109 */ 0x2bd0, /* VPMOVSQBZ256mr */ 0x2bd2, /* VPMOVSQBZ256rr */ /* Table12111 */ 0x2bc1, /* VPMOVSDWZ256mr */ 0x2bc3, /* VPMOVSDWZ256rr */ /* Table12113 */ 0x2bee, /* VPMOVSQWZ256mr */ 0x2bf0, /* VPMOVSQWZ256rr */ /* Table12115 */ 0x2bdf, /* VPMOVSQDZ256mr */ 0x2be1, /* VPMOVSQDZ256rr */ /* Table12117 */ 0x359b, /* VPTESTNMBZ256rm */ 0x359d, /* VPTESTNMBZ256rr */ /* Table12119 */ 0x35a9, /* VPTESTNMDZ256rm */ 0x35ad, /* VPTESTNMDZ256rr */ /* Table12121 */ 0x0, /* */ 0x2b70, /* VPMOVM2BZ256rr */ /* Table12123 */ 0x0, /* */ 0x2b4c, /* VPMOVB2MZ256rr */ /* Table12125 */ 0x2ced, /* VPMOVWBZ256mr */ 0x2cef, /* VPMOVWBZ256rr */ /* Table12127 */ 0x2b56, /* VPMOVDBZ256mr */ 0x2b58, /* VPMOVDBZ256rr */ /* Table12129 */ 0x2b85, /* VPMOVQBZ256mr */ 0x2b87, /* VPMOVQBZ256rr */ /* Table12131 */ 0x2b65, /* VPMOVDWZ256mr */ 0x2b67, /* VPMOVDWZ256rr */ /* Table12133 */ 0x2ba3, /* VPMOVQWZ256mr */ 0x2ba5, /* VPMOVQWZ256rr */ /* Table12135 */ 0x2b94, /* VPMOVQDZ256mr */ 0x2b96, /* VPMOVQDZ256rr */ /* Table12137 */ 0x0, /* */ 0x2b73, /* VPMOVM2DZ256rr */ /* Table12139 */ 0x0, /* */ 0x2b4f, /* VPMOVD2MZ256rr */ /* Table12141 */ 0x0, /* */ 0x231d, /* VPBROADCASTMW2DZ256rr */ /* Table12143 */ 0x3158, /* VPSHUFBZ256rm */ 0x315b, /* VPSHUFBZ256rr */ /* Table12145 */ 0x2987, /* VPMADDUBSWZ256rm */ 0x298a, /* VPMADDUBSWZ256rr */ /* Table12147 */ 0x2da2, /* VPMULHRSWZ256rm */ 0x2da5, /* VPMULHRSWZ256rr */ /* Table12149 */ 0x2724, /* VPERMILPSZ256rm */ 0x272a, /* VPERMILPSZ256rr */ /* Table12151 */ 0xeed, /* VCVTPH2PSZ256rm */ 0xef0, /* VCVTPH2PSZ256rr */ /* Table12153 */ 0x2fa9, /* VPRORVDZ256rm */ 0x2faf, /* VPRORVDZ256rr */ /* Table12155 */ 0x2f3d, /* VPROLVDZ256rm */ 0x2f43, /* VPROLVDZ256rr */ /* Table12157 */ 0x276b, /* VPERMPSZ256rm */ 0x2771, /* VPERMPSZ256rr */ /* Table12159 */ 0xd40, /* VBROADCASTSSZ256m */ 0xd43, /* VBROADCASTSSZ256r */ /* Table12161 */ 0xce7, /* VBROADCASTF32X2Z256m */ 0xcea, /* VBROADCASTF32X2Z256r */ /* Table12163 */ 0xcf3, /* VBROADCASTF32X4Z256rm */ 0x0, /* */ /* Table12165 */ 0x2035, /* VPABSBZ256rm */ 0x2038, /* VPABSBZ256rr */ /* Table12167 */ 0x2085, /* VPABSWZ256rm */ 0x2088, /* VPABSWZ256rr */ /* Table12169 */ 0x204e, /* VPABSDZ256rm */ 0x2054, /* VPABSDZ256rr */ /* Table12171 */ 0x2c3b, /* VPMOVSXBWZ256rm */ 0x2c3e, /* VPMOVSXBWZ256rr */ /* Table12173 */ 0x2c0f, /* VPMOVSXBDZ256rm */ 0x2c12, /* VPMOVSXBDZ256rr */ /* Table12175 */ 0x2c25, /* VPMOVSXBQZ256rm */ 0x2c28, /* VPMOVSXBQZ256rr */ /* Table12177 */ 0x2c67, /* VPMOVSXWDZ256rm */ 0x2c6a, /* VPMOVSXWDZ256rr */ /* Table12179 */ 0x2c7d, /* VPMOVSXWQZ256rm */ 0x2c80, /* VPMOVSXWQZ256rr */ /* Table12181 */ 0x2c51, /* VPMOVSXDQZ256rm */ 0x2c54, /* VPMOVSXDQZ256rr */ /* Table12183 */ 0x355f, /* VPTESTMBZ256rm */ 0x3561, /* VPTESTMBZ256rr */ /* Table12185 */ 0x356d, /* VPTESTMDZ256rm */ 0x3571, /* VPTESTMDZ256rr */ /* Table12187 */ 0x1eac, /* VMOVNTDQAZ256rm */ 0x0, /* */ /* Table12189 */ 0x20d3, /* VPACKUSDWZ256rm */ 0x20d9, /* VPACKUSDWZ256rr */ /* Table12191 */ 0x38f2, /* VSCALEFPSZ256rm */ 0x38f8, /* VSCALEFPSZ256rr */ /* Table12193 */ 0x2d2b, /* VPMOVZXBWZ256rm */ 0x2d2e, /* VPMOVZXBWZ256rr */ /* Table12195 */ 0x2cff, /* VPMOVZXBDZ256rm */ 0x2d02, /* VPMOVZXBDZ256rr */ /* Table12197 */ 0x2d15, /* VPMOVZXBQZ256rm */ 0x2d18, /* VPMOVZXBQZ256rr */ /* Table12199 */ 0x2d57, /* VPMOVZXWDZ256rm */ 0x2d5a, /* VPMOVZXWDZ256rr */ /* Table12201 */ 0x2d6d, /* VPMOVZXWQZ256rm */ 0x2d70, /* VPMOVZXWQZ256rr */ /* Table12203 */ 0x2d41, /* VPMOVZXDQZ256rm */ 0x2d44, /* VPMOVZXDQZ256rr */ /* Table12205 */ 0x2615, /* VPERMDZ256rm */ 0x261b, /* VPERMDZ256rr */ /* Table12207 */ 0x2a87, /* VPMINSBZ256rm */ 0x2a8a, /* VPMINSBZ256rr */ /* Table12209 */ 0x2aa0, /* VPMINSDZ256rm */ 0x2aa6, /* VPMINSDZ256rr */ /* Table12211 */ 0x2b3d, /* VPMINUWZ256rm */ 0x2b40, /* VPMINUWZ256rr */ /* Table12213 */ 0x2b06, /* VPMINUDZ256rm */ 0x2b0c, /* VPMINUDZ256rr */ /* Table12215 */ 0x29bb, /* VPMAXSBZ256rm */ 0x29be, /* VPMAXSBZ256rr */ /* Table12217 */ 0x29d4, /* VPMAXSDZ256rm */ 0x29da, /* VPMAXSDZ256rr */ /* Table12219 */ 0x2a71, /* VPMAXUWZ256rm */ 0x2a74, /* VPMAXUWZ256rr */ /* Table12221 */ 0x2a3a, /* VPMAXUDZ256rm */ 0x2a40, /* VPMAXUDZ256rr */ /* Table12223 */ 0x2de7, /* VPMULLDZ256rm */ 0x2ded, /* VPMULLDZ256rr */ /* Table12225 */ 0x1ab7, /* VGETEXPPSZ256m */ 0x1abd, /* VGETEXPPSZ256r */ /* Table12227 */ 0x2904, /* VPLZCNTDZ256rm */ 0x290a, /* VPLZCNTDZ256rr */ /* Table12229 */ 0x33f4, /* VPSRLVDZ256rm */ 0x33fa, /* VPSRLVDZ256rr */ /* Table12231 */ 0x3310, /* VPSRAVDZ256rm */ 0x3316, /* VPSRAVDZ256rr */ /* Table12233 */ 0x3236, /* VPSLLVDZ256rm */ 0x323c, /* VPSLLVDZ256rr */ /* Table12235 */ 0x3757, /* VRCP14PSZ256m */ 0x375d, /* VRCP14PSZ256r */ /* Table12237 */ 0x387b, /* VRSQRT14PSZ256m */ 0x3881, /* VRSQRT14PSZ256r */ /* Table12239 */ 0x25b5, /* VPDPBUSDZ256m */ 0x25bb, /* VPDPBUSDZ256r */ /* Table12241 */ 0x259a, /* VPDPBUSDSZ256m */ 0x25a0, /* VPDPBUSDSZ256r */ /* Table12243 */ 0x25eb, /* VPDPWSSDZ256m */ 0x25f1, /* VPDPWSSDZ256r */ /* Table12245 */ 0x25d0, /* VPDPWSSDSZ256m */ 0x25d6, /* VPDPWSSDSZ256r */ /* Table12247 */ 0x2e6c, /* VPOPCNTBZ256rm */ 0x2e6f, /* VPOPCNTBZ256rr */ /* Table12249 */ 0x2e81, /* VPOPCNTDZ256rm */ 0x2e87, /* VPOPCNTDZ256rr */ /* Table12251 */ 0x2302, /* VPBROADCASTDZ256m */ 0x2305, /* VPBROADCASTDZ256r */ /* Table12253 */ 0xd0c, /* VBROADCASTI32X2Z256m */ 0xd0f, /* VBROADCASTI32X2Z256r */ /* Table12255 */ 0xd18, /* VBROADCASTI32X4Z256rm */ 0x0, /* */ /* Table12257 */ 0x284b, /* VPEXPANDBZ256rm */ 0x284e, /* VPEXPANDBZ256rr */ /* Table12259 */ 0x250c, /* VPCOMPRESSBZ256mr */ 0x250e, /* VPCOMPRESSBZ256rr */ /* Table12261 */ 0x2294, /* VPBLENDMDZ256rm */ 0x229a, /* VPBLENDMDZ256rr */ /* Table12263 */ 0xcc4, /* VBLENDMPSZ256rm */ 0xcca, /* VBLENDMPSZ256rr */ /* Table12265 */ 0x227f, /* VPBLENDMBZ256rm */ 0x2282, /* VPBLENDMBZ256rr */ /* Table12267 */ 0x3057, /* VPSHLDVDZ256m */ 0x305d, /* VPSHLDVDZ256r */ /* Table12269 */ 0x30f3, /* VPSHRDVDZ256m */ 0x30f9, /* VPSHRDVDZ256r */ /* Table12271 */ 0x262d, /* VPERMI2B256rm */ 0x2630, /* VPERMI2B256rr */ /* Table12273 */ 0x2642, /* VPERMI2D256rm */ 0x2648, /* VPERMI2D256rr */ /* Table12275 */ 0x2678, /* VPERMI2PS256rm */ 0x267e, /* VPERMI2PS256rr */ /* Table12277 */ 0x22e3, /* VPBROADCASTBZ256m */ 0x22e6, /* VPBROADCASTBZ256r */ /* Table12279 */ 0x2346, /* VPBROADCASTWZ256m */ 0x2349, /* VPBROADCASTWZ256r */ /* Table12281 */ 0x0, /* */ 0x22f2, /* VPBROADCASTBrZ256r */ /* Table12283 */ 0x0, /* */ 0x2355, /* VPBROADCASTWrZ256r */ /* Table12285 */ 0x0, /* */ 0x2311, /* VPBROADCASTDrZ256r */ /* Table12287 */ 0x27a9, /* VPERMT2B256rm */ 0x27ac, /* VPERMT2B256rr */ /* Table12289 */ 0x27be, /* VPERMT2D256rm */ 0x27c4, /* VPERMT2D256rr */ /* Table12291 */ 0x27f4, /* VPERMT2PS256rm */ 0x27fa, /* VPERMT2PS256rr */ /* Table12293 */ 0x12b6, /* VEXPANDPSZ256rm */ 0x12b9, /* VEXPANDPSZ256rr */ /* Table12295 */ 0x285d, /* VPEXPANDDZ256rm */ 0x2860, /* VPEXPANDDZ256rr */ /* Table12297 */ 0xdfc, /* VCOMPRESSPSZ256mr */ 0xdfe, /* VCOMPRESSPSZ256rr */ /* Table12299 */ 0x251b, /* VPCOMPRESSDZ256mr */ 0x251d, /* VPCOMPRESSDZ256rr */ /* Table12301 */ 0x2607, /* VPERMBZ256rm */ 0x260a, /* VPERMBZ256rr */ /* Table12303 */ 0x3148, /* VPSHUFBITQMBZ256rm */ 0x314a, /* VPSHUFBITQMBZ256rr */ /* Table12305 */ 0x14cd, /* VFMADDSUB132PSZ256m */ 0x14d3, /* VFMADDSUB132PSZ256r */ /* Table12307 */ 0x16d5, /* VFMSUBADD132PSZ256m */ 0x16db, /* VFMSUBADD132PSZ256r */ /* Table12309 */ 0x1381, /* VFMADD132PSZ256m */ 0x1387, /* VFMADD132PSZ256r */ /* Table12311 */ 0x15a9, /* VFMSUB132PSZ256m */ 0x15af, /* VFMSUB132PSZ256r */ /* Table12313 */ 0x17d1, /* VFNMADD132PSZ256m */ 0x17d7, /* VFNMADD132PSZ256r */ /* Table12315 */ 0x191d, /* VFNMSUB132PSZ256m */ 0x1923, /* VFNMSUB132PSZ256r */ /* Table12317 */ 0x1511, /* VFMADDSUB213PSZ256m */ 0x1517, /* VFMADDSUB213PSZ256r */ /* Table12319 */ 0x1719, /* VFMSUBADD213PSZ256m */ 0x171f, /* VFMSUBADD213PSZ256r */ /* Table12321 */ 0x13e5, /* VFMADD213PSZ256m */ 0x13eb, /* VFMADD213PSZ256r */ /* Table12323 */ 0x160d, /* VFMSUB213PSZ256m */ 0x1613, /* VFMSUB213PSZ256r */ /* Table12325 */ 0x1835, /* VFNMADD213PSZ256m */ 0x183b, /* VFNMADD213PSZ256r */ /* Table12327 */ 0x1981, /* VFNMSUB213PSZ256m */ 0x1987, /* VFNMSUB213PSZ256r */ /* Table12329 */ 0x1555, /* VFMADDSUB231PSZ256m */ 0x155b, /* VFMADDSUB231PSZ256r */ /* Table12331 */ 0x175d, /* VFMSUBADD231PSZ256m */ 0x1763, /* VFMSUBADD231PSZ256r */ /* Table12333 */ 0x1449, /* VFMADD231PSZ256m */ 0x144f, /* VFMADD231PSZ256r */ /* Table12335 */ 0x1671, /* VFMSUB231PSZ256m */ 0x1677, /* VFMSUB231PSZ256r */ /* Table12337 */ 0x1899, /* VFNMADD231PSZ256m */ 0x189f, /* VFNMADD231PSZ256r */ /* Table12339 */ 0x19e5, /* VFNMSUB231PSZ256m */ 0x19eb, /* VFNMSUB231PSZ256r */ /* Table12341 */ 0x2564, /* VPCONFLICTDZ256rm */ 0x256a, /* VPCONFLICTDZ256rr */ /* Table12343 */ 0x1b72, /* VGF2P8MULBZ256rm */ 0x1b75, /* VGF2P8MULBZ256rr */ /* Table12345 */ 0xbe4, /* VAESENCZ256rm */ 0xbe5, /* VAESENCZ256rr */ /* Table12347 */ 0xbda, /* VAESENCLASTZ256rm */ 0xbdb, /* VAESENCLASTZ256rr */ /* Table12349 */ 0xbd0, /* VAESDECZ256rm */ 0xbd1, /* VAESDECZ256rr */ /* Table12351 */ 0xbc6, /* VAESDECLASTZ256rm */ 0xbc7, /* VAESDECLASTZ256rr */ /* Table12353 */ 0x35cb, /* VPTESTNMWZ256rm */ 0x35cd, /* VPTESTNMWZ256rr */ /* Table12355 */ 0x35bb, /* VPTESTNMQZ256rm */ 0x35bf, /* VPTESTNMQZ256rr */ /* Table12357 */ 0x0, /* */ 0x2b79, /* VPMOVM2WZ256rr */ /* Table12359 */ 0x0, /* */ 0x2ce6, /* VPMOVW2MZ256rr */ /* Table12361 */ 0x0, /* */ 0x231a, /* VPBROADCASTMB2QZ256rr */ /* Table12363 */ 0x0, /* */ 0x2b76, /* VPMOVM2QZ256rr */ /* Table12365 */ 0x0, /* */ 0x2b7e, /* VPMOVQ2MZ256rr */ /* Table12367 */ 0x26e6, /* VPERMILPDZ256rm */ 0x26ec, /* VPERMILPDZ256rr */ /* Table12369 */ 0x342d, /* VPSRLVWZ256rm */ 0x3430, /* VPSRLVWZ256rr */ /* Table12371 */ 0x3345, /* VPSRAVWZ256rm */ 0x3348, /* VPSRAVWZ256rr */ /* Table12373 */ 0x326f, /* VPSLLVWZ256rm */ 0x3272, /* VPSLLVWZ256rr */ /* Table12375 */ 0x2fc4, /* VPRORVQZ256rm */ 0x2fca, /* VPRORVQZ256rr */ /* Table12377 */ 0x2f58, /* VPROLVQZ256rm */ 0x2f5e, /* VPROLVQZ256rr */ /* Table12379 */ 0x274e, /* VPERMPDZ256rm */ 0x2754, /* VPERMPDZ256rr */ /* Table12381 */ 0xd2c, /* VBROADCASTSDZ256m */ 0xd2f, /* VBROADCASTSDZ256r */ /* Table12383 */ 0xcfc, /* VBROADCASTF64X2Z128rm */ 0x0, /* */ /* Table12385 */ 0x206b, /* VPABSQZ256rm */ 0x2071, /* VPABSQZ256rr */ /* Table12387 */ 0x358f, /* VPTESTMWZ256rm */ 0x3591, /* VPTESTMWZ256rr */ /* Table12389 */ 0x357f, /* VPTESTMQZ256rm */ 0x3583, /* VPTESTMQZ256rr */ /* Table12391 */ 0x2d86, /* VPMULDQZ256rm */ 0x2d8c, /* VPMULDQZ256rr */ /* Table12393 */ 0x23d9, /* VPCMPEQQZ256rm */ 0x23dd, /* VPCMPEQQZ256rr */ /* Table12395 */ 0x38d4, /* VSCALEFPDZ256rm */ 0x38da, /* VSCALEFPDZ256rr */ /* Table12397 */ 0x2788, /* VPERMQZ256rm */ 0x278e, /* VPERMQZ256rr */ /* Table12399 */ 0x2429, /* VPCMPGTQZ256rm */ 0x242d, /* VPCMPGTQZ256rr */ /* Table12401 */ 0x2abd, /* VPMINSQZ256rm */ 0x2ac3, /* VPMINSQZ256rr */ /* Table12403 */ 0x2b23, /* VPMINUQZ256rm */ 0x2b29, /* VPMINUQZ256rr */ /* Table12405 */ 0x29f1, /* VPMAXSQZ256rm */ 0x29f7, /* VPMAXSQZ256rr */ /* Table12407 */ 0x2a57, /* VPMAXUQZ256rm */ 0x2a5d, /* VPMAXUQZ256rr */ /* Table12409 */ 0x2e04, /* VPMULLQZ256rm */ 0x2e0a, /* VPMULLQZ256rr */ /* Table12411 */ 0x1a99, /* VGETEXPPDZ256m */ 0x1a9f, /* VGETEXPPDZ256r */ /* Table12413 */ 0x291f, /* VPLZCNTQZ256rm */ 0x2925, /* VPLZCNTQZ256rr */ /* Table12415 */ 0x3413, /* VPSRLVQZ256rm */ 0x3419, /* VPSRLVQZ256rr */ /* Table12417 */ 0x332d, /* VPSRAVQZ256rm */ 0x3333, /* VPSRAVQZ256rr */ /* Table12419 */ 0x3255, /* VPSLLVQZ256rm */ 0x325b, /* VPSLLVQZ256rr */ /* Table12421 */ 0x373c, /* VRCP14PDZ256m */ 0x3742, /* VRCP14PDZ256r */ /* Table12423 */ 0x3860, /* VRSQRT14PDZ256m */ 0x3866, /* VRSQRT14PDZ256r */ /* Table12425 */ 0x2eb4, /* VPOPCNTWZ256rm */ 0x2eb7, /* VPOPCNTWZ256rr */ /* Table12427 */ 0x2e9c, /* VPOPCNTQZ256rm */ 0x2ea2, /* VPOPCNTQZ256rr */ /* Table12429 */ 0x2327, /* VPBROADCASTQZ256m */ 0x232a, /* VPBROADCASTQZ256r */ /* Table12431 */ 0xd21, /* VBROADCASTI64X2Z128rm */ 0x0, /* */ /* Table12433 */ 0x2881, /* VPEXPANDWZ256rm */ 0x2884, /* VPEXPANDWZ256rr */ /* Table12435 */ 0x2539, /* VPCOMPRESSWZ256mr */ 0x253b, /* VPCOMPRESSWZ256rr */ /* Table12437 */ 0x22af, /* VPBLENDMQZ256rm */ 0x22b5, /* VPBLENDMQZ256rr */ /* Table12439 */ 0xca9, /* VBLENDMPDZ256rm */ 0xcaf, /* VBLENDMPDZ256rr */ /* Table12441 */ 0x22c7, /* VPBLENDMWZ256rm */ 0x22ca, /* VPBLENDMWZ256rr */ /* Table12443 */ 0x308a, /* VPSHLDVWZ256m */ 0x308d, /* VPSHLDVWZ256r */ /* Table12445 */ 0x3072, /* VPSHLDVQZ256m */ 0x3078, /* VPSHLDVQZ256r */ /* Table12447 */ 0x3126, /* VPSHRDVWZ256m */ 0x3129, /* VPSHRDVWZ256r */ /* Table12449 */ 0x310e, /* VPSHRDVQZ256m */ 0x3114, /* VPSHRDVQZ256r */ /* Table12451 */ 0x26ab, /* VPERMI2W256rm */ 0x26ae, /* VPERMI2W256rr */ /* Table12453 */ 0x2693, /* VPERMI2Q256rm */ 0x2699, /* VPERMI2Q256rr */ /* Table12455 */ 0x265d, /* VPERMI2PD256rm */ 0x2663, /* VPERMI2PD256rr */ /* Table12457 */ 0x0, /* */ 0x2336, /* VPBROADCASTQrZ256r */ /* Table12459 */ 0x2827, /* VPERMT2W256rm */ 0x282a, /* VPERMT2W256rr */ /* Table12461 */ 0x280f, /* VPERMT2Q256rm */ 0x2815, /* VPERMT2Q256rr */ /* Table12463 */ 0x27d9, /* VPERMT2PD256rm */ 0x27df, /* VPERMT2PD256rr */ /* Table12465 */ 0x2e35, /* VPMULTISHIFTQBZ256rm */ 0x2e3b, /* VPMULTISHIFTQBZ256rr */ /* Table12467 */ 0x12a4, /* VEXPANDPDZ256rm */ 0x12a7, /* VEXPANDPDZ256rr */ /* Table12469 */ 0x286f, /* VPEXPANDQZ256rm */ 0x2872, /* VPEXPANDQZ256rr */ /* Table12471 */ 0xded, /* VCOMPRESSPDZ256mr */ 0xdef, /* VCOMPRESSPDZ256rr */ /* Table12473 */ 0x252a, /* VPCOMPRESSQZ256mr */ 0x252c, /* VPCOMPRESSQZ256rr */ /* Table12475 */ 0x2839, /* VPERMWZ256rm */ 0x283c, /* VPERMWZ256rr */ /* Table12477 */ 0x14ab, /* VFMADDSUB132PDZ256m */ 0x14b1, /* VFMADDSUB132PDZ256r */ /* Table12479 */ 0x16b3, /* VFMSUBADD132PDZ256m */ 0x16b9, /* VFMSUBADD132PDZ256r */ /* Table12481 */ 0x135f, /* VFMADD132PDZ256m */ 0x1365, /* VFMADD132PDZ256r */ /* Table12483 */ 0x1587, /* VFMSUB132PDZ256m */ 0x158d, /* VFMSUB132PDZ256r */ /* Table12485 */ 0x17af, /* VFNMADD132PDZ256m */ 0x17b5, /* VFNMADD132PDZ256r */ /* Table12487 */ 0x18fb, /* VFNMSUB132PDZ256m */ 0x1901, /* VFNMSUB132PDZ256r */ /* Table12489 */ 0x14ef, /* VFMADDSUB213PDZ256m */ 0x14f5, /* VFMADDSUB213PDZ256r */ /* Table12491 */ 0x16f7, /* VFMSUBADD213PDZ256m */ 0x16fd, /* VFMSUBADD213PDZ256r */ /* Table12493 */ 0x13c3, /* VFMADD213PDZ256m */ 0x13c9, /* VFMADD213PDZ256r */ /* Table12495 */ 0x15eb, /* VFMSUB213PDZ256m */ 0x15f1, /* VFMSUB213PDZ256r */ /* Table12497 */ 0x1813, /* VFNMADD213PDZ256m */ 0x1819, /* VFNMADD213PDZ256r */ /* Table12499 */ 0x195f, /* VFNMSUB213PDZ256m */ 0x1965, /* VFNMSUB213PDZ256r */ /* Table12501 */ 0x296d, /* VPMADD52LUQZ256m */ 0x2973, /* VPMADD52LUQZ256r */ /* Table12503 */ 0x2952, /* VPMADD52HUQZ256m */ 0x2958, /* VPMADD52HUQZ256r */ /* Table12505 */ 0x1533, /* VFMADDSUB231PDZ256m */ 0x1539, /* VFMADDSUB231PDZ256r */ /* Table12507 */ 0x173b, /* VFMSUBADD231PDZ256m */ 0x1741, /* VFMSUBADD231PDZ256r */ /* Table12509 */ 0x1427, /* VFMADD231PDZ256m */ 0x142d, /* VFMADD231PDZ256r */ /* Table12511 */ 0x164f, /* VFMSUB231PDZ256m */ 0x1655, /* VFMSUB231PDZ256r */ /* Table12513 */ 0x1877, /* VFNMADD231PDZ256m */ 0x187d, /* VFNMADD231PDZ256r */ /* Table12515 */ 0x19c3, /* VFNMSUB231PDZ256m */ 0x19c9, /* VFNMSUB231PDZ256r */ /* Table12517 */ 0x257f, /* VPCONFLICTQZ256rm */ 0x2585, /* VPCONFLICTQZ256rr */ /* Table12519 */ 0x2ce0, /* VPMOVUSWBZmr */ 0x2ce2, /* VPMOVUSWBZrr */ /* Table12521 */ 0x2c95, /* VPMOVUSDBZmr */ 0x2c97, /* VPMOVUSDBZrr */ /* Table12523 */ 0x2cb3, /* VPMOVUSQBZmr */ 0x2cb5, /* VPMOVUSQBZrr */ /* Table12525 */ 0x2ca4, /* VPMOVUSDWZmr */ 0x2ca6, /* VPMOVUSDWZrr */ /* Table12527 */ 0x2cd1, /* VPMOVUSQWZmr */ 0x2cd3, /* VPMOVUSQWZrr */ /* Table12529 */ 0x2cc2, /* VPMOVUSQDZmr */ 0x2cc4, /* VPMOVUSQDZrr */ /* Table12531 */ 0x2c02, /* VPMOVSWBZmr */ 0x2c04, /* VPMOVSWBZrr */ /* Table12533 */ 0x2bb7, /* VPMOVSDBZmr */ 0x2bb9, /* VPMOVSDBZrr */ /* Table12535 */ 0x2bd5, /* VPMOVSQBZmr */ 0x2bd7, /* VPMOVSQBZrr */ /* Table12537 */ 0x2bc6, /* VPMOVSDWZmr */ 0x2bc8, /* VPMOVSDWZrr */ /* Table12539 */ 0x2bf3, /* VPMOVSQWZmr */ 0x2bf5, /* VPMOVSQWZrr */ /* Table12541 */ 0x2be4, /* VPMOVSQDZmr */ 0x2be6, /* VPMOVSQDZrr */ /* Table12543 */ 0x359f, /* VPTESTNMBZrm */ 0x35a1, /* VPTESTNMBZrr */ /* Table12545 */ 0x35af, /* VPTESTNMDZrm */ 0x35b3, /* VPTESTNMDZrr */ /* Table12547 */ 0x0, /* */ 0x2b71, /* VPMOVM2BZrr */ /* Table12549 */ 0x0, /* */ 0x2b4d, /* VPMOVB2MZrr */ /* Table12551 */ 0x2cf2, /* VPMOVWBZmr */ 0x2cf4, /* VPMOVWBZrr */ /* Table12553 */ 0x2b5b, /* VPMOVDBZmr */ 0x2b5d, /* VPMOVDBZrr */ /* Table12555 */ 0x2b8a, /* VPMOVQBZmr */ 0x2b8c, /* VPMOVQBZrr */ /* Table12557 */ 0x2b6a, /* VPMOVDWZmr */ 0x2b6c, /* VPMOVDWZrr */ /* Table12559 */ 0x2ba8, /* VPMOVQWZmr */ 0x2baa, /* VPMOVQWZrr */ /* Table12561 */ 0x2b99, /* VPMOVQDZmr */ 0x2b9b, /* VPMOVQDZrr */ /* Table12563 */ 0x0, /* */ 0x2b74, /* VPMOVM2DZrr */ /* Table12565 */ 0x0, /* */ 0x2b50, /* VPMOVD2MZrr */ /* Table12567 */ 0x0, /* */ 0x231e, /* VPBROADCASTMW2DZrr */ /* Table12569 */ 0x202a, /* VP4DPWSSDrm */ 0x0, /* */ /* Table12571 */ 0x2027, /* VP4DPWSSDSrm */ 0x0, /* */ /* Table12573 */ 0xb4c, /* V4FMADDPSrm */ 0x0, /* */ /* Table12575 */ 0xb52, /* V4FNMADDPSrm */ 0x0, /* */ /* Table12577 */ 0x315e, /* VPSHUFBZrm */ 0x3161, /* VPSHUFBZrr */ /* Table12579 */ 0x298d, /* VPMADDUBSWZrm */ 0x2990, /* VPMADDUBSWZrr */ /* Table12581 */ 0x2da8, /* VPMULHRSWZrm */ 0x2dab, /* VPMULHRSWZrr */ /* Table12583 */ 0x2736, /* VPERMILPSZrm */ 0x273c, /* VPERMILPSZrr */ /* Table12585 */ 0xef3, /* VCVTPH2PSZrm */ 0xef6, /* VCVTPH2PSZrr */ /* Table12587 */ 0x2fb2, /* VPRORVDZrm */ 0x2fb8, /* VPRORVDZrr */ /* Table12589 */ 0x2f46, /* VPROLVDZrm */ 0x2f4c, /* VPROLVDZrr */ /* Table12591 */ 0x2774, /* VPERMPSZrm */ 0x277a, /* VPERMPSZrr */ /* Table12593 */ 0xd46, /* VBROADCASTSSZm */ 0xd49, /* VBROADCASTSSZr */ /* Table12595 */ 0xced, /* VBROADCASTF32X2Zm */ 0xcf0, /* VBROADCASTF32X2Zr */ /* Table12597 */ 0xcf6, /* VBROADCASTF32X4rm */ 0x0, /* */ /* Table12599 */ 0xcf9, /* VBROADCASTF32X8rm */ 0x0, /* */ /* Table12601 */ 0x203b, /* VPABSBZrm */ 0x203e, /* VPABSBZrr */ /* Table12603 */ 0x208b, /* VPABSWZrm */ 0x208e, /* VPABSWZrr */ /* Table12605 */ 0x2057, /* VPABSDZrm */ 0x205d, /* VPABSDZrr */ /* Table12607 */ 0x2c41, /* VPMOVSXBWZrm */ 0x2c44, /* VPMOVSXBWZrr */ /* Table12609 */ 0x2c15, /* VPMOVSXBDZrm */ 0x2c18, /* VPMOVSXBDZrr */ /* Table12611 */ 0x2c2b, /* VPMOVSXBQZrm */ 0x2c2e, /* VPMOVSXBQZrr */ /* Table12613 */ 0x2c6d, /* VPMOVSXWDZrm */ 0x2c70, /* VPMOVSXWDZrr */ /* Table12615 */ 0x2c83, /* VPMOVSXWQZrm */ 0x2c86, /* VPMOVSXWQZrr */ /* Table12617 */ 0x2c57, /* VPMOVSXDQZrm */ 0x2c5a, /* VPMOVSXDQZrr */ /* Table12619 */ 0x3563, /* VPTESTMBZrm */ 0x3565, /* VPTESTMBZrr */ /* Table12621 */ 0x3573, /* VPTESTMDZrm */ 0x3577, /* VPTESTMDZrr */ /* Table12623 */ 0x1ead, /* VMOVNTDQAZrm */ 0x0, /* */ /* Table12625 */ 0x20dc, /* VPACKUSDWZrm */ 0x20e2, /* VPACKUSDWZrr */ /* Table12627 */ 0x38fb, /* VSCALEFPSZrm */ 0x3901, /* VSCALEFPSZrr */ /* Table12629 */ 0x2d31, /* VPMOVZXBWZrm */ 0x2d34, /* VPMOVZXBWZrr */ /* Table12631 */ 0x2d05, /* VPMOVZXBDZrm */ 0x2d08, /* VPMOVZXBDZrr */ /* Table12633 */ 0x2d1b, /* VPMOVZXBQZrm */ 0x2d1e, /* VPMOVZXBQZrr */ /* Table12635 */ 0x2d5d, /* VPMOVZXWDZrm */ 0x2d60, /* VPMOVZXWDZrr */ /* Table12637 */ 0x2d73, /* VPMOVZXWQZrm */ 0x2d76, /* VPMOVZXWQZrr */ /* Table12639 */ 0x2d47, /* VPMOVZXDQZrm */ 0x2d4a, /* VPMOVZXDQZrr */ /* Table12641 */ 0x261e, /* VPERMDZrm */ 0x2624, /* VPERMDZrr */ /* Table12643 */ 0x2a8d, /* VPMINSBZrm */ 0x2a90, /* VPMINSBZrr */ /* Table12645 */ 0x2aa9, /* VPMINSDZrm */ 0x2aaf, /* VPMINSDZrr */ /* Table12647 */ 0x2b43, /* VPMINUWZrm */ 0x2b46, /* VPMINUWZrr */ /* Table12649 */ 0x2b0f, /* VPMINUDZrm */ 0x2b15, /* VPMINUDZrr */ /* Table12651 */ 0x29c1, /* VPMAXSBZrm */ 0x29c4, /* VPMAXSBZrr */ /* Table12653 */ 0x29dd, /* VPMAXSDZrm */ 0x29e3, /* VPMAXSDZrr */ /* Table12655 */ 0x2a77, /* VPMAXUWZrm */ 0x2a7a, /* VPMAXUWZrr */ /* Table12657 */ 0x2a43, /* VPMAXUDZrm */ 0x2a49, /* VPMAXUDZrr */ /* Table12659 */ 0x2df0, /* VPMULLDZrm */ 0x2df6, /* VPMULLDZrr */ /* Table12661 */ 0x1ac0, /* VGETEXPPSZm */ 0x1ac6, /* VGETEXPPSZr */ /* Table12663 */ 0x290d, /* VPLZCNTDZrm */ 0x2913, /* VPLZCNTDZrr */ /* Table12665 */ 0x33fd, /* VPSRLVDZrm */ 0x3403, /* VPSRLVDZrr */ /* Table12667 */ 0x3319, /* VPSRAVDZrm */ 0x331f, /* VPSRAVDZrr */ /* Table12669 */ 0x323f, /* VPSLLVDZrm */ 0x3245, /* VPSLLVDZrr */ /* Table12671 */ 0x3760, /* VRCP14PSZm */ 0x3766, /* VRCP14PSZr */ /* Table12673 */ 0x3884, /* VRSQRT14PSZm */ 0x388a, /* VRSQRT14PSZr */ /* Table12675 */ 0x25be, /* VPDPBUSDZm */ 0x25c4, /* VPDPBUSDZr */ /* Table12677 */ 0x25a3, /* VPDPBUSDSZm */ 0x25a9, /* VPDPBUSDSZr */ /* Table12679 */ 0x25f4, /* VPDPWSSDZm */ 0x25fa, /* VPDPWSSDZr */ /* Table12681 */ 0x25d9, /* VPDPWSSDSZm */ 0x25df, /* VPDPWSSDSZr */ /* Table12683 */ 0x2e72, /* VPOPCNTBZrm */ 0x2e75, /* VPOPCNTBZrr */ /* Table12685 */ 0x2e8a, /* VPOPCNTDZrm */ 0x2e90, /* VPOPCNTDZrr */ /* Table12687 */ 0x2308, /* VPBROADCASTDZm */ 0x230b, /* VPBROADCASTDZr */ /* Table12689 */ 0xd12, /* VBROADCASTI32X2Zm */ 0xd15, /* VBROADCASTI32X2Zr */ /* Table12691 */ 0xd1b, /* VBROADCASTI32X4rm */ 0x0, /* */ /* Table12693 */ 0xd1e, /* VBROADCASTI32X8rm */ 0x0, /* */ /* Table12695 */ 0x2851, /* VPEXPANDBZrm */ 0x2854, /* VPEXPANDBZrr */ /* Table12697 */ 0x2511, /* VPCOMPRESSBZmr */ 0x2513, /* VPCOMPRESSBZrr */ /* Table12699 */ 0x229d, /* VPBLENDMDZrm */ 0x22a3, /* VPBLENDMDZrr */ /* Table12701 */ 0xccd, /* VBLENDMPSZrm */ 0xcd3, /* VBLENDMPSZrr */ /* Table12703 */ 0x2285, /* VPBLENDMBZrm */ 0x2288, /* VPBLENDMBZrr */ /* Table12705 */ 0x3060, /* VPSHLDVDZm */ 0x3066, /* VPSHLDVDZr */ /* Table12707 */ 0x30fc, /* VPSHRDVDZm */ 0x3102, /* VPSHRDVDZr */ /* Table12709 */ 0x2633, /* VPERMI2Brm */ 0x2636, /* VPERMI2Brr */ /* Table12711 */ 0x264b, /* VPERMI2Drm */ 0x2651, /* VPERMI2Drr */ /* Table12713 */ 0x2681, /* VPERMI2PSrm */ 0x2687, /* VPERMI2PSrr */ /* Table12715 */ 0x22e9, /* VPBROADCASTBZm */ 0x22ec, /* VPBROADCASTBZr */ /* Table12717 */ 0x234c, /* VPBROADCASTWZm */ 0x234f, /* VPBROADCASTWZr */ /* Table12719 */ 0x0, /* */ 0x22f5, /* VPBROADCASTBrZr */ /* Table12721 */ 0x0, /* */ 0x2358, /* VPBROADCASTWrZr */ /* Table12723 */ 0x0, /* */ 0x2314, /* VPBROADCASTDrZr */ /* Table12725 */ 0x27af, /* VPERMT2Brm */ 0x27b2, /* VPERMT2Brr */ /* Table12727 */ 0x27c7, /* VPERMT2Drm */ 0x27cd, /* VPERMT2Drr */ /* Table12729 */ 0x27fd, /* VPERMT2PSrm */ 0x2803, /* VPERMT2PSrr */ /* Table12731 */ 0x12bc, /* VEXPANDPSZrm */ 0x12bf, /* VEXPANDPSZrr */ /* Table12733 */ 0x2863, /* VPEXPANDDZrm */ 0x2866, /* VPEXPANDDZrr */ /* Table12735 */ 0xe01, /* VCOMPRESSPSZmr */ 0xe03, /* VCOMPRESSPSZrr */ /* Table12737 */ 0x2520, /* VPCOMPRESSDZmr */ 0x2522, /* VPCOMPRESSDZrr */ /* Table12739 */ 0x260d, /* VPERMBZrm */ 0x2610, /* VPERMBZrr */ /* Table12741 */ 0x314c, /* VPSHUFBITQMBZrm */ 0x314e, /* VPSHUFBITQMBZrr */ /* Table12743 */ 0x14d6, /* VFMADDSUB132PSZm */ 0x14dc, /* VFMADDSUB132PSZr */ /* Table12745 */ 0x16de, /* VFMSUBADD132PSZm */ 0x16e4, /* VFMSUBADD132PSZr */ /* Table12747 */ 0x138a, /* VFMADD132PSZm */ 0x1390, /* VFMADD132PSZr */ /* Table12749 */ 0x15b2, /* VFMSUB132PSZm */ 0x15b8, /* VFMSUB132PSZr */ /* Table12751 */ 0x17da, /* VFNMADD132PSZm */ 0x17e0, /* VFNMADD132PSZr */ /* Table12753 */ 0x1926, /* VFNMSUB132PSZm */ 0x192c, /* VFNMSUB132PSZr */ /* Table12755 */ 0x151a, /* VFMADDSUB213PSZm */ 0x1520, /* VFMADDSUB213PSZr */ /* Table12757 */ 0x1722, /* VFMSUBADD213PSZm */ 0x1728, /* VFMSUBADD213PSZr */ /* Table12759 */ 0x13ee, /* VFMADD213PSZm */ 0x13f4, /* VFMADD213PSZr */ /* Table12761 */ 0x1616, /* VFMSUB213PSZm */ 0x161c, /* VFMSUB213PSZr */ /* Table12763 */ 0x183e, /* VFNMADD213PSZm */ 0x1844, /* VFNMADD213PSZr */ /* Table12765 */ 0x198a, /* VFNMSUB213PSZm */ 0x1990, /* VFNMSUB213PSZr */ /* Table12767 */ 0x155e, /* VFMADDSUB231PSZm */ 0x1564, /* VFMADDSUB231PSZr */ /* Table12769 */ 0x1766, /* VFMSUBADD231PSZm */ 0x176c, /* VFMSUBADD231PSZr */ /* Table12771 */ 0x1452, /* VFMADD231PSZm */ 0x1458, /* VFMADD231PSZr */ /* Table12773 */ 0x167a, /* VFMSUB231PSZm */ 0x1680, /* VFMSUB231PSZr */ /* Table12775 */ 0x18a2, /* VFNMADD231PSZm */ 0x18a8, /* VFNMADD231PSZr */ /* Table12777 */ 0x19ee, /* VFNMSUB231PSZm */ 0x19f4, /* VFNMSUB231PSZr */ /* Table12779 */ 0x256d, /* VPCONFLICTDZrm */ 0x2573, /* VPCONFLICTDZrr */ /* Table12781 */ 0x1292, /* VEXP2PSZm */ 0x1298, /* VEXP2PSZr */ /* Table12783 */ 0x3781, /* VRCP28PSZm */ 0x3787, /* VRCP28PSZr */ /* Table12785 */ 0x38a5, /* VRSQRT28PSZm */ 0x38ab, /* VRSQRT28PSZr */ /* Table12787 */ 0x1b78, /* VGF2P8MULBZrm */ 0x1b7b, /* VGF2P8MULBZrr */ /* Table12789 */ 0xbe6, /* VAESENCZrm */ 0xbe7, /* VAESENCZrr */ /* Table12791 */ 0xbdc, /* VAESENCLASTZrm */ 0xbdd, /* VAESENCLASTZrr */ /* Table12793 */ 0xbd2, /* VAESDECZrm */ 0xbd3, /* VAESDECZrr */ /* Table12795 */ 0xbc8, /* VAESDECLASTZrm */ 0xbc9, /* VAESDECLASTZrr */ /* Table12797 */ 0x35cf, /* VPTESTNMWZrm */ 0x35d1, /* VPTESTNMWZrr */ /* Table12799 */ 0x35c1, /* VPTESTNMQZrm */ 0x35c5, /* VPTESTNMQZrr */ /* Table12801 */ 0x0, /* */ 0x2b7a, /* VPMOVM2WZrr */ /* Table12803 */ 0x0, /* */ 0x2ce7, /* VPMOVW2MZrr */ /* Table12805 */ 0x0, /* */ 0x231b, /* VPBROADCASTMB2QZrr */ /* Table12807 */ 0x0, /* */ 0x2b77, /* VPMOVM2QZrr */ /* Table12809 */ 0x0, /* */ 0x2b7f, /* VPMOVQ2MZrr */ /* Table12811 */ 0x26f8, /* VPERMILPDZrm */ 0x26fe, /* VPERMILPDZrr */ /* Table12813 */ 0x3433, /* VPSRLVWZrm */ 0x3436, /* VPSRLVWZrr */ /* Table12815 */ 0x334b, /* VPSRAVWZrm */ 0x334e, /* VPSRAVWZrr */ /* Table12817 */ 0x3275, /* VPSLLVWZrm */ 0x3278, /* VPSLLVWZrr */ /* Table12819 */ 0x2fcd, /* VPRORVQZrm */ 0x2fd3, /* VPRORVQZrr */ /* Table12821 */ 0x2f61, /* VPROLVQZrm */ 0x2f67, /* VPROLVQZrr */ /* Table12823 */ 0x2760, /* VPERMPDZrm */ 0x2766, /* VPERMPDZrr */ /* Table12825 */ 0xd32, /* VBROADCASTSDZm */ 0xd35, /* VBROADCASTSDZr */ /* Table12827 */ 0xcff, /* VBROADCASTF64X2rm */ 0x0, /* */ /* Table12829 */ 0xd02, /* VBROADCASTF64X4rm */ 0x0, /* */ /* Table12831 */ 0x2074, /* VPABSQZrm */ 0x207a, /* VPABSQZrr */ /* Table12833 */ 0x3593, /* VPTESTMWZrm */ 0x3595, /* VPTESTMWZrr */ /* Table12835 */ 0x3585, /* VPTESTMQZrm */ 0x3589, /* VPTESTMQZrr */ /* Table12837 */ 0x2d8f, /* VPMULDQZrm */ 0x2d95, /* VPMULDQZrr */ /* Table12839 */ 0x23df, /* VPCMPEQQZrm */ 0x23e3, /* VPCMPEQQZrr */ /* Table12841 */ 0x38dd, /* VSCALEFPDZrm */ 0x38e3, /* VSCALEFPDZrr */ /* Table12843 */ 0x279a, /* VPERMQZrm */ 0x27a0, /* VPERMQZrr */ /* Table12845 */ 0x242f, /* VPCMPGTQZrm */ 0x2433, /* VPCMPGTQZrr */ /* Table12847 */ 0x2ac6, /* VPMINSQZrm */ 0x2acc, /* VPMINSQZrr */ /* Table12849 */ 0x2b2c, /* VPMINUQZrm */ 0x2b32, /* VPMINUQZrr */ /* Table12851 */ 0x29fa, /* VPMAXSQZrm */ 0x2a00, /* VPMAXSQZrr */ /* Table12853 */ 0x2a60, /* VPMAXUQZrm */ 0x2a66, /* VPMAXUQZrr */ /* Table12855 */ 0x2e0d, /* VPMULLQZrm */ 0x2e13, /* VPMULLQZrr */ /* Table12857 */ 0x1aa2, /* VGETEXPPDZm */ 0x1aa8, /* VGETEXPPDZr */ /* Table12859 */ 0x2928, /* VPLZCNTQZrm */ 0x292e, /* VPLZCNTQZrr */ /* Table12861 */ 0x341c, /* VPSRLVQZrm */ 0x3422, /* VPSRLVQZrr */ /* Table12863 */ 0x3336, /* VPSRAVQZrm */ 0x333c, /* VPSRAVQZrr */ /* Table12865 */ 0x325e, /* VPSLLVQZrm */ 0x3264, /* VPSLLVQZrr */ /* Table12867 */ 0x3745, /* VRCP14PDZm */ 0x374b, /* VRCP14PDZr */ /* Table12869 */ 0x3869, /* VRSQRT14PDZm */ 0x386f, /* VRSQRT14PDZr */ /* Table12871 */ 0x2eba, /* VPOPCNTWZrm */ 0x2ebd, /* VPOPCNTWZrr */ /* Table12873 */ 0x2ea5, /* VPOPCNTQZrm */ 0x2eab, /* VPOPCNTQZrr */ /* Table12875 */ 0x232d, /* VPBROADCASTQZm */ 0x2330, /* VPBROADCASTQZr */ /* Table12877 */ 0xd24, /* VBROADCASTI64X2rm */ 0x0, /* */ /* Table12879 */ 0xd27, /* VBROADCASTI64X4rm */ 0x0, /* */ /* Table12881 */ 0x2887, /* VPEXPANDWZrm */ 0x288a, /* VPEXPANDWZrr */ /* Table12883 */ 0x253e, /* VPCOMPRESSWZmr */ 0x2540, /* VPCOMPRESSWZrr */ /* Table12885 */ 0x22b8, /* VPBLENDMQZrm */ 0x22be, /* VPBLENDMQZrr */ /* Table12887 */ 0xcb2, /* VBLENDMPDZrm */ 0xcb8, /* VBLENDMPDZrr */ /* Table12889 */ 0x22cd, /* VPBLENDMWZrm */ 0x22d0, /* VPBLENDMWZrr */ /* Table12891 */ 0x3090, /* VPSHLDVWZm */ 0x3093, /* VPSHLDVWZr */ /* Table12893 */ 0x307b, /* VPSHLDVQZm */ 0x3081, /* VPSHLDVQZr */ /* Table12895 */ 0x312c, /* VPSHRDVWZm */ 0x312f, /* VPSHRDVWZr */ /* Table12897 */ 0x3117, /* VPSHRDVQZm */ 0x311d, /* VPSHRDVQZr */ /* Table12899 */ 0x26b1, /* VPERMI2Wrm */ 0x26b4, /* VPERMI2Wrr */ /* Table12901 */ 0x269c, /* VPERMI2Qrm */ 0x26a2, /* VPERMI2Qrr */ /* Table12903 */ 0x2666, /* VPERMI2PDrm */ 0x266c, /* VPERMI2PDrr */ /* Table12905 */ 0x0, /* */ 0x2339, /* VPBROADCASTQrZr */ /* Table12907 */ 0x282d, /* VPERMT2Wrm */ 0x2830, /* VPERMT2Wrr */ /* Table12909 */ 0x2818, /* VPERMT2Qrm */ 0x281e, /* VPERMT2Qrr */ /* Table12911 */ 0x27e2, /* VPERMT2PDrm */ 0x27e8, /* VPERMT2PDrr */ /* Table12913 */ 0x2e3e, /* VPMULTISHIFTQBZrm */ 0x2e44, /* VPMULTISHIFTQBZrr */ /* Table12915 */ 0x12aa, /* VEXPANDPDZrm */ 0x12ad, /* VEXPANDPDZrr */ /* Table12917 */ 0x2875, /* VPEXPANDQZrm */ 0x2878, /* VPEXPANDQZrr */ /* Table12919 */ 0xdf2, /* VCOMPRESSPDZmr */ 0xdf4, /* VCOMPRESSPDZrr */ /* Table12921 */ 0x252f, /* VPCOMPRESSQZmr */ 0x2531, /* VPCOMPRESSQZrr */ /* Table12923 */ 0x283f, /* VPERMWZrm */ 0x2842, /* VPERMWZrr */ /* Table12925 */ 0x14b4, /* VFMADDSUB132PDZm */ 0x14ba, /* VFMADDSUB132PDZr */ /* Table12927 */ 0x16bc, /* VFMSUBADD132PDZm */ 0x16c2, /* VFMSUBADD132PDZr */ /* Table12929 */ 0x1368, /* VFMADD132PDZm */ 0x136e, /* VFMADD132PDZr */ /* Table12931 */ 0x1590, /* VFMSUB132PDZm */ 0x1596, /* VFMSUB132PDZr */ /* Table12933 */ 0x17b8, /* VFNMADD132PDZm */ 0x17be, /* VFNMADD132PDZr */ /* Table12935 */ 0x1904, /* VFNMSUB132PDZm */ 0x190a, /* VFNMSUB132PDZr */ /* Table12937 */ 0x14f8, /* VFMADDSUB213PDZm */ 0x14fe, /* VFMADDSUB213PDZr */ /* Table12939 */ 0x1700, /* VFMSUBADD213PDZm */ 0x1706, /* VFMSUBADD213PDZr */ /* Table12941 */ 0x13cc, /* VFMADD213PDZm */ 0x13d2, /* VFMADD213PDZr */ /* Table12943 */ 0x15f4, /* VFMSUB213PDZm */ 0x15fa, /* VFMSUB213PDZr */ /* Table12945 */ 0x181c, /* VFNMADD213PDZm */ 0x1822, /* VFNMADD213PDZr */ /* Table12947 */ 0x1968, /* VFNMSUB213PDZm */ 0x196e, /* VFNMSUB213PDZr */ /* Table12949 */ 0x2976, /* VPMADD52LUQZm */ 0x297c, /* VPMADD52LUQZr */ /* Table12951 */ 0x295b, /* VPMADD52HUQZm */ 0x2961, /* VPMADD52HUQZr */ /* Table12953 */ 0x153c, /* VFMADDSUB231PDZm */ 0x1542, /* VFMADDSUB231PDZr */ /* Table12955 */ 0x1744, /* VFMSUBADD231PDZm */ 0x174a, /* VFMSUBADD231PDZr */ /* Table12957 */ 0x1430, /* VFMADD231PDZm */ 0x1436, /* VFMADD231PDZr */ /* Table12959 */ 0x1658, /* VFMSUB231PDZm */ 0x165e, /* VFMSUB231PDZr */ /* Table12961 */ 0x1880, /* VFNMADD231PDZm */ 0x1886, /* VFNMADD231PDZr */ /* Table12963 */ 0x19cc, /* VFNMSUB231PDZm */ 0x19d2, /* VFNMSUB231PDZr */ /* Table12965 */ 0x2588, /* VPCONFLICTQZrm */ 0x258e, /* VPCONFLICTQZrr */ /* Table12967 */ 0x1286, /* VEXP2PDZm */ 0x128c, /* VEXP2PDZr */ /* Table12969 */ 0x3775, /* VRCP28PDZm */ 0x377b, /* VRCP28PDZr */ /* Table12971 */ 0x3899, /* VRSQRT28PDZm */ 0x389f, /* VRSQRT28PDZr */ /* Table12973 */ 0x2cd7, /* VPMOVUSWBZ128mrk */ 0x2cd9, /* VPMOVUSWBZ128rrk */ /* Table12975 */ 0x2c8c, /* VPMOVUSDBZ128mrk */ 0x2c8e, /* VPMOVUSDBZ128rrk */ /* Table12977 */ 0x2caa, /* VPMOVUSQBZ128mrk */ 0x2cac, /* VPMOVUSQBZ128rrk */ /* Table12979 */ 0x2c9b, /* VPMOVUSDWZ128mrk */ 0x2c9d, /* VPMOVUSDWZ128rrk */ /* Table12981 */ 0x2cc8, /* VPMOVUSQWZ128mrk */ 0x2cca, /* VPMOVUSQWZ128rrk */ /* Table12983 */ 0x2cb9, /* VPMOVUSQDZ128mrk */ 0x2cbb, /* VPMOVUSQDZ128rrk */ /* Table12985 */ 0x2bf9, /* VPMOVSWBZ128mrk */ 0x2bfb, /* VPMOVSWBZ128rrk */ /* Table12987 */ 0x2bae, /* VPMOVSDBZ128mrk */ 0x2bb0, /* VPMOVSDBZ128rrk */ /* Table12989 */ 0x2bcc, /* VPMOVSQBZ128mrk */ 0x2bce, /* VPMOVSQBZ128rrk */ /* Table12991 */ 0x2bbd, /* VPMOVSDWZ128mrk */ 0x2bbf, /* VPMOVSDWZ128rrk */ /* Table12993 */ 0x2bea, /* VPMOVSQWZ128mrk */ 0x2bec, /* VPMOVSQWZ128rrk */ /* Table12995 */ 0x2bdb, /* VPMOVSQDZ128mrk */ 0x2bdd, /* VPMOVSQDZ128rrk */ /* Table12997 */ 0x3598, /* VPTESTNMBZ128rmk */ 0x359a, /* VPTESTNMBZ128rrk */ /* Table12999 */ 0x35a6, /* VPTESTNMDZ128rmk */ 0x35a8, /* VPTESTNMDZ128rrk */ /* Table13001 */ 0x2ce9, /* VPMOVWBZ128mrk */ 0x2ceb, /* VPMOVWBZ128rrk */ /* Table13003 */ 0x2b52, /* VPMOVDBZ128mrk */ 0x2b54, /* VPMOVDBZ128rrk */ /* Table13005 */ 0x2b81, /* VPMOVQBZ128mrk */ 0x2b83, /* VPMOVQBZ128rrk */ /* Table13007 */ 0x2b61, /* VPMOVDWZ128mrk */ 0x2b63, /* VPMOVDWZ128rrk */ /* Table13009 */ 0x2b9f, /* VPMOVQWZ128mrk */ 0x2ba1, /* VPMOVQWZ128rrk */ /* Table13011 */ 0x2b90, /* VPMOVQDZ128mrk */ 0x2b92, /* VPMOVQDZ128rrk */ /* Table13013 */ 0xb50, /* V4FMADDSSrmk */ 0x0, /* */ /* Table13015 */ 0xb56, /* V4FNMADDSSrmk */ 0x0, /* */ /* Table13017 */ 0x3153, /* VPSHUFBZ128rmk */ 0x3156, /* VPSHUFBZ128rrk */ /* Table13019 */ 0x2982, /* VPMADDUBSWZ128rmk */ 0x2985, /* VPMADDUBSWZ128rrk */ /* Table13021 */ 0x2d9d, /* VPMULHRSWZ128rmk */ 0x2da0, /* VPMULHRSWZ128rrk */ /* Table13023 */ 0x2716, /* VPERMILPSZ128rmk */ 0x2719, /* VPERMILPSZ128rrk */ /* Table13025 */ 0xee8, /* VCVTPH2PSZ128rmk */ 0xeeb, /* VCVTPH2PSZ128rrk */ /* Table13027 */ 0x2fa4, /* VPRORVDZ128rmk */ 0x2fa7, /* VPRORVDZ128rrk */ /* Table13029 */ 0x2f38, /* VPROLVDZ128rmk */ 0x2f3b, /* VPROLVDZ128rrk */ /* Table13031 */ 0xd3b, /* VBROADCASTSSZ128mk */ 0xd3e, /* VBROADCASTSSZ128rk */ /* Table13033 */ 0x2030, /* VPABSBZ128rmk */ 0x2033, /* VPABSBZ128rrk */ /* Table13035 */ 0x2080, /* VPABSWZ128rmk */ 0x2083, /* VPABSWZ128rrk */ /* Table13037 */ 0x2049, /* VPABSDZ128rmk */ 0x204c, /* VPABSDZ128rrk */ /* Table13039 */ 0x2c36, /* VPMOVSXBWZ128rmk */ 0x2c39, /* VPMOVSXBWZ128rrk */ /* Table13041 */ 0x2c0a, /* VPMOVSXBDZ128rmk */ 0x2c0d, /* VPMOVSXBDZ128rrk */ /* Table13043 */ 0x2c20, /* VPMOVSXBQZ128rmk */ 0x2c23, /* VPMOVSXBQZ128rrk */ /* Table13045 */ 0x2c62, /* VPMOVSXWDZ128rmk */ 0x2c65, /* VPMOVSXWDZ128rrk */ /* Table13047 */ 0x2c78, /* VPMOVSXWQZ128rmk */ 0x2c7b, /* VPMOVSXWQZ128rrk */ /* Table13049 */ 0x2c4c, /* VPMOVSXDQZ128rmk */ 0x2c4f, /* VPMOVSXDQZ128rrk */ /* Table13051 */ 0x355c, /* VPTESTMBZ128rmk */ 0x355e, /* VPTESTMBZ128rrk */ /* Table13053 */ 0x356a, /* VPTESTMDZ128rmk */ 0x356c, /* VPTESTMDZ128rrk */ /* Table13055 */ 0x20ce, /* VPACKUSDWZ128rmk */ 0x20d1, /* VPACKUSDWZ128rrk */ /* Table13057 */ 0x38ed, /* VSCALEFPSZ128rmk */ 0x38f0, /* VSCALEFPSZ128rrk */ /* Table13059 */ 0x3911, /* VSCALEFSSZrmk */ 0x3917, /* VSCALEFSSZrrk */ /* Table13061 */ 0x2d26, /* VPMOVZXBWZ128rmk */ 0x2d29, /* VPMOVZXBWZ128rrk */ /* Table13063 */ 0x2cfa, /* VPMOVZXBDZ128rmk */ 0x2cfd, /* VPMOVZXBDZ128rrk */ /* Table13065 */ 0x2d10, /* VPMOVZXBQZ128rmk */ 0x2d13, /* VPMOVZXBQZ128rrk */ /* Table13067 */ 0x2d52, /* VPMOVZXWDZ128rmk */ 0x2d55, /* VPMOVZXWDZ128rrk */ /* Table13069 */ 0x2d68, /* VPMOVZXWQZ128rmk */ 0x2d6b, /* VPMOVZXWQZ128rrk */ /* Table13071 */ 0x2d3c, /* VPMOVZXDQZ128rmk */ 0x2d3f, /* VPMOVZXDQZ128rrk */ /* Table13073 */ 0x2a82, /* VPMINSBZ128rmk */ 0x2a85, /* VPMINSBZ128rrk */ /* Table13075 */ 0x2a9b, /* VPMINSDZ128rmk */ 0x2a9e, /* VPMINSDZ128rrk */ /* Table13077 */ 0x2b38, /* VPMINUWZ128rmk */ 0x2b3b, /* VPMINUWZ128rrk */ /* Table13079 */ 0x2b01, /* VPMINUDZ128rmk */ 0x2b04, /* VPMINUDZ128rrk */ /* Table13081 */ 0x29b6, /* VPMAXSBZ128rmk */ 0x29b9, /* VPMAXSBZ128rrk */ /* Table13083 */ 0x29cf, /* VPMAXSDZ128rmk */ 0x29d2, /* VPMAXSDZ128rrk */ /* Table13085 */ 0x2a6c, /* VPMAXUWZ128rmk */ 0x2a6f, /* VPMAXUWZ128rrk */ /* Table13087 */ 0x2a35, /* VPMAXUDZ128rmk */ 0x2a38, /* VPMAXUDZ128rrk */ /* Table13089 */ 0x2de2, /* VPMULLDZ128rmk */ 0x2de5, /* VPMULLDZ128rrk */ /* Table13091 */ 0x1ab2, /* VGETEXPPSZ128mk */ 0x1ab5, /* VGETEXPPSZ128rk */ /* Table13093 */ 0x1ad6, /* VGETEXPSSZmk */ 0x1adc, /* VGETEXPSSZrk */ /* Table13095 */ 0x28ff, /* VPLZCNTDZ128rmk */ 0x2902, /* VPLZCNTDZ128rrk */ /* Table13097 */ 0x33ef, /* VPSRLVDZ128rmk */ 0x33f2, /* VPSRLVDZ128rrk */ /* Table13099 */ 0x330b, /* VPSRAVDZ128rmk */ 0x330e, /* VPSRAVDZ128rrk */ /* Table13101 */ 0x3231, /* VPSLLVDZ128rmk */ 0x3234, /* VPSLLVDZ128rrk */ /* Table13103 */ 0x3752, /* VRCP14PSZ128mk */ 0x3755, /* VRCP14PSZ128rk */ /* Table13105 */ 0x3770, /* VRCP14SSZrmk */ 0x3773, /* VRCP14SSZrrk */ /* Table13107 */ 0x3876, /* VRSQRT14PSZ128mk */ 0x3879, /* VRSQRT14PSZ128rk */ /* Table13109 */ 0x3894, /* VRSQRT14SSZrmk */ 0x3897, /* VRSQRT14SSZrrk */ /* Table13111 */ 0x25b0, /* VPDPBUSDZ128mk */ 0x25b3, /* VPDPBUSDZ128rk */ /* Table13113 */ 0x2595, /* VPDPBUSDSZ128mk */ 0x2598, /* VPDPBUSDSZ128rk */ /* Table13115 */ 0x25e6, /* VPDPWSSDZ128mk */ 0x25e9, /* VPDPWSSDZ128rk */ /* Table13117 */ 0x25cb, /* VPDPWSSDSZ128mk */ 0x25ce, /* VPDPWSSDSZ128rk */ /* Table13119 */ 0x2e67, /* VPOPCNTBZ128rmk */ 0x2e6a, /* VPOPCNTBZ128rrk */ /* Table13121 */ 0x2e7c, /* VPOPCNTDZ128rmk */ 0x2e7f, /* VPOPCNTDZ128rrk */ /* Table13123 */ 0x22fd, /* VPBROADCASTDZ128mk */ 0x2300, /* VPBROADCASTDZ128rk */ /* Table13125 */ 0xd07, /* VBROADCASTI32X2Z128mk */ 0xd0a, /* VBROADCASTI32X2Z128rk */ /* Table13127 */ 0x2846, /* VPEXPANDBZ128rmk */ 0x2849, /* VPEXPANDBZ128rrk */ /* Table13129 */ 0x2508, /* VPCOMPRESSBZ128mrk */ 0x250a, /* VPCOMPRESSBZ128rrk */ /* Table13131 */ 0x228f, /* VPBLENDMDZ128rmk */ 0x2292, /* VPBLENDMDZ128rrk */ /* Table13133 */ 0xcbf, /* VBLENDMPSZ128rmk */ 0xcc2, /* VBLENDMPSZ128rrk */ /* Table13135 */ 0x227a, /* VPBLENDMBZ128rmk */ 0x227d, /* VPBLENDMBZ128rrk */ /* Table13137 */ 0x3052, /* VPSHLDVDZ128mk */ 0x3055, /* VPSHLDVDZ128rk */ /* Table13139 */ 0x30ee, /* VPSHRDVDZ128mk */ 0x30f1, /* VPSHRDVDZ128rk */ /* Table13141 */ 0x2628, /* VPERMI2B128rmk */ 0x262b, /* VPERMI2B128rrk */ /* Table13143 */ 0x263d, /* VPERMI2D128rmk */ 0x2640, /* VPERMI2D128rrk */ /* Table13145 */ 0x2673, /* VPERMI2PS128rmk */ 0x2676, /* VPERMI2PS128rrk */ /* Table13147 */ 0x22de, /* VPBROADCASTBZ128mk */ 0x22e1, /* VPBROADCASTBZ128rk */ /* Table13149 */ 0x2341, /* VPBROADCASTWZ128mk */ 0x2344, /* VPBROADCASTWZ128rk */ /* Table13151 */ 0x0, /* */ 0x22f0, /* VPBROADCASTBrZ128rk */ /* Table13153 */ 0x0, /* */ 0x2353, /* VPBROADCASTWrZ128rk */ /* Table13155 */ 0x0, /* */ 0x230f, /* VPBROADCASTDrZ128rk */ /* Table13157 */ 0x27a4, /* VPERMT2B128rmk */ 0x27a7, /* VPERMT2B128rrk */ /* Table13159 */ 0x27b9, /* VPERMT2D128rmk */ 0x27bc, /* VPERMT2D128rrk */ /* Table13161 */ 0x27ef, /* VPERMT2PS128rmk */ 0x27f2, /* VPERMT2PS128rrk */ /* Table13163 */ 0x12b1, /* VEXPANDPSZ128rmk */ 0x12b4, /* VEXPANDPSZ128rrk */ /* Table13165 */ 0x2858, /* VPEXPANDDZ128rmk */ 0x285b, /* VPEXPANDDZ128rrk */ /* Table13167 */ 0xdf8, /* VCOMPRESSPSZ128mrk */ 0xdfa, /* VCOMPRESSPSZ128rrk */ /* Table13169 */ 0x2517, /* VPCOMPRESSDZ128mrk */ 0x2519, /* VPCOMPRESSDZ128rrk */ /* Table13171 */ 0x2602, /* VPERMBZ128rmk */ 0x2605, /* VPERMBZ128rrk */ /* Table13173 */ 0x3145, /* VPSHUFBITQMBZ128rmk */ 0x3147, /* VPSHUFBITQMBZ128rrk */ /* Table13175 */ 0x28a0, /* VPGATHERDDZ128rm */ 0x0, /* */ /* Table13177 */ 0x28aa, /* VPGATHERQDZ128rm */ 0x0, /* */ /* Table13179 */ 0x1a7a, /* VGATHERDPSZ128rm */ 0x0, /* */ /* Table13181 */ 0x1a8c, /* VGATHERQPSZ128rm */ 0x0, /* */ /* Table13183 */ 0x14c8, /* VFMADDSUB132PSZ128mk */ 0x14cb, /* VFMADDSUB132PSZ128rk */ /* Table13185 */ 0x16d0, /* VFMSUBADD132PSZ128mk */ 0x16d3, /* VFMSUBADD132PSZ128rk */ /* Table13187 */ 0x137c, /* VFMADD132PSZ128mk */ 0x137f, /* VFMADD132PSZ128rk */ /* Table13189 */ 0x13aa, /* VFMADD132SSZm_Intk */ 0x13ae, /* VFMADD132SSZr_Intk */ /* Table13191 */ 0x15a4, /* VFMSUB132PSZ128mk */ 0x15a7, /* VFMSUB132PSZ128rk */ /* Table13193 */ 0x15d2, /* VFMSUB132SSZm_Intk */ 0x15d6, /* VFMSUB132SSZr_Intk */ /* Table13195 */ 0x17cc, /* VFNMADD132PSZ128mk */ 0x17cf, /* VFNMADD132PSZ128rk */ /* Table13197 */ 0x17fa, /* VFNMADD132SSZm_Intk */ 0x17fe, /* VFNMADD132SSZr_Intk */ /* Table13199 */ 0x1918, /* VFNMSUB132PSZ128mk */ 0x191b, /* VFNMSUB132PSZ128rk */ /* Table13201 */ 0x1946, /* VFNMSUB132SSZm_Intk */ 0x194a, /* VFNMSUB132SSZr_Intk */ /* Table13203 */ 0x2ff8, /* VPSCATTERDDZ128mr */ 0x0, /* */ /* Table13205 */ 0x2ffe, /* VPSCATTERQDZ128mr */ 0x0, /* */ /* Table13207 */ 0x391c, /* VSCATTERDPSZ128mr */ 0x0, /* */ /* Table13209 */ 0x392a, /* VSCATTERQPSZ128mr */ 0x0, /* */ /* Table13211 */ 0x150c, /* VFMADDSUB213PSZ128mk */ 0x150f, /* VFMADDSUB213PSZ128rk */ /* Table13213 */ 0x1714, /* VFMSUBADD213PSZ128mk */ 0x1717, /* VFMSUBADD213PSZ128rk */ /* Table13215 */ 0x13e0, /* VFMADD213PSZ128mk */ 0x13e3, /* VFMADD213PSZ128rk */ /* Table13217 */ 0x140e, /* VFMADD213SSZm_Intk */ 0x1412, /* VFMADD213SSZr_Intk */ /* Table13219 */ 0x1608, /* VFMSUB213PSZ128mk */ 0x160b, /* VFMSUB213PSZ128rk */ /* Table13221 */ 0x1636, /* VFMSUB213SSZm_Intk */ 0x163a, /* VFMSUB213SSZr_Intk */ /* Table13223 */ 0x1830, /* VFNMADD213PSZ128mk */ 0x1833, /* VFNMADD213PSZ128rk */ /* Table13225 */ 0x185e, /* VFNMADD213SSZm_Intk */ 0x1862, /* VFNMADD213SSZr_Intk */ /* Table13227 */ 0x197c, /* VFNMSUB213PSZ128mk */ 0x197f, /* VFNMSUB213PSZ128rk */ /* Table13229 */ 0x19aa, /* VFNMSUB213SSZm_Intk */ 0x19ae, /* VFNMSUB213SSZr_Intk */ /* Table13231 */ 0x1550, /* VFMADDSUB231PSZ128mk */ 0x1553, /* VFMADDSUB231PSZ128rk */ /* Table13233 */ 0x1758, /* VFMSUBADD231PSZ128mk */ 0x175b, /* VFMSUBADD231PSZ128rk */ /* Table13235 */ 0x1444, /* VFMADD231PSZ128mk */ 0x1447, /* VFMADD231PSZ128rk */ /* Table13237 */ 0x1472, /* VFMADD231SSZm_Intk */ 0x1476, /* VFMADD231SSZr_Intk */ /* Table13239 */ 0x166c, /* VFMSUB231PSZ128mk */ 0x166f, /* VFMSUB231PSZ128rk */ /* Table13241 */ 0x169a, /* VFMSUB231SSZm_Intk */ 0x169e, /* VFMSUB231SSZr_Intk */ /* Table13243 */ 0x1894, /* VFNMADD231PSZ128mk */ 0x1897, /* VFNMADD231PSZ128rk */ /* Table13245 */ 0x18c2, /* VFNMADD231SSZm_Intk */ 0x18c6, /* VFNMADD231SSZr_Intk */ /* Table13247 */ 0x19e0, /* VFNMSUB231PSZ128mk */ 0x19e3, /* VFNMSUB231PSZ128rk */ /* Table13249 */ 0x1a0e, /* VFNMSUB231SSZm_Intk */ 0x1a12, /* VFNMSUB231SSZr_Intk */ /* Table13251 */ 0x255f, /* VPCONFLICTDZ128rmk */ 0x2562, /* VPCONFLICTDZ128rrk */ /* Table13253 */ 0x3797, /* VRCP28SSZmk */ 0x379d, /* VRCP28SSZrk */ /* Table13255 */ 0x38bb, /* VRSQRT28SSZmk */ 0x38c1, /* VRSQRT28SSZrk */ /* Table13257 */ 0x1b6d, /* VGF2P8MULBZ128rmk */ 0x1b70, /* VGF2P8MULBZ128rrk */ /* Table13259 */ 0x35c8, /* VPTESTNMWZ128rmk */ 0x35ca, /* VPTESTNMWZ128rrk */ /* Table13261 */ 0x35b8, /* VPTESTNMQZ128rmk */ 0x35ba, /* VPTESTNMQZ128rrk */ /* Table13263 */ 0x26d8, /* VPERMILPDZ128rmk */ 0x26db, /* VPERMILPDZ128rrk */ /* Table13265 */ 0x3428, /* VPSRLVWZ128rmk */ 0x342b, /* VPSRLVWZ128rrk */ /* Table13267 */ 0x3340, /* VPSRAVWZ128rmk */ 0x3343, /* VPSRAVWZ128rrk */ /* Table13269 */ 0x326a, /* VPSLLVWZ128rmk */ 0x326d, /* VPSLLVWZ128rrk */ /* Table13271 */ 0x2fbf, /* VPRORVQZ128rmk */ 0x2fc2, /* VPRORVQZ128rrk */ /* Table13273 */ 0x2f53, /* VPROLVQZ128rmk */ 0x2f56, /* VPROLVQZ128rrk */ /* Table13275 */ 0x2066, /* VPABSQZ128rmk */ 0x2069, /* VPABSQZ128rrk */ /* Table13277 */ 0x358c, /* VPTESTMWZ128rmk */ 0x358e, /* VPTESTMWZ128rrk */ /* Table13279 */ 0x357c, /* VPTESTMQZ128rmk */ 0x357e, /* VPTESTMQZ128rrk */ /* Table13281 */ 0x2d81, /* VPMULDQZ128rmk */ 0x2d84, /* VPMULDQZ128rrk */ /* Table13283 */ 0x23d6, /* VPCMPEQQZ128rmk */ 0x23d8, /* VPCMPEQQZ128rrk */ /* Table13285 */ 0x38cf, /* VSCALEFPDZ128rmk */ 0x38d2, /* VSCALEFPDZ128rrk */ /* Table13287 */ 0x3908, /* VSCALEFSDZrmk */ 0x390e, /* VSCALEFSDZrrk */ /* Table13289 */ 0x2426, /* VPCMPGTQZ128rmk */ 0x2428, /* VPCMPGTQZ128rrk */ /* Table13291 */ 0x2ab8, /* VPMINSQZ128rmk */ 0x2abb, /* VPMINSQZ128rrk */ /* Table13293 */ 0x2b1e, /* VPMINUQZ128rmk */ 0x2b21, /* VPMINUQZ128rrk */ /* Table13295 */ 0x29ec, /* VPMAXSQZ128rmk */ 0x29ef, /* VPMAXSQZ128rrk */ /* Table13297 */ 0x2a52, /* VPMAXUQZ128rmk */ 0x2a55, /* VPMAXUQZ128rrk */ /* Table13299 */ 0x2dff, /* VPMULLQZ128rmk */ 0x2e02, /* VPMULLQZ128rrk */ /* Table13301 */ 0x1a94, /* VGETEXPPDZ128mk */ 0x1a97, /* VGETEXPPDZ128rk */ /* Table13303 */ 0x1acd, /* VGETEXPSDZmk */ 0x1ad3, /* VGETEXPSDZrk */ /* Table13305 */ 0x291a, /* VPLZCNTQZ128rmk */ 0x291d, /* VPLZCNTQZ128rrk */ /* Table13307 */ 0x340e, /* VPSRLVQZ128rmk */ 0x3411, /* VPSRLVQZ128rrk */ /* Table13309 */ 0x3328, /* VPSRAVQZ128rmk */ 0x332b, /* VPSRAVQZ128rrk */ /* Table13311 */ 0x3250, /* VPSLLVQZ128rmk */ 0x3253, /* VPSLLVQZ128rrk */ /* Table13313 */ 0x3737, /* VRCP14PDZ128mk */ 0x373a, /* VRCP14PDZ128rk */ /* Table13315 */ 0x376a, /* VRCP14SDZrmk */ 0x376d, /* VRCP14SDZrrk */ /* Table13317 */ 0x385b, /* VRSQRT14PDZ128mk */ 0x385e, /* VRSQRT14PDZ128rk */ /* Table13319 */ 0x388e, /* VRSQRT14SDZrmk */ 0x3891, /* VRSQRT14SDZrrk */ /* Table13321 */ 0x2eaf, /* VPOPCNTWZ128rmk */ 0x2eb2, /* VPOPCNTWZ128rrk */ /* Table13323 */ 0x2e97, /* VPOPCNTQZ128rmk */ 0x2e9a, /* VPOPCNTQZ128rrk */ /* Table13325 */ 0x2322, /* VPBROADCASTQZ128mk */ 0x2325, /* VPBROADCASTQZ128rk */ /* Table13327 */ 0x287c, /* VPEXPANDWZ128rmk */ 0x287f, /* VPEXPANDWZ128rrk */ /* Table13329 */ 0x2535, /* VPCOMPRESSWZ128mrk */ 0x2537, /* VPCOMPRESSWZ128rrk */ /* Table13331 */ 0x22aa, /* VPBLENDMQZ128rmk */ 0x22ad, /* VPBLENDMQZ128rrk */ /* Table13333 */ 0xca4, /* VBLENDMPDZ128rmk */ 0xca7, /* VBLENDMPDZ128rrk */ /* Table13335 */ 0x22c2, /* VPBLENDMWZ128rmk */ 0x22c5, /* VPBLENDMWZ128rrk */ /* Table13337 */ 0x3085, /* VPSHLDVWZ128mk */ 0x3088, /* VPSHLDVWZ128rk */ /* Table13339 */ 0x306d, /* VPSHLDVQZ128mk */ 0x3070, /* VPSHLDVQZ128rk */ /* Table13341 */ 0x3121, /* VPSHRDVWZ128mk */ 0x3124, /* VPSHRDVWZ128rk */ /* Table13343 */ 0x3109, /* VPSHRDVQZ128mk */ 0x310c, /* VPSHRDVQZ128rk */ /* Table13345 */ 0x26a6, /* VPERMI2W128rmk */ 0x26a9, /* VPERMI2W128rrk */ /* Table13347 */ 0x268e, /* VPERMI2Q128rmk */ 0x2691, /* VPERMI2Q128rrk */ /* Table13349 */ 0x2658, /* VPERMI2PD128rmk */ 0x265b, /* VPERMI2PD128rrk */ /* Table13351 */ 0x0, /* */ 0x2334, /* VPBROADCASTQrZ128rk */ /* Table13353 */ 0x2822, /* VPERMT2W128rmk */ 0x2825, /* VPERMT2W128rrk */ /* Table13355 */ 0x280a, /* VPERMT2Q128rmk */ 0x280d, /* VPERMT2Q128rrk */ /* Table13357 */ 0x27d4, /* VPERMT2PD128rmk */ 0x27d7, /* VPERMT2PD128rrk */ /* Table13359 */ 0x2e30, /* VPMULTISHIFTQBZ128rmk */ 0x2e33, /* VPMULTISHIFTQBZ128rrk */ /* Table13361 */ 0x129f, /* VEXPANDPDZ128rmk */ 0x12a2, /* VEXPANDPDZ128rrk */ /* Table13363 */ 0x286a, /* VPEXPANDQZ128rmk */ 0x286d, /* VPEXPANDQZ128rrk */ /* Table13365 */ 0xde9, /* VCOMPRESSPDZ128mrk */ 0xdeb, /* VCOMPRESSPDZ128rrk */ /* Table13367 */ 0x2526, /* VPCOMPRESSQZ128mrk */ 0x2528, /* VPCOMPRESSQZ128rrk */ /* Table13369 */ 0x2834, /* VPERMWZ128rmk */ 0x2837, /* VPERMWZ128rrk */ /* Table13371 */ 0x28a5, /* VPGATHERDQZ128rm */ 0x0, /* */ /* Table13373 */ 0x28af, /* VPGATHERQQZ128rm */ 0x0, /* */ /* Table13375 */ 0x1a75, /* VGATHERDPDZ128rm */ 0x0, /* */ /* Table13377 */ 0x1a87, /* VGATHERQPDZ128rm */ 0x0, /* */ /* Table13379 */ 0x14a6, /* VFMADDSUB132PDZ128mk */ 0x14a9, /* VFMADDSUB132PDZ128rk */ /* Table13381 */ 0x16ae, /* VFMSUBADD132PDZ128mk */ 0x16b1, /* VFMSUBADD132PDZ128rk */ /* Table13383 */ 0x135a, /* VFMADD132PDZ128mk */ 0x135d, /* VFMADD132PDZ128rk */ /* Table13385 */ 0x139a, /* VFMADD132SDZm_Intk */ 0x139e, /* VFMADD132SDZr_Intk */ /* Table13387 */ 0x1582, /* VFMSUB132PDZ128mk */ 0x1585, /* VFMSUB132PDZ128rk */ /* Table13389 */ 0x15c2, /* VFMSUB132SDZm_Intk */ 0x15c6, /* VFMSUB132SDZr_Intk */ /* Table13391 */ 0x17aa, /* VFNMADD132PDZ128mk */ 0x17ad, /* VFNMADD132PDZ128rk */ /* Table13393 */ 0x17ea, /* VFNMADD132SDZm_Intk */ 0x17ee, /* VFNMADD132SDZr_Intk */ /* Table13395 */ 0x18f6, /* VFNMSUB132PDZ128mk */ 0x18f9, /* VFNMSUB132PDZ128rk */ /* Table13397 */ 0x1936, /* VFNMSUB132SDZm_Intk */ 0x193a, /* VFNMSUB132SDZr_Intk */ /* Table13399 */ 0x2ffb, /* VPSCATTERDQZ128mr */ 0x0, /* */ /* Table13401 */ 0x3001, /* VPSCATTERQQZ128mr */ 0x0, /* */ /* Table13403 */ 0x3919, /* VSCATTERDPDZ128mr */ 0x0, /* */ /* Table13405 */ 0x3927, /* VSCATTERQPDZ128mr */ 0x0, /* */ /* Table13407 */ 0x14ea, /* VFMADDSUB213PDZ128mk */ 0x14ed, /* VFMADDSUB213PDZ128rk */ /* Table13409 */ 0x16f2, /* VFMSUBADD213PDZ128mk */ 0x16f5, /* VFMSUBADD213PDZ128rk */ /* Table13411 */ 0x13be, /* VFMADD213PDZ128mk */ 0x13c1, /* VFMADD213PDZ128rk */ /* Table13413 */ 0x13fe, /* VFMADD213SDZm_Intk */ 0x1402, /* VFMADD213SDZr_Intk */ /* Table13415 */ 0x15e6, /* VFMSUB213PDZ128mk */ 0x15e9, /* VFMSUB213PDZ128rk */ /* Table13417 */ 0x1626, /* VFMSUB213SDZm_Intk */ 0x162a, /* VFMSUB213SDZr_Intk */ /* Table13419 */ 0x180e, /* VFNMADD213PDZ128mk */ 0x1811, /* VFNMADD213PDZ128rk */ /* Table13421 */ 0x184e, /* VFNMADD213SDZm_Intk */ 0x1852, /* VFNMADD213SDZr_Intk */ /* Table13423 */ 0x195a, /* VFNMSUB213PDZ128mk */ 0x195d, /* VFNMSUB213PDZ128rk */ /* Table13425 */ 0x199a, /* VFNMSUB213SDZm_Intk */ 0x199e, /* VFNMSUB213SDZr_Intk */ /* Table13427 */ 0x2968, /* VPMADD52LUQZ128mk */ 0x296b, /* VPMADD52LUQZ128rk */ /* Table13429 */ 0x294d, /* VPMADD52HUQZ128mk */ 0x2950, /* VPMADD52HUQZ128rk */ /* Table13431 */ 0x152e, /* VFMADDSUB231PDZ128mk */ 0x1531, /* VFMADDSUB231PDZ128rk */ /* Table13433 */ 0x1736, /* VFMSUBADD231PDZ128mk */ 0x1739, /* VFMSUBADD231PDZ128rk */ /* Table13435 */ 0x1422, /* VFMADD231PDZ128mk */ 0x1425, /* VFMADD231PDZ128rk */ /* Table13437 */ 0x1462, /* VFMADD231SDZm_Intk */ 0x1466, /* VFMADD231SDZr_Intk */ /* Table13439 */ 0x164a, /* VFMSUB231PDZ128mk */ 0x164d, /* VFMSUB231PDZ128rk */ /* Table13441 */ 0x168a, /* VFMSUB231SDZm_Intk */ 0x168e, /* VFMSUB231SDZr_Intk */ /* Table13443 */ 0x1872, /* VFNMADD231PDZ128mk */ 0x1875, /* VFNMADD231PDZ128rk */ /* Table13445 */ 0x18b2, /* VFNMADD231SDZm_Intk */ 0x18b6, /* VFNMADD231SDZr_Intk */ /* Table13447 */ 0x19be, /* VFNMSUB231PDZ128mk */ 0x19c1, /* VFNMSUB231PDZ128rk */ /* Table13449 */ 0x19fe, /* VFNMSUB231SDZm_Intk */ 0x1a02, /* VFNMSUB231SDZr_Intk */ /* Table13451 */ 0x257a, /* VPCONFLICTQZ128rmk */ 0x257d, /* VPCONFLICTQZ128rrk */ /* Table13453 */ 0x378e, /* VRCP28SDZmk */ 0x3794, /* VRCP28SDZrk */ /* Table13455 */ 0x38b2, /* VRSQRT28SDZmk */ 0x38b8, /* VRSQRT28SDZrk */ /* Table13457 */ 0x2cdc, /* VPMOVUSWBZ256mrk */ 0x2cde, /* VPMOVUSWBZ256rrk */ /* Table13459 */ 0x2c91, /* VPMOVUSDBZ256mrk */ 0x2c93, /* VPMOVUSDBZ256rrk */ /* Table13461 */ 0x2caf, /* VPMOVUSQBZ256mrk */ 0x2cb1, /* VPMOVUSQBZ256rrk */ /* Table13463 */ 0x2ca0, /* VPMOVUSDWZ256mrk */ 0x2ca2, /* VPMOVUSDWZ256rrk */ /* Table13465 */ 0x2ccd, /* VPMOVUSQWZ256mrk */ 0x2ccf, /* VPMOVUSQWZ256rrk */ /* Table13467 */ 0x2cbe, /* VPMOVUSQDZ256mrk */ 0x2cc0, /* VPMOVUSQDZ256rrk */ /* Table13469 */ 0x2bfe, /* VPMOVSWBZ256mrk */ 0x2c00, /* VPMOVSWBZ256rrk */ /* Table13471 */ 0x2bb3, /* VPMOVSDBZ256mrk */ 0x2bb5, /* VPMOVSDBZ256rrk */ /* Table13473 */ 0x2bd1, /* VPMOVSQBZ256mrk */ 0x2bd3, /* VPMOVSQBZ256rrk */ /* Table13475 */ 0x2bc2, /* VPMOVSDWZ256mrk */ 0x2bc4, /* VPMOVSDWZ256rrk */ /* Table13477 */ 0x2bef, /* VPMOVSQWZ256mrk */ 0x2bf1, /* VPMOVSQWZ256rrk */ /* Table13479 */ 0x2be0, /* VPMOVSQDZ256mrk */ 0x2be2, /* VPMOVSQDZ256rrk */ /* Table13481 */ 0x359c, /* VPTESTNMBZ256rmk */ 0x359e, /* VPTESTNMBZ256rrk */ /* Table13483 */ 0x35ac, /* VPTESTNMDZ256rmk */ 0x35ae, /* VPTESTNMDZ256rrk */ /* Table13485 */ 0x2cee, /* VPMOVWBZ256mrk */ 0x2cf0, /* VPMOVWBZ256rrk */ /* Table13487 */ 0x2b57, /* VPMOVDBZ256mrk */ 0x2b59, /* VPMOVDBZ256rrk */ /* Table13489 */ 0x2b86, /* VPMOVQBZ256mrk */ 0x2b88, /* VPMOVQBZ256rrk */ /* Table13491 */ 0x2b66, /* VPMOVDWZ256mrk */ 0x2b68, /* VPMOVDWZ256rrk */ /* Table13493 */ 0x2ba4, /* VPMOVQWZ256mrk */ 0x2ba6, /* VPMOVQWZ256rrk */ /* Table13495 */ 0x2b95, /* VPMOVQDZ256mrk */ 0x2b97, /* VPMOVQDZ256rrk */ /* Table13497 */ 0x3159, /* VPSHUFBZ256rmk */ 0x315c, /* VPSHUFBZ256rrk */ /* Table13499 */ 0x2988, /* VPMADDUBSWZ256rmk */ 0x298b, /* VPMADDUBSWZ256rrk */ /* Table13501 */ 0x2da3, /* VPMULHRSWZ256rmk */ 0x2da6, /* VPMULHRSWZ256rrk */ /* Table13503 */ 0x2728, /* VPERMILPSZ256rmk */ 0x272b, /* VPERMILPSZ256rrk */ /* Table13505 */ 0xeee, /* VCVTPH2PSZ256rmk */ 0xef1, /* VCVTPH2PSZ256rrk */ /* Table13507 */ 0x2fad, /* VPRORVDZ256rmk */ 0x2fb0, /* VPRORVDZ256rrk */ /* Table13509 */ 0x2f41, /* VPROLVDZ256rmk */ 0x2f44, /* VPROLVDZ256rrk */ /* Table13511 */ 0x276f, /* VPERMPSZ256rmk */ 0x2772, /* VPERMPSZ256rrk */ /* Table13513 */ 0xd41, /* VBROADCASTSSZ256mk */ 0xd44, /* VBROADCASTSSZ256rk */ /* Table13515 */ 0xce8, /* VBROADCASTF32X2Z256mk */ 0xceb, /* VBROADCASTF32X2Z256rk */ /* Table13517 */ 0xcf4, /* VBROADCASTF32X4Z256rmk */ 0x0, /* */ /* Table13519 */ 0x2036, /* VPABSBZ256rmk */ 0x2039, /* VPABSBZ256rrk */ /* Table13521 */ 0x2086, /* VPABSWZ256rmk */ 0x2089, /* VPABSWZ256rrk */ /* Table13523 */ 0x2052, /* VPABSDZ256rmk */ 0x2055, /* VPABSDZ256rrk */ /* Table13525 */ 0x2c3c, /* VPMOVSXBWZ256rmk */ 0x2c3f, /* VPMOVSXBWZ256rrk */ /* Table13527 */ 0x2c10, /* VPMOVSXBDZ256rmk */ 0x2c13, /* VPMOVSXBDZ256rrk */ /* Table13529 */ 0x2c26, /* VPMOVSXBQZ256rmk */ 0x2c29, /* VPMOVSXBQZ256rrk */ /* Table13531 */ 0x2c68, /* VPMOVSXWDZ256rmk */ 0x2c6b, /* VPMOVSXWDZ256rrk */ /* Table13533 */ 0x2c7e, /* VPMOVSXWQZ256rmk */ 0x2c81, /* VPMOVSXWQZ256rrk */ /* Table13535 */ 0x2c52, /* VPMOVSXDQZ256rmk */ 0x2c55, /* VPMOVSXDQZ256rrk */ /* Table13537 */ 0x3560, /* VPTESTMBZ256rmk */ 0x3562, /* VPTESTMBZ256rrk */ /* Table13539 */ 0x3570, /* VPTESTMDZ256rmk */ 0x3572, /* VPTESTMDZ256rrk */ /* Table13541 */ 0x20d7, /* VPACKUSDWZ256rmk */ 0x20da, /* VPACKUSDWZ256rrk */ /* Table13543 */ 0x38f6, /* VSCALEFPSZ256rmk */ 0x38f9, /* VSCALEFPSZ256rrk */ /* Table13545 */ 0x2d2c, /* VPMOVZXBWZ256rmk */ 0x2d2f, /* VPMOVZXBWZ256rrk */ /* Table13547 */ 0x2d00, /* VPMOVZXBDZ256rmk */ 0x2d03, /* VPMOVZXBDZ256rrk */ /* Table13549 */ 0x2d16, /* VPMOVZXBQZ256rmk */ 0x2d19, /* VPMOVZXBQZ256rrk */ /* Table13551 */ 0x2d58, /* VPMOVZXWDZ256rmk */ 0x2d5b, /* VPMOVZXWDZ256rrk */ /* Table13553 */ 0x2d6e, /* VPMOVZXWQZ256rmk */ 0x2d71, /* VPMOVZXWQZ256rrk */ /* Table13555 */ 0x2d42, /* VPMOVZXDQZ256rmk */ 0x2d45, /* VPMOVZXDQZ256rrk */ /* Table13557 */ 0x2619, /* VPERMDZ256rmk */ 0x261c, /* VPERMDZ256rrk */ /* Table13559 */ 0x2a88, /* VPMINSBZ256rmk */ 0x2a8b, /* VPMINSBZ256rrk */ /* Table13561 */ 0x2aa4, /* VPMINSDZ256rmk */ 0x2aa7, /* VPMINSDZ256rrk */ /* Table13563 */ 0x2b3e, /* VPMINUWZ256rmk */ 0x2b41, /* VPMINUWZ256rrk */ /* Table13565 */ 0x2b0a, /* VPMINUDZ256rmk */ 0x2b0d, /* VPMINUDZ256rrk */ /* Table13567 */ 0x29bc, /* VPMAXSBZ256rmk */ 0x29bf, /* VPMAXSBZ256rrk */ /* Table13569 */ 0x29d8, /* VPMAXSDZ256rmk */ 0x29db, /* VPMAXSDZ256rrk */ /* Table13571 */ 0x2a72, /* VPMAXUWZ256rmk */ 0x2a75, /* VPMAXUWZ256rrk */ /* Table13573 */ 0x2a3e, /* VPMAXUDZ256rmk */ 0x2a41, /* VPMAXUDZ256rrk */ /* Table13575 */ 0x2deb, /* VPMULLDZ256rmk */ 0x2dee, /* VPMULLDZ256rrk */ /* Table13577 */ 0x1abb, /* VGETEXPPSZ256mk */ 0x1abe, /* VGETEXPPSZ256rk */ /* Table13579 */ 0x2908, /* VPLZCNTDZ256rmk */ 0x290b, /* VPLZCNTDZ256rrk */ /* Table13581 */ 0x33f8, /* VPSRLVDZ256rmk */ 0x33fb, /* VPSRLVDZ256rrk */ /* Table13583 */ 0x3314, /* VPSRAVDZ256rmk */ 0x3317, /* VPSRAVDZ256rrk */ /* Table13585 */ 0x323a, /* VPSLLVDZ256rmk */ 0x323d, /* VPSLLVDZ256rrk */ /* Table13587 */ 0x375b, /* VRCP14PSZ256mk */ 0x375e, /* VRCP14PSZ256rk */ /* Table13589 */ 0x387f, /* VRSQRT14PSZ256mk */ 0x3882, /* VRSQRT14PSZ256rk */ /* Table13591 */ 0x25b9, /* VPDPBUSDZ256mk */ 0x25bc, /* VPDPBUSDZ256rk */ /* Table13593 */ 0x259e, /* VPDPBUSDSZ256mk */ 0x25a1, /* VPDPBUSDSZ256rk */ /* Table13595 */ 0x25ef, /* VPDPWSSDZ256mk */ 0x25f2, /* VPDPWSSDZ256rk */ /* Table13597 */ 0x25d4, /* VPDPWSSDSZ256mk */ 0x25d7, /* VPDPWSSDSZ256rk */ /* Table13599 */ 0x2e6d, /* VPOPCNTBZ256rmk */ 0x2e70, /* VPOPCNTBZ256rrk */ /* Table13601 */ 0x2e85, /* VPOPCNTDZ256rmk */ 0x2e88, /* VPOPCNTDZ256rrk */ /* Table13603 */ 0x2303, /* VPBROADCASTDZ256mk */ 0x2306, /* VPBROADCASTDZ256rk */ /* Table13605 */ 0xd0d, /* VBROADCASTI32X2Z256mk */ 0xd10, /* VBROADCASTI32X2Z256rk */ /* Table13607 */ 0xd19, /* VBROADCASTI32X4Z256rmk */ 0x0, /* */ /* Table13609 */ 0x284c, /* VPEXPANDBZ256rmk */ 0x284f, /* VPEXPANDBZ256rrk */ /* Table13611 */ 0x250d, /* VPCOMPRESSBZ256mrk */ 0x250f, /* VPCOMPRESSBZ256rrk */ /* Table13613 */ 0x2298, /* VPBLENDMDZ256rmk */ 0x229b, /* VPBLENDMDZ256rrk */ /* Table13615 */ 0xcc8, /* VBLENDMPSZ256rmk */ 0xccb, /* VBLENDMPSZ256rrk */ /* Table13617 */ 0x2280, /* VPBLENDMBZ256rmk */ 0x2283, /* VPBLENDMBZ256rrk */ /* Table13619 */ 0x305b, /* VPSHLDVDZ256mk */ 0x305e, /* VPSHLDVDZ256rk */ /* Table13621 */ 0x30f7, /* VPSHRDVDZ256mk */ 0x30fa, /* VPSHRDVDZ256rk */ /* Table13623 */ 0x262e, /* VPERMI2B256rmk */ 0x2631, /* VPERMI2B256rrk */ /* Table13625 */ 0x2646, /* VPERMI2D256rmk */ 0x2649, /* VPERMI2D256rrk */ /* Table13627 */ 0x267c, /* VPERMI2PS256rmk */ 0x267f, /* VPERMI2PS256rrk */ /* Table13629 */ 0x22e4, /* VPBROADCASTBZ256mk */ 0x22e7, /* VPBROADCASTBZ256rk */ /* Table13631 */ 0x2347, /* VPBROADCASTWZ256mk */ 0x234a, /* VPBROADCASTWZ256rk */ /* Table13633 */ 0x0, /* */ 0x22f3, /* VPBROADCASTBrZ256rk */ /* Table13635 */ 0x0, /* */ 0x2356, /* VPBROADCASTWrZ256rk */ /* Table13637 */ 0x0, /* */ 0x2312, /* VPBROADCASTDrZ256rk */ /* Table13639 */ 0x27aa, /* VPERMT2B256rmk */ 0x27ad, /* VPERMT2B256rrk */ /* Table13641 */ 0x27c2, /* VPERMT2D256rmk */ 0x27c5, /* VPERMT2D256rrk */ /* Table13643 */ 0x27f8, /* VPERMT2PS256rmk */ 0x27fb, /* VPERMT2PS256rrk */ /* Table13645 */ 0x12b7, /* VEXPANDPSZ256rmk */ 0x12ba, /* VEXPANDPSZ256rrk */ /* Table13647 */ 0x285e, /* VPEXPANDDZ256rmk */ 0x2861, /* VPEXPANDDZ256rrk */ /* Table13649 */ 0xdfd, /* VCOMPRESSPSZ256mrk */ 0xdff, /* VCOMPRESSPSZ256rrk */ /* Table13651 */ 0x251c, /* VPCOMPRESSDZ256mrk */ 0x251e, /* VPCOMPRESSDZ256rrk */ /* Table13653 */ 0x2608, /* VPERMBZ256rmk */ 0x260b, /* VPERMBZ256rrk */ /* Table13655 */ 0x3149, /* VPSHUFBITQMBZ256rmk */ 0x314b, /* VPSHUFBITQMBZ256rrk */ /* Table13657 */ 0x28a1, /* VPGATHERDDZ256rm */ 0x0, /* */ /* Table13659 */ 0x28ab, /* VPGATHERQDZ256rm */ 0x0, /* */ /* Table13661 */ 0x1a7b, /* VGATHERDPSZ256rm */ 0x0, /* */ /* Table13663 */ 0x1a8d, /* VGATHERQPSZ256rm */ 0x0, /* */ /* Table13665 */ 0x14d1, /* VFMADDSUB132PSZ256mk */ 0x14d4, /* VFMADDSUB132PSZ256rk */ /* Table13667 */ 0x16d9, /* VFMSUBADD132PSZ256mk */ 0x16dc, /* VFMSUBADD132PSZ256rk */ /* Table13669 */ 0x1385, /* VFMADD132PSZ256mk */ 0x1388, /* VFMADD132PSZ256rk */ /* Table13671 */ 0x15ad, /* VFMSUB132PSZ256mk */ 0x15b0, /* VFMSUB132PSZ256rk */ /* Table13673 */ 0x17d5, /* VFNMADD132PSZ256mk */ 0x17d8, /* VFNMADD132PSZ256rk */ /* Table13675 */ 0x1921, /* VFNMSUB132PSZ256mk */ 0x1924, /* VFNMSUB132PSZ256rk */ /* Table13677 */ 0x2ff9, /* VPSCATTERDDZ256mr */ 0x0, /* */ /* Table13679 */ 0x2fff, /* VPSCATTERQDZ256mr */ 0x0, /* */ /* Table13681 */ 0x391d, /* VSCATTERDPSZ256mr */ 0x0, /* */ /* Table13683 */ 0x392b, /* VSCATTERQPSZ256mr */ 0x0, /* */ /* Table13685 */ 0x1515, /* VFMADDSUB213PSZ256mk */ 0x1518, /* VFMADDSUB213PSZ256rk */ /* Table13687 */ 0x171d, /* VFMSUBADD213PSZ256mk */ 0x1720, /* VFMSUBADD213PSZ256rk */ /* Table13689 */ 0x13e9, /* VFMADD213PSZ256mk */ 0x13ec, /* VFMADD213PSZ256rk */ /* Table13691 */ 0x1611, /* VFMSUB213PSZ256mk */ 0x1614, /* VFMSUB213PSZ256rk */ /* Table13693 */ 0x1839, /* VFNMADD213PSZ256mk */ 0x183c, /* VFNMADD213PSZ256rk */ /* Table13695 */ 0x1985, /* VFNMSUB213PSZ256mk */ 0x1988, /* VFNMSUB213PSZ256rk */ /* Table13697 */ 0x1559, /* VFMADDSUB231PSZ256mk */ 0x155c, /* VFMADDSUB231PSZ256rk */ /* Table13699 */ 0x1761, /* VFMSUBADD231PSZ256mk */ 0x1764, /* VFMSUBADD231PSZ256rk */ /* Table13701 */ 0x144d, /* VFMADD231PSZ256mk */ 0x1450, /* VFMADD231PSZ256rk */ /* Table13703 */ 0x1675, /* VFMSUB231PSZ256mk */ 0x1678, /* VFMSUB231PSZ256rk */ /* Table13705 */ 0x189d, /* VFNMADD231PSZ256mk */ 0x18a0, /* VFNMADD231PSZ256rk */ /* Table13707 */ 0x19e9, /* VFNMSUB231PSZ256mk */ 0x19ec, /* VFNMSUB231PSZ256rk */ /* Table13709 */ 0x2568, /* VPCONFLICTDZ256rmk */ 0x256b, /* VPCONFLICTDZ256rrk */ /* Table13711 */ 0x1b73, /* VGF2P8MULBZ256rmk */ 0x1b76, /* VGF2P8MULBZ256rrk */ /* Table13713 */ 0x35cc, /* VPTESTNMWZ256rmk */ 0x35ce, /* VPTESTNMWZ256rrk */ /* Table13715 */ 0x35be, /* VPTESTNMQZ256rmk */ 0x35c0, /* VPTESTNMQZ256rrk */ /* Table13717 */ 0x26ea, /* VPERMILPDZ256rmk */ 0x26ed, /* VPERMILPDZ256rrk */ /* Table13719 */ 0x342e, /* VPSRLVWZ256rmk */ 0x3431, /* VPSRLVWZ256rrk */ /* Table13721 */ 0x3346, /* VPSRAVWZ256rmk */ 0x3349, /* VPSRAVWZ256rrk */ /* Table13723 */ 0x3270, /* VPSLLVWZ256rmk */ 0x3273, /* VPSLLVWZ256rrk */ /* Table13725 */ 0x2fc8, /* VPRORVQZ256rmk */ 0x2fcb, /* VPRORVQZ256rrk */ /* Table13727 */ 0x2f5c, /* VPROLVQZ256rmk */ 0x2f5f, /* VPROLVQZ256rrk */ /* Table13729 */ 0x2752, /* VPERMPDZ256rmk */ 0x2755, /* VPERMPDZ256rrk */ /* Table13731 */ 0xd2d, /* VBROADCASTSDZ256mk */ 0xd30, /* VBROADCASTSDZ256rk */ /* Table13733 */ 0xcfd, /* VBROADCASTF64X2Z128rmk */ 0x0, /* */ /* Table13735 */ 0x206f, /* VPABSQZ256rmk */ 0x2072, /* VPABSQZ256rrk */ /* Table13737 */ 0x3590, /* VPTESTMWZ256rmk */ 0x3592, /* VPTESTMWZ256rrk */ /* Table13739 */ 0x3582, /* VPTESTMQZ256rmk */ 0x3584, /* VPTESTMQZ256rrk */ /* Table13741 */ 0x2d8a, /* VPMULDQZ256rmk */ 0x2d8d, /* VPMULDQZ256rrk */ /* Table13743 */ 0x23dc, /* VPCMPEQQZ256rmk */ 0x23de, /* VPCMPEQQZ256rrk */ /* Table13745 */ 0x38d8, /* VSCALEFPDZ256rmk */ 0x38db, /* VSCALEFPDZ256rrk */ /* Table13747 */ 0x278c, /* VPERMQZ256rmk */ 0x278f, /* VPERMQZ256rrk */ /* Table13749 */ 0x242c, /* VPCMPGTQZ256rmk */ 0x242e, /* VPCMPGTQZ256rrk */ /* Table13751 */ 0x2ac1, /* VPMINSQZ256rmk */ 0x2ac4, /* VPMINSQZ256rrk */ /* Table13753 */ 0x2b27, /* VPMINUQZ256rmk */ 0x2b2a, /* VPMINUQZ256rrk */ /* Table13755 */ 0x29f5, /* VPMAXSQZ256rmk */ 0x29f8, /* VPMAXSQZ256rrk */ /* Table13757 */ 0x2a5b, /* VPMAXUQZ256rmk */ 0x2a5e, /* VPMAXUQZ256rrk */ /* Table13759 */ 0x2e08, /* VPMULLQZ256rmk */ 0x2e0b, /* VPMULLQZ256rrk */ /* Table13761 */ 0x1a9d, /* VGETEXPPDZ256mk */ 0x1aa0, /* VGETEXPPDZ256rk */ /* Table13763 */ 0x2923, /* VPLZCNTQZ256rmk */ 0x2926, /* VPLZCNTQZ256rrk */ /* Table13765 */ 0x3417, /* VPSRLVQZ256rmk */ 0x341a, /* VPSRLVQZ256rrk */ /* Table13767 */ 0x3331, /* VPSRAVQZ256rmk */ 0x3334, /* VPSRAVQZ256rrk */ /* Table13769 */ 0x3259, /* VPSLLVQZ256rmk */ 0x325c, /* VPSLLVQZ256rrk */ /* Table13771 */ 0x3740, /* VRCP14PDZ256mk */ 0x3743, /* VRCP14PDZ256rk */ /* Table13773 */ 0x3864, /* VRSQRT14PDZ256mk */ 0x3867, /* VRSQRT14PDZ256rk */ /* Table13775 */ 0x2eb5, /* VPOPCNTWZ256rmk */ 0x2eb8, /* VPOPCNTWZ256rrk */ /* Table13777 */ 0x2ea0, /* VPOPCNTQZ256rmk */ 0x2ea3, /* VPOPCNTQZ256rrk */ /* Table13779 */ 0x2328, /* VPBROADCASTQZ256mk */ 0x232b, /* VPBROADCASTQZ256rk */ /* Table13781 */ 0xd22, /* VBROADCASTI64X2Z128rmk */ 0x0, /* */ /* Table13783 */ 0x2882, /* VPEXPANDWZ256rmk */ 0x2885, /* VPEXPANDWZ256rrk */ /* Table13785 */ 0x253a, /* VPCOMPRESSWZ256mrk */ 0x253c, /* VPCOMPRESSWZ256rrk */ /* Table13787 */ 0x22b3, /* VPBLENDMQZ256rmk */ 0x22b6, /* VPBLENDMQZ256rrk */ /* Table13789 */ 0xcad, /* VBLENDMPDZ256rmk */ 0xcb0, /* VBLENDMPDZ256rrk */ /* Table13791 */ 0x22c8, /* VPBLENDMWZ256rmk */ 0x22cb, /* VPBLENDMWZ256rrk */ /* Table13793 */ 0x308b, /* VPSHLDVWZ256mk */ 0x308e, /* VPSHLDVWZ256rk */ /* Table13795 */ 0x3076, /* VPSHLDVQZ256mk */ 0x3079, /* VPSHLDVQZ256rk */ /* Table13797 */ 0x3127, /* VPSHRDVWZ256mk */ 0x312a, /* VPSHRDVWZ256rk */ /* Table13799 */ 0x3112, /* VPSHRDVQZ256mk */ 0x3115, /* VPSHRDVQZ256rk */ /* Table13801 */ 0x26ac, /* VPERMI2W256rmk */ 0x26af, /* VPERMI2W256rrk */ /* Table13803 */ 0x2697, /* VPERMI2Q256rmk */ 0x269a, /* VPERMI2Q256rrk */ /* Table13805 */ 0x2661, /* VPERMI2PD256rmk */ 0x2664, /* VPERMI2PD256rrk */ /* Table13807 */ 0x0, /* */ 0x2337, /* VPBROADCASTQrZ256rk */ /* Table13809 */ 0x2828, /* VPERMT2W256rmk */ 0x282b, /* VPERMT2W256rrk */ /* Table13811 */ 0x2813, /* VPERMT2Q256rmk */ 0x2816, /* VPERMT2Q256rrk */ /* Table13813 */ 0x27dd, /* VPERMT2PD256rmk */ 0x27e0, /* VPERMT2PD256rrk */ /* Table13815 */ 0x2e39, /* VPMULTISHIFTQBZ256rmk */ 0x2e3c, /* VPMULTISHIFTQBZ256rrk */ /* Table13817 */ 0x12a5, /* VEXPANDPDZ256rmk */ 0x12a8, /* VEXPANDPDZ256rrk */ /* Table13819 */ 0x2870, /* VPEXPANDQZ256rmk */ 0x2873, /* VPEXPANDQZ256rrk */ /* Table13821 */ 0xdee, /* VCOMPRESSPDZ256mrk */ 0xdf0, /* VCOMPRESSPDZ256rrk */ /* Table13823 */ 0x252b, /* VPCOMPRESSQZ256mrk */ 0x252d, /* VPCOMPRESSQZ256rrk */ /* Table13825 */ 0x283a, /* VPERMWZ256rmk */ 0x283d, /* VPERMWZ256rrk */ /* Table13827 */ 0x28a6, /* VPGATHERDQZ256rm */ 0x0, /* */ /* Table13829 */ 0x28b0, /* VPGATHERQQZ256rm */ 0x0, /* */ /* Table13831 */ 0x1a76, /* VGATHERDPDZ256rm */ 0x0, /* */ /* Table13833 */ 0x1a88, /* VGATHERQPDZ256rm */ 0x0, /* */ /* Table13835 */ 0x14af, /* VFMADDSUB132PDZ256mk */ 0x14b2, /* VFMADDSUB132PDZ256rk */ /* Table13837 */ 0x16b7, /* VFMSUBADD132PDZ256mk */ 0x16ba, /* VFMSUBADD132PDZ256rk */ /* Table13839 */ 0x1363, /* VFMADD132PDZ256mk */ 0x1366, /* VFMADD132PDZ256rk */ /* Table13841 */ 0x158b, /* VFMSUB132PDZ256mk */ 0x158e, /* VFMSUB132PDZ256rk */ /* Table13843 */ 0x17b3, /* VFNMADD132PDZ256mk */ 0x17b6, /* VFNMADD132PDZ256rk */ /* Table13845 */ 0x18ff, /* VFNMSUB132PDZ256mk */ 0x1902, /* VFNMSUB132PDZ256rk */ /* Table13847 */ 0x2ffc, /* VPSCATTERDQZ256mr */ 0x0, /* */ /* Table13849 */ 0x3002, /* VPSCATTERQQZ256mr */ 0x0, /* */ /* Table13851 */ 0x391a, /* VSCATTERDPDZ256mr */ 0x0, /* */ /* Table13853 */ 0x3928, /* VSCATTERQPDZ256mr */ 0x0, /* */ /* Table13855 */ 0x14f3, /* VFMADDSUB213PDZ256mk */ 0x14f6, /* VFMADDSUB213PDZ256rk */ /* Table13857 */ 0x16fb, /* VFMSUBADD213PDZ256mk */ 0x16fe, /* VFMSUBADD213PDZ256rk */ /* Table13859 */ 0x13c7, /* VFMADD213PDZ256mk */ 0x13ca, /* VFMADD213PDZ256rk */ /* Table13861 */ 0x15ef, /* VFMSUB213PDZ256mk */ 0x15f2, /* VFMSUB213PDZ256rk */ /* Table13863 */ 0x1817, /* VFNMADD213PDZ256mk */ 0x181a, /* VFNMADD213PDZ256rk */ /* Table13865 */ 0x1963, /* VFNMSUB213PDZ256mk */ 0x1966, /* VFNMSUB213PDZ256rk */ /* Table13867 */ 0x2971, /* VPMADD52LUQZ256mk */ 0x2974, /* VPMADD52LUQZ256rk */ /* Table13869 */ 0x2956, /* VPMADD52HUQZ256mk */ 0x2959, /* VPMADD52HUQZ256rk */ /* Table13871 */ 0x1537, /* VFMADDSUB231PDZ256mk */ 0x153a, /* VFMADDSUB231PDZ256rk */ /* Table13873 */ 0x173f, /* VFMSUBADD231PDZ256mk */ 0x1742, /* VFMSUBADD231PDZ256rk */ /* Table13875 */ 0x142b, /* VFMADD231PDZ256mk */ 0x142e, /* VFMADD231PDZ256rk */ /* Table13877 */ 0x1653, /* VFMSUB231PDZ256mk */ 0x1656, /* VFMSUB231PDZ256rk */ /* Table13879 */ 0x187b, /* VFNMADD231PDZ256mk */ 0x187e, /* VFNMADD231PDZ256rk */ /* Table13881 */ 0x19c7, /* VFNMSUB231PDZ256mk */ 0x19ca, /* VFNMSUB231PDZ256rk */ /* Table13883 */ 0x2583, /* VPCONFLICTQZ256rmk */ 0x2586, /* VPCONFLICTQZ256rrk */ /* Table13885 */ 0x2ce1, /* VPMOVUSWBZmrk */ 0x2ce3, /* VPMOVUSWBZrrk */ /* Table13887 */ 0x2c96, /* VPMOVUSDBZmrk */ 0x2c98, /* VPMOVUSDBZrrk */ /* Table13889 */ 0x2cb4, /* VPMOVUSQBZmrk */ 0x2cb6, /* VPMOVUSQBZrrk */ /* Table13891 */ 0x2ca5, /* VPMOVUSDWZmrk */ 0x2ca7, /* VPMOVUSDWZrrk */ /* Table13893 */ 0x2cd2, /* VPMOVUSQWZmrk */ 0x2cd4, /* VPMOVUSQWZrrk */ /* Table13895 */ 0x2cc3, /* VPMOVUSQDZmrk */ 0x2cc5, /* VPMOVUSQDZrrk */ /* Table13897 */ 0x2c03, /* VPMOVSWBZmrk */ 0x2c05, /* VPMOVSWBZrrk */ /* Table13899 */ 0x2bb8, /* VPMOVSDBZmrk */ 0x2bba, /* VPMOVSDBZrrk */ /* Table13901 */ 0x2bd6, /* VPMOVSQBZmrk */ 0x2bd8, /* VPMOVSQBZrrk */ /* Table13903 */ 0x2bc7, /* VPMOVSDWZmrk */ 0x2bc9, /* VPMOVSDWZrrk */ /* Table13905 */ 0x2bf4, /* VPMOVSQWZmrk */ 0x2bf6, /* VPMOVSQWZrrk */ /* Table13907 */ 0x2be5, /* VPMOVSQDZmrk */ 0x2be7, /* VPMOVSQDZrrk */ /* Table13909 */ 0x35a0, /* VPTESTNMBZrmk */ 0x35a2, /* VPTESTNMBZrrk */ /* Table13911 */ 0x35b2, /* VPTESTNMDZrmk */ 0x35b4, /* VPTESTNMDZrrk */ /* Table13913 */ 0x2cf3, /* VPMOVWBZmrk */ 0x2cf5, /* VPMOVWBZrrk */ /* Table13915 */ 0x2b5c, /* VPMOVDBZmrk */ 0x2b5e, /* VPMOVDBZrrk */ /* Table13917 */ 0x2b8b, /* VPMOVQBZmrk */ 0x2b8d, /* VPMOVQBZrrk */ /* Table13919 */ 0x2b6b, /* VPMOVDWZmrk */ 0x2b6d, /* VPMOVDWZrrk */ /* Table13921 */ 0x2ba9, /* VPMOVQWZmrk */ 0x2bab, /* VPMOVQWZrrk */ /* Table13923 */ 0x2b9a, /* VPMOVQDZmrk */ 0x2b9c, /* VPMOVQDZrrk */ /* Table13925 */ 0x202b, /* VP4DPWSSDrmk */ 0x0, /* */ /* Table13927 */ 0x2028, /* VP4DPWSSDSrmk */ 0x0, /* */ /* Table13929 */ 0xb4d, /* V4FMADDPSrmk */ 0x0, /* */ /* Table13931 */ 0xb53, /* V4FNMADDPSrmk */ 0x0, /* */ /* Table13933 */ 0x315f, /* VPSHUFBZrmk */ 0x3162, /* VPSHUFBZrrk */ /* Table13935 */ 0x298e, /* VPMADDUBSWZrmk */ 0x2991, /* VPMADDUBSWZrrk */ /* Table13937 */ 0x2da9, /* VPMULHRSWZrmk */ 0x2dac, /* VPMULHRSWZrrk */ /* Table13939 */ 0x273a, /* VPERMILPSZrmk */ 0x273d, /* VPERMILPSZrrk */ /* Table13941 */ 0xef4, /* VCVTPH2PSZrmk */ 0xefa, /* VCVTPH2PSZrrk */ /* Table13943 */ 0x2fb6, /* VPRORVDZrmk */ 0x2fb9, /* VPRORVDZrrk */ /* Table13945 */ 0x2f4a, /* VPROLVDZrmk */ 0x2f4d, /* VPROLVDZrrk */ /* Table13947 */ 0x2778, /* VPERMPSZrmk */ 0x277b, /* VPERMPSZrrk */ /* Table13949 */ 0xd47, /* VBROADCASTSSZmk */ 0xd4a, /* VBROADCASTSSZrk */ /* Table13951 */ 0xcee, /* VBROADCASTF32X2Zmk */ 0xcf1, /* VBROADCASTF32X2Zrk */ /* Table13953 */ 0xcf7, /* VBROADCASTF32X4rmk */ 0x0, /* */ /* Table13955 */ 0xcfa, /* VBROADCASTF32X8rmk */ 0x0, /* */ /* Table13957 */ 0x203c, /* VPABSBZrmk */ 0x203f, /* VPABSBZrrk */ /* Table13959 */ 0x208c, /* VPABSWZrmk */ 0x208f, /* VPABSWZrrk */ /* Table13961 */ 0x205b, /* VPABSDZrmk */ 0x205e, /* VPABSDZrrk */ /* Table13963 */ 0x2c42, /* VPMOVSXBWZrmk */ 0x2c45, /* VPMOVSXBWZrrk */ /* Table13965 */ 0x2c16, /* VPMOVSXBDZrmk */ 0x2c19, /* VPMOVSXBDZrrk */ /* Table13967 */ 0x2c2c, /* VPMOVSXBQZrmk */ 0x2c2f, /* VPMOVSXBQZrrk */ /* Table13969 */ 0x2c6e, /* VPMOVSXWDZrmk */ 0x2c71, /* VPMOVSXWDZrrk */ /* Table13971 */ 0x2c84, /* VPMOVSXWQZrmk */ 0x2c87, /* VPMOVSXWQZrrk */ /* Table13973 */ 0x2c58, /* VPMOVSXDQZrmk */ 0x2c5b, /* VPMOVSXDQZrrk */ /* Table13975 */ 0x3564, /* VPTESTMBZrmk */ 0x3566, /* VPTESTMBZrrk */ /* Table13977 */ 0x3576, /* VPTESTMDZrmk */ 0x3578, /* VPTESTMDZrrk */ /* Table13979 */ 0x20e0, /* VPACKUSDWZrmk */ 0x20e3, /* VPACKUSDWZrrk */ /* Table13981 */ 0x38ff, /* VSCALEFPSZrmk */ 0x3905, /* VSCALEFPSZrrk */ /* Table13983 */ 0x2d32, /* VPMOVZXBWZrmk */ 0x2d35, /* VPMOVZXBWZrrk */ /* Table13985 */ 0x2d06, /* VPMOVZXBDZrmk */ 0x2d09, /* VPMOVZXBDZrrk */ /* Table13987 */ 0x2d1c, /* VPMOVZXBQZrmk */ 0x2d1f, /* VPMOVZXBQZrrk */ /* Table13989 */ 0x2d5e, /* VPMOVZXWDZrmk */ 0x2d61, /* VPMOVZXWDZrrk */ /* Table13991 */ 0x2d74, /* VPMOVZXWQZrmk */ 0x2d77, /* VPMOVZXWQZrrk */ /* Table13993 */ 0x2d48, /* VPMOVZXDQZrmk */ 0x2d4b, /* VPMOVZXDQZrrk */ /* Table13995 */ 0x2622, /* VPERMDZrmk */ 0x2625, /* VPERMDZrrk */ /* Table13997 */ 0x2a8e, /* VPMINSBZrmk */ 0x2a91, /* VPMINSBZrrk */ /* Table13999 */ 0x2aad, /* VPMINSDZrmk */ 0x2ab0, /* VPMINSDZrrk */ /* Table14001 */ 0x2b44, /* VPMINUWZrmk */ 0x2b47, /* VPMINUWZrrk */ /* Table14003 */ 0x2b13, /* VPMINUDZrmk */ 0x2b16, /* VPMINUDZrrk */ /* Table14005 */ 0x29c2, /* VPMAXSBZrmk */ 0x29c5, /* VPMAXSBZrrk */ /* Table14007 */ 0x29e1, /* VPMAXSDZrmk */ 0x29e4, /* VPMAXSDZrrk */ /* Table14009 */ 0x2a78, /* VPMAXUWZrmk */ 0x2a7b, /* VPMAXUWZrrk */ /* Table14011 */ 0x2a47, /* VPMAXUDZrmk */ 0x2a4a, /* VPMAXUDZrrk */ /* Table14013 */ 0x2df4, /* VPMULLDZrmk */ 0x2df7, /* VPMULLDZrrk */ /* Table14015 */ 0x1ac4, /* VGETEXPPSZmk */ 0x1aca, /* VGETEXPPSZrk */ /* Table14017 */ 0x2911, /* VPLZCNTDZrmk */ 0x2914, /* VPLZCNTDZrrk */ /* Table14019 */ 0x3401, /* VPSRLVDZrmk */ 0x3404, /* VPSRLVDZrrk */ /* Table14021 */ 0x331d, /* VPSRAVDZrmk */ 0x3320, /* VPSRAVDZrrk */ /* Table14023 */ 0x3243, /* VPSLLVDZrmk */ 0x3246, /* VPSLLVDZrrk */ /* Table14025 */ 0x3764, /* VRCP14PSZmk */ 0x3767, /* VRCP14PSZrk */ /* Table14027 */ 0x3888, /* VRSQRT14PSZmk */ 0x388b, /* VRSQRT14PSZrk */ /* Table14029 */ 0x25c2, /* VPDPBUSDZmk */ 0x25c5, /* VPDPBUSDZrk */ /* Table14031 */ 0x25a7, /* VPDPBUSDSZmk */ 0x25aa, /* VPDPBUSDSZrk */ /* Table14033 */ 0x25f8, /* VPDPWSSDZmk */ 0x25fb, /* VPDPWSSDZrk */ /* Table14035 */ 0x25dd, /* VPDPWSSDSZmk */ 0x25e0, /* VPDPWSSDSZrk */ /* Table14037 */ 0x2e73, /* VPOPCNTBZrmk */ 0x2e76, /* VPOPCNTBZrrk */ /* Table14039 */ 0x2e8e, /* VPOPCNTDZrmk */ 0x2e91, /* VPOPCNTDZrrk */ /* Table14041 */ 0x2309, /* VPBROADCASTDZmk */ 0x230c, /* VPBROADCASTDZrk */ /* Table14043 */ 0xd13, /* VBROADCASTI32X2Zmk */ 0xd16, /* VBROADCASTI32X2Zrk */ /* Table14045 */ 0xd1c, /* VBROADCASTI32X4rmk */ 0x0, /* */ /* Table14047 */ 0xd1f, /* VBROADCASTI32X8rmk */ 0x0, /* */ /* Table14049 */ 0x2852, /* VPEXPANDBZrmk */ 0x2855, /* VPEXPANDBZrrk */ /* Table14051 */ 0x2512, /* VPCOMPRESSBZmrk */ 0x2514, /* VPCOMPRESSBZrrk */ /* Table14053 */ 0x22a1, /* VPBLENDMDZrmk */ 0x22a4, /* VPBLENDMDZrrk */ /* Table14055 */ 0xcd1, /* VBLENDMPSZrmk */ 0xcd4, /* VBLENDMPSZrrk */ /* Table14057 */ 0x2286, /* VPBLENDMBZrmk */ 0x2289, /* VPBLENDMBZrrk */ /* Table14059 */ 0x3064, /* VPSHLDVDZmk */ 0x3067, /* VPSHLDVDZrk */ /* Table14061 */ 0x3100, /* VPSHRDVDZmk */ 0x3103, /* VPSHRDVDZrk */ /* Table14063 */ 0x2634, /* VPERMI2Brmk */ 0x2637, /* VPERMI2Brrk */ /* Table14065 */ 0x264f, /* VPERMI2Drmk */ 0x2652, /* VPERMI2Drrk */ /* Table14067 */ 0x2685, /* VPERMI2PSrmk */ 0x2688, /* VPERMI2PSrrk */ /* Table14069 */ 0x22ea, /* VPBROADCASTBZmk */ 0x22ed, /* VPBROADCASTBZrk */ /* Table14071 */ 0x234d, /* VPBROADCASTWZmk */ 0x2350, /* VPBROADCASTWZrk */ /* Table14073 */ 0x0, /* */ 0x22f6, /* VPBROADCASTBrZrk */ /* Table14075 */ 0x0, /* */ 0x2359, /* VPBROADCASTWrZrk */ /* Table14077 */ 0x0, /* */ 0x2315, /* VPBROADCASTDrZrk */ /* Table14079 */ 0x27b0, /* VPERMT2Brmk */ 0x27b3, /* VPERMT2Brrk */ /* Table14081 */ 0x27cb, /* VPERMT2Drmk */ 0x27ce, /* VPERMT2Drrk */ /* Table14083 */ 0x2801, /* VPERMT2PSrmk */ 0x2804, /* VPERMT2PSrrk */ /* Table14085 */ 0x12bd, /* VEXPANDPSZrmk */ 0x12c0, /* VEXPANDPSZrrk */ /* Table14087 */ 0x2864, /* VPEXPANDDZrmk */ 0x2867, /* VPEXPANDDZrrk */ /* Table14089 */ 0xe02, /* VCOMPRESSPSZmrk */ 0xe04, /* VCOMPRESSPSZrrk */ /* Table14091 */ 0x2521, /* VPCOMPRESSDZmrk */ 0x2523, /* VPCOMPRESSDZrrk */ /* Table14093 */ 0x260e, /* VPERMBZrmk */ 0x2611, /* VPERMBZrrk */ /* Table14095 */ 0x314d, /* VPSHUFBITQMBZrmk */ 0x314f, /* VPSHUFBITQMBZrrk */ /* Table14097 */ 0x28a2, /* VPGATHERDDZrm */ 0x0, /* */ /* Table14099 */ 0x28ac, /* VPGATHERQDZrm */ 0x0, /* */ /* Table14101 */ 0x1a7c, /* VGATHERDPSZrm */ 0x0, /* */ /* Table14103 */ 0x1a8e, /* VGATHERQPSZrm */ 0x0, /* */ /* Table14105 */ 0x14da, /* VFMADDSUB132PSZmk */ 0x14e0, /* VFMADDSUB132PSZrk */ /* Table14107 */ 0x16e2, /* VFMSUBADD132PSZmk */ 0x16e8, /* VFMSUBADD132PSZrk */ /* Table14109 */ 0x138e, /* VFMADD132PSZmk */ 0x1394, /* VFMADD132PSZrk */ /* Table14111 */ 0x15b6, /* VFMSUB132PSZmk */ 0x15bc, /* VFMSUB132PSZrk */ /* Table14113 */ 0x17de, /* VFNMADD132PSZmk */ 0x17e4, /* VFNMADD132PSZrk */ /* Table14115 */ 0x192a, /* VFNMSUB132PSZmk */ 0x1930, /* VFNMSUB132PSZrk */ /* Table14117 */ 0x2ffa, /* VPSCATTERDDZmr */ 0x0, /* */ /* Table14119 */ 0x3000, /* VPSCATTERQDZmr */ 0x0, /* */ /* Table14121 */ 0x391e, /* VSCATTERDPSZmr */ 0x0, /* */ /* Table14123 */ 0x392c, /* VSCATTERQPSZmr */ 0x0, /* */ /* Table14125 */ 0x151e, /* VFMADDSUB213PSZmk */ 0x1524, /* VFMADDSUB213PSZrk */ /* Table14127 */ 0x1726, /* VFMSUBADD213PSZmk */ 0x172c, /* VFMSUBADD213PSZrk */ /* Table14129 */ 0x13f2, /* VFMADD213PSZmk */ 0x13f8, /* VFMADD213PSZrk */ /* Table14131 */ 0x161a, /* VFMSUB213PSZmk */ 0x1620, /* VFMSUB213PSZrk */ /* Table14133 */ 0x1842, /* VFNMADD213PSZmk */ 0x1848, /* VFNMADD213PSZrk */ /* Table14135 */ 0x198e, /* VFNMSUB213PSZmk */ 0x1994, /* VFNMSUB213PSZrk */ /* Table14137 */ 0x1562, /* VFMADDSUB231PSZmk */ 0x1568, /* VFMADDSUB231PSZrk */ /* Table14139 */ 0x176a, /* VFMSUBADD231PSZmk */ 0x1770, /* VFMSUBADD231PSZrk */ /* Table14141 */ 0x1456, /* VFMADD231PSZmk */ 0x145c, /* VFMADD231PSZrk */ /* Table14143 */ 0x167e, /* VFMSUB231PSZmk */ 0x1684, /* VFMSUB231PSZrk */ /* Table14145 */ 0x18a6, /* VFNMADD231PSZmk */ 0x18ac, /* VFNMADD231PSZrk */ /* Table14147 */ 0x19f2, /* VFNMSUB231PSZmk */ 0x19f8, /* VFNMSUB231PSZrk */ /* Table14149 */ 0x2571, /* VPCONFLICTDZrmk */ 0x2574, /* VPCONFLICTDZrrk */ /* Table14151 */ 0x0, /* */ 0x1a7f, /* VGATHERPF0DPSm */ 0x1a83, /* VGATHERPF1DPSm */ 0x0, /* */ 0x0, /* */ 0x3920, /* VSCATTERPF0DPSm */ 0x3924, /* VSCATTERPF1DPSm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table14167 */ 0x0, /* */ 0x1a81, /* VGATHERPF0QPSm */ 0x1a85, /* VGATHERPF1QPSm */ 0x0, /* */ 0x0, /* */ 0x3922, /* VSCATTERPF0QPSm */ 0x3926, /* VSCATTERPF1QPSm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table14183 */ 0x1296, /* VEXP2PSZmk */ 0x129c, /* VEXP2PSZrk */ /* Table14185 */ 0x3785, /* VRCP28PSZmk */ 0x378b, /* VRCP28PSZrk */ /* Table14187 */ 0x38a9, /* VRSQRT28PSZmk */ 0x38af, /* VRSQRT28PSZrk */ /* Table14189 */ 0x1b79, /* VGF2P8MULBZrmk */ 0x1b7c, /* VGF2P8MULBZrrk */ /* Table14191 */ 0x35d0, /* VPTESTNMWZrmk */ 0x35d2, /* VPTESTNMWZrrk */ /* Table14193 */ 0x35c4, /* VPTESTNMQZrmk */ 0x35c6, /* VPTESTNMQZrrk */ /* Table14195 */ 0x26fc, /* VPERMILPDZrmk */ 0x26ff, /* VPERMILPDZrrk */ /* Table14197 */ 0x3434, /* VPSRLVWZrmk */ 0x3437, /* VPSRLVWZrrk */ /* Table14199 */ 0x334c, /* VPSRAVWZrmk */ 0x334f, /* VPSRAVWZrrk */ /* Table14201 */ 0x3276, /* VPSLLVWZrmk */ 0x3279, /* VPSLLVWZrrk */ /* Table14203 */ 0x2fd1, /* VPRORVQZrmk */ 0x2fd4, /* VPRORVQZrrk */ /* Table14205 */ 0x2f65, /* VPROLVQZrmk */ 0x2f68, /* VPROLVQZrrk */ /* Table14207 */ 0x2764, /* VPERMPDZrmk */ 0x2767, /* VPERMPDZrrk */ /* Table14209 */ 0xd33, /* VBROADCASTSDZmk */ 0xd36, /* VBROADCASTSDZrk */ /* Table14211 */ 0xd00, /* VBROADCASTF64X2rmk */ 0x0, /* */ /* Table14213 */ 0xd03, /* VBROADCASTF64X4rmk */ 0x0, /* */ /* Table14215 */ 0x2078, /* VPABSQZrmk */ 0x207b, /* VPABSQZrrk */ /* Table14217 */ 0x3594, /* VPTESTMWZrmk */ 0x3596, /* VPTESTMWZrrk */ /* Table14219 */ 0x3588, /* VPTESTMQZrmk */ 0x358a, /* VPTESTMQZrrk */ /* Table14221 */ 0x2d93, /* VPMULDQZrmk */ 0x2d96, /* VPMULDQZrrk */ /* Table14223 */ 0x23e2, /* VPCMPEQQZrmk */ 0x23e4, /* VPCMPEQQZrrk */ /* Table14225 */ 0x38e1, /* VSCALEFPDZrmk */ 0x38e7, /* VSCALEFPDZrrk */ /* Table14227 */ 0x279e, /* VPERMQZrmk */ 0x27a1, /* VPERMQZrrk */ /* Table14229 */ 0x2432, /* VPCMPGTQZrmk */ 0x2434, /* VPCMPGTQZrrk */ /* Table14231 */ 0x2aca, /* VPMINSQZrmk */ 0x2acd, /* VPMINSQZrrk */ /* Table14233 */ 0x2b30, /* VPMINUQZrmk */ 0x2b33, /* VPMINUQZrrk */ /* Table14235 */ 0x29fe, /* VPMAXSQZrmk */ 0x2a01, /* VPMAXSQZrrk */ /* Table14237 */ 0x2a64, /* VPMAXUQZrmk */ 0x2a67, /* VPMAXUQZrrk */ /* Table14239 */ 0x2e11, /* VPMULLQZrmk */ 0x2e14, /* VPMULLQZrrk */ /* Table14241 */ 0x1aa6, /* VGETEXPPDZmk */ 0x1aac, /* VGETEXPPDZrk */ /* Table14243 */ 0x292c, /* VPLZCNTQZrmk */ 0x292f, /* VPLZCNTQZrrk */ /* Table14245 */ 0x3420, /* VPSRLVQZrmk */ 0x3423, /* VPSRLVQZrrk */ /* Table14247 */ 0x333a, /* VPSRAVQZrmk */ 0x333d, /* VPSRAVQZrrk */ /* Table14249 */ 0x3262, /* VPSLLVQZrmk */ 0x3265, /* VPSLLVQZrrk */ /* Table14251 */ 0x3749, /* VRCP14PDZmk */ 0x374c, /* VRCP14PDZrk */ /* Table14253 */ 0x386d, /* VRSQRT14PDZmk */ 0x3870, /* VRSQRT14PDZrk */ /* Table14255 */ 0x2ebb, /* VPOPCNTWZrmk */ 0x2ebe, /* VPOPCNTWZrrk */ /* Table14257 */ 0x2ea9, /* VPOPCNTQZrmk */ 0x2eac, /* VPOPCNTQZrrk */ /* Table14259 */ 0x232e, /* VPBROADCASTQZmk */ 0x2331, /* VPBROADCASTQZrk */ /* Table14261 */ 0xd25, /* VBROADCASTI64X2rmk */ 0x0, /* */ /* Table14263 */ 0xd28, /* VBROADCASTI64X4rmk */ 0x0, /* */ /* Table14265 */ 0x2888, /* VPEXPANDWZrmk */ 0x288b, /* VPEXPANDWZrrk */ /* Table14267 */ 0x253f, /* VPCOMPRESSWZmrk */ 0x2541, /* VPCOMPRESSWZrrk */ /* Table14269 */ 0x22bc, /* VPBLENDMQZrmk */ 0x22bf, /* VPBLENDMQZrrk */ /* Table14271 */ 0xcb6, /* VBLENDMPDZrmk */ 0xcb9, /* VBLENDMPDZrrk */ /* Table14273 */ 0x22ce, /* VPBLENDMWZrmk */ 0x22d1, /* VPBLENDMWZrrk */ /* Table14275 */ 0x3091, /* VPSHLDVWZmk */ 0x3094, /* VPSHLDVWZrk */ /* Table14277 */ 0x307f, /* VPSHLDVQZmk */ 0x3082, /* VPSHLDVQZrk */ /* Table14279 */ 0x312d, /* VPSHRDVWZmk */ 0x3130, /* VPSHRDVWZrk */ /* Table14281 */ 0x311b, /* VPSHRDVQZmk */ 0x311e, /* VPSHRDVQZrk */ /* Table14283 */ 0x26b2, /* VPERMI2Wrmk */ 0x26b5, /* VPERMI2Wrrk */ /* Table14285 */ 0x26a0, /* VPERMI2Qrmk */ 0x26a3, /* VPERMI2Qrrk */ /* Table14287 */ 0x266a, /* VPERMI2PDrmk */ 0x266d, /* VPERMI2PDrrk */ /* Table14289 */ 0x0, /* */ 0x233a, /* VPBROADCASTQrZrk */ /* Table14291 */ 0x282e, /* VPERMT2Wrmk */ 0x2831, /* VPERMT2Wrrk */ /* Table14293 */ 0x281c, /* VPERMT2Qrmk */ 0x281f, /* VPERMT2Qrrk */ /* Table14295 */ 0x27e6, /* VPERMT2PDrmk */ 0x27e9, /* VPERMT2PDrrk */ /* Table14297 */ 0x2e42, /* VPMULTISHIFTQBZrmk */ 0x2e45, /* VPMULTISHIFTQBZrrk */ /* Table14299 */ 0x12ab, /* VEXPANDPDZrmk */ 0x12ae, /* VEXPANDPDZrrk */ /* Table14301 */ 0x2876, /* VPEXPANDQZrmk */ 0x2879, /* VPEXPANDQZrrk */ /* Table14303 */ 0xdf3, /* VCOMPRESSPDZmrk */ 0xdf5, /* VCOMPRESSPDZrrk */ /* Table14305 */ 0x2530, /* VPCOMPRESSQZmrk */ 0x2532, /* VPCOMPRESSQZrrk */ /* Table14307 */ 0x2840, /* VPERMWZrmk */ 0x2843, /* VPERMWZrrk */ /* Table14309 */ 0x28a7, /* VPGATHERDQZrm */ 0x0, /* */ /* Table14311 */ 0x28b1, /* VPGATHERQQZrm */ 0x0, /* */ /* Table14313 */ 0x1a77, /* VGATHERDPDZrm */ 0x0, /* */ /* Table14315 */ 0x1a89, /* VGATHERQPDZrm */ 0x0, /* */ /* Table14317 */ 0x14b8, /* VFMADDSUB132PDZmk */ 0x14be, /* VFMADDSUB132PDZrk */ /* Table14319 */ 0x16c0, /* VFMSUBADD132PDZmk */ 0x16c6, /* VFMSUBADD132PDZrk */ /* Table14321 */ 0x136c, /* VFMADD132PDZmk */ 0x1372, /* VFMADD132PDZrk */ /* Table14323 */ 0x1594, /* VFMSUB132PDZmk */ 0x159a, /* VFMSUB132PDZrk */ /* Table14325 */ 0x17bc, /* VFNMADD132PDZmk */ 0x17c2, /* VFNMADD132PDZrk */ /* Table14327 */ 0x1908, /* VFNMSUB132PDZmk */ 0x190e, /* VFNMSUB132PDZrk */ /* Table14329 */ 0x2ffd, /* VPSCATTERDQZmr */ 0x0, /* */ /* Table14331 */ 0x3003, /* VPSCATTERQQZmr */ 0x0, /* */ /* Table14333 */ 0x391b, /* VSCATTERDPDZmr */ 0x0, /* */ /* Table14335 */ 0x3929, /* VSCATTERQPDZmr */ 0x0, /* */ /* Table14337 */ 0x14fc, /* VFMADDSUB213PDZmk */ 0x1502, /* VFMADDSUB213PDZrk */ /* Table14339 */ 0x1704, /* VFMSUBADD213PDZmk */ 0x170a, /* VFMSUBADD213PDZrk */ /* Table14341 */ 0x13d0, /* VFMADD213PDZmk */ 0x13d6, /* VFMADD213PDZrk */ /* Table14343 */ 0x15f8, /* VFMSUB213PDZmk */ 0x15fe, /* VFMSUB213PDZrk */ /* Table14345 */ 0x1820, /* VFNMADD213PDZmk */ 0x1826, /* VFNMADD213PDZrk */ /* Table14347 */ 0x196c, /* VFNMSUB213PDZmk */ 0x1972, /* VFNMSUB213PDZrk */ /* Table14349 */ 0x297a, /* VPMADD52LUQZmk */ 0x297d, /* VPMADD52LUQZrk */ /* Table14351 */ 0x295f, /* VPMADD52HUQZmk */ 0x2962, /* VPMADD52HUQZrk */ /* Table14353 */ 0x1540, /* VFMADDSUB231PDZmk */ 0x1546, /* VFMADDSUB231PDZrk */ /* Table14355 */ 0x1748, /* VFMSUBADD231PDZmk */ 0x174e, /* VFMSUBADD231PDZrk */ /* Table14357 */ 0x1434, /* VFMADD231PDZmk */ 0x143a, /* VFMADD231PDZrk */ /* Table14359 */ 0x165c, /* VFMSUB231PDZmk */ 0x1662, /* VFMSUB231PDZrk */ /* Table14361 */ 0x1884, /* VFNMADD231PDZmk */ 0x188a, /* VFNMADD231PDZrk */ /* Table14363 */ 0x19d0, /* VFNMSUB231PDZmk */ 0x19d6, /* VFNMSUB231PDZrk */ /* Table14365 */ 0x258c, /* VPCONFLICTQZrmk */ 0x258f, /* VPCONFLICTQZrrk */ /* Table14367 */ 0x0, /* */ 0x1a7e, /* VGATHERPF0DPDm */ 0x1a82, /* VGATHERPF1DPDm */ 0x0, /* */ 0x0, /* */ 0x391f, /* VSCATTERPF0DPDm */ 0x3923, /* VSCATTERPF1DPDm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table14383 */ 0x0, /* */ 0x1a80, /* VGATHERPF0QPDm */ 0x1a84, /* VGATHERPF1QPDm */ 0x0, /* */ 0x0, /* */ 0x3921, /* VSCATTERPF0QPDm */ 0x3925, /* VSCATTERPF1QPDm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table14399 */ 0x128a, /* VEXP2PDZmk */ 0x1290, /* VEXP2PDZrk */ /* Table14401 */ 0x3779, /* VRCP28PDZmk */ 0x377f, /* VRCP28PDZrk */ /* Table14403 */ 0x389d, /* VRSQRT28PDZmk */ 0x38a3, /* VRSQRT28PDZrk */ /* Table14405 */ 0x35a4, /* VPTESTNMDZ128rmb */ 0x0, /* */ /* Table14407 */ 0x2713, /* VPERMILPSZ128rmb */ 0x0, /* */ /* Table14409 */ 0x0, /* */ 0xef7, /* VCVTPH2PSZrrb */ /* Table14411 */ 0x2fa1, /* VPRORVDZ128rmb */ 0x0, /* */ /* Table14413 */ 0x2f35, /* VPROLVDZ128rmb */ 0x0, /* */ /* Table14415 */ 0x2046, /* VPABSDZ128rmb */ 0x0, /* */ /* Table14417 */ 0x3568, /* VPTESTMDZ128rmb */ 0x0, /* */ /* Table14419 */ 0x20cb, /* VPACKUSDWZ128rmb */ 0x0, /* */ /* Table14421 */ 0x38ea, /* VSCALEFPSZ128rmb */ 0x3902, /* VSCALEFPSZrrb */ /* Table14423 */ 0x0, /* */ 0x3914, /* VSCALEFSSZrrb_Int */ /* Table14425 */ 0x2a98, /* VPMINSDZ128rmb */ 0x0, /* */ /* Table14427 */ 0x2afe, /* VPMINUDZ128rmb */ 0x0, /* */ /* Table14429 */ 0x29cc, /* VPMAXSDZ128rmb */ 0x0, /* */ /* Table14431 */ 0x2a32, /* VPMAXUDZ128rmb */ 0x0, /* */ /* Table14433 */ 0x2ddf, /* VPMULLDZ128rmb */ 0x0, /* */ /* Table14435 */ 0x1aaf, /* VGETEXPPSZ128mb */ 0x1ac7, /* VGETEXPPSZrb */ /* Table14437 */ 0x0, /* */ 0x1ad9, /* VGETEXPSSZrb */ /* Table14439 */ 0x28fc, /* VPLZCNTDZ128rmb */ 0x0, /* */ /* Table14441 */ 0x33ec, /* VPSRLVDZ128rmb */ 0x0, /* */ /* Table14443 */ 0x3308, /* VPSRAVDZ128rmb */ 0x0, /* */ /* Table14445 */ 0x322e, /* VPSLLVDZ128rmb */ 0x0, /* */ /* Table14447 */ 0x374f, /* VRCP14PSZ128mb */ 0x0, /* */ /* Table14449 */ 0x3873, /* VRSQRT14PSZ128mb */ 0x0, /* */ /* Table14451 */ 0x25ad, /* VPDPBUSDZ128mb */ 0x0, /* */ /* Table14453 */ 0x2592, /* VPDPBUSDSZ128mb */ 0x0, /* */ /* Table14455 */ 0x25e3, /* VPDPWSSDZ128mb */ 0x0, /* */ /* Table14457 */ 0x25c8, /* VPDPWSSDSZ128mb */ 0x0, /* */ /* Table14459 */ 0x2e79, /* VPOPCNTDZ128rmb */ 0x0, /* */ /* Table14461 */ 0x228c, /* VPBLENDMDZ128rmb */ 0x0, /* */ /* Table14463 */ 0xcbc, /* VBLENDMPSZ128rmb */ 0x0, /* */ /* Table14465 */ 0x304f, /* VPSHLDVDZ128mb */ 0x0, /* */ /* Table14467 */ 0x30eb, /* VPSHRDVDZ128mb */ 0x0, /* */ /* Table14469 */ 0x263a, /* VPERMI2D128rmb */ 0x0, /* */ /* Table14471 */ 0x2670, /* VPERMI2PS128rmb */ 0x0, /* */ /* Table14473 */ 0x27b6, /* VPERMT2D128rmb */ 0x0, /* */ /* Table14475 */ 0x27ec, /* VPERMT2PS128rmb */ 0x0, /* */ /* Table14477 */ 0x14c5, /* VFMADDSUB132PSZ128mb */ 0x14dd, /* VFMADDSUB132PSZrb */ /* Table14479 */ 0x16cd, /* VFMSUBADD132PSZ128mb */ 0x16e5, /* VFMSUBADD132PSZrb */ /* Table14481 */ 0x1379, /* VFMADD132PSZ128mb */ 0x1391, /* VFMADD132PSZrb */ /* Table14483 */ 0x0, /* */ 0x13b1, /* VFMADD132SSZrb_Int */ /* Table14485 */ 0x15a1, /* VFMSUB132PSZ128mb */ 0x15b9, /* VFMSUB132PSZrb */ /* Table14487 */ 0x0, /* */ 0x15d9, /* VFMSUB132SSZrb_Int */ /* Table14489 */ 0x17c9, /* VFNMADD132PSZ128mb */ 0x17e1, /* VFNMADD132PSZrb */ /* Table14491 */ 0x0, /* */ 0x1801, /* VFNMADD132SSZrb_Int */ /* Table14493 */ 0x1915, /* VFNMSUB132PSZ128mb */ 0x192d, /* VFNMSUB132PSZrb */ /* Table14495 */ 0x0, /* */ 0x194d, /* VFNMSUB132SSZrb_Int */ /* Table14497 */ 0x1509, /* VFMADDSUB213PSZ128mb */ 0x1521, /* VFMADDSUB213PSZrb */ /* Table14499 */ 0x1711, /* VFMSUBADD213PSZ128mb */ 0x1729, /* VFMSUBADD213PSZrb */ /* Table14501 */ 0x13dd, /* VFMADD213PSZ128mb */ 0x13f5, /* VFMADD213PSZrb */ /* Table14503 */ 0x0, /* */ 0x1415, /* VFMADD213SSZrb_Int */ /* Table14505 */ 0x1605, /* VFMSUB213PSZ128mb */ 0x161d, /* VFMSUB213PSZrb */ /* Table14507 */ 0x0, /* */ 0x163d, /* VFMSUB213SSZrb_Int */ /* Table14509 */ 0x182d, /* VFNMADD213PSZ128mb */ 0x1845, /* VFNMADD213PSZrb */ /* Table14511 */ 0x0, /* */ 0x1865, /* VFNMADD213SSZrb_Int */ /* Table14513 */ 0x1979, /* VFNMSUB213PSZ128mb */ 0x1991, /* VFNMSUB213PSZrb */ /* Table14515 */ 0x0, /* */ 0x19b1, /* VFNMSUB213SSZrb_Int */ /* Table14517 */ 0x154d, /* VFMADDSUB231PSZ128mb */ 0x1565, /* VFMADDSUB231PSZrb */ /* Table14519 */ 0x1755, /* VFMSUBADD231PSZ128mb */ 0x176d, /* VFMSUBADD231PSZrb */ /* Table14521 */ 0x1441, /* VFMADD231PSZ128mb */ 0x1459, /* VFMADD231PSZrb */ /* Table14523 */ 0x0, /* */ 0x1479, /* VFMADD231SSZrb_Int */ /* Table14525 */ 0x1669, /* VFMSUB231PSZ128mb */ 0x1681, /* VFMSUB231PSZrb */ /* Table14527 */ 0x0, /* */ 0x16a1, /* VFMSUB231SSZrb_Int */ /* Table14529 */ 0x1891, /* VFNMADD231PSZ128mb */ 0x18a9, /* VFNMADD231PSZrb */ /* Table14531 */ 0x0, /* */ 0x18c9, /* VFNMADD231SSZrb_Int */ /* Table14533 */ 0x19dd, /* VFNMSUB231PSZ128mb */ 0x19f5, /* VFNMSUB231PSZrb */ /* Table14535 */ 0x0, /* */ 0x1a15, /* VFNMSUB231SSZrb_Int */ /* Table14537 */ 0x255c, /* VPCONFLICTDZ128rmb */ 0x0, /* */ /* Table14539 */ 0x0, /* */ 0x1299, /* VEXP2PSZrb */ /* Table14541 */ 0x0, /* */ 0x3788, /* VRCP28PSZrb */ /* Table14543 */ 0x0, /* */ 0x379a, /* VRCP28SSZrb */ /* Table14545 */ 0x0, /* */ 0x38ac, /* VRSQRT28PSZrb */ /* Table14547 */ 0x0, /* */ 0x38be, /* VRSQRT28SSZrb */ /* Table14549 */ 0x35b6, /* VPTESTNMQZ128rmb */ 0x0, /* */ /* Table14551 */ 0x26d5, /* VPERMILPDZ128rmb */ 0x0, /* */ /* Table14553 */ 0x2fbc, /* VPRORVQZ128rmb */ 0x0, /* */ /* Table14555 */ 0x2f50, /* VPROLVQZ128rmb */ 0x0, /* */ /* Table14557 */ 0x2063, /* VPABSQZ128rmb */ 0x0, /* */ /* Table14559 */ 0x357a, /* VPTESTMQZ128rmb */ 0x0, /* */ /* Table14561 */ 0x2d7e, /* VPMULDQZ128rmb */ 0x0, /* */ /* Table14563 */ 0x23d4, /* VPCMPEQQZ128rmb */ 0x0, /* */ /* Table14565 */ 0x38cc, /* VSCALEFPDZ128rmb */ 0x38e4, /* VSCALEFPDZrrb */ /* Table14567 */ 0x0, /* */ 0x390b, /* VSCALEFSDZrrb_Int */ /* Table14569 */ 0x2424, /* VPCMPGTQZ128rmb */ 0x0, /* */ /* Table14571 */ 0x2ab5, /* VPMINSQZ128rmb */ 0x0, /* */ /* Table14573 */ 0x2b1b, /* VPMINUQZ128rmb */ 0x0, /* */ /* Table14575 */ 0x29e9, /* VPMAXSQZ128rmb */ 0x0, /* */ /* Table14577 */ 0x2a4f, /* VPMAXUQZ128rmb */ 0x0, /* */ /* Table14579 */ 0x2dfc, /* VPMULLQZ128rmb */ 0x0, /* */ /* Table14581 */ 0x1a91, /* VGETEXPPDZ128mb */ 0x1aa9, /* VGETEXPPDZrb */ /* Table14583 */ 0x0, /* */ 0x1ad0, /* VGETEXPSDZrb */ /* Table14585 */ 0x2917, /* VPLZCNTQZ128rmb */ 0x0, /* */ /* Table14587 */ 0x340b, /* VPSRLVQZ128rmb */ 0x0, /* */ /* Table14589 */ 0x3325, /* VPSRAVQZ128rmb */ 0x0, /* */ /* Table14591 */ 0x324d, /* VPSLLVQZ128rmb */ 0x0, /* */ /* Table14593 */ 0x3734, /* VRCP14PDZ128mb */ 0x0, /* */ /* Table14595 */ 0x3858, /* VRSQRT14PDZ128mb */ 0x0, /* */ /* Table14597 */ 0x2e94, /* VPOPCNTQZ128rmb */ 0x0, /* */ /* Table14599 */ 0x22a7, /* VPBLENDMQZ128rmb */ 0x0, /* */ /* Table14601 */ 0xca1, /* VBLENDMPDZ128rmb */ 0x0, /* */ /* Table14603 */ 0x306a, /* VPSHLDVQZ128mb */ 0x0, /* */ /* Table14605 */ 0x3106, /* VPSHRDVQZ128mb */ 0x0, /* */ /* Table14607 */ 0x268b, /* VPERMI2Q128rmb */ 0x0, /* */ /* Table14609 */ 0x2655, /* VPERMI2PD128rmb */ 0x0, /* */ /* Table14611 */ 0x2807, /* VPERMT2Q128rmb */ 0x0, /* */ /* Table14613 */ 0x27d1, /* VPERMT2PD128rmb */ 0x0, /* */ /* Table14615 */ 0x2e2d, /* VPMULTISHIFTQBZ128rmb */ 0x0, /* */ /* Table14617 */ 0x14a3, /* VFMADDSUB132PDZ128mb */ 0x14bb, /* VFMADDSUB132PDZrb */ /* Table14619 */ 0x16ab, /* VFMSUBADD132PDZ128mb */ 0x16c3, /* VFMSUBADD132PDZrb */ /* Table14621 */ 0x1357, /* VFMADD132PDZ128mb */ 0x136f, /* VFMADD132PDZrb */ /* Table14623 */ 0x0, /* */ 0x13a1, /* VFMADD132SDZrb_Int */ /* Table14625 */ 0x157f, /* VFMSUB132PDZ128mb */ 0x1597, /* VFMSUB132PDZrb */ /* Table14627 */ 0x0, /* */ 0x15c9, /* VFMSUB132SDZrb_Int */ /* Table14629 */ 0x17a7, /* VFNMADD132PDZ128mb */ 0x17bf, /* VFNMADD132PDZrb */ /* Table14631 */ 0x0, /* */ 0x17f1, /* VFNMADD132SDZrb_Int */ /* Table14633 */ 0x18f3, /* VFNMSUB132PDZ128mb */ 0x190b, /* VFNMSUB132PDZrb */ /* Table14635 */ 0x0, /* */ 0x193d, /* VFNMSUB132SDZrb_Int */ /* Table14637 */ 0x14e7, /* VFMADDSUB213PDZ128mb */ 0x14ff, /* VFMADDSUB213PDZrb */ /* Table14639 */ 0x16ef, /* VFMSUBADD213PDZ128mb */ 0x1707, /* VFMSUBADD213PDZrb */ /* Table14641 */ 0x13bb, /* VFMADD213PDZ128mb */ 0x13d3, /* VFMADD213PDZrb */ /* Table14643 */ 0x0, /* */ 0x1405, /* VFMADD213SDZrb_Int */ /* Table14645 */ 0x15e3, /* VFMSUB213PDZ128mb */ 0x15fb, /* VFMSUB213PDZrb */ /* Table14647 */ 0x0, /* */ 0x162d, /* VFMSUB213SDZrb_Int */ /* Table14649 */ 0x180b, /* VFNMADD213PDZ128mb */ 0x1823, /* VFNMADD213PDZrb */ /* Table14651 */ 0x0, /* */ 0x1855, /* VFNMADD213SDZrb_Int */ /* Table14653 */ 0x1957, /* VFNMSUB213PDZ128mb */ 0x196f, /* VFNMSUB213PDZrb */ /* Table14655 */ 0x0, /* */ 0x19a1, /* VFNMSUB213SDZrb_Int */ /* Table14657 */ 0x2965, /* VPMADD52LUQZ128mb */ 0x0, /* */ /* Table14659 */ 0x294a, /* VPMADD52HUQZ128mb */ 0x0, /* */ /* Table14661 */ 0x152b, /* VFMADDSUB231PDZ128mb */ 0x1543, /* VFMADDSUB231PDZrb */ /* Table14663 */ 0x1733, /* VFMSUBADD231PDZ128mb */ 0x174b, /* VFMSUBADD231PDZrb */ /* Table14665 */ 0x141f, /* VFMADD231PDZ128mb */ 0x1437, /* VFMADD231PDZrb */ /* Table14667 */ 0x0, /* */ 0x1469, /* VFMADD231SDZrb_Int */ /* Table14669 */ 0x1647, /* VFMSUB231PDZ128mb */ 0x165f, /* VFMSUB231PDZrb */ /* Table14671 */ 0x0, /* */ 0x1691, /* VFMSUB231SDZrb_Int */ /* Table14673 */ 0x186f, /* VFNMADD231PDZ128mb */ 0x1887, /* VFNMADD231PDZrb */ /* Table14675 */ 0x0, /* */ 0x18b9, /* VFNMADD231SDZrb_Int */ /* Table14677 */ 0x19bb, /* VFNMSUB231PDZ128mb */ 0x19d3, /* VFNMSUB231PDZrb */ /* Table14679 */ 0x0, /* */ 0x1a05, /* VFNMSUB231SDZrb_Int */ /* Table14681 */ 0x2577, /* VPCONFLICTQZ128rmb */ 0x0, /* */ /* Table14683 */ 0x0, /* */ 0x128d, /* VEXP2PDZrb */ /* Table14685 */ 0x0, /* */ 0x377c, /* VRCP28PDZrb */ /* Table14687 */ 0x0, /* */ 0x3791, /* VRCP28SDZrb */ /* Table14689 */ 0x0, /* */ 0x38a0, /* VRSQRT28PDZrb */ /* Table14691 */ 0x0, /* */ 0x38b5, /* VRSQRT28SDZrb */ /* Table14693 */ 0x35aa, /* VPTESTNMDZ256rmb */ 0x0, /* */ /* Table14695 */ 0x2725, /* VPERMILPSZ256rmb */ 0x0, /* */ /* Table14697 */ 0x2faa, /* VPRORVDZ256rmb */ 0x0, /* */ /* Table14699 */ 0x2f3e, /* VPROLVDZ256rmb */ 0x0, /* */ /* Table14701 */ 0x276c, /* VPERMPSZ256rmb */ 0x0, /* */ /* Table14703 */ 0x204f, /* VPABSDZ256rmb */ 0x0, /* */ /* Table14705 */ 0x356e, /* VPTESTMDZ256rmb */ 0x0, /* */ /* Table14707 */ 0x20d4, /* VPACKUSDWZ256rmb */ 0x0, /* */ /* Table14709 */ 0x38f3, /* VSCALEFPSZ256rmb */ 0x3902, /* VSCALEFPSZrrb */ /* Table14711 */ 0x2616, /* VPERMDZ256rmb */ 0x0, /* */ /* Table14713 */ 0x2aa1, /* VPMINSDZ256rmb */ 0x0, /* */ /* Table14715 */ 0x2b07, /* VPMINUDZ256rmb */ 0x0, /* */ /* Table14717 */ 0x29d5, /* VPMAXSDZ256rmb */ 0x0, /* */ /* Table14719 */ 0x2a3b, /* VPMAXUDZ256rmb */ 0x0, /* */ /* Table14721 */ 0x2de8, /* VPMULLDZ256rmb */ 0x0, /* */ /* Table14723 */ 0x1ab8, /* VGETEXPPSZ256mb */ 0x1ac7, /* VGETEXPPSZrb */ /* Table14725 */ 0x2905, /* VPLZCNTDZ256rmb */ 0x0, /* */ /* Table14727 */ 0x33f5, /* VPSRLVDZ256rmb */ 0x0, /* */ /* Table14729 */ 0x3311, /* VPSRAVDZ256rmb */ 0x0, /* */ /* Table14731 */ 0x3237, /* VPSLLVDZ256rmb */ 0x0, /* */ /* Table14733 */ 0x3758, /* VRCP14PSZ256mb */ 0x0, /* */ /* Table14735 */ 0x387c, /* VRSQRT14PSZ256mb */ 0x0, /* */ /* Table14737 */ 0x25b6, /* VPDPBUSDZ256mb */ 0x0, /* */ /* Table14739 */ 0x259b, /* VPDPBUSDSZ256mb */ 0x0, /* */ /* Table14741 */ 0x25ec, /* VPDPWSSDZ256mb */ 0x0, /* */ /* Table14743 */ 0x25d1, /* VPDPWSSDSZ256mb */ 0x0, /* */ /* Table14745 */ 0x2e82, /* VPOPCNTDZ256rmb */ 0x0, /* */ /* Table14747 */ 0x2295, /* VPBLENDMDZ256rmb */ 0x0, /* */ /* Table14749 */ 0xcc5, /* VBLENDMPSZ256rmb */ 0x0, /* */ /* Table14751 */ 0x3058, /* VPSHLDVDZ256mb */ 0x0, /* */ /* Table14753 */ 0x30f4, /* VPSHRDVDZ256mb */ 0x0, /* */ /* Table14755 */ 0x2643, /* VPERMI2D256rmb */ 0x0, /* */ /* Table14757 */ 0x2679, /* VPERMI2PS256rmb */ 0x0, /* */ /* Table14759 */ 0x27bf, /* VPERMT2D256rmb */ 0x0, /* */ /* Table14761 */ 0x27f5, /* VPERMT2PS256rmb */ 0x0, /* */ /* Table14763 */ 0x14ce, /* VFMADDSUB132PSZ256mb */ 0x14dd, /* VFMADDSUB132PSZrb */ /* Table14765 */ 0x16d6, /* VFMSUBADD132PSZ256mb */ 0x16e5, /* VFMSUBADD132PSZrb */ /* Table14767 */ 0x1382, /* VFMADD132PSZ256mb */ 0x1391, /* VFMADD132PSZrb */ /* Table14769 */ 0x15aa, /* VFMSUB132PSZ256mb */ 0x15b9, /* VFMSUB132PSZrb */ /* Table14771 */ 0x17d2, /* VFNMADD132PSZ256mb */ 0x17e1, /* VFNMADD132PSZrb */ /* Table14773 */ 0x191e, /* VFNMSUB132PSZ256mb */ 0x192d, /* VFNMSUB132PSZrb */ /* Table14775 */ 0x1512, /* VFMADDSUB213PSZ256mb */ 0x1521, /* VFMADDSUB213PSZrb */ /* Table14777 */ 0x171a, /* VFMSUBADD213PSZ256mb */ 0x1729, /* VFMSUBADD213PSZrb */ /* Table14779 */ 0x13e6, /* VFMADD213PSZ256mb */ 0x13f5, /* VFMADD213PSZrb */ /* Table14781 */ 0x160e, /* VFMSUB213PSZ256mb */ 0x161d, /* VFMSUB213PSZrb */ /* Table14783 */ 0x1836, /* VFNMADD213PSZ256mb */ 0x1845, /* VFNMADD213PSZrb */ /* Table14785 */ 0x1982, /* VFNMSUB213PSZ256mb */ 0x1991, /* VFNMSUB213PSZrb */ /* Table14787 */ 0x1556, /* VFMADDSUB231PSZ256mb */ 0x1565, /* VFMADDSUB231PSZrb */ /* Table14789 */ 0x175e, /* VFMSUBADD231PSZ256mb */ 0x176d, /* VFMSUBADD231PSZrb */ /* Table14791 */ 0x144a, /* VFMADD231PSZ256mb */ 0x1459, /* VFMADD231PSZrb */ /* Table14793 */ 0x1672, /* VFMSUB231PSZ256mb */ 0x1681, /* VFMSUB231PSZrb */ /* Table14795 */ 0x189a, /* VFNMADD231PSZ256mb */ 0x18a9, /* VFNMADD231PSZrb */ /* Table14797 */ 0x19e6, /* VFNMSUB231PSZ256mb */ 0x19f5, /* VFNMSUB231PSZrb */ /* Table14799 */ 0x2565, /* VPCONFLICTDZ256rmb */ 0x0, /* */ /* Table14801 */ 0x35bc, /* VPTESTNMQZ256rmb */ 0x0, /* */ /* Table14803 */ 0x26e7, /* VPERMILPDZ256rmb */ 0x0, /* */ /* Table14805 */ 0x2fc5, /* VPRORVQZ256rmb */ 0x0, /* */ /* Table14807 */ 0x2f59, /* VPROLVQZ256rmb */ 0x0, /* */ /* Table14809 */ 0x274f, /* VPERMPDZ256rmb */ 0x0, /* */ /* Table14811 */ 0x206c, /* VPABSQZ256rmb */ 0x0, /* */ /* Table14813 */ 0x3580, /* VPTESTMQZ256rmb */ 0x0, /* */ /* Table14815 */ 0x2d87, /* VPMULDQZ256rmb */ 0x0, /* */ /* Table14817 */ 0x23da, /* VPCMPEQQZ256rmb */ 0x0, /* */ /* Table14819 */ 0x38d5, /* VSCALEFPDZ256rmb */ 0x38e4, /* VSCALEFPDZrrb */ /* Table14821 */ 0x2789, /* VPERMQZ256rmb */ 0x0, /* */ /* Table14823 */ 0x242a, /* VPCMPGTQZ256rmb */ 0x0, /* */ /* Table14825 */ 0x2abe, /* VPMINSQZ256rmb */ 0x0, /* */ /* Table14827 */ 0x2b24, /* VPMINUQZ256rmb */ 0x0, /* */ /* Table14829 */ 0x29f2, /* VPMAXSQZ256rmb */ 0x0, /* */ /* Table14831 */ 0x2a58, /* VPMAXUQZ256rmb */ 0x0, /* */ /* Table14833 */ 0x2e05, /* VPMULLQZ256rmb */ 0x0, /* */ /* Table14835 */ 0x1a9a, /* VGETEXPPDZ256mb */ 0x1aa9, /* VGETEXPPDZrb */ /* Table14837 */ 0x2920, /* VPLZCNTQZ256rmb */ 0x0, /* */ /* Table14839 */ 0x3414, /* VPSRLVQZ256rmb */ 0x0, /* */ /* Table14841 */ 0x332e, /* VPSRAVQZ256rmb */ 0x0, /* */ /* Table14843 */ 0x3256, /* VPSLLVQZ256rmb */ 0x0, /* */ /* Table14845 */ 0x373d, /* VRCP14PDZ256mb */ 0x0, /* */ /* Table14847 */ 0x3861, /* VRSQRT14PDZ256mb */ 0x0, /* */ /* Table14849 */ 0x2e9d, /* VPOPCNTQZ256rmb */ 0x0, /* */ /* Table14851 */ 0x22b0, /* VPBLENDMQZ256rmb */ 0x0, /* */ /* Table14853 */ 0xcaa, /* VBLENDMPDZ256rmb */ 0x0, /* */ /* Table14855 */ 0x3073, /* VPSHLDVQZ256mb */ 0x0, /* */ /* Table14857 */ 0x310f, /* VPSHRDVQZ256mb */ 0x0, /* */ /* Table14859 */ 0x2694, /* VPERMI2Q256rmb */ 0x0, /* */ /* Table14861 */ 0x265e, /* VPERMI2PD256rmb */ 0x0, /* */ /* Table14863 */ 0x2810, /* VPERMT2Q256rmb */ 0x0, /* */ /* Table14865 */ 0x27da, /* VPERMT2PD256rmb */ 0x0, /* */ /* Table14867 */ 0x2e36, /* VPMULTISHIFTQBZ256rmb */ 0x0, /* */ /* Table14869 */ 0x14ac, /* VFMADDSUB132PDZ256mb */ 0x14bb, /* VFMADDSUB132PDZrb */ /* Table14871 */ 0x16b4, /* VFMSUBADD132PDZ256mb */ 0x16c3, /* VFMSUBADD132PDZrb */ /* Table14873 */ 0x1360, /* VFMADD132PDZ256mb */ 0x136f, /* VFMADD132PDZrb */ /* Table14875 */ 0x1588, /* VFMSUB132PDZ256mb */ 0x1597, /* VFMSUB132PDZrb */ /* Table14877 */ 0x17b0, /* VFNMADD132PDZ256mb */ 0x17bf, /* VFNMADD132PDZrb */ /* Table14879 */ 0x18fc, /* VFNMSUB132PDZ256mb */ 0x190b, /* VFNMSUB132PDZrb */ /* Table14881 */ 0x14f0, /* VFMADDSUB213PDZ256mb */ 0x14ff, /* VFMADDSUB213PDZrb */ /* Table14883 */ 0x16f8, /* VFMSUBADD213PDZ256mb */ 0x1707, /* VFMSUBADD213PDZrb */ /* Table14885 */ 0x13c4, /* VFMADD213PDZ256mb */ 0x13d3, /* VFMADD213PDZrb */ /* Table14887 */ 0x15ec, /* VFMSUB213PDZ256mb */ 0x15fb, /* VFMSUB213PDZrb */ /* Table14889 */ 0x1814, /* VFNMADD213PDZ256mb */ 0x1823, /* VFNMADD213PDZrb */ /* Table14891 */ 0x1960, /* VFNMSUB213PDZ256mb */ 0x196f, /* VFNMSUB213PDZrb */ /* Table14893 */ 0x296e, /* VPMADD52LUQZ256mb */ 0x0, /* */ /* Table14895 */ 0x2953, /* VPMADD52HUQZ256mb */ 0x0, /* */ /* Table14897 */ 0x1534, /* VFMADDSUB231PDZ256mb */ 0x1543, /* VFMADDSUB231PDZrb */ /* Table14899 */ 0x173c, /* VFMSUBADD231PDZ256mb */ 0x174b, /* VFMSUBADD231PDZrb */ /* Table14901 */ 0x1428, /* VFMADD231PDZ256mb */ 0x1437, /* VFMADD231PDZrb */ /* Table14903 */ 0x1650, /* VFMSUB231PDZ256mb */ 0x165f, /* VFMSUB231PDZrb */ /* Table14905 */ 0x1878, /* VFNMADD231PDZ256mb */ 0x1887, /* VFNMADD231PDZrb */ /* Table14907 */ 0x19c4, /* VFNMSUB231PDZ256mb */ 0x19d3, /* VFNMSUB231PDZrb */ /* Table14909 */ 0x2580, /* VPCONFLICTQZ256rmb */ 0x0, /* */ /* Table14911 */ 0x35b0, /* VPTESTNMDZrmb */ 0x0, /* */ /* Table14913 */ 0x2737, /* VPERMILPSZrmb */ 0x0, /* */ /* Table14915 */ 0x2fb3, /* VPRORVDZrmb */ 0x0, /* */ /* Table14917 */ 0x2f47, /* VPROLVDZrmb */ 0x0, /* */ /* Table14919 */ 0x2775, /* VPERMPSZrmb */ 0x0, /* */ /* Table14921 */ 0x2058, /* VPABSDZrmb */ 0x0, /* */ /* Table14923 */ 0x3574, /* VPTESTMDZrmb */ 0x0, /* */ /* Table14925 */ 0x20dd, /* VPACKUSDWZrmb */ 0x0, /* */ /* Table14927 */ 0x38fc, /* VSCALEFPSZrmb */ 0x3902, /* VSCALEFPSZrrb */ /* Table14929 */ 0x261f, /* VPERMDZrmb */ 0x0, /* */ /* Table14931 */ 0x2aaa, /* VPMINSDZrmb */ 0x0, /* */ /* Table14933 */ 0x2b10, /* VPMINUDZrmb */ 0x0, /* */ /* Table14935 */ 0x29de, /* VPMAXSDZrmb */ 0x0, /* */ /* Table14937 */ 0x2a44, /* VPMAXUDZrmb */ 0x0, /* */ /* Table14939 */ 0x2df1, /* VPMULLDZrmb */ 0x0, /* */ /* Table14941 */ 0x1ac1, /* VGETEXPPSZmb */ 0x1ac7, /* VGETEXPPSZrb */ /* Table14943 */ 0x290e, /* VPLZCNTDZrmb */ 0x0, /* */ /* Table14945 */ 0x33fe, /* VPSRLVDZrmb */ 0x0, /* */ /* Table14947 */ 0x331a, /* VPSRAVDZrmb */ 0x0, /* */ /* Table14949 */ 0x3240, /* VPSLLVDZrmb */ 0x0, /* */ /* Table14951 */ 0x3761, /* VRCP14PSZmb */ 0x0, /* */ /* Table14953 */ 0x3885, /* VRSQRT14PSZmb */ 0x0, /* */ /* Table14955 */ 0x25bf, /* VPDPBUSDZmb */ 0x0, /* */ /* Table14957 */ 0x25a4, /* VPDPBUSDSZmb */ 0x0, /* */ /* Table14959 */ 0x25f5, /* VPDPWSSDZmb */ 0x0, /* */ /* Table14961 */ 0x25da, /* VPDPWSSDSZmb */ 0x0, /* */ /* Table14963 */ 0x2e8b, /* VPOPCNTDZrmb */ 0x0, /* */ /* Table14965 */ 0x229e, /* VPBLENDMDZrmb */ 0x0, /* */ /* Table14967 */ 0xcce, /* VBLENDMPSZrmb */ 0x0, /* */ /* Table14969 */ 0x3061, /* VPSHLDVDZmb */ 0x0, /* */ /* Table14971 */ 0x30fd, /* VPSHRDVDZmb */ 0x0, /* */ /* Table14973 */ 0x264c, /* VPERMI2Drmb */ 0x0, /* */ /* Table14975 */ 0x2682, /* VPERMI2PSrmb */ 0x0, /* */ /* Table14977 */ 0x27c8, /* VPERMT2Drmb */ 0x0, /* */ /* Table14979 */ 0x27fe, /* VPERMT2PSrmb */ 0x0, /* */ /* Table14981 */ 0x14d7, /* VFMADDSUB132PSZmb */ 0x14dd, /* VFMADDSUB132PSZrb */ /* Table14983 */ 0x16df, /* VFMSUBADD132PSZmb */ 0x16e5, /* VFMSUBADD132PSZrb */ /* Table14985 */ 0x138b, /* VFMADD132PSZmb */ 0x1391, /* VFMADD132PSZrb */ /* Table14987 */ 0x15b3, /* VFMSUB132PSZmb */ 0x15b9, /* VFMSUB132PSZrb */ /* Table14989 */ 0x17db, /* VFNMADD132PSZmb */ 0x17e1, /* VFNMADD132PSZrb */ /* Table14991 */ 0x1927, /* VFNMSUB132PSZmb */ 0x192d, /* VFNMSUB132PSZrb */ /* Table14993 */ 0x151b, /* VFMADDSUB213PSZmb */ 0x1521, /* VFMADDSUB213PSZrb */ /* Table14995 */ 0x1723, /* VFMSUBADD213PSZmb */ 0x1729, /* VFMSUBADD213PSZrb */ /* Table14997 */ 0x13ef, /* VFMADD213PSZmb */ 0x13f5, /* VFMADD213PSZrb */ /* Table14999 */ 0x1617, /* VFMSUB213PSZmb */ 0x161d, /* VFMSUB213PSZrb */ /* Table15001 */ 0x183f, /* VFNMADD213PSZmb */ 0x1845, /* VFNMADD213PSZrb */ /* Table15003 */ 0x198b, /* VFNMSUB213PSZmb */ 0x1991, /* VFNMSUB213PSZrb */ /* Table15005 */ 0x155f, /* VFMADDSUB231PSZmb */ 0x1565, /* VFMADDSUB231PSZrb */ /* Table15007 */ 0x1767, /* VFMSUBADD231PSZmb */ 0x176d, /* VFMSUBADD231PSZrb */ /* Table15009 */ 0x1453, /* VFMADD231PSZmb */ 0x1459, /* VFMADD231PSZrb */ /* Table15011 */ 0x167b, /* VFMSUB231PSZmb */ 0x1681, /* VFMSUB231PSZrb */ /* Table15013 */ 0x18a3, /* VFNMADD231PSZmb */ 0x18a9, /* VFNMADD231PSZrb */ /* Table15015 */ 0x19ef, /* VFNMSUB231PSZmb */ 0x19f5, /* VFNMSUB231PSZrb */ /* Table15017 */ 0x256e, /* VPCONFLICTDZrmb */ 0x0, /* */ /* Table15019 */ 0x1293, /* VEXP2PSZmb */ 0x1299, /* VEXP2PSZrb */ /* Table15021 */ 0x3782, /* VRCP28PSZmb */ 0x3788, /* VRCP28PSZrb */ /* Table15023 */ 0x38a6, /* VRSQRT28PSZmb */ 0x38ac, /* VRSQRT28PSZrb */ /* Table15025 */ 0x35c2, /* VPTESTNMQZrmb */ 0x0, /* */ /* Table15027 */ 0x26f9, /* VPERMILPDZrmb */ 0x0, /* */ /* Table15029 */ 0x2fce, /* VPRORVQZrmb */ 0x0, /* */ /* Table15031 */ 0x2f62, /* VPROLVQZrmb */ 0x0, /* */ /* Table15033 */ 0x2761, /* VPERMPDZrmb */ 0x0, /* */ /* Table15035 */ 0x2075, /* VPABSQZrmb */ 0x0, /* */ /* Table15037 */ 0x3586, /* VPTESTMQZrmb */ 0x0, /* */ /* Table15039 */ 0x2d90, /* VPMULDQZrmb */ 0x0, /* */ /* Table15041 */ 0x23e0, /* VPCMPEQQZrmb */ 0x0, /* */ /* Table15043 */ 0x38de, /* VSCALEFPDZrmb */ 0x38e4, /* VSCALEFPDZrrb */ /* Table15045 */ 0x279b, /* VPERMQZrmb */ 0x0, /* */ /* Table15047 */ 0x2430, /* VPCMPGTQZrmb */ 0x0, /* */ /* Table15049 */ 0x2ac7, /* VPMINSQZrmb */ 0x0, /* */ /* Table15051 */ 0x2b2d, /* VPMINUQZrmb */ 0x0, /* */ /* Table15053 */ 0x29fb, /* VPMAXSQZrmb */ 0x0, /* */ /* Table15055 */ 0x2a61, /* VPMAXUQZrmb */ 0x0, /* */ /* Table15057 */ 0x2e0e, /* VPMULLQZrmb */ 0x0, /* */ /* Table15059 */ 0x1aa3, /* VGETEXPPDZmb */ 0x1aa9, /* VGETEXPPDZrb */ /* Table15061 */ 0x2929, /* VPLZCNTQZrmb */ 0x0, /* */ /* Table15063 */ 0x341d, /* VPSRLVQZrmb */ 0x0, /* */ /* Table15065 */ 0x3337, /* VPSRAVQZrmb */ 0x0, /* */ /* Table15067 */ 0x325f, /* VPSLLVQZrmb */ 0x0, /* */ /* Table15069 */ 0x3746, /* VRCP14PDZmb */ 0x0, /* */ /* Table15071 */ 0x386a, /* VRSQRT14PDZmb */ 0x0, /* */ /* Table15073 */ 0x2ea6, /* VPOPCNTQZrmb */ 0x0, /* */ /* Table15075 */ 0x22b9, /* VPBLENDMQZrmb */ 0x0, /* */ /* Table15077 */ 0xcb3, /* VBLENDMPDZrmb */ 0x0, /* */ /* Table15079 */ 0x307c, /* VPSHLDVQZmb */ 0x0, /* */ /* Table15081 */ 0x3118, /* VPSHRDVQZmb */ 0x0, /* */ /* Table15083 */ 0x269d, /* VPERMI2Qrmb */ 0x0, /* */ /* Table15085 */ 0x2667, /* VPERMI2PDrmb */ 0x0, /* */ /* Table15087 */ 0x2819, /* VPERMT2Qrmb */ 0x0, /* */ /* Table15089 */ 0x27e3, /* VPERMT2PDrmb */ 0x0, /* */ /* Table15091 */ 0x2e3f, /* VPMULTISHIFTQBZrmb */ 0x0, /* */ /* Table15093 */ 0x14b5, /* VFMADDSUB132PDZmb */ 0x14bb, /* VFMADDSUB132PDZrb */ /* Table15095 */ 0x16bd, /* VFMSUBADD132PDZmb */ 0x16c3, /* VFMSUBADD132PDZrb */ /* Table15097 */ 0x1369, /* VFMADD132PDZmb */ 0x136f, /* VFMADD132PDZrb */ /* Table15099 */ 0x1591, /* VFMSUB132PDZmb */ 0x1597, /* VFMSUB132PDZrb */ /* Table15101 */ 0x17b9, /* VFNMADD132PDZmb */ 0x17bf, /* VFNMADD132PDZrb */ /* Table15103 */ 0x1905, /* VFNMSUB132PDZmb */ 0x190b, /* VFNMSUB132PDZrb */ /* Table15105 */ 0x14f9, /* VFMADDSUB213PDZmb */ 0x14ff, /* VFMADDSUB213PDZrb */ /* Table15107 */ 0x1701, /* VFMSUBADD213PDZmb */ 0x1707, /* VFMSUBADD213PDZrb */ /* Table15109 */ 0x13cd, /* VFMADD213PDZmb */ 0x13d3, /* VFMADD213PDZrb */ /* Table15111 */ 0x15f5, /* VFMSUB213PDZmb */ 0x15fb, /* VFMSUB213PDZrb */ /* Table15113 */ 0x181d, /* VFNMADD213PDZmb */ 0x1823, /* VFNMADD213PDZrb */ /* Table15115 */ 0x1969, /* VFNMSUB213PDZmb */ 0x196f, /* VFNMSUB213PDZrb */ /* Table15117 */ 0x2977, /* VPMADD52LUQZmb */ 0x0, /* */ /* Table15119 */ 0x295c, /* VPMADD52HUQZmb */ 0x0, /* */ /* Table15121 */ 0x153d, /* VFMADDSUB231PDZmb */ 0x1543, /* VFMADDSUB231PDZrb */ /* Table15123 */ 0x1745, /* VFMSUBADD231PDZmb */ 0x174b, /* VFMSUBADD231PDZrb */ /* Table15125 */ 0x1431, /* VFMADD231PDZmb */ 0x1437, /* VFMADD231PDZrb */ /* Table15127 */ 0x1659, /* VFMSUB231PDZmb */ 0x165f, /* VFMSUB231PDZrb */ /* Table15129 */ 0x1881, /* VFNMADD231PDZmb */ 0x1887, /* VFNMADD231PDZrb */ /* Table15131 */ 0x19cd, /* VFNMSUB231PDZmb */ 0x19d3, /* VFNMSUB231PDZrb */ /* Table15133 */ 0x2589, /* VPCONFLICTQZrmb */ 0x0, /* */ /* Table15135 */ 0x1287, /* VEXP2PDZmb */ 0x128d, /* VEXP2PDZrb */ /* Table15137 */ 0x3776, /* VRCP28PDZmb */ 0x377c, /* VRCP28PDZrb */ /* Table15139 */ 0x389a, /* VRSQRT28PDZmb */ 0x38a0, /* VRSQRT28PDZrb */ /* Table15141 */ 0x35a5, /* VPTESTNMDZ128rmbk */ 0x0, /* */ /* Table15143 */ 0x2714, /* VPERMILPSZ128rmbk */ 0x0, /* */ /* Table15145 */ 0x0, /* */ 0xef8, /* VCVTPH2PSZrrbk */ /* Table15147 */ 0x2fa2, /* VPRORVDZ128rmbk */ 0x0, /* */ /* Table15149 */ 0x2f36, /* VPROLVDZ128rmbk */ 0x0, /* */ /* Table15151 */ 0x2047, /* VPABSDZ128rmbk */ 0x0, /* */ /* Table15153 */ 0x3569, /* VPTESTMDZ128rmbk */ 0x0, /* */ /* Table15155 */ 0x20cc, /* VPACKUSDWZ128rmbk */ 0x0, /* */ /* Table15157 */ 0x38eb, /* VSCALEFPSZ128rmbk */ 0x3903, /* VSCALEFPSZrrbk */ /* Table15159 */ 0x0, /* */ 0x3915, /* VSCALEFSSZrrb_Intk */ /* Table15161 */ 0x2a99, /* VPMINSDZ128rmbk */ 0x0, /* */ /* Table15163 */ 0x2aff, /* VPMINUDZ128rmbk */ 0x0, /* */ /* Table15165 */ 0x29cd, /* VPMAXSDZ128rmbk */ 0x0, /* */ /* Table15167 */ 0x2a33, /* VPMAXUDZ128rmbk */ 0x0, /* */ /* Table15169 */ 0x2de0, /* VPMULLDZ128rmbk */ 0x0, /* */ /* Table15171 */ 0x1ab0, /* VGETEXPPSZ128mbk */ 0x1ac8, /* VGETEXPPSZrbk */ /* Table15173 */ 0x0, /* */ 0x1ada, /* VGETEXPSSZrbk */ /* Table15175 */ 0x28fd, /* VPLZCNTDZ128rmbk */ 0x0, /* */ /* Table15177 */ 0x33ed, /* VPSRLVDZ128rmbk */ 0x0, /* */ /* Table15179 */ 0x3309, /* VPSRAVDZ128rmbk */ 0x0, /* */ /* Table15181 */ 0x322f, /* VPSLLVDZ128rmbk */ 0x0, /* */ /* Table15183 */ 0x3750, /* VRCP14PSZ128mbk */ 0x0, /* */ /* Table15185 */ 0x3874, /* VRSQRT14PSZ128mbk */ 0x0, /* */ /* Table15187 */ 0x25ae, /* VPDPBUSDZ128mbk */ 0x0, /* */ /* Table15189 */ 0x2593, /* VPDPBUSDSZ128mbk */ 0x0, /* */ /* Table15191 */ 0x25e4, /* VPDPWSSDZ128mbk */ 0x0, /* */ /* Table15193 */ 0x25c9, /* VPDPWSSDSZ128mbk */ 0x0, /* */ /* Table15195 */ 0x2e7a, /* VPOPCNTDZ128rmbk */ 0x0, /* */ /* Table15197 */ 0x228d, /* VPBLENDMDZ128rmbk */ 0x0, /* */ /* Table15199 */ 0xcbd, /* VBLENDMPSZ128rmbk */ 0x0, /* */ /* Table15201 */ 0x3050, /* VPSHLDVDZ128mbk */ 0x0, /* */ /* Table15203 */ 0x30ec, /* VPSHRDVDZ128mbk */ 0x0, /* */ /* Table15205 */ 0x263b, /* VPERMI2D128rmbk */ 0x0, /* */ /* Table15207 */ 0x2671, /* VPERMI2PS128rmbk */ 0x0, /* */ /* Table15209 */ 0x27b7, /* VPERMT2D128rmbk */ 0x0, /* */ /* Table15211 */ 0x27ed, /* VPERMT2PS128rmbk */ 0x0, /* */ /* Table15213 */ 0x14c6, /* VFMADDSUB132PSZ128mbk */ 0x14de, /* VFMADDSUB132PSZrbk */ /* Table15215 */ 0x16ce, /* VFMSUBADD132PSZ128mbk */ 0x16e6, /* VFMSUBADD132PSZrbk */ /* Table15217 */ 0x137a, /* VFMADD132PSZ128mbk */ 0x1392, /* VFMADD132PSZrbk */ /* Table15219 */ 0x0, /* */ 0x13b2, /* VFMADD132SSZrb_Intk */ /* Table15221 */ 0x15a2, /* VFMSUB132PSZ128mbk */ 0x15ba, /* VFMSUB132PSZrbk */ /* Table15223 */ 0x0, /* */ 0x15da, /* VFMSUB132SSZrb_Intk */ /* Table15225 */ 0x17ca, /* VFNMADD132PSZ128mbk */ 0x17e2, /* VFNMADD132PSZrbk */ /* Table15227 */ 0x0, /* */ 0x1802, /* VFNMADD132SSZrb_Intk */ /* Table15229 */ 0x1916, /* VFNMSUB132PSZ128mbk */ 0x192e, /* VFNMSUB132PSZrbk */ /* Table15231 */ 0x0, /* */ 0x194e, /* VFNMSUB132SSZrb_Intk */ /* Table15233 */ 0x150a, /* VFMADDSUB213PSZ128mbk */ 0x1522, /* VFMADDSUB213PSZrbk */ /* Table15235 */ 0x1712, /* VFMSUBADD213PSZ128mbk */ 0x172a, /* VFMSUBADD213PSZrbk */ /* Table15237 */ 0x13de, /* VFMADD213PSZ128mbk */ 0x13f6, /* VFMADD213PSZrbk */ /* Table15239 */ 0x0, /* */ 0x1416, /* VFMADD213SSZrb_Intk */ /* Table15241 */ 0x1606, /* VFMSUB213PSZ128mbk */ 0x161e, /* VFMSUB213PSZrbk */ /* Table15243 */ 0x0, /* */ 0x163e, /* VFMSUB213SSZrb_Intk */ /* Table15245 */ 0x182e, /* VFNMADD213PSZ128mbk */ 0x1846, /* VFNMADD213PSZrbk */ /* Table15247 */ 0x0, /* */ 0x1866, /* VFNMADD213SSZrb_Intk */ /* Table15249 */ 0x197a, /* VFNMSUB213PSZ128mbk */ 0x1992, /* VFNMSUB213PSZrbk */ /* Table15251 */ 0x0, /* */ 0x19b2, /* VFNMSUB213SSZrb_Intk */ /* Table15253 */ 0x154e, /* VFMADDSUB231PSZ128mbk */ 0x1566, /* VFMADDSUB231PSZrbk */ /* Table15255 */ 0x1756, /* VFMSUBADD231PSZ128mbk */ 0x176e, /* VFMSUBADD231PSZrbk */ /* Table15257 */ 0x1442, /* VFMADD231PSZ128mbk */ 0x145a, /* VFMADD231PSZrbk */ /* Table15259 */ 0x0, /* */ 0x147a, /* VFMADD231SSZrb_Intk */ /* Table15261 */ 0x166a, /* VFMSUB231PSZ128mbk */ 0x1682, /* VFMSUB231PSZrbk */ /* Table15263 */ 0x0, /* */ 0x16a2, /* VFMSUB231SSZrb_Intk */ /* Table15265 */ 0x1892, /* VFNMADD231PSZ128mbk */ 0x18aa, /* VFNMADD231PSZrbk */ /* Table15267 */ 0x0, /* */ 0x18ca, /* VFNMADD231SSZrb_Intk */ /* Table15269 */ 0x19de, /* VFNMSUB231PSZ128mbk */ 0x19f6, /* VFNMSUB231PSZrbk */ /* Table15271 */ 0x0, /* */ 0x1a16, /* VFNMSUB231SSZrb_Intk */ /* Table15273 */ 0x255d, /* VPCONFLICTDZ128rmbk */ 0x0, /* */ /* Table15275 */ 0x0, /* */ 0x129a, /* VEXP2PSZrbk */ /* Table15277 */ 0x0, /* */ 0x3789, /* VRCP28PSZrbk */ /* Table15279 */ 0x0, /* */ 0x379b, /* VRCP28SSZrbk */ /* Table15281 */ 0x0, /* */ 0x38ad, /* VRSQRT28PSZrbk */ /* Table15283 */ 0x0, /* */ 0x38bf, /* VRSQRT28SSZrbk */ /* Table15285 */ 0x35b7, /* VPTESTNMQZ128rmbk */ 0x0, /* */ /* Table15287 */ 0x26d6, /* VPERMILPDZ128rmbk */ 0x0, /* */ /* Table15289 */ 0x2fbd, /* VPRORVQZ128rmbk */ 0x0, /* */ /* Table15291 */ 0x2f51, /* VPROLVQZ128rmbk */ 0x0, /* */ /* Table15293 */ 0x2064, /* VPABSQZ128rmbk */ 0x0, /* */ /* Table15295 */ 0x357b, /* VPTESTMQZ128rmbk */ 0x0, /* */ /* Table15297 */ 0x2d7f, /* VPMULDQZ128rmbk */ 0x0, /* */ /* Table15299 */ 0x23d5, /* VPCMPEQQZ128rmbk */ 0x0, /* */ /* Table15301 */ 0x38cd, /* VSCALEFPDZ128rmbk */ 0x38e5, /* VSCALEFPDZrrbk */ /* Table15303 */ 0x0, /* */ 0x390c, /* VSCALEFSDZrrb_Intk */ /* Table15305 */ 0x2425, /* VPCMPGTQZ128rmbk */ 0x0, /* */ /* Table15307 */ 0x2ab6, /* VPMINSQZ128rmbk */ 0x0, /* */ /* Table15309 */ 0x2b1c, /* VPMINUQZ128rmbk */ 0x0, /* */ /* Table15311 */ 0x29ea, /* VPMAXSQZ128rmbk */ 0x0, /* */ /* Table15313 */ 0x2a50, /* VPMAXUQZ128rmbk */ 0x0, /* */ /* Table15315 */ 0x2dfd, /* VPMULLQZ128rmbk */ 0x0, /* */ /* Table15317 */ 0x1a92, /* VGETEXPPDZ128mbk */ 0x1aaa, /* VGETEXPPDZrbk */ /* Table15319 */ 0x0, /* */ 0x1ad1, /* VGETEXPSDZrbk */ /* Table15321 */ 0x2918, /* VPLZCNTQZ128rmbk */ 0x0, /* */ /* Table15323 */ 0x340c, /* VPSRLVQZ128rmbk */ 0x0, /* */ /* Table15325 */ 0x3326, /* VPSRAVQZ128rmbk */ 0x0, /* */ /* Table15327 */ 0x324e, /* VPSLLVQZ128rmbk */ 0x0, /* */ /* Table15329 */ 0x3735, /* VRCP14PDZ128mbk */ 0x0, /* */ /* Table15331 */ 0x3859, /* VRSQRT14PDZ128mbk */ 0x0, /* */ /* Table15333 */ 0x2e95, /* VPOPCNTQZ128rmbk */ 0x0, /* */ /* Table15335 */ 0x22a8, /* VPBLENDMQZ128rmbk */ 0x0, /* */ /* Table15337 */ 0xca2, /* VBLENDMPDZ128rmbk */ 0x0, /* */ /* Table15339 */ 0x306b, /* VPSHLDVQZ128mbk */ 0x0, /* */ /* Table15341 */ 0x3107, /* VPSHRDVQZ128mbk */ 0x0, /* */ /* Table15343 */ 0x268c, /* VPERMI2Q128rmbk */ 0x0, /* */ /* Table15345 */ 0x2656, /* VPERMI2PD128rmbk */ 0x0, /* */ /* Table15347 */ 0x2808, /* VPERMT2Q128rmbk */ 0x0, /* */ /* Table15349 */ 0x27d2, /* VPERMT2PD128rmbk */ 0x0, /* */ /* Table15351 */ 0x2e2e, /* VPMULTISHIFTQBZ128rmbk */ 0x0, /* */ /* Table15353 */ 0x14a4, /* VFMADDSUB132PDZ128mbk */ 0x14bc, /* VFMADDSUB132PDZrbk */ /* Table15355 */ 0x16ac, /* VFMSUBADD132PDZ128mbk */ 0x16c4, /* VFMSUBADD132PDZrbk */ /* Table15357 */ 0x1358, /* VFMADD132PDZ128mbk */ 0x1370, /* VFMADD132PDZrbk */ /* Table15359 */ 0x0, /* */ 0x13a2, /* VFMADD132SDZrb_Intk */ /* Table15361 */ 0x1580, /* VFMSUB132PDZ128mbk */ 0x1598, /* VFMSUB132PDZrbk */ /* Table15363 */ 0x0, /* */ 0x15ca, /* VFMSUB132SDZrb_Intk */ /* Table15365 */ 0x17a8, /* VFNMADD132PDZ128mbk */ 0x17c0, /* VFNMADD132PDZrbk */ /* Table15367 */ 0x0, /* */ 0x17f2, /* VFNMADD132SDZrb_Intk */ /* Table15369 */ 0x18f4, /* VFNMSUB132PDZ128mbk */ 0x190c, /* VFNMSUB132PDZrbk */ /* Table15371 */ 0x0, /* */ 0x193e, /* VFNMSUB132SDZrb_Intk */ /* Table15373 */ 0x14e8, /* VFMADDSUB213PDZ128mbk */ 0x1500, /* VFMADDSUB213PDZrbk */ /* Table15375 */ 0x16f0, /* VFMSUBADD213PDZ128mbk */ 0x1708, /* VFMSUBADD213PDZrbk */ /* Table15377 */ 0x13bc, /* VFMADD213PDZ128mbk */ 0x13d4, /* VFMADD213PDZrbk */ /* Table15379 */ 0x0, /* */ 0x1406, /* VFMADD213SDZrb_Intk */ /* Table15381 */ 0x15e4, /* VFMSUB213PDZ128mbk */ 0x15fc, /* VFMSUB213PDZrbk */ /* Table15383 */ 0x0, /* */ 0x162e, /* VFMSUB213SDZrb_Intk */ /* Table15385 */ 0x180c, /* VFNMADD213PDZ128mbk */ 0x1824, /* VFNMADD213PDZrbk */ /* Table15387 */ 0x0, /* */ 0x1856, /* VFNMADD213SDZrb_Intk */ /* Table15389 */ 0x1958, /* VFNMSUB213PDZ128mbk */ 0x1970, /* VFNMSUB213PDZrbk */ /* Table15391 */ 0x0, /* */ 0x19a2, /* VFNMSUB213SDZrb_Intk */ /* Table15393 */ 0x2966, /* VPMADD52LUQZ128mbk */ 0x0, /* */ /* Table15395 */ 0x294b, /* VPMADD52HUQZ128mbk */ 0x0, /* */ /* Table15397 */ 0x152c, /* VFMADDSUB231PDZ128mbk */ 0x1544, /* VFMADDSUB231PDZrbk */ /* Table15399 */ 0x1734, /* VFMSUBADD231PDZ128mbk */ 0x174c, /* VFMSUBADD231PDZrbk */ /* Table15401 */ 0x1420, /* VFMADD231PDZ128mbk */ 0x1438, /* VFMADD231PDZrbk */ /* Table15403 */ 0x0, /* */ 0x146a, /* VFMADD231SDZrb_Intk */ /* Table15405 */ 0x1648, /* VFMSUB231PDZ128mbk */ 0x1660, /* VFMSUB231PDZrbk */ /* Table15407 */ 0x0, /* */ 0x1692, /* VFMSUB231SDZrb_Intk */ /* Table15409 */ 0x1870, /* VFNMADD231PDZ128mbk */ 0x1888, /* VFNMADD231PDZrbk */ /* Table15411 */ 0x0, /* */ 0x18ba, /* VFNMADD231SDZrb_Intk */ /* Table15413 */ 0x19bc, /* VFNMSUB231PDZ128mbk */ 0x19d4, /* VFNMSUB231PDZrbk */ /* Table15415 */ 0x0, /* */ 0x1a06, /* VFNMSUB231SDZrb_Intk */ /* Table15417 */ 0x2578, /* VPCONFLICTQZ128rmbk */ 0x0, /* */ /* Table15419 */ 0x0, /* */ 0x128e, /* VEXP2PDZrbk */ /* Table15421 */ 0x0, /* */ 0x377d, /* VRCP28PDZrbk */ /* Table15423 */ 0x0, /* */ 0x3792, /* VRCP28SDZrbk */ /* Table15425 */ 0x0, /* */ 0x38a1, /* VRSQRT28PDZrbk */ /* Table15427 */ 0x0, /* */ 0x38b6, /* VRSQRT28SDZrbk */ /* Table15429 */ 0x35ab, /* VPTESTNMDZ256rmbk */ 0x0, /* */ /* Table15431 */ 0x2726, /* VPERMILPSZ256rmbk */ 0x0, /* */ /* Table15433 */ 0x2fab, /* VPRORVDZ256rmbk */ 0x0, /* */ /* Table15435 */ 0x2f3f, /* VPROLVDZ256rmbk */ 0x0, /* */ /* Table15437 */ 0x276d, /* VPERMPSZ256rmbk */ 0x0, /* */ /* Table15439 */ 0x2050, /* VPABSDZ256rmbk */ 0x0, /* */ /* Table15441 */ 0x356f, /* VPTESTMDZ256rmbk */ 0x0, /* */ /* Table15443 */ 0x20d5, /* VPACKUSDWZ256rmbk */ 0x0, /* */ /* Table15445 */ 0x38f4, /* VSCALEFPSZ256rmbk */ 0x3903, /* VSCALEFPSZrrbk */ /* Table15447 */ 0x2617, /* VPERMDZ256rmbk */ 0x0, /* */ /* Table15449 */ 0x2aa2, /* VPMINSDZ256rmbk */ 0x0, /* */ /* Table15451 */ 0x2b08, /* VPMINUDZ256rmbk */ 0x0, /* */ /* Table15453 */ 0x29d6, /* VPMAXSDZ256rmbk */ 0x0, /* */ /* Table15455 */ 0x2a3c, /* VPMAXUDZ256rmbk */ 0x0, /* */ /* Table15457 */ 0x2de9, /* VPMULLDZ256rmbk */ 0x0, /* */ /* Table15459 */ 0x1ab9, /* VGETEXPPSZ256mbk */ 0x1ac8, /* VGETEXPPSZrbk */ /* Table15461 */ 0x2906, /* VPLZCNTDZ256rmbk */ 0x0, /* */ /* Table15463 */ 0x33f6, /* VPSRLVDZ256rmbk */ 0x0, /* */ /* Table15465 */ 0x3312, /* VPSRAVDZ256rmbk */ 0x0, /* */ /* Table15467 */ 0x3238, /* VPSLLVDZ256rmbk */ 0x0, /* */ /* Table15469 */ 0x3759, /* VRCP14PSZ256mbk */ 0x0, /* */ /* Table15471 */ 0x387d, /* VRSQRT14PSZ256mbk */ 0x0, /* */ /* Table15473 */ 0x25b7, /* VPDPBUSDZ256mbk */ 0x0, /* */ /* Table15475 */ 0x259c, /* VPDPBUSDSZ256mbk */ 0x0, /* */ /* Table15477 */ 0x25ed, /* VPDPWSSDZ256mbk */ 0x0, /* */ /* Table15479 */ 0x25d2, /* VPDPWSSDSZ256mbk */ 0x0, /* */ /* Table15481 */ 0x2e83, /* VPOPCNTDZ256rmbk */ 0x0, /* */ /* Table15483 */ 0x2296, /* VPBLENDMDZ256rmbk */ 0x0, /* */ /* Table15485 */ 0xcc6, /* VBLENDMPSZ256rmbk */ 0x0, /* */ /* Table15487 */ 0x3059, /* VPSHLDVDZ256mbk */ 0x0, /* */ /* Table15489 */ 0x30f5, /* VPSHRDVDZ256mbk */ 0x0, /* */ /* Table15491 */ 0x2644, /* VPERMI2D256rmbk */ 0x0, /* */ /* Table15493 */ 0x267a, /* VPERMI2PS256rmbk */ 0x0, /* */ /* Table15495 */ 0x27c0, /* VPERMT2D256rmbk */ 0x0, /* */ /* Table15497 */ 0x27f6, /* VPERMT2PS256rmbk */ 0x0, /* */ /* Table15499 */ 0x14cf, /* VFMADDSUB132PSZ256mbk */ 0x14de, /* VFMADDSUB132PSZrbk */ /* Table15501 */ 0x16d7, /* VFMSUBADD132PSZ256mbk */ 0x16e6, /* VFMSUBADD132PSZrbk */ /* Table15503 */ 0x1383, /* VFMADD132PSZ256mbk */ 0x1392, /* VFMADD132PSZrbk */ /* Table15505 */ 0x15ab, /* VFMSUB132PSZ256mbk */ 0x15ba, /* VFMSUB132PSZrbk */ /* Table15507 */ 0x17d3, /* VFNMADD132PSZ256mbk */ 0x17e2, /* VFNMADD132PSZrbk */ /* Table15509 */ 0x191f, /* VFNMSUB132PSZ256mbk */ 0x192e, /* VFNMSUB132PSZrbk */ /* Table15511 */ 0x1513, /* VFMADDSUB213PSZ256mbk */ 0x1522, /* VFMADDSUB213PSZrbk */ /* Table15513 */ 0x171b, /* VFMSUBADD213PSZ256mbk */ 0x172a, /* VFMSUBADD213PSZrbk */ /* Table15515 */ 0x13e7, /* VFMADD213PSZ256mbk */ 0x13f6, /* VFMADD213PSZrbk */ /* Table15517 */ 0x160f, /* VFMSUB213PSZ256mbk */ 0x161e, /* VFMSUB213PSZrbk */ /* Table15519 */ 0x1837, /* VFNMADD213PSZ256mbk */ 0x1846, /* VFNMADD213PSZrbk */ /* Table15521 */ 0x1983, /* VFNMSUB213PSZ256mbk */ 0x1992, /* VFNMSUB213PSZrbk */ /* Table15523 */ 0x1557, /* VFMADDSUB231PSZ256mbk */ 0x1566, /* VFMADDSUB231PSZrbk */ /* Table15525 */ 0x175f, /* VFMSUBADD231PSZ256mbk */ 0x176e, /* VFMSUBADD231PSZrbk */ /* Table15527 */ 0x144b, /* VFMADD231PSZ256mbk */ 0x145a, /* VFMADD231PSZrbk */ /* Table15529 */ 0x1673, /* VFMSUB231PSZ256mbk */ 0x1682, /* VFMSUB231PSZrbk */ /* Table15531 */ 0x189b, /* VFNMADD231PSZ256mbk */ 0x18aa, /* VFNMADD231PSZrbk */ /* Table15533 */ 0x19e7, /* VFNMSUB231PSZ256mbk */ 0x19f6, /* VFNMSUB231PSZrbk */ /* Table15535 */ 0x2566, /* VPCONFLICTDZ256rmbk */ 0x0, /* */ /* Table15537 */ 0x35bd, /* VPTESTNMQZ256rmbk */ 0x0, /* */ /* Table15539 */ 0x26e8, /* VPERMILPDZ256rmbk */ 0x0, /* */ /* Table15541 */ 0x2fc6, /* VPRORVQZ256rmbk */ 0x0, /* */ /* Table15543 */ 0x2f5a, /* VPROLVQZ256rmbk */ 0x0, /* */ /* Table15545 */ 0x2750, /* VPERMPDZ256rmbk */ 0x0, /* */ /* Table15547 */ 0x206d, /* VPABSQZ256rmbk */ 0x0, /* */ /* Table15549 */ 0x3581, /* VPTESTMQZ256rmbk */ 0x0, /* */ /* Table15551 */ 0x2d88, /* VPMULDQZ256rmbk */ 0x0, /* */ /* Table15553 */ 0x23db, /* VPCMPEQQZ256rmbk */ 0x0, /* */ /* Table15555 */ 0x38d6, /* VSCALEFPDZ256rmbk */ 0x38e5, /* VSCALEFPDZrrbk */ /* Table15557 */ 0x278a, /* VPERMQZ256rmbk */ 0x0, /* */ /* Table15559 */ 0x242b, /* VPCMPGTQZ256rmbk */ 0x0, /* */ /* Table15561 */ 0x2abf, /* VPMINSQZ256rmbk */ 0x0, /* */ /* Table15563 */ 0x2b25, /* VPMINUQZ256rmbk */ 0x0, /* */ /* Table15565 */ 0x29f3, /* VPMAXSQZ256rmbk */ 0x0, /* */ /* Table15567 */ 0x2a59, /* VPMAXUQZ256rmbk */ 0x0, /* */ /* Table15569 */ 0x2e06, /* VPMULLQZ256rmbk */ 0x0, /* */ /* Table15571 */ 0x1a9b, /* VGETEXPPDZ256mbk */ 0x1aaa, /* VGETEXPPDZrbk */ /* Table15573 */ 0x2921, /* VPLZCNTQZ256rmbk */ 0x0, /* */ /* Table15575 */ 0x3415, /* VPSRLVQZ256rmbk */ 0x0, /* */ /* Table15577 */ 0x332f, /* VPSRAVQZ256rmbk */ 0x0, /* */ /* Table15579 */ 0x3257, /* VPSLLVQZ256rmbk */ 0x0, /* */ /* Table15581 */ 0x373e, /* VRCP14PDZ256mbk */ 0x0, /* */ /* Table15583 */ 0x3862, /* VRSQRT14PDZ256mbk */ 0x0, /* */ /* Table15585 */ 0x2e9e, /* VPOPCNTQZ256rmbk */ 0x0, /* */ /* Table15587 */ 0x22b1, /* VPBLENDMQZ256rmbk */ 0x0, /* */ /* Table15589 */ 0xcab, /* VBLENDMPDZ256rmbk */ 0x0, /* */ /* Table15591 */ 0x3074, /* VPSHLDVQZ256mbk */ 0x0, /* */ /* Table15593 */ 0x3110, /* VPSHRDVQZ256mbk */ 0x0, /* */ /* Table15595 */ 0x2695, /* VPERMI2Q256rmbk */ 0x0, /* */ /* Table15597 */ 0x265f, /* VPERMI2PD256rmbk */ 0x0, /* */ /* Table15599 */ 0x2811, /* VPERMT2Q256rmbk */ 0x0, /* */ /* Table15601 */ 0x27db, /* VPERMT2PD256rmbk */ 0x0, /* */ /* Table15603 */ 0x2e37, /* VPMULTISHIFTQBZ256rmbk */ 0x0, /* */ /* Table15605 */ 0x14ad, /* VFMADDSUB132PDZ256mbk */ 0x14bc, /* VFMADDSUB132PDZrbk */ /* Table15607 */ 0x16b5, /* VFMSUBADD132PDZ256mbk */ 0x16c4, /* VFMSUBADD132PDZrbk */ /* Table15609 */ 0x1361, /* VFMADD132PDZ256mbk */ 0x1370, /* VFMADD132PDZrbk */ /* Table15611 */ 0x1589, /* VFMSUB132PDZ256mbk */ 0x1598, /* VFMSUB132PDZrbk */ /* Table15613 */ 0x17b1, /* VFNMADD132PDZ256mbk */ 0x17c0, /* VFNMADD132PDZrbk */ /* Table15615 */ 0x18fd, /* VFNMSUB132PDZ256mbk */ 0x190c, /* VFNMSUB132PDZrbk */ /* Table15617 */ 0x14f1, /* VFMADDSUB213PDZ256mbk */ 0x1500, /* VFMADDSUB213PDZrbk */ /* Table15619 */ 0x16f9, /* VFMSUBADD213PDZ256mbk */ 0x1708, /* VFMSUBADD213PDZrbk */ /* Table15621 */ 0x13c5, /* VFMADD213PDZ256mbk */ 0x13d4, /* VFMADD213PDZrbk */ /* Table15623 */ 0x15ed, /* VFMSUB213PDZ256mbk */ 0x15fc, /* VFMSUB213PDZrbk */ /* Table15625 */ 0x1815, /* VFNMADD213PDZ256mbk */ 0x1824, /* VFNMADD213PDZrbk */ /* Table15627 */ 0x1961, /* VFNMSUB213PDZ256mbk */ 0x1970, /* VFNMSUB213PDZrbk */ /* Table15629 */ 0x296f, /* VPMADD52LUQZ256mbk */ 0x0, /* */ /* Table15631 */ 0x2954, /* VPMADD52HUQZ256mbk */ 0x0, /* */ /* Table15633 */ 0x1535, /* VFMADDSUB231PDZ256mbk */ 0x1544, /* VFMADDSUB231PDZrbk */ /* Table15635 */ 0x173d, /* VFMSUBADD231PDZ256mbk */ 0x174c, /* VFMSUBADD231PDZrbk */ /* Table15637 */ 0x1429, /* VFMADD231PDZ256mbk */ 0x1438, /* VFMADD231PDZrbk */ /* Table15639 */ 0x1651, /* VFMSUB231PDZ256mbk */ 0x1660, /* VFMSUB231PDZrbk */ /* Table15641 */ 0x1879, /* VFNMADD231PDZ256mbk */ 0x1888, /* VFNMADD231PDZrbk */ /* Table15643 */ 0x19c5, /* VFNMSUB231PDZ256mbk */ 0x19d4, /* VFNMSUB231PDZrbk */ /* Table15645 */ 0x2581, /* VPCONFLICTQZ256rmbk */ 0x0, /* */ /* Table15647 */ 0x35b1, /* VPTESTNMDZrmbk */ 0x0, /* */ /* Table15649 */ 0x2738, /* VPERMILPSZrmbk */ 0x0, /* */ /* Table15651 */ 0x2fb4, /* VPRORVDZrmbk */ 0x0, /* */ /* Table15653 */ 0x2f48, /* VPROLVDZrmbk */ 0x0, /* */ /* Table15655 */ 0x2776, /* VPERMPSZrmbk */ 0x0, /* */ /* Table15657 */ 0x2059, /* VPABSDZrmbk */ 0x0, /* */ /* Table15659 */ 0x3575, /* VPTESTMDZrmbk */ 0x0, /* */ /* Table15661 */ 0x20de, /* VPACKUSDWZrmbk */ 0x0, /* */ /* Table15663 */ 0x38fd, /* VSCALEFPSZrmbk */ 0x3903, /* VSCALEFPSZrrbk */ /* Table15665 */ 0x2620, /* VPERMDZrmbk */ 0x0, /* */ /* Table15667 */ 0x2aab, /* VPMINSDZrmbk */ 0x0, /* */ /* Table15669 */ 0x2b11, /* VPMINUDZrmbk */ 0x0, /* */ /* Table15671 */ 0x29df, /* VPMAXSDZrmbk */ 0x0, /* */ /* Table15673 */ 0x2a45, /* VPMAXUDZrmbk */ 0x0, /* */ /* Table15675 */ 0x2df2, /* VPMULLDZrmbk */ 0x0, /* */ /* Table15677 */ 0x1ac2, /* VGETEXPPSZmbk */ 0x1ac8, /* VGETEXPPSZrbk */ /* Table15679 */ 0x290f, /* VPLZCNTDZrmbk */ 0x0, /* */ /* Table15681 */ 0x33ff, /* VPSRLVDZrmbk */ 0x0, /* */ /* Table15683 */ 0x331b, /* VPSRAVDZrmbk */ 0x0, /* */ /* Table15685 */ 0x3241, /* VPSLLVDZrmbk */ 0x0, /* */ /* Table15687 */ 0x3762, /* VRCP14PSZmbk */ 0x0, /* */ /* Table15689 */ 0x3886, /* VRSQRT14PSZmbk */ 0x0, /* */ /* Table15691 */ 0x25c0, /* VPDPBUSDZmbk */ 0x0, /* */ /* Table15693 */ 0x25a5, /* VPDPBUSDSZmbk */ 0x0, /* */ /* Table15695 */ 0x25f6, /* VPDPWSSDZmbk */ 0x0, /* */ /* Table15697 */ 0x25db, /* VPDPWSSDSZmbk */ 0x0, /* */ /* Table15699 */ 0x2e8c, /* VPOPCNTDZrmbk */ 0x0, /* */ /* Table15701 */ 0x229f, /* VPBLENDMDZrmbk */ 0x0, /* */ /* Table15703 */ 0xccf, /* VBLENDMPSZrmbk */ 0x0, /* */ /* Table15705 */ 0x3062, /* VPSHLDVDZmbk */ 0x0, /* */ /* Table15707 */ 0x30fe, /* VPSHRDVDZmbk */ 0x0, /* */ /* Table15709 */ 0x264d, /* VPERMI2Drmbk */ 0x0, /* */ /* Table15711 */ 0x2683, /* VPERMI2PSrmbk */ 0x0, /* */ /* Table15713 */ 0x27c9, /* VPERMT2Drmbk */ 0x0, /* */ /* Table15715 */ 0x27ff, /* VPERMT2PSrmbk */ 0x0, /* */ /* Table15717 */ 0x14d8, /* VFMADDSUB132PSZmbk */ 0x14de, /* VFMADDSUB132PSZrbk */ /* Table15719 */ 0x16e0, /* VFMSUBADD132PSZmbk */ 0x16e6, /* VFMSUBADD132PSZrbk */ /* Table15721 */ 0x138c, /* VFMADD132PSZmbk */ 0x1392, /* VFMADD132PSZrbk */ /* Table15723 */ 0x15b4, /* VFMSUB132PSZmbk */ 0x15ba, /* VFMSUB132PSZrbk */ /* Table15725 */ 0x17dc, /* VFNMADD132PSZmbk */ 0x17e2, /* VFNMADD132PSZrbk */ /* Table15727 */ 0x1928, /* VFNMSUB132PSZmbk */ 0x192e, /* VFNMSUB132PSZrbk */ /* Table15729 */ 0x151c, /* VFMADDSUB213PSZmbk */ 0x1522, /* VFMADDSUB213PSZrbk */ /* Table15731 */ 0x1724, /* VFMSUBADD213PSZmbk */ 0x172a, /* VFMSUBADD213PSZrbk */ /* Table15733 */ 0x13f0, /* VFMADD213PSZmbk */ 0x13f6, /* VFMADD213PSZrbk */ /* Table15735 */ 0x1618, /* VFMSUB213PSZmbk */ 0x161e, /* VFMSUB213PSZrbk */ /* Table15737 */ 0x1840, /* VFNMADD213PSZmbk */ 0x1846, /* VFNMADD213PSZrbk */ /* Table15739 */ 0x198c, /* VFNMSUB213PSZmbk */ 0x1992, /* VFNMSUB213PSZrbk */ /* Table15741 */ 0x1560, /* VFMADDSUB231PSZmbk */ 0x1566, /* VFMADDSUB231PSZrbk */ /* Table15743 */ 0x1768, /* VFMSUBADD231PSZmbk */ 0x176e, /* VFMSUBADD231PSZrbk */ /* Table15745 */ 0x1454, /* VFMADD231PSZmbk */ 0x145a, /* VFMADD231PSZrbk */ /* Table15747 */ 0x167c, /* VFMSUB231PSZmbk */ 0x1682, /* VFMSUB231PSZrbk */ /* Table15749 */ 0x18a4, /* VFNMADD231PSZmbk */ 0x18aa, /* VFNMADD231PSZrbk */ /* Table15751 */ 0x19f0, /* VFNMSUB231PSZmbk */ 0x19f6, /* VFNMSUB231PSZrbk */ /* Table15753 */ 0x256f, /* VPCONFLICTDZrmbk */ 0x0, /* */ /* Table15755 */ 0x1294, /* VEXP2PSZmbk */ 0x129a, /* VEXP2PSZrbk */ /* Table15757 */ 0x3783, /* VRCP28PSZmbk */ 0x3789, /* VRCP28PSZrbk */ /* Table15759 */ 0x38a7, /* VRSQRT28PSZmbk */ 0x38ad, /* VRSQRT28PSZrbk */ /* Table15761 */ 0x35c3, /* VPTESTNMQZrmbk */ 0x0, /* */ /* Table15763 */ 0x26fa, /* VPERMILPDZrmbk */ 0x0, /* */ /* Table15765 */ 0x2fcf, /* VPRORVQZrmbk */ 0x0, /* */ /* Table15767 */ 0x2f63, /* VPROLVQZrmbk */ 0x0, /* */ /* Table15769 */ 0x2762, /* VPERMPDZrmbk */ 0x0, /* */ /* Table15771 */ 0x2076, /* VPABSQZrmbk */ 0x0, /* */ /* Table15773 */ 0x3587, /* VPTESTMQZrmbk */ 0x0, /* */ /* Table15775 */ 0x2d91, /* VPMULDQZrmbk */ 0x0, /* */ /* Table15777 */ 0x23e1, /* VPCMPEQQZrmbk */ 0x0, /* */ /* Table15779 */ 0x38df, /* VSCALEFPDZrmbk */ 0x38e5, /* VSCALEFPDZrrbk */ /* Table15781 */ 0x279c, /* VPERMQZrmbk */ 0x0, /* */ /* Table15783 */ 0x2431, /* VPCMPGTQZrmbk */ 0x0, /* */ /* Table15785 */ 0x2ac8, /* VPMINSQZrmbk */ 0x0, /* */ /* Table15787 */ 0x2b2e, /* VPMINUQZrmbk */ 0x0, /* */ /* Table15789 */ 0x29fc, /* VPMAXSQZrmbk */ 0x0, /* */ /* Table15791 */ 0x2a62, /* VPMAXUQZrmbk */ 0x0, /* */ /* Table15793 */ 0x2e0f, /* VPMULLQZrmbk */ 0x0, /* */ /* Table15795 */ 0x1aa4, /* VGETEXPPDZmbk */ 0x1aaa, /* VGETEXPPDZrbk */ /* Table15797 */ 0x292a, /* VPLZCNTQZrmbk */ 0x0, /* */ /* Table15799 */ 0x341e, /* VPSRLVQZrmbk */ 0x0, /* */ /* Table15801 */ 0x3338, /* VPSRAVQZrmbk */ 0x0, /* */ /* Table15803 */ 0x3260, /* VPSLLVQZrmbk */ 0x0, /* */ /* Table15805 */ 0x3747, /* VRCP14PDZmbk */ 0x0, /* */ /* Table15807 */ 0x386b, /* VRSQRT14PDZmbk */ 0x0, /* */ /* Table15809 */ 0x2ea7, /* VPOPCNTQZrmbk */ 0x0, /* */ /* Table15811 */ 0x22ba, /* VPBLENDMQZrmbk */ 0x0, /* */ /* Table15813 */ 0xcb4, /* VBLENDMPDZrmbk */ 0x0, /* */ /* Table15815 */ 0x307d, /* VPSHLDVQZmbk */ 0x0, /* */ /* Table15817 */ 0x3119, /* VPSHRDVQZmbk */ 0x0, /* */ /* Table15819 */ 0x269e, /* VPERMI2Qrmbk */ 0x0, /* */ /* Table15821 */ 0x2668, /* VPERMI2PDrmbk */ 0x0, /* */ /* Table15823 */ 0x281a, /* VPERMT2Qrmbk */ 0x0, /* */ /* Table15825 */ 0x27e4, /* VPERMT2PDrmbk */ 0x0, /* */ /* Table15827 */ 0x2e40, /* VPMULTISHIFTQBZrmbk */ 0x0, /* */ /* Table15829 */ 0x14b6, /* VFMADDSUB132PDZmbk */ 0x14bc, /* VFMADDSUB132PDZrbk */ /* Table15831 */ 0x16be, /* VFMSUBADD132PDZmbk */ 0x16c4, /* VFMSUBADD132PDZrbk */ /* Table15833 */ 0x136a, /* VFMADD132PDZmbk */ 0x1370, /* VFMADD132PDZrbk */ /* Table15835 */ 0x1592, /* VFMSUB132PDZmbk */ 0x1598, /* VFMSUB132PDZrbk */ /* Table15837 */ 0x17ba, /* VFNMADD132PDZmbk */ 0x17c0, /* VFNMADD132PDZrbk */ /* Table15839 */ 0x1906, /* VFNMSUB132PDZmbk */ 0x190c, /* VFNMSUB132PDZrbk */ /* Table15841 */ 0x14fa, /* VFMADDSUB213PDZmbk */ 0x1500, /* VFMADDSUB213PDZrbk */ /* Table15843 */ 0x1702, /* VFMSUBADD213PDZmbk */ 0x1708, /* VFMSUBADD213PDZrbk */ /* Table15845 */ 0x13ce, /* VFMADD213PDZmbk */ 0x13d4, /* VFMADD213PDZrbk */ /* Table15847 */ 0x15f6, /* VFMSUB213PDZmbk */ 0x15fc, /* VFMSUB213PDZrbk */ /* Table15849 */ 0x181e, /* VFNMADD213PDZmbk */ 0x1824, /* VFNMADD213PDZrbk */ /* Table15851 */ 0x196a, /* VFNMSUB213PDZmbk */ 0x1970, /* VFNMSUB213PDZrbk */ /* Table15853 */ 0x2978, /* VPMADD52LUQZmbk */ 0x0, /* */ /* Table15855 */ 0x295d, /* VPMADD52HUQZmbk */ 0x0, /* */ /* Table15857 */ 0x153e, /* VFMADDSUB231PDZmbk */ 0x1544, /* VFMADDSUB231PDZrbk */ /* Table15859 */ 0x1746, /* VFMSUBADD231PDZmbk */ 0x174c, /* VFMSUBADD231PDZrbk */ /* Table15861 */ 0x1432, /* VFMADD231PDZmbk */ 0x1438, /* VFMADD231PDZrbk */ /* Table15863 */ 0x165a, /* VFMSUB231PDZmbk */ 0x1660, /* VFMSUB231PDZrbk */ /* Table15865 */ 0x1882, /* VFNMADD231PDZmbk */ 0x1888, /* VFNMADD231PDZrbk */ /* Table15867 */ 0x19ce, /* VFNMSUB231PDZmbk */ 0x19d4, /* VFNMSUB231PDZrbk */ /* Table15869 */ 0x258a, /* VPCONFLICTQZrmbk */ 0x0, /* */ /* Table15871 */ 0x1288, /* VEXP2PDZmbk */ 0x128e, /* VEXP2PDZrbk */ /* Table15873 */ 0x3777, /* VRCP28PDZmbk */ 0x377d, /* VRCP28PDZrbk */ /* Table15875 */ 0x389b, /* VRSQRT28PDZmbk */ 0x38a1, /* VRSQRT28PDZrbk */ /* Table15877 */ 0x2715, /* VPERMILPSZ128rmbkz */ 0x0, /* */ /* Table15879 */ 0x0, /* */ 0xef9, /* VCVTPH2PSZrrbkz */ /* Table15881 */ 0x2fa3, /* VPRORVDZ128rmbkz */ 0x0, /* */ /* Table15883 */ 0x2f37, /* VPROLVDZ128rmbkz */ 0x0, /* */ /* Table15885 */ 0x2048, /* VPABSDZ128rmbkz */ 0x0, /* */ /* Table15887 */ 0x20cd, /* VPACKUSDWZ128rmbkz */ 0x0, /* */ /* Table15889 */ 0x38ec, /* VSCALEFPSZ128rmbkz */ 0x3904, /* VSCALEFPSZrrbkz */ /* Table15891 */ 0x0, /* */ 0x3916, /* VSCALEFSSZrrb_Intkz */ /* Table15893 */ 0x2a9a, /* VPMINSDZ128rmbkz */ 0x0, /* */ /* Table15895 */ 0x2b00, /* VPMINUDZ128rmbkz */ 0x0, /* */ /* Table15897 */ 0x29ce, /* VPMAXSDZ128rmbkz */ 0x0, /* */ /* Table15899 */ 0x2a34, /* VPMAXUDZ128rmbkz */ 0x0, /* */ /* Table15901 */ 0x2de1, /* VPMULLDZ128rmbkz */ 0x0, /* */ /* Table15903 */ 0x1ab1, /* VGETEXPPSZ128mbkz */ 0x1ac9, /* VGETEXPPSZrbkz */ /* Table15905 */ 0x0, /* */ 0x1adb, /* VGETEXPSSZrbkz */ /* Table15907 */ 0x28fe, /* VPLZCNTDZ128rmbkz */ 0x0, /* */ /* Table15909 */ 0x33ee, /* VPSRLVDZ128rmbkz */ 0x0, /* */ /* Table15911 */ 0x330a, /* VPSRAVDZ128rmbkz */ 0x0, /* */ /* Table15913 */ 0x3230, /* VPSLLVDZ128rmbkz */ 0x0, /* */ /* Table15915 */ 0x3751, /* VRCP14PSZ128mbkz */ 0x0, /* */ /* Table15917 */ 0x3875, /* VRSQRT14PSZ128mbkz */ 0x0, /* */ /* Table15919 */ 0x25af, /* VPDPBUSDZ128mbkz */ 0x0, /* */ /* Table15921 */ 0x2594, /* VPDPBUSDSZ128mbkz */ 0x0, /* */ /* Table15923 */ 0x25e5, /* VPDPWSSDZ128mbkz */ 0x0, /* */ /* Table15925 */ 0x25ca, /* VPDPWSSDSZ128mbkz */ 0x0, /* */ /* Table15927 */ 0x2e7b, /* VPOPCNTDZ128rmbkz */ 0x0, /* */ /* Table15929 */ 0x228e, /* VPBLENDMDZ128rmbkz */ 0x0, /* */ /* Table15931 */ 0xcbe, /* VBLENDMPSZ128rmbkz */ 0x0, /* */ /* Table15933 */ 0x3051, /* VPSHLDVDZ128mbkz */ 0x0, /* */ /* Table15935 */ 0x30ed, /* VPSHRDVDZ128mbkz */ 0x0, /* */ /* Table15937 */ 0x263c, /* VPERMI2D128rmbkz */ 0x0, /* */ /* Table15939 */ 0x2672, /* VPERMI2PS128rmbkz */ 0x0, /* */ /* Table15941 */ 0x27b8, /* VPERMT2D128rmbkz */ 0x0, /* */ /* Table15943 */ 0x27ee, /* VPERMT2PS128rmbkz */ 0x0, /* */ /* Table15945 */ 0x14c7, /* VFMADDSUB132PSZ128mbkz */ 0x14df, /* VFMADDSUB132PSZrbkz */ /* Table15947 */ 0x16cf, /* VFMSUBADD132PSZ128mbkz */ 0x16e7, /* VFMSUBADD132PSZrbkz */ /* Table15949 */ 0x137b, /* VFMADD132PSZ128mbkz */ 0x1393, /* VFMADD132PSZrbkz */ /* Table15951 */ 0x0, /* */ 0x13b3, /* VFMADD132SSZrb_Intkz */ /* Table15953 */ 0x15a3, /* VFMSUB132PSZ128mbkz */ 0x15bb, /* VFMSUB132PSZrbkz */ /* Table15955 */ 0x0, /* */ 0x15db, /* VFMSUB132SSZrb_Intkz */ /* Table15957 */ 0x17cb, /* VFNMADD132PSZ128mbkz */ 0x17e3, /* VFNMADD132PSZrbkz */ /* Table15959 */ 0x0, /* */ 0x1803, /* VFNMADD132SSZrb_Intkz */ /* Table15961 */ 0x1917, /* VFNMSUB132PSZ128mbkz */ 0x192f, /* VFNMSUB132PSZrbkz */ /* Table15963 */ 0x0, /* */ 0x194f, /* VFNMSUB132SSZrb_Intkz */ /* Table15965 */ 0x150b, /* VFMADDSUB213PSZ128mbkz */ 0x1523, /* VFMADDSUB213PSZrbkz */ /* Table15967 */ 0x1713, /* VFMSUBADD213PSZ128mbkz */ 0x172b, /* VFMSUBADD213PSZrbkz */ /* Table15969 */ 0x13df, /* VFMADD213PSZ128mbkz */ 0x13f7, /* VFMADD213PSZrbkz */ /* Table15971 */ 0x0, /* */ 0x1417, /* VFMADD213SSZrb_Intkz */ /* Table15973 */ 0x1607, /* VFMSUB213PSZ128mbkz */ 0x161f, /* VFMSUB213PSZrbkz */ /* Table15975 */ 0x0, /* */ 0x163f, /* VFMSUB213SSZrb_Intkz */ /* Table15977 */ 0x182f, /* VFNMADD213PSZ128mbkz */ 0x1847, /* VFNMADD213PSZrbkz */ /* Table15979 */ 0x0, /* */ 0x1867, /* VFNMADD213SSZrb_Intkz */ /* Table15981 */ 0x197b, /* VFNMSUB213PSZ128mbkz */ 0x1993, /* VFNMSUB213PSZrbkz */ /* Table15983 */ 0x0, /* */ 0x19b3, /* VFNMSUB213SSZrb_Intkz */ /* Table15985 */ 0x154f, /* VFMADDSUB231PSZ128mbkz */ 0x1567, /* VFMADDSUB231PSZrbkz */ /* Table15987 */ 0x1757, /* VFMSUBADD231PSZ128mbkz */ 0x176f, /* VFMSUBADD231PSZrbkz */ /* Table15989 */ 0x1443, /* VFMADD231PSZ128mbkz */ 0x145b, /* VFMADD231PSZrbkz */ /* Table15991 */ 0x0, /* */ 0x147b, /* VFMADD231SSZrb_Intkz */ /* Table15993 */ 0x166b, /* VFMSUB231PSZ128mbkz */ 0x1683, /* VFMSUB231PSZrbkz */ /* Table15995 */ 0x0, /* */ 0x16a3, /* VFMSUB231SSZrb_Intkz */ /* Table15997 */ 0x1893, /* VFNMADD231PSZ128mbkz */ 0x18ab, /* VFNMADD231PSZrbkz */ /* Table15999 */ 0x0, /* */ 0x18cb, /* VFNMADD231SSZrb_Intkz */ /* Table16001 */ 0x19df, /* VFNMSUB231PSZ128mbkz */ 0x19f7, /* VFNMSUB231PSZrbkz */ /* Table16003 */ 0x0, /* */ 0x1a17, /* VFNMSUB231SSZrb_Intkz */ /* Table16005 */ 0x255e, /* VPCONFLICTDZ128rmbkz */ 0x0, /* */ /* Table16007 */ 0x0, /* */ 0x129b, /* VEXP2PSZrbkz */ /* Table16009 */ 0x0, /* */ 0x378a, /* VRCP28PSZrbkz */ /* Table16011 */ 0x0, /* */ 0x379c, /* VRCP28SSZrbkz */ /* Table16013 */ 0x0, /* */ 0x38ae, /* VRSQRT28PSZrbkz */ /* Table16015 */ 0x0, /* */ 0x38c0, /* VRSQRT28SSZrbkz */ /* Table16017 */ 0x26d7, /* VPERMILPDZ128rmbkz */ 0x0, /* */ /* Table16019 */ 0x2fbe, /* VPRORVQZ128rmbkz */ 0x0, /* */ /* Table16021 */ 0x2f52, /* VPROLVQZ128rmbkz */ 0x0, /* */ /* Table16023 */ 0x2065, /* VPABSQZ128rmbkz */ 0x0, /* */ /* Table16025 */ 0x2d80, /* VPMULDQZ128rmbkz */ 0x0, /* */ /* Table16027 */ 0x38ce, /* VSCALEFPDZ128rmbkz */ 0x38e6, /* VSCALEFPDZrrbkz */ /* Table16029 */ 0x0, /* */ 0x390d, /* VSCALEFSDZrrb_Intkz */ /* Table16031 */ 0x2ab7, /* VPMINSQZ128rmbkz */ 0x0, /* */ /* Table16033 */ 0x2b1d, /* VPMINUQZ128rmbkz */ 0x0, /* */ /* Table16035 */ 0x29eb, /* VPMAXSQZ128rmbkz */ 0x0, /* */ /* Table16037 */ 0x2a51, /* VPMAXUQZ128rmbkz */ 0x0, /* */ /* Table16039 */ 0x2dfe, /* VPMULLQZ128rmbkz */ 0x0, /* */ /* Table16041 */ 0x1a93, /* VGETEXPPDZ128mbkz */ 0x1aab, /* VGETEXPPDZrbkz */ /* Table16043 */ 0x0, /* */ 0x1ad2, /* VGETEXPSDZrbkz */ /* Table16045 */ 0x2919, /* VPLZCNTQZ128rmbkz */ 0x0, /* */ /* Table16047 */ 0x340d, /* VPSRLVQZ128rmbkz */ 0x0, /* */ /* Table16049 */ 0x3327, /* VPSRAVQZ128rmbkz */ 0x0, /* */ /* Table16051 */ 0x324f, /* VPSLLVQZ128rmbkz */ 0x0, /* */ /* Table16053 */ 0x3736, /* VRCP14PDZ128mbkz */ 0x0, /* */ /* Table16055 */ 0x385a, /* VRSQRT14PDZ128mbkz */ 0x0, /* */ /* Table16057 */ 0x2e96, /* VPOPCNTQZ128rmbkz */ 0x0, /* */ /* Table16059 */ 0x22a9, /* VPBLENDMQZ128rmbkz */ 0x0, /* */ /* Table16061 */ 0xca3, /* VBLENDMPDZ128rmbkz */ 0x0, /* */ /* Table16063 */ 0x306c, /* VPSHLDVQZ128mbkz */ 0x0, /* */ /* Table16065 */ 0x3108, /* VPSHRDVQZ128mbkz */ 0x0, /* */ /* Table16067 */ 0x268d, /* VPERMI2Q128rmbkz */ 0x0, /* */ /* Table16069 */ 0x2657, /* VPERMI2PD128rmbkz */ 0x0, /* */ /* Table16071 */ 0x2809, /* VPERMT2Q128rmbkz */ 0x0, /* */ /* Table16073 */ 0x27d3, /* VPERMT2PD128rmbkz */ 0x0, /* */ /* Table16075 */ 0x2e2f, /* VPMULTISHIFTQBZ128rmbkz */ 0x0, /* */ /* Table16077 */ 0x14a5, /* VFMADDSUB132PDZ128mbkz */ 0x14bd, /* VFMADDSUB132PDZrbkz */ /* Table16079 */ 0x16ad, /* VFMSUBADD132PDZ128mbkz */ 0x16c5, /* VFMSUBADD132PDZrbkz */ /* Table16081 */ 0x1359, /* VFMADD132PDZ128mbkz */ 0x1371, /* VFMADD132PDZrbkz */ /* Table16083 */ 0x0, /* */ 0x13a3, /* VFMADD132SDZrb_Intkz */ /* Table16085 */ 0x1581, /* VFMSUB132PDZ128mbkz */ 0x1599, /* VFMSUB132PDZrbkz */ /* Table16087 */ 0x0, /* */ 0x15cb, /* VFMSUB132SDZrb_Intkz */ /* Table16089 */ 0x17a9, /* VFNMADD132PDZ128mbkz */ 0x17c1, /* VFNMADD132PDZrbkz */ /* Table16091 */ 0x0, /* */ 0x17f3, /* VFNMADD132SDZrb_Intkz */ /* Table16093 */ 0x18f5, /* VFNMSUB132PDZ128mbkz */ 0x190d, /* VFNMSUB132PDZrbkz */ /* Table16095 */ 0x0, /* */ 0x193f, /* VFNMSUB132SDZrb_Intkz */ /* Table16097 */ 0x14e9, /* VFMADDSUB213PDZ128mbkz */ 0x1501, /* VFMADDSUB213PDZrbkz */ /* Table16099 */ 0x16f1, /* VFMSUBADD213PDZ128mbkz */ 0x1709, /* VFMSUBADD213PDZrbkz */ /* Table16101 */ 0x13bd, /* VFMADD213PDZ128mbkz */ 0x13d5, /* VFMADD213PDZrbkz */ /* Table16103 */ 0x0, /* */ 0x1407, /* VFMADD213SDZrb_Intkz */ /* Table16105 */ 0x15e5, /* VFMSUB213PDZ128mbkz */ 0x15fd, /* VFMSUB213PDZrbkz */ /* Table16107 */ 0x0, /* */ 0x162f, /* VFMSUB213SDZrb_Intkz */ /* Table16109 */ 0x180d, /* VFNMADD213PDZ128mbkz */ 0x1825, /* VFNMADD213PDZrbkz */ /* Table16111 */ 0x0, /* */ 0x1857, /* VFNMADD213SDZrb_Intkz */ /* Table16113 */ 0x1959, /* VFNMSUB213PDZ128mbkz */ 0x1971, /* VFNMSUB213PDZrbkz */ /* Table16115 */ 0x0, /* */ 0x19a3, /* VFNMSUB213SDZrb_Intkz */ /* Table16117 */ 0x2967, /* VPMADD52LUQZ128mbkz */ 0x0, /* */ /* Table16119 */ 0x294c, /* VPMADD52HUQZ128mbkz */ 0x0, /* */ /* Table16121 */ 0x152d, /* VFMADDSUB231PDZ128mbkz */ 0x1545, /* VFMADDSUB231PDZrbkz */ /* Table16123 */ 0x1735, /* VFMSUBADD231PDZ128mbkz */ 0x174d, /* VFMSUBADD231PDZrbkz */ /* Table16125 */ 0x1421, /* VFMADD231PDZ128mbkz */ 0x1439, /* VFMADD231PDZrbkz */ /* Table16127 */ 0x0, /* */ 0x146b, /* VFMADD231SDZrb_Intkz */ /* Table16129 */ 0x1649, /* VFMSUB231PDZ128mbkz */ 0x1661, /* VFMSUB231PDZrbkz */ /* Table16131 */ 0x0, /* */ 0x1693, /* VFMSUB231SDZrb_Intkz */ /* Table16133 */ 0x1871, /* VFNMADD231PDZ128mbkz */ 0x1889, /* VFNMADD231PDZrbkz */ /* Table16135 */ 0x0, /* */ 0x18bb, /* VFNMADD231SDZrb_Intkz */ /* Table16137 */ 0x19bd, /* VFNMSUB231PDZ128mbkz */ 0x19d5, /* VFNMSUB231PDZrbkz */ /* Table16139 */ 0x0, /* */ 0x1a07, /* VFNMSUB231SDZrb_Intkz */ /* Table16141 */ 0x2579, /* VPCONFLICTQZ128rmbkz */ 0x0, /* */ /* Table16143 */ 0x0, /* */ 0x128f, /* VEXP2PDZrbkz */ /* Table16145 */ 0x0, /* */ 0x377e, /* VRCP28PDZrbkz */ /* Table16147 */ 0x0, /* */ 0x3793, /* VRCP28SDZrbkz */ /* Table16149 */ 0x0, /* */ 0x38a2, /* VRSQRT28PDZrbkz */ /* Table16151 */ 0x0, /* */ 0x38b7, /* VRSQRT28SDZrbkz */ /* Table16153 */ 0x2727, /* VPERMILPSZ256rmbkz */ 0x0, /* */ /* Table16155 */ 0x2fac, /* VPRORVDZ256rmbkz */ 0x0, /* */ /* Table16157 */ 0x2f40, /* VPROLVDZ256rmbkz */ 0x0, /* */ /* Table16159 */ 0x276e, /* VPERMPSZ256rmbkz */ 0x0, /* */ /* Table16161 */ 0x2051, /* VPABSDZ256rmbkz */ 0x0, /* */ /* Table16163 */ 0x20d6, /* VPACKUSDWZ256rmbkz */ 0x0, /* */ /* Table16165 */ 0x38f5, /* VSCALEFPSZ256rmbkz */ 0x3904, /* VSCALEFPSZrrbkz */ /* Table16167 */ 0x2618, /* VPERMDZ256rmbkz */ 0x0, /* */ /* Table16169 */ 0x2aa3, /* VPMINSDZ256rmbkz */ 0x0, /* */ /* Table16171 */ 0x2b09, /* VPMINUDZ256rmbkz */ 0x0, /* */ /* Table16173 */ 0x29d7, /* VPMAXSDZ256rmbkz */ 0x0, /* */ /* Table16175 */ 0x2a3d, /* VPMAXUDZ256rmbkz */ 0x0, /* */ /* Table16177 */ 0x2dea, /* VPMULLDZ256rmbkz */ 0x0, /* */ /* Table16179 */ 0x1aba, /* VGETEXPPSZ256mbkz */ 0x1ac9, /* VGETEXPPSZrbkz */ /* Table16181 */ 0x2907, /* VPLZCNTDZ256rmbkz */ 0x0, /* */ /* Table16183 */ 0x33f7, /* VPSRLVDZ256rmbkz */ 0x0, /* */ /* Table16185 */ 0x3313, /* VPSRAVDZ256rmbkz */ 0x0, /* */ /* Table16187 */ 0x3239, /* VPSLLVDZ256rmbkz */ 0x0, /* */ /* Table16189 */ 0x375a, /* VRCP14PSZ256mbkz */ 0x0, /* */ /* Table16191 */ 0x387e, /* VRSQRT14PSZ256mbkz */ 0x0, /* */ /* Table16193 */ 0x25b8, /* VPDPBUSDZ256mbkz */ 0x0, /* */ /* Table16195 */ 0x259d, /* VPDPBUSDSZ256mbkz */ 0x0, /* */ /* Table16197 */ 0x25ee, /* VPDPWSSDZ256mbkz */ 0x0, /* */ /* Table16199 */ 0x25d3, /* VPDPWSSDSZ256mbkz */ 0x0, /* */ /* Table16201 */ 0x2e84, /* VPOPCNTDZ256rmbkz */ 0x0, /* */ /* Table16203 */ 0x2297, /* VPBLENDMDZ256rmbkz */ 0x0, /* */ /* Table16205 */ 0xcc7, /* VBLENDMPSZ256rmbkz */ 0x0, /* */ /* Table16207 */ 0x305a, /* VPSHLDVDZ256mbkz */ 0x0, /* */ /* Table16209 */ 0x30f6, /* VPSHRDVDZ256mbkz */ 0x0, /* */ /* Table16211 */ 0x2645, /* VPERMI2D256rmbkz */ 0x0, /* */ /* Table16213 */ 0x267b, /* VPERMI2PS256rmbkz */ 0x0, /* */ /* Table16215 */ 0x27c1, /* VPERMT2D256rmbkz */ 0x0, /* */ /* Table16217 */ 0x27f7, /* VPERMT2PS256rmbkz */ 0x0, /* */ /* Table16219 */ 0x14d0, /* VFMADDSUB132PSZ256mbkz */ 0x14df, /* VFMADDSUB132PSZrbkz */ /* Table16221 */ 0x16d8, /* VFMSUBADD132PSZ256mbkz */ 0x16e7, /* VFMSUBADD132PSZrbkz */ /* Table16223 */ 0x1384, /* VFMADD132PSZ256mbkz */ 0x1393, /* VFMADD132PSZrbkz */ /* Table16225 */ 0x15ac, /* VFMSUB132PSZ256mbkz */ 0x15bb, /* VFMSUB132PSZrbkz */ /* Table16227 */ 0x17d4, /* VFNMADD132PSZ256mbkz */ 0x17e3, /* VFNMADD132PSZrbkz */ /* Table16229 */ 0x1920, /* VFNMSUB132PSZ256mbkz */ 0x192f, /* VFNMSUB132PSZrbkz */ /* Table16231 */ 0x1514, /* VFMADDSUB213PSZ256mbkz */ 0x1523, /* VFMADDSUB213PSZrbkz */ /* Table16233 */ 0x171c, /* VFMSUBADD213PSZ256mbkz */ 0x172b, /* VFMSUBADD213PSZrbkz */ /* Table16235 */ 0x13e8, /* VFMADD213PSZ256mbkz */ 0x13f7, /* VFMADD213PSZrbkz */ /* Table16237 */ 0x1610, /* VFMSUB213PSZ256mbkz */ 0x161f, /* VFMSUB213PSZrbkz */ /* Table16239 */ 0x1838, /* VFNMADD213PSZ256mbkz */ 0x1847, /* VFNMADD213PSZrbkz */ /* Table16241 */ 0x1984, /* VFNMSUB213PSZ256mbkz */ 0x1993, /* VFNMSUB213PSZrbkz */ /* Table16243 */ 0x1558, /* VFMADDSUB231PSZ256mbkz */ 0x1567, /* VFMADDSUB231PSZrbkz */ /* Table16245 */ 0x1760, /* VFMSUBADD231PSZ256mbkz */ 0x176f, /* VFMSUBADD231PSZrbkz */ /* Table16247 */ 0x144c, /* VFMADD231PSZ256mbkz */ 0x145b, /* VFMADD231PSZrbkz */ /* Table16249 */ 0x1674, /* VFMSUB231PSZ256mbkz */ 0x1683, /* VFMSUB231PSZrbkz */ /* Table16251 */ 0x189c, /* VFNMADD231PSZ256mbkz */ 0x18ab, /* VFNMADD231PSZrbkz */ /* Table16253 */ 0x19e8, /* VFNMSUB231PSZ256mbkz */ 0x19f7, /* VFNMSUB231PSZrbkz */ /* Table16255 */ 0x2567, /* VPCONFLICTDZ256rmbkz */ 0x0, /* */ /* Table16257 */ 0x26e9, /* VPERMILPDZ256rmbkz */ 0x0, /* */ /* Table16259 */ 0x2fc7, /* VPRORVQZ256rmbkz */ 0x0, /* */ /* Table16261 */ 0x2f5b, /* VPROLVQZ256rmbkz */ 0x0, /* */ /* Table16263 */ 0x2751, /* VPERMPDZ256rmbkz */ 0x0, /* */ /* Table16265 */ 0x206e, /* VPABSQZ256rmbkz */ 0x0, /* */ /* Table16267 */ 0x2d89, /* VPMULDQZ256rmbkz */ 0x0, /* */ /* Table16269 */ 0x38d7, /* VSCALEFPDZ256rmbkz */ 0x38e6, /* VSCALEFPDZrrbkz */ /* Table16271 */ 0x278b, /* VPERMQZ256rmbkz */ 0x0, /* */ /* Table16273 */ 0x2ac0, /* VPMINSQZ256rmbkz */ 0x0, /* */ /* Table16275 */ 0x2b26, /* VPMINUQZ256rmbkz */ 0x0, /* */ /* Table16277 */ 0x29f4, /* VPMAXSQZ256rmbkz */ 0x0, /* */ /* Table16279 */ 0x2a5a, /* VPMAXUQZ256rmbkz */ 0x0, /* */ /* Table16281 */ 0x2e07, /* VPMULLQZ256rmbkz */ 0x0, /* */ /* Table16283 */ 0x1a9c, /* VGETEXPPDZ256mbkz */ 0x1aab, /* VGETEXPPDZrbkz */ /* Table16285 */ 0x2922, /* VPLZCNTQZ256rmbkz */ 0x0, /* */ /* Table16287 */ 0x3416, /* VPSRLVQZ256rmbkz */ 0x0, /* */ /* Table16289 */ 0x3330, /* VPSRAVQZ256rmbkz */ 0x0, /* */ /* Table16291 */ 0x3258, /* VPSLLVQZ256rmbkz */ 0x0, /* */ /* Table16293 */ 0x373f, /* VRCP14PDZ256mbkz */ 0x0, /* */ /* Table16295 */ 0x3863, /* VRSQRT14PDZ256mbkz */ 0x0, /* */ /* Table16297 */ 0x2e9f, /* VPOPCNTQZ256rmbkz */ 0x0, /* */ /* Table16299 */ 0x22b2, /* VPBLENDMQZ256rmbkz */ 0x0, /* */ /* Table16301 */ 0xcac, /* VBLENDMPDZ256rmbkz */ 0x0, /* */ /* Table16303 */ 0x3075, /* VPSHLDVQZ256mbkz */ 0x0, /* */ /* Table16305 */ 0x3111, /* VPSHRDVQZ256mbkz */ 0x0, /* */ /* Table16307 */ 0x2696, /* VPERMI2Q256rmbkz */ 0x0, /* */ /* Table16309 */ 0x2660, /* VPERMI2PD256rmbkz */ 0x0, /* */ /* Table16311 */ 0x2812, /* VPERMT2Q256rmbkz */ 0x0, /* */ /* Table16313 */ 0x27dc, /* VPERMT2PD256rmbkz */ 0x0, /* */ /* Table16315 */ 0x2e38, /* VPMULTISHIFTQBZ256rmbkz */ 0x0, /* */ /* Table16317 */ 0x14ae, /* VFMADDSUB132PDZ256mbkz */ 0x14bd, /* VFMADDSUB132PDZrbkz */ /* Table16319 */ 0x16b6, /* VFMSUBADD132PDZ256mbkz */ 0x16c5, /* VFMSUBADD132PDZrbkz */ /* Table16321 */ 0x1362, /* VFMADD132PDZ256mbkz */ 0x1371, /* VFMADD132PDZrbkz */ /* Table16323 */ 0x158a, /* VFMSUB132PDZ256mbkz */ 0x1599, /* VFMSUB132PDZrbkz */ /* Table16325 */ 0x17b2, /* VFNMADD132PDZ256mbkz */ 0x17c1, /* VFNMADD132PDZrbkz */ /* Table16327 */ 0x18fe, /* VFNMSUB132PDZ256mbkz */ 0x190d, /* VFNMSUB132PDZrbkz */ /* Table16329 */ 0x14f2, /* VFMADDSUB213PDZ256mbkz */ 0x1501, /* VFMADDSUB213PDZrbkz */ /* Table16331 */ 0x16fa, /* VFMSUBADD213PDZ256mbkz */ 0x1709, /* VFMSUBADD213PDZrbkz */ /* Table16333 */ 0x13c6, /* VFMADD213PDZ256mbkz */ 0x13d5, /* VFMADD213PDZrbkz */ /* Table16335 */ 0x15ee, /* VFMSUB213PDZ256mbkz */ 0x15fd, /* VFMSUB213PDZrbkz */ /* Table16337 */ 0x1816, /* VFNMADD213PDZ256mbkz */ 0x1825, /* VFNMADD213PDZrbkz */ /* Table16339 */ 0x1962, /* VFNMSUB213PDZ256mbkz */ 0x1971, /* VFNMSUB213PDZrbkz */ /* Table16341 */ 0x2970, /* VPMADD52LUQZ256mbkz */ 0x0, /* */ /* Table16343 */ 0x2955, /* VPMADD52HUQZ256mbkz */ 0x0, /* */ /* Table16345 */ 0x1536, /* VFMADDSUB231PDZ256mbkz */ 0x1545, /* VFMADDSUB231PDZrbkz */ /* Table16347 */ 0x173e, /* VFMSUBADD231PDZ256mbkz */ 0x174d, /* VFMSUBADD231PDZrbkz */ /* Table16349 */ 0x142a, /* VFMADD231PDZ256mbkz */ 0x1439, /* VFMADD231PDZrbkz */ /* Table16351 */ 0x1652, /* VFMSUB231PDZ256mbkz */ 0x1661, /* VFMSUB231PDZrbkz */ /* Table16353 */ 0x187a, /* VFNMADD231PDZ256mbkz */ 0x1889, /* VFNMADD231PDZrbkz */ /* Table16355 */ 0x19c6, /* VFNMSUB231PDZ256mbkz */ 0x19d5, /* VFNMSUB231PDZrbkz */ /* Table16357 */ 0x2582, /* VPCONFLICTQZ256rmbkz */ 0x0, /* */ /* Table16359 */ 0x2739, /* VPERMILPSZrmbkz */ 0x0, /* */ /* Table16361 */ 0x2fb5, /* VPRORVDZrmbkz */ 0x0, /* */ /* Table16363 */ 0x2f49, /* VPROLVDZrmbkz */ 0x0, /* */ /* Table16365 */ 0x2777, /* VPERMPSZrmbkz */ 0x0, /* */ /* Table16367 */ 0x205a, /* VPABSDZrmbkz */ 0x0, /* */ /* Table16369 */ 0x20df, /* VPACKUSDWZrmbkz */ 0x0, /* */ /* Table16371 */ 0x38fe, /* VSCALEFPSZrmbkz */ 0x3904, /* VSCALEFPSZrrbkz */ /* Table16373 */ 0x2621, /* VPERMDZrmbkz */ 0x0, /* */ /* Table16375 */ 0x2aac, /* VPMINSDZrmbkz */ 0x0, /* */ /* Table16377 */ 0x2b12, /* VPMINUDZrmbkz */ 0x0, /* */ /* Table16379 */ 0x29e0, /* VPMAXSDZrmbkz */ 0x0, /* */ /* Table16381 */ 0x2a46, /* VPMAXUDZrmbkz */ 0x0, /* */ /* Table16383 */ 0x2df3, /* VPMULLDZrmbkz */ 0x0, /* */ /* Table16385 */ 0x1ac3, /* VGETEXPPSZmbkz */ 0x1ac9, /* VGETEXPPSZrbkz */ /* Table16387 */ 0x2910, /* VPLZCNTDZrmbkz */ 0x0, /* */ /* Table16389 */ 0x3400, /* VPSRLVDZrmbkz */ 0x0, /* */ /* Table16391 */ 0x331c, /* VPSRAVDZrmbkz */ 0x0, /* */ /* Table16393 */ 0x3242, /* VPSLLVDZrmbkz */ 0x0, /* */ /* Table16395 */ 0x3763, /* VRCP14PSZmbkz */ 0x0, /* */ /* Table16397 */ 0x3887, /* VRSQRT14PSZmbkz */ 0x0, /* */ /* Table16399 */ 0x25c1, /* VPDPBUSDZmbkz */ 0x0, /* */ /* Table16401 */ 0x25a6, /* VPDPBUSDSZmbkz */ 0x0, /* */ /* Table16403 */ 0x25f7, /* VPDPWSSDZmbkz */ 0x0, /* */ /* Table16405 */ 0x25dc, /* VPDPWSSDSZmbkz */ 0x0, /* */ /* Table16407 */ 0x2e8d, /* VPOPCNTDZrmbkz */ 0x0, /* */ /* Table16409 */ 0x22a0, /* VPBLENDMDZrmbkz */ 0x0, /* */ /* Table16411 */ 0xcd0, /* VBLENDMPSZrmbkz */ 0x0, /* */ /* Table16413 */ 0x3063, /* VPSHLDVDZmbkz */ 0x0, /* */ /* Table16415 */ 0x30ff, /* VPSHRDVDZmbkz */ 0x0, /* */ /* Table16417 */ 0x264e, /* VPERMI2Drmbkz */ 0x0, /* */ /* Table16419 */ 0x2684, /* VPERMI2PSrmbkz */ 0x0, /* */ /* Table16421 */ 0x27ca, /* VPERMT2Drmbkz */ 0x0, /* */ /* Table16423 */ 0x2800, /* VPERMT2PSrmbkz */ 0x0, /* */ /* Table16425 */ 0x14d9, /* VFMADDSUB132PSZmbkz */ 0x14df, /* VFMADDSUB132PSZrbkz */ /* Table16427 */ 0x16e1, /* VFMSUBADD132PSZmbkz */ 0x16e7, /* VFMSUBADD132PSZrbkz */ /* Table16429 */ 0x138d, /* VFMADD132PSZmbkz */ 0x1393, /* VFMADD132PSZrbkz */ /* Table16431 */ 0x15b5, /* VFMSUB132PSZmbkz */ 0x15bb, /* VFMSUB132PSZrbkz */ /* Table16433 */ 0x17dd, /* VFNMADD132PSZmbkz */ 0x17e3, /* VFNMADD132PSZrbkz */ /* Table16435 */ 0x1929, /* VFNMSUB132PSZmbkz */ 0x192f, /* VFNMSUB132PSZrbkz */ /* Table16437 */ 0x151d, /* VFMADDSUB213PSZmbkz */ 0x1523, /* VFMADDSUB213PSZrbkz */ /* Table16439 */ 0x1725, /* VFMSUBADD213PSZmbkz */ 0x172b, /* VFMSUBADD213PSZrbkz */ /* Table16441 */ 0x13f1, /* VFMADD213PSZmbkz */ 0x13f7, /* VFMADD213PSZrbkz */ /* Table16443 */ 0x1619, /* VFMSUB213PSZmbkz */ 0x161f, /* VFMSUB213PSZrbkz */ /* Table16445 */ 0x1841, /* VFNMADD213PSZmbkz */ 0x1847, /* VFNMADD213PSZrbkz */ /* Table16447 */ 0x198d, /* VFNMSUB213PSZmbkz */ 0x1993, /* VFNMSUB213PSZrbkz */ /* Table16449 */ 0x1561, /* VFMADDSUB231PSZmbkz */ 0x1567, /* VFMADDSUB231PSZrbkz */ /* Table16451 */ 0x1769, /* VFMSUBADD231PSZmbkz */ 0x176f, /* VFMSUBADD231PSZrbkz */ /* Table16453 */ 0x1455, /* VFMADD231PSZmbkz */ 0x145b, /* VFMADD231PSZrbkz */ /* Table16455 */ 0x167d, /* VFMSUB231PSZmbkz */ 0x1683, /* VFMSUB231PSZrbkz */ /* Table16457 */ 0x18a5, /* VFNMADD231PSZmbkz */ 0x18ab, /* VFNMADD231PSZrbkz */ /* Table16459 */ 0x19f1, /* VFNMSUB231PSZmbkz */ 0x19f7, /* VFNMSUB231PSZrbkz */ /* Table16461 */ 0x2570, /* VPCONFLICTDZrmbkz */ 0x0, /* */ /* Table16463 */ 0x1295, /* VEXP2PSZmbkz */ 0x129b, /* VEXP2PSZrbkz */ /* Table16465 */ 0x3784, /* VRCP28PSZmbkz */ 0x378a, /* VRCP28PSZrbkz */ /* Table16467 */ 0x38a8, /* VRSQRT28PSZmbkz */ 0x38ae, /* VRSQRT28PSZrbkz */ /* Table16469 */ 0x26fb, /* VPERMILPDZrmbkz */ 0x0, /* */ /* Table16471 */ 0x2fd0, /* VPRORVQZrmbkz */ 0x0, /* */ /* Table16473 */ 0x2f64, /* VPROLVQZrmbkz */ 0x0, /* */ /* Table16475 */ 0x2763, /* VPERMPDZrmbkz */ 0x0, /* */ /* Table16477 */ 0x2077, /* VPABSQZrmbkz */ 0x0, /* */ /* Table16479 */ 0x2d92, /* VPMULDQZrmbkz */ 0x0, /* */ /* Table16481 */ 0x38e0, /* VSCALEFPDZrmbkz */ 0x38e6, /* VSCALEFPDZrrbkz */ /* Table16483 */ 0x279d, /* VPERMQZrmbkz */ 0x0, /* */ /* Table16485 */ 0x2ac9, /* VPMINSQZrmbkz */ 0x0, /* */ /* Table16487 */ 0x2b2f, /* VPMINUQZrmbkz */ 0x0, /* */ /* Table16489 */ 0x29fd, /* VPMAXSQZrmbkz */ 0x0, /* */ /* Table16491 */ 0x2a63, /* VPMAXUQZrmbkz */ 0x0, /* */ /* Table16493 */ 0x2e10, /* VPMULLQZrmbkz */ 0x0, /* */ /* Table16495 */ 0x1aa5, /* VGETEXPPDZmbkz */ 0x1aab, /* VGETEXPPDZrbkz */ /* Table16497 */ 0x292b, /* VPLZCNTQZrmbkz */ 0x0, /* */ /* Table16499 */ 0x341f, /* VPSRLVQZrmbkz */ 0x0, /* */ /* Table16501 */ 0x3339, /* VPSRAVQZrmbkz */ 0x0, /* */ /* Table16503 */ 0x3261, /* VPSLLVQZrmbkz */ 0x0, /* */ /* Table16505 */ 0x3748, /* VRCP14PDZmbkz */ 0x0, /* */ /* Table16507 */ 0x386c, /* VRSQRT14PDZmbkz */ 0x0, /* */ /* Table16509 */ 0x2ea8, /* VPOPCNTQZrmbkz */ 0x0, /* */ /* Table16511 */ 0x22bb, /* VPBLENDMQZrmbkz */ 0x0, /* */ /* Table16513 */ 0xcb5, /* VBLENDMPDZrmbkz */ 0x0, /* */ /* Table16515 */ 0x307e, /* VPSHLDVQZmbkz */ 0x0, /* */ /* Table16517 */ 0x311a, /* VPSHRDVQZmbkz */ 0x0, /* */ /* Table16519 */ 0x269f, /* VPERMI2Qrmbkz */ 0x0, /* */ /* Table16521 */ 0x2669, /* VPERMI2PDrmbkz */ 0x0, /* */ /* Table16523 */ 0x281b, /* VPERMT2Qrmbkz */ 0x0, /* */ /* Table16525 */ 0x27e5, /* VPERMT2PDrmbkz */ 0x0, /* */ /* Table16527 */ 0x2e41, /* VPMULTISHIFTQBZrmbkz */ 0x0, /* */ /* Table16529 */ 0x14b7, /* VFMADDSUB132PDZmbkz */ 0x14bd, /* VFMADDSUB132PDZrbkz */ /* Table16531 */ 0x16bf, /* VFMSUBADD132PDZmbkz */ 0x16c5, /* VFMSUBADD132PDZrbkz */ /* Table16533 */ 0x136b, /* VFMADD132PDZmbkz */ 0x1371, /* VFMADD132PDZrbkz */ /* Table16535 */ 0x1593, /* VFMSUB132PDZmbkz */ 0x1599, /* VFMSUB132PDZrbkz */ /* Table16537 */ 0x17bb, /* VFNMADD132PDZmbkz */ 0x17c1, /* VFNMADD132PDZrbkz */ /* Table16539 */ 0x1907, /* VFNMSUB132PDZmbkz */ 0x190d, /* VFNMSUB132PDZrbkz */ /* Table16541 */ 0x14fb, /* VFMADDSUB213PDZmbkz */ 0x1501, /* VFMADDSUB213PDZrbkz */ /* Table16543 */ 0x1703, /* VFMSUBADD213PDZmbkz */ 0x1709, /* VFMSUBADD213PDZrbkz */ /* Table16545 */ 0x13cf, /* VFMADD213PDZmbkz */ 0x13d5, /* VFMADD213PDZrbkz */ /* Table16547 */ 0x15f7, /* VFMSUB213PDZmbkz */ 0x15fd, /* VFMSUB213PDZrbkz */ /* Table16549 */ 0x181f, /* VFNMADD213PDZmbkz */ 0x1825, /* VFNMADD213PDZrbkz */ /* Table16551 */ 0x196b, /* VFNMSUB213PDZmbkz */ 0x1971, /* VFNMSUB213PDZrbkz */ /* Table16553 */ 0x2979, /* VPMADD52LUQZmbkz */ 0x0, /* */ /* Table16555 */ 0x295e, /* VPMADD52HUQZmbkz */ 0x0, /* */ /* Table16557 */ 0x153f, /* VFMADDSUB231PDZmbkz */ 0x1545, /* VFMADDSUB231PDZrbkz */ /* Table16559 */ 0x1747, /* VFMSUBADD231PDZmbkz */ 0x174d, /* VFMSUBADD231PDZrbkz */ /* Table16561 */ 0x1433, /* VFMADD231PDZmbkz */ 0x1439, /* VFMADD231PDZrbkz */ /* Table16563 */ 0x165b, /* VFMSUB231PDZmbkz */ 0x1661, /* VFMSUB231PDZrbkz */ /* Table16565 */ 0x1883, /* VFNMADD231PDZmbkz */ 0x1889, /* VFNMADD231PDZrbkz */ /* Table16567 */ 0x19cf, /* VFNMSUB231PDZmbkz */ 0x19d5, /* VFNMSUB231PDZrbkz */ /* Table16569 */ 0x258b, /* VPCONFLICTQZrmbkz */ 0x0, /* */ /* Table16571 */ 0x1289, /* VEXP2PDZmbkz */ 0x128f, /* VEXP2PDZrbkz */ /* Table16573 */ 0x3778, /* VRCP28PDZmbkz */ 0x377e, /* VRCP28PDZrbkz */ /* Table16575 */ 0x389c, /* VRSQRT28PDZmbkz */ 0x38a2, /* VRSQRT28PDZrbkz */ /* Table16577 */ 0x0, /* */ 0x2cda, /* VPMOVUSWBZ128rrkz */ /* Table16579 */ 0x0, /* */ 0x2c8f, /* VPMOVUSDBZ128rrkz */ /* Table16581 */ 0x0, /* */ 0x2cad, /* VPMOVUSQBZ128rrkz */ /* Table16583 */ 0x0, /* */ 0x2c9e, /* VPMOVUSDWZ128rrkz */ /* Table16585 */ 0x0, /* */ 0x2ccb, /* VPMOVUSQWZ128rrkz */ /* Table16587 */ 0x0, /* */ 0x2cbc, /* VPMOVUSQDZ128rrkz */ /* Table16589 */ 0x0, /* */ 0x2bfc, /* VPMOVSWBZ128rrkz */ /* Table16591 */ 0x0, /* */ 0x2bb1, /* VPMOVSDBZ128rrkz */ /* Table16593 */ 0x0, /* */ 0x2bcf, /* VPMOVSQBZ128rrkz */ /* Table16595 */ 0x0, /* */ 0x2bc0, /* VPMOVSDWZ128rrkz */ /* Table16597 */ 0x0, /* */ 0x2bed, /* VPMOVSQWZ128rrkz */ /* Table16599 */ 0x0, /* */ 0x2bde, /* VPMOVSQDZ128rrkz */ /* Table16601 */ 0x0, /* */ 0x2cec, /* VPMOVWBZ128rrkz */ /* Table16603 */ 0x0, /* */ 0x2b55, /* VPMOVDBZ128rrkz */ /* Table16605 */ 0x0, /* */ 0x2b84, /* VPMOVQBZ128rrkz */ /* Table16607 */ 0x0, /* */ 0x2b64, /* VPMOVDWZ128rrkz */ /* Table16609 */ 0x0, /* */ 0x2ba2, /* VPMOVQWZ128rrkz */ /* Table16611 */ 0x0, /* */ 0x2b93, /* VPMOVQDZ128rrkz */ /* Table16613 */ 0xb51, /* V4FMADDSSrmkz */ 0x0, /* */ /* Table16615 */ 0xb57, /* V4FNMADDSSrmkz */ 0x0, /* */ /* Table16617 */ 0x3154, /* VPSHUFBZ128rmkz */ 0x3157, /* VPSHUFBZ128rrkz */ /* Table16619 */ 0x2983, /* VPMADDUBSWZ128rmkz */ 0x2986, /* VPMADDUBSWZ128rrkz */ /* Table16621 */ 0x2d9e, /* VPMULHRSWZ128rmkz */ 0x2da1, /* VPMULHRSWZ128rrkz */ /* Table16623 */ 0x2717, /* VPERMILPSZ128rmkz */ 0x271a, /* VPERMILPSZ128rrkz */ /* Table16625 */ 0xee9, /* VCVTPH2PSZ128rmkz */ 0xeec, /* VCVTPH2PSZ128rrkz */ /* Table16627 */ 0x2fa5, /* VPRORVDZ128rmkz */ 0x2fa8, /* VPRORVDZ128rrkz */ /* Table16629 */ 0x2f39, /* VPROLVDZ128rmkz */ 0x2f3c, /* VPROLVDZ128rrkz */ /* Table16631 */ 0xd3c, /* VBROADCASTSSZ128mkz */ 0xd3f, /* VBROADCASTSSZ128rkz */ /* Table16633 */ 0x2031, /* VPABSBZ128rmkz */ 0x2034, /* VPABSBZ128rrkz */ /* Table16635 */ 0x2081, /* VPABSWZ128rmkz */ 0x2084, /* VPABSWZ128rrkz */ /* Table16637 */ 0x204a, /* VPABSDZ128rmkz */ 0x204d, /* VPABSDZ128rrkz */ /* Table16639 */ 0x2c37, /* VPMOVSXBWZ128rmkz */ 0x2c3a, /* VPMOVSXBWZ128rrkz */ /* Table16641 */ 0x2c0b, /* VPMOVSXBDZ128rmkz */ 0x2c0e, /* VPMOVSXBDZ128rrkz */ /* Table16643 */ 0x2c21, /* VPMOVSXBQZ128rmkz */ 0x2c24, /* VPMOVSXBQZ128rrkz */ /* Table16645 */ 0x2c63, /* VPMOVSXWDZ128rmkz */ 0x2c66, /* VPMOVSXWDZ128rrkz */ /* Table16647 */ 0x2c79, /* VPMOVSXWQZ128rmkz */ 0x2c7c, /* VPMOVSXWQZ128rrkz */ /* Table16649 */ 0x2c4d, /* VPMOVSXDQZ128rmkz */ 0x2c50, /* VPMOVSXDQZ128rrkz */ /* Table16651 */ 0x20cf, /* VPACKUSDWZ128rmkz */ 0x20d2, /* VPACKUSDWZ128rrkz */ /* Table16653 */ 0x38ee, /* VSCALEFPSZ128rmkz */ 0x38f1, /* VSCALEFPSZ128rrkz */ /* Table16655 */ 0x3912, /* VSCALEFSSZrmkz */ 0x3918, /* VSCALEFSSZrrkz */ /* Table16657 */ 0x2d27, /* VPMOVZXBWZ128rmkz */ 0x2d2a, /* VPMOVZXBWZ128rrkz */ /* Table16659 */ 0x2cfb, /* VPMOVZXBDZ128rmkz */ 0x2cfe, /* VPMOVZXBDZ128rrkz */ /* Table16661 */ 0x2d11, /* VPMOVZXBQZ128rmkz */ 0x2d14, /* VPMOVZXBQZ128rrkz */ /* Table16663 */ 0x2d53, /* VPMOVZXWDZ128rmkz */ 0x2d56, /* VPMOVZXWDZ128rrkz */ /* Table16665 */ 0x2d69, /* VPMOVZXWQZ128rmkz */ 0x2d6c, /* VPMOVZXWQZ128rrkz */ /* Table16667 */ 0x2d3d, /* VPMOVZXDQZ128rmkz */ 0x2d40, /* VPMOVZXDQZ128rrkz */ /* Table16669 */ 0x2a83, /* VPMINSBZ128rmkz */ 0x2a86, /* VPMINSBZ128rrkz */ /* Table16671 */ 0x2a9c, /* VPMINSDZ128rmkz */ 0x2a9f, /* VPMINSDZ128rrkz */ /* Table16673 */ 0x2b39, /* VPMINUWZ128rmkz */ 0x2b3c, /* VPMINUWZ128rrkz */ /* Table16675 */ 0x2b02, /* VPMINUDZ128rmkz */ 0x2b05, /* VPMINUDZ128rrkz */ /* Table16677 */ 0x29b7, /* VPMAXSBZ128rmkz */ 0x29ba, /* VPMAXSBZ128rrkz */ /* Table16679 */ 0x29d0, /* VPMAXSDZ128rmkz */ 0x29d3, /* VPMAXSDZ128rrkz */ /* Table16681 */ 0x2a6d, /* VPMAXUWZ128rmkz */ 0x2a70, /* VPMAXUWZ128rrkz */ /* Table16683 */ 0x2a36, /* VPMAXUDZ128rmkz */ 0x2a39, /* VPMAXUDZ128rrkz */ /* Table16685 */ 0x2de3, /* VPMULLDZ128rmkz */ 0x2de6, /* VPMULLDZ128rrkz */ /* Table16687 */ 0x1ab3, /* VGETEXPPSZ128mkz */ 0x1ab6, /* VGETEXPPSZ128rkz */ /* Table16689 */ 0x1ad7, /* VGETEXPSSZmkz */ 0x1add, /* VGETEXPSSZrkz */ /* Table16691 */ 0x2900, /* VPLZCNTDZ128rmkz */ 0x2903, /* VPLZCNTDZ128rrkz */ /* Table16693 */ 0x33f0, /* VPSRLVDZ128rmkz */ 0x33f3, /* VPSRLVDZ128rrkz */ /* Table16695 */ 0x330c, /* VPSRAVDZ128rmkz */ 0x330f, /* VPSRAVDZ128rrkz */ /* Table16697 */ 0x3232, /* VPSLLVDZ128rmkz */ 0x3235, /* VPSLLVDZ128rrkz */ /* Table16699 */ 0x3753, /* VRCP14PSZ128mkz */ 0x3756, /* VRCP14PSZ128rkz */ /* Table16701 */ 0x3771, /* VRCP14SSZrmkz */ 0x3774, /* VRCP14SSZrrkz */ /* Table16703 */ 0x3877, /* VRSQRT14PSZ128mkz */ 0x387a, /* VRSQRT14PSZ128rkz */ /* Table16705 */ 0x3895, /* VRSQRT14SSZrmkz */ 0x3898, /* VRSQRT14SSZrrkz */ /* Table16707 */ 0x25b1, /* VPDPBUSDZ128mkz */ 0x25b4, /* VPDPBUSDZ128rkz */ /* Table16709 */ 0x2596, /* VPDPBUSDSZ128mkz */ 0x2599, /* VPDPBUSDSZ128rkz */ /* Table16711 */ 0x25e7, /* VPDPWSSDZ128mkz */ 0x25ea, /* VPDPWSSDZ128rkz */ /* Table16713 */ 0x25cc, /* VPDPWSSDSZ128mkz */ 0x25cf, /* VPDPWSSDSZ128rkz */ /* Table16715 */ 0x2e68, /* VPOPCNTBZ128rmkz */ 0x2e6b, /* VPOPCNTBZ128rrkz */ /* Table16717 */ 0x2e7d, /* VPOPCNTDZ128rmkz */ 0x2e80, /* VPOPCNTDZ128rrkz */ /* Table16719 */ 0x22fe, /* VPBROADCASTDZ128mkz */ 0x2301, /* VPBROADCASTDZ128rkz */ /* Table16721 */ 0xd08, /* VBROADCASTI32X2Z128mkz */ 0xd0b, /* VBROADCASTI32X2Z128rkz */ /* Table16723 */ 0x2847, /* VPEXPANDBZ128rmkz */ 0x284a, /* VPEXPANDBZ128rrkz */ /* Table16725 */ 0x0, /* */ 0x250b, /* VPCOMPRESSBZ128rrkz */ /* Table16727 */ 0x2290, /* VPBLENDMDZ128rmkz */ 0x2293, /* VPBLENDMDZ128rrkz */ /* Table16729 */ 0xcc0, /* VBLENDMPSZ128rmkz */ 0xcc3, /* VBLENDMPSZ128rrkz */ /* Table16731 */ 0x227b, /* VPBLENDMBZ128rmkz */ 0x227e, /* VPBLENDMBZ128rrkz */ /* Table16733 */ 0x3053, /* VPSHLDVDZ128mkz */ 0x3056, /* VPSHLDVDZ128rkz */ /* Table16735 */ 0x30ef, /* VPSHRDVDZ128mkz */ 0x30f2, /* VPSHRDVDZ128rkz */ /* Table16737 */ 0x2629, /* VPERMI2B128rmkz */ 0x262c, /* VPERMI2B128rrkz */ /* Table16739 */ 0x263e, /* VPERMI2D128rmkz */ 0x2641, /* VPERMI2D128rrkz */ /* Table16741 */ 0x2674, /* VPERMI2PS128rmkz */ 0x2677, /* VPERMI2PS128rrkz */ /* Table16743 */ 0x22df, /* VPBROADCASTBZ128mkz */ 0x22e2, /* VPBROADCASTBZ128rkz */ /* Table16745 */ 0x2342, /* VPBROADCASTWZ128mkz */ 0x2345, /* VPBROADCASTWZ128rkz */ /* Table16747 */ 0x0, /* */ 0x22f1, /* VPBROADCASTBrZ128rkz */ /* Table16749 */ 0x0, /* */ 0x2354, /* VPBROADCASTWrZ128rkz */ /* Table16751 */ 0x0, /* */ 0x2310, /* VPBROADCASTDrZ128rkz */ /* Table16753 */ 0x27a5, /* VPERMT2B128rmkz */ 0x27a8, /* VPERMT2B128rrkz */ /* Table16755 */ 0x27ba, /* VPERMT2D128rmkz */ 0x27bd, /* VPERMT2D128rrkz */ /* Table16757 */ 0x27f0, /* VPERMT2PS128rmkz */ 0x27f3, /* VPERMT2PS128rrkz */ /* Table16759 */ 0x12b2, /* VEXPANDPSZ128rmkz */ 0x12b5, /* VEXPANDPSZ128rrkz */ /* Table16761 */ 0x2859, /* VPEXPANDDZ128rmkz */ 0x285c, /* VPEXPANDDZ128rrkz */ /* Table16763 */ 0x0, /* */ 0xdfb, /* VCOMPRESSPSZ128rrkz */ /* Table16765 */ 0x0, /* */ 0x251a, /* VPCOMPRESSDZ128rrkz */ /* Table16767 */ 0x2603, /* VPERMBZ128rmkz */ 0x2606, /* VPERMBZ128rrkz */ /* Table16769 */ 0x14c9, /* VFMADDSUB132PSZ128mkz */ 0x14cc, /* VFMADDSUB132PSZ128rkz */ /* Table16771 */ 0x16d1, /* VFMSUBADD132PSZ128mkz */ 0x16d4, /* VFMSUBADD132PSZ128rkz */ /* Table16773 */ 0x137d, /* VFMADD132PSZ128mkz */ 0x1380, /* VFMADD132PSZ128rkz */ /* Table16775 */ 0x13ab, /* VFMADD132SSZm_Intkz */ 0x13af, /* VFMADD132SSZr_Intkz */ /* Table16777 */ 0x15a5, /* VFMSUB132PSZ128mkz */ 0x15a8, /* VFMSUB132PSZ128rkz */ /* Table16779 */ 0x15d3, /* VFMSUB132SSZm_Intkz */ 0x15d7, /* VFMSUB132SSZr_Intkz */ /* Table16781 */ 0x17cd, /* VFNMADD132PSZ128mkz */ 0x17d0, /* VFNMADD132PSZ128rkz */ /* Table16783 */ 0x17fb, /* VFNMADD132SSZm_Intkz */ 0x17ff, /* VFNMADD132SSZr_Intkz */ /* Table16785 */ 0x1919, /* VFNMSUB132PSZ128mkz */ 0x191c, /* VFNMSUB132PSZ128rkz */ /* Table16787 */ 0x1947, /* VFNMSUB132SSZm_Intkz */ 0x194b, /* VFNMSUB132SSZr_Intkz */ /* Table16789 */ 0x150d, /* VFMADDSUB213PSZ128mkz */ 0x1510, /* VFMADDSUB213PSZ128rkz */ /* Table16791 */ 0x1715, /* VFMSUBADD213PSZ128mkz */ 0x1718, /* VFMSUBADD213PSZ128rkz */ /* Table16793 */ 0x13e1, /* VFMADD213PSZ128mkz */ 0x13e4, /* VFMADD213PSZ128rkz */ /* Table16795 */ 0x140f, /* VFMADD213SSZm_Intkz */ 0x1413, /* VFMADD213SSZr_Intkz */ /* Table16797 */ 0x1609, /* VFMSUB213PSZ128mkz */ 0x160c, /* VFMSUB213PSZ128rkz */ /* Table16799 */ 0x1637, /* VFMSUB213SSZm_Intkz */ 0x163b, /* VFMSUB213SSZr_Intkz */ /* Table16801 */ 0x1831, /* VFNMADD213PSZ128mkz */ 0x1834, /* VFNMADD213PSZ128rkz */ /* Table16803 */ 0x185f, /* VFNMADD213SSZm_Intkz */ 0x1863, /* VFNMADD213SSZr_Intkz */ /* Table16805 */ 0x197d, /* VFNMSUB213PSZ128mkz */ 0x1980, /* VFNMSUB213PSZ128rkz */ /* Table16807 */ 0x19ab, /* VFNMSUB213SSZm_Intkz */ 0x19af, /* VFNMSUB213SSZr_Intkz */ /* Table16809 */ 0x1551, /* VFMADDSUB231PSZ128mkz */ 0x1554, /* VFMADDSUB231PSZ128rkz */ /* Table16811 */ 0x1759, /* VFMSUBADD231PSZ128mkz */ 0x175c, /* VFMSUBADD231PSZ128rkz */ /* Table16813 */ 0x1445, /* VFMADD231PSZ128mkz */ 0x1448, /* VFMADD231PSZ128rkz */ /* Table16815 */ 0x1473, /* VFMADD231SSZm_Intkz */ 0x1477, /* VFMADD231SSZr_Intkz */ /* Table16817 */ 0x166d, /* VFMSUB231PSZ128mkz */ 0x1670, /* VFMSUB231PSZ128rkz */ /* Table16819 */ 0x169b, /* VFMSUB231SSZm_Intkz */ 0x169f, /* VFMSUB231SSZr_Intkz */ /* Table16821 */ 0x1895, /* VFNMADD231PSZ128mkz */ 0x1898, /* VFNMADD231PSZ128rkz */ /* Table16823 */ 0x18c3, /* VFNMADD231SSZm_Intkz */ 0x18c7, /* VFNMADD231SSZr_Intkz */ /* Table16825 */ 0x19e1, /* VFNMSUB231PSZ128mkz */ 0x19e4, /* VFNMSUB231PSZ128rkz */ /* Table16827 */ 0x1a0f, /* VFNMSUB231SSZm_Intkz */ 0x1a13, /* VFNMSUB231SSZr_Intkz */ /* Table16829 */ 0x2560, /* VPCONFLICTDZ128rmkz */ 0x2563, /* VPCONFLICTDZ128rrkz */ /* Table16831 */ 0x3798, /* VRCP28SSZmkz */ 0x379e, /* VRCP28SSZrkz */ /* Table16833 */ 0x38bc, /* VRSQRT28SSZmkz */ 0x38c2, /* VRSQRT28SSZrkz */ /* Table16835 */ 0x1b6e, /* VGF2P8MULBZ128rmkz */ 0x1b71, /* VGF2P8MULBZ128rrkz */ /* Table16837 */ 0x26d9, /* VPERMILPDZ128rmkz */ 0x26dc, /* VPERMILPDZ128rrkz */ /* Table16839 */ 0x3429, /* VPSRLVWZ128rmkz */ 0x342c, /* VPSRLVWZ128rrkz */ /* Table16841 */ 0x3341, /* VPSRAVWZ128rmkz */ 0x3344, /* VPSRAVWZ128rrkz */ /* Table16843 */ 0x326b, /* VPSLLVWZ128rmkz */ 0x326e, /* VPSLLVWZ128rrkz */ /* Table16845 */ 0x2fc0, /* VPRORVQZ128rmkz */ 0x2fc3, /* VPRORVQZ128rrkz */ /* Table16847 */ 0x2f54, /* VPROLVQZ128rmkz */ 0x2f57, /* VPROLVQZ128rrkz */ /* Table16849 */ 0x2067, /* VPABSQZ128rmkz */ 0x206a, /* VPABSQZ128rrkz */ /* Table16851 */ 0x2d82, /* VPMULDQZ128rmkz */ 0x2d85, /* VPMULDQZ128rrkz */ /* Table16853 */ 0x38d0, /* VSCALEFPDZ128rmkz */ 0x38d3, /* VSCALEFPDZ128rrkz */ /* Table16855 */ 0x3909, /* VSCALEFSDZrmkz */ 0x390f, /* VSCALEFSDZrrkz */ /* Table16857 */ 0x2ab9, /* VPMINSQZ128rmkz */ 0x2abc, /* VPMINSQZ128rrkz */ /* Table16859 */ 0x2b1f, /* VPMINUQZ128rmkz */ 0x2b22, /* VPMINUQZ128rrkz */ /* Table16861 */ 0x29ed, /* VPMAXSQZ128rmkz */ 0x29f0, /* VPMAXSQZ128rrkz */ /* Table16863 */ 0x2a53, /* VPMAXUQZ128rmkz */ 0x2a56, /* VPMAXUQZ128rrkz */ /* Table16865 */ 0x2e00, /* VPMULLQZ128rmkz */ 0x2e03, /* VPMULLQZ128rrkz */ /* Table16867 */ 0x1a95, /* VGETEXPPDZ128mkz */ 0x1a98, /* VGETEXPPDZ128rkz */ /* Table16869 */ 0x1ace, /* VGETEXPSDZmkz */ 0x1ad4, /* VGETEXPSDZrkz */ /* Table16871 */ 0x291b, /* VPLZCNTQZ128rmkz */ 0x291e, /* VPLZCNTQZ128rrkz */ /* Table16873 */ 0x340f, /* VPSRLVQZ128rmkz */ 0x3412, /* VPSRLVQZ128rrkz */ /* Table16875 */ 0x3329, /* VPSRAVQZ128rmkz */ 0x332c, /* VPSRAVQZ128rrkz */ /* Table16877 */ 0x3251, /* VPSLLVQZ128rmkz */ 0x3254, /* VPSLLVQZ128rrkz */ /* Table16879 */ 0x3738, /* VRCP14PDZ128mkz */ 0x373b, /* VRCP14PDZ128rkz */ /* Table16881 */ 0x376b, /* VRCP14SDZrmkz */ 0x376e, /* VRCP14SDZrrkz */ /* Table16883 */ 0x385c, /* VRSQRT14PDZ128mkz */ 0x385f, /* VRSQRT14PDZ128rkz */ /* Table16885 */ 0x388f, /* VRSQRT14SDZrmkz */ 0x3892, /* VRSQRT14SDZrrkz */ /* Table16887 */ 0x2eb0, /* VPOPCNTWZ128rmkz */ 0x2eb3, /* VPOPCNTWZ128rrkz */ /* Table16889 */ 0x2e98, /* VPOPCNTQZ128rmkz */ 0x2e9b, /* VPOPCNTQZ128rrkz */ /* Table16891 */ 0x2323, /* VPBROADCASTQZ128mkz */ 0x2326, /* VPBROADCASTQZ128rkz */ /* Table16893 */ 0x287d, /* VPEXPANDWZ128rmkz */ 0x2880, /* VPEXPANDWZ128rrkz */ /* Table16895 */ 0x0, /* */ 0x2538, /* VPCOMPRESSWZ128rrkz */ /* Table16897 */ 0x22ab, /* VPBLENDMQZ128rmkz */ 0x22ae, /* VPBLENDMQZ128rrkz */ /* Table16899 */ 0xca5, /* VBLENDMPDZ128rmkz */ 0xca8, /* VBLENDMPDZ128rrkz */ /* Table16901 */ 0x22c3, /* VPBLENDMWZ128rmkz */ 0x22c6, /* VPBLENDMWZ128rrkz */ /* Table16903 */ 0x3086, /* VPSHLDVWZ128mkz */ 0x3089, /* VPSHLDVWZ128rkz */ /* Table16905 */ 0x306e, /* VPSHLDVQZ128mkz */ 0x3071, /* VPSHLDVQZ128rkz */ /* Table16907 */ 0x3122, /* VPSHRDVWZ128mkz */ 0x3125, /* VPSHRDVWZ128rkz */ /* Table16909 */ 0x310a, /* VPSHRDVQZ128mkz */ 0x310d, /* VPSHRDVQZ128rkz */ /* Table16911 */ 0x26a7, /* VPERMI2W128rmkz */ 0x26aa, /* VPERMI2W128rrkz */ /* Table16913 */ 0x268f, /* VPERMI2Q128rmkz */ 0x2692, /* VPERMI2Q128rrkz */ /* Table16915 */ 0x2659, /* VPERMI2PD128rmkz */ 0x265c, /* VPERMI2PD128rrkz */ /* Table16917 */ 0x0, /* */ 0x2335, /* VPBROADCASTQrZ128rkz */ /* Table16919 */ 0x2823, /* VPERMT2W128rmkz */ 0x2826, /* VPERMT2W128rrkz */ /* Table16921 */ 0x280b, /* VPERMT2Q128rmkz */ 0x280e, /* VPERMT2Q128rrkz */ /* Table16923 */ 0x27d5, /* VPERMT2PD128rmkz */ 0x27d8, /* VPERMT2PD128rrkz */ /* Table16925 */ 0x2e31, /* VPMULTISHIFTQBZ128rmkz */ 0x2e34, /* VPMULTISHIFTQBZ128rrkz */ /* Table16927 */ 0x12a0, /* VEXPANDPDZ128rmkz */ 0x12a3, /* VEXPANDPDZ128rrkz */ /* Table16929 */ 0x286b, /* VPEXPANDQZ128rmkz */ 0x286e, /* VPEXPANDQZ128rrkz */ /* Table16931 */ 0x0, /* */ 0xdec, /* VCOMPRESSPDZ128rrkz */ /* Table16933 */ 0x0, /* */ 0x2529, /* VPCOMPRESSQZ128rrkz */ /* Table16935 */ 0x2835, /* VPERMWZ128rmkz */ 0x2838, /* VPERMWZ128rrkz */ /* Table16937 */ 0x14a7, /* VFMADDSUB132PDZ128mkz */ 0x14aa, /* VFMADDSUB132PDZ128rkz */ /* Table16939 */ 0x16af, /* VFMSUBADD132PDZ128mkz */ 0x16b2, /* VFMSUBADD132PDZ128rkz */ /* Table16941 */ 0x135b, /* VFMADD132PDZ128mkz */ 0x135e, /* VFMADD132PDZ128rkz */ /* Table16943 */ 0x139b, /* VFMADD132SDZm_Intkz */ 0x139f, /* VFMADD132SDZr_Intkz */ /* Table16945 */ 0x1583, /* VFMSUB132PDZ128mkz */ 0x1586, /* VFMSUB132PDZ128rkz */ /* Table16947 */ 0x15c3, /* VFMSUB132SDZm_Intkz */ 0x15c7, /* VFMSUB132SDZr_Intkz */ /* Table16949 */ 0x17ab, /* VFNMADD132PDZ128mkz */ 0x17ae, /* VFNMADD132PDZ128rkz */ /* Table16951 */ 0x17eb, /* VFNMADD132SDZm_Intkz */ 0x17ef, /* VFNMADD132SDZr_Intkz */ /* Table16953 */ 0x18f7, /* VFNMSUB132PDZ128mkz */ 0x18fa, /* VFNMSUB132PDZ128rkz */ /* Table16955 */ 0x1937, /* VFNMSUB132SDZm_Intkz */ 0x193b, /* VFNMSUB132SDZr_Intkz */ /* Table16957 */ 0x14eb, /* VFMADDSUB213PDZ128mkz */ 0x14ee, /* VFMADDSUB213PDZ128rkz */ /* Table16959 */ 0x16f3, /* VFMSUBADD213PDZ128mkz */ 0x16f6, /* VFMSUBADD213PDZ128rkz */ /* Table16961 */ 0x13bf, /* VFMADD213PDZ128mkz */ 0x13c2, /* VFMADD213PDZ128rkz */ /* Table16963 */ 0x13ff, /* VFMADD213SDZm_Intkz */ 0x1403, /* VFMADD213SDZr_Intkz */ /* Table16965 */ 0x15e7, /* VFMSUB213PDZ128mkz */ 0x15ea, /* VFMSUB213PDZ128rkz */ /* Table16967 */ 0x1627, /* VFMSUB213SDZm_Intkz */ 0x162b, /* VFMSUB213SDZr_Intkz */ /* Table16969 */ 0x180f, /* VFNMADD213PDZ128mkz */ 0x1812, /* VFNMADD213PDZ128rkz */ /* Table16971 */ 0x184f, /* VFNMADD213SDZm_Intkz */ 0x1853, /* VFNMADD213SDZr_Intkz */ /* Table16973 */ 0x195b, /* VFNMSUB213PDZ128mkz */ 0x195e, /* VFNMSUB213PDZ128rkz */ /* Table16975 */ 0x199b, /* VFNMSUB213SDZm_Intkz */ 0x199f, /* VFNMSUB213SDZr_Intkz */ /* Table16977 */ 0x2969, /* VPMADD52LUQZ128mkz */ 0x296c, /* VPMADD52LUQZ128rkz */ /* Table16979 */ 0x294e, /* VPMADD52HUQZ128mkz */ 0x2951, /* VPMADD52HUQZ128rkz */ /* Table16981 */ 0x152f, /* VFMADDSUB231PDZ128mkz */ 0x1532, /* VFMADDSUB231PDZ128rkz */ /* Table16983 */ 0x1737, /* VFMSUBADD231PDZ128mkz */ 0x173a, /* VFMSUBADD231PDZ128rkz */ /* Table16985 */ 0x1423, /* VFMADD231PDZ128mkz */ 0x1426, /* VFMADD231PDZ128rkz */ /* Table16987 */ 0x1463, /* VFMADD231SDZm_Intkz */ 0x1467, /* VFMADD231SDZr_Intkz */ /* Table16989 */ 0x164b, /* VFMSUB231PDZ128mkz */ 0x164e, /* VFMSUB231PDZ128rkz */ /* Table16991 */ 0x168b, /* VFMSUB231SDZm_Intkz */ 0x168f, /* VFMSUB231SDZr_Intkz */ /* Table16993 */ 0x1873, /* VFNMADD231PDZ128mkz */ 0x1876, /* VFNMADD231PDZ128rkz */ /* Table16995 */ 0x18b3, /* VFNMADD231SDZm_Intkz */ 0x18b7, /* VFNMADD231SDZr_Intkz */ /* Table16997 */ 0x19bf, /* VFNMSUB231PDZ128mkz */ 0x19c2, /* VFNMSUB231PDZ128rkz */ /* Table16999 */ 0x19ff, /* VFNMSUB231SDZm_Intkz */ 0x1a03, /* VFNMSUB231SDZr_Intkz */ /* Table17001 */ 0x257b, /* VPCONFLICTQZ128rmkz */ 0x257e, /* VPCONFLICTQZ128rrkz */ /* Table17003 */ 0x378f, /* VRCP28SDZmkz */ 0x3795, /* VRCP28SDZrkz */ /* Table17005 */ 0x38b3, /* VRSQRT28SDZmkz */ 0x38b9, /* VRSQRT28SDZrkz */ /* Table17007 */ 0x0, /* */ 0x2cdf, /* VPMOVUSWBZ256rrkz */ /* Table17009 */ 0x0, /* */ 0x2c94, /* VPMOVUSDBZ256rrkz */ /* Table17011 */ 0x0, /* */ 0x2cb2, /* VPMOVUSQBZ256rrkz */ /* Table17013 */ 0x0, /* */ 0x2ca3, /* VPMOVUSDWZ256rrkz */ /* Table17015 */ 0x0, /* */ 0x2cd0, /* VPMOVUSQWZ256rrkz */ /* Table17017 */ 0x0, /* */ 0x2cc1, /* VPMOVUSQDZ256rrkz */ /* Table17019 */ 0x0, /* */ 0x2c01, /* VPMOVSWBZ256rrkz */ /* Table17021 */ 0x0, /* */ 0x2bb6, /* VPMOVSDBZ256rrkz */ /* Table17023 */ 0x0, /* */ 0x2bd4, /* VPMOVSQBZ256rrkz */ /* Table17025 */ 0x0, /* */ 0x2bc5, /* VPMOVSDWZ256rrkz */ /* Table17027 */ 0x0, /* */ 0x2bf2, /* VPMOVSQWZ256rrkz */ /* Table17029 */ 0x0, /* */ 0x2be3, /* VPMOVSQDZ256rrkz */ /* Table17031 */ 0x0, /* */ 0x2cf1, /* VPMOVWBZ256rrkz */ /* Table17033 */ 0x0, /* */ 0x2b5a, /* VPMOVDBZ256rrkz */ /* Table17035 */ 0x0, /* */ 0x2b89, /* VPMOVQBZ256rrkz */ /* Table17037 */ 0x0, /* */ 0x2b69, /* VPMOVDWZ256rrkz */ /* Table17039 */ 0x0, /* */ 0x2ba7, /* VPMOVQWZ256rrkz */ /* Table17041 */ 0x0, /* */ 0x2b98, /* VPMOVQDZ256rrkz */ /* Table17043 */ 0x315a, /* VPSHUFBZ256rmkz */ 0x315d, /* VPSHUFBZ256rrkz */ /* Table17045 */ 0x2989, /* VPMADDUBSWZ256rmkz */ 0x298c, /* VPMADDUBSWZ256rrkz */ /* Table17047 */ 0x2da4, /* VPMULHRSWZ256rmkz */ 0x2da7, /* VPMULHRSWZ256rrkz */ /* Table17049 */ 0x2729, /* VPERMILPSZ256rmkz */ 0x272c, /* VPERMILPSZ256rrkz */ /* Table17051 */ 0xeef, /* VCVTPH2PSZ256rmkz */ 0xef2, /* VCVTPH2PSZ256rrkz */ /* Table17053 */ 0x2fae, /* VPRORVDZ256rmkz */ 0x2fb1, /* VPRORVDZ256rrkz */ /* Table17055 */ 0x2f42, /* VPROLVDZ256rmkz */ 0x2f45, /* VPROLVDZ256rrkz */ /* Table17057 */ 0x2770, /* VPERMPSZ256rmkz */ 0x2773, /* VPERMPSZ256rrkz */ /* Table17059 */ 0xd42, /* VBROADCASTSSZ256mkz */ 0xd45, /* VBROADCASTSSZ256rkz */ /* Table17061 */ 0xce9, /* VBROADCASTF32X2Z256mkz */ 0xcec, /* VBROADCASTF32X2Z256rkz */ /* Table17063 */ 0xcf5, /* VBROADCASTF32X4Z256rmkz */ 0x0, /* */ /* Table17065 */ 0x2037, /* VPABSBZ256rmkz */ 0x203a, /* VPABSBZ256rrkz */ /* Table17067 */ 0x2087, /* VPABSWZ256rmkz */ 0x208a, /* VPABSWZ256rrkz */ /* Table17069 */ 0x2053, /* VPABSDZ256rmkz */ 0x2056, /* VPABSDZ256rrkz */ /* Table17071 */ 0x2c3d, /* VPMOVSXBWZ256rmkz */ 0x2c40, /* VPMOVSXBWZ256rrkz */ /* Table17073 */ 0x2c11, /* VPMOVSXBDZ256rmkz */ 0x2c14, /* VPMOVSXBDZ256rrkz */ /* Table17075 */ 0x2c27, /* VPMOVSXBQZ256rmkz */ 0x2c2a, /* VPMOVSXBQZ256rrkz */ /* Table17077 */ 0x2c69, /* VPMOVSXWDZ256rmkz */ 0x2c6c, /* VPMOVSXWDZ256rrkz */ /* Table17079 */ 0x2c7f, /* VPMOVSXWQZ256rmkz */ 0x2c82, /* VPMOVSXWQZ256rrkz */ /* Table17081 */ 0x2c53, /* VPMOVSXDQZ256rmkz */ 0x2c56, /* VPMOVSXDQZ256rrkz */ /* Table17083 */ 0x20d8, /* VPACKUSDWZ256rmkz */ 0x20db, /* VPACKUSDWZ256rrkz */ /* Table17085 */ 0x38f7, /* VSCALEFPSZ256rmkz */ 0x38fa, /* VSCALEFPSZ256rrkz */ /* Table17087 */ 0x2d2d, /* VPMOVZXBWZ256rmkz */ 0x2d30, /* VPMOVZXBWZ256rrkz */ /* Table17089 */ 0x2d01, /* VPMOVZXBDZ256rmkz */ 0x2d04, /* VPMOVZXBDZ256rrkz */ /* Table17091 */ 0x2d17, /* VPMOVZXBQZ256rmkz */ 0x2d1a, /* VPMOVZXBQZ256rrkz */ /* Table17093 */ 0x2d59, /* VPMOVZXWDZ256rmkz */ 0x2d5c, /* VPMOVZXWDZ256rrkz */ /* Table17095 */ 0x2d6f, /* VPMOVZXWQZ256rmkz */ 0x2d72, /* VPMOVZXWQZ256rrkz */ /* Table17097 */ 0x2d43, /* VPMOVZXDQZ256rmkz */ 0x2d46, /* VPMOVZXDQZ256rrkz */ /* Table17099 */ 0x261a, /* VPERMDZ256rmkz */ 0x261d, /* VPERMDZ256rrkz */ /* Table17101 */ 0x2a89, /* VPMINSBZ256rmkz */ 0x2a8c, /* VPMINSBZ256rrkz */ /* Table17103 */ 0x2aa5, /* VPMINSDZ256rmkz */ 0x2aa8, /* VPMINSDZ256rrkz */ /* Table17105 */ 0x2b3f, /* VPMINUWZ256rmkz */ 0x2b42, /* VPMINUWZ256rrkz */ /* Table17107 */ 0x2b0b, /* VPMINUDZ256rmkz */ 0x2b0e, /* VPMINUDZ256rrkz */ /* Table17109 */ 0x29bd, /* VPMAXSBZ256rmkz */ 0x29c0, /* VPMAXSBZ256rrkz */ /* Table17111 */ 0x29d9, /* VPMAXSDZ256rmkz */ 0x29dc, /* VPMAXSDZ256rrkz */ /* Table17113 */ 0x2a73, /* VPMAXUWZ256rmkz */ 0x2a76, /* VPMAXUWZ256rrkz */ /* Table17115 */ 0x2a3f, /* VPMAXUDZ256rmkz */ 0x2a42, /* VPMAXUDZ256rrkz */ /* Table17117 */ 0x2dec, /* VPMULLDZ256rmkz */ 0x2def, /* VPMULLDZ256rrkz */ /* Table17119 */ 0x1abc, /* VGETEXPPSZ256mkz */ 0x1abf, /* VGETEXPPSZ256rkz */ /* Table17121 */ 0x2909, /* VPLZCNTDZ256rmkz */ 0x290c, /* VPLZCNTDZ256rrkz */ /* Table17123 */ 0x33f9, /* VPSRLVDZ256rmkz */ 0x33fc, /* VPSRLVDZ256rrkz */ /* Table17125 */ 0x3315, /* VPSRAVDZ256rmkz */ 0x3318, /* VPSRAVDZ256rrkz */ /* Table17127 */ 0x323b, /* VPSLLVDZ256rmkz */ 0x323e, /* VPSLLVDZ256rrkz */ /* Table17129 */ 0x375c, /* VRCP14PSZ256mkz */ 0x375f, /* VRCP14PSZ256rkz */ /* Table17131 */ 0x3880, /* VRSQRT14PSZ256mkz */ 0x3883, /* VRSQRT14PSZ256rkz */ /* Table17133 */ 0x25ba, /* VPDPBUSDZ256mkz */ 0x25bd, /* VPDPBUSDZ256rkz */ /* Table17135 */ 0x259f, /* VPDPBUSDSZ256mkz */ 0x25a2, /* VPDPBUSDSZ256rkz */ /* Table17137 */ 0x25f0, /* VPDPWSSDZ256mkz */ 0x25f3, /* VPDPWSSDZ256rkz */ /* Table17139 */ 0x25d5, /* VPDPWSSDSZ256mkz */ 0x25d8, /* VPDPWSSDSZ256rkz */ /* Table17141 */ 0x2e6e, /* VPOPCNTBZ256rmkz */ 0x2e71, /* VPOPCNTBZ256rrkz */ /* Table17143 */ 0x2e86, /* VPOPCNTDZ256rmkz */ 0x2e89, /* VPOPCNTDZ256rrkz */ /* Table17145 */ 0x2304, /* VPBROADCASTDZ256mkz */ 0x2307, /* VPBROADCASTDZ256rkz */ /* Table17147 */ 0xd0e, /* VBROADCASTI32X2Z256mkz */ 0xd11, /* VBROADCASTI32X2Z256rkz */ /* Table17149 */ 0xd1a, /* VBROADCASTI32X4Z256rmkz */ 0x0, /* */ /* Table17151 */ 0x284d, /* VPEXPANDBZ256rmkz */ 0x2850, /* VPEXPANDBZ256rrkz */ /* Table17153 */ 0x0, /* */ 0x2510, /* VPCOMPRESSBZ256rrkz */ /* Table17155 */ 0x2299, /* VPBLENDMDZ256rmkz */ 0x229c, /* VPBLENDMDZ256rrkz */ /* Table17157 */ 0xcc9, /* VBLENDMPSZ256rmkz */ 0xccc, /* VBLENDMPSZ256rrkz */ /* Table17159 */ 0x2281, /* VPBLENDMBZ256rmkz */ 0x2284, /* VPBLENDMBZ256rrkz */ /* Table17161 */ 0x305c, /* VPSHLDVDZ256mkz */ 0x305f, /* VPSHLDVDZ256rkz */ /* Table17163 */ 0x30f8, /* VPSHRDVDZ256mkz */ 0x30fb, /* VPSHRDVDZ256rkz */ /* Table17165 */ 0x262f, /* VPERMI2B256rmkz */ 0x2632, /* VPERMI2B256rrkz */ /* Table17167 */ 0x2647, /* VPERMI2D256rmkz */ 0x264a, /* VPERMI2D256rrkz */ /* Table17169 */ 0x267d, /* VPERMI2PS256rmkz */ 0x2680, /* VPERMI2PS256rrkz */ /* Table17171 */ 0x22e5, /* VPBROADCASTBZ256mkz */ 0x22e8, /* VPBROADCASTBZ256rkz */ /* Table17173 */ 0x2348, /* VPBROADCASTWZ256mkz */ 0x234b, /* VPBROADCASTWZ256rkz */ /* Table17175 */ 0x0, /* */ 0x22f4, /* VPBROADCASTBrZ256rkz */ /* Table17177 */ 0x0, /* */ 0x2357, /* VPBROADCASTWrZ256rkz */ /* Table17179 */ 0x0, /* */ 0x2313, /* VPBROADCASTDrZ256rkz */ /* Table17181 */ 0x27ab, /* VPERMT2B256rmkz */ 0x27ae, /* VPERMT2B256rrkz */ /* Table17183 */ 0x27c3, /* VPERMT2D256rmkz */ 0x27c6, /* VPERMT2D256rrkz */ /* Table17185 */ 0x27f9, /* VPERMT2PS256rmkz */ 0x27fc, /* VPERMT2PS256rrkz */ /* Table17187 */ 0x12b8, /* VEXPANDPSZ256rmkz */ 0x12bb, /* VEXPANDPSZ256rrkz */ /* Table17189 */ 0x285f, /* VPEXPANDDZ256rmkz */ 0x2862, /* VPEXPANDDZ256rrkz */ /* Table17191 */ 0x0, /* */ 0xe00, /* VCOMPRESSPSZ256rrkz */ /* Table17193 */ 0x0, /* */ 0x251f, /* VPCOMPRESSDZ256rrkz */ /* Table17195 */ 0x2609, /* VPERMBZ256rmkz */ 0x260c, /* VPERMBZ256rrkz */ /* Table17197 */ 0x14d2, /* VFMADDSUB132PSZ256mkz */ 0x14d5, /* VFMADDSUB132PSZ256rkz */ /* Table17199 */ 0x16da, /* VFMSUBADD132PSZ256mkz */ 0x16dd, /* VFMSUBADD132PSZ256rkz */ /* Table17201 */ 0x1386, /* VFMADD132PSZ256mkz */ 0x1389, /* VFMADD132PSZ256rkz */ /* Table17203 */ 0x15ae, /* VFMSUB132PSZ256mkz */ 0x15b1, /* VFMSUB132PSZ256rkz */ /* Table17205 */ 0x17d6, /* VFNMADD132PSZ256mkz */ 0x17d9, /* VFNMADD132PSZ256rkz */ /* Table17207 */ 0x1922, /* VFNMSUB132PSZ256mkz */ 0x1925, /* VFNMSUB132PSZ256rkz */ /* Table17209 */ 0x1516, /* VFMADDSUB213PSZ256mkz */ 0x1519, /* VFMADDSUB213PSZ256rkz */ /* Table17211 */ 0x171e, /* VFMSUBADD213PSZ256mkz */ 0x1721, /* VFMSUBADD213PSZ256rkz */ /* Table17213 */ 0x13ea, /* VFMADD213PSZ256mkz */ 0x13ed, /* VFMADD213PSZ256rkz */ /* Table17215 */ 0x1612, /* VFMSUB213PSZ256mkz */ 0x1615, /* VFMSUB213PSZ256rkz */ /* Table17217 */ 0x183a, /* VFNMADD213PSZ256mkz */ 0x183d, /* VFNMADD213PSZ256rkz */ /* Table17219 */ 0x1986, /* VFNMSUB213PSZ256mkz */ 0x1989, /* VFNMSUB213PSZ256rkz */ /* Table17221 */ 0x155a, /* VFMADDSUB231PSZ256mkz */ 0x155d, /* VFMADDSUB231PSZ256rkz */ /* Table17223 */ 0x1762, /* VFMSUBADD231PSZ256mkz */ 0x1765, /* VFMSUBADD231PSZ256rkz */ /* Table17225 */ 0x144e, /* VFMADD231PSZ256mkz */ 0x1451, /* VFMADD231PSZ256rkz */ /* Table17227 */ 0x1676, /* VFMSUB231PSZ256mkz */ 0x1679, /* VFMSUB231PSZ256rkz */ /* Table17229 */ 0x189e, /* VFNMADD231PSZ256mkz */ 0x18a1, /* VFNMADD231PSZ256rkz */ /* Table17231 */ 0x19ea, /* VFNMSUB231PSZ256mkz */ 0x19ed, /* VFNMSUB231PSZ256rkz */ /* Table17233 */ 0x2569, /* VPCONFLICTDZ256rmkz */ 0x256c, /* VPCONFLICTDZ256rrkz */ /* Table17235 */ 0x1b74, /* VGF2P8MULBZ256rmkz */ 0x1b77, /* VGF2P8MULBZ256rrkz */ /* Table17237 */ 0x26eb, /* VPERMILPDZ256rmkz */ 0x26ee, /* VPERMILPDZ256rrkz */ /* Table17239 */ 0x342f, /* VPSRLVWZ256rmkz */ 0x3432, /* VPSRLVWZ256rrkz */ /* Table17241 */ 0x3347, /* VPSRAVWZ256rmkz */ 0x334a, /* VPSRAVWZ256rrkz */ /* Table17243 */ 0x3271, /* VPSLLVWZ256rmkz */ 0x3274, /* VPSLLVWZ256rrkz */ /* Table17245 */ 0x2fc9, /* VPRORVQZ256rmkz */ 0x2fcc, /* VPRORVQZ256rrkz */ /* Table17247 */ 0x2f5d, /* VPROLVQZ256rmkz */ 0x2f60, /* VPROLVQZ256rrkz */ /* Table17249 */ 0x2753, /* VPERMPDZ256rmkz */ 0x2756, /* VPERMPDZ256rrkz */ /* Table17251 */ 0xd2e, /* VBROADCASTSDZ256mkz */ 0xd31, /* VBROADCASTSDZ256rkz */ /* Table17253 */ 0xcfe, /* VBROADCASTF64X2Z128rmkz */ 0x0, /* */ /* Table17255 */ 0x2070, /* VPABSQZ256rmkz */ 0x2073, /* VPABSQZ256rrkz */ /* Table17257 */ 0x2d8b, /* VPMULDQZ256rmkz */ 0x2d8e, /* VPMULDQZ256rrkz */ /* Table17259 */ 0x38d9, /* VSCALEFPDZ256rmkz */ 0x38dc, /* VSCALEFPDZ256rrkz */ /* Table17261 */ 0x278d, /* VPERMQZ256rmkz */ 0x2790, /* VPERMQZ256rrkz */ /* Table17263 */ 0x2ac2, /* VPMINSQZ256rmkz */ 0x2ac5, /* VPMINSQZ256rrkz */ /* Table17265 */ 0x2b28, /* VPMINUQZ256rmkz */ 0x2b2b, /* VPMINUQZ256rrkz */ /* Table17267 */ 0x29f6, /* VPMAXSQZ256rmkz */ 0x29f9, /* VPMAXSQZ256rrkz */ /* Table17269 */ 0x2a5c, /* VPMAXUQZ256rmkz */ 0x2a5f, /* VPMAXUQZ256rrkz */ /* Table17271 */ 0x2e09, /* VPMULLQZ256rmkz */ 0x2e0c, /* VPMULLQZ256rrkz */ /* Table17273 */ 0x1a9e, /* VGETEXPPDZ256mkz */ 0x1aa1, /* VGETEXPPDZ256rkz */ /* Table17275 */ 0x2924, /* VPLZCNTQZ256rmkz */ 0x2927, /* VPLZCNTQZ256rrkz */ /* Table17277 */ 0x3418, /* VPSRLVQZ256rmkz */ 0x341b, /* VPSRLVQZ256rrkz */ /* Table17279 */ 0x3332, /* VPSRAVQZ256rmkz */ 0x3335, /* VPSRAVQZ256rrkz */ /* Table17281 */ 0x325a, /* VPSLLVQZ256rmkz */ 0x325d, /* VPSLLVQZ256rrkz */ /* Table17283 */ 0x3741, /* VRCP14PDZ256mkz */ 0x3744, /* VRCP14PDZ256rkz */ /* Table17285 */ 0x3865, /* VRSQRT14PDZ256mkz */ 0x3868, /* VRSQRT14PDZ256rkz */ /* Table17287 */ 0x2eb6, /* VPOPCNTWZ256rmkz */ 0x2eb9, /* VPOPCNTWZ256rrkz */ /* Table17289 */ 0x2ea1, /* VPOPCNTQZ256rmkz */ 0x2ea4, /* VPOPCNTQZ256rrkz */ /* Table17291 */ 0x2329, /* VPBROADCASTQZ256mkz */ 0x232c, /* VPBROADCASTQZ256rkz */ /* Table17293 */ 0xd23, /* VBROADCASTI64X2Z128rmkz */ 0x0, /* */ /* Table17295 */ 0x2883, /* VPEXPANDWZ256rmkz */ 0x2886, /* VPEXPANDWZ256rrkz */ /* Table17297 */ 0x0, /* */ 0x253d, /* VPCOMPRESSWZ256rrkz */ /* Table17299 */ 0x22b4, /* VPBLENDMQZ256rmkz */ 0x22b7, /* VPBLENDMQZ256rrkz */ /* Table17301 */ 0xcae, /* VBLENDMPDZ256rmkz */ 0xcb1, /* VBLENDMPDZ256rrkz */ /* Table17303 */ 0x22c9, /* VPBLENDMWZ256rmkz */ 0x22cc, /* VPBLENDMWZ256rrkz */ /* Table17305 */ 0x308c, /* VPSHLDVWZ256mkz */ 0x308f, /* VPSHLDVWZ256rkz */ /* Table17307 */ 0x3077, /* VPSHLDVQZ256mkz */ 0x307a, /* VPSHLDVQZ256rkz */ /* Table17309 */ 0x3128, /* VPSHRDVWZ256mkz */ 0x312b, /* VPSHRDVWZ256rkz */ /* Table17311 */ 0x3113, /* VPSHRDVQZ256mkz */ 0x3116, /* VPSHRDVQZ256rkz */ /* Table17313 */ 0x26ad, /* VPERMI2W256rmkz */ 0x26b0, /* VPERMI2W256rrkz */ /* Table17315 */ 0x2698, /* VPERMI2Q256rmkz */ 0x269b, /* VPERMI2Q256rrkz */ /* Table17317 */ 0x2662, /* VPERMI2PD256rmkz */ 0x2665, /* VPERMI2PD256rrkz */ /* Table17319 */ 0x0, /* */ 0x2338, /* VPBROADCASTQrZ256rkz */ /* Table17321 */ 0x2829, /* VPERMT2W256rmkz */ 0x282c, /* VPERMT2W256rrkz */ /* Table17323 */ 0x2814, /* VPERMT2Q256rmkz */ 0x2817, /* VPERMT2Q256rrkz */ /* Table17325 */ 0x27de, /* VPERMT2PD256rmkz */ 0x27e1, /* VPERMT2PD256rrkz */ /* Table17327 */ 0x2e3a, /* VPMULTISHIFTQBZ256rmkz */ 0x2e3d, /* VPMULTISHIFTQBZ256rrkz */ /* Table17329 */ 0x12a6, /* VEXPANDPDZ256rmkz */ 0x12a9, /* VEXPANDPDZ256rrkz */ /* Table17331 */ 0x2871, /* VPEXPANDQZ256rmkz */ 0x2874, /* VPEXPANDQZ256rrkz */ /* Table17333 */ 0x0, /* */ 0xdf1, /* VCOMPRESSPDZ256rrkz */ /* Table17335 */ 0x0, /* */ 0x252e, /* VPCOMPRESSQZ256rrkz */ /* Table17337 */ 0x283b, /* VPERMWZ256rmkz */ 0x283e, /* VPERMWZ256rrkz */ /* Table17339 */ 0x14b0, /* VFMADDSUB132PDZ256mkz */ 0x14b3, /* VFMADDSUB132PDZ256rkz */ /* Table17341 */ 0x16b8, /* VFMSUBADD132PDZ256mkz */ 0x16bb, /* VFMSUBADD132PDZ256rkz */ /* Table17343 */ 0x1364, /* VFMADD132PDZ256mkz */ 0x1367, /* VFMADD132PDZ256rkz */ /* Table17345 */ 0x158c, /* VFMSUB132PDZ256mkz */ 0x158f, /* VFMSUB132PDZ256rkz */ /* Table17347 */ 0x17b4, /* VFNMADD132PDZ256mkz */ 0x17b7, /* VFNMADD132PDZ256rkz */ /* Table17349 */ 0x1900, /* VFNMSUB132PDZ256mkz */ 0x1903, /* VFNMSUB132PDZ256rkz */ /* Table17351 */ 0x14f4, /* VFMADDSUB213PDZ256mkz */ 0x14f7, /* VFMADDSUB213PDZ256rkz */ /* Table17353 */ 0x16fc, /* VFMSUBADD213PDZ256mkz */ 0x16ff, /* VFMSUBADD213PDZ256rkz */ /* Table17355 */ 0x13c8, /* VFMADD213PDZ256mkz */ 0x13cb, /* VFMADD213PDZ256rkz */ /* Table17357 */ 0x15f0, /* VFMSUB213PDZ256mkz */ 0x15f3, /* VFMSUB213PDZ256rkz */ /* Table17359 */ 0x1818, /* VFNMADD213PDZ256mkz */ 0x181b, /* VFNMADD213PDZ256rkz */ /* Table17361 */ 0x1964, /* VFNMSUB213PDZ256mkz */ 0x1967, /* VFNMSUB213PDZ256rkz */ /* Table17363 */ 0x2972, /* VPMADD52LUQZ256mkz */ 0x2975, /* VPMADD52LUQZ256rkz */ /* Table17365 */ 0x2957, /* VPMADD52HUQZ256mkz */ 0x295a, /* VPMADD52HUQZ256rkz */ /* Table17367 */ 0x1538, /* VFMADDSUB231PDZ256mkz */ 0x153b, /* VFMADDSUB231PDZ256rkz */ /* Table17369 */ 0x1740, /* VFMSUBADD231PDZ256mkz */ 0x1743, /* VFMSUBADD231PDZ256rkz */ /* Table17371 */ 0x142c, /* VFMADD231PDZ256mkz */ 0x142f, /* VFMADD231PDZ256rkz */ /* Table17373 */ 0x1654, /* VFMSUB231PDZ256mkz */ 0x1657, /* VFMSUB231PDZ256rkz */ /* Table17375 */ 0x187c, /* VFNMADD231PDZ256mkz */ 0x187f, /* VFNMADD231PDZ256rkz */ /* Table17377 */ 0x19c8, /* VFNMSUB231PDZ256mkz */ 0x19cb, /* VFNMSUB231PDZ256rkz */ /* Table17379 */ 0x2584, /* VPCONFLICTQZ256rmkz */ 0x2587, /* VPCONFLICTQZ256rrkz */ /* Table17381 */ 0x0, /* */ 0x2ce4, /* VPMOVUSWBZrrkz */ /* Table17383 */ 0x0, /* */ 0x2c99, /* VPMOVUSDBZrrkz */ /* Table17385 */ 0x0, /* */ 0x2cb7, /* VPMOVUSQBZrrkz */ /* Table17387 */ 0x0, /* */ 0x2ca8, /* VPMOVUSDWZrrkz */ /* Table17389 */ 0x0, /* */ 0x2cd5, /* VPMOVUSQWZrrkz */ /* Table17391 */ 0x0, /* */ 0x2cc6, /* VPMOVUSQDZrrkz */ /* Table17393 */ 0x0, /* */ 0x2c06, /* VPMOVSWBZrrkz */ /* Table17395 */ 0x0, /* */ 0x2bbb, /* VPMOVSDBZrrkz */ /* Table17397 */ 0x0, /* */ 0x2bd9, /* VPMOVSQBZrrkz */ /* Table17399 */ 0x0, /* */ 0x2bca, /* VPMOVSDWZrrkz */ /* Table17401 */ 0x0, /* */ 0x2bf7, /* VPMOVSQWZrrkz */ /* Table17403 */ 0x0, /* */ 0x2be8, /* VPMOVSQDZrrkz */ /* Table17405 */ 0x0, /* */ 0x2cf6, /* VPMOVWBZrrkz */ /* Table17407 */ 0x0, /* */ 0x2b5f, /* VPMOVDBZrrkz */ /* Table17409 */ 0x0, /* */ 0x2b8e, /* VPMOVQBZrrkz */ /* Table17411 */ 0x0, /* */ 0x2b6e, /* VPMOVDWZrrkz */ /* Table17413 */ 0x0, /* */ 0x2bac, /* VPMOVQWZrrkz */ /* Table17415 */ 0x0, /* */ 0x2b9d, /* VPMOVQDZrrkz */ /* Table17417 */ 0x202c, /* VP4DPWSSDrmkz */ 0x0, /* */ /* Table17419 */ 0x2029, /* VP4DPWSSDSrmkz */ 0x0, /* */ /* Table17421 */ 0xb4e, /* V4FMADDPSrmkz */ 0x0, /* */ /* Table17423 */ 0xb54, /* V4FNMADDPSrmkz */ 0x0, /* */ /* Table17425 */ 0x3160, /* VPSHUFBZrmkz */ 0x3163, /* VPSHUFBZrrkz */ /* Table17427 */ 0x298f, /* VPMADDUBSWZrmkz */ 0x2992, /* VPMADDUBSWZrrkz */ /* Table17429 */ 0x2daa, /* VPMULHRSWZrmkz */ 0x2dad, /* VPMULHRSWZrrkz */ /* Table17431 */ 0x273b, /* VPERMILPSZrmkz */ 0x273e, /* VPERMILPSZrrkz */ /* Table17433 */ 0xef5, /* VCVTPH2PSZrmkz */ 0xefb, /* VCVTPH2PSZrrkz */ /* Table17435 */ 0x2fb7, /* VPRORVDZrmkz */ 0x2fba, /* VPRORVDZrrkz */ /* Table17437 */ 0x2f4b, /* VPROLVDZrmkz */ 0x2f4e, /* VPROLVDZrrkz */ /* Table17439 */ 0x2779, /* VPERMPSZrmkz */ 0x277c, /* VPERMPSZrrkz */ /* Table17441 */ 0xd48, /* VBROADCASTSSZmkz */ 0xd4b, /* VBROADCASTSSZrkz */ /* Table17443 */ 0xcef, /* VBROADCASTF32X2Zmkz */ 0xcf2, /* VBROADCASTF32X2Zrkz */ /* Table17445 */ 0xcf8, /* VBROADCASTF32X4rmkz */ 0x0, /* */ /* Table17447 */ 0xcfb, /* VBROADCASTF32X8rmkz */ 0x0, /* */ /* Table17449 */ 0x203d, /* VPABSBZrmkz */ 0x2040, /* VPABSBZrrkz */ /* Table17451 */ 0x208d, /* VPABSWZrmkz */ 0x2090, /* VPABSWZrrkz */ /* Table17453 */ 0x205c, /* VPABSDZrmkz */ 0x205f, /* VPABSDZrrkz */ /* Table17455 */ 0x2c43, /* VPMOVSXBWZrmkz */ 0x2c46, /* VPMOVSXBWZrrkz */ /* Table17457 */ 0x2c17, /* VPMOVSXBDZrmkz */ 0x2c1a, /* VPMOVSXBDZrrkz */ /* Table17459 */ 0x2c2d, /* VPMOVSXBQZrmkz */ 0x2c30, /* VPMOVSXBQZrrkz */ /* Table17461 */ 0x2c6f, /* VPMOVSXWDZrmkz */ 0x2c72, /* VPMOVSXWDZrrkz */ /* Table17463 */ 0x2c85, /* VPMOVSXWQZrmkz */ 0x2c88, /* VPMOVSXWQZrrkz */ /* Table17465 */ 0x2c59, /* VPMOVSXDQZrmkz */ 0x2c5c, /* VPMOVSXDQZrrkz */ /* Table17467 */ 0x20e1, /* VPACKUSDWZrmkz */ 0x20e4, /* VPACKUSDWZrrkz */ /* Table17469 */ 0x3900, /* VSCALEFPSZrmkz */ 0x3906, /* VSCALEFPSZrrkz */ /* Table17471 */ 0x2d33, /* VPMOVZXBWZrmkz */ 0x2d36, /* VPMOVZXBWZrrkz */ /* Table17473 */ 0x2d07, /* VPMOVZXBDZrmkz */ 0x2d0a, /* VPMOVZXBDZrrkz */ /* Table17475 */ 0x2d1d, /* VPMOVZXBQZrmkz */ 0x2d20, /* VPMOVZXBQZrrkz */ /* Table17477 */ 0x2d5f, /* VPMOVZXWDZrmkz */ 0x2d62, /* VPMOVZXWDZrrkz */ /* Table17479 */ 0x2d75, /* VPMOVZXWQZrmkz */ 0x2d78, /* VPMOVZXWQZrrkz */ /* Table17481 */ 0x2d49, /* VPMOVZXDQZrmkz */ 0x2d4c, /* VPMOVZXDQZrrkz */ /* Table17483 */ 0x2623, /* VPERMDZrmkz */ 0x2626, /* VPERMDZrrkz */ /* Table17485 */ 0x2a8f, /* VPMINSBZrmkz */ 0x2a92, /* VPMINSBZrrkz */ /* Table17487 */ 0x2aae, /* VPMINSDZrmkz */ 0x2ab1, /* VPMINSDZrrkz */ /* Table17489 */ 0x2b45, /* VPMINUWZrmkz */ 0x2b48, /* VPMINUWZrrkz */ /* Table17491 */ 0x2b14, /* VPMINUDZrmkz */ 0x2b17, /* VPMINUDZrrkz */ /* Table17493 */ 0x29c3, /* VPMAXSBZrmkz */ 0x29c6, /* VPMAXSBZrrkz */ /* Table17495 */ 0x29e2, /* VPMAXSDZrmkz */ 0x29e5, /* VPMAXSDZrrkz */ /* Table17497 */ 0x2a79, /* VPMAXUWZrmkz */ 0x2a7c, /* VPMAXUWZrrkz */ /* Table17499 */ 0x2a48, /* VPMAXUDZrmkz */ 0x2a4b, /* VPMAXUDZrrkz */ /* Table17501 */ 0x2df5, /* VPMULLDZrmkz */ 0x2df8, /* VPMULLDZrrkz */ /* Table17503 */ 0x1ac5, /* VGETEXPPSZmkz */ 0x1acb, /* VGETEXPPSZrkz */ /* Table17505 */ 0x2912, /* VPLZCNTDZrmkz */ 0x2915, /* VPLZCNTDZrrkz */ /* Table17507 */ 0x3402, /* VPSRLVDZrmkz */ 0x3405, /* VPSRLVDZrrkz */ /* Table17509 */ 0x331e, /* VPSRAVDZrmkz */ 0x3321, /* VPSRAVDZrrkz */ /* Table17511 */ 0x3244, /* VPSLLVDZrmkz */ 0x3247, /* VPSLLVDZrrkz */ /* Table17513 */ 0x3765, /* VRCP14PSZmkz */ 0x3768, /* VRCP14PSZrkz */ /* Table17515 */ 0x3889, /* VRSQRT14PSZmkz */ 0x388c, /* VRSQRT14PSZrkz */ /* Table17517 */ 0x25c3, /* VPDPBUSDZmkz */ 0x25c6, /* VPDPBUSDZrkz */ /* Table17519 */ 0x25a8, /* VPDPBUSDSZmkz */ 0x25ab, /* VPDPBUSDSZrkz */ /* Table17521 */ 0x25f9, /* VPDPWSSDZmkz */ 0x25fc, /* VPDPWSSDZrkz */ /* Table17523 */ 0x25de, /* VPDPWSSDSZmkz */ 0x25e1, /* VPDPWSSDSZrkz */ /* Table17525 */ 0x2e74, /* VPOPCNTBZrmkz */ 0x2e77, /* VPOPCNTBZrrkz */ /* Table17527 */ 0x2e8f, /* VPOPCNTDZrmkz */ 0x2e92, /* VPOPCNTDZrrkz */ /* Table17529 */ 0x230a, /* VPBROADCASTDZmkz */ 0x230d, /* VPBROADCASTDZrkz */ /* Table17531 */ 0xd14, /* VBROADCASTI32X2Zmkz */ 0xd17, /* VBROADCASTI32X2Zrkz */ /* Table17533 */ 0xd1d, /* VBROADCASTI32X4rmkz */ 0x0, /* */ /* Table17535 */ 0xd20, /* VBROADCASTI32X8rmkz */ 0x0, /* */ /* Table17537 */ 0x2853, /* VPEXPANDBZrmkz */ 0x2856, /* VPEXPANDBZrrkz */ /* Table17539 */ 0x0, /* */ 0x2515, /* VPCOMPRESSBZrrkz */ /* Table17541 */ 0x22a2, /* VPBLENDMDZrmkz */ 0x22a5, /* VPBLENDMDZrrkz */ /* Table17543 */ 0xcd2, /* VBLENDMPSZrmkz */ 0xcd5, /* VBLENDMPSZrrkz */ /* Table17545 */ 0x2287, /* VPBLENDMBZrmkz */ 0x228a, /* VPBLENDMBZrrkz */ /* Table17547 */ 0x3065, /* VPSHLDVDZmkz */ 0x3068, /* VPSHLDVDZrkz */ /* Table17549 */ 0x3101, /* VPSHRDVDZmkz */ 0x3104, /* VPSHRDVDZrkz */ /* Table17551 */ 0x2635, /* VPERMI2Brmkz */ 0x2638, /* VPERMI2Brrkz */ /* Table17553 */ 0x2650, /* VPERMI2Drmkz */ 0x2653, /* VPERMI2Drrkz */ /* Table17555 */ 0x2686, /* VPERMI2PSrmkz */ 0x2689, /* VPERMI2PSrrkz */ /* Table17557 */ 0x22eb, /* VPBROADCASTBZmkz */ 0x22ee, /* VPBROADCASTBZrkz */ /* Table17559 */ 0x234e, /* VPBROADCASTWZmkz */ 0x2351, /* VPBROADCASTWZrkz */ /* Table17561 */ 0x0, /* */ 0x22f7, /* VPBROADCASTBrZrkz */ /* Table17563 */ 0x0, /* */ 0x235a, /* VPBROADCASTWrZrkz */ /* Table17565 */ 0x0, /* */ 0x2316, /* VPBROADCASTDrZrkz */ /* Table17567 */ 0x27b1, /* VPERMT2Brmkz */ 0x27b4, /* VPERMT2Brrkz */ /* Table17569 */ 0x27cc, /* VPERMT2Drmkz */ 0x27cf, /* VPERMT2Drrkz */ /* Table17571 */ 0x2802, /* VPERMT2PSrmkz */ 0x2805, /* VPERMT2PSrrkz */ /* Table17573 */ 0x12be, /* VEXPANDPSZrmkz */ 0x12c1, /* VEXPANDPSZrrkz */ /* Table17575 */ 0x2865, /* VPEXPANDDZrmkz */ 0x2868, /* VPEXPANDDZrrkz */ /* Table17577 */ 0x0, /* */ 0xe05, /* VCOMPRESSPSZrrkz */ /* Table17579 */ 0x0, /* */ 0x2524, /* VPCOMPRESSDZrrkz */ /* Table17581 */ 0x260f, /* VPERMBZrmkz */ 0x2612, /* VPERMBZrrkz */ /* Table17583 */ 0x14db, /* VFMADDSUB132PSZmkz */ 0x14e1, /* VFMADDSUB132PSZrkz */ /* Table17585 */ 0x16e3, /* VFMSUBADD132PSZmkz */ 0x16e9, /* VFMSUBADD132PSZrkz */ /* Table17587 */ 0x138f, /* VFMADD132PSZmkz */ 0x1395, /* VFMADD132PSZrkz */ /* Table17589 */ 0x15b7, /* VFMSUB132PSZmkz */ 0x15bd, /* VFMSUB132PSZrkz */ /* Table17591 */ 0x17df, /* VFNMADD132PSZmkz */ 0x17e5, /* VFNMADD132PSZrkz */ /* Table17593 */ 0x192b, /* VFNMSUB132PSZmkz */ 0x1931, /* VFNMSUB132PSZrkz */ /* Table17595 */ 0x151f, /* VFMADDSUB213PSZmkz */ 0x1525, /* VFMADDSUB213PSZrkz */ /* Table17597 */ 0x1727, /* VFMSUBADD213PSZmkz */ 0x172d, /* VFMSUBADD213PSZrkz */ /* Table17599 */ 0x13f3, /* VFMADD213PSZmkz */ 0x13f9, /* VFMADD213PSZrkz */ /* Table17601 */ 0x161b, /* VFMSUB213PSZmkz */ 0x1621, /* VFMSUB213PSZrkz */ /* Table17603 */ 0x1843, /* VFNMADD213PSZmkz */ 0x1849, /* VFNMADD213PSZrkz */ /* Table17605 */ 0x198f, /* VFNMSUB213PSZmkz */ 0x1995, /* VFNMSUB213PSZrkz */ /* Table17607 */ 0x1563, /* VFMADDSUB231PSZmkz */ 0x1569, /* VFMADDSUB231PSZrkz */ /* Table17609 */ 0x176b, /* VFMSUBADD231PSZmkz */ 0x1771, /* VFMSUBADD231PSZrkz */ /* Table17611 */ 0x1457, /* VFMADD231PSZmkz */ 0x145d, /* VFMADD231PSZrkz */ /* Table17613 */ 0x167f, /* VFMSUB231PSZmkz */ 0x1685, /* VFMSUB231PSZrkz */ /* Table17615 */ 0x18a7, /* VFNMADD231PSZmkz */ 0x18ad, /* VFNMADD231PSZrkz */ /* Table17617 */ 0x19f3, /* VFNMSUB231PSZmkz */ 0x19f9, /* VFNMSUB231PSZrkz */ /* Table17619 */ 0x2572, /* VPCONFLICTDZrmkz */ 0x2575, /* VPCONFLICTDZrrkz */ /* Table17621 */ 0x1297, /* VEXP2PSZmkz */ 0x129d, /* VEXP2PSZrkz */ /* Table17623 */ 0x3786, /* VRCP28PSZmkz */ 0x378c, /* VRCP28PSZrkz */ /* Table17625 */ 0x38aa, /* VRSQRT28PSZmkz */ 0x38b0, /* VRSQRT28PSZrkz */ /* Table17627 */ 0x1b7a, /* VGF2P8MULBZrmkz */ 0x1b7d, /* VGF2P8MULBZrrkz */ /* Table17629 */ 0x26fd, /* VPERMILPDZrmkz */ 0x2700, /* VPERMILPDZrrkz */ /* Table17631 */ 0x3435, /* VPSRLVWZrmkz */ 0x3438, /* VPSRLVWZrrkz */ /* Table17633 */ 0x334d, /* VPSRAVWZrmkz */ 0x3350, /* VPSRAVWZrrkz */ /* Table17635 */ 0x3277, /* VPSLLVWZrmkz */ 0x327a, /* VPSLLVWZrrkz */ /* Table17637 */ 0x2fd2, /* VPRORVQZrmkz */ 0x2fd5, /* VPRORVQZrrkz */ /* Table17639 */ 0x2f66, /* VPROLVQZrmkz */ 0x2f69, /* VPROLVQZrrkz */ /* Table17641 */ 0x2765, /* VPERMPDZrmkz */ 0x2768, /* VPERMPDZrrkz */ /* Table17643 */ 0xd34, /* VBROADCASTSDZmkz */ 0xd37, /* VBROADCASTSDZrkz */ /* Table17645 */ 0xd01, /* VBROADCASTF64X2rmkz */ 0x0, /* */ /* Table17647 */ 0xd04, /* VBROADCASTF64X4rmkz */ 0x0, /* */ /* Table17649 */ 0x2079, /* VPABSQZrmkz */ 0x207c, /* VPABSQZrrkz */ /* Table17651 */ 0x2d94, /* VPMULDQZrmkz */ 0x2d97, /* VPMULDQZrrkz */ /* Table17653 */ 0x38e2, /* VSCALEFPDZrmkz */ 0x38e8, /* VSCALEFPDZrrkz */ /* Table17655 */ 0x279f, /* VPERMQZrmkz */ 0x27a2, /* VPERMQZrrkz */ /* Table17657 */ 0x2acb, /* VPMINSQZrmkz */ 0x2ace, /* VPMINSQZrrkz */ /* Table17659 */ 0x2b31, /* VPMINUQZrmkz */ 0x2b34, /* VPMINUQZrrkz */ /* Table17661 */ 0x29ff, /* VPMAXSQZrmkz */ 0x2a02, /* VPMAXSQZrrkz */ /* Table17663 */ 0x2a65, /* VPMAXUQZrmkz */ 0x2a68, /* VPMAXUQZrrkz */ /* Table17665 */ 0x2e12, /* VPMULLQZrmkz */ 0x2e15, /* VPMULLQZrrkz */ /* Table17667 */ 0x1aa7, /* VGETEXPPDZmkz */ 0x1aad, /* VGETEXPPDZrkz */ /* Table17669 */ 0x292d, /* VPLZCNTQZrmkz */ 0x2930, /* VPLZCNTQZrrkz */ /* Table17671 */ 0x3421, /* VPSRLVQZrmkz */ 0x3424, /* VPSRLVQZrrkz */ /* Table17673 */ 0x333b, /* VPSRAVQZrmkz */ 0x333e, /* VPSRAVQZrrkz */ /* Table17675 */ 0x3263, /* VPSLLVQZrmkz */ 0x3266, /* VPSLLVQZrrkz */ /* Table17677 */ 0x374a, /* VRCP14PDZmkz */ 0x374d, /* VRCP14PDZrkz */ /* Table17679 */ 0x386e, /* VRSQRT14PDZmkz */ 0x3871, /* VRSQRT14PDZrkz */ /* Table17681 */ 0x2ebc, /* VPOPCNTWZrmkz */ 0x2ebf, /* VPOPCNTWZrrkz */ /* Table17683 */ 0x2eaa, /* VPOPCNTQZrmkz */ 0x2ead, /* VPOPCNTQZrrkz */ /* Table17685 */ 0x232f, /* VPBROADCASTQZmkz */ 0x2332, /* VPBROADCASTQZrkz */ /* Table17687 */ 0xd26, /* VBROADCASTI64X2rmkz */ 0x0, /* */ /* Table17689 */ 0xd29, /* VBROADCASTI64X4rmkz */ 0x0, /* */ /* Table17691 */ 0x2889, /* VPEXPANDWZrmkz */ 0x288c, /* VPEXPANDWZrrkz */ /* Table17693 */ 0x0, /* */ 0x2542, /* VPCOMPRESSWZrrkz */ /* Table17695 */ 0x22bd, /* VPBLENDMQZrmkz */ 0x22c0, /* VPBLENDMQZrrkz */ /* Table17697 */ 0xcb7, /* VBLENDMPDZrmkz */ 0xcba, /* VBLENDMPDZrrkz */ /* Table17699 */ 0x22cf, /* VPBLENDMWZrmkz */ 0x22d2, /* VPBLENDMWZrrkz */ /* Table17701 */ 0x3092, /* VPSHLDVWZmkz */ 0x3095, /* VPSHLDVWZrkz */ /* Table17703 */ 0x3080, /* VPSHLDVQZmkz */ 0x3083, /* VPSHLDVQZrkz */ /* Table17705 */ 0x312e, /* VPSHRDVWZmkz */ 0x3131, /* VPSHRDVWZrkz */ /* Table17707 */ 0x311c, /* VPSHRDVQZmkz */ 0x311f, /* VPSHRDVQZrkz */ /* Table17709 */ 0x26b3, /* VPERMI2Wrmkz */ 0x26b6, /* VPERMI2Wrrkz */ /* Table17711 */ 0x26a1, /* VPERMI2Qrmkz */ 0x26a4, /* VPERMI2Qrrkz */ /* Table17713 */ 0x266b, /* VPERMI2PDrmkz */ 0x266e, /* VPERMI2PDrrkz */ /* Table17715 */ 0x0, /* */ 0x233b, /* VPBROADCASTQrZrkz */ /* Table17717 */ 0x282f, /* VPERMT2Wrmkz */ 0x2832, /* VPERMT2Wrrkz */ /* Table17719 */ 0x281d, /* VPERMT2Qrmkz */ 0x2820, /* VPERMT2Qrrkz */ /* Table17721 */ 0x27e7, /* VPERMT2PDrmkz */ 0x27ea, /* VPERMT2PDrrkz */ /* Table17723 */ 0x2e43, /* VPMULTISHIFTQBZrmkz */ 0x2e46, /* VPMULTISHIFTQBZrrkz */ /* Table17725 */ 0x12ac, /* VEXPANDPDZrmkz */ 0x12af, /* VEXPANDPDZrrkz */ /* Table17727 */ 0x2877, /* VPEXPANDQZrmkz */ 0x287a, /* VPEXPANDQZrrkz */ /* Table17729 */ 0x0, /* */ 0xdf6, /* VCOMPRESSPDZrrkz */ /* Table17731 */ 0x0, /* */ 0x2533, /* VPCOMPRESSQZrrkz */ /* Table17733 */ 0x2841, /* VPERMWZrmkz */ 0x2844, /* VPERMWZrrkz */ /* Table17735 */ 0x14b9, /* VFMADDSUB132PDZmkz */ 0x14bf, /* VFMADDSUB132PDZrkz */ /* Table17737 */ 0x16c1, /* VFMSUBADD132PDZmkz */ 0x16c7, /* VFMSUBADD132PDZrkz */ /* Table17739 */ 0x136d, /* VFMADD132PDZmkz */ 0x1373, /* VFMADD132PDZrkz */ /* Table17741 */ 0x1595, /* VFMSUB132PDZmkz */ 0x159b, /* VFMSUB132PDZrkz */ /* Table17743 */ 0x17bd, /* VFNMADD132PDZmkz */ 0x17c3, /* VFNMADD132PDZrkz */ /* Table17745 */ 0x1909, /* VFNMSUB132PDZmkz */ 0x190f, /* VFNMSUB132PDZrkz */ /* Table17747 */ 0x14fd, /* VFMADDSUB213PDZmkz */ 0x1503, /* VFMADDSUB213PDZrkz */ /* Table17749 */ 0x1705, /* VFMSUBADD213PDZmkz */ 0x170b, /* VFMSUBADD213PDZrkz */ /* Table17751 */ 0x13d1, /* VFMADD213PDZmkz */ 0x13d7, /* VFMADD213PDZrkz */ /* Table17753 */ 0x15f9, /* VFMSUB213PDZmkz */ 0x15ff, /* VFMSUB213PDZrkz */ /* Table17755 */ 0x1821, /* VFNMADD213PDZmkz */ 0x1827, /* VFNMADD213PDZrkz */ /* Table17757 */ 0x196d, /* VFNMSUB213PDZmkz */ 0x1973, /* VFNMSUB213PDZrkz */ /* Table17759 */ 0x297b, /* VPMADD52LUQZmkz */ 0x297e, /* VPMADD52LUQZrkz */ /* Table17761 */ 0x2960, /* VPMADD52HUQZmkz */ 0x2963, /* VPMADD52HUQZrkz */ /* Table17763 */ 0x1541, /* VFMADDSUB231PDZmkz */ 0x1547, /* VFMADDSUB231PDZrkz */ /* Table17765 */ 0x1749, /* VFMSUBADD231PDZmkz */ 0x174f, /* VFMSUBADD231PDZrkz */ /* Table17767 */ 0x1435, /* VFMADD231PDZmkz */ 0x143b, /* VFMADD231PDZrkz */ /* Table17769 */ 0x165d, /* VFMSUB231PDZmkz */ 0x1663, /* VFMSUB231PDZrkz */ /* Table17771 */ 0x1885, /* VFNMADD231PDZmkz */ 0x188b, /* VFNMADD231PDZrkz */ /* Table17773 */ 0x19d1, /* VFNMSUB231PDZmkz */ 0x19d7, /* VFNMSUB231PDZrkz */ /* Table17775 */ 0x258d, /* VPCONFLICTQZrmkz */ 0x2590, /* VPCONFLICTQZrrkz */ /* Table17777 */ 0x128b, /* VEXP2PDZmkz */ 0x1291, /* VEXP2PDZrkz */ /* Table17779 */ 0x377a, /* VRCP28PDZmkz */ 0x3780, /* VRCP28PDZrkz */ /* Table17781 */ 0x389e, /* VRSQRT28PDZmkz */ 0x38a4, /* VRSQRT28PDZrkz */ /* Table17783 */ 0x588, /* MMX_PALIGNRrmi */ 0x589, /* MMX_PALIGNRrri */ /* Table17785 */ 0x9ff, /* SHA1RNDS4rmi */ 0xa00, /* SHA1RNDS4rri */ /* Table17787 */ 0x963, /* ROUNDPSm */ 0x964, /* ROUNDPSr */ /* Table17789 */ 0x961, /* ROUNDPDm */ 0x962, /* ROUNDPDr */ /* Table17791 */ 0x969, /* ROUNDSSm */ 0x96b, /* ROUNDSSr */ /* Table17793 */ 0x965, /* ROUNDSDm */ 0x967, /* ROUNDSDr */ /* Table17795 */ 0x16b, /* BLENDPSrmi */ 0x16c, /* BLENDPSrri */ /* Table17797 */ 0x169, /* BLENDPDrmi */ 0x16a, /* BLENDPDrri */ /* Table17799 */ 0x789, /* PBLENDWrmi */ 0x78a, /* PBLENDWrri */ /* Table17801 */ 0x77a, /* PALIGNRrmi */ 0x77b, /* PALIGNRrri */ /* Table17803 */ 0x7ae, /* PEXTRBmr */ 0x7af, /* PEXTRBrr */ /* Table17805 */ 0x7b4, /* PEXTRWmr */ 0x7b6, /* PEXTRWrr_REV */ /* Table17807 */ 0x7b0, /* PEXTRDmr */ 0x7b1, /* PEXTRDrr */ /* Table17809 */ 0x379, /* EXTRACTPSmr */ 0x37a, /* EXTRACTPSrr */ /* Table17811 */ 0x7ef, /* PINSRBrm */ 0x7f0, /* PINSRBrr */ /* Table17813 */ 0x40c, /* INSERTPSrm */ 0x40d, /* INSERTPSrr */ /* Table17815 */ 0x7f1, /* PINSRDrm */ 0x7f2, /* PINSRDrr */ /* Table17817 */ 0x371, /* DPPSrmi */ 0x372, /* DPPSrri */ /* Table17819 */ 0x36f, /* DPPDrmi */ 0x370, /* DPPDrri */ /* Table17821 */ 0x6cb, /* MPSADBWrmi */ 0x6cc, /* MPSADBWrri */ /* Table17823 */ 0x78b, /* PCLMULQDQrm */ 0x78c, /* PCLMULQDQrr */ /* Table17825 */ 0x797, /* PCMPESTRMrm */ 0x798, /* PCMPESTRMrr */ /* Table17827 */ 0x795, /* PCMPESTRIrm */ 0x796, /* PCMPESTRIrr */ /* Table17829 */ 0x7a3, /* PCMPISTRMrm */ 0x7a4, /* PCMPISTRMrr */ /* Table17831 */ 0x7a1, /* PCMPISTRIrm */ 0x7a2, /* PCMPISTRIrr */ /* Table17833 */ 0x3be, /* GF2P8AFFINEQBrmi */ 0x3bf, /* GF2P8AFFINEQBrri */ /* Table17835 */ 0x3bc, /* GF2P8AFFINEINVQBrmi */ 0x3bd, /* GF2P8AFFINEINVQBrri */ /* Table17837 */ 0x119, /* AESKEYGENASSIST128rm */ 0x11a, /* AESKEYGENASSIST128rr */ /* Table17839 */ 0x7b2, /* PEXTRQmr */ 0x7b3, /* PEXTRQrr */ /* Table17841 */ 0x7f3, /* PINSRQrm */ 0x7f4, /* PINSRQrr */ /* Table17843 */ 0x95d, /* RORX32mi */ 0x95e, /* RORX32ri */ /* Table17845 */ 0x2277, /* VPBLENDDrmi */ 0x2278, /* VPBLENDDrri */ /* Table17847 */ 0x273f, /* VPERMILPSmi */ 0x2740, /* VPERMILPSri */ /* Table17849 */ 0x2701, /* VPERMILPDmi */ 0x2702, /* VPERMILPDri */ /* Table17851 */ 0x384d, /* VROUNDPSm */ 0x384e, /* VROUNDPSr */ /* Table17853 */ 0x3849, /* VROUNDPDm */ 0x384a, /* VROUNDPDr */ /* Table17855 */ 0x3853, /* VROUNDSSm */ 0x3855, /* VROUNDSSr */ /* Table17857 */ 0x384f, /* VROUNDSDm */ 0x3851, /* VROUNDSDr */ /* Table17859 */ 0xcdc, /* VBLENDPSrmi */ 0xcdd, /* VBLENDPSrri */ /* Table17861 */ 0xcd8, /* VBLENDPDrmi */ 0xcd9, /* VBLENDPDrri */ /* Table17863 */ 0x22d9, /* VPBLENDWrmi */ 0x22da, /* VPBLENDWrri */ /* Table17865 */ 0x21d3, /* VPALIGNRrmi */ 0x21d4, /* VPALIGNRrri */ /* Table17867 */ 0x288f, /* VPEXTRBmr */ 0x2890, /* VPEXTRBrr */ /* Table17869 */ 0x289c, /* VPEXTRWmr */ 0x289e, /* VPEXTRWrr_REV */ /* Table17871 */ 0x2893, /* VPEXTRDmr */ 0x2894, /* VPEXTRDrr */ /* Table17873 */ 0x1304, /* VEXTRACTPSmr */ 0x1305, /* VEXTRACTPSrr */ /* Table17875 */ 0xf56, /* VCVTPS2PHmr */ 0xf57, /* VCVTPS2PHrr */ /* Table17877 */ 0x28ed, /* VPINSRBrm */ 0x28ee, /* VPINSRBrr */ /* Table17879 */ 0x1bde, /* VINSERTPSrm */ 0x1bdf, /* VINSERTPSrr */ /* Table17881 */ 0x28f1, /* VPINSRDrm */ 0x28f2, /* VPINSRDrr */ /* Table17883 */ 0x0, /* */ 0x4af, /* KSHIFTRBri */ /* Table17885 */ 0x0, /* */ 0x4b0, /* KSHIFTRDri */ /* Table17887 */ 0x0, /* */ 0x4ab, /* KSHIFTLBri */ /* Table17889 */ 0x0, /* */ 0x4ac, /* KSHIFTLDri */ /* Table17891 */ 0x1280, /* VDPPSrmi */ 0x1281, /* VDPPSrri */ /* Table17893 */ 0x127c, /* VDPPDrmi */ 0x127d, /* VDPPDrri */ /* Table17895 */ 0x1f74, /* VMPSADBWrmi */ 0x1f75, /* VMPSADBWrri */ /* Table17897 */ 0x2365, /* VPCLMULQDQrm */ 0x2366, /* VPCLMULQDQrr */ /* Table17899 */ 0x26c3, /* VPERMIL2PSmr */ 0x26c5, /* VPERMIL2PSrr */ /* Table17901 */ 0x26bb, /* VPERMIL2PDmr */ 0x26bd, /* VPERMIL2PDrr */ /* Table17903 */ 0xce4, /* VBLENDVPSrm */ 0xce5, /* VBLENDVPSrr */ /* Table17905 */ 0xce0, /* VBLENDVPDrm */ 0xce1, /* VBLENDVPDrr */ /* Table17907 */ 0x22d5, /* VPBLENDVBrm */ 0x22d6, /* VPBLENDVBrr */ /* Table17909 */ 0x1578, /* VFMADDSUBPS4mr */ 0x157b, /* VFMADDSUBPS4rr_REV */ /* Table17911 */ 0x1570, /* VFMADDSUBPD4mr */ 0x1573, /* VFMADDSUBPD4rr_REV */ /* Table17913 */ 0x1780, /* VFMSUBADDPS4mr */ 0x1783, /* VFMSUBADDPS4rr_REV */ /* Table17915 */ 0x1778, /* VFMSUBADDPD4mr */ 0x177b, /* VFMSUBADDPD4rr_REV */ /* Table17917 */ 0x23f9, /* VPCMPESTRMrm */ 0x23fa, /* VPCMPESTRMrr */ /* Table17919 */ 0x23f7, /* VPCMPESTRIrm */ 0x23f8, /* VPCMPESTRIrr */ /* Table17921 */ 0x2449, /* VPCMPISTRMrm */ 0x244a, /* VPCMPISTRMrr */ /* Table17923 */ 0x2447, /* VPCMPISTRIrm */ 0x2448, /* VPCMPISTRIrr */ /* Table17925 */ 0x148c, /* VFMADDPS4mr */ 0x148f, /* VFMADDPS4rr_REV */ /* Table17927 */ 0x1484, /* VFMADDPD4mr */ 0x1487, /* VFMADDPD4rr_REV */ /* Table17929 */ 0x1498, /* VFMADDSS4mr */ 0x149f, /* VFMADDSS4rr_REV */ /* Table17931 */ 0x1490, /* VFMADDSD4mr */ 0x1497, /* VFMADDSD4rr_REV */ /* Table17933 */ 0x1790, /* VFMSUBPS4mr */ 0x1793, /* VFMSUBPS4rr_REV */ /* Table17935 */ 0x1788, /* VFMSUBPD4mr */ 0x178b, /* VFMSUBPD4rr_REV */ /* Table17937 */ 0x179c, /* VFMSUBSS4mr */ 0x17a3, /* VFMSUBSS4rr_REV */ /* Table17939 */ 0x1794, /* VFMSUBSD4mr */ 0x179b, /* VFMSUBSD4rr_REV */ /* Table17941 */ 0x18dc, /* VFNMADDPS4mr */ 0x18df, /* VFNMADDPS4rr_REV */ /* Table17943 */ 0x18d4, /* VFNMADDPD4mr */ 0x18d7, /* VFNMADDPD4rr_REV */ /* Table17945 */ 0x18e8, /* VFNMADDSS4mr */ 0x18ef, /* VFNMADDSS4rr_REV */ /* Table17947 */ 0x18e0, /* VFNMADDSD4mr */ 0x18e7, /* VFNMADDSD4rr_REV */ /* Table17949 */ 0x1a28, /* VFNMSUBPS4mr */ 0x1a2b, /* VFNMSUBPS4rr_REV */ /* Table17951 */ 0x1a20, /* VFNMSUBPD4mr */ 0x1a23, /* VFNMSUBPD4rr_REV */ /* Table17953 */ 0x1a34, /* VFNMSUBSS4mr */ 0x1a3b, /* VFNMSUBSS4rr_REV */ /* Table17955 */ 0x1a2c, /* VFNMSUBSD4mr */ 0x1a33, /* VFNMSUBSD4rr_REV */ /* Table17957 */ 0xbec, /* VAESKEYGENASSIST128rm */ 0xbed, /* VAESKEYGENASSIST128rr */ /* Table17959 */ 0x95f, /* RORX64mi */ 0x960, /* RORX64ri */ /* Table17961 */ 0x2897, /* VPEXTRQmr */ 0x2898, /* VPEXTRQrr */ /* Table17963 */ 0x28f5, /* VPINSRQrm */ 0x28f6, /* VPINSRQrr */ /* Table17965 */ 0x0, /* */ 0x4b2, /* KSHIFTRWri */ /* Table17967 */ 0x0, /* */ 0x4b1, /* KSHIFTRQri */ /* Table17969 */ 0x0, /* */ 0x4ae, /* KSHIFTLWri */ /* Table17971 */ 0x0, /* */ 0x4ad, /* KSHIFTLQri */ /* Table17973 */ 0x26c4, /* VPERMIL2PSrm */ 0x26c6, /* VPERMIL2PSrr_REV */ /* Table17975 */ 0x26bc, /* VPERMIL2PDrm */ 0x26be, /* VPERMIL2PDrr_REV */ /* Table17977 */ 0x1579, /* VFMADDSUBPS4rm */ 0x157a, /* VFMADDSUBPS4rr */ /* Table17979 */ 0x1571, /* VFMADDSUBPD4rm */ 0x1572, /* VFMADDSUBPD4rr */ /* Table17981 */ 0x1781, /* VFMSUBADDPS4rm */ 0x1782, /* VFMSUBADDPS4rr */ /* Table17983 */ 0x1779, /* VFMSUBADDPD4rm */ 0x177a, /* VFMSUBADDPD4rr */ /* Table17985 */ 0x148d, /* VFMADDPS4rm */ 0x148e, /* VFMADDPS4rr */ /* Table17987 */ 0x1485, /* VFMADDPD4rm */ 0x1486, /* VFMADDPD4rr */ /* Table17989 */ 0x149a, /* VFMADDSS4rm */ 0x149c, /* VFMADDSS4rr */ /* Table17991 */ 0x1492, /* VFMADDSD4rm */ 0x1494, /* VFMADDSD4rr */ /* Table17993 */ 0x1791, /* VFMSUBPS4rm */ 0x1792, /* VFMSUBPS4rr */ /* Table17995 */ 0x1789, /* VFMSUBPD4rm */ 0x178a, /* VFMSUBPD4rr */ /* Table17997 */ 0x179e, /* VFMSUBSS4rm */ 0x17a0, /* VFMSUBSS4rr */ /* Table17999 */ 0x1796, /* VFMSUBSD4rm */ 0x1798, /* VFMSUBSD4rr */ /* Table18001 */ 0x18dd, /* VFNMADDPS4rm */ 0x18de, /* VFNMADDPS4rr */ /* Table18003 */ 0x18d5, /* VFNMADDPD4rm */ 0x18d6, /* VFNMADDPD4rr */ /* Table18005 */ 0x18ea, /* VFNMADDSS4rm */ 0x18ec, /* VFNMADDSS4rr */ /* Table18007 */ 0x18e2, /* VFNMADDSD4rm */ 0x18e4, /* VFNMADDSD4rr */ /* Table18009 */ 0x1a29, /* VFNMSUBPS4rm */ 0x1a2a, /* VFNMSUBPS4rr */ /* Table18011 */ 0x1a21, /* VFNMSUBPD4rm */ 0x1a22, /* VFNMSUBPD4rr */ /* Table18013 */ 0x1a36, /* VFNMSUBSS4rm */ 0x1a38, /* VFNMSUBSS4rr */ /* Table18015 */ 0x1a2e, /* VFNMSUBSD4rm */ 0x1a30, /* VFNMSUBSD4rr */ /* Table18017 */ 0x1b68, /* VGF2P8AFFINEQBrmi */ 0x1b69, /* VGF2P8AFFINEQBrri */ /* Table18019 */ 0x1b49, /* VGF2P8AFFINEINVQBrmi */ 0x1b4a, /* VGF2P8AFFINEINVQBrri */ /* Table18021 */ 0x2275, /* VPBLENDDYrmi */ 0x2276, /* VPBLENDDYrri */ /* Table18023 */ 0x2705, /* VPERMILPSYmi */ 0x2706, /* VPERMILPSYri */ /* Table18025 */ 0x26c7, /* VPERMILPDYmi */ 0x26c8, /* VPERMILPDYri */ /* Table18027 */ 0x25fd, /* VPERM2F128rm */ 0x25fe, /* VPERM2F128rr */ /* Table18029 */ 0x384b, /* VROUNDPSYm */ 0x384c, /* VROUNDPSYr */ /* Table18031 */ 0x3847, /* VROUNDPDYm */ 0x3848, /* VROUNDPDYr */ /* Table18033 */ 0xcda, /* VBLENDPSYrmi */ 0xcdb, /* VBLENDPSYrri */ /* Table18035 */ 0xcd6, /* VBLENDPDYrmi */ 0xcd7, /* VBLENDPDYrri */ /* Table18037 */ 0x22d7, /* VPBLENDWYrmi */ 0x22d8, /* VPBLENDWYrri */ /* Table18039 */ 0x21bf, /* VPALIGNRYrmi */ 0x21c0, /* VPALIGNRYrri */ /* Table18041 */ 0x1b90, /* VINSERTF128rm */ 0x1b91, /* VINSERTF128rr */ /* Table18043 */ 0x12c2, /* VEXTRACTF128mr */ 0x12c3, /* VEXTRACTF128rr */ /* Table18045 */ 0xf42, /* VCVTPS2PHYmr */ 0xf43, /* VCVTPS2PHYrr */ /* Table18047 */ 0x1bb6, /* VINSERTI128rm */ 0x1bb7, /* VINSERTI128rr */ /* Table18049 */ 0x12e2, /* VEXTRACTI128mr */ 0x12e3, /* VEXTRACTI128rr */ /* Table18051 */ 0x127e, /* VDPPSYrmi */ 0x127f, /* VDPPSYrri */ /* Table18053 */ 0x1f72, /* VMPSADBWYrmi */ 0x1f73, /* VMPSADBWYrri */ /* Table18055 */ 0x235d, /* VPCLMULQDQYrm */ 0x235e, /* VPCLMULQDQYrr */ /* Table18057 */ 0x25ff, /* VPERM2I128rm */ 0x2600, /* VPERM2I128rr */ /* Table18059 */ 0x26bf, /* VPERMIL2PSYmr */ 0x26c1, /* VPERMIL2PSYrr */ /* Table18061 */ 0x26b7, /* VPERMIL2PDYmr */ 0x26b9, /* VPERMIL2PDYrr */ /* Table18063 */ 0xce2, /* VBLENDVPSYrm */ 0xce3, /* VBLENDVPSYrr */ /* Table18065 */ 0xcde, /* VBLENDVPDYrm */ 0xcdf, /* VBLENDVPDYrr */ /* Table18067 */ 0x22d3, /* VPBLENDVBYrm */ 0x22d4, /* VPBLENDVBYrr */ /* Table18069 */ 0x1574, /* VFMADDSUBPS4Ymr */ 0x1577, /* VFMADDSUBPS4Yrr_REV */ /* Table18071 */ 0x156c, /* VFMADDSUBPD4Ymr */ 0x156f, /* VFMADDSUBPD4Yrr_REV */ /* Table18073 */ 0x177c, /* VFMSUBADDPS4Ymr */ 0x177f, /* VFMSUBADDPS4Yrr_REV */ /* Table18075 */ 0x1774, /* VFMSUBADDPD4Ymr */ 0x1777, /* VFMSUBADDPD4Yrr_REV */ /* Table18077 */ 0x1488, /* VFMADDPS4Ymr */ 0x148b, /* VFMADDPS4Yrr_REV */ /* Table18079 */ 0x1480, /* VFMADDPD4Ymr */ 0x1483, /* VFMADDPD4Yrr_REV */ /* Table18081 */ 0x178c, /* VFMSUBPS4Ymr */ 0x178f, /* VFMSUBPS4Yrr_REV */ /* Table18083 */ 0x1784, /* VFMSUBPD4Ymr */ 0x1787, /* VFMSUBPD4Yrr_REV */ /* Table18085 */ 0x18d8, /* VFNMADDPS4Ymr */ 0x18db, /* VFNMADDPS4Yrr_REV */ /* Table18087 */ 0x18d0, /* VFNMADDPD4Ymr */ 0x18d3, /* VFNMADDPD4Yrr_REV */ /* Table18089 */ 0x1a24, /* VFNMSUBPS4Ymr */ 0x1a27, /* VFNMSUBPS4Yrr_REV */ /* Table18091 */ 0x1a1c, /* VFNMSUBPD4Ymr */ 0x1a1f, /* VFNMSUBPD4Yrr_REV */ /* Table18093 */ 0x277d, /* VPERMQYmi */ 0x277e, /* VPERMQYri */ /* Table18095 */ 0x2743, /* VPERMPDYmi */ 0x2744, /* VPERMPDYri */ /* Table18097 */ 0x26c0, /* VPERMIL2PSYrm */ 0x26c2, /* VPERMIL2PSYrr_REV */ /* Table18099 */ 0x26b8, /* VPERMIL2PDYrm */ 0x26ba, /* VPERMIL2PDYrr_REV */ /* Table18101 */ 0x1575, /* VFMADDSUBPS4Yrm */ 0x1576, /* VFMADDSUBPS4Yrr */ /* Table18103 */ 0x156d, /* VFMADDSUBPD4Yrm */ 0x156e, /* VFMADDSUBPD4Yrr */ /* Table18105 */ 0x177d, /* VFMSUBADDPS4Yrm */ 0x177e, /* VFMSUBADDPS4Yrr */ /* Table18107 */ 0x1775, /* VFMSUBADDPD4Yrm */ 0x1776, /* VFMSUBADDPD4Yrr */ /* Table18109 */ 0x1489, /* VFMADDPS4Yrm */ 0x148a, /* VFMADDPS4Yrr */ /* Table18111 */ 0x1481, /* VFMADDPD4Yrm */ 0x1482, /* VFMADDPD4Yrr */ /* Table18113 */ 0x178d, /* VFMSUBPS4Yrm */ 0x178e, /* VFMSUBPS4Yrr */ /* Table18115 */ 0x1785, /* VFMSUBPD4Yrm */ 0x1786, /* VFMSUBPD4Yrr */ /* Table18117 */ 0x18d9, /* VFNMADDPS4Yrm */ 0x18da, /* VFNMADDPS4Yrr */ /* Table18119 */ 0x18d1, /* VFNMADDPD4Yrm */ 0x18d2, /* VFNMADDPD4Yrr */ /* Table18121 */ 0x1a25, /* VFNMSUBPS4Yrm */ 0x1a26, /* VFNMSUBPS4Yrr */ /* Table18123 */ 0x1a1d, /* VFNMSUBPD4Yrm */ 0x1a1e, /* VFNMSUBPD4Yrr */ /* Table18125 */ 0x1b4b, /* VGF2P8AFFINEQBYrmi */ 0x1b4c, /* VGF2P8AFFINEQBYrri */ /* Table18127 */ 0x1b2c, /* VGF2P8AFFINEINVQBYrmi */ 0x1b2d, /* VGF2P8AFFINEINVQBYrri */ /* Table18129 */ 0xbf1, /* VALIGNDZ128rmi */ 0xbf4, /* VALIGNDZ128rri */ /* Table18131 */ 0x270c, /* VPERMILPSZ128mi */ 0x270f, /* VPERMILPSZ128ri */ /* Table18133 */ 0x3816, /* VRNDSCALEPSZ128rmi */ 0x3819, /* VRNDSCALEPSZ128rri */ /* Table18135 */ 0x383d, /* VRNDSCALESSZm_Int */ 0x3841, /* VRNDSCALESSZr_Int */ /* Table18137 */ 0x21c1, /* VPALIGNRZ128rmi */ 0x21c4, /* VPALIGNRZ128rri */ /* Table18139 */ 0x288d, /* VPEXTRBZmr */ 0x288e, /* VPEXTRBZrr */ /* Table18141 */ 0x2899, /* VPEXTRWZmr */ 0x289b, /* VPEXTRWZrr_REV */ /* Table18143 */ 0x2891, /* VPEXTRDZmr */ 0x2892, /* VPEXTRDZrr */ /* Table18145 */ 0x1302, /* VEXTRACTPSZmr */ 0x1303, /* VEXTRACTPSZrr */ /* Table18147 */ 0xf44, /* VCVTPS2PHZ128mr */ 0xf46, /* VCVTPS2PHZ128rr */ /* Table18149 */ 0x2487, /* VPCMPUDZ128rmi */ 0x248f, /* VPCMPUDZ128rri */ /* Table18151 */ 0x2387, /* VPCMPDZ128rmi */ 0x238f, /* VPCMPDZ128rri */ /* Table18153 */ 0x28eb, /* VPINSRBZrm */ 0x28ec, /* VPINSRBZrr */ /* Table18155 */ 0x1bdc, /* VINSERTPSZrm */ 0x1bdd, /* VINSERTPSZrr */ /* Table18157 */ 0x28ef, /* VPINSRDZrm */ 0x28f0, /* VPINSRDZrr */ /* Table18159 */ 0x3528, /* VPTERNLOGDZ128rmi */ 0x352b, /* VPTERNLOGDZ128rri */ /* Table18161 */ 0x1aff, /* VGETMANTPSZ128rmi */ 0x1b02, /* VGETMANTPSZ128rri */ /* Table18163 */ 0x1b23, /* VGETMANTSSZrmi */ 0x1b26, /* VGETMANTSSZrri */ /* Table18165 */ 0x246f, /* VPCMPUBZ128rmi */ 0x2473, /* VPCMPUBZ128rri */ /* Table18167 */ 0x236f, /* VPCMPBZ128rmi */ 0x2373, /* VPCMPBZ128rri */ /* Table18169 */ 0x1208, /* VDBPSADBWZ128rmi */ 0x120b, /* VDBPSADBWZ128rri */ /* Table18171 */ 0x235f, /* VPCLMULQDQZ128rm */ 0x2360, /* VPCLMULQDQZ128rr */ /* Table18173 */ 0x3706, /* VRANGEPSZ128rmi */ 0x3709, /* VRANGEPSZ128rri */ /* Table18175 */ 0x372a, /* VRANGESSZrmi */ 0x372d, /* VRANGESSZrri */ /* Table18177 */ 0x1327, /* VFIXUPIMMPSZ128rmi */ 0x132a, /* VFIXUPIMMPSZ128rri */ /* Table18179 */ 0x134b, /* VFIXUPIMMSSZrmi */ 0x134e, /* VFIXUPIMMSSZrri */ /* Table18181 */ 0x37c8, /* VREDUCEPSZ128rmi */ 0x37cb, /* VREDUCEPSZ128rri */ /* Table18183 */ 0x37ec, /* VREDUCESSZrmi */ 0x37ef, /* VREDUCESSZrri */ /* Table18185 */ 0x1a4e, /* VFPCLASSPSZ128rm */ 0x1a52, /* VFPCLASSPSZ128rr */ /* Table18187 */ 0x1a64, /* VFPCLASSSSZrm */ 0x1a66, /* VFPCLASSSSZrr */ /* Table18189 */ 0x301b, /* VPSHLDDZ128rmi */ 0x301e, /* VPSHLDDZ128rri */ /* Table18191 */ 0x30b7, /* VPSHRDDZ128rmi */ 0x30ba, /* VPSHRDDZ128rri */ /* Table18193 */ 0xc0c, /* VALIGNQZ128rmi */ 0xc0f, /* VALIGNQZ128rri */ /* Table18195 */ 0x26ce, /* VPERMILPDZ128mi */ 0x26d1, /* VPERMILPDZ128ri */ /* Table18197 */ 0x37f8, /* VRNDSCALEPDZ128rmi */ 0x37fb, /* VRNDSCALEPDZ128rri */ /* Table18199 */ 0x3832, /* VRNDSCALESDZm_Int */ 0x3836, /* VRNDSCALESDZr_Int */ /* Table18201 */ 0x2895, /* VPEXTRQZmr */ 0x2896, /* VPEXTRQZrr */ /* Table18203 */ 0x24ab, /* VPCMPUQZ128rmi */ 0x24b3, /* VPCMPUQZ128rri */ /* Table18205 */ 0x244b, /* VPCMPQZ128rmi */ 0x2453, /* VPCMPQZ128rri */ /* Table18207 */ 0x28f3, /* VPINSRQZrm */ 0x28f4, /* VPINSRQZrr */ /* Table18209 */ 0x3543, /* VPTERNLOGQZ128rmi */ 0x3546, /* VPTERNLOGQZ128rri */ /* Table18211 */ 0x1ae1, /* VGETMANTPDZ128rmi */ 0x1ae4, /* VGETMANTPDZ128rri */ /* Table18213 */ 0x1b1a, /* VGETMANTSDZrmi */ 0x1b1d, /* VGETMANTSDZrri */ /* Table18215 */ 0x24cf, /* VPCMPUWZ128rmi */ 0x24d3, /* VPCMPUWZ128rri */ /* Table18217 */ 0x24e7, /* VPCMPWZ128rmi */ 0x24eb, /* VPCMPWZ128rri */ /* Table18219 */ 0x36e8, /* VRANGEPDZ128rmi */ 0x36eb, /* VRANGEPDZ128rri */ /* Table18221 */ 0x3721, /* VRANGESDZrmi */ 0x3724, /* VRANGESDZrri */ /* Table18223 */ 0x1309, /* VFIXUPIMMPDZ128rmi */ 0x130c, /* VFIXUPIMMPDZ128rri */ /* Table18225 */ 0x1342, /* VFIXUPIMMSDZrmi */ 0x1345, /* VFIXUPIMMSDZrri */ /* Table18227 */ 0x37aa, /* VREDUCEPDZ128rmi */ 0x37ad, /* VREDUCEPDZ128rri */ /* Table18229 */ 0x37e3, /* VREDUCESDZrmi */ 0x37e6, /* VREDUCESDZrri */ /* Table18231 */ 0x1a3c, /* VFPCLASSPDZ128rm */ 0x1a40, /* VFPCLASSPDZ128rr */ /* Table18233 */ 0x1a60, /* VFPCLASSSDZrm */ 0x1a62, /* VFPCLASSSDZrr */ /* Table18235 */ 0x3096, /* VPSHLDWZ128rmi */ 0x3099, /* VPSHLDWZ128rri */ /* Table18237 */ 0x3036, /* VPSHLDQZ128rmi */ 0x3039, /* VPSHLDQZ128rri */ /* Table18239 */ 0x3132, /* VPSHRDWZ128rmi */ 0x3135, /* VPSHRDWZ128rri */ /* Table18241 */ 0x30d2, /* VPSHRDQZ128rmi */ 0x30d5, /* VPSHRDQZ128rri */ /* Table18243 */ 0x1b50, /* VGF2P8AFFINEQBZ128rmi */ 0x1b53, /* VGF2P8AFFINEQBZ128rri */ /* Table18245 */ 0x1b31, /* VGF2P8AFFINEINVQBZ128rmi */ 0x1b34, /* VGF2P8AFFINEINVQBZ128rri */ /* Table18247 */ 0xbfa, /* VALIGNDZ256rmi */ 0xbfd, /* VALIGNDZ256rri */ /* Table18249 */ 0x271e, /* VPERMILPSZ256mi */ 0x2721, /* VPERMILPSZ256ri */ /* Table18251 */ 0x381f, /* VRNDSCALEPSZ256rmi */ 0x3822, /* VRNDSCALEPSZ256rri */ /* Table18253 */ 0x21c7, /* VPALIGNRZ256rmi */ 0x21ca, /* VPALIGNRZ256rri */ /* Table18255 */ 0x1b92, /* VINSERTF32x4Z256rm */ 0x1b95, /* VINSERTF32x4Z256rr */ /* Table18257 */ 0x12c4, /* VEXTRACTF32x4Z256mr */ 0x12c6, /* VEXTRACTF32x4Z256rr */ /* Table18259 */ 0xf49, /* VCVTPS2PHZ256mr */ 0xf4b, /* VCVTPS2PHZ256rr */ /* Table18261 */ 0x2493, /* VPCMPUDZ256rmi */ 0x249b, /* VPCMPUDZ256rri */ /* Table18263 */ 0x2393, /* VPCMPDZ256rmi */ 0x239b, /* VPCMPDZ256rri */ /* Table18265 */ 0x3930, /* VSHUFF32X4Z256rmi */ 0x3933, /* VSHUFF32X4Z256rri */ /* Table18267 */ 0x3531, /* VPTERNLOGDZ256rmi */ 0x3534, /* VPTERNLOGDZ256rri */ /* Table18269 */ 0x1b08, /* VGETMANTPSZ256rmi */ 0x1b0b, /* VGETMANTPSZ256rri */ /* Table18271 */ 0x1bb8, /* VINSERTI32x4Z256rm */ 0x1bbb, /* VINSERTI32x4Z256rr */ /* Table18273 */ 0x12e4, /* VEXTRACTI32x4Z256mr */ 0x12e6, /* VEXTRACTI32x4Z256rr */ /* Table18275 */ 0x2477, /* VPCMPUBZ256rmi */ 0x247b, /* VPCMPUBZ256rri */ /* Table18277 */ 0x2377, /* VPCMPBZ256rmi */ 0x237b, /* VPCMPBZ256rri */ /* Table18279 */ 0x120e, /* VDBPSADBWZ256rmi */ 0x1211, /* VDBPSADBWZ256rri */ /* Table18281 */ 0x3954, /* VSHUFI32X4Z256rmi */ 0x3957, /* VSHUFI32X4Z256rri */ /* Table18283 */ 0x2361, /* VPCLMULQDQZ256rm */ 0x2362, /* VPCLMULQDQZ256rr */ /* Table18285 */ 0x370f, /* VRANGEPSZ256rmi */ 0x3712, /* VRANGEPSZ256rri */ /* Table18287 */ 0x1330, /* VFIXUPIMMPSZ256rmi */ 0x1333, /* VFIXUPIMMPSZ256rri */ /* Table18289 */ 0x37d1, /* VREDUCEPSZ256rmi */ 0x37d4, /* VREDUCEPSZ256rri */ /* Table18291 */ 0x1a54, /* VFPCLASSPSZ256rm */ 0x1a58, /* VFPCLASSPSZ256rr */ /* Table18293 */ 0x3024, /* VPSHLDDZ256rmi */ 0x3027, /* VPSHLDDZ256rri */ /* Table18295 */ 0x30c0, /* VPSHRDDZ256rmi */ 0x30c3, /* VPSHRDDZ256rri */ /* Table18297 */ 0x2782, /* VPERMQZ256mi */ 0x2785, /* VPERMQZ256ri */ /* Table18299 */ 0x2748, /* VPERMPDZ256mi */ 0x274b, /* VPERMPDZ256ri */ /* Table18301 */ 0xc15, /* VALIGNQZ256rmi */ 0xc18, /* VALIGNQZ256rri */ /* Table18303 */ 0x26e0, /* VPERMILPDZ256mi */ 0x26e3, /* VPERMILPDZ256ri */ /* Table18305 */ 0x3801, /* VRNDSCALEPDZ256rmi */ 0x3804, /* VRNDSCALEPDZ256rri */ /* Table18307 */ 0x1ba4, /* VINSERTF64x2Z256rm */ 0x1ba7, /* VINSERTF64x2Z256rr */ /* Table18309 */ 0x12d3, /* VEXTRACTF64x2Z256mr */ 0x12d5, /* VEXTRACTF64x2Z256rr */ /* Table18311 */ 0x24b7, /* VPCMPUQZ256rmi */ 0x24bf, /* VPCMPUQZ256rri */ /* Table18313 */ 0x2457, /* VPCMPQZ256rmi */ 0x245f, /* VPCMPQZ256rri */ /* Table18315 */ 0x3942, /* VSHUFF64X2Z256rmi */ 0x3945, /* VSHUFF64X2Z256rri */ /* Table18317 */ 0x354c, /* VPTERNLOGQZ256rmi */ 0x354f, /* VPTERNLOGQZ256rri */ /* Table18319 */ 0x1aea, /* VGETMANTPDZ256rmi */ 0x1aed, /* VGETMANTPDZ256rri */ /* Table18321 */ 0x1bca, /* VINSERTI64x2Z256rm */ 0x1bcd, /* VINSERTI64x2Z256rr */ /* Table18323 */ 0x12f3, /* VEXTRACTI64x2Z256mr */ 0x12f5, /* VEXTRACTI64x2Z256rr */ /* Table18325 */ 0x24d7, /* VPCMPUWZ256rmi */ 0x24db, /* VPCMPUWZ256rri */ /* Table18327 */ 0x24ef, /* VPCMPWZ256rmi */ 0x24f3, /* VPCMPWZ256rri */ /* Table18329 */ 0x3966, /* VSHUFI64X2Z256rmi */ 0x3969, /* VSHUFI64X2Z256rri */ /* Table18331 */ 0x36f1, /* VRANGEPDZ256rmi */ 0x36f4, /* VRANGEPDZ256rri */ /* Table18333 */ 0x1312, /* VFIXUPIMMPDZ256rmi */ 0x1315, /* VFIXUPIMMPDZ256rri */ /* Table18335 */ 0x37b3, /* VREDUCEPDZ256rmi */ 0x37b6, /* VREDUCEPDZ256rri */ /* Table18337 */ 0x1a42, /* VFPCLASSPDZ256rm */ 0x1a46, /* VFPCLASSPDZ256rr */ /* Table18339 */ 0x309c, /* VPSHLDWZ256rmi */ 0x309f, /* VPSHLDWZ256rri */ /* Table18341 */ 0x303f, /* VPSHLDQZ256rmi */ 0x3042, /* VPSHLDQZ256rri */ /* Table18343 */ 0x3138, /* VPSHRDWZ256rmi */ 0x313b, /* VPSHRDWZ256rri */ /* Table18345 */ 0x30db, /* VPSHRDQZ256rmi */ 0x30de, /* VPSHRDQZ256rri */ /* Table18347 */ 0x1b59, /* VGF2P8AFFINEQBZ256rmi */ 0x1b5c, /* VGF2P8AFFINEQBZ256rri */ /* Table18349 */ 0x1b3a, /* VGF2P8AFFINEINVQBZ256rmi */ 0x1b3d, /* VGF2P8AFFINEINVQBZ256rri */ /* Table18351 */ 0xc03, /* VALIGNDZrmi */ 0xc06, /* VALIGNDZrri */ /* Table18353 */ 0x2730, /* VPERMILPSZmi */ 0x2733, /* VPERMILPSZri */ /* Table18355 */ 0x3828, /* VRNDSCALEPSZrmi */ 0x382b, /* VRNDSCALEPSZrri */ /* Table18357 */ 0x21cd, /* VPALIGNRZrmi */ 0x21d0, /* VPALIGNRZrri */ /* Table18359 */ 0x1b98, /* VINSERTF32x4Zrm */ 0x1b9b, /* VINSERTF32x4Zrr */ /* Table18361 */ 0x12c9, /* VEXTRACTF32x4Zmr */ 0x12cb, /* VEXTRACTF32x4Zrr */ /* Table18363 */ 0x1b9e, /* VINSERTF32x8Zrm */ 0x1ba1, /* VINSERTF32x8Zrr */ /* Table18365 */ 0x12ce, /* VEXTRACTF32x8Zmr */ 0x12d0, /* VEXTRACTF32x8Zrr */ /* Table18367 */ 0xf4e, /* VCVTPS2PHZmr */ 0xf50, /* VCVTPS2PHZrr */ /* Table18369 */ 0x249f, /* VPCMPUDZrmi */ 0x24a7, /* VPCMPUDZrri */ /* Table18371 */ 0x239f, /* VPCMPDZrmi */ 0x23a7, /* VPCMPDZrri */ /* Table18373 */ 0x3939, /* VSHUFF32X4Zrmi */ 0x393c, /* VSHUFF32X4Zrri */ /* Table18375 */ 0x353a, /* VPTERNLOGDZrmi */ 0x353d, /* VPTERNLOGDZrri */ /* Table18377 */ 0x1b11, /* VGETMANTPSZrmi */ 0x1b14, /* VGETMANTPSZrri */ /* Table18379 */ 0x1bbe, /* VINSERTI32x4Zrm */ 0x1bc1, /* VINSERTI32x4Zrr */ /* Table18381 */ 0x12e9, /* VEXTRACTI32x4Zmr */ 0x12eb, /* VEXTRACTI32x4Zrr */ /* Table18383 */ 0x1bc4, /* VINSERTI32x8Zrm */ 0x1bc7, /* VINSERTI32x8Zrr */ /* Table18385 */ 0x12ee, /* VEXTRACTI32x8Zmr */ 0x12f0, /* VEXTRACTI32x8Zrr */ /* Table18387 */ 0x247f, /* VPCMPUBZrmi */ 0x2483, /* VPCMPUBZrri */ /* Table18389 */ 0x237f, /* VPCMPBZrmi */ 0x2383, /* VPCMPBZrri */ /* Table18391 */ 0x1214, /* VDBPSADBWZrmi */ 0x1217, /* VDBPSADBWZrri */ /* Table18393 */ 0x395d, /* VSHUFI32X4Zrmi */ 0x3960, /* VSHUFI32X4Zrri */ /* Table18395 */ 0x2363, /* VPCLMULQDQZrm */ 0x2364, /* VPCLMULQDQZrr */ /* Table18397 */ 0x3718, /* VRANGEPSZrmi */ 0x371b, /* VRANGEPSZrri */ /* Table18399 */ 0x1339, /* VFIXUPIMMPSZrmi */ 0x133c, /* VFIXUPIMMPSZrri */ /* Table18401 */ 0x37da, /* VREDUCEPSZrmi */ 0x37dd, /* VREDUCEPSZrri */ /* Table18403 */ 0x1a5a, /* VFPCLASSPSZrm */ 0x1a5e, /* VFPCLASSPSZrr */ /* Table18405 */ 0x302d, /* VPSHLDDZrmi */ 0x3030, /* VPSHLDDZrri */ /* Table18407 */ 0x30c9, /* VPSHRDDZrmi */ 0x30cc, /* VPSHRDDZrri */ /* Table18409 */ 0x2794, /* VPERMQZmi */ 0x2797, /* VPERMQZri */ /* Table18411 */ 0x275a, /* VPERMPDZmi */ 0x275d, /* VPERMPDZri */ /* Table18413 */ 0xc1e, /* VALIGNQZrmi */ 0xc21, /* VALIGNQZrri */ /* Table18415 */ 0x26f2, /* VPERMILPDZmi */ 0x26f5, /* VPERMILPDZri */ /* Table18417 */ 0x380a, /* VRNDSCALEPDZrmi */ 0x380d, /* VRNDSCALEPDZrri */ /* Table18419 */ 0x1baa, /* VINSERTF64x2Zrm */ 0x1bad, /* VINSERTF64x2Zrr */ /* Table18421 */ 0x12d8, /* VEXTRACTF64x2Zmr */ 0x12da, /* VEXTRACTF64x2Zrr */ /* Table18423 */ 0x1bb0, /* VINSERTF64x4Zrm */ 0x1bb3, /* VINSERTF64x4Zrr */ /* Table18425 */ 0x12dd, /* VEXTRACTF64x4Zmr */ 0x12df, /* VEXTRACTF64x4Zrr */ /* Table18427 */ 0x24c3, /* VPCMPUQZrmi */ 0x24cb, /* VPCMPUQZrri */ /* Table18429 */ 0x2463, /* VPCMPQZrmi */ 0x246b, /* VPCMPQZrri */ /* Table18431 */ 0x394b, /* VSHUFF64X2Zrmi */ 0x394e, /* VSHUFF64X2Zrri */ /* Table18433 */ 0x3555, /* VPTERNLOGQZrmi */ 0x3558, /* VPTERNLOGQZrri */ /* Table18435 */ 0x1af3, /* VGETMANTPDZrmi */ 0x1af6, /* VGETMANTPDZrri */ /* Table18437 */ 0x1bd0, /* VINSERTI64x2Zrm */ 0x1bd3, /* VINSERTI64x2Zrr */ /* Table18439 */ 0x12f8, /* VEXTRACTI64x2Zmr */ 0x12fa, /* VEXTRACTI64x2Zrr */ /* Table18441 */ 0x1bd6, /* VINSERTI64x4Zrm */ 0x1bd9, /* VINSERTI64x4Zrr */ /* Table18443 */ 0x12fd, /* VEXTRACTI64x4Zmr */ 0x12ff, /* VEXTRACTI64x4Zrr */ /* Table18445 */ 0x24df, /* VPCMPUWZrmi */ 0x24e3, /* VPCMPUWZrri */ /* Table18447 */ 0x24f7, /* VPCMPWZrmi */ 0x24fb, /* VPCMPWZrri */ /* Table18449 */ 0x396f, /* VSHUFI64X2Zrmi */ 0x3972, /* VSHUFI64X2Zrri */ /* Table18451 */ 0x36fa, /* VRANGEPDZrmi */ 0x36fd, /* VRANGEPDZrri */ /* Table18453 */ 0x131b, /* VFIXUPIMMPDZrmi */ 0x131e, /* VFIXUPIMMPDZrri */ /* Table18455 */ 0x37bc, /* VREDUCEPDZrmi */ 0x37bf, /* VREDUCEPDZrri */ /* Table18457 */ 0x1a48, /* VFPCLASSPDZrm */ 0x1a4c, /* VFPCLASSPDZrr */ /* Table18459 */ 0x30a2, /* VPSHLDWZrmi */ 0x30a5, /* VPSHLDWZrri */ /* Table18461 */ 0x3048, /* VPSHLDQZrmi */ 0x304b, /* VPSHLDQZrri */ /* Table18463 */ 0x313e, /* VPSHRDWZrmi */ 0x3141, /* VPSHRDWZrri */ /* Table18465 */ 0x30e4, /* VPSHRDQZrmi */ 0x30e7, /* VPSHRDQZrri */ /* Table18467 */ 0x1b62, /* VGF2P8AFFINEQBZrmi */ 0x1b65, /* VGF2P8AFFINEQBZrri */ /* Table18469 */ 0x1b43, /* VGF2P8AFFINEINVQBZrmi */ 0x1b46, /* VGF2P8AFFINEINVQBZrri */ /* Table18471 */ 0xbf2, /* VALIGNDZ128rmik */ 0xbf5, /* VALIGNDZ128rrik */ /* Table18473 */ 0x270d, /* VPERMILPSZ128mik */ 0x2710, /* VPERMILPSZ128rik */ /* Table18475 */ 0x3817, /* VRNDSCALEPSZ128rmik */ 0x381a, /* VRNDSCALEPSZ128rrik */ /* Table18477 */ 0x383e, /* VRNDSCALESSZm_Intk */ 0x3842, /* VRNDSCALESSZr_Intk */ /* Table18479 */ 0x21c2, /* VPALIGNRZ128rmik */ 0x21c5, /* VPALIGNRZ128rrik */ /* Table18481 */ 0xf45, /* VCVTPS2PHZ128mrk */ 0xf47, /* VCVTPS2PHZ128rrk */ /* Table18483 */ 0x248d, /* VPCMPUDZ128rmik */ 0x2491, /* VPCMPUDZ128rrik */ /* Table18485 */ 0x238d, /* VPCMPDZ128rmik */ 0x2391, /* VPCMPDZ128rrik */ /* Table18487 */ 0x3529, /* VPTERNLOGDZ128rmik */ 0x352c, /* VPTERNLOGDZ128rrik */ /* Table18489 */ 0x1b00, /* VGETMANTPSZ128rmik */ 0x1b03, /* VGETMANTPSZ128rrik */ /* Table18491 */ 0x1b24, /* VGETMANTSSZrmik */ 0x1b2a, /* VGETMANTSSZrrik */ /* Table18493 */ 0x2471, /* VPCMPUBZ128rmik */ 0x2475, /* VPCMPUBZ128rrik */ /* Table18495 */ 0x2371, /* VPCMPBZ128rmik */ 0x2375, /* VPCMPBZ128rrik */ /* Table18497 */ 0x1209, /* VDBPSADBWZ128rmik */ 0x120c, /* VDBPSADBWZ128rrik */ /* Table18499 */ 0x3707, /* VRANGEPSZ128rmik */ 0x370a, /* VRANGEPSZ128rrik */ /* Table18501 */ 0x372b, /* VRANGESSZrmik */ 0x3731, /* VRANGESSZrrik */ /* Table18503 */ 0x1328, /* VFIXUPIMMPSZ128rmik */ 0x132b, /* VFIXUPIMMPSZ128rrik */ /* Table18505 */ 0x134c, /* VFIXUPIMMSSZrmik */ 0x1352, /* VFIXUPIMMSSZrrik */ /* Table18507 */ 0x37c9, /* VREDUCEPSZ128rmik */ 0x37cc, /* VREDUCEPSZ128rrik */ /* Table18509 */ 0x37ed, /* VREDUCESSZrmik */ 0x37f3, /* VREDUCESSZrrik */ /* Table18511 */ 0x1a51, /* VFPCLASSPSZ128rmk */ 0x1a53, /* VFPCLASSPSZ128rrk */ /* Table18513 */ 0x1a65, /* VFPCLASSSSZrmk */ 0x1a67, /* VFPCLASSSSZrrk */ /* Table18515 */ 0x301c, /* VPSHLDDZ128rmik */ 0x301f, /* VPSHLDDZ128rrik */ /* Table18517 */ 0x30b8, /* VPSHRDDZ128rmik */ 0x30bb, /* VPSHRDDZ128rrik */ /* Table18519 */ 0xc0d, /* VALIGNQZ128rmik */ 0xc10, /* VALIGNQZ128rrik */ /* Table18521 */ 0x26cf, /* VPERMILPDZ128mik */ 0x26d2, /* VPERMILPDZ128rik */ /* Table18523 */ 0x37f9, /* VRNDSCALEPDZ128rmik */ 0x37fc, /* VRNDSCALEPDZ128rrik */ /* Table18525 */ 0x3833, /* VRNDSCALESDZm_Intk */ 0x3837, /* VRNDSCALESDZr_Intk */ /* Table18527 */ 0x24b1, /* VPCMPUQZ128rmik */ 0x24b5, /* VPCMPUQZ128rrik */ /* Table18529 */ 0x2451, /* VPCMPQZ128rmik */ 0x2455, /* VPCMPQZ128rrik */ /* Table18531 */ 0x3544, /* VPTERNLOGQZ128rmik */ 0x3547, /* VPTERNLOGQZ128rrik */ /* Table18533 */ 0x1ae2, /* VGETMANTPDZ128rmik */ 0x1ae5, /* VGETMANTPDZ128rrik */ /* Table18535 */ 0x1b1b, /* VGETMANTSDZrmik */ 0x1b21, /* VGETMANTSDZrrik */ /* Table18537 */ 0x24d1, /* VPCMPUWZ128rmik */ 0x24d5, /* VPCMPUWZ128rrik */ /* Table18539 */ 0x24e9, /* VPCMPWZ128rmik */ 0x24ed, /* VPCMPWZ128rrik */ /* Table18541 */ 0x36e9, /* VRANGEPDZ128rmik */ 0x36ec, /* VRANGEPDZ128rrik */ /* Table18543 */ 0x3722, /* VRANGESDZrmik */ 0x3728, /* VRANGESDZrrik */ /* Table18545 */ 0x130a, /* VFIXUPIMMPDZ128rmik */ 0x130d, /* VFIXUPIMMPDZ128rrik */ /* Table18547 */ 0x1343, /* VFIXUPIMMSDZrmik */ 0x1349, /* VFIXUPIMMSDZrrik */ /* Table18549 */ 0x37ab, /* VREDUCEPDZ128rmik */ 0x37ae, /* VREDUCEPDZ128rrik */ /* Table18551 */ 0x37e4, /* VREDUCESDZrmik */ 0x37ea, /* VREDUCESDZrrik */ /* Table18553 */ 0x1a3f, /* VFPCLASSPDZ128rmk */ 0x1a41, /* VFPCLASSPDZ128rrk */ /* Table18555 */ 0x1a61, /* VFPCLASSSDZrmk */ 0x1a63, /* VFPCLASSSDZrrk */ /* Table18557 */ 0x3097, /* VPSHLDWZ128rmik */ 0x309a, /* VPSHLDWZ128rrik */ /* Table18559 */ 0x3037, /* VPSHLDQZ128rmik */ 0x303a, /* VPSHLDQZ128rrik */ /* Table18561 */ 0x3133, /* VPSHRDWZ128rmik */ 0x3136, /* VPSHRDWZ128rrik */ /* Table18563 */ 0x30d3, /* VPSHRDQZ128rmik */ 0x30d6, /* VPSHRDQZ128rrik */ /* Table18565 */ 0x1b51, /* VGF2P8AFFINEQBZ128rmik */ 0x1b54, /* VGF2P8AFFINEQBZ128rrik */ /* Table18567 */ 0x1b32, /* VGF2P8AFFINEINVQBZ128rmik */ 0x1b35, /* VGF2P8AFFINEINVQBZ128rrik */ /* Table18569 */ 0xbfb, /* VALIGNDZ256rmik */ 0xbfe, /* VALIGNDZ256rrik */ /* Table18571 */ 0x271f, /* VPERMILPSZ256mik */ 0x2722, /* VPERMILPSZ256rik */ /* Table18573 */ 0x3820, /* VRNDSCALEPSZ256rmik */ 0x3823, /* VRNDSCALEPSZ256rrik */ /* Table18575 */ 0x21c8, /* VPALIGNRZ256rmik */ 0x21cb, /* VPALIGNRZ256rrik */ /* Table18577 */ 0x1b93, /* VINSERTF32x4Z256rmk */ 0x1b96, /* VINSERTF32x4Z256rrk */ /* Table18579 */ 0x12c5, /* VEXTRACTF32x4Z256mrk */ 0x12c7, /* VEXTRACTF32x4Z256rrk */ /* Table18581 */ 0xf4a, /* VCVTPS2PHZ256mrk */ 0xf4c, /* VCVTPS2PHZ256rrk */ /* Table18583 */ 0x2499, /* VPCMPUDZ256rmik */ 0x249d, /* VPCMPUDZ256rrik */ /* Table18585 */ 0x2399, /* VPCMPDZ256rmik */ 0x239d, /* VPCMPDZ256rrik */ /* Table18587 */ 0x3931, /* VSHUFF32X4Z256rmik */ 0x3934, /* VSHUFF32X4Z256rrik */ /* Table18589 */ 0x3532, /* VPTERNLOGDZ256rmik */ 0x3535, /* VPTERNLOGDZ256rrik */ /* Table18591 */ 0x1b09, /* VGETMANTPSZ256rmik */ 0x1b0c, /* VGETMANTPSZ256rrik */ /* Table18593 */ 0x1bb9, /* VINSERTI32x4Z256rmk */ 0x1bbc, /* VINSERTI32x4Z256rrk */ /* Table18595 */ 0x12e5, /* VEXTRACTI32x4Z256mrk */ 0x12e7, /* VEXTRACTI32x4Z256rrk */ /* Table18597 */ 0x2479, /* VPCMPUBZ256rmik */ 0x247d, /* VPCMPUBZ256rrik */ /* Table18599 */ 0x2379, /* VPCMPBZ256rmik */ 0x237d, /* VPCMPBZ256rrik */ /* Table18601 */ 0x120f, /* VDBPSADBWZ256rmik */ 0x1212, /* VDBPSADBWZ256rrik */ /* Table18603 */ 0x3955, /* VSHUFI32X4Z256rmik */ 0x3958, /* VSHUFI32X4Z256rrik */ /* Table18605 */ 0x3710, /* VRANGEPSZ256rmik */ 0x3713, /* VRANGEPSZ256rrik */ /* Table18607 */ 0x1331, /* VFIXUPIMMPSZ256rmik */ 0x1334, /* VFIXUPIMMPSZ256rrik */ /* Table18609 */ 0x37d2, /* VREDUCEPSZ256rmik */ 0x37d5, /* VREDUCEPSZ256rrik */ /* Table18611 */ 0x1a57, /* VFPCLASSPSZ256rmk */ 0x1a59, /* VFPCLASSPSZ256rrk */ /* Table18613 */ 0x3025, /* VPSHLDDZ256rmik */ 0x3028, /* VPSHLDDZ256rrik */ /* Table18615 */ 0x30c1, /* VPSHRDDZ256rmik */ 0x30c4, /* VPSHRDDZ256rrik */ /* Table18617 */ 0x2783, /* VPERMQZ256mik */ 0x2786, /* VPERMQZ256rik */ /* Table18619 */ 0x2749, /* VPERMPDZ256mik */ 0x274c, /* VPERMPDZ256rik */ /* Table18621 */ 0xc16, /* VALIGNQZ256rmik */ 0xc19, /* VALIGNQZ256rrik */ /* Table18623 */ 0x26e1, /* VPERMILPDZ256mik */ 0x26e4, /* VPERMILPDZ256rik */ /* Table18625 */ 0x3802, /* VRNDSCALEPDZ256rmik */ 0x3805, /* VRNDSCALEPDZ256rrik */ /* Table18627 */ 0x1ba5, /* VINSERTF64x2Z256rmk */ 0x1ba8, /* VINSERTF64x2Z256rrk */ /* Table18629 */ 0x12d4, /* VEXTRACTF64x2Z256mrk */ 0x12d6, /* VEXTRACTF64x2Z256rrk */ /* Table18631 */ 0x24bd, /* VPCMPUQZ256rmik */ 0x24c1, /* VPCMPUQZ256rrik */ /* Table18633 */ 0x245d, /* VPCMPQZ256rmik */ 0x2461, /* VPCMPQZ256rrik */ /* Table18635 */ 0x3943, /* VSHUFF64X2Z256rmik */ 0x3946, /* VSHUFF64X2Z256rrik */ /* Table18637 */ 0x354d, /* VPTERNLOGQZ256rmik */ 0x3550, /* VPTERNLOGQZ256rrik */ /* Table18639 */ 0x1aeb, /* VGETMANTPDZ256rmik */ 0x1aee, /* VGETMANTPDZ256rrik */ /* Table18641 */ 0x1bcb, /* VINSERTI64x2Z256rmk */ 0x1bce, /* VINSERTI64x2Z256rrk */ /* Table18643 */ 0x12f4, /* VEXTRACTI64x2Z256mrk */ 0x12f6, /* VEXTRACTI64x2Z256rrk */ /* Table18645 */ 0x24d9, /* VPCMPUWZ256rmik */ 0x24dd, /* VPCMPUWZ256rrik */ /* Table18647 */ 0x24f1, /* VPCMPWZ256rmik */ 0x24f5, /* VPCMPWZ256rrik */ /* Table18649 */ 0x3967, /* VSHUFI64X2Z256rmik */ 0x396a, /* VSHUFI64X2Z256rrik */ /* Table18651 */ 0x36f2, /* VRANGEPDZ256rmik */ 0x36f5, /* VRANGEPDZ256rrik */ /* Table18653 */ 0x1313, /* VFIXUPIMMPDZ256rmik */ 0x1316, /* VFIXUPIMMPDZ256rrik */ /* Table18655 */ 0x37b4, /* VREDUCEPDZ256rmik */ 0x37b7, /* VREDUCEPDZ256rrik */ /* Table18657 */ 0x1a45, /* VFPCLASSPDZ256rmk */ 0x1a47, /* VFPCLASSPDZ256rrk */ /* Table18659 */ 0x309d, /* VPSHLDWZ256rmik */ 0x30a0, /* VPSHLDWZ256rrik */ /* Table18661 */ 0x3040, /* VPSHLDQZ256rmik */ 0x3043, /* VPSHLDQZ256rrik */ /* Table18663 */ 0x3139, /* VPSHRDWZ256rmik */ 0x313c, /* VPSHRDWZ256rrik */ /* Table18665 */ 0x30dc, /* VPSHRDQZ256rmik */ 0x30df, /* VPSHRDQZ256rrik */ /* Table18667 */ 0x1b5a, /* VGF2P8AFFINEQBZ256rmik */ 0x1b5d, /* VGF2P8AFFINEQBZ256rrik */ /* Table18669 */ 0x1b3b, /* VGF2P8AFFINEINVQBZ256rmik */ 0x1b3e, /* VGF2P8AFFINEINVQBZ256rrik */ /* Table18671 */ 0xc04, /* VALIGNDZrmik */ 0xc07, /* VALIGNDZrrik */ /* Table18673 */ 0x2731, /* VPERMILPSZmik */ 0x2734, /* VPERMILPSZrik */ /* Table18675 */ 0x3829, /* VRNDSCALEPSZrmik */ 0x382f, /* VRNDSCALEPSZrrik */ /* Table18677 */ 0x21ce, /* VPALIGNRZrmik */ 0x21d1, /* VPALIGNRZrrik */ /* Table18679 */ 0x1b99, /* VINSERTF32x4Zrmk */ 0x1b9c, /* VINSERTF32x4Zrrk */ /* Table18681 */ 0x12ca, /* VEXTRACTF32x4Zmrk */ 0x12cc, /* VEXTRACTF32x4Zrrk */ /* Table18683 */ 0x1b9f, /* VINSERTF32x8Zrmk */ 0x1ba2, /* VINSERTF32x8Zrrk */ /* Table18685 */ 0x12cf, /* VEXTRACTF32x8Zmrk */ 0x12d1, /* VEXTRACTF32x8Zrrk */ /* Table18687 */ 0xf4f, /* VCVTPS2PHZmrk */ 0xf54, /* VCVTPS2PHZrrk */ /* Table18689 */ 0x24a5, /* VPCMPUDZrmik */ 0x24a9, /* VPCMPUDZrrik */ /* Table18691 */ 0x23a5, /* VPCMPDZrmik */ 0x23a9, /* VPCMPDZrrik */ /* Table18693 */ 0x393a, /* VSHUFF32X4Zrmik */ 0x393d, /* VSHUFF32X4Zrrik */ /* Table18695 */ 0x353b, /* VPTERNLOGDZrmik */ 0x353e, /* VPTERNLOGDZrrik */ /* Table18697 */ 0x1b12, /* VGETMANTPSZrmik */ 0x1b18, /* VGETMANTPSZrrik */ /* Table18699 */ 0x1bbf, /* VINSERTI32x4Zrmk */ 0x1bc2, /* VINSERTI32x4Zrrk */ /* Table18701 */ 0x12ea, /* VEXTRACTI32x4Zmrk */ 0x12ec, /* VEXTRACTI32x4Zrrk */ /* Table18703 */ 0x1bc5, /* VINSERTI32x8Zrmk */ 0x1bc8, /* VINSERTI32x8Zrrk */ /* Table18705 */ 0x12ef, /* VEXTRACTI32x8Zmrk */ 0x12f1, /* VEXTRACTI32x8Zrrk */ /* Table18707 */ 0x2481, /* VPCMPUBZrmik */ 0x2485, /* VPCMPUBZrrik */ /* Table18709 */ 0x2381, /* VPCMPBZrmik */ 0x2385, /* VPCMPBZrrik */ /* Table18711 */ 0x1215, /* VDBPSADBWZrmik */ 0x1218, /* VDBPSADBWZrrik */ /* Table18713 */ 0x395e, /* VSHUFI32X4Zrmik */ 0x3961, /* VSHUFI32X4Zrrik */ /* Table18715 */ 0x3719, /* VRANGEPSZrmik */ 0x371f, /* VRANGEPSZrrik */ /* Table18717 */ 0x133a, /* VFIXUPIMMPSZrmik */ 0x1340, /* VFIXUPIMMPSZrrik */ /* Table18719 */ 0x37db, /* VREDUCEPSZrmik */ 0x37e1, /* VREDUCEPSZrrik */ /* Table18721 */ 0x1a5d, /* VFPCLASSPSZrmk */ 0x1a5f, /* VFPCLASSPSZrrk */ /* Table18723 */ 0x302e, /* VPSHLDDZrmik */ 0x3031, /* VPSHLDDZrrik */ /* Table18725 */ 0x30ca, /* VPSHRDDZrmik */ 0x30cd, /* VPSHRDDZrrik */ /* Table18727 */ 0x2795, /* VPERMQZmik */ 0x2798, /* VPERMQZrik */ /* Table18729 */ 0x275b, /* VPERMPDZmik */ 0x275e, /* VPERMPDZrik */ /* Table18731 */ 0xc1f, /* VALIGNQZrmik */ 0xc22, /* VALIGNQZrrik */ /* Table18733 */ 0x26f3, /* VPERMILPDZmik */ 0x26f6, /* VPERMILPDZrik */ /* Table18735 */ 0x380b, /* VRNDSCALEPDZrmik */ 0x3811, /* VRNDSCALEPDZrrik */ /* Table18737 */ 0x1bab, /* VINSERTF64x2Zrmk */ 0x1bae, /* VINSERTF64x2Zrrk */ /* Table18739 */ 0x12d9, /* VEXTRACTF64x2Zmrk */ 0x12db, /* VEXTRACTF64x2Zrrk */ /* Table18741 */ 0x1bb1, /* VINSERTF64x4Zrmk */ 0x1bb4, /* VINSERTF64x4Zrrk */ /* Table18743 */ 0x12de, /* VEXTRACTF64x4Zmrk */ 0x12e0, /* VEXTRACTF64x4Zrrk */ /* Table18745 */ 0x24c9, /* VPCMPUQZrmik */ 0x24cd, /* VPCMPUQZrrik */ /* Table18747 */ 0x2469, /* VPCMPQZrmik */ 0x246d, /* VPCMPQZrrik */ /* Table18749 */ 0x394c, /* VSHUFF64X2Zrmik */ 0x394f, /* VSHUFF64X2Zrrik */ /* Table18751 */ 0x3556, /* VPTERNLOGQZrmik */ 0x3559, /* VPTERNLOGQZrrik */ /* Table18753 */ 0x1af4, /* VGETMANTPDZrmik */ 0x1afa, /* VGETMANTPDZrrik */ /* Table18755 */ 0x1bd1, /* VINSERTI64x2Zrmk */ 0x1bd4, /* VINSERTI64x2Zrrk */ /* Table18757 */ 0x12f9, /* VEXTRACTI64x2Zmrk */ 0x12fb, /* VEXTRACTI64x2Zrrk */ /* Table18759 */ 0x1bd7, /* VINSERTI64x4Zrmk */ 0x1bda, /* VINSERTI64x4Zrrk */ /* Table18761 */ 0x12fe, /* VEXTRACTI64x4Zmrk */ 0x1300, /* VEXTRACTI64x4Zrrk */ /* Table18763 */ 0x24e1, /* VPCMPUWZrmik */ 0x24e5, /* VPCMPUWZrrik */ /* Table18765 */ 0x24f9, /* VPCMPWZrmik */ 0x24fd, /* VPCMPWZrrik */ /* Table18767 */ 0x3970, /* VSHUFI64X2Zrmik */ 0x3973, /* VSHUFI64X2Zrrik */ /* Table18769 */ 0x36fb, /* VRANGEPDZrmik */ 0x3701, /* VRANGEPDZrrik */ /* Table18771 */ 0x131c, /* VFIXUPIMMPDZrmik */ 0x1322, /* VFIXUPIMMPDZrrik */ /* Table18773 */ 0x37bd, /* VREDUCEPDZrmik */ 0x37c3, /* VREDUCEPDZrrik */ /* Table18775 */ 0x1a4b, /* VFPCLASSPDZrmk */ 0x1a4d, /* VFPCLASSPDZrrk */ /* Table18777 */ 0x30a3, /* VPSHLDWZrmik */ 0x30a6, /* VPSHLDWZrrik */ /* Table18779 */ 0x3049, /* VPSHLDQZrmik */ 0x304c, /* VPSHLDQZrrik */ /* Table18781 */ 0x313f, /* VPSHRDWZrmik */ 0x3142, /* VPSHRDWZrrik */ /* Table18783 */ 0x30e5, /* VPSHRDQZrmik */ 0x30e8, /* VPSHRDQZrrik */ /* Table18785 */ 0x1b63, /* VGF2P8AFFINEQBZrmik */ 0x1b66, /* VGF2P8AFFINEQBZrrik */ /* Table18787 */ 0x1b44, /* VGF2P8AFFINEINVQBZrmik */ 0x1b47, /* VGF2P8AFFINEINVQBZrrik */ /* Table18789 */ 0xbee, /* VALIGNDZ128rmbi */ 0x0, /* */ /* Table18791 */ 0x2709, /* VPERMILPSZ128mbi */ 0x0, /* */ /* Table18793 */ 0x3813, /* VRNDSCALEPSZ128rmbi */ 0x382c, /* VRNDSCALEPSZrrib */ /* Table18795 */ 0x0, /* */ 0x3844, /* VRNDSCALESSZrb_Int */ /* Table18797 */ 0x0, /* */ 0xf51, /* VCVTPS2PHZrrb */ /* Table18799 */ 0x2489, /* VPCMPUDZ128rmib */ 0x0, /* */ /* Table18801 */ 0x2389, /* VPCMPDZ128rmib */ 0x0, /* */ /* Table18803 */ 0x3525, /* VPTERNLOGDZ128rmbi */ 0x0, /* */ /* Table18805 */ 0x1afc, /* VGETMANTPSZ128rmbi */ 0x1b15, /* VGETMANTPSZrrib */ /* Table18807 */ 0x0, /* */ 0x1b27, /* VGETMANTSSZrrib */ /* Table18809 */ 0x3703, /* VRANGEPSZ128rmbi */ 0x371c, /* VRANGEPSZrrib */ /* Table18811 */ 0x0, /* */ 0x372e, /* VRANGESSZrrib */ /* Table18813 */ 0x1324, /* VFIXUPIMMPSZ128rmbi */ 0x133d, /* VFIXUPIMMPSZrrib */ /* Table18815 */ 0x0, /* */ 0x134f, /* VFIXUPIMMSSZrrib */ /* Table18817 */ 0x37c5, /* VREDUCEPSZ128rmbi */ 0x37de, /* VREDUCEPSZrrib */ /* Table18819 */ 0x0, /* */ 0x37f0, /* VREDUCESSZrrib */ /* Table18821 */ 0x1a4f, /* VFPCLASSPSZ128rmb */ 0x0, /* */ /* Table18823 */ 0x3018, /* VPSHLDDZ128rmbi */ 0x0, /* */ /* Table18825 */ 0x30b4, /* VPSHRDDZ128rmbi */ 0x0, /* */ /* Table18827 */ 0xc09, /* VALIGNQZ128rmbi */ 0x0, /* */ /* Table18829 */ 0x26cb, /* VPERMILPDZ128mbi */ 0x0, /* */ /* Table18831 */ 0x37f5, /* VRNDSCALEPDZ128rmbi */ 0x380e, /* VRNDSCALEPDZrrib */ /* Table18833 */ 0x0, /* */ 0x3839, /* VRNDSCALESDZrb_Int */ /* Table18835 */ 0x24ad, /* VPCMPUQZ128rmib */ 0x0, /* */ /* Table18837 */ 0x244d, /* VPCMPQZ128rmib */ 0x0, /* */ /* Table18839 */ 0x3540, /* VPTERNLOGQZ128rmbi */ 0x0, /* */ /* Table18841 */ 0x1ade, /* VGETMANTPDZ128rmbi */ 0x1af7, /* VGETMANTPDZrrib */ /* Table18843 */ 0x0, /* */ 0x1b1e, /* VGETMANTSDZrrib */ /* Table18845 */ 0x36e5, /* VRANGEPDZ128rmbi */ 0x36fe, /* VRANGEPDZrrib */ /* Table18847 */ 0x0, /* */ 0x3725, /* VRANGESDZrrib */ /* Table18849 */ 0x1306, /* VFIXUPIMMPDZ128rmbi */ 0x131f, /* VFIXUPIMMPDZrrib */ /* Table18851 */ 0x0, /* */ 0x1346, /* VFIXUPIMMSDZrrib */ /* Table18853 */ 0x37a7, /* VREDUCEPDZ128rmbi */ 0x37c0, /* VREDUCEPDZrrib */ /* Table18855 */ 0x0, /* */ 0x37e7, /* VREDUCESDZrrib */ /* Table18857 */ 0x1a3d, /* VFPCLASSPDZ128rmb */ 0x0, /* */ /* Table18859 */ 0x3033, /* VPSHLDQZ128rmbi */ 0x0, /* */ /* Table18861 */ 0x30cf, /* VPSHRDQZ128rmbi */ 0x0, /* */ /* Table18863 */ 0x1b4d, /* VGF2P8AFFINEQBZ128rmbi */ 0x0, /* */ /* Table18865 */ 0x1b2e, /* VGF2P8AFFINEINVQBZ128rmbi */ 0x0, /* */ /* Table18867 */ 0xbf7, /* VALIGNDZ256rmbi */ 0x0, /* */ /* Table18869 */ 0x271b, /* VPERMILPSZ256mbi */ 0x0, /* */ /* Table18871 */ 0x381c, /* VRNDSCALEPSZ256rmbi */ 0x382c, /* VRNDSCALEPSZrrib */ /* Table18873 */ 0x2495, /* VPCMPUDZ256rmib */ 0x0, /* */ /* Table18875 */ 0x2395, /* VPCMPDZ256rmib */ 0x0, /* */ /* Table18877 */ 0x392d, /* VSHUFF32X4Z256rmbi */ 0x0, /* */ /* Table18879 */ 0x352e, /* VPTERNLOGDZ256rmbi */ 0x0, /* */ /* Table18881 */ 0x1b05, /* VGETMANTPSZ256rmbi */ 0x1b15, /* VGETMANTPSZrrib */ /* Table18883 */ 0x3951, /* VSHUFI32X4Z256rmbi */ 0x0, /* */ /* Table18885 */ 0x370c, /* VRANGEPSZ256rmbi */ 0x371c, /* VRANGEPSZrrib */ /* Table18887 */ 0x132d, /* VFIXUPIMMPSZ256rmbi */ 0x133d, /* VFIXUPIMMPSZrrib */ /* Table18889 */ 0x37ce, /* VREDUCEPSZ256rmbi */ 0x37de, /* VREDUCEPSZrrib */ /* Table18891 */ 0x1a55, /* VFPCLASSPSZ256rmb */ 0x0, /* */ /* Table18893 */ 0x3021, /* VPSHLDDZ256rmbi */ 0x0, /* */ /* Table18895 */ 0x30bd, /* VPSHRDDZ256rmbi */ 0x0, /* */ /* Table18897 */ 0x277f, /* VPERMQZ256mbi */ 0x0, /* */ /* Table18899 */ 0x2745, /* VPERMPDZ256mbi */ 0x0, /* */ /* Table18901 */ 0xc12, /* VALIGNQZ256rmbi */ 0x0, /* */ /* Table18903 */ 0x26dd, /* VPERMILPDZ256mbi */ 0x0, /* */ /* Table18905 */ 0x37fe, /* VRNDSCALEPDZ256rmbi */ 0x380e, /* VRNDSCALEPDZrrib */ /* Table18907 */ 0x24b9, /* VPCMPUQZ256rmib */ 0x0, /* */ /* Table18909 */ 0x2459, /* VPCMPQZ256rmib */ 0x0, /* */ /* Table18911 */ 0x393f, /* VSHUFF64X2Z256rmbi */ 0x0, /* */ /* Table18913 */ 0x3549, /* VPTERNLOGQZ256rmbi */ 0x0, /* */ /* Table18915 */ 0x1ae7, /* VGETMANTPDZ256rmbi */ 0x1af7, /* VGETMANTPDZrrib */ /* Table18917 */ 0x3963, /* VSHUFI64X2Z256rmbi */ 0x0, /* */ /* Table18919 */ 0x36ee, /* VRANGEPDZ256rmbi */ 0x36fe, /* VRANGEPDZrrib */ /* Table18921 */ 0x130f, /* VFIXUPIMMPDZ256rmbi */ 0x131f, /* VFIXUPIMMPDZrrib */ /* Table18923 */ 0x37b0, /* VREDUCEPDZ256rmbi */ 0x37c0, /* VREDUCEPDZrrib */ /* Table18925 */ 0x1a43, /* VFPCLASSPDZ256rmb */ 0x0, /* */ /* Table18927 */ 0x303c, /* VPSHLDQZ256rmbi */ 0x0, /* */ /* Table18929 */ 0x30d8, /* VPSHRDQZ256rmbi */ 0x0, /* */ /* Table18931 */ 0x1b56, /* VGF2P8AFFINEQBZ256rmbi */ 0x0, /* */ /* Table18933 */ 0x1b37, /* VGF2P8AFFINEINVQBZ256rmbi */ 0x0, /* */ /* Table18935 */ 0xc00, /* VALIGNDZrmbi */ 0x0, /* */ /* Table18937 */ 0x272d, /* VPERMILPSZmbi */ 0x0, /* */ /* Table18939 */ 0x3825, /* VRNDSCALEPSZrmbi */ 0x382c, /* VRNDSCALEPSZrrib */ /* Table18941 */ 0x24a1, /* VPCMPUDZrmib */ 0x0, /* */ /* Table18943 */ 0x23a1, /* VPCMPDZrmib */ 0x0, /* */ /* Table18945 */ 0x3936, /* VSHUFF32X4Zrmbi */ 0x0, /* */ /* Table18947 */ 0x3537, /* VPTERNLOGDZrmbi */ 0x0, /* */ /* Table18949 */ 0x1b0e, /* VGETMANTPSZrmbi */ 0x1b15, /* VGETMANTPSZrrib */ /* Table18951 */ 0x395a, /* VSHUFI32X4Zrmbi */ 0x0, /* */ /* Table18953 */ 0x3715, /* VRANGEPSZrmbi */ 0x371c, /* VRANGEPSZrrib */ /* Table18955 */ 0x1336, /* VFIXUPIMMPSZrmbi */ 0x133d, /* VFIXUPIMMPSZrrib */ /* Table18957 */ 0x37d7, /* VREDUCEPSZrmbi */ 0x37de, /* VREDUCEPSZrrib */ /* Table18959 */ 0x1a5b, /* VFPCLASSPSZrmb */ 0x0, /* */ /* Table18961 */ 0x302a, /* VPSHLDDZrmbi */ 0x0, /* */ /* Table18963 */ 0x30c6, /* VPSHRDDZrmbi */ 0x0, /* */ /* Table18965 */ 0x2791, /* VPERMQZmbi */ 0x0, /* */ /* Table18967 */ 0x2757, /* VPERMPDZmbi */ 0x0, /* */ /* Table18969 */ 0xc1b, /* VALIGNQZrmbi */ 0x0, /* */ /* Table18971 */ 0x26ef, /* VPERMILPDZmbi */ 0x0, /* */ /* Table18973 */ 0x3807, /* VRNDSCALEPDZrmbi */ 0x380e, /* VRNDSCALEPDZrrib */ /* Table18975 */ 0x24c5, /* VPCMPUQZrmib */ 0x0, /* */ /* Table18977 */ 0x2465, /* VPCMPQZrmib */ 0x0, /* */ /* Table18979 */ 0x3948, /* VSHUFF64X2Zrmbi */ 0x0, /* */ /* Table18981 */ 0x3552, /* VPTERNLOGQZrmbi */ 0x0, /* */ /* Table18983 */ 0x1af0, /* VGETMANTPDZrmbi */ 0x1af7, /* VGETMANTPDZrrib */ /* Table18985 */ 0x396c, /* VSHUFI64X2Zrmbi */ 0x0, /* */ /* Table18987 */ 0x36f7, /* VRANGEPDZrmbi */ 0x36fe, /* VRANGEPDZrrib */ /* Table18989 */ 0x1318, /* VFIXUPIMMPDZrmbi */ 0x131f, /* VFIXUPIMMPDZrrib */ /* Table18991 */ 0x37b9, /* VREDUCEPDZrmbi */ 0x37c0, /* VREDUCEPDZrrib */ /* Table18993 */ 0x1a49, /* VFPCLASSPDZrmb */ 0x0, /* */ /* Table18995 */ 0x3045, /* VPSHLDQZrmbi */ 0x0, /* */ /* Table18997 */ 0x30e1, /* VPSHRDQZrmbi */ 0x0, /* */ /* Table18999 */ 0x1b5f, /* VGF2P8AFFINEQBZrmbi */ 0x0, /* */ /* Table19001 */ 0x1b40, /* VGF2P8AFFINEINVQBZrmbi */ 0x0, /* */ /* Table19003 */ 0xbef, /* VALIGNDZ128rmbik */ 0x0, /* */ /* Table19005 */ 0x270a, /* VPERMILPSZ128mbik */ 0x0, /* */ /* Table19007 */ 0x3814, /* VRNDSCALEPSZ128rmbik */ 0x382d, /* VRNDSCALEPSZrribk */ /* Table19009 */ 0x0, /* */ 0x3845, /* VRNDSCALESSZrb_Intk */ /* Table19011 */ 0x0, /* */ 0xf52, /* VCVTPS2PHZrrbk */ /* Table19013 */ 0x248b, /* VPCMPUDZ128rmibk */ 0x0, /* */ /* Table19015 */ 0x238b, /* VPCMPDZ128rmibk */ 0x0, /* */ /* Table19017 */ 0x3526, /* VPTERNLOGDZ128rmbik */ 0x0, /* */ /* Table19019 */ 0x1afd, /* VGETMANTPSZ128rmbik */ 0x1b16, /* VGETMANTPSZrribk */ /* Table19021 */ 0x0, /* */ 0x1b28, /* VGETMANTSSZrribk */ /* Table19023 */ 0x3704, /* VRANGEPSZ128rmbik */ 0x371d, /* VRANGEPSZrribk */ /* Table19025 */ 0x0, /* */ 0x372f, /* VRANGESSZrribk */ /* Table19027 */ 0x1325, /* VFIXUPIMMPSZ128rmbik */ 0x133e, /* VFIXUPIMMPSZrribk */ /* Table19029 */ 0x0, /* */ 0x1350, /* VFIXUPIMMSSZrribk */ /* Table19031 */ 0x37c6, /* VREDUCEPSZ128rmbik */ 0x37df, /* VREDUCEPSZrribk */ /* Table19033 */ 0x0, /* */ 0x37f1, /* VREDUCESSZrribk */ /* Table19035 */ 0x1a50, /* VFPCLASSPSZ128rmbk */ 0x0, /* */ /* Table19037 */ 0x3019, /* VPSHLDDZ128rmbik */ 0x0, /* */ /* Table19039 */ 0x30b5, /* VPSHRDDZ128rmbik */ 0x0, /* */ /* Table19041 */ 0xc0a, /* VALIGNQZ128rmbik */ 0x0, /* */ /* Table19043 */ 0x26cc, /* VPERMILPDZ128mbik */ 0x0, /* */ /* Table19045 */ 0x37f6, /* VRNDSCALEPDZ128rmbik */ 0x380f, /* VRNDSCALEPDZrribk */ /* Table19047 */ 0x0, /* */ 0x383a, /* VRNDSCALESDZrb_Intk */ /* Table19049 */ 0x24af, /* VPCMPUQZ128rmibk */ 0x0, /* */ /* Table19051 */ 0x244f, /* VPCMPQZ128rmibk */ 0x0, /* */ /* Table19053 */ 0x3541, /* VPTERNLOGQZ128rmbik */ 0x0, /* */ /* Table19055 */ 0x1adf, /* VGETMANTPDZ128rmbik */ 0x1af8, /* VGETMANTPDZrribk */ /* Table19057 */ 0x0, /* */ 0x1b1f, /* VGETMANTSDZrribk */ /* Table19059 */ 0x36e6, /* VRANGEPDZ128rmbik */ 0x36ff, /* VRANGEPDZrribk */ /* Table19061 */ 0x0, /* */ 0x3726, /* VRANGESDZrribk */ /* Table19063 */ 0x1307, /* VFIXUPIMMPDZ128rmbik */ 0x1320, /* VFIXUPIMMPDZrribk */ /* Table19065 */ 0x0, /* */ 0x1347, /* VFIXUPIMMSDZrribk */ /* Table19067 */ 0x37a8, /* VREDUCEPDZ128rmbik */ 0x37c1, /* VREDUCEPDZrribk */ /* Table19069 */ 0x0, /* */ 0x37e8, /* VREDUCESDZrribk */ /* Table19071 */ 0x1a3e, /* VFPCLASSPDZ128rmbk */ 0x0, /* */ /* Table19073 */ 0x3034, /* VPSHLDQZ128rmbik */ 0x0, /* */ /* Table19075 */ 0x30d0, /* VPSHRDQZ128rmbik */ 0x0, /* */ /* Table19077 */ 0x1b4e, /* VGF2P8AFFINEQBZ128rmbik */ 0x0, /* */ /* Table19079 */ 0x1b2f, /* VGF2P8AFFINEINVQBZ128rmbik */ 0x0, /* */ /* Table19081 */ 0xbf8, /* VALIGNDZ256rmbik */ 0x0, /* */ /* Table19083 */ 0x271c, /* VPERMILPSZ256mbik */ 0x0, /* */ /* Table19085 */ 0x381d, /* VRNDSCALEPSZ256rmbik */ 0x382d, /* VRNDSCALEPSZrribk */ /* Table19087 */ 0x2497, /* VPCMPUDZ256rmibk */ 0x0, /* */ /* Table19089 */ 0x2397, /* VPCMPDZ256rmibk */ 0x0, /* */ /* Table19091 */ 0x392e, /* VSHUFF32X4Z256rmbik */ 0x0, /* */ /* Table19093 */ 0x352f, /* VPTERNLOGDZ256rmbik */ 0x0, /* */ /* Table19095 */ 0x1b06, /* VGETMANTPSZ256rmbik */ 0x1b16, /* VGETMANTPSZrribk */ /* Table19097 */ 0x3952, /* VSHUFI32X4Z256rmbik */ 0x0, /* */ /* Table19099 */ 0x370d, /* VRANGEPSZ256rmbik */ 0x371d, /* VRANGEPSZrribk */ /* Table19101 */ 0x132e, /* VFIXUPIMMPSZ256rmbik */ 0x133e, /* VFIXUPIMMPSZrribk */ /* Table19103 */ 0x37cf, /* VREDUCEPSZ256rmbik */ 0x37df, /* VREDUCEPSZrribk */ /* Table19105 */ 0x1a56, /* VFPCLASSPSZ256rmbk */ 0x0, /* */ /* Table19107 */ 0x3022, /* VPSHLDDZ256rmbik */ 0x0, /* */ /* Table19109 */ 0x30be, /* VPSHRDDZ256rmbik */ 0x0, /* */ /* Table19111 */ 0x2780, /* VPERMQZ256mbik */ 0x0, /* */ /* Table19113 */ 0x2746, /* VPERMPDZ256mbik */ 0x0, /* */ /* Table19115 */ 0xc13, /* VALIGNQZ256rmbik */ 0x0, /* */ /* Table19117 */ 0x26de, /* VPERMILPDZ256mbik */ 0x0, /* */ /* Table19119 */ 0x37ff, /* VRNDSCALEPDZ256rmbik */ 0x380f, /* VRNDSCALEPDZrribk */ /* Table19121 */ 0x24bb, /* VPCMPUQZ256rmibk */ 0x0, /* */ /* Table19123 */ 0x245b, /* VPCMPQZ256rmibk */ 0x0, /* */ /* Table19125 */ 0x3940, /* VSHUFF64X2Z256rmbik */ 0x0, /* */ /* Table19127 */ 0x354a, /* VPTERNLOGQZ256rmbik */ 0x0, /* */ /* Table19129 */ 0x1ae8, /* VGETMANTPDZ256rmbik */ 0x1af8, /* VGETMANTPDZrribk */ /* Table19131 */ 0x3964, /* VSHUFI64X2Z256rmbik */ 0x0, /* */ /* Table19133 */ 0x36ef, /* VRANGEPDZ256rmbik */ 0x36ff, /* VRANGEPDZrribk */ /* Table19135 */ 0x1310, /* VFIXUPIMMPDZ256rmbik */ 0x1320, /* VFIXUPIMMPDZrribk */ /* Table19137 */ 0x37b1, /* VREDUCEPDZ256rmbik */ 0x37c1, /* VREDUCEPDZrribk */ /* Table19139 */ 0x1a44, /* VFPCLASSPDZ256rmbk */ 0x0, /* */ /* Table19141 */ 0x303d, /* VPSHLDQZ256rmbik */ 0x0, /* */ /* Table19143 */ 0x30d9, /* VPSHRDQZ256rmbik */ 0x0, /* */ /* Table19145 */ 0x1b57, /* VGF2P8AFFINEQBZ256rmbik */ 0x0, /* */ /* Table19147 */ 0x1b38, /* VGF2P8AFFINEINVQBZ256rmbik */ 0x0, /* */ /* Table19149 */ 0xc01, /* VALIGNDZrmbik */ 0x0, /* */ /* Table19151 */ 0x272e, /* VPERMILPSZmbik */ 0x0, /* */ /* Table19153 */ 0x3826, /* VRNDSCALEPSZrmbik */ 0x382d, /* VRNDSCALEPSZrribk */ /* Table19155 */ 0x24a3, /* VPCMPUDZrmibk */ 0x0, /* */ /* Table19157 */ 0x23a3, /* VPCMPDZrmibk */ 0x0, /* */ /* Table19159 */ 0x3937, /* VSHUFF32X4Zrmbik */ 0x0, /* */ /* Table19161 */ 0x3538, /* VPTERNLOGDZrmbik */ 0x0, /* */ /* Table19163 */ 0x1b0f, /* VGETMANTPSZrmbik */ 0x1b16, /* VGETMANTPSZrribk */ /* Table19165 */ 0x395b, /* VSHUFI32X4Zrmbik */ 0x0, /* */ /* Table19167 */ 0x3716, /* VRANGEPSZrmbik */ 0x371d, /* VRANGEPSZrribk */ /* Table19169 */ 0x1337, /* VFIXUPIMMPSZrmbik */ 0x133e, /* VFIXUPIMMPSZrribk */ /* Table19171 */ 0x37d8, /* VREDUCEPSZrmbik */ 0x37df, /* VREDUCEPSZrribk */ /* Table19173 */ 0x1a5c, /* VFPCLASSPSZrmbk */ 0x0, /* */ /* Table19175 */ 0x302b, /* VPSHLDDZrmbik */ 0x0, /* */ /* Table19177 */ 0x30c7, /* VPSHRDDZrmbik */ 0x0, /* */ /* Table19179 */ 0x2792, /* VPERMQZmbik */ 0x0, /* */ /* Table19181 */ 0x2758, /* VPERMPDZmbik */ 0x0, /* */ /* Table19183 */ 0xc1c, /* VALIGNQZrmbik */ 0x0, /* */ /* Table19185 */ 0x26f0, /* VPERMILPDZmbik */ 0x0, /* */ /* Table19187 */ 0x3808, /* VRNDSCALEPDZrmbik */ 0x380f, /* VRNDSCALEPDZrribk */ /* Table19189 */ 0x24c7, /* VPCMPUQZrmibk */ 0x0, /* */ /* Table19191 */ 0x2467, /* VPCMPQZrmibk */ 0x0, /* */ /* Table19193 */ 0x3949, /* VSHUFF64X2Zrmbik */ 0x0, /* */ /* Table19195 */ 0x3553, /* VPTERNLOGQZrmbik */ 0x0, /* */ /* Table19197 */ 0x1af1, /* VGETMANTPDZrmbik */ 0x1af8, /* VGETMANTPDZrribk */ /* Table19199 */ 0x396d, /* VSHUFI64X2Zrmbik */ 0x0, /* */ /* Table19201 */ 0x36f8, /* VRANGEPDZrmbik */ 0x36ff, /* VRANGEPDZrribk */ /* Table19203 */ 0x1319, /* VFIXUPIMMPDZrmbik */ 0x1320, /* VFIXUPIMMPDZrribk */ /* Table19205 */ 0x37ba, /* VREDUCEPDZrmbik */ 0x37c1, /* VREDUCEPDZrribk */ /* Table19207 */ 0x1a4a, /* VFPCLASSPDZrmbk */ 0x0, /* */ /* Table19209 */ 0x3046, /* VPSHLDQZrmbik */ 0x0, /* */ /* Table19211 */ 0x30e2, /* VPSHRDQZrmbik */ 0x0, /* */ /* Table19213 */ 0x1b60, /* VGF2P8AFFINEQBZrmbik */ 0x0, /* */ /* Table19215 */ 0x1b41, /* VGF2P8AFFINEINVQBZrmbik */ 0x0, /* */ /* Table19217 */ 0xbf0, /* VALIGNDZ128rmbikz */ 0x0, /* */ /* Table19219 */ 0x270b, /* VPERMILPSZ128mbikz */ 0x0, /* */ /* Table19221 */ 0x3815, /* VRNDSCALEPSZ128rmbikz */ 0x382e, /* VRNDSCALEPSZrribkz */ /* Table19223 */ 0x0, /* */ 0x3846, /* VRNDSCALESSZrb_Intkz */ /* Table19225 */ 0x0, /* */ 0xf53, /* VCVTPS2PHZrrbkz */ /* Table19227 */ 0x3527, /* VPTERNLOGDZ128rmbikz */ 0x0, /* */ /* Table19229 */ 0x1afe, /* VGETMANTPSZ128rmbikz */ 0x1b17, /* VGETMANTPSZrribkz */ /* Table19231 */ 0x0, /* */ 0x1b29, /* VGETMANTSSZrribkz */ /* Table19233 */ 0x3705, /* VRANGEPSZ128rmbikz */ 0x371e, /* VRANGEPSZrribkz */ /* Table19235 */ 0x0, /* */ 0x3730, /* VRANGESSZrribkz */ /* Table19237 */ 0x1326, /* VFIXUPIMMPSZ128rmbikz */ 0x133f, /* VFIXUPIMMPSZrribkz */ /* Table19239 */ 0x0, /* */ 0x1351, /* VFIXUPIMMSSZrribkz */ /* Table19241 */ 0x37c7, /* VREDUCEPSZ128rmbikz */ 0x37e0, /* VREDUCEPSZrribkz */ /* Table19243 */ 0x0, /* */ 0x37f2, /* VREDUCESSZrribkz */ /* Table19245 */ 0x301a, /* VPSHLDDZ128rmbikz */ 0x0, /* */ /* Table19247 */ 0x30b6, /* VPSHRDDZ128rmbikz */ 0x0, /* */ /* Table19249 */ 0xc0b, /* VALIGNQZ128rmbikz */ 0x0, /* */ /* Table19251 */ 0x26cd, /* VPERMILPDZ128mbikz */ 0x0, /* */ /* Table19253 */ 0x37f7, /* VRNDSCALEPDZ128rmbikz */ 0x3810, /* VRNDSCALEPDZrribkz */ /* Table19255 */ 0x0, /* */ 0x383b, /* VRNDSCALESDZrb_Intkz */ /* Table19257 */ 0x3542, /* VPTERNLOGQZ128rmbikz */ 0x0, /* */ /* Table19259 */ 0x1ae0, /* VGETMANTPDZ128rmbikz */ 0x1af9, /* VGETMANTPDZrribkz */ /* Table19261 */ 0x0, /* */ 0x1b20, /* VGETMANTSDZrribkz */ /* Table19263 */ 0x36e7, /* VRANGEPDZ128rmbikz */ 0x3700, /* VRANGEPDZrribkz */ /* Table19265 */ 0x0, /* */ 0x3727, /* VRANGESDZrribkz */ /* Table19267 */ 0x1308, /* VFIXUPIMMPDZ128rmbikz */ 0x1321, /* VFIXUPIMMPDZrribkz */ /* Table19269 */ 0x0, /* */ 0x1348, /* VFIXUPIMMSDZrribkz */ /* Table19271 */ 0x37a9, /* VREDUCEPDZ128rmbikz */ 0x37c2, /* VREDUCEPDZrribkz */ /* Table19273 */ 0x0, /* */ 0x37e9, /* VREDUCESDZrribkz */ /* Table19275 */ 0x3035, /* VPSHLDQZ128rmbikz */ 0x0, /* */ /* Table19277 */ 0x30d1, /* VPSHRDQZ128rmbikz */ 0x0, /* */ /* Table19279 */ 0x1b4f, /* VGF2P8AFFINEQBZ128rmbikz */ 0x0, /* */ /* Table19281 */ 0x1b30, /* VGF2P8AFFINEINVQBZ128rmbikz */ 0x0, /* */ /* Table19283 */ 0xbf9, /* VALIGNDZ256rmbikz */ 0x0, /* */ /* Table19285 */ 0x271d, /* VPERMILPSZ256mbikz */ 0x0, /* */ /* Table19287 */ 0x381e, /* VRNDSCALEPSZ256rmbikz */ 0x382e, /* VRNDSCALEPSZrribkz */ /* Table19289 */ 0x392f, /* VSHUFF32X4Z256rmbikz */ 0x0, /* */ /* Table19291 */ 0x3530, /* VPTERNLOGDZ256rmbikz */ 0x0, /* */ /* Table19293 */ 0x1b07, /* VGETMANTPSZ256rmbikz */ 0x1b17, /* VGETMANTPSZrribkz */ /* Table19295 */ 0x3953, /* VSHUFI32X4Z256rmbikz */ 0x0, /* */ /* Table19297 */ 0x370e, /* VRANGEPSZ256rmbikz */ 0x371e, /* VRANGEPSZrribkz */ /* Table19299 */ 0x132f, /* VFIXUPIMMPSZ256rmbikz */ 0x133f, /* VFIXUPIMMPSZrribkz */ /* Table19301 */ 0x37d0, /* VREDUCEPSZ256rmbikz */ 0x37e0, /* VREDUCEPSZrribkz */ /* Table19303 */ 0x3023, /* VPSHLDDZ256rmbikz */ 0x0, /* */ /* Table19305 */ 0x30bf, /* VPSHRDDZ256rmbikz */ 0x0, /* */ /* Table19307 */ 0x2781, /* VPERMQZ256mbikz */ 0x0, /* */ /* Table19309 */ 0x2747, /* VPERMPDZ256mbikz */ 0x0, /* */ /* Table19311 */ 0xc14, /* VALIGNQZ256rmbikz */ 0x0, /* */ /* Table19313 */ 0x26df, /* VPERMILPDZ256mbikz */ 0x0, /* */ /* Table19315 */ 0x3800, /* VRNDSCALEPDZ256rmbikz */ 0x3810, /* VRNDSCALEPDZrribkz */ /* Table19317 */ 0x3941, /* VSHUFF64X2Z256rmbikz */ 0x0, /* */ /* Table19319 */ 0x354b, /* VPTERNLOGQZ256rmbikz */ 0x0, /* */ /* Table19321 */ 0x1ae9, /* VGETMANTPDZ256rmbikz */ 0x1af9, /* VGETMANTPDZrribkz */ /* Table19323 */ 0x3965, /* VSHUFI64X2Z256rmbikz */ 0x0, /* */ /* Table19325 */ 0x36f0, /* VRANGEPDZ256rmbikz */ 0x3700, /* VRANGEPDZrribkz */ /* Table19327 */ 0x1311, /* VFIXUPIMMPDZ256rmbikz */ 0x1321, /* VFIXUPIMMPDZrribkz */ /* Table19329 */ 0x37b2, /* VREDUCEPDZ256rmbikz */ 0x37c2, /* VREDUCEPDZrribkz */ /* Table19331 */ 0x303e, /* VPSHLDQZ256rmbikz */ 0x0, /* */ /* Table19333 */ 0x30da, /* VPSHRDQZ256rmbikz */ 0x0, /* */ /* Table19335 */ 0x1b58, /* VGF2P8AFFINEQBZ256rmbikz */ 0x0, /* */ /* Table19337 */ 0x1b39, /* VGF2P8AFFINEINVQBZ256rmbikz */ 0x0, /* */ /* Table19339 */ 0xc02, /* VALIGNDZrmbikz */ 0x0, /* */ /* Table19341 */ 0x272f, /* VPERMILPSZmbikz */ 0x0, /* */ /* Table19343 */ 0x3827, /* VRNDSCALEPSZrmbikz */ 0x382e, /* VRNDSCALEPSZrribkz */ /* Table19345 */ 0x3938, /* VSHUFF32X4Zrmbikz */ 0x0, /* */ /* Table19347 */ 0x3539, /* VPTERNLOGDZrmbikz */ 0x0, /* */ /* Table19349 */ 0x1b10, /* VGETMANTPSZrmbikz */ 0x1b17, /* VGETMANTPSZrribkz */ /* Table19351 */ 0x395c, /* VSHUFI32X4Zrmbikz */ 0x0, /* */ /* Table19353 */ 0x3717, /* VRANGEPSZrmbikz */ 0x371e, /* VRANGEPSZrribkz */ /* Table19355 */ 0x1338, /* VFIXUPIMMPSZrmbikz */ 0x133f, /* VFIXUPIMMPSZrribkz */ /* Table19357 */ 0x37d9, /* VREDUCEPSZrmbikz */ 0x37e0, /* VREDUCEPSZrribkz */ /* Table19359 */ 0x302c, /* VPSHLDDZrmbikz */ 0x0, /* */ /* Table19361 */ 0x30c8, /* VPSHRDDZrmbikz */ 0x0, /* */ /* Table19363 */ 0x2793, /* VPERMQZmbikz */ 0x0, /* */ /* Table19365 */ 0x2759, /* VPERMPDZmbikz */ 0x0, /* */ /* Table19367 */ 0xc1d, /* VALIGNQZrmbikz */ 0x0, /* */ /* Table19369 */ 0x26f1, /* VPERMILPDZmbikz */ 0x0, /* */ /* Table19371 */ 0x3809, /* VRNDSCALEPDZrmbikz */ 0x3810, /* VRNDSCALEPDZrribkz */ /* Table19373 */ 0x394a, /* VSHUFF64X2Zrmbikz */ 0x0, /* */ /* Table19375 */ 0x3554, /* VPTERNLOGQZrmbikz */ 0x0, /* */ /* Table19377 */ 0x1af2, /* VGETMANTPDZrmbikz */ 0x1af9, /* VGETMANTPDZrribkz */ /* Table19379 */ 0x396e, /* VSHUFI64X2Zrmbikz */ 0x0, /* */ /* Table19381 */ 0x36f9, /* VRANGEPDZrmbikz */ 0x3700, /* VRANGEPDZrribkz */ /* Table19383 */ 0x131a, /* VFIXUPIMMPDZrmbikz */ 0x1321, /* VFIXUPIMMPDZrribkz */ /* Table19385 */ 0x37bb, /* VREDUCEPDZrmbikz */ 0x37c2, /* VREDUCEPDZrribkz */ /* Table19387 */ 0x3047, /* VPSHLDQZrmbikz */ 0x0, /* */ /* Table19389 */ 0x30e3, /* VPSHRDQZrmbikz */ 0x0, /* */ /* Table19391 */ 0x1b61, /* VGF2P8AFFINEQBZrmbikz */ 0x0, /* */ /* Table19393 */ 0x1b42, /* VGF2P8AFFINEINVQBZrmbikz */ 0x0, /* */ /* Table19395 */ 0xbf3, /* VALIGNDZ128rmikz */ 0xbf6, /* VALIGNDZ128rrikz */ /* Table19397 */ 0x270e, /* VPERMILPSZ128mikz */ 0x2711, /* VPERMILPSZ128rikz */ /* Table19399 */ 0x3818, /* VRNDSCALEPSZ128rmikz */ 0x381b, /* VRNDSCALEPSZ128rrikz */ /* Table19401 */ 0x383f, /* VRNDSCALESSZm_Intkz */ 0x3843, /* VRNDSCALESSZr_Intkz */ /* Table19403 */ 0x21c3, /* VPALIGNRZ128rmikz */ 0x21c6, /* VPALIGNRZ128rrikz */ /* Table19405 */ 0x0, /* */ 0xf48, /* VCVTPS2PHZ128rrkz */ /* Table19407 */ 0x352a, /* VPTERNLOGDZ128rmikz */ 0x352d, /* VPTERNLOGDZ128rrikz */ /* Table19409 */ 0x1b01, /* VGETMANTPSZ128rmikz */ 0x1b04, /* VGETMANTPSZ128rrikz */ /* Table19411 */ 0x1b25, /* VGETMANTSSZrmikz */ 0x1b2b, /* VGETMANTSSZrrikz */ /* Table19413 */ 0x120a, /* VDBPSADBWZ128rmikz */ 0x120d, /* VDBPSADBWZ128rrikz */ /* Table19415 */ 0x3708, /* VRANGEPSZ128rmikz */ 0x370b, /* VRANGEPSZ128rrikz */ /* Table19417 */ 0x372c, /* VRANGESSZrmikz */ 0x3732, /* VRANGESSZrrikz */ /* Table19419 */ 0x1329, /* VFIXUPIMMPSZ128rmikz */ 0x132c, /* VFIXUPIMMPSZ128rrikz */ /* Table19421 */ 0x134d, /* VFIXUPIMMSSZrmikz */ 0x1353, /* VFIXUPIMMSSZrrikz */ /* Table19423 */ 0x37ca, /* VREDUCEPSZ128rmikz */ 0x37cd, /* VREDUCEPSZ128rrikz */ /* Table19425 */ 0x37ee, /* VREDUCESSZrmikz */ 0x37f4, /* VREDUCESSZrrikz */ /* Table19427 */ 0x301d, /* VPSHLDDZ128rmikz */ 0x3020, /* VPSHLDDZ128rrikz */ /* Table19429 */ 0x30b9, /* VPSHRDDZ128rmikz */ 0x30bc, /* VPSHRDDZ128rrikz */ /* Table19431 */ 0xc0e, /* VALIGNQZ128rmikz */ 0xc11, /* VALIGNQZ128rrikz */ /* Table19433 */ 0x26d0, /* VPERMILPDZ128mikz */ 0x26d3, /* VPERMILPDZ128rikz */ /* Table19435 */ 0x37fa, /* VRNDSCALEPDZ128rmikz */ 0x37fd, /* VRNDSCALEPDZ128rrikz */ /* Table19437 */ 0x3834, /* VRNDSCALESDZm_Intkz */ 0x3838, /* VRNDSCALESDZr_Intkz */ /* Table19439 */ 0x3545, /* VPTERNLOGQZ128rmikz */ 0x3548, /* VPTERNLOGQZ128rrikz */ /* Table19441 */ 0x1ae3, /* VGETMANTPDZ128rmikz */ 0x1ae6, /* VGETMANTPDZ128rrikz */ /* Table19443 */ 0x1b1c, /* VGETMANTSDZrmikz */ 0x1b22, /* VGETMANTSDZrrikz */ /* Table19445 */ 0x36ea, /* VRANGEPDZ128rmikz */ 0x36ed, /* VRANGEPDZ128rrikz */ /* Table19447 */ 0x3723, /* VRANGESDZrmikz */ 0x3729, /* VRANGESDZrrikz */ /* Table19449 */ 0x130b, /* VFIXUPIMMPDZ128rmikz */ 0x130e, /* VFIXUPIMMPDZ128rrikz */ /* Table19451 */ 0x1344, /* VFIXUPIMMSDZrmikz */ 0x134a, /* VFIXUPIMMSDZrrikz */ /* Table19453 */ 0x37ac, /* VREDUCEPDZ128rmikz */ 0x37af, /* VREDUCEPDZ128rrikz */ /* Table19455 */ 0x37e5, /* VREDUCESDZrmikz */ 0x37eb, /* VREDUCESDZrrikz */ /* Table19457 */ 0x3098, /* VPSHLDWZ128rmikz */ 0x309b, /* VPSHLDWZ128rrikz */ /* Table19459 */ 0x3038, /* VPSHLDQZ128rmikz */ 0x303b, /* VPSHLDQZ128rrikz */ /* Table19461 */ 0x3134, /* VPSHRDWZ128rmikz */ 0x3137, /* VPSHRDWZ128rrikz */ /* Table19463 */ 0x30d4, /* VPSHRDQZ128rmikz */ 0x30d7, /* VPSHRDQZ128rrikz */ /* Table19465 */ 0x1b52, /* VGF2P8AFFINEQBZ128rmikz */ 0x1b55, /* VGF2P8AFFINEQBZ128rrikz */ /* Table19467 */ 0x1b33, /* VGF2P8AFFINEINVQBZ128rmikz */ 0x1b36, /* VGF2P8AFFINEINVQBZ128rrikz */ /* Table19469 */ 0xbfc, /* VALIGNDZ256rmikz */ 0xbff, /* VALIGNDZ256rrikz */ /* Table19471 */ 0x2720, /* VPERMILPSZ256mikz */ 0x2723, /* VPERMILPSZ256rikz */ /* Table19473 */ 0x3821, /* VRNDSCALEPSZ256rmikz */ 0x3824, /* VRNDSCALEPSZ256rrikz */ /* Table19475 */ 0x21c9, /* VPALIGNRZ256rmikz */ 0x21cc, /* VPALIGNRZ256rrikz */ /* Table19477 */ 0x1b94, /* VINSERTF32x4Z256rmkz */ 0x1b97, /* VINSERTF32x4Z256rrkz */ /* Table19479 */ 0x0, /* */ 0x12c8, /* VEXTRACTF32x4Z256rrkz */ /* Table19481 */ 0x0, /* */ 0xf4d, /* VCVTPS2PHZ256rrkz */ /* Table19483 */ 0x3932, /* VSHUFF32X4Z256rmikz */ 0x3935, /* VSHUFF32X4Z256rrikz */ /* Table19485 */ 0x3533, /* VPTERNLOGDZ256rmikz */ 0x3536, /* VPTERNLOGDZ256rrikz */ /* Table19487 */ 0x1b0a, /* VGETMANTPSZ256rmikz */ 0x1b0d, /* VGETMANTPSZ256rrikz */ /* Table19489 */ 0x1bba, /* VINSERTI32x4Z256rmkz */ 0x1bbd, /* VINSERTI32x4Z256rrkz */ /* Table19491 */ 0x0, /* */ 0x12e8, /* VEXTRACTI32x4Z256rrkz */ /* Table19493 */ 0x1210, /* VDBPSADBWZ256rmikz */ 0x1213, /* VDBPSADBWZ256rrikz */ /* Table19495 */ 0x3956, /* VSHUFI32X4Z256rmikz */ 0x3959, /* VSHUFI32X4Z256rrikz */ /* Table19497 */ 0x3711, /* VRANGEPSZ256rmikz */ 0x3714, /* VRANGEPSZ256rrikz */ /* Table19499 */ 0x1332, /* VFIXUPIMMPSZ256rmikz */ 0x1335, /* VFIXUPIMMPSZ256rrikz */ /* Table19501 */ 0x37d3, /* VREDUCEPSZ256rmikz */ 0x37d6, /* VREDUCEPSZ256rrikz */ /* Table19503 */ 0x3026, /* VPSHLDDZ256rmikz */ 0x3029, /* VPSHLDDZ256rrikz */ /* Table19505 */ 0x30c2, /* VPSHRDDZ256rmikz */ 0x30c5, /* VPSHRDDZ256rrikz */ /* Table19507 */ 0x2784, /* VPERMQZ256mikz */ 0x2787, /* VPERMQZ256rikz */ /* Table19509 */ 0x274a, /* VPERMPDZ256mikz */ 0x274d, /* VPERMPDZ256rikz */ /* Table19511 */ 0xc17, /* VALIGNQZ256rmikz */ 0xc1a, /* VALIGNQZ256rrikz */ /* Table19513 */ 0x26e2, /* VPERMILPDZ256mikz */ 0x26e5, /* VPERMILPDZ256rikz */ /* Table19515 */ 0x3803, /* VRNDSCALEPDZ256rmikz */ 0x3806, /* VRNDSCALEPDZ256rrikz */ /* Table19517 */ 0x1ba6, /* VINSERTF64x2Z256rmkz */ 0x1ba9, /* VINSERTF64x2Z256rrkz */ /* Table19519 */ 0x0, /* */ 0x12d7, /* VEXTRACTF64x2Z256rrkz */ /* Table19521 */ 0x3944, /* VSHUFF64X2Z256rmikz */ 0x3947, /* VSHUFF64X2Z256rrikz */ /* Table19523 */ 0x354e, /* VPTERNLOGQZ256rmikz */ 0x3551, /* VPTERNLOGQZ256rrikz */ /* Table19525 */ 0x1aec, /* VGETMANTPDZ256rmikz */ 0x1aef, /* VGETMANTPDZ256rrikz */ /* Table19527 */ 0x1bcc, /* VINSERTI64x2Z256rmkz */ 0x1bcf, /* VINSERTI64x2Z256rrkz */ /* Table19529 */ 0x0, /* */ 0x12f7, /* VEXTRACTI64x2Z256rrkz */ /* Table19531 */ 0x3968, /* VSHUFI64X2Z256rmikz */ 0x396b, /* VSHUFI64X2Z256rrikz */ /* Table19533 */ 0x36f3, /* VRANGEPDZ256rmikz */ 0x36f6, /* VRANGEPDZ256rrikz */ /* Table19535 */ 0x1314, /* VFIXUPIMMPDZ256rmikz */ 0x1317, /* VFIXUPIMMPDZ256rrikz */ /* Table19537 */ 0x37b5, /* VREDUCEPDZ256rmikz */ 0x37b8, /* VREDUCEPDZ256rrikz */ /* Table19539 */ 0x309e, /* VPSHLDWZ256rmikz */ 0x30a1, /* VPSHLDWZ256rrikz */ /* Table19541 */ 0x3041, /* VPSHLDQZ256rmikz */ 0x3044, /* VPSHLDQZ256rrikz */ /* Table19543 */ 0x313a, /* VPSHRDWZ256rmikz */ 0x313d, /* VPSHRDWZ256rrikz */ /* Table19545 */ 0x30dd, /* VPSHRDQZ256rmikz */ 0x30e0, /* VPSHRDQZ256rrikz */ /* Table19547 */ 0x1b5b, /* VGF2P8AFFINEQBZ256rmikz */ 0x1b5e, /* VGF2P8AFFINEQBZ256rrikz */ /* Table19549 */ 0x1b3c, /* VGF2P8AFFINEINVQBZ256rmikz */ 0x1b3f, /* VGF2P8AFFINEINVQBZ256rrikz */ /* Table19551 */ 0xc05, /* VALIGNDZrmikz */ 0xc08, /* VALIGNDZrrikz */ /* Table19553 */ 0x2732, /* VPERMILPSZmikz */ 0x2735, /* VPERMILPSZrikz */ /* Table19555 */ 0x382a, /* VRNDSCALEPSZrmikz */ 0x3830, /* VRNDSCALEPSZrrikz */ /* Table19557 */ 0x21cf, /* VPALIGNRZrmikz */ 0x21d2, /* VPALIGNRZrrikz */ /* Table19559 */ 0x1b9a, /* VINSERTF32x4Zrmkz */ 0x1b9d, /* VINSERTF32x4Zrrkz */ /* Table19561 */ 0x0, /* */ 0x12cd, /* VEXTRACTF32x4Zrrkz */ /* Table19563 */ 0x1ba0, /* VINSERTF32x8Zrmkz */ 0x1ba3, /* VINSERTF32x8Zrrkz */ /* Table19565 */ 0x0, /* */ 0x12d2, /* VEXTRACTF32x8Zrrkz */ /* Table19567 */ 0x0, /* */ 0xf55, /* VCVTPS2PHZrrkz */ /* Table19569 */ 0x393b, /* VSHUFF32X4Zrmikz */ 0x393e, /* VSHUFF32X4Zrrikz */ /* Table19571 */ 0x353c, /* VPTERNLOGDZrmikz */ 0x353f, /* VPTERNLOGDZrrikz */ /* Table19573 */ 0x1b13, /* VGETMANTPSZrmikz */ 0x1b19, /* VGETMANTPSZrrikz */ /* Table19575 */ 0x1bc0, /* VINSERTI32x4Zrmkz */ 0x1bc3, /* VINSERTI32x4Zrrkz */ /* Table19577 */ 0x0, /* */ 0x12ed, /* VEXTRACTI32x4Zrrkz */ /* Table19579 */ 0x1bc6, /* VINSERTI32x8Zrmkz */ 0x1bc9, /* VINSERTI32x8Zrrkz */ /* Table19581 */ 0x0, /* */ 0x12f2, /* VEXTRACTI32x8Zrrkz */ /* Table19583 */ 0x1216, /* VDBPSADBWZrmikz */ 0x1219, /* VDBPSADBWZrrikz */ /* Table19585 */ 0x395f, /* VSHUFI32X4Zrmikz */ 0x3962, /* VSHUFI32X4Zrrikz */ /* Table19587 */ 0x371a, /* VRANGEPSZrmikz */ 0x3720, /* VRANGEPSZrrikz */ /* Table19589 */ 0x133b, /* VFIXUPIMMPSZrmikz */ 0x1341, /* VFIXUPIMMPSZrrikz */ /* Table19591 */ 0x37dc, /* VREDUCEPSZrmikz */ 0x37e2, /* VREDUCEPSZrrikz */ /* Table19593 */ 0x302f, /* VPSHLDDZrmikz */ 0x3032, /* VPSHLDDZrrikz */ /* Table19595 */ 0x30cb, /* VPSHRDDZrmikz */ 0x30ce, /* VPSHRDDZrrikz */ /* Table19597 */ 0x2796, /* VPERMQZmikz */ 0x2799, /* VPERMQZrikz */ /* Table19599 */ 0x275c, /* VPERMPDZmikz */ 0x275f, /* VPERMPDZrikz */ /* Table19601 */ 0xc20, /* VALIGNQZrmikz */ 0xc23, /* VALIGNQZrrikz */ /* Table19603 */ 0x26f4, /* VPERMILPDZmikz */ 0x26f7, /* VPERMILPDZrikz */ /* Table19605 */ 0x380c, /* VRNDSCALEPDZrmikz */ 0x3812, /* VRNDSCALEPDZrrikz */ /* Table19607 */ 0x1bac, /* VINSERTF64x2Zrmkz */ 0x1baf, /* VINSERTF64x2Zrrkz */ /* Table19609 */ 0x0, /* */ 0x12dc, /* VEXTRACTF64x2Zrrkz */ /* Table19611 */ 0x1bb2, /* VINSERTF64x4Zrmkz */ 0x1bb5, /* VINSERTF64x4Zrrkz */ /* Table19613 */ 0x0, /* */ 0x12e1, /* VEXTRACTF64x4Zrrkz */ /* Table19615 */ 0x394d, /* VSHUFF64X2Zrmikz */ 0x3950, /* VSHUFF64X2Zrrikz */ /* Table19617 */ 0x3557, /* VPTERNLOGQZrmikz */ 0x355a, /* VPTERNLOGQZrrikz */ /* Table19619 */ 0x1af5, /* VGETMANTPDZrmikz */ 0x1afb, /* VGETMANTPDZrrikz */ /* Table19621 */ 0x1bd2, /* VINSERTI64x2Zrmkz */ 0x1bd5, /* VINSERTI64x2Zrrkz */ /* Table19623 */ 0x0, /* */ 0x12fc, /* VEXTRACTI64x2Zrrkz */ /* Table19625 */ 0x1bd8, /* VINSERTI64x4Zrmkz */ 0x1bdb, /* VINSERTI64x4Zrrkz */ /* Table19627 */ 0x0, /* */ 0x1301, /* VEXTRACTI64x4Zrrkz */ /* Table19629 */ 0x3971, /* VSHUFI64X2Zrmikz */ 0x3974, /* VSHUFI64X2Zrrikz */ /* Table19631 */ 0x36fc, /* VRANGEPDZrmikz */ 0x3702, /* VRANGEPDZrrikz */ /* Table19633 */ 0x131d, /* VFIXUPIMMPDZrmikz */ 0x1323, /* VFIXUPIMMPDZrrikz */ /* Table19635 */ 0x37be, /* VREDUCEPDZrmikz */ 0x37c4, /* VREDUCEPDZrrikz */ /* Table19637 */ 0x30a4, /* VPSHLDWZrmikz */ 0x30a7, /* VPSHLDWZrrikz */ /* Table19639 */ 0x304a, /* VPSHLDQZrmikz */ 0x304d, /* VPSHLDQZrrikz */ /* Table19641 */ 0x3140, /* VPSHRDWZrmikz */ 0x3143, /* VPSHRDWZrrikz */ /* Table19643 */ 0x30e6, /* VPSHRDQZrmikz */ 0x30e9, /* VPSHRDQZrrikz */ /* Table19645 */ 0x1b64, /* VGF2P8AFFINEQBZrmikz */ 0x1b67, /* VGF2P8AFFINEQBZrrikz */ /* Table19647 */ 0x1b45, /* VGF2P8AFFINEINVQBZrmikz */ 0x1b48, /* VGF2P8AFFINEINVQBZrrikz */ /* Table19649 */ 0x293f, /* VPMACSSWWrm */ 0x2940, /* VPMACSSWWrr */ /* Table19651 */ 0x293d, /* VPMACSSWDrm */ 0x293e, /* VPMACSSWDrr */ /* Table19653 */ 0x293b, /* VPMACSSDQLrm */ 0x293c, /* VPMACSSDQLrr */ /* Table19655 */ 0x2937, /* VPMACSSDDrm */ 0x2938, /* VPMACSSDDrr */ /* Table19657 */ 0x2939, /* VPMACSSDQHrm */ 0x293a, /* VPMACSSDQHrr */ /* Table19659 */ 0x2943, /* VPMACSWWrm */ 0x2944, /* VPMACSWWrr */ /* Table19661 */ 0x2941, /* VPMACSWDrm */ 0x2942, /* VPMACSWDrr */ /* Table19663 */ 0x2935, /* VPMACSDQLrm */ 0x2936, /* VPMACSDQLrr */ /* Table19665 */ 0x2931, /* VPMACSDDrm */ 0x2932, /* VPMACSDDrr */ /* Table19667 */ 0x2933, /* VPMACSDQHrm */ 0x2934, /* VPMACSDQHrr */ /* Table19669 */ 0x236b, /* VPCMOVrmr */ 0x236d, /* VPCMOVrrr */ /* Table19671 */ 0x2efa, /* VPPERMrmr */ 0x2efc, /* VPPERMrrr */ /* Table19673 */ 0x2945, /* VPMADCSSWDrm */ 0x2946, /* VPMADCSSWDrr */ /* Table19675 */ 0x2947, /* VPMADCSWDrm */ 0x2948, /* VPMADCSWDrr */ /* Table19677 */ 0x2fd6, /* VPROTBmi */ 0x2fd8, /* VPROTBri */ /* Table19679 */ 0x2fe8, /* VPROTWmi */ 0x2fea, /* VPROTWri */ /* Table19681 */ 0x2fdc, /* VPROTDmi */ 0x2fde, /* VPROTDri */ /* Table19683 */ 0x2fe2, /* VPROTQmi */ 0x2fe4, /* VPROTQri */ /* Table19685 */ 0x24ff, /* VPCOMBmi */ 0x2501, /* VPCOMBri */ /* Table19687 */ 0x2557, /* VPCOMWmi */ 0x2559, /* VPCOMWri */ /* Table19689 */ 0x2503, /* VPCOMDmi */ 0x2505, /* VPCOMDri */ /* Table19691 */ 0x2543, /* VPCOMQmi */ 0x2545, /* VPCOMQri */ /* Table19693 */ 0x2547, /* VPCOMUBmi */ 0x2549, /* VPCOMUBri */ /* Table19695 */ 0x2553, /* VPCOMUWmi */ 0x2555, /* VPCOMUWri */ /* Table19697 */ 0x254b, /* VPCOMUDmi */ 0x254d, /* VPCOMUDri */ /* Table19699 */ 0x254f, /* VPCOMUQmi */ 0x2551, /* VPCOMUQri */ /* Table19701 */ 0x236c, /* VPCMOVrrm */ 0x236e, /* VPCMOVrrr_REV */ /* Table19703 */ 0x2efb, /* VPPERMrrm */ 0x2efd, /* VPPERMrrr_REV */ /* Table19705 */ 0x2367, /* VPCMOVYrmr */ 0x2369, /* VPCMOVYrrr */ /* Table19707 */ 0x2368, /* VPCMOVYrrm */ 0x236a, /* VPCMOVYrrr_REV */ /* Table19709 */ 0x0, /* */ 0x155, /* BLCFILL32rm */ 0x171, /* BLSFILL32rm */ 0x165, /* BLCS32rm */ 0xb26, /* TZMSK32rm */ 0x15d, /* BLCIC32rm */ 0x179, /* BLSIC32rm */ 0xafb, /* T1MSKC32rm */ 0x0, /* */ 0x156, /* BLCFILL32rr */ 0x172, /* BLSFILL32rr */ 0x166, /* BLCS32rr */ 0xb27, /* TZMSK32rr */ 0x15e, /* BLCIC32rr */ 0x17a, /* BLSIC32rr */ 0xafc, /* T1MSKC32rr */ /* Table19725 */ 0x0, /* */ 0x161, /* BLCMSK32rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x159, /* BLCI32rm */ 0x0, /* */ 0x0, /* */ 0x162, /* BLCMSK32rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x15a, /* BLCI32rr */ 0x0, /* */ /* Table19741 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4f6, /* LLWPCB */ 0xa67, /* SLWPCB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table19757 */ 0x1a6e, /* VFRCZPSrm */ 0x1a6f, /* VFRCZPSrr */ /* Table19759 */ 0x1a6a, /* VFRCZPDrm */ 0x1a6b, /* VFRCZPDrr */ /* Table19761 */ 0x1a72, /* VFRCZSSrm */ 0x1a73, /* VFRCZSSrr */ /* Table19763 */ 0x1a70, /* VFRCZSDrm */ 0x1a71, /* VFRCZSDrr */ /* Table19765 */ 0x2fd7, /* VPROTBmr */ 0x2fda, /* VPROTBrr */ /* Table19767 */ 0x2fe9, /* VPROTWmr */ 0x2fec, /* VPROTWrr */ /* Table19769 */ 0x2fdd, /* VPROTDmr */ 0x2fe0, /* VPROTDrr */ /* Table19771 */ 0x2fe3, /* VPROTQmr */ 0x2fe6, /* VPROTQrr */ /* Table19773 */ 0x3014, /* VPSHLBmr */ 0x3016, /* VPSHLBrr */ /* Table19775 */ 0x30b0, /* VPSHLWmr */ 0x30b2, /* VPSHLWrr */ /* Table19777 */ 0x30a8, /* VPSHLDmr */ 0x30aa, /* VPSHLDrr */ /* Table19779 */ 0x30ac, /* VPSHLQmr */ 0x30ae, /* VPSHLQrr */ /* Table19781 */ 0x3004, /* VPSHABmr */ 0x3006, /* VPSHABrr */ /* Table19783 */ 0x3010, /* VPSHAWmr */ 0x3012, /* VPSHAWrr */ /* Table19785 */ 0x3008, /* VPSHADmr */ 0x300a, /* VPSHADrr */ /* Table19787 */ 0x300c, /* VPSHAQmr */ 0x300e, /* VPSHAQrr */ /* Table19789 */ 0x28b7, /* VPHADDBWrm */ 0x28b8, /* VPHADDBWrr */ /* Table19791 */ 0x28b3, /* VPHADDBDrm */ 0x28b4, /* VPHADDBDrr */ /* Table19793 */ 0x28b5, /* VPHADDBQrm */ 0x28b6, /* VPHADDBQrr */ /* Table19795 */ 0x28cf, /* VPHADDWDrm */ 0x28d0, /* VPHADDWDrr */ /* Table19797 */ 0x28d1, /* VPHADDWQrm */ 0x28d2, /* VPHADDWQrr */ /* Table19799 */ 0x28b9, /* VPHADDDQrm */ 0x28ba, /* VPHADDDQrr */ /* Table19801 */ 0x28c7, /* VPHADDUBWrm */ 0x28c8, /* VPHADDUBWrr */ /* Table19803 */ 0x28c3, /* VPHADDUBDrm */ 0x28c4, /* VPHADDUBDrr */ /* Table19805 */ 0x28c5, /* VPHADDUBQrm */ 0x28c6, /* VPHADDUBQrr */ /* Table19807 */ 0x28cb, /* VPHADDUWDrm */ 0x28cc, /* VPHADDUWDrr */ /* Table19809 */ 0x28cd, /* VPHADDUWQrm */ 0x28ce, /* VPHADDUWQrr */ /* Table19811 */ 0x28c9, /* VPHADDUDQrm */ 0x28ca, /* VPHADDUDQrr */ /* Table19813 */ 0x28d9, /* VPHSUBBWrm */ 0x28da, /* VPHSUBBWrr */ /* Table19815 */ 0x28e5, /* VPHSUBWDrm */ 0x28e6, /* VPHSUBWDrr */ /* Table19817 */ 0x28db, /* VPHSUBDQrm */ 0x28dc, /* VPHSUBDQrr */ /* Table19819 */ 0x0, /* */ 0x157, /* BLCFILL64rm */ 0x173, /* BLSFILL64rm */ 0x167, /* BLCS64rm */ 0xb28, /* TZMSK64rm */ 0x15f, /* BLCIC64rm */ 0x17b, /* BLSIC64rm */ 0xafd, /* T1MSKC64rm */ 0x0, /* */ 0x158, /* BLCFILL64rr */ 0x174, /* BLSFILL64rr */ 0x168, /* BLCS64rr */ 0xb29, /* TZMSK64rr */ 0x160, /* BLCIC64rr */ 0x17c, /* BLSIC64rr */ 0xafe, /* T1MSKC64rr */ /* Table19835 */ 0x0, /* */ 0x163, /* BLCMSK64rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x15b, /* BLCI64rm */ 0x0, /* */ 0x0, /* */ 0x164, /* BLCMSK64rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x15c, /* BLCI64rr */ 0x0, /* */ /* Table19851 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x4f7, /* LLWPCB64 */ 0xa68, /* SLWPCB64 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table19867 */ 0x2fd9, /* VPROTBrm */ 0x2fdb, /* VPROTBrr_REV */ /* Table19869 */ 0x2feb, /* VPROTWrm */ 0x2fed, /* VPROTWrr_REV */ /* Table19871 */ 0x2fdf, /* VPROTDrm */ 0x2fe1, /* VPROTDrr_REV */ /* Table19873 */ 0x2fe5, /* VPROTQrm */ 0x2fe7, /* VPROTQrr_REV */ /* Table19875 */ 0x3015, /* VPSHLBrm */ 0x3017, /* VPSHLBrr_REV */ /* Table19877 */ 0x30b1, /* VPSHLWrm */ 0x30b3, /* VPSHLWrr_REV */ /* Table19879 */ 0x30a9, /* VPSHLDrm */ 0x30ab, /* VPSHLDrr_REV */ /* Table19881 */ 0x30ad, /* VPSHLQrm */ 0x30af, /* VPSHLQrr_REV */ /* Table19883 */ 0x3005, /* VPSHABrm */ 0x3007, /* VPSHABrr_REV */ /* Table19885 */ 0x3011, /* VPSHAWrm */ 0x3013, /* VPSHAWrr_REV */ /* Table19887 */ 0x3009, /* VPSHADrm */ 0x300b, /* VPSHADrr_REV */ /* Table19889 */ 0x300d, /* VPSHAQrm */ 0x300f, /* VPSHAQrr_REV */ /* Table19891 */ 0x1a6c, /* VFRCZPSYrm */ 0x1a6d, /* VFRCZPSYrr */ /* Table19893 */ 0x1a68, /* VFRCZPDYrm */ 0x1a69, /* VFRCZPDYrr */ /* Table19895 */ 0x151, /* BEXTRI32mi */ 0x152, /* BEXTRI32ri */ /* Table19897 */ 0x513, /* LWPINS32rmi */ 0x517, /* LWPVAL32rmi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x514, /* LWPINS32rri */ 0x518, /* LWPVAL32rri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table19913 */ 0x153, /* BEXTRI64mi */ 0x154, /* BEXTRI64ri */ /* Table19915 */ 0x515, /* LWPINS64rmi */ 0x519, /* LWPVAL64rmi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x516, /* LWPINS64rri */ 0x51a, /* LWPVAL64rri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table19931 */ 0x7ed, /* PI2FWrm */ 0x7ee, /* PI2FWrr */ /* Table19933 */ 0x7eb, /* PI2FDrm */ 0x7ec, /* PI2FDrr */ /* Table19935 */ 0x7b9, /* PF2IWrm */ 0x7ba, /* PF2IWrr */ /* Table19937 */ 0x7b7, /* PF2IDrm */ 0x7b8, /* PF2IDrr */ /* Table19939 */ 0x7cb, /* PFNACCrm */ 0x7cc, /* PFNACCrr */ /* Table19941 */ 0x7cd, /* PFPNACCrm */ 0x7ce, /* PFPNACCrr */ /* Table19943 */ 0x7c1, /* PFCMPGErm */ 0x7c2, /* PFCMPGErr */ /* Table19945 */ 0x7c7, /* PFMINrm */ 0x7c8, /* PFMINrr */ /* Table19947 */ 0x7d3, /* PFRCPrm */ 0x7d4, /* PFRCPrr */ /* Table19949 */ 0x7d7, /* PFRSQRTrm */ 0x7d8, /* PFRSQRTrr */ /* Table19951 */ 0x7db, /* PFSUBrm */ 0x7dc, /* PFSUBrr */ /* Table19953 */ 0x7bd, /* PFADDrm */ 0x7be, /* PFADDrr */ /* Table19955 */ 0x7c3, /* PFCMPGTrm */ 0x7c4, /* PFCMPGTrr */ /* Table19957 */ 0x7c5, /* PFMAXrm */ 0x7c6, /* PFMAXrr */ /* Table19959 */ 0x7cf, /* PFRCPIT1rm */ 0x7d0, /* PFRCPIT1rr */ /* Table19961 */ 0x7d5, /* PFRSQIT1rm */ 0x7d6, /* PFRSQIT1rr */ /* Table19963 */ 0x7d9, /* PFSUBRrm */ 0x7da, /* PFSUBRrr */ /* Table19965 */ 0x7bb, /* PFACCrm */ 0x7bc, /* PFACCrr */ /* Table19967 */ 0x7bf, /* PFCMPEQrm */ 0x7c0, /* PFCMPEQrr */ /* Table19969 */ 0x7c9, /* PFMULrm */ 0x7ca, /* PFMULrr */ /* Table19971 */ 0x7d1, /* PFRCPIT2rm */ 0x7d2, /* PFRCPIT2rr */ /* Table19973 */ 0x830, /* PMULHRWrm */ 0x831, /* PMULHRWrr */ /* Table19975 */ 0x89f, /* PSWAPDrm */ 0x8a0, /* PSWAPDrr */ /* Table19977 */ 0x783, /* PAVGUSBrm */ 0x784, /* PAVGUSBrr */ 0x0 }; capstone-sys-0.15.0/capstone/arch/X86/X86GenDisassemblerTables2.inc000064400000000000000000124022600072674642500230010ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ static const unsigned char index_x86DisassemblerOneByteOpcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 16, 17, 18, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86DisassemblerOneByteOpcodes[] = { { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 3 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 7 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 10 }, { MODRM_ONEENTRY, 11 }, { MODRM_ONEENTRY, 12 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 15 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 19 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 22 }, { MODRM_ONEENTRY, 23 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 26 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 30 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 33 }, { MODRM_ONEENTRY, 34 }, { MODRM_ONEENTRY, 35 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 38 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 42 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 45 }, { MODRM_ONEENTRY, 46 }, { MODRM_ONEENTRY, 47 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 50 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 54 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 57 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 58 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 61 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 65 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 68 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 69 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 72 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 76 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 79 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 80 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 83 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 87 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 90 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 91 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 96 }, { MODRM_ONEENTRY, 97 }, { MODRM_SPLITRM, 98 }, { MODRM_SPLITRM, 100 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 103 }, { MODRM_SPLITRM, 104 }, { MODRM_ONEENTRY, 106 }, { MODRM_SPLITRM, 107 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 110 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 112 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 145 }, { MODRM_SPLITREG, 161 }, { MODRM_SPLITREG, 177 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 195 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 199 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 203 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 207 }, { MODRM_SPLITRM, 209 }, { MODRM_SPLITRM, 211 }, { MODRM_SPLITRM, 213 }, { MODRM_SPLITREG, 215 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 233 }, { MODRM_ONEENTRY, 234 }, { MODRM_ONEENTRY, 235 }, { MODRM_ONEENTRY, 236 }, { MODRM_ONEENTRY, 237 }, { MODRM_ONEENTRY, 238 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 241 }, { MODRM_ONEENTRY, 242 }, { MODRM_ONEENTRY, 243 }, { MODRM_ONEENTRY, 244 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_SPLITREG, 259 }, { MODRM_SPLITREG, 275 }, { MODRM_ONEENTRY, 291 }, { MODRM_ONEENTRY, 292 }, { MODRM_SPLITRM, 293 }, { MODRM_SPLITRM, 295 }, { MODRM_SPLITMISC, 297 }, { MODRM_SPLITMISC, 369 }, { MODRM_ONEENTRY, 441 }, { MODRM_ONEENTRY, 442 }, { MODRM_ONEENTRY, 443 }, { MODRM_ONEENTRY, 444 }, { MODRM_ONEENTRY, 445 }, { MODRM_ONEENTRY, 446 }, { MODRM_ONEENTRY, 447 }, { MODRM_ONEENTRY, 448 }, { MODRM_SPLITREG, 449 }, { MODRM_SPLITREG, 465 }, { MODRM_SPLITREG, 481 }, { MODRM_SPLITREG, 497 }, { MODRM_ONEENTRY, 513 }, { MODRM_ONEENTRY, 514 }, { MODRM_ONEENTRY, 515 }, { MODRM_ONEENTRY, 516 }, { MODRM_SPLITREG, 517 }, { MODRM_SPLITMISC, 533 }, { MODRM_SPLITMISC, 605 }, { MODRM_SPLITMISC, 677 }, { MODRM_SPLITREG, 749 }, { MODRM_SPLITREG, 765 }, { MODRM_SPLITMISC, 781 }, { MODRM_SPLITMISC, 853 }, { MODRM_ONEENTRY, 925 }, { MODRM_ONEENTRY, 926 }, { MODRM_ONEENTRY, 927 }, { MODRM_ONEENTRY, 928 }, { MODRM_ONEENTRY, 929 }, { MODRM_ONEENTRY, 930 }, { MODRM_ONEENTRY, 931 }, { MODRM_ONEENTRY, 932 }, { MODRM_ONEENTRY, 933 }, { MODRM_ONEENTRY, 934 }, { MODRM_ONEENTRY, 935 }, { MODRM_ONEENTRY, 936 }, { MODRM_ONEENTRY, 937 }, { MODRM_ONEENTRY, 938 }, { MODRM_ONEENTRY, 939 }, { MODRM_ONEENTRY, 940 }, { MODRM_ONEENTRY, 941 }, { MODRM_ONEENTRY, 942 }, { MODRM_ONEENTRY, 943 }, { MODRM_ONEENTRY, 944 }, { MODRM_ONEENTRY, 945 }, { MODRM_ONEENTRY, 946 }, { MODRM_SPLITREG, 947 }, { MODRM_SPLITREG, 963 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 981 }, { MODRM_ONEENTRY, 982 }, { MODRM_ONEENTRY, 983 }, { MODRM_ONEENTRY, 984 }, { MODRM_SPLITREG, 985 }, { MODRM_SPLITREG, 1001 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 3 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 7 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 10 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 15 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 19 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 22 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 26 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 30 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 33 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 38 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 42 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 45 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 50 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 54 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 57 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 61 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 65 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 68 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 72 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 76 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 79 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 83 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 87 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 90 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1017 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1020 }, { MODRM_SPLITRM, 104 }, { MODRM_ONEENTRY, 1021 }, { MODRM_SPLITRM, 107 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 110 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 112 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 145 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 177 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 195 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 199 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 203 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 207 }, { MODRM_SPLITRM, 209 }, { MODRM_SPLITRM, 1022 }, { MODRM_SPLITRM, 213 }, { MODRM_SPLITREG, 1024 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 233 }, { MODRM_ONEENTRY, 234 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 236 }, { MODRM_ONEENTRY, 1040 }, { MODRM_ONEENTRY, 1041 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 1042 }, { MODRM_ONEENTRY, 1043 }, { MODRM_ONEENTRY, 1044 }, { MODRM_ONEENTRY, 1045 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_ONEENTRY, 258 }, { MODRM_SPLITREG, 259 }, { MODRM_SPLITREG, 275 }, { MODRM_ONEENTRY, 1046 }, { MODRM_ONEENTRY, 1047 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 297 }, { MODRM_SPLITMISC, 369 }, { MODRM_ONEENTRY, 441 }, { MODRM_ONEENTRY, 1048 }, { MODRM_ONEENTRY, 443 }, { MODRM_ONEENTRY, 444 }, { MODRM_ONEENTRY, 445 }, { MODRM_ONEENTRY, 446 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 448 }, { MODRM_SPLITREG, 449 }, { MODRM_SPLITREG, 465 }, { MODRM_SPLITREG, 481 }, { MODRM_SPLITREG, 497 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 516 }, { MODRM_SPLITREG, 517 }, { MODRM_SPLITMISC, 533 }, { MODRM_SPLITMISC, 605 }, { MODRM_SPLITMISC, 677 }, { MODRM_SPLITREG, 749 }, { MODRM_SPLITREG, 765 }, { MODRM_SPLITMISC, 781 }, { MODRM_SPLITMISC, 853 }, { MODRM_ONEENTRY, 925 }, { MODRM_ONEENTRY, 926 }, { MODRM_ONEENTRY, 927 }, { MODRM_ONEENTRY, 1049 }, { MODRM_ONEENTRY, 929 }, { MODRM_ONEENTRY, 930 }, { MODRM_ONEENTRY, 931 }, { MODRM_ONEENTRY, 932 }, { MODRM_ONEENTRY, 1050 }, { MODRM_ONEENTRY, 934 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 936 }, { MODRM_ONEENTRY, 937 }, { MODRM_ONEENTRY, 938 }, { MODRM_ONEENTRY, 939 }, { MODRM_ONEENTRY, 940 }, { MODRM_ONEENTRY, 941 }, { MODRM_ONEENTRY, 942 }, { MODRM_ONEENTRY, 943 }, { MODRM_ONEENTRY, 944 }, { MODRM_ONEENTRY, 945 }, { MODRM_ONEENTRY, 946 }, { MODRM_SPLITREG, 947 }, { MODRM_SPLITREG, 963 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 981 }, { MODRM_ONEENTRY, 982 }, { MODRM_ONEENTRY, 983 }, { MODRM_ONEENTRY, 984 }, { MODRM_SPLITREG, 985 }, { MODRM_SPLITREG, 1051 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 1067 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 1069 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 1071 }, { MODRM_ONEENTRY, 1072 }, { MODRM_ONEENTRY, 1073 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 1074 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 1076 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 1078 }, { MODRM_ONEENTRY, 1079 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 1080 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 1082 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 1084 }, { MODRM_ONEENTRY, 1085 }, { MODRM_ONEENTRY, 1086 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 1087 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 1089 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 1091 }, { MODRM_ONEENTRY, 1092 }, { MODRM_ONEENTRY, 1093 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 1094 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 1096 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 1098 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 58 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 1099 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 1101 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 1103 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 69 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 1104 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 1106 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 1108 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 80 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 1109 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 1111 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 1113 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 91 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1114 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1115 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1118 }, { MODRM_ONEENTRY, 1119 }, { MODRM_SPLITRM, 1120 }, { MODRM_SPLITRM, 100 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1122 }, { MODRM_SPLITRM, 1123 }, { MODRM_ONEENTRY, 1125 }, { MODRM_SPLITRM, 1126 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 1128 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 1129 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 1130 }, { MODRM_SPLITREG, 161 }, { MODRM_SPLITREG, 1146 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 1162 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 1164 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 1166 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 1168 }, { MODRM_SPLITRM, 1170 }, { MODRM_SPLITRM, 1172 }, { MODRM_SPLITRM, 1174 }, { MODRM_SPLITREG, 1176 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1192 }, { MODRM_ONEENTRY, 1193 }, { MODRM_ONEENTRY, 1194 }, { MODRM_ONEENTRY, 1195 }, { MODRM_ONEENTRY, 236 }, { MODRM_ONEENTRY, 1196 }, { MODRM_ONEENTRY, 1197 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 241 }, { MODRM_ONEENTRY, 1198 }, { MODRM_ONEENTRY, 243 }, { MODRM_ONEENTRY, 1199 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 1200 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 1201 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 1202 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 1203 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 1204 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 1205 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_ONEENTRY, 1206 }, { MODRM_SPLITREG, 259 }, { MODRM_SPLITREG, 1207 }, { MODRM_ONEENTRY, 1223 }, { MODRM_ONEENTRY, 1224 }, { MODRM_SPLITRM, 1225 }, { MODRM_SPLITRM, 1227 }, { MODRM_SPLITMISC, 297 }, { MODRM_SPLITMISC, 1229 }, { MODRM_ONEENTRY, 441 }, { MODRM_ONEENTRY, 442 }, { MODRM_ONEENTRY, 1301 }, { MODRM_ONEENTRY, 1302 }, { MODRM_ONEENTRY, 445 }, { MODRM_ONEENTRY, 446 }, { MODRM_ONEENTRY, 447 }, { MODRM_ONEENTRY, 1303 }, { MODRM_SPLITREG, 449 }, { MODRM_SPLITREG, 1304 }, { MODRM_SPLITREG, 481 }, { MODRM_SPLITREG, 1320 }, { MODRM_ONEENTRY, 513 }, { MODRM_ONEENTRY, 514 }, { MODRM_ONEENTRY, 515 }, { MODRM_ONEENTRY, 516 }, { MODRM_SPLITREG, 517 }, { MODRM_SPLITMISC, 533 }, { MODRM_SPLITMISC, 605 }, { MODRM_SPLITMISC, 677 }, { MODRM_SPLITREG, 749 }, { MODRM_SPLITREG, 765 }, { MODRM_SPLITMISC, 781 }, { MODRM_SPLITMISC, 853 }, { MODRM_ONEENTRY, 925 }, { MODRM_ONEENTRY, 926 }, { MODRM_ONEENTRY, 927 }, { MODRM_ONEENTRY, 928 }, { MODRM_ONEENTRY, 929 }, { MODRM_ONEENTRY, 1336 }, { MODRM_ONEENTRY, 931 }, { MODRM_ONEENTRY, 1337 }, { MODRM_ONEENTRY, 1338 }, { MODRM_ONEENTRY, 1339 }, { MODRM_ONEENTRY, 1340 }, { MODRM_ONEENTRY, 936 }, { MODRM_ONEENTRY, 937 }, { MODRM_ONEENTRY, 1341 }, { MODRM_ONEENTRY, 939 }, { MODRM_ONEENTRY, 1342 }, { MODRM_ONEENTRY, 941 }, { MODRM_ONEENTRY, 942 }, { MODRM_ONEENTRY, 943 }, { MODRM_ONEENTRY, 944 }, { MODRM_ONEENTRY, 945 }, { MODRM_ONEENTRY, 946 }, { MODRM_SPLITREG, 947 }, { MODRM_SPLITREG, 1343 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 981 }, { MODRM_ONEENTRY, 982 }, { MODRM_ONEENTRY, 983 }, { MODRM_ONEENTRY, 984 }, { MODRM_SPLITREG, 985 }, { MODRM_SPLITREG, 1359 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 3 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 7 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 10 }, { MODRM_ONEENTRY, 11 }, { MODRM_ONEENTRY, 12 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 15 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 19 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 22 }, { MODRM_ONEENTRY, 23 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 26 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 30 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 33 }, { 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{ MODRM_ONEENTRY, 984 }, { MODRM_SPLITREG, 985 }, { MODRM_SPLITREG, 1626 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 1383 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 1385 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 1387 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 1388 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 1390 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 1392 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 1393 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 1395 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 1397 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 1398 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 1400 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 1402 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 1403 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 1405 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 1407 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 1408 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 1410 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 1412 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 1413 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 1415 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 1417 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 1418 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 1420 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 1422 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1017 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1018 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 1019 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1423 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1020 }, { MODRM_SPLITRM, 1425 }, { MODRM_ONEENTRY, 1021 }, { MODRM_SPLITRM, 1427 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 110 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 112 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 1429 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1445 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 1461 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 1463 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 1465 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 1467 }, { MODRM_SPLITRM, 1469 }, { MODRM_SPLITRM, 1471 }, { MODRM_SPLITRM, 1473 }, { MODRM_SPLITREG, 1024 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1476 }, { MODRM_ONEENTRY, 1477 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 236 }, { MODRM_ONEENTRY, 1040 }, { MODRM_ONEENTRY, 1041 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 1042 }, { MODRM_ONEENTRY, 1478 }, { MODRM_ONEENTRY, 1044 }, { MODRM_ONEENTRY, 1479 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 1480 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 1481 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 1482 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 1483 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 1484 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 1485 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_SPLITREG, 259 }, { MODRM_SPLITREG, 1487 }, { MODRM_ONEENTRY, 1046 }, { MODRM_ONEENTRY, 1047 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 297 }, { MODRM_SPLITMISC, 1503 }, { MODRM_ONEENTRY, 441 }, { MODRM_ONEENTRY, 1048 }, { MODRM_ONEENTRY, 1575 }, { MODRM_ONEENTRY, 1576 }, { MODRM_ONEENTRY, 445 }, { MODRM_ONEENTRY, 446 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1577 }, { MODRM_SPLITREG, 449 }, { MODRM_SPLITREG, 1578 }, { MODRM_SPLITREG, 481 }, { MODRM_SPLITREG, 1594 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 516 }, { MODRM_SPLITREG, 517 }, { MODRM_SPLITMISC, 533 }, { MODRM_SPLITMISC, 605 }, { MODRM_SPLITMISC, 677 }, { MODRM_SPLITREG, 749 }, { MODRM_SPLITREG, 765 }, { MODRM_SPLITMISC, 781 }, { MODRM_SPLITMISC, 853 }, { MODRM_ONEENTRY, 925 }, { MODRM_ONEENTRY, 926 }, { MODRM_ONEENTRY, 927 }, { MODRM_ONEENTRY, 1049 }, { MODRM_ONEENTRY, 929 }, { MODRM_ONEENTRY, 930 }, { MODRM_ONEENTRY, 931 }, { MODRM_ONEENTRY, 932 }, { MODRM_ONEENTRY, 1050 }, { MODRM_ONEENTRY, 934 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 936 }, { MODRM_ONEENTRY, 937 }, { MODRM_ONEENTRY, 938 }, { MODRM_ONEENTRY, 939 }, { MODRM_ONEENTRY, 940 }, { MODRM_ONEENTRY, 941 }, { MODRM_ONEENTRY, 942 }, { MODRM_ONEENTRY, 943 }, { MODRM_ONEENTRY, 944 }, { MODRM_ONEENTRY, 945 }, { MODRM_ONEENTRY, 946 }, { MODRM_SPLITREG, 947 }, { MODRM_SPLITREG, 1610 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 981 }, { MODRM_ONEENTRY, 982 }, { MODRM_ONEENTRY, 983 }, { MODRM_ONEENTRY, 984 }, { MODRM_SPLITREG, 985 }, { MODRM_SPLITREG, 1626 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 1383 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 1385 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 1387 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 1388 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 1390 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 1392 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 1393 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 1395 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 1397 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 1398 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 1400 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 1402 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 1403 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 1405 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 1407 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 1408 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 1410 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 1412 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 1413 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 1415 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 1417 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 1418 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 1420 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 1422 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1017 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1116 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 1117 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1423 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1122 }, { MODRM_SPLITRM, 1425 }, { MODRM_ONEENTRY, 1125 }, { MODRM_SPLITRM, 1427 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 1128 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 1129 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 1429 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1445 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 1461 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 1463 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 1465 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 1467 }, { MODRM_SPLITRM, 1469 }, { MODRM_SPLITRM, 1471 }, { MODRM_SPLITRM, 1473 }, { MODRM_SPLITREG, 1176 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1475 }, { MODRM_ONEENTRY, 1476 }, { MODRM_ONEENTRY, 1477 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 236 }, { MODRM_ONEENTRY, 1196 }, { MODRM_ONEENTRY, 1197 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 1042 }, { MODRM_ONEENTRY, 1478 }, { MODRM_ONEENTRY, 1044 }, { MODRM_ONEENTRY, 1479 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 1480 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 1481 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 1482 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 1483 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 1484 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 1485 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_ONEENTRY, 1486 }, { MODRM_SPLITREG, 259 }, { MODRM_SPLITREG, 1487 }, { MODRM_ONEENTRY, 1223 }, { MODRM_ONEENTRY, 1224 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 297 }, { MODRM_SPLITMISC, 1644 }, { MODRM_ONEENTRY, 441 }, { MODRM_ONEENTRY, 1048 }, { MODRM_ONEENTRY, 1575 }, { MODRM_ONEENTRY, 1576 }, { MODRM_ONEENTRY, 445 }, { MODRM_ONEENTRY, 446 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1577 }, { MODRM_SPLITREG, 449 }, { MODRM_SPLITREG, 1578 }, { MODRM_SPLITREG, 481 }, { MODRM_SPLITREG, 1594 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 516 }, { MODRM_SPLITREG, 517 }, { MODRM_SPLITMISC, 533 }, { MODRM_SPLITMISC, 605 }, { MODRM_SPLITMISC, 677 }, { MODRM_SPLITREG, 749 }, { MODRM_SPLITREG, 765 }, { MODRM_SPLITMISC, 781 }, { MODRM_SPLITMISC, 853 }, { MODRM_ONEENTRY, 925 }, { MODRM_ONEENTRY, 926 }, { MODRM_ONEENTRY, 927 }, { MODRM_ONEENTRY, 1049 }, { MODRM_ONEENTRY, 929 }, { MODRM_ONEENTRY, 1336 }, { MODRM_ONEENTRY, 931 }, { MODRM_ONEENTRY, 1337 }, { MODRM_ONEENTRY, 1338 }, { MODRM_ONEENTRY, 1339 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 936 }, { MODRM_ONEENTRY, 937 }, { MODRM_ONEENTRY, 1341 }, { MODRM_ONEENTRY, 939 }, { MODRM_ONEENTRY, 1342 }, { MODRM_ONEENTRY, 941 }, { MODRM_ONEENTRY, 942 }, { MODRM_ONEENTRY, 943 }, { MODRM_ONEENTRY, 944 }, { MODRM_ONEENTRY, 945 }, { MODRM_ONEENTRY, 946 }, { MODRM_SPLITREG, 947 }, { MODRM_SPLITREG, 1610 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 981 }, { MODRM_ONEENTRY, 982 }, { MODRM_ONEENTRY, 983 }, { MODRM_ONEENTRY, 984 }, { MODRM_SPLITREG, 985 }, { MODRM_SPLITREG, 1716 }, } }, }; static const unsigned char index_x86DisassemblerTwoByteOpcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 8, 0, 9, 10, 11, 12, 13, 14, 15, 16, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, }; static const struct OpcodeDecision x86DisassemblerTwoByteOpcodes[] = { { { { MODRM_SPLITREG, 1750 }, { MODRM_SPLITMISC, 1766 }, { MODRM_SPLITRM, 1838 }, { MODRM_SPLITRM, 1840 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1865 }, { MODRM_SPLITRM, 1867 }, { MODRM_SPLITRM, 1869 }, { MODRM_SPLITRM, 1871 }, { MODRM_SPLITRM, 1873 }, { MODRM_SPLITRM, 1875 }, { MODRM_SPLITRM, 1877 }, { MODRM_SPLITRM, 1879 }, { MODRM_SPLITREG, 1881 }, { MODRM_SPLITRM, 1897 }, { MODRM_SPLITRM, 1899 }, { MODRM_SPLITRM, 1901 }, { MODRM_SPLITREG, 1903 }, { MODRM_SPLITRM, 1919 }, { MODRM_SPLITRM, 1921 }, { MODRM_SPLITRM, 1923 }, { MODRM_SPLITRM, 1925 }, { MODRM_SPLITRM, 1927 }, { MODRM_SPLITRM, 1929 }, { MODRM_SPLITRM, 1931 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1933 }, { MODRM_SPLITRM, 1935 }, { MODRM_SPLITRM, 1937 }, { MODRM_SPLITRM, 1939 }, { MODRM_SPLITRM, 1941 }, { MODRM_SPLITRM, 1943 }, { MODRM_SPLITRM, 1945 }, { MODRM_SPLITRM, 1947 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1956 }, { MODRM_SPLITRM, 1958 }, { MODRM_SPLITRM, 1960 }, { MODRM_SPLITRM, 1962 }, { MODRM_SPLITRM, 1964 }, { MODRM_SPLITRM, 1966 }, { MODRM_SPLITRM, 1968 }, { MODRM_SPLITRM, 1970 }, { MODRM_SPLITRM, 1972 }, { MODRM_SPLITRM, 1974 }, { MODRM_SPLITRM, 1976 }, { MODRM_SPLITRM, 1978 }, { MODRM_SPLITRM, 1980 }, { MODRM_SPLITRM, 1982 }, { MODRM_SPLITRM, 1984 }, { MODRM_SPLITRM, 1986 }, { MODRM_SPLITRM, 1988 }, { MODRM_SPLITRM, 1990 }, { MODRM_SPLITRM, 1992 }, { MODRM_SPLITRM, 1994 }, { MODRM_SPLITRM, 1996 }, { MODRM_SPLITRM, 1998 }, { MODRM_SPLITRM, 2000 }, { MODRM_SPLITRM, 2002 }, { MODRM_SPLITRM, 2004 }, { MODRM_SPLITRM, 2006 }, { MODRM_SPLITRM, 2008 }, { MODRM_SPLITRM, 2010 }, { MODRM_SPLITRM, 2012 }, { MODRM_SPLITRM, 2014 }, { MODRM_SPLITRM, 2016 }, { MODRM_SPLITRM, 2018 }, { MODRM_SPLITRM, 2020 }, { MODRM_SPLITRM, 2022 }, { MODRM_SPLITRM, 2024 }, { MODRM_SPLITRM, 2026 }, { MODRM_SPLITRM, 2028 }, { MODRM_SPLITRM, 2030 }, { MODRM_SPLITRM, 2032 }, { MODRM_SPLITRM, 2034 }, { MODRM_SPLITRM, 2036 }, { MODRM_SPLITRM, 2038 }, { MODRM_SPLITRM, 2040 }, { MODRM_SPLITRM, 2042 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2044 }, { MODRM_SPLITRM, 2046 }, { MODRM_SPLITRM, 2048 }, { MODRM_SPLITREG, 2050 }, { MODRM_SPLITREG, 2066 }, { MODRM_SPLITREG, 2082 }, { MODRM_SPLITRM, 2098 }, { MODRM_SPLITRM, 2100 }, { MODRM_SPLITRM, 2102 }, { MODRM_ONEENTRY, 2104 }, { MODRM_SPLITRM, 2105 }, { MODRM_SPLITRM, 2107 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2109 }, { MODRM_SPLITRM, 2111 }, { MODRM_ONEENTRY, 2113 }, { MODRM_ONEENTRY, 2114 }, { MODRM_ONEENTRY, 2115 }, { MODRM_ONEENTRY, 2116 }, { MODRM_ONEENTRY, 2117 }, { MODRM_ONEENTRY, 2118 }, { MODRM_ONEENTRY, 2119 }, { MODRM_ONEENTRY, 2120 }, { MODRM_ONEENTRY, 2121 }, { MODRM_ONEENTRY, 2122 }, { MODRM_ONEENTRY, 2123 }, { MODRM_ONEENTRY, 2124 }, { MODRM_ONEENTRY, 2125 }, { MODRM_ONEENTRY, 2126 }, { MODRM_ONEENTRY, 2127 }, { MODRM_ONEENTRY, 2128 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2161 }, { MODRM_ONEENTRY, 2162 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2164 }, { MODRM_SPLITRM, 2166 }, { MODRM_SPLITRM, 2168 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2314 }, { MODRM_ONEENTRY, 2315 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2317 }, { MODRM_SPLITRM, 2319 }, { MODRM_SPLITRM, 2321 }, { MODRM_SPLITMISC, 2323 }, { MODRM_SPLITRM, 2395 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 2399 }, { MODRM_SPLITRM, 2401 }, { MODRM_SPLITRM, 2403 }, { MODRM_SPLITRM, 2405 }, { MODRM_SPLITRM, 2407 }, { MODRM_SPLITRM, 2409 }, { MODRM_SPLITRM, 2411 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 2414 }, { MODRM_SPLITRM, 2430 }, { MODRM_SPLITRM, 2432 }, { MODRM_SPLITRM, 2434 }, { MODRM_SPLITRM, 2436 }, { MODRM_SPLITRM, 2438 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 2442 }, { MODRM_SPLITRM, 2444 }, { MODRM_SPLITRM, 2446 }, { MODRM_SPLITRM, 2448 }, { MODRM_SPLITRM, 2450 }, { MODRM_SPLITRM, 2452 }, { MODRM_SPLITREG, 2454 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2471 }, { MODRM_SPLITRM, 2473 }, { MODRM_SPLITRM, 2475 }, { MODRM_SPLITRM, 2477 }, { MODRM_SPLITRM, 2479 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2481 }, { MODRM_SPLITRM, 2483 }, { MODRM_SPLITRM, 2485 }, { MODRM_SPLITRM, 2487 }, { MODRM_SPLITRM, 2489 }, { MODRM_SPLITRM, 2491 }, { MODRM_SPLITRM, 2493 }, { MODRM_SPLITRM, 2495 }, { MODRM_SPLITRM, 2497 }, { MODRM_SPLITRM, 2499 }, { MODRM_SPLITRM, 2501 }, { MODRM_SPLITRM, 2503 }, { MODRM_SPLITRM, 2505 }, { MODRM_SPLITRM, 2507 }, { MODRM_SPLITRM, 2509 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2511 }, { MODRM_SPLITRM, 2513 }, { MODRM_SPLITRM, 2515 }, { MODRM_SPLITRM, 2517 }, { MODRM_SPLITRM, 2519 }, { MODRM_SPLITRM, 2521 }, { MODRM_SPLITRM, 2523 }, { MODRM_SPLITRM, 2525 }, { MODRM_SPLITRM, 2527 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2529 }, { MODRM_SPLITRM, 2531 }, { MODRM_SPLITRM, 2533 }, { MODRM_SPLITRM, 2535 }, { MODRM_SPLITRM, 2537 }, { MODRM_SPLITRM, 2539 }, { MODRM_SPLITRM, 2541 }, { MODRM_SPLITRM, 2543 }, { MODRM_SPLITRM, 2545 }, { MODRM_SPLITRM, 2547 }, { MODRM_SPLITRM, 2549 }, { MODRM_SPLITRM, 2551 }, { MODRM_SPLITRM, 2553 }, { MODRM_SPLITRM, 2555 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 1750 }, { MODRM_SPLITMISC, 2558 }, { MODRM_SPLITRM, 1838 }, { MODRM_SPLITRM, 1840 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1865 }, { MODRM_SPLITRM, 1867 }, { MODRM_SPLITRM, 1869 }, { MODRM_SPLITRM, 1871 }, { MODRM_SPLITRM, 1873 }, { MODRM_SPLITRM, 1875 }, { MODRM_SPLITRM, 1877 }, { MODRM_SPLITRM, 1879 }, { MODRM_SPLITREG, 1881 }, { MODRM_SPLITRM, 1897 }, { MODRM_SPLITRM, 1899 }, { MODRM_SPLITRM, 1901 }, { MODRM_SPLITREG, 1903 }, { MODRM_SPLITRM, 1919 }, { MODRM_SPLITRM, 1921 }, { MODRM_SPLITRM, 1923 }, { MODRM_SPLITRM, 2630 }, { MODRM_SPLITRM, 2632 }, { MODRM_SPLITRM, 2634 }, { MODRM_SPLITRM, 2636 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1933 }, { MODRM_SPLITRM, 1935 }, { MODRM_SPLITRM, 1937 }, { MODRM_SPLITRM, 1939 }, { MODRM_SPLITRM, 1941 }, { MODRM_SPLITRM, 1943 }, { MODRM_SPLITRM, 1945 }, { MODRM_SPLITRM, 1947 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1956 }, { MODRM_SPLITRM, 1958 }, { MODRM_SPLITRM, 1960 }, { MODRM_SPLITRM, 1962 }, { MODRM_SPLITRM, 1964 }, { MODRM_SPLITRM, 1966 }, { MODRM_SPLITRM, 1968 }, { MODRM_SPLITRM, 1970 }, { MODRM_SPLITRM, 1972 }, { MODRM_SPLITRM, 1974 }, { MODRM_SPLITRM, 1976 }, { MODRM_SPLITRM, 1978 }, { MODRM_SPLITRM, 1980 }, { MODRM_SPLITRM, 1982 }, { MODRM_SPLITRM, 1984 }, { MODRM_SPLITRM, 1986 }, { MODRM_SPLITRM, 1988 }, { MODRM_SPLITRM, 1990 }, { MODRM_SPLITRM, 1992 }, { MODRM_SPLITRM, 1994 }, { MODRM_SPLITRM, 1996 }, { MODRM_SPLITRM, 1998 }, { MODRM_SPLITRM, 2000 }, { MODRM_SPLITRM, 2002 }, { MODRM_SPLITRM, 2004 }, { MODRM_SPLITRM, 2006 }, { MODRM_SPLITRM, 2008 }, { MODRM_SPLITRM, 2010 }, { MODRM_SPLITRM, 2012 }, { MODRM_SPLITRM, 2014 }, { MODRM_SPLITRM, 2016 }, { MODRM_SPLITRM, 2018 }, { MODRM_SPLITRM, 2020 }, { MODRM_SPLITRM, 2022 }, { MODRM_SPLITRM, 2024 }, { MODRM_SPLITRM, 2026 }, { MODRM_SPLITRM, 2028 }, { MODRM_SPLITRM, 2030 }, { MODRM_SPLITRM, 2032 }, { MODRM_SPLITRM, 2034 }, { MODRM_SPLITRM, 2036 }, { MODRM_SPLITRM, 2038 }, { MODRM_SPLITRM, 2040 }, { MODRM_SPLITRM, 2042 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2044 }, { MODRM_SPLITRM, 2046 }, { MODRM_SPLITRM, 2048 }, { MODRM_SPLITREG, 2050 }, { MODRM_SPLITREG, 2066 }, { MODRM_SPLITREG, 2082 }, { MODRM_SPLITRM, 2098 }, { MODRM_SPLITRM, 2100 }, { MODRM_SPLITRM, 2102 }, { MODRM_ONEENTRY, 2104 }, { MODRM_SPLITRM, 2638 }, { MODRM_SPLITRM, 2640 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2109 }, { MODRM_SPLITRM, 2111 }, { MODRM_ONEENTRY, 2113 }, { MODRM_ONEENTRY, 2114 }, { MODRM_ONEENTRY, 2115 }, { MODRM_ONEENTRY, 2116 }, { MODRM_ONEENTRY, 2117 }, { MODRM_ONEENTRY, 2118 }, { MODRM_ONEENTRY, 2119 }, { MODRM_ONEENTRY, 2120 }, { MODRM_ONEENTRY, 2121 }, { MODRM_ONEENTRY, 2122 }, { MODRM_ONEENTRY, 2123 }, { MODRM_ONEENTRY, 2124 }, { MODRM_ONEENTRY, 2125 }, { MODRM_ONEENTRY, 2126 }, { MODRM_ONEENTRY, 2127 }, { MODRM_ONEENTRY, 2128 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2642 }, { MODRM_ONEENTRY, 2643 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2164 }, { MODRM_SPLITRM, 2166 }, { MODRM_SPLITRM, 2168 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2644 }, { MODRM_ONEENTRY, 2645 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2317 }, { MODRM_SPLITRM, 2319 }, { MODRM_SPLITRM, 2321 }, { MODRM_SPLITMISC, 2323 }, { MODRM_SPLITRM, 2395 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 2399 }, { MODRM_SPLITRM, 2401 }, { MODRM_SPLITRM, 2403 }, { MODRM_SPLITRM, 2405 }, { MODRM_SPLITRM, 2407 }, { MODRM_SPLITRM, 2409 }, { MODRM_SPLITRM, 2411 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 2414 }, { MODRM_SPLITRM, 2430 }, { MODRM_SPLITRM, 2432 }, { MODRM_SPLITRM, 2434 }, { MODRM_SPLITRM, 2436 }, { MODRM_SPLITRM, 2438 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 2442 }, { MODRM_SPLITRM, 2444 }, { MODRM_SPLITRM, 2446 }, { MODRM_SPLITRM, 2448 }, { MODRM_SPLITRM, 2450 }, { MODRM_SPLITRM, 2452 }, { MODRM_SPLITREG, 2454 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2471 }, { MODRM_SPLITRM, 2473 }, { MODRM_SPLITRM, 2475 }, { MODRM_SPLITRM, 2477 }, { MODRM_SPLITRM, 2479 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2481 }, { MODRM_SPLITRM, 2483 }, { MODRM_SPLITRM, 2485 }, { MODRM_SPLITRM, 2487 }, { MODRM_SPLITRM, 2489 }, { MODRM_SPLITRM, 2491 }, { MODRM_SPLITRM, 2493 }, { MODRM_SPLITRM, 2495 }, { MODRM_SPLITRM, 2497 }, { MODRM_SPLITRM, 2499 }, { MODRM_SPLITRM, 2501 }, { MODRM_SPLITRM, 2503 }, { MODRM_SPLITRM, 2505 }, { MODRM_SPLITRM, 2507 }, { MODRM_SPLITRM, 2509 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2511 }, { MODRM_SPLITRM, 2513 }, { MODRM_SPLITRM, 2515 }, { MODRM_SPLITRM, 2517 }, { MODRM_SPLITRM, 2519 }, { MODRM_SPLITRM, 2521 }, { MODRM_SPLITRM, 2523 }, { MODRM_SPLITRM, 2525 }, { MODRM_SPLITRM, 2527 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2529 }, { MODRM_SPLITRM, 2531 }, { MODRM_SPLITRM, 2533 }, { MODRM_SPLITRM, 2535 }, { MODRM_SPLITRM, 2537 }, { MODRM_SPLITRM, 2539 }, { MODRM_SPLITRM, 2646 }, { MODRM_SPLITRM, 2543 }, { MODRM_SPLITRM, 2545 }, { MODRM_SPLITRM, 2547 }, { MODRM_SPLITRM, 2549 }, { MODRM_SPLITRM, 2551 }, { MODRM_SPLITRM, 2553 }, { MODRM_SPLITRM, 2555 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 2648 }, { MODRM_SPLITMISC, 2664 }, { MODRM_SPLITRM, 2736 }, { MODRM_SPLITRM, 2738 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2740 }, { MODRM_SPLITRM, 2742 }, { MODRM_SPLITRM, 2744 }, { MODRM_SPLITRM, 2746 }, { MODRM_SPLITRM, 2748 }, { MODRM_SPLITRM, 2750 }, { MODRM_SPLITRM, 2752 }, { MODRM_SPLITRM, 2754 }, { MODRM_SPLITREG, 2756 }, { MODRM_SPLITRM, 2772 }, { MODRM_SPLITRM, 2774 }, { MODRM_SPLITRM, 2776 }, { MODRM_SPLITRM, 2778 }, { MODRM_SPLITRM, 2780 }, { MODRM_SPLITRM, 2782 }, { MODRM_SPLITRM, 2784 }, { MODRM_SPLITRM, 1925 }, { MODRM_SPLITRM, 1927 }, { MODRM_SPLITRM, 1929 }, { MODRM_SPLITRM, 1931 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2786 }, { MODRM_SPLITRM, 2788 }, { MODRM_SPLITRM, 2790 }, { MODRM_SPLITRM, 2792 }, { MODRM_SPLITRM, 2794 }, { MODRM_SPLITRM, 2796 }, { MODRM_SPLITRM, 2798 }, { MODRM_SPLITRM, 2800 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2802 }, { MODRM_SPLITRM, 2804 }, { MODRM_SPLITRM, 2806 }, { MODRM_SPLITRM, 2808 }, { MODRM_SPLITRM, 2810 }, { MODRM_SPLITRM, 2812 }, { MODRM_SPLITRM, 2814 }, { MODRM_SPLITRM, 2816 }, { MODRM_SPLITRM, 2818 }, { MODRM_SPLITRM, 2820 }, { MODRM_SPLITRM, 2822 }, { MODRM_SPLITRM, 2824 }, { MODRM_SPLITRM, 2826 }, { MODRM_SPLITRM, 2828 }, { MODRM_SPLITRM, 2830 }, { MODRM_SPLITRM, 2832 }, { MODRM_SPLITRM, 2834 }, { MODRM_SPLITRM, 2836 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2838 }, { MODRM_SPLITRM, 2840 }, { MODRM_SPLITRM, 2842 }, { MODRM_SPLITRM, 2844 }, { MODRM_SPLITRM, 2846 }, { MODRM_SPLITRM, 2848 }, { MODRM_SPLITRM, 2850 }, { MODRM_SPLITRM, 2852 }, { MODRM_SPLITRM, 2854 }, { MODRM_SPLITRM, 2856 }, { MODRM_SPLITRM, 2858 }, { MODRM_SPLITRM, 2860 }, { MODRM_SPLITRM, 2862 }, { MODRM_SPLITRM, 2864 }, { MODRM_SPLITRM, 2866 }, { MODRM_SPLITRM, 2868 }, { MODRM_SPLITRM, 2870 }, { MODRM_SPLITRM, 2872 }, { MODRM_SPLITRM, 2874 }, { MODRM_SPLITRM, 2876 }, { MODRM_SPLITRM, 2878 }, { MODRM_SPLITRM, 2880 }, { MODRM_SPLITRM, 2882 }, { MODRM_SPLITRM, 2884 }, { MODRM_SPLITRM, 2886 }, { MODRM_SPLITRM, 2888 }, { MODRM_SPLITRM, 2890 }, { MODRM_SPLITRM, 2892 }, { MODRM_SPLITRM, 2894 }, { MODRM_SPLITREG, 2896 }, { MODRM_SPLITREG, 2912 }, { MODRM_SPLITREG, 2928 }, { MODRM_SPLITRM, 2944 }, { MODRM_SPLITRM, 2946 }, { MODRM_SPLITRM, 2948 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2950 }, { MODRM_SPLITRM, 2952 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2954 }, { MODRM_SPLITRM, 2956 }, { MODRM_SPLITRM, 2958 }, { MODRM_SPLITRM, 2960 }, { MODRM_ONEENTRY, 2962 }, { MODRM_ONEENTRY, 2963 }, { MODRM_ONEENTRY, 2964 }, { MODRM_ONEENTRY, 2965 }, { MODRM_ONEENTRY, 2966 }, { MODRM_ONEENTRY, 2967 }, { MODRM_ONEENTRY, 2968 }, { MODRM_ONEENTRY, 2969 }, { MODRM_ONEENTRY, 2970 }, { MODRM_ONEENTRY, 2971 }, { MODRM_ONEENTRY, 2972 }, { MODRM_ONEENTRY, 2973 }, { MODRM_ONEENTRY, 2974 }, { MODRM_ONEENTRY, 2975 }, { MODRM_ONEENTRY, 2976 }, { MODRM_ONEENTRY, 2977 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2978 }, { MODRM_ONEENTRY, 2979 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2980 }, { MODRM_SPLITRM, 2982 }, { MODRM_SPLITRM, 2984 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2986 }, { MODRM_ONEENTRY, 2987 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2988 }, { MODRM_SPLITRM, 2990 }, { MODRM_SPLITRM, 2992 }, { MODRM_SPLITREG, 2994 }, { MODRM_SPLITRM, 3010 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 3012 }, { MODRM_SPLITRM, 3014 }, { MODRM_SPLITRM, 3016 }, { MODRM_SPLITRM, 3018 }, { MODRM_SPLITRM, 3020 }, { MODRM_SPLITRM, 3022 }, { MODRM_SPLITRM, 3024 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 3026 }, { MODRM_SPLITRM, 3042 }, { MODRM_SPLITRM, 3044 }, { MODRM_SPLITRM, 3046 }, { MODRM_SPLITRM, 3048 }, { MODRM_SPLITRM, 3050 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 3052 }, { MODRM_SPLITRM, 3054 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3056 }, { MODRM_SPLITRM, 3058 }, { MODRM_SPLITRM, 3060 }, { MODRM_SPLITREG, 3062 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_SPLITRM, 3079 }, { MODRM_SPLITRM, 3081 }, { MODRM_SPLITRM, 3083 }, { MODRM_SPLITRM, 3085 }, { MODRM_SPLITRM, 3087 }, { MODRM_SPLITRM, 3089 }, { MODRM_SPLITRM, 3091 }, { MODRM_SPLITRM, 3093 }, { MODRM_SPLITRM, 3095 }, { MODRM_SPLITRM, 3097 }, { MODRM_SPLITRM, 3099 }, { MODRM_SPLITRM, 3101 }, { MODRM_SPLITRM, 3103 }, { MODRM_SPLITRM, 3105 }, { MODRM_SPLITRM, 3107 }, { MODRM_SPLITRM, 3109 }, { MODRM_SPLITRM, 3111 }, { MODRM_SPLITRM, 3113 }, { MODRM_SPLITRM, 3115 }, { MODRM_SPLITRM, 3117 }, { MODRM_SPLITRM, 3119 }, { MODRM_SPLITRM, 3121 }, { MODRM_SPLITRM, 3123 }, { MODRM_SPLITRM, 3125 }, { MODRM_SPLITRM, 3127 }, { MODRM_SPLITRM, 3129 }, { MODRM_SPLITRM, 3131 }, { MODRM_SPLITRM, 3133 }, { MODRM_SPLITRM, 3135 }, { MODRM_SPLITRM, 3137 }, { MODRM_SPLITRM, 3139 }, { MODRM_SPLITRM, 3141 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3143 }, { MODRM_SPLITRM, 3145 }, { MODRM_SPLITRM, 3147 }, { MODRM_SPLITRM, 3149 }, { MODRM_SPLITRM, 3151 }, { MODRM_SPLITRM, 3153 }, { MODRM_SPLITRM, 3155 }, { MODRM_SPLITRM, 3157 }, { MODRM_SPLITRM, 3159 }, { MODRM_SPLITRM, 3161 }, { MODRM_SPLITRM, 3163 }, { MODRM_SPLITRM, 3165 }, { MODRM_SPLITRM, 3167 }, { MODRM_SPLITRM, 3169 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 1750 }, { MODRM_SPLITMISC, 1766 }, { MODRM_SPLITRM, 1838 }, { MODRM_SPLITRM, 1840 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1865 }, { MODRM_SPLITRM, 1867 }, { MODRM_SPLITRM, 1869 }, { MODRM_SPLITRM, 1871 }, { MODRM_SPLITRM, 1873 }, { MODRM_SPLITRM, 1875 }, { MODRM_SPLITRM, 1877 }, { MODRM_SPLITRM, 1879 }, { MODRM_SPLITREG, 1881 }, { MODRM_SPLITRM, 1897 }, { MODRM_SPLITRM, 1899 }, { MODRM_SPLITRM, 1901 }, { MODRM_SPLITREG, 1903 }, { MODRM_SPLITRM, 1919 }, { MODRM_SPLITRM, 1921 }, { MODRM_SPLITRM, 1923 }, { MODRM_SPLITRM, 1925 }, { MODRM_SPLITRM, 1927 }, { MODRM_SPLITRM, 1929 }, { MODRM_SPLITRM, 1931 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1933 }, { MODRM_SPLITRM, 1935 }, { MODRM_SPLITRM, 1937 }, { MODRM_SPLITRM, 1939 }, { MODRM_SPLITRM, 1941 }, { MODRM_SPLITRM, 1943 }, { MODRM_SPLITRM, 1945 }, { MODRM_SPLITRM, 1947 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1956 }, { MODRM_SPLITRM, 1958 }, { MODRM_SPLITRM, 1960 }, { MODRM_SPLITRM, 1962 }, { MODRM_SPLITRM, 1964 }, { MODRM_SPLITRM, 1966 }, { MODRM_SPLITRM, 1968 }, { MODRM_SPLITRM, 1970 }, { MODRM_SPLITRM, 1972 }, { MODRM_SPLITRM, 1974 }, { MODRM_SPLITRM, 1976 }, { MODRM_SPLITRM, 1978 }, { MODRM_SPLITRM, 1980 }, { MODRM_SPLITRM, 1982 }, { MODRM_SPLITRM, 1984 }, { MODRM_SPLITRM, 1986 }, { MODRM_SPLITRM, 1988 }, { MODRM_SPLITRM, 1990 }, { MODRM_SPLITRM, 1992 }, { MODRM_SPLITRM, 1994 }, { MODRM_SPLITRM, 1996 }, { MODRM_SPLITRM, 1998 }, { MODRM_SPLITRM, 2000 }, { MODRM_SPLITRM, 2002 }, { MODRM_SPLITRM, 2004 }, { MODRM_SPLITRM, 2006 }, { MODRM_SPLITRM, 2008 }, { MODRM_SPLITRM, 2010 }, { MODRM_SPLITRM, 2012 }, { MODRM_SPLITRM, 2014 }, { MODRM_SPLITRM, 2016 }, { MODRM_SPLITRM, 2018 }, { MODRM_SPLITRM, 2020 }, { MODRM_SPLITRM, 2022 }, { MODRM_SPLITRM, 2024 }, { MODRM_SPLITRM, 2026 }, { MODRM_SPLITRM, 2028 }, { MODRM_SPLITRM, 2030 }, { MODRM_SPLITRM, 2032 }, { MODRM_SPLITRM, 2034 }, { MODRM_SPLITRM, 2036 }, { MODRM_SPLITRM, 2038 }, { MODRM_SPLITRM, 2040 }, { MODRM_SPLITRM, 2042 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2044 }, { MODRM_SPLITRM, 2046 }, { MODRM_SPLITRM, 2048 }, { MODRM_SPLITREG, 2050 }, { MODRM_SPLITREG, 2066 }, { MODRM_SPLITREG, 2082 }, { MODRM_SPLITRM, 2098 }, { MODRM_SPLITRM, 2100 }, { MODRM_SPLITRM, 2102 }, { MODRM_ONEENTRY, 2104 }, { MODRM_SPLITRM, 2105 }, { MODRM_SPLITRM, 2107 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2109 }, { MODRM_SPLITRM, 2111 }, { MODRM_ONEENTRY, 2113 }, { MODRM_ONEENTRY, 2114 }, { MODRM_ONEENTRY, 2115 }, { MODRM_ONEENTRY, 2116 }, { MODRM_ONEENTRY, 2117 }, { MODRM_ONEENTRY, 2118 }, { MODRM_ONEENTRY, 2119 }, { MODRM_ONEENTRY, 2120 }, { MODRM_ONEENTRY, 2121 }, { MODRM_ONEENTRY, 2122 }, { MODRM_ONEENTRY, 2123 }, { MODRM_ONEENTRY, 2124 }, { MODRM_ONEENTRY, 2125 }, { MODRM_ONEENTRY, 2126 }, { MODRM_ONEENTRY, 2127 }, { MODRM_ONEENTRY, 2128 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2161 }, { MODRM_ONEENTRY, 2162 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2164 }, { MODRM_SPLITRM, 2166 }, { MODRM_SPLITRM, 2168 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2314 }, { MODRM_ONEENTRY, 2315 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2317 }, { MODRM_SPLITRM, 2319 }, { MODRM_SPLITRM, 2321 }, { MODRM_SPLITMISC, 2323 }, { MODRM_SPLITRM, 2395 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 2399 }, { MODRM_SPLITRM, 2401 }, { MODRM_SPLITRM, 2403 }, { MODRM_SPLITRM, 2405 }, { MODRM_SPLITRM, 2407 }, { MODRM_SPLITRM, 2409 }, { MODRM_SPLITRM, 2411 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 2414 }, { MODRM_SPLITRM, 2430 }, { MODRM_SPLITRM, 2432 }, { MODRM_SPLITRM, 2434 }, { MODRM_SPLITRM, 2436 }, { MODRM_SPLITRM, 2438 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 2442 }, { MODRM_SPLITRM, 2444 }, { MODRM_SPLITRM, 2446 }, { MODRM_SPLITRM, 2448 }, { MODRM_SPLITRM, 2450 }, { MODRM_SPLITRM, 2452 }, { MODRM_SPLITREG, 2454 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2471 }, { MODRM_SPLITRM, 2473 }, { MODRM_SPLITRM, 2475 }, { MODRM_SPLITRM, 2477 }, { MODRM_SPLITRM, 2479 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2481 }, { MODRM_SPLITRM, 2483 }, { MODRM_SPLITRM, 2485 }, { MODRM_SPLITRM, 2487 }, { MODRM_SPLITRM, 2489 }, { MODRM_SPLITRM, 2491 }, { MODRM_SPLITRM, 2493 }, { MODRM_SPLITRM, 2495 }, { MODRM_SPLITRM, 2497 }, { MODRM_SPLITRM, 2499 }, { MODRM_SPLITRM, 2501 }, { MODRM_SPLITRM, 2503 }, { MODRM_SPLITRM, 2505 }, { MODRM_SPLITRM, 2507 }, { MODRM_SPLITRM, 2509 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2511 }, { MODRM_SPLITRM, 2513 }, { MODRM_SPLITRM, 2515 }, { MODRM_SPLITRM, 2517 }, { MODRM_SPLITRM, 2519 }, { MODRM_SPLITRM, 2521 }, { MODRM_SPLITRM, 2523 }, { MODRM_SPLITRM, 2525 }, { MODRM_SPLITRM, 2527 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2529 }, { MODRM_SPLITRM, 2531 }, { MODRM_SPLITRM, 2533 }, { MODRM_SPLITRM, 2535 }, { MODRM_SPLITRM, 2537 }, { MODRM_SPLITRM, 2539 }, { MODRM_SPLITRM, 2541 }, { MODRM_SPLITRM, 2543 }, { MODRM_SPLITRM, 2545 }, { MODRM_SPLITRM, 2547 }, { MODRM_SPLITRM, 2549 }, { MODRM_SPLITRM, 2551 }, { MODRM_SPLITRM, 2553 }, { MODRM_SPLITRM, 2555 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 2648 }, { MODRM_SPLITMISC, 2664 }, { MODRM_SPLITRM, 2736 }, { MODRM_SPLITRM, 2738 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2740 }, { MODRM_SPLITRM, 2742 }, { MODRM_SPLITRM, 3171 }, { MODRM_SPLITRM, 2746 }, { MODRM_SPLITRM, 2748 }, { MODRM_SPLITRM, 2750 }, { MODRM_SPLITRM, 3173 }, { MODRM_SPLITRM, 2754 }, { MODRM_SPLITREG, 2756 }, { MODRM_SPLITRM, 2772 }, { MODRM_SPLITRM, 2774 }, { MODRM_SPLITRM, 2776 }, { MODRM_SPLITRM, 2778 }, { MODRM_SPLITRM, 2780 }, { MODRM_SPLITRM, 2782 }, { MODRM_SPLITRM, 2784 }, { MODRM_SPLITRM, 1925 }, { MODRM_SPLITRM, 1927 }, { MODRM_SPLITRM, 1929 }, { MODRM_SPLITRM, 1931 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2786 }, { MODRM_SPLITRM, 2788 }, { MODRM_SPLITRM, 2790 }, { MODRM_SPLITRM, 2792 }, { MODRM_SPLITRM, 2794 }, { MODRM_SPLITRM, 2796 }, { MODRM_SPLITRM, 2798 }, { MODRM_SPLITRM, 2800 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2802 }, { MODRM_SPLITRM, 2804 }, { MODRM_SPLITRM, 2806 }, { MODRM_SPLITRM, 2808 }, { MODRM_SPLITRM, 2810 }, { MODRM_SPLITRM, 2812 }, { MODRM_SPLITRM, 2814 }, { MODRM_SPLITRM, 2816 }, { MODRM_SPLITRM, 2818 }, { MODRM_SPLITRM, 2820 }, { MODRM_SPLITRM, 2822 }, { MODRM_SPLITRM, 2824 }, { MODRM_SPLITRM, 2826 }, { MODRM_SPLITRM, 2828 }, { MODRM_SPLITRM, 2830 }, { MODRM_SPLITRM, 2832 }, { MODRM_SPLITRM, 2834 }, { MODRM_SPLITRM, 2836 }, { MODRM_SPLITRM, 1992 }, { MODRM_SPLITRM, 1994 }, { MODRM_SPLITRM, 2838 }, { MODRM_SPLITRM, 2840 }, { MODRM_SPLITRM, 2842 }, { MODRM_SPLITRM, 2844 }, { MODRM_SPLITRM, 2846 }, { MODRM_SPLITRM, 2848 }, { MODRM_SPLITRM, 2850 }, { MODRM_SPLITRM, 2852 }, { MODRM_SPLITRM, 2854 }, { MODRM_SPLITRM, 2856 }, { MODRM_SPLITRM, 2858 }, { MODRM_SPLITRM, 2860 }, { MODRM_SPLITRM, 2862 }, { MODRM_SPLITRM, 2864 }, { MODRM_SPLITRM, 2866 }, { MODRM_SPLITRM, 2868 }, { MODRM_SPLITRM, 2870 }, { MODRM_SPLITRM, 2872 }, { MODRM_SPLITRM, 2874 }, { MODRM_SPLITRM, 2876 }, { MODRM_SPLITRM, 2878 }, { MODRM_SPLITRM, 2880 }, { MODRM_SPLITRM, 2882 }, { MODRM_SPLITRM, 2884 }, { MODRM_SPLITRM, 2886 }, { MODRM_SPLITRM, 2888 }, { MODRM_SPLITRM, 2890 }, { MODRM_SPLITRM, 2892 }, { MODRM_SPLITRM, 2894 }, { MODRM_SPLITREG, 2896 }, { MODRM_SPLITREG, 2912 }, { MODRM_SPLITREG, 2928 }, { MODRM_SPLITRM, 2944 }, { MODRM_SPLITRM, 2946 }, { MODRM_SPLITRM, 2948 }, { MODRM_ONEENTRY, 2104 }, { MODRM_SPLITRM, 3175 }, { MODRM_SPLITRM, 3177 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2954 }, { MODRM_SPLITRM, 2956 }, { MODRM_SPLITRM, 2958 }, { MODRM_SPLITRM, 2960 }, { MODRM_ONEENTRY, 2962 }, { MODRM_ONEENTRY, 2963 }, { MODRM_ONEENTRY, 2964 }, { MODRM_ONEENTRY, 2965 }, { MODRM_ONEENTRY, 2966 }, { MODRM_ONEENTRY, 2967 }, { MODRM_ONEENTRY, 2968 }, { MODRM_ONEENTRY, 2969 }, { MODRM_ONEENTRY, 2970 }, { MODRM_ONEENTRY, 2971 }, { MODRM_ONEENTRY, 2972 }, { MODRM_ONEENTRY, 2973 }, { MODRM_ONEENTRY, 2974 }, { MODRM_ONEENTRY, 2975 }, { MODRM_ONEENTRY, 2976 }, { MODRM_ONEENTRY, 2977 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2978 }, { MODRM_ONEENTRY, 2979 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2980 }, { MODRM_SPLITRM, 2982 }, { MODRM_SPLITRM, 2984 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2986 }, { MODRM_ONEENTRY, 2987 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2988 }, { MODRM_SPLITRM, 2990 }, { MODRM_SPLITRM, 2992 }, { MODRM_SPLITMISC, 3179 }, { MODRM_SPLITRM, 3010 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 3012 }, { MODRM_SPLITRM, 3014 }, { MODRM_SPLITRM, 3016 }, { MODRM_SPLITRM, 3018 }, { MODRM_SPLITRM, 3020 }, { MODRM_SPLITRM, 3022 }, { MODRM_SPLITRM, 3024 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 3026 }, { MODRM_SPLITRM, 3042 }, { MODRM_SPLITRM, 3044 }, { MODRM_SPLITRM, 3046 }, { MODRM_SPLITRM, 3048 }, { MODRM_SPLITRM, 3050 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 3052 }, { MODRM_SPLITRM, 3054 }, { MODRM_SPLITRM, 2446 }, { MODRM_SPLITRM, 3056 }, { MODRM_SPLITRM, 3058 }, { MODRM_SPLITRM, 3060 }, { MODRM_SPLITREG, 3251 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_SPLITRM, 3079 }, { MODRM_SPLITRM, 3081 }, { MODRM_SPLITRM, 3083 }, { MODRM_SPLITRM, 3085 }, { MODRM_SPLITRM, 3087 }, { MODRM_SPLITRM, 3089 }, { MODRM_SPLITRM, 3091 }, { MODRM_SPLITRM, 3093 }, { MODRM_SPLITRM, 3095 }, { MODRM_SPLITRM, 3097 }, { MODRM_SPLITRM, 3099 }, { MODRM_SPLITRM, 3101 }, { MODRM_SPLITRM, 3103 }, { MODRM_SPLITRM, 3105 }, { MODRM_SPLITRM, 3107 }, { MODRM_SPLITRM, 3109 }, { MODRM_SPLITRM, 3111 }, { MODRM_SPLITRM, 3113 }, { MODRM_SPLITRM, 3115 }, { MODRM_SPLITRM, 3117 }, { MODRM_SPLITRM, 3119 }, { MODRM_SPLITRM, 3121 }, { MODRM_SPLITRM, 3123 }, { MODRM_SPLITRM, 3125 }, { MODRM_SPLITRM, 3127 }, { MODRM_SPLITRM, 3129 }, { MODRM_SPLITRM, 3131 }, { MODRM_SPLITRM, 3133 }, { MODRM_SPLITRM, 3135 }, { MODRM_SPLITRM, 3137 }, { MODRM_SPLITRM, 3139 }, { MODRM_SPLITRM, 3141 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3143 }, { MODRM_SPLITRM, 3145 }, { MODRM_SPLITRM, 3147 }, { MODRM_SPLITRM, 3149 }, { MODRM_SPLITRM, 3151 }, { MODRM_SPLITRM, 3153 }, { MODRM_SPLITRM, 3155 }, { MODRM_SPLITRM, 3157 }, { MODRM_SPLITRM, 3159 }, { MODRM_SPLITRM, 3161 }, { MODRM_SPLITRM, 3163 }, { MODRM_SPLITRM, 3165 }, { MODRM_SPLITRM, 3167 }, { MODRM_SPLITRM, 3169 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 1750 }, { MODRM_SPLITMISC, 1766 }, { MODRM_SPLITRM, 1838 }, { MODRM_SPLITRM, 1840 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3267 }, { MODRM_SPLITRM, 3269 }, { MODRM_SPLITRM, 3271 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1881 }, { MODRM_SPLITRM, 1897 }, { MODRM_SPLITRM, 3273 }, { MODRM_SPLITRM, 3275 }, { MODRM_SPLITREG, 1903 }, { MODRM_SPLITRM, 1919 }, { MODRM_SPLITRM, 1921 }, { MODRM_SPLITRM, 1923 }, { MODRM_SPLITRM, 1925 }, { MODRM_SPLITRM, 1927 }, { MODRM_SPLITRM, 1929 }, { MODRM_SPLITRM, 1931 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3277 }, { MODRM_SPLITRM, 3279 }, { MODRM_SPLITRM, 3281 }, { MODRM_SPLITRM, 3283 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1956 }, { MODRM_SPLITRM, 1958 }, { MODRM_SPLITRM, 1960 }, { MODRM_SPLITRM, 1962 }, { MODRM_SPLITRM, 1964 }, { MODRM_SPLITRM, 1966 }, { MODRM_SPLITRM, 1968 }, { MODRM_SPLITRM, 1970 }, { MODRM_SPLITRM, 1972 }, { MODRM_SPLITRM, 1974 }, { MODRM_SPLITRM, 1976 }, { MODRM_SPLITRM, 1978 }, { MODRM_SPLITRM, 1980 }, { MODRM_SPLITRM, 1982 }, { MODRM_SPLITRM, 1984 }, { MODRM_SPLITRM, 1986 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3285 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3287 }, { MODRM_SPLITRM, 3289 }, { MODRM_SPLITRM, 3291 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3293 }, { MODRM_SPLITRM, 3295 }, { MODRM_SPLITRM, 3297 }, { MODRM_SPLITRM, 3299 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3301 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2802 }, { MODRM_SPLITRM, 2804 }, { MODRM_SPLITRM, 2806 }, { MODRM_SPLITRM, 2808 }, { MODRM_SPLITRM, 2810 }, { MODRM_SPLITRM, 2812 }, { MODRM_SPLITRM, 2814 }, { MODRM_SPLITRM, 2816 }, { MODRM_SPLITRM, 2818 }, { MODRM_SPLITRM, 2820 }, { MODRM_SPLITRM, 2822 }, { MODRM_SPLITRM, 2824 }, { MODRM_SPLITRM, 2826 }, { MODRM_SPLITRM, 2828 }, { MODRM_SPLITRM, 2830 }, { MODRM_SPLITRM, 2832 }, { MODRM_SPLITRM, 2834 }, { MODRM_SPLITRM, 2836 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2838 }, { MODRM_SPLITRM, 2840 }, { MODRM_SPLITRM, 2842 }, { MODRM_SPLITRM, 2844 }, { MODRM_SPLITRM, 2846 }, { MODRM_SPLITRM, 2848 }, { MODRM_SPLITRM, 2850 }, { MODRM_SPLITRM, 2852 }, { MODRM_SPLITRM, 2854 }, { MODRM_SPLITRM, 2856 }, { MODRM_SPLITRM, 2858 }, { MODRM_SPLITRM, 2860 }, { MODRM_SPLITRM, 2862 }, { MODRM_SPLITRM, 2864 }, { MODRM_SPLITRM, 2866 }, { MODRM_SPLITRM, 2868 }, { MODRM_SPLITRM, 2870 }, { MODRM_SPLITRM, 2872 }, { MODRM_SPLITRM, 2874 }, { MODRM_SPLITRM, 2876 }, { MODRM_SPLITRM, 2878 }, { MODRM_SPLITRM, 2880 }, { MODRM_SPLITRM, 2882 }, { MODRM_SPLITRM, 2884 }, { MODRM_SPLITRM, 2886 }, { MODRM_SPLITRM, 2888 }, { MODRM_SPLITRM, 2890 }, { MODRM_SPLITRM, 2892 }, { MODRM_SPLITRM, 2894 }, { MODRM_SPLITREG, 2896 }, { MODRM_SPLITREG, 2912 }, { MODRM_SPLITREG, 2928 }, { MODRM_SPLITRM, 2944 }, { MODRM_SPLITRM, 2946 }, { MODRM_SPLITRM, 2948 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2950 }, { MODRM_SPLITRM, 2952 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2954 }, { MODRM_SPLITRM, 2956 }, { MODRM_SPLITRM, 2958 }, { MODRM_SPLITRM, 2960 }, { MODRM_ONEENTRY, 2962 }, { MODRM_ONEENTRY, 2963 }, { MODRM_ONEENTRY, 2964 }, { MODRM_ONEENTRY, 2965 }, { MODRM_ONEENTRY, 2966 }, { MODRM_ONEENTRY, 2967 }, { MODRM_ONEENTRY, 2968 }, { MODRM_ONEENTRY, 2969 }, { MODRM_ONEENTRY, 2970 }, { MODRM_ONEENTRY, 2971 }, { MODRM_ONEENTRY, 2972 }, { MODRM_ONEENTRY, 2973 }, { MODRM_ONEENTRY, 2974 }, { MODRM_ONEENTRY, 2975 }, { MODRM_ONEENTRY, 2976 }, { MODRM_ONEENTRY, 2977 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2978 }, { MODRM_ONEENTRY, 2979 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2980 }, { MODRM_SPLITRM, 2982 }, { MODRM_SPLITRM, 2984 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2986 }, { MODRM_ONEENTRY, 2987 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2988 }, { MODRM_SPLITRM, 2990 }, { MODRM_SPLITRM, 2992 }, { MODRM_SPLITREG, 2994 }, { MODRM_SPLITRM, 3010 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 3012 }, { MODRM_SPLITRM, 3014 }, { MODRM_SPLITRM, 3016 }, { MODRM_SPLITRM, 3018 }, { MODRM_SPLITRM, 3020 }, { MODRM_SPLITRM, 3022 }, { MODRM_SPLITRM, 3024 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 3026 }, { MODRM_SPLITRM, 3042 }, { MODRM_SPLITRM, 3044 }, { MODRM_SPLITRM, 3046 }, { MODRM_SPLITRM, 3048 }, { MODRM_SPLITRM, 3050 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 3052 }, { MODRM_SPLITRM, 3054 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3056 }, { MODRM_SPLITRM, 3058 }, { MODRM_SPLITRM, 3060 }, { MODRM_SPLITREG, 3062 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_ONEENTRY, 3078 }, { MODRM_SPLITRM, 3079 }, { MODRM_SPLITRM, 3081 }, { MODRM_SPLITRM, 3083 }, { MODRM_SPLITRM, 3085 }, { MODRM_SPLITRM, 3087 }, { MODRM_SPLITRM, 3089 }, { MODRM_SPLITRM, 3091 }, { MODRM_SPLITRM, 3093 }, { MODRM_SPLITRM, 3095 }, { MODRM_SPLITRM, 3097 }, { MODRM_SPLITRM, 3099 }, { MODRM_SPLITRM, 3101 }, { MODRM_SPLITRM, 3103 }, { MODRM_SPLITRM, 3105 }, { MODRM_SPLITRM, 3107 }, { MODRM_SPLITRM, 3109 }, { MODRM_SPLITRM, 3111 }, { MODRM_SPLITRM, 3113 }, { MODRM_SPLITRM, 3115 }, { MODRM_SPLITRM, 3117 }, { MODRM_SPLITRM, 3119 }, { MODRM_SPLITRM, 3121 }, { MODRM_SPLITRM, 3123 }, { MODRM_SPLITRM, 3125 }, { MODRM_SPLITRM, 3127 }, { MODRM_SPLITRM, 3129 }, { MODRM_SPLITRM, 3131 }, { MODRM_SPLITRM, 3133 }, { MODRM_SPLITRM, 3135 }, { MODRM_SPLITRM, 3137 }, { MODRM_SPLITRM, 3139 }, { MODRM_SPLITRM, 3141 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3143 }, { MODRM_SPLITRM, 3145 }, { MODRM_SPLITRM, 3147 }, { MODRM_SPLITRM, 3149 }, { MODRM_SPLITRM, 3151 }, { MODRM_SPLITRM, 3153 }, { MODRM_SPLITRM, 3989 }, { MODRM_SPLITRM, 3157 }, { MODRM_SPLITRM, 3159 }, { MODRM_SPLITRM, 3161 }, { MODRM_SPLITRM, 3163 }, { MODRM_SPLITRM, 3165 }, { MODRM_SPLITRM, 3167 }, { MODRM_SPLITRM, 3169 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 1750 }, { MODRM_SPLITMISC, 2558 }, { MODRM_SPLITRM, 1838 }, { MODRM_SPLITRM, 1840 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1865 }, { MODRM_SPLITRM, 1867 }, { MODRM_SPLITRM, 1869 }, { MODRM_SPLITRM, 1871 }, { MODRM_SPLITRM, 1873 }, { MODRM_SPLITRM, 1875 }, { MODRM_SPLITRM, 1877 }, { MODRM_SPLITRM, 1879 }, { MODRM_SPLITREG, 1881 }, { MODRM_SPLITRM, 1897 }, { MODRM_SPLITRM, 1899 }, { MODRM_SPLITRM, 1901 }, { MODRM_SPLITREG, 1903 }, { MODRM_SPLITRM, 1919 }, { MODRM_SPLITRM, 1921 }, { MODRM_SPLITRM, 1923 }, { MODRM_SPLITRM, 2630 }, { MODRM_SPLITRM, 2632 }, { MODRM_SPLITRM, 2634 }, { MODRM_SPLITRM, 2636 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1933 }, { MODRM_SPLITRM, 1935 }, { MODRM_SPLITRM, 1937 }, { MODRM_SPLITRM, 1939 }, { MODRM_SPLITRM, 1941 }, { MODRM_SPLITRM, 1943 }, { MODRM_SPLITRM, 1945 }, { MODRM_SPLITRM, 1947 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1956 }, { MODRM_SPLITRM, 1958 }, { MODRM_SPLITRM, 1960 }, { MODRM_SPLITRM, 1962 }, { MODRM_SPLITRM, 1964 }, { MODRM_SPLITRM, 1966 }, { MODRM_SPLITRM, 1968 }, { MODRM_SPLITRM, 1970 }, { MODRM_SPLITRM, 1972 }, { MODRM_SPLITRM, 1974 }, { MODRM_SPLITRM, 1976 }, { MODRM_SPLITRM, 1978 }, { MODRM_SPLITRM, 1980 }, { MODRM_SPLITRM, 1982 }, { MODRM_SPLITRM, 1984 }, { MODRM_SPLITRM, 1986 }, { MODRM_SPLITRM, 1988 }, { MODRM_SPLITRM, 1990 }, { MODRM_SPLITRM, 1992 }, { MODRM_SPLITRM, 1994 }, { MODRM_SPLITRM, 1996 }, { MODRM_SPLITRM, 1998 }, { MODRM_SPLITRM, 2000 }, { MODRM_SPLITRM, 2002 }, { MODRM_SPLITRM, 2004 }, { MODRM_SPLITRM, 2006 }, { MODRM_SPLITRM, 2008 }, { MODRM_SPLITRM, 2010 }, { MODRM_SPLITRM, 2012 }, { MODRM_SPLITRM, 2014 }, { MODRM_SPLITRM, 2016 }, { MODRM_SPLITRM, 2018 }, { MODRM_SPLITRM, 2020 }, { MODRM_SPLITRM, 2022 }, { MODRM_SPLITRM, 2024 }, { MODRM_SPLITRM, 2026 }, { MODRM_SPLITRM, 2028 }, { MODRM_SPLITRM, 2030 }, { MODRM_SPLITRM, 2032 }, { MODRM_SPLITRM, 2034 }, { MODRM_SPLITRM, 2036 }, { MODRM_SPLITRM, 2038 }, { MODRM_SPLITRM, 2040 }, { MODRM_SPLITRM, 2042 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2044 }, { MODRM_SPLITRM, 2046 }, { MODRM_SPLITRM, 2048 }, { MODRM_SPLITREG, 2050 }, { MODRM_SPLITREG, 2066 }, { MODRM_SPLITREG, 2082 }, { MODRM_SPLITRM, 2098 }, { MODRM_SPLITRM, 2100 }, { MODRM_SPLITRM, 2102 }, { MODRM_ONEENTRY, 2104 }, { MODRM_SPLITRM, 2638 }, { MODRM_SPLITRM, 2640 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2109 }, { MODRM_SPLITRM, 2111 }, { MODRM_ONEENTRY, 2113 }, { MODRM_ONEENTRY, 2114 }, { MODRM_ONEENTRY, 2115 }, { MODRM_ONEENTRY, 2116 }, { MODRM_ONEENTRY, 2117 }, { MODRM_ONEENTRY, 2118 }, { MODRM_ONEENTRY, 2119 }, { MODRM_ONEENTRY, 2120 }, { MODRM_ONEENTRY, 2121 }, { MODRM_ONEENTRY, 2122 }, { MODRM_ONEENTRY, 2123 }, { MODRM_ONEENTRY, 2124 }, { MODRM_ONEENTRY, 2125 }, { MODRM_ONEENTRY, 2126 }, { MODRM_ONEENTRY, 2127 }, { MODRM_ONEENTRY, 2128 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2642 }, { MODRM_ONEENTRY, 2643 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2164 }, { MODRM_SPLITRM, 2166 }, { MODRM_SPLITRM, 2168 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2644 }, { MODRM_ONEENTRY, 2645 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2317 }, { MODRM_SPLITRM, 2319 }, { MODRM_SPLITRM, 2321 }, { MODRM_SPLITMISC, 2323 }, { MODRM_SPLITRM, 2395 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 2399 }, { MODRM_SPLITRM, 2401 }, { MODRM_SPLITRM, 2403 }, { MODRM_SPLITRM, 2405 }, { MODRM_SPLITRM, 2407 }, { MODRM_SPLITRM, 2409 }, { MODRM_SPLITRM, 2411 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 2413 }, { MODRM_SPLITREG, 2414 }, { MODRM_SPLITRM, 2430 }, { MODRM_SPLITRM, 2432 }, { MODRM_SPLITRM, 2434 }, { MODRM_SPLITRM, 2436 }, { MODRM_SPLITRM, 2438 }, { MODRM_SPLITRM, 2440 }, { MODRM_SPLITRM, 2442 }, { MODRM_SPLITRM, 2444 }, { MODRM_SPLITRM, 2446 }, { MODRM_SPLITRM, 2448 }, { MODRM_SPLITRM, 2450 }, { MODRM_SPLITRM, 2452 }, { MODRM_SPLITREG, 2454 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 2470 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2471 }, { MODRM_SPLITRM, 2473 }, { MODRM_SPLITRM, 2475 }, { MODRM_SPLITRM, 2477 }, { MODRM_SPLITRM, 2479 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2481 }, { MODRM_SPLITRM, 2483 }, { MODRM_SPLITRM, 2485 }, { MODRM_SPLITRM, 2487 }, { MODRM_SPLITRM, 2489 }, { MODRM_SPLITRM, 2491 }, { MODRM_SPLITRM, 2493 }, { MODRM_SPLITRM, 2495 }, { MODRM_SPLITRM, 2497 }, { MODRM_SPLITRM, 2499 }, { MODRM_SPLITRM, 2501 }, { MODRM_SPLITRM, 2503 }, { MODRM_SPLITRM, 2505 }, { MODRM_SPLITRM, 2507 }, { MODRM_SPLITRM, 2509 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2511 }, { MODRM_SPLITRM, 2513 }, { MODRM_SPLITRM, 2515 }, { MODRM_SPLITRM, 2517 }, { MODRM_SPLITRM, 2519 }, { MODRM_SPLITRM, 2521 }, { MODRM_SPLITRM, 2523 }, { MODRM_SPLITRM, 2525 }, { MODRM_SPLITRM, 2527 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2529 }, { MODRM_SPLITRM, 2531 }, { MODRM_SPLITRM, 2533 }, { MODRM_SPLITRM, 2535 }, { MODRM_SPLITRM, 2537 }, { MODRM_SPLITRM, 2539 }, { MODRM_SPLITRM, 2646 }, { MODRM_SPLITRM, 2543 }, { MODRM_SPLITRM, 2545 }, { MODRM_SPLITRM, 2547 }, { MODRM_SPLITRM, 2549 }, { MODRM_SPLITRM, 2551 }, { MODRM_SPLITRM, 2553 }, { MODRM_SPLITRM, 2555 }, { MODRM_ONEENTRY, 2557 }, } }, { { { MODRM_SPLITREG, 2648 }, { MODRM_SPLITMISC, 3991 }, { MODRM_SPLITRM, 2736 }, { MODRM_SPLITRM, 2738 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1848 }, { MODRM_ONEENTRY, 1864 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2740 }, { MODRM_SPLITRM, 2742 }, { MODRM_SPLITRM, 3171 }, { MODRM_SPLITRM, 2746 }, { MODRM_SPLITRM, 2748 }, { MODRM_SPLITRM, 2750 }, { MODRM_SPLITRM, 3173 }, { MODRM_SPLITRM, 2754 }, { MODRM_SPLITREG, 2756 }, { MODRM_SPLITRM, 2772 }, { MODRM_SPLITRM, 3893 }, { MODRM_SPLITRM, 3895 }, { MODRM_SPLITRM, 2778 }, { MODRM_SPLITRM, 2780 }, { MODRM_SPLITRM, 2782 }, { MODRM_SPLITRM, 2784 }, { MODRM_SPLITRM, 2630 }, { MODRM_SPLITRM, 2632 }, { MODRM_SPLITRM, 2634 }, { MODRM_SPLITRM, 2636 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2786 }, { MODRM_SPLITRM, 2788 }, { MODRM_SPLITRM, 2790 }, { MODRM_SPLITRM, 2792 }, { MODRM_SPLITRM, 2794 }, { MODRM_SPLITRM, 2796 }, { MODRM_SPLITRM, 2798 }, { MODRM_SPLITRM, 2800 }, { MODRM_ONEENTRY, 1949 }, { MODRM_ONEENTRY, 1950 }, { MODRM_ONEENTRY, 1951 }, { MODRM_ONEENTRY, 1952 }, { MODRM_ONEENTRY, 1953 }, { MODRM_ONEENTRY, 1954 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2802 }, { MODRM_SPLITRM, 2804 }, { MODRM_SPLITRM, 2806 }, { MODRM_SPLITRM, 2808 }, { MODRM_SPLITRM, 2810 }, { MODRM_SPLITRM, 2812 }, { MODRM_SPLITRM, 2814 }, { MODRM_SPLITRM, 2816 }, { MODRM_SPLITRM, 2818 }, { MODRM_SPLITRM, 2820 }, { MODRM_SPLITRM, 2822 }, { MODRM_SPLITRM, 2824 }, { MODRM_SPLITRM, 2826 }, { MODRM_SPLITRM, 2828 }, { MODRM_SPLITRM, 2830 }, { MODRM_SPLITRM, 2832 }, { MODRM_SPLITRM, 2834 }, { MODRM_SPLITRM, 2836 }, { MODRM_SPLITRM, 1992 }, { MODRM_SPLITRM, 1994 }, { MODRM_SPLITRM, 2838 }, { MODRM_SPLITRM, 2840 }, { MODRM_SPLITRM, 2842 }, { MODRM_SPLITRM, 2844 }, { MODRM_SPLITRM, 2846 }, { MODRM_SPLITRM, 2848 }, { MODRM_SPLITRM, 2850 }, { MODRM_SPLITRM, 2852 }, { MODRM_SPLITRM, 2854 }, { MODRM_SPLITRM, 2856 }, { MODRM_SPLITRM, 2858 }, { MODRM_SPLITRM, 2860 }, { MODRM_SPLITRM, 2862 }, { MODRM_SPLITRM, 2864 }, { MODRM_SPLITRM, 2866 }, { MODRM_SPLITRM, 2868 }, { MODRM_SPLITRM, 2870 }, { MODRM_SPLITRM, 2872 }, { MODRM_SPLITRM, 2874 }, { MODRM_SPLITRM, 2876 }, { MODRM_SPLITRM, 2878 }, { MODRM_SPLITRM, 2880 }, { MODRM_SPLITRM, 2882 }, { MODRM_SPLITRM, 2884 }, { MODRM_SPLITRM, 2886 }, { MODRM_SPLITRM, 2888 }, { MODRM_SPLITRM, 2890 }, { MODRM_SPLITRM, 2892 }, { MODRM_SPLITRM, 2894 }, { MODRM_SPLITREG, 2896 }, { MODRM_SPLITREG, 2912 }, { MODRM_SPLITREG, 2928 }, { MODRM_SPLITRM, 2944 }, { MODRM_SPLITRM, 2946 }, { MODRM_SPLITRM, 2948 }, { MODRM_ONEENTRY, 2104 }, { MODRM_SPLITRM, 3897 }, { MODRM_SPLITRM, 3899 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2954 }, { MODRM_SPLITRM, 2956 }, { MODRM_SPLITRM, 2958 }, { MODRM_SPLITRM, 2960 }, { MODRM_ONEENTRY, 2962 }, { MODRM_ONEENTRY, 2963 }, { MODRM_ONEENTRY, 2964 }, { MODRM_ONEENTRY, 2965 }, { MODRM_ONEENTRY, 2966 }, { MODRM_ONEENTRY, 2967 }, { MODRM_ONEENTRY, 2968 }, { MODRM_ONEENTRY, 2969 }, { MODRM_ONEENTRY, 2970 }, { MODRM_ONEENTRY, 2971 }, { MODRM_ONEENTRY, 2972 }, { MODRM_ONEENTRY, 2973 }, { MODRM_ONEENTRY, 2974 }, { MODRM_ONEENTRY, 2975 }, { MODRM_ONEENTRY, 2976 }, { MODRM_ONEENTRY, 2977 }, { MODRM_SPLITRM, 2129 }, { MODRM_SPLITRM, 2131 }, { MODRM_SPLITRM, 2133 }, { MODRM_SPLITRM, 2135 }, { MODRM_SPLITRM, 2137 }, { MODRM_SPLITRM, 2139 }, { MODRM_SPLITRM, 2141 }, { MODRM_SPLITRM, 2143 }, { MODRM_SPLITRM, 2145 }, { MODRM_SPLITRM, 2147 }, { MODRM_SPLITRM, 2149 }, { MODRM_SPLITRM, 2151 }, { MODRM_SPLITRM, 2153 }, { MODRM_SPLITRM, 2155 }, { MODRM_SPLITRM, 2157 }, { MODRM_SPLITRM, 2159 }, { MODRM_ONEENTRY, 2978 }, { MODRM_ONEENTRY, 2979 }, { MODRM_ONEENTRY, 2163 }, { MODRM_SPLITRM, 2980 }, { MODRM_SPLITRM, 2982 }, { MODRM_SPLITRM, 2984 }, { MODRM_SPLITMISC, 2170 }, { MODRM_SPLITMISC, 2242 }, { MODRM_ONEENTRY, 2986 }, { MODRM_ONEENTRY, 2987 }, { MODRM_ONEENTRY, 2316 }, { MODRM_SPLITRM, 2988 }, { MODRM_SPLITRM, 2990 }, { MODRM_SPLITRM, 2992 }, { MODRM_SPLITMISC, 3179 }, { MODRM_SPLITRM, 3010 }, { MODRM_SPLITRM, 2397 }, { MODRM_SPLITRM, 3012 }, { MODRM_SPLITRM, 3014 }, { MODRM_SPLITRM, 3016 }, { MODRM_SPLITRM, 3018 }, { MODRM_SPLITRM, 3020 }, { MODRM_SPLITRM, 3022 }, { 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MODRM_ONEENTRY, 3892 }, { MODRM_ONEENTRY, 3892 }, { MODRM_ONEENTRY, 3892 }, { MODRM_ONEENTRY, 3892 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2471 }, { MODRM_SPLITRM, 2473 }, { MODRM_SPLITRM, 2475 }, { MODRM_SPLITRM, 2477 }, { MODRM_SPLITRM, 2479 }, { MODRM_SPLITRM, 3588 }, { MODRM_SPLITRM, 2481 }, { MODRM_SPLITRM, 2483 }, { MODRM_SPLITRM, 2485 }, { MODRM_SPLITRM, 2487 }, { MODRM_SPLITRM, 2489 }, { MODRM_SPLITRM, 2491 }, { MODRM_SPLITRM, 2493 }, { MODRM_SPLITRM, 2495 }, { MODRM_SPLITRM, 2497 }, { MODRM_SPLITRM, 2499 }, { MODRM_SPLITRM, 2501 }, { MODRM_SPLITRM, 2503 }, { MODRM_SPLITRM, 2505 }, { MODRM_SPLITRM, 2507 }, { MODRM_SPLITRM, 2509 }, { MODRM_SPLITRM, 3590 }, { MODRM_SPLITRM, 2511 }, { MODRM_SPLITRM, 2513 }, { MODRM_SPLITRM, 2515 }, { MODRM_SPLITRM, 2517 }, { MODRM_SPLITRM, 2519 }, { MODRM_SPLITRM, 2521 }, { MODRM_SPLITRM, 2523 }, { MODRM_SPLITRM, 2525 }, { MODRM_SPLITRM, 2527 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2529 }, { MODRM_SPLITRM, 2531 }, { MODRM_SPLITRM, 2533 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10707 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10709 }, { MODRM_SPLITRM, 10711 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10713 }, { MODRM_SPLITRM, 10715 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10717 }, { MODRM_SPLITRM, 10719 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10721 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10723 }, { MODRM_SPLITRM, 10725 }, { MODRM_SPLITRM, 10727 }, { MODRM_SPLITRM, 10729 }, { MODRM_SPLITRM, 10731 }, { MODRM_SPLITRM, 10733 }, { MODRM_SPLITRM, 10735 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10737 }, { MODRM_SPLITRM, 10739 }, { MODRM_SPLITRM, 10741 }, { MODRM_SPLITRM, 10743 }, { MODRM_SPLITRM, 10553 }, { MODRM_SPLITRM, 10555 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10559 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10561 }, { MODRM_SPLITRM, 10563 }, { MODRM_SPLITRM, 10565 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10745 }, { MODRM_SPLITRM, 10747 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10749 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 10575 }, { MODRM_SPLITREG, 10751 }, { MODRM_SPLITREG, 10767 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10783 }, { MODRM_SPLITRM, 10785 }, { MODRM_SPLITRM, 10787 }, { MODRM_SPLITRM, 10789 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10791 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10793 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10795 }, { MODRM_SPLITRM, 10797 }, { MODRM_SPLITRM, 10621 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10623 }, { MODRM_SPLITRM, 10625 }, { MODRM_SPLITRM, 10627 }, { MODRM_SPLITRM, 10799 }, { MODRM_SPLITRM, 10631 }, { MODRM_SPLITRM, 10633 }, { MODRM_SPLITRM, 10635 }, { MODRM_SPLITRM, 10801 }, { MODRM_SPLITRM, 10639 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10803 }, { MODRM_SPLITRM, 10645 }, { MODRM_SPLITRM, 10647 }, { MODRM_SPLITRM, 10649 }, { MODRM_SPLITRM, 10805 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10651 }, { MODRM_SPLITRM, 10653 }, { MODRM_SPLITRM, 10655 }, { MODRM_SPLITRM, 10807 }, { MODRM_SPLITRM, 10659 }, { MODRM_SPLITRM, 10661 }, { MODRM_SPLITRM, 10663 }, { MODRM_SPLITRM, 10809 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10811 }, { MODRM_SPLITRM, 10813 }, { MODRM_SPLITRM, 10671 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10673 }, { MODRM_SPLITRM, 10675 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10815 }, { MODRM_SPLITRM, 10679 }, { MODRM_SPLITRM, 10681 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; static const unsigned char index_x86DisassemblerThreeByte38Opcodes[] = { 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 9, 10, 11, 12, 13, 14, 15, 16, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 0, 0, 0, 30, 0, 0, 0, 31, 0, 32, 33, 34, 0, 35, 0, 36, 0, 37, 0, 38, 0, 39, 0, 40, 0, 41, 42, 43, 0, 44, 0, 45, 0, 46, 47, 48, 0, 49, 0, 50, 0, 51, 0, 52, 0, 53, 0, 54, 0, 55, 56, 57, 0, 58, 0, 59, 0, 60, 0, 61, 0, 62, 0, 63, 0, 64, 0, 65, 0, 66, 0, 67, 0, 68, 0, 69, 0, 70, 0, 71, 0, 72, 0, 73, 0, 74, 0, 75, 0, 76, 0, 77, 0, 78, 0, 79, 0, 80, 0, 81, 0, 82, 0, 83, 0, 0, 0, 84, 0, 0, 0, 85, 0, 0, 0, 86, 0, 0, 0, 87, 0, 0, 0, 88, 0, 0, 0, 89, 0, 90, 91, 92, 0, 0, 0, 93, 0, 94, 0, 95, 0, 0, 0, 96, 0, 97, 98, 99, 0, 0, 0, 100, }; static const struct OpcodeDecision x86DisassemblerThreeByte38Opcodes[] = { { { { MODRM_SPLITRM, 10817 }, { MODRM_SPLITRM, 10819 }, { MODRM_SPLITRM, 10821 }, { MODRM_SPLITRM, 10823 }, { MODRM_SPLITRM, 10825 }, { MODRM_SPLITRM, 10827 }, { MODRM_SPLITRM, 10829 }, { MODRM_SPLITRM, 10831 }, { MODRM_SPLITRM, 10833 }, { MODRM_SPLITRM, 10835 }, { MODRM_SPLITRM, 10837 }, { MODRM_SPLITRM, 10839 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10841 }, { MODRM_SPLITRM, 10843 }, { MODRM_SPLITRM, 10845 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10847 }, { MODRM_SPLITRM, 10849 }, { MODRM_SPLITRM, 10851 }, { MODRM_SPLITRM, 10853 }, { MODRM_SPLITRM, 10855 }, { MODRM_SPLITRM, 10857 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10859 }, { MODRM_SPLITRM, 10861 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10863 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 10865 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_SPLITRM, 10817 }, { MODRM_SPLITRM, 10819 }, { MODRM_SPLITRM, 10821 }, { MODRM_SPLITRM, 10823 }, { MODRM_SPLITRM, 10825 }, { MODRM_SPLITRM, 10827 }, { MODRM_SPLITRM, 10829 }, { MODRM_SPLITRM, 10831 }, { MODRM_SPLITRM, 10833 }, { MODRM_SPLITRM, 10835 }, { MODRM_SPLITRM, 10837 }, { MODRM_SPLITRM, 10839 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17455 }, { MODRM_SPLITRM, 17457 }, { MODRM_SPLITRM, 17459 }, { MODRM_SPLITRM, 17461 }, { MODRM_SPLITRM, 17463 }, { MODRM_SPLITRM, 17465 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17467 }, { MODRM_SPLITRM, 17469 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17471 }, { MODRM_SPLITRM, 17473 }, { MODRM_SPLITRM, 17475 }, { MODRM_SPLITRM, 17477 }, { MODRM_SPLITRM, 17479 }, { MODRM_SPLITRM, 17481 }, { MODRM_SPLITRM, 17483 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17485 }, { MODRM_SPLITRM, 17487 }, { MODRM_SPLITRM, 17489 }, { MODRM_SPLITRM, 17491 }, { MODRM_SPLITRM, 17493 }, { MODRM_SPLITRM, 17495 }, { MODRM_SPLITRM, 17497 }, { MODRM_SPLITRM, 17499 }, { MODRM_SPLITRM, 17501 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17503 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17505 }, { MODRM_SPLITRM, 17507 }, { MODRM_SPLITRM, 17509 }, { MODRM_SPLITRM, 17511 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17513 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17515 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17517 }, { MODRM_SPLITRM, 17519 }, { MODRM_SPLITRM, 17521 }, { MODRM_SPLITRM, 17523 }, { MODRM_SPLITRM, 17525 }, { MODRM_SPLITRM, 17527 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17529 }, { MODRM_SPLITRM, 17531 }, { MODRM_SPLITRM, 17533 }, { MODRM_SPLITRM, 17535 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17537 }, { MODRM_SPLITRM, 17539 }, { MODRM_SPLITRM, 17541 }, { MODRM_SPLITRM, 17543 }, { MODRM_SPLITRM, 17545 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17547 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17549 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17551 }, { MODRM_SPLITRM, 17553 }, { MODRM_SPLITRM, 17555 }, { MODRM_SPLITRM, 17557 }, { MODRM_SPLITRM, 17559 }, { MODRM_SPLITRM, 17561 }, { MODRM_SPLITRM, 17563 }, { MODRM_SPLITRM, 17565 }, { MODRM_SPLITRM, 17567 }, { MODRM_SPLITRM, 17569 }, { MODRM_SPLITRM, 17571 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17573 }, { MODRM_SPLITRM, 17575 }, { MODRM_SPLITRM, 17577 }, { MODRM_SPLITRM, 17579 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17581 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17583 }, { MODRM_SPLITRM, 17585 }, { MODRM_SPLITRM, 17587 }, { MODRM_SPLITRM, 16775 }, { MODRM_SPLITRM, 17589 }, { MODRM_SPLITRM, 16779 }, { MODRM_SPLITRM, 17591 }, { MODRM_SPLITRM, 16783 }, { MODRM_SPLITRM, 17593 }, { MODRM_SPLITRM, 16787 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17595 }, { MODRM_SPLITRM, 17597 }, { MODRM_SPLITRM, 17599 }, { MODRM_SPLITRM, 16795 }, { MODRM_SPLITRM, 17601 }, { MODRM_SPLITRM, 16799 }, { MODRM_SPLITRM, 17603 }, { MODRM_SPLITRM, 16803 }, { MODRM_SPLITRM, 17605 }, { MODRM_SPLITRM, 16807 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17607 }, { MODRM_SPLITRM, 17609 }, { MODRM_SPLITRM, 17611 }, { MODRM_SPLITRM, 16815 }, { MODRM_SPLITRM, 17613 }, { MODRM_SPLITRM, 16819 }, { MODRM_SPLITRM, 17615 }, { MODRM_SPLITRM, 16823 }, { MODRM_SPLITRM, 17617 }, { MODRM_SPLITRM, 16827 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17619 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17621 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17623 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17625 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17627 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_SPLITRM, 17425 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17427 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17429 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17629 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17631 }, { MODRM_SPLITRM, 17633 }, { MODRM_SPLITRM, 17635 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17637 }, { MODRM_SPLITRM, 17639 }, { MODRM_SPLITRM, 17641 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17643 }, { MODRM_SPLITRM, 17645 }, { MODRM_SPLITRM, 17647 }, { MODRM_SPLITRM, 17449 }, { MODRM_SPLITRM, 17451 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17649 }, { MODRM_SPLITRM, 17455 }, { MODRM_SPLITRM, 17457 }, { MODRM_SPLITRM, 17459 }, { MODRM_SPLITRM, 17461 }, { MODRM_SPLITRM, 17463 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17651 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17653 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17471 }, { MODRM_SPLITRM, 17473 }, { MODRM_SPLITRM, 17475 }, { MODRM_SPLITRM, 17477 }, { MODRM_SPLITRM, 17479 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17655 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17485 }, { MODRM_SPLITRM, 17657 }, { MODRM_SPLITRM, 17489 }, { MODRM_SPLITRM, 17659 }, { MODRM_SPLITRM, 17493 }, { MODRM_SPLITRM, 17661 }, { MODRM_SPLITRM, 17497 }, { MODRM_SPLITRM, 17663 }, { MODRM_SPLITRM, 17665 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17667 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17669 }, { MODRM_SPLITRM, 17671 }, { MODRM_SPLITRM, 17673 }, { MODRM_SPLITRM, 17675 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17677 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17679 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17681 }, { MODRM_SPLITRM, 17683 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17685 }, { MODRM_SPLITRM, 17687 }, { MODRM_SPLITRM, 17689 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17691 }, { MODRM_SPLITRM, 17693 }, { MODRM_SPLITRM, 17695 }, { MODRM_SPLITRM, 17697 }, { MODRM_SPLITRM, 17699 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17701 }, { MODRM_SPLITRM, 17703 }, { MODRM_SPLITRM, 17705 }, { MODRM_SPLITRM, 17707 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17709 }, { MODRM_SPLITRM, 17711 }, { MODRM_SPLITRM, 17713 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17715 }, { MODRM_SPLITRM, 17717 }, { MODRM_SPLITRM, 17719 }, { MODRM_SPLITRM, 17721 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17723 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17725 }, { MODRM_SPLITRM, 17727 }, { MODRM_SPLITRM, 17729 }, { MODRM_SPLITRM, 17731 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17733 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17735 }, { MODRM_SPLITRM, 17737 }, { MODRM_SPLITRM, 17739 }, { MODRM_SPLITRM, 16943 }, { MODRM_SPLITRM, 17741 }, { MODRM_SPLITRM, 16947 }, { MODRM_SPLITRM, 17743 }, { MODRM_SPLITRM, 16951 }, { MODRM_SPLITRM, 17745 }, { MODRM_SPLITRM, 16955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17747 }, { MODRM_SPLITRM, 17749 }, { MODRM_SPLITRM, 17751 }, { MODRM_SPLITRM, 16963 }, { MODRM_SPLITRM, 17753 }, { MODRM_SPLITRM, 16967 }, { MODRM_SPLITRM, 17755 }, { MODRM_SPLITRM, 16971 }, { MODRM_SPLITRM, 17757 }, { MODRM_SPLITRM, 16975 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17759 }, { MODRM_SPLITRM, 17761 }, { MODRM_SPLITRM, 17763 }, { MODRM_SPLITRM, 17765 }, { MODRM_SPLITRM, 17767 }, { MODRM_SPLITRM, 16987 }, { MODRM_SPLITRM, 17769 }, { MODRM_SPLITRM, 16991 }, { MODRM_SPLITRM, 17771 }, { MODRM_SPLITRM, 16995 }, { MODRM_SPLITRM, 17773 }, { MODRM_SPLITRM, 16999 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17775 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17777 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17779 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17781 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; static const unsigned char index_x86DisassemblerThreeByte3AOpcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 16, 17, 18, 19, 0, 0, 20, 21, 0, 0, 22, 23, 0, 0, 0, 24, 0, 0, 0, 25, 0, 0, 0, 26, 0, 0, 0, 27, 0, 0, 0, 28, 0, 0, 0, 29, 0, 0, 0, 30, 0, 0, 0, 31, 0, 0, 0, 32, 0, 0, 0, 33, 0, 0, 0, 34, 0, 0, 0, 35, 0, 0, 0, 36, 0, 0, 0, 37, 0, 0, 0, 38, 0, 0, 0, 39, 0, 0, 0, 40, 0, 0, 0, 41, 0, 0, 0, 42, 0, 0, 0, 43, 0, 0, 0, 44, 0, 0, 0, 45, 0, 0, 0, 46, 0, 0, 0, 47, 0, 0, 0, 48, 0, 0, 0, 49, 0, 0, 0, 50, 0, 0, 0, 51, 0, 0, 0, 52, 0, 0, 0, 53, 0, 0, 0, 54, 0, 0, 0, 55, 0, 0, 0, 56, 0, 0, 0, 57, 0, 0, 0, 58, 0, 0, 0, 59, 0, 0, 0, 60, 0, 0, 0, 61, }; static const struct OpcodeDecision x86DisassemblerThreeByte3AOpcodes[] = { { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 17783 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19645 }, { MODRM_SPLITRM, 19647 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; static const unsigned char index_x86DisassemblerXOP8Opcodes[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86DisassemblerXOP8Opcodes[] = { { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19649 }, { MODRM_SPLITRM, 19651 }, { MODRM_SPLITRM, 19653 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19655 }, { MODRM_SPLITRM, 19657 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19659 }, { MODRM_SPLITRM, 19661 }, { MODRM_SPLITRM, 19663 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19665 }, { MODRM_SPLITRM, 19667 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19669 }, { MODRM_SPLITRM, 19671 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19673 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19675 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19677 }, { MODRM_SPLITRM, 19679 }, { MODRM_SPLITRM, 19681 }, { MODRM_SPLITRM, 19683 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19685 }, { MODRM_SPLITRM, 19687 }, { MODRM_SPLITRM, 19689 }, { MODRM_SPLITRM, 19691 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19693 }, { MODRM_SPLITRM, 19695 }, { MODRM_SPLITRM, 19697 }, { MODRM_SPLITRM, 19699 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19701 }, { MODRM_SPLITRM, 19703 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19705 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19707 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; static const unsigned char index_x86DisassemblerXOP9Opcodes[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86DisassemblerXOP9Opcodes[] = { { { { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 19709 }, { MODRM_SPLITREG, 19725 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 19741 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19757 }, { MODRM_SPLITRM, 19759 }, { MODRM_SPLITRM, 19761 }, { MODRM_SPLITRM, 19763 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19765 }, { MODRM_SPLITRM, 19767 }, { MODRM_SPLITRM, 19769 }, { MODRM_SPLITRM, 19771 }, { MODRM_SPLITRM, 19773 }, { MODRM_SPLITRM, 19775 }, { MODRM_SPLITRM, 19777 }, { MODRM_SPLITRM, 19779 }, { MODRM_SPLITRM, 19781 }, { MODRM_SPLITRM, 19783 }, { MODRM_SPLITRM, 19785 }, { MODRM_SPLITRM, 19787 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19789 }, { MODRM_SPLITRM, 19791 }, { MODRM_SPLITRM, 19793 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19795 }, { MODRM_SPLITRM, 19797 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19799 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19801 }, { MODRM_SPLITRM, 19803 }, { MODRM_SPLITRM, 19805 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19807 }, { MODRM_SPLITRM, 19809 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19811 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19813 }, { MODRM_SPLITRM, 19815 }, { MODRM_SPLITRM, 19817 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 19819 }, { MODRM_SPLITREG, 19835 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 19851 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19867 }, { MODRM_SPLITRM, 19869 }, { MODRM_SPLITRM, 19871 }, { MODRM_SPLITRM, 19873 }, { MODRM_SPLITRM, 19875 }, { MODRM_SPLITRM, 19877 }, { MODRM_SPLITRM, 19879 }, { MODRM_SPLITRM, 19881 }, { MODRM_SPLITRM, 19883 }, { MODRM_SPLITRM, 19885 }, { MODRM_SPLITRM, 19887 }, { MODRM_SPLITRM, 19889 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19891 }, { MODRM_SPLITRM, 19893 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; static const unsigned char index_x86DisassemblerXOPAOpcodes[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19913 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 19915 }, { MODRM_ONEENTRY, 0 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; static const unsigned char index_x86Disassembler3DNowOpcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 16, 17, 18, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86Disassembler3DNowOpcodes[] = { { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19931 }, { MODRM_SPLITRM, 19933 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19935 }, { MODRM_SPLITRM, 19937 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19939 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19941 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19943 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19945 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19947 }, { MODRM_SPLITRM, 19949 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19951 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19953 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19957 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19959 }, { MODRM_SPLITRM, 19961 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19963 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19965 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19967 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19969 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19971 }, { MODRM_SPLITRM, 19973 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19975 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19977 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19931 }, { MODRM_SPLITRM, 19933 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19935 }, { MODRM_SPLITRM, 19937 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19939 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19941 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19943 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19945 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19947 }, { MODRM_SPLITRM, 19949 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19951 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19953 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19955 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19957 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19959 }, { MODRM_SPLITRM, 19961 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19963 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19965 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19967 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19969 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19971 }, { MODRM_SPLITRM, 19973 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19975 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19977 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19931 }, { MODRM_SPLITRM, 19933 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 19935 }, { MODRM_SPLITRM, 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; capstone-sys-0.15.0/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc000064400000000000000000024640120072674642500242500ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * X86 Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ static const struct OperandSpecifier x86OperandSets[][6] = { { /* 0 */ { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 1 */ { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 2 */ { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 3 */ { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 4 */ { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 5 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 6 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 7 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 8 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 9 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 10 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 11 */ { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 12 */ { ENCODING_RM, TYPE_M }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 13 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 14 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 15 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 16 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 17 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 18 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 19 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 20 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 21 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 22 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 23 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 24 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 25 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 26 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 27 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 28 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 29 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 30 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 31 */ { ENCODING_RM, TYPE_R16 }, { ENCODING_REG, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 32 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 33 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_VVVV, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 34 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 35 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_VVVV, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 36 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 37 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 38 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 39 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 40 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 41 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 42 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 43 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 44 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 45 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 46 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 47 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 48 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_Rv, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 49 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RO, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 50 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 51 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 52 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 53 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 54 */ { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 55 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 56 */ { ENCODING_ID, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 57 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 58 */ { ENCODING_IW, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 59 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 60 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_ID, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 61 */ { ENCODING_RM, TYPE_R8 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 62 */ { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 63 */ { ENCODING_RM, TYPE_R8 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 64 */ { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 65 */ { ENCODING_DI, TYPE_DSTIDX }, { ENCODING_SI, TYPE_SRCIDX }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 66 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 67 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 68 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 69 */ { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 70 */ { ENCODING_IW, TYPE_IMM }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 71 */ { ENCODING_Iv, TYPE_IMM }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 72 */ { ENCODING_Iv, TYPE_IMM }, { ENCODING_IW, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 73 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 74 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 75 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 76 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 77 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 78 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 79 */ { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 80 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 81 */ { ENCODING_DI, TYPE_DSTIDX }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 82 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 83 */ { ENCODING_IB, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 84 */ { ENCODING_Iv, TYPE_REL }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 85 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 86 */ { ENCODING_RM, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 87 */ { ENCODING_SI, TYPE_SRCIDX }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 88 */ { ENCODING_IW, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 89 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 90 */ { ENCODING_VVVV, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 91 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 92 */ { ENCODING_VVVV, TYPE_R64 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 93 */ { ENCODING_Ia, TYPE_MOFFS }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 94 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 95 */ { ENCODING_Rv, TYPE_Rv }, { ENCODING_Iv, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 96 */ { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 97 */ { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 98 */ { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 99 */ { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 100 */ { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 101 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 102 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 103 */ { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 104 */ { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 105 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_CONTROLREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 106 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_DEBUGREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 107 */ { ENCODING_RO, TYPE_R64 }, { ENCODING_IO, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 108 */ { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 109 */ { ENCODING_REG, TYPE_SEGMENTREG }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 110 */ { ENCODING_RB, TYPE_R8 }, { ENCODING_IB, TYPE_IMM }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 111 */ { ENCODING_REG, TYPE_R16 }, { ENCODING_RM, TYPE_M }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 112 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 113 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 114 */ { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 115 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R16 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 116 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 117 */ { ENCODING_Rv, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 118 */ { ENCODING_RO, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 119 */ { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 120 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 121 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 122 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 123 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 124 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 125 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 126 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_M }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 127 */ { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 128 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_Rv }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 129 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 130 */ { ENCODING_RM, TYPE_M }, { ENCODING_REG, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 131 */ { ENCODING_DUP, TYPE_DUP1 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_IB, TYPE_UIMM8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 132 */ { ENCODING_RM, TYPE_R32 }, { ENCODING_REG, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 133 */ { ENCODING_REG, TYPE_R32 }, { ENCODING_RM, TYPE_R32 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 134 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_RM, TYPE_Rv }, { ENCODING_REG, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 135 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 136 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 137 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_Rv }, { ENCODING_RM, TYPE_Rv }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 138 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_R64 }, { ENCODING_RM, TYPE_R64 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, { /* 139 */ { ENCODING_DUP, TYPE_DUP2 }, { ENCODING_DUP, TYPE_DUP3 }, { ENCODING_REG, TYPE_R8 }, { ENCODING_RM, TYPE_R8 }, { ENCODING_NONE, TYPE_NONE }, { ENCODING_NONE, TYPE_NONE }, }, }; static const struct InstructionSpecifier x86DisassemblerInstrSpecifiers[1671] = { { /* 0 */ 0, /* */ }, { /* 1 */ 0, /* */ }, { /* 2 */ 0, /* */ }, { /* 3 */ 0, /* */ }, { /* 4 */ 0, /* */ }, { /* 5 */ 0, /* */ }, { /* 6 */ 0, /* */ }, { /* 7 */ 0, /* */ }, { /* 8 */ 0, /* */ }, { /* 9 */ 0, /* */ }, { /* 10 */ 0, /* */ }, { /* 11 */ 0, /* */ }, { /* 12 */ 0, /* */ }, { /* 13 */ 0, /* */ }, { /* 14 */ 0, /* */ }, { /* 15 */ 0, /* */ }, { /* 16 */ 0, /* */ }, { /* 17 */ 0, /* */ }, { /* 18 */ 0, /* */ }, { /* 19 */ 0, /* */ }, { /* 20 */ 0, /* */ }, { /* 21 */ 0, /* */ }, { /* 22 */ 0, /* */ }, { /* 23 */ 0, /* */ }, { /* 24 */ 0, /* */ }, { /* 25 */ 0, /* */ }, { /* 26 */ 0, /* */ }, { /* 27 */ 0, /* */ }, { /* 28 */ 0, /* */ }, { /* 29 */ 0, /* */ }, { /* 30 */ 0, /* */ }, { /* 31 */ 0, /* */ }, { /* 32 */ 0, /* */ }, { /* 33 */ 0, /* */ }, { /* 34 */ 0, /* */ }, { /* 35 */ 0, /* */ }, { /* 36 */ 0, /* */ }, { /* 37 */ 0, /* */ }, { /* 38 */ 0, /* */ }, { /* 39 */ 0, /* */ }, { /* 40 */ 0, /* */ }, { /* 41 */ 0, /* */ }, { /* 42 */ 0, /* */ }, { /* 43 */ 0, /* */ }, { /* 44 */ 0, /* */ }, { /* 45 */ 0, /* */ }, { /* 46 */ 0, /* */ }, { /* 47 */ 0, /* */ }, { /* 48 */ 0, /* */ }, { /* 49 */ 0, /* */ }, { /* 50 */ 0, /* */ }, { /* 51 */ 0, /* */ }, { /* 52 */ 0, /* */ }, { /* 53 */ 0, /* */ }, { /* 54 */ 0, /* */ }, { /* 55 */ 0, /* */ }, { /* 56 */ 0, /* */ }, { /* 57 */ 0, /* */ }, { /* 58 */ 0, /* */ }, { /* 59 */ 0, /* */ }, { /* 60 */ 0, /* */ }, { /* 61 */ 0, /* */ }, { /* 62 */ 0, /* */ }, { /* 63 */ 0, /* */ }, { /* 64 */ 0, /* */ }, { /* 65 */ 0, /* */ }, { /* 66 */ 0, /* */ }, { /* 67 */ 0, /* */ }, { /* 68 */ 0, /* */ }, { /* 69 */ 0, /* */ }, { /* 70 */ 0, /* */ }, { /* 71 */ 0, /* */ }, { /* 72 */ 0, /* */ }, { /* 73 */ 0, /* */ }, { /* 74 */ 0, /* */ }, { /* 75 */ 0, /* */ }, { /* 76 */ 0, /* */ }, { /* 77 */ 0, /* */ }, { /* 78 */ 0, /* */ }, { /* 79 */ 0, /* */ }, { /* 80 */ 0, /* */ }, { /* 81 */ 0, /* */ }, { /* 82 */ 0, /* */ }, { /* 83 */ 0, /* */ }, { /* 84 */ 0, /* */ }, { /* 85 */ 0, /* */ }, { /* 86 */ 0, /* */ }, { /* 87 */ 0, /* */ }, { /* 88 */ 0, /* */ }, { /* 89 */ 0, /* */ }, { /* 90 */ 0, /* */ }, { /* 91 */ 0, /* */ }, { /* 92 */ 0, /* */ }, { /* 93 */ 0, /* */ }, { /* 94 */ 0, /* */ }, { /* 95 */ 0, /* */ }, { /* 96 */ 0, /* */ }, { /* 97 */ 0, /* */ }, { /* 98 */ 0, /* */ }, { /* 99 */ 0, /* */ }, { /* 100 */ 0, /* */ }, { /* 101 */ 0, /* */ }, { /* 102 */ 0, /* */ }, { /* 103 */ 0, /* */ }, { /* 104 */ 0, /* */ }, { /* 105 */ 0, /* */ }, { /* 106 */ 0, /* */ }, { /* 107 */ 0, /* */ }, { /* 108 */ 0, /* */ }, { /* 109 */ 0, /* */ }, { /* 110 */ 0, /* */ }, { /* 111 */ 0, /* */ }, { /* 112 */ 0, /* */ }, { /* 113 */ 0, /* */ }, { /* 114 */ 0, /* */ }, { /* 115 */ 0, /* */ }, { /* 116 */ 0, /* */ }, { /* 117 */ 0, /* */ }, { /* 118 */ 0, /* */ }, { /* 119 */ 0, /* */ }, { /* 120 */ 0, /* */ }, { /* 121 */ 0, /* */ }, { /* 122 */ 0, /* */ }, { /* 123 */ 0, /* */ }, { /* 124 */ 0, /* */ }, { /* 125 */ 0, /* */ }, { /* 126 */ 0, /* AAA */ }, { /* 127 */ 1, /* AAD8i8 */ }, { /* 128 */ 1, /* AAM8i8 */ }, { /* 129 */ 0, /* AAS */ }, { /* 130 */ 2, /* ADC16i16 */ }, { /* 131 */ 3, /* ADC16mi */ }, { /* 132 */ 4, /* ADC16mi8 */ }, { /* 133 */ 5, /* ADC16mr */ }, { /* 134 */ 6, /* ADC16ri */ }, { /* 135 */ 7, /* ADC16ri8 */ }, { /* 136 */ 8, /* ADC16rm */ }, { /* 137 */ 9, /* ADC16rr */ }, { /* 138 */ 10, /* ADC16rr_REV */ }, { /* 139 */ 2, /* ADC32i32 */ }, { /* 140 */ 3, /* ADC32mi */ }, { /* 141 */ 4, /* ADC32mi8 */ }, { /* 142 */ 5, /* ADC32mr */ }, { /* 143 */ 6, /* ADC32ri */ }, { /* 144 */ 7, /* ADC32ri8 */ }, { /* 145 */ 8, /* ADC32rm */ }, { /* 146 */ 9, /* ADC32rr */ }, { /* 147 */ 10, /* ADC32rr_REV */ }, { /* 148 */ 11, /* ADC64i32 */ }, { /* 149 */ 12, /* ADC64mi32 */ }, { /* 150 */ 4, /* ADC64mi8 */ }, { /* 151 */ 13, /* ADC64mr */ }, { /* 152 */ 14, /* ADC64ri32 */ }, { /* 153 */ 15, /* ADC64ri8 */ }, { /* 154 */ 16, /* ADC64rm */ }, { /* 155 */ 17, /* ADC64rr */ }, { /* 156 */ 18, /* ADC64rr_REV */ }, { /* 157 */ 1, /* ADC8i8 */ }, { /* 158 */ 4, /* ADC8mi */ }, { /* 159 */ 4, /* ADC8mi8 */ }, { /* 160 */ 19, /* ADC8mr */ }, { /* 161 */ 20, /* ADC8ri */ }, { /* 162 */ 20, /* ADC8ri8 */ }, { /* 163 */ 21, /* ADC8rm */ }, { /* 164 */ 22, /* ADC8rr */ }, { /* 165 */ 23, /* ADC8rr_REV */ }, { /* 166 */ 24, /* ADCX32rm */ }, { /* 167 */ 25, /* ADCX32rr */ }, { /* 168 */ 16, /* ADCX64rm */ }, { /* 169 */ 18, /* ADCX64rr */ }, { /* 170 */ 2, /* ADD16i16 */ }, { /* 171 */ 3, /* ADD16mi */ }, { /* 172 */ 4, /* ADD16mi8 */ }, { /* 173 */ 5, /* ADD16mr */ }, { /* 174 */ 6, /* ADD16ri */ }, { /* 175 */ 7, /* ADD16ri8 */ }, { /* 176 */ 8, /* ADD16rm */ }, { /* 177 */ 9, /* ADD16rr */ }, { /* 178 */ 10, /* ADD16rr_REV */ }, { /* 179 */ 2, /* ADD32i32 */ }, { /* 180 */ 3, /* ADD32mi */ }, { /* 181 */ 4, /* ADD32mi8 */ }, { /* 182 */ 5, /* ADD32mr */ }, { /* 183 */ 6, /* ADD32ri */ }, { /* 184 */ 7, /* ADD32ri8 */ }, { /* 185 */ 8, /* ADD32rm */ }, { /* 186 */ 9, /* ADD32rr */ }, { /* 187 */ 10, /* ADD32rr_REV */ }, { /* 188 */ 11, /* ADD64i32 */ }, { /* 189 */ 12, /* ADD64mi32 */ }, { /* 190 */ 4, /* ADD64mi8 */ }, { /* 191 */ 13, /* ADD64mr */ }, { /* 192 */ 14, /* ADD64ri32 */ }, { /* 193 */ 15, /* ADD64ri8 */ }, { /* 194 */ 16, /* ADD64rm */ }, { /* 195 */ 17, /* ADD64rr */ }, { /* 196 */ 18, /* ADD64rr_REV */ }, { /* 197 */ 1, /* ADD8i8 */ }, { /* 198 */ 4, /* ADD8mi */ }, { /* 199 */ 4, /* ADD8mi8 */ }, { /* 200 */ 19, /* ADD8mr */ }, { /* 201 */ 20, /* ADD8ri */ }, { /* 202 */ 20, /* ADD8ri8 */ }, { /* 203 */ 21, /* ADD8rm */ }, { /* 204 */ 22, /* ADD8rr */ }, { /* 205 */ 23, /* ADD8rr_REV */ }, { /* 206 */ 24, /* ADOX32rm */ }, { /* 207 */ 25, /* ADOX32rr */ }, { /* 208 */ 16, /* ADOX64rm */ }, { /* 209 */ 18, /* ADOX64rr */ }, { /* 210 */ 2, /* AND16i16 */ }, { /* 211 */ 3, /* AND16mi */ }, { /* 212 */ 4, /* AND16mi8 */ }, { /* 213 */ 5, /* AND16mr */ }, { /* 214 */ 6, /* AND16ri */ }, { /* 215 */ 7, /* AND16ri8 */ }, { /* 216 */ 8, /* AND16rm */ }, { /* 217 */ 9, /* AND16rr */ }, { /* 218 */ 10, /* AND16rr_REV */ }, { /* 219 */ 2, /* AND32i32 */ }, { /* 220 */ 3, /* AND32mi */ }, { /* 221 */ 4, /* AND32mi8 */ }, { /* 222 */ 5, /* AND32mr */ }, { /* 223 */ 6, /* AND32ri */ }, { /* 224 */ 7, /* AND32ri8 */ }, { /* 225 */ 8, /* AND32rm */ }, { /* 226 */ 9, /* AND32rr */ }, { /* 227 */ 10, /* AND32rr_REV */ }, { /* 228 */ 11, /* AND64i32 */ }, { /* 229 */ 12, /* AND64mi32 */ }, { /* 230 */ 4, /* AND64mi8 */ }, { /* 231 */ 13, /* AND64mr */ }, { /* 232 */ 14, /* AND64ri32 */ }, { /* 233 */ 15, /* AND64ri8 */ }, { /* 234 */ 16, /* AND64rm */ }, { /* 235 */ 17, /* AND64rr */ }, { /* 236 */ 18, /* AND64rr_REV */ }, { /* 237 */ 1, /* AND8i8 */ }, { /* 238 */ 4, /* AND8mi */ }, { /* 239 */ 4, /* AND8mi8 */ }, { /* 240 */ 19, /* AND8mr */ }, { /* 241 */ 20, /* AND8ri */ }, { /* 242 */ 20, /* AND8ri8 */ }, { /* 243 */ 21, /* AND8rm */ }, { /* 244 */ 22, /* AND8rr */ }, { /* 245 */ 23, /* AND8rr_REV */ }, { /* 246 */ 26, /* ANDN32rm */ }, { /* 247 */ 27, /* ANDN32rr */ }, { /* 248 */ 28, /* ANDN64rm */ }, { /* 249 */ 29, /* ANDN64rr */ }, { /* 250 */ 30, /* ARPL16mr */ }, { /* 251 */ 31, /* ARPL16rr */ }, { /* 252 */ 32, /* BEXTR32rm */ }, { /* 253 */ 33, /* BEXTR32rr */ }, { /* 254 */ 34, /* BEXTR64rm */ }, { /* 255 */ 35, /* BEXTR64rr */ }, { /* 256 */ 36, /* BEXTRI32mi */ }, { /* 257 */ 37, /* BEXTRI32ri */ }, { /* 258 */ 38, /* BEXTRI64mi */ }, { /* 259 */ 39, /* BEXTRI64ri */ }, { /* 260 */ 40, /* BLCFILL32rm */ }, { /* 261 */ 41, /* BLCFILL32rr */ }, { /* 262 */ 42, /* BLCFILL64rm */ }, { /* 263 */ 43, /* BLCFILL64rr */ }, { /* 264 */ 40, /* BLCI32rm */ }, { /* 265 */ 41, /* BLCI32rr */ }, { /* 266 */ 42, /* BLCI64rm */ }, { /* 267 */ 43, /* BLCI64rr */ }, { /* 268 */ 40, /* BLCIC32rm */ }, { /* 269 */ 41, /* BLCIC32rr */ }, { /* 270 */ 42, /* BLCIC64rm */ }, { /* 271 */ 43, /* BLCIC64rr */ }, { /* 272 */ 40, /* BLCMSK32rm */ }, { /* 273 */ 41, /* BLCMSK32rr */ }, { /* 274 */ 42, /* BLCMSK64rm */ }, { /* 275 */ 43, /* BLCMSK64rr */ }, { /* 276 */ 40, /* BLCS32rm */ }, { /* 277 */ 41, /* BLCS32rr */ }, { /* 278 */ 42, /* BLCS64rm */ }, { /* 279 */ 43, /* BLCS64rr */ }, { /* 280 */ 40, /* BLSFILL32rm */ }, { /* 281 */ 41, /* BLSFILL32rr */ }, { /* 282 */ 42, /* BLSFILL64rm */ }, { /* 283 */ 43, /* BLSFILL64rr */ }, { /* 284 */ 40, /* BLSI32rm */ }, { /* 285 */ 41, /* BLSI32rr */ }, { /* 286 */ 42, /* BLSI64rm */ }, { /* 287 */ 43, /* BLSI64rr */ }, { /* 288 */ 40, /* BLSIC32rm */ }, { /* 289 */ 41, /* BLSIC32rr */ }, { /* 290 */ 42, /* BLSIC64rm */ }, { /* 291 */ 43, /* BLSIC64rr */ }, { /* 292 */ 40, /* BLSMSK32rm */ }, { /* 293 */ 41, /* BLSMSK32rr */ }, { /* 294 */ 42, /* BLSMSK64rm */ }, { /* 295 */ 43, /* BLSMSK64rr */ }, { /* 296 */ 40, /* BLSR32rm */ }, { /* 297 */ 41, /* BLSR32rr */ }, { /* 298 */ 42, /* BLSR64rm */ }, { /* 299 */ 43, /* BLSR64rr */ }, { /* 300 */ 44, /* BOUNDS16rm */ }, { /* 301 */ 44, /* BOUNDS32rm */ }, { /* 302 */ 44, /* BSF16rm */ }, { /* 303 */ 45, /* BSF16rr */ }, { /* 304 */ 44, /* BSF32rm */ }, { /* 305 */ 45, /* BSF32rr */ }, { /* 306 */ 46, /* BSF64rm */ }, { /* 307 */ 47, /* BSF64rr */ }, { /* 308 */ 44, /* BSR16rm */ }, { /* 309 */ 45, /* BSR16rr */ }, { /* 310 */ 44, /* BSR32rm */ }, { /* 311 */ 45, /* BSR32rr */ }, { /* 312 */ 46, /* BSR64rm */ }, { /* 313 */ 47, /* BSR64rr */ }, { /* 314 */ 48, /* BSWAP16r_BAD */ }, { /* 315 */ 48, /* BSWAP32r */ }, { /* 316 */ 49, /* BSWAP64r */ }, { /* 317 */ 4, /* BT16mi8 */ }, { /* 318 */ 5, /* BT16mr */ }, { /* 319 */ 50, /* BT16ri8 */ }, { /* 320 */ 51, /* BT16rr */ }, { /* 321 */ 4, /* BT32mi8 */ }, { /* 322 */ 5, /* BT32mr */ }, { /* 323 */ 50, /* BT32ri8 */ }, { /* 324 */ 51, /* BT32rr */ }, { /* 325 */ 4, /* BT64mi8 */ }, { /* 326 */ 13, /* BT64mr */ }, { /* 327 */ 52, /* BT64ri8 */ }, { /* 328 */ 53, /* BT64rr */ }, { /* 329 */ 4, /* BTC16mi8 */ }, { /* 330 */ 5, /* BTC16mr */ }, { /* 331 */ 7, /* BTC16ri8 */ }, { /* 332 */ 9, /* BTC16rr */ }, { /* 333 */ 4, /* BTC32mi8 */ }, { /* 334 */ 5, /* BTC32mr */ }, { /* 335 */ 7, /* BTC32ri8 */ }, { /* 336 */ 9, /* BTC32rr */ }, { /* 337 */ 4, /* BTC64mi8 */ }, { /* 338 */ 13, /* BTC64mr */ }, { /* 339 */ 15, /* BTC64ri8 */ }, { /* 340 */ 17, /* BTC64rr */ }, { /* 341 */ 4, /* BTR16mi8 */ }, { /* 342 */ 5, /* BTR16mr */ }, { /* 343 */ 7, /* BTR16ri8 */ }, { /* 344 */ 9, /* BTR16rr */ }, { /* 345 */ 4, /* BTR32mi8 */ }, { /* 346 */ 5, /* BTR32mr */ }, { /* 347 */ 7, /* BTR32ri8 */ }, { /* 348 */ 9, /* BTR32rr */ }, { /* 349 */ 4, /* BTR64mi8 */ }, { /* 350 */ 13, /* BTR64mr */ }, { /* 351 */ 15, /* BTR64ri8 */ }, { /* 352 */ 17, /* BTR64rr */ }, { /* 353 */ 4, /* BTS16mi8 */ }, { /* 354 */ 5, /* BTS16mr */ }, { /* 355 */ 7, /* BTS16ri8 */ }, { /* 356 */ 9, /* BTS16rr */ }, { /* 357 */ 4, /* BTS32mi8 */ }, { /* 358 */ 5, /* BTS32mr */ }, { /* 359 */ 7, /* BTS32ri8 */ }, { /* 360 */ 9, /* BTS32rr */ }, { /* 361 */ 4, /* BTS64mi8 */ }, { /* 362 */ 13, /* BTS64mr */ }, { /* 363 */ 15, /* BTS64ri8 */ }, { /* 364 */ 17, /* BTS64rr */ }, { /* 365 */ 32, /* BZHI32rm */ }, { /* 366 */ 33, /* BZHI32rr */ }, { /* 367 */ 34, /* BZHI64rm */ }, { /* 368 */ 35, /* BZHI64rr */ }, { /* 369 */ 54, /* CALL16m */ }, { /* 370 */ 0, /* */ }, { /* 371 */ 55, /* CALL16r */ }, { /* 372 */ 0, /* */ }, { /* 373 */ 54, /* CALL32m */ }, { /* 374 */ 0, /* */ }, { /* 375 */ 55, /* CALL32r */ }, { /* 376 */ 0, /* */ }, { /* 377 */ 54, /* CALL64m */ }, { /* 378 */ 0, /* */ }, { /* 379 */ 56, /* CALL64pcrel32 */ }, { /* 380 */ 57, /* CALL64r */ }, { /* 381 */ 0, /* */ }, { /* 382 */ 58, /* CALLpcrel16 */ }, { /* 383 */ 56, /* CALLpcrel32 */ }, { /* 384 */ 0, /* CBW */ }, { /* 385 */ 0, /* CDQ */ }, { /* 386 */ 0, /* CDQE */ }, { /* 387 */ 0, /* CLAC */ }, { /* 388 */ 0, /* CLC */ }, { /* 389 */ 0, /* CLD */ }, { /* 390 */ 54, /* CLDEMOTE */ }, { /* 391 */ 54, /* CLFLUSHOPT */ }, { /* 392 */ 0, /* CLGI */ }, { /* 393 */ 0, /* CLI */ }, { /* 394 */ 54, /* CLRSSBSY */ }, { /* 395 */ 0, /* CLTS */ }, { /* 396 */ 54, /* CLWB */ }, { /* 397 */ 0, /* CLZEROr */ }, { /* 398 */ 0, /* CMC */ }, { /* 399 */ 8, /* CMOVA16rm */ }, { /* 400 */ 10, /* CMOVA16rr */ }, { /* 401 */ 8, /* CMOVA32rm */ }, { /* 402 */ 10, /* CMOVA32rr */ }, { /* 403 */ 16, /* CMOVA64rm */ }, { /* 404 */ 18, /* CMOVA64rr */ }, { /* 405 */ 8, /* CMOVAE16rm */ }, { /* 406 */ 10, /* CMOVAE16rr */ }, { /* 407 */ 8, /* CMOVAE32rm */ }, { /* 408 */ 10, /* CMOVAE32rr */ }, { /* 409 */ 16, /* CMOVAE64rm */ }, { /* 410 */ 18, /* CMOVAE64rr */ }, { /* 411 */ 8, /* CMOVB16rm */ }, { /* 412 */ 10, /* CMOVB16rr */ }, { /* 413 */ 8, /* CMOVB32rm */ }, { /* 414 */ 10, /* CMOVB32rr */ }, { /* 415 */ 16, /* CMOVB64rm */ }, { /* 416 */ 18, /* CMOVB64rr */ }, { /* 417 */ 8, /* CMOVBE16rm */ }, { /* 418 */ 10, /* CMOVBE16rr */ }, { /* 419 */ 8, /* CMOVBE32rm */ }, { /* 420 */ 10, /* CMOVBE32rr */ }, { /* 421 */ 16, /* CMOVBE64rm */ }, { /* 422 */ 18, /* CMOVBE64rr */ }, { /* 423 */ 8, /* CMOVE16rm */ }, { /* 424 */ 10, /* CMOVE16rr */ }, { /* 425 */ 8, /* CMOVE32rm */ }, { /* 426 */ 10, /* CMOVE32rr */ }, { /* 427 */ 16, /* CMOVE64rm */ }, { /* 428 */ 18, /* CMOVE64rr */ }, { /* 429 */ 8, /* CMOVG16rm */ }, { /* 430 */ 10, /* CMOVG16rr */ }, { /* 431 */ 8, /* CMOVG32rm */ }, { /* 432 */ 10, /* CMOVG32rr */ }, { /* 433 */ 16, /* CMOVG64rm */ }, { /* 434 */ 18, /* CMOVG64rr */ }, { /* 435 */ 8, /* CMOVGE16rm */ }, { /* 436 */ 10, /* CMOVGE16rr */ }, { /* 437 */ 8, /* CMOVGE32rm */ }, { /* 438 */ 10, /* CMOVGE32rr */ }, { /* 439 */ 16, /* CMOVGE64rm */ }, { /* 440 */ 18, /* CMOVGE64rr */ }, { /* 441 */ 8, /* CMOVL16rm */ }, { /* 442 */ 10, /* CMOVL16rr */ }, { /* 443 */ 8, /* CMOVL32rm */ }, { /* 444 */ 10, /* CMOVL32rr */ }, { /* 445 */ 16, /* CMOVL64rm */ }, { /* 446 */ 18, /* CMOVL64rr */ }, { /* 447 */ 8, /* CMOVLE16rm */ }, { /* 448 */ 10, /* CMOVLE16rr */ }, { /* 449 */ 8, /* CMOVLE32rm */ }, { /* 450 */ 10, /* CMOVLE32rr */ }, { /* 451 */ 16, /* CMOVLE64rm */ }, { /* 452 */ 18, /* CMOVLE64rr */ }, { /* 453 */ 8, /* CMOVNE16rm */ }, { /* 454 */ 10, /* CMOVNE16rr */ }, { /* 455 */ 8, /* CMOVNE32rm */ }, { /* 456 */ 10, /* CMOVNE32rr */ }, { /* 457 */ 16, /* CMOVNE64rm */ }, { /* 458 */ 18, /* CMOVNE64rr */ }, { /* 459 */ 8, /* CMOVNO16rm */ }, { /* 460 */ 10, /* CMOVNO16rr */ }, { /* 461 */ 8, /* CMOVNO32rm */ }, { /* 462 */ 10, /* CMOVNO32rr */ }, { /* 463 */ 16, /* CMOVNO64rm */ }, { /* 464 */ 18, /* CMOVNO64rr */ }, { /* 465 */ 8, /* CMOVNP16rm */ }, { /* 466 */ 10, /* CMOVNP16rr */ }, { /* 467 */ 8, /* CMOVNP32rm */ }, { /* 468 */ 10, /* CMOVNP32rr */ }, { /* 469 */ 16, /* CMOVNP64rm */ }, { /* 470 */ 18, /* CMOVNP64rr */ }, { /* 471 */ 8, /* CMOVNS16rm */ }, { /* 472 */ 10, /* CMOVNS16rr */ }, { /* 473 */ 8, /* CMOVNS32rm */ }, { /* 474 */ 10, /* CMOVNS32rr */ }, { /* 475 */ 16, /* CMOVNS64rm */ }, { /* 476 */ 18, /* CMOVNS64rr */ }, { /* 477 */ 8, /* CMOVO16rm */ }, { /* 478 */ 10, /* CMOVO16rr */ }, { /* 479 */ 8, /* CMOVO32rm */ }, { /* 480 */ 10, /* CMOVO32rr */ }, { /* 481 */ 16, /* CMOVO64rm */ }, { /* 482 */ 18, /* CMOVO64rr */ }, { /* 483 */ 8, /* CMOVP16rm */ }, { /* 484 */ 10, /* CMOVP16rr */ }, { /* 485 */ 8, /* CMOVP32rm */ }, { /* 486 */ 10, /* CMOVP32rr */ }, { /* 487 */ 16, /* CMOVP64rm */ }, { /* 488 */ 18, /* CMOVP64rr */ }, { /* 489 */ 8, /* CMOVS16rm */ }, { /* 490 */ 10, /* CMOVS16rr */ }, { /* 491 */ 8, /* CMOVS32rm */ }, { /* 492 */ 10, /* CMOVS32rr */ }, { /* 493 */ 16, /* CMOVS64rm */ }, { /* 494 */ 18, /* CMOVS64rr */ }, { /* 495 */ 2, /* CMP16i16 */ }, { /* 496 */ 3, /* CMP16mi */ }, { /* 497 */ 4, /* CMP16mi8 */ }, { /* 498 */ 5, /* CMP16mr */ }, { /* 499 */ 59, /* CMP16ri */ }, { /* 500 */ 50, /* CMP16ri8 */ }, { /* 501 */ 44, /* CMP16rm */ }, { /* 502 */ 51, /* CMP16rr */ }, { /* 503 */ 45, /* CMP16rr_REV */ }, { /* 504 */ 2, /* CMP32i32 */ }, { /* 505 */ 3, /* CMP32mi */ }, { /* 506 */ 4, /* CMP32mi8 */ }, { /* 507 */ 5, /* CMP32mr */ }, { /* 508 */ 59, /* CMP32ri */ }, { /* 509 */ 50, /* CMP32ri8 */ }, { /* 510 */ 44, /* CMP32rm */ }, { /* 511 */ 51, /* CMP32rr */ }, { /* 512 */ 45, /* CMP32rr_REV */ }, { /* 513 */ 11, /* CMP64i32 */ }, { /* 514 */ 12, /* CMP64mi32 */ }, { /* 515 */ 4, /* CMP64mi8 */ }, { /* 516 */ 13, /* CMP64mr */ }, { /* 517 */ 60, /* CMP64ri32 */ }, { /* 518 */ 52, /* CMP64ri8 */ }, { /* 519 */ 46, /* CMP64rm */ }, { /* 520 */ 53, /* CMP64rr */ }, { /* 521 */ 47, /* CMP64rr_REV */ }, { /* 522 */ 1, /* CMP8i8 */ }, { /* 523 */ 4, /* CMP8mi */ }, { /* 524 */ 4, /* CMP8mi8 */ }, { /* 525 */ 19, /* CMP8mr */ }, { /* 526 */ 61, /* CMP8ri */ }, { /* 527 */ 61, /* CMP8ri8 */ }, { /* 528 */ 62, /* CMP8rm */ }, { /* 529 */ 63, /* CMP8rr */ }, { /* 530 */ 64, /* CMP8rr_REV */ }, { /* 531 */ 65, /* CMPSB */ }, { /* 532 */ 65, /* CMPSL */ }, { /* 533 */ 65, /* CMPSQ */ }, { /* 534 */ 65, /* CMPSW */ }, { /* 535 */ 54, /* CMPXCHG16B */ }, { /* 536 */ 5, /* CMPXCHG16rm */ }, { /* 537 */ 51, /* CMPXCHG16rr */ }, { /* 538 */ 5, /* CMPXCHG32rm */ }, { /* 539 */ 51, /* CMPXCHG32rr */ }, { /* 540 */ 13, /* CMPXCHG64rm */ }, { /* 541 */ 53, /* CMPXCHG64rr */ }, { /* 542 */ 54, /* CMPXCHG8B */ }, { /* 543 */ 19, /* CMPXCHG8rm */ }, { /* 544 */ 63, /* CMPXCHG8rr */ }, { /* 545 */ 0, /* CPUID */ }, { /* 546 */ 0, /* CQO */ }, { /* 547 */ 0, /* CWD */ }, { /* 548 */ 0, /* CWDE */ }, { /* 549 */ 0, /* DAA */ }, { /* 550 */ 0, /* DAS */ }, { /* 551 */ 0, /* DATA16_PREFIX */ }, { /* 552 */ 54, /* DEC16m */ }, { /* 553 */ 66, /* DEC16r */ }, { /* 554 */ 48, /* DEC16r_alt */ }, { /* 555 */ 54, /* DEC32m */ }, { /* 556 */ 66, /* DEC32r */ }, { /* 557 */ 48, /* DEC32r_alt */ }, { /* 558 */ 54, /* DEC64m */ }, { /* 559 */ 67, /* DEC64r */ }, { /* 560 */ 54, /* DEC8m */ }, { /* 561 */ 68, /* DEC8r */ }, { /* 562 */ 54, /* DIV16m */ }, { /* 563 */ 55, /* DIV16r */ }, { /* 564 */ 54, /* DIV32m */ }, { /* 565 */ 55, /* DIV32r */ }, { /* 566 */ 54, /* DIV64m */ }, { /* 567 */ 57, /* DIV64r */ }, { /* 568 */ 54, /* DIV8m */ }, { /* 569 */ 69, /* DIV8r */ }, { /* 570 */ 0, /* ENDBR32 */ }, { /* 571 */ 0, /* ENDBR64 */ }, { /* 572 */ 70, /* ENTER */ }, { /* 573 */ 71, /* FARCALL16i */ }, { /* 574 */ 54, /* FARCALL16m */ }, { /* 575 */ 72, /* FARCALL32i */ }, { /* 576 */ 54, /* FARCALL32m */ }, { /* 577 */ 54, /* FARCALL64 */ }, { /* 578 */ 71, /* FARJMP16i */ }, { /* 579 */ 54, /* FARJMP16m */ }, { /* 580 */ 72, /* FARJMP32i */ }, { /* 581 */ 54, /* FARJMP32m */ }, { /* 582 */ 54, /* FARJMP64 */ }, { /* 583 */ 0, /* FSETPM */ }, { /* 584 */ 0, /* GETSEC */ }, { /* 585 */ 0, /* HLT */ }, { /* 586 */ 54, /* IDIV16m */ }, { /* 587 */ 55, /* IDIV16r */ }, { /* 588 */ 54, /* IDIV32m */ }, { /* 589 */ 55, /* IDIV32r */ }, { /* 590 */ 54, /* IDIV64m */ }, { /* 591 */ 57, /* IDIV64r */ }, { /* 592 */ 54, /* IDIV8m */ }, { /* 593 */ 69, /* IDIV8r */ }, { /* 594 */ 54, /* IMUL16m */ }, { /* 595 */ 55, /* IMUL16r */ }, { /* 596 */ 8, /* IMUL16rm */ }, { /* 597 */ 73, /* IMUL16rmi */ }, { /* 598 */ 74, /* IMUL16rmi8 */ }, { /* 599 */ 10, /* IMUL16rr */ }, { /* 600 */ 75, /* IMUL16rri */ }, { /* 601 */ 76, /* IMUL16rri8 */ }, { /* 602 */ 54, /* IMUL32m */ }, { /* 603 */ 55, /* IMUL32r */ }, { /* 604 */ 8, /* IMUL32rm */ }, { /* 605 */ 73, /* IMUL32rmi */ }, { /* 606 */ 74, /* IMUL32rmi8 */ }, { /* 607 */ 10, /* IMUL32rr */ }, { /* 608 */ 75, /* IMUL32rri */ }, { /* 609 */ 76, /* IMUL32rri8 */ }, { /* 610 */ 54, /* IMUL64m */ }, { /* 611 */ 57, /* IMUL64r */ }, { /* 612 */ 16, /* IMUL64rm */ }, { /* 613 */ 38, /* IMUL64rmi32 */ }, { /* 614 */ 77, /* IMUL64rmi8 */ }, { /* 615 */ 18, /* IMUL64rr */ }, { /* 616 */ 39, /* IMUL64rri32 */ }, { /* 617 */ 78, /* IMUL64rri8 */ }, { /* 618 */ 54, /* IMUL8m */ }, { /* 619 */ 69, /* IMUL8r */ }, { /* 620 */ 79, /* IN16ri */ }, { /* 621 */ 0, /* IN16rr */ }, { /* 622 */ 79, /* IN32ri */ }, { /* 623 */ 0, /* IN32rr */ }, { /* 624 */ 79, /* IN8ri */ }, { /* 625 */ 0, /* IN8rr */ }, { /* 626 */ 54, /* INC16m */ }, { /* 627 */ 66, /* INC16r */ }, { /* 628 */ 48, /* INC16r_alt */ }, { /* 629 */ 54, /* INC32m */ }, { /* 630 */ 66, /* INC32r */ }, { /* 631 */ 48, /* INC32r_alt */ }, { /* 632 */ 54, /* INC64m */ }, { /* 633 */ 67, /* INC64r */ }, { /* 634 */ 54, /* INC8m */ }, { /* 635 */ 68, /* INC8r */ }, { /* 636 */ 80, /* INCSSPD */ }, { /* 637 */ 57, /* INCSSPQ */ }, { /* 638 */ 81, /* INSB */ }, { /* 639 */ 81, /* INSL */ }, { /* 640 */ 81, /* INSW */ }, { /* 641 */ 79, /* INT */ }, { /* 642 */ 0, /* INT1 */ }, { /* 643 */ 0, /* INT3 */ }, { /* 644 */ 0, /* INTO */ }, { /* 645 */ 0, /* INVD */ }, { /* 646 */ 82, /* INVEPT32 */ }, { /* 647 */ 46, /* INVEPT64 */ }, { /* 648 */ 54, /* INVLPG */ }, { /* 649 */ 0, /* INVLPGA32 */ }, { /* 650 */ 0, /* INVLPGA64 */ }, { /* 651 */ 82, /* INVPCID32 */ }, { /* 652 */ 46, /* INVPCID64 */ }, { /* 653 */ 82, /* INVVPID32 */ }, { /* 654 */ 46, /* INVVPID64 */ }, { /* 655 */ 0, /* IRET16 */ }, { /* 656 */ 0, /* IRET32 */ }, { /* 657 */ 0, /* IRET64 */ }, { /* 658 */ 83, /* JAE_1 */ }, { /* 659 */ 84, /* JAE_2 */ }, { /* 660 */ 84, /* JAE_4 */ }, { /* 661 */ 83, /* JA_1 */ }, { /* 662 */ 84, /* JA_2 */ }, { /* 663 */ 84, /* JA_4 */ }, { /* 664 */ 83, /* JBE_1 */ }, { /* 665 */ 84, /* JBE_2 */ }, { /* 666 */ 84, /* JBE_4 */ }, { /* 667 */ 83, /* JB_1 */ }, { /* 668 */ 84, /* JB_2 */ }, { /* 669 */ 84, /* JB_4 */ }, { /* 670 */ 83, /* JCXZ */ }, { /* 671 */ 83, /* JECXZ */ }, { /* 672 */ 83, /* JE_1 */ }, { /* 673 */ 84, /* JE_2 */ }, { /* 674 */ 84, /* JE_4 */ }, { /* 675 */ 83, /* JGE_1 */ }, { /* 676 */ 84, /* JGE_2 */ }, { /* 677 */ 84, /* JGE_4 */ }, { /* 678 */ 83, /* JG_1 */ }, { /* 679 */ 84, /* JG_2 */ }, { /* 680 */ 84, /* JG_4 */ }, { /* 681 */ 83, /* JLE_1 */ }, { /* 682 */ 84, /* JLE_2 */ }, { /* 683 */ 84, /* JLE_4 */ }, { /* 684 */ 83, /* JL_1 */ }, { /* 685 */ 84, /* JL_2 */ }, { /* 686 */ 84, /* JL_4 */ }, { /* 687 */ 54, /* JMP16m */ }, { /* 688 */ 0, /* */ }, { /* 689 */ 55, /* JMP16r */ }, { /* 690 */ 0, /* */ }, { /* 691 */ 54, /* JMP32m */ }, { /* 692 */ 0, /* */ }, { /* 693 */ 55, /* JMP32r */ }, { /* 694 */ 0, /* */ }, { /* 695 */ 54, /* JMP64m */ }, { /* 696 */ 0, /* */ }, { /* 697 */ 57, /* JMP64r */ }, { /* 698 */ 0, /* */ }, { /* 699 */ 83, /* JMP_1 */ }, { /* 700 */ 84, /* JMP_2 */ }, { /* 701 */ 84, /* JMP_4 */ }, { /* 702 */ 83, /* JNE_1 */ }, { /* 703 */ 84, /* JNE_2 */ }, { /* 704 */ 84, /* JNE_4 */ }, { /* 705 */ 83, /* JNO_1 */ }, { /* 706 */ 84, /* JNO_2 */ }, { /* 707 */ 84, /* JNO_4 */ }, { /* 708 */ 83, /* JNP_1 */ }, { /* 709 */ 84, /* JNP_2 */ }, { /* 710 */ 84, /* JNP_4 */ }, { /* 711 */ 83, /* JNS_1 */ }, { /* 712 */ 84, /* JNS_2 */ }, { /* 713 */ 84, /* JNS_4 */ }, { /* 714 */ 83, /* JO_1 */ }, { /* 715 */ 84, /* JO_2 */ }, { /* 716 */ 84, /* JO_4 */ }, { /* 717 */ 83, /* JP_1 */ }, { /* 718 */ 84, /* JP_2 */ }, { /* 719 */ 84, /* JP_4 */ }, { /* 720 */ 83, /* JRCXZ */ }, { /* 721 */ 83, /* JS_1 */ }, { /* 722 */ 84, /* JS_2 */ }, { /* 723 */ 84, /* JS_4 */ }, { /* 724 */ 0, /* LAHF */ }, { /* 725 */ 44, /* LAR16rm */ }, { /* 726 */ 45, /* LAR16rr */ }, { /* 727 */ 44, /* LAR32rm */ }, { /* 728 */ 45, /* LAR32rr */ }, { /* 729 */ 46, /* LAR64rm */ }, { /* 730 */ 85, /* LAR64rr */ }, { /* 731 */ 44, /* LDS16rm */ }, { /* 732 */ 44, /* LDS32rm */ }, { /* 733 */ 44, /* LEA16r */ }, { /* 734 */ 44, /* LEA32r */ }, { /* 735 */ 44, /* LEA64_32r */ }, { /* 736 */ 46, /* LEA64r */ }, { /* 737 */ 0, /* LEAVE */ }, { /* 738 */ 0, /* LEAVE64 */ }, { /* 739 */ 44, /* LES16rm */ }, { /* 740 */ 44, /* LES32rm */ }, { /* 741 */ 44, /* LFS16rm */ }, { /* 742 */ 44, /* LFS32rm */ }, { /* 743 */ 46, /* LFS64rm */ }, { /* 744 */ 54, /* LGDT16m */ }, { /* 745 */ 54, /* LGDT32m */ }, { /* 746 */ 54, /* LGDT64m */ }, { /* 747 */ 44, /* LGS16rm */ }, { /* 748 */ 44, /* LGS32rm */ }, { /* 749 */ 46, /* LGS64rm */ }, { /* 750 */ 54, /* LIDT16m */ }, { /* 751 */ 54, /* LIDT32m */ }, { /* 752 */ 54, /* LIDT64m */ }, { /* 753 */ 54, /* LLDT16m */ }, { /* 754 */ 86, /* LLDT16r */ }, { /* 755 */ 80, /* LLWPCB */ }, { /* 756 */ 57, /* LLWPCB64 */ }, { /* 757 */ 54, /* LMSW16m */ }, { /* 758 */ 86, /* LMSW16r */ }, { /* 759 */ 0, /* LOCK_PREFIX */ }, { /* 760 */ 87, /* LODSB */ }, { /* 761 */ 87, /* LODSL */ }, { /* 762 */ 87, /* LODSQ */ }, { /* 763 */ 87, /* LODSW */ }, { /* 764 */ 83, /* LOOP */ }, { /* 765 */ 83, /* LOOPE */ }, { /* 766 */ 83, /* LOOPNE */ }, { /* 767 */ 88, /* LRETIL */ }, { /* 768 */ 88, /* LRETIQ */ }, { /* 769 */ 2, /* LRETIW */ }, { /* 770 */ 0, /* LRETL */ }, { /* 771 */ 0, /* LRETQ */ }, { /* 772 */ 0, /* LRETW */ }, { /* 773 */ 44, /* LSL16rm */ }, { /* 774 */ 45, /* LSL16rr */ }, { /* 775 */ 44, /* LSL32rm */ }, { /* 776 */ 45, /* LSL32rr */ }, { /* 777 */ 46, /* LSL64rm */ }, { /* 778 */ 85, /* LSL64rr */ }, { /* 779 */ 44, /* LSS16rm */ }, { /* 780 */ 44, /* LSS32rm */ }, { /* 781 */ 46, /* LSS64rm */ }, { /* 782 */ 54, /* LTRm */ }, { /* 783 */ 86, /* LTRr */ }, { /* 784 */ 89, /* LWPINS32rmi */ }, { /* 785 */ 90, /* LWPINS32rri */ }, { /* 786 */ 91, /* LWPINS64rmi */ }, { /* 787 */ 92, /* LWPINS64rri */ }, { /* 788 */ 89, /* LWPVAL32rmi */ }, { /* 789 */ 90, /* LWPVAL32rri */ }, { /* 790 */ 91, /* LWPVAL64rmi */ }, { /* 791 */ 92, /* LWPVAL64rri */ }, { /* 792 */ 44, /* LZCNT16rm */ }, { /* 793 */ 45, /* LZCNT16rr */ }, { /* 794 */ 44, /* LZCNT32rm */ }, { /* 795 */ 45, /* LZCNT32rr */ }, { /* 796 */ 46, /* LZCNT64rm */ }, { /* 797 */ 47, /* LZCNT64rr */ }, { /* 798 */ 0, /* MONITORXrrr */ }, { /* 799 */ 0, /* MONTMUL */ }, { /* 800 */ 93, /* MOV16ao16 */ }, { /* 801 */ 93, /* MOV16ao32 */ }, { /* 802 */ 93, /* MOV16ao64 */ }, { /* 803 */ 3, /* MOV16mi */ }, { /* 804 */ 5, /* MOV16mr */ }, { /* 805 */ 94, /* MOV16ms */ }, { /* 806 */ 93, /* MOV16o16a */ }, { /* 807 */ 93, /* MOV16o32a */ }, { /* 808 */ 93, /* MOV16o64a */ }, { /* 809 */ 95, /* MOV16ri */ }, { /* 810 */ 59, /* MOV16ri_alt */ }, { /* 811 */ 44, /* MOV16rm */ }, { /* 812 */ 51, /* MOV16rr */ }, { /* 813 */ 45, /* MOV16rr_REV */ }, { /* 814 */ 96, /* MOV16rs */ }, { /* 815 */ 97, /* MOV16sm */ }, { /* 816 */ 98, /* MOV16sr */ }, { /* 817 */ 93, /* MOV32ao16 */ }, { /* 818 */ 93, /* MOV32ao32 */ }, { /* 819 */ 93, /* MOV32ao64 */ }, { /* 820 */ 99, /* MOV32cr */ }, { /* 821 */ 100, /* MOV32dr */ }, { /* 822 */ 3, /* MOV32mi */ }, { /* 823 */ 5, /* MOV32mr */ }, { /* 824 */ 93, /* MOV32o16a */ }, { /* 825 */ 93, /* MOV32o32a */ }, { /* 826 */ 93, /* MOV32o64a */ }, { /* 827 */ 101, /* MOV32rc */ }, { /* 828 */ 102, /* MOV32rd */ }, { /* 829 */ 95, /* MOV32ri */ }, { /* 830 */ 59, /* MOV32ri_alt */ }, { /* 831 */ 44, /* MOV32rm */ }, { /* 832 */ 51, /* MOV32rr */ }, { /* 833 */ 45, /* MOV32rr_REV */ }, { /* 834 */ 96, /* MOV32rs */ }, { /* 835 */ 98, /* MOV32sr */ }, { /* 836 */ 93, /* MOV64ao32 */ }, { /* 837 */ 93, /* MOV64ao64 */ }, { /* 838 */ 103, /* MOV64cr */ }, { /* 839 */ 104, /* MOV64dr */ }, { /* 840 */ 12, /* MOV64mi32 */ }, { /* 841 */ 13, /* MOV64mr */ }, { /* 842 */ 93, /* MOV64o32a */ }, { /* 843 */ 93, /* MOV64o64a */ }, { /* 844 */ 105, /* MOV64rc */ }, { /* 845 */ 106, /* MOV64rd */ }, { /* 846 */ 107, /* MOV64ri */ }, { /* 847 */ 60, /* MOV64ri32 */ }, { /* 848 */ 46, /* MOV64rm */ }, { /* 849 */ 53, /* MOV64rr */ }, { /* 850 */ 47, /* MOV64rr_REV */ }, { /* 851 */ 108, /* MOV64rs */ }, { /* 852 */ 109, /* MOV64sr */ }, { /* 853 */ 93, /* MOV8ao16 */ }, { /* 854 */ 93, /* MOV8ao32 */ }, { /* 855 */ 93, /* MOV8ao64 */ }, { /* 856 */ 4, /* MOV8mi */ }, { /* 857 */ 19, /* MOV8mr */ }, { /* 858 */ 0, /* */ }, { /* 859 */ 93, /* MOV8o16a */ }, { /* 860 */ 93, /* MOV8o32a */ }, { /* 861 */ 93, /* MOV8o64a */ }, { /* 862 */ 110, /* MOV8ri */ }, { /* 863 */ 61, /* MOV8ri_alt */ }, { /* 864 */ 62, /* MOV8rm */ }, { /* 865 */ 0, /* */ }, { /* 866 */ 63, /* MOV8rr */ }, { /* 867 */ 0, /* */ }, { /* 868 */ 64, /* MOV8rr_REV */ }, { /* 869 */ 5, /* MOVBE16mr */ }, { /* 870 */ 44, /* MOVBE16rm */ }, { /* 871 */ 5, /* MOVBE32mr */ }, { /* 872 */ 44, /* MOVBE32rm */ }, { /* 873 */ 13, /* MOVBE64mr */ }, { /* 874 */ 46, /* MOVBE64rm */ }, { /* 875 */ 111, /* MOVDIR64B16 */ }, { /* 876 */ 82, /* MOVDIR64B32 */ }, { /* 877 */ 46, /* MOVDIR64B64 */ }, { /* 878 */ 112, /* MOVDIRI32 */ }, { /* 879 */ 13, /* MOVDIRI64 */ }, { /* 880 */ 65, /* MOVSB */ }, { /* 881 */ 65, /* MOVSL */ }, { /* 882 */ 65, /* MOVSQ */ }, { /* 883 */ 65, /* MOVSW */ }, { /* 884 */ 44, /* MOVSX16rm16 */ }, { /* 885 */ 44, /* MOVSX16rm8 */ }, { /* 886 */ 45, /* MOVSX16rr16 */ }, { /* 887 */ 113, /* MOVSX16rr8 */ }, { /* 888 */ 44, /* MOVSX32rm16 */ }, { /* 889 */ 44, /* MOVSX32rm8 */ }, { /* 890 */ 0, /* */ }, { /* 891 */ 114, /* MOVSX32rr16 */ }, { /* 892 */ 113, /* MOVSX32rr8 */ }, { /* 893 */ 0, /* */ }, { /* 894 */ 46, /* MOVSX64rm16 */ }, { /* 895 */ 46, /* MOVSX64rm32 */ }, { /* 896 */ 46, /* MOVSX64rm8 */ }, { /* 897 */ 115, /* MOVSX64rr16 */ }, { /* 898 */ 85, /* MOVSX64rr32 */ }, { /* 899 */ 116, /* MOVSX64rr8 */ }, { /* 900 */ 44, /* MOVZX16rm16 */ }, { /* 901 */ 44, /* MOVZX16rm8 */ }, { /* 902 */ 45, /* MOVZX16rr16 */ }, { /* 903 */ 113, /* MOVZX16rr8 */ }, { /* 904 */ 44, /* MOVZX32rm16 */ }, { /* 905 */ 44, /* MOVZX32rm8 */ }, { /* 906 */ 0, /* */ }, { /* 907 */ 114, /* MOVZX32rr16 */ }, { /* 908 */ 113, /* MOVZX32rr8 */ }, { /* 909 */ 0, /* */ }, { /* 910 */ 46, /* MOVZX64rm16 */ }, { /* 911 */ 46, /* MOVZX64rm8 */ }, { /* 912 */ 115, /* MOVZX64rr16 */ }, { /* 913 */ 116, /* MOVZX64rr8 */ }, { /* 914 */ 54, /* MUL16m */ }, { /* 915 */ 55, /* MUL16r */ }, { /* 916 */ 54, /* MUL32m */ }, { /* 917 */ 55, /* MUL32r */ }, { /* 918 */ 54, /* MUL64m */ }, { /* 919 */ 57, /* MUL64r */ }, { /* 920 */ 54, /* MUL8m */ }, { /* 921 */ 69, /* MUL8r */ }, { /* 922 */ 26, /* MULX32rm */ }, { /* 923 */ 27, /* MULX32rr */ }, { /* 924 */ 28, /* MULX64rm */ }, { /* 925 */ 29, /* MULX64rr */ }, { /* 926 */ 0, /* MWAITXrrr */ }, { /* 927 */ 54, /* NEG16m */ }, { /* 928 */ 66, /* NEG16r */ }, { /* 929 */ 54, /* NEG32m */ }, { /* 930 */ 66, /* NEG32r */ }, { /* 931 */ 54, /* NEG64m */ }, { /* 932 */ 67, /* NEG64r */ }, { /* 933 */ 54, /* NEG8m */ }, { /* 934 */ 68, /* NEG8r */ }, { /* 935 */ 0, /* NOOP */ }, { /* 936 */ 54, /* NOOP18_16m4 */ }, { /* 937 */ 54, /* NOOP18_16m5 */ }, { /* 938 */ 54, /* NOOP18_16m6 */ }, { /* 939 */ 54, /* NOOP18_16m7 */ }, { /* 940 */ 55, /* NOOP18_16r4 */ }, { /* 941 */ 55, /* NOOP18_16r5 */ }, { /* 942 */ 55, /* NOOP18_16r6 */ }, { /* 943 */ 55, /* NOOP18_16r7 */ }, { /* 944 */ 54, /* NOOP18_m4 */ }, { /* 945 */ 54, /* NOOP18_m5 */ }, { /* 946 */ 54, /* NOOP18_m6 */ }, { /* 947 */ 54, /* NOOP18_m7 */ }, { /* 948 */ 55, /* NOOP18_r4 */ }, { /* 949 */ 55, /* NOOP18_r5 */ }, { /* 950 */ 55, /* NOOP18_r6 */ }, { /* 951 */ 55, /* NOOP18_r7 */ }, { /* 952 */ 45, /* NOOP19rr */ }, { /* 953 */ 54, /* NOOPL */ }, { /* 954 */ 54, /* NOOPL_19 */ }, { /* 955 */ 54, /* NOOPL_1d */ }, { /* 956 */ 54, /* NOOPL_1e */ }, { /* 957 */ 55, /* NOOPLr */ }, { /* 958 */ 54, /* NOOPQ */ }, { /* 959 */ 57, /* NOOPQr */ }, { /* 960 */ 54, /* NOOPW */ }, { /* 961 */ 54, /* NOOPW_19 */ }, { /* 962 */ 54, /* NOOPW_1c */ }, { /* 963 */ 54, /* NOOPW_1d */ }, { /* 964 */ 54, /* NOOPW_1e */ }, { /* 965 */ 55, /* NOOPWr */ }, { /* 966 */ 54, /* NOT16m */ }, { /* 967 */ 66, /* NOT16r */ }, { /* 968 */ 54, /* NOT32m */ }, { /* 969 */ 66, /* NOT32r */ }, { /* 970 */ 54, /* NOT64m */ }, { /* 971 */ 67, /* NOT64r */ }, { /* 972 */ 54, /* NOT8m */ }, { /* 973 */ 68, /* NOT8r */ }, { /* 974 */ 2, /* OR16i16 */ }, { /* 975 */ 3, /* OR16mi */ }, { /* 976 */ 4, /* OR16mi8 */ }, { /* 977 */ 5, /* OR16mr */ }, { /* 978 */ 6, /* OR16ri */ }, { /* 979 */ 7, /* OR16ri8 */ }, { /* 980 */ 8, /* OR16rm */ }, { /* 981 */ 9, /* OR16rr */ }, { /* 982 */ 10, /* OR16rr_REV */ }, { /* 983 */ 2, /* OR32i32 */ }, { /* 984 */ 3, /* OR32mi */ }, { /* 985 */ 4, /* OR32mi8 */ }, { /* 986 */ 5, /* OR32mr */ }, { /* 987 */ 6, /* OR32ri */ }, { /* 988 */ 7, /* OR32ri8 */ }, { /* 989 */ 8, /* OR32rm */ }, { /* 990 */ 9, /* OR32rr */ }, { /* 991 */ 10, /* OR32rr_REV */ }, { /* 992 */ 11, /* OR64i32 */ }, { /* 993 */ 12, /* OR64mi32 */ }, { /* 994 */ 4, /* OR64mi8 */ }, { /* 995 */ 13, /* OR64mr */ }, { /* 996 */ 14, /* OR64ri32 */ }, { /* 997 */ 15, /* OR64ri8 */ }, { /* 998 */ 16, /* OR64rm */ }, { /* 999 */ 17, /* OR64rr */ }, { /* 1000 */ 18, /* OR64rr_REV */ }, { /* 1001 */ 1, /* OR8i8 */ }, { /* 1002 */ 4, /* OR8mi */ }, { /* 1003 */ 4, /* OR8mi8 */ }, { /* 1004 */ 19, /* OR8mr */ }, { /* 1005 */ 20, /* OR8ri */ }, { /* 1006 */ 20, /* OR8ri8 */ }, { /* 1007 */ 21, /* OR8rm */ }, { /* 1008 */ 22, /* OR8rr */ }, { /* 1009 */ 23, /* OR8rr_REV */ }, { /* 1010 */ 79, /* OUT16ir */ }, { /* 1011 */ 0, /* OUT16rr */ }, { /* 1012 */ 79, /* OUT32ir */ }, { /* 1013 */ 0, /* OUT32rr */ }, { /* 1014 */ 79, /* OUT8ir */ }, { /* 1015 */ 0, /* OUT8rr */ }, { /* 1016 */ 87, /* OUTSB */ }, { /* 1017 */ 87, /* OUTSL */ }, { /* 1018 */ 87, /* OUTSW */ }, { /* 1019 */ 0, /* PCONFIG */ }, { /* 1020 */ 26, /* PDEP32rm */ }, { /* 1021 */ 27, /* PDEP32rr */ }, { /* 1022 */ 28, /* PDEP64rm */ }, { /* 1023 */ 29, /* PDEP64rr */ }, { /* 1024 */ 26, /* PEXT32rm */ }, { /* 1025 */ 27, /* PEXT32rr */ }, { /* 1026 */ 28, /* PEXT64rm */ }, { /* 1027 */ 29, /* PEXT64rr */ }, { /* 1028 */ 117, /* POP16r */ }, { /* 1029 */ 54, /* POP16rmm */ }, { /* 1030 */ 55, /* POP16rmr */ }, { /* 1031 */ 117, /* POP32r */ }, { /* 1032 */ 54, /* POP32rmm */ }, { /* 1033 */ 55, /* POP32rmr */ }, { /* 1034 */ 118, /* POP64r */ }, { /* 1035 */ 54, /* POP64rmm */ }, { /* 1036 */ 57, /* POP64rmr */ }, { /* 1037 */ 0, /* POPA16 */ }, { /* 1038 */ 0, /* POPA32 */ }, { /* 1039 */ 0, /* POPDS16 */ }, { /* 1040 */ 0, /* POPDS32 */ }, { /* 1041 */ 0, /* POPES16 */ }, { /* 1042 */ 0, /* POPES32 */ }, { /* 1043 */ 0, /* POPF16 */ }, { /* 1044 */ 0, /* POPF32 */ }, { /* 1045 */ 0, /* POPF64 */ }, { /* 1046 */ 0, /* POPFS16 */ }, { /* 1047 */ 0, /* POPFS32 */ }, { /* 1048 */ 0, /* POPFS64 */ }, { /* 1049 */ 0, /* POPGS16 */ }, { /* 1050 */ 0, /* POPGS32 */ }, { /* 1051 */ 0, /* POPGS64 */ }, { /* 1052 */ 0, /* POPSS16 */ }, { /* 1053 */ 0, /* POPSS32 */ }, { /* 1054 */ 54, /* PTWRITE64m */ }, { /* 1055 */ 57, /* PTWRITE64r */ }, { /* 1056 */ 54, /* PTWRITEm */ }, { /* 1057 */ 80, /* PTWRITEr */ }, { /* 1058 */ 1, /* PUSH16i8 */ }, { /* 1059 */ 117, /* PUSH16r */ }, { /* 1060 */ 54, /* PUSH16rmm */ }, { /* 1061 */ 55, /* PUSH16rmr */ }, { /* 1062 */ 1, /* PUSH32i8 */ }, { /* 1063 */ 117, /* PUSH32r */ }, { /* 1064 */ 54, /* PUSH32rmm */ }, { /* 1065 */ 55, /* PUSH32rmr */ }, { /* 1066 */ 11, /* PUSH64i32 */ }, { /* 1067 */ 1, /* PUSH64i8 */ }, { /* 1068 */ 118, /* PUSH64r */ }, { /* 1069 */ 54, /* PUSH64rmm */ }, { /* 1070 */ 57, /* PUSH64rmr */ }, { /* 1071 */ 0, /* PUSHA16 */ }, { /* 1072 */ 0, /* PUSHA32 */ }, { /* 1073 */ 0, /* PUSHCS16 */ }, { /* 1074 */ 0, /* PUSHCS32 */ }, { /* 1075 */ 0, /* PUSHDS16 */ }, { /* 1076 */ 0, /* PUSHDS32 */ }, { /* 1077 */ 0, /* PUSHES16 */ }, { /* 1078 */ 0, /* PUSHES32 */ }, { /* 1079 */ 0, /* PUSHF16 */ }, { /* 1080 */ 0, /* PUSHF32 */ }, { /* 1081 */ 0, /* PUSHF64 */ }, { /* 1082 */ 0, /* PUSHFS16 */ }, { /* 1083 */ 0, /* PUSHFS32 */ }, { /* 1084 */ 0, /* PUSHFS64 */ }, { /* 1085 */ 0, /* PUSHGS16 */ }, { /* 1086 */ 0, /* PUSHGS32 */ }, { /* 1087 */ 0, /* PUSHGS64 */ }, { /* 1088 */ 0, /* PUSHSS16 */ }, { /* 1089 */ 0, /* PUSHSS32 */ }, { /* 1090 */ 2, /* PUSHi16 */ }, { /* 1091 */ 2, /* PUSHi32 */ }, { /* 1092 */ 54, /* RCL16m1 */ }, { /* 1093 */ 54, /* RCL16mCL */ }, { /* 1094 */ 119, /* RCL16mi */ }, { /* 1095 */ 66, /* RCL16r1 */ }, { /* 1096 */ 66, /* RCL16rCL */ }, { /* 1097 */ 120, /* RCL16ri */ }, { /* 1098 */ 54, /* RCL32m1 */ }, { /* 1099 */ 54, /* RCL32mCL */ }, { /* 1100 */ 119, /* RCL32mi */ }, { /* 1101 */ 66, /* RCL32r1 */ }, { /* 1102 */ 66, /* RCL32rCL */ }, { /* 1103 */ 120, /* RCL32ri */ }, { /* 1104 */ 54, /* RCL64m1 */ }, { /* 1105 */ 54, /* RCL64mCL */ }, { /* 1106 */ 119, /* RCL64mi */ }, { /* 1107 */ 67, /* RCL64r1 */ }, { /* 1108 */ 67, /* RCL64rCL */ }, { /* 1109 */ 121, /* RCL64ri */ }, { /* 1110 */ 54, /* RCL8m1 */ }, { /* 1111 */ 54, /* RCL8mCL */ }, { /* 1112 */ 119, /* RCL8mi */ }, { /* 1113 */ 68, /* RCL8r1 */ }, { /* 1114 */ 68, /* RCL8rCL */ }, { /* 1115 */ 122, /* RCL8ri */ }, { /* 1116 */ 54, /* RCR16m1 */ }, { /* 1117 */ 54, /* RCR16mCL */ }, { /* 1118 */ 119, /* RCR16mi */ }, { /* 1119 */ 66, /* RCR16r1 */ }, { /* 1120 */ 66, /* RCR16rCL */ }, { /* 1121 */ 120, /* RCR16ri */ }, { /* 1122 */ 54, /* RCR32m1 */ }, { /* 1123 */ 54, /* RCR32mCL */ }, { /* 1124 */ 119, /* RCR32mi */ }, { /* 1125 */ 66, /* RCR32r1 */ }, { /* 1126 */ 66, /* RCR32rCL */ }, { /* 1127 */ 120, /* RCR32ri */ }, { /* 1128 */ 54, /* RCR64m1 */ }, { /* 1129 */ 54, /* RCR64mCL */ }, { /* 1130 */ 119, /* RCR64mi */ }, { /* 1131 */ 67, /* RCR64r1 */ }, { /* 1132 */ 67, /* RCR64rCL */ }, { /* 1133 */ 121, /* RCR64ri */ }, { /* 1134 */ 54, /* RCR8m1 */ }, { /* 1135 */ 54, /* RCR8mCL */ }, { /* 1136 */ 119, /* RCR8mi */ }, { /* 1137 */ 68, /* RCR8r1 */ }, { /* 1138 */ 68, /* RCR8rCL */ }, { /* 1139 */ 122, /* RCR8ri */ }, { /* 1140 */ 80, /* RDFSBASE */ }, { /* 1141 */ 57, /* RDFSBASE64 */ }, { /* 1142 */ 80, /* RDGSBASE */ }, { /* 1143 */ 57, /* RDGSBASE64 */ }, { /* 1144 */ 0, /* RDMSR */ }, { /* 1145 */ 80, /* RDPID32 */ }, { /* 1146 */ 57, /* RDPID64 */ }, { /* 1147 */ 0, /* RDPKRUr */ }, { /* 1148 */ 0, /* RDPMC */ }, { /* 1149 */ 55, /* RDRAND16r */ }, { /* 1150 */ 55, /* RDRAND32r */ }, { /* 1151 */ 57, /* RDRAND64r */ }, { /* 1152 */ 55, /* RDSEED16r */ }, { /* 1153 */ 55, /* RDSEED32r */ }, { /* 1154 */ 57, /* RDSEED64r */ }, { /* 1155 */ 123, /* RDSSPD */ }, { /* 1156 */ 67, /* RDSSPQ */ }, { /* 1157 */ 0, /* RDTSC */ }, { /* 1158 */ 0, /* RDTSCP */ }, { /* 1159 */ 0, /* REPNE_PREFIX */ }, { /* 1160 */ 0, /* REP_PREFIX */ }, { /* 1161 */ 88, /* RETIL */ }, { /* 1162 */ 88, /* RETIQ */ }, { /* 1163 */ 2, /* RETIW */ }, { /* 1164 */ 0, /* RETL */ }, { /* 1165 */ 0, /* RETQ */ }, { /* 1166 */ 0, /* RETW */ }, { /* 1167 */ 0, /* REX64_PREFIX */ }, { /* 1168 */ 54, /* ROL16m1 */ }, { /* 1169 */ 54, /* ROL16mCL */ }, { /* 1170 */ 119, /* ROL16mi */ }, { /* 1171 */ 66, /* ROL16r1 */ }, { /* 1172 */ 66, /* ROL16rCL */ }, { /* 1173 */ 120, /* ROL16ri */ }, { /* 1174 */ 54, /* ROL32m1 */ }, { /* 1175 */ 54, /* ROL32mCL */ }, { /* 1176 */ 119, /* ROL32mi */ }, { /* 1177 */ 66, /* ROL32r1 */ }, { /* 1178 */ 66, /* ROL32rCL */ }, { /* 1179 */ 120, /* ROL32ri */ }, { /* 1180 */ 54, /* ROL64m1 */ }, { /* 1181 */ 54, /* ROL64mCL */ }, { /* 1182 */ 119, /* ROL64mi */ }, { /* 1183 */ 67, /* ROL64r1 */ }, { /* 1184 */ 67, /* ROL64rCL */ }, { /* 1185 */ 121, /* ROL64ri */ }, { /* 1186 */ 54, /* ROL8m1 */ }, { /* 1187 */ 54, /* ROL8mCL */ }, { /* 1188 */ 119, /* ROL8mi */ }, { /* 1189 */ 68, /* ROL8r1 */ }, { /* 1190 */ 68, /* ROL8rCL */ }, { /* 1191 */ 122, /* ROL8ri */ }, { /* 1192 */ 54, /* ROR16m1 */ }, { /* 1193 */ 54, /* ROR16mCL */ }, { /* 1194 */ 119, /* ROR16mi */ }, { /* 1195 */ 66, /* ROR16r1 */ }, { /* 1196 */ 66, /* ROR16rCL */ }, { /* 1197 */ 120, /* ROR16ri */ }, { /* 1198 */ 54, /* ROR32m1 */ }, { /* 1199 */ 54, /* ROR32mCL */ }, { /* 1200 */ 119, /* ROR32mi */ }, { /* 1201 */ 66, /* ROR32r1 */ }, { /* 1202 */ 66, /* ROR32rCL */ }, { /* 1203 */ 120, /* ROR32ri */ }, { /* 1204 */ 54, /* ROR64m1 */ }, { /* 1205 */ 54, /* ROR64mCL */ }, { /* 1206 */ 119, /* ROR64mi */ }, { /* 1207 */ 67, /* ROR64r1 */ }, { /* 1208 */ 67, /* ROR64rCL */ }, { /* 1209 */ 121, /* ROR64ri */ }, { /* 1210 */ 54, /* ROR8m1 */ }, { /* 1211 */ 54, /* ROR8mCL */ }, { /* 1212 */ 119, /* ROR8mi */ }, { /* 1213 */ 68, /* ROR8r1 */ }, { /* 1214 */ 68, /* ROR8rCL */ }, { /* 1215 */ 122, /* ROR8ri */ }, { /* 1216 */ 124, /* RORX32mi */ }, { /* 1217 */ 125, /* RORX32ri */ }, { /* 1218 */ 126, /* RORX64mi */ }, { /* 1219 */ 127, /* RORX64ri */ }, { /* 1220 */ 0, /* RSM */ }, { /* 1221 */ 54, /* RSTORSSP */ }, { /* 1222 */ 0, /* SAHF */ }, { /* 1223 */ 54, /* SAL16m1 */ }, { /* 1224 */ 54, /* SAL16mCL */ }, { /* 1225 */ 4, /* SAL16mi */ }, { /* 1226 */ 66, /* SAL16r1 */ }, { /* 1227 */ 66, /* SAL16rCL */ }, { /* 1228 */ 7, /* SAL16ri */ }, { /* 1229 */ 54, /* SAL32m1 */ }, { /* 1230 */ 54, /* SAL32mCL */ }, { /* 1231 */ 4, /* SAL32mi */ }, { /* 1232 */ 66, /* SAL32r1 */ }, { /* 1233 */ 66, /* SAL32rCL */ }, { /* 1234 */ 7, /* SAL32ri */ }, { /* 1235 */ 54, /* SAL64m1 */ }, { /* 1236 */ 54, /* SAL64mCL */ }, { /* 1237 */ 4, /* SAL64mi */ }, { /* 1238 */ 67, /* SAL64r1 */ }, { /* 1239 */ 67, /* SAL64rCL */ }, { /* 1240 */ 15, /* SAL64ri */ }, { /* 1241 */ 54, /* SAL8m1 */ }, { /* 1242 */ 54, /* SAL8mCL */ }, { /* 1243 */ 4, /* SAL8mi */ }, { /* 1244 */ 68, /* SAL8r1 */ }, { /* 1245 */ 68, /* SAL8rCL */ }, { /* 1246 */ 20, /* SAL8ri */ }, { /* 1247 */ 0, /* SALC */ }, { /* 1248 */ 54, /* SAR16m1 */ }, { /* 1249 */ 54, /* SAR16mCL */ }, { /* 1250 */ 119, /* SAR16mi */ }, { /* 1251 */ 66, /* SAR16r1 */ }, { /* 1252 */ 66, /* SAR16rCL */ }, { /* 1253 */ 120, /* SAR16ri */ }, { /* 1254 */ 54, /* SAR32m1 */ }, { /* 1255 */ 54, /* SAR32mCL */ }, { /* 1256 */ 119, /* SAR32mi */ }, { /* 1257 */ 66, /* SAR32r1 */ }, { /* 1258 */ 66, /* SAR32rCL */ }, { /* 1259 */ 120, /* SAR32ri */ }, { /* 1260 */ 54, /* SAR64m1 */ }, { /* 1261 */ 54, /* SAR64mCL */ }, { /* 1262 */ 119, /* SAR64mi */ }, { /* 1263 */ 67, /* SAR64r1 */ }, { /* 1264 */ 67, /* SAR64rCL */ }, { /* 1265 */ 121, /* SAR64ri */ }, { /* 1266 */ 54, /* SAR8m1 */ }, { /* 1267 */ 54, /* SAR8mCL */ }, { /* 1268 */ 119, /* SAR8mi */ }, { /* 1269 */ 68, /* SAR8r1 */ }, { /* 1270 */ 68, /* SAR8rCL */ }, { /* 1271 */ 122, /* SAR8ri */ }, { /* 1272 */ 32, /* SARX32rm */ }, { /* 1273 */ 33, /* SARX32rr */ }, { /* 1274 */ 34, /* SARX64rm */ }, { /* 1275 */ 35, /* SARX64rr */ }, { /* 1276 */ 0, /* SAVEPREVSSP */ }, { /* 1277 */ 2, /* SBB16i16 */ }, { /* 1278 */ 3, /* SBB16mi */ }, { /* 1279 */ 4, /* SBB16mi8 */ }, { /* 1280 */ 5, /* SBB16mr */ }, { /* 1281 */ 6, /* SBB16ri */ }, { /* 1282 */ 7, /* SBB16ri8 */ }, { /* 1283 */ 8, /* SBB16rm */ }, { /* 1284 */ 9, /* SBB16rr */ }, { /* 1285 */ 10, /* SBB16rr_REV */ }, { /* 1286 */ 2, /* SBB32i32 */ }, { /* 1287 */ 3, /* SBB32mi */ }, { /* 1288 */ 4, /* SBB32mi8 */ }, { /* 1289 */ 5, /* SBB32mr */ }, { /* 1290 */ 6, /* SBB32ri */ }, { /* 1291 */ 7, /* SBB32ri8 */ }, { /* 1292 */ 8, /* SBB32rm */ }, { /* 1293 */ 9, /* SBB32rr */ }, { /* 1294 */ 10, /* SBB32rr_REV */ }, { /* 1295 */ 11, /* SBB64i32 */ }, { /* 1296 */ 12, /* SBB64mi32 */ }, { /* 1297 */ 4, /* SBB64mi8 */ }, { /* 1298 */ 13, /* SBB64mr */ }, { /* 1299 */ 14, /* SBB64ri32 */ }, { /* 1300 */ 15, /* SBB64ri8 */ }, { /* 1301 */ 16, /* SBB64rm */ }, { /* 1302 */ 17, /* SBB64rr */ }, { /* 1303 */ 18, /* SBB64rr_REV */ }, { /* 1304 */ 1, /* SBB8i8 */ }, { /* 1305 */ 4, /* SBB8mi */ }, { /* 1306 */ 4, /* SBB8mi8 */ }, { /* 1307 */ 19, /* SBB8mr */ }, { /* 1308 */ 20, /* SBB8ri */ }, { /* 1309 */ 20, /* SBB8ri8 */ }, { /* 1310 */ 21, /* SBB8rm */ }, { /* 1311 */ 22, /* SBB8rr */ }, { /* 1312 */ 23, /* SBB8rr_REV */ }, { /* 1313 */ 81, /* SCASB */ }, { /* 1314 */ 81, /* SCASL */ }, { /* 1315 */ 81, /* SCASQ */ }, { /* 1316 */ 81, /* SCASW */ }, { /* 1317 */ 54, /* SETAEm */ }, { /* 1318 */ 69, /* SETAEr */ }, { /* 1319 */ 54, /* SETAm */ }, { /* 1320 */ 69, /* SETAr */ }, { /* 1321 */ 54, /* SETBEm */ }, { /* 1322 */ 69, /* SETBEr */ }, { /* 1323 */ 54, /* SETBm */ }, { /* 1324 */ 69, /* SETBr */ }, { /* 1325 */ 54, /* SETEm */ }, { /* 1326 */ 69, /* SETEr */ }, { /* 1327 */ 54, /* SETGEm */ }, { /* 1328 */ 69, /* SETGEr */ }, { /* 1329 */ 54, /* SETGm */ }, { /* 1330 */ 69, /* SETGr */ }, { /* 1331 */ 54, /* SETLEm */ }, { /* 1332 */ 69, /* SETLEr */ }, { /* 1333 */ 54, /* SETLm */ }, { /* 1334 */ 69, /* SETLr */ }, { /* 1335 */ 54, /* SETNEm */ }, { /* 1336 */ 69, /* SETNEr */ }, { /* 1337 */ 54, /* SETNOm */ }, { /* 1338 */ 69, /* SETNOr */ }, { /* 1339 */ 54, /* SETNPm */ }, { /* 1340 */ 69, /* SETNPr */ }, { /* 1341 */ 54, /* SETNSm */ }, { /* 1342 */ 69, /* SETNSr */ }, { /* 1343 */ 54, /* SETOm */ }, { /* 1344 */ 69, /* SETOr */ }, { /* 1345 */ 54, /* SETPm */ }, { /* 1346 */ 69, /* SETPr */ }, { /* 1347 */ 0, /* SETSSBSY */ }, { /* 1348 */ 54, /* SETSm */ }, { /* 1349 */ 69, /* SETSr */ }, { /* 1350 */ 54, /* SGDT16m */ }, { /* 1351 */ 54, /* SGDT32m */ }, { /* 1352 */ 54, /* SGDT64m */ }, { /* 1353 */ 54, /* SHL16m1 */ }, { /* 1354 */ 54, /* SHL16mCL */ }, { /* 1355 */ 119, /* SHL16mi */ }, { /* 1356 */ 66, /* SHL16r1 */ }, { /* 1357 */ 66, /* SHL16rCL */ }, { /* 1358 */ 120, /* SHL16ri */ }, { /* 1359 */ 54, /* SHL32m1 */ }, { /* 1360 */ 54, /* SHL32mCL */ }, { /* 1361 */ 119, /* SHL32mi */ }, { /* 1362 */ 66, /* SHL32r1 */ }, { /* 1363 */ 66, /* SHL32rCL */ }, { /* 1364 */ 120, /* SHL32ri */ }, { /* 1365 */ 54, /* SHL64m1 */ }, { /* 1366 */ 54, /* SHL64mCL */ }, { /* 1367 */ 119, /* SHL64mi */ }, { /* 1368 */ 67, /* SHL64r1 */ }, { /* 1369 */ 67, /* SHL64rCL */ }, { /* 1370 */ 121, /* SHL64ri */ }, { /* 1371 */ 54, /* SHL8m1 */ }, { /* 1372 */ 54, /* SHL8mCL */ }, { /* 1373 */ 119, /* SHL8mi */ }, { /* 1374 */ 68, /* SHL8r1 */ }, { /* 1375 */ 68, /* SHL8rCL */ }, { /* 1376 */ 122, /* SHL8ri */ }, { /* 1377 */ 5, /* SHLD16mrCL */ }, { /* 1378 */ 128, /* SHLD16mri8 */ }, { /* 1379 */ 9, /* SHLD16rrCL */ }, { /* 1380 */ 129, /* SHLD16rri8 */ }, { /* 1381 */ 5, /* SHLD32mrCL */ }, { /* 1382 */ 128, /* SHLD32mri8 */ }, { /* 1383 */ 9, /* SHLD32rrCL */ }, { /* 1384 */ 129, /* SHLD32rri8 */ }, { /* 1385 */ 13, /* SHLD64mrCL */ }, { /* 1386 */ 130, /* SHLD64mri8 */ }, { /* 1387 */ 17, /* SHLD64rrCL */ }, { /* 1388 */ 131, /* SHLD64rri8 */ }, { /* 1389 */ 32, /* SHLX32rm */ }, { /* 1390 */ 33, /* SHLX32rr */ }, { /* 1391 */ 34, /* SHLX64rm */ }, { /* 1392 */ 35, /* SHLX64rr */ }, { /* 1393 */ 54, /* SHR16m1 */ }, { /* 1394 */ 54, /* SHR16mCL */ }, { /* 1395 */ 119, /* SHR16mi */ }, { /* 1396 */ 66, /* SHR16r1 */ }, { /* 1397 */ 66, /* SHR16rCL */ }, { /* 1398 */ 120, /* SHR16ri */ }, { /* 1399 */ 54, /* SHR32m1 */ }, { /* 1400 */ 54, /* SHR32mCL */ }, { /* 1401 */ 119, /* SHR32mi */ }, { /* 1402 */ 66, /* SHR32r1 */ }, { /* 1403 */ 66, /* SHR32rCL */ }, { /* 1404 */ 120, /* SHR32ri */ }, { /* 1405 */ 54, /* SHR64m1 */ }, { /* 1406 */ 54, /* SHR64mCL */ }, { /* 1407 */ 119, /* SHR64mi */ }, { /* 1408 */ 67, /* SHR64r1 */ }, { /* 1409 */ 67, /* SHR64rCL */ }, { /* 1410 */ 121, /* SHR64ri */ }, { /* 1411 */ 54, /* SHR8m1 */ }, { /* 1412 */ 54, /* SHR8mCL */ }, { /* 1413 */ 119, /* SHR8mi */ }, { /* 1414 */ 68, /* SHR8r1 */ }, { /* 1415 */ 68, /* SHR8rCL */ }, { /* 1416 */ 122, /* SHR8ri */ }, { /* 1417 */ 5, /* SHRD16mrCL */ }, { /* 1418 */ 128, /* SHRD16mri8 */ }, { /* 1419 */ 9, /* SHRD16rrCL */ }, { /* 1420 */ 129, /* SHRD16rri8 */ }, { /* 1421 */ 5, /* SHRD32mrCL */ }, { /* 1422 */ 128, /* SHRD32mri8 */ }, { /* 1423 */ 9, /* SHRD32rrCL */ }, { /* 1424 */ 129, /* SHRD32rri8 */ }, { /* 1425 */ 13, /* SHRD64mrCL */ }, { /* 1426 */ 130, /* SHRD64mri8 */ }, { /* 1427 */ 17, /* SHRD64rrCL */ }, { /* 1428 */ 131, /* SHRD64rri8 */ }, { /* 1429 */ 32, /* SHRX32rm */ }, { /* 1430 */ 33, /* SHRX32rr */ }, { /* 1431 */ 34, /* SHRX64rm */ }, { /* 1432 */ 35, /* SHRX64rr */ }, { /* 1433 */ 54, /* SIDT16m */ }, { /* 1434 */ 54, /* SIDT32m */ }, { /* 1435 */ 54, /* SIDT64m */ }, { /* 1436 */ 0, /* SKINIT */ }, { /* 1437 */ 54, /* SLDT16m */ }, { /* 1438 */ 55, /* SLDT16r */ }, { /* 1439 */ 55, /* SLDT32r */ }, { /* 1440 */ 57, /* SLDT64r */ }, { /* 1441 */ 80, /* SLWPCB */ }, { /* 1442 */ 57, /* SLWPCB64 */ }, { /* 1443 */ 54, /* SMSW16m */ }, { /* 1444 */ 55, /* SMSW16r */ }, { /* 1445 */ 55, /* SMSW32r */ }, { /* 1446 */ 57, /* SMSW64r */ }, { /* 1447 */ 0, /* STAC */ }, { /* 1448 */ 0, /* STC */ }, { /* 1449 */ 0, /* STD */ }, { /* 1450 */ 0, /* STGI */ }, { /* 1451 */ 0, /* STI */ }, { /* 1452 */ 81, /* STOSB */ }, { /* 1453 */ 81, /* STOSL */ }, { /* 1454 */ 81, /* STOSQ */ }, { /* 1455 */ 81, /* STOSW */ }, { /* 1456 */ 55, /* STR16r */ }, { /* 1457 */ 55, /* STR32r */ }, { /* 1458 */ 57, /* STR64r */ }, { /* 1459 */ 54, /* STRm */ }, { /* 1460 */ 2, /* SUB16i16 */ }, { /* 1461 */ 3, /* SUB16mi */ }, { /* 1462 */ 4, /* SUB16mi8 */ }, { /* 1463 */ 5, /* SUB16mr */ }, { /* 1464 */ 6, /* SUB16ri */ }, { /* 1465 */ 7, /* SUB16ri8 */ }, { /* 1466 */ 8, /* SUB16rm */ }, { /* 1467 */ 9, /* SUB16rr */ }, { /* 1468 */ 10, /* SUB16rr_REV */ }, { /* 1469 */ 2, /* SUB32i32 */ }, { /* 1470 */ 3, /* SUB32mi */ }, { /* 1471 */ 4, /* SUB32mi8 */ }, { /* 1472 */ 5, /* SUB32mr */ }, { /* 1473 */ 6, /* SUB32ri */ }, { /* 1474 */ 7, /* SUB32ri8 */ }, { /* 1475 */ 8, /* SUB32rm */ }, { /* 1476 */ 9, /* SUB32rr */ }, { /* 1477 */ 10, /* SUB32rr_REV */ }, { /* 1478 */ 11, /* SUB64i32 */ }, { /* 1479 */ 12, /* SUB64mi32 */ }, { /* 1480 */ 4, /* SUB64mi8 */ }, { /* 1481 */ 13, /* SUB64mr */ }, { /* 1482 */ 14, /* SUB64ri32 */ }, { /* 1483 */ 15, /* SUB64ri8 */ }, { /* 1484 */ 16, /* SUB64rm */ }, { /* 1485 */ 17, /* SUB64rr */ }, { /* 1486 */ 18, /* SUB64rr_REV */ }, { /* 1487 */ 1, /* SUB8i8 */ }, { /* 1488 */ 4, /* SUB8mi */ }, { /* 1489 */ 4, /* SUB8mi8 */ }, { /* 1490 */ 19, /* SUB8mr */ }, { /* 1491 */ 20, /* SUB8ri */ }, { /* 1492 */ 20, /* SUB8ri8 */ }, { /* 1493 */ 21, /* SUB8rm */ }, { /* 1494 */ 22, /* SUB8rr */ }, { /* 1495 */ 23, /* SUB8rr_REV */ }, { /* 1496 */ 0, /* SWAPGS */ }, { /* 1497 */ 0, /* SYSCALL */ }, { /* 1498 */ 0, /* SYSENTER */ }, { /* 1499 */ 0, /* SYSEXIT */ }, { /* 1500 */ 0, /* SYSEXIT64 */ }, { /* 1501 */ 0, /* SYSRET */ }, { /* 1502 */ 0, /* SYSRET64 */ }, { /* 1503 */ 40, /* T1MSKC32rm */ }, { /* 1504 */ 41, /* T1MSKC32rr */ }, { /* 1505 */ 42, /* T1MSKC64rm */ }, { /* 1506 */ 43, /* T1MSKC64rr */ }, { /* 1507 */ 2, /* TEST16i16 */ }, { /* 1508 */ 3, /* TEST16mi */ }, { /* 1509 */ 3, /* TEST16mi_alt */ }, { /* 1510 */ 5, /* TEST16mr */ }, { /* 1511 */ 59, /* TEST16ri */ }, { /* 1512 */ 59, /* TEST16ri_alt */ }, { /* 1513 */ 51, /* TEST16rr */ }, { /* 1514 */ 2, /* TEST32i32 */ }, { /* 1515 */ 3, /* TEST32mi */ }, { /* 1516 */ 3, /* TEST32mi_alt */ }, { /* 1517 */ 5, /* TEST32mr */ }, { /* 1518 */ 59, /* TEST32ri */ }, { /* 1519 */ 59, /* TEST32ri_alt */ }, { /* 1520 */ 51, /* TEST32rr */ }, { /* 1521 */ 11, /* TEST64i32 */ }, { /* 1522 */ 12, /* TEST64mi32 */ }, { /* 1523 */ 12, /* TEST64mi32_alt */ }, { /* 1524 */ 13, /* TEST64mr */ }, { /* 1525 */ 60, /* TEST64ri32 */ }, { /* 1526 */ 60, /* TEST64ri32_alt */ }, { /* 1527 */ 53, /* TEST64rr */ }, { /* 1528 */ 1, /* TEST8i8 */ }, { /* 1529 */ 4, /* TEST8mi */ }, { /* 1530 */ 4, /* TEST8mi_alt */ }, { /* 1531 */ 19, /* TEST8mr */ }, { /* 1532 */ 61, /* TEST8ri */ }, { /* 1533 */ 61, /* TEST8ri_alt */ }, { /* 1534 */ 63, /* TEST8rr */ }, { /* 1535 */ 80, /* TPAUSE */ }, { /* 1536 */ 44, /* TZCNT16rm */ }, { /* 1537 */ 45, /* TZCNT16rr */ }, { /* 1538 */ 44, /* TZCNT32rm */ }, { /* 1539 */ 45, /* TZCNT32rr */ }, { /* 1540 */ 46, /* TZCNT64rm */ }, { /* 1541 */ 47, /* TZCNT64rr */ }, { /* 1542 */ 40, /* TZMSK32rm */ }, { /* 1543 */ 41, /* TZMSK32rr */ }, { /* 1544 */ 42, /* TZMSK64rm */ }, { /* 1545 */ 43, /* TZMSK64rr */ }, { /* 1546 */ 0, /* UD0 */ }, { /* 1547 */ 0, /* UD1 */ }, { /* 1548 */ 0, /* UD2 */ }, { /* 1549 */ 86, /* UMONITOR16 */ }, { /* 1550 */ 80, /* UMONITOR32 */ }, { /* 1551 */ 57, /* UMONITOR64 */ }, { /* 1552 */ 80, /* UMWAIT */ }, { /* 1553 */ 54, /* VERRm */ }, { /* 1554 */ 86, /* VERRr */ }, { /* 1555 */ 54, /* VERWm */ }, { /* 1556 */ 86, /* VERWr */ }, { /* 1557 */ 0, /* VMCALL */ }, { /* 1558 */ 54, /* VMCLEARm */ }, { /* 1559 */ 0, /* VMFUNC */ }, { /* 1560 */ 0, /* VMLAUNCH */ }, { /* 1561 */ 0, /* VMLOAD32 */ }, { /* 1562 */ 0, /* VMLOAD64 */ }, { /* 1563 */ 0, /* VMMCALL */ }, { /* 1564 */ 54, /* VMPTRLDm */ }, { /* 1565 */ 54, /* VMPTRSTm */ }, { /* 1566 */ 112, /* VMREAD32mr */ }, { /* 1567 */ 132, /* VMREAD32rr */ }, { /* 1568 */ 13, /* VMREAD64mr */ }, { /* 1569 */ 53, /* VMREAD64rr */ }, { /* 1570 */ 0, /* VMRESUME */ }, { /* 1571 */ 0, /* VMRUN32 */ }, { /* 1572 */ 0, /* VMRUN64 */ }, { /* 1573 */ 0, /* VMSAVE32 */ }, { /* 1574 */ 0, /* VMSAVE64 */ }, { /* 1575 */ 82, /* VMWRITE32rm */ }, { /* 1576 */ 133, /* VMWRITE32rr */ }, { /* 1577 */ 46, /* VMWRITE64rm */ }, { /* 1578 */ 47, /* VMWRITE64rr */ }, { /* 1579 */ 0, /* VMXOFF */ }, { /* 1580 */ 54, /* VMXON */ }, { /* 1581 */ 0, /* WBINVD */ }, { /* 1582 */ 0, /* WBNOINVD */ }, { /* 1583 */ 80, /* WRFSBASE */ }, { /* 1584 */ 57, /* WRFSBASE64 */ }, { /* 1585 */ 80, /* WRGSBASE */ }, { /* 1586 */ 57, /* WRGSBASE64 */ }, { /* 1587 */ 0, /* WRMSR */ }, { /* 1588 */ 0, /* WRPKRUr */ }, { /* 1589 */ 112, /* WRSSD */ }, { /* 1590 */ 13, /* WRSSQ */ }, { /* 1591 */ 112, /* WRUSSD */ }, { /* 1592 */ 13, /* WRUSSQ */ }, { /* 1593 */ 8, /* XADD16rm */ }, { /* 1594 */ 134, /* XADD16rr */ }, { /* 1595 */ 8, /* XADD32rm */ }, { /* 1596 */ 134, /* XADD32rr */ }, { /* 1597 */ 16, /* XADD64rm */ }, { /* 1598 */ 135, /* XADD64rr */ }, { /* 1599 */ 21, /* XADD8rm */ }, { /* 1600 */ 136, /* XADD8rr */ }, { /* 1601 */ 48, /* XCHG16ar */ }, { /* 1602 */ 8, /* XCHG16rm */ }, { /* 1603 */ 137, /* XCHG16rr */ }, { /* 1604 */ 48, /* XCHG32ar */ }, { /* 1605 */ 8, /* XCHG32rm */ }, { /* 1606 */ 137, /* XCHG32rr */ }, { /* 1607 */ 49, /* XCHG64ar */ }, { /* 1608 */ 16, /* XCHG64rm */ }, { /* 1609 */ 138, /* XCHG64rr */ }, { /* 1610 */ 21, /* XCHG8rm */ }, { /* 1611 */ 139, /* XCHG8rr */ }, { /* 1612 */ 0, /* XCRYPTCBC */ }, { /* 1613 */ 0, /* XCRYPTCFB */ }, { /* 1614 */ 0, /* XCRYPTCTR */ }, { /* 1615 */ 0, /* XCRYPTECB */ }, { /* 1616 */ 0, /* XCRYPTOFB */ }, { /* 1617 */ 0, /* XGETBV */ }, { /* 1618 */ 0, /* XLAT */ }, { /* 1619 */ 2, /* XOR16i16 */ }, { /* 1620 */ 3, /* XOR16mi */ }, { /* 1621 */ 4, /* XOR16mi8 */ }, { /* 1622 */ 5, /* XOR16mr */ }, { /* 1623 */ 6, /* XOR16ri */ }, { /* 1624 */ 7, /* XOR16ri8 */ }, { /* 1625 */ 8, /* XOR16rm */ }, { /* 1626 */ 9, /* XOR16rr */ }, { /* 1627 */ 10, /* XOR16rr_REV */ }, { /* 1628 */ 2, /* XOR32i32 */ }, { /* 1629 */ 3, /* XOR32mi */ }, { /* 1630 */ 4, /* XOR32mi8 */ }, { /* 1631 */ 5, /* XOR32mr */ }, { /* 1632 */ 6, /* XOR32ri */ }, { /* 1633 */ 7, /* XOR32ri8 */ }, { /* 1634 */ 8, /* XOR32rm */ }, { /* 1635 */ 9, /* XOR32rr */ }, { /* 1636 */ 10, /* XOR32rr_REV */ }, { /* 1637 */ 11, /* XOR64i32 */ }, { /* 1638 */ 12, /* XOR64mi32 */ }, { /* 1639 */ 4, /* XOR64mi8 */ }, { /* 1640 */ 13, /* XOR64mr */ }, { /* 1641 */ 14, /* XOR64ri32 */ }, { /* 1642 */ 15, /* XOR64ri8 */ }, { /* 1643 */ 16, /* XOR64rm */ }, { /* 1644 */ 17, /* XOR64rr */ }, { /* 1645 */ 18, /* XOR64rr_REV */ }, { /* 1646 */ 1, /* XOR8i8 */ }, { /* 1647 */ 4, /* XOR8mi */ }, { /* 1648 */ 4, /* XOR8mi8 */ }, { /* 1649 */ 19, /* XOR8mr */ }, { /* 1650 */ 20, /* XOR8ri */ }, { /* 1651 */ 20, /* XOR8ri8 */ }, { /* 1652 */ 21, /* XOR8rm */ }, { /* 1653 */ 22, /* XOR8rr */ }, { /* 1654 */ 23, /* XOR8rr_REV */ }, { /* 1655 */ 54, /* XRSTOR */ }, { /* 1656 */ 54, /* XRSTOR64 */ }, { /* 1657 */ 54, /* XRSTORS */ }, { /* 1658 */ 54, /* XRSTORS64 */ }, { /* 1659 */ 54, /* XSAVE */ }, { /* 1660 */ 54, /* XSAVE64 */ }, { /* 1661 */ 54, /* XSAVEC */ }, { /* 1662 */ 54, /* XSAVEC64 */ }, { /* 1663 */ 54, /* XSAVEOPT */ }, { /* 1664 */ 54, /* XSAVEOPT64 */ }, { /* 1665 */ 54, /* XSAVES */ }, { /* 1666 */ 54, /* XSAVES64 */ }, { /* 1667 */ 0, /* XSETBV */ }, { /* 1668 */ 0, /* XSHA1 */ }, { /* 1669 */ 0, /* XSHA256 */ }, { /* 1670 */ 0, /* XSTORE */ }, }; static const uint8_t x86DisassemblerContexts[16384] = { IC, /* 0 */ IC_64BIT, /* 1 */ IC_XS, /* 2 */ IC_64BIT_XS, /* 3 */ IC_XD, /* 4 */ IC_64BIT_XD, /* 5 */ IC_XS, /* 6 */ IC_64BIT_XS, /* 7 */ IC, /* 8 */ IC_64BIT_REXW, /* 9 */ IC_XS, /* 10 */ IC_64BIT_REXW_XS, /* 11 */ IC_XD, /* 12 */ IC_64BIT_REXW_XD, /* 13 */ IC_XS, /* 14 */ IC_64BIT_REXW_XS, /* 15 */ IC_OPSIZE, /* 16 */ IC_64BIT_OPSIZE, /* 17 */ IC_XS_OPSIZE, /* 18 */ IC_64BIT_XS_OPSIZE, /* 19 */ IC_XD_OPSIZE, /* 20 */ IC_64BIT_XD_OPSIZE, /* 21 */ IC_XS_OPSIZE, /* 22 */ IC_64BIT_XD_OPSIZE, /* 23 */ IC_OPSIZE, /* 24 */ IC_64BIT_REXW_OPSIZE, /* 25 */ IC_XS_OPSIZE, /* 26 */ IC_64BIT_REXW_XS, /* 27 */ IC_XD_OPSIZE, /* 28 */ IC_64BIT_REXW_XD, /* 29 */ IC_XS_OPSIZE, /* 30 */ IC_64BIT_REXW_XS, /* 31 */ IC_ADSIZE, /* 32 */ IC_64BIT_ADSIZE, /* 33 */ IC_XS_ADSIZE, /* 34 */ IC_64BIT_XS_ADSIZE, /* 35 */ IC_XD_ADSIZE, /* 36 */ IC_64BIT_XD_ADSIZE, /* 37 */ IC_XS_ADSIZE, /* 38 */ IC_64BIT_XD_ADSIZE, /* 39 */ IC_ADSIZE, /* 40 */ IC_64BIT_REXW_ADSIZE, /* 41 */ IC_XS_ADSIZE, /* 42 */ IC_64BIT_REXW_XS, /* 43 */ IC_XD_ADSIZE, /* 44 */ IC_64BIT_REXW_XD, /* 45 */ IC_XS_ADSIZE, /* 46 */ IC_64BIT_REXW_XS, /* 47 */ IC_OPSIZE_ADSIZE, /* 48 */ IC_64BIT_OPSIZE_ADSIZE, /* 49 */ IC_XS_OPSIZE, /* 50 */ IC_64BIT_XS_OPSIZE, /* 51 */ IC_XD_OPSIZE, /* 52 */ IC_64BIT_XD_OPSIZE, /* 53 */ IC_XS_OPSIZE, /* 54 */ IC_64BIT_XD_OPSIZE, /* 55 */ IC_OPSIZE_ADSIZE, /* 56 */ IC_64BIT_REXW_OPSIZE, /* 57 */ IC_XS_OPSIZE, /* 58 */ IC_64BIT_REXW_XS, /* 59 */ IC_XD_OPSIZE, /* 60 */ IC_64BIT_REXW_XD, /* 61 */ IC_XS_OPSIZE, /* 62 */ IC_64BIT_REXW_XS, /* 63 */ IC_VEX, /* 64 */ IC_VEX, /* 65 */ IC_VEX_XS, /* 66 */ IC_VEX_XS, /* 67 */ IC_VEX_XD, /* 68 */ IC_VEX_XD, /* 69 */ IC_VEX_XD, /* 70 */ IC_VEX_XD, /* 71 */ IC_VEX_W, /* 72 */ IC_VEX_W, /* 73 */ IC_VEX_W_XS, /* 74 */ IC_VEX_W_XS, /* 75 */ IC_VEX_W_XD, /* 76 */ IC_VEX_W_XD, /* 77 */ IC_VEX_W_XD, /* 78 */ IC_VEX_W_XD, /* 79 */ IC_VEX_OPSIZE, /* 80 */ IC_VEX_OPSIZE, /* 81 */ IC_VEX_OPSIZE, /* 82 */ IC_VEX_OPSIZE, /* 83 */ IC_VEX_OPSIZE, /* 84 */ IC_VEX_OPSIZE, /* 85 */ IC_VEX_OPSIZE, /* 86 */ IC_VEX_OPSIZE, /* 87 */ IC_VEX_W_OPSIZE, /* 88 */ IC_VEX_W_OPSIZE, /* 89 */ IC_VEX_W_OPSIZE, /* 90 */ IC_VEX_W_OPSIZE, /* 91 */ IC_VEX_W_OPSIZE, /* 92 */ IC_VEX_W_OPSIZE, /* 93 */ IC_VEX_W_OPSIZE, /* 94 */ IC_VEX_W_OPSIZE, /* 95 */ IC_VEX, /* 96 */ IC_VEX, /* 97 */ IC_VEX_XS, /* 98 */ IC_VEX_XS, /* 99 */ IC_VEX_XD, /* 100 */ IC_VEX_XD, /* 101 */ IC_VEX_XD, /* 102 */ IC_VEX_XD, /* 103 */ IC_VEX_W, /* 104 */ IC_VEX_W, /* 105 */ IC_VEX_W_XS, /* 106 */ IC_VEX_W_XS, /* 107 */ IC_VEX_W_XD, /* 108 */ IC_VEX_W_XD, /* 109 */ IC_VEX_W_XD, /* 110 */ IC_VEX_W_XD, /* 111 */ IC_VEX_OPSIZE, /* 112 */ IC_VEX_OPSIZE, /* 113 */ IC_VEX_OPSIZE, /* 114 */ IC_VEX_OPSIZE, /* 115 */ IC_VEX_OPSIZE, /* 116 */ IC_VEX_OPSIZE, /* 117 */ IC_VEX_OPSIZE, /* 118 */ IC_VEX_OPSIZE, /* 119 */ IC_VEX_W_OPSIZE, /* 120 */ IC_VEX_W_OPSIZE, /* 121 */ IC_VEX_W_OPSIZE, /* 122 */ IC_VEX_W_OPSIZE, /* 123 */ IC_VEX_W_OPSIZE, /* 124 */ IC_VEX_W_OPSIZE, /* 125 */ IC_VEX_W_OPSIZE, /* 126 */ IC_VEX_W_OPSIZE, /* 127 */ IC_VEX_L, /* 128 */ IC_VEX_L, /* 129 */ IC_VEX_L_XS, /* 130 */ IC_VEX_L_XS, /* 131 */ IC_VEX_L_XD, /* 132 */ IC_VEX_L_XD, /* 133 */ IC_VEX_L_XD, /* 134 */ IC_VEX_L_XD, /* 135 */ IC_VEX_L_W, /* 136 */ IC_VEX_L_W, /* 137 */ IC_VEX_L_W_XS, /* 138 */ IC_VEX_L_W_XS, /* 139 */ IC_VEX_L_W_XD, /* 140 */ IC_VEX_L_W_XD, /* 141 */ IC_VEX_L_W_XD, /* 142 */ IC_VEX_L_W_XD, /* 143 */ IC_VEX_L_OPSIZE, /* 144 */ IC_VEX_L_OPSIZE, /* 145 */ IC_VEX_L_OPSIZE, /* 146 */ IC_VEX_L_OPSIZE, /* 147 */ IC_VEX_L_OPSIZE, /* 148 */ IC_VEX_L_OPSIZE, /* 149 */ IC_VEX_L_OPSIZE, /* 150 */ IC_VEX_L_OPSIZE, /* 151 */ IC_VEX_L_W_OPSIZE, /* 152 */ IC_VEX_L_W_OPSIZE, /* 153 */ IC_VEX_L_W_OPSIZE, /* 154 */ IC_VEX_L_W_OPSIZE, /* 155 */ IC_VEX_L_W_OPSIZE, /* 156 */ IC_VEX_L_W_OPSIZE, /* 157 */ IC_VEX_L_W_OPSIZE, /* 158 */ IC_VEX_L_W_OPSIZE, /* 159 */ IC_VEX_L, /* 160 */ IC_VEX_L, /* 161 */ IC_VEX_L_XS, /* 162 */ IC_VEX_L_XS, /* 163 */ IC_VEX_L_XD, /* 164 */ IC_VEX_L_XD, /* 165 */ IC_VEX_L_XD, /* 166 */ IC_VEX_L_XD, /* 167 */ IC_VEX_L_W, /* 168 */ IC_VEX_L_W, /* 169 */ IC_VEX_L_W_XS, /* 170 */ IC_VEX_L_W_XS, /* 171 */ IC_VEX_L_W_XD, /* 172 */ IC_VEX_L_W_XD, /* 173 */ IC_VEX_L_W_XD, /* 174 */ IC_VEX_L_W_XD, /* 175 */ IC_VEX_L_OPSIZE, /* 176 */ IC_VEX_L_OPSIZE, /* 177 */ IC_VEX_L_OPSIZE, /* 178 */ IC_VEX_L_OPSIZE, /* 179 */ IC_VEX_L_OPSIZE, /* 180 */ IC_VEX_L_OPSIZE, /* 181 */ IC_VEX_L_OPSIZE, /* 182 */ IC_VEX_L_OPSIZE, /* 183 */ IC_VEX_L_W_OPSIZE, /* 184 */ IC_VEX_L_W_OPSIZE, /* 185 */ IC_VEX_L_W_OPSIZE, /* 186 */ IC_VEX_L_W_OPSIZE, /* 187 */ IC_VEX_L_W_OPSIZE, /* 188 */ IC_VEX_L_W_OPSIZE, /* 189 */ IC_VEX_L_W_OPSIZE, /* 190 */ IC_VEX_L_W_OPSIZE, /* 191 */ IC_VEX_L, /* 192 */ IC_VEX_L, /* 193 */ IC_VEX_L_XS, /* 194 */ IC_VEX_L_XS, /* 195 */ IC_VEX_L_XD, /* 196 */ IC_VEX_L_XD, /* 197 */ IC_VEX_L_XD, /* 198 */ IC_VEX_L_XD, /* 199 */ IC_VEX_L_W, /* 200 */ IC_VEX_L_W, /* 201 */ IC_VEX_L_W_XS, /* 202 */ IC_VEX_L_W_XS, /* 203 */ IC_VEX_L_W_XD, /* 204 */ IC_VEX_L_W_XD, /* 205 */ IC_VEX_L_W_XD, /* 206 */ IC_VEX_L_W_XD, /* 207 */ IC_VEX_L_OPSIZE, /* 208 */ IC_VEX_L_OPSIZE, /* 209 */ IC_VEX_L_OPSIZE, /* 210 */ IC_VEX_L_OPSIZE, /* 211 */ IC_VEX_L_OPSIZE, /* 212 */ IC_VEX_L_OPSIZE, /* 213 */ IC_VEX_L_OPSIZE, /* 214 */ IC_VEX_L_OPSIZE, /* 215 */ IC_VEX_L_W_OPSIZE, /* 216 */ IC_VEX_L_W_OPSIZE, /* 217 */ IC_VEX_L_W_OPSIZE, /* 218 */ IC_VEX_L_W_OPSIZE, /* 219 */ IC_VEX_L_W_OPSIZE, /* 220 */ IC_VEX_L_W_OPSIZE, /* 221 */ IC_VEX_L_W_OPSIZE, /* 222 */ IC_VEX_L_W_OPSIZE, /* 223 */ IC_VEX_L, /* 224 */ IC_VEX_L, /* 225 */ IC_VEX_L_XS, /* 226 */ IC_VEX_L_XS, /* 227 */ IC_VEX_L_XD, /* 228 */ IC_VEX_L_XD, /* 229 */ IC_VEX_L_XD, /* 230 */ IC_VEX_L_XD, /* 231 */ IC_VEX_L_W, /* 232 */ IC_VEX_L_W, /* 233 */ IC_VEX_L_W_XS, /* 234 */ IC_VEX_L_W_XS, /* 235 */ IC_VEX_L_W_XD, /* 236 */ IC_VEX_L_W_XD, /* 237 */ IC_VEX_L_W_XD, /* 238 */ IC_VEX_L_W_XD, /* 239 */ IC_VEX_L_OPSIZE, /* 240 */ IC_VEX_L_OPSIZE, /* 241 */ IC_VEX_L_OPSIZE, /* 242 */ IC_VEX_L_OPSIZE, /* 243 */ IC_VEX_L_OPSIZE, /* 244 */ IC_VEX_L_OPSIZE, /* 245 */ IC_VEX_L_OPSIZE, /* 246 */ IC_VEX_L_OPSIZE, /* 247 */ IC_VEX_L_W_OPSIZE, /* 248 */ IC_VEX_L_W_OPSIZE, /* 249 */ IC_VEX_L_W_OPSIZE, /* 250 */ IC_VEX_L_W_OPSIZE, /* 251 */ IC_VEX_L_W_OPSIZE, /* 252 */ IC_VEX_L_W_OPSIZE, /* 253 */ IC_VEX_L_W_OPSIZE, /* 254 */ IC_VEX_L_W_OPSIZE, /* 255 */ IC_EVEX, /* 256 */ IC_EVEX, /* 257 */ IC_EVEX_XS, /* 258 */ IC_EVEX_XS, /* 259 */ IC_EVEX_XD, /* 260 */ IC_EVEX_XD, /* 261 */ IC_EVEX_XD, /* 262 */ IC_EVEX_XD, /* 263 */ IC_EVEX_W, /* 264 */ IC_EVEX_W, /* 265 */ IC_EVEX_W_XS, /* 266 */ IC_EVEX_W_XS, /* 267 */ IC_EVEX_W_XD, /* 268 */ IC_EVEX_W_XD, /* 269 */ IC_EVEX_W_XD, /* 270 */ IC_EVEX_W_XD, /* 271 */ IC_EVEX_OPSIZE, /* 272 */ IC_EVEX_OPSIZE, /* 273 */ IC_EVEX_OPSIZE, /* 274 */ IC_EVEX_OPSIZE, /* 275 */ IC_EVEX_OPSIZE, /* 276 */ IC_EVEX_OPSIZE, /* 277 */ IC_EVEX_OPSIZE, /* 278 */ IC_EVEX_OPSIZE, /* 279 */ IC_EVEX_W_OPSIZE, /* 280 */ IC_EVEX_W_OPSIZE, /* 281 */ IC_EVEX_W_OPSIZE, /* 282 */ IC_EVEX_W_OPSIZE, /* 283 */ IC_EVEX_W_OPSIZE, /* 284 */ IC_EVEX_W_OPSIZE, /* 285 */ IC_EVEX_W_OPSIZE, /* 286 */ IC_EVEX_W_OPSIZE, /* 287 */ IC_EVEX, /* 288 */ IC_EVEX, /* 289 */ IC_EVEX_XS, /* 290 */ IC_EVEX_XS, /* 291 */ IC_EVEX_XD, /* 292 */ IC_EVEX_XD, /* 293 */ IC_EVEX_XD, /* 294 */ IC_EVEX_XD, /* 295 */ IC_EVEX_W, /* 296 */ IC_EVEX_W, /* 297 */ IC_EVEX_W_XS, /* 298 */ IC_EVEX_W_XS, /* 299 */ IC_EVEX_W_XD, /* 300 */ IC_EVEX_W_XD, /* 301 */ IC_EVEX_W_XD, /* 302 */ IC_EVEX_W_XD, /* 303 */ IC_EVEX_OPSIZE, /* 304 */ IC_EVEX_OPSIZE, /* 305 */ IC_EVEX_OPSIZE, /* 306 */ IC_EVEX_OPSIZE, /* 307 */ IC_EVEX_OPSIZE, /* 308 */ IC_EVEX_OPSIZE, /* 309 */ IC_EVEX_OPSIZE, /* 310 */ IC_EVEX_OPSIZE, /* 311 */ IC_EVEX_W_OPSIZE, /* 312 */ IC_EVEX_W_OPSIZE, /* 313 */ IC_EVEX_W_OPSIZE, /* 314 */ IC_EVEX_W_OPSIZE, /* 315 */ IC_EVEX_W_OPSIZE, /* 316 */ IC_EVEX_W_OPSIZE, /* 317 */ IC_EVEX_W_OPSIZE, /* 318 */ IC_EVEX_W_OPSIZE, /* 319 */ IC_EVEX, /* 320 */ IC_EVEX, /* 321 */ IC_EVEX_XS, /* 322 */ IC_EVEX_XS, /* 323 */ IC_EVEX_XD, /* 324 */ IC_EVEX_XD, /* 325 */ IC_EVEX_XD, /* 326 */ IC_EVEX_XD, /* 327 */ IC_EVEX_W, /* 328 */ IC_EVEX_W, /* 329 */ IC_EVEX_W_XS, /* 330 */ IC_EVEX_W_XS, /* 331 */ IC_EVEX_W_XD, /* 332 */ IC_EVEX_W_XD, /* 333 */ IC_EVEX_W_XD, /* 334 */ IC_EVEX_W_XD, /* 335 */ IC_EVEX_OPSIZE, /* 336 */ IC_EVEX_OPSIZE, /* 337 */ IC_EVEX_OPSIZE, /* 338 */ IC_EVEX_OPSIZE, /* 339 */ IC_EVEX_OPSIZE, /* 340 */ IC_EVEX_OPSIZE, /* 341 */ IC_EVEX_OPSIZE, /* 342 */ IC_EVEX_OPSIZE, /* 343 */ IC_EVEX_W_OPSIZE, /* 344 */ IC_EVEX_W_OPSIZE, /* 345 */ IC_EVEX_W_OPSIZE, /* 346 */ IC_EVEX_W_OPSIZE, /* 347 */ IC_EVEX_W_OPSIZE, /* 348 */ IC_EVEX_W_OPSIZE, /* 349 */ IC_EVEX_W_OPSIZE, /* 350 */ IC_EVEX_W_OPSIZE, /* 351 */ IC_EVEX, /* 352 */ IC_EVEX, /* 353 */ IC_EVEX_XS, /* 354 */ IC_EVEX_XS, /* 355 */ IC_EVEX_XD, /* 356 */ IC_EVEX_XD, /* 357 */ IC_EVEX_XD, /* 358 */ IC_EVEX_XD, /* 359 */ IC_EVEX_W, /* 360 */ IC_EVEX_W, /* 361 */ IC_EVEX_W_XS, /* 362 */ IC_EVEX_W_XS, /* 363 */ IC_EVEX_W_XD, /* 364 */ IC_EVEX_W_XD, /* 365 */ IC_EVEX_W_XD, /* 366 */ IC_EVEX_W_XD, /* 367 */ IC_EVEX_OPSIZE, /* 368 */ IC_EVEX_OPSIZE, /* 369 */ IC_EVEX_OPSIZE, /* 370 */ IC_EVEX_OPSIZE, /* 371 */ IC_EVEX_OPSIZE, /* 372 */ IC_EVEX_OPSIZE, /* 373 */ IC_EVEX_OPSIZE, /* 374 */ IC_EVEX_OPSIZE, /* 375 */ IC_EVEX_W_OPSIZE, /* 376 */ IC_EVEX_W_OPSIZE, /* 377 */ IC_EVEX_W_OPSIZE, /* 378 */ IC_EVEX_W_OPSIZE, /* 379 */ IC_EVEX_W_OPSIZE, /* 380 */ IC_EVEX_W_OPSIZE, /* 381 */ IC_EVEX_W_OPSIZE, /* 382 */ IC_EVEX_W_OPSIZE, /* 383 */ IC_EVEX, /* 384 */ IC_EVEX, /* 385 */ IC_EVEX_XS, /* 386 */ IC_EVEX_XS, /* 387 */ IC_EVEX_XD, /* 388 */ IC_EVEX_XD, /* 389 */ IC_EVEX_XD, /* 390 */ IC_EVEX_XD, /* 391 */ IC_EVEX_W, /* 392 */ IC_EVEX_W, /* 393 */ IC_EVEX_W_XS, /* 394 */ IC_EVEX_W_XS, /* 395 */ IC_EVEX_W_XD, /* 396 */ IC_EVEX_W_XD, /* 397 */ IC_EVEX_W_XD, /* 398 */ IC_EVEX_W_XD, /* 399 */ IC_EVEX_OPSIZE, /* 400 */ IC_EVEX_OPSIZE, /* 401 */ IC_EVEX_OPSIZE, /* 402 */ IC_EVEX_OPSIZE, /* 403 */ IC_EVEX_OPSIZE, /* 404 */ IC_EVEX_OPSIZE, /* 405 */ IC_EVEX_OPSIZE, /* 406 */ IC_EVEX_OPSIZE, /* 407 */ IC_EVEX_W_OPSIZE, /* 408 */ IC_EVEX_W_OPSIZE, /* 409 */ IC_EVEX_W_OPSIZE, /* 410 */ IC_EVEX_W_OPSIZE, /* 411 */ IC_EVEX_W_OPSIZE, /* 412 */ IC_EVEX_W_OPSIZE, /* 413 */ IC_EVEX_W_OPSIZE, /* 414 */ IC_EVEX_W_OPSIZE, /* 415 */ IC_EVEX, /* 416 */ IC_EVEX, /* 417 */ IC_EVEX_XS, /* 418 */ IC_EVEX_XS, /* 419 */ IC_EVEX_XD, /* 420 */ IC_EVEX_XD, /* 421 */ IC_EVEX_XD, /* 422 */ IC_EVEX_XD, /* 423 */ IC_EVEX_W, /* 424 */ IC_EVEX_W, /* 425 */ IC_EVEX_W_XS, /* 426 */ IC_EVEX_W_XS, /* 427 */ IC_EVEX_W_XD, /* 428 */ IC_EVEX_W_XD, /* 429 */ IC_EVEX_W_XD, /* 430 */ IC_EVEX_W_XD, /* 431 */ IC_EVEX_OPSIZE, /* 432 */ IC_EVEX_OPSIZE, /* 433 */ IC_EVEX_OPSIZE, /* 434 */ IC_EVEX_OPSIZE, /* 435 */ IC_EVEX_OPSIZE, /* 436 */ IC_EVEX_OPSIZE, /* 437 */ IC_EVEX_OPSIZE, /* 438 */ IC_EVEX_OPSIZE, /* 439 */ IC_EVEX_W_OPSIZE, /* 440 */ IC_EVEX_W_OPSIZE, /* 441 */ IC_EVEX_W_OPSIZE, /* 442 */ IC_EVEX_W_OPSIZE, /* 443 */ IC_EVEX_W_OPSIZE, /* 444 */ IC_EVEX_W_OPSIZE, /* 445 */ IC_EVEX_W_OPSIZE, /* 446 */ IC_EVEX_W_OPSIZE, /* 447 */ IC_EVEX, /* 448 */ IC_EVEX, /* 449 */ IC_EVEX_XS, /* 450 */ IC_EVEX_XS, /* 451 */ IC_EVEX_XD, /* 452 */ IC_EVEX_XD, /* 453 */ IC_EVEX_XD, /* 454 */ IC_EVEX_XD, /* 455 */ IC_EVEX_W, /* 456 */ IC_EVEX_W, /* 457 */ IC_EVEX_W_XS, /* 458 */ IC_EVEX_W_XS, /* 459 */ IC_EVEX_W_XD, /* 460 */ IC_EVEX_W_XD, /* 461 */ IC_EVEX_W_XD, /* 462 */ IC_EVEX_W_XD, /* 463 */ IC_EVEX_OPSIZE, /* 464 */ IC_EVEX_OPSIZE, /* 465 */ IC_EVEX_OPSIZE, /* 466 */ IC_EVEX_OPSIZE, /* 467 */ IC_EVEX_OPSIZE, /* 468 */ IC_EVEX_OPSIZE, /* 469 */ IC_EVEX_OPSIZE, /* 470 */ IC_EVEX_OPSIZE, /* 471 */ IC_EVEX_W_OPSIZE, /* 472 */ IC_EVEX_W_OPSIZE, /* 473 */ IC_EVEX_W_OPSIZE, /* 474 */ IC_EVEX_W_OPSIZE, /* 475 */ IC_EVEX_W_OPSIZE, /* 476 */ IC_EVEX_W_OPSIZE, /* 477 */ IC_EVEX_W_OPSIZE, /* 478 */ IC_EVEX_W_OPSIZE, /* 479 */ IC_EVEX, /* 480 */ IC_EVEX, /* 481 */ IC_EVEX_XS, /* 482 */ IC_EVEX_XS, /* 483 */ IC_EVEX_XD, /* 484 */ IC_EVEX_XD, /* 485 */ IC_EVEX_XD, /* 486 */ IC_EVEX_XD, /* 487 */ IC_EVEX_W, /* 488 */ IC_EVEX_W, /* 489 */ IC_EVEX_W_XS, /* 490 */ IC_EVEX_W_XS, /* 491 */ IC_EVEX_W_XD, /* 492 */ IC_EVEX_W_XD, /* 493 */ IC_EVEX_W_XD, /* 494 */ IC_EVEX_W_XD, /* 495 */ IC_EVEX_OPSIZE, /* 496 */ IC_EVEX_OPSIZE, /* 497 */ IC_EVEX_OPSIZE, /* 498 */ IC_EVEX_OPSIZE, /* 499 */ IC_EVEX_OPSIZE, /* 500 */ IC_EVEX_OPSIZE, /* 501 */ IC_EVEX_OPSIZE, /* 502 */ IC_EVEX_OPSIZE, /* 503 */ IC_EVEX_W_OPSIZE, /* 504 */ IC_EVEX_W_OPSIZE, /* 505 */ IC_EVEX_W_OPSIZE, /* 506 */ IC_EVEX_W_OPSIZE, /* 507 */ IC_EVEX_W_OPSIZE, /* 508 */ IC_EVEX_W_OPSIZE, /* 509 */ IC_EVEX_W_OPSIZE, /* 510 */ IC_EVEX_W_OPSIZE, /* 511 */ IC, /* 512 */ IC_64BIT, /* 513 */ IC_XS, /* 514 */ IC_64BIT_XS, /* 515 */ IC_XD, /* 516 */ IC_64BIT_XD, /* 517 */ IC_XS, /* 518 */ IC_64BIT_XS, /* 519 */ IC, /* 520 */ IC_64BIT_REXW, /* 521 */ IC_XS, /* 522 */ IC_64BIT_REXW_XS, /* 523 */ IC_XD, /* 524 */ IC_64BIT_REXW_XD, /* 525 */ IC_XS, /* 526 */ IC_64BIT_REXW_XS, /* 527 */ IC_OPSIZE, /* 528 */ IC_64BIT_OPSIZE, /* 529 */ IC_XS_OPSIZE, /* 530 */ IC_64BIT_XS_OPSIZE, /* 531 */ IC_XD_OPSIZE, /* 532 */ IC_64BIT_XD_OPSIZE, /* 533 */ IC_XS_OPSIZE, /* 534 */ IC_64BIT_XD_OPSIZE, /* 535 */ IC_OPSIZE, /* 536 */ IC_64BIT_REXW_OPSIZE, /* 537 */ IC_XS_OPSIZE, /* 538 */ IC_64BIT_REXW_XS, /* 539 */ IC_XD_OPSIZE, /* 540 */ IC_64BIT_REXW_XD, /* 541 */ IC_XS_OPSIZE, /* 542 */ IC_64BIT_REXW_XS, /* 543 */ IC_ADSIZE, /* 544 */ IC_64BIT_ADSIZE, /* 545 */ IC_XS_ADSIZE, /* 546 */ IC_64BIT_XS_ADSIZE, /* 547 */ IC_XD_ADSIZE, /* 548 */ IC_64BIT_XD_ADSIZE, /* 549 */ IC_XS_ADSIZE, /* 550 */ IC_64BIT_XD_ADSIZE, /* 551 */ IC_ADSIZE, /* 552 */ IC_64BIT_REXW_ADSIZE, /* 553 */ IC_XS_ADSIZE, /* 554 */ IC_64BIT_REXW_XS, /* 555 */ IC_XD_ADSIZE, /* 556 */ IC_64BIT_REXW_XD, /* 557 */ IC_XS_ADSIZE, /* 558 */ IC_64BIT_REXW_XS, /* 559 */ IC_OPSIZE_ADSIZE, /* 560 */ IC_64BIT_OPSIZE_ADSIZE, /* 561 */ IC_XS_OPSIZE, /* 562 */ IC_64BIT_XS_OPSIZE, /* 563 */ IC_XD_OPSIZE, /* 564 */ IC_64BIT_XD_OPSIZE, /* 565 */ IC_XS_OPSIZE, /* 566 */ IC_64BIT_XD_OPSIZE, /* 567 */ IC_OPSIZE_ADSIZE, /* 568 */ IC_64BIT_REXW_OPSIZE, /* 569 */ IC_XS_OPSIZE, /* 570 */ IC_64BIT_REXW_XS, /* 571 */ IC_XD_OPSIZE, /* 572 */ IC_64BIT_REXW_XD, /* 573 */ IC_XS_OPSIZE, /* 574 */ IC_64BIT_REXW_XS, /* 575 */ IC_VEX, /* 576 */ IC_VEX, /* 577 */ IC_VEX_XS, /* 578 */ IC_VEX_XS, /* 579 */ IC_VEX_XD, /* 580 */ IC_VEX_XD, /* 581 */ IC_VEX_XD, /* 582 */ IC_VEX_XD, /* 583 */ IC_VEX_W, /* 584 */ IC_VEX_W, /* 585 */ IC_VEX_W_XS, /* 586 */ IC_VEX_W_XS, /* 587 */ IC_VEX_W_XD, /* 588 */ IC_VEX_W_XD, /* 589 */ IC_VEX_W_XD, /* 590 */ IC_VEX_W_XD, /* 591 */ IC_VEX_OPSIZE, /* 592 */ IC_VEX_OPSIZE, /* 593 */ IC_VEX_OPSIZE, /* 594 */ IC_VEX_OPSIZE, /* 595 */ IC_VEX_OPSIZE, /* 596 */ IC_VEX_OPSIZE, /* 597 */ IC_VEX_OPSIZE, /* 598 */ IC_VEX_OPSIZE, /* 599 */ IC_VEX_W_OPSIZE, /* 600 */ IC_VEX_W_OPSIZE, /* 601 */ IC_VEX_W_OPSIZE, /* 602 */ IC_VEX_W_OPSIZE, /* 603 */ IC_VEX_W_OPSIZE, /* 604 */ IC_VEX_W_OPSIZE, /* 605 */ IC_VEX_W_OPSIZE, /* 606 */ IC_VEX_W_OPSIZE, /* 607 */ IC_VEX, /* 608 */ IC_VEX, /* 609 */ IC_VEX_XS, /* 610 */ IC_VEX_XS, /* 611 */ IC_VEX_XD, /* 612 */ IC_VEX_XD, /* 613 */ IC_VEX_XD, /* 614 */ IC_VEX_XD, /* 615 */ IC_VEX_W, /* 616 */ IC_VEX_W, /* 617 */ IC_VEX_W_XS, /* 618 */ IC_VEX_W_XS, /* 619 */ IC_VEX_W_XD, /* 620 */ IC_VEX_W_XD, /* 621 */ IC_VEX_W_XD, /* 622 */ IC_VEX_W_XD, /* 623 */ IC_VEX_OPSIZE, /* 624 */ IC_VEX_OPSIZE, /* 625 */ IC_VEX_OPSIZE, /* 626 */ IC_VEX_OPSIZE, /* 627 */ IC_VEX_OPSIZE, /* 628 */ IC_VEX_OPSIZE, /* 629 */ IC_VEX_OPSIZE, /* 630 */ IC_VEX_OPSIZE, /* 631 */ IC_VEX_W_OPSIZE, /* 632 */ IC_VEX_W_OPSIZE, /* 633 */ IC_VEX_W_OPSIZE, /* 634 */ IC_VEX_W_OPSIZE, /* 635 */ IC_VEX_W_OPSIZE, /* 636 */ IC_VEX_W_OPSIZE, /* 637 */ IC_VEX_W_OPSIZE, /* 638 */ IC_VEX_W_OPSIZE, /* 639 */ IC_VEX_L, /* 640 */ IC_VEX_L, /* 641 */ IC_VEX_L_XS, /* 642 */ IC_VEX_L_XS, /* 643 */ IC_VEX_L_XD, /* 644 */ IC_VEX_L_XD, /* 645 */ IC_VEX_L_XD, /* 646 */ IC_VEX_L_XD, /* 647 */ IC_VEX_L_W, /* 648 */ IC_VEX_L_W, /* 649 */ IC_VEX_L_W_XS, /* 650 */ IC_VEX_L_W_XS, /* 651 */ IC_VEX_L_W_XD, /* 652 */ IC_VEX_L_W_XD, /* 653 */ IC_VEX_L_W_XD, /* 654 */ IC_VEX_L_W_XD, /* 655 */ IC_VEX_L_OPSIZE, /* 656 */ IC_VEX_L_OPSIZE, /* 657 */ IC_VEX_L_OPSIZE, /* 658 */ IC_VEX_L_OPSIZE, /* 659 */ IC_VEX_L_OPSIZE, /* 660 */ IC_VEX_L_OPSIZE, /* 661 */ IC_VEX_L_OPSIZE, /* 662 */ IC_VEX_L_OPSIZE, /* 663 */ IC_VEX_L_W_OPSIZE, /* 664 */ IC_VEX_L_W_OPSIZE, /* 665 */ IC_VEX_L_W_OPSIZE, /* 666 */ IC_VEX_L_W_OPSIZE, /* 667 */ IC_VEX_L_W_OPSIZE, /* 668 */ IC_VEX_L_W_OPSIZE, /* 669 */ IC_VEX_L_W_OPSIZE, /* 670 */ IC_VEX_L_W_OPSIZE, /* 671 */ IC_VEX_L, /* 672 */ IC_VEX_L, /* 673 */ IC_VEX_L_XS, /* 674 */ IC_VEX_L_XS, /* 675 */ IC_VEX_L_XD, /* 676 */ IC_VEX_L_XD, /* 677 */ IC_VEX_L_XD, /* 678 */ IC_VEX_L_XD, /* 679 */ IC_VEX_L_W, /* 680 */ IC_VEX_L_W, /* 681 */ IC_VEX_L_W_XS, /* 682 */ IC_VEX_L_W_XS, /* 683 */ IC_VEX_L_W_XD, /* 684 */ IC_VEX_L_W_XD, /* 685 */ IC_VEX_L_W_XD, /* 686 */ IC_VEX_L_W_XD, /* 687 */ IC_VEX_L_OPSIZE, /* 688 */ IC_VEX_L_OPSIZE, /* 689 */ IC_VEX_L_OPSIZE, /* 690 */ IC_VEX_L_OPSIZE, /* 691 */ IC_VEX_L_OPSIZE, /* 692 */ IC_VEX_L_OPSIZE, /* 693 */ IC_VEX_L_OPSIZE, /* 694 */ IC_VEX_L_OPSIZE, /* 695 */ IC_VEX_L_W_OPSIZE, /* 696 */ IC_VEX_L_W_OPSIZE, /* 697 */ IC_VEX_L_W_OPSIZE, /* 698 */ IC_VEX_L_W_OPSIZE, /* 699 */ IC_VEX_L_W_OPSIZE, /* 700 */ IC_VEX_L_W_OPSIZE, /* 701 */ IC_VEX_L_W_OPSIZE, /* 702 */ IC_VEX_L_W_OPSIZE, /* 703 */ IC_VEX_L, /* 704 */ IC_VEX_L, /* 705 */ IC_VEX_L_XS, /* 706 */ IC_VEX_L_XS, /* 707 */ IC_VEX_L_XD, /* 708 */ IC_VEX_L_XD, /* 709 */ IC_VEX_L_XD, /* 710 */ IC_VEX_L_XD, /* 711 */ IC_VEX_L_W, /* 712 */ IC_VEX_L_W, /* 713 */ IC_VEX_L_W_XS, /* 714 */ IC_VEX_L_W_XS, /* 715 */ IC_VEX_L_W_XD, /* 716 */ IC_VEX_L_W_XD, /* 717 */ IC_VEX_L_W_XD, /* 718 */ IC_VEX_L_W_XD, /* 719 */ IC_VEX_L_OPSIZE, /* 720 */ IC_VEX_L_OPSIZE, /* 721 */ IC_VEX_L_OPSIZE, /* 722 */ IC_VEX_L_OPSIZE, /* 723 */ IC_VEX_L_OPSIZE, /* 724 */ IC_VEX_L_OPSIZE, /* 725 */ IC_VEX_L_OPSIZE, /* 726 */ IC_VEX_L_OPSIZE, /* 727 */ IC_VEX_L_W_OPSIZE, /* 728 */ IC_VEX_L_W_OPSIZE, /* 729 */ IC_VEX_L_W_OPSIZE, /* 730 */ IC_VEX_L_W_OPSIZE, /* 731 */ IC_VEX_L_W_OPSIZE, /* 732 */ IC_VEX_L_W_OPSIZE, /* 733 */ IC_VEX_L_W_OPSIZE, /* 734 */ IC_VEX_L_W_OPSIZE, /* 735 */ IC_VEX_L, /* 736 */ IC_VEX_L, /* 737 */ IC_VEX_L_XS, /* 738 */ IC_VEX_L_XS, /* 739 */ IC_VEX_L_XD, /* 740 */ IC_VEX_L_XD, /* 741 */ IC_VEX_L_XD, /* 742 */ IC_VEX_L_XD, /* 743 */ IC_VEX_L_W, /* 744 */ IC_VEX_L_W, /* 745 */ IC_VEX_L_W_XS, /* 746 */ IC_VEX_L_W_XS, /* 747 */ IC_VEX_L_W_XD, /* 748 */ IC_VEX_L_W_XD, /* 749 */ IC_VEX_L_W_XD, /* 750 */ IC_VEX_L_W_XD, /* 751 */ IC_VEX_L_OPSIZE, /* 752 */ IC_VEX_L_OPSIZE, /* 753 */ IC_VEX_L_OPSIZE, /* 754 */ IC_VEX_L_OPSIZE, /* 755 */ IC_VEX_L_OPSIZE, /* 756 */ IC_VEX_L_OPSIZE, /* 757 */ IC_VEX_L_OPSIZE, /* 758 */ IC_VEX_L_OPSIZE, /* 759 */ IC_VEX_L_W_OPSIZE, /* 760 */ IC_VEX_L_W_OPSIZE, /* 761 */ IC_VEX_L_W_OPSIZE, /* 762 */ IC_VEX_L_W_OPSIZE, /* 763 */ IC_VEX_L_W_OPSIZE, /* 764 */ IC_VEX_L_W_OPSIZE, /* 765 */ IC_VEX_L_W_OPSIZE, /* 766 */ IC_VEX_L_W_OPSIZE, /* 767 */ IC_EVEX_L, /* 768 */ IC_EVEX_L, /* 769 */ IC_EVEX_L_XS, /* 770 */ IC_EVEX_L_XS, /* 771 */ IC_EVEX_L_XD, /* 772 */ IC_EVEX_L_XD, /* 773 */ IC_EVEX_L_XD, /* 774 */ IC_EVEX_L_XD, /* 775 */ IC_EVEX_L_W, /* 776 */ IC_EVEX_L_W, /* 777 */ IC_EVEX_L_W_XS, /* 778 */ IC_EVEX_L_W_XS, /* 779 */ IC_EVEX_L_W_XD, /* 780 */ IC_EVEX_L_W_XD, /* 781 */ IC_EVEX_L_W_XD, /* 782 */ IC_EVEX_L_W_XD, /* 783 */ IC_EVEX_L_OPSIZE, /* 784 */ IC_EVEX_L_OPSIZE, /* 785 */ IC_EVEX_L_OPSIZE, /* 786 */ IC_EVEX_L_OPSIZE, /* 787 */ IC_EVEX_L_OPSIZE, /* 788 */ IC_EVEX_L_OPSIZE, /* 789 */ IC_EVEX_L_OPSIZE, /* 790 */ IC_EVEX_L_OPSIZE, /* 791 */ IC_EVEX_L_W_OPSIZE, /* 792 */ IC_EVEX_L_W_OPSIZE, /* 793 */ IC_EVEX_L_W_OPSIZE, /* 794 */ IC_EVEX_L_W_OPSIZE, /* 795 */ IC_EVEX_L_W_OPSIZE, /* 796 */ IC_EVEX_L_W_OPSIZE, /* 797 */ IC_EVEX_L_W_OPSIZE, /* 798 */ IC_EVEX_L_W_OPSIZE, /* 799 */ IC_EVEX_L, /* 800 */ IC_EVEX_L, /* 801 */ IC_EVEX_L_XS, /* 802 */ IC_EVEX_L_XS, /* 803 */ IC_EVEX_L_XD, /* 804 */ IC_EVEX_L_XD, /* 805 */ IC_EVEX_L_XD, /* 806 */ IC_EVEX_L_XD, /* 807 */ IC_EVEX_L_W, /* 808 */ IC_EVEX_L_W, /* 809 */ IC_EVEX_L_W_XS, /* 810 */ IC_EVEX_L_W_XS, /* 811 */ IC_EVEX_L_W_XD, /* 812 */ IC_EVEX_L_W_XD, /* 813 */ IC_EVEX_L_W_XD, /* 814 */ IC_EVEX_L_W_XD, /* 815 */ IC_EVEX_L_OPSIZE, /* 816 */ IC_EVEX_L_OPSIZE, /* 817 */ IC_EVEX_L_OPSIZE, /* 818 */ IC_EVEX_L_OPSIZE, /* 819 */ IC_EVEX_L_OPSIZE, /* 820 */ IC_EVEX_L_OPSIZE, /* 821 */ IC_EVEX_L_OPSIZE, /* 822 */ IC_EVEX_L_OPSIZE, /* 823 */ IC_EVEX_L_W_OPSIZE, /* 824 */ IC_EVEX_L_W_OPSIZE, /* 825 */ IC_EVEX_L_W_OPSIZE, /* 826 */ IC_EVEX_L_W_OPSIZE, /* 827 */ IC_EVEX_L_W_OPSIZE, /* 828 */ IC_EVEX_L_W_OPSIZE, /* 829 */ IC_EVEX_L_W_OPSIZE, /* 830 */ IC_EVEX_L_W_OPSIZE, /* 831 */ IC_EVEX_L, /* 832 */ IC_EVEX_L, /* 833 */ IC_EVEX_L_XS, /* 834 */ IC_EVEX_L_XS, /* 835 */ IC_EVEX_L_XD, /* 836 */ IC_EVEX_L_XD, /* 837 */ IC_EVEX_L_XD, /* 838 */ IC_EVEX_L_XD, /* 839 */ IC_EVEX_L_W, /* 840 */ IC_EVEX_L_W, /* 841 */ IC_EVEX_L_W_XS, /* 842 */ IC_EVEX_L_W_XS, /* 843 */ IC_EVEX_L_W_XD, /* 844 */ IC_EVEX_L_W_XD, /* 845 */ IC_EVEX_L_W_XD, /* 846 */ IC_EVEX_L_W_XD, /* 847 */ IC_EVEX_L_OPSIZE, /* 848 */ IC_EVEX_L_OPSIZE, /* 849 */ IC_EVEX_L_OPSIZE, /* 850 */ IC_EVEX_L_OPSIZE, /* 851 */ IC_EVEX_L_OPSIZE, /* 852 */ IC_EVEX_L_OPSIZE, /* 853 */ IC_EVEX_L_OPSIZE, /* 854 */ IC_EVEX_L_OPSIZE, /* 855 */ IC_EVEX_L_W_OPSIZE, /* 856 */ IC_EVEX_L_W_OPSIZE, /* 857 */ IC_EVEX_L_W_OPSIZE, /* 858 */ IC_EVEX_L_W_OPSIZE, /* 859 */ IC_EVEX_L_W_OPSIZE, /* 860 */ IC_EVEX_L_W_OPSIZE, /* 861 */ IC_EVEX_L_W_OPSIZE, /* 862 */ IC_EVEX_L_W_OPSIZE, /* 863 */ IC_EVEX_L, /* 864 */ IC_EVEX_L, /* 865 */ IC_EVEX_L_XS, /* 866 */ IC_EVEX_L_XS, /* 867 */ IC_EVEX_L_XD, /* 868 */ IC_EVEX_L_XD, /* 869 */ IC_EVEX_L_XD, /* 870 */ IC_EVEX_L_XD, /* 871 */ IC_EVEX_L_W, /* 872 */ IC_EVEX_L_W, /* 873 */ IC_EVEX_L_W_XS, /* 874 */ IC_EVEX_L_W_XS, /* 875 */ IC_EVEX_L_W_XD, /* 876 */ IC_EVEX_L_W_XD, /* 877 */ IC_EVEX_L_W_XD, /* 878 */ IC_EVEX_L_W_XD, /* 879 */ IC_EVEX_L_OPSIZE, /* 880 */ IC_EVEX_L_OPSIZE, /* 881 */ IC_EVEX_L_OPSIZE, /* 882 */ IC_EVEX_L_OPSIZE, /* 883 */ IC_EVEX_L_OPSIZE, /* 884 */ IC_EVEX_L_OPSIZE, /* 885 */ IC_EVEX_L_OPSIZE, /* 886 */ IC_EVEX_L_OPSIZE, /* 887 */ IC_EVEX_L_W_OPSIZE, /* 888 */ IC_EVEX_L_W_OPSIZE, /* 889 */ IC_EVEX_L_W_OPSIZE, /* 890 */ IC_EVEX_L_W_OPSIZE, /* 891 */ IC_EVEX_L_W_OPSIZE, /* 892 */ IC_EVEX_L_W_OPSIZE, /* 893 */ IC_EVEX_L_W_OPSIZE, /* 894 */ IC_EVEX_L_W_OPSIZE, /* 895 */ IC_EVEX_L, /* 896 */ IC_EVEX_L, /* 897 */ IC_EVEX_L_XS, /* 898 */ IC_EVEX_L_XS, /* 899 */ IC_EVEX_L_XD, /* 900 */ IC_EVEX_L_XD, /* 901 */ IC_EVEX_L_XD, /* 902 */ IC_EVEX_L_XD, /* 903 */ IC_EVEX_L_W, /* 904 */ IC_EVEX_L_W, /* 905 */ IC_EVEX_L_W_XS, /* 906 */ IC_EVEX_L_W_XS, /* 907 */ IC_EVEX_L_W_XD, /* 908 */ IC_EVEX_L_W_XD, /* 909 */ IC_EVEX_L_W_XD, /* 910 */ IC_EVEX_L_W_XD, /* 911 */ IC_EVEX_L_OPSIZE, /* 912 */ IC_EVEX_L_OPSIZE, /* 913 */ IC_EVEX_L_OPSIZE, /* 914 */ IC_EVEX_L_OPSIZE, /* 915 */ IC_EVEX_L_OPSIZE, /* 916 */ IC_EVEX_L_OPSIZE, /* 917 */ IC_EVEX_L_OPSIZE, /* 918 */ IC_EVEX_L_OPSIZE, /* 919 */ IC_EVEX_L_W_OPSIZE, /* 920 */ IC_EVEX_L_W_OPSIZE, /* 921 */ IC_EVEX_L_W_OPSIZE, /* 922 */ IC_EVEX_L_W_OPSIZE, /* 923 */ IC_EVEX_L_W_OPSIZE, /* 924 */ IC_EVEX_L_W_OPSIZE, /* 925 */ IC_EVEX_L_W_OPSIZE, /* 926 */ IC_EVEX_L_W_OPSIZE, /* 927 */ IC_EVEX_L, /* 928 */ IC_EVEX_L, /* 929 */ IC_EVEX_L_XS, /* 930 */ IC_EVEX_L_XS, /* 931 */ IC_EVEX_L_XD, /* 932 */ IC_EVEX_L_XD, /* 933 */ IC_EVEX_L_XD, /* 934 */ IC_EVEX_L_XD, /* 935 */ IC_EVEX_L_W, /* 936 */ IC_EVEX_L_W, /* 937 */ IC_EVEX_L_W_XS, /* 938 */ IC_EVEX_L_W_XS, /* 939 */ IC_EVEX_L_W_XD, /* 940 */ IC_EVEX_L_W_XD, /* 941 */ IC_EVEX_L_W_XD, /* 942 */ IC_EVEX_L_W_XD, /* 943 */ IC_EVEX_L_OPSIZE, /* 944 */ IC_EVEX_L_OPSIZE, /* 945 */ IC_EVEX_L_OPSIZE, /* 946 */ IC_EVEX_L_OPSIZE, /* 947 */ IC_EVEX_L_OPSIZE, /* 948 */ IC_EVEX_L_OPSIZE, /* 949 */ IC_EVEX_L_OPSIZE, /* 950 */ IC_EVEX_L_OPSIZE, /* 951 */ IC_EVEX_L_W_OPSIZE, /* 952 */ IC_EVEX_L_W_OPSIZE, /* 953 */ IC_EVEX_L_W_OPSIZE, /* 954 */ IC_EVEX_L_W_OPSIZE, /* 955 */ IC_EVEX_L_W_OPSIZE, /* 956 */ IC_EVEX_L_W_OPSIZE, /* 957 */ IC_EVEX_L_W_OPSIZE, /* 958 */ IC_EVEX_L_W_OPSIZE, /* 959 */ IC_EVEX_L, /* 960 */ IC_EVEX_L, /* 961 */ IC_EVEX_L_XS, /* 962 */ IC_EVEX_L_XS, /* 963 */ IC_EVEX_L_XD, /* 964 */ IC_EVEX_L_XD, /* 965 */ IC_EVEX_L_XD, /* 966 */ IC_EVEX_L_XD, /* 967 */ IC_EVEX_L_W, /* 968 */ IC_EVEX_L_W, /* 969 */ IC_EVEX_L_W_XS, /* 970 */ IC_EVEX_L_W_XS, /* 971 */ IC_EVEX_L_W_XD, /* 972 */ IC_EVEX_L_W_XD, /* 973 */ IC_EVEX_L_W_XD, /* 974 */ IC_EVEX_L_W_XD, /* 975 */ IC_EVEX_L_OPSIZE, /* 976 */ IC_EVEX_L_OPSIZE, /* 977 */ IC_EVEX_L_OPSIZE, /* 978 */ IC_EVEX_L_OPSIZE, /* 979 */ IC_EVEX_L_OPSIZE, /* 980 */ IC_EVEX_L_OPSIZE, /* 981 */ IC_EVEX_L_OPSIZE, /* 982 */ IC_EVEX_L_OPSIZE, /* 983 */ IC_EVEX_L_W_OPSIZE, /* 984 */ IC_EVEX_L_W_OPSIZE, /* 985 */ IC_EVEX_L_W_OPSIZE, /* 986 */ IC_EVEX_L_W_OPSIZE, /* 987 */ IC_EVEX_L_W_OPSIZE, /* 988 */ IC_EVEX_L_W_OPSIZE, /* 989 */ IC_EVEX_L_W_OPSIZE, /* 990 */ IC_EVEX_L_W_OPSIZE, /* 991 */ IC_EVEX_L, /* 992 */ IC_EVEX_L, /* 993 */ IC_EVEX_L_XS, /* 994 */ IC_EVEX_L_XS, /* 995 */ IC_EVEX_L_XD, /* 996 */ IC_EVEX_L_XD, /* 997 */ IC_EVEX_L_XD, /* 998 */ IC_EVEX_L_XD, /* 999 */ IC_EVEX_L_W, /* 1000 */ IC_EVEX_L_W, /* 1001 */ IC_EVEX_L_W_XS, /* 1002 */ IC_EVEX_L_W_XS, /* 1003 */ IC_EVEX_L_W_XD, /* 1004 */ IC_EVEX_L_W_XD, /* 1005 */ IC_EVEX_L_W_XD, /* 1006 */ IC_EVEX_L_W_XD, /* 1007 */ IC_EVEX_L_OPSIZE, /* 1008 */ IC_EVEX_L_OPSIZE, /* 1009 */ IC_EVEX_L_OPSIZE, /* 1010 */ IC_EVEX_L_OPSIZE, /* 1011 */ IC_EVEX_L_OPSIZE, /* 1012 */ IC_EVEX_L_OPSIZE, /* 1013 */ IC_EVEX_L_OPSIZE, /* 1014 */ IC_EVEX_L_OPSIZE, /* 1015 */ IC_EVEX_L_W_OPSIZE, /* 1016 */ IC_EVEX_L_W_OPSIZE, /* 1017 */ IC_EVEX_L_W_OPSIZE, /* 1018 */ IC_EVEX_L_W_OPSIZE, /* 1019 */ IC_EVEX_L_W_OPSIZE, /* 1020 */ IC_EVEX_L_W_OPSIZE, /* 1021 */ IC_EVEX_L_W_OPSIZE, /* 1022 */ IC_EVEX_L_W_OPSIZE, /* 1023 */ IC, /* 1024 */ IC_64BIT, /* 1025 */ IC_XS, /* 1026 */ IC_64BIT_XS, /* 1027 */ IC_XD, /* 1028 */ IC_64BIT_XD, /* 1029 */ IC_XS, /* 1030 */ IC_64BIT_XS, /* 1031 */ IC, /* 1032 */ IC_64BIT_REXW, /* 1033 */ IC_XS, /* 1034 */ IC_64BIT_REXW_XS, /* 1035 */ IC_XD, /* 1036 */ IC_64BIT_REXW_XD, /* 1037 */ IC_XS, /* 1038 */ IC_64BIT_REXW_XS, /* 1039 */ IC_OPSIZE, /* 1040 */ IC_64BIT_OPSIZE, /* 1041 */ IC_XS_OPSIZE, /* 1042 */ IC_64BIT_XS_OPSIZE, /* 1043 */ IC_XD_OPSIZE, /* 1044 */ IC_64BIT_XD_OPSIZE, /* 1045 */ IC_XS_OPSIZE, /* 1046 */ IC_64BIT_XD_OPSIZE, /* 1047 */ IC_OPSIZE, /* 1048 */ IC_64BIT_REXW_OPSIZE, /* 1049 */ IC_XS_OPSIZE, /* 1050 */ IC_64BIT_REXW_XS, /* 1051 */ IC_XD_OPSIZE, /* 1052 */ IC_64BIT_REXW_XD, /* 1053 */ IC_XS_OPSIZE, /* 1054 */ IC_64BIT_REXW_XS, /* 1055 */ IC_ADSIZE, /* 1056 */ IC_64BIT_ADSIZE, /* 1057 */ IC_XS_ADSIZE, /* 1058 */ IC_64BIT_XS_ADSIZE, /* 1059 */ IC_XD_ADSIZE, /* 1060 */ IC_64BIT_XD_ADSIZE, /* 1061 */ IC_XS_ADSIZE, /* 1062 */ IC_64BIT_XD_ADSIZE, /* 1063 */ IC_ADSIZE, /* 1064 */ IC_64BIT_REXW_ADSIZE, /* 1065 */ IC_XS_ADSIZE, /* 1066 */ IC_64BIT_REXW_XS, /* 1067 */ IC_XD_ADSIZE, /* 1068 */ IC_64BIT_REXW_XD, /* 1069 */ IC_XS_ADSIZE, /* 1070 */ IC_64BIT_REXW_XS, /* 1071 */ IC_OPSIZE_ADSIZE, /* 1072 */ IC_64BIT_OPSIZE_ADSIZE, /* 1073 */ IC_XS_OPSIZE, /* 1074 */ IC_64BIT_XS_OPSIZE, /* 1075 */ IC_XD_OPSIZE, /* 1076 */ IC_64BIT_XD_OPSIZE, /* 1077 */ IC_XS_OPSIZE, /* 1078 */ IC_64BIT_XD_OPSIZE, /* 1079 */ IC_OPSIZE_ADSIZE, /* 1080 */ IC_64BIT_REXW_OPSIZE, /* 1081 */ IC_XS_OPSIZE, /* 1082 */ IC_64BIT_REXW_XS, /* 1083 */ IC_XD_OPSIZE, /* 1084 */ IC_64BIT_REXW_XD, /* 1085 */ IC_XS_OPSIZE, /* 1086 */ IC_64BIT_REXW_XS, /* 1087 */ IC_VEX, /* 1088 */ IC_VEX, /* 1089 */ IC_VEX_XS, /* 1090 */ IC_VEX_XS, /* 1091 */ IC_VEX_XD, /* 1092 */ IC_VEX_XD, /* 1093 */ IC_VEX_XD, /* 1094 */ IC_VEX_XD, /* 1095 */ IC_VEX_W, /* 1096 */ IC_VEX_W, /* 1097 */ IC_VEX_W_XS, /* 1098 */ IC_VEX_W_XS, /* 1099 */ IC_VEX_W_XD, /* 1100 */ IC_VEX_W_XD, /* 1101 */ IC_VEX_W_XD, /* 1102 */ IC_VEX_W_XD, /* 1103 */ IC_VEX_OPSIZE, /* 1104 */ IC_VEX_OPSIZE, /* 1105 */ IC_VEX_OPSIZE, /* 1106 */ IC_VEX_OPSIZE, /* 1107 */ IC_VEX_OPSIZE, /* 1108 */ IC_VEX_OPSIZE, /* 1109 */ IC_VEX_OPSIZE, /* 1110 */ IC_VEX_OPSIZE, /* 1111 */ IC_VEX_W_OPSIZE, /* 1112 */ IC_VEX_W_OPSIZE, /* 1113 */ IC_VEX_W_OPSIZE, /* 1114 */ IC_VEX_W_OPSIZE, /* 1115 */ IC_VEX_W_OPSIZE, /* 1116 */ IC_VEX_W_OPSIZE, /* 1117 */ IC_VEX_W_OPSIZE, /* 1118 */ IC_VEX_W_OPSIZE, /* 1119 */ IC_VEX, /* 1120 */ IC_VEX, /* 1121 */ IC_VEX_XS, /* 1122 */ IC_VEX_XS, /* 1123 */ IC_VEX_XD, /* 1124 */ IC_VEX_XD, /* 1125 */ IC_VEX_XD, /* 1126 */ IC_VEX_XD, /* 1127 */ IC_VEX_W, /* 1128 */ IC_VEX_W, /* 1129 */ IC_VEX_W_XS, /* 1130 */ IC_VEX_W_XS, /* 1131 */ IC_VEX_W_XD, /* 1132 */ IC_VEX_W_XD, /* 1133 */ IC_VEX_W_XD, /* 1134 */ IC_VEX_W_XD, /* 1135 */ IC_VEX_OPSIZE, /* 1136 */ IC_VEX_OPSIZE, /* 1137 */ IC_VEX_OPSIZE, /* 1138 */ IC_VEX_OPSIZE, /* 1139 */ IC_VEX_OPSIZE, /* 1140 */ IC_VEX_OPSIZE, /* 1141 */ IC_VEX_OPSIZE, /* 1142 */ IC_VEX_OPSIZE, /* 1143 */ IC_VEX_W_OPSIZE, /* 1144 */ IC_VEX_W_OPSIZE, /* 1145 */ IC_VEX_W_OPSIZE, /* 1146 */ IC_VEX_W_OPSIZE, /* 1147 */ IC_VEX_W_OPSIZE, /* 1148 */ IC_VEX_W_OPSIZE, /* 1149 */ IC_VEX_W_OPSIZE, /* 1150 */ IC_VEX_W_OPSIZE, /* 1151 */ IC_VEX_L, /* 1152 */ IC_VEX_L, /* 1153 */ IC_VEX_L_XS, /* 1154 */ IC_VEX_L_XS, /* 1155 */ IC_VEX_L_XD, /* 1156 */ IC_VEX_L_XD, /* 1157 */ IC_VEX_L_XD, /* 1158 */ IC_VEX_L_XD, /* 1159 */ IC_VEX_L_W, /* 1160 */ IC_VEX_L_W, /* 1161 */ IC_VEX_L_W_XS, /* 1162 */ IC_VEX_L_W_XS, /* 1163 */ IC_VEX_L_W_XD, /* 1164 */ IC_VEX_L_W_XD, /* 1165 */ IC_VEX_L_W_XD, /* 1166 */ IC_VEX_L_W_XD, /* 1167 */ IC_VEX_L_OPSIZE, /* 1168 */ IC_VEX_L_OPSIZE, /* 1169 */ IC_VEX_L_OPSIZE, /* 1170 */ IC_VEX_L_OPSIZE, /* 1171 */ IC_VEX_L_OPSIZE, /* 1172 */ IC_VEX_L_OPSIZE, /* 1173 */ IC_VEX_L_OPSIZE, /* 1174 */ IC_VEX_L_OPSIZE, /* 1175 */ IC_VEX_L_W_OPSIZE, /* 1176 */ IC_VEX_L_W_OPSIZE, /* 1177 */ IC_VEX_L_W_OPSIZE, /* 1178 */ IC_VEX_L_W_OPSIZE, /* 1179 */ IC_VEX_L_W_OPSIZE, /* 1180 */ IC_VEX_L_W_OPSIZE, /* 1181 */ IC_VEX_L_W_OPSIZE, /* 1182 */ IC_VEX_L_W_OPSIZE, /* 1183 */ IC_VEX_L, /* 1184 */ IC_VEX_L, /* 1185 */ IC_VEX_L_XS, /* 1186 */ IC_VEX_L_XS, /* 1187 */ IC_VEX_L_XD, /* 1188 */ IC_VEX_L_XD, /* 1189 */ IC_VEX_L_XD, /* 1190 */ IC_VEX_L_XD, /* 1191 */ IC_VEX_L_W, /* 1192 */ IC_VEX_L_W, /* 1193 */ IC_VEX_L_W_XS, /* 1194 */ IC_VEX_L_W_XS, /* 1195 */ IC_VEX_L_W_XD, /* 1196 */ IC_VEX_L_W_XD, /* 1197 */ IC_VEX_L_W_XD, /* 1198 */ IC_VEX_L_W_XD, /* 1199 */ IC_VEX_L_OPSIZE, /* 1200 */ IC_VEX_L_OPSIZE, /* 1201 */ IC_VEX_L_OPSIZE, /* 1202 */ IC_VEX_L_OPSIZE, /* 1203 */ IC_VEX_L_OPSIZE, /* 1204 */ IC_VEX_L_OPSIZE, /* 1205 */ IC_VEX_L_OPSIZE, /* 1206 */ IC_VEX_L_OPSIZE, /* 1207 */ IC_VEX_L_W_OPSIZE, /* 1208 */ IC_VEX_L_W_OPSIZE, /* 1209 */ IC_VEX_L_W_OPSIZE, /* 1210 */ IC_VEX_L_W_OPSIZE, /* 1211 */ IC_VEX_L_W_OPSIZE, /* 1212 */ IC_VEX_L_W_OPSIZE, /* 1213 */ IC_VEX_L_W_OPSIZE, /* 1214 */ IC_VEX_L_W_OPSIZE, /* 1215 */ IC_VEX_L, /* 1216 */ IC_VEX_L, /* 1217 */ IC_VEX_L_XS, /* 1218 */ IC_VEX_L_XS, /* 1219 */ IC_VEX_L_XD, /* 1220 */ IC_VEX_L_XD, /* 1221 */ IC_VEX_L_XD, /* 1222 */ IC_VEX_L_XD, /* 1223 */ IC_VEX_L_W, /* 1224 */ IC_VEX_L_W, /* 1225 */ IC_VEX_L_W_XS, /* 1226 */ IC_VEX_L_W_XS, /* 1227 */ IC_VEX_L_W_XD, /* 1228 */ IC_VEX_L_W_XD, /* 1229 */ IC_VEX_L_W_XD, /* 1230 */ IC_VEX_L_W_XD, /* 1231 */ IC_VEX_L_OPSIZE, /* 1232 */ IC_VEX_L_OPSIZE, /* 1233 */ IC_VEX_L_OPSIZE, /* 1234 */ IC_VEX_L_OPSIZE, /* 1235 */ IC_VEX_L_OPSIZE, /* 1236 */ IC_VEX_L_OPSIZE, /* 1237 */ IC_VEX_L_OPSIZE, /* 1238 */ IC_VEX_L_OPSIZE, /* 1239 */ IC_VEX_L_W_OPSIZE, /* 1240 */ IC_VEX_L_W_OPSIZE, /* 1241 */ IC_VEX_L_W_OPSIZE, /* 1242 */ IC_VEX_L_W_OPSIZE, /* 1243 */ IC_VEX_L_W_OPSIZE, /* 1244 */ IC_VEX_L_W_OPSIZE, /* 1245 */ IC_VEX_L_W_OPSIZE, /* 1246 */ IC_VEX_L_W_OPSIZE, /* 1247 */ IC_VEX_L, /* 1248 */ IC_VEX_L, /* 1249 */ IC_VEX_L_XS, /* 1250 */ IC_VEX_L_XS, /* 1251 */ IC_VEX_L_XD, /* 1252 */ IC_VEX_L_XD, /* 1253 */ IC_VEX_L_XD, /* 1254 */ IC_VEX_L_XD, /* 1255 */ IC_VEX_L_W, /* 1256 */ IC_VEX_L_W, /* 1257 */ IC_VEX_L_W_XS, /* 1258 */ IC_VEX_L_W_XS, /* 1259 */ IC_VEX_L_W_XD, /* 1260 */ IC_VEX_L_W_XD, /* 1261 */ IC_VEX_L_W_XD, /* 1262 */ IC_VEX_L_W_XD, /* 1263 */ IC_VEX_L_OPSIZE, /* 1264 */ IC_VEX_L_OPSIZE, /* 1265 */ IC_VEX_L_OPSIZE, /* 1266 */ IC_VEX_L_OPSIZE, /* 1267 */ IC_VEX_L_OPSIZE, /* 1268 */ IC_VEX_L_OPSIZE, /* 1269 */ IC_VEX_L_OPSIZE, /* 1270 */ IC_VEX_L_OPSIZE, /* 1271 */ IC_VEX_L_W_OPSIZE, /* 1272 */ IC_VEX_L_W_OPSIZE, /* 1273 */ IC_VEX_L_W_OPSIZE, /* 1274 */ IC_VEX_L_W_OPSIZE, /* 1275 */ IC_VEX_L_W_OPSIZE, /* 1276 */ IC_VEX_L_W_OPSIZE, /* 1277 */ IC_VEX_L_W_OPSIZE, /* 1278 */ IC_VEX_L_W_OPSIZE, /* 1279 */ IC_EVEX_L2, /* 1280 */ IC_EVEX_L2, /* 1281 */ IC_EVEX_L2_XS, /* 1282 */ IC_EVEX_L2_XS, /* 1283 */ IC_EVEX_L2_XD, /* 1284 */ IC_EVEX_L2_XD, /* 1285 */ IC_EVEX_L2_XD, /* 1286 */ IC_EVEX_L2_XD, /* 1287 */ IC_EVEX_L2_W, /* 1288 */ IC_EVEX_L2_W, /* 1289 */ IC_EVEX_L2_W_XS, /* 1290 */ IC_EVEX_L2_W_XS, /* 1291 */ IC_EVEX_L2_W_XD, /* 1292 */ IC_EVEX_L2_W_XD, /* 1293 */ IC_EVEX_L2_W_XD, /* 1294 */ IC_EVEX_L2_W_XD, /* 1295 */ IC_EVEX_L2_OPSIZE, /* 1296 */ IC_EVEX_L2_OPSIZE, /* 1297 */ IC_EVEX_L2_OPSIZE, /* 1298 */ IC_EVEX_L2_OPSIZE, /* 1299 */ IC_EVEX_L2_OPSIZE, /* 1300 */ IC_EVEX_L2_OPSIZE, /* 1301 */ IC_EVEX_L2_OPSIZE, /* 1302 */ IC_EVEX_L2_OPSIZE, /* 1303 */ IC_EVEX_L2_W_OPSIZE, /* 1304 */ IC_EVEX_L2_W_OPSIZE, /* 1305 */ IC_EVEX_L2_W_OPSIZE, /* 1306 */ IC_EVEX_L2_W_OPSIZE, /* 1307 */ IC_EVEX_L2_W_OPSIZE, /* 1308 */ IC_EVEX_L2_W_OPSIZE, /* 1309 */ IC_EVEX_L2_W_OPSIZE, /* 1310 */ IC_EVEX_L2_W_OPSIZE, /* 1311 */ IC_EVEX_L2, /* 1312 */ IC_EVEX_L2, /* 1313 */ IC_EVEX_L2_XS, /* 1314 */ IC_EVEX_L2_XS, /* 1315 */ IC_EVEX_L2_XD, /* 1316 */ IC_EVEX_L2_XD, /* 1317 */ IC_EVEX_L2_XD, /* 1318 */ IC_EVEX_L2_XD, /* 1319 */ IC_EVEX_L2_W, /* 1320 */ IC_EVEX_L2_W, /* 1321 */ IC_EVEX_L2_W_XS, /* 1322 */ IC_EVEX_L2_W_XS, /* 1323 */ IC_EVEX_L2_W_XD, /* 1324 */ IC_EVEX_L2_W_XD, /* 1325 */ IC_EVEX_L2_W_XD, /* 1326 */ IC_EVEX_L2_W_XD, /* 1327 */ IC_EVEX_L2_OPSIZE, /* 1328 */ IC_EVEX_L2_OPSIZE, /* 1329 */ IC_EVEX_L2_OPSIZE, /* 1330 */ IC_EVEX_L2_OPSIZE, /* 1331 */ IC_EVEX_L2_OPSIZE, /* 1332 */ IC_EVEX_L2_OPSIZE, /* 1333 */ IC_EVEX_L2_OPSIZE, /* 1334 */ IC_EVEX_L2_OPSIZE, /* 1335 */ IC_EVEX_L2_W_OPSIZE, /* 1336 */ IC_EVEX_L2_W_OPSIZE, /* 1337 */ IC_EVEX_L2_W_OPSIZE, /* 1338 */ IC_EVEX_L2_W_OPSIZE, /* 1339 */ IC_EVEX_L2_W_OPSIZE, /* 1340 */ IC_EVEX_L2_W_OPSIZE, /* 1341 */ IC_EVEX_L2_W_OPSIZE, /* 1342 */ IC_EVEX_L2_W_OPSIZE, /* 1343 */ IC_EVEX_L2, /* 1344 */ IC_EVEX_L2, /* 1345 */ IC_EVEX_L2_XS, /* 1346 */ IC_EVEX_L2_XS, /* 1347 */ IC_EVEX_L2_XD, /* 1348 */ IC_EVEX_L2_XD, /* 1349 */ IC_EVEX_L2_XD, /* 1350 */ IC_EVEX_L2_XD, /* 1351 */ IC_EVEX_L2_W, /* 1352 */ IC_EVEX_L2_W, /* 1353 */ IC_EVEX_L2_W_XS, /* 1354 */ IC_EVEX_L2_W_XS, /* 1355 */ IC_EVEX_L2_W_XD, /* 1356 */ IC_EVEX_L2_W_XD, /* 1357 */ IC_EVEX_L2_W_XD, /* 1358 */ IC_EVEX_L2_W_XD, /* 1359 */ IC_EVEX_L2_OPSIZE, /* 1360 */ IC_EVEX_L2_OPSIZE, /* 1361 */ IC_EVEX_L2_OPSIZE, /* 1362 */ IC_EVEX_L2_OPSIZE, /* 1363 */ IC_EVEX_L2_OPSIZE, /* 1364 */ IC_EVEX_L2_OPSIZE, /* 1365 */ IC_EVEX_L2_OPSIZE, /* 1366 */ IC_EVEX_L2_OPSIZE, /* 1367 */ IC_EVEX_L2_W_OPSIZE, /* 1368 */ IC_EVEX_L2_W_OPSIZE, /* 1369 */ IC_EVEX_L2_W_OPSIZE, /* 1370 */ IC_EVEX_L2_W_OPSIZE, /* 1371 */ IC_EVEX_L2_W_OPSIZE, /* 1372 */ IC_EVEX_L2_W_OPSIZE, /* 1373 */ IC_EVEX_L2_W_OPSIZE, /* 1374 */ IC_EVEX_L2_W_OPSIZE, /* 1375 */ IC_EVEX_L2, /* 1376 */ IC_EVEX_L2, /* 1377 */ IC_EVEX_L2_XS, /* 1378 */ IC_EVEX_L2_XS, /* 1379 */ IC_EVEX_L2_XD, /* 1380 */ IC_EVEX_L2_XD, /* 1381 */ IC_EVEX_L2_XD, /* 1382 */ IC_EVEX_L2_XD, /* 1383 */ IC_EVEX_L2_W, /* 1384 */ IC_EVEX_L2_W, /* 1385 */ IC_EVEX_L2_W_XS, /* 1386 */ IC_EVEX_L2_W_XS, /* 1387 */ IC_EVEX_L2_W_XD, /* 1388 */ IC_EVEX_L2_W_XD, /* 1389 */ IC_EVEX_L2_W_XD, /* 1390 */ IC_EVEX_L2_W_XD, /* 1391 */ IC_EVEX_L2_OPSIZE, /* 1392 */ IC_EVEX_L2_OPSIZE, /* 1393 */ IC_EVEX_L2_OPSIZE, /* 1394 */ IC_EVEX_L2_OPSIZE, /* 1395 */ IC_EVEX_L2_OPSIZE, /* 1396 */ IC_EVEX_L2_OPSIZE, /* 1397 */ IC_EVEX_L2_OPSIZE, /* 1398 */ IC_EVEX_L2_OPSIZE, /* 1399 */ IC_EVEX_L2_W_OPSIZE, /* 1400 */ IC_EVEX_L2_W_OPSIZE, /* 1401 */ IC_EVEX_L2_W_OPSIZE, /* 1402 */ IC_EVEX_L2_W_OPSIZE, /* 1403 */ IC_EVEX_L2_W_OPSIZE, /* 1404 */ IC_EVEX_L2_W_OPSIZE, /* 1405 */ IC_EVEX_L2_W_OPSIZE, /* 1406 */ IC_EVEX_L2_W_OPSIZE, /* 1407 */ IC_EVEX_L2, /* 1408 */ IC_EVEX_L2, /* 1409 */ IC_EVEX_L2_XS, /* 1410 */ IC_EVEX_L2_XS, /* 1411 */ IC_EVEX_L2_XD, /* 1412 */ IC_EVEX_L2_XD, /* 1413 */ IC_EVEX_L2_XD, /* 1414 */ IC_EVEX_L2_XD, /* 1415 */ IC_EVEX_L2_W, /* 1416 */ IC_EVEX_L2_W, /* 1417 */ IC_EVEX_L2_W_XS, /* 1418 */ IC_EVEX_L2_W_XS, /* 1419 */ IC_EVEX_L2_W_XD, /* 1420 */ IC_EVEX_L2_W_XD, /* 1421 */ IC_EVEX_L2_W_XD, /* 1422 */ IC_EVEX_L2_W_XD, /* 1423 */ IC_EVEX_L2_OPSIZE, /* 1424 */ IC_EVEX_L2_OPSIZE, /* 1425 */ IC_EVEX_L2_OPSIZE, /* 1426 */ IC_EVEX_L2_OPSIZE, /* 1427 */ IC_EVEX_L2_OPSIZE, /* 1428 */ IC_EVEX_L2_OPSIZE, /* 1429 */ IC_EVEX_L2_OPSIZE, /* 1430 */ IC_EVEX_L2_OPSIZE, /* 1431 */ IC_EVEX_L2_W_OPSIZE, /* 1432 */ IC_EVEX_L2_W_OPSIZE, /* 1433 */ IC_EVEX_L2_W_OPSIZE, /* 1434 */ IC_EVEX_L2_W_OPSIZE, /* 1435 */ IC_EVEX_L2_W_OPSIZE, /* 1436 */ IC_EVEX_L2_W_OPSIZE, /* 1437 */ IC_EVEX_L2_W_OPSIZE, /* 1438 */ IC_EVEX_L2_W_OPSIZE, /* 1439 */ IC_EVEX_L2, /* 1440 */ IC_EVEX_L2, /* 1441 */ IC_EVEX_L2_XS, /* 1442 */ IC_EVEX_L2_XS, /* 1443 */ IC_EVEX_L2_XD, /* 1444 */ IC_EVEX_L2_XD, /* 1445 */ IC_EVEX_L2_XD, /* 1446 */ IC_EVEX_L2_XD, /* 1447 */ IC_EVEX_L2_W, /* 1448 */ IC_EVEX_L2_W, /* 1449 */ IC_EVEX_L2_W_XS, /* 1450 */ IC_EVEX_L2_W_XS, /* 1451 */ IC_EVEX_L2_W_XD, /* 1452 */ IC_EVEX_L2_W_XD, /* 1453 */ IC_EVEX_L2_W_XD, /* 1454 */ IC_EVEX_L2_W_XD, /* 1455 */ IC_EVEX_L2_OPSIZE, /* 1456 */ IC_EVEX_L2_OPSIZE, /* 1457 */ IC_EVEX_L2_OPSIZE, /* 1458 */ IC_EVEX_L2_OPSIZE, /* 1459 */ IC_EVEX_L2_OPSIZE, /* 1460 */ IC_EVEX_L2_OPSIZE, /* 1461 */ IC_EVEX_L2_OPSIZE, /* 1462 */ IC_EVEX_L2_OPSIZE, /* 1463 */ IC_EVEX_L2_W_OPSIZE, /* 1464 */ IC_EVEX_L2_W_OPSIZE, /* 1465 */ IC_EVEX_L2_W_OPSIZE, /* 1466 */ IC_EVEX_L2_W_OPSIZE, /* 1467 */ IC_EVEX_L2_W_OPSIZE, /* 1468 */ IC_EVEX_L2_W_OPSIZE, /* 1469 */ IC_EVEX_L2_W_OPSIZE, /* 1470 */ IC_EVEX_L2_W_OPSIZE, /* 1471 */ IC_EVEX_L2, /* 1472 */ IC_EVEX_L2, /* 1473 */ IC_EVEX_L2_XS, /* 1474 */ IC_EVEX_L2_XS, /* 1475 */ IC_EVEX_L2_XD, /* 1476 */ IC_EVEX_L2_XD, /* 1477 */ IC_EVEX_L2_XD, /* 1478 */ IC_EVEX_L2_XD, /* 1479 */ IC_EVEX_L2_W, /* 1480 */ IC_EVEX_L2_W, /* 1481 */ IC_EVEX_L2_W_XS, /* 1482 */ IC_EVEX_L2_W_XS, /* 1483 */ IC_EVEX_L2_W_XD, /* 1484 */ IC_EVEX_L2_W_XD, /* 1485 */ IC_EVEX_L2_W_XD, /* 1486 */ IC_EVEX_L2_W_XD, /* 1487 */ IC_EVEX_L2_OPSIZE, /* 1488 */ IC_EVEX_L2_OPSIZE, /* 1489 */ IC_EVEX_L2_OPSIZE, /* 1490 */ IC_EVEX_L2_OPSIZE, /* 1491 */ IC_EVEX_L2_OPSIZE, /* 1492 */ IC_EVEX_L2_OPSIZE, /* 1493 */ IC_EVEX_L2_OPSIZE, /* 1494 */ IC_EVEX_L2_OPSIZE, /* 1495 */ IC_EVEX_L2_W_OPSIZE, /* 1496 */ IC_EVEX_L2_W_OPSIZE, /* 1497 */ IC_EVEX_L2_W_OPSIZE, /* 1498 */ IC_EVEX_L2_W_OPSIZE, /* 1499 */ IC_EVEX_L2_W_OPSIZE, /* 1500 */ IC_EVEX_L2_W_OPSIZE, /* 1501 */ IC_EVEX_L2_W_OPSIZE, /* 1502 */ IC_EVEX_L2_W_OPSIZE, /* 1503 */ IC_EVEX_L2, /* 1504 */ IC_EVEX_L2, /* 1505 */ IC_EVEX_L2_XS, /* 1506 */ IC_EVEX_L2_XS, /* 1507 */ IC_EVEX_L2_XD, /* 1508 */ IC_EVEX_L2_XD, /* 1509 */ IC_EVEX_L2_XD, /* 1510 */ IC_EVEX_L2_XD, /* 1511 */ IC_EVEX_L2_W, /* 1512 */ IC_EVEX_L2_W, /* 1513 */ IC_EVEX_L2_W_XS, /* 1514 */ IC_EVEX_L2_W_XS, /* 1515 */ IC_EVEX_L2_W_XD, /* 1516 */ IC_EVEX_L2_W_XD, /* 1517 */ IC_EVEX_L2_W_XD, /* 1518 */ IC_EVEX_L2_W_XD, /* 1519 */ IC_EVEX_L2_OPSIZE, /* 1520 */ IC_EVEX_L2_OPSIZE, /* 1521 */ IC_EVEX_L2_OPSIZE, /* 1522 */ IC_EVEX_L2_OPSIZE, /* 1523 */ IC_EVEX_L2_OPSIZE, /* 1524 */ IC_EVEX_L2_OPSIZE, /* 1525 */ IC_EVEX_L2_OPSIZE, /* 1526 */ IC_EVEX_L2_OPSIZE, /* 1527 */ IC_EVEX_L2_W_OPSIZE, /* 1528 */ IC_EVEX_L2_W_OPSIZE, /* 1529 */ IC_EVEX_L2_W_OPSIZE, /* 1530 */ IC_EVEX_L2_W_OPSIZE, /* 1531 */ IC_EVEX_L2_W_OPSIZE, /* 1532 */ IC_EVEX_L2_W_OPSIZE, /* 1533 */ IC_EVEX_L2_W_OPSIZE, /* 1534 */ IC_EVEX_L2_W_OPSIZE, /* 1535 */ IC, /* 1536 */ IC_64BIT, /* 1537 */ IC_XS, /* 1538 */ IC_64BIT_XS, /* 1539 */ IC_XD, /* 1540 */ IC_64BIT_XD, /* 1541 */ IC_XS, /* 1542 */ IC_64BIT_XS, /* 1543 */ IC, /* 1544 */ IC_64BIT_REXW, /* 1545 */ IC_XS, /* 1546 */ IC_64BIT_REXW_XS, /* 1547 */ IC_XD, /* 1548 */ IC_64BIT_REXW_XD, /* 1549 */ IC_XS, /* 1550 */ IC_64BIT_REXW_XS, /* 1551 */ IC_OPSIZE, /* 1552 */ IC_64BIT_OPSIZE, /* 1553 */ IC_XS_OPSIZE, /* 1554 */ IC_64BIT_XS_OPSIZE, /* 1555 */ IC_XD_OPSIZE, /* 1556 */ IC_64BIT_XD_OPSIZE, /* 1557 */ IC_XS_OPSIZE, /* 1558 */ IC_64BIT_XD_OPSIZE, /* 1559 */ IC_OPSIZE, /* 1560 */ IC_64BIT_REXW_OPSIZE, /* 1561 */ IC_XS_OPSIZE, /* 1562 */ IC_64BIT_REXW_XS, /* 1563 */ IC_XD_OPSIZE, /* 1564 */ IC_64BIT_REXW_XD, /* 1565 */ IC_XS_OPSIZE, /* 1566 */ IC_64BIT_REXW_XS, /* 1567 */ IC_ADSIZE, /* 1568 */ IC_64BIT_ADSIZE, /* 1569 */ IC_XS_ADSIZE, /* 1570 */ IC_64BIT_XS_ADSIZE, /* 1571 */ IC_XD_ADSIZE, /* 1572 */ IC_64BIT_XD_ADSIZE, /* 1573 */ IC_XS_ADSIZE, /* 1574 */ IC_64BIT_XD_ADSIZE, /* 1575 */ IC_ADSIZE, /* 1576 */ IC_64BIT_REXW_ADSIZE, /* 1577 */ IC_XS_ADSIZE, /* 1578 */ IC_64BIT_REXW_XS, /* 1579 */ IC_XD_ADSIZE, /* 1580 */ IC_64BIT_REXW_XD, /* 1581 */ IC_XS_ADSIZE, /* 1582 */ IC_64BIT_REXW_XS, /* 1583 */ IC_OPSIZE_ADSIZE, /* 1584 */ IC_64BIT_OPSIZE_ADSIZE, /* 1585 */ IC_XS_OPSIZE, /* 1586 */ IC_64BIT_XS_OPSIZE, /* 1587 */ IC_XD_OPSIZE, /* 1588 */ IC_64BIT_XD_OPSIZE, /* 1589 */ IC_XS_OPSIZE, /* 1590 */ IC_64BIT_XD_OPSIZE, /* 1591 */ IC_OPSIZE_ADSIZE, /* 1592 */ IC_64BIT_REXW_OPSIZE, /* 1593 */ IC_XS_OPSIZE, /* 1594 */ IC_64BIT_REXW_XS, /* 1595 */ IC_XD_OPSIZE, /* 1596 */ IC_64BIT_REXW_XD, /* 1597 */ IC_XS_OPSIZE, /* 1598 */ IC_64BIT_REXW_XS, /* 1599 */ IC_VEX, /* 1600 */ IC_VEX, /* 1601 */ IC_VEX_XS, /* 1602 */ IC_VEX_XS, /* 1603 */ IC_VEX_XD, /* 1604 */ IC_VEX_XD, /* 1605 */ IC_VEX_XD, /* 1606 */ IC_VEX_XD, /* 1607 */ IC_VEX_W, /* 1608 */ IC_VEX_W, /* 1609 */ IC_VEX_W_XS, /* 1610 */ IC_VEX_W_XS, /* 1611 */ IC_VEX_W_XD, /* 1612 */ IC_VEX_W_XD, /* 1613 */ IC_VEX_W_XD, /* 1614 */ IC_VEX_W_XD, /* 1615 */ IC_VEX_OPSIZE, /* 1616 */ IC_VEX_OPSIZE, /* 1617 */ IC_VEX_OPSIZE, /* 1618 */ IC_VEX_OPSIZE, /* 1619 */ IC_VEX_OPSIZE, /* 1620 */ IC_VEX_OPSIZE, /* 1621 */ IC_VEX_OPSIZE, /* 1622 */ IC_VEX_OPSIZE, /* 1623 */ IC_VEX_W_OPSIZE, /* 1624 */ IC_VEX_W_OPSIZE, /* 1625 */ IC_VEX_W_OPSIZE, /* 1626 */ IC_VEX_W_OPSIZE, /* 1627 */ IC_VEX_W_OPSIZE, /* 1628 */ IC_VEX_W_OPSIZE, /* 1629 */ IC_VEX_W_OPSIZE, /* 1630 */ IC_VEX_W_OPSIZE, /* 1631 */ IC_VEX, /* 1632 */ IC_VEX, /* 1633 */ IC_VEX_XS, /* 1634 */ IC_VEX_XS, /* 1635 */ IC_VEX_XD, /* 1636 */ IC_VEX_XD, /* 1637 */ IC_VEX_XD, /* 1638 */ IC_VEX_XD, /* 1639 */ IC_VEX_W, /* 1640 */ IC_VEX_W, /* 1641 */ IC_VEX_W_XS, /* 1642 */ IC_VEX_W_XS, /* 1643 */ IC_VEX_W_XD, /* 1644 */ IC_VEX_W_XD, /* 1645 */ IC_VEX_W_XD, /* 1646 */ IC_VEX_W_XD, /* 1647 */ IC_VEX_OPSIZE, /* 1648 */ IC_VEX_OPSIZE, /* 1649 */ IC_VEX_OPSIZE, /* 1650 */ IC_VEX_OPSIZE, /* 1651 */ IC_VEX_OPSIZE, /* 1652 */ IC_VEX_OPSIZE, /* 1653 */ IC_VEX_OPSIZE, /* 1654 */ IC_VEX_OPSIZE, /* 1655 */ IC_VEX_W_OPSIZE, /* 1656 */ IC_VEX_W_OPSIZE, /* 1657 */ IC_VEX_W_OPSIZE, /* 1658 */ IC_VEX_W_OPSIZE, /* 1659 */ IC_VEX_W_OPSIZE, /* 1660 */ IC_VEX_W_OPSIZE, /* 1661 */ IC_VEX_W_OPSIZE, /* 1662 */ IC_VEX_W_OPSIZE, /* 1663 */ IC_VEX_L, /* 1664 */ IC_VEX_L, /* 1665 */ IC_VEX_L_XS, /* 1666 */ IC_VEX_L_XS, /* 1667 */ IC_VEX_L_XD, /* 1668 */ IC_VEX_L_XD, /* 1669 */ IC_VEX_L_XD, /* 1670 */ IC_VEX_L_XD, /* 1671 */ IC_VEX_L_W, /* 1672 */ IC_VEX_L_W, /* 1673 */ IC_VEX_L_W_XS, /* 1674 */ IC_VEX_L_W_XS, /* 1675 */ IC_VEX_L_W_XD, /* 1676 */ IC_VEX_L_W_XD, /* 1677 */ IC_VEX_L_W_XD, /* 1678 */ IC_VEX_L_W_XD, /* 1679 */ IC_VEX_L_OPSIZE, /* 1680 */ IC_VEX_L_OPSIZE, /* 1681 */ IC_VEX_L_OPSIZE, /* 1682 */ IC_VEX_L_OPSIZE, /* 1683 */ IC_VEX_L_OPSIZE, /* 1684 */ IC_VEX_L_OPSIZE, /* 1685 */ IC_VEX_L_OPSIZE, /* 1686 */ IC_VEX_L_OPSIZE, /* 1687 */ IC_VEX_L_W_OPSIZE, /* 1688 */ IC_VEX_L_W_OPSIZE, /* 1689 */ IC_VEX_L_W_OPSIZE, /* 1690 */ IC_VEX_L_W_OPSIZE, /* 1691 */ IC_VEX_L_W_OPSIZE, /* 1692 */ IC_VEX_L_W_OPSIZE, /* 1693 */ IC_VEX_L_W_OPSIZE, /* 1694 */ IC_VEX_L_W_OPSIZE, /* 1695 */ IC_VEX_L, /* 1696 */ IC_VEX_L, /* 1697 */ IC_VEX_L_XS, /* 1698 */ IC_VEX_L_XS, /* 1699 */ IC_VEX_L_XD, /* 1700 */ IC_VEX_L_XD, /* 1701 */ IC_VEX_L_XD, /* 1702 */ IC_VEX_L_XD, /* 1703 */ IC_VEX_L_W, /* 1704 */ IC_VEX_L_W, /* 1705 */ IC_VEX_L_W_XS, /* 1706 */ IC_VEX_L_W_XS, /* 1707 */ IC_VEX_L_W_XD, /* 1708 */ IC_VEX_L_W_XD, /* 1709 */ IC_VEX_L_W_XD, /* 1710 */ IC_VEX_L_W_XD, /* 1711 */ IC_VEX_L_OPSIZE, /* 1712 */ IC_VEX_L_OPSIZE, /* 1713 */ IC_VEX_L_OPSIZE, /* 1714 */ IC_VEX_L_OPSIZE, /* 1715 */ IC_VEX_L_OPSIZE, /* 1716 */ IC_VEX_L_OPSIZE, /* 1717 */ IC_VEX_L_OPSIZE, /* 1718 */ IC_VEX_L_OPSIZE, /* 1719 */ IC_VEX_L_W_OPSIZE, /* 1720 */ IC_VEX_L_W_OPSIZE, /* 1721 */ IC_VEX_L_W_OPSIZE, /* 1722 */ IC_VEX_L_W_OPSIZE, /* 1723 */ IC_VEX_L_W_OPSIZE, /* 1724 */ IC_VEX_L_W_OPSIZE, /* 1725 */ IC_VEX_L_W_OPSIZE, /* 1726 */ IC_VEX_L_W_OPSIZE, /* 1727 */ IC_VEX_L, /* 1728 */ IC_VEX_L, /* 1729 */ IC_VEX_L_XS, /* 1730 */ IC_VEX_L_XS, /* 1731 */ IC_VEX_L_XD, /* 1732 */ IC_VEX_L_XD, /* 1733 */ IC_VEX_L_XD, /* 1734 */ IC_VEX_L_XD, /* 1735 */ IC_VEX_L_W, /* 1736 */ IC_VEX_L_W, /* 1737 */ IC_VEX_L_W_XS, /* 1738 */ IC_VEX_L_W_XS, /* 1739 */ IC_VEX_L_W_XD, /* 1740 */ IC_VEX_L_W_XD, /* 1741 */ IC_VEX_L_W_XD, /* 1742 */ IC_VEX_L_W_XD, /* 1743 */ IC_VEX_L_OPSIZE, /* 1744 */ IC_VEX_L_OPSIZE, /* 1745 */ IC_VEX_L_OPSIZE, /* 1746 */ IC_VEX_L_OPSIZE, /* 1747 */ IC_VEX_L_OPSIZE, /* 1748 */ IC_VEX_L_OPSIZE, /* 1749 */ IC_VEX_L_OPSIZE, /* 1750 */ IC_VEX_L_OPSIZE, /* 1751 */ IC_VEX_L_W_OPSIZE, /* 1752 */ IC_VEX_L_W_OPSIZE, /* 1753 */ IC_VEX_L_W_OPSIZE, /* 1754 */ IC_VEX_L_W_OPSIZE, /* 1755 */ IC_VEX_L_W_OPSIZE, /* 1756 */ IC_VEX_L_W_OPSIZE, /* 1757 */ IC_VEX_L_W_OPSIZE, /* 1758 */ IC_VEX_L_W_OPSIZE, /* 1759 */ IC_VEX_L, /* 1760 */ IC_VEX_L, /* 1761 */ IC_VEX_L_XS, /* 1762 */ IC_VEX_L_XS, /* 1763 */ IC_VEX_L_XD, /* 1764 */ IC_VEX_L_XD, /* 1765 */ IC_VEX_L_XD, /* 1766 */ IC_VEX_L_XD, /* 1767 */ IC_VEX_L_W, /* 1768 */ IC_VEX_L_W, /* 1769 */ IC_VEX_L_W_XS, /* 1770 */ IC_VEX_L_W_XS, /* 1771 */ IC_VEX_L_W_XD, /* 1772 */ IC_VEX_L_W_XD, /* 1773 */ IC_VEX_L_W_XD, /* 1774 */ IC_VEX_L_W_XD, /* 1775 */ IC_VEX_L_OPSIZE, /* 1776 */ IC_VEX_L_OPSIZE, /* 1777 */ IC_VEX_L_OPSIZE, /* 1778 */ IC_VEX_L_OPSIZE, /* 1779 */ IC_VEX_L_OPSIZE, /* 1780 */ IC_VEX_L_OPSIZE, /* 1781 */ IC_VEX_L_OPSIZE, /* 1782 */ IC_VEX_L_OPSIZE, /* 1783 */ IC_VEX_L_W_OPSIZE, /* 1784 */ IC_VEX_L_W_OPSIZE, /* 1785 */ IC_VEX_L_W_OPSIZE, /* 1786 */ IC_VEX_L_W_OPSIZE, /* 1787 */ IC_VEX_L_W_OPSIZE, /* 1788 */ IC_VEX_L_W_OPSIZE, /* 1789 */ IC_VEX_L_W_OPSIZE, /* 1790 */ IC_VEX_L_W_OPSIZE, /* 1791 */ IC_EVEX_L2, /* 1792 */ IC_EVEX_L2, /* 1793 */ IC_EVEX_L2_XS, /* 1794 */ IC_EVEX_L2_XS, /* 1795 */ IC_EVEX_L2_XD, /* 1796 */ IC_EVEX_L2_XD, /* 1797 */ IC_EVEX_L2_XD, /* 1798 */ IC_EVEX_L2_XD, /* 1799 */ IC_EVEX_L2_W, /* 1800 */ IC_EVEX_L2_W, /* 1801 */ IC_EVEX_L2_W_XS, /* 1802 */ IC_EVEX_L2_W_XS, /* 1803 */ IC_EVEX_L2_W_XD, /* 1804 */ IC_EVEX_L2_W_XD, /* 1805 */ IC_EVEX_L2_W_XD, /* 1806 */ IC_EVEX_L2_W_XD, /* 1807 */ IC_EVEX_L2_OPSIZE, /* 1808 */ IC_EVEX_L2_OPSIZE, /* 1809 */ IC_EVEX_L2_OPSIZE, /* 1810 */ IC_EVEX_L2_OPSIZE, /* 1811 */ IC_EVEX_L2_OPSIZE, /* 1812 */ IC_EVEX_L2_OPSIZE, /* 1813 */ IC_EVEX_L2_OPSIZE, /* 1814 */ IC_EVEX_L2_OPSIZE, /* 1815 */ IC_EVEX_L2_W_OPSIZE, /* 1816 */ IC_EVEX_L2_W_OPSIZE, /* 1817 */ IC_EVEX_L2_W_OPSIZE, /* 1818 */ IC_EVEX_L2_W_OPSIZE, /* 1819 */ IC_EVEX_L2_W_OPSIZE, /* 1820 */ IC_EVEX_L2_W_OPSIZE, /* 1821 */ IC_EVEX_L2_W_OPSIZE, /* 1822 */ IC_EVEX_L2_W_OPSIZE, /* 1823 */ IC_EVEX_L2, /* 1824 */ IC_EVEX_L2, /* 1825 */ IC_EVEX_L2_XS, /* 1826 */ IC_EVEX_L2_XS, /* 1827 */ IC_EVEX_L2_XD, /* 1828 */ IC_EVEX_L2_XD, /* 1829 */ IC_EVEX_L2_XD, /* 1830 */ IC_EVEX_L2_XD, /* 1831 */ IC_EVEX_L2_W, /* 1832 */ IC_EVEX_L2_W, /* 1833 */ IC_EVEX_L2_W_XS, /* 1834 */ IC_EVEX_L2_W_XS, /* 1835 */ IC_EVEX_L2_W_XD, /* 1836 */ IC_EVEX_L2_W_XD, /* 1837 */ IC_EVEX_L2_W_XD, /* 1838 */ IC_EVEX_L2_W_XD, /* 1839 */ IC_EVEX_L2_OPSIZE, /* 1840 */ IC_EVEX_L2_OPSIZE, /* 1841 */ IC_EVEX_L2_OPSIZE, /* 1842 */ IC_EVEX_L2_OPSIZE, /* 1843 */ IC_EVEX_L2_OPSIZE, /* 1844 */ IC_EVEX_L2_OPSIZE, /* 1845 */ IC_EVEX_L2_OPSIZE, /* 1846 */ IC_EVEX_L2_OPSIZE, /* 1847 */ IC_EVEX_L2_W_OPSIZE, /* 1848 */ IC_EVEX_L2_W_OPSIZE, /* 1849 */ IC_EVEX_L2_W_OPSIZE, /* 1850 */ IC_EVEX_L2_W_OPSIZE, /* 1851 */ IC_EVEX_L2_W_OPSIZE, /* 1852 */ IC_EVEX_L2_W_OPSIZE, /* 1853 */ IC_EVEX_L2_W_OPSIZE, /* 1854 */ IC_EVEX_L2_W_OPSIZE, /* 1855 */ IC_EVEX_L2, /* 1856 */ IC_EVEX_L2, /* 1857 */ IC_EVEX_L2_XS, /* 1858 */ IC_EVEX_L2_XS, /* 1859 */ IC_EVEX_L2_XD, /* 1860 */ IC_EVEX_L2_XD, /* 1861 */ IC_EVEX_L2_XD, /* 1862 */ IC_EVEX_L2_XD, /* 1863 */ IC_EVEX_L2_W, /* 1864 */ IC_EVEX_L2_W, /* 1865 */ IC_EVEX_L2_W_XS, /* 1866 */ IC_EVEX_L2_W_XS, /* 1867 */ IC_EVEX_L2_W_XD, /* 1868 */ IC_EVEX_L2_W_XD, /* 1869 */ IC_EVEX_L2_W_XD, /* 1870 */ IC_EVEX_L2_W_XD, /* 1871 */ IC_EVEX_L2_OPSIZE, /* 1872 */ IC_EVEX_L2_OPSIZE, /* 1873 */ IC_EVEX_L2_OPSIZE, /* 1874 */ IC_EVEX_L2_OPSIZE, /* 1875 */ IC_EVEX_L2_OPSIZE, /* 1876 */ IC_EVEX_L2_OPSIZE, /* 1877 */ IC_EVEX_L2_OPSIZE, /* 1878 */ IC_EVEX_L2_OPSIZE, /* 1879 */ IC_EVEX_L2_W_OPSIZE, /* 1880 */ IC_EVEX_L2_W_OPSIZE, /* 1881 */ IC_EVEX_L2_W_OPSIZE, /* 1882 */ IC_EVEX_L2_W_OPSIZE, /* 1883 */ IC_EVEX_L2_W_OPSIZE, /* 1884 */ IC_EVEX_L2_W_OPSIZE, /* 1885 */ IC_EVEX_L2_W_OPSIZE, /* 1886 */ IC_EVEX_L2_W_OPSIZE, /* 1887 */ IC_EVEX_L2, /* 1888 */ IC_EVEX_L2, /* 1889 */ IC_EVEX_L2_XS, /* 1890 */ IC_EVEX_L2_XS, /* 1891 */ IC_EVEX_L2_XD, /* 1892 */ IC_EVEX_L2_XD, /* 1893 */ IC_EVEX_L2_XD, /* 1894 */ IC_EVEX_L2_XD, /* 1895 */ IC_EVEX_L2_W, /* 1896 */ IC_EVEX_L2_W, /* 1897 */ IC_EVEX_L2_W_XS, /* 1898 */ IC_EVEX_L2_W_XS, /* 1899 */ IC_EVEX_L2_W_XD, /* 1900 */ IC_EVEX_L2_W_XD, /* 1901 */ IC_EVEX_L2_W_XD, /* 1902 */ IC_EVEX_L2_W_XD, /* 1903 */ IC_EVEX_L2_OPSIZE, /* 1904 */ IC_EVEX_L2_OPSIZE, /* 1905 */ IC_EVEX_L2_OPSIZE, /* 1906 */ IC_EVEX_L2_OPSIZE, /* 1907 */ IC_EVEX_L2_OPSIZE, /* 1908 */ IC_EVEX_L2_OPSIZE, /* 1909 */ IC_EVEX_L2_OPSIZE, /* 1910 */ IC_EVEX_L2_OPSIZE, /* 1911 */ IC_EVEX_L2_W_OPSIZE, /* 1912 */ IC_EVEX_L2_W_OPSIZE, /* 1913 */ IC_EVEX_L2_W_OPSIZE, /* 1914 */ IC_EVEX_L2_W_OPSIZE, /* 1915 */ IC_EVEX_L2_W_OPSIZE, /* 1916 */ IC_EVEX_L2_W_OPSIZE, /* 1917 */ IC_EVEX_L2_W_OPSIZE, /* 1918 */ IC_EVEX_L2_W_OPSIZE, /* 1919 */ IC_EVEX_L2, /* 1920 */ IC_EVEX_L2, /* 1921 */ IC_EVEX_L2_XS, /* 1922 */ IC_EVEX_L2_XS, /* 1923 */ IC_EVEX_L2_XD, /* 1924 */ IC_EVEX_L2_XD, /* 1925 */ IC_EVEX_L2_XD, /* 1926 */ IC_EVEX_L2_XD, /* 1927 */ IC_EVEX_L2_W, /* 1928 */ IC_EVEX_L2_W, /* 1929 */ IC_EVEX_L2_W_XS, /* 1930 */ IC_EVEX_L2_W_XS, /* 1931 */ IC_EVEX_L2_W_XD, /* 1932 */ IC_EVEX_L2_W_XD, /* 1933 */ IC_EVEX_L2_W_XD, /* 1934 */ IC_EVEX_L2_W_XD, /* 1935 */ IC_EVEX_L2_OPSIZE, /* 1936 */ IC_EVEX_L2_OPSIZE, /* 1937 */ IC_EVEX_L2_OPSIZE, /* 1938 */ IC_EVEX_L2_OPSIZE, /* 1939 */ IC_EVEX_L2_OPSIZE, /* 1940 */ IC_EVEX_L2_OPSIZE, /* 1941 */ IC_EVEX_L2_OPSIZE, /* 1942 */ IC_EVEX_L2_OPSIZE, /* 1943 */ IC_EVEX_L2_W_OPSIZE, /* 1944 */ IC_EVEX_L2_W_OPSIZE, /* 1945 */ IC_EVEX_L2_W_OPSIZE, /* 1946 */ IC_EVEX_L2_W_OPSIZE, /* 1947 */ IC_EVEX_L2_W_OPSIZE, /* 1948 */ IC_EVEX_L2_W_OPSIZE, /* 1949 */ IC_EVEX_L2_W_OPSIZE, /* 1950 */ IC_EVEX_L2_W_OPSIZE, /* 1951 */ IC_EVEX_L2, /* 1952 */ IC_EVEX_L2, /* 1953 */ IC_EVEX_L2_XS, /* 1954 */ IC_EVEX_L2_XS, /* 1955 */ IC_EVEX_L2_XD, /* 1956 */ IC_EVEX_L2_XD, /* 1957 */ IC_EVEX_L2_XD, /* 1958 */ IC_EVEX_L2_XD, /* 1959 */ IC_EVEX_L2_W, /* 1960 */ IC_EVEX_L2_W, /* 1961 */ IC_EVEX_L2_W_XS, /* 1962 */ IC_EVEX_L2_W_XS, /* 1963 */ IC_EVEX_L2_W_XD, /* 1964 */ IC_EVEX_L2_W_XD, /* 1965 */ IC_EVEX_L2_W_XD, /* 1966 */ IC_EVEX_L2_W_XD, /* 1967 */ IC_EVEX_L2_OPSIZE, /* 1968 */ IC_EVEX_L2_OPSIZE, /* 1969 */ IC_EVEX_L2_OPSIZE, /* 1970 */ IC_EVEX_L2_OPSIZE, /* 1971 */ IC_EVEX_L2_OPSIZE, /* 1972 */ IC_EVEX_L2_OPSIZE, /* 1973 */ IC_EVEX_L2_OPSIZE, /* 1974 */ IC_EVEX_L2_OPSIZE, /* 1975 */ IC_EVEX_L2_W_OPSIZE, /* 1976 */ IC_EVEX_L2_W_OPSIZE, /* 1977 */ IC_EVEX_L2_W_OPSIZE, /* 1978 */ IC_EVEX_L2_W_OPSIZE, /* 1979 */ IC_EVEX_L2_W_OPSIZE, /* 1980 */ IC_EVEX_L2_W_OPSIZE, /* 1981 */ IC_EVEX_L2_W_OPSIZE, /* 1982 */ IC_EVEX_L2_W_OPSIZE, /* 1983 */ IC_EVEX_L2, /* 1984 */ IC_EVEX_L2, /* 1985 */ IC_EVEX_L2_XS, /* 1986 */ IC_EVEX_L2_XS, /* 1987 */ IC_EVEX_L2_XD, /* 1988 */ IC_EVEX_L2_XD, /* 1989 */ IC_EVEX_L2_XD, /* 1990 */ IC_EVEX_L2_XD, /* 1991 */ IC_EVEX_L2_W, /* 1992 */ IC_EVEX_L2_W, /* 1993 */ IC_EVEX_L2_W_XS, /* 1994 */ IC_EVEX_L2_W_XS, /* 1995 */ IC_EVEX_L2_W_XD, /* 1996 */ IC_EVEX_L2_W_XD, /* 1997 */ IC_EVEX_L2_W_XD, /* 1998 */ IC_EVEX_L2_W_XD, /* 1999 */ IC_EVEX_L2_OPSIZE, /* 2000 */ IC_EVEX_L2_OPSIZE, /* 2001 */ IC_EVEX_L2_OPSIZE, /* 2002 */ IC_EVEX_L2_OPSIZE, /* 2003 */ IC_EVEX_L2_OPSIZE, /* 2004 */ IC_EVEX_L2_OPSIZE, /* 2005 */ IC_EVEX_L2_OPSIZE, /* 2006 */ IC_EVEX_L2_OPSIZE, /* 2007 */ IC_EVEX_L2_W_OPSIZE, /* 2008 */ IC_EVEX_L2_W_OPSIZE, /* 2009 */ IC_EVEX_L2_W_OPSIZE, /* 2010 */ IC_EVEX_L2_W_OPSIZE, /* 2011 */ IC_EVEX_L2_W_OPSIZE, /* 2012 */ IC_EVEX_L2_W_OPSIZE, /* 2013 */ IC_EVEX_L2_W_OPSIZE, /* 2014 */ IC_EVEX_L2_W_OPSIZE, /* 2015 */ IC_EVEX_L2, /* 2016 */ IC_EVEX_L2, /* 2017 */ IC_EVEX_L2_XS, /* 2018 */ IC_EVEX_L2_XS, /* 2019 */ IC_EVEX_L2_XD, /* 2020 */ IC_EVEX_L2_XD, /* 2021 */ IC_EVEX_L2_XD, /* 2022 */ IC_EVEX_L2_XD, /* 2023 */ IC_EVEX_L2_W, /* 2024 */ IC_EVEX_L2_W, /* 2025 */ IC_EVEX_L2_W_XS, /* 2026 */ IC_EVEX_L2_W_XS, /* 2027 */ IC_EVEX_L2_W_XD, /* 2028 */ IC_EVEX_L2_W_XD, /* 2029 */ IC_EVEX_L2_W_XD, /* 2030 */ IC_EVEX_L2_W_XD, /* 2031 */ IC_EVEX_L2_OPSIZE, /* 2032 */ IC_EVEX_L2_OPSIZE, /* 2033 */ IC_EVEX_L2_OPSIZE, /* 2034 */ IC_EVEX_L2_OPSIZE, /* 2035 */ IC_EVEX_L2_OPSIZE, /* 2036 */ IC_EVEX_L2_OPSIZE, /* 2037 */ IC_EVEX_L2_OPSIZE, /* 2038 */ IC_EVEX_L2_OPSIZE, /* 2039 */ IC_EVEX_L2_W_OPSIZE, /* 2040 */ IC_EVEX_L2_W_OPSIZE, /* 2041 */ IC_EVEX_L2_W_OPSIZE, /* 2042 */ IC_EVEX_L2_W_OPSIZE, /* 2043 */ IC_EVEX_L2_W_OPSIZE, /* 2044 */ IC_EVEX_L2_W_OPSIZE, /* 2045 */ IC_EVEX_L2_W_OPSIZE, /* 2046 */ IC_EVEX_L2_W_OPSIZE, /* 2047 */ IC, /* 2048 */ IC_64BIT, /* 2049 */ IC_XS, /* 2050 */ IC_64BIT_XS, /* 2051 */ IC_XD, /* 2052 */ IC_64BIT_XD, /* 2053 */ IC_XS, /* 2054 */ IC_64BIT_XS, /* 2055 */ IC, /* 2056 */ IC_64BIT_REXW, /* 2057 */ IC_XS, /* 2058 */ IC_64BIT_REXW_XS, /* 2059 */ IC_XD, /* 2060 */ IC_64BIT_REXW_XD, /* 2061 */ IC_XS, /* 2062 */ IC_64BIT_REXW_XS, /* 2063 */ IC_OPSIZE, /* 2064 */ IC_64BIT_OPSIZE, /* 2065 */ IC_XS_OPSIZE, /* 2066 */ IC_64BIT_XS_OPSIZE, /* 2067 */ IC_XD_OPSIZE, /* 2068 */ IC_64BIT_XD_OPSIZE, /* 2069 */ IC_XS_OPSIZE, /* 2070 */ IC_64BIT_XD_OPSIZE, /* 2071 */ IC_OPSIZE, /* 2072 */ IC_64BIT_REXW_OPSIZE, /* 2073 */ IC_XS_OPSIZE, /* 2074 */ IC_64BIT_REXW_XS, /* 2075 */ IC_XD_OPSIZE, /* 2076 */ IC_64BIT_REXW_XD, /* 2077 */ IC_XS_OPSIZE, /* 2078 */ IC_64BIT_REXW_XS, /* 2079 */ IC_ADSIZE, /* 2080 */ IC_64BIT_ADSIZE, /* 2081 */ IC_XS_ADSIZE, /* 2082 */ IC_64BIT_XS_ADSIZE, /* 2083 */ IC_XD_ADSIZE, /* 2084 */ IC_64BIT_XD_ADSIZE, /* 2085 */ IC_XS_ADSIZE, /* 2086 */ IC_64BIT_XD_ADSIZE, /* 2087 */ IC_ADSIZE, /* 2088 */ IC_64BIT_REXW_ADSIZE, /* 2089 */ IC_XS_ADSIZE, /* 2090 */ IC_64BIT_REXW_XS, /* 2091 */ IC_XD_ADSIZE, /* 2092 */ IC_64BIT_REXW_XD, /* 2093 */ IC_XS_ADSIZE, /* 2094 */ IC_64BIT_REXW_XS, /* 2095 */ IC_OPSIZE_ADSIZE, /* 2096 */ IC_64BIT_OPSIZE_ADSIZE, /* 2097 */ IC_XS_OPSIZE, /* 2098 */ IC_64BIT_XS_OPSIZE, /* 2099 */ IC_XD_OPSIZE, /* 2100 */ IC_64BIT_XD_OPSIZE, /* 2101 */ IC_XS_OPSIZE, /* 2102 */ IC_64BIT_XD_OPSIZE, /* 2103 */ IC_OPSIZE_ADSIZE, /* 2104 */ IC_64BIT_REXW_OPSIZE, /* 2105 */ IC_XS_OPSIZE, /* 2106 */ IC_64BIT_REXW_XS, /* 2107 */ IC_XD_OPSIZE, /* 2108 */ IC_64BIT_REXW_XD, /* 2109 */ IC_XS_OPSIZE, /* 2110 */ IC_64BIT_REXW_XS, /* 2111 */ IC_VEX, /* 2112 */ IC_VEX, /* 2113 */ IC_VEX_XS, /* 2114 */ IC_VEX_XS, /* 2115 */ IC_VEX_XD, /* 2116 */ IC_VEX_XD, /* 2117 */ IC_VEX_XD, /* 2118 */ IC_VEX_XD, /* 2119 */ IC_VEX_W, /* 2120 */ IC_VEX_W, /* 2121 */ IC_VEX_W_XS, /* 2122 */ IC_VEX_W_XS, /* 2123 */ IC_VEX_W_XD, /* 2124 */ IC_VEX_W_XD, /* 2125 */ IC_VEX_W_XD, /* 2126 */ IC_VEX_W_XD, /* 2127 */ IC_VEX_OPSIZE, /* 2128 */ IC_VEX_OPSIZE, /* 2129 */ IC_VEX_OPSIZE, /* 2130 */ IC_VEX_OPSIZE, /* 2131 */ IC_VEX_OPSIZE, /* 2132 */ IC_VEX_OPSIZE, /* 2133 */ IC_VEX_OPSIZE, /* 2134 */ IC_VEX_OPSIZE, /* 2135 */ IC_VEX_W_OPSIZE, /* 2136 */ IC_VEX_W_OPSIZE, /* 2137 */ IC_VEX_W_OPSIZE, /* 2138 */ IC_VEX_W_OPSIZE, /* 2139 */ IC_VEX_W_OPSIZE, /* 2140 */ IC_VEX_W_OPSIZE, /* 2141 */ IC_VEX_W_OPSIZE, /* 2142 */ IC_VEX_W_OPSIZE, /* 2143 */ IC_VEX, /* 2144 */ IC_VEX, /* 2145 */ IC_VEX_XS, /* 2146 */ IC_VEX_XS, /* 2147 */ IC_VEX_XD, /* 2148 */ IC_VEX_XD, /* 2149 */ IC_VEX_XD, /* 2150 */ IC_VEX_XD, /* 2151 */ IC_VEX_W, /* 2152 */ IC_VEX_W, /* 2153 */ IC_VEX_W_XS, /* 2154 */ IC_VEX_W_XS, /* 2155 */ IC_VEX_W_XD, /* 2156 */ IC_VEX_W_XD, /* 2157 */ IC_VEX_W_XD, /* 2158 */ IC_VEX_W_XD, /* 2159 */ IC_VEX_OPSIZE, /* 2160 */ IC_VEX_OPSIZE, /* 2161 */ IC_VEX_OPSIZE, /* 2162 */ IC_VEX_OPSIZE, /* 2163 */ IC_VEX_OPSIZE, /* 2164 */ IC_VEX_OPSIZE, /* 2165 */ IC_VEX_OPSIZE, /* 2166 */ IC_VEX_OPSIZE, /* 2167 */ IC_VEX_W_OPSIZE, /* 2168 */ IC_VEX_W_OPSIZE, /* 2169 */ IC_VEX_W_OPSIZE, /* 2170 */ IC_VEX_W_OPSIZE, /* 2171 */ IC_VEX_W_OPSIZE, /* 2172 */ IC_VEX_W_OPSIZE, /* 2173 */ IC_VEX_W_OPSIZE, /* 2174 */ IC_VEX_W_OPSIZE, /* 2175 */ IC_VEX_L, /* 2176 */ IC_VEX_L, /* 2177 */ IC_VEX_L_XS, /* 2178 */ IC_VEX_L_XS, /* 2179 */ IC_VEX_L_XD, /* 2180 */ IC_VEX_L_XD, /* 2181 */ IC_VEX_L_XD, /* 2182 */ IC_VEX_L_XD, /* 2183 */ IC_VEX_L_W, /* 2184 */ IC_VEX_L_W, /* 2185 */ IC_VEX_L_W_XS, /* 2186 */ IC_VEX_L_W_XS, /* 2187 */ IC_VEX_L_W_XD, /* 2188 */ IC_VEX_L_W_XD, /* 2189 */ IC_VEX_L_W_XD, /* 2190 */ IC_VEX_L_W_XD, /* 2191 */ IC_VEX_L_OPSIZE, /* 2192 */ IC_VEX_L_OPSIZE, /* 2193 */ IC_VEX_L_OPSIZE, /* 2194 */ IC_VEX_L_OPSIZE, /* 2195 */ IC_VEX_L_OPSIZE, /* 2196 */ IC_VEX_L_OPSIZE, /* 2197 */ IC_VEX_L_OPSIZE, /* 2198 */ IC_VEX_L_OPSIZE, /* 2199 */ IC_VEX_L_W_OPSIZE, /* 2200 */ IC_VEX_L_W_OPSIZE, /* 2201 */ IC_VEX_L_W_OPSIZE, /* 2202 */ IC_VEX_L_W_OPSIZE, /* 2203 */ IC_VEX_L_W_OPSIZE, /* 2204 */ IC_VEX_L_W_OPSIZE, /* 2205 */ IC_VEX_L_W_OPSIZE, /* 2206 */ IC_VEX_L_W_OPSIZE, /* 2207 */ IC_VEX_L, /* 2208 */ IC_VEX_L, /* 2209 */ IC_VEX_L_XS, /* 2210 */ IC_VEX_L_XS, /* 2211 */ IC_VEX_L_XD, /* 2212 */ IC_VEX_L_XD, /* 2213 */ IC_VEX_L_XD, /* 2214 */ IC_VEX_L_XD, /* 2215 */ IC_VEX_L_W, /* 2216 */ IC_VEX_L_W, /* 2217 */ IC_VEX_L_W_XS, /* 2218 */ IC_VEX_L_W_XS, /* 2219 */ IC_VEX_L_W_XD, /* 2220 */ IC_VEX_L_W_XD, /* 2221 */ IC_VEX_L_W_XD, /* 2222 */ IC_VEX_L_W_XD, /* 2223 */ IC_VEX_L_OPSIZE, /* 2224 */ IC_VEX_L_OPSIZE, /* 2225 */ IC_VEX_L_OPSIZE, /* 2226 */ IC_VEX_L_OPSIZE, /* 2227 */ IC_VEX_L_OPSIZE, /* 2228 */ IC_VEX_L_OPSIZE, /* 2229 */ IC_VEX_L_OPSIZE, /* 2230 */ IC_VEX_L_OPSIZE, /* 2231 */ IC_VEX_L_W_OPSIZE, /* 2232 */ IC_VEX_L_W_OPSIZE, /* 2233 */ IC_VEX_L_W_OPSIZE, /* 2234 */ IC_VEX_L_W_OPSIZE, /* 2235 */ IC_VEX_L_W_OPSIZE, /* 2236 */ IC_VEX_L_W_OPSIZE, /* 2237 */ IC_VEX_L_W_OPSIZE, /* 2238 */ IC_VEX_L_W_OPSIZE, /* 2239 */ IC_VEX_L, /* 2240 */ IC_VEX_L, /* 2241 */ IC_VEX_L_XS, /* 2242 */ IC_VEX_L_XS, /* 2243 */ IC_VEX_L_XD, /* 2244 */ IC_VEX_L_XD, /* 2245 */ IC_VEX_L_XD, /* 2246 */ IC_VEX_L_XD, /* 2247 */ IC_VEX_L_W, /* 2248 */ IC_VEX_L_W, /* 2249 */ IC_VEX_L_W_XS, /* 2250 */ IC_VEX_L_W_XS, /* 2251 */ IC_VEX_L_W_XD, /* 2252 */ IC_VEX_L_W_XD, /* 2253 */ IC_VEX_L_W_XD, /* 2254 */ IC_VEX_L_W_XD, /* 2255 */ IC_VEX_L_OPSIZE, /* 2256 */ IC_VEX_L_OPSIZE, /* 2257 */ IC_VEX_L_OPSIZE, /* 2258 */ IC_VEX_L_OPSIZE, /* 2259 */ IC_VEX_L_OPSIZE, /* 2260 */ IC_VEX_L_OPSIZE, /* 2261 */ IC_VEX_L_OPSIZE, /* 2262 */ IC_VEX_L_OPSIZE, /* 2263 */ IC_VEX_L_W_OPSIZE, /* 2264 */ IC_VEX_L_W_OPSIZE, /* 2265 */ IC_VEX_L_W_OPSIZE, /* 2266 */ IC_VEX_L_W_OPSIZE, /* 2267 */ IC_VEX_L_W_OPSIZE, /* 2268 */ IC_VEX_L_W_OPSIZE, /* 2269 */ IC_VEX_L_W_OPSIZE, /* 2270 */ IC_VEX_L_W_OPSIZE, /* 2271 */ IC_VEX_L, /* 2272 */ IC_VEX_L, /* 2273 */ IC_VEX_L_XS, /* 2274 */ IC_VEX_L_XS, /* 2275 */ IC_VEX_L_XD, /* 2276 */ IC_VEX_L_XD, /* 2277 */ IC_VEX_L_XD, /* 2278 */ IC_VEX_L_XD, /* 2279 */ IC_VEX_L_W, /* 2280 */ IC_VEX_L_W, /* 2281 */ IC_VEX_L_W_XS, /* 2282 */ IC_VEX_L_W_XS, /* 2283 */ IC_VEX_L_W_XD, /* 2284 */ IC_VEX_L_W_XD, /* 2285 */ IC_VEX_L_W_XD, /* 2286 */ IC_VEX_L_W_XD, /* 2287 */ IC_VEX_L_OPSIZE, /* 2288 */ IC_VEX_L_OPSIZE, /* 2289 */ IC_VEX_L_OPSIZE, /* 2290 */ IC_VEX_L_OPSIZE, /* 2291 */ IC_VEX_L_OPSIZE, /* 2292 */ IC_VEX_L_OPSIZE, /* 2293 */ IC_VEX_L_OPSIZE, /* 2294 */ IC_VEX_L_OPSIZE, /* 2295 */ IC_VEX_L_W_OPSIZE, /* 2296 */ IC_VEX_L_W_OPSIZE, /* 2297 */ IC_VEX_L_W_OPSIZE, /* 2298 */ IC_VEX_L_W_OPSIZE, /* 2299 */ IC_VEX_L_W_OPSIZE, /* 2300 */ IC_VEX_L_W_OPSIZE, /* 2301 */ IC_VEX_L_W_OPSIZE, /* 2302 */ IC_VEX_L_W_OPSIZE, /* 2303 */ IC_EVEX_K, /* 2304 */ IC_EVEX_K, /* 2305 */ IC_EVEX_XS_K, /* 2306 */ IC_EVEX_XS_K, /* 2307 */ IC_EVEX_XD_K, /* 2308 */ IC_EVEX_XD_K, /* 2309 */ IC_EVEX_XD_K, /* 2310 */ IC_EVEX_XD_K, /* 2311 */ IC_EVEX_W_K, /* 2312 */ IC_EVEX_W_K, /* 2313 */ IC_EVEX_W_XS_K, /* 2314 */ IC_EVEX_W_XS_K, /* 2315 */ IC_EVEX_W_XD_K, /* 2316 */ IC_EVEX_W_XD_K, /* 2317 */ IC_EVEX_W_XD_K, /* 2318 */ IC_EVEX_W_XD_K, /* 2319 */ IC_EVEX_OPSIZE_K, /* 2320 */ IC_EVEX_OPSIZE_K, /* 2321 */ IC_EVEX_OPSIZE_K, /* 2322 */ IC_EVEX_OPSIZE_K, /* 2323 */ IC_EVEX_OPSIZE_K, /* 2324 */ IC_EVEX_OPSIZE_K, /* 2325 */ IC_EVEX_OPSIZE_K, /* 2326 */ IC_EVEX_OPSIZE_K, /* 2327 */ IC_EVEX_W_OPSIZE_K, /* 2328 */ IC_EVEX_W_OPSIZE_K, /* 2329 */ IC_EVEX_W_OPSIZE_K, /* 2330 */ IC_EVEX_W_OPSIZE_K, /* 2331 */ IC_EVEX_W_OPSIZE_K, /* 2332 */ IC_EVEX_W_OPSIZE_K, /* 2333 */ IC_EVEX_W_OPSIZE_K, /* 2334 */ IC_EVEX_W_OPSIZE_K, /* 2335 */ IC_EVEX_K, /* 2336 */ IC_EVEX_K, /* 2337 */ IC_EVEX_XS_K, /* 2338 */ IC_EVEX_XS_K, /* 2339 */ IC_EVEX_XD_K, /* 2340 */ IC_EVEX_XD_K, /* 2341 */ IC_EVEX_XD_K, /* 2342 */ IC_EVEX_XD_K, /* 2343 */ IC_EVEX_W_K, /* 2344 */ IC_EVEX_W_K, /* 2345 */ IC_EVEX_W_XS_K, /* 2346 */ IC_EVEX_W_XS_K, /* 2347 */ IC_EVEX_W_XD_K, /* 2348 */ IC_EVEX_W_XD_K, /* 2349 */ IC_EVEX_W_XD_K, /* 2350 */ IC_EVEX_W_XD_K, /* 2351 */ IC_EVEX_OPSIZE_K, /* 2352 */ IC_EVEX_OPSIZE_K, /* 2353 */ IC_EVEX_OPSIZE_K, /* 2354 */ IC_EVEX_OPSIZE_K, /* 2355 */ IC_EVEX_OPSIZE_K, /* 2356 */ IC_EVEX_OPSIZE_K, /* 2357 */ IC_EVEX_OPSIZE_K, /* 2358 */ IC_EVEX_OPSIZE_K, /* 2359 */ IC_EVEX_W_OPSIZE_K, /* 2360 */ IC_EVEX_W_OPSIZE_K, /* 2361 */ IC_EVEX_W_OPSIZE_K, /* 2362 */ IC_EVEX_W_OPSIZE_K, /* 2363 */ IC_EVEX_W_OPSIZE_K, /* 2364 */ IC_EVEX_W_OPSIZE_K, /* 2365 */ IC_EVEX_W_OPSIZE_K, /* 2366 */ IC_EVEX_W_OPSIZE_K, /* 2367 */ IC_EVEX_K, /* 2368 */ IC_EVEX_K, /* 2369 */ IC_EVEX_XS_K, /* 2370 */ IC_EVEX_XS_K, /* 2371 */ IC_EVEX_XD_K, /* 2372 */ IC_EVEX_XD_K, /* 2373 */ IC_EVEX_XD_K, /* 2374 */ IC_EVEX_XD_K, /* 2375 */ IC_EVEX_W_K, /* 2376 */ IC_EVEX_W_K, /* 2377 */ IC_EVEX_W_XS_K, /* 2378 */ IC_EVEX_W_XS_K, /* 2379 */ IC_EVEX_W_XD_K, /* 2380 */ IC_EVEX_W_XD_K, /* 2381 */ IC_EVEX_W_XD_K, /* 2382 */ IC_EVEX_W_XD_K, /* 2383 */ IC_EVEX_OPSIZE_K, /* 2384 */ IC_EVEX_OPSIZE_K, /* 2385 */ IC_EVEX_OPSIZE_K, /* 2386 */ IC_EVEX_OPSIZE_K, /* 2387 */ IC_EVEX_OPSIZE_K, /* 2388 */ IC_EVEX_OPSIZE_K, /* 2389 */ IC_EVEX_OPSIZE_K, /* 2390 */ IC_EVEX_OPSIZE_K, /* 2391 */ IC_EVEX_W_OPSIZE_K, /* 2392 */ IC_EVEX_W_OPSIZE_K, /* 2393 */ IC_EVEX_W_OPSIZE_K, /* 2394 */ IC_EVEX_W_OPSIZE_K, /* 2395 */ IC_EVEX_W_OPSIZE_K, /* 2396 */ IC_EVEX_W_OPSIZE_K, /* 2397 */ IC_EVEX_W_OPSIZE_K, /* 2398 */ IC_EVEX_W_OPSIZE_K, /* 2399 */ IC_EVEX_K, /* 2400 */ IC_EVEX_K, /* 2401 */ IC_EVEX_XS_K, /* 2402 */ IC_EVEX_XS_K, /* 2403 */ IC_EVEX_XD_K, /* 2404 */ IC_EVEX_XD_K, /* 2405 */ IC_EVEX_XD_K, /* 2406 */ IC_EVEX_XD_K, /* 2407 */ IC_EVEX_W_K, /* 2408 */ IC_EVEX_W_K, /* 2409 */ IC_EVEX_W_XS_K, /* 2410 */ IC_EVEX_W_XS_K, /* 2411 */ IC_EVEX_W_XD_K, /* 2412 */ IC_EVEX_W_XD_K, /* 2413 */ IC_EVEX_W_XD_K, /* 2414 */ IC_EVEX_W_XD_K, /* 2415 */ IC_EVEX_OPSIZE_K, /* 2416 */ IC_EVEX_OPSIZE_K, /* 2417 */ IC_EVEX_OPSIZE_K, /* 2418 */ IC_EVEX_OPSIZE_K, /* 2419 */ IC_EVEX_OPSIZE_K, /* 2420 */ IC_EVEX_OPSIZE_K, /* 2421 */ IC_EVEX_OPSIZE_K, /* 2422 */ IC_EVEX_OPSIZE_K, /* 2423 */ IC_EVEX_W_OPSIZE_K, /* 2424 */ IC_EVEX_W_OPSIZE_K, /* 2425 */ IC_EVEX_W_OPSIZE_K, /* 2426 */ IC_EVEX_W_OPSIZE_K, /* 2427 */ IC_EVEX_W_OPSIZE_K, /* 2428 */ IC_EVEX_W_OPSIZE_K, /* 2429 */ IC_EVEX_W_OPSIZE_K, /* 2430 */ IC_EVEX_W_OPSIZE_K, /* 2431 */ IC_EVEX_K, /* 2432 */ IC_EVEX_K, /* 2433 */ IC_EVEX_XS_K, /* 2434 */ IC_EVEX_XS_K, /* 2435 */ IC_EVEX_XD_K, /* 2436 */ IC_EVEX_XD_K, /* 2437 */ IC_EVEX_XD_K, /* 2438 */ IC_EVEX_XD_K, /* 2439 */ IC_EVEX_W_K, /* 2440 */ IC_EVEX_W_K, /* 2441 */ IC_EVEX_W_XS_K, /* 2442 */ IC_EVEX_W_XS_K, /* 2443 */ IC_EVEX_W_XD_K, /* 2444 */ IC_EVEX_W_XD_K, /* 2445 */ IC_EVEX_W_XD_K, /* 2446 */ IC_EVEX_W_XD_K, /* 2447 */ IC_EVEX_OPSIZE_K, /* 2448 */ IC_EVEX_OPSIZE_K, /* 2449 */ IC_EVEX_OPSIZE_K, /* 2450 */ IC_EVEX_OPSIZE_K, /* 2451 */ IC_EVEX_OPSIZE_K, /* 2452 */ IC_EVEX_OPSIZE_K, /* 2453 */ IC_EVEX_OPSIZE_K, /* 2454 */ IC_EVEX_OPSIZE_K, /* 2455 */ IC_EVEX_W_OPSIZE_K, /* 2456 */ IC_EVEX_W_OPSIZE_K, /* 2457 */ IC_EVEX_W_OPSIZE_K, /* 2458 */ IC_EVEX_W_OPSIZE_K, /* 2459 */ IC_EVEX_W_OPSIZE_K, /* 2460 */ IC_EVEX_W_OPSIZE_K, /* 2461 */ IC_EVEX_W_OPSIZE_K, /* 2462 */ IC_EVEX_W_OPSIZE_K, /* 2463 */ IC_EVEX_K, /* 2464 */ IC_EVEX_K, /* 2465 */ IC_EVEX_XS_K, /* 2466 */ IC_EVEX_XS_K, /* 2467 */ IC_EVEX_XD_K, /* 2468 */ IC_EVEX_XD_K, /* 2469 */ IC_EVEX_XD_K, /* 2470 */ IC_EVEX_XD_K, /* 2471 */ IC_EVEX_W_K, /* 2472 */ IC_EVEX_W_K, /* 2473 */ IC_EVEX_W_XS_K, /* 2474 */ IC_EVEX_W_XS_K, /* 2475 */ IC_EVEX_W_XD_K, /* 2476 */ IC_EVEX_W_XD_K, /* 2477 */ IC_EVEX_W_XD_K, /* 2478 */ IC_EVEX_W_XD_K, /* 2479 */ IC_EVEX_OPSIZE_K, /* 2480 */ IC_EVEX_OPSIZE_K, /* 2481 */ IC_EVEX_OPSIZE_K, /* 2482 */ IC_EVEX_OPSIZE_K, /* 2483 */ IC_EVEX_OPSIZE_K, /* 2484 */ IC_EVEX_OPSIZE_K, /* 2485 */ IC_EVEX_OPSIZE_K, /* 2486 */ IC_EVEX_OPSIZE_K, /* 2487 */ IC_EVEX_W_OPSIZE_K, /* 2488 */ IC_EVEX_W_OPSIZE_K, /* 2489 */ IC_EVEX_W_OPSIZE_K, /* 2490 */ IC_EVEX_W_OPSIZE_K, /* 2491 */ IC_EVEX_W_OPSIZE_K, /* 2492 */ IC_EVEX_W_OPSIZE_K, /* 2493 */ IC_EVEX_W_OPSIZE_K, /* 2494 */ IC_EVEX_W_OPSIZE_K, /* 2495 */ IC_EVEX_K, /* 2496 */ IC_EVEX_K, /* 2497 */ IC_EVEX_XS_K, /* 2498 */ IC_EVEX_XS_K, /* 2499 */ IC_EVEX_XD_K, /* 2500 */ IC_EVEX_XD_K, /* 2501 */ IC_EVEX_XD_K, /* 2502 */ IC_EVEX_XD_K, /* 2503 */ IC_EVEX_W_K, /* 2504 */ IC_EVEX_W_K, /* 2505 */ IC_EVEX_W_XS_K, /* 2506 */ IC_EVEX_W_XS_K, /* 2507 */ IC_EVEX_W_XD_K, /* 2508 */ IC_EVEX_W_XD_K, /* 2509 */ IC_EVEX_W_XD_K, /* 2510 */ IC_EVEX_W_XD_K, /* 2511 */ IC_EVEX_OPSIZE_K, /* 2512 */ IC_EVEX_OPSIZE_K, /* 2513 */ IC_EVEX_OPSIZE_K, /* 2514 */ IC_EVEX_OPSIZE_K, /* 2515 */ IC_EVEX_OPSIZE_K, /* 2516 */ IC_EVEX_OPSIZE_K, /* 2517 */ IC_EVEX_OPSIZE_K, /* 2518 */ IC_EVEX_OPSIZE_K, /* 2519 */ IC_EVEX_W_OPSIZE_K, /* 2520 */ IC_EVEX_W_OPSIZE_K, /* 2521 */ IC_EVEX_W_OPSIZE_K, /* 2522 */ IC_EVEX_W_OPSIZE_K, /* 2523 */ IC_EVEX_W_OPSIZE_K, /* 2524 */ IC_EVEX_W_OPSIZE_K, /* 2525 */ IC_EVEX_W_OPSIZE_K, /* 2526 */ IC_EVEX_W_OPSIZE_K, /* 2527 */ IC_EVEX_K, /* 2528 */ IC_EVEX_K, /* 2529 */ IC_EVEX_XS_K, /* 2530 */ IC_EVEX_XS_K, /* 2531 */ IC_EVEX_XD_K, /* 2532 */ IC_EVEX_XD_K, /* 2533 */ IC_EVEX_XD_K, /* 2534 */ IC_EVEX_XD_K, /* 2535 */ IC_EVEX_W_K, /* 2536 */ IC_EVEX_W_K, /* 2537 */ IC_EVEX_W_XS_K, /* 2538 */ IC_EVEX_W_XS_K, /* 2539 */ IC_EVEX_W_XD_K, /* 2540 */ IC_EVEX_W_XD_K, /* 2541 */ IC_EVEX_W_XD_K, /* 2542 */ IC_EVEX_W_XD_K, /* 2543 */ IC_EVEX_OPSIZE_K, /* 2544 */ IC_EVEX_OPSIZE_K, /* 2545 */ IC_EVEX_OPSIZE_K, /* 2546 */ IC_EVEX_OPSIZE_K, /* 2547 */ IC_EVEX_OPSIZE_K, /* 2548 */ IC_EVEX_OPSIZE_K, /* 2549 */ IC_EVEX_OPSIZE_K, /* 2550 */ IC_EVEX_OPSIZE_K, /* 2551 */ IC_EVEX_W_OPSIZE_K, /* 2552 */ IC_EVEX_W_OPSIZE_K, /* 2553 */ IC_EVEX_W_OPSIZE_K, /* 2554 */ IC_EVEX_W_OPSIZE_K, /* 2555 */ IC_EVEX_W_OPSIZE_K, /* 2556 */ IC_EVEX_W_OPSIZE_K, /* 2557 */ IC_EVEX_W_OPSIZE_K, /* 2558 */ IC_EVEX_W_OPSIZE_K, /* 2559 */ IC, /* 2560 */ IC_64BIT, /* 2561 */ IC_XS, /* 2562 */ IC_64BIT_XS, /* 2563 */ IC_XD, /* 2564 */ IC_64BIT_XD, /* 2565 */ IC_XS, /* 2566 */ IC_64BIT_XS, /* 2567 */ IC, /* 2568 */ IC_64BIT_REXW, /* 2569 */ IC_XS, /* 2570 */ IC_64BIT_REXW_XS, /* 2571 */ IC_XD, /* 2572 */ IC_64BIT_REXW_XD, /* 2573 */ IC_XS, /* 2574 */ IC_64BIT_REXW_XS, /* 2575 */ IC_OPSIZE, /* 2576 */ IC_64BIT_OPSIZE, /* 2577 */ IC_XS_OPSIZE, /* 2578 */ IC_64BIT_XS_OPSIZE, /* 2579 */ IC_XD_OPSIZE, /* 2580 */ IC_64BIT_XD_OPSIZE, /* 2581 */ IC_XS_OPSIZE, /* 2582 */ IC_64BIT_XD_OPSIZE, /* 2583 */ IC_OPSIZE, /* 2584 */ IC_64BIT_REXW_OPSIZE, /* 2585 */ IC_XS_OPSIZE, /* 2586 */ IC_64BIT_REXW_XS, /* 2587 */ IC_XD_OPSIZE, /* 2588 */ IC_64BIT_REXW_XD, /* 2589 */ IC_XS_OPSIZE, /* 2590 */ IC_64BIT_REXW_XS, /* 2591 */ IC_ADSIZE, /* 2592 */ IC_64BIT_ADSIZE, /* 2593 */ IC_XS_ADSIZE, /* 2594 */ IC_64BIT_XS_ADSIZE, /* 2595 */ IC_XD_ADSIZE, /* 2596 */ IC_64BIT_XD_ADSIZE, /* 2597 */ IC_XS_ADSIZE, /* 2598 */ IC_64BIT_XD_ADSIZE, /* 2599 */ IC_ADSIZE, /* 2600 */ IC_64BIT_REXW_ADSIZE, /* 2601 */ IC_XS_ADSIZE, /* 2602 */ IC_64BIT_REXW_XS, /* 2603 */ IC_XD_ADSIZE, /* 2604 */ IC_64BIT_REXW_XD, /* 2605 */ IC_XS_ADSIZE, /* 2606 */ IC_64BIT_REXW_XS, /* 2607 */ IC_OPSIZE_ADSIZE, /* 2608 */ IC_64BIT_OPSIZE_ADSIZE, /* 2609 */ IC_XS_OPSIZE, /* 2610 */ IC_64BIT_XS_OPSIZE, /* 2611 */ IC_XD_OPSIZE, /* 2612 */ IC_64BIT_XD_OPSIZE, /* 2613 */ IC_XS_OPSIZE, /* 2614 */ IC_64BIT_XD_OPSIZE, /* 2615 */ IC_OPSIZE_ADSIZE, /* 2616 */ IC_64BIT_REXW_OPSIZE, /* 2617 */ IC_XS_OPSIZE, /* 2618 */ IC_64BIT_REXW_XS, /* 2619 */ IC_XD_OPSIZE, /* 2620 */ IC_64BIT_REXW_XD, /* 2621 */ IC_XS_OPSIZE, /* 2622 */ IC_64BIT_REXW_XS, /* 2623 */ IC_VEX, /* 2624 */ IC_VEX, /* 2625 */ IC_VEX_XS, /* 2626 */ IC_VEX_XS, /* 2627 */ IC_VEX_XD, /* 2628 */ IC_VEX_XD, /* 2629 */ IC_VEX_XD, /* 2630 */ IC_VEX_XD, /* 2631 */ IC_VEX_W, /* 2632 */ IC_VEX_W, /* 2633 */ IC_VEX_W_XS, /* 2634 */ IC_VEX_W_XS, /* 2635 */ IC_VEX_W_XD, /* 2636 */ IC_VEX_W_XD, /* 2637 */ IC_VEX_W_XD, /* 2638 */ IC_VEX_W_XD, /* 2639 */ IC_VEX_OPSIZE, /* 2640 */ IC_VEX_OPSIZE, /* 2641 */ IC_VEX_OPSIZE, /* 2642 */ IC_VEX_OPSIZE, /* 2643 */ IC_VEX_OPSIZE, /* 2644 */ IC_VEX_OPSIZE, /* 2645 */ IC_VEX_OPSIZE, /* 2646 */ IC_VEX_OPSIZE, /* 2647 */ IC_VEX_W_OPSIZE, /* 2648 */ IC_VEX_W_OPSIZE, /* 2649 */ IC_VEX_W_OPSIZE, /* 2650 */ IC_VEX_W_OPSIZE, /* 2651 */ IC_VEX_W_OPSIZE, /* 2652 */ IC_VEX_W_OPSIZE, /* 2653 */ IC_VEX_W_OPSIZE, /* 2654 */ IC_VEX_W_OPSIZE, /* 2655 */ IC_VEX, /* 2656 */ IC_VEX, /* 2657 */ IC_VEX_XS, /* 2658 */ IC_VEX_XS, /* 2659 */ IC_VEX_XD, /* 2660 */ IC_VEX_XD, /* 2661 */ IC_VEX_XD, /* 2662 */ IC_VEX_XD, /* 2663 */ IC_VEX_W, /* 2664 */ IC_VEX_W, /* 2665 */ IC_VEX_W_XS, /* 2666 */ IC_VEX_W_XS, /* 2667 */ IC_VEX_W_XD, /* 2668 */ IC_VEX_W_XD, /* 2669 */ IC_VEX_W_XD, /* 2670 */ IC_VEX_W_XD, /* 2671 */ IC_VEX_OPSIZE, /* 2672 */ IC_VEX_OPSIZE, /* 2673 */ IC_VEX_OPSIZE, /* 2674 */ IC_VEX_OPSIZE, /* 2675 */ IC_VEX_OPSIZE, /* 2676 */ IC_VEX_OPSIZE, /* 2677 */ IC_VEX_OPSIZE, /* 2678 */ IC_VEX_OPSIZE, /* 2679 */ IC_VEX_W_OPSIZE, /* 2680 */ IC_VEX_W_OPSIZE, /* 2681 */ IC_VEX_W_OPSIZE, /* 2682 */ IC_VEX_W_OPSIZE, /* 2683 */ IC_VEX_W_OPSIZE, /* 2684 */ IC_VEX_W_OPSIZE, /* 2685 */ IC_VEX_W_OPSIZE, /* 2686 */ IC_VEX_W_OPSIZE, /* 2687 */ IC_VEX_L, /* 2688 */ IC_VEX_L, /* 2689 */ IC_VEX_L_XS, /* 2690 */ IC_VEX_L_XS, /* 2691 */ IC_VEX_L_XD, /* 2692 */ IC_VEX_L_XD, /* 2693 */ IC_VEX_L_XD, /* 2694 */ IC_VEX_L_XD, /* 2695 */ IC_VEX_L_W, /* 2696 */ IC_VEX_L_W, /* 2697 */ IC_VEX_L_W_XS, /* 2698 */ IC_VEX_L_W_XS, /* 2699 */ IC_VEX_L_W_XD, /* 2700 */ IC_VEX_L_W_XD, /* 2701 */ IC_VEX_L_W_XD, /* 2702 */ IC_VEX_L_W_XD, /* 2703 */ IC_VEX_L_OPSIZE, /* 2704 */ IC_VEX_L_OPSIZE, /* 2705 */ IC_VEX_L_OPSIZE, /* 2706 */ IC_VEX_L_OPSIZE, /* 2707 */ IC_VEX_L_OPSIZE, /* 2708 */ IC_VEX_L_OPSIZE, /* 2709 */ IC_VEX_L_OPSIZE, /* 2710 */ IC_VEX_L_OPSIZE, /* 2711 */ IC_VEX_L_W_OPSIZE, /* 2712 */ IC_VEX_L_W_OPSIZE, /* 2713 */ IC_VEX_L_W_OPSIZE, /* 2714 */ IC_VEX_L_W_OPSIZE, /* 2715 */ IC_VEX_L_W_OPSIZE, /* 2716 */ IC_VEX_L_W_OPSIZE, /* 2717 */ IC_VEX_L_W_OPSIZE, /* 2718 */ IC_VEX_L_W_OPSIZE, /* 2719 */ IC_VEX_L, /* 2720 */ IC_VEX_L, /* 2721 */ IC_VEX_L_XS, /* 2722 */ IC_VEX_L_XS, /* 2723 */ IC_VEX_L_XD, /* 2724 */ IC_VEX_L_XD, /* 2725 */ IC_VEX_L_XD, /* 2726 */ IC_VEX_L_XD, /* 2727 */ IC_VEX_L_W, /* 2728 */ IC_VEX_L_W, /* 2729 */ IC_VEX_L_W_XS, /* 2730 */ IC_VEX_L_W_XS, /* 2731 */ IC_VEX_L_W_XD, /* 2732 */ IC_VEX_L_W_XD, /* 2733 */ IC_VEX_L_W_XD, /* 2734 */ IC_VEX_L_W_XD, /* 2735 */ IC_VEX_L_OPSIZE, /* 2736 */ IC_VEX_L_OPSIZE, /* 2737 */ IC_VEX_L_OPSIZE, /* 2738 */ IC_VEX_L_OPSIZE, /* 2739 */ IC_VEX_L_OPSIZE, /* 2740 */ IC_VEX_L_OPSIZE, /* 2741 */ IC_VEX_L_OPSIZE, /* 2742 */ IC_VEX_L_OPSIZE, /* 2743 */ IC_VEX_L_W_OPSIZE, /* 2744 */ IC_VEX_L_W_OPSIZE, /* 2745 */ IC_VEX_L_W_OPSIZE, /* 2746 */ IC_VEX_L_W_OPSIZE, /* 2747 */ IC_VEX_L_W_OPSIZE, /* 2748 */ IC_VEX_L_W_OPSIZE, /* 2749 */ IC_VEX_L_W_OPSIZE, /* 2750 */ IC_VEX_L_W_OPSIZE, /* 2751 */ IC_VEX_L, /* 2752 */ IC_VEX_L, /* 2753 */ IC_VEX_L_XS, /* 2754 */ IC_VEX_L_XS, /* 2755 */ IC_VEX_L_XD, /* 2756 */ IC_VEX_L_XD, /* 2757 */ IC_VEX_L_XD, /* 2758 */ IC_VEX_L_XD, /* 2759 */ IC_VEX_L_W, /* 2760 */ IC_VEX_L_W, /* 2761 */ IC_VEX_L_W_XS, /* 2762 */ IC_VEX_L_W_XS, /* 2763 */ IC_VEX_L_W_XD, /* 2764 */ IC_VEX_L_W_XD, /* 2765 */ IC_VEX_L_W_XD, /* 2766 */ IC_VEX_L_W_XD, /* 2767 */ IC_VEX_L_OPSIZE, /* 2768 */ IC_VEX_L_OPSIZE, /* 2769 */ IC_VEX_L_OPSIZE, /* 2770 */ IC_VEX_L_OPSIZE, /* 2771 */ IC_VEX_L_OPSIZE, /* 2772 */ IC_VEX_L_OPSIZE, /* 2773 */ IC_VEX_L_OPSIZE, /* 2774 */ IC_VEX_L_OPSIZE, /* 2775 */ IC_VEX_L_W_OPSIZE, /* 2776 */ IC_VEX_L_W_OPSIZE, /* 2777 */ IC_VEX_L_W_OPSIZE, /* 2778 */ IC_VEX_L_W_OPSIZE, /* 2779 */ IC_VEX_L_W_OPSIZE, /* 2780 */ IC_VEX_L_W_OPSIZE, /* 2781 */ IC_VEX_L_W_OPSIZE, /* 2782 */ IC_VEX_L_W_OPSIZE, /* 2783 */ IC_VEX_L, /* 2784 */ IC_VEX_L, /* 2785 */ IC_VEX_L_XS, /* 2786 */ IC_VEX_L_XS, /* 2787 */ IC_VEX_L_XD, /* 2788 */ IC_VEX_L_XD, /* 2789 */ IC_VEX_L_XD, /* 2790 */ IC_VEX_L_XD, /* 2791 */ IC_VEX_L_W, /* 2792 */ IC_VEX_L_W, /* 2793 */ IC_VEX_L_W_XS, /* 2794 */ IC_VEX_L_W_XS, /* 2795 */ IC_VEX_L_W_XD, /* 2796 */ IC_VEX_L_W_XD, /* 2797 */ IC_VEX_L_W_XD, /* 2798 */ IC_VEX_L_W_XD, /* 2799 */ IC_VEX_L_OPSIZE, /* 2800 */ IC_VEX_L_OPSIZE, /* 2801 */ IC_VEX_L_OPSIZE, /* 2802 */ IC_VEX_L_OPSIZE, /* 2803 */ IC_VEX_L_OPSIZE, /* 2804 */ IC_VEX_L_OPSIZE, /* 2805 */ IC_VEX_L_OPSIZE, /* 2806 */ IC_VEX_L_OPSIZE, /* 2807 */ IC_VEX_L_W_OPSIZE, /* 2808 */ IC_VEX_L_W_OPSIZE, /* 2809 */ IC_VEX_L_W_OPSIZE, /* 2810 */ IC_VEX_L_W_OPSIZE, /* 2811 */ IC_VEX_L_W_OPSIZE, /* 2812 */ IC_VEX_L_W_OPSIZE, /* 2813 */ IC_VEX_L_W_OPSIZE, /* 2814 */ IC_VEX_L_W_OPSIZE, /* 2815 */ IC_EVEX_L_K, /* 2816 */ IC_EVEX_L_K, /* 2817 */ IC_EVEX_L_XS_K, /* 2818 */ IC_EVEX_L_XS_K, /* 2819 */ IC_EVEX_L_XD_K, /* 2820 */ IC_EVEX_L_XD_K, /* 2821 */ IC_EVEX_L_XD_K, /* 2822 */ IC_EVEX_L_XD_K, /* 2823 */ IC_EVEX_L_W_K, /* 2824 */ IC_EVEX_L_W_K, /* 2825 */ IC_EVEX_L_W_XS_K, /* 2826 */ IC_EVEX_L_W_XS_K, /* 2827 */ IC_EVEX_L_W_XD_K, /* 2828 */ IC_EVEX_L_W_XD_K, /* 2829 */ IC_EVEX_L_W_XD_K, /* 2830 */ IC_EVEX_L_W_XD_K, /* 2831 */ IC_EVEX_L_OPSIZE_K, /* 2832 */ IC_EVEX_L_OPSIZE_K, /* 2833 */ IC_EVEX_L_OPSIZE_K, /* 2834 */ IC_EVEX_L_OPSIZE_K, /* 2835 */ IC_EVEX_L_OPSIZE_K, /* 2836 */ IC_EVEX_L_OPSIZE_K, /* 2837 */ IC_EVEX_L_OPSIZE_K, /* 2838 */ IC_EVEX_L_OPSIZE_K, /* 2839 */ IC_EVEX_L_W_OPSIZE_K, /* 2840 */ IC_EVEX_L_W_OPSIZE_K, /* 2841 */ IC_EVEX_L_W_OPSIZE_K, /* 2842 */ IC_EVEX_L_W_OPSIZE_K, /* 2843 */ IC_EVEX_L_W_OPSIZE_K, /* 2844 */ IC_EVEX_L_W_OPSIZE_K, /* 2845 */ IC_EVEX_L_W_OPSIZE_K, /* 2846 */ IC_EVEX_L_W_OPSIZE_K, /* 2847 */ IC_EVEX_L_K, /* 2848 */ IC_EVEX_L_K, /* 2849 */ IC_EVEX_L_XS_K, /* 2850 */ IC_EVEX_L_XS_K, /* 2851 */ IC_EVEX_L_XD_K, /* 2852 */ IC_EVEX_L_XD_K, /* 2853 */ IC_EVEX_L_XD_K, /* 2854 */ IC_EVEX_L_XD_K, /* 2855 */ IC_EVEX_L_W_K, /* 2856 */ IC_EVEX_L_W_K, /* 2857 */ IC_EVEX_L_W_XS_K, /* 2858 */ IC_EVEX_L_W_XS_K, /* 2859 */ IC_EVEX_L_W_XD_K, /* 2860 */ IC_EVEX_L_W_XD_K, /* 2861 */ IC_EVEX_L_W_XD_K, /* 2862 */ IC_EVEX_L_W_XD_K, /* 2863 */ IC_EVEX_L_OPSIZE_K, /* 2864 */ IC_EVEX_L_OPSIZE_K, /* 2865 */ IC_EVEX_L_OPSIZE_K, /* 2866 */ IC_EVEX_L_OPSIZE_K, /* 2867 */ IC_EVEX_L_OPSIZE_K, /* 2868 */ IC_EVEX_L_OPSIZE_K, /* 2869 */ IC_EVEX_L_OPSIZE_K, /* 2870 */ IC_EVEX_L_OPSIZE_K, /* 2871 */ IC_EVEX_L_W_OPSIZE_K, /* 2872 */ IC_EVEX_L_W_OPSIZE_K, /* 2873 */ IC_EVEX_L_W_OPSIZE_K, /* 2874 */ IC_EVEX_L_W_OPSIZE_K, /* 2875 */ IC_EVEX_L_W_OPSIZE_K, /* 2876 */ IC_EVEX_L_W_OPSIZE_K, /* 2877 */ IC_EVEX_L_W_OPSIZE_K, /* 2878 */ IC_EVEX_L_W_OPSIZE_K, /* 2879 */ IC_EVEX_L_K, /* 2880 */ IC_EVEX_L_K, /* 2881 */ IC_EVEX_L_XS_K, /* 2882 */ IC_EVEX_L_XS_K, /* 2883 */ IC_EVEX_L_XD_K, /* 2884 */ IC_EVEX_L_XD_K, /* 2885 */ IC_EVEX_L_XD_K, /* 2886 */ IC_EVEX_L_XD_K, /* 2887 */ IC_EVEX_L_W_K, /* 2888 */ IC_EVEX_L_W_K, /* 2889 */ IC_EVEX_L_W_XS_K, /* 2890 */ IC_EVEX_L_W_XS_K, /* 2891 */ IC_EVEX_L_W_XD_K, /* 2892 */ IC_EVEX_L_W_XD_K, /* 2893 */ IC_EVEX_L_W_XD_K, /* 2894 */ IC_EVEX_L_W_XD_K, /* 2895 */ IC_EVEX_L_OPSIZE_K, /* 2896 */ IC_EVEX_L_OPSIZE_K, /* 2897 */ IC_EVEX_L_OPSIZE_K, /* 2898 */ IC_EVEX_L_OPSIZE_K, /* 2899 */ IC_EVEX_L_OPSIZE_K, /* 2900 */ IC_EVEX_L_OPSIZE_K, /* 2901 */ IC_EVEX_L_OPSIZE_K, /* 2902 */ IC_EVEX_L_OPSIZE_K, /* 2903 */ IC_EVEX_L_W_OPSIZE_K, /* 2904 */ IC_EVEX_L_W_OPSIZE_K, /* 2905 */ IC_EVEX_L_W_OPSIZE_K, /* 2906 */ IC_EVEX_L_W_OPSIZE_K, /* 2907 */ IC_EVEX_L_W_OPSIZE_K, /* 2908 */ IC_EVEX_L_W_OPSIZE_K, /* 2909 */ IC_EVEX_L_W_OPSIZE_K, /* 2910 */ IC_EVEX_L_W_OPSIZE_K, /* 2911 */ IC_EVEX_L_K, /* 2912 */ IC_EVEX_L_K, /* 2913 */ IC_EVEX_L_XS_K, /* 2914 */ IC_EVEX_L_XS_K, /* 2915 */ IC_EVEX_L_XD_K, /* 2916 */ IC_EVEX_L_XD_K, /* 2917 */ IC_EVEX_L_XD_K, /* 2918 */ IC_EVEX_L_XD_K, /* 2919 */ IC_EVEX_L_W_K, /* 2920 */ IC_EVEX_L_W_K, /* 2921 */ IC_EVEX_L_W_XS_K, /* 2922 */ IC_EVEX_L_W_XS_K, /* 2923 */ IC_EVEX_L_W_XD_K, /* 2924 */ IC_EVEX_L_W_XD_K, /* 2925 */ IC_EVEX_L_W_XD_K, /* 2926 */ IC_EVEX_L_W_XD_K, /* 2927 */ IC_EVEX_L_OPSIZE_K, /* 2928 */ IC_EVEX_L_OPSIZE_K, /* 2929 */ IC_EVEX_L_OPSIZE_K, /* 2930 */ IC_EVEX_L_OPSIZE_K, /* 2931 */ IC_EVEX_L_OPSIZE_K, /* 2932 */ IC_EVEX_L_OPSIZE_K, /* 2933 */ IC_EVEX_L_OPSIZE_K, /* 2934 */ IC_EVEX_L_OPSIZE_K, /* 2935 */ IC_EVEX_L_W_OPSIZE_K, /* 2936 */ IC_EVEX_L_W_OPSIZE_K, /* 2937 */ IC_EVEX_L_W_OPSIZE_K, /* 2938 */ IC_EVEX_L_W_OPSIZE_K, /* 2939 */ IC_EVEX_L_W_OPSIZE_K, /* 2940 */ IC_EVEX_L_W_OPSIZE_K, /* 2941 */ IC_EVEX_L_W_OPSIZE_K, /* 2942 */ IC_EVEX_L_W_OPSIZE_K, /* 2943 */ IC_EVEX_L_K, /* 2944 */ IC_EVEX_L_K, /* 2945 */ IC_EVEX_L_XS_K, /* 2946 */ IC_EVEX_L_XS_K, /* 2947 */ IC_EVEX_L_XD_K, /* 2948 */ IC_EVEX_L_XD_K, /* 2949 */ IC_EVEX_L_XD_K, /* 2950 */ IC_EVEX_L_XD_K, /* 2951 */ IC_EVEX_L_W_K, /* 2952 */ IC_EVEX_L_W_K, /* 2953 */ IC_EVEX_L_W_XS_K, /* 2954 */ IC_EVEX_L_W_XS_K, /* 2955 */ IC_EVEX_L_W_XD_K, /* 2956 */ IC_EVEX_L_W_XD_K, /* 2957 */ IC_EVEX_L_W_XD_K, /* 2958 */ IC_EVEX_L_W_XD_K, /* 2959 */ IC_EVEX_L_OPSIZE_K, /* 2960 */ IC_EVEX_L_OPSIZE_K, /* 2961 */ IC_EVEX_L_OPSIZE_K, /* 2962 */ IC_EVEX_L_OPSIZE_K, /* 2963 */ IC_EVEX_L_OPSIZE_K, /* 2964 */ IC_EVEX_L_OPSIZE_K, /* 2965 */ IC_EVEX_L_OPSIZE_K, /* 2966 */ IC_EVEX_L_OPSIZE_K, /* 2967 */ IC_EVEX_L_W_OPSIZE_K, /* 2968 */ IC_EVEX_L_W_OPSIZE_K, /* 2969 */ IC_EVEX_L_W_OPSIZE_K, /* 2970 */ IC_EVEX_L_W_OPSIZE_K, /* 2971 */ IC_EVEX_L_W_OPSIZE_K, /* 2972 */ IC_EVEX_L_W_OPSIZE_K, /* 2973 */ IC_EVEX_L_W_OPSIZE_K, /* 2974 */ IC_EVEX_L_W_OPSIZE_K, /* 2975 */ IC_EVEX_L_K, /* 2976 */ IC_EVEX_L_K, /* 2977 */ IC_EVEX_L_XS_K, /* 2978 */ IC_EVEX_L_XS_K, /* 2979 */ IC_EVEX_L_XD_K, /* 2980 */ IC_EVEX_L_XD_K, /* 2981 */ IC_EVEX_L_XD_K, /* 2982 */ IC_EVEX_L_XD_K, /* 2983 */ IC_EVEX_L_W_K, /* 2984 */ IC_EVEX_L_W_K, /* 2985 */ IC_EVEX_L_W_XS_K, /* 2986 */ IC_EVEX_L_W_XS_K, /* 2987 */ IC_EVEX_L_W_XD_K, /* 2988 */ IC_EVEX_L_W_XD_K, /* 2989 */ IC_EVEX_L_W_XD_K, /* 2990 */ IC_EVEX_L_W_XD_K, /* 2991 */ IC_EVEX_L_OPSIZE_K, /* 2992 */ IC_EVEX_L_OPSIZE_K, /* 2993 */ IC_EVEX_L_OPSIZE_K, /* 2994 */ IC_EVEX_L_OPSIZE_K, /* 2995 */ IC_EVEX_L_OPSIZE_K, /* 2996 */ IC_EVEX_L_OPSIZE_K, /* 2997 */ IC_EVEX_L_OPSIZE_K, /* 2998 */ IC_EVEX_L_OPSIZE_K, /* 2999 */ IC_EVEX_L_W_OPSIZE_K, /* 3000 */ IC_EVEX_L_W_OPSIZE_K, /* 3001 */ IC_EVEX_L_W_OPSIZE_K, /* 3002 */ IC_EVEX_L_W_OPSIZE_K, /* 3003 */ IC_EVEX_L_W_OPSIZE_K, /* 3004 */ IC_EVEX_L_W_OPSIZE_K, /* 3005 */ IC_EVEX_L_W_OPSIZE_K, /* 3006 */ IC_EVEX_L_W_OPSIZE_K, /* 3007 */ IC_EVEX_L_K, /* 3008 */ IC_EVEX_L_K, /* 3009 */ IC_EVEX_L_XS_K, /* 3010 */ IC_EVEX_L_XS_K, /* 3011 */ IC_EVEX_L_XD_K, /* 3012 */ IC_EVEX_L_XD_K, /* 3013 */ IC_EVEX_L_XD_K, /* 3014 */ IC_EVEX_L_XD_K, /* 3015 */ IC_EVEX_L_W_K, /* 3016 */ IC_EVEX_L_W_K, /* 3017 */ IC_EVEX_L_W_XS_K, /* 3018 */ IC_EVEX_L_W_XS_K, /* 3019 */ IC_EVEX_L_W_XD_K, /* 3020 */ IC_EVEX_L_W_XD_K, /* 3021 */ IC_EVEX_L_W_XD_K, /* 3022 */ IC_EVEX_L_W_XD_K, /* 3023 */ IC_EVEX_L_OPSIZE_K, /* 3024 */ IC_EVEX_L_OPSIZE_K, /* 3025 */ IC_EVEX_L_OPSIZE_K, /* 3026 */ IC_EVEX_L_OPSIZE_K, /* 3027 */ IC_EVEX_L_OPSIZE_K, /* 3028 */ IC_EVEX_L_OPSIZE_K, /* 3029 */ IC_EVEX_L_OPSIZE_K, /* 3030 */ IC_EVEX_L_OPSIZE_K, /* 3031 */ IC_EVEX_L_W_OPSIZE_K, /* 3032 */ IC_EVEX_L_W_OPSIZE_K, /* 3033 */ IC_EVEX_L_W_OPSIZE_K, /* 3034 */ IC_EVEX_L_W_OPSIZE_K, /* 3035 */ IC_EVEX_L_W_OPSIZE_K, /* 3036 */ IC_EVEX_L_W_OPSIZE_K, /* 3037 */ IC_EVEX_L_W_OPSIZE_K, /* 3038 */ IC_EVEX_L_W_OPSIZE_K, /* 3039 */ IC_EVEX_L_K, /* 3040 */ IC_EVEX_L_K, /* 3041 */ IC_EVEX_L_XS_K, /* 3042 */ IC_EVEX_L_XS_K, /* 3043 */ IC_EVEX_L_XD_K, /* 3044 */ IC_EVEX_L_XD_K, /* 3045 */ IC_EVEX_L_XD_K, /* 3046 */ IC_EVEX_L_XD_K, /* 3047 */ IC_EVEX_L_W_K, /* 3048 */ IC_EVEX_L_W_K, /* 3049 */ IC_EVEX_L_W_XS_K, /* 3050 */ IC_EVEX_L_W_XS_K, /* 3051 */ IC_EVEX_L_W_XD_K, /* 3052 */ IC_EVEX_L_W_XD_K, /* 3053 */ IC_EVEX_L_W_XD_K, /* 3054 */ IC_EVEX_L_W_XD_K, /* 3055 */ IC_EVEX_L_OPSIZE_K, /* 3056 */ IC_EVEX_L_OPSIZE_K, /* 3057 */ IC_EVEX_L_OPSIZE_K, /* 3058 */ IC_EVEX_L_OPSIZE_K, /* 3059 */ IC_EVEX_L_OPSIZE_K, /* 3060 */ IC_EVEX_L_OPSIZE_K, /* 3061 */ IC_EVEX_L_OPSIZE_K, /* 3062 */ IC_EVEX_L_OPSIZE_K, /* 3063 */ IC_EVEX_L_W_OPSIZE_K, /* 3064 */ IC_EVEX_L_W_OPSIZE_K, /* 3065 */ IC_EVEX_L_W_OPSIZE_K, /* 3066 */ IC_EVEX_L_W_OPSIZE_K, /* 3067 */ IC_EVEX_L_W_OPSIZE_K, /* 3068 */ IC_EVEX_L_W_OPSIZE_K, /* 3069 */ IC_EVEX_L_W_OPSIZE_K, /* 3070 */ IC_EVEX_L_W_OPSIZE_K, /* 3071 */ IC, /* 3072 */ IC_64BIT, /* 3073 */ IC_XS, /* 3074 */ IC_64BIT_XS, /* 3075 */ IC_XD, /* 3076 */ IC_64BIT_XD, /* 3077 */ IC_XS, /* 3078 */ IC_64BIT_XS, /* 3079 */ IC, /* 3080 */ IC_64BIT_REXW, /* 3081 */ IC_XS, /* 3082 */ IC_64BIT_REXW_XS, /* 3083 */ IC_XD, /* 3084 */ IC_64BIT_REXW_XD, /* 3085 */ IC_XS, /* 3086 */ IC_64BIT_REXW_XS, /* 3087 */ IC_OPSIZE, /* 3088 */ IC_64BIT_OPSIZE, /* 3089 */ IC_XS_OPSIZE, /* 3090 */ IC_64BIT_XS_OPSIZE, /* 3091 */ IC_XD_OPSIZE, /* 3092 */ IC_64BIT_XD_OPSIZE, /* 3093 */ IC_XS_OPSIZE, /* 3094 */ IC_64BIT_XD_OPSIZE, /* 3095 */ IC_OPSIZE, /* 3096 */ IC_64BIT_REXW_OPSIZE, /* 3097 */ IC_XS_OPSIZE, /* 3098 */ IC_64BIT_REXW_XS, /* 3099 */ IC_XD_OPSIZE, /* 3100 */ IC_64BIT_REXW_XD, /* 3101 */ IC_XS_OPSIZE, /* 3102 */ IC_64BIT_REXW_XS, /* 3103 */ IC_ADSIZE, /* 3104 */ IC_64BIT_ADSIZE, /* 3105 */ IC_XS_ADSIZE, /* 3106 */ IC_64BIT_XS_ADSIZE, /* 3107 */ IC_XD_ADSIZE, /* 3108 */ IC_64BIT_XD_ADSIZE, /* 3109 */ IC_XS_ADSIZE, /* 3110 */ IC_64BIT_XD_ADSIZE, /* 3111 */ IC_ADSIZE, /* 3112 */ IC_64BIT_REXW_ADSIZE, /* 3113 */ IC_XS_ADSIZE, /* 3114 */ IC_64BIT_REXW_XS, /* 3115 */ IC_XD_ADSIZE, /* 3116 */ IC_64BIT_REXW_XD, /* 3117 */ IC_XS_ADSIZE, /* 3118 */ IC_64BIT_REXW_XS, /* 3119 */ IC_OPSIZE_ADSIZE, /* 3120 */ IC_64BIT_OPSIZE_ADSIZE, /* 3121 */ IC_XS_OPSIZE, /* 3122 */ IC_64BIT_XS_OPSIZE, /* 3123 */ IC_XD_OPSIZE, /* 3124 */ IC_64BIT_XD_OPSIZE, /* 3125 */ IC_XS_OPSIZE, /* 3126 */ IC_64BIT_XD_OPSIZE, /* 3127 */ IC_OPSIZE_ADSIZE, /* 3128 */ IC_64BIT_REXW_OPSIZE, /* 3129 */ IC_XS_OPSIZE, /* 3130 */ IC_64BIT_REXW_XS, /* 3131 */ IC_XD_OPSIZE, /* 3132 */ IC_64BIT_REXW_XD, /* 3133 */ IC_XS_OPSIZE, /* 3134 */ IC_64BIT_REXW_XS, /* 3135 */ IC_VEX, /* 3136 */ IC_VEX, /* 3137 */ IC_VEX_XS, /* 3138 */ IC_VEX_XS, /* 3139 */ IC_VEX_XD, /* 3140 */ IC_VEX_XD, /* 3141 */ IC_VEX_XD, /* 3142 */ IC_VEX_XD, /* 3143 */ IC_VEX_W, /* 3144 */ IC_VEX_W, /* 3145 */ IC_VEX_W_XS, /* 3146 */ IC_VEX_W_XS, /* 3147 */ IC_VEX_W_XD, /* 3148 */ IC_VEX_W_XD, /* 3149 */ IC_VEX_W_XD, /* 3150 */ IC_VEX_W_XD, /* 3151 */ IC_VEX_OPSIZE, /* 3152 */ IC_VEX_OPSIZE, /* 3153 */ IC_VEX_OPSIZE, /* 3154 */ IC_VEX_OPSIZE, /* 3155 */ IC_VEX_OPSIZE, /* 3156 */ IC_VEX_OPSIZE, /* 3157 */ IC_VEX_OPSIZE, /* 3158 */ IC_VEX_OPSIZE, /* 3159 */ IC_VEX_W_OPSIZE, /* 3160 */ IC_VEX_W_OPSIZE, /* 3161 */ IC_VEX_W_OPSIZE, /* 3162 */ IC_VEX_W_OPSIZE, /* 3163 */ IC_VEX_W_OPSIZE, /* 3164 */ IC_VEX_W_OPSIZE, /* 3165 */ IC_VEX_W_OPSIZE, /* 3166 */ IC_VEX_W_OPSIZE, /* 3167 */ IC_VEX, /* 3168 */ IC_VEX, /* 3169 */ IC_VEX_XS, /* 3170 */ IC_VEX_XS, /* 3171 */ IC_VEX_XD, /* 3172 */ IC_VEX_XD, /* 3173 */ IC_VEX_XD, /* 3174 */ IC_VEX_XD, /* 3175 */ IC_VEX_W, /* 3176 */ IC_VEX_W, /* 3177 */ IC_VEX_W_XS, /* 3178 */ IC_VEX_W_XS, /* 3179 */ IC_VEX_W_XD, /* 3180 */ IC_VEX_W_XD, /* 3181 */ IC_VEX_W_XD, /* 3182 */ IC_VEX_W_XD, /* 3183 */ IC_VEX_OPSIZE, /* 3184 */ IC_VEX_OPSIZE, /* 3185 */ IC_VEX_OPSIZE, /* 3186 */ IC_VEX_OPSIZE, /* 3187 */ IC_VEX_OPSIZE, /* 3188 */ IC_VEX_OPSIZE, /* 3189 */ IC_VEX_OPSIZE, /* 3190 */ IC_VEX_OPSIZE, /* 3191 */ IC_VEX_W_OPSIZE, /* 3192 */ IC_VEX_W_OPSIZE, /* 3193 */ IC_VEX_W_OPSIZE, /* 3194 */ IC_VEX_W_OPSIZE, /* 3195 */ IC_VEX_W_OPSIZE, /* 3196 */ IC_VEX_W_OPSIZE, /* 3197 */ IC_VEX_W_OPSIZE, /* 3198 */ IC_VEX_W_OPSIZE, /* 3199 */ IC_VEX_L, /* 3200 */ IC_VEX_L, /* 3201 */ IC_VEX_L_XS, /* 3202 */ IC_VEX_L_XS, /* 3203 */ IC_VEX_L_XD, /* 3204 */ IC_VEX_L_XD, /* 3205 */ IC_VEX_L_XD, /* 3206 */ IC_VEX_L_XD, /* 3207 */ IC_VEX_L_W, /* 3208 */ IC_VEX_L_W, /* 3209 */ IC_VEX_L_W_XS, /* 3210 */ IC_VEX_L_W_XS, /* 3211 */ IC_VEX_L_W_XD, /* 3212 */ IC_VEX_L_W_XD, /* 3213 */ IC_VEX_L_W_XD, /* 3214 */ IC_VEX_L_W_XD, /* 3215 */ IC_VEX_L_OPSIZE, /* 3216 */ IC_VEX_L_OPSIZE, /* 3217 */ IC_VEX_L_OPSIZE, /* 3218 */ IC_VEX_L_OPSIZE, /* 3219 */ IC_VEX_L_OPSIZE, /* 3220 */ IC_VEX_L_OPSIZE, /* 3221 */ IC_VEX_L_OPSIZE, /* 3222 */ IC_VEX_L_OPSIZE, /* 3223 */ IC_VEX_L_W_OPSIZE, /* 3224 */ IC_VEX_L_W_OPSIZE, /* 3225 */ IC_VEX_L_W_OPSIZE, /* 3226 */ IC_VEX_L_W_OPSIZE, /* 3227 */ IC_VEX_L_W_OPSIZE, /* 3228 */ IC_VEX_L_W_OPSIZE, /* 3229 */ IC_VEX_L_W_OPSIZE, /* 3230 */ IC_VEX_L_W_OPSIZE, /* 3231 */ IC_VEX_L, /* 3232 */ IC_VEX_L, /* 3233 */ IC_VEX_L_XS, /* 3234 */ IC_VEX_L_XS, /* 3235 */ IC_VEX_L_XD, /* 3236 */ IC_VEX_L_XD, /* 3237 */ IC_VEX_L_XD, /* 3238 */ IC_VEX_L_XD, /* 3239 */ IC_VEX_L_W, /* 3240 */ IC_VEX_L_W, /* 3241 */ IC_VEX_L_W_XS, /* 3242 */ IC_VEX_L_W_XS, /* 3243 */ IC_VEX_L_W_XD, /* 3244 */ IC_VEX_L_W_XD, /* 3245 */ IC_VEX_L_W_XD, /* 3246 */ IC_VEX_L_W_XD, /* 3247 */ IC_VEX_L_OPSIZE, /* 3248 */ IC_VEX_L_OPSIZE, /* 3249 */ IC_VEX_L_OPSIZE, /* 3250 */ IC_VEX_L_OPSIZE, /* 3251 */ IC_VEX_L_OPSIZE, /* 3252 */ IC_VEX_L_OPSIZE, /* 3253 */ IC_VEX_L_OPSIZE, /* 3254 */ IC_VEX_L_OPSIZE, /* 3255 */ IC_VEX_L_W_OPSIZE, /* 3256 */ IC_VEX_L_W_OPSIZE, /* 3257 */ IC_VEX_L_W_OPSIZE, /* 3258 */ IC_VEX_L_W_OPSIZE, /* 3259 */ IC_VEX_L_W_OPSIZE, /* 3260 */ IC_VEX_L_W_OPSIZE, /* 3261 */ IC_VEX_L_W_OPSIZE, /* 3262 */ IC_VEX_L_W_OPSIZE, /* 3263 */ IC_VEX_L, /* 3264 */ IC_VEX_L, /* 3265 */ IC_VEX_L_XS, /* 3266 */ IC_VEX_L_XS, /* 3267 */ IC_VEX_L_XD, /* 3268 */ IC_VEX_L_XD, /* 3269 */ IC_VEX_L_XD, /* 3270 */ IC_VEX_L_XD, /* 3271 */ IC_VEX_L_W, /* 3272 */ IC_VEX_L_W, /* 3273 */ IC_VEX_L_W_XS, /* 3274 */ IC_VEX_L_W_XS, /* 3275 */ IC_VEX_L_W_XD, /* 3276 */ IC_VEX_L_W_XD, /* 3277 */ IC_VEX_L_W_XD, /* 3278 */ IC_VEX_L_W_XD, /* 3279 */ IC_VEX_L_OPSIZE, /* 3280 */ IC_VEX_L_OPSIZE, /* 3281 */ IC_VEX_L_OPSIZE, /* 3282 */ IC_VEX_L_OPSIZE, /* 3283 */ IC_VEX_L_OPSIZE, /* 3284 */ IC_VEX_L_OPSIZE, /* 3285 */ IC_VEX_L_OPSIZE, /* 3286 */ IC_VEX_L_OPSIZE, /* 3287 */ IC_VEX_L_W_OPSIZE, /* 3288 */ IC_VEX_L_W_OPSIZE, /* 3289 */ IC_VEX_L_W_OPSIZE, /* 3290 */ IC_VEX_L_W_OPSIZE, /* 3291 */ IC_VEX_L_W_OPSIZE, /* 3292 */ IC_VEX_L_W_OPSIZE, /* 3293 */ IC_VEX_L_W_OPSIZE, /* 3294 */ IC_VEX_L_W_OPSIZE, /* 3295 */ IC_VEX_L, /* 3296 */ IC_VEX_L, /* 3297 */ IC_VEX_L_XS, /* 3298 */ IC_VEX_L_XS, /* 3299 */ IC_VEX_L_XD, /* 3300 */ IC_VEX_L_XD, /* 3301 */ IC_VEX_L_XD, /* 3302 */ IC_VEX_L_XD, /* 3303 */ IC_VEX_L_W, /* 3304 */ IC_VEX_L_W, /* 3305 */ IC_VEX_L_W_XS, /* 3306 */ IC_VEX_L_W_XS, /* 3307 */ IC_VEX_L_W_XD, /* 3308 */ IC_VEX_L_W_XD, /* 3309 */ IC_VEX_L_W_XD, /* 3310 */ IC_VEX_L_W_XD, /* 3311 */ IC_VEX_L_OPSIZE, /* 3312 */ IC_VEX_L_OPSIZE, /* 3313 */ IC_VEX_L_OPSIZE, /* 3314 */ IC_VEX_L_OPSIZE, /* 3315 */ IC_VEX_L_OPSIZE, /* 3316 */ IC_VEX_L_OPSIZE, /* 3317 */ IC_VEX_L_OPSIZE, /* 3318 */ IC_VEX_L_OPSIZE, /* 3319 */ IC_VEX_L_W_OPSIZE, /* 3320 */ IC_VEX_L_W_OPSIZE, /* 3321 */ IC_VEX_L_W_OPSIZE, /* 3322 */ IC_VEX_L_W_OPSIZE, /* 3323 */ IC_VEX_L_W_OPSIZE, /* 3324 */ IC_VEX_L_W_OPSIZE, /* 3325 */ IC_VEX_L_W_OPSIZE, /* 3326 */ IC_VEX_L_W_OPSIZE, /* 3327 */ IC_EVEX_L2_K, /* 3328 */ IC_EVEX_L2_K, /* 3329 */ IC_EVEX_L2_XS_K, /* 3330 */ IC_EVEX_L2_XS_K, /* 3331 */ IC_EVEX_L2_XD_K, /* 3332 */ IC_EVEX_L2_XD_K, /* 3333 */ IC_EVEX_L2_XD_K, /* 3334 */ IC_EVEX_L2_XD_K, /* 3335 */ IC_EVEX_L2_W_K, /* 3336 */ IC_EVEX_L2_W_K, /* 3337 */ IC_EVEX_L2_W_XS_K, /* 3338 */ IC_EVEX_L2_W_XS_K, /* 3339 */ IC_EVEX_L2_W_XD_K, /* 3340 */ IC_EVEX_L2_W_XD_K, /* 3341 */ IC_EVEX_L2_W_XD_K, /* 3342 */ IC_EVEX_L2_W_XD_K, /* 3343 */ IC_EVEX_L2_OPSIZE_K, /* 3344 */ IC_EVEX_L2_OPSIZE_K, /* 3345 */ IC_EVEX_L2_OPSIZE_K, /* 3346 */ IC_EVEX_L2_OPSIZE_K, /* 3347 */ IC_EVEX_L2_OPSIZE_K, /* 3348 */ IC_EVEX_L2_OPSIZE_K, /* 3349 */ IC_EVEX_L2_OPSIZE_K, /* 3350 */ IC_EVEX_L2_OPSIZE_K, /* 3351 */ IC_EVEX_L2_W_OPSIZE_K, /* 3352 */ IC_EVEX_L2_W_OPSIZE_K, /* 3353 */ IC_EVEX_L2_W_OPSIZE_K, /* 3354 */ IC_EVEX_L2_W_OPSIZE_K, /* 3355 */ IC_EVEX_L2_W_OPSIZE_K, /* 3356 */ IC_EVEX_L2_W_OPSIZE_K, /* 3357 */ IC_EVEX_L2_W_OPSIZE_K, /* 3358 */ IC_EVEX_L2_W_OPSIZE_K, /* 3359 */ IC_EVEX_L2_K, /* 3360 */ IC_EVEX_L2_K, /* 3361 */ IC_EVEX_L2_XS_K, /* 3362 */ IC_EVEX_L2_XS_K, /* 3363 */ IC_EVEX_L2_XD_K, /* 3364 */ IC_EVEX_L2_XD_K, /* 3365 */ IC_EVEX_L2_XD_K, /* 3366 */ IC_EVEX_L2_XD_K, /* 3367 */ IC_EVEX_L2_W_K, /* 3368 */ IC_EVEX_L2_W_K, /* 3369 */ IC_EVEX_L2_W_XS_K, /* 3370 */ IC_EVEX_L2_W_XS_K, /* 3371 */ IC_EVEX_L2_W_XD_K, /* 3372 */ IC_EVEX_L2_W_XD_K, /* 3373 */ IC_EVEX_L2_W_XD_K, /* 3374 */ IC_EVEX_L2_W_XD_K, /* 3375 */ IC_EVEX_L2_OPSIZE_K, /* 3376 */ IC_EVEX_L2_OPSIZE_K, /* 3377 */ IC_EVEX_L2_OPSIZE_K, /* 3378 */ IC_EVEX_L2_OPSIZE_K, /* 3379 */ IC_EVEX_L2_OPSIZE_K, /* 3380 */ IC_EVEX_L2_OPSIZE_K, /* 3381 */ IC_EVEX_L2_OPSIZE_K, /* 3382 */ IC_EVEX_L2_OPSIZE_K, /* 3383 */ IC_EVEX_L2_W_OPSIZE_K, /* 3384 */ IC_EVEX_L2_W_OPSIZE_K, /* 3385 */ IC_EVEX_L2_W_OPSIZE_K, /* 3386 */ IC_EVEX_L2_W_OPSIZE_K, /* 3387 */ IC_EVEX_L2_W_OPSIZE_K, /* 3388 */ IC_EVEX_L2_W_OPSIZE_K, /* 3389 */ IC_EVEX_L2_W_OPSIZE_K, /* 3390 */ IC_EVEX_L2_W_OPSIZE_K, /* 3391 */ IC_EVEX_L2_K, /* 3392 */ IC_EVEX_L2_K, /* 3393 */ IC_EVEX_L2_XS_K, /* 3394 */ IC_EVEX_L2_XS_K, /* 3395 */ IC_EVEX_L2_XD_K, /* 3396 */ IC_EVEX_L2_XD_K, /* 3397 */ IC_EVEX_L2_XD_K, /* 3398 */ IC_EVEX_L2_XD_K, /* 3399 */ IC_EVEX_L2_W_K, /* 3400 */ IC_EVEX_L2_W_K, /* 3401 */ IC_EVEX_L2_W_XS_K, /* 3402 */ IC_EVEX_L2_W_XS_K, /* 3403 */ IC_EVEX_L2_W_XD_K, /* 3404 */ IC_EVEX_L2_W_XD_K, /* 3405 */ IC_EVEX_L2_W_XD_K, /* 3406 */ IC_EVEX_L2_W_XD_K, /* 3407 */ IC_EVEX_L2_OPSIZE_K, /* 3408 */ IC_EVEX_L2_OPSIZE_K, /* 3409 */ IC_EVEX_L2_OPSIZE_K, /* 3410 */ IC_EVEX_L2_OPSIZE_K, /* 3411 */ IC_EVEX_L2_OPSIZE_K, /* 3412 */ IC_EVEX_L2_OPSIZE_K, /* 3413 */ IC_EVEX_L2_OPSIZE_K, /* 3414 */ IC_EVEX_L2_OPSIZE_K, /* 3415 */ IC_EVEX_L2_W_OPSIZE_K, /* 3416 */ IC_EVEX_L2_W_OPSIZE_K, /* 3417 */ IC_EVEX_L2_W_OPSIZE_K, /* 3418 */ IC_EVEX_L2_W_OPSIZE_K, /* 3419 */ IC_EVEX_L2_W_OPSIZE_K, /* 3420 */ IC_EVEX_L2_W_OPSIZE_K, /* 3421 */ IC_EVEX_L2_W_OPSIZE_K, /* 3422 */ IC_EVEX_L2_W_OPSIZE_K, /* 3423 */ IC_EVEX_L2_K, /* 3424 */ IC_EVEX_L2_K, /* 3425 */ IC_EVEX_L2_XS_K, /* 3426 */ IC_EVEX_L2_XS_K, /* 3427 */ IC_EVEX_L2_XD_K, /* 3428 */ IC_EVEX_L2_XD_K, /* 3429 */ IC_EVEX_L2_XD_K, /* 3430 */ IC_EVEX_L2_XD_K, /* 3431 */ IC_EVEX_L2_W_K, /* 3432 */ IC_EVEX_L2_W_K, /* 3433 */ IC_EVEX_L2_W_XS_K, /* 3434 */ IC_EVEX_L2_W_XS_K, /* 3435 */ IC_EVEX_L2_W_XD_K, /* 3436 */ IC_EVEX_L2_W_XD_K, /* 3437 */ IC_EVEX_L2_W_XD_K, /* 3438 */ IC_EVEX_L2_W_XD_K, /* 3439 */ IC_EVEX_L2_OPSIZE_K, /* 3440 */ IC_EVEX_L2_OPSIZE_K, /* 3441 */ IC_EVEX_L2_OPSIZE_K, /* 3442 */ IC_EVEX_L2_OPSIZE_K, /* 3443 */ IC_EVEX_L2_OPSIZE_K, /* 3444 */ IC_EVEX_L2_OPSIZE_K, /* 3445 */ IC_EVEX_L2_OPSIZE_K, /* 3446 */ IC_EVEX_L2_OPSIZE_K, /* 3447 */ IC_EVEX_L2_W_OPSIZE_K, /* 3448 */ IC_EVEX_L2_W_OPSIZE_K, /* 3449 */ IC_EVEX_L2_W_OPSIZE_K, /* 3450 */ IC_EVEX_L2_W_OPSIZE_K, /* 3451 */ IC_EVEX_L2_W_OPSIZE_K, /* 3452 */ IC_EVEX_L2_W_OPSIZE_K, /* 3453 */ IC_EVEX_L2_W_OPSIZE_K, /* 3454 */ IC_EVEX_L2_W_OPSIZE_K, /* 3455 */ IC_EVEX_L2_K, /* 3456 */ IC_EVEX_L2_K, /* 3457 */ IC_EVEX_L2_XS_K, /* 3458 */ IC_EVEX_L2_XS_K, /* 3459 */ IC_EVEX_L2_XD_K, /* 3460 */ IC_EVEX_L2_XD_K, /* 3461 */ IC_EVEX_L2_XD_K, /* 3462 */ IC_EVEX_L2_XD_K, /* 3463 */ IC_EVEX_L2_W_K, /* 3464 */ IC_EVEX_L2_W_K, /* 3465 */ IC_EVEX_L2_W_XS_K, /* 3466 */ IC_EVEX_L2_W_XS_K, /* 3467 */ IC_EVEX_L2_W_XD_K, /* 3468 */ IC_EVEX_L2_W_XD_K, /* 3469 */ IC_EVEX_L2_W_XD_K, /* 3470 */ IC_EVEX_L2_W_XD_K, /* 3471 */ IC_EVEX_L2_OPSIZE_K, /* 3472 */ IC_EVEX_L2_OPSIZE_K, /* 3473 */ IC_EVEX_L2_OPSIZE_K, /* 3474 */ IC_EVEX_L2_OPSIZE_K, /* 3475 */ IC_EVEX_L2_OPSIZE_K, /* 3476 */ IC_EVEX_L2_OPSIZE_K, /* 3477 */ IC_EVEX_L2_OPSIZE_K, /* 3478 */ IC_EVEX_L2_OPSIZE_K, /* 3479 */ IC_EVEX_L2_W_OPSIZE_K, /* 3480 */ IC_EVEX_L2_W_OPSIZE_K, /* 3481 */ IC_EVEX_L2_W_OPSIZE_K, /* 3482 */ IC_EVEX_L2_W_OPSIZE_K, /* 3483 */ IC_EVEX_L2_W_OPSIZE_K, /* 3484 */ IC_EVEX_L2_W_OPSIZE_K, /* 3485 */ IC_EVEX_L2_W_OPSIZE_K, /* 3486 */ IC_EVEX_L2_W_OPSIZE_K, /* 3487 */ IC_EVEX_L2_K, /* 3488 */ IC_EVEX_L2_K, /* 3489 */ IC_EVEX_L2_XS_K, /* 3490 */ IC_EVEX_L2_XS_K, /* 3491 */ IC_EVEX_L2_XD_K, /* 3492 */ IC_EVEX_L2_XD_K, /* 3493 */ IC_EVEX_L2_XD_K, /* 3494 */ IC_EVEX_L2_XD_K, /* 3495 */ IC_EVEX_L2_W_K, /* 3496 */ IC_EVEX_L2_W_K, /* 3497 */ IC_EVEX_L2_W_XS_K, /* 3498 */ IC_EVEX_L2_W_XS_K, /* 3499 */ IC_EVEX_L2_W_XD_K, /* 3500 */ IC_EVEX_L2_W_XD_K, /* 3501 */ IC_EVEX_L2_W_XD_K, /* 3502 */ IC_EVEX_L2_W_XD_K, /* 3503 */ IC_EVEX_L2_OPSIZE_K, /* 3504 */ IC_EVEX_L2_OPSIZE_K, /* 3505 */ IC_EVEX_L2_OPSIZE_K, /* 3506 */ IC_EVEX_L2_OPSIZE_K, /* 3507 */ IC_EVEX_L2_OPSIZE_K, /* 3508 */ IC_EVEX_L2_OPSIZE_K, /* 3509 */ IC_EVEX_L2_OPSIZE_K, /* 3510 */ IC_EVEX_L2_OPSIZE_K, /* 3511 */ IC_EVEX_L2_W_OPSIZE_K, /* 3512 */ IC_EVEX_L2_W_OPSIZE_K, /* 3513 */ IC_EVEX_L2_W_OPSIZE_K, /* 3514 */ IC_EVEX_L2_W_OPSIZE_K, /* 3515 */ IC_EVEX_L2_W_OPSIZE_K, /* 3516 */ IC_EVEX_L2_W_OPSIZE_K, /* 3517 */ IC_EVEX_L2_W_OPSIZE_K, /* 3518 */ IC_EVEX_L2_W_OPSIZE_K, /* 3519 */ IC_EVEX_L2_K, /* 3520 */ IC_EVEX_L2_K, /* 3521 */ IC_EVEX_L2_XS_K, /* 3522 */ IC_EVEX_L2_XS_K, /* 3523 */ IC_EVEX_L2_XD_K, /* 3524 */ IC_EVEX_L2_XD_K, /* 3525 */ IC_EVEX_L2_XD_K, /* 3526 */ IC_EVEX_L2_XD_K, /* 3527 */ IC_EVEX_L2_W_K, /* 3528 */ IC_EVEX_L2_W_K, /* 3529 */ IC_EVEX_L2_W_XS_K, /* 3530 */ IC_EVEX_L2_W_XS_K, /* 3531 */ IC_EVEX_L2_W_XD_K, /* 3532 */ IC_EVEX_L2_W_XD_K, /* 3533 */ IC_EVEX_L2_W_XD_K, /* 3534 */ IC_EVEX_L2_W_XD_K, /* 3535 */ IC_EVEX_L2_OPSIZE_K, /* 3536 */ IC_EVEX_L2_OPSIZE_K, /* 3537 */ IC_EVEX_L2_OPSIZE_K, /* 3538 */ IC_EVEX_L2_OPSIZE_K, /* 3539 */ IC_EVEX_L2_OPSIZE_K, /* 3540 */ IC_EVEX_L2_OPSIZE_K, /* 3541 */ IC_EVEX_L2_OPSIZE_K, /* 3542 */ IC_EVEX_L2_OPSIZE_K, /* 3543 */ IC_EVEX_L2_W_OPSIZE_K, /* 3544 */ IC_EVEX_L2_W_OPSIZE_K, /* 3545 */ IC_EVEX_L2_W_OPSIZE_K, /* 3546 */ IC_EVEX_L2_W_OPSIZE_K, /* 3547 */ IC_EVEX_L2_W_OPSIZE_K, /* 3548 */ IC_EVEX_L2_W_OPSIZE_K, /* 3549 */ IC_EVEX_L2_W_OPSIZE_K, /* 3550 */ IC_EVEX_L2_W_OPSIZE_K, /* 3551 */ IC_EVEX_L2_K, /* 3552 */ IC_EVEX_L2_K, /* 3553 */ IC_EVEX_L2_XS_K, /* 3554 */ IC_EVEX_L2_XS_K, /* 3555 */ IC_EVEX_L2_XD_K, /* 3556 */ IC_EVEX_L2_XD_K, /* 3557 */ IC_EVEX_L2_XD_K, /* 3558 */ IC_EVEX_L2_XD_K, /* 3559 */ IC_EVEX_L2_W_K, /* 3560 */ IC_EVEX_L2_W_K, /* 3561 */ IC_EVEX_L2_W_XS_K, /* 3562 */ IC_EVEX_L2_W_XS_K, /* 3563 */ IC_EVEX_L2_W_XD_K, /* 3564 */ IC_EVEX_L2_W_XD_K, /* 3565 */ IC_EVEX_L2_W_XD_K, /* 3566 */ IC_EVEX_L2_W_XD_K, /* 3567 */ IC_EVEX_L2_OPSIZE_K, /* 3568 */ IC_EVEX_L2_OPSIZE_K, /* 3569 */ IC_EVEX_L2_OPSIZE_K, /* 3570 */ IC_EVEX_L2_OPSIZE_K, /* 3571 */ IC_EVEX_L2_OPSIZE_K, /* 3572 */ IC_EVEX_L2_OPSIZE_K, /* 3573 */ IC_EVEX_L2_OPSIZE_K, /* 3574 */ IC_EVEX_L2_OPSIZE_K, /* 3575 */ IC_EVEX_L2_W_OPSIZE_K, /* 3576 */ IC_EVEX_L2_W_OPSIZE_K, /* 3577 */ IC_EVEX_L2_W_OPSIZE_K, /* 3578 */ IC_EVEX_L2_W_OPSIZE_K, /* 3579 */ IC_EVEX_L2_W_OPSIZE_K, /* 3580 */ IC_EVEX_L2_W_OPSIZE_K, /* 3581 */ IC_EVEX_L2_W_OPSIZE_K, /* 3582 */ IC_EVEX_L2_W_OPSIZE_K, /* 3583 */ IC, /* 3584 */ IC_64BIT, /* 3585 */ IC_XS, /* 3586 */ IC_64BIT_XS, /* 3587 */ IC_XD, /* 3588 */ IC_64BIT_XD, /* 3589 */ IC_XS, /* 3590 */ IC_64BIT_XS, /* 3591 */ IC, /* 3592 */ IC_64BIT_REXW, /* 3593 */ IC_XS, /* 3594 */ IC_64BIT_REXW_XS, /* 3595 */ IC_XD, /* 3596 */ IC_64BIT_REXW_XD, /* 3597 */ IC_XS, /* 3598 */ IC_64BIT_REXW_XS, /* 3599 */ IC_OPSIZE, /* 3600 */ IC_64BIT_OPSIZE, /* 3601 */ IC_XS_OPSIZE, /* 3602 */ IC_64BIT_XS_OPSIZE, /* 3603 */ IC_XD_OPSIZE, /* 3604 */ IC_64BIT_XD_OPSIZE, /* 3605 */ IC_XS_OPSIZE, /* 3606 */ IC_64BIT_XD_OPSIZE, /* 3607 */ IC_OPSIZE, /* 3608 */ IC_64BIT_REXW_OPSIZE, /* 3609 */ IC_XS_OPSIZE, /* 3610 */ IC_64BIT_REXW_XS, /* 3611 */ IC_XD_OPSIZE, /* 3612 */ IC_64BIT_REXW_XD, /* 3613 */ IC_XS_OPSIZE, /* 3614 */ IC_64BIT_REXW_XS, /* 3615 */ IC_ADSIZE, /* 3616 */ IC_64BIT_ADSIZE, /* 3617 */ IC_XS_ADSIZE, /* 3618 */ IC_64BIT_XS_ADSIZE, /* 3619 */ IC_XD_ADSIZE, /* 3620 */ IC_64BIT_XD_ADSIZE, /* 3621 */ IC_XS_ADSIZE, /* 3622 */ IC_64BIT_XD_ADSIZE, /* 3623 */ IC_ADSIZE, /* 3624 */ IC_64BIT_REXW_ADSIZE, /* 3625 */ IC_XS_ADSIZE, /* 3626 */ IC_64BIT_REXW_XS, /* 3627 */ IC_XD_ADSIZE, /* 3628 */ IC_64BIT_REXW_XD, /* 3629 */ IC_XS_ADSIZE, /* 3630 */ IC_64BIT_REXW_XS, /* 3631 */ IC_OPSIZE_ADSIZE, /* 3632 */ IC_64BIT_OPSIZE_ADSIZE, /* 3633 */ IC_XS_OPSIZE, /* 3634 */ IC_64BIT_XS_OPSIZE, /* 3635 */ IC_XD_OPSIZE, /* 3636 */ IC_64BIT_XD_OPSIZE, /* 3637 */ IC_XS_OPSIZE, /* 3638 */ IC_64BIT_XD_OPSIZE, /* 3639 */ IC_OPSIZE_ADSIZE, /* 3640 */ IC_64BIT_REXW_OPSIZE, /* 3641 */ IC_XS_OPSIZE, /* 3642 */ IC_64BIT_REXW_XS, /* 3643 */ IC_XD_OPSIZE, /* 3644 */ IC_64BIT_REXW_XD, /* 3645 */ IC_XS_OPSIZE, /* 3646 */ IC_64BIT_REXW_XS, /* 3647 */ IC_VEX, /* 3648 */ IC_VEX, /* 3649 */ IC_VEX_XS, /* 3650 */ IC_VEX_XS, /* 3651 */ IC_VEX_XD, /* 3652 */ IC_VEX_XD, /* 3653 */ IC_VEX_XD, /* 3654 */ IC_VEX_XD, /* 3655 */ IC_VEX_W, /* 3656 */ IC_VEX_W, /* 3657 */ IC_VEX_W_XS, /* 3658 */ IC_VEX_W_XS, /* 3659 */ IC_VEX_W_XD, /* 3660 */ IC_VEX_W_XD, /* 3661 */ IC_VEX_W_XD, /* 3662 */ IC_VEX_W_XD, /* 3663 */ IC_VEX_OPSIZE, /* 3664 */ IC_VEX_OPSIZE, /* 3665 */ IC_VEX_OPSIZE, /* 3666 */ IC_VEX_OPSIZE, /* 3667 */ IC_VEX_OPSIZE, /* 3668 */ IC_VEX_OPSIZE, /* 3669 */ IC_VEX_OPSIZE, /* 3670 */ IC_VEX_OPSIZE, /* 3671 */ IC_VEX_W_OPSIZE, /* 3672 */ IC_VEX_W_OPSIZE, /* 3673 */ IC_VEX_W_OPSIZE, /* 3674 */ IC_VEX_W_OPSIZE, /* 3675 */ IC_VEX_W_OPSIZE, /* 3676 */ IC_VEX_W_OPSIZE, /* 3677 */ IC_VEX_W_OPSIZE, /* 3678 */ IC_VEX_W_OPSIZE, /* 3679 */ IC_VEX, /* 3680 */ IC_VEX, /* 3681 */ IC_VEX_XS, /* 3682 */ IC_VEX_XS, /* 3683 */ IC_VEX_XD, /* 3684 */ IC_VEX_XD, /* 3685 */ IC_VEX_XD, /* 3686 */ IC_VEX_XD, /* 3687 */ IC_VEX_W, /* 3688 */ IC_VEX_W, /* 3689 */ IC_VEX_W_XS, /* 3690 */ IC_VEX_W_XS, /* 3691 */ IC_VEX_W_XD, /* 3692 */ IC_VEX_W_XD, /* 3693 */ IC_VEX_W_XD, /* 3694 */ IC_VEX_W_XD, /* 3695 */ IC_VEX_OPSIZE, /* 3696 */ IC_VEX_OPSIZE, /* 3697 */ IC_VEX_OPSIZE, /* 3698 */ IC_VEX_OPSIZE, /* 3699 */ IC_VEX_OPSIZE, /* 3700 */ IC_VEX_OPSIZE, /* 3701 */ IC_VEX_OPSIZE, /* 3702 */ IC_VEX_OPSIZE, /* 3703 */ IC_VEX_W_OPSIZE, /* 3704 */ IC_VEX_W_OPSIZE, /* 3705 */ IC_VEX_W_OPSIZE, /* 3706 */ IC_VEX_W_OPSIZE, /* 3707 */ IC_VEX_W_OPSIZE, /* 3708 */ IC_VEX_W_OPSIZE, /* 3709 */ IC_VEX_W_OPSIZE, /* 3710 */ IC_VEX_W_OPSIZE, /* 3711 */ IC_VEX_L, /* 3712 */ IC_VEX_L, /* 3713 */ IC_VEX_L_XS, /* 3714 */ IC_VEX_L_XS, /* 3715 */ IC_VEX_L_XD, /* 3716 */ IC_VEX_L_XD, /* 3717 */ IC_VEX_L_XD, /* 3718 */ IC_VEX_L_XD, /* 3719 */ IC_VEX_L_W, /* 3720 */ IC_VEX_L_W, /* 3721 */ IC_VEX_L_W_XS, /* 3722 */ IC_VEX_L_W_XS, /* 3723 */ IC_VEX_L_W_XD, /* 3724 */ IC_VEX_L_W_XD, /* 3725 */ IC_VEX_L_W_XD, /* 3726 */ IC_VEX_L_W_XD, /* 3727 */ IC_VEX_L_OPSIZE, /* 3728 */ IC_VEX_L_OPSIZE, /* 3729 */ IC_VEX_L_OPSIZE, /* 3730 */ IC_VEX_L_OPSIZE, /* 3731 */ IC_VEX_L_OPSIZE, /* 3732 */ IC_VEX_L_OPSIZE, /* 3733 */ IC_VEX_L_OPSIZE, /* 3734 */ IC_VEX_L_OPSIZE, /* 3735 */ IC_VEX_L_W_OPSIZE, /* 3736 */ IC_VEX_L_W_OPSIZE, /* 3737 */ IC_VEX_L_W_OPSIZE, /* 3738 */ IC_VEX_L_W_OPSIZE, /* 3739 */ IC_VEX_L_W_OPSIZE, /* 3740 */ IC_VEX_L_W_OPSIZE, /* 3741 */ IC_VEX_L_W_OPSIZE, /* 3742 */ IC_VEX_L_W_OPSIZE, /* 3743 */ IC_VEX_L, /* 3744 */ IC_VEX_L, /* 3745 */ IC_VEX_L_XS, /* 3746 */ IC_VEX_L_XS, /* 3747 */ IC_VEX_L_XD, /* 3748 */ IC_VEX_L_XD, /* 3749 */ IC_VEX_L_XD, /* 3750 */ IC_VEX_L_XD, /* 3751 */ IC_VEX_L_W, /* 3752 */ IC_VEX_L_W, /* 3753 */ IC_VEX_L_W_XS, /* 3754 */ IC_VEX_L_W_XS, /* 3755 */ IC_VEX_L_W_XD, /* 3756 */ IC_VEX_L_W_XD, /* 3757 */ IC_VEX_L_W_XD, /* 3758 */ IC_VEX_L_W_XD, /* 3759 */ IC_VEX_L_OPSIZE, /* 3760 */ IC_VEX_L_OPSIZE, /* 3761 */ IC_VEX_L_OPSIZE, /* 3762 */ IC_VEX_L_OPSIZE, /* 3763 */ IC_VEX_L_OPSIZE, /* 3764 */ IC_VEX_L_OPSIZE, /* 3765 */ IC_VEX_L_OPSIZE, /* 3766 */ IC_VEX_L_OPSIZE, /* 3767 */ IC_VEX_L_W_OPSIZE, /* 3768 */ IC_VEX_L_W_OPSIZE, /* 3769 */ IC_VEX_L_W_OPSIZE, /* 3770 */ IC_VEX_L_W_OPSIZE, /* 3771 */ IC_VEX_L_W_OPSIZE, /* 3772 */ IC_VEX_L_W_OPSIZE, /* 3773 */ IC_VEX_L_W_OPSIZE, /* 3774 */ IC_VEX_L_W_OPSIZE, /* 3775 */ IC_VEX_L, /* 3776 */ IC_VEX_L, /* 3777 */ IC_VEX_L_XS, /* 3778 */ IC_VEX_L_XS, /* 3779 */ IC_VEX_L_XD, /* 3780 */ IC_VEX_L_XD, /* 3781 */ IC_VEX_L_XD, /* 3782 */ IC_VEX_L_XD, /* 3783 */ IC_VEX_L_W, /* 3784 */ IC_VEX_L_W, /* 3785 */ IC_VEX_L_W_XS, /* 3786 */ IC_VEX_L_W_XS, /* 3787 */ IC_VEX_L_W_XD, /* 3788 */ IC_VEX_L_W_XD, /* 3789 */ IC_VEX_L_W_XD, /* 3790 */ IC_VEX_L_W_XD, /* 3791 */ IC_VEX_L_OPSIZE, /* 3792 */ IC_VEX_L_OPSIZE, /* 3793 */ IC_VEX_L_OPSIZE, /* 3794 */ IC_VEX_L_OPSIZE, /* 3795 */ IC_VEX_L_OPSIZE, /* 3796 */ IC_VEX_L_OPSIZE, /* 3797 */ IC_VEX_L_OPSIZE, /* 3798 */ IC_VEX_L_OPSIZE, /* 3799 */ IC_VEX_L_W_OPSIZE, /* 3800 */ IC_VEX_L_W_OPSIZE, /* 3801 */ IC_VEX_L_W_OPSIZE, /* 3802 */ IC_VEX_L_W_OPSIZE, /* 3803 */ IC_VEX_L_W_OPSIZE, /* 3804 */ IC_VEX_L_W_OPSIZE, /* 3805 */ IC_VEX_L_W_OPSIZE, /* 3806 */ IC_VEX_L_W_OPSIZE, /* 3807 */ IC_VEX_L, /* 3808 */ IC_VEX_L, /* 3809 */ IC_VEX_L_XS, /* 3810 */ IC_VEX_L_XS, /* 3811 */ IC_VEX_L_XD, /* 3812 */ IC_VEX_L_XD, /* 3813 */ IC_VEX_L_XD, /* 3814 */ IC_VEX_L_XD, /* 3815 */ IC_VEX_L_W, /* 3816 */ IC_VEX_L_W, /* 3817 */ IC_VEX_L_W_XS, /* 3818 */ IC_VEX_L_W_XS, /* 3819 */ IC_VEX_L_W_XD, /* 3820 */ IC_VEX_L_W_XD, /* 3821 */ IC_VEX_L_W_XD, /* 3822 */ IC_VEX_L_W_XD, /* 3823 */ IC_VEX_L_OPSIZE, /* 3824 */ IC_VEX_L_OPSIZE, /* 3825 */ IC_VEX_L_OPSIZE, /* 3826 */ IC_VEX_L_OPSIZE, /* 3827 */ IC_VEX_L_OPSIZE, /* 3828 */ IC_VEX_L_OPSIZE, /* 3829 */ IC_VEX_L_OPSIZE, /* 3830 */ IC_VEX_L_OPSIZE, /* 3831 */ IC_VEX_L_W_OPSIZE, /* 3832 */ IC_VEX_L_W_OPSIZE, /* 3833 */ IC_VEX_L_W_OPSIZE, /* 3834 */ IC_VEX_L_W_OPSIZE, /* 3835 */ IC_VEX_L_W_OPSIZE, /* 3836 */ IC_VEX_L_W_OPSIZE, /* 3837 */ IC_VEX_L_W_OPSIZE, /* 3838 */ IC_VEX_L_W_OPSIZE, /* 3839 */ IC_EVEX_L2_K, /* 3840 */ IC_EVEX_L2_K, /* 3841 */ IC_EVEX_L2_XS_K, /* 3842 */ IC_EVEX_L2_XS_K, /* 3843 */ IC_EVEX_L2_XD_K, /* 3844 */ IC_EVEX_L2_XD_K, /* 3845 */ IC_EVEX_L2_XD_K, /* 3846 */ IC_EVEX_L2_XD_K, /* 3847 */ IC_EVEX_L2_W_K, /* 3848 */ IC_EVEX_L2_W_K, /* 3849 */ IC_EVEX_L2_W_XS_K, /* 3850 */ IC_EVEX_L2_W_XS_K, /* 3851 */ IC_EVEX_L2_W_XD_K, /* 3852 */ IC_EVEX_L2_W_XD_K, /* 3853 */ IC_EVEX_L2_W_XD_K, /* 3854 */ IC_EVEX_L2_W_XD_K, /* 3855 */ IC_EVEX_L2_OPSIZE_K, /* 3856 */ IC_EVEX_L2_OPSIZE_K, /* 3857 */ IC_EVEX_L2_OPSIZE_K, /* 3858 */ IC_EVEX_L2_OPSIZE_K, /* 3859 */ IC_EVEX_L2_OPSIZE_K, /* 3860 */ IC_EVEX_L2_OPSIZE_K, /* 3861 */ IC_EVEX_L2_OPSIZE_K, /* 3862 */ IC_EVEX_L2_OPSIZE_K, /* 3863 */ IC_EVEX_L2_W_OPSIZE_K, /* 3864 */ IC_EVEX_L2_W_OPSIZE_K, /* 3865 */ IC_EVEX_L2_W_OPSIZE_K, /* 3866 */ IC_EVEX_L2_W_OPSIZE_K, /* 3867 */ IC_EVEX_L2_W_OPSIZE_K, /* 3868 */ IC_EVEX_L2_W_OPSIZE_K, /* 3869 */ IC_EVEX_L2_W_OPSIZE_K, /* 3870 */ IC_EVEX_L2_W_OPSIZE_K, /* 3871 */ IC_EVEX_L2_K, /* 3872 */ IC_EVEX_L2_K, /* 3873 */ IC_EVEX_L2_XS_K, /* 3874 */ IC_EVEX_L2_XS_K, /* 3875 */ IC_EVEX_L2_XD_K, /* 3876 */ IC_EVEX_L2_XD_K, /* 3877 */ IC_EVEX_L2_XD_K, /* 3878 */ IC_EVEX_L2_XD_K, /* 3879 */ IC_EVEX_L2_W_K, /* 3880 */ IC_EVEX_L2_W_K, /* 3881 */ IC_EVEX_L2_W_XS_K, /* 3882 */ IC_EVEX_L2_W_XS_K, /* 3883 */ IC_EVEX_L2_W_XD_K, /* 3884 */ IC_EVEX_L2_W_XD_K, /* 3885 */ IC_EVEX_L2_W_XD_K, /* 3886 */ IC_EVEX_L2_W_XD_K, /* 3887 */ IC_EVEX_L2_OPSIZE_K, /* 3888 */ IC_EVEX_L2_OPSIZE_K, /* 3889 */ IC_EVEX_L2_OPSIZE_K, /* 3890 */ IC_EVEX_L2_OPSIZE_K, /* 3891 */ IC_EVEX_L2_OPSIZE_K, /* 3892 */ IC_EVEX_L2_OPSIZE_K, /* 3893 */ IC_EVEX_L2_OPSIZE_K, /* 3894 */ IC_EVEX_L2_OPSIZE_K, /* 3895 */ IC_EVEX_L2_W_OPSIZE_K, /* 3896 */ IC_EVEX_L2_W_OPSIZE_K, /* 3897 */ IC_EVEX_L2_W_OPSIZE_K, /* 3898 */ IC_EVEX_L2_W_OPSIZE_K, /* 3899 */ IC_EVEX_L2_W_OPSIZE_K, /* 3900 */ IC_EVEX_L2_W_OPSIZE_K, /* 3901 */ IC_EVEX_L2_W_OPSIZE_K, /* 3902 */ IC_EVEX_L2_W_OPSIZE_K, /* 3903 */ IC_EVEX_L2_K, /* 3904 */ IC_EVEX_L2_K, /* 3905 */ IC_EVEX_L2_XS_K, /* 3906 */ IC_EVEX_L2_XS_K, /* 3907 */ IC_EVEX_L2_XD_K, /* 3908 */ IC_EVEX_L2_XD_K, /* 3909 */ IC_EVEX_L2_XD_K, /* 3910 */ IC_EVEX_L2_XD_K, /* 3911 */ IC_EVEX_L2_W_K, /* 3912 */ IC_EVEX_L2_W_K, /* 3913 */ IC_EVEX_L2_W_XS_K, /* 3914 */ IC_EVEX_L2_W_XS_K, /* 3915 */ IC_EVEX_L2_W_XD_K, /* 3916 */ IC_EVEX_L2_W_XD_K, /* 3917 */ IC_EVEX_L2_W_XD_K, /* 3918 */ IC_EVEX_L2_W_XD_K, /* 3919 */ IC_EVEX_L2_OPSIZE_K, /* 3920 */ IC_EVEX_L2_OPSIZE_K, /* 3921 */ IC_EVEX_L2_OPSIZE_K, /* 3922 */ IC_EVEX_L2_OPSIZE_K, /* 3923 */ IC_EVEX_L2_OPSIZE_K, /* 3924 */ IC_EVEX_L2_OPSIZE_K, /* 3925 */ IC_EVEX_L2_OPSIZE_K, /* 3926 */ IC_EVEX_L2_OPSIZE_K, /* 3927 */ IC_EVEX_L2_W_OPSIZE_K, /* 3928 */ IC_EVEX_L2_W_OPSIZE_K, /* 3929 */ IC_EVEX_L2_W_OPSIZE_K, /* 3930 */ IC_EVEX_L2_W_OPSIZE_K, /* 3931 */ IC_EVEX_L2_W_OPSIZE_K, /* 3932 */ IC_EVEX_L2_W_OPSIZE_K, /* 3933 */ IC_EVEX_L2_W_OPSIZE_K, /* 3934 */ IC_EVEX_L2_W_OPSIZE_K, /* 3935 */ IC_EVEX_L2_K, /* 3936 */ IC_EVEX_L2_K, /* 3937 */ IC_EVEX_L2_XS_K, /* 3938 */ IC_EVEX_L2_XS_K, /* 3939 */ IC_EVEX_L2_XD_K, /* 3940 */ IC_EVEX_L2_XD_K, /* 3941 */ IC_EVEX_L2_XD_K, /* 3942 */ IC_EVEX_L2_XD_K, /* 3943 */ IC_EVEX_L2_W_K, /* 3944 */ IC_EVEX_L2_W_K, /* 3945 */ IC_EVEX_L2_W_XS_K, /* 3946 */ IC_EVEX_L2_W_XS_K, /* 3947 */ IC_EVEX_L2_W_XD_K, /* 3948 */ IC_EVEX_L2_W_XD_K, /* 3949 */ IC_EVEX_L2_W_XD_K, /* 3950 */ IC_EVEX_L2_W_XD_K, /* 3951 */ IC_EVEX_L2_OPSIZE_K, /* 3952 */ IC_EVEX_L2_OPSIZE_K, /* 3953 */ IC_EVEX_L2_OPSIZE_K, /* 3954 */ IC_EVEX_L2_OPSIZE_K, /* 3955 */ IC_EVEX_L2_OPSIZE_K, /* 3956 */ IC_EVEX_L2_OPSIZE_K, /* 3957 */ IC_EVEX_L2_OPSIZE_K, /* 3958 */ IC_EVEX_L2_OPSIZE_K, /* 3959 */ IC_EVEX_L2_W_OPSIZE_K, /* 3960 */ IC_EVEX_L2_W_OPSIZE_K, /* 3961 */ IC_EVEX_L2_W_OPSIZE_K, /* 3962 */ IC_EVEX_L2_W_OPSIZE_K, /* 3963 */ IC_EVEX_L2_W_OPSIZE_K, /* 3964 */ IC_EVEX_L2_W_OPSIZE_K, /* 3965 */ IC_EVEX_L2_W_OPSIZE_K, /* 3966 */ IC_EVEX_L2_W_OPSIZE_K, /* 3967 */ IC_EVEX_L2_K, /* 3968 */ IC_EVEX_L2_K, /* 3969 */ IC_EVEX_L2_XS_K, /* 3970 */ IC_EVEX_L2_XS_K, /* 3971 */ IC_EVEX_L2_XD_K, /* 3972 */ IC_EVEX_L2_XD_K, /* 3973 */ IC_EVEX_L2_XD_K, /* 3974 */ IC_EVEX_L2_XD_K, /* 3975 */ IC_EVEX_L2_W_K, /* 3976 */ IC_EVEX_L2_W_K, /* 3977 */ IC_EVEX_L2_W_XS_K, /* 3978 */ IC_EVEX_L2_W_XS_K, /* 3979 */ IC_EVEX_L2_W_XD_K, /* 3980 */ IC_EVEX_L2_W_XD_K, /* 3981 */ IC_EVEX_L2_W_XD_K, /* 3982 */ IC_EVEX_L2_W_XD_K, /* 3983 */ IC_EVEX_L2_OPSIZE_K, /* 3984 */ IC_EVEX_L2_OPSIZE_K, /* 3985 */ IC_EVEX_L2_OPSIZE_K, /* 3986 */ IC_EVEX_L2_OPSIZE_K, /* 3987 */ IC_EVEX_L2_OPSIZE_K, /* 3988 */ IC_EVEX_L2_OPSIZE_K, /* 3989 */ IC_EVEX_L2_OPSIZE_K, /* 3990 */ IC_EVEX_L2_OPSIZE_K, /* 3991 */ IC_EVEX_L2_W_OPSIZE_K, /* 3992 */ IC_EVEX_L2_W_OPSIZE_K, /* 3993 */ IC_EVEX_L2_W_OPSIZE_K, /* 3994 */ IC_EVEX_L2_W_OPSIZE_K, /* 3995 */ IC_EVEX_L2_W_OPSIZE_K, /* 3996 */ IC_EVEX_L2_W_OPSIZE_K, /* 3997 */ IC_EVEX_L2_W_OPSIZE_K, /* 3998 */ IC_EVEX_L2_W_OPSIZE_K, /* 3999 */ IC_EVEX_L2_K, /* 4000 */ IC_EVEX_L2_K, /* 4001 */ IC_EVEX_L2_XS_K, /* 4002 */ IC_EVEX_L2_XS_K, /* 4003 */ IC_EVEX_L2_XD_K, /* 4004 */ IC_EVEX_L2_XD_K, /* 4005 */ IC_EVEX_L2_XD_K, /* 4006 */ IC_EVEX_L2_XD_K, /* 4007 */ IC_EVEX_L2_W_K, /* 4008 */ IC_EVEX_L2_W_K, /* 4009 */ IC_EVEX_L2_W_XS_K, /* 4010 */ IC_EVEX_L2_W_XS_K, /* 4011 */ IC_EVEX_L2_W_XD_K, /* 4012 */ IC_EVEX_L2_W_XD_K, /* 4013 */ IC_EVEX_L2_W_XD_K, /* 4014 */ IC_EVEX_L2_W_XD_K, /* 4015 */ IC_EVEX_L2_OPSIZE_K, /* 4016 */ IC_EVEX_L2_OPSIZE_K, /* 4017 */ IC_EVEX_L2_OPSIZE_K, /* 4018 */ IC_EVEX_L2_OPSIZE_K, /* 4019 */ IC_EVEX_L2_OPSIZE_K, /* 4020 */ IC_EVEX_L2_OPSIZE_K, /* 4021 */ IC_EVEX_L2_OPSIZE_K, /* 4022 */ IC_EVEX_L2_OPSIZE_K, /* 4023 */ IC_EVEX_L2_W_OPSIZE_K, /* 4024 */ IC_EVEX_L2_W_OPSIZE_K, /* 4025 */ IC_EVEX_L2_W_OPSIZE_K, /* 4026 */ IC_EVEX_L2_W_OPSIZE_K, /* 4027 */ IC_EVEX_L2_W_OPSIZE_K, /* 4028 */ IC_EVEX_L2_W_OPSIZE_K, /* 4029 */ IC_EVEX_L2_W_OPSIZE_K, /* 4030 */ IC_EVEX_L2_W_OPSIZE_K, /* 4031 */ IC_EVEX_L2_K, /* 4032 */ IC_EVEX_L2_K, /* 4033 */ IC_EVEX_L2_XS_K, /* 4034 */ IC_EVEX_L2_XS_K, /* 4035 */ IC_EVEX_L2_XD_K, /* 4036 */ IC_EVEX_L2_XD_K, /* 4037 */ IC_EVEX_L2_XD_K, /* 4038 */ IC_EVEX_L2_XD_K, /* 4039 */ IC_EVEX_L2_W_K, /* 4040 */ IC_EVEX_L2_W_K, /* 4041 */ IC_EVEX_L2_W_XS_K, /* 4042 */ IC_EVEX_L2_W_XS_K, /* 4043 */ IC_EVEX_L2_W_XD_K, /* 4044 */ IC_EVEX_L2_W_XD_K, /* 4045 */ IC_EVEX_L2_W_XD_K, /* 4046 */ IC_EVEX_L2_W_XD_K, /* 4047 */ IC_EVEX_L2_OPSIZE_K, /* 4048 */ IC_EVEX_L2_OPSIZE_K, /* 4049 */ IC_EVEX_L2_OPSIZE_K, /* 4050 */ IC_EVEX_L2_OPSIZE_K, /* 4051 */ IC_EVEX_L2_OPSIZE_K, /* 4052 */ IC_EVEX_L2_OPSIZE_K, /* 4053 */ IC_EVEX_L2_OPSIZE_K, /* 4054 */ IC_EVEX_L2_OPSIZE_K, /* 4055 */ IC_EVEX_L2_W_OPSIZE_K, /* 4056 */ IC_EVEX_L2_W_OPSIZE_K, /* 4057 */ IC_EVEX_L2_W_OPSIZE_K, /* 4058 */ IC_EVEX_L2_W_OPSIZE_K, /* 4059 */ IC_EVEX_L2_W_OPSIZE_K, /* 4060 */ IC_EVEX_L2_W_OPSIZE_K, /* 4061 */ IC_EVEX_L2_W_OPSIZE_K, /* 4062 */ IC_EVEX_L2_W_OPSIZE_K, /* 4063 */ IC_EVEX_L2_K, /* 4064 */ IC_EVEX_L2_K, /* 4065 */ IC_EVEX_L2_XS_K, /* 4066 */ IC_EVEX_L2_XS_K, /* 4067 */ IC_EVEX_L2_XD_K, /* 4068 */ IC_EVEX_L2_XD_K, /* 4069 */ IC_EVEX_L2_XD_K, /* 4070 */ IC_EVEX_L2_XD_K, /* 4071 */ IC_EVEX_L2_W_K, /* 4072 */ IC_EVEX_L2_W_K, /* 4073 */ IC_EVEX_L2_W_XS_K, /* 4074 */ IC_EVEX_L2_W_XS_K, /* 4075 */ IC_EVEX_L2_W_XD_K, /* 4076 */ IC_EVEX_L2_W_XD_K, /* 4077 */ IC_EVEX_L2_W_XD_K, /* 4078 */ IC_EVEX_L2_W_XD_K, /* 4079 */ IC_EVEX_L2_OPSIZE_K, /* 4080 */ IC_EVEX_L2_OPSIZE_K, /* 4081 */ IC_EVEX_L2_OPSIZE_K, /* 4082 */ IC_EVEX_L2_OPSIZE_K, /* 4083 */ IC_EVEX_L2_OPSIZE_K, /* 4084 */ IC_EVEX_L2_OPSIZE_K, /* 4085 */ IC_EVEX_L2_OPSIZE_K, /* 4086 */ IC_EVEX_L2_OPSIZE_K, /* 4087 */ IC_EVEX_L2_W_OPSIZE_K, /* 4088 */ IC_EVEX_L2_W_OPSIZE_K, /* 4089 */ IC_EVEX_L2_W_OPSIZE_K, /* 4090 */ IC_EVEX_L2_W_OPSIZE_K, /* 4091 */ IC_EVEX_L2_W_OPSIZE_K, /* 4092 */ IC_EVEX_L2_W_OPSIZE_K, /* 4093 */ IC_EVEX_L2_W_OPSIZE_K, /* 4094 */ IC_EVEX_L2_W_OPSIZE_K, /* 4095 */ IC, /* 4096 */ IC_64BIT, /* 4097 */ IC_XS, /* 4098 */ IC_64BIT_XS, /* 4099 */ IC_XD, /* 4100 */ IC_64BIT_XD, /* 4101 */ IC_XS, /* 4102 */ IC_64BIT_XS, /* 4103 */ IC, /* 4104 */ IC_64BIT_REXW, /* 4105 */ IC_XS, /* 4106 */ IC_64BIT_REXW_XS, /* 4107 */ IC_XD, /* 4108 */ IC_64BIT_REXW_XD, /* 4109 */ IC_XS, /* 4110 */ IC_64BIT_REXW_XS, /* 4111 */ IC_OPSIZE, /* 4112 */ IC_64BIT_OPSIZE, /* 4113 */ IC_XS_OPSIZE, /* 4114 */ IC_64BIT_XS_OPSIZE, /* 4115 */ IC_XD_OPSIZE, /* 4116 */ IC_64BIT_XD_OPSIZE, /* 4117 */ IC_XS_OPSIZE, /* 4118 */ IC_64BIT_XD_OPSIZE, /* 4119 */ IC_OPSIZE, /* 4120 */ IC_64BIT_REXW_OPSIZE, /* 4121 */ IC_XS_OPSIZE, /* 4122 */ IC_64BIT_REXW_XS, /* 4123 */ IC_XD_OPSIZE, /* 4124 */ IC_64BIT_REXW_XD, /* 4125 */ IC_XS_OPSIZE, /* 4126 */ IC_64BIT_REXW_XS, /* 4127 */ IC_ADSIZE, /* 4128 */ IC_64BIT_ADSIZE, /* 4129 */ IC_XS_ADSIZE, /* 4130 */ IC_64BIT_XS_ADSIZE, /* 4131 */ IC_XD_ADSIZE, /* 4132 */ IC_64BIT_XD_ADSIZE, /* 4133 */ IC_XS_ADSIZE, /* 4134 */ IC_64BIT_XD_ADSIZE, /* 4135 */ IC_ADSIZE, /* 4136 */ IC_64BIT_REXW_ADSIZE, /* 4137 */ IC_XS_ADSIZE, /* 4138 */ IC_64BIT_REXW_XS, /* 4139 */ IC_XD_ADSIZE, /* 4140 */ IC_64BIT_REXW_XD, /* 4141 */ IC_XS_ADSIZE, /* 4142 */ IC_64BIT_REXW_XS, /* 4143 */ IC_OPSIZE_ADSIZE, /* 4144 */ IC_64BIT_OPSIZE_ADSIZE, /* 4145 */ IC_XS_OPSIZE, /* 4146 */ IC_64BIT_XS_OPSIZE, /* 4147 */ IC_XD_OPSIZE, /* 4148 */ IC_64BIT_XD_OPSIZE, /* 4149 */ IC_XS_OPSIZE, /* 4150 */ IC_64BIT_XD_OPSIZE, /* 4151 */ IC_OPSIZE_ADSIZE, /* 4152 */ IC_64BIT_REXW_OPSIZE, /* 4153 */ IC_XS_OPSIZE, /* 4154 */ IC_64BIT_REXW_XS, /* 4155 */ IC_XD_OPSIZE, /* 4156 */ IC_64BIT_REXW_XD, /* 4157 */ IC_XS_OPSIZE, /* 4158 */ IC_64BIT_REXW_XS, /* 4159 */ IC_VEX, /* 4160 */ IC_VEX, /* 4161 */ IC_VEX_XS, /* 4162 */ IC_VEX_XS, /* 4163 */ IC_VEX_XD, /* 4164 */ IC_VEX_XD, /* 4165 */ IC_VEX_XD, /* 4166 */ IC_VEX_XD, /* 4167 */ IC_VEX_W, /* 4168 */ IC_VEX_W, /* 4169 */ IC_VEX_W_XS, /* 4170 */ IC_VEX_W_XS, /* 4171 */ IC_VEX_W_XD, /* 4172 */ IC_VEX_W_XD, /* 4173 */ IC_VEX_W_XD, /* 4174 */ IC_VEX_W_XD, /* 4175 */ IC_VEX_OPSIZE, /* 4176 */ IC_VEX_OPSIZE, /* 4177 */ IC_VEX_OPSIZE, /* 4178 */ IC_VEX_OPSIZE, /* 4179 */ IC_VEX_OPSIZE, /* 4180 */ IC_VEX_OPSIZE, /* 4181 */ IC_VEX_OPSIZE, /* 4182 */ IC_VEX_OPSIZE, /* 4183 */ IC_VEX_W_OPSIZE, /* 4184 */ IC_VEX_W_OPSIZE, /* 4185 */ IC_VEX_W_OPSIZE, /* 4186 */ IC_VEX_W_OPSIZE, /* 4187 */ IC_VEX_W_OPSIZE, /* 4188 */ IC_VEX_W_OPSIZE, /* 4189 */ IC_VEX_W_OPSIZE, /* 4190 */ IC_VEX_W_OPSIZE, /* 4191 */ IC_VEX, /* 4192 */ IC_VEX, /* 4193 */ IC_VEX_XS, /* 4194 */ IC_VEX_XS, /* 4195 */ IC_VEX_XD, /* 4196 */ IC_VEX_XD, /* 4197 */ IC_VEX_XD, /* 4198 */ IC_VEX_XD, /* 4199 */ IC_VEX_W, /* 4200 */ IC_VEX_W, /* 4201 */ IC_VEX_W_XS, /* 4202 */ IC_VEX_W_XS, /* 4203 */ IC_VEX_W_XD, /* 4204 */ IC_VEX_W_XD, /* 4205 */ IC_VEX_W_XD, /* 4206 */ IC_VEX_W_XD, /* 4207 */ IC_VEX_OPSIZE, /* 4208 */ IC_VEX_OPSIZE, /* 4209 */ IC_VEX_OPSIZE, /* 4210 */ IC_VEX_OPSIZE, /* 4211 */ IC_VEX_OPSIZE, /* 4212 */ IC_VEX_OPSIZE, /* 4213 */ IC_VEX_OPSIZE, /* 4214 */ IC_VEX_OPSIZE, /* 4215 */ IC_VEX_W_OPSIZE, /* 4216 */ IC_VEX_W_OPSIZE, /* 4217 */ IC_VEX_W_OPSIZE, /* 4218 */ IC_VEX_W_OPSIZE, /* 4219 */ IC_VEX_W_OPSIZE, /* 4220 */ IC_VEX_W_OPSIZE, /* 4221 */ IC_VEX_W_OPSIZE, /* 4222 */ IC_VEX_W_OPSIZE, /* 4223 */ IC_VEX_L, /* 4224 */ IC_VEX_L, /* 4225 */ IC_VEX_L_XS, /* 4226 */ IC_VEX_L_XS, /* 4227 */ IC_VEX_L_XD, /* 4228 */ IC_VEX_L_XD, /* 4229 */ IC_VEX_L_XD, /* 4230 */ IC_VEX_L_XD, /* 4231 */ IC_VEX_L_W, /* 4232 */ IC_VEX_L_W, /* 4233 */ IC_VEX_L_W_XS, /* 4234 */ IC_VEX_L_W_XS, /* 4235 */ IC_VEX_L_W_XD, /* 4236 */ IC_VEX_L_W_XD, /* 4237 */ IC_VEX_L_W_XD, /* 4238 */ IC_VEX_L_W_XD, /* 4239 */ IC_VEX_L_OPSIZE, /* 4240 */ IC_VEX_L_OPSIZE, /* 4241 */ IC_VEX_L_OPSIZE, /* 4242 */ IC_VEX_L_OPSIZE, /* 4243 */ IC_VEX_L_OPSIZE, /* 4244 */ IC_VEX_L_OPSIZE, /* 4245 */ IC_VEX_L_OPSIZE, /* 4246 */ IC_VEX_L_OPSIZE, /* 4247 */ IC_VEX_L_W_OPSIZE, /* 4248 */ IC_VEX_L_W_OPSIZE, /* 4249 */ IC_VEX_L_W_OPSIZE, /* 4250 */ IC_VEX_L_W_OPSIZE, /* 4251 */ IC_VEX_L_W_OPSIZE, /* 4252 */ IC_VEX_L_W_OPSIZE, /* 4253 */ IC_VEX_L_W_OPSIZE, /* 4254 */ IC_VEX_L_W_OPSIZE, /* 4255 */ IC_VEX_L, /* 4256 */ IC_VEX_L, /* 4257 */ IC_VEX_L_XS, /* 4258 */ IC_VEX_L_XS, /* 4259 */ IC_VEX_L_XD, /* 4260 */ IC_VEX_L_XD, /* 4261 */ IC_VEX_L_XD, /* 4262 */ IC_VEX_L_XD, /* 4263 */ IC_VEX_L_W, /* 4264 */ IC_VEX_L_W, /* 4265 */ IC_VEX_L_W_XS, /* 4266 */ IC_VEX_L_W_XS, /* 4267 */ IC_VEX_L_W_XD, /* 4268 */ IC_VEX_L_W_XD, /* 4269 */ IC_VEX_L_W_XD, /* 4270 */ IC_VEX_L_W_XD, /* 4271 */ IC_VEX_L_OPSIZE, /* 4272 */ IC_VEX_L_OPSIZE, /* 4273 */ IC_VEX_L_OPSIZE, /* 4274 */ IC_VEX_L_OPSIZE, /* 4275 */ IC_VEX_L_OPSIZE, /* 4276 */ IC_VEX_L_OPSIZE, /* 4277 */ IC_VEX_L_OPSIZE, /* 4278 */ IC_VEX_L_OPSIZE, /* 4279 */ IC_VEX_L_W_OPSIZE, /* 4280 */ IC_VEX_L_W_OPSIZE, /* 4281 */ IC_VEX_L_W_OPSIZE, /* 4282 */ IC_VEX_L_W_OPSIZE, /* 4283 */ IC_VEX_L_W_OPSIZE, /* 4284 */ IC_VEX_L_W_OPSIZE, /* 4285 */ IC_VEX_L_W_OPSIZE, /* 4286 */ IC_VEX_L_W_OPSIZE, /* 4287 */ IC_VEX_L, /* 4288 */ IC_VEX_L, /* 4289 */ IC_VEX_L_XS, /* 4290 */ IC_VEX_L_XS, /* 4291 */ IC_VEX_L_XD, /* 4292 */ IC_VEX_L_XD, /* 4293 */ IC_VEX_L_XD, /* 4294 */ IC_VEX_L_XD, /* 4295 */ IC_VEX_L_W, /* 4296 */ IC_VEX_L_W, /* 4297 */ IC_VEX_L_W_XS, /* 4298 */ IC_VEX_L_W_XS, /* 4299 */ IC_VEX_L_W_XD, /* 4300 */ IC_VEX_L_W_XD, /* 4301 */ IC_VEX_L_W_XD, /* 4302 */ IC_VEX_L_W_XD, /* 4303 */ IC_VEX_L_OPSIZE, /* 4304 */ IC_VEX_L_OPSIZE, /* 4305 */ IC_VEX_L_OPSIZE, /* 4306 */ IC_VEX_L_OPSIZE, /* 4307 */ IC_VEX_L_OPSIZE, /* 4308 */ IC_VEX_L_OPSIZE, /* 4309 */ IC_VEX_L_OPSIZE, /* 4310 */ IC_VEX_L_OPSIZE, /* 4311 */ IC_VEX_L_W_OPSIZE, /* 4312 */ IC_VEX_L_W_OPSIZE, /* 4313 */ IC_VEX_L_W_OPSIZE, /* 4314 */ IC_VEX_L_W_OPSIZE, /* 4315 */ IC_VEX_L_W_OPSIZE, /* 4316 */ IC_VEX_L_W_OPSIZE, /* 4317 */ IC_VEX_L_W_OPSIZE, /* 4318 */ IC_VEX_L_W_OPSIZE, /* 4319 */ IC_VEX_L, /* 4320 */ IC_VEX_L, /* 4321 */ IC_VEX_L_XS, /* 4322 */ IC_VEX_L_XS, /* 4323 */ IC_VEX_L_XD, /* 4324 */ IC_VEX_L_XD, /* 4325 */ IC_VEX_L_XD, /* 4326 */ IC_VEX_L_XD, /* 4327 */ IC_VEX_L_W, /* 4328 */ IC_VEX_L_W, /* 4329 */ IC_VEX_L_W_XS, /* 4330 */ IC_VEX_L_W_XS, /* 4331 */ IC_VEX_L_W_XD, /* 4332 */ IC_VEX_L_W_XD, /* 4333 */ IC_VEX_L_W_XD, /* 4334 */ IC_VEX_L_W_XD, /* 4335 */ IC_VEX_L_OPSIZE, /* 4336 */ IC_VEX_L_OPSIZE, /* 4337 */ IC_VEX_L_OPSIZE, /* 4338 */ IC_VEX_L_OPSIZE, /* 4339 */ IC_VEX_L_OPSIZE, /* 4340 */ IC_VEX_L_OPSIZE, /* 4341 */ IC_VEX_L_OPSIZE, /* 4342 */ IC_VEX_L_OPSIZE, /* 4343 */ IC_VEX_L_W_OPSIZE, /* 4344 */ IC_VEX_L_W_OPSIZE, /* 4345 */ IC_VEX_L_W_OPSIZE, /* 4346 */ IC_VEX_L_W_OPSIZE, /* 4347 */ IC_VEX_L_W_OPSIZE, /* 4348 */ IC_VEX_L_W_OPSIZE, /* 4349 */ IC_VEX_L_W_OPSIZE, /* 4350 */ IC_VEX_L_W_OPSIZE, /* 4351 */ IC_EVEX_KZ, /* 4352 */ IC_EVEX_KZ, /* 4353 */ IC_EVEX_XS_KZ, /* 4354 */ IC_EVEX_XS_KZ, /* 4355 */ IC_EVEX_XD_KZ, /* 4356 */ IC_EVEX_XD_KZ, /* 4357 */ IC_EVEX_XD_KZ, /* 4358 */ IC_EVEX_XD_KZ, /* 4359 */ IC_EVEX_W_KZ, /* 4360 */ IC_EVEX_W_KZ, /* 4361 */ IC_EVEX_W_XS_KZ, /* 4362 */ IC_EVEX_W_XS_KZ, /* 4363 */ IC_EVEX_W_XD_KZ, /* 4364 */ IC_EVEX_W_XD_KZ, /* 4365 */ IC_EVEX_W_XD_KZ, /* 4366 */ IC_EVEX_W_XD_KZ, /* 4367 */ IC_EVEX_OPSIZE_KZ, /* 4368 */ IC_EVEX_OPSIZE_KZ, /* 4369 */ IC_EVEX_OPSIZE_KZ, /* 4370 */ IC_EVEX_OPSIZE_KZ, /* 4371 */ IC_EVEX_OPSIZE_KZ, /* 4372 */ IC_EVEX_OPSIZE_KZ, /* 4373 */ IC_EVEX_OPSIZE_KZ, /* 4374 */ IC_EVEX_OPSIZE_KZ, /* 4375 */ IC_EVEX_W_OPSIZE_KZ, /* 4376 */ IC_EVEX_W_OPSIZE_KZ, /* 4377 */ IC_EVEX_W_OPSIZE_KZ, /* 4378 */ IC_EVEX_W_OPSIZE_KZ, /* 4379 */ IC_EVEX_W_OPSIZE_KZ, /* 4380 */ IC_EVEX_W_OPSIZE_KZ, /* 4381 */ IC_EVEX_W_OPSIZE_KZ, /* 4382 */ IC_EVEX_W_OPSIZE_KZ, /* 4383 */ IC_EVEX_KZ, /* 4384 */ IC_EVEX_KZ, /* 4385 */ IC_EVEX_XS_KZ, /* 4386 */ IC_EVEX_XS_KZ, /* 4387 */ IC_EVEX_XD_KZ, /* 4388 */ IC_EVEX_XD_KZ, /* 4389 */ IC_EVEX_XD_KZ, /* 4390 */ IC_EVEX_XD_KZ, /* 4391 */ IC_EVEX_W_KZ, /* 4392 */ IC_EVEX_W_KZ, /* 4393 */ IC_EVEX_W_XS_KZ, /* 4394 */ IC_EVEX_W_XS_KZ, /* 4395 */ IC_EVEX_W_XD_KZ, /* 4396 */ IC_EVEX_W_XD_KZ, /* 4397 */ IC_EVEX_W_XD_KZ, /* 4398 */ IC_EVEX_W_XD_KZ, /* 4399 */ IC_EVEX_OPSIZE_KZ, /* 4400 */ IC_EVEX_OPSIZE_KZ, /* 4401 */ IC_EVEX_OPSIZE_KZ, /* 4402 */ IC_EVEX_OPSIZE_KZ, /* 4403 */ IC_EVEX_OPSIZE_KZ, /* 4404 */ IC_EVEX_OPSIZE_KZ, /* 4405 */ IC_EVEX_OPSIZE_KZ, /* 4406 */ IC_EVEX_OPSIZE_KZ, /* 4407 */ IC_EVEX_W_OPSIZE_KZ, /* 4408 */ IC_EVEX_W_OPSIZE_KZ, /* 4409 */ IC_EVEX_W_OPSIZE_KZ, /* 4410 */ IC_EVEX_W_OPSIZE_KZ, /* 4411 */ IC_EVEX_W_OPSIZE_KZ, /* 4412 */ IC_EVEX_W_OPSIZE_KZ, /* 4413 */ IC_EVEX_W_OPSIZE_KZ, /* 4414 */ IC_EVEX_W_OPSIZE_KZ, /* 4415 */ IC_EVEX_KZ, /* 4416 */ IC_EVEX_KZ, /* 4417 */ IC_EVEX_XS_KZ, /* 4418 */ IC_EVEX_XS_KZ, /* 4419 */ IC_EVEX_XD_KZ, /* 4420 */ IC_EVEX_XD_KZ, /* 4421 */ IC_EVEX_XD_KZ, /* 4422 */ IC_EVEX_XD_KZ, /* 4423 */ IC_EVEX_W_KZ, /* 4424 */ IC_EVEX_W_KZ, /* 4425 */ IC_EVEX_W_XS_KZ, /* 4426 */ IC_EVEX_W_XS_KZ, /* 4427 */ IC_EVEX_W_XD_KZ, /* 4428 */ IC_EVEX_W_XD_KZ, /* 4429 */ IC_EVEX_W_XD_KZ, /* 4430 */ IC_EVEX_W_XD_KZ, /* 4431 */ IC_EVEX_OPSIZE_KZ, /* 4432 */ IC_EVEX_OPSIZE_KZ, /* 4433 */ IC_EVEX_OPSIZE_KZ, /* 4434 */ IC_EVEX_OPSIZE_KZ, /* 4435 */ IC_EVEX_OPSIZE_KZ, /* 4436 */ IC_EVEX_OPSIZE_KZ, /* 4437 */ IC_EVEX_OPSIZE_KZ, /* 4438 */ IC_EVEX_OPSIZE_KZ, /* 4439 */ IC_EVEX_W_OPSIZE_KZ, /* 4440 */ IC_EVEX_W_OPSIZE_KZ, /* 4441 */ IC_EVEX_W_OPSIZE_KZ, /* 4442 */ IC_EVEX_W_OPSIZE_KZ, /* 4443 */ IC_EVEX_W_OPSIZE_KZ, /* 4444 */ IC_EVEX_W_OPSIZE_KZ, /* 4445 */ IC_EVEX_W_OPSIZE_KZ, /* 4446 */ IC_EVEX_W_OPSIZE_KZ, /* 4447 */ IC_EVEX_KZ, /* 4448 */ IC_EVEX_KZ, /* 4449 */ IC_EVEX_XS_KZ, /* 4450 */ IC_EVEX_XS_KZ, /* 4451 */ IC_EVEX_XD_KZ, /* 4452 */ IC_EVEX_XD_KZ, /* 4453 */ IC_EVEX_XD_KZ, /* 4454 */ IC_EVEX_XD_KZ, /* 4455 */ IC_EVEX_W_KZ, /* 4456 */ IC_EVEX_W_KZ, /* 4457 */ IC_EVEX_W_XS_KZ, /* 4458 */ IC_EVEX_W_XS_KZ, /* 4459 */ IC_EVEX_W_XD_KZ, /* 4460 */ IC_EVEX_W_XD_KZ, /* 4461 */ IC_EVEX_W_XD_KZ, /* 4462 */ IC_EVEX_W_XD_KZ, /* 4463 */ IC_EVEX_OPSIZE_KZ, /* 4464 */ IC_EVEX_OPSIZE_KZ, /* 4465 */ IC_EVEX_OPSIZE_KZ, /* 4466 */ IC_EVEX_OPSIZE_KZ, /* 4467 */ IC_EVEX_OPSIZE_KZ, /* 4468 */ IC_EVEX_OPSIZE_KZ, /* 4469 */ IC_EVEX_OPSIZE_KZ, /* 4470 */ IC_EVEX_OPSIZE_KZ, /* 4471 */ IC_EVEX_W_OPSIZE_KZ, /* 4472 */ IC_EVEX_W_OPSIZE_KZ, /* 4473 */ IC_EVEX_W_OPSIZE_KZ, /* 4474 */ IC_EVEX_W_OPSIZE_KZ, /* 4475 */ IC_EVEX_W_OPSIZE_KZ, /* 4476 */ IC_EVEX_W_OPSIZE_KZ, /* 4477 */ IC_EVEX_W_OPSIZE_KZ, /* 4478 */ IC_EVEX_W_OPSIZE_KZ, /* 4479 */ IC_EVEX_KZ, /* 4480 */ IC_EVEX_KZ, /* 4481 */ IC_EVEX_XS_KZ, /* 4482 */ IC_EVEX_XS_KZ, /* 4483 */ IC_EVEX_XD_KZ, /* 4484 */ IC_EVEX_XD_KZ, /* 4485 */ IC_EVEX_XD_KZ, /* 4486 */ IC_EVEX_XD_KZ, /* 4487 */ IC_EVEX_W_KZ, /* 4488 */ IC_EVEX_W_KZ, /* 4489 */ IC_EVEX_W_XS_KZ, /* 4490 */ IC_EVEX_W_XS_KZ, /* 4491 */ IC_EVEX_W_XD_KZ, /* 4492 */ IC_EVEX_W_XD_KZ, /* 4493 */ IC_EVEX_W_XD_KZ, /* 4494 */ IC_EVEX_W_XD_KZ, /* 4495 */ IC_EVEX_OPSIZE_KZ, /* 4496 */ IC_EVEX_OPSIZE_KZ, /* 4497 */ IC_EVEX_OPSIZE_KZ, /* 4498 */ IC_EVEX_OPSIZE_KZ, /* 4499 */ IC_EVEX_OPSIZE_KZ, /* 4500 */ IC_EVEX_OPSIZE_KZ, /* 4501 */ IC_EVEX_OPSIZE_KZ, /* 4502 */ IC_EVEX_OPSIZE_KZ, /* 4503 */ IC_EVEX_W_OPSIZE_KZ, /* 4504 */ IC_EVEX_W_OPSIZE_KZ, /* 4505 */ IC_EVEX_W_OPSIZE_KZ, /* 4506 */ IC_EVEX_W_OPSIZE_KZ, /* 4507 */ IC_EVEX_W_OPSIZE_KZ, /* 4508 */ IC_EVEX_W_OPSIZE_KZ, /* 4509 */ IC_EVEX_W_OPSIZE_KZ, /* 4510 */ IC_EVEX_W_OPSIZE_KZ, /* 4511 */ IC_EVEX_KZ, /* 4512 */ IC_EVEX_KZ, /* 4513 */ IC_EVEX_XS_KZ, /* 4514 */ IC_EVEX_XS_KZ, /* 4515 */ IC_EVEX_XD_KZ, /* 4516 */ IC_EVEX_XD_KZ, /* 4517 */ IC_EVEX_XD_KZ, /* 4518 */ IC_EVEX_XD_KZ, /* 4519 */ IC_EVEX_W_KZ, /* 4520 */ IC_EVEX_W_KZ, /* 4521 */ IC_EVEX_W_XS_KZ, /* 4522 */ IC_EVEX_W_XS_KZ, /* 4523 */ IC_EVEX_W_XD_KZ, /* 4524 */ IC_EVEX_W_XD_KZ, /* 4525 */ IC_EVEX_W_XD_KZ, /* 4526 */ IC_EVEX_W_XD_KZ, /* 4527 */ IC_EVEX_OPSIZE_KZ, /* 4528 */ IC_EVEX_OPSIZE_KZ, /* 4529 */ IC_EVEX_OPSIZE_KZ, /* 4530 */ IC_EVEX_OPSIZE_KZ, /* 4531 */ IC_EVEX_OPSIZE_KZ, /* 4532 */ IC_EVEX_OPSIZE_KZ, /* 4533 */ IC_EVEX_OPSIZE_KZ, /* 4534 */ IC_EVEX_OPSIZE_KZ, /* 4535 */ IC_EVEX_W_OPSIZE_KZ, /* 4536 */ IC_EVEX_W_OPSIZE_KZ, /* 4537 */ IC_EVEX_W_OPSIZE_KZ, /* 4538 */ IC_EVEX_W_OPSIZE_KZ, /* 4539 */ IC_EVEX_W_OPSIZE_KZ, /* 4540 */ IC_EVEX_W_OPSIZE_KZ, /* 4541 */ IC_EVEX_W_OPSIZE_KZ, /* 4542 */ IC_EVEX_W_OPSIZE_KZ, /* 4543 */ IC_EVEX_KZ, /* 4544 */ IC_EVEX_KZ, /* 4545 */ IC_EVEX_XS_KZ, /* 4546 */ IC_EVEX_XS_KZ, /* 4547 */ IC_EVEX_XD_KZ, /* 4548 */ IC_EVEX_XD_KZ, /* 4549 */ IC_EVEX_XD_KZ, /* 4550 */ IC_EVEX_XD_KZ, /* 4551 */ IC_EVEX_W_KZ, /* 4552 */ IC_EVEX_W_KZ, /* 4553 */ IC_EVEX_W_XS_KZ, /* 4554 */ IC_EVEX_W_XS_KZ, /* 4555 */ IC_EVEX_W_XD_KZ, /* 4556 */ IC_EVEX_W_XD_KZ, /* 4557 */ IC_EVEX_W_XD_KZ, /* 4558 */ IC_EVEX_W_XD_KZ, /* 4559 */ IC_EVEX_OPSIZE_KZ, /* 4560 */ IC_EVEX_OPSIZE_KZ, /* 4561 */ IC_EVEX_OPSIZE_KZ, /* 4562 */ IC_EVEX_OPSIZE_KZ, /* 4563 */ IC_EVEX_OPSIZE_KZ, /* 4564 */ IC_EVEX_OPSIZE_KZ, /* 4565 */ IC_EVEX_OPSIZE_KZ, /* 4566 */ IC_EVEX_OPSIZE_KZ, /* 4567 */ IC_EVEX_W_OPSIZE_KZ, /* 4568 */ IC_EVEX_W_OPSIZE_KZ, /* 4569 */ IC_EVEX_W_OPSIZE_KZ, /* 4570 */ IC_EVEX_W_OPSIZE_KZ, /* 4571 */ IC_EVEX_W_OPSIZE_KZ, /* 4572 */ IC_EVEX_W_OPSIZE_KZ, /* 4573 */ IC_EVEX_W_OPSIZE_KZ, /* 4574 */ IC_EVEX_W_OPSIZE_KZ, /* 4575 */ IC_EVEX_KZ, /* 4576 */ IC_EVEX_KZ, /* 4577 */ IC_EVEX_XS_KZ, /* 4578 */ IC_EVEX_XS_KZ, /* 4579 */ IC_EVEX_XD_KZ, /* 4580 */ IC_EVEX_XD_KZ, /* 4581 */ IC_EVEX_XD_KZ, /* 4582 */ IC_EVEX_XD_KZ, /* 4583 */ IC_EVEX_W_KZ, /* 4584 */ IC_EVEX_W_KZ, /* 4585 */ IC_EVEX_W_XS_KZ, /* 4586 */ IC_EVEX_W_XS_KZ, /* 4587 */ IC_EVEX_W_XD_KZ, /* 4588 */ IC_EVEX_W_XD_KZ, /* 4589 */ IC_EVEX_W_XD_KZ, /* 4590 */ IC_EVEX_W_XD_KZ, /* 4591 */ IC_EVEX_OPSIZE_KZ, /* 4592 */ IC_EVEX_OPSIZE_KZ, /* 4593 */ IC_EVEX_OPSIZE_KZ, /* 4594 */ IC_EVEX_OPSIZE_KZ, /* 4595 */ IC_EVEX_OPSIZE_KZ, /* 4596 */ IC_EVEX_OPSIZE_KZ, /* 4597 */ IC_EVEX_OPSIZE_KZ, /* 4598 */ IC_EVEX_OPSIZE_KZ, /* 4599 */ IC_EVEX_W_OPSIZE_KZ, /* 4600 */ IC_EVEX_W_OPSIZE_KZ, /* 4601 */ IC_EVEX_W_OPSIZE_KZ, /* 4602 */ IC_EVEX_W_OPSIZE_KZ, /* 4603 */ IC_EVEX_W_OPSIZE_KZ, /* 4604 */ IC_EVEX_W_OPSIZE_KZ, /* 4605 */ IC_EVEX_W_OPSIZE_KZ, /* 4606 */ IC_EVEX_W_OPSIZE_KZ, /* 4607 */ IC, /* 4608 */ IC_64BIT, /* 4609 */ IC_XS, /* 4610 */ IC_64BIT_XS, /* 4611 */ IC_XD, /* 4612 */ IC_64BIT_XD, /* 4613 */ IC_XS, /* 4614 */ IC_64BIT_XS, /* 4615 */ IC, /* 4616 */ IC_64BIT_REXW, /* 4617 */ IC_XS, /* 4618 */ IC_64BIT_REXW_XS, /* 4619 */ IC_XD, /* 4620 */ IC_64BIT_REXW_XD, /* 4621 */ IC_XS, /* 4622 */ IC_64BIT_REXW_XS, /* 4623 */ IC_OPSIZE, /* 4624 */ IC_64BIT_OPSIZE, /* 4625 */ IC_XS_OPSIZE, /* 4626 */ IC_64BIT_XS_OPSIZE, /* 4627 */ IC_XD_OPSIZE, /* 4628 */ IC_64BIT_XD_OPSIZE, /* 4629 */ IC_XS_OPSIZE, /* 4630 */ IC_64BIT_XD_OPSIZE, /* 4631 */ IC_OPSIZE, /* 4632 */ IC_64BIT_REXW_OPSIZE, /* 4633 */ IC_XS_OPSIZE, /* 4634 */ IC_64BIT_REXW_XS, /* 4635 */ IC_XD_OPSIZE, /* 4636 */ IC_64BIT_REXW_XD, /* 4637 */ IC_XS_OPSIZE, /* 4638 */ IC_64BIT_REXW_XS, /* 4639 */ IC_ADSIZE, /* 4640 */ IC_64BIT_ADSIZE, /* 4641 */ IC_XS_ADSIZE, /* 4642 */ IC_64BIT_XS_ADSIZE, /* 4643 */ IC_XD_ADSIZE, /* 4644 */ IC_64BIT_XD_ADSIZE, /* 4645 */ IC_XS_ADSIZE, /* 4646 */ IC_64BIT_XD_ADSIZE, /* 4647 */ IC_ADSIZE, /* 4648 */ IC_64BIT_REXW_ADSIZE, /* 4649 */ IC_XS_ADSIZE, /* 4650 */ IC_64BIT_REXW_XS, /* 4651 */ IC_XD_ADSIZE, /* 4652 */ IC_64BIT_REXW_XD, /* 4653 */ IC_XS_ADSIZE, /* 4654 */ IC_64BIT_REXW_XS, /* 4655 */ IC_OPSIZE_ADSIZE, /* 4656 */ IC_64BIT_OPSIZE_ADSIZE, /* 4657 */ IC_XS_OPSIZE, /* 4658 */ IC_64BIT_XS_OPSIZE, /* 4659 */ IC_XD_OPSIZE, /* 4660 */ IC_64BIT_XD_OPSIZE, /* 4661 */ IC_XS_OPSIZE, /* 4662 */ IC_64BIT_XD_OPSIZE, /* 4663 */ IC_OPSIZE_ADSIZE, /* 4664 */ IC_64BIT_REXW_OPSIZE, /* 4665 */ IC_XS_OPSIZE, /* 4666 */ IC_64BIT_REXW_XS, /* 4667 */ IC_XD_OPSIZE, /* 4668 */ IC_64BIT_REXW_XD, /* 4669 */ IC_XS_OPSIZE, /* 4670 */ IC_64BIT_REXW_XS, /* 4671 */ IC_VEX, /* 4672 */ IC_VEX, /* 4673 */ IC_VEX_XS, /* 4674 */ IC_VEX_XS, /* 4675 */ IC_VEX_XD, /* 4676 */ IC_VEX_XD, /* 4677 */ IC_VEX_XD, /* 4678 */ IC_VEX_XD, /* 4679 */ IC_VEX_W, /* 4680 */ IC_VEX_W, /* 4681 */ IC_VEX_W_XS, /* 4682 */ IC_VEX_W_XS, /* 4683 */ IC_VEX_W_XD, /* 4684 */ IC_VEX_W_XD, /* 4685 */ IC_VEX_W_XD, /* 4686 */ IC_VEX_W_XD, /* 4687 */ IC_VEX_OPSIZE, /* 4688 */ IC_VEX_OPSIZE, /* 4689 */ IC_VEX_OPSIZE, /* 4690 */ IC_VEX_OPSIZE, /* 4691 */ IC_VEX_OPSIZE, /* 4692 */ IC_VEX_OPSIZE, /* 4693 */ IC_VEX_OPSIZE, /* 4694 */ IC_VEX_OPSIZE, /* 4695 */ IC_VEX_W_OPSIZE, /* 4696 */ IC_VEX_W_OPSIZE, /* 4697 */ IC_VEX_W_OPSIZE, /* 4698 */ IC_VEX_W_OPSIZE, /* 4699 */ IC_VEX_W_OPSIZE, /* 4700 */ IC_VEX_W_OPSIZE, /* 4701 */ IC_VEX_W_OPSIZE, /* 4702 */ IC_VEX_W_OPSIZE, /* 4703 */ IC_VEX, /* 4704 */ IC_VEX, /* 4705 */ IC_VEX_XS, /* 4706 */ IC_VEX_XS, /* 4707 */ IC_VEX_XD, /* 4708 */ IC_VEX_XD, /* 4709 */ IC_VEX_XD, /* 4710 */ IC_VEX_XD, /* 4711 */ IC_VEX_W, /* 4712 */ IC_VEX_W, /* 4713 */ IC_VEX_W_XS, /* 4714 */ IC_VEX_W_XS, /* 4715 */ IC_VEX_W_XD, /* 4716 */ IC_VEX_W_XD, /* 4717 */ IC_VEX_W_XD, /* 4718 */ IC_VEX_W_XD, /* 4719 */ IC_VEX_OPSIZE, /* 4720 */ IC_VEX_OPSIZE, /* 4721 */ IC_VEX_OPSIZE, /* 4722 */ IC_VEX_OPSIZE, /* 4723 */ IC_VEX_OPSIZE, /* 4724 */ IC_VEX_OPSIZE, /* 4725 */ IC_VEX_OPSIZE, /* 4726 */ IC_VEX_OPSIZE, /* 4727 */ IC_VEX_W_OPSIZE, /* 4728 */ IC_VEX_W_OPSIZE, /* 4729 */ IC_VEX_W_OPSIZE, /* 4730 */ IC_VEX_W_OPSIZE, /* 4731 */ IC_VEX_W_OPSIZE, /* 4732 */ IC_VEX_W_OPSIZE, /* 4733 */ IC_VEX_W_OPSIZE, /* 4734 */ IC_VEX_W_OPSIZE, /* 4735 */ IC_VEX_L, /* 4736 */ IC_VEX_L, /* 4737 */ IC_VEX_L_XS, /* 4738 */ IC_VEX_L_XS, /* 4739 */ IC_VEX_L_XD, /* 4740 */ IC_VEX_L_XD, /* 4741 */ IC_VEX_L_XD, /* 4742 */ IC_VEX_L_XD, /* 4743 */ IC_VEX_L_W, /* 4744 */ IC_VEX_L_W, /* 4745 */ IC_VEX_L_W_XS, /* 4746 */ IC_VEX_L_W_XS, /* 4747 */ IC_VEX_L_W_XD, /* 4748 */ IC_VEX_L_W_XD, /* 4749 */ IC_VEX_L_W_XD, /* 4750 */ IC_VEX_L_W_XD, /* 4751 */ IC_VEX_L_OPSIZE, /* 4752 */ IC_VEX_L_OPSIZE, /* 4753 */ IC_VEX_L_OPSIZE, /* 4754 */ IC_VEX_L_OPSIZE, /* 4755 */ IC_VEX_L_OPSIZE, /* 4756 */ IC_VEX_L_OPSIZE, /* 4757 */ IC_VEX_L_OPSIZE, /* 4758 */ IC_VEX_L_OPSIZE, /* 4759 */ IC_VEX_L_W_OPSIZE, /* 4760 */ IC_VEX_L_W_OPSIZE, /* 4761 */ IC_VEX_L_W_OPSIZE, /* 4762 */ IC_VEX_L_W_OPSIZE, /* 4763 */ IC_VEX_L_W_OPSIZE, /* 4764 */ IC_VEX_L_W_OPSIZE, /* 4765 */ IC_VEX_L_W_OPSIZE, /* 4766 */ IC_VEX_L_W_OPSIZE, /* 4767 */ IC_VEX_L, /* 4768 */ IC_VEX_L, /* 4769 */ IC_VEX_L_XS, /* 4770 */ IC_VEX_L_XS, /* 4771 */ IC_VEX_L_XD, /* 4772 */ IC_VEX_L_XD, /* 4773 */ IC_VEX_L_XD, /* 4774 */ IC_VEX_L_XD, /* 4775 */ IC_VEX_L_W, /* 4776 */ IC_VEX_L_W, /* 4777 */ IC_VEX_L_W_XS, /* 4778 */ IC_VEX_L_W_XS, /* 4779 */ IC_VEX_L_W_XD, /* 4780 */ IC_VEX_L_W_XD, /* 4781 */ IC_VEX_L_W_XD, /* 4782 */ IC_VEX_L_W_XD, /* 4783 */ IC_VEX_L_OPSIZE, /* 4784 */ IC_VEX_L_OPSIZE, /* 4785 */ IC_VEX_L_OPSIZE, /* 4786 */ IC_VEX_L_OPSIZE, /* 4787 */ IC_VEX_L_OPSIZE, /* 4788 */ IC_VEX_L_OPSIZE, /* 4789 */ IC_VEX_L_OPSIZE, /* 4790 */ IC_VEX_L_OPSIZE, /* 4791 */ IC_VEX_L_W_OPSIZE, /* 4792 */ IC_VEX_L_W_OPSIZE, /* 4793 */ IC_VEX_L_W_OPSIZE, /* 4794 */ IC_VEX_L_W_OPSIZE, /* 4795 */ IC_VEX_L_W_OPSIZE, /* 4796 */ IC_VEX_L_W_OPSIZE, /* 4797 */ IC_VEX_L_W_OPSIZE, /* 4798 */ IC_VEX_L_W_OPSIZE, /* 4799 */ IC_VEX_L, /* 4800 */ IC_VEX_L, /* 4801 */ IC_VEX_L_XS, /* 4802 */ IC_VEX_L_XS, /* 4803 */ IC_VEX_L_XD, /* 4804 */ IC_VEX_L_XD, /* 4805 */ IC_VEX_L_XD, /* 4806 */ IC_VEX_L_XD, /* 4807 */ IC_VEX_L_W, /* 4808 */ IC_VEX_L_W, /* 4809 */ IC_VEX_L_W_XS, /* 4810 */ IC_VEX_L_W_XS, /* 4811 */ IC_VEX_L_W_XD, /* 4812 */ IC_VEX_L_W_XD, /* 4813 */ IC_VEX_L_W_XD, /* 4814 */ IC_VEX_L_W_XD, /* 4815 */ IC_VEX_L_OPSIZE, /* 4816 */ IC_VEX_L_OPSIZE, /* 4817 */ IC_VEX_L_OPSIZE, /* 4818 */ IC_VEX_L_OPSIZE, /* 4819 */ IC_VEX_L_OPSIZE, /* 4820 */ IC_VEX_L_OPSIZE, /* 4821 */ IC_VEX_L_OPSIZE, /* 4822 */ IC_VEX_L_OPSIZE, /* 4823 */ IC_VEX_L_W_OPSIZE, /* 4824 */ IC_VEX_L_W_OPSIZE, /* 4825 */ IC_VEX_L_W_OPSIZE, /* 4826 */ IC_VEX_L_W_OPSIZE, /* 4827 */ IC_VEX_L_W_OPSIZE, /* 4828 */ IC_VEX_L_W_OPSIZE, /* 4829 */ IC_VEX_L_W_OPSIZE, /* 4830 */ IC_VEX_L_W_OPSIZE, /* 4831 */ IC_VEX_L, /* 4832 */ IC_VEX_L, /* 4833 */ IC_VEX_L_XS, /* 4834 */ IC_VEX_L_XS, /* 4835 */ IC_VEX_L_XD, /* 4836 */ IC_VEX_L_XD, /* 4837 */ IC_VEX_L_XD, /* 4838 */ IC_VEX_L_XD, /* 4839 */ IC_VEX_L_W, /* 4840 */ IC_VEX_L_W, /* 4841 */ IC_VEX_L_W_XS, /* 4842 */ IC_VEX_L_W_XS, /* 4843 */ IC_VEX_L_W_XD, /* 4844 */ IC_VEX_L_W_XD, /* 4845 */ IC_VEX_L_W_XD, /* 4846 */ IC_VEX_L_W_XD, /* 4847 */ IC_VEX_L_OPSIZE, /* 4848 */ IC_VEX_L_OPSIZE, /* 4849 */ IC_VEX_L_OPSIZE, /* 4850 */ IC_VEX_L_OPSIZE, /* 4851 */ IC_VEX_L_OPSIZE, /* 4852 */ IC_VEX_L_OPSIZE, /* 4853 */ IC_VEX_L_OPSIZE, /* 4854 */ IC_VEX_L_OPSIZE, /* 4855 */ IC_VEX_L_W_OPSIZE, /* 4856 */ IC_VEX_L_W_OPSIZE, /* 4857 */ IC_VEX_L_W_OPSIZE, /* 4858 */ IC_VEX_L_W_OPSIZE, /* 4859 */ IC_VEX_L_W_OPSIZE, /* 4860 */ IC_VEX_L_W_OPSIZE, /* 4861 */ IC_VEX_L_W_OPSIZE, /* 4862 */ IC_VEX_L_W_OPSIZE, /* 4863 */ IC_EVEX_L_KZ, /* 4864 */ IC_EVEX_L_KZ, /* 4865 */ IC_EVEX_L_XS_KZ, /* 4866 */ IC_EVEX_L_XS_KZ, /* 4867 */ IC_EVEX_L_XD_KZ, /* 4868 */ IC_EVEX_L_XD_KZ, /* 4869 */ IC_EVEX_L_XD_KZ, /* 4870 */ IC_EVEX_L_XD_KZ, /* 4871 */ IC_EVEX_L_W_KZ, /* 4872 */ IC_EVEX_L_W_KZ, /* 4873 */ IC_EVEX_L_W_XS_KZ, /* 4874 */ IC_EVEX_L_W_XS_KZ, /* 4875 */ IC_EVEX_L_W_XD_KZ, /* 4876 */ IC_EVEX_L_W_XD_KZ, /* 4877 */ IC_EVEX_L_W_XD_KZ, /* 4878 */ IC_EVEX_L_W_XD_KZ, /* 4879 */ IC_EVEX_L_OPSIZE_KZ, /* 4880 */ IC_EVEX_L_OPSIZE_KZ, /* 4881 */ IC_EVEX_L_OPSIZE_KZ, /* 4882 */ IC_EVEX_L_OPSIZE_KZ, /* 4883 */ IC_EVEX_L_OPSIZE_KZ, /* 4884 */ IC_EVEX_L_OPSIZE_KZ, /* 4885 */ IC_EVEX_L_OPSIZE_KZ, /* 4886 */ IC_EVEX_L_OPSIZE_KZ, /* 4887 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4888 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4889 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4890 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4891 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4892 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4893 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4894 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4895 */ IC_EVEX_L_KZ, /* 4896 */ IC_EVEX_L_KZ, /* 4897 */ IC_EVEX_L_XS_KZ, /* 4898 */ IC_EVEX_L_XS_KZ, /* 4899 */ IC_EVEX_L_XD_KZ, /* 4900 */ IC_EVEX_L_XD_KZ, /* 4901 */ IC_EVEX_L_XD_KZ, /* 4902 */ IC_EVEX_L_XD_KZ, /* 4903 */ IC_EVEX_L_W_KZ, /* 4904 */ IC_EVEX_L_W_KZ, /* 4905 */ IC_EVEX_L_W_XS_KZ, /* 4906 */ IC_EVEX_L_W_XS_KZ, /* 4907 */ IC_EVEX_L_W_XD_KZ, /* 4908 */ IC_EVEX_L_W_XD_KZ, /* 4909 */ IC_EVEX_L_W_XD_KZ, /* 4910 */ IC_EVEX_L_W_XD_KZ, /* 4911 */ IC_EVEX_L_OPSIZE_KZ, /* 4912 */ IC_EVEX_L_OPSIZE_KZ, /* 4913 */ IC_EVEX_L_OPSIZE_KZ, /* 4914 */ IC_EVEX_L_OPSIZE_KZ, /* 4915 */ IC_EVEX_L_OPSIZE_KZ, /* 4916 */ IC_EVEX_L_OPSIZE_KZ, /* 4917 */ IC_EVEX_L_OPSIZE_KZ, /* 4918 */ IC_EVEX_L_OPSIZE_KZ, /* 4919 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4920 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4921 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4922 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4923 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4924 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4925 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4926 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4927 */ IC_EVEX_L_KZ, /* 4928 */ IC_EVEX_L_KZ, /* 4929 */ IC_EVEX_L_XS_KZ, /* 4930 */ IC_EVEX_L_XS_KZ, /* 4931 */ IC_EVEX_L_XD_KZ, /* 4932 */ IC_EVEX_L_XD_KZ, /* 4933 */ IC_EVEX_L_XD_KZ, /* 4934 */ IC_EVEX_L_XD_KZ, /* 4935 */ IC_EVEX_L_W_KZ, /* 4936 */ IC_EVEX_L_W_KZ, /* 4937 */ IC_EVEX_L_W_XS_KZ, /* 4938 */ IC_EVEX_L_W_XS_KZ, /* 4939 */ IC_EVEX_L_W_XD_KZ, /* 4940 */ IC_EVEX_L_W_XD_KZ, /* 4941 */ IC_EVEX_L_W_XD_KZ, /* 4942 */ IC_EVEX_L_W_XD_KZ, /* 4943 */ IC_EVEX_L_OPSIZE_KZ, /* 4944 */ IC_EVEX_L_OPSIZE_KZ, /* 4945 */ IC_EVEX_L_OPSIZE_KZ, /* 4946 */ IC_EVEX_L_OPSIZE_KZ, /* 4947 */ IC_EVEX_L_OPSIZE_KZ, /* 4948 */ IC_EVEX_L_OPSIZE_KZ, /* 4949 */ IC_EVEX_L_OPSIZE_KZ, /* 4950 */ IC_EVEX_L_OPSIZE_KZ, /* 4951 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4952 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4953 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4954 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4955 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4956 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4957 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4958 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4959 */ IC_EVEX_L_KZ, /* 4960 */ IC_EVEX_L_KZ, /* 4961 */ IC_EVEX_L_XS_KZ, /* 4962 */ IC_EVEX_L_XS_KZ, /* 4963 */ IC_EVEX_L_XD_KZ, /* 4964 */ IC_EVEX_L_XD_KZ, /* 4965 */ IC_EVEX_L_XD_KZ, /* 4966 */ IC_EVEX_L_XD_KZ, /* 4967 */ IC_EVEX_L_W_KZ, /* 4968 */ IC_EVEX_L_W_KZ, /* 4969 */ IC_EVEX_L_W_XS_KZ, /* 4970 */ IC_EVEX_L_W_XS_KZ, /* 4971 */ IC_EVEX_L_W_XD_KZ, /* 4972 */ IC_EVEX_L_W_XD_KZ, /* 4973 */ IC_EVEX_L_W_XD_KZ, /* 4974 */ IC_EVEX_L_W_XD_KZ, /* 4975 */ IC_EVEX_L_OPSIZE_KZ, /* 4976 */ IC_EVEX_L_OPSIZE_KZ, /* 4977 */ IC_EVEX_L_OPSIZE_KZ, /* 4978 */ IC_EVEX_L_OPSIZE_KZ, /* 4979 */ IC_EVEX_L_OPSIZE_KZ, /* 4980 */ IC_EVEX_L_OPSIZE_KZ, /* 4981 */ IC_EVEX_L_OPSIZE_KZ, /* 4982 */ IC_EVEX_L_OPSIZE_KZ, /* 4983 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4984 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4985 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4986 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4987 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4988 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4989 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4990 */ IC_EVEX_L_W_OPSIZE_KZ, /* 4991 */ IC_EVEX_L_KZ, /* 4992 */ IC_EVEX_L_KZ, /* 4993 */ IC_EVEX_L_XS_KZ, /* 4994 */ IC_EVEX_L_XS_KZ, /* 4995 */ IC_EVEX_L_XD_KZ, /* 4996 */ IC_EVEX_L_XD_KZ, /* 4997 */ IC_EVEX_L_XD_KZ, /* 4998 */ IC_EVEX_L_XD_KZ, /* 4999 */ IC_EVEX_L_W_KZ, /* 5000 */ IC_EVEX_L_W_KZ, /* 5001 */ IC_EVEX_L_W_XS_KZ, /* 5002 */ IC_EVEX_L_W_XS_KZ, /* 5003 */ IC_EVEX_L_W_XD_KZ, /* 5004 */ IC_EVEX_L_W_XD_KZ, /* 5005 */ IC_EVEX_L_W_XD_KZ, /* 5006 */ IC_EVEX_L_W_XD_KZ, /* 5007 */ IC_EVEX_L_OPSIZE_KZ, /* 5008 */ IC_EVEX_L_OPSIZE_KZ, /* 5009 */ IC_EVEX_L_OPSIZE_KZ, /* 5010 */ IC_EVEX_L_OPSIZE_KZ, /* 5011 */ IC_EVEX_L_OPSIZE_KZ, /* 5012 */ IC_EVEX_L_OPSIZE_KZ, /* 5013 */ IC_EVEX_L_OPSIZE_KZ, /* 5014 */ IC_EVEX_L_OPSIZE_KZ, /* 5015 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5016 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5017 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5018 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5019 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5020 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5021 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5022 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5023 */ IC_EVEX_L_KZ, /* 5024 */ IC_EVEX_L_KZ, /* 5025 */ IC_EVEX_L_XS_KZ, /* 5026 */ IC_EVEX_L_XS_KZ, /* 5027 */ IC_EVEX_L_XD_KZ, /* 5028 */ IC_EVEX_L_XD_KZ, /* 5029 */ IC_EVEX_L_XD_KZ, /* 5030 */ IC_EVEX_L_XD_KZ, /* 5031 */ IC_EVEX_L_W_KZ, /* 5032 */ IC_EVEX_L_W_KZ, /* 5033 */ IC_EVEX_L_W_XS_KZ, /* 5034 */ IC_EVEX_L_W_XS_KZ, /* 5035 */ IC_EVEX_L_W_XD_KZ, /* 5036 */ IC_EVEX_L_W_XD_KZ, /* 5037 */ IC_EVEX_L_W_XD_KZ, /* 5038 */ IC_EVEX_L_W_XD_KZ, /* 5039 */ IC_EVEX_L_OPSIZE_KZ, /* 5040 */ IC_EVEX_L_OPSIZE_KZ, /* 5041 */ IC_EVEX_L_OPSIZE_KZ, /* 5042 */ IC_EVEX_L_OPSIZE_KZ, /* 5043 */ IC_EVEX_L_OPSIZE_KZ, /* 5044 */ IC_EVEX_L_OPSIZE_KZ, /* 5045 */ IC_EVEX_L_OPSIZE_KZ, /* 5046 */ IC_EVEX_L_OPSIZE_KZ, /* 5047 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5048 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5049 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5050 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5051 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5052 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5053 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5054 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5055 */ IC_EVEX_L_KZ, /* 5056 */ IC_EVEX_L_KZ, /* 5057 */ IC_EVEX_L_XS_KZ, /* 5058 */ IC_EVEX_L_XS_KZ, /* 5059 */ IC_EVEX_L_XD_KZ, /* 5060 */ IC_EVEX_L_XD_KZ, /* 5061 */ IC_EVEX_L_XD_KZ, /* 5062 */ IC_EVEX_L_XD_KZ, /* 5063 */ IC_EVEX_L_W_KZ, /* 5064 */ IC_EVEX_L_W_KZ, /* 5065 */ IC_EVEX_L_W_XS_KZ, /* 5066 */ IC_EVEX_L_W_XS_KZ, /* 5067 */ IC_EVEX_L_W_XD_KZ, /* 5068 */ IC_EVEX_L_W_XD_KZ, /* 5069 */ IC_EVEX_L_W_XD_KZ, /* 5070 */ IC_EVEX_L_W_XD_KZ, /* 5071 */ IC_EVEX_L_OPSIZE_KZ, /* 5072 */ IC_EVEX_L_OPSIZE_KZ, /* 5073 */ IC_EVEX_L_OPSIZE_KZ, /* 5074 */ IC_EVEX_L_OPSIZE_KZ, /* 5075 */ IC_EVEX_L_OPSIZE_KZ, /* 5076 */ IC_EVEX_L_OPSIZE_KZ, /* 5077 */ IC_EVEX_L_OPSIZE_KZ, /* 5078 */ IC_EVEX_L_OPSIZE_KZ, /* 5079 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5080 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5081 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5082 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5083 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5084 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5085 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5086 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5087 */ IC_EVEX_L_KZ, /* 5088 */ IC_EVEX_L_KZ, /* 5089 */ IC_EVEX_L_XS_KZ, /* 5090 */ IC_EVEX_L_XS_KZ, /* 5091 */ IC_EVEX_L_XD_KZ, /* 5092 */ IC_EVEX_L_XD_KZ, /* 5093 */ IC_EVEX_L_XD_KZ, /* 5094 */ IC_EVEX_L_XD_KZ, /* 5095 */ IC_EVEX_L_W_KZ, /* 5096 */ IC_EVEX_L_W_KZ, /* 5097 */ IC_EVEX_L_W_XS_KZ, /* 5098 */ IC_EVEX_L_W_XS_KZ, /* 5099 */ IC_EVEX_L_W_XD_KZ, /* 5100 */ IC_EVEX_L_W_XD_KZ, /* 5101 */ IC_EVEX_L_W_XD_KZ, /* 5102 */ IC_EVEX_L_W_XD_KZ, /* 5103 */ IC_EVEX_L_OPSIZE_KZ, /* 5104 */ IC_EVEX_L_OPSIZE_KZ, /* 5105 */ IC_EVEX_L_OPSIZE_KZ, /* 5106 */ IC_EVEX_L_OPSIZE_KZ, /* 5107 */ IC_EVEX_L_OPSIZE_KZ, /* 5108 */ IC_EVEX_L_OPSIZE_KZ, /* 5109 */ IC_EVEX_L_OPSIZE_KZ, /* 5110 */ IC_EVEX_L_OPSIZE_KZ, /* 5111 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5112 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5113 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5114 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5115 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5116 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5117 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5118 */ IC_EVEX_L_W_OPSIZE_KZ, /* 5119 */ IC, /* 5120 */ IC_64BIT, /* 5121 */ IC_XS, /* 5122 */ IC_64BIT_XS, /* 5123 */ IC_XD, /* 5124 */ IC_64BIT_XD, /* 5125 */ IC_XS, /* 5126 */ IC_64BIT_XS, /* 5127 */ IC, /* 5128 */ IC_64BIT_REXW, /* 5129 */ IC_XS, /* 5130 */ IC_64BIT_REXW_XS, /* 5131 */ IC_XD, /* 5132 */ IC_64BIT_REXW_XD, /* 5133 */ IC_XS, /* 5134 */ IC_64BIT_REXW_XS, /* 5135 */ IC_OPSIZE, /* 5136 */ IC_64BIT_OPSIZE, /* 5137 */ IC_XS_OPSIZE, /* 5138 */ IC_64BIT_XS_OPSIZE, /* 5139 */ IC_XD_OPSIZE, /* 5140 */ IC_64BIT_XD_OPSIZE, /* 5141 */ IC_XS_OPSIZE, /* 5142 */ IC_64BIT_XD_OPSIZE, /* 5143 */ IC_OPSIZE, /* 5144 */ IC_64BIT_REXW_OPSIZE, /* 5145 */ IC_XS_OPSIZE, /* 5146 */ IC_64BIT_REXW_XS, /* 5147 */ IC_XD_OPSIZE, /* 5148 */ IC_64BIT_REXW_XD, /* 5149 */ IC_XS_OPSIZE, /* 5150 */ IC_64BIT_REXW_XS, /* 5151 */ IC_ADSIZE, /* 5152 */ IC_64BIT_ADSIZE, /* 5153 */ IC_XS_ADSIZE, /* 5154 */ IC_64BIT_XS_ADSIZE, /* 5155 */ IC_XD_ADSIZE, /* 5156 */ IC_64BIT_XD_ADSIZE, /* 5157 */ IC_XS_ADSIZE, /* 5158 */ IC_64BIT_XD_ADSIZE, /* 5159 */ IC_ADSIZE, /* 5160 */ IC_64BIT_REXW_ADSIZE, /* 5161 */ IC_XS_ADSIZE, /* 5162 */ IC_64BIT_REXW_XS, /* 5163 */ IC_XD_ADSIZE, /* 5164 */ IC_64BIT_REXW_XD, /* 5165 */ IC_XS_ADSIZE, /* 5166 */ IC_64BIT_REXW_XS, /* 5167 */ IC_OPSIZE_ADSIZE, /* 5168 */ IC_64BIT_OPSIZE_ADSIZE, /* 5169 */ IC_XS_OPSIZE, /* 5170 */ IC_64BIT_XS_OPSIZE, /* 5171 */ IC_XD_OPSIZE, /* 5172 */ IC_64BIT_XD_OPSIZE, /* 5173 */ IC_XS_OPSIZE, /* 5174 */ IC_64BIT_XD_OPSIZE, /* 5175 */ IC_OPSIZE_ADSIZE, /* 5176 */ IC_64BIT_REXW_OPSIZE, /* 5177 */ IC_XS_OPSIZE, /* 5178 */ IC_64BIT_REXW_XS, /* 5179 */ IC_XD_OPSIZE, /* 5180 */ IC_64BIT_REXW_XD, /* 5181 */ IC_XS_OPSIZE, /* 5182 */ IC_64BIT_REXW_XS, /* 5183 */ IC_VEX, /* 5184 */ IC_VEX, /* 5185 */ IC_VEX_XS, /* 5186 */ IC_VEX_XS, /* 5187 */ IC_VEX_XD, /* 5188 */ IC_VEX_XD, /* 5189 */ IC_VEX_XD, /* 5190 */ IC_VEX_XD, /* 5191 */ IC_VEX_W, /* 5192 */ IC_VEX_W, /* 5193 */ IC_VEX_W_XS, /* 5194 */ IC_VEX_W_XS, /* 5195 */ IC_VEX_W_XD, /* 5196 */ IC_VEX_W_XD, /* 5197 */ IC_VEX_W_XD, /* 5198 */ IC_VEX_W_XD, /* 5199 */ IC_VEX_OPSIZE, /* 5200 */ IC_VEX_OPSIZE, /* 5201 */ IC_VEX_OPSIZE, /* 5202 */ IC_VEX_OPSIZE, /* 5203 */ IC_VEX_OPSIZE, /* 5204 */ IC_VEX_OPSIZE, /* 5205 */ IC_VEX_OPSIZE, /* 5206 */ IC_VEX_OPSIZE, /* 5207 */ IC_VEX_W_OPSIZE, /* 5208 */ IC_VEX_W_OPSIZE, /* 5209 */ IC_VEX_W_OPSIZE, /* 5210 */ IC_VEX_W_OPSIZE, /* 5211 */ IC_VEX_W_OPSIZE, /* 5212 */ IC_VEX_W_OPSIZE, /* 5213 */ IC_VEX_W_OPSIZE, /* 5214 */ IC_VEX_W_OPSIZE, /* 5215 */ IC_VEX, /* 5216 */ IC_VEX, /* 5217 */ IC_VEX_XS, /* 5218 */ IC_VEX_XS, /* 5219 */ IC_VEX_XD, /* 5220 */ IC_VEX_XD, /* 5221 */ IC_VEX_XD, /* 5222 */ IC_VEX_XD, /* 5223 */ IC_VEX_W, /* 5224 */ IC_VEX_W, /* 5225 */ IC_VEX_W_XS, /* 5226 */ IC_VEX_W_XS, /* 5227 */ IC_VEX_W_XD, /* 5228 */ IC_VEX_W_XD, /* 5229 */ IC_VEX_W_XD, /* 5230 */ IC_VEX_W_XD, /* 5231 */ IC_VEX_OPSIZE, /* 5232 */ IC_VEX_OPSIZE, /* 5233 */ IC_VEX_OPSIZE, /* 5234 */ IC_VEX_OPSIZE, /* 5235 */ IC_VEX_OPSIZE, /* 5236 */ IC_VEX_OPSIZE, /* 5237 */ IC_VEX_OPSIZE, /* 5238 */ IC_VEX_OPSIZE, /* 5239 */ IC_VEX_W_OPSIZE, /* 5240 */ IC_VEX_W_OPSIZE, /* 5241 */ IC_VEX_W_OPSIZE, /* 5242 */ IC_VEX_W_OPSIZE, /* 5243 */ IC_VEX_W_OPSIZE, /* 5244 */ IC_VEX_W_OPSIZE, /* 5245 */ IC_VEX_W_OPSIZE, /* 5246 */ IC_VEX_W_OPSIZE, /* 5247 */ IC_VEX_L, /* 5248 */ IC_VEX_L, /* 5249 */ IC_VEX_L_XS, /* 5250 */ IC_VEX_L_XS, /* 5251 */ IC_VEX_L_XD, /* 5252 */ IC_VEX_L_XD, /* 5253 */ IC_VEX_L_XD, /* 5254 */ IC_VEX_L_XD, /* 5255 */ IC_VEX_L_W, /* 5256 */ IC_VEX_L_W, /* 5257 */ IC_VEX_L_W_XS, /* 5258 */ IC_VEX_L_W_XS, /* 5259 */ IC_VEX_L_W_XD, /* 5260 */ IC_VEX_L_W_XD, /* 5261 */ IC_VEX_L_W_XD, /* 5262 */ IC_VEX_L_W_XD, /* 5263 */ IC_VEX_L_OPSIZE, /* 5264 */ IC_VEX_L_OPSIZE, /* 5265 */ IC_VEX_L_OPSIZE, /* 5266 */ IC_VEX_L_OPSIZE, /* 5267 */ IC_VEX_L_OPSIZE, /* 5268 */ IC_VEX_L_OPSIZE, /* 5269 */ IC_VEX_L_OPSIZE, /* 5270 */ IC_VEX_L_OPSIZE, /* 5271 */ IC_VEX_L_W_OPSIZE, /* 5272 */ IC_VEX_L_W_OPSIZE, /* 5273 */ IC_VEX_L_W_OPSIZE, /* 5274 */ IC_VEX_L_W_OPSIZE, /* 5275 */ IC_VEX_L_W_OPSIZE, /* 5276 */ IC_VEX_L_W_OPSIZE, /* 5277 */ IC_VEX_L_W_OPSIZE, /* 5278 */ IC_VEX_L_W_OPSIZE, /* 5279 */ IC_VEX_L, /* 5280 */ IC_VEX_L, /* 5281 */ IC_VEX_L_XS, /* 5282 */ IC_VEX_L_XS, /* 5283 */ IC_VEX_L_XD, /* 5284 */ IC_VEX_L_XD, /* 5285 */ IC_VEX_L_XD, /* 5286 */ IC_VEX_L_XD, /* 5287 */ IC_VEX_L_W, /* 5288 */ IC_VEX_L_W, /* 5289 */ IC_VEX_L_W_XS, /* 5290 */ IC_VEX_L_W_XS, /* 5291 */ IC_VEX_L_W_XD, /* 5292 */ IC_VEX_L_W_XD, /* 5293 */ IC_VEX_L_W_XD, /* 5294 */ IC_VEX_L_W_XD, /* 5295 */ IC_VEX_L_OPSIZE, /* 5296 */ IC_VEX_L_OPSIZE, /* 5297 */ IC_VEX_L_OPSIZE, /* 5298 */ IC_VEX_L_OPSIZE, /* 5299 */ IC_VEX_L_OPSIZE, /* 5300 */ IC_VEX_L_OPSIZE, /* 5301 */ IC_VEX_L_OPSIZE, /* 5302 */ IC_VEX_L_OPSIZE, /* 5303 */ IC_VEX_L_W_OPSIZE, /* 5304 */ IC_VEX_L_W_OPSIZE, /* 5305 */ IC_VEX_L_W_OPSIZE, /* 5306 */ IC_VEX_L_W_OPSIZE, /* 5307 */ IC_VEX_L_W_OPSIZE, /* 5308 */ IC_VEX_L_W_OPSIZE, /* 5309 */ IC_VEX_L_W_OPSIZE, /* 5310 */ IC_VEX_L_W_OPSIZE, /* 5311 */ IC_VEX_L, /* 5312 */ IC_VEX_L, /* 5313 */ IC_VEX_L_XS, /* 5314 */ IC_VEX_L_XS, /* 5315 */ IC_VEX_L_XD, /* 5316 */ IC_VEX_L_XD, /* 5317 */ IC_VEX_L_XD, /* 5318 */ IC_VEX_L_XD, /* 5319 */ IC_VEX_L_W, /* 5320 */ IC_VEX_L_W, /* 5321 */ IC_VEX_L_W_XS, /* 5322 */ IC_VEX_L_W_XS, /* 5323 */ IC_VEX_L_W_XD, /* 5324 */ IC_VEX_L_W_XD, /* 5325 */ IC_VEX_L_W_XD, /* 5326 */ IC_VEX_L_W_XD, /* 5327 */ IC_VEX_L_OPSIZE, /* 5328 */ IC_VEX_L_OPSIZE, /* 5329 */ IC_VEX_L_OPSIZE, /* 5330 */ IC_VEX_L_OPSIZE, /* 5331 */ IC_VEX_L_OPSIZE, /* 5332 */ IC_VEX_L_OPSIZE, /* 5333 */ IC_VEX_L_OPSIZE, /* 5334 */ IC_VEX_L_OPSIZE, /* 5335 */ IC_VEX_L_W_OPSIZE, /* 5336 */ IC_VEX_L_W_OPSIZE, /* 5337 */ IC_VEX_L_W_OPSIZE, /* 5338 */ IC_VEX_L_W_OPSIZE, /* 5339 */ IC_VEX_L_W_OPSIZE, /* 5340 */ IC_VEX_L_W_OPSIZE, /* 5341 */ IC_VEX_L_W_OPSIZE, /* 5342 */ IC_VEX_L_W_OPSIZE, /* 5343 */ IC_VEX_L, /* 5344 */ IC_VEX_L, /* 5345 */ IC_VEX_L_XS, /* 5346 */ IC_VEX_L_XS, /* 5347 */ IC_VEX_L_XD, /* 5348 */ IC_VEX_L_XD, /* 5349 */ IC_VEX_L_XD, /* 5350 */ IC_VEX_L_XD, /* 5351 */ IC_VEX_L_W, /* 5352 */ IC_VEX_L_W, /* 5353 */ IC_VEX_L_W_XS, /* 5354 */ IC_VEX_L_W_XS, /* 5355 */ IC_VEX_L_W_XD, /* 5356 */ IC_VEX_L_W_XD, /* 5357 */ IC_VEX_L_W_XD, /* 5358 */ IC_VEX_L_W_XD, /* 5359 */ IC_VEX_L_OPSIZE, /* 5360 */ IC_VEX_L_OPSIZE, /* 5361 */ IC_VEX_L_OPSIZE, /* 5362 */ IC_VEX_L_OPSIZE, /* 5363 */ IC_VEX_L_OPSIZE, /* 5364 */ IC_VEX_L_OPSIZE, /* 5365 */ IC_VEX_L_OPSIZE, /* 5366 */ IC_VEX_L_OPSIZE, /* 5367 */ IC_VEX_L_W_OPSIZE, /* 5368 */ IC_VEX_L_W_OPSIZE, /* 5369 */ IC_VEX_L_W_OPSIZE, /* 5370 */ IC_VEX_L_W_OPSIZE, /* 5371 */ IC_VEX_L_W_OPSIZE, /* 5372 */ IC_VEX_L_W_OPSIZE, /* 5373 */ IC_VEX_L_W_OPSIZE, /* 5374 */ IC_VEX_L_W_OPSIZE, /* 5375 */ IC_EVEX_L2_KZ, /* 5376 */ IC_EVEX_L2_KZ, /* 5377 */ IC_EVEX_L2_XS_KZ, /* 5378 */ IC_EVEX_L2_XS_KZ, /* 5379 */ IC_EVEX_L2_XD_KZ, /* 5380 */ IC_EVEX_L2_XD_KZ, /* 5381 */ IC_EVEX_L2_XD_KZ, /* 5382 */ IC_EVEX_L2_XD_KZ, /* 5383 */ IC_EVEX_L2_W_KZ, /* 5384 */ IC_EVEX_L2_W_KZ, /* 5385 */ IC_EVEX_L2_W_XS_KZ, /* 5386 */ IC_EVEX_L2_W_XS_KZ, /* 5387 */ IC_EVEX_L2_W_XD_KZ, /* 5388 */ IC_EVEX_L2_W_XD_KZ, /* 5389 */ IC_EVEX_L2_W_XD_KZ, /* 5390 */ IC_EVEX_L2_W_XD_KZ, /* 5391 */ IC_EVEX_L2_OPSIZE_KZ, /* 5392 */ IC_EVEX_L2_OPSIZE_KZ, /* 5393 */ IC_EVEX_L2_OPSIZE_KZ, /* 5394 */ IC_EVEX_L2_OPSIZE_KZ, /* 5395 */ IC_EVEX_L2_OPSIZE_KZ, /* 5396 */ IC_EVEX_L2_OPSIZE_KZ, /* 5397 */ IC_EVEX_L2_OPSIZE_KZ, /* 5398 */ IC_EVEX_L2_OPSIZE_KZ, /* 5399 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5400 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5401 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5402 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5403 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5404 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5405 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5406 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5407 */ IC_EVEX_L2_KZ, /* 5408 */ IC_EVEX_L2_KZ, /* 5409 */ IC_EVEX_L2_XS_KZ, /* 5410 */ IC_EVEX_L2_XS_KZ, /* 5411 */ IC_EVEX_L2_XD_KZ, /* 5412 */ IC_EVEX_L2_XD_KZ, /* 5413 */ IC_EVEX_L2_XD_KZ, /* 5414 */ IC_EVEX_L2_XD_KZ, /* 5415 */ IC_EVEX_L2_W_KZ, /* 5416 */ IC_EVEX_L2_W_KZ, /* 5417 */ IC_EVEX_L2_W_XS_KZ, /* 5418 */ IC_EVEX_L2_W_XS_KZ, /* 5419 */ IC_EVEX_L2_W_XD_KZ, /* 5420 */ IC_EVEX_L2_W_XD_KZ, /* 5421 */ IC_EVEX_L2_W_XD_KZ, /* 5422 */ IC_EVEX_L2_W_XD_KZ, /* 5423 */ IC_EVEX_L2_OPSIZE_KZ, /* 5424 */ IC_EVEX_L2_OPSIZE_KZ, /* 5425 */ IC_EVEX_L2_OPSIZE_KZ, /* 5426 */ IC_EVEX_L2_OPSIZE_KZ, /* 5427 */ IC_EVEX_L2_OPSIZE_KZ, /* 5428 */ IC_EVEX_L2_OPSIZE_KZ, /* 5429 */ IC_EVEX_L2_OPSIZE_KZ, /* 5430 */ IC_EVEX_L2_OPSIZE_KZ, /* 5431 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5432 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5433 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5434 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5435 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5436 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5437 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5438 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5439 */ IC_EVEX_L2_KZ, /* 5440 */ IC_EVEX_L2_KZ, /* 5441 */ IC_EVEX_L2_XS_KZ, /* 5442 */ IC_EVEX_L2_XS_KZ, /* 5443 */ IC_EVEX_L2_XD_KZ, /* 5444 */ IC_EVEX_L2_XD_KZ, /* 5445 */ IC_EVEX_L2_XD_KZ, /* 5446 */ IC_EVEX_L2_XD_KZ, /* 5447 */ IC_EVEX_L2_W_KZ, /* 5448 */ IC_EVEX_L2_W_KZ, /* 5449 */ IC_EVEX_L2_W_XS_KZ, /* 5450 */ IC_EVEX_L2_W_XS_KZ, /* 5451 */ IC_EVEX_L2_W_XD_KZ, /* 5452 */ IC_EVEX_L2_W_XD_KZ, /* 5453 */ IC_EVEX_L2_W_XD_KZ, /* 5454 */ IC_EVEX_L2_W_XD_KZ, /* 5455 */ IC_EVEX_L2_OPSIZE_KZ, /* 5456 */ IC_EVEX_L2_OPSIZE_KZ, /* 5457 */ IC_EVEX_L2_OPSIZE_KZ, /* 5458 */ IC_EVEX_L2_OPSIZE_KZ, /* 5459 */ IC_EVEX_L2_OPSIZE_KZ, /* 5460 */ IC_EVEX_L2_OPSIZE_KZ, /* 5461 */ IC_EVEX_L2_OPSIZE_KZ, /* 5462 */ IC_EVEX_L2_OPSIZE_KZ, /* 5463 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5464 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5465 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5466 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5467 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5468 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5469 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5470 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5471 */ IC_EVEX_L2_KZ, /* 5472 */ IC_EVEX_L2_KZ, /* 5473 */ IC_EVEX_L2_XS_KZ, /* 5474 */ IC_EVEX_L2_XS_KZ, /* 5475 */ IC_EVEX_L2_XD_KZ, /* 5476 */ IC_EVEX_L2_XD_KZ, /* 5477 */ IC_EVEX_L2_XD_KZ, /* 5478 */ IC_EVEX_L2_XD_KZ, /* 5479 */ IC_EVEX_L2_W_KZ, /* 5480 */ IC_EVEX_L2_W_KZ, /* 5481 */ IC_EVEX_L2_W_XS_KZ, /* 5482 */ IC_EVEX_L2_W_XS_KZ, /* 5483 */ IC_EVEX_L2_W_XD_KZ, /* 5484 */ IC_EVEX_L2_W_XD_KZ, /* 5485 */ IC_EVEX_L2_W_XD_KZ, /* 5486 */ IC_EVEX_L2_W_XD_KZ, /* 5487 */ IC_EVEX_L2_OPSIZE_KZ, /* 5488 */ IC_EVEX_L2_OPSIZE_KZ, /* 5489 */ IC_EVEX_L2_OPSIZE_KZ, /* 5490 */ IC_EVEX_L2_OPSIZE_KZ, /* 5491 */ IC_EVEX_L2_OPSIZE_KZ, /* 5492 */ IC_EVEX_L2_OPSIZE_KZ, /* 5493 */ IC_EVEX_L2_OPSIZE_KZ, /* 5494 */ IC_EVEX_L2_OPSIZE_KZ, /* 5495 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5496 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5497 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5498 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5499 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5500 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5501 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5502 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5503 */ IC_EVEX_L2_KZ, /* 5504 */ IC_EVEX_L2_KZ, /* 5505 */ IC_EVEX_L2_XS_KZ, /* 5506 */ IC_EVEX_L2_XS_KZ, /* 5507 */ IC_EVEX_L2_XD_KZ, /* 5508 */ IC_EVEX_L2_XD_KZ, /* 5509 */ IC_EVEX_L2_XD_KZ, /* 5510 */ IC_EVEX_L2_XD_KZ, /* 5511 */ IC_EVEX_L2_W_KZ, /* 5512 */ IC_EVEX_L2_W_KZ, /* 5513 */ IC_EVEX_L2_W_XS_KZ, /* 5514 */ IC_EVEX_L2_W_XS_KZ, /* 5515 */ IC_EVEX_L2_W_XD_KZ, /* 5516 */ IC_EVEX_L2_W_XD_KZ, /* 5517 */ IC_EVEX_L2_W_XD_KZ, /* 5518 */ IC_EVEX_L2_W_XD_KZ, /* 5519 */ IC_EVEX_L2_OPSIZE_KZ, /* 5520 */ IC_EVEX_L2_OPSIZE_KZ, /* 5521 */ IC_EVEX_L2_OPSIZE_KZ, /* 5522 */ IC_EVEX_L2_OPSIZE_KZ, /* 5523 */ IC_EVEX_L2_OPSIZE_KZ, /* 5524 */ IC_EVEX_L2_OPSIZE_KZ, /* 5525 */ IC_EVEX_L2_OPSIZE_KZ, /* 5526 */ IC_EVEX_L2_OPSIZE_KZ, /* 5527 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5528 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5529 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5530 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5531 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5532 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5533 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5534 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5535 */ IC_EVEX_L2_KZ, /* 5536 */ IC_EVEX_L2_KZ, /* 5537 */ IC_EVEX_L2_XS_KZ, /* 5538 */ IC_EVEX_L2_XS_KZ, /* 5539 */ IC_EVEX_L2_XD_KZ, /* 5540 */ IC_EVEX_L2_XD_KZ, /* 5541 */ IC_EVEX_L2_XD_KZ, /* 5542 */ IC_EVEX_L2_XD_KZ, /* 5543 */ IC_EVEX_L2_W_KZ, /* 5544 */ IC_EVEX_L2_W_KZ, /* 5545 */ IC_EVEX_L2_W_XS_KZ, /* 5546 */ IC_EVEX_L2_W_XS_KZ, /* 5547 */ IC_EVEX_L2_W_XD_KZ, /* 5548 */ IC_EVEX_L2_W_XD_KZ, /* 5549 */ IC_EVEX_L2_W_XD_KZ, /* 5550 */ IC_EVEX_L2_W_XD_KZ, /* 5551 */ IC_EVEX_L2_OPSIZE_KZ, /* 5552 */ IC_EVEX_L2_OPSIZE_KZ, /* 5553 */ IC_EVEX_L2_OPSIZE_KZ, /* 5554 */ IC_EVEX_L2_OPSIZE_KZ, /* 5555 */ IC_EVEX_L2_OPSIZE_KZ, /* 5556 */ IC_EVEX_L2_OPSIZE_KZ, /* 5557 */ IC_EVEX_L2_OPSIZE_KZ, /* 5558 */ IC_EVEX_L2_OPSIZE_KZ, /* 5559 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5560 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5561 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5562 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5563 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5564 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5565 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5566 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5567 */ IC_EVEX_L2_KZ, /* 5568 */ IC_EVEX_L2_KZ, /* 5569 */ IC_EVEX_L2_XS_KZ, /* 5570 */ IC_EVEX_L2_XS_KZ, /* 5571 */ IC_EVEX_L2_XD_KZ, /* 5572 */ IC_EVEX_L2_XD_KZ, /* 5573 */ IC_EVEX_L2_XD_KZ, /* 5574 */ IC_EVEX_L2_XD_KZ, /* 5575 */ IC_EVEX_L2_W_KZ, /* 5576 */ IC_EVEX_L2_W_KZ, /* 5577 */ IC_EVEX_L2_W_XS_KZ, /* 5578 */ IC_EVEX_L2_W_XS_KZ, /* 5579 */ IC_EVEX_L2_W_XD_KZ, /* 5580 */ IC_EVEX_L2_W_XD_KZ, /* 5581 */ IC_EVEX_L2_W_XD_KZ, /* 5582 */ IC_EVEX_L2_W_XD_KZ, /* 5583 */ IC_EVEX_L2_OPSIZE_KZ, /* 5584 */ IC_EVEX_L2_OPSIZE_KZ, /* 5585 */ IC_EVEX_L2_OPSIZE_KZ, /* 5586 */ IC_EVEX_L2_OPSIZE_KZ, /* 5587 */ IC_EVEX_L2_OPSIZE_KZ, /* 5588 */ IC_EVEX_L2_OPSIZE_KZ, /* 5589 */ IC_EVEX_L2_OPSIZE_KZ, /* 5590 */ IC_EVEX_L2_OPSIZE_KZ, /* 5591 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5592 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5593 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5594 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5595 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5596 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5597 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5598 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5599 */ IC_EVEX_L2_KZ, /* 5600 */ IC_EVEX_L2_KZ, /* 5601 */ IC_EVEX_L2_XS_KZ, /* 5602 */ IC_EVEX_L2_XS_KZ, /* 5603 */ IC_EVEX_L2_XD_KZ, /* 5604 */ IC_EVEX_L2_XD_KZ, /* 5605 */ IC_EVEX_L2_XD_KZ, /* 5606 */ IC_EVEX_L2_XD_KZ, /* 5607 */ IC_EVEX_L2_W_KZ, /* 5608 */ IC_EVEX_L2_W_KZ, /* 5609 */ IC_EVEX_L2_W_XS_KZ, /* 5610 */ IC_EVEX_L2_W_XS_KZ, /* 5611 */ IC_EVEX_L2_W_XD_KZ, /* 5612 */ IC_EVEX_L2_W_XD_KZ, /* 5613 */ IC_EVEX_L2_W_XD_KZ, /* 5614 */ IC_EVEX_L2_W_XD_KZ, /* 5615 */ IC_EVEX_L2_OPSIZE_KZ, /* 5616 */ IC_EVEX_L2_OPSIZE_KZ, /* 5617 */ IC_EVEX_L2_OPSIZE_KZ, /* 5618 */ IC_EVEX_L2_OPSIZE_KZ, /* 5619 */ IC_EVEX_L2_OPSIZE_KZ, /* 5620 */ IC_EVEX_L2_OPSIZE_KZ, /* 5621 */ IC_EVEX_L2_OPSIZE_KZ, /* 5622 */ IC_EVEX_L2_OPSIZE_KZ, /* 5623 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5624 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5625 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5626 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5627 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5628 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5629 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5630 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5631 */ IC, /* 5632 */ IC_64BIT, /* 5633 */ IC_XS, /* 5634 */ IC_64BIT_XS, /* 5635 */ IC_XD, /* 5636 */ IC_64BIT_XD, /* 5637 */ IC_XS, /* 5638 */ IC_64BIT_XS, /* 5639 */ IC, /* 5640 */ IC_64BIT_REXW, /* 5641 */ IC_XS, /* 5642 */ IC_64BIT_REXW_XS, /* 5643 */ IC_XD, /* 5644 */ IC_64BIT_REXW_XD, /* 5645 */ IC_XS, /* 5646 */ IC_64BIT_REXW_XS, /* 5647 */ IC_OPSIZE, /* 5648 */ IC_64BIT_OPSIZE, /* 5649 */ IC_XS_OPSIZE, /* 5650 */ IC_64BIT_XS_OPSIZE, /* 5651 */ IC_XD_OPSIZE, /* 5652 */ IC_64BIT_XD_OPSIZE, /* 5653 */ IC_XS_OPSIZE, /* 5654 */ IC_64BIT_XD_OPSIZE, /* 5655 */ IC_OPSIZE, /* 5656 */ IC_64BIT_REXW_OPSIZE, /* 5657 */ IC_XS_OPSIZE, /* 5658 */ IC_64BIT_REXW_XS, /* 5659 */ IC_XD_OPSIZE, /* 5660 */ IC_64BIT_REXW_XD, /* 5661 */ IC_XS_OPSIZE, /* 5662 */ IC_64BIT_REXW_XS, /* 5663 */ IC_ADSIZE, /* 5664 */ IC_64BIT_ADSIZE, /* 5665 */ IC_XS_ADSIZE, /* 5666 */ IC_64BIT_XS_ADSIZE, /* 5667 */ IC_XD_ADSIZE, /* 5668 */ IC_64BIT_XD_ADSIZE, /* 5669 */ IC_XS_ADSIZE, /* 5670 */ IC_64BIT_XD_ADSIZE, /* 5671 */ IC_ADSIZE, /* 5672 */ IC_64BIT_REXW_ADSIZE, /* 5673 */ IC_XS_ADSIZE, /* 5674 */ IC_64BIT_REXW_XS, /* 5675 */ IC_XD_ADSIZE, /* 5676 */ IC_64BIT_REXW_XD, /* 5677 */ IC_XS_ADSIZE, /* 5678 */ IC_64BIT_REXW_XS, /* 5679 */ IC_OPSIZE_ADSIZE, /* 5680 */ IC_64BIT_OPSIZE_ADSIZE, /* 5681 */ IC_XS_OPSIZE, /* 5682 */ IC_64BIT_XS_OPSIZE, /* 5683 */ IC_XD_OPSIZE, /* 5684 */ IC_64BIT_XD_OPSIZE, /* 5685 */ IC_XS_OPSIZE, /* 5686 */ IC_64BIT_XD_OPSIZE, /* 5687 */ IC_OPSIZE_ADSIZE, /* 5688 */ IC_64BIT_REXW_OPSIZE, /* 5689 */ IC_XS_OPSIZE, /* 5690 */ IC_64BIT_REXW_XS, /* 5691 */ IC_XD_OPSIZE, /* 5692 */ IC_64BIT_REXW_XD, /* 5693 */ IC_XS_OPSIZE, /* 5694 */ IC_64BIT_REXW_XS, /* 5695 */ IC_VEX, /* 5696 */ IC_VEX, /* 5697 */ IC_VEX_XS, /* 5698 */ IC_VEX_XS, /* 5699 */ IC_VEX_XD, /* 5700 */ IC_VEX_XD, /* 5701 */ IC_VEX_XD, /* 5702 */ IC_VEX_XD, /* 5703 */ IC_VEX_W, /* 5704 */ IC_VEX_W, /* 5705 */ IC_VEX_W_XS, /* 5706 */ IC_VEX_W_XS, /* 5707 */ IC_VEX_W_XD, /* 5708 */ IC_VEX_W_XD, /* 5709 */ IC_VEX_W_XD, /* 5710 */ IC_VEX_W_XD, /* 5711 */ IC_VEX_OPSIZE, /* 5712 */ IC_VEX_OPSIZE, /* 5713 */ IC_VEX_OPSIZE, /* 5714 */ IC_VEX_OPSIZE, /* 5715 */ IC_VEX_OPSIZE, /* 5716 */ IC_VEX_OPSIZE, /* 5717 */ IC_VEX_OPSIZE, /* 5718 */ IC_VEX_OPSIZE, /* 5719 */ IC_VEX_W_OPSIZE, /* 5720 */ IC_VEX_W_OPSIZE, /* 5721 */ IC_VEX_W_OPSIZE, /* 5722 */ IC_VEX_W_OPSIZE, /* 5723 */ IC_VEX_W_OPSIZE, /* 5724 */ IC_VEX_W_OPSIZE, /* 5725 */ IC_VEX_W_OPSIZE, /* 5726 */ IC_VEX_W_OPSIZE, /* 5727 */ IC_VEX, /* 5728 */ IC_VEX, /* 5729 */ IC_VEX_XS, /* 5730 */ IC_VEX_XS, /* 5731 */ IC_VEX_XD, /* 5732 */ IC_VEX_XD, /* 5733 */ IC_VEX_XD, /* 5734 */ IC_VEX_XD, /* 5735 */ IC_VEX_W, /* 5736 */ IC_VEX_W, /* 5737 */ IC_VEX_W_XS, /* 5738 */ IC_VEX_W_XS, /* 5739 */ IC_VEX_W_XD, /* 5740 */ IC_VEX_W_XD, /* 5741 */ IC_VEX_W_XD, /* 5742 */ IC_VEX_W_XD, /* 5743 */ IC_VEX_OPSIZE, /* 5744 */ IC_VEX_OPSIZE, /* 5745 */ IC_VEX_OPSIZE, /* 5746 */ IC_VEX_OPSIZE, /* 5747 */ IC_VEX_OPSIZE, /* 5748 */ IC_VEX_OPSIZE, /* 5749 */ IC_VEX_OPSIZE, /* 5750 */ IC_VEX_OPSIZE, /* 5751 */ IC_VEX_W_OPSIZE, /* 5752 */ IC_VEX_W_OPSIZE, /* 5753 */ IC_VEX_W_OPSIZE, /* 5754 */ IC_VEX_W_OPSIZE, /* 5755 */ IC_VEX_W_OPSIZE, /* 5756 */ IC_VEX_W_OPSIZE, /* 5757 */ IC_VEX_W_OPSIZE, /* 5758 */ IC_VEX_W_OPSIZE, /* 5759 */ IC_VEX_L, /* 5760 */ IC_VEX_L, /* 5761 */ IC_VEX_L_XS, /* 5762 */ IC_VEX_L_XS, /* 5763 */ IC_VEX_L_XD, /* 5764 */ IC_VEX_L_XD, /* 5765 */ IC_VEX_L_XD, /* 5766 */ IC_VEX_L_XD, /* 5767 */ IC_VEX_L_W, /* 5768 */ IC_VEX_L_W, /* 5769 */ IC_VEX_L_W_XS, /* 5770 */ IC_VEX_L_W_XS, /* 5771 */ IC_VEX_L_W_XD, /* 5772 */ IC_VEX_L_W_XD, /* 5773 */ IC_VEX_L_W_XD, /* 5774 */ IC_VEX_L_W_XD, /* 5775 */ IC_VEX_L_OPSIZE, /* 5776 */ IC_VEX_L_OPSIZE, /* 5777 */ IC_VEX_L_OPSIZE, /* 5778 */ IC_VEX_L_OPSIZE, /* 5779 */ IC_VEX_L_OPSIZE, /* 5780 */ IC_VEX_L_OPSIZE, /* 5781 */ IC_VEX_L_OPSIZE, /* 5782 */ IC_VEX_L_OPSIZE, /* 5783 */ IC_VEX_L_W_OPSIZE, /* 5784 */ IC_VEX_L_W_OPSIZE, /* 5785 */ IC_VEX_L_W_OPSIZE, /* 5786 */ IC_VEX_L_W_OPSIZE, /* 5787 */ IC_VEX_L_W_OPSIZE, /* 5788 */ IC_VEX_L_W_OPSIZE, /* 5789 */ IC_VEX_L_W_OPSIZE, /* 5790 */ IC_VEX_L_W_OPSIZE, /* 5791 */ IC_VEX_L, /* 5792 */ IC_VEX_L, /* 5793 */ IC_VEX_L_XS, /* 5794 */ IC_VEX_L_XS, /* 5795 */ IC_VEX_L_XD, /* 5796 */ IC_VEX_L_XD, /* 5797 */ IC_VEX_L_XD, /* 5798 */ IC_VEX_L_XD, /* 5799 */ IC_VEX_L_W, /* 5800 */ IC_VEX_L_W, /* 5801 */ IC_VEX_L_W_XS, /* 5802 */ IC_VEX_L_W_XS, /* 5803 */ IC_VEX_L_W_XD, /* 5804 */ IC_VEX_L_W_XD, /* 5805 */ IC_VEX_L_W_XD, /* 5806 */ IC_VEX_L_W_XD, /* 5807 */ IC_VEX_L_OPSIZE, /* 5808 */ IC_VEX_L_OPSIZE, /* 5809 */ IC_VEX_L_OPSIZE, /* 5810 */ IC_VEX_L_OPSIZE, /* 5811 */ IC_VEX_L_OPSIZE, /* 5812 */ IC_VEX_L_OPSIZE, /* 5813 */ IC_VEX_L_OPSIZE, /* 5814 */ IC_VEX_L_OPSIZE, /* 5815 */ IC_VEX_L_W_OPSIZE, /* 5816 */ IC_VEX_L_W_OPSIZE, /* 5817 */ IC_VEX_L_W_OPSIZE, /* 5818 */ IC_VEX_L_W_OPSIZE, /* 5819 */ IC_VEX_L_W_OPSIZE, /* 5820 */ IC_VEX_L_W_OPSIZE, /* 5821 */ IC_VEX_L_W_OPSIZE, /* 5822 */ IC_VEX_L_W_OPSIZE, /* 5823 */ IC_VEX_L, /* 5824 */ IC_VEX_L, /* 5825 */ IC_VEX_L_XS, /* 5826 */ IC_VEX_L_XS, /* 5827 */ IC_VEX_L_XD, /* 5828 */ IC_VEX_L_XD, /* 5829 */ IC_VEX_L_XD, /* 5830 */ IC_VEX_L_XD, /* 5831 */ IC_VEX_L_W, /* 5832 */ IC_VEX_L_W, /* 5833 */ IC_VEX_L_W_XS, /* 5834 */ IC_VEX_L_W_XS, /* 5835 */ IC_VEX_L_W_XD, /* 5836 */ IC_VEX_L_W_XD, /* 5837 */ IC_VEX_L_W_XD, /* 5838 */ IC_VEX_L_W_XD, /* 5839 */ IC_VEX_L_OPSIZE, /* 5840 */ IC_VEX_L_OPSIZE, /* 5841 */ IC_VEX_L_OPSIZE, /* 5842 */ IC_VEX_L_OPSIZE, /* 5843 */ IC_VEX_L_OPSIZE, /* 5844 */ IC_VEX_L_OPSIZE, /* 5845 */ IC_VEX_L_OPSIZE, /* 5846 */ IC_VEX_L_OPSIZE, /* 5847 */ IC_VEX_L_W_OPSIZE, /* 5848 */ IC_VEX_L_W_OPSIZE, /* 5849 */ IC_VEX_L_W_OPSIZE, /* 5850 */ IC_VEX_L_W_OPSIZE, /* 5851 */ IC_VEX_L_W_OPSIZE, /* 5852 */ IC_VEX_L_W_OPSIZE, /* 5853 */ IC_VEX_L_W_OPSIZE, /* 5854 */ IC_VEX_L_W_OPSIZE, /* 5855 */ IC_VEX_L, /* 5856 */ IC_VEX_L, /* 5857 */ IC_VEX_L_XS, /* 5858 */ IC_VEX_L_XS, /* 5859 */ IC_VEX_L_XD, /* 5860 */ IC_VEX_L_XD, /* 5861 */ IC_VEX_L_XD, /* 5862 */ IC_VEX_L_XD, /* 5863 */ IC_VEX_L_W, /* 5864 */ IC_VEX_L_W, /* 5865 */ IC_VEX_L_W_XS, /* 5866 */ IC_VEX_L_W_XS, /* 5867 */ IC_VEX_L_W_XD, /* 5868 */ IC_VEX_L_W_XD, /* 5869 */ IC_VEX_L_W_XD, /* 5870 */ IC_VEX_L_W_XD, /* 5871 */ IC_VEX_L_OPSIZE, /* 5872 */ IC_VEX_L_OPSIZE, /* 5873 */ IC_VEX_L_OPSIZE, /* 5874 */ IC_VEX_L_OPSIZE, /* 5875 */ IC_VEX_L_OPSIZE, /* 5876 */ IC_VEX_L_OPSIZE, /* 5877 */ IC_VEX_L_OPSIZE, /* 5878 */ IC_VEX_L_OPSIZE, /* 5879 */ IC_VEX_L_W_OPSIZE, /* 5880 */ IC_VEX_L_W_OPSIZE, /* 5881 */ IC_VEX_L_W_OPSIZE, /* 5882 */ IC_VEX_L_W_OPSIZE, /* 5883 */ IC_VEX_L_W_OPSIZE, /* 5884 */ IC_VEX_L_W_OPSIZE, /* 5885 */ IC_VEX_L_W_OPSIZE, /* 5886 */ IC_VEX_L_W_OPSIZE, /* 5887 */ IC_EVEX_L2_KZ, /* 5888 */ IC_EVEX_L2_KZ, /* 5889 */ IC_EVEX_L2_XS_KZ, /* 5890 */ IC_EVEX_L2_XS_KZ, /* 5891 */ IC_EVEX_L2_XD_KZ, /* 5892 */ IC_EVEX_L2_XD_KZ, /* 5893 */ IC_EVEX_L2_XD_KZ, /* 5894 */ IC_EVEX_L2_XD_KZ, /* 5895 */ IC_EVEX_L2_W_KZ, /* 5896 */ IC_EVEX_L2_W_KZ, /* 5897 */ IC_EVEX_L2_W_XS_KZ, /* 5898 */ IC_EVEX_L2_W_XS_KZ, /* 5899 */ IC_EVEX_L2_W_XD_KZ, /* 5900 */ IC_EVEX_L2_W_XD_KZ, /* 5901 */ IC_EVEX_L2_W_XD_KZ, /* 5902 */ IC_EVEX_L2_W_XD_KZ, /* 5903 */ IC_EVEX_L2_OPSIZE_KZ, /* 5904 */ IC_EVEX_L2_OPSIZE_KZ, /* 5905 */ IC_EVEX_L2_OPSIZE_KZ, /* 5906 */ IC_EVEX_L2_OPSIZE_KZ, /* 5907 */ IC_EVEX_L2_OPSIZE_KZ, /* 5908 */ IC_EVEX_L2_OPSIZE_KZ, /* 5909 */ IC_EVEX_L2_OPSIZE_KZ, /* 5910 */ IC_EVEX_L2_OPSIZE_KZ, /* 5911 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5912 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5913 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5914 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5915 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5916 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5917 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5918 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5919 */ IC_EVEX_L2_KZ, /* 5920 */ IC_EVEX_L2_KZ, /* 5921 */ IC_EVEX_L2_XS_KZ, /* 5922 */ IC_EVEX_L2_XS_KZ, /* 5923 */ IC_EVEX_L2_XD_KZ, /* 5924 */ IC_EVEX_L2_XD_KZ, /* 5925 */ IC_EVEX_L2_XD_KZ, /* 5926 */ IC_EVEX_L2_XD_KZ, /* 5927 */ IC_EVEX_L2_W_KZ, /* 5928 */ IC_EVEX_L2_W_KZ, /* 5929 */ IC_EVEX_L2_W_XS_KZ, /* 5930 */ IC_EVEX_L2_W_XS_KZ, /* 5931 */ IC_EVEX_L2_W_XD_KZ, /* 5932 */ IC_EVEX_L2_W_XD_KZ, /* 5933 */ IC_EVEX_L2_W_XD_KZ, /* 5934 */ IC_EVEX_L2_W_XD_KZ, /* 5935 */ IC_EVEX_L2_OPSIZE_KZ, /* 5936 */ IC_EVEX_L2_OPSIZE_KZ, /* 5937 */ IC_EVEX_L2_OPSIZE_KZ, /* 5938 */ IC_EVEX_L2_OPSIZE_KZ, /* 5939 */ IC_EVEX_L2_OPSIZE_KZ, /* 5940 */ IC_EVEX_L2_OPSIZE_KZ, /* 5941 */ IC_EVEX_L2_OPSIZE_KZ, /* 5942 */ IC_EVEX_L2_OPSIZE_KZ, /* 5943 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5944 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5945 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5946 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5947 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5948 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5949 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5950 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5951 */ IC_EVEX_L2_KZ, /* 5952 */ IC_EVEX_L2_KZ, /* 5953 */ IC_EVEX_L2_XS_KZ, /* 5954 */ IC_EVEX_L2_XS_KZ, /* 5955 */ IC_EVEX_L2_XD_KZ, /* 5956 */ IC_EVEX_L2_XD_KZ, /* 5957 */ IC_EVEX_L2_XD_KZ, /* 5958 */ IC_EVEX_L2_XD_KZ, /* 5959 */ IC_EVEX_L2_W_KZ, /* 5960 */ IC_EVEX_L2_W_KZ, /* 5961 */ IC_EVEX_L2_W_XS_KZ, /* 5962 */ IC_EVEX_L2_W_XS_KZ, /* 5963 */ IC_EVEX_L2_W_XD_KZ, /* 5964 */ IC_EVEX_L2_W_XD_KZ, /* 5965 */ IC_EVEX_L2_W_XD_KZ, /* 5966 */ IC_EVEX_L2_W_XD_KZ, /* 5967 */ IC_EVEX_L2_OPSIZE_KZ, /* 5968 */ IC_EVEX_L2_OPSIZE_KZ, /* 5969 */ IC_EVEX_L2_OPSIZE_KZ, /* 5970 */ IC_EVEX_L2_OPSIZE_KZ, /* 5971 */ IC_EVEX_L2_OPSIZE_KZ, /* 5972 */ IC_EVEX_L2_OPSIZE_KZ, /* 5973 */ IC_EVEX_L2_OPSIZE_KZ, /* 5974 */ IC_EVEX_L2_OPSIZE_KZ, /* 5975 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5976 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5977 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5978 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5979 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5980 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5981 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5982 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 5983 */ IC_EVEX_L2_KZ, /* 5984 */ IC_EVEX_L2_KZ, /* 5985 */ IC_EVEX_L2_XS_KZ, /* 5986 */ IC_EVEX_L2_XS_KZ, /* 5987 */ IC_EVEX_L2_XD_KZ, /* 5988 */ IC_EVEX_L2_XD_KZ, /* 5989 */ IC_EVEX_L2_XD_KZ, /* 5990 */ IC_EVEX_L2_XD_KZ, /* 5991 */ IC_EVEX_L2_W_KZ, /* 5992 */ IC_EVEX_L2_W_KZ, /* 5993 */ IC_EVEX_L2_W_XS_KZ, /* 5994 */ IC_EVEX_L2_W_XS_KZ, /* 5995 */ IC_EVEX_L2_W_XD_KZ, /* 5996 */ IC_EVEX_L2_W_XD_KZ, /* 5997 */ IC_EVEX_L2_W_XD_KZ, /* 5998 */ IC_EVEX_L2_W_XD_KZ, /* 5999 */ IC_EVEX_L2_OPSIZE_KZ, /* 6000 */ IC_EVEX_L2_OPSIZE_KZ, /* 6001 */ IC_EVEX_L2_OPSIZE_KZ, /* 6002 */ IC_EVEX_L2_OPSIZE_KZ, /* 6003 */ IC_EVEX_L2_OPSIZE_KZ, /* 6004 */ IC_EVEX_L2_OPSIZE_KZ, /* 6005 */ IC_EVEX_L2_OPSIZE_KZ, /* 6006 */ IC_EVEX_L2_OPSIZE_KZ, /* 6007 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6008 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6009 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6010 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6011 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6012 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6013 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6014 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6015 */ IC_EVEX_L2_KZ, /* 6016 */ IC_EVEX_L2_KZ, /* 6017 */ IC_EVEX_L2_XS_KZ, /* 6018 */ IC_EVEX_L2_XS_KZ, /* 6019 */ IC_EVEX_L2_XD_KZ, /* 6020 */ IC_EVEX_L2_XD_KZ, /* 6021 */ IC_EVEX_L2_XD_KZ, /* 6022 */ IC_EVEX_L2_XD_KZ, /* 6023 */ IC_EVEX_L2_W_KZ, /* 6024 */ IC_EVEX_L2_W_KZ, /* 6025 */ IC_EVEX_L2_W_XS_KZ, /* 6026 */ IC_EVEX_L2_W_XS_KZ, /* 6027 */ IC_EVEX_L2_W_XD_KZ, /* 6028 */ IC_EVEX_L2_W_XD_KZ, /* 6029 */ IC_EVEX_L2_W_XD_KZ, /* 6030 */ IC_EVEX_L2_W_XD_KZ, /* 6031 */ IC_EVEX_L2_OPSIZE_KZ, /* 6032 */ IC_EVEX_L2_OPSIZE_KZ, /* 6033 */ IC_EVEX_L2_OPSIZE_KZ, /* 6034 */ IC_EVEX_L2_OPSIZE_KZ, /* 6035 */ IC_EVEX_L2_OPSIZE_KZ, /* 6036 */ IC_EVEX_L2_OPSIZE_KZ, /* 6037 */ IC_EVEX_L2_OPSIZE_KZ, /* 6038 */ IC_EVEX_L2_OPSIZE_KZ, /* 6039 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6040 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6041 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6042 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6043 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6044 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6045 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6046 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6047 */ IC_EVEX_L2_KZ, /* 6048 */ IC_EVEX_L2_KZ, /* 6049 */ IC_EVEX_L2_XS_KZ, /* 6050 */ IC_EVEX_L2_XS_KZ, /* 6051 */ IC_EVEX_L2_XD_KZ, /* 6052 */ IC_EVEX_L2_XD_KZ, /* 6053 */ IC_EVEX_L2_XD_KZ, /* 6054 */ IC_EVEX_L2_XD_KZ, /* 6055 */ IC_EVEX_L2_W_KZ, /* 6056 */ IC_EVEX_L2_W_KZ, /* 6057 */ IC_EVEX_L2_W_XS_KZ, /* 6058 */ IC_EVEX_L2_W_XS_KZ, /* 6059 */ IC_EVEX_L2_W_XD_KZ, /* 6060 */ IC_EVEX_L2_W_XD_KZ, /* 6061 */ IC_EVEX_L2_W_XD_KZ, /* 6062 */ IC_EVEX_L2_W_XD_KZ, /* 6063 */ IC_EVEX_L2_OPSIZE_KZ, /* 6064 */ IC_EVEX_L2_OPSIZE_KZ, /* 6065 */ IC_EVEX_L2_OPSIZE_KZ, /* 6066 */ IC_EVEX_L2_OPSIZE_KZ, /* 6067 */ IC_EVEX_L2_OPSIZE_KZ, /* 6068 */ IC_EVEX_L2_OPSIZE_KZ, /* 6069 */ IC_EVEX_L2_OPSIZE_KZ, /* 6070 */ IC_EVEX_L2_OPSIZE_KZ, /* 6071 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6072 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6073 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6074 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6075 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6076 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6077 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6078 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6079 */ IC_EVEX_L2_KZ, /* 6080 */ IC_EVEX_L2_KZ, /* 6081 */ IC_EVEX_L2_XS_KZ, /* 6082 */ IC_EVEX_L2_XS_KZ, /* 6083 */ IC_EVEX_L2_XD_KZ, /* 6084 */ IC_EVEX_L2_XD_KZ, /* 6085 */ IC_EVEX_L2_XD_KZ, /* 6086 */ IC_EVEX_L2_XD_KZ, /* 6087 */ IC_EVEX_L2_W_KZ, /* 6088 */ IC_EVEX_L2_W_KZ, /* 6089 */ IC_EVEX_L2_W_XS_KZ, /* 6090 */ IC_EVEX_L2_W_XS_KZ, /* 6091 */ IC_EVEX_L2_W_XD_KZ, /* 6092 */ IC_EVEX_L2_W_XD_KZ, /* 6093 */ IC_EVEX_L2_W_XD_KZ, /* 6094 */ IC_EVEX_L2_W_XD_KZ, /* 6095 */ IC_EVEX_L2_OPSIZE_KZ, /* 6096 */ IC_EVEX_L2_OPSIZE_KZ, /* 6097 */ IC_EVEX_L2_OPSIZE_KZ, /* 6098 */ IC_EVEX_L2_OPSIZE_KZ, /* 6099 */ IC_EVEX_L2_OPSIZE_KZ, /* 6100 */ IC_EVEX_L2_OPSIZE_KZ, /* 6101 */ IC_EVEX_L2_OPSIZE_KZ, /* 6102 */ IC_EVEX_L2_OPSIZE_KZ, /* 6103 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6104 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6105 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6106 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6107 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6108 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6109 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6110 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6111 */ IC_EVEX_L2_KZ, /* 6112 */ IC_EVEX_L2_KZ, /* 6113 */ IC_EVEX_L2_XS_KZ, /* 6114 */ IC_EVEX_L2_XS_KZ, /* 6115 */ IC_EVEX_L2_XD_KZ, /* 6116 */ IC_EVEX_L2_XD_KZ, /* 6117 */ IC_EVEX_L2_XD_KZ, /* 6118 */ IC_EVEX_L2_XD_KZ, /* 6119 */ IC_EVEX_L2_W_KZ, /* 6120 */ IC_EVEX_L2_W_KZ, /* 6121 */ IC_EVEX_L2_W_XS_KZ, /* 6122 */ IC_EVEX_L2_W_XS_KZ, /* 6123 */ IC_EVEX_L2_W_XD_KZ, /* 6124 */ IC_EVEX_L2_W_XD_KZ, /* 6125 */ IC_EVEX_L2_W_XD_KZ, /* 6126 */ IC_EVEX_L2_W_XD_KZ, /* 6127 */ IC_EVEX_L2_OPSIZE_KZ, /* 6128 */ IC_EVEX_L2_OPSIZE_KZ, /* 6129 */ IC_EVEX_L2_OPSIZE_KZ, /* 6130 */ IC_EVEX_L2_OPSIZE_KZ, /* 6131 */ IC_EVEX_L2_OPSIZE_KZ, /* 6132 */ IC_EVEX_L2_OPSIZE_KZ, /* 6133 */ IC_EVEX_L2_OPSIZE_KZ, /* 6134 */ IC_EVEX_L2_OPSIZE_KZ, /* 6135 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6136 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6137 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6138 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6139 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6140 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6141 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6142 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 6143 */ IC, /* 6144 */ IC_64BIT, /* 6145 */ IC_XS, /* 6146 */ IC_64BIT_XS, /* 6147 */ IC_XD, /* 6148 */ IC_64BIT_XD, /* 6149 */ IC_XS, /* 6150 */ IC_64BIT_XS, /* 6151 */ IC, /* 6152 */ IC_64BIT_REXW, /* 6153 */ IC_XS, /* 6154 */ IC_64BIT_REXW_XS, /* 6155 */ IC_XD, /* 6156 */ IC_64BIT_REXW_XD, /* 6157 */ IC_XS, /* 6158 */ IC_64BIT_REXW_XS, /* 6159 */ IC_OPSIZE, /* 6160 */ IC_64BIT_OPSIZE, /* 6161 */ IC_XS_OPSIZE, /* 6162 */ IC_64BIT_XS_OPSIZE, /* 6163 */ IC_XD_OPSIZE, /* 6164 */ IC_64BIT_XD_OPSIZE, /* 6165 */ IC_XS_OPSIZE, /* 6166 */ IC_64BIT_XD_OPSIZE, /* 6167 */ IC_OPSIZE, /* 6168 */ IC_64BIT_REXW_OPSIZE, /* 6169 */ IC_XS_OPSIZE, /* 6170 */ IC_64BIT_REXW_XS, /* 6171 */ IC_XD_OPSIZE, /* 6172 */ IC_64BIT_REXW_XD, /* 6173 */ IC_XS_OPSIZE, /* 6174 */ IC_64BIT_REXW_XS, /* 6175 */ IC_ADSIZE, /* 6176 */ IC_64BIT_ADSIZE, /* 6177 */ IC_XS_ADSIZE, /* 6178 */ IC_64BIT_XS_ADSIZE, /* 6179 */ IC_XD_ADSIZE, /* 6180 */ IC_64BIT_XD_ADSIZE, /* 6181 */ IC_XS_ADSIZE, /* 6182 */ IC_64BIT_XD_ADSIZE, /* 6183 */ IC_ADSIZE, /* 6184 */ IC_64BIT_REXW_ADSIZE, /* 6185 */ IC_XS_ADSIZE, /* 6186 */ IC_64BIT_REXW_XS, /* 6187 */ IC_XD_ADSIZE, /* 6188 */ IC_64BIT_REXW_XD, /* 6189 */ IC_XS_ADSIZE, /* 6190 */ IC_64BIT_REXW_XS, /* 6191 */ IC_OPSIZE_ADSIZE, /* 6192 */ IC_64BIT_OPSIZE_ADSIZE, /* 6193 */ IC_XS_OPSIZE, /* 6194 */ IC_64BIT_XS_OPSIZE, /* 6195 */ IC_XD_OPSIZE, /* 6196 */ IC_64BIT_XD_OPSIZE, /* 6197 */ IC_XS_OPSIZE, /* 6198 */ IC_64BIT_XD_OPSIZE, /* 6199 */ IC_OPSIZE_ADSIZE, /* 6200 */ IC_64BIT_REXW_OPSIZE, /* 6201 */ IC_XS_OPSIZE, /* 6202 */ IC_64BIT_REXW_XS, /* 6203 */ IC_XD_OPSIZE, /* 6204 */ IC_64BIT_REXW_XD, /* 6205 */ IC_XS_OPSIZE, /* 6206 */ IC_64BIT_REXW_XS, /* 6207 */ IC_VEX, /* 6208 */ IC_VEX, /* 6209 */ IC_VEX_XS, /* 6210 */ IC_VEX_XS, /* 6211 */ IC_VEX_XD, /* 6212 */ IC_VEX_XD, /* 6213 */ IC_VEX_XD, /* 6214 */ IC_VEX_XD, /* 6215 */ IC_VEX_W, /* 6216 */ IC_VEX_W, /* 6217 */ IC_VEX_W_XS, /* 6218 */ IC_VEX_W_XS, /* 6219 */ IC_VEX_W_XD, /* 6220 */ IC_VEX_W_XD, /* 6221 */ IC_VEX_W_XD, /* 6222 */ IC_VEX_W_XD, /* 6223 */ IC_VEX_OPSIZE, /* 6224 */ IC_VEX_OPSIZE, /* 6225 */ IC_VEX_OPSIZE, /* 6226 */ IC_VEX_OPSIZE, /* 6227 */ IC_VEX_OPSIZE, /* 6228 */ IC_VEX_OPSIZE, /* 6229 */ IC_VEX_OPSIZE, /* 6230 */ IC_VEX_OPSIZE, /* 6231 */ IC_VEX_W_OPSIZE, /* 6232 */ IC_VEX_W_OPSIZE, /* 6233 */ IC_VEX_W_OPSIZE, /* 6234 */ IC_VEX_W_OPSIZE, /* 6235 */ IC_VEX_W_OPSIZE, /* 6236 */ IC_VEX_W_OPSIZE, /* 6237 */ IC_VEX_W_OPSIZE, /* 6238 */ IC_VEX_W_OPSIZE, /* 6239 */ IC_VEX, /* 6240 */ IC_VEX, /* 6241 */ IC_VEX_XS, /* 6242 */ IC_VEX_XS, /* 6243 */ IC_VEX_XD, /* 6244 */ IC_VEX_XD, /* 6245 */ IC_VEX_XD, /* 6246 */ IC_VEX_XD, /* 6247 */ IC_VEX_W, /* 6248 */ IC_VEX_W, /* 6249 */ IC_VEX_W_XS, /* 6250 */ IC_VEX_W_XS, /* 6251 */ IC_VEX_W_XD, /* 6252 */ IC_VEX_W_XD, /* 6253 */ IC_VEX_W_XD, /* 6254 */ IC_VEX_W_XD, /* 6255 */ IC_VEX_OPSIZE, /* 6256 */ IC_VEX_OPSIZE, /* 6257 */ IC_VEX_OPSIZE, /* 6258 */ IC_VEX_OPSIZE, /* 6259 */ IC_VEX_OPSIZE, /* 6260 */ IC_VEX_OPSIZE, /* 6261 */ IC_VEX_OPSIZE, /* 6262 */ IC_VEX_OPSIZE, /* 6263 */ IC_VEX_W_OPSIZE, /* 6264 */ IC_VEX_W_OPSIZE, /* 6265 */ IC_VEX_W_OPSIZE, /* 6266 */ IC_VEX_W_OPSIZE, /* 6267 */ IC_VEX_W_OPSIZE, /* 6268 */ IC_VEX_W_OPSIZE, /* 6269 */ IC_VEX_W_OPSIZE, /* 6270 */ IC_VEX_W_OPSIZE, /* 6271 */ IC_VEX_L, /* 6272 */ IC_VEX_L, /* 6273 */ IC_VEX_L_XS, /* 6274 */ IC_VEX_L_XS, /* 6275 */ IC_VEX_L_XD, /* 6276 */ IC_VEX_L_XD, /* 6277 */ IC_VEX_L_XD, /* 6278 */ IC_VEX_L_XD, /* 6279 */ IC_VEX_L_W, /* 6280 */ IC_VEX_L_W, /* 6281 */ IC_VEX_L_W_XS, /* 6282 */ IC_VEX_L_W_XS, /* 6283 */ IC_VEX_L_W_XD, /* 6284 */ IC_VEX_L_W_XD, /* 6285 */ IC_VEX_L_W_XD, /* 6286 */ IC_VEX_L_W_XD, /* 6287 */ IC_VEX_L_OPSIZE, /* 6288 */ IC_VEX_L_OPSIZE, /* 6289 */ IC_VEX_L_OPSIZE, /* 6290 */ IC_VEX_L_OPSIZE, /* 6291 */ IC_VEX_L_OPSIZE, /* 6292 */ IC_VEX_L_OPSIZE, /* 6293 */ IC_VEX_L_OPSIZE, /* 6294 */ IC_VEX_L_OPSIZE, /* 6295 */ IC_VEX_L_W_OPSIZE, /* 6296 */ IC_VEX_L_W_OPSIZE, /* 6297 */ IC_VEX_L_W_OPSIZE, /* 6298 */ IC_VEX_L_W_OPSIZE, /* 6299 */ IC_VEX_L_W_OPSIZE, /* 6300 */ IC_VEX_L_W_OPSIZE, /* 6301 */ IC_VEX_L_W_OPSIZE, /* 6302 */ IC_VEX_L_W_OPSIZE, /* 6303 */ IC_VEX_L, /* 6304 */ IC_VEX_L, /* 6305 */ IC_VEX_L_XS, /* 6306 */ IC_VEX_L_XS, /* 6307 */ IC_VEX_L_XD, /* 6308 */ IC_VEX_L_XD, /* 6309 */ IC_VEX_L_XD, /* 6310 */ IC_VEX_L_XD, /* 6311 */ IC_VEX_L_W, /* 6312 */ IC_VEX_L_W, /* 6313 */ IC_VEX_L_W_XS, /* 6314 */ IC_VEX_L_W_XS, /* 6315 */ IC_VEX_L_W_XD, /* 6316 */ IC_VEX_L_W_XD, /* 6317 */ IC_VEX_L_W_XD, /* 6318 */ IC_VEX_L_W_XD, /* 6319 */ IC_VEX_L_OPSIZE, /* 6320 */ IC_VEX_L_OPSIZE, /* 6321 */ IC_VEX_L_OPSIZE, /* 6322 */ IC_VEX_L_OPSIZE, /* 6323 */ IC_VEX_L_OPSIZE, /* 6324 */ IC_VEX_L_OPSIZE, /* 6325 */ IC_VEX_L_OPSIZE, /* 6326 */ IC_VEX_L_OPSIZE, /* 6327 */ IC_VEX_L_W_OPSIZE, /* 6328 */ IC_VEX_L_W_OPSIZE, /* 6329 */ IC_VEX_L_W_OPSIZE, /* 6330 */ IC_VEX_L_W_OPSIZE, /* 6331 */ IC_VEX_L_W_OPSIZE, /* 6332 */ IC_VEX_L_W_OPSIZE, /* 6333 */ IC_VEX_L_W_OPSIZE, /* 6334 */ IC_VEX_L_W_OPSIZE, /* 6335 */ IC_VEX_L, /* 6336 */ IC_VEX_L, /* 6337 */ IC_VEX_L_XS, /* 6338 */ IC_VEX_L_XS, /* 6339 */ IC_VEX_L_XD, /* 6340 */ IC_VEX_L_XD, /* 6341 */ IC_VEX_L_XD, /* 6342 */ IC_VEX_L_XD, /* 6343 */ IC_VEX_L_W, /* 6344 */ IC_VEX_L_W, /* 6345 */ IC_VEX_L_W_XS, /* 6346 */ IC_VEX_L_W_XS, /* 6347 */ IC_VEX_L_W_XD, /* 6348 */ IC_VEX_L_W_XD, /* 6349 */ IC_VEX_L_W_XD, /* 6350 */ IC_VEX_L_W_XD, /* 6351 */ IC_VEX_L_OPSIZE, /* 6352 */ IC_VEX_L_OPSIZE, /* 6353 */ IC_VEX_L_OPSIZE, /* 6354 */ IC_VEX_L_OPSIZE, /* 6355 */ IC_VEX_L_OPSIZE, /* 6356 */ IC_VEX_L_OPSIZE, /* 6357 */ IC_VEX_L_OPSIZE, /* 6358 */ IC_VEX_L_OPSIZE, /* 6359 */ IC_VEX_L_W_OPSIZE, /* 6360 */ IC_VEX_L_W_OPSIZE, /* 6361 */ IC_VEX_L_W_OPSIZE, /* 6362 */ IC_VEX_L_W_OPSIZE, /* 6363 */ IC_VEX_L_W_OPSIZE, /* 6364 */ IC_VEX_L_W_OPSIZE, /* 6365 */ IC_VEX_L_W_OPSIZE, /* 6366 */ IC_VEX_L_W_OPSIZE, /* 6367 */ IC_VEX_L, /* 6368 */ IC_VEX_L, /* 6369 */ IC_VEX_L_XS, /* 6370 */ IC_VEX_L_XS, /* 6371 */ IC_VEX_L_XD, /* 6372 */ IC_VEX_L_XD, /* 6373 */ IC_VEX_L_XD, /* 6374 */ IC_VEX_L_XD, /* 6375 */ IC_VEX_L_W, /* 6376 */ IC_VEX_L_W, /* 6377 */ IC_VEX_L_W_XS, /* 6378 */ IC_VEX_L_W_XS, /* 6379 */ IC_VEX_L_W_XD, /* 6380 */ IC_VEX_L_W_XD, /* 6381 */ IC_VEX_L_W_XD, /* 6382 */ IC_VEX_L_W_XD, /* 6383 */ IC_VEX_L_OPSIZE, /* 6384 */ IC_VEX_L_OPSIZE, /* 6385 */ IC_VEX_L_OPSIZE, /* 6386 */ IC_VEX_L_OPSIZE, /* 6387 */ IC_VEX_L_OPSIZE, /* 6388 */ IC_VEX_L_OPSIZE, /* 6389 */ IC_VEX_L_OPSIZE, /* 6390 */ IC_VEX_L_OPSIZE, /* 6391 */ IC_VEX_L_W_OPSIZE, /* 6392 */ IC_VEX_L_W_OPSIZE, /* 6393 */ IC_VEX_L_W_OPSIZE, /* 6394 */ IC_VEX_L_W_OPSIZE, /* 6395 */ IC_VEX_L_W_OPSIZE, /* 6396 */ IC_VEX_L_W_OPSIZE, /* 6397 */ IC_VEX_L_W_OPSIZE, /* 6398 */ IC_VEX_L_W_OPSIZE, /* 6399 */ IC_EVEX_KZ, /* 6400 */ IC_EVEX_KZ, /* 6401 */ IC_EVEX_XS_KZ, /* 6402 */ IC_EVEX_XS_KZ, /* 6403 */ IC_EVEX_XD_KZ, /* 6404 */ IC_EVEX_XD_KZ, /* 6405 */ IC_EVEX_XD_KZ, /* 6406 */ IC_EVEX_XD_KZ, /* 6407 */ IC_EVEX_W_KZ, /* 6408 */ IC_EVEX_W_KZ, /* 6409 */ IC_EVEX_W_XS_KZ, /* 6410 */ IC_EVEX_W_XS_KZ, /* 6411 */ IC_EVEX_W_XD_KZ, /* 6412 */ IC_EVEX_W_XD_KZ, /* 6413 */ IC_EVEX_W_XD_KZ, /* 6414 */ IC_EVEX_W_XD_KZ, /* 6415 */ IC_EVEX_OPSIZE_KZ, /* 6416 */ IC_EVEX_OPSIZE_KZ, /* 6417 */ IC_EVEX_OPSIZE_KZ, /* 6418 */ IC_EVEX_OPSIZE_KZ, /* 6419 */ IC_EVEX_OPSIZE_KZ, /* 6420 */ IC_EVEX_OPSIZE_KZ, /* 6421 */ IC_EVEX_OPSIZE_KZ, /* 6422 */ IC_EVEX_OPSIZE_KZ, /* 6423 */ IC_EVEX_W_OPSIZE_KZ, /* 6424 */ IC_EVEX_W_OPSIZE_KZ, /* 6425 */ IC_EVEX_W_OPSIZE_KZ, /* 6426 */ IC_EVEX_W_OPSIZE_KZ, /* 6427 */ IC_EVEX_W_OPSIZE_KZ, /* 6428 */ IC_EVEX_W_OPSIZE_KZ, /* 6429 */ IC_EVEX_W_OPSIZE_KZ, /* 6430 */ IC_EVEX_W_OPSIZE_KZ, /* 6431 */ IC_EVEX_KZ, /* 6432 */ IC_EVEX_KZ, /* 6433 */ IC_EVEX_XS_KZ, /* 6434 */ IC_EVEX_XS_KZ, /* 6435 */ IC_EVEX_XD_KZ, /* 6436 */ IC_EVEX_XD_KZ, /* 6437 */ IC_EVEX_XD_KZ, /* 6438 */ IC_EVEX_XD_KZ, /* 6439 */ IC_EVEX_W_KZ, /* 6440 */ IC_EVEX_W_KZ, /* 6441 */ IC_EVEX_W_XS_KZ, /* 6442 */ IC_EVEX_W_XS_KZ, /* 6443 */ IC_EVEX_W_XD_KZ, /* 6444 */ IC_EVEX_W_XD_KZ, /* 6445 */ IC_EVEX_W_XD_KZ, /* 6446 */ IC_EVEX_W_XD_KZ, /* 6447 */ IC_EVEX_OPSIZE_KZ, /* 6448 */ IC_EVEX_OPSIZE_KZ, /* 6449 */ IC_EVEX_OPSIZE_KZ, /* 6450 */ IC_EVEX_OPSIZE_KZ, /* 6451 */ IC_EVEX_OPSIZE_KZ, /* 6452 */ IC_EVEX_OPSIZE_KZ, /* 6453 */ IC_EVEX_OPSIZE_KZ, /* 6454 */ IC_EVEX_OPSIZE_KZ, /* 6455 */ IC_EVEX_W_OPSIZE_KZ, /* 6456 */ IC_EVEX_W_OPSIZE_KZ, /* 6457 */ IC_EVEX_W_OPSIZE_KZ, /* 6458 */ IC_EVEX_W_OPSIZE_KZ, /* 6459 */ IC_EVEX_W_OPSIZE_KZ, /* 6460 */ IC_EVEX_W_OPSIZE_KZ, /* 6461 */ IC_EVEX_W_OPSIZE_KZ, /* 6462 */ IC_EVEX_W_OPSIZE_KZ, /* 6463 */ IC_EVEX_KZ, /* 6464 */ IC_EVEX_KZ, /* 6465 */ IC_EVEX_XS_KZ, /* 6466 */ IC_EVEX_XS_KZ, /* 6467 */ IC_EVEX_XD_KZ, /* 6468 */ IC_EVEX_XD_KZ, /* 6469 */ IC_EVEX_XD_KZ, /* 6470 */ IC_EVEX_XD_KZ, /* 6471 */ IC_EVEX_W_KZ, /* 6472 */ IC_EVEX_W_KZ, /* 6473 */ IC_EVEX_W_XS_KZ, /* 6474 */ IC_EVEX_W_XS_KZ, /* 6475 */ IC_EVEX_W_XD_KZ, /* 6476 */ IC_EVEX_W_XD_KZ, /* 6477 */ IC_EVEX_W_XD_KZ, /* 6478 */ IC_EVEX_W_XD_KZ, /* 6479 */ IC_EVEX_OPSIZE_KZ, /* 6480 */ IC_EVEX_OPSIZE_KZ, /* 6481 */ IC_EVEX_OPSIZE_KZ, /* 6482 */ IC_EVEX_OPSIZE_KZ, /* 6483 */ IC_EVEX_OPSIZE_KZ, /* 6484 */ IC_EVEX_OPSIZE_KZ, /* 6485 */ IC_EVEX_OPSIZE_KZ, /* 6486 */ IC_EVEX_OPSIZE_KZ, /* 6487 */ IC_EVEX_W_OPSIZE_KZ, /* 6488 */ IC_EVEX_W_OPSIZE_KZ, /* 6489 */ IC_EVEX_W_OPSIZE_KZ, /* 6490 */ IC_EVEX_W_OPSIZE_KZ, /* 6491 */ IC_EVEX_W_OPSIZE_KZ, /* 6492 */ IC_EVEX_W_OPSIZE_KZ, /* 6493 */ IC_EVEX_W_OPSIZE_KZ, /* 6494 */ IC_EVEX_W_OPSIZE_KZ, /* 6495 */ IC_EVEX_KZ, /* 6496 */ IC_EVEX_KZ, /* 6497 */ IC_EVEX_XS_KZ, /* 6498 */ IC_EVEX_XS_KZ, /* 6499 */ IC_EVEX_XD_KZ, /* 6500 */ IC_EVEX_XD_KZ, /* 6501 */ IC_EVEX_XD_KZ, /* 6502 */ IC_EVEX_XD_KZ, /* 6503 */ IC_EVEX_W_KZ, /* 6504 */ IC_EVEX_W_KZ, /* 6505 */ IC_EVEX_W_XS_KZ, /* 6506 */ IC_EVEX_W_XS_KZ, /* 6507 */ IC_EVEX_W_XD_KZ, /* 6508 */ IC_EVEX_W_XD_KZ, /* 6509 */ IC_EVEX_W_XD_KZ, /* 6510 */ IC_EVEX_W_XD_KZ, /* 6511 */ IC_EVEX_OPSIZE_KZ, /* 6512 */ IC_EVEX_OPSIZE_KZ, /* 6513 */ IC_EVEX_OPSIZE_KZ, /* 6514 */ IC_EVEX_OPSIZE_KZ, /* 6515 */ IC_EVEX_OPSIZE_KZ, /* 6516 */ IC_EVEX_OPSIZE_KZ, /* 6517 */ IC_EVEX_OPSIZE_KZ, /* 6518 */ IC_EVEX_OPSIZE_KZ, /* 6519 */ IC_EVEX_W_OPSIZE_KZ, /* 6520 */ IC_EVEX_W_OPSIZE_KZ, /* 6521 */ IC_EVEX_W_OPSIZE_KZ, /* 6522 */ IC_EVEX_W_OPSIZE_KZ, /* 6523 */ IC_EVEX_W_OPSIZE_KZ, /* 6524 */ IC_EVEX_W_OPSIZE_KZ, /* 6525 */ IC_EVEX_W_OPSIZE_KZ, /* 6526 */ IC_EVEX_W_OPSIZE_KZ, /* 6527 */ IC_EVEX_KZ, /* 6528 */ IC_EVEX_KZ, /* 6529 */ IC_EVEX_XS_KZ, /* 6530 */ IC_EVEX_XS_KZ, /* 6531 */ IC_EVEX_XD_KZ, /* 6532 */ IC_EVEX_XD_KZ, /* 6533 */ IC_EVEX_XD_KZ, /* 6534 */ IC_EVEX_XD_KZ, /* 6535 */ IC_EVEX_W_KZ, /* 6536 */ IC_EVEX_W_KZ, /* 6537 */ IC_EVEX_W_XS_KZ, /* 6538 */ IC_EVEX_W_XS_KZ, /* 6539 */ IC_EVEX_W_XD_KZ, /* 6540 */ IC_EVEX_W_XD_KZ, /* 6541 */ IC_EVEX_W_XD_KZ, /* 6542 */ IC_EVEX_W_XD_KZ, /* 6543 */ IC_EVEX_OPSIZE_KZ, /* 6544 */ IC_EVEX_OPSIZE_KZ, /* 6545 */ IC_EVEX_OPSIZE_KZ, /* 6546 */ IC_EVEX_OPSIZE_KZ, /* 6547 */ IC_EVEX_OPSIZE_KZ, /* 6548 */ IC_EVEX_OPSIZE_KZ, /* 6549 */ IC_EVEX_OPSIZE_KZ, /* 6550 */ IC_EVEX_OPSIZE_KZ, /* 6551 */ IC_EVEX_W_OPSIZE_KZ, /* 6552 */ IC_EVEX_W_OPSIZE_KZ, /* 6553 */ IC_EVEX_W_OPSIZE_KZ, /* 6554 */ IC_EVEX_W_OPSIZE_KZ, /* 6555 */ IC_EVEX_W_OPSIZE_KZ, /* 6556 */ IC_EVEX_W_OPSIZE_KZ, /* 6557 */ IC_EVEX_W_OPSIZE_KZ, /* 6558 */ IC_EVEX_W_OPSIZE_KZ, /* 6559 */ IC_EVEX_KZ, /* 6560 */ IC_EVEX_KZ, /* 6561 */ IC_EVEX_XS_KZ, /* 6562 */ IC_EVEX_XS_KZ, /* 6563 */ IC_EVEX_XD_KZ, /* 6564 */ IC_EVEX_XD_KZ, /* 6565 */ IC_EVEX_XD_KZ, /* 6566 */ IC_EVEX_XD_KZ, /* 6567 */ IC_EVEX_W_KZ, /* 6568 */ IC_EVEX_W_KZ, /* 6569 */ IC_EVEX_W_XS_KZ, /* 6570 */ IC_EVEX_W_XS_KZ, /* 6571 */ IC_EVEX_W_XD_KZ, /* 6572 */ IC_EVEX_W_XD_KZ, /* 6573 */ IC_EVEX_W_XD_KZ, /* 6574 */ IC_EVEX_W_XD_KZ, /* 6575 */ IC_EVEX_OPSIZE_KZ, /* 6576 */ IC_EVEX_OPSIZE_KZ, /* 6577 */ IC_EVEX_OPSIZE_KZ, /* 6578 */ IC_EVEX_OPSIZE_KZ, /* 6579 */ IC_EVEX_OPSIZE_KZ, /* 6580 */ IC_EVEX_OPSIZE_KZ, /* 6581 */ IC_EVEX_OPSIZE_KZ, /* 6582 */ IC_EVEX_OPSIZE_KZ, /* 6583 */ IC_EVEX_W_OPSIZE_KZ, /* 6584 */ IC_EVEX_W_OPSIZE_KZ, /* 6585 */ IC_EVEX_W_OPSIZE_KZ, /* 6586 */ IC_EVEX_W_OPSIZE_KZ, /* 6587 */ IC_EVEX_W_OPSIZE_KZ, /* 6588 */ IC_EVEX_W_OPSIZE_KZ, /* 6589 */ IC_EVEX_W_OPSIZE_KZ, /* 6590 */ IC_EVEX_W_OPSIZE_KZ, /* 6591 */ IC_EVEX_KZ, /* 6592 */ IC_EVEX_KZ, /* 6593 */ IC_EVEX_XS_KZ, /* 6594 */ IC_EVEX_XS_KZ, /* 6595 */ IC_EVEX_XD_KZ, /* 6596 */ IC_EVEX_XD_KZ, /* 6597 */ IC_EVEX_XD_KZ, /* 6598 */ IC_EVEX_XD_KZ, /* 6599 */ IC_EVEX_W_KZ, /* 6600 */ IC_EVEX_W_KZ, /* 6601 */ IC_EVEX_W_XS_KZ, /* 6602 */ IC_EVEX_W_XS_KZ, /* 6603 */ IC_EVEX_W_XD_KZ, /* 6604 */ IC_EVEX_W_XD_KZ, /* 6605 */ IC_EVEX_W_XD_KZ, /* 6606 */ IC_EVEX_W_XD_KZ, /* 6607 */ IC_EVEX_OPSIZE_KZ, /* 6608 */ IC_EVEX_OPSIZE_KZ, /* 6609 */ IC_EVEX_OPSIZE_KZ, /* 6610 */ IC_EVEX_OPSIZE_KZ, /* 6611 */ IC_EVEX_OPSIZE_KZ, /* 6612 */ IC_EVEX_OPSIZE_KZ, /* 6613 */ IC_EVEX_OPSIZE_KZ, /* 6614 */ IC_EVEX_OPSIZE_KZ, /* 6615 */ IC_EVEX_W_OPSIZE_KZ, /* 6616 */ IC_EVEX_W_OPSIZE_KZ, /* 6617 */ IC_EVEX_W_OPSIZE_KZ, /* 6618 */ IC_EVEX_W_OPSIZE_KZ, /* 6619 */ IC_EVEX_W_OPSIZE_KZ, /* 6620 */ IC_EVEX_W_OPSIZE_KZ, /* 6621 */ IC_EVEX_W_OPSIZE_KZ, /* 6622 */ IC_EVEX_W_OPSIZE_KZ, /* 6623 */ IC_EVEX_KZ, /* 6624 */ IC_EVEX_KZ, /* 6625 */ IC_EVEX_XS_KZ, /* 6626 */ IC_EVEX_XS_KZ, /* 6627 */ IC_EVEX_XD_KZ, /* 6628 */ IC_EVEX_XD_KZ, /* 6629 */ IC_EVEX_XD_KZ, /* 6630 */ IC_EVEX_XD_KZ, /* 6631 */ IC_EVEX_W_KZ, /* 6632 */ IC_EVEX_W_KZ, /* 6633 */ IC_EVEX_W_XS_KZ, /* 6634 */ IC_EVEX_W_XS_KZ, /* 6635 */ IC_EVEX_W_XD_KZ, /* 6636 */ IC_EVEX_W_XD_KZ, /* 6637 */ IC_EVEX_W_XD_KZ, /* 6638 */ IC_EVEX_W_XD_KZ, /* 6639 */ IC_EVEX_OPSIZE_KZ, /* 6640 */ IC_EVEX_OPSIZE_KZ, /* 6641 */ IC_EVEX_OPSIZE_KZ, /* 6642 */ IC_EVEX_OPSIZE_KZ, /* 6643 */ IC_EVEX_OPSIZE_KZ, /* 6644 */ IC_EVEX_OPSIZE_KZ, /* 6645 */ IC_EVEX_OPSIZE_KZ, /* 6646 */ IC_EVEX_OPSIZE_KZ, /* 6647 */ IC_EVEX_W_OPSIZE_KZ, /* 6648 */ IC_EVEX_W_OPSIZE_KZ, /* 6649 */ IC_EVEX_W_OPSIZE_KZ, /* 6650 */ IC_EVEX_W_OPSIZE_KZ, /* 6651 */ IC_EVEX_W_OPSIZE_KZ, /* 6652 */ IC_EVEX_W_OPSIZE_KZ, /* 6653 */ IC_EVEX_W_OPSIZE_KZ, /* 6654 */ IC_EVEX_W_OPSIZE_KZ, /* 6655 */ IC, /* 6656 */ IC_64BIT, /* 6657 */ IC_XS, /* 6658 */ IC_64BIT_XS, /* 6659 */ IC_XD, /* 6660 */ IC_64BIT_XD, /* 6661 */ IC_XS, /* 6662 */ IC_64BIT_XS, /* 6663 */ IC, /* 6664 */ IC_64BIT_REXW, /* 6665 */ IC_XS, /* 6666 */ IC_64BIT_REXW_XS, /* 6667 */ IC_XD, /* 6668 */ IC_64BIT_REXW_XD, /* 6669 */ IC_XS, /* 6670 */ IC_64BIT_REXW_XS, /* 6671 */ IC_OPSIZE, /* 6672 */ IC_64BIT_OPSIZE, /* 6673 */ IC_XS_OPSIZE, /* 6674 */ IC_64BIT_XS_OPSIZE, /* 6675 */ IC_XD_OPSIZE, /* 6676 */ IC_64BIT_XD_OPSIZE, /* 6677 */ IC_XS_OPSIZE, /* 6678 */ IC_64BIT_XD_OPSIZE, /* 6679 */ IC_OPSIZE, /* 6680 */ IC_64BIT_REXW_OPSIZE, /* 6681 */ IC_XS_OPSIZE, /* 6682 */ IC_64BIT_REXW_XS, /* 6683 */ IC_XD_OPSIZE, /* 6684 */ IC_64BIT_REXW_XD, /* 6685 */ IC_XS_OPSIZE, /* 6686 */ IC_64BIT_REXW_XS, /* 6687 */ IC_ADSIZE, /* 6688 */ IC_64BIT_ADSIZE, /* 6689 */ IC_XS_ADSIZE, /* 6690 */ IC_64BIT_XS_ADSIZE, /* 6691 */ IC_XD_ADSIZE, /* 6692 */ IC_64BIT_XD_ADSIZE, /* 6693 */ IC_XS_ADSIZE, /* 6694 */ IC_64BIT_XD_ADSIZE, /* 6695 */ IC_ADSIZE, /* 6696 */ IC_64BIT_REXW_ADSIZE, /* 6697 */ IC_XS_ADSIZE, /* 6698 */ IC_64BIT_REXW_XS, /* 6699 */ IC_XD_ADSIZE, /* 6700 */ IC_64BIT_REXW_XD, /* 6701 */ IC_XS_ADSIZE, /* 6702 */ IC_64BIT_REXW_XS, /* 6703 */ IC_OPSIZE_ADSIZE, /* 6704 */ IC_64BIT_OPSIZE_ADSIZE, /* 6705 */ IC_XS_OPSIZE, /* 6706 */ IC_64BIT_XS_OPSIZE, /* 6707 */ IC_XD_OPSIZE, /* 6708 */ IC_64BIT_XD_OPSIZE, /* 6709 */ IC_XS_OPSIZE, /* 6710 */ IC_64BIT_XD_OPSIZE, /* 6711 */ IC_OPSIZE_ADSIZE, /* 6712 */ IC_64BIT_REXW_OPSIZE, /* 6713 */ IC_XS_OPSIZE, /* 6714 */ IC_64BIT_REXW_XS, /* 6715 */ IC_XD_OPSIZE, /* 6716 */ IC_64BIT_REXW_XD, /* 6717 */ IC_XS_OPSIZE, /* 6718 */ IC_64BIT_REXW_XS, /* 6719 */ IC_VEX, /* 6720 */ IC_VEX, /* 6721 */ IC_VEX_XS, /* 6722 */ IC_VEX_XS, /* 6723 */ IC_VEX_XD, /* 6724 */ IC_VEX_XD, /* 6725 */ IC_VEX_XD, /* 6726 */ IC_VEX_XD, /* 6727 */ IC_VEX_W, /* 6728 */ IC_VEX_W, /* 6729 */ IC_VEX_W_XS, /* 6730 */ IC_VEX_W_XS, /* 6731 */ IC_VEX_W_XD, /* 6732 */ IC_VEX_W_XD, /* 6733 */ IC_VEX_W_XD, /* 6734 */ IC_VEX_W_XD, /* 6735 */ IC_VEX_OPSIZE, /* 6736 */ IC_VEX_OPSIZE, /* 6737 */ IC_VEX_OPSIZE, /* 6738 */ IC_VEX_OPSIZE, /* 6739 */ IC_VEX_OPSIZE, /* 6740 */ IC_VEX_OPSIZE, /* 6741 */ IC_VEX_OPSIZE, /* 6742 */ IC_VEX_OPSIZE, /* 6743 */ IC_VEX_W_OPSIZE, /* 6744 */ IC_VEX_W_OPSIZE, /* 6745 */ IC_VEX_W_OPSIZE, /* 6746 */ IC_VEX_W_OPSIZE, /* 6747 */ IC_VEX_W_OPSIZE, /* 6748 */ IC_VEX_W_OPSIZE, /* 6749 */ IC_VEX_W_OPSIZE, /* 6750 */ IC_VEX_W_OPSIZE, /* 6751 */ IC_VEX, /* 6752 */ IC_VEX, /* 6753 */ IC_VEX_XS, /* 6754 */ IC_VEX_XS, /* 6755 */ IC_VEX_XD, /* 6756 */ IC_VEX_XD, /* 6757 */ IC_VEX_XD, /* 6758 */ IC_VEX_XD, /* 6759 */ IC_VEX_W, /* 6760 */ IC_VEX_W, /* 6761 */ IC_VEX_W_XS, /* 6762 */ IC_VEX_W_XS, /* 6763 */ IC_VEX_W_XD, /* 6764 */ IC_VEX_W_XD, /* 6765 */ IC_VEX_W_XD, /* 6766 */ IC_VEX_W_XD, /* 6767 */ IC_VEX_OPSIZE, /* 6768 */ IC_VEX_OPSIZE, /* 6769 */ IC_VEX_OPSIZE, /* 6770 */ IC_VEX_OPSIZE, /* 6771 */ IC_VEX_OPSIZE, /* 6772 */ IC_VEX_OPSIZE, /* 6773 */ IC_VEX_OPSIZE, /* 6774 */ IC_VEX_OPSIZE, /* 6775 */ IC_VEX_W_OPSIZE, /* 6776 */ IC_VEX_W_OPSIZE, /* 6777 */ IC_VEX_W_OPSIZE, /* 6778 */ IC_VEX_W_OPSIZE, /* 6779 */ IC_VEX_W_OPSIZE, /* 6780 */ IC_VEX_W_OPSIZE, /* 6781 */ IC_VEX_W_OPSIZE, /* 6782 */ IC_VEX_W_OPSIZE, /* 6783 */ IC_VEX_L, /* 6784 */ IC_VEX_L, /* 6785 */ IC_VEX_L_XS, /* 6786 */ IC_VEX_L_XS, /* 6787 */ IC_VEX_L_XD, /* 6788 */ IC_VEX_L_XD, /* 6789 */ IC_VEX_L_XD, /* 6790 */ IC_VEX_L_XD, /* 6791 */ IC_VEX_L_W, /* 6792 */ IC_VEX_L_W, /* 6793 */ IC_VEX_L_W_XS, /* 6794 */ IC_VEX_L_W_XS, /* 6795 */ IC_VEX_L_W_XD, /* 6796 */ IC_VEX_L_W_XD, /* 6797 */ IC_VEX_L_W_XD, /* 6798 */ IC_VEX_L_W_XD, /* 6799 */ IC_VEX_L_OPSIZE, /* 6800 */ IC_VEX_L_OPSIZE, /* 6801 */ IC_VEX_L_OPSIZE, /* 6802 */ IC_VEX_L_OPSIZE, /* 6803 */ IC_VEX_L_OPSIZE, /* 6804 */ IC_VEX_L_OPSIZE, /* 6805 */ IC_VEX_L_OPSIZE, /* 6806 */ IC_VEX_L_OPSIZE, /* 6807 */ IC_VEX_L_W_OPSIZE, /* 6808 */ IC_VEX_L_W_OPSIZE, /* 6809 */ IC_VEX_L_W_OPSIZE, /* 6810 */ IC_VEX_L_W_OPSIZE, /* 6811 */ IC_VEX_L_W_OPSIZE, /* 6812 */ IC_VEX_L_W_OPSIZE, /* 6813 */ IC_VEX_L_W_OPSIZE, /* 6814 */ IC_VEX_L_W_OPSIZE, /* 6815 */ IC_VEX_L, /* 6816 */ IC_VEX_L, /* 6817 */ IC_VEX_L_XS, /* 6818 */ IC_VEX_L_XS, /* 6819 */ IC_VEX_L_XD, /* 6820 */ IC_VEX_L_XD, /* 6821 */ IC_VEX_L_XD, /* 6822 */ IC_VEX_L_XD, /* 6823 */ IC_VEX_L_W, /* 6824 */ IC_VEX_L_W, /* 6825 */ IC_VEX_L_W_XS, /* 6826 */ IC_VEX_L_W_XS, /* 6827 */ IC_VEX_L_W_XD, /* 6828 */ IC_VEX_L_W_XD, /* 6829 */ IC_VEX_L_W_XD, /* 6830 */ IC_VEX_L_W_XD, /* 6831 */ IC_VEX_L_OPSIZE, /* 6832 */ IC_VEX_L_OPSIZE, /* 6833 */ IC_VEX_L_OPSIZE, /* 6834 */ IC_VEX_L_OPSIZE, /* 6835 */ IC_VEX_L_OPSIZE, /* 6836 */ IC_VEX_L_OPSIZE, /* 6837 */ IC_VEX_L_OPSIZE, /* 6838 */ IC_VEX_L_OPSIZE, /* 6839 */ IC_VEX_L_W_OPSIZE, /* 6840 */ IC_VEX_L_W_OPSIZE, /* 6841 */ IC_VEX_L_W_OPSIZE, /* 6842 */ IC_VEX_L_W_OPSIZE, /* 6843 */ IC_VEX_L_W_OPSIZE, /* 6844 */ IC_VEX_L_W_OPSIZE, /* 6845 */ IC_VEX_L_W_OPSIZE, /* 6846 */ IC_VEX_L_W_OPSIZE, /* 6847 */ IC_VEX_L, /* 6848 */ IC_VEX_L, /* 6849 */ IC_VEX_L_XS, /* 6850 */ IC_VEX_L_XS, /* 6851 */ IC_VEX_L_XD, /* 6852 */ IC_VEX_L_XD, /* 6853 */ IC_VEX_L_XD, /* 6854 */ IC_VEX_L_XD, /* 6855 */ IC_VEX_L_W, /* 6856 */ IC_VEX_L_W, /* 6857 */ IC_VEX_L_W_XS, /* 6858 */ IC_VEX_L_W_XS, /* 6859 */ IC_VEX_L_W_XD, /* 6860 */ IC_VEX_L_W_XD, /* 6861 */ IC_VEX_L_W_XD, /* 6862 */ IC_VEX_L_W_XD, /* 6863 */ IC_VEX_L_OPSIZE, /* 6864 */ IC_VEX_L_OPSIZE, /* 6865 */ IC_VEX_L_OPSIZE, /* 6866 */ IC_VEX_L_OPSIZE, /* 6867 */ IC_VEX_L_OPSIZE, /* 6868 */ IC_VEX_L_OPSIZE, /* 6869 */ IC_VEX_L_OPSIZE, /* 6870 */ IC_VEX_L_OPSIZE, /* 6871 */ IC_VEX_L_W_OPSIZE, /* 6872 */ IC_VEX_L_W_OPSIZE, /* 6873 */ IC_VEX_L_W_OPSIZE, /* 6874 */ IC_VEX_L_W_OPSIZE, /* 6875 */ IC_VEX_L_W_OPSIZE, /* 6876 */ IC_VEX_L_W_OPSIZE, /* 6877 */ IC_VEX_L_W_OPSIZE, /* 6878 */ IC_VEX_L_W_OPSIZE, /* 6879 */ IC_VEX_L, /* 6880 */ IC_VEX_L, /* 6881 */ IC_VEX_L_XS, /* 6882 */ IC_VEX_L_XS, /* 6883 */ IC_VEX_L_XD, /* 6884 */ IC_VEX_L_XD, /* 6885 */ IC_VEX_L_XD, /* 6886 */ IC_VEX_L_XD, /* 6887 */ IC_VEX_L_W, /* 6888 */ IC_VEX_L_W, /* 6889 */ IC_VEX_L_W_XS, /* 6890 */ IC_VEX_L_W_XS, /* 6891 */ IC_VEX_L_W_XD, /* 6892 */ IC_VEX_L_W_XD, /* 6893 */ IC_VEX_L_W_XD, /* 6894 */ IC_VEX_L_W_XD, /* 6895 */ IC_VEX_L_OPSIZE, /* 6896 */ IC_VEX_L_OPSIZE, /* 6897 */ IC_VEX_L_OPSIZE, /* 6898 */ IC_VEX_L_OPSIZE, /* 6899 */ IC_VEX_L_OPSIZE, /* 6900 */ IC_VEX_L_OPSIZE, /* 6901 */ IC_VEX_L_OPSIZE, /* 6902 */ IC_VEX_L_OPSIZE, /* 6903 */ IC_VEX_L_W_OPSIZE, /* 6904 */ IC_VEX_L_W_OPSIZE, /* 6905 */ IC_VEX_L_W_OPSIZE, /* 6906 */ IC_VEX_L_W_OPSIZE, /* 6907 */ IC_VEX_L_W_OPSIZE, /* 6908 */ IC_VEX_L_W_OPSIZE, /* 6909 */ IC_VEX_L_W_OPSIZE, /* 6910 */ IC_VEX_L_W_OPSIZE, /* 6911 */ IC_EVEX_L_KZ, /* 6912 */ IC_EVEX_L_KZ, /* 6913 */ IC_EVEX_L_XS_KZ, /* 6914 */ IC_EVEX_L_XS_KZ, /* 6915 */ IC_EVEX_L_XD_KZ, /* 6916 */ IC_EVEX_L_XD_KZ, /* 6917 */ IC_EVEX_L_XD_KZ, /* 6918 */ IC_EVEX_L_XD_KZ, /* 6919 */ IC_EVEX_L_W_KZ, /* 6920 */ IC_EVEX_L_W_KZ, /* 6921 */ IC_EVEX_L_W_XS_KZ, /* 6922 */ IC_EVEX_L_W_XS_KZ, /* 6923 */ IC_EVEX_L_W_XD_KZ, /* 6924 */ IC_EVEX_L_W_XD_KZ, /* 6925 */ IC_EVEX_L_W_XD_KZ, /* 6926 */ IC_EVEX_L_W_XD_KZ, /* 6927 */ IC_EVEX_L_OPSIZE_KZ, /* 6928 */ IC_EVEX_L_OPSIZE_KZ, /* 6929 */ IC_EVEX_L_OPSIZE_KZ, /* 6930 */ IC_EVEX_L_OPSIZE_KZ, /* 6931 */ IC_EVEX_L_OPSIZE_KZ, /* 6932 */ IC_EVEX_L_OPSIZE_KZ, /* 6933 */ IC_EVEX_L_OPSIZE_KZ, /* 6934 */ IC_EVEX_L_OPSIZE_KZ, /* 6935 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6936 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6937 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6938 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6939 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6940 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6941 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6942 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6943 */ IC_EVEX_L_KZ, /* 6944 */ IC_EVEX_L_KZ, /* 6945 */ IC_EVEX_L_XS_KZ, /* 6946 */ IC_EVEX_L_XS_KZ, /* 6947 */ IC_EVEX_L_XD_KZ, /* 6948 */ IC_EVEX_L_XD_KZ, /* 6949 */ IC_EVEX_L_XD_KZ, /* 6950 */ IC_EVEX_L_XD_KZ, /* 6951 */ IC_EVEX_L_W_KZ, /* 6952 */ IC_EVEX_L_W_KZ, /* 6953 */ IC_EVEX_L_W_XS_KZ, /* 6954 */ IC_EVEX_L_W_XS_KZ, /* 6955 */ IC_EVEX_L_W_XD_KZ, /* 6956 */ IC_EVEX_L_W_XD_KZ, /* 6957 */ IC_EVEX_L_W_XD_KZ, /* 6958 */ IC_EVEX_L_W_XD_KZ, /* 6959 */ IC_EVEX_L_OPSIZE_KZ, /* 6960 */ IC_EVEX_L_OPSIZE_KZ, /* 6961 */ IC_EVEX_L_OPSIZE_KZ, /* 6962 */ IC_EVEX_L_OPSIZE_KZ, /* 6963 */ IC_EVEX_L_OPSIZE_KZ, /* 6964 */ IC_EVEX_L_OPSIZE_KZ, /* 6965 */ IC_EVEX_L_OPSIZE_KZ, /* 6966 */ IC_EVEX_L_OPSIZE_KZ, /* 6967 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6968 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6969 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6970 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6971 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6972 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6973 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6974 */ IC_EVEX_L_W_OPSIZE_KZ, /* 6975 */ IC_EVEX_L_KZ, /* 6976 */ IC_EVEX_L_KZ, /* 6977 */ IC_EVEX_L_XS_KZ, /* 6978 */ IC_EVEX_L_XS_KZ, /* 6979 */ IC_EVEX_L_XD_KZ, /* 6980 */ IC_EVEX_L_XD_KZ, /* 6981 */ IC_EVEX_L_XD_KZ, /* 6982 */ IC_EVEX_L_XD_KZ, /* 6983 */ IC_EVEX_L_W_KZ, /* 6984 */ IC_EVEX_L_W_KZ, /* 6985 */ IC_EVEX_L_W_XS_KZ, /* 6986 */ IC_EVEX_L_W_XS_KZ, /* 6987 */ IC_EVEX_L_W_XD_KZ, /* 6988 */ IC_EVEX_L_W_XD_KZ, /* 6989 */ IC_EVEX_L_W_XD_KZ, /* 6990 */ IC_EVEX_L_W_XD_KZ, /* 6991 */ IC_EVEX_L_OPSIZE_KZ, /* 6992 */ IC_EVEX_L_OPSIZE_KZ, /* 6993 */ IC_EVEX_L_OPSIZE_KZ, /* 6994 */ IC_EVEX_L_OPSIZE_KZ, /* 6995 */ IC_EVEX_L_OPSIZE_KZ, /* 6996 */ IC_EVEX_L_OPSIZE_KZ, /* 6997 */ IC_EVEX_L_OPSIZE_KZ, /* 6998 */ IC_EVEX_L_OPSIZE_KZ, /* 6999 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7000 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7001 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7002 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7003 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7004 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7005 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7006 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7007 */ IC_EVEX_L_KZ, /* 7008 */ IC_EVEX_L_KZ, /* 7009 */ IC_EVEX_L_XS_KZ, /* 7010 */ IC_EVEX_L_XS_KZ, /* 7011 */ IC_EVEX_L_XD_KZ, /* 7012 */ IC_EVEX_L_XD_KZ, /* 7013 */ IC_EVEX_L_XD_KZ, /* 7014 */ IC_EVEX_L_XD_KZ, /* 7015 */ IC_EVEX_L_W_KZ, /* 7016 */ IC_EVEX_L_W_KZ, /* 7017 */ IC_EVEX_L_W_XS_KZ, /* 7018 */ IC_EVEX_L_W_XS_KZ, /* 7019 */ IC_EVEX_L_W_XD_KZ, /* 7020 */ IC_EVEX_L_W_XD_KZ, /* 7021 */ IC_EVEX_L_W_XD_KZ, /* 7022 */ IC_EVEX_L_W_XD_KZ, /* 7023 */ IC_EVEX_L_OPSIZE_KZ, /* 7024 */ IC_EVEX_L_OPSIZE_KZ, /* 7025 */ IC_EVEX_L_OPSIZE_KZ, /* 7026 */ IC_EVEX_L_OPSIZE_KZ, /* 7027 */ IC_EVEX_L_OPSIZE_KZ, /* 7028 */ IC_EVEX_L_OPSIZE_KZ, /* 7029 */ IC_EVEX_L_OPSIZE_KZ, /* 7030 */ IC_EVEX_L_OPSIZE_KZ, /* 7031 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7032 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7033 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7034 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7035 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7036 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7037 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7038 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7039 */ IC_EVEX_L_KZ, /* 7040 */ IC_EVEX_L_KZ, /* 7041 */ IC_EVEX_L_XS_KZ, /* 7042 */ IC_EVEX_L_XS_KZ, /* 7043 */ IC_EVEX_L_XD_KZ, /* 7044 */ IC_EVEX_L_XD_KZ, /* 7045 */ IC_EVEX_L_XD_KZ, /* 7046 */ IC_EVEX_L_XD_KZ, /* 7047 */ IC_EVEX_L_W_KZ, /* 7048 */ IC_EVEX_L_W_KZ, /* 7049 */ IC_EVEX_L_W_XS_KZ, /* 7050 */ IC_EVEX_L_W_XS_KZ, /* 7051 */ IC_EVEX_L_W_XD_KZ, /* 7052 */ IC_EVEX_L_W_XD_KZ, /* 7053 */ IC_EVEX_L_W_XD_KZ, /* 7054 */ IC_EVEX_L_W_XD_KZ, /* 7055 */ IC_EVEX_L_OPSIZE_KZ, /* 7056 */ IC_EVEX_L_OPSIZE_KZ, /* 7057 */ IC_EVEX_L_OPSIZE_KZ, /* 7058 */ IC_EVEX_L_OPSIZE_KZ, /* 7059 */ IC_EVEX_L_OPSIZE_KZ, /* 7060 */ IC_EVEX_L_OPSIZE_KZ, /* 7061 */ IC_EVEX_L_OPSIZE_KZ, /* 7062 */ IC_EVEX_L_OPSIZE_KZ, /* 7063 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7064 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7065 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7066 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7067 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7068 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7069 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7070 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7071 */ IC_EVEX_L_KZ, /* 7072 */ IC_EVEX_L_KZ, /* 7073 */ IC_EVEX_L_XS_KZ, /* 7074 */ IC_EVEX_L_XS_KZ, /* 7075 */ IC_EVEX_L_XD_KZ, /* 7076 */ IC_EVEX_L_XD_KZ, /* 7077 */ IC_EVEX_L_XD_KZ, /* 7078 */ IC_EVEX_L_XD_KZ, /* 7079 */ IC_EVEX_L_W_KZ, /* 7080 */ IC_EVEX_L_W_KZ, /* 7081 */ IC_EVEX_L_W_XS_KZ, /* 7082 */ IC_EVEX_L_W_XS_KZ, /* 7083 */ IC_EVEX_L_W_XD_KZ, /* 7084 */ IC_EVEX_L_W_XD_KZ, /* 7085 */ IC_EVEX_L_W_XD_KZ, /* 7086 */ IC_EVEX_L_W_XD_KZ, /* 7087 */ IC_EVEX_L_OPSIZE_KZ, /* 7088 */ IC_EVEX_L_OPSIZE_KZ, /* 7089 */ IC_EVEX_L_OPSIZE_KZ, /* 7090 */ IC_EVEX_L_OPSIZE_KZ, /* 7091 */ IC_EVEX_L_OPSIZE_KZ, /* 7092 */ IC_EVEX_L_OPSIZE_KZ, /* 7093 */ IC_EVEX_L_OPSIZE_KZ, /* 7094 */ IC_EVEX_L_OPSIZE_KZ, /* 7095 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7096 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7097 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7098 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7099 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7100 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7101 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7102 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7103 */ IC_EVEX_L_KZ, /* 7104 */ IC_EVEX_L_KZ, /* 7105 */ IC_EVEX_L_XS_KZ, /* 7106 */ IC_EVEX_L_XS_KZ, /* 7107 */ IC_EVEX_L_XD_KZ, /* 7108 */ IC_EVEX_L_XD_KZ, /* 7109 */ IC_EVEX_L_XD_KZ, /* 7110 */ IC_EVEX_L_XD_KZ, /* 7111 */ IC_EVEX_L_W_KZ, /* 7112 */ IC_EVEX_L_W_KZ, /* 7113 */ IC_EVEX_L_W_XS_KZ, /* 7114 */ IC_EVEX_L_W_XS_KZ, /* 7115 */ IC_EVEX_L_W_XD_KZ, /* 7116 */ IC_EVEX_L_W_XD_KZ, /* 7117 */ IC_EVEX_L_W_XD_KZ, /* 7118 */ IC_EVEX_L_W_XD_KZ, /* 7119 */ IC_EVEX_L_OPSIZE_KZ, /* 7120 */ IC_EVEX_L_OPSIZE_KZ, /* 7121 */ IC_EVEX_L_OPSIZE_KZ, /* 7122 */ IC_EVEX_L_OPSIZE_KZ, /* 7123 */ IC_EVEX_L_OPSIZE_KZ, /* 7124 */ IC_EVEX_L_OPSIZE_KZ, /* 7125 */ IC_EVEX_L_OPSIZE_KZ, /* 7126 */ IC_EVEX_L_OPSIZE_KZ, /* 7127 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7128 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7129 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7130 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7131 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7132 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7133 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7134 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7135 */ IC_EVEX_L_KZ, /* 7136 */ IC_EVEX_L_KZ, /* 7137 */ IC_EVEX_L_XS_KZ, /* 7138 */ IC_EVEX_L_XS_KZ, /* 7139 */ IC_EVEX_L_XD_KZ, /* 7140 */ IC_EVEX_L_XD_KZ, /* 7141 */ IC_EVEX_L_XD_KZ, /* 7142 */ IC_EVEX_L_XD_KZ, /* 7143 */ IC_EVEX_L_W_KZ, /* 7144 */ IC_EVEX_L_W_KZ, /* 7145 */ IC_EVEX_L_W_XS_KZ, /* 7146 */ IC_EVEX_L_W_XS_KZ, /* 7147 */ IC_EVEX_L_W_XD_KZ, /* 7148 */ IC_EVEX_L_W_XD_KZ, /* 7149 */ IC_EVEX_L_W_XD_KZ, /* 7150 */ IC_EVEX_L_W_XD_KZ, /* 7151 */ IC_EVEX_L_OPSIZE_KZ, /* 7152 */ IC_EVEX_L_OPSIZE_KZ, /* 7153 */ IC_EVEX_L_OPSIZE_KZ, /* 7154 */ IC_EVEX_L_OPSIZE_KZ, /* 7155 */ IC_EVEX_L_OPSIZE_KZ, /* 7156 */ IC_EVEX_L_OPSIZE_KZ, /* 7157 */ IC_EVEX_L_OPSIZE_KZ, /* 7158 */ IC_EVEX_L_OPSIZE_KZ, /* 7159 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7160 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7161 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7162 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7163 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7164 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7165 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7166 */ IC_EVEX_L_W_OPSIZE_KZ, /* 7167 */ IC, /* 7168 */ IC_64BIT, /* 7169 */ IC_XS, /* 7170 */ IC_64BIT_XS, /* 7171 */ IC_XD, /* 7172 */ IC_64BIT_XD, /* 7173 */ IC_XS, /* 7174 */ IC_64BIT_XS, /* 7175 */ IC, /* 7176 */ IC_64BIT_REXW, /* 7177 */ IC_XS, /* 7178 */ IC_64BIT_REXW_XS, /* 7179 */ IC_XD, /* 7180 */ IC_64BIT_REXW_XD, /* 7181 */ IC_XS, /* 7182 */ IC_64BIT_REXW_XS, /* 7183 */ IC_OPSIZE, /* 7184 */ IC_64BIT_OPSIZE, /* 7185 */ IC_XS_OPSIZE, /* 7186 */ IC_64BIT_XS_OPSIZE, /* 7187 */ IC_XD_OPSIZE, /* 7188 */ IC_64BIT_XD_OPSIZE, /* 7189 */ IC_XS_OPSIZE, /* 7190 */ IC_64BIT_XD_OPSIZE, /* 7191 */ IC_OPSIZE, /* 7192 */ IC_64BIT_REXW_OPSIZE, /* 7193 */ IC_XS_OPSIZE, /* 7194 */ IC_64BIT_REXW_XS, /* 7195 */ IC_XD_OPSIZE, /* 7196 */ IC_64BIT_REXW_XD, /* 7197 */ IC_XS_OPSIZE, /* 7198 */ IC_64BIT_REXW_XS, /* 7199 */ IC_ADSIZE, /* 7200 */ IC_64BIT_ADSIZE, /* 7201 */ IC_XS_ADSIZE, /* 7202 */ IC_64BIT_XS_ADSIZE, /* 7203 */ IC_XD_ADSIZE, /* 7204 */ IC_64BIT_XD_ADSIZE, /* 7205 */ IC_XS_ADSIZE, /* 7206 */ IC_64BIT_XD_ADSIZE, /* 7207 */ IC_ADSIZE, /* 7208 */ IC_64BIT_REXW_ADSIZE, /* 7209 */ IC_XS_ADSIZE, /* 7210 */ IC_64BIT_REXW_XS, /* 7211 */ IC_XD_ADSIZE, /* 7212 */ IC_64BIT_REXW_XD, /* 7213 */ IC_XS_ADSIZE, /* 7214 */ IC_64BIT_REXW_XS, /* 7215 */ IC_OPSIZE_ADSIZE, /* 7216 */ IC_64BIT_OPSIZE_ADSIZE, /* 7217 */ IC_XS_OPSIZE, /* 7218 */ IC_64BIT_XS_OPSIZE, /* 7219 */ IC_XD_OPSIZE, /* 7220 */ IC_64BIT_XD_OPSIZE, /* 7221 */ IC_XS_OPSIZE, /* 7222 */ IC_64BIT_XD_OPSIZE, /* 7223 */ IC_OPSIZE_ADSIZE, /* 7224 */ IC_64BIT_REXW_OPSIZE, /* 7225 */ IC_XS_OPSIZE, /* 7226 */ IC_64BIT_REXW_XS, /* 7227 */ IC_XD_OPSIZE, /* 7228 */ IC_64BIT_REXW_XD, /* 7229 */ IC_XS_OPSIZE, /* 7230 */ IC_64BIT_REXW_XS, /* 7231 */ IC_VEX, /* 7232 */ IC_VEX, /* 7233 */ IC_VEX_XS, /* 7234 */ IC_VEX_XS, /* 7235 */ IC_VEX_XD, /* 7236 */ IC_VEX_XD, /* 7237 */ IC_VEX_XD, /* 7238 */ IC_VEX_XD, /* 7239 */ IC_VEX_W, /* 7240 */ IC_VEX_W, /* 7241 */ IC_VEX_W_XS, /* 7242 */ IC_VEX_W_XS, /* 7243 */ IC_VEX_W_XD, /* 7244 */ IC_VEX_W_XD, /* 7245 */ IC_VEX_W_XD, /* 7246 */ IC_VEX_W_XD, /* 7247 */ IC_VEX_OPSIZE, /* 7248 */ IC_VEX_OPSIZE, /* 7249 */ IC_VEX_OPSIZE, /* 7250 */ IC_VEX_OPSIZE, /* 7251 */ IC_VEX_OPSIZE, /* 7252 */ IC_VEX_OPSIZE, /* 7253 */ IC_VEX_OPSIZE, /* 7254 */ IC_VEX_OPSIZE, /* 7255 */ IC_VEX_W_OPSIZE, /* 7256 */ IC_VEX_W_OPSIZE, /* 7257 */ IC_VEX_W_OPSIZE, /* 7258 */ IC_VEX_W_OPSIZE, /* 7259 */ IC_VEX_W_OPSIZE, /* 7260 */ IC_VEX_W_OPSIZE, /* 7261 */ IC_VEX_W_OPSIZE, /* 7262 */ IC_VEX_W_OPSIZE, /* 7263 */ IC_VEX, /* 7264 */ IC_VEX, /* 7265 */ IC_VEX_XS, /* 7266 */ IC_VEX_XS, /* 7267 */ IC_VEX_XD, /* 7268 */ IC_VEX_XD, /* 7269 */ IC_VEX_XD, /* 7270 */ IC_VEX_XD, /* 7271 */ IC_VEX_W, /* 7272 */ IC_VEX_W, /* 7273 */ IC_VEX_W_XS, /* 7274 */ IC_VEX_W_XS, /* 7275 */ IC_VEX_W_XD, /* 7276 */ IC_VEX_W_XD, /* 7277 */ IC_VEX_W_XD, /* 7278 */ IC_VEX_W_XD, /* 7279 */ IC_VEX_OPSIZE, /* 7280 */ IC_VEX_OPSIZE, /* 7281 */ IC_VEX_OPSIZE, /* 7282 */ IC_VEX_OPSIZE, /* 7283 */ IC_VEX_OPSIZE, /* 7284 */ IC_VEX_OPSIZE, /* 7285 */ IC_VEX_OPSIZE, /* 7286 */ IC_VEX_OPSIZE, /* 7287 */ IC_VEX_W_OPSIZE, /* 7288 */ IC_VEX_W_OPSIZE, /* 7289 */ IC_VEX_W_OPSIZE, /* 7290 */ IC_VEX_W_OPSIZE, /* 7291 */ IC_VEX_W_OPSIZE, /* 7292 */ IC_VEX_W_OPSIZE, /* 7293 */ IC_VEX_W_OPSIZE, /* 7294 */ IC_VEX_W_OPSIZE, /* 7295 */ IC_VEX_L, /* 7296 */ IC_VEX_L, /* 7297 */ IC_VEX_L_XS, /* 7298 */ IC_VEX_L_XS, /* 7299 */ IC_VEX_L_XD, /* 7300 */ IC_VEX_L_XD, /* 7301 */ IC_VEX_L_XD, /* 7302 */ IC_VEX_L_XD, /* 7303 */ IC_VEX_L_W, /* 7304 */ IC_VEX_L_W, /* 7305 */ IC_VEX_L_W_XS, /* 7306 */ IC_VEX_L_W_XS, /* 7307 */ IC_VEX_L_W_XD, /* 7308 */ IC_VEX_L_W_XD, /* 7309 */ IC_VEX_L_W_XD, /* 7310 */ IC_VEX_L_W_XD, /* 7311 */ IC_VEX_L_OPSIZE, /* 7312 */ IC_VEX_L_OPSIZE, /* 7313 */ IC_VEX_L_OPSIZE, /* 7314 */ IC_VEX_L_OPSIZE, /* 7315 */ IC_VEX_L_OPSIZE, /* 7316 */ IC_VEX_L_OPSIZE, /* 7317 */ IC_VEX_L_OPSIZE, /* 7318 */ IC_VEX_L_OPSIZE, /* 7319 */ IC_VEX_L_W_OPSIZE, /* 7320 */ IC_VEX_L_W_OPSIZE, /* 7321 */ IC_VEX_L_W_OPSIZE, /* 7322 */ IC_VEX_L_W_OPSIZE, /* 7323 */ IC_VEX_L_W_OPSIZE, /* 7324 */ IC_VEX_L_W_OPSIZE, /* 7325 */ IC_VEX_L_W_OPSIZE, /* 7326 */ IC_VEX_L_W_OPSIZE, /* 7327 */ IC_VEX_L, /* 7328 */ IC_VEX_L, /* 7329 */ IC_VEX_L_XS, /* 7330 */ IC_VEX_L_XS, /* 7331 */ IC_VEX_L_XD, /* 7332 */ IC_VEX_L_XD, /* 7333 */ IC_VEX_L_XD, /* 7334 */ IC_VEX_L_XD, /* 7335 */ IC_VEX_L_W, /* 7336 */ IC_VEX_L_W, /* 7337 */ IC_VEX_L_W_XS, /* 7338 */ IC_VEX_L_W_XS, /* 7339 */ IC_VEX_L_W_XD, /* 7340 */ IC_VEX_L_W_XD, /* 7341 */ IC_VEX_L_W_XD, /* 7342 */ IC_VEX_L_W_XD, /* 7343 */ IC_VEX_L_OPSIZE, /* 7344 */ IC_VEX_L_OPSIZE, /* 7345 */ IC_VEX_L_OPSIZE, /* 7346 */ IC_VEX_L_OPSIZE, /* 7347 */ IC_VEX_L_OPSIZE, /* 7348 */ IC_VEX_L_OPSIZE, /* 7349 */ IC_VEX_L_OPSIZE, /* 7350 */ IC_VEX_L_OPSIZE, /* 7351 */ IC_VEX_L_W_OPSIZE, /* 7352 */ IC_VEX_L_W_OPSIZE, /* 7353 */ IC_VEX_L_W_OPSIZE, /* 7354 */ IC_VEX_L_W_OPSIZE, /* 7355 */ IC_VEX_L_W_OPSIZE, /* 7356 */ IC_VEX_L_W_OPSIZE, /* 7357 */ IC_VEX_L_W_OPSIZE, /* 7358 */ IC_VEX_L_W_OPSIZE, /* 7359 */ IC_VEX_L, /* 7360 */ IC_VEX_L, /* 7361 */ IC_VEX_L_XS, /* 7362 */ IC_VEX_L_XS, /* 7363 */ IC_VEX_L_XD, /* 7364 */ IC_VEX_L_XD, /* 7365 */ IC_VEX_L_XD, /* 7366 */ IC_VEX_L_XD, /* 7367 */ IC_VEX_L_W, /* 7368 */ IC_VEX_L_W, /* 7369 */ IC_VEX_L_W_XS, /* 7370 */ IC_VEX_L_W_XS, /* 7371 */ IC_VEX_L_W_XD, /* 7372 */ IC_VEX_L_W_XD, /* 7373 */ IC_VEX_L_W_XD, /* 7374 */ IC_VEX_L_W_XD, /* 7375 */ IC_VEX_L_OPSIZE, /* 7376 */ IC_VEX_L_OPSIZE, /* 7377 */ IC_VEX_L_OPSIZE, /* 7378 */ IC_VEX_L_OPSIZE, /* 7379 */ IC_VEX_L_OPSIZE, /* 7380 */ IC_VEX_L_OPSIZE, /* 7381 */ IC_VEX_L_OPSIZE, /* 7382 */ IC_VEX_L_OPSIZE, /* 7383 */ IC_VEX_L_W_OPSIZE, /* 7384 */ IC_VEX_L_W_OPSIZE, /* 7385 */ IC_VEX_L_W_OPSIZE, /* 7386 */ IC_VEX_L_W_OPSIZE, /* 7387 */ IC_VEX_L_W_OPSIZE, /* 7388 */ IC_VEX_L_W_OPSIZE, /* 7389 */ IC_VEX_L_W_OPSIZE, /* 7390 */ IC_VEX_L_W_OPSIZE, /* 7391 */ IC_VEX_L, /* 7392 */ IC_VEX_L, /* 7393 */ IC_VEX_L_XS, /* 7394 */ IC_VEX_L_XS, /* 7395 */ IC_VEX_L_XD, /* 7396 */ IC_VEX_L_XD, /* 7397 */ IC_VEX_L_XD, /* 7398 */ IC_VEX_L_XD, /* 7399 */ IC_VEX_L_W, /* 7400 */ IC_VEX_L_W, /* 7401 */ IC_VEX_L_W_XS, /* 7402 */ IC_VEX_L_W_XS, /* 7403 */ IC_VEX_L_W_XD, /* 7404 */ IC_VEX_L_W_XD, /* 7405 */ IC_VEX_L_W_XD, /* 7406 */ IC_VEX_L_W_XD, /* 7407 */ IC_VEX_L_OPSIZE, /* 7408 */ IC_VEX_L_OPSIZE, /* 7409 */ IC_VEX_L_OPSIZE, /* 7410 */ IC_VEX_L_OPSIZE, /* 7411 */ IC_VEX_L_OPSIZE, /* 7412 */ IC_VEX_L_OPSIZE, /* 7413 */ IC_VEX_L_OPSIZE, /* 7414 */ IC_VEX_L_OPSIZE, /* 7415 */ IC_VEX_L_W_OPSIZE, /* 7416 */ IC_VEX_L_W_OPSIZE, /* 7417 */ IC_VEX_L_W_OPSIZE, /* 7418 */ IC_VEX_L_W_OPSIZE, /* 7419 */ IC_VEX_L_W_OPSIZE, /* 7420 */ IC_VEX_L_W_OPSIZE, /* 7421 */ IC_VEX_L_W_OPSIZE, /* 7422 */ IC_VEX_L_W_OPSIZE, /* 7423 */ IC_EVEX_L2_KZ, /* 7424 */ IC_EVEX_L2_KZ, /* 7425 */ IC_EVEX_L2_XS_KZ, /* 7426 */ IC_EVEX_L2_XS_KZ, /* 7427 */ IC_EVEX_L2_XD_KZ, /* 7428 */ IC_EVEX_L2_XD_KZ, /* 7429 */ IC_EVEX_L2_XD_KZ, /* 7430 */ IC_EVEX_L2_XD_KZ, /* 7431 */ IC_EVEX_L2_W_KZ, /* 7432 */ IC_EVEX_L2_W_KZ, /* 7433 */ IC_EVEX_L2_W_XS_KZ, /* 7434 */ IC_EVEX_L2_W_XS_KZ, /* 7435 */ IC_EVEX_L2_W_XD_KZ, /* 7436 */ IC_EVEX_L2_W_XD_KZ, /* 7437 */ IC_EVEX_L2_W_XD_KZ, /* 7438 */ IC_EVEX_L2_W_XD_KZ, /* 7439 */ IC_EVEX_L2_OPSIZE_KZ, /* 7440 */ IC_EVEX_L2_OPSIZE_KZ, /* 7441 */ IC_EVEX_L2_OPSIZE_KZ, /* 7442 */ IC_EVEX_L2_OPSIZE_KZ, /* 7443 */ IC_EVEX_L2_OPSIZE_KZ, /* 7444 */ IC_EVEX_L2_OPSIZE_KZ, /* 7445 */ IC_EVEX_L2_OPSIZE_KZ, /* 7446 */ IC_EVEX_L2_OPSIZE_KZ, /* 7447 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7448 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7449 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7450 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7451 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7452 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7453 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7454 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7455 */ IC_EVEX_L2_KZ, /* 7456 */ IC_EVEX_L2_KZ, /* 7457 */ IC_EVEX_L2_XS_KZ, /* 7458 */ IC_EVEX_L2_XS_KZ, /* 7459 */ IC_EVEX_L2_XD_KZ, /* 7460 */ IC_EVEX_L2_XD_KZ, /* 7461 */ IC_EVEX_L2_XD_KZ, /* 7462 */ IC_EVEX_L2_XD_KZ, /* 7463 */ IC_EVEX_L2_W_KZ, /* 7464 */ IC_EVEX_L2_W_KZ, /* 7465 */ IC_EVEX_L2_W_XS_KZ, /* 7466 */ IC_EVEX_L2_W_XS_KZ, /* 7467 */ IC_EVEX_L2_W_XD_KZ, /* 7468 */ IC_EVEX_L2_W_XD_KZ, /* 7469 */ IC_EVEX_L2_W_XD_KZ, /* 7470 */ IC_EVEX_L2_W_XD_KZ, /* 7471 */ IC_EVEX_L2_OPSIZE_KZ, /* 7472 */ IC_EVEX_L2_OPSIZE_KZ, /* 7473 */ IC_EVEX_L2_OPSIZE_KZ, /* 7474 */ IC_EVEX_L2_OPSIZE_KZ, /* 7475 */ IC_EVEX_L2_OPSIZE_KZ, /* 7476 */ IC_EVEX_L2_OPSIZE_KZ, /* 7477 */ IC_EVEX_L2_OPSIZE_KZ, /* 7478 */ IC_EVEX_L2_OPSIZE_KZ, /* 7479 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7480 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7481 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7482 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7483 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7484 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7485 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7486 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7487 */ IC_EVEX_L2_KZ, /* 7488 */ IC_EVEX_L2_KZ, /* 7489 */ IC_EVEX_L2_XS_KZ, /* 7490 */ IC_EVEX_L2_XS_KZ, /* 7491 */ IC_EVEX_L2_XD_KZ, /* 7492 */ IC_EVEX_L2_XD_KZ, /* 7493 */ IC_EVEX_L2_XD_KZ, /* 7494 */ IC_EVEX_L2_XD_KZ, /* 7495 */ IC_EVEX_L2_W_KZ, /* 7496 */ IC_EVEX_L2_W_KZ, /* 7497 */ IC_EVEX_L2_W_XS_KZ, /* 7498 */ IC_EVEX_L2_W_XS_KZ, /* 7499 */ IC_EVEX_L2_W_XD_KZ, /* 7500 */ IC_EVEX_L2_W_XD_KZ, /* 7501 */ IC_EVEX_L2_W_XD_KZ, /* 7502 */ IC_EVEX_L2_W_XD_KZ, /* 7503 */ IC_EVEX_L2_OPSIZE_KZ, /* 7504 */ IC_EVEX_L2_OPSIZE_KZ, /* 7505 */ IC_EVEX_L2_OPSIZE_KZ, /* 7506 */ IC_EVEX_L2_OPSIZE_KZ, /* 7507 */ IC_EVEX_L2_OPSIZE_KZ, /* 7508 */ IC_EVEX_L2_OPSIZE_KZ, /* 7509 */ IC_EVEX_L2_OPSIZE_KZ, /* 7510 */ IC_EVEX_L2_OPSIZE_KZ, /* 7511 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7512 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7513 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7514 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7515 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7516 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7517 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7518 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7519 */ IC_EVEX_L2_KZ, /* 7520 */ IC_EVEX_L2_KZ, /* 7521 */ IC_EVEX_L2_XS_KZ, /* 7522 */ IC_EVEX_L2_XS_KZ, /* 7523 */ IC_EVEX_L2_XD_KZ, /* 7524 */ IC_EVEX_L2_XD_KZ, /* 7525 */ IC_EVEX_L2_XD_KZ, /* 7526 */ IC_EVEX_L2_XD_KZ, /* 7527 */ IC_EVEX_L2_W_KZ, /* 7528 */ IC_EVEX_L2_W_KZ, /* 7529 */ IC_EVEX_L2_W_XS_KZ, /* 7530 */ IC_EVEX_L2_W_XS_KZ, /* 7531 */ IC_EVEX_L2_W_XD_KZ, /* 7532 */ IC_EVEX_L2_W_XD_KZ, /* 7533 */ IC_EVEX_L2_W_XD_KZ, /* 7534 */ IC_EVEX_L2_W_XD_KZ, /* 7535 */ IC_EVEX_L2_OPSIZE_KZ, /* 7536 */ IC_EVEX_L2_OPSIZE_KZ, /* 7537 */ IC_EVEX_L2_OPSIZE_KZ, /* 7538 */ IC_EVEX_L2_OPSIZE_KZ, /* 7539 */ IC_EVEX_L2_OPSIZE_KZ, /* 7540 */ IC_EVEX_L2_OPSIZE_KZ, /* 7541 */ IC_EVEX_L2_OPSIZE_KZ, /* 7542 */ IC_EVEX_L2_OPSIZE_KZ, /* 7543 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7544 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7545 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7546 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7547 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7548 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7549 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7550 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7551 */ IC_EVEX_L2_KZ, /* 7552 */ IC_EVEX_L2_KZ, /* 7553 */ IC_EVEX_L2_XS_KZ, /* 7554 */ IC_EVEX_L2_XS_KZ, /* 7555 */ IC_EVEX_L2_XD_KZ, /* 7556 */ IC_EVEX_L2_XD_KZ, /* 7557 */ IC_EVEX_L2_XD_KZ, /* 7558 */ IC_EVEX_L2_XD_KZ, /* 7559 */ IC_EVEX_L2_W_KZ, /* 7560 */ IC_EVEX_L2_W_KZ, /* 7561 */ IC_EVEX_L2_W_XS_KZ, /* 7562 */ IC_EVEX_L2_W_XS_KZ, /* 7563 */ IC_EVEX_L2_W_XD_KZ, /* 7564 */ IC_EVEX_L2_W_XD_KZ, /* 7565 */ IC_EVEX_L2_W_XD_KZ, /* 7566 */ IC_EVEX_L2_W_XD_KZ, /* 7567 */ IC_EVEX_L2_OPSIZE_KZ, /* 7568 */ IC_EVEX_L2_OPSIZE_KZ, /* 7569 */ IC_EVEX_L2_OPSIZE_KZ, /* 7570 */ IC_EVEX_L2_OPSIZE_KZ, /* 7571 */ IC_EVEX_L2_OPSIZE_KZ, /* 7572 */ IC_EVEX_L2_OPSIZE_KZ, /* 7573 */ IC_EVEX_L2_OPSIZE_KZ, /* 7574 */ IC_EVEX_L2_OPSIZE_KZ, /* 7575 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7576 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7577 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7578 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7579 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7580 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7581 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7582 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7583 */ IC_EVEX_L2_KZ, /* 7584 */ IC_EVEX_L2_KZ, /* 7585 */ IC_EVEX_L2_XS_KZ, /* 7586 */ IC_EVEX_L2_XS_KZ, /* 7587 */ IC_EVEX_L2_XD_KZ, /* 7588 */ IC_EVEX_L2_XD_KZ, /* 7589 */ IC_EVEX_L2_XD_KZ, /* 7590 */ IC_EVEX_L2_XD_KZ, /* 7591 */ IC_EVEX_L2_W_KZ, /* 7592 */ IC_EVEX_L2_W_KZ, /* 7593 */ IC_EVEX_L2_W_XS_KZ, /* 7594 */ IC_EVEX_L2_W_XS_KZ, /* 7595 */ IC_EVEX_L2_W_XD_KZ, /* 7596 */ IC_EVEX_L2_W_XD_KZ, /* 7597 */ IC_EVEX_L2_W_XD_KZ, /* 7598 */ IC_EVEX_L2_W_XD_KZ, /* 7599 */ IC_EVEX_L2_OPSIZE_KZ, /* 7600 */ IC_EVEX_L2_OPSIZE_KZ, /* 7601 */ IC_EVEX_L2_OPSIZE_KZ, /* 7602 */ IC_EVEX_L2_OPSIZE_KZ, /* 7603 */ IC_EVEX_L2_OPSIZE_KZ, /* 7604 */ IC_EVEX_L2_OPSIZE_KZ, /* 7605 */ IC_EVEX_L2_OPSIZE_KZ, /* 7606 */ IC_EVEX_L2_OPSIZE_KZ, /* 7607 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7608 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7609 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7610 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7611 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7612 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7613 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7614 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7615 */ IC_EVEX_L2_KZ, /* 7616 */ IC_EVEX_L2_KZ, /* 7617 */ IC_EVEX_L2_XS_KZ, /* 7618 */ IC_EVEX_L2_XS_KZ, /* 7619 */ IC_EVEX_L2_XD_KZ, /* 7620 */ IC_EVEX_L2_XD_KZ, /* 7621 */ IC_EVEX_L2_XD_KZ, /* 7622 */ IC_EVEX_L2_XD_KZ, /* 7623 */ IC_EVEX_L2_W_KZ, /* 7624 */ IC_EVEX_L2_W_KZ, /* 7625 */ IC_EVEX_L2_W_XS_KZ, /* 7626 */ IC_EVEX_L2_W_XS_KZ, /* 7627 */ IC_EVEX_L2_W_XD_KZ, /* 7628 */ IC_EVEX_L2_W_XD_KZ, /* 7629 */ IC_EVEX_L2_W_XD_KZ, /* 7630 */ IC_EVEX_L2_W_XD_KZ, /* 7631 */ IC_EVEX_L2_OPSIZE_KZ, /* 7632 */ IC_EVEX_L2_OPSIZE_KZ, /* 7633 */ IC_EVEX_L2_OPSIZE_KZ, /* 7634 */ IC_EVEX_L2_OPSIZE_KZ, /* 7635 */ IC_EVEX_L2_OPSIZE_KZ, /* 7636 */ IC_EVEX_L2_OPSIZE_KZ, /* 7637 */ IC_EVEX_L2_OPSIZE_KZ, /* 7638 */ IC_EVEX_L2_OPSIZE_KZ, /* 7639 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7640 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7641 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7642 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7643 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7644 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7645 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7646 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7647 */ IC_EVEX_L2_KZ, /* 7648 */ IC_EVEX_L2_KZ, /* 7649 */ IC_EVEX_L2_XS_KZ, /* 7650 */ IC_EVEX_L2_XS_KZ, /* 7651 */ IC_EVEX_L2_XD_KZ, /* 7652 */ IC_EVEX_L2_XD_KZ, /* 7653 */ IC_EVEX_L2_XD_KZ, /* 7654 */ IC_EVEX_L2_XD_KZ, /* 7655 */ IC_EVEX_L2_W_KZ, /* 7656 */ IC_EVEX_L2_W_KZ, /* 7657 */ IC_EVEX_L2_W_XS_KZ, /* 7658 */ IC_EVEX_L2_W_XS_KZ, /* 7659 */ IC_EVEX_L2_W_XD_KZ, /* 7660 */ IC_EVEX_L2_W_XD_KZ, /* 7661 */ IC_EVEX_L2_W_XD_KZ, /* 7662 */ IC_EVEX_L2_W_XD_KZ, /* 7663 */ IC_EVEX_L2_OPSIZE_KZ, /* 7664 */ IC_EVEX_L2_OPSIZE_KZ, /* 7665 */ IC_EVEX_L2_OPSIZE_KZ, /* 7666 */ IC_EVEX_L2_OPSIZE_KZ, /* 7667 */ IC_EVEX_L2_OPSIZE_KZ, /* 7668 */ IC_EVEX_L2_OPSIZE_KZ, /* 7669 */ IC_EVEX_L2_OPSIZE_KZ, /* 7670 */ IC_EVEX_L2_OPSIZE_KZ, /* 7671 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7672 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7673 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7674 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7675 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7676 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7677 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7678 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7679 */ IC, /* 7680 */ IC_64BIT, /* 7681 */ IC_XS, /* 7682 */ IC_64BIT_XS, /* 7683 */ IC_XD, /* 7684 */ IC_64BIT_XD, /* 7685 */ IC_XS, /* 7686 */ IC_64BIT_XS, /* 7687 */ IC, /* 7688 */ IC_64BIT_REXW, /* 7689 */ IC_XS, /* 7690 */ IC_64BIT_REXW_XS, /* 7691 */ IC_XD, /* 7692 */ IC_64BIT_REXW_XD, /* 7693 */ IC_XS, /* 7694 */ IC_64BIT_REXW_XS, /* 7695 */ IC_OPSIZE, /* 7696 */ IC_64BIT_OPSIZE, /* 7697 */ IC_XS_OPSIZE, /* 7698 */ IC_64BIT_XS_OPSIZE, /* 7699 */ IC_XD_OPSIZE, /* 7700 */ IC_64BIT_XD_OPSIZE, /* 7701 */ IC_XS_OPSIZE, /* 7702 */ IC_64BIT_XD_OPSIZE, /* 7703 */ IC_OPSIZE, /* 7704 */ IC_64BIT_REXW_OPSIZE, /* 7705 */ IC_XS_OPSIZE, /* 7706 */ IC_64BIT_REXW_XS, /* 7707 */ IC_XD_OPSIZE, /* 7708 */ IC_64BIT_REXW_XD, /* 7709 */ IC_XS_OPSIZE, /* 7710 */ IC_64BIT_REXW_XS, /* 7711 */ IC_ADSIZE, /* 7712 */ IC_64BIT_ADSIZE, /* 7713 */ IC_XS_ADSIZE, /* 7714 */ IC_64BIT_XS_ADSIZE, /* 7715 */ IC_XD_ADSIZE, /* 7716 */ IC_64BIT_XD_ADSIZE, /* 7717 */ IC_XS_ADSIZE, /* 7718 */ IC_64BIT_XD_ADSIZE, /* 7719 */ IC_ADSIZE, /* 7720 */ IC_64BIT_REXW_ADSIZE, /* 7721 */ IC_XS_ADSIZE, /* 7722 */ IC_64BIT_REXW_XS, /* 7723 */ IC_XD_ADSIZE, /* 7724 */ IC_64BIT_REXW_XD, /* 7725 */ IC_XS_ADSIZE, /* 7726 */ IC_64BIT_REXW_XS, /* 7727 */ IC_OPSIZE_ADSIZE, /* 7728 */ IC_64BIT_OPSIZE_ADSIZE, /* 7729 */ IC_XS_OPSIZE, /* 7730 */ IC_64BIT_XS_OPSIZE, /* 7731 */ IC_XD_OPSIZE, /* 7732 */ IC_64BIT_XD_OPSIZE, /* 7733 */ IC_XS_OPSIZE, /* 7734 */ IC_64BIT_XD_OPSIZE, /* 7735 */ IC_OPSIZE_ADSIZE, /* 7736 */ IC_64BIT_REXW_OPSIZE, /* 7737 */ IC_XS_OPSIZE, /* 7738 */ IC_64BIT_REXW_XS, /* 7739 */ IC_XD_OPSIZE, /* 7740 */ IC_64BIT_REXW_XD, /* 7741 */ IC_XS_OPSIZE, /* 7742 */ IC_64BIT_REXW_XS, /* 7743 */ IC_VEX, /* 7744 */ IC_VEX, /* 7745 */ IC_VEX_XS, /* 7746 */ IC_VEX_XS, /* 7747 */ IC_VEX_XD, /* 7748 */ IC_VEX_XD, /* 7749 */ IC_VEX_XD, /* 7750 */ IC_VEX_XD, /* 7751 */ IC_VEX_W, /* 7752 */ IC_VEX_W, /* 7753 */ IC_VEX_W_XS, /* 7754 */ IC_VEX_W_XS, /* 7755 */ IC_VEX_W_XD, /* 7756 */ IC_VEX_W_XD, /* 7757 */ IC_VEX_W_XD, /* 7758 */ IC_VEX_W_XD, /* 7759 */ IC_VEX_OPSIZE, /* 7760 */ IC_VEX_OPSIZE, /* 7761 */ IC_VEX_OPSIZE, /* 7762 */ IC_VEX_OPSIZE, /* 7763 */ IC_VEX_OPSIZE, /* 7764 */ IC_VEX_OPSIZE, /* 7765 */ IC_VEX_OPSIZE, /* 7766 */ IC_VEX_OPSIZE, /* 7767 */ IC_VEX_W_OPSIZE, /* 7768 */ IC_VEX_W_OPSIZE, /* 7769 */ IC_VEX_W_OPSIZE, /* 7770 */ IC_VEX_W_OPSIZE, /* 7771 */ IC_VEX_W_OPSIZE, /* 7772 */ IC_VEX_W_OPSIZE, /* 7773 */ IC_VEX_W_OPSIZE, /* 7774 */ IC_VEX_W_OPSIZE, /* 7775 */ IC_VEX, /* 7776 */ IC_VEX, /* 7777 */ IC_VEX_XS, /* 7778 */ IC_VEX_XS, /* 7779 */ IC_VEX_XD, /* 7780 */ IC_VEX_XD, /* 7781 */ IC_VEX_XD, /* 7782 */ IC_VEX_XD, /* 7783 */ IC_VEX_W, /* 7784 */ IC_VEX_W, /* 7785 */ IC_VEX_W_XS, /* 7786 */ IC_VEX_W_XS, /* 7787 */ IC_VEX_W_XD, /* 7788 */ IC_VEX_W_XD, /* 7789 */ IC_VEX_W_XD, /* 7790 */ IC_VEX_W_XD, /* 7791 */ IC_VEX_OPSIZE, /* 7792 */ IC_VEX_OPSIZE, /* 7793 */ IC_VEX_OPSIZE, /* 7794 */ IC_VEX_OPSIZE, /* 7795 */ IC_VEX_OPSIZE, /* 7796 */ IC_VEX_OPSIZE, /* 7797 */ IC_VEX_OPSIZE, /* 7798 */ IC_VEX_OPSIZE, /* 7799 */ IC_VEX_W_OPSIZE, /* 7800 */ IC_VEX_W_OPSIZE, /* 7801 */ IC_VEX_W_OPSIZE, /* 7802 */ IC_VEX_W_OPSIZE, /* 7803 */ IC_VEX_W_OPSIZE, /* 7804 */ IC_VEX_W_OPSIZE, /* 7805 */ IC_VEX_W_OPSIZE, /* 7806 */ IC_VEX_W_OPSIZE, /* 7807 */ IC_VEX_L, /* 7808 */ IC_VEX_L, /* 7809 */ IC_VEX_L_XS, /* 7810 */ IC_VEX_L_XS, /* 7811 */ IC_VEX_L_XD, /* 7812 */ IC_VEX_L_XD, /* 7813 */ IC_VEX_L_XD, /* 7814 */ IC_VEX_L_XD, /* 7815 */ IC_VEX_L_W, /* 7816 */ IC_VEX_L_W, /* 7817 */ IC_VEX_L_W_XS, /* 7818 */ IC_VEX_L_W_XS, /* 7819 */ IC_VEX_L_W_XD, /* 7820 */ IC_VEX_L_W_XD, /* 7821 */ IC_VEX_L_W_XD, /* 7822 */ IC_VEX_L_W_XD, /* 7823 */ IC_VEX_L_OPSIZE, /* 7824 */ IC_VEX_L_OPSIZE, /* 7825 */ IC_VEX_L_OPSIZE, /* 7826 */ IC_VEX_L_OPSIZE, /* 7827 */ IC_VEX_L_OPSIZE, /* 7828 */ IC_VEX_L_OPSIZE, /* 7829 */ IC_VEX_L_OPSIZE, /* 7830 */ IC_VEX_L_OPSIZE, /* 7831 */ IC_VEX_L_W_OPSIZE, /* 7832 */ IC_VEX_L_W_OPSIZE, /* 7833 */ IC_VEX_L_W_OPSIZE, /* 7834 */ IC_VEX_L_W_OPSIZE, /* 7835 */ IC_VEX_L_W_OPSIZE, /* 7836 */ IC_VEX_L_W_OPSIZE, /* 7837 */ IC_VEX_L_W_OPSIZE, /* 7838 */ IC_VEX_L_W_OPSIZE, /* 7839 */ IC_VEX_L, /* 7840 */ IC_VEX_L, /* 7841 */ IC_VEX_L_XS, /* 7842 */ IC_VEX_L_XS, /* 7843 */ IC_VEX_L_XD, /* 7844 */ IC_VEX_L_XD, /* 7845 */ IC_VEX_L_XD, /* 7846 */ IC_VEX_L_XD, /* 7847 */ IC_VEX_L_W, /* 7848 */ IC_VEX_L_W, /* 7849 */ IC_VEX_L_W_XS, /* 7850 */ IC_VEX_L_W_XS, /* 7851 */ IC_VEX_L_W_XD, /* 7852 */ IC_VEX_L_W_XD, /* 7853 */ IC_VEX_L_W_XD, /* 7854 */ IC_VEX_L_W_XD, /* 7855 */ IC_VEX_L_OPSIZE, /* 7856 */ IC_VEX_L_OPSIZE, /* 7857 */ IC_VEX_L_OPSIZE, /* 7858 */ IC_VEX_L_OPSIZE, /* 7859 */ IC_VEX_L_OPSIZE, /* 7860 */ IC_VEX_L_OPSIZE, /* 7861 */ IC_VEX_L_OPSIZE, /* 7862 */ IC_VEX_L_OPSIZE, /* 7863 */ IC_VEX_L_W_OPSIZE, /* 7864 */ IC_VEX_L_W_OPSIZE, /* 7865 */ IC_VEX_L_W_OPSIZE, /* 7866 */ IC_VEX_L_W_OPSIZE, /* 7867 */ IC_VEX_L_W_OPSIZE, /* 7868 */ IC_VEX_L_W_OPSIZE, /* 7869 */ IC_VEX_L_W_OPSIZE, /* 7870 */ IC_VEX_L_W_OPSIZE, /* 7871 */ IC_VEX_L, /* 7872 */ IC_VEX_L, /* 7873 */ IC_VEX_L_XS, /* 7874 */ IC_VEX_L_XS, /* 7875 */ IC_VEX_L_XD, /* 7876 */ IC_VEX_L_XD, /* 7877 */ IC_VEX_L_XD, /* 7878 */ IC_VEX_L_XD, /* 7879 */ IC_VEX_L_W, /* 7880 */ IC_VEX_L_W, /* 7881 */ IC_VEX_L_W_XS, /* 7882 */ IC_VEX_L_W_XS, /* 7883 */ IC_VEX_L_W_XD, /* 7884 */ IC_VEX_L_W_XD, /* 7885 */ IC_VEX_L_W_XD, /* 7886 */ IC_VEX_L_W_XD, /* 7887 */ IC_VEX_L_OPSIZE, /* 7888 */ IC_VEX_L_OPSIZE, /* 7889 */ IC_VEX_L_OPSIZE, /* 7890 */ IC_VEX_L_OPSIZE, /* 7891 */ IC_VEX_L_OPSIZE, /* 7892 */ IC_VEX_L_OPSIZE, /* 7893 */ IC_VEX_L_OPSIZE, /* 7894 */ IC_VEX_L_OPSIZE, /* 7895 */ IC_VEX_L_W_OPSIZE, /* 7896 */ IC_VEX_L_W_OPSIZE, /* 7897 */ IC_VEX_L_W_OPSIZE, /* 7898 */ IC_VEX_L_W_OPSIZE, /* 7899 */ IC_VEX_L_W_OPSIZE, /* 7900 */ IC_VEX_L_W_OPSIZE, /* 7901 */ IC_VEX_L_W_OPSIZE, /* 7902 */ IC_VEX_L_W_OPSIZE, /* 7903 */ IC_VEX_L, /* 7904 */ IC_VEX_L, /* 7905 */ IC_VEX_L_XS, /* 7906 */ IC_VEX_L_XS, /* 7907 */ IC_VEX_L_XD, /* 7908 */ IC_VEX_L_XD, /* 7909 */ IC_VEX_L_XD, /* 7910 */ IC_VEX_L_XD, /* 7911 */ IC_VEX_L_W, /* 7912 */ IC_VEX_L_W, /* 7913 */ IC_VEX_L_W_XS, /* 7914 */ IC_VEX_L_W_XS, /* 7915 */ IC_VEX_L_W_XD, /* 7916 */ IC_VEX_L_W_XD, /* 7917 */ IC_VEX_L_W_XD, /* 7918 */ IC_VEX_L_W_XD, /* 7919 */ IC_VEX_L_OPSIZE, /* 7920 */ IC_VEX_L_OPSIZE, /* 7921 */ IC_VEX_L_OPSIZE, /* 7922 */ IC_VEX_L_OPSIZE, /* 7923 */ IC_VEX_L_OPSIZE, /* 7924 */ IC_VEX_L_OPSIZE, /* 7925 */ IC_VEX_L_OPSIZE, /* 7926 */ IC_VEX_L_OPSIZE, /* 7927 */ IC_VEX_L_W_OPSIZE, /* 7928 */ IC_VEX_L_W_OPSIZE, /* 7929 */ IC_VEX_L_W_OPSIZE, /* 7930 */ IC_VEX_L_W_OPSIZE, /* 7931 */ IC_VEX_L_W_OPSIZE, /* 7932 */ IC_VEX_L_W_OPSIZE, /* 7933 */ IC_VEX_L_W_OPSIZE, /* 7934 */ IC_VEX_L_W_OPSIZE, /* 7935 */ IC_EVEX_L2_KZ, /* 7936 */ IC_EVEX_L2_KZ, /* 7937 */ IC_EVEX_L2_XS_KZ, /* 7938 */ IC_EVEX_L2_XS_KZ, /* 7939 */ IC_EVEX_L2_XD_KZ, /* 7940 */ IC_EVEX_L2_XD_KZ, /* 7941 */ IC_EVEX_L2_XD_KZ, /* 7942 */ IC_EVEX_L2_XD_KZ, /* 7943 */ IC_EVEX_L2_W_KZ, /* 7944 */ IC_EVEX_L2_W_KZ, /* 7945 */ IC_EVEX_L2_W_XS_KZ, /* 7946 */ IC_EVEX_L2_W_XS_KZ, /* 7947 */ IC_EVEX_L2_W_XD_KZ, /* 7948 */ IC_EVEX_L2_W_XD_KZ, /* 7949 */ IC_EVEX_L2_W_XD_KZ, /* 7950 */ IC_EVEX_L2_W_XD_KZ, /* 7951 */ IC_EVEX_L2_OPSIZE_KZ, /* 7952 */ IC_EVEX_L2_OPSIZE_KZ, /* 7953 */ IC_EVEX_L2_OPSIZE_KZ, /* 7954 */ IC_EVEX_L2_OPSIZE_KZ, /* 7955 */ IC_EVEX_L2_OPSIZE_KZ, /* 7956 */ IC_EVEX_L2_OPSIZE_KZ, /* 7957 */ IC_EVEX_L2_OPSIZE_KZ, /* 7958 */ IC_EVEX_L2_OPSIZE_KZ, /* 7959 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7960 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7961 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7962 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7963 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7964 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7965 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7966 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7967 */ IC_EVEX_L2_KZ, /* 7968 */ IC_EVEX_L2_KZ, /* 7969 */ IC_EVEX_L2_XS_KZ, /* 7970 */ IC_EVEX_L2_XS_KZ, /* 7971 */ IC_EVEX_L2_XD_KZ, /* 7972 */ IC_EVEX_L2_XD_KZ, /* 7973 */ IC_EVEX_L2_XD_KZ, /* 7974 */ IC_EVEX_L2_XD_KZ, /* 7975 */ IC_EVEX_L2_W_KZ, /* 7976 */ IC_EVEX_L2_W_KZ, /* 7977 */ IC_EVEX_L2_W_XS_KZ, /* 7978 */ IC_EVEX_L2_W_XS_KZ, /* 7979 */ IC_EVEX_L2_W_XD_KZ, /* 7980 */ IC_EVEX_L2_W_XD_KZ, /* 7981 */ IC_EVEX_L2_W_XD_KZ, /* 7982 */ IC_EVEX_L2_W_XD_KZ, /* 7983 */ IC_EVEX_L2_OPSIZE_KZ, /* 7984 */ IC_EVEX_L2_OPSIZE_KZ, /* 7985 */ IC_EVEX_L2_OPSIZE_KZ, /* 7986 */ IC_EVEX_L2_OPSIZE_KZ, /* 7987 */ IC_EVEX_L2_OPSIZE_KZ, /* 7988 */ IC_EVEX_L2_OPSIZE_KZ, /* 7989 */ IC_EVEX_L2_OPSIZE_KZ, /* 7990 */ IC_EVEX_L2_OPSIZE_KZ, /* 7991 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7992 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7993 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7994 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7995 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7996 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7997 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7998 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 7999 */ IC_EVEX_L2_KZ, /* 8000 */ IC_EVEX_L2_KZ, /* 8001 */ IC_EVEX_L2_XS_KZ, /* 8002 */ IC_EVEX_L2_XS_KZ, /* 8003 */ IC_EVEX_L2_XD_KZ, /* 8004 */ IC_EVEX_L2_XD_KZ, /* 8005 */ IC_EVEX_L2_XD_KZ, /* 8006 */ IC_EVEX_L2_XD_KZ, /* 8007 */ IC_EVEX_L2_W_KZ, /* 8008 */ IC_EVEX_L2_W_KZ, /* 8009 */ IC_EVEX_L2_W_XS_KZ, /* 8010 */ IC_EVEX_L2_W_XS_KZ, /* 8011 */ IC_EVEX_L2_W_XD_KZ, /* 8012 */ IC_EVEX_L2_W_XD_KZ, /* 8013 */ IC_EVEX_L2_W_XD_KZ, /* 8014 */ IC_EVEX_L2_W_XD_KZ, /* 8015 */ IC_EVEX_L2_OPSIZE_KZ, /* 8016 */ IC_EVEX_L2_OPSIZE_KZ, /* 8017 */ IC_EVEX_L2_OPSIZE_KZ, /* 8018 */ IC_EVEX_L2_OPSIZE_KZ, /* 8019 */ IC_EVEX_L2_OPSIZE_KZ, /* 8020 */ IC_EVEX_L2_OPSIZE_KZ, /* 8021 */ IC_EVEX_L2_OPSIZE_KZ, /* 8022 */ IC_EVEX_L2_OPSIZE_KZ, /* 8023 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8024 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8025 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8026 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8027 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8028 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8029 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8030 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8031 */ IC_EVEX_L2_KZ, /* 8032 */ IC_EVEX_L2_KZ, /* 8033 */ IC_EVEX_L2_XS_KZ, /* 8034 */ IC_EVEX_L2_XS_KZ, /* 8035 */ IC_EVEX_L2_XD_KZ, /* 8036 */ IC_EVEX_L2_XD_KZ, /* 8037 */ IC_EVEX_L2_XD_KZ, /* 8038 */ IC_EVEX_L2_XD_KZ, /* 8039 */ IC_EVEX_L2_W_KZ, /* 8040 */ IC_EVEX_L2_W_KZ, /* 8041 */ IC_EVEX_L2_W_XS_KZ, /* 8042 */ IC_EVEX_L2_W_XS_KZ, /* 8043 */ IC_EVEX_L2_W_XD_KZ, /* 8044 */ IC_EVEX_L2_W_XD_KZ, /* 8045 */ IC_EVEX_L2_W_XD_KZ, /* 8046 */ IC_EVEX_L2_W_XD_KZ, /* 8047 */ IC_EVEX_L2_OPSIZE_KZ, /* 8048 */ IC_EVEX_L2_OPSIZE_KZ, /* 8049 */ IC_EVEX_L2_OPSIZE_KZ, /* 8050 */ IC_EVEX_L2_OPSIZE_KZ, /* 8051 */ IC_EVEX_L2_OPSIZE_KZ, /* 8052 */ IC_EVEX_L2_OPSIZE_KZ, /* 8053 */ IC_EVEX_L2_OPSIZE_KZ, /* 8054 */ IC_EVEX_L2_OPSIZE_KZ, /* 8055 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8056 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8057 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8058 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8059 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8060 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8061 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8062 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8063 */ IC_EVEX_L2_KZ, /* 8064 */ IC_EVEX_L2_KZ, /* 8065 */ IC_EVEX_L2_XS_KZ, /* 8066 */ IC_EVEX_L2_XS_KZ, /* 8067 */ IC_EVEX_L2_XD_KZ, /* 8068 */ IC_EVEX_L2_XD_KZ, /* 8069 */ IC_EVEX_L2_XD_KZ, /* 8070 */ IC_EVEX_L2_XD_KZ, /* 8071 */ IC_EVEX_L2_W_KZ, /* 8072 */ IC_EVEX_L2_W_KZ, /* 8073 */ IC_EVEX_L2_W_XS_KZ, /* 8074 */ IC_EVEX_L2_W_XS_KZ, /* 8075 */ IC_EVEX_L2_W_XD_KZ, /* 8076 */ IC_EVEX_L2_W_XD_KZ, /* 8077 */ IC_EVEX_L2_W_XD_KZ, /* 8078 */ IC_EVEX_L2_W_XD_KZ, /* 8079 */ IC_EVEX_L2_OPSIZE_KZ, /* 8080 */ IC_EVEX_L2_OPSIZE_KZ, /* 8081 */ IC_EVEX_L2_OPSIZE_KZ, /* 8082 */ IC_EVEX_L2_OPSIZE_KZ, /* 8083 */ IC_EVEX_L2_OPSIZE_KZ, /* 8084 */ IC_EVEX_L2_OPSIZE_KZ, /* 8085 */ IC_EVEX_L2_OPSIZE_KZ, /* 8086 */ IC_EVEX_L2_OPSIZE_KZ, /* 8087 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8088 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8089 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8090 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8091 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8092 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8093 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8094 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8095 */ IC_EVEX_L2_KZ, /* 8096 */ IC_EVEX_L2_KZ, /* 8097 */ IC_EVEX_L2_XS_KZ, /* 8098 */ IC_EVEX_L2_XS_KZ, /* 8099 */ IC_EVEX_L2_XD_KZ, /* 8100 */ IC_EVEX_L2_XD_KZ, /* 8101 */ IC_EVEX_L2_XD_KZ, /* 8102 */ IC_EVEX_L2_XD_KZ, /* 8103 */ IC_EVEX_L2_W_KZ, /* 8104 */ IC_EVEX_L2_W_KZ, /* 8105 */ IC_EVEX_L2_W_XS_KZ, /* 8106 */ IC_EVEX_L2_W_XS_KZ, /* 8107 */ IC_EVEX_L2_W_XD_KZ, /* 8108 */ IC_EVEX_L2_W_XD_KZ, /* 8109 */ IC_EVEX_L2_W_XD_KZ, /* 8110 */ IC_EVEX_L2_W_XD_KZ, /* 8111 */ IC_EVEX_L2_OPSIZE_KZ, /* 8112 */ IC_EVEX_L2_OPSIZE_KZ, /* 8113 */ IC_EVEX_L2_OPSIZE_KZ, /* 8114 */ IC_EVEX_L2_OPSIZE_KZ, /* 8115 */ IC_EVEX_L2_OPSIZE_KZ, /* 8116 */ IC_EVEX_L2_OPSIZE_KZ, /* 8117 */ IC_EVEX_L2_OPSIZE_KZ, /* 8118 */ IC_EVEX_L2_OPSIZE_KZ, /* 8119 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8120 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8121 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8122 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8123 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8124 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8125 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8126 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8127 */ IC_EVEX_L2_KZ, /* 8128 */ IC_EVEX_L2_KZ, /* 8129 */ IC_EVEX_L2_XS_KZ, /* 8130 */ IC_EVEX_L2_XS_KZ, /* 8131 */ IC_EVEX_L2_XD_KZ, /* 8132 */ IC_EVEX_L2_XD_KZ, /* 8133 */ IC_EVEX_L2_XD_KZ, /* 8134 */ IC_EVEX_L2_XD_KZ, /* 8135 */ IC_EVEX_L2_W_KZ, /* 8136 */ IC_EVEX_L2_W_KZ, /* 8137 */ IC_EVEX_L2_W_XS_KZ, /* 8138 */ IC_EVEX_L2_W_XS_KZ, /* 8139 */ IC_EVEX_L2_W_XD_KZ, /* 8140 */ IC_EVEX_L2_W_XD_KZ, /* 8141 */ IC_EVEX_L2_W_XD_KZ, /* 8142 */ IC_EVEX_L2_W_XD_KZ, /* 8143 */ IC_EVEX_L2_OPSIZE_KZ, /* 8144 */ IC_EVEX_L2_OPSIZE_KZ, /* 8145 */ IC_EVEX_L2_OPSIZE_KZ, /* 8146 */ IC_EVEX_L2_OPSIZE_KZ, /* 8147 */ IC_EVEX_L2_OPSIZE_KZ, /* 8148 */ IC_EVEX_L2_OPSIZE_KZ, /* 8149 */ IC_EVEX_L2_OPSIZE_KZ, /* 8150 */ IC_EVEX_L2_OPSIZE_KZ, /* 8151 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8152 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8153 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8154 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8155 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8156 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8157 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8158 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8159 */ IC_EVEX_L2_KZ, /* 8160 */ IC_EVEX_L2_KZ, /* 8161 */ IC_EVEX_L2_XS_KZ, /* 8162 */ IC_EVEX_L2_XS_KZ, /* 8163 */ IC_EVEX_L2_XD_KZ, /* 8164 */ IC_EVEX_L2_XD_KZ, /* 8165 */ IC_EVEX_L2_XD_KZ, /* 8166 */ IC_EVEX_L2_XD_KZ, /* 8167 */ IC_EVEX_L2_W_KZ, /* 8168 */ IC_EVEX_L2_W_KZ, /* 8169 */ IC_EVEX_L2_W_XS_KZ, /* 8170 */ IC_EVEX_L2_W_XS_KZ, /* 8171 */ IC_EVEX_L2_W_XD_KZ, /* 8172 */ IC_EVEX_L2_W_XD_KZ, /* 8173 */ IC_EVEX_L2_W_XD_KZ, /* 8174 */ IC_EVEX_L2_W_XD_KZ, /* 8175 */ IC_EVEX_L2_OPSIZE_KZ, /* 8176 */ IC_EVEX_L2_OPSIZE_KZ, /* 8177 */ IC_EVEX_L2_OPSIZE_KZ, /* 8178 */ IC_EVEX_L2_OPSIZE_KZ, /* 8179 */ IC_EVEX_L2_OPSIZE_KZ, /* 8180 */ IC_EVEX_L2_OPSIZE_KZ, /* 8181 */ IC_EVEX_L2_OPSIZE_KZ, /* 8182 */ IC_EVEX_L2_OPSIZE_KZ, /* 8183 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8184 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8185 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8186 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8187 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8188 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8189 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8190 */ IC_EVEX_L2_W_OPSIZE_KZ, /* 8191 */ IC, /* 8192 */ IC_64BIT, /* 8193 */ IC_XS, /* 8194 */ IC_64BIT_XS, /* 8195 */ IC_XD, /* 8196 */ IC_64BIT_XD, /* 8197 */ IC_XS, /* 8198 */ IC_64BIT_XS, /* 8199 */ IC, /* 8200 */ IC_64BIT_REXW, /* 8201 */ IC_XS, /* 8202 */ IC_64BIT_REXW_XS, /* 8203 */ IC_XD, /* 8204 */ IC_64BIT_REXW_XD, /* 8205 */ IC_XS, /* 8206 */ IC_64BIT_REXW_XS, /* 8207 */ IC_OPSIZE, /* 8208 */ IC_64BIT_OPSIZE, /* 8209 */ IC_XS_OPSIZE, /* 8210 */ IC_64BIT_XS_OPSIZE, /* 8211 */ IC_XD_OPSIZE, /* 8212 */ IC_64BIT_XD_OPSIZE, /* 8213 */ IC_XS_OPSIZE, /* 8214 */ IC_64BIT_XD_OPSIZE, /* 8215 */ IC_OPSIZE, /* 8216 */ IC_64BIT_REXW_OPSIZE, /* 8217 */ IC_XS_OPSIZE, /* 8218 */ IC_64BIT_REXW_XS, /* 8219 */ IC_XD_OPSIZE, /* 8220 */ IC_64BIT_REXW_XD, /* 8221 */ IC_XS_OPSIZE, /* 8222 */ IC_64BIT_REXW_XS, /* 8223 */ IC_ADSIZE, /* 8224 */ IC_64BIT_ADSIZE, /* 8225 */ IC_XS_ADSIZE, /* 8226 */ IC_64BIT_XS_ADSIZE, /* 8227 */ IC_XD_ADSIZE, /* 8228 */ IC_64BIT_XD_ADSIZE, /* 8229 */ IC_XS_ADSIZE, /* 8230 */ IC_64BIT_XD_ADSIZE, /* 8231 */ IC_ADSIZE, /* 8232 */ IC_64BIT_REXW_ADSIZE, /* 8233 */ IC_XS_ADSIZE, /* 8234 */ IC_64BIT_REXW_XS, /* 8235 */ IC_XD_ADSIZE, /* 8236 */ IC_64BIT_REXW_XD, /* 8237 */ IC_XS_ADSIZE, /* 8238 */ IC_64BIT_REXW_XS, /* 8239 */ IC_OPSIZE_ADSIZE, /* 8240 */ IC_64BIT_OPSIZE_ADSIZE, /* 8241 */ IC_XS_OPSIZE, /* 8242 */ IC_64BIT_XS_OPSIZE, /* 8243 */ IC_XD_OPSIZE, /* 8244 */ IC_64BIT_XD_OPSIZE, /* 8245 */ IC_XS_OPSIZE, /* 8246 */ IC_64BIT_XD_OPSIZE, /* 8247 */ IC_OPSIZE_ADSIZE, /* 8248 */ IC_64BIT_REXW_OPSIZE, /* 8249 */ IC_XS_OPSIZE, /* 8250 */ IC_64BIT_REXW_XS, /* 8251 */ IC_XD_OPSIZE, /* 8252 */ IC_64BIT_REXW_XD, /* 8253 */ IC_XS_OPSIZE, /* 8254 */ IC_64BIT_REXW_XS, /* 8255 */ IC_VEX, /* 8256 */ IC_VEX, /* 8257 */ IC_VEX_XS, /* 8258 */ IC_VEX_XS, /* 8259 */ IC_VEX_XD, /* 8260 */ IC_VEX_XD, /* 8261 */ IC_VEX_XD, /* 8262 */ IC_VEX_XD, /* 8263 */ IC_VEX_W, /* 8264 */ IC_VEX_W, /* 8265 */ IC_VEX_W_XS, /* 8266 */ IC_VEX_W_XS, /* 8267 */ IC_VEX_W_XD, /* 8268 */ IC_VEX_W_XD, /* 8269 */ IC_VEX_W_XD, /* 8270 */ IC_VEX_W_XD, /* 8271 */ IC_VEX_OPSIZE, /* 8272 */ IC_VEX_OPSIZE, /* 8273 */ IC_VEX_OPSIZE, /* 8274 */ IC_VEX_OPSIZE, /* 8275 */ IC_VEX_OPSIZE, /* 8276 */ IC_VEX_OPSIZE, /* 8277 */ IC_VEX_OPSIZE, /* 8278 */ IC_VEX_OPSIZE, /* 8279 */ IC_VEX_W_OPSIZE, /* 8280 */ IC_VEX_W_OPSIZE, /* 8281 */ IC_VEX_W_OPSIZE, /* 8282 */ IC_VEX_W_OPSIZE, /* 8283 */ IC_VEX_W_OPSIZE, /* 8284 */ IC_VEX_W_OPSIZE, /* 8285 */ IC_VEX_W_OPSIZE, /* 8286 */ IC_VEX_W_OPSIZE, /* 8287 */ IC_VEX, /* 8288 */ IC_VEX, /* 8289 */ IC_VEX_XS, /* 8290 */ IC_VEX_XS, /* 8291 */ IC_VEX_XD, /* 8292 */ IC_VEX_XD, /* 8293 */ IC_VEX_XD, /* 8294 */ IC_VEX_XD, /* 8295 */ IC_VEX_W, /* 8296 */ IC_VEX_W, /* 8297 */ IC_VEX_W_XS, /* 8298 */ IC_VEX_W_XS, /* 8299 */ IC_VEX_W_XD, /* 8300 */ IC_VEX_W_XD, /* 8301 */ IC_VEX_W_XD, /* 8302 */ IC_VEX_W_XD, /* 8303 */ IC_VEX_OPSIZE, /* 8304 */ IC_VEX_OPSIZE, /* 8305 */ IC_VEX_OPSIZE, /* 8306 */ IC_VEX_OPSIZE, /* 8307 */ IC_VEX_OPSIZE, /* 8308 */ IC_VEX_OPSIZE, /* 8309 */ IC_VEX_OPSIZE, /* 8310 */ IC_VEX_OPSIZE, /* 8311 */ IC_VEX_W_OPSIZE, /* 8312 */ IC_VEX_W_OPSIZE, /* 8313 */ IC_VEX_W_OPSIZE, /* 8314 */ IC_VEX_W_OPSIZE, /* 8315 */ IC_VEX_W_OPSIZE, /* 8316 */ IC_VEX_W_OPSIZE, /* 8317 */ IC_VEX_W_OPSIZE, /* 8318 */ IC_VEX_W_OPSIZE, /* 8319 */ IC_VEX_L, /* 8320 */ IC_VEX_L, /* 8321 */ IC_VEX_L_XS, /* 8322 */ IC_VEX_L_XS, /* 8323 */ IC_VEX_L_XD, /* 8324 */ IC_VEX_L_XD, /* 8325 */ IC_VEX_L_XD, /* 8326 */ IC_VEX_L_XD, /* 8327 */ IC_VEX_L_W, /* 8328 */ IC_VEX_L_W, /* 8329 */ IC_VEX_L_W_XS, /* 8330 */ IC_VEX_L_W_XS, /* 8331 */ IC_VEX_L_W_XD, /* 8332 */ IC_VEX_L_W_XD, /* 8333 */ IC_VEX_L_W_XD, /* 8334 */ IC_VEX_L_W_XD, /* 8335 */ IC_VEX_L_OPSIZE, /* 8336 */ IC_VEX_L_OPSIZE, /* 8337 */ IC_VEX_L_OPSIZE, /* 8338 */ IC_VEX_L_OPSIZE, /* 8339 */ IC_VEX_L_OPSIZE, /* 8340 */ IC_VEX_L_OPSIZE, /* 8341 */ IC_VEX_L_OPSIZE, /* 8342 */ IC_VEX_L_OPSIZE, /* 8343 */ IC_VEX_L_W_OPSIZE, /* 8344 */ IC_VEX_L_W_OPSIZE, /* 8345 */ IC_VEX_L_W_OPSIZE, /* 8346 */ IC_VEX_L_W_OPSIZE, /* 8347 */ IC_VEX_L_W_OPSIZE, /* 8348 */ IC_VEX_L_W_OPSIZE, /* 8349 */ IC_VEX_L_W_OPSIZE, /* 8350 */ IC_VEX_L_W_OPSIZE, /* 8351 */ IC_VEX_L, /* 8352 */ IC_VEX_L, /* 8353 */ IC_VEX_L_XS, /* 8354 */ IC_VEX_L_XS, /* 8355 */ IC_VEX_L_XD, /* 8356 */ IC_VEX_L_XD, /* 8357 */ IC_VEX_L_XD, /* 8358 */ IC_VEX_L_XD, /* 8359 */ IC_VEX_L_W, /* 8360 */ IC_VEX_L_W, /* 8361 */ IC_VEX_L_W_XS, /* 8362 */ IC_VEX_L_W_XS, /* 8363 */ IC_VEX_L_W_XD, /* 8364 */ IC_VEX_L_W_XD, /* 8365 */ IC_VEX_L_W_XD, /* 8366 */ IC_VEX_L_W_XD, /* 8367 */ IC_VEX_L_OPSIZE, /* 8368 */ IC_VEX_L_OPSIZE, /* 8369 */ IC_VEX_L_OPSIZE, /* 8370 */ IC_VEX_L_OPSIZE, /* 8371 */ IC_VEX_L_OPSIZE, /* 8372 */ IC_VEX_L_OPSIZE, /* 8373 */ IC_VEX_L_OPSIZE, /* 8374 */ IC_VEX_L_OPSIZE, /* 8375 */ IC_VEX_L_W_OPSIZE, /* 8376 */ IC_VEX_L_W_OPSIZE, /* 8377 */ IC_VEX_L_W_OPSIZE, /* 8378 */ IC_VEX_L_W_OPSIZE, /* 8379 */ IC_VEX_L_W_OPSIZE, /* 8380 */ IC_VEX_L_W_OPSIZE, /* 8381 */ IC_VEX_L_W_OPSIZE, /* 8382 */ IC_VEX_L_W_OPSIZE, /* 8383 */ IC_VEX_L, /* 8384 */ IC_VEX_L, /* 8385 */ IC_VEX_L_XS, /* 8386 */ IC_VEX_L_XS, /* 8387 */ IC_VEX_L_XD, /* 8388 */ IC_VEX_L_XD, /* 8389 */ IC_VEX_L_XD, /* 8390 */ IC_VEX_L_XD, /* 8391 */ IC_VEX_L_W, /* 8392 */ IC_VEX_L_W, /* 8393 */ IC_VEX_L_W_XS, /* 8394 */ IC_VEX_L_W_XS, /* 8395 */ IC_VEX_L_W_XD, /* 8396 */ IC_VEX_L_W_XD, /* 8397 */ IC_VEX_L_W_XD, /* 8398 */ IC_VEX_L_W_XD, /* 8399 */ IC_VEX_L_OPSIZE, /* 8400 */ IC_VEX_L_OPSIZE, /* 8401 */ IC_VEX_L_OPSIZE, /* 8402 */ IC_VEX_L_OPSIZE, /* 8403 */ IC_VEX_L_OPSIZE, /* 8404 */ IC_VEX_L_OPSIZE, /* 8405 */ IC_VEX_L_OPSIZE, /* 8406 */ IC_VEX_L_OPSIZE, /* 8407 */ IC_VEX_L_W_OPSIZE, /* 8408 */ IC_VEX_L_W_OPSIZE, /* 8409 */ IC_VEX_L_W_OPSIZE, /* 8410 */ IC_VEX_L_W_OPSIZE, /* 8411 */ IC_VEX_L_W_OPSIZE, /* 8412 */ IC_VEX_L_W_OPSIZE, /* 8413 */ IC_VEX_L_W_OPSIZE, /* 8414 */ IC_VEX_L_W_OPSIZE, /* 8415 */ IC_VEX_L, /* 8416 */ IC_VEX_L, /* 8417 */ IC_VEX_L_XS, /* 8418 */ IC_VEX_L_XS, /* 8419 */ IC_VEX_L_XD, /* 8420 */ IC_VEX_L_XD, /* 8421 */ IC_VEX_L_XD, /* 8422 */ IC_VEX_L_XD, /* 8423 */ IC_VEX_L_W, /* 8424 */ IC_VEX_L_W, /* 8425 */ IC_VEX_L_W_XS, /* 8426 */ IC_VEX_L_W_XS, /* 8427 */ IC_VEX_L_W_XD, /* 8428 */ IC_VEX_L_W_XD, /* 8429 */ IC_VEX_L_W_XD, /* 8430 */ IC_VEX_L_W_XD, /* 8431 */ IC_VEX_L_OPSIZE, /* 8432 */ IC_VEX_L_OPSIZE, /* 8433 */ IC_VEX_L_OPSIZE, /* 8434 */ IC_VEX_L_OPSIZE, /* 8435 */ IC_VEX_L_OPSIZE, /* 8436 */ IC_VEX_L_OPSIZE, /* 8437 */ IC_VEX_L_OPSIZE, /* 8438 */ IC_VEX_L_OPSIZE, /* 8439 */ IC_VEX_L_W_OPSIZE, /* 8440 */ IC_VEX_L_W_OPSIZE, /* 8441 */ IC_VEX_L_W_OPSIZE, /* 8442 */ IC_VEX_L_W_OPSIZE, /* 8443 */ IC_VEX_L_W_OPSIZE, /* 8444 */ IC_VEX_L_W_OPSIZE, /* 8445 */ IC_VEX_L_W_OPSIZE, /* 8446 */ IC_VEX_L_W_OPSIZE, /* 8447 */ IC_EVEX_B, /* 8448 */ IC_EVEX_B, /* 8449 */ IC_EVEX_XS_B, /* 8450 */ IC_EVEX_XS_B, /* 8451 */ IC_EVEX_XD_B, /* 8452 */ IC_EVEX_XD_B, /* 8453 */ IC_EVEX_XD_B, /* 8454 */ IC_EVEX_XD_B, /* 8455 */ IC_EVEX_W_B, /* 8456 */ IC_EVEX_W_B, /* 8457 */ IC_EVEX_W_XS_B, /* 8458 */ IC_EVEX_W_XS_B, /* 8459 */ IC_EVEX_W_XD_B, /* 8460 */ IC_EVEX_W_XD_B, /* 8461 */ IC_EVEX_W_XD_B, /* 8462 */ IC_EVEX_W_XD_B, /* 8463 */ IC_EVEX_OPSIZE_B, /* 8464 */ IC_EVEX_OPSIZE_B, /* 8465 */ IC_EVEX_OPSIZE_B, /* 8466 */ IC_EVEX_OPSIZE_B, /* 8467 */ IC_EVEX_OPSIZE_B, /* 8468 */ IC_EVEX_OPSIZE_B, /* 8469 */ IC_EVEX_OPSIZE_B, /* 8470 */ IC_EVEX_OPSIZE_B, /* 8471 */ IC_EVEX_W_OPSIZE_B, /* 8472 */ IC_EVEX_W_OPSIZE_B, /* 8473 */ IC_EVEX_W_OPSIZE_B, /* 8474 */ IC_EVEX_W_OPSIZE_B, /* 8475 */ IC_EVEX_W_OPSIZE_B, /* 8476 */ IC_EVEX_W_OPSIZE_B, /* 8477 */ IC_EVEX_W_OPSIZE_B, /* 8478 */ IC_EVEX_W_OPSIZE_B, /* 8479 */ IC_EVEX_B, /* 8480 */ IC_EVEX_B, /* 8481 */ IC_EVEX_XS_B, /* 8482 */ IC_EVEX_XS_B, /* 8483 */ IC_EVEX_XD_B, /* 8484 */ IC_EVEX_XD_B, /* 8485 */ IC_EVEX_XD_B, /* 8486 */ IC_EVEX_XD_B, /* 8487 */ IC_EVEX_W_B, /* 8488 */ IC_EVEX_W_B, /* 8489 */ IC_EVEX_W_XS_B, /* 8490 */ IC_EVEX_W_XS_B, /* 8491 */ IC_EVEX_W_XD_B, /* 8492 */ IC_EVEX_W_XD_B, /* 8493 */ IC_EVEX_W_XD_B, /* 8494 */ IC_EVEX_W_XD_B, /* 8495 */ IC_EVEX_OPSIZE_B, /* 8496 */ IC_EVEX_OPSIZE_B, /* 8497 */ IC_EVEX_OPSIZE_B, /* 8498 */ IC_EVEX_OPSIZE_B, /* 8499 */ IC_EVEX_OPSIZE_B, /* 8500 */ IC_EVEX_OPSIZE_B, /* 8501 */ IC_EVEX_OPSIZE_B, /* 8502 */ IC_EVEX_OPSIZE_B, /* 8503 */ IC_EVEX_W_OPSIZE_B, /* 8504 */ IC_EVEX_W_OPSIZE_B, /* 8505 */ IC_EVEX_W_OPSIZE_B, /* 8506 */ IC_EVEX_W_OPSIZE_B, /* 8507 */ IC_EVEX_W_OPSIZE_B, /* 8508 */ IC_EVEX_W_OPSIZE_B, /* 8509 */ IC_EVEX_W_OPSIZE_B, /* 8510 */ IC_EVEX_W_OPSIZE_B, /* 8511 */ IC_EVEX_B, /* 8512 */ IC_EVEX_B, /* 8513 */ IC_EVEX_XS_B, /* 8514 */ IC_EVEX_XS_B, /* 8515 */ IC_EVEX_XD_B, /* 8516 */ IC_EVEX_XD_B, /* 8517 */ IC_EVEX_XD_B, /* 8518 */ IC_EVEX_XD_B, /* 8519 */ IC_EVEX_W_B, /* 8520 */ IC_EVEX_W_B, /* 8521 */ IC_EVEX_W_XS_B, /* 8522 */ IC_EVEX_W_XS_B, /* 8523 */ IC_EVEX_W_XD_B, /* 8524 */ IC_EVEX_W_XD_B, /* 8525 */ IC_EVEX_W_XD_B, /* 8526 */ IC_EVEX_W_XD_B, /* 8527 */ IC_EVEX_OPSIZE_B, /* 8528 */ IC_EVEX_OPSIZE_B, /* 8529 */ IC_EVEX_OPSIZE_B, /* 8530 */ IC_EVEX_OPSIZE_B, /* 8531 */ IC_EVEX_OPSIZE_B, /* 8532 */ IC_EVEX_OPSIZE_B, /* 8533 */ IC_EVEX_OPSIZE_B, /* 8534 */ IC_EVEX_OPSIZE_B, /* 8535 */ IC_EVEX_W_OPSIZE_B, /* 8536 */ IC_EVEX_W_OPSIZE_B, /* 8537 */ IC_EVEX_W_OPSIZE_B, /* 8538 */ IC_EVEX_W_OPSIZE_B, /* 8539 */ IC_EVEX_W_OPSIZE_B, /* 8540 */ IC_EVEX_W_OPSIZE_B, /* 8541 */ IC_EVEX_W_OPSIZE_B, /* 8542 */ IC_EVEX_W_OPSIZE_B, /* 8543 */ IC_EVEX_B, /* 8544 */ IC_EVEX_B, /* 8545 */ IC_EVEX_XS_B, /* 8546 */ IC_EVEX_XS_B, /* 8547 */ IC_EVEX_XD_B, /* 8548 */ IC_EVEX_XD_B, /* 8549 */ IC_EVEX_XD_B, /* 8550 */ IC_EVEX_XD_B, /* 8551 */ IC_EVEX_W_B, /* 8552 */ IC_EVEX_W_B, /* 8553 */ IC_EVEX_W_XS_B, /* 8554 */ IC_EVEX_W_XS_B, /* 8555 */ IC_EVEX_W_XD_B, /* 8556 */ IC_EVEX_W_XD_B, /* 8557 */ IC_EVEX_W_XD_B, /* 8558 */ IC_EVEX_W_XD_B, /* 8559 */ IC_EVEX_OPSIZE_B, /* 8560 */ IC_EVEX_OPSIZE_B, /* 8561 */ IC_EVEX_OPSIZE_B, /* 8562 */ IC_EVEX_OPSIZE_B, /* 8563 */ IC_EVEX_OPSIZE_B, /* 8564 */ IC_EVEX_OPSIZE_B, /* 8565 */ IC_EVEX_OPSIZE_B, /* 8566 */ IC_EVEX_OPSIZE_B, /* 8567 */ IC_EVEX_W_OPSIZE_B, /* 8568 */ IC_EVEX_W_OPSIZE_B, /* 8569 */ IC_EVEX_W_OPSIZE_B, /* 8570 */ IC_EVEX_W_OPSIZE_B, /* 8571 */ IC_EVEX_W_OPSIZE_B, /* 8572 */ IC_EVEX_W_OPSIZE_B, /* 8573 */ IC_EVEX_W_OPSIZE_B, /* 8574 */ IC_EVEX_W_OPSIZE_B, /* 8575 */ IC_EVEX_B, /* 8576 */ IC_EVEX_B, /* 8577 */ IC_EVEX_XS_B, /* 8578 */ IC_EVEX_XS_B, /* 8579 */ IC_EVEX_XD_B, /* 8580 */ IC_EVEX_XD_B, /* 8581 */ IC_EVEX_XD_B, /* 8582 */ IC_EVEX_XD_B, /* 8583 */ IC_EVEX_W_B, /* 8584 */ IC_EVEX_W_B, /* 8585 */ IC_EVEX_W_XS_B, /* 8586 */ IC_EVEX_W_XS_B, /* 8587 */ IC_EVEX_W_XD_B, /* 8588 */ IC_EVEX_W_XD_B, /* 8589 */ IC_EVEX_W_XD_B, /* 8590 */ IC_EVEX_W_XD_B, /* 8591 */ IC_EVEX_OPSIZE_B, /* 8592 */ IC_EVEX_OPSIZE_B, /* 8593 */ IC_EVEX_OPSIZE_B, /* 8594 */ IC_EVEX_OPSIZE_B, /* 8595 */ IC_EVEX_OPSIZE_B, /* 8596 */ IC_EVEX_OPSIZE_B, /* 8597 */ IC_EVEX_OPSIZE_B, /* 8598 */ IC_EVEX_OPSIZE_B, /* 8599 */ IC_EVEX_W_OPSIZE_B, /* 8600 */ IC_EVEX_W_OPSIZE_B, /* 8601 */ IC_EVEX_W_OPSIZE_B, /* 8602 */ IC_EVEX_W_OPSIZE_B, /* 8603 */ IC_EVEX_W_OPSIZE_B, /* 8604 */ IC_EVEX_W_OPSIZE_B, /* 8605 */ IC_EVEX_W_OPSIZE_B, /* 8606 */ IC_EVEX_W_OPSIZE_B, /* 8607 */ IC_EVEX_B, /* 8608 */ IC_EVEX_B, /* 8609 */ IC_EVEX_XS_B, /* 8610 */ IC_EVEX_XS_B, /* 8611 */ IC_EVEX_XD_B, /* 8612 */ IC_EVEX_XD_B, /* 8613 */ IC_EVEX_XD_B, /* 8614 */ IC_EVEX_XD_B, /* 8615 */ IC_EVEX_W_B, /* 8616 */ IC_EVEX_W_B, /* 8617 */ IC_EVEX_W_XS_B, /* 8618 */ IC_EVEX_W_XS_B, /* 8619 */ IC_EVEX_W_XD_B, /* 8620 */ IC_EVEX_W_XD_B, /* 8621 */ IC_EVEX_W_XD_B, /* 8622 */ IC_EVEX_W_XD_B, /* 8623 */ IC_EVEX_OPSIZE_B, /* 8624 */ IC_EVEX_OPSIZE_B, /* 8625 */ IC_EVEX_OPSIZE_B, /* 8626 */ IC_EVEX_OPSIZE_B, /* 8627 */ IC_EVEX_OPSIZE_B, /* 8628 */ IC_EVEX_OPSIZE_B, /* 8629 */ IC_EVEX_OPSIZE_B, /* 8630 */ IC_EVEX_OPSIZE_B, /* 8631 */ IC_EVEX_W_OPSIZE_B, /* 8632 */ IC_EVEX_W_OPSIZE_B, /* 8633 */ IC_EVEX_W_OPSIZE_B, /* 8634 */ IC_EVEX_W_OPSIZE_B, /* 8635 */ IC_EVEX_W_OPSIZE_B, /* 8636 */ IC_EVEX_W_OPSIZE_B, /* 8637 */ IC_EVEX_W_OPSIZE_B, /* 8638 */ IC_EVEX_W_OPSIZE_B, /* 8639 */ IC_EVEX_B, /* 8640 */ IC_EVEX_B, /* 8641 */ IC_EVEX_XS_B, /* 8642 */ IC_EVEX_XS_B, /* 8643 */ IC_EVEX_XD_B, /* 8644 */ IC_EVEX_XD_B, /* 8645 */ IC_EVEX_XD_B, /* 8646 */ IC_EVEX_XD_B, /* 8647 */ IC_EVEX_W_B, /* 8648 */ IC_EVEX_W_B, /* 8649 */ IC_EVEX_W_XS_B, /* 8650 */ IC_EVEX_W_XS_B, /* 8651 */ IC_EVEX_W_XD_B, /* 8652 */ IC_EVEX_W_XD_B, /* 8653 */ IC_EVEX_W_XD_B, /* 8654 */ IC_EVEX_W_XD_B, /* 8655 */ IC_EVEX_OPSIZE_B, /* 8656 */ IC_EVEX_OPSIZE_B, /* 8657 */ IC_EVEX_OPSIZE_B, /* 8658 */ IC_EVEX_OPSIZE_B, /* 8659 */ IC_EVEX_OPSIZE_B, /* 8660 */ IC_EVEX_OPSIZE_B, /* 8661 */ IC_EVEX_OPSIZE_B, /* 8662 */ IC_EVEX_OPSIZE_B, /* 8663 */ IC_EVEX_W_OPSIZE_B, /* 8664 */ IC_EVEX_W_OPSIZE_B, /* 8665 */ IC_EVEX_W_OPSIZE_B, /* 8666 */ IC_EVEX_W_OPSIZE_B, /* 8667 */ IC_EVEX_W_OPSIZE_B, /* 8668 */ IC_EVEX_W_OPSIZE_B, /* 8669 */ IC_EVEX_W_OPSIZE_B, /* 8670 */ IC_EVEX_W_OPSIZE_B, /* 8671 */ IC_EVEX_B, /* 8672 */ IC_EVEX_B, /* 8673 */ IC_EVEX_XS_B, /* 8674 */ IC_EVEX_XS_B, /* 8675 */ IC_EVEX_XD_B, /* 8676 */ IC_EVEX_XD_B, /* 8677 */ IC_EVEX_XD_B, /* 8678 */ IC_EVEX_XD_B, /* 8679 */ IC_EVEX_W_B, /* 8680 */ IC_EVEX_W_B, /* 8681 */ IC_EVEX_W_XS_B, /* 8682 */ IC_EVEX_W_XS_B, /* 8683 */ IC_EVEX_W_XD_B, /* 8684 */ IC_EVEX_W_XD_B, /* 8685 */ IC_EVEX_W_XD_B, /* 8686 */ IC_EVEX_W_XD_B, /* 8687 */ IC_EVEX_OPSIZE_B, /* 8688 */ IC_EVEX_OPSIZE_B, /* 8689 */ IC_EVEX_OPSIZE_B, /* 8690 */ IC_EVEX_OPSIZE_B, /* 8691 */ IC_EVEX_OPSIZE_B, /* 8692 */ IC_EVEX_OPSIZE_B, /* 8693 */ IC_EVEX_OPSIZE_B, /* 8694 */ IC_EVEX_OPSIZE_B, /* 8695 */ IC_EVEX_W_OPSIZE_B, /* 8696 */ IC_EVEX_W_OPSIZE_B, /* 8697 */ IC_EVEX_W_OPSIZE_B, /* 8698 */ IC_EVEX_W_OPSIZE_B, /* 8699 */ IC_EVEX_W_OPSIZE_B, /* 8700 */ IC_EVEX_W_OPSIZE_B, /* 8701 */ IC_EVEX_W_OPSIZE_B, /* 8702 */ IC_EVEX_W_OPSIZE_B, /* 8703 */ IC, /* 8704 */ IC_64BIT, /* 8705 */ IC_XS, /* 8706 */ IC_64BIT_XS, /* 8707 */ IC_XD, /* 8708 */ IC_64BIT_XD, /* 8709 */ IC_XS, /* 8710 */ IC_64BIT_XS, /* 8711 */ IC, /* 8712 */ IC_64BIT_REXW, /* 8713 */ IC_XS, /* 8714 */ IC_64BIT_REXW_XS, /* 8715 */ IC_XD, /* 8716 */ IC_64BIT_REXW_XD, /* 8717 */ IC_XS, /* 8718 */ IC_64BIT_REXW_XS, /* 8719 */ IC_OPSIZE, /* 8720 */ IC_64BIT_OPSIZE, /* 8721 */ IC_XS_OPSIZE, /* 8722 */ IC_64BIT_XS_OPSIZE, /* 8723 */ IC_XD_OPSIZE, /* 8724 */ IC_64BIT_XD_OPSIZE, /* 8725 */ IC_XS_OPSIZE, /* 8726 */ IC_64BIT_XD_OPSIZE, /* 8727 */ IC_OPSIZE, /* 8728 */ IC_64BIT_REXW_OPSIZE, /* 8729 */ IC_XS_OPSIZE, /* 8730 */ IC_64BIT_REXW_XS, /* 8731 */ IC_XD_OPSIZE, /* 8732 */ IC_64BIT_REXW_XD, /* 8733 */ IC_XS_OPSIZE, /* 8734 */ IC_64BIT_REXW_XS, /* 8735 */ IC_ADSIZE, /* 8736 */ IC_64BIT_ADSIZE, /* 8737 */ IC_XS_ADSIZE, /* 8738 */ IC_64BIT_XS_ADSIZE, /* 8739 */ IC_XD_ADSIZE, /* 8740 */ IC_64BIT_XD_ADSIZE, /* 8741 */ IC_XS_ADSIZE, /* 8742 */ IC_64BIT_XD_ADSIZE, /* 8743 */ IC_ADSIZE, /* 8744 */ IC_64BIT_REXW_ADSIZE, /* 8745 */ IC_XS_ADSIZE, /* 8746 */ IC_64BIT_REXW_XS, /* 8747 */ IC_XD_ADSIZE, /* 8748 */ IC_64BIT_REXW_XD, /* 8749 */ IC_XS_ADSIZE, /* 8750 */ IC_64BIT_REXW_XS, /* 8751 */ IC_OPSIZE_ADSIZE, /* 8752 */ IC_64BIT_OPSIZE_ADSIZE, /* 8753 */ IC_XS_OPSIZE, /* 8754 */ IC_64BIT_XS_OPSIZE, /* 8755 */ IC_XD_OPSIZE, /* 8756 */ IC_64BIT_XD_OPSIZE, /* 8757 */ IC_XS_OPSIZE, /* 8758 */ IC_64BIT_XD_OPSIZE, /* 8759 */ IC_OPSIZE_ADSIZE, /* 8760 */ IC_64BIT_REXW_OPSIZE, /* 8761 */ IC_XS_OPSIZE, /* 8762 */ IC_64BIT_REXW_XS, /* 8763 */ IC_XD_OPSIZE, /* 8764 */ IC_64BIT_REXW_XD, /* 8765 */ IC_XS_OPSIZE, /* 8766 */ IC_64BIT_REXW_XS, /* 8767 */ IC_VEX, /* 8768 */ IC_VEX, /* 8769 */ IC_VEX_XS, /* 8770 */ IC_VEX_XS, /* 8771 */ IC_VEX_XD, /* 8772 */ IC_VEX_XD, /* 8773 */ IC_VEX_XD, /* 8774 */ IC_VEX_XD, /* 8775 */ IC_VEX_W, /* 8776 */ IC_VEX_W, /* 8777 */ IC_VEX_W_XS, /* 8778 */ IC_VEX_W_XS, /* 8779 */ IC_VEX_W_XD, /* 8780 */ IC_VEX_W_XD, /* 8781 */ IC_VEX_W_XD, /* 8782 */ IC_VEX_W_XD, /* 8783 */ IC_VEX_OPSIZE, /* 8784 */ IC_VEX_OPSIZE, /* 8785 */ IC_VEX_OPSIZE, /* 8786 */ IC_VEX_OPSIZE, /* 8787 */ IC_VEX_OPSIZE, /* 8788 */ IC_VEX_OPSIZE, /* 8789 */ IC_VEX_OPSIZE, /* 8790 */ IC_VEX_OPSIZE, /* 8791 */ IC_VEX_W_OPSIZE, /* 8792 */ IC_VEX_W_OPSIZE, /* 8793 */ IC_VEX_W_OPSIZE, /* 8794 */ IC_VEX_W_OPSIZE, /* 8795 */ IC_VEX_W_OPSIZE, /* 8796 */ IC_VEX_W_OPSIZE, /* 8797 */ IC_VEX_W_OPSIZE, /* 8798 */ IC_VEX_W_OPSIZE, /* 8799 */ IC_VEX, /* 8800 */ IC_VEX, /* 8801 */ IC_VEX_XS, /* 8802 */ IC_VEX_XS, /* 8803 */ IC_VEX_XD, /* 8804 */ IC_VEX_XD, /* 8805 */ IC_VEX_XD, /* 8806 */ IC_VEX_XD, /* 8807 */ IC_VEX_W, /* 8808 */ IC_VEX_W, /* 8809 */ IC_VEX_W_XS, /* 8810 */ IC_VEX_W_XS, /* 8811 */ IC_VEX_W_XD, /* 8812 */ IC_VEX_W_XD, /* 8813 */ IC_VEX_W_XD, /* 8814 */ IC_VEX_W_XD, /* 8815 */ IC_VEX_OPSIZE, /* 8816 */ IC_VEX_OPSIZE, /* 8817 */ IC_VEX_OPSIZE, /* 8818 */ IC_VEX_OPSIZE, /* 8819 */ IC_VEX_OPSIZE, /* 8820 */ IC_VEX_OPSIZE, /* 8821 */ IC_VEX_OPSIZE, /* 8822 */ IC_VEX_OPSIZE, /* 8823 */ IC_VEX_W_OPSIZE, /* 8824 */ IC_VEX_W_OPSIZE, /* 8825 */ IC_VEX_W_OPSIZE, /* 8826 */ IC_VEX_W_OPSIZE, /* 8827 */ IC_VEX_W_OPSIZE, /* 8828 */ IC_VEX_W_OPSIZE, /* 8829 */ IC_VEX_W_OPSIZE, /* 8830 */ IC_VEX_W_OPSIZE, /* 8831 */ IC_VEX_L, /* 8832 */ IC_VEX_L, /* 8833 */ IC_VEX_L_XS, /* 8834 */ IC_VEX_L_XS, /* 8835 */ IC_VEX_L_XD, /* 8836 */ IC_VEX_L_XD, /* 8837 */ IC_VEX_L_XD, /* 8838 */ IC_VEX_L_XD, /* 8839 */ IC_VEX_L_W, /* 8840 */ IC_VEX_L_W, /* 8841 */ IC_VEX_L_W_XS, /* 8842 */ IC_VEX_L_W_XS, /* 8843 */ IC_VEX_L_W_XD, /* 8844 */ IC_VEX_L_W_XD, /* 8845 */ IC_VEX_L_W_XD, /* 8846 */ IC_VEX_L_W_XD, /* 8847 */ IC_VEX_L_OPSIZE, /* 8848 */ IC_VEX_L_OPSIZE, /* 8849 */ IC_VEX_L_OPSIZE, /* 8850 */ IC_VEX_L_OPSIZE, /* 8851 */ IC_VEX_L_OPSIZE, /* 8852 */ IC_VEX_L_OPSIZE, /* 8853 */ IC_VEX_L_OPSIZE, /* 8854 */ IC_VEX_L_OPSIZE, /* 8855 */ IC_VEX_L_W_OPSIZE, /* 8856 */ IC_VEX_L_W_OPSIZE, /* 8857 */ IC_VEX_L_W_OPSIZE, /* 8858 */ IC_VEX_L_W_OPSIZE, /* 8859 */ IC_VEX_L_W_OPSIZE, /* 8860 */ IC_VEX_L_W_OPSIZE, /* 8861 */ IC_VEX_L_W_OPSIZE, /* 8862 */ IC_VEX_L_W_OPSIZE, /* 8863 */ IC_VEX_L, /* 8864 */ IC_VEX_L, /* 8865 */ IC_VEX_L_XS, /* 8866 */ IC_VEX_L_XS, /* 8867 */ IC_VEX_L_XD, /* 8868 */ IC_VEX_L_XD, /* 8869 */ IC_VEX_L_XD, /* 8870 */ IC_VEX_L_XD, /* 8871 */ IC_VEX_L_W, /* 8872 */ IC_VEX_L_W, /* 8873 */ IC_VEX_L_W_XS, /* 8874 */ IC_VEX_L_W_XS, /* 8875 */ IC_VEX_L_W_XD, /* 8876 */ IC_VEX_L_W_XD, /* 8877 */ IC_VEX_L_W_XD, /* 8878 */ IC_VEX_L_W_XD, /* 8879 */ IC_VEX_L_OPSIZE, /* 8880 */ IC_VEX_L_OPSIZE, /* 8881 */ IC_VEX_L_OPSIZE, /* 8882 */ IC_VEX_L_OPSIZE, /* 8883 */ IC_VEX_L_OPSIZE, /* 8884 */ IC_VEX_L_OPSIZE, /* 8885 */ IC_VEX_L_OPSIZE, /* 8886 */ IC_VEX_L_OPSIZE, /* 8887 */ IC_VEX_L_W_OPSIZE, /* 8888 */ IC_VEX_L_W_OPSIZE, /* 8889 */ IC_VEX_L_W_OPSIZE, /* 8890 */ IC_VEX_L_W_OPSIZE, /* 8891 */ IC_VEX_L_W_OPSIZE, /* 8892 */ IC_VEX_L_W_OPSIZE, /* 8893 */ IC_VEX_L_W_OPSIZE, /* 8894 */ IC_VEX_L_W_OPSIZE, /* 8895 */ IC_VEX_L, /* 8896 */ IC_VEX_L, /* 8897 */ IC_VEX_L_XS, /* 8898 */ IC_VEX_L_XS, /* 8899 */ IC_VEX_L_XD, /* 8900 */ IC_VEX_L_XD, /* 8901 */ IC_VEX_L_XD, /* 8902 */ IC_VEX_L_XD, /* 8903 */ IC_VEX_L_W, /* 8904 */ IC_VEX_L_W, /* 8905 */ IC_VEX_L_W_XS, /* 8906 */ IC_VEX_L_W_XS, /* 8907 */ IC_VEX_L_W_XD, /* 8908 */ IC_VEX_L_W_XD, /* 8909 */ IC_VEX_L_W_XD, /* 8910 */ IC_VEX_L_W_XD, /* 8911 */ IC_VEX_L_OPSIZE, /* 8912 */ IC_VEX_L_OPSIZE, /* 8913 */ IC_VEX_L_OPSIZE, /* 8914 */ IC_VEX_L_OPSIZE, /* 8915 */ IC_VEX_L_OPSIZE, /* 8916 */ IC_VEX_L_OPSIZE, /* 8917 */ IC_VEX_L_OPSIZE, /* 8918 */ IC_VEX_L_OPSIZE, /* 8919 */ IC_VEX_L_W_OPSIZE, /* 8920 */ IC_VEX_L_W_OPSIZE, /* 8921 */ IC_VEX_L_W_OPSIZE, /* 8922 */ IC_VEX_L_W_OPSIZE, /* 8923 */ IC_VEX_L_W_OPSIZE, /* 8924 */ IC_VEX_L_W_OPSIZE, /* 8925 */ IC_VEX_L_W_OPSIZE, /* 8926 */ IC_VEX_L_W_OPSIZE, /* 8927 */ IC_VEX_L, /* 8928 */ IC_VEX_L, /* 8929 */ IC_VEX_L_XS, /* 8930 */ IC_VEX_L_XS, /* 8931 */ IC_VEX_L_XD, /* 8932 */ IC_VEX_L_XD, /* 8933 */ IC_VEX_L_XD, /* 8934 */ IC_VEX_L_XD, /* 8935 */ IC_VEX_L_W, /* 8936 */ IC_VEX_L_W, /* 8937 */ IC_VEX_L_W_XS, /* 8938 */ IC_VEX_L_W_XS, /* 8939 */ IC_VEX_L_W_XD, /* 8940 */ IC_VEX_L_W_XD, /* 8941 */ IC_VEX_L_W_XD, /* 8942 */ IC_VEX_L_W_XD, /* 8943 */ IC_VEX_L_OPSIZE, /* 8944 */ IC_VEX_L_OPSIZE, /* 8945 */ IC_VEX_L_OPSIZE, /* 8946 */ IC_VEX_L_OPSIZE, /* 8947 */ IC_VEX_L_OPSIZE, /* 8948 */ IC_VEX_L_OPSIZE, /* 8949 */ IC_VEX_L_OPSIZE, /* 8950 */ IC_VEX_L_OPSIZE, /* 8951 */ IC_VEX_L_W_OPSIZE, /* 8952 */ IC_VEX_L_W_OPSIZE, /* 8953 */ IC_VEX_L_W_OPSIZE, /* 8954 */ IC_VEX_L_W_OPSIZE, /* 8955 */ IC_VEX_L_W_OPSIZE, /* 8956 */ IC_VEX_L_W_OPSIZE, /* 8957 */ IC_VEX_L_W_OPSIZE, /* 8958 */ IC_VEX_L_W_OPSIZE, /* 8959 */ IC_EVEX_L_B, /* 8960 */ IC_EVEX_L_B, /* 8961 */ IC_EVEX_L_XS_B, /* 8962 */ IC_EVEX_L_XS_B, /* 8963 */ IC_EVEX_L_XD_B, /* 8964 */ IC_EVEX_L_XD_B, /* 8965 */ IC_EVEX_L_XD_B, /* 8966 */ IC_EVEX_L_XD_B, /* 8967 */ IC_EVEX_L_W_B, /* 8968 */ IC_EVEX_L_W_B, /* 8969 */ IC_EVEX_L_W_XS_B, /* 8970 */ IC_EVEX_L_W_XS_B, /* 8971 */ IC_EVEX_L_W_XD_B, /* 8972 */ IC_EVEX_L_W_XD_B, /* 8973 */ IC_EVEX_L_W_XD_B, /* 8974 */ IC_EVEX_L_W_XD_B, /* 8975 */ IC_EVEX_L_OPSIZE_B, /* 8976 */ IC_EVEX_L_OPSIZE_B, /* 8977 */ IC_EVEX_L_OPSIZE_B, /* 8978 */ IC_EVEX_L_OPSIZE_B, /* 8979 */ IC_EVEX_L_OPSIZE_B, /* 8980 */ IC_EVEX_L_OPSIZE_B, /* 8981 */ IC_EVEX_L_OPSIZE_B, /* 8982 */ IC_EVEX_L_OPSIZE_B, /* 8983 */ IC_EVEX_L_W_OPSIZE_B, /* 8984 */ IC_EVEX_L_W_OPSIZE_B, /* 8985 */ IC_EVEX_L_W_OPSIZE_B, /* 8986 */ IC_EVEX_L_W_OPSIZE_B, /* 8987 */ IC_EVEX_L_W_OPSIZE_B, /* 8988 */ IC_EVEX_L_W_OPSIZE_B, /* 8989 */ IC_EVEX_L_W_OPSIZE_B, /* 8990 */ IC_EVEX_L_W_OPSIZE_B, /* 8991 */ IC_EVEX_L_B, /* 8992 */ IC_EVEX_L_B, /* 8993 */ IC_EVEX_L_XS_B, /* 8994 */ IC_EVEX_L_XS_B, /* 8995 */ IC_EVEX_L_XD_B, /* 8996 */ IC_EVEX_L_XD_B, /* 8997 */ IC_EVEX_L_XD_B, /* 8998 */ IC_EVEX_L_XD_B, /* 8999 */ IC_EVEX_L_W_B, /* 9000 */ IC_EVEX_L_W_B, /* 9001 */ IC_EVEX_L_W_XS_B, /* 9002 */ IC_EVEX_L_W_XS_B, /* 9003 */ IC_EVEX_L_W_XD_B, /* 9004 */ IC_EVEX_L_W_XD_B, /* 9005 */ IC_EVEX_L_W_XD_B, /* 9006 */ IC_EVEX_L_W_XD_B, /* 9007 */ IC_EVEX_L_OPSIZE_B, /* 9008 */ IC_EVEX_L_OPSIZE_B, /* 9009 */ IC_EVEX_L_OPSIZE_B, /* 9010 */ IC_EVEX_L_OPSIZE_B, /* 9011 */ IC_EVEX_L_OPSIZE_B, /* 9012 */ IC_EVEX_L_OPSIZE_B, /* 9013 */ IC_EVEX_L_OPSIZE_B, /* 9014 */ IC_EVEX_L_OPSIZE_B, /* 9015 */ IC_EVEX_L_W_OPSIZE_B, /* 9016 */ IC_EVEX_L_W_OPSIZE_B, /* 9017 */ IC_EVEX_L_W_OPSIZE_B, /* 9018 */ IC_EVEX_L_W_OPSIZE_B, /* 9019 */ IC_EVEX_L_W_OPSIZE_B, /* 9020 */ IC_EVEX_L_W_OPSIZE_B, /* 9021 */ IC_EVEX_L_W_OPSIZE_B, /* 9022 */ IC_EVEX_L_W_OPSIZE_B, /* 9023 */ IC_EVEX_L_B, /* 9024 */ IC_EVEX_L_B, /* 9025 */ IC_EVEX_L_XS_B, /* 9026 */ IC_EVEX_L_XS_B, /* 9027 */ IC_EVEX_L_XD_B, /* 9028 */ IC_EVEX_L_XD_B, /* 9029 */ IC_EVEX_L_XD_B, /* 9030 */ IC_EVEX_L_XD_B, /* 9031 */ IC_EVEX_L_W_B, /* 9032 */ IC_EVEX_L_W_B, /* 9033 */ IC_EVEX_L_W_XS_B, /* 9034 */ IC_EVEX_L_W_XS_B, /* 9035 */ IC_EVEX_L_W_XD_B, /* 9036 */ IC_EVEX_L_W_XD_B, /* 9037 */ IC_EVEX_L_W_XD_B, /* 9038 */ IC_EVEX_L_W_XD_B, /* 9039 */ IC_EVEX_L_OPSIZE_B, /* 9040 */ IC_EVEX_L_OPSIZE_B, /* 9041 */ IC_EVEX_L_OPSIZE_B, /* 9042 */ IC_EVEX_L_OPSIZE_B, /* 9043 */ IC_EVEX_L_OPSIZE_B, /* 9044 */ IC_EVEX_L_OPSIZE_B, /* 9045 */ IC_EVEX_L_OPSIZE_B, /* 9046 */ IC_EVEX_L_OPSIZE_B, /* 9047 */ IC_EVEX_L_W_OPSIZE_B, /* 9048 */ IC_EVEX_L_W_OPSIZE_B, /* 9049 */ IC_EVEX_L_W_OPSIZE_B, /* 9050 */ IC_EVEX_L_W_OPSIZE_B, /* 9051 */ IC_EVEX_L_W_OPSIZE_B, /* 9052 */ IC_EVEX_L_W_OPSIZE_B, /* 9053 */ IC_EVEX_L_W_OPSIZE_B, /* 9054 */ IC_EVEX_L_W_OPSIZE_B, /* 9055 */ IC_EVEX_L_B, /* 9056 */ IC_EVEX_L_B, /* 9057 */ IC_EVEX_L_XS_B, /* 9058 */ IC_EVEX_L_XS_B, /* 9059 */ IC_EVEX_L_XD_B, /* 9060 */ IC_EVEX_L_XD_B, /* 9061 */ IC_EVEX_L_XD_B, /* 9062 */ IC_EVEX_L_XD_B, /* 9063 */ IC_EVEX_L_W_B, /* 9064 */ IC_EVEX_L_W_B, /* 9065 */ IC_EVEX_L_W_XS_B, /* 9066 */ IC_EVEX_L_W_XS_B, /* 9067 */ IC_EVEX_L_W_XD_B, /* 9068 */ IC_EVEX_L_W_XD_B, /* 9069 */ IC_EVEX_L_W_XD_B, /* 9070 */ IC_EVEX_L_W_XD_B, /* 9071 */ IC_EVEX_L_OPSIZE_B, /* 9072 */ IC_EVEX_L_OPSIZE_B, /* 9073 */ IC_EVEX_L_OPSIZE_B, /* 9074 */ IC_EVEX_L_OPSIZE_B, /* 9075 */ IC_EVEX_L_OPSIZE_B, /* 9076 */ IC_EVEX_L_OPSIZE_B, /* 9077 */ IC_EVEX_L_OPSIZE_B, /* 9078 */ IC_EVEX_L_OPSIZE_B, /* 9079 */ IC_EVEX_L_W_OPSIZE_B, /* 9080 */ IC_EVEX_L_W_OPSIZE_B, /* 9081 */ IC_EVEX_L_W_OPSIZE_B, /* 9082 */ IC_EVEX_L_W_OPSIZE_B, /* 9083 */ IC_EVEX_L_W_OPSIZE_B, /* 9084 */ IC_EVEX_L_W_OPSIZE_B, /* 9085 */ IC_EVEX_L_W_OPSIZE_B, /* 9086 */ IC_EVEX_L_W_OPSIZE_B, /* 9087 */ IC_EVEX_L_B, /* 9088 */ IC_EVEX_L_B, /* 9089 */ IC_EVEX_L_XS_B, /* 9090 */ IC_EVEX_L_XS_B, /* 9091 */ IC_EVEX_L_XD_B, /* 9092 */ IC_EVEX_L_XD_B, /* 9093 */ IC_EVEX_L_XD_B, /* 9094 */ IC_EVEX_L_XD_B, /* 9095 */ IC_EVEX_L_W_B, /* 9096 */ IC_EVEX_L_W_B, /* 9097 */ IC_EVEX_L_W_XS_B, /* 9098 */ IC_EVEX_L_W_XS_B, /* 9099 */ IC_EVEX_L_W_XD_B, /* 9100 */ IC_EVEX_L_W_XD_B, /* 9101 */ IC_EVEX_L_W_XD_B, /* 9102 */ IC_EVEX_L_W_XD_B, /* 9103 */ IC_EVEX_L_OPSIZE_B, /* 9104 */ IC_EVEX_L_OPSIZE_B, /* 9105 */ IC_EVEX_L_OPSIZE_B, /* 9106 */ IC_EVEX_L_OPSIZE_B, /* 9107 */ IC_EVEX_L_OPSIZE_B, /* 9108 */ IC_EVEX_L_OPSIZE_B, /* 9109 */ IC_EVEX_L_OPSIZE_B, /* 9110 */ IC_EVEX_L_OPSIZE_B, /* 9111 */ IC_EVEX_L_W_OPSIZE_B, /* 9112 */ IC_EVEX_L_W_OPSIZE_B, /* 9113 */ IC_EVEX_L_W_OPSIZE_B, /* 9114 */ IC_EVEX_L_W_OPSIZE_B, /* 9115 */ IC_EVEX_L_W_OPSIZE_B, /* 9116 */ IC_EVEX_L_W_OPSIZE_B, /* 9117 */ IC_EVEX_L_W_OPSIZE_B, /* 9118 */ IC_EVEX_L_W_OPSIZE_B, /* 9119 */ IC_EVEX_L_B, /* 9120 */ IC_EVEX_L_B, /* 9121 */ IC_EVEX_L_XS_B, /* 9122 */ IC_EVEX_L_XS_B, /* 9123 */ IC_EVEX_L_XD_B, /* 9124 */ IC_EVEX_L_XD_B, /* 9125 */ IC_EVEX_L_XD_B, /* 9126 */ IC_EVEX_L_XD_B, /* 9127 */ IC_EVEX_L_W_B, /* 9128 */ IC_EVEX_L_W_B, /* 9129 */ IC_EVEX_L_W_XS_B, /* 9130 */ IC_EVEX_L_W_XS_B, /* 9131 */ IC_EVEX_L_W_XD_B, /* 9132 */ IC_EVEX_L_W_XD_B, /* 9133 */ IC_EVEX_L_W_XD_B, /* 9134 */ IC_EVEX_L_W_XD_B, /* 9135 */ IC_EVEX_L_OPSIZE_B, /* 9136 */ IC_EVEX_L_OPSIZE_B, /* 9137 */ IC_EVEX_L_OPSIZE_B, /* 9138 */ IC_EVEX_L_OPSIZE_B, /* 9139 */ IC_EVEX_L_OPSIZE_B, /* 9140 */ IC_EVEX_L_OPSIZE_B, /* 9141 */ IC_EVEX_L_OPSIZE_B, /* 9142 */ IC_EVEX_L_OPSIZE_B, /* 9143 */ IC_EVEX_L_W_OPSIZE_B, /* 9144 */ IC_EVEX_L_W_OPSIZE_B, /* 9145 */ IC_EVEX_L_W_OPSIZE_B, /* 9146 */ IC_EVEX_L_W_OPSIZE_B, /* 9147 */ IC_EVEX_L_W_OPSIZE_B, /* 9148 */ IC_EVEX_L_W_OPSIZE_B, /* 9149 */ IC_EVEX_L_W_OPSIZE_B, /* 9150 */ IC_EVEX_L_W_OPSIZE_B, /* 9151 */ IC_EVEX_L_B, /* 9152 */ IC_EVEX_L_B, /* 9153 */ IC_EVEX_L_XS_B, /* 9154 */ IC_EVEX_L_XS_B, /* 9155 */ IC_EVEX_L_XD_B, /* 9156 */ IC_EVEX_L_XD_B, /* 9157 */ IC_EVEX_L_XD_B, /* 9158 */ IC_EVEX_L_XD_B, /* 9159 */ IC_EVEX_L_W_B, /* 9160 */ IC_EVEX_L_W_B, /* 9161 */ IC_EVEX_L_W_XS_B, /* 9162 */ IC_EVEX_L_W_XS_B, /* 9163 */ IC_EVEX_L_W_XD_B, /* 9164 */ IC_EVEX_L_W_XD_B, /* 9165 */ IC_EVEX_L_W_XD_B, /* 9166 */ IC_EVEX_L_W_XD_B, /* 9167 */ IC_EVEX_L_OPSIZE_B, /* 9168 */ IC_EVEX_L_OPSIZE_B, /* 9169 */ IC_EVEX_L_OPSIZE_B, /* 9170 */ IC_EVEX_L_OPSIZE_B, /* 9171 */ IC_EVEX_L_OPSIZE_B, /* 9172 */ IC_EVEX_L_OPSIZE_B, /* 9173 */ IC_EVEX_L_OPSIZE_B, /* 9174 */ IC_EVEX_L_OPSIZE_B, /* 9175 */ IC_EVEX_L_W_OPSIZE_B, /* 9176 */ IC_EVEX_L_W_OPSIZE_B, /* 9177 */ IC_EVEX_L_W_OPSIZE_B, /* 9178 */ IC_EVEX_L_W_OPSIZE_B, /* 9179 */ IC_EVEX_L_W_OPSIZE_B, /* 9180 */ IC_EVEX_L_W_OPSIZE_B, /* 9181 */ IC_EVEX_L_W_OPSIZE_B, /* 9182 */ IC_EVEX_L_W_OPSIZE_B, /* 9183 */ IC_EVEX_L_B, /* 9184 */ IC_EVEX_L_B, /* 9185 */ IC_EVEX_L_XS_B, /* 9186 */ IC_EVEX_L_XS_B, /* 9187 */ IC_EVEX_L_XD_B, /* 9188 */ IC_EVEX_L_XD_B, /* 9189 */ IC_EVEX_L_XD_B, /* 9190 */ IC_EVEX_L_XD_B, /* 9191 */ IC_EVEX_L_W_B, /* 9192 */ IC_EVEX_L_W_B, /* 9193 */ IC_EVEX_L_W_XS_B, /* 9194 */ IC_EVEX_L_W_XS_B, /* 9195 */ IC_EVEX_L_W_XD_B, /* 9196 */ IC_EVEX_L_W_XD_B, /* 9197 */ IC_EVEX_L_W_XD_B, /* 9198 */ IC_EVEX_L_W_XD_B, /* 9199 */ IC_EVEX_L_OPSIZE_B, /* 9200 */ IC_EVEX_L_OPSIZE_B, /* 9201 */ IC_EVEX_L_OPSIZE_B, /* 9202 */ IC_EVEX_L_OPSIZE_B, /* 9203 */ IC_EVEX_L_OPSIZE_B, /* 9204 */ IC_EVEX_L_OPSIZE_B, /* 9205 */ IC_EVEX_L_OPSIZE_B, /* 9206 */ IC_EVEX_L_OPSIZE_B, /* 9207 */ IC_EVEX_L_W_OPSIZE_B, /* 9208 */ IC_EVEX_L_W_OPSIZE_B, /* 9209 */ IC_EVEX_L_W_OPSIZE_B, /* 9210 */ IC_EVEX_L_W_OPSIZE_B, /* 9211 */ IC_EVEX_L_W_OPSIZE_B, /* 9212 */ IC_EVEX_L_W_OPSIZE_B, /* 9213 */ IC_EVEX_L_W_OPSIZE_B, /* 9214 */ IC_EVEX_L_W_OPSIZE_B, /* 9215 */ IC, /* 9216 */ IC_64BIT, /* 9217 */ IC_XS, /* 9218 */ IC_64BIT_XS, /* 9219 */ IC_XD, /* 9220 */ IC_64BIT_XD, /* 9221 */ IC_XS, /* 9222 */ IC_64BIT_XS, /* 9223 */ IC, /* 9224 */ IC_64BIT_REXW, /* 9225 */ IC_XS, /* 9226 */ IC_64BIT_REXW_XS, /* 9227 */ IC_XD, /* 9228 */ IC_64BIT_REXW_XD, /* 9229 */ IC_XS, /* 9230 */ IC_64BIT_REXW_XS, /* 9231 */ IC_OPSIZE, /* 9232 */ IC_64BIT_OPSIZE, /* 9233 */ IC_XS_OPSIZE, /* 9234 */ IC_64BIT_XS_OPSIZE, /* 9235 */ IC_XD_OPSIZE, /* 9236 */ IC_64BIT_XD_OPSIZE, /* 9237 */ IC_XS_OPSIZE, /* 9238 */ IC_64BIT_XD_OPSIZE, /* 9239 */ IC_OPSIZE, /* 9240 */ IC_64BIT_REXW_OPSIZE, /* 9241 */ IC_XS_OPSIZE, /* 9242 */ IC_64BIT_REXW_XS, /* 9243 */ IC_XD_OPSIZE, /* 9244 */ IC_64BIT_REXW_XD, /* 9245 */ IC_XS_OPSIZE, /* 9246 */ IC_64BIT_REXW_XS, /* 9247 */ IC_ADSIZE, /* 9248 */ IC_64BIT_ADSIZE, /* 9249 */ IC_XS_ADSIZE, /* 9250 */ IC_64BIT_XS_ADSIZE, /* 9251 */ IC_XD_ADSIZE, /* 9252 */ IC_64BIT_XD_ADSIZE, /* 9253 */ IC_XS_ADSIZE, /* 9254 */ IC_64BIT_XD_ADSIZE, /* 9255 */ IC_ADSIZE, /* 9256 */ IC_64BIT_REXW_ADSIZE, /* 9257 */ IC_XS_ADSIZE, /* 9258 */ IC_64BIT_REXW_XS, /* 9259 */ IC_XD_ADSIZE, /* 9260 */ IC_64BIT_REXW_XD, /* 9261 */ IC_XS_ADSIZE, /* 9262 */ IC_64BIT_REXW_XS, /* 9263 */ IC_OPSIZE_ADSIZE, /* 9264 */ IC_64BIT_OPSIZE_ADSIZE, /* 9265 */ IC_XS_OPSIZE, /* 9266 */ IC_64BIT_XS_OPSIZE, /* 9267 */ IC_XD_OPSIZE, /* 9268 */ IC_64BIT_XD_OPSIZE, /* 9269 */ IC_XS_OPSIZE, /* 9270 */ IC_64BIT_XD_OPSIZE, /* 9271 */ IC_OPSIZE_ADSIZE, /* 9272 */ IC_64BIT_REXW_OPSIZE, /* 9273 */ IC_XS_OPSIZE, /* 9274 */ IC_64BIT_REXW_XS, /* 9275 */ IC_XD_OPSIZE, /* 9276 */ IC_64BIT_REXW_XD, /* 9277 */ IC_XS_OPSIZE, /* 9278 */ IC_64BIT_REXW_XS, /* 9279 */ IC_VEX, /* 9280 */ IC_VEX, /* 9281 */ IC_VEX_XS, /* 9282 */ IC_VEX_XS, /* 9283 */ IC_VEX_XD, /* 9284 */ IC_VEX_XD, /* 9285 */ IC_VEX_XD, /* 9286 */ IC_VEX_XD, /* 9287 */ IC_VEX_W, /* 9288 */ IC_VEX_W, /* 9289 */ IC_VEX_W_XS, /* 9290 */ IC_VEX_W_XS, /* 9291 */ IC_VEX_W_XD, /* 9292 */ IC_VEX_W_XD, /* 9293 */ IC_VEX_W_XD, /* 9294 */ IC_VEX_W_XD, /* 9295 */ IC_VEX_OPSIZE, /* 9296 */ IC_VEX_OPSIZE, /* 9297 */ IC_VEX_OPSIZE, /* 9298 */ IC_VEX_OPSIZE, /* 9299 */ IC_VEX_OPSIZE, /* 9300 */ IC_VEX_OPSIZE, /* 9301 */ IC_VEX_OPSIZE, /* 9302 */ IC_VEX_OPSIZE, /* 9303 */ IC_VEX_W_OPSIZE, /* 9304 */ IC_VEX_W_OPSIZE, /* 9305 */ IC_VEX_W_OPSIZE, /* 9306 */ IC_VEX_W_OPSIZE, /* 9307 */ IC_VEX_W_OPSIZE, /* 9308 */ IC_VEX_W_OPSIZE, /* 9309 */ IC_VEX_W_OPSIZE, /* 9310 */ IC_VEX_W_OPSIZE, /* 9311 */ IC_VEX, /* 9312 */ IC_VEX, /* 9313 */ IC_VEX_XS, /* 9314 */ IC_VEX_XS, /* 9315 */ IC_VEX_XD, /* 9316 */ IC_VEX_XD, /* 9317 */ IC_VEX_XD, /* 9318 */ IC_VEX_XD, /* 9319 */ IC_VEX_W, /* 9320 */ IC_VEX_W, /* 9321 */ IC_VEX_W_XS, /* 9322 */ IC_VEX_W_XS, /* 9323 */ IC_VEX_W_XD, /* 9324 */ IC_VEX_W_XD, /* 9325 */ IC_VEX_W_XD, /* 9326 */ IC_VEX_W_XD, /* 9327 */ IC_VEX_OPSIZE, /* 9328 */ IC_VEX_OPSIZE, /* 9329 */ IC_VEX_OPSIZE, /* 9330 */ IC_VEX_OPSIZE, /* 9331 */ IC_VEX_OPSIZE, /* 9332 */ IC_VEX_OPSIZE, /* 9333 */ IC_VEX_OPSIZE, /* 9334 */ IC_VEX_OPSIZE, /* 9335 */ IC_VEX_W_OPSIZE, /* 9336 */ IC_VEX_W_OPSIZE, /* 9337 */ IC_VEX_W_OPSIZE, /* 9338 */ IC_VEX_W_OPSIZE, /* 9339 */ IC_VEX_W_OPSIZE, /* 9340 */ IC_VEX_W_OPSIZE, /* 9341 */ IC_VEX_W_OPSIZE, /* 9342 */ IC_VEX_W_OPSIZE, /* 9343 */ IC_VEX_L, /* 9344 */ IC_VEX_L, /* 9345 */ IC_VEX_L_XS, /* 9346 */ IC_VEX_L_XS, /* 9347 */ IC_VEX_L_XD, /* 9348 */ IC_VEX_L_XD, /* 9349 */ IC_VEX_L_XD, /* 9350 */ IC_VEX_L_XD, /* 9351 */ IC_VEX_L_W, /* 9352 */ IC_VEX_L_W, /* 9353 */ IC_VEX_L_W_XS, /* 9354 */ IC_VEX_L_W_XS, /* 9355 */ IC_VEX_L_W_XD, /* 9356 */ IC_VEX_L_W_XD, /* 9357 */ IC_VEX_L_W_XD, /* 9358 */ IC_VEX_L_W_XD, /* 9359 */ IC_VEX_L_OPSIZE, /* 9360 */ IC_VEX_L_OPSIZE, /* 9361 */ IC_VEX_L_OPSIZE, /* 9362 */ IC_VEX_L_OPSIZE, /* 9363 */ IC_VEX_L_OPSIZE, /* 9364 */ IC_VEX_L_OPSIZE, /* 9365 */ IC_VEX_L_OPSIZE, /* 9366 */ IC_VEX_L_OPSIZE, /* 9367 */ IC_VEX_L_W_OPSIZE, /* 9368 */ IC_VEX_L_W_OPSIZE, /* 9369 */ IC_VEX_L_W_OPSIZE, /* 9370 */ IC_VEX_L_W_OPSIZE, /* 9371 */ IC_VEX_L_W_OPSIZE, /* 9372 */ IC_VEX_L_W_OPSIZE, /* 9373 */ IC_VEX_L_W_OPSIZE, /* 9374 */ IC_VEX_L_W_OPSIZE, /* 9375 */ IC_VEX_L, /* 9376 */ IC_VEX_L, /* 9377 */ IC_VEX_L_XS, /* 9378 */ IC_VEX_L_XS, /* 9379 */ IC_VEX_L_XD, /* 9380 */ IC_VEX_L_XD, /* 9381 */ IC_VEX_L_XD, /* 9382 */ IC_VEX_L_XD, /* 9383 */ IC_VEX_L_W, /* 9384 */ IC_VEX_L_W, /* 9385 */ IC_VEX_L_W_XS, /* 9386 */ IC_VEX_L_W_XS, /* 9387 */ IC_VEX_L_W_XD, /* 9388 */ IC_VEX_L_W_XD, /* 9389 */ IC_VEX_L_W_XD, /* 9390 */ IC_VEX_L_W_XD, /* 9391 */ IC_VEX_L_OPSIZE, /* 9392 */ IC_VEX_L_OPSIZE, /* 9393 */ IC_VEX_L_OPSIZE, /* 9394 */ IC_VEX_L_OPSIZE, /* 9395 */ IC_VEX_L_OPSIZE, /* 9396 */ IC_VEX_L_OPSIZE, /* 9397 */ IC_VEX_L_OPSIZE, /* 9398 */ IC_VEX_L_OPSIZE, /* 9399 */ IC_VEX_L_W_OPSIZE, /* 9400 */ IC_VEX_L_W_OPSIZE, /* 9401 */ IC_VEX_L_W_OPSIZE, /* 9402 */ IC_VEX_L_W_OPSIZE, /* 9403 */ IC_VEX_L_W_OPSIZE, /* 9404 */ IC_VEX_L_W_OPSIZE, /* 9405 */ IC_VEX_L_W_OPSIZE, /* 9406 */ IC_VEX_L_W_OPSIZE, /* 9407 */ IC_VEX_L, /* 9408 */ IC_VEX_L, /* 9409 */ IC_VEX_L_XS, /* 9410 */ IC_VEX_L_XS, /* 9411 */ IC_VEX_L_XD, /* 9412 */ IC_VEX_L_XD, /* 9413 */ IC_VEX_L_XD, /* 9414 */ IC_VEX_L_XD, /* 9415 */ IC_VEX_L_W, /* 9416 */ IC_VEX_L_W, /* 9417 */ IC_VEX_L_W_XS, /* 9418 */ IC_VEX_L_W_XS, /* 9419 */ IC_VEX_L_W_XD, /* 9420 */ IC_VEX_L_W_XD, /* 9421 */ IC_VEX_L_W_XD, /* 9422 */ IC_VEX_L_W_XD, /* 9423 */ IC_VEX_L_OPSIZE, /* 9424 */ IC_VEX_L_OPSIZE, /* 9425 */ IC_VEX_L_OPSIZE, /* 9426 */ IC_VEX_L_OPSIZE, /* 9427 */ IC_VEX_L_OPSIZE, /* 9428 */ IC_VEX_L_OPSIZE, /* 9429 */ IC_VEX_L_OPSIZE, /* 9430 */ IC_VEX_L_OPSIZE, /* 9431 */ IC_VEX_L_W_OPSIZE, /* 9432 */ IC_VEX_L_W_OPSIZE, /* 9433 */ IC_VEX_L_W_OPSIZE, /* 9434 */ IC_VEX_L_W_OPSIZE, /* 9435 */ IC_VEX_L_W_OPSIZE, /* 9436 */ IC_VEX_L_W_OPSIZE, /* 9437 */ IC_VEX_L_W_OPSIZE, /* 9438 */ IC_VEX_L_W_OPSIZE, /* 9439 */ IC_VEX_L, /* 9440 */ IC_VEX_L, /* 9441 */ IC_VEX_L_XS, /* 9442 */ IC_VEX_L_XS, /* 9443 */ IC_VEX_L_XD, /* 9444 */ IC_VEX_L_XD, /* 9445 */ IC_VEX_L_XD, /* 9446 */ IC_VEX_L_XD, /* 9447 */ IC_VEX_L_W, /* 9448 */ IC_VEX_L_W, /* 9449 */ IC_VEX_L_W_XS, /* 9450 */ IC_VEX_L_W_XS, /* 9451 */ IC_VEX_L_W_XD, /* 9452 */ IC_VEX_L_W_XD, /* 9453 */ IC_VEX_L_W_XD, /* 9454 */ IC_VEX_L_W_XD, /* 9455 */ IC_VEX_L_OPSIZE, /* 9456 */ IC_VEX_L_OPSIZE, /* 9457 */ IC_VEX_L_OPSIZE, /* 9458 */ IC_VEX_L_OPSIZE, /* 9459 */ IC_VEX_L_OPSIZE, /* 9460 */ IC_VEX_L_OPSIZE, /* 9461 */ IC_VEX_L_OPSIZE, /* 9462 */ IC_VEX_L_OPSIZE, /* 9463 */ IC_VEX_L_W_OPSIZE, /* 9464 */ IC_VEX_L_W_OPSIZE, /* 9465 */ IC_VEX_L_W_OPSIZE, /* 9466 */ IC_VEX_L_W_OPSIZE, /* 9467 */ IC_VEX_L_W_OPSIZE, /* 9468 */ IC_VEX_L_W_OPSIZE, /* 9469 */ IC_VEX_L_W_OPSIZE, /* 9470 */ IC_VEX_L_W_OPSIZE, /* 9471 */ IC_EVEX_L2_B, /* 9472 */ IC_EVEX_L2_B, /* 9473 */ IC_EVEX_L2_XS_B, /* 9474 */ IC_EVEX_L2_XS_B, /* 9475 */ IC_EVEX_L2_XD_B, /* 9476 */ IC_EVEX_L2_XD_B, /* 9477 */ IC_EVEX_L2_XD_B, /* 9478 */ IC_EVEX_L2_XD_B, /* 9479 */ IC_EVEX_L2_W_B, /* 9480 */ IC_EVEX_L2_W_B, /* 9481 */ IC_EVEX_L2_W_XS_B, /* 9482 */ IC_EVEX_L2_W_XS_B, /* 9483 */ IC_EVEX_L2_W_XD_B, /* 9484 */ IC_EVEX_L2_W_XD_B, /* 9485 */ IC_EVEX_L2_W_XD_B, /* 9486 */ IC_EVEX_L2_W_XD_B, /* 9487 */ IC_EVEX_L2_OPSIZE_B, /* 9488 */ IC_EVEX_L2_OPSIZE_B, /* 9489 */ IC_EVEX_L2_OPSIZE_B, /* 9490 */ IC_EVEX_L2_OPSIZE_B, /* 9491 */ IC_EVEX_L2_OPSIZE_B, /* 9492 */ IC_EVEX_L2_OPSIZE_B, /* 9493 */ IC_EVEX_L2_OPSIZE_B, /* 9494 */ IC_EVEX_L2_OPSIZE_B, /* 9495 */ IC_EVEX_L2_W_OPSIZE_B, /* 9496 */ IC_EVEX_L2_W_OPSIZE_B, /* 9497 */ IC_EVEX_L2_W_OPSIZE_B, /* 9498 */ IC_EVEX_L2_W_OPSIZE_B, /* 9499 */ IC_EVEX_L2_W_OPSIZE_B, /* 9500 */ IC_EVEX_L2_W_OPSIZE_B, /* 9501 */ IC_EVEX_L2_W_OPSIZE_B, /* 9502 */ IC_EVEX_L2_W_OPSIZE_B, /* 9503 */ IC_EVEX_L2_B, /* 9504 */ IC_EVEX_L2_B, /* 9505 */ IC_EVEX_L2_XS_B, /* 9506 */ IC_EVEX_L2_XS_B, /* 9507 */ IC_EVEX_L2_XD_B, /* 9508 */ IC_EVEX_L2_XD_B, /* 9509 */ IC_EVEX_L2_XD_B, /* 9510 */ IC_EVEX_L2_XD_B, /* 9511 */ IC_EVEX_L2_W_B, /* 9512 */ IC_EVEX_L2_W_B, /* 9513 */ IC_EVEX_L2_W_XS_B, /* 9514 */ IC_EVEX_L2_W_XS_B, /* 9515 */ IC_EVEX_L2_W_XD_B, /* 9516 */ IC_EVEX_L2_W_XD_B, /* 9517 */ IC_EVEX_L2_W_XD_B, /* 9518 */ IC_EVEX_L2_W_XD_B, /* 9519 */ IC_EVEX_L2_OPSIZE_B, /* 9520 */ IC_EVEX_L2_OPSIZE_B, /* 9521 */ IC_EVEX_L2_OPSIZE_B, /* 9522 */ IC_EVEX_L2_OPSIZE_B, /* 9523 */ IC_EVEX_L2_OPSIZE_B, /* 9524 */ IC_EVEX_L2_OPSIZE_B, /* 9525 */ IC_EVEX_L2_OPSIZE_B, /* 9526 */ IC_EVEX_L2_OPSIZE_B, /* 9527 */ IC_EVEX_L2_W_OPSIZE_B, /* 9528 */ IC_EVEX_L2_W_OPSIZE_B, /* 9529 */ IC_EVEX_L2_W_OPSIZE_B, /* 9530 */ IC_EVEX_L2_W_OPSIZE_B, /* 9531 */ IC_EVEX_L2_W_OPSIZE_B, /* 9532 */ IC_EVEX_L2_W_OPSIZE_B, /* 9533 */ IC_EVEX_L2_W_OPSIZE_B, /* 9534 */ IC_EVEX_L2_W_OPSIZE_B, /* 9535 */ IC_EVEX_L2_B, /* 9536 */ IC_EVEX_L2_B, /* 9537 */ IC_EVEX_L2_XS_B, /* 9538 */ IC_EVEX_L2_XS_B, /* 9539 */ IC_EVEX_L2_XD_B, /* 9540 */ IC_EVEX_L2_XD_B, /* 9541 */ IC_EVEX_L2_XD_B, /* 9542 */ IC_EVEX_L2_XD_B, /* 9543 */ IC_EVEX_L2_W_B, /* 9544 */ IC_EVEX_L2_W_B, /* 9545 */ IC_EVEX_L2_W_XS_B, /* 9546 */ IC_EVEX_L2_W_XS_B, /* 9547 */ IC_EVEX_L2_W_XD_B, /* 9548 */ IC_EVEX_L2_W_XD_B, /* 9549 */ IC_EVEX_L2_W_XD_B, /* 9550 */ IC_EVEX_L2_W_XD_B, /* 9551 */ IC_EVEX_L2_OPSIZE_B, /* 9552 */ IC_EVEX_L2_OPSIZE_B, /* 9553 */ IC_EVEX_L2_OPSIZE_B, /* 9554 */ IC_EVEX_L2_OPSIZE_B, /* 9555 */ IC_EVEX_L2_OPSIZE_B, /* 9556 */ IC_EVEX_L2_OPSIZE_B, /* 9557 */ IC_EVEX_L2_OPSIZE_B, /* 9558 */ IC_EVEX_L2_OPSIZE_B, /* 9559 */ IC_EVEX_L2_W_OPSIZE_B, /* 9560 */ IC_EVEX_L2_W_OPSIZE_B, /* 9561 */ IC_EVEX_L2_W_OPSIZE_B, /* 9562 */ IC_EVEX_L2_W_OPSIZE_B, /* 9563 */ IC_EVEX_L2_W_OPSIZE_B, /* 9564 */ IC_EVEX_L2_W_OPSIZE_B, /* 9565 */ IC_EVEX_L2_W_OPSIZE_B, /* 9566 */ IC_EVEX_L2_W_OPSIZE_B, /* 9567 */ IC_EVEX_L2_B, /* 9568 */ IC_EVEX_L2_B, /* 9569 */ IC_EVEX_L2_XS_B, /* 9570 */ IC_EVEX_L2_XS_B, /* 9571 */ IC_EVEX_L2_XD_B, /* 9572 */ IC_EVEX_L2_XD_B, /* 9573 */ IC_EVEX_L2_XD_B, /* 9574 */ IC_EVEX_L2_XD_B, /* 9575 */ IC_EVEX_L2_W_B, /* 9576 */ IC_EVEX_L2_W_B, /* 9577 */ IC_EVEX_L2_W_XS_B, /* 9578 */ IC_EVEX_L2_W_XS_B, /* 9579 */ IC_EVEX_L2_W_XD_B, /* 9580 */ IC_EVEX_L2_W_XD_B, /* 9581 */ IC_EVEX_L2_W_XD_B, /* 9582 */ IC_EVEX_L2_W_XD_B, /* 9583 */ IC_EVEX_L2_OPSIZE_B, /* 9584 */ IC_EVEX_L2_OPSIZE_B, /* 9585 */ IC_EVEX_L2_OPSIZE_B, /* 9586 */ IC_EVEX_L2_OPSIZE_B, /* 9587 */ IC_EVEX_L2_OPSIZE_B, /* 9588 */ IC_EVEX_L2_OPSIZE_B, /* 9589 */ IC_EVEX_L2_OPSIZE_B, /* 9590 */ IC_EVEX_L2_OPSIZE_B, /* 9591 */ IC_EVEX_L2_W_OPSIZE_B, /* 9592 */ IC_EVEX_L2_W_OPSIZE_B, /* 9593 */ IC_EVEX_L2_W_OPSIZE_B, /* 9594 */ IC_EVEX_L2_W_OPSIZE_B, /* 9595 */ IC_EVEX_L2_W_OPSIZE_B, /* 9596 */ IC_EVEX_L2_W_OPSIZE_B, /* 9597 */ IC_EVEX_L2_W_OPSIZE_B, /* 9598 */ IC_EVEX_L2_W_OPSIZE_B, /* 9599 */ IC_EVEX_L2_B, /* 9600 */ IC_EVEX_L2_B, /* 9601 */ IC_EVEX_L2_XS_B, /* 9602 */ IC_EVEX_L2_XS_B, /* 9603 */ IC_EVEX_L2_XD_B, /* 9604 */ IC_EVEX_L2_XD_B, /* 9605 */ IC_EVEX_L2_XD_B, /* 9606 */ IC_EVEX_L2_XD_B, /* 9607 */ IC_EVEX_L2_W_B, /* 9608 */ IC_EVEX_L2_W_B, /* 9609 */ IC_EVEX_L2_W_XS_B, /* 9610 */ IC_EVEX_L2_W_XS_B, /* 9611 */ IC_EVEX_L2_W_XD_B, /* 9612 */ IC_EVEX_L2_W_XD_B, /* 9613 */ IC_EVEX_L2_W_XD_B, /* 9614 */ IC_EVEX_L2_W_XD_B, /* 9615 */ IC_EVEX_L2_OPSIZE_B, /* 9616 */ IC_EVEX_L2_OPSIZE_B, /* 9617 */ IC_EVEX_L2_OPSIZE_B, /* 9618 */ IC_EVEX_L2_OPSIZE_B, /* 9619 */ IC_EVEX_L2_OPSIZE_B, /* 9620 */ IC_EVEX_L2_OPSIZE_B, /* 9621 */ IC_EVEX_L2_OPSIZE_B, /* 9622 */ IC_EVEX_L2_OPSIZE_B, /* 9623 */ IC_EVEX_L2_W_OPSIZE_B, /* 9624 */ IC_EVEX_L2_W_OPSIZE_B, /* 9625 */ IC_EVEX_L2_W_OPSIZE_B, /* 9626 */ IC_EVEX_L2_W_OPSIZE_B, /* 9627 */ IC_EVEX_L2_W_OPSIZE_B, /* 9628 */ IC_EVEX_L2_W_OPSIZE_B, /* 9629 */ IC_EVEX_L2_W_OPSIZE_B, /* 9630 */ IC_EVEX_L2_W_OPSIZE_B, /* 9631 */ IC_EVEX_L2_B, /* 9632 */ IC_EVEX_L2_B, /* 9633 */ IC_EVEX_L2_XS_B, /* 9634 */ IC_EVEX_L2_XS_B, /* 9635 */ IC_EVEX_L2_XD_B, /* 9636 */ IC_EVEX_L2_XD_B, /* 9637 */ IC_EVEX_L2_XD_B, /* 9638 */ IC_EVEX_L2_XD_B, /* 9639 */ IC_EVEX_L2_W_B, /* 9640 */ IC_EVEX_L2_W_B, /* 9641 */ IC_EVEX_L2_W_XS_B, /* 9642 */ IC_EVEX_L2_W_XS_B, /* 9643 */ IC_EVEX_L2_W_XD_B, /* 9644 */ IC_EVEX_L2_W_XD_B, /* 9645 */ IC_EVEX_L2_W_XD_B, /* 9646 */ IC_EVEX_L2_W_XD_B, /* 9647 */ IC_EVEX_L2_OPSIZE_B, /* 9648 */ IC_EVEX_L2_OPSIZE_B, /* 9649 */ IC_EVEX_L2_OPSIZE_B, /* 9650 */ IC_EVEX_L2_OPSIZE_B, /* 9651 */ IC_EVEX_L2_OPSIZE_B, /* 9652 */ IC_EVEX_L2_OPSIZE_B, /* 9653 */ IC_EVEX_L2_OPSIZE_B, /* 9654 */ IC_EVEX_L2_OPSIZE_B, /* 9655 */ IC_EVEX_L2_W_OPSIZE_B, /* 9656 */ IC_EVEX_L2_W_OPSIZE_B, /* 9657 */ IC_EVEX_L2_W_OPSIZE_B, /* 9658 */ IC_EVEX_L2_W_OPSIZE_B, /* 9659 */ IC_EVEX_L2_W_OPSIZE_B, /* 9660 */ IC_EVEX_L2_W_OPSIZE_B, /* 9661 */ IC_EVEX_L2_W_OPSIZE_B, /* 9662 */ IC_EVEX_L2_W_OPSIZE_B, /* 9663 */ IC_EVEX_L2_B, /* 9664 */ IC_EVEX_L2_B, /* 9665 */ IC_EVEX_L2_XS_B, /* 9666 */ IC_EVEX_L2_XS_B, /* 9667 */ IC_EVEX_L2_XD_B, /* 9668 */ IC_EVEX_L2_XD_B, /* 9669 */ IC_EVEX_L2_XD_B, /* 9670 */ IC_EVEX_L2_XD_B, /* 9671 */ IC_EVEX_L2_W_B, /* 9672 */ IC_EVEX_L2_W_B, /* 9673 */ IC_EVEX_L2_W_XS_B, /* 9674 */ IC_EVEX_L2_W_XS_B, /* 9675 */ IC_EVEX_L2_W_XD_B, /* 9676 */ IC_EVEX_L2_W_XD_B, /* 9677 */ IC_EVEX_L2_W_XD_B, /* 9678 */ IC_EVEX_L2_W_XD_B, /* 9679 */ IC_EVEX_L2_OPSIZE_B, /* 9680 */ IC_EVEX_L2_OPSIZE_B, /* 9681 */ IC_EVEX_L2_OPSIZE_B, /* 9682 */ IC_EVEX_L2_OPSIZE_B, /* 9683 */ IC_EVEX_L2_OPSIZE_B, /* 9684 */ IC_EVEX_L2_OPSIZE_B, /* 9685 */ IC_EVEX_L2_OPSIZE_B, /* 9686 */ IC_EVEX_L2_OPSIZE_B, /* 9687 */ IC_EVEX_L2_W_OPSIZE_B, /* 9688 */ IC_EVEX_L2_W_OPSIZE_B, /* 9689 */ IC_EVEX_L2_W_OPSIZE_B, /* 9690 */ IC_EVEX_L2_W_OPSIZE_B, /* 9691 */ IC_EVEX_L2_W_OPSIZE_B, /* 9692 */ IC_EVEX_L2_W_OPSIZE_B, /* 9693 */ IC_EVEX_L2_W_OPSIZE_B, /* 9694 */ IC_EVEX_L2_W_OPSIZE_B, /* 9695 */ IC_EVEX_L2_B, /* 9696 */ IC_EVEX_L2_B, /* 9697 */ IC_EVEX_L2_XS_B, /* 9698 */ IC_EVEX_L2_XS_B, /* 9699 */ IC_EVEX_L2_XD_B, /* 9700 */ IC_EVEX_L2_XD_B, /* 9701 */ IC_EVEX_L2_XD_B, /* 9702 */ IC_EVEX_L2_XD_B, /* 9703 */ IC_EVEX_L2_W_B, /* 9704 */ IC_EVEX_L2_W_B, /* 9705 */ IC_EVEX_L2_W_XS_B, /* 9706 */ IC_EVEX_L2_W_XS_B, /* 9707 */ IC_EVEX_L2_W_XD_B, /* 9708 */ IC_EVEX_L2_W_XD_B, /* 9709 */ IC_EVEX_L2_W_XD_B, /* 9710 */ IC_EVEX_L2_W_XD_B, /* 9711 */ IC_EVEX_L2_OPSIZE_B, /* 9712 */ IC_EVEX_L2_OPSIZE_B, /* 9713 */ IC_EVEX_L2_OPSIZE_B, /* 9714 */ IC_EVEX_L2_OPSIZE_B, /* 9715 */ IC_EVEX_L2_OPSIZE_B, /* 9716 */ IC_EVEX_L2_OPSIZE_B, /* 9717 */ IC_EVEX_L2_OPSIZE_B, /* 9718 */ IC_EVEX_L2_OPSIZE_B, /* 9719 */ IC_EVEX_L2_W_OPSIZE_B, /* 9720 */ IC_EVEX_L2_W_OPSIZE_B, /* 9721 */ IC_EVEX_L2_W_OPSIZE_B, /* 9722 */ IC_EVEX_L2_W_OPSIZE_B, /* 9723 */ IC_EVEX_L2_W_OPSIZE_B, /* 9724 */ IC_EVEX_L2_W_OPSIZE_B, /* 9725 */ IC_EVEX_L2_W_OPSIZE_B, /* 9726 */ IC_EVEX_L2_W_OPSIZE_B, /* 9727 */ IC, /* 9728 */ IC_64BIT, /* 9729 */ IC_XS, /* 9730 */ IC_64BIT_XS, /* 9731 */ IC_XD, /* 9732 */ IC_64BIT_XD, /* 9733 */ IC_XS, /* 9734 */ IC_64BIT_XS, /* 9735 */ IC, /* 9736 */ IC_64BIT_REXW, /* 9737 */ IC_XS, /* 9738 */ IC_64BIT_REXW_XS, /* 9739 */ IC_XD, /* 9740 */ IC_64BIT_REXW_XD, /* 9741 */ IC_XS, /* 9742 */ IC_64BIT_REXW_XS, /* 9743 */ IC_OPSIZE, /* 9744 */ IC_64BIT_OPSIZE, /* 9745 */ IC_XS_OPSIZE, /* 9746 */ IC_64BIT_XS_OPSIZE, /* 9747 */ IC_XD_OPSIZE, /* 9748 */ IC_64BIT_XD_OPSIZE, /* 9749 */ IC_XS_OPSIZE, /* 9750 */ IC_64BIT_XD_OPSIZE, /* 9751 */ IC_OPSIZE, /* 9752 */ IC_64BIT_REXW_OPSIZE, /* 9753 */ IC_XS_OPSIZE, /* 9754 */ IC_64BIT_REXW_XS, /* 9755 */ IC_XD_OPSIZE, /* 9756 */ IC_64BIT_REXW_XD, /* 9757 */ IC_XS_OPSIZE, /* 9758 */ IC_64BIT_REXW_XS, /* 9759 */ IC_ADSIZE, /* 9760 */ IC_64BIT_ADSIZE, /* 9761 */ IC_XS_ADSIZE, /* 9762 */ IC_64BIT_XS_ADSIZE, /* 9763 */ IC_XD_ADSIZE, /* 9764 */ IC_64BIT_XD_ADSIZE, /* 9765 */ IC_XS_ADSIZE, /* 9766 */ IC_64BIT_XD_ADSIZE, /* 9767 */ IC_ADSIZE, /* 9768 */ IC_64BIT_REXW_ADSIZE, /* 9769 */ IC_XS_ADSIZE, /* 9770 */ IC_64BIT_REXW_XS, /* 9771 */ IC_XD_ADSIZE, /* 9772 */ IC_64BIT_REXW_XD, /* 9773 */ IC_XS_ADSIZE, /* 9774 */ IC_64BIT_REXW_XS, /* 9775 */ IC_OPSIZE_ADSIZE, /* 9776 */ IC_64BIT_OPSIZE_ADSIZE, /* 9777 */ IC_XS_OPSIZE, /* 9778 */ IC_64BIT_XS_OPSIZE, /* 9779 */ IC_XD_OPSIZE, /* 9780 */ IC_64BIT_XD_OPSIZE, /* 9781 */ IC_XS_OPSIZE, /* 9782 */ IC_64BIT_XD_OPSIZE, /* 9783 */ IC_OPSIZE_ADSIZE, /* 9784 */ IC_64BIT_REXW_OPSIZE, /* 9785 */ IC_XS_OPSIZE, /* 9786 */ IC_64BIT_REXW_XS, /* 9787 */ IC_XD_OPSIZE, /* 9788 */ IC_64BIT_REXW_XD, /* 9789 */ IC_XS_OPSIZE, /* 9790 */ IC_64BIT_REXW_XS, /* 9791 */ IC_VEX, /* 9792 */ IC_VEX, /* 9793 */ IC_VEX_XS, /* 9794 */ IC_VEX_XS, /* 9795 */ IC_VEX_XD, /* 9796 */ IC_VEX_XD, /* 9797 */ IC_VEX_XD, /* 9798 */ IC_VEX_XD, /* 9799 */ IC_VEX_W, /* 9800 */ IC_VEX_W, /* 9801 */ IC_VEX_W_XS, /* 9802 */ IC_VEX_W_XS, /* 9803 */ IC_VEX_W_XD, /* 9804 */ IC_VEX_W_XD, /* 9805 */ IC_VEX_W_XD, /* 9806 */ IC_VEX_W_XD, /* 9807 */ IC_VEX_OPSIZE, /* 9808 */ IC_VEX_OPSIZE, /* 9809 */ IC_VEX_OPSIZE, /* 9810 */ IC_VEX_OPSIZE, /* 9811 */ IC_VEX_OPSIZE, /* 9812 */ IC_VEX_OPSIZE, /* 9813 */ IC_VEX_OPSIZE, /* 9814 */ IC_VEX_OPSIZE, /* 9815 */ IC_VEX_W_OPSIZE, /* 9816 */ IC_VEX_W_OPSIZE, /* 9817 */ IC_VEX_W_OPSIZE, /* 9818 */ IC_VEX_W_OPSIZE, /* 9819 */ IC_VEX_W_OPSIZE, /* 9820 */ IC_VEX_W_OPSIZE, /* 9821 */ IC_VEX_W_OPSIZE, /* 9822 */ IC_VEX_W_OPSIZE, /* 9823 */ IC_VEX, /* 9824 */ IC_VEX, /* 9825 */ IC_VEX_XS, /* 9826 */ IC_VEX_XS, /* 9827 */ IC_VEX_XD, /* 9828 */ IC_VEX_XD, /* 9829 */ IC_VEX_XD, /* 9830 */ IC_VEX_XD, /* 9831 */ IC_VEX_W, /* 9832 */ IC_VEX_W, /* 9833 */ IC_VEX_W_XS, /* 9834 */ IC_VEX_W_XS, /* 9835 */ IC_VEX_W_XD, /* 9836 */ IC_VEX_W_XD, /* 9837 */ IC_VEX_W_XD, /* 9838 */ IC_VEX_W_XD, /* 9839 */ IC_VEX_OPSIZE, /* 9840 */ IC_VEX_OPSIZE, /* 9841 */ IC_VEX_OPSIZE, /* 9842 */ IC_VEX_OPSIZE, /* 9843 */ IC_VEX_OPSIZE, /* 9844 */ IC_VEX_OPSIZE, /* 9845 */ IC_VEX_OPSIZE, /* 9846 */ IC_VEX_OPSIZE, /* 9847 */ IC_VEX_W_OPSIZE, /* 9848 */ IC_VEX_W_OPSIZE, /* 9849 */ IC_VEX_W_OPSIZE, /* 9850 */ IC_VEX_W_OPSIZE, /* 9851 */ IC_VEX_W_OPSIZE, /* 9852 */ IC_VEX_W_OPSIZE, /* 9853 */ IC_VEX_W_OPSIZE, /* 9854 */ IC_VEX_W_OPSIZE, /* 9855 */ IC_VEX_L, /* 9856 */ IC_VEX_L, /* 9857 */ IC_VEX_L_XS, /* 9858 */ IC_VEX_L_XS, /* 9859 */ IC_VEX_L_XD, /* 9860 */ IC_VEX_L_XD, /* 9861 */ IC_VEX_L_XD, /* 9862 */ IC_VEX_L_XD, /* 9863 */ IC_VEX_L_W, /* 9864 */ IC_VEX_L_W, /* 9865 */ IC_VEX_L_W_XS, /* 9866 */ IC_VEX_L_W_XS, /* 9867 */ IC_VEX_L_W_XD, /* 9868 */ IC_VEX_L_W_XD, /* 9869 */ IC_VEX_L_W_XD, /* 9870 */ IC_VEX_L_W_XD, /* 9871 */ IC_VEX_L_OPSIZE, /* 9872 */ IC_VEX_L_OPSIZE, /* 9873 */ IC_VEX_L_OPSIZE, /* 9874 */ IC_VEX_L_OPSIZE, /* 9875 */ IC_VEX_L_OPSIZE, /* 9876 */ IC_VEX_L_OPSIZE, /* 9877 */ IC_VEX_L_OPSIZE, /* 9878 */ IC_VEX_L_OPSIZE, /* 9879 */ IC_VEX_L_W_OPSIZE, /* 9880 */ IC_VEX_L_W_OPSIZE, /* 9881 */ IC_VEX_L_W_OPSIZE, /* 9882 */ IC_VEX_L_W_OPSIZE, /* 9883 */ IC_VEX_L_W_OPSIZE, /* 9884 */ IC_VEX_L_W_OPSIZE, /* 9885 */ IC_VEX_L_W_OPSIZE, /* 9886 */ IC_VEX_L_W_OPSIZE, /* 9887 */ IC_VEX_L, /* 9888 */ IC_VEX_L, /* 9889 */ IC_VEX_L_XS, /* 9890 */ IC_VEX_L_XS, /* 9891 */ IC_VEX_L_XD, /* 9892 */ IC_VEX_L_XD, /* 9893 */ IC_VEX_L_XD, /* 9894 */ IC_VEX_L_XD, /* 9895 */ IC_VEX_L_W, /* 9896 */ IC_VEX_L_W, /* 9897 */ IC_VEX_L_W_XS, /* 9898 */ IC_VEX_L_W_XS, /* 9899 */ IC_VEX_L_W_XD, /* 9900 */ IC_VEX_L_W_XD, /* 9901 */ IC_VEX_L_W_XD, /* 9902 */ IC_VEX_L_W_XD, /* 9903 */ IC_VEX_L_OPSIZE, /* 9904 */ IC_VEX_L_OPSIZE, /* 9905 */ IC_VEX_L_OPSIZE, /* 9906 */ IC_VEX_L_OPSIZE, /* 9907 */ IC_VEX_L_OPSIZE, /* 9908 */ IC_VEX_L_OPSIZE, /* 9909 */ IC_VEX_L_OPSIZE, /* 9910 */ IC_VEX_L_OPSIZE, /* 9911 */ IC_VEX_L_W_OPSIZE, /* 9912 */ IC_VEX_L_W_OPSIZE, /* 9913 */ IC_VEX_L_W_OPSIZE, /* 9914 */ IC_VEX_L_W_OPSIZE, /* 9915 */ IC_VEX_L_W_OPSIZE, /* 9916 */ IC_VEX_L_W_OPSIZE, /* 9917 */ IC_VEX_L_W_OPSIZE, /* 9918 */ IC_VEX_L_W_OPSIZE, /* 9919 */ IC_VEX_L, /* 9920 */ IC_VEX_L, /* 9921 */ IC_VEX_L_XS, /* 9922 */ IC_VEX_L_XS, /* 9923 */ IC_VEX_L_XD, /* 9924 */ IC_VEX_L_XD, /* 9925 */ IC_VEX_L_XD, /* 9926 */ IC_VEX_L_XD, /* 9927 */ IC_VEX_L_W, /* 9928 */ IC_VEX_L_W, /* 9929 */ IC_VEX_L_W_XS, /* 9930 */ IC_VEX_L_W_XS, /* 9931 */ IC_VEX_L_W_XD, /* 9932 */ IC_VEX_L_W_XD, /* 9933 */ IC_VEX_L_W_XD, /* 9934 */ IC_VEX_L_W_XD, /* 9935 */ IC_VEX_L_OPSIZE, /* 9936 */ IC_VEX_L_OPSIZE, /* 9937 */ IC_VEX_L_OPSIZE, /* 9938 */ IC_VEX_L_OPSIZE, /* 9939 */ IC_VEX_L_OPSIZE, /* 9940 */ IC_VEX_L_OPSIZE, /* 9941 */ IC_VEX_L_OPSIZE, /* 9942 */ IC_VEX_L_OPSIZE, /* 9943 */ IC_VEX_L_W_OPSIZE, /* 9944 */ IC_VEX_L_W_OPSIZE, /* 9945 */ IC_VEX_L_W_OPSIZE, /* 9946 */ IC_VEX_L_W_OPSIZE, /* 9947 */ IC_VEX_L_W_OPSIZE, /* 9948 */ IC_VEX_L_W_OPSIZE, /* 9949 */ IC_VEX_L_W_OPSIZE, /* 9950 */ IC_VEX_L_W_OPSIZE, /* 9951 */ IC_VEX_L, /* 9952 */ IC_VEX_L, /* 9953 */ IC_VEX_L_XS, /* 9954 */ IC_VEX_L_XS, /* 9955 */ IC_VEX_L_XD, /* 9956 */ IC_VEX_L_XD, /* 9957 */ IC_VEX_L_XD, /* 9958 */ IC_VEX_L_XD, /* 9959 */ IC_VEX_L_W, /* 9960 */ IC_VEX_L_W, /* 9961 */ IC_VEX_L_W_XS, /* 9962 */ IC_VEX_L_W_XS, /* 9963 */ IC_VEX_L_W_XD, /* 9964 */ IC_VEX_L_W_XD, /* 9965 */ IC_VEX_L_W_XD, /* 9966 */ IC_VEX_L_W_XD, /* 9967 */ IC_VEX_L_OPSIZE, /* 9968 */ IC_VEX_L_OPSIZE, /* 9969 */ IC_VEX_L_OPSIZE, /* 9970 */ IC_VEX_L_OPSIZE, /* 9971 */ IC_VEX_L_OPSIZE, /* 9972 */ IC_VEX_L_OPSIZE, /* 9973 */ IC_VEX_L_OPSIZE, /* 9974 */ IC_VEX_L_OPSIZE, /* 9975 */ IC_VEX_L_W_OPSIZE, /* 9976 */ IC_VEX_L_W_OPSIZE, /* 9977 */ IC_VEX_L_W_OPSIZE, /* 9978 */ IC_VEX_L_W_OPSIZE, /* 9979 */ IC_VEX_L_W_OPSIZE, /* 9980 */ IC_VEX_L_W_OPSIZE, /* 9981 */ IC_VEX_L_W_OPSIZE, /* 9982 */ IC_VEX_L_W_OPSIZE, /* 9983 */ IC_EVEX_L2_B, /* 9984 */ IC_EVEX_L2_B, /* 9985 */ IC_EVEX_L2_XS_B, /* 9986 */ IC_EVEX_L2_XS_B, /* 9987 */ IC_EVEX_L2_XD_B, /* 9988 */ IC_EVEX_L2_XD_B, /* 9989 */ IC_EVEX_L2_XD_B, /* 9990 */ IC_EVEX_L2_XD_B, /* 9991 */ IC_EVEX_L2_W_B, /* 9992 */ IC_EVEX_L2_W_B, /* 9993 */ IC_EVEX_L2_W_XS_B, /* 9994 */ IC_EVEX_L2_W_XS_B, /* 9995 */ IC_EVEX_L2_W_XD_B, /* 9996 */ IC_EVEX_L2_W_XD_B, /* 9997 */ IC_EVEX_L2_W_XD_B, /* 9998 */ IC_EVEX_L2_W_XD_B, /* 9999 */ IC_EVEX_L2_OPSIZE_B, /* 10000 */ IC_EVEX_L2_OPSIZE_B, /* 10001 */ IC_EVEX_L2_OPSIZE_B, /* 10002 */ IC_EVEX_L2_OPSIZE_B, /* 10003 */ IC_EVEX_L2_OPSIZE_B, /* 10004 */ IC_EVEX_L2_OPSIZE_B, /* 10005 */ IC_EVEX_L2_OPSIZE_B, /* 10006 */ IC_EVEX_L2_OPSIZE_B, /* 10007 */ IC_EVEX_L2_W_OPSIZE_B, /* 10008 */ IC_EVEX_L2_W_OPSIZE_B, /* 10009 */ IC_EVEX_L2_W_OPSIZE_B, /* 10010 */ IC_EVEX_L2_W_OPSIZE_B, /* 10011 */ IC_EVEX_L2_W_OPSIZE_B, /* 10012 */ IC_EVEX_L2_W_OPSIZE_B, /* 10013 */ IC_EVEX_L2_W_OPSIZE_B, /* 10014 */ IC_EVEX_L2_W_OPSIZE_B, /* 10015 */ IC_EVEX_L2_B, /* 10016 */ IC_EVEX_L2_B, /* 10017 */ IC_EVEX_L2_XS_B, /* 10018 */ IC_EVEX_L2_XS_B, /* 10019 */ IC_EVEX_L2_XD_B, /* 10020 */ IC_EVEX_L2_XD_B, /* 10021 */ IC_EVEX_L2_XD_B, /* 10022 */ IC_EVEX_L2_XD_B, /* 10023 */ IC_EVEX_L2_W_B, /* 10024 */ IC_EVEX_L2_W_B, /* 10025 */ IC_EVEX_L2_W_XS_B, /* 10026 */ IC_EVEX_L2_W_XS_B, /* 10027 */ IC_EVEX_L2_W_XD_B, /* 10028 */ IC_EVEX_L2_W_XD_B, /* 10029 */ IC_EVEX_L2_W_XD_B, /* 10030 */ IC_EVEX_L2_W_XD_B, /* 10031 */ IC_EVEX_L2_OPSIZE_B, /* 10032 */ IC_EVEX_L2_OPSIZE_B, /* 10033 */ IC_EVEX_L2_OPSIZE_B, /* 10034 */ IC_EVEX_L2_OPSIZE_B, /* 10035 */ IC_EVEX_L2_OPSIZE_B, /* 10036 */ IC_EVEX_L2_OPSIZE_B, /* 10037 */ IC_EVEX_L2_OPSIZE_B, /* 10038 */ IC_EVEX_L2_OPSIZE_B, /* 10039 */ IC_EVEX_L2_W_OPSIZE_B, /* 10040 */ IC_EVEX_L2_W_OPSIZE_B, /* 10041 */ IC_EVEX_L2_W_OPSIZE_B, /* 10042 */ IC_EVEX_L2_W_OPSIZE_B, /* 10043 */ IC_EVEX_L2_W_OPSIZE_B, /* 10044 */ IC_EVEX_L2_W_OPSIZE_B, /* 10045 */ IC_EVEX_L2_W_OPSIZE_B, /* 10046 */ IC_EVEX_L2_W_OPSIZE_B, /* 10047 */ IC_EVEX_L2_B, /* 10048 */ IC_EVEX_L2_B, /* 10049 */ IC_EVEX_L2_XS_B, /* 10050 */ IC_EVEX_L2_XS_B, /* 10051 */ IC_EVEX_L2_XD_B, /* 10052 */ IC_EVEX_L2_XD_B, /* 10053 */ IC_EVEX_L2_XD_B, /* 10054 */ IC_EVEX_L2_XD_B, /* 10055 */ IC_EVEX_L2_W_B, /* 10056 */ IC_EVEX_L2_W_B, /* 10057 */ IC_EVEX_L2_W_XS_B, /* 10058 */ IC_EVEX_L2_W_XS_B, /* 10059 */ IC_EVEX_L2_W_XD_B, /* 10060 */ IC_EVEX_L2_W_XD_B, /* 10061 */ IC_EVEX_L2_W_XD_B, /* 10062 */ IC_EVEX_L2_W_XD_B, /* 10063 */ IC_EVEX_L2_OPSIZE_B, /* 10064 */ IC_EVEX_L2_OPSIZE_B, /* 10065 */ IC_EVEX_L2_OPSIZE_B, /* 10066 */ IC_EVEX_L2_OPSIZE_B, /* 10067 */ IC_EVEX_L2_OPSIZE_B, /* 10068 */ IC_EVEX_L2_OPSIZE_B, /* 10069 */ IC_EVEX_L2_OPSIZE_B, /* 10070 */ IC_EVEX_L2_OPSIZE_B, /* 10071 */ IC_EVEX_L2_W_OPSIZE_B, /* 10072 */ IC_EVEX_L2_W_OPSIZE_B, /* 10073 */ IC_EVEX_L2_W_OPSIZE_B, /* 10074 */ IC_EVEX_L2_W_OPSIZE_B, /* 10075 */ IC_EVEX_L2_W_OPSIZE_B, /* 10076 */ IC_EVEX_L2_W_OPSIZE_B, /* 10077 */ IC_EVEX_L2_W_OPSIZE_B, /* 10078 */ IC_EVEX_L2_W_OPSIZE_B, /* 10079 */ IC_EVEX_L2_B, /* 10080 */ IC_EVEX_L2_B, /* 10081 */ IC_EVEX_L2_XS_B, /* 10082 */ IC_EVEX_L2_XS_B, /* 10083 */ IC_EVEX_L2_XD_B, /* 10084 */ IC_EVEX_L2_XD_B, /* 10085 */ IC_EVEX_L2_XD_B, /* 10086 */ IC_EVEX_L2_XD_B, /* 10087 */ IC_EVEX_L2_W_B, /* 10088 */ IC_EVEX_L2_W_B, /* 10089 */ IC_EVEX_L2_W_XS_B, /* 10090 */ IC_EVEX_L2_W_XS_B, /* 10091 */ IC_EVEX_L2_W_XD_B, /* 10092 */ IC_EVEX_L2_W_XD_B, /* 10093 */ IC_EVEX_L2_W_XD_B, /* 10094 */ IC_EVEX_L2_W_XD_B, /* 10095 */ IC_EVEX_L2_OPSIZE_B, /* 10096 */ IC_EVEX_L2_OPSIZE_B, /* 10097 */ IC_EVEX_L2_OPSIZE_B, /* 10098 */ IC_EVEX_L2_OPSIZE_B, /* 10099 */ IC_EVEX_L2_OPSIZE_B, /* 10100 */ IC_EVEX_L2_OPSIZE_B, /* 10101 */ IC_EVEX_L2_OPSIZE_B, /* 10102 */ IC_EVEX_L2_OPSIZE_B, /* 10103 */ IC_EVEX_L2_W_OPSIZE_B, /* 10104 */ IC_EVEX_L2_W_OPSIZE_B, /* 10105 */ IC_EVEX_L2_W_OPSIZE_B, /* 10106 */ IC_EVEX_L2_W_OPSIZE_B, /* 10107 */ IC_EVEX_L2_W_OPSIZE_B, /* 10108 */ IC_EVEX_L2_W_OPSIZE_B, /* 10109 */ IC_EVEX_L2_W_OPSIZE_B, /* 10110 */ IC_EVEX_L2_W_OPSIZE_B, /* 10111 */ IC_EVEX_L2_B, /* 10112 */ IC_EVEX_L2_B, /* 10113 */ IC_EVEX_L2_XS_B, /* 10114 */ IC_EVEX_L2_XS_B, /* 10115 */ IC_EVEX_L2_XD_B, /* 10116 */ IC_EVEX_L2_XD_B, /* 10117 */ IC_EVEX_L2_XD_B, /* 10118 */ IC_EVEX_L2_XD_B, /* 10119 */ IC_EVEX_L2_W_B, /* 10120 */ IC_EVEX_L2_W_B, /* 10121 */ IC_EVEX_L2_W_XS_B, /* 10122 */ IC_EVEX_L2_W_XS_B, /* 10123 */ IC_EVEX_L2_W_XD_B, /* 10124 */ IC_EVEX_L2_W_XD_B, /* 10125 */ IC_EVEX_L2_W_XD_B, /* 10126 */ IC_EVEX_L2_W_XD_B, /* 10127 */ IC_EVEX_L2_OPSIZE_B, /* 10128 */ IC_EVEX_L2_OPSIZE_B, /* 10129 */ IC_EVEX_L2_OPSIZE_B, /* 10130 */ IC_EVEX_L2_OPSIZE_B, /* 10131 */ IC_EVEX_L2_OPSIZE_B, /* 10132 */ IC_EVEX_L2_OPSIZE_B, /* 10133 */ IC_EVEX_L2_OPSIZE_B, /* 10134 */ IC_EVEX_L2_OPSIZE_B, /* 10135 */ IC_EVEX_L2_W_OPSIZE_B, /* 10136 */ IC_EVEX_L2_W_OPSIZE_B, /* 10137 */ IC_EVEX_L2_W_OPSIZE_B, /* 10138 */ IC_EVEX_L2_W_OPSIZE_B, /* 10139 */ IC_EVEX_L2_W_OPSIZE_B, /* 10140 */ IC_EVEX_L2_W_OPSIZE_B, /* 10141 */ IC_EVEX_L2_W_OPSIZE_B, /* 10142 */ IC_EVEX_L2_W_OPSIZE_B, /* 10143 */ IC_EVEX_L2_B, /* 10144 */ IC_EVEX_L2_B, /* 10145 */ IC_EVEX_L2_XS_B, /* 10146 */ IC_EVEX_L2_XS_B, /* 10147 */ IC_EVEX_L2_XD_B, /* 10148 */ IC_EVEX_L2_XD_B, /* 10149 */ IC_EVEX_L2_XD_B, /* 10150 */ IC_EVEX_L2_XD_B, /* 10151 */ IC_EVEX_L2_W_B, /* 10152 */ IC_EVEX_L2_W_B, /* 10153 */ IC_EVEX_L2_W_XS_B, /* 10154 */ IC_EVEX_L2_W_XS_B, /* 10155 */ IC_EVEX_L2_W_XD_B, /* 10156 */ IC_EVEX_L2_W_XD_B, /* 10157 */ IC_EVEX_L2_W_XD_B, /* 10158 */ IC_EVEX_L2_W_XD_B, /* 10159 */ IC_EVEX_L2_OPSIZE_B, /* 10160 */ IC_EVEX_L2_OPSIZE_B, /* 10161 */ IC_EVEX_L2_OPSIZE_B, /* 10162 */ IC_EVEX_L2_OPSIZE_B, /* 10163 */ IC_EVEX_L2_OPSIZE_B, /* 10164 */ IC_EVEX_L2_OPSIZE_B, /* 10165 */ IC_EVEX_L2_OPSIZE_B, /* 10166 */ IC_EVEX_L2_OPSIZE_B, /* 10167 */ IC_EVEX_L2_W_OPSIZE_B, /* 10168 */ IC_EVEX_L2_W_OPSIZE_B, /* 10169 */ IC_EVEX_L2_W_OPSIZE_B, /* 10170 */ IC_EVEX_L2_W_OPSIZE_B, /* 10171 */ IC_EVEX_L2_W_OPSIZE_B, /* 10172 */ IC_EVEX_L2_W_OPSIZE_B, /* 10173 */ IC_EVEX_L2_W_OPSIZE_B, /* 10174 */ IC_EVEX_L2_W_OPSIZE_B, /* 10175 */ IC_EVEX_L2_B, /* 10176 */ IC_EVEX_L2_B, /* 10177 */ IC_EVEX_L2_XS_B, /* 10178 */ IC_EVEX_L2_XS_B, /* 10179 */ IC_EVEX_L2_XD_B, /* 10180 */ IC_EVEX_L2_XD_B, /* 10181 */ IC_EVEX_L2_XD_B, /* 10182 */ IC_EVEX_L2_XD_B, /* 10183 */ IC_EVEX_L2_W_B, /* 10184 */ IC_EVEX_L2_W_B, /* 10185 */ IC_EVEX_L2_W_XS_B, /* 10186 */ IC_EVEX_L2_W_XS_B, /* 10187 */ IC_EVEX_L2_W_XD_B, /* 10188 */ IC_EVEX_L2_W_XD_B, /* 10189 */ IC_EVEX_L2_W_XD_B, /* 10190 */ IC_EVEX_L2_W_XD_B, /* 10191 */ IC_EVEX_L2_OPSIZE_B, /* 10192 */ IC_EVEX_L2_OPSIZE_B, /* 10193 */ IC_EVEX_L2_OPSIZE_B, /* 10194 */ IC_EVEX_L2_OPSIZE_B, /* 10195 */ IC_EVEX_L2_OPSIZE_B, /* 10196 */ IC_EVEX_L2_OPSIZE_B, /* 10197 */ IC_EVEX_L2_OPSIZE_B, /* 10198 */ IC_EVEX_L2_OPSIZE_B, /* 10199 */ IC_EVEX_L2_W_OPSIZE_B, /* 10200 */ IC_EVEX_L2_W_OPSIZE_B, /* 10201 */ IC_EVEX_L2_W_OPSIZE_B, /* 10202 */ IC_EVEX_L2_W_OPSIZE_B, /* 10203 */ IC_EVEX_L2_W_OPSIZE_B, /* 10204 */ IC_EVEX_L2_W_OPSIZE_B, /* 10205 */ IC_EVEX_L2_W_OPSIZE_B, /* 10206 */ IC_EVEX_L2_W_OPSIZE_B, /* 10207 */ IC_EVEX_L2_B, /* 10208 */ IC_EVEX_L2_B, /* 10209 */ IC_EVEX_L2_XS_B, /* 10210 */ IC_EVEX_L2_XS_B, /* 10211 */ IC_EVEX_L2_XD_B, /* 10212 */ IC_EVEX_L2_XD_B, /* 10213 */ IC_EVEX_L2_XD_B, /* 10214 */ IC_EVEX_L2_XD_B, /* 10215 */ IC_EVEX_L2_W_B, /* 10216 */ IC_EVEX_L2_W_B, /* 10217 */ IC_EVEX_L2_W_XS_B, /* 10218 */ IC_EVEX_L2_W_XS_B, /* 10219 */ IC_EVEX_L2_W_XD_B, /* 10220 */ IC_EVEX_L2_W_XD_B, /* 10221 */ IC_EVEX_L2_W_XD_B, /* 10222 */ IC_EVEX_L2_W_XD_B, /* 10223 */ IC_EVEX_L2_OPSIZE_B, /* 10224 */ IC_EVEX_L2_OPSIZE_B, /* 10225 */ IC_EVEX_L2_OPSIZE_B, /* 10226 */ IC_EVEX_L2_OPSIZE_B, /* 10227 */ IC_EVEX_L2_OPSIZE_B, /* 10228 */ IC_EVEX_L2_OPSIZE_B, /* 10229 */ IC_EVEX_L2_OPSIZE_B, /* 10230 */ IC_EVEX_L2_OPSIZE_B, /* 10231 */ IC_EVEX_L2_W_OPSIZE_B, /* 10232 */ IC_EVEX_L2_W_OPSIZE_B, /* 10233 */ IC_EVEX_L2_W_OPSIZE_B, /* 10234 */ IC_EVEX_L2_W_OPSIZE_B, /* 10235 */ IC_EVEX_L2_W_OPSIZE_B, /* 10236 */ IC_EVEX_L2_W_OPSIZE_B, /* 10237 */ IC_EVEX_L2_W_OPSIZE_B, /* 10238 */ IC_EVEX_L2_W_OPSIZE_B, /* 10239 */ IC, /* 10240 */ IC_64BIT, /* 10241 */ IC_XS, /* 10242 */ IC_64BIT_XS, /* 10243 */ IC_XD, /* 10244 */ IC_64BIT_XD, /* 10245 */ IC_XS, /* 10246 */ IC_64BIT_XS, /* 10247 */ IC, /* 10248 */ IC_64BIT_REXW, /* 10249 */ IC_XS, /* 10250 */ IC_64BIT_REXW_XS, /* 10251 */ IC_XD, /* 10252 */ IC_64BIT_REXW_XD, /* 10253 */ IC_XS, /* 10254 */ IC_64BIT_REXW_XS, /* 10255 */ IC_OPSIZE, /* 10256 */ IC_64BIT_OPSIZE, /* 10257 */ IC_XS_OPSIZE, /* 10258 */ IC_64BIT_XS_OPSIZE, /* 10259 */ IC_XD_OPSIZE, /* 10260 */ IC_64BIT_XD_OPSIZE, /* 10261 */ IC_XS_OPSIZE, /* 10262 */ IC_64BIT_XD_OPSIZE, /* 10263 */ IC_OPSIZE, /* 10264 */ IC_64BIT_REXW_OPSIZE, /* 10265 */ IC_XS_OPSIZE, /* 10266 */ IC_64BIT_REXW_XS, /* 10267 */ IC_XD_OPSIZE, /* 10268 */ IC_64BIT_REXW_XD, /* 10269 */ IC_XS_OPSIZE, /* 10270 */ IC_64BIT_REXW_XS, /* 10271 */ IC_ADSIZE, /* 10272 */ IC_64BIT_ADSIZE, /* 10273 */ IC_XS_ADSIZE, /* 10274 */ IC_64BIT_XS_ADSIZE, /* 10275 */ IC_XD_ADSIZE, /* 10276 */ IC_64BIT_XD_ADSIZE, /* 10277 */ IC_XS_ADSIZE, /* 10278 */ IC_64BIT_XD_ADSIZE, /* 10279 */ IC_ADSIZE, /* 10280 */ IC_64BIT_REXW_ADSIZE, /* 10281 */ IC_XS_ADSIZE, /* 10282 */ IC_64BIT_REXW_XS, /* 10283 */ IC_XD_ADSIZE, /* 10284 */ IC_64BIT_REXW_XD, /* 10285 */ IC_XS_ADSIZE, /* 10286 */ IC_64BIT_REXW_XS, /* 10287 */ IC_OPSIZE_ADSIZE, /* 10288 */ IC_64BIT_OPSIZE_ADSIZE, /* 10289 */ IC_XS_OPSIZE, /* 10290 */ IC_64BIT_XS_OPSIZE, /* 10291 */ IC_XD_OPSIZE, /* 10292 */ IC_64BIT_XD_OPSIZE, /* 10293 */ IC_XS_OPSIZE, /* 10294 */ IC_64BIT_XD_OPSIZE, /* 10295 */ IC_OPSIZE_ADSIZE, /* 10296 */ IC_64BIT_REXW_OPSIZE, /* 10297 */ IC_XS_OPSIZE, /* 10298 */ IC_64BIT_REXW_XS, /* 10299 */ IC_XD_OPSIZE, /* 10300 */ IC_64BIT_REXW_XD, /* 10301 */ IC_XS_OPSIZE, /* 10302 */ IC_64BIT_REXW_XS, /* 10303 */ IC_VEX, /* 10304 */ IC_VEX, /* 10305 */ IC_VEX_XS, /* 10306 */ IC_VEX_XS, /* 10307 */ IC_VEX_XD, /* 10308 */ IC_VEX_XD, /* 10309 */ IC_VEX_XD, /* 10310 */ IC_VEX_XD, /* 10311 */ IC_VEX_W, /* 10312 */ IC_VEX_W, /* 10313 */ IC_VEX_W_XS, /* 10314 */ IC_VEX_W_XS, /* 10315 */ IC_VEX_W_XD, /* 10316 */ IC_VEX_W_XD, /* 10317 */ IC_VEX_W_XD, /* 10318 */ IC_VEX_W_XD, /* 10319 */ IC_VEX_OPSIZE, /* 10320 */ IC_VEX_OPSIZE, /* 10321 */ IC_VEX_OPSIZE, /* 10322 */ IC_VEX_OPSIZE, /* 10323 */ IC_VEX_OPSIZE, /* 10324 */ IC_VEX_OPSIZE, /* 10325 */ IC_VEX_OPSIZE, /* 10326 */ IC_VEX_OPSIZE, /* 10327 */ IC_VEX_W_OPSIZE, /* 10328 */ IC_VEX_W_OPSIZE, /* 10329 */ IC_VEX_W_OPSIZE, /* 10330 */ IC_VEX_W_OPSIZE, /* 10331 */ IC_VEX_W_OPSIZE, /* 10332 */ IC_VEX_W_OPSIZE, /* 10333 */ IC_VEX_W_OPSIZE, /* 10334 */ IC_VEX_W_OPSIZE, /* 10335 */ IC_VEX, /* 10336 */ IC_VEX, /* 10337 */ IC_VEX_XS, /* 10338 */ IC_VEX_XS, /* 10339 */ IC_VEX_XD, /* 10340 */ IC_VEX_XD, /* 10341 */ IC_VEX_XD, /* 10342 */ IC_VEX_XD, /* 10343 */ IC_VEX_W, /* 10344 */ IC_VEX_W, /* 10345 */ IC_VEX_W_XS, /* 10346 */ IC_VEX_W_XS, /* 10347 */ IC_VEX_W_XD, /* 10348 */ IC_VEX_W_XD, /* 10349 */ IC_VEX_W_XD, /* 10350 */ IC_VEX_W_XD, /* 10351 */ IC_VEX_OPSIZE, /* 10352 */ IC_VEX_OPSIZE, /* 10353 */ IC_VEX_OPSIZE, /* 10354 */ IC_VEX_OPSIZE, /* 10355 */ IC_VEX_OPSIZE, /* 10356 */ IC_VEX_OPSIZE, /* 10357 */ IC_VEX_OPSIZE, /* 10358 */ IC_VEX_OPSIZE, /* 10359 */ IC_VEX_W_OPSIZE, /* 10360 */ IC_VEX_W_OPSIZE, /* 10361 */ IC_VEX_W_OPSIZE, /* 10362 */ IC_VEX_W_OPSIZE, /* 10363 */ IC_VEX_W_OPSIZE, /* 10364 */ IC_VEX_W_OPSIZE, /* 10365 */ IC_VEX_W_OPSIZE, /* 10366 */ IC_VEX_W_OPSIZE, /* 10367 */ IC_VEX_L, /* 10368 */ IC_VEX_L, /* 10369 */ IC_VEX_L_XS, /* 10370 */ IC_VEX_L_XS, /* 10371 */ IC_VEX_L_XD, /* 10372 */ IC_VEX_L_XD, /* 10373 */ IC_VEX_L_XD, /* 10374 */ IC_VEX_L_XD, /* 10375 */ IC_VEX_L_W, /* 10376 */ IC_VEX_L_W, /* 10377 */ IC_VEX_L_W_XS, /* 10378 */ IC_VEX_L_W_XS, /* 10379 */ IC_VEX_L_W_XD, /* 10380 */ IC_VEX_L_W_XD, /* 10381 */ IC_VEX_L_W_XD, /* 10382 */ IC_VEX_L_W_XD, /* 10383 */ IC_VEX_L_OPSIZE, /* 10384 */ IC_VEX_L_OPSIZE, /* 10385 */ IC_VEX_L_OPSIZE, /* 10386 */ IC_VEX_L_OPSIZE, /* 10387 */ IC_VEX_L_OPSIZE, /* 10388 */ IC_VEX_L_OPSIZE, /* 10389 */ IC_VEX_L_OPSIZE, /* 10390 */ IC_VEX_L_OPSIZE, /* 10391 */ IC_VEX_L_W_OPSIZE, /* 10392 */ IC_VEX_L_W_OPSIZE, /* 10393 */ IC_VEX_L_W_OPSIZE, /* 10394 */ IC_VEX_L_W_OPSIZE, /* 10395 */ IC_VEX_L_W_OPSIZE, /* 10396 */ IC_VEX_L_W_OPSIZE, /* 10397 */ IC_VEX_L_W_OPSIZE, /* 10398 */ IC_VEX_L_W_OPSIZE, /* 10399 */ IC_VEX_L, /* 10400 */ IC_VEX_L, /* 10401 */ IC_VEX_L_XS, /* 10402 */ IC_VEX_L_XS, /* 10403 */ IC_VEX_L_XD, /* 10404 */ IC_VEX_L_XD, /* 10405 */ IC_VEX_L_XD, /* 10406 */ IC_VEX_L_XD, /* 10407 */ IC_VEX_L_W, /* 10408 */ IC_VEX_L_W, /* 10409 */ IC_VEX_L_W_XS, /* 10410 */ IC_VEX_L_W_XS, /* 10411 */ IC_VEX_L_W_XD, /* 10412 */ IC_VEX_L_W_XD, /* 10413 */ IC_VEX_L_W_XD, /* 10414 */ IC_VEX_L_W_XD, /* 10415 */ IC_VEX_L_OPSIZE, /* 10416 */ IC_VEX_L_OPSIZE, /* 10417 */ IC_VEX_L_OPSIZE, /* 10418 */ IC_VEX_L_OPSIZE, /* 10419 */ IC_VEX_L_OPSIZE, /* 10420 */ IC_VEX_L_OPSIZE, /* 10421 */ IC_VEX_L_OPSIZE, /* 10422 */ IC_VEX_L_OPSIZE, /* 10423 */ IC_VEX_L_W_OPSIZE, /* 10424 */ IC_VEX_L_W_OPSIZE, /* 10425 */ IC_VEX_L_W_OPSIZE, /* 10426 */ IC_VEX_L_W_OPSIZE, /* 10427 */ IC_VEX_L_W_OPSIZE, /* 10428 */ IC_VEX_L_W_OPSIZE, /* 10429 */ IC_VEX_L_W_OPSIZE, /* 10430 */ IC_VEX_L_W_OPSIZE, /* 10431 */ IC_VEX_L, /* 10432 */ IC_VEX_L, /* 10433 */ IC_VEX_L_XS, /* 10434 */ IC_VEX_L_XS, /* 10435 */ IC_VEX_L_XD, /* 10436 */ IC_VEX_L_XD, /* 10437 */ IC_VEX_L_XD, /* 10438 */ IC_VEX_L_XD, /* 10439 */ IC_VEX_L_W, /* 10440 */ IC_VEX_L_W, /* 10441 */ IC_VEX_L_W_XS, /* 10442 */ IC_VEX_L_W_XS, /* 10443 */ IC_VEX_L_W_XD, /* 10444 */ IC_VEX_L_W_XD, /* 10445 */ IC_VEX_L_W_XD, /* 10446 */ IC_VEX_L_W_XD, /* 10447 */ IC_VEX_L_OPSIZE, /* 10448 */ IC_VEX_L_OPSIZE, /* 10449 */ IC_VEX_L_OPSIZE, /* 10450 */ IC_VEX_L_OPSIZE, /* 10451 */ IC_VEX_L_OPSIZE, /* 10452 */ IC_VEX_L_OPSIZE, /* 10453 */ IC_VEX_L_OPSIZE, /* 10454 */ IC_VEX_L_OPSIZE, /* 10455 */ IC_VEX_L_W_OPSIZE, /* 10456 */ IC_VEX_L_W_OPSIZE, /* 10457 */ IC_VEX_L_W_OPSIZE, /* 10458 */ IC_VEX_L_W_OPSIZE, /* 10459 */ IC_VEX_L_W_OPSIZE, /* 10460 */ IC_VEX_L_W_OPSIZE, /* 10461 */ IC_VEX_L_W_OPSIZE, /* 10462 */ IC_VEX_L_W_OPSIZE, /* 10463 */ IC_VEX_L, /* 10464 */ IC_VEX_L, /* 10465 */ IC_VEX_L_XS, /* 10466 */ IC_VEX_L_XS, /* 10467 */ IC_VEX_L_XD, /* 10468 */ IC_VEX_L_XD, /* 10469 */ IC_VEX_L_XD, /* 10470 */ IC_VEX_L_XD, /* 10471 */ IC_VEX_L_W, /* 10472 */ IC_VEX_L_W, /* 10473 */ IC_VEX_L_W_XS, /* 10474 */ IC_VEX_L_W_XS, /* 10475 */ IC_VEX_L_W_XD, /* 10476 */ IC_VEX_L_W_XD, /* 10477 */ IC_VEX_L_W_XD, /* 10478 */ IC_VEX_L_W_XD, /* 10479 */ IC_VEX_L_OPSIZE, /* 10480 */ IC_VEX_L_OPSIZE, /* 10481 */ IC_VEX_L_OPSIZE, /* 10482 */ IC_VEX_L_OPSIZE, /* 10483 */ IC_VEX_L_OPSIZE, /* 10484 */ IC_VEX_L_OPSIZE, /* 10485 */ IC_VEX_L_OPSIZE, /* 10486 */ IC_VEX_L_OPSIZE, /* 10487 */ IC_VEX_L_W_OPSIZE, /* 10488 */ IC_VEX_L_W_OPSIZE, /* 10489 */ IC_VEX_L_W_OPSIZE, /* 10490 */ IC_VEX_L_W_OPSIZE, /* 10491 */ IC_VEX_L_W_OPSIZE, /* 10492 */ IC_VEX_L_W_OPSIZE, /* 10493 */ IC_VEX_L_W_OPSIZE, /* 10494 */ IC_VEX_L_W_OPSIZE, /* 10495 */ IC_EVEX_K_B, /* 10496 */ IC_EVEX_K_B, /* 10497 */ IC_EVEX_XS_K_B, /* 10498 */ IC_EVEX_XS_K_B, /* 10499 */ IC_EVEX_XD_K_B, /* 10500 */ IC_EVEX_XD_K_B, /* 10501 */ IC_EVEX_XD_K_B, /* 10502 */ IC_EVEX_XD_K_B, /* 10503 */ IC_EVEX_W_K_B, /* 10504 */ IC_EVEX_W_K_B, /* 10505 */ IC_EVEX_W_XS_K_B, /* 10506 */ IC_EVEX_W_XS_K_B, /* 10507 */ IC_EVEX_W_XD_K_B, /* 10508 */ IC_EVEX_W_XD_K_B, /* 10509 */ IC_EVEX_W_XD_K_B, /* 10510 */ IC_EVEX_W_XD_K_B, /* 10511 */ IC_EVEX_OPSIZE_K_B, /* 10512 */ IC_EVEX_OPSIZE_K_B, /* 10513 */ IC_EVEX_OPSIZE_K_B, /* 10514 */ IC_EVEX_OPSIZE_K_B, /* 10515 */ IC_EVEX_OPSIZE_K_B, /* 10516 */ IC_EVEX_OPSIZE_K_B, /* 10517 */ IC_EVEX_OPSIZE_K_B, /* 10518 */ IC_EVEX_OPSIZE_K_B, /* 10519 */ IC_EVEX_W_OPSIZE_K_B, /* 10520 */ IC_EVEX_W_OPSIZE_K_B, /* 10521 */ IC_EVEX_W_OPSIZE_K_B, /* 10522 */ IC_EVEX_W_OPSIZE_K_B, /* 10523 */ IC_EVEX_W_OPSIZE_K_B, /* 10524 */ IC_EVEX_W_OPSIZE_K_B, /* 10525 */ IC_EVEX_W_OPSIZE_K_B, /* 10526 */ IC_EVEX_W_OPSIZE_K_B, /* 10527 */ IC_EVEX_K_B, /* 10528 */ IC_EVEX_K_B, /* 10529 */ IC_EVEX_XS_K_B, /* 10530 */ IC_EVEX_XS_K_B, /* 10531 */ IC_EVEX_XD_K_B, /* 10532 */ IC_EVEX_XD_K_B, /* 10533 */ IC_EVEX_XD_K_B, /* 10534 */ IC_EVEX_XD_K_B, /* 10535 */ IC_EVEX_W_K_B, /* 10536 */ IC_EVEX_W_K_B, /* 10537 */ IC_EVEX_W_XS_K_B, /* 10538 */ IC_EVEX_W_XS_K_B, /* 10539 */ IC_EVEX_W_XD_K_B, /* 10540 */ IC_EVEX_W_XD_K_B, /* 10541 */ IC_EVEX_W_XD_K_B, /* 10542 */ IC_EVEX_W_XD_K_B, /* 10543 */ IC_EVEX_OPSIZE_K_B, /* 10544 */ IC_EVEX_OPSIZE_K_B, /* 10545 */ IC_EVEX_OPSIZE_K_B, /* 10546 */ IC_EVEX_OPSIZE_K_B, /* 10547 */ IC_EVEX_OPSIZE_K_B, /* 10548 */ IC_EVEX_OPSIZE_K_B, /* 10549 */ IC_EVEX_OPSIZE_K_B, /* 10550 */ IC_EVEX_OPSIZE_K_B, /* 10551 */ IC_EVEX_W_OPSIZE_K_B, /* 10552 */ IC_EVEX_W_OPSIZE_K_B, /* 10553 */ IC_EVEX_W_OPSIZE_K_B, /* 10554 */ IC_EVEX_W_OPSIZE_K_B, /* 10555 */ IC_EVEX_W_OPSIZE_K_B, /* 10556 */ IC_EVEX_W_OPSIZE_K_B, /* 10557 */ IC_EVEX_W_OPSIZE_K_B, /* 10558 */ IC_EVEX_W_OPSIZE_K_B, /* 10559 */ IC_EVEX_K_B, /* 10560 */ IC_EVEX_K_B, /* 10561 */ IC_EVEX_XS_K_B, /* 10562 */ IC_EVEX_XS_K_B, /* 10563 */ IC_EVEX_XD_K_B, /* 10564 */ IC_EVEX_XD_K_B, /* 10565 */ IC_EVEX_XD_K_B, /* 10566 */ IC_EVEX_XD_K_B, /* 10567 */ IC_EVEX_W_K_B, /* 10568 */ IC_EVEX_W_K_B, /* 10569 */ IC_EVEX_W_XS_K_B, /* 10570 */ IC_EVEX_W_XS_K_B, /* 10571 */ IC_EVEX_W_XD_K_B, /* 10572 */ IC_EVEX_W_XD_K_B, /* 10573 */ IC_EVEX_W_XD_K_B, /* 10574 */ IC_EVEX_W_XD_K_B, /* 10575 */ IC_EVEX_OPSIZE_K_B, /* 10576 */ IC_EVEX_OPSIZE_K_B, /* 10577 */ IC_EVEX_OPSIZE_K_B, /* 10578 */ IC_EVEX_OPSIZE_K_B, /* 10579 */ IC_EVEX_OPSIZE_K_B, /* 10580 */ IC_EVEX_OPSIZE_K_B, /* 10581 */ IC_EVEX_OPSIZE_K_B, /* 10582 */ IC_EVEX_OPSIZE_K_B, /* 10583 */ IC_EVEX_W_OPSIZE_K_B, /* 10584 */ IC_EVEX_W_OPSIZE_K_B, /* 10585 */ IC_EVEX_W_OPSIZE_K_B, /* 10586 */ IC_EVEX_W_OPSIZE_K_B, /* 10587 */ IC_EVEX_W_OPSIZE_K_B, /* 10588 */ IC_EVEX_W_OPSIZE_K_B, /* 10589 */ IC_EVEX_W_OPSIZE_K_B, /* 10590 */ IC_EVEX_W_OPSIZE_K_B, /* 10591 */ IC_EVEX_K_B, /* 10592 */ IC_EVEX_K_B, /* 10593 */ IC_EVEX_XS_K_B, /* 10594 */ IC_EVEX_XS_K_B, /* 10595 */ IC_EVEX_XD_K_B, /* 10596 */ IC_EVEX_XD_K_B, /* 10597 */ IC_EVEX_XD_K_B, /* 10598 */ IC_EVEX_XD_K_B, /* 10599 */ IC_EVEX_W_K_B, /* 10600 */ IC_EVEX_W_K_B, /* 10601 */ IC_EVEX_W_XS_K_B, /* 10602 */ IC_EVEX_W_XS_K_B, /* 10603 */ IC_EVEX_W_XD_K_B, /* 10604 */ IC_EVEX_W_XD_K_B, /* 10605 */ IC_EVEX_W_XD_K_B, /* 10606 */ IC_EVEX_W_XD_K_B, /* 10607 */ IC_EVEX_OPSIZE_K_B, /* 10608 */ IC_EVEX_OPSIZE_K_B, /* 10609 */ IC_EVEX_OPSIZE_K_B, /* 10610 */ IC_EVEX_OPSIZE_K_B, /* 10611 */ IC_EVEX_OPSIZE_K_B, /* 10612 */ IC_EVEX_OPSIZE_K_B, /* 10613 */ IC_EVEX_OPSIZE_K_B, /* 10614 */ IC_EVEX_OPSIZE_K_B, /* 10615 */ IC_EVEX_W_OPSIZE_K_B, /* 10616 */ IC_EVEX_W_OPSIZE_K_B, /* 10617 */ IC_EVEX_W_OPSIZE_K_B, /* 10618 */ IC_EVEX_W_OPSIZE_K_B, /* 10619 */ IC_EVEX_W_OPSIZE_K_B, /* 10620 */ IC_EVEX_W_OPSIZE_K_B, /* 10621 */ IC_EVEX_W_OPSIZE_K_B, /* 10622 */ IC_EVEX_W_OPSIZE_K_B, /* 10623 */ IC_EVEX_K_B, /* 10624 */ IC_EVEX_K_B, /* 10625 */ IC_EVEX_XS_K_B, /* 10626 */ IC_EVEX_XS_K_B, /* 10627 */ IC_EVEX_XD_K_B, /* 10628 */ IC_EVEX_XD_K_B, /* 10629 */ IC_EVEX_XD_K_B, /* 10630 */ IC_EVEX_XD_K_B, /* 10631 */ IC_EVEX_W_K_B, /* 10632 */ IC_EVEX_W_K_B, /* 10633 */ IC_EVEX_W_XS_K_B, /* 10634 */ IC_EVEX_W_XS_K_B, /* 10635 */ IC_EVEX_W_XD_K_B, /* 10636 */ IC_EVEX_W_XD_K_B, /* 10637 */ IC_EVEX_W_XD_K_B, /* 10638 */ IC_EVEX_W_XD_K_B, /* 10639 */ IC_EVEX_OPSIZE_K_B, /* 10640 */ IC_EVEX_OPSIZE_K_B, /* 10641 */ IC_EVEX_OPSIZE_K_B, /* 10642 */ IC_EVEX_OPSIZE_K_B, /* 10643 */ IC_EVEX_OPSIZE_K_B, /* 10644 */ IC_EVEX_OPSIZE_K_B, /* 10645 */ IC_EVEX_OPSIZE_K_B, /* 10646 */ IC_EVEX_OPSIZE_K_B, /* 10647 */ IC_EVEX_W_OPSIZE_K_B, /* 10648 */ IC_EVEX_W_OPSIZE_K_B, /* 10649 */ IC_EVEX_W_OPSIZE_K_B, /* 10650 */ IC_EVEX_W_OPSIZE_K_B, /* 10651 */ IC_EVEX_W_OPSIZE_K_B, /* 10652 */ IC_EVEX_W_OPSIZE_K_B, /* 10653 */ IC_EVEX_W_OPSIZE_K_B, /* 10654 */ IC_EVEX_W_OPSIZE_K_B, /* 10655 */ IC_EVEX_K_B, /* 10656 */ IC_EVEX_K_B, /* 10657 */ IC_EVEX_XS_K_B, /* 10658 */ IC_EVEX_XS_K_B, /* 10659 */ IC_EVEX_XD_K_B, /* 10660 */ IC_EVEX_XD_K_B, /* 10661 */ IC_EVEX_XD_K_B, /* 10662 */ IC_EVEX_XD_K_B, /* 10663 */ IC_EVEX_W_K_B, /* 10664 */ IC_EVEX_W_K_B, /* 10665 */ IC_EVEX_W_XS_K_B, /* 10666 */ IC_EVEX_W_XS_K_B, /* 10667 */ IC_EVEX_W_XD_K_B, /* 10668 */ IC_EVEX_W_XD_K_B, /* 10669 */ IC_EVEX_W_XD_K_B, /* 10670 */ IC_EVEX_W_XD_K_B, /* 10671 */ IC_EVEX_OPSIZE_K_B, /* 10672 */ IC_EVEX_OPSIZE_K_B, /* 10673 */ IC_EVEX_OPSIZE_K_B, /* 10674 */ IC_EVEX_OPSIZE_K_B, /* 10675 */ IC_EVEX_OPSIZE_K_B, /* 10676 */ IC_EVEX_OPSIZE_K_B, /* 10677 */ IC_EVEX_OPSIZE_K_B, /* 10678 */ IC_EVEX_OPSIZE_K_B, /* 10679 */ IC_EVEX_W_OPSIZE_K_B, /* 10680 */ IC_EVEX_W_OPSIZE_K_B, /* 10681 */ IC_EVEX_W_OPSIZE_K_B, /* 10682 */ IC_EVEX_W_OPSIZE_K_B, /* 10683 */ IC_EVEX_W_OPSIZE_K_B, /* 10684 */ IC_EVEX_W_OPSIZE_K_B, /* 10685 */ IC_EVEX_W_OPSIZE_K_B, /* 10686 */ IC_EVEX_W_OPSIZE_K_B, /* 10687 */ IC_EVEX_K_B, /* 10688 */ IC_EVEX_K_B, /* 10689 */ IC_EVEX_XS_K_B, /* 10690 */ IC_EVEX_XS_K_B, /* 10691 */ IC_EVEX_XD_K_B, /* 10692 */ IC_EVEX_XD_K_B, /* 10693 */ IC_EVEX_XD_K_B, /* 10694 */ IC_EVEX_XD_K_B, /* 10695 */ IC_EVEX_W_K_B, /* 10696 */ IC_EVEX_W_K_B, /* 10697 */ IC_EVEX_W_XS_K_B, /* 10698 */ IC_EVEX_W_XS_K_B, /* 10699 */ IC_EVEX_W_XD_K_B, /* 10700 */ IC_EVEX_W_XD_K_B, /* 10701 */ IC_EVEX_W_XD_K_B, /* 10702 */ IC_EVEX_W_XD_K_B, /* 10703 */ IC_EVEX_OPSIZE_K_B, /* 10704 */ IC_EVEX_OPSIZE_K_B, /* 10705 */ IC_EVEX_OPSIZE_K_B, /* 10706 */ IC_EVEX_OPSIZE_K_B, /* 10707 */ IC_EVEX_OPSIZE_K_B, /* 10708 */ IC_EVEX_OPSIZE_K_B, /* 10709 */ IC_EVEX_OPSIZE_K_B, /* 10710 */ IC_EVEX_OPSIZE_K_B, /* 10711 */ IC_EVEX_W_OPSIZE_K_B, /* 10712 */ IC_EVEX_W_OPSIZE_K_B, /* 10713 */ IC_EVEX_W_OPSIZE_K_B, /* 10714 */ IC_EVEX_W_OPSIZE_K_B, /* 10715 */ IC_EVEX_W_OPSIZE_K_B, /* 10716 */ IC_EVEX_W_OPSIZE_K_B, /* 10717 */ IC_EVEX_W_OPSIZE_K_B, /* 10718 */ IC_EVEX_W_OPSIZE_K_B, /* 10719 */ IC_EVEX_K_B, /* 10720 */ IC_EVEX_K_B, /* 10721 */ IC_EVEX_XS_K_B, /* 10722 */ IC_EVEX_XS_K_B, /* 10723 */ IC_EVEX_XD_K_B, /* 10724 */ IC_EVEX_XD_K_B, /* 10725 */ IC_EVEX_XD_K_B, /* 10726 */ IC_EVEX_XD_K_B, /* 10727 */ IC_EVEX_W_K_B, /* 10728 */ IC_EVEX_W_K_B, /* 10729 */ IC_EVEX_W_XS_K_B, /* 10730 */ IC_EVEX_W_XS_K_B, /* 10731 */ IC_EVEX_W_XD_K_B, /* 10732 */ IC_EVEX_W_XD_K_B, /* 10733 */ IC_EVEX_W_XD_K_B, /* 10734 */ IC_EVEX_W_XD_K_B, /* 10735 */ IC_EVEX_OPSIZE_K_B, /* 10736 */ IC_EVEX_OPSIZE_K_B, /* 10737 */ IC_EVEX_OPSIZE_K_B, /* 10738 */ IC_EVEX_OPSIZE_K_B, /* 10739 */ IC_EVEX_OPSIZE_K_B, /* 10740 */ IC_EVEX_OPSIZE_K_B, /* 10741 */ IC_EVEX_OPSIZE_K_B, /* 10742 */ IC_EVEX_OPSIZE_K_B, /* 10743 */ IC_EVEX_W_OPSIZE_K_B, /* 10744 */ IC_EVEX_W_OPSIZE_K_B, /* 10745 */ IC_EVEX_W_OPSIZE_K_B, /* 10746 */ IC_EVEX_W_OPSIZE_K_B, /* 10747 */ IC_EVEX_W_OPSIZE_K_B, /* 10748 */ IC_EVEX_W_OPSIZE_K_B, /* 10749 */ IC_EVEX_W_OPSIZE_K_B, /* 10750 */ IC_EVEX_W_OPSIZE_K_B, /* 10751 */ IC, /* 10752 */ IC_64BIT, /* 10753 */ IC_XS, /* 10754 */ IC_64BIT_XS, /* 10755 */ IC_XD, /* 10756 */ IC_64BIT_XD, /* 10757 */ IC_XS, /* 10758 */ IC_64BIT_XS, /* 10759 */ IC, /* 10760 */ IC_64BIT_REXW, /* 10761 */ IC_XS, /* 10762 */ IC_64BIT_REXW_XS, /* 10763 */ IC_XD, /* 10764 */ IC_64BIT_REXW_XD, /* 10765 */ IC_XS, /* 10766 */ IC_64BIT_REXW_XS, /* 10767 */ IC_OPSIZE, /* 10768 */ IC_64BIT_OPSIZE, /* 10769 */ IC_XS_OPSIZE, /* 10770 */ IC_64BIT_XS_OPSIZE, /* 10771 */ IC_XD_OPSIZE, /* 10772 */ IC_64BIT_XD_OPSIZE, /* 10773 */ IC_XS_OPSIZE, /* 10774 */ IC_64BIT_XD_OPSIZE, /* 10775 */ IC_OPSIZE, /* 10776 */ IC_64BIT_REXW_OPSIZE, /* 10777 */ IC_XS_OPSIZE, /* 10778 */ IC_64BIT_REXW_XS, /* 10779 */ IC_XD_OPSIZE, /* 10780 */ IC_64BIT_REXW_XD, /* 10781 */ IC_XS_OPSIZE, /* 10782 */ IC_64BIT_REXW_XS, /* 10783 */ IC_ADSIZE, /* 10784 */ IC_64BIT_ADSIZE, /* 10785 */ IC_XS_ADSIZE, /* 10786 */ IC_64BIT_XS_ADSIZE, /* 10787 */ IC_XD_ADSIZE, /* 10788 */ IC_64BIT_XD_ADSIZE, /* 10789 */ IC_XS_ADSIZE, /* 10790 */ IC_64BIT_XD_ADSIZE, /* 10791 */ IC_ADSIZE, /* 10792 */ IC_64BIT_REXW_ADSIZE, /* 10793 */ IC_XS_ADSIZE, /* 10794 */ IC_64BIT_REXW_XS, /* 10795 */ IC_XD_ADSIZE, /* 10796 */ IC_64BIT_REXW_XD, /* 10797 */ IC_XS_ADSIZE, /* 10798 */ IC_64BIT_REXW_XS, /* 10799 */ IC_OPSIZE_ADSIZE, /* 10800 */ IC_64BIT_OPSIZE_ADSIZE, /* 10801 */ IC_XS_OPSIZE, /* 10802 */ IC_64BIT_XS_OPSIZE, /* 10803 */ IC_XD_OPSIZE, /* 10804 */ IC_64BIT_XD_OPSIZE, /* 10805 */ IC_XS_OPSIZE, /* 10806 */ IC_64BIT_XD_OPSIZE, /* 10807 */ IC_OPSIZE_ADSIZE, /* 10808 */ IC_64BIT_REXW_OPSIZE, /* 10809 */ IC_XS_OPSIZE, /* 10810 */ IC_64BIT_REXW_XS, /* 10811 */ IC_XD_OPSIZE, /* 10812 */ IC_64BIT_REXW_XD, /* 10813 */ IC_XS_OPSIZE, /* 10814 */ IC_64BIT_REXW_XS, /* 10815 */ IC_VEX, /* 10816 */ IC_VEX, /* 10817 */ IC_VEX_XS, /* 10818 */ IC_VEX_XS, /* 10819 */ IC_VEX_XD, /* 10820 */ IC_VEX_XD, /* 10821 */ IC_VEX_XD, /* 10822 */ IC_VEX_XD, /* 10823 */ IC_VEX_W, /* 10824 */ IC_VEX_W, /* 10825 */ IC_VEX_W_XS, /* 10826 */ IC_VEX_W_XS, /* 10827 */ IC_VEX_W_XD, /* 10828 */ IC_VEX_W_XD, /* 10829 */ IC_VEX_W_XD, /* 10830 */ IC_VEX_W_XD, /* 10831 */ IC_VEX_OPSIZE, /* 10832 */ IC_VEX_OPSIZE, /* 10833 */ IC_VEX_OPSIZE, /* 10834 */ IC_VEX_OPSIZE, /* 10835 */ IC_VEX_OPSIZE, /* 10836 */ IC_VEX_OPSIZE, /* 10837 */ IC_VEX_OPSIZE, /* 10838 */ IC_VEX_OPSIZE, /* 10839 */ IC_VEX_W_OPSIZE, /* 10840 */ IC_VEX_W_OPSIZE, /* 10841 */ IC_VEX_W_OPSIZE, /* 10842 */ IC_VEX_W_OPSIZE, /* 10843 */ IC_VEX_W_OPSIZE, /* 10844 */ IC_VEX_W_OPSIZE, /* 10845 */ IC_VEX_W_OPSIZE, /* 10846 */ IC_VEX_W_OPSIZE, /* 10847 */ IC_VEX, /* 10848 */ IC_VEX, /* 10849 */ IC_VEX_XS, /* 10850 */ IC_VEX_XS, /* 10851 */ IC_VEX_XD, /* 10852 */ IC_VEX_XD, /* 10853 */ IC_VEX_XD, /* 10854 */ IC_VEX_XD, /* 10855 */ IC_VEX_W, /* 10856 */ IC_VEX_W, /* 10857 */ IC_VEX_W_XS, /* 10858 */ IC_VEX_W_XS, /* 10859 */ IC_VEX_W_XD, /* 10860 */ IC_VEX_W_XD, /* 10861 */ IC_VEX_W_XD, /* 10862 */ IC_VEX_W_XD, /* 10863 */ IC_VEX_OPSIZE, /* 10864 */ IC_VEX_OPSIZE, /* 10865 */ IC_VEX_OPSIZE, /* 10866 */ IC_VEX_OPSIZE, /* 10867 */ IC_VEX_OPSIZE, /* 10868 */ IC_VEX_OPSIZE, /* 10869 */ IC_VEX_OPSIZE, /* 10870 */ IC_VEX_OPSIZE, /* 10871 */ IC_VEX_W_OPSIZE, /* 10872 */ IC_VEX_W_OPSIZE, /* 10873 */ IC_VEX_W_OPSIZE, /* 10874 */ IC_VEX_W_OPSIZE, /* 10875 */ IC_VEX_W_OPSIZE, /* 10876 */ IC_VEX_W_OPSIZE, /* 10877 */ IC_VEX_W_OPSIZE, /* 10878 */ IC_VEX_W_OPSIZE, /* 10879 */ IC_VEX_L, /* 10880 */ IC_VEX_L, /* 10881 */ IC_VEX_L_XS, /* 10882 */ IC_VEX_L_XS, /* 10883 */ IC_VEX_L_XD, /* 10884 */ IC_VEX_L_XD, /* 10885 */ IC_VEX_L_XD, /* 10886 */ IC_VEX_L_XD, /* 10887 */ IC_VEX_L_W, /* 10888 */ IC_VEX_L_W, /* 10889 */ IC_VEX_L_W_XS, /* 10890 */ IC_VEX_L_W_XS, /* 10891 */ IC_VEX_L_W_XD, /* 10892 */ IC_VEX_L_W_XD, /* 10893 */ IC_VEX_L_W_XD, /* 10894 */ IC_VEX_L_W_XD, /* 10895 */ IC_VEX_L_OPSIZE, /* 10896 */ IC_VEX_L_OPSIZE, /* 10897 */ IC_VEX_L_OPSIZE, /* 10898 */ IC_VEX_L_OPSIZE, /* 10899 */ IC_VEX_L_OPSIZE, /* 10900 */ IC_VEX_L_OPSIZE, /* 10901 */ IC_VEX_L_OPSIZE, /* 10902 */ IC_VEX_L_OPSIZE, /* 10903 */ IC_VEX_L_W_OPSIZE, /* 10904 */ IC_VEX_L_W_OPSIZE, /* 10905 */ IC_VEX_L_W_OPSIZE, /* 10906 */ IC_VEX_L_W_OPSIZE, /* 10907 */ IC_VEX_L_W_OPSIZE, /* 10908 */ IC_VEX_L_W_OPSIZE, /* 10909 */ IC_VEX_L_W_OPSIZE, /* 10910 */ IC_VEX_L_W_OPSIZE, /* 10911 */ IC_VEX_L, /* 10912 */ IC_VEX_L, /* 10913 */ IC_VEX_L_XS, /* 10914 */ IC_VEX_L_XS, /* 10915 */ IC_VEX_L_XD, /* 10916 */ IC_VEX_L_XD, /* 10917 */ IC_VEX_L_XD, /* 10918 */ IC_VEX_L_XD, /* 10919 */ IC_VEX_L_W, /* 10920 */ IC_VEX_L_W, /* 10921 */ IC_VEX_L_W_XS, /* 10922 */ IC_VEX_L_W_XS, /* 10923 */ IC_VEX_L_W_XD, /* 10924 */ IC_VEX_L_W_XD, /* 10925 */ IC_VEX_L_W_XD, /* 10926 */ IC_VEX_L_W_XD, /* 10927 */ IC_VEX_L_OPSIZE, /* 10928 */ IC_VEX_L_OPSIZE, /* 10929 */ IC_VEX_L_OPSIZE, /* 10930 */ IC_VEX_L_OPSIZE, /* 10931 */ IC_VEX_L_OPSIZE, /* 10932 */ IC_VEX_L_OPSIZE, /* 10933 */ IC_VEX_L_OPSIZE, /* 10934 */ IC_VEX_L_OPSIZE, /* 10935 */ IC_VEX_L_W_OPSIZE, /* 10936 */ IC_VEX_L_W_OPSIZE, /* 10937 */ IC_VEX_L_W_OPSIZE, /* 10938 */ IC_VEX_L_W_OPSIZE, /* 10939 */ IC_VEX_L_W_OPSIZE, /* 10940 */ IC_VEX_L_W_OPSIZE, /* 10941 */ IC_VEX_L_W_OPSIZE, /* 10942 */ IC_VEX_L_W_OPSIZE, /* 10943 */ IC_VEX_L, /* 10944 */ IC_VEX_L, /* 10945 */ IC_VEX_L_XS, /* 10946 */ IC_VEX_L_XS, /* 10947 */ IC_VEX_L_XD, /* 10948 */ IC_VEX_L_XD, /* 10949 */ IC_VEX_L_XD, /* 10950 */ IC_VEX_L_XD, /* 10951 */ IC_VEX_L_W, /* 10952 */ IC_VEX_L_W, /* 10953 */ IC_VEX_L_W_XS, /* 10954 */ IC_VEX_L_W_XS, /* 10955 */ IC_VEX_L_W_XD, /* 10956 */ IC_VEX_L_W_XD, /* 10957 */ IC_VEX_L_W_XD, /* 10958 */ IC_VEX_L_W_XD, /* 10959 */ IC_VEX_L_OPSIZE, /* 10960 */ IC_VEX_L_OPSIZE, /* 10961 */ IC_VEX_L_OPSIZE, /* 10962 */ IC_VEX_L_OPSIZE, /* 10963 */ IC_VEX_L_OPSIZE, /* 10964 */ IC_VEX_L_OPSIZE, /* 10965 */ IC_VEX_L_OPSIZE, /* 10966 */ IC_VEX_L_OPSIZE, /* 10967 */ IC_VEX_L_W_OPSIZE, /* 10968 */ IC_VEX_L_W_OPSIZE, /* 10969 */ IC_VEX_L_W_OPSIZE, /* 10970 */ IC_VEX_L_W_OPSIZE, /* 10971 */ IC_VEX_L_W_OPSIZE, /* 10972 */ IC_VEX_L_W_OPSIZE, /* 10973 */ IC_VEX_L_W_OPSIZE, /* 10974 */ IC_VEX_L_W_OPSIZE, /* 10975 */ IC_VEX_L, /* 10976 */ IC_VEX_L, /* 10977 */ IC_VEX_L_XS, /* 10978 */ IC_VEX_L_XS, /* 10979 */ IC_VEX_L_XD, /* 10980 */ IC_VEX_L_XD, /* 10981 */ IC_VEX_L_XD, /* 10982 */ IC_VEX_L_XD, /* 10983 */ IC_VEX_L_W, /* 10984 */ IC_VEX_L_W, /* 10985 */ IC_VEX_L_W_XS, /* 10986 */ IC_VEX_L_W_XS, /* 10987 */ IC_VEX_L_W_XD, /* 10988 */ IC_VEX_L_W_XD, /* 10989 */ IC_VEX_L_W_XD, /* 10990 */ IC_VEX_L_W_XD, /* 10991 */ IC_VEX_L_OPSIZE, /* 10992 */ IC_VEX_L_OPSIZE, /* 10993 */ IC_VEX_L_OPSIZE, /* 10994 */ IC_VEX_L_OPSIZE, /* 10995 */ IC_VEX_L_OPSIZE, /* 10996 */ IC_VEX_L_OPSIZE, /* 10997 */ IC_VEX_L_OPSIZE, /* 10998 */ IC_VEX_L_OPSIZE, /* 10999 */ IC_VEX_L_W_OPSIZE, /* 11000 */ IC_VEX_L_W_OPSIZE, /* 11001 */ IC_VEX_L_W_OPSIZE, /* 11002 */ IC_VEX_L_W_OPSIZE, /* 11003 */ IC_VEX_L_W_OPSIZE, /* 11004 */ IC_VEX_L_W_OPSIZE, /* 11005 */ IC_VEX_L_W_OPSIZE, /* 11006 */ IC_VEX_L_W_OPSIZE, /* 11007 */ IC_EVEX_L_K_B, /* 11008 */ IC_EVEX_L_K_B, /* 11009 */ IC_EVEX_L_XS_K_B, /* 11010 */ IC_EVEX_L_XS_K_B, /* 11011 */ IC_EVEX_L_XD_K_B, /* 11012 */ IC_EVEX_L_XD_K_B, /* 11013 */ IC_EVEX_L_XD_K_B, /* 11014 */ IC_EVEX_L_XD_K_B, /* 11015 */ IC_EVEX_L_W_K_B, /* 11016 */ IC_EVEX_L_W_K_B, /* 11017 */ IC_EVEX_L_W_XS_K_B, /* 11018 */ IC_EVEX_L_W_XS_K_B, /* 11019 */ IC_EVEX_L_W_XD_K_B, /* 11020 */ IC_EVEX_L_W_XD_K_B, /* 11021 */ IC_EVEX_L_W_XD_K_B, /* 11022 */ IC_EVEX_L_W_XD_K_B, /* 11023 */ IC_EVEX_L_OPSIZE_K_B, /* 11024 */ IC_EVEX_L_OPSIZE_K_B, /* 11025 */ IC_EVEX_L_OPSIZE_K_B, /* 11026 */ IC_EVEX_L_OPSIZE_K_B, /* 11027 */ IC_EVEX_L_OPSIZE_K_B, /* 11028 */ IC_EVEX_L_OPSIZE_K_B, /* 11029 */ IC_EVEX_L_OPSIZE_K_B, /* 11030 */ IC_EVEX_L_OPSIZE_K_B, /* 11031 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11032 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11033 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11034 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11035 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11036 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11037 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11038 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11039 */ IC_EVEX_L_K_B, /* 11040 */ IC_EVEX_L_K_B, /* 11041 */ IC_EVEX_L_XS_K_B, /* 11042 */ IC_EVEX_L_XS_K_B, /* 11043 */ IC_EVEX_L_XD_K_B, /* 11044 */ IC_EVEX_L_XD_K_B, /* 11045 */ IC_EVEX_L_XD_K_B, /* 11046 */ IC_EVEX_L_XD_K_B, /* 11047 */ IC_EVEX_L_W_K_B, /* 11048 */ IC_EVEX_L_W_K_B, /* 11049 */ IC_EVEX_L_W_XS_K_B, /* 11050 */ IC_EVEX_L_W_XS_K_B, /* 11051 */ IC_EVEX_L_W_XD_K_B, /* 11052 */ IC_EVEX_L_W_XD_K_B, /* 11053 */ IC_EVEX_L_W_XD_K_B, /* 11054 */ IC_EVEX_L_W_XD_K_B, /* 11055 */ IC_EVEX_L_OPSIZE_K_B, /* 11056 */ IC_EVEX_L_OPSIZE_K_B, /* 11057 */ IC_EVEX_L_OPSIZE_K_B, /* 11058 */ IC_EVEX_L_OPSIZE_K_B, /* 11059 */ IC_EVEX_L_OPSIZE_K_B, /* 11060 */ IC_EVEX_L_OPSIZE_K_B, /* 11061 */ IC_EVEX_L_OPSIZE_K_B, /* 11062 */ IC_EVEX_L_OPSIZE_K_B, /* 11063 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11064 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11065 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11066 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11067 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11068 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11069 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11070 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11071 */ IC_EVEX_L_K_B, /* 11072 */ IC_EVEX_L_K_B, /* 11073 */ IC_EVEX_L_XS_K_B, /* 11074 */ IC_EVEX_L_XS_K_B, /* 11075 */ IC_EVEX_L_XD_K_B, /* 11076 */ IC_EVEX_L_XD_K_B, /* 11077 */ IC_EVEX_L_XD_K_B, /* 11078 */ IC_EVEX_L_XD_K_B, /* 11079 */ IC_EVEX_L_W_K_B, /* 11080 */ IC_EVEX_L_W_K_B, /* 11081 */ IC_EVEX_L_W_XS_K_B, /* 11082 */ IC_EVEX_L_W_XS_K_B, /* 11083 */ IC_EVEX_L_W_XD_K_B, /* 11084 */ IC_EVEX_L_W_XD_K_B, /* 11085 */ IC_EVEX_L_W_XD_K_B, /* 11086 */ IC_EVEX_L_W_XD_K_B, /* 11087 */ IC_EVEX_L_OPSIZE_K_B, /* 11088 */ IC_EVEX_L_OPSIZE_K_B, /* 11089 */ IC_EVEX_L_OPSIZE_K_B, /* 11090 */ IC_EVEX_L_OPSIZE_K_B, /* 11091 */ IC_EVEX_L_OPSIZE_K_B, /* 11092 */ IC_EVEX_L_OPSIZE_K_B, /* 11093 */ IC_EVEX_L_OPSIZE_K_B, /* 11094 */ IC_EVEX_L_OPSIZE_K_B, /* 11095 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11096 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11097 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11098 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11099 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11100 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11101 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11102 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11103 */ IC_EVEX_L_K_B, /* 11104 */ IC_EVEX_L_K_B, /* 11105 */ IC_EVEX_L_XS_K_B, /* 11106 */ IC_EVEX_L_XS_K_B, /* 11107 */ IC_EVEX_L_XD_K_B, /* 11108 */ IC_EVEX_L_XD_K_B, /* 11109 */ IC_EVEX_L_XD_K_B, /* 11110 */ IC_EVEX_L_XD_K_B, /* 11111 */ IC_EVEX_L_W_K_B, /* 11112 */ IC_EVEX_L_W_K_B, /* 11113 */ IC_EVEX_L_W_XS_K_B, /* 11114 */ IC_EVEX_L_W_XS_K_B, /* 11115 */ IC_EVEX_L_W_XD_K_B, /* 11116 */ IC_EVEX_L_W_XD_K_B, /* 11117 */ IC_EVEX_L_W_XD_K_B, /* 11118 */ IC_EVEX_L_W_XD_K_B, /* 11119 */ IC_EVEX_L_OPSIZE_K_B, /* 11120 */ IC_EVEX_L_OPSIZE_K_B, /* 11121 */ IC_EVEX_L_OPSIZE_K_B, /* 11122 */ IC_EVEX_L_OPSIZE_K_B, /* 11123 */ IC_EVEX_L_OPSIZE_K_B, /* 11124 */ IC_EVEX_L_OPSIZE_K_B, /* 11125 */ IC_EVEX_L_OPSIZE_K_B, /* 11126 */ IC_EVEX_L_OPSIZE_K_B, /* 11127 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11128 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11129 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11130 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11131 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11132 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11133 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11134 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11135 */ IC_EVEX_L_K_B, /* 11136 */ IC_EVEX_L_K_B, /* 11137 */ IC_EVEX_L_XS_K_B, /* 11138 */ IC_EVEX_L_XS_K_B, /* 11139 */ IC_EVEX_L_XD_K_B, /* 11140 */ IC_EVEX_L_XD_K_B, /* 11141 */ IC_EVEX_L_XD_K_B, /* 11142 */ IC_EVEX_L_XD_K_B, /* 11143 */ IC_EVEX_L_W_K_B, /* 11144 */ IC_EVEX_L_W_K_B, /* 11145 */ IC_EVEX_L_W_XS_K_B, /* 11146 */ IC_EVEX_L_W_XS_K_B, /* 11147 */ IC_EVEX_L_W_XD_K_B, /* 11148 */ IC_EVEX_L_W_XD_K_B, /* 11149 */ IC_EVEX_L_W_XD_K_B, /* 11150 */ IC_EVEX_L_W_XD_K_B, /* 11151 */ IC_EVEX_L_OPSIZE_K_B, /* 11152 */ IC_EVEX_L_OPSIZE_K_B, /* 11153 */ IC_EVEX_L_OPSIZE_K_B, /* 11154 */ IC_EVEX_L_OPSIZE_K_B, /* 11155 */ IC_EVEX_L_OPSIZE_K_B, /* 11156 */ IC_EVEX_L_OPSIZE_K_B, /* 11157 */ IC_EVEX_L_OPSIZE_K_B, /* 11158 */ IC_EVEX_L_OPSIZE_K_B, /* 11159 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11160 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11161 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11162 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11163 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11164 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11165 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11166 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11167 */ IC_EVEX_L_K_B, /* 11168 */ IC_EVEX_L_K_B, /* 11169 */ IC_EVEX_L_XS_K_B, /* 11170 */ IC_EVEX_L_XS_K_B, /* 11171 */ IC_EVEX_L_XD_K_B, /* 11172 */ IC_EVEX_L_XD_K_B, /* 11173 */ IC_EVEX_L_XD_K_B, /* 11174 */ IC_EVEX_L_XD_K_B, /* 11175 */ IC_EVEX_L_W_K_B, /* 11176 */ IC_EVEX_L_W_K_B, /* 11177 */ IC_EVEX_L_W_XS_K_B, /* 11178 */ IC_EVEX_L_W_XS_K_B, /* 11179 */ IC_EVEX_L_W_XD_K_B, /* 11180 */ IC_EVEX_L_W_XD_K_B, /* 11181 */ IC_EVEX_L_W_XD_K_B, /* 11182 */ IC_EVEX_L_W_XD_K_B, /* 11183 */ IC_EVEX_L_OPSIZE_K_B, /* 11184 */ IC_EVEX_L_OPSIZE_K_B, /* 11185 */ IC_EVEX_L_OPSIZE_K_B, /* 11186 */ IC_EVEX_L_OPSIZE_K_B, /* 11187 */ IC_EVEX_L_OPSIZE_K_B, /* 11188 */ IC_EVEX_L_OPSIZE_K_B, /* 11189 */ IC_EVEX_L_OPSIZE_K_B, /* 11190 */ IC_EVEX_L_OPSIZE_K_B, /* 11191 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11192 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11193 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11194 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11195 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11196 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11197 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11198 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11199 */ IC_EVEX_L_K_B, /* 11200 */ IC_EVEX_L_K_B, /* 11201 */ IC_EVEX_L_XS_K_B, /* 11202 */ IC_EVEX_L_XS_K_B, /* 11203 */ IC_EVEX_L_XD_K_B, /* 11204 */ IC_EVEX_L_XD_K_B, /* 11205 */ IC_EVEX_L_XD_K_B, /* 11206 */ IC_EVEX_L_XD_K_B, /* 11207 */ IC_EVEX_L_W_K_B, /* 11208 */ IC_EVEX_L_W_K_B, /* 11209 */ IC_EVEX_L_W_XS_K_B, /* 11210 */ IC_EVEX_L_W_XS_K_B, /* 11211 */ IC_EVEX_L_W_XD_K_B, /* 11212 */ IC_EVEX_L_W_XD_K_B, /* 11213 */ IC_EVEX_L_W_XD_K_B, /* 11214 */ IC_EVEX_L_W_XD_K_B, /* 11215 */ IC_EVEX_L_OPSIZE_K_B, /* 11216 */ IC_EVEX_L_OPSIZE_K_B, /* 11217 */ IC_EVEX_L_OPSIZE_K_B, /* 11218 */ IC_EVEX_L_OPSIZE_K_B, /* 11219 */ IC_EVEX_L_OPSIZE_K_B, /* 11220 */ IC_EVEX_L_OPSIZE_K_B, /* 11221 */ IC_EVEX_L_OPSIZE_K_B, /* 11222 */ IC_EVEX_L_OPSIZE_K_B, /* 11223 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11224 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11225 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11226 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11227 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11228 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11229 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11230 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11231 */ IC_EVEX_L_K_B, /* 11232 */ IC_EVEX_L_K_B, /* 11233 */ IC_EVEX_L_XS_K_B, /* 11234 */ IC_EVEX_L_XS_K_B, /* 11235 */ IC_EVEX_L_XD_K_B, /* 11236 */ IC_EVEX_L_XD_K_B, /* 11237 */ IC_EVEX_L_XD_K_B, /* 11238 */ IC_EVEX_L_XD_K_B, /* 11239 */ IC_EVEX_L_W_K_B, /* 11240 */ IC_EVEX_L_W_K_B, /* 11241 */ IC_EVEX_L_W_XS_K_B, /* 11242 */ IC_EVEX_L_W_XS_K_B, /* 11243 */ IC_EVEX_L_W_XD_K_B, /* 11244 */ IC_EVEX_L_W_XD_K_B, /* 11245 */ IC_EVEX_L_W_XD_K_B, /* 11246 */ IC_EVEX_L_W_XD_K_B, /* 11247 */ IC_EVEX_L_OPSIZE_K_B, /* 11248 */ IC_EVEX_L_OPSIZE_K_B, /* 11249 */ IC_EVEX_L_OPSIZE_K_B, /* 11250 */ IC_EVEX_L_OPSIZE_K_B, /* 11251 */ IC_EVEX_L_OPSIZE_K_B, /* 11252 */ IC_EVEX_L_OPSIZE_K_B, /* 11253 */ IC_EVEX_L_OPSIZE_K_B, /* 11254 */ IC_EVEX_L_OPSIZE_K_B, /* 11255 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11256 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11257 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11258 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11259 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11260 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11261 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11262 */ IC_EVEX_L_W_OPSIZE_K_B, /* 11263 */ IC, /* 11264 */ IC_64BIT, /* 11265 */ IC_XS, /* 11266 */ IC_64BIT_XS, /* 11267 */ IC_XD, /* 11268 */ IC_64BIT_XD, /* 11269 */ IC_XS, /* 11270 */ IC_64BIT_XS, /* 11271 */ IC, /* 11272 */ IC_64BIT_REXW, /* 11273 */ IC_XS, /* 11274 */ IC_64BIT_REXW_XS, /* 11275 */ IC_XD, /* 11276 */ IC_64BIT_REXW_XD, /* 11277 */ IC_XS, /* 11278 */ IC_64BIT_REXW_XS, /* 11279 */ IC_OPSIZE, /* 11280 */ IC_64BIT_OPSIZE, /* 11281 */ IC_XS_OPSIZE, /* 11282 */ IC_64BIT_XS_OPSIZE, /* 11283 */ IC_XD_OPSIZE, /* 11284 */ IC_64BIT_XD_OPSIZE, /* 11285 */ IC_XS_OPSIZE, /* 11286 */ IC_64BIT_XD_OPSIZE, /* 11287 */ IC_OPSIZE, /* 11288 */ IC_64BIT_REXW_OPSIZE, /* 11289 */ IC_XS_OPSIZE, /* 11290 */ IC_64BIT_REXW_XS, /* 11291 */ IC_XD_OPSIZE, /* 11292 */ IC_64BIT_REXW_XD, /* 11293 */ IC_XS_OPSIZE, /* 11294 */ IC_64BIT_REXW_XS, /* 11295 */ IC_ADSIZE, /* 11296 */ IC_64BIT_ADSIZE, /* 11297 */ IC_XS_ADSIZE, /* 11298 */ IC_64BIT_XS_ADSIZE, /* 11299 */ IC_XD_ADSIZE, /* 11300 */ IC_64BIT_XD_ADSIZE, /* 11301 */ IC_XS_ADSIZE, /* 11302 */ IC_64BIT_XD_ADSIZE, /* 11303 */ IC_ADSIZE, /* 11304 */ IC_64BIT_REXW_ADSIZE, /* 11305 */ IC_XS_ADSIZE, /* 11306 */ IC_64BIT_REXW_XS, /* 11307 */ IC_XD_ADSIZE, /* 11308 */ IC_64BIT_REXW_XD, /* 11309 */ IC_XS_ADSIZE, /* 11310 */ IC_64BIT_REXW_XS, /* 11311 */ IC_OPSIZE_ADSIZE, /* 11312 */ IC_64BIT_OPSIZE_ADSIZE, /* 11313 */ IC_XS_OPSIZE, /* 11314 */ IC_64BIT_XS_OPSIZE, /* 11315 */ IC_XD_OPSIZE, /* 11316 */ IC_64BIT_XD_OPSIZE, /* 11317 */ IC_XS_OPSIZE, /* 11318 */ IC_64BIT_XD_OPSIZE, /* 11319 */ IC_OPSIZE_ADSIZE, /* 11320 */ IC_64BIT_REXW_OPSIZE, /* 11321 */ IC_XS_OPSIZE, /* 11322 */ IC_64BIT_REXW_XS, /* 11323 */ IC_XD_OPSIZE, /* 11324 */ IC_64BIT_REXW_XD, /* 11325 */ IC_XS_OPSIZE, /* 11326 */ IC_64BIT_REXW_XS, /* 11327 */ IC_VEX, /* 11328 */ IC_VEX, /* 11329 */ IC_VEX_XS, /* 11330 */ IC_VEX_XS, /* 11331 */ IC_VEX_XD, /* 11332 */ IC_VEX_XD, /* 11333 */ IC_VEX_XD, /* 11334 */ IC_VEX_XD, /* 11335 */ IC_VEX_W, /* 11336 */ IC_VEX_W, /* 11337 */ IC_VEX_W_XS, /* 11338 */ IC_VEX_W_XS, /* 11339 */ IC_VEX_W_XD, /* 11340 */ IC_VEX_W_XD, /* 11341 */ IC_VEX_W_XD, /* 11342 */ IC_VEX_W_XD, /* 11343 */ IC_VEX_OPSIZE, /* 11344 */ IC_VEX_OPSIZE, /* 11345 */ IC_VEX_OPSIZE, /* 11346 */ IC_VEX_OPSIZE, /* 11347 */ IC_VEX_OPSIZE, /* 11348 */ IC_VEX_OPSIZE, /* 11349 */ IC_VEX_OPSIZE, /* 11350 */ IC_VEX_OPSIZE, /* 11351 */ IC_VEX_W_OPSIZE, /* 11352 */ IC_VEX_W_OPSIZE, /* 11353 */ IC_VEX_W_OPSIZE, /* 11354 */ IC_VEX_W_OPSIZE, /* 11355 */ IC_VEX_W_OPSIZE, /* 11356 */ IC_VEX_W_OPSIZE, /* 11357 */ IC_VEX_W_OPSIZE, /* 11358 */ IC_VEX_W_OPSIZE, /* 11359 */ IC_VEX, /* 11360 */ IC_VEX, /* 11361 */ IC_VEX_XS, /* 11362 */ IC_VEX_XS, /* 11363 */ IC_VEX_XD, /* 11364 */ IC_VEX_XD, /* 11365 */ IC_VEX_XD, /* 11366 */ IC_VEX_XD, /* 11367 */ IC_VEX_W, /* 11368 */ IC_VEX_W, /* 11369 */ IC_VEX_W_XS, /* 11370 */ IC_VEX_W_XS, /* 11371 */ IC_VEX_W_XD, /* 11372 */ IC_VEX_W_XD, /* 11373 */ IC_VEX_W_XD, /* 11374 */ IC_VEX_W_XD, /* 11375 */ IC_VEX_OPSIZE, /* 11376 */ IC_VEX_OPSIZE, /* 11377 */ IC_VEX_OPSIZE, /* 11378 */ IC_VEX_OPSIZE, /* 11379 */ IC_VEX_OPSIZE, /* 11380 */ IC_VEX_OPSIZE, /* 11381 */ IC_VEX_OPSIZE, /* 11382 */ IC_VEX_OPSIZE, /* 11383 */ IC_VEX_W_OPSIZE, /* 11384 */ IC_VEX_W_OPSIZE, /* 11385 */ IC_VEX_W_OPSIZE, /* 11386 */ IC_VEX_W_OPSIZE, /* 11387 */ IC_VEX_W_OPSIZE, /* 11388 */ IC_VEX_W_OPSIZE, /* 11389 */ IC_VEX_W_OPSIZE, /* 11390 */ IC_VEX_W_OPSIZE, /* 11391 */ IC_VEX_L, /* 11392 */ IC_VEX_L, /* 11393 */ IC_VEX_L_XS, /* 11394 */ IC_VEX_L_XS, /* 11395 */ IC_VEX_L_XD, /* 11396 */ IC_VEX_L_XD, /* 11397 */ IC_VEX_L_XD, /* 11398 */ IC_VEX_L_XD, /* 11399 */ IC_VEX_L_W, /* 11400 */ IC_VEX_L_W, /* 11401 */ IC_VEX_L_W_XS, /* 11402 */ IC_VEX_L_W_XS, /* 11403 */ IC_VEX_L_W_XD, /* 11404 */ IC_VEX_L_W_XD, /* 11405 */ IC_VEX_L_W_XD, /* 11406 */ IC_VEX_L_W_XD, /* 11407 */ IC_VEX_L_OPSIZE, /* 11408 */ IC_VEX_L_OPSIZE, /* 11409 */ IC_VEX_L_OPSIZE, /* 11410 */ IC_VEX_L_OPSIZE, /* 11411 */ IC_VEX_L_OPSIZE, /* 11412 */ IC_VEX_L_OPSIZE, /* 11413 */ IC_VEX_L_OPSIZE, /* 11414 */ IC_VEX_L_OPSIZE, /* 11415 */ IC_VEX_L_W_OPSIZE, /* 11416 */ IC_VEX_L_W_OPSIZE, /* 11417 */ IC_VEX_L_W_OPSIZE, /* 11418 */ IC_VEX_L_W_OPSIZE, /* 11419 */ IC_VEX_L_W_OPSIZE, /* 11420 */ IC_VEX_L_W_OPSIZE, /* 11421 */ IC_VEX_L_W_OPSIZE, /* 11422 */ IC_VEX_L_W_OPSIZE, /* 11423 */ IC_VEX_L, /* 11424 */ IC_VEX_L, /* 11425 */ IC_VEX_L_XS, /* 11426 */ IC_VEX_L_XS, /* 11427 */ IC_VEX_L_XD, /* 11428 */ IC_VEX_L_XD, /* 11429 */ IC_VEX_L_XD, /* 11430 */ IC_VEX_L_XD, /* 11431 */ IC_VEX_L_W, /* 11432 */ IC_VEX_L_W, /* 11433 */ IC_VEX_L_W_XS, /* 11434 */ IC_VEX_L_W_XS, /* 11435 */ IC_VEX_L_W_XD, /* 11436 */ IC_VEX_L_W_XD, /* 11437 */ IC_VEX_L_W_XD, /* 11438 */ IC_VEX_L_W_XD, /* 11439 */ IC_VEX_L_OPSIZE, /* 11440 */ IC_VEX_L_OPSIZE, /* 11441 */ IC_VEX_L_OPSIZE, /* 11442 */ IC_VEX_L_OPSIZE, /* 11443 */ IC_VEX_L_OPSIZE, /* 11444 */ IC_VEX_L_OPSIZE, /* 11445 */ IC_VEX_L_OPSIZE, /* 11446 */ IC_VEX_L_OPSIZE, /* 11447 */ IC_VEX_L_W_OPSIZE, /* 11448 */ IC_VEX_L_W_OPSIZE, /* 11449 */ IC_VEX_L_W_OPSIZE, /* 11450 */ IC_VEX_L_W_OPSIZE, /* 11451 */ IC_VEX_L_W_OPSIZE, /* 11452 */ IC_VEX_L_W_OPSIZE, /* 11453 */ IC_VEX_L_W_OPSIZE, /* 11454 */ IC_VEX_L_W_OPSIZE, /* 11455 */ IC_VEX_L, /* 11456 */ IC_VEX_L, /* 11457 */ IC_VEX_L_XS, /* 11458 */ IC_VEX_L_XS, /* 11459 */ IC_VEX_L_XD, /* 11460 */ IC_VEX_L_XD, /* 11461 */ IC_VEX_L_XD, /* 11462 */ IC_VEX_L_XD, /* 11463 */ IC_VEX_L_W, /* 11464 */ IC_VEX_L_W, /* 11465 */ IC_VEX_L_W_XS, /* 11466 */ IC_VEX_L_W_XS, /* 11467 */ IC_VEX_L_W_XD, /* 11468 */ IC_VEX_L_W_XD, /* 11469 */ IC_VEX_L_W_XD, /* 11470 */ IC_VEX_L_W_XD, /* 11471 */ IC_VEX_L_OPSIZE, /* 11472 */ IC_VEX_L_OPSIZE, /* 11473 */ IC_VEX_L_OPSIZE, /* 11474 */ IC_VEX_L_OPSIZE, /* 11475 */ IC_VEX_L_OPSIZE, /* 11476 */ IC_VEX_L_OPSIZE, /* 11477 */ IC_VEX_L_OPSIZE, /* 11478 */ IC_VEX_L_OPSIZE, /* 11479 */ IC_VEX_L_W_OPSIZE, /* 11480 */ IC_VEX_L_W_OPSIZE, /* 11481 */ IC_VEX_L_W_OPSIZE, /* 11482 */ IC_VEX_L_W_OPSIZE, /* 11483 */ IC_VEX_L_W_OPSIZE, /* 11484 */ IC_VEX_L_W_OPSIZE, /* 11485 */ IC_VEX_L_W_OPSIZE, /* 11486 */ IC_VEX_L_W_OPSIZE, /* 11487 */ IC_VEX_L, /* 11488 */ IC_VEX_L, /* 11489 */ IC_VEX_L_XS, /* 11490 */ IC_VEX_L_XS, /* 11491 */ IC_VEX_L_XD, /* 11492 */ IC_VEX_L_XD, /* 11493 */ IC_VEX_L_XD, /* 11494 */ IC_VEX_L_XD, /* 11495 */ IC_VEX_L_W, /* 11496 */ IC_VEX_L_W, /* 11497 */ IC_VEX_L_W_XS, /* 11498 */ IC_VEX_L_W_XS, /* 11499 */ IC_VEX_L_W_XD, /* 11500 */ IC_VEX_L_W_XD, /* 11501 */ IC_VEX_L_W_XD, /* 11502 */ IC_VEX_L_W_XD, /* 11503 */ IC_VEX_L_OPSIZE, /* 11504 */ IC_VEX_L_OPSIZE, /* 11505 */ IC_VEX_L_OPSIZE, /* 11506 */ IC_VEX_L_OPSIZE, /* 11507 */ IC_VEX_L_OPSIZE, /* 11508 */ IC_VEX_L_OPSIZE, /* 11509 */ IC_VEX_L_OPSIZE, /* 11510 */ IC_VEX_L_OPSIZE, /* 11511 */ IC_VEX_L_W_OPSIZE, /* 11512 */ IC_VEX_L_W_OPSIZE, /* 11513 */ IC_VEX_L_W_OPSIZE, /* 11514 */ IC_VEX_L_W_OPSIZE, /* 11515 */ IC_VEX_L_W_OPSIZE, /* 11516 */ IC_VEX_L_W_OPSIZE, /* 11517 */ IC_VEX_L_W_OPSIZE, /* 11518 */ IC_VEX_L_W_OPSIZE, /* 11519 */ IC_EVEX_L2_K_B, /* 11520 */ IC_EVEX_L2_K_B, /* 11521 */ IC_EVEX_L2_XS_K_B, /* 11522 */ IC_EVEX_L2_XS_K_B, /* 11523 */ IC_EVEX_L2_XD_K_B, /* 11524 */ IC_EVEX_L2_XD_K_B, /* 11525 */ IC_EVEX_L2_XD_K_B, /* 11526 */ IC_EVEX_L2_XD_K_B, /* 11527 */ IC_EVEX_L2_W_K_B, /* 11528 */ IC_EVEX_L2_W_K_B, /* 11529 */ IC_EVEX_L2_W_XS_K_B, /* 11530 */ IC_EVEX_L2_W_XS_K_B, /* 11531 */ IC_EVEX_L2_W_XD_K_B, /* 11532 */ IC_EVEX_L2_W_XD_K_B, /* 11533 */ IC_EVEX_L2_W_XD_K_B, /* 11534 */ IC_EVEX_L2_W_XD_K_B, /* 11535 */ IC_EVEX_L2_OPSIZE_K_B, /* 11536 */ IC_EVEX_L2_OPSIZE_K_B, /* 11537 */ IC_EVEX_L2_OPSIZE_K_B, /* 11538 */ IC_EVEX_L2_OPSIZE_K_B, /* 11539 */ IC_EVEX_L2_OPSIZE_K_B, /* 11540 */ IC_EVEX_L2_OPSIZE_K_B, /* 11541 */ IC_EVEX_L2_OPSIZE_K_B, /* 11542 */ IC_EVEX_L2_OPSIZE_K_B, /* 11543 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11544 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11545 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11546 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11547 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11548 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11549 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11550 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11551 */ IC_EVEX_L2_K_B, /* 11552 */ IC_EVEX_L2_K_B, /* 11553 */ IC_EVEX_L2_XS_K_B, /* 11554 */ IC_EVEX_L2_XS_K_B, /* 11555 */ IC_EVEX_L2_XD_K_B, /* 11556 */ IC_EVEX_L2_XD_K_B, /* 11557 */ IC_EVEX_L2_XD_K_B, /* 11558 */ IC_EVEX_L2_XD_K_B, /* 11559 */ IC_EVEX_L2_W_K_B, /* 11560 */ IC_EVEX_L2_W_K_B, /* 11561 */ IC_EVEX_L2_W_XS_K_B, /* 11562 */ IC_EVEX_L2_W_XS_K_B, /* 11563 */ IC_EVEX_L2_W_XD_K_B, /* 11564 */ IC_EVEX_L2_W_XD_K_B, /* 11565 */ IC_EVEX_L2_W_XD_K_B, /* 11566 */ IC_EVEX_L2_W_XD_K_B, /* 11567 */ IC_EVEX_L2_OPSIZE_K_B, /* 11568 */ IC_EVEX_L2_OPSIZE_K_B, /* 11569 */ IC_EVEX_L2_OPSIZE_K_B, /* 11570 */ IC_EVEX_L2_OPSIZE_K_B, /* 11571 */ IC_EVEX_L2_OPSIZE_K_B, /* 11572 */ IC_EVEX_L2_OPSIZE_K_B, /* 11573 */ IC_EVEX_L2_OPSIZE_K_B, /* 11574 */ IC_EVEX_L2_OPSIZE_K_B, /* 11575 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11576 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11577 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11578 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11579 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11580 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11581 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11582 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11583 */ IC_EVEX_L2_K_B, /* 11584 */ IC_EVEX_L2_K_B, /* 11585 */ IC_EVEX_L2_XS_K_B, /* 11586 */ IC_EVEX_L2_XS_K_B, /* 11587 */ IC_EVEX_L2_XD_K_B, /* 11588 */ IC_EVEX_L2_XD_K_B, /* 11589 */ IC_EVEX_L2_XD_K_B, /* 11590 */ IC_EVEX_L2_XD_K_B, /* 11591 */ IC_EVEX_L2_W_K_B, /* 11592 */ IC_EVEX_L2_W_K_B, /* 11593 */ IC_EVEX_L2_W_XS_K_B, /* 11594 */ IC_EVEX_L2_W_XS_K_B, /* 11595 */ IC_EVEX_L2_W_XD_K_B, /* 11596 */ IC_EVEX_L2_W_XD_K_B, /* 11597 */ IC_EVEX_L2_W_XD_K_B, /* 11598 */ IC_EVEX_L2_W_XD_K_B, /* 11599 */ IC_EVEX_L2_OPSIZE_K_B, /* 11600 */ IC_EVEX_L2_OPSIZE_K_B, /* 11601 */ IC_EVEX_L2_OPSIZE_K_B, /* 11602 */ IC_EVEX_L2_OPSIZE_K_B, /* 11603 */ IC_EVEX_L2_OPSIZE_K_B, /* 11604 */ IC_EVEX_L2_OPSIZE_K_B, /* 11605 */ IC_EVEX_L2_OPSIZE_K_B, /* 11606 */ IC_EVEX_L2_OPSIZE_K_B, /* 11607 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11608 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11609 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11610 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11611 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11612 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11613 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11614 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11615 */ IC_EVEX_L2_K_B, /* 11616 */ IC_EVEX_L2_K_B, /* 11617 */ IC_EVEX_L2_XS_K_B, /* 11618 */ IC_EVEX_L2_XS_K_B, /* 11619 */ IC_EVEX_L2_XD_K_B, /* 11620 */ IC_EVEX_L2_XD_K_B, /* 11621 */ IC_EVEX_L2_XD_K_B, /* 11622 */ IC_EVEX_L2_XD_K_B, /* 11623 */ IC_EVEX_L2_W_K_B, /* 11624 */ IC_EVEX_L2_W_K_B, /* 11625 */ IC_EVEX_L2_W_XS_K_B, /* 11626 */ IC_EVEX_L2_W_XS_K_B, /* 11627 */ IC_EVEX_L2_W_XD_K_B, /* 11628 */ IC_EVEX_L2_W_XD_K_B, /* 11629 */ IC_EVEX_L2_W_XD_K_B, /* 11630 */ IC_EVEX_L2_W_XD_K_B, /* 11631 */ IC_EVEX_L2_OPSIZE_K_B, /* 11632 */ IC_EVEX_L2_OPSIZE_K_B, /* 11633 */ IC_EVEX_L2_OPSIZE_K_B, /* 11634 */ IC_EVEX_L2_OPSIZE_K_B, /* 11635 */ IC_EVEX_L2_OPSIZE_K_B, /* 11636 */ IC_EVEX_L2_OPSIZE_K_B, /* 11637 */ IC_EVEX_L2_OPSIZE_K_B, /* 11638 */ IC_EVEX_L2_OPSIZE_K_B, /* 11639 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11640 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11641 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11642 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11643 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11644 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11645 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11646 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11647 */ IC_EVEX_L2_K_B, /* 11648 */ IC_EVEX_L2_K_B, /* 11649 */ IC_EVEX_L2_XS_K_B, /* 11650 */ IC_EVEX_L2_XS_K_B, /* 11651 */ IC_EVEX_L2_XD_K_B, /* 11652 */ IC_EVEX_L2_XD_K_B, /* 11653 */ IC_EVEX_L2_XD_K_B, /* 11654 */ IC_EVEX_L2_XD_K_B, /* 11655 */ IC_EVEX_L2_W_K_B, /* 11656 */ IC_EVEX_L2_W_K_B, /* 11657 */ IC_EVEX_L2_W_XS_K_B, /* 11658 */ IC_EVEX_L2_W_XS_K_B, /* 11659 */ IC_EVEX_L2_W_XD_K_B, /* 11660 */ IC_EVEX_L2_W_XD_K_B, /* 11661 */ IC_EVEX_L2_W_XD_K_B, /* 11662 */ IC_EVEX_L2_W_XD_K_B, /* 11663 */ IC_EVEX_L2_OPSIZE_K_B, /* 11664 */ IC_EVEX_L2_OPSIZE_K_B, /* 11665 */ IC_EVEX_L2_OPSIZE_K_B, /* 11666 */ IC_EVEX_L2_OPSIZE_K_B, /* 11667 */ IC_EVEX_L2_OPSIZE_K_B, /* 11668 */ IC_EVEX_L2_OPSIZE_K_B, /* 11669 */ IC_EVEX_L2_OPSIZE_K_B, /* 11670 */ IC_EVEX_L2_OPSIZE_K_B, /* 11671 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11672 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11673 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11674 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11675 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11676 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11677 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11678 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11679 */ IC_EVEX_L2_K_B, /* 11680 */ IC_EVEX_L2_K_B, /* 11681 */ IC_EVEX_L2_XS_K_B, /* 11682 */ IC_EVEX_L2_XS_K_B, /* 11683 */ IC_EVEX_L2_XD_K_B, /* 11684 */ IC_EVEX_L2_XD_K_B, /* 11685 */ IC_EVEX_L2_XD_K_B, /* 11686 */ IC_EVEX_L2_XD_K_B, /* 11687 */ IC_EVEX_L2_W_K_B, /* 11688 */ IC_EVEX_L2_W_K_B, /* 11689 */ IC_EVEX_L2_W_XS_K_B, /* 11690 */ IC_EVEX_L2_W_XS_K_B, /* 11691 */ IC_EVEX_L2_W_XD_K_B, /* 11692 */ IC_EVEX_L2_W_XD_K_B, /* 11693 */ IC_EVEX_L2_W_XD_K_B, /* 11694 */ IC_EVEX_L2_W_XD_K_B, /* 11695 */ IC_EVEX_L2_OPSIZE_K_B, /* 11696 */ IC_EVEX_L2_OPSIZE_K_B, /* 11697 */ IC_EVEX_L2_OPSIZE_K_B, /* 11698 */ IC_EVEX_L2_OPSIZE_K_B, /* 11699 */ IC_EVEX_L2_OPSIZE_K_B, /* 11700 */ IC_EVEX_L2_OPSIZE_K_B, /* 11701 */ IC_EVEX_L2_OPSIZE_K_B, /* 11702 */ IC_EVEX_L2_OPSIZE_K_B, /* 11703 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11704 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11705 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11706 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11707 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11708 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11709 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11710 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11711 */ IC_EVEX_L2_K_B, /* 11712 */ IC_EVEX_L2_K_B, /* 11713 */ IC_EVEX_L2_XS_K_B, /* 11714 */ IC_EVEX_L2_XS_K_B, /* 11715 */ IC_EVEX_L2_XD_K_B, /* 11716 */ IC_EVEX_L2_XD_K_B, /* 11717 */ IC_EVEX_L2_XD_K_B, /* 11718 */ IC_EVEX_L2_XD_K_B, /* 11719 */ IC_EVEX_L2_W_K_B, /* 11720 */ IC_EVEX_L2_W_K_B, /* 11721 */ IC_EVEX_L2_W_XS_K_B, /* 11722 */ IC_EVEX_L2_W_XS_K_B, /* 11723 */ IC_EVEX_L2_W_XD_K_B, /* 11724 */ IC_EVEX_L2_W_XD_K_B, /* 11725 */ IC_EVEX_L2_W_XD_K_B, /* 11726 */ IC_EVEX_L2_W_XD_K_B, /* 11727 */ IC_EVEX_L2_OPSIZE_K_B, /* 11728 */ IC_EVEX_L2_OPSIZE_K_B, /* 11729 */ IC_EVEX_L2_OPSIZE_K_B, /* 11730 */ IC_EVEX_L2_OPSIZE_K_B, /* 11731 */ IC_EVEX_L2_OPSIZE_K_B, /* 11732 */ IC_EVEX_L2_OPSIZE_K_B, /* 11733 */ IC_EVEX_L2_OPSIZE_K_B, /* 11734 */ IC_EVEX_L2_OPSIZE_K_B, /* 11735 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11736 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11737 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11738 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11739 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11740 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11741 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11742 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11743 */ IC_EVEX_L2_K_B, /* 11744 */ IC_EVEX_L2_K_B, /* 11745 */ IC_EVEX_L2_XS_K_B, /* 11746 */ IC_EVEX_L2_XS_K_B, /* 11747 */ IC_EVEX_L2_XD_K_B, /* 11748 */ IC_EVEX_L2_XD_K_B, /* 11749 */ IC_EVEX_L2_XD_K_B, /* 11750 */ IC_EVEX_L2_XD_K_B, /* 11751 */ IC_EVEX_L2_W_K_B, /* 11752 */ IC_EVEX_L2_W_K_B, /* 11753 */ IC_EVEX_L2_W_XS_K_B, /* 11754 */ IC_EVEX_L2_W_XS_K_B, /* 11755 */ IC_EVEX_L2_W_XD_K_B, /* 11756 */ IC_EVEX_L2_W_XD_K_B, /* 11757 */ IC_EVEX_L2_W_XD_K_B, /* 11758 */ IC_EVEX_L2_W_XD_K_B, /* 11759 */ IC_EVEX_L2_OPSIZE_K_B, /* 11760 */ IC_EVEX_L2_OPSIZE_K_B, /* 11761 */ IC_EVEX_L2_OPSIZE_K_B, /* 11762 */ IC_EVEX_L2_OPSIZE_K_B, /* 11763 */ IC_EVEX_L2_OPSIZE_K_B, /* 11764 */ IC_EVEX_L2_OPSIZE_K_B, /* 11765 */ IC_EVEX_L2_OPSIZE_K_B, /* 11766 */ IC_EVEX_L2_OPSIZE_K_B, /* 11767 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11768 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11769 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11770 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11771 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11772 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11773 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11774 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 11775 */ IC, /* 11776 */ IC_64BIT, /* 11777 */ IC_XS, /* 11778 */ IC_64BIT_XS, /* 11779 */ IC_XD, /* 11780 */ IC_64BIT_XD, /* 11781 */ IC_XS, /* 11782 */ IC_64BIT_XS, /* 11783 */ IC, /* 11784 */ IC_64BIT_REXW, /* 11785 */ IC_XS, /* 11786 */ IC_64BIT_REXW_XS, /* 11787 */ IC_XD, /* 11788 */ IC_64BIT_REXW_XD, /* 11789 */ IC_XS, /* 11790 */ IC_64BIT_REXW_XS, /* 11791 */ IC_OPSIZE, /* 11792 */ IC_64BIT_OPSIZE, /* 11793 */ IC_XS_OPSIZE, /* 11794 */ IC_64BIT_XS_OPSIZE, /* 11795 */ IC_XD_OPSIZE, /* 11796 */ IC_64BIT_XD_OPSIZE, /* 11797 */ IC_XS_OPSIZE, /* 11798 */ IC_64BIT_XD_OPSIZE, /* 11799 */ IC_OPSIZE, /* 11800 */ IC_64BIT_REXW_OPSIZE, /* 11801 */ IC_XS_OPSIZE, /* 11802 */ IC_64BIT_REXW_XS, /* 11803 */ IC_XD_OPSIZE, /* 11804 */ IC_64BIT_REXW_XD, /* 11805 */ IC_XS_OPSIZE, /* 11806 */ IC_64BIT_REXW_XS, /* 11807 */ IC_ADSIZE, /* 11808 */ IC_64BIT_ADSIZE, /* 11809 */ IC_XS_ADSIZE, /* 11810 */ IC_64BIT_XS_ADSIZE, /* 11811 */ IC_XD_ADSIZE, /* 11812 */ IC_64BIT_XD_ADSIZE, /* 11813 */ IC_XS_ADSIZE, /* 11814 */ IC_64BIT_XD_ADSIZE, /* 11815 */ IC_ADSIZE, /* 11816 */ IC_64BIT_REXW_ADSIZE, /* 11817 */ IC_XS_ADSIZE, /* 11818 */ IC_64BIT_REXW_XS, /* 11819 */ IC_XD_ADSIZE, /* 11820 */ IC_64BIT_REXW_XD, /* 11821 */ IC_XS_ADSIZE, /* 11822 */ IC_64BIT_REXW_XS, /* 11823 */ IC_OPSIZE_ADSIZE, /* 11824 */ IC_64BIT_OPSIZE_ADSIZE, /* 11825 */ IC_XS_OPSIZE, /* 11826 */ IC_64BIT_XS_OPSIZE, /* 11827 */ IC_XD_OPSIZE, /* 11828 */ IC_64BIT_XD_OPSIZE, /* 11829 */ IC_XS_OPSIZE, /* 11830 */ IC_64BIT_XD_OPSIZE, /* 11831 */ IC_OPSIZE_ADSIZE, /* 11832 */ IC_64BIT_REXW_OPSIZE, /* 11833 */ IC_XS_OPSIZE, /* 11834 */ IC_64BIT_REXW_XS, /* 11835 */ IC_XD_OPSIZE, /* 11836 */ IC_64BIT_REXW_XD, /* 11837 */ IC_XS_OPSIZE, /* 11838 */ IC_64BIT_REXW_XS, /* 11839 */ IC_VEX, /* 11840 */ IC_VEX, /* 11841 */ IC_VEX_XS, /* 11842 */ IC_VEX_XS, /* 11843 */ IC_VEX_XD, /* 11844 */ IC_VEX_XD, /* 11845 */ IC_VEX_XD, /* 11846 */ IC_VEX_XD, /* 11847 */ IC_VEX_W, /* 11848 */ IC_VEX_W, /* 11849 */ IC_VEX_W_XS, /* 11850 */ IC_VEX_W_XS, /* 11851 */ IC_VEX_W_XD, /* 11852 */ IC_VEX_W_XD, /* 11853 */ IC_VEX_W_XD, /* 11854 */ IC_VEX_W_XD, /* 11855 */ IC_VEX_OPSIZE, /* 11856 */ IC_VEX_OPSIZE, /* 11857 */ IC_VEX_OPSIZE, /* 11858 */ IC_VEX_OPSIZE, /* 11859 */ IC_VEX_OPSIZE, /* 11860 */ IC_VEX_OPSIZE, /* 11861 */ IC_VEX_OPSIZE, /* 11862 */ IC_VEX_OPSIZE, /* 11863 */ IC_VEX_W_OPSIZE, /* 11864 */ IC_VEX_W_OPSIZE, /* 11865 */ IC_VEX_W_OPSIZE, /* 11866 */ IC_VEX_W_OPSIZE, /* 11867 */ IC_VEX_W_OPSIZE, /* 11868 */ IC_VEX_W_OPSIZE, /* 11869 */ IC_VEX_W_OPSIZE, /* 11870 */ IC_VEX_W_OPSIZE, /* 11871 */ IC_VEX, /* 11872 */ IC_VEX, /* 11873 */ IC_VEX_XS, /* 11874 */ IC_VEX_XS, /* 11875 */ IC_VEX_XD, /* 11876 */ IC_VEX_XD, /* 11877 */ IC_VEX_XD, /* 11878 */ IC_VEX_XD, /* 11879 */ IC_VEX_W, /* 11880 */ IC_VEX_W, /* 11881 */ IC_VEX_W_XS, /* 11882 */ IC_VEX_W_XS, /* 11883 */ IC_VEX_W_XD, /* 11884 */ IC_VEX_W_XD, /* 11885 */ IC_VEX_W_XD, /* 11886 */ IC_VEX_W_XD, /* 11887 */ IC_VEX_OPSIZE, /* 11888 */ IC_VEX_OPSIZE, /* 11889 */ IC_VEX_OPSIZE, /* 11890 */ IC_VEX_OPSIZE, /* 11891 */ IC_VEX_OPSIZE, /* 11892 */ IC_VEX_OPSIZE, /* 11893 */ IC_VEX_OPSIZE, /* 11894 */ IC_VEX_OPSIZE, /* 11895 */ IC_VEX_W_OPSIZE, /* 11896 */ IC_VEX_W_OPSIZE, /* 11897 */ IC_VEX_W_OPSIZE, /* 11898 */ IC_VEX_W_OPSIZE, /* 11899 */ IC_VEX_W_OPSIZE, /* 11900 */ IC_VEX_W_OPSIZE, /* 11901 */ IC_VEX_W_OPSIZE, /* 11902 */ IC_VEX_W_OPSIZE, /* 11903 */ IC_VEX_L, /* 11904 */ IC_VEX_L, /* 11905 */ IC_VEX_L_XS, /* 11906 */ IC_VEX_L_XS, /* 11907 */ IC_VEX_L_XD, /* 11908 */ IC_VEX_L_XD, /* 11909 */ IC_VEX_L_XD, /* 11910 */ IC_VEX_L_XD, /* 11911 */ IC_VEX_L_W, /* 11912 */ IC_VEX_L_W, /* 11913 */ IC_VEX_L_W_XS, /* 11914 */ IC_VEX_L_W_XS, /* 11915 */ IC_VEX_L_W_XD, /* 11916 */ IC_VEX_L_W_XD, /* 11917 */ IC_VEX_L_W_XD, /* 11918 */ IC_VEX_L_W_XD, /* 11919 */ IC_VEX_L_OPSIZE, /* 11920 */ IC_VEX_L_OPSIZE, /* 11921 */ IC_VEX_L_OPSIZE, /* 11922 */ IC_VEX_L_OPSIZE, /* 11923 */ IC_VEX_L_OPSIZE, /* 11924 */ IC_VEX_L_OPSIZE, /* 11925 */ IC_VEX_L_OPSIZE, /* 11926 */ IC_VEX_L_OPSIZE, /* 11927 */ IC_VEX_L_W_OPSIZE, /* 11928 */ IC_VEX_L_W_OPSIZE, /* 11929 */ IC_VEX_L_W_OPSIZE, /* 11930 */ IC_VEX_L_W_OPSIZE, /* 11931 */ IC_VEX_L_W_OPSIZE, /* 11932 */ IC_VEX_L_W_OPSIZE, /* 11933 */ IC_VEX_L_W_OPSIZE, /* 11934 */ IC_VEX_L_W_OPSIZE, /* 11935 */ IC_VEX_L, /* 11936 */ IC_VEX_L, /* 11937 */ IC_VEX_L_XS, /* 11938 */ IC_VEX_L_XS, /* 11939 */ IC_VEX_L_XD, /* 11940 */ IC_VEX_L_XD, /* 11941 */ IC_VEX_L_XD, /* 11942 */ IC_VEX_L_XD, /* 11943 */ IC_VEX_L_W, /* 11944 */ IC_VEX_L_W, /* 11945 */ IC_VEX_L_W_XS, /* 11946 */ IC_VEX_L_W_XS, /* 11947 */ IC_VEX_L_W_XD, /* 11948 */ IC_VEX_L_W_XD, /* 11949 */ IC_VEX_L_W_XD, /* 11950 */ IC_VEX_L_W_XD, /* 11951 */ IC_VEX_L_OPSIZE, /* 11952 */ IC_VEX_L_OPSIZE, /* 11953 */ IC_VEX_L_OPSIZE, /* 11954 */ IC_VEX_L_OPSIZE, /* 11955 */ IC_VEX_L_OPSIZE, /* 11956 */ IC_VEX_L_OPSIZE, /* 11957 */ IC_VEX_L_OPSIZE, /* 11958 */ IC_VEX_L_OPSIZE, /* 11959 */ IC_VEX_L_W_OPSIZE, /* 11960 */ IC_VEX_L_W_OPSIZE, /* 11961 */ IC_VEX_L_W_OPSIZE, /* 11962 */ IC_VEX_L_W_OPSIZE, /* 11963 */ IC_VEX_L_W_OPSIZE, /* 11964 */ IC_VEX_L_W_OPSIZE, /* 11965 */ IC_VEX_L_W_OPSIZE, /* 11966 */ IC_VEX_L_W_OPSIZE, /* 11967 */ IC_VEX_L, /* 11968 */ IC_VEX_L, /* 11969 */ IC_VEX_L_XS, /* 11970 */ IC_VEX_L_XS, /* 11971 */ IC_VEX_L_XD, /* 11972 */ IC_VEX_L_XD, /* 11973 */ IC_VEX_L_XD, /* 11974 */ IC_VEX_L_XD, /* 11975 */ IC_VEX_L_W, /* 11976 */ IC_VEX_L_W, /* 11977 */ IC_VEX_L_W_XS, /* 11978 */ IC_VEX_L_W_XS, /* 11979 */ IC_VEX_L_W_XD, /* 11980 */ IC_VEX_L_W_XD, /* 11981 */ IC_VEX_L_W_XD, /* 11982 */ IC_VEX_L_W_XD, /* 11983 */ IC_VEX_L_OPSIZE, /* 11984 */ IC_VEX_L_OPSIZE, /* 11985 */ IC_VEX_L_OPSIZE, /* 11986 */ IC_VEX_L_OPSIZE, /* 11987 */ IC_VEX_L_OPSIZE, /* 11988 */ IC_VEX_L_OPSIZE, /* 11989 */ IC_VEX_L_OPSIZE, /* 11990 */ IC_VEX_L_OPSIZE, /* 11991 */ IC_VEX_L_W_OPSIZE, /* 11992 */ IC_VEX_L_W_OPSIZE, /* 11993 */ IC_VEX_L_W_OPSIZE, /* 11994 */ IC_VEX_L_W_OPSIZE, /* 11995 */ IC_VEX_L_W_OPSIZE, /* 11996 */ IC_VEX_L_W_OPSIZE, /* 11997 */ IC_VEX_L_W_OPSIZE, /* 11998 */ IC_VEX_L_W_OPSIZE, /* 11999 */ IC_VEX_L, /* 12000 */ IC_VEX_L, /* 12001 */ IC_VEX_L_XS, /* 12002 */ IC_VEX_L_XS, /* 12003 */ IC_VEX_L_XD, /* 12004 */ IC_VEX_L_XD, /* 12005 */ IC_VEX_L_XD, /* 12006 */ IC_VEX_L_XD, /* 12007 */ IC_VEX_L_W, /* 12008 */ IC_VEX_L_W, /* 12009 */ IC_VEX_L_W_XS, /* 12010 */ IC_VEX_L_W_XS, /* 12011 */ IC_VEX_L_W_XD, /* 12012 */ IC_VEX_L_W_XD, /* 12013 */ IC_VEX_L_W_XD, /* 12014 */ IC_VEX_L_W_XD, /* 12015 */ IC_VEX_L_OPSIZE, /* 12016 */ IC_VEX_L_OPSIZE, /* 12017 */ IC_VEX_L_OPSIZE, /* 12018 */ IC_VEX_L_OPSIZE, /* 12019 */ IC_VEX_L_OPSIZE, /* 12020 */ IC_VEX_L_OPSIZE, /* 12021 */ IC_VEX_L_OPSIZE, /* 12022 */ IC_VEX_L_OPSIZE, /* 12023 */ IC_VEX_L_W_OPSIZE, /* 12024 */ IC_VEX_L_W_OPSIZE, /* 12025 */ IC_VEX_L_W_OPSIZE, /* 12026 */ IC_VEX_L_W_OPSIZE, /* 12027 */ IC_VEX_L_W_OPSIZE, /* 12028 */ IC_VEX_L_W_OPSIZE, /* 12029 */ IC_VEX_L_W_OPSIZE, /* 12030 */ IC_VEX_L_W_OPSIZE, /* 12031 */ IC_EVEX_L2_K_B, /* 12032 */ IC_EVEX_L2_K_B, /* 12033 */ IC_EVEX_L2_XS_K_B, /* 12034 */ IC_EVEX_L2_XS_K_B, /* 12035 */ IC_EVEX_L2_XD_K_B, /* 12036 */ IC_EVEX_L2_XD_K_B, /* 12037 */ IC_EVEX_L2_XD_K_B, /* 12038 */ IC_EVEX_L2_XD_K_B, /* 12039 */ IC_EVEX_L2_W_K_B, /* 12040 */ IC_EVEX_L2_W_K_B, /* 12041 */ IC_EVEX_L2_W_XS_K_B, /* 12042 */ IC_EVEX_L2_W_XS_K_B, /* 12043 */ IC_EVEX_L2_W_XD_K_B, /* 12044 */ IC_EVEX_L2_W_XD_K_B, /* 12045 */ IC_EVEX_L2_W_XD_K_B, /* 12046 */ IC_EVEX_L2_W_XD_K_B, /* 12047 */ IC_EVEX_L2_OPSIZE_K_B, /* 12048 */ IC_EVEX_L2_OPSIZE_K_B, /* 12049 */ IC_EVEX_L2_OPSIZE_K_B, /* 12050 */ IC_EVEX_L2_OPSIZE_K_B, /* 12051 */ IC_EVEX_L2_OPSIZE_K_B, /* 12052 */ IC_EVEX_L2_OPSIZE_K_B, /* 12053 */ IC_EVEX_L2_OPSIZE_K_B, /* 12054 */ IC_EVEX_L2_OPSIZE_K_B, /* 12055 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12056 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12057 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12058 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12059 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12060 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12061 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12062 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12063 */ IC_EVEX_L2_K_B, /* 12064 */ IC_EVEX_L2_K_B, /* 12065 */ IC_EVEX_L2_XS_K_B, /* 12066 */ IC_EVEX_L2_XS_K_B, /* 12067 */ IC_EVEX_L2_XD_K_B, /* 12068 */ IC_EVEX_L2_XD_K_B, /* 12069 */ IC_EVEX_L2_XD_K_B, /* 12070 */ IC_EVEX_L2_XD_K_B, /* 12071 */ IC_EVEX_L2_W_K_B, /* 12072 */ IC_EVEX_L2_W_K_B, /* 12073 */ IC_EVEX_L2_W_XS_K_B, /* 12074 */ IC_EVEX_L2_W_XS_K_B, /* 12075 */ IC_EVEX_L2_W_XD_K_B, /* 12076 */ IC_EVEX_L2_W_XD_K_B, /* 12077 */ IC_EVEX_L2_W_XD_K_B, /* 12078 */ IC_EVEX_L2_W_XD_K_B, /* 12079 */ IC_EVEX_L2_OPSIZE_K_B, /* 12080 */ IC_EVEX_L2_OPSIZE_K_B, /* 12081 */ IC_EVEX_L2_OPSIZE_K_B, /* 12082 */ IC_EVEX_L2_OPSIZE_K_B, /* 12083 */ IC_EVEX_L2_OPSIZE_K_B, /* 12084 */ IC_EVEX_L2_OPSIZE_K_B, /* 12085 */ IC_EVEX_L2_OPSIZE_K_B, /* 12086 */ IC_EVEX_L2_OPSIZE_K_B, /* 12087 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12088 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12089 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12090 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12091 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12092 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12093 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12094 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12095 */ IC_EVEX_L2_K_B, /* 12096 */ IC_EVEX_L2_K_B, /* 12097 */ IC_EVEX_L2_XS_K_B, /* 12098 */ IC_EVEX_L2_XS_K_B, /* 12099 */ IC_EVEX_L2_XD_K_B, /* 12100 */ IC_EVEX_L2_XD_K_B, /* 12101 */ IC_EVEX_L2_XD_K_B, /* 12102 */ IC_EVEX_L2_XD_K_B, /* 12103 */ IC_EVEX_L2_W_K_B, /* 12104 */ IC_EVEX_L2_W_K_B, /* 12105 */ IC_EVEX_L2_W_XS_K_B, /* 12106 */ IC_EVEX_L2_W_XS_K_B, /* 12107 */ IC_EVEX_L2_W_XD_K_B, /* 12108 */ IC_EVEX_L2_W_XD_K_B, /* 12109 */ IC_EVEX_L2_W_XD_K_B, /* 12110 */ IC_EVEX_L2_W_XD_K_B, /* 12111 */ IC_EVEX_L2_OPSIZE_K_B, /* 12112 */ IC_EVEX_L2_OPSIZE_K_B, /* 12113 */ IC_EVEX_L2_OPSIZE_K_B, /* 12114 */ IC_EVEX_L2_OPSIZE_K_B, /* 12115 */ IC_EVEX_L2_OPSIZE_K_B, /* 12116 */ IC_EVEX_L2_OPSIZE_K_B, /* 12117 */ IC_EVEX_L2_OPSIZE_K_B, /* 12118 */ IC_EVEX_L2_OPSIZE_K_B, /* 12119 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12120 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12121 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12122 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12123 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12124 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12125 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12126 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12127 */ IC_EVEX_L2_K_B, /* 12128 */ IC_EVEX_L2_K_B, /* 12129 */ IC_EVEX_L2_XS_K_B, /* 12130 */ IC_EVEX_L2_XS_K_B, /* 12131 */ IC_EVEX_L2_XD_K_B, /* 12132 */ IC_EVEX_L2_XD_K_B, /* 12133 */ IC_EVEX_L2_XD_K_B, /* 12134 */ IC_EVEX_L2_XD_K_B, /* 12135 */ IC_EVEX_L2_W_K_B, /* 12136 */ IC_EVEX_L2_W_K_B, /* 12137 */ IC_EVEX_L2_W_XS_K_B, /* 12138 */ IC_EVEX_L2_W_XS_K_B, /* 12139 */ IC_EVEX_L2_W_XD_K_B, /* 12140 */ IC_EVEX_L2_W_XD_K_B, /* 12141 */ IC_EVEX_L2_W_XD_K_B, /* 12142 */ IC_EVEX_L2_W_XD_K_B, /* 12143 */ IC_EVEX_L2_OPSIZE_K_B, /* 12144 */ IC_EVEX_L2_OPSIZE_K_B, /* 12145 */ IC_EVEX_L2_OPSIZE_K_B, /* 12146 */ IC_EVEX_L2_OPSIZE_K_B, /* 12147 */ IC_EVEX_L2_OPSIZE_K_B, /* 12148 */ IC_EVEX_L2_OPSIZE_K_B, /* 12149 */ IC_EVEX_L2_OPSIZE_K_B, /* 12150 */ IC_EVEX_L2_OPSIZE_K_B, /* 12151 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12152 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12153 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12154 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12155 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12156 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12157 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12158 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12159 */ IC_EVEX_L2_K_B, /* 12160 */ IC_EVEX_L2_K_B, /* 12161 */ IC_EVEX_L2_XS_K_B, /* 12162 */ IC_EVEX_L2_XS_K_B, /* 12163 */ IC_EVEX_L2_XD_K_B, /* 12164 */ IC_EVEX_L2_XD_K_B, /* 12165 */ IC_EVEX_L2_XD_K_B, /* 12166 */ IC_EVEX_L2_XD_K_B, /* 12167 */ IC_EVEX_L2_W_K_B, /* 12168 */ IC_EVEX_L2_W_K_B, /* 12169 */ IC_EVEX_L2_W_XS_K_B, /* 12170 */ IC_EVEX_L2_W_XS_K_B, /* 12171 */ IC_EVEX_L2_W_XD_K_B, /* 12172 */ IC_EVEX_L2_W_XD_K_B, /* 12173 */ IC_EVEX_L2_W_XD_K_B, /* 12174 */ IC_EVEX_L2_W_XD_K_B, /* 12175 */ IC_EVEX_L2_OPSIZE_K_B, /* 12176 */ IC_EVEX_L2_OPSIZE_K_B, /* 12177 */ IC_EVEX_L2_OPSIZE_K_B, /* 12178 */ IC_EVEX_L2_OPSIZE_K_B, /* 12179 */ IC_EVEX_L2_OPSIZE_K_B, /* 12180 */ IC_EVEX_L2_OPSIZE_K_B, /* 12181 */ IC_EVEX_L2_OPSIZE_K_B, /* 12182 */ IC_EVEX_L2_OPSIZE_K_B, /* 12183 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12184 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12185 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12186 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12187 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12188 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12189 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12190 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12191 */ IC_EVEX_L2_K_B, /* 12192 */ IC_EVEX_L2_K_B, /* 12193 */ IC_EVEX_L2_XS_K_B, /* 12194 */ IC_EVEX_L2_XS_K_B, /* 12195 */ IC_EVEX_L2_XD_K_B, /* 12196 */ IC_EVEX_L2_XD_K_B, /* 12197 */ IC_EVEX_L2_XD_K_B, /* 12198 */ IC_EVEX_L2_XD_K_B, /* 12199 */ IC_EVEX_L2_W_K_B, /* 12200 */ IC_EVEX_L2_W_K_B, /* 12201 */ IC_EVEX_L2_W_XS_K_B, /* 12202 */ IC_EVEX_L2_W_XS_K_B, /* 12203 */ IC_EVEX_L2_W_XD_K_B, /* 12204 */ IC_EVEX_L2_W_XD_K_B, /* 12205 */ IC_EVEX_L2_W_XD_K_B, /* 12206 */ IC_EVEX_L2_W_XD_K_B, /* 12207 */ IC_EVEX_L2_OPSIZE_K_B, /* 12208 */ IC_EVEX_L2_OPSIZE_K_B, /* 12209 */ IC_EVEX_L2_OPSIZE_K_B, /* 12210 */ IC_EVEX_L2_OPSIZE_K_B, /* 12211 */ IC_EVEX_L2_OPSIZE_K_B, /* 12212 */ IC_EVEX_L2_OPSIZE_K_B, /* 12213 */ IC_EVEX_L2_OPSIZE_K_B, /* 12214 */ IC_EVEX_L2_OPSIZE_K_B, /* 12215 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12216 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12217 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12218 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12219 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12220 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12221 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12222 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12223 */ IC_EVEX_L2_K_B, /* 12224 */ IC_EVEX_L2_K_B, /* 12225 */ IC_EVEX_L2_XS_K_B, /* 12226 */ IC_EVEX_L2_XS_K_B, /* 12227 */ IC_EVEX_L2_XD_K_B, /* 12228 */ IC_EVEX_L2_XD_K_B, /* 12229 */ IC_EVEX_L2_XD_K_B, /* 12230 */ IC_EVEX_L2_XD_K_B, /* 12231 */ IC_EVEX_L2_W_K_B, /* 12232 */ IC_EVEX_L2_W_K_B, /* 12233 */ IC_EVEX_L2_W_XS_K_B, /* 12234 */ IC_EVEX_L2_W_XS_K_B, /* 12235 */ IC_EVEX_L2_W_XD_K_B, /* 12236 */ IC_EVEX_L2_W_XD_K_B, /* 12237 */ IC_EVEX_L2_W_XD_K_B, /* 12238 */ IC_EVEX_L2_W_XD_K_B, /* 12239 */ IC_EVEX_L2_OPSIZE_K_B, /* 12240 */ IC_EVEX_L2_OPSIZE_K_B, /* 12241 */ IC_EVEX_L2_OPSIZE_K_B, /* 12242 */ IC_EVEX_L2_OPSIZE_K_B, /* 12243 */ IC_EVEX_L2_OPSIZE_K_B, /* 12244 */ IC_EVEX_L2_OPSIZE_K_B, /* 12245 */ IC_EVEX_L2_OPSIZE_K_B, /* 12246 */ IC_EVEX_L2_OPSIZE_K_B, /* 12247 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12248 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12249 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12250 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12251 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12252 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12253 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12254 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12255 */ IC_EVEX_L2_K_B, /* 12256 */ IC_EVEX_L2_K_B, /* 12257 */ IC_EVEX_L2_XS_K_B, /* 12258 */ IC_EVEX_L2_XS_K_B, /* 12259 */ IC_EVEX_L2_XD_K_B, /* 12260 */ IC_EVEX_L2_XD_K_B, /* 12261 */ IC_EVEX_L2_XD_K_B, /* 12262 */ IC_EVEX_L2_XD_K_B, /* 12263 */ IC_EVEX_L2_W_K_B, /* 12264 */ IC_EVEX_L2_W_K_B, /* 12265 */ IC_EVEX_L2_W_XS_K_B, /* 12266 */ IC_EVEX_L2_W_XS_K_B, /* 12267 */ IC_EVEX_L2_W_XD_K_B, /* 12268 */ IC_EVEX_L2_W_XD_K_B, /* 12269 */ IC_EVEX_L2_W_XD_K_B, /* 12270 */ IC_EVEX_L2_W_XD_K_B, /* 12271 */ IC_EVEX_L2_OPSIZE_K_B, /* 12272 */ IC_EVEX_L2_OPSIZE_K_B, /* 12273 */ IC_EVEX_L2_OPSIZE_K_B, /* 12274 */ IC_EVEX_L2_OPSIZE_K_B, /* 12275 */ IC_EVEX_L2_OPSIZE_K_B, /* 12276 */ IC_EVEX_L2_OPSIZE_K_B, /* 12277 */ IC_EVEX_L2_OPSIZE_K_B, /* 12278 */ IC_EVEX_L2_OPSIZE_K_B, /* 12279 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12280 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12281 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12282 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12283 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12284 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12285 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12286 */ IC_EVEX_L2_W_OPSIZE_K_B, /* 12287 */ IC, /* 12288 */ IC_64BIT, /* 12289 */ IC_XS, /* 12290 */ IC_64BIT_XS, /* 12291 */ IC_XD, /* 12292 */ IC_64BIT_XD, /* 12293 */ IC_XS, /* 12294 */ IC_64BIT_XS, /* 12295 */ IC, /* 12296 */ IC_64BIT_REXW, /* 12297 */ IC_XS, /* 12298 */ IC_64BIT_REXW_XS, /* 12299 */ IC_XD, /* 12300 */ IC_64BIT_REXW_XD, /* 12301 */ IC_XS, /* 12302 */ IC_64BIT_REXW_XS, /* 12303 */ IC_OPSIZE, /* 12304 */ IC_64BIT_OPSIZE, /* 12305 */ IC_XS_OPSIZE, /* 12306 */ IC_64BIT_XS_OPSIZE, /* 12307 */ IC_XD_OPSIZE, /* 12308 */ IC_64BIT_XD_OPSIZE, /* 12309 */ IC_XS_OPSIZE, /* 12310 */ IC_64BIT_XD_OPSIZE, /* 12311 */ IC_OPSIZE, /* 12312 */ IC_64BIT_REXW_OPSIZE, /* 12313 */ IC_XS_OPSIZE, /* 12314 */ IC_64BIT_REXW_XS, /* 12315 */ IC_XD_OPSIZE, /* 12316 */ IC_64BIT_REXW_XD, /* 12317 */ IC_XS_OPSIZE, /* 12318 */ IC_64BIT_REXW_XS, /* 12319 */ IC_ADSIZE, /* 12320 */ IC_64BIT_ADSIZE, /* 12321 */ IC_XS_ADSIZE, /* 12322 */ IC_64BIT_XS_ADSIZE, /* 12323 */ IC_XD_ADSIZE, /* 12324 */ IC_64BIT_XD_ADSIZE, /* 12325 */ IC_XS_ADSIZE, /* 12326 */ IC_64BIT_XD_ADSIZE, /* 12327 */ IC_ADSIZE, /* 12328 */ IC_64BIT_REXW_ADSIZE, /* 12329 */ IC_XS_ADSIZE, /* 12330 */ IC_64BIT_REXW_XS, /* 12331 */ IC_XD_ADSIZE, /* 12332 */ IC_64BIT_REXW_XD, /* 12333 */ IC_XS_ADSIZE, /* 12334 */ IC_64BIT_REXW_XS, /* 12335 */ IC_OPSIZE_ADSIZE, /* 12336 */ IC_64BIT_OPSIZE_ADSIZE, /* 12337 */ IC_XS_OPSIZE, /* 12338 */ IC_64BIT_XS_OPSIZE, /* 12339 */ IC_XD_OPSIZE, /* 12340 */ IC_64BIT_XD_OPSIZE, /* 12341 */ IC_XS_OPSIZE, /* 12342 */ IC_64BIT_XD_OPSIZE, /* 12343 */ IC_OPSIZE_ADSIZE, /* 12344 */ IC_64BIT_REXW_OPSIZE, /* 12345 */ IC_XS_OPSIZE, /* 12346 */ IC_64BIT_REXW_XS, /* 12347 */ IC_XD_OPSIZE, /* 12348 */ IC_64BIT_REXW_XD, /* 12349 */ IC_XS_OPSIZE, /* 12350 */ IC_64BIT_REXW_XS, /* 12351 */ IC_VEX, /* 12352 */ IC_VEX, /* 12353 */ IC_VEX_XS, /* 12354 */ IC_VEX_XS, /* 12355 */ IC_VEX_XD, /* 12356 */ IC_VEX_XD, /* 12357 */ IC_VEX_XD, /* 12358 */ IC_VEX_XD, /* 12359 */ IC_VEX_W, /* 12360 */ IC_VEX_W, /* 12361 */ IC_VEX_W_XS, /* 12362 */ IC_VEX_W_XS, /* 12363 */ IC_VEX_W_XD, /* 12364 */ IC_VEX_W_XD, /* 12365 */ IC_VEX_W_XD, /* 12366 */ IC_VEX_W_XD, /* 12367 */ IC_VEX_OPSIZE, /* 12368 */ IC_VEX_OPSIZE, /* 12369 */ IC_VEX_OPSIZE, /* 12370 */ IC_VEX_OPSIZE, /* 12371 */ IC_VEX_OPSIZE, /* 12372 */ IC_VEX_OPSIZE, /* 12373 */ IC_VEX_OPSIZE, /* 12374 */ IC_VEX_OPSIZE, /* 12375 */ IC_VEX_W_OPSIZE, /* 12376 */ IC_VEX_W_OPSIZE, /* 12377 */ IC_VEX_W_OPSIZE, /* 12378 */ IC_VEX_W_OPSIZE, /* 12379 */ IC_VEX_W_OPSIZE, /* 12380 */ IC_VEX_W_OPSIZE, /* 12381 */ IC_VEX_W_OPSIZE, /* 12382 */ IC_VEX_W_OPSIZE, /* 12383 */ IC_VEX, /* 12384 */ IC_VEX, /* 12385 */ IC_VEX_XS, /* 12386 */ IC_VEX_XS, /* 12387 */ IC_VEX_XD, /* 12388 */ IC_VEX_XD, /* 12389 */ IC_VEX_XD, /* 12390 */ IC_VEX_XD, /* 12391 */ IC_VEX_W, /* 12392 */ IC_VEX_W, /* 12393 */ IC_VEX_W_XS, /* 12394 */ IC_VEX_W_XS, /* 12395 */ IC_VEX_W_XD, /* 12396 */ IC_VEX_W_XD, /* 12397 */ IC_VEX_W_XD, /* 12398 */ IC_VEX_W_XD, /* 12399 */ IC_VEX_OPSIZE, /* 12400 */ IC_VEX_OPSIZE, /* 12401 */ IC_VEX_OPSIZE, /* 12402 */ IC_VEX_OPSIZE, /* 12403 */ IC_VEX_OPSIZE, /* 12404 */ IC_VEX_OPSIZE, /* 12405 */ IC_VEX_OPSIZE, /* 12406 */ IC_VEX_OPSIZE, /* 12407 */ IC_VEX_W_OPSIZE, /* 12408 */ IC_VEX_W_OPSIZE, /* 12409 */ IC_VEX_W_OPSIZE, /* 12410 */ IC_VEX_W_OPSIZE, /* 12411 */ IC_VEX_W_OPSIZE, /* 12412 */ IC_VEX_W_OPSIZE, /* 12413 */ IC_VEX_W_OPSIZE, /* 12414 */ IC_VEX_W_OPSIZE, /* 12415 */ IC_VEX_L, /* 12416 */ IC_VEX_L, /* 12417 */ IC_VEX_L_XS, /* 12418 */ IC_VEX_L_XS, /* 12419 */ IC_VEX_L_XD, /* 12420 */ IC_VEX_L_XD, /* 12421 */ IC_VEX_L_XD, /* 12422 */ IC_VEX_L_XD, /* 12423 */ IC_VEX_L_W, /* 12424 */ IC_VEX_L_W, /* 12425 */ IC_VEX_L_W_XS, /* 12426 */ IC_VEX_L_W_XS, /* 12427 */ IC_VEX_L_W_XD, /* 12428 */ IC_VEX_L_W_XD, /* 12429 */ IC_VEX_L_W_XD, /* 12430 */ IC_VEX_L_W_XD, /* 12431 */ IC_VEX_L_OPSIZE, /* 12432 */ IC_VEX_L_OPSIZE, /* 12433 */ IC_VEX_L_OPSIZE, /* 12434 */ IC_VEX_L_OPSIZE, /* 12435 */ IC_VEX_L_OPSIZE, /* 12436 */ IC_VEX_L_OPSIZE, /* 12437 */ IC_VEX_L_OPSIZE, /* 12438 */ IC_VEX_L_OPSIZE, /* 12439 */ IC_VEX_L_W_OPSIZE, /* 12440 */ IC_VEX_L_W_OPSIZE, /* 12441 */ IC_VEX_L_W_OPSIZE, /* 12442 */ IC_VEX_L_W_OPSIZE, /* 12443 */ IC_VEX_L_W_OPSIZE, /* 12444 */ IC_VEX_L_W_OPSIZE, /* 12445 */ IC_VEX_L_W_OPSIZE, /* 12446 */ IC_VEX_L_W_OPSIZE, /* 12447 */ IC_VEX_L, /* 12448 */ IC_VEX_L, /* 12449 */ IC_VEX_L_XS, /* 12450 */ IC_VEX_L_XS, /* 12451 */ IC_VEX_L_XD, /* 12452 */ IC_VEX_L_XD, /* 12453 */ IC_VEX_L_XD, /* 12454 */ IC_VEX_L_XD, /* 12455 */ IC_VEX_L_W, /* 12456 */ IC_VEX_L_W, /* 12457 */ IC_VEX_L_W_XS, /* 12458 */ IC_VEX_L_W_XS, /* 12459 */ IC_VEX_L_W_XD, /* 12460 */ IC_VEX_L_W_XD, /* 12461 */ IC_VEX_L_W_XD, /* 12462 */ IC_VEX_L_W_XD, /* 12463 */ IC_VEX_L_OPSIZE, /* 12464 */ IC_VEX_L_OPSIZE, /* 12465 */ IC_VEX_L_OPSIZE, /* 12466 */ IC_VEX_L_OPSIZE, /* 12467 */ IC_VEX_L_OPSIZE, /* 12468 */ IC_VEX_L_OPSIZE, /* 12469 */ IC_VEX_L_OPSIZE, /* 12470 */ IC_VEX_L_OPSIZE, /* 12471 */ IC_VEX_L_W_OPSIZE, /* 12472 */ IC_VEX_L_W_OPSIZE, /* 12473 */ IC_VEX_L_W_OPSIZE, /* 12474 */ IC_VEX_L_W_OPSIZE, /* 12475 */ IC_VEX_L_W_OPSIZE, /* 12476 */ IC_VEX_L_W_OPSIZE, /* 12477 */ IC_VEX_L_W_OPSIZE, /* 12478 */ IC_VEX_L_W_OPSIZE, /* 12479 */ IC_VEX_L, /* 12480 */ IC_VEX_L, /* 12481 */ IC_VEX_L_XS, /* 12482 */ IC_VEX_L_XS, /* 12483 */ IC_VEX_L_XD, /* 12484 */ IC_VEX_L_XD, /* 12485 */ IC_VEX_L_XD, /* 12486 */ IC_VEX_L_XD, /* 12487 */ IC_VEX_L_W, /* 12488 */ IC_VEX_L_W, /* 12489 */ IC_VEX_L_W_XS, /* 12490 */ IC_VEX_L_W_XS, /* 12491 */ IC_VEX_L_W_XD, /* 12492 */ IC_VEX_L_W_XD, /* 12493 */ IC_VEX_L_W_XD, /* 12494 */ IC_VEX_L_W_XD, /* 12495 */ IC_VEX_L_OPSIZE, /* 12496 */ IC_VEX_L_OPSIZE, /* 12497 */ IC_VEX_L_OPSIZE, /* 12498 */ IC_VEX_L_OPSIZE, /* 12499 */ IC_VEX_L_OPSIZE, /* 12500 */ IC_VEX_L_OPSIZE, /* 12501 */ IC_VEX_L_OPSIZE, /* 12502 */ IC_VEX_L_OPSIZE, /* 12503 */ IC_VEX_L_W_OPSIZE, /* 12504 */ IC_VEX_L_W_OPSIZE, /* 12505 */ IC_VEX_L_W_OPSIZE, /* 12506 */ IC_VEX_L_W_OPSIZE, /* 12507 */ IC_VEX_L_W_OPSIZE, /* 12508 */ IC_VEX_L_W_OPSIZE, /* 12509 */ IC_VEX_L_W_OPSIZE, /* 12510 */ IC_VEX_L_W_OPSIZE, /* 12511 */ IC_VEX_L, /* 12512 */ IC_VEX_L, /* 12513 */ IC_VEX_L_XS, /* 12514 */ IC_VEX_L_XS, /* 12515 */ IC_VEX_L_XD, /* 12516 */ IC_VEX_L_XD, /* 12517 */ IC_VEX_L_XD, /* 12518 */ IC_VEX_L_XD, /* 12519 */ IC_VEX_L_W, /* 12520 */ IC_VEX_L_W, /* 12521 */ IC_VEX_L_W_XS, /* 12522 */ IC_VEX_L_W_XS, /* 12523 */ IC_VEX_L_W_XD, /* 12524 */ IC_VEX_L_W_XD, /* 12525 */ IC_VEX_L_W_XD, /* 12526 */ IC_VEX_L_W_XD, /* 12527 */ IC_VEX_L_OPSIZE, /* 12528 */ IC_VEX_L_OPSIZE, /* 12529 */ IC_VEX_L_OPSIZE, /* 12530 */ IC_VEX_L_OPSIZE, /* 12531 */ IC_VEX_L_OPSIZE, /* 12532 */ IC_VEX_L_OPSIZE, /* 12533 */ IC_VEX_L_OPSIZE, /* 12534 */ IC_VEX_L_OPSIZE, /* 12535 */ IC_VEX_L_W_OPSIZE, /* 12536 */ IC_VEX_L_W_OPSIZE, /* 12537 */ IC_VEX_L_W_OPSIZE, /* 12538 */ IC_VEX_L_W_OPSIZE, /* 12539 */ IC_VEX_L_W_OPSIZE, /* 12540 */ IC_VEX_L_W_OPSIZE, /* 12541 */ IC_VEX_L_W_OPSIZE, /* 12542 */ IC_VEX_L_W_OPSIZE, /* 12543 */ IC_EVEX_KZ_B, /* 12544 */ IC_EVEX_KZ_B, /* 12545 */ IC_EVEX_XS_KZ_B, /* 12546 */ IC_EVEX_XS_KZ_B, /* 12547 */ IC_EVEX_XD_KZ_B, /* 12548 */ IC_EVEX_XD_KZ_B, /* 12549 */ IC_EVEX_XD_KZ_B, /* 12550 */ IC_EVEX_XD_KZ_B, /* 12551 */ IC_EVEX_W_KZ_B, /* 12552 */ IC_EVEX_W_KZ_B, /* 12553 */ IC_EVEX_W_XS_KZ_B, /* 12554 */ IC_EVEX_W_XS_KZ_B, /* 12555 */ IC_EVEX_W_XD_KZ_B, /* 12556 */ IC_EVEX_W_XD_KZ_B, /* 12557 */ IC_EVEX_W_XD_KZ_B, /* 12558 */ IC_EVEX_W_XD_KZ_B, /* 12559 */ IC_EVEX_OPSIZE_KZ_B, /* 12560 */ IC_EVEX_OPSIZE_KZ_B, /* 12561 */ IC_EVEX_OPSIZE_KZ_B, /* 12562 */ IC_EVEX_OPSIZE_KZ_B, /* 12563 */ IC_EVEX_OPSIZE_KZ_B, /* 12564 */ IC_EVEX_OPSIZE_KZ_B, /* 12565 */ IC_EVEX_OPSIZE_KZ_B, /* 12566 */ IC_EVEX_OPSIZE_KZ_B, /* 12567 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12568 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12569 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12570 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12571 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12572 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12573 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12574 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12575 */ IC_EVEX_KZ_B, /* 12576 */ IC_EVEX_KZ_B, /* 12577 */ IC_EVEX_XS_KZ_B, /* 12578 */ IC_EVEX_XS_KZ_B, /* 12579 */ IC_EVEX_XD_KZ_B, /* 12580 */ IC_EVEX_XD_KZ_B, /* 12581 */ IC_EVEX_XD_KZ_B, /* 12582 */ IC_EVEX_XD_KZ_B, /* 12583 */ IC_EVEX_W_KZ_B, /* 12584 */ IC_EVEX_W_KZ_B, /* 12585 */ IC_EVEX_W_XS_KZ_B, /* 12586 */ IC_EVEX_W_XS_KZ_B, /* 12587 */ IC_EVEX_W_XD_KZ_B, /* 12588 */ IC_EVEX_W_XD_KZ_B, /* 12589 */ IC_EVEX_W_XD_KZ_B, /* 12590 */ IC_EVEX_W_XD_KZ_B, /* 12591 */ IC_EVEX_OPSIZE_KZ_B, /* 12592 */ IC_EVEX_OPSIZE_KZ_B, /* 12593 */ IC_EVEX_OPSIZE_KZ_B, /* 12594 */ IC_EVEX_OPSIZE_KZ_B, /* 12595 */ IC_EVEX_OPSIZE_KZ_B, /* 12596 */ IC_EVEX_OPSIZE_KZ_B, /* 12597 */ IC_EVEX_OPSIZE_KZ_B, /* 12598 */ IC_EVEX_OPSIZE_KZ_B, /* 12599 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12600 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12601 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12602 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12603 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12604 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12605 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12606 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12607 */ IC_EVEX_KZ_B, /* 12608 */ IC_EVEX_KZ_B, /* 12609 */ IC_EVEX_XS_KZ_B, /* 12610 */ IC_EVEX_XS_KZ_B, /* 12611 */ IC_EVEX_XD_KZ_B, /* 12612 */ IC_EVEX_XD_KZ_B, /* 12613 */ IC_EVEX_XD_KZ_B, /* 12614 */ IC_EVEX_XD_KZ_B, /* 12615 */ IC_EVEX_W_KZ_B, /* 12616 */ IC_EVEX_W_KZ_B, /* 12617 */ IC_EVEX_W_XS_KZ_B, /* 12618 */ IC_EVEX_W_XS_KZ_B, /* 12619 */ IC_EVEX_W_XD_KZ_B, /* 12620 */ IC_EVEX_W_XD_KZ_B, /* 12621 */ IC_EVEX_W_XD_KZ_B, /* 12622 */ IC_EVEX_W_XD_KZ_B, /* 12623 */ IC_EVEX_OPSIZE_KZ_B, /* 12624 */ IC_EVEX_OPSIZE_KZ_B, /* 12625 */ IC_EVEX_OPSIZE_KZ_B, /* 12626 */ IC_EVEX_OPSIZE_KZ_B, /* 12627 */ IC_EVEX_OPSIZE_KZ_B, /* 12628 */ IC_EVEX_OPSIZE_KZ_B, /* 12629 */ IC_EVEX_OPSIZE_KZ_B, /* 12630 */ IC_EVEX_OPSIZE_KZ_B, /* 12631 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12632 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12633 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12634 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12635 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12636 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12637 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12638 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12639 */ IC_EVEX_KZ_B, /* 12640 */ IC_EVEX_KZ_B, /* 12641 */ IC_EVEX_XS_KZ_B, /* 12642 */ IC_EVEX_XS_KZ_B, /* 12643 */ IC_EVEX_XD_KZ_B, /* 12644 */ IC_EVEX_XD_KZ_B, /* 12645 */ IC_EVEX_XD_KZ_B, /* 12646 */ IC_EVEX_XD_KZ_B, /* 12647 */ IC_EVEX_W_KZ_B, /* 12648 */ IC_EVEX_W_KZ_B, /* 12649 */ IC_EVEX_W_XS_KZ_B, /* 12650 */ IC_EVEX_W_XS_KZ_B, /* 12651 */ IC_EVEX_W_XD_KZ_B, /* 12652 */ IC_EVEX_W_XD_KZ_B, /* 12653 */ IC_EVEX_W_XD_KZ_B, /* 12654 */ IC_EVEX_W_XD_KZ_B, /* 12655 */ IC_EVEX_OPSIZE_KZ_B, /* 12656 */ IC_EVEX_OPSIZE_KZ_B, /* 12657 */ IC_EVEX_OPSIZE_KZ_B, /* 12658 */ IC_EVEX_OPSIZE_KZ_B, /* 12659 */ IC_EVEX_OPSIZE_KZ_B, /* 12660 */ IC_EVEX_OPSIZE_KZ_B, /* 12661 */ IC_EVEX_OPSIZE_KZ_B, /* 12662 */ IC_EVEX_OPSIZE_KZ_B, /* 12663 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12664 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12665 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12666 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12667 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12668 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12669 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12670 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12671 */ IC_EVEX_KZ_B, /* 12672 */ IC_EVEX_KZ_B, /* 12673 */ IC_EVEX_XS_KZ_B, /* 12674 */ IC_EVEX_XS_KZ_B, /* 12675 */ IC_EVEX_XD_KZ_B, /* 12676 */ IC_EVEX_XD_KZ_B, /* 12677 */ IC_EVEX_XD_KZ_B, /* 12678 */ IC_EVEX_XD_KZ_B, /* 12679 */ IC_EVEX_W_KZ_B, /* 12680 */ IC_EVEX_W_KZ_B, /* 12681 */ IC_EVEX_W_XS_KZ_B, /* 12682 */ IC_EVEX_W_XS_KZ_B, /* 12683 */ IC_EVEX_W_XD_KZ_B, /* 12684 */ IC_EVEX_W_XD_KZ_B, /* 12685 */ IC_EVEX_W_XD_KZ_B, /* 12686 */ IC_EVEX_W_XD_KZ_B, /* 12687 */ IC_EVEX_OPSIZE_KZ_B, /* 12688 */ IC_EVEX_OPSIZE_KZ_B, /* 12689 */ IC_EVEX_OPSIZE_KZ_B, /* 12690 */ IC_EVEX_OPSIZE_KZ_B, /* 12691 */ IC_EVEX_OPSIZE_KZ_B, /* 12692 */ IC_EVEX_OPSIZE_KZ_B, /* 12693 */ IC_EVEX_OPSIZE_KZ_B, /* 12694 */ IC_EVEX_OPSIZE_KZ_B, /* 12695 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12696 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12697 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12698 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12699 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12700 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12701 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12702 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12703 */ IC_EVEX_KZ_B, /* 12704 */ IC_EVEX_KZ_B, /* 12705 */ IC_EVEX_XS_KZ_B, /* 12706 */ IC_EVEX_XS_KZ_B, /* 12707 */ IC_EVEX_XD_KZ_B, /* 12708 */ IC_EVEX_XD_KZ_B, /* 12709 */ IC_EVEX_XD_KZ_B, /* 12710 */ IC_EVEX_XD_KZ_B, /* 12711 */ IC_EVEX_W_KZ_B, /* 12712 */ IC_EVEX_W_KZ_B, /* 12713 */ IC_EVEX_W_XS_KZ_B, /* 12714 */ IC_EVEX_W_XS_KZ_B, /* 12715 */ IC_EVEX_W_XD_KZ_B, /* 12716 */ IC_EVEX_W_XD_KZ_B, /* 12717 */ IC_EVEX_W_XD_KZ_B, /* 12718 */ IC_EVEX_W_XD_KZ_B, /* 12719 */ IC_EVEX_OPSIZE_KZ_B, /* 12720 */ IC_EVEX_OPSIZE_KZ_B, /* 12721 */ IC_EVEX_OPSIZE_KZ_B, /* 12722 */ IC_EVEX_OPSIZE_KZ_B, /* 12723 */ IC_EVEX_OPSIZE_KZ_B, /* 12724 */ IC_EVEX_OPSIZE_KZ_B, /* 12725 */ IC_EVEX_OPSIZE_KZ_B, /* 12726 */ IC_EVEX_OPSIZE_KZ_B, /* 12727 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12728 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12729 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12730 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12731 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12732 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12733 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12734 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12735 */ IC_EVEX_KZ_B, /* 12736 */ IC_EVEX_KZ_B, /* 12737 */ IC_EVEX_XS_KZ_B, /* 12738 */ IC_EVEX_XS_KZ_B, /* 12739 */ IC_EVEX_XD_KZ_B, /* 12740 */ IC_EVEX_XD_KZ_B, /* 12741 */ IC_EVEX_XD_KZ_B, /* 12742 */ IC_EVEX_XD_KZ_B, /* 12743 */ IC_EVEX_W_KZ_B, /* 12744 */ IC_EVEX_W_KZ_B, /* 12745 */ IC_EVEX_W_XS_KZ_B, /* 12746 */ IC_EVEX_W_XS_KZ_B, /* 12747 */ IC_EVEX_W_XD_KZ_B, /* 12748 */ IC_EVEX_W_XD_KZ_B, /* 12749 */ IC_EVEX_W_XD_KZ_B, /* 12750 */ IC_EVEX_W_XD_KZ_B, /* 12751 */ IC_EVEX_OPSIZE_KZ_B, /* 12752 */ IC_EVEX_OPSIZE_KZ_B, /* 12753 */ IC_EVEX_OPSIZE_KZ_B, /* 12754 */ IC_EVEX_OPSIZE_KZ_B, /* 12755 */ IC_EVEX_OPSIZE_KZ_B, /* 12756 */ IC_EVEX_OPSIZE_KZ_B, /* 12757 */ IC_EVEX_OPSIZE_KZ_B, /* 12758 */ IC_EVEX_OPSIZE_KZ_B, /* 12759 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12760 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12761 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12762 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12763 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12764 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12765 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12766 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12767 */ IC_EVEX_KZ_B, /* 12768 */ IC_EVEX_KZ_B, /* 12769 */ IC_EVEX_XS_KZ_B, /* 12770 */ IC_EVEX_XS_KZ_B, /* 12771 */ IC_EVEX_XD_KZ_B, /* 12772 */ IC_EVEX_XD_KZ_B, /* 12773 */ IC_EVEX_XD_KZ_B, /* 12774 */ IC_EVEX_XD_KZ_B, /* 12775 */ IC_EVEX_W_KZ_B, /* 12776 */ IC_EVEX_W_KZ_B, /* 12777 */ IC_EVEX_W_XS_KZ_B, /* 12778 */ IC_EVEX_W_XS_KZ_B, /* 12779 */ IC_EVEX_W_XD_KZ_B, /* 12780 */ IC_EVEX_W_XD_KZ_B, /* 12781 */ IC_EVEX_W_XD_KZ_B, /* 12782 */ IC_EVEX_W_XD_KZ_B, /* 12783 */ IC_EVEX_OPSIZE_KZ_B, /* 12784 */ IC_EVEX_OPSIZE_KZ_B, /* 12785 */ IC_EVEX_OPSIZE_KZ_B, /* 12786 */ IC_EVEX_OPSIZE_KZ_B, /* 12787 */ IC_EVEX_OPSIZE_KZ_B, /* 12788 */ IC_EVEX_OPSIZE_KZ_B, /* 12789 */ IC_EVEX_OPSIZE_KZ_B, /* 12790 */ IC_EVEX_OPSIZE_KZ_B, /* 12791 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12792 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12793 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12794 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12795 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12796 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12797 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12798 */ IC_EVEX_W_OPSIZE_KZ_B, /* 12799 */ IC, /* 12800 */ IC_64BIT, /* 12801 */ IC_XS, /* 12802 */ IC_64BIT_XS, /* 12803 */ IC_XD, /* 12804 */ IC_64BIT_XD, /* 12805 */ IC_XS, /* 12806 */ IC_64BIT_XS, /* 12807 */ IC, /* 12808 */ IC_64BIT_REXW, /* 12809 */ IC_XS, /* 12810 */ IC_64BIT_REXW_XS, /* 12811 */ IC_XD, /* 12812 */ IC_64BIT_REXW_XD, /* 12813 */ IC_XS, /* 12814 */ IC_64BIT_REXW_XS, /* 12815 */ IC_OPSIZE, /* 12816 */ IC_64BIT_OPSIZE, /* 12817 */ IC_XS_OPSIZE, /* 12818 */ IC_64BIT_XS_OPSIZE, /* 12819 */ IC_XD_OPSIZE, /* 12820 */ IC_64BIT_XD_OPSIZE, /* 12821 */ IC_XS_OPSIZE, /* 12822 */ IC_64BIT_XD_OPSIZE, /* 12823 */ IC_OPSIZE, /* 12824 */ IC_64BIT_REXW_OPSIZE, /* 12825 */ IC_XS_OPSIZE, /* 12826 */ IC_64BIT_REXW_XS, /* 12827 */ IC_XD_OPSIZE, /* 12828 */ IC_64BIT_REXW_XD, /* 12829 */ IC_XS_OPSIZE, /* 12830 */ IC_64BIT_REXW_XS, /* 12831 */ IC_ADSIZE, /* 12832 */ IC_64BIT_ADSIZE, /* 12833 */ IC_XS_ADSIZE, /* 12834 */ IC_64BIT_XS_ADSIZE, /* 12835 */ IC_XD_ADSIZE, /* 12836 */ IC_64BIT_XD_ADSIZE, /* 12837 */ IC_XS_ADSIZE, /* 12838 */ IC_64BIT_XD_ADSIZE, /* 12839 */ IC_ADSIZE, /* 12840 */ IC_64BIT_REXW_ADSIZE, /* 12841 */ IC_XS_ADSIZE, /* 12842 */ IC_64BIT_REXW_XS, /* 12843 */ IC_XD_ADSIZE, /* 12844 */ IC_64BIT_REXW_XD, /* 12845 */ IC_XS_ADSIZE, /* 12846 */ IC_64BIT_REXW_XS, /* 12847 */ IC_OPSIZE_ADSIZE, /* 12848 */ IC_64BIT_OPSIZE_ADSIZE, /* 12849 */ IC_XS_OPSIZE, /* 12850 */ IC_64BIT_XS_OPSIZE, /* 12851 */ IC_XD_OPSIZE, /* 12852 */ IC_64BIT_XD_OPSIZE, /* 12853 */ IC_XS_OPSIZE, /* 12854 */ IC_64BIT_XD_OPSIZE, /* 12855 */ IC_OPSIZE_ADSIZE, /* 12856 */ IC_64BIT_REXW_OPSIZE, /* 12857 */ IC_XS_OPSIZE, /* 12858 */ IC_64BIT_REXW_XS, /* 12859 */ IC_XD_OPSIZE, /* 12860 */ IC_64BIT_REXW_XD, /* 12861 */ IC_XS_OPSIZE, /* 12862 */ IC_64BIT_REXW_XS, /* 12863 */ IC_VEX, /* 12864 */ IC_VEX, /* 12865 */ IC_VEX_XS, /* 12866 */ IC_VEX_XS, /* 12867 */ IC_VEX_XD, /* 12868 */ IC_VEX_XD, /* 12869 */ IC_VEX_XD, /* 12870 */ IC_VEX_XD, /* 12871 */ IC_VEX_W, /* 12872 */ IC_VEX_W, /* 12873 */ IC_VEX_W_XS, /* 12874 */ IC_VEX_W_XS, /* 12875 */ IC_VEX_W_XD, /* 12876 */ IC_VEX_W_XD, /* 12877 */ IC_VEX_W_XD, /* 12878 */ IC_VEX_W_XD, /* 12879 */ IC_VEX_OPSIZE, /* 12880 */ IC_VEX_OPSIZE, /* 12881 */ IC_VEX_OPSIZE, /* 12882 */ IC_VEX_OPSIZE, /* 12883 */ IC_VEX_OPSIZE, /* 12884 */ IC_VEX_OPSIZE, /* 12885 */ IC_VEX_OPSIZE, /* 12886 */ IC_VEX_OPSIZE, /* 12887 */ IC_VEX_W_OPSIZE, /* 12888 */ IC_VEX_W_OPSIZE, /* 12889 */ IC_VEX_W_OPSIZE, /* 12890 */ IC_VEX_W_OPSIZE, /* 12891 */ IC_VEX_W_OPSIZE, /* 12892 */ IC_VEX_W_OPSIZE, /* 12893 */ IC_VEX_W_OPSIZE, /* 12894 */ IC_VEX_W_OPSIZE, /* 12895 */ IC_VEX, /* 12896 */ IC_VEX, /* 12897 */ IC_VEX_XS, /* 12898 */ IC_VEX_XS, /* 12899 */ IC_VEX_XD, /* 12900 */ IC_VEX_XD, /* 12901 */ IC_VEX_XD, /* 12902 */ IC_VEX_XD, /* 12903 */ IC_VEX_W, /* 12904 */ IC_VEX_W, /* 12905 */ IC_VEX_W_XS, /* 12906 */ IC_VEX_W_XS, /* 12907 */ IC_VEX_W_XD, /* 12908 */ IC_VEX_W_XD, /* 12909 */ IC_VEX_W_XD, /* 12910 */ IC_VEX_W_XD, /* 12911 */ IC_VEX_OPSIZE, /* 12912 */ IC_VEX_OPSIZE, /* 12913 */ IC_VEX_OPSIZE, /* 12914 */ IC_VEX_OPSIZE, /* 12915 */ IC_VEX_OPSIZE, /* 12916 */ IC_VEX_OPSIZE, /* 12917 */ IC_VEX_OPSIZE, /* 12918 */ IC_VEX_OPSIZE, /* 12919 */ IC_VEX_W_OPSIZE, /* 12920 */ IC_VEX_W_OPSIZE, /* 12921 */ IC_VEX_W_OPSIZE, /* 12922 */ IC_VEX_W_OPSIZE, /* 12923 */ IC_VEX_W_OPSIZE, /* 12924 */ IC_VEX_W_OPSIZE, /* 12925 */ IC_VEX_W_OPSIZE, /* 12926 */ IC_VEX_W_OPSIZE, /* 12927 */ IC_VEX_L, /* 12928 */ IC_VEX_L, /* 12929 */ IC_VEX_L_XS, /* 12930 */ IC_VEX_L_XS, /* 12931 */ IC_VEX_L_XD, /* 12932 */ IC_VEX_L_XD, /* 12933 */ IC_VEX_L_XD, /* 12934 */ IC_VEX_L_XD, /* 12935 */ IC_VEX_L_W, /* 12936 */ IC_VEX_L_W, /* 12937 */ IC_VEX_L_W_XS, /* 12938 */ IC_VEX_L_W_XS, /* 12939 */ IC_VEX_L_W_XD, /* 12940 */ IC_VEX_L_W_XD, /* 12941 */ IC_VEX_L_W_XD, /* 12942 */ IC_VEX_L_W_XD, /* 12943 */ IC_VEX_L_OPSIZE, /* 12944 */ IC_VEX_L_OPSIZE, /* 12945 */ IC_VEX_L_OPSIZE, /* 12946 */ IC_VEX_L_OPSIZE, /* 12947 */ IC_VEX_L_OPSIZE, /* 12948 */ IC_VEX_L_OPSIZE, /* 12949 */ IC_VEX_L_OPSIZE, /* 12950 */ IC_VEX_L_OPSIZE, /* 12951 */ IC_VEX_L_W_OPSIZE, /* 12952 */ IC_VEX_L_W_OPSIZE, /* 12953 */ IC_VEX_L_W_OPSIZE, /* 12954 */ IC_VEX_L_W_OPSIZE, /* 12955 */ IC_VEX_L_W_OPSIZE, /* 12956 */ IC_VEX_L_W_OPSIZE, /* 12957 */ IC_VEX_L_W_OPSIZE, /* 12958 */ IC_VEX_L_W_OPSIZE, /* 12959 */ IC_VEX_L, /* 12960 */ IC_VEX_L, /* 12961 */ IC_VEX_L_XS, /* 12962 */ IC_VEX_L_XS, /* 12963 */ IC_VEX_L_XD, /* 12964 */ IC_VEX_L_XD, /* 12965 */ IC_VEX_L_XD, /* 12966 */ IC_VEX_L_XD, /* 12967 */ IC_VEX_L_W, /* 12968 */ IC_VEX_L_W, /* 12969 */ IC_VEX_L_W_XS, /* 12970 */ IC_VEX_L_W_XS, /* 12971 */ IC_VEX_L_W_XD, /* 12972 */ IC_VEX_L_W_XD, /* 12973 */ IC_VEX_L_W_XD, /* 12974 */ IC_VEX_L_W_XD, /* 12975 */ IC_VEX_L_OPSIZE, /* 12976 */ IC_VEX_L_OPSIZE, /* 12977 */ IC_VEX_L_OPSIZE, /* 12978 */ IC_VEX_L_OPSIZE, /* 12979 */ IC_VEX_L_OPSIZE, /* 12980 */ IC_VEX_L_OPSIZE, /* 12981 */ IC_VEX_L_OPSIZE, /* 12982 */ IC_VEX_L_OPSIZE, /* 12983 */ IC_VEX_L_W_OPSIZE, /* 12984 */ IC_VEX_L_W_OPSIZE, /* 12985 */ IC_VEX_L_W_OPSIZE, /* 12986 */ IC_VEX_L_W_OPSIZE, /* 12987 */ IC_VEX_L_W_OPSIZE, /* 12988 */ IC_VEX_L_W_OPSIZE, /* 12989 */ IC_VEX_L_W_OPSIZE, /* 12990 */ IC_VEX_L_W_OPSIZE, /* 12991 */ IC_VEX_L, /* 12992 */ IC_VEX_L, /* 12993 */ IC_VEX_L_XS, /* 12994 */ IC_VEX_L_XS, /* 12995 */ IC_VEX_L_XD, /* 12996 */ IC_VEX_L_XD, /* 12997 */ IC_VEX_L_XD, /* 12998 */ IC_VEX_L_XD, /* 12999 */ IC_VEX_L_W, /* 13000 */ IC_VEX_L_W, /* 13001 */ IC_VEX_L_W_XS, /* 13002 */ IC_VEX_L_W_XS, /* 13003 */ IC_VEX_L_W_XD, /* 13004 */ IC_VEX_L_W_XD, /* 13005 */ IC_VEX_L_W_XD, /* 13006 */ IC_VEX_L_W_XD, /* 13007 */ IC_VEX_L_OPSIZE, /* 13008 */ IC_VEX_L_OPSIZE, /* 13009 */ IC_VEX_L_OPSIZE, /* 13010 */ IC_VEX_L_OPSIZE, /* 13011 */ IC_VEX_L_OPSIZE, /* 13012 */ IC_VEX_L_OPSIZE, /* 13013 */ IC_VEX_L_OPSIZE, /* 13014 */ IC_VEX_L_OPSIZE, /* 13015 */ IC_VEX_L_W_OPSIZE, /* 13016 */ IC_VEX_L_W_OPSIZE, /* 13017 */ IC_VEX_L_W_OPSIZE, /* 13018 */ IC_VEX_L_W_OPSIZE, /* 13019 */ IC_VEX_L_W_OPSIZE, /* 13020 */ IC_VEX_L_W_OPSIZE, /* 13021 */ IC_VEX_L_W_OPSIZE, /* 13022 */ IC_VEX_L_W_OPSIZE, /* 13023 */ IC_VEX_L, /* 13024 */ IC_VEX_L, /* 13025 */ IC_VEX_L_XS, /* 13026 */ IC_VEX_L_XS, /* 13027 */ IC_VEX_L_XD, /* 13028 */ IC_VEX_L_XD, /* 13029 */ IC_VEX_L_XD, /* 13030 */ IC_VEX_L_XD, /* 13031 */ IC_VEX_L_W, /* 13032 */ IC_VEX_L_W, /* 13033 */ IC_VEX_L_W_XS, /* 13034 */ IC_VEX_L_W_XS, /* 13035 */ IC_VEX_L_W_XD, /* 13036 */ IC_VEX_L_W_XD, /* 13037 */ IC_VEX_L_W_XD, /* 13038 */ IC_VEX_L_W_XD, /* 13039 */ IC_VEX_L_OPSIZE, /* 13040 */ IC_VEX_L_OPSIZE, /* 13041 */ IC_VEX_L_OPSIZE, /* 13042 */ IC_VEX_L_OPSIZE, /* 13043 */ IC_VEX_L_OPSIZE, /* 13044 */ IC_VEX_L_OPSIZE, /* 13045 */ IC_VEX_L_OPSIZE, /* 13046 */ IC_VEX_L_OPSIZE, /* 13047 */ IC_VEX_L_W_OPSIZE, /* 13048 */ IC_VEX_L_W_OPSIZE, /* 13049 */ IC_VEX_L_W_OPSIZE, /* 13050 */ IC_VEX_L_W_OPSIZE, /* 13051 */ IC_VEX_L_W_OPSIZE, /* 13052 */ IC_VEX_L_W_OPSIZE, /* 13053 */ IC_VEX_L_W_OPSIZE, /* 13054 */ IC_VEX_L_W_OPSIZE, /* 13055 */ IC_EVEX_L_KZ_B, /* 13056 */ IC_EVEX_L_KZ_B, /* 13057 */ IC_EVEX_L_XS_KZ_B, /* 13058 */ IC_EVEX_L_XS_KZ_B, /* 13059 */ IC_EVEX_L_XD_KZ_B, /* 13060 */ IC_EVEX_L_XD_KZ_B, /* 13061 */ IC_EVEX_L_XD_KZ_B, /* 13062 */ IC_EVEX_L_XD_KZ_B, /* 13063 */ IC_EVEX_L_W_KZ_B, /* 13064 */ IC_EVEX_L_W_KZ_B, /* 13065 */ IC_EVEX_L_W_XS_KZ_B, /* 13066 */ IC_EVEX_L_W_XS_KZ_B, /* 13067 */ IC_EVEX_L_W_XD_KZ_B, /* 13068 */ IC_EVEX_L_W_XD_KZ_B, /* 13069 */ IC_EVEX_L_W_XD_KZ_B, /* 13070 */ IC_EVEX_L_W_XD_KZ_B, /* 13071 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13072 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13073 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13074 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13075 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13076 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13077 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13078 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13079 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13080 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13081 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13082 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13083 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13084 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13085 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13086 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13087 */ IC_EVEX_L_KZ_B, /* 13088 */ IC_EVEX_L_KZ_B, /* 13089 */ IC_EVEX_L_XS_KZ_B, /* 13090 */ IC_EVEX_L_XS_KZ_B, /* 13091 */ IC_EVEX_L_XD_KZ_B, /* 13092 */ IC_EVEX_L_XD_KZ_B, /* 13093 */ IC_EVEX_L_XD_KZ_B, /* 13094 */ IC_EVEX_L_XD_KZ_B, /* 13095 */ IC_EVEX_L_W_KZ_B, /* 13096 */ IC_EVEX_L_W_KZ_B, /* 13097 */ IC_EVEX_L_W_XS_KZ_B, /* 13098 */ IC_EVEX_L_W_XS_KZ_B, /* 13099 */ IC_EVEX_L_W_XD_KZ_B, /* 13100 */ IC_EVEX_L_W_XD_KZ_B, /* 13101 */ IC_EVEX_L_W_XD_KZ_B, /* 13102 */ IC_EVEX_L_W_XD_KZ_B, /* 13103 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13104 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13105 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13106 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13107 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13108 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13109 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13110 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13111 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13112 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13113 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13114 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13115 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13116 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13117 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13118 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13119 */ IC_EVEX_L_KZ_B, /* 13120 */ IC_EVEX_L_KZ_B, /* 13121 */ IC_EVEX_L_XS_KZ_B, /* 13122 */ IC_EVEX_L_XS_KZ_B, /* 13123 */ IC_EVEX_L_XD_KZ_B, /* 13124 */ IC_EVEX_L_XD_KZ_B, /* 13125 */ IC_EVEX_L_XD_KZ_B, /* 13126 */ IC_EVEX_L_XD_KZ_B, /* 13127 */ IC_EVEX_L_W_KZ_B, /* 13128 */ IC_EVEX_L_W_KZ_B, /* 13129 */ IC_EVEX_L_W_XS_KZ_B, /* 13130 */ IC_EVEX_L_W_XS_KZ_B, /* 13131 */ IC_EVEX_L_W_XD_KZ_B, /* 13132 */ IC_EVEX_L_W_XD_KZ_B, /* 13133 */ IC_EVEX_L_W_XD_KZ_B, /* 13134 */ IC_EVEX_L_W_XD_KZ_B, /* 13135 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13136 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13137 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13138 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13139 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13140 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13141 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13142 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13143 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13144 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13145 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13146 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13147 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13148 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13149 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13150 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13151 */ IC_EVEX_L_KZ_B, /* 13152 */ IC_EVEX_L_KZ_B, /* 13153 */ IC_EVEX_L_XS_KZ_B, /* 13154 */ IC_EVEX_L_XS_KZ_B, /* 13155 */ IC_EVEX_L_XD_KZ_B, /* 13156 */ IC_EVEX_L_XD_KZ_B, /* 13157 */ IC_EVEX_L_XD_KZ_B, /* 13158 */ IC_EVEX_L_XD_KZ_B, /* 13159 */ IC_EVEX_L_W_KZ_B, /* 13160 */ IC_EVEX_L_W_KZ_B, /* 13161 */ IC_EVEX_L_W_XS_KZ_B, /* 13162 */ IC_EVEX_L_W_XS_KZ_B, /* 13163 */ IC_EVEX_L_W_XD_KZ_B, /* 13164 */ IC_EVEX_L_W_XD_KZ_B, /* 13165 */ IC_EVEX_L_W_XD_KZ_B, /* 13166 */ IC_EVEX_L_W_XD_KZ_B, /* 13167 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13168 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13169 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13170 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13171 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13172 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13173 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13174 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13175 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13176 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13177 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13178 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13179 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13180 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13181 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13182 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13183 */ IC_EVEX_L_KZ_B, /* 13184 */ IC_EVEX_L_KZ_B, /* 13185 */ IC_EVEX_L_XS_KZ_B, /* 13186 */ IC_EVEX_L_XS_KZ_B, /* 13187 */ IC_EVEX_L_XD_KZ_B, /* 13188 */ IC_EVEX_L_XD_KZ_B, /* 13189 */ IC_EVEX_L_XD_KZ_B, /* 13190 */ IC_EVEX_L_XD_KZ_B, /* 13191 */ IC_EVEX_L_W_KZ_B, /* 13192 */ IC_EVEX_L_W_KZ_B, /* 13193 */ IC_EVEX_L_W_XS_KZ_B, /* 13194 */ IC_EVEX_L_W_XS_KZ_B, /* 13195 */ IC_EVEX_L_W_XD_KZ_B, /* 13196 */ IC_EVEX_L_W_XD_KZ_B, /* 13197 */ IC_EVEX_L_W_XD_KZ_B, /* 13198 */ IC_EVEX_L_W_XD_KZ_B, /* 13199 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13200 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13201 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13202 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13203 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13204 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13205 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13206 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13207 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13208 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13209 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13210 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13211 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13212 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13213 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13214 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13215 */ IC_EVEX_L_KZ_B, /* 13216 */ IC_EVEX_L_KZ_B, /* 13217 */ IC_EVEX_L_XS_KZ_B, /* 13218 */ IC_EVEX_L_XS_KZ_B, /* 13219 */ IC_EVEX_L_XD_KZ_B, /* 13220 */ IC_EVEX_L_XD_KZ_B, /* 13221 */ IC_EVEX_L_XD_KZ_B, /* 13222 */ IC_EVEX_L_XD_KZ_B, /* 13223 */ IC_EVEX_L_W_KZ_B, /* 13224 */ IC_EVEX_L_W_KZ_B, /* 13225 */ IC_EVEX_L_W_XS_KZ_B, /* 13226 */ IC_EVEX_L_W_XS_KZ_B, /* 13227 */ IC_EVEX_L_W_XD_KZ_B, /* 13228 */ IC_EVEX_L_W_XD_KZ_B, /* 13229 */ IC_EVEX_L_W_XD_KZ_B, /* 13230 */ IC_EVEX_L_W_XD_KZ_B, /* 13231 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13232 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13233 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13234 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13235 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13236 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13237 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13238 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13239 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13240 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13241 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13242 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13243 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13244 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13245 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13246 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13247 */ IC_EVEX_L_KZ_B, /* 13248 */ IC_EVEX_L_KZ_B, /* 13249 */ IC_EVEX_L_XS_KZ_B, /* 13250 */ IC_EVEX_L_XS_KZ_B, /* 13251 */ IC_EVEX_L_XD_KZ_B, /* 13252 */ IC_EVEX_L_XD_KZ_B, /* 13253 */ IC_EVEX_L_XD_KZ_B, /* 13254 */ IC_EVEX_L_XD_KZ_B, /* 13255 */ IC_EVEX_L_W_KZ_B, /* 13256 */ IC_EVEX_L_W_KZ_B, /* 13257 */ IC_EVEX_L_W_XS_KZ_B, /* 13258 */ IC_EVEX_L_W_XS_KZ_B, /* 13259 */ IC_EVEX_L_W_XD_KZ_B, /* 13260 */ IC_EVEX_L_W_XD_KZ_B, /* 13261 */ IC_EVEX_L_W_XD_KZ_B, /* 13262 */ IC_EVEX_L_W_XD_KZ_B, /* 13263 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13264 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13265 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13266 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13267 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13268 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13269 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13270 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13271 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13272 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13273 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13274 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13275 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13276 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13277 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13278 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13279 */ IC_EVEX_L_KZ_B, /* 13280 */ IC_EVEX_L_KZ_B, /* 13281 */ IC_EVEX_L_XS_KZ_B, /* 13282 */ IC_EVEX_L_XS_KZ_B, /* 13283 */ IC_EVEX_L_XD_KZ_B, /* 13284 */ IC_EVEX_L_XD_KZ_B, /* 13285 */ IC_EVEX_L_XD_KZ_B, /* 13286 */ IC_EVEX_L_XD_KZ_B, /* 13287 */ IC_EVEX_L_W_KZ_B, /* 13288 */ IC_EVEX_L_W_KZ_B, /* 13289 */ IC_EVEX_L_W_XS_KZ_B, /* 13290 */ IC_EVEX_L_W_XS_KZ_B, /* 13291 */ IC_EVEX_L_W_XD_KZ_B, /* 13292 */ IC_EVEX_L_W_XD_KZ_B, /* 13293 */ IC_EVEX_L_W_XD_KZ_B, /* 13294 */ IC_EVEX_L_W_XD_KZ_B, /* 13295 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13296 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13297 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13298 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13299 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13300 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13301 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13302 */ IC_EVEX_L_OPSIZE_KZ_B, /* 13303 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13304 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13305 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13306 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13307 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13308 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13309 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13310 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13311 */ IC, /* 13312 */ IC_64BIT, /* 13313 */ IC_XS, /* 13314 */ IC_64BIT_XS, /* 13315 */ IC_XD, /* 13316 */ IC_64BIT_XD, /* 13317 */ IC_XS, /* 13318 */ IC_64BIT_XS, /* 13319 */ IC, /* 13320 */ IC_64BIT_REXW, /* 13321 */ IC_XS, /* 13322 */ IC_64BIT_REXW_XS, /* 13323 */ IC_XD, /* 13324 */ IC_64BIT_REXW_XD, /* 13325 */ IC_XS, /* 13326 */ IC_64BIT_REXW_XS, /* 13327 */ IC_OPSIZE, /* 13328 */ IC_64BIT_OPSIZE, /* 13329 */ IC_XS_OPSIZE, /* 13330 */ IC_64BIT_XS_OPSIZE, /* 13331 */ IC_XD_OPSIZE, /* 13332 */ IC_64BIT_XD_OPSIZE, /* 13333 */ IC_XS_OPSIZE, /* 13334 */ IC_64BIT_XD_OPSIZE, /* 13335 */ IC_OPSIZE, /* 13336 */ IC_64BIT_REXW_OPSIZE, /* 13337 */ IC_XS_OPSIZE, /* 13338 */ IC_64BIT_REXW_XS, /* 13339 */ IC_XD_OPSIZE, /* 13340 */ IC_64BIT_REXW_XD, /* 13341 */ IC_XS_OPSIZE, /* 13342 */ IC_64BIT_REXW_XS, /* 13343 */ IC_ADSIZE, /* 13344 */ IC_64BIT_ADSIZE, /* 13345 */ IC_XS_ADSIZE, /* 13346 */ IC_64BIT_XS_ADSIZE, /* 13347 */ IC_XD_ADSIZE, /* 13348 */ IC_64BIT_XD_ADSIZE, /* 13349 */ IC_XS_ADSIZE, /* 13350 */ IC_64BIT_XD_ADSIZE, /* 13351 */ IC_ADSIZE, /* 13352 */ IC_64BIT_REXW_ADSIZE, /* 13353 */ IC_XS_ADSIZE, /* 13354 */ IC_64BIT_REXW_XS, /* 13355 */ IC_XD_ADSIZE, /* 13356 */ IC_64BIT_REXW_XD, /* 13357 */ IC_XS_ADSIZE, /* 13358 */ IC_64BIT_REXW_XS, /* 13359 */ IC_OPSIZE_ADSIZE, /* 13360 */ IC_64BIT_OPSIZE_ADSIZE, /* 13361 */ IC_XS_OPSIZE, /* 13362 */ IC_64BIT_XS_OPSIZE, /* 13363 */ IC_XD_OPSIZE, /* 13364 */ IC_64BIT_XD_OPSIZE, /* 13365 */ IC_XS_OPSIZE, /* 13366 */ IC_64BIT_XD_OPSIZE, /* 13367 */ IC_OPSIZE_ADSIZE, /* 13368 */ IC_64BIT_REXW_OPSIZE, /* 13369 */ IC_XS_OPSIZE, /* 13370 */ IC_64BIT_REXW_XS, /* 13371 */ IC_XD_OPSIZE, /* 13372 */ IC_64BIT_REXW_XD, /* 13373 */ IC_XS_OPSIZE, /* 13374 */ IC_64BIT_REXW_XS, /* 13375 */ IC_VEX, /* 13376 */ IC_VEX, /* 13377 */ IC_VEX_XS, /* 13378 */ IC_VEX_XS, /* 13379 */ IC_VEX_XD, /* 13380 */ IC_VEX_XD, /* 13381 */ IC_VEX_XD, /* 13382 */ IC_VEX_XD, /* 13383 */ IC_VEX_W, /* 13384 */ IC_VEX_W, /* 13385 */ IC_VEX_W_XS, /* 13386 */ IC_VEX_W_XS, /* 13387 */ IC_VEX_W_XD, /* 13388 */ IC_VEX_W_XD, /* 13389 */ IC_VEX_W_XD, /* 13390 */ IC_VEX_W_XD, /* 13391 */ IC_VEX_OPSIZE, /* 13392 */ IC_VEX_OPSIZE, /* 13393 */ IC_VEX_OPSIZE, /* 13394 */ IC_VEX_OPSIZE, /* 13395 */ IC_VEX_OPSIZE, /* 13396 */ IC_VEX_OPSIZE, /* 13397 */ IC_VEX_OPSIZE, /* 13398 */ IC_VEX_OPSIZE, /* 13399 */ IC_VEX_W_OPSIZE, /* 13400 */ IC_VEX_W_OPSIZE, /* 13401 */ IC_VEX_W_OPSIZE, /* 13402 */ IC_VEX_W_OPSIZE, /* 13403 */ IC_VEX_W_OPSIZE, /* 13404 */ IC_VEX_W_OPSIZE, /* 13405 */ IC_VEX_W_OPSIZE, /* 13406 */ IC_VEX_W_OPSIZE, /* 13407 */ IC_VEX, /* 13408 */ IC_VEX, /* 13409 */ IC_VEX_XS, /* 13410 */ IC_VEX_XS, /* 13411 */ IC_VEX_XD, /* 13412 */ IC_VEX_XD, /* 13413 */ IC_VEX_XD, /* 13414 */ IC_VEX_XD, /* 13415 */ IC_VEX_W, /* 13416 */ IC_VEX_W, /* 13417 */ IC_VEX_W_XS, /* 13418 */ IC_VEX_W_XS, /* 13419 */ IC_VEX_W_XD, /* 13420 */ IC_VEX_W_XD, /* 13421 */ IC_VEX_W_XD, /* 13422 */ IC_VEX_W_XD, /* 13423 */ IC_VEX_OPSIZE, /* 13424 */ IC_VEX_OPSIZE, /* 13425 */ IC_VEX_OPSIZE, /* 13426 */ IC_VEX_OPSIZE, /* 13427 */ IC_VEX_OPSIZE, /* 13428 */ IC_VEX_OPSIZE, /* 13429 */ IC_VEX_OPSIZE, /* 13430 */ IC_VEX_OPSIZE, /* 13431 */ IC_VEX_W_OPSIZE, /* 13432 */ IC_VEX_W_OPSIZE, /* 13433 */ IC_VEX_W_OPSIZE, /* 13434 */ IC_VEX_W_OPSIZE, /* 13435 */ IC_VEX_W_OPSIZE, /* 13436 */ IC_VEX_W_OPSIZE, /* 13437 */ IC_VEX_W_OPSIZE, /* 13438 */ IC_VEX_W_OPSIZE, /* 13439 */ IC_VEX_L, /* 13440 */ IC_VEX_L, /* 13441 */ IC_VEX_L_XS, /* 13442 */ IC_VEX_L_XS, /* 13443 */ IC_VEX_L_XD, /* 13444 */ IC_VEX_L_XD, /* 13445 */ IC_VEX_L_XD, /* 13446 */ IC_VEX_L_XD, /* 13447 */ IC_VEX_L_W, /* 13448 */ IC_VEX_L_W, /* 13449 */ IC_VEX_L_W_XS, /* 13450 */ IC_VEX_L_W_XS, /* 13451 */ IC_VEX_L_W_XD, /* 13452 */ IC_VEX_L_W_XD, /* 13453 */ IC_VEX_L_W_XD, /* 13454 */ IC_VEX_L_W_XD, /* 13455 */ IC_VEX_L_OPSIZE, /* 13456 */ IC_VEX_L_OPSIZE, /* 13457 */ IC_VEX_L_OPSIZE, /* 13458 */ IC_VEX_L_OPSIZE, /* 13459 */ IC_VEX_L_OPSIZE, /* 13460 */ IC_VEX_L_OPSIZE, /* 13461 */ IC_VEX_L_OPSIZE, /* 13462 */ IC_VEX_L_OPSIZE, /* 13463 */ IC_VEX_L_W_OPSIZE, /* 13464 */ IC_VEX_L_W_OPSIZE, /* 13465 */ IC_VEX_L_W_OPSIZE, /* 13466 */ IC_VEX_L_W_OPSIZE, /* 13467 */ IC_VEX_L_W_OPSIZE, /* 13468 */ IC_VEX_L_W_OPSIZE, /* 13469 */ IC_VEX_L_W_OPSIZE, /* 13470 */ IC_VEX_L_W_OPSIZE, /* 13471 */ IC_VEX_L, /* 13472 */ IC_VEX_L, /* 13473 */ IC_VEX_L_XS, /* 13474 */ IC_VEX_L_XS, /* 13475 */ IC_VEX_L_XD, /* 13476 */ IC_VEX_L_XD, /* 13477 */ IC_VEX_L_XD, /* 13478 */ IC_VEX_L_XD, /* 13479 */ IC_VEX_L_W, /* 13480 */ IC_VEX_L_W, /* 13481 */ IC_VEX_L_W_XS, /* 13482 */ IC_VEX_L_W_XS, /* 13483 */ IC_VEX_L_W_XD, /* 13484 */ IC_VEX_L_W_XD, /* 13485 */ IC_VEX_L_W_XD, /* 13486 */ IC_VEX_L_W_XD, /* 13487 */ IC_VEX_L_OPSIZE, /* 13488 */ IC_VEX_L_OPSIZE, /* 13489 */ IC_VEX_L_OPSIZE, /* 13490 */ IC_VEX_L_OPSIZE, /* 13491 */ IC_VEX_L_OPSIZE, /* 13492 */ IC_VEX_L_OPSIZE, /* 13493 */ IC_VEX_L_OPSIZE, /* 13494 */ IC_VEX_L_OPSIZE, /* 13495 */ IC_VEX_L_W_OPSIZE, /* 13496 */ IC_VEX_L_W_OPSIZE, /* 13497 */ IC_VEX_L_W_OPSIZE, /* 13498 */ IC_VEX_L_W_OPSIZE, /* 13499 */ IC_VEX_L_W_OPSIZE, /* 13500 */ IC_VEX_L_W_OPSIZE, /* 13501 */ IC_VEX_L_W_OPSIZE, /* 13502 */ IC_VEX_L_W_OPSIZE, /* 13503 */ IC_VEX_L, /* 13504 */ IC_VEX_L, /* 13505 */ IC_VEX_L_XS, /* 13506 */ IC_VEX_L_XS, /* 13507 */ IC_VEX_L_XD, /* 13508 */ IC_VEX_L_XD, /* 13509 */ IC_VEX_L_XD, /* 13510 */ IC_VEX_L_XD, /* 13511 */ IC_VEX_L_W, /* 13512 */ IC_VEX_L_W, /* 13513 */ IC_VEX_L_W_XS, /* 13514 */ IC_VEX_L_W_XS, /* 13515 */ IC_VEX_L_W_XD, /* 13516 */ IC_VEX_L_W_XD, /* 13517 */ IC_VEX_L_W_XD, /* 13518 */ IC_VEX_L_W_XD, /* 13519 */ IC_VEX_L_OPSIZE, /* 13520 */ IC_VEX_L_OPSIZE, /* 13521 */ IC_VEX_L_OPSIZE, /* 13522 */ IC_VEX_L_OPSIZE, /* 13523 */ IC_VEX_L_OPSIZE, /* 13524 */ IC_VEX_L_OPSIZE, /* 13525 */ IC_VEX_L_OPSIZE, /* 13526 */ IC_VEX_L_OPSIZE, /* 13527 */ IC_VEX_L_W_OPSIZE, /* 13528 */ IC_VEX_L_W_OPSIZE, /* 13529 */ IC_VEX_L_W_OPSIZE, /* 13530 */ IC_VEX_L_W_OPSIZE, /* 13531 */ IC_VEX_L_W_OPSIZE, /* 13532 */ IC_VEX_L_W_OPSIZE, /* 13533 */ IC_VEX_L_W_OPSIZE, /* 13534 */ IC_VEX_L_W_OPSIZE, /* 13535 */ IC_VEX_L, /* 13536 */ IC_VEX_L, /* 13537 */ IC_VEX_L_XS, /* 13538 */ IC_VEX_L_XS, /* 13539 */ IC_VEX_L_XD, /* 13540 */ IC_VEX_L_XD, /* 13541 */ IC_VEX_L_XD, /* 13542 */ IC_VEX_L_XD, /* 13543 */ IC_VEX_L_W, /* 13544 */ IC_VEX_L_W, /* 13545 */ IC_VEX_L_W_XS, /* 13546 */ IC_VEX_L_W_XS, /* 13547 */ IC_VEX_L_W_XD, /* 13548 */ IC_VEX_L_W_XD, /* 13549 */ IC_VEX_L_W_XD, /* 13550 */ IC_VEX_L_W_XD, /* 13551 */ IC_VEX_L_OPSIZE, /* 13552 */ IC_VEX_L_OPSIZE, /* 13553 */ IC_VEX_L_OPSIZE, /* 13554 */ IC_VEX_L_OPSIZE, /* 13555 */ IC_VEX_L_OPSIZE, /* 13556 */ IC_VEX_L_OPSIZE, /* 13557 */ IC_VEX_L_OPSIZE, /* 13558 */ IC_VEX_L_OPSIZE, /* 13559 */ IC_VEX_L_W_OPSIZE, /* 13560 */ IC_VEX_L_W_OPSIZE, /* 13561 */ IC_VEX_L_W_OPSIZE, /* 13562 */ IC_VEX_L_W_OPSIZE, /* 13563 */ IC_VEX_L_W_OPSIZE, /* 13564 */ IC_VEX_L_W_OPSIZE, /* 13565 */ IC_VEX_L_W_OPSIZE, /* 13566 */ IC_VEX_L_W_OPSIZE, /* 13567 */ IC_EVEX_L2_KZ_B, /* 13568 */ IC_EVEX_L2_KZ_B, /* 13569 */ IC_EVEX_L2_XS_KZ_B, /* 13570 */ IC_EVEX_L2_XS_KZ_B, /* 13571 */ IC_EVEX_L2_XD_KZ_B, /* 13572 */ IC_EVEX_L2_XD_KZ_B, /* 13573 */ IC_EVEX_L2_XD_KZ_B, /* 13574 */ IC_EVEX_L2_XD_KZ_B, /* 13575 */ IC_EVEX_L2_W_KZ_B, /* 13576 */ IC_EVEX_L2_W_KZ_B, /* 13577 */ IC_EVEX_L2_W_XS_KZ_B, /* 13578 */ IC_EVEX_L2_W_XS_KZ_B, /* 13579 */ IC_EVEX_L2_W_XD_KZ_B, /* 13580 */ IC_EVEX_L2_W_XD_KZ_B, /* 13581 */ IC_EVEX_L2_W_XD_KZ_B, /* 13582 */ IC_EVEX_L2_W_XD_KZ_B, /* 13583 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13584 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13585 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13586 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13587 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13588 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13589 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13590 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13591 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13592 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13593 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13594 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13595 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13596 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13597 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13598 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13599 */ IC_EVEX_L2_KZ_B, /* 13600 */ IC_EVEX_L2_KZ_B, /* 13601 */ IC_EVEX_L2_XS_KZ_B, /* 13602 */ IC_EVEX_L2_XS_KZ_B, /* 13603 */ IC_EVEX_L2_XD_KZ_B, /* 13604 */ IC_EVEX_L2_XD_KZ_B, /* 13605 */ IC_EVEX_L2_XD_KZ_B, /* 13606 */ IC_EVEX_L2_XD_KZ_B, /* 13607 */ IC_EVEX_L2_W_KZ_B, /* 13608 */ IC_EVEX_L2_W_KZ_B, /* 13609 */ IC_EVEX_L2_W_XS_KZ_B, /* 13610 */ IC_EVEX_L2_W_XS_KZ_B, /* 13611 */ IC_EVEX_L2_W_XD_KZ_B, /* 13612 */ IC_EVEX_L2_W_XD_KZ_B, /* 13613 */ IC_EVEX_L2_W_XD_KZ_B, /* 13614 */ IC_EVEX_L2_W_XD_KZ_B, /* 13615 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13616 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13617 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13618 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13619 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13620 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13621 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13622 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13623 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13624 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13625 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13626 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13627 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13628 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13629 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13630 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13631 */ IC_EVEX_L2_KZ_B, /* 13632 */ IC_EVEX_L2_KZ_B, /* 13633 */ IC_EVEX_L2_XS_KZ_B, /* 13634 */ IC_EVEX_L2_XS_KZ_B, /* 13635 */ IC_EVEX_L2_XD_KZ_B, /* 13636 */ IC_EVEX_L2_XD_KZ_B, /* 13637 */ IC_EVEX_L2_XD_KZ_B, /* 13638 */ IC_EVEX_L2_XD_KZ_B, /* 13639 */ IC_EVEX_L2_W_KZ_B, /* 13640 */ IC_EVEX_L2_W_KZ_B, /* 13641 */ IC_EVEX_L2_W_XS_KZ_B, /* 13642 */ IC_EVEX_L2_W_XS_KZ_B, /* 13643 */ IC_EVEX_L2_W_XD_KZ_B, /* 13644 */ IC_EVEX_L2_W_XD_KZ_B, /* 13645 */ IC_EVEX_L2_W_XD_KZ_B, /* 13646 */ IC_EVEX_L2_W_XD_KZ_B, /* 13647 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13648 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13649 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13650 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13651 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13652 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13653 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13654 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13655 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13656 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13657 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13658 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13659 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13660 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13661 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13662 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13663 */ IC_EVEX_L2_KZ_B, /* 13664 */ IC_EVEX_L2_KZ_B, /* 13665 */ IC_EVEX_L2_XS_KZ_B, /* 13666 */ IC_EVEX_L2_XS_KZ_B, /* 13667 */ IC_EVEX_L2_XD_KZ_B, /* 13668 */ IC_EVEX_L2_XD_KZ_B, /* 13669 */ IC_EVEX_L2_XD_KZ_B, /* 13670 */ IC_EVEX_L2_XD_KZ_B, /* 13671 */ IC_EVEX_L2_W_KZ_B, /* 13672 */ IC_EVEX_L2_W_KZ_B, /* 13673 */ IC_EVEX_L2_W_XS_KZ_B, /* 13674 */ IC_EVEX_L2_W_XS_KZ_B, /* 13675 */ IC_EVEX_L2_W_XD_KZ_B, /* 13676 */ IC_EVEX_L2_W_XD_KZ_B, /* 13677 */ IC_EVEX_L2_W_XD_KZ_B, /* 13678 */ IC_EVEX_L2_W_XD_KZ_B, /* 13679 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13680 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13681 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13682 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13683 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13684 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13685 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13686 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13687 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13688 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13689 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13690 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13691 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13692 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13693 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13694 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13695 */ IC_EVEX_L2_KZ_B, /* 13696 */ IC_EVEX_L2_KZ_B, /* 13697 */ IC_EVEX_L2_XS_KZ_B, /* 13698 */ IC_EVEX_L2_XS_KZ_B, /* 13699 */ IC_EVEX_L2_XD_KZ_B, /* 13700 */ IC_EVEX_L2_XD_KZ_B, /* 13701 */ IC_EVEX_L2_XD_KZ_B, /* 13702 */ IC_EVEX_L2_XD_KZ_B, /* 13703 */ IC_EVEX_L2_W_KZ_B, /* 13704 */ IC_EVEX_L2_W_KZ_B, /* 13705 */ IC_EVEX_L2_W_XS_KZ_B, /* 13706 */ IC_EVEX_L2_W_XS_KZ_B, /* 13707 */ IC_EVEX_L2_W_XD_KZ_B, /* 13708 */ IC_EVEX_L2_W_XD_KZ_B, /* 13709 */ IC_EVEX_L2_W_XD_KZ_B, /* 13710 */ IC_EVEX_L2_W_XD_KZ_B, /* 13711 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13712 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13713 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13714 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13715 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13716 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13717 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13718 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13719 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13720 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13721 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13722 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13723 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13724 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13725 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13726 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13727 */ IC_EVEX_L2_KZ_B, /* 13728 */ IC_EVEX_L2_KZ_B, /* 13729 */ IC_EVEX_L2_XS_KZ_B, /* 13730 */ IC_EVEX_L2_XS_KZ_B, /* 13731 */ IC_EVEX_L2_XD_KZ_B, /* 13732 */ IC_EVEX_L2_XD_KZ_B, /* 13733 */ IC_EVEX_L2_XD_KZ_B, /* 13734 */ IC_EVEX_L2_XD_KZ_B, /* 13735 */ IC_EVEX_L2_W_KZ_B, /* 13736 */ IC_EVEX_L2_W_KZ_B, /* 13737 */ IC_EVEX_L2_W_XS_KZ_B, /* 13738 */ IC_EVEX_L2_W_XS_KZ_B, /* 13739 */ IC_EVEX_L2_W_XD_KZ_B, /* 13740 */ IC_EVEX_L2_W_XD_KZ_B, /* 13741 */ IC_EVEX_L2_W_XD_KZ_B, /* 13742 */ IC_EVEX_L2_W_XD_KZ_B, /* 13743 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13744 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13745 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13746 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13747 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13748 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13749 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13750 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13751 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13752 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13753 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13754 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13755 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13756 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13757 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13758 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13759 */ IC_EVEX_L2_KZ_B, /* 13760 */ IC_EVEX_L2_KZ_B, /* 13761 */ IC_EVEX_L2_XS_KZ_B, /* 13762 */ IC_EVEX_L2_XS_KZ_B, /* 13763 */ IC_EVEX_L2_XD_KZ_B, /* 13764 */ IC_EVEX_L2_XD_KZ_B, /* 13765 */ IC_EVEX_L2_XD_KZ_B, /* 13766 */ IC_EVEX_L2_XD_KZ_B, /* 13767 */ IC_EVEX_L2_W_KZ_B, /* 13768 */ IC_EVEX_L2_W_KZ_B, /* 13769 */ IC_EVEX_L2_W_XS_KZ_B, /* 13770 */ IC_EVEX_L2_W_XS_KZ_B, /* 13771 */ IC_EVEX_L2_W_XD_KZ_B, /* 13772 */ IC_EVEX_L2_W_XD_KZ_B, /* 13773 */ IC_EVEX_L2_W_XD_KZ_B, /* 13774 */ IC_EVEX_L2_W_XD_KZ_B, /* 13775 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13776 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13777 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13778 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13779 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13780 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13781 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13782 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13783 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13784 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13785 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13786 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13787 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13788 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13789 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13790 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13791 */ IC_EVEX_L2_KZ_B, /* 13792 */ IC_EVEX_L2_KZ_B, /* 13793 */ IC_EVEX_L2_XS_KZ_B, /* 13794 */ IC_EVEX_L2_XS_KZ_B, /* 13795 */ IC_EVEX_L2_XD_KZ_B, /* 13796 */ IC_EVEX_L2_XD_KZ_B, /* 13797 */ IC_EVEX_L2_XD_KZ_B, /* 13798 */ IC_EVEX_L2_XD_KZ_B, /* 13799 */ IC_EVEX_L2_W_KZ_B, /* 13800 */ IC_EVEX_L2_W_KZ_B, /* 13801 */ IC_EVEX_L2_W_XS_KZ_B, /* 13802 */ IC_EVEX_L2_W_XS_KZ_B, /* 13803 */ IC_EVEX_L2_W_XD_KZ_B, /* 13804 */ IC_EVEX_L2_W_XD_KZ_B, /* 13805 */ IC_EVEX_L2_W_XD_KZ_B, /* 13806 */ IC_EVEX_L2_W_XD_KZ_B, /* 13807 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13808 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13809 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13810 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13811 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13812 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13813 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13814 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 13815 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13816 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13817 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13818 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13819 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13820 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13821 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13822 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13823 */ IC, /* 13824 */ IC_64BIT, /* 13825 */ IC_XS, /* 13826 */ IC_64BIT_XS, /* 13827 */ IC_XD, /* 13828 */ IC_64BIT_XD, /* 13829 */ IC_XS, /* 13830 */ IC_64BIT_XS, /* 13831 */ IC, /* 13832 */ IC_64BIT_REXW, /* 13833 */ IC_XS, /* 13834 */ IC_64BIT_REXW_XS, /* 13835 */ IC_XD, /* 13836 */ IC_64BIT_REXW_XD, /* 13837 */ IC_XS, /* 13838 */ IC_64BIT_REXW_XS, /* 13839 */ IC_OPSIZE, /* 13840 */ IC_64BIT_OPSIZE, /* 13841 */ IC_XS_OPSIZE, /* 13842 */ IC_64BIT_XS_OPSIZE, /* 13843 */ IC_XD_OPSIZE, /* 13844 */ IC_64BIT_XD_OPSIZE, /* 13845 */ IC_XS_OPSIZE, /* 13846 */ IC_64BIT_XD_OPSIZE, /* 13847 */ IC_OPSIZE, /* 13848 */ IC_64BIT_REXW_OPSIZE, /* 13849 */ IC_XS_OPSIZE, /* 13850 */ IC_64BIT_REXW_XS, /* 13851 */ IC_XD_OPSIZE, /* 13852 */ IC_64BIT_REXW_XD, /* 13853 */ IC_XS_OPSIZE, /* 13854 */ IC_64BIT_REXW_XS, /* 13855 */ IC_ADSIZE, /* 13856 */ IC_64BIT_ADSIZE, /* 13857 */ IC_XS_ADSIZE, /* 13858 */ IC_64BIT_XS_ADSIZE, /* 13859 */ IC_XD_ADSIZE, /* 13860 */ IC_64BIT_XD_ADSIZE, /* 13861 */ IC_XS_ADSIZE, /* 13862 */ IC_64BIT_XD_ADSIZE, /* 13863 */ IC_ADSIZE, /* 13864 */ IC_64BIT_REXW_ADSIZE, /* 13865 */ IC_XS_ADSIZE, /* 13866 */ IC_64BIT_REXW_XS, /* 13867 */ IC_XD_ADSIZE, /* 13868 */ IC_64BIT_REXW_XD, /* 13869 */ IC_XS_ADSIZE, /* 13870 */ IC_64BIT_REXW_XS, /* 13871 */ IC_OPSIZE_ADSIZE, /* 13872 */ IC_64BIT_OPSIZE_ADSIZE, /* 13873 */ IC_XS_OPSIZE, /* 13874 */ IC_64BIT_XS_OPSIZE, /* 13875 */ IC_XD_OPSIZE, /* 13876 */ IC_64BIT_XD_OPSIZE, /* 13877 */ IC_XS_OPSIZE, /* 13878 */ IC_64BIT_XD_OPSIZE, /* 13879 */ IC_OPSIZE_ADSIZE, /* 13880 */ IC_64BIT_REXW_OPSIZE, /* 13881 */ IC_XS_OPSIZE, /* 13882 */ IC_64BIT_REXW_XS, /* 13883 */ IC_XD_OPSIZE, /* 13884 */ IC_64BIT_REXW_XD, /* 13885 */ IC_XS_OPSIZE, /* 13886 */ IC_64BIT_REXW_XS, /* 13887 */ IC_VEX, /* 13888 */ IC_VEX, /* 13889 */ IC_VEX_XS, /* 13890 */ IC_VEX_XS, /* 13891 */ IC_VEX_XD, /* 13892 */ IC_VEX_XD, /* 13893 */ IC_VEX_XD, /* 13894 */ IC_VEX_XD, /* 13895 */ IC_VEX_W, /* 13896 */ IC_VEX_W, /* 13897 */ IC_VEX_W_XS, /* 13898 */ IC_VEX_W_XS, /* 13899 */ IC_VEX_W_XD, /* 13900 */ IC_VEX_W_XD, /* 13901 */ IC_VEX_W_XD, /* 13902 */ IC_VEX_W_XD, /* 13903 */ IC_VEX_OPSIZE, /* 13904 */ IC_VEX_OPSIZE, /* 13905 */ IC_VEX_OPSIZE, /* 13906 */ IC_VEX_OPSIZE, /* 13907 */ IC_VEX_OPSIZE, /* 13908 */ IC_VEX_OPSIZE, /* 13909 */ IC_VEX_OPSIZE, /* 13910 */ IC_VEX_OPSIZE, /* 13911 */ IC_VEX_W_OPSIZE, /* 13912 */ IC_VEX_W_OPSIZE, /* 13913 */ IC_VEX_W_OPSIZE, /* 13914 */ IC_VEX_W_OPSIZE, /* 13915 */ IC_VEX_W_OPSIZE, /* 13916 */ IC_VEX_W_OPSIZE, /* 13917 */ IC_VEX_W_OPSIZE, /* 13918 */ IC_VEX_W_OPSIZE, /* 13919 */ IC_VEX, /* 13920 */ IC_VEX, /* 13921 */ IC_VEX_XS, /* 13922 */ IC_VEX_XS, /* 13923 */ IC_VEX_XD, /* 13924 */ IC_VEX_XD, /* 13925 */ IC_VEX_XD, /* 13926 */ IC_VEX_XD, /* 13927 */ IC_VEX_W, /* 13928 */ IC_VEX_W, /* 13929 */ IC_VEX_W_XS, /* 13930 */ IC_VEX_W_XS, /* 13931 */ IC_VEX_W_XD, /* 13932 */ IC_VEX_W_XD, /* 13933 */ IC_VEX_W_XD, /* 13934 */ IC_VEX_W_XD, /* 13935 */ IC_VEX_OPSIZE, /* 13936 */ IC_VEX_OPSIZE, /* 13937 */ IC_VEX_OPSIZE, /* 13938 */ IC_VEX_OPSIZE, /* 13939 */ IC_VEX_OPSIZE, /* 13940 */ IC_VEX_OPSIZE, /* 13941 */ IC_VEX_OPSIZE, /* 13942 */ IC_VEX_OPSIZE, /* 13943 */ IC_VEX_W_OPSIZE, /* 13944 */ IC_VEX_W_OPSIZE, /* 13945 */ IC_VEX_W_OPSIZE, /* 13946 */ IC_VEX_W_OPSIZE, /* 13947 */ IC_VEX_W_OPSIZE, /* 13948 */ IC_VEX_W_OPSIZE, /* 13949 */ IC_VEX_W_OPSIZE, /* 13950 */ IC_VEX_W_OPSIZE, /* 13951 */ IC_VEX_L, /* 13952 */ IC_VEX_L, /* 13953 */ IC_VEX_L_XS, /* 13954 */ IC_VEX_L_XS, /* 13955 */ IC_VEX_L_XD, /* 13956 */ IC_VEX_L_XD, /* 13957 */ IC_VEX_L_XD, /* 13958 */ IC_VEX_L_XD, /* 13959 */ IC_VEX_L_W, /* 13960 */ IC_VEX_L_W, /* 13961 */ IC_VEX_L_W_XS, /* 13962 */ IC_VEX_L_W_XS, /* 13963 */ IC_VEX_L_W_XD, /* 13964 */ IC_VEX_L_W_XD, /* 13965 */ IC_VEX_L_W_XD, /* 13966 */ IC_VEX_L_W_XD, /* 13967 */ IC_VEX_L_OPSIZE, /* 13968 */ IC_VEX_L_OPSIZE, /* 13969 */ IC_VEX_L_OPSIZE, /* 13970 */ IC_VEX_L_OPSIZE, /* 13971 */ IC_VEX_L_OPSIZE, /* 13972 */ IC_VEX_L_OPSIZE, /* 13973 */ IC_VEX_L_OPSIZE, /* 13974 */ IC_VEX_L_OPSIZE, /* 13975 */ IC_VEX_L_W_OPSIZE, /* 13976 */ IC_VEX_L_W_OPSIZE, /* 13977 */ IC_VEX_L_W_OPSIZE, /* 13978 */ IC_VEX_L_W_OPSIZE, /* 13979 */ IC_VEX_L_W_OPSIZE, /* 13980 */ IC_VEX_L_W_OPSIZE, /* 13981 */ IC_VEX_L_W_OPSIZE, /* 13982 */ IC_VEX_L_W_OPSIZE, /* 13983 */ IC_VEX_L, /* 13984 */ IC_VEX_L, /* 13985 */ IC_VEX_L_XS, /* 13986 */ IC_VEX_L_XS, /* 13987 */ IC_VEX_L_XD, /* 13988 */ IC_VEX_L_XD, /* 13989 */ IC_VEX_L_XD, /* 13990 */ IC_VEX_L_XD, /* 13991 */ IC_VEX_L_W, /* 13992 */ IC_VEX_L_W, /* 13993 */ IC_VEX_L_W_XS, /* 13994 */ IC_VEX_L_W_XS, /* 13995 */ IC_VEX_L_W_XD, /* 13996 */ IC_VEX_L_W_XD, /* 13997 */ IC_VEX_L_W_XD, /* 13998 */ IC_VEX_L_W_XD, /* 13999 */ IC_VEX_L_OPSIZE, /* 14000 */ IC_VEX_L_OPSIZE, /* 14001 */ IC_VEX_L_OPSIZE, /* 14002 */ IC_VEX_L_OPSIZE, /* 14003 */ IC_VEX_L_OPSIZE, /* 14004 */ IC_VEX_L_OPSIZE, /* 14005 */ IC_VEX_L_OPSIZE, /* 14006 */ IC_VEX_L_OPSIZE, /* 14007 */ IC_VEX_L_W_OPSIZE, /* 14008 */ IC_VEX_L_W_OPSIZE, /* 14009 */ IC_VEX_L_W_OPSIZE, /* 14010 */ IC_VEX_L_W_OPSIZE, /* 14011 */ IC_VEX_L_W_OPSIZE, /* 14012 */ IC_VEX_L_W_OPSIZE, /* 14013 */ IC_VEX_L_W_OPSIZE, /* 14014 */ IC_VEX_L_W_OPSIZE, /* 14015 */ IC_VEX_L, /* 14016 */ IC_VEX_L, /* 14017 */ IC_VEX_L_XS, /* 14018 */ IC_VEX_L_XS, /* 14019 */ IC_VEX_L_XD, /* 14020 */ IC_VEX_L_XD, /* 14021 */ IC_VEX_L_XD, /* 14022 */ IC_VEX_L_XD, /* 14023 */ IC_VEX_L_W, /* 14024 */ IC_VEX_L_W, /* 14025 */ IC_VEX_L_W_XS, /* 14026 */ IC_VEX_L_W_XS, /* 14027 */ IC_VEX_L_W_XD, /* 14028 */ IC_VEX_L_W_XD, /* 14029 */ IC_VEX_L_W_XD, /* 14030 */ IC_VEX_L_W_XD, /* 14031 */ IC_VEX_L_OPSIZE, /* 14032 */ IC_VEX_L_OPSIZE, /* 14033 */ IC_VEX_L_OPSIZE, /* 14034 */ IC_VEX_L_OPSIZE, /* 14035 */ IC_VEX_L_OPSIZE, /* 14036 */ IC_VEX_L_OPSIZE, /* 14037 */ IC_VEX_L_OPSIZE, /* 14038 */ IC_VEX_L_OPSIZE, /* 14039 */ IC_VEX_L_W_OPSIZE, /* 14040 */ IC_VEX_L_W_OPSIZE, /* 14041 */ IC_VEX_L_W_OPSIZE, /* 14042 */ IC_VEX_L_W_OPSIZE, /* 14043 */ IC_VEX_L_W_OPSIZE, /* 14044 */ IC_VEX_L_W_OPSIZE, /* 14045 */ IC_VEX_L_W_OPSIZE, /* 14046 */ IC_VEX_L_W_OPSIZE, /* 14047 */ IC_VEX_L, /* 14048 */ IC_VEX_L, /* 14049 */ IC_VEX_L_XS, /* 14050 */ IC_VEX_L_XS, /* 14051 */ IC_VEX_L_XD, /* 14052 */ IC_VEX_L_XD, /* 14053 */ IC_VEX_L_XD, /* 14054 */ IC_VEX_L_XD, /* 14055 */ IC_VEX_L_W, /* 14056 */ IC_VEX_L_W, /* 14057 */ IC_VEX_L_W_XS, /* 14058 */ IC_VEX_L_W_XS, /* 14059 */ IC_VEX_L_W_XD, /* 14060 */ IC_VEX_L_W_XD, /* 14061 */ IC_VEX_L_W_XD, /* 14062 */ IC_VEX_L_W_XD, /* 14063 */ IC_VEX_L_OPSIZE, /* 14064 */ IC_VEX_L_OPSIZE, /* 14065 */ IC_VEX_L_OPSIZE, /* 14066 */ IC_VEX_L_OPSIZE, /* 14067 */ IC_VEX_L_OPSIZE, /* 14068 */ IC_VEX_L_OPSIZE, /* 14069 */ IC_VEX_L_OPSIZE, /* 14070 */ IC_VEX_L_OPSIZE, /* 14071 */ IC_VEX_L_W_OPSIZE, /* 14072 */ IC_VEX_L_W_OPSIZE, /* 14073 */ IC_VEX_L_W_OPSIZE, /* 14074 */ IC_VEX_L_W_OPSIZE, /* 14075 */ IC_VEX_L_W_OPSIZE, /* 14076 */ IC_VEX_L_W_OPSIZE, /* 14077 */ IC_VEX_L_W_OPSIZE, /* 14078 */ IC_VEX_L_W_OPSIZE, /* 14079 */ IC_EVEX_L2_KZ_B, /* 14080 */ IC_EVEX_L2_KZ_B, /* 14081 */ IC_EVEX_L2_XS_KZ_B, /* 14082 */ IC_EVEX_L2_XS_KZ_B, /* 14083 */ IC_EVEX_L2_XD_KZ_B, /* 14084 */ IC_EVEX_L2_XD_KZ_B, /* 14085 */ IC_EVEX_L2_XD_KZ_B, /* 14086 */ IC_EVEX_L2_XD_KZ_B, /* 14087 */ IC_EVEX_L2_W_KZ_B, /* 14088 */ IC_EVEX_L2_W_KZ_B, /* 14089 */ IC_EVEX_L2_W_XS_KZ_B, /* 14090 */ IC_EVEX_L2_W_XS_KZ_B, /* 14091 */ IC_EVEX_L2_W_XD_KZ_B, /* 14092 */ IC_EVEX_L2_W_XD_KZ_B, /* 14093 */ IC_EVEX_L2_W_XD_KZ_B, /* 14094 */ IC_EVEX_L2_W_XD_KZ_B, /* 14095 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14096 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14097 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14098 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14099 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14100 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14101 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14102 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14103 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14104 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14105 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14106 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14107 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14108 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14109 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14110 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14111 */ IC_EVEX_L2_KZ_B, /* 14112 */ IC_EVEX_L2_KZ_B, /* 14113 */ IC_EVEX_L2_XS_KZ_B, /* 14114 */ IC_EVEX_L2_XS_KZ_B, /* 14115 */ IC_EVEX_L2_XD_KZ_B, /* 14116 */ IC_EVEX_L2_XD_KZ_B, /* 14117 */ IC_EVEX_L2_XD_KZ_B, /* 14118 */ IC_EVEX_L2_XD_KZ_B, /* 14119 */ IC_EVEX_L2_W_KZ_B, /* 14120 */ IC_EVEX_L2_W_KZ_B, /* 14121 */ IC_EVEX_L2_W_XS_KZ_B, /* 14122 */ IC_EVEX_L2_W_XS_KZ_B, /* 14123 */ IC_EVEX_L2_W_XD_KZ_B, /* 14124 */ IC_EVEX_L2_W_XD_KZ_B, /* 14125 */ IC_EVEX_L2_W_XD_KZ_B, /* 14126 */ IC_EVEX_L2_W_XD_KZ_B, /* 14127 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14128 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14129 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14130 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14131 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14132 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14133 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14134 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14135 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14136 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14137 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14138 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14139 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14140 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14141 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14142 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14143 */ IC_EVEX_L2_KZ_B, /* 14144 */ IC_EVEX_L2_KZ_B, /* 14145 */ IC_EVEX_L2_XS_KZ_B, /* 14146 */ IC_EVEX_L2_XS_KZ_B, /* 14147 */ IC_EVEX_L2_XD_KZ_B, /* 14148 */ IC_EVEX_L2_XD_KZ_B, /* 14149 */ IC_EVEX_L2_XD_KZ_B, /* 14150 */ IC_EVEX_L2_XD_KZ_B, /* 14151 */ IC_EVEX_L2_W_KZ_B, /* 14152 */ IC_EVEX_L2_W_KZ_B, /* 14153 */ IC_EVEX_L2_W_XS_KZ_B, /* 14154 */ IC_EVEX_L2_W_XS_KZ_B, /* 14155 */ IC_EVEX_L2_W_XD_KZ_B, /* 14156 */ IC_EVEX_L2_W_XD_KZ_B, /* 14157 */ IC_EVEX_L2_W_XD_KZ_B, /* 14158 */ IC_EVEX_L2_W_XD_KZ_B, /* 14159 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14160 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14161 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14162 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14163 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14164 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14165 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14166 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14167 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14168 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14169 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14170 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14171 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14172 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14173 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14174 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14175 */ IC_EVEX_L2_KZ_B, /* 14176 */ IC_EVEX_L2_KZ_B, /* 14177 */ IC_EVEX_L2_XS_KZ_B, /* 14178 */ IC_EVEX_L2_XS_KZ_B, /* 14179 */ IC_EVEX_L2_XD_KZ_B, /* 14180 */ IC_EVEX_L2_XD_KZ_B, /* 14181 */ IC_EVEX_L2_XD_KZ_B, /* 14182 */ IC_EVEX_L2_XD_KZ_B, /* 14183 */ IC_EVEX_L2_W_KZ_B, /* 14184 */ IC_EVEX_L2_W_KZ_B, /* 14185 */ IC_EVEX_L2_W_XS_KZ_B, /* 14186 */ IC_EVEX_L2_W_XS_KZ_B, /* 14187 */ IC_EVEX_L2_W_XD_KZ_B, /* 14188 */ IC_EVEX_L2_W_XD_KZ_B, /* 14189 */ IC_EVEX_L2_W_XD_KZ_B, /* 14190 */ IC_EVEX_L2_W_XD_KZ_B, /* 14191 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14192 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14193 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14194 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14195 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14196 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14197 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14198 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14199 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14200 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14201 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14202 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14203 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14204 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14205 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14206 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14207 */ IC_EVEX_L2_KZ_B, /* 14208 */ IC_EVEX_L2_KZ_B, /* 14209 */ IC_EVEX_L2_XS_KZ_B, /* 14210 */ IC_EVEX_L2_XS_KZ_B, /* 14211 */ IC_EVEX_L2_XD_KZ_B, /* 14212 */ IC_EVEX_L2_XD_KZ_B, /* 14213 */ IC_EVEX_L2_XD_KZ_B, /* 14214 */ IC_EVEX_L2_XD_KZ_B, /* 14215 */ IC_EVEX_L2_W_KZ_B, /* 14216 */ IC_EVEX_L2_W_KZ_B, /* 14217 */ IC_EVEX_L2_W_XS_KZ_B, /* 14218 */ IC_EVEX_L2_W_XS_KZ_B, /* 14219 */ IC_EVEX_L2_W_XD_KZ_B, /* 14220 */ IC_EVEX_L2_W_XD_KZ_B, /* 14221 */ IC_EVEX_L2_W_XD_KZ_B, /* 14222 */ IC_EVEX_L2_W_XD_KZ_B, /* 14223 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14224 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14225 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14226 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14227 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14228 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14229 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14230 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14231 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14232 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14233 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14234 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14235 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14236 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14237 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14238 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14239 */ IC_EVEX_L2_KZ_B, /* 14240 */ IC_EVEX_L2_KZ_B, /* 14241 */ IC_EVEX_L2_XS_KZ_B, /* 14242 */ IC_EVEX_L2_XS_KZ_B, /* 14243 */ IC_EVEX_L2_XD_KZ_B, /* 14244 */ IC_EVEX_L2_XD_KZ_B, /* 14245 */ IC_EVEX_L2_XD_KZ_B, /* 14246 */ IC_EVEX_L2_XD_KZ_B, /* 14247 */ IC_EVEX_L2_W_KZ_B, /* 14248 */ IC_EVEX_L2_W_KZ_B, /* 14249 */ IC_EVEX_L2_W_XS_KZ_B, /* 14250 */ IC_EVEX_L2_W_XS_KZ_B, /* 14251 */ IC_EVEX_L2_W_XD_KZ_B, /* 14252 */ IC_EVEX_L2_W_XD_KZ_B, /* 14253 */ IC_EVEX_L2_W_XD_KZ_B, /* 14254 */ IC_EVEX_L2_W_XD_KZ_B, /* 14255 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14256 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14257 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14258 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14259 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14260 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14261 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14262 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14263 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14264 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14265 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14266 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14267 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14268 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14269 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14270 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14271 */ IC_EVEX_L2_KZ_B, /* 14272 */ IC_EVEX_L2_KZ_B, /* 14273 */ IC_EVEX_L2_XS_KZ_B, /* 14274 */ IC_EVEX_L2_XS_KZ_B, /* 14275 */ IC_EVEX_L2_XD_KZ_B, /* 14276 */ IC_EVEX_L2_XD_KZ_B, /* 14277 */ IC_EVEX_L2_XD_KZ_B, /* 14278 */ IC_EVEX_L2_XD_KZ_B, /* 14279 */ IC_EVEX_L2_W_KZ_B, /* 14280 */ IC_EVEX_L2_W_KZ_B, /* 14281 */ IC_EVEX_L2_W_XS_KZ_B, /* 14282 */ IC_EVEX_L2_W_XS_KZ_B, /* 14283 */ IC_EVEX_L2_W_XD_KZ_B, /* 14284 */ IC_EVEX_L2_W_XD_KZ_B, /* 14285 */ IC_EVEX_L2_W_XD_KZ_B, /* 14286 */ IC_EVEX_L2_W_XD_KZ_B, /* 14287 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14288 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14289 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14290 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14291 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14292 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14293 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14294 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14295 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14296 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14297 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14298 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14299 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14300 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14301 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14302 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14303 */ IC_EVEX_L2_KZ_B, /* 14304 */ IC_EVEX_L2_KZ_B, /* 14305 */ IC_EVEX_L2_XS_KZ_B, /* 14306 */ IC_EVEX_L2_XS_KZ_B, /* 14307 */ IC_EVEX_L2_XD_KZ_B, /* 14308 */ IC_EVEX_L2_XD_KZ_B, /* 14309 */ IC_EVEX_L2_XD_KZ_B, /* 14310 */ IC_EVEX_L2_XD_KZ_B, /* 14311 */ IC_EVEX_L2_W_KZ_B, /* 14312 */ IC_EVEX_L2_W_KZ_B, /* 14313 */ IC_EVEX_L2_W_XS_KZ_B, /* 14314 */ IC_EVEX_L2_W_XS_KZ_B, /* 14315 */ IC_EVEX_L2_W_XD_KZ_B, /* 14316 */ IC_EVEX_L2_W_XD_KZ_B, /* 14317 */ IC_EVEX_L2_W_XD_KZ_B, /* 14318 */ IC_EVEX_L2_W_XD_KZ_B, /* 14319 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14320 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14321 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14322 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14323 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14324 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14325 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14326 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 14327 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14328 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14329 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14330 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14331 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14332 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14333 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14334 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14335 */ IC, /* 14336 */ IC_64BIT, /* 14337 */ IC_XS, /* 14338 */ IC_64BIT_XS, /* 14339 */ IC_XD, /* 14340 */ IC_64BIT_XD, /* 14341 */ IC_XS, /* 14342 */ IC_64BIT_XS, /* 14343 */ IC, /* 14344 */ IC_64BIT_REXW, /* 14345 */ IC_XS, /* 14346 */ IC_64BIT_REXW_XS, /* 14347 */ IC_XD, /* 14348 */ IC_64BIT_REXW_XD, /* 14349 */ IC_XS, /* 14350 */ IC_64BIT_REXW_XS, /* 14351 */ IC_OPSIZE, /* 14352 */ IC_64BIT_OPSIZE, /* 14353 */ IC_XS_OPSIZE, /* 14354 */ IC_64BIT_XS_OPSIZE, /* 14355 */ IC_XD_OPSIZE, /* 14356 */ IC_64BIT_XD_OPSIZE, /* 14357 */ IC_XS_OPSIZE, /* 14358 */ IC_64BIT_XD_OPSIZE, /* 14359 */ IC_OPSIZE, /* 14360 */ IC_64BIT_REXW_OPSIZE, /* 14361 */ IC_XS_OPSIZE, /* 14362 */ IC_64BIT_REXW_XS, /* 14363 */ IC_XD_OPSIZE, /* 14364 */ IC_64BIT_REXW_XD, /* 14365 */ IC_XS_OPSIZE, /* 14366 */ IC_64BIT_REXW_XS, /* 14367 */ IC_ADSIZE, /* 14368 */ IC_64BIT_ADSIZE, /* 14369 */ IC_XS_ADSIZE, /* 14370 */ IC_64BIT_XS_ADSIZE, /* 14371 */ IC_XD_ADSIZE, /* 14372 */ IC_64BIT_XD_ADSIZE, /* 14373 */ IC_XS_ADSIZE, /* 14374 */ IC_64BIT_XD_ADSIZE, /* 14375 */ IC_ADSIZE, /* 14376 */ IC_64BIT_REXW_ADSIZE, /* 14377 */ IC_XS_ADSIZE, /* 14378 */ IC_64BIT_REXW_XS, /* 14379 */ IC_XD_ADSIZE, /* 14380 */ IC_64BIT_REXW_XD, /* 14381 */ IC_XS_ADSIZE, /* 14382 */ IC_64BIT_REXW_XS, /* 14383 */ IC_OPSIZE_ADSIZE, /* 14384 */ IC_64BIT_OPSIZE_ADSIZE, /* 14385 */ IC_XS_OPSIZE, /* 14386 */ IC_64BIT_XS_OPSIZE, /* 14387 */ IC_XD_OPSIZE, /* 14388 */ IC_64BIT_XD_OPSIZE, /* 14389 */ IC_XS_OPSIZE, /* 14390 */ IC_64BIT_XD_OPSIZE, /* 14391 */ IC_OPSIZE_ADSIZE, /* 14392 */ IC_64BIT_REXW_OPSIZE, /* 14393 */ IC_XS_OPSIZE, /* 14394 */ IC_64BIT_REXW_XS, /* 14395 */ IC_XD_OPSIZE, /* 14396 */ IC_64BIT_REXW_XD, /* 14397 */ IC_XS_OPSIZE, /* 14398 */ IC_64BIT_REXW_XS, /* 14399 */ IC_VEX, /* 14400 */ IC_VEX, /* 14401 */ IC_VEX_XS, /* 14402 */ IC_VEX_XS, /* 14403 */ IC_VEX_XD, /* 14404 */ IC_VEX_XD, /* 14405 */ IC_VEX_XD, /* 14406 */ IC_VEX_XD, /* 14407 */ IC_VEX_W, /* 14408 */ IC_VEX_W, /* 14409 */ IC_VEX_W_XS, /* 14410 */ IC_VEX_W_XS, /* 14411 */ IC_VEX_W_XD, /* 14412 */ IC_VEX_W_XD, /* 14413 */ IC_VEX_W_XD, /* 14414 */ IC_VEX_W_XD, /* 14415 */ IC_VEX_OPSIZE, /* 14416 */ IC_VEX_OPSIZE, /* 14417 */ IC_VEX_OPSIZE, /* 14418 */ IC_VEX_OPSIZE, /* 14419 */ IC_VEX_OPSIZE, /* 14420 */ IC_VEX_OPSIZE, /* 14421 */ IC_VEX_OPSIZE, /* 14422 */ IC_VEX_OPSIZE, /* 14423 */ IC_VEX_W_OPSIZE, /* 14424 */ IC_VEX_W_OPSIZE, /* 14425 */ IC_VEX_W_OPSIZE, /* 14426 */ IC_VEX_W_OPSIZE, /* 14427 */ IC_VEX_W_OPSIZE, /* 14428 */ IC_VEX_W_OPSIZE, /* 14429 */ IC_VEX_W_OPSIZE, /* 14430 */ IC_VEX_W_OPSIZE, /* 14431 */ IC_VEX, /* 14432 */ IC_VEX, /* 14433 */ IC_VEX_XS, /* 14434 */ IC_VEX_XS, /* 14435 */ IC_VEX_XD, /* 14436 */ IC_VEX_XD, /* 14437 */ IC_VEX_XD, /* 14438 */ IC_VEX_XD, /* 14439 */ IC_VEX_W, /* 14440 */ IC_VEX_W, /* 14441 */ IC_VEX_W_XS, /* 14442 */ IC_VEX_W_XS, /* 14443 */ IC_VEX_W_XD, /* 14444 */ IC_VEX_W_XD, /* 14445 */ IC_VEX_W_XD, /* 14446 */ IC_VEX_W_XD, /* 14447 */ IC_VEX_OPSIZE, /* 14448 */ IC_VEX_OPSIZE, /* 14449 */ IC_VEX_OPSIZE, /* 14450 */ IC_VEX_OPSIZE, /* 14451 */ IC_VEX_OPSIZE, /* 14452 */ IC_VEX_OPSIZE, /* 14453 */ IC_VEX_OPSIZE, /* 14454 */ IC_VEX_OPSIZE, /* 14455 */ IC_VEX_W_OPSIZE, /* 14456 */ IC_VEX_W_OPSIZE, /* 14457 */ IC_VEX_W_OPSIZE, /* 14458 */ IC_VEX_W_OPSIZE, /* 14459 */ IC_VEX_W_OPSIZE, /* 14460 */ IC_VEX_W_OPSIZE, /* 14461 */ IC_VEX_W_OPSIZE, /* 14462 */ IC_VEX_W_OPSIZE, /* 14463 */ IC_VEX_L, /* 14464 */ IC_VEX_L, /* 14465 */ IC_VEX_L_XS, /* 14466 */ IC_VEX_L_XS, /* 14467 */ IC_VEX_L_XD, /* 14468 */ IC_VEX_L_XD, /* 14469 */ IC_VEX_L_XD, /* 14470 */ IC_VEX_L_XD, /* 14471 */ IC_VEX_L_W, /* 14472 */ IC_VEX_L_W, /* 14473 */ IC_VEX_L_W_XS, /* 14474 */ IC_VEX_L_W_XS, /* 14475 */ IC_VEX_L_W_XD, /* 14476 */ IC_VEX_L_W_XD, /* 14477 */ IC_VEX_L_W_XD, /* 14478 */ IC_VEX_L_W_XD, /* 14479 */ IC_VEX_L_OPSIZE, /* 14480 */ IC_VEX_L_OPSIZE, /* 14481 */ IC_VEX_L_OPSIZE, /* 14482 */ IC_VEX_L_OPSIZE, /* 14483 */ IC_VEX_L_OPSIZE, /* 14484 */ IC_VEX_L_OPSIZE, /* 14485 */ IC_VEX_L_OPSIZE, /* 14486 */ IC_VEX_L_OPSIZE, /* 14487 */ IC_VEX_L_W_OPSIZE, /* 14488 */ IC_VEX_L_W_OPSIZE, /* 14489 */ IC_VEX_L_W_OPSIZE, /* 14490 */ IC_VEX_L_W_OPSIZE, /* 14491 */ IC_VEX_L_W_OPSIZE, /* 14492 */ IC_VEX_L_W_OPSIZE, /* 14493 */ IC_VEX_L_W_OPSIZE, /* 14494 */ IC_VEX_L_W_OPSIZE, /* 14495 */ IC_VEX_L, /* 14496 */ IC_VEX_L, /* 14497 */ IC_VEX_L_XS, /* 14498 */ IC_VEX_L_XS, /* 14499 */ IC_VEX_L_XD, /* 14500 */ IC_VEX_L_XD, /* 14501 */ IC_VEX_L_XD, /* 14502 */ IC_VEX_L_XD, /* 14503 */ IC_VEX_L_W, /* 14504 */ IC_VEX_L_W, /* 14505 */ IC_VEX_L_W_XS, /* 14506 */ IC_VEX_L_W_XS, /* 14507 */ IC_VEX_L_W_XD, /* 14508 */ IC_VEX_L_W_XD, /* 14509 */ IC_VEX_L_W_XD, /* 14510 */ IC_VEX_L_W_XD, /* 14511 */ IC_VEX_L_OPSIZE, /* 14512 */ IC_VEX_L_OPSIZE, /* 14513 */ IC_VEX_L_OPSIZE, /* 14514 */ IC_VEX_L_OPSIZE, /* 14515 */ IC_VEX_L_OPSIZE, /* 14516 */ IC_VEX_L_OPSIZE, /* 14517 */ IC_VEX_L_OPSIZE, /* 14518 */ IC_VEX_L_OPSIZE, /* 14519 */ IC_VEX_L_W_OPSIZE, /* 14520 */ IC_VEX_L_W_OPSIZE, /* 14521 */ IC_VEX_L_W_OPSIZE, /* 14522 */ IC_VEX_L_W_OPSIZE, /* 14523 */ IC_VEX_L_W_OPSIZE, /* 14524 */ IC_VEX_L_W_OPSIZE, /* 14525 */ IC_VEX_L_W_OPSIZE, /* 14526 */ IC_VEX_L_W_OPSIZE, /* 14527 */ IC_VEX_L, /* 14528 */ IC_VEX_L, /* 14529 */ IC_VEX_L_XS, /* 14530 */ IC_VEX_L_XS, /* 14531 */ IC_VEX_L_XD, /* 14532 */ IC_VEX_L_XD, /* 14533 */ IC_VEX_L_XD, /* 14534 */ IC_VEX_L_XD, /* 14535 */ IC_VEX_L_W, /* 14536 */ IC_VEX_L_W, /* 14537 */ IC_VEX_L_W_XS, /* 14538 */ IC_VEX_L_W_XS, /* 14539 */ IC_VEX_L_W_XD, /* 14540 */ IC_VEX_L_W_XD, /* 14541 */ IC_VEX_L_W_XD, /* 14542 */ IC_VEX_L_W_XD, /* 14543 */ IC_VEX_L_OPSIZE, /* 14544 */ IC_VEX_L_OPSIZE, /* 14545 */ IC_VEX_L_OPSIZE, /* 14546 */ IC_VEX_L_OPSIZE, /* 14547 */ IC_VEX_L_OPSIZE, /* 14548 */ IC_VEX_L_OPSIZE, /* 14549 */ IC_VEX_L_OPSIZE, /* 14550 */ IC_VEX_L_OPSIZE, /* 14551 */ IC_VEX_L_W_OPSIZE, /* 14552 */ IC_VEX_L_W_OPSIZE, /* 14553 */ IC_VEX_L_W_OPSIZE, /* 14554 */ IC_VEX_L_W_OPSIZE, /* 14555 */ IC_VEX_L_W_OPSIZE, /* 14556 */ IC_VEX_L_W_OPSIZE, /* 14557 */ IC_VEX_L_W_OPSIZE, /* 14558 */ IC_VEX_L_W_OPSIZE, /* 14559 */ IC_VEX_L, /* 14560 */ IC_VEX_L, /* 14561 */ IC_VEX_L_XS, /* 14562 */ IC_VEX_L_XS, /* 14563 */ IC_VEX_L_XD, /* 14564 */ IC_VEX_L_XD, /* 14565 */ IC_VEX_L_XD, /* 14566 */ IC_VEX_L_XD, /* 14567 */ IC_VEX_L_W, /* 14568 */ IC_VEX_L_W, /* 14569 */ IC_VEX_L_W_XS, /* 14570 */ IC_VEX_L_W_XS, /* 14571 */ IC_VEX_L_W_XD, /* 14572 */ IC_VEX_L_W_XD, /* 14573 */ IC_VEX_L_W_XD, /* 14574 */ IC_VEX_L_W_XD, /* 14575 */ IC_VEX_L_OPSIZE, /* 14576 */ IC_VEX_L_OPSIZE, /* 14577 */ IC_VEX_L_OPSIZE, /* 14578 */ IC_VEX_L_OPSIZE, /* 14579 */ IC_VEX_L_OPSIZE, /* 14580 */ IC_VEX_L_OPSIZE, /* 14581 */ IC_VEX_L_OPSIZE, /* 14582 */ IC_VEX_L_OPSIZE, /* 14583 */ IC_VEX_L_W_OPSIZE, /* 14584 */ IC_VEX_L_W_OPSIZE, /* 14585 */ IC_VEX_L_W_OPSIZE, /* 14586 */ IC_VEX_L_W_OPSIZE, /* 14587 */ IC_VEX_L_W_OPSIZE, /* 14588 */ IC_VEX_L_W_OPSIZE, /* 14589 */ IC_VEX_L_W_OPSIZE, /* 14590 */ IC_VEX_L_W_OPSIZE, /* 14591 */ IC_EVEX_KZ_B, /* 14592 */ IC_EVEX_KZ_B, /* 14593 */ IC_EVEX_XS_KZ_B, /* 14594 */ IC_EVEX_XS_KZ_B, /* 14595 */ IC_EVEX_XD_KZ_B, /* 14596 */ IC_EVEX_XD_KZ_B, /* 14597 */ IC_EVEX_XD_KZ_B, /* 14598 */ IC_EVEX_XD_KZ_B, /* 14599 */ IC_EVEX_W_KZ_B, /* 14600 */ IC_EVEX_W_KZ_B, /* 14601 */ IC_EVEX_W_XS_KZ_B, /* 14602 */ IC_EVEX_W_XS_KZ_B, /* 14603 */ IC_EVEX_W_XD_KZ_B, /* 14604 */ IC_EVEX_W_XD_KZ_B, /* 14605 */ IC_EVEX_W_XD_KZ_B, /* 14606 */ IC_EVEX_W_XD_KZ_B, /* 14607 */ IC_EVEX_OPSIZE_KZ_B, /* 14608 */ IC_EVEX_OPSIZE_KZ_B, /* 14609 */ IC_EVEX_OPSIZE_KZ_B, /* 14610 */ IC_EVEX_OPSIZE_KZ_B, /* 14611 */ IC_EVEX_OPSIZE_KZ_B, /* 14612 */ IC_EVEX_OPSIZE_KZ_B, /* 14613 */ IC_EVEX_OPSIZE_KZ_B, /* 14614 */ IC_EVEX_OPSIZE_KZ_B, /* 14615 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14616 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14617 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14618 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14619 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14620 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14621 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14622 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14623 */ IC_EVEX_KZ_B, /* 14624 */ IC_EVEX_KZ_B, /* 14625 */ IC_EVEX_XS_KZ_B, /* 14626 */ IC_EVEX_XS_KZ_B, /* 14627 */ IC_EVEX_XD_KZ_B, /* 14628 */ IC_EVEX_XD_KZ_B, /* 14629 */ IC_EVEX_XD_KZ_B, /* 14630 */ IC_EVEX_XD_KZ_B, /* 14631 */ IC_EVEX_W_KZ_B, /* 14632 */ IC_EVEX_W_KZ_B, /* 14633 */ IC_EVEX_W_XS_KZ_B, /* 14634 */ IC_EVEX_W_XS_KZ_B, /* 14635 */ IC_EVEX_W_XD_KZ_B, /* 14636 */ IC_EVEX_W_XD_KZ_B, /* 14637 */ IC_EVEX_W_XD_KZ_B, /* 14638 */ IC_EVEX_W_XD_KZ_B, /* 14639 */ IC_EVEX_OPSIZE_KZ_B, /* 14640 */ IC_EVEX_OPSIZE_KZ_B, /* 14641 */ IC_EVEX_OPSIZE_KZ_B, /* 14642 */ IC_EVEX_OPSIZE_KZ_B, /* 14643 */ IC_EVEX_OPSIZE_KZ_B, /* 14644 */ IC_EVEX_OPSIZE_KZ_B, /* 14645 */ IC_EVEX_OPSIZE_KZ_B, /* 14646 */ IC_EVEX_OPSIZE_KZ_B, /* 14647 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14648 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14649 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14650 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14651 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14652 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14653 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14654 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14655 */ IC_EVEX_KZ_B, /* 14656 */ IC_EVEX_KZ_B, /* 14657 */ IC_EVEX_XS_KZ_B, /* 14658 */ IC_EVEX_XS_KZ_B, /* 14659 */ IC_EVEX_XD_KZ_B, /* 14660 */ IC_EVEX_XD_KZ_B, /* 14661 */ IC_EVEX_XD_KZ_B, /* 14662 */ IC_EVEX_XD_KZ_B, /* 14663 */ IC_EVEX_W_KZ_B, /* 14664 */ IC_EVEX_W_KZ_B, /* 14665 */ IC_EVEX_W_XS_KZ_B, /* 14666 */ IC_EVEX_W_XS_KZ_B, /* 14667 */ IC_EVEX_W_XD_KZ_B, /* 14668 */ IC_EVEX_W_XD_KZ_B, /* 14669 */ IC_EVEX_W_XD_KZ_B, /* 14670 */ IC_EVEX_W_XD_KZ_B, /* 14671 */ IC_EVEX_OPSIZE_KZ_B, /* 14672 */ IC_EVEX_OPSIZE_KZ_B, /* 14673 */ IC_EVEX_OPSIZE_KZ_B, /* 14674 */ IC_EVEX_OPSIZE_KZ_B, /* 14675 */ IC_EVEX_OPSIZE_KZ_B, /* 14676 */ IC_EVEX_OPSIZE_KZ_B, /* 14677 */ IC_EVEX_OPSIZE_KZ_B, /* 14678 */ IC_EVEX_OPSIZE_KZ_B, /* 14679 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14680 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14681 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14682 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14683 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14684 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14685 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14686 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14687 */ IC_EVEX_KZ_B, /* 14688 */ IC_EVEX_KZ_B, /* 14689 */ IC_EVEX_XS_KZ_B, /* 14690 */ IC_EVEX_XS_KZ_B, /* 14691 */ IC_EVEX_XD_KZ_B, /* 14692 */ IC_EVEX_XD_KZ_B, /* 14693 */ IC_EVEX_XD_KZ_B, /* 14694 */ IC_EVEX_XD_KZ_B, /* 14695 */ IC_EVEX_W_KZ_B, /* 14696 */ IC_EVEX_W_KZ_B, /* 14697 */ IC_EVEX_W_XS_KZ_B, /* 14698 */ IC_EVEX_W_XS_KZ_B, /* 14699 */ IC_EVEX_W_XD_KZ_B, /* 14700 */ IC_EVEX_W_XD_KZ_B, /* 14701 */ IC_EVEX_W_XD_KZ_B, /* 14702 */ IC_EVEX_W_XD_KZ_B, /* 14703 */ IC_EVEX_OPSIZE_KZ_B, /* 14704 */ IC_EVEX_OPSIZE_KZ_B, /* 14705 */ IC_EVEX_OPSIZE_KZ_B, /* 14706 */ IC_EVEX_OPSIZE_KZ_B, /* 14707 */ IC_EVEX_OPSIZE_KZ_B, /* 14708 */ IC_EVEX_OPSIZE_KZ_B, /* 14709 */ IC_EVEX_OPSIZE_KZ_B, /* 14710 */ IC_EVEX_OPSIZE_KZ_B, /* 14711 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14712 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14713 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14714 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14715 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14716 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14717 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14718 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14719 */ IC_EVEX_KZ_B, /* 14720 */ IC_EVEX_KZ_B, /* 14721 */ IC_EVEX_XS_KZ_B, /* 14722 */ IC_EVEX_XS_KZ_B, /* 14723 */ IC_EVEX_XD_KZ_B, /* 14724 */ IC_EVEX_XD_KZ_B, /* 14725 */ IC_EVEX_XD_KZ_B, /* 14726 */ IC_EVEX_XD_KZ_B, /* 14727 */ IC_EVEX_W_KZ_B, /* 14728 */ IC_EVEX_W_KZ_B, /* 14729 */ IC_EVEX_W_XS_KZ_B, /* 14730 */ IC_EVEX_W_XS_KZ_B, /* 14731 */ IC_EVEX_W_XD_KZ_B, /* 14732 */ IC_EVEX_W_XD_KZ_B, /* 14733 */ IC_EVEX_W_XD_KZ_B, /* 14734 */ IC_EVEX_W_XD_KZ_B, /* 14735 */ IC_EVEX_OPSIZE_KZ_B, /* 14736 */ IC_EVEX_OPSIZE_KZ_B, /* 14737 */ IC_EVEX_OPSIZE_KZ_B, /* 14738 */ IC_EVEX_OPSIZE_KZ_B, /* 14739 */ IC_EVEX_OPSIZE_KZ_B, /* 14740 */ IC_EVEX_OPSIZE_KZ_B, /* 14741 */ IC_EVEX_OPSIZE_KZ_B, /* 14742 */ IC_EVEX_OPSIZE_KZ_B, /* 14743 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14744 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14745 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14746 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14747 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14748 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14749 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14750 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14751 */ IC_EVEX_KZ_B, /* 14752 */ IC_EVEX_KZ_B, /* 14753 */ IC_EVEX_XS_KZ_B, /* 14754 */ IC_EVEX_XS_KZ_B, /* 14755 */ IC_EVEX_XD_KZ_B, /* 14756 */ IC_EVEX_XD_KZ_B, /* 14757 */ IC_EVEX_XD_KZ_B, /* 14758 */ IC_EVEX_XD_KZ_B, /* 14759 */ IC_EVEX_W_KZ_B, /* 14760 */ IC_EVEX_W_KZ_B, /* 14761 */ IC_EVEX_W_XS_KZ_B, /* 14762 */ IC_EVEX_W_XS_KZ_B, /* 14763 */ IC_EVEX_W_XD_KZ_B, /* 14764 */ IC_EVEX_W_XD_KZ_B, /* 14765 */ IC_EVEX_W_XD_KZ_B, /* 14766 */ IC_EVEX_W_XD_KZ_B, /* 14767 */ IC_EVEX_OPSIZE_KZ_B, /* 14768 */ IC_EVEX_OPSIZE_KZ_B, /* 14769 */ IC_EVEX_OPSIZE_KZ_B, /* 14770 */ IC_EVEX_OPSIZE_KZ_B, /* 14771 */ IC_EVEX_OPSIZE_KZ_B, /* 14772 */ IC_EVEX_OPSIZE_KZ_B, /* 14773 */ IC_EVEX_OPSIZE_KZ_B, /* 14774 */ IC_EVEX_OPSIZE_KZ_B, /* 14775 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14776 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14777 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14778 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14779 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14780 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14781 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14782 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14783 */ IC_EVEX_KZ_B, /* 14784 */ IC_EVEX_KZ_B, /* 14785 */ IC_EVEX_XS_KZ_B, /* 14786 */ IC_EVEX_XS_KZ_B, /* 14787 */ IC_EVEX_XD_KZ_B, /* 14788 */ IC_EVEX_XD_KZ_B, /* 14789 */ IC_EVEX_XD_KZ_B, /* 14790 */ IC_EVEX_XD_KZ_B, /* 14791 */ IC_EVEX_W_KZ_B, /* 14792 */ IC_EVEX_W_KZ_B, /* 14793 */ IC_EVEX_W_XS_KZ_B, /* 14794 */ IC_EVEX_W_XS_KZ_B, /* 14795 */ IC_EVEX_W_XD_KZ_B, /* 14796 */ IC_EVEX_W_XD_KZ_B, /* 14797 */ IC_EVEX_W_XD_KZ_B, /* 14798 */ IC_EVEX_W_XD_KZ_B, /* 14799 */ IC_EVEX_OPSIZE_KZ_B, /* 14800 */ IC_EVEX_OPSIZE_KZ_B, /* 14801 */ IC_EVEX_OPSIZE_KZ_B, /* 14802 */ IC_EVEX_OPSIZE_KZ_B, /* 14803 */ IC_EVEX_OPSIZE_KZ_B, /* 14804 */ IC_EVEX_OPSIZE_KZ_B, /* 14805 */ IC_EVEX_OPSIZE_KZ_B, /* 14806 */ IC_EVEX_OPSIZE_KZ_B, /* 14807 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14808 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14809 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14810 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14811 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14812 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14813 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14814 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14815 */ IC_EVEX_KZ_B, /* 14816 */ IC_EVEX_KZ_B, /* 14817 */ IC_EVEX_XS_KZ_B, /* 14818 */ IC_EVEX_XS_KZ_B, /* 14819 */ IC_EVEX_XD_KZ_B, /* 14820 */ IC_EVEX_XD_KZ_B, /* 14821 */ IC_EVEX_XD_KZ_B, /* 14822 */ IC_EVEX_XD_KZ_B, /* 14823 */ IC_EVEX_W_KZ_B, /* 14824 */ IC_EVEX_W_KZ_B, /* 14825 */ IC_EVEX_W_XS_KZ_B, /* 14826 */ IC_EVEX_W_XS_KZ_B, /* 14827 */ IC_EVEX_W_XD_KZ_B, /* 14828 */ IC_EVEX_W_XD_KZ_B, /* 14829 */ IC_EVEX_W_XD_KZ_B, /* 14830 */ IC_EVEX_W_XD_KZ_B, /* 14831 */ IC_EVEX_OPSIZE_KZ_B, /* 14832 */ IC_EVEX_OPSIZE_KZ_B, /* 14833 */ IC_EVEX_OPSIZE_KZ_B, /* 14834 */ IC_EVEX_OPSIZE_KZ_B, /* 14835 */ IC_EVEX_OPSIZE_KZ_B, /* 14836 */ IC_EVEX_OPSIZE_KZ_B, /* 14837 */ IC_EVEX_OPSIZE_KZ_B, /* 14838 */ IC_EVEX_OPSIZE_KZ_B, /* 14839 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14840 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14841 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14842 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14843 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14844 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14845 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14846 */ IC_EVEX_W_OPSIZE_KZ_B, /* 14847 */ IC, /* 14848 */ IC_64BIT, /* 14849 */ IC_XS, /* 14850 */ IC_64BIT_XS, /* 14851 */ IC_XD, /* 14852 */ IC_64BIT_XD, /* 14853 */ IC_XS, /* 14854 */ IC_64BIT_XS, /* 14855 */ IC, /* 14856 */ IC_64BIT_REXW, /* 14857 */ IC_XS, /* 14858 */ IC_64BIT_REXW_XS, /* 14859 */ IC_XD, /* 14860 */ IC_64BIT_REXW_XD, /* 14861 */ IC_XS, /* 14862 */ IC_64BIT_REXW_XS, /* 14863 */ IC_OPSIZE, /* 14864 */ IC_64BIT_OPSIZE, /* 14865 */ IC_XS_OPSIZE, /* 14866 */ IC_64BIT_XS_OPSIZE, /* 14867 */ IC_XD_OPSIZE, /* 14868 */ IC_64BIT_XD_OPSIZE, /* 14869 */ IC_XS_OPSIZE, /* 14870 */ IC_64BIT_XD_OPSIZE, /* 14871 */ IC_OPSIZE, /* 14872 */ IC_64BIT_REXW_OPSIZE, /* 14873 */ IC_XS_OPSIZE, /* 14874 */ IC_64BIT_REXW_XS, /* 14875 */ IC_XD_OPSIZE, /* 14876 */ IC_64BIT_REXW_XD, /* 14877 */ IC_XS_OPSIZE, /* 14878 */ IC_64BIT_REXW_XS, /* 14879 */ IC_ADSIZE, /* 14880 */ IC_64BIT_ADSIZE, /* 14881 */ IC_XS_ADSIZE, /* 14882 */ IC_64BIT_XS_ADSIZE, /* 14883 */ IC_XD_ADSIZE, /* 14884 */ IC_64BIT_XD_ADSIZE, /* 14885 */ IC_XS_ADSIZE, /* 14886 */ IC_64BIT_XD_ADSIZE, /* 14887 */ IC_ADSIZE, /* 14888 */ IC_64BIT_REXW_ADSIZE, /* 14889 */ IC_XS_ADSIZE, /* 14890 */ IC_64BIT_REXW_XS, /* 14891 */ IC_XD_ADSIZE, /* 14892 */ IC_64BIT_REXW_XD, /* 14893 */ IC_XS_ADSIZE, /* 14894 */ IC_64BIT_REXW_XS, /* 14895 */ IC_OPSIZE_ADSIZE, /* 14896 */ IC_64BIT_OPSIZE_ADSIZE, /* 14897 */ IC_XS_OPSIZE, /* 14898 */ IC_64BIT_XS_OPSIZE, /* 14899 */ IC_XD_OPSIZE, /* 14900 */ IC_64BIT_XD_OPSIZE, /* 14901 */ IC_XS_OPSIZE, /* 14902 */ IC_64BIT_XD_OPSIZE, /* 14903 */ IC_OPSIZE_ADSIZE, /* 14904 */ IC_64BIT_REXW_OPSIZE, /* 14905 */ IC_XS_OPSIZE, /* 14906 */ IC_64BIT_REXW_XS, /* 14907 */ IC_XD_OPSIZE, /* 14908 */ IC_64BIT_REXW_XD, /* 14909 */ IC_XS_OPSIZE, /* 14910 */ IC_64BIT_REXW_XS, /* 14911 */ IC_VEX, /* 14912 */ IC_VEX, /* 14913 */ IC_VEX_XS, /* 14914 */ IC_VEX_XS, /* 14915 */ IC_VEX_XD, /* 14916 */ IC_VEX_XD, /* 14917 */ IC_VEX_XD, /* 14918 */ IC_VEX_XD, /* 14919 */ IC_VEX_W, /* 14920 */ IC_VEX_W, /* 14921 */ IC_VEX_W_XS, /* 14922 */ IC_VEX_W_XS, /* 14923 */ IC_VEX_W_XD, /* 14924 */ IC_VEX_W_XD, /* 14925 */ IC_VEX_W_XD, /* 14926 */ IC_VEX_W_XD, /* 14927 */ IC_VEX_OPSIZE, /* 14928 */ IC_VEX_OPSIZE, /* 14929 */ IC_VEX_OPSIZE, /* 14930 */ IC_VEX_OPSIZE, /* 14931 */ IC_VEX_OPSIZE, /* 14932 */ IC_VEX_OPSIZE, /* 14933 */ IC_VEX_OPSIZE, /* 14934 */ IC_VEX_OPSIZE, /* 14935 */ IC_VEX_W_OPSIZE, /* 14936 */ IC_VEX_W_OPSIZE, /* 14937 */ IC_VEX_W_OPSIZE, /* 14938 */ IC_VEX_W_OPSIZE, /* 14939 */ IC_VEX_W_OPSIZE, /* 14940 */ IC_VEX_W_OPSIZE, /* 14941 */ IC_VEX_W_OPSIZE, /* 14942 */ IC_VEX_W_OPSIZE, /* 14943 */ IC_VEX, /* 14944 */ IC_VEX, /* 14945 */ IC_VEX_XS, /* 14946 */ IC_VEX_XS, /* 14947 */ IC_VEX_XD, /* 14948 */ IC_VEX_XD, /* 14949 */ IC_VEX_XD, /* 14950 */ IC_VEX_XD, /* 14951 */ IC_VEX_W, /* 14952 */ IC_VEX_W, /* 14953 */ IC_VEX_W_XS, /* 14954 */ IC_VEX_W_XS, /* 14955 */ IC_VEX_W_XD, /* 14956 */ IC_VEX_W_XD, /* 14957 */ IC_VEX_W_XD, /* 14958 */ IC_VEX_W_XD, /* 14959 */ IC_VEX_OPSIZE, /* 14960 */ IC_VEX_OPSIZE, /* 14961 */ IC_VEX_OPSIZE, /* 14962 */ IC_VEX_OPSIZE, /* 14963 */ IC_VEX_OPSIZE, /* 14964 */ IC_VEX_OPSIZE, /* 14965 */ IC_VEX_OPSIZE, /* 14966 */ IC_VEX_OPSIZE, /* 14967 */ IC_VEX_W_OPSIZE, /* 14968 */ IC_VEX_W_OPSIZE, /* 14969 */ IC_VEX_W_OPSIZE, /* 14970 */ IC_VEX_W_OPSIZE, /* 14971 */ IC_VEX_W_OPSIZE, /* 14972 */ IC_VEX_W_OPSIZE, /* 14973 */ IC_VEX_W_OPSIZE, /* 14974 */ IC_VEX_W_OPSIZE, /* 14975 */ IC_VEX_L, /* 14976 */ IC_VEX_L, /* 14977 */ IC_VEX_L_XS, /* 14978 */ IC_VEX_L_XS, /* 14979 */ IC_VEX_L_XD, /* 14980 */ IC_VEX_L_XD, /* 14981 */ IC_VEX_L_XD, /* 14982 */ IC_VEX_L_XD, /* 14983 */ IC_VEX_L_W, /* 14984 */ IC_VEX_L_W, /* 14985 */ IC_VEX_L_W_XS, /* 14986 */ IC_VEX_L_W_XS, /* 14987 */ IC_VEX_L_W_XD, /* 14988 */ IC_VEX_L_W_XD, /* 14989 */ IC_VEX_L_W_XD, /* 14990 */ IC_VEX_L_W_XD, /* 14991 */ IC_VEX_L_OPSIZE, /* 14992 */ IC_VEX_L_OPSIZE, /* 14993 */ IC_VEX_L_OPSIZE, /* 14994 */ IC_VEX_L_OPSIZE, /* 14995 */ IC_VEX_L_OPSIZE, /* 14996 */ IC_VEX_L_OPSIZE, /* 14997 */ IC_VEX_L_OPSIZE, /* 14998 */ IC_VEX_L_OPSIZE, /* 14999 */ IC_VEX_L_W_OPSIZE, /* 15000 */ IC_VEX_L_W_OPSIZE, /* 15001 */ IC_VEX_L_W_OPSIZE, /* 15002 */ IC_VEX_L_W_OPSIZE, /* 15003 */ IC_VEX_L_W_OPSIZE, /* 15004 */ IC_VEX_L_W_OPSIZE, /* 15005 */ IC_VEX_L_W_OPSIZE, /* 15006 */ IC_VEX_L_W_OPSIZE, /* 15007 */ IC_VEX_L, /* 15008 */ IC_VEX_L, /* 15009 */ IC_VEX_L_XS, /* 15010 */ IC_VEX_L_XS, /* 15011 */ IC_VEX_L_XD, /* 15012 */ IC_VEX_L_XD, /* 15013 */ IC_VEX_L_XD, /* 15014 */ IC_VEX_L_XD, /* 15015 */ IC_VEX_L_W, /* 15016 */ IC_VEX_L_W, /* 15017 */ IC_VEX_L_W_XS, /* 15018 */ IC_VEX_L_W_XS, /* 15019 */ IC_VEX_L_W_XD, /* 15020 */ IC_VEX_L_W_XD, /* 15021 */ IC_VEX_L_W_XD, /* 15022 */ IC_VEX_L_W_XD, /* 15023 */ IC_VEX_L_OPSIZE, /* 15024 */ IC_VEX_L_OPSIZE, /* 15025 */ IC_VEX_L_OPSIZE, /* 15026 */ IC_VEX_L_OPSIZE, /* 15027 */ IC_VEX_L_OPSIZE, /* 15028 */ IC_VEX_L_OPSIZE, /* 15029 */ IC_VEX_L_OPSIZE, /* 15030 */ IC_VEX_L_OPSIZE, /* 15031 */ IC_VEX_L_W_OPSIZE, /* 15032 */ IC_VEX_L_W_OPSIZE, /* 15033 */ IC_VEX_L_W_OPSIZE, /* 15034 */ IC_VEX_L_W_OPSIZE, /* 15035 */ IC_VEX_L_W_OPSIZE, /* 15036 */ IC_VEX_L_W_OPSIZE, /* 15037 */ IC_VEX_L_W_OPSIZE, /* 15038 */ IC_VEX_L_W_OPSIZE, /* 15039 */ IC_VEX_L, /* 15040 */ IC_VEX_L, /* 15041 */ IC_VEX_L_XS, /* 15042 */ IC_VEX_L_XS, /* 15043 */ IC_VEX_L_XD, /* 15044 */ IC_VEX_L_XD, /* 15045 */ IC_VEX_L_XD, /* 15046 */ IC_VEX_L_XD, /* 15047 */ IC_VEX_L_W, /* 15048 */ IC_VEX_L_W, /* 15049 */ IC_VEX_L_W_XS, /* 15050 */ IC_VEX_L_W_XS, /* 15051 */ IC_VEX_L_W_XD, /* 15052 */ IC_VEX_L_W_XD, /* 15053 */ IC_VEX_L_W_XD, /* 15054 */ IC_VEX_L_W_XD, /* 15055 */ IC_VEX_L_OPSIZE, /* 15056 */ IC_VEX_L_OPSIZE, /* 15057 */ IC_VEX_L_OPSIZE, /* 15058 */ IC_VEX_L_OPSIZE, /* 15059 */ IC_VEX_L_OPSIZE, /* 15060 */ IC_VEX_L_OPSIZE, /* 15061 */ IC_VEX_L_OPSIZE, /* 15062 */ IC_VEX_L_OPSIZE, /* 15063 */ IC_VEX_L_W_OPSIZE, /* 15064 */ IC_VEX_L_W_OPSIZE, /* 15065 */ IC_VEX_L_W_OPSIZE, /* 15066 */ IC_VEX_L_W_OPSIZE, /* 15067 */ IC_VEX_L_W_OPSIZE, /* 15068 */ IC_VEX_L_W_OPSIZE, /* 15069 */ IC_VEX_L_W_OPSIZE, /* 15070 */ IC_VEX_L_W_OPSIZE, /* 15071 */ IC_VEX_L, /* 15072 */ IC_VEX_L, /* 15073 */ IC_VEX_L_XS, /* 15074 */ IC_VEX_L_XS, /* 15075 */ IC_VEX_L_XD, /* 15076 */ IC_VEX_L_XD, /* 15077 */ IC_VEX_L_XD, /* 15078 */ IC_VEX_L_XD, /* 15079 */ IC_VEX_L_W, /* 15080 */ IC_VEX_L_W, /* 15081 */ IC_VEX_L_W_XS, /* 15082 */ IC_VEX_L_W_XS, /* 15083 */ IC_VEX_L_W_XD, /* 15084 */ IC_VEX_L_W_XD, /* 15085 */ IC_VEX_L_W_XD, /* 15086 */ IC_VEX_L_W_XD, /* 15087 */ IC_VEX_L_OPSIZE, /* 15088 */ IC_VEX_L_OPSIZE, /* 15089 */ IC_VEX_L_OPSIZE, /* 15090 */ IC_VEX_L_OPSIZE, /* 15091 */ IC_VEX_L_OPSIZE, /* 15092 */ IC_VEX_L_OPSIZE, /* 15093 */ IC_VEX_L_OPSIZE, /* 15094 */ IC_VEX_L_OPSIZE, /* 15095 */ IC_VEX_L_W_OPSIZE, /* 15096 */ IC_VEX_L_W_OPSIZE, /* 15097 */ IC_VEX_L_W_OPSIZE, /* 15098 */ IC_VEX_L_W_OPSIZE, /* 15099 */ IC_VEX_L_W_OPSIZE, /* 15100 */ IC_VEX_L_W_OPSIZE, /* 15101 */ IC_VEX_L_W_OPSIZE, /* 15102 */ IC_VEX_L_W_OPSIZE, /* 15103 */ IC_EVEX_L_KZ_B, /* 15104 */ IC_EVEX_L_KZ_B, /* 15105 */ IC_EVEX_L_XS_KZ_B, /* 15106 */ IC_EVEX_L_XS_KZ_B, /* 15107 */ IC_EVEX_L_XD_KZ_B, /* 15108 */ IC_EVEX_L_XD_KZ_B, /* 15109 */ IC_EVEX_L_XD_KZ_B, /* 15110 */ IC_EVEX_L_XD_KZ_B, /* 15111 */ IC_EVEX_L_W_KZ_B, /* 15112 */ IC_EVEX_L_W_KZ_B, /* 15113 */ IC_EVEX_L_W_XS_KZ_B, /* 15114 */ IC_EVEX_L_W_XS_KZ_B, /* 15115 */ IC_EVEX_L_W_XD_KZ_B, /* 15116 */ IC_EVEX_L_W_XD_KZ_B, /* 15117 */ IC_EVEX_L_W_XD_KZ_B, /* 15118 */ IC_EVEX_L_W_XD_KZ_B, /* 15119 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15120 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15121 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15122 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15123 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15124 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15125 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15126 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15127 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15128 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15129 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15130 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15131 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15132 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15133 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15134 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15135 */ IC_EVEX_L_KZ_B, /* 15136 */ IC_EVEX_L_KZ_B, /* 15137 */ IC_EVEX_L_XS_KZ_B, /* 15138 */ IC_EVEX_L_XS_KZ_B, /* 15139 */ IC_EVEX_L_XD_KZ_B, /* 15140 */ IC_EVEX_L_XD_KZ_B, /* 15141 */ IC_EVEX_L_XD_KZ_B, /* 15142 */ IC_EVEX_L_XD_KZ_B, /* 15143 */ IC_EVEX_L_W_KZ_B, /* 15144 */ IC_EVEX_L_W_KZ_B, /* 15145 */ IC_EVEX_L_W_XS_KZ_B, /* 15146 */ IC_EVEX_L_W_XS_KZ_B, /* 15147 */ IC_EVEX_L_W_XD_KZ_B, /* 15148 */ IC_EVEX_L_W_XD_KZ_B, /* 15149 */ IC_EVEX_L_W_XD_KZ_B, /* 15150 */ IC_EVEX_L_W_XD_KZ_B, /* 15151 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15152 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15153 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15154 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15155 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15156 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15157 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15158 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15159 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15160 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15161 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15162 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15163 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15164 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15165 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15166 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15167 */ IC_EVEX_L_KZ_B, /* 15168 */ IC_EVEX_L_KZ_B, /* 15169 */ IC_EVEX_L_XS_KZ_B, /* 15170 */ IC_EVEX_L_XS_KZ_B, /* 15171 */ IC_EVEX_L_XD_KZ_B, /* 15172 */ IC_EVEX_L_XD_KZ_B, /* 15173 */ IC_EVEX_L_XD_KZ_B, /* 15174 */ IC_EVEX_L_XD_KZ_B, /* 15175 */ IC_EVEX_L_W_KZ_B, /* 15176 */ IC_EVEX_L_W_KZ_B, /* 15177 */ IC_EVEX_L_W_XS_KZ_B, /* 15178 */ IC_EVEX_L_W_XS_KZ_B, /* 15179 */ IC_EVEX_L_W_XD_KZ_B, /* 15180 */ IC_EVEX_L_W_XD_KZ_B, /* 15181 */ IC_EVEX_L_W_XD_KZ_B, /* 15182 */ IC_EVEX_L_W_XD_KZ_B, /* 15183 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15184 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15185 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15186 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15187 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15188 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15189 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15190 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15191 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15192 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15193 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15194 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15195 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15196 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15197 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15198 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15199 */ IC_EVEX_L_KZ_B, /* 15200 */ IC_EVEX_L_KZ_B, /* 15201 */ IC_EVEX_L_XS_KZ_B, /* 15202 */ IC_EVEX_L_XS_KZ_B, /* 15203 */ IC_EVEX_L_XD_KZ_B, /* 15204 */ IC_EVEX_L_XD_KZ_B, /* 15205 */ IC_EVEX_L_XD_KZ_B, /* 15206 */ IC_EVEX_L_XD_KZ_B, /* 15207 */ IC_EVEX_L_W_KZ_B, /* 15208 */ IC_EVEX_L_W_KZ_B, /* 15209 */ IC_EVEX_L_W_XS_KZ_B, /* 15210 */ IC_EVEX_L_W_XS_KZ_B, /* 15211 */ IC_EVEX_L_W_XD_KZ_B, /* 15212 */ IC_EVEX_L_W_XD_KZ_B, /* 15213 */ IC_EVEX_L_W_XD_KZ_B, /* 15214 */ IC_EVEX_L_W_XD_KZ_B, /* 15215 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15216 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15217 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15218 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15219 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15220 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15221 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15222 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15223 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15224 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15225 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15226 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15227 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15228 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15229 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15230 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15231 */ IC_EVEX_L_KZ_B, /* 15232 */ IC_EVEX_L_KZ_B, /* 15233 */ IC_EVEX_L_XS_KZ_B, /* 15234 */ IC_EVEX_L_XS_KZ_B, /* 15235 */ IC_EVEX_L_XD_KZ_B, /* 15236 */ IC_EVEX_L_XD_KZ_B, /* 15237 */ IC_EVEX_L_XD_KZ_B, /* 15238 */ IC_EVEX_L_XD_KZ_B, /* 15239 */ IC_EVEX_L_W_KZ_B, /* 15240 */ IC_EVEX_L_W_KZ_B, /* 15241 */ IC_EVEX_L_W_XS_KZ_B, /* 15242 */ IC_EVEX_L_W_XS_KZ_B, /* 15243 */ IC_EVEX_L_W_XD_KZ_B, /* 15244 */ IC_EVEX_L_W_XD_KZ_B, /* 15245 */ IC_EVEX_L_W_XD_KZ_B, /* 15246 */ IC_EVEX_L_W_XD_KZ_B, /* 15247 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15248 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15249 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15250 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15251 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15252 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15253 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15254 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15255 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15256 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15257 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15258 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15259 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15260 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15261 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15262 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15263 */ IC_EVEX_L_KZ_B, /* 15264 */ IC_EVEX_L_KZ_B, /* 15265 */ IC_EVEX_L_XS_KZ_B, /* 15266 */ IC_EVEX_L_XS_KZ_B, /* 15267 */ IC_EVEX_L_XD_KZ_B, /* 15268 */ IC_EVEX_L_XD_KZ_B, /* 15269 */ IC_EVEX_L_XD_KZ_B, /* 15270 */ IC_EVEX_L_XD_KZ_B, /* 15271 */ IC_EVEX_L_W_KZ_B, /* 15272 */ IC_EVEX_L_W_KZ_B, /* 15273 */ IC_EVEX_L_W_XS_KZ_B, /* 15274 */ IC_EVEX_L_W_XS_KZ_B, /* 15275 */ IC_EVEX_L_W_XD_KZ_B, /* 15276 */ IC_EVEX_L_W_XD_KZ_B, /* 15277 */ IC_EVEX_L_W_XD_KZ_B, /* 15278 */ IC_EVEX_L_W_XD_KZ_B, /* 15279 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15280 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15281 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15282 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15283 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15284 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15285 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15286 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15287 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15288 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15289 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15290 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15291 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15292 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15293 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15294 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15295 */ IC_EVEX_L_KZ_B, /* 15296 */ IC_EVEX_L_KZ_B, /* 15297 */ IC_EVEX_L_XS_KZ_B, /* 15298 */ IC_EVEX_L_XS_KZ_B, /* 15299 */ IC_EVEX_L_XD_KZ_B, /* 15300 */ IC_EVEX_L_XD_KZ_B, /* 15301 */ IC_EVEX_L_XD_KZ_B, /* 15302 */ IC_EVEX_L_XD_KZ_B, /* 15303 */ IC_EVEX_L_W_KZ_B, /* 15304 */ IC_EVEX_L_W_KZ_B, /* 15305 */ IC_EVEX_L_W_XS_KZ_B, /* 15306 */ IC_EVEX_L_W_XS_KZ_B, /* 15307 */ IC_EVEX_L_W_XD_KZ_B, /* 15308 */ IC_EVEX_L_W_XD_KZ_B, /* 15309 */ IC_EVEX_L_W_XD_KZ_B, /* 15310 */ IC_EVEX_L_W_XD_KZ_B, /* 15311 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15312 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15313 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15314 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15315 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15316 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15317 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15318 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15319 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15320 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15321 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15322 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15323 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15324 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15325 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15326 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15327 */ IC_EVEX_L_KZ_B, /* 15328 */ IC_EVEX_L_KZ_B, /* 15329 */ IC_EVEX_L_XS_KZ_B, /* 15330 */ IC_EVEX_L_XS_KZ_B, /* 15331 */ IC_EVEX_L_XD_KZ_B, /* 15332 */ IC_EVEX_L_XD_KZ_B, /* 15333 */ IC_EVEX_L_XD_KZ_B, /* 15334 */ IC_EVEX_L_XD_KZ_B, /* 15335 */ IC_EVEX_L_W_KZ_B, /* 15336 */ IC_EVEX_L_W_KZ_B, /* 15337 */ IC_EVEX_L_W_XS_KZ_B, /* 15338 */ IC_EVEX_L_W_XS_KZ_B, /* 15339 */ IC_EVEX_L_W_XD_KZ_B, /* 15340 */ IC_EVEX_L_W_XD_KZ_B, /* 15341 */ IC_EVEX_L_W_XD_KZ_B, /* 15342 */ IC_EVEX_L_W_XD_KZ_B, /* 15343 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15344 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15345 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15346 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15347 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15348 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15349 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15350 */ IC_EVEX_L_OPSIZE_KZ_B, /* 15351 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15352 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15353 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15354 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15355 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15356 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15357 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15358 */ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15359 */ IC, /* 15360 */ IC_64BIT, /* 15361 */ IC_XS, /* 15362 */ IC_64BIT_XS, /* 15363 */ IC_XD, /* 15364 */ IC_64BIT_XD, /* 15365 */ IC_XS, /* 15366 */ IC_64BIT_XS, /* 15367 */ IC, /* 15368 */ IC_64BIT_REXW, /* 15369 */ IC_XS, /* 15370 */ IC_64BIT_REXW_XS, /* 15371 */ IC_XD, /* 15372 */ IC_64BIT_REXW_XD, /* 15373 */ IC_XS, /* 15374 */ IC_64BIT_REXW_XS, /* 15375 */ IC_OPSIZE, /* 15376 */ IC_64BIT_OPSIZE, /* 15377 */ IC_XS_OPSIZE, /* 15378 */ IC_64BIT_XS_OPSIZE, /* 15379 */ IC_XD_OPSIZE, /* 15380 */ IC_64BIT_XD_OPSIZE, /* 15381 */ IC_XS_OPSIZE, /* 15382 */ IC_64BIT_XD_OPSIZE, /* 15383 */ IC_OPSIZE, /* 15384 */ IC_64BIT_REXW_OPSIZE, /* 15385 */ IC_XS_OPSIZE, /* 15386 */ IC_64BIT_REXW_XS, /* 15387 */ IC_XD_OPSIZE, /* 15388 */ IC_64BIT_REXW_XD, /* 15389 */ IC_XS_OPSIZE, /* 15390 */ IC_64BIT_REXW_XS, /* 15391 */ IC_ADSIZE, /* 15392 */ IC_64BIT_ADSIZE, /* 15393 */ IC_XS_ADSIZE, /* 15394 */ IC_64BIT_XS_ADSIZE, /* 15395 */ IC_XD_ADSIZE, /* 15396 */ IC_64BIT_XD_ADSIZE, /* 15397 */ IC_XS_ADSIZE, /* 15398 */ IC_64BIT_XD_ADSIZE, /* 15399 */ IC_ADSIZE, /* 15400 */ IC_64BIT_REXW_ADSIZE, /* 15401 */ IC_XS_ADSIZE, /* 15402 */ IC_64BIT_REXW_XS, /* 15403 */ IC_XD_ADSIZE, /* 15404 */ IC_64BIT_REXW_XD, /* 15405 */ IC_XS_ADSIZE, /* 15406 */ IC_64BIT_REXW_XS, /* 15407 */ IC_OPSIZE_ADSIZE, /* 15408 */ IC_64BIT_OPSIZE_ADSIZE, /* 15409 */ IC_XS_OPSIZE, /* 15410 */ IC_64BIT_XS_OPSIZE, /* 15411 */ IC_XD_OPSIZE, /* 15412 */ IC_64BIT_XD_OPSIZE, /* 15413 */ IC_XS_OPSIZE, /* 15414 */ IC_64BIT_XD_OPSIZE, /* 15415 */ IC_OPSIZE_ADSIZE, /* 15416 */ IC_64BIT_REXW_OPSIZE, /* 15417 */ IC_XS_OPSIZE, /* 15418 */ IC_64BIT_REXW_XS, /* 15419 */ IC_XD_OPSIZE, /* 15420 */ IC_64BIT_REXW_XD, /* 15421 */ IC_XS_OPSIZE, /* 15422 */ IC_64BIT_REXW_XS, /* 15423 */ IC_VEX, /* 15424 */ IC_VEX, /* 15425 */ IC_VEX_XS, /* 15426 */ IC_VEX_XS, /* 15427 */ IC_VEX_XD, /* 15428 */ IC_VEX_XD, /* 15429 */ IC_VEX_XD, /* 15430 */ IC_VEX_XD, /* 15431 */ IC_VEX_W, /* 15432 */ IC_VEX_W, /* 15433 */ IC_VEX_W_XS, /* 15434 */ IC_VEX_W_XS, /* 15435 */ IC_VEX_W_XD, /* 15436 */ IC_VEX_W_XD, /* 15437 */ IC_VEX_W_XD, /* 15438 */ IC_VEX_W_XD, /* 15439 */ IC_VEX_OPSIZE, /* 15440 */ IC_VEX_OPSIZE, /* 15441 */ IC_VEX_OPSIZE, /* 15442 */ IC_VEX_OPSIZE, /* 15443 */ IC_VEX_OPSIZE, /* 15444 */ IC_VEX_OPSIZE, /* 15445 */ IC_VEX_OPSIZE, /* 15446 */ IC_VEX_OPSIZE, /* 15447 */ IC_VEX_W_OPSIZE, /* 15448 */ IC_VEX_W_OPSIZE, /* 15449 */ IC_VEX_W_OPSIZE, /* 15450 */ IC_VEX_W_OPSIZE, /* 15451 */ IC_VEX_W_OPSIZE, /* 15452 */ IC_VEX_W_OPSIZE, /* 15453 */ IC_VEX_W_OPSIZE, /* 15454 */ IC_VEX_W_OPSIZE, /* 15455 */ IC_VEX, /* 15456 */ IC_VEX, /* 15457 */ IC_VEX_XS, /* 15458 */ IC_VEX_XS, /* 15459 */ IC_VEX_XD, /* 15460 */ IC_VEX_XD, /* 15461 */ IC_VEX_XD, /* 15462 */ IC_VEX_XD, /* 15463 */ IC_VEX_W, /* 15464 */ IC_VEX_W, /* 15465 */ IC_VEX_W_XS, /* 15466 */ IC_VEX_W_XS, /* 15467 */ IC_VEX_W_XD, /* 15468 */ IC_VEX_W_XD, /* 15469 */ IC_VEX_W_XD, /* 15470 */ IC_VEX_W_XD, /* 15471 */ IC_VEX_OPSIZE, /* 15472 */ IC_VEX_OPSIZE, /* 15473 */ IC_VEX_OPSIZE, /* 15474 */ IC_VEX_OPSIZE, /* 15475 */ IC_VEX_OPSIZE, /* 15476 */ IC_VEX_OPSIZE, /* 15477 */ IC_VEX_OPSIZE, /* 15478 */ IC_VEX_OPSIZE, /* 15479 */ IC_VEX_W_OPSIZE, /* 15480 */ IC_VEX_W_OPSIZE, /* 15481 */ IC_VEX_W_OPSIZE, /* 15482 */ IC_VEX_W_OPSIZE, /* 15483 */ IC_VEX_W_OPSIZE, /* 15484 */ IC_VEX_W_OPSIZE, /* 15485 */ IC_VEX_W_OPSIZE, /* 15486 */ IC_VEX_W_OPSIZE, /* 15487 */ IC_VEX_L, /* 15488 */ IC_VEX_L, /* 15489 */ IC_VEX_L_XS, /* 15490 */ IC_VEX_L_XS, /* 15491 */ IC_VEX_L_XD, /* 15492 */ IC_VEX_L_XD, /* 15493 */ IC_VEX_L_XD, /* 15494 */ IC_VEX_L_XD, /* 15495 */ IC_VEX_L_W, /* 15496 */ IC_VEX_L_W, /* 15497 */ IC_VEX_L_W_XS, /* 15498 */ IC_VEX_L_W_XS, /* 15499 */ IC_VEX_L_W_XD, /* 15500 */ IC_VEX_L_W_XD, /* 15501 */ IC_VEX_L_W_XD, /* 15502 */ IC_VEX_L_W_XD, /* 15503 */ IC_VEX_L_OPSIZE, /* 15504 */ IC_VEX_L_OPSIZE, /* 15505 */ IC_VEX_L_OPSIZE, /* 15506 */ IC_VEX_L_OPSIZE, /* 15507 */ IC_VEX_L_OPSIZE, /* 15508 */ IC_VEX_L_OPSIZE, /* 15509 */ IC_VEX_L_OPSIZE, /* 15510 */ IC_VEX_L_OPSIZE, /* 15511 */ IC_VEX_L_W_OPSIZE, /* 15512 */ IC_VEX_L_W_OPSIZE, /* 15513 */ IC_VEX_L_W_OPSIZE, /* 15514 */ IC_VEX_L_W_OPSIZE, /* 15515 */ IC_VEX_L_W_OPSIZE, /* 15516 */ IC_VEX_L_W_OPSIZE, /* 15517 */ IC_VEX_L_W_OPSIZE, /* 15518 */ IC_VEX_L_W_OPSIZE, /* 15519 */ IC_VEX_L, /* 15520 */ IC_VEX_L, /* 15521 */ IC_VEX_L_XS, /* 15522 */ IC_VEX_L_XS, /* 15523 */ IC_VEX_L_XD, /* 15524 */ IC_VEX_L_XD, /* 15525 */ IC_VEX_L_XD, /* 15526 */ IC_VEX_L_XD, /* 15527 */ IC_VEX_L_W, /* 15528 */ IC_VEX_L_W, /* 15529 */ IC_VEX_L_W_XS, /* 15530 */ IC_VEX_L_W_XS, /* 15531 */ IC_VEX_L_W_XD, /* 15532 */ IC_VEX_L_W_XD, /* 15533 */ IC_VEX_L_W_XD, /* 15534 */ IC_VEX_L_W_XD, /* 15535 */ IC_VEX_L_OPSIZE, /* 15536 */ IC_VEX_L_OPSIZE, /* 15537 */ IC_VEX_L_OPSIZE, /* 15538 */ IC_VEX_L_OPSIZE, /* 15539 */ IC_VEX_L_OPSIZE, /* 15540 */ IC_VEX_L_OPSIZE, /* 15541 */ IC_VEX_L_OPSIZE, /* 15542 */ IC_VEX_L_OPSIZE, /* 15543 */ IC_VEX_L_W_OPSIZE, /* 15544 */ IC_VEX_L_W_OPSIZE, /* 15545 */ IC_VEX_L_W_OPSIZE, /* 15546 */ IC_VEX_L_W_OPSIZE, /* 15547 */ IC_VEX_L_W_OPSIZE, /* 15548 */ IC_VEX_L_W_OPSIZE, /* 15549 */ IC_VEX_L_W_OPSIZE, /* 15550 */ IC_VEX_L_W_OPSIZE, /* 15551 */ IC_VEX_L, /* 15552 */ IC_VEX_L, /* 15553 */ IC_VEX_L_XS, /* 15554 */ IC_VEX_L_XS, /* 15555 */ IC_VEX_L_XD, /* 15556 */ IC_VEX_L_XD, /* 15557 */ IC_VEX_L_XD, /* 15558 */ IC_VEX_L_XD, /* 15559 */ IC_VEX_L_W, /* 15560 */ IC_VEX_L_W, /* 15561 */ IC_VEX_L_W_XS, /* 15562 */ IC_VEX_L_W_XS, /* 15563 */ IC_VEX_L_W_XD, /* 15564 */ IC_VEX_L_W_XD, /* 15565 */ IC_VEX_L_W_XD, /* 15566 */ IC_VEX_L_W_XD, /* 15567 */ IC_VEX_L_OPSIZE, /* 15568 */ IC_VEX_L_OPSIZE, /* 15569 */ IC_VEX_L_OPSIZE, /* 15570 */ IC_VEX_L_OPSIZE, /* 15571 */ IC_VEX_L_OPSIZE, /* 15572 */ IC_VEX_L_OPSIZE, /* 15573 */ IC_VEX_L_OPSIZE, /* 15574 */ IC_VEX_L_OPSIZE, /* 15575 */ IC_VEX_L_W_OPSIZE, /* 15576 */ IC_VEX_L_W_OPSIZE, /* 15577 */ IC_VEX_L_W_OPSIZE, /* 15578 */ IC_VEX_L_W_OPSIZE, /* 15579 */ IC_VEX_L_W_OPSIZE, /* 15580 */ IC_VEX_L_W_OPSIZE, /* 15581 */ IC_VEX_L_W_OPSIZE, /* 15582 */ IC_VEX_L_W_OPSIZE, /* 15583 */ IC_VEX_L, /* 15584 */ IC_VEX_L, /* 15585 */ IC_VEX_L_XS, /* 15586 */ IC_VEX_L_XS, /* 15587 */ IC_VEX_L_XD, /* 15588 */ IC_VEX_L_XD, /* 15589 */ IC_VEX_L_XD, /* 15590 */ IC_VEX_L_XD, /* 15591 */ IC_VEX_L_W, /* 15592 */ IC_VEX_L_W, /* 15593 */ IC_VEX_L_W_XS, /* 15594 */ IC_VEX_L_W_XS, /* 15595 */ IC_VEX_L_W_XD, /* 15596 */ IC_VEX_L_W_XD, /* 15597 */ IC_VEX_L_W_XD, /* 15598 */ IC_VEX_L_W_XD, /* 15599 */ IC_VEX_L_OPSIZE, /* 15600 */ IC_VEX_L_OPSIZE, /* 15601 */ IC_VEX_L_OPSIZE, /* 15602 */ IC_VEX_L_OPSIZE, /* 15603 */ IC_VEX_L_OPSIZE, /* 15604 */ IC_VEX_L_OPSIZE, /* 15605 */ IC_VEX_L_OPSIZE, /* 15606 */ IC_VEX_L_OPSIZE, /* 15607 */ IC_VEX_L_W_OPSIZE, /* 15608 */ IC_VEX_L_W_OPSIZE, /* 15609 */ IC_VEX_L_W_OPSIZE, /* 15610 */ IC_VEX_L_W_OPSIZE, /* 15611 */ IC_VEX_L_W_OPSIZE, /* 15612 */ IC_VEX_L_W_OPSIZE, /* 15613 */ IC_VEX_L_W_OPSIZE, /* 15614 */ IC_VEX_L_W_OPSIZE, /* 15615 */ IC_EVEX_L2_KZ_B, /* 15616 */ IC_EVEX_L2_KZ_B, /* 15617 */ IC_EVEX_L2_XS_KZ_B, /* 15618 */ IC_EVEX_L2_XS_KZ_B, /* 15619 */ IC_EVEX_L2_XD_KZ_B, /* 15620 */ IC_EVEX_L2_XD_KZ_B, /* 15621 */ IC_EVEX_L2_XD_KZ_B, /* 15622 */ IC_EVEX_L2_XD_KZ_B, /* 15623 */ IC_EVEX_L2_W_KZ_B, /* 15624 */ IC_EVEX_L2_W_KZ_B, /* 15625 */ IC_EVEX_L2_W_XS_KZ_B, /* 15626 */ IC_EVEX_L2_W_XS_KZ_B, /* 15627 */ IC_EVEX_L2_W_XD_KZ_B, /* 15628 */ IC_EVEX_L2_W_XD_KZ_B, /* 15629 */ IC_EVEX_L2_W_XD_KZ_B, /* 15630 */ IC_EVEX_L2_W_XD_KZ_B, /* 15631 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15632 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15633 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15634 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15635 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15636 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15637 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15638 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15639 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15640 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15641 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15642 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15643 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15644 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15645 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15646 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15647 */ IC_EVEX_L2_KZ_B, /* 15648 */ IC_EVEX_L2_KZ_B, /* 15649 */ IC_EVEX_L2_XS_KZ_B, /* 15650 */ IC_EVEX_L2_XS_KZ_B, /* 15651 */ IC_EVEX_L2_XD_KZ_B, /* 15652 */ IC_EVEX_L2_XD_KZ_B, /* 15653 */ IC_EVEX_L2_XD_KZ_B, /* 15654 */ IC_EVEX_L2_XD_KZ_B, /* 15655 */ IC_EVEX_L2_W_KZ_B, /* 15656 */ IC_EVEX_L2_W_KZ_B, /* 15657 */ IC_EVEX_L2_W_XS_KZ_B, /* 15658 */ IC_EVEX_L2_W_XS_KZ_B, /* 15659 */ IC_EVEX_L2_W_XD_KZ_B, /* 15660 */ IC_EVEX_L2_W_XD_KZ_B, /* 15661 */ IC_EVEX_L2_W_XD_KZ_B, /* 15662 */ IC_EVEX_L2_W_XD_KZ_B, /* 15663 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15664 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15665 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15666 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15667 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15668 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15669 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15670 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15671 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15672 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15673 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15674 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15675 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15676 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15677 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15678 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15679 */ IC_EVEX_L2_KZ_B, /* 15680 */ IC_EVEX_L2_KZ_B, /* 15681 */ IC_EVEX_L2_XS_KZ_B, /* 15682 */ IC_EVEX_L2_XS_KZ_B, /* 15683 */ IC_EVEX_L2_XD_KZ_B, /* 15684 */ IC_EVEX_L2_XD_KZ_B, /* 15685 */ IC_EVEX_L2_XD_KZ_B, /* 15686 */ IC_EVEX_L2_XD_KZ_B, /* 15687 */ IC_EVEX_L2_W_KZ_B, /* 15688 */ IC_EVEX_L2_W_KZ_B, /* 15689 */ IC_EVEX_L2_W_XS_KZ_B, /* 15690 */ IC_EVEX_L2_W_XS_KZ_B, /* 15691 */ IC_EVEX_L2_W_XD_KZ_B, /* 15692 */ IC_EVEX_L2_W_XD_KZ_B, /* 15693 */ IC_EVEX_L2_W_XD_KZ_B, /* 15694 */ IC_EVEX_L2_W_XD_KZ_B, /* 15695 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15696 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15697 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15698 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15699 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15700 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15701 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15702 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15703 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15704 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15705 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15706 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15707 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15708 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15709 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15710 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15711 */ IC_EVEX_L2_KZ_B, /* 15712 */ IC_EVEX_L2_KZ_B, /* 15713 */ IC_EVEX_L2_XS_KZ_B, /* 15714 */ IC_EVEX_L2_XS_KZ_B, /* 15715 */ IC_EVEX_L2_XD_KZ_B, /* 15716 */ IC_EVEX_L2_XD_KZ_B, /* 15717 */ IC_EVEX_L2_XD_KZ_B, /* 15718 */ IC_EVEX_L2_XD_KZ_B, /* 15719 */ IC_EVEX_L2_W_KZ_B, /* 15720 */ IC_EVEX_L2_W_KZ_B, /* 15721 */ IC_EVEX_L2_W_XS_KZ_B, /* 15722 */ IC_EVEX_L2_W_XS_KZ_B, /* 15723 */ IC_EVEX_L2_W_XD_KZ_B, /* 15724 */ IC_EVEX_L2_W_XD_KZ_B, /* 15725 */ IC_EVEX_L2_W_XD_KZ_B, /* 15726 */ IC_EVEX_L2_W_XD_KZ_B, /* 15727 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15728 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15729 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15730 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15731 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15732 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15733 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15734 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15735 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15736 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15737 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15738 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15739 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15740 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15741 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15742 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15743 */ IC_EVEX_L2_KZ_B, /* 15744 */ IC_EVEX_L2_KZ_B, /* 15745 */ IC_EVEX_L2_XS_KZ_B, /* 15746 */ IC_EVEX_L2_XS_KZ_B, /* 15747 */ IC_EVEX_L2_XD_KZ_B, /* 15748 */ IC_EVEX_L2_XD_KZ_B, /* 15749 */ IC_EVEX_L2_XD_KZ_B, /* 15750 */ IC_EVEX_L2_XD_KZ_B, /* 15751 */ IC_EVEX_L2_W_KZ_B, /* 15752 */ IC_EVEX_L2_W_KZ_B, /* 15753 */ IC_EVEX_L2_W_XS_KZ_B, /* 15754 */ IC_EVEX_L2_W_XS_KZ_B, /* 15755 */ IC_EVEX_L2_W_XD_KZ_B, /* 15756 */ IC_EVEX_L2_W_XD_KZ_B, /* 15757 */ IC_EVEX_L2_W_XD_KZ_B, /* 15758 */ IC_EVEX_L2_W_XD_KZ_B, /* 15759 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15760 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15761 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15762 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15763 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15764 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15765 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15766 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15767 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15768 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15769 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15770 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15771 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15772 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15773 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15774 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15775 */ IC_EVEX_L2_KZ_B, /* 15776 */ IC_EVEX_L2_KZ_B, /* 15777 */ IC_EVEX_L2_XS_KZ_B, /* 15778 */ IC_EVEX_L2_XS_KZ_B, /* 15779 */ IC_EVEX_L2_XD_KZ_B, /* 15780 */ IC_EVEX_L2_XD_KZ_B, /* 15781 */ IC_EVEX_L2_XD_KZ_B, /* 15782 */ IC_EVEX_L2_XD_KZ_B, /* 15783 */ IC_EVEX_L2_W_KZ_B, /* 15784 */ IC_EVEX_L2_W_KZ_B, /* 15785 */ IC_EVEX_L2_W_XS_KZ_B, /* 15786 */ IC_EVEX_L2_W_XS_KZ_B, /* 15787 */ IC_EVEX_L2_W_XD_KZ_B, /* 15788 */ IC_EVEX_L2_W_XD_KZ_B, /* 15789 */ IC_EVEX_L2_W_XD_KZ_B, /* 15790 */ IC_EVEX_L2_W_XD_KZ_B, /* 15791 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15792 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15793 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15794 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15795 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15796 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15797 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15798 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15799 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15800 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15801 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15802 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15803 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15804 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15805 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15806 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15807 */ IC_EVEX_L2_KZ_B, /* 15808 */ IC_EVEX_L2_KZ_B, /* 15809 */ IC_EVEX_L2_XS_KZ_B, /* 15810 */ IC_EVEX_L2_XS_KZ_B, /* 15811 */ IC_EVEX_L2_XD_KZ_B, /* 15812 */ IC_EVEX_L2_XD_KZ_B, /* 15813 */ IC_EVEX_L2_XD_KZ_B, /* 15814 */ IC_EVEX_L2_XD_KZ_B, /* 15815 */ IC_EVEX_L2_W_KZ_B, /* 15816 */ IC_EVEX_L2_W_KZ_B, /* 15817 */ IC_EVEX_L2_W_XS_KZ_B, /* 15818 */ IC_EVEX_L2_W_XS_KZ_B, /* 15819 */ IC_EVEX_L2_W_XD_KZ_B, /* 15820 */ IC_EVEX_L2_W_XD_KZ_B, /* 15821 */ IC_EVEX_L2_W_XD_KZ_B, /* 15822 */ IC_EVEX_L2_W_XD_KZ_B, /* 15823 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15824 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15825 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15826 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15827 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15828 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15829 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15830 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15831 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15832 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15833 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15834 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15835 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15836 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15837 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15838 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15839 */ IC_EVEX_L2_KZ_B, /* 15840 */ IC_EVEX_L2_KZ_B, /* 15841 */ IC_EVEX_L2_XS_KZ_B, /* 15842 */ IC_EVEX_L2_XS_KZ_B, /* 15843 */ IC_EVEX_L2_XD_KZ_B, /* 15844 */ IC_EVEX_L2_XD_KZ_B, /* 15845 */ IC_EVEX_L2_XD_KZ_B, /* 15846 */ IC_EVEX_L2_XD_KZ_B, /* 15847 */ IC_EVEX_L2_W_KZ_B, /* 15848 */ IC_EVEX_L2_W_KZ_B, /* 15849 */ IC_EVEX_L2_W_XS_KZ_B, /* 15850 */ IC_EVEX_L2_W_XS_KZ_B, /* 15851 */ IC_EVEX_L2_W_XD_KZ_B, /* 15852 */ IC_EVEX_L2_W_XD_KZ_B, /* 15853 */ IC_EVEX_L2_W_XD_KZ_B, /* 15854 */ IC_EVEX_L2_W_XD_KZ_B, /* 15855 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15856 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15857 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15858 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15859 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15860 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15861 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15862 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 15863 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15864 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15865 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15866 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15867 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15868 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15869 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15870 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15871 */ IC, /* 15872 */ IC_64BIT, /* 15873 */ IC_XS, /* 15874 */ IC_64BIT_XS, /* 15875 */ IC_XD, /* 15876 */ IC_64BIT_XD, /* 15877 */ IC_XS, /* 15878 */ IC_64BIT_XS, /* 15879 */ IC, /* 15880 */ IC_64BIT_REXW, /* 15881 */ IC_XS, /* 15882 */ IC_64BIT_REXW_XS, /* 15883 */ IC_XD, /* 15884 */ IC_64BIT_REXW_XD, /* 15885 */ IC_XS, /* 15886 */ IC_64BIT_REXW_XS, /* 15887 */ IC_OPSIZE, /* 15888 */ IC_64BIT_OPSIZE, /* 15889 */ IC_XS_OPSIZE, /* 15890 */ IC_64BIT_XS_OPSIZE, /* 15891 */ IC_XD_OPSIZE, /* 15892 */ IC_64BIT_XD_OPSIZE, /* 15893 */ IC_XS_OPSIZE, /* 15894 */ IC_64BIT_XD_OPSIZE, /* 15895 */ IC_OPSIZE, /* 15896 */ IC_64BIT_REXW_OPSIZE, /* 15897 */ IC_XS_OPSIZE, /* 15898 */ IC_64BIT_REXW_XS, /* 15899 */ IC_XD_OPSIZE, /* 15900 */ IC_64BIT_REXW_XD, /* 15901 */ IC_XS_OPSIZE, /* 15902 */ IC_64BIT_REXW_XS, /* 15903 */ IC_ADSIZE, /* 15904 */ IC_64BIT_ADSIZE, /* 15905 */ IC_XS_ADSIZE, /* 15906 */ IC_64BIT_XS_ADSIZE, /* 15907 */ IC_XD_ADSIZE, /* 15908 */ IC_64BIT_XD_ADSIZE, /* 15909 */ IC_XS_ADSIZE, /* 15910 */ IC_64BIT_XD_ADSIZE, /* 15911 */ IC_ADSIZE, /* 15912 */ IC_64BIT_REXW_ADSIZE, /* 15913 */ IC_XS_ADSIZE, /* 15914 */ IC_64BIT_REXW_XS, /* 15915 */ IC_XD_ADSIZE, /* 15916 */ IC_64BIT_REXW_XD, /* 15917 */ IC_XS_ADSIZE, /* 15918 */ IC_64BIT_REXW_XS, /* 15919 */ IC_OPSIZE_ADSIZE, /* 15920 */ IC_64BIT_OPSIZE_ADSIZE, /* 15921 */ IC_XS_OPSIZE, /* 15922 */ IC_64BIT_XS_OPSIZE, /* 15923 */ IC_XD_OPSIZE, /* 15924 */ IC_64BIT_XD_OPSIZE, /* 15925 */ IC_XS_OPSIZE, /* 15926 */ IC_64BIT_XD_OPSIZE, /* 15927 */ IC_OPSIZE_ADSIZE, /* 15928 */ IC_64BIT_REXW_OPSIZE, /* 15929 */ IC_XS_OPSIZE, /* 15930 */ IC_64BIT_REXW_XS, /* 15931 */ IC_XD_OPSIZE, /* 15932 */ IC_64BIT_REXW_XD, /* 15933 */ IC_XS_OPSIZE, /* 15934 */ IC_64BIT_REXW_XS, /* 15935 */ IC_VEX, /* 15936 */ IC_VEX, /* 15937 */ IC_VEX_XS, /* 15938 */ IC_VEX_XS, /* 15939 */ IC_VEX_XD, /* 15940 */ IC_VEX_XD, /* 15941 */ IC_VEX_XD, /* 15942 */ IC_VEX_XD, /* 15943 */ IC_VEX_W, /* 15944 */ IC_VEX_W, /* 15945 */ IC_VEX_W_XS, /* 15946 */ IC_VEX_W_XS, /* 15947 */ IC_VEX_W_XD, /* 15948 */ IC_VEX_W_XD, /* 15949 */ IC_VEX_W_XD, /* 15950 */ IC_VEX_W_XD, /* 15951 */ IC_VEX_OPSIZE, /* 15952 */ IC_VEX_OPSIZE, /* 15953 */ IC_VEX_OPSIZE, /* 15954 */ IC_VEX_OPSIZE, /* 15955 */ IC_VEX_OPSIZE, /* 15956 */ IC_VEX_OPSIZE, /* 15957 */ IC_VEX_OPSIZE, /* 15958 */ IC_VEX_OPSIZE, /* 15959 */ IC_VEX_W_OPSIZE, /* 15960 */ IC_VEX_W_OPSIZE, /* 15961 */ IC_VEX_W_OPSIZE, /* 15962 */ IC_VEX_W_OPSIZE, /* 15963 */ IC_VEX_W_OPSIZE, /* 15964 */ IC_VEX_W_OPSIZE, /* 15965 */ IC_VEX_W_OPSIZE, /* 15966 */ IC_VEX_W_OPSIZE, /* 15967 */ IC_VEX, /* 15968 */ IC_VEX, /* 15969 */ IC_VEX_XS, /* 15970 */ IC_VEX_XS, /* 15971 */ IC_VEX_XD, /* 15972 */ IC_VEX_XD, /* 15973 */ IC_VEX_XD, /* 15974 */ IC_VEX_XD, /* 15975 */ IC_VEX_W, /* 15976 */ IC_VEX_W, /* 15977 */ IC_VEX_W_XS, /* 15978 */ IC_VEX_W_XS, /* 15979 */ IC_VEX_W_XD, /* 15980 */ IC_VEX_W_XD, /* 15981 */ IC_VEX_W_XD, /* 15982 */ IC_VEX_W_XD, /* 15983 */ IC_VEX_OPSIZE, /* 15984 */ IC_VEX_OPSIZE, /* 15985 */ IC_VEX_OPSIZE, /* 15986 */ IC_VEX_OPSIZE, /* 15987 */ IC_VEX_OPSIZE, /* 15988 */ IC_VEX_OPSIZE, /* 15989 */ IC_VEX_OPSIZE, /* 15990 */ IC_VEX_OPSIZE, /* 15991 */ IC_VEX_W_OPSIZE, /* 15992 */ IC_VEX_W_OPSIZE, /* 15993 */ IC_VEX_W_OPSIZE, /* 15994 */ IC_VEX_W_OPSIZE, /* 15995 */ IC_VEX_W_OPSIZE, /* 15996 */ IC_VEX_W_OPSIZE, /* 15997 */ IC_VEX_W_OPSIZE, /* 15998 */ IC_VEX_W_OPSIZE, /* 15999 */ IC_VEX_L, /* 16000 */ IC_VEX_L, /* 16001 */ IC_VEX_L_XS, /* 16002 */ IC_VEX_L_XS, /* 16003 */ IC_VEX_L_XD, /* 16004 */ IC_VEX_L_XD, /* 16005 */ IC_VEX_L_XD, /* 16006 */ IC_VEX_L_XD, /* 16007 */ IC_VEX_L_W, /* 16008 */ IC_VEX_L_W, /* 16009 */ IC_VEX_L_W_XS, /* 16010 */ IC_VEX_L_W_XS, /* 16011 */ IC_VEX_L_W_XD, /* 16012 */ IC_VEX_L_W_XD, /* 16013 */ IC_VEX_L_W_XD, /* 16014 */ IC_VEX_L_W_XD, /* 16015 */ IC_VEX_L_OPSIZE, /* 16016 */ IC_VEX_L_OPSIZE, /* 16017 */ IC_VEX_L_OPSIZE, /* 16018 */ IC_VEX_L_OPSIZE, /* 16019 */ IC_VEX_L_OPSIZE, /* 16020 */ IC_VEX_L_OPSIZE, /* 16021 */ IC_VEX_L_OPSIZE, /* 16022 */ IC_VEX_L_OPSIZE, /* 16023 */ IC_VEX_L_W_OPSIZE, /* 16024 */ IC_VEX_L_W_OPSIZE, /* 16025 */ IC_VEX_L_W_OPSIZE, /* 16026 */ IC_VEX_L_W_OPSIZE, /* 16027 */ IC_VEX_L_W_OPSIZE, /* 16028 */ IC_VEX_L_W_OPSIZE, /* 16029 */ IC_VEX_L_W_OPSIZE, /* 16030 */ IC_VEX_L_W_OPSIZE, /* 16031 */ IC_VEX_L, /* 16032 */ IC_VEX_L, /* 16033 */ IC_VEX_L_XS, /* 16034 */ IC_VEX_L_XS, /* 16035 */ IC_VEX_L_XD, /* 16036 */ IC_VEX_L_XD, /* 16037 */ IC_VEX_L_XD, /* 16038 */ IC_VEX_L_XD, /* 16039 */ IC_VEX_L_W, /* 16040 */ IC_VEX_L_W, /* 16041 */ IC_VEX_L_W_XS, /* 16042 */ IC_VEX_L_W_XS, /* 16043 */ IC_VEX_L_W_XD, /* 16044 */ IC_VEX_L_W_XD, /* 16045 */ IC_VEX_L_W_XD, /* 16046 */ IC_VEX_L_W_XD, /* 16047 */ IC_VEX_L_OPSIZE, /* 16048 */ IC_VEX_L_OPSIZE, /* 16049 */ IC_VEX_L_OPSIZE, /* 16050 */ IC_VEX_L_OPSIZE, /* 16051 */ IC_VEX_L_OPSIZE, /* 16052 */ IC_VEX_L_OPSIZE, /* 16053 */ IC_VEX_L_OPSIZE, /* 16054 */ IC_VEX_L_OPSIZE, /* 16055 */ IC_VEX_L_W_OPSIZE, /* 16056 */ IC_VEX_L_W_OPSIZE, /* 16057 */ IC_VEX_L_W_OPSIZE, /* 16058 */ IC_VEX_L_W_OPSIZE, /* 16059 */ IC_VEX_L_W_OPSIZE, /* 16060 */ IC_VEX_L_W_OPSIZE, /* 16061 */ IC_VEX_L_W_OPSIZE, /* 16062 */ IC_VEX_L_W_OPSIZE, /* 16063 */ IC_VEX_L, /* 16064 */ IC_VEX_L, /* 16065 */ IC_VEX_L_XS, /* 16066 */ IC_VEX_L_XS, /* 16067 */ IC_VEX_L_XD, /* 16068 */ IC_VEX_L_XD, /* 16069 */ IC_VEX_L_XD, /* 16070 */ IC_VEX_L_XD, /* 16071 */ IC_VEX_L_W, /* 16072 */ IC_VEX_L_W, /* 16073 */ IC_VEX_L_W_XS, /* 16074 */ IC_VEX_L_W_XS, /* 16075 */ IC_VEX_L_W_XD, /* 16076 */ IC_VEX_L_W_XD, /* 16077 */ IC_VEX_L_W_XD, /* 16078 */ IC_VEX_L_W_XD, /* 16079 */ IC_VEX_L_OPSIZE, /* 16080 */ IC_VEX_L_OPSIZE, /* 16081 */ IC_VEX_L_OPSIZE, /* 16082 */ IC_VEX_L_OPSIZE, /* 16083 */ IC_VEX_L_OPSIZE, /* 16084 */ IC_VEX_L_OPSIZE, /* 16085 */ IC_VEX_L_OPSIZE, /* 16086 */ IC_VEX_L_OPSIZE, /* 16087 */ IC_VEX_L_W_OPSIZE, /* 16088 */ IC_VEX_L_W_OPSIZE, /* 16089 */ IC_VEX_L_W_OPSIZE, /* 16090 */ IC_VEX_L_W_OPSIZE, /* 16091 */ IC_VEX_L_W_OPSIZE, /* 16092 */ IC_VEX_L_W_OPSIZE, /* 16093 */ IC_VEX_L_W_OPSIZE, /* 16094 */ IC_VEX_L_W_OPSIZE, /* 16095 */ IC_VEX_L, /* 16096 */ IC_VEX_L, /* 16097 */ IC_VEX_L_XS, /* 16098 */ IC_VEX_L_XS, /* 16099 */ IC_VEX_L_XD, /* 16100 */ IC_VEX_L_XD, /* 16101 */ IC_VEX_L_XD, /* 16102 */ IC_VEX_L_XD, /* 16103 */ IC_VEX_L_W, /* 16104 */ IC_VEX_L_W, /* 16105 */ IC_VEX_L_W_XS, /* 16106 */ IC_VEX_L_W_XS, /* 16107 */ IC_VEX_L_W_XD, /* 16108 */ IC_VEX_L_W_XD, /* 16109 */ IC_VEX_L_W_XD, /* 16110 */ IC_VEX_L_W_XD, /* 16111 */ IC_VEX_L_OPSIZE, /* 16112 */ IC_VEX_L_OPSIZE, /* 16113 */ IC_VEX_L_OPSIZE, /* 16114 */ IC_VEX_L_OPSIZE, /* 16115 */ IC_VEX_L_OPSIZE, /* 16116 */ IC_VEX_L_OPSIZE, /* 16117 */ IC_VEX_L_OPSIZE, /* 16118 */ IC_VEX_L_OPSIZE, /* 16119 */ IC_VEX_L_W_OPSIZE, /* 16120 */ IC_VEX_L_W_OPSIZE, /* 16121 */ IC_VEX_L_W_OPSIZE, /* 16122 */ IC_VEX_L_W_OPSIZE, /* 16123 */ IC_VEX_L_W_OPSIZE, /* 16124 */ IC_VEX_L_W_OPSIZE, /* 16125 */ IC_VEX_L_W_OPSIZE, /* 16126 */ IC_VEX_L_W_OPSIZE, /* 16127 */ IC_EVEX_L2_KZ_B, /* 16128 */ IC_EVEX_L2_KZ_B, /* 16129 */ IC_EVEX_L2_XS_KZ_B, /* 16130 */ IC_EVEX_L2_XS_KZ_B, /* 16131 */ IC_EVEX_L2_XD_KZ_B, /* 16132 */ IC_EVEX_L2_XD_KZ_B, /* 16133 */ IC_EVEX_L2_XD_KZ_B, /* 16134 */ IC_EVEX_L2_XD_KZ_B, /* 16135 */ IC_EVEX_L2_W_KZ_B, /* 16136 */ IC_EVEX_L2_W_KZ_B, /* 16137 */ IC_EVEX_L2_W_XS_KZ_B, /* 16138 */ IC_EVEX_L2_W_XS_KZ_B, /* 16139 */ IC_EVEX_L2_W_XD_KZ_B, /* 16140 */ IC_EVEX_L2_W_XD_KZ_B, /* 16141 */ IC_EVEX_L2_W_XD_KZ_B, /* 16142 */ IC_EVEX_L2_W_XD_KZ_B, /* 16143 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16144 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16145 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16146 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16147 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16148 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16149 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16150 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16151 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16152 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16153 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16154 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16155 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16156 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16157 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16158 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16159 */ IC_EVEX_L2_KZ_B, /* 16160 */ IC_EVEX_L2_KZ_B, /* 16161 */ IC_EVEX_L2_XS_KZ_B, /* 16162 */ IC_EVEX_L2_XS_KZ_B, /* 16163 */ IC_EVEX_L2_XD_KZ_B, /* 16164 */ IC_EVEX_L2_XD_KZ_B, /* 16165 */ IC_EVEX_L2_XD_KZ_B, /* 16166 */ IC_EVEX_L2_XD_KZ_B, /* 16167 */ IC_EVEX_L2_W_KZ_B, /* 16168 */ IC_EVEX_L2_W_KZ_B, /* 16169 */ IC_EVEX_L2_W_XS_KZ_B, /* 16170 */ IC_EVEX_L2_W_XS_KZ_B, /* 16171 */ IC_EVEX_L2_W_XD_KZ_B, /* 16172 */ IC_EVEX_L2_W_XD_KZ_B, /* 16173 */ IC_EVEX_L2_W_XD_KZ_B, /* 16174 */ IC_EVEX_L2_W_XD_KZ_B, /* 16175 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16176 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16177 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16178 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16179 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16180 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16181 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16182 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16183 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16184 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16185 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16186 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16187 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16188 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16189 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16190 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16191 */ IC_EVEX_L2_KZ_B, /* 16192 */ IC_EVEX_L2_KZ_B, /* 16193 */ IC_EVEX_L2_XS_KZ_B, /* 16194 */ IC_EVEX_L2_XS_KZ_B, /* 16195 */ IC_EVEX_L2_XD_KZ_B, /* 16196 */ IC_EVEX_L2_XD_KZ_B, /* 16197 */ IC_EVEX_L2_XD_KZ_B, /* 16198 */ IC_EVEX_L2_XD_KZ_B, /* 16199 */ IC_EVEX_L2_W_KZ_B, /* 16200 */ IC_EVEX_L2_W_KZ_B, /* 16201 */ IC_EVEX_L2_W_XS_KZ_B, /* 16202 */ IC_EVEX_L2_W_XS_KZ_B, /* 16203 */ IC_EVEX_L2_W_XD_KZ_B, /* 16204 */ IC_EVEX_L2_W_XD_KZ_B, /* 16205 */ IC_EVEX_L2_W_XD_KZ_B, /* 16206 */ IC_EVEX_L2_W_XD_KZ_B, /* 16207 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16208 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16209 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16210 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16211 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16212 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16213 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16214 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16215 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16216 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16217 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16218 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16219 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16220 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16221 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16222 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16223 */ IC_EVEX_L2_KZ_B, /* 16224 */ IC_EVEX_L2_KZ_B, /* 16225 */ IC_EVEX_L2_XS_KZ_B, /* 16226 */ IC_EVEX_L2_XS_KZ_B, /* 16227 */ IC_EVEX_L2_XD_KZ_B, /* 16228 */ IC_EVEX_L2_XD_KZ_B, /* 16229 */ IC_EVEX_L2_XD_KZ_B, /* 16230 */ IC_EVEX_L2_XD_KZ_B, /* 16231 */ IC_EVEX_L2_W_KZ_B, /* 16232 */ IC_EVEX_L2_W_KZ_B, /* 16233 */ IC_EVEX_L2_W_XS_KZ_B, /* 16234 */ IC_EVEX_L2_W_XS_KZ_B, /* 16235 */ IC_EVEX_L2_W_XD_KZ_B, /* 16236 */ IC_EVEX_L2_W_XD_KZ_B, /* 16237 */ IC_EVEX_L2_W_XD_KZ_B, /* 16238 */ IC_EVEX_L2_W_XD_KZ_B, /* 16239 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16240 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16241 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16242 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16243 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16244 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16245 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16246 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16247 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16248 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16249 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16250 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16251 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16252 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16253 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16254 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16255 */ IC_EVEX_L2_KZ_B, /* 16256 */ IC_EVEX_L2_KZ_B, /* 16257 */ IC_EVEX_L2_XS_KZ_B, /* 16258 */ IC_EVEX_L2_XS_KZ_B, /* 16259 */ IC_EVEX_L2_XD_KZ_B, /* 16260 */ IC_EVEX_L2_XD_KZ_B, /* 16261 */ IC_EVEX_L2_XD_KZ_B, /* 16262 */ IC_EVEX_L2_XD_KZ_B, /* 16263 */ IC_EVEX_L2_W_KZ_B, /* 16264 */ IC_EVEX_L2_W_KZ_B, /* 16265 */ IC_EVEX_L2_W_XS_KZ_B, /* 16266 */ IC_EVEX_L2_W_XS_KZ_B, /* 16267 */ IC_EVEX_L2_W_XD_KZ_B, /* 16268 */ IC_EVEX_L2_W_XD_KZ_B, /* 16269 */ IC_EVEX_L2_W_XD_KZ_B, /* 16270 */ IC_EVEX_L2_W_XD_KZ_B, /* 16271 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16272 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16273 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16274 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16275 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16276 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16277 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16278 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16279 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16280 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16281 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16282 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16283 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16284 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16285 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16286 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16287 */ IC_EVEX_L2_KZ_B, /* 16288 */ IC_EVEX_L2_KZ_B, /* 16289 */ IC_EVEX_L2_XS_KZ_B, /* 16290 */ IC_EVEX_L2_XS_KZ_B, /* 16291 */ IC_EVEX_L2_XD_KZ_B, /* 16292 */ IC_EVEX_L2_XD_KZ_B, /* 16293 */ IC_EVEX_L2_XD_KZ_B, /* 16294 */ IC_EVEX_L2_XD_KZ_B, /* 16295 */ IC_EVEX_L2_W_KZ_B, /* 16296 */ IC_EVEX_L2_W_KZ_B, /* 16297 */ IC_EVEX_L2_W_XS_KZ_B, /* 16298 */ IC_EVEX_L2_W_XS_KZ_B, /* 16299 */ IC_EVEX_L2_W_XD_KZ_B, /* 16300 */ IC_EVEX_L2_W_XD_KZ_B, /* 16301 */ IC_EVEX_L2_W_XD_KZ_B, /* 16302 */ IC_EVEX_L2_W_XD_KZ_B, /* 16303 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16304 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16305 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16306 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16307 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16308 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16309 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16310 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16311 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16312 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16313 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16314 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16315 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16316 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16317 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16318 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16319 */ IC_EVEX_L2_KZ_B, /* 16320 */ IC_EVEX_L2_KZ_B, /* 16321 */ IC_EVEX_L2_XS_KZ_B, /* 16322 */ IC_EVEX_L2_XS_KZ_B, /* 16323 */ IC_EVEX_L2_XD_KZ_B, /* 16324 */ IC_EVEX_L2_XD_KZ_B, /* 16325 */ IC_EVEX_L2_XD_KZ_B, /* 16326 */ IC_EVEX_L2_XD_KZ_B, /* 16327 */ IC_EVEX_L2_W_KZ_B, /* 16328 */ IC_EVEX_L2_W_KZ_B, /* 16329 */ IC_EVEX_L2_W_XS_KZ_B, /* 16330 */ IC_EVEX_L2_W_XS_KZ_B, /* 16331 */ IC_EVEX_L2_W_XD_KZ_B, /* 16332 */ IC_EVEX_L2_W_XD_KZ_B, /* 16333 */ IC_EVEX_L2_W_XD_KZ_B, /* 16334 */ IC_EVEX_L2_W_XD_KZ_B, /* 16335 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16336 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16337 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16338 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16339 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16340 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16341 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16342 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16343 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16344 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16345 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16346 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16347 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16348 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16349 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16350 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16351 */ IC_EVEX_L2_KZ_B, /* 16352 */ IC_EVEX_L2_KZ_B, /* 16353 */ IC_EVEX_L2_XS_KZ_B, /* 16354 */ IC_EVEX_L2_XS_KZ_B, /* 16355 */ IC_EVEX_L2_XD_KZ_B, /* 16356 */ IC_EVEX_L2_XD_KZ_B, /* 16357 */ IC_EVEX_L2_XD_KZ_B, /* 16358 */ IC_EVEX_L2_XD_KZ_B, /* 16359 */ IC_EVEX_L2_W_KZ_B, /* 16360 */ IC_EVEX_L2_W_KZ_B, /* 16361 */ IC_EVEX_L2_W_XS_KZ_B, /* 16362 */ IC_EVEX_L2_W_XS_KZ_B, /* 16363 */ IC_EVEX_L2_W_XD_KZ_B, /* 16364 */ IC_EVEX_L2_W_XD_KZ_B, /* 16365 */ IC_EVEX_L2_W_XD_KZ_B, /* 16366 */ IC_EVEX_L2_W_XD_KZ_B, /* 16367 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16368 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16369 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16370 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16371 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16372 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16373 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16374 */ IC_EVEX_L2_OPSIZE_KZ_B, /* 16375 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16376 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16377 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16378 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16379 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16380 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16381 */ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16382 */ IC_EVEX_L2_W_OPSIZE_KZ_B /* 16383 */ }; static const InstrUID modRMTable[] = { /* EmptyTable */ 0x0, /* Table1 */ 0xc8, /* ADD8mr */ 0xcc, /* ADD8rr */ /* Table3 */ 0xb6, /* ADD32mr */ 0xba, /* ADD32rr */ /* Table5 */ 0xcb, /* ADD8rm */ 0xcd, /* ADD8rr_REV */ /* Table7 */ 0xb9, /* ADD32rm */ 0xbb, /* ADD32rr_REV */ /* Table9 */ 0xc5, /* ADD8i8 */ /* Table10 */ 0xb3, /* ADD32i32 */ /* Table11 */ 0x436, /* PUSHES32 */ /* Table12 */ 0x412, /* POPES32 */ /* Table13 */ 0x3ec, /* OR8mr */ 0x3f0, /* OR8rr */ /* Table15 */ 0x3da, /* OR32mr */ 0x3de, /* OR32rr */ /* Table17 */ 0x3ef, /* OR8rm */ 0x3f1, /* OR8rr_REV */ /* Table19 */ 0x3dd, /* OR32rm */ 0x3df, /* OR32rr_REV */ /* Table21 */ 0x3e9, /* OR8i8 */ /* Table22 */ 0x3d7, /* OR32i32 */ /* Table23 */ 0x432, /* PUSHCS32 */ /* Table24 */ 0xa0, /* ADC8mr */ 0xa4, /* ADC8rr */ /* Table26 */ 0x8e, /* ADC32mr */ 0x92, /* ADC32rr */ /* Table28 */ 0xa3, /* ADC8rm */ 0xa5, /* ADC8rr_REV */ /* Table30 */ 0x91, /* ADC32rm */ 0x93, /* ADC32rr_REV */ /* Table32 */ 0x9d, /* ADC8i8 */ /* Table33 */ 0x8b, /* ADC32i32 */ /* Table34 */ 0x441, /* PUSHSS32 */ /* Table35 */ 0x41d, /* POPSS32 */ /* Table36 */ 0x51b, /* SBB8mr */ 0x51f, /* SBB8rr */ /* Table38 */ 0x509, /* SBB32mr */ 0x50d, /* SBB32rr */ /* Table40 */ 0x51e, /* SBB8rm */ 0x520, /* SBB8rr_REV */ /* Table42 */ 0x50c, /* SBB32rm */ 0x50e, /* SBB32rr_REV */ /* Table44 */ 0x518, /* SBB8i8 */ /* Table45 */ 0x506, /* SBB32i32 */ /* Table46 */ 0x434, /* PUSHDS32 */ /* Table47 */ 0x410, /* POPDS32 */ /* Table48 */ 0xf0, /* AND8mr */ 0xf4, /* AND8rr */ /* Table50 */ 0xde, /* AND32mr */ 0xe2, /* AND32rr */ /* Table52 */ 0xf3, /* AND8rm */ 0xf5, /* AND8rr_REV */ /* Table54 */ 0xe1, /* AND32rm */ 0xe3, /* AND32rr_REV */ /* Table56 */ 0xed, /* AND8i8 */ /* Table57 */ 0xdb, /* AND32i32 */ /* Table58 */ 0x225, /* DAA */ /* Table59 */ 0x5d2, /* SUB8mr */ 0x5d6, /* SUB8rr */ /* Table61 */ 0x5c0, /* SUB32mr */ 0x5c4, /* SUB32rr */ /* Table63 */ 0x5d5, /* SUB8rm */ 0x5d7, /* SUB8rr_REV */ /* Table65 */ 0x5c3, /* SUB32rm */ 0x5c5, /* SUB32rr_REV */ /* Table67 */ 0x5cf, /* SUB8i8 */ /* Table68 */ 0x5bd, /* SUB32i32 */ /* Table69 */ 0x226, /* DAS */ /* Table70 */ 0x671, /* XOR8mr */ 0x675, /* XOR8rr */ /* Table72 */ 0x65f, /* XOR32mr */ 0x663, /* XOR32rr */ /* Table74 */ 0x674, /* XOR8rm */ 0x676, /* XOR8rr_REV */ /* Table76 */ 0x662, /* XOR32rm */ 0x664, /* XOR32rr_REV */ /* Table78 */ 0x66e, /* XOR8i8 */ /* Table79 */ 0x65c, /* XOR32i32 */ /* Table80 */ 0x7e, /* AAA */ /* Table81 */ 0x20d, /* CMP8mr */ 0x211, /* CMP8rr */ /* Table83 */ 0x1fb, /* CMP32mr */ 0x1ff, /* CMP32rr */ /* Table85 */ 0x210, /* CMP8rm */ 0x212, /* CMP8rr_REV */ /* Table87 */ 0x1fe, /* CMP32rm */ 0x200, /* CMP32rr_REV */ /* Table89 */ 0x20a, /* CMP8i8 */ /* Table90 */ 0x1f8, /* CMP32i32 */ /* Table91 */ 0x81, /* AAS */ /* Table92 */ 0x277, /* INC32r_alt */ /* Table93 */ 0x22d, /* DEC32r_alt */ /* Table94 */ 0x427, /* PUSH32r */ /* Table95 */ 0x407, /* POP32r */ /* Table96 */ 0x430, /* PUSHA32 */ /* Table97 */ 0x40e, /* POPA32 */ /* Table98 */ 0x12d, /* BOUNDS32rm */ 0x0, /* */ /* Table100 */ 0xfa, /* ARPL16mr */ 0xfb, /* ARPL16rr */ /* Table102 */ 0x227, /* DATA16_PREFIX */ /* Table103 */ 0x443, /* PUSHi32 */ /* Table104 */ 0x25d, /* IMUL32rmi */ 0x260, /* IMUL32rri */ /* Table106 */ 0x426, /* PUSH32i8 */ /* Table107 */ 0x25e, /* IMUL32rmi8 */ 0x261, /* IMUL32rri8 */ /* Table109 */ 0x27e, /* INSB */ /* Table110 */ 0x27f, /* INSL */ /* Table111 */ 0x3f8, /* OUTSB */ /* Table112 */ 0x3f9, /* OUTSL */ /* Table113 */ 0x2ca, /* JO_1 */ /* Table114 */ 0x2c1, /* JNO_1 */ /* Table115 */ 0x29b, /* JB_1 */ /* Table116 */ 0x292, /* JAE_1 */ /* Table117 */ 0x2a0, /* JE_1 */ /* Table118 */ 0x2be, /* JNE_1 */ /* Table119 */ 0x298, /* JBE_1 */ /* Table120 */ 0x295, /* JA_1 */ /* Table121 */ 0x2d1, /* JS_1 */ /* Table122 */ 0x2c7, /* JNS_1 */ /* Table123 */ 0x2cd, /* JP_1 */ /* Table124 */ 0x2c4, /* JNP_1 */ /* Table125 */ 0x2ac, /* JL_1 */ /* Table126 */ 0x2a3, /* JGE_1 */ /* Table127 */ 0x2a9, /* JLE_1 */ /* Table128 */ 0x2a6, /* JG_1 */ /* Table129 */ 0xc6, /* ADD8mi */ 0x3ea, /* OR8mi */ 0x9e, /* ADC8mi */ 0x519, /* SBB8mi */ 0xee, /* AND8mi */ 0x5d0, /* SUB8mi */ 0x66f, /* XOR8mi */ 0x20b, /* CMP8mi */ 0xc9, /* ADD8ri */ 0x3ed, /* OR8ri */ 0xa1, /* ADC8ri */ 0x51c, /* SBB8ri */ 0xf1, /* AND8ri */ 0x5d3, /* SUB8ri */ 0x672, /* XOR8ri */ 0x20e, /* CMP8ri */ /* Table145 */ 0xb4, /* ADD32mi */ 0x3d8, /* OR32mi */ 0x8c, /* ADC32mi */ 0x507, /* SBB32mi */ 0xdc, /* AND32mi */ 0x5be, /* SUB32mi */ 0x65d, /* XOR32mi */ 0x1f9, /* CMP32mi */ 0xb7, /* ADD32ri */ 0x3db, /* OR32ri */ 0x8f, /* ADC32ri */ 0x50a, /* SBB32ri */ 0xdf, /* AND32ri */ 0x5c1, /* SUB32ri */ 0x660, /* XOR32ri */ 0x1fc, /* CMP32ri */ /* Table161 */ 0xc7, /* ADD8mi8 */ 0x3eb, /* OR8mi8 */ 0x9f, /* ADC8mi8 */ 0x51a, /* SBB8mi8 */ 0xef, /* AND8mi8 */ 0x5d1, /* SUB8mi8 */ 0x670, /* XOR8mi8 */ 0x20c, /* CMP8mi8 */ 0xca, /* ADD8ri8 */ 0x3ee, /* OR8ri8 */ 0xa2, /* ADC8ri8 */ 0x51d, /* SBB8ri8 */ 0xf2, /* AND8ri8 */ 0x5d4, /* SUB8ri8 */ 0x673, /* XOR8ri8 */ 0x20f, /* CMP8ri8 */ /* Table177 */ 0xb5, /* ADD32mi8 */ 0x3d9, /* OR32mi8 */ 0x8d, /* ADC32mi8 */ 0x508, /* SBB32mi8 */ 0xdd, /* AND32mi8 */ 0x5bf, /* SUB32mi8 */ 0x65e, /* XOR32mi8 */ 0x1fa, /* CMP32mi8 */ 0xb8, /* ADD32ri8 */ 0x3dc, /* OR32ri8 */ 0x90, /* ADC32ri8 */ 0x50b, /* SBB32ri8 */ 0xe0, /* AND32ri8 */ 0x5c2, /* SUB32ri8 */ 0x661, /* XOR32ri8 */ 0x1fd, /* CMP32ri8 */ /* Table193 */ 0x5fb, /* TEST8mr */ 0x5fe, /* TEST8rr */ /* Table195 */ 0x5ed, /* TEST32mr */ 0x5f0, /* TEST32rr */ /* Table197 */ 0x64a, /* XCHG8rm */ 0x64b, /* XCHG8rr */ /* Table199 */ 0x645, /* XCHG32rm */ 0x646, /* XCHG32rr */ /* Table201 */ 0x359, /* MOV8mr */ 0x362, /* MOV8rr */ /* Table203 */ 0x337, /* MOV32mr */ 0x340, /* MOV32rr */ /* Table205 */ 0x360, /* MOV8rm */ 0x364, /* MOV8rr_REV */ /* Table207 */ 0x33f, /* MOV32rm */ 0x341, /* MOV32rr_REV */ /* Table209 */ 0x325, /* MOV16ms */ 0x342, /* MOV32rs */ /* Table211 */ 0x2de, /* LEA32r */ 0x0, /* */ /* Table213 */ 0x32f, /* MOV16sm */ 0x343, /* MOV32sr */ /* Table215 */ 0x408, /* POP32rmm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x409, /* POP32rmr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table231 */ 0x3a7, /* NOOP */ /* Table232 */ 0x644, /* XCHG32ar */ /* Table233 */ 0x224, /* CWDE */ /* Table234 */ 0x181, /* CDQ */ /* Table235 */ 0x23f, /* FARCALL32i */ /* Table236 */ 0x438, /* PUSHF32 */ /* Table237 */ 0x414, /* POPF32 */ /* Table238 */ 0x4c6, /* SAHF */ /* Table239 */ 0x2d4, /* LAHF */ /* Table240 */ 0x356, /* MOV8ao32 */ /* Table241 */ 0x332, /* MOV32ao32 */ /* Table242 */ 0x35c, /* MOV8o32a */ /* Table243 */ 0x339, /* MOV32o32a */ /* Table244 */ 0x370, /* MOVSB */ /* Table245 */ 0x371, /* MOVSL */ /* Table246 */ 0x213, /* CMPSB */ /* Table247 */ 0x214, /* CMPSL */ /* Table248 */ 0x5f8, /* TEST8i8 */ /* Table249 */ 0x5ea, /* TEST32i32 */ /* Table250 */ 0x5ac, /* STOSB */ /* Table251 */ 0x5ad, /* STOSL */ /* Table252 */ 0x2f8, /* LODSB */ /* Table253 */ 0x2f9, /* LODSL */ /* Table254 */ 0x521, /* SCASB */ /* Table255 */ 0x522, /* SCASL */ /* Table256 */ 0x35e, /* MOV8ri */ /* Table257 */ 0x33d, /* MOV32ri */ /* Table258 */ 0x4a4, /* ROL8mi */ 0x4bc, /* ROR8mi */ 0x458, /* RCL8mi */ 0x470, /* RCR8mi */ 0x55d, /* SHL8mi */ 0x585, /* SHR8mi */ 0x4db, /* SAL8mi */ 0x4f4, /* SAR8mi */ 0x4a7, /* ROL8ri */ 0x4bf, /* ROR8ri */ 0x45b, /* RCL8ri */ 0x473, /* RCR8ri */ 0x560, /* SHL8ri */ 0x588, /* SHR8ri */ 0x4de, /* SAL8ri */ 0x4f7, /* SAR8ri */ /* Table274 */ 0x498, /* ROL32mi */ 0x4b0, /* ROR32mi */ 0x44c, /* RCL32mi */ 0x464, /* RCR32mi */ 0x551, /* SHL32mi */ 0x579, /* SHR32mi */ 0x4cf, /* SAL32mi */ 0x4e8, /* SAR32mi */ 0x49b, /* ROL32ri */ 0x4b3, /* ROR32ri */ 0x44f, /* RCL32ri */ 0x467, /* RCR32ri */ 0x554, /* SHL32ri */ 0x57c, /* SHR32ri */ 0x4d2, /* SAL32ri */ 0x4eb, /* SAR32ri */ /* Table290 */ 0x489, /* RETIL */ /* Table291 */ 0x48c, /* RETL */ /* Table292 */ 0x2e4, /* LES32rm */ 0x0, /* */ /* Table294 */ 0x2dc, /* LDS32rm */ 0x0, /* */ /* Table296 */ 0x358, /* MOV8mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x35f, /* MOV8ri_alt */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table312 */ 0x336, /* MOV32mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x33e, /* MOV32ri_alt */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table328 */ 0x23c, /* ENTER */ /* Table329 */ 0x2e1, /* LEAVE */ /* Table330 */ 0x2ff, /* LRETIL */ /* Table331 */ 0x302, /* LRETL */ /* Table332 */ 0x283, /* INT3 */ /* Table333 */ 0x281, /* INT */ /* Table334 */ 0x284, /* INTO */ /* Table335 */ 0x290, /* IRET32 */ /* Table336 */ 0x4a2, /* ROL8m1 */ 0x4ba, /* ROR8m1 */ 0x456, /* RCL8m1 */ 0x46e, /* RCR8m1 */ 0x55b, /* SHL8m1 */ 0x583, /* SHR8m1 */ 0x4d9, /* SAL8m1 */ 0x4f2, /* SAR8m1 */ 0x4a5, /* ROL8r1 */ 0x4bd, /* ROR8r1 */ 0x459, /* RCL8r1 */ 0x471, /* RCR8r1 */ 0x55e, /* SHL8r1 */ 0x586, /* SHR8r1 */ 0x4dc, /* SAL8r1 */ 0x4f5, /* SAR8r1 */ /* Table352 */ 0x496, /* ROL32m1 */ 0x4ae, /* ROR32m1 */ 0x44a, /* RCL32m1 */ 0x462, /* RCR32m1 */ 0x54f, /* SHL32m1 */ 0x577, /* SHR32m1 */ 0x4cd, /* SAL32m1 */ 0x4e6, /* SAR32m1 */ 0x499, /* ROL32r1 */ 0x4b1, /* ROR32r1 */ 0x44d, /* RCL32r1 */ 0x465, /* RCR32r1 */ 0x552, /* SHL32r1 */ 0x57a, /* SHR32r1 */ 0x4d0, /* SAL32r1 */ 0x4e9, /* SAR32r1 */ /* Table368 */ 0x4a3, /* ROL8mCL */ 0x4bb, /* ROR8mCL */ 0x457, /* RCL8mCL */ 0x46f, /* RCR8mCL */ 0x55c, /* SHL8mCL */ 0x584, /* SHR8mCL */ 0x4da, /* SAL8mCL */ 0x4f3, /* SAR8mCL */ 0x4a6, /* ROL8rCL */ 0x4be, /* ROR8rCL */ 0x45a, /* RCL8rCL */ 0x472, /* RCR8rCL */ 0x55f, /* SHL8rCL */ 0x587, /* SHR8rCL */ 0x4dd, /* SAL8rCL */ 0x4f6, /* SAR8rCL */ /* Table384 */ 0x497, /* ROL32mCL */ 0x4af, /* ROR32mCL */ 0x44b, /* RCL32mCL */ 0x463, /* RCR32mCL */ 0x550, /* SHL32mCL */ 0x578, /* SHR32mCL */ 0x4ce, /* SAL32mCL */ 0x4e7, /* SAR32mCL */ 0x49a, /* ROL32rCL */ 0x4b2, /* ROR32rCL */ 0x44e, /* RCL32rCL */ 0x466, /* RCR32rCL */ 0x553, /* SHL32rCL */ 0x57b, /* SHR32rCL */ 0x4d1, /* SAL32rCL */ 0x4ea, /* SAR32rCL */ /* Table400 */ 0x80, /* AAM8i8 */ /* Table401 */ 0x7f, /* AAD8i8 */ /* Table402 */ 0x4df, /* SALC */ /* Table403 */ 0x652, /* XLAT */ /* Table404 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x247, /* FSETPM */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table476 */ 0x2fe, /* LOOPNE */ /* Table477 */ 0x2fd, /* LOOPE */ /* Table478 */ 0x2fc, /* LOOP */ /* Table479 */ 0x29f, /* JECXZ */ /* Table480 */ 0x270, /* IN8ri */ /* Table481 */ 0x26e, /* IN32ri */ /* Table482 */ 0x3f6, /* OUT8ir */ /* Table483 */ 0x3f4, /* OUT32ir */ /* Table484 */ 0x17f, /* CALLpcrel32 */ /* Table485 */ 0x2bd, /* JMP_4 */ /* Table486 */ 0x244, /* FARJMP32i */ /* Table487 */ 0x2bb, /* JMP_1 */ /* Table488 */ 0x271, /* IN8rr */ /* Table489 */ 0x26f, /* IN32rr */ /* Table490 */ 0x3f7, /* OUT8rr */ /* Table491 */ 0x3f5, /* OUT32rr */ /* Table492 */ 0x2f7, /* LOCK_PREFIX */ /* Table493 */ 0x282, /* INT1 */ /* Table494 */ 0x487, /* REPNE_PREFIX */ /* Table495 */ 0x488, /* REP_PREFIX */ /* Table496 */ 0x249, /* HLT */ /* Table497 */ 0x18e, /* CMC */ /* Table498 */ 0x5f9, /* TEST8mi */ 0x5fa, /* TEST8mi_alt */ 0x3cc, /* NOT8m */ 0x3a5, /* NEG8m */ 0x398, /* MUL8m */ 0x26a, /* IMUL8m */ 0x238, /* DIV8m */ 0x250, /* IDIV8m */ 0x5fc, /* TEST8ri */ 0x5fd, /* TEST8ri_alt */ 0x3cd, /* NOT8r */ 0x3a6, /* NEG8r */ 0x399, /* MUL8r */ 0x26b, /* IMUL8r */ 0x239, /* DIV8r */ 0x251, /* IDIV8r */ /* Table514 */ 0x5eb, /* TEST32mi */ 0x5ec, /* TEST32mi_alt */ 0x3c8, /* NOT32m */ 0x3a1, /* NEG32m */ 0x394, /* MUL32m */ 0x25a, /* IMUL32m */ 0x234, /* DIV32m */ 0x24c, /* IDIV32m */ 0x5ee, /* TEST32ri */ 0x5ef, /* TEST32ri_alt */ 0x3c9, /* NOT32r */ 0x3a2, /* NEG32r */ 0x395, /* MUL32r */ 0x25b, /* IMUL32r */ 0x235, /* DIV32r */ 0x24d, /* IDIV32r */ /* Table530 */ 0x184, /* CLC */ /* Table531 */ 0x5a8, /* STC */ /* Table532 */ 0x189, /* CLI */ /* Table533 */ 0x5ab, /* STI */ /* Table534 */ 0x185, /* CLD */ /* Table535 */ 0x5a9, /* STD */ /* Table536 */ 0x27a, /* INC8m */ 0x230, /* DEC8m */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x27b, /* INC8r */ 0x231, /* DEC8r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table552 */ 0x275, /* INC32m */ 0x22b, /* DEC32m */ 0x175, /* CALL32m */ 0x240, /* FARCALL32m */ 0x2b3, /* JMP32m */ 0x245, /* FARJMP32m */ 0x428, /* PUSH32rmm */ 0x0, /* */ 0x276, /* INC32r */ 0x22c, /* DEC32r */ 0x177, /* CALL32r */ 0x0, /* */ 0x2b5, /* JMP32r */ 0x0, /* */ 0x429, /* PUSH32rmr */ 0x0, /* */ /* Table568 */ 0x48f, /* REX64_PREFIX */ /* Table569 */ 0x42c, /* PUSH64r */ /* Table570 */ 0x40a, /* POP64r */ /* Table571 */ 0x42a, /* PUSH64i32 */ /* Table572 */ 0x42b, /* PUSH64i8 */ /* Table573 */ 0x2df, /* LEA64_32r */ 0x0, /* */ /* Table575 */ 0x40b, /* POP64rmm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x40c, /* POP64rmr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table591 */ 0x439, /* PUSHF64 */ /* Table592 */ 0x415, /* POPF64 */ /* Table593 */ 0x357, /* MOV8ao64 */ /* Table594 */ 0x333, /* MOV32ao64 */ /* Table595 */ 0x35d, /* MOV8o64a */ /* Table596 */ 0x33a, /* MOV32o64a */ /* Table597 */ 0x48a, /* RETIQ */ /* Table598 */ 0x48d, /* RETQ */ /* Table599 */ 0x2e2, /* LEAVE64 */ /* Table600 */ 0x2d0, /* JRCXZ */ /* Table601 */ 0x17b, /* CALL64pcrel32 */ /* Table602 */ 0x275, /* INC32m */ 0x22b, /* DEC32m */ 0x179, /* CALL64m */ 0x240, /* FARCALL32m */ 0x2b7, /* JMP64m */ 0x245, /* FARJMP32m */ 0x42d, /* PUSH64rmm */ 0x0, /* */ 0x276, /* INC32r */ 0x22c, /* DEC32r */ 0x17c, /* CALL64r */ 0x0, /* */ 0x2b9, /* JMP64r */ 0x0, /* */ 0x42e, /* PUSH64rmr */ 0x0, /* */ /* Table618 */ 0xad, /* ADD16mr */ 0xb1, /* ADD16rr */ /* Table620 */ 0xb0, /* ADD16rm */ 0xb2, /* ADD16rr_REV */ /* Table622 */ 0xaa, /* ADD16i16 */ /* Table623 */ 0x435, /* PUSHES16 */ /* Table624 */ 0x411, /* POPES16 */ /* Table625 */ 0x3d1, /* OR16mr */ 0x3d5, /* OR16rr */ /* Table627 */ 0x3d4, /* OR16rm */ 0x3d6, /* OR16rr_REV */ /* Table629 */ 0x3ce, /* OR16i16 */ /* Table630 */ 0x431, /* PUSHCS16 */ /* Table631 */ 0x85, /* ADC16mr */ 0x89, /* ADC16rr */ /* Table633 */ 0x88, /* ADC16rm */ 0x8a, /* ADC16rr_REV */ /* Table635 */ 0x82, /* ADC16i16 */ /* Table636 */ 0x440, /* PUSHSS16 */ /* Table637 */ 0x41c, /* POPSS16 */ /* Table638 */ 0x500, /* SBB16mr */ 0x504, /* SBB16rr */ /* Table640 */ 0x503, /* SBB16rm */ 0x505, /* SBB16rr_REV */ /* Table642 */ 0x4fd, /* SBB16i16 */ /* Table643 */ 0x433, /* PUSHDS16 */ /* Table644 */ 0x40f, /* POPDS16 */ /* Table645 */ 0xd5, /* AND16mr */ 0xd9, /* AND16rr */ /* Table647 */ 0xd8, /* AND16rm */ 0xda, /* AND16rr_REV */ /* Table649 */ 0xd2, /* AND16i16 */ /* Table650 */ 0x5b7, /* SUB16mr */ 0x5bb, /* SUB16rr */ /* Table652 */ 0x5ba, /* SUB16rm */ 0x5bc, /* SUB16rr_REV */ /* Table654 */ 0x5b4, /* SUB16i16 */ /* Table655 */ 0x656, /* XOR16mr */ 0x65a, /* XOR16rr */ /* Table657 */ 0x659, /* XOR16rm */ 0x65b, /* XOR16rr_REV */ /* Table659 */ 0x653, /* XOR16i16 */ /* Table660 */ 0x1f2, /* CMP16mr */ 0x1f6, /* CMP16rr */ /* Table662 */ 0x1f5, /* CMP16rm */ 0x1f7, /* CMP16rr_REV */ /* Table664 */ 0x1ef, /* CMP16i16 */ /* Table665 */ 0x274, /* INC16r_alt */ /* Table666 */ 0x22a, /* DEC16r_alt */ /* Table667 */ 0x423, /* PUSH16r */ /* Table668 */ 0x404, /* POP16r */ /* Table669 */ 0x42f, /* PUSHA16 */ /* Table670 */ 0x40d, /* POPA16 */ /* Table671 */ 0x12c, /* BOUNDS16rm */ 0x0, /* */ /* Table673 */ 0x442, /* PUSHi16 */ /* Table674 */ 0x255, /* IMUL16rmi */ 0x258, /* IMUL16rri */ /* Table676 */ 0x422, /* PUSH16i8 */ /* Table677 */ 0x256, /* IMUL16rmi8 */ 0x259, /* IMUL16rri8 */ /* Table679 */ 0x280, /* INSW */ /* Table680 */ 0x3fa, /* OUTSW */ /* Table681 */ 0xab, /* ADD16mi */ 0x3cf, /* OR16mi */ 0x83, /* ADC16mi */ 0x4fe, /* SBB16mi */ 0xd3, /* AND16mi */ 0x5b5, /* SUB16mi */ 0x654, /* XOR16mi */ 0x1f0, /* CMP16mi */ 0xae, /* ADD16ri */ 0x3d2, /* OR16ri */ 0x86, /* ADC16ri */ 0x501, /* SBB16ri */ 0xd6, /* AND16ri */ 0x5b8, /* SUB16ri */ 0x657, /* XOR16ri */ 0x1f3, /* CMP16ri */ /* Table697 */ 0xac, /* ADD16mi8 */ 0x3d0, /* OR16mi8 */ 0x84, /* ADC16mi8 */ 0x4ff, /* SBB16mi8 */ 0xd4, /* AND16mi8 */ 0x5b6, /* SUB16mi8 */ 0x655, /* XOR16mi8 */ 0x1f1, /* CMP16mi8 */ 0xaf, /* ADD16ri8 */ 0x3d3, /* OR16ri8 */ 0x87, /* ADC16ri8 */ 0x502, /* SBB16ri8 */ 0xd7, /* AND16ri8 */ 0x5b9, /* SUB16ri8 */ 0x658, /* XOR16ri8 */ 0x1f4, /* CMP16ri8 */ /* Table713 */ 0x5e6, /* TEST16mr */ 0x5e9, /* TEST16rr */ /* Table715 */ 0x642, /* XCHG16rm */ 0x643, /* XCHG16rr */ /* Table717 */ 0x324, /* MOV16mr */ 0x32c, /* MOV16rr */ /* Table719 */ 0x32b, /* MOV16rm */ 0x32d, /* MOV16rr_REV */ /* Table721 */ 0x325, /* MOV16ms */ 0x32e, /* MOV16rs */ /* Table723 */ 0x2dd, /* LEA16r */ 0x0, /* */ /* Table725 */ 0x32f, /* MOV16sm */ 0x330, /* MOV16sr */ /* Table727 */ 0x405, /* POP16rmm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x406, /* POP16rmr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table743 */ 0x641, /* XCHG16ar */ /* Table744 */ 0x180, /* CBW */ /* Table745 */ 0x223, /* CWD */ /* Table746 */ 0x23d, /* FARCALL16i */ /* Table747 */ 0x437, /* PUSHF16 */ /* Table748 */ 0x413, /* POPF16 */ /* Table749 */ 0x321, /* MOV16ao32 */ /* Table750 */ 0x327, /* MOV16o32a */ /* Table751 */ 0x373, /* MOVSW */ /* Table752 */ 0x216, /* CMPSW */ /* Table753 */ 0x5e3, /* TEST16i16 */ /* Table754 */ 0x5af, /* STOSW */ /* Table755 */ 0x2fb, /* LODSW */ /* Table756 */ 0x524, /* SCASW */ /* Table757 */ 0x329, /* MOV16ri */ /* Table758 */ 0x492, /* ROL16mi */ 0x4aa, /* ROR16mi */ 0x446, /* RCL16mi */ 0x45e, /* RCR16mi */ 0x54b, /* SHL16mi */ 0x573, /* SHR16mi */ 0x4c9, /* SAL16mi */ 0x4e2, /* SAR16mi */ 0x495, /* ROL16ri */ 0x4ad, /* ROR16ri */ 0x449, /* RCL16ri */ 0x461, /* RCR16ri */ 0x54e, /* SHL16ri */ 0x576, /* SHR16ri */ 0x4cc, /* SAL16ri */ 0x4e5, /* SAR16ri */ /* Table774 */ 0x48b, /* RETIW */ /* Table775 */ 0x48e, /* RETW */ /* Table776 */ 0x2e3, /* LES16rm */ 0x0, /* */ /* Table778 */ 0x2db, /* LDS16rm */ 0x0, /* */ /* Table780 */ 0x323, /* MOV16mi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x32a, /* MOV16ri_alt */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table796 */ 0x301, /* LRETIW */ /* Table797 */ 0x304, /* LRETW */ /* Table798 */ 0x28f, /* IRET16 */ /* Table799 */ 0x490, /* ROL16m1 */ 0x4a8, /* ROR16m1 */ 0x444, /* RCL16m1 */ 0x45c, /* RCR16m1 */ 0x549, /* SHL16m1 */ 0x571, /* SHR16m1 */ 0x4c7, /* SAL16m1 */ 0x4e0, /* SAR16m1 */ 0x493, /* ROL16r1 */ 0x4ab, /* ROR16r1 */ 0x447, /* RCL16r1 */ 0x45f, /* RCR16r1 */ 0x54c, /* SHL16r1 */ 0x574, /* SHR16r1 */ 0x4ca, /* SAL16r1 */ 0x4e3, /* SAR16r1 */ /* Table815 */ 0x491, /* ROL16mCL */ 0x4a9, /* ROR16mCL */ 0x445, /* RCL16mCL */ 0x45d, /* RCR16mCL */ 0x54a, /* SHL16mCL */ 0x572, /* SHR16mCL */ 0x4c8, /* SAL16mCL */ 0x4e1, /* SAR16mCL */ 0x494, /* ROL16rCL */ 0x4ac, /* ROR16rCL */ 0x448, /* RCL16rCL */ 0x460, /* RCR16rCL */ 0x54d, /* SHL16rCL */ 0x575, /* SHR16rCL */ 0x4cb, /* SAL16rCL */ 0x4e4, /* SAR16rCL */ /* Table831 */ 0x26c, /* IN16ri */ /* Table832 */ 0x3f2, /* OUT16ir */ /* Table833 */ 0x17e, /* CALLpcrel16 */ /* Table834 */ 0x2bc, /* JMP_2 */ /* Table835 */ 0x242, /* FARJMP16i */ /* Table836 */ 0x26d, /* IN16rr */ /* Table837 */ 0x3f3, /* OUT16rr */ /* Table838 */ 0x5e4, /* TEST16mi */ 0x5e5, /* TEST16mi_alt */ 0x3c6, /* NOT16m */ 0x39f, /* NEG16m */ 0x392, /* MUL16m */ 0x252, /* IMUL16m */ 0x232, /* DIV16m */ 0x24a, /* IDIV16m */ 0x5e7, /* TEST16ri */ 0x5e8, /* TEST16ri_alt */ 0x3c7, /* NOT16r */ 0x3a0, /* NEG16r */ 0x393, /* MUL16r */ 0x253, /* IMUL16r */ 0x233, /* DIV16r */ 0x24b, /* IDIV16r */ /* Table854 */ 0x272, /* INC16m */ 0x228, /* DEC16m */ 0x171, /* CALL16m */ 0x23e, /* FARCALL16m */ 0x2af, /* JMP16m */ 0x243, /* FARJMP16m */ 0x424, /* PUSH16rmm */ 0x0, /* */ 0x273, /* INC16r */ 0x229, /* DEC16r */ 0x173, /* CALL16r */ 0x0, /* */ 0x2b1, /* JMP16r */ 0x0, /* */ 0x425, /* PUSH16rmr */ 0x0, /* */ /* Table870 */ 0x355, /* MOV8ao16 */ /* Table871 */ 0x331, /* MOV32ao16 */ /* Table872 */ 0x35b, /* MOV8o16a */ /* Table873 */ 0x338, /* MOV32o16a */ /* Table874 */ 0x29e, /* JCXZ */ /* Table875 */ 0x320, /* MOV16ao16 */ /* Table876 */ 0x326, /* MOV16o16a */ /* Table877 */ 0xbf, /* ADD64mr */ 0xc3, /* ADD64rr */ /* Table879 */ 0xc2, /* ADD64rm */ 0xc4, /* ADD64rr_REV */ /* Table881 */ 0xbc, /* ADD64i32 */ /* Table882 */ 0x3e3, /* OR64mr */ 0x3e7, /* OR64rr */ /* Table884 */ 0x3e6, /* OR64rm */ 0x3e8, /* OR64rr_REV */ /* Table886 */ 0x3e0, /* OR64i32 */ /* Table887 */ 0x97, /* ADC64mr */ 0x9b, /* ADC64rr */ /* Table889 */ 0x9a, /* ADC64rm */ 0x9c, /* ADC64rr_REV */ /* Table891 */ 0x94, /* ADC64i32 */ /* Table892 */ 0x512, /* SBB64mr */ 0x516, /* SBB64rr */ /* Table894 */ 0x515, /* SBB64rm */ 0x517, /* SBB64rr_REV */ /* Table896 */ 0x50f, /* SBB64i32 */ /* Table897 */ 0xe7, /* AND64mr */ 0xeb, /* AND64rr */ /* Table899 */ 0xea, /* AND64rm */ 0xec, /* AND64rr_REV */ /* Table901 */ 0xe4, /* AND64i32 */ /* Table902 */ 0x5c9, /* SUB64mr */ 0x5cd, /* SUB64rr */ /* Table904 */ 0x5cc, /* SUB64rm */ 0x5ce, /* SUB64rr_REV */ /* Table906 */ 0x5c6, /* SUB64i32 */ /* Table907 */ 0x668, /* XOR64mr */ 0x66c, /* XOR64rr */ /* Table909 */ 0x66b, /* XOR64rm */ 0x66d, /* XOR64rr_REV */ /* Table911 */ 0x665, /* XOR64i32 */ /* Table912 */ 0x204, /* CMP64mr */ 0x208, /* CMP64rr */ /* Table914 */ 0x207, /* CMP64rm */ 0x209, /* CMP64rr_REV */ /* Table916 */ 0x201, /* CMP64i32 */ /* Table917 */ 0x37f, /* MOVSX64rm32 */ 0x382, /* MOVSX64rr32 */ /* Table919 */ 0x265, /* IMUL64rmi32 */ 0x268, /* IMUL64rri32 */ /* Table921 */ 0x266, /* IMUL64rmi8 */ 0x269, /* IMUL64rri8 */ /* Table923 */ 0xbd, /* ADD64mi32 */ 0x3e1, /* OR64mi32 */ 0x95, /* ADC64mi32 */ 0x510, /* SBB64mi32 */ 0xe5, /* AND64mi32 */ 0x5c7, /* SUB64mi32 */ 0x666, /* XOR64mi32 */ 0x202, /* CMP64mi32 */ 0xc0, /* ADD64ri32 */ 0x3e4, /* OR64ri32 */ 0x98, /* ADC64ri32 */ 0x513, /* SBB64ri32 */ 0xe8, /* AND64ri32 */ 0x5ca, /* SUB64ri32 */ 0x669, /* XOR64ri32 */ 0x205, /* CMP64ri32 */ /* Table939 */ 0xbe, /* ADD64mi8 */ 0x3e2, /* OR64mi8 */ 0x96, /* ADC64mi8 */ 0x511, /* SBB64mi8 */ 0xe6, /* AND64mi8 */ 0x5c8, /* SUB64mi8 */ 0x667, /* XOR64mi8 */ 0x203, /* CMP64mi8 */ 0xc1, /* ADD64ri8 */ 0x3e5, /* OR64ri8 */ 0x99, /* ADC64ri8 */ 0x514, /* SBB64ri8 */ 0xe9, /* AND64ri8 */ 0x5cb, /* SUB64ri8 */ 0x66a, /* XOR64ri8 */ 0x206, /* CMP64ri8 */ /* Table955 */ 0x5f4, /* TEST64mr */ 0x5f7, /* TEST64rr */ /* Table957 */ 0x648, /* XCHG64rm */ 0x649, /* XCHG64rr */ /* Table959 */ 0x349, /* MOV64mr */ 0x351, /* MOV64rr */ /* Table961 */ 0x350, /* MOV64rm */ 0x352, /* MOV64rr_REV */ /* Table963 */ 0x325, /* MOV16ms */ 0x353, /* MOV64rs */ /* Table965 */ 0x2e0, /* LEA64r */ 0x0, /* */ /* Table967 */ 0x32f, /* MOV16sm */ 0x354, /* MOV64sr */ /* Table969 */ 0x647, /* XCHG64ar */ /* Table970 */ 0x182, /* CDQE */ /* Table971 */ 0x222, /* CQO */ /* Table972 */ 0x345, /* MOV64ao64 */ /* Table973 */ 0x34b, /* MOV64o64a */ /* Table974 */ 0x372, /* MOVSQ */ /* Table975 */ 0x215, /* CMPSQ */ /* Table976 */ 0x5f1, /* TEST64i32 */ /* Table977 */ 0x5ae, /* STOSQ */ /* Table978 */ 0x2fa, /* LODSQ */ /* Table979 */ 0x523, /* SCASQ */ /* Table980 */ 0x34e, /* MOV64ri */ /* Table981 */ 0x49e, /* ROL64mi */ 0x4b6, /* ROR64mi */ 0x452, /* RCL64mi */ 0x46a, /* RCR64mi */ 0x557, /* SHL64mi */ 0x57f, /* SHR64mi */ 0x4d5, /* SAL64mi */ 0x4ee, /* SAR64mi */ 0x4a1, /* ROL64ri */ 0x4b9, /* ROR64ri */ 0x455, /* RCL64ri */ 0x46d, /* RCR64ri */ 0x55a, /* SHL64ri */ 0x582, /* SHR64ri */ 0x4d8, /* SAL64ri */ 0x4f1, /* SAR64ri */ /* Table997 */ 0x348, /* MOV64mi32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x34f, /* MOV64ri32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1013 */ 0x300, /* LRETIQ */ /* Table1014 */ 0x303, /* LRETQ */ /* Table1015 */ 0x291, /* IRET64 */ /* Table1016 */ 0x49c, /* ROL64m1 */ 0x4b4, /* ROR64m1 */ 0x450, /* RCL64m1 */ 0x468, /* RCR64m1 */ 0x555, /* SHL64m1 */ 0x57d, /* SHR64m1 */ 0x4d3, /* SAL64m1 */ 0x4ec, /* SAR64m1 */ 0x49f, /* ROL64r1 */ 0x4b7, /* ROR64r1 */ 0x453, /* RCL64r1 */ 0x46b, /* RCR64r1 */ 0x558, /* SHL64r1 */ 0x580, /* SHR64r1 */ 0x4d6, /* SAL64r1 */ 0x4ef, /* SAR64r1 */ /* Table1032 */ 0x49d, /* ROL64mCL */ 0x4b5, /* ROR64mCL */ 0x451, /* RCL64mCL */ 0x469, /* RCR64mCL */ 0x556, /* SHL64mCL */ 0x57e, /* SHR64mCL */ 0x4d4, /* SAL64mCL */ 0x4ed, /* SAR64mCL */ 0x4a0, /* ROL64rCL */ 0x4b8, /* ROR64rCL */ 0x454, /* RCL64rCL */ 0x46c, /* RCR64rCL */ 0x559, /* SHL64rCL */ 0x581, /* SHR64rCL */ 0x4d7, /* SAL64rCL */ 0x4f0, /* SAR64rCL */ /* Table1048 */ 0x5f2, /* TEST64mi32 */ 0x5f3, /* TEST64mi32_alt */ 0x3ca, /* NOT64m */ 0x3a3, /* NEG64m */ 0x396, /* MUL64m */ 0x262, /* IMUL64m */ 0x236, /* DIV64m */ 0x24e, /* IDIV64m */ 0x5f5, /* TEST64ri32 */ 0x5f6, /* TEST64ri32_alt */ 0x3cb, /* NOT64r */ 0x3a4, /* NEG64r */ 0x397, /* MUL64r */ 0x263, /* IMUL64r */ 0x237, /* DIV64r */ 0x24f, /* IDIV64r */ /* Table1064 */ 0x278, /* INC64m */ 0x22e, /* DEC64m */ 0x179, /* CALL64m */ 0x241, /* FARCALL64 */ 0x2b7, /* JMP64m */ 0x246, /* FARJMP64 */ 0x42d, /* PUSH64rmm */ 0x0, /* */ 0x279, /* INC64r */ 0x22f, /* DEC64r */ 0x17c, /* CALL64r */ 0x0, /* */ 0x2b9, /* JMP64r */ 0x0, /* */ 0x42e, /* PUSH64rmr */ 0x0, /* */ /* Table1080 */ 0x344, /* MOV64ao32 */ /* Table1081 */ 0x34a, /* MOV64o32a */ /* Table1082 */ 0x278, /* INC64m */ 0x22e, /* DEC64m */ 0x179, /* CALL64m */ 0x241, /* FARCALL64 */ 0x2b7, /* JMP64m */ 0x246, /* FARJMP64 */ 0x424, /* PUSH16rmm */ 0x0, /* */ 0x279, /* INC64r */ 0x22f, /* DEC64r */ 0x17c, /* CALL64r */ 0x0, /* */ 0x2b9, /* JMP64r */ 0x0, /* */ 0x425, /* PUSH16rmr */ 0x0, /* */ /* Table1098 */ 0x322, /* MOV16ao64 */ /* Table1099 */ 0x328, /* MOV16o64a */ /* Table1100 */ 0x272, /* INC16m */ 0x228, /* DEC16m */ 0x179, /* CALL64m */ 0x23e, /* FARCALL16m */ 0x2b7, /* JMP64m */ 0x243, /* FARJMP16m */ 0x424, /* PUSH16rmm */ 0x0, /* */ 0x273, /* INC16r */ 0x229, /* DEC16r */ 0x17c, /* CALL64r */ 0x0, /* */ 0x2b9, /* JMP64r */ 0x0, /* */ 0x425, /* PUSH16rmr */ 0x0, /* */ /* Table1116 */ 0x59d, /* SLDT16m */ 0x5b3, /* STRm */ 0x2f1, /* LLDT16m */ 0x30e, /* LTRm */ 0x611, /* VERRm */ 0x613, /* VERWm */ 0x0, /* */ 0x0, /* */ 0x59f, /* SLDT32r */ 0x5b1, /* STR32r */ 0x2f2, /* LLDT16r */ 0x30f, /* LTRr */ 0x612, /* VERRr */ 0x614, /* VERWr */ 0x0, /* */ 0x0, /* */ /* Table1132 */ 0x547, /* SGDT32m */ 0x59a, /* SIDT32m */ 0x2e9, /* LGDT32m */ 0x2ef, /* LIDT32m */ 0x5a3, /* SMSW16m */ 0x0, /* */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x623, /* VMRUN32 */ 0x61b, /* VMMCALL */ 0x619, /* VMLOAD32 */ 0x625, /* VMSAVE32 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x289, /* INVLPGA32 */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1204 */ 0x2d7, /* LAR32rm */ 0x2d8, /* LAR32rr */ /* Table1206 */ 0x307, /* LSL32rm */ 0x308, /* LSL32rr */ /* Table1208 */ 0x5d9, /* SYSCALL */ /* Table1209 */ 0x18b, /* CLTS */ /* Table1210 */ 0x5dd, /* SYSRET */ /* Table1211 */ 0x285, /* INVD */ /* Table1212 */ 0x62d, /* WBINVD */ /* Table1213 */ 0x60c, /* UD2 */ /* Table1214 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b0, /* NOOP18_m4 */ 0x3b1, /* NOOP18_m5 */ 0x3b2, /* NOOP18_m6 */ 0x3b3, /* NOOP18_m7 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3b4, /* NOOP18_r4 */ 0x3b5, /* NOOP18_r5 */ 0x3b6, /* NOOP18_r6 */ 0x3b7, /* NOOP18_r7 */ /* Table1230 */ 0x3ba, /* NOOPL_19 */ 0x3b8, /* NOOP19rr */ /* Table1232 */ 0x186, /* CLDEMOTE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1248 */ 0x3bb, /* NOOPL_1d */ 0x0, /* */ /* Table1250 */ 0x3bc, /* NOOPL_1e */ 0x0, /* */ /* Table1252 */ 0x3b9, /* NOOPL */ 0x3bd, /* NOOPLr */ /* Table1254 */ 0x0, /* */ 0x33b, /* MOV32rc */ /* Table1256 */ 0x0, /* */ 0x33c, /* MOV32rd */ /* Table1258 */ 0x0, /* */ 0x334, /* MOV32cr */ /* Table1260 */ 0x0, /* */ 0x335, /* MOV32dr */ /* Table1262 */ 0x633, /* WRMSR */ /* Table1263 */ 0x485, /* RDTSC */ /* Table1264 */ 0x478, /* RDMSR */ /* Table1265 */ 0x47c, /* RDPMC */ /* Table1266 */ 0x5da, /* SYSENTER */ /* Table1267 */ 0x5db, /* SYSEXIT */ /* Table1268 */ 0x248, /* GETSEC */ /* Table1269 */ 0x1df, /* CMOVO32rm */ 0x1e0, /* CMOVO32rr */ /* Table1271 */ 0x1cd, /* CMOVNO32rm */ 0x1ce, /* CMOVNO32rr */ /* Table1273 */ 0x19d, /* CMOVB32rm */ 0x19e, /* CMOVB32rr */ /* Table1275 */ 0x197, /* CMOVAE32rm */ 0x198, /* CMOVAE32rr */ /* Table1277 */ 0x1a9, /* CMOVE32rm */ 0x1aa, /* CMOVE32rr */ /* Table1279 */ 0x1c7, /* CMOVNE32rm */ 0x1c8, /* CMOVNE32rr */ /* Table1281 */ 0x1a3, /* CMOVBE32rm */ 0x1a4, /* CMOVBE32rr */ /* Table1283 */ 0x191, /* CMOVA32rm */ 0x192, /* CMOVA32rr */ /* Table1285 */ 0x1eb, /* CMOVS32rm */ 0x1ec, /* CMOVS32rr */ /* Table1287 */ 0x1d9, /* CMOVNS32rm */ 0x1da, /* CMOVNS32rr */ /* Table1289 */ 0x1e5, /* CMOVP32rm */ 0x1e6, /* CMOVP32rr */ /* Table1291 */ 0x1d3, /* CMOVNP32rm */ 0x1d4, /* CMOVNP32rr */ /* Table1293 */ 0x1bb, /* CMOVL32rm */ 0x1bc, /* CMOVL32rr */ /* Table1295 */ 0x1b5, /* CMOVGE32rm */ 0x1b6, /* CMOVGE32rr */ /* Table1297 */ 0x1c1, /* CMOVLE32rm */ 0x1c2, /* CMOVLE32rr */ /* Table1299 */ 0x1af, /* CMOVG32rm */ 0x1b0, /* CMOVG32rr */ /* Table1301 */ 0x61e, /* VMREAD32mr */ 0x61f, /* VMREAD32rr */ /* Table1303 */ 0x627, /* VMWRITE32rm */ 0x628, /* VMWRITE32rr */ /* Table1305 */ 0x2cc, /* JO_4 */ /* Table1306 */ 0x2c3, /* JNO_4 */ /* Table1307 */ 0x29d, /* JB_4 */ /* Table1308 */ 0x294, /* JAE_4 */ /* Table1309 */ 0x2a2, /* JE_4 */ /* Table1310 */ 0x2c0, /* JNE_4 */ /* Table1311 */ 0x29a, /* JBE_4 */ /* Table1312 */ 0x297, /* JA_4 */ /* Table1313 */ 0x2d3, /* JS_4 */ /* Table1314 */ 0x2c9, /* JNS_4 */ /* Table1315 */ 0x2cf, /* JP_4 */ /* Table1316 */ 0x2c6, /* JNP_4 */ /* Table1317 */ 0x2ae, /* JL_4 */ /* Table1318 */ 0x2a5, /* JGE_4 */ /* Table1319 */ 0x2ab, /* JLE_4 */ /* Table1320 */ 0x2a8, /* JG_4 */ /* Table1321 */ 0x53f, /* SETOm */ 0x540, /* SETOr */ /* Table1323 */ 0x539, /* SETNOm */ 0x53a, /* SETNOr */ /* Table1325 */ 0x52b, /* SETBm */ 0x52c, /* SETBr */ /* Table1327 */ 0x525, /* SETAEm */ 0x526, /* SETAEr */ /* Table1329 */ 0x52d, /* SETEm */ 0x52e, /* SETEr */ /* Table1331 */ 0x537, /* SETNEm */ 0x538, /* SETNEr */ /* Table1333 */ 0x529, /* SETBEm */ 0x52a, /* SETBEr */ /* Table1335 */ 0x527, /* SETAm */ 0x528, /* SETAr */ /* Table1337 */ 0x544, /* SETSm */ 0x545, /* SETSr */ /* Table1339 */ 0x53d, /* SETNSm */ 0x53e, /* SETNSr */ /* Table1341 */ 0x541, /* SETPm */ 0x542, /* SETPr */ /* Table1343 */ 0x53b, /* SETNPm */ 0x53c, /* SETNPr */ /* Table1345 */ 0x535, /* SETLm */ 0x536, /* SETLr */ /* Table1347 */ 0x52f, /* SETGEm */ 0x530, /* SETGEr */ /* Table1349 */ 0x533, /* SETLEm */ 0x534, /* SETLEr */ /* Table1351 */ 0x531, /* SETGm */ 0x532, /* SETGr */ /* Table1353 */ 0x43b, /* PUSHFS32 */ /* Table1354 */ 0x417, /* POPFS32 */ /* Table1355 */ 0x221, /* CPUID */ /* Table1356 */ 0x142, /* BT32mr */ 0x144, /* BT32rr */ /* Table1358 */ 0x566, /* SHLD32mri8 */ 0x568, /* SHLD32rri8 */ /* Table1360 */ 0x565, /* SHLD32mrCL */ 0x567, /* SHLD32rrCL */ /* Table1362 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x31f, /* MONTMUL */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x684, /* XSHA1 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x685, /* XSHA256 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1434 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x686, /* XSTORE */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x64f, /* XCRYPTECB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x64c, /* XCRYPTCBC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x64e, /* XCRYPTCTR */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x64d, /* XCRYPTCFB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x650, /* XCRYPTOFB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1506 */ 0x43e, /* PUSHGS32 */ /* Table1507 */ 0x41a, /* POPGS32 */ /* Table1508 */ 0x4c4, /* RSM */ /* Table1509 */ 0x166, /* BTS32mr */ 0x168, /* BTS32rr */ /* Table1511 */ 0x58e, /* SHRD32mri8 */ 0x590, /* SHRD32rri8 */ /* Table1513 */ 0x58d, /* SHRD32mrCL */ 0x58f, /* SHRD32rrCL */ /* Table1515 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x67b, /* XSAVE */ 0x677, /* XRSTOR */ 0x67f, /* XSAVEOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1531 */ 0x25c, /* IMUL32rm */ 0x25f, /* IMUL32rr */ /* Table1533 */ 0x21f, /* CMPXCHG8rm */ 0x220, /* CMPXCHG8rr */ /* Table1535 */ 0x21a, /* CMPXCHG32rm */ 0x21b, /* CMPXCHG32rr */ /* Table1537 */ 0x30c, /* LSS32rm */ 0x0, /* */ /* Table1539 */ 0x15a, /* BTR32mr */ 0x15c, /* BTR32rr */ /* Table1541 */ 0x2e6, /* LFS32rm */ 0x0, /* */ /* Table1543 */ 0x2ec, /* LGS32rm */ 0x0, /* */ /* Table1545 */ 0x389, /* MOVZX32rm8 */ 0x38c, /* MOVZX32rr8 */ /* Table1547 */ 0x388, /* MOVZX32rm16 */ 0x38b, /* MOVZX32rr16 */ /* Table1549 */ 0x60b, /* UD1 */ /* Table1550 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x141, /* BT32mi8 */ 0x165, /* BTS32mi8 */ 0x159, /* BTR32mi8 */ 0x14d, /* BTC32mi8 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x143, /* BT32ri8 */ 0x167, /* BTS32ri8 */ 0x15b, /* BTR32ri8 */ 0x14f, /* BTC32ri8 */ /* Table1566 */ 0x14e, /* BTC32mr */ 0x150, /* BTC32rr */ /* Table1568 */ 0x130, /* BSF32rm */ 0x131, /* BSF32rr */ /* Table1570 */ 0x136, /* BSR32rm */ 0x137, /* BSR32rr */ /* Table1572 */ 0x379, /* MOVSX32rm8 */ 0x37c, /* MOVSX32rr8 */ /* Table1574 */ 0x378, /* MOVSX32rm16 */ 0x37b, /* MOVSX32rr16 */ /* Table1576 */ 0x63f, /* XADD8rm */ 0x640, /* XADD8rr */ /* Table1578 */ 0x63b, /* XADD32rm */ 0x63c, /* XADD32rr */ /* Table1580 */ 0x0, /* */ 0x21e, /* CMPXCHG8B */ 0x0, /* */ 0x679, /* XRSTORS */ 0x67d, /* XSAVEC */ 0x681, /* XSAVES */ 0x61c, /* VMPTRLDm */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47e, /* RDRAND32r */ 0x481, /* RDSEED32r */ /* Table1596 */ 0x13b, /* BSWAP32r */ /* Table1597 */ 0x60a, /* UD0 */ /* Table1598 */ 0x548, /* SGDT64m */ 0x59b, /* SIDT64m */ 0x2ea, /* LGDT64m */ 0x2f0, /* LIDT64m */ 0x5a3, /* SMSW16m */ 0x0, /* */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x624, /* VMRUN64 */ 0x61b, /* VMMCALL */ 0x61a, /* VMLOAD64 */ 0x626, /* VMSAVE64 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x28a, /* INVLPGA64 */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1670 */ 0x0, /* */ 0x34c, /* MOV64rc */ /* Table1672 */ 0x0, /* */ 0x34d, /* MOV64rd */ /* Table1674 */ 0x0, /* */ 0x346, /* MOV64cr */ /* Table1676 */ 0x0, /* */ 0x347, /* MOV64dr */ /* Table1678 */ 0x620, /* VMREAD64mr */ 0x621, /* VMREAD64rr */ /* Table1680 */ 0x629, /* VMWRITE64rm */ 0x62a, /* VMWRITE64rr */ /* Table1682 */ 0x43c, /* PUSHFS64 */ /* Table1683 */ 0x418, /* POPFS64 */ /* Table1684 */ 0x43f, /* PUSHGS64 */ /* Table1685 */ 0x41b, /* POPGS64 */ /* Table1686 */ 0x59d, /* SLDT16m */ 0x5b3, /* STRm */ 0x2f1, /* LLDT16m */ 0x30e, /* LTRm */ 0x611, /* VERRm */ 0x613, /* VERWm */ 0x0, /* */ 0x0, /* */ 0x59e, /* SLDT16r */ 0x5b0, /* STR16r */ 0x2f2, /* LLDT16r */ 0x30f, /* LTRr */ 0x612, /* VERRr */ 0x614, /* VERWr */ 0x0, /* */ 0x0, /* */ /* Table1702 */ 0x546, /* SGDT16m */ 0x599, /* SIDT16m */ 0x2e8, /* LGDT16m */ 0x2ee, /* LIDT16m */ 0x5a3, /* SMSW16m */ 0x0, /* */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x623, /* VMRUN32 */ 0x61b, /* VMMCALL */ 0x619, /* VMLOAD32 */ 0x625, /* VMSAVE32 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x289, /* INVLPGA32 */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table1774 */ 0x2d5, /* LAR16rm */ 0x2d6, /* LAR16rr */ /* Table1776 */ 0x305, /* LSL16rm */ 0x306, /* LSL16rr */ /* Table1778 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3a8, /* NOOP18_16m4 */ 0x3a9, /* NOOP18_16m5 */ 0x3aa, /* NOOP18_16m6 */ 0x3ab, /* NOOP18_16m7 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x3ac, /* NOOP18_16r4 */ 0x3ad, /* NOOP18_16r5 */ 0x3ae, /* NOOP18_16r6 */ 0x3af, /* NOOP18_16r7 */ /* Table1794 */ 0x3c1, /* NOOPW_19 */ 0x3b8, /* NOOP19rr */ /* Table1796 */ 0x3c2, /* NOOPW_1c */ 0x0, /* */ /* Table1798 */ 0x3c3, /* NOOPW_1d */ 0x0, /* */ /* Table1800 */ 0x3c4, /* NOOPW_1e */ 0x0, /* */ /* Table1802 */ 0x3c0, /* NOOPW */ 0x3c5, /* NOOPWr */ /* Table1804 */ 0x1dd, /* CMOVO16rm */ 0x1de, /* CMOVO16rr */ /* Table1806 */ 0x1cb, /* CMOVNO16rm */ 0x1cc, /* CMOVNO16rr */ /* Table1808 */ 0x19b, /* CMOVB16rm */ 0x19c, /* CMOVB16rr */ /* Table1810 */ 0x195, /* CMOVAE16rm */ 0x196, /* CMOVAE16rr */ /* Table1812 */ 0x1a7, /* CMOVE16rm */ 0x1a8, /* CMOVE16rr */ /* Table1814 */ 0x1c5, /* CMOVNE16rm */ 0x1c6, /* CMOVNE16rr */ /* Table1816 */ 0x1a1, /* CMOVBE16rm */ 0x1a2, /* CMOVBE16rr */ /* Table1818 */ 0x18f, /* CMOVA16rm */ 0x190, /* CMOVA16rr */ /* Table1820 */ 0x1e9, /* CMOVS16rm */ 0x1ea, /* CMOVS16rr */ /* Table1822 */ 0x1d7, /* CMOVNS16rm */ 0x1d8, /* CMOVNS16rr */ /* Table1824 */ 0x1e3, /* CMOVP16rm */ 0x1e4, /* CMOVP16rr */ /* Table1826 */ 0x1d1, /* CMOVNP16rm */ 0x1d2, /* CMOVNP16rr */ /* Table1828 */ 0x1b9, /* CMOVL16rm */ 0x1ba, /* CMOVL16rr */ /* Table1830 */ 0x1b3, /* CMOVGE16rm */ 0x1b4, /* CMOVGE16rr */ /* Table1832 */ 0x1bf, /* CMOVLE16rm */ 0x1c0, /* CMOVLE16rr */ /* Table1834 */ 0x1ad, /* CMOVG16rm */ 0x1ae, /* CMOVG16rr */ /* Table1836 */ 0x2cb, /* JO_2 */ /* Table1837 */ 0x2c2, /* JNO_2 */ /* Table1838 */ 0x29c, /* JB_2 */ /* Table1839 */ 0x293, /* JAE_2 */ /* Table1840 */ 0x2a1, /* JE_2 */ /* Table1841 */ 0x2bf, /* JNE_2 */ /* Table1842 */ 0x299, /* JBE_2 */ /* Table1843 */ 0x296, /* JA_2 */ /* Table1844 */ 0x2d2, /* JS_2 */ /* Table1845 */ 0x2c8, /* JNS_2 */ /* Table1846 */ 0x2ce, /* JP_2 */ /* Table1847 */ 0x2c5, /* JNP_2 */ /* Table1848 */ 0x2ad, /* JL_2 */ /* Table1849 */ 0x2a4, /* JGE_2 */ /* Table1850 */ 0x2aa, /* JLE_2 */ /* Table1851 */ 0x2a7, /* JG_2 */ /* Table1852 */ 0x43a, /* PUSHFS16 */ /* Table1853 */ 0x416, /* POPFS16 */ /* Table1854 */ 0x13e, /* BT16mr */ 0x140, /* BT16rr */ /* Table1856 */ 0x562, /* SHLD16mri8 */ 0x564, /* SHLD16rri8 */ /* Table1858 */ 0x561, /* SHLD16mrCL */ 0x563, /* SHLD16rrCL */ /* Table1860 */ 0x43d, /* PUSHGS16 */ /* Table1861 */ 0x419, /* POPGS16 */ /* Table1862 */ 0x162, /* BTS16mr */ 0x164, /* BTS16rr */ /* Table1864 */ 0x58a, /* SHRD16mri8 */ 0x58c, /* SHRD16rri8 */ /* Table1866 */ 0x589, /* SHRD16mrCL */ 0x58b, /* SHRD16rrCL */ /* Table1868 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x18c, /* CLWB */ 0x187, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5ff, /* TPAUSE */ 0x0, /* */ /* Table1884 */ 0x254, /* IMUL16rm */ 0x257, /* IMUL16rr */ /* Table1886 */ 0x218, /* CMPXCHG16rm */ 0x219, /* CMPXCHG16rr */ /* Table1888 */ 0x30b, /* LSS16rm */ 0x0, /* */ /* Table1890 */ 0x156, /* BTR16mr */ 0x158, /* BTR16rr */ /* Table1892 */ 0x2e5, /* LFS16rm */ 0x0, /* */ /* Table1894 */ 0x2eb, /* LGS16rm */ 0x0, /* */ /* Table1896 */ 0x385, /* MOVZX16rm8 */ 0x387, /* MOVZX16rr8 */ /* Table1898 */ 0x384, /* MOVZX16rm16 */ 0x386, /* MOVZX16rr16 */ /* Table1900 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x13d, /* BT16mi8 */ 0x161, /* BTS16mi8 */ 0x155, /* BTR16mi8 */ 0x149, /* BTC16mi8 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x13f, /* BT16ri8 */ 0x163, /* BTS16ri8 */ 0x157, /* BTR16ri8 */ 0x14b, /* BTC16ri8 */ /* Table1916 */ 0x14a, /* BTC16mr */ 0x14c, /* BTC16rr */ /* Table1918 */ 0x12e, /* BSF16rm */ 0x12f, /* BSF16rr */ /* Table1920 */ 0x134, /* BSR16rm */ 0x135, /* BSR16rr */ /* Table1922 */ 0x375, /* MOVSX16rm8 */ 0x377, /* MOVSX16rr8 */ /* Table1924 */ 0x374, /* MOVSX16rm16 */ 0x376, /* MOVSX16rr16 */ /* Table1926 */ 0x639, /* XADD16rm */ 0x63a, /* XADD16rr */ /* Table1928 */ 0x0, /* */ 0x21e, /* CMPXCHG8B */ 0x0, /* */ 0x679, /* XRSTORS */ 0x67d, /* XSAVEC */ 0x681, /* XSAVES */ 0x616, /* VMCLEARm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47d, /* RDRAND16r */ 0x480, /* RDSEED16r */ /* Table1944 */ 0x13a, /* BSWAP16r_BAD */ /* Table1945 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x67b, /* XSAVE */ 0x677, /* XRSTOR */ 0x18c, /* CLWB */ 0x187, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5ff, /* TPAUSE */ 0x0, /* */ /* Table1961 */ 0x0, /* */ 0x21e, /* CMPXCHG8B */ 0x0, /* */ 0x679, /* XRSTORS */ 0x67d, /* XSAVEC */ 0x681, /* XSAVES */ 0x616, /* VMCLEARm */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47d, /* RDRAND16r */ 0x480, /* RDSEED16r */ /* Table1977 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x610, /* UMWAIT */ 0x0, /* */ /* Table1993 */ 0x0, /* */ 0x21e, /* CMPXCHG8B */ 0x0, /* */ 0x679, /* XRSTORS */ 0x67d, /* XSAVEC */ 0x681, /* XSAVES */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2009 */ 0x547, /* SGDT32m */ 0x59a, /* SIDT32m */ 0x2e9, /* LGDT32m */ 0x2ef, /* LIDT32m */ 0x5a3, /* SMSW16m */ 0x4c5, /* RSTORSSP */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x623, /* VMRUN32 */ 0x61b, /* VMMCALL */ 0x619, /* VMLOAD32 */ 0x625, /* VMSAVE32 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x289, /* INVLPGA32 */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x543, /* SETSSBSY */ 0x0, /* */ 0x4fc, /* SAVEPREVSSP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2081 */ 0x62e, /* WBNOINVD */ /* Table2082 */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x483, /* RDSSPD */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x23b, /* ENDBR64 */ 0x23a, /* ENDBR32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2154 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x420, /* PTWRITEm */ 0x0, /* */ 0x18a, /* CLRSSBSY */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x421, /* PTWRITEr */ 0x27c, /* INCSSPD */ 0x60e, /* UMONITOR32 */ 0x0, /* */ /* Table2170 */ 0x602, /* TZCNT32rm */ 0x603, /* TZCNT32rr */ /* Table2172 */ 0x31a, /* LZCNT32rm */ 0x31b, /* LZCNT32rr */ /* Table2174 */ 0x0, /* */ 0x21e, /* CMPXCHG8B */ 0x0, /* */ 0x679, /* XRSTORS */ 0x67d, /* XSAVEC */ 0x681, /* XSAVES */ 0x62c, /* VMXON */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x479, /* RDPID32 */ /* Table2190 */ 0x600, /* TZCNT16rm */ 0x601, /* TZCNT16rr */ /* Table2192 */ 0x318, /* LZCNT16rm */ 0x319, /* LZCNT16rr */ /* Table2194 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x60d, /* UMONITOR16 */ 0x0, /* */ /* Table2210 */ 0x59d, /* SLDT16m */ 0x5b3, /* STRm */ 0x2f1, /* LLDT16m */ 0x30e, /* LTRm */ 0x611, /* VERRm */ 0x613, /* VERWm */ 0x0, /* */ 0x0, /* */ 0x5a0, /* SLDT64r */ 0x5b2, /* STR64r */ 0x2f2, /* LLDT16r */ 0x30f, /* LTRr */ 0x612, /* VERRr */ 0x614, /* VERWr */ 0x0, /* */ 0x0, /* */ /* Table2226 */ 0x548, /* SGDT64m */ 0x59b, /* SIDT64m */ 0x2ea, /* LGDT64m */ 0x2f0, /* LIDT64m */ 0x5a3, /* SMSW16m */ 0x0, /* */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x624, /* VMRUN64 */ 0x61b, /* VMMCALL */ 0x61a, /* VMLOAD64 */ 0x626, /* VMSAVE64 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x28a, /* INVLPGA64 */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2298 */ 0x2d9, /* LAR64rm */ 0x2da, /* LAR64rr */ /* Table2300 */ 0x309, /* LSL64rm */ 0x30a, /* LSL64rr */ /* Table2302 */ 0x5de, /* SYSRET64 */ /* Table2303 */ 0x3be, /* NOOPQ */ 0x3bf, /* NOOPQr */ /* Table2305 */ 0x5dc, /* SYSEXIT64 */ /* Table2306 */ 0x1e1, /* CMOVO64rm */ 0x1e2, /* CMOVO64rr */ /* Table2308 */ 0x1cf, /* CMOVNO64rm */ 0x1d0, /* CMOVNO64rr */ /* Table2310 */ 0x19f, /* CMOVB64rm */ 0x1a0, /* CMOVB64rr */ /* Table2312 */ 0x199, /* CMOVAE64rm */ 0x19a, /* CMOVAE64rr */ /* Table2314 */ 0x1ab, /* CMOVE64rm */ 0x1ac, /* CMOVE64rr */ /* Table2316 */ 0x1c9, /* CMOVNE64rm */ 0x1ca, /* CMOVNE64rr */ /* Table2318 */ 0x1a5, /* CMOVBE64rm */ 0x1a6, /* CMOVBE64rr */ /* Table2320 */ 0x193, /* CMOVA64rm */ 0x194, /* CMOVA64rr */ /* Table2322 */ 0x1ed, /* CMOVS64rm */ 0x1ee, /* CMOVS64rr */ /* Table2324 */ 0x1db, /* CMOVNS64rm */ 0x1dc, /* CMOVNS64rr */ /* Table2326 */ 0x1e7, /* CMOVP64rm */ 0x1e8, /* CMOVP64rr */ /* Table2328 */ 0x1d5, /* CMOVNP64rm */ 0x1d6, /* CMOVNP64rr */ /* Table2330 */ 0x1bd, /* CMOVL64rm */ 0x1be, /* CMOVL64rr */ /* Table2332 */ 0x1b7, /* CMOVGE64rm */ 0x1b8, /* CMOVGE64rr */ /* Table2334 */ 0x1c3, /* CMOVLE64rm */ 0x1c4, /* CMOVLE64rr */ /* Table2336 */ 0x1b1, /* CMOVG64rm */ 0x1b2, /* CMOVG64rr */ /* Table2338 */ 0x146, /* BT64mr */ 0x148, /* BT64rr */ /* Table2340 */ 0x56a, /* SHLD64mri8 */ 0x56c, /* SHLD64rri8 */ /* Table2342 */ 0x569, /* SHLD64mrCL */ 0x56b, /* SHLD64rrCL */ /* Table2344 */ 0x16a, /* BTS64mr */ 0x16c, /* BTS64rr */ /* Table2346 */ 0x592, /* SHRD64mri8 */ 0x594, /* SHRD64rri8 */ /* Table2348 */ 0x591, /* SHRD64mrCL */ 0x593, /* SHRD64rrCL */ /* Table2350 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x67c, /* XSAVE64 */ 0x678, /* XRSTOR64 */ 0x680, /* XSAVEOPT64 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2366 */ 0x264, /* IMUL64rm */ 0x267, /* IMUL64rr */ /* Table2368 */ 0x21c, /* CMPXCHG64rm */ 0x21d, /* CMPXCHG64rr */ /* Table2370 */ 0x30d, /* LSS64rm */ 0x0, /* */ /* Table2372 */ 0x15e, /* BTR64mr */ 0x160, /* BTR64rr */ /* Table2374 */ 0x2e7, /* LFS64rm */ 0x0, /* */ /* Table2376 */ 0x2ed, /* LGS64rm */ 0x0, /* */ /* Table2378 */ 0x38f, /* MOVZX64rm8 */ 0x391, /* MOVZX64rr8 */ /* Table2380 */ 0x38e, /* MOVZX64rm16 */ 0x390, /* MOVZX64rr16 */ /* Table2382 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x145, /* BT64mi8 */ 0x169, /* BTS64mi8 */ 0x15d, /* BTR64mi8 */ 0x151, /* BTC64mi8 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x147, /* BT64ri8 */ 0x16b, /* BTS64ri8 */ 0x15f, /* BTR64ri8 */ 0x153, /* BTC64ri8 */ /* Table2398 */ 0x152, /* BTC64mr */ 0x154, /* BTC64rr */ /* Table2400 */ 0x132, /* BSF64rm */ 0x133, /* BSF64rr */ /* Table2402 */ 0x138, /* BSR64rm */ 0x139, /* BSR64rr */ /* Table2404 */ 0x380, /* MOVSX64rm8 */ 0x383, /* MOVSX64rr8 */ /* Table2406 */ 0x37e, /* MOVSX64rm16 */ 0x381, /* MOVSX64rr16 */ /* Table2408 */ 0x63d, /* XADD64rm */ 0x63e, /* XADD64rr */ /* Table2410 */ 0x0, /* */ 0x217, /* CMPXCHG16B */ 0x0, /* */ 0x67a, /* XRSTORS64 */ 0x67e, /* XSAVEC64 */ 0x682, /* XSAVES64 */ 0x61c, /* VMPTRLDm */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47f, /* RDRAND64r */ 0x482, /* RDSEED64r */ /* Table2426 */ 0x13c, /* BSWAP64r */ /* Table2427 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x67c, /* XSAVE64 */ 0x678, /* XRSTOR64 */ 0x680, /* XSAVEOPT64 */ 0x187, /* CLFLUSHOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x5ff, /* TPAUSE */ 0x0, /* */ /* Table2443 */ 0x0, /* */ 0x217, /* CMPXCHG16B */ 0x0, /* */ 0x67a, /* XRSTORS64 */ 0x67e, /* XSAVEC64 */ 0x682, /* XSAVES64 */ 0x616, /* VMCLEARm */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47f, /* RDRAND64r */ 0x482, /* RDSEED64r */ /* Table2459 */ 0x548, /* SGDT64m */ 0x59b, /* SIDT64m */ 0x2ea, /* LGDT64m */ 0x2f0, /* LIDT64m */ 0x5a3, /* SMSW16m */ 0x0, /* */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x624, /* VMRUN64 */ 0x61b, /* VMMCALL */ 0x61a, /* VMLOAD64 */ 0x626, /* VMSAVE64 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x28a, /* INVLPGA64 */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x5a4, /* SMSW16r */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2531 */ 0x548, /* SGDT64m */ 0x59b, /* SIDT64m */ 0x2ea, /* LGDT64m */ 0x2f0, /* LIDT64m */ 0x5a3, /* SMSW16m */ 0x4c5, /* RSTORSSP */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x624, /* VMRUN64 */ 0x61b, /* VMMCALL */ 0x61a, /* VMLOAD64 */ 0x626, /* VMSAVE64 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x28a, /* INVLPGA64 */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x5a5, /* SMSW32r */ 0x543, /* SETSSBSY */ 0x0, /* */ 0x4fc, /* SAVEPREVSSP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2603 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x420, /* PTWRITEm */ 0x0, /* */ 0x18a, /* CLRSSBSY */ 0x0, /* */ 0x474, /* RDFSBASE */ 0x476, /* RDGSBASE */ 0x62f, /* WRFSBASE */ 0x631, /* WRGSBASE */ 0x421, /* PTWRITEr */ 0x27c, /* INCSSPD */ 0x60f, /* UMONITOR64 */ 0x0, /* */ /* Table2619 */ 0x0, /* */ 0x21e, /* CMPXCHG8B */ 0x0, /* */ 0x679, /* XRSTORS */ 0x67d, /* XSAVEC */ 0x681, /* XSAVES */ 0x62c, /* VMXON */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47a, /* RDPID64 */ /* Table2635 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x420, /* PTWRITEm */ 0x0, /* */ 0x18a, /* CLRSSBSY */ 0x0, /* */ 0x474, /* RDFSBASE */ 0x476, /* RDGSBASE */ 0x62f, /* WRFSBASE */ 0x631, /* WRGSBASE */ 0x421, /* PTWRITEr */ 0x27c, /* INCSSPD */ 0x60e, /* UMONITOR32 */ 0x0, /* */ /* Table2651 */ 0x548, /* SGDT64m */ 0x59b, /* SIDT64m */ 0x2ea, /* LGDT64m */ 0x2f0, /* LIDT64m */ 0x5a3, /* SMSW16m */ 0x4c5, /* RSTORSSP */ 0x2f5, /* LMSW16m */ 0x288, /* INVLPG */ 0x0, /* */ 0x615, /* VMCALL */ 0x618, /* VMLAUNCH */ 0x622, /* VMRESUME */ 0x62b, /* VMXOFF */ 0x3fb, /* PCONFIG */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x183, /* CLAC */ 0x5a7, /* STAC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x651, /* XGETBV */ 0x683, /* XSETBV */ 0x0, /* */ 0x0, /* */ 0x617, /* VMFUNC */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x624, /* VMRUN64 */ 0x61b, /* VMMCALL */ 0x61a, /* VMLOAD64 */ 0x626, /* VMSAVE64 */ 0x5aa, /* STGI */ 0x188, /* CLGI */ 0x59c, /* SKINIT */ 0x28a, /* INVLPGA64 */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x5a6, /* SMSW64r */ 0x543, /* SETSSBSY */ 0x0, /* */ 0x4fc, /* SAVEPREVSSP */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47b, /* RDPKRUr */ 0x634, /* WRPKRUr */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x2f6, /* LMSW16r */ 0x5d8, /* SWAPGS */ 0x486, /* RDTSCP */ 0x31e, /* MONITORXrrr */ 0x39e, /* MWAITXrrr */ 0x18d, /* CLZEROr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2723 */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x3bc, /* NOOPL_1e */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x484, /* RDSSPQ */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x23b, /* ENDBR64 */ 0x23a, /* ENDBR32 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2795 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x41e, /* PTWRITE64m */ 0x677, /* XRSTOR */ 0x18a, /* CLRSSBSY */ 0x0, /* */ 0x475, /* RDFSBASE64 */ 0x477, /* RDGSBASE64 */ 0x630, /* WRFSBASE64 */ 0x632, /* WRGSBASE64 */ 0x41f, /* PTWRITE64r */ 0x27d, /* INCSSPQ */ 0x60f, /* UMONITOR64 */ 0x0, /* */ /* Table2811 */ 0x604, /* TZCNT64rm */ 0x605, /* TZCNT64rr */ /* Table2813 */ 0x31c, /* LZCNT64rm */ 0x31d, /* LZCNT64rr */ /* Table2815 */ 0x0, /* */ 0x217, /* CMPXCHG16B */ 0x0, /* */ 0x67a, /* XRSTORS64 */ 0x67e, /* XSAVEC64 */ 0x682, /* XSAVES64 */ 0x62c, /* VMXON */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47e, /* RDRAND32r */ 0x47a, /* RDPID64 */ /* Table2831 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x67b, /* XSAVE */ 0x677, /* XRSTOR */ 0x67f, /* XSAVEOPT */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x610, /* UMWAIT */ 0x0, /* */ /* Table2847 */ 0x0, /* */ 0x217, /* CMPXCHG16B */ 0x0, /* */ 0x67a, /* XRSTORS64 */ 0x67e, /* XSAVEC64 */ 0x682, /* XSAVES64 */ 0x61c, /* VMPTRLDm */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47e, /* RDRAND32r */ 0x481, /* RDSEED32r */ /* Table2863 */ 0x0, /* */ 0x217, /* CMPXCHG16B */ 0x0, /* */ 0x67a, /* XRSTORS64 */ 0x67e, /* XSAVEC64 */ 0x682, /* XSAVES64 */ 0x616, /* VMCLEARm */ 0x61d, /* VMPTRSTm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x47d, /* RDRAND16r */ 0x480, /* RDSEED16r */ /* Table2879 */ 0x368, /* MOVBE32rm */ 0x0, /* */ /* Table2881 */ 0x367, /* MOVBE32mr */ 0x0, /* */ /* Table2883 */ 0x635, /* WRSSD */ 0x0, /* */ /* Table2885 */ 0x36e, /* MOVDIRI32 */ 0x0, /* */ /* Table2887 */ 0x286, /* INVEPT32 */ 0x0, /* */ /* Table2889 */ 0x28d, /* INVVPID32 */ 0x0, /* */ /* Table2891 */ 0x28b, /* INVPCID32 */ 0x0, /* */ /* Table2893 */ 0x366, /* MOVBE16rm */ 0x0, /* */ /* Table2895 */ 0x365, /* MOVBE16mr */ 0x0, /* */ /* Table2897 */ 0x637, /* WRUSSD */ 0x0, /* */ /* Table2899 */ 0xa6, /* ADCX32rm */ 0xa7, /* ADCX32rr */ /* Table2901 */ 0x36c, /* MOVDIR64B32 */ 0x0, /* */ /* Table2903 */ 0x36b, /* MOVDIR64B16 */ 0x0, /* */ /* Table2905 */ 0xce, /* ADOX32rm */ 0xcf, /* ADOX32rr */ /* Table2907 */ 0x36a, /* MOVBE64rm */ 0x0, /* */ /* Table2909 */ 0x369, /* MOVBE64mr */ 0x0, /* */ /* Table2911 */ 0x636, /* WRSSQ */ 0x0, /* */ /* Table2913 */ 0x36f, /* MOVDIRI64 */ 0x0, /* */ /* Table2915 */ 0x287, /* INVEPT64 */ 0x0, /* */ /* Table2917 */ 0x28e, /* INVVPID64 */ 0x0, /* */ /* Table2919 */ 0x28c, /* INVPCID64 */ 0x0, /* */ /* Table2921 */ 0x636, /* WRSSQ */ 0xa7, /* ADCX32rr */ /* Table2923 */ 0x36d, /* MOVDIR64B64 */ 0x0, /* */ /* Table2925 */ 0xd0, /* ADOX64rm */ 0xd1, /* ADOX64rr */ /* Table2927 */ 0x638, /* WRUSSQ */ 0x0, /* */ /* Table2929 */ 0xa8, /* ADCX64rm */ 0xa9, /* ADCX64rr */ /* Table2931 */ 0xf6, /* ANDN32rm */ 0xf7, /* ANDN32rr */ /* Table2933 */ 0x0, /* */ 0x128, /* BLSR32rm */ 0x124, /* BLSMSK32rm */ 0x11c, /* BLSI32rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x129, /* BLSR32rr */ 0x125, /* BLSMSK32rr */ 0x11d, /* BLSI32rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2949 */ 0x16d, /* BZHI32rm */ 0x16e, /* BZHI32rr */ /* Table2951 */ 0xfc, /* BEXTR32rm */ 0xfd, /* BEXTR32rr */ /* Table2953 */ 0x400, /* PEXT32rm */ 0x401, /* PEXT32rr */ /* Table2955 */ 0x4f8, /* SARX32rm */ 0x4f9, /* SARX32rr */ /* Table2957 */ 0x3fc, /* PDEP32rm */ 0x3fd, /* PDEP32rr */ /* Table2959 */ 0x39a, /* MULX32rm */ 0x39b, /* MULX32rr */ /* Table2961 */ 0x595, /* SHRX32rm */ 0x596, /* SHRX32rr */ /* Table2963 */ 0x56d, /* SHLX32rm */ 0x56e, /* SHLX32rr */ /* Table2965 */ 0xf8, /* ANDN64rm */ 0xf9, /* ANDN64rr */ /* Table2967 */ 0x0, /* */ 0x12a, /* BLSR64rm */ 0x126, /* BLSMSK64rm */ 0x11e, /* BLSI64rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x12b, /* BLSR64rr */ 0x127, /* BLSMSK64rr */ 0x11f, /* BLSI64rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table2983 */ 0x16f, /* BZHI64rm */ 0x170, /* BZHI64rr */ /* Table2985 */ 0xfe, /* BEXTR64rm */ 0xff, /* BEXTR64rr */ /* Table2987 */ 0x402, /* PEXT64rm */ 0x403, /* PEXT64rr */ /* Table2989 */ 0x4fa, /* SARX64rm */ 0x4fb, /* SARX64rr */ /* Table2991 */ 0x3fe, /* PDEP64rm */ 0x3ff, /* PDEP64rr */ /* Table2993 */ 0x39c, /* MULX64rm */ 0x39d, /* MULX64rr */ /* Table2995 */ 0x597, /* SHRX64rm */ 0x598, /* SHRX64rr */ /* Table2997 */ 0x56f, /* SHLX64rm */ 0x570, /* SHLX64rr */ /* Table2999 */ 0x4c0, /* RORX32mi */ 0x4c1, /* RORX32ri */ /* Table3001 */ 0x4c2, /* RORX64mi */ 0x4c3, /* RORX64ri */ /* Table3003 */ 0x0, /* */ 0x104, /* BLCFILL32rm */ 0x118, /* BLSFILL32rm */ 0x114, /* BLCS32rm */ 0x606, /* TZMSK32rm */ 0x10c, /* BLCIC32rm */ 0x120, /* BLSIC32rm */ 0x5df, /* T1MSKC32rm */ 0x0, /* */ 0x105, /* BLCFILL32rr */ 0x119, /* BLSFILL32rr */ 0x115, /* BLCS32rr */ 0x607, /* TZMSK32rr */ 0x10d, /* BLCIC32rr */ 0x121, /* BLSIC32rr */ 0x5e0, /* T1MSKC32rr */ /* Table3019 */ 0x0, /* */ 0x110, /* BLCMSK32rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x108, /* BLCI32rm */ 0x0, /* */ 0x0, /* */ 0x111, /* BLCMSK32rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x109, /* BLCI32rr */ 0x0, /* */ /* Table3035 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f3, /* LLWPCB */ 0x5a1, /* SLWPCB */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3051 */ 0x0, /* */ 0x106, /* BLCFILL64rm */ 0x11a, /* BLSFILL64rm */ 0x116, /* BLCS64rm */ 0x608, /* TZMSK64rm */ 0x10e, /* BLCIC64rm */ 0x122, /* BLSIC64rm */ 0x5e1, /* T1MSKC64rm */ 0x0, /* */ 0x107, /* BLCFILL64rr */ 0x11b, /* BLSFILL64rr */ 0x117, /* BLCS64rr */ 0x609, /* TZMSK64rr */ 0x10f, /* BLCIC64rr */ 0x123, /* BLSIC64rr */ 0x5e2, /* T1MSKC64rr */ /* Table3067 */ 0x0, /* */ 0x112, /* BLCMSK64rm */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x10a, /* BLCI64rm */ 0x0, /* */ 0x0, /* */ 0x113, /* BLCMSK64rr */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x10b, /* BLCI64rr */ 0x0, /* */ /* Table3083 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x2f4, /* LLWPCB64 */ 0x5a2, /* SLWPCB64 */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3099 */ 0x100, /* BEXTRI32mi */ 0x101, /* BEXTRI32ri */ /* Table3101 */ 0x310, /* LWPINS32rmi */ 0x314, /* LWPVAL32rmi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x311, /* LWPINS32rri */ 0x315, /* LWPVAL32rri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ /* Table3117 */ 0x102, /* BEXTRI64mi */ 0x103, /* BEXTRI64ri */ /* Table3119 */ 0x312, /* LWPINS64rmi */ 0x316, /* LWPVAL64rmi */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x313, /* LWPINS64rri */ 0x317, /* LWPVAL64rri */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0, /* */ 0x0 }; capstone-sys-0.15.0/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc000064400000000000000000017232150072674642500243340ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ static const unsigned char index_x86DisassemblerOneByteOpcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 16, 17, 18, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86DisassemblerOneByteOpcodes[] = { { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 3 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 7 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 10 }, { MODRM_ONEENTRY, 11 }, { MODRM_ONEENTRY, 12 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 15 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 19 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 22 }, { MODRM_ONEENTRY, 23 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 26 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 30 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 33 }, { MODRM_ONEENTRY, 34 }, { MODRM_ONEENTRY, 35 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 38 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 42 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 45 }, { MODRM_ONEENTRY, 46 }, { MODRM_ONEENTRY, 47 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 50 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 54 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 57 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 58 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 61 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 65 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 68 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 69 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 72 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 76 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 79 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 80 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 83 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 87 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 90 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 91 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 92 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 93 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 94 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 95 }, { MODRM_ONEENTRY, 96 }, { MODRM_ONEENTRY, 97 }, { MODRM_SPLITRM, 98 }, { MODRM_SPLITRM, 100 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 103 }, { MODRM_SPLITRM, 104 }, { MODRM_ONEENTRY, 106 }, { MODRM_SPLITRM, 107 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 110 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 112 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 145 }, { MODRM_SPLITREG, 161 }, { MODRM_SPLITREG, 177 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 195 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 199 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 203 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 207 }, { MODRM_SPLITRM, 209 }, { MODRM_SPLITRM, 211 }, { MODRM_SPLITRM, 213 }, { MODRM_SPLITREG, 215 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 233 }, { MODRM_ONEENTRY, 234 }, { MODRM_ONEENTRY, 235 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 236 }, { MODRM_ONEENTRY, 237 }, { MODRM_ONEENTRY, 238 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 241 }, { MODRM_ONEENTRY, 242 }, { MODRM_ONEENTRY, 243 }, { MODRM_ONEENTRY, 244 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_SPLITREG, 258 }, { MODRM_SPLITREG, 274 }, { MODRM_ONEENTRY, 290 }, { MODRM_ONEENTRY, 291 }, { MODRM_SPLITRM, 292 }, { MODRM_SPLITRM, 294 }, { MODRM_SPLITREG, 296 }, { MODRM_SPLITREG, 312 }, { MODRM_ONEENTRY, 328 }, { MODRM_ONEENTRY, 329 }, { MODRM_ONEENTRY, 330 }, { MODRM_ONEENTRY, 331 }, { MODRM_ONEENTRY, 332 }, { MODRM_ONEENTRY, 333 }, { MODRM_ONEENTRY, 334 }, { MODRM_ONEENTRY, 335 }, { MODRM_SPLITREG, 336 }, { MODRM_SPLITREG, 352 }, { MODRM_SPLITREG, 368 }, { MODRM_SPLITREG, 384 }, { MODRM_ONEENTRY, 400 }, { MODRM_ONEENTRY, 401 }, { MODRM_ONEENTRY, 402 }, { MODRM_ONEENTRY, 403 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 404 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 476 }, { MODRM_ONEENTRY, 477 }, { MODRM_ONEENTRY, 478 }, { MODRM_ONEENTRY, 479 }, { MODRM_ONEENTRY, 480 }, { MODRM_ONEENTRY, 481 }, { MODRM_ONEENTRY, 482 }, { MODRM_ONEENTRY, 483 }, { MODRM_ONEENTRY, 484 }, { MODRM_ONEENTRY, 485 }, { MODRM_ONEENTRY, 486 }, { MODRM_ONEENTRY, 487 }, { MODRM_ONEENTRY, 488 }, { MODRM_ONEENTRY, 489 }, { MODRM_ONEENTRY, 490 }, { MODRM_ONEENTRY, 491 }, { MODRM_ONEENTRY, 492 }, { MODRM_ONEENTRY, 493 }, { MODRM_ONEENTRY, 494 }, { MODRM_ONEENTRY, 495 }, { MODRM_ONEENTRY, 496 }, { MODRM_ONEENTRY, 497 }, { MODRM_SPLITREG, 498 }, { MODRM_SPLITREG, 514 }, { MODRM_ONEENTRY, 530 }, { MODRM_ONEENTRY, 531 }, { MODRM_ONEENTRY, 532 }, { MODRM_ONEENTRY, 533 }, { MODRM_ONEENTRY, 534 }, { MODRM_ONEENTRY, 535 }, { MODRM_SPLITREG, 536 }, { MODRM_SPLITREG, 552 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 3 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 7 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 10 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 15 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 19 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 22 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 26 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 30 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 33 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 38 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 42 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 45 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 50 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 54 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 57 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 61 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 65 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 68 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 72 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 76 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 79 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 83 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 87 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 90 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 568 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 571 }, { MODRM_SPLITRM, 104 }, { MODRM_ONEENTRY, 572 }, { MODRM_SPLITRM, 107 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 110 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 112 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 145 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 177 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 195 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 199 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 203 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 207 }, { MODRM_SPLITRM, 209 }, { MODRM_SPLITRM, 573 }, { MODRM_SPLITRM, 213 }, { MODRM_SPLITREG, 575 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 232 }, { MODRM_ONEENTRY, 233 }, { MODRM_ONEENTRY, 234 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 591 }, { MODRM_ONEENTRY, 592 }, { MODRM_ONEENTRY, 238 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 593 }, { MODRM_ONEENTRY, 594 }, { MODRM_ONEENTRY, 595 }, { MODRM_ONEENTRY, 596 }, { MODRM_ONEENTRY, 244 }, { MODRM_ONEENTRY, 245 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 247 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 249 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 251 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 253 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 255 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_ONEENTRY, 257 }, { MODRM_SPLITREG, 258 }, { MODRM_SPLITREG, 274 }, { MODRM_ONEENTRY, 597 }, { MODRM_ONEENTRY, 598 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 296 }, { MODRM_SPLITREG, 312 }, { MODRM_ONEENTRY, 328 }, { MODRM_ONEENTRY, 599 }, { MODRM_ONEENTRY, 330 }, { MODRM_ONEENTRY, 331 }, { MODRM_ONEENTRY, 332 }, { MODRM_ONEENTRY, 333 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 335 }, { MODRM_SPLITREG, 336 }, { MODRM_SPLITREG, 352 }, { MODRM_SPLITREG, 368 }, { MODRM_SPLITREG, 384 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 403 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 404 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 476 }, { MODRM_ONEENTRY, 477 }, { MODRM_ONEENTRY, 478 }, { MODRM_ONEENTRY, 600 }, { MODRM_ONEENTRY, 480 }, { MODRM_ONEENTRY, 481 }, { MODRM_ONEENTRY, 482 }, { MODRM_ONEENTRY, 483 }, { MODRM_ONEENTRY, 601 }, { MODRM_ONEENTRY, 485 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 487 }, { MODRM_ONEENTRY, 488 }, { MODRM_ONEENTRY, 489 }, { MODRM_ONEENTRY, 490 }, { MODRM_ONEENTRY, 491 }, { MODRM_ONEENTRY, 492 }, { MODRM_ONEENTRY, 493 }, { MODRM_ONEENTRY, 494 }, { MODRM_ONEENTRY, 495 }, { MODRM_ONEENTRY, 496 }, { MODRM_ONEENTRY, 497 }, { MODRM_SPLITREG, 498 }, { MODRM_SPLITREG, 514 }, { MODRM_ONEENTRY, 530 }, { MODRM_ONEENTRY, 531 }, { MODRM_ONEENTRY, 532 }, { MODRM_ONEENTRY, 533 }, { MODRM_ONEENTRY, 534 }, { MODRM_ONEENTRY, 535 }, { MODRM_SPLITREG, 536 }, { MODRM_SPLITREG, 602 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 618 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 620 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 622 }, { MODRM_ONEENTRY, 623 }, { MODRM_ONEENTRY, 624 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 625 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 627 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 629 }, { MODRM_ONEENTRY, 630 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 631 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 633 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 635 }, { MODRM_ONEENTRY, 636 }, { MODRM_ONEENTRY, 637 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 638 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 640 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 642 }, { MODRM_ONEENTRY, 643 }, { MODRM_ONEENTRY, 644 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 645 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 647 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 649 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 58 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 650 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 652 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 654 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 69 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 655 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 657 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 659 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 80 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 660 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 662 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 664 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 91 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 665 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 666 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 669 }, { MODRM_ONEENTRY, 670 }, { MODRM_SPLITRM, 671 }, { MODRM_SPLITRM, 100 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 673 }, { MODRM_SPLITRM, 674 }, { MODRM_ONEENTRY, 676 }, { MODRM_SPLITRM, 677 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 679 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 680 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 681 }, { MODRM_SPLITREG, 161 }, { MODRM_SPLITREG, 697 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 713 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 715 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 717 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 719 }, { MODRM_SPLITRM, 721 }, { MODRM_SPLITRM, 723 }, { MODRM_SPLITRM, 725 }, { MODRM_SPLITREG, 727 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 743 }, { MODRM_ONEENTRY, 744 }, { MODRM_ONEENTRY, 745 }, { MODRM_ONEENTRY, 746 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 747 }, { MODRM_ONEENTRY, 748 }, { MODRM_ONEENTRY, 238 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 240 }, { MODRM_ONEENTRY, 749 }, { MODRM_ONEENTRY, 242 }, { MODRM_ONEENTRY, 750 }, { MODRM_ONEENTRY, 244 }, { MODRM_ONEENTRY, 751 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 752 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 753 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 754 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 755 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 756 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_ONEENTRY, 757 }, { MODRM_SPLITREG, 258 }, { MODRM_SPLITREG, 758 }, { MODRM_ONEENTRY, 774 }, { MODRM_ONEENTRY, 775 }, { MODRM_SPLITRM, 776 }, { MODRM_SPLITRM, 778 }, { MODRM_SPLITREG, 296 }, { MODRM_SPLITREG, 780 }, { MODRM_ONEENTRY, 328 }, { MODRM_ONEENTRY, 329 }, { MODRM_ONEENTRY, 796 }, { MODRM_ONEENTRY, 797 }, { MODRM_ONEENTRY, 332 }, { MODRM_ONEENTRY, 333 }, { MODRM_ONEENTRY, 334 }, { MODRM_ONEENTRY, 798 }, { MODRM_SPLITREG, 336 }, { MODRM_SPLITREG, 799 }, { MODRM_SPLITREG, 368 }, { MODRM_SPLITREG, 815 }, { MODRM_ONEENTRY, 400 }, { MODRM_ONEENTRY, 401 }, { MODRM_ONEENTRY, 402 }, { MODRM_ONEENTRY, 403 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 404 }, { 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493 }, { MODRM_ONEENTRY, 494 }, { MODRM_ONEENTRY, 495 }, { MODRM_ONEENTRY, 496 }, { MODRM_ONEENTRY, 497 }, { MODRM_SPLITREG, 498 }, { MODRM_SPLITREG, 1048 }, { MODRM_ONEENTRY, 530 }, { MODRM_ONEENTRY, 531 }, { MODRM_ONEENTRY, 532 }, { MODRM_ONEENTRY, 533 }, { MODRM_ONEENTRY, 534 }, { MODRM_ONEENTRY, 535 }, { MODRM_SPLITREG, 536 }, { MODRM_SPLITREG, 1064 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 877 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 879 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 881 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 882 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 884 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 886 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 887 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 889 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 891 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 892 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 894 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 896 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 897 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 899 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 901 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 902 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 904 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 906 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 907 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 909 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 911 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 912 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 914 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 916 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 568 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 569 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 570 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 917 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 571 }, { MODRM_SPLITRM, 919 }, { MODRM_ONEENTRY, 572 }, { MODRM_SPLITRM, 921 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 110 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 112 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 923 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 939 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 955 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 957 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 959 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 961 }, { MODRM_SPLITRM, 963 }, { MODRM_SPLITRM, 965 }, { MODRM_SPLITRM, 967 }, { MODRM_SPLITREG, 575 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 970 }, { MODRM_ONEENTRY, 971 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 591 }, { MODRM_ONEENTRY, 592 }, { MODRM_ONEENTRY, 238 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 593 }, { MODRM_ONEENTRY, 972 }, { MODRM_ONEENTRY, 595 }, { MODRM_ONEENTRY, 973 }, { MODRM_ONEENTRY, 244 }, { MODRM_ONEENTRY, 974 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 975 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 976 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 977 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 978 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_SPLITREG, 258 }, { MODRM_SPLITREG, 981 }, { MODRM_ONEENTRY, 597 }, { MODRM_ONEENTRY, 598 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 296 }, { MODRM_SPLITREG, 997 }, { MODRM_ONEENTRY, 328 }, { MODRM_ONEENTRY, 599 }, { MODRM_ONEENTRY, 1013 }, { MODRM_ONEENTRY, 1014 }, { MODRM_ONEENTRY, 332 }, { MODRM_ONEENTRY, 333 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1015 }, { MODRM_SPLITREG, 336 }, { MODRM_SPLITREG, 1016 }, { MODRM_SPLITREG, 368 }, { MODRM_SPLITREG, 1032 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 403 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 404 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 476 }, { MODRM_ONEENTRY, 477 }, { MODRM_ONEENTRY, 478 }, { MODRM_ONEENTRY, 600 }, { MODRM_ONEENTRY, 480 }, { MODRM_ONEENTRY, 481 }, { MODRM_ONEENTRY, 482 }, { MODRM_ONEENTRY, 483 }, { MODRM_ONEENTRY, 601 }, { MODRM_ONEENTRY, 485 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 487 }, { MODRM_ONEENTRY, 488 }, { MODRM_ONEENTRY, 489 }, { MODRM_ONEENTRY, 490 }, { MODRM_ONEENTRY, 491 }, { MODRM_ONEENTRY, 492 }, { MODRM_ONEENTRY, 493 }, { MODRM_ONEENTRY, 494 }, { MODRM_ONEENTRY, 495 }, { MODRM_ONEENTRY, 496 }, { MODRM_ONEENTRY, 497 }, { MODRM_SPLITREG, 498 }, { MODRM_SPLITREG, 1048 }, { MODRM_ONEENTRY, 530 }, { MODRM_ONEENTRY, 531 }, { MODRM_ONEENTRY, 532 }, { MODRM_ONEENTRY, 533 }, { MODRM_ONEENTRY, 534 }, { MODRM_ONEENTRY, 535 }, { MODRM_SPLITREG, 536 }, { MODRM_SPLITREG, 1064 }, } }, { { { MODRM_SPLITRM, 1 }, { MODRM_SPLITRM, 877 }, { MODRM_SPLITRM, 5 }, { MODRM_SPLITRM, 879 }, { MODRM_ONEENTRY, 9 }, { MODRM_ONEENTRY, 881 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 13 }, { MODRM_SPLITRM, 882 }, { MODRM_SPLITRM, 17 }, { MODRM_SPLITRM, 884 }, { MODRM_ONEENTRY, 21 }, { MODRM_ONEENTRY, 886 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 24 }, { MODRM_SPLITRM, 887 }, { MODRM_SPLITRM, 28 }, { MODRM_SPLITRM, 889 }, { MODRM_ONEENTRY, 32 }, { MODRM_ONEENTRY, 891 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 36 }, { MODRM_SPLITRM, 892 }, { MODRM_SPLITRM, 40 }, { MODRM_SPLITRM, 894 }, { MODRM_ONEENTRY, 44 }, { MODRM_ONEENTRY, 896 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 48 }, { MODRM_SPLITRM, 897 }, { MODRM_SPLITRM, 52 }, { MODRM_SPLITRM, 899 }, { MODRM_ONEENTRY, 56 }, { MODRM_ONEENTRY, 901 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 59 }, { MODRM_SPLITRM, 902 }, { MODRM_SPLITRM, 63 }, { MODRM_SPLITRM, 904 }, { MODRM_ONEENTRY, 67 }, { MODRM_ONEENTRY, 906 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 70 }, { MODRM_SPLITRM, 907 }, { MODRM_SPLITRM, 74 }, { MODRM_SPLITRM, 909 }, { MODRM_ONEENTRY, 78 }, { MODRM_ONEENTRY, 911 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 81 }, { MODRM_SPLITRM, 912 }, { MODRM_SPLITRM, 85 }, { MODRM_SPLITRM, 914 }, { MODRM_ONEENTRY, 89 }, { MODRM_ONEENTRY, 916 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 568 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 667 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 668 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 917 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 102 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 673 }, { MODRM_SPLITRM, 919 }, { MODRM_ONEENTRY, 676 }, { MODRM_SPLITRM, 921 }, { MODRM_ONEENTRY, 109 }, { MODRM_ONEENTRY, 679 }, { MODRM_ONEENTRY, 111 }, { MODRM_ONEENTRY, 680 }, { MODRM_ONEENTRY, 113 }, { MODRM_ONEENTRY, 114 }, { MODRM_ONEENTRY, 115 }, { MODRM_ONEENTRY, 116 }, { MODRM_ONEENTRY, 117 }, { MODRM_ONEENTRY, 118 }, { MODRM_ONEENTRY, 119 }, { MODRM_ONEENTRY, 120 }, { MODRM_ONEENTRY, 121 }, { MODRM_ONEENTRY, 122 }, { MODRM_ONEENTRY, 123 }, { MODRM_ONEENTRY, 124 }, { MODRM_ONEENTRY, 125 }, { MODRM_ONEENTRY, 126 }, { MODRM_ONEENTRY, 127 }, { MODRM_ONEENTRY, 128 }, { MODRM_SPLITREG, 129 }, { MODRM_SPLITREG, 923 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 939 }, { MODRM_SPLITRM, 193 }, { MODRM_SPLITRM, 955 }, { MODRM_SPLITRM, 197 }, { MODRM_SPLITRM, 957 }, { MODRM_SPLITRM, 201 }, { MODRM_SPLITRM, 959 }, { MODRM_SPLITRM, 205 }, { MODRM_SPLITRM, 961 }, { MODRM_SPLITRM, 963 }, { MODRM_SPLITRM, 965 }, { MODRM_SPLITRM, 967 }, { MODRM_SPLITREG, 727 }, { MODRM_ONEENTRY, 231 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 969 }, { MODRM_ONEENTRY, 970 }, { MODRM_ONEENTRY, 971 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 747 }, { MODRM_ONEENTRY, 748 }, { MODRM_ONEENTRY, 238 }, { MODRM_ONEENTRY, 239 }, { MODRM_ONEENTRY, 593 }, { MODRM_ONEENTRY, 972 }, { MODRM_ONEENTRY, 595 }, { MODRM_ONEENTRY, 973 }, { MODRM_ONEENTRY, 244 }, { MODRM_ONEENTRY, 974 }, { MODRM_ONEENTRY, 246 }, { MODRM_ONEENTRY, 975 }, { MODRM_ONEENTRY, 248 }, { MODRM_ONEENTRY, 976 }, { MODRM_ONEENTRY, 250 }, { MODRM_ONEENTRY, 977 }, { MODRM_ONEENTRY, 252 }, { MODRM_ONEENTRY, 978 }, { MODRM_ONEENTRY, 254 }, { MODRM_ONEENTRY, 979 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 256 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_ONEENTRY, 980 }, { MODRM_SPLITREG, 258 }, { MODRM_SPLITREG, 981 }, { MODRM_ONEENTRY, 774 }, { MODRM_ONEENTRY, 775 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 296 }, { MODRM_SPLITREG, 997 }, { MODRM_ONEENTRY, 328 }, { MODRM_ONEENTRY, 599 }, { MODRM_ONEENTRY, 1013 }, { MODRM_ONEENTRY, 1014 }, { MODRM_ONEENTRY, 332 }, { MODRM_ONEENTRY, 333 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1015 }, { MODRM_SPLITREG, 336 }, { MODRM_SPLITREG, 1016 }, { MODRM_SPLITREG, 368 }, { MODRM_SPLITREG, 1032 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 403 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITMISC, 404 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 476 }, { MODRM_ONEENTRY, 477 }, { MODRM_ONEENTRY, 478 }, { MODRM_ONEENTRY, 600 }, { MODRM_ONEENTRY, 480 }, { MODRM_ONEENTRY, 831 }, { MODRM_ONEENTRY, 482 }, { MODRM_ONEENTRY, 832 }, { MODRM_ONEENTRY, 833 }, { MODRM_ONEENTRY, 834 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 487 }, { MODRM_ONEENTRY, 488 }, { MODRM_ONEENTRY, 836 }, { MODRM_ONEENTRY, 490 }, { MODRM_ONEENTRY, 837 }, { MODRM_ONEENTRY, 492 }, { MODRM_ONEENTRY, 493 }, { MODRM_ONEENTRY, 494 }, { MODRM_ONEENTRY, 495 }, { MODRM_ONEENTRY, 496 }, { MODRM_ONEENTRY, 497 }, { MODRM_SPLITREG, 498 }, { MODRM_SPLITREG, 1048 }, { MODRM_ONEENTRY, 530 }, { MODRM_ONEENTRY, 531 }, { MODRM_ONEENTRY, 532 }, { MODRM_ONEENTRY, 533 }, { MODRM_ONEENTRY, 534 }, { MODRM_ONEENTRY, 535 }, { MODRM_SPLITREG, 536 }, { MODRM_SPLITREG, 1082 }, } }, }; static const unsigned char index_x86DisassemblerTwoByteOpcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 8, 0, 9, 10, 11, 12, 13, 14, 15, 16, 0, 17, 18, 19, 20, 21, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86DisassemblerTwoByteOpcodes[] = { { { { MODRM_SPLITREG, 1116 }, { MODRM_SPLITMISC, 1132 }, { MODRM_SPLITRM, 1204 }, { MODRM_SPLITRM, 1206 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1208 }, { MODRM_ONEENTRY, 1209 }, { MODRM_ONEENTRY, 1210 }, { MODRM_ONEENTRY, 1211 }, { MODRM_ONEENTRY, 1212 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1213 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1214 }, { MODRM_SPLITRM, 1230 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1232 }, { MODRM_SPLITRM, 1248 }, { MODRM_SPLITRM, 1250 }, { MODRM_SPLITRM, 1252 }, { MODRM_SPLITRM, 1254 }, { MODRM_SPLITRM, 1256 }, { MODRM_SPLITRM, 1258 }, { MODRM_SPLITRM, 1260 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1262 }, { MODRM_ONEENTRY, 1263 }, { MODRM_ONEENTRY, 1264 }, { MODRM_ONEENTRY, 1265 }, { MODRM_ONEENTRY, 1266 }, { MODRM_ONEENTRY, 1267 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1268 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1269 }, { MODRM_SPLITRM, 1271 }, { MODRM_SPLITRM, 1273 }, { MODRM_SPLITRM, 1275 }, { MODRM_SPLITRM, 1277 }, { MODRM_SPLITRM, 1279 }, { MODRM_SPLITRM, 1281 }, { MODRM_SPLITRM, 1283 }, { MODRM_SPLITRM, 1285 }, { MODRM_SPLITRM, 1287 }, { MODRM_SPLITRM, 1289 }, { MODRM_SPLITRM, 1291 }, { MODRM_SPLITRM, 1293 }, { MODRM_SPLITRM, 1295 }, { MODRM_SPLITRM, 1297 }, { MODRM_SPLITRM, 1299 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1301 }, { MODRM_SPLITRM, 1303 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1305 }, { MODRM_ONEENTRY, 1306 }, { MODRM_ONEENTRY, 1307 }, { MODRM_ONEENTRY, 1308 }, { MODRM_ONEENTRY, 1309 }, { MODRM_ONEENTRY, 1310 }, { MODRM_ONEENTRY, 1311 }, { MODRM_ONEENTRY, 1312 }, { MODRM_ONEENTRY, 1313 }, { MODRM_ONEENTRY, 1314 }, { MODRM_ONEENTRY, 1315 }, { MODRM_ONEENTRY, 1316 }, { MODRM_ONEENTRY, 1317 }, { MODRM_ONEENTRY, 1318 }, { MODRM_ONEENTRY, 1319 }, { MODRM_ONEENTRY, 1320 }, { MODRM_SPLITRM, 1321 }, { MODRM_SPLITRM, 1323 }, { MODRM_SPLITRM, 1325 }, { MODRM_SPLITRM, 1327 }, { MODRM_SPLITRM, 1329 }, { MODRM_SPLITRM, 1331 }, { MODRM_SPLITRM, 1333 }, { MODRM_SPLITRM, 1335 }, { MODRM_SPLITRM, 1337 }, { MODRM_SPLITRM, 1339 }, { MODRM_SPLITRM, 1341 }, { MODRM_SPLITRM, 1343 }, { MODRM_SPLITRM, 1345 }, { MODRM_SPLITRM, 1347 }, { MODRM_SPLITRM, 1349 }, { MODRM_SPLITRM, 1351 }, { MODRM_ONEENTRY, 1353 }, { MODRM_ONEENTRY, 1354 }, { MODRM_ONEENTRY, 1355 }, { MODRM_SPLITRM, 1356 }, { MODRM_SPLITRM, 1358 }, { MODRM_SPLITRM, 1360 }, { MODRM_SPLITMISC, 1362 }, { MODRM_SPLITMISC, 1434 }, { MODRM_ONEENTRY, 1506 }, { MODRM_ONEENTRY, 1507 }, { MODRM_ONEENTRY, 1508 }, { MODRM_SPLITRM, 1509 }, { MODRM_SPLITRM, 1511 }, { MODRM_SPLITRM, 1513 }, { MODRM_SPLITREG, 1515 }, { MODRM_SPLITRM, 1531 }, { MODRM_SPLITRM, 1533 }, { MODRM_SPLITRM, 1535 }, { MODRM_SPLITRM, 1537 }, { MODRM_SPLITRM, 1539 }, { MODRM_SPLITRM, 1541 }, { MODRM_SPLITRM, 1543 }, { MODRM_SPLITRM, 1545 }, { MODRM_SPLITRM, 1547 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1549 }, { MODRM_SPLITREG, 1550 }, { MODRM_SPLITRM, 1566 }, { MODRM_SPLITRM, 1568 }, { MODRM_SPLITRM, 1570 }, { MODRM_SPLITRM, 1572 }, { MODRM_SPLITRM, 1574 }, { MODRM_SPLITRM, 1576 }, { MODRM_SPLITRM, 1578 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1580 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 1596 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, 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MODRM_SPLITRM, 2326 }, { MODRM_SPLITRM, 2328 }, { MODRM_SPLITRM, 2330 }, { MODRM_SPLITRM, 2332 }, { MODRM_SPLITRM, 2334 }, { MODRM_SPLITRM, 2336 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1678 }, { MODRM_SPLITRM, 1680 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1305 }, { MODRM_ONEENTRY, 1306 }, { MODRM_ONEENTRY, 1307 }, { MODRM_ONEENTRY, 1308 }, { MODRM_ONEENTRY, 1309 }, { MODRM_ONEENTRY, 1310 }, { MODRM_ONEENTRY, 1311 }, { MODRM_ONEENTRY, 1312 }, { MODRM_ONEENTRY, 1313 }, { MODRM_ONEENTRY, 1314 }, { MODRM_ONEENTRY, 1315 }, { MODRM_ONEENTRY, 1316 }, { MODRM_ONEENTRY, 1317 }, { MODRM_ONEENTRY, 1318 }, { MODRM_ONEENTRY, 1319 }, { MODRM_ONEENTRY, 1320 }, { MODRM_SPLITRM, 1321 }, { MODRM_SPLITRM, 1323 }, { MODRM_SPLITRM, 1325 }, { MODRM_SPLITRM, 1327 }, { MODRM_SPLITRM, 1329 }, { MODRM_SPLITRM, 1331 }, { MODRM_SPLITRM, 1333 }, { MODRM_SPLITRM, 1335 }, { MODRM_SPLITRM, 1337 }, { MODRM_SPLITRM, 1339 }, { MODRM_SPLITRM, 1341 }, { MODRM_SPLITRM, 1343 }, { MODRM_SPLITRM, 1345 }, { MODRM_SPLITRM, 1347 }, { MODRM_SPLITRM, 1349 }, { MODRM_SPLITRM, 1351 }, { MODRM_ONEENTRY, 1682 }, { MODRM_ONEENTRY, 1683 }, { MODRM_ONEENTRY, 1355 }, { MODRM_SPLITRM, 2338 }, { MODRM_SPLITRM, 2340 }, { MODRM_SPLITRM, 2342 }, { MODRM_SPLITMISC, 1362 }, { MODRM_SPLITMISC, 1434 }, { MODRM_ONEENTRY, 1684 }, { MODRM_ONEENTRY, 1685 }, { MODRM_ONEENTRY, 1508 }, { MODRM_SPLITRM, 2344 }, { MODRM_SPLITRM, 2346 }, { MODRM_SPLITRM, 2348 }, { MODRM_SPLITREG, 2831 }, { MODRM_SPLITRM, 2366 }, { MODRM_SPLITRM, 1533 }, { MODRM_SPLITRM, 2368 }, { MODRM_SPLITRM, 2370 }, { MODRM_SPLITRM, 2372 }, { MODRM_SPLITRM, 2374 }, { MODRM_SPLITRM, 2376 }, { MODRM_SPLITRM, 2378 }, { MODRM_SPLITRM, 2380 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1549 }, { MODRM_SPLITREG, 2382 }, { MODRM_SPLITRM, 2398 }, { MODRM_SPLITRM, 1568 }, { MODRM_SPLITRM, 1570 }, { MODRM_SPLITRM, 2404 }, { MODRM_SPLITRM, 2406 }, { MODRM_SPLITRM, 1576 }, { MODRM_SPLITRM, 2408 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 2847 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1597 }, } }, { { { MODRM_SPLITREG, 2210 }, { MODRM_SPLITMISC, 2226 }, { MODRM_SPLITRM, 2298 }, { MODRM_SPLITRM, 2300 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1208 }, { MODRM_ONEENTRY, 1209 }, { MODRM_ONEENTRY, 2302 }, { MODRM_ONEENTRY, 1211 }, { MODRM_ONEENTRY, 1212 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1213 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 1778 }, { MODRM_SPLITRM, 1794 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1796 }, { MODRM_SPLITRM, 1798 }, { MODRM_SPLITRM, 1800 }, { MODRM_SPLITRM, 2303 }, { MODRM_SPLITRM, 1670 }, { MODRM_SPLITRM, 1672 }, { MODRM_SPLITRM, 1674 }, { MODRM_SPLITRM, 1676 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1262 }, { MODRM_ONEENTRY, 1263 }, { MODRM_ONEENTRY, 1264 }, { MODRM_ONEENTRY, 1265 }, { MODRM_ONEENTRY, 1266 }, { MODRM_ONEENTRY, 2305 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1268 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2306 }, { MODRM_SPLITRM, 2308 }, { MODRM_SPLITRM, 2310 }, { MODRM_SPLITRM, 2312 }, { MODRM_SPLITRM, 2314 }, { MODRM_SPLITRM, 2316 }, { MODRM_SPLITRM, 2318 }, { MODRM_SPLITRM, 2320 }, { MODRM_SPLITRM, 2322 }, { MODRM_SPLITRM, 2324 }, { MODRM_SPLITRM, 2326 }, { MODRM_SPLITRM, 2328 }, { MODRM_SPLITRM, 2330 }, { MODRM_SPLITRM, 2332 }, { MODRM_SPLITRM, 2334 }, { MODRM_SPLITRM, 2336 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 1678 }, { MODRM_SPLITRM, 1680 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1836 }, { MODRM_ONEENTRY, 1837 }, { MODRM_ONEENTRY, 1838 }, { MODRM_ONEENTRY, 1839 }, { MODRM_ONEENTRY, 1840 }, { MODRM_ONEENTRY, 1841 }, { MODRM_ONEENTRY, 1842 }, { MODRM_ONEENTRY, 1843 }, { MODRM_ONEENTRY, 1844 }, { MODRM_ONEENTRY, 1845 }, { MODRM_ONEENTRY, 1846 }, { MODRM_ONEENTRY, 1847 }, { MODRM_ONEENTRY, 1848 }, { MODRM_ONEENTRY, 1849 }, { MODRM_ONEENTRY, 1850 }, { MODRM_ONEENTRY, 1851 }, { MODRM_SPLITRM, 1321 }, { MODRM_SPLITRM, 1323 }, { MODRM_SPLITRM, 1325 }, { MODRM_SPLITRM, 1327 }, { MODRM_SPLITRM, 1329 }, { MODRM_SPLITRM, 1331 }, { MODRM_SPLITRM, 1333 }, { MODRM_SPLITRM, 1335 }, { MODRM_SPLITRM, 1337 }, { MODRM_SPLITRM, 1339 }, { MODRM_SPLITRM, 1341 }, { MODRM_SPLITRM, 1343 }, { MODRM_SPLITRM, 1345 }, { MODRM_SPLITRM, 1347 }, { MODRM_SPLITRM, 1349 }, { MODRM_SPLITRM, 1351 }, { MODRM_ONEENTRY, 1852 }, { MODRM_ONEENTRY, 1853 }, { MODRM_ONEENTRY, 1355 }, { MODRM_SPLITRM, 2338 }, { MODRM_SPLITRM, 2340 }, { MODRM_SPLITRM, 2342 }, { MODRM_SPLITMISC, 1362 }, { MODRM_SPLITMISC, 1434 }, { MODRM_ONEENTRY, 1860 }, { MODRM_ONEENTRY, 1861 }, { MODRM_ONEENTRY, 1508 }, { MODRM_SPLITRM, 2344 }, { MODRM_SPLITRM, 2346 }, { MODRM_SPLITRM, 2348 }, { MODRM_SPLITREG, 1945 }, { MODRM_SPLITRM, 2366 }, { MODRM_SPLITRM, 1533 }, { MODRM_SPLITRM, 2368 }, { MODRM_SPLITRM, 2370 }, { MODRM_SPLITRM, 2372 }, { MODRM_SPLITRM, 2374 }, { MODRM_SPLITRM, 2376 }, { MODRM_SPLITRM, 2378 }, { MODRM_SPLITRM, 2380 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1549 }, { MODRM_SPLITREG, 2382 }, { MODRM_SPLITRM, 2398 }, { MODRM_SPLITRM, 1918 }, { MODRM_SPLITRM, 1920 }, { MODRM_SPLITRM, 2404 }, { MODRM_SPLITRM, 2406 }, { MODRM_SPLITRM, 1576 }, { MODRM_SPLITRM, 2408 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITREG, 2863 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 2426 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 1597 }, } }, }; static const unsigned char index_x86DisassemblerThreeByte38Opcodes[] = { 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 0, 0, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; static const struct OpcodeDecision x86DisassemblerThreeByte38Opcodes[] = { { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { 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MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 2999 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, { { { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_SPLITRM, 3001 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, { MODRM_ONEENTRY, 0 }, } }, }; capstone-sys-0.15.0/capstone/arch/X86/X86GenInstrInfo.inc000064400000000000000000014567650072674642500211030ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { X86_AAA = 146, X86_AAD8i8 = 147, X86_AAM8i8 = 148, X86_AAS = 149, X86_ABS_F = 150, X86_ABS_Fp32 = 151, X86_ABS_Fp64 = 152, X86_ABS_Fp80 = 153, X86_ADC16i16 = 154, X86_ADC16mi = 155, X86_ADC16mi8 = 156, X86_ADC16mr = 157, X86_ADC16ri = 158, X86_ADC16ri8 = 159, X86_ADC16rm = 160, X86_ADC16rr = 161, X86_ADC16rr_REV = 162, X86_ADC32i32 = 163, X86_ADC32mi = 164, X86_ADC32mi8 = 165, X86_ADC32mr = 166, X86_ADC32ri = 167, X86_ADC32ri8 = 168, X86_ADC32rm = 169, X86_ADC32rr = 170, X86_ADC32rr_REV = 171, X86_ADC64i32 = 172, X86_ADC64mi32 = 173, X86_ADC64mi8 = 174, X86_ADC64mr = 175, X86_ADC64ri32 = 176, X86_ADC64ri8 = 177, X86_ADC64rm = 178, X86_ADC64rr = 179, X86_ADC64rr_REV = 180, X86_ADC8i8 = 181, X86_ADC8mi = 182, X86_ADC8mi8 = 183, X86_ADC8mr = 184, X86_ADC8ri = 185, X86_ADC8ri8 = 186, X86_ADC8rm = 187, X86_ADC8rr = 188, X86_ADC8rr_REV = 189, X86_ADCX32rm = 190, X86_ADCX32rr = 191, X86_ADCX64rm = 192, X86_ADCX64rr = 193, X86_ADD16i16 = 194, X86_ADD16mi = 195, X86_ADD16mi8 = 196, X86_ADD16mr = 197, X86_ADD16ri = 198, X86_ADD16ri8 = 199, X86_ADD16rm = 200, X86_ADD16rr = 201, X86_ADD16rr_REV = 202, X86_ADD32i32 = 203, X86_ADD32mi = 204, X86_ADD32mi8 = 205, X86_ADD32mr = 206, X86_ADD32ri = 207, X86_ADD32ri8 = 208, X86_ADD32rm = 209, X86_ADD32rr = 210, X86_ADD32rr_REV = 211, X86_ADD64i32 = 212, X86_ADD64mi32 = 213, X86_ADD64mi8 = 214, X86_ADD64mr = 215, X86_ADD64ri32 = 216, X86_ADD64ri8 = 217, X86_ADD64rm = 218, X86_ADD64rr = 219, X86_ADD64rr_REV = 220, X86_ADD8i8 = 221, X86_ADD8mi = 222, X86_ADD8mi8 = 223, X86_ADD8mr = 224, X86_ADD8ri = 225, X86_ADD8ri8 = 226, X86_ADD8rm = 227, X86_ADD8rr = 228, X86_ADD8rr_REV = 229, X86_ADDPDrm = 230, X86_ADDPDrr = 231, X86_ADDPSrm = 232, X86_ADDPSrr = 233, X86_ADDSDrm = 234, X86_ADDSDrm_Int = 235, X86_ADDSDrr = 236, X86_ADDSDrr_Int = 237, X86_ADDSSrm = 238, X86_ADDSSrm_Int = 239, X86_ADDSSrr = 240, X86_ADDSSrr_Int = 241, X86_ADDSUBPDrm = 242, X86_ADDSUBPDrr = 243, X86_ADDSUBPSrm = 244, X86_ADDSUBPSrr = 245, X86_ADD_F32m = 246, X86_ADD_F64m = 247, X86_ADD_FI16m = 248, X86_ADD_FI32m = 249, X86_ADD_FPrST0 = 250, X86_ADD_FST0r = 251, X86_ADD_Fp32 = 252, X86_ADD_Fp32m = 253, X86_ADD_Fp64 = 254, X86_ADD_Fp64m = 255, X86_ADD_Fp64m32 = 256, X86_ADD_Fp80 = 257, X86_ADD_Fp80m32 = 258, X86_ADD_Fp80m64 = 259, X86_ADD_FpI16m32 = 260, X86_ADD_FpI16m64 = 261, X86_ADD_FpI16m80 = 262, X86_ADD_FpI32m32 = 263, X86_ADD_FpI32m64 = 264, X86_ADD_FpI32m80 = 265, X86_ADD_FrST0 = 266, X86_ADOX32rm = 267, X86_ADOX32rr = 268, X86_ADOX64rm = 269, X86_ADOX64rr = 270, X86_AESDECLASTrm = 271, X86_AESDECLASTrr = 272, X86_AESDECrm = 273, X86_AESDECrr = 274, X86_AESENCLASTrm = 275, X86_AESENCLASTrr = 276, X86_AESENCrm = 277, X86_AESENCrr = 278, X86_AESIMCrm = 279, X86_AESIMCrr = 280, X86_AESKEYGENASSIST128rm = 281, X86_AESKEYGENASSIST128rr = 282, X86_AND16i16 = 283, X86_AND16mi = 284, X86_AND16mi8 = 285, X86_AND16mr = 286, X86_AND16ri = 287, X86_AND16ri8 = 288, X86_AND16rm = 289, X86_AND16rr = 290, X86_AND16rr_REV = 291, X86_AND32i32 = 292, X86_AND32mi = 293, X86_AND32mi8 = 294, X86_AND32mr = 295, X86_AND32ri = 296, X86_AND32ri8 = 297, X86_AND32rm = 298, X86_AND32rr = 299, X86_AND32rr_REV = 300, X86_AND64i32 = 301, X86_AND64mi32 = 302, X86_AND64mi8 = 303, X86_AND64mr = 304, X86_AND64ri32 = 305, X86_AND64ri8 = 306, X86_AND64rm = 307, X86_AND64rr = 308, X86_AND64rr_REV = 309, X86_AND8i8 = 310, X86_AND8mi = 311, X86_AND8mi8 = 312, X86_AND8mr = 313, X86_AND8ri = 314, X86_AND8ri8 = 315, X86_AND8rm = 316, X86_AND8rr = 317, X86_AND8rr_REV = 318, X86_ANDN32rm = 319, X86_ANDN32rr = 320, X86_ANDN64rm = 321, X86_ANDN64rr = 322, X86_ANDNPDrm = 323, X86_ANDNPDrr = 324, X86_ANDNPSrm = 325, X86_ANDNPSrr = 326, X86_ANDPDrm = 327, X86_ANDPDrr = 328, X86_ANDPSrm = 329, X86_ANDPSrr = 330, X86_ARPL16mr = 331, X86_ARPL16rr = 332, X86_BEXTR32rm = 333, X86_BEXTR32rr = 334, X86_BEXTR64rm = 335, X86_BEXTR64rr = 336, X86_BEXTRI32mi = 337, X86_BEXTRI32ri = 338, X86_BEXTRI64mi = 339, X86_BEXTRI64ri = 340, X86_BLCFILL32rm = 341, X86_BLCFILL32rr = 342, X86_BLCFILL64rm = 343, X86_BLCFILL64rr = 344, X86_BLCI32rm = 345, X86_BLCI32rr = 346, X86_BLCI64rm = 347, X86_BLCI64rr = 348, X86_BLCIC32rm = 349, X86_BLCIC32rr = 350, X86_BLCIC64rm = 351, X86_BLCIC64rr = 352, X86_BLCMSK32rm = 353, X86_BLCMSK32rr = 354, X86_BLCMSK64rm = 355, X86_BLCMSK64rr = 356, X86_BLCS32rm = 357, X86_BLCS32rr = 358, X86_BLCS64rm = 359, X86_BLCS64rr = 360, X86_BLENDPDrmi = 361, X86_BLENDPDrri = 362, X86_BLENDPSrmi = 363, X86_BLENDPSrri = 364, X86_BLENDVPDrm0 = 365, X86_BLENDVPDrr0 = 366, X86_BLENDVPSrm0 = 367, X86_BLENDVPSrr0 = 368, X86_BLSFILL32rm = 369, X86_BLSFILL32rr = 370, X86_BLSFILL64rm = 371, X86_BLSFILL64rr = 372, X86_BLSI32rm = 373, X86_BLSI32rr = 374, X86_BLSI64rm = 375, X86_BLSI64rr = 376, X86_BLSIC32rm = 377, X86_BLSIC32rr = 378, X86_BLSIC64rm = 379, X86_BLSIC64rr = 380, X86_BLSMSK32rm = 381, X86_BLSMSK32rr = 382, X86_BLSMSK64rm = 383, X86_BLSMSK64rr = 384, X86_BLSR32rm = 385, X86_BLSR32rr = 386, X86_BLSR64rm = 387, X86_BLSR64rr = 388, X86_BNDCL32rm = 389, X86_BNDCL32rr = 390, X86_BNDCL64rm = 391, X86_BNDCL64rr = 392, X86_BNDCN32rm = 393, X86_BNDCN32rr = 394, X86_BNDCN64rm = 395, X86_BNDCN64rr = 396, X86_BNDCU32rm = 397, X86_BNDCU32rr = 398, X86_BNDCU64rm = 399, X86_BNDCU64rr = 400, X86_BNDLDXrm = 401, X86_BNDMK32rm = 402, X86_BNDMK64rm = 403, X86_BNDMOV32mr = 404, X86_BNDMOV32rm = 405, X86_BNDMOV64mr = 406, X86_BNDMOV64rm = 407, X86_BNDMOVrr = 408, X86_BNDMOVrr_REV = 409, X86_BNDSTXmr = 410, X86_BOUNDS16rm = 411, X86_BOUNDS32rm = 412, X86_BSF16rm = 413, X86_BSF16rr = 414, X86_BSF32rm = 415, X86_BSF32rr = 416, X86_BSF64rm = 417, X86_BSF64rr = 418, X86_BSR16rm = 419, X86_BSR16rr = 420, X86_BSR32rm = 421, X86_BSR32rr = 422, X86_BSR64rm = 423, X86_BSR64rr = 424, X86_BSWAP16r_BAD = 425, X86_BSWAP32r = 426, X86_BSWAP64r = 427, X86_BT16mi8 = 428, X86_BT16mr = 429, X86_BT16ri8 = 430, X86_BT16rr = 431, X86_BT32mi8 = 432, X86_BT32mr = 433, X86_BT32ri8 = 434, X86_BT32rr = 435, X86_BT64mi8 = 436, X86_BT64mr = 437, X86_BT64ri8 = 438, X86_BT64rr = 439, X86_BTC16mi8 = 440, X86_BTC16mr = 441, X86_BTC16ri8 = 442, X86_BTC16rr = 443, X86_BTC32mi8 = 444, X86_BTC32mr = 445, X86_BTC32ri8 = 446, X86_BTC32rr = 447, X86_BTC64mi8 = 448, X86_BTC64mr = 449, X86_BTC64ri8 = 450, X86_BTC64rr = 451, X86_BTR16mi8 = 452, X86_BTR16mr = 453, X86_BTR16ri8 = 454, X86_BTR16rr = 455, X86_BTR32mi8 = 456, X86_BTR32mr = 457, X86_BTR32ri8 = 458, X86_BTR32rr = 459, X86_BTR64mi8 = 460, X86_BTR64mr = 461, X86_BTR64ri8 = 462, X86_BTR64rr = 463, X86_BTS16mi8 = 464, X86_BTS16mr = 465, X86_BTS16ri8 = 466, X86_BTS16rr = 467, X86_BTS32mi8 = 468, X86_BTS32mr = 469, X86_BTS32ri8 = 470, X86_BTS32rr = 471, X86_BTS64mi8 = 472, X86_BTS64mr = 473, X86_BTS64ri8 = 474, X86_BTS64rr = 475, X86_BZHI32rm = 476, X86_BZHI32rr = 477, X86_BZHI64rm = 478, X86_BZHI64rr = 479, X86_CALL16m = 480, X86_CALL16m_NT = 481, X86_CALL16r = 482, X86_CALL16r_NT = 483, X86_CALL32m = 484, X86_CALL32m_NT = 485, X86_CALL32r = 486, X86_CALL32r_NT = 487, X86_CALL64m = 488, X86_CALL64m_NT = 489, X86_CALL64pcrel32 = 490, X86_CALL64r = 491, X86_CALL64r_NT = 492, X86_CALLpcrel16 = 493, X86_CALLpcrel32 = 494, X86_CBW = 495, X86_CDQ = 496, X86_CDQE = 497, X86_CHS_F = 498, X86_CHS_Fp32 = 499, X86_CHS_Fp64 = 500, X86_CHS_Fp80 = 501, X86_CLAC = 502, X86_CLC = 503, X86_CLD = 504, X86_CLDEMOTE = 505, X86_CLFLUSH = 506, X86_CLFLUSHOPT = 507, X86_CLGI = 508, X86_CLI = 509, X86_CLRSSBSY = 510, X86_CLTS = 511, X86_CLWB = 512, X86_CLZEROr = 513, X86_CMC = 514, X86_CMOVA16rm = 515, X86_CMOVA16rr = 516, X86_CMOVA32rm = 517, X86_CMOVA32rr = 518, X86_CMOVA64rm = 519, X86_CMOVA64rr = 520, X86_CMOVAE16rm = 521, X86_CMOVAE16rr = 522, X86_CMOVAE32rm = 523, X86_CMOVAE32rr = 524, X86_CMOVAE64rm = 525, X86_CMOVAE64rr = 526, X86_CMOVB16rm = 527, X86_CMOVB16rr = 528, X86_CMOVB32rm = 529, X86_CMOVB32rr = 530, X86_CMOVB64rm = 531, X86_CMOVB64rr = 532, X86_CMOVBE16rm = 533, X86_CMOVBE16rr = 534, X86_CMOVBE32rm = 535, X86_CMOVBE32rr = 536, X86_CMOVBE64rm = 537, X86_CMOVBE64rr = 538, X86_CMOVBE_F = 539, X86_CMOVBE_Fp32 = 540, X86_CMOVBE_Fp64 = 541, X86_CMOVBE_Fp80 = 542, X86_CMOVB_F = 543, X86_CMOVB_Fp32 = 544, X86_CMOVB_Fp64 = 545, X86_CMOVB_Fp80 = 546, X86_CMOVE16rm = 547, X86_CMOVE16rr = 548, X86_CMOVE32rm = 549, X86_CMOVE32rr = 550, X86_CMOVE64rm = 551, X86_CMOVE64rr = 552, X86_CMOVE_F = 553, X86_CMOVE_Fp32 = 554, X86_CMOVE_Fp64 = 555, X86_CMOVE_Fp80 = 556, X86_CMOVG16rm = 557, X86_CMOVG16rr = 558, X86_CMOVG32rm = 559, X86_CMOVG32rr = 560, X86_CMOVG64rm = 561, X86_CMOVG64rr = 562, X86_CMOVGE16rm = 563, X86_CMOVGE16rr = 564, X86_CMOVGE32rm = 565, X86_CMOVGE32rr = 566, X86_CMOVGE64rm = 567, X86_CMOVGE64rr = 568, X86_CMOVL16rm = 569, X86_CMOVL16rr = 570, X86_CMOVL32rm = 571, X86_CMOVL32rr = 572, X86_CMOVL64rm = 573, X86_CMOVL64rr = 574, X86_CMOVLE16rm = 575, X86_CMOVLE16rr = 576, X86_CMOVLE32rm = 577, X86_CMOVLE32rr = 578, X86_CMOVLE64rm = 579, X86_CMOVLE64rr = 580, X86_CMOVNBE_F = 581, X86_CMOVNBE_Fp32 = 582, X86_CMOVNBE_Fp64 = 583, X86_CMOVNBE_Fp80 = 584, X86_CMOVNB_F = 585, X86_CMOVNB_Fp32 = 586, X86_CMOVNB_Fp64 = 587, X86_CMOVNB_Fp80 = 588, X86_CMOVNE16rm = 589, X86_CMOVNE16rr = 590, X86_CMOVNE32rm = 591, X86_CMOVNE32rr = 592, X86_CMOVNE64rm = 593, X86_CMOVNE64rr = 594, X86_CMOVNE_F = 595, X86_CMOVNE_Fp32 = 596, X86_CMOVNE_Fp64 = 597, X86_CMOVNE_Fp80 = 598, X86_CMOVNO16rm = 599, X86_CMOVNO16rr = 600, X86_CMOVNO32rm = 601, X86_CMOVNO32rr = 602, X86_CMOVNO64rm = 603, X86_CMOVNO64rr = 604, X86_CMOVNP16rm = 605, X86_CMOVNP16rr = 606, X86_CMOVNP32rm = 607, X86_CMOVNP32rr = 608, X86_CMOVNP64rm = 609, X86_CMOVNP64rr = 610, X86_CMOVNP_F = 611, X86_CMOVNP_Fp32 = 612, X86_CMOVNP_Fp64 = 613, X86_CMOVNP_Fp80 = 614, X86_CMOVNS16rm = 615, X86_CMOVNS16rr = 616, X86_CMOVNS32rm = 617, X86_CMOVNS32rr = 618, X86_CMOVNS64rm = 619, X86_CMOVNS64rr = 620, X86_CMOVO16rm = 621, X86_CMOVO16rr = 622, X86_CMOVO32rm = 623, X86_CMOVO32rr = 624, X86_CMOVO64rm = 625, X86_CMOVO64rr = 626, X86_CMOVP16rm = 627, X86_CMOVP16rr = 628, X86_CMOVP32rm = 629, X86_CMOVP32rr = 630, X86_CMOVP64rm = 631, X86_CMOVP64rr = 632, X86_CMOVP_F = 633, X86_CMOVP_Fp32 = 634, X86_CMOVP_Fp64 = 635, X86_CMOVP_Fp80 = 636, X86_CMOVS16rm = 637, X86_CMOVS16rr = 638, X86_CMOVS32rm = 639, X86_CMOVS32rr = 640, X86_CMOVS64rm = 641, X86_CMOVS64rr = 642, X86_CMP16i16 = 643, X86_CMP16mi = 644, X86_CMP16mi8 = 645, X86_CMP16mr = 646, X86_CMP16ri = 647, X86_CMP16ri8 = 648, X86_CMP16rm = 649, X86_CMP16rr = 650, X86_CMP16rr_REV = 651, X86_CMP32i32 = 652, X86_CMP32mi = 653, X86_CMP32mi8 = 654, X86_CMP32mr = 655, X86_CMP32ri = 656, X86_CMP32ri8 = 657, X86_CMP32rm = 658, X86_CMP32rr = 659, X86_CMP32rr_REV = 660, X86_CMP64i32 = 661, X86_CMP64mi32 = 662, X86_CMP64mi8 = 663, X86_CMP64mr = 664, X86_CMP64ri32 = 665, X86_CMP64ri8 = 666, X86_CMP64rm = 667, X86_CMP64rr = 668, X86_CMP64rr_REV = 669, X86_CMP8i8 = 670, X86_CMP8mi = 671, X86_CMP8mi8 = 672, X86_CMP8mr = 673, X86_CMP8ri = 674, X86_CMP8ri8 = 675, X86_CMP8rm = 676, X86_CMP8rr = 677, X86_CMP8rr_REV = 678, X86_CMPPDrmi = 679, X86_CMPPDrmi_alt = 680, X86_CMPPDrri = 681, X86_CMPPDrri_alt = 682, X86_CMPPSrmi = 683, X86_CMPPSrmi_alt = 684, X86_CMPPSrri = 685, X86_CMPPSrri_alt = 686, X86_CMPSB = 687, X86_CMPSDrm = 688, X86_CMPSDrm_Int = 689, X86_CMPSDrm_alt = 690, X86_CMPSDrr = 691, X86_CMPSDrr_Int = 692, X86_CMPSDrr_alt = 693, X86_CMPSL = 694, X86_CMPSQ = 695, X86_CMPSSrm = 696, X86_CMPSSrm_Int = 697, X86_CMPSSrm_alt = 698, X86_CMPSSrr = 699, X86_CMPSSrr_Int = 700, X86_CMPSSrr_alt = 701, X86_CMPSW = 702, X86_CMPXCHG16B = 703, X86_CMPXCHG16rm = 704, X86_CMPXCHG16rr = 705, X86_CMPXCHG32rm = 706, X86_CMPXCHG32rr = 707, X86_CMPXCHG64rm = 708, X86_CMPXCHG64rr = 709, X86_CMPXCHG8B = 710, X86_CMPXCHG8rm = 711, X86_CMPXCHG8rr = 712, X86_COMISDrm = 713, X86_COMISDrm_Int = 714, X86_COMISDrr = 715, X86_COMISDrr_Int = 716, X86_COMISSrm = 717, X86_COMISSrm_Int = 718, X86_COMISSrr = 719, X86_COMISSrr_Int = 720, X86_COMP_FST0r = 721, X86_COM_FIPr = 722, X86_COM_FIr = 723, X86_COM_FST0r = 724, X86_COS_F = 725, X86_COS_Fp32 = 726, X86_COS_Fp64 = 727, X86_COS_Fp80 = 728, X86_CPUID = 729, X86_CQO = 730, X86_CRC32r32m16 = 731, X86_CRC32r32m32 = 732, X86_CRC32r32m8 = 733, X86_CRC32r32r16 = 734, X86_CRC32r32r32 = 735, X86_CRC32r32r8 = 736, X86_CRC32r64m64 = 737, X86_CRC32r64m8 = 738, X86_CRC32r64r64 = 739, X86_CRC32r64r8 = 740, X86_CVTDQ2PDrm = 741, X86_CVTDQ2PDrr = 742, X86_CVTDQ2PSrm = 743, X86_CVTDQ2PSrr = 744, X86_CVTPD2DQrm = 745, X86_CVTPD2DQrr = 746, X86_CVTPD2PSrm = 747, X86_CVTPD2PSrr = 748, X86_CVTPS2DQrm = 749, X86_CVTPS2DQrr = 750, X86_CVTPS2PDrm = 751, X86_CVTPS2PDrr = 752, X86_CVTSD2SI64rm_Int = 753, X86_CVTSD2SI64rr_Int = 754, X86_CVTSD2SIrm_Int = 755, X86_CVTSD2SIrr_Int = 756, X86_CVTSD2SSrm = 757, X86_CVTSD2SSrm_Int = 758, X86_CVTSD2SSrr = 759, X86_CVTSD2SSrr_Int = 760, X86_CVTSI2SDrm = 761, X86_CVTSI2SDrm_Int = 762, X86_CVTSI2SDrr = 763, X86_CVTSI2SDrr_Int = 764, X86_CVTSI2SSrm = 765, X86_CVTSI2SSrm_Int = 766, X86_CVTSI2SSrr = 767, X86_CVTSI2SSrr_Int = 768, X86_CVTSI642SDrm = 769, X86_CVTSI642SDrm_Int = 770, X86_CVTSI642SDrr = 771, X86_CVTSI642SDrr_Int = 772, X86_CVTSI642SSrm = 773, X86_CVTSI642SSrm_Int = 774, X86_CVTSI642SSrr = 775, X86_CVTSI642SSrr_Int = 776, X86_CVTSS2SDrm = 777, X86_CVTSS2SDrm_Int = 778, X86_CVTSS2SDrr = 779, X86_CVTSS2SDrr_Int = 780, X86_CVTSS2SI64rm_Int = 781, X86_CVTSS2SI64rr_Int = 782, X86_CVTSS2SIrm_Int = 783, X86_CVTSS2SIrr_Int = 784, X86_CVTTPD2DQrm = 785, X86_CVTTPD2DQrr = 786, X86_CVTTPS2DQrm = 787, X86_CVTTPS2DQrr = 788, X86_CVTTSD2SI64rm = 789, X86_CVTTSD2SI64rm_Int = 790, X86_CVTTSD2SI64rr = 791, X86_CVTTSD2SI64rr_Int = 792, X86_CVTTSD2SIrm = 793, X86_CVTTSD2SIrm_Int = 794, X86_CVTTSD2SIrr = 795, X86_CVTTSD2SIrr_Int = 796, X86_CVTTSS2SI64rm = 797, X86_CVTTSS2SI64rm_Int = 798, X86_CVTTSS2SI64rr = 799, X86_CVTTSS2SI64rr_Int = 800, X86_CVTTSS2SIrm = 801, X86_CVTTSS2SIrm_Int = 802, X86_CVTTSS2SIrr = 803, X86_CVTTSS2SIrr_Int = 804, X86_CWD = 805, X86_CWDE = 806, X86_DAA = 807, X86_DAS = 808, X86_DATA16_PREFIX = 809, X86_DEC16m = 810, X86_DEC16r = 811, X86_DEC16r_alt = 812, X86_DEC32m = 813, X86_DEC32r = 814, X86_DEC32r_alt = 815, X86_DEC64m = 816, X86_DEC64r = 817, X86_DEC8m = 818, X86_DEC8r = 819, X86_DIV16m = 820, X86_DIV16r = 821, X86_DIV32m = 822, X86_DIV32r = 823, X86_DIV64m = 824, X86_DIV64r = 825, X86_DIV8m = 826, X86_DIV8r = 827, X86_DIVPDrm = 828, X86_DIVPDrr = 829, X86_DIVPSrm = 830, X86_DIVPSrr = 831, X86_DIVR_F32m = 832, X86_DIVR_F64m = 833, X86_DIVR_FI16m = 834, X86_DIVR_FI32m = 835, X86_DIVR_FPrST0 = 836, X86_DIVR_FST0r = 837, X86_DIVR_Fp32m = 838, X86_DIVR_Fp64m = 839, X86_DIVR_Fp64m32 = 840, X86_DIVR_Fp80m32 = 841, X86_DIVR_Fp80m64 = 842, X86_DIVR_FpI16m32 = 843, X86_DIVR_FpI16m64 = 844, X86_DIVR_FpI16m80 = 845, X86_DIVR_FpI32m32 = 846, X86_DIVR_FpI32m64 = 847, X86_DIVR_FpI32m80 = 848, X86_DIVR_FrST0 = 849, X86_DIVSDrm = 850, X86_DIVSDrm_Int = 851, X86_DIVSDrr = 852, X86_DIVSDrr_Int = 853, X86_DIVSSrm = 854, X86_DIVSSrm_Int = 855, X86_DIVSSrr = 856, X86_DIVSSrr_Int = 857, X86_DIV_F32m = 858, X86_DIV_F64m = 859, X86_DIV_FI16m = 860, X86_DIV_FI32m = 861, X86_DIV_FPrST0 = 862, X86_DIV_FST0r = 863, X86_DIV_Fp32 = 864, X86_DIV_Fp32m = 865, X86_DIV_Fp64 = 866, X86_DIV_Fp64m = 867, X86_DIV_Fp64m32 = 868, X86_DIV_Fp80 = 869, X86_DIV_Fp80m32 = 870, X86_DIV_Fp80m64 = 871, X86_DIV_FpI16m32 = 872, X86_DIV_FpI16m64 = 873, X86_DIV_FpI16m80 = 874, X86_DIV_FpI32m32 = 875, X86_DIV_FpI32m64 = 876, X86_DIV_FpI32m80 = 877, X86_DIV_FrST0 = 878, X86_DPPDrmi = 879, X86_DPPDrri = 880, X86_DPPSrmi = 881, X86_DPPSrri = 882, X86_ENCLS = 883, X86_ENCLU = 884, X86_ENCLV = 885, X86_ENDBR32 = 886, X86_ENDBR64 = 887, X86_ENTER = 888, X86_EXTRACTPSmr = 889, X86_EXTRACTPSrr = 890, X86_EXTRQ = 891, X86_EXTRQI = 892, X86_F2XM1 = 893, X86_FARCALL16i = 894, X86_FARCALL16m = 895, X86_FARCALL32i = 896, X86_FARCALL32m = 897, X86_FARCALL64 = 898, X86_FARJMP16i = 899, X86_FARJMP16m = 900, X86_FARJMP32i = 901, X86_FARJMP32m = 902, X86_FARJMP64 = 903, X86_FBLDm = 904, X86_FBSTPm = 905, X86_FCOM32m = 906, X86_FCOM64m = 907, X86_FCOMP32m = 908, X86_FCOMP64m = 909, X86_FCOMPP = 910, X86_FDECSTP = 911, X86_FDISI8087_NOP = 912, X86_FEMMS = 913, X86_FENI8087_NOP = 914, X86_FFREE = 915, X86_FFREEP = 916, X86_FICOM16m = 917, X86_FICOM32m = 918, X86_FICOMP16m = 919, X86_FICOMP32m = 920, X86_FINCSTP = 921, X86_FLDCW16m = 922, X86_FLDENVm = 923, X86_FLDL2E = 924, X86_FLDL2T = 925, X86_FLDLG2 = 926, X86_FLDLN2 = 927, X86_FLDPI = 928, X86_FNCLEX = 929, X86_FNINIT = 930, X86_FNOP = 931, X86_FNSTCW16m = 932, X86_FNSTSW16r = 933, X86_FNSTSWm = 934, X86_FPATAN = 935, X86_FPNCEST0r = 936, X86_FPREM = 937, X86_FPREM1 = 938, X86_FPTAN = 939, X86_FRNDINT = 940, X86_FRSTORm = 941, X86_FSAVEm = 942, X86_FSCALE = 943, X86_FSETPM = 944, X86_FSINCOS = 945, X86_FSTENVm = 946, X86_FXAM = 947, X86_FXRSTOR = 948, X86_FXRSTOR64 = 949, X86_FXSAVE = 950, X86_FXSAVE64 = 951, X86_FXTRACT = 952, X86_FYL2X = 953, X86_FYL2XP1 = 954, X86_GETSEC = 955, X86_GF2P8AFFINEINVQBrmi = 956, X86_GF2P8AFFINEINVQBrri = 957, X86_GF2P8AFFINEQBrmi = 958, X86_GF2P8AFFINEQBrri = 959, X86_GF2P8MULBrm = 960, X86_GF2P8MULBrr = 961, X86_HADDPDrm = 962, X86_HADDPDrr = 963, X86_HADDPSrm = 964, X86_HADDPSrr = 965, X86_HLT = 966, X86_HSUBPDrm = 967, X86_HSUBPDrr = 968, X86_HSUBPSrm = 969, X86_HSUBPSrr = 970, X86_IDIV16m = 971, X86_IDIV16r = 972, X86_IDIV32m = 973, X86_IDIV32r = 974, X86_IDIV64m = 975, X86_IDIV64r = 976, X86_IDIV8m = 977, X86_IDIV8r = 978, X86_ILD_F16m = 979, X86_ILD_F32m = 980, X86_ILD_F64m = 981, X86_ILD_Fp16m32 = 982, X86_ILD_Fp16m64 = 983, X86_ILD_Fp16m80 = 984, X86_ILD_Fp32m32 = 985, X86_ILD_Fp32m64 = 986, X86_ILD_Fp32m80 = 987, X86_ILD_Fp64m32 = 988, X86_ILD_Fp64m64 = 989, X86_ILD_Fp64m80 = 990, X86_IMUL16m = 991, X86_IMUL16r = 992, X86_IMUL16rm = 993, X86_IMUL16rmi = 994, X86_IMUL16rmi8 = 995, X86_IMUL16rr = 996, X86_IMUL16rri = 997, X86_IMUL16rri8 = 998, X86_IMUL32m = 999, X86_IMUL32r = 1000, X86_IMUL32rm = 1001, X86_IMUL32rmi = 1002, X86_IMUL32rmi8 = 1003, X86_IMUL32rr = 1004, X86_IMUL32rri = 1005, X86_IMUL32rri8 = 1006, X86_IMUL64m = 1007, X86_IMUL64r = 1008, X86_IMUL64rm = 1009, X86_IMUL64rmi32 = 1010, X86_IMUL64rmi8 = 1011, X86_IMUL64rr = 1012, X86_IMUL64rri32 = 1013, X86_IMUL64rri8 = 1014, X86_IMUL8m = 1015, X86_IMUL8r = 1016, X86_IN16ri = 1017, X86_IN16rr = 1018, X86_IN32ri = 1019, X86_IN32rr = 1020, X86_IN8ri = 1021, X86_IN8rr = 1022, X86_INC16m = 1023, X86_INC16r = 1024, X86_INC16r_alt = 1025, X86_INC32m = 1026, X86_INC32r = 1027, X86_INC32r_alt = 1028, X86_INC64m = 1029, X86_INC64r = 1030, X86_INC8m = 1031, X86_INC8r = 1032, X86_INCSSPD = 1033, X86_INCSSPQ = 1034, X86_INSB = 1035, X86_INSERTPSrm = 1036, X86_INSERTPSrr = 1037, X86_INSERTQ = 1038, X86_INSERTQI = 1039, X86_INSL = 1040, X86_INSW = 1041, X86_INT = 1042, X86_INT1 = 1043, X86_INT3 = 1044, X86_INTO = 1045, X86_INVD = 1046, X86_INVEPT32 = 1047, X86_INVEPT64 = 1048, X86_INVLPG = 1049, X86_INVLPGA32 = 1050, X86_INVLPGA64 = 1051, X86_INVPCID32 = 1052, X86_INVPCID64 = 1053, X86_INVVPID32 = 1054, X86_INVVPID64 = 1055, X86_IRET16 = 1056, X86_IRET32 = 1057, X86_IRET64 = 1058, X86_ISTT_FP16m = 1059, X86_ISTT_FP32m = 1060, X86_ISTT_FP64m = 1061, X86_ISTT_Fp16m32 = 1062, X86_ISTT_Fp16m64 = 1063, X86_ISTT_Fp16m80 = 1064, X86_ISTT_Fp32m32 = 1065, X86_ISTT_Fp32m64 = 1066, X86_ISTT_Fp32m80 = 1067, X86_ISTT_Fp64m32 = 1068, X86_ISTT_Fp64m64 = 1069, X86_ISTT_Fp64m80 = 1070, X86_IST_F16m = 1071, X86_IST_F32m = 1072, X86_IST_FP16m = 1073, X86_IST_FP32m = 1074, X86_IST_FP64m = 1075, X86_IST_Fp16m32 = 1076, X86_IST_Fp16m64 = 1077, X86_IST_Fp16m80 = 1078, X86_IST_Fp32m32 = 1079, X86_IST_Fp32m64 = 1080, X86_IST_Fp32m80 = 1081, X86_IST_Fp64m32 = 1082, X86_IST_Fp64m64 = 1083, X86_IST_Fp64m80 = 1084, X86_JAE_1 = 1085, X86_JAE_2 = 1086, X86_JAE_4 = 1087, X86_JA_1 = 1088, X86_JA_2 = 1089, X86_JA_4 = 1090, X86_JBE_1 = 1091, X86_JBE_2 = 1092, X86_JBE_4 = 1093, X86_JB_1 = 1094, X86_JB_2 = 1095, X86_JB_4 = 1096, X86_JCXZ = 1097, X86_JECXZ = 1098, X86_JE_1 = 1099, X86_JE_2 = 1100, X86_JE_4 = 1101, X86_JGE_1 = 1102, X86_JGE_2 = 1103, X86_JGE_4 = 1104, X86_JG_1 = 1105, X86_JG_2 = 1106, X86_JG_4 = 1107, X86_JLE_1 = 1108, X86_JLE_2 = 1109, X86_JLE_4 = 1110, X86_JL_1 = 1111, X86_JL_2 = 1112, X86_JL_4 = 1113, X86_JMP16m = 1114, X86_JMP16m_NT = 1115, X86_JMP16r = 1116, X86_JMP16r_NT = 1117, X86_JMP32m = 1118, X86_JMP32m_NT = 1119, X86_JMP32r = 1120, X86_JMP32r_NT = 1121, X86_JMP64m = 1122, X86_JMP64m_NT = 1123, X86_JMP64r = 1124, X86_JMP64r_NT = 1125, X86_JMP_1 = 1126, X86_JMP_2 = 1127, X86_JMP_4 = 1128, X86_JNE_1 = 1129, X86_JNE_2 = 1130, X86_JNE_4 = 1131, X86_JNO_1 = 1132, X86_JNO_2 = 1133, X86_JNO_4 = 1134, X86_JNP_1 = 1135, X86_JNP_2 = 1136, X86_JNP_4 = 1137, X86_JNS_1 = 1138, X86_JNS_2 = 1139, X86_JNS_4 = 1140, X86_JO_1 = 1141, X86_JO_2 = 1142, X86_JO_4 = 1143, X86_JP_1 = 1144, X86_JP_2 = 1145, X86_JP_4 = 1146, X86_JRCXZ = 1147, X86_JS_1 = 1148, X86_JS_2 = 1149, X86_JS_4 = 1150, X86_KADDBrr = 1151, X86_KADDDrr = 1152, X86_KADDQrr = 1153, X86_KADDWrr = 1154, X86_KANDBrr = 1155, X86_KANDDrr = 1156, X86_KANDNBrr = 1157, X86_KANDNDrr = 1158, X86_KANDNQrr = 1159, X86_KANDNWrr = 1160, X86_KANDQrr = 1161, X86_KANDWrr = 1162, X86_KMOVBkk = 1163, X86_KMOVBkm = 1164, X86_KMOVBkr = 1165, X86_KMOVBmk = 1166, X86_KMOVBrk = 1167, X86_KMOVDkk = 1168, X86_KMOVDkm = 1169, X86_KMOVDkr = 1170, X86_KMOVDmk = 1171, X86_KMOVDrk = 1172, X86_KMOVQkk = 1173, X86_KMOVQkm = 1174, X86_KMOVQkr = 1175, X86_KMOVQmk = 1176, X86_KMOVQrk = 1177, X86_KMOVWkk = 1178, X86_KMOVWkm = 1179, X86_KMOVWkr = 1180, X86_KMOVWmk = 1181, X86_KMOVWrk = 1182, X86_KNOTBrr = 1183, X86_KNOTDrr = 1184, X86_KNOTQrr = 1185, X86_KNOTWrr = 1186, X86_KORBrr = 1187, X86_KORDrr = 1188, X86_KORQrr = 1189, X86_KORTESTBrr = 1190, X86_KORTESTDrr = 1191, X86_KORTESTQrr = 1192, X86_KORTESTWrr = 1193, X86_KORWrr = 1194, X86_KSHIFTLBri = 1195, X86_KSHIFTLDri = 1196, X86_KSHIFTLQri = 1197, X86_KSHIFTLWri = 1198, X86_KSHIFTRBri = 1199, X86_KSHIFTRDri = 1200, X86_KSHIFTRQri = 1201, X86_KSHIFTRWri = 1202, X86_KTESTBrr = 1203, X86_KTESTDrr = 1204, X86_KTESTQrr = 1205, X86_KTESTWrr = 1206, X86_KUNPCKBWrr = 1207, X86_KUNPCKDQrr = 1208, X86_KUNPCKWDrr = 1209, X86_KXNORBrr = 1210, X86_KXNORDrr = 1211, X86_KXNORQrr = 1212, X86_KXNORWrr = 1213, X86_KXORBrr = 1214, X86_KXORDrr = 1215, X86_KXORQrr = 1216, X86_KXORWrr = 1217, X86_LAHF = 1218, X86_LAR16rm = 1219, X86_LAR16rr = 1220, X86_LAR32rm = 1221, X86_LAR32rr = 1222, X86_LAR64rm = 1223, X86_LAR64rr = 1224, X86_LDDQUrm = 1225, X86_LDMXCSR = 1226, X86_LDS16rm = 1227, X86_LDS32rm = 1228, X86_LD_F0 = 1229, X86_LD_F1 = 1230, X86_LD_F32m = 1231, X86_LD_F64m = 1232, X86_LD_F80m = 1233, X86_LD_Fp032 = 1234, X86_LD_Fp064 = 1235, X86_LD_Fp080 = 1236, X86_LD_Fp132 = 1237, X86_LD_Fp164 = 1238, X86_LD_Fp180 = 1239, X86_LD_Fp32m = 1240, X86_LD_Fp32m64 = 1241, X86_LD_Fp32m80 = 1242, X86_LD_Fp64m = 1243, X86_LD_Fp64m80 = 1244, X86_LD_Fp80m = 1245, X86_LD_Frr = 1246, X86_LEA16r = 1247, X86_LEA32r = 1248, X86_LEA64_32r = 1249, X86_LEA64r = 1250, X86_LEAVE = 1251, X86_LEAVE64 = 1252, X86_LES16rm = 1253, X86_LES32rm = 1254, X86_LFENCE = 1255, X86_LFS16rm = 1256, X86_LFS32rm = 1257, X86_LFS64rm = 1258, X86_LGDT16m = 1259, X86_LGDT32m = 1260, X86_LGDT64m = 1261, X86_LGS16rm = 1262, X86_LGS32rm = 1263, X86_LGS64rm = 1264, X86_LIDT16m = 1265, X86_LIDT32m = 1266, X86_LIDT64m = 1267, X86_LLDT16m = 1268, X86_LLDT16r = 1269, X86_LLWPCB = 1270, X86_LLWPCB64 = 1271, X86_LMSW16m = 1272, X86_LMSW16r = 1273, X86_LOCK_PREFIX = 1274, X86_LODSB = 1275, X86_LODSL = 1276, X86_LODSQ = 1277, X86_LODSW = 1278, X86_LOOP = 1279, X86_LOOPE = 1280, X86_LOOPNE = 1281, X86_LRETIL = 1282, X86_LRETIQ = 1283, X86_LRETIW = 1284, X86_LRETL = 1285, X86_LRETQ = 1286, X86_LRETW = 1287, X86_LSL16rm = 1288, X86_LSL16rr = 1289, X86_LSL32rm = 1290, X86_LSL32rr = 1291, X86_LSL64rm = 1292, X86_LSL64rr = 1293, X86_LSS16rm = 1294, X86_LSS32rm = 1295, X86_LSS64rm = 1296, X86_LTRm = 1297, X86_LTRr = 1298, X86_LWPINS32rmi = 1299, X86_LWPINS32rri = 1300, X86_LWPINS64rmi = 1301, X86_LWPINS64rri = 1302, X86_LWPVAL32rmi = 1303, X86_LWPVAL32rri = 1304, X86_LWPVAL64rmi = 1305, X86_LWPVAL64rri = 1306, X86_LZCNT16rm = 1307, X86_LZCNT16rr = 1308, X86_LZCNT32rm = 1309, X86_LZCNT32rr = 1310, X86_LZCNT64rm = 1311, X86_LZCNT64rr = 1312, X86_MASKMOVDQU = 1313, X86_MASKMOVDQU64 = 1314, X86_MAXCPDrm = 1315, X86_MAXCPDrr = 1316, X86_MAXCPSrm = 1317, X86_MAXCPSrr = 1318, X86_MAXCSDrm = 1319, X86_MAXCSDrr = 1320, X86_MAXCSSrm = 1321, X86_MAXCSSrr = 1322, X86_MAXPDrm = 1323, X86_MAXPDrr = 1324, X86_MAXPSrm = 1325, X86_MAXPSrr = 1326, X86_MAXSDrm = 1327, X86_MAXSDrm_Int = 1328, X86_MAXSDrr = 1329, X86_MAXSDrr_Int = 1330, X86_MAXSSrm = 1331, X86_MAXSSrm_Int = 1332, X86_MAXSSrr = 1333, X86_MAXSSrr_Int = 1334, X86_MFENCE = 1335, X86_MINCPDrm = 1336, X86_MINCPDrr = 1337, X86_MINCPSrm = 1338, X86_MINCPSrr = 1339, X86_MINCSDrm = 1340, X86_MINCSDrr = 1341, X86_MINCSSrm = 1342, X86_MINCSSrr = 1343, X86_MINPDrm = 1344, X86_MINPDrr = 1345, X86_MINPSrm = 1346, X86_MINPSrr = 1347, X86_MINSDrm = 1348, X86_MINSDrm_Int = 1349, X86_MINSDrr = 1350, X86_MINSDrr_Int = 1351, X86_MINSSrm = 1352, X86_MINSSrm_Int = 1353, X86_MINSSrr = 1354, X86_MINSSrr_Int = 1355, X86_MMX_CVTPD2PIirm = 1356, X86_MMX_CVTPD2PIirr = 1357, X86_MMX_CVTPI2PDirm = 1358, X86_MMX_CVTPI2PDirr = 1359, X86_MMX_CVTPI2PSirm = 1360, X86_MMX_CVTPI2PSirr = 1361, X86_MMX_CVTPS2PIirm = 1362, X86_MMX_CVTPS2PIirr = 1363, X86_MMX_CVTTPD2PIirm = 1364, X86_MMX_CVTTPD2PIirr = 1365, X86_MMX_CVTTPS2PIirm = 1366, X86_MMX_CVTTPS2PIirr = 1367, X86_MMX_EMMS = 1368, X86_MMX_MASKMOVQ = 1369, X86_MMX_MASKMOVQ64 = 1370, X86_MMX_MOVD64from64rm = 1371, X86_MMX_MOVD64from64rr = 1372, X86_MMX_MOVD64grr = 1373, X86_MMX_MOVD64mr = 1374, X86_MMX_MOVD64rm = 1375, X86_MMX_MOVD64rr = 1376, X86_MMX_MOVD64to64rm = 1377, X86_MMX_MOVD64to64rr = 1378, X86_MMX_MOVDQ2Qrr = 1379, X86_MMX_MOVFR642Qrr = 1380, X86_MMX_MOVNTQmr = 1381, X86_MMX_MOVQ2DQrr = 1382, X86_MMX_MOVQ2FR64rr = 1383, X86_MMX_MOVQ64mr = 1384, X86_MMX_MOVQ64rm = 1385, X86_MMX_MOVQ64rr = 1386, X86_MMX_MOVQ64rr_REV = 1387, X86_MMX_PABSBrm = 1388, X86_MMX_PABSBrr = 1389, X86_MMX_PABSDrm = 1390, X86_MMX_PABSDrr = 1391, X86_MMX_PABSWrm = 1392, X86_MMX_PABSWrr = 1393, X86_MMX_PACKSSDWirm = 1394, X86_MMX_PACKSSDWirr = 1395, X86_MMX_PACKSSWBirm = 1396, X86_MMX_PACKSSWBirr = 1397, X86_MMX_PACKUSWBirm = 1398, X86_MMX_PACKUSWBirr = 1399, X86_MMX_PADDBirm = 1400, X86_MMX_PADDBirr = 1401, X86_MMX_PADDDirm = 1402, X86_MMX_PADDDirr = 1403, X86_MMX_PADDQirm = 1404, X86_MMX_PADDQirr = 1405, X86_MMX_PADDSBirm = 1406, X86_MMX_PADDSBirr = 1407, X86_MMX_PADDSWirm = 1408, X86_MMX_PADDSWirr = 1409, X86_MMX_PADDUSBirm = 1410, X86_MMX_PADDUSBirr = 1411, X86_MMX_PADDUSWirm = 1412, X86_MMX_PADDUSWirr = 1413, X86_MMX_PADDWirm = 1414, X86_MMX_PADDWirr = 1415, X86_MMX_PALIGNRrmi = 1416, X86_MMX_PALIGNRrri = 1417, X86_MMX_PANDNirm = 1418, X86_MMX_PANDNirr = 1419, X86_MMX_PANDirm = 1420, X86_MMX_PANDirr = 1421, X86_MMX_PAVGBirm = 1422, X86_MMX_PAVGBirr = 1423, X86_MMX_PAVGWirm = 1424, X86_MMX_PAVGWirr = 1425, X86_MMX_PCMPEQBirm = 1426, X86_MMX_PCMPEQBirr = 1427, X86_MMX_PCMPEQDirm = 1428, X86_MMX_PCMPEQDirr = 1429, X86_MMX_PCMPEQWirm = 1430, X86_MMX_PCMPEQWirr = 1431, X86_MMX_PCMPGTBirm = 1432, X86_MMX_PCMPGTBirr = 1433, X86_MMX_PCMPGTDirm = 1434, X86_MMX_PCMPGTDirr = 1435, X86_MMX_PCMPGTWirm = 1436, X86_MMX_PCMPGTWirr = 1437, X86_MMX_PEXTRWrr = 1438, X86_MMX_PHADDDrm = 1439, X86_MMX_PHADDDrr = 1440, X86_MMX_PHADDSWrm = 1441, X86_MMX_PHADDSWrr = 1442, X86_MMX_PHADDWrm = 1443, X86_MMX_PHADDWrr = 1444, X86_MMX_PHSUBDrm = 1445, X86_MMX_PHSUBDrr = 1446, X86_MMX_PHSUBSWrm = 1447, X86_MMX_PHSUBSWrr = 1448, X86_MMX_PHSUBWrm = 1449, X86_MMX_PHSUBWrr = 1450, X86_MMX_PINSRWrm = 1451, X86_MMX_PINSRWrr = 1452, X86_MMX_PMADDUBSWrm = 1453, X86_MMX_PMADDUBSWrr = 1454, X86_MMX_PMADDWDirm = 1455, X86_MMX_PMADDWDirr = 1456, X86_MMX_PMAXSWirm = 1457, X86_MMX_PMAXSWirr = 1458, X86_MMX_PMAXUBirm = 1459, X86_MMX_PMAXUBirr = 1460, X86_MMX_PMINSWirm = 1461, X86_MMX_PMINSWirr = 1462, X86_MMX_PMINUBirm = 1463, X86_MMX_PMINUBirr = 1464, X86_MMX_PMOVMSKBrr = 1465, X86_MMX_PMULHRSWrm = 1466, X86_MMX_PMULHRSWrr = 1467, X86_MMX_PMULHUWirm = 1468, X86_MMX_PMULHUWirr = 1469, X86_MMX_PMULHWirm = 1470, X86_MMX_PMULHWirr = 1471, X86_MMX_PMULLWirm = 1472, X86_MMX_PMULLWirr = 1473, X86_MMX_PMULUDQirm = 1474, X86_MMX_PMULUDQirr = 1475, X86_MMX_PORirm = 1476, X86_MMX_PORirr = 1477, X86_MMX_PSADBWirm = 1478, X86_MMX_PSADBWirr = 1479, X86_MMX_PSHUFBrm = 1480, X86_MMX_PSHUFBrr = 1481, X86_MMX_PSHUFWmi = 1482, X86_MMX_PSHUFWri = 1483, X86_MMX_PSIGNBrm = 1484, X86_MMX_PSIGNBrr = 1485, X86_MMX_PSIGNDrm = 1486, X86_MMX_PSIGNDrr = 1487, X86_MMX_PSIGNWrm = 1488, X86_MMX_PSIGNWrr = 1489, X86_MMX_PSLLDri = 1490, X86_MMX_PSLLDrm = 1491, X86_MMX_PSLLDrr = 1492, X86_MMX_PSLLQri = 1493, X86_MMX_PSLLQrm = 1494, X86_MMX_PSLLQrr = 1495, X86_MMX_PSLLWri = 1496, X86_MMX_PSLLWrm = 1497, X86_MMX_PSLLWrr = 1498, X86_MMX_PSRADri = 1499, X86_MMX_PSRADrm = 1500, X86_MMX_PSRADrr = 1501, X86_MMX_PSRAWri = 1502, X86_MMX_PSRAWrm = 1503, X86_MMX_PSRAWrr = 1504, X86_MMX_PSRLDri = 1505, X86_MMX_PSRLDrm = 1506, X86_MMX_PSRLDrr = 1507, X86_MMX_PSRLQri = 1508, X86_MMX_PSRLQrm = 1509, X86_MMX_PSRLQrr = 1510, X86_MMX_PSRLWri = 1511, X86_MMX_PSRLWrm = 1512, X86_MMX_PSRLWrr = 1513, X86_MMX_PSUBBirm = 1514, X86_MMX_PSUBBirr = 1515, X86_MMX_PSUBDirm = 1516, X86_MMX_PSUBDirr = 1517, X86_MMX_PSUBQirm = 1518, X86_MMX_PSUBQirr = 1519, X86_MMX_PSUBSBirm = 1520, X86_MMX_PSUBSBirr = 1521, X86_MMX_PSUBSWirm = 1522, X86_MMX_PSUBSWirr = 1523, X86_MMX_PSUBUSBirm = 1524, X86_MMX_PSUBUSBirr = 1525, X86_MMX_PSUBUSWirm = 1526, X86_MMX_PSUBUSWirr = 1527, X86_MMX_PSUBWirm = 1528, X86_MMX_PSUBWirr = 1529, X86_MMX_PUNPCKHBWirm = 1530, X86_MMX_PUNPCKHBWirr = 1531, X86_MMX_PUNPCKHDQirm = 1532, X86_MMX_PUNPCKHDQirr = 1533, X86_MMX_PUNPCKHWDirm = 1534, X86_MMX_PUNPCKHWDirr = 1535, X86_MMX_PUNPCKLBWirm = 1536, X86_MMX_PUNPCKLBWirr = 1537, X86_MMX_PUNPCKLDQirm = 1538, X86_MMX_PUNPCKLDQirr = 1539, X86_MMX_PUNPCKLWDirm = 1540, X86_MMX_PUNPCKLWDirr = 1541, X86_MMX_PXORirm = 1542, X86_MMX_PXORirr = 1543, X86_MONITORXrrr = 1544, X86_MONITORrrr = 1545, X86_MONTMUL = 1546, X86_MOV16ao16 = 1547, X86_MOV16ao32 = 1548, X86_MOV16ao64 = 1549, X86_MOV16mi = 1550, X86_MOV16mr = 1551, X86_MOV16ms = 1552, X86_MOV16o16a = 1553, X86_MOV16o32a = 1554, X86_MOV16o64a = 1555, X86_MOV16ri = 1556, X86_MOV16ri_alt = 1557, X86_MOV16rm = 1558, X86_MOV16rr = 1559, X86_MOV16rr_REV = 1560, X86_MOV16rs = 1561, X86_MOV16sm = 1562, X86_MOV16sr = 1563, X86_MOV32ao16 = 1564, X86_MOV32ao32 = 1565, X86_MOV32ao64 = 1566, X86_MOV32cr = 1567, X86_MOV32dr = 1568, X86_MOV32mi = 1569, X86_MOV32mr = 1570, X86_MOV32o16a = 1571, X86_MOV32o32a = 1572, X86_MOV32o64a = 1573, X86_MOV32rc = 1574, X86_MOV32rd = 1575, X86_MOV32ri = 1576, X86_MOV32ri_alt = 1577, X86_MOV32rm = 1578, X86_MOV32rr = 1579, X86_MOV32rr_REV = 1580, X86_MOV32rs = 1581, X86_MOV32sr = 1582, X86_MOV64ao32 = 1583, X86_MOV64ao64 = 1584, X86_MOV64cr = 1585, X86_MOV64dr = 1586, X86_MOV64mi32 = 1587, X86_MOV64mr = 1588, X86_MOV64o32a = 1589, X86_MOV64o64a = 1590, X86_MOV64rc = 1591, X86_MOV64rd = 1592, X86_MOV64ri = 1593, X86_MOV64ri32 = 1594, X86_MOV64rm = 1595, X86_MOV64rr = 1596, X86_MOV64rr_REV = 1597, X86_MOV64rs = 1598, X86_MOV64sr = 1599, X86_MOV64toPQIrm = 1600, X86_MOV64toPQIrr = 1601, X86_MOV64toSDrm = 1602, X86_MOV64toSDrr = 1603, X86_MOV8ao16 = 1604, X86_MOV8ao32 = 1605, X86_MOV8ao64 = 1606, X86_MOV8mi = 1607, X86_MOV8mr = 1608, X86_MOV8mr_NOREX = 1609, X86_MOV8o16a = 1610, X86_MOV8o32a = 1611, X86_MOV8o64a = 1612, X86_MOV8ri = 1613, X86_MOV8ri_alt = 1614, X86_MOV8rm = 1615, X86_MOV8rm_NOREX = 1616, X86_MOV8rr = 1617, X86_MOV8rr_NOREX = 1618, X86_MOV8rr_REV = 1619, X86_MOVAPDmr = 1620, X86_MOVAPDrm = 1621, X86_MOVAPDrr = 1622, X86_MOVAPDrr_REV = 1623, X86_MOVAPSmr = 1624, X86_MOVAPSrm = 1625, X86_MOVAPSrr = 1626, X86_MOVAPSrr_REV = 1627, X86_MOVBE16mr = 1628, X86_MOVBE16rm = 1629, X86_MOVBE32mr = 1630, X86_MOVBE32rm = 1631, X86_MOVBE64mr = 1632, X86_MOVBE64rm = 1633, X86_MOVDDUPrm = 1634, X86_MOVDDUPrr = 1635, X86_MOVDI2PDIrm = 1636, X86_MOVDI2PDIrr = 1637, X86_MOVDI2SSrm = 1638, X86_MOVDI2SSrr = 1639, X86_MOVDIR64B16 = 1640, X86_MOVDIR64B32 = 1641, X86_MOVDIR64B64 = 1642, X86_MOVDIRI32 = 1643, X86_MOVDIRI64 = 1644, X86_MOVDQAmr = 1645, X86_MOVDQArm = 1646, X86_MOVDQArr = 1647, X86_MOVDQArr_REV = 1648, X86_MOVDQUmr = 1649, X86_MOVDQUrm = 1650, X86_MOVDQUrr = 1651, X86_MOVDQUrr_REV = 1652, X86_MOVHLPSrr = 1653, X86_MOVHPDmr = 1654, X86_MOVHPDrm = 1655, X86_MOVHPSmr = 1656, X86_MOVHPSrm = 1657, X86_MOVLHPSrr = 1658, X86_MOVLPDmr = 1659, X86_MOVLPDrm = 1660, X86_MOVLPSmr = 1661, X86_MOVLPSrm = 1662, X86_MOVMSKPDrr = 1663, X86_MOVMSKPSrr = 1664, X86_MOVNTDQArm = 1665, X86_MOVNTDQmr = 1666, X86_MOVNTI_64mr = 1667, X86_MOVNTImr = 1668, X86_MOVNTPDmr = 1669, X86_MOVNTPSmr = 1670, X86_MOVNTSD = 1671, X86_MOVNTSS = 1672, X86_MOVPDI2DImr = 1673, X86_MOVPDI2DIrr = 1674, X86_MOVPQI2QImr = 1675, X86_MOVPQI2QIrr = 1676, X86_MOVPQIto64mr = 1677, X86_MOVPQIto64rr = 1678, X86_MOVQI2PQIrm = 1679, X86_MOVSB = 1680, X86_MOVSDmr = 1681, X86_MOVSDrm = 1682, X86_MOVSDrr = 1683, X86_MOVSDrr_REV = 1684, X86_MOVSDto64mr = 1685, X86_MOVSDto64rr = 1686, X86_MOVSHDUPrm = 1687, X86_MOVSHDUPrr = 1688, X86_MOVSL = 1689, X86_MOVSLDUPrm = 1690, X86_MOVSLDUPrr = 1691, X86_MOVSQ = 1692, X86_MOVSS2DImr = 1693, X86_MOVSS2DIrr = 1694, X86_MOVSSmr = 1695, X86_MOVSSrm = 1696, X86_MOVSSrr = 1697, X86_MOVSSrr_REV = 1698, X86_MOVSW = 1699, X86_MOVSX16rm16 = 1700, X86_MOVSX16rm8 = 1701, X86_MOVSX16rr16 = 1702, X86_MOVSX16rr8 = 1703, X86_MOVSX32rm16 = 1704, X86_MOVSX32rm8 = 1705, X86_MOVSX32rm8_NOREX = 1706, X86_MOVSX32rr16 = 1707, X86_MOVSX32rr8 = 1708, X86_MOVSX32rr8_NOREX = 1709, X86_MOVSX64rm16 = 1710, X86_MOVSX64rm32 = 1711, X86_MOVSX64rm8 = 1712, X86_MOVSX64rr16 = 1713, X86_MOVSX64rr32 = 1714, X86_MOVSX64rr8 = 1715, X86_MOVUPDmr = 1716, X86_MOVUPDrm = 1717, X86_MOVUPDrr = 1718, X86_MOVUPDrr_REV = 1719, X86_MOVUPSmr = 1720, X86_MOVUPSrm = 1721, X86_MOVUPSrr = 1722, X86_MOVUPSrr_REV = 1723, X86_MOVZPQILo2PQIrr = 1724, X86_MOVZX16rm16 = 1725, X86_MOVZX16rm8 = 1726, X86_MOVZX16rr16 = 1727, X86_MOVZX16rr8 = 1728, X86_MOVZX32rm16 = 1729, X86_MOVZX32rm8 = 1730, X86_MOVZX32rm8_NOREX = 1731, X86_MOVZX32rr16 = 1732, X86_MOVZX32rr8 = 1733, X86_MOVZX32rr8_NOREX = 1734, X86_MOVZX64rm16 = 1735, X86_MOVZX64rm8 = 1736, X86_MOVZX64rr16 = 1737, X86_MOVZX64rr8 = 1738, X86_MPSADBWrmi = 1739, X86_MPSADBWrri = 1740, X86_MUL16m = 1741, X86_MUL16r = 1742, X86_MUL32m = 1743, X86_MUL32r = 1744, X86_MUL64m = 1745, X86_MUL64r = 1746, X86_MUL8m = 1747, X86_MUL8r = 1748, X86_MULPDrm = 1749, X86_MULPDrr = 1750, X86_MULPSrm = 1751, X86_MULPSrr = 1752, X86_MULSDrm = 1753, X86_MULSDrm_Int = 1754, X86_MULSDrr = 1755, X86_MULSDrr_Int = 1756, X86_MULSSrm = 1757, X86_MULSSrm_Int = 1758, X86_MULSSrr = 1759, X86_MULSSrr_Int = 1760, X86_MULX32rm = 1761, X86_MULX32rr = 1762, X86_MULX64rm = 1763, X86_MULX64rr = 1764, X86_MUL_F32m = 1765, X86_MUL_F64m = 1766, X86_MUL_FI16m = 1767, X86_MUL_FI32m = 1768, X86_MUL_FPrST0 = 1769, X86_MUL_FST0r = 1770, X86_MUL_Fp32 = 1771, X86_MUL_Fp32m = 1772, X86_MUL_Fp64 = 1773, X86_MUL_Fp64m = 1774, X86_MUL_Fp64m32 = 1775, X86_MUL_Fp80 = 1776, X86_MUL_Fp80m32 = 1777, X86_MUL_Fp80m64 = 1778, X86_MUL_FpI16m32 = 1779, X86_MUL_FpI16m64 = 1780, X86_MUL_FpI16m80 = 1781, X86_MUL_FpI32m32 = 1782, X86_MUL_FpI32m64 = 1783, X86_MUL_FpI32m80 = 1784, X86_MUL_FrST0 = 1785, X86_MWAITXrrr = 1786, X86_MWAITrr = 1787, X86_NEG16m = 1788, X86_NEG16r = 1789, X86_NEG32m = 1790, X86_NEG32r = 1791, X86_NEG64m = 1792, X86_NEG64r = 1793, X86_NEG8m = 1794, X86_NEG8r = 1795, X86_NOOP = 1796, X86_NOOP18_16m4 = 1797, X86_NOOP18_16m5 = 1798, X86_NOOP18_16m6 = 1799, X86_NOOP18_16m7 = 1800, X86_NOOP18_16r4 = 1801, X86_NOOP18_16r5 = 1802, X86_NOOP18_16r6 = 1803, X86_NOOP18_16r7 = 1804, X86_NOOP18_m4 = 1805, X86_NOOP18_m5 = 1806, X86_NOOP18_m6 = 1807, X86_NOOP18_m7 = 1808, X86_NOOP18_r4 = 1809, X86_NOOP18_r5 = 1810, X86_NOOP18_r6 = 1811, X86_NOOP18_r7 = 1812, X86_NOOP19rr = 1813, X86_NOOPL = 1814, X86_NOOPL_19 = 1815, X86_NOOPL_1d = 1816, X86_NOOPL_1e = 1817, X86_NOOPLr = 1818, X86_NOOPQ = 1819, X86_NOOPQr = 1820, X86_NOOPW = 1821, X86_NOOPW_19 = 1822, X86_NOOPW_1c = 1823, X86_NOOPW_1d = 1824, X86_NOOPW_1e = 1825, X86_NOOPWr = 1826, X86_NOT16m = 1827, X86_NOT16r = 1828, X86_NOT32m = 1829, X86_NOT32r = 1830, X86_NOT64m = 1831, X86_NOT64r = 1832, X86_NOT8m = 1833, X86_NOT8r = 1834, X86_OR16i16 = 1835, X86_OR16mi = 1836, X86_OR16mi8 = 1837, X86_OR16mr = 1838, X86_OR16ri = 1839, X86_OR16ri8 = 1840, X86_OR16rm = 1841, X86_OR16rr = 1842, X86_OR16rr_REV = 1843, X86_OR32i32 = 1844, X86_OR32mi = 1845, X86_OR32mi8 = 1846, X86_OR32mr = 1847, X86_OR32ri = 1848, X86_OR32ri8 = 1849, X86_OR32rm = 1850, X86_OR32rr = 1851, X86_OR32rr_REV = 1852, X86_OR64i32 = 1853, X86_OR64mi32 = 1854, X86_OR64mi8 = 1855, X86_OR64mr = 1856, X86_OR64ri32 = 1857, X86_OR64ri8 = 1858, X86_OR64rm = 1859, X86_OR64rr = 1860, X86_OR64rr_REV = 1861, X86_OR8i8 = 1862, X86_OR8mi = 1863, X86_OR8mi8 = 1864, X86_OR8mr = 1865, X86_OR8ri = 1866, X86_OR8ri8 = 1867, X86_OR8rm = 1868, X86_OR8rr = 1869, X86_OR8rr_REV = 1870, X86_ORPDrm = 1871, X86_ORPDrr = 1872, X86_ORPSrm = 1873, X86_ORPSrr = 1874, X86_OUT16ir = 1875, X86_OUT16rr = 1876, X86_OUT32ir = 1877, X86_OUT32rr = 1878, X86_OUT8ir = 1879, X86_OUT8rr = 1880, X86_OUTSB = 1881, X86_OUTSL = 1882, X86_OUTSW = 1883, X86_PABSBrm = 1884, X86_PABSBrr = 1885, X86_PABSDrm = 1886, X86_PABSDrr = 1887, X86_PABSWrm = 1888, X86_PABSWrr = 1889, X86_PACKSSDWrm = 1890, X86_PACKSSDWrr = 1891, X86_PACKSSWBrm = 1892, X86_PACKSSWBrr = 1893, X86_PACKUSDWrm = 1894, X86_PACKUSDWrr = 1895, X86_PACKUSWBrm = 1896, X86_PACKUSWBrr = 1897, X86_PADDBrm = 1898, X86_PADDBrr = 1899, X86_PADDDrm = 1900, X86_PADDDrr = 1901, X86_PADDQrm = 1902, X86_PADDQrr = 1903, X86_PADDSBrm = 1904, X86_PADDSBrr = 1905, X86_PADDSWrm = 1906, X86_PADDSWrr = 1907, X86_PADDUSBrm = 1908, X86_PADDUSBrr = 1909, X86_PADDUSWrm = 1910, X86_PADDUSWrr = 1911, X86_PADDWrm = 1912, X86_PADDWrr = 1913, X86_PALIGNRrmi = 1914, X86_PALIGNRrri = 1915, X86_PANDNrm = 1916, X86_PANDNrr = 1917, X86_PANDrm = 1918, X86_PANDrr = 1919, X86_PAUSE = 1920, X86_PAVGBrm = 1921, X86_PAVGBrr = 1922, X86_PAVGUSBrm = 1923, X86_PAVGUSBrr = 1924, X86_PAVGWrm = 1925, X86_PAVGWrr = 1926, X86_PBLENDVBrm0 = 1927, X86_PBLENDVBrr0 = 1928, X86_PBLENDWrmi = 1929, X86_PBLENDWrri = 1930, X86_PCLMULQDQrm = 1931, X86_PCLMULQDQrr = 1932, X86_PCMPEQBrm = 1933, X86_PCMPEQBrr = 1934, X86_PCMPEQDrm = 1935, X86_PCMPEQDrr = 1936, X86_PCMPEQQrm = 1937, X86_PCMPEQQrr = 1938, X86_PCMPEQWrm = 1939, X86_PCMPEQWrr = 1940, X86_PCMPESTRIrm = 1941, X86_PCMPESTRIrr = 1942, X86_PCMPESTRMrm = 1943, X86_PCMPESTRMrr = 1944, X86_PCMPGTBrm = 1945, X86_PCMPGTBrr = 1946, X86_PCMPGTDrm = 1947, X86_PCMPGTDrr = 1948, X86_PCMPGTQrm = 1949, X86_PCMPGTQrr = 1950, X86_PCMPGTWrm = 1951, X86_PCMPGTWrr = 1952, X86_PCMPISTRIrm = 1953, X86_PCMPISTRIrr = 1954, X86_PCMPISTRMrm = 1955, X86_PCMPISTRMrr = 1956, X86_PCONFIG = 1957, X86_PDEP32rm = 1958, X86_PDEP32rr = 1959, X86_PDEP64rm = 1960, X86_PDEP64rr = 1961, X86_PEXT32rm = 1962, X86_PEXT32rr = 1963, X86_PEXT64rm = 1964, X86_PEXT64rr = 1965, X86_PEXTRBmr = 1966, X86_PEXTRBrr = 1967, X86_PEXTRDmr = 1968, X86_PEXTRDrr = 1969, X86_PEXTRQmr = 1970, X86_PEXTRQrr = 1971, X86_PEXTRWmr = 1972, X86_PEXTRWrr = 1973, X86_PEXTRWrr_REV = 1974, X86_PF2IDrm = 1975, X86_PF2IDrr = 1976, X86_PF2IWrm = 1977, X86_PF2IWrr = 1978, X86_PFACCrm = 1979, X86_PFACCrr = 1980, X86_PFADDrm = 1981, X86_PFADDrr = 1982, X86_PFCMPEQrm = 1983, X86_PFCMPEQrr = 1984, X86_PFCMPGErm = 1985, X86_PFCMPGErr = 1986, X86_PFCMPGTrm = 1987, X86_PFCMPGTrr = 1988, X86_PFMAXrm = 1989, X86_PFMAXrr = 1990, X86_PFMINrm = 1991, X86_PFMINrr = 1992, X86_PFMULrm = 1993, X86_PFMULrr = 1994, X86_PFNACCrm = 1995, X86_PFNACCrr = 1996, X86_PFPNACCrm = 1997, X86_PFPNACCrr = 1998, X86_PFRCPIT1rm = 1999, X86_PFRCPIT1rr = 2000, X86_PFRCPIT2rm = 2001, X86_PFRCPIT2rr = 2002, X86_PFRCPrm = 2003, X86_PFRCPrr = 2004, X86_PFRSQIT1rm = 2005, X86_PFRSQIT1rr = 2006, X86_PFRSQRTrm = 2007, X86_PFRSQRTrr = 2008, X86_PFSUBRrm = 2009, X86_PFSUBRrr = 2010, X86_PFSUBrm = 2011, X86_PFSUBrr = 2012, X86_PHADDDrm = 2013, X86_PHADDDrr = 2014, X86_PHADDSWrm = 2015, X86_PHADDSWrr = 2016, X86_PHADDWrm = 2017, X86_PHADDWrr = 2018, X86_PHMINPOSUWrm = 2019, X86_PHMINPOSUWrr = 2020, X86_PHSUBDrm = 2021, X86_PHSUBDrr = 2022, X86_PHSUBSWrm = 2023, X86_PHSUBSWrr = 2024, X86_PHSUBWrm = 2025, X86_PHSUBWrr = 2026, X86_PI2FDrm = 2027, X86_PI2FDrr = 2028, X86_PI2FWrm = 2029, X86_PI2FWrr = 2030, X86_PINSRBrm = 2031, X86_PINSRBrr = 2032, X86_PINSRDrm = 2033, X86_PINSRDrr = 2034, X86_PINSRQrm = 2035, X86_PINSRQrr = 2036, X86_PINSRWrm = 2037, X86_PINSRWrr = 2038, X86_PMADDUBSWrm = 2039, X86_PMADDUBSWrr = 2040, X86_PMADDWDrm = 2041, X86_PMADDWDrr = 2042, X86_PMAXSBrm = 2043, X86_PMAXSBrr = 2044, X86_PMAXSDrm = 2045, X86_PMAXSDrr = 2046, X86_PMAXSWrm = 2047, X86_PMAXSWrr = 2048, X86_PMAXUBrm = 2049, X86_PMAXUBrr = 2050, X86_PMAXUDrm = 2051, X86_PMAXUDrr = 2052, X86_PMAXUWrm = 2053, X86_PMAXUWrr = 2054, X86_PMINSBrm = 2055, X86_PMINSBrr = 2056, X86_PMINSDrm = 2057, X86_PMINSDrr = 2058, X86_PMINSWrm = 2059, X86_PMINSWrr = 2060, X86_PMINUBrm = 2061, X86_PMINUBrr = 2062, X86_PMINUDrm = 2063, X86_PMINUDrr = 2064, X86_PMINUWrm = 2065, X86_PMINUWrr = 2066, X86_PMOVMSKBrr = 2067, X86_PMOVSXBDrm = 2068, X86_PMOVSXBDrr = 2069, X86_PMOVSXBQrm = 2070, X86_PMOVSXBQrr = 2071, X86_PMOVSXBWrm = 2072, X86_PMOVSXBWrr = 2073, X86_PMOVSXDQrm = 2074, X86_PMOVSXDQrr = 2075, X86_PMOVSXWDrm = 2076, X86_PMOVSXWDrr = 2077, X86_PMOVSXWQrm = 2078, X86_PMOVSXWQrr = 2079, X86_PMOVZXBDrm = 2080, X86_PMOVZXBDrr = 2081, X86_PMOVZXBQrm = 2082, X86_PMOVZXBQrr = 2083, X86_PMOVZXBWrm = 2084, X86_PMOVZXBWrr = 2085, X86_PMOVZXDQrm = 2086, X86_PMOVZXDQrr = 2087, X86_PMOVZXWDrm = 2088, X86_PMOVZXWDrr = 2089, X86_PMOVZXWQrm = 2090, X86_PMOVZXWQrr = 2091, X86_PMULDQrm = 2092, X86_PMULDQrr = 2093, X86_PMULHRSWrm = 2094, X86_PMULHRSWrr = 2095, X86_PMULHRWrm = 2096, X86_PMULHRWrr = 2097, X86_PMULHUWrm = 2098, X86_PMULHUWrr = 2099, X86_PMULHWrm = 2100, X86_PMULHWrr = 2101, X86_PMULLDrm = 2102, X86_PMULLDrr = 2103, X86_PMULLWrm = 2104, X86_PMULLWrr = 2105, X86_PMULUDQrm = 2106, X86_PMULUDQrr = 2107, X86_POP16r = 2108, X86_POP16rmm = 2109, X86_POP16rmr = 2110, X86_POP32r = 2111, X86_POP32rmm = 2112, X86_POP32rmr = 2113, X86_POP64r = 2114, X86_POP64rmm = 2115, X86_POP64rmr = 2116, X86_POPA16 = 2117, X86_POPA32 = 2118, X86_POPCNT16rm = 2119, X86_POPCNT16rr = 2120, X86_POPCNT32rm = 2121, X86_POPCNT32rr = 2122, X86_POPCNT64rm = 2123, X86_POPCNT64rr = 2124, X86_POPDS16 = 2125, X86_POPDS32 = 2126, X86_POPES16 = 2127, X86_POPES32 = 2128, X86_POPF16 = 2129, X86_POPF32 = 2130, X86_POPF64 = 2131, X86_POPFS16 = 2132, X86_POPFS32 = 2133, X86_POPFS64 = 2134, X86_POPGS16 = 2135, X86_POPGS32 = 2136, X86_POPGS64 = 2137, X86_POPSS16 = 2138, X86_POPSS32 = 2139, X86_PORrm = 2140, X86_PORrr = 2141, X86_PREFETCH = 2142, X86_PREFETCHNTA = 2143, X86_PREFETCHT0 = 2144, X86_PREFETCHT1 = 2145, X86_PREFETCHT2 = 2146, X86_PREFETCHW = 2147, X86_PREFETCHWT1 = 2148, X86_PSADBWrm = 2149, X86_PSADBWrr = 2150, X86_PSHUFBrm = 2151, X86_PSHUFBrr = 2152, X86_PSHUFDmi = 2153, X86_PSHUFDri = 2154, X86_PSHUFHWmi = 2155, X86_PSHUFHWri = 2156, X86_PSHUFLWmi = 2157, X86_PSHUFLWri = 2158, X86_PSIGNBrm = 2159, X86_PSIGNBrr = 2160, X86_PSIGNDrm = 2161, X86_PSIGNDrr = 2162, X86_PSIGNWrm = 2163, X86_PSIGNWrr = 2164, X86_PSLLDQri = 2165, X86_PSLLDri = 2166, X86_PSLLDrm = 2167, X86_PSLLDrr = 2168, X86_PSLLQri = 2169, X86_PSLLQrm = 2170, X86_PSLLQrr = 2171, X86_PSLLWri = 2172, X86_PSLLWrm = 2173, X86_PSLLWrr = 2174, X86_PSRADri = 2175, X86_PSRADrm = 2176, X86_PSRADrr = 2177, X86_PSRAWri = 2178, X86_PSRAWrm = 2179, X86_PSRAWrr = 2180, X86_PSRLDQri = 2181, X86_PSRLDri = 2182, X86_PSRLDrm = 2183, X86_PSRLDrr = 2184, X86_PSRLQri = 2185, X86_PSRLQrm = 2186, X86_PSRLQrr = 2187, X86_PSRLWri = 2188, X86_PSRLWrm = 2189, X86_PSRLWrr = 2190, X86_PSUBBrm = 2191, X86_PSUBBrr = 2192, X86_PSUBDrm = 2193, X86_PSUBDrr = 2194, X86_PSUBQrm = 2195, X86_PSUBQrr = 2196, X86_PSUBSBrm = 2197, X86_PSUBSBrr = 2198, X86_PSUBSWrm = 2199, X86_PSUBSWrr = 2200, X86_PSUBUSBrm = 2201, X86_PSUBUSBrr = 2202, X86_PSUBUSWrm = 2203, X86_PSUBUSWrr = 2204, X86_PSUBWrm = 2205, X86_PSUBWrr = 2206, X86_PSWAPDrm = 2207, X86_PSWAPDrr = 2208, X86_PTESTrm = 2209, X86_PTESTrr = 2210, X86_PTWRITE64m = 2211, X86_PTWRITE64r = 2212, X86_PTWRITEm = 2213, X86_PTWRITEr = 2214, X86_PUNPCKHBWrm = 2215, X86_PUNPCKHBWrr = 2216, X86_PUNPCKHDQrm = 2217, X86_PUNPCKHDQrr = 2218, X86_PUNPCKHQDQrm = 2219, X86_PUNPCKHQDQrr = 2220, X86_PUNPCKHWDrm = 2221, X86_PUNPCKHWDrr = 2222, X86_PUNPCKLBWrm = 2223, X86_PUNPCKLBWrr = 2224, X86_PUNPCKLDQrm = 2225, X86_PUNPCKLDQrr = 2226, X86_PUNPCKLQDQrm = 2227, X86_PUNPCKLQDQrr = 2228, X86_PUNPCKLWDrm = 2229, X86_PUNPCKLWDrr = 2230, X86_PUSH16i8 = 2231, X86_PUSH16r = 2232, X86_PUSH16rmm = 2233, X86_PUSH16rmr = 2234, X86_PUSH32i8 = 2235, X86_PUSH32r = 2236, X86_PUSH32rmm = 2237, X86_PUSH32rmr = 2238, X86_PUSH64i32 = 2239, X86_PUSH64i8 = 2240, X86_PUSH64r = 2241, X86_PUSH64rmm = 2242, X86_PUSH64rmr = 2243, X86_PUSHA16 = 2244, X86_PUSHA32 = 2245, X86_PUSHCS16 = 2246, X86_PUSHCS32 = 2247, X86_PUSHDS16 = 2248, X86_PUSHDS32 = 2249, X86_PUSHES16 = 2250, X86_PUSHES32 = 2251, X86_PUSHF16 = 2252, X86_PUSHF32 = 2253, X86_PUSHF64 = 2254, X86_PUSHFS16 = 2255, X86_PUSHFS32 = 2256, X86_PUSHFS64 = 2257, X86_PUSHGS16 = 2258, X86_PUSHGS32 = 2259, X86_PUSHGS64 = 2260, X86_PUSHSS16 = 2261, X86_PUSHSS32 = 2262, X86_PUSHi16 = 2263, X86_PUSHi32 = 2264, X86_PXORrm = 2265, X86_PXORrr = 2266, X86_RCL16m1 = 2267, X86_RCL16mCL = 2268, X86_RCL16mi = 2269, X86_RCL16r1 = 2270, X86_RCL16rCL = 2271, X86_RCL16ri = 2272, X86_RCL32m1 = 2273, X86_RCL32mCL = 2274, X86_RCL32mi = 2275, X86_RCL32r1 = 2276, X86_RCL32rCL = 2277, X86_RCL32ri = 2278, X86_RCL64m1 = 2279, X86_RCL64mCL = 2280, X86_RCL64mi = 2281, X86_RCL64r1 = 2282, X86_RCL64rCL = 2283, X86_RCL64ri = 2284, X86_RCL8m1 = 2285, X86_RCL8mCL = 2286, X86_RCL8mi = 2287, X86_RCL8r1 = 2288, X86_RCL8rCL = 2289, X86_RCL8ri = 2290, X86_RCPPSm = 2291, X86_RCPPSr = 2292, X86_RCPSSm = 2293, X86_RCPSSm_Int = 2294, X86_RCPSSr = 2295, X86_RCPSSr_Int = 2296, X86_RCR16m1 = 2297, X86_RCR16mCL = 2298, X86_RCR16mi = 2299, X86_RCR16r1 = 2300, X86_RCR16rCL = 2301, X86_RCR16ri = 2302, X86_RCR32m1 = 2303, X86_RCR32mCL = 2304, X86_RCR32mi = 2305, X86_RCR32r1 = 2306, X86_RCR32rCL = 2307, X86_RCR32ri = 2308, X86_RCR64m1 = 2309, X86_RCR64mCL = 2310, X86_RCR64mi = 2311, X86_RCR64r1 = 2312, X86_RCR64rCL = 2313, X86_RCR64ri = 2314, X86_RCR8m1 = 2315, X86_RCR8mCL = 2316, X86_RCR8mi = 2317, X86_RCR8r1 = 2318, X86_RCR8rCL = 2319, X86_RCR8ri = 2320, X86_RDFSBASE = 2321, X86_RDFSBASE64 = 2322, X86_RDGSBASE = 2323, X86_RDGSBASE64 = 2324, X86_RDMSR = 2325, X86_RDPID32 = 2326, X86_RDPID64 = 2327, X86_RDPKRUr = 2328, X86_RDPMC = 2329, X86_RDRAND16r = 2330, X86_RDRAND32r = 2331, X86_RDRAND64r = 2332, X86_RDSEED16r = 2333, X86_RDSEED32r = 2334, X86_RDSEED64r = 2335, X86_RDSSPD = 2336, X86_RDSSPQ = 2337, X86_RDTSC = 2338, X86_RDTSCP = 2339, X86_REPNE_PREFIX = 2340, X86_REP_PREFIX = 2341, X86_RETIL = 2342, X86_RETIQ = 2343, X86_RETIW = 2344, X86_RETL = 2345, X86_RETQ = 2346, X86_RETW = 2347, X86_REX64_PREFIX = 2348, X86_ROL16m1 = 2349, X86_ROL16mCL = 2350, X86_ROL16mi = 2351, X86_ROL16r1 = 2352, X86_ROL16rCL = 2353, X86_ROL16ri = 2354, X86_ROL32m1 = 2355, X86_ROL32mCL = 2356, X86_ROL32mi = 2357, X86_ROL32r1 = 2358, X86_ROL32rCL = 2359, X86_ROL32ri = 2360, X86_ROL64m1 = 2361, X86_ROL64mCL = 2362, X86_ROL64mi = 2363, X86_ROL64r1 = 2364, X86_ROL64rCL = 2365, X86_ROL64ri = 2366, X86_ROL8m1 = 2367, X86_ROL8mCL = 2368, X86_ROL8mi = 2369, X86_ROL8r1 = 2370, X86_ROL8rCL = 2371, X86_ROL8ri = 2372, X86_ROR16m1 = 2373, X86_ROR16mCL = 2374, X86_ROR16mi = 2375, X86_ROR16r1 = 2376, X86_ROR16rCL = 2377, X86_ROR16ri = 2378, X86_ROR32m1 = 2379, X86_ROR32mCL = 2380, X86_ROR32mi = 2381, X86_ROR32r1 = 2382, X86_ROR32rCL = 2383, X86_ROR32ri = 2384, X86_ROR64m1 = 2385, X86_ROR64mCL = 2386, X86_ROR64mi = 2387, X86_ROR64r1 = 2388, X86_ROR64rCL = 2389, X86_ROR64ri = 2390, X86_ROR8m1 = 2391, X86_ROR8mCL = 2392, X86_ROR8mi = 2393, X86_ROR8r1 = 2394, X86_ROR8rCL = 2395, X86_ROR8ri = 2396, X86_RORX32mi = 2397, X86_RORX32ri = 2398, X86_RORX64mi = 2399, X86_RORX64ri = 2400, X86_ROUNDPDm = 2401, X86_ROUNDPDr = 2402, X86_ROUNDPSm = 2403, X86_ROUNDPSr = 2404, X86_ROUNDSDm = 2405, X86_ROUNDSDm_Int = 2406, X86_ROUNDSDr = 2407, X86_ROUNDSDr_Int = 2408, X86_ROUNDSSm = 2409, X86_ROUNDSSm_Int = 2410, X86_ROUNDSSr = 2411, X86_ROUNDSSr_Int = 2412, X86_RSM = 2413, X86_RSQRTPSm = 2414, X86_RSQRTPSr = 2415, X86_RSQRTSSm = 2416, X86_RSQRTSSm_Int = 2417, X86_RSQRTSSr = 2418, X86_RSQRTSSr_Int = 2419, X86_RSTORSSP = 2420, X86_SAHF = 2421, X86_SAL16m1 = 2422, X86_SAL16mCL = 2423, X86_SAL16mi = 2424, X86_SAL16r1 = 2425, X86_SAL16rCL = 2426, X86_SAL16ri = 2427, X86_SAL32m1 = 2428, X86_SAL32mCL = 2429, X86_SAL32mi = 2430, X86_SAL32r1 = 2431, X86_SAL32rCL = 2432, X86_SAL32ri = 2433, X86_SAL64m1 = 2434, X86_SAL64mCL = 2435, X86_SAL64mi = 2436, X86_SAL64r1 = 2437, X86_SAL64rCL = 2438, X86_SAL64ri = 2439, X86_SAL8m1 = 2440, X86_SAL8mCL = 2441, X86_SAL8mi = 2442, X86_SAL8r1 = 2443, X86_SAL8rCL = 2444, X86_SAL8ri = 2445, X86_SALC = 2446, X86_SAR16m1 = 2447, X86_SAR16mCL = 2448, X86_SAR16mi = 2449, X86_SAR16r1 = 2450, X86_SAR16rCL = 2451, X86_SAR16ri = 2452, X86_SAR32m1 = 2453, X86_SAR32mCL = 2454, X86_SAR32mi = 2455, X86_SAR32r1 = 2456, X86_SAR32rCL = 2457, X86_SAR32ri = 2458, X86_SAR64m1 = 2459, X86_SAR64mCL = 2460, X86_SAR64mi = 2461, X86_SAR64r1 = 2462, X86_SAR64rCL = 2463, X86_SAR64ri = 2464, X86_SAR8m1 = 2465, X86_SAR8mCL = 2466, X86_SAR8mi = 2467, X86_SAR8r1 = 2468, X86_SAR8rCL = 2469, X86_SAR8ri = 2470, X86_SARX32rm = 2471, X86_SARX32rr = 2472, X86_SARX64rm = 2473, X86_SARX64rr = 2474, X86_SAVEPREVSSP = 2475, X86_SBB16i16 = 2476, X86_SBB16mi = 2477, X86_SBB16mi8 = 2478, X86_SBB16mr = 2479, X86_SBB16ri = 2480, X86_SBB16ri8 = 2481, X86_SBB16rm = 2482, X86_SBB16rr = 2483, X86_SBB16rr_REV = 2484, X86_SBB32i32 = 2485, X86_SBB32mi = 2486, X86_SBB32mi8 = 2487, X86_SBB32mr = 2488, X86_SBB32ri = 2489, X86_SBB32ri8 = 2490, X86_SBB32rm = 2491, X86_SBB32rr = 2492, X86_SBB32rr_REV = 2493, X86_SBB64i32 = 2494, X86_SBB64mi32 = 2495, X86_SBB64mi8 = 2496, X86_SBB64mr = 2497, X86_SBB64ri32 = 2498, X86_SBB64ri8 = 2499, X86_SBB64rm = 2500, X86_SBB64rr = 2501, X86_SBB64rr_REV = 2502, X86_SBB8i8 = 2503, X86_SBB8mi = 2504, X86_SBB8mi8 = 2505, X86_SBB8mr = 2506, X86_SBB8ri = 2507, X86_SBB8ri8 = 2508, X86_SBB8rm = 2509, X86_SBB8rr = 2510, X86_SBB8rr_REV = 2511, X86_SCASB = 2512, X86_SCASL = 2513, X86_SCASQ = 2514, X86_SCASW = 2515, X86_SETAEm = 2516, X86_SETAEr = 2517, X86_SETAm = 2518, X86_SETAr = 2519, X86_SETBEm = 2520, X86_SETBEr = 2521, X86_SETBm = 2522, X86_SETBr = 2523, X86_SETEm = 2524, X86_SETEr = 2525, X86_SETGEm = 2526, X86_SETGEr = 2527, X86_SETGm = 2528, X86_SETGr = 2529, X86_SETLEm = 2530, X86_SETLEr = 2531, X86_SETLm = 2532, X86_SETLr = 2533, X86_SETNEm = 2534, X86_SETNEr = 2535, X86_SETNOm = 2536, X86_SETNOr = 2537, X86_SETNPm = 2538, X86_SETNPr = 2539, X86_SETNSm = 2540, X86_SETNSr = 2541, X86_SETOm = 2542, X86_SETOr = 2543, X86_SETPm = 2544, X86_SETPr = 2545, X86_SETSSBSY = 2546, X86_SETSm = 2547, X86_SETSr = 2548, X86_SFENCE = 2549, X86_SGDT16m = 2550, X86_SGDT32m = 2551, X86_SGDT64m = 2552, X86_SHA1MSG1rm = 2553, X86_SHA1MSG1rr = 2554, X86_SHA1MSG2rm = 2555, X86_SHA1MSG2rr = 2556, X86_SHA1NEXTErm = 2557, X86_SHA1NEXTErr = 2558, X86_SHA1RNDS4rmi = 2559, X86_SHA1RNDS4rri = 2560, X86_SHA256MSG1rm = 2561, X86_SHA256MSG1rr = 2562, X86_SHA256MSG2rm = 2563, X86_SHA256MSG2rr = 2564, X86_SHA256RNDS2rm = 2565, X86_SHA256RNDS2rr = 2566, X86_SHL16m1 = 2567, X86_SHL16mCL = 2568, X86_SHL16mi = 2569, X86_SHL16r1 = 2570, X86_SHL16rCL = 2571, X86_SHL16ri = 2572, X86_SHL32m1 = 2573, X86_SHL32mCL = 2574, X86_SHL32mi = 2575, X86_SHL32r1 = 2576, X86_SHL32rCL = 2577, X86_SHL32ri = 2578, X86_SHL64m1 = 2579, X86_SHL64mCL = 2580, X86_SHL64mi = 2581, X86_SHL64r1 = 2582, X86_SHL64rCL = 2583, X86_SHL64ri = 2584, X86_SHL8m1 = 2585, X86_SHL8mCL = 2586, X86_SHL8mi = 2587, X86_SHL8r1 = 2588, X86_SHL8rCL = 2589, X86_SHL8ri = 2590, X86_SHLD16mrCL = 2591, X86_SHLD16mri8 = 2592, X86_SHLD16rrCL = 2593, X86_SHLD16rri8 = 2594, X86_SHLD32mrCL = 2595, X86_SHLD32mri8 = 2596, X86_SHLD32rrCL = 2597, X86_SHLD32rri8 = 2598, X86_SHLD64mrCL = 2599, X86_SHLD64mri8 = 2600, X86_SHLD64rrCL = 2601, X86_SHLD64rri8 = 2602, X86_SHLX32rm = 2603, X86_SHLX32rr = 2604, X86_SHLX64rm = 2605, X86_SHLX64rr = 2606, X86_SHR16m1 = 2607, X86_SHR16mCL = 2608, X86_SHR16mi = 2609, X86_SHR16r1 = 2610, X86_SHR16rCL = 2611, X86_SHR16ri = 2612, X86_SHR32m1 = 2613, X86_SHR32mCL = 2614, X86_SHR32mi = 2615, X86_SHR32r1 = 2616, X86_SHR32rCL = 2617, X86_SHR32ri = 2618, X86_SHR64m1 = 2619, X86_SHR64mCL = 2620, X86_SHR64mi = 2621, X86_SHR64r1 = 2622, X86_SHR64rCL = 2623, X86_SHR64ri = 2624, X86_SHR8m1 = 2625, X86_SHR8mCL = 2626, X86_SHR8mi = 2627, X86_SHR8r1 = 2628, X86_SHR8rCL = 2629, X86_SHR8ri = 2630, X86_SHRD16mrCL = 2631, X86_SHRD16mri8 = 2632, X86_SHRD16rrCL = 2633, X86_SHRD16rri8 = 2634, X86_SHRD32mrCL = 2635, X86_SHRD32mri8 = 2636, X86_SHRD32rrCL = 2637, X86_SHRD32rri8 = 2638, X86_SHRD64mrCL = 2639, X86_SHRD64mri8 = 2640, X86_SHRD64rrCL = 2641, X86_SHRD64rri8 = 2642, X86_SHRX32rm = 2643, X86_SHRX32rr = 2644, X86_SHRX64rm = 2645, X86_SHRX64rr = 2646, X86_SHUFPDrmi = 2647, X86_SHUFPDrri = 2648, X86_SHUFPSrmi = 2649, X86_SHUFPSrri = 2650, X86_SIDT16m = 2651, X86_SIDT32m = 2652, X86_SIDT64m = 2653, X86_SIN_F = 2654, X86_SIN_Fp32 = 2655, X86_SIN_Fp64 = 2656, X86_SIN_Fp80 = 2657, X86_SKINIT = 2658, X86_SLDT16m = 2659, X86_SLDT16r = 2660, X86_SLDT32r = 2661, X86_SLDT64r = 2662, X86_SLWPCB = 2663, X86_SLWPCB64 = 2664, X86_SMSW16m = 2665, X86_SMSW16r = 2666, X86_SMSW32r = 2667, X86_SMSW64r = 2668, X86_SQRTPDm = 2669, X86_SQRTPDr = 2670, X86_SQRTPSm = 2671, X86_SQRTPSr = 2672, X86_SQRTSDm = 2673, X86_SQRTSDm_Int = 2674, X86_SQRTSDr = 2675, X86_SQRTSDr_Int = 2676, X86_SQRTSSm = 2677, X86_SQRTSSm_Int = 2678, X86_SQRTSSr = 2679, X86_SQRTSSr_Int = 2680, X86_SQRT_F = 2681, X86_SQRT_Fp32 = 2682, X86_SQRT_Fp64 = 2683, X86_SQRT_Fp80 = 2684, X86_STAC = 2685, X86_STC = 2686, X86_STD = 2687, X86_STGI = 2688, X86_STI = 2689, X86_STMXCSR = 2690, X86_STOSB = 2691, X86_STOSL = 2692, X86_STOSQ = 2693, X86_STOSW = 2694, X86_STR16r = 2695, X86_STR32r = 2696, X86_STR64r = 2697, X86_STRm = 2698, X86_ST_F32m = 2699, X86_ST_F64m = 2700, X86_ST_FP32m = 2701, X86_ST_FP64m = 2702, X86_ST_FP80m = 2703, X86_ST_FPrr = 2704, X86_ST_Fp32m = 2705, X86_ST_Fp64m = 2706, X86_ST_Fp64m32 = 2707, X86_ST_Fp80m32 = 2708, X86_ST_Fp80m64 = 2709, X86_ST_FpP32m = 2710, X86_ST_FpP64m = 2711, X86_ST_FpP64m32 = 2712, X86_ST_FpP80m = 2713, X86_ST_FpP80m32 = 2714, X86_ST_FpP80m64 = 2715, X86_ST_Frr = 2716, X86_SUB16i16 = 2717, X86_SUB16mi = 2718, X86_SUB16mi8 = 2719, X86_SUB16mr = 2720, X86_SUB16ri = 2721, X86_SUB16ri8 = 2722, X86_SUB16rm = 2723, X86_SUB16rr = 2724, X86_SUB16rr_REV = 2725, X86_SUB32i32 = 2726, X86_SUB32mi = 2727, X86_SUB32mi8 = 2728, X86_SUB32mr = 2729, X86_SUB32ri = 2730, X86_SUB32ri8 = 2731, X86_SUB32rm = 2732, X86_SUB32rr = 2733, X86_SUB32rr_REV = 2734, X86_SUB64i32 = 2735, X86_SUB64mi32 = 2736, X86_SUB64mi8 = 2737, X86_SUB64mr = 2738, X86_SUB64ri32 = 2739, X86_SUB64ri8 = 2740, X86_SUB64rm = 2741, X86_SUB64rr = 2742, X86_SUB64rr_REV = 2743, X86_SUB8i8 = 2744, X86_SUB8mi = 2745, X86_SUB8mi8 = 2746, X86_SUB8mr = 2747, X86_SUB8ri = 2748, X86_SUB8ri8 = 2749, X86_SUB8rm = 2750, X86_SUB8rr = 2751, X86_SUB8rr_REV = 2752, X86_SUBPDrm = 2753, X86_SUBPDrr = 2754, X86_SUBPSrm = 2755, X86_SUBPSrr = 2756, X86_SUBR_F32m = 2757, X86_SUBR_F64m = 2758, X86_SUBR_FI16m = 2759, X86_SUBR_FI32m = 2760, X86_SUBR_FPrST0 = 2761, X86_SUBR_FST0r = 2762, X86_SUBR_Fp32m = 2763, X86_SUBR_Fp64m = 2764, X86_SUBR_Fp64m32 = 2765, X86_SUBR_Fp80m32 = 2766, X86_SUBR_Fp80m64 = 2767, X86_SUBR_FpI16m32 = 2768, X86_SUBR_FpI16m64 = 2769, X86_SUBR_FpI16m80 = 2770, X86_SUBR_FpI32m32 = 2771, X86_SUBR_FpI32m64 = 2772, X86_SUBR_FpI32m80 = 2773, X86_SUBR_FrST0 = 2774, X86_SUBSDrm = 2775, X86_SUBSDrm_Int = 2776, X86_SUBSDrr = 2777, X86_SUBSDrr_Int = 2778, X86_SUBSSrm = 2779, X86_SUBSSrm_Int = 2780, X86_SUBSSrr = 2781, X86_SUBSSrr_Int = 2782, X86_SUB_F32m = 2783, X86_SUB_F64m = 2784, X86_SUB_FI16m = 2785, X86_SUB_FI32m = 2786, X86_SUB_FPrST0 = 2787, X86_SUB_FST0r = 2788, X86_SUB_Fp32 = 2789, X86_SUB_Fp32m = 2790, X86_SUB_Fp64 = 2791, X86_SUB_Fp64m = 2792, X86_SUB_Fp64m32 = 2793, X86_SUB_Fp80 = 2794, X86_SUB_Fp80m32 = 2795, X86_SUB_Fp80m64 = 2796, X86_SUB_FpI16m32 = 2797, X86_SUB_FpI16m64 = 2798, X86_SUB_FpI16m80 = 2799, X86_SUB_FpI32m32 = 2800, X86_SUB_FpI32m64 = 2801, X86_SUB_FpI32m80 = 2802, X86_SUB_FrST0 = 2803, X86_SWAPGS = 2804, X86_SYSCALL = 2805, X86_SYSENTER = 2806, X86_SYSEXIT = 2807, X86_SYSEXIT64 = 2808, X86_SYSRET = 2809, X86_SYSRET64 = 2810, X86_T1MSKC32rm = 2811, X86_T1MSKC32rr = 2812, X86_T1MSKC64rm = 2813, X86_T1MSKC64rr = 2814, X86_TEST16i16 = 2815, X86_TEST16mi = 2816, X86_TEST16mi_alt = 2817, X86_TEST16mr = 2818, X86_TEST16ri = 2819, X86_TEST16ri_alt = 2820, X86_TEST16rr = 2821, X86_TEST32i32 = 2822, X86_TEST32mi = 2823, X86_TEST32mi_alt = 2824, X86_TEST32mr = 2825, X86_TEST32ri = 2826, X86_TEST32ri_alt = 2827, X86_TEST32rr = 2828, X86_TEST64i32 = 2829, X86_TEST64mi32 = 2830, X86_TEST64mi32_alt = 2831, X86_TEST64mr = 2832, X86_TEST64ri32 = 2833, X86_TEST64ri32_alt = 2834, X86_TEST64rr = 2835, X86_TEST8i8 = 2836, X86_TEST8mi = 2837, X86_TEST8mi_alt = 2838, X86_TEST8mr = 2839, X86_TEST8ri = 2840, X86_TEST8ri_alt = 2841, X86_TEST8rr = 2842, X86_TPAUSE = 2843, X86_TST_F = 2844, X86_TST_Fp32 = 2845, X86_TST_Fp64 = 2846, X86_TST_Fp80 = 2847, X86_TZCNT16rm = 2848, X86_TZCNT16rr = 2849, X86_TZCNT32rm = 2850, X86_TZCNT32rr = 2851, X86_TZCNT64rm = 2852, X86_TZCNT64rr = 2853, X86_TZMSK32rm = 2854, X86_TZMSK32rr = 2855, X86_TZMSK64rm = 2856, X86_TZMSK64rr = 2857, X86_UCOMISDrm = 2858, X86_UCOMISDrm_Int = 2859, X86_UCOMISDrr = 2860, X86_UCOMISDrr_Int = 2861, X86_UCOMISSrm = 2862, X86_UCOMISSrm_Int = 2863, X86_UCOMISSrr = 2864, X86_UCOMISSrr_Int = 2865, X86_UCOM_FIPr = 2866, X86_UCOM_FIr = 2867, X86_UCOM_FPPr = 2868, X86_UCOM_FPr = 2869, X86_UCOM_FpIr32 = 2870, X86_UCOM_FpIr64 = 2871, X86_UCOM_FpIr80 = 2872, X86_UCOM_Fpr32 = 2873, X86_UCOM_Fpr64 = 2874, X86_UCOM_Fpr80 = 2875, X86_UCOM_Fr = 2876, X86_UD0 = 2877, X86_UD1 = 2878, X86_UD2 = 2879, X86_UMONITOR16 = 2880, X86_UMONITOR32 = 2881, X86_UMONITOR64 = 2882, X86_UMWAIT = 2883, X86_UNPCKHPDrm = 2884, X86_UNPCKHPDrr = 2885, X86_UNPCKHPSrm = 2886, X86_UNPCKHPSrr = 2887, X86_UNPCKLPDrm = 2888, X86_UNPCKLPDrr = 2889, X86_UNPCKLPSrm = 2890, X86_UNPCKLPSrr = 2891, X86_V4FMADDPSrm = 2892, X86_V4FMADDPSrmk = 2893, X86_V4FMADDPSrmkz = 2894, X86_V4FMADDSSrm = 2895, X86_V4FMADDSSrmk = 2896, X86_V4FMADDSSrmkz = 2897, X86_V4FNMADDPSrm = 2898, X86_V4FNMADDPSrmk = 2899, X86_V4FNMADDPSrmkz = 2900, X86_V4FNMADDSSrm = 2901, X86_V4FNMADDSSrmk = 2902, X86_V4FNMADDSSrmkz = 2903, X86_VADDPDYrm = 2904, X86_VADDPDYrr = 2905, X86_VADDPDZ128rm = 2906, X86_VADDPDZ128rmb = 2907, X86_VADDPDZ128rmbk = 2908, X86_VADDPDZ128rmbkz = 2909, X86_VADDPDZ128rmk = 2910, X86_VADDPDZ128rmkz = 2911, X86_VADDPDZ128rr = 2912, X86_VADDPDZ128rrk = 2913, X86_VADDPDZ128rrkz = 2914, X86_VADDPDZ256rm = 2915, X86_VADDPDZ256rmb = 2916, X86_VADDPDZ256rmbk = 2917, X86_VADDPDZ256rmbkz = 2918, X86_VADDPDZ256rmk = 2919, X86_VADDPDZ256rmkz = 2920, X86_VADDPDZ256rr = 2921, X86_VADDPDZ256rrk = 2922, X86_VADDPDZ256rrkz = 2923, X86_VADDPDZrm = 2924, X86_VADDPDZrmb = 2925, X86_VADDPDZrmbk = 2926, X86_VADDPDZrmbkz = 2927, X86_VADDPDZrmk = 2928, X86_VADDPDZrmkz = 2929, X86_VADDPDZrr = 2930, X86_VADDPDZrrb = 2931, X86_VADDPDZrrbk = 2932, X86_VADDPDZrrbkz = 2933, X86_VADDPDZrrk = 2934, X86_VADDPDZrrkz = 2935, X86_VADDPDrm = 2936, X86_VADDPDrr = 2937, X86_VADDPSYrm = 2938, X86_VADDPSYrr = 2939, X86_VADDPSZ128rm = 2940, X86_VADDPSZ128rmb = 2941, X86_VADDPSZ128rmbk = 2942, X86_VADDPSZ128rmbkz = 2943, X86_VADDPSZ128rmk = 2944, X86_VADDPSZ128rmkz = 2945, X86_VADDPSZ128rr = 2946, X86_VADDPSZ128rrk = 2947, X86_VADDPSZ128rrkz = 2948, X86_VADDPSZ256rm = 2949, X86_VADDPSZ256rmb = 2950, X86_VADDPSZ256rmbk = 2951, X86_VADDPSZ256rmbkz = 2952, X86_VADDPSZ256rmk = 2953, X86_VADDPSZ256rmkz = 2954, X86_VADDPSZ256rr = 2955, X86_VADDPSZ256rrk = 2956, X86_VADDPSZ256rrkz = 2957, X86_VADDPSZrm = 2958, X86_VADDPSZrmb = 2959, X86_VADDPSZrmbk = 2960, X86_VADDPSZrmbkz = 2961, X86_VADDPSZrmk = 2962, X86_VADDPSZrmkz = 2963, X86_VADDPSZrr = 2964, X86_VADDPSZrrb = 2965, X86_VADDPSZrrbk = 2966, X86_VADDPSZrrbkz = 2967, X86_VADDPSZrrk = 2968, X86_VADDPSZrrkz = 2969, X86_VADDPSrm = 2970, X86_VADDPSrr = 2971, X86_VADDSDZrm = 2972, X86_VADDSDZrm_Int = 2973, X86_VADDSDZrm_Intk = 2974, X86_VADDSDZrm_Intkz = 2975, X86_VADDSDZrr = 2976, X86_VADDSDZrr_Int = 2977, X86_VADDSDZrr_Intk = 2978, X86_VADDSDZrr_Intkz = 2979, X86_VADDSDZrrb_Int = 2980, X86_VADDSDZrrb_Intk = 2981, X86_VADDSDZrrb_Intkz = 2982, X86_VADDSDrm = 2983, X86_VADDSDrm_Int = 2984, X86_VADDSDrr = 2985, X86_VADDSDrr_Int = 2986, X86_VADDSSZrm = 2987, X86_VADDSSZrm_Int = 2988, X86_VADDSSZrm_Intk = 2989, X86_VADDSSZrm_Intkz = 2990, X86_VADDSSZrr = 2991, X86_VADDSSZrr_Int = 2992, X86_VADDSSZrr_Intk = 2993, X86_VADDSSZrr_Intkz = 2994, X86_VADDSSZrrb_Int = 2995, X86_VADDSSZrrb_Intk = 2996, X86_VADDSSZrrb_Intkz = 2997, X86_VADDSSrm = 2998, X86_VADDSSrm_Int = 2999, X86_VADDSSrr = 3000, X86_VADDSSrr_Int = 3001, X86_VADDSUBPDYrm = 3002, X86_VADDSUBPDYrr = 3003, X86_VADDSUBPDrm = 3004, X86_VADDSUBPDrr = 3005, X86_VADDSUBPSYrm = 3006, X86_VADDSUBPSYrr = 3007, X86_VADDSUBPSrm = 3008, X86_VADDSUBPSrr = 3009, X86_VAESDECLASTYrm = 3010, X86_VAESDECLASTYrr = 3011, X86_VAESDECLASTZ128rm = 3012, X86_VAESDECLASTZ128rr = 3013, X86_VAESDECLASTZ256rm = 3014, X86_VAESDECLASTZ256rr = 3015, X86_VAESDECLASTZrm = 3016, X86_VAESDECLASTZrr = 3017, X86_VAESDECLASTrm = 3018, X86_VAESDECLASTrr = 3019, X86_VAESDECYrm = 3020, X86_VAESDECYrr = 3021, X86_VAESDECZ128rm = 3022, X86_VAESDECZ128rr = 3023, X86_VAESDECZ256rm = 3024, X86_VAESDECZ256rr = 3025, X86_VAESDECZrm = 3026, X86_VAESDECZrr = 3027, X86_VAESDECrm = 3028, X86_VAESDECrr = 3029, X86_VAESENCLASTYrm = 3030, X86_VAESENCLASTYrr = 3031, X86_VAESENCLASTZ128rm = 3032, X86_VAESENCLASTZ128rr = 3033, X86_VAESENCLASTZ256rm = 3034, X86_VAESENCLASTZ256rr = 3035, X86_VAESENCLASTZrm = 3036, X86_VAESENCLASTZrr = 3037, X86_VAESENCLASTrm = 3038, X86_VAESENCLASTrr = 3039, X86_VAESENCYrm = 3040, X86_VAESENCYrr = 3041, X86_VAESENCZ128rm = 3042, X86_VAESENCZ128rr = 3043, X86_VAESENCZ256rm = 3044, X86_VAESENCZ256rr = 3045, X86_VAESENCZrm = 3046, X86_VAESENCZrr = 3047, X86_VAESENCrm = 3048, X86_VAESENCrr = 3049, X86_VAESIMCrm = 3050, X86_VAESIMCrr = 3051, X86_VAESKEYGENASSIST128rm = 3052, X86_VAESKEYGENASSIST128rr = 3053, X86_VALIGNDZ128rmbi = 3054, X86_VALIGNDZ128rmbik = 3055, X86_VALIGNDZ128rmbikz = 3056, X86_VALIGNDZ128rmi = 3057, X86_VALIGNDZ128rmik = 3058, X86_VALIGNDZ128rmikz = 3059, X86_VALIGNDZ128rri = 3060, X86_VALIGNDZ128rrik = 3061, X86_VALIGNDZ128rrikz = 3062, X86_VALIGNDZ256rmbi = 3063, X86_VALIGNDZ256rmbik = 3064, X86_VALIGNDZ256rmbikz = 3065, X86_VALIGNDZ256rmi = 3066, X86_VALIGNDZ256rmik = 3067, X86_VALIGNDZ256rmikz = 3068, X86_VALIGNDZ256rri = 3069, X86_VALIGNDZ256rrik = 3070, X86_VALIGNDZ256rrikz = 3071, X86_VALIGNDZrmbi = 3072, X86_VALIGNDZrmbik = 3073, X86_VALIGNDZrmbikz = 3074, X86_VALIGNDZrmi = 3075, X86_VALIGNDZrmik = 3076, X86_VALIGNDZrmikz = 3077, X86_VALIGNDZrri = 3078, X86_VALIGNDZrrik = 3079, X86_VALIGNDZrrikz = 3080, X86_VALIGNQZ128rmbi = 3081, X86_VALIGNQZ128rmbik = 3082, X86_VALIGNQZ128rmbikz = 3083, X86_VALIGNQZ128rmi = 3084, X86_VALIGNQZ128rmik = 3085, X86_VALIGNQZ128rmikz = 3086, X86_VALIGNQZ128rri = 3087, X86_VALIGNQZ128rrik = 3088, X86_VALIGNQZ128rrikz = 3089, X86_VALIGNQZ256rmbi = 3090, X86_VALIGNQZ256rmbik = 3091, X86_VALIGNQZ256rmbikz = 3092, X86_VALIGNQZ256rmi = 3093, X86_VALIGNQZ256rmik = 3094, X86_VALIGNQZ256rmikz = 3095, X86_VALIGNQZ256rri = 3096, X86_VALIGNQZ256rrik = 3097, X86_VALIGNQZ256rrikz = 3098, X86_VALIGNQZrmbi = 3099, X86_VALIGNQZrmbik = 3100, X86_VALIGNQZrmbikz = 3101, X86_VALIGNQZrmi = 3102, X86_VALIGNQZrmik = 3103, X86_VALIGNQZrmikz = 3104, X86_VALIGNQZrri = 3105, X86_VALIGNQZrrik = 3106, X86_VALIGNQZrrikz = 3107, X86_VANDNPDYrm = 3108, X86_VANDNPDYrr = 3109, X86_VANDNPDZ128rm = 3110, X86_VANDNPDZ128rmb = 3111, X86_VANDNPDZ128rmbk = 3112, X86_VANDNPDZ128rmbkz = 3113, X86_VANDNPDZ128rmk = 3114, X86_VANDNPDZ128rmkz = 3115, X86_VANDNPDZ128rr = 3116, X86_VANDNPDZ128rrk = 3117, X86_VANDNPDZ128rrkz = 3118, X86_VANDNPDZ256rm = 3119, X86_VANDNPDZ256rmb = 3120, X86_VANDNPDZ256rmbk = 3121, X86_VANDNPDZ256rmbkz = 3122, X86_VANDNPDZ256rmk = 3123, X86_VANDNPDZ256rmkz = 3124, X86_VANDNPDZ256rr = 3125, X86_VANDNPDZ256rrk = 3126, X86_VANDNPDZ256rrkz = 3127, X86_VANDNPDZrm = 3128, X86_VANDNPDZrmb = 3129, X86_VANDNPDZrmbk = 3130, X86_VANDNPDZrmbkz = 3131, X86_VANDNPDZrmk = 3132, X86_VANDNPDZrmkz = 3133, X86_VANDNPDZrr = 3134, X86_VANDNPDZrrk = 3135, X86_VANDNPDZrrkz = 3136, X86_VANDNPDrm = 3137, X86_VANDNPDrr = 3138, X86_VANDNPSYrm = 3139, X86_VANDNPSYrr = 3140, X86_VANDNPSZ128rm = 3141, X86_VANDNPSZ128rmb = 3142, X86_VANDNPSZ128rmbk = 3143, X86_VANDNPSZ128rmbkz = 3144, X86_VANDNPSZ128rmk = 3145, X86_VANDNPSZ128rmkz = 3146, X86_VANDNPSZ128rr = 3147, X86_VANDNPSZ128rrk = 3148, X86_VANDNPSZ128rrkz = 3149, X86_VANDNPSZ256rm = 3150, X86_VANDNPSZ256rmb = 3151, X86_VANDNPSZ256rmbk = 3152, X86_VANDNPSZ256rmbkz = 3153, X86_VANDNPSZ256rmk = 3154, X86_VANDNPSZ256rmkz = 3155, X86_VANDNPSZ256rr = 3156, X86_VANDNPSZ256rrk = 3157, X86_VANDNPSZ256rrkz = 3158, X86_VANDNPSZrm = 3159, X86_VANDNPSZrmb = 3160, X86_VANDNPSZrmbk = 3161, X86_VANDNPSZrmbkz = 3162, X86_VANDNPSZrmk = 3163, X86_VANDNPSZrmkz = 3164, X86_VANDNPSZrr = 3165, X86_VANDNPSZrrk = 3166, X86_VANDNPSZrrkz = 3167, X86_VANDNPSrm = 3168, X86_VANDNPSrr = 3169, X86_VANDPDYrm = 3170, X86_VANDPDYrr = 3171, X86_VANDPDZ128rm = 3172, X86_VANDPDZ128rmb = 3173, X86_VANDPDZ128rmbk = 3174, X86_VANDPDZ128rmbkz = 3175, X86_VANDPDZ128rmk = 3176, X86_VANDPDZ128rmkz = 3177, X86_VANDPDZ128rr = 3178, X86_VANDPDZ128rrk = 3179, X86_VANDPDZ128rrkz = 3180, X86_VANDPDZ256rm = 3181, X86_VANDPDZ256rmb = 3182, X86_VANDPDZ256rmbk = 3183, X86_VANDPDZ256rmbkz = 3184, X86_VANDPDZ256rmk = 3185, X86_VANDPDZ256rmkz = 3186, X86_VANDPDZ256rr = 3187, X86_VANDPDZ256rrk = 3188, X86_VANDPDZ256rrkz = 3189, X86_VANDPDZrm = 3190, X86_VANDPDZrmb = 3191, X86_VANDPDZrmbk = 3192, X86_VANDPDZrmbkz = 3193, X86_VANDPDZrmk = 3194, X86_VANDPDZrmkz = 3195, X86_VANDPDZrr = 3196, X86_VANDPDZrrk = 3197, X86_VANDPDZrrkz = 3198, X86_VANDPDrm = 3199, X86_VANDPDrr = 3200, X86_VANDPSYrm = 3201, X86_VANDPSYrr = 3202, X86_VANDPSZ128rm = 3203, X86_VANDPSZ128rmb = 3204, X86_VANDPSZ128rmbk = 3205, X86_VANDPSZ128rmbkz = 3206, X86_VANDPSZ128rmk = 3207, X86_VANDPSZ128rmkz = 3208, X86_VANDPSZ128rr = 3209, X86_VANDPSZ128rrk = 3210, X86_VANDPSZ128rrkz = 3211, X86_VANDPSZ256rm = 3212, X86_VANDPSZ256rmb = 3213, X86_VANDPSZ256rmbk = 3214, X86_VANDPSZ256rmbkz = 3215, X86_VANDPSZ256rmk = 3216, X86_VANDPSZ256rmkz = 3217, X86_VANDPSZ256rr = 3218, X86_VANDPSZ256rrk = 3219, X86_VANDPSZ256rrkz = 3220, X86_VANDPSZrm = 3221, X86_VANDPSZrmb = 3222, X86_VANDPSZrmbk = 3223, X86_VANDPSZrmbkz = 3224, X86_VANDPSZrmk = 3225, X86_VANDPSZrmkz = 3226, X86_VANDPSZrr = 3227, X86_VANDPSZrrk = 3228, X86_VANDPSZrrkz = 3229, X86_VANDPSrm = 3230, X86_VANDPSrr = 3231, X86_VBLENDMPDZ128rm = 3232, X86_VBLENDMPDZ128rmb = 3233, X86_VBLENDMPDZ128rmbk = 3234, X86_VBLENDMPDZ128rmbkz = 3235, X86_VBLENDMPDZ128rmk = 3236, X86_VBLENDMPDZ128rmkz = 3237, X86_VBLENDMPDZ128rr = 3238, X86_VBLENDMPDZ128rrk = 3239, X86_VBLENDMPDZ128rrkz = 3240, X86_VBLENDMPDZ256rm = 3241, X86_VBLENDMPDZ256rmb = 3242, X86_VBLENDMPDZ256rmbk = 3243, X86_VBLENDMPDZ256rmbkz = 3244, X86_VBLENDMPDZ256rmk = 3245, X86_VBLENDMPDZ256rmkz = 3246, X86_VBLENDMPDZ256rr = 3247, X86_VBLENDMPDZ256rrk = 3248, X86_VBLENDMPDZ256rrkz = 3249, X86_VBLENDMPDZrm = 3250, X86_VBLENDMPDZrmb = 3251, X86_VBLENDMPDZrmbk = 3252, X86_VBLENDMPDZrmbkz = 3253, X86_VBLENDMPDZrmk = 3254, X86_VBLENDMPDZrmkz = 3255, X86_VBLENDMPDZrr = 3256, X86_VBLENDMPDZrrk = 3257, X86_VBLENDMPDZrrkz = 3258, X86_VBLENDMPSZ128rm = 3259, X86_VBLENDMPSZ128rmb = 3260, X86_VBLENDMPSZ128rmbk = 3261, X86_VBLENDMPSZ128rmbkz = 3262, X86_VBLENDMPSZ128rmk = 3263, X86_VBLENDMPSZ128rmkz = 3264, X86_VBLENDMPSZ128rr = 3265, X86_VBLENDMPSZ128rrk = 3266, X86_VBLENDMPSZ128rrkz = 3267, X86_VBLENDMPSZ256rm = 3268, X86_VBLENDMPSZ256rmb = 3269, X86_VBLENDMPSZ256rmbk = 3270, X86_VBLENDMPSZ256rmbkz = 3271, X86_VBLENDMPSZ256rmk = 3272, X86_VBLENDMPSZ256rmkz = 3273, X86_VBLENDMPSZ256rr = 3274, X86_VBLENDMPSZ256rrk = 3275, X86_VBLENDMPSZ256rrkz = 3276, X86_VBLENDMPSZrm = 3277, X86_VBLENDMPSZrmb = 3278, X86_VBLENDMPSZrmbk = 3279, X86_VBLENDMPSZrmbkz = 3280, X86_VBLENDMPSZrmk = 3281, X86_VBLENDMPSZrmkz = 3282, X86_VBLENDMPSZrr = 3283, X86_VBLENDMPSZrrk = 3284, X86_VBLENDMPSZrrkz = 3285, X86_VBLENDPDYrmi = 3286, X86_VBLENDPDYrri = 3287, X86_VBLENDPDrmi = 3288, X86_VBLENDPDrri = 3289, X86_VBLENDPSYrmi = 3290, X86_VBLENDPSYrri = 3291, X86_VBLENDPSrmi = 3292, X86_VBLENDPSrri = 3293, X86_VBLENDVPDYrm = 3294, X86_VBLENDVPDYrr = 3295, X86_VBLENDVPDrm = 3296, X86_VBLENDVPDrr = 3297, X86_VBLENDVPSYrm = 3298, X86_VBLENDVPSYrr = 3299, X86_VBLENDVPSrm = 3300, X86_VBLENDVPSrr = 3301, X86_VBROADCASTF128 = 3302, X86_VBROADCASTF32X2Z256m = 3303, X86_VBROADCASTF32X2Z256mk = 3304, X86_VBROADCASTF32X2Z256mkz = 3305, X86_VBROADCASTF32X2Z256r = 3306, X86_VBROADCASTF32X2Z256rk = 3307, X86_VBROADCASTF32X2Z256rkz = 3308, X86_VBROADCASTF32X2Zm = 3309, X86_VBROADCASTF32X2Zmk = 3310, X86_VBROADCASTF32X2Zmkz = 3311, X86_VBROADCASTF32X2Zr = 3312, X86_VBROADCASTF32X2Zrk = 3313, X86_VBROADCASTF32X2Zrkz = 3314, X86_VBROADCASTF32X4Z256rm = 3315, X86_VBROADCASTF32X4Z256rmk = 3316, X86_VBROADCASTF32X4Z256rmkz = 3317, X86_VBROADCASTF32X4rm = 3318, X86_VBROADCASTF32X4rmk = 3319, X86_VBROADCASTF32X4rmkz = 3320, X86_VBROADCASTF32X8rm = 3321, X86_VBROADCASTF32X8rmk = 3322, X86_VBROADCASTF32X8rmkz = 3323, X86_VBROADCASTF64X2Z128rm = 3324, X86_VBROADCASTF64X2Z128rmk = 3325, X86_VBROADCASTF64X2Z128rmkz = 3326, X86_VBROADCASTF64X2rm = 3327, X86_VBROADCASTF64X2rmk = 3328, X86_VBROADCASTF64X2rmkz = 3329, X86_VBROADCASTF64X4rm = 3330, X86_VBROADCASTF64X4rmk = 3331, X86_VBROADCASTF64X4rmkz = 3332, X86_VBROADCASTI128 = 3333, X86_VBROADCASTI32X2Z128m = 3334, X86_VBROADCASTI32X2Z128mk = 3335, X86_VBROADCASTI32X2Z128mkz = 3336, X86_VBROADCASTI32X2Z128r = 3337, X86_VBROADCASTI32X2Z128rk = 3338, X86_VBROADCASTI32X2Z128rkz = 3339, X86_VBROADCASTI32X2Z256m = 3340, X86_VBROADCASTI32X2Z256mk = 3341, X86_VBROADCASTI32X2Z256mkz = 3342, X86_VBROADCASTI32X2Z256r = 3343, X86_VBROADCASTI32X2Z256rk = 3344, X86_VBROADCASTI32X2Z256rkz = 3345, X86_VBROADCASTI32X2Zm = 3346, X86_VBROADCASTI32X2Zmk = 3347, X86_VBROADCASTI32X2Zmkz = 3348, X86_VBROADCASTI32X2Zr = 3349, X86_VBROADCASTI32X2Zrk = 3350, X86_VBROADCASTI32X2Zrkz = 3351, X86_VBROADCASTI32X4Z256rm = 3352, X86_VBROADCASTI32X4Z256rmk = 3353, X86_VBROADCASTI32X4Z256rmkz = 3354, X86_VBROADCASTI32X4rm = 3355, X86_VBROADCASTI32X4rmk = 3356, X86_VBROADCASTI32X4rmkz = 3357, X86_VBROADCASTI32X8rm = 3358, X86_VBROADCASTI32X8rmk = 3359, X86_VBROADCASTI32X8rmkz = 3360, X86_VBROADCASTI64X2Z128rm = 3361, X86_VBROADCASTI64X2Z128rmk = 3362, X86_VBROADCASTI64X2Z128rmkz = 3363, X86_VBROADCASTI64X2rm = 3364, X86_VBROADCASTI64X2rmk = 3365, X86_VBROADCASTI64X2rmkz = 3366, X86_VBROADCASTI64X4rm = 3367, X86_VBROADCASTI64X4rmk = 3368, X86_VBROADCASTI64X4rmkz = 3369, X86_VBROADCASTSDYrm = 3370, X86_VBROADCASTSDYrr = 3371, X86_VBROADCASTSDZ256m = 3372, X86_VBROADCASTSDZ256mk = 3373, X86_VBROADCASTSDZ256mkz = 3374, X86_VBROADCASTSDZ256r = 3375, X86_VBROADCASTSDZ256rk = 3376, X86_VBROADCASTSDZ256rkz = 3377, X86_VBROADCASTSDZm = 3378, X86_VBROADCASTSDZmk = 3379, X86_VBROADCASTSDZmkz = 3380, X86_VBROADCASTSDZr = 3381, X86_VBROADCASTSDZrk = 3382, X86_VBROADCASTSDZrkz = 3383, X86_VBROADCASTSSYrm = 3384, X86_VBROADCASTSSYrr = 3385, X86_VBROADCASTSSZ128m = 3386, X86_VBROADCASTSSZ128mk = 3387, X86_VBROADCASTSSZ128mkz = 3388, X86_VBROADCASTSSZ128r = 3389, X86_VBROADCASTSSZ128rk = 3390, X86_VBROADCASTSSZ128rkz = 3391, X86_VBROADCASTSSZ256m = 3392, X86_VBROADCASTSSZ256mk = 3393, X86_VBROADCASTSSZ256mkz = 3394, X86_VBROADCASTSSZ256r = 3395, X86_VBROADCASTSSZ256rk = 3396, X86_VBROADCASTSSZ256rkz = 3397, X86_VBROADCASTSSZm = 3398, X86_VBROADCASTSSZmk = 3399, X86_VBROADCASTSSZmkz = 3400, X86_VBROADCASTSSZr = 3401, X86_VBROADCASTSSZrk = 3402, X86_VBROADCASTSSZrkz = 3403, X86_VBROADCASTSSrm = 3404, X86_VBROADCASTSSrr = 3405, X86_VCMPPDYrmi = 3406, X86_VCMPPDYrmi_alt = 3407, X86_VCMPPDYrri = 3408, X86_VCMPPDYrri_alt = 3409, X86_VCMPPDZ128rmbi = 3410, X86_VCMPPDZ128rmbi_alt = 3411, X86_VCMPPDZ128rmbi_altk = 3412, X86_VCMPPDZ128rmbik = 3413, X86_VCMPPDZ128rmi = 3414, X86_VCMPPDZ128rmi_alt = 3415, X86_VCMPPDZ128rmi_altk = 3416, X86_VCMPPDZ128rmik = 3417, X86_VCMPPDZ128rri = 3418, X86_VCMPPDZ128rri_alt = 3419, X86_VCMPPDZ128rri_altk = 3420, X86_VCMPPDZ128rrik = 3421, X86_VCMPPDZ256rmbi = 3422, X86_VCMPPDZ256rmbi_alt = 3423, X86_VCMPPDZ256rmbi_altk = 3424, X86_VCMPPDZ256rmbik = 3425, X86_VCMPPDZ256rmi = 3426, X86_VCMPPDZ256rmi_alt = 3427, X86_VCMPPDZ256rmi_altk = 3428, X86_VCMPPDZ256rmik = 3429, X86_VCMPPDZ256rri = 3430, X86_VCMPPDZ256rri_alt = 3431, X86_VCMPPDZ256rri_altk = 3432, X86_VCMPPDZ256rrik = 3433, X86_VCMPPDZrmbi = 3434, X86_VCMPPDZrmbi_alt = 3435, X86_VCMPPDZrmbi_altk = 3436, X86_VCMPPDZrmbik = 3437, X86_VCMPPDZrmi = 3438, X86_VCMPPDZrmi_alt = 3439, X86_VCMPPDZrmi_altk = 3440, X86_VCMPPDZrmik = 3441, X86_VCMPPDZrri = 3442, X86_VCMPPDZrri_alt = 3443, X86_VCMPPDZrri_altk = 3444, X86_VCMPPDZrrib = 3445, X86_VCMPPDZrrib_alt = 3446, X86_VCMPPDZrrib_altk = 3447, X86_VCMPPDZrribk = 3448, X86_VCMPPDZrrik = 3449, X86_VCMPPDrmi = 3450, X86_VCMPPDrmi_alt = 3451, X86_VCMPPDrri = 3452, X86_VCMPPDrri_alt = 3453, X86_VCMPPSYrmi = 3454, X86_VCMPPSYrmi_alt = 3455, X86_VCMPPSYrri = 3456, X86_VCMPPSYrri_alt = 3457, X86_VCMPPSZ128rmbi = 3458, X86_VCMPPSZ128rmbi_alt = 3459, X86_VCMPPSZ128rmbi_altk = 3460, X86_VCMPPSZ128rmbik = 3461, X86_VCMPPSZ128rmi = 3462, X86_VCMPPSZ128rmi_alt = 3463, X86_VCMPPSZ128rmi_altk = 3464, X86_VCMPPSZ128rmik = 3465, X86_VCMPPSZ128rri = 3466, X86_VCMPPSZ128rri_alt = 3467, X86_VCMPPSZ128rri_altk = 3468, X86_VCMPPSZ128rrik = 3469, X86_VCMPPSZ256rmbi = 3470, X86_VCMPPSZ256rmbi_alt = 3471, X86_VCMPPSZ256rmbi_altk = 3472, X86_VCMPPSZ256rmbik = 3473, X86_VCMPPSZ256rmi = 3474, X86_VCMPPSZ256rmi_alt = 3475, X86_VCMPPSZ256rmi_altk = 3476, X86_VCMPPSZ256rmik = 3477, X86_VCMPPSZ256rri = 3478, X86_VCMPPSZ256rri_alt = 3479, X86_VCMPPSZ256rri_altk = 3480, X86_VCMPPSZ256rrik = 3481, X86_VCMPPSZrmbi = 3482, X86_VCMPPSZrmbi_alt = 3483, X86_VCMPPSZrmbi_altk = 3484, X86_VCMPPSZrmbik = 3485, X86_VCMPPSZrmi = 3486, X86_VCMPPSZrmi_alt = 3487, X86_VCMPPSZrmi_altk = 3488, X86_VCMPPSZrmik = 3489, X86_VCMPPSZrri = 3490, X86_VCMPPSZrri_alt = 3491, X86_VCMPPSZrri_altk = 3492, X86_VCMPPSZrrib = 3493, X86_VCMPPSZrrib_alt = 3494, X86_VCMPPSZrrib_altk = 3495, X86_VCMPPSZrribk = 3496, X86_VCMPPSZrrik = 3497, X86_VCMPPSrmi = 3498, X86_VCMPPSrmi_alt = 3499, X86_VCMPPSrri = 3500, X86_VCMPPSrri_alt = 3501, X86_VCMPSDZrm = 3502, X86_VCMPSDZrm_Int = 3503, X86_VCMPSDZrm_Intk = 3504, X86_VCMPSDZrmi_alt = 3505, X86_VCMPSDZrmi_altk = 3506, X86_VCMPSDZrr = 3507, X86_VCMPSDZrr_Int = 3508, X86_VCMPSDZrr_Intk = 3509, X86_VCMPSDZrrb_Int = 3510, X86_VCMPSDZrrb_Intk = 3511, X86_VCMPSDZrrb_alt = 3512, X86_VCMPSDZrrb_altk = 3513, X86_VCMPSDZrri_alt = 3514, X86_VCMPSDZrri_altk = 3515, X86_VCMPSDrm = 3516, X86_VCMPSDrm_Int = 3517, X86_VCMPSDrm_alt = 3518, X86_VCMPSDrr = 3519, X86_VCMPSDrr_Int = 3520, X86_VCMPSDrr_alt = 3521, X86_VCMPSSZrm = 3522, X86_VCMPSSZrm_Int = 3523, X86_VCMPSSZrm_Intk = 3524, X86_VCMPSSZrmi_alt = 3525, X86_VCMPSSZrmi_altk = 3526, X86_VCMPSSZrr = 3527, X86_VCMPSSZrr_Int = 3528, X86_VCMPSSZrr_Intk = 3529, X86_VCMPSSZrrb_Int = 3530, X86_VCMPSSZrrb_Intk = 3531, X86_VCMPSSZrrb_alt = 3532, X86_VCMPSSZrrb_altk = 3533, X86_VCMPSSZrri_alt = 3534, X86_VCMPSSZrri_altk = 3535, X86_VCMPSSrm = 3536, X86_VCMPSSrm_Int = 3537, X86_VCMPSSrm_alt = 3538, X86_VCMPSSrr = 3539, X86_VCMPSSrr_Int = 3540, X86_VCMPSSrr_alt = 3541, X86_VCOMISDZrm = 3542, X86_VCOMISDZrm_Int = 3543, X86_VCOMISDZrr = 3544, X86_VCOMISDZrr_Int = 3545, X86_VCOMISDZrrb = 3546, X86_VCOMISDrm = 3547, X86_VCOMISDrm_Int = 3548, X86_VCOMISDrr = 3549, X86_VCOMISDrr_Int = 3550, X86_VCOMISSZrm = 3551, X86_VCOMISSZrm_Int = 3552, X86_VCOMISSZrr = 3553, X86_VCOMISSZrr_Int = 3554, X86_VCOMISSZrrb = 3555, X86_VCOMISSrm = 3556, X86_VCOMISSrm_Int = 3557, X86_VCOMISSrr = 3558, X86_VCOMISSrr_Int = 3559, X86_VCOMPRESSPDZ128mr = 3560, X86_VCOMPRESSPDZ128mrk = 3561, X86_VCOMPRESSPDZ128rr = 3562, X86_VCOMPRESSPDZ128rrk = 3563, X86_VCOMPRESSPDZ128rrkz = 3564, X86_VCOMPRESSPDZ256mr = 3565, X86_VCOMPRESSPDZ256mrk = 3566, X86_VCOMPRESSPDZ256rr = 3567, X86_VCOMPRESSPDZ256rrk = 3568, X86_VCOMPRESSPDZ256rrkz = 3569, X86_VCOMPRESSPDZmr = 3570, X86_VCOMPRESSPDZmrk = 3571, X86_VCOMPRESSPDZrr = 3572, X86_VCOMPRESSPDZrrk = 3573, X86_VCOMPRESSPDZrrkz = 3574, X86_VCOMPRESSPSZ128mr = 3575, X86_VCOMPRESSPSZ128mrk = 3576, X86_VCOMPRESSPSZ128rr = 3577, X86_VCOMPRESSPSZ128rrk = 3578, X86_VCOMPRESSPSZ128rrkz = 3579, X86_VCOMPRESSPSZ256mr = 3580, X86_VCOMPRESSPSZ256mrk = 3581, X86_VCOMPRESSPSZ256rr = 3582, X86_VCOMPRESSPSZ256rrk = 3583, X86_VCOMPRESSPSZ256rrkz = 3584, X86_VCOMPRESSPSZmr = 3585, X86_VCOMPRESSPSZmrk = 3586, X86_VCOMPRESSPSZrr = 3587, X86_VCOMPRESSPSZrrk = 3588, X86_VCOMPRESSPSZrrkz = 3589, X86_VCVTDQ2PDYrm = 3590, X86_VCVTDQ2PDYrr = 3591, X86_VCVTDQ2PDZ128rm = 3592, X86_VCVTDQ2PDZ128rmb = 3593, X86_VCVTDQ2PDZ128rmbk = 3594, X86_VCVTDQ2PDZ128rmbkz = 3595, X86_VCVTDQ2PDZ128rmk = 3596, X86_VCVTDQ2PDZ128rmkz = 3597, X86_VCVTDQ2PDZ128rr = 3598, X86_VCVTDQ2PDZ128rrk = 3599, X86_VCVTDQ2PDZ128rrkz = 3600, X86_VCVTDQ2PDZ256rm = 3601, X86_VCVTDQ2PDZ256rmb = 3602, X86_VCVTDQ2PDZ256rmbk = 3603, X86_VCVTDQ2PDZ256rmbkz = 3604, X86_VCVTDQ2PDZ256rmk = 3605, X86_VCVTDQ2PDZ256rmkz = 3606, X86_VCVTDQ2PDZ256rr = 3607, X86_VCVTDQ2PDZ256rrk = 3608, X86_VCVTDQ2PDZ256rrkz = 3609, X86_VCVTDQ2PDZrm = 3610, X86_VCVTDQ2PDZrmb = 3611, X86_VCVTDQ2PDZrmbk = 3612, X86_VCVTDQ2PDZrmbkz = 3613, X86_VCVTDQ2PDZrmk = 3614, X86_VCVTDQ2PDZrmkz = 3615, X86_VCVTDQ2PDZrr = 3616, X86_VCVTDQ2PDZrrk = 3617, X86_VCVTDQ2PDZrrkz = 3618, X86_VCVTDQ2PDrm = 3619, X86_VCVTDQ2PDrr = 3620, X86_VCVTDQ2PSYrm = 3621, X86_VCVTDQ2PSYrr = 3622, X86_VCVTDQ2PSZ128rm = 3623, X86_VCVTDQ2PSZ128rmb = 3624, X86_VCVTDQ2PSZ128rmbk = 3625, X86_VCVTDQ2PSZ128rmbkz = 3626, X86_VCVTDQ2PSZ128rmk = 3627, X86_VCVTDQ2PSZ128rmkz = 3628, X86_VCVTDQ2PSZ128rr = 3629, X86_VCVTDQ2PSZ128rrk = 3630, X86_VCVTDQ2PSZ128rrkz = 3631, X86_VCVTDQ2PSZ256rm = 3632, X86_VCVTDQ2PSZ256rmb = 3633, X86_VCVTDQ2PSZ256rmbk = 3634, X86_VCVTDQ2PSZ256rmbkz = 3635, X86_VCVTDQ2PSZ256rmk = 3636, X86_VCVTDQ2PSZ256rmkz = 3637, X86_VCVTDQ2PSZ256rr = 3638, X86_VCVTDQ2PSZ256rrk = 3639, X86_VCVTDQ2PSZ256rrkz = 3640, X86_VCVTDQ2PSZrm = 3641, X86_VCVTDQ2PSZrmb = 3642, X86_VCVTDQ2PSZrmbk = 3643, X86_VCVTDQ2PSZrmbkz = 3644, X86_VCVTDQ2PSZrmk = 3645, X86_VCVTDQ2PSZrmkz = 3646, X86_VCVTDQ2PSZrr = 3647, X86_VCVTDQ2PSZrrb = 3648, X86_VCVTDQ2PSZrrbk = 3649, X86_VCVTDQ2PSZrrbkz = 3650, X86_VCVTDQ2PSZrrk = 3651, X86_VCVTDQ2PSZrrkz = 3652, X86_VCVTDQ2PSrm = 3653, X86_VCVTDQ2PSrr = 3654, X86_VCVTPD2DQYrm = 3655, X86_VCVTPD2DQYrr = 3656, X86_VCVTPD2DQZ128rm = 3657, X86_VCVTPD2DQZ128rmb = 3658, X86_VCVTPD2DQZ128rmbk = 3659, X86_VCVTPD2DQZ128rmbkz = 3660, X86_VCVTPD2DQZ128rmk = 3661, X86_VCVTPD2DQZ128rmkz = 3662, X86_VCVTPD2DQZ128rr = 3663, X86_VCVTPD2DQZ128rrk = 3664, X86_VCVTPD2DQZ128rrkz = 3665, X86_VCVTPD2DQZ256rm = 3666, X86_VCVTPD2DQZ256rmb = 3667, X86_VCVTPD2DQZ256rmbk = 3668, X86_VCVTPD2DQZ256rmbkz = 3669, X86_VCVTPD2DQZ256rmk = 3670, X86_VCVTPD2DQZ256rmkz = 3671, X86_VCVTPD2DQZ256rr = 3672, X86_VCVTPD2DQZ256rrk = 3673, X86_VCVTPD2DQZ256rrkz = 3674, X86_VCVTPD2DQZrm = 3675, X86_VCVTPD2DQZrmb = 3676, X86_VCVTPD2DQZrmbk = 3677, X86_VCVTPD2DQZrmbkz = 3678, X86_VCVTPD2DQZrmk = 3679, X86_VCVTPD2DQZrmkz = 3680, X86_VCVTPD2DQZrr = 3681, X86_VCVTPD2DQZrrb = 3682, X86_VCVTPD2DQZrrbk = 3683, X86_VCVTPD2DQZrrbkz = 3684, X86_VCVTPD2DQZrrk = 3685, X86_VCVTPD2DQZrrkz = 3686, X86_VCVTPD2DQrm = 3687, X86_VCVTPD2DQrr = 3688, X86_VCVTPD2PSYrm = 3689, X86_VCVTPD2PSYrr = 3690, X86_VCVTPD2PSZ128rm = 3691, X86_VCVTPD2PSZ128rmb = 3692, X86_VCVTPD2PSZ128rmbk = 3693, X86_VCVTPD2PSZ128rmbkz = 3694, X86_VCVTPD2PSZ128rmk = 3695, X86_VCVTPD2PSZ128rmkz = 3696, X86_VCVTPD2PSZ128rr = 3697, X86_VCVTPD2PSZ128rrk = 3698, X86_VCVTPD2PSZ128rrkz = 3699, X86_VCVTPD2PSZ256rm = 3700, X86_VCVTPD2PSZ256rmb = 3701, X86_VCVTPD2PSZ256rmbk = 3702, X86_VCVTPD2PSZ256rmbkz = 3703, X86_VCVTPD2PSZ256rmk = 3704, X86_VCVTPD2PSZ256rmkz = 3705, X86_VCVTPD2PSZ256rr = 3706, X86_VCVTPD2PSZ256rrk = 3707, X86_VCVTPD2PSZ256rrkz = 3708, X86_VCVTPD2PSZrm = 3709, X86_VCVTPD2PSZrmb = 3710, X86_VCVTPD2PSZrmbk = 3711, X86_VCVTPD2PSZrmbkz = 3712, X86_VCVTPD2PSZrmk = 3713, X86_VCVTPD2PSZrmkz = 3714, X86_VCVTPD2PSZrr = 3715, X86_VCVTPD2PSZrrb = 3716, X86_VCVTPD2PSZrrbk = 3717, X86_VCVTPD2PSZrrbkz = 3718, X86_VCVTPD2PSZrrk = 3719, X86_VCVTPD2PSZrrkz = 3720, X86_VCVTPD2PSrm = 3721, X86_VCVTPD2PSrr = 3722, X86_VCVTPD2QQZ128rm = 3723, X86_VCVTPD2QQZ128rmb = 3724, X86_VCVTPD2QQZ128rmbk = 3725, X86_VCVTPD2QQZ128rmbkz = 3726, X86_VCVTPD2QQZ128rmk = 3727, X86_VCVTPD2QQZ128rmkz = 3728, X86_VCVTPD2QQZ128rr = 3729, X86_VCVTPD2QQZ128rrk = 3730, X86_VCVTPD2QQZ128rrkz = 3731, X86_VCVTPD2QQZ256rm = 3732, X86_VCVTPD2QQZ256rmb = 3733, X86_VCVTPD2QQZ256rmbk = 3734, X86_VCVTPD2QQZ256rmbkz = 3735, X86_VCVTPD2QQZ256rmk = 3736, X86_VCVTPD2QQZ256rmkz = 3737, X86_VCVTPD2QQZ256rr = 3738, X86_VCVTPD2QQZ256rrk = 3739, X86_VCVTPD2QQZ256rrkz = 3740, X86_VCVTPD2QQZrm = 3741, X86_VCVTPD2QQZrmb = 3742, X86_VCVTPD2QQZrmbk = 3743, X86_VCVTPD2QQZrmbkz = 3744, X86_VCVTPD2QQZrmk = 3745, X86_VCVTPD2QQZrmkz = 3746, X86_VCVTPD2QQZrr = 3747, X86_VCVTPD2QQZrrb = 3748, X86_VCVTPD2QQZrrbk = 3749, X86_VCVTPD2QQZrrbkz = 3750, X86_VCVTPD2QQZrrk = 3751, X86_VCVTPD2QQZrrkz = 3752, X86_VCVTPD2UDQZ128rm = 3753, X86_VCVTPD2UDQZ128rmb = 3754, X86_VCVTPD2UDQZ128rmbk = 3755, X86_VCVTPD2UDQZ128rmbkz = 3756, X86_VCVTPD2UDQZ128rmk = 3757, X86_VCVTPD2UDQZ128rmkz = 3758, X86_VCVTPD2UDQZ128rr = 3759, X86_VCVTPD2UDQZ128rrk = 3760, X86_VCVTPD2UDQZ128rrkz = 3761, X86_VCVTPD2UDQZ256rm = 3762, X86_VCVTPD2UDQZ256rmb = 3763, X86_VCVTPD2UDQZ256rmbk = 3764, X86_VCVTPD2UDQZ256rmbkz = 3765, X86_VCVTPD2UDQZ256rmk = 3766, X86_VCVTPD2UDQZ256rmkz = 3767, X86_VCVTPD2UDQZ256rr = 3768, X86_VCVTPD2UDQZ256rrk = 3769, X86_VCVTPD2UDQZ256rrkz = 3770, X86_VCVTPD2UDQZrm = 3771, X86_VCVTPD2UDQZrmb = 3772, X86_VCVTPD2UDQZrmbk = 3773, X86_VCVTPD2UDQZrmbkz = 3774, X86_VCVTPD2UDQZrmk = 3775, X86_VCVTPD2UDQZrmkz = 3776, X86_VCVTPD2UDQZrr = 3777, X86_VCVTPD2UDQZrrb = 3778, X86_VCVTPD2UDQZrrbk = 3779, X86_VCVTPD2UDQZrrbkz = 3780, X86_VCVTPD2UDQZrrk = 3781, X86_VCVTPD2UDQZrrkz = 3782, X86_VCVTPD2UQQZ128rm = 3783, X86_VCVTPD2UQQZ128rmb = 3784, X86_VCVTPD2UQQZ128rmbk = 3785, X86_VCVTPD2UQQZ128rmbkz = 3786, X86_VCVTPD2UQQZ128rmk = 3787, X86_VCVTPD2UQQZ128rmkz = 3788, X86_VCVTPD2UQQZ128rr = 3789, X86_VCVTPD2UQQZ128rrk = 3790, X86_VCVTPD2UQQZ128rrkz = 3791, X86_VCVTPD2UQQZ256rm = 3792, X86_VCVTPD2UQQZ256rmb = 3793, X86_VCVTPD2UQQZ256rmbk = 3794, X86_VCVTPD2UQQZ256rmbkz = 3795, X86_VCVTPD2UQQZ256rmk = 3796, X86_VCVTPD2UQQZ256rmkz = 3797, X86_VCVTPD2UQQZ256rr = 3798, X86_VCVTPD2UQQZ256rrk = 3799, X86_VCVTPD2UQQZ256rrkz = 3800, X86_VCVTPD2UQQZrm = 3801, X86_VCVTPD2UQQZrmb = 3802, X86_VCVTPD2UQQZrmbk = 3803, X86_VCVTPD2UQQZrmbkz = 3804, X86_VCVTPD2UQQZrmk = 3805, X86_VCVTPD2UQQZrmkz = 3806, X86_VCVTPD2UQQZrr = 3807, X86_VCVTPD2UQQZrrb = 3808, X86_VCVTPD2UQQZrrbk = 3809, X86_VCVTPD2UQQZrrbkz = 3810, X86_VCVTPD2UQQZrrk = 3811, X86_VCVTPD2UQQZrrkz = 3812, X86_VCVTPH2PSYrm = 3813, X86_VCVTPH2PSYrr = 3814, X86_VCVTPH2PSZ128rm = 3815, X86_VCVTPH2PSZ128rmk = 3816, X86_VCVTPH2PSZ128rmkz = 3817, X86_VCVTPH2PSZ128rr = 3818, X86_VCVTPH2PSZ128rrk = 3819, X86_VCVTPH2PSZ128rrkz = 3820, X86_VCVTPH2PSZ256rm = 3821, X86_VCVTPH2PSZ256rmk = 3822, X86_VCVTPH2PSZ256rmkz = 3823, X86_VCVTPH2PSZ256rr = 3824, X86_VCVTPH2PSZ256rrk = 3825, X86_VCVTPH2PSZ256rrkz = 3826, X86_VCVTPH2PSZrm = 3827, X86_VCVTPH2PSZrmk = 3828, X86_VCVTPH2PSZrmkz = 3829, X86_VCVTPH2PSZrr = 3830, X86_VCVTPH2PSZrrb = 3831, X86_VCVTPH2PSZrrbk = 3832, X86_VCVTPH2PSZrrbkz = 3833, X86_VCVTPH2PSZrrk = 3834, X86_VCVTPH2PSZrrkz = 3835, X86_VCVTPH2PSrm = 3836, X86_VCVTPH2PSrr = 3837, X86_VCVTPS2DQYrm = 3838, X86_VCVTPS2DQYrr = 3839, X86_VCVTPS2DQZ128rm = 3840, X86_VCVTPS2DQZ128rmb = 3841, X86_VCVTPS2DQZ128rmbk = 3842, X86_VCVTPS2DQZ128rmbkz = 3843, X86_VCVTPS2DQZ128rmk = 3844, X86_VCVTPS2DQZ128rmkz = 3845, X86_VCVTPS2DQZ128rr = 3846, X86_VCVTPS2DQZ128rrk = 3847, X86_VCVTPS2DQZ128rrkz = 3848, X86_VCVTPS2DQZ256rm = 3849, X86_VCVTPS2DQZ256rmb = 3850, X86_VCVTPS2DQZ256rmbk = 3851, X86_VCVTPS2DQZ256rmbkz = 3852, X86_VCVTPS2DQZ256rmk = 3853, X86_VCVTPS2DQZ256rmkz = 3854, X86_VCVTPS2DQZ256rr = 3855, X86_VCVTPS2DQZ256rrk = 3856, X86_VCVTPS2DQZ256rrkz = 3857, X86_VCVTPS2DQZrm = 3858, X86_VCVTPS2DQZrmb = 3859, X86_VCVTPS2DQZrmbk = 3860, X86_VCVTPS2DQZrmbkz = 3861, X86_VCVTPS2DQZrmk = 3862, X86_VCVTPS2DQZrmkz = 3863, X86_VCVTPS2DQZrr = 3864, X86_VCVTPS2DQZrrb = 3865, X86_VCVTPS2DQZrrbk = 3866, X86_VCVTPS2DQZrrbkz = 3867, X86_VCVTPS2DQZrrk = 3868, X86_VCVTPS2DQZrrkz = 3869, X86_VCVTPS2DQrm = 3870, X86_VCVTPS2DQrr = 3871, X86_VCVTPS2PDYrm = 3872, X86_VCVTPS2PDYrr = 3873, X86_VCVTPS2PDZ128rm = 3874, X86_VCVTPS2PDZ128rmb = 3875, X86_VCVTPS2PDZ128rmbk = 3876, X86_VCVTPS2PDZ128rmbkz = 3877, X86_VCVTPS2PDZ128rmk = 3878, X86_VCVTPS2PDZ128rmkz = 3879, X86_VCVTPS2PDZ128rr = 3880, X86_VCVTPS2PDZ128rrk = 3881, X86_VCVTPS2PDZ128rrkz = 3882, X86_VCVTPS2PDZ256rm = 3883, X86_VCVTPS2PDZ256rmb = 3884, X86_VCVTPS2PDZ256rmbk = 3885, X86_VCVTPS2PDZ256rmbkz = 3886, X86_VCVTPS2PDZ256rmk = 3887, X86_VCVTPS2PDZ256rmkz = 3888, X86_VCVTPS2PDZ256rr = 3889, X86_VCVTPS2PDZ256rrk = 3890, X86_VCVTPS2PDZ256rrkz = 3891, X86_VCVTPS2PDZrm = 3892, X86_VCVTPS2PDZrmb = 3893, X86_VCVTPS2PDZrmbk = 3894, X86_VCVTPS2PDZrmbkz = 3895, X86_VCVTPS2PDZrmk = 3896, X86_VCVTPS2PDZrmkz = 3897, X86_VCVTPS2PDZrr = 3898, X86_VCVTPS2PDZrrb = 3899, X86_VCVTPS2PDZrrbk = 3900, X86_VCVTPS2PDZrrbkz = 3901, X86_VCVTPS2PDZrrk = 3902, X86_VCVTPS2PDZrrkz = 3903, X86_VCVTPS2PDrm = 3904, X86_VCVTPS2PDrr = 3905, X86_VCVTPS2PHYmr = 3906, X86_VCVTPS2PHYrr = 3907, X86_VCVTPS2PHZ128mr = 3908, X86_VCVTPS2PHZ128mrk = 3909, X86_VCVTPS2PHZ128rr = 3910, X86_VCVTPS2PHZ128rrk = 3911, X86_VCVTPS2PHZ128rrkz = 3912, X86_VCVTPS2PHZ256mr = 3913, X86_VCVTPS2PHZ256mrk = 3914, X86_VCVTPS2PHZ256rr = 3915, X86_VCVTPS2PHZ256rrk = 3916, X86_VCVTPS2PHZ256rrkz = 3917, X86_VCVTPS2PHZmr = 3918, X86_VCVTPS2PHZmrk = 3919, X86_VCVTPS2PHZrr = 3920, X86_VCVTPS2PHZrrb = 3921, X86_VCVTPS2PHZrrbk = 3922, X86_VCVTPS2PHZrrbkz = 3923, X86_VCVTPS2PHZrrk = 3924, X86_VCVTPS2PHZrrkz = 3925, X86_VCVTPS2PHmr = 3926, X86_VCVTPS2PHrr = 3927, X86_VCVTPS2QQZ128rm = 3928, X86_VCVTPS2QQZ128rmb = 3929, X86_VCVTPS2QQZ128rmbk = 3930, X86_VCVTPS2QQZ128rmbkz = 3931, X86_VCVTPS2QQZ128rmk = 3932, X86_VCVTPS2QQZ128rmkz = 3933, X86_VCVTPS2QQZ128rr = 3934, X86_VCVTPS2QQZ128rrk = 3935, X86_VCVTPS2QQZ128rrkz = 3936, X86_VCVTPS2QQZ256rm = 3937, X86_VCVTPS2QQZ256rmb = 3938, X86_VCVTPS2QQZ256rmbk = 3939, X86_VCVTPS2QQZ256rmbkz = 3940, X86_VCVTPS2QQZ256rmk = 3941, X86_VCVTPS2QQZ256rmkz = 3942, X86_VCVTPS2QQZ256rr = 3943, X86_VCVTPS2QQZ256rrk = 3944, X86_VCVTPS2QQZ256rrkz = 3945, X86_VCVTPS2QQZrm = 3946, X86_VCVTPS2QQZrmb = 3947, X86_VCVTPS2QQZrmbk = 3948, X86_VCVTPS2QQZrmbkz = 3949, X86_VCVTPS2QQZrmk = 3950, X86_VCVTPS2QQZrmkz = 3951, X86_VCVTPS2QQZrr = 3952, X86_VCVTPS2QQZrrb = 3953, X86_VCVTPS2QQZrrbk = 3954, X86_VCVTPS2QQZrrbkz = 3955, X86_VCVTPS2QQZrrk = 3956, X86_VCVTPS2QQZrrkz = 3957, X86_VCVTPS2UDQZ128rm = 3958, X86_VCVTPS2UDQZ128rmb = 3959, X86_VCVTPS2UDQZ128rmbk = 3960, X86_VCVTPS2UDQZ128rmbkz = 3961, X86_VCVTPS2UDQZ128rmk = 3962, X86_VCVTPS2UDQZ128rmkz = 3963, X86_VCVTPS2UDQZ128rr = 3964, X86_VCVTPS2UDQZ128rrk = 3965, X86_VCVTPS2UDQZ128rrkz = 3966, X86_VCVTPS2UDQZ256rm = 3967, X86_VCVTPS2UDQZ256rmb = 3968, X86_VCVTPS2UDQZ256rmbk = 3969, X86_VCVTPS2UDQZ256rmbkz = 3970, X86_VCVTPS2UDQZ256rmk = 3971, X86_VCVTPS2UDQZ256rmkz = 3972, X86_VCVTPS2UDQZ256rr = 3973, X86_VCVTPS2UDQZ256rrk = 3974, X86_VCVTPS2UDQZ256rrkz = 3975, X86_VCVTPS2UDQZrm = 3976, X86_VCVTPS2UDQZrmb = 3977, X86_VCVTPS2UDQZrmbk = 3978, X86_VCVTPS2UDQZrmbkz = 3979, X86_VCVTPS2UDQZrmk = 3980, X86_VCVTPS2UDQZrmkz = 3981, X86_VCVTPS2UDQZrr = 3982, X86_VCVTPS2UDQZrrb = 3983, X86_VCVTPS2UDQZrrbk = 3984, X86_VCVTPS2UDQZrrbkz = 3985, X86_VCVTPS2UDQZrrk = 3986, X86_VCVTPS2UDQZrrkz = 3987, X86_VCVTPS2UQQZ128rm = 3988, X86_VCVTPS2UQQZ128rmb = 3989, X86_VCVTPS2UQQZ128rmbk = 3990, X86_VCVTPS2UQQZ128rmbkz = 3991, X86_VCVTPS2UQQZ128rmk = 3992, X86_VCVTPS2UQQZ128rmkz = 3993, X86_VCVTPS2UQQZ128rr = 3994, X86_VCVTPS2UQQZ128rrk = 3995, X86_VCVTPS2UQQZ128rrkz = 3996, X86_VCVTPS2UQQZ256rm = 3997, X86_VCVTPS2UQQZ256rmb = 3998, X86_VCVTPS2UQQZ256rmbk = 3999, X86_VCVTPS2UQQZ256rmbkz = 4000, X86_VCVTPS2UQQZ256rmk = 4001, X86_VCVTPS2UQQZ256rmkz = 4002, X86_VCVTPS2UQQZ256rr = 4003, X86_VCVTPS2UQQZ256rrk = 4004, X86_VCVTPS2UQQZ256rrkz = 4005, X86_VCVTPS2UQQZrm = 4006, X86_VCVTPS2UQQZrmb = 4007, X86_VCVTPS2UQQZrmbk = 4008, X86_VCVTPS2UQQZrmbkz = 4009, X86_VCVTPS2UQQZrmk = 4010, X86_VCVTPS2UQQZrmkz = 4011, X86_VCVTPS2UQQZrr = 4012, X86_VCVTPS2UQQZrrb = 4013, X86_VCVTPS2UQQZrrbk = 4014, X86_VCVTPS2UQQZrrbkz = 4015, X86_VCVTPS2UQQZrrk = 4016, X86_VCVTPS2UQQZrrkz = 4017, X86_VCVTQQ2PDZ128rm = 4018, X86_VCVTQQ2PDZ128rmb = 4019, X86_VCVTQQ2PDZ128rmbk = 4020, X86_VCVTQQ2PDZ128rmbkz = 4021, X86_VCVTQQ2PDZ128rmk = 4022, X86_VCVTQQ2PDZ128rmkz = 4023, X86_VCVTQQ2PDZ128rr = 4024, X86_VCVTQQ2PDZ128rrk = 4025, X86_VCVTQQ2PDZ128rrkz = 4026, X86_VCVTQQ2PDZ256rm = 4027, X86_VCVTQQ2PDZ256rmb = 4028, X86_VCVTQQ2PDZ256rmbk = 4029, X86_VCVTQQ2PDZ256rmbkz = 4030, X86_VCVTQQ2PDZ256rmk = 4031, X86_VCVTQQ2PDZ256rmkz = 4032, X86_VCVTQQ2PDZ256rr = 4033, X86_VCVTQQ2PDZ256rrk = 4034, X86_VCVTQQ2PDZ256rrkz = 4035, X86_VCVTQQ2PDZrm = 4036, X86_VCVTQQ2PDZrmb = 4037, X86_VCVTQQ2PDZrmbk = 4038, X86_VCVTQQ2PDZrmbkz = 4039, X86_VCVTQQ2PDZrmk = 4040, X86_VCVTQQ2PDZrmkz = 4041, X86_VCVTQQ2PDZrr = 4042, X86_VCVTQQ2PDZrrb = 4043, X86_VCVTQQ2PDZrrbk = 4044, X86_VCVTQQ2PDZrrbkz = 4045, X86_VCVTQQ2PDZrrk = 4046, X86_VCVTQQ2PDZrrkz = 4047, X86_VCVTQQ2PSZ128rm = 4048, X86_VCVTQQ2PSZ128rmb = 4049, X86_VCVTQQ2PSZ128rmbk = 4050, X86_VCVTQQ2PSZ128rmbkz = 4051, X86_VCVTQQ2PSZ128rmk = 4052, X86_VCVTQQ2PSZ128rmkz = 4053, X86_VCVTQQ2PSZ128rr = 4054, X86_VCVTQQ2PSZ128rrk = 4055, X86_VCVTQQ2PSZ128rrkz = 4056, X86_VCVTQQ2PSZ256rm = 4057, X86_VCVTQQ2PSZ256rmb = 4058, X86_VCVTQQ2PSZ256rmbk = 4059, X86_VCVTQQ2PSZ256rmbkz = 4060, X86_VCVTQQ2PSZ256rmk = 4061, X86_VCVTQQ2PSZ256rmkz = 4062, X86_VCVTQQ2PSZ256rr = 4063, X86_VCVTQQ2PSZ256rrk = 4064, X86_VCVTQQ2PSZ256rrkz = 4065, X86_VCVTQQ2PSZrm = 4066, X86_VCVTQQ2PSZrmb = 4067, X86_VCVTQQ2PSZrmbk = 4068, X86_VCVTQQ2PSZrmbkz = 4069, X86_VCVTQQ2PSZrmk = 4070, X86_VCVTQQ2PSZrmkz = 4071, X86_VCVTQQ2PSZrr = 4072, X86_VCVTQQ2PSZrrb = 4073, X86_VCVTQQ2PSZrrbk = 4074, X86_VCVTQQ2PSZrrbkz = 4075, X86_VCVTQQ2PSZrrk = 4076, X86_VCVTQQ2PSZrrkz = 4077, X86_VCVTSD2SI64Zrm_Int = 4078, X86_VCVTSD2SI64Zrr_Int = 4079, X86_VCVTSD2SI64Zrrb_Int = 4080, X86_VCVTSD2SI64rm_Int = 4081, X86_VCVTSD2SI64rr_Int = 4082, X86_VCVTSD2SIZrm_Int = 4083, X86_VCVTSD2SIZrr_Int = 4084, X86_VCVTSD2SIZrrb_Int = 4085, X86_VCVTSD2SIrm_Int = 4086, X86_VCVTSD2SIrr_Int = 4087, X86_VCVTSD2SSZrm = 4088, X86_VCVTSD2SSZrm_Int = 4089, X86_VCVTSD2SSZrm_Intk = 4090, X86_VCVTSD2SSZrm_Intkz = 4091, X86_VCVTSD2SSZrr = 4092, X86_VCVTSD2SSZrr_Int = 4093, X86_VCVTSD2SSZrr_Intk = 4094, X86_VCVTSD2SSZrr_Intkz = 4095, X86_VCVTSD2SSZrrb_Int = 4096, X86_VCVTSD2SSZrrb_Intk = 4097, X86_VCVTSD2SSZrrb_Intkz = 4098, X86_VCVTSD2SSrm = 4099, X86_VCVTSD2SSrm_Int = 4100, X86_VCVTSD2SSrr = 4101, X86_VCVTSD2SSrr_Int = 4102, X86_VCVTSD2USI64Zrm_Int = 4103, X86_VCVTSD2USI64Zrr_Int = 4104, X86_VCVTSD2USI64Zrrb_Int = 4105, X86_VCVTSD2USIZrm_Int = 4106, X86_VCVTSD2USIZrr_Int = 4107, X86_VCVTSD2USIZrrb_Int = 4108, X86_VCVTSI2SDZrm = 4109, X86_VCVTSI2SDZrm_Int = 4110, X86_VCVTSI2SDZrr = 4111, X86_VCVTSI2SDZrr_Int = 4112, X86_VCVTSI2SDZrrb_Int = 4113, X86_VCVTSI2SDrm = 4114, X86_VCVTSI2SDrm_Int = 4115, X86_VCVTSI2SDrr = 4116, X86_VCVTSI2SDrr_Int = 4117, X86_VCVTSI2SSZrm = 4118, X86_VCVTSI2SSZrm_Int = 4119, X86_VCVTSI2SSZrr = 4120, X86_VCVTSI2SSZrr_Int = 4121, X86_VCVTSI2SSZrrb_Int = 4122, X86_VCVTSI2SSrm = 4123, X86_VCVTSI2SSrm_Int = 4124, X86_VCVTSI2SSrr = 4125, X86_VCVTSI2SSrr_Int = 4126, X86_VCVTSI642SDZrm = 4127, X86_VCVTSI642SDZrm_Int = 4128, X86_VCVTSI642SDZrr = 4129, X86_VCVTSI642SDZrr_Int = 4130, X86_VCVTSI642SDZrrb_Int = 4131, X86_VCVTSI642SDrm = 4132, X86_VCVTSI642SDrm_Int = 4133, X86_VCVTSI642SDrr = 4134, X86_VCVTSI642SDrr_Int = 4135, X86_VCVTSI642SSZrm = 4136, X86_VCVTSI642SSZrm_Int = 4137, X86_VCVTSI642SSZrr = 4138, X86_VCVTSI642SSZrr_Int = 4139, X86_VCVTSI642SSZrrb_Int = 4140, X86_VCVTSI642SSrm = 4141, X86_VCVTSI642SSrm_Int = 4142, X86_VCVTSI642SSrr = 4143, X86_VCVTSI642SSrr_Int = 4144, X86_VCVTSS2SDZrm = 4145, X86_VCVTSS2SDZrm_Int = 4146, X86_VCVTSS2SDZrm_Intk = 4147, X86_VCVTSS2SDZrm_Intkz = 4148, X86_VCVTSS2SDZrr = 4149, X86_VCVTSS2SDZrr_Int = 4150, X86_VCVTSS2SDZrr_Intk = 4151, X86_VCVTSS2SDZrr_Intkz = 4152, X86_VCVTSS2SDZrrb_Int = 4153, X86_VCVTSS2SDZrrb_Intk = 4154, X86_VCVTSS2SDZrrb_Intkz = 4155, X86_VCVTSS2SDrm = 4156, X86_VCVTSS2SDrm_Int = 4157, X86_VCVTSS2SDrr = 4158, X86_VCVTSS2SDrr_Int = 4159, X86_VCVTSS2SI64Zrm_Int = 4160, X86_VCVTSS2SI64Zrr_Int = 4161, X86_VCVTSS2SI64Zrrb_Int = 4162, X86_VCVTSS2SI64rm_Int = 4163, X86_VCVTSS2SI64rr_Int = 4164, X86_VCVTSS2SIZrm_Int = 4165, X86_VCVTSS2SIZrr_Int = 4166, X86_VCVTSS2SIZrrb_Int = 4167, X86_VCVTSS2SIrm_Int = 4168, X86_VCVTSS2SIrr_Int = 4169, X86_VCVTSS2USI64Zrm_Int = 4170, X86_VCVTSS2USI64Zrr_Int = 4171, X86_VCVTSS2USI64Zrrb_Int = 4172, X86_VCVTSS2USIZrm_Int = 4173, X86_VCVTSS2USIZrr_Int = 4174, X86_VCVTSS2USIZrrb_Int = 4175, X86_VCVTTPD2DQYrm = 4176, X86_VCVTTPD2DQYrr = 4177, X86_VCVTTPD2DQZ128rm = 4178, X86_VCVTTPD2DQZ128rmb = 4179, X86_VCVTTPD2DQZ128rmbk = 4180, X86_VCVTTPD2DQZ128rmbkz = 4181, X86_VCVTTPD2DQZ128rmk = 4182, X86_VCVTTPD2DQZ128rmkz = 4183, X86_VCVTTPD2DQZ128rr = 4184, X86_VCVTTPD2DQZ128rrk = 4185, X86_VCVTTPD2DQZ128rrkz = 4186, X86_VCVTTPD2DQZ256rm = 4187, X86_VCVTTPD2DQZ256rmb = 4188, X86_VCVTTPD2DQZ256rmbk = 4189, X86_VCVTTPD2DQZ256rmbkz = 4190, X86_VCVTTPD2DQZ256rmk = 4191, X86_VCVTTPD2DQZ256rmkz = 4192, X86_VCVTTPD2DQZ256rr = 4193, X86_VCVTTPD2DQZ256rrk = 4194, X86_VCVTTPD2DQZ256rrkz = 4195, X86_VCVTTPD2DQZrm = 4196, X86_VCVTTPD2DQZrmb = 4197, X86_VCVTTPD2DQZrmbk = 4198, X86_VCVTTPD2DQZrmbkz = 4199, X86_VCVTTPD2DQZrmk = 4200, X86_VCVTTPD2DQZrmkz = 4201, X86_VCVTTPD2DQZrr = 4202, X86_VCVTTPD2DQZrrb = 4203, X86_VCVTTPD2DQZrrbk = 4204, X86_VCVTTPD2DQZrrbkz = 4205, X86_VCVTTPD2DQZrrk = 4206, X86_VCVTTPD2DQZrrkz = 4207, X86_VCVTTPD2DQrm = 4208, X86_VCVTTPD2DQrr = 4209, X86_VCVTTPD2QQZ128rm = 4210, X86_VCVTTPD2QQZ128rmb = 4211, X86_VCVTTPD2QQZ128rmbk = 4212, X86_VCVTTPD2QQZ128rmbkz = 4213, X86_VCVTTPD2QQZ128rmk = 4214, X86_VCVTTPD2QQZ128rmkz = 4215, X86_VCVTTPD2QQZ128rr = 4216, X86_VCVTTPD2QQZ128rrk = 4217, X86_VCVTTPD2QQZ128rrkz = 4218, X86_VCVTTPD2QQZ256rm = 4219, X86_VCVTTPD2QQZ256rmb = 4220, X86_VCVTTPD2QQZ256rmbk = 4221, X86_VCVTTPD2QQZ256rmbkz = 4222, X86_VCVTTPD2QQZ256rmk = 4223, X86_VCVTTPD2QQZ256rmkz = 4224, X86_VCVTTPD2QQZ256rr = 4225, X86_VCVTTPD2QQZ256rrk = 4226, X86_VCVTTPD2QQZ256rrkz = 4227, X86_VCVTTPD2QQZrm = 4228, X86_VCVTTPD2QQZrmb = 4229, X86_VCVTTPD2QQZrmbk = 4230, X86_VCVTTPD2QQZrmbkz = 4231, X86_VCVTTPD2QQZrmk = 4232, X86_VCVTTPD2QQZrmkz = 4233, X86_VCVTTPD2QQZrr = 4234, X86_VCVTTPD2QQZrrb = 4235, X86_VCVTTPD2QQZrrbk = 4236, X86_VCVTTPD2QQZrrbkz = 4237, X86_VCVTTPD2QQZrrk = 4238, X86_VCVTTPD2QQZrrkz = 4239, X86_VCVTTPD2UDQZ128rm = 4240, X86_VCVTTPD2UDQZ128rmb = 4241, X86_VCVTTPD2UDQZ128rmbk = 4242, X86_VCVTTPD2UDQZ128rmbkz = 4243, X86_VCVTTPD2UDQZ128rmk = 4244, X86_VCVTTPD2UDQZ128rmkz = 4245, X86_VCVTTPD2UDQZ128rr = 4246, X86_VCVTTPD2UDQZ128rrk = 4247, X86_VCVTTPD2UDQZ128rrkz = 4248, X86_VCVTTPD2UDQZ256rm = 4249, X86_VCVTTPD2UDQZ256rmb = 4250, X86_VCVTTPD2UDQZ256rmbk = 4251, X86_VCVTTPD2UDQZ256rmbkz = 4252, X86_VCVTTPD2UDQZ256rmk = 4253, X86_VCVTTPD2UDQZ256rmkz = 4254, X86_VCVTTPD2UDQZ256rr = 4255, X86_VCVTTPD2UDQZ256rrk = 4256, X86_VCVTTPD2UDQZ256rrkz = 4257, X86_VCVTTPD2UDQZrm = 4258, X86_VCVTTPD2UDQZrmb = 4259, X86_VCVTTPD2UDQZrmbk = 4260, X86_VCVTTPD2UDQZrmbkz = 4261, X86_VCVTTPD2UDQZrmk = 4262, X86_VCVTTPD2UDQZrmkz = 4263, X86_VCVTTPD2UDQZrr = 4264, X86_VCVTTPD2UDQZrrb = 4265, X86_VCVTTPD2UDQZrrbk = 4266, X86_VCVTTPD2UDQZrrbkz = 4267, X86_VCVTTPD2UDQZrrk = 4268, X86_VCVTTPD2UDQZrrkz = 4269, X86_VCVTTPD2UQQZ128rm = 4270, X86_VCVTTPD2UQQZ128rmb = 4271, X86_VCVTTPD2UQQZ128rmbk = 4272, X86_VCVTTPD2UQQZ128rmbkz = 4273, X86_VCVTTPD2UQQZ128rmk = 4274, X86_VCVTTPD2UQQZ128rmkz = 4275, X86_VCVTTPD2UQQZ128rr = 4276, X86_VCVTTPD2UQQZ128rrk = 4277, X86_VCVTTPD2UQQZ128rrkz = 4278, X86_VCVTTPD2UQQZ256rm = 4279, X86_VCVTTPD2UQQZ256rmb = 4280, X86_VCVTTPD2UQQZ256rmbk = 4281, X86_VCVTTPD2UQQZ256rmbkz = 4282, X86_VCVTTPD2UQQZ256rmk = 4283, X86_VCVTTPD2UQQZ256rmkz = 4284, X86_VCVTTPD2UQQZ256rr = 4285, X86_VCVTTPD2UQQZ256rrk = 4286, X86_VCVTTPD2UQQZ256rrkz = 4287, X86_VCVTTPD2UQQZrm = 4288, X86_VCVTTPD2UQQZrmb = 4289, X86_VCVTTPD2UQQZrmbk = 4290, X86_VCVTTPD2UQQZrmbkz = 4291, X86_VCVTTPD2UQQZrmk = 4292, X86_VCVTTPD2UQQZrmkz = 4293, X86_VCVTTPD2UQQZrr = 4294, X86_VCVTTPD2UQQZrrb = 4295, X86_VCVTTPD2UQQZrrbk = 4296, X86_VCVTTPD2UQQZrrbkz = 4297, X86_VCVTTPD2UQQZrrk = 4298, X86_VCVTTPD2UQQZrrkz = 4299, X86_VCVTTPS2DQYrm = 4300, X86_VCVTTPS2DQYrr = 4301, X86_VCVTTPS2DQZ128rm = 4302, X86_VCVTTPS2DQZ128rmb = 4303, X86_VCVTTPS2DQZ128rmbk = 4304, X86_VCVTTPS2DQZ128rmbkz = 4305, X86_VCVTTPS2DQZ128rmk = 4306, X86_VCVTTPS2DQZ128rmkz = 4307, X86_VCVTTPS2DQZ128rr = 4308, X86_VCVTTPS2DQZ128rrk = 4309, X86_VCVTTPS2DQZ128rrkz = 4310, X86_VCVTTPS2DQZ256rm = 4311, X86_VCVTTPS2DQZ256rmb = 4312, X86_VCVTTPS2DQZ256rmbk = 4313, X86_VCVTTPS2DQZ256rmbkz = 4314, X86_VCVTTPS2DQZ256rmk = 4315, X86_VCVTTPS2DQZ256rmkz = 4316, X86_VCVTTPS2DQZ256rr = 4317, X86_VCVTTPS2DQZ256rrk = 4318, X86_VCVTTPS2DQZ256rrkz = 4319, X86_VCVTTPS2DQZrm = 4320, X86_VCVTTPS2DQZrmb = 4321, X86_VCVTTPS2DQZrmbk = 4322, X86_VCVTTPS2DQZrmbkz = 4323, X86_VCVTTPS2DQZrmk = 4324, X86_VCVTTPS2DQZrmkz = 4325, X86_VCVTTPS2DQZrr = 4326, X86_VCVTTPS2DQZrrb = 4327, X86_VCVTTPS2DQZrrbk = 4328, X86_VCVTTPS2DQZrrbkz = 4329, X86_VCVTTPS2DQZrrk = 4330, X86_VCVTTPS2DQZrrkz = 4331, X86_VCVTTPS2DQrm = 4332, X86_VCVTTPS2DQrr = 4333, X86_VCVTTPS2QQZ128rm = 4334, X86_VCVTTPS2QQZ128rmb = 4335, X86_VCVTTPS2QQZ128rmbk = 4336, X86_VCVTTPS2QQZ128rmbkz = 4337, X86_VCVTTPS2QQZ128rmk = 4338, X86_VCVTTPS2QQZ128rmkz = 4339, X86_VCVTTPS2QQZ128rr = 4340, X86_VCVTTPS2QQZ128rrk = 4341, X86_VCVTTPS2QQZ128rrkz = 4342, X86_VCVTTPS2QQZ256rm = 4343, X86_VCVTTPS2QQZ256rmb = 4344, X86_VCVTTPS2QQZ256rmbk = 4345, X86_VCVTTPS2QQZ256rmbkz = 4346, X86_VCVTTPS2QQZ256rmk = 4347, X86_VCVTTPS2QQZ256rmkz = 4348, X86_VCVTTPS2QQZ256rr = 4349, X86_VCVTTPS2QQZ256rrk = 4350, X86_VCVTTPS2QQZ256rrkz = 4351, X86_VCVTTPS2QQZrm = 4352, X86_VCVTTPS2QQZrmb = 4353, X86_VCVTTPS2QQZrmbk = 4354, X86_VCVTTPS2QQZrmbkz = 4355, X86_VCVTTPS2QQZrmk = 4356, X86_VCVTTPS2QQZrmkz = 4357, X86_VCVTTPS2QQZrr = 4358, X86_VCVTTPS2QQZrrb = 4359, X86_VCVTTPS2QQZrrbk = 4360, X86_VCVTTPS2QQZrrbkz = 4361, X86_VCVTTPS2QQZrrk = 4362, X86_VCVTTPS2QQZrrkz = 4363, X86_VCVTTPS2UDQZ128rm = 4364, X86_VCVTTPS2UDQZ128rmb = 4365, X86_VCVTTPS2UDQZ128rmbk = 4366, X86_VCVTTPS2UDQZ128rmbkz = 4367, X86_VCVTTPS2UDQZ128rmk = 4368, X86_VCVTTPS2UDQZ128rmkz = 4369, X86_VCVTTPS2UDQZ128rr = 4370, X86_VCVTTPS2UDQZ128rrk = 4371, X86_VCVTTPS2UDQZ128rrkz = 4372, X86_VCVTTPS2UDQZ256rm = 4373, X86_VCVTTPS2UDQZ256rmb = 4374, X86_VCVTTPS2UDQZ256rmbk = 4375, X86_VCVTTPS2UDQZ256rmbkz = 4376, X86_VCVTTPS2UDQZ256rmk = 4377, X86_VCVTTPS2UDQZ256rmkz = 4378, X86_VCVTTPS2UDQZ256rr = 4379, X86_VCVTTPS2UDQZ256rrk = 4380, X86_VCVTTPS2UDQZ256rrkz = 4381, X86_VCVTTPS2UDQZrm = 4382, X86_VCVTTPS2UDQZrmb = 4383, X86_VCVTTPS2UDQZrmbk = 4384, X86_VCVTTPS2UDQZrmbkz = 4385, X86_VCVTTPS2UDQZrmk = 4386, X86_VCVTTPS2UDQZrmkz = 4387, X86_VCVTTPS2UDQZrr = 4388, X86_VCVTTPS2UDQZrrb = 4389, X86_VCVTTPS2UDQZrrbk = 4390, X86_VCVTTPS2UDQZrrbkz = 4391, X86_VCVTTPS2UDQZrrk = 4392, X86_VCVTTPS2UDQZrrkz = 4393, X86_VCVTTPS2UQQZ128rm = 4394, X86_VCVTTPS2UQQZ128rmb = 4395, X86_VCVTTPS2UQQZ128rmbk = 4396, X86_VCVTTPS2UQQZ128rmbkz = 4397, X86_VCVTTPS2UQQZ128rmk = 4398, X86_VCVTTPS2UQQZ128rmkz = 4399, X86_VCVTTPS2UQQZ128rr = 4400, X86_VCVTTPS2UQQZ128rrk = 4401, X86_VCVTTPS2UQQZ128rrkz = 4402, X86_VCVTTPS2UQQZ256rm = 4403, X86_VCVTTPS2UQQZ256rmb = 4404, X86_VCVTTPS2UQQZ256rmbk = 4405, X86_VCVTTPS2UQQZ256rmbkz = 4406, X86_VCVTTPS2UQQZ256rmk = 4407, X86_VCVTTPS2UQQZ256rmkz = 4408, X86_VCVTTPS2UQQZ256rr = 4409, X86_VCVTTPS2UQQZ256rrk = 4410, X86_VCVTTPS2UQQZ256rrkz = 4411, X86_VCVTTPS2UQQZrm = 4412, X86_VCVTTPS2UQQZrmb = 4413, X86_VCVTTPS2UQQZrmbk = 4414, X86_VCVTTPS2UQQZrmbkz = 4415, X86_VCVTTPS2UQQZrmk = 4416, X86_VCVTTPS2UQQZrmkz = 4417, X86_VCVTTPS2UQQZrr = 4418, X86_VCVTTPS2UQQZrrb = 4419, X86_VCVTTPS2UQQZrrbk = 4420, X86_VCVTTPS2UQQZrrbkz = 4421, X86_VCVTTPS2UQQZrrk = 4422, X86_VCVTTPS2UQQZrrkz = 4423, X86_VCVTTSD2SI64Zrm = 4424, X86_VCVTTSD2SI64Zrm_Int = 4425, X86_VCVTTSD2SI64Zrr = 4426, X86_VCVTTSD2SI64Zrr_Int = 4427, X86_VCVTTSD2SI64Zrrb_Int = 4428, X86_VCVTTSD2SI64rm = 4429, X86_VCVTTSD2SI64rm_Int = 4430, X86_VCVTTSD2SI64rr = 4431, X86_VCVTTSD2SI64rr_Int = 4432, X86_VCVTTSD2SIZrm = 4433, X86_VCVTTSD2SIZrm_Int = 4434, X86_VCVTTSD2SIZrr = 4435, X86_VCVTTSD2SIZrr_Int = 4436, X86_VCVTTSD2SIZrrb_Int = 4437, X86_VCVTTSD2SIrm = 4438, X86_VCVTTSD2SIrm_Int = 4439, X86_VCVTTSD2SIrr = 4440, X86_VCVTTSD2SIrr_Int = 4441, X86_VCVTTSD2USI64Zrm = 4442, X86_VCVTTSD2USI64Zrm_Int = 4443, X86_VCVTTSD2USI64Zrr = 4444, X86_VCVTTSD2USI64Zrr_Int = 4445, X86_VCVTTSD2USI64Zrrb_Int = 4446, X86_VCVTTSD2USIZrm = 4447, X86_VCVTTSD2USIZrm_Int = 4448, X86_VCVTTSD2USIZrr = 4449, X86_VCVTTSD2USIZrr_Int = 4450, X86_VCVTTSD2USIZrrb_Int = 4451, X86_VCVTTSS2SI64Zrm = 4452, X86_VCVTTSS2SI64Zrm_Int = 4453, X86_VCVTTSS2SI64Zrr = 4454, X86_VCVTTSS2SI64Zrr_Int = 4455, X86_VCVTTSS2SI64Zrrb_Int = 4456, X86_VCVTTSS2SI64rm = 4457, X86_VCVTTSS2SI64rm_Int = 4458, X86_VCVTTSS2SI64rr = 4459, X86_VCVTTSS2SI64rr_Int = 4460, X86_VCVTTSS2SIZrm = 4461, X86_VCVTTSS2SIZrm_Int = 4462, X86_VCVTTSS2SIZrr = 4463, X86_VCVTTSS2SIZrr_Int = 4464, X86_VCVTTSS2SIZrrb_Int = 4465, X86_VCVTTSS2SIrm = 4466, X86_VCVTTSS2SIrm_Int = 4467, X86_VCVTTSS2SIrr = 4468, X86_VCVTTSS2SIrr_Int = 4469, X86_VCVTTSS2USI64Zrm = 4470, X86_VCVTTSS2USI64Zrm_Int = 4471, X86_VCVTTSS2USI64Zrr = 4472, X86_VCVTTSS2USI64Zrr_Int = 4473, X86_VCVTTSS2USI64Zrrb_Int = 4474, X86_VCVTTSS2USIZrm = 4475, X86_VCVTTSS2USIZrm_Int = 4476, X86_VCVTTSS2USIZrr = 4477, X86_VCVTTSS2USIZrr_Int = 4478, X86_VCVTTSS2USIZrrb_Int = 4479, X86_VCVTUDQ2PDZ128rm = 4480, X86_VCVTUDQ2PDZ128rmb = 4481, X86_VCVTUDQ2PDZ128rmbk = 4482, X86_VCVTUDQ2PDZ128rmbkz = 4483, X86_VCVTUDQ2PDZ128rmk = 4484, X86_VCVTUDQ2PDZ128rmkz = 4485, X86_VCVTUDQ2PDZ128rr = 4486, X86_VCVTUDQ2PDZ128rrk = 4487, X86_VCVTUDQ2PDZ128rrkz = 4488, X86_VCVTUDQ2PDZ256rm = 4489, X86_VCVTUDQ2PDZ256rmb = 4490, X86_VCVTUDQ2PDZ256rmbk = 4491, X86_VCVTUDQ2PDZ256rmbkz = 4492, X86_VCVTUDQ2PDZ256rmk = 4493, X86_VCVTUDQ2PDZ256rmkz = 4494, X86_VCVTUDQ2PDZ256rr = 4495, X86_VCVTUDQ2PDZ256rrk = 4496, X86_VCVTUDQ2PDZ256rrkz = 4497, X86_VCVTUDQ2PDZrm = 4498, X86_VCVTUDQ2PDZrmb = 4499, X86_VCVTUDQ2PDZrmbk = 4500, X86_VCVTUDQ2PDZrmbkz = 4501, X86_VCVTUDQ2PDZrmk = 4502, X86_VCVTUDQ2PDZrmkz = 4503, X86_VCVTUDQ2PDZrr = 4504, X86_VCVTUDQ2PDZrrk = 4505, X86_VCVTUDQ2PDZrrkz = 4506, X86_VCVTUDQ2PSZ128rm = 4507, X86_VCVTUDQ2PSZ128rmb = 4508, X86_VCVTUDQ2PSZ128rmbk = 4509, X86_VCVTUDQ2PSZ128rmbkz = 4510, X86_VCVTUDQ2PSZ128rmk = 4511, X86_VCVTUDQ2PSZ128rmkz = 4512, X86_VCVTUDQ2PSZ128rr = 4513, X86_VCVTUDQ2PSZ128rrk = 4514, X86_VCVTUDQ2PSZ128rrkz = 4515, X86_VCVTUDQ2PSZ256rm = 4516, X86_VCVTUDQ2PSZ256rmb = 4517, X86_VCVTUDQ2PSZ256rmbk = 4518, X86_VCVTUDQ2PSZ256rmbkz = 4519, X86_VCVTUDQ2PSZ256rmk = 4520, X86_VCVTUDQ2PSZ256rmkz = 4521, X86_VCVTUDQ2PSZ256rr = 4522, X86_VCVTUDQ2PSZ256rrk = 4523, X86_VCVTUDQ2PSZ256rrkz = 4524, X86_VCVTUDQ2PSZrm = 4525, X86_VCVTUDQ2PSZrmb = 4526, X86_VCVTUDQ2PSZrmbk = 4527, X86_VCVTUDQ2PSZrmbkz = 4528, X86_VCVTUDQ2PSZrmk = 4529, X86_VCVTUDQ2PSZrmkz = 4530, X86_VCVTUDQ2PSZrr = 4531, X86_VCVTUDQ2PSZrrb = 4532, X86_VCVTUDQ2PSZrrbk = 4533, X86_VCVTUDQ2PSZrrbkz = 4534, X86_VCVTUDQ2PSZrrk = 4535, X86_VCVTUDQ2PSZrrkz = 4536, X86_VCVTUQQ2PDZ128rm = 4537, X86_VCVTUQQ2PDZ128rmb = 4538, X86_VCVTUQQ2PDZ128rmbk = 4539, X86_VCVTUQQ2PDZ128rmbkz = 4540, X86_VCVTUQQ2PDZ128rmk = 4541, X86_VCVTUQQ2PDZ128rmkz = 4542, X86_VCVTUQQ2PDZ128rr = 4543, X86_VCVTUQQ2PDZ128rrk = 4544, X86_VCVTUQQ2PDZ128rrkz = 4545, X86_VCVTUQQ2PDZ256rm = 4546, X86_VCVTUQQ2PDZ256rmb = 4547, X86_VCVTUQQ2PDZ256rmbk = 4548, X86_VCVTUQQ2PDZ256rmbkz = 4549, X86_VCVTUQQ2PDZ256rmk = 4550, X86_VCVTUQQ2PDZ256rmkz = 4551, X86_VCVTUQQ2PDZ256rr = 4552, X86_VCVTUQQ2PDZ256rrk = 4553, X86_VCVTUQQ2PDZ256rrkz = 4554, X86_VCVTUQQ2PDZrm = 4555, X86_VCVTUQQ2PDZrmb = 4556, X86_VCVTUQQ2PDZrmbk = 4557, X86_VCVTUQQ2PDZrmbkz = 4558, X86_VCVTUQQ2PDZrmk = 4559, X86_VCVTUQQ2PDZrmkz = 4560, X86_VCVTUQQ2PDZrr = 4561, X86_VCVTUQQ2PDZrrb = 4562, X86_VCVTUQQ2PDZrrbk = 4563, X86_VCVTUQQ2PDZrrbkz = 4564, X86_VCVTUQQ2PDZrrk = 4565, X86_VCVTUQQ2PDZrrkz = 4566, X86_VCVTUQQ2PSZ128rm = 4567, X86_VCVTUQQ2PSZ128rmb = 4568, X86_VCVTUQQ2PSZ128rmbk = 4569, X86_VCVTUQQ2PSZ128rmbkz = 4570, X86_VCVTUQQ2PSZ128rmk = 4571, X86_VCVTUQQ2PSZ128rmkz = 4572, X86_VCVTUQQ2PSZ128rr = 4573, X86_VCVTUQQ2PSZ128rrk = 4574, X86_VCVTUQQ2PSZ128rrkz = 4575, X86_VCVTUQQ2PSZ256rm = 4576, X86_VCVTUQQ2PSZ256rmb = 4577, X86_VCVTUQQ2PSZ256rmbk = 4578, X86_VCVTUQQ2PSZ256rmbkz = 4579, X86_VCVTUQQ2PSZ256rmk = 4580, X86_VCVTUQQ2PSZ256rmkz = 4581, X86_VCVTUQQ2PSZ256rr = 4582, X86_VCVTUQQ2PSZ256rrk = 4583, X86_VCVTUQQ2PSZ256rrkz = 4584, X86_VCVTUQQ2PSZrm = 4585, X86_VCVTUQQ2PSZrmb = 4586, X86_VCVTUQQ2PSZrmbk = 4587, X86_VCVTUQQ2PSZrmbkz = 4588, X86_VCVTUQQ2PSZrmk = 4589, X86_VCVTUQQ2PSZrmkz = 4590, X86_VCVTUQQ2PSZrr = 4591, X86_VCVTUQQ2PSZrrb = 4592, X86_VCVTUQQ2PSZrrbk = 4593, X86_VCVTUQQ2PSZrrbkz = 4594, X86_VCVTUQQ2PSZrrk = 4595, X86_VCVTUQQ2PSZrrkz = 4596, X86_VCVTUSI2SDZrm = 4597, X86_VCVTUSI2SDZrm_Int = 4598, X86_VCVTUSI2SDZrr = 4599, X86_VCVTUSI2SDZrr_Int = 4600, X86_VCVTUSI2SSZrm = 4601, X86_VCVTUSI2SSZrm_Int = 4602, X86_VCVTUSI2SSZrr = 4603, X86_VCVTUSI2SSZrr_Int = 4604, X86_VCVTUSI2SSZrrb_Int = 4605, X86_VCVTUSI642SDZrm = 4606, X86_VCVTUSI642SDZrm_Int = 4607, X86_VCVTUSI642SDZrr = 4608, X86_VCVTUSI642SDZrr_Int = 4609, X86_VCVTUSI642SDZrrb_Int = 4610, X86_VCVTUSI642SSZrm = 4611, X86_VCVTUSI642SSZrm_Int = 4612, X86_VCVTUSI642SSZrr = 4613, X86_VCVTUSI642SSZrr_Int = 4614, X86_VCVTUSI642SSZrrb_Int = 4615, X86_VDBPSADBWZ128rmi = 4616, X86_VDBPSADBWZ128rmik = 4617, X86_VDBPSADBWZ128rmikz = 4618, X86_VDBPSADBWZ128rri = 4619, X86_VDBPSADBWZ128rrik = 4620, X86_VDBPSADBWZ128rrikz = 4621, X86_VDBPSADBWZ256rmi = 4622, X86_VDBPSADBWZ256rmik = 4623, X86_VDBPSADBWZ256rmikz = 4624, X86_VDBPSADBWZ256rri = 4625, X86_VDBPSADBWZ256rrik = 4626, X86_VDBPSADBWZ256rrikz = 4627, X86_VDBPSADBWZrmi = 4628, X86_VDBPSADBWZrmik = 4629, X86_VDBPSADBWZrmikz = 4630, X86_VDBPSADBWZrri = 4631, X86_VDBPSADBWZrrik = 4632, X86_VDBPSADBWZrrikz = 4633, X86_VDIVPDYrm = 4634, X86_VDIVPDYrr = 4635, X86_VDIVPDZ128rm = 4636, X86_VDIVPDZ128rmb = 4637, X86_VDIVPDZ128rmbk = 4638, X86_VDIVPDZ128rmbkz = 4639, X86_VDIVPDZ128rmk = 4640, X86_VDIVPDZ128rmkz = 4641, X86_VDIVPDZ128rr = 4642, X86_VDIVPDZ128rrk = 4643, X86_VDIVPDZ128rrkz = 4644, X86_VDIVPDZ256rm = 4645, X86_VDIVPDZ256rmb = 4646, X86_VDIVPDZ256rmbk = 4647, X86_VDIVPDZ256rmbkz = 4648, X86_VDIVPDZ256rmk = 4649, X86_VDIVPDZ256rmkz = 4650, X86_VDIVPDZ256rr = 4651, X86_VDIVPDZ256rrk = 4652, X86_VDIVPDZ256rrkz = 4653, X86_VDIVPDZrm = 4654, X86_VDIVPDZrmb = 4655, X86_VDIVPDZrmbk = 4656, X86_VDIVPDZrmbkz = 4657, X86_VDIVPDZrmk = 4658, X86_VDIVPDZrmkz = 4659, X86_VDIVPDZrr = 4660, X86_VDIVPDZrrb = 4661, X86_VDIVPDZrrbk = 4662, X86_VDIVPDZrrbkz = 4663, X86_VDIVPDZrrk = 4664, X86_VDIVPDZrrkz = 4665, X86_VDIVPDrm = 4666, X86_VDIVPDrr = 4667, X86_VDIVPSYrm = 4668, X86_VDIVPSYrr = 4669, X86_VDIVPSZ128rm = 4670, X86_VDIVPSZ128rmb = 4671, X86_VDIVPSZ128rmbk = 4672, X86_VDIVPSZ128rmbkz = 4673, X86_VDIVPSZ128rmk = 4674, X86_VDIVPSZ128rmkz = 4675, X86_VDIVPSZ128rr = 4676, X86_VDIVPSZ128rrk = 4677, X86_VDIVPSZ128rrkz = 4678, X86_VDIVPSZ256rm = 4679, X86_VDIVPSZ256rmb = 4680, X86_VDIVPSZ256rmbk = 4681, X86_VDIVPSZ256rmbkz = 4682, X86_VDIVPSZ256rmk = 4683, X86_VDIVPSZ256rmkz = 4684, X86_VDIVPSZ256rr = 4685, X86_VDIVPSZ256rrk = 4686, X86_VDIVPSZ256rrkz = 4687, X86_VDIVPSZrm = 4688, X86_VDIVPSZrmb = 4689, X86_VDIVPSZrmbk = 4690, X86_VDIVPSZrmbkz = 4691, X86_VDIVPSZrmk = 4692, X86_VDIVPSZrmkz = 4693, X86_VDIVPSZrr = 4694, X86_VDIVPSZrrb = 4695, X86_VDIVPSZrrbk = 4696, X86_VDIVPSZrrbkz = 4697, X86_VDIVPSZrrk = 4698, X86_VDIVPSZrrkz = 4699, X86_VDIVPSrm = 4700, X86_VDIVPSrr = 4701, X86_VDIVSDZrm = 4702, X86_VDIVSDZrm_Int = 4703, X86_VDIVSDZrm_Intk = 4704, X86_VDIVSDZrm_Intkz = 4705, X86_VDIVSDZrr = 4706, X86_VDIVSDZrr_Int = 4707, X86_VDIVSDZrr_Intk = 4708, X86_VDIVSDZrr_Intkz = 4709, X86_VDIVSDZrrb_Int = 4710, X86_VDIVSDZrrb_Intk = 4711, X86_VDIVSDZrrb_Intkz = 4712, X86_VDIVSDrm = 4713, X86_VDIVSDrm_Int = 4714, X86_VDIVSDrr = 4715, X86_VDIVSDrr_Int = 4716, X86_VDIVSSZrm = 4717, X86_VDIVSSZrm_Int = 4718, X86_VDIVSSZrm_Intk = 4719, X86_VDIVSSZrm_Intkz = 4720, X86_VDIVSSZrr = 4721, X86_VDIVSSZrr_Int = 4722, X86_VDIVSSZrr_Intk = 4723, X86_VDIVSSZrr_Intkz = 4724, X86_VDIVSSZrrb_Int = 4725, X86_VDIVSSZrrb_Intk = 4726, X86_VDIVSSZrrb_Intkz = 4727, X86_VDIVSSrm = 4728, X86_VDIVSSrm_Int = 4729, X86_VDIVSSrr = 4730, X86_VDIVSSrr_Int = 4731, X86_VDPPDrmi = 4732, X86_VDPPDrri = 4733, X86_VDPPSYrmi = 4734, X86_VDPPSYrri = 4735, X86_VDPPSrmi = 4736, X86_VDPPSrri = 4737, X86_VERRm = 4738, X86_VERRr = 4739, X86_VERWm = 4740, X86_VERWr = 4741, X86_VEXP2PDZm = 4742, X86_VEXP2PDZmb = 4743, X86_VEXP2PDZmbk = 4744, X86_VEXP2PDZmbkz = 4745, X86_VEXP2PDZmk = 4746, X86_VEXP2PDZmkz = 4747, X86_VEXP2PDZr = 4748, X86_VEXP2PDZrb = 4749, X86_VEXP2PDZrbk = 4750, X86_VEXP2PDZrbkz = 4751, X86_VEXP2PDZrk = 4752, X86_VEXP2PDZrkz = 4753, X86_VEXP2PSZm = 4754, X86_VEXP2PSZmb = 4755, X86_VEXP2PSZmbk = 4756, X86_VEXP2PSZmbkz = 4757, X86_VEXP2PSZmk = 4758, X86_VEXP2PSZmkz = 4759, X86_VEXP2PSZr = 4760, X86_VEXP2PSZrb = 4761, X86_VEXP2PSZrbk = 4762, X86_VEXP2PSZrbkz = 4763, X86_VEXP2PSZrk = 4764, X86_VEXP2PSZrkz = 4765, X86_VEXPANDPDZ128rm = 4766, X86_VEXPANDPDZ128rmk = 4767, X86_VEXPANDPDZ128rmkz = 4768, X86_VEXPANDPDZ128rr = 4769, X86_VEXPANDPDZ128rrk = 4770, X86_VEXPANDPDZ128rrkz = 4771, X86_VEXPANDPDZ256rm = 4772, X86_VEXPANDPDZ256rmk = 4773, X86_VEXPANDPDZ256rmkz = 4774, X86_VEXPANDPDZ256rr = 4775, X86_VEXPANDPDZ256rrk = 4776, X86_VEXPANDPDZ256rrkz = 4777, X86_VEXPANDPDZrm = 4778, X86_VEXPANDPDZrmk = 4779, X86_VEXPANDPDZrmkz = 4780, X86_VEXPANDPDZrr = 4781, X86_VEXPANDPDZrrk = 4782, X86_VEXPANDPDZrrkz = 4783, X86_VEXPANDPSZ128rm = 4784, X86_VEXPANDPSZ128rmk = 4785, X86_VEXPANDPSZ128rmkz = 4786, X86_VEXPANDPSZ128rr = 4787, X86_VEXPANDPSZ128rrk = 4788, X86_VEXPANDPSZ128rrkz = 4789, X86_VEXPANDPSZ256rm = 4790, X86_VEXPANDPSZ256rmk = 4791, X86_VEXPANDPSZ256rmkz = 4792, X86_VEXPANDPSZ256rr = 4793, X86_VEXPANDPSZ256rrk = 4794, X86_VEXPANDPSZ256rrkz = 4795, X86_VEXPANDPSZrm = 4796, X86_VEXPANDPSZrmk = 4797, X86_VEXPANDPSZrmkz = 4798, X86_VEXPANDPSZrr = 4799, X86_VEXPANDPSZrrk = 4800, X86_VEXPANDPSZrrkz = 4801, X86_VEXTRACTF128mr = 4802, X86_VEXTRACTF128rr = 4803, X86_VEXTRACTF32x4Z256mr = 4804, X86_VEXTRACTF32x4Z256mrk = 4805, X86_VEXTRACTF32x4Z256rr = 4806, X86_VEXTRACTF32x4Z256rrk = 4807, X86_VEXTRACTF32x4Z256rrkz = 4808, X86_VEXTRACTF32x4Zmr = 4809, X86_VEXTRACTF32x4Zmrk = 4810, X86_VEXTRACTF32x4Zrr = 4811, X86_VEXTRACTF32x4Zrrk = 4812, X86_VEXTRACTF32x4Zrrkz = 4813, X86_VEXTRACTF32x8Zmr = 4814, X86_VEXTRACTF32x8Zmrk = 4815, X86_VEXTRACTF32x8Zrr = 4816, X86_VEXTRACTF32x8Zrrk = 4817, X86_VEXTRACTF32x8Zrrkz = 4818, X86_VEXTRACTF64x2Z256mr = 4819, X86_VEXTRACTF64x2Z256mrk = 4820, X86_VEXTRACTF64x2Z256rr = 4821, X86_VEXTRACTF64x2Z256rrk = 4822, X86_VEXTRACTF64x2Z256rrkz = 4823, X86_VEXTRACTF64x2Zmr = 4824, X86_VEXTRACTF64x2Zmrk = 4825, X86_VEXTRACTF64x2Zrr = 4826, X86_VEXTRACTF64x2Zrrk = 4827, X86_VEXTRACTF64x2Zrrkz = 4828, X86_VEXTRACTF64x4Zmr = 4829, X86_VEXTRACTF64x4Zmrk = 4830, X86_VEXTRACTF64x4Zrr = 4831, X86_VEXTRACTF64x4Zrrk = 4832, X86_VEXTRACTF64x4Zrrkz = 4833, X86_VEXTRACTI128mr = 4834, X86_VEXTRACTI128rr = 4835, X86_VEXTRACTI32x4Z256mr = 4836, X86_VEXTRACTI32x4Z256mrk = 4837, X86_VEXTRACTI32x4Z256rr = 4838, X86_VEXTRACTI32x4Z256rrk = 4839, X86_VEXTRACTI32x4Z256rrkz = 4840, X86_VEXTRACTI32x4Zmr = 4841, X86_VEXTRACTI32x4Zmrk = 4842, X86_VEXTRACTI32x4Zrr = 4843, X86_VEXTRACTI32x4Zrrk = 4844, X86_VEXTRACTI32x4Zrrkz = 4845, X86_VEXTRACTI32x8Zmr = 4846, X86_VEXTRACTI32x8Zmrk = 4847, X86_VEXTRACTI32x8Zrr = 4848, X86_VEXTRACTI32x8Zrrk = 4849, X86_VEXTRACTI32x8Zrrkz = 4850, X86_VEXTRACTI64x2Z256mr = 4851, X86_VEXTRACTI64x2Z256mrk = 4852, X86_VEXTRACTI64x2Z256rr = 4853, X86_VEXTRACTI64x2Z256rrk = 4854, X86_VEXTRACTI64x2Z256rrkz = 4855, X86_VEXTRACTI64x2Zmr = 4856, X86_VEXTRACTI64x2Zmrk = 4857, X86_VEXTRACTI64x2Zrr = 4858, X86_VEXTRACTI64x2Zrrk = 4859, X86_VEXTRACTI64x2Zrrkz = 4860, X86_VEXTRACTI64x4Zmr = 4861, X86_VEXTRACTI64x4Zmrk = 4862, X86_VEXTRACTI64x4Zrr = 4863, X86_VEXTRACTI64x4Zrrk = 4864, X86_VEXTRACTI64x4Zrrkz = 4865, X86_VEXTRACTPSZmr = 4866, X86_VEXTRACTPSZrr = 4867, X86_VEXTRACTPSmr = 4868, X86_VEXTRACTPSrr = 4869, X86_VFIXUPIMMPDZ128rmbi = 4870, X86_VFIXUPIMMPDZ128rmbik = 4871, X86_VFIXUPIMMPDZ128rmbikz = 4872, X86_VFIXUPIMMPDZ128rmi = 4873, X86_VFIXUPIMMPDZ128rmik = 4874, X86_VFIXUPIMMPDZ128rmikz = 4875, X86_VFIXUPIMMPDZ128rri = 4876, X86_VFIXUPIMMPDZ128rrik = 4877, X86_VFIXUPIMMPDZ128rrikz = 4878, X86_VFIXUPIMMPDZ256rmbi = 4879, X86_VFIXUPIMMPDZ256rmbik = 4880, X86_VFIXUPIMMPDZ256rmbikz = 4881, X86_VFIXUPIMMPDZ256rmi = 4882, X86_VFIXUPIMMPDZ256rmik = 4883, X86_VFIXUPIMMPDZ256rmikz = 4884, X86_VFIXUPIMMPDZ256rri = 4885, X86_VFIXUPIMMPDZ256rrik = 4886, X86_VFIXUPIMMPDZ256rrikz = 4887, X86_VFIXUPIMMPDZrmbi = 4888, X86_VFIXUPIMMPDZrmbik = 4889, X86_VFIXUPIMMPDZrmbikz = 4890, X86_VFIXUPIMMPDZrmi = 4891, X86_VFIXUPIMMPDZrmik = 4892, X86_VFIXUPIMMPDZrmikz = 4893, X86_VFIXUPIMMPDZrri = 4894, X86_VFIXUPIMMPDZrrib = 4895, X86_VFIXUPIMMPDZrribk = 4896, X86_VFIXUPIMMPDZrribkz = 4897, X86_VFIXUPIMMPDZrrik = 4898, X86_VFIXUPIMMPDZrrikz = 4899, X86_VFIXUPIMMPSZ128rmbi = 4900, X86_VFIXUPIMMPSZ128rmbik = 4901, X86_VFIXUPIMMPSZ128rmbikz = 4902, X86_VFIXUPIMMPSZ128rmi = 4903, X86_VFIXUPIMMPSZ128rmik = 4904, X86_VFIXUPIMMPSZ128rmikz = 4905, X86_VFIXUPIMMPSZ128rri = 4906, X86_VFIXUPIMMPSZ128rrik = 4907, X86_VFIXUPIMMPSZ128rrikz = 4908, X86_VFIXUPIMMPSZ256rmbi = 4909, X86_VFIXUPIMMPSZ256rmbik = 4910, X86_VFIXUPIMMPSZ256rmbikz = 4911, X86_VFIXUPIMMPSZ256rmi = 4912, X86_VFIXUPIMMPSZ256rmik = 4913, X86_VFIXUPIMMPSZ256rmikz = 4914, X86_VFIXUPIMMPSZ256rri = 4915, X86_VFIXUPIMMPSZ256rrik = 4916, X86_VFIXUPIMMPSZ256rrikz = 4917, X86_VFIXUPIMMPSZrmbi = 4918, X86_VFIXUPIMMPSZrmbik = 4919, X86_VFIXUPIMMPSZrmbikz = 4920, X86_VFIXUPIMMPSZrmi = 4921, X86_VFIXUPIMMPSZrmik = 4922, X86_VFIXUPIMMPSZrmikz = 4923, X86_VFIXUPIMMPSZrri = 4924, X86_VFIXUPIMMPSZrrib = 4925, X86_VFIXUPIMMPSZrribk = 4926, X86_VFIXUPIMMPSZrribkz = 4927, X86_VFIXUPIMMPSZrrik = 4928, X86_VFIXUPIMMPSZrrikz = 4929, X86_VFIXUPIMMSDZrmi = 4930, X86_VFIXUPIMMSDZrmik = 4931, X86_VFIXUPIMMSDZrmikz = 4932, X86_VFIXUPIMMSDZrri = 4933, X86_VFIXUPIMMSDZrrib = 4934, X86_VFIXUPIMMSDZrribk = 4935, X86_VFIXUPIMMSDZrribkz = 4936, X86_VFIXUPIMMSDZrrik = 4937, X86_VFIXUPIMMSDZrrikz = 4938, X86_VFIXUPIMMSSZrmi = 4939, X86_VFIXUPIMMSSZrmik = 4940, X86_VFIXUPIMMSSZrmikz = 4941, X86_VFIXUPIMMSSZrri = 4942, X86_VFIXUPIMMSSZrrib = 4943, X86_VFIXUPIMMSSZrribk = 4944, X86_VFIXUPIMMSSZrribkz = 4945, X86_VFIXUPIMMSSZrrik = 4946, X86_VFIXUPIMMSSZrrikz = 4947, X86_VFMADD132PDYm = 4948, X86_VFMADD132PDYr = 4949, X86_VFMADD132PDZ128m = 4950, X86_VFMADD132PDZ128mb = 4951, X86_VFMADD132PDZ128mbk = 4952, X86_VFMADD132PDZ128mbkz = 4953, X86_VFMADD132PDZ128mk = 4954, X86_VFMADD132PDZ128mkz = 4955, X86_VFMADD132PDZ128r = 4956, X86_VFMADD132PDZ128rk = 4957, X86_VFMADD132PDZ128rkz = 4958, X86_VFMADD132PDZ256m = 4959, X86_VFMADD132PDZ256mb = 4960, X86_VFMADD132PDZ256mbk = 4961, X86_VFMADD132PDZ256mbkz = 4962, X86_VFMADD132PDZ256mk = 4963, X86_VFMADD132PDZ256mkz = 4964, X86_VFMADD132PDZ256r = 4965, X86_VFMADD132PDZ256rk = 4966, X86_VFMADD132PDZ256rkz = 4967, X86_VFMADD132PDZm = 4968, X86_VFMADD132PDZmb = 4969, X86_VFMADD132PDZmbk = 4970, X86_VFMADD132PDZmbkz = 4971, X86_VFMADD132PDZmk = 4972, X86_VFMADD132PDZmkz = 4973, X86_VFMADD132PDZr = 4974, X86_VFMADD132PDZrb = 4975, X86_VFMADD132PDZrbk = 4976, X86_VFMADD132PDZrbkz = 4977, X86_VFMADD132PDZrk = 4978, X86_VFMADD132PDZrkz = 4979, X86_VFMADD132PDm = 4980, X86_VFMADD132PDr = 4981, X86_VFMADD132PSYm = 4982, X86_VFMADD132PSYr = 4983, X86_VFMADD132PSZ128m = 4984, X86_VFMADD132PSZ128mb = 4985, X86_VFMADD132PSZ128mbk = 4986, X86_VFMADD132PSZ128mbkz = 4987, X86_VFMADD132PSZ128mk = 4988, X86_VFMADD132PSZ128mkz = 4989, X86_VFMADD132PSZ128r = 4990, X86_VFMADD132PSZ128rk = 4991, X86_VFMADD132PSZ128rkz = 4992, X86_VFMADD132PSZ256m = 4993, X86_VFMADD132PSZ256mb = 4994, X86_VFMADD132PSZ256mbk = 4995, X86_VFMADD132PSZ256mbkz = 4996, X86_VFMADD132PSZ256mk = 4997, X86_VFMADD132PSZ256mkz = 4998, X86_VFMADD132PSZ256r = 4999, X86_VFMADD132PSZ256rk = 5000, X86_VFMADD132PSZ256rkz = 5001, X86_VFMADD132PSZm = 5002, X86_VFMADD132PSZmb = 5003, X86_VFMADD132PSZmbk = 5004, X86_VFMADD132PSZmbkz = 5005, X86_VFMADD132PSZmk = 5006, X86_VFMADD132PSZmkz = 5007, X86_VFMADD132PSZr = 5008, X86_VFMADD132PSZrb = 5009, X86_VFMADD132PSZrbk = 5010, X86_VFMADD132PSZrbkz = 5011, X86_VFMADD132PSZrk = 5012, X86_VFMADD132PSZrkz = 5013, X86_VFMADD132PSm = 5014, X86_VFMADD132PSr = 5015, X86_VFMADD132SDZm = 5016, X86_VFMADD132SDZm_Int = 5017, X86_VFMADD132SDZm_Intk = 5018, X86_VFMADD132SDZm_Intkz = 5019, X86_VFMADD132SDZr = 5020, X86_VFMADD132SDZr_Int = 5021, X86_VFMADD132SDZr_Intk = 5022, X86_VFMADD132SDZr_Intkz = 5023, X86_VFMADD132SDZrb = 5024, X86_VFMADD132SDZrb_Int = 5025, X86_VFMADD132SDZrb_Intk = 5026, X86_VFMADD132SDZrb_Intkz = 5027, X86_VFMADD132SDm = 5028, X86_VFMADD132SDm_Int = 5029, X86_VFMADD132SDr = 5030, X86_VFMADD132SDr_Int = 5031, X86_VFMADD132SSZm = 5032, X86_VFMADD132SSZm_Int = 5033, X86_VFMADD132SSZm_Intk = 5034, X86_VFMADD132SSZm_Intkz = 5035, X86_VFMADD132SSZr = 5036, X86_VFMADD132SSZr_Int = 5037, X86_VFMADD132SSZr_Intk = 5038, X86_VFMADD132SSZr_Intkz = 5039, X86_VFMADD132SSZrb = 5040, X86_VFMADD132SSZrb_Int = 5041, X86_VFMADD132SSZrb_Intk = 5042, X86_VFMADD132SSZrb_Intkz = 5043, X86_VFMADD132SSm = 5044, X86_VFMADD132SSm_Int = 5045, X86_VFMADD132SSr = 5046, X86_VFMADD132SSr_Int = 5047, X86_VFMADD213PDYm = 5048, X86_VFMADD213PDYr = 5049, X86_VFMADD213PDZ128m = 5050, X86_VFMADD213PDZ128mb = 5051, X86_VFMADD213PDZ128mbk = 5052, X86_VFMADD213PDZ128mbkz = 5053, X86_VFMADD213PDZ128mk = 5054, X86_VFMADD213PDZ128mkz = 5055, X86_VFMADD213PDZ128r = 5056, X86_VFMADD213PDZ128rk = 5057, X86_VFMADD213PDZ128rkz = 5058, X86_VFMADD213PDZ256m = 5059, X86_VFMADD213PDZ256mb = 5060, X86_VFMADD213PDZ256mbk = 5061, X86_VFMADD213PDZ256mbkz = 5062, X86_VFMADD213PDZ256mk = 5063, X86_VFMADD213PDZ256mkz = 5064, X86_VFMADD213PDZ256r = 5065, X86_VFMADD213PDZ256rk = 5066, X86_VFMADD213PDZ256rkz = 5067, X86_VFMADD213PDZm = 5068, X86_VFMADD213PDZmb = 5069, X86_VFMADD213PDZmbk = 5070, X86_VFMADD213PDZmbkz = 5071, X86_VFMADD213PDZmk = 5072, X86_VFMADD213PDZmkz = 5073, X86_VFMADD213PDZr = 5074, X86_VFMADD213PDZrb = 5075, X86_VFMADD213PDZrbk = 5076, X86_VFMADD213PDZrbkz = 5077, X86_VFMADD213PDZrk = 5078, X86_VFMADD213PDZrkz = 5079, X86_VFMADD213PDm = 5080, X86_VFMADD213PDr = 5081, X86_VFMADD213PSYm = 5082, X86_VFMADD213PSYr = 5083, X86_VFMADD213PSZ128m = 5084, X86_VFMADD213PSZ128mb = 5085, X86_VFMADD213PSZ128mbk = 5086, X86_VFMADD213PSZ128mbkz = 5087, X86_VFMADD213PSZ128mk = 5088, X86_VFMADD213PSZ128mkz = 5089, X86_VFMADD213PSZ128r = 5090, X86_VFMADD213PSZ128rk = 5091, X86_VFMADD213PSZ128rkz = 5092, X86_VFMADD213PSZ256m = 5093, X86_VFMADD213PSZ256mb = 5094, X86_VFMADD213PSZ256mbk = 5095, X86_VFMADD213PSZ256mbkz = 5096, X86_VFMADD213PSZ256mk = 5097, X86_VFMADD213PSZ256mkz = 5098, X86_VFMADD213PSZ256r = 5099, X86_VFMADD213PSZ256rk = 5100, X86_VFMADD213PSZ256rkz = 5101, X86_VFMADD213PSZm = 5102, X86_VFMADD213PSZmb = 5103, X86_VFMADD213PSZmbk = 5104, X86_VFMADD213PSZmbkz = 5105, X86_VFMADD213PSZmk = 5106, X86_VFMADD213PSZmkz = 5107, X86_VFMADD213PSZr = 5108, X86_VFMADD213PSZrb = 5109, X86_VFMADD213PSZrbk = 5110, X86_VFMADD213PSZrbkz = 5111, X86_VFMADD213PSZrk = 5112, X86_VFMADD213PSZrkz = 5113, X86_VFMADD213PSm = 5114, X86_VFMADD213PSr = 5115, X86_VFMADD213SDZm = 5116, X86_VFMADD213SDZm_Int = 5117, X86_VFMADD213SDZm_Intk = 5118, X86_VFMADD213SDZm_Intkz = 5119, X86_VFMADD213SDZr = 5120, X86_VFMADD213SDZr_Int = 5121, X86_VFMADD213SDZr_Intk = 5122, X86_VFMADD213SDZr_Intkz = 5123, X86_VFMADD213SDZrb = 5124, X86_VFMADD213SDZrb_Int = 5125, X86_VFMADD213SDZrb_Intk = 5126, X86_VFMADD213SDZrb_Intkz = 5127, X86_VFMADD213SDm = 5128, X86_VFMADD213SDm_Int = 5129, X86_VFMADD213SDr = 5130, X86_VFMADD213SDr_Int = 5131, X86_VFMADD213SSZm = 5132, X86_VFMADD213SSZm_Int = 5133, X86_VFMADD213SSZm_Intk = 5134, X86_VFMADD213SSZm_Intkz = 5135, X86_VFMADD213SSZr = 5136, X86_VFMADD213SSZr_Int = 5137, X86_VFMADD213SSZr_Intk = 5138, X86_VFMADD213SSZr_Intkz = 5139, X86_VFMADD213SSZrb = 5140, X86_VFMADD213SSZrb_Int = 5141, X86_VFMADD213SSZrb_Intk = 5142, X86_VFMADD213SSZrb_Intkz = 5143, X86_VFMADD213SSm = 5144, X86_VFMADD213SSm_Int = 5145, X86_VFMADD213SSr = 5146, X86_VFMADD213SSr_Int = 5147, X86_VFMADD231PDYm = 5148, X86_VFMADD231PDYr = 5149, X86_VFMADD231PDZ128m = 5150, X86_VFMADD231PDZ128mb = 5151, X86_VFMADD231PDZ128mbk = 5152, X86_VFMADD231PDZ128mbkz = 5153, X86_VFMADD231PDZ128mk = 5154, X86_VFMADD231PDZ128mkz = 5155, X86_VFMADD231PDZ128r = 5156, X86_VFMADD231PDZ128rk = 5157, X86_VFMADD231PDZ128rkz = 5158, X86_VFMADD231PDZ256m = 5159, X86_VFMADD231PDZ256mb = 5160, X86_VFMADD231PDZ256mbk = 5161, X86_VFMADD231PDZ256mbkz = 5162, X86_VFMADD231PDZ256mk = 5163, X86_VFMADD231PDZ256mkz = 5164, X86_VFMADD231PDZ256r = 5165, X86_VFMADD231PDZ256rk = 5166, X86_VFMADD231PDZ256rkz = 5167, X86_VFMADD231PDZm = 5168, X86_VFMADD231PDZmb = 5169, X86_VFMADD231PDZmbk = 5170, X86_VFMADD231PDZmbkz = 5171, X86_VFMADD231PDZmk = 5172, X86_VFMADD231PDZmkz = 5173, X86_VFMADD231PDZr = 5174, X86_VFMADD231PDZrb = 5175, X86_VFMADD231PDZrbk = 5176, X86_VFMADD231PDZrbkz = 5177, X86_VFMADD231PDZrk = 5178, X86_VFMADD231PDZrkz = 5179, X86_VFMADD231PDm = 5180, X86_VFMADD231PDr = 5181, X86_VFMADD231PSYm = 5182, X86_VFMADD231PSYr = 5183, X86_VFMADD231PSZ128m = 5184, X86_VFMADD231PSZ128mb = 5185, X86_VFMADD231PSZ128mbk = 5186, X86_VFMADD231PSZ128mbkz = 5187, X86_VFMADD231PSZ128mk = 5188, X86_VFMADD231PSZ128mkz = 5189, X86_VFMADD231PSZ128r = 5190, X86_VFMADD231PSZ128rk = 5191, X86_VFMADD231PSZ128rkz = 5192, X86_VFMADD231PSZ256m = 5193, X86_VFMADD231PSZ256mb = 5194, X86_VFMADD231PSZ256mbk = 5195, X86_VFMADD231PSZ256mbkz = 5196, X86_VFMADD231PSZ256mk = 5197, X86_VFMADD231PSZ256mkz = 5198, X86_VFMADD231PSZ256r = 5199, X86_VFMADD231PSZ256rk = 5200, X86_VFMADD231PSZ256rkz = 5201, X86_VFMADD231PSZm = 5202, X86_VFMADD231PSZmb = 5203, X86_VFMADD231PSZmbk = 5204, X86_VFMADD231PSZmbkz = 5205, X86_VFMADD231PSZmk = 5206, X86_VFMADD231PSZmkz = 5207, X86_VFMADD231PSZr = 5208, X86_VFMADD231PSZrb = 5209, X86_VFMADD231PSZrbk = 5210, X86_VFMADD231PSZrbkz = 5211, X86_VFMADD231PSZrk = 5212, X86_VFMADD231PSZrkz = 5213, X86_VFMADD231PSm = 5214, X86_VFMADD231PSr = 5215, X86_VFMADD231SDZm = 5216, X86_VFMADD231SDZm_Int = 5217, X86_VFMADD231SDZm_Intk = 5218, X86_VFMADD231SDZm_Intkz = 5219, X86_VFMADD231SDZr = 5220, X86_VFMADD231SDZr_Int = 5221, X86_VFMADD231SDZr_Intk = 5222, X86_VFMADD231SDZr_Intkz = 5223, X86_VFMADD231SDZrb = 5224, X86_VFMADD231SDZrb_Int = 5225, X86_VFMADD231SDZrb_Intk = 5226, X86_VFMADD231SDZrb_Intkz = 5227, X86_VFMADD231SDm = 5228, X86_VFMADD231SDm_Int = 5229, X86_VFMADD231SDr = 5230, X86_VFMADD231SDr_Int = 5231, X86_VFMADD231SSZm = 5232, X86_VFMADD231SSZm_Int = 5233, X86_VFMADD231SSZm_Intk = 5234, X86_VFMADD231SSZm_Intkz = 5235, X86_VFMADD231SSZr = 5236, X86_VFMADD231SSZr_Int = 5237, X86_VFMADD231SSZr_Intk = 5238, X86_VFMADD231SSZr_Intkz = 5239, X86_VFMADD231SSZrb = 5240, X86_VFMADD231SSZrb_Int = 5241, X86_VFMADD231SSZrb_Intk = 5242, X86_VFMADD231SSZrb_Intkz = 5243, X86_VFMADD231SSm = 5244, X86_VFMADD231SSm_Int = 5245, X86_VFMADD231SSr = 5246, X86_VFMADD231SSr_Int = 5247, X86_VFMADDPD4Ymr = 5248, X86_VFMADDPD4Yrm = 5249, X86_VFMADDPD4Yrr = 5250, X86_VFMADDPD4Yrr_REV = 5251, X86_VFMADDPD4mr = 5252, X86_VFMADDPD4rm = 5253, X86_VFMADDPD4rr = 5254, X86_VFMADDPD4rr_REV = 5255, X86_VFMADDPS4Ymr = 5256, X86_VFMADDPS4Yrm = 5257, X86_VFMADDPS4Yrr = 5258, X86_VFMADDPS4Yrr_REV = 5259, X86_VFMADDPS4mr = 5260, X86_VFMADDPS4rm = 5261, X86_VFMADDPS4rr = 5262, X86_VFMADDPS4rr_REV = 5263, X86_VFMADDSD4mr = 5264, X86_VFMADDSD4mr_Int = 5265, X86_VFMADDSD4rm = 5266, X86_VFMADDSD4rm_Int = 5267, X86_VFMADDSD4rr = 5268, X86_VFMADDSD4rr_Int = 5269, X86_VFMADDSD4rr_Int_REV = 5270, X86_VFMADDSD4rr_REV = 5271, X86_VFMADDSS4mr = 5272, X86_VFMADDSS4mr_Int = 5273, X86_VFMADDSS4rm = 5274, X86_VFMADDSS4rm_Int = 5275, X86_VFMADDSS4rr = 5276, X86_VFMADDSS4rr_Int = 5277, X86_VFMADDSS4rr_Int_REV = 5278, X86_VFMADDSS4rr_REV = 5279, X86_VFMADDSUB132PDYm = 5280, X86_VFMADDSUB132PDYr = 5281, X86_VFMADDSUB132PDZ128m = 5282, X86_VFMADDSUB132PDZ128mb = 5283, X86_VFMADDSUB132PDZ128mbk = 5284, X86_VFMADDSUB132PDZ128mbkz = 5285, X86_VFMADDSUB132PDZ128mk = 5286, X86_VFMADDSUB132PDZ128mkz = 5287, X86_VFMADDSUB132PDZ128r = 5288, X86_VFMADDSUB132PDZ128rk = 5289, X86_VFMADDSUB132PDZ128rkz = 5290, X86_VFMADDSUB132PDZ256m = 5291, X86_VFMADDSUB132PDZ256mb = 5292, X86_VFMADDSUB132PDZ256mbk = 5293, X86_VFMADDSUB132PDZ256mbkz = 5294, X86_VFMADDSUB132PDZ256mk = 5295, X86_VFMADDSUB132PDZ256mkz = 5296, X86_VFMADDSUB132PDZ256r = 5297, X86_VFMADDSUB132PDZ256rk = 5298, X86_VFMADDSUB132PDZ256rkz = 5299, X86_VFMADDSUB132PDZm = 5300, X86_VFMADDSUB132PDZmb = 5301, X86_VFMADDSUB132PDZmbk = 5302, X86_VFMADDSUB132PDZmbkz = 5303, X86_VFMADDSUB132PDZmk = 5304, X86_VFMADDSUB132PDZmkz = 5305, X86_VFMADDSUB132PDZr = 5306, X86_VFMADDSUB132PDZrb = 5307, X86_VFMADDSUB132PDZrbk = 5308, X86_VFMADDSUB132PDZrbkz = 5309, X86_VFMADDSUB132PDZrk = 5310, X86_VFMADDSUB132PDZrkz = 5311, X86_VFMADDSUB132PDm = 5312, X86_VFMADDSUB132PDr = 5313, X86_VFMADDSUB132PSYm = 5314, X86_VFMADDSUB132PSYr = 5315, X86_VFMADDSUB132PSZ128m = 5316, X86_VFMADDSUB132PSZ128mb = 5317, X86_VFMADDSUB132PSZ128mbk = 5318, X86_VFMADDSUB132PSZ128mbkz = 5319, X86_VFMADDSUB132PSZ128mk = 5320, X86_VFMADDSUB132PSZ128mkz = 5321, X86_VFMADDSUB132PSZ128r = 5322, X86_VFMADDSUB132PSZ128rk = 5323, X86_VFMADDSUB132PSZ128rkz = 5324, X86_VFMADDSUB132PSZ256m = 5325, X86_VFMADDSUB132PSZ256mb = 5326, X86_VFMADDSUB132PSZ256mbk = 5327, X86_VFMADDSUB132PSZ256mbkz = 5328, X86_VFMADDSUB132PSZ256mk = 5329, X86_VFMADDSUB132PSZ256mkz = 5330, X86_VFMADDSUB132PSZ256r = 5331, X86_VFMADDSUB132PSZ256rk = 5332, X86_VFMADDSUB132PSZ256rkz = 5333, X86_VFMADDSUB132PSZm = 5334, X86_VFMADDSUB132PSZmb = 5335, X86_VFMADDSUB132PSZmbk = 5336, X86_VFMADDSUB132PSZmbkz = 5337, X86_VFMADDSUB132PSZmk = 5338, X86_VFMADDSUB132PSZmkz = 5339, X86_VFMADDSUB132PSZr = 5340, X86_VFMADDSUB132PSZrb = 5341, X86_VFMADDSUB132PSZrbk = 5342, X86_VFMADDSUB132PSZrbkz = 5343, X86_VFMADDSUB132PSZrk = 5344, X86_VFMADDSUB132PSZrkz = 5345, X86_VFMADDSUB132PSm = 5346, X86_VFMADDSUB132PSr = 5347, X86_VFMADDSUB213PDYm = 5348, X86_VFMADDSUB213PDYr = 5349, X86_VFMADDSUB213PDZ128m = 5350, X86_VFMADDSUB213PDZ128mb = 5351, X86_VFMADDSUB213PDZ128mbk = 5352, X86_VFMADDSUB213PDZ128mbkz = 5353, X86_VFMADDSUB213PDZ128mk = 5354, X86_VFMADDSUB213PDZ128mkz = 5355, X86_VFMADDSUB213PDZ128r = 5356, X86_VFMADDSUB213PDZ128rk = 5357, X86_VFMADDSUB213PDZ128rkz = 5358, X86_VFMADDSUB213PDZ256m = 5359, X86_VFMADDSUB213PDZ256mb = 5360, X86_VFMADDSUB213PDZ256mbk = 5361, X86_VFMADDSUB213PDZ256mbkz = 5362, X86_VFMADDSUB213PDZ256mk = 5363, X86_VFMADDSUB213PDZ256mkz = 5364, X86_VFMADDSUB213PDZ256r = 5365, X86_VFMADDSUB213PDZ256rk = 5366, X86_VFMADDSUB213PDZ256rkz = 5367, X86_VFMADDSUB213PDZm = 5368, X86_VFMADDSUB213PDZmb = 5369, X86_VFMADDSUB213PDZmbk = 5370, X86_VFMADDSUB213PDZmbkz = 5371, X86_VFMADDSUB213PDZmk = 5372, X86_VFMADDSUB213PDZmkz = 5373, X86_VFMADDSUB213PDZr = 5374, X86_VFMADDSUB213PDZrb = 5375, X86_VFMADDSUB213PDZrbk = 5376, X86_VFMADDSUB213PDZrbkz = 5377, X86_VFMADDSUB213PDZrk = 5378, X86_VFMADDSUB213PDZrkz = 5379, X86_VFMADDSUB213PDm = 5380, X86_VFMADDSUB213PDr = 5381, X86_VFMADDSUB213PSYm = 5382, X86_VFMADDSUB213PSYr = 5383, X86_VFMADDSUB213PSZ128m = 5384, X86_VFMADDSUB213PSZ128mb = 5385, X86_VFMADDSUB213PSZ128mbk = 5386, X86_VFMADDSUB213PSZ128mbkz = 5387, X86_VFMADDSUB213PSZ128mk = 5388, X86_VFMADDSUB213PSZ128mkz = 5389, X86_VFMADDSUB213PSZ128r = 5390, X86_VFMADDSUB213PSZ128rk = 5391, X86_VFMADDSUB213PSZ128rkz = 5392, X86_VFMADDSUB213PSZ256m = 5393, X86_VFMADDSUB213PSZ256mb = 5394, X86_VFMADDSUB213PSZ256mbk = 5395, X86_VFMADDSUB213PSZ256mbkz = 5396, X86_VFMADDSUB213PSZ256mk = 5397, X86_VFMADDSUB213PSZ256mkz = 5398, X86_VFMADDSUB213PSZ256r = 5399, X86_VFMADDSUB213PSZ256rk = 5400, X86_VFMADDSUB213PSZ256rkz = 5401, X86_VFMADDSUB213PSZm = 5402, X86_VFMADDSUB213PSZmb = 5403, X86_VFMADDSUB213PSZmbk = 5404, X86_VFMADDSUB213PSZmbkz = 5405, X86_VFMADDSUB213PSZmk = 5406, X86_VFMADDSUB213PSZmkz = 5407, X86_VFMADDSUB213PSZr = 5408, X86_VFMADDSUB213PSZrb = 5409, X86_VFMADDSUB213PSZrbk = 5410, X86_VFMADDSUB213PSZrbkz = 5411, X86_VFMADDSUB213PSZrk = 5412, X86_VFMADDSUB213PSZrkz = 5413, X86_VFMADDSUB213PSm = 5414, X86_VFMADDSUB213PSr = 5415, X86_VFMADDSUB231PDYm = 5416, X86_VFMADDSUB231PDYr = 5417, X86_VFMADDSUB231PDZ128m = 5418, X86_VFMADDSUB231PDZ128mb = 5419, X86_VFMADDSUB231PDZ128mbk = 5420, X86_VFMADDSUB231PDZ128mbkz = 5421, X86_VFMADDSUB231PDZ128mk = 5422, X86_VFMADDSUB231PDZ128mkz = 5423, X86_VFMADDSUB231PDZ128r = 5424, X86_VFMADDSUB231PDZ128rk = 5425, X86_VFMADDSUB231PDZ128rkz = 5426, X86_VFMADDSUB231PDZ256m = 5427, X86_VFMADDSUB231PDZ256mb = 5428, X86_VFMADDSUB231PDZ256mbk = 5429, X86_VFMADDSUB231PDZ256mbkz = 5430, X86_VFMADDSUB231PDZ256mk = 5431, X86_VFMADDSUB231PDZ256mkz = 5432, X86_VFMADDSUB231PDZ256r = 5433, X86_VFMADDSUB231PDZ256rk = 5434, X86_VFMADDSUB231PDZ256rkz = 5435, X86_VFMADDSUB231PDZm = 5436, X86_VFMADDSUB231PDZmb = 5437, X86_VFMADDSUB231PDZmbk = 5438, X86_VFMADDSUB231PDZmbkz = 5439, X86_VFMADDSUB231PDZmk = 5440, X86_VFMADDSUB231PDZmkz = 5441, X86_VFMADDSUB231PDZr = 5442, X86_VFMADDSUB231PDZrb = 5443, X86_VFMADDSUB231PDZrbk = 5444, X86_VFMADDSUB231PDZrbkz = 5445, X86_VFMADDSUB231PDZrk = 5446, X86_VFMADDSUB231PDZrkz = 5447, X86_VFMADDSUB231PDm = 5448, X86_VFMADDSUB231PDr = 5449, X86_VFMADDSUB231PSYm = 5450, X86_VFMADDSUB231PSYr = 5451, X86_VFMADDSUB231PSZ128m = 5452, X86_VFMADDSUB231PSZ128mb = 5453, X86_VFMADDSUB231PSZ128mbk = 5454, X86_VFMADDSUB231PSZ128mbkz = 5455, X86_VFMADDSUB231PSZ128mk = 5456, X86_VFMADDSUB231PSZ128mkz = 5457, X86_VFMADDSUB231PSZ128r = 5458, X86_VFMADDSUB231PSZ128rk = 5459, X86_VFMADDSUB231PSZ128rkz = 5460, X86_VFMADDSUB231PSZ256m = 5461, X86_VFMADDSUB231PSZ256mb = 5462, X86_VFMADDSUB231PSZ256mbk = 5463, X86_VFMADDSUB231PSZ256mbkz = 5464, X86_VFMADDSUB231PSZ256mk = 5465, X86_VFMADDSUB231PSZ256mkz = 5466, X86_VFMADDSUB231PSZ256r = 5467, X86_VFMADDSUB231PSZ256rk = 5468, X86_VFMADDSUB231PSZ256rkz = 5469, X86_VFMADDSUB231PSZm = 5470, X86_VFMADDSUB231PSZmb = 5471, X86_VFMADDSUB231PSZmbk = 5472, X86_VFMADDSUB231PSZmbkz = 5473, X86_VFMADDSUB231PSZmk = 5474, X86_VFMADDSUB231PSZmkz = 5475, X86_VFMADDSUB231PSZr = 5476, X86_VFMADDSUB231PSZrb = 5477, X86_VFMADDSUB231PSZrbk = 5478, X86_VFMADDSUB231PSZrbkz = 5479, X86_VFMADDSUB231PSZrk = 5480, X86_VFMADDSUB231PSZrkz = 5481, X86_VFMADDSUB231PSm = 5482, X86_VFMADDSUB231PSr = 5483, X86_VFMADDSUBPD4Ymr = 5484, X86_VFMADDSUBPD4Yrm = 5485, X86_VFMADDSUBPD4Yrr = 5486, X86_VFMADDSUBPD4Yrr_REV = 5487, X86_VFMADDSUBPD4mr = 5488, X86_VFMADDSUBPD4rm = 5489, X86_VFMADDSUBPD4rr = 5490, X86_VFMADDSUBPD4rr_REV = 5491, X86_VFMADDSUBPS4Ymr = 5492, X86_VFMADDSUBPS4Yrm = 5493, X86_VFMADDSUBPS4Yrr = 5494, X86_VFMADDSUBPS4Yrr_REV = 5495, X86_VFMADDSUBPS4mr = 5496, X86_VFMADDSUBPS4rm = 5497, X86_VFMADDSUBPS4rr = 5498, X86_VFMADDSUBPS4rr_REV = 5499, X86_VFMSUB132PDYm = 5500, X86_VFMSUB132PDYr = 5501, X86_VFMSUB132PDZ128m = 5502, X86_VFMSUB132PDZ128mb = 5503, X86_VFMSUB132PDZ128mbk = 5504, X86_VFMSUB132PDZ128mbkz = 5505, X86_VFMSUB132PDZ128mk = 5506, X86_VFMSUB132PDZ128mkz = 5507, X86_VFMSUB132PDZ128r = 5508, X86_VFMSUB132PDZ128rk = 5509, X86_VFMSUB132PDZ128rkz = 5510, X86_VFMSUB132PDZ256m = 5511, X86_VFMSUB132PDZ256mb = 5512, X86_VFMSUB132PDZ256mbk = 5513, X86_VFMSUB132PDZ256mbkz = 5514, X86_VFMSUB132PDZ256mk = 5515, X86_VFMSUB132PDZ256mkz = 5516, X86_VFMSUB132PDZ256r = 5517, X86_VFMSUB132PDZ256rk = 5518, X86_VFMSUB132PDZ256rkz = 5519, X86_VFMSUB132PDZm = 5520, X86_VFMSUB132PDZmb = 5521, X86_VFMSUB132PDZmbk = 5522, X86_VFMSUB132PDZmbkz = 5523, X86_VFMSUB132PDZmk = 5524, X86_VFMSUB132PDZmkz = 5525, X86_VFMSUB132PDZr = 5526, X86_VFMSUB132PDZrb = 5527, X86_VFMSUB132PDZrbk = 5528, X86_VFMSUB132PDZrbkz = 5529, X86_VFMSUB132PDZrk = 5530, X86_VFMSUB132PDZrkz = 5531, X86_VFMSUB132PDm = 5532, X86_VFMSUB132PDr = 5533, X86_VFMSUB132PSYm = 5534, X86_VFMSUB132PSYr = 5535, X86_VFMSUB132PSZ128m = 5536, X86_VFMSUB132PSZ128mb = 5537, X86_VFMSUB132PSZ128mbk = 5538, X86_VFMSUB132PSZ128mbkz = 5539, X86_VFMSUB132PSZ128mk = 5540, X86_VFMSUB132PSZ128mkz = 5541, X86_VFMSUB132PSZ128r = 5542, X86_VFMSUB132PSZ128rk = 5543, X86_VFMSUB132PSZ128rkz = 5544, X86_VFMSUB132PSZ256m = 5545, X86_VFMSUB132PSZ256mb = 5546, X86_VFMSUB132PSZ256mbk = 5547, X86_VFMSUB132PSZ256mbkz = 5548, X86_VFMSUB132PSZ256mk = 5549, X86_VFMSUB132PSZ256mkz = 5550, X86_VFMSUB132PSZ256r = 5551, X86_VFMSUB132PSZ256rk = 5552, X86_VFMSUB132PSZ256rkz = 5553, X86_VFMSUB132PSZm = 5554, X86_VFMSUB132PSZmb = 5555, X86_VFMSUB132PSZmbk = 5556, X86_VFMSUB132PSZmbkz = 5557, X86_VFMSUB132PSZmk = 5558, X86_VFMSUB132PSZmkz = 5559, X86_VFMSUB132PSZr = 5560, X86_VFMSUB132PSZrb = 5561, X86_VFMSUB132PSZrbk = 5562, X86_VFMSUB132PSZrbkz = 5563, X86_VFMSUB132PSZrk = 5564, X86_VFMSUB132PSZrkz = 5565, X86_VFMSUB132PSm = 5566, X86_VFMSUB132PSr = 5567, X86_VFMSUB132SDZm = 5568, X86_VFMSUB132SDZm_Int = 5569, X86_VFMSUB132SDZm_Intk = 5570, X86_VFMSUB132SDZm_Intkz = 5571, X86_VFMSUB132SDZr = 5572, X86_VFMSUB132SDZr_Int = 5573, X86_VFMSUB132SDZr_Intk = 5574, X86_VFMSUB132SDZr_Intkz = 5575, X86_VFMSUB132SDZrb = 5576, X86_VFMSUB132SDZrb_Int = 5577, X86_VFMSUB132SDZrb_Intk = 5578, X86_VFMSUB132SDZrb_Intkz = 5579, X86_VFMSUB132SDm = 5580, X86_VFMSUB132SDm_Int = 5581, X86_VFMSUB132SDr = 5582, X86_VFMSUB132SDr_Int = 5583, X86_VFMSUB132SSZm = 5584, X86_VFMSUB132SSZm_Int = 5585, X86_VFMSUB132SSZm_Intk = 5586, X86_VFMSUB132SSZm_Intkz = 5587, X86_VFMSUB132SSZr = 5588, X86_VFMSUB132SSZr_Int = 5589, X86_VFMSUB132SSZr_Intk = 5590, X86_VFMSUB132SSZr_Intkz = 5591, X86_VFMSUB132SSZrb = 5592, X86_VFMSUB132SSZrb_Int = 5593, X86_VFMSUB132SSZrb_Intk = 5594, X86_VFMSUB132SSZrb_Intkz = 5595, X86_VFMSUB132SSm = 5596, X86_VFMSUB132SSm_Int = 5597, X86_VFMSUB132SSr = 5598, X86_VFMSUB132SSr_Int = 5599, X86_VFMSUB213PDYm = 5600, X86_VFMSUB213PDYr = 5601, X86_VFMSUB213PDZ128m = 5602, X86_VFMSUB213PDZ128mb = 5603, X86_VFMSUB213PDZ128mbk = 5604, X86_VFMSUB213PDZ128mbkz = 5605, X86_VFMSUB213PDZ128mk = 5606, X86_VFMSUB213PDZ128mkz = 5607, X86_VFMSUB213PDZ128r = 5608, X86_VFMSUB213PDZ128rk = 5609, X86_VFMSUB213PDZ128rkz = 5610, X86_VFMSUB213PDZ256m = 5611, X86_VFMSUB213PDZ256mb = 5612, X86_VFMSUB213PDZ256mbk = 5613, X86_VFMSUB213PDZ256mbkz = 5614, X86_VFMSUB213PDZ256mk = 5615, X86_VFMSUB213PDZ256mkz = 5616, X86_VFMSUB213PDZ256r = 5617, X86_VFMSUB213PDZ256rk = 5618, X86_VFMSUB213PDZ256rkz = 5619, X86_VFMSUB213PDZm = 5620, X86_VFMSUB213PDZmb = 5621, X86_VFMSUB213PDZmbk = 5622, X86_VFMSUB213PDZmbkz = 5623, X86_VFMSUB213PDZmk = 5624, X86_VFMSUB213PDZmkz = 5625, X86_VFMSUB213PDZr = 5626, X86_VFMSUB213PDZrb = 5627, X86_VFMSUB213PDZrbk = 5628, X86_VFMSUB213PDZrbkz = 5629, X86_VFMSUB213PDZrk = 5630, X86_VFMSUB213PDZrkz = 5631, X86_VFMSUB213PDm = 5632, X86_VFMSUB213PDr = 5633, X86_VFMSUB213PSYm = 5634, X86_VFMSUB213PSYr = 5635, X86_VFMSUB213PSZ128m = 5636, X86_VFMSUB213PSZ128mb = 5637, X86_VFMSUB213PSZ128mbk = 5638, X86_VFMSUB213PSZ128mbkz = 5639, X86_VFMSUB213PSZ128mk = 5640, X86_VFMSUB213PSZ128mkz = 5641, X86_VFMSUB213PSZ128r = 5642, X86_VFMSUB213PSZ128rk = 5643, X86_VFMSUB213PSZ128rkz = 5644, X86_VFMSUB213PSZ256m = 5645, X86_VFMSUB213PSZ256mb = 5646, X86_VFMSUB213PSZ256mbk = 5647, X86_VFMSUB213PSZ256mbkz = 5648, X86_VFMSUB213PSZ256mk = 5649, X86_VFMSUB213PSZ256mkz = 5650, X86_VFMSUB213PSZ256r = 5651, X86_VFMSUB213PSZ256rk = 5652, X86_VFMSUB213PSZ256rkz = 5653, X86_VFMSUB213PSZm = 5654, X86_VFMSUB213PSZmb = 5655, X86_VFMSUB213PSZmbk = 5656, X86_VFMSUB213PSZmbkz = 5657, X86_VFMSUB213PSZmk = 5658, X86_VFMSUB213PSZmkz = 5659, X86_VFMSUB213PSZr = 5660, X86_VFMSUB213PSZrb = 5661, X86_VFMSUB213PSZrbk = 5662, X86_VFMSUB213PSZrbkz = 5663, X86_VFMSUB213PSZrk = 5664, X86_VFMSUB213PSZrkz = 5665, X86_VFMSUB213PSm = 5666, X86_VFMSUB213PSr = 5667, X86_VFMSUB213SDZm = 5668, X86_VFMSUB213SDZm_Int = 5669, X86_VFMSUB213SDZm_Intk = 5670, X86_VFMSUB213SDZm_Intkz = 5671, X86_VFMSUB213SDZr = 5672, X86_VFMSUB213SDZr_Int = 5673, X86_VFMSUB213SDZr_Intk = 5674, X86_VFMSUB213SDZr_Intkz = 5675, X86_VFMSUB213SDZrb = 5676, X86_VFMSUB213SDZrb_Int = 5677, X86_VFMSUB213SDZrb_Intk = 5678, X86_VFMSUB213SDZrb_Intkz = 5679, X86_VFMSUB213SDm = 5680, X86_VFMSUB213SDm_Int = 5681, X86_VFMSUB213SDr = 5682, X86_VFMSUB213SDr_Int = 5683, X86_VFMSUB213SSZm = 5684, X86_VFMSUB213SSZm_Int = 5685, X86_VFMSUB213SSZm_Intk = 5686, X86_VFMSUB213SSZm_Intkz = 5687, X86_VFMSUB213SSZr = 5688, X86_VFMSUB213SSZr_Int = 5689, X86_VFMSUB213SSZr_Intk = 5690, X86_VFMSUB213SSZr_Intkz = 5691, X86_VFMSUB213SSZrb = 5692, X86_VFMSUB213SSZrb_Int = 5693, X86_VFMSUB213SSZrb_Intk = 5694, X86_VFMSUB213SSZrb_Intkz = 5695, X86_VFMSUB213SSm = 5696, X86_VFMSUB213SSm_Int = 5697, X86_VFMSUB213SSr = 5698, X86_VFMSUB213SSr_Int = 5699, X86_VFMSUB231PDYm = 5700, X86_VFMSUB231PDYr = 5701, X86_VFMSUB231PDZ128m = 5702, X86_VFMSUB231PDZ128mb = 5703, X86_VFMSUB231PDZ128mbk = 5704, X86_VFMSUB231PDZ128mbkz = 5705, X86_VFMSUB231PDZ128mk = 5706, X86_VFMSUB231PDZ128mkz = 5707, X86_VFMSUB231PDZ128r = 5708, X86_VFMSUB231PDZ128rk = 5709, X86_VFMSUB231PDZ128rkz = 5710, X86_VFMSUB231PDZ256m = 5711, X86_VFMSUB231PDZ256mb = 5712, X86_VFMSUB231PDZ256mbk = 5713, X86_VFMSUB231PDZ256mbkz = 5714, X86_VFMSUB231PDZ256mk = 5715, X86_VFMSUB231PDZ256mkz = 5716, X86_VFMSUB231PDZ256r = 5717, X86_VFMSUB231PDZ256rk = 5718, X86_VFMSUB231PDZ256rkz = 5719, X86_VFMSUB231PDZm = 5720, X86_VFMSUB231PDZmb = 5721, X86_VFMSUB231PDZmbk = 5722, X86_VFMSUB231PDZmbkz = 5723, X86_VFMSUB231PDZmk = 5724, X86_VFMSUB231PDZmkz = 5725, X86_VFMSUB231PDZr = 5726, X86_VFMSUB231PDZrb = 5727, X86_VFMSUB231PDZrbk = 5728, X86_VFMSUB231PDZrbkz = 5729, X86_VFMSUB231PDZrk = 5730, X86_VFMSUB231PDZrkz = 5731, X86_VFMSUB231PDm = 5732, X86_VFMSUB231PDr = 5733, X86_VFMSUB231PSYm = 5734, X86_VFMSUB231PSYr = 5735, X86_VFMSUB231PSZ128m = 5736, X86_VFMSUB231PSZ128mb = 5737, X86_VFMSUB231PSZ128mbk = 5738, X86_VFMSUB231PSZ128mbkz = 5739, X86_VFMSUB231PSZ128mk = 5740, X86_VFMSUB231PSZ128mkz = 5741, X86_VFMSUB231PSZ128r = 5742, X86_VFMSUB231PSZ128rk = 5743, X86_VFMSUB231PSZ128rkz = 5744, X86_VFMSUB231PSZ256m = 5745, X86_VFMSUB231PSZ256mb = 5746, X86_VFMSUB231PSZ256mbk = 5747, X86_VFMSUB231PSZ256mbkz = 5748, X86_VFMSUB231PSZ256mk = 5749, X86_VFMSUB231PSZ256mkz = 5750, X86_VFMSUB231PSZ256r = 5751, X86_VFMSUB231PSZ256rk = 5752, X86_VFMSUB231PSZ256rkz = 5753, X86_VFMSUB231PSZm = 5754, X86_VFMSUB231PSZmb = 5755, X86_VFMSUB231PSZmbk = 5756, X86_VFMSUB231PSZmbkz = 5757, X86_VFMSUB231PSZmk = 5758, X86_VFMSUB231PSZmkz = 5759, X86_VFMSUB231PSZr = 5760, X86_VFMSUB231PSZrb = 5761, X86_VFMSUB231PSZrbk = 5762, X86_VFMSUB231PSZrbkz = 5763, X86_VFMSUB231PSZrk = 5764, X86_VFMSUB231PSZrkz = 5765, X86_VFMSUB231PSm = 5766, X86_VFMSUB231PSr = 5767, X86_VFMSUB231SDZm = 5768, X86_VFMSUB231SDZm_Int = 5769, X86_VFMSUB231SDZm_Intk = 5770, X86_VFMSUB231SDZm_Intkz = 5771, X86_VFMSUB231SDZr = 5772, X86_VFMSUB231SDZr_Int = 5773, X86_VFMSUB231SDZr_Intk = 5774, X86_VFMSUB231SDZr_Intkz = 5775, X86_VFMSUB231SDZrb = 5776, X86_VFMSUB231SDZrb_Int = 5777, X86_VFMSUB231SDZrb_Intk = 5778, X86_VFMSUB231SDZrb_Intkz = 5779, X86_VFMSUB231SDm = 5780, X86_VFMSUB231SDm_Int = 5781, X86_VFMSUB231SDr = 5782, X86_VFMSUB231SDr_Int = 5783, X86_VFMSUB231SSZm = 5784, X86_VFMSUB231SSZm_Int = 5785, X86_VFMSUB231SSZm_Intk = 5786, X86_VFMSUB231SSZm_Intkz = 5787, X86_VFMSUB231SSZr = 5788, X86_VFMSUB231SSZr_Int = 5789, X86_VFMSUB231SSZr_Intk = 5790, X86_VFMSUB231SSZr_Intkz = 5791, X86_VFMSUB231SSZrb = 5792, X86_VFMSUB231SSZrb_Int = 5793, X86_VFMSUB231SSZrb_Intk = 5794, X86_VFMSUB231SSZrb_Intkz = 5795, X86_VFMSUB231SSm = 5796, X86_VFMSUB231SSm_Int = 5797, X86_VFMSUB231SSr = 5798, X86_VFMSUB231SSr_Int = 5799, X86_VFMSUBADD132PDYm = 5800, X86_VFMSUBADD132PDYr = 5801, X86_VFMSUBADD132PDZ128m = 5802, X86_VFMSUBADD132PDZ128mb = 5803, X86_VFMSUBADD132PDZ128mbk = 5804, X86_VFMSUBADD132PDZ128mbkz = 5805, X86_VFMSUBADD132PDZ128mk = 5806, X86_VFMSUBADD132PDZ128mkz = 5807, X86_VFMSUBADD132PDZ128r = 5808, X86_VFMSUBADD132PDZ128rk = 5809, X86_VFMSUBADD132PDZ128rkz = 5810, X86_VFMSUBADD132PDZ256m = 5811, X86_VFMSUBADD132PDZ256mb = 5812, X86_VFMSUBADD132PDZ256mbk = 5813, X86_VFMSUBADD132PDZ256mbkz = 5814, X86_VFMSUBADD132PDZ256mk = 5815, X86_VFMSUBADD132PDZ256mkz = 5816, X86_VFMSUBADD132PDZ256r = 5817, X86_VFMSUBADD132PDZ256rk = 5818, X86_VFMSUBADD132PDZ256rkz = 5819, X86_VFMSUBADD132PDZm = 5820, X86_VFMSUBADD132PDZmb = 5821, X86_VFMSUBADD132PDZmbk = 5822, X86_VFMSUBADD132PDZmbkz = 5823, X86_VFMSUBADD132PDZmk = 5824, X86_VFMSUBADD132PDZmkz = 5825, X86_VFMSUBADD132PDZr = 5826, X86_VFMSUBADD132PDZrb = 5827, X86_VFMSUBADD132PDZrbk = 5828, X86_VFMSUBADD132PDZrbkz = 5829, X86_VFMSUBADD132PDZrk = 5830, X86_VFMSUBADD132PDZrkz = 5831, X86_VFMSUBADD132PDm = 5832, X86_VFMSUBADD132PDr = 5833, X86_VFMSUBADD132PSYm = 5834, X86_VFMSUBADD132PSYr = 5835, X86_VFMSUBADD132PSZ128m = 5836, X86_VFMSUBADD132PSZ128mb = 5837, X86_VFMSUBADD132PSZ128mbk = 5838, X86_VFMSUBADD132PSZ128mbkz = 5839, X86_VFMSUBADD132PSZ128mk = 5840, X86_VFMSUBADD132PSZ128mkz = 5841, X86_VFMSUBADD132PSZ128r = 5842, X86_VFMSUBADD132PSZ128rk = 5843, X86_VFMSUBADD132PSZ128rkz = 5844, X86_VFMSUBADD132PSZ256m = 5845, X86_VFMSUBADD132PSZ256mb = 5846, X86_VFMSUBADD132PSZ256mbk = 5847, X86_VFMSUBADD132PSZ256mbkz = 5848, X86_VFMSUBADD132PSZ256mk = 5849, X86_VFMSUBADD132PSZ256mkz = 5850, X86_VFMSUBADD132PSZ256r = 5851, X86_VFMSUBADD132PSZ256rk = 5852, X86_VFMSUBADD132PSZ256rkz = 5853, X86_VFMSUBADD132PSZm = 5854, X86_VFMSUBADD132PSZmb = 5855, X86_VFMSUBADD132PSZmbk = 5856, X86_VFMSUBADD132PSZmbkz = 5857, X86_VFMSUBADD132PSZmk = 5858, X86_VFMSUBADD132PSZmkz = 5859, X86_VFMSUBADD132PSZr = 5860, X86_VFMSUBADD132PSZrb = 5861, X86_VFMSUBADD132PSZrbk = 5862, X86_VFMSUBADD132PSZrbkz = 5863, X86_VFMSUBADD132PSZrk = 5864, X86_VFMSUBADD132PSZrkz = 5865, X86_VFMSUBADD132PSm = 5866, X86_VFMSUBADD132PSr = 5867, X86_VFMSUBADD213PDYm = 5868, X86_VFMSUBADD213PDYr = 5869, X86_VFMSUBADD213PDZ128m = 5870, X86_VFMSUBADD213PDZ128mb = 5871, X86_VFMSUBADD213PDZ128mbk = 5872, X86_VFMSUBADD213PDZ128mbkz = 5873, X86_VFMSUBADD213PDZ128mk = 5874, X86_VFMSUBADD213PDZ128mkz = 5875, X86_VFMSUBADD213PDZ128r = 5876, X86_VFMSUBADD213PDZ128rk = 5877, X86_VFMSUBADD213PDZ128rkz = 5878, X86_VFMSUBADD213PDZ256m = 5879, X86_VFMSUBADD213PDZ256mb = 5880, X86_VFMSUBADD213PDZ256mbk = 5881, X86_VFMSUBADD213PDZ256mbkz = 5882, X86_VFMSUBADD213PDZ256mk = 5883, X86_VFMSUBADD213PDZ256mkz = 5884, X86_VFMSUBADD213PDZ256r = 5885, X86_VFMSUBADD213PDZ256rk = 5886, X86_VFMSUBADD213PDZ256rkz = 5887, X86_VFMSUBADD213PDZm = 5888, X86_VFMSUBADD213PDZmb = 5889, X86_VFMSUBADD213PDZmbk = 5890, X86_VFMSUBADD213PDZmbkz = 5891, X86_VFMSUBADD213PDZmk = 5892, X86_VFMSUBADD213PDZmkz = 5893, X86_VFMSUBADD213PDZr = 5894, X86_VFMSUBADD213PDZrb = 5895, X86_VFMSUBADD213PDZrbk = 5896, X86_VFMSUBADD213PDZrbkz = 5897, X86_VFMSUBADD213PDZrk = 5898, X86_VFMSUBADD213PDZrkz = 5899, X86_VFMSUBADD213PDm = 5900, X86_VFMSUBADD213PDr = 5901, X86_VFMSUBADD213PSYm = 5902, X86_VFMSUBADD213PSYr = 5903, X86_VFMSUBADD213PSZ128m = 5904, X86_VFMSUBADD213PSZ128mb = 5905, X86_VFMSUBADD213PSZ128mbk = 5906, X86_VFMSUBADD213PSZ128mbkz = 5907, X86_VFMSUBADD213PSZ128mk = 5908, X86_VFMSUBADD213PSZ128mkz = 5909, X86_VFMSUBADD213PSZ128r = 5910, X86_VFMSUBADD213PSZ128rk = 5911, X86_VFMSUBADD213PSZ128rkz = 5912, X86_VFMSUBADD213PSZ256m = 5913, X86_VFMSUBADD213PSZ256mb = 5914, X86_VFMSUBADD213PSZ256mbk = 5915, X86_VFMSUBADD213PSZ256mbkz = 5916, X86_VFMSUBADD213PSZ256mk = 5917, X86_VFMSUBADD213PSZ256mkz = 5918, X86_VFMSUBADD213PSZ256r = 5919, X86_VFMSUBADD213PSZ256rk = 5920, X86_VFMSUBADD213PSZ256rkz = 5921, X86_VFMSUBADD213PSZm = 5922, X86_VFMSUBADD213PSZmb = 5923, X86_VFMSUBADD213PSZmbk = 5924, X86_VFMSUBADD213PSZmbkz = 5925, X86_VFMSUBADD213PSZmk = 5926, X86_VFMSUBADD213PSZmkz = 5927, X86_VFMSUBADD213PSZr = 5928, X86_VFMSUBADD213PSZrb = 5929, X86_VFMSUBADD213PSZrbk = 5930, X86_VFMSUBADD213PSZrbkz = 5931, X86_VFMSUBADD213PSZrk = 5932, X86_VFMSUBADD213PSZrkz = 5933, X86_VFMSUBADD213PSm = 5934, X86_VFMSUBADD213PSr = 5935, X86_VFMSUBADD231PDYm = 5936, X86_VFMSUBADD231PDYr = 5937, X86_VFMSUBADD231PDZ128m = 5938, X86_VFMSUBADD231PDZ128mb = 5939, X86_VFMSUBADD231PDZ128mbk = 5940, X86_VFMSUBADD231PDZ128mbkz = 5941, X86_VFMSUBADD231PDZ128mk = 5942, X86_VFMSUBADD231PDZ128mkz = 5943, X86_VFMSUBADD231PDZ128r = 5944, X86_VFMSUBADD231PDZ128rk = 5945, X86_VFMSUBADD231PDZ128rkz = 5946, X86_VFMSUBADD231PDZ256m = 5947, X86_VFMSUBADD231PDZ256mb = 5948, X86_VFMSUBADD231PDZ256mbk = 5949, X86_VFMSUBADD231PDZ256mbkz = 5950, X86_VFMSUBADD231PDZ256mk = 5951, X86_VFMSUBADD231PDZ256mkz = 5952, X86_VFMSUBADD231PDZ256r = 5953, X86_VFMSUBADD231PDZ256rk = 5954, X86_VFMSUBADD231PDZ256rkz = 5955, X86_VFMSUBADD231PDZm = 5956, X86_VFMSUBADD231PDZmb = 5957, X86_VFMSUBADD231PDZmbk = 5958, X86_VFMSUBADD231PDZmbkz = 5959, X86_VFMSUBADD231PDZmk = 5960, X86_VFMSUBADD231PDZmkz = 5961, X86_VFMSUBADD231PDZr = 5962, X86_VFMSUBADD231PDZrb = 5963, X86_VFMSUBADD231PDZrbk = 5964, X86_VFMSUBADD231PDZrbkz = 5965, X86_VFMSUBADD231PDZrk = 5966, X86_VFMSUBADD231PDZrkz = 5967, X86_VFMSUBADD231PDm = 5968, X86_VFMSUBADD231PDr = 5969, X86_VFMSUBADD231PSYm = 5970, X86_VFMSUBADD231PSYr = 5971, X86_VFMSUBADD231PSZ128m = 5972, X86_VFMSUBADD231PSZ128mb = 5973, X86_VFMSUBADD231PSZ128mbk = 5974, X86_VFMSUBADD231PSZ128mbkz = 5975, X86_VFMSUBADD231PSZ128mk = 5976, X86_VFMSUBADD231PSZ128mkz = 5977, X86_VFMSUBADD231PSZ128r = 5978, X86_VFMSUBADD231PSZ128rk = 5979, X86_VFMSUBADD231PSZ128rkz = 5980, X86_VFMSUBADD231PSZ256m = 5981, X86_VFMSUBADD231PSZ256mb = 5982, X86_VFMSUBADD231PSZ256mbk = 5983, X86_VFMSUBADD231PSZ256mbkz = 5984, X86_VFMSUBADD231PSZ256mk = 5985, X86_VFMSUBADD231PSZ256mkz = 5986, X86_VFMSUBADD231PSZ256r = 5987, X86_VFMSUBADD231PSZ256rk = 5988, X86_VFMSUBADD231PSZ256rkz = 5989, X86_VFMSUBADD231PSZm = 5990, X86_VFMSUBADD231PSZmb = 5991, X86_VFMSUBADD231PSZmbk = 5992, X86_VFMSUBADD231PSZmbkz = 5993, X86_VFMSUBADD231PSZmk = 5994, X86_VFMSUBADD231PSZmkz = 5995, X86_VFMSUBADD231PSZr = 5996, X86_VFMSUBADD231PSZrb = 5997, X86_VFMSUBADD231PSZrbk = 5998, X86_VFMSUBADD231PSZrbkz = 5999, X86_VFMSUBADD231PSZrk = 6000, X86_VFMSUBADD231PSZrkz = 6001, X86_VFMSUBADD231PSm = 6002, X86_VFMSUBADD231PSr = 6003, X86_VFMSUBADDPD4Ymr = 6004, X86_VFMSUBADDPD4Yrm = 6005, X86_VFMSUBADDPD4Yrr = 6006, X86_VFMSUBADDPD4Yrr_REV = 6007, X86_VFMSUBADDPD4mr = 6008, X86_VFMSUBADDPD4rm = 6009, X86_VFMSUBADDPD4rr = 6010, X86_VFMSUBADDPD4rr_REV = 6011, X86_VFMSUBADDPS4Ymr = 6012, X86_VFMSUBADDPS4Yrm = 6013, X86_VFMSUBADDPS4Yrr = 6014, X86_VFMSUBADDPS4Yrr_REV = 6015, X86_VFMSUBADDPS4mr = 6016, X86_VFMSUBADDPS4rm = 6017, X86_VFMSUBADDPS4rr = 6018, X86_VFMSUBADDPS4rr_REV = 6019, X86_VFMSUBPD4Ymr = 6020, X86_VFMSUBPD4Yrm = 6021, X86_VFMSUBPD4Yrr = 6022, X86_VFMSUBPD4Yrr_REV = 6023, X86_VFMSUBPD4mr = 6024, X86_VFMSUBPD4rm = 6025, X86_VFMSUBPD4rr = 6026, X86_VFMSUBPD4rr_REV = 6027, X86_VFMSUBPS4Ymr = 6028, X86_VFMSUBPS4Yrm = 6029, X86_VFMSUBPS4Yrr = 6030, X86_VFMSUBPS4Yrr_REV = 6031, X86_VFMSUBPS4mr = 6032, X86_VFMSUBPS4rm = 6033, X86_VFMSUBPS4rr = 6034, X86_VFMSUBPS4rr_REV = 6035, X86_VFMSUBSD4mr = 6036, X86_VFMSUBSD4mr_Int = 6037, X86_VFMSUBSD4rm = 6038, X86_VFMSUBSD4rm_Int = 6039, X86_VFMSUBSD4rr = 6040, X86_VFMSUBSD4rr_Int = 6041, X86_VFMSUBSD4rr_Int_REV = 6042, X86_VFMSUBSD4rr_REV = 6043, X86_VFMSUBSS4mr = 6044, X86_VFMSUBSS4mr_Int = 6045, X86_VFMSUBSS4rm = 6046, X86_VFMSUBSS4rm_Int = 6047, X86_VFMSUBSS4rr = 6048, X86_VFMSUBSS4rr_Int = 6049, X86_VFMSUBSS4rr_Int_REV = 6050, X86_VFMSUBSS4rr_REV = 6051, X86_VFNMADD132PDYm = 6052, X86_VFNMADD132PDYr = 6053, X86_VFNMADD132PDZ128m = 6054, X86_VFNMADD132PDZ128mb = 6055, X86_VFNMADD132PDZ128mbk = 6056, X86_VFNMADD132PDZ128mbkz = 6057, X86_VFNMADD132PDZ128mk = 6058, X86_VFNMADD132PDZ128mkz = 6059, X86_VFNMADD132PDZ128r = 6060, X86_VFNMADD132PDZ128rk = 6061, X86_VFNMADD132PDZ128rkz = 6062, X86_VFNMADD132PDZ256m = 6063, X86_VFNMADD132PDZ256mb = 6064, X86_VFNMADD132PDZ256mbk = 6065, X86_VFNMADD132PDZ256mbkz = 6066, X86_VFNMADD132PDZ256mk = 6067, X86_VFNMADD132PDZ256mkz = 6068, X86_VFNMADD132PDZ256r = 6069, X86_VFNMADD132PDZ256rk = 6070, X86_VFNMADD132PDZ256rkz = 6071, X86_VFNMADD132PDZm = 6072, X86_VFNMADD132PDZmb = 6073, X86_VFNMADD132PDZmbk = 6074, X86_VFNMADD132PDZmbkz = 6075, X86_VFNMADD132PDZmk = 6076, X86_VFNMADD132PDZmkz = 6077, X86_VFNMADD132PDZr = 6078, X86_VFNMADD132PDZrb = 6079, X86_VFNMADD132PDZrbk = 6080, X86_VFNMADD132PDZrbkz = 6081, X86_VFNMADD132PDZrk = 6082, X86_VFNMADD132PDZrkz = 6083, X86_VFNMADD132PDm = 6084, X86_VFNMADD132PDr = 6085, X86_VFNMADD132PSYm = 6086, X86_VFNMADD132PSYr = 6087, X86_VFNMADD132PSZ128m = 6088, X86_VFNMADD132PSZ128mb = 6089, X86_VFNMADD132PSZ128mbk = 6090, X86_VFNMADD132PSZ128mbkz = 6091, X86_VFNMADD132PSZ128mk = 6092, X86_VFNMADD132PSZ128mkz = 6093, X86_VFNMADD132PSZ128r = 6094, X86_VFNMADD132PSZ128rk = 6095, X86_VFNMADD132PSZ128rkz = 6096, X86_VFNMADD132PSZ256m = 6097, X86_VFNMADD132PSZ256mb = 6098, X86_VFNMADD132PSZ256mbk = 6099, X86_VFNMADD132PSZ256mbkz = 6100, X86_VFNMADD132PSZ256mk = 6101, X86_VFNMADD132PSZ256mkz = 6102, X86_VFNMADD132PSZ256r = 6103, X86_VFNMADD132PSZ256rk = 6104, X86_VFNMADD132PSZ256rkz = 6105, X86_VFNMADD132PSZm = 6106, X86_VFNMADD132PSZmb = 6107, X86_VFNMADD132PSZmbk = 6108, X86_VFNMADD132PSZmbkz = 6109, X86_VFNMADD132PSZmk = 6110, X86_VFNMADD132PSZmkz = 6111, X86_VFNMADD132PSZr = 6112, X86_VFNMADD132PSZrb = 6113, X86_VFNMADD132PSZrbk = 6114, X86_VFNMADD132PSZrbkz = 6115, X86_VFNMADD132PSZrk = 6116, X86_VFNMADD132PSZrkz = 6117, X86_VFNMADD132PSm = 6118, X86_VFNMADD132PSr = 6119, X86_VFNMADD132SDZm = 6120, X86_VFNMADD132SDZm_Int = 6121, X86_VFNMADD132SDZm_Intk = 6122, X86_VFNMADD132SDZm_Intkz = 6123, X86_VFNMADD132SDZr = 6124, X86_VFNMADD132SDZr_Int = 6125, X86_VFNMADD132SDZr_Intk = 6126, X86_VFNMADD132SDZr_Intkz = 6127, X86_VFNMADD132SDZrb = 6128, X86_VFNMADD132SDZrb_Int = 6129, X86_VFNMADD132SDZrb_Intk = 6130, X86_VFNMADD132SDZrb_Intkz = 6131, X86_VFNMADD132SDm = 6132, X86_VFNMADD132SDm_Int = 6133, X86_VFNMADD132SDr = 6134, X86_VFNMADD132SDr_Int = 6135, X86_VFNMADD132SSZm = 6136, X86_VFNMADD132SSZm_Int = 6137, X86_VFNMADD132SSZm_Intk = 6138, X86_VFNMADD132SSZm_Intkz = 6139, X86_VFNMADD132SSZr = 6140, X86_VFNMADD132SSZr_Int = 6141, X86_VFNMADD132SSZr_Intk = 6142, X86_VFNMADD132SSZr_Intkz = 6143, X86_VFNMADD132SSZrb = 6144, X86_VFNMADD132SSZrb_Int = 6145, X86_VFNMADD132SSZrb_Intk = 6146, X86_VFNMADD132SSZrb_Intkz = 6147, X86_VFNMADD132SSm = 6148, X86_VFNMADD132SSm_Int = 6149, X86_VFNMADD132SSr = 6150, X86_VFNMADD132SSr_Int = 6151, X86_VFNMADD213PDYm = 6152, X86_VFNMADD213PDYr = 6153, X86_VFNMADD213PDZ128m = 6154, X86_VFNMADD213PDZ128mb = 6155, X86_VFNMADD213PDZ128mbk = 6156, X86_VFNMADD213PDZ128mbkz = 6157, X86_VFNMADD213PDZ128mk = 6158, X86_VFNMADD213PDZ128mkz = 6159, X86_VFNMADD213PDZ128r = 6160, X86_VFNMADD213PDZ128rk = 6161, X86_VFNMADD213PDZ128rkz = 6162, X86_VFNMADD213PDZ256m = 6163, X86_VFNMADD213PDZ256mb = 6164, X86_VFNMADD213PDZ256mbk = 6165, X86_VFNMADD213PDZ256mbkz = 6166, X86_VFNMADD213PDZ256mk = 6167, X86_VFNMADD213PDZ256mkz = 6168, X86_VFNMADD213PDZ256r = 6169, X86_VFNMADD213PDZ256rk = 6170, X86_VFNMADD213PDZ256rkz = 6171, X86_VFNMADD213PDZm = 6172, X86_VFNMADD213PDZmb = 6173, X86_VFNMADD213PDZmbk = 6174, X86_VFNMADD213PDZmbkz = 6175, X86_VFNMADD213PDZmk = 6176, X86_VFNMADD213PDZmkz = 6177, X86_VFNMADD213PDZr = 6178, X86_VFNMADD213PDZrb = 6179, X86_VFNMADD213PDZrbk = 6180, X86_VFNMADD213PDZrbkz = 6181, X86_VFNMADD213PDZrk = 6182, X86_VFNMADD213PDZrkz = 6183, X86_VFNMADD213PDm = 6184, X86_VFNMADD213PDr = 6185, X86_VFNMADD213PSYm = 6186, X86_VFNMADD213PSYr = 6187, X86_VFNMADD213PSZ128m = 6188, X86_VFNMADD213PSZ128mb = 6189, X86_VFNMADD213PSZ128mbk = 6190, X86_VFNMADD213PSZ128mbkz = 6191, X86_VFNMADD213PSZ128mk = 6192, X86_VFNMADD213PSZ128mkz = 6193, X86_VFNMADD213PSZ128r = 6194, X86_VFNMADD213PSZ128rk = 6195, X86_VFNMADD213PSZ128rkz = 6196, X86_VFNMADD213PSZ256m = 6197, X86_VFNMADD213PSZ256mb = 6198, X86_VFNMADD213PSZ256mbk = 6199, X86_VFNMADD213PSZ256mbkz = 6200, X86_VFNMADD213PSZ256mk = 6201, X86_VFNMADD213PSZ256mkz = 6202, X86_VFNMADD213PSZ256r = 6203, X86_VFNMADD213PSZ256rk = 6204, X86_VFNMADD213PSZ256rkz = 6205, X86_VFNMADD213PSZm = 6206, X86_VFNMADD213PSZmb = 6207, X86_VFNMADD213PSZmbk = 6208, X86_VFNMADD213PSZmbkz = 6209, X86_VFNMADD213PSZmk = 6210, X86_VFNMADD213PSZmkz = 6211, X86_VFNMADD213PSZr = 6212, X86_VFNMADD213PSZrb = 6213, X86_VFNMADD213PSZrbk = 6214, X86_VFNMADD213PSZrbkz = 6215, X86_VFNMADD213PSZrk = 6216, X86_VFNMADD213PSZrkz = 6217, X86_VFNMADD213PSm = 6218, X86_VFNMADD213PSr = 6219, X86_VFNMADD213SDZm = 6220, X86_VFNMADD213SDZm_Int = 6221, X86_VFNMADD213SDZm_Intk = 6222, X86_VFNMADD213SDZm_Intkz = 6223, X86_VFNMADD213SDZr = 6224, X86_VFNMADD213SDZr_Int = 6225, X86_VFNMADD213SDZr_Intk = 6226, X86_VFNMADD213SDZr_Intkz = 6227, X86_VFNMADD213SDZrb = 6228, X86_VFNMADD213SDZrb_Int = 6229, X86_VFNMADD213SDZrb_Intk = 6230, X86_VFNMADD213SDZrb_Intkz = 6231, X86_VFNMADD213SDm = 6232, X86_VFNMADD213SDm_Int = 6233, X86_VFNMADD213SDr = 6234, X86_VFNMADD213SDr_Int = 6235, X86_VFNMADD213SSZm = 6236, X86_VFNMADD213SSZm_Int = 6237, X86_VFNMADD213SSZm_Intk = 6238, X86_VFNMADD213SSZm_Intkz = 6239, X86_VFNMADD213SSZr = 6240, X86_VFNMADD213SSZr_Int = 6241, X86_VFNMADD213SSZr_Intk = 6242, X86_VFNMADD213SSZr_Intkz = 6243, X86_VFNMADD213SSZrb = 6244, X86_VFNMADD213SSZrb_Int = 6245, X86_VFNMADD213SSZrb_Intk = 6246, X86_VFNMADD213SSZrb_Intkz = 6247, X86_VFNMADD213SSm = 6248, X86_VFNMADD213SSm_Int = 6249, X86_VFNMADD213SSr = 6250, X86_VFNMADD213SSr_Int = 6251, X86_VFNMADD231PDYm = 6252, X86_VFNMADD231PDYr = 6253, X86_VFNMADD231PDZ128m = 6254, X86_VFNMADD231PDZ128mb = 6255, X86_VFNMADD231PDZ128mbk = 6256, X86_VFNMADD231PDZ128mbkz = 6257, X86_VFNMADD231PDZ128mk = 6258, X86_VFNMADD231PDZ128mkz = 6259, X86_VFNMADD231PDZ128r = 6260, X86_VFNMADD231PDZ128rk = 6261, X86_VFNMADD231PDZ128rkz = 6262, X86_VFNMADD231PDZ256m = 6263, X86_VFNMADD231PDZ256mb = 6264, X86_VFNMADD231PDZ256mbk = 6265, X86_VFNMADD231PDZ256mbkz = 6266, X86_VFNMADD231PDZ256mk = 6267, X86_VFNMADD231PDZ256mkz = 6268, X86_VFNMADD231PDZ256r = 6269, X86_VFNMADD231PDZ256rk = 6270, X86_VFNMADD231PDZ256rkz = 6271, X86_VFNMADD231PDZm = 6272, X86_VFNMADD231PDZmb = 6273, X86_VFNMADD231PDZmbk = 6274, X86_VFNMADD231PDZmbkz = 6275, X86_VFNMADD231PDZmk = 6276, X86_VFNMADD231PDZmkz = 6277, X86_VFNMADD231PDZr = 6278, X86_VFNMADD231PDZrb = 6279, X86_VFNMADD231PDZrbk = 6280, X86_VFNMADD231PDZrbkz = 6281, X86_VFNMADD231PDZrk = 6282, X86_VFNMADD231PDZrkz = 6283, X86_VFNMADD231PDm = 6284, X86_VFNMADD231PDr = 6285, X86_VFNMADD231PSYm = 6286, X86_VFNMADD231PSYr = 6287, X86_VFNMADD231PSZ128m = 6288, X86_VFNMADD231PSZ128mb = 6289, X86_VFNMADD231PSZ128mbk = 6290, X86_VFNMADD231PSZ128mbkz = 6291, X86_VFNMADD231PSZ128mk = 6292, X86_VFNMADD231PSZ128mkz = 6293, X86_VFNMADD231PSZ128r = 6294, X86_VFNMADD231PSZ128rk = 6295, X86_VFNMADD231PSZ128rkz = 6296, X86_VFNMADD231PSZ256m = 6297, X86_VFNMADD231PSZ256mb = 6298, X86_VFNMADD231PSZ256mbk = 6299, X86_VFNMADD231PSZ256mbkz = 6300, X86_VFNMADD231PSZ256mk = 6301, X86_VFNMADD231PSZ256mkz = 6302, X86_VFNMADD231PSZ256r = 6303, X86_VFNMADD231PSZ256rk = 6304, X86_VFNMADD231PSZ256rkz = 6305, X86_VFNMADD231PSZm = 6306, X86_VFNMADD231PSZmb = 6307, X86_VFNMADD231PSZmbk = 6308, X86_VFNMADD231PSZmbkz = 6309, X86_VFNMADD231PSZmk = 6310, X86_VFNMADD231PSZmkz = 6311, X86_VFNMADD231PSZr = 6312, X86_VFNMADD231PSZrb = 6313, X86_VFNMADD231PSZrbk = 6314, X86_VFNMADD231PSZrbkz = 6315, X86_VFNMADD231PSZrk = 6316, X86_VFNMADD231PSZrkz = 6317, X86_VFNMADD231PSm = 6318, X86_VFNMADD231PSr = 6319, X86_VFNMADD231SDZm = 6320, X86_VFNMADD231SDZm_Int = 6321, X86_VFNMADD231SDZm_Intk = 6322, X86_VFNMADD231SDZm_Intkz = 6323, X86_VFNMADD231SDZr = 6324, X86_VFNMADD231SDZr_Int = 6325, X86_VFNMADD231SDZr_Intk = 6326, X86_VFNMADD231SDZr_Intkz = 6327, X86_VFNMADD231SDZrb = 6328, X86_VFNMADD231SDZrb_Int = 6329, X86_VFNMADD231SDZrb_Intk = 6330, X86_VFNMADD231SDZrb_Intkz = 6331, X86_VFNMADD231SDm = 6332, X86_VFNMADD231SDm_Int = 6333, X86_VFNMADD231SDr = 6334, X86_VFNMADD231SDr_Int = 6335, X86_VFNMADD231SSZm = 6336, X86_VFNMADD231SSZm_Int = 6337, X86_VFNMADD231SSZm_Intk = 6338, X86_VFNMADD231SSZm_Intkz = 6339, X86_VFNMADD231SSZr = 6340, X86_VFNMADD231SSZr_Int = 6341, X86_VFNMADD231SSZr_Intk = 6342, X86_VFNMADD231SSZr_Intkz = 6343, X86_VFNMADD231SSZrb = 6344, X86_VFNMADD231SSZrb_Int = 6345, X86_VFNMADD231SSZrb_Intk = 6346, X86_VFNMADD231SSZrb_Intkz = 6347, X86_VFNMADD231SSm = 6348, X86_VFNMADD231SSm_Int = 6349, X86_VFNMADD231SSr = 6350, X86_VFNMADD231SSr_Int = 6351, X86_VFNMADDPD4Ymr = 6352, X86_VFNMADDPD4Yrm = 6353, X86_VFNMADDPD4Yrr = 6354, X86_VFNMADDPD4Yrr_REV = 6355, X86_VFNMADDPD4mr = 6356, X86_VFNMADDPD4rm = 6357, X86_VFNMADDPD4rr = 6358, X86_VFNMADDPD4rr_REV = 6359, X86_VFNMADDPS4Ymr = 6360, X86_VFNMADDPS4Yrm = 6361, X86_VFNMADDPS4Yrr = 6362, X86_VFNMADDPS4Yrr_REV = 6363, X86_VFNMADDPS4mr = 6364, X86_VFNMADDPS4rm = 6365, X86_VFNMADDPS4rr = 6366, X86_VFNMADDPS4rr_REV = 6367, X86_VFNMADDSD4mr = 6368, X86_VFNMADDSD4mr_Int = 6369, X86_VFNMADDSD4rm = 6370, X86_VFNMADDSD4rm_Int = 6371, X86_VFNMADDSD4rr = 6372, X86_VFNMADDSD4rr_Int = 6373, X86_VFNMADDSD4rr_Int_REV = 6374, X86_VFNMADDSD4rr_REV = 6375, X86_VFNMADDSS4mr = 6376, X86_VFNMADDSS4mr_Int = 6377, X86_VFNMADDSS4rm = 6378, X86_VFNMADDSS4rm_Int = 6379, X86_VFNMADDSS4rr = 6380, X86_VFNMADDSS4rr_Int = 6381, X86_VFNMADDSS4rr_Int_REV = 6382, X86_VFNMADDSS4rr_REV = 6383, X86_VFNMSUB132PDYm = 6384, X86_VFNMSUB132PDYr = 6385, X86_VFNMSUB132PDZ128m = 6386, X86_VFNMSUB132PDZ128mb = 6387, X86_VFNMSUB132PDZ128mbk = 6388, X86_VFNMSUB132PDZ128mbkz = 6389, X86_VFNMSUB132PDZ128mk = 6390, X86_VFNMSUB132PDZ128mkz = 6391, X86_VFNMSUB132PDZ128r = 6392, X86_VFNMSUB132PDZ128rk = 6393, X86_VFNMSUB132PDZ128rkz = 6394, X86_VFNMSUB132PDZ256m = 6395, X86_VFNMSUB132PDZ256mb = 6396, X86_VFNMSUB132PDZ256mbk = 6397, X86_VFNMSUB132PDZ256mbkz = 6398, X86_VFNMSUB132PDZ256mk = 6399, X86_VFNMSUB132PDZ256mkz = 6400, X86_VFNMSUB132PDZ256r = 6401, X86_VFNMSUB132PDZ256rk = 6402, X86_VFNMSUB132PDZ256rkz = 6403, X86_VFNMSUB132PDZm = 6404, X86_VFNMSUB132PDZmb = 6405, X86_VFNMSUB132PDZmbk = 6406, X86_VFNMSUB132PDZmbkz = 6407, X86_VFNMSUB132PDZmk = 6408, X86_VFNMSUB132PDZmkz = 6409, X86_VFNMSUB132PDZr = 6410, X86_VFNMSUB132PDZrb = 6411, X86_VFNMSUB132PDZrbk = 6412, X86_VFNMSUB132PDZrbkz = 6413, X86_VFNMSUB132PDZrk = 6414, X86_VFNMSUB132PDZrkz = 6415, X86_VFNMSUB132PDm = 6416, X86_VFNMSUB132PDr = 6417, X86_VFNMSUB132PSYm = 6418, X86_VFNMSUB132PSYr = 6419, X86_VFNMSUB132PSZ128m = 6420, X86_VFNMSUB132PSZ128mb = 6421, X86_VFNMSUB132PSZ128mbk = 6422, X86_VFNMSUB132PSZ128mbkz = 6423, X86_VFNMSUB132PSZ128mk = 6424, X86_VFNMSUB132PSZ128mkz = 6425, X86_VFNMSUB132PSZ128r = 6426, X86_VFNMSUB132PSZ128rk = 6427, X86_VFNMSUB132PSZ128rkz = 6428, X86_VFNMSUB132PSZ256m = 6429, X86_VFNMSUB132PSZ256mb = 6430, X86_VFNMSUB132PSZ256mbk = 6431, X86_VFNMSUB132PSZ256mbkz = 6432, X86_VFNMSUB132PSZ256mk = 6433, X86_VFNMSUB132PSZ256mkz = 6434, X86_VFNMSUB132PSZ256r = 6435, X86_VFNMSUB132PSZ256rk = 6436, X86_VFNMSUB132PSZ256rkz = 6437, X86_VFNMSUB132PSZm = 6438, X86_VFNMSUB132PSZmb = 6439, X86_VFNMSUB132PSZmbk = 6440, X86_VFNMSUB132PSZmbkz = 6441, X86_VFNMSUB132PSZmk = 6442, X86_VFNMSUB132PSZmkz = 6443, X86_VFNMSUB132PSZr = 6444, X86_VFNMSUB132PSZrb = 6445, X86_VFNMSUB132PSZrbk = 6446, X86_VFNMSUB132PSZrbkz = 6447, X86_VFNMSUB132PSZrk = 6448, X86_VFNMSUB132PSZrkz = 6449, X86_VFNMSUB132PSm = 6450, X86_VFNMSUB132PSr = 6451, X86_VFNMSUB132SDZm = 6452, X86_VFNMSUB132SDZm_Int = 6453, X86_VFNMSUB132SDZm_Intk = 6454, X86_VFNMSUB132SDZm_Intkz = 6455, X86_VFNMSUB132SDZr = 6456, X86_VFNMSUB132SDZr_Int = 6457, X86_VFNMSUB132SDZr_Intk = 6458, X86_VFNMSUB132SDZr_Intkz = 6459, X86_VFNMSUB132SDZrb = 6460, X86_VFNMSUB132SDZrb_Int = 6461, X86_VFNMSUB132SDZrb_Intk = 6462, X86_VFNMSUB132SDZrb_Intkz = 6463, X86_VFNMSUB132SDm = 6464, X86_VFNMSUB132SDm_Int = 6465, X86_VFNMSUB132SDr = 6466, X86_VFNMSUB132SDr_Int = 6467, X86_VFNMSUB132SSZm = 6468, X86_VFNMSUB132SSZm_Int = 6469, X86_VFNMSUB132SSZm_Intk = 6470, X86_VFNMSUB132SSZm_Intkz = 6471, X86_VFNMSUB132SSZr = 6472, X86_VFNMSUB132SSZr_Int = 6473, X86_VFNMSUB132SSZr_Intk = 6474, X86_VFNMSUB132SSZr_Intkz = 6475, X86_VFNMSUB132SSZrb = 6476, X86_VFNMSUB132SSZrb_Int = 6477, X86_VFNMSUB132SSZrb_Intk = 6478, X86_VFNMSUB132SSZrb_Intkz = 6479, X86_VFNMSUB132SSm = 6480, X86_VFNMSUB132SSm_Int = 6481, X86_VFNMSUB132SSr = 6482, X86_VFNMSUB132SSr_Int = 6483, X86_VFNMSUB213PDYm = 6484, X86_VFNMSUB213PDYr = 6485, X86_VFNMSUB213PDZ128m = 6486, X86_VFNMSUB213PDZ128mb = 6487, X86_VFNMSUB213PDZ128mbk = 6488, X86_VFNMSUB213PDZ128mbkz = 6489, X86_VFNMSUB213PDZ128mk = 6490, X86_VFNMSUB213PDZ128mkz = 6491, X86_VFNMSUB213PDZ128r = 6492, X86_VFNMSUB213PDZ128rk = 6493, X86_VFNMSUB213PDZ128rkz = 6494, X86_VFNMSUB213PDZ256m = 6495, X86_VFNMSUB213PDZ256mb = 6496, X86_VFNMSUB213PDZ256mbk = 6497, X86_VFNMSUB213PDZ256mbkz = 6498, X86_VFNMSUB213PDZ256mk = 6499, X86_VFNMSUB213PDZ256mkz = 6500, X86_VFNMSUB213PDZ256r = 6501, X86_VFNMSUB213PDZ256rk = 6502, X86_VFNMSUB213PDZ256rkz = 6503, X86_VFNMSUB213PDZm = 6504, X86_VFNMSUB213PDZmb = 6505, X86_VFNMSUB213PDZmbk = 6506, X86_VFNMSUB213PDZmbkz = 6507, X86_VFNMSUB213PDZmk = 6508, X86_VFNMSUB213PDZmkz = 6509, X86_VFNMSUB213PDZr = 6510, X86_VFNMSUB213PDZrb = 6511, X86_VFNMSUB213PDZrbk = 6512, X86_VFNMSUB213PDZrbkz = 6513, X86_VFNMSUB213PDZrk = 6514, X86_VFNMSUB213PDZrkz = 6515, X86_VFNMSUB213PDm = 6516, X86_VFNMSUB213PDr = 6517, X86_VFNMSUB213PSYm = 6518, X86_VFNMSUB213PSYr = 6519, X86_VFNMSUB213PSZ128m = 6520, X86_VFNMSUB213PSZ128mb = 6521, X86_VFNMSUB213PSZ128mbk = 6522, X86_VFNMSUB213PSZ128mbkz = 6523, X86_VFNMSUB213PSZ128mk = 6524, X86_VFNMSUB213PSZ128mkz = 6525, X86_VFNMSUB213PSZ128r = 6526, X86_VFNMSUB213PSZ128rk = 6527, X86_VFNMSUB213PSZ128rkz = 6528, X86_VFNMSUB213PSZ256m = 6529, X86_VFNMSUB213PSZ256mb = 6530, X86_VFNMSUB213PSZ256mbk = 6531, X86_VFNMSUB213PSZ256mbkz = 6532, X86_VFNMSUB213PSZ256mk = 6533, X86_VFNMSUB213PSZ256mkz = 6534, X86_VFNMSUB213PSZ256r = 6535, X86_VFNMSUB213PSZ256rk = 6536, X86_VFNMSUB213PSZ256rkz = 6537, X86_VFNMSUB213PSZm = 6538, X86_VFNMSUB213PSZmb = 6539, X86_VFNMSUB213PSZmbk = 6540, X86_VFNMSUB213PSZmbkz = 6541, X86_VFNMSUB213PSZmk = 6542, X86_VFNMSUB213PSZmkz = 6543, X86_VFNMSUB213PSZr = 6544, X86_VFNMSUB213PSZrb = 6545, X86_VFNMSUB213PSZrbk = 6546, X86_VFNMSUB213PSZrbkz = 6547, X86_VFNMSUB213PSZrk = 6548, X86_VFNMSUB213PSZrkz = 6549, X86_VFNMSUB213PSm = 6550, X86_VFNMSUB213PSr = 6551, X86_VFNMSUB213SDZm = 6552, X86_VFNMSUB213SDZm_Int = 6553, X86_VFNMSUB213SDZm_Intk = 6554, X86_VFNMSUB213SDZm_Intkz = 6555, X86_VFNMSUB213SDZr = 6556, X86_VFNMSUB213SDZr_Int = 6557, X86_VFNMSUB213SDZr_Intk = 6558, X86_VFNMSUB213SDZr_Intkz = 6559, X86_VFNMSUB213SDZrb = 6560, X86_VFNMSUB213SDZrb_Int = 6561, X86_VFNMSUB213SDZrb_Intk = 6562, X86_VFNMSUB213SDZrb_Intkz = 6563, X86_VFNMSUB213SDm = 6564, X86_VFNMSUB213SDm_Int = 6565, X86_VFNMSUB213SDr = 6566, X86_VFNMSUB213SDr_Int = 6567, X86_VFNMSUB213SSZm = 6568, X86_VFNMSUB213SSZm_Int = 6569, X86_VFNMSUB213SSZm_Intk = 6570, X86_VFNMSUB213SSZm_Intkz = 6571, X86_VFNMSUB213SSZr = 6572, X86_VFNMSUB213SSZr_Int = 6573, X86_VFNMSUB213SSZr_Intk = 6574, X86_VFNMSUB213SSZr_Intkz = 6575, X86_VFNMSUB213SSZrb = 6576, X86_VFNMSUB213SSZrb_Int = 6577, X86_VFNMSUB213SSZrb_Intk = 6578, X86_VFNMSUB213SSZrb_Intkz = 6579, X86_VFNMSUB213SSm = 6580, X86_VFNMSUB213SSm_Int = 6581, X86_VFNMSUB213SSr = 6582, X86_VFNMSUB213SSr_Int = 6583, X86_VFNMSUB231PDYm = 6584, X86_VFNMSUB231PDYr = 6585, X86_VFNMSUB231PDZ128m = 6586, X86_VFNMSUB231PDZ128mb = 6587, X86_VFNMSUB231PDZ128mbk = 6588, X86_VFNMSUB231PDZ128mbkz = 6589, X86_VFNMSUB231PDZ128mk = 6590, X86_VFNMSUB231PDZ128mkz = 6591, X86_VFNMSUB231PDZ128r = 6592, X86_VFNMSUB231PDZ128rk = 6593, X86_VFNMSUB231PDZ128rkz = 6594, X86_VFNMSUB231PDZ256m = 6595, X86_VFNMSUB231PDZ256mb = 6596, X86_VFNMSUB231PDZ256mbk = 6597, X86_VFNMSUB231PDZ256mbkz = 6598, X86_VFNMSUB231PDZ256mk = 6599, X86_VFNMSUB231PDZ256mkz = 6600, X86_VFNMSUB231PDZ256r = 6601, X86_VFNMSUB231PDZ256rk = 6602, X86_VFNMSUB231PDZ256rkz = 6603, X86_VFNMSUB231PDZm = 6604, X86_VFNMSUB231PDZmb = 6605, X86_VFNMSUB231PDZmbk = 6606, X86_VFNMSUB231PDZmbkz = 6607, X86_VFNMSUB231PDZmk = 6608, X86_VFNMSUB231PDZmkz = 6609, X86_VFNMSUB231PDZr = 6610, X86_VFNMSUB231PDZrb = 6611, X86_VFNMSUB231PDZrbk = 6612, X86_VFNMSUB231PDZrbkz = 6613, X86_VFNMSUB231PDZrk = 6614, X86_VFNMSUB231PDZrkz = 6615, X86_VFNMSUB231PDm = 6616, X86_VFNMSUB231PDr = 6617, X86_VFNMSUB231PSYm = 6618, X86_VFNMSUB231PSYr = 6619, X86_VFNMSUB231PSZ128m = 6620, X86_VFNMSUB231PSZ128mb = 6621, X86_VFNMSUB231PSZ128mbk = 6622, X86_VFNMSUB231PSZ128mbkz = 6623, X86_VFNMSUB231PSZ128mk = 6624, X86_VFNMSUB231PSZ128mkz = 6625, X86_VFNMSUB231PSZ128r = 6626, X86_VFNMSUB231PSZ128rk = 6627, X86_VFNMSUB231PSZ128rkz = 6628, X86_VFNMSUB231PSZ256m = 6629, X86_VFNMSUB231PSZ256mb = 6630, X86_VFNMSUB231PSZ256mbk = 6631, X86_VFNMSUB231PSZ256mbkz = 6632, X86_VFNMSUB231PSZ256mk = 6633, X86_VFNMSUB231PSZ256mkz = 6634, X86_VFNMSUB231PSZ256r = 6635, X86_VFNMSUB231PSZ256rk = 6636, X86_VFNMSUB231PSZ256rkz = 6637, X86_VFNMSUB231PSZm = 6638, X86_VFNMSUB231PSZmb = 6639, X86_VFNMSUB231PSZmbk = 6640, X86_VFNMSUB231PSZmbkz = 6641, X86_VFNMSUB231PSZmk = 6642, X86_VFNMSUB231PSZmkz = 6643, X86_VFNMSUB231PSZr = 6644, X86_VFNMSUB231PSZrb = 6645, X86_VFNMSUB231PSZrbk = 6646, X86_VFNMSUB231PSZrbkz = 6647, X86_VFNMSUB231PSZrk = 6648, X86_VFNMSUB231PSZrkz = 6649, X86_VFNMSUB231PSm = 6650, X86_VFNMSUB231PSr = 6651, X86_VFNMSUB231SDZm = 6652, X86_VFNMSUB231SDZm_Int = 6653, X86_VFNMSUB231SDZm_Intk = 6654, X86_VFNMSUB231SDZm_Intkz = 6655, X86_VFNMSUB231SDZr = 6656, X86_VFNMSUB231SDZr_Int = 6657, X86_VFNMSUB231SDZr_Intk = 6658, X86_VFNMSUB231SDZr_Intkz = 6659, X86_VFNMSUB231SDZrb = 6660, X86_VFNMSUB231SDZrb_Int = 6661, X86_VFNMSUB231SDZrb_Intk = 6662, X86_VFNMSUB231SDZrb_Intkz = 6663, X86_VFNMSUB231SDm = 6664, X86_VFNMSUB231SDm_Int = 6665, X86_VFNMSUB231SDr = 6666, X86_VFNMSUB231SDr_Int = 6667, X86_VFNMSUB231SSZm = 6668, X86_VFNMSUB231SSZm_Int = 6669, X86_VFNMSUB231SSZm_Intk = 6670, X86_VFNMSUB231SSZm_Intkz = 6671, X86_VFNMSUB231SSZr = 6672, X86_VFNMSUB231SSZr_Int = 6673, X86_VFNMSUB231SSZr_Intk = 6674, X86_VFNMSUB231SSZr_Intkz = 6675, X86_VFNMSUB231SSZrb = 6676, X86_VFNMSUB231SSZrb_Int = 6677, X86_VFNMSUB231SSZrb_Intk = 6678, X86_VFNMSUB231SSZrb_Intkz = 6679, X86_VFNMSUB231SSm = 6680, X86_VFNMSUB231SSm_Int = 6681, X86_VFNMSUB231SSr = 6682, X86_VFNMSUB231SSr_Int = 6683, X86_VFNMSUBPD4Ymr = 6684, X86_VFNMSUBPD4Yrm = 6685, X86_VFNMSUBPD4Yrr = 6686, X86_VFNMSUBPD4Yrr_REV = 6687, X86_VFNMSUBPD4mr = 6688, X86_VFNMSUBPD4rm = 6689, X86_VFNMSUBPD4rr = 6690, X86_VFNMSUBPD4rr_REV = 6691, X86_VFNMSUBPS4Ymr = 6692, X86_VFNMSUBPS4Yrm = 6693, X86_VFNMSUBPS4Yrr = 6694, X86_VFNMSUBPS4Yrr_REV = 6695, X86_VFNMSUBPS4mr = 6696, X86_VFNMSUBPS4rm = 6697, X86_VFNMSUBPS4rr = 6698, X86_VFNMSUBPS4rr_REV = 6699, X86_VFNMSUBSD4mr = 6700, X86_VFNMSUBSD4mr_Int = 6701, X86_VFNMSUBSD4rm = 6702, X86_VFNMSUBSD4rm_Int = 6703, X86_VFNMSUBSD4rr = 6704, X86_VFNMSUBSD4rr_Int = 6705, X86_VFNMSUBSD4rr_Int_REV = 6706, X86_VFNMSUBSD4rr_REV = 6707, X86_VFNMSUBSS4mr = 6708, X86_VFNMSUBSS4mr_Int = 6709, X86_VFNMSUBSS4rm = 6710, X86_VFNMSUBSS4rm_Int = 6711, X86_VFNMSUBSS4rr = 6712, X86_VFNMSUBSS4rr_Int = 6713, X86_VFNMSUBSS4rr_Int_REV = 6714, X86_VFNMSUBSS4rr_REV = 6715, X86_VFPCLASSPDZ128rm = 6716, X86_VFPCLASSPDZ128rmb = 6717, X86_VFPCLASSPDZ128rmbk = 6718, X86_VFPCLASSPDZ128rmk = 6719, X86_VFPCLASSPDZ128rr = 6720, X86_VFPCLASSPDZ128rrk = 6721, X86_VFPCLASSPDZ256rm = 6722, X86_VFPCLASSPDZ256rmb = 6723, X86_VFPCLASSPDZ256rmbk = 6724, X86_VFPCLASSPDZ256rmk = 6725, X86_VFPCLASSPDZ256rr = 6726, X86_VFPCLASSPDZ256rrk = 6727, X86_VFPCLASSPDZrm = 6728, X86_VFPCLASSPDZrmb = 6729, X86_VFPCLASSPDZrmbk = 6730, X86_VFPCLASSPDZrmk = 6731, X86_VFPCLASSPDZrr = 6732, X86_VFPCLASSPDZrrk = 6733, X86_VFPCLASSPSZ128rm = 6734, X86_VFPCLASSPSZ128rmb = 6735, X86_VFPCLASSPSZ128rmbk = 6736, X86_VFPCLASSPSZ128rmk = 6737, X86_VFPCLASSPSZ128rr = 6738, X86_VFPCLASSPSZ128rrk = 6739, X86_VFPCLASSPSZ256rm = 6740, X86_VFPCLASSPSZ256rmb = 6741, X86_VFPCLASSPSZ256rmbk = 6742, X86_VFPCLASSPSZ256rmk = 6743, X86_VFPCLASSPSZ256rr = 6744, X86_VFPCLASSPSZ256rrk = 6745, X86_VFPCLASSPSZrm = 6746, X86_VFPCLASSPSZrmb = 6747, X86_VFPCLASSPSZrmbk = 6748, X86_VFPCLASSPSZrmk = 6749, X86_VFPCLASSPSZrr = 6750, X86_VFPCLASSPSZrrk = 6751, X86_VFPCLASSSDZrm = 6752, X86_VFPCLASSSDZrmk = 6753, X86_VFPCLASSSDZrr = 6754, X86_VFPCLASSSDZrrk = 6755, X86_VFPCLASSSSZrm = 6756, X86_VFPCLASSSSZrmk = 6757, X86_VFPCLASSSSZrr = 6758, X86_VFPCLASSSSZrrk = 6759, X86_VFRCZPDYrm = 6760, X86_VFRCZPDYrr = 6761, X86_VFRCZPDrm = 6762, X86_VFRCZPDrr = 6763, X86_VFRCZPSYrm = 6764, X86_VFRCZPSYrr = 6765, X86_VFRCZPSrm = 6766, X86_VFRCZPSrr = 6767, X86_VFRCZSDrm = 6768, X86_VFRCZSDrr = 6769, X86_VFRCZSSrm = 6770, X86_VFRCZSSrr = 6771, X86_VGATHERDPDYrm = 6772, X86_VGATHERDPDZ128rm = 6773, X86_VGATHERDPDZ256rm = 6774, X86_VGATHERDPDZrm = 6775, X86_VGATHERDPDrm = 6776, X86_VGATHERDPSYrm = 6777, X86_VGATHERDPSZ128rm = 6778, X86_VGATHERDPSZ256rm = 6779, X86_VGATHERDPSZrm = 6780, X86_VGATHERDPSrm = 6781, X86_VGATHERPF0DPDm = 6782, X86_VGATHERPF0DPSm = 6783, X86_VGATHERPF0QPDm = 6784, X86_VGATHERPF0QPSm = 6785, X86_VGATHERPF1DPDm = 6786, X86_VGATHERPF1DPSm = 6787, X86_VGATHERPF1QPDm = 6788, X86_VGATHERPF1QPSm = 6789, X86_VGATHERQPDYrm = 6790, X86_VGATHERQPDZ128rm = 6791, X86_VGATHERQPDZ256rm = 6792, X86_VGATHERQPDZrm = 6793, X86_VGATHERQPDrm = 6794, X86_VGATHERQPSYrm = 6795, X86_VGATHERQPSZ128rm = 6796, X86_VGATHERQPSZ256rm = 6797, X86_VGATHERQPSZrm = 6798, X86_VGATHERQPSrm = 6799, X86_VGETEXPPDZ128m = 6800, X86_VGETEXPPDZ128mb = 6801, X86_VGETEXPPDZ128mbk = 6802, X86_VGETEXPPDZ128mbkz = 6803, X86_VGETEXPPDZ128mk = 6804, X86_VGETEXPPDZ128mkz = 6805, X86_VGETEXPPDZ128r = 6806, X86_VGETEXPPDZ128rk = 6807, X86_VGETEXPPDZ128rkz = 6808, X86_VGETEXPPDZ256m = 6809, X86_VGETEXPPDZ256mb = 6810, X86_VGETEXPPDZ256mbk = 6811, X86_VGETEXPPDZ256mbkz = 6812, X86_VGETEXPPDZ256mk = 6813, X86_VGETEXPPDZ256mkz = 6814, X86_VGETEXPPDZ256r = 6815, X86_VGETEXPPDZ256rk = 6816, X86_VGETEXPPDZ256rkz = 6817, X86_VGETEXPPDZm = 6818, X86_VGETEXPPDZmb = 6819, X86_VGETEXPPDZmbk = 6820, X86_VGETEXPPDZmbkz = 6821, X86_VGETEXPPDZmk = 6822, X86_VGETEXPPDZmkz = 6823, X86_VGETEXPPDZr = 6824, X86_VGETEXPPDZrb = 6825, X86_VGETEXPPDZrbk = 6826, X86_VGETEXPPDZrbkz = 6827, X86_VGETEXPPDZrk = 6828, X86_VGETEXPPDZrkz = 6829, X86_VGETEXPPSZ128m = 6830, X86_VGETEXPPSZ128mb = 6831, X86_VGETEXPPSZ128mbk = 6832, X86_VGETEXPPSZ128mbkz = 6833, X86_VGETEXPPSZ128mk = 6834, X86_VGETEXPPSZ128mkz = 6835, X86_VGETEXPPSZ128r = 6836, X86_VGETEXPPSZ128rk = 6837, X86_VGETEXPPSZ128rkz = 6838, X86_VGETEXPPSZ256m = 6839, X86_VGETEXPPSZ256mb = 6840, X86_VGETEXPPSZ256mbk = 6841, X86_VGETEXPPSZ256mbkz = 6842, X86_VGETEXPPSZ256mk = 6843, X86_VGETEXPPSZ256mkz = 6844, X86_VGETEXPPSZ256r = 6845, X86_VGETEXPPSZ256rk = 6846, X86_VGETEXPPSZ256rkz = 6847, X86_VGETEXPPSZm = 6848, X86_VGETEXPPSZmb = 6849, X86_VGETEXPPSZmbk = 6850, X86_VGETEXPPSZmbkz = 6851, X86_VGETEXPPSZmk = 6852, X86_VGETEXPPSZmkz = 6853, X86_VGETEXPPSZr = 6854, X86_VGETEXPPSZrb = 6855, X86_VGETEXPPSZrbk = 6856, X86_VGETEXPPSZrbkz = 6857, X86_VGETEXPPSZrk = 6858, X86_VGETEXPPSZrkz = 6859, X86_VGETEXPSDZm = 6860, X86_VGETEXPSDZmk = 6861, X86_VGETEXPSDZmkz = 6862, X86_VGETEXPSDZr = 6863, X86_VGETEXPSDZrb = 6864, X86_VGETEXPSDZrbk = 6865, X86_VGETEXPSDZrbkz = 6866, X86_VGETEXPSDZrk = 6867, X86_VGETEXPSDZrkz = 6868, X86_VGETEXPSSZm = 6869, X86_VGETEXPSSZmk = 6870, X86_VGETEXPSSZmkz = 6871, X86_VGETEXPSSZr = 6872, X86_VGETEXPSSZrb = 6873, X86_VGETEXPSSZrbk = 6874, X86_VGETEXPSSZrbkz = 6875, X86_VGETEXPSSZrk = 6876, X86_VGETEXPSSZrkz = 6877, X86_VGETMANTPDZ128rmbi = 6878, X86_VGETMANTPDZ128rmbik = 6879, X86_VGETMANTPDZ128rmbikz = 6880, X86_VGETMANTPDZ128rmi = 6881, X86_VGETMANTPDZ128rmik = 6882, X86_VGETMANTPDZ128rmikz = 6883, X86_VGETMANTPDZ128rri = 6884, X86_VGETMANTPDZ128rrik = 6885, X86_VGETMANTPDZ128rrikz = 6886, X86_VGETMANTPDZ256rmbi = 6887, X86_VGETMANTPDZ256rmbik = 6888, X86_VGETMANTPDZ256rmbikz = 6889, X86_VGETMANTPDZ256rmi = 6890, X86_VGETMANTPDZ256rmik = 6891, X86_VGETMANTPDZ256rmikz = 6892, X86_VGETMANTPDZ256rri = 6893, X86_VGETMANTPDZ256rrik = 6894, X86_VGETMANTPDZ256rrikz = 6895, X86_VGETMANTPDZrmbi = 6896, X86_VGETMANTPDZrmbik = 6897, X86_VGETMANTPDZrmbikz = 6898, X86_VGETMANTPDZrmi = 6899, X86_VGETMANTPDZrmik = 6900, X86_VGETMANTPDZrmikz = 6901, X86_VGETMANTPDZrri = 6902, X86_VGETMANTPDZrrib = 6903, X86_VGETMANTPDZrribk = 6904, X86_VGETMANTPDZrribkz = 6905, X86_VGETMANTPDZrrik = 6906, X86_VGETMANTPDZrrikz = 6907, X86_VGETMANTPSZ128rmbi = 6908, X86_VGETMANTPSZ128rmbik = 6909, X86_VGETMANTPSZ128rmbikz = 6910, X86_VGETMANTPSZ128rmi = 6911, X86_VGETMANTPSZ128rmik = 6912, X86_VGETMANTPSZ128rmikz = 6913, X86_VGETMANTPSZ128rri = 6914, X86_VGETMANTPSZ128rrik = 6915, X86_VGETMANTPSZ128rrikz = 6916, X86_VGETMANTPSZ256rmbi = 6917, X86_VGETMANTPSZ256rmbik = 6918, X86_VGETMANTPSZ256rmbikz = 6919, X86_VGETMANTPSZ256rmi = 6920, X86_VGETMANTPSZ256rmik = 6921, X86_VGETMANTPSZ256rmikz = 6922, X86_VGETMANTPSZ256rri = 6923, X86_VGETMANTPSZ256rrik = 6924, X86_VGETMANTPSZ256rrikz = 6925, X86_VGETMANTPSZrmbi = 6926, X86_VGETMANTPSZrmbik = 6927, X86_VGETMANTPSZrmbikz = 6928, X86_VGETMANTPSZrmi = 6929, X86_VGETMANTPSZrmik = 6930, X86_VGETMANTPSZrmikz = 6931, X86_VGETMANTPSZrri = 6932, X86_VGETMANTPSZrrib = 6933, X86_VGETMANTPSZrribk = 6934, X86_VGETMANTPSZrribkz = 6935, X86_VGETMANTPSZrrik = 6936, X86_VGETMANTPSZrrikz = 6937, X86_VGETMANTSDZrmi = 6938, X86_VGETMANTSDZrmik = 6939, X86_VGETMANTSDZrmikz = 6940, X86_VGETMANTSDZrri = 6941, X86_VGETMANTSDZrrib = 6942, X86_VGETMANTSDZrribk = 6943, X86_VGETMANTSDZrribkz = 6944, X86_VGETMANTSDZrrik = 6945, X86_VGETMANTSDZrrikz = 6946, X86_VGETMANTSSZrmi = 6947, X86_VGETMANTSSZrmik = 6948, X86_VGETMANTSSZrmikz = 6949, X86_VGETMANTSSZrri = 6950, X86_VGETMANTSSZrrib = 6951, X86_VGETMANTSSZrribk = 6952, X86_VGETMANTSSZrribkz = 6953, X86_VGETMANTSSZrrik = 6954, X86_VGETMANTSSZrrikz = 6955, X86_VGF2P8AFFINEINVQBYrmi = 6956, X86_VGF2P8AFFINEINVQBYrri = 6957, X86_VGF2P8AFFINEINVQBZ128rmbi = 6958, X86_VGF2P8AFFINEINVQBZ128rmbik = 6959, X86_VGF2P8AFFINEINVQBZ128rmbikz = 6960, X86_VGF2P8AFFINEINVQBZ128rmi = 6961, X86_VGF2P8AFFINEINVQBZ128rmik = 6962, X86_VGF2P8AFFINEINVQBZ128rmikz = 6963, X86_VGF2P8AFFINEINVQBZ128rri = 6964, X86_VGF2P8AFFINEINVQBZ128rrik = 6965, X86_VGF2P8AFFINEINVQBZ128rrikz = 6966, X86_VGF2P8AFFINEINVQBZ256rmbi = 6967, X86_VGF2P8AFFINEINVQBZ256rmbik = 6968, X86_VGF2P8AFFINEINVQBZ256rmbikz = 6969, X86_VGF2P8AFFINEINVQBZ256rmi = 6970, X86_VGF2P8AFFINEINVQBZ256rmik = 6971, X86_VGF2P8AFFINEINVQBZ256rmikz = 6972, X86_VGF2P8AFFINEINVQBZ256rri = 6973, X86_VGF2P8AFFINEINVQBZ256rrik = 6974, X86_VGF2P8AFFINEINVQBZ256rrikz = 6975, X86_VGF2P8AFFINEINVQBZrmbi = 6976, X86_VGF2P8AFFINEINVQBZrmbik = 6977, X86_VGF2P8AFFINEINVQBZrmbikz = 6978, X86_VGF2P8AFFINEINVQBZrmi = 6979, X86_VGF2P8AFFINEINVQBZrmik = 6980, X86_VGF2P8AFFINEINVQBZrmikz = 6981, X86_VGF2P8AFFINEINVQBZrri = 6982, X86_VGF2P8AFFINEINVQBZrrik = 6983, X86_VGF2P8AFFINEINVQBZrrikz = 6984, X86_VGF2P8AFFINEINVQBrmi = 6985, X86_VGF2P8AFFINEINVQBrri = 6986, X86_VGF2P8AFFINEQBYrmi = 6987, X86_VGF2P8AFFINEQBYrri = 6988, X86_VGF2P8AFFINEQBZ128rmbi = 6989, X86_VGF2P8AFFINEQBZ128rmbik = 6990, X86_VGF2P8AFFINEQBZ128rmbikz = 6991, X86_VGF2P8AFFINEQBZ128rmi = 6992, X86_VGF2P8AFFINEQBZ128rmik = 6993, X86_VGF2P8AFFINEQBZ128rmikz = 6994, X86_VGF2P8AFFINEQBZ128rri = 6995, X86_VGF2P8AFFINEQBZ128rrik = 6996, X86_VGF2P8AFFINEQBZ128rrikz = 6997, X86_VGF2P8AFFINEQBZ256rmbi = 6998, X86_VGF2P8AFFINEQBZ256rmbik = 6999, X86_VGF2P8AFFINEQBZ256rmbikz = 7000, X86_VGF2P8AFFINEQBZ256rmi = 7001, X86_VGF2P8AFFINEQBZ256rmik = 7002, X86_VGF2P8AFFINEQBZ256rmikz = 7003, X86_VGF2P8AFFINEQBZ256rri = 7004, X86_VGF2P8AFFINEQBZ256rrik = 7005, X86_VGF2P8AFFINEQBZ256rrikz = 7006, X86_VGF2P8AFFINEQBZrmbi = 7007, X86_VGF2P8AFFINEQBZrmbik = 7008, X86_VGF2P8AFFINEQBZrmbikz = 7009, X86_VGF2P8AFFINEQBZrmi = 7010, X86_VGF2P8AFFINEQBZrmik = 7011, X86_VGF2P8AFFINEQBZrmikz = 7012, X86_VGF2P8AFFINEQBZrri = 7013, X86_VGF2P8AFFINEQBZrrik = 7014, X86_VGF2P8AFFINEQBZrrikz = 7015, X86_VGF2P8AFFINEQBrmi = 7016, X86_VGF2P8AFFINEQBrri = 7017, X86_VGF2P8MULBYrm = 7018, X86_VGF2P8MULBYrr = 7019, X86_VGF2P8MULBZ128rm = 7020, X86_VGF2P8MULBZ128rmk = 7021, X86_VGF2P8MULBZ128rmkz = 7022, X86_VGF2P8MULBZ128rr = 7023, X86_VGF2P8MULBZ128rrk = 7024, X86_VGF2P8MULBZ128rrkz = 7025, X86_VGF2P8MULBZ256rm = 7026, X86_VGF2P8MULBZ256rmk = 7027, X86_VGF2P8MULBZ256rmkz = 7028, X86_VGF2P8MULBZ256rr = 7029, X86_VGF2P8MULBZ256rrk = 7030, X86_VGF2P8MULBZ256rrkz = 7031, X86_VGF2P8MULBZrm = 7032, X86_VGF2P8MULBZrmk = 7033, X86_VGF2P8MULBZrmkz = 7034, X86_VGF2P8MULBZrr = 7035, X86_VGF2P8MULBZrrk = 7036, X86_VGF2P8MULBZrrkz = 7037, X86_VGF2P8MULBrm = 7038, X86_VGF2P8MULBrr = 7039, X86_VHADDPDYrm = 7040, X86_VHADDPDYrr = 7041, X86_VHADDPDrm = 7042, X86_VHADDPDrr = 7043, X86_VHADDPSYrm = 7044, X86_VHADDPSYrr = 7045, X86_VHADDPSrm = 7046, X86_VHADDPSrr = 7047, X86_VHSUBPDYrm = 7048, X86_VHSUBPDYrr = 7049, X86_VHSUBPDrm = 7050, X86_VHSUBPDrr = 7051, X86_VHSUBPSYrm = 7052, X86_VHSUBPSYrr = 7053, X86_VHSUBPSrm = 7054, X86_VHSUBPSrr = 7055, X86_VINSERTF128rm = 7056, X86_VINSERTF128rr = 7057, X86_VINSERTF32x4Z256rm = 7058, X86_VINSERTF32x4Z256rmk = 7059, X86_VINSERTF32x4Z256rmkz = 7060, X86_VINSERTF32x4Z256rr = 7061, X86_VINSERTF32x4Z256rrk = 7062, X86_VINSERTF32x4Z256rrkz = 7063, X86_VINSERTF32x4Zrm = 7064, X86_VINSERTF32x4Zrmk = 7065, X86_VINSERTF32x4Zrmkz = 7066, X86_VINSERTF32x4Zrr = 7067, X86_VINSERTF32x4Zrrk = 7068, X86_VINSERTF32x4Zrrkz = 7069, X86_VINSERTF32x8Zrm = 7070, X86_VINSERTF32x8Zrmk = 7071, X86_VINSERTF32x8Zrmkz = 7072, X86_VINSERTF32x8Zrr = 7073, X86_VINSERTF32x8Zrrk = 7074, X86_VINSERTF32x8Zrrkz = 7075, X86_VINSERTF64x2Z256rm = 7076, X86_VINSERTF64x2Z256rmk = 7077, X86_VINSERTF64x2Z256rmkz = 7078, X86_VINSERTF64x2Z256rr = 7079, X86_VINSERTF64x2Z256rrk = 7080, X86_VINSERTF64x2Z256rrkz = 7081, X86_VINSERTF64x2Zrm = 7082, X86_VINSERTF64x2Zrmk = 7083, X86_VINSERTF64x2Zrmkz = 7084, X86_VINSERTF64x2Zrr = 7085, X86_VINSERTF64x2Zrrk = 7086, X86_VINSERTF64x2Zrrkz = 7087, X86_VINSERTF64x4Zrm = 7088, X86_VINSERTF64x4Zrmk = 7089, X86_VINSERTF64x4Zrmkz = 7090, X86_VINSERTF64x4Zrr = 7091, X86_VINSERTF64x4Zrrk = 7092, X86_VINSERTF64x4Zrrkz = 7093, X86_VINSERTI128rm = 7094, X86_VINSERTI128rr = 7095, X86_VINSERTI32x4Z256rm = 7096, X86_VINSERTI32x4Z256rmk = 7097, X86_VINSERTI32x4Z256rmkz = 7098, X86_VINSERTI32x4Z256rr = 7099, X86_VINSERTI32x4Z256rrk = 7100, X86_VINSERTI32x4Z256rrkz = 7101, X86_VINSERTI32x4Zrm = 7102, X86_VINSERTI32x4Zrmk = 7103, X86_VINSERTI32x4Zrmkz = 7104, X86_VINSERTI32x4Zrr = 7105, X86_VINSERTI32x4Zrrk = 7106, X86_VINSERTI32x4Zrrkz = 7107, X86_VINSERTI32x8Zrm = 7108, X86_VINSERTI32x8Zrmk = 7109, X86_VINSERTI32x8Zrmkz = 7110, X86_VINSERTI32x8Zrr = 7111, X86_VINSERTI32x8Zrrk = 7112, X86_VINSERTI32x8Zrrkz = 7113, X86_VINSERTI64x2Z256rm = 7114, X86_VINSERTI64x2Z256rmk = 7115, X86_VINSERTI64x2Z256rmkz = 7116, X86_VINSERTI64x2Z256rr = 7117, X86_VINSERTI64x2Z256rrk = 7118, X86_VINSERTI64x2Z256rrkz = 7119, X86_VINSERTI64x2Zrm = 7120, X86_VINSERTI64x2Zrmk = 7121, X86_VINSERTI64x2Zrmkz = 7122, X86_VINSERTI64x2Zrr = 7123, X86_VINSERTI64x2Zrrk = 7124, X86_VINSERTI64x2Zrrkz = 7125, X86_VINSERTI64x4Zrm = 7126, X86_VINSERTI64x4Zrmk = 7127, X86_VINSERTI64x4Zrmkz = 7128, X86_VINSERTI64x4Zrr = 7129, X86_VINSERTI64x4Zrrk = 7130, X86_VINSERTI64x4Zrrkz = 7131, X86_VINSERTPSZrm = 7132, X86_VINSERTPSZrr = 7133, X86_VINSERTPSrm = 7134, X86_VINSERTPSrr = 7135, X86_VLDDQUYrm = 7136, X86_VLDDQUrm = 7137, X86_VLDMXCSR = 7138, X86_VMASKMOVDQU = 7139, X86_VMASKMOVDQU64 = 7140, X86_VMASKMOVPDYmr = 7141, X86_VMASKMOVPDYrm = 7142, X86_VMASKMOVPDmr = 7143, X86_VMASKMOVPDrm = 7144, X86_VMASKMOVPSYmr = 7145, X86_VMASKMOVPSYrm = 7146, X86_VMASKMOVPSmr = 7147, X86_VMASKMOVPSrm = 7148, X86_VMAXCPDYrm = 7149, X86_VMAXCPDYrr = 7150, X86_VMAXCPDZ128rm = 7151, X86_VMAXCPDZ128rmb = 7152, X86_VMAXCPDZ128rmbk = 7153, X86_VMAXCPDZ128rmbkz = 7154, X86_VMAXCPDZ128rmk = 7155, X86_VMAXCPDZ128rmkz = 7156, X86_VMAXCPDZ128rr = 7157, X86_VMAXCPDZ128rrk = 7158, X86_VMAXCPDZ128rrkz = 7159, X86_VMAXCPDZ256rm = 7160, X86_VMAXCPDZ256rmb = 7161, X86_VMAXCPDZ256rmbk = 7162, X86_VMAXCPDZ256rmbkz = 7163, X86_VMAXCPDZ256rmk = 7164, X86_VMAXCPDZ256rmkz = 7165, X86_VMAXCPDZ256rr = 7166, X86_VMAXCPDZ256rrk = 7167, X86_VMAXCPDZ256rrkz = 7168, X86_VMAXCPDZrm = 7169, X86_VMAXCPDZrmb = 7170, X86_VMAXCPDZrmbk = 7171, X86_VMAXCPDZrmbkz = 7172, X86_VMAXCPDZrmk = 7173, X86_VMAXCPDZrmkz = 7174, X86_VMAXCPDZrr = 7175, X86_VMAXCPDZrrk = 7176, X86_VMAXCPDZrrkz = 7177, X86_VMAXCPDrm = 7178, X86_VMAXCPDrr = 7179, X86_VMAXCPSYrm = 7180, X86_VMAXCPSYrr = 7181, X86_VMAXCPSZ128rm = 7182, X86_VMAXCPSZ128rmb = 7183, X86_VMAXCPSZ128rmbk = 7184, X86_VMAXCPSZ128rmbkz = 7185, X86_VMAXCPSZ128rmk = 7186, X86_VMAXCPSZ128rmkz = 7187, X86_VMAXCPSZ128rr = 7188, X86_VMAXCPSZ128rrk = 7189, X86_VMAXCPSZ128rrkz = 7190, X86_VMAXCPSZ256rm = 7191, X86_VMAXCPSZ256rmb = 7192, X86_VMAXCPSZ256rmbk = 7193, X86_VMAXCPSZ256rmbkz = 7194, X86_VMAXCPSZ256rmk = 7195, X86_VMAXCPSZ256rmkz = 7196, X86_VMAXCPSZ256rr = 7197, X86_VMAXCPSZ256rrk = 7198, X86_VMAXCPSZ256rrkz = 7199, X86_VMAXCPSZrm = 7200, X86_VMAXCPSZrmb = 7201, X86_VMAXCPSZrmbk = 7202, X86_VMAXCPSZrmbkz = 7203, X86_VMAXCPSZrmk = 7204, X86_VMAXCPSZrmkz = 7205, X86_VMAXCPSZrr = 7206, X86_VMAXCPSZrrk = 7207, X86_VMAXCPSZrrkz = 7208, X86_VMAXCPSrm = 7209, X86_VMAXCPSrr = 7210, X86_VMAXCSDZrm = 7211, X86_VMAXCSDZrr = 7212, X86_VMAXCSDrm = 7213, X86_VMAXCSDrr = 7214, X86_VMAXCSSZrm = 7215, X86_VMAXCSSZrr = 7216, X86_VMAXCSSrm = 7217, X86_VMAXCSSrr = 7218, X86_VMAXPDYrm = 7219, X86_VMAXPDYrr = 7220, X86_VMAXPDZ128rm = 7221, X86_VMAXPDZ128rmb = 7222, X86_VMAXPDZ128rmbk = 7223, X86_VMAXPDZ128rmbkz = 7224, X86_VMAXPDZ128rmk = 7225, X86_VMAXPDZ128rmkz = 7226, X86_VMAXPDZ128rr = 7227, X86_VMAXPDZ128rrk = 7228, X86_VMAXPDZ128rrkz = 7229, X86_VMAXPDZ256rm = 7230, X86_VMAXPDZ256rmb = 7231, X86_VMAXPDZ256rmbk = 7232, X86_VMAXPDZ256rmbkz = 7233, X86_VMAXPDZ256rmk = 7234, X86_VMAXPDZ256rmkz = 7235, X86_VMAXPDZ256rr = 7236, X86_VMAXPDZ256rrk = 7237, X86_VMAXPDZ256rrkz = 7238, X86_VMAXPDZrm = 7239, X86_VMAXPDZrmb = 7240, X86_VMAXPDZrmbk = 7241, X86_VMAXPDZrmbkz = 7242, X86_VMAXPDZrmk = 7243, X86_VMAXPDZrmkz = 7244, X86_VMAXPDZrr = 7245, X86_VMAXPDZrrb = 7246, X86_VMAXPDZrrbk = 7247, X86_VMAXPDZrrbkz = 7248, X86_VMAXPDZrrk = 7249, X86_VMAXPDZrrkz = 7250, X86_VMAXPDrm = 7251, X86_VMAXPDrr = 7252, X86_VMAXPSYrm = 7253, X86_VMAXPSYrr = 7254, X86_VMAXPSZ128rm = 7255, X86_VMAXPSZ128rmb = 7256, X86_VMAXPSZ128rmbk = 7257, X86_VMAXPSZ128rmbkz = 7258, X86_VMAXPSZ128rmk = 7259, X86_VMAXPSZ128rmkz = 7260, X86_VMAXPSZ128rr = 7261, X86_VMAXPSZ128rrk = 7262, X86_VMAXPSZ128rrkz = 7263, X86_VMAXPSZ256rm = 7264, X86_VMAXPSZ256rmb = 7265, X86_VMAXPSZ256rmbk = 7266, X86_VMAXPSZ256rmbkz = 7267, X86_VMAXPSZ256rmk = 7268, X86_VMAXPSZ256rmkz = 7269, X86_VMAXPSZ256rr = 7270, X86_VMAXPSZ256rrk = 7271, X86_VMAXPSZ256rrkz = 7272, X86_VMAXPSZrm = 7273, X86_VMAXPSZrmb = 7274, X86_VMAXPSZrmbk = 7275, X86_VMAXPSZrmbkz = 7276, X86_VMAXPSZrmk = 7277, X86_VMAXPSZrmkz = 7278, X86_VMAXPSZrr = 7279, X86_VMAXPSZrrb = 7280, X86_VMAXPSZrrbk = 7281, X86_VMAXPSZrrbkz = 7282, X86_VMAXPSZrrk = 7283, X86_VMAXPSZrrkz = 7284, X86_VMAXPSrm = 7285, X86_VMAXPSrr = 7286, X86_VMAXSDZrm = 7287, X86_VMAXSDZrm_Int = 7288, X86_VMAXSDZrm_Intk = 7289, X86_VMAXSDZrm_Intkz = 7290, X86_VMAXSDZrr = 7291, X86_VMAXSDZrr_Int = 7292, X86_VMAXSDZrr_Intk = 7293, X86_VMAXSDZrr_Intkz = 7294, X86_VMAXSDZrrb_Int = 7295, X86_VMAXSDZrrb_Intk = 7296, X86_VMAXSDZrrb_Intkz = 7297, X86_VMAXSDrm = 7298, X86_VMAXSDrm_Int = 7299, X86_VMAXSDrr = 7300, X86_VMAXSDrr_Int = 7301, X86_VMAXSSZrm = 7302, X86_VMAXSSZrm_Int = 7303, X86_VMAXSSZrm_Intk = 7304, X86_VMAXSSZrm_Intkz = 7305, X86_VMAXSSZrr = 7306, X86_VMAXSSZrr_Int = 7307, X86_VMAXSSZrr_Intk = 7308, X86_VMAXSSZrr_Intkz = 7309, X86_VMAXSSZrrb_Int = 7310, X86_VMAXSSZrrb_Intk = 7311, X86_VMAXSSZrrb_Intkz = 7312, X86_VMAXSSrm = 7313, X86_VMAXSSrm_Int = 7314, X86_VMAXSSrr = 7315, X86_VMAXSSrr_Int = 7316, X86_VMCALL = 7317, X86_VMCLEARm = 7318, X86_VMFUNC = 7319, X86_VMINCPDYrm = 7320, X86_VMINCPDYrr = 7321, X86_VMINCPDZ128rm = 7322, X86_VMINCPDZ128rmb = 7323, X86_VMINCPDZ128rmbk = 7324, X86_VMINCPDZ128rmbkz = 7325, X86_VMINCPDZ128rmk = 7326, X86_VMINCPDZ128rmkz = 7327, X86_VMINCPDZ128rr = 7328, X86_VMINCPDZ128rrk = 7329, X86_VMINCPDZ128rrkz = 7330, X86_VMINCPDZ256rm = 7331, X86_VMINCPDZ256rmb = 7332, X86_VMINCPDZ256rmbk = 7333, X86_VMINCPDZ256rmbkz = 7334, X86_VMINCPDZ256rmk = 7335, X86_VMINCPDZ256rmkz = 7336, X86_VMINCPDZ256rr = 7337, X86_VMINCPDZ256rrk = 7338, X86_VMINCPDZ256rrkz = 7339, X86_VMINCPDZrm = 7340, X86_VMINCPDZrmb = 7341, X86_VMINCPDZrmbk = 7342, X86_VMINCPDZrmbkz = 7343, X86_VMINCPDZrmk = 7344, X86_VMINCPDZrmkz = 7345, X86_VMINCPDZrr = 7346, X86_VMINCPDZrrk = 7347, X86_VMINCPDZrrkz = 7348, X86_VMINCPDrm = 7349, X86_VMINCPDrr = 7350, X86_VMINCPSYrm = 7351, X86_VMINCPSYrr = 7352, X86_VMINCPSZ128rm = 7353, X86_VMINCPSZ128rmb = 7354, X86_VMINCPSZ128rmbk = 7355, X86_VMINCPSZ128rmbkz = 7356, X86_VMINCPSZ128rmk = 7357, X86_VMINCPSZ128rmkz = 7358, X86_VMINCPSZ128rr = 7359, X86_VMINCPSZ128rrk = 7360, X86_VMINCPSZ128rrkz = 7361, X86_VMINCPSZ256rm = 7362, X86_VMINCPSZ256rmb = 7363, X86_VMINCPSZ256rmbk = 7364, X86_VMINCPSZ256rmbkz = 7365, X86_VMINCPSZ256rmk = 7366, X86_VMINCPSZ256rmkz = 7367, X86_VMINCPSZ256rr = 7368, X86_VMINCPSZ256rrk = 7369, X86_VMINCPSZ256rrkz = 7370, X86_VMINCPSZrm = 7371, X86_VMINCPSZrmb = 7372, X86_VMINCPSZrmbk = 7373, X86_VMINCPSZrmbkz = 7374, X86_VMINCPSZrmk = 7375, X86_VMINCPSZrmkz = 7376, X86_VMINCPSZrr = 7377, X86_VMINCPSZrrk = 7378, X86_VMINCPSZrrkz = 7379, X86_VMINCPSrm = 7380, X86_VMINCPSrr = 7381, X86_VMINCSDZrm = 7382, X86_VMINCSDZrr = 7383, X86_VMINCSDrm = 7384, X86_VMINCSDrr = 7385, X86_VMINCSSZrm = 7386, X86_VMINCSSZrr = 7387, X86_VMINCSSrm = 7388, X86_VMINCSSrr = 7389, X86_VMINPDYrm = 7390, X86_VMINPDYrr = 7391, X86_VMINPDZ128rm = 7392, X86_VMINPDZ128rmb = 7393, X86_VMINPDZ128rmbk = 7394, X86_VMINPDZ128rmbkz = 7395, X86_VMINPDZ128rmk = 7396, X86_VMINPDZ128rmkz = 7397, X86_VMINPDZ128rr = 7398, X86_VMINPDZ128rrk = 7399, X86_VMINPDZ128rrkz = 7400, X86_VMINPDZ256rm = 7401, X86_VMINPDZ256rmb = 7402, X86_VMINPDZ256rmbk = 7403, X86_VMINPDZ256rmbkz = 7404, X86_VMINPDZ256rmk = 7405, X86_VMINPDZ256rmkz = 7406, X86_VMINPDZ256rr = 7407, X86_VMINPDZ256rrk = 7408, X86_VMINPDZ256rrkz = 7409, X86_VMINPDZrm = 7410, X86_VMINPDZrmb = 7411, X86_VMINPDZrmbk = 7412, X86_VMINPDZrmbkz = 7413, X86_VMINPDZrmk = 7414, X86_VMINPDZrmkz = 7415, X86_VMINPDZrr = 7416, X86_VMINPDZrrb = 7417, X86_VMINPDZrrbk = 7418, X86_VMINPDZrrbkz = 7419, X86_VMINPDZrrk = 7420, X86_VMINPDZrrkz = 7421, X86_VMINPDrm = 7422, X86_VMINPDrr = 7423, X86_VMINPSYrm = 7424, X86_VMINPSYrr = 7425, X86_VMINPSZ128rm = 7426, X86_VMINPSZ128rmb = 7427, X86_VMINPSZ128rmbk = 7428, X86_VMINPSZ128rmbkz = 7429, X86_VMINPSZ128rmk = 7430, X86_VMINPSZ128rmkz = 7431, X86_VMINPSZ128rr = 7432, X86_VMINPSZ128rrk = 7433, X86_VMINPSZ128rrkz = 7434, X86_VMINPSZ256rm = 7435, X86_VMINPSZ256rmb = 7436, X86_VMINPSZ256rmbk = 7437, X86_VMINPSZ256rmbkz = 7438, X86_VMINPSZ256rmk = 7439, X86_VMINPSZ256rmkz = 7440, X86_VMINPSZ256rr = 7441, X86_VMINPSZ256rrk = 7442, X86_VMINPSZ256rrkz = 7443, X86_VMINPSZrm = 7444, X86_VMINPSZrmb = 7445, X86_VMINPSZrmbk = 7446, X86_VMINPSZrmbkz = 7447, X86_VMINPSZrmk = 7448, X86_VMINPSZrmkz = 7449, X86_VMINPSZrr = 7450, X86_VMINPSZrrb = 7451, X86_VMINPSZrrbk = 7452, X86_VMINPSZrrbkz = 7453, X86_VMINPSZrrk = 7454, X86_VMINPSZrrkz = 7455, X86_VMINPSrm = 7456, X86_VMINPSrr = 7457, X86_VMINSDZrm = 7458, X86_VMINSDZrm_Int = 7459, X86_VMINSDZrm_Intk = 7460, X86_VMINSDZrm_Intkz = 7461, X86_VMINSDZrr = 7462, X86_VMINSDZrr_Int = 7463, X86_VMINSDZrr_Intk = 7464, X86_VMINSDZrr_Intkz = 7465, X86_VMINSDZrrb_Int = 7466, X86_VMINSDZrrb_Intk = 7467, X86_VMINSDZrrb_Intkz = 7468, X86_VMINSDrm = 7469, X86_VMINSDrm_Int = 7470, X86_VMINSDrr = 7471, X86_VMINSDrr_Int = 7472, X86_VMINSSZrm = 7473, X86_VMINSSZrm_Int = 7474, X86_VMINSSZrm_Intk = 7475, X86_VMINSSZrm_Intkz = 7476, X86_VMINSSZrr = 7477, X86_VMINSSZrr_Int = 7478, X86_VMINSSZrr_Intk = 7479, X86_VMINSSZrr_Intkz = 7480, X86_VMINSSZrrb_Int = 7481, X86_VMINSSZrrb_Intk = 7482, X86_VMINSSZrrb_Intkz = 7483, X86_VMINSSrm = 7484, X86_VMINSSrm_Int = 7485, X86_VMINSSrr = 7486, X86_VMINSSrr_Int = 7487, X86_VMLAUNCH = 7488, X86_VMLOAD32 = 7489, X86_VMLOAD64 = 7490, X86_VMMCALL = 7491, X86_VMOV64toPQIZrm = 7492, X86_VMOV64toPQIZrr = 7493, X86_VMOV64toPQIrm = 7494, X86_VMOV64toPQIrr = 7495, X86_VMOV64toSDZrm = 7496, X86_VMOV64toSDZrr = 7497, X86_VMOV64toSDrm = 7498, X86_VMOV64toSDrr = 7499, X86_VMOVAPDYmr = 7500, X86_VMOVAPDYrm = 7501, X86_VMOVAPDYrr = 7502, X86_VMOVAPDYrr_REV = 7503, X86_VMOVAPDZ128mr = 7504, X86_VMOVAPDZ128mrk = 7505, X86_VMOVAPDZ128rm = 7506, X86_VMOVAPDZ128rmk = 7507, X86_VMOVAPDZ128rmkz = 7508, X86_VMOVAPDZ128rr = 7509, X86_VMOVAPDZ128rr_REV = 7510, X86_VMOVAPDZ128rrk = 7511, X86_VMOVAPDZ128rrk_REV = 7512, X86_VMOVAPDZ128rrkz = 7513, X86_VMOVAPDZ128rrkz_REV = 7514, X86_VMOVAPDZ256mr = 7515, X86_VMOVAPDZ256mrk = 7516, X86_VMOVAPDZ256rm = 7517, X86_VMOVAPDZ256rmk = 7518, X86_VMOVAPDZ256rmkz = 7519, X86_VMOVAPDZ256rr = 7520, X86_VMOVAPDZ256rr_REV = 7521, X86_VMOVAPDZ256rrk = 7522, X86_VMOVAPDZ256rrk_REV = 7523, X86_VMOVAPDZ256rrkz = 7524, X86_VMOVAPDZ256rrkz_REV = 7525, X86_VMOVAPDZmr = 7526, X86_VMOVAPDZmrk = 7527, X86_VMOVAPDZrm = 7528, X86_VMOVAPDZrmk = 7529, X86_VMOVAPDZrmkz = 7530, X86_VMOVAPDZrr = 7531, X86_VMOVAPDZrr_REV = 7532, X86_VMOVAPDZrrk = 7533, X86_VMOVAPDZrrk_REV = 7534, X86_VMOVAPDZrrkz = 7535, X86_VMOVAPDZrrkz_REV = 7536, X86_VMOVAPDmr = 7537, X86_VMOVAPDrm = 7538, X86_VMOVAPDrr = 7539, X86_VMOVAPDrr_REV = 7540, X86_VMOVAPSYmr = 7541, X86_VMOVAPSYrm = 7542, X86_VMOVAPSYrr = 7543, X86_VMOVAPSYrr_REV = 7544, X86_VMOVAPSZ128mr = 7545, X86_VMOVAPSZ128mrk = 7546, X86_VMOVAPSZ128rm = 7547, X86_VMOVAPSZ128rmk = 7548, X86_VMOVAPSZ128rmkz = 7549, X86_VMOVAPSZ128rr = 7550, X86_VMOVAPSZ128rr_REV = 7551, X86_VMOVAPSZ128rrk = 7552, X86_VMOVAPSZ128rrk_REV = 7553, X86_VMOVAPSZ128rrkz = 7554, X86_VMOVAPSZ128rrkz_REV = 7555, X86_VMOVAPSZ256mr = 7556, X86_VMOVAPSZ256mrk = 7557, X86_VMOVAPSZ256rm = 7558, X86_VMOVAPSZ256rmk = 7559, X86_VMOVAPSZ256rmkz = 7560, X86_VMOVAPSZ256rr = 7561, X86_VMOVAPSZ256rr_REV = 7562, X86_VMOVAPSZ256rrk = 7563, X86_VMOVAPSZ256rrk_REV = 7564, X86_VMOVAPSZ256rrkz = 7565, X86_VMOVAPSZ256rrkz_REV = 7566, X86_VMOVAPSZmr = 7567, X86_VMOVAPSZmrk = 7568, X86_VMOVAPSZrm = 7569, X86_VMOVAPSZrmk = 7570, X86_VMOVAPSZrmkz = 7571, X86_VMOVAPSZrr = 7572, X86_VMOVAPSZrr_REV = 7573, X86_VMOVAPSZrrk = 7574, X86_VMOVAPSZrrk_REV = 7575, X86_VMOVAPSZrrkz = 7576, X86_VMOVAPSZrrkz_REV = 7577, X86_VMOVAPSmr = 7578, X86_VMOVAPSrm = 7579, X86_VMOVAPSrr = 7580, X86_VMOVAPSrr_REV = 7581, X86_VMOVDDUPYrm = 7582, X86_VMOVDDUPYrr = 7583, X86_VMOVDDUPZ128rm = 7584, X86_VMOVDDUPZ128rmk = 7585, X86_VMOVDDUPZ128rmkz = 7586, X86_VMOVDDUPZ128rr = 7587, X86_VMOVDDUPZ128rrk = 7588, X86_VMOVDDUPZ128rrkz = 7589, X86_VMOVDDUPZ256rm = 7590, X86_VMOVDDUPZ256rmk = 7591, X86_VMOVDDUPZ256rmkz = 7592, X86_VMOVDDUPZ256rr = 7593, X86_VMOVDDUPZ256rrk = 7594, X86_VMOVDDUPZ256rrkz = 7595, X86_VMOVDDUPZrm = 7596, X86_VMOVDDUPZrmk = 7597, X86_VMOVDDUPZrmkz = 7598, X86_VMOVDDUPZrr = 7599, X86_VMOVDDUPZrrk = 7600, X86_VMOVDDUPZrrkz = 7601, X86_VMOVDDUPrm = 7602, X86_VMOVDDUPrr = 7603, X86_VMOVDI2PDIZrm = 7604, X86_VMOVDI2PDIZrr = 7605, X86_VMOVDI2PDIrm = 7606, X86_VMOVDI2PDIrr = 7607, X86_VMOVDI2SSZrm = 7608, X86_VMOVDI2SSZrr = 7609, X86_VMOVDI2SSrm = 7610, X86_VMOVDI2SSrr = 7611, X86_VMOVDQA32Z128mr = 7612, X86_VMOVDQA32Z128mrk = 7613, X86_VMOVDQA32Z128rm = 7614, X86_VMOVDQA32Z128rmk = 7615, X86_VMOVDQA32Z128rmkz = 7616, X86_VMOVDQA32Z128rr = 7617, X86_VMOVDQA32Z128rr_REV = 7618, X86_VMOVDQA32Z128rrk = 7619, X86_VMOVDQA32Z128rrk_REV = 7620, X86_VMOVDQA32Z128rrkz = 7621, X86_VMOVDQA32Z128rrkz_REV = 7622, X86_VMOVDQA32Z256mr = 7623, X86_VMOVDQA32Z256mrk = 7624, X86_VMOVDQA32Z256rm = 7625, X86_VMOVDQA32Z256rmk = 7626, X86_VMOVDQA32Z256rmkz = 7627, X86_VMOVDQA32Z256rr = 7628, X86_VMOVDQA32Z256rr_REV = 7629, X86_VMOVDQA32Z256rrk = 7630, X86_VMOVDQA32Z256rrk_REV = 7631, X86_VMOVDQA32Z256rrkz = 7632, X86_VMOVDQA32Z256rrkz_REV = 7633, X86_VMOVDQA32Zmr = 7634, X86_VMOVDQA32Zmrk = 7635, X86_VMOVDQA32Zrm = 7636, X86_VMOVDQA32Zrmk = 7637, X86_VMOVDQA32Zrmkz = 7638, X86_VMOVDQA32Zrr = 7639, X86_VMOVDQA32Zrr_REV = 7640, X86_VMOVDQA32Zrrk = 7641, X86_VMOVDQA32Zrrk_REV = 7642, X86_VMOVDQA32Zrrkz = 7643, X86_VMOVDQA32Zrrkz_REV = 7644, X86_VMOVDQA64Z128mr = 7645, X86_VMOVDQA64Z128mrk = 7646, X86_VMOVDQA64Z128rm = 7647, X86_VMOVDQA64Z128rmk = 7648, X86_VMOVDQA64Z128rmkz = 7649, X86_VMOVDQA64Z128rr = 7650, X86_VMOVDQA64Z128rr_REV = 7651, X86_VMOVDQA64Z128rrk = 7652, X86_VMOVDQA64Z128rrk_REV = 7653, X86_VMOVDQA64Z128rrkz = 7654, X86_VMOVDQA64Z128rrkz_REV = 7655, X86_VMOVDQA64Z256mr = 7656, X86_VMOVDQA64Z256mrk = 7657, X86_VMOVDQA64Z256rm = 7658, X86_VMOVDQA64Z256rmk = 7659, X86_VMOVDQA64Z256rmkz = 7660, X86_VMOVDQA64Z256rr = 7661, X86_VMOVDQA64Z256rr_REV = 7662, X86_VMOVDQA64Z256rrk = 7663, X86_VMOVDQA64Z256rrk_REV = 7664, X86_VMOVDQA64Z256rrkz = 7665, X86_VMOVDQA64Z256rrkz_REV = 7666, X86_VMOVDQA64Zmr = 7667, X86_VMOVDQA64Zmrk = 7668, X86_VMOVDQA64Zrm = 7669, X86_VMOVDQA64Zrmk = 7670, X86_VMOVDQA64Zrmkz = 7671, X86_VMOVDQA64Zrr = 7672, X86_VMOVDQA64Zrr_REV = 7673, X86_VMOVDQA64Zrrk = 7674, X86_VMOVDQA64Zrrk_REV = 7675, X86_VMOVDQA64Zrrkz = 7676, X86_VMOVDQA64Zrrkz_REV = 7677, X86_VMOVDQAYmr = 7678, X86_VMOVDQAYrm = 7679, X86_VMOVDQAYrr = 7680, X86_VMOVDQAYrr_REV = 7681, X86_VMOVDQAmr = 7682, X86_VMOVDQArm = 7683, X86_VMOVDQArr = 7684, X86_VMOVDQArr_REV = 7685, X86_VMOVDQU16Z128mr = 7686, X86_VMOVDQU16Z128mrk = 7687, X86_VMOVDQU16Z128rm = 7688, X86_VMOVDQU16Z128rmk = 7689, X86_VMOVDQU16Z128rmkz = 7690, X86_VMOVDQU16Z128rr = 7691, X86_VMOVDQU16Z128rr_REV = 7692, X86_VMOVDQU16Z128rrk = 7693, X86_VMOVDQU16Z128rrk_REV = 7694, X86_VMOVDQU16Z128rrkz = 7695, X86_VMOVDQU16Z128rrkz_REV = 7696, X86_VMOVDQU16Z256mr = 7697, X86_VMOVDQU16Z256mrk = 7698, X86_VMOVDQU16Z256rm = 7699, X86_VMOVDQU16Z256rmk = 7700, X86_VMOVDQU16Z256rmkz = 7701, X86_VMOVDQU16Z256rr = 7702, X86_VMOVDQU16Z256rr_REV = 7703, X86_VMOVDQU16Z256rrk = 7704, X86_VMOVDQU16Z256rrk_REV = 7705, X86_VMOVDQU16Z256rrkz = 7706, X86_VMOVDQU16Z256rrkz_REV = 7707, X86_VMOVDQU16Zmr = 7708, X86_VMOVDQU16Zmrk = 7709, X86_VMOVDQU16Zrm = 7710, X86_VMOVDQU16Zrmk = 7711, X86_VMOVDQU16Zrmkz = 7712, X86_VMOVDQU16Zrr = 7713, X86_VMOVDQU16Zrr_REV = 7714, X86_VMOVDQU16Zrrk = 7715, X86_VMOVDQU16Zrrk_REV = 7716, X86_VMOVDQU16Zrrkz = 7717, X86_VMOVDQU16Zrrkz_REV = 7718, X86_VMOVDQU32Z128mr = 7719, X86_VMOVDQU32Z128mrk = 7720, X86_VMOVDQU32Z128rm = 7721, X86_VMOVDQU32Z128rmk = 7722, X86_VMOVDQU32Z128rmkz = 7723, X86_VMOVDQU32Z128rr = 7724, X86_VMOVDQU32Z128rr_REV = 7725, X86_VMOVDQU32Z128rrk = 7726, X86_VMOVDQU32Z128rrk_REV = 7727, X86_VMOVDQU32Z128rrkz = 7728, X86_VMOVDQU32Z128rrkz_REV = 7729, X86_VMOVDQU32Z256mr = 7730, X86_VMOVDQU32Z256mrk = 7731, X86_VMOVDQU32Z256rm = 7732, X86_VMOVDQU32Z256rmk = 7733, X86_VMOVDQU32Z256rmkz = 7734, X86_VMOVDQU32Z256rr = 7735, X86_VMOVDQU32Z256rr_REV = 7736, X86_VMOVDQU32Z256rrk = 7737, X86_VMOVDQU32Z256rrk_REV = 7738, X86_VMOVDQU32Z256rrkz = 7739, X86_VMOVDQU32Z256rrkz_REV = 7740, X86_VMOVDQU32Zmr = 7741, X86_VMOVDQU32Zmrk = 7742, X86_VMOVDQU32Zrm = 7743, X86_VMOVDQU32Zrmk = 7744, X86_VMOVDQU32Zrmkz = 7745, X86_VMOVDQU32Zrr = 7746, X86_VMOVDQU32Zrr_REV = 7747, X86_VMOVDQU32Zrrk = 7748, X86_VMOVDQU32Zrrk_REV = 7749, X86_VMOVDQU32Zrrkz = 7750, X86_VMOVDQU32Zrrkz_REV = 7751, X86_VMOVDQU64Z128mr = 7752, X86_VMOVDQU64Z128mrk = 7753, X86_VMOVDQU64Z128rm = 7754, X86_VMOVDQU64Z128rmk = 7755, X86_VMOVDQU64Z128rmkz = 7756, X86_VMOVDQU64Z128rr = 7757, X86_VMOVDQU64Z128rr_REV = 7758, X86_VMOVDQU64Z128rrk = 7759, X86_VMOVDQU64Z128rrk_REV = 7760, X86_VMOVDQU64Z128rrkz = 7761, X86_VMOVDQU64Z128rrkz_REV = 7762, X86_VMOVDQU64Z256mr = 7763, X86_VMOVDQU64Z256mrk = 7764, X86_VMOVDQU64Z256rm = 7765, X86_VMOVDQU64Z256rmk = 7766, X86_VMOVDQU64Z256rmkz = 7767, X86_VMOVDQU64Z256rr = 7768, X86_VMOVDQU64Z256rr_REV = 7769, X86_VMOVDQU64Z256rrk = 7770, X86_VMOVDQU64Z256rrk_REV = 7771, X86_VMOVDQU64Z256rrkz = 7772, X86_VMOVDQU64Z256rrkz_REV = 7773, X86_VMOVDQU64Zmr = 7774, X86_VMOVDQU64Zmrk = 7775, X86_VMOVDQU64Zrm = 7776, X86_VMOVDQU64Zrmk = 7777, X86_VMOVDQU64Zrmkz = 7778, X86_VMOVDQU64Zrr = 7779, X86_VMOVDQU64Zrr_REV = 7780, X86_VMOVDQU64Zrrk = 7781, X86_VMOVDQU64Zrrk_REV = 7782, X86_VMOVDQU64Zrrkz = 7783, X86_VMOVDQU64Zrrkz_REV = 7784, X86_VMOVDQU8Z128mr = 7785, X86_VMOVDQU8Z128mrk = 7786, X86_VMOVDQU8Z128rm = 7787, X86_VMOVDQU8Z128rmk = 7788, X86_VMOVDQU8Z128rmkz = 7789, X86_VMOVDQU8Z128rr = 7790, X86_VMOVDQU8Z128rr_REV = 7791, X86_VMOVDQU8Z128rrk = 7792, X86_VMOVDQU8Z128rrk_REV = 7793, X86_VMOVDQU8Z128rrkz = 7794, X86_VMOVDQU8Z128rrkz_REV = 7795, X86_VMOVDQU8Z256mr = 7796, X86_VMOVDQU8Z256mrk = 7797, X86_VMOVDQU8Z256rm = 7798, X86_VMOVDQU8Z256rmk = 7799, X86_VMOVDQU8Z256rmkz = 7800, X86_VMOVDQU8Z256rr = 7801, X86_VMOVDQU8Z256rr_REV = 7802, X86_VMOVDQU8Z256rrk = 7803, X86_VMOVDQU8Z256rrk_REV = 7804, X86_VMOVDQU8Z256rrkz = 7805, X86_VMOVDQU8Z256rrkz_REV = 7806, X86_VMOVDQU8Zmr = 7807, X86_VMOVDQU8Zmrk = 7808, X86_VMOVDQU8Zrm = 7809, X86_VMOVDQU8Zrmk = 7810, X86_VMOVDQU8Zrmkz = 7811, X86_VMOVDQU8Zrr = 7812, X86_VMOVDQU8Zrr_REV = 7813, X86_VMOVDQU8Zrrk = 7814, X86_VMOVDQU8Zrrk_REV = 7815, X86_VMOVDQU8Zrrkz = 7816, X86_VMOVDQU8Zrrkz_REV = 7817, X86_VMOVDQUYmr = 7818, X86_VMOVDQUYrm = 7819, X86_VMOVDQUYrr = 7820, X86_VMOVDQUYrr_REV = 7821, X86_VMOVDQUmr = 7822, X86_VMOVDQUrm = 7823, X86_VMOVDQUrr = 7824, X86_VMOVDQUrr_REV = 7825, X86_VMOVHLPSZrr = 7826, X86_VMOVHLPSrr = 7827, X86_VMOVHPDZ128mr = 7828, X86_VMOVHPDZ128rm = 7829, X86_VMOVHPDmr = 7830, X86_VMOVHPDrm = 7831, X86_VMOVHPSZ128mr = 7832, X86_VMOVHPSZ128rm = 7833, X86_VMOVHPSmr = 7834, X86_VMOVHPSrm = 7835, X86_VMOVLHPSZrr = 7836, X86_VMOVLHPSrr = 7837, X86_VMOVLPDZ128mr = 7838, X86_VMOVLPDZ128rm = 7839, X86_VMOVLPDmr = 7840, X86_VMOVLPDrm = 7841, X86_VMOVLPSZ128mr = 7842, X86_VMOVLPSZ128rm = 7843, X86_VMOVLPSmr = 7844, X86_VMOVLPSrm = 7845, X86_VMOVMSKPDYrr = 7846, X86_VMOVMSKPDrr = 7847, X86_VMOVMSKPSYrr = 7848, X86_VMOVMSKPSrr = 7849, X86_VMOVNTDQAYrm = 7850, X86_VMOVNTDQAZ128rm = 7851, X86_VMOVNTDQAZ256rm = 7852, X86_VMOVNTDQAZrm = 7853, X86_VMOVNTDQArm = 7854, X86_VMOVNTDQYmr = 7855, X86_VMOVNTDQZ128mr = 7856, X86_VMOVNTDQZ256mr = 7857, X86_VMOVNTDQZmr = 7858, X86_VMOVNTDQmr = 7859, X86_VMOVNTPDYmr = 7860, X86_VMOVNTPDZ128mr = 7861, X86_VMOVNTPDZ256mr = 7862, X86_VMOVNTPDZmr = 7863, X86_VMOVNTPDmr = 7864, X86_VMOVNTPSYmr = 7865, X86_VMOVNTPSZ128mr = 7866, X86_VMOVNTPSZ256mr = 7867, X86_VMOVNTPSZmr = 7868, X86_VMOVNTPSmr = 7869, X86_VMOVPDI2DIZmr = 7870, X86_VMOVPDI2DIZrr = 7871, X86_VMOVPDI2DImr = 7872, X86_VMOVPDI2DIrr = 7873, X86_VMOVPQI2QIZmr = 7874, X86_VMOVPQI2QIZrr = 7875, X86_VMOVPQI2QImr = 7876, X86_VMOVPQI2QIrr = 7877, X86_VMOVPQIto64Zmr = 7878, X86_VMOVPQIto64Zrr = 7879, X86_VMOVPQIto64mr = 7880, X86_VMOVPQIto64rr = 7881, X86_VMOVQI2PQIZrm = 7882, X86_VMOVQI2PQIrm = 7883, X86_VMOVSDZmr = 7884, X86_VMOVSDZmrk = 7885, X86_VMOVSDZrm = 7886, X86_VMOVSDZrmk = 7887, X86_VMOVSDZrmkz = 7888, X86_VMOVSDZrr = 7889, X86_VMOVSDZrr_REV = 7890, X86_VMOVSDZrrk = 7891, X86_VMOVSDZrrk_REV = 7892, X86_VMOVSDZrrkz = 7893, X86_VMOVSDZrrkz_REV = 7894, X86_VMOVSDmr = 7895, X86_VMOVSDrm = 7896, X86_VMOVSDrr = 7897, X86_VMOVSDrr_REV = 7898, X86_VMOVSDto64Zmr = 7899, X86_VMOVSDto64Zrr = 7900, X86_VMOVSDto64mr = 7901, X86_VMOVSDto64rr = 7902, X86_VMOVSHDUPYrm = 7903, X86_VMOVSHDUPYrr = 7904, X86_VMOVSHDUPZ128rm = 7905, X86_VMOVSHDUPZ128rmk = 7906, X86_VMOVSHDUPZ128rmkz = 7907, X86_VMOVSHDUPZ128rr = 7908, X86_VMOVSHDUPZ128rrk = 7909, X86_VMOVSHDUPZ128rrkz = 7910, X86_VMOVSHDUPZ256rm = 7911, X86_VMOVSHDUPZ256rmk = 7912, X86_VMOVSHDUPZ256rmkz = 7913, X86_VMOVSHDUPZ256rr = 7914, X86_VMOVSHDUPZ256rrk = 7915, X86_VMOVSHDUPZ256rrkz = 7916, X86_VMOVSHDUPZrm = 7917, X86_VMOVSHDUPZrmk = 7918, X86_VMOVSHDUPZrmkz = 7919, X86_VMOVSHDUPZrr = 7920, X86_VMOVSHDUPZrrk = 7921, X86_VMOVSHDUPZrrkz = 7922, X86_VMOVSHDUPrm = 7923, X86_VMOVSHDUPrr = 7924, X86_VMOVSLDUPYrm = 7925, X86_VMOVSLDUPYrr = 7926, X86_VMOVSLDUPZ128rm = 7927, X86_VMOVSLDUPZ128rmk = 7928, X86_VMOVSLDUPZ128rmkz = 7929, X86_VMOVSLDUPZ128rr = 7930, X86_VMOVSLDUPZ128rrk = 7931, X86_VMOVSLDUPZ128rrkz = 7932, X86_VMOVSLDUPZ256rm = 7933, X86_VMOVSLDUPZ256rmk = 7934, X86_VMOVSLDUPZ256rmkz = 7935, X86_VMOVSLDUPZ256rr = 7936, X86_VMOVSLDUPZ256rrk = 7937, X86_VMOVSLDUPZ256rrkz = 7938, X86_VMOVSLDUPZrm = 7939, X86_VMOVSLDUPZrmk = 7940, X86_VMOVSLDUPZrmkz = 7941, X86_VMOVSLDUPZrr = 7942, X86_VMOVSLDUPZrrk = 7943, X86_VMOVSLDUPZrrkz = 7944, X86_VMOVSLDUPrm = 7945, X86_VMOVSLDUPrr = 7946, X86_VMOVSS2DIZmr = 7947, X86_VMOVSS2DIZrr = 7948, X86_VMOVSS2DImr = 7949, X86_VMOVSS2DIrr = 7950, X86_VMOVSSZmr = 7951, X86_VMOVSSZmrk = 7952, X86_VMOVSSZrm = 7953, X86_VMOVSSZrmk = 7954, X86_VMOVSSZrmkz = 7955, X86_VMOVSSZrr = 7956, X86_VMOVSSZrr_REV = 7957, X86_VMOVSSZrrk = 7958, X86_VMOVSSZrrk_REV = 7959, X86_VMOVSSZrrkz = 7960, X86_VMOVSSZrrkz_REV = 7961, X86_VMOVSSmr = 7962, X86_VMOVSSrm = 7963, X86_VMOVSSrr = 7964, X86_VMOVSSrr_REV = 7965, X86_VMOVUPDYmr = 7966, X86_VMOVUPDYrm = 7967, X86_VMOVUPDYrr = 7968, X86_VMOVUPDYrr_REV = 7969, X86_VMOVUPDZ128mr = 7970, X86_VMOVUPDZ128mrk = 7971, X86_VMOVUPDZ128rm = 7972, X86_VMOVUPDZ128rmk = 7973, X86_VMOVUPDZ128rmkz = 7974, X86_VMOVUPDZ128rr = 7975, X86_VMOVUPDZ128rr_REV = 7976, X86_VMOVUPDZ128rrk = 7977, X86_VMOVUPDZ128rrk_REV = 7978, X86_VMOVUPDZ128rrkz = 7979, X86_VMOVUPDZ128rrkz_REV = 7980, X86_VMOVUPDZ256mr = 7981, X86_VMOVUPDZ256mrk = 7982, X86_VMOVUPDZ256rm = 7983, X86_VMOVUPDZ256rmk = 7984, X86_VMOVUPDZ256rmkz = 7985, X86_VMOVUPDZ256rr = 7986, X86_VMOVUPDZ256rr_REV = 7987, X86_VMOVUPDZ256rrk = 7988, X86_VMOVUPDZ256rrk_REV = 7989, X86_VMOVUPDZ256rrkz = 7990, X86_VMOVUPDZ256rrkz_REV = 7991, X86_VMOVUPDZmr = 7992, X86_VMOVUPDZmrk = 7993, X86_VMOVUPDZrm = 7994, X86_VMOVUPDZrmk = 7995, X86_VMOVUPDZrmkz = 7996, X86_VMOVUPDZrr = 7997, X86_VMOVUPDZrr_REV = 7998, X86_VMOVUPDZrrk = 7999, X86_VMOVUPDZrrk_REV = 8000, X86_VMOVUPDZrrkz = 8001, X86_VMOVUPDZrrkz_REV = 8002, X86_VMOVUPDmr = 8003, X86_VMOVUPDrm = 8004, X86_VMOVUPDrr = 8005, X86_VMOVUPDrr_REV = 8006, X86_VMOVUPSYmr = 8007, X86_VMOVUPSYrm = 8008, X86_VMOVUPSYrr = 8009, X86_VMOVUPSYrr_REV = 8010, X86_VMOVUPSZ128mr = 8011, X86_VMOVUPSZ128mrk = 8012, X86_VMOVUPSZ128rm = 8013, X86_VMOVUPSZ128rmk = 8014, X86_VMOVUPSZ128rmkz = 8015, X86_VMOVUPSZ128rr = 8016, X86_VMOVUPSZ128rr_REV = 8017, X86_VMOVUPSZ128rrk = 8018, X86_VMOVUPSZ128rrk_REV = 8019, X86_VMOVUPSZ128rrkz = 8020, X86_VMOVUPSZ128rrkz_REV = 8021, X86_VMOVUPSZ256mr = 8022, X86_VMOVUPSZ256mrk = 8023, X86_VMOVUPSZ256rm = 8024, X86_VMOVUPSZ256rmk = 8025, X86_VMOVUPSZ256rmkz = 8026, X86_VMOVUPSZ256rr = 8027, X86_VMOVUPSZ256rr_REV = 8028, X86_VMOVUPSZ256rrk = 8029, X86_VMOVUPSZ256rrk_REV = 8030, X86_VMOVUPSZ256rrkz = 8031, X86_VMOVUPSZ256rrkz_REV = 8032, X86_VMOVUPSZmr = 8033, X86_VMOVUPSZmrk = 8034, X86_VMOVUPSZrm = 8035, X86_VMOVUPSZrmk = 8036, X86_VMOVUPSZrmkz = 8037, X86_VMOVUPSZrr = 8038, X86_VMOVUPSZrr_REV = 8039, X86_VMOVUPSZrrk = 8040, X86_VMOVUPSZrrk_REV = 8041, X86_VMOVUPSZrrkz = 8042, X86_VMOVUPSZrrkz_REV = 8043, X86_VMOVUPSmr = 8044, X86_VMOVUPSrm = 8045, X86_VMOVUPSrr = 8046, X86_VMOVUPSrr_REV = 8047, X86_VMOVZPQILo2PQIZrr = 8048, X86_VMOVZPQILo2PQIrr = 8049, X86_VMPSADBWYrmi = 8050, X86_VMPSADBWYrri = 8051, X86_VMPSADBWrmi = 8052, X86_VMPSADBWrri = 8053, X86_VMPTRLDm = 8054, X86_VMPTRSTm = 8055, X86_VMREAD32mr = 8056, X86_VMREAD32rr = 8057, X86_VMREAD64mr = 8058, X86_VMREAD64rr = 8059, X86_VMRESUME = 8060, X86_VMRUN32 = 8061, X86_VMRUN64 = 8062, X86_VMSAVE32 = 8063, X86_VMSAVE64 = 8064, X86_VMULPDYrm = 8065, X86_VMULPDYrr = 8066, X86_VMULPDZ128rm = 8067, X86_VMULPDZ128rmb = 8068, X86_VMULPDZ128rmbk = 8069, X86_VMULPDZ128rmbkz = 8070, X86_VMULPDZ128rmk = 8071, X86_VMULPDZ128rmkz = 8072, X86_VMULPDZ128rr = 8073, X86_VMULPDZ128rrk = 8074, X86_VMULPDZ128rrkz = 8075, X86_VMULPDZ256rm = 8076, X86_VMULPDZ256rmb = 8077, X86_VMULPDZ256rmbk = 8078, X86_VMULPDZ256rmbkz = 8079, X86_VMULPDZ256rmk = 8080, X86_VMULPDZ256rmkz = 8081, X86_VMULPDZ256rr = 8082, X86_VMULPDZ256rrk = 8083, X86_VMULPDZ256rrkz = 8084, X86_VMULPDZrm = 8085, X86_VMULPDZrmb = 8086, X86_VMULPDZrmbk = 8087, X86_VMULPDZrmbkz = 8088, X86_VMULPDZrmk = 8089, X86_VMULPDZrmkz = 8090, X86_VMULPDZrr = 8091, X86_VMULPDZrrb = 8092, X86_VMULPDZrrbk = 8093, X86_VMULPDZrrbkz = 8094, X86_VMULPDZrrk = 8095, X86_VMULPDZrrkz = 8096, X86_VMULPDrm = 8097, X86_VMULPDrr = 8098, X86_VMULPSYrm = 8099, X86_VMULPSYrr = 8100, X86_VMULPSZ128rm = 8101, X86_VMULPSZ128rmb = 8102, X86_VMULPSZ128rmbk = 8103, X86_VMULPSZ128rmbkz = 8104, X86_VMULPSZ128rmk = 8105, X86_VMULPSZ128rmkz = 8106, X86_VMULPSZ128rr = 8107, X86_VMULPSZ128rrk = 8108, X86_VMULPSZ128rrkz = 8109, X86_VMULPSZ256rm = 8110, X86_VMULPSZ256rmb = 8111, X86_VMULPSZ256rmbk = 8112, X86_VMULPSZ256rmbkz = 8113, X86_VMULPSZ256rmk = 8114, X86_VMULPSZ256rmkz = 8115, X86_VMULPSZ256rr = 8116, X86_VMULPSZ256rrk = 8117, X86_VMULPSZ256rrkz = 8118, X86_VMULPSZrm = 8119, X86_VMULPSZrmb = 8120, X86_VMULPSZrmbk = 8121, X86_VMULPSZrmbkz = 8122, X86_VMULPSZrmk = 8123, X86_VMULPSZrmkz = 8124, X86_VMULPSZrr = 8125, X86_VMULPSZrrb = 8126, X86_VMULPSZrrbk = 8127, X86_VMULPSZrrbkz = 8128, X86_VMULPSZrrk = 8129, X86_VMULPSZrrkz = 8130, X86_VMULPSrm = 8131, X86_VMULPSrr = 8132, X86_VMULSDZrm = 8133, X86_VMULSDZrm_Int = 8134, X86_VMULSDZrm_Intk = 8135, X86_VMULSDZrm_Intkz = 8136, X86_VMULSDZrr = 8137, X86_VMULSDZrr_Int = 8138, X86_VMULSDZrr_Intk = 8139, X86_VMULSDZrr_Intkz = 8140, X86_VMULSDZrrb_Int = 8141, X86_VMULSDZrrb_Intk = 8142, X86_VMULSDZrrb_Intkz = 8143, X86_VMULSDrm = 8144, X86_VMULSDrm_Int = 8145, X86_VMULSDrr = 8146, X86_VMULSDrr_Int = 8147, X86_VMULSSZrm = 8148, X86_VMULSSZrm_Int = 8149, X86_VMULSSZrm_Intk = 8150, X86_VMULSSZrm_Intkz = 8151, X86_VMULSSZrr = 8152, X86_VMULSSZrr_Int = 8153, X86_VMULSSZrr_Intk = 8154, X86_VMULSSZrr_Intkz = 8155, X86_VMULSSZrrb_Int = 8156, X86_VMULSSZrrb_Intk = 8157, X86_VMULSSZrrb_Intkz = 8158, X86_VMULSSrm = 8159, X86_VMULSSrm_Int = 8160, X86_VMULSSrr = 8161, X86_VMULSSrr_Int = 8162, X86_VMWRITE32rm = 8163, X86_VMWRITE32rr = 8164, X86_VMWRITE64rm = 8165, X86_VMWRITE64rr = 8166, X86_VMXOFF = 8167, X86_VMXON = 8168, X86_VORPDYrm = 8169, X86_VORPDYrr = 8170, X86_VORPDZ128rm = 8171, X86_VORPDZ128rmb = 8172, X86_VORPDZ128rmbk = 8173, X86_VORPDZ128rmbkz = 8174, X86_VORPDZ128rmk = 8175, X86_VORPDZ128rmkz = 8176, X86_VORPDZ128rr = 8177, X86_VORPDZ128rrk = 8178, X86_VORPDZ128rrkz = 8179, X86_VORPDZ256rm = 8180, X86_VORPDZ256rmb = 8181, X86_VORPDZ256rmbk = 8182, X86_VORPDZ256rmbkz = 8183, X86_VORPDZ256rmk = 8184, X86_VORPDZ256rmkz = 8185, X86_VORPDZ256rr = 8186, X86_VORPDZ256rrk = 8187, X86_VORPDZ256rrkz = 8188, X86_VORPDZrm = 8189, X86_VORPDZrmb = 8190, X86_VORPDZrmbk = 8191, X86_VORPDZrmbkz = 8192, X86_VORPDZrmk = 8193, X86_VORPDZrmkz = 8194, X86_VORPDZrr = 8195, X86_VORPDZrrk = 8196, X86_VORPDZrrkz = 8197, X86_VORPDrm = 8198, X86_VORPDrr = 8199, X86_VORPSYrm = 8200, X86_VORPSYrr = 8201, X86_VORPSZ128rm = 8202, X86_VORPSZ128rmb = 8203, X86_VORPSZ128rmbk = 8204, X86_VORPSZ128rmbkz = 8205, X86_VORPSZ128rmk = 8206, X86_VORPSZ128rmkz = 8207, X86_VORPSZ128rr = 8208, X86_VORPSZ128rrk = 8209, X86_VORPSZ128rrkz = 8210, X86_VORPSZ256rm = 8211, X86_VORPSZ256rmb = 8212, X86_VORPSZ256rmbk = 8213, X86_VORPSZ256rmbkz = 8214, X86_VORPSZ256rmk = 8215, X86_VORPSZ256rmkz = 8216, X86_VORPSZ256rr = 8217, X86_VORPSZ256rrk = 8218, X86_VORPSZ256rrkz = 8219, X86_VORPSZrm = 8220, X86_VORPSZrmb = 8221, X86_VORPSZrmbk = 8222, X86_VORPSZrmbkz = 8223, X86_VORPSZrmk = 8224, X86_VORPSZrmkz = 8225, X86_VORPSZrr = 8226, X86_VORPSZrrk = 8227, X86_VORPSZrrkz = 8228, X86_VORPSrm = 8229, X86_VORPSrr = 8230, X86_VP4DPWSSDSrm = 8231, X86_VP4DPWSSDSrmk = 8232, X86_VP4DPWSSDSrmkz = 8233, X86_VP4DPWSSDrm = 8234, X86_VP4DPWSSDrmk = 8235, X86_VP4DPWSSDrmkz = 8236, X86_VPABSBYrm = 8237, X86_VPABSBYrr = 8238, X86_VPABSBZ128rm = 8239, X86_VPABSBZ128rmk = 8240, X86_VPABSBZ128rmkz = 8241, X86_VPABSBZ128rr = 8242, X86_VPABSBZ128rrk = 8243, X86_VPABSBZ128rrkz = 8244, X86_VPABSBZ256rm = 8245, X86_VPABSBZ256rmk = 8246, X86_VPABSBZ256rmkz = 8247, X86_VPABSBZ256rr = 8248, X86_VPABSBZ256rrk = 8249, X86_VPABSBZ256rrkz = 8250, X86_VPABSBZrm = 8251, X86_VPABSBZrmk = 8252, X86_VPABSBZrmkz = 8253, X86_VPABSBZrr = 8254, X86_VPABSBZrrk = 8255, X86_VPABSBZrrkz = 8256, X86_VPABSBrm = 8257, X86_VPABSBrr = 8258, X86_VPABSDYrm = 8259, X86_VPABSDYrr = 8260, X86_VPABSDZ128rm = 8261, X86_VPABSDZ128rmb = 8262, X86_VPABSDZ128rmbk = 8263, X86_VPABSDZ128rmbkz = 8264, X86_VPABSDZ128rmk = 8265, X86_VPABSDZ128rmkz = 8266, X86_VPABSDZ128rr = 8267, X86_VPABSDZ128rrk = 8268, X86_VPABSDZ128rrkz = 8269, X86_VPABSDZ256rm = 8270, X86_VPABSDZ256rmb = 8271, X86_VPABSDZ256rmbk = 8272, X86_VPABSDZ256rmbkz = 8273, X86_VPABSDZ256rmk = 8274, X86_VPABSDZ256rmkz = 8275, X86_VPABSDZ256rr = 8276, X86_VPABSDZ256rrk = 8277, X86_VPABSDZ256rrkz = 8278, X86_VPABSDZrm = 8279, X86_VPABSDZrmb = 8280, X86_VPABSDZrmbk = 8281, X86_VPABSDZrmbkz = 8282, X86_VPABSDZrmk = 8283, X86_VPABSDZrmkz = 8284, X86_VPABSDZrr = 8285, X86_VPABSDZrrk = 8286, X86_VPABSDZrrkz = 8287, X86_VPABSDrm = 8288, X86_VPABSDrr = 8289, X86_VPABSQZ128rm = 8290, X86_VPABSQZ128rmb = 8291, X86_VPABSQZ128rmbk = 8292, X86_VPABSQZ128rmbkz = 8293, X86_VPABSQZ128rmk = 8294, X86_VPABSQZ128rmkz = 8295, X86_VPABSQZ128rr = 8296, X86_VPABSQZ128rrk = 8297, X86_VPABSQZ128rrkz = 8298, X86_VPABSQZ256rm = 8299, X86_VPABSQZ256rmb = 8300, X86_VPABSQZ256rmbk = 8301, X86_VPABSQZ256rmbkz = 8302, X86_VPABSQZ256rmk = 8303, X86_VPABSQZ256rmkz = 8304, X86_VPABSQZ256rr = 8305, X86_VPABSQZ256rrk = 8306, X86_VPABSQZ256rrkz = 8307, X86_VPABSQZrm = 8308, X86_VPABSQZrmb = 8309, X86_VPABSQZrmbk = 8310, X86_VPABSQZrmbkz = 8311, X86_VPABSQZrmk = 8312, X86_VPABSQZrmkz = 8313, X86_VPABSQZrr = 8314, X86_VPABSQZrrk = 8315, X86_VPABSQZrrkz = 8316, X86_VPABSWYrm = 8317, X86_VPABSWYrr = 8318, X86_VPABSWZ128rm = 8319, X86_VPABSWZ128rmk = 8320, X86_VPABSWZ128rmkz = 8321, X86_VPABSWZ128rr = 8322, X86_VPABSWZ128rrk = 8323, X86_VPABSWZ128rrkz = 8324, X86_VPABSWZ256rm = 8325, X86_VPABSWZ256rmk = 8326, X86_VPABSWZ256rmkz = 8327, X86_VPABSWZ256rr = 8328, X86_VPABSWZ256rrk = 8329, X86_VPABSWZ256rrkz = 8330, X86_VPABSWZrm = 8331, X86_VPABSWZrmk = 8332, X86_VPABSWZrmkz = 8333, X86_VPABSWZrr = 8334, X86_VPABSWZrrk = 8335, X86_VPABSWZrrkz = 8336, X86_VPABSWrm = 8337, X86_VPABSWrr = 8338, X86_VPACKSSDWYrm = 8339, X86_VPACKSSDWYrr = 8340, X86_VPACKSSDWZ128rm = 8341, X86_VPACKSSDWZ128rmb = 8342, X86_VPACKSSDWZ128rmbk = 8343, X86_VPACKSSDWZ128rmbkz = 8344, X86_VPACKSSDWZ128rmk = 8345, X86_VPACKSSDWZ128rmkz = 8346, X86_VPACKSSDWZ128rr = 8347, X86_VPACKSSDWZ128rrk = 8348, X86_VPACKSSDWZ128rrkz = 8349, X86_VPACKSSDWZ256rm = 8350, X86_VPACKSSDWZ256rmb = 8351, X86_VPACKSSDWZ256rmbk = 8352, X86_VPACKSSDWZ256rmbkz = 8353, X86_VPACKSSDWZ256rmk = 8354, X86_VPACKSSDWZ256rmkz = 8355, X86_VPACKSSDWZ256rr = 8356, X86_VPACKSSDWZ256rrk = 8357, X86_VPACKSSDWZ256rrkz = 8358, X86_VPACKSSDWZrm = 8359, X86_VPACKSSDWZrmb = 8360, X86_VPACKSSDWZrmbk = 8361, X86_VPACKSSDWZrmbkz = 8362, X86_VPACKSSDWZrmk = 8363, X86_VPACKSSDWZrmkz = 8364, X86_VPACKSSDWZrr = 8365, X86_VPACKSSDWZrrk = 8366, X86_VPACKSSDWZrrkz = 8367, X86_VPACKSSDWrm = 8368, X86_VPACKSSDWrr = 8369, X86_VPACKSSWBYrm = 8370, X86_VPACKSSWBYrr = 8371, X86_VPACKSSWBZ128rm = 8372, X86_VPACKSSWBZ128rmk = 8373, X86_VPACKSSWBZ128rmkz = 8374, X86_VPACKSSWBZ128rr = 8375, X86_VPACKSSWBZ128rrk = 8376, X86_VPACKSSWBZ128rrkz = 8377, X86_VPACKSSWBZ256rm = 8378, X86_VPACKSSWBZ256rmk = 8379, X86_VPACKSSWBZ256rmkz = 8380, X86_VPACKSSWBZ256rr = 8381, X86_VPACKSSWBZ256rrk = 8382, X86_VPACKSSWBZ256rrkz = 8383, X86_VPACKSSWBZrm = 8384, X86_VPACKSSWBZrmk = 8385, X86_VPACKSSWBZrmkz = 8386, X86_VPACKSSWBZrr = 8387, X86_VPACKSSWBZrrk = 8388, X86_VPACKSSWBZrrkz = 8389, X86_VPACKSSWBrm = 8390, X86_VPACKSSWBrr = 8391, X86_VPACKUSDWYrm = 8392, X86_VPACKUSDWYrr = 8393, X86_VPACKUSDWZ128rm = 8394, X86_VPACKUSDWZ128rmb = 8395, X86_VPACKUSDWZ128rmbk = 8396, X86_VPACKUSDWZ128rmbkz = 8397, X86_VPACKUSDWZ128rmk = 8398, X86_VPACKUSDWZ128rmkz = 8399, X86_VPACKUSDWZ128rr = 8400, X86_VPACKUSDWZ128rrk = 8401, X86_VPACKUSDWZ128rrkz = 8402, X86_VPACKUSDWZ256rm = 8403, X86_VPACKUSDWZ256rmb = 8404, X86_VPACKUSDWZ256rmbk = 8405, X86_VPACKUSDWZ256rmbkz = 8406, X86_VPACKUSDWZ256rmk = 8407, X86_VPACKUSDWZ256rmkz = 8408, X86_VPACKUSDWZ256rr = 8409, X86_VPACKUSDWZ256rrk = 8410, X86_VPACKUSDWZ256rrkz = 8411, X86_VPACKUSDWZrm = 8412, X86_VPACKUSDWZrmb = 8413, X86_VPACKUSDWZrmbk = 8414, X86_VPACKUSDWZrmbkz = 8415, X86_VPACKUSDWZrmk = 8416, X86_VPACKUSDWZrmkz = 8417, X86_VPACKUSDWZrr = 8418, X86_VPACKUSDWZrrk = 8419, X86_VPACKUSDWZrrkz = 8420, X86_VPACKUSDWrm = 8421, X86_VPACKUSDWrr = 8422, X86_VPACKUSWBYrm = 8423, X86_VPACKUSWBYrr = 8424, X86_VPACKUSWBZ128rm = 8425, X86_VPACKUSWBZ128rmk = 8426, X86_VPACKUSWBZ128rmkz = 8427, X86_VPACKUSWBZ128rr = 8428, X86_VPACKUSWBZ128rrk = 8429, X86_VPACKUSWBZ128rrkz = 8430, X86_VPACKUSWBZ256rm = 8431, X86_VPACKUSWBZ256rmk = 8432, X86_VPACKUSWBZ256rmkz = 8433, X86_VPACKUSWBZ256rr = 8434, X86_VPACKUSWBZ256rrk = 8435, X86_VPACKUSWBZ256rrkz = 8436, X86_VPACKUSWBZrm = 8437, X86_VPACKUSWBZrmk = 8438, X86_VPACKUSWBZrmkz = 8439, X86_VPACKUSWBZrr = 8440, X86_VPACKUSWBZrrk = 8441, X86_VPACKUSWBZrrkz = 8442, X86_VPACKUSWBrm = 8443, X86_VPACKUSWBrr = 8444, X86_VPADDBYrm = 8445, X86_VPADDBYrr = 8446, X86_VPADDBZ128rm = 8447, X86_VPADDBZ128rmk = 8448, X86_VPADDBZ128rmkz = 8449, X86_VPADDBZ128rr = 8450, X86_VPADDBZ128rrk = 8451, X86_VPADDBZ128rrkz = 8452, X86_VPADDBZ256rm = 8453, X86_VPADDBZ256rmk = 8454, X86_VPADDBZ256rmkz = 8455, X86_VPADDBZ256rr = 8456, X86_VPADDBZ256rrk = 8457, X86_VPADDBZ256rrkz = 8458, X86_VPADDBZrm = 8459, X86_VPADDBZrmk = 8460, X86_VPADDBZrmkz = 8461, X86_VPADDBZrr = 8462, X86_VPADDBZrrk = 8463, X86_VPADDBZrrkz = 8464, X86_VPADDBrm = 8465, X86_VPADDBrr = 8466, X86_VPADDDYrm = 8467, X86_VPADDDYrr = 8468, X86_VPADDDZ128rm = 8469, X86_VPADDDZ128rmb = 8470, X86_VPADDDZ128rmbk = 8471, X86_VPADDDZ128rmbkz = 8472, X86_VPADDDZ128rmk = 8473, X86_VPADDDZ128rmkz = 8474, X86_VPADDDZ128rr = 8475, X86_VPADDDZ128rrk = 8476, X86_VPADDDZ128rrkz = 8477, X86_VPADDDZ256rm = 8478, X86_VPADDDZ256rmb = 8479, X86_VPADDDZ256rmbk = 8480, X86_VPADDDZ256rmbkz = 8481, X86_VPADDDZ256rmk = 8482, X86_VPADDDZ256rmkz = 8483, X86_VPADDDZ256rr = 8484, X86_VPADDDZ256rrk = 8485, X86_VPADDDZ256rrkz = 8486, X86_VPADDDZrm = 8487, X86_VPADDDZrmb = 8488, X86_VPADDDZrmbk = 8489, X86_VPADDDZrmbkz = 8490, X86_VPADDDZrmk = 8491, X86_VPADDDZrmkz = 8492, X86_VPADDDZrr = 8493, X86_VPADDDZrrk = 8494, X86_VPADDDZrrkz = 8495, X86_VPADDDrm = 8496, X86_VPADDDrr = 8497, X86_VPADDQYrm = 8498, X86_VPADDQYrr = 8499, X86_VPADDQZ128rm = 8500, X86_VPADDQZ128rmb = 8501, X86_VPADDQZ128rmbk = 8502, X86_VPADDQZ128rmbkz = 8503, X86_VPADDQZ128rmk = 8504, X86_VPADDQZ128rmkz = 8505, X86_VPADDQZ128rr = 8506, X86_VPADDQZ128rrk = 8507, X86_VPADDQZ128rrkz = 8508, X86_VPADDQZ256rm = 8509, X86_VPADDQZ256rmb = 8510, X86_VPADDQZ256rmbk = 8511, X86_VPADDQZ256rmbkz = 8512, X86_VPADDQZ256rmk = 8513, X86_VPADDQZ256rmkz = 8514, X86_VPADDQZ256rr = 8515, X86_VPADDQZ256rrk = 8516, X86_VPADDQZ256rrkz = 8517, X86_VPADDQZrm = 8518, X86_VPADDQZrmb = 8519, X86_VPADDQZrmbk = 8520, X86_VPADDQZrmbkz = 8521, X86_VPADDQZrmk = 8522, X86_VPADDQZrmkz = 8523, X86_VPADDQZrr = 8524, X86_VPADDQZrrk = 8525, X86_VPADDQZrrkz = 8526, X86_VPADDQrm = 8527, X86_VPADDQrr = 8528, X86_VPADDSBYrm = 8529, X86_VPADDSBYrr = 8530, X86_VPADDSBZ128rm = 8531, X86_VPADDSBZ128rmk = 8532, X86_VPADDSBZ128rmkz = 8533, X86_VPADDSBZ128rr = 8534, X86_VPADDSBZ128rrk = 8535, X86_VPADDSBZ128rrkz = 8536, X86_VPADDSBZ256rm = 8537, X86_VPADDSBZ256rmk = 8538, X86_VPADDSBZ256rmkz = 8539, X86_VPADDSBZ256rr = 8540, X86_VPADDSBZ256rrk = 8541, X86_VPADDSBZ256rrkz = 8542, X86_VPADDSBZrm = 8543, X86_VPADDSBZrmk = 8544, X86_VPADDSBZrmkz = 8545, X86_VPADDSBZrr = 8546, X86_VPADDSBZrrk = 8547, X86_VPADDSBZrrkz = 8548, X86_VPADDSBrm = 8549, X86_VPADDSBrr = 8550, X86_VPADDSWYrm = 8551, X86_VPADDSWYrr = 8552, X86_VPADDSWZ128rm = 8553, X86_VPADDSWZ128rmk = 8554, X86_VPADDSWZ128rmkz = 8555, X86_VPADDSWZ128rr = 8556, X86_VPADDSWZ128rrk = 8557, X86_VPADDSWZ128rrkz = 8558, X86_VPADDSWZ256rm = 8559, X86_VPADDSWZ256rmk = 8560, X86_VPADDSWZ256rmkz = 8561, X86_VPADDSWZ256rr = 8562, X86_VPADDSWZ256rrk = 8563, X86_VPADDSWZ256rrkz = 8564, X86_VPADDSWZrm = 8565, X86_VPADDSWZrmk = 8566, X86_VPADDSWZrmkz = 8567, X86_VPADDSWZrr = 8568, X86_VPADDSWZrrk = 8569, X86_VPADDSWZrrkz = 8570, X86_VPADDSWrm = 8571, X86_VPADDSWrr = 8572, X86_VPADDUSBYrm = 8573, X86_VPADDUSBYrr = 8574, X86_VPADDUSBZ128rm = 8575, X86_VPADDUSBZ128rmk = 8576, X86_VPADDUSBZ128rmkz = 8577, X86_VPADDUSBZ128rr = 8578, X86_VPADDUSBZ128rrk = 8579, X86_VPADDUSBZ128rrkz = 8580, X86_VPADDUSBZ256rm = 8581, X86_VPADDUSBZ256rmk = 8582, X86_VPADDUSBZ256rmkz = 8583, X86_VPADDUSBZ256rr = 8584, X86_VPADDUSBZ256rrk = 8585, X86_VPADDUSBZ256rrkz = 8586, X86_VPADDUSBZrm = 8587, X86_VPADDUSBZrmk = 8588, X86_VPADDUSBZrmkz = 8589, X86_VPADDUSBZrr = 8590, X86_VPADDUSBZrrk = 8591, X86_VPADDUSBZrrkz = 8592, X86_VPADDUSBrm = 8593, X86_VPADDUSBrr = 8594, X86_VPADDUSWYrm = 8595, X86_VPADDUSWYrr = 8596, X86_VPADDUSWZ128rm = 8597, X86_VPADDUSWZ128rmk = 8598, X86_VPADDUSWZ128rmkz = 8599, X86_VPADDUSWZ128rr = 8600, X86_VPADDUSWZ128rrk = 8601, X86_VPADDUSWZ128rrkz = 8602, X86_VPADDUSWZ256rm = 8603, X86_VPADDUSWZ256rmk = 8604, X86_VPADDUSWZ256rmkz = 8605, X86_VPADDUSWZ256rr = 8606, X86_VPADDUSWZ256rrk = 8607, X86_VPADDUSWZ256rrkz = 8608, X86_VPADDUSWZrm = 8609, X86_VPADDUSWZrmk = 8610, X86_VPADDUSWZrmkz = 8611, X86_VPADDUSWZrr = 8612, X86_VPADDUSWZrrk = 8613, X86_VPADDUSWZrrkz = 8614, X86_VPADDUSWrm = 8615, X86_VPADDUSWrr = 8616, X86_VPADDWYrm = 8617, X86_VPADDWYrr = 8618, X86_VPADDWZ128rm = 8619, X86_VPADDWZ128rmk = 8620, X86_VPADDWZ128rmkz = 8621, X86_VPADDWZ128rr = 8622, X86_VPADDWZ128rrk = 8623, X86_VPADDWZ128rrkz = 8624, X86_VPADDWZ256rm = 8625, X86_VPADDWZ256rmk = 8626, X86_VPADDWZ256rmkz = 8627, X86_VPADDWZ256rr = 8628, X86_VPADDWZ256rrk = 8629, X86_VPADDWZ256rrkz = 8630, X86_VPADDWZrm = 8631, X86_VPADDWZrmk = 8632, X86_VPADDWZrmkz = 8633, X86_VPADDWZrr = 8634, X86_VPADDWZrrk = 8635, X86_VPADDWZrrkz = 8636, X86_VPADDWrm = 8637, X86_VPADDWrr = 8638, X86_VPALIGNRYrmi = 8639, X86_VPALIGNRYrri = 8640, X86_VPALIGNRZ128rmi = 8641, X86_VPALIGNRZ128rmik = 8642, X86_VPALIGNRZ128rmikz = 8643, X86_VPALIGNRZ128rri = 8644, X86_VPALIGNRZ128rrik = 8645, X86_VPALIGNRZ128rrikz = 8646, X86_VPALIGNRZ256rmi = 8647, X86_VPALIGNRZ256rmik = 8648, X86_VPALIGNRZ256rmikz = 8649, X86_VPALIGNRZ256rri = 8650, X86_VPALIGNRZ256rrik = 8651, X86_VPALIGNRZ256rrikz = 8652, X86_VPALIGNRZrmi = 8653, X86_VPALIGNRZrmik = 8654, X86_VPALIGNRZrmikz = 8655, X86_VPALIGNRZrri = 8656, X86_VPALIGNRZrrik = 8657, X86_VPALIGNRZrrikz = 8658, X86_VPALIGNRrmi = 8659, X86_VPALIGNRrri = 8660, X86_VPANDDZ128rm = 8661, X86_VPANDDZ128rmb = 8662, X86_VPANDDZ128rmbk = 8663, X86_VPANDDZ128rmbkz = 8664, X86_VPANDDZ128rmk = 8665, X86_VPANDDZ128rmkz = 8666, X86_VPANDDZ128rr = 8667, X86_VPANDDZ128rrk = 8668, X86_VPANDDZ128rrkz = 8669, X86_VPANDDZ256rm = 8670, X86_VPANDDZ256rmb = 8671, X86_VPANDDZ256rmbk = 8672, X86_VPANDDZ256rmbkz = 8673, X86_VPANDDZ256rmk = 8674, X86_VPANDDZ256rmkz = 8675, X86_VPANDDZ256rr = 8676, X86_VPANDDZ256rrk = 8677, X86_VPANDDZ256rrkz = 8678, X86_VPANDDZrm = 8679, X86_VPANDDZrmb = 8680, X86_VPANDDZrmbk = 8681, X86_VPANDDZrmbkz = 8682, X86_VPANDDZrmk = 8683, X86_VPANDDZrmkz = 8684, X86_VPANDDZrr = 8685, X86_VPANDDZrrk = 8686, X86_VPANDDZrrkz = 8687, X86_VPANDNDZ128rm = 8688, X86_VPANDNDZ128rmb = 8689, X86_VPANDNDZ128rmbk = 8690, X86_VPANDNDZ128rmbkz = 8691, X86_VPANDNDZ128rmk = 8692, X86_VPANDNDZ128rmkz = 8693, X86_VPANDNDZ128rr = 8694, X86_VPANDNDZ128rrk = 8695, X86_VPANDNDZ128rrkz = 8696, X86_VPANDNDZ256rm = 8697, X86_VPANDNDZ256rmb = 8698, X86_VPANDNDZ256rmbk = 8699, X86_VPANDNDZ256rmbkz = 8700, X86_VPANDNDZ256rmk = 8701, X86_VPANDNDZ256rmkz = 8702, X86_VPANDNDZ256rr = 8703, X86_VPANDNDZ256rrk = 8704, X86_VPANDNDZ256rrkz = 8705, X86_VPANDNDZrm = 8706, X86_VPANDNDZrmb = 8707, X86_VPANDNDZrmbk = 8708, X86_VPANDNDZrmbkz = 8709, X86_VPANDNDZrmk = 8710, X86_VPANDNDZrmkz = 8711, X86_VPANDNDZrr = 8712, X86_VPANDNDZrrk = 8713, X86_VPANDNDZrrkz = 8714, X86_VPANDNQZ128rm = 8715, X86_VPANDNQZ128rmb = 8716, X86_VPANDNQZ128rmbk = 8717, X86_VPANDNQZ128rmbkz = 8718, X86_VPANDNQZ128rmk = 8719, X86_VPANDNQZ128rmkz = 8720, X86_VPANDNQZ128rr = 8721, X86_VPANDNQZ128rrk = 8722, X86_VPANDNQZ128rrkz = 8723, X86_VPANDNQZ256rm = 8724, X86_VPANDNQZ256rmb = 8725, X86_VPANDNQZ256rmbk = 8726, X86_VPANDNQZ256rmbkz = 8727, X86_VPANDNQZ256rmk = 8728, X86_VPANDNQZ256rmkz = 8729, X86_VPANDNQZ256rr = 8730, X86_VPANDNQZ256rrk = 8731, X86_VPANDNQZ256rrkz = 8732, X86_VPANDNQZrm = 8733, X86_VPANDNQZrmb = 8734, X86_VPANDNQZrmbk = 8735, X86_VPANDNQZrmbkz = 8736, X86_VPANDNQZrmk = 8737, X86_VPANDNQZrmkz = 8738, X86_VPANDNQZrr = 8739, X86_VPANDNQZrrk = 8740, X86_VPANDNQZrrkz = 8741, X86_VPANDNYrm = 8742, X86_VPANDNYrr = 8743, X86_VPANDNrm = 8744, X86_VPANDNrr = 8745, X86_VPANDQZ128rm = 8746, X86_VPANDQZ128rmb = 8747, X86_VPANDQZ128rmbk = 8748, X86_VPANDQZ128rmbkz = 8749, X86_VPANDQZ128rmk = 8750, X86_VPANDQZ128rmkz = 8751, X86_VPANDQZ128rr = 8752, X86_VPANDQZ128rrk = 8753, X86_VPANDQZ128rrkz = 8754, X86_VPANDQZ256rm = 8755, X86_VPANDQZ256rmb = 8756, X86_VPANDQZ256rmbk = 8757, X86_VPANDQZ256rmbkz = 8758, X86_VPANDQZ256rmk = 8759, X86_VPANDQZ256rmkz = 8760, X86_VPANDQZ256rr = 8761, X86_VPANDQZ256rrk = 8762, X86_VPANDQZ256rrkz = 8763, X86_VPANDQZrm = 8764, X86_VPANDQZrmb = 8765, X86_VPANDQZrmbk = 8766, X86_VPANDQZrmbkz = 8767, X86_VPANDQZrmk = 8768, X86_VPANDQZrmkz = 8769, X86_VPANDQZrr = 8770, X86_VPANDQZrrk = 8771, X86_VPANDQZrrkz = 8772, X86_VPANDYrm = 8773, X86_VPANDYrr = 8774, X86_VPANDrm = 8775, X86_VPANDrr = 8776, X86_VPAVGBYrm = 8777, X86_VPAVGBYrr = 8778, X86_VPAVGBZ128rm = 8779, X86_VPAVGBZ128rmk = 8780, X86_VPAVGBZ128rmkz = 8781, X86_VPAVGBZ128rr = 8782, X86_VPAVGBZ128rrk = 8783, X86_VPAVGBZ128rrkz = 8784, X86_VPAVGBZ256rm = 8785, X86_VPAVGBZ256rmk = 8786, X86_VPAVGBZ256rmkz = 8787, X86_VPAVGBZ256rr = 8788, X86_VPAVGBZ256rrk = 8789, X86_VPAVGBZ256rrkz = 8790, X86_VPAVGBZrm = 8791, X86_VPAVGBZrmk = 8792, X86_VPAVGBZrmkz = 8793, X86_VPAVGBZrr = 8794, X86_VPAVGBZrrk = 8795, X86_VPAVGBZrrkz = 8796, X86_VPAVGBrm = 8797, X86_VPAVGBrr = 8798, X86_VPAVGWYrm = 8799, X86_VPAVGWYrr = 8800, X86_VPAVGWZ128rm = 8801, X86_VPAVGWZ128rmk = 8802, X86_VPAVGWZ128rmkz = 8803, X86_VPAVGWZ128rr = 8804, X86_VPAVGWZ128rrk = 8805, X86_VPAVGWZ128rrkz = 8806, X86_VPAVGWZ256rm = 8807, X86_VPAVGWZ256rmk = 8808, X86_VPAVGWZ256rmkz = 8809, X86_VPAVGWZ256rr = 8810, X86_VPAVGWZ256rrk = 8811, X86_VPAVGWZ256rrkz = 8812, X86_VPAVGWZrm = 8813, X86_VPAVGWZrmk = 8814, X86_VPAVGWZrmkz = 8815, X86_VPAVGWZrr = 8816, X86_VPAVGWZrrk = 8817, X86_VPAVGWZrrkz = 8818, X86_VPAVGWrm = 8819, X86_VPAVGWrr = 8820, X86_VPBLENDDYrmi = 8821, X86_VPBLENDDYrri = 8822, X86_VPBLENDDrmi = 8823, X86_VPBLENDDrri = 8824, X86_VPBLENDMBZ128rm = 8825, X86_VPBLENDMBZ128rmk = 8826, X86_VPBLENDMBZ128rmkz = 8827, X86_VPBLENDMBZ128rr = 8828, X86_VPBLENDMBZ128rrk = 8829, X86_VPBLENDMBZ128rrkz = 8830, X86_VPBLENDMBZ256rm = 8831, X86_VPBLENDMBZ256rmk = 8832, X86_VPBLENDMBZ256rmkz = 8833, X86_VPBLENDMBZ256rr = 8834, X86_VPBLENDMBZ256rrk = 8835, X86_VPBLENDMBZ256rrkz = 8836, X86_VPBLENDMBZrm = 8837, X86_VPBLENDMBZrmk = 8838, X86_VPBLENDMBZrmkz = 8839, X86_VPBLENDMBZrr = 8840, X86_VPBLENDMBZrrk = 8841, X86_VPBLENDMBZrrkz = 8842, X86_VPBLENDMDZ128rm = 8843, X86_VPBLENDMDZ128rmb = 8844, X86_VPBLENDMDZ128rmbk = 8845, X86_VPBLENDMDZ128rmbkz = 8846, X86_VPBLENDMDZ128rmk = 8847, X86_VPBLENDMDZ128rmkz = 8848, X86_VPBLENDMDZ128rr = 8849, X86_VPBLENDMDZ128rrk = 8850, X86_VPBLENDMDZ128rrkz = 8851, X86_VPBLENDMDZ256rm = 8852, X86_VPBLENDMDZ256rmb = 8853, X86_VPBLENDMDZ256rmbk = 8854, X86_VPBLENDMDZ256rmbkz = 8855, X86_VPBLENDMDZ256rmk = 8856, X86_VPBLENDMDZ256rmkz = 8857, X86_VPBLENDMDZ256rr = 8858, X86_VPBLENDMDZ256rrk = 8859, X86_VPBLENDMDZ256rrkz = 8860, X86_VPBLENDMDZrm = 8861, X86_VPBLENDMDZrmb = 8862, X86_VPBLENDMDZrmbk = 8863, X86_VPBLENDMDZrmbkz = 8864, X86_VPBLENDMDZrmk = 8865, X86_VPBLENDMDZrmkz = 8866, X86_VPBLENDMDZrr = 8867, X86_VPBLENDMDZrrk = 8868, X86_VPBLENDMDZrrkz = 8869, X86_VPBLENDMQZ128rm = 8870, X86_VPBLENDMQZ128rmb = 8871, X86_VPBLENDMQZ128rmbk = 8872, X86_VPBLENDMQZ128rmbkz = 8873, X86_VPBLENDMQZ128rmk = 8874, X86_VPBLENDMQZ128rmkz = 8875, X86_VPBLENDMQZ128rr = 8876, X86_VPBLENDMQZ128rrk = 8877, X86_VPBLENDMQZ128rrkz = 8878, X86_VPBLENDMQZ256rm = 8879, X86_VPBLENDMQZ256rmb = 8880, X86_VPBLENDMQZ256rmbk = 8881, X86_VPBLENDMQZ256rmbkz = 8882, X86_VPBLENDMQZ256rmk = 8883, X86_VPBLENDMQZ256rmkz = 8884, X86_VPBLENDMQZ256rr = 8885, X86_VPBLENDMQZ256rrk = 8886, X86_VPBLENDMQZ256rrkz = 8887, X86_VPBLENDMQZrm = 8888, X86_VPBLENDMQZrmb = 8889, X86_VPBLENDMQZrmbk = 8890, X86_VPBLENDMQZrmbkz = 8891, X86_VPBLENDMQZrmk = 8892, X86_VPBLENDMQZrmkz = 8893, X86_VPBLENDMQZrr = 8894, X86_VPBLENDMQZrrk = 8895, X86_VPBLENDMQZrrkz = 8896, X86_VPBLENDMWZ128rm = 8897, X86_VPBLENDMWZ128rmk = 8898, X86_VPBLENDMWZ128rmkz = 8899, X86_VPBLENDMWZ128rr = 8900, X86_VPBLENDMWZ128rrk = 8901, X86_VPBLENDMWZ128rrkz = 8902, X86_VPBLENDMWZ256rm = 8903, X86_VPBLENDMWZ256rmk = 8904, X86_VPBLENDMWZ256rmkz = 8905, X86_VPBLENDMWZ256rr = 8906, X86_VPBLENDMWZ256rrk = 8907, X86_VPBLENDMWZ256rrkz = 8908, X86_VPBLENDMWZrm = 8909, X86_VPBLENDMWZrmk = 8910, X86_VPBLENDMWZrmkz = 8911, X86_VPBLENDMWZrr = 8912, X86_VPBLENDMWZrrk = 8913, X86_VPBLENDMWZrrkz = 8914, X86_VPBLENDVBYrm = 8915, X86_VPBLENDVBYrr = 8916, X86_VPBLENDVBrm = 8917, X86_VPBLENDVBrr = 8918, X86_VPBLENDWYrmi = 8919, X86_VPBLENDWYrri = 8920, X86_VPBLENDWrmi = 8921, X86_VPBLENDWrri = 8922, X86_VPBROADCASTBYrm = 8923, X86_VPBROADCASTBYrr = 8924, X86_VPBROADCASTBZ128m = 8925, X86_VPBROADCASTBZ128mk = 8926, X86_VPBROADCASTBZ128mkz = 8927, X86_VPBROADCASTBZ128r = 8928, X86_VPBROADCASTBZ128rk = 8929, X86_VPBROADCASTBZ128rkz = 8930, X86_VPBROADCASTBZ256m = 8931, X86_VPBROADCASTBZ256mk = 8932, X86_VPBROADCASTBZ256mkz = 8933, X86_VPBROADCASTBZ256r = 8934, X86_VPBROADCASTBZ256rk = 8935, X86_VPBROADCASTBZ256rkz = 8936, X86_VPBROADCASTBZm = 8937, X86_VPBROADCASTBZmk = 8938, X86_VPBROADCASTBZmkz = 8939, X86_VPBROADCASTBZr = 8940, X86_VPBROADCASTBZrk = 8941, X86_VPBROADCASTBZrkz = 8942, X86_VPBROADCASTBrZ128r = 8943, X86_VPBROADCASTBrZ128rk = 8944, X86_VPBROADCASTBrZ128rkz = 8945, X86_VPBROADCASTBrZ256r = 8946, X86_VPBROADCASTBrZ256rk = 8947, X86_VPBROADCASTBrZ256rkz = 8948, X86_VPBROADCASTBrZr = 8949, X86_VPBROADCASTBrZrk = 8950, X86_VPBROADCASTBrZrkz = 8951, X86_VPBROADCASTBrm = 8952, X86_VPBROADCASTBrr = 8953, X86_VPBROADCASTDYrm = 8954, X86_VPBROADCASTDYrr = 8955, X86_VPBROADCASTDZ128m = 8956, X86_VPBROADCASTDZ128mk = 8957, X86_VPBROADCASTDZ128mkz = 8958, X86_VPBROADCASTDZ128r = 8959, X86_VPBROADCASTDZ128rk = 8960, X86_VPBROADCASTDZ128rkz = 8961, X86_VPBROADCASTDZ256m = 8962, X86_VPBROADCASTDZ256mk = 8963, X86_VPBROADCASTDZ256mkz = 8964, X86_VPBROADCASTDZ256r = 8965, X86_VPBROADCASTDZ256rk = 8966, X86_VPBROADCASTDZ256rkz = 8967, X86_VPBROADCASTDZm = 8968, X86_VPBROADCASTDZmk = 8969, X86_VPBROADCASTDZmkz = 8970, X86_VPBROADCASTDZr = 8971, X86_VPBROADCASTDZrk = 8972, X86_VPBROADCASTDZrkz = 8973, X86_VPBROADCASTDrZ128r = 8974, X86_VPBROADCASTDrZ128rk = 8975, X86_VPBROADCASTDrZ128rkz = 8976, X86_VPBROADCASTDrZ256r = 8977, X86_VPBROADCASTDrZ256rk = 8978, X86_VPBROADCASTDrZ256rkz = 8979, X86_VPBROADCASTDrZr = 8980, X86_VPBROADCASTDrZrk = 8981, X86_VPBROADCASTDrZrkz = 8982, X86_VPBROADCASTDrm = 8983, X86_VPBROADCASTDrr = 8984, X86_VPBROADCASTMB2QZ128rr = 8985, X86_VPBROADCASTMB2QZ256rr = 8986, X86_VPBROADCASTMB2QZrr = 8987, X86_VPBROADCASTMW2DZ128rr = 8988, X86_VPBROADCASTMW2DZ256rr = 8989, X86_VPBROADCASTMW2DZrr = 8990, X86_VPBROADCASTQYrm = 8991, X86_VPBROADCASTQYrr = 8992, X86_VPBROADCASTQZ128m = 8993, X86_VPBROADCASTQZ128mk = 8994, X86_VPBROADCASTQZ128mkz = 8995, X86_VPBROADCASTQZ128r = 8996, X86_VPBROADCASTQZ128rk = 8997, X86_VPBROADCASTQZ128rkz = 8998, X86_VPBROADCASTQZ256m = 8999, X86_VPBROADCASTQZ256mk = 9000, X86_VPBROADCASTQZ256mkz = 9001, X86_VPBROADCASTQZ256r = 9002, X86_VPBROADCASTQZ256rk = 9003, X86_VPBROADCASTQZ256rkz = 9004, X86_VPBROADCASTQZm = 9005, X86_VPBROADCASTQZmk = 9006, X86_VPBROADCASTQZmkz = 9007, X86_VPBROADCASTQZr = 9008, X86_VPBROADCASTQZrk = 9009, X86_VPBROADCASTQZrkz = 9010, X86_VPBROADCASTQrZ128r = 9011, X86_VPBROADCASTQrZ128rk = 9012, X86_VPBROADCASTQrZ128rkz = 9013, X86_VPBROADCASTQrZ256r = 9014, X86_VPBROADCASTQrZ256rk = 9015, X86_VPBROADCASTQrZ256rkz = 9016, X86_VPBROADCASTQrZr = 9017, X86_VPBROADCASTQrZrk = 9018, X86_VPBROADCASTQrZrkz = 9019, X86_VPBROADCASTQrm = 9020, X86_VPBROADCASTQrr = 9021, X86_VPBROADCASTWYrm = 9022, X86_VPBROADCASTWYrr = 9023, X86_VPBROADCASTWZ128m = 9024, X86_VPBROADCASTWZ128mk = 9025, X86_VPBROADCASTWZ128mkz = 9026, X86_VPBROADCASTWZ128r = 9027, X86_VPBROADCASTWZ128rk = 9028, X86_VPBROADCASTWZ128rkz = 9029, X86_VPBROADCASTWZ256m = 9030, X86_VPBROADCASTWZ256mk = 9031, X86_VPBROADCASTWZ256mkz = 9032, X86_VPBROADCASTWZ256r = 9033, X86_VPBROADCASTWZ256rk = 9034, X86_VPBROADCASTWZ256rkz = 9035, X86_VPBROADCASTWZm = 9036, X86_VPBROADCASTWZmk = 9037, X86_VPBROADCASTWZmkz = 9038, X86_VPBROADCASTWZr = 9039, X86_VPBROADCASTWZrk = 9040, X86_VPBROADCASTWZrkz = 9041, X86_VPBROADCASTWrZ128r = 9042, X86_VPBROADCASTWrZ128rk = 9043, X86_VPBROADCASTWrZ128rkz = 9044, X86_VPBROADCASTWrZ256r = 9045, X86_VPBROADCASTWrZ256rk = 9046, X86_VPBROADCASTWrZ256rkz = 9047, X86_VPBROADCASTWrZr = 9048, X86_VPBROADCASTWrZrk = 9049, X86_VPBROADCASTWrZrkz = 9050, X86_VPBROADCASTWrm = 9051, X86_VPBROADCASTWrr = 9052, X86_VPCLMULQDQYrm = 9053, X86_VPCLMULQDQYrr = 9054, X86_VPCLMULQDQZ128rm = 9055, X86_VPCLMULQDQZ128rr = 9056, X86_VPCLMULQDQZ256rm = 9057, X86_VPCLMULQDQZ256rr = 9058, X86_VPCLMULQDQZrm = 9059, X86_VPCLMULQDQZrr = 9060, X86_VPCLMULQDQrm = 9061, X86_VPCLMULQDQrr = 9062, X86_VPCMOVYrmr = 9063, X86_VPCMOVYrrm = 9064, X86_VPCMOVYrrr = 9065, X86_VPCMOVYrrr_REV = 9066, X86_VPCMOVrmr = 9067, X86_VPCMOVrrm = 9068, X86_VPCMOVrrr = 9069, X86_VPCMOVrrr_REV = 9070, X86_VPCMPBZ128rmi = 9071, X86_VPCMPBZ128rmi_alt = 9072, X86_VPCMPBZ128rmik = 9073, X86_VPCMPBZ128rmik_alt = 9074, X86_VPCMPBZ128rri = 9075, X86_VPCMPBZ128rri_alt = 9076, X86_VPCMPBZ128rrik = 9077, X86_VPCMPBZ128rrik_alt = 9078, X86_VPCMPBZ256rmi = 9079, X86_VPCMPBZ256rmi_alt = 9080, X86_VPCMPBZ256rmik = 9081, X86_VPCMPBZ256rmik_alt = 9082, X86_VPCMPBZ256rri = 9083, X86_VPCMPBZ256rri_alt = 9084, X86_VPCMPBZ256rrik = 9085, X86_VPCMPBZ256rrik_alt = 9086, X86_VPCMPBZrmi = 9087, X86_VPCMPBZrmi_alt = 9088, X86_VPCMPBZrmik = 9089, X86_VPCMPBZrmik_alt = 9090, X86_VPCMPBZrri = 9091, X86_VPCMPBZrri_alt = 9092, X86_VPCMPBZrrik = 9093, X86_VPCMPBZrrik_alt = 9094, X86_VPCMPDZ128rmi = 9095, X86_VPCMPDZ128rmi_alt = 9096, X86_VPCMPDZ128rmib = 9097, X86_VPCMPDZ128rmib_alt = 9098, X86_VPCMPDZ128rmibk = 9099, X86_VPCMPDZ128rmibk_alt = 9100, X86_VPCMPDZ128rmik = 9101, X86_VPCMPDZ128rmik_alt = 9102, X86_VPCMPDZ128rri = 9103, X86_VPCMPDZ128rri_alt = 9104, X86_VPCMPDZ128rrik = 9105, X86_VPCMPDZ128rrik_alt = 9106, X86_VPCMPDZ256rmi = 9107, X86_VPCMPDZ256rmi_alt = 9108, X86_VPCMPDZ256rmib = 9109, X86_VPCMPDZ256rmib_alt = 9110, X86_VPCMPDZ256rmibk = 9111, X86_VPCMPDZ256rmibk_alt = 9112, X86_VPCMPDZ256rmik = 9113, X86_VPCMPDZ256rmik_alt = 9114, X86_VPCMPDZ256rri = 9115, X86_VPCMPDZ256rri_alt = 9116, X86_VPCMPDZ256rrik = 9117, X86_VPCMPDZ256rrik_alt = 9118, X86_VPCMPDZrmi = 9119, X86_VPCMPDZrmi_alt = 9120, X86_VPCMPDZrmib = 9121, X86_VPCMPDZrmib_alt = 9122, X86_VPCMPDZrmibk = 9123, X86_VPCMPDZrmibk_alt = 9124, X86_VPCMPDZrmik = 9125, X86_VPCMPDZrmik_alt = 9126, X86_VPCMPDZrri = 9127, X86_VPCMPDZrri_alt = 9128, X86_VPCMPDZrrik = 9129, X86_VPCMPDZrrik_alt = 9130, X86_VPCMPEQBYrm = 9131, X86_VPCMPEQBYrr = 9132, X86_VPCMPEQBZ128rm = 9133, X86_VPCMPEQBZ128rmk = 9134, X86_VPCMPEQBZ128rr = 9135, X86_VPCMPEQBZ128rrk = 9136, X86_VPCMPEQBZ256rm = 9137, X86_VPCMPEQBZ256rmk = 9138, X86_VPCMPEQBZ256rr = 9139, X86_VPCMPEQBZ256rrk = 9140, X86_VPCMPEQBZrm = 9141, X86_VPCMPEQBZrmk = 9142, X86_VPCMPEQBZrr = 9143, X86_VPCMPEQBZrrk = 9144, X86_VPCMPEQBrm = 9145, X86_VPCMPEQBrr = 9146, X86_VPCMPEQDYrm = 9147, X86_VPCMPEQDYrr = 9148, X86_VPCMPEQDZ128rm = 9149, X86_VPCMPEQDZ128rmb = 9150, X86_VPCMPEQDZ128rmbk = 9151, X86_VPCMPEQDZ128rmk = 9152, X86_VPCMPEQDZ128rr = 9153, X86_VPCMPEQDZ128rrk = 9154, X86_VPCMPEQDZ256rm = 9155, X86_VPCMPEQDZ256rmb = 9156, X86_VPCMPEQDZ256rmbk = 9157, X86_VPCMPEQDZ256rmk = 9158, X86_VPCMPEQDZ256rr = 9159, X86_VPCMPEQDZ256rrk = 9160, X86_VPCMPEQDZrm = 9161, X86_VPCMPEQDZrmb = 9162, X86_VPCMPEQDZrmbk = 9163, X86_VPCMPEQDZrmk = 9164, X86_VPCMPEQDZrr = 9165, X86_VPCMPEQDZrrk = 9166, X86_VPCMPEQDrm = 9167, X86_VPCMPEQDrr = 9168, X86_VPCMPEQQYrm = 9169, X86_VPCMPEQQYrr = 9170, X86_VPCMPEQQZ128rm = 9171, X86_VPCMPEQQZ128rmb = 9172, X86_VPCMPEQQZ128rmbk = 9173, X86_VPCMPEQQZ128rmk = 9174, X86_VPCMPEQQZ128rr = 9175, X86_VPCMPEQQZ128rrk = 9176, X86_VPCMPEQQZ256rm = 9177, X86_VPCMPEQQZ256rmb = 9178, X86_VPCMPEQQZ256rmbk = 9179, X86_VPCMPEQQZ256rmk = 9180, X86_VPCMPEQQZ256rr = 9181, X86_VPCMPEQQZ256rrk = 9182, X86_VPCMPEQQZrm = 9183, X86_VPCMPEQQZrmb = 9184, X86_VPCMPEQQZrmbk = 9185, X86_VPCMPEQQZrmk = 9186, X86_VPCMPEQQZrr = 9187, X86_VPCMPEQQZrrk = 9188, X86_VPCMPEQQrm = 9189, X86_VPCMPEQQrr = 9190, X86_VPCMPEQWYrm = 9191, X86_VPCMPEQWYrr = 9192, X86_VPCMPEQWZ128rm = 9193, X86_VPCMPEQWZ128rmk = 9194, X86_VPCMPEQWZ128rr = 9195, X86_VPCMPEQWZ128rrk = 9196, X86_VPCMPEQWZ256rm = 9197, X86_VPCMPEQWZ256rmk = 9198, X86_VPCMPEQWZ256rr = 9199, X86_VPCMPEQWZ256rrk = 9200, X86_VPCMPEQWZrm = 9201, X86_VPCMPEQWZrmk = 9202, X86_VPCMPEQWZrr = 9203, X86_VPCMPEQWZrrk = 9204, X86_VPCMPEQWrm = 9205, X86_VPCMPEQWrr = 9206, X86_VPCMPESTRIrm = 9207, X86_VPCMPESTRIrr = 9208, X86_VPCMPESTRMrm = 9209, X86_VPCMPESTRMrr = 9210, X86_VPCMPGTBYrm = 9211, X86_VPCMPGTBYrr = 9212, X86_VPCMPGTBZ128rm = 9213, X86_VPCMPGTBZ128rmk = 9214, X86_VPCMPGTBZ128rr = 9215, X86_VPCMPGTBZ128rrk = 9216, X86_VPCMPGTBZ256rm = 9217, X86_VPCMPGTBZ256rmk = 9218, X86_VPCMPGTBZ256rr = 9219, X86_VPCMPGTBZ256rrk = 9220, X86_VPCMPGTBZrm = 9221, X86_VPCMPGTBZrmk = 9222, X86_VPCMPGTBZrr = 9223, X86_VPCMPGTBZrrk = 9224, X86_VPCMPGTBrm = 9225, X86_VPCMPGTBrr = 9226, X86_VPCMPGTDYrm = 9227, X86_VPCMPGTDYrr = 9228, X86_VPCMPGTDZ128rm = 9229, X86_VPCMPGTDZ128rmb = 9230, X86_VPCMPGTDZ128rmbk = 9231, X86_VPCMPGTDZ128rmk = 9232, X86_VPCMPGTDZ128rr = 9233, X86_VPCMPGTDZ128rrk = 9234, X86_VPCMPGTDZ256rm = 9235, X86_VPCMPGTDZ256rmb = 9236, X86_VPCMPGTDZ256rmbk = 9237, X86_VPCMPGTDZ256rmk = 9238, X86_VPCMPGTDZ256rr = 9239, X86_VPCMPGTDZ256rrk = 9240, X86_VPCMPGTDZrm = 9241, X86_VPCMPGTDZrmb = 9242, X86_VPCMPGTDZrmbk = 9243, X86_VPCMPGTDZrmk = 9244, X86_VPCMPGTDZrr = 9245, X86_VPCMPGTDZrrk = 9246, X86_VPCMPGTDrm = 9247, X86_VPCMPGTDrr = 9248, X86_VPCMPGTQYrm = 9249, X86_VPCMPGTQYrr = 9250, X86_VPCMPGTQZ128rm = 9251, X86_VPCMPGTQZ128rmb = 9252, X86_VPCMPGTQZ128rmbk = 9253, X86_VPCMPGTQZ128rmk = 9254, X86_VPCMPGTQZ128rr = 9255, X86_VPCMPGTQZ128rrk = 9256, X86_VPCMPGTQZ256rm = 9257, X86_VPCMPGTQZ256rmb = 9258, X86_VPCMPGTQZ256rmbk = 9259, X86_VPCMPGTQZ256rmk = 9260, X86_VPCMPGTQZ256rr = 9261, X86_VPCMPGTQZ256rrk = 9262, X86_VPCMPGTQZrm = 9263, X86_VPCMPGTQZrmb = 9264, X86_VPCMPGTQZrmbk = 9265, X86_VPCMPGTQZrmk = 9266, X86_VPCMPGTQZrr = 9267, X86_VPCMPGTQZrrk = 9268, X86_VPCMPGTQrm = 9269, X86_VPCMPGTQrr = 9270, X86_VPCMPGTWYrm = 9271, X86_VPCMPGTWYrr = 9272, X86_VPCMPGTWZ128rm = 9273, X86_VPCMPGTWZ128rmk = 9274, X86_VPCMPGTWZ128rr = 9275, X86_VPCMPGTWZ128rrk = 9276, X86_VPCMPGTWZ256rm = 9277, X86_VPCMPGTWZ256rmk = 9278, X86_VPCMPGTWZ256rr = 9279, X86_VPCMPGTWZ256rrk = 9280, X86_VPCMPGTWZrm = 9281, X86_VPCMPGTWZrmk = 9282, X86_VPCMPGTWZrr = 9283, X86_VPCMPGTWZrrk = 9284, X86_VPCMPGTWrm = 9285, X86_VPCMPGTWrr = 9286, X86_VPCMPISTRIrm = 9287, X86_VPCMPISTRIrr = 9288, X86_VPCMPISTRMrm = 9289, X86_VPCMPISTRMrr = 9290, X86_VPCMPQZ128rmi = 9291, X86_VPCMPQZ128rmi_alt = 9292, X86_VPCMPQZ128rmib = 9293, X86_VPCMPQZ128rmib_alt = 9294, X86_VPCMPQZ128rmibk = 9295, X86_VPCMPQZ128rmibk_alt = 9296, X86_VPCMPQZ128rmik = 9297, X86_VPCMPQZ128rmik_alt = 9298, X86_VPCMPQZ128rri = 9299, X86_VPCMPQZ128rri_alt = 9300, X86_VPCMPQZ128rrik = 9301, X86_VPCMPQZ128rrik_alt = 9302, X86_VPCMPQZ256rmi = 9303, X86_VPCMPQZ256rmi_alt = 9304, X86_VPCMPQZ256rmib = 9305, X86_VPCMPQZ256rmib_alt = 9306, X86_VPCMPQZ256rmibk = 9307, X86_VPCMPQZ256rmibk_alt = 9308, X86_VPCMPQZ256rmik = 9309, X86_VPCMPQZ256rmik_alt = 9310, X86_VPCMPQZ256rri = 9311, X86_VPCMPQZ256rri_alt = 9312, X86_VPCMPQZ256rrik = 9313, X86_VPCMPQZ256rrik_alt = 9314, X86_VPCMPQZrmi = 9315, X86_VPCMPQZrmi_alt = 9316, X86_VPCMPQZrmib = 9317, X86_VPCMPQZrmib_alt = 9318, X86_VPCMPQZrmibk = 9319, X86_VPCMPQZrmibk_alt = 9320, X86_VPCMPQZrmik = 9321, X86_VPCMPQZrmik_alt = 9322, X86_VPCMPQZrri = 9323, X86_VPCMPQZrri_alt = 9324, X86_VPCMPQZrrik = 9325, X86_VPCMPQZrrik_alt = 9326, X86_VPCMPUBZ128rmi = 9327, X86_VPCMPUBZ128rmi_alt = 9328, X86_VPCMPUBZ128rmik = 9329, X86_VPCMPUBZ128rmik_alt = 9330, X86_VPCMPUBZ128rri = 9331, X86_VPCMPUBZ128rri_alt = 9332, X86_VPCMPUBZ128rrik = 9333, X86_VPCMPUBZ128rrik_alt = 9334, X86_VPCMPUBZ256rmi = 9335, X86_VPCMPUBZ256rmi_alt = 9336, X86_VPCMPUBZ256rmik = 9337, X86_VPCMPUBZ256rmik_alt = 9338, X86_VPCMPUBZ256rri = 9339, X86_VPCMPUBZ256rri_alt = 9340, X86_VPCMPUBZ256rrik = 9341, X86_VPCMPUBZ256rrik_alt = 9342, X86_VPCMPUBZrmi = 9343, X86_VPCMPUBZrmi_alt = 9344, X86_VPCMPUBZrmik = 9345, X86_VPCMPUBZrmik_alt = 9346, X86_VPCMPUBZrri = 9347, X86_VPCMPUBZrri_alt = 9348, X86_VPCMPUBZrrik = 9349, X86_VPCMPUBZrrik_alt = 9350, X86_VPCMPUDZ128rmi = 9351, X86_VPCMPUDZ128rmi_alt = 9352, X86_VPCMPUDZ128rmib = 9353, X86_VPCMPUDZ128rmib_alt = 9354, X86_VPCMPUDZ128rmibk = 9355, X86_VPCMPUDZ128rmibk_alt = 9356, X86_VPCMPUDZ128rmik = 9357, X86_VPCMPUDZ128rmik_alt = 9358, X86_VPCMPUDZ128rri = 9359, X86_VPCMPUDZ128rri_alt = 9360, X86_VPCMPUDZ128rrik = 9361, X86_VPCMPUDZ128rrik_alt = 9362, X86_VPCMPUDZ256rmi = 9363, X86_VPCMPUDZ256rmi_alt = 9364, X86_VPCMPUDZ256rmib = 9365, X86_VPCMPUDZ256rmib_alt = 9366, X86_VPCMPUDZ256rmibk = 9367, X86_VPCMPUDZ256rmibk_alt = 9368, X86_VPCMPUDZ256rmik = 9369, X86_VPCMPUDZ256rmik_alt = 9370, X86_VPCMPUDZ256rri = 9371, X86_VPCMPUDZ256rri_alt = 9372, X86_VPCMPUDZ256rrik = 9373, X86_VPCMPUDZ256rrik_alt = 9374, X86_VPCMPUDZrmi = 9375, X86_VPCMPUDZrmi_alt = 9376, X86_VPCMPUDZrmib = 9377, X86_VPCMPUDZrmib_alt = 9378, X86_VPCMPUDZrmibk = 9379, X86_VPCMPUDZrmibk_alt = 9380, X86_VPCMPUDZrmik = 9381, X86_VPCMPUDZrmik_alt = 9382, X86_VPCMPUDZrri = 9383, X86_VPCMPUDZrri_alt = 9384, X86_VPCMPUDZrrik = 9385, X86_VPCMPUDZrrik_alt = 9386, X86_VPCMPUQZ128rmi = 9387, X86_VPCMPUQZ128rmi_alt = 9388, X86_VPCMPUQZ128rmib = 9389, X86_VPCMPUQZ128rmib_alt = 9390, X86_VPCMPUQZ128rmibk = 9391, X86_VPCMPUQZ128rmibk_alt = 9392, X86_VPCMPUQZ128rmik = 9393, X86_VPCMPUQZ128rmik_alt = 9394, X86_VPCMPUQZ128rri = 9395, X86_VPCMPUQZ128rri_alt = 9396, X86_VPCMPUQZ128rrik = 9397, X86_VPCMPUQZ128rrik_alt = 9398, X86_VPCMPUQZ256rmi = 9399, X86_VPCMPUQZ256rmi_alt = 9400, X86_VPCMPUQZ256rmib = 9401, X86_VPCMPUQZ256rmib_alt = 9402, X86_VPCMPUQZ256rmibk = 9403, X86_VPCMPUQZ256rmibk_alt = 9404, X86_VPCMPUQZ256rmik = 9405, X86_VPCMPUQZ256rmik_alt = 9406, X86_VPCMPUQZ256rri = 9407, X86_VPCMPUQZ256rri_alt = 9408, X86_VPCMPUQZ256rrik = 9409, X86_VPCMPUQZ256rrik_alt = 9410, X86_VPCMPUQZrmi = 9411, X86_VPCMPUQZrmi_alt = 9412, X86_VPCMPUQZrmib = 9413, X86_VPCMPUQZrmib_alt = 9414, X86_VPCMPUQZrmibk = 9415, X86_VPCMPUQZrmibk_alt = 9416, X86_VPCMPUQZrmik = 9417, X86_VPCMPUQZrmik_alt = 9418, X86_VPCMPUQZrri = 9419, X86_VPCMPUQZrri_alt = 9420, X86_VPCMPUQZrrik = 9421, X86_VPCMPUQZrrik_alt = 9422, X86_VPCMPUWZ128rmi = 9423, X86_VPCMPUWZ128rmi_alt = 9424, X86_VPCMPUWZ128rmik = 9425, X86_VPCMPUWZ128rmik_alt = 9426, X86_VPCMPUWZ128rri = 9427, X86_VPCMPUWZ128rri_alt = 9428, X86_VPCMPUWZ128rrik = 9429, X86_VPCMPUWZ128rrik_alt = 9430, X86_VPCMPUWZ256rmi = 9431, X86_VPCMPUWZ256rmi_alt = 9432, X86_VPCMPUWZ256rmik = 9433, X86_VPCMPUWZ256rmik_alt = 9434, X86_VPCMPUWZ256rri = 9435, X86_VPCMPUWZ256rri_alt = 9436, X86_VPCMPUWZ256rrik = 9437, X86_VPCMPUWZ256rrik_alt = 9438, X86_VPCMPUWZrmi = 9439, X86_VPCMPUWZrmi_alt = 9440, X86_VPCMPUWZrmik = 9441, X86_VPCMPUWZrmik_alt = 9442, X86_VPCMPUWZrri = 9443, X86_VPCMPUWZrri_alt = 9444, X86_VPCMPUWZrrik = 9445, X86_VPCMPUWZrrik_alt = 9446, X86_VPCMPWZ128rmi = 9447, X86_VPCMPWZ128rmi_alt = 9448, X86_VPCMPWZ128rmik = 9449, X86_VPCMPWZ128rmik_alt = 9450, X86_VPCMPWZ128rri = 9451, X86_VPCMPWZ128rri_alt = 9452, X86_VPCMPWZ128rrik = 9453, X86_VPCMPWZ128rrik_alt = 9454, X86_VPCMPWZ256rmi = 9455, X86_VPCMPWZ256rmi_alt = 9456, X86_VPCMPWZ256rmik = 9457, X86_VPCMPWZ256rmik_alt = 9458, X86_VPCMPWZ256rri = 9459, X86_VPCMPWZ256rri_alt = 9460, X86_VPCMPWZ256rrik = 9461, X86_VPCMPWZ256rrik_alt = 9462, X86_VPCMPWZrmi = 9463, X86_VPCMPWZrmi_alt = 9464, X86_VPCMPWZrmik = 9465, X86_VPCMPWZrmik_alt = 9466, X86_VPCMPWZrri = 9467, X86_VPCMPWZrri_alt = 9468, X86_VPCMPWZrrik = 9469, X86_VPCMPWZrrik_alt = 9470, X86_VPCOMBmi = 9471, X86_VPCOMBmi_alt = 9472, X86_VPCOMBri = 9473, X86_VPCOMBri_alt = 9474, X86_VPCOMDmi = 9475, X86_VPCOMDmi_alt = 9476, X86_VPCOMDri = 9477, X86_VPCOMDri_alt = 9478, X86_VPCOMPRESSBZ128mr = 9479, X86_VPCOMPRESSBZ128mrk = 9480, X86_VPCOMPRESSBZ128rr = 9481, X86_VPCOMPRESSBZ128rrk = 9482, X86_VPCOMPRESSBZ128rrkz = 9483, X86_VPCOMPRESSBZ256mr = 9484, X86_VPCOMPRESSBZ256mrk = 9485, X86_VPCOMPRESSBZ256rr = 9486, X86_VPCOMPRESSBZ256rrk = 9487, X86_VPCOMPRESSBZ256rrkz = 9488, X86_VPCOMPRESSBZmr = 9489, X86_VPCOMPRESSBZmrk = 9490, X86_VPCOMPRESSBZrr = 9491, X86_VPCOMPRESSBZrrk = 9492, X86_VPCOMPRESSBZrrkz = 9493, X86_VPCOMPRESSDZ128mr = 9494, X86_VPCOMPRESSDZ128mrk = 9495, X86_VPCOMPRESSDZ128rr = 9496, X86_VPCOMPRESSDZ128rrk = 9497, X86_VPCOMPRESSDZ128rrkz = 9498, X86_VPCOMPRESSDZ256mr = 9499, X86_VPCOMPRESSDZ256mrk = 9500, X86_VPCOMPRESSDZ256rr = 9501, X86_VPCOMPRESSDZ256rrk = 9502, X86_VPCOMPRESSDZ256rrkz = 9503, X86_VPCOMPRESSDZmr = 9504, X86_VPCOMPRESSDZmrk = 9505, X86_VPCOMPRESSDZrr = 9506, X86_VPCOMPRESSDZrrk = 9507, X86_VPCOMPRESSDZrrkz = 9508, X86_VPCOMPRESSQZ128mr = 9509, X86_VPCOMPRESSQZ128mrk = 9510, X86_VPCOMPRESSQZ128rr = 9511, X86_VPCOMPRESSQZ128rrk = 9512, X86_VPCOMPRESSQZ128rrkz = 9513, X86_VPCOMPRESSQZ256mr = 9514, X86_VPCOMPRESSQZ256mrk = 9515, X86_VPCOMPRESSQZ256rr = 9516, X86_VPCOMPRESSQZ256rrk = 9517, X86_VPCOMPRESSQZ256rrkz = 9518, X86_VPCOMPRESSQZmr = 9519, X86_VPCOMPRESSQZmrk = 9520, X86_VPCOMPRESSQZrr = 9521, X86_VPCOMPRESSQZrrk = 9522, X86_VPCOMPRESSQZrrkz = 9523, X86_VPCOMPRESSWZ128mr = 9524, X86_VPCOMPRESSWZ128mrk = 9525, X86_VPCOMPRESSWZ128rr = 9526, X86_VPCOMPRESSWZ128rrk = 9527, X86_VPCOMPRESSWZ128rrkz = 9528, X86_VPCOMPRESSWZ256mr = 9529, X86_VPCOMPRESSWZ256mrk = 9530, X86_VPCOMPRESSWZ256rr = 9531, X86_VPCOMPRESSWZ256rrk = 9532, X86_VPCOMPRESSWZ256rrkz = 9533, X86_VPCOMPRESSWZmr = 9534, X86_VPCOMPRESSWZmrk = 9535, X86_VPCOMPRESSWZrr = 9536, X86_VPCOMPRESSWZrrk = 9537, X86_VPCOMPRESSWZrrkz = 9538, X86_VPCOMQmi = 9539, X86_VPCOMQmi_alt = 9540, X86_VPCOMQri = 9541, X86_VPCOMQri_alt = 9542, X86_VPCOMUBmi = 9543, X86_VPCOMUBmi_alt = 9544, X86_VPCOMUBri = 9545, X86_VPCOMUBri_alt = 9546, X86_VPCOMUDmi = 9547, X86_VPCOMUDmi_alt = 9548, X86_VPCOMUDri = 9549, X86_VPCOMUDri_alt = 9550, X86_VPCOMUQmi = 9551, X86_VPCOMUQmi_alt = 9552, X86_VPCOMUQri = 9553, X86_VPCOMUQri_alt = 9554, X86_VPCOMUWmi = 9555, X86_VPCOMUWmi_alt = 9556, X86_VPCOMUWri = 9557, X86_VPCOMUWri_alt = 9558, X86_VPCOMWmi = 9559, X86_VPCOMWmi_alt = 9560, X86_VPCOMWri = 9561, X86_VPCOMWri_alt = 9562, X86_VPCONFLICTDZ128rm = 9563, X86_VPCONFLICTDZ128rmb = 9564, X86_VPCONFLICTDZ128rmbk = 9565, X86_VPCONFLICTDZ128rmbkz = 9566, X86_VPCONFLICTDZ128rmk = 9567, X86_VPCONFLICTDZ128rmkz = 9568, X86_VPCONFLICTDZ128rr = 9569, X86_VPCONFLICTDZ128rrk = 9570, X86_VPCONFLICTDZ128rrkz = 9571, X86_VPCONFLICTDZ256rm = 9572, X86_VPCONFLICTDZ256rmb = 9573, X86_VPCONFLICTDZ256rmbk = 9574, X86_VPCONFLICTDZ256rmbkz = 9575, X86_VPCONFLICTDZ256rmk = 9576, X86_VPCONFLICTDZ256rmkz = 9577, X86_VPCONFLICTDZ256rr = 9578, X86_VPCONFLICTDZ256rrk = 9579, X86_VPCONFLICTDZ256rrkz = 9580, X86_VPCONFLICTDZrm = 9581, X86_VPCONFLICTDZrmb = 9582, X86_VPCONFLICTDZrmbk = 9583, X86_VPCONFLICTDZrmbkz = 9584, X86_VPCONFLICTDZrmk = 9585, X86_VPCONFLICTDZrmkz = 9586, X86_VPCONFLICTDZrr = 9587, X86_VPCONFLICTDZrrk = 9588, X86_VPCONFLICTDZrrkz = 9589, X86_VPCONFLICTQZ128rm = 9590, X86_VPCONFLICTQZ128rmb = 9591, X86_VPCONFLICTQZ128rmbk = 9592, X86_VPCONFLICTQZ128rmbkz = 9593, X86_VPCONFLICTQZ128rmk = 9594, X86_VPCONFLICTQZ128rmkz = 9595, X86_VPCONFLICTQZ128rr = 9596, X86_VPCONFLICTQZ128rrk = 9597, X86_VPCONFLICTQZ128rrkz = 9598, X86_VPCONFLICTQZ256rm = 9599, X86_VPCONFLICTQZ256rmb = 9600, X86_VPCONFLICTQZ256rmbk = 9601, X86_VPCONFLICTQZ256rmbkz = 9602, X86_VPCONFLICTQZ256rmk = 9603, X86_VPCONFLICTQZ256rmkz = 9604, X86_VPCONFLICTQZ256rr = 9605, X86_VPCONFLICTQZ256rrk = 9606, X86_VPCONFLICTQZ256rrkz = 9607, X86_VPCONFLICTQZrm = 9608, X86_VPCONFLICTQZrmb = 9609, X86_VPCONFLICTQZrmbk = 9610, X86_VPCONFLICTQZrmbkz = 9611, X86_VPCONFLICTQZrmk = 9612, X86_VPCONFLICTQZrmkz = 9613, X86_VPCONFLICTQZrr = 9614, X86_VPCONFLICTQZrrk = 9615, X86_VPCONFLICTQZrrkz = 9616, X86_VPDPBUSDSZ128m = 9617, X86_VPDPBUSDSZ128mb = 9618, X86_VPDPBUSDSZ128mbk = 9619, X86_VPDPBUSDSZ128mbkz = 9620, X86_VPDPBUSDSZ128mk = 9621, X86_VPDPBUSDSZ128mkz = 9622, X86_VPDPBUSDSZ128r = 9623, X86_VPDPBUSDSZ128rk = 9624, X86_VPDPBUSDSZ128rkz = 9625, X86_VPDPBUSDSZ256m = 9626, X86_VPDPBUSDSZ256mb = 9627, X86_VPDPBUSDSZ256mbk = 9628, X86_VPDPBUSDSZ256mbkz = 9629, X86_VPDPBUSDSZ256mk = 9630, X86_VPDPBUSDSZ256mkz = 9631, X86_VPDPBUSDSZ256r = 9632, X86_VPDPBUSDSZ256rk = 9633, X86_VPDPBUSDSZ256rkz = 9634, X86_VPDPBUSDSZm = 9635, X86_VPDPBUSDSZmb = 9636, X86_VPDPBUSDSZmbk = 9637, X86_VPDPBUSDSZmbkz = 9638, X86_VPDPBUSDSZmk = 9639, X86_VPDPBUSDSZmkz = 9640, X86_VPDPBUSDSZr = 9641, X86_VPDPBUSDSZrk = 9642, X86_VPDPBUSDSZrkz = 9643, X86_VPDPBUSDZ128m = 9644, X86_VPDPBUSDZ128mb = 9645, X86_VPDPBUSDZ128mbk = 9646, X86_VPDPBUSDZ128mbkz = 9647, X86_VPDPBUSDZ128mk = 9648, X86_VPDPBUSDZ128mkz = 9649, X86_VPDPBUSDZ128r = 9650, X86_VPDPBUSDZ128rk = 9651, X86_VPDPBUSDZ128rkz = 9652, X86_VPDPBUSDZ256m = 9653, X86_VPDPBUSDZ256mb = 9654, X86_VPDPBUSDZ256mbk = 9655, X86_VPDPBUSDZ256mbkz = 9656, X86_VPDPBUSDZ256mk = 9657, X86_VPDPBUSDZ256mkz = 9658, X86_VPDPBUSDZ256r = 9659, X86_VPDPBUSDZ256rk = 9660, X86_VPDPBUSDZ256rkz = 9661, X86_VPDPBUSDZm = 9662, X86_VPDPBUSDZmb = 9663, X86_VPDPBUSDZmbk = 9664, X86_VPDPBUSDZmbkz = 9665, X86_VPDPBUSDZmk = 9666, X86_VPDPBUSDZmkz = 9667, X86_VPDPBUSDZr = 9668, X86_VPDPBUSDZrk = 9669, X86_VPDPBUSDZrkz = 9670, X86_VPDPWSSDSZ128m = 9671, X86_VPDPWSSDSZ128mb = 9672, X86_VPDPWSSDSZ128mbk = 9673, X86_VPDPWSSDSZ128mbkz = 9674, X86_VPDPWSSDSZ128mk = 9675, X86_VPDPWSSDSZ128mkz = 9676, X86_VPDPWSSDSZ128r = 9677, X86_VPDPWSSDSZ128rk = 9678, X86_VPDPWSSDSZ128rkz = 9679, X86_VPDPWSSDSZ256m = 9680, X86_VPDPWSSDSZ256mb = 9681, X86_VPDPWSSDSZ256mbk = 9682, X86_VPDPWSSDSZ256mbkz = 9683, X86_VPDPWSSDSZ256mk = 9684, X86_VPDPWSSDSZ256mkz = 9685, X86_VPDPWSSDSZ256r = 9686, X86_VPDPWSSDSZ256rk = 9687, X86_VPDPWSSDSZ256rkz = 9688, X86_VPDPWSSDSZm = 9689, X86_VPDPWSSDSZmb = 9690, X86_VPDPWSSDSZmbk = 9691, X86_VPDPWSSDSZmbkz = 9692, X86_VPDPWSSDSZmk = 9693, X86_VPDPWSSDSZmkz = 9694, X86_VPDPWSSDSZr = 9695, X86_VPDPWSSDSZrk = 9696, X86_VPDPWSSDSZrkz = 9697, X86_VPDPWSSDZ128m = 9698, X86_VPDPWSSDZ128mb = 9699, X86_VPDPWSSDZ128mbk = 9700, X86_VPDPWSSDZ128mbkz = 9701, X86_VPDPWSSDZ128mk = 9702, X86_VPDPWSSDZ128mkz = 9703, X86_VPDPWSSDZ128r = 9704, X86_VPDPWSSDZ128rk = 9705, X86_VPDPWSSDZ128rkz = 9706, X86_VPDPWSSDZ256m = 9707, X86_VPDPWSSDZ256mb = 9708, X86_VPDPWSSDZ256mbk = 9709, X86_VPDPWSSDZ256mbkz = 9710, X86_VPDPWSSDZ256mk = 9711, X86_VPDPWSSDZ256mkz = 9712, X86_VPDPWSSDZ256r = 9713, X86_VPDPWSSDZ256rk = 9714, X86_VPDPWSSDZ256rkz = 9715, X86_VPDPWSSDZm = 9716, X86_VPDPWSSDZmb = 9717, X86_VPDPWSSDZmbk = 9718, X86_VPDPWSSDZmbkz = 9719, X86_VPDPWSSDZmk = 9720, X86_VPDPWSSDZmkz = 9721, X86_VPDPWSSDZr = 9722, X86_VPDPWSSDZrk = 9723, X86_VPDPWSSDZrkz = 9724, X86_VPERM2F128rm = 9725, X86_VPERM2F128rr = 9726, X86_VPERM2I128rm = 9727, X86_VPERM2I128rr = 9728, X86_VPERMBZ128rm = 9729, X86_VPERMBZ128rmk = 9730, X86_VPERMBZ128rmkz = 9731, X86_VPERMBZ128rr = 9732, X86_VPERMBZ128rrk = 9733, X86_VPERMBZ128rrkz = 9734, X86_VPERMBZ256rm = 9735, X86_VPERMBZ256rmk = 9736, X86_VPERMBZ256rmkz = 9737, X86_VPERMBZ256rr = 9738, X86_VPERMBZ256rrk = 9739, X86_VPERMBZ256rrkz = 9740, X86_VPERMBZrm = 9741, X86_VPERMBZrmk = 9742, X86_VPERMBZrmkz = 9743, X86_VPERMBZrr = 9744, X86_VPERMBZrrk = 9745, X86_VPERMBZrrkz = 9746, X86_VPERMDYrm = 9747, X86_VPERMDYrr = 9748, X86_VPERMDZ256rm = 9749, X86_VPERMDZ256rmb = 9750, X86_VPERMDZ256rmbk = 9751, X86_VPERMDZ256rmbkz = 9752, X86_VPERMDZ256rmk = 9753, X86_VPERMDZ256rmkz = 9754, X86_VPERMDZ256rr = 9755, X86_VPERMDZ256rrk = 9756, X86_VPERMDZ256rrkz = 9757, X86_VPERMDZrm = 9758, X86_VPERMDZrmb = 9759, X86_VPERMDZrmbk = 9760, X86_VPERMDZrmbkz = 9761, X86_VPERMDZrmk = 9762, X86_VPERMDZrmkz = 9763, X86_VPERMDZrr = 9764, X86_VPERMDZrrk = 9765, X86_VPERMDZrrkz = 9766, X86_VPERMI2B128rm = 9767, X86_VPERMI2B128rmk = 9768, X86_VPERMI2B128rmkz = 9769, X86_VPERMI2B128rr = 9770, X86_VPERMI2B128rrk = 9771, X86_VPERMI2B128rrkz = 9772, X86_VPERMI2B256rm = 9773, X86_VPERMI2B256rmk = 9774, X86_VPERMI2B256rmkz = 9775, X86_VPERMI2B256rr = 9776, X86_VPERMI2B256rrk = 9777, X86_VPERMI2B256rrkz = 9778, X86_VPERMI2Brm = 9779, X86_VPERMI2Brmk = 9780, X86_VPERMI2Brmkz = 9781, X86_VPERMI2Brr = 9782, X86_VPERMI2Brrk = 9783, X86_VPERMI2Brrkz = 9784, X86_VPERMI2D128rm = 9785, X86_VPERMI2D128rmb = 9786, X86_VPERMI2D128rmbk = 9787, X86_VPERMI2D128rmbkz = 9788, X86_VPERMI2D128rmk = 9789, X86_VPERMI2D128rmkz = 9790, X86_VPERMI2D128rr = 9791, X86_VPERMI2D128rrk = 9792, X86_VPERMI2D128rrkz = 9793, X86_VPERMI2D256rm = 9794, X86_VPERMI2D256rmb = 9795, X86_VPERMI2D256rmbk = 9796, X86_VPERMI2D256rmbkz = 9797, X86_VPERMI2D256rmk = 9798, X86_VPERMI2D256rmkz = 9799, X86_VPERMI2D256rr = 9800, X86_VPERMI2D256rrk = 9801, X86_VPERMI2D256rrkz = 9802, X86_VPERMI2Drm = 9803, X86_VPERMI2Drmb = 9804, X86_VPERMI2Drmbk = 9805, X86_VPERMI2Drmbkz = 9806, X86_VPERMI2Drmk = 9807, X86_VPERMI2Drmkz = 9808, X86_VPERMI2Drr = 9809, X86_VPERMI2Drrk = 9810, X86_VPERMI2Drrkz = 9811, X86_VPERMI2PD128rm = 9812, X86_VPERMI2PD128rmb = 9813, X86_VPERMI2PD128rmbk = 9814, X86_VPERMI2PD128rmbkz = 9815, X86_VPERMI2PD128rmk = 9816, X86_VPERMI2PD128rmkz = 9817, X86_VPERMI2PD128rr = 9818, X86_VPERMI2PD128rrk = 9819, X86_VPERMI2PD128rrkz = 9820, X86_VPERMI2PD256rm = 9821, X86_VPERMI2PD256rmb = 9822, X86_VPERMI2PD256rmbk = 9823, X86_VPERMI2PD256rmbkz = 9824, X86_VPERMI2PD256rmk = 9825, X86_VPERMI2PD256rmkz = 9826, X86_VPERMI2PD256rr = 9827, X86_VPERMI2PD256rrk = 9828, X86_VPERMI2PD256rrkz = 9829, X86_VPERMI2PDrm = 9830, X86_VPERMI2PDrmb = 9831, X86_VPERMI2PDrmbk = 9832, X86_VPERMI2PDrmbkz = 9833, X86_VPERMI2PDrmk = 9834, X86_VPERMI2PDrmkz = 9835, X86_VPERMI2PDrr = 9836, X86_VPERMI2PDrrk = 9837, X86_VPERMI2PDrrkz = 9838, X86_VPERMI2PS128rm = 9839, X86_VPERMI2PS128rmb = 9840, X86_VPERMI2PS128rmbk = 9841, X86_VPERMI2PS128rmbkz = 9842, X86_VPERMI2PS128rmk = 9843, X86_VPERMI2PS128rmkz = 9844, X86_VPERMI2PS128rr = 9845, X86_VPERMI2PS128rrk = 9846, X86_VPERMI2PS128rrkz = 9847, X86_VPERMI2PS256rm = 9848, X86_VPERMI2PS256rmb = 9849, X86_VPERMI2PS256rmbk = 9850, X86_VPERMI2PS256rmbkz = 9851, X86_VPERMI2PS256rmk = 9852, X86_VPERMI2PS256rmkz = 9853, X86_VPERMI2PS256rr = 9854, X86_VPERMI2PS256rrk = 9855, X86_VPERMI2PS256rrkz = 9856, X86_VPERMI2PSrm = 9857, X86_VPERMI2PSrmb = 9858, X86_VPERMI2PSrmbk = 9859, X86_VPERMI2PSrmbkz = 9860, X86_VPERMI2PSrmk = 9861, X86_VPERMI2PSrmkz = 9862, X86_VPERMI2PSrr = 9863, X86_VPERMI2PSrrk = 9864, X86_VPERMI2PSrrkz = 9865, X86_VPERMI2Q128rm = 9866, X86_VPERMI2Q128rmb = 9867, X86_VPERMI2Q128rmbk = 9868, X86_VPERMI2Q128rmbkz = 9869, X86_VPERMI2Q128rmk = 9870, X86_VPERMI2Q128rmkz = 9871, X86_VPERMI2Q128rr = 9872, X86_VPERMI2Q128rrk = 9873, X86_VPERMI2Q128rrkz = 9874, X86_VPERMI2Q256rm = 9875, X86_VPERMI2Q256rmb = 9876, X86_VPERMI2Q256rmbk = 9877, X86_VPERMI2Q256rmbkz = 9878, X86_VPERMI2Q256rmk = 9879, X86_VPERMI2Q256rmkz = 9880, X86_VPERMI2Q256rr = 9881, X86_VPERMI2Q256rrk = 9882, X86_VPERMI2Q256rrkz = 9883, X86_VPERMI2Qrm = 9884, X86_VPERMI2Qrmb = 9885, X86_VPERMI2Qrmbk = 9886, X86_VPERMI2Qrmbkz = 9887, X86_VPERMI2Qrmk = 9888, X86_VPERMI2Qrmkz = 9889, X86_VPERMI2Qrr = 9890, X86_VPERMI2Qrrk = 9891, X86_VPERMI2Qrrkz = 9892, X86_VPERMI2W128rm = 9893, X86_VPERMI2W128rmk = 9894, X86_VPERMI2W128rmkz = 9895, X86_VPERMI2W128rr = 9896, X86_VPERMI2W128rrk = 9897, X86_VPERMI2W128rrkz = 9898, X86_VPERMI2W256rm = 9899, X86_VPERMI2W256rmk = 9900, X86_VPERMI2W256rmkz = 9901, X86_VPERMI2W256rr = 9902, X86_VPERMI2W256rrk = 9903, X86_VPERMI2W256rrkz = 9904, X86_VPERMI2Wrm = 9905, X86_VPERMI2Wrmk = 9906, X86_VPERMI2Wrmkz = 9907, X86_VPERMI2Wrr = 9908, X86_VPERMI2Wrrk = 9909, X86_VPERMI2Wrrkz = 9910, X86_VPERMIL2PDYmr = 9911, X86_VPERMIL2PDYrm = 9912, X86_VPERMIL2PDYrr = 9913, X86_VPERMIL2PDYrr_REV = 9914, X86_VPERMIL2PDmr = 9915, X86_VPERMIL2PDrm = 9916, X86_VPERMIL2PDrr = 9917, X86_VPERMIL2PDrr_REV = 9918, X86_VPERMIL2PSYmr = 9919, X86_VPERMIL2PSYrm = 9920, X86_VPERMIL2PSYrr = 9921, X86_VPERMIL2PSYrr_REV = 9922, X86_VPERMIL2PSmr = 9923, X86_VPERMIL2PSrm = 9924, X86_VPERMIL2PSrr = 9925, X86_VPERMIL2PSrr_REV = 9926, X86_VPERMILPDYmi = 9927, X86_VPERMILPDYri = 9928, X86_VPERMILPDYrm = 9929, X86_VPERMILPDYrr = 9930, X86_VPERMILPDZ128mbi = 9931, X86_VPERMILPDZ128mbik = 9932, X86_VPERMILPDZ128mbikz = 9933, X86_VPERMILPDZ128mi = 9934, X86_VPERMILPDZ128mik = 9935, X86_VPERMILPDZ128mikz = 9936, X86_VPERMILPDZ128ri = 9937, X86_VPERMILPDZ128rik = 9938, X86_VPERMILPDZ128rikz = 9939, X86_VPERMILPDZ128rm = 9940, X86_VPERMILPDZ128rmb = 9941, X86_VPERMILPDZ128rmbk = 9942, X86_VPERMILPDZ128rmbkz = 9943, X86_VPERMILPDZ128rmk = 9944, X86_VPERMILPDZ128rmkz = 9945, X86_VPERMILPDZ128rr = 9946, X86_VPERMILPDZ128rrk = 9947, X86_VPERMILPDZ128rrkz = 9948, X86_VPERMILPDZ256mbi = 9949, X86_VPERMILPDZ256mbik = 9950, X86_VPERMILPDZ256mbikz = 9951, X86_VPERMILPDZ256mi = 9952, X86_VPERMILPDZ256mik = 9953, X86_VPERMILPDZ256mikz = 9954, X86_VPERMILPDZ256ri = 9955, X86_VPERMILPDZ256rik = 9956, X86_VPERMILPDZ256rikz = 9957, X86_VPERMILPDZ256rm = 9958, X86_VPERMILPDZ256rmb = 9959, X86_VPERMILPDZ256rmbk = 9960, X86_VPERMILPDZ256rmbkz = 9961, X86_VPERMILPDZ256rmk = 9962, X86_VPERMILPDZ256rmkz = 9963, X86_VPERMILPDZ256rr = 9964, X86_VPERMILPDZ256rrk = 9965, X86_VPERMILPDZ256rrkz = 9966, X86_VPERMILPDZmbi = 9967, X86_VPERMILPDZmbik = 9968, X86_VPERMILPDZmbikz = 9969, X86_VPERMILPDZmi = 9970, X86_VPERMILPDZmik = 9971, X86_VPERMILPDZmikz = 9972, X86_VPERMILPDZri = 9973, X86_VPERMILPDZrik = 9974, X86_VPERMILPDZrikz = 9975, X86_VPERMILPDZrm = 9976, X86_VPERMILPDZrmb = 9977, X86_VPERMILPDZrmbk = 9978, X86_VPERMILPDZrmbkz = 9979, X86_VPERMILPDZrmk = 9980, X86_VPERMILPDZrmkz = 9981, X86_VPERMILPDZrr = 9982, X86_VPERMILPDZrrk = 9983, X86_VPERMILPDZrrkz = 9984, X86_VPERMILPDmi = 9985, X86_VPERMILPDri = 9986, X86_VPERMILPDrm = 9987, X86_VPERMILPDrr = 9988, X86_VPERMILPSYmi = 9989, X86_VPERMILPSYri = 9990, X86_VPERMILPSYrm = 9991, X86_VPERMILPSYrr = 9992, X86_VPERMILPSZ128mbi = 9993, X86_VPERMILPSZ128mbik = 9994, X86_VPERMILPSZ128mbikz = 9995, X86_VPERMILPSZ128mi = 9996, X86_VPERMILPSZ128mik = 9997, X86_VPERMILPSZ128mikz = 9998, X86_VPERMILPSZ128ri = 9999, X86_VPERMILPSZ128rik = 10000, X86_VPERMILPSZ128rikz = 10001, X86_VPERMILPSZ128rm = 10002, X86_VPERMILPSZ128rmb = 10003, X86_VPERMILPSZ128rmbk = 10004, X86_VPERMILPSZ128rmbkz = 10005, X86_VPERMILPSZ128rmk = 10006, X86_VPERMILPSZ128rmkz = 10007, X86_VPERMILPSZ128rr = 10008, X86_VPERMILPSZ128rrk = 10009, X86_VPERMILPSZ128rrkz = 10010, X86_VPERMILPSZ256mbi = 10011, X86_VPERMILPSZ256mbik = 10012, X86_VPERMILPSZ256mbikz = 10013, X86_VPERMILPSZ256mi = 10014, X86_VPERMILPSZ256mik = 10015, X86_VPERMILPSZ256mikz = 10016, X86_VPERMILPSZ256ri = 10017, X86_VPERMILPSZ256rik = 10018, X86_VPERMILPSZ256rikz = 10019, X86_VPERMILPSZ256rm = 10020, X86_VPERMILPSZ256rmb = 10021, X86_VPERMILPSZ256rmbk = 10022, X86_VPERMILPSZ256rmbkz = 10023, X86_VPERMILPSZ256rmk = 10024, X86_VPERMILPSZ256rmkz = 10025, X86_VPERMILPSZ256rr = 10026, X86_VPERMILPSZ256rrk = 10027, X86_VPERMILPSZ256rrkz = 10028, X86_VPERMILPSZmbi = 10029, X86_VPERMILPSZmbik = 10030, X86_VPERMILPSZmbikz = 10031, X86_VPERMILPSZmi = 10032, X86_VPERMILPSZmik = 10033, X86_VPERMILPSZmikz = 10034, X86_VPERMILPSZri = 10035, X86_VPERMILPSZrik = 10036, X86_VPERMILPSZrikz = 10037, X86_VPERMILPSZrm = 10038, X86_VPERMILPSZrmb = 10039, X86_VPERMILPSZrmbk = 10040, X86_VPERMILPSZrmbkz = 10041, X86_VPERMILPSZrmk = 10042, X86_VPERMILPSZrmkz = 10043, X86_VPERMILPSZrr = 10044, X86_VPERMILPSZrrk = 10045, X86_VPERMILPSZrrkz = 10046, X86_VPERMILPSmi = 10047, X86_VPERMILPSri = 10048, X86_VPERMILPSrm = 10049, X86_VPERMILPSrr = 10050, X86_VPERMPDYmi = 10051, X86_VPERMPDYri = 10052, X86_VPERMPDZ256mbi = 10053, X86_VPERMPDZ256mbik = 10054, X86_VPERMPDZ256mbikz = 10055, X86_VPERMPDZ256mi = 10056, X86_VPERMPDZ256mik = 10057, X86_VPERMPDZ256mikz = 10058, X86_VPERMPDZ256ri = 10059, X86_VPERMPDZ256rik = 10060, X86_VPERMPDZ256rikz = 10061, X86_VPERMPDZ256rm = 10062, X86_VPERMPDZ256rmb = 10063, X86_VPERMPDZ256rmbk = 10064, X86_VPERMPDZ256rmbkz = 10065, X86_VPERMPDZ256rmk = 10066, X86_VPERMPDZ256rmkz = 10067, X86_VPERMPDZ256rr = 10068, X86_VPERMPDZ256rrk = 10069, X86_VPERMPDZ256rrkz = 10070, X86_VPERMPDZmbi = 10071, X86_VPERMPDZmbik = 10072, X86_VPERMPDZmbikz = 10073, X86_VPERMPDZmi = 10074, X86_VPERMPDZmik = 10075, X86_VPERMPDZmikz = 10076, X86_VPERMPDZri = 10077, X86_VPERMPDZrik = 10078, X86_VPERMPDZrikz = 10079, X86_VPERMPDZrm = 10080, X86_VPERMPDZrmb = 10081, X86_VPERMPDZrmbk = 10082, X86_VPERMPDZrmbkz = 10083, X86_VPERMPDZrmk = 10084, X86_VPERMPDZrmkz = 10085, X86_VPERMPDZrr = 10086, X86_VPERMPDZrrk = 10087, X86_VPERMPDZrrkz = 10088, X86_VPERMPSYrm = 10089, X86_VPERMPSYrr = 10090, X86_VPERMPSZ256rm = 10091, X86_VPERMPSZ256rmb = 10092, X86_VPERMPSZ256rmbk = 10093, X86_VPERMPSZ256rmbkz = 10094, X86_VPERMPSZ256rmk = 10095, X86_VPERMPSZ256rmkz = 10096, X86_VPERMPSZ256rr = 10097, X86_VPERMPSZ256rrk = 10098, X86_VPERMPSZ256rrkz = 10099, X86_VPERMPSZrm = 10100, X86_VPERMPSZrmb = 10101, X86_VPERMPSZrmbk = 10102, X86_VPERMPSZrmbkz = 10103, X86_VPERMPSZrmk = 10104, X86_VPERMPSZrmkz = 10105, X86_VPERMPSZrr = 10106, X86_VPERMPSZrrk = 10107, X86_VPERMPSZrrkz = 10108, X86_VPERMQYmi = 10109, X86_VPERMQYri = 10110, X86_VPERMQZ256mbi = 10111, X86_VPERMQZ256mbik = 10112, X86_VPERMQZ256mbikz = 10113, X86_VPERMQZ256mi = 10114, X86_VPERMQZ256mik = 10115, X86_VPERMQZ256mikz = 10116, X86_VPERMQZ256ri = 10117, X86_VPERMQZ256rik = 10118, X86_VPERMQZ256rikz = 10119, X86_VPERMQZ256rm = 10120, X86_VPERMQZ256rmb = 10121, X86_VPERMQZ256rmbk = 10122, X86_VPERMQZ256rmbkz = 10123, X86_VPERMQZ256rmk = 10124, X86_VPERMQZ256rmkz = 10125, X86_VPERMQZ256rr = 10126, X86_VPERMQZ256rrk = 10127, X86_VPERMQZ256rrkz = 10128, X86_VPERMQZmbi = 10129, X86_VPERMQZmbik = 10130, X86_VPERMQZmbikz = 10131, X86_VPERMQZmi = 10132, X86_VPERMQZmik = 10133, X86_VPERMQZmikz = 10134, X86_VPERMQZri = 10135, X86_VPERMQZrik = 10136, X86_VPERMQZrikz = 10137, X86_VPERMQZrm = 10138, X86_VPERMQZrmb = 10139, X86_VPERMQZrmbk = 10140, X86_VPERMQZrmbkz = 10141, X86_VPERMQZrmk = 10142, X86_VPERMQZrmkz = 10143, X86_VPERMQZrr = 10144, X86_VPERMQZrrk = 10145, X86_VPERMQZrrkz = 10146, X86_VPERMT2B128rm = 10147, X86_VPERMT2B128rmk = 10148, X86_VPERMT2B128rmkz = 10149, X86_VPERMT2B128rr = 10150, X86_VPERMT2B128rrk = 10151, X86_VPERMT2B128rrkz = 10152, X86_VPERMT2B256rm = 10153, X86_VPERMT2B256rmk = 10154, X86_VPERMT2B256rmkz = 10155, X86_VPERMT2B256rr = 10156, X86_VPERMT2B256rrk = 10157, X86_VPERMT2B256rrkz = 10158, X86_VPERMT2Brm = 10159, X86_VPERMT2Brmk = 10160, X86_VPERMT2Brmkz = 10161, X86_VPERMT2Brr = 10162, X86_VPERMT2Brrk = 10163, X86_VPERMT2Brrkz = 10164, X86_VPERMT2D128rm = 10165, X86_VPERMT2D128rmb = 10166, X86_VPERMT2D128rmbk = 10167, X86_VPERMT2D128rmbkz = 10168, X86_VPERMT2D128rmk = 10169, X86_VPERMT2D128rmkz = 10170, X86_VPERMT2D128rr = 10171, X86_VPERMT2D128rrk = 10172, X86_VPERMT2D128rrkz = 10173, X86_VPERMT2D256rm = 10174, X86_VPERMT2D256rmb = 10175, X86_VPERMT2D256rmbk = 10176, X86_VPERMT2D256rmbkz = 10177, X86_VPERMT2D256rmk = 10178, X86_VPERMT2D256rmkz = 10179, X86_VPERMT2D256rr = 10180, X86_VPERMT2D256rrk = 10181, X86_VPERMT2D256rrkz = 10182, X86_VPERMT2Drm = 10183, X86_VPERMT2Drmb = 10184, X86_VPERMT2Drmbk = 10185, X86_VPERMT2Drmbkz = 10186, X86_VPERMT2Drmk = 10187, X86_VPERMT2Drmkz = 10188, X86_VPERMT2Drr = 10189, X86_VPERMT2Drrk = 10190, X86_VPERMT2Drrkz = 10191, X86_VPERMT2PD128rm = 10192, X86_VPERMT2PD128rmb = 10193, X86_VPERMT2PD128rmbk = 10194, X86_VPERMT2PD128rmbkz = 10195, X86_VPERMT2PD128rmk = 10196, X86_VPERMT2PD128rmkz = 10197, X86_VPERMT2PD128rr = 10198, X86_VPERMT2PD128rrk = 10199, X86_VPERMT2PD128rrkz = 10200, X86_VPERMT2PD256rm = 10201, X86_VPERMT2PD256rmb = 10202, X86_VPERMT2PD256rmbk = 10203, X86_VPERMT2PD256rmbkz = 10204, X86_VPERMT2PD256rmk = 10205, X86_VPERMT2PD256rmkz = 10206, X86_VPERMT2PD256rr = 10207, X86_VPERMT2PD256rrk = 10208, X86_VPERMT2PD256rrkz = 10209, X86_VPERMT2PDrm = 10210, X86_VPERMT2PDrmb = 10211, X86_VPERMT2PDrmbk = 10212, X86_VPERMT2PDrmbkz = 10213, X86_VPERMT2PDrmk = 10214, X86_VPERMT2PDrmkz = 10215, X86_VPERMT2PDrr = 10216, X86_VPERMT2PDrrk = 10217, X86_VPERMT2PDrrkz = 10218, X86_VPERMT2PS128rm = 10219, X86_VPERMT2PS128rmb = 10220, X86_VPERMT2PS128rmbk = 10221, X86_VPERMT2PS128rmbkz = 10222, X86_VPERMT2PS128rmk = 10223, X86_VPERMT2PS128rmkz = 10224, X86_VPERMT2PS128rr = 10225, X86_VPERMT2PS128rrk = 10226, X86_VPERMT2PS128rrkz = 10227, X86_VPERMT2PS256rm = 10228, X86_VPERMT2PS256rmb = 10229, X86_VPERMT2PS256rmbk = 10230, X86_VPERMT2PS256rmbkz = 10231, X86_VPERMT2PS256rmk = 10232, X86_VPERMT2PS256rmkz = 10233, X86_VPERMT2PS256rr = 10234, X86_VPERMT2PS256rrk = 10235, X86_VPERMT2PS256rrkz = 10236, X86_VPERMT2PSrm = 10237, X86_VPERMT2PSrmb = 10238, X86_VPERMT2PSrmbk = 10239, X86_VPERMT2PSrmbkz = 10240, X86_VPERMT2PSrmk = 10241, X86_VPERMT2PSrmkz = 10242, X86_VPERMT2PSrr = 10243, X86_VPERMT2PSrrk = 10244, X86_VPERMT2PSrrkz = 10245, X86_VPERMT2Q128rm = 10246, X86_VPERMT2Q128rmb = 10247, X86_VPERMT2Q128rmbk = 10248, X86_VPERMT2Q128rmbkz = 10249, X86_VPERMT2Q128rmk = 10250, X86_VPERMT2Q128rmkz = 10251, X86_VPERMT2Q128rr = 10252, X86_VPERMT2Q128rrk = 10253, X86_VPERMT2Q128rrkz = 10254, X86_VPERMT2Q256rm = 10255, X86_VPERMT2Q256rmb = 10256, X86_VPERMT2Q256rmbk = 10257, X86_VPERMT2Q256rmbkz = 10258, X86_VPERMT2Q256rmk = 10259, X86_VPERMT2Q256rmkz = 10260, X86_VPERMT2Q256rr = 10261, X86_VPERMT2Q256rrk = 10262, X86_VPERMT2Q256rrkz = 10263, X86_VPERMT2Qrm = 10264, X86_VPERMT2Qrmb = 10265, X86_VPERMT2Qrmbk = 10266, X86_VPERMT2Qrmbkz = 10267, X86_VPERMT2Qrmk = 10268, X86_VPERMT2Qrmkz = 10269, X86_VPERMT2Qrr = 10270, X86_VPERMT2Qrrk = 10271, X86_VPERMT2Qrrkz = 10272, X86_VPERMT2W128rm = 10273, X86_VPERMT2W128rmk = 10274, X86_VPERMT2W128rmkz = 10275, X86_VPERMT2W128rr = 10276, X86_VPERMT2W128rrk = 10277, X86_VPERMT2W128rrkz = 10278, X86_VPERMT2W256rm = 10279, X86_VPERMT2W256rmk = 10280, X86_VPERMT2W256rmkz = 10281, X86_VPERMT2W256rr = 10282, X86_VPERMT2W256rrk = 10283, X86_VPERMT2W256rrkz = 10284, X86_VPERMT2Wrm = 10285, X86_VPERMT2Wrmk = 10286, X86_VPERMT2Wrmkz = 10287, X86_VPERMT2Wrr = 10288, X86_VPERMT2Wrrk = 10289, X86_VPERMT2Wrrkz = 10290, X86_VPERMWZ128rm = 10291, X86_VPERMWZ128rmk = 10292, X86_VPERMWZ128rmkz = 10293, X86_VPERMWZ128rr = 10294, X86_VPERMWZ128rrk = 10295, X86_VPERMWZ128rrkz = 10296, X86_VPERMWZ256rm = 10297, X86_VPERMWZ256rmk = 10298, X86_VPERMWZ256rmkz = 10299, X86_VPERMWZ256rr = 10300, X86_VPERMWZ256rrk = 10301, X86_VPERMWZ256rrkz = 10302, X86_VPERMWZrm = 10303, X86_VPERMWZrmk = 10304, X86_VPERMWZrmkz = 10305, X86_VPERMWZrr = 10306, X86_VPERMWZrrk = 10307, X86_VPERMWZrrkz = 10308, X86_VPEXPANDBZ128rm = 10309, X86_VPEXPANDBZ128rmk = 10310, X86_VPEXPANDBZ128rmkz = 10311, X86_VPEXPANDBZ128rr = 10312, X86_VPEXPANDBZ128rrk = 10313, X86_VPEXPANDBZ128rrkz = 10314, X86_VPEXPANDBZ256rm = 10315, X86_VPEXPANDBZ256rmk = 10316, X86_VPEXPANDBZ256rmkz = 10317, X86_VPEXPANDBZ256rr = 10318, X86_VPEXPANDBZ256rrk = 10319, X86_VPEXPANDBZ256rrkz = 10320, X86_VPEXPANDBZrm = 10321, X86_VPEXPANDBZrmk = 10322, X86_VPEXPANDBZrmkz = 10323, X86_VPEXPANDBZrr = 10324, X86_VPEXPANDBZrrk = 10325, X86_VPEXPANDBZrrkz = 10326, X86_VPEXPANDDZ128rm = 10327, X86_VPEXPANDDZ128rmk = 10328, X86_VPEXPANDDZ128rmkz = 10329, X86_VPEXPANDDZ128rr = 10330, X86_VPEXPANDDZ128rrk = 10331, X86_VPEXPANDDZ128rrkz = 10332, X86_VPEXPANDDZ256rm = 10333, X86_VPEXPANDDZ256rmk = 10334, X86_VPEXPANDDZ256rmkz = 10335, X86_VPEXPANDDZ256rr = 10336, X86_VPEXPANDDZ256rrk = 10337, X86_VPEXPANDDZ256rrkz = 10338, X86_VPEXPANDDZrm = 10339, X86_VPEXPANDDZrmk = 10340, X86_VPEXPANDDZrmkz = 10341, X86_VPEXPANDDZrr = 10342, X86_VPEXPANDDZrrk = 10343, X86_VPEXPANDDZrrkz = 10344, X86_VPEXPANDQZ128rm = 10345, X86_VPEXPANDQZ128rmk = 10346, X86_VPEXPANDQZ128rmkz = 10347, X86_VPEXPANDQZ128rr = 10348, X86_VPEXPANDQZ128rrk = 10349, X86_VPEXPANDQZ128rrkz = 10350, X86_VPEXPANDQZ256rm = 10351, X86_VPEXPANDQZ256rmk = 10352, X86_VPEXPANDQZ256rmkz = 10353, X86_VPEXPANDQZ256rr = 10354, X86_VPEXPANDQZ256rrk = 10355, X86_VPEXPANDQZ256rrkz = 10356, X86_VPEXPANDQZrm = 10357, X86_VPEXPANDQZrmk = 10358, X86_VPEXPANDQZrmkz = 10359, X86_VPEXPANDQZrr = 10360, X86_VPEXPANDQZrrk = 10361, X86_VPEXPANDQZrrkz = 10362, X86_VPEXPANDWZ128rm = 10363, X86_VPEXPANDWZ128rmk = 10364, X86_VPEXPANDWZ128rmkz = 10365, X86_VPEXPANDWZ128rr = 10366, X86_VPEXPANDWZ128rrk = 10367, X86_VPEXPANDWZ128rrkz = 10368, X86_VPEXPANDWZ256rm = 10369, X86_VPEXPANDWZ256rmk = 10370, X86_VPEXPANDWZ256rmkz = 10371, X86_VPEXPANDWZ256rr = 10372, X86_VPEXPANDWZ256rrk = 10373, X86_VPEXPANDWZ256rrkz = 10374, X86_VPEXPANDWZrm = 10375, X86_VPEXPANDWZrmk = 10376, X86_VPEXPANDWZrmkz = 10377, X86_VPEXPANDWZrr = 10378, X86_VPEXPANDWZrrk = 10379, X86_VPEXPANDWZrrkz = 10380, X86_VPEXTRBZmr = 10381, X86_VPEXTRBZrr = 10382, X86_VPEXTRBmr = 10383, X86_VPEXTRBrr = 10384, X86_VPEXTRDZmr = 10385, X86_VPEXTRDZrr = 10386, X86_VPEXTRDmr = 10387, X86_VPEXTRDrr = 10388, X86_VPEXTRQZmr = 10389, X86_VPEXTRQZrr = 10390, X86_VPEXTRQmr = 10391, X86_VPEXTRQrr = 10392, X86_VPEXTRWZmr = 10393, X86_VPEXTRWZrr = 10394, X86_VPEXTRWZrr_REV = 10395, X86_VPEXTRWmr = 10396, X86_VPEXTRWrr = 10397, X86_VPEXTRWrr_REV = 10398, X86_VPGATHERDDYrm = 10399, X86_VPGATHERDDZ128rm = 10400, X86_VPGATHERDDZ256rm = 10401, X86_VPGATHERDDZrm = 10402, X86_VPGATHERDDrm = 10403, X86_VPGATHERDQYrm = 10404, X86_VPGATHERDQZ128rm = 10405, X86_VPGATHERDQZ256rm = 10406, X86_VPGATHERDQZrm = 10407, X86_VPGATHERDQrm = 10408, X86_VPGATHERQDYrm = 10409, X86_VPGATHERQDZ128rm = 10410, X86_VPGATHERQDZ256rm = 10411, X86_VPGATHERQDZrm = 10412, X86_VPGATHERQDrm = 10413, X86_VPGATHERQQYrm = 10414, X86_VPGATHERQQZ128rm = 10415, X86_VPGATHERQQZ256rm = 10416, X86_VPGATHERQQZrm = 10417, X86_VPGATHERQQrm = 10418, X86_VPHADDBDrm = 10419, X86_VPHADDBDrr = 10420, X86_VPHADDBQrm = 10421, X86_VPHADDBQrr = 10422, X86_VPHADDBWrm = 10423, X86_VPHADDBWrr = 10424, X86_VPHADDDQrm = 10425, X86_VPHADDDQrr = 10426, X86_VPHADDDYrm = 10427, X86_VPHADDDYrr = 10428, X86_VPHADDDrm = 10429, X86_VPHADDDrr = 10430, X86_VPHADDSWYrm = 10431, X86_VPHADDSWYrr = 10432, X86_VPHADDSWrm = 10433, X86_VPHADDSWrr = 10434, X86_VPHADDUBDrm = 10435, X86_VPHADDUBDrr = 10436, X86_VPHADDUBQrm = 10437, X86_VPHADDUBQrr = 10438, X86_VPHADDUBWrm = 10439, X86_VPHADDUBWrr = 10440, X86_VPHADDUDQrm = 10441, X86_VPHADDUDQrr = 10442, X86_VPHADDUWDrm = 10443, X86_VPHADDUWDrr = 10444, X86_VPHADDUWQrm = 10445, X86_VPHADDUWQrr = 10446, X86_VPHADDWDrm = 10447, X86_VPHADDWDrr = 10448, X86_VPHADDWQrm = 10449, X86_VPHADDWQrr = 10450, X86_VPHADDWYrm = 10451, X86_VPHADDWYrr = 10452, X86_VPHADDWrm = 10453, X86_VPHADDWrr = 10454, X86_VPHMINPOSUWrm = 10455, X86_VPHMINPOSUWrr = 10456, X86_VPHSUBBWrm = 10457, X86_VPHSUBBWrr = 10458, X86_VPHSUBDQrm = 10459, X86_VPHSUBDQrr = 10460, X86_VPHSUBDYrm = 10461, X86_VPHSUBDYrr = 10462, X86_VPHSUBDrm = 10463, X86_VPHSUBDrr = 10464, X86_VPHSUBSWYrm = 10465, X86_VPHSUBSWYrr = 10466, X86_VPHSUBSWrm = 10467, X86_VPHSUBSWrr = 10468, X86_VPHSUBWDrm = 10469, X86_VPHSUBWDrr = 10470, X86_VPHSUBWYrm = 10471, X86_VPHSUBWYrr = 10472, X86_VPHSUBWrm = 10473, X86_VPHSUBWrr = 10474, X86_VPINSRBZrm = 10475, X86_VPINSRBZrr = 10476, X86_VPINSRBrm = 10477, X86_VPINSRBrr = 10478, X86_VPINSRDZrm = 10479, X86_VPINSRDZrr = 10480, X86_VPINSRDrm = 10481, X86_VPINSRDrr = 10482, X86_VPINSRQZrm = 10483, X86_VPINSRQZrr = 10484, X86_VPINSRQrm = 10485, X86_VPINSRQrr = 10486, X86_VPINSRWZrm = 10487, X86_VPINSRWZrr = 10488, X86_VPINSRWrm = 10489, X86_VPINSRWrr = 10490, X86_VPLZCNTDZ128rm = 10491, X86_VPLZCNTDZ128rmb = 10492, X86_VPLZCNTDZ128rmbk = 10493, X86_VPLZCNTDZ128rmbkz = 10494, X86_VPLZCNTDZ128rmk = 10495, X86_VPLZCNTDZ128rmkz = 10496, X86_VPLZCNTDZ128rr = 10497, X86_VPLZCNTDZ128rrk = 10498, X86_VPLZCNTDZ128rrkz = 10499, X86_VPLZCNTDZ256rm = 10500, X86_VPLZCNTDZ256rmb = 10501, X86_VPLZCNTDZ256rmbk = 10502, X86_VPLZCNTDZ256rmbkz = 10503, X86_VPLZCNTDZ256rmk = 10504, X86_VPLZCNTDZ256rmkz = 10505, X86_VPLZCNTDZ256rr = 10506, X86_VPLZCNTDZ256rrk = 10507, X86_VPLZCNTDZ256rrkz = 10508, X86_VPLZCNTDZrm = 10509, X86_VPLZCNTDZrmb = 10510, X86_VPLZCNTDZrmbk = 10511, X86_VPLZCNTDZrmbkz = 10512, X86_VPLZCNTDZrmk = 10513, X86_VPLZCNTDZrmkz = 10514, X86_VPLZCNTDZrr = 10515, X86_VPLZCNTDZrrk = 10516, X86_VPLZCNTDZrrkz = 10517, X86_VPLZCNTQZ128rm = 10518, X86_VPLZCNTQZ128rmb = 10519, X86_VPLZCNTQZ128rmbk = 10520, X86_VPLZCNTQZ128rmbkz = 10521, X86_VPLZCNTQZ128rmk = 10522, X86_VPLZCNTQZ128rmkz = 10523, X86_VPLZCNTQZ128rr = 10524, X86_VPLZCNTQZ128rrk = 10525, X86_VPLZCNTQZ128rrkz = 10526, X86_VPLZCNTQZ256rm = 10527, X86_VPLZCNTQZ256rmb = 10528, X86_VPLZCNTQZ256rmbk = 10529, X86_VPLZCNTQZ256rmbkz = 10530, X86_VPLZCNTQZ256rmk = 10531, X86_VPLZCNTQZ256rmkz = 10532, X86_VPLZCNTQZ256rr = 10533, X86_VPLZCNTQZ256rrk = 10534, X86_VPLZCNTQZ256rrkz = 10535, X86_VPLZCNTQZrm = 10536, X86_VPLZCNTQZrmb = 10537, X86_VPLZCNTQZrmbk = 10538, X86_VPLZCNTQZrmbkz = 10539, X86_VPLZCNTQZrmk = 10540, X86_VPLZCNTQZrmkz = 10541, X86_VPLZCNTQZrr = 10542, X86_VPLZCNTQZrrk = 10543, X86_VPLZCNTQZrrkz = 10544, X86_VPMACSDDrm = 10545, X86_VPMACSDDrr = 10546, X86_VPMACSDQHrm = 10547, X86_VPMACSDQHrr = 10548, X86_VPMACSDQLrm = 10549, X86_VPMACSDQLrr = 10550, X86_VPMACSSDDrm = 10551, X86_VPMACSSDDrr = 10552, X86_VPMACSSDQHrm = 10553, X86_VPMACSSDQHrr = 10554, X86_VPMACSSDQLrm = 10555, X86_VPMACSSDQLrr = 10556, X86_VPMACSSWDrm = 10557, X86_VPMACSSWDrr = 10558, X86_VPMACSSWWrm = 10559, X86_VPMACSSWWrr = 10560, X86_VPMACSWDrm = 10561, X86_VPMACSWDrr = 10562, X86_VPMACSWWrm = 10563, X86_VPMACSWWrr = 10564, X86_VPMADCSSWDrm = 10565, X86_VPMADCSSWDrr = 10566, X86_VPMADCSWDrm = 10567, X86_VPMADCSWDrr = 10568, X86_VPMADD52HUQZ128m = 10569, X86_VPMADD52HUQZ128mb = 10570, X86_VPMADD52HUQZ128mbk = 10571, X86_VPMADD52HUQZ128mbkz = 10572, X86_VPMADD52HUQZ128mk = 10573, X86_VPMADD52HUQZ128mkz = 10574, X86_VPMADD52HUQZ128r = 10575, X86_VPMADD52HUQZ128rk = 10576, X86_VPMADD52HUQZ128rkz = 10577, X86_VPMADD52HUQZ256m = 10578, X86_VPMADD52HUQZ256mb = 10579, X86_VPMADD52HUQZ256mbk = 10580, X86_VPMADD52HUQZ256mbkz = 10581, X86_VPMADD52HUQZ256mk = 10582, X86_VPMADD52HUQZ256mkz = 10583, X86_VPMADD52HUQZ256r = 10584, X86_VPMADD52HUQZ256rk = 10585, X86_VPMADD52HUQZ256rkz = 10586, X86_VPMADD52HUQZm = 10587, X86_VPMADD52HUQZmb = 10588, X86_VPMADD52HUQZmbk = 10589, X86_VPMADD52HUQZmbkz = 10590, X86_VPMADD52HUQZmk = 10591, X86_VPMADD52HUQZmkz = 10592, X86_VPMADD52HUQZr = 10593, X86_VPMADD52HUQZrk = 10594, X86_VPMADD52HUQZrkz = 10595, X86_VPMADD52LUQZ128m = 10596, X86_VPMADD52LUQZ128mb = 10597, X86_VPMADD52LUQZ128mbk = 10598, X86_VPMADD52LUQZ128mbkz = 10599, X86_VPMADD52LUQZ128mk = 10600, X86_VPMADD52LUQZ128mkz = 10601, X86_VPMADD52LUQZ128r = 10602, X86_VPMADD52LUQZ128rk = 10603, X86_VPMADD52LUQZ128rkz = 10604, X86_VPMADD52LUQZ256m = 10605, X86_VPMADD52LUQZ256mb = 10606, X86_VPMADD52LUQZ256mbk = 10607, X86_VPMADD52LUQZ256mbkz = 10608, X86_VPMADD52LUQZ256mk = 10609, X86_VPMADD52LUQZ256mkz = 10610, X86_VPMADD52LUQZ256r = 10611, X86_VPMADD52LUQZ256rk = 10612, X86_VPMADD52LUQZ256rkz = 10613, X86_VPMADD52LUQZm = 10614, X86_VPMADD52LUQZmb = 10615, X86_VPMADD52LUQZmbk = 10616, X86_VPMADD52LUQZmbkz = 10617, X86_VPMADD52LUQZmk = 10618, X86_VPMADD52LUQZmkz = 10619, X86_VPMADD52LUQZr = 10620, X86_VPMADD52LUQZrk = 10621, X86_VPMADD52LUQZrkz = 10622, X86_VPMADDUBSWYrm = 10623, X86_VPMADDUBSWYrr = 10624, X86_VPMADDUBSWZ128rm = 10625, X86_VPMADDUBSWZ128rmk = 10626, X86_VPMADDUBSWZ128rmkz = 10627, X86_VPMADDUBSWZ128rr = 10628, X86_VPMADDUBSWZ128rrk = 10629, X86_VPMADDUBSWZ128rrkz = 10630, X86_VPMADDUBSWZ256rm = 10631, X86_VPMADDUBSWZ256rmk = 10632, X86_VPMADDUBSWZ256rmkz = 10633, X86_VPMADDUBSWZ256rr = 10634, X86_VPMADDUBSWZ256rrk = 10635, X86_VPMADDUBSWZ256rrkz = 10636, X86_VPMADDUBSWZrm = 10637, X86_VPMADDUBSWZrmk = 10638, X86_VPMADDUBSWZrmkz = 10639, X86_VPMADDUBSWZrr = 10640, X86_VPMADDUBSWZrrk = 10641, X86_VPMADDUBSWZrrkz = 10642, X86_VPMADDUBSWrm = 10643, X86_VPMADDUBSWrr = 10644, X86_VPMADDWDYrm = 10645, X86_VPMADDWDYrr = 10646, X86_VPMADDWDZ128rm = 10647, X86_VPMADDWDZ128rmk = 10648, X86_VPMADDWDZ128rmkz = 10649, X86_VPMADDWDZ128rr = 10650, X86_VPMADDWDZ128rrk = 10651, X86_VPMADDWDZ128rrkz = 10652, X86_VPMADDWDZ256rm = 10653, X86_VPMADDWDZ256rmk = 10654, X86_VPMADDWDZ256rmkz = 10655, X86_VPMADDWDZ256rr = 10656, X86_VPMADDWDZ256rrk = 10657, X86_VPMADDWDZ256rrkz = 10658, X86_VPMADDWDZrm = 10659, X86_VPMADDWDZrmk = 10660, X86_VPMADDWDZrmkz = 10661, X86_VPMADDWDZrr = 10662, X86_VPMADDWDZrrk = 10663, X86_VPMADDWDZrrkz = 10664, X86_VPMADDWDrm = 10665, X86_VPMADDWDrr = 10666, X86_VPMASKMOVDYmr = 10667, X86_VPMASKMOVDYrm = 10668, X86_VPMASKMOVDmr = 10669, X86_VPMASKMOVDrm = 10670, X86_VPMASKMOVQYmr = 10671, X86_VPMASKMOVQYrm = 10672, X86_VPMASKMOVQmr = 10673, X86_VPMASKMOVQrm = 10674, X86_VPMAXSBYrm = 10675, X86_VPMAXSBYrr = 10676, X86_VPMAXSBZ128rm = 10677, X86_VPMAXSBZ128rmk = 10678, X86_VPMAXSBZ128rmkz = 10679, X86_VPMAXSBZ128rr = 10680, X86_VPMAXSBZ128rrk = 10681, X86_VPMAXSBZ128rrkz = 10682, X86_VPMAXSBZ256rm = 10683, X86_VPMAXSBZ256rmk = 10684, X86_VPMAXSBZ256rmkz = 10685, X86_VPMAXSBZ256rr = 10686, X86_VPMAXSBZ256rrk = 10687, X86_VPMAXSBZ256rrkz = 10688, X86_VPMAXSBZrm = 10689, X86_VPMAXSBZrmk = 10690, X86_VPMAXSBZrmkz = 10691, X86_VPMAXSBZrr = 10692, X86_VPMAXSBZrrk = 10693, X86_VPMAXSBZrrkz = 10694, X86_VPMAXSBrm = 10695, X86_VPMAXSBrr = 10696, X86_VPMAXSDYrm = 10697, X86_VPMAXSDYrr = 10698, X86_VPMAXSDZ128rm = 10699, X86_VPMAXSDZ128rmb = 10700, X86_VPMAXSDZ128rmbk = 10701, X86_VPMAXSDZ128rmbkz = 10702, X86_VPMAXSDZ128rmk = 10703, X86_VPMAXSDZ128rmkz = 10704, X86_VPMAXSDZ128rr = 10705, X86_VPMAXSDZ128rrk = 10706, X86_VPMAXSDZ128rrkz = 10707, X86_VPMAXSDZ256rm = 10708, X86_VPMAXSDZ256rmb = 10709, X86_VPMAXSDZ256rmbk = 10710, X86_VPMAXSDZ256rmbkz = 10711, X86_VPMAXSDZ256rmk = 10712, X86_VPMAXSDZ256rmkz = 10713, X86_VPMAXSDZ256rr = 10714, X86_VPMAXSDZ256rrk = 10715, X86_VPMAXSDZ256rrkz = 10716, X86_VPMAXSDZrm = 10717, X86_VPMAXSDZrmb = 10718, X86_VPMAXSDZrmbk = 10719, X86_VPMAXSDZrmbkz = 10720, X86_VPMAXSDZrmk = 10721, X86_VPMAXSDZrmkz = 10722, X86_VPMAXSDZrr = 10723, X86_VPMAXSDZrrk = 10724, X86_VPMAXSDZrrkz = 10725, X86_VPMAXSDrm = 10726, X86_VPMAXSDrr = 10727, X86_VPMAXSQZ128rm = 10728, X86_VPMAXSQZ128rmb = 10729, X86_VPMAXSQZ128rmbk = 10730, X86_VPMAXSQZ128rmbkz = 10731, X86_VPMAXSQZ128rmk = 10732, X86_VPMAXSQZ128rmkz = 10733, X86_VPMAXSQZ128rr = 10734, X86_VPMAXSQZ128rrk = 10735, X86_VPMAXSQZ128rrkz = 10736, X86_VPMAXSQZ256rm = 10737, X86_VPMAXSQZ256rmb = 10738, X86_VPMAXSQZ256rmbk = 10739, X86_VPMAXSQZ256rmbkz = 10740, X86_VPMAXSQZ256rmk = 10741, X86_VPMAXSQZ256rmkz = 10742, X86_VPMAXSQZ256rr = 10743, X86_VPMAXSQZ256rrk = 10744, X86_VPMAXSQZ256rrkz = 10745, X86_VPMAXSQZrm = 10746, X86_VPMAXSQZrmb = 10747, X86_VPMAXSQZrmbk = 10748, X86_VPMAXSQZrmbkz = 10749, X86_VPMAXSQZrmk = 10750, X86_VPMAXSQZrmkz = 10751, X86_VPMAXSQZrr = 10752, X86_VPMAXSQZrrk = 10753, X86_VPMAXSQZrrkz = 10754, X86_VPMAXSWYrm = 10755, X86_VPMAXSWYrr = 10756, X86_VPMAXSWZ128rm = 10757, X86_VPMAXSWZ128rmk = 10758, X86_VPMAXSWZ128rmkz = 10759, X86_VPMAXSWZ128rr = 10760, X86_VPMAXSWZ128rrk = 10761, X86_VPMAXSWZ128rrkz = 10762, X86_VPMAXSWZ256rm = 10763, X86_VPMAXSWZ256rmk = 10764, X86_VPMAXSWZ256rmkz = 10765, X86_VPMAXSWZ256rr = 10766, X86_VPMAXSWZ256rrk = 10767, X86_VPMAXSWZ256rrkz = 10768, X86_VPMAXSWZrm = 10769, X86_VPMAXSWZrmk = 10770, X86_VPMAXSWZrmkz = 10771, X86_VPMAXSWZrr = 10772, X86_VPMAXSWZrrk = 10773, X86_VPMAXSWZrrkz = 10774, X86_VPMAXSWrm = 10775, X86_VPMAXSWrr = 10776, X86_VPMAXUBYrm = 10777, X86_VPMAXUBYrr = 10778, X86_VPMAXUBZ128rm = 10779, X86_VPMAXUBZ128rmk = 10780, X86_VPMAXUBZ128rmkz = 10781, X86_VPMAXUBZ128rr = 10782, X86_VPMAXUBZ128rrk = 10783, X86_VPMAXUBZ128rrkz = 10784, X86_VPMAXUBZ256rm = 10785, X86_VPMAXUBZ256rmk = 10786, X86_VPMAXUBZ256rmkz = 10787, X86_VPMAXUBZ256rr = 10788, X86_VPMAXUBZ256rrk = 10789, X86_VPMAXUBZ256rrkz = 10790, X86_VPMAXUBZrm = 10791, X86_VPMAXUBZrmk = 10792, X86_VPMAXUBZrmkz = 10793, X86_VPMAXUBZrr = 10794, X86_VPMAXUBZrrk = 10795, X86_VPMAXUBZrrkz = 10796, X86_VPMAXUBrm = 10797, X86_VPMAXUBrr = 10798, X86_VPMAXUDYrm = 10799, X86_VPMAXUDYrr = 10800, X86_VPMAXUDZ128rm = 10801, X86_VPMAXUDZ128rmb = 10802, X86_VPMAXUDZ128rmbk = 10803, X86_VPMAXUDZ128rmbkz = 10804, X86_VPMAXUDZ128rmk = 10805, X86_VPMAXUDZ128rmkz = 10806, X86_VPMAXUDZ128rr = 10807, X86_VPMAXUDZ128rrk = 10808, X86_VPMAXUDZ128rrkz = 10809, X86_VPMAXUDZ256rm = 10810, X86_VPMAXUDZ256rmb = 10811, X86_VPMAXUDZ256rmbk = 10812, X86_VPMAXUDZ256rmbkz = 10813, X86_VPMAXUDZ256rmk = 10814, X86_VPMAXUDZ256rmkz = 10815, X86_VPMAXUDZ256rr = 10816, X86_VPMAXUDZ256rrk = 10817, X86_VPMAXUDZ256rrkz = 10818, X86_VPMAXUDZrm = 10819, X86_VPMAXUDZrmb = 10820, X86_VPMAXUDZrmbk = 10821, X86_VPMAXUDZrmbkz = 10822, X86_VPMAXUDZrmk = 10823, X86_VPMAXUDZrmkz = 10824, X86_VPMAXUDZrr = 10825, X86_VPMAXUDZrrk = 10826, X86_VPMAXUDZrrkz = 10827, X86_VPMAXUDrm = 10828, X86_VPMAXUDrr = 10829, X86_VPMAXUQZ128rm = 10830, X86_VPMAXUQZ128rmb = 10831, X86_VPMAXUQZ128rmbk = 10832, X86_VPMAXUQZ128rmbkz = 10833, X86_VPMAXUQZ128rmk = 10834, X86_VPMAXUQZ128rmkz = 10835, X86_VPMAXUQZ128rr = 10836, X86_VPMAXUQZ128rrk = 10837, X86_VPMAXUQZ128rrkz = 10838, X86_VPMAXUQZ256rm = 10839, X86_VPMAXUQZ256rmb = 10840, X86_VPMAXUQZ256rmbk = 10841, X86_VPMAXUQZ256rmbkz = 10842, X86_VPMAXUQZ256rmk = 10843, X86_VPMAXUQZ256rmkz = 10844, X86_VPMAXUQZ256rr = 10845, X86_VPMAXUQZ256rrk = 10846, X86_VPMAXUQZ256rrkz = 10847, X86_VPMAXUQZrm = 10848, X86_VPMAXUQZrmb = 10849, X86_VPMAXUQZrmbk = 10850, X86_VPMAXUQZrmbkz = 10851, X86_VPMAXUQZrmk = 10852, X86_VPMAXUQZrmkz = 10853, X86_VPMAXUQZrr = 10854, X86_VPMAXUQZrrk = 10855, X86_VPMAXUQZrrkz = 10856, X86_VPMAXUWYrm = 10857, X86_VPMAXUWYrr = 10858, X86_VPMAXUWZ128rm = 10859, X86_VPMAXUWZ128rmk = 10860, X86_VPMAXUWZ128rmkz = 10861, X86_VPMAXUWZ128rr = 10862, X86_VPMAXUWZ128rrk = 10863, X86_VPMAXUWZ128rrkz = 10864, X86_VPMAXUWZ256rm = 10865, X86_VPMAXUWZ256rmk = 10866, X86_VPMAXUWZ256rmkz = 10867, X86_VPMAXUWZ256rr = 10868, X86_VPMAXUWZ256rrk = 10869, X86_VPMAXUWZ256rrkz = 10870, X86_VPMAXUWZrm = 10871, X86_VPMAXUWZrmk = 10872, X86_VPMAXUWZrmkz = 10873, X86_VPMAXUWZrr = 10874, X86_VPMAXUWZrrk = 10875, X86_VPMAXUWZrrkz = 10876, X86_VPMAXUWrm = 10877, X86_VPMAXUWrr = 10878, X86_VPMINSBYrm = 10879, X86_VPMINSBYrr = 10880, X86_VPMINSBZ128rm = 10881, X86_VPMINSBZ128rmk = 10882, X86_VPMINSBZ128rmkz = 10883, X86_VPMINSBZ128rr = 10884, X86_VPMINSBZ128rrk = 10885, X86_VPMINSBZ128rrkz = 10886, X86_VPMINSBZ256rm = 10887, X86_VPMINSBZ256rmk = 10888, X86_VPMINSBZ256rmkz = 10889, X86_VPMINSBZ256rr = 10890, X86_VPMINSBZ256rrk = 10891, X86_VPMINSBZ256rrkz = 10892, X86_VPMINSBZrm = 10893, X86_VPMINSBZrmk = 10894, X86_VPMINSBZrmkz = 10895, X86_VPMINSBZrr = 10896, X86_VPMINSBZrrk = 10897, X86_VPMINSBZrrkz = 10898, X86_VPMINSBrm = 10899, X86_VPMINSBrr = 10900, X86_VPMINSDYrm = 10901, X86_VPMINSDYrr = 10902, X86_VPMINSDZ128rm = 10903, X86_VPMINSDZ128rmb = 10904, X86_VPMINSDZ128rmbk = 10905, X86_VPMINSDZ128rmbkz = 10906, X86_VPMINSDZ128rmk = 10907, X86_VPMINSDZ128rmkz = 10908, X86_VPMINSDZ128rr = 10909, X86_VPMINSDZ128rrk = 10910, X86_VPMINSDZ128rrkz = 10911, X86_VPMINSDZ256rm = 10912, X86_VPMINSDZ256rmb = 10913, X86_VPMINSDZ256rmbk = 10914, X86_VPMINSDZ256rmbkz = 10915, X86_VPMINSDZ256rmk = 10916, X86_VPMINSDZ256rmkz = 10917, X86_VPMINSDZ256rr = 10918, X86_VPMINSDZ256rrk = 10919, X86_VPMINSDZ256rrkz = 10920, X86_VPMINSDZrm = 10921, X86_VPMINSDZrmb = 10922, X86_VPMINSDZrmbk = 10923, X86_VPMINSDZrmbkz = 10924, X86_VPMINSDZrmk = 10925, X86_VPMINSDZrmkz = 10926, X86_VPMINSDZrr = 10927, X86_VPMINSDZrrk = 10928, X86_VPMINSDZrrkz = 10929, X86_VPMINSDrm = 10930, X86_VPMINSDrr = 10931, X86_VPMINSQZ128rm = 10932, X86_VPMINSQZ128rmb = 10933, X86_VPMINSQZ128rmbk = 10934, X86_VPMINSQZ128rmbkz = 10935, X86_VPMINSQZ128rmk = 10936, X86_VPMINSQZ128rmkz = 10937, X86_VPMINSQZ128rr = 10938, X86_VPMINSQZ128rrk = 10939, X86_VPMINSQZ128rrkz = 10940, X86_VPMINSQZ256rm = 10941, X86_VPMINSQZ256rmb = 10942, X86_VPMINSQZ256rmbk = 10943, X86_VPMINSQZ256rmbkz = 10944, X86_VPMINSQZ256rmk = 10945, X86_VPMINSQZ256rmkz = 10946, X86_VPMINSQZ256rr = 10947, X86_VPMINSQZ256rrk = 10948, X86_VPMINSQZ256rrkz = 10949, X86_VPMINSQZrm = 10950, X86_VPMINSQZrmb = 10951, X86_VPMINSQZrmbk = 10952, X86_VPMINSQZrmbkz = 10953, X86_VPMINSQZrmk = 10954, X86_VPMINSQZrmkz = 10955, X86_VPMINSQZrr = 10956, X86_VPMINSQZrrk = 10957, X86_VPMINSQZrrkz = 10958, X86_VPMINSWYrm = 10959, X86_VPMINSWYrr = 10960, X86_VPMINSWZ128rm = 10961, X86_VPMINSWZ128rmk = 10962, X86_VPMINSWZ128rmkz = 10963, X86_VPMINSWZ128rr = 10964, X86_VPMINSWZ128rrk = 10965, X86_VPMINSWZ128rrkz = 10966, X86_VPMINSWZ256rm = 10967, X86_VPMINSWZ256rmk = 10968, X86_VPMINSWZ256rmkz = 10969, X86_VPMINSWZ256rr = 10970, X86_VPMINSWZ256rrk = 10971, X86_VPMINSWZ256rrkz = 10972, X86_VPMINSWZrm = 10973, X86_VPMINSWZrmk = 10974, X86_VPMINSWZrmkz = 10975, X86_VPMINSWZrr = 10976, X86_VPMINSWZrrk = 10977, X86_VPMINSWZrrkz = 10978, X86_VPMINSWrm = 10979, X86_VPMINSWrr = 10980, X86_VPMINUBYrm = 10981, X86_VPMINUBYrr = 10982, X86_VPMINUBZ128rm = 10983, X86_VPMINUBZ128rmk = 10984, X86_VPMINUBZ128rmkz = 10985, X86_VPMINUBZ128rr = 10986, X86_VPMINUBZ128rrk = 10987, X86_VPMINUBZ128rrkz = 10988, X86_VPMINUBZ256rm = 10989, X86_VPMINUBZ256rmk = 10990, X86_VPMINUBZ256rmkz = 10991, X86_VPMINUBZ256rr = 10992, X86_VPMINUBZ256rrk = 10993, X86_VPMINUBZ256rrkz = 10994, X86_VPMINUBZrm = 10995, X86_VPMINUBZrmk = 10996, X86_VPMINUBZrmkz = 10997, X86_VPMINUBZrr = 10998, X86_VPMINUBZrrk = 10999, X86_VPMINUBZrrkz = 11000, X86_VPMINUBrm = 11001, X86_VPMINUBrr = 11002, X86_VPMINUDYrm = 11003, X86_VPMINUDYrr = 11004, X86_VPMINUDZ128rm = 11005, X86_VPMINUDZ128rmb = 11006, X86_VPMINUDZ128rmbk = 11007, X86_VPMINUDZ128rmbkz = 11008, X86_VPMINUDZ128rmk = 11009, X86_VPMINUDZ128rmkz = 11010, X86_VPMINUDZ128rr = 11011, X86_VPMINUDZ128rrk = 11012, X86_VPMINUDZ128rrkz = 11013, X86_VPMINUDZ256rm = 11014, X86_VPMINUDZ256rmb = 11015, X86_VPMINUDZ256rmbk = 11016, X86_VPMINUDZ256rmbkz = 11017, X86_VPMINUDZ256rmk = 11018, X86_VPMINUDZ256rmkz = 11019, X86_VPMINUDZ256rr = 11020, X86_VPMINUDZ256rrk = 11021, X86_VPMINUDZ256rrkz = 11022, X86_VPMINUDZrm = 11023, X86_VPMINUDZrmb = 11024, X86_VPMINUDZrmbk = 11025, X86_VPMINUDZrmbkz = 11026, X86_VPMINUDZrmk = 11027, X86_VPMINUDZrmkz = 11028, X86_VPMINUDZrr = 11029, X86_VPMINUDZrrk = 11030, X86_VPMINUDZrrkz = 11031, X86_VPMINUDrm = 11032, X86_VPMINUDrr = 11033, X86_VPMINUQZ128rm = 11034, X86_VPMINUQZ128rmb = 11035, X86_VPMINUQZ128rmbk = 11036, X86_VPMINUQZ128rmbkz = 11037, X86_VPMINUQZ128rmk = 11038, X86_VPMINUQZ128rmkz = 11039, X86_VPMINUQZ128rr = 11040, X86_VPMINUQZ128rrk = 11041, X86_VPMINUQZ128rrkz = 11042, X86_VPMINUQZ256rm = 11043, X86_VPMINUQZ256rmb = 11044, X86_VPMINUQZ256rmbk = 11045, X86_VPMINUQZ256rmbkz = 11046, X86_VPMINUQZ256rmk = 11047, X86_VPMINUQZ256rmkz = 11048, X86_VPMINUQZ256rr = 11049, X86_VPMINUQZ256rrk = 11050, X86_VPMINUQZ256rrkz = 11051, X86_VPMINUQZrm = 11052, X86_VPMINUQZrmb = 11053, X86_VPMINUQZrmbk = 11054, X86_VPMINUQZrmbkz = 11055, X86_VPMINUQZrmk = 11056, X86_VPMINUQZrmkz = 11057, X86_VPMINUQZrr = 11058, X86_VPMINUQZrrk = 11059, X86_VPMINUQZrrkz = 11060, X86_VPMINUWYrm = 11061, X86_VPMINUWYrr = 11062, X86_VPMINUWZ128rm = 11063, X86_VPMINUWZ128rmk = 11064, X86_VPMINUWZ128rmkz = 11065, X86_VPMINUWZ128rr = 11066, X86_VPMINUWZ128rrk = 11067, X86_VPMINUWZ128rrkz = 11068, X86_VPMINUWZ256rm = 11069, X86_VPMINUWZ256rmk = 11070, X86_VPMINUWZ256rmkz = 11071, X86_VPMINUWZ256rr = 11072, X86_VPMINUWZ256rrk = 11073, X86_VPMINUWZ256rrkz = 11074, X86_VPMINUWZrm = 11075, X86_VPMINUWZrmk = 11076, X86_VPMINUWZrmkz = 11077, X86_VPMINUWZrr = 11078, X86_VPMINUWZrrk = 11079, X86_VPMINUWZrrkz = 11080, X86_VPMINUWrm = 11081, X86_VPMINUWrr = 11082, X86_VPMOVB2MZ128rr = 11083, X86_VPMOVB2MZ256rr = 11084, X86_VPMOVB2MZrr = 11085, X86_VPMOVD2MZ128rr = 11086, X86_VPMOVD2MZ256rr = 11087, X86_VPMOVD2MZrr = 11088, X86_VPMOVDBZ128mr = 11089, X86_VPMOVDBZ128mrk = 11090, X86_VPMOVDBZ128rr = 11091, X86_VPMOVDBZ128rrk = 11092, X86_VPMOVDBZ128rrkz = 11093, X86_VPMOVDBZ256mr = 11094, X86_VPMOVDBZ256mrk = 11095, X86_VPMOVDBZ256rr = 11096, X86_VPMOVDBZ256rrk = 11097, X86_VPMOVDBZ256rrkz = 11098, X86_VPMOVDBZmr = 11099, X86_VPMOVDBZmrk = 11100, X86_VPMOVDBZrr = 11101, X86_VPMOVDBZrrk = 11102, X86_VPMOVDBZrrkz = 11103, X86_VPMOVDWZ128mr = 11104, X86_VPMOVDWZ128mrk = 11105, X86_VPMOVDWZ128rr = 11106, X86_VPMOVDWZ128rrk = 11107, X86_VPMOVDWZ128rrkz = 11108, X86_VPMOVDWZ256mr = 11109, X86_VPMOVDWZ256mrk = 11110, X86_VPMOVDWZ256rr = 11111, X86_VPMOVDWZ256rrk = 11112, X86_VPMOVDWZ256rrkz = 11113, X86_VPMOVDWZmr = 11114, X86_VPMOVDWZmrk = 11115, X86_VPMOVDWZrr = 11116, X86_VPMOVDWZrrk = 11117, X86_VPMOVDWZrrkz = 11118, X86_VPMOVM2BZ128rr = 11119, X86_VPMOVM2BZ256rr = 11120, X86_VPMOVM2BZrr = 11121, X86_VPMOVM2DZ128rr = 11122, X86_VPMOVM2DZ256rr = 11123, X86_VPMOVM2DZrr = 11124, X86_VPMOVM2QZ128rr = 11125, X86_VPMOVM2QZ256rr = 11126, X86_VPMOVM2QZrr = 11127, X86_VPMOVM2WZ128rr = 11128, X86_VPMOVM2WZ256rr = 11129, X86_VPMOVM2WZrr = 11130, X86_VPMOVMSKBYrr = 11131, X86_VPMOVMSKBrr = 11132, X86_VPMOVQ2MZ128rr = 11133, X86_VPMOVQ2MZ256rr = 11134, X86_VPMOVQ2MZrr = 11135, X86_VPMOVQBZ128mr = 11136, X86_VPMOVQBZ128mrk = 11137, X86_VPMOVQBZ128rr = 11138, X86_VPMOVQBZ128rrk = 11139, X86_VPMOVQBZ128rrkz = 11140, X86_VPMOVQBZ256mr = 11141, X86_VPMOVQBZ256mrk = 11142, X86_VPMOVQBZ256rr = 11143, X86_VPMOVQBZ256rrk = 11144, X86_VPMOVQBZ256rrkz = 11145, X86_VPMOVQBZmr = 11146, X86_VPMOVQBZmrk = 11147, X86_VPMOVQBZrr = 11148, X86_VPMOVQBZrrk = 11149, X86_VPMOVQBZrrkz = 11150, X86_VPMOVQDZ128mr = 11151, X86_VPMOVQDZ128mrk = 11152, X86_VPMOVQDZ128rr = 11153, X86_VPMOVQDZ128rrk = 11154, X86_VPMOVQDZ128rrkz = 11155, X86_VPMOVQDZ256mr = 11156, X86_VPMOVQDZ256mrk = 11157, X86_VPMOVQDZ256rr = 11158, X86_VPMOVQDZ256rrk = 11159, X86_VPMOVQDZ256rrkz = 11160, X86_VPMOVQDZmr = 11161, X86_VPMOVQDZmrk = 11162, X86_VPMOVQDZrr = 11163, X86_VPMOVQDZrrk = 11164, X86_VPMOVQDZrrkz = 11165, X86_VPMOVQWZ128mr = 11166, X86_VPMOVQWZ128mrk = 11167, X86_VPMOVQWZ128rr = 11168, X86_VPMOVQWZ128rrk = 11169, X86_VPMOVQWZ128rrkz = 11170, X86_VPMOVQWZ256mr = 11171, X86_VPMOVQWZ256mrk = 11172, X86_VPMOVQWZ256rr = 11173, X86_VPMOVQWZ256rrk = 11174, X86_VPMOVQWZ256rrkz = 11175, X86_VPMOVQWZmr = 11176, X86_VPMOVQWZmrk = 11177, X86_VPMOVQWZrr = 11178, X86_VPMOVQWZrrk = 11179, X86_VPMOVQWZrrkz = 11180, X86_VPMOVSDBZ128mr = 11181, X86_VPMOVSDBZ128mrk = 11182, X86_VPMOVSDBZ128rr = 11183, X86_VPMOVSDBZ128rrk = 11184, X86_VPMOVSDBZ128rrkz = 11185, X86_VPMOVSDBZ256mr = 11186, X86_VPMOVSDBZ256mrk = 11187, X86_VPMOVSDBZ256rr = 11188, X86_VPMOVSDBZ256rrk = 11189, X86_VPMOVSDBZ256rrkz = 11190, X86_VPMOVSDBZmr = 11191, X86_VPMOVSDBZmrk = 11192, X86_VPMOVSDBZrr = 11193, X86_VPMOVSDBZrrk = 11194, X86_VPMOVSDBZrrkz = 11195, X86_VPMOVSDWZ128mr = 11196, X86_VPMOVSDWZ128mrk = 11197, X86_VPMOVSDWZ128rr = 11198, X86_VPMOVSDWZ128rrk = 11199, X86_VPMOVSDWZ128rrkz = 11200, X86_VPMOVSDWZ256mr = 11201, X86_VPMOVSDWZ256mrk = 11202, X86_VPMOVSDWZ256rr = 11203, X86_VPMOVSDWZ256rrk = 11204, X86_VPMOVSDWZ256rrkz = 11205, X86_VPMOVSDWZmr = 11206, X86_VPMOVSDWZmrk = 11207, X86_VPMOVSDWZrr = 11208, X86_VPMOVSDWZrrk = 11209, X86_VPMOVSDWZrrkz = 11210, X86_VPMOVSQBZ128mr = 11211, X86_VPMOVSQBZ128mrk = 11212, X86_VPMOVSQBZ128rr = 11213, X86_VPMOVSQBZ128rrk = 11214, X86_VPMOVSQBZ128rrkz = 11215, X86_VPMOVSQBZ256mr = 11216, X86_VPMOVSQBZ256mrk = 11217, X86_VPMOVSQBZ256rr = 11218, X86_VPMOVSQBZ256rrk = 11219, X86_VPMOVSQBZ256rrkz = 11220, X86_VPMOVSQBZmr = 11221, X86_VPMOVSQBZmrk = 11222, X86_VPMOVSQBZrr = 11223, X86_VPMOVSQBZrrk = 11224, X86_VPMOVSQBZrrkz = 11225, X86_VPMOVSQDZ128mr = 11226, X86_VPMOVSQDZ128mrk = 11227, X86_VPMOVSQDZ128rr = 11228, X86_VPMOVSQDZ128rrk = 11229, X86_VPMOVSQDZ128rrkz = 11230, X86_VPMOVSQDZ256mr = 11231, X86_VPMOVSQDZ256mrk = 11232, X86_VPMOVSQDZ256rr = 11233, X86_VPMOVSQDZ256rrk = 11234, X86_VPMOVSQDZ256rrkz = 11235, X86_VPMOVSQDZmr = 11236, X86_VPMOVSQDZmrk = 11237, X86_VPMOVSQDZrr = 11238, X86_VPMOVSQDZrrk = 11239, X86_VPMOVSQDZrrkz = 11240, X86_VPMOVSQWZ128mr = 11241, X86_VPMOVSQWZ128mrk = 11242, X86_VPMOVSQWZ128rr = 11243, X86_VPMOVSQWZ128rrk = 11244, X86_VPMOVSQWZ128rrkz = 11245, X86_VPMOVSQWZ256mr = 11246, X86_VPMOVSQWZ256mrk = 11247, X86_VPMOVSQWZ256rr = 11248, X86_VPMOVSQWZ256rrk = 11249, X86_VPMOVSQWZ256rrkz = 11250, X86_VPMOVSQWZmr = 11251, X86_VPMOVSQWZmrk = 11252, X86_VPMOVSQWZrr = 11253, X86_VPMOVSQWZrrk = 11254, X86_VPMOVSQWZrrkz = 11255, X86_VPMOVSWBZ128mr = 11256, X86_VPMOVSWBZ128mrk = 11257, X86_VPMOVSWBZ128rr = 11258, X86_VPMOVSWBZ128rrk = 11259, X86_VPMOVSWBZ128rrkz = 11260, X86_VPMOVSWBZ256mr = 11261, X86_VPMOVSWBZ256mrk = 11262, X86_VPMOVSWBZ256rr = 11263, X86_VPMOVSWBZ256rrk = 11264, X86_VPMOVSWBZ256rrkz = 11265, X86_VPMOVSWBZmr = 11266, X86_VPMOVSWBZmrk = 11267, X86_VPMOVSWBZrr = 11268, X86_VPMOVSWBZrrk = 11269, X86_VPMOVSWBZrrkz = 11270, X86_VPMOVSXBDYrm = 11271, X86_VPMOVSXBDYrr = 11272, X86_VPMOVSXBDZ128rm = 11273, X86_VPMOVSXBDZ128rmk = 11274, X86_VPMOVSXBDZ128rmkz = 11275, X86_VPMOVSXBDZ128rr = 11276, X86_VPMOVSXBDZ128rrk = 11277, X86_VPMOVSXBDZ128rrkz = 11278, X86_VPMOVSXBDZ256rm = 11279, X86_VPMOVSXBDZ256rmk = 11280, X86_VPMOVSXBDZ256rmkz = 11281, X86_VPMOVSXBDZ256rr = 11282, X86_VPMOVSXBDZ256rrk = 11283, X86_VPMOVSXBDZ256rrkz = 11284, X86_VPMOVSXBDZrm = 11285, X86_VPMOVSXBDZrmk = 11286, X86_VPMOVSXBDZrmkz = 11287, X86_VPMOVSXBDZrr = 11288, X86_VPMOVSXBDZrrk = 11289, X86_VPMOVSXBDZrrkz = 11290, X86_VPMOVSXBDrm = 11291, X86_VPMOVSXBDrr = 11292, X86_VPMOVSXBQYrm = 11293, X86_VPMOVSXBQYrr = 11294, X86_VPMOVSXBQZ128rm = 11295, X86_VPMOVSXBQZ128rmk = 11296, X86_VPMOVSXBQZ128rmkz = 11297, X86_VPMOVSXBQZ128rr = 11298, X86_VPMOVSXBQZ128rrk = 11299, X86_VPMOVSXBQZ128rrkz = 11300, X86_VPMOVSXBQZ256rm = 11301, X86_VPMOVSXBQZ256rmk = 11302, X86_VPMOVSXBQZ256rmkz = 11303, X86_VPMOVSXBQZ256rr = 11304, X86_VPMOVSXBQZ256rrk = 11305, X86_VPMOVSXBQZ256rrkz = 11306, X86_VPMOVSXBQZrm = 11307, X86_VPMOVSXBQZrmk = 11308, X86_VPMOVSXBQZrmkz = 11309, X86_VPMOVSXBQZrr = 11310, X86_VPMOVSXBQZrrk = 11311, X86_VPMOVSXBQZrrkz = 11312, X86_VPMOVSXBQrm = 11313, X86_VPMOVSXBQrr = 11314, X86_VPMOVSXBWYrm = 11315, X86_VPMOVSXBWYrr = 11316, X86_VPMOVSXBWZ128rm = 11317, X86_VPMOVSXBWZ128rmk = 11318, X86_VPMOVSXBWZ128rmkz = 11319, X86_VPMOVSXBWZ128rr = 11320, X86_VPMOVSXBWZ128rrk = 11321, X86_VPMOVSXBWZ128rrkz = 11322, X86_VPMOVSXBWZ256rm = 11323, X86_VPMOVSXBWZ256rmk = 11324, X86_VPMOVSXBWZ256rmkz = 11325, X86_VPMOVSXBWZ256rr = 11326, X86_VPMOVSXBWZ256rrk = 11327, X86_VPMOVSXBWZ256rrkz = 11328, X86_VPMOVSXBWZrm = 11329, X86_VPMOVSXBWZrmk = 11330, X86_VPMOVSXBWZrmkz = 11331, X86_VPMOVSXBWZrr = 11332, X86_VPMOVSXBWZrrk = 11333, X86_VPMOVSXBWZrrkz = 11334, X86_VPMOVSXBWrm = 11335, X86_VPMOVSXBWrr = 11336, X86_VPMOVSXDQYrm = 11337, X86_VPMOVSXDQYrr = 11338, X86_VPMOVSXDQZ128rm = 11339, X86_VPMOVSXDQZ128rmk = 11340, X86_VPMOVSXDQZ128rmkz = 11341, X86_VPMOVSXDQZ128rr = 11342, X86_VPMOVSXDQZ128rrk = 11343, X86_VPMOVSXDQZ128rrkz = 11344, X86_VPMOVSXDQZ256rm = 11345, X86_VPMOVSXDQZ256rmk = 11346, X86_VPMOVSXDQZ256rmkz = 11347, X86_VPMOVSXDQZ256rr = 11348, X86_VPMOVSXDQZ256rrk = 11349, X86_VPMOVSXDQZ256rrkz = 11350, X86_VPMOVSXDQZrm = 11351, X86_VPMOVSXDQZrmk = 11352, X86_VPMOVSXDQZrmkz = 11353, X86_VPMOVSXDQZrr = 11354, X86_VPMOVSXDQZrrk = 11355, X86_VPMOVSXDQZrrkz = 11356, X86_VPMOVSXDQrm = 11357, X86_VPMOVSXDQrr = 11358, X86_VPMOVSXWDYrm = 11359, X86_VPMOVSXWDYrr = 11360, X86_VPMOVSXWDZ128rm = 11361, X86_VPMOVSXWDZ128rmk = 11362, X86_VPMOVSXWDZ128rmkz = 11363, X86_VPMOVSXWDZ128rr = 11364, X86_VPMOVSXWDZ128rrk = 11365, X86_VPMOVSXWDZ128rrkz = 11366, X86_VPMOVSXWDZ256rm = 11367, X86_VPMOVSXWDZ256rmk = 11368, X86_VPMOVSXWDZ256rmkz = 11369, X86_VPMOVSXWDZ256rr = 11370, X86_VPMOVSXWDZ256rrk = 11371, X86_VPMOVSXWDZ256rrkz = 11372, X86_VPMOVSXWDZrm = 11373, X86_VPMOVSXWDZrmk = 11374, X86_VPMOVSXWDZrmkz = 11375, X86_VPMOVSXWDZrr = 11376, X86_VPMOVSXWDZrrk = 11377, X86_VPMOVSXWDZrrkz = 11378, X86_VPMOVSXWDrm = 11379, X86_VPMOVSXWDrr = 11380, X86_VPMOVSXWQYrm = 11381, X86_VPMOVSXWQYrr = 11382, X86_VPMOVSXWQZ128rm = 11383, X86_VPMOVSXWQZ128rmk = 11384, X86_VPMOVSXWQZ128rmkz = 11385, X86_VPMOVSXWQZ128rr = 11386, X86_VPMOVSXWQZ128rrk = 11387, X86_VPMOVSXWQZ128rrkz = 11388, X86_VPMOVSXWQZ256rm = 11389, X86_VPMOVSXWQZ256rmk = 11390, X86_VPMOVSXWQZ256rmkz = 11391, X86_VPMOVSXWQZ256rr = 11392, X86_VPMOVSXWQZ256rrk = 11393, X86_VPMOVSXWQZ256rrkz = 11394, X86_VPMOVSXWQZrm = 11395, X86_VPMOVSXWQZrmk = 11396, X86_VPMOVSXWQZrmkz = 11397, X86_VPMOVSXWQZrr = 11398, X86_VPMOVSXWQZrrk = 11399, X86_VPMOVSXWQZrrkz = 11400, X86_VPMOVSXWQrm = 11401, X86_VPMOVSXWQrr = 11402, X86_VPMOVUSDBZ128mr = 11403, X86_VPMOVUSDBZ128mrk = 11404, X86_VPMOVUSDBZ128rr = 11405, X86_VPMOVUSDBZ128rrk = 11406, X86_VPMOVUSDBZ128rrkz = 11407, X86_VPMOVUSDBZ256mr = 11408, X86_VPMOVUSDBZ256mrk = 11409, X86_VPMOVUSDBZ256rr = 11410, X86_VPMOVUSDBZ256rrk = 11411, X86_VPMOVUSDBZ256rrkz = 11412, X86_VPMOVUSDBZmr = 11413, X86_VPMOVUSDBZmrk = 11414, X86_VPMOVUSDBZrr = 11415, X86_VPMOVUSDBZrrk = 11416, X86_VPMOVUSDBZrrkz = 11417, X86_VPMOVUSDWZ128mr = 11418, X86_VPMOVUSDWZ128mrk = 11419, X86_VPMOVUSDWZ128rr = 11420, X86_VPMOVUSDWZ128rrk = 11421, X86_VPMOVUSDWZ128rrkz = 11422, X86_VPMOVUSDWZ256mr = 11423, X86_VPMOVUSDWZ256mrk = 11424, X86_VPMOVUSDWZ256rr = 11425, X86_VPMOVUSDWZ256rrk = 11426, X86_VPMOVUSDWZ256rrkz = 11427, X86_VPMOVUSDWZmr = 11428, X86_VPMOVUSDWZmrk = 11429, X86_VPMOVUSDWZrr = 11430, X86_VPMOVUSDWZrrk = 11431, X86_VPMOVUSDWZrrkz = 11432, X86_VPMOVUSQBZ128mr = 11433, X86_VPMOVUSQBZ128mrk = 11434, X86_VPMOVUSQBZ128rr = 11435, X86_VPMOVUSQBZ128rrk = 11436, X86_VPMOVUSQBZ128rrkz = 11437, X86_VPMOVUSQBZ256mr = 11438, X86_VPMOVUSQBZ256mrk = 11439, X86_VPMOVUSQBZ256rr = 11440, X86_VPMOVUSQBZ256rrk = 11441, X86_VPMOVUSQBZ256rrkz = 11442, X86_VPMOVUSQBZmr = 11443, X86_VPMOVUSQBZmrk = 11444, X86_VPMOVUSQBZrr = 11445, X86_VPMOVUSQBZrrk = 11446, X86_VPMOVUSQBZrrkz = 11447, X86_VPMOVUSQDZ128mr = 11448, X86_VPMOVUSQDZ128mrk = 11449, X86_VPMOVUSQDZ128rr = 11450, X86_VPMOVUSQDZ128rrk = 11451, X86_VPMOVUSQDZ128rrkz = 11452, X86_VPMOVUSQDZ256mr = 11453, X86_VPMOVUSQDZ256mrk = 11454, X86_VPMOVUSQDZ256rr = 11455, X86_VPMOVUSQDZ256rrk = 11456, X86_VPMOVUSQDZ256rrkz = 11457, X86_VPMOVUSQDZmr = 11458, X86_VPMOVUSQDZmrk = 11459, X86_VPMOVUSQDZrr = 11460, X86_VPMOVUSQDZrrk = 11461, X86_VPMOVUSQDZrrkz = 11462, X86_VPMOVUSQWZ128mr = 11463, X86_VPMOVUSQWZ128mrk = 11464, X86_VPMOVUSQWZ128rr = 11465, X86_VPMOVUSQWZ128rrk = 11466, X86_VPMOVUSQWZ128rrkz = 11467, X86_VPMOVUSQWZ256mr = 11468, X86_VPMOVUSQWZ256mrk = 11469, X86_VPMOVUSQWZ256rr = 11470, X86_VPMOVUSQWZ256rrk = 11471, X86_VPMOVUSQWZ256rrkz = 11472, X86_VPMOVUSQWZmr = 11473, X86_VPMOVUSQWZmrk = 11474, X86_VPMOVUSQWZrr = 11475, X86_VPMOVUSQWZrrk = 11476, X86_VPMOVUSQWZrrkz = 11477, X86_VPMOVUSWBZ128mr = 11478, X86_VPMOVUSWBZ128mrk = 11479, X86_VPMOVUSWBZ128rr = 11480, X86_VPMOVUSWBZ128rrk = 11481, X86_VPMOVUSWBZ128rrkz = 11482, X86_VPMOVUSWBZ256mr = 11483, X86_VPMOVUSWBZ256mrk = 11484, X86_VPMOVUSWBZ256rr = 11485, X86_VPMOVUSWBZ256rrk = 11486, X86_VPMOVUSWBZ256rrkz = 11487, X86_VPMOVUSWBZmr = 11488, X86_VPMOVUSWBZmrk = 11489, X86_VPMOVUSWBZrr = 11490, X86_VPMOVUSWBZrrk = 11491, X86_VPMOVUSWBZrrkz = 11492, X86_VPMOVW2MZ128rr = 11493, X86_VPMOVW2MZ256rr = 11494, X86_VPMOVW2MZrr = 11495, X86_VPMOVWBZ128mr = 11496, X86_VPMOVWBZ128mrk = 11497, X86_VPMOVWBZ128rr = 11498, X86_VPMOVWBZ128rrk = 11499, X86_VPMOVWBZ128rrkz = 11500, X86_VPMOVWBZ256mr = 11501, X86_VPMOVWBZ256mrk = 11502, X86_VPMOVWBZ256rr = 11503, X86_VPMOVWBZ256rrk = 11504, X86_VPMOVWBZ256rrkz = 11505, X86_VPMOVWBZmr = 11506, X86_VPMOVWBZmrk = 11507, X86_VPMOVWBZrr = 11508, X86_VPMOVWBZrrk = 11509, X86_VPMOVWBZrrkz = 11510, X86_VPMOVZXBDYrm = 11511, X86_VPMOVZXBDYrr = 11512, X86_VPMOVZXBDZ128rm = 11513, X86_VPMOVZXBDZ128rmk = 11514, X86_VPMOVZXBDZ128rmkz = 11515, X86_VPMOVZXBDZ128rr = 11516, X86_VPMOVZXBDZ128rrk = 11517, X86_VPMOVZXBDZ128rrkz = 11518, X86_VPMOVZXBDZ256rm = 11519, X86_VPMOVZXBDZ256rmk = 11520, X86_VPMOVZXBDZ256rmkz = 11521, X86_VPMOVZXBDZ256rr = 11522, X86_VPMOVZXBDZ256rrk = 11523, X86_VPMOVZXBDZ256rrkz = 11524, X86_VPMOVZXBDZrm = 11525, X86_VPMOVZXBDZrmk = 11526, X86_VPMOVZXBDZrmkz = 11527, X86_VPMOVZXBDZrr = 11528, X86_VPMOVZXBDZrrk = 11529, X86_VPMOVZXBDZrrkz = 11530, X86_VPMOVZXBDrm = 11531, X86_VPMOVZXBDrr = 11532, X86_VPMOVZXBQYrm = 11533, X86_VPMOVZXBQYrr = 11534, X86_VPMOVZXBQZ128rm = 11535, X86_VPMOVZXBQZ128rmk = 11536, X86_VPMOVZXBQZ128rmkz = 11537, X86_VPMOVZXBQZ128rr = 11538, X86_VPMOVZXBQZ128rrk = 11539, X86_VPMOVZXBQZ128rrkz = 11540, X86_VPMOVZXBQZ256rm = 11541, X86_VPMOVZXBQZ256rmk = 11542, X86_VPMOVZXBQZ256rmkz = 11543, X86_VPMOVZXBQZ256rr = 11544, X86_VPMOVZXBQZ256rrk = 11545, X86_VPMOVZXBQZ256rrkz = 11546, X86_VPMOVZXBQZrm = 11547, X86_VPMOVZXBQZrmk = 11548, X86_VPMOVZXBQZrmkz = 11549, X86_VPMOVZXBQZrr = 11550, X86_VPMOVZXBQZrrk = 11551, X86_VPMOVZXBQZrrkz = 11552, X86_VPMOVZXBQrm = 11553, X86_VPMOVZXBQrr = 11554, X86_VPMOVZXBWYrm = 11555, X86_VPMOVZXBWYrr = 11556, X86_VPMOVZXBWZ128rm = 11557, X86_VPMOVZXBWZ128rmk = 11558, X86_VPMOVZXBWZ128rmkz = 11559, X86_VPMOVZXBWZ128rr = 11560, X86_VPMOVZXBWZ128rrk = 11561, X86_VPMOVZXBWZ128rrkz = 11562, X86_VPMOVZXBWZ256rm = 11563, X86_VPMOVZXBWZ256rmk = 11564, X86_VPMOVZXBWZ256rmkz = 11565, X86_VPMOVZXBWZ256rr = 11566, X86_VPMOVZXBWZ256rrk = 11567, X86_VPMOVZXBWZ256rrkz = 11568, X86_VPMOVZXBWZrm = 11569, X86_VPMOVZXBWZrmk = 11570, X86_VPMOVZXBWZrmkz = 11571, X86_VPMOVZXBWZrr = 11572, X86_VPMOVZXBWZrrk = 11573, X86_VPMOVZXBWZrrkz = 11574, X86_VPMOVZXBWrm = 11575, X86_VPMOVZXBWrr = 11576, X86_VPMOVZXDQYrm = 11577, X86_VPMOVZXDQYrr = 11578, X86_VPMOVZXDQZ128rm = 11579, X86_VPMOVZXDQZ128rmk = 11580, X86_VPMOVZXDQZ128rmkz = 11581, X86_VPMOVZXDQZ128rr = 11582, X86_VPMOVZXDQZ128rrk = 11583, X86_VPMOVZXDQZ128rrkz = 11584, X86_VPMOVZXDQZ256rm = 11585, X86_VPMOVZXDQZ256rmk = 11586, X86_VPMOVZXDQZ256rmkz = 11587, X86_VPMOVZXDQZ256rr = 11588, X86_VPMOVZXDQZ256rrk = 11589, X86_VPMOVZXDQZ256rrkz = 11590, X86_VPMOVZXDQZrm = 11591, X86_VPMOVZXDQZrmk = 11592, X86_VPMOVZXDQZrmkz = 11593, X86_VPMOVZXDQZrr = 11594, X86_VPMOVZXDQZrrk = 11595, X86_VPMOVZXDQZrrkz = 11596, X86_VPMOVZXDQrm = 11597, X86_VPMOVZXDQrr = 11598, X86_VPMOVZXWDYrm = 11599, X86_VPMOVZXWDYrr = 11600, X86_VPMOVZXWDZ128rm = 11601, X86_VPMOVZXWDZ128rmk = 11602, X86_VPMOVZXWDZ128rmkz = 11603, X86_VPMOVZXWDZ128rr = 11604, X86_VPMOVZXWDZ128rrk = 11605, X86_VPMOVZXWDZ128rrkz = 11606, X86_VPMOVZXWDZ256rm = 11607, X86_VPMOVZXWDZ256rmk = 11608, X86_VPMOVZXWDZ256rmkz = 11609, X86_VPMOVZXWDZ256rr = 11610, X86_VPMOVZXWDZ256rrk = 11611, X86_VPMOVZXWDZ256rrkz = 11612, X86_VPMOVZXWDZrm = 11613, X86_VPMOVZXWDZrmk = 11614, X86_VPMOVZXWDZrmkz = 11615, X86_VPMOVZXWDZrr = 11616, X86_VPMOVZXWDZrrk = 11617, X86_VPMOVZXWDZrrkz = 11618, X86_VPMOVZXWDrm = 11619, X86_VPMOVZXWDrr = 11620, X86_VPMOVZXWQYrm = 11621, X86_VPMOVZXWQYrr = 11622, X86_VPMOVZXWQZ128rm = 11623, X86_VPMOVZXWQZ128rmk = 11624, X86_VPMOVZXWQZ128rmkz = 11625, X86_VPMOVZXWQZ128rr = 11626, X86_VPMOVZXWQZ128rrk = 11627, X86_VPMOVZXWQZ128rrkz = 11628, X86_VPMOVZXWQZ256rm = 11629, X86_VPMOVZXWQZ256rmk = 11630, X86_VPMOVZXWQZ256rmkz = 11631, X86_VPMOVZXWQZ256rr = 11632, X86_VPMOVZXWQZ256rrk = 11633, X86_VPMOVZXWQZ256rrkz = 11634, X86_VPMOVZXWQZrm = 11635, X86_VPMOVZXWQZrmk = 11636, X86_VPMOVZXWQZrmkz = 11637, X86_VPMOVZXWQZrr = 11638, X86_VPMOVZXWQZrrk = 11639, X86_VPMOVZXWQZrrkz = 11640, X86_VPMOVZXWQrm = 11641, X86_VPMOVZXWQrr = 11642, X86_VPMULDQYrm = 11643, X86_VPMULDQYrr = 11644, X86_VPMULDQZ128rm = 11645, X86_VPMULDQZ128rmb = 11646, X86_VPMULDQZ128rmbk = 11647, X86_VPMULDQZ128rmbkz = 11648, X86_VPMULDQZ128rmk = 11649, X86_VPMULDQZ128rmkz = 11650, X86_VPMULDQZ128rr = 11651, X86_VPMULDQZ128rrk = 11652, X86_VPMULDQZ128rrkz = 11653, X86_VPMULDQZ256rm = 11654, X86_VPMULDQZ256rmb = 11655, X86_VPMULDQZ256rmbk = 11656, X86_VPMULDQZ256rmbkz = 11657, X86_VPMULDQZ256rmk = 11658, X86_VPMULDQZ256rmkz = 11659, X86_VPMULDQZ256rr = 11660, X86_VPMULDQZ256rrk = 11661, X86_VPMULDQZ256rrkz = 11662, X86_VPMULDQZrm = 11663, X86_VPMULDQZrmb = 11664, X86_VPMULDQZrmbk = 11665, X86_VPMULDQZrmbkz = 11666, X86_VPMULDQZrmk = 11667, X86_VPMULDQZrmkz = 11668, X86_VPMULDQZrr = 11669, X86_VPMULDQZrrk = 11670, X86_VPMULDQZrrkz = 11671, X86_VPMULDQrm = 11672, X86_VPMULDQrr = 11673, X86_VPMULHRSWYrm = 11674, X86_VPMULHRSWYrr = 11675, X86_VPMULHRSWZ128rm = 11676, X86_VPMULHRSWZ128rmk = 11677, X86_VPMULHRSWZ128rmkz = 11678, X86_VPMULHRSWZ128rr = 11679, X86_VPMULHRSWZ128rrk = 11680, X86_VPMULHRSWZ128rrkz = 11681, X86_VPMULHRSWZ256rm = 11682, X86_VPMULHRSWZ256rmk = 11683, X86_VPMULHRSWZ256rmkz = 11684, X86_VPMULHRSWZ256rr = 11685, X86_VPMULHRSWZ256rrk = 11686, X86_VPMULHRSWZ256rrkz = 11687, X86_VPMULHRSWZrm = 11688, X86_VPMULHRSWZrmk = 11689, X86_VPMULHRSWZrmkz = 11690, X86_VPMULHRSWZrr = 11691, X86_VPMULHRSWZrrk = 11692, X86_VPMULHRSWZrrkz = 11693, X86_VPMULHRSWrm = 11694, X86_VPMULHRSWrr = 11695, X86_VPMULHUWYrm = 11696, X86_VPMULHUWYrr = 11697, X86_VPMULHUWZ128rm = 11698, X86_VPMULHUWZ128rmk = 11699, X86_VPMULHUWZ128rmkz = 11700, X86_VPMULHUWZ128rr = 11701, X86_VPMULHUWZ128rrk = 11702, X86_VPMULHUWZ128rrkz = 11703, X86_VPMULHUWZ256rm = 11704, X86_VPMULHUWZ256rmk = 11705, X86_VPMULHUWZ256rmkz = 11706, X86_VPMULHUWZ256rr = 11707, X86_VPMULHUWZ256rrk = 11708, X86_VPMULHUWZ256rrkz = 11709, X86_VPMULHUWZrm = 11710, X86_VPMULHUWZrmk = 11711, X86_VPMULHUWZrmkz = 11712, X86_VPMULHUWZrr = 11713, X86_VPMULHUWZrrk = 11714, X86_VPMULHUWZrrkz = 11715, X86_VPMULHUWrm = 11716, X86_VPMULHUWrr = 11717, X86_VPMULHWYrm = 11718, X86_VPMULHWYrr = 11719, X86_VPMULHWZ128rm = 11720, X86_VPMULHWZ128rmk = 11721, X86_VPMULHWZ128rmkz = 11722, X86_VPMULHWZ128rr = 11723, X86_VPMULHWZ128rrk = 11724, X86_VPMULHWZ128rrkz = 11725, X86_VPMULHWZ256rm = 11726, X86_VPMULHWZ256rmk = 11727, X86_VPMULHWZ256rmkz = 11728, X86_VPMULHWZ256rr = 11729, X86_VPMULHWZ256rrk = 11730, X86_VPMULHWZ256rrkz = 11731, X86_VPMULHWZrm = 11732, X86_VPMULHWZrmk = 11733, X86_VPMULHWZrmkz = 11734, X86_VPMULHWZrr = 11735, X86_VPMULHWZrrk = 11736, X86_VPMULHWZrrkz = 11737, X86_VPMULHWrm = 11738, X86_VPMULHWrr = 11739, X86_VPMULLDYrm = 11740, X86_VPMULLDYrr = 11741, X86_VPMULLDZ128rm = 11742, X86_VPMULLDZ128rmb = 11743, X86_VPMULLDZ128rmbk = 11744, X86_VPMULLDZ128rmbkz = 11745, X86_VPMULLDZ128rmk = 11746, X86_VPMULLDZ128rmkz = 11747, X86_VPMULLDZ128rr = 11748, X86_VPMULLDZ128rrk = 11749, X86_VPMULLDZ128rrkz = 11750, X86_VPMULLDZ256rm = 11751, X86_VPMULLDZ256rmb = 11752, X86_VPMULLDZ256rmbk = 11753, X86_VPMULLDZ256rmbkz = 11754, X86_VPMULLDZ256rmk = 11755, X86_VPMULLDZ256rmkz = 11756, X86_VPMULLDZ256rr = 11757, X86_VPMULLDZ256rrk = 11758, X86_VPMULLDZ256rrkz = 11759, X86_VPMULLDZrm = 11760, X86_VPMULLDZrmb = 11761, X86_VPMULLDZrmbk = 11762, X86_VPMULLDZrmbkz = 11763, X86_VPMULLDZrmk = 11764, X86_VPMULLDZrmkz = 11765, X86_VPMULLDZrr = 11766, X86_VPMULLDZrrk = 11767, X86_VPMULLDZrrkz = 11768, X86_VPMULLDrm = 11769, X86_VPMULLDrr = 11770, X86_VPMULLQZ128rm = 11771, X86_VPMULLQZ128rmb = 11772, X86_VPMULLQZ128rmbk = 11773, X86_VPMULLQZ128rmbkz = 11774, X86_VPMULLQZ128rmk = 11775, X86_VPMULLQZ128rmkz = 11776, X86_VPMULLQZ128rr = 11777, X86_VPMULLQZ128rrk = 11778, X86_VPMULLQZ128rrkz = 11779, X86_VPMULLQZ256rm = 11780, X86_VPMULLQZ256rmb = 11781, X86_VPMULLQZ256rmbk = 11782, X86_VPMULLQZ256rmbkz = 11783, X86_VPMULLQZ256rmk = 11784, X86_VPMULLQZ256rmkz = 11785, X86_VPMULLQZ256rr = 11786, X86_VPMULLQZ256rrk = 11787, X86_VPMULLQZ256rrkz = 11788, X86_VPMULLQZrm = 11789, X86_VPMULLQZrmb = 11790, X86_VPMULLQZrmbk = 11791, X86_VPMULLQZrmbkz = 11792, X86_VPMULLQZrmk = 11793, X86_VPMULLQZrmkz = 11794, X86_VPMULLQZrr = 11795, X86_VPMULLQZrrk = 11796, X86_VPMULLQZrrkz = 11797, X86_VPMULLWYrm = 11798, X86_VPMULLWYrr = 11799, X86_VPMULLWZ128rm = 11800, X86_VPMULLWZ128rmk = 11801, X86_VPMULLWZ128rmkz = 11802, X86_VPMULLWZ128rr = 11803, X86_VPMULLWZ128rrk = 11804, X86_VPMULLWZ128rrkz = 11805, X86_VPMULLWZ256rm = 11806, X86_VPMULLWZ256rmk = 11807, X86_VPMULLWZ256rmkz = 11808, X86_VPMULLWZ256rr = 11809, X86_VPMULLWZ256rrk = 11810, X86_VPMULLWZ256rrkz = 11811, X86_VPMULLWZrm = 11812, X86_VPMULLWZrmk = 11813, X86_VPMULLWZrmkz = 11814, X86_VPMULLWZrr = 11815, X86_VPMULLWZrrk = 11816, X86_VPMULLWZrrkz = 11817, X86_VPMULLWrm = 11818, X86_VPMULLWrr = 11819, X86_VPMULTISHIFTQBZ128rm = 11820, X86_VPMULTISHIFTQBZ128rmb = 11821, X86_VPMULTISHIFTQBZ128rmbk = 11822, X86_VPMULTISHIFTQBZ128rmbkz = 11823, X86_VPMULTISHIFTQBZ128rmk = 11824, X86_VPMULTISHIFTQBZ128rmkz = 11825, X86_VPMULTISHIFTQBZ128rr = 11826, X86_VPMULTISHIFTQBZ128rrk = 11827, X86_VPMULTISHIFTQBZ128rrkz = 11828, X86_VPMULTISHIFTQBZ256rm = 11829, X86_VPMULTISHIFTQBZ256rmb = 11830, X86_VPMULTISHIFTQBZ256rmbk = 11831, X86_VPMULTISHIFTQBZ256rmbkz = 11832, X86_VPMULTISHIFTQBZ256rmk = 11833, X86_VPMULTISHIFTQBZ256rmkz = 11834, X86_VPMULTISHIFTQBZ256rr = 11835, X86_VPMULTISHIFTQBZ256rrk = 11836, X86_VPMULTISHIFTQBZ256rrkz = 11837, X86_VPMULTISHIFTQBZrm = 11838, X86_VPMULTISHIFTQBZrmb = 11839, X86_VPMULTISHIFTQBZrmbk = 11840, X86_VPMULTISHIFTQBZrmbkz = 11841, X86_VPMULTISHIFTQBZrmk = 11842, X86_VPMULTISHIFTQBZrmkz = 11843, X86_VPMULTISHIFTQBZrr = 11844, X86_VPMULTISHIFTQBZrrk = 11845, X86_VPMULTISHIFTQBZrrkz = 11846, X86_VPMULUDQYrm = 11847, X86_VPMULUDQYrr = 11848, X86_VPMULUDQZ128rm = 11849, X86_VPMULUDQZ128rmb = 11850, X86_VPMULUDQZ128rmbk = 11851, X86_VPMULUDQZ128rmbkz = 11852, X86_VPMULUDQZ128rmk = 11853, X86_VPMULUDQZ128rmkz = 11854, X86_VPMULUDQZ128rr = 11855, X86_VPMULUDQZ128rrk = 11856, X86_VPMULUDQZ128rrkz = 11857, X86_VPMULUDQZ256rm = 11858, X86_VPMULUDQZ256rmb = 11859, X86_VPMULUDQZ256rmbk = 11860, X86_VPMULUDQZ256rmbkz = 11861, X86_VPMULUDQZ256rmk = 11862, X86_VPMULUDQZ256rmkz = 11863, X86_VPMULUDQZ256rr = 11864, X86_VPMULUDQZ256rrk = 11865, X86_VPMULUDQZ256rrkz = 11866, X86_VPMULUDQZrm = 11867, X86_VPMULUDQZrmb = 11868, X86_VPMULUDQZrmbk = 11869, X86_VPMULUDQZrmbkz = 11870, X86_VPMULUDQZrmk = 11871, X86_VPMULUDQZrmkz = 11872, X86_VPMULUDQZrr = 11873, X86_VPMULUDQZrrk = 11874, X86_VPMULUDQZrrkz = 11875, X86_VPMULUDQrm = 11876, X86_VPMULUDQrr = 11877, X86_VPOPCNTBZ128rm = 11878, X86_VPOPCNTBZ128rmk = 11879, X86_VPOPCNTBZ128rmkz = 11880, X86_VPOPCNTBZ128rr = 11881, X86_VPOPCNTBZ128rrk = 11882, X86_VPOPCNTBZ128rrkz = 11883, X86_VPOPCNTBZ256rm = 11884, X86_VPOPCNTBZ256rmk = 11885, X86_VPOPCNTBZ256rmkz = 11886, X86_VPOPCNTBZ256rr = 11887, X86_VPOPCNTBZ256rrk = 11888, X86_VPOPCNTBZ256rrkz = 11889, X86_VPOPCNTBZrm = 11890, X86_VPOPCNTBZrmk = 11891, X86_VPOPCNTBZrmkz = 11892, X86_VPOPCNTBZrr = 11893, X86_VPOPCNTBZrrk = 11894, X86_VPOPCNTBZrrkz = 11895, X86_VPOPCNTDZ128rm = 11896, X86_VPOPCNTDZ128rmb = 11897, X86_VPOPCNTDZ128rmbk = 11898, X86_VPOPCNTDZ128rmbkz = 11899, X86_VPOPCNTDZ128rmk = 11900, X86_VPOPCNTDZ128rmkz = 11901, X86_VPOPCNTDZ128rr = 11902, X86_VPOPCNTDZ128rrk = 11903, X86_VPOPCNTDZ128rrkz = 11904, X86_VPOPCNTDZ256rm = 11905, X86_VPOPCNTDZ256rmb = 11906, X86_VPOPCNTDZ256rmbk = 11907, X86_VPOPCNTDZ256rmbkz = 11908, X86_VPOPCNTDZ256rmk = 11909, X86_VPOPCNTDZ256rmkz = 11910, X86_VPOPCNTDZ256rr = 11911, X86_VPOPCNTDZ256rrk = 11912, X86_VPOPCNTDZ256rrkz = 11913, X86_VPOPCNTDZrm = 11914, X86_VPOPCNTDZrmb = 11915, X86_VPOPCNTDZrmbk = 11916, X86_VPOPCNTDZrmbkz = 11917, X86_VPOPCNTDZrmk = 11918, X86_VPOPCNTDZrmkz = 11919, X86_VPOPCNTDZrr = 11920, X86_VPOPCNTDZrrk = 11921, X86_VPOPCNTDZrrkz = 11922, X86_VPOPCNTQZ128rm = 11923, X86_VPOPCNTQZ128rmb = 11924, X86_VPOPCNTQZ128rmbk = 11925, X86_VPOPCNTQZ128rmbkz = 11926, X86_VPOPCNTQZ128rmk = 11927, X86_VPOPCNTQZ128rmkz = 11928, X86_VPOPCNTQZ128rr = 11929, X86_VPOPCNTQZ128rrk = 11930, X86_VPOPCNTQZ128rrkz = 11931, X86_VPOPCNTQZ256rm = 11932, X86_VPOPCNTQZ256rmb = 11933, X86_VPOPCNTQZ256rmbk = 11934, X86_VPOPCNTQZ256rmbkz = 11935, X86_VPOPCNTQZ256rmk = 11936, X86_VPOPCNTQZ256rmkz = 11937, X86_VPOPCNTQZ256rr = 11938, X86_VPOPCNTQZ256rrk = 11939, X86_VPOPCNTQZ256rrkz = 11940, X86_VPOPCNTQZrm = 11941, X86_VPOPCNTQZrmb = 11942, X86_VPOPCNTQZrmbk = 11943, X86_VPOPCNTQZrmbkz = 11944, X86_VPOPCNTQZrmk = 11945, X86_VPOPCNTQZrmkz = 11946, X86_VPOPCNTQZrr = 11947, X86_VPOPCNTQZrrk = 11948, X86_VPOPCNTQZrrkz = 11949, X86_VPOPCNTWZ128rm = 11950, X86_VPOPCNTWZ128rmk = 11951, X86_VPOPCNTWZ128rmkz = 11952, X86_VPOPCNTWZ128rr = 11953, X86_VPOPCNTWZ128rrk = 11954, X86_VPOPCNTWZ128rrkz = 11955, X86_VPOPCNTWZ256rm = 11956, X86_VPOPCNTWZ256rmk = 11957, X86_VPOPCNTWZ256rmkz = 11958, X86_VPOPCNTWZ256rr = 11959, X86_VPOPCNTWZ256rrk = 11960, X86_VPOPCNTWZ256rrkz = 11961, X86_VPOPCNTWZrm = 11962, X86_VPOPCNTWZrmk = 11963, X86_VPOPCNTWZrmkz = 11964, X86_VPOPCNTWZrr = 11965, X86_VPOPCNTWZrrk = 11966, X86_VPOPCNTWZrrkz = 11967, X86_VPORDZ128rm = 11968, X86_VPORDZ128rmb = 11969, X86_VPORDZ128rmbk = 11970, X86_VPORDZ128rmbkz = 11971, X86_VPORDZ128rmk = 11972, X86_VPORDZ128rmkz = 11973, X86_VPORDZ128rr = 11974, X86_VPORDZ128rrk = 11975, X86_VPORDZ128rrkz = 11976, X86_VPORDZ256rm = 11977, X86_VPORDZ256rmb = 11978, X86_VPORDZ256rmbk = 11979, X86_VPORDZ256rmbkz = 11980, X86_VPORDZ256rmk = 11981, X86_VPORDZ256rmkz = 11982, X86_VPORDZ256rr = 11983, X86_VPORDZ256rrk = 11984, X86_VPORDZ256rrkz = 11985, X86_VPORDZrm = 11986, X86_VPORDZrmb = 11987, X86_VPORDZrmbk = 11988, X86_VPORDZrmbkz = 11989, X86_VPORDZrmk = 11990, X86_VPORDZrmkz = 11991, X86_VPORDZrr = 11992, X86_VPORDZrrk = 11993, X86_VPORDZrrkz = 11994, X86_VPORQZ128rm = 11995, X86_VPORQZ128rmb = 11996, X86_VPORQZ128rmbk = 11997, X86_VPORQZ128rmbkz = 11998, X86_VPORQZ128rmk = 11999, X86_VPORQZ128rmkz = 12000, X86_VPORQZ128rr = 12001, X86_VPORQZ128rrk = 12002, X86_VPORQZ128rrkz = 12003, X86_VPORQZ256rm = 12004, X86_VPORQZ256rmb = 12005, X86_VPORQZ256rmbk = 12006, X86_VPORQZ256rmbkz = 12007, X86_VPORQZ256rmk = 12008, X86_VPORQZ256rmkz = 12009, X86_VPORQZ256rr = 12010, X86_VPORQZ256rrk = 12011, X86_VPORQZ256rrkz = 12012, X86_VPORQZrm = 12013, X86_VPORQZrmb = 12014, X86_VPORQZrmbk = 12015, X86_VPORQZrmbkz = 12016, X86_VPORQZrmk = 12017, X86_VPORQZrmkz = 12018, X86_VPORQZrr = 12019, X86_VPORQZrrk = 12020, X86_VPORQZrrkz = 12021, X86_VPORYrm = 12022, X86_VPORYrr = 12023, X86_VPORrm = 12024, X86_VPORrr = 12025, X86_VPPERMrmr = 12026, X86_VPPERMrrm = 12027, X86_VPPERMrrr = 12028, X86_VPPERMrrr_REV = 12029, X86_VPROLDZ128mbi = 12030, X86_VPROLDZ128mbik = 12031, X86_VPROLDZ128mbikz = 12032, X86_VPROLDZ128mi = 12033, X86_VPROLDZ128mik = 12034, X86_VPROLDZ128mikz = 12035, X86_VPROLDZ128ri = 12036, X86_VPROLDZ128rik = 12037, X86_VPROLDZ128rikz = 12038, X86_VPROLDZ256mbi = 12039, X86_VPROLDZ256mbik = 12040, X86_VPROLDZ256mbikz = 12041, X86_VPROLDZ256mi = 12042, X86_VPROLDZ256mik = 12043, X86_VPROLDZ256mikz = 12044, X86_VPROLDZ256ri = 12045, X86_VPROLDZ256rik = 12046, X86_VPROLDZ256rikz = 12047, X86_VPROLDZmbi = 12048, X86_VPROLDZmbik = 12049, X86_VPROLDZmbikz = 12050, X86_VPROLDZmi = 12051, X86_VPROLDZmik = 12052, X86_VPROLDZmikz = 12053, X86_VPROLDZri = 12054, X86_VPROLDZrik = 12055, X86_VPROLDZrikz = 12056, X86_VPROLQZ128mbi = 12057, X86_VPROLQZ128mbik = 12058, X86_VPROLQZ128mbikz = 12059, X86_VPROLQZ128mi = 12060, X86_VPROLQZ128mik = 12061, X86_VPROLQZ128mikz = 12062, X86_VPROLQZ128ri = 12063, X86_VPROLQZ128rik = 12064, X86_VPROLQZ128rikz = 12065, X86_VPROLQZ256mbi = 12066, X86_VPROLQZ256mbik = 12067, X86_VPROLQZ256mbikz = 12068, X86_VPROLQZ256mi = 12069, X86_VPROLQZ256mik = 12070, X86_VPROLQZ256mikz = 12071, X86_VPROLQZ256ri = 12072, X86_VPROLQZ256rik = 12073, X86_VPROLQZ256rikz = 12074, X86_VPROLQZmbi = 12075, X86_VPROLQZmbik = 12076, X86_VPROLQZmbikz = 12077, X86_VPROLQZmi = 12078, X86_VPROLQZmik = 12079, X86_VPROLQZmikz = 12080, X86_VPROLQZri = 12081, X86_VPROLQZrik = 12082, X86_VPROLQZrikz = 12083, X86_VPROLVDZ128rm = 12084, X86_VPROLVDZ128rmb = 12085, X86_VPROLVDZ128rmbk = 12086, X86_VPROLVDZ128rmbkz = 12087, X86_VPROLVDZ128rmk = 12088, X86_VPROLVDZ128rmkz = 12089, X86_VPROLVDZ128rr = 12090, X86_VPROLVDZ128rrk = 12091, X86_VPROLVDZ128rrkz = 12092, X86_VPROLVDZ256rm = 12093, X86_VPROLVDZ256rmb = 12094, X86_VPROLVDZ256rmbk = 12095, X86_VPROLVDZ256rmbkz = 12096, X86_VPROLVDZ256rmk = 12097, X86_VPROLVDZ256rmkz = 12098, X86_VPROLVDZ256rr = 12099, X86_VPROLVDZ256rrk = 12100, X86_VPROLVDZ256rrkz = 12101, X86_VPROLVDZrm = 12102, X86_VPROLVDZrmb = 12103, X86_VPROLVDZrmbk = 12104, X86_VPROLVDZrmbkz = 12105, X86_VPROLVDZrmk = 12106, X86_VPROLVDZrmkz = 12107, X86_VPROLVDZrr = 12108, X86_VPROLVDZrrk = 12109, X86_VPROLVDZrrkz = 12110, X86_VPROLVQZ128rm = 12111, X86_VPROLVQZ128rmb = 12112, X86_VPROLVQZ128rmbk = 12113, X86_VPROLVQZ128rmbkz = 12114, X86_VPROLVQZ128rmk = 12115, X86_VPROLVQZ128rmkz = 12116, X86_VPROLVQZ128rr = 12117, X86_VPROLVQZ128rrk = 12118, X86_VPROLVQZ128rrkz = 12119, X86_VPROLVQZ256rm = 12120, X86_VPROLVQZ256rmb = 12121, X86_VPROLVQZ256rmbk = 12122, X86_VPROLVQZ256rmbkz = 12123, X86_VPROLVQZ256rmk = 12124, X86_VPROLVQZ256rmkz = 12125, X86_VPROLVQZ256rr = 12126, X86_VPROLVQZ256rrk = 12127, X86_VPROLVQZ256rrkz = 12128, X86_VPROLVQZrm = 12129, X86_VPROLVQZrmb = 12130, X86_VPROLVQZrmbk = 12131, X86_VPROLVQZrmbkz = 12132, X86_VPROLVQZrmk = 12133, X86_VPROLVQZrmkz = 12134, X86_VPROLVQZrr = 12135, X86_VPROLVQZrrk = 12136, X86_VPROLVQZrrkz = 12137, X86_VPRORDZ128mbi = 12138, X86_VPRORDZ128mbik = 12139, X86_VPRORDZ128mbikz = 12140, X86_VPRORDZ128mi = 12141, X86_VPRORDZ128mik = 12142, X86_VPRORDZ128mikz = 12143, X86_VPRORDZ128ri = 12144, X86_VPRORDZ128rik = 12145, X86_VPRORDZ128rikz = 12146, X86_VPRORDZ256mbi = 12147, X86_VPRORDZ256mbik = 12148, X86_VPRORDZ256mbikz = 12149, X86_VPRORDZ256mi = 12150, X86_VPRORDZ256mik = 12151, X86_VPRORDZ256mikz = 12152, X86_VPRORDZ256ri = 12153, X86_VPRORDZ256rik = 12154, X86_VPRORDZ256rikz = 12155, X86_VPRORDZmbi = 12156, X86_VPRORDZmbik = 12157, X86_VPRORDZmbikz = 12158, X86_VPRORDZmi = 12159, X86_VPRORDZmik = 12160, X86_VPRORDZmikz = 12161, X86_VPRORDZri = 12162, X86_VPRORDZrik = 12163, X86_VPRORDZrikz = 12164, X86_VPRORQZ128mbi = 12165, X86_VPRORQZ128mbik = 12166, X86_VPRORQZ128mbikz = 12167, X86_VPRORQZ128mi = 12168, X86_VPRORQZ128mik = 12169, X86_VPRORQZ128mikz = 12170, X86_VPRORQZ128ri = 12171, X86_VPRORQZ128rik = 12172, X86_VPRORQZ128rikz = 12173, X86_VPRORQZ256mbi = 12174, X86_VPRORQZ256mbik = 12175, X86_VPRORQZ256mbikz = 12176, X86_VPRORQZ256mi = 12177, X86_VPRORQZ256mik = 12178, X86_VPRORQZ256mikz = 12179, X86_VPRORQZ256ri = 12180, X86_VPRORQZ256rik = 12181, X86_VPRORQZ256rikz = 12182, X86_VPRORQZmbi = 12183, X86_VPRORQZmbik = 12184, X86_VPRORQZmbikz = 12185, X86_VPRORQZmi = 12186, X86_VPRORQZmik = 12187, X86_VPRORQZmikz = 12188, X86_VPRORQZri = 12189, X86_VPRORQZrik = 12190, X86_VPRORQZrikz = 12191, X86_VPRORVDZ128rm = 12192, X86_VPRORVDZ128rmb = 12193, X86_VPRORVDZ128rmbk = 12194, X86_VPRORVDZ128rmbkz = 12195, X86_VPRORVDZ128rmk = 12196, X86_VPRORVDZ128rmkz = 12197, X86_VPRORVDZ128rr = 12198, X86_VPRORVDZ128rrk = 12199, X86_VPRORVDZ128rrkz = 12200, X86_VPRORVDZ256rm = 12201, X86_VPRORVDZ256rmb = 12202, X86_VPRORVDZ256rmbk = 12203, X86_VPRORVDZ256rmbkz = 12204, X86_VPRORVDZ256rmk = 12205, X86_VPRORVDZ256rmkz = 12206, X86_VPRORVDZ256rr = 12207, X86_VPRORVDZ256rrk = 12208, X86_VPRORVDZ256rrkz = 12209, X86_VPRORVDZrm = 12210, X86_VPRORVDZrmb = 12211, X86_VPRORVDZrmbk = 12212, X86_VPRORVDZrmbkz = 12213, X86_VPRORVDZrmk = 12214, X86_VPRORVDZrmkz = 12215, X86_VPRORVDZrr = 12216, X86_VPRORVDZrrk = 12217, X86_VPRORVDZrrkz = 12218, X86_VPRORVQZ128rm = 12219, X86_VPRORVQZ128rmb = 12220, X86_VPRORVQZ128rmbk = 12221, X86_VPRORVQZ128rmbkz = 12222, X86_VPRORVQZ128rmk = 12223, X86_VPRORVQZ128rmkz = 12224, X86_VPRORVQZ128rr = 12225, X86_VPRORVQZ128rrk = 12226, X86_VPRORVQZ128rrkz = 12227, X86_VPRORVQZ256rm = 12228, X86_VPRORVQZ256rmb = 12229, X86_VPRORVQZ256rmbk = 12230, X86_VPRORVQZ256rmbkz = 12231, X86_VPRORVQZ256rmk = 12232, X86_VPRORVQZ256rmkz = 12233, X86_VPRORVQZ256rr = 12234, X86_VPRORVQZ256rrk = 12235, X86_VPRORVQZ256rrkz = 12236, X86_VPRORVQZrm = 12237, X86_VPRORVQZrmb = 12238, X86_VPRORVQZrmbk = 12239, X86_VPRORVQZrmbkz = 12240, X86_VPRORVQZrmk = 12241, X86_VPRORVQZrmkz = 12242, X86_VPRORVQZrr = 12243, X86_VPRORVQZrrk = 12244, X86_VPRORVQZrrkz = 12245, X86_VPROTBmi = 12246, X86_VPROTBmr = 12247, X86_VPROTBri = 12248, X86_VPROTBrm = 12249, X86_VPROTBrr = 12250, X86_VPROTBrr_REV = 12251, X86_VPROTDmi = 12252, X86_VPROTDmr = 12253, X86_VPROTDri = 12254, X86_VPROTDrm = 12255, X86_VPROTDrr = 12256, X86_VPROTDrr_REV = 12257, X86_VPROTQmi = 12258, X86_VPROTQmr = 12259, X86_VPROTQri = 12260, X86_VPROTQrm = 12261, X86_VPROTQrr = 12262, X86_VPROTQrr_REV = 12263, X86_VPROTWmi = 12264, X86_VPROTWmr = 12265, X86_VPROTWri = 12266, X86_VPROTWrm = 12267, X86_VPROTWrr = 12268, X86_VPROTWrr_REV = 12269, X86_VPSADBWYrm = 12270, X86_VPSADBWYrr = 12271, X86_VPSADBWZ128rm = 12272, X86_VPSADBWZ128rr = 12273, X86_VPSADBWZ256rm = 12274, X86_VPSADBWZ256rr = 12275, X86_VPSADBWZrm = 12276, X86_VPSADBWZrr = 12277, X86_VPSADBWrm = 12278, X86_VPSADBWrr = 12279, X86_VPSCATTERDDZ128mr = 12280, X86_VPSCATTERDDZ256mr = 12281, X86_VPSCATTERDDZmr = 12282, X86_VPSCATTERDQZ128mr = 12283, X86_VPSCATTERDQZ256mr = 12284, X86_VPSCATTERDQZmr = 12285, X86_VPSCATTERQDZ128mr = 12286, X86_VPSCATTERQDZ256mr = 12287, X86_VPSCATTERQDZmr = 12288, X86_VPSCATTERQQZ128mr = 12289, X86_VPSCATTERQQZ256mr = 12290, X86_VPSCATTERQQZmr = 12291, X86_VPSHABmr = 12292, X86_VPSHABrm = 12293, X86_VPSHABrr = 12294, X86_VPSHABrr_REV = 12295, X86_VPSHADmr = 12296, X86_VPSHADrm = 12297, X86_VPSHADrr = 12298, X86_VPSHADrr_REV = 12299, X86_VPSHAQmr = 12300, X86_VPSHAQrm = 12301, X86_VPSHAQrr = 12302, X86_VPSHAQrr_REV = 12303, X86_VPSHAWmr = 12304, X86_VPSHAWrm = 12305, X86_VPSHAWrr = 12306, X86_VPSHAWrr_REV = 12307, X86_VPSHLBmr = 12308, X86_VPSHLBrm = 12309, X86_VPSHLBrr = 12310, X86_VPSHLBrr_REV = 12311, X86_VPSHLDDZ128rmbi = 12312, X86_VPSHLDDZ128rmbik = 12313, X86_VPSHLDDZ128rmbikz = 12314, X86_VPSHLDDZ128rmi = 12315, X86_VPSHLDDZ128rmik = 12316, X86_VPSHLDDZ128rmikz = 12317, X86_VPSHLDDZ128rri = 12318, X86_VPSHLDDZ128rrik = 12319, X86_VPSHLDDZ128rrikz = 12320, X86_VPSHLDDZ256rmbi = 12321, X86_VPSHLDDZ256rmbik = 12322, X86_VPSHLDDZ256rmbikz = 12323, X86_VPSHLDDZ256rmi = 12324, X86_VPSHLDDZ256rmik = 12325, X86_VPSHLDDZ256rmikz = 12326, X86_VPSHLDDZ256rri = 12327, X86_VPSHLDDZ256rrik = 12328, X86_VPSHLDDZ256rrikz = 12329, X86_VPSHLDDZrmbi = 12330, X86_VPSHLDDZrmbik = 12331, X86_VPSHLDDZrmbikz = 12332, X86_VPSHLDDZrmi = 12333, X86_VPSHLDDZrmik = 12334, X86_VPSHLDDZrmikz = 12335, X86_VPSHLDDZrri = 12336, X86_VPSHLDDZrrik = 12337, X86_VPSHLDDZrrikz = 12338, X86_VPSHLDQZ128rmbi = 12339, X86_VPSHLDQZ128rmbik = 12340, X86_VPSHLDQZ128rmbikz = 12341, X86_VPSHLDQZ128rmi = 12342, X86_VPSHLDQZ128rmik = 12343, X86_VPSHLDQZ128rmikz = 12344, X86_VPSHLDQZ128rri = 12345, X86_VPSHLDQZ128rrik = 12346, X86_VPSHLDQZ128rrikz = 12347, X86_VPSHLDQZ256rmbi = 12348, X86_VPSHLDQZ256rmbik = 12349, X86_VPSHLDQZ256rmbikz = 12350, X86_VPSHLDQZ256rmi = 12351, X86_VPSHLDQZ256rmik = 12352, X86_VPSHLDQZ256rmikz = 12353, X86_VPSHLDQZ256rri = 12354, X86_VPSHLDQZ256rrik = 12355, X86_VPSHLDQZ256rrikz = 12356, X86_VPSHLDQZrmbi = 12357, X86_VPSHLDQZrmbik = 12358, X86_VPSHLDQZrmbikz = 12359, X86_VPSHLDQZrmi = 12360, X86_VPSHLDQZrmik = 12361, X86_VPSHLDQZrmikz = 12362, X86_VPSHLDQZrri = 12363, X86_VPSHLDQZrrik = 12364, X86_VPSHLDQZrrikz = 12365, X86_VPSHLDVDZ128m = 12366, X86_VPSHLDVDZ128mb = 12367, X86_VPSHLDVDZ128mbk = 12368, X86_VPSHLDVDZ128mbkz = 12369, X86_VPSHLDVDZ128mk = 12370, X86_VPSHLDVDZ128mkz = 12371, X86_VPSHLDVDZ128r = 12372, X86_VPSHLDVDZ128rk = 12373, X86_VPSHLDVDZ128rkz = 12374, X86_VPSHLDVDZ256m = 12375, X86_VPSHLDVDZ256mb = 12376, X86_VPSHLDVDZ256mbk = 12377, X86_VPSHLDVDZ256mbkz = 12378, X86_VPSHLDVDZ256mk = 12379, X86_VPSHLDVDZ256mkz = 12380, X86_VPSHLDVDZ256r = 12381, X86_VPSHLDVDZ256rk = 12382, X86_VPSHLDVDZ256rkz = 12383, X86_VPSHLDVDZm = 12384, X86_VPSHLDVDZmb = 12385, X86_VPSHLDVDZmbk = 12386, X86_VPSHLDVDZmbkz = 12387, X86_VPSHLDVDZmk = 12388, X86_VPSHLDVDZmkz = 12389, X86_VPSHLDVDZr = 12390, X86_VPSHLDVDZrk = 12391, X86_VPSHLDVDZrkz = 12392, X86_VPSHLDVQZ128m = 12393, X86_VPSHLDVQZ128mb = 12394, X86_VPSHLDVQZ128mbk = 12395, X86_VPSHLDVQZ128mbkz = 12396, X86_VPSHLDVQZ128mk = 12397, X86_VPSHLDVQZ128mkz = 12398, X86_VPSHLDVQZ128r = 12399, X86_VPSHLDVQZ128rk = 12400, X86_VPSHLDVQZ128rkz = 12401, X86_VPSHLDVQZ256m = 12402, X86_VPSHLDVQZ256mb = 12403, X86_VPSHLDVQZ256mbk = 12404, X86_VPSHLDVQZ256mbkz = 12405, X86_VPSHLDVQZ256mk = 12406, X86_VPSHLDVQZ256mkz = 12407, X86_VPSHLDVQZ256r = 12408, X86_VPSHLDVQZ256rk = 12409, X86_VPSHLDVQZ256rkz = 12410, X86_VPSHLDVQZm = 12411, X86_VPSHLDVQZmb = 12412, X86_VPSHLDVQZmbk = 12413, X86_VPSHLDVQZmbkz = 12414, X86_VPSHLDVQZmk = 12415, X86_VPSHLDVQZmkz = 12416, X86_VPSHLDVQZr = 12417, X86_VPSHLDVQZrk = 12418, X86_VPSHLDVQZrkz = 12419, X86_VPSHLDVWZ128m = 12420, X86_VPSHLDVWZ128mk = 12421, X86_VPSHLDVWZ128mkz = 12422, X86_VPSHLDVWZ128r = 12423, X86_VPSHLDVWZ128rk = 12424, X86_VPSHLDVWZ128rkz = 12425, X86_VPSHLDVWZ256m = 12426, X86_VPSHLDVWZ256mk = 12427, X86_VPSHLDVWZ256mkz = 12428, X86_VPSHLDVWZ256r = 12429, X86_VPSHLDVWZ256rk = 12430, X86_VPSHLDVWZ256rkz = 12431, X86_VPSHLDVWZm = 12432, X86_VPSHLDVWZmk = 12433, X86_VPSHLDVWZmkz = 12434, X86_VPSHLDVWZr = 12435, X86_VPSHLDVWZrk = 12436, X86_VPSHLDVWZrkz = 12437, X86_VPSHLDWZ128rmi = 12438, X86_VPSHLDWZ128rmik = 12439, X86_VPSHLDWZ128rmikz = 12440, X86_VPSHLDWZ128rri = 12441, X86_VPSHLDWZ128rrik = 12442, X86_VPSHLDWZ128rrikz = 12443, X86_VPSHLDWZ256rmi = 12444, X86_VPSHLDWZ256rmik = 12445, X86_VPSHLDWZ256rmikz = 12446, X86_VPSHLDWZ256rri = 12447, X86_VPSHLDWZ256rrik = 12448, X86_VPSHLDWZ256rrikz = 12449, X86_VPSHLDWZrmi = 12450, X86_VPSHLDWZrmik = 12451, X86_VPSHLDWZrmikz = 12452, X86_VPSHLDWZrri = 12453, X86_VPSHLDWZrrik = 12454, X86_VPSHLDWZrrikz = 12455, X86_VPSHLDmr = 12456, X86_VPSHLDrm = 12457, X86_VPSHLDrr = 12458, X86_VPSHLDrr_REV = 12459, X86_VPSHLQmr = 12460, X86_VPSHLQrm = 12461, X86_VPSHLQrr = 12462, X86_VPSHLQrr_REV = 12463, X86_VPSHLWmr = 12464, X86_VPSHLWrm = 12465, X86_VPSHLWrr = 12466, X86_VPSHLWrr_REV = 12467, X86_VPSHRDDZ128rmbi = 12468, X86_VPSHRDDZ128rmbik = 12469, X86_VPSHRDDZ128rmbikz = 12470, X86_VPSHRDDZ128rmi = 12471, X86_VPSHRDDZ128rmik = 12472, X86_VPSHRDDZ128rmikz = 12473, X86_VPSHRDDZ128rri = 12474, X86_VPSHRDDZ128rrik = 12475, X86_VPSHRDDZ128rrikz = 12476, X86_VPSHRDDZ256rmbi = 12477, X86_VPSHRDDZ256rmbik = 12478, X86_VPSHRDDZ256rmbikz = 12479, X86_VPSHRDDZ256rmi = 12480, X86_VPSHRDDZ256rmik = 12481, X86_VPSHRDDZ256rmikz = 12482, X86_VPSHRDDZ256rri = 12483, X86_VPSHRDDZ256rrik = 12484, X86_VPSHRDDZ256rrikz = 12485, X86_VPSHRDDZrmbi = 12486, X86_VPSHRDDZrmbik = 12487, X86_VPSHRDDZrmbikz = 12488, X86_VPSHRDDZrmi = 12489, X86_VPSHRDDZrmik = 12490, X86_VPSHRDDZrmikz = 12491, X86_VPSHRDDZrri = 12492, X86_VPSHRDDZrrik = 12493, X86_VPSHRDDZrrikz = 12494, X86_VPSHRDQZ128rmbi = 12495, X86_VPSHRDQZ128rmbik = 12496, X86_VPSHRDQZ128rmbikz = 12497, X86_VPSHRDQZ128rmi = 12498, X86_VPSHRDQZ128rmik = 12499, X86_VPSHRDQZ128rmikz = 12500, X86_VPSHRDQZ128rri = 12501, X86_VPSHRDQZ128rrik = 12502, X86_VPSHRDQZ128rrikz = 12503, X86_VPSHRDQZ256rmbi = 12504, X86_VPSHRDQZ256rmbik = 12505, X86_VPSHRDQZ256rmbikz = 12506, X86_VPSHRDQZ256rmi = 12507, X86_VPSHRDQZ256rmik = 12508, X86_VPSHRDQZ256rmikz = 12509, X86_VPSHRDQZ256rri = 12510, X86_VPSHRDQZ256rrik = 12511, X86_VPSHRDQZ256rrikz = 12512, X86_VPSHRDQZrmbi = 12513, X86_VPSHRDQZrmbik = 12514, X86_VPSHRDQZrmbikz = 12515, X86_VPSHRDQZrmi = 12516, X86_VPSHRDQZrmik = 12517, X86_VPSHRDQZrmikz = 12518, X86_VPSHRDQZrri = 12519, X86_VPSHRDQZrrik = 12520, X86_VPSHRDQZrrikz = 12521, X86_VPSHRDVDZ128m = 12522, X86_VPSHRDVDZ128mb = 12523, X86_VPSHRDVDZ128mbk = 12524, X86_VPSHRDVDZ128mbkz = 12525, X86_VPSHRDVDZ128mk = 12526, X86_VPSHRDVDZ128mkz = 12527, X86_VPSHRDVDZ128r = 12528, X86_VPSHRDVDZ128rk = 12529, X86_VPSHRDVDZ128rkz = 12530, X86_VPSHRDVDZ256m = 12531, X86_VPSHRDVDZ256mb = 12532, X86_VPSHRDVDZ256mbk = 12533, X86_VPSHRDVDZ256mbkz = 12534, X86_VPSHRDVDZ256mk = 12535, X86_VPSHRDVDZ256mkz = 12536, X86_VPSHRDVDZ256r = 12537, X86_VPSHRDVDZ256rk = 12538, X86_VPSHRDVDZ256rkz = 12539, X86_VPSHRDVDZm = 12540, X86_VPSHRDVDZmb = 12541, X86_VPSHRDVDZmbk = 12542, X86_VPSHRDVDZmbkz = 12543, X86_VPSHRDVDZmk = 12544, X86_VPSHRDVDZmkz = 12545, X86_VPSHRDVDZr = 12546, X86_VPSHRDVDZrk = 12547, X86_VPSHRDVDZrkz = 12548, X86_VPSHRDVQZ128m = 12549, X86_VPSHRDVQZ128mb = 12550, X86_VPSHRDVQZ128mbk = 12551, X86_VPSHRDVQZ128mbkz = 12552, X86_VPSHRDVQZ128mk = 12553, X86_VPSHRDVQZ128mkz = 12554, X86_VPSHRDVQZ128r = 12555, X86_VPSHRDVQZ128rk = 12556, X86_VPSHRDVQZ128rkz = 12557, X86_VPSHRDVQZ256m = 12558, X86_VPSHRDVQZ256mb = 12559, X86_VPSHRDVQZ256mbk = 12560, X86_VPSHRDVQZ256mbkz = 12561, X86_VPSHRDVQZ256mk = 12562, X86_VPSHRDVQZ256mkz = 12563, X86_VPSHRDVQZ256r = 12564, X86_VPSHRDVQZ256rk = 12565, X86_VPSHRDVQZ256rkz = 12566, X86_VPSHRDVQZm = 12567, X86_VPSHRDVQZmb = 12568, X86_VPSHRDVQZmbk = 12569, X86_VPSHRDVQZmbkz = 12570, X86_VPSHRDVQZmk = 12571, X86_VPSHRDVQZmkz = 12572, X86_VPSHRDVQZr = 12573, X86_VPSHRDVQZrk = 12574, X86_VPSHRDVQZrkz = 12575, X86_VPSHRDVWZ128m = 12576, X86_VPSHRDVWZ128mk = 12577, X86_VPSHRDVWZ128mkz = 12578, X86_VPSHRDVWZ128r = 12579, X86_VPSHRDVWZ128rk = 12580, X86_VPSHRDVWZ128rkz = 12581, X86_VPSHRDVWZ256m = 12582, X86_VPSHRDVWZ256mk = 12583, X86_VPSHRDVWZ256mkz = 12584, X86_VPSHRDVWZ256r = 12585, X86_VPSHRDVWZ256rk = 12586, X86_VPSHRDVWZ256rkz = 12587, X86_VPSHRDVWZm = 12588, X86_VPSHRDVWZmk = 12589, X86_VPSHRDVWZmkz = 12590, X86_VPSHRDVWZr = 12591, X86_VPSHRDVWZrk = 12592, X86_VPSHRDVWZrkz = 12593, X86_VPSHRDWZ128rmi = 12594, X86_VPSHRDWZ128rmik = 12595, X86_VPSHRDWZ128rmikz = 12596, X86_VPSHRDWZ128rri = 12597, X86_VPSHRDWZ128rrik = 12598, X86_VPSHRDWZ128rrikz = 12599, X86_VPSHRDWZ256rmi = 12600, X86_VPSHRDWZ256rmik = 12601, X86_VPSHRDWZ256rmikz = 12602, X86_VPSHRDWZ256rri = 12603, X86_VPSHRDWZ256rrik = 12604, X86_VPSHRDWZ256rrikz = 12605, X86_VPSHRDWZrmi = 12606, X86_VPSHRDWZrmik = 12607, X86_VPSHRDWZrmikz = 12608, X86_VPSHRDWZrri = 12609, X86_VPSHRDWZrrik = 12610, X86_VPSHRDWZrrikz = 12611, X86_VPSHUFBITQMBZ128rm = 12612, X86_VPSHUFBITQMBZ128rmk = 12613, X86_VPSHUFBITQMBZ128rr = 12614, X86_VPSHUFBITQMBZ128rrk = 12615, X86_VPSHUFBITQMBZ256rm = 12616, X86_VPSHUFBITQMBZ256rmk = 12617, X86_VPSHUFBITQMBZ256rr = 12618, X86_VPSHUFBITQMBZ256rrk = 12619, X86_VPSHUFBITQMBZrm = 12620, X86_VPSHUFBITQMBZrmk = 12621, X86_VPSHUFBITQMBZrr = 12622, X86_VPSHUFBITQMBZrrk = 12623, X86_VPSHUFBYrm = 12624, X86_VPSHUFBYrr = 12625, X86_VPSHUFBZ128rm = 12626, X86_VPSHUFBZ128rmk = 12627, X86_VPSHUFBZ128rmkz = 12628, X86_VPSHUFBZ128rr = 12629, X86_VPSHUFBZ128rrk = 12630, X86_VPSHUFBZ128rrkz = 12631, X86_VPSHUFBZ256rm = 12632, X86_VPSHUFBZ256rmk = 12633, X86_VPSHUFBZ256rmkz = 12634, X86_VPSHUFBZ256rr = 12635, X86_VPSHUFBZ256rrk = 12636, X86_VPSHUFBZ256rrkz = 12637, X86_VPSHUFBZrm = 12638, X86_VPSHUFBZrmk = 12639, X86_VPSHUFBZrmkz = 12640, X86_VPSHUFBZrr = 12641, X86_VPSHUFBZrrk = 12642, X86_VPSHUFBZrrkz = 12643, X86_VPSHUFBrm = 12644, X86_VPSHUFBrr = 12645, X86_VPSHUFDYmi = 12646, X86_VPSHUFDYri = 12647, X86_VPSHUFDZ128mbi = 12648, X86_VPSHUFDZ128mbik = 12649, X86_VPSHUFDZ128mbikz = 12650, X86_VPSHUFDZ128mi = 12651, X86_VPSHUFDZ128mik = 12652, X86_VPSHUFDZ128mikz = 12653, X86_VPSHUFDZ128ri = 12654, X86_VPSHUFDZ128rik = 12655, X86_VPSHUFDZ128rikz = 12656, X86_VPSHUFDZ256mbi = 12657, X86_VPSHUFDZ256mbik = 12658, X86_VPSHUFDZ256mbikz = 12659, X86_VPSHUFDZ256mi = 12660, X86_VPSHUFDZ256mik = 12661, X86_VPSHUFDZ256mikz = 12662, X86_VPSHUFDZ256ri = 12663, X86_VPSHUFDZ256rik = 12664, X86_VPSHUFDZ256rikz = 12665, X86_VPSHUFDZmbi = 12666, X86_VPSHUFDZmbik = 12667, X86_VPSHUFDZmbikz = 12668, X86_VPSHUFDZmi = 12669, X86_VPSHUFDZmik = 12670, X86_VPSHUFDZmikz = 12671, X86_VPSHUFDZri = 12672, X86_VPSHUFDZrik = 12673, X86_VPSHUFDZrikz = 12674, X86_VPSHUFDmi = 12675, X86_VPSHUFDri = 12676, X86_VPSHUFHWYmi = 12677, X86_VPSHUFHWYri = 12678, X86_VPSHUFHWZ128mi = 12679, X86_VPSHUFHWZ128mik = 12680, X86_VPSHUFHWZ128mikz = 12681, X86_VPSHUFHWZ128ri = 12682, X86_VPSHUFHWZ128rik = 12683, X86_VPSHUFHWZ128rikz = 12684, X86_VPSHUFHWZ256mi = 12685, X86_VPSHUFHWZ256mik = 12686, X86_VPSHUFHWZ256mikz = 12687, X86_VPSHUFHWZ256ri = 12688, X86_VPSHUFHWZ256rik = 12689, X86_VPSHUFHWZ256rikz = 12690, X86_VPSHUFHWZmi = 12691, X86_VPSHUFHWZmik = 12692, X86_VPSHUFHWZmikz = 12693, X86_VPSHUFHWZri = 12694, X86_VPSHUFHWZrik = 12695, X86_VPSHUFHWZrikz = 12696, X86_VPSHUFHWmi = 12697, X86_VPSHUFHWri = 12698, X86_VPSHUFLWYmi = 12699, X86_VPSHUFLWYri = 12700, X86_VPSHUFLWZ128mi = 12701, X86_VPSHUFLWZ128mik = 12702, X86_VPSHUFLWZ128mikz = 12703, X86_VPSHUFLWZ128ri = 12704, X86_VPSHUFLWZ128rik = 12705, X86_VPSHUFLWZ128rikz = 12706, X86_VPSHUFLWZ256mi = 12707, X86_VPSHUFLWZ256mik = 12708, X86_VPSHUFLWZ256mikz = 12709, X86_VPSHUFLWZ256ri = 12710, X86_VPSHUFLWZ256rik = 12711, X86_VPSHUFLWZ256rikz = 12712, X86_VPSHUFLWZmi = 12713, X86_VPSHUFLWZmik = 12714, X86_VPSHUFLWZmikz = 12715, X86_VPSHUFLWZri = 12716, X86_VPSHUFLWZrik = 12717, X86_VPSHUFLWZrikz = 12718, X86_VPSHUFLWmi = 12719, X86_VPSHUFLWri = 12720, X86_VPSIGNBYrm = 12721, X86_VPSIGNBYrr = 12722, X86_VPSIGNBrm = 12723, X86_VPSIGNBrr = 12724, X86_VPSIGNDYrm = 12725, X86_VPSIGNDYrr = 12726, X86_VPSIGNDrm = 12727, X86_VPSIGNDrr = 12728, X86_VPSIGNWYrm = 12729, X86_VPSIGNWYrr = 12730, X86_VPSIGNWrm = 12731, X86_VPSIGNWrr = 12732, X86_VPSLLDQYri = 12733, X86_VPSLLDQZ128rm = 12734, X86_VPSLLDQZ128rr = 12735, X86_VPSLLDQZ256rm = 12736, X86_VPSLLDQZ256rr = 12737, X86_VPSLLDQZrm = 12738, X86_VPSLLDQZrr = 12739, X86_VPSLLDQri = 12740, X86_VPSLLDYri = 12741, X86_VPSLLDYrm = 12742, X86_VPSLLDYrr = 12743, X86_VPSLLDZ128mbi = 12744, X86_VPSLLDZ128mbik = 12745, X86_VPSLLDZ128mbikz = 12746, X86_VPSLLDZ128mi = 12747, X86_VPSLLDZ128mik = 12748, X86_VPSLLDZ128mikz = 12749, X86_VPSLLDZ128ri = 12750, X86_VPSLLDZ128rik = 12751, X86_VPSLLDZ128rikz = 12752, X86_VPSLLDZ128rm = 12753, X86_VPSLLDZ128rmk = 12754, X86_VPSLLDZ128rmkz = 12755, X86_VPSLLDZ128rr = 12756, X86_VPSLLDZ128rrk = 12757, X86_VPSLLDZ128rrkz = 12758, X86_VPSLLDZ256mbi = 12759, X86_VPSLLDZ256mbik = 12760, X86_VPSLLDZ256mbikz = 12761, X86_VPSLLDZ256mi = 12762, X86_VPSLLDZ256mik = 12763, X86_VPSLLDZ256mikz = 12764, X86_VPSLLDZ256ri = 12765, X86_VPSLLDZ256rik = 12766, X86_VPSLLDZ256rikz = 12767, X86_VPSLLDZ256rm = 12768, X86_VPSLLDZ256rmk = 12769, X86_VPSLLDZ256rmkz = 12770, X86_VPSLLDZ256rr = 12771, X86_VPSLLDZ256rrk = 12772, X86_VPSLLDZ256rrkz = 12773, X86_VPSLLDZmbi = 12774, X86_VPSLLDZmbik = 12775, X86_VPSLLDZmbikz = 12776, X86_VPSLLDZmi = 12777, X86_VPSLLDZmik = 12778, X86_VPSLLDZmikz = 12779, X86_VPSLLDZri = 12780, X86_VPSLLDZrik = 12781, X86_VPSLLDZrikz = 12782, X86_VPSLLDZrm = 12783, X86_VPSLLDZrmk = 12784, X86_VPSLLDZrmkz = 12785, X86_VPSLLDZrr = 12786, X86_VPSLLDZrrk = 12787, X86_VPSLLDZrrkz = 12788, X86_VPSLLDri = 12789, X86_VPSLLDrm = 12790, X86_VPSLLDrr = 12791, X86_VPSLLQYri = 12792, X86_VPSLLQYrm = 12793, X86_VPSLLQYrr = 12794, X86_VPSLLQZ128mbi = 12795, X86_VPSLLQZ128mbik = 12796, X86_VPSLLQZ128mbikz = 12797, X86_VPSLLQZ128mi = 12798, X86_VPSLLQZ128mik = 12799, X86_VPSLLQZ128mikz = 12800, X86_VPSLLQZ128ri = 12801, X86_VPSLLQZ128rik = 12802, X86_VPSLLQZ128rikz = 12803, X86_VPSLLQZ128rm = 12804, X86_VPSLLQZ128rmk = 12805, X86_VPSLLQZ128rmkz = 12806, X86_VPSLLQZ128rr = 12807, X86_VPSLLQZ128rrk = 12808, X86_VPSLLQZ128rrkz = 12809, X86_VPSLLQZ256mbi = 12810, X86_VPSLLQZ256mbik = 12811, X86_VPSLLQZ256mbikz = 12812, X86_VPSLLQZ256mi = 12813, X86_VPSLLQZ256mik = 12814, X86_VPSLLQZ256mikz = 12815, X86_VPSLLQZ256ri = 12816, X86_VPSLLQZ256rik = 12817, X86_VPSLLQZ256rikz = 12818, X86_VPSLLQZ256rm = 12819, X86_VPSLLQZ256rmk = 12820, X86_VPSLLQZ256rmkz = 12821, X86_VPSLLQZ256rr = 12822, X86_VPSLLQZ256rrk = 12823, X86_VPSLLQZ256rrkz = 12824, X86_VPSLLQZmbi = 12825, X86_VPSLLQZmbik = 12826, X86_VPSLLQZmbikz = 12827, X86_VPSLLQZmi = 12828, X86_VPSLLQZmik = 12829, X86_VPSLLQZmikz = 12830, X86_VPSLLQZri = 12831, X86_VPSLLQZrik = 12832, X86_VPSLLQZrikz = 12833, X86_VPSLLQZrm = 12834, X86_VPSLLQZrmk = 12835, X86_VPSLLQZrmkz = 12836, X86_VPSLLQZrr = 12837, X86_VPSLLQZrrk = 12838, X86_VPSLLQZrrkz = 12839, X86_VPSLLQri = 12840, X86_VPSLLQrm = 12841, X86_VPSLLQrr = 12842, X86_VPSLLVDYrm = 12843, X86_VPSLLVDYrr = 12844, X86_VPSLLVDZ128rm = 12845, X86_VPSLLVDZ128rmb = 12846, X86_VPSLLVDZ128rmbk = 12847, X86_VPSLLVDZ128rmbkz = 12848, X86_VPSLLVDZ128rmk = 12849, X86_VPSLLVDZ128rmkz = 12850, X86_VPSLLVDZ128rr = 12851, X86_VPSLLVDZ128rrk = 12852, X86_VPSLLVDZ128rrkz = 12853, X86_VPSLLVDZ256rm = 12854, X86_VPSLLVDZ256rmb = 12855, X86_VPSLLVDZ256rmbk = 12856, X86_VPSLLVDZ256rmbkz = 12857, X86_VPSLLVDZ256rmk = 12858, X86_VPSLLVDZ256rmkz = 12859, X86_VPSLLVDZ256rr = 12860, X86_VPSLLVDZ256rrk = 12861, X86_VPSLLVDZ256rrkz = 12862, X86_VPSLLVDZrm = 12863, X86_VPSLLVDZrmb = 12864, X86_VPSLLVDZrmbk = 12865, X86_VPSLLVDZrmbkz = 12866, X86_VPSLLVDZrmk = 12867, X86_VPSLLVDZrmkz = 12868, X86_VPSLLVDZrr = 12869, X86_VPSLLVDZrrk = 12870, X86_VPSLLVDZrrkz = 12871, X86_VPSLLVDrm = 12872, X86_VPSLLVDrr = 12873, X86_VPSLLVQYrm = 12874, X86_VPSLLVQYrr = 12875, X86_VPSLLVQZ128rm = 12876, X86_VPSLLVQZ128rmb = 12877, X86_VPSLLVQZ128rmbk = 12878, X86_VPSLLVQZ128rmbkz = 12879, X86_VPSLLVQZ128rmk = 12880, X86_VPSLLVQZ128rmkz = 12881, X86_VPSLLVQZ128rr = 12882, X86_VPSLLVQZ128rrk = 12883, X86_VPSLLVQZ128rrkz = 12884, X86_VPSLLVQZ256rm = 12885, X86_VPSLLVQZ256rmb = 12886, X86_VPSLLVQZ256rmbk = 12887, X86_VPSLLVQZ256rmbkz = 12888, X86_VPSLLVQZ256rmk = 12889, X86_VPSLLVQZ256rmkz = 12890, X86_VPSLLVQZ256rr = 12891, X86_VPSLLVQZ256rrk = 12892, X86_VPSLLVQZ256rrkz = 12893, X86_VPSLLVQZrm = 12894, X86_VPSLLVQZrmb = 12895, X86_VPSLLVQZrmbk = 12896, X86_VPSLLVQZrmbkz = 12897, X86_VPSLLVQZrmk = 12898, X86_VPSLLVQZrmkz = 12899, X86_VPSLLVQZrr = 12900, X86_VPSLLVQZrrk = 12901, X86_VPSLLVQZrrkz = 12902, X86_VPSLLVQrm = 12903, X86_VPSLLVQrr = 12904, X86_VPSLLVWZ128rm = 12905, X86_VPSLLVWZ128rmk = 12906, X86_VPSLLVWZ128rmkz = 12907, X86_VPSLLVWZ128rr = 12908, X86_VPSLLVWZ128rrk = 12909, X86_VPSLLVWZ128rrkz = 12910, X86_VPSLLVWZ256rm = 12911, X86_VPSLLVWZ256rmk = 12912, X86_VPSLLVWZ256rmkz = 12913, X86_VPSLLVWZ256rr = 12914, X86_VPSLLVWZ256rrk = 12915, X86_VPSLLVWZ256rrkz = 12916, X86_VPSLLVWZrm = 12917, X86_VPSLLVWZrmk = 12918, X86_VPSLLVWZrmkz = 12919, X86_VPSLLVWZrr = 12920, X86_VPSLLVWZrrk = 12921, X86_VPSLLVWZrrkz = 12922, X86_VPSLLWYri = 12923, X86_VPSLLWYrm = 12924, X86_VPSLLWYrr = 12925, X86_VPSLLWZ128mi = 12926, X86_VPSLLWZ128mik = 12927, X86_VPSLLWZ128mikz = 12928, X86_VPSLLWZ128ri = 12929, X86_VPSLLWZ128rik = 12930, X86_VPSLLWZ128rikz = 12931, X86_VPSLLWZ128rm = 12932, X86_VPSLLWZ128rmk = 12933, X86_VPSLLWZ128rmkz = 12934, X86_VPSLLWZ128rr = 12935, X86_VPSLLWZ128rrk = 12936, X86_VPSLLWZ128rrkz = 12937, X86_VPSLLWZ256mi = 12938, X86_VPSLLWZ256mik = 12939, X86_VPSLLWZ256mikz = 12940, X86_VPSLLWZ256ri = 12941, X86_VPSLLWZ256rik = 12942, X86_VPSLLWZ256rikz = 12943, X86_VPSLLWZ256rm = 12944, X86_VPSLLWZ256rmk = 12945, X86_VPSLLWZ256rmkz = 12946, X86_VPSLLWZ256rr = 12947, X86_VPSLLWZ256rrk = 12948, X86_VPSLLWZ256rrkz = 12949, X86_VPSLLWZmi = 12950, X86_VPSLLWZmik = 12951, X86_VPSLLWZmikz = 12952, X86_VPSLLWZri = 12953, X86_VPSLLWZrik = 12954, X86_VPSLLWZrikz = 12955, X86_VPSLLWZrm = 12956, X86_VPSLLWZrmk = 12957, X86_VPSLLWZrmkz = 12958, X86_VPSLLWZrr = 12959, X86_VPSLLWZrrk = 12960, X86_VPSLLWZrrkz = 12961, X86_VPSLLWri = 12962, X86_VPSLLWrm = 12963, X86_VPSLLWrr = 12964, X86_VPSRADYri = 12965, X86_VPSRADYrm = 12966, X86_VPSRADYrr = 12967, X86_VPSRADZ128mbi = 12968, X86_VPSRADZ128mbik = 12969, X86_VPSRADZ128mbikz = 12970, X86_VPSRADZ128mi = 12971, X86_VPSRADZ128mik = 12972, X86_VPSRADZ128mikz = 12973, X86_VPSRADZ128ri = 12974, X86_VPSRADZ128rik = 12975, X86_VPSRADZ128rikz = 12976, X86_VPSRADZ128rm = 12977, X86_VPSRADZ128rmk = 12978, X86_VPSRADZ128rmkz = 12979, X86_VPSRADZ128rr = 12980, X86_VPSRADZ128rrk = 12981, X86_VPSRADZ128rrkz = 12982, X86_VPSRADZ256mbi = 12983, X86_VPSRADZ256mbik = 12984, X86_VPSRADZ256mbikz = 12985, X86_VPSRADZ256mi = 12986, X86_VPSRADZ256mik = 12987, X86_VPSRADZ256mikz = 12988, X86_VPSRADZ256ri = 12989, X86_VPSRADZ256rik = 12990, X86_VPSRADZ256rikz = 12991, X86_VPSRADZ256rm = 12992, X86_VPSRADZ256rmk = 12993, X86_VPSRADZ256rmkz = 12994, X86_VPSRADZ256rr = 12995, X86_VPSRADZ256rrk = 12996, X86_VPSRADZ256rrkz = 12997, X86_VPSRADZmbi = 12998, X86_VPSRADZmbik = 12999, X86_VPSRADZmbikz = 13000, X86_VPSRADZmi = 13001, X86_VPSRADZmik = 13002, X86_VPSRADZmikz = 13003, X86_VPSRADZri = 13004, X86_VPSRADZrik = 13005, X86_VPSRADZrikz = 13006, X86_VPSRADZrm = 13007, X86_VPSRADZrmk = 13008, X86_VPSRADZrmkz = 13009, X86_VPSRADZrr = 13010, X86_VPSRADZrrk = 13011, X86_VPSRADZrrkz = 13012, X86_VPSRADri = 13013, X86_VPSRADrm = 13014, X86_VPSRADrr = 13015, X86_VPSRAQZ128mbi = 13016, X86_VPSRAQZ128mbik = 13017, X86_VPSRAQZ128mbikz = 13018, X86_VPSRAQZ128mi = 13019, X86_VPSRAQZ128mik = 13020, X86_VPSRAQZ128mikz = 13021, X86_VPSRAQZ128ri = 13022, X86_VPSRAQZ128rik = 13023, X86_VPSRAQZ128rikz = 13024, X86_VPSRAQZ128rm = 13025, X86_VPSRAQZ128rmk = 13026, X86_VPSRAQZ128rmkz = 13027, X86_VPSRAQZ128rr = 13028, X86_VPSRAQZ128rrk = 13029, X86_VPSRAQZ128rrkz = 13030, X86_VPSRAQZ256mbi = 13031, X86_VPSRAQZ256mbik = 13032, X86_VPSRAQZ256mbikz = 13033, X86_VPSRAQZ256mi = 13034, X86_VPSRAQZ256mik = 13035, X86_VPSRAQZ256mikz = 13036, X86_VPSRAQZ256ri = 13037, X86_VPSRAQZ256rik = 13038, X86_VPSRAQZ256rikz = 13039, X86_VPSRAQZ256rm = 13040, X86_VPSRAQZ256rmk = 13041, X86_VPSRAQZ256rmkz = 13042, X86_VPSRAQZ256rr = 13043, X86_VPSRAQZ256rrk = 13044, X86_VPSRAQZ256rrkz = 13045, X86_VPSRAQZmbi = 13046, X86_VPSRAQZmbik = 13047, X86_VPSRAQZmbikz = 13048, X86_VPSRAQZmi = 13049, X86_VPSRAQZmik = 13050, X86_VPSRAQZmikz = 13051, X86_VPSRAQZri = 13052, X86_VPSRAQZrik = 13053, X86_VPSRAQZrikz = 13054, X86_VPSRAQZrm = 13055, X86_VPSRAQZrmk = 13056, X86_VPSRAQZrmkz = 13057, X86_VPSRAQZrr = 13058, X86_VPSRAQZrrk = 13059, X86_VPSRAQZrrkz = 13060, X86_VPSRAVDYrm = 13061, X86_VPSRAVDYrr = 13062, X86_VPSRAVDZ128rm = 13063, X86_VPSRAVDZ128rmb = 13064, X86_VPSRAVDZ128rmbk = 13065, X86_VPSRAVDZ128rmbkz = 13066, X86_VPSRAVDZ128rmk = 13067, X86_VPSRAVDZ128rmkz = 13068, X86_VPSRAVDZ128rr = 13069, X86_VPSRAVDZ128rrk = 13070, X86_VPSRAVDZ128rrkz = 13071, X86_VPSRAVDZ256rm = 13072, X86_VPSRAVDZ256rmb = 13073, X86_VPSRAVDZ256rmbk = 13074, X86_VPSRAVDZ256rmbkz = 13075, X86_VPSRAVDZ256rmk = 13076, X86_VPSRAVDZ256rmkz = 13077, X86_VPSRAVDZ256rr = 13078, X86_VPSRAVDZ256rrk = 13079, X86_VPSRAVDZ256rrkz = 13080, X86_VPSRAVDZrm = 13081, X86_VPSRAVDZrmb = 13082, X86_VPSRAVDZrmbk = 13083, X86_VPSRAVDZrmbkz = 13084, X86_VPSRAVDZrmk = 13085, X86_VPSRAVDZrmkz = 13086, X86_VPSRAVDZrr = 13087, X86_VPSRAVDZrrk = 13088, X86_VPSRAVDZrrkz = 13089, X86_VPSRAVDrm = 13090, X86_VPSRAVDrr = 13091, X86_VPSRAVQZ128rm = 13092, X86_VPSRAVQZ128rmb = 13093, X86_VPSRAVQZ128rmbk = 13094, X86_VPSRAVQZ128rmbkz = 13095, X86_VPSRAVQZ128rmk = 13096, X86_VPSRAVQZ128rmkz = 13097, X86_VPSRAVQZ128rr = 13098, X86_VPSRAVQZ128rrk = 13099, X86_VPSRAVQZ128rrkz = 13100, X86_VPSRAVQZ256rm = 13101, X86_VPSRAVQZ256rmb = 13102, X86_VPSRAVQZ256rmbk = 13103, X86_VPSRAVQZ256rmbkz = 13104, X86_VPSRAVQZ256rmk = 13105, X86_VPSRAVQZ256rmkz = 13106, X86_VPSRAVQZ256rr = 13107, X86_VPSRAVQZ256rrk = 13108, X86_VPSRAVQZ256rrkz = 13109, X86_VPSRAVQZrm = 13110, X86_VPSRAVQZrmb = 13111, X86_VPSRAVQZrmbk = 13112, X86_VPSRAVQZrmbkz = 13113, X86_VPSRAVQZrmk = 13114, X86_VPSRAVQZrmkz = 13115, X86_VPSRAVQZrr = 13116, X86_VPSRAVQZrrk = 13117, X86_VPSRAVQZrrkz = 13118, X86_VPSRAVWZ128rm = 13119, X86_VPSRAVWZ128rmk = 13120, X86_VPSRAVWZ128rmkz = 13121, X86_VPSRAVWZ128rr = 13122, X86_VPSRAVWZ128rrk = 13123, X86_VPSRAVWZ128rrkz = 13124, X86_VPSRAVWZ256rm = 13125, X86_VPSRAVWZ256rmk = 13126, X86_VPSRAVWZ256rmkz = 13127, X86_VPSRAVWZ256rr = 13128, X86_VPSRAVWZ256rrk = 13129, X86_VPSRAVWZ256rrkz = 13130, X86_VPSRAVWZrm = 13131, X86_VPSRAVWZrmk = 13132, X86_VPSRAVWZrmkz = 13133, X86_VPSRAVWZrr = 13134, X86_VPSRAVWZrrk = 13135, X86_VPSRAVWZrrkz = 13136, X86_VPSRAWYri = 13137, X86_VPSRAWYrm = 13138, X86_VPSRAWYrr = 13139, X86_VPSRAWZ128mi = 13140, X86_VPSRAWZ128mik = 13141, X86_VPSRAWZ128mikz = 13142, X86_VPSRAWZ128ri = 13143, X86_VPSRAWZ128rik = 13144, X86_VPSRAWZ128rikz = 13145, X86_VPSRAWZ128rm = 13146, X86_VPSRAWZ128rmk = 13147, X86_VPSRAWZ128rmkz = 13148, X86_VPSRAWZ128rr = 13149, X86_VPSRAWZ128rrk = 13150, X86_VPSRAWZ128rrkz = 13151, X86_VPSRAWZ256mi = 13152, X86_VPSRAWZ256mik = 13153, X86_VPSRAWZ256mikz = 13154, X86_VPSRAWZ256ri = 13155, X86_VPSRAWZ256rik = 13156, X86_VPSRAWZ256rikz = 13157, X86_VPSRAWZ256rm = 13158, X86_VPSRAWZ256rmk = 13159, X86_VPSRAWZ256rmkz = 13160, X86_VPSRAWZ256rr = 13161, X86_VPSRAWZ256rrk = 13162, X86_VPSRAWZ256rrkz = 13163, X86_VPSRAWZmi = 13164, X86_VPSRAWZmik = 13165, X86_VPSRAWZmikz = 13166, X86_VPSRAWZri = 13167, X86_VPSRAWZrik = 13168, X86_VPSRAWZrikz = 13169, X86_VPSRAWZrm = 13170, X86_VPSRAWZrmk = 13171, X86_VPSRAWZrmkz = 13172, X86_VPSRAWZrr = 13173, X86_VPSRAWZrrk = 13174, X86_VPSRAWZrrkz = 13175, X86_VPSRAWri = 13176, X86_VPSRAWrm = 13177, X86_VPSRAWrr = 13178, X86_VPSRLDQYri = 13179, X86_VPSRLDQZ128rm = 13180, X86_VPSRLDQZ128rr = 13181, X86_VPSRLDQZ256rm = 13182, X86_VPSRLDQZ256rr = 13183, X86_VPSRLDQZrm = 13184, X86_VPSRLDQZrr = 13185, X86_VPSRLDQri = 13186, X86_VPSRLDYri = 13187, X86_VPSRLDYrm = 13188, X86_VPSRLDYrr = 13189, X86_VPSRLDZ128mbi = 13190, X86_VPSRLDZ128mbik = 13191, X86_VPSRLDZ128mbikz = 13192, X86_VPSRLDZ128mi = 13193, X86_VPSRLDZ128mik = 13194, X86_VPSRLDZ128mikz = 13195, X86_VPSRLDZ128ri = 13196, X86_VPSRLDZ128rik = 13197, X86_VPSRLDZ128rikz = 13198, X86_VPSRLDZ128rm = 13199, X86_VPSRLDZ128rmk = 13200, X86_VPSRLDZ128rmkz = 13201, X86_VPSRLDZ128rr = 13202, X86_VPSRLDZ128rrk = 13203, X86_VPSRLDZ128rrkz = 13204, X86_VPSRLDZ256mbi = 13205, X86_VPSRLDZ256mbik = 13206, X86_VPSRLDZ256mbikz = 13207, X86_VPSRLDZ256mi = 13208, X86_VPSRLDZ256mik = 13209, X86_VPSRLDZ256mikz = 13210, X86_VPSRLDZ256ri = 13211, X86_VPSRLDZ256rik = 13212, X86_VPSRLDZ256rikz = 13213, X86_VPSRLDZ256rm = 13214, X86_VPSRLDZ256rmk = 13215, X86_VPSRLDZ256rmkz = 13216, X86_VPSRLDZ256rr = 13217, X86_VPSRLDZ256rrk = 13218, X86_VPSRLDZ256rrkz = 13219, X86_VPSRLDZmbi = 13220, X86_VPSRLDZmbik = 13221, X86_VPSRLDZmbikz = 13222, X86_VPSRLDZmi = 13223, X86_VPSRLDZmik = 13224, X86_VPSRLDZmikz = 13225, X86_VPSRLDZri = 13226, X86_VPSRLDZrik = 13227, X86_VPSRLDZrikz = 13228, X86_VPSRLDZrm = 13229, X86_VPSRLDZrmk = 13230, X86_VPSRLDZrmkz = 13231, X86_VPSRLDZrr = 13232, X86_VPSRLDZrrk = 13233, X86_VPSRLDZrrkz = 13234, X86_VPSRLDri = 13235, X86_VPSRLDrm = 13236, X86_VPSRLDrr = 13237, X86_VPSRLQYri = 13238, X86_VPSRLQYrm = 13239, X86_VPSRLQYrr = 13240, X86_VPSRLQZ128mbi = 13241, X86_VPSRLQZ128mbik = 13242, X86_VPSRLQZ128mbikz = 13243, X86_VPSRLQZ128mi = 13244, X86_VPSRLQZ128mik = 13245, X86_VPSRLQZ128mikz = 13246, X86_VPSRLQZ128ri = 13247, X86_VPSRLQZ128rik = 13248, X86_VPSRLQZ128rikz = 13249, X86_VPSRLQZ128rm = 13250, X86_VPSRLQZ128rmk = 13251, X86_VPSRLQZ128rmkz = 13252, X86_VPSRLQZ128rr = 13253, X86_VPSRLQZ128rrk = 13254, X86_VPSRLQZ128rrkz = 13255, X86_VPSRLQZ256mbi = 13256, X86_VPSRLQZ256mbik = 13257, X86_VPSRLQZ256mbikz = 13258, X86_VPSRLQZ256mi = 13259, X86_VPSRLQZ256mik = 13260, X86_VPSRLQZ256mikz = 13261, X86_VPSRLQZ256ri = 13262, X86_VPSRLQZ256rik = 13263, X86_VPSRLQZ256rikz = 13264, X86_VPSRLQZ256rm = 13265, X86_VPSRLQZ256rmk = 13266, X86_VPSRLQZ256rmkz = 13267, X86_VPSRLQZ256rr = 13268, X86_VPSRLQZ256rrk = 13269, X86_VPSRLQZ256rrkz = 13270, X86_VPSRLQZmbi = 13271, X86_VPSRLQZmbik = 13272, X86_VPSRLQZmbikz = 13273, X86_VPSRLQZmi = 13274, X86_VPSRLQZmik = 13275, X86_VPSRLQZmikz = 13276, X86_VPSRLQZri = 13277, X86_VPSRLQZrik = 13278, X86_VPSRLQZrikz = 13279, X86_VPSRLQZrm = 13280, X86_VPSRLQZrmk = 13281, X86_VPSRLQZrmkz = 13282, X86_VPSRLQZrr = 13283, X86_VPSRLQZrrk = 13284, X86_VPSRLQZrrkz = 13285, X86_VPSRLQri = 13286, X86_VPSRLQrm = 13287, X86_VPSRLQrr = 13288, X86_VPSRLVDYrm = 13289, X86_VPSRLVDYrr = 13290, X86_VPSRLVDZ128rm = 13291, X86_VPSRLVDZ128rmb = 13292, X86_VPSRLVDZ128rmbk = 13293, X86_VPSRLVDZ128rmbkz = 13294, X86_VPSRLVDZ128rmk = 13295, X86_VPSRLVDZ128rmkz = 13296, X86_VPSRLVDZ128rr = 13297, X86_VPSRLVDZ128rrk = 13298, X86_VPSRLVDZ128rrkz = 13299, X86_VPSRLVDZ256rm = 13300, X86_VPSRLVDZ256rmb = 13301, X86_VPSRLVDZ256rmbk = 13302, X86_VPSRLVDZ256rmbkz = 13303, X86_VPSRLVDZ256rmk = 13304, X86_VPSRLVDZ256rmkz = 13305, X86_VPSRLVDZ256rr = 13306, X86_VPSRLVDZ256rrk = 13307, X86_VPSRLVDZ256rrkz = 13308, X86_VPSRLVDZrm = 13309, X86_VPSRLVDZrmb = 13310, X86_VPSRLVDZrmbk = 13311, X86_VPSRLVDZrmbkz = 13312, X86_VPSRLVDZrmk = 13313, X86_VPSRLVDZrmkz = 13314, X86_VPSRLVDZrr = 13315, X86_VPSRLVDZrrk = 13316, X86_VPSRLVDZrrkz = 13317, X86_VPSRLVDrm = 13318, X86_VPSRLVDrr = 13319, X86_VPSRLVQYrm = 13320, X86_VPSRLVQYrr = 13321, X86_VPSRLVQZ128rm = 13322, X86_VPSRLVQZ128rmb = 13323, X86_VPSRLVQZ128rmbk = 13324, X86_VPSRLVQZ128rmbkz = 13325, X86_VPSRLVQZ128rmk = 13326, X86_VPSRLVQZ128rmkz = 13327, X86_VPSRLVQZ128rr = 13328, X86_VPSRLVQZ128rrk = 13329, X86_VPSRLVQZ128rrkz = 13330, X86_VPSRLVQZ256rm = 13331, X86_VPSRLVQZ256rmb = 13332, X86_VPSRLVQZ256rmbk = 13333, X86_VPSRLVQZ256rmbkz = 13334, X86_VPSRLVQZ256rmk = 13335, X86_VPSRLVQZ256rmkz = 13336, X86_VPSRLVQZ256rr = 13337, X86_VPSRLVQZ256rrk = 13338, X86_VPSRLVQZ256rrkz = 13339, X86_VPSRLVQZrm = 13340, X86_VPSRLVQZrmb = 13341, X86_VPSRLVQZrmbk = 13342, X86_VPSRLVQZrmbkz = 13343, X86_VPSRLVQZrmk = 13344, X86_VPSRLVQZrmkz = 13345, X86_VPSRLVQZrr = 13346, X86_VPSRLVQZrrk = 13347, X86_VPSRLVQZrrkz = 13348, X86_VPSRLVQrm = 13349, X86_VPSRLVQrr = 13350, X86_VPSRLVWZ128rm = 13351, X86_VPSRLVWZ128rmk = 13352, X86_VPSRLVWZ128rmkz = 13353, X86_VPSRLVWZ128rr = 13354, X86_VPSRLVWZ128rrk = 13355, X86_VPSRLVWZ128rrkz = 13356, X86_VPSRLVWZ256rm = 13357, X86_VPSRLVWZ256rmk = 13358, X86_VPSRLVWZ256rmkz = 13359, X86_VPSRLVWZ256rr = 13360, X86_VPSRLVWZ256rrk = 13361, X86_VPSRLVWZ256rrkz = 13362, X86_VPSRLVWZrm = 13363, X86_VPSRLVWZrmk = 13364, X86_VPSRLVWZrmkz = 13365, X86_VPSRLVWZrr = 13366, X86_VPSRLVWZrrk = 13367, X86_VPSRLVWZrrkz = 13368, X86_VPSRLWYri = 13369, X86_VPSRLWYrm = 13370, X86_VPSRLWYrr = 13371, X86_VPSRLWZ128mi = 13372, X86_VPSRLWZ128mik = 13373, X86_VPSRLWZ128mikz = 13374, X86_VPSRLWZ128ri = 13375, X86_VPSRLWZ128rik = 13376, X86_VPSRLWZ128rikz = 13377, X86_VPSRLWZ128rm = 13378, X86_VPSRLWZ128rmk = 13379, X86_VPSRLWZ128rmkz = 13380, X86_VPSRLWZ128rr = 13381, X86_VPSRLWZ128rrk = 13382, X86_VPSRLWZ128rrkz = 13383, X86_VPSRLWZ256mi = 13384, X86_VPSRLWZ256mik = 13385, X86_VPSRLWZ256mikz = 13386, X86_VPSRLWZ256ri = 13387, X86_VPSRLWZ256rik = 13388, X86_VPSRLWZ256rikz = 13389, X86_VPSRLWZ256rm = 13390, X86_VPSRLWZ256rmk = 13391, X86_VPSRLWZ256rmkz = 13392, X86_VPSRLWZ256rr = 13393, X86_VPSRLWZ256rrk = 13394, X86_VPSRLWZ256rrkz = 13395, X86_VPSRLWZmi = 13396, X86_VPSRLWZmik = 13397, X86_VPSRLWZmikz = 13398, X86_VPSRLWZri = 13399, X86_VPSRLWZrik = 13400, X86_VPSRLWZrikz = 13401, X86_VPSRLWZrm = 13402, X86_VPSRLWZrmk = 13403, X86_VPSRLWZrmkz = 13404, X86_VPSRLWZrr = 13405, X86_VPSRLWZrrk = 13406, X86_VPSRLWZrrkz = 13407, X86_VPSRLWri = 13408, X86_VPSRLWrm = 13409, X86_VPSRLWrr = 13410, X86_VPSUBBYrm = 13411, X86_VPSUBBYrr = 13412, X86_VPSUBBZ128rm = 13413, X86_VPSUBBZ128rmk = 13414, X86_VPSUBBZ128rmkz = 13415, X86_VPSUBBZ128rr = 13416, X86_VPSUBBZ128rrk = 13417, X86_VPSUBBZ128rrkz = 13418, X86_VPSUBBZ256rm = 13419, X86_VPSUBBZ256rmk = 13420, X86_VPSUBBZ256rmkz = 13421, X86_VPSUBBZ256rr = 13422, X86_VPSUBBZ256rrk = 13423, X86_VPSUBBZ256rrkz = 13424, X86_VPSUBBZrm = 13425, X86_VPSUBBZrmk = 13426, X86_VPSUBBZrmkz = 13427, X86_VPSUBBZrr = 13428, X86_VPSUBBZrrk = 13429, X86_VPSUBBZrrkz = 13430, X86_VPSUBBrm = 13431, X86_VPSUBBrr = 13432, X86_VPSUBDYrm = 13433, X86_VPSUBDYrr = 13434, X86_VPSUBDZ128rm = 13435, X86_VPSUBDZ128rmb = 13436, X86_VPSUBDZ128rmbk = 13437, X86_VPSUBDZ128rmbkz = 13438, X86_VPSUBDZ128rmk = 13439, X86_VPSUBDZ128rmkz = 13440, X86_VPSUBDZ128rr = 13441, X86_VPSUBDZ128rrk = 13442, X86_VPSUBDZ128rrkz = 13443, X86_VPSUBDZ256rm = 13444, X86_VPSUBDZ256rmb = 13445, X86_VPSUBDZ256rmbk = 13446, X86_VPSUBDZ256rmbkz = 13447, X86_VPSUBDZ256rmk = 13448, X86_VPSUBDZ256rmkz = 13449, X86_VPSUBDZ256rr = 13450, X86_VPSUBDZ256rrk = 13451, X86_VPSUBDZ256rrkz = 13452, X86_VPSUBDZrm = 13453, X86_VPSUBDZrmb = 13454, X86_VPSUBDZrmbk = 13455, X86_VPSUBDZrmbkz = 13456, X86_VPSUBDZrmk = 13457, X86_VPSUBDZrmkz = 13458, X86_VPSUBDZrr = 13459, X86_VPSUBDZrrk = 13460, X86_VPSUBDZrrkz = 13461, X86_VPSUBDrm = 13462, X86_VPSUBDrr = 13463, X86_VPSUBQYrm = 13464, X86_VPSUBQYrr = 13465, X86_VPSUBQZ128rm = 13466, X86_VPSUBQZ128rmb = 13467, X86_VPSUBQZ128rmbk = 13468, X86_VPSUBQZ128rmbkz = 13469, X86_VPSUBQZ128rmk = 13470, X86_VPSUBQZ128rmkz = 13471, X86_VPSUBQZ128rr = 13472, X86_VPSUBQZ128rrk = 13473, X86_VPSUBQZ128rrkz = 13474, X86_VPSUBQZ256rm = 13475, X86_VPSUBQZ256rmb = 13476, X86_VPSUBQZ256rmbk = 13477, X86_VPSUBQZ256rmbkz = 13478, X86_VPSUBQZ256rmk = 13479, X86_VPSUBQZ256rmkz = 13480, X86_VPSUBQZ256rr = 13481, X86_VPSUBQZ256rrk = 13482, X86_VPSUBQZ256rrkz = 13483, X86_VPSUBQZrm = 13484, X86_VPSUBQZrmb = 13485, X86_VPSUBQZrmbk = 13486, X86_VPSUBQZrmbkz = 13487, X86_VPSUBQZrmk = 13488, X86_VPSUBQZrmkz = 13489, X86_VPSUBQZrr = 13490, X86_VPSUBQZrrk = 13491, X86_VPSUBQZrrkz = 13492, X86_VPSUBQrm = 13493, X86_VPSUBQrr = 13494, X86_VPSUBSBYrm = 13495, X86_VPSUBSBYrr = 13496, X86_VPSUBSBZ128rm = 13497, X86_VPSUBSBZ128rmk = 13498, X86_VPSUBSBZ128rmkz = 13499, X86_VPSUBSBZ128rr = 13500, X86_VPSUBSBZ128rrk = 13501, X86_VPSUBSBZ128rrkz = 13502, X86_VPSUBSBZ256rm = 13503, X86_VPSUBSBZ256rmk = 13504, X86_VPSUBSBZ256rmkz = 13505, X86_VPSUBSBZ256rr = 13506, X86_VPSUBSBZ256rrk = 13507, X86_VPSUBSBZ256rrkz = 13508, X86_VPSUBSBZrm = 13509, X86_VPSUBSBZrmk = 13510, X86_VPSUBSBZrmkz = 13511, X86_VPSUBSBZrr = 13512, X86_VPSUBSBZrrk = 13513, X86_VPSUBSBZrrkz = 13514, X86_VPSUBSBrm = 13515, X86_VPSUBSBrr = 13516, X86_VPSUBSWYrm = 13517, X86_VPSUBSWYrr = 13518, X86_VPSUBSWZ128rm = 13519, X86_VPSUBSWZ128rmk = 13520, X86_VPSUBSWZ128rmkz = 13521, X86_VPSUBSWZ128rr = 13522, X86_VPSUBSWZ128rrk = 13523, X86_VPSUBSWZ128rrkz = 13524, X86_VPSUBSWZ256rm = 13525, X86_VPSUBSWZ256rmk = 13526, X86_VPSUBSWZ256rmkz = 13527, X86_VPSUBSWZ256rr = 13528, X86_VPSUBSWZ256rrk = 13529, X86_VPSUBSWZ256rrkz = 13530, X86_VPSUBSWZrm = 13531, X86_VPSUBSWZrmk = 13532, X86_VPSUBSWZrmkz = 13533, X86_VPSUBSWZrr = 13534, X86_VPSUBSWZrrk = 13535, X86_VPSUBSWZrrkz = 13536, X86_VPSUBSWrm = 13537, X86_VPSUBSWrr = 13538, X86_VPSUBUSBYrm = 13539, X86_VPSUBUSBYrr = 13540, X86_VPSUBUSBZ128rm = 13541, X86_VPSUBUSBZ128rmk = 13542, X86_VPSUBUSBZ128rmkz = 13543, X86_VPSUBUSBZ128rr = 13544, X86_VPSUBUSBZ128rrk = 13545, X86_VPSUBUSBZ128rrkz = 13546, X86_VPSUBUSBZ256rm = 13547, X86_VPSUBUSBZ256rmk = 13548, X86_VPSUBUSBZ256rmkz = 13549, X86_VPSUBUSBZ256rr = 13550, X86_VPSUBUSBZ256rrk = 13551, X86_VPSUBUSBZ256rrkz = 13552, X86_VPSUBUSBZrm = 13553, X86_VPSUBUSBZrmk = 13554, X86_VPSUBUSBZrmkz = 13555, X86_VPSUBUSBZrr = 13556, X86_VPSUBUSBZrrk = 13557, X86_VPSUBUSBZrrkz = 13558, X86_VPSUBUSBrm = 13559, X86_VPSUBUSBrr = 13560, X86_VPSUBUSWYrm = 13561, X86_VPSUBUSWYrr = 13562, X86_VPSUBUSWZ128rm = 13563, X86_VPSUBUSWZ128rmk = 13564, X86_VPSUBUSWZ128rmkz = 13565, X86_VPSUBUSWZ128rr = 13566, X86_VPSUBUSWZ128rrk = 13567, X86_VPSUBUSWZ128rrkz = 13568, X86_VPSUBUSWZ256rm = 13569, X86_VPSUBUSWZ256rmk = 13570, X86_VPSUBUSWZ256rmkz = 13571, X86_VPSUBUSWZ256rr = 13572, X86_VPSUBUSWZ256rrk = 13573, X86_VPSUBUSWZ256rrkz = 13574, X86_VPSUBUSWZrm = 13575, X86_VPSUBUSWZrmk = 13576, X86_VPSUBUSWZrmkz = 13577, X86_VPSUBUSWZrr = 13578, X86_VPSUBUSWZrrk = 13579, X86_VPSUBUSWZrrkz = 13580, X86_VPSUBUSWrm = 13581, X86_VPSUBUSWrr = 13582, X86_VPSUBWYrm = 13583, X86_VPSUBWYrr = 13584, X86_VPSUBWZ128rm = 13585, X86_VPSUBWZ128rmk = 13586, X86_VPSUBWZ128rmkz = 13587, X86_VPSUBWZ128rr = 13588, X86_VPSUBWZ128rrk = 13589, X86_VPSUBWZ128rrkz = 13590, X86_VPSUBWZ256rm = 13591, X86_VPSUBWZ256rmk = 13592, X86_VPSUBWZ256rmkz = 13593, X86_VPSUBWZ256rr = 13594, X86_VPSUBWZ256rrk = 13595, X86_VPSUBWZ256rrkz = 13596, X86_VPSUBWZrm = 13597, X86_VPSUBWZrmk = 13598, X86_VPSUBWZrmkz = 13599, X86_VPSUBWZrr = 13600, X86_VPSUBWZrrk = 13601, X86_VPSUBWZrrkz = 13602, X86_VPSUBWrm = 13603, X86_VPSUBWrr = 13604, X86_VPTERNLOGDZ128rmbi = 13605, X86_VPTERNLOGDZ128rmbik = 13606, X86_VPTERNLOGDZ128rmbikz = 13607, X86_VPTERNLOGDZ128rmi = 13608, X86_VPTERNLOGDZ128rmik = 13609, X86_VPTERNLOGDZ128rmikz = 13610, X86_VPTERNLOGDZ128rri = 13611, X86_VPTERNLOGDZ128rrik = 13612, X86_VPTERNLOGDZ128rrikz = 13613, X86_VPTERNLOGDZ256rmbi = 13614, X86_VPTERNLOGDZ256rmbik = 13615, X86_VPTERNLOGDZ256rmbikz = 13616, X86_VPTERNLOGDZ256rmi = 13617, X86_VPTERNLOGDZ256rmik = 13618, X86_VPTERNLOGDZ256rmikz = 13619, X86_VPTERNLOGDZ256rri = 13620, X86_VPTERNLOGDZ256rrik = 13621, X86_VPTERNLOGDZ256rrikz = 13622, X86_VPTERNLOGDZrmbi = 13623, X86_VPTERNLOGDZrmbik = 13624, X86_VPTERNLOGDZrmbikz = 13625, X86_VPTERNLOGDZrmi = 13626, X86_VPTERNLOGDZrmik = 13627, X86_VPTERNLOGDZrmikz = 13628, X86_VPTERNLOGDZrri = 13629, X86_VPTERNLOGDZrrik = 13630, X86_VPTERNLOGDZrrikz = 13631, X86_VPTERNLOGQZ128rmbi = 13632, X86_VPTERNLOGQZ128rmbik = 13633, X86_VPTERNLOGQZ128rmbikz = 13634, X86_VPTERNLOGQZ128rmi = 13635, X86_VPTERNLOGQZ128rmik = 13636, X86_VPTERNLOGQZ128rmikz = 13637, X86_VPTERNLOGQZ128rri = 13638, X86_VPTERNLOGQZ128rrik = 13639, X86_VPTERNLOGQZ128rrikz = 13640, X86_VPTERNLOGQZ256rmbi = 13641, X86_VPTERNLOGQZ256rmbik = 13642, X86_VPTERNLOGQZ256rmbikz = 13643, X86_VPTERNLOGQZ256rmi = 13644, X86_VPTERNLOGQZ256rmik = 13645, X86_VPTERNLOGQZ256rmikz = 13646, X86_VPTERNLOGQZ256rri = 13647, X86_VPTERNLOGQZ256rrik = 13648, X86_VPTERNLOGQZ256rrikz = 13649, X86_VPTERNLOGQZrmbi = 13650, X86_VPTERNLOGQZrmbik = 13651, X86_VPTERNLOGQZrmbikz = 13652, X86_VPTERNLOGQZrmi = 13653, X86_VPTERNLOGQZrmik = 13654, X86_VPTERNLOGQZrmikz = 13655, X86_VPTERNLOGQZrri = 13656, X86_VPTERNLOGQZrrik = 13657, X86_VPTERNLOGQZrrikz = 13658, X86_VPTESTMBZ128rm = 13659, X86_VPTESTMBZ128rmk = 13660, X86_VPTESTMBZ128rr = 13661, X86_VPTESTMBZ128rrk = 13662, X86_VPTESTMBZ256rm = 13663, X86_VPTESTMBZ256rmk = 13664, X86_VPTESTMBZ256rr = 13665, X86_VPTESTMBZ256rrk = 13666, X86_VPTESTMBZrm = 13667, X86_VPTESTMBZrmk = 13668, X86_VPTESTMBZrr = 13669, X86_VPTESTMBZrrk = 13670, X86_VPTESTMDZ128rm = 13671, X86_VPTESTMDZ128rmb = 13672, X86_VPTESTMDZ128rmbk = 13673, X86_VPTESTMDZ128rmk = 13674, X86_VPTESTMDZ128rr = 13675, X86_VPTESTMDZ128rrk = 13676, X86_VPTESTMDZ256rm = 13677, X86_VPTESTMDZ256rmb = 13678, X86_VPTESTMDZ256rmbk = 13679, X86_VPTESTMDZ256rmk = 13680, X86_VPTESTMDZ256rr = 13681, X86_VPTESTMDZ256rrk = 13682, X86_VPTESTMDZrm = 13683, X86_VPTESTMDZrmb = 13684, X86_VPTESTMDZrmbk = 13685, X86_VPTESTMDZrmk = 13686, X86_VPTESTMDZrr = 13687, X86_VPTESTMDZrrk = 13688, X86_VPTESTMQZ128rm = 13689, X86_VPTESTMQZ128rmb = 13690, X86_VPTESTMQZ128rmbk = 13691, X86_VPTESTMQZ128rmk = 13692, X86_VPTESTMQZ128rr = 13693, X86_VPTESTMQZ128rrk = 13694, X86_VPTESTMQZ256rm = 13695, X86_VPTESTMQZ256rmb = 13696, X86_VPTESTMQZ256rmbk = 13697, X86_VPTESTMQZ256rmk = 13698, X86_VPTESTMQZ256rr = 13699, X86_VPTESTMQZ256rrk = 13700, X86_VPTESTMQZrm = 13701, X86_VPTESTMQZrmb = 13702, X86_VPTESTMQZrmbk = 13703, X86_VPTESTMQZrmk = 13704, X86_VPTESTMQZrr = 13705, X86_VPTESTMQZrrk = 13706, X86_VPTESTMWZ128rm = 13707, X86_VPTESTMWZ128rmk = 13708, X86_VPTESTMWZ128rr = 13709, X86_VPTESTMWZ128rrk = 13710, X86_VPTESTMWZ256rm = 13711, X86_VPTESTMWZ256rmk = 13712, X86_VPTESTMWZ256rr = 13713, X86_VPTESTMWZ256rrk = 13714, X86_VPTESTMWZrm = 13715, X86_VPTESTMWZrmk = 13716, X86_VPTESTMWZrr = 13717, X86_VPTESTMWZrrk = 13718, X86_VPTESTNMBZ128rm = 13719, X86_VPTESTNMBZ128rmk = 13720, X86_VPTESTNMBZ128rr = 13721, X86_VPTESTNMBZ128rrk = 13722, X86_VPTESTNMBZ256rm = 13723, X86_VPTESTNMBZ256rmk = 13724, X86_VPTESTNMBZ256rr = 13725, X86_VPTESTNMBZ256rrk = 13726, X86_VPTESTNMBZrm = 13727, X86_VPTESTNMBZrmk = 13728, X86_VPTESTNMBZrr = 13729, X86_VPTESTNMBZrrk = 13730, X86_VPTESTNMDZ128rm = 13731, X86_VPTESTNMDZ128rmb = 13732, X86_VPTESTNMDZ128rmbk = 13733, X86_VPTESTNMDZ128rmk = 13734, X86_VPTESTNMDZ128rr = 13735, X86_VPTESTNMDZ128rrk = 13736, X86_VPTESTNMDZ256rm = 13737, X86_VPTESTNMDZ256rmb = 13738, X86_VPTESTNMDZ256rmbk = 13739, X86_VPTESTNMDZ256rmk = 13740, X86_VPTESTNMDZ256rr = 13741, X86_VPTESTNMDZ256rrk = 13742, X86_VPTESTNMDZrm = 13743, X86_VPTESTNMDZrmb = 13744, X86_VPTESTNMDZrmbk = 13745, X86_VPTESTNMDZrmk = 13746, X86_VPTESTNMDZrr = 13747, X86_VPTESTNMDZrrk = 13748, X86_VPTESTNMQZ128rm = 13749, X86_VPTESTNMQZ128rmb = 13750, X86_VPTESTNMQZ128rmbk = 13751, X86_VPTESTNMQZ128rmk = 13752, X86_VPTESTNMQZ128rr = 13753, X86_VPTESTNMQZ128rrk = 13754, X86_VPTESTNMQZ256rm = 13755, X86_VPTESTNMQZ256rmb = 13756, X86_VPTESTNMQZ256rmbk = 13757, X86_VPTESTNMQZ256rmk = 13758, X86_VPTESTNMQZ256rr = 13759, X86_VPTESTNMQZ256rrk = 13760, X86_VPTESTNMQZrm = 13761, X86_VPTESTNMQZrmb = 13762, X86_VPTESTNMQZrmbk = 13763, X86_VPTESTNMQZrmk = 13764, X86_VPTESTNMQZrr = 13765, X86_VPTESTNMQZrrk = 13766, X86_VPTESTNMWZ128rm = 13767, X86_VPTESTNMWZ128rmk = 13768, X86_VPTESTNMWZ128rr = 13769, X86_VPTESTNMWZ128rrk = 13770, X86_VPTESTNMWZ256rm = 13771, X86_VPTESTNMWZ256rmk = 13772, X86_VPTESTNMWZ256rr = 13773, X86_VPTESTNMWZ256rrk = 13774, X86_VPTESTNMWZrm = 13775, X86_VPTESTNMWZrmk = 13776, X86_VPTESTNMWZrr = 13777, X86_VPTESTNMWZrrk = 13778, X86_VPTESTYrm = 13779, X86_VPTESTYrr = 13780, X86_VPTESTrm = 13781, X86_VPTESTrr = 13782, X86_VPUNPCKHBWYrm = 13783, X86_VPUNPCKHBWYrr = 13784, X86_VPUNPCKHBWZ128rm = 13785, X86_VPUNPCKHBWZ128rmk = 13786, X86_VPUNPCKHBWZ128rmkz = 13787, X86_VPUNPCKHBWZ128rr = 13788, X86_VPUNPCKHBWZ128rrk = 13789, X86_VPUNPCKHBWZ128rrkz = 13790, X86_VPUNPCKHBWZ256rm = 13791, X86_VPUNPCKHBWZ256rmk = 13792, X86_VPUNPCKHBWZ256rmkz = 13793, X86_VPUNPCKHBWZ256rr = 13794, X86_VPUNPCKHBWZ256rrk = 13795, X86_VPUNPCKHBWZ256rrkz = 13796, X86_VPUNPCKHBWZrm = 13797, X86_VPUNPCKHBWZrmk = 13798, X86_VPUNPCKHBWZrmkz = 13799, X86_VPUNPCKHBWZrr = 13800, X86_VPUNPCKHBWZrrk = 13801, X86_VPUNPCKHBWZrrkz = 13802, X86_VPUNPCKHBWrm = 13803, X86_VPUNPCKHBWrr = 13804, X86_VPUNPCKHDQYrm = 13805, X86_VPUNPCKHDQYrr = 13806, X86_VPUNPCKHDQZ128rm = 13807, X86_VPUNPCKHDQZ128rmb = 13808, X86_VPUNPCKHDQZ128rmbk = 13809, X86_VPUNPCKHDQZ128rmbkz = 13810, X86_VPUNPCKHDQZ128rmk = 13811, X86_VPUNPCKHDQZ128rmkz = 13812, X86_VPUNPCKHDQZ128rr = 13813, X86_VPUNPCKHDQZ128rrk = 13814, X86_VPUNPCKHDQZ128rrkz = 13815, X86_VPUNPCKHDQZ256rm = 13816, X86_VPUNPCKHDQZ256rmb = 13817, X86_VPUNPCKHDQZ256rmbk = 13818, X86_VPUNPCKHDQZ256rmbkz = 13819, X86_VPUNPCKHDQZ256rmk = 13820, X86_VPUNPCKHDQZ256rmkz = 13821, X86_VPUNPCKHDQZ256rr = 13822, X86_VPUNPCKHDQZ256rrk = 13823, X86_VPUNPCKHDQZ256rrkz = 13824, X86_VPUNPCKHDQZrm = 13825, X86_VPUNPCKHDQZrmb = 13826, X86_VPUNPCKHDQZrmbk = 13827, X86_VPUNPCKHDQZrmbkz = 13828, X86_VPUNPCKHDQZrmk = 13829, X86_VPUNPCKHDQZrmkz = 13830, X86_VPUNPCKHDQZrr = 13831, X86_VPUNPCKHDQZrrk = 13832, X86_VPUNPCKHDQZrrkz = 13833, X86_VPUNPCKHDQrm = 13834, X86_VPUNPCKHDQrr = 13835, X86_VPUNPCKHQDQYrm = 13836, X86_VPUNPCKHQDQYrr = 13837, X86_VPUNPCKHQDQZ128rm = 13838, X86_VPUNPCKHQDQZ128rmb = 13839, X86_VPUNPCKHQDQZ128rmbk = 13840, X86_VPUNPCKHQDQZ128rmbkz = 13841, X86_VPUNPCKHQDQZ128rmk = 13842, X86_VPUNPCKHQDQZ128rmkz = 13843, X86_VPUNPCKHQDQZ128rr = 13844, X86_VPUNPCKHQDQZ128rrk = 13845, X86_VPUNPCKHQDQZ128rrkz = 13846, X86_VPUNPCKHQDQZ256rm = 13847, X86_VPUNPCKHQDQZ256rmb = 13848, X86_VPUNPCKHQDQZ256rmbk = 13849, X86_VPUNPCKHQDQZ256rmbkz = 13850, X86_VPUNPCKHQDQZ256rmk = 13851, X86_VPUNPCKHQDQZ256rmkz = 13852, X86_VPUNPCKHQDQZ256rr = 13853, X86_VPUNPCKHQDQZ256rrk = 13854, X86_VPUNPCKHQDQZ256rrkz = 13855, X86_VPUNPCKHQDQZrm = 13856, X86_VPUNPCKHQDQZrmb = 13857, X86_VPUNPCKHQDQZrmbk = 13858, X86_VPUNPCKHQDQZrmbkz = 13859, X86_VPUNPCKHQDQZrmk = 13860, X86_VPUNPCKHQDQZrmkz = 13861, X86_VPUNPCKHQDQZrr = 13862, X86_VPUNPCKHQDQZrrk = 13863, X86_VPUNPCKHQDQZrrkz = 13864, X86_VPUNPCKHQDQrm = 13865, X86_VPUNPCKHQDQrr = 13866, X86_VPUNPCKHWDYrm = 13867, X86_VPUNPCKHWDYrr = 13868, X86_VPUNPCKHWDZ128rm = 13869, X86_VPUNPCKHWDZ128rmk = 13870, X86_VPUNPCKHWDZ128rmkz = 13871, X86_VPUNPCKHWDZ128rr = 13872, X86_VPUNPCKHWDZ128rrk = 13873, X86_VPUNPCKHWDZ128rrkz = 13874, X86_VPUNPCKHWDZ256rm = 13875, X86_VPUNPCKHWDZ256rmk = 13876, X86_VPUNPCKHWDZ256rmkz = 13877, X86_VPUNPCKHWDZ256rr = 13878, X86_VPUNPCKHWDZ256rrk = 13879, X86_VPUNPCKHWDZ256rrkz = 13880, X86_VPUNPCKHWDZrm = 13881, X86_VPUNPCKHWDZrmk = 13882, X86_VPUNPCKHWDZrmkz = 13883, X86_VPUNPCKHWDZrr = 13884, X86_VPUNPCKHWDZrrk = 13885, X86_VPUNPCKHWDZrrkz = 13886, X86_VPUNPCKHWDrm = 13887, X86_VPUNPCKHWDrr = 13888, X86_VPUNPCKLBWYrm = 13889, X86_VPUNPCKLBWYrr = 13890, X86_VPUNPCKLBWZ128rm = 13891, X86_VPUNPCKLBWZ128rmk = 13892, X86_VPUNPCKLBWZ128rmkz = 13893, X86_VPUNPCKLBWZ128rr = 13894, X86_VPUNPCKLBWZ128rrk = 13895, X86_VPUNPCKLBWZ128rrkz = 13896, X86_VPUNPCKLBWZ256rm = 13897, X86_VPUNPCKLBWZ256rmk = 13898, X86_VPUNPCKLBWZ256rmkz = 13899, X86_VPUNPCKLBWZ256rr = 13900, X86_VPUNPCKLBWZ256rrk = 13901, X86_VPUNPCKLBWZ256rrkz = 13902, X86_VPUNPCKLBWZrm = 13903, X86_VPUNPCKLBWZrmk = 13904, X86_VPUNPCKLBWZrmkz = 13905, X86_VPUNPCKLBWZrr = 13906, X86_VPUNPCKLBWZrrk = 13907, X86_VPUNPCKLBWZrrkz = 13908, X86_VPUNPCKLBWrm = 13909, X86_VPUNPCKLBWrr = 13910, X86_VPUNPCKLDQYrm = 13911, X86_VPUNPCKLDQYrr = 13912, X86_VPUNPCKLDQZ128rm = 13913, X86_VPUNPCKLDQZ128rmb = 13914, X86_VPUNPCKLDQZ128rmbk = 13915, X86_VPUNPCKLDQZ128rmbkz = 13916, X86_VPUNPCKLDQZ128rmk = 13917, X86_VPUNPCKLDQZ128rmkz = 13918, X86_VPUNPCKLDQZ128rr = 13919, X86_VPUNPCKLDQZ128rrk = 13920, X86_VPUNPCKLDQZ128rrkz = 13921, X86_VPUNPCKLDQZ256rm = 13922, X86_VPUNPCKLDQZ256rmb = 13923, X86_VPUNPCKLDQZ256rmbk = 13924, X86_VPUNPCKLDQZ256rmbkz = 13925, X86_VPUNPCKLDQZ256rmk = 13926, X86_VPUNPCKLDQZ256rmkz = 13927, X86_VPUNPCKLDQZ256rr = 13928, X86_VPUNPCKLDQZ256rrk = 13929, X86_VPUNPCKLDQZ256rrkz = 13930, X86_VPUNPCKLDQZrm = 13931, X86_VPUNPCKLDQZrmb = 13932, X86_VPUNPCKLDQZrmbk = 13933, X86_VPUNPCKLDQZrmbkz = 13934, X86_VPUNPCKLDQZrmk = 13935, X86_VPUNPCKLDQZrmkz = 13936, X86_VPUNPCKLDQZrr = 13937, X86_VPUNPCKLDQZrrk = 13938, X86_VPUNPCKLDQZrrkz = 13939, X86_VPUNPCKLDQrm = 13940, X86_VPUNPCKLDQrr = 13941, X86_VPUNPCKLQDQYrm = 13942, X86_VPUNPCKLQDQYrr = 13943, X86_VPUNPCKLQDQZ128rm = 13944, X86_VPUNPCKLQDQZ128rmb = 13945, X86_VPUNPCKLQDQZ128rmbk = 13946, X86_VPUNPCKLQDQZ128rmbkz = 13947, X86_VPUNPCKLQDQZ128rmk = 13948, X86_VPUNPCKLQDQZ128rmkz = 13949, X86_VPUNPCKLQDQZ128rr = 13950, X86_VPUNPCKLQDQZ128rrk = 13951, X86_VPUNPCKLQDQZ128rrkz = 13952, X86_VPUNPCKLQDQZ256rm = 13953, X86_VPUNPCKLQDQZ256rmb = 13954, X86_VPUNPCKLQDQZ256rmbk = 13955, X86_VPUNPCKLQDQZ256rmbkz = 13956, X86_VPUNPCKLQDQZ256rmk = 13957, X86_VPUNPCKLQDQZ256rmkz = 13958, X86_VPUNPCKLQDQZ256rr = 13959, X86_VPUNPCKLQDQZ256rrk = 13960, X86_VPUNPCKLQDQZ256rrkz = 13961, X86_VPUNPCKLQDQZrm = 13962, X86_VPUNPCKLQDQZrmb = 13963, X86_VPUNPCKLQDQZrmbk = 13964, X86_VPUNPCKLQDQZrmbkz = 13965, X86_VPUNPCKLQDQZrmk = 13966, X86_VPUNPCKLQDQZrmkz = 13967, X86_VPUNPCKLQDQZrr = 13968, X86_VPUNPCKLQDQZrrk = 13969, X86_VPUNPCKLQDQZrrkz = 13970, X86_VPUNPCKLQDQrm = 13971, X86_VPUNPCKLQDQrr = 13972, X86_VPUNPCKLWDYrm = 13973, X86_VPUNPCKLWDYrr = 13974, X86_VPUNPCKLWDZ128rm = 13975, X86_VPUNPCKLWDZ128rmk = 13976, X86_VPUNPCKLWDZ128rmkz = 13977, X86_VPUNPCKLWDZ128rr = 13978, X86_VPUNPCKLWDZ128rrk = 13979, X86_VPUNPCKLWDZ128rrkz = 13980, X86_VPUNPCKLWDZ256rm = 13981, X86_VPUNPCKLWDZ256rmk = 13982, X86_VPUNPCKLWDZ256rmkz = 13983, X86_VPUNPCKLWDZ256rr = 13984, X86_VPUNPCKLWDZ256rrk = 13985, X86_VPUNPCKLWDZ256rrkz = 13986, X86_VPUNPCKLWDZrm = 13987, X86_VPUNPCKLWDZrmk = 13988, X86_VPUNPCKLWDZrmkz = 13989, X86_VPUNPCKLWDZrr = 13990, X86_VPUNPCKLWDZrrk = 13991, X86_VPUNPCKLWDZrrkz = 13992, X86_VPUNPCKLWDrm = 13993, X86_VPUNPCKLWDrr = 13994, X86_VPXORDZ128rm = 13995, X86_VPXORDZ128rmb = 13996, X86_VPXORDZ128rmbk = 13997, X86_VPXORDZ128rmbkz = 13998, X86_VPXORDZ128rmk = 13999, X86_VPXORDZ128rmkz = 14000, X86_VPXORDZ128rr = 14001, X86_VPXORDZ128rrk = 14002, X86_VPXORDZ128rrkz = 14003, X86_VPXORDZ256rm = 14004, X86_VPXORDZ256rmb = 14005, X86_VPXORDZ256rmbk = 14006, X86_VPXORDZ256rmbkz = 14007, X86_VPXORDZ256rmk = 14008, X86_VPXORDZ256rmkz = 14009, X86_VPXORDZ256rr = 14010, X86_VPXORDZ256rrk = 14011, X86_VPXORDZ256rrkz = 14012, X86_VPXORDZrm = 14013, X86_VPXORDZrmb = 14014, X86_VPXORDZrmbk = 14015, X86_VPXORDZrmbkz = 14016, X86_VPXORDZrmk = 14017, X86_VPXORDZrmkz = 14018, X86_VPXORDZrr = 14019, X86_VPXORDZrrk = 14020, X86_VPXORDZrrkz = 14021, X86_VPXORQZ128rm = 14022, X86_VPXORQZ128rmb = 14023, X86_VPXORQZ128rmbk = 14024, X86_VPXORQZ128rmbkz = 14025, X86_VPXORQZ128rmk = 14026, X86_VPXORQZ128rmkz = 14027, X86_VPXORQZ128rr = 14028, X86_VPXORQZ128rrk = 14029, X86_VPXORQZ128rrkz = 14030, X86_VPXORQZ256rm = 14031, X86_VPXORQZ256rmb = 14032, X86_VPXORQZ256rmbk = 14033, X86_VPXORQZ256rmbkz = 14034, X86_VPXORQZ256rmk = 14035, X86_VPXORQZ256rmkz = 14036, X86_VPXORQZ256rr = 14037, X86_VPXORQZ256rrk = 14038, X86_VPXORQZ256rrkz = 14039, X86_VPXORQZrm = 14040, X86_VPXORQZrmb = 14041, X86_VPXORQZrmbk = 14042, X86_VPXORQZrmbkz = 14043, X86_VPXORQZrmk = 14044, X86_VPXORQZrmkz = 14045, X86_VPXORQZrr = 14046, X86_VPXORQZrrk = 14047, X86_VPXORQZrrkz = 14048, X86_VPXORYrm = 14049, X86_VPXORYrr = 14050, X86_VPXORrm = 14051, X86_VPXORrr = 14052, X86_VRANGEPDZ128rmbi = 14053, X86_VRANGEPDZ128rmbik = 14054, X86_VRANGEPDZ128rmbikz = 14055, X86_VRANGEPDZ128rmi = 14056, X86_VRANGEPDZ128rmik = 14057, X86_VRANGEPDZ128rmikz = 14058, X86_VRANGEPDZ128rri = 14059, X86_VRANGEPDZ128rrik = 14060, X86_VRANGEPDZ128rrikz = 14061, X86_VRANGEPDZ256rmbi = 14062, X86_VRANGEPDZ256rmbik = 14063, X86_VRANGEPDZ256rmbikz = 14064, X86_VRANGEPDZ256rmi = 14065, X86_VRANGEPDZ256rmik = 14066, X86_VRANGEPDZ256rmikz = 14067, X86_VRANGEPDZ256rri = 14068, X86_VRANGEPDZ256rrik = 14069, X86_VRANGEPDZ256rrikz = 14070, X86_VRANGEPDZrmbi = 14071, X86_VRANGEPDZrmbik = 14072, X86_VRANGEPDZrmbikz = 14073, X86_VRANGEPDZrmi = 14074, X86_VRANGEPDZrmik = 14075, X86_VRANGEPDZrmikz = 14076, X86_VRANGEPDZrri = 14077, X86_VRANGEPDZrrib = 14078, X86_VRANGEPDZrribk = 14079, X86_VRANGEPDZrribkz = 14080, X86_VRANGEPDZrrik = 14081, X86_VRANGEPDZrrikz = 14082, X86_VRANGEPSZ128rmbi = 14083, X86_VRANGEPSZ128rmbik = 14084, X86_VRANGEPSZ128rmbikz = 14085, X86_VRANGEPSZ128rmi = 14086, X86_VRANGEPSZ128rmik = 14087, X86_VRANGEPSZ128rmikz = 14088, X86_VRANGEPSZ128rri = 14089, X86_VRANGEPSZ128rrik = 14090, X86_VRANGEPSZ128rrikz = 14091, X86_VRANGEPSZ256rmbi = 14092, X86_VRANGEPSZ256rmbik = 14093, X86_VRANGEPSZ256rmbikz = 14094, X86_VRANGEPSZ256rmi = 14095, X86_VRANGEPSZ256rmik = 14096, X86_VRANGEPSZ256rmikz = 14097, X86_VRANGEPSZ256rri = 14098, X86_VRANGEPSZ256rrik = 14099, X86_VRANGEPSZ256rrikz = 14100, X86_VRANGEPSZrmbi = 14101, X86_VRANGEPSZrmbik = 14102, X86_VRANGEPSZrmbikz = 14103, X86_VRANGEPSZrmi = 14104, X86_VRANGEPSZrmik = 14105, X86_VRANGEPSZrmikz = 14106, X86_VRANGEPSZrri = 14107, X86_VRANGEPSZrrib = 14108, X86_VRANGEPSZrribk = 14109, X86_VRANGEPSZrribkz = 14110, X86_VRANGEPSZrrik = 14111, X86_VRANGEPSZrrikz = 14112, X86_VRANGESDZrmi = 14113, X86_VRANGESDZrmik = 14114, X86_VRANGESDZrmikz = 14115, X86_VRANGESDZrri = 14116, X86_VRANGESDZrrib = 14117, X86_VRANGESDZrribk = 14118, X86_VRANGESDZrribkz = 14119, X86_VRANGESDZrrik = 14120, X86_VRANGESDZrrikz = 14121, X86_VRANGESSZrmi = 14122, X86_VRANGESSZrmik = 14123, X86_VRANGESSZrmikz = 14124, X86_VRANGESSZrri = 14125, X86_VRANGESSZrrib = 14126, X86_VRANGESSZrribk = 14127, X86_VRANGESSZrribkz = 14128, X86_VRANGESSZrrik = 14129, X86_VRANGESSZrrikz = 14130, X86_VRCP14PDZ128m = 14131, X86_VRCP14PDZ128mb = 14132, X86_VRCP14PDZ128mbk = 14133, X86_VRCP14PDZ128mbkz = 14134, X86_VRCP14PDZ128mk = 14135, X86_VRCP14PDZ128mkz = 14136, X86_VRCP14PDZ128r = 14137, X86_VRCP14PDZ128rk = 14138, X86_VRCP14PDZ128rkz = 14139, X86_VRCP14PDZ256m = 14140, X86_VRCP14PDZ256mb = 14141, X86_VRCP14PDZ256mbk = 14142, X86_VRCP14PDZ256mbkz = 14143, X86_VRCP14PDZ256mk = 14144, X86_VRCP14PDZ256mkz = 14145, X86_VRCP14PDZ256r = 14146, X86_VRCP14PDZ256rk = 14147, X86_VRCP14PDZ256rkz = 14148, X86_VRCP14PDZm = 14149, X86_VRCP14PDZmb = 14150, X86_VRCP14PDZmbk = 14151, X86_VRCP14PDZmbkz = 14152, X86_VRCP14PDZmk = 14153, X86_VRCP14PDZmkz = 14154, X86_VRCP14PDZr = 14155, X86_VRCP14PDZrk = 14156, X86_VRCP14PDZrkz = 14157, X86_VRCP14PSZ128m = 14158, X86_VRCP14PSZ128mb = 14159, X86_VRCP14PSZ128mbk = 14160, X86_VRCP14PSZ128mbkz = 14161, X86_VRCP14PSZ128mk = 14162, X86_VRCP14PSZ128mkz = 14163, X86_VRCP14PSZ128r = 14164, X86_VRCP14PSZ128rk = 14165, X86_VRCP14PSZ128rkz = 14166, X86_VRCP14PSZ256m = 14167, X86_VRCP14PSZ256mb = 14168, X86_VRCP14PSZ256mbk = 14169, X86_VRCP14PSZ256mbkz = 14170, X86_VRCP14PSZ256mk = 14171, X86_VRCP14PSZ256mkz = 14172, X86_VRCP14PSZ256r = 14173, X86_VRCP14PSZ256rk = 14174, X86_VRCP14PSZ256rkz = 14175, X86_VRCP14PSZm = 14176, X86_VRCP14PSZmb = 14177, X86_VRCP14PSZmbk = 14178, X86_VRCP14PSZmbkz = 14179, X86_VRCP14PSZmk = 14180, X86_VRCP14PSZmkz = 14181, X86_VRCP14PSZr = 14182, X86_VRCP14PSZrk = 14183, X86_VRCP14PSZrkz = 14184, X86_VRCP14SDZrm = 14185, X86_VRCP14SDZrmk = 14186, X86_VRCP14SDZrmkz = 14187, X86_VRCP14SDZrr = 14188, X86_VRCP14SDZrrk = 14189, X86_VRCP14SDZrrkz = 14190, X86_VRCP14SSZrm = 14191, X86_VRCP14SSZrmk = 14192, X86_VRCP14SSZrmkz = 14193, X86_VRCP14SSZrr = 14194, X86_VRCP14SSZrrk = 14195, X86_VRCP14SSZrrkz = 14196, X86_VRCP28PDZm = 14197, X86_VRCP28PDZmb = 14198, X86_VRCP28PDZmbk = 14199, X86_VRCP28PDZmbkz = 14200, X86_VRCP28PDZmk = 14201, X86_VRCP28PDZmkz = 14202, X86_VRCP28PDZr = 14203, X86_VRCP28PDZrb = 14204, X86_VRCP28PDZrbk = 14205, X86_VRCP28PDZrbkz = 14206, X86_VRCP28PDZrk = 14207, X86_VRCP28PDZrkz = 14208, X86_VRCP28PSZm = 14209, X86_VRCP28PSZmb = 14210, X86_VRCP28PSZmbk = 14211, X86_VRCP28PSZmbkz = 14212, X86_VRCP28PSZmk = 14213, X86_VRCP28PSZmkz = 14214, X86_VRCP28PSZr = 14215, X86_VRCP28PSZrb = 14216, X86_VRCP28PSZrbk = 14217, X86_VRCP28PSZrbkz = 14218, X86_VRCP28PSZrk = 14219, X86_VRCP28PSZrkz = 14220, X86_VRCP28SDZm = 14221, X86_VRCP28SDZmk = 14222, X86_VRCP28SDZmkz = 14223, X86_VRCP28SDZr = 14224, X86_VRCP28SDZrb = 14225, X86_VRCP28SDZrbk = 14226, X86_VRCP28SDZrbkz = 14227, X86_VRCP28SDZrk = 14228, X86_VRCP28SDZrkz = 14229, X86_VRCP28SSZm = 14230, X86_VRCP28SSZmk = 14231, X86_VRCP28SSZmkz = 14232, X86_VRCP28SSZr = 14233, X86_VRCP28SSZrb = 14234, X86_VRCP28SSZrbk = 14235, X86_VRCP28SSZrbkz = 14236, X86_VRCP28SSZrk = 14237, X86_VRCP28SSZrkz = 14238, X86_VRCPPSYm = 14239, X86_VRCPPSYr = 14240, X86_VRCPPSm = 14241, X86_VRCPPSr = 14242, X86_VRCPSSm = 14243, X86_VRCPSSm_Int = 14244, X86_VRCPSSr = 14245, X86_VRCPSSr_Int = 14246, X86_VREDUCEPDZ128rmbi = 14247, X86_VREDUCEPDZ128rmbik = 14248, X86_VREDUCEPDZ128rmbikz = 14249, X86_VREDUCEPDZ128rmi = 14250, X86_VREDUCEPDZ128rmik = 14251, X86_VREDUCEPDZ128rmikz = 14252, X86_VREDUCEPDZ128rri = 14253, X86_VREDUCEPDZ128rrik = 14254, X86_VREDUCEPDZ128rrikz = 14255, X86_VREDUCEPDZ256rmbi = 14256, X86_VREDUCEPDZ256rmbik = 14257, X86_VREDUCEPDZ256rmbikz = 14258, X86_VREDUCEPDZ256rmi = 14259, X86_VREDUCEPDZ256rmik = 14260, X86_VREDUCEPDZ256rmikz = 14261, X86_VREDUCEPDZ256rri = 14262, X86_VREDUCEPDZ256rrik = 14263, X86_VREDUCEPDZ256rrikz = 14264, X86_VREDUCEPDZrmbi = 14265, X86_VREDUCEPDZrmbik = 14266, X86_VREDUCEPDZrmbikz = 14267, X86_VREDUCEPDZrmi = 14268, X86_VREDUCEPDZrmik = 14269, X86_VREDUCEPDZrmikz = 14270, X86_VREDUCEPDZrri = 14271, X86_VREDUCEPDZrrib = 14272, X86_VREDUCEPDZrribk = 14273, X86_VREDUCEPDZrribkz = 14274, X86_VREDUCEPDZrrik = 14275, X86_VREDUCEPDZrrikz = 14276, X86_VREDUCEPSZ128rmbi = 14277, X86_VREDUCEPSZ128rmbik = 14278, X86_VREDUCEPSZ128rmbikz = 14279, X86_VREDUCEPSZ128rmi = 14280, X86_VREDUCEPSZ128rmik = 14281, X86_VREDUCEPSZ128rmikz = 14282, X86_VREDUCEPSZ128rri = 14283, X86_VREDUCEPSZ128rrik = 14284, X86_VREDUCEPSZ128rrikz = 14285, X86_VREDUCEPSZ256rmbi = 14286, X86_VREDUCEPSZ256rmbik = 14287, X86_VREDUCEPSZ256rmbikz = 14288, X86_VREDUCEPSZ256rmi = 14289, X86_VREDUCEPSZ256rmik = 14290, X86_VREDUCEPSZ256rmikz = 14291, X86_VREDUCEPSZ256rri = 14292, X86_VREDUCEPSZ256rrik = 14293, X86_VREDUCEPSZ256rrikz = 14294, X86_VREDUCEPSZrmbi = 14295, X86_VREDUCEPSZrmbik = 14296, X86_VREDUCEPSZrmbikz = 14297, X86_VREDUCEPSZrmi = 14298, X86_VREDUCEPSZrmik = 14299, X86_VREDUCEPSZrmikz = 14300, X86_VREDUCEPSZrri = 14301, X86_VREDUCEPSZrrib = 14302, X86_VREDUCEPSZrribk = 14303, X86_VREDUCEPSZrribkz = 14304, X86_VREDUCEPSZrrik = 14305, X86_VREDUCEPSZrrikz = 14306, X86_VREDUCESDZrmi = 14307, X86_VREDUCESDZrmik = 14308, X86_VREDUCESDZrmikz = 14309, X86_VREDUCESDZrri = 14310, X86_VREDUCESDZrrib = 14311, X86_VREDUCESDZrribk = 14312, X86_VREDUCESDZrribkz = 14313, X86_VREDUCESDZrrik = 14314, X86_VREDUCESDZrrikz = 14315, X86_VREDUCESSZrmi = 14316, X86_VREDUCESSZrmik = 14317, X86_VREDUCESSZrmikz = 14318, X86_VREDUCESSZrri = 14319, X86_VREDUCESSZrrib = 14320, X86_VREDUCESSZrribk = 14321, X86_VREDUCESSZrribkz = 14322, X86_VREDUCESSZrrik = 14323, X86_VREDUCESSZrrikz = 14324, X86_VRNDSCALEPDZ128rmbi = 14325, X86_VRNDSCALEPDZ128rmbik = 14326, X86_VRNDSCALEPDZ128rmbikz = 14327, X86_VRNDSCALEPDZ128rmi = 14328, X86_VRNDSCALEPDZ128rmik = 14329, X86_VRNDSCALEPDZ128rmikz = 14330, X86_VRNDSCALEPDZ128rri = 14331, X86_VRNDSCALEPDZ128rrik = 14332, X86_VRNDSCALEPDZ128rrikz = 14333, X86_VRNDSCALEPDZ256rmbi = 14334, X86_VRNDSCALEPDZ256rmbik = 14335, X86_VRNDSCALEPDZ256rmbikz = 14336, X86_VRNDSCALEPDZ256rmi = 14337, X86_VRNDSCALEPDZ256rmik = 14338, X86_VRNDSCALEPDZ256rmikz = 14339, X86_VRNDSCALEPDZ256rri = 14340, X86_VRNDSCALEPDZ256rrik = 14341, X86_VRNDSCALEPDZ256rrikz = 14342, X86_VRNDSCALEPDZrmbi = 14343, X86_VRNDSCALEPDZrmbik = 14344, X86_VRNDSCALEPDZrmbikz = 14345, X86_VRNDSCALEPDZrmi = 14346, X86_VRNDSCALEPDZrmik = 14347, X86_VRNDSCALEPDZrmikz = 14348, X86_VRNDSCALEPDZrri = 14349, X86_VRNDSCALEPDZrrib = 14350, X86_VRNDSCALEPDZrribk = 14351, X86_VRNDSCALEPDZrribkz = 14352, X86_VRNDSCALEPDZrrik = 14353, X86_VRNDSCALEPDZrrikz = 14354, X86_VRNDSCALEPSZ128rmbi = 14355, X86_VRNDSCALEPSZ128rmbik = 14356, X86_VRNDSCALEPSZ128rmbikz = 14357, X86_VRNDSCALEPSZ128rmi = 14358, X86_VRNDSCALEPSZ128rmik = 14359, X86_VRNDSCALEPSZ128rmikz = 14360, X86_VRNDSCALEPSZ128rri = 14361, X86_VRNDSCALEPSZ128rrik = 14362, X86_VRNDSCALEPSZ128rrikz = 14363, X86_VRNDSCALEPSZ256rmbi = 14364, X86_VRNDSCALEPSZ256rmbik = 14365, X86_VRNDSCALEPSZ256rmbikz = 14366, X86_VRNDSCALEPSZ256rmi = 14367, X86_VRNDSCALEPSZ256rmik = 14368, X86_VRNDSCALEPSZ256rmikz = 14369, X86_VRNDSCALEPSZ256rri = 14370, X86_VRNDSCALEPSZ256rrik = 14371, X86_VRNDSCALEPSZ256rrikz = 14372, X86_VRNDSCALEPSZrmbi = 14373, X86_VRNDSCALEPSZrmbik = 14374, X86_VRNDSCALEPSZrmbikz = 14375, X86_VRNDSCALEPSZrmi = 14376, X86_VRNDSCALEPSZrmik = 14377, X86_VRNDSCALEPSZrmikz = 14378, X86_VRNDSCALEPSZrri = 14379, X86_VRNDSCALEPSZrrib = 14380, X86_VRNDSCALEPSZrribk = 14381, X86_VRNDSCALEPSZrribkz = 14382, X86_VRNDSCALEPSZrrik = 14383, X86_VRNDSCALEPSZrrikz = 14384, X86_VRNDSCALESDZm = 14385, X86_VRNDSCALESDZm_Int = 14386, X86_VRNDSCALESDZm_Intk = 14387, X86_VRNDSCALESDZm_Intkz = 14388, X86_VRNDSCALESDZr = 14389, X86_VRNDSCALESDZr_Int = 14390, X86_VRNDSCALESDZr_Intk = 14391, X86_VRNDSCALESDZr_Intkz = 14392, X86_VRNDSCALESDZrb_Int = 14393, X86_VRNDSCALESDZrb_Intk = 14394, X86_VRNDSCALESDZrb_Intkz = 14395, X86_VRNDSCALESSZm = 14396, X86_VRNDSCALESSZm_Int = 14397, X86_VRNDSCALESSZm_Intk = 14398, X86_VRNDSCALESSZm_Intkz = 14399, X86_VRNDSCALESSZr = 14400, X86_VRNDSCALESSZr_Int = 14401, X86_VRNDSCALESSZr_Intk = 14402, X86_VRNDSCALESSZr_Intkz = 14403, X86_VRNDSCALESSZrb_Int = 14404, X86_VRNDSCALESSZrb_Intk = 14405, X86_VRNDSCALESSZrb_Intkz = 14406, X86_VROUNDPDYm = 14407, X86_VROUNDPDYr = 14408, X86_VROUNDPDm = 14409, X86_VROUNDPDr = 14410, X86_VROUNDPSYm = 14411, X86_VROUNDPSYr = 14412, X86_VROUNDPSm = 14413, X86_VROUNDPSr = 14414, X86_VROUNDSDm = 14415, X86_VROUNDSDm_Int = 14416, X86_VROUNDSDr = 14417, X86_VROUNDSDr_Int = 14418, X86_VROUNDSSm = 14419, X86_VROUNDSSm_Int = 14420, X86_VROUNDSSr = 14421, X86_VROUNDSSr_Int = 14422, X86_VRSQRT14PDZ128m = 14423, X86_VRSQRT14PDZ128mb = 14424, X86_VRSQRT14PDZ128mbk = 14425, X86_VRSQRT14PDZ128mbkz = 14426, X86_VRSQRT14PDZ128mk = 14427, X86_VRSQRT14PDZ128mkz = 14428, X86_VRSQRT14PDZ128r = 14429, X86_VRSQRT14PDZ128rk = 14430, X86_VRSQRT14PDZ128rkz = 14431, X86_VRSQRT14PDZ256m = 14432, X86_VRSQRT14PDZ256mb = 14433, X86_VRSQRT14PDZ256mbk = 14434, X86_VRSQRT14PDZ256mbkz = 14435, X86_VRSQRT14PDZ256mk = 14436, X86_VRSQRT14PDZ256mkz = 14437, X86_VRSQRT14PDZ256r = 14438, X86_VRSQRT14PDZ256rk = 14439, X86_VRSQRT14PDZ256rkz = 14440, X86_VRSQRT14PDZm = 14441, X86_VRSQRT14PDZmb = 14442, X86_VRSQRT14PDZmbk = 14443, X86_VRSQRT14PDZmbkz = 14444, X86_VRSQRT14PDZmk = 14445, X86_VRSQRT14PDZmkz = 14446, X86_VRSQRT14PDZr = 14447, X86_VRSQRT14PDZrk = 14448, X86_VRSQRT14PDZrkz = 14449, X86_VRSQRT14PSZ128m = 14450, X86_VRSQRT14PSZ128mb = 14451, X86_VRSQRT14PSZ128mbk = 14452, X86_VRSQRT14PSZ128mbkz = 14453, X86_VRSQRT14PSZ128mk = 14454, X86_VRSQRT14PSZ128mkz = 14455, X86_VRSQRT14PSZ128r = 14456, X86_VRSQRT14PSZ128rk = 14457, X86_VRSQRT14PSZ128rkz = 14458, X86_VRSQRT14PSZ256m = 14459, X86_VRSQRT14PSZ256mb = 14460, X86_VRSQRT14PSZ256mbk = 14461, X86_VRSQRT14PSZ256mbkz = 14462, X86_VRSQRT14PSZ256mk = 14463, X86_VRSQRT14PSZ256mkz = 14464, X86_VRSQRT14PSZ256r = 14465, X86_VRSQRT14PSZ256rk = 14466, X86_VRSQRT14PSZ256rkz = 14467, X86_VRSQRT14PSZm = 14468, X86_VRSQRT14PSZmb = 14469, X86_VRSQRT14PSZmbk = 14470, X86_VRSQRT14PSZmbkz = 14471, X86_VRSQRT14PSZmk = 14472, X86_VRSQRT14PSZmkz = 14473, X86_VRSQRT14PSZr = 14474, X86_VRSQRT14PSZrk = 14475, X86_VRSQRT14PSZrkz = 14476, X86_VRSQRT14SDZrm = 14477, X86_VRSQRT14SDZrmk = 14478, X86_VRSQRT14SDZrmkz = 14479, X86_VRSQRT14SDZrr = 14480, X86_VRSQRT14SDZrrk = 14481, X86_VRSQRT14SDZrrkz = 14482, X86_VRSQRT14SSZrm = 14483, X86_VRSQRT14SSZrmk = 14484, X86_VRSQRT14SSZrmkz = 14485, X86_VRSQRT14SSZrr = 14486, X86_VRSQRT14SSZrrk = 14487, X86_VRSQRT14SSZrrkz = 14488, X86_VRSQRT28PDZm = 14489, X86_VRSQRT28PDZmb = 14490, X86_VRSQRT28PDZmbk = 14491, X86_VRSQRT28PDZmbkz = 14492, X86_VRSQRT28PDZmk = 14493, X86_VRSQRT28PDZmkz = 14494, X86_VRSQRT28PDZr = 14495, X86_VRSQRT28PDZrb = 14496, X86_VRSQRT28PDZrbk = 14497, X86_VRSQRT28PDZrbkz = 14498, X86_VRSQRT28PDZrk = 14499, X86_VRSQRT28PDZrkz = 14500, X86_VRSQRT28PSZm = 14501, X86_VRSQRT28PSZmb = 14502, X86_VRSQRT28PSZmbk = 14503, X86_VRSQRT28PSZmbkz = 14504, X86_VRSQRT28PSZmk = 14505, X86_VRSQRT28PSZmkz = 14506, X86_VRSQRT28PSZr = 14507, X86_VRSQRT28PSZrb = 14508, X86_VRSQRT28PSZrbk = 14509, X86_VRSQRT28PSZrbkz = 14510, X86_VRSQRT28PSZrk = 14511, X86_VRSQRT28PSZrkz = 14512, X86_VRSQRT28SDZm = 14513, X86_VRSQRT28SDZmk = 14514, X86_VRSQRT28SDZmkz = 14515, X86_VRSQRT28SDZr = 14516, X86_VRSQRT28SDZrb = 14517, X86_VRSQRT28SDZrbk = 14518, X86_VRSQRT28SDZrbkz = 14519, X86_VRSQRT28SDZrk = 14520, X86_VRSQRT28SDZrkz = 14521, X86_VRSQRT28SSZm = 14522, X86_VRSQRT28SSZmk = 14523, X86_VRSQRT28SSZmkz = 14524, X86_VRSQRT28SSZr = 14525, X86_VRSQRT28SSZrb = 14526, X86_VRSQRT28SSZrbk = 14527, X86_VRSQRT28SSZrbkz = 14528, X86_VRSQRT28SSZrk = 14529, X86_VRSQRT28SSZrkz = 14530, X86_VRSQRTPSYm = 14531, X86_VRSQRTPSYr = 14532, X86_VRSQRTPSm = 14533, X86_VRSQRTPSr = 14534, X86_VRSQRTSSm = 14535, X86_VRSQRTSSm_Int = 14536, X86_VRSQRTSSr = 14537, X86_VRSQRTSSr_Int = 14538, X86_VSCALEFPDZ128rm = 14539, X86_VSCALEFPDZ128rmb = 14540, X86_VSCALEFPDZ128rmbk = 14541, X86_VSCALEFPDZ128rmbkz = 14542, X86_VSCALEFPDZ128rmk = 14543, X86_VSCALEFPDZ128rmkz = 14544, X86_VSCALEFPDZ128rr = 14545, X86_VSCALEFPDZ128rrk = 14546, X86_VSCALEFPDZ128rrkz = 14547, X86_VSCALEFPDZ256rm = 14548, X86_VSCALEFPDZ256rmb = 14549, X86_VSCALEFPDZ256rmbk = 14550, X86_VSCALEFPDZ256rmbkz = 14551, X86_VSCALEFPDZ256rmk = 14552, X86_VSCALEFPDZ256rmkz = 14553, X86_VSCALEFPDZ256rr = 14554, X86_VSCALEFPDZ256rrk = 14555, X86_VSCALEFPDZ256rrkz = 14556, X86_VSCALEFPDZrm = 14557, X86_VSCALEFPDZrmb = 14558, X86_VSCALEFPDZrmbk = 14559, X86_VSCALEFPDZrmbkz = 14560, X86_VSCALEFPDZrmk = 14561, X86_VSCALEFPDZrmkz = 14562, X86_VSCALEFPDZrr = 14563, X86_VSCALEFPDZrrb = 14564, X86_VSCALEFPDZrrbk = 14565, X86_VSCALEFPDZrrbkz = 14566, X86_VSCALEFPDZrrk = 14567, X86_VSCALEFPDZrrkz = 14568, X86_VSCALEFPSZ128rm = 14569, X86_VSCALEFPSZ128rmb = 14570, X86_VSCALEFPSZ128rmbk = 14571, X86_VSCALEFPSZ128rmbkz = 14572, X86_VSCALEFPSZ128rmk = 14573, X86_VSCALEFPSZ128rmkz = 14574, X86_VSCALEFPSZ128rr = 14575, X86_VSCALEFPSZ128rrk = 14576, X86_VSCALEFPSZ128rrkz = 14577, X86_VSCALEFPSZ256rm = 14578, X86_VSCALEFPSZ256rmb = 14579, X86_VSCALEFPSZ256rmbk = 14580, X86_VSCALEFPSZ256rmbkz = 14581, X86_VSCALEFPSZ256rmk = 14582, X86_VSCALEFPSZ256rmkz = 14583, X86_VSCALEFPSZ256rr = 14584, X86_VSCALEFPSZ256rrk = 14585, X86_VSCALEFPSZ256rrkz = 14586, X86_VSCALEFPSZrm = 14587, X86_VSCALEFPSZrmb = 14588, X86_VSCALEFPSZrmbk = 14589, X86_VSCALEFPSZrmbkz = 14590, X86_VSCALEFPSZrmk = 14591, X86_VSCALEFPSZrmkz = 14592, X86_VSCALEFPSZrr = 14593, X86_VSCALEFPSZrrb = 14594, X86_VSCALEFPSZrrbk = 14595, X86_VSCALEFPSZrrbkz = 14596, X86_VSCALEFPSZrrk = 14597, X86_VSCALEFPSZrrkz = 14598, X86_VSCALEFSDZrm = 14599, X86_VSCALEFSDZrmk = 14600, X86_VSCALEFSDZrmkz = 14601, X86_VSCALEFSDZrr = 14602, X86_VSCALEFSDZrrb_Int = 14603, X86_VSCALEFSDZrrb_Intk = 14604, X86_VSCALEFSDZrrb_Intkz = 14605, X86_VSCALEFSDZrrk = 14606, X86_VSCALEFSDZrrkz = 14607, X86_VSCALEFSSZrm = 14608, X86_VSCALEFSSZrmk = 14609, X86_VSCALEFSSZrmkz = 14610, X86_VSCALEFSSZrr = 14611, X86_VSCALEFSSZrrb_Int = 14612, X86_VSCALEFSSZrrb_Intk = 14613, X86_VSCALEFSSZrrb_Intkz = 14614, X86_VSCALEFSSZrrk = 14615, X86_VSCALEFSSZrrkz = 14616, X86_VSCATTERDPDZ128mr = 14617, X86_VSCATTERDPDZ256mr = 14618, X86_VSCATTERDPDZmr = 14619, X86_VSCATTERDPSZ128mr = 14620, X86_VSCATTERDPSZ256mr = 14621, X86_VSCATTERDPSZmr = 14622, X86_VSCATTERPF0DPDm = 14623, X86_VSCATTERPF0DPSm = 14624, X86_VSCATTERPF0QPDm = 14625, X86_VSCATTERPF0QPSm = 14626, X86_VSCATTERPF1DPDm = 14627, X86_VSCATTERPF1DPSm = 14628, X86_VSCATTERPF1QPDm = 14629, X86_VSCATTERPF1QPSm = 14630, X86_VSCATTERQPDZ128mr = 14631, X86_VSCATTERQPDZ256mr = 14632, X86_VSCATTERQPDZmr = 14633, X86_VSCATTERQPSZ128mr = 14634, X86_VSCATTERQPSZ256mr = 14635, X86_VSCATTERQPSZmr = 14636, X86_VSHUFF32X4Z256rmbi = 14637, X86_VSHUFF32X4Z256rmbik = 14638, X86_VSHUFF32X4Z256rmbikz = 14639, X86_VSHUFF32X4Z256rmi = 14640, X86_VSHUFF32X4Z256rmik = 14641, X86_VSHUFF32X4Z256rmikz = 14642, X86_VSHUFF32X4Z256rri = 14643, X86_VSHUFF32X4Z256rrik = 14644, X86_VSHUFF32X4Z256rrikz = 14645, X86_VSHUFF32X4Zrmbi = 14646, X86_VSHUFF32X4Zrmbik = 14647, X86_VSHUFF32X4Zrmbikz = 14648, X86_VSHUFF32X4Zrmi = 14649, X86_VSHUFF32X4Zrmik = 14650, X86_VSHUFF32X4Zrmikz = 14651, X86_VSHUFF32X4Zrri = 14652, X86_VSHUFF32X4Zrrik = 14653, X86_VSHUFF32X4Zrrikz = 14654, X86_VSHUFF64X2Z256rmbi = 14655, X86_VSHUFF64X2Z256rmbik = 14656, X86_VSHUFF64X2Z256rmbikz = 14657, X86_VSHUFF64X2Z256rmi = 14658, X86_VSHUFF64X2Z256rmik = 14659, X86_VSHUFF64X2Z256rmikz = 14660, X86_VSHUFF64X2Z256rri = 14661, X86_VSHUFF64X2Z256rrik = 14662, X86_VSHUFF64X2Z256rrikz = 14663, X86_VSHUFF64X2Zrmbi = 14664, X86_VSHUFF64X2Zrmbik = 14665, X86_VSHUFF64X2Zrmbikz = 14666, X86_VSHUFF64X2Zrmi = 14667, X86_VSHUFF64X2Zrmik = 14668, X86_VSHUFF64X2Zrmikz = 14669, X86_VSHUFF64X2Zrri = 14670, X86_VSHUFF64X2Zrrik = 14671, X86_VSHUFF64X2Zrrikz = 14672, X86_VSHUFI32X4Z256rmbi = 14673, X86_VSHUFI32X4Z256rmbik = 14674, X86_VSHUFI32X4Z256rmbikz = 14675, X86_VSHUFI32X4Z256rmi = 14676, X86_VSHUFI32X4Z256rmik = 14677, X86_VSHUFI32X4Z256rmikz = 14678, X86_VSHUFI32X4Z256rri = 14679, X86_VSHUFI32X4Z256rrik = 14680, X86_VSHUFI32X4Z256rrikz = 14681, X86_VSHUFI32X4Zrmbi = 14682, X86_VSHUFI32X4Zrmbik = 14683, X86_VSHUFI32X4Zrmbikz = 14684, X86_VSHUFI32X4Zrmi = 14685, X86_VSHUFI32X4Zrmik = 14686, X86_VSHUFI32X4Zrmikz = 14687, X86_VSHUFI32X4Zrri = 14688, X86_VSHUFI32X4Zrrik = 14689, X86_VSHUFI32X4Zrrikz = 14690, X86_VSHUFI64X2Z256rmbi = 14691, X86_VSHUFI64X2Z256rmbik = 14692, X86_VSHUFI64X2Z256rmbikz = 14693, X86_VSHUFI64X2Z256rmi = 14694, X86_VSHUFI64X2Z256rmik = 14695, X86_VSHUFI64X2Z256rmikz = 14696, X86_VSHUFI64X2Z256rri = 14697, X86_VSHUFI64X2Z256rrik = 14698, X86_VSHUFI64X2Z256rrikz = 14699, X86_VSHUFI64X2Zrmbi = 14700, X86_VSHUFI64X2Zrmbik = 14701, X86_VSHUFI64X2Zrmbikz = 14702, X86_VSHUFI64X2Zrmi = 14703, X86_VSHUFI64X2Zrmik = 14704, X86_VSHUFI64X2Zrmikz = 14705, X86_VSHUFI64X2Zrri = 14706, X86_VSHUFI64X2Zrrik = 14707, X86_VSHUFI64X2Zrrikz = 14708, X86_VSHUFPDYrmi = 14709, X86_VSHUFPDYrri = 14710, X86_VSHUFPDZ128rmbi = 14711, X86_VSHUFPDZ128rmbik = 14712, X86_VSHUFPDZ128rmbikz = 14713, X86_VSHUFPDZ128rmi = 14714, X86_VSHUFPDZ128rmik = 14715, X86_VSHUFPDZ128rmikz = 14716, X86_VSHUFPDZ128rri = 14717, X86_VSHUFPDZ128rrik = 14718, X86_VSHUFPDZ128rrikz = 14719, X86_VSHUFPDZ256rmbi = 14720, X86_VSHUFPDZ256rmbik = 14721, X86_VSHUFPDZ256rmbikz = 14722, X86_VSHUFPDZ256rmi = 14723, X86_VSHUFPDZ256rmik = 14724, X86_VSHUFPDZ256rmikz = 14725, X86_VSHUFPDZ256rri = 14726, X86_VSHUFPDZ256rrik = 14727, X86_VSHUFPDZ256rrikz = 14728, X86_VSHUFPDZrmbi = 14729, X86_VSHUFPDZrmbik = 14730, X86_VSHUFPDZrmbikz = 14731, X86_VSHUFPDZrmi = 14732, X86_VSHUFPDZrmik = 14733, X86_VSHUFPDZrmikz = 14734, X86_VSHUFPDZrri = 14735, X86_VSHUFPDZrrik = 14736, X86_VSHUFPDZrrikz = 14737, X86_VSHUFPDrmi = 14738, X86_VSHUFPDrri = 14739, X86_VSHUFPSYrmi = 14740, X86_VSHUFPSYrri = 14741, X86_VSHUFPSZ128rmbi = 14742, X86_VSHUFPSZ128rmbik = 14743, X86_VSHUFPSZ128rmbikz = 14744, X86_VSHUFPSZ128rmi = 14745, X86_VSHUFPSZ128rmik = 14746, X86_VSHUFPSZ128rmikz = 14747, X86_VSHUFPSZ128rri = 14748, X86_VSHUFPSZ128rrik = 14749, X86_VSHUFPSZ128rrikz = 14750, X86_VSHUFPSZ256rmbi = 14751, X86_VSHUFPSZ256rmbik = 14752, X86_VSHUFPSZ256rmbikz = 14753, X86_VSHUFPSZ256rmi = 14754, X86_VSHUFPSZ256rmik = 14755, X86_VSHUFPSZ256rmikz = 14756, X86_VSHUFPSZ256rri = 14757, X86_VSHUFPSZ256rrik = 14758, X86_VSHUFPSZ256rrikz = 14759, X86_VSHUFPSZrmbi = 14760, X86_VSHUFPSZrmbik = 14761, X86_VSHUFPSZrmbikz = 14762, X86_VSHUFPSZrmi = 14763, X86_VSHUFPSZrmik = 14764, X86_VSHUFPSZrmikz = 14765, X86_VSHUFPSZrri = 14766, X86_VSHUFPSZrrik = 14767, X86_VSHUFPSZrrikz = 14768, X86_VSHUFPSrmi = 14769, X86_VSHUFPSrri = 14770, X86_VSQRTPDYm = 14771, X86_VSQRTPDYr = 14772, X86_VSQRTPDZ128m = 14773, X86_VSQRTPDZ128mb = 14774, X86_VSQRTPDZ128mbk = 14775, X86_VSQRTPDZ128mbkz = 14776, X86_VSQRTPDZ128mk = 14777, X86_VSQRTPDZ128mkz = 14778, X86_VSQRTPDZ128r = 14779, X86_VSQRTPDZ128rk = 14780, X86_VSQRTPDZ128rkz = 14781, X86_VSQRTPDZ256m = 14782, X86_VSQRTPDZ256mb = 14783, X86_VSQRTPDZ256mbk = 14784, X86_VSQRTPDZ256mbkz = 14785, X86_VSQRTPDZ256mk = 14786, X86_VSQRTPDZ256mkz = 14787, X86_VSQRTPDZ256r = 14788, X86_VSQRTPDZ256rk = 14789, X86_VSQRTPDZ256rkz = 14790, X86_VSQRTPDZm = 14791, X86_VSQRTPDZmb = 14792, X86_VSQRTPDZmbk = 14793, X86_VSQRTPDZmbkz = 14794, X86_VSQRTPDZmk = 14795, X86_VSQRTPDZmkz = 14796, X86_VSQRTPDZr = 14797, X86_VSQRTPDZrb = 14798, X86_VSQRTPDZrbk = 14799, X86_VSQRTPDZrbkz = 14800, X86_VSQRTPDZrk = 14801, X86_VSQRTPDZrkz = 14802, X86_VSQRTPDm = 14803, X86_VSQRTPDr = 14804, X86_VSQRTPSYm = 14805, X86_VSQRTPSYr = 14806, X86_VSQRTPSZ128m = 14807, X86_VSQRTPSZ128mb = 14808, X86_VSQRTPSZ128mbk = 14809, X86_VSQRTPSZ128mbkz = 14810, X86_VSQRTPSZ128mk = 14811, X86_VSQRTPSZ128mkz = 14812, X86_VSQRTPSZ128r = 14813, X86_VSQRTPSZ128rk = 14814, X86_VSQRTPSZ128rkz = 14815, X86_VSQRTPSZ256m = 14816, X86_VSQRTPSZ256mb = 14817, X86_VSQRTPSZ256mbk = 14818, X86_VSQRTPSZ256mbkz = 14819, X86_VSQRTPSZ256mk = 14820, X86_VSQRTPSZ256mkz = 14821, X86_VSQRTPSZ256r = 14822, X86_VSQRTPSZ256rk = 14823, X86_VSQRTPSZ256rkz = 14824, X86_VSQRTPSZm = 14825, X86_VSQRTPSZmb = 14826, X86_VSQRTPSZmbk = 14827, X86_VSQRTPSZmbkz = 14828, X86_VSQRTPSZmk = 14829, X86_VSQRTPSZmkz = 14830, X86_VSQRTPSZr = 14831, X86_VSQRTPSZrb = 14832, X86_VSQRTPSZrbk = 14833, X86_VSQRTPSZrbkz = 14834, X86_VSQRTPSZrk = 14835, X86_VSQRTPSZrkz = 14836, X86_VSQRTPSm = 14837, X86_VSQRTPSr = 14838, X86_VSQRTSDZm = 14839, X86_VSQRTSDZm_Int = 14840, X86_VSQRTSDZm_Intk = 14841, X86_VSQRTSDZm_Intkz = 14842, X86_VSQRTSDZr = 14843, X86_VSQRTSDZr_Int = 14844, X86_VSQRTSDZr_Intk = 14845, X86_VSQRTSDZr_Intkz = 14846, X86_VSQRTSDZrb_Int = 14847, X86_VSQRTSDZrb_Intk = 14848, X86_VSQRTSDZrb_Intkz = 14849, X86_VSQRTSDm = 14850, X86_VSQRTSDm_Int = 14851, X86_VSQRTSDr = 14852, X86_VSQRTSDr_Int = 14853, X86_VSQRTSSZm = 14854, X86_VSQRTSSZm_Int = 14855, X86_VSQRTSSZm_Intk = 14856, X86_VSQRTSSZm_Intkz = 14857, X86_VSQRTSSZr = 14858, X86_VSQRTSSZr_Int = 14859, X86_VSQRTSSZr_Intk = 14860, X86_VSQRTSSZr_Intkz = 14861, X86_VSQRTSSZrb_Int = 14862, X86_VSQRTSSZrb_Intk = 14863, X86_VSQRTSSZrb_Intkz = 14864, X86_VSQRTSSm = 14865, X86_VSQRTSSm_Int = 14866, X86_VSQRTSSr = 14867, X86_VSQRTSSr_Int = 14868, X86_VSTMXCSR = 14869, X86_VSUBPDYrm = 14870, X86_VSUBPDYrr = 14871, X86_VSUBPDZ128rm = 14872, X86_VSUBPDZ128rmb = 14873, X86_VSUBPDZ128rmbk = 14874, X86_VSUBPDZ128rmbkz = 14875, X86_VSUBPDZ128rmk = 14876, X86_VSUBPDZ128rmkz = 14877, X86_VSUBPDZ128rr = 14878, X86_VSUBPDZ128rrk = 14879, X86_VSUBPDZ128rrkz = 14880, X86_VSUBPDZ256rm = 14881, X86_VSUBPDZ256rmb = 14882, X86_VSUBPDZ256rmbk = 14883, X86_VSUBPDZ256rmbkz = 14884, X86_VSUBPDZ256rmk = 14885, X86_VSUBPDZ256rmkz = 14886, X86_VSUBPDZ256rr = 14887, X86_VSUBPDZ256rrk = 14888, X86_VSUBPDZ256rrkz = 14889, X86_VSUBPDZrm = 14890, X86_VSUBPDZrmb = 14891, X86_VSUBPDZrmbk = 14892, X86_VSUBPDZrmbkz = 14893, X86_VSUBPDZrmk = 14894, X86_VSUBPDZrmkz = 14895, X86_VSUBPDZrr = 14896, X86_VSUBPDZrrb = 14897, X86_VSUBPDZrrbk = 14898, X86_VSUBPDZrrbkz = 14899, X86_VSUBPDZrrk = 14900, X86_VSUBPDZrrkz = 14901, X86_VSUBPDrm = 14902, X86_VSUBPDrr = 14903, X86_VSUBPSYrm = 14904, X86_VSUBPSYrr = 14905, X86_VSUBPSZ128rm = 14906, X86_VSUBPSZ128rmb = 14907, X86_VSUBPSZ128rmbk = 14908, X86_VSUBPSZ128rmbkz = 14909, X86_VSUBPSZ128rmk = 14910, X86_VSUBPSZ128rmkz = 14911, X86_VSUBPSZ128rr = 14912, X86_VSUBPSZ128rrk = 14913, X86_VSUBPSZ128rrkz = 14914, X86_VSUBPSZ256rm = 14915, X86_VSUBPSZ256rmb = 14916, X86_VSUBPSZ256rmbk = 14917, X86_VSUBPSZ256rmbkz = 14918, X86_VSUBPSZ256rmk = 14919, X86_VSUBPSZ256rmkz = 14920, X86_VSUBPSZ256rr = 14921, X86_VSUBPSZ256rrk = 14922, X86_VSUBPSZ256rrkz = 14923, X86_VSUBPSZrm = 14924, X86_VSUBPSZrmb = 14925, X86_VSUBPSZrmbk = 14926, X86_VSUBPSZrmbkz = 14927, X86_VSUBPSZrmk = 14928, X86_VSUBPSZrmkz = 14929, X86_VSUBPSZrr = 14930, X86_VSUBPSZrrb = 14931, X86_VSUBPSZrrbk = 14932, X86_VSUBPSZrrbkz = 14933, X86_VSUBPSZrrk = 14934, X86_VSUBPSZrrkz = 14935, X86_VSUBPSrm = 14936, X86_VSUBPSrr = 14937, X86_VSUBSDZrm = 14938, X86_VSUBSDZrm_Int = 14939, X86_VSUBSDZrm_Intk = 14940, X86_VSUBSDZrm_Intkz = 14941, X86_VSUBSDZrr = 14942, X86_VSUBSDZrr_Int = 14943, X86_VSUBSDZrr_Intk = 14944, X86_VSUBSDZrr_Intkz = 14945, X86_VSUBSDZrrb_Int = 14946, X86_VSUBSDZrrb_Intk = 14947, X86_VSUBSDZrrb_Intkz = 14948, X86_VSUBSDrm = 14949, X86_VSUBSDrm_Int = 14950, X86_VSUBSDrr = 14951, X86_VSUBSDrr_Int = 14952, X86_VSUBSSZrm = 14953, X86_VSUBSSZrm_Int = 14954, X86_VSUBSSZrm_Intk = 14955, X86_VSUBSSZrm_Intkz = 14956, X86_VSUBSSZrr = 14957, X86_VSUBSSZrr_Int = 14958, X86_VSUBSSZrr_Intk = 14959, X86_VSUBSSZrr_Intkz = 14960, X86_VSUBSSZrrb_Int = 14961, X86_VSUBSSZrrb_Intk = 14962, X86_VSUBSSZrrb_Intkz = 14963, X86_VSUBSSrm = 14964, X86_VSUBSSrm_Int = 14965, X86_VSUBSSrr = 14966, X86_VSUBSSrr_Int = 14967, X86_VTESTPDYrm = 14968, X86_VTESTPDYrr = 14969, X86_VTESTPDrm = 14970, X86_VTESTPDrr = 14971, X86_VTESTPSYrm = 14972, X86_VTESTPSYrr = 14973, X86_VTESTPSrm = 14974, X86_VTESTPSrr = 14975, X86_VUCOMISDZrm = 14976, X86_VUCOMISDZrm_Int = 14977, X86_VUCOMISDZrr = 14978, X86_VUCOMISDZrr_Int = 14979, X86_VUCOMISDZrrb = 14980, X86_VUCOMISDrm = 14981, X86_VUCOMISDrm_Int = 14982, X86_VUCOMISDrr = 14983, X86_VUCOMISDrr_Int = 14984, X86_VUCOMISSZrm = 14985, X86_VUCOMISSZrm_Int = 14986, X86_VUCOMISSZrr = 14987, X86_VUCOMISSZrr_Int = 14988, X86_VUCOMISSZrrb = 14989, X86_VUCOMISSrm = 14990, X86_VUCOMISSrm_Int = 14991, X86_VUCOMISSrr = 14992, X86_VUCOMISSrr_Int = 14993, X86_VUNPCKHPDYrm = 14994, X86_VUNPCKHPDYrr = 14995, X86_VUNPCKHPDZ128rm = 14996, X86_VUNPCKHPDZ128rmb = 14997, X86_VUNPCKHPDZ128rmbk = 14998, X86_VUNPCKHPDZ128rmbkz = 14999, X86_VUNPCKHPDZ128rmk = 15000, X86_VUNPCKHPDZ128rmkz = 15001, X86_VUNPCKHPDZ128rr = 15002, X86_VUNPCKHPDZ128rrk = 15003, X86_VUNPCKHPDZ128rrkz = 15004, X86_VUNPCKHPDZ256rm = 15005, X86_VUNPCKHPDZ256rmb = 15006, X86_VUNPCKHPDZ256rmbk = 15007, X86_VUNPCKHPDZ256rmbkz = 15008, X86_VUNPCKHPDZ256rmk = 15009, X86_VUNPCKHPDZ256rmkz = 15010, X86_VUNPCKHPDZ256rr = 15011, X86_VUNPCKHPDZ256rrk = 15012, X86_VUNPCKHPDZ256rrkz = 15013, X86_VUNPCKHPDZrm = 15014, X86_VUNPCKHPDZrmb = 15015, X86_VUNPCKHPDZrmbk = 15016, X86_VUNPCKHPDZrmbkz = 15017, X86_VUNPCKHPDZrmk = 15018, X86_VUNPCKHPDZrmkz = 15019, X86_VUNPCKHPDZrr = 15020, X86_VUNPCKHPDZrrk = 15021, X86_VUNPCKHPDZrrkz = 15022, X86_VUNPCKHPDrm = 15023, X86_VUNPCKHPDrr = 15024, X86_VUNPCKHPSYrm = 15025, X86_VUNPCKHPSYrr = 15026, X86_VUNPCKHPSZ128rm = 15027, X86_VUNPCKHPSZ128rmb = 15028, X86_VUNPCKHPSZ128rmbk = 15029, X86_VUNPCKHPSZ128rmbkz = 15030, X86_VUNPCKHPSZ128rmk = 15031, X86_VUNPCKHPSZ128rmkz = 15032, X86_VUNPCKHPSZ128rr = 15033, X86_VUNPCKHPSZ128rrk = 15034, X86_VUNPCKHPSZ128rrkz = 15035, X86_VUNPCKHPSZ256rm = 15036, X86_VUNPCKHPSZ256rmb = 15037, X86_VUNPCKHPSZ256rmbk = 15038, X86_VUNPCKHPSZ256rmbkz = 15039, X86_VUNPCKHPSZ256rmk = 15040, X86_VUNPCKHPSZ256rmkz = 15041, X86_VUNPCKHPSZ256rr = 15042, X86_VUNPCKHPSZ256rrk = 15043, X86_VUNPCKHPSZ256rrkz = 15044, X86_VUNPCKHPSZrm = 15045, X86_VUNPCKHPSZrmb = 15046, X86_VUNPCKHPSZrmbk = 15047, X86_VUNPCKHPSZrmbkz = 15048, X86_VUNPCKHPSZrmk = 15049, X86_VUNPCKHPSZrmkz = 15050, X86_VUNPCKHPSZrr = 15051, X86_VUNPCKHPSZrrk = 15052, X86_VUNPCKHPSZrrkz = 15053, X86_VUNPCKHPSrm = 15054, X86_VUNPCKHPSrr = 15055, X86_VUNPCKLPDYrm = 15056, X86_VUNPCKLPDYrr = 15057, X86_VUNPCKLPDZ128rm = 15058, X86_VUNPCKLPDZ128rmb = 15059, X86_VUNPCKLPDZ128rmbk = 15060, X86_VUNPCKLPDZ128rmbkz = 15061, X86_VUNPCKLPDZ128rmk = 15062, X86_VUNPCKLPDZ128rmkz = 15063, X86_VUNPCKLPDZ128rr = 15064, X86_VUNPCKLPDZ128rrk = 15065, X86_VUNPCKLPDZ128rrkz = 15066, X86_VUNPCKLPDZ256rm = 15067, X86_VUNPCKLPDZ256rmb = 15068, X86_VUNPCKLPDZ256rmbk = 15069, X86_VUNPCKLPDZ256rmbkz = 15070, X86_VUNPCKLPDZ256rmk = 15071, X86_VUNPCKLPDZ256rmkz = 15072, X86_VUNPCKLPDZ256rr = 15073, X86_VUNPCKLPDZ256rrk = 15074, X86_VUNPCKLPDZ256rrkz = 15075, X86_VUNPCKLPDZrm = 15076, X86_VUNPCKLPDZrmb = 15077, X86_VUNPCKLPDZrmbk = 15078, X86_VUNPCKLPDZrmbkz = 15079, X86_VUNPCKLPDZrmk = 15080, X86_VUNPCKLPDZrmkz = 15081, X86_VUNPCKLPDZrr = 15082, X86_VUNPCKLPDZrrk = 15083, X86_VUNPCKLPDZrrkz = 15084, X86_VUNPCKLPDrm = 15085, X86_VUNPCKLPDrr = 15086, X86_VUNPCKLPSYrm = 15087, X86_VUNPCKLPSYrr = 15088, X86_VUNPCKLPSZ128rm = 15089, X86_VUNPCKLPSZ128rmb = 15090, X86_VUNPCKLPSZ128rmbk = 15091, X86_VUNPCKLPSZ128rmbkz = 15092, X86_VUNPCKLPSZ128rmk = 15093, X86_VUNPCKLPSZ128rmkz = 15094, X86_VUNPCKLPSZ128rr = 15095, X86_VUNPCKLPSZ128rrk = 15096, X86_VUNPCKLPSZ128rrkz = 15097, X86_VUNPCKLPSZ256rm = 15098, X86_VUNPCKLPSZ256rmb = 15099, X86_VUNPCKLPSZ256rmbk = 15100, X86_VUNPCKLPSZ256rmbkz = 15101, X86_VUNPCKLPSZ256rmk = 15102, X86_VUNPCKLPSZ256rmkz = 15103, X86_VUNPCKLPSZ256rr = 15104, X86_VUNPCKLPSZ256rrk = 15105, X86_VUNPCKLPSZ256rrkz = 15106, X86_VUNPCKLPSZrm = 15107, X86_VUNPCKLPSZrmb = 15108, X86_VUNPCKLPSZrmbk = 15109, X86_VUNPCKLPSZrmbkz = 15110, X86_VUNPCKLPSZrmk = 15111, X86_VUNPCKLPSZrmkz = 15112, X86_VUNPCKLPSZrr = 15113, X86_VUNPCKLPSZrrk = 15114, X86_VUNPCKLPSZrrkz = 15115, X86_VUNPCKLPSrm = 15116, X86_VUNPCKLPSrr = 15117, X86_VXORPDYrm = 15118, X86_VXORPDYrr = 15119, X86_VXORPDZ128rm = 15120, X86_VXORPDZ128rmb = 15121, X86_VXORPDZ128rmbk = 15122, X86_VXORPDZ128rmbkz = 15123, X86_VXORPDZ128rmk = 15124, X86_VXORPDZ128rmkz = 15125, X86_VXORPDZ128rr = 15126, X86_VXORPDZ128rrk = 15127, X86_VXORPDZ128rrkz = 15128, X86_VXORPDZ256rm = 15129, X86_VXORPDZ256rmb = 15130, X86_VXORPDZ256rmbk = 15131, X86_VXORPDZ256rmbkz = 15132, X86_VXORPDZ256rmk = 15133, X86_VXORPDZ256rmkz = 15134, X86_VXORPDZ256rr = 15135, X86_VXORPDZ256rrk = 15136, X86_VXORPDZ256rrkz = 15137, X86_VXORPDZrm = 15138, X86_VXORPDZrmb = 15139, X86_VXORPDZrmbk = 15140, X86_VXORPDZrmbkz = 15141, X86_VXORPDZrmk = 15142, X86_VXORPDZrmkz = 15143, X86_VXORPDZrr = 15144, X86_VXORPDZrrk = 15145, X86_VXORPDZrrkz = 15146, X86_VXORPDrm = 15147, X86_VXORPDrr = 15148, X86_VXORPSYrm = 15149, X86_VXORPSYrr = 15150, X86_VXORPSZ128rm = 15151, X86_VXORPSZ128rmb = 15152, X86_VXORPSZ128rmbk = 15153, X86_VXORPSZ128rmbkz = 15154, X86_VXORPSZ128rmk = 15155, X86_VXORPSZ128rmkz = 15156, X86_VXORPSZ128rr = 15157, X86_VXORPSZ128rrk = 15158, X86_VXORPSZ128rrkz = 15159, X86_VXORPSZ256rm = 15160, X86_VXORPSZ256rmb = 15161, X86_VXORPSZ256rmbk = 15162, X86_VXORPSZ256rmbkz = 15163, X86_VXORPSZ256rmk = 15164, X86_VXORPSZ256rmkz = 15165, X86_VXORPSZ256rr = 15166, X86_VXORPSZ256rrk = 15167, X86_VXORPSZ256rrkz = 15168, X86_VXORPSZrm = 15169, X86_VXORPSZrmb = 15170, X86_VXORPSZrmbk = 15171, X86_VXORPSZrmbkz = 15172, X86_VXORPSZrmk = 15173, X86_VXORPSZrmkz = 15174, X86_VXORPSZrr = 15175, X86_VXORPSZrrk = 15176, X86_VXORPSZrrkz = 15177, X86_VXORPSrm = 15178, X86_VXORPSrr = 15179, X86_VZEROALL = 15180, X86_VZEROUPPER = 15181, X86_WAIT = 15182, X86_WBINVD = 15183, X86_WBNOINVD = 15184, X86_WRFSBASE = 15185, X86_WRFSBASE64 = 15186, X86_WRGSBASE = 15187, X86_WRGSBASE64 = 15188, X86_WRMSR = 15189, X86_WRPKRUr = 15190, X86_WRSSD = 15191, X86_WRSSQ = 15192, X86_WRUSSD = 15193, X86_WRUSSQ = 15194, X86_XABORT = 15195, X86_XACQUIRE_PREFIX = 15196, X86_XADD16rm = 15197, X86_XADD16rr = 15198, X86_XADD32rm = 15199, X86_XADD32rr = 15200, X86_XADD64rm = 15201, X86_XADD64rr = 15202, X86_XADD8rm = 15203, X86_XADD8rr = 15204, X86_XBEGIN_2 = 15205, X86_XBEGIN_4 = 15206, X86_XCHG16ar = 15207, X86_XCHG16rm = 15208, X86_XCHG16rr = 15209, X86_XCHG32ar = 15210, X86_XCHG32rm = 15211, X86_XCHG32rr = 15212, X86_XCHG64ar = 15213, X86_XCHG64rm = 15214, X86_XCHG64rr = 15215, X86_XCHG8rm = 15216, X86_XCHG8rr = 15217, X86_XCH_F = 15218, X86_XCRYPTCBC = 15219, X86_XCRYPTCFB = 15220, X86_XCRYPTCTR = 15221, X86_XCRYPTECB = 15222, X86_XCRYPTOFB = 15223, X86_XEND = 15224, X86_XGETBV = 15225, X86_XLAT = 15226, X86_XOR16i16 = 15227, X86_XOR16mi = 15228, X86_XOR16mi8 = 15229, X86_XOR16mr = 15230, X86_XOR16ri = 15231, X86_XOR16ri8 = 15232, X86_XOR16rm = 15233, X86_XOR16rr = 15234, X86_XOR16rr_REV = 15235, X86_XOR32i32 = 15236, X86_XOR32mi = 15237, X86_XOR32mi8 = 15238, X86_XOR32mr = 15239, X86_XOR32ri = 15240, X86_XOR32ri8 = 15241, X86_XOR32rm = 15242, X86_XOR32rr = 15243, X86_XOR32rr_REV = 15244, X86_XOR64i32 = 15245, X86_XOR64mi32 = 15246, X86_XOR64mi8 = 15247, X86_XOR64mr = 15248, X86_XOR64ri32 = 15249, X86_XOR64ri8 = 15250, X86_XOR64rm = 15251, X86_XOR64rr = 15252, X86_XOR64rr_REV = 15253, X86_XOR8i8 = 15254, X86_XOR8mi = 15255, X86_XOR8mi8 = 15256, X86_XOR8mr = 15257, X86_XOR8ri = 15258, X86_XOR8ri8 = 15259, X86_XOR8rm = 15260, X86_XOR8rr = 15261, X86_XOR8rr_REV = 15262, X86_XORPDrm = 15263, X86_XORPDrr = 15264, X86_XORPSrm = 15265, X86_XORPSrr = 15266, X86_XRELEASE_PREFIX = 15267, X86_XRSTOR = 15268, X86_XRSTOR64 = 15269, X86_XRSTORS = 15270, X86_XRSTORS64 = 15271, X86_XSAVE = 15272, X86_XSAVE64 = 15273, X86_XSAVEC = 15274, X86_XSAVEC64 = 15275, X86_XSAVEOPT = 15276, X86_XSAVEOPT64 = 15277, X86_XSAVES = 15278, X86_XSAVES64 = 15279, X86_XSETBV = 15280, X86_XSHA1 = 15281, X86_XSHA256 = 15282, X86_XSTORE = 15283, X86_XTEST = 15284, X86_INSTRUCTION_LIST_END = 15285 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/X86/X86GenInstrInfo_reduce.inc000064400000000000000000001007530072674642500224100ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { X86_AAA = 126, X86_AAD8i8 = 127, X86_AAM8i8 = 128, X86_AAS = 129, X86_ADC16i16 = 130, X86_ADC16mi = 131, X86_ADC16mi8 = 132, X86_ADC16mr = 133, X86_ADC16ri = 134, X86_ADC16ri8 = 135, X86_ADC16rm = 136, X86_ADC16rr = 137, X86_ADC16rr_REV = 138, X86_ADC32i32 = 139, X86_ADC32mi = 140, X86_ADC32mi8 = 141, X86_ADC32mr = 142, X86_ADC32ri = 143, X86_ADC32ri8 = 144, X86_ADC32rm = 145, X86_ADC32rr = 146, X86_ADC32rr_REV = 147, X86_ADC64i32 = 148, X86_ADC64mi32 = 149, X86_ADC64mi8 = 150, X86_ADC64mr = 151, X86_ADC64ri32 = 152, X86_ADC64ri8 = 153, X86_ADC64rm = 154, X86_ADC64rr = 155, X86_ADC64rr_REV = 156, X86_ADC8i8 = 157, X86_ADC8mi = 158, X86_ADC8mi8 = 159, X86_ADC8mr = 160, X86_ADC8ri = 161, X86_ADC8ri8 = 162, X86_ADC8rm = 163, X86_ADC8rr = 164, X86_ADC8rr_REV = 165, X86_ADCX32rm = 166, X86_ADCX32rr = 167, X86_ADCX64rm = 168, X86_ADCX64rr = 169, X86_ADD16i16 = 170, X86_ADD16mi = 171, X86_ADD16mi8 = 172, X86_ADD16mr = 173, X86_ADD16ri = 174, X86_ADD16ri8 = 175, X86_ADD16rm = 176, X86_ADD16rr = 177, X86_ADD16rr_REV = 178, X86_ADD32i32 = 179, X86_ADD32mi = 180, X86_ADD32mi8 = 181, X86_ADD32mr = 182, X86_ADD32ri = 183, X86_ADD32ri8 = 184, X86_ADD32rm = 185, X86_ADD32rr = 186, X86_ADD32rr_REV = 187, X86_ADD64i32 = 188, X86_ADD64mi32 = 189, X86_ADD64mi8 = 190, X86_ADD64mr = 191, X86_ADD64ri32 = 192, X86_ADD64ri8 = 193, X86_ADD64rm = 194, X86_ADD64rr = 195, X86_ADD64rr_REV = 196, X86_ADD8i8 = 197, X86_ADD8mi = 198, X86_ADD8mi8 = 199, X86_ADD8mr = 200, X86_ADD8ri = 201, X86_ADD8ri8 = 202, X86_ADD8rm = 203, X86_ADD8rr = 204, X86_ADD8rr_REV = 205, X86_ADOX32rm = 206, X86_ADOX32rr = 207, X86_ADOX64rm = 208, X86_ADOX64rr = 209, X86_AND16i16 = 210, X86_AND16mi = 211, X86_AND16mi8 = 212, X86_AND16mr = 213, X86_AND16ri = 214, X86_AND16ri8 = 215, X86_AND16rm = 216, X86_AND16rr = 217, X86_AND16rr_REV = 218, X86_AND32i32 = 219, X86_AND32mi = 220, X86_AND32mi8 = 221, X86_AND32mr = 222, X86_AND32ri = 223, X86_AND32ri8 = 224, X86_AND32rm = 225, X86_AND32rr = 226, X86_AND32rr_REV = 227, X86_AND64i32 = 228, X86_AND64mi32 = 229, X86_AND64mi8 = 230, X86_AND64mr = 231, X86_AND64ri32 = 232, X86_AND64ri8 = 233, X86_AND64rm = 234, X86_AND64rr = 235, X86_AND64rr_REV = 236, X86_AND8i8 = 237, X86_AND8mi = 238, X86_AND8mi8 = 239, X86_AND8mr = 240, X86_AND8ri = 241, X86_AND8ri8 = 242, X86_AND8rm = 243, X86_AND8rr = 244, X86_AND8rr_REV = 245, X86_ANDN32rm = 246, X86_ANDN32rr = 247, X86_ANDN64rm = 248, X86_ANDN64rr = 249, X86_ARPL16mr = 250, X86_ARPL16rr = 251, X86_BEXTR32rm = 252, X86_BEXTR32rr = 253, X86_BEXTR64rm = 254, X86_BEXTR64rr = 255, X86_BEXTRI32mi = 256, X86_BEXTRI32ri = 257, X86_BEXTRI64mi = 258, X86_BEXTRI64ri = 259, X86_BLCFILL32rm = 260, X86_BLCFILL32rr = 261, X86_BLCFILL64rm = 262, X86_BLCFILL64rr = 263, X86_BLCI32rm = 264, X86_BLCI32rr = 265, X86_BLCI64rm = 266, X86_BLCI64rr = 267, X86_BLCIC32rm = 268, X86_BLCIC32rr = 269, X86_BLCIC64rm = 270, X86_BLCIC64rr = 271, X86_BLCMSK32rm = 272, X86_BLCMSK32rr = 273, X86_BLCMSK64rm = 274, X86_BLCMSK64rr = 275, X86_BLCS32rm = 276, X86_BLCS32rr = 277, X86_BLCS64rm = 278, X86_BLCS64rr = 279, X86_BLSFILL32rm = 280, X86_BLSFILL32rr = 281, X86_BLSFILL64rm = 282, X86_BLSFILL64rr = 283, X86_BLSI32rm = 284, X86_BLSI32rr = 285, X86_BLSI64rm = 286, X86_BLSI64rr = 287, X86_BLSIC32rm = 288, X86_BLSIC32rr = 289, X86_BLSIC64rm = 290, X86_BLSIC64rr = 291, X86_BLSMSK32rm = 292, X86_BLSMSK32rr = 293, X86_BLSMSK64rm = 294, X86_BLSMSK64rr = 295, X86_BLSR32rm = 296, X86_BLSR32rr = 297, X86_BLSR64rm = 298, X86_BLSR64rr = 299, X86_BOUNDS16rm = 300, X86_BOUNDS32rm = 301, X86_BSF16rm = 302, X86_BSF16rr = 303, X86_BSF32rm = 304, X86_BSF32rr = 305, X86_BSF64rm = 306, X86_BSF64rr = 307, X86_BSR16rm = 308, X86_BSR16rr = 309, X86_BSR32rm = 310, X86_BSR32rr = 311, X86_BSR64rm = 312, X86_BSR64rr = 313, X86_BSWAP16r_BAD = 314, X86_BSWAP32r = 315, X86_BSWAP64r = 316, X86_BT16mi8 = 317, X86_BT16mr = 318, X86_BT16ri8 = 319, X86_BT16rr = 320, X86_BT32mi8 = 321, X86_BT32mr = 322, X86_BT32ri8 = 323, X86_BT32rr = 324, X86_BT64mi8 = 325, X86_BT64mr = 326, X86_BT64ri8 = 327, X86_BT64rr = 328, X86_BTC16mi8 = 329, X86_BTC16mr = 330, X86_BTC16ri8 = 331, X86_BTC16rr = 332, X86_BTC32mi8 = 333, X86_BTC32mr = 334, X86_BTC32ri8 = 335, X86_BTC32rr = 336, X86_BTC64mi8 = 337, X86_BTC64mr = 338, X86_BTC64ri8 = 339, X86_BTC64rr = 340, X86_BTR16mi8 = 341, X86_BTR16mr = 342, X86_BTR16ri8 = 343, X86_BTR16rr = 344, X86_BTR32mi8 = 345, X86_BTR32mr = 346, X86_BTR32ri8 = 347, X86_BTR32rr = 348, X86_BTR64mi8 = 349, X86_BTR64mr = 350, X86_BTR64ri8 = 351, X86_BTR64rr = 352, X86_BTS16mi8 = 353, X86_BTS16mr = 354, X86_BTS16ri8 = 355, X86_BTS16rr = 356, X86_BTS32mi8 = 357, X86_BTS32mr = 358, X86_BTS32ri8 = 359, X86_BTS32rr = 360, X86_BTS64mi8 = 361, X86_BTS64mr = 362, X86_BTS64ri8 = 363, X86_BTS64rr = 364, X86_BZHI32rm = 365, X86_BZHI32rr = 366, X86_BZHI64rm = 367, X86_BZHI64rr = 368, X86_CALL16m = 369, X86_CALL16m_NT = 370, X86_CALL16r = 371, X86_CALL16r_NT = 372, X86_CALL32m = 373, X86_CALL32m_NT = 374, X86_CALL32r = 375, X86_CALL32r_NT = 376, X86_CALL64m = 377, X86_CALL64m_NT = 378, X86_CALL64pcrel32 = 379, X86_CALL64r = 380, X86_CALL64r_NT = 381, X86_CALLpcrel16 = 382, X86_CALLpcrel32 = 383, X86_CBW = 384, X86_CDQ = 385, X86_CDQE = 386, X86_CLAC = 387, X86_CLC = 388, X86_CLD = 389, X86_CLDEMOTE = 390, X86_CLFLUSHOPT = 391, X86_CLGI = 392, X86_CLI = 393, X86_CLRSSBSY = 394, X86_CLTS = 395, X86_CLWB = 396, X86_CLZEROr = 397, X86_CMC = 398, X86_CMOVA16rm = 399, X86_CMOVA16rr = 400, X86_CMOVA32rm = 401, X86_CMOVA32rr = 402, X86_CMOVA64rm = 403, X86_CMOVA64rr = 404, X86_CMOVAE16rm = 405, X86_CMOVAE16rr = 406, X86_CMOVAE32rm = 407, X86_CMOVAE32rr = 408, X86_CMOVAE64rm = 409, X86_CMOVAE64rr = 410, X86_CMOVB16rm = 411, X86_CMOVB16rr = 412, X86_CMOVB32rm = 413, X86_CMOVB32rr = 414, X86_CMOVB64rm = 415, X86_CMOVB64rr = 416, X86_CMOVBE16rm = 417, X86_CMOVBE16rr = 418, X86_CMOVBE32rm = 419, X86_CMOVBE32rr = 420, X86_CMOVBE64rm = 421, X86_CMOVBE64rr = 422, X86_CMOVE16rm = 423, X86_CMOVE16rr = 424, X86_CMOVE32rm = 425, X86_CMOVE32rr = 426, X86_CMOVE64rm = 427, X86_CMOVE64rr = 428, X86_CMOVG16rm = 429, X86_CMOVG16rr = 430, X86_CMOVG32rm = 431, X86_CMOVG32rr = 432, X86_CMOVG64rm = 433, X86_CMOVG64rr = 434, X86_CMOVGE16rm = 435, X86_CMOVGE16rr = 436, X86_CMOVGE32rm = 437, X86_CMOVGE32rr = 438, X86_CMOVGE64rm = 439, X86_CMOVGE64rr = 440, X86_CMOVL16rm = 441, X86_CMOVL16rr = 442, X86_CMOVL32rm = 443, X86_CMOVL32rr = 444, X86_CMOVL64rm = 445, X86_CMOVL64rr = 446, X86_CMOVLE16rm = 447, X86_CMOVLE16rr = 448, X86_CMOVLE32rm = 449, X86_CMOVLE32rr = 450, X86_CMOVLE64rm = 451, X86_CMOVLE64rr = 452, X86_CMOVNE16rm = 453, X86_CMOVNE16rr = 454, X86_CMOVNE32rm = 455, X86_CMOVNE32rr = 456, X86_CMOVNE64rm = 457, X86_CMOVNE64rr = 458, X86_CMOVNO16rm = 459, X86_CMOVNO16rr = 460, X86_CMOVNO32rm = 461, X86_CMOVNO32rr = 462, X86_CMOVNO64rm = 463, X86_CMOVNO64rr = 464, X86_CMOVNP16rm = 465, X86_CMOVNP16rr = 466, X86_CMOVNP32rm = 467, X86_CMOVNP32rr = 468, X86_CMOVNP64rm = 469, X86_CMOVNP64rr = 470, X86_CMOVNS16rm = 471, X86_CMOVNS16rr = 472, X86_CMOVNS32rm = 473, X86_CMOVNS32rr = 474, X86_CMOVNS64rm = 475, X86_CMOVNS64rr = 476, X86_CMOVO16rm = 477, X86_CMOVO16rr = 478, X86_CMOVO32rm = 479, X86_CMOVO32rr = 480, X86_CMOVO64rm = 481, X86_CMOVO64rr = 482, X86_CMOVP16rm = 483, X86_CMOVP16rr = 484, X86_CMOVP32rm = 485, X86_CMOVP32rr = 486, X86_CMOVP64rm = 487, X86_CMOVP64rr = 488, X86_CMOVS16rm = 489, X86_CMOVS16rr = 490, X86_CMOVS32rm = 491, X86_CMOVS32rr = 492, X86_CMOVS64rm = 493, X86_CMOVS64rr = 494, X86_CMP16i16 = 495, X86_CMP16mi = 496, X86_CMP16mi8 = 497, X86_CMP16mr = 498, X86_CMP16ri = 499, X86_CMP16ri8 = 500, X86_CMP16rm = 501, X86_CMP16rr = 502, X86_CMP16rr_REV = 503, X86_CMP32i32 = 504, X86_CMP32mi = 505, X86_CMP32mi8 = 506, X86_CMP32mr = 507, X86_CMP32ri = 508, X86_CMP32ri8 = 509, X86_CMP32rm = 510, X86_CMP32rr = 511, X86_CMP32rr_REV = 512, X86_CMP64i32 = 513, X86_CMP64mi32 = 514, X86_CMP64mi8 = 515, X86_CMP64mr = 516, X86_CMP64ri32 = 517, X86_CMP64ri8 = 518, X86_CMP64rm = 519, X86_CMP64rr = 520, X86_CMP64rr_REV = 521, X86_CMP8i8 = 522, X86_CMP8mi = 523, X86_CMP8mi8 = 524, X86_CMP8mr = 525, X86_CMP8ri = 526, X86_CMP8ri8 = 527, X86_CMP8rm = 528, X86_CMP8rr = 529, X86_CMP8rr_REV = 530, X86_CMPSB = 531, X86_CMPSL = 532, X86_CMPSQ = 533, X86_CMPSW = 534, X86_CMPXCHG16B = 535, X86_CMPXCHG16rm = 536, X86_CMPXCHG16rr = 537, X86_CMPXCHG32rm = 538, X86_CMPXCHG32rr = 539, X86_CMPXCHG64rm = 540, X86_CMPXCHG64rr = 541, X86_CMPXCHG8B = 542, X86_CMPXCHG8rm = 543, X86_CMPXCHG8rr = 544, X86_CPUID = 545, X86_CQO = 546, X86_CWD = 547, X86_CWDE = 548, X86_DAA = 549, X86_DAS = 550, X86_DATA16_PREFIX = 551, X86_DEC16m = 552, X86_DEC16r = 553, X86_DEC16r_alt = 554, X86_DEC32m = 555, X86_DEC32r = 556, X86_DEC32r_alt = 557, X86_DEC64m = 558, X86_DEC64r = 559, X86_DEC8m = 560, X86_DEC8r = 561, X86_DIV16m = 562, X86_DIV16r = 563, X86_DIV32m = 564, X86_DIV32r = 565, X86_DIV64m = 566, X86_DIV64r = 567, X86_DIV8m = 568, X86_DIV8r = 569, X86_ENDBR32 = 570, X86_ENDBR64 = 571, X86_ENTER = 572, X86_FARCALL16i = 573, X86_FARCALL16m = 574, X86_FARCALL32i = 575, X86_FARCALL32m = 576, X86_FARCALL64 = 577, X86_FARJMP16i = 578, X86_FARJMP16m = 579, X86_FARJMP32i = 580, X86_FARJMP32m = 581, X86_FARJMP64 = 582, X86_FSETPM = 583, X86_GETSEC = 584, X86_HLT = 585, X86_IDIV16m = 586, X86_IDIV16r = 587, X86_IDIV32m = 588, X86_IDIV32r = 589, X86_IDIV64m = 590, X86_IDIV64r = 591, X86_IDIV8m = 592, X86_IDIV8r = 593, X86_IMUL16m = 594, X86_IMUL16r = 595, X86_IMUL16rm = 596, X86_IMUL16rmi = 597, X86_IMUL16rmi8 = 598, X86_IMUL16rr = 599, X86_IMUL16rri = 600, X86_IMUL16rri8 = 601, X86_IMUL32m = 602, X86_IMUL32r = 603, X86_IMUL32rm = 604, X86_IMUL32rmi = 605, X86_IMUL32rmi8 = 606, X86_IMUL32rr = 607, X86_IMUL32rri = 608, X86_IMUL32rri8 = 609, X86_IMUL64m = 610, X86_IMUL64r = 611, X86_IMUL64rm = 612, X86_IMUL64rmi32 = 613, X86_IMUL64rmi8 = 614, X86_IMUL64rr = 615, X86_IMUL64rri32 = 616, X86_IMUL64rri8 = 617, X86_IMUL8m = 618, X86_IMUL8r = 619, X86_IN16ri = 620, X86_IN16rr = 621, X86_IN32ri = 622, X86_IN32rr = 623, X86_IN8ri = 624, X86_IN8rr = 625, X86_INC16m = 626, X86_INC16r = 627, X86_INC16r_alt = 628, X86_INC32m = 629, X86_INC32r = 630, X86_INC32r_alt = 631, X86_INC64m = 632, X86_INC64r = 633, X86_INC8m = 634, X86_INC8r = 635, X86_INCSSPD = 636, X86_INCSSPQ = 637, X86_INSB = 638, X86_INSL = 639, X86_INSW = 640, X86_INT = 641, X86_INT1 = 642, X86_INT3 = 643, X86_INTO = 644, X86_INVD = 645, X86_INVEPT32 = 646, X86_INVEPT64 = 647, X86_INVLPG = 648, X86_INVLPGA32 = 649, X86_INVLPGA64 = 650, X86_INVPCID32 = 651, X86_INVPCID64 = 652, X86_INVVPID32 = 653, X86_INVVPID64 = 654, X86_IRET16 = 655, X86_IRET32 = 656, X86_IRET64 = 657, X86_JAE_1 = 658, X86_JAE_2 = 659, X86_JAE_4 = 660, X86_JA_1 = 661, X86_JA_2 = 662, X86_JA_4 = 663, X86_JBE_1 = 664, X86_JBE_2 = 665, X86_JBE_4 = 666, X86_JB_1 = 667, X86_JB_2 = 668, X86_JB_4 = 669, X86_JCXZ = 670, X86_JECXZ = 671, X86_JE_1 = 672, X86_JE_2 = 673, X86_JE_4 = 674, X86_JGE_1 = 675, X86_JGE_2 = 676, X86_JGE_4 = 677, X86_JG_1 = 678, X86_JG_2 = 679, X86_JG_4 = 680, X86_JLE_1 = 681, X86_JLE_2 = 682, X86_JLE_4 = 683, X86_JL_1 = 684, X86_JL_2 = 685, X86_JL_4 = 686, X86_JMP16m = 687, X86_JMP16m_NT = 688, X86_JMP16r = 689, X86_JMP16r_NT = 690, X86_JMP32m = 691, X86_JMP32m_NT = 692, X86_JMP32r = 693, X86_JMP32r_NT = 694, X86_JMP64m = 695, X86_JMP64m_NT = 696, X86_JMP64r = 697, X86_JMP64r_NT = 698, X86_JMP_1 = 699, X86_JMP_2 = 700, X86_JMP_4 = 701, X86_JNE_1 = 702, X86_JNE_2 = 703, X86_JNE_4 = 704, X86_JNO_1 = 705, X86_JNO_2 = 706, X86_JNO_4 = 707, X86_JNP_1 = 708, X86_JNP_2 = 709, X86_JNP_4 = 710, X86_JNS_1 = 711, X86_JNS_2 = 712, X86_JNS_4 = 713, X86_JO_1 = 714, X86_JO_2 = 715, X86_JO_4 = 716, X86_JP_1 = 717, X86_JP_2 = 718, X86_JP_4 = 719, X86_JRCXZ = 720, X86_JS_1 = 721, X86_JS_2 = 722, X86_JS_4 = 723, X86_LAHF = 724, X86_LAR16rm = 725, X86_LAR16rr = 726, X86_LAR32rm = 727, X86_LAR32rr = 728, X86_LAR64rm = 729, X86_LAR64rr = 730, X86_LDS16rm = 731, X86_LDS32rm = 732, X86_LEA16r = 733, X86_LEA32r = 734, X86_LEA64_32r = 735, X86_LEA64r = 736, X86_LEAVE = 737, X86_LEAVE64 = 738, X86_LES16rm = 739, X86_LES32rm = 740, X86_LFS16rm = 741, X86_LFS32rm = 742, X86_LFS64rm = 743, X86_LGDT16m = 744, X86_LGDT32m = 745, X86_LGDT64m = 746, X86_LGS16rm = 747, X86_LGS32rm = 748, X86_LGS64rm = 749, X86_LIDT16m = 750, X86_LIDT32m = 751, X86_LIDT64m = 752, X86_LLDT16m = 753, X86_LLDT16r = 754, X86_LLWPCB = 755, X86_LLWPCB64 = 756, X86_LMSW16m = 757, X86_LMSW16r = 758, X86_LOCK_PREFIX = 759, X86_LODSB = 760, X86_LODSL = 761, X86_LODSQ = 762, X86_LODSW = 763, X86_LOOP = 764, X86_LOOPE = 765, X86_LOOPNE = 766, X86_LRETIL = 767, X86_LRETIQ = 768, X86_LRETIW = 769, X86_LRETL = 770, X86_LRETQ = 771, X86_LRETW = 772, X86_LSL16rm = 773, X86_LSL16rr = 774, X86_LSL32rm = 775, X86_LSL32rr = 776, X86_LSL64rm = 777, X86_LSL64rr = 778, X86_LSS16rm = 779, X86_LSS32rm = 780, X86_LSS64rm = 781, X86_LTRm = 782, X86_LTRr = 783, X86_LWPINS32rmi = 784, X86_LWPINS32rri = 785, X86_LWPINS64rmi = 786, X86_LWPINS64rri = 787, X86_LWPVAL32rmi = 788, X86_LWPVAL32rri = 789, X86_LWPVAL64rmi = 790, X86_LWPVAL64rri = 791, X86_LZCNT16rm = 792, X86_LZCNT16rr = 793, X86_LZCNT32rm = 794, X86_LZCNT32rr = 795, X86_LZCNT64rm = 796, X86_LZCNT64rr = 797, X86_MONITORXrrr = 798, X86_MONTMUL = 799, X86_MOV16ao16 = 800, X86_MOV16ao32 = 801, X86_MOV16ao64 = 802, X86_MOV16mi = 803, X86_MOV16mr = 804, X86_MOV16ms = 805, X86_MOV16o16a = 806, X86_MOV16o32a = 807, X86_MOV16o64a = 808, X86_MOV16ri = 809, X86_MOV16ri_alt = 810, X86_MOV16rm = 811, X86_MOV16rr = 812, X86_MOV16rr_REV = 813, X86_MOV16rs = 814, X86_MOV16sm = 815, X86_MOV16sr = 816, X86_MOV32ao16 = 817, X86_MOV32ao32 = 818, X86_MOV32ao64 = 819, X86_MOV32cr = 820, X86_MOV32dr = 821, X86_MOV32mi = 822, X86_MOV32mr = 823, X86_MOV32o16a = 824, X86_MOV32o32a = 825, X86_MOV32o64a = 826, X86_MOV32rc = 827, X86_MOV32rd = 828, X86_MOV32ri = 829, X86_MOV32ri_alt = 830, X86_MOV32rm = 831, X86_MOV32rr = 832, X86_MOV32rr_REV = 833, X86_MOV32rs = 834, X86_MOV32sr = 835, X86_MOV64ao32 = 836, X86_MOV64ao64 = 837, X86_MOV64cr = 838, X86_MOV64dr = 839, X86_MOV64mi32 = 840, X86_MOV64mr = 841, X86_MOV64o32a = 842, X86_MOV64o64a = 843, X86_MOV64rc = 844, X86_MOV64rd = 845, X86_MOV64ri = 846, X86_MOV64ri32 = 847, X86_MOV64rm = 848, X86_MOV64rr = 849, X86_MOV64rr_REV = 850, X86_MOV64rs = 851, X86_MOV64sr = 852, X86_MOV8ao16 = 853, X86_MOV8ao32 = 854, X86_MOV8ao64 = 855, X86_MOV8mi = 856, X86_MOV8mr = 857, X86_MOV8mr_NOREX = 858, X86_MOV8o16a = 859, X86_MOV8o32a = 860, X86_MOV8o64a = 861, X86_MOV8ri = 862, X86_MOV8ri_alt = 863, X86_MOV8rm = 864, X86_MOV8rm_NOREX = 865, X86_MOV8rr = 866, X86_MOV8rr_NOREX = 867, X86_MOV8rr_REV = 868, X86_MOVBE16mr = 869, X86_MOVBE16rm = 870, X86_MOVBE32mr = 871, X86_MOVBE32rm = 872, X86_MOVBE64mr = 873, X86_MOVBE64rm = 874, X86_MOVDIR64B16 = 875, X86_MOVDIR64B32 = 876, X86_MOVDIR64B64 = 877, X86_MOVDIRI32 = 878, X86_MOVDIRI64 = 879, X86_MOVSB = 880, X86_MOVSL = 881, X86_MOVSQ = 882, X86_MOVSW = 883, X86_MOVSX16rm16 = 884, X86_MOVSX16rm8 = 885, X86_MOVSX16rr16 = 886, X86_MOVSX16rr8 = 887, X86_MOVSX32rm16 = 888, X86_MOVSX32rm8 = 889, X86_MOVSX32rm8_NOREX = 890, X86_MOVSX32rr16 = 891, X86_MOVSX32rr8 = 892, X86_MOVSX32rr8_NOREX = 893, X86_MOVSX64rm16 = 894, X86_MOVSX64rm32 = 895, X86_MOVSX64rm8 = 896, X86_MOVSX64rr16 = 897, X86_MOVSX64rr32 = 898, X86_MOVSX64rr8 = 899, X86_MOVZX16rm16 = 900, X86_MOVZX16rm8 = 901, X86_MOVZX16rr16 = 902, X86_MOVZX16rr8 = 903, X86_MOVZX32rm16 = 904, X86_MOVZX32rm8 = 905, X86_MOVZX32rm8_NOREX = 906, X86_MOVZX32rr16 = 907, X86_MOVZX32rr8 = 908, X86_MOVZX32rr8_NOREX = 909, X86_MOVZX64rm16 = 910, X86_MOVZX64rm8 = 911, X86_MOVZX64rr16 = 912, X86_MOVZX64rr8 = 913, X86_MUL16m = 914, X86_MUL16r = 915, X86_MUL32m = 916, X86_MUL32r = 917, X86_MUL64m = 918, X86_MUL64r = 919, X86_MUL8m = 920, X86_MUL8r = 921, X86_MULX32rm = 922, X86_MULX32rr = 923, X86_MULX64rm = 924, X86_MULX64rr = 925, X86_MWAITXrrr = 926, X86_NEG16m = 927, X86_NEG16r = 928, X86_NEG32m = 929, X86_NEG32r = 930, X86_NEG64m = 931, X86_NEG64r = 932, X86_NEG8m = 933, X86_NEG8r = 934, X86_NOOP = 935, X86_NOOP18_16m4 = 936, X86_NOOP18_16m5 = 937, X86_NOOP18_16m6 = 938, X86_NOOP18_16m7 = 939, X86_NOOP18_16r4 = 940, X86_NOOP18_16r5 = 941, X86_NOOP18_16r6 = 942, X86_NOOP18_16r7 = 943, X86_NOOP18_m4 = 944, X86_NOOP18_m5 = 945, X86_NOOP18_m6 = 946, X86_NOOP18_m7 = 947, X86_NOOP18_r4 = 948, X86_NOOP18_r5 = 949, X86_NOOP18_r6 = 950, X86_NOOP18_r7 = 951, X86_NOOP19rr = 952, X86_NOOPL = 953, X86_NOOPL_19 = 954, X86_NOOPL_1d = 955, X86_NOOPL_1e = 956, X86_NOOPLr = 957, X86_NOOPQ = 958, X86_NOOPQr = 959, X86_NOOPW = 960, X86_NOOPW_19 = 961, X86_NOOPW_1c = 962, X86_NOOPW_1d = 963, X86_NOOPW_1e = 964, X86_NOOPWr = 965, X86_NOT16m = 966, X86_NOT16r = 967, X86_NOT32m = 968, X86_NOT32r = 969, X86_NOT64m = 970, X86_NOT64r = 971, X86_NOT8m = 972, X86_NOT8r = 973, X86_OR16i16 = 974, X86_OR16mi = 975, X86_OR16mi8 = 976, X86_OR16mr = 977, X86_OR16ri = 978, X86_OR16ri8 = 979, X86_OR16rm = 980, X86_OR16rr = 981, X86_OR16rr_REV = 982, X86_OR32i32 = 983, X86_OR32mi = 984, X86_OR32mi8 = 985, X86_OR32mr = 986, X86_OR32ri = 987, X86_OR32ri8 = 988, X86_OR32rm = 989, X86_OR32rr = 990, X86_OR32rr_REV = 991, X86_OR64i32 = 992, X86_OR64mi32 = 993, X86_OR64mi8 = 994, X86_OR64mr = 995, X86_OR64ri32 = 996, X86_OR64ri8 = 997, X86_OR64rm = 998, X86_OR64rr = 999, X86_OR64rr_REV = 1000, X86_OR8i8 = 1001, X86_OR8mi = 1002, X86_OR8mi8 = 1003, X86_OR8mr = 1004, X86_OR8ri = 1005, X86_OR8ri8 = 1006, X86_OR8rm = 1007, X86_OR8rr = 1008, X86_OR8rr_REV = 1009, X86_OUT16ir = 1010, X86_OUT16rr = 1011, X86_OUT32ir = 1012, X86_OUT32rr = 1013, X86_OUT8ir = 1014, X86_OUT8rr = 1015, X86_OUTSB = 1016, X86_OUTSL = 1017, X86_OUTSW = 1018, X86_PCONFIG = 1019, X86_PDEP32rm = 1020, X86_PDEP32rr = 1021, X86_PDEP64rm = 1022, X86_PDEP64rr = 1023, X86_PEXT32rm = 1024, X86_PEXT32rr = 1025, X86_PEXT64rm = 1026, X86_PEXT64rr = 1027, X86_POP16r = 1028, X86_POP16rmm = 1029, X86_POP16rmr = 1030, X86_POP32r = 1031, X86_POP32rmm = 1032, X86_POP32rmr = 1033, X86_POP64r = 1034, X86_POP64rmm = 1035, X86_POP64rmr = 1036, X86_POPA16 = 1037, X86_POPA32 = 1038, X86_POPDS16 = 1039, X86_POPDS32 = 1040, X86_POPES16 = 1041, X86_POPES32 = 1042, X86_POPF16 = 1043, X86_POPF32 = 1044, X86_POPF64 = 1045, X86_POPFS16 = 1046, X86_POPFS32 = 1047, X86_POPFS64 = 1048, X86_POPGS16 = 1049, X86_POPGS32 = 1050, X86_POPGS64 = 1051, X86_POPSS16 = 1052, X86_POPSS32 = 1053, X86_PTWRITE64m = 1054, X86_PTWRITE64r = 1055, X86_PTWRITEm = 1056, X86_PTWRITEr = 1057, X86_PUSH16i8 = 1058, X86_PUSH16r = 1059, X86_PUSH16rmm = 1060, X86_PUSH16rmr = 1061, X86_PUSH32i8 = 1062, X86_PUSH32r = 1063, X86_PUSH32rmm = 1064, X86_PUSH32rmr = 1065, X86_PUSH64i32 = 1066, X86_PUSH64i8 = 1067, X86_PUSH64r = 1068, X86_PUSH64rmm = 1069, X86_PUSH64rmr = 1070, X86_PUSHA16 = 1071, X86_PUSHA32 = 1072, X86_PUSHCS16 = 1073, X86_PUSHCS32 = 1074, X86_PUSHDS16 = 1075, X86_PUSHDS32 = 1076, X86_PUSHES16 = 1077, X86_PUSHES32 = 1078, X86_PUSHF16 = 1079, X86_PUSHF32 = 1080, X86_PUSHF64 = 1081, X86_PUSHFS16 = 1082, X86_PUSHFS32 = 1083, X86_PUSHFS64 = 1084, X86_PUSHGS16 = 1085, X86_PUSHGS32 = 1086, X86_PUSHGS64 = 1087, X86_PUSHSS16 = 1088, X86_PUSHSS32 = 1089, X86_PUSHi16 = 1090, X86_PUSHi32 = 1091, X86_RCL16m1 = 1092, X86_RCL16mCL = 1093, X86_RCL16mi = 1094, X86_RCL16r1 = 1095, X86_RCL16rCL = 1096, X86_RCL16ri = 1097, X86_RCL32m1 = 1098, X86_RCL32mCL = 1099, X86_RCL32mi = 1100, X86_RCL32r1 = 1101, X86_RCL32rCL = 1102, X86_RCL32ri = 1103, X86_RCL64m1 = 1104, X86_RCL64mCL = 1105, X86_RCL64mi = 1106, X86_RCL64r1 = 1107, X86_RCL64rCL = 1108, X86_RCL64ri = 1109, X86_RCL8m1 = 1110, X86_RCL8mCL = 1111, X86_RCL8mi = 1112, X86_RCL8r1 = 1113, X86_RCL8rCL = 1114, X86_RCL8ri = 1115, X86_RCR16m1 = 1116, X86_RCR16mCL = 1117, X86_RCR16mi = 1118, X86_RCR16r1 = 1119, X86_RCR16rCL = 1120, X86_RCR16ri = 1121, X86_RCR32m1 = 1122, X86_RCR32mCL = 1123, X86_RCR32mi = 1124, X86_RCR32r1 = 1125, X86_RCR32rCL = 1126, X86_RCR32ri = 1127, X86_RCR64m1 = 1128, X86_RCR64mCL = 1129, X86_RCR64mi = 1130, X86_RCR64r1 = 1131, X86_RCR64rCL = 1132, X86_RCR64ri = 1133, X86_RCR8m1 = 1134, X86_RCR8mCL = 1135, X86_RCR8mi = 1136, X86_RCR8r1 = 1137, X86_RCR8rCL = 1138, X86_RCR8ri = 1139, X86_RDFSBASE = 1140, X86_RDFSBASE64 = 1141, X86_RDGSBASE = 1142, X86_RDGSBASE64 = 1143, X86_RDMSR = 1144, X86_RDPID32 = 1145, X86_RDPID64 = 1146, X86_RDPKRUr = 1147, X86_RDPMC = 1148, X86_RDRAND16r = 1149, X86_RDRAND32r = 1150, X86_RDRAND64r = 1151, X86_RDSEED16r = 1152, X86_RDSEED32r = 1153, X86_RDSEED64r = 1154, X86_RDSSPD = 1155, X86_RDSSPQ = 1156, X86_RDTSC = 1157, X86_RDTSCP = 1158, X86_REPNE_PREFIX = 1159, X86_REP_PREFIX = 1160, X86_RETIL = 1161, X86_RETIQ = 1162, X86_RETIW = 1163, X86_RETL = 1164, X86_RETQ = 1165, X86_RETW = 1166, X86_REX64_PREFIX = 1167, X86_ROL16m1 = 1168, X86_ROL16mCL = 1169, X86_ROL16mi = 1170, X86_ROL16r1 = 1171, X86_ROL16rCL = 1172, X86_ROL16ri = 1173, X86_ROL32m1 = 1174, X86_ROL32mCL = 1175, X86_ROL32mi = 1176, X86_ROL32r1 = 1177, X86_ROL32rCL = 1178, X86_ROL32ri = 1179, X86_ROL64m1 = 1180, X86_ROL64mCL = 1181, X86_ROL64mi = 1182, X86_ROL64r1 = 1183, X86_ROL64rCL = 1184, X86_ROL64ri = 1185, X86_ROL8m1 = 1186, X86_ROL8mCL = 1187, X86_ROL8mi = 1188, X86_ROL8r1 = 1189, X86_ROL8rCL = 1190, X86_ROL8ri = 1191, X86_ROR16m1 = 1192, X86_ROR16mCL = 1193, X86_ROR16mi = 1194, X86_ROR16r1 = 1195, X86_ROR16rCL = 1196, X86_ROR16ri = 1197, X86_ROR32m1 = 1198, X86_ROR32mCL = 1199, X86_ROR32mi = 1200, X86_ROR32r1 = 1201, X86_ROR32rCL = 1202, X86_ROR32ri = 1203, X86_ROR64m1 = 1204, X86_ROR64mCL = 1205, X86_ROR64mi = 1206, X86_ROR64r1 = 1207, X86_ROR64rCL = 1208, X86_ROR64ri = 1209, X86_ROR8m1 = 1210, X86_ROR8mCL = 1211, X86_ROR8mi = 1212, X86_ROR8r1 = 1213, X86_ROR8rCL = 1214, X86_ROR8ri = 1215, X86_RORX32mi = 1216, X86_RORX32ri = 1217, X86_RORX64mi = 1218, X86_RORX64ri = 1219, X86_RSM = 1220, X86_RSTORSSP = 1221, X86_SAHF = 1222, X86_SAL16m1 = 1223, X86_SAL16mCL = 1224, X86_SAL16mi = 1225, X86_SAL16r1 = 1226, X86_SAL16rCL = 1227, X86_SAL16ri = 1228, X86_SAL32m1 = 1229, X86_SAL32mCL = 1230, X86_SAL32mi = 1231, X86_SAL32r1 = 1232, X86_SAL32rCL = 1233, X86_SAL32ri = 1234, X86_SAL64m1 = 1235, X86_SAL64mCL = 1236, X86_SAL64mi = 1237, X86_SAL64r1 = 1238, X86_SAL64rCL = 1239, X86_SAL64ri = 1240, X86_SAL8m1 = 1241, X86_SAL8mCL = 1242, X86_SAL8mi = 1243, X86_SAL8r1 = 1244, X86_SAL8rCL = 1245, X86_SAL8ri = 1246, X86_SALC = 1247, X86_SAR16m1 = 1248, X86_SAR16mCL = 1249, X86_SAR16mi = 1250, X86_SAR16r1 = 1251, X86_SAR16rCL = 1252, X86_SAR16ri = 1253, X86_SAR32m1 = 1254, X86_SAR32mCL = 1255, X86_SAR32mi = 1256, X86_SAR32r1 = 1257, X86_SAR32rCL = 1258, X86_SAR32ri = 1259, X86_SAR64m1 = 1260, X86_SAR64mCL = 1261, X86_SAR64mi = 1262, X86_SAR64r1 = 1263, X86_SAR64rCL = 1264, X86_SAR64ri = 1265, X86_SAR8m1 = 1266, X86_SAR8mCL = 1267, X86_SAR8mi = 1268, X86_SAR8r1 = 1269, X86_SAR8rCL = 1270, X86_SAR8ri = 1271, X86_SARX32rm = 1272, X86_SARX32rr = 1273, X86_SARX64rm = 1274, X86_SARX64rr = 1275, X86_SAVEPREVSSP = 1276, X86_SBB16i16 = 1277, X86_SBB16mi = 1278, X86_SBB16mi8 = 1279, X86_SBB16mr = 1280, X86_SBB16ri = 1281, X86_SBB16ri8 = 1282, X86_SBB16rm = 1283, X86_SBB16rr = 1284, X86_SBB16rr_REV = 1285, X86_SBB32i32 = 1286, X86_SBB32mi = 1287, X86_SBB32mi8 = 1288, X86_SBB32mr = 1289, X86_SBB32ri = 1290, X86_SBB32ri8 = 1291, X86_SBB32rm = 1292, X86_SBB32rr = 1293, X86_SBB32rr_REV = 1294, X86_SBB64i32 = 1295, X86_SBB64mi32 = 1296, X86_SBB64mi8 = 1297, X86_SBB64mr = 1298, X86_SBB64ri32 = 1299, X86_SBB64ri8 = 1300, X86_SBB64rm = 1301, X86_SBB64rr = 1302, X86_SBB64rr_REV = 1303, X86_SBB8i8 = 1304, X86_SBB8mi = 1305, X86_SBB8mi8 = 1306, X86_SBB8mr = 1307, X86_SBB8ri = 1308, X86_SBB8ri8 = 1309, X86_SBB8rm = 1310, X86_SBB8rr = 1311, X86_SBB8rr_REV = 1312, X86_SCASB = 1313, X86_SCASL = 1314, X86_SCASQ = 1315, X86_SCASW = 1316, X86_SETAEm = 1317, X86_SETAEr = 1318, X86_SETAm = 1319, X86_SETAr = 1320, X86_SETBEm = 1321, X86_SETBEr = 1322, X86_SETBm = 1323, X86_SETBr = 1324, X86_SETEm = 1325, X86_SETEr = 1326, X86_SETGEm = 1327, X86_SETGEr = 1328, X86_SETGm = 1329, X86_SETGr = 1330, X86_SETLEm = 1331, X86_SETLEr = 1332, X86_SETLm = 1333, X86_SETLr = 1334, X86_SETNEm = 1335, X86_SETNEr = 1336, X86_SETNOm = 1337, X86_SETNOr = 1338, X86_SETNPm = 1339, X86_SETNPr = 1340, X86_SETNSm = 1341, X86_SETNSr = 1342, X86_SETOm = 1343, X86_SETOr = 1344, X86_SETPm = 1345, X86_SETPr = 1346, X86_SETSSBSY = 1347, X86_SETSm = 1348, X86_SETSr = 1349, X86_SGDT16m = 1350, X86_SGDT32m = 1351, X86_SGDT64m = 1352, X86_SHL16m1 = 1353, X86_SHL16mCL = 1354, X86_SHL16mi = 1355, X86_SHL16r1 = 1356, X86_SHL16rCL = 1357, X86_SHL16ri = 1358, X86_SHL32m1 = 1359, X86_SHL32mCL = 1360, X86_SHL32mi = 1361, X86_SHL32r1 = 1362, X86_SHL32rCL = 1363, X86_SHL32ri = 1364, X86_SHL64m1 = 1365, X86_SHL64mCL = 1366, X86_SHL64mi = 1367, X86_SHL64r1 = 1368, X86_SHL64rCL = 1369, X86_SHL64ri = 1370, X86_SHL8m1 = 1371, X86_SHL8mCL = 1372, X86_SHL8mi = 1373, X86_SHL8r1 = 1374, X86_SHL8rCL = 1375, X86_SHL8ri = 1376, X86_SHLD16mrCL = 1377, X86_SHLD16mri8 = 1378, X86_SHLD16rrCL = 1379, X86_SHLD16rri8 = 1380, X86_SHLD32mrCL = 1381, X86_SHLD32mri8 = 1382, X86_SHLD32rrCL = 1383, X86_SHLD32rri8 = 1384, X86_SHLD64mrCL = 1385, X86_SHLD64mri8 = 1386, X86_SHLD64rrCL = 1387, X86_SHLD64rri8 = 1388, X86_SHLX32rm = 1389, X86_SHLX32rr = 1390, X86_SHLX64rm = 1391, X86_SHLX64rr = 1392, X86_SHR16m1 = 1393, X86_SHR16mCL = 1394, X86_SHR16mi = 1395, X86_SHR16r1 = 1396, X86_SHR16rCL = 1397, X86_SHR16ri = 1398, X86_SHR32m1 = 1399, X86_SHR32mCL = 1400, X86_SHR32mi = 1401, X86_SHR32r1 = 1402, X86_SHR32rCL = 1403, X86_SHR32ri = 1404, X86_SHR64m1 = 1405, X86_SHR64mCL = 1406, X86_SHR64mi = 1407, X86_SHR64r1 = 1408, X86_SHR64rCL = 1409, X86_SHR64ri = 1410, X86_SHR8m1 = 1411, X86_SHR8mCL = 1412, X86_SHR8mi = 1413, X86_SHR8r1 = 1414, X86_SHR8rCL = 1415, X86_SHR8ri = 1416, X86_SHRD16mrCL = 1417, X86_SHRD16mri8 = 1418, X86_SHRD16rrCL = 1419, X86_SHRD16rri8 = 1420, X86_SHRD32mrCL = 1421, X86_SHRD32mri8 = 1422, X86_SHRD32rrCL = 1423, X86_SHRD32rri8 = 1424, X86_SHRD64mrCL = 1425, X86_SHRD64mri8 = 1426, X86_SHRD64rrCL = 1427, X86_SHRD64rri8 = 1428, X86_SHRX32rm = 1429, X86_SHRX32rr = 1430, X86_SHRX64rm = 1431, X86_SHRX64rr = 1432, X86_SIDT16m = 1433, X86_SIDT32m = 1434, X86_SIDT64m = 1435, X86_SKINIT = 1436, X86_SLDT16m = 1437, X86_SLDT16r = 1438, X86_SLDT32r = 1439, X86_SLDT64r = 1440, X86_SLWPCB = 1441, X86_SLWPCB64 = 1442, X86_SMSW16m = 1443, X86_SMSW16r = 1444, X86_SMSW32r = 1445, X86_SMSW64r = 1446, X86_STAC = 1447, X86_STC = 1448, X86_STD = 1449, X86_STGI = 1450, X86_STI = 1451, X86_STOSB = 1452, X86_STOSL = 1453, X86_STOSQ = 1454, X86_STOSW = 1455, X86_STR16r = 1456, X86_STR32r = 1457, X86_STR64r = 1458, X86_STRm = 1459, X86_SUB16i16 = 1460, X86_SUB16mi = 1461, X86_SUB16mi8 = 1462, X86_SUB16mr = 1463, X86_SUB16ri = 1464, X86_SUB16ri8 = 1465, X86_SUB16rm = 1466, X86_SUB16rr = 1467, X86_SUB16rr_REV = 1468, X86_SUB32i32 = 1469, X86_SUB32mi = 1470, X86_SUB32mi8 = 1471, X86_SUB32mr = 1472, X86_SUB32ri = 1473, X86_SUB32ri8 = 1474, X86_SUB32rm = 1475, X86_SUB32rr = 1476, X86_SUB32rr_REV = 1477, X86_SUB64i32 = 1478, X86_SUB64mi32 = 1479, X86_SUB64mi8 = 1480, X86_SUB64mr = 1481, X86_SUB64ri32 = 1482, X86_SUB64ri8 = 1483, X86_SUB64rm = 1484, X86_SUB64rr = 1485, X86_SUB64rr_REV = 1486, X86_SUB8i8 = 1487, X86_SUB8mi = 1488, X86_SUB8mi8 = 1489, X86_SUB8mr = 1490, X86_SUB8ri = 1491, X86_SUB8ri8 = 1492, X86_SUB8rm = 1493, X86_SUB8rr = 1494, X86_SUB8rr_REV = 1495, X86_SWAPGS = 1496, X86_SYSCALL = 1497, X86_SYSENTER = 1498, X86_SYSEXIT = 1499, X86_SYSEXIT64 = 1500, X86_SYSRET = 1501, X86_SYSRET64 = 1502, X86_T1MSKC32rm = 1503, X86_T1MSKC32rr = 1504, X86_T1MSKC64rm = 1505, X86_T1MSKC64rr = 1506, X86_TEST16i16 = 1507, X86_TEST16mi = 1508, X86_TEST16mi_alt = 1509, X86_TEST16mr = 1510, X86_TEST16ri = 1511, X86_TEST16ri_alt = 1512, X86_TEST16rr = 1513, X86_TEST32i32 = 1514, X86_TEST32mi = 1515, X86_TEST32mi_alt = 1516, X86_TEST32mr = 1517, X86_TEST32ri = 1518, X86_TEST32ri_alt = 1519, X86_TEST32rr = 1520, X86_TEST64i32 = 1521, X86_TEST64mi32 = 1522, X86_TEST64mi32_alt = 1523, X86_TEST64mr = 1524, X86_TEST64ri32 = 1525, X86_TEST64ri32_alt = 1526, X86_TEST64rr = 1527, X86_TEST8i8 = 1528, X86_TEST8mi = 1529, X86_TEST8mi_alt = 1530, X86_TEST8mr = 1531, X86_TEST8ri = 1532, X86_TEST8ri_alt = 1533, X86_TEST8rr = 1534, X86_TPAUSE = 1535, X86_TZCNT16rm = 1536, X86_TZCNT16rr = 1537, X86_TZCNT32rm = 1538, X86_TZCNT32rr = 1539, X86_TZCNT64rm = 1540, X86_TZCNT64rr = 1541, X86_TZMSK32rm = 1542, X86_TZMSK32rr = 1543, X86_TZMSK64rm = 1544, X86_TZMSK64rr = 1545, X86_UD0 = 1546, X86_UD1 = 1547, X86_UD2 = 1548, X86_UMONITOR16 = 1549, X86_UMONITOR32 = 1550, X86_UMONITOR64 = 1551, X86_UMWAIT = 1552, X86_VERRm = 1553, X86_VERRr = 1554, X86_VERWm = 1555, X86_VERWr = 1556, X86_VMCALL = 1557, X86_VMCLEARm = 1558, X86_VMFUNC = 1559, X86_VMLAUNCH = 1560, X86_VMLOAD32 = 1561, X86_VMLOAD64 = 1562, X86_VMMCALL = 1563, X86_VMPTRLDm = 1564, X86_VMPTRSTm = 1565, X86_VMREAD32mr = 1566, X86_VMREAD32rr = 1567, X86_VMREAD64mr = 1568, X86_VMREAD64rr = 1569, X86_VMRESUME = 1570, X86_VMRUN32 = 1571, X86_VMRUN64 = 1572, X86_VMSAVE32 = 1573, X86_VMSAVE64 = 1574, X86_VMWRITE32rm = 1575, X86_VMWRITE32rr = 1576, X86_VMWRITE64rm = 1577, X86_VMWRITE64rr = 1578, X86_VMXOFF = 1579, X86_VMXON = 1580, X86_WBINVD = 1581, X86_WBNOINVD = 1582, X86_WRFSBASE = 1583, X86_WRFSBASE64 = 1584, X86_WRGSBASE = 1585, X86_WRGSBASE64 = 1586, X86_WRMSR = 1587, X86_WRPKRUr = 1588, X86_WRSSD = 1589, X86_WRSSQ = 1590, X86_WRUSSD = 1591, X86_WRUSSQ = 1592, X86_XADD16rm = 1593, X86_XADD16rr = 1594, X86_XADD32rm = 1595, X86_XADD32rr = 1596, X86_XADD64rm = 1597, X86_XADD64rr = 1598, X86_XADD8rm = 1599, X86_XADD8rr = 1600, X86_XCHG16ar = 1601, X86_XCHG16rm = 1602, X86_XCHG16rr = 1603, X86_XCHG32ar = 1604, X86_XCHG32rm = 1605, X86_XCHG32rr = 1606, X86_XCHG64ar = 1607, X86_XCHG64rm = 1608, X86_XCHG64rr = 1609, X86_XCHG8rm = 1610, X86_XCHG8rr = 1611, X86_XCRYPTCBC = 1612, X86_XCRYPTCFB = 1613, X86_XCRYPTCTR = 1614, X86_XCRYPTECB = 1615, X86_XCRYPTOFB = 1616, X86_XGETBV = 1617, X86_XLAT = 1618, X86_XOR16i16 = 1619, X86_XOR16mi = 1620, X86_XOR16mi8 = 1621, X86_XOR16mr = 1622, X86_XOR16ri = 1623, X86_XOR16ri8 = 1624, X86_XOR16rm = 1625, X86_XOR16rr = 1626, X86_XOR16rr_REV = 1627, X86_XOR32i32 = 1628, X86_XOR32mi = 1629, X86_XOR32mi8 = 1630, X86_XOR32mr = 1631, X86_XOR32ri = 1632, X86_XOR32ri8 = 1633, X86_XOR32rm = 1634, X86_XOR32rr = 1635, X86_XOR32rr_REV = 1636, X86_XOR64i32 = 1637, X86_XOR64mi32 = 1638, X86_XOR64mi8 = 1639, X86_XOR64mr = 1640, X86_XOR64ri32 = 1641, X86_XOR64ri8 = 1642, X86_XOR64rm = 1643, X86_XOR64rr = 1644, X86_XOR64rr_REV = 1645, X86_XOR8i8 = 1646, X86_XOR8mi = 1647, X86_XOR8mi8 = 1648, X86_XOR8mr = 1649, X86_XOR8ri = 1650, X86_XOR8ri8 = 1651, X86_XOR8rm = 1652, X86_XOR8rr = 1653, X86_XOR8rr_REV = 1654, X86_XRSTOR = 1655, X86_XRSTOR64 = 1656, X86_XRSTORS = 1657, X86_XRSTORS64 = 1658, X86_XSAVE = 1659, X86_XSAVE64 = 1660, X86_XSAVEC = 1661, X86_XSAVEC64 = 1662, X86_XSAVEOPT = 1663, X86_XSAVEOPT64 = 1664, X86_XSAVES = 1665, X86_XSAVES64 = 1666, X86_XSETBV = 1667, X86_XSHA1 = 1668, X86_XSHA256 = 1669, X86_XSTORE = 1670, X86_INSTRUCTION_LIST_END = 1671 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/X86/X86GenRegisterInfo.inc000064400000000000000000001562040072674642500215500ustar 00000000000000 /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { X86_NoRegister, X86_AH = 1, X86_AL = 2, X86_AX = 3, X86_BH = 4, X86_BL = 5, X86_BP = 6, X86_BPH = 7, X86_BPL = 8, X86_BX = 9, X86_CH = 10, X86_CL = 11, X86_CS = 12, X86_CX = 13, X86_DF = 14, X86_DH = 15, X86_DI = 16, X86_DIH = 17, X86_DIL = 18, X86_DL = 19, X86_DS = 20, X86_DX = 21, X86_EAX = 22, X86_EBP = 23, X86_EBX = 24, X86_ECX = 25, X86_EDI = 26, X86_EDX = 27, X86_EFLAGS = 28, X86_EIP = 29, X86_EIZ = 30, X86_ES = 31, X86_ESI = 32, X86_ESP = 33, X86_FPSW = 34, X86_FS = 35, X86_GS = 36, X86_HAX = 37, X86_HBP = 38, X86_HBX = 39, X86_HCX = 40, X86_HDI = 41, X86_HDX = 42, X86_HIP = 43, X86_HSI = 44, X86_HSP = 45, X86_IP = 46, X86_RAX = 47, X86_RBP = 48, X86_RBX = 49, X86_RCX = 50, X86_RDI = 51, X86_RDX = 52, X86_RIP = 53, X86_RIZ = 54, X86_RSI = 55, X86_RSP = 56, X86_SI = 57, X86_SIH = 58, X86_SIL = 59, X86_SP = 60, X86_SPH = 61, X86_SPL = 62, X86_SS = 63, X86_SSP = 64, X86_BND0 = 65, X86_BND1 = 66, X86_BND2 = 67, X86_BND3 = 68, X86_CR0 = 69, X86_CR1 = 70, X86_CR2 = 71, X86_CR3 = 72, X86_CR4 = 73, X86_CR5 = 74, X86_CR6 = 75, X86_CR7 = 76, X86_CR8 = 77, X86_CR9 = 78, X86_CR10 = 79, X86_CR11 = 80, X86_CR12 = 81, X86_CR13 = 82, X86_CR14 = 83, X86_CR15 = 84, X86_DR0 = 85, X86_DR1 = 86, X86_DR2 = 87, X86_DR3 = 88, X86_DR4 = 89, X86_DR5 = 90, X86_DR6 = 91, X86_DR7 = 92, X86_DR8 = 93, X86_DR9 = 94, X86_DR10 = 95, X86_DR11 = 96, X86_DR12 = 97, X86_DR13 = 98, X86_DR14 = 99, X86_DR15 = 100, X86_FP0 = 101, X86_FP1 = 102, X86_FP2 = 103, X86_FP3 = 104, X86_FP4 = 105, X86_FP5 = 106, X86_FP6 = 107, X86_FP7 = 108, X86_K0 = 109, X86_K1 = 110, X86_K2 = 111, X86_K3 = 112, X86_K4 = 113, X86_K5 = 114, X86_K6 = 115, X86_K7 = 116, X86_MM0 = 117, X86_MM1 = 118, X86_MM2 = 119, X86_MM3 = 120, X86_MM4 = 121, X86_MM5 = 122, X86_MM6 = 123, X86_MM7 = 124, X86_R8 = 125, X86_R9 = 126, X86_R10 = 127, X86_R11 = 128, X86_R12 = 129, X86_R13 = 130, X86_R14 = 131, X86_R15 = 132, X86_ST0 = 133, X86_ST1 = 134, X86_ST2 = 135, X86_ST3 = 136, X86_ST4 = 137, X86_ST5 = 138, X86_ST6 = 139, X86_ST7 = 140, X86_XMM0 = 141, X86_XMM1 = 142, X86_XMM2 = 143, X86_XMM3 = 144, X86_XMM4 = 145, X86_XMM5 = 146, X86_XMM6 = 147, X86_XMM7 = 148, X86_XMM8 = 149, X86_XMM9 = 150, X86_XMM10 = 151, X86_XMM11 = 152, X86_XMM12 = 153, X86_XMM13 = 154, X86_XMM14 = 155, X86_XMM15 = 156, X86_XMM16 = 157, X86_XMM17 = 158, X86_XMM18 = 159, X86_XMM19 = 160, X86_XMM20 = 161, X86_XMM21 = 162, X86_XMM22 = 163, X86_XMM23 = 164, X86_XMM24 = 165, X86_XMM25 = 166, X86_XMM26 = 167, X86_XMM27 = 168, X86_XMM28 = 169, X86_XMM29 = 170, X86_XMM30 = 171, X86_XMM31 = 172, X86_YMM0 = 173, X86_YMM1 = 174, X86_YMM2 = 175, X86_YMM3 = 176, X86_YMM4 = 177, X86_YMM5 = 178, X86_YMM6 = 179, X86_YMM7 = 180, X86_YMM8 = 181, X86_YMM9 = 182, X86_YMM10 = 183, X86_YMM11 = 184, X86_YMM12 = 185, X86_YMM13 = 186, X86_YMM14 = 187, X86_YMM15 = 188, X86_YMM16 = 189, X86_YMM17 = 190, X86_YMM18 = 191, X86_YMM19 = 192, X86_YMM20 = 193, X86_YMM21 = 194, X86_YMM22 = 195, X86_YMM23 = 196, X86_YMM24 = 197, X86_YMM25 = 198, X86_YMM26 = 199, X86_YMM27 = 200, X86_YMM28 = 201, X86_YMM29 = 202, X86_YMM30 = 203, X86_YMM31 = 204, X86_ZMM0 = 205, X86_ZMM1 = 206, X86_ZMM2 = 207, X86_ZMM3 = 208, X86_ZMM4 = 209, X86_ZMM5 = 210, X86_ZMM6 = 211, X86_ZMM7 = 212, X86_ZMM8 = 213, X86_ZMM9 = 214, X86_ZMM10 = 215, X86_ZMM11 = 216, X86_ZMM12 = 217, X86_ZMM13 = 218, X86_ZMM14 = 219, X86_ZMM15 = 220, X86_ZMM16 = 221, X86_ZMM17 = 222, X86_ZMM18 = 223, X86_ZMM19 = 224, X86_ZMM20 = 225, X86_ZMM21 = 226, X86_ZMM22 = 227, X86_ZMM23 = 228, X86_ZMM24 = 229, X86_ZMM25 = 230, X86_ZMM26 = 231, X86_ZMM27 = 232, X86_ZMM28 = 233, X86_ZMM29 = 234, X86_ZMM30 = 235, X86_ZMM31 = 236, X86_R8B = 237, X86_R9B = 238, X86_R10B = 239, X86_R11B = 240, X86_R12B = 241, X86_R13B = 242, X86_R14B = 243, X86_R15B = 244, X86_R8BH = 245, X86_R9BH = 246, X86_R10BH = 247, X86_R11BH = 248, X86_R12BH = 249, X86_R13BH = 250, X86_R14BH = 251, X86_R15BH = 252, X86_R8D = 253, X86_R9D = 254, X86_R10D = 255, X86_R11D = 256, X86_R12D = 257, X86_R13D = 258, X86_R14D = 259, X86_R15D = 260, X86_R8W = 261, X86_R9W = 262, X86_R10W = 263, X86_R11W = 264, X86_R12W = 265, X86_R13W = 266, X86_R14W = 267, X86_R15W = 268, X86_R8WH = 269, X86_R9WH = 270, X86_R10WH = 271, X86_R11WH = 272, X86_R12WH = 273, X86_R13WH = 274, X86_R14WH = 275, X86_R15WH = 276, X86_NUM_TARGET_REGS // 277 }; // Register classes enum { X86_GR8RegClassID = 0, X86_GRH8RegClassID = 1, X86_GR8_NOREXRegClassID = 2, X86_GR8_ABCD_HRegClassID = 3, X86_GR8_ABCD_LRegClassID = 4, X86_GRH16RegClassID = 5, X86_GR16RegClassID = 6, X86_GR16_NOREXRegClassID = 7, X86_VK1RegClassID = 8, X86_VK16RegClassID = 9, X86_VK2RegClassID = 10, X86_VK4RegClassID = 11, X86_VK8RegClassID = 12, X86_VK16WMRegClassID = 13, X86_VK1WMRegClassID = 14, X86_VK2WMRegClassID = 15, X86_VK4WMRegClassID = 16, X86_VK8WMRegClassID = 17, X86_SEGMENT_REGRegClassID = 18, X86_GR16_ABCDRegClassID = 19, X86_FPCCRRegClassID = 20, X86_FR32XRegClassID = 21, X86_LOW32_ADDR_ACCESS_RBPRegClassID = 22, X86_LOW32_ADDR_ACCESSRegClassID = 23, X86_LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 24, X86_DEBUG_REGRegClassID = 25, X86_FR32RegClassID = 26, X86_GR32RegClassID = 27, X86_GR32_NOSPRegClassID = 28, X86_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 29, X86_GR32_NOREXRegClassID = 30, X86_VK32RegClassID = 31, X86_GR32_NOREX_NOSPRegClassID = 32, X86_RFP32RegClassID = 33, X86_VK32WMRegClassID = 34, X86_GR32_ABCDRegClassID = 35, X86_GR32_TCRegClassID = 36, X86_GR32_ADRegClassID = 37, X86_LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 38, X86_CCRRegClassID = 39, X86_DFCCRRegClassID = 40, X86_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 41, X86_LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 42, X86_RFP64RegClassID = 43, X86_FR64XRegClassID = 44, X86_GR64RegClassID = 45, X86_CONTROL_REGRegClassID = 46, X86_FR64RegClassID = 47, X86_GR64_with_sub_8bitRegClassID = 48, X86_GR64_NOSPRegClassID = 49, X86_GR64_NOREXRegClassID = 50, X86_GR64_TCRegClassID = 51, X86_GR64_NOSP_and_GR64_TCRegClassID = 52, X86_GR64_TCW64RegClassID = 53, X86_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 54, X86_VK64RegClassID = 55, X86_VR64RegClassID = 56, X86_GR64_NOREX_NOSPRegClassID = 57, X86_GR64_NOSP_and_GR64_TCW64RegClassID = 58, X86_GR64_TC_and_GR64_TCW64RegClassID = 59, X86_VK64WMRegClassID = 60, X86_GR64_NOREX_and_GR64_TCRegClassID = 61, X86_GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 62, X86_GR64_NOREX_NOSP_and_GR64_TCRegClassID = 63, X86_GR64_ABCDRegClassID = 64, X86_GR64_NOREX_and_GR64_TCW64RegClassID = 65, X86_GR64_with_sub_32bit_in_GR32_TCRegClassID = 66, X86_GR64_ADRegClassID = 67, X86_GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 68, X86_GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID = 69, X86_GR64_and_LOW32_ADDR_ACCESSRegClassID = 70, X86_RSTRegClassID = 71, X86_RFP80RegClassID = 72, X86_VR128XRegClassID = 73, X86_VR128RegClassID = 74, X86_VR128HRegClassID = 75, X86_VR128LRegClassID = 76, X86_BNDRRegClassID = 77, X86_VR256XRegClassID = 78, X86_VR256RegClassID = 79, X86_VR256HRegClassID = 80, X86_VR256LRegClassID = 81, X86_VR512RegClassID = 82, X86_VR512_with_sub_xmm_in_FR32RegClassID = 83, X86_VR512_with_sub_xmm_in_VR128HRegClassID = 84, X86_VR512_with_sub_xmm_in_VR128LRegClassID = 85, }; #endif // GET_REGINFO_ENUM #ifdef GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC static const MCPhysReg X86RegDiffLists[] = { /* 0 */ 0, 1, 0, /* 3 */ 64875, 1, 1, 0, /* 7 */ 65259, 1, 1, 0, /* 11 */ 65397, 1, 1, 0, /* 15 */ 65466, 1, 1, 0, /* 19 */ 2, 1, 0, /* 22 */ 4, 1, 0, /* 25 */ 6, 1, 0, /* 28 */ 11, 1, 0, /* 31 */ 22, 1, 0, /* 34 */ 26, 1, 0, /* 37 */ 29, 1, 0, /* 40 */ 64851, 1, 0, /* 43 */ 10, 3, 0, /* 46 */ 4, 0, /* 48 */ 5, 0, /* 50 */ 65292, 1, 7, 0, /* 54 */ 65417, 1, 7, 0, /* 58 */ 10, 3, 7, 0, /* 62 */ 65512, 8, 0, /* 65 */ 65342, 1, 11, 0, /* 69 */ 65348, 1, 11, 0, /* 73 */ 65442, 1, 11, 0, /* 77 */ 65448, 1, 11, 0, /* 81 */ 12, 0, /* 83 */ 65342, 1, 14, 0, /* 87 */ 65348, 1, 14, 0, /* 91 */ 65442, 1, 14, 0, /* 95 */ 65448, 1, 14, 0, /* 99 */ 21, 0, /* 101 */ 22, 0, /* 103 */ 65534, 65509, 23, 0, /* 107 */ 65535, 65509, 23, 0, /* 111 */ 65534, 65511, 23, 0, /* 115 */ 65535, 65511, 23, 0, /* 119 */ 65524, 23, 0, /* 122 */ 128, 8, 65512, 8, 24, 0, /* 128 */ 65519, 24, 0, /* 131 */ 65522, 24, 0, /* 134 */ 65511, 65526, 2, 65535, 24, 0, /* 140 */ 2, 6, 25, 0, /* 144 */ 6, 6, 25, 0, /* 148 */ 65534, 10, 25, 0, /* 152 */ 65535, 10, 25, 0, /* 156 */ 2, 12, 25, 0, /* 160 */ 3, 12, 25, 0, /* 164 */ 4, 15, 25, 0, /* 168 */ 5, 15, 25, 0, /* 172 */ 65534, 17, 25, 0, /* 176 */ 65535, 17, 25, 0, /* 180 */ 1, 19, 25, 0, /* 184 */ 2, 19, 25, 0, /* 188 */ 65521, 25, 0, /* 191 */ 26, 0, /* 193 */ 65511, 65530, 65534, 65532, 27, 0, /* 199 */ 65511, 65524, 65534, 65535, 30, 0, /* 205 */ 65511, 65519, 2, 65535, 31, 0, /* 211 */ 32, 32, 0, /* 214 */ 65511, 65521, 65532, 65535, 35, 0, /* 220 */ 65511, 65517, 65535, 65535, 36, 0, /* 226 */ 64829, 0, /* 228 */ 64900, 0, /* 230 */ 64923, 0, /* 232 */ 65131, 0, /* 234 */ 65520, 65408, 0, /* 237 */ 16, 65528, 65408, 0, /* 241 */ 24, 65528, 65408, 0, /* 245 */ 65430, 0, /* 247 */ 65432, 0, /* 249 */ 65461, 0, /* 251 */ 65493, 0, /* 253 */ 65504, 65504, 0, /* 256 */ 65509, 0, /* 258 */ 65511, 0, /* 260 */ 65514, 0, /* 262 */ 65513, 27, 2, 65535, 65520, 0, /* 268 */ 65513, 25, 2, 65535, 65522, 0, /* 274 */ 65525, 0, /* 276 */ 65530, 0, /* 278 */ 65531, 0, /* 280 */ 65534, 65532, 0, /* 283 */ 65512, 17, 65533, 0, /* 287 */ 65534, 0, /* 289 */ 2, 65535, 0, /* 292 */ 65532, 65535, 0, /* 295 */ 65534, 65535, 0, /* 298 */ 65535, 65535, 0, }; static const uint16_t X86SubRegIdxLists[] = { /* 0 */ 1, 2, 0, /* 3 */ 1, 3, 0, /* 6 */ 6, 4, 1, 2, 5, 0, /* 12 */ 6, 4, 1, 3, 5, 0, /* 18 */ 6, 4, 5, 0, /* 22 */ 8, 7, 0, }; static const MCRegisterDesc X86RegDesc[] = { { 5, 0, 0, 0, 0, 0 }, { 873, 2, 184, 2, 4641, 0 }, { 1014, 2, 180, 2, 4641, 0 }, { 1148, 298, 181, 0, 0, 2 }, { 879, 2, 168, 2, 4593, 0 }, { 1017, 2, 164, 2, 4593, 0 }, { 1043, 289, 173, 3, 352, 5 }, { 936, 2, 176, 2, 768, 0 }, { 1034, 2, 172, 2, 736, 0 }, { 1160, 292, 165, 0, 304, 2 }, { 922, 2, 160, 2, 4497, 0 }, { 1020, 2, 156, 2, 4497, 0 }, { 1082, 2, 2, 2, 4497, 0 }, { 1172, 295, 157, 0, 400, 2 }, { 870, 2, 2, 2, 4449, 0 }, { 925, 2, 144, 2, 4449, 0 }, { 991, 289, 149, 3, 448, 5 }, { 928, 2, 152, 2, 1296, 0 }, { 1026, 2, 148, 2, 4130, 0 }, { 1023, 2, 140, 2, 4417, 0 }, { 1085, 2, 2, 2, 4417, 0 }, { 1184, 280, 141, 0, 688, 2 }, { 1147, 221, 142, 7, 1524, 8 }, { 1042, 206, 142, 13, 1236, 12 }, { 1159, 215, 142, 7, 1460, 8 }, { 1171, 200, 142, 7, 1172, 8 }, { 990, 135, 142, 13, 869, 12 }, { 1183, 194, 142, 7, 928, 8 }, { 1094, 2, 2, 2, 1584, 0 }, { 1054, 284, 126, 19, 496, 16 }, { 1195, 2, 2, 2, 4417, 0 }, { 1088, 2, 2, 2, 4417, 0 }, { 1002, 269, 105, 13, 243, 12 }, { 1066, 263, 105, 13, 243, 12 }, { 1142, 2, 2, 2, 4593, 0 }, { 1091, 2, 2, 2, 4593, 0 }, { 1098, 2, 2, 2, 4593, 0 }, { 1151, 2, 188, 2, 4161, 0 }, { 1046, 2, 188, 2, 4161, 0 }, { 1163, 2, 188, 2, 4161, 0 }, { 1175, 2, 188, 2, 4161, 0 }, { 994, 2, 188, 2, 4161, 0 }, { 1187, 2, 188, 2, 4161, 0 }, { 1058, 2, 131, 2, 3923, 0 }, { 1006, 2, 119, 2, 3955, 0 }, { 1070, 2, 119, 2, 3955, 0 }, { 1055, 2, 128, 2, 1616, 0 }, { 1155, 220, 2, 6, 1396, 8 }, { 1050, 205, 2, 12, 1108, 12 }, { 1167, 214, 2, 6, 1332, 8 }, { 1179, 199, 2, 6, 1044, 8 }, { 998, 134, 2, 12, 805, 12 }, { 1191, 193, 2, 6, 928, 8 }, { 1062, 283, 2, 18, 496, 16 }, { 1199, 2, 2, 2, 3488, 0 }, { 1010, 268, 2, 12, 179, 12 }, { 1074, 262, 2, 12, 179, 12 }, { 1003, 289, 112, 3, 544, 5 }, { 932, 2, 115, 2, 3152, 0 }, { 1030, 2, 111, 2, 3056, 0 }, { 1067, 289, 104, 3, 592, 5 }, { 940, 2, 107, 2, 3248, 0 }, { 1038, 2, 103, 2, 3719, 0 }, { 1101, 2, 2, 2, 4097, 0 }, { 1078, 2, 2, 2, 4097, 0 }, { 64, 2, 2, 2, 4097, 0 }, { 167, 2, 2, 2, 4097, 0 }, { 252, 2, 2, 2, 4097, 0 }, { 337, 2, 2, 2, 4097, 0 }, { 91, 2, 2, 2, 4097, 0 }, { 194, 2, 2, 2, 4097, 0 }, { 279, 2, 2, 2, 4097, 0 }, { 364, 2, 2, 2, 4097, 0 }, { 444, 2, 2, 2, 4097, 0 }, { 524, 2, 2, 2, 4097, 0 }, { 594, 2, 2, 2, 4097, 0 }, { 664, 2, 2, 2, 4097, 0 }, { 727, 2, 2, 2, 4097, 0 }, { 786, 2, 2, 2, 4097, 0 }, { 18, 2, 2, 2, 4097, 0 }, { 121, 2, 2, 2, 4097, 0 }, { 224, 2, 2, 2, 4097, 0 }, { 309, 2, 2, 2, 4097, 0 }, { 394, 2, 2, 2, 4097, 0 }, { 474, 2, 2, 2, 4097, 0 }, { 95, 2, 2, 2, 4097, 0 }, { 198, 2, 2, 2, 4097, 0 }, { 283, 2, 2, 2, 4097, 0 }, { 368, 2, 2, 2, 4097, 0 }, { 448, 2, 2, 2, 4097, 0 }, { 528, 2, 2, 2, 4097, 0 }, { 598, 2, 2, 2, 4097, 0 }, { 668, 2, 2, 2, 4097, 0 }, { 731, 2, 2, 2, 4097, 0 }, { 790, 2, 2, 2, 4097, 0 }, { 23, 2, 2, 2, 4097, 0 }, { 126, 2, 2, 2, 4097, 0 }, { 229, 2, 2, 2, 4097, 0 }, { 314, 2, 2, 2, 4097, 0 }, { 399, 2, 2, 2, 4097, 0 }, { 479, 2, 2, 2, 4097, 0 }, { 87, 2, 2, 2, 4097, 0 }, { 190, 2, 2, 2, 4097, 0 }, { 275, 2, 2, 2, 4097, 0 }, { 360, 2, 2, 2, 4097, 0 }, { 440, 2, 2, 2, 4097, 0 }, { 520, 2, 2, 2, 4097, 0 }, { 590, 2, 2, 2, 4097, 0 }, { 660, 2, 2, 2, 4097, 0 }, { 69, 2, 2, 2, 4097, 0 }, { 172, 2, 2, 2, 4097, 0 }, { 257, 2, 2, 2, 4097, 0 }, { 342, 2, 2, 2, 4097, 0 }, { 422, 2, 2, 2, 4097, 0 }, { 502, 2, 2, 2, 4097, 0 }, { 572, 2, 2, 2, 4097, 0 }, { 642, 2, 2, 2, 4097, 0 }, { 73, 2, 2, 2, 4097, 0 }, { 176, 2, 2, 2, 4097, 0 }, { 261, 2, 2, 2, 4097, 0 }, { 346, 2, 2, 2, 4097, 0 }, { 426, 2, 2, 2, 4097, 0 }, { 506, 2, 2, 2, 4097, 0 }, { 576, 2, 2, 2, 4097, 0 }, { 646, 2, 2, 2, 4097, 0 }, { 728, 122, 2, 12, 115, 12 }, { 787, 122, 2, 12, 115, 12 }, { 19, 122, 2, 12, 115, 12 }, { 122, 122, 2, 12, 115, 12 }, { 225, 122, 2, 12, 115, 12 }, { 310, 122, 2, 12, 115, 12 }, { 395, 122, 2, 12, 115, 12 }, { 475, 122, 2, 12, 115, 12 }, { 99, 2, 2, 2, 4385, 0 }, { 202, 2, 2, 2, 4385, 0 }, { 287, 2, 2, 2, 4385, 0 }, { 372, 2, 2, 2, 4385, 0 }, { 452, 2, 2, 2, 4385, 0 }, { 532, 2, 2, 2, 4385, 0 }, { 602, 2, 2, 2, 4385, 0 }, { 672, 2, 2, 2, 4385, 0 }, { 72, 2, 211, 2, 4385, 0 }, { 175, 2, 211, 2, 4385, 0 }, { 260, 2, 211, 2, 4385, 0 }, { 345, 2, 211, 2, 4385, 0 }, { 425, 2, 211, 2, 4385, 0 }, { 505, 2, 211, 2, 4385, 0 }, { 575, 2, 211, 2, 4385, 0 }, { 645, 2, 211, 2, 4385, 0 }, { 712, 2, 211, 2, 4385, 0 }, { 771, 2, 211, 2, 4385, 0 }, { 0, 2, 211, 2, 4385, 0 }, { 103, 2, 211, 2, 4385, 0 }, { 206, 2, 211, 2, 4385, 0 }, { 291, 2, 211, 2, 4385, 0 }, { 376, 2, 211, 2, 4385, 0 }, { 456, 2, 211, 2, 4385, 0 }, { 536, 2, 211, 2, 4385, 0 }, { 606, 2, 211, 2, 4385, 0 }, { 676, 2, 211, 2, 4385, 0 }, { 735, 2, 211, 2, 4385, 0 }, { 28, 2, 211, 2, 4385, 0 }, { 131, 2, 211, 2, 4385, 0 }, { 234, 2, 211, 2, 4385, 0 }, { 319, 2, 211, 2, 4385, 0 }, { 404, 2, 211, 2, 4385, 0 }, { 484, 2, 211, 2, 4385, 0 }, { 554, 2, 211, 2, 4385, 0 }, { 624, 2, 211, 2, 4385, 0 }, { 694, 2, 211, 2, 4385, 0 }, { 753, 2, 211, 2, 4385, 0 }, { 46, 2, 211, 2, 4385, 0 }, { 149, 2, 211, 2, 4385, 0 }, { 77, 254, 212, 23, 4017, 19 }, { 180, 254, 212, 23, 4017, 19 }, { 265, 254, 212, 23, 4017, 19 }, { 350, 254, 212, 23, 4017, 19 }, { 430, 254, 212, 23, 4017, 19 }, { 510, 254, 212, 23, 4017, 19 }, { 580, 254, 212, 23, 4017, 19 }, { 650, 254, 212, 23, 4017, 19 }, { 717, 254, 212, 23, 4017, 19 }, { 776, 254, 212, 23, 4017, 19 }, { 6, 254, 212, 23, 4017, 19 }, { 109, 254, 212, 23, 4017, 19 }, { 212, 254, 212, 23, 4017, 19 }, { 297, 254, 212, 23, 4017, 19 }, { 382, 254, 212, 23, 4017, 19 }, { 462, 254, 212, 23, 4017, 19 }, { 542, 254, 212, 23, 4017, 19 }, { 612, 254, 212, 23, 4017, 19 }, { 682, 254, 212, 23, 4017, 19 }, { 741, 254, 212, 23, 4017, 19 }, { 34, 254, 212, 23, 4017, 19 }, { 137, 254, 212, 23, 4017, 19 }, { 240, 254, 212, 23, 4017, 19 }, { 325, 254, 212, 23, 4017, 19 }, { 410, 254, 212, 23, 4017, 19 }, { 490, 254, 212, 23, 4017, 19 }, { 560, 254, 212, 23, 4017, 19 }, { 630, 254, 212, 23, 4017, 19 }, { 700, 254, 212, 23, 4017, 19 }, { 759, 254, 212, 23, 4017, 19 }, { 52, 254, 212, 23, 4017, 19 }, { 155, 254, 212, 23, 4017, 19 }, { 82, 253, 2, 22, 3985, 19 }, { 185, 253, 2, 22, 3985, 19 }, { 270, 253, 2, 22, 3985, 19 }, { 355, 253, 2, 22, 3985, 19 }, { 435, 253, 2, 22, 3985, 19 }, { 515, 253, 2, 22, 3985, 19 }, { 585, 253, 2, 22, 3985, 19 }, { 655, 253, 2, 22, 3985, 19 }, { 722, 253, 2, 22, 3985, 19 }, { 781, 253, 2, 22, 3985, 19 }, { 12, 253, 2, 22, 3985, 19 }, { 115, 253, 2, 22, 3985, 19 }, { 218, 253, 2, 22, 3985, 19 }, { 303, 253, 2, 22, 3985, 19 }, { 388, 253, 2, 22, 3985, 19 }, { 468, 253, 2, 22, 3985, 19 }, { 548, 253, 2, 22, 3985, 19 }, { 618, 253, 2, 22, 3985, 19 }, { 688, 253, 2, 22, 3985, 19 }, { 747, 253, 2, 22, 3985, 19 }, { 40, 253, 2, 22, 3985, 19 }, { 143, 253, 2, 22, 3985, 19 }, { 246, 253, 2, 22, 3985, 19 }, { 331, 253, 2, 22, 3985, 19 }, { 416, 253, 2, 22, 3985, 19 }, { 496, 253, 2, 22, 3985, 19 }, { 566, 253, 2, 22, 3985, 19 }, { 636, 253, 2, 22, 3985, 19 }, { 706, 253, 2, 22, 3985, 19 }, { 765, 253, 2, 22, 3985, 19 }, { 58, 253, 2, 22, 3985, 19 }, { 161, 253, 2, 22, 3985, 19 }, { 824, 2, 241, 2, 3683, 0 }, { 828, 2, 241, 2, 3683, 0 }, { 794, 2, 241, 2, 3683, 0 }, { 799, 2, 241, 2, 3683, 0 }, { 804, 2, 241, 2, 3683, 0 }, { 809, 2, 241, 2, 3683, 0 }, { 814, 2, 241, 2, 3683, 0 }, { 819, 2, 241, 2, 3683, 0 }, { 912, 2, 237, 2, 3651, 0 }, { 917, 2, 237, 2, 3651, 0 }, { 876, 2, 237, 2, 3651, 0 }, { 882, 2, 237, 2, 3651, 0 }, { 888, 2, 237, 2, 3651, 0 }, { 894, 2, 237, 2, 3651, 0 }, { 900, 2, 237, 2, 3651, 0 }, { 906, 2, 237, 2, 3651, 0 }, { 862, 123, 235, 13, 51, 12 }, { 866, 123, 235, 13, 51, 12 }, { 832, 123, 235, 13, 51, 12 }, { 837, 123, 235, 13, 51, 12 }, { 842, 123, 235, 13, 51, 12 }, { 847, 123, 235, 13, 51, 12 }, { 852, 123, 235, 13, 51, 12 }, { 857, 123, 235, 13, 51, 12 }, { 1134, 62, 238, 3, 643, 5 }, { 1138, 62, 238, 3, 643, 5 }, { 1104, 62, 238, 3, 643, 5 }, { 1109, 62, 238, 3, 643, 5 }, { 1114, 62, 238, 3, 643, 5 }, { 1119, 62, 238, 3, 643, 5 }, { 1124, 62, 238, 3, 643, 5 }, { 1129, 62, 238, 3, 643, 5 }, { 980, 2, 234, 2, 3619, 0 }, { 985, 2, 234, 2, 3619, 0 }, { 944, 2, 234, 2, 3619, 0 }, { 950, 2, 234, 2, 3619, 0 }, { 956, 2, 234, 2, 3619, 0 }, { 962, 2, 234, 2, 3619, 0 }, { 968, 2, 234, 2, 3619, 0 }, { 974, 2, 234, 2, 3619, 0 }, }; // GR8 Register Class... static const MCPhysReg GR8[] = { X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, X86_SIL, X86_DIL, X86_BPL, X86_SPL, X86_R8B, X86_R9B, X86_R10B, X86_R11B, X86_R14B, X86_R15B, X86_R12B, X86_R13B, }; // GR8 Bit set. static const uint8_t GR8Bits[] = { 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GRH8 Register Class... static const MCPhysReg GRH8[] = { X86_SIH, X86_DIH, X86_BPH, X86_SPH, X86_R8BH, X86_R9BH, X86_R10BH, X86_R11BH, X86_R12BH, X86_R13BH, X86_R14BH, X86_R15BH, }; // GRH8 Bit set. static const uint8_t GRH8Bits[] = { 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR8_NOREX Register Class... static const MCPhysReg GR8_NOREX[] = { X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, }; // GR8_NOREX Bit set. static const uint8_t GR8_NOREXBits[] = { 0x36, 0x8c, 0x08, }; // GR8_ABCD_H Register Class... static const MCPhysReg GR8_ABCD_H[] = { X86_AH, X86_CH, X86_DH, X86_BH, }; // GR8_ABCD_H Bit set. static const uint8_t GR8_ABCD_HBits[] = { 0x12, 0x84, }; // GR8_ABCD_L Register Class... static const MCPhysReg GR8_ABCD_L[] = { X86_AL, X86_CL, X86_DL, X86_BL, }; // GR8_ABCD_L Bit set. static const uint8_t GR8_ABCD_LBits[] = { 0x24, 0x08, 0x08, }; // GRH16 Register Class... static const MCPhysReg GRH16[] = { X86_HAX, X86_HCX, X86_HDX, X86_HSI, X86_HDI, X86_HBX, X86_HBP, X86_HSP, X86_HIP, X86_R8WH, X86_R9WH, X86_R10WH, X86_R11WH, X86_R12WH, X86_R13WH, X86_R14WH, X86_R15WH, }; // GRH16 Bit set. static const uint8_t GRH16Bits[] = { 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR16 Register Class... static const MCPhysReg GR16[] = { X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP, X86_R8W, X86_R9W, X86_R10W, X86_R11W, X86_R14W, X86_R15W, X86_R12W, X86_R13W, }; // GR16 Bit set. static const uint8_t GR16Bits[] = { 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR16_NOREX Register Class... static const MCPhysReg GR16_NOREX[] = { X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP, }; // GR16_NOREX Bit set. static const uint8_t GR16_NOREXBits[] = { 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x12, }; // VK1 Register Class... static const MCPhysReg VK1[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK1 Bit set. static const uint8_t VK1Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VK16 Register Class... static const MCPhysReg VK16[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK16 Bit set. static const uint8_t VK16Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VK2 Register Class... static const MCPhysReg VK2[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK2 Bit set. static const uint8_t VK2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VK4 Register Class... static const MCPhysReg VK4[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK4 Bit set. static const uint8_t VK4Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VK8 Register Class... static const MCPhysReg VK8[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK8 Bit set. static const uint8_t VK8Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VK16WM Register Class... static const MCPhysReg VK16WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK16WM Bit set. static const uint8_t VK16WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // VK1WM Register Class... static const MCPhysReg VK1WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK1WM Bit set. static const uint8_t VK1WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // VK2WM Register Class... static const MCPhysReg VK2WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK2WM Bit set. static const uint8_t VK2WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // VK4WM Register Class... static const MCPhysReg VK4WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK4WM Bit set. static const uint8_t VK4WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // VK8WM Register Class... static const MCPhysReg VK8WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK8WM Bit set. static const uint8_t VK8WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // SEGMENT_REG Register Class... static const MCPhysReg SEGMENT_REG[] = { X86_CS, X86_DS, X86_SS, X86_ES, X86_FS, X86_GS, }; // SEGMENT_REG Bit set. static const uint8_t SEGMENT_REGBits[] = { 0x00, 0x10, 0x10, 0x80, 0x18, 0x00, 0x00, 0x80, }; // GR16_ABCD Register Class... static const MCPhysReg GR16_ABCD[] = { X86_AX, X86_CX, X86_DX, X86_BX, }; // GR16_ABCD Bit set. static const uint8_t GR16_ABCDBits[] = { 0x08, 0x22, 0x20, }; // FPCCR Register Class... static const MCPhysReg FPCCR[] = { X86_FPSW, }; // FPCCR Bit set. static const uint8_t FPCCRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x04, }; // FR32X Register Class... static const MCPhysReg FR32X[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31, }; // FR32X Bit set. static const uint8_t FR32XBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // LOW32_ADDR_ACCESS_RBP Register Class... static const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RIP, X86_RBP, }; // LOW32_ADDR_ACCESS_RBP Bit set. static const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // LOW32_ADDR_ACCESS Register Class... static const MCPhysReg LOW32_ADDR_ACCESS[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RIP, }; // LOW32_ADDR_ACCESS Bit set. static const uint8_t LOW32_ADDR_ACCESSBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class... static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, X86_RBP, }; // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set. static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // DEBUG_REG Register Class... static const MCPhysReg DEBUG_REG[] = { X86_DR0, X86_DR1, X86_DR2, X86_DR3, X86_DR4, X86_DR5, X86_DR6, X86_DR7, X86_DR8, X86_DR9, X86_DR10, X86_DR11, X86_DR12, X86_DR13, X86_DR14, X86_DR15, }; // DEBUG_REG Bit set. static const uint8_t DEBUG_REGBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // FR32 Register Class... static const MCPhysReg FR32[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, }; // FR32 Bit set. static const uint8_t FR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // GR32 Register Class... static const MCPhysReg GR32[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, }; // GR32 Bit set. static const uint8_t GR32Bits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR32_NOSP Register Class... static const MCPhysReg GR32_NOSP[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D, }; // GR32_NOSP Bit set. static const uint8_t GR32_NOSPBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class... static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_RBP, }; // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set. static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x01, }; // GR32_NOREX Register Class... static const MCPhysReg GR32_NOREX[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, }; // GR32_NOREX Bit set. static const uint8_t GR32_NOREXBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x03, }; // VK32 Register Class... static const MCPhysReg VK32[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK32 Bit set. static const uint8_t VK32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR32_NOREX_NOSP Register Class... static const MCPhysReg GR32_NOREX_NOSP[] = { X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, }; // GR32_NOREX_NOSP Bit set. static const uint8_t GR32_NOREX_NOSPBits[] = { 0x00, 0x00, 0xc0, 0x0f, 0x01, }; // RFP32 Register Class... static const MCPhysReg RFP32[] = { X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6, }; // RFP32 Bit set. static const uint8_t RFP32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // VK32WM Register Class... static const MCPhysReg VK32WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK32WM Bit set. static const uint8_t VK32WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // GR32_ABCD Register Class... static const MCPhysReg GR32_ABCD[] = { X86_EAX, X86_ECX, X86_EDX, X86_EBX, }; // GR32_ABCD Bit set. static const uint8_t GR32_ABCDBits[] = { 0x00, 0x00, 0x40, 0x0b, }; // GR32_TC Register Class... static const MCPhysReg GR32_TC[] = { X86_EAX, X86_ECX, X86_EDX, }; // GR32_TC Bit set. static const uint8_t GR32_TCBits[] = { 0x00, 0x00, 0x40, 0x0a, }; // GR32_AD Register Class... static const MCPhysReg GR32_AD[] = { X86_EAX, X86_EDX, }; // GR32_AD Bit set. static const uint8_t GR32_ADBits[] = { 0x00, 0x00, 0x40, 0x08, }; // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class... static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = { X86_RIP, X86_RBP, }; // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set. static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, }; // CCR Register Class... static const MCPhysReg CCR[] = { X86_EFLAGS, }; // CCR Bit set. static const uint8_t CCRBits[] = { 0x00, 0x00, 0x00, 0x10, }; // DFCCR Register Class... static const MCPhysReg DFCCR[] = { X86_DF, }; // DFCCR Bit set. static const uint8_t DFCCRBits[] = { 0x00, 0x40, }; // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class... static const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = { X86_RBP, }; // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set. static const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; // LOW32_ADDR_ACCESS_with_sub_32bit Register Class... static const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = { X86_RIP, }; // LOW32_ADDR_ACCESS_with_sub_32bit Bit set. static const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // RFP64 Register Class... static const MCPhysReg RFP64[] = { X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6, }; // RFP64 Bit set. static const uint8_t RFP64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // FR64X Register Class... static const MCPhysReg FR64X[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31, }; // FR64X Bit set. static const uint8_t FR64XBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // GR64 Register Class... static const MCPhysReg GR64[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, X86_RIP, }; // GR64 Bit set. static const uint8_t GR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // CONTROL_REG Register Class... static const MCPhysReg CONTROL_REG[] = { X86_CR0, X86_CR1, X86_CR2, X86_CR3, X86_CR4, X86_CR5, X86_CR6, X86_CR7, X86_CR8, X86_CR9, X86_CR10, X86_CR11, X86_CR12, X86_CR13, X86_CR14, X86_CR15, }; // CONTROL_REG Bit set. static const uint8_t CONTROL_REGBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // FR64 Register Class... static const MCPhysReg FR64[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, }; // FR64 Bit set. static const uint8_t FR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // GR64_with_sub_8bit Register Class... static const MCPhysReg GR64_with_sub_8bit[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, }; // GR64_with_sub_8bit Bit set. static const uint8_t GR64_with_sub_8bitBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR64_NOSP Register Class... static const MCPhysReg GR64_NOSP[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, }; // GR64_NOSP Bit set. static const uint8_t GR64_NOSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR64_NOREX Register Class... static const MCPhysReg GR64_NOREX[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, X86_RIP, }; // GR64_NOREX Bit set. static const uint8_t GR64_NOREXBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, }; // GR64_TC Register Class... static const MCPhysReg GR64_TC[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, X86_RIP, }; // GR64_TC Bit set. static const uint8_t GR64_TCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, }; // GR64_NOSP_and_GR64_TC Register Class... static const MCPhysReg GR64_NOSP_and_GR64_TC[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, }; // GR64_NOSP_and_GR64_TC Bit set. static const uint8_t GR64_NOSP_and_GR64_TCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, }; // GR64_TCW64 Register Class... static const MCPhysReg GR64_TCW64[] = { X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R10, X86_R11, X86_RIP, }; // GR64_TCW64 Bit set. static const uint8_t GR64_TCW64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, }; // GR64_with_sub_16bit_in_GR16_NOREX Register Class... static const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, }; // GR64_with_sub_16bit_in_GR16_NOREX Bit set. static const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, }; // VK64 Register Class... static const MCPhysReg VK64[] = { X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK64 Bit set. static const uint8_t VK64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VR64 Register Class... static const MCPhysReg VR64[] = { X86_MM0, X86_MM1, X86_MM2, X86_MM3, X86_MM4, X86_MM5, X86_MM6, X86_MM7, }; // VR64 Bit set. static const uint8_t VR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // GR64_NOREX_NOSP Register Class... static const MCPhysReg GR64_NOREX_NOSP[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, }; // GR64_NOREX_NOSP Bit set. static const uint8_t GR64_NOREX_NOSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, }; // GR64_NOSP_and_GR64_TCW64 Register Class... static const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = { X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R10, X86_R11, }; // GR64_NOSP_and_GR64_TCW64 Bit set. static const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, }; // GR64_TC_and_GR64_TCW64 Register Class... static const MCPhysReg GR64_TC_and_GR64_TCW64[] = { X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11, X86_RIP, }; // GR64_TC_and_GR64_TCW64 Bit set. static const uint8_t GR64_TC_and_GR64_TCW64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, }; // VK64WM Register Class... static const MCPhysReg VK64WM[] = { X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7, }; // VK64WM Bit set. static const uint8_t VK64WMBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, }; // GR64_NOREX_and_GR64_TC Register Class... static const MCPhysReg GR64_NOREX_and_GR64_TC[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RIP, }; // GR64_NOREX_and_GR64_TC Bit set. static const uint8_t GR64_NOREX_and_GR64_TCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbc, }; // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class... static const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = { X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11, }; // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set. static const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x01, }; // GR64_NOREX_NOSP_and_GR64_TC Register Class... static const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = { X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, }; // GR64_NOREX_NOSP_and_GR64_TC Bit set. static const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9c, }; // GR64_ABCD Register Class... static const MCPhysReg GR64_ABCD[] = { X86_RAX, X86_RCX, X86_RDX, X86_RBX, }; // GR64_ABCD Bit set. static const uint8_t GR64_ABCDBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x16, }; // GR64_NOREX_and_GR64_TCW64 Register Class... static const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = { X86_RAX, X86_RCX, X86_RDX, X86_RIP, }; // GR64_NOREX_and_GR64_TCW64 Bit set. static const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x34, }; // GR64_with_sub_32bit_in_GR32_TC Register Class... static const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = { X86_RAX, X86_RCX, X86_RDX, }; // GR64_with_sub_32bit_in_GR32_TC Bit set. static const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x14, }; // GR64_AD Register Class... static const MCPhysReg GR64_AD[] = { X86_RAX, X86_RDX, }; // GR64_AD Bit set. static const uint8_t GR64_ADBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10, }; // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class... static const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = { X86_RBP, X86_RIP, }; // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set. static const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, }; // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Register Class... static const MCPhysReg GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP[] = { X86_RBP, }; // GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP Bit set. static const uint8_t GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; // GR64_and_LOW32_ADDR_ACCESS Register Class... static const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = { X86_RIP, }; // GR64_and_LOW32_ADDR_ACCESS Bit set. static const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // RST Register Class... static const MCPhysReg RST[] = { X86_ST0, X86_ST1, X86_ST2, X86_ST3, X86_ST4, X86_ST5, X86_ST6, X86_ST7, }; // RST Bit set. static const uint8_t RSTBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // RFP80 Register Class... static const MCPhysReg RFP80[] = { X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6, }; // RFP80 Bit set. static const uint8_t RFP80Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; // VR128X Register Class... static const MCPhysReg VR128X[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31, }; // VR128X Bit set. static const uint8_t VR128XBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // VR128 Register Class... static const MCPhysReg VR128[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, }; // VR128 Bit set. static const uint8_t VR128Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // VR128H Register Class... static const MCPhysReg VR128H[] = { X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, }; // VR128H Bit set. static const uint8_t VR128HBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VR128L Register Class... static const MCPhysReg VR128L[] = { X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, }; // VR128L Bit set. static const uint8_t VR128LBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // BNDR Register Class... static const MCPhysReg BNDR[] = { X86_BND0, X86_BND1, X86_BND2, X86_BND3, }; // BNDR Bit set. static const uint8_t BNDRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, }; // VR256X Register Class... static const MCPhysReg VR256X[] = { X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, X86_YMM16, X86_YMM17, X86_YMM18, X86_YMM19, X86_YMM20, X86_YMM21, X86_YMM22, X86_YMM23, X86_YMM24, X86_YMM25, X86_YMM26, X86_YMM27, X86_YMM28, X86_YMM29, X86_YMM30, X86_YMM31, }; // VR256X Bit set. static const uint8_t VR256XBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // VR256 Register Class... static const MCPhysReg VR256[] = { X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, }; // VR256 Bit set. static const uint8_t VR256Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // VR256H Register Class... static const MCPhysReg VR256H[] = { X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, }; // VR256H Bit set. static const uint8_t VR256HBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VR256L Register Class... static const MCPhysReg VR256L[] = { X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, }; // VR256L Bit set. static const uint8_t VR256LBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VR512 Register Class... static const MCPhysReg VR512[] = { X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, X86_ZMM16, X86_ZMM17, X86_ZMM18, X86_ZMM19, X86_ZMM20, X86_ZMM21, X86_ZMM22, X86_ZMM23, X86_ZMM24, X86_ZMM25, X86_ZMM26, X86_ZMM27, X86_ZMM28, X86_ZMM29, X86_ZMM30, X86_ZMM31, }; // VR512 Bit set. static const uint8_t VR512Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; // VR512_with_sub_xmm_in_FR32 Register Class... static const MCPhysReg VR512_with_sub_xmm_in_FR32[] = { X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, }; // VR512_with_sub_xmm_in_FR32 Bit set. static const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; // VR512_with_sub_xmm_in_VR128H Register Class... static const MCPhysReg VR512_with_sub_xmm_in_VR128H[] = { X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, }; // VR512_with_sub_xmm_in_VR128H Bit set. static const uint8_t VR512_with_sub_xmm_in_VR128HBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; // VR512_with_sub_xmm_in_VR128L Register Class... static const MCPhysReg VR512_with_sub_xmm_in_VR128L[] = { X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, }; // VR512_with_sub_xmm_in_VR128L Bit set. static const uint8_t VR512_with_sub_xmm_in_VR128LBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; static const MCRegisterClass X86MCRegisterClasses[] = { { GR8, GR8Bits, sizeof(GR8Bits) }, { GRH8, GRH8Bits, sizeof(GRH8Bits) }, { GR8_NOREX, GR8_NOREXBits, sizeof(GR8_NOREXBits) }, { GR8_ABCD_H, GR8_ABCD_HBits, sizeof(GR8_ABCD_HBits) }, { GR8_ABCD_L, GR8_ABCD_LBits, sizeof(GR8_ABCD_LBits) }, { GRH16, GRH16Bits, sizeof(GRH16Bits) }, { GR16, GR16Bits, sizeof(GR16Bits) }, { GR16_NOREX, GR16_NOREXBits, sizeof(GR16_NOREXBits) }, { VK1, VK1Bits, sizeof(VK1Bits) }, { VK16, VK16Bits, sizeof(VK16Bits) }, { VK2, VK2Bits, sizeof(VK2Bits) }, { VK4, VK4Bits, sizeof(VK4Bits) }, { VK8, VK8Bits, sizeof(VK8Bits) }, { VK16WM, VK16WMBits, sizeof(VK16WMBits) }, { VK1WM, VK1WMBits, sizeof(VK1WMBits) }, { VK2WM, VK2WMBits, sizeof(VK2WMBits) }, { VK4WM, VK4WMBits, sizeof(VK4WMBits) }, { VK8WM, VK8WMBits, sizeof(VK8WMBits) }, { SEGMENT_REG, SEGMENT_REGBits, sizeof(SEGMENT_REGBits) }, { GR16_ABCD, GR16_ABCDBits, sizeof(GR16_ABCDBits) }, { FPCCR, FPCCRBits, sizeof(FPCCRBits) }, { FR32X, FR32XBits, sizeof(FR32XBits) }, { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, sizeof(LOW32_ADDR_ACCESS_RBPBits) }, { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, sizeof(LOW32_ADDR_ACCESSBits) }, { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits) }, { DEBUG_REG, DEBUG_REGBits, sizeof(DEBUG_REGBits) }, { FR32, FR32Bits, sizeof(FR32Bits) }, { GR32, GR32Bits, sizeof(GR32Bits) }, { GR32_NOSP, GR32_NOSPBits, sizeof(GR32_NOSPBits) }, { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits) }, { GR32_NOREX, GR32_NOREXBits, sizeof(GR32_NOREXBits) }, { VK32, VK32Bits, sizeof(VK32Bits) }, { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, sizeof(GR32_NOREX_NOSPBits) }, { RFP32, RFP32Bits, sizeof(RFP32Bits) }, { VK32WM, VK32WMBits, sizeof(VK32WMBits) }, { GR32_ABCD, GR32_ABCDBits, sizeof(GR32_ABCDBits) }, { GR32_TC, GR32_TCBits, sizeof(GR32_TCBits) }, { GR32_AD, GR32_ADBits, sizeof(GR32_ADBits) }, { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { DFCCR, DFCCRBits, sizeof(DFCCRBits) }, { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits) }, { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits) }, { RFP64, RFP64Bits, sizeof(RFP64Bits) }, { FR64X, FR64XBits, sizeof(FR64XBits) }, { GR64, GR64Bits, sizeof(GR64Bits) }, { CONTROL_REG, CONTROL_REGBits, sizeof(CONTROL_REGBits) }, { FR64, FR64Bits, sizeof(FR64Bits) }, { GR64_with_sub_8bit, GR64_with_sub_8bitBits, sizeof(GR64_with_sub_8bitBits) }, { GR64_NOSP, GR64_NOSPBits, sizeof(GR64_NOSPBits) }, { GR64_NOREX, GR64_NOREXBits, sizeof(GR64_NOREXBits) }, { GR64_TC, GR64_TCBits, sizeof(GR64_TCBits) }, { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, sizeof(GR64_NOSP_and_GR64_TCBits) }, { GR64_TCW64, GR64_TCW64Bits, sizeof(GR64_TCW64Bits) }, { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits) }, { VK64, VK64Bits, sizeof(VK64Bits) }, { VR64, VR64Bits, sizeof(VR64Bits) }, { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, sizeof(GR64_NOREX_NOSPBits) }, { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, sizeof(GR64_NOSP_and_GR64_TCW64Bits) }, { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, sizeof(GR64_TC_and_GR64_TCW64Bits) }, { VK64WM, VK64WMBits, sizeof(VK64WMBits) }, { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, sizeof(GR64_NOREX_and_GR64_TCBits) }, { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits) }, { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits) }, { GR64_ABCD, GR64_ABCDBits, sizeof(GR64_ABCDBits) }, { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, sizeof(GR64_NOREX_and_GR64_TCW64Bits) }, { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, sizeof(GR64_with_sub_32bit_in_GR32_TCBits) }, { GR64_AD, GR64_ADBits, sizeof(GR64_ADBits) }, { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits) }, { GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBP, GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits, sizeof(GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPBits) }, { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, sizeof(GR64_and_LOW32_ADDR_ACCESSBits) }, { RST, RSTBits, sizeof(RSTBits) }, { RFP80, RFP80Bits, sizeof(RFP80Bits) }, { VR128X, VR128XBits, sizeof(VR128XBits) }, { VR128, VR128Bits, sizeof(VR128Bits) }, { VR128H, VR128HBits, sizeof(VR128HBits) }, { VR128L, VR128LBits, sizeof(VR128LBits) }, { BNDR, BNDRBits, sizeof(BNDRBits) }, { VR256X, VR256XBits, sizeof(VR256XBits) }, { VR256, VR256Bits, sizeof(VR256Bits) }, { VR256H, VR256HBits, sizeof(VR256HBits) }, { VR256L, VR256LBits, sizeof(VR256LBits) }, { VR512, VR512Bits, sizeof(VR512Bits) }, { VR512_with_sub_xmm_in_FR32, VR512_with_sub_xmm_in_FR32Bits, sizeof(VR512_with_sub_xmm_in_FR32Bits) }, { VR512_with_sub_xmm_in_VR128H, VR512_with_sub_xmm_in_VR128HBits, sizeof(VR512_with_sub_xmm_in_VR128HBits) }, { VR512_with_sub_xmm_in_VR128L, VR512_with_sub_xmm_in_VR128LBits, sizeof(VR512_with_sub_xmm_in_VR128LBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/X86/X86GenRegisterName.inc000064400000000000000000000247210072674642500215330ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 's', 't', '(', '0', ')', 0, /* 6 */ 's', 't', '(', '1', ')', 0, /* 12 */ 's', 't', '(', '2', ')', 0, /* 18 */ 's', 't', '(', '3', ')', 0, /* 24 */ 's', 't', '(', '4', ')', 0, /* 30 */ 's', 't', '(', '5', ')', 0, /* 36 */ 's', 't', '(', '6', ')', 0, /* 42 */ 's', 't', '(', '7', ')', 0, /* 48 */ 'x', 'm', 'm', '1', '0', 0, /* 54 */ 'y', 'm', 'm', '1', '0', 0, /* 60 */ 'z', 'm', 'm', '1', '0', 0, /* 66 */ 'c', 'r', '1', '0', 0, /* 71 */ 'd', 'r', '1', '0', 0, /* 76 */ 'x', 'm', 'm', '2', '0', 0, /* 82 */ 'y', 'm', 'm', '2', '0', 0, /* 88 */ 'z', 'm', 'm', '2', '0', 0, /* 94 */ 'x', 'm', 'm', '3', '0', 0, /* 100 */ 'y', 'm', 'm', '3', '0', 0, /* 106 */ 'z', 'm', 'm', '3', '0', 0, /* 112 */ 'b', 'n', 'd', '0', 0, /* 117 */ 'k', '0', 0, /* 120 */ 'x', 'm', 'm', '0', 0, /* 125 */ 'y', 'm', 'm', '0', 0, /* 130 */ 'z', 'm', 'm', '0', 0, /* 135 */ 'f', 'p', '0', 0, /* 139 */ 'c', 'r', '0', 0, /* 143 */ 'd', 'r', '0', 0, /* 147 */ 'x', 'm', 'm', '1', '1', 0, /* 153 */ 'y', 'm', 'm', '1', '1', 0, /* 159 */ 'z', 'm', 'm', '1', '1', 0, /* 165 */ 'c', 'r', '1', '1', 0, /* 170 */ 'd', 'r', '1', '1', 0, /* 175 */ 'x', 'm', 'm', '2', '1', 0, /* 181 */ 'y', 'm', 'm', '2', '1', 0, /* 187 */ 'z', 'm', 'm', '2', '1', 0, /* 193 */ 'x', 'm', 'm', '3', '1', 0, /* 199 */ 'y', 'm', 'm', '3', '1', 0, /* 205 */ 'z', 'm', 'm', '3', '1', 0, /* 211 */ 'b', 'n', 'd', '1', 0, /* 216 */ 'k', '1', 0, /* 219 */ 'x', 'm', 'm', '1', 0, /* 224 */ 'y', 'm', 'm', '1', 0, /* 229 */ 'z', 'm', 'm', '1', 0, /* 234 */ 'f', 'p', '1', 0, /* 238 */ 'c', 'r', '1', 0, /* 242 */ 'd', 'r', '1', 0, /* 246 */ 'x', 'm', 'm', '1', '2', 0, /* 252 */ 'y', 'm', 'm', '1', '2', 0, /* 258 */ 'z', 'm', 'm', '1', '2', 0, /* 264 */ 'c', 'r', '1', '2', 0, /* 269 */ 'd', 'r', '1', '2', 0, /* 274 */ 'x', 'm', 'm', '2', '2', 0, /* 280 */ 'y', 'm', 'm', '2', '2', 0, /* 286 */ 'z', 'm', 'm', '2', '2', 0, /* 292 */ 'b', 'n', 'd', '2', 0, /* 297 */ 'k', '2', 0, /* 300 */ 'x', 'm', 'm', '2', 0, /* 305 */ 'y', 'm', 'm', '2', 0, /* 310 */ 'z', 'm', 'm', '2', 0, /* 315 */ 'f', 'p', '2', 0, /* 319 */ 'c', 'r', '2', 0, /* 323 */ 'd', 'r', '2', 0, /* 327 */ 'x', 'm', 'm', '1', '3', 0, /* 333 */ 'y', 'm', 'm', '1', '3', 0, /* 339 */ 'z', 'm', 'm', '1', '3', 0, /* 345 */ 'c', 'r', '1', '3', 0, /* 350 */ 'd', 'r', '1', '3', 0, /* 355 */ 'x', 'm', 'm', '2', '3', 0, /* 361 */ 'y', 'm', 'm', '2', '3', 0, /* 367 */ 'z', 'm', 'm', '2', '3', 0, /* 373 */ 'b', 'n', 'd', '3', 0, /* 378 */ 'k', '3', 0, /* 381 */ 'x', 'm', 'm', '3', 0, /* 386 */ 'y', 'm', 'm', '3', 0, /* 391 */ 'z', 'm', 'm', '3', 0, /* 396 */ 'f', 'p', '3', 0, /* 400 */ 'c', 'r', '3', 0, /* 404 */ 'd', 'r', '3', 0, /* 408 */ 'x', 'm', 'm', '1', '4', 0, /* 414 */ 'y', 'm', 'm', '1', '4', 0, /* 420 */ 'z', 'm', 'm', '1', '4', 0, /* 426 */ 'c', 'r', '1', '4', 0, /* 431 */ 'd', 'r', '1', '4', 0, /* 436 */ 'x', 'm', 'm', '2', '4', 0, /* 442 */ 'y', 'm', 'm', '2', '4', 0, /* 448 */ 'z', 'm', 'm', '2', '4', 0, /* 454 */ 'k', '4', 0, /* 457 */ 'x', 'm', 'm', '4', 0, /* 462 */ 'y', 'm', 'm', '4', 0, /* 467 */ 'z', 'm', 'm', '4', 0, /* 472 */ 'f', 'p', '4', 0, /* 476 */ 'c', 'r', '4', 0, /* 480 */ 'd', 'r', '4', 0, /* 484 */ 'x', 'm', 'm', '1', '5', 0, /* 490 */ 'y', 'm', 'm', '1', '5', 0, /* 496 */ 'z', 'm', 'm', '1', '5', 0, /* 502 */ 'c', 'r', '1', '5', 0, /* 507 */ 'd', 'r', '1', '5', 0, /* 512 */ 'x', 'm', 'm', '2', '5', 0, /* 518 */ 'y', 'm', 'm', '2', '5', 0, /* 524 */ 'z', 'm', 'm', '2', '5', 0, /* 530 */ 'k', '5', 0, /* 533 */ 'x', 'm', 'm', '5', 0, /* 538 */ 'y', 'm', 'm', '5', 0, /* 543 */ 'z', 'm', 'm', '5', 0, /* 548 */ 'f', 'p', '5', 0, /* 552 */ 'c', 'r', '5', 0, /* 556 */ 'd', 'r', '5', 0, /* 560 */ 'x', 'm', 'm', '1', '6', 0, /* 566 */ 'y', 'm', 'm', '1', '6', 0, /* 572 */ 'z', 'm', 'm', '1', '6', 0, /* 578 */ 'x', 'm', 'm', '2', '6', 0, /* 584 */ 'y', 'm', 'm', '2', '6', 0, /* 590 */ 'z', 'm', 'm', '2', '6', 0, /* 596 */ 'k', '6', 0, /* 599 */ 'x', 'm', 'm', '6', 0, /* 604 */ 'y', 'm', 'm', '6', 0, /* 609 */ 'z', 'm', 'm', '6', 0, /* 614 */ 'f', 'p', '6', 0, /* 618 */ 'c', 'r', '6', 0, /* 622 */ 'd', 'r', '6', 0, /* 626 */ 'x', 'm', 'm', '1', '7', 0, /* 632 */ 'y', 'm', 'm', '1', '7', 0, /* 638 */ 'z', 'm', 'm', '1', '7', 0, /* 644 */ 'x', 'm', 'm', '2', '7', 0, /* 650 */ 'y', 'm', 'm', '2', '7', 0, /* 656 */ 'z', 'm', 'm', '2', '7', 0, /* 662 */ 'k', '7', 0, /* 665 */ 'x', 'm', 'm', '7', 0, /* 670 */ 'y', 'm', 'm', '7', 0, /* 675 */ 'z', 'm', 'm', '7', 0, /* 680 */ 'f', 'p', '7', 0, /* 684 */ 'c', 'r', '7', 0, /* 688 */ 'd', 'r', '7', 0, /* 692 */ 'x', 'm', 'm', '1', '8', 0, /* 698 */ 'y', 'm', 'm', '1', '8', 0, /* 704 */ 'z', 'm', 'm', '1', '8', 0, /* 710 */ 'x', 'm', 'm', '2', '8', 0, /* 716 */ 'y', 'm', 'm', '2', '8', 0, /* 722 */ 'z', 'm', 'm', '2', '8', 0, /* 728 */ 'x', 'm', 'm', '8', 0, /* 733 */ 'y', 'm', 'm', '8', 0, /* 738 */ 'z', 'm', 'm', '8', 0, /* 743 */ 'c', 'r', '8', 0, /* 747 */ 'd', 'r', '8', 0, /* 751 */ 'x', 'm', 'm', '1', '9', 0, /* 757 */ 'y', 'm', 'm', '1', '9', 0, /* 763 */ 'z', 'm', 'm', '1', '9', 0, /* 769 */ 'x', 'm', 'm', '2', '9', 0, /* 775 */ 'y', 'm', 'm', '2', '9', 0, /* 781 */ 'z', 'm', 'm', '2', '9', 0, /* 787 */ 'x', 'm', 'm', '9', 0, /* 792 */ 'y', 'm', 'm', '9', 0, /* 797 */ 'z', 'm', 'm', '9', 0, /* 802 */ 'c', 'r', '9', 0, /* 806 */ 'd', 'r', '9', 0, /* 810 */ 'R', '1', '0', 'B', 'H', 0, /* 816 */ 'R', '1', '1', 'B', 'H', 0, /* 822 */ 'R', '1', '2', 'B', 'H', 0, /* 828 */ 'R', '1', '3', 'B', 'H', 0, /* 834 */ 'R', '1', '4', 'B', 'H', 0, /* 840 */ 'R', '1', '5', 'B', 'H', 0, /* 846 */ 'R', '8', 'B', 'H', 0, /* 851 */ 'R', '9', 'B', 'H', 0, /* 856 */ 'D', 'I', 'H', 0, /* 860 */ 'S', 'I', 'H', 0, /* 864 */ 'B', 'P', 'H', 0, /* 868 */ 'S', 'P', 'H', 0, /* 872 */ 'R', '1', '0', 'W', 'H', 0, /* 878 */ 'R', '1', '1', 'W', 'H', 0, /* 884 */ 'R', '1', '2', 'W', 'H', 0, /* 890 */ 'R', '1', '3', 'W', 'H', 0, /* 896 */ 'R', '1', '4', 'W', 'H', 0, /* 902 */ 'R', '1', '5', 'W', 'H', 0, /* 908 */ 'R', '8', 'W', 'H', 0, /* 913 */ 'R', '9', 'W', 'H', 0, /* 918 */ 'H', 'D', 'I', 0, /* 922 */ 'H', 'S', 'I', 0, /* 926 */ 'H', 'B', 'P', 0, /* 930 */ 'H', 'I', 'P', 0, /* 934 */ 'H', 'S', 'P', 0, /* 938 */ 'H', 'A', 'X', 0, /* 942 */ 'H', 'B', 'X', 0, /* 946 */ 'H', 'C', 'X', 0, /* 950 */ 'H', 'D', 'X', 0, /* 954 */ 'r', '1', '0', 'b', 0, /* 959 */ 'r', '1', '1', 'b', 0, /* 964 */ 'r', '1', '2', 'b', 0, /* 969 */ 'r', '1', '3', 'b', 0, /* 974 */ 'r', '1', '4', 'b', 0, /* 979 */ 'r', '1', '5', 'b', 0, /* 984 */ 'r', '8', 'b', 0, /* 988 */ 'r', '9', 'b', 0, /* 992 */ 'r', '1', '0', 'd', 0, /* 997 */ 'r', '1', '1', 'd', 0, /* 1002 */ 'r', '1', '2', 'd', 0, /* 1007 */ 'r', '1', '3', 'd', 0, /* 1012 */ 'r', '1', '4', 'd', 0, /* 1017 */ 'r', '1', '5', 'd', 0, /* 1022 */ 'r', '8', 'd', 0, /* 1026 */ 'r', '9', 'd', 0, /* 1030 */ 'd', 'i', 'r', 'f', 'l', 'a', 'g', 0, /* 1038 */ 'a', 'h', 0, /* 1041 */ 'b', 'h', 0, /* 1044 */ 'c', 'h', 0, /* 1047 */ 'd', 'h', 0, /* 1050 */ 'e', 'd', 'i', 0, /* 1054 */ 'r', 'd', 'i', 0, /* 1058 */ 'e', 's', 'i', 0, /* 1062 */ 'r', 's', 'i', 0, /* 1066 */ 'a', 'l', 0, /* 1069 */ 'b', 'l', 0, /* 1072 */ 'c', 'l', 0, /* 1075 */ 'd', 'l', 0, /* 1078 */ 'd', 'i', 'l', 0, /* 1082 */ 's', 'i', 'l', 0, /* 1086 */ 'b', 'p', 'l', 0, /* 1090 */ 's', 'p', 'l', 0, /* 1094 */ 'e', 'b', 'p', 0, /* 1098 */ 'r', 'b', 'p', 0, /* 1102 */ 'e', 'i', 'p', 0, /* 1106 */ 'r', 'i', 'p', 0, /* 1110 */ 'e', 's', 'p', 0, /* 1114 */ 'r', 's', 'p', 0, /* 1118 */ 's', 's', 'p', 0, /* 1122 */ 'c', 's', 0, /* 1125 */ 'd', 's', 0, /* 1128 */ 'e', 's', 0, /* 1131 */ 'f', 's', 0, /* 1134 */ 'f', 'l', 'a', 'g', 's', 0, /* 1140 */ 's', 's', 0, /* 1143 */ 'r', '1', '0', 'w', 0, /* 1148 */ 'r', '1', '1', 'w', 0, /* 1153 */ 'r', '1', '2', 'w', 0, /* 1158 */ 'r', '1', '3', 'w', 0, /* 1163 */ 'r', '1', '4', 'w', 0, /* 1168 */ 'r', '1', '5', 'w', 0, /* 1173 */ 'r', '8', 'w', 0, /* 1177 */ 'r', '9', 'w', 0, /* 1181 */ 'f', 'p', 's', 'w', 0, /* 1186 */ 'e', 'a', 'x', 0, /* 1190 */ 'r', 'a', 'x', 0, /* 1194 */ 'e', 'b', 'x', 0, /* 1198 */ 'r', 'b', 'x', 0, /* 1202 */ 'e', 'c', 'x', 0, /* 1206 */ 'r', 'c', 'x', 0, /* 1210 */ 'e', 'd', 'x', 0, /* 1214 */ 'r', 'd', 'x', 0, /* 1218 */ 'e', 'i', 'z', 0, /* 1222 */ 'r', 'i', 'z', 0, }; static const uint16_t RegAsmOffset[] = { 1038, 1066, 1187, 1041, 1069, 1095, 864, 1086, 1195, 1044, 1072, 1122, 1203, 1030, 1047, 1051, 856, 1078, 1075, 1125, 1211, 1186, 1094, 1194, 1202, 1050, 1210, 1134, 1102, 1218, 1128, 1058, 1110, 1181, 1131, 1137, 938, 926, 942, 946, 918, 950, 930, 922, 934, 1103, 1190, 1098, 1198, 1206, 1054, 1214, 1106, 1222, 1062, 1114, 1059, 860, 1082, 1111, 868, 1090, 1140, 1118, 112, 211, 292, 373, 139, 238, 319, 400, 476, 552, 618, 684, 743, 802, 66, 165, 264, 345, 426, 502, 143, 242, 323, 404, 480, 556, 622, 688, 747, 806, 71, 170, 269, 350, 431, 507, 135, 234, 315, 396, 472, 548, 614, 680, 117, 216, 297, 378, 454, 530, 596, 662, 121, 220, 301, 382, 458, 534, 600, 666, 744, 803, 67, 166, 265, 346, 427, 503, 0, 6, 12, 18, 24, 30, 36, 42, 120, 219, 300, 381, 457, 533, 599, 665, 728, 787, 48, 147, 246, 327, 408, 484, 560, 626, 692, 751, 76, 175, 274, 355, 436, 512, 578, 644, 710, 769, 94, 193, 125, 224, 305, 386, 462, 538, 604, 670, 733, 792, 54, 153, 252, 333, 414, 490, 566, 632, 698, 757, 82, 181, 280, 361, 442, 518, 584, 650, 716, 775, 100, 199, 130, 229, 310, 391, 467, 543, 609, 675, 738, 797, 60, 159, 258, 339, 420, 496, 572, 638, 704, 763, 88, 187, 286, 367, 448, 524, 590, 656, 722, 781, 106, 205, 984, 988, 954, 959, 964, 969, 974, 979, 846, 851, 810, 816, 822, 828, 834, 840, 1022, 1026, 992, 997, 1002, 1007, 1012, 1017, 1173, 1177, 1143, 1148, 1153, 1158, 1163, 1168, 908, 913, 872, 878, 884, 890, 896, 902, }; return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/X86/X86GenRegisterName1.inc000064400000000000000000000247200072674642500216130ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 's', 't', '(', '0', ')', 0, /* 6 */ 's', 't', '(', '1', ')', 0, /* 12 */ 's', 't', '(', '2', ')', 0, /* 18 */ 's', 't', '(', '3', ')', 0, /* 24 */ 's', 't', '(', '4', ')', 0, /* 30 */ 's', 't', '(', '5', ')', 0, /* 36 */ 's', 't', '(', '6', ')', 0, /* 42 */ 's', 't', '(', '7', ')', 0, /* 48 */ 'x', 'm', 'm', '1', '0', 0, /* 54 */ 'y', 'm', 'm', '1', '0', 0, /* 60 */ 'z', 'm', 'm', '1', '0', 0, /* 66 */ 'c', 'r', '1', '0', 0, /* 71 */ 'd', 'r', '1', '0', 0, /* 76 */ 'x', 'm', 'm', '2', '0', 0, /* 82 */ 'y', 'm', 'm', '2', '0', 0, /* 88 */ 'z', 'm', 'm', '2', '0', 0, /* 94 */ 'x', 'm', 'm', '3', '0', 0, /* 100 */ 'y', 'm', 'm', '3', '0', 0, /* 106 */ 'z', 'm', 'm', '3', '0', 0, /* 112 */ 'b', 'n', 'd', '0', 0, /* 117 */ 'k', '0', 0, /* 120 */ 'x', 'm', 'm', '0', 0, /* 125 */ 'y', 'm', 'm', '0', 0, /* 130 */ 'z', 'm', 'm', '0', 0, /* 135 */ 'f', 'p', '0', 0, /* 139 */ 'c', 'r', '0', 0, /* 143 */ 'd', 'r', '0', 0, /* 147 */ 'x', 'm', 'm', '1', '1', 0, /* 153 */ 'y', 'm', 'm', '1', '1', 0, /* 159 */ 'z', 'm', 'm', '1', '1', 0, /* 165 */ 'c', 'r', '1', '1', 0, /* 170 */ 'd', 'r', '1', '1', 0, /* 175 */ 'x', 'm', 'm', '2', '1', 0, /* 181 */ 'y', 'm', 'm', '2', '1', 0, /* 187 */ 'z', 'm', 'm', '2', '1', 0, /* 193 */ 'x', 'm', 'm', '3', '1', 0, /* 199 */ 'y', 'm', 'm', '3', '1', 0, /* 205 */ 'z', 'm', 'm', '3', '1', 0, /* 211 */ 'b', 'n', 'd', '1', 0, /* 216 */ 'k', '1', 0, /* 219 */ 'x', 'm', 'm', '1', 0, /* 224 */ 'y', 'm', 'm', '1', 0, /* 229 */ 'z', 'm', 'm', '1', 0, /* 234 */ 'f', 'p', '1', 0, /* 238 */ 'c', 'r', '1', 0, /* 242 */ 'd', 'r', '1', 0, /* 246 */ 'x', 'm', 'm', '1', '2', 0, /* 252 */ 'y', 'm', 'm', '1', '2', 0, /* 258 */ 'z', 'm', 'm', '1', '2', 0, /* 264 */ 'c', 'r', '1', '2', 0, /* 269 */ 'd', 'r', '1', '2', 0, /* 274 */ 'x', 'm', 'm', '2', '2', 0, /* 280 */ 'y', 'm', 'm', '2', '2', 0, /* 286 */ 'z', 'm', 'm', '2', '2', 0, /* 292 */ 'b', 'n', 'd', '2', 0, /* 297 */ 'k', '2', 0, /* 300 */ 'x', 'm', 'm', '2', 0, /* 305 */ 'y', 'm', 'm', '2', 0, /* 310 */ 'z', 'm', 'm', '2', 0, /* 315 */ 'f', 'p', '2', 0, /* 319 */ 'c', 'r', '2', 0, /* 323 */ 'd', 'r', '2', 0, /* 327 */ 'x', 'm', 'm', '1', '3', 0, /* 333 */ 'y', 'm', 'm', '1', '3', 0, /* 339 */ 'z', 'm', 'm', '1', '3', 0, /* 345 */ 'c', 'r', '1', '3', 0, /* 350 */ 'd', 'r', '1', '3', 0, /* 355 */ 'x', 'm', 'm', '2', '3', 0, /* 361 */ 'y', 'm', 'm', '2', '3', 0, /* 367 */ 'z', 'm', 'm', '2', '3', 0, /* 373 */ 'b', 'n', 'd', '3', 0, /* 378 */ 'k', '3', 0, /* 381 */ 'x', 'm', 'm', '3', 0, /* 386 */ 'y', 'm', 'm', '3', 0, /* 391 */ 'z', 'm', 'm', '3', 0, /* 396 */ 'f', 'p', '3', 0, /* 400 */ 'c', 'r', '3', 0, /* 404 */ 'd', 'r', '3', 0, /* 408 */ 'x', 'm', 'm', '1', '4', 0, /* 414 */ 'y', 'm', 'm', '1', '4', 0, /* 420 */ 'z', 'm', 'm', '1', '4', 0, /* 426 */ 'c', 'r', '1', '4', 0, /* 431 */ 'd', 'r', '1', '4', 0, /* 436 */ 'x', 'm', 'm', '2', '4', 0, /* 442 */ 'y', 'm', 'm', '2', '4', 0, /* 448 */ 'z', 'm', 'm', '2', '4', 0, /* 454 */ 'k', '4', 0, /* 457 */ 'x', 'm', 'm', '4', 0, /* 462 */ 'y', 'm', 'm', '4', 0, /* 467 */ 'z', 'm', 'm', '4', 0, /* 472 */ 'f', 'p', '4', 0, /* 476 */ 'c', 'r', '4', 0, /* 480 */ 'd', 'r', '4', 0, /* 484 */ 'x', 'm', 'm', '1', '5', 0, /* 490 */ 'y', 'm', 'm', '1', '5', 0, /* 496 */ 'z', 'm', 'm', '1', '5', 0, /* 502 */ 'c', 'r', '1', '5', 0, /* 507 */ 'd', 'r', '1', '5', 0, /* 512 */ 'x', 'm', 'm', '2', '5', 0, /* 518 */ 'y', 'm', 'm', '2', '5', 0, /* 524 */ 'z', 'm', 'm', '2', '5', 0, /* 530 */ 'k', '5', 0, /* 533 */ 'x', 'm', 'm', '5', 0, /* 538 */ 'y', 'm', 'm', '5', 0, /* 543 */ 'z', 'm', 'm', '5', 0, /* 548 */ 'f', 'p', '5', 0, /* 552 */ 'c', 'r', '5', 0, /* 556 */ 'd', 'r', '5', 0, /* 560 */ 'x', 'm', 'm', '1', '6', 0, /* 566 */ 'y', 'm', 'm', '1', '6', 0, /* 572 */ 'z', 'm', 'm', '1', '6', 0, /* 578 */ 'x', 'm', 'm', '2', '6', 0, /* 584 */ 'y', 'm', 'm', '2', '6', 0, /* 590 */ 'z', 'm', 'm', '2', '6', 0, /* 596 */ 'k', '6', 0, /* 599 */ 'x', 'm', 'm', '6', 0, /* 604 */ 'y', 'm', 'm', '6', 0, /* 609 */ 'z', 'm', 'm', '6', 0, /* 614 */ 'f', 'p', '6', 0, /* 618 */ 'c', 'r', '6', 0, /* 622 */ 'd', 'r', '6', 0, /* 626 */ 'x', 'm', 'm', '1', '7', 0, /* 632 */ 'y', 'm', 'm', '1', '7', 0, /* 638 */ 'z', 'm', 'm', '1', '7', 0, /* 644 */ 'x', 'm', 'm', '2', '7', 0, /* 650 */ 'y', 'm', 'm', '2', '7', 0, /* 656 */ 'z', 'm', 'm', '2', '7', 0, /* 662 */ 'k', '7', 0, /* 665 */ 'x', 'm', 'm', '7', 0, /* 670 */ 'y', 'm', 'm', '7', 0, /* 675 */ 'z', 'm', 'm', '7', 0, /* 680 */ 'f', 'p', '7', 0, /* 684 */ 'c', 'r', '7', 0, /* 688 */ 'd', 'r', '7', 0, /* 692 */ 'x', 'm', 'm', '1', '8', 0, /* 698 */ 'y', 'm', 'm', '1', '8', 0, /* 704 */ 'z', 'm', 'm', '1', '8', 0, /* 710 */ 'x', 'm', 'm', '2', '8', 0, /* 716 */ 'y', 'm', 'm', '2', '8', 0, /* 722 */ 'z', 'm', 'm', '2', '8', 0, /* 728 */ 'x', 'm', 'm', '8', 0, /* 733 */ 'y', 'm', 'm', '8', 0, /* 738 */ 'z', 'm', 'm', '8', 0, /* 743 */ 'c', 'r', '8', 0, /* 747 */ 'd', 'r', '8', 0, /* 751 */ 'x', 'm', 'm', '1', '9', 0, /* 757 */ 'y', 'm', 'm', '1', '9', 0, /* 763 */ 'z', 'm', 'm', '1', '9', 0, /* 769 */ 'x', 'm', 'm', '2', '9', 0, /* 775 */ 'y', 'm', 'm', '2', '9', 0, /* 781 */ 'z', 'm', 'm', '2', '9', 0, /* 787 */ 'x', 'm', 'm', '9', 0, /* 792 */ 'y', 'm', 'm', '9', 0, /* 797 */ 'z', 'm', 'm', '9', 0, /* 802 */ 'c', 'r', '9', 0, /* 806 */ 'd', 'r', '9', 0, /* 810 */ 'R', '1', '0', 'B', 'H', 0, /* 816 */ 'R', '1', '1', 'B', 'H', 0, /* 822 */ 'R', '1', '2', 'B', 'H', 0, /* 828 */ 'R', '1', '3', 'B', 'H', 0, /* 834 */ 'R', '1', '4', 'B', 'H', 0, /* 840 */ 'R', '1', '5', 'B', 'H', 0, /* 846 */ 'R', '8', 'B', 'H', 0, /* 851 */ 'R', '9', 'B', 'H', 0, /* 856 */ 'D', 'I', 'H', 0, /* 860 */ 'S', 'I', 'H', 0, /* 864 */ 'B', 'P', 'H', 0, /* 868 */ 'S', 'P', 'H', 0, /* 872 */ 'R', '1', '0', 'W', 'H', 0, /* 878 */ 'R', '1', '1', 'W', 'H', 0, /* 884 */ 'R', '1', '2', 'W', 'H', 0, /* 890 */ 'R', '1', '3', 'W', 'H', 0, /* 896 */ 'R', '1', '4', 'W', 'H', 0, /* 902 */ 'R', '1', '5', 'W', 'H', 0, /* 908 */ 'R', '8', 'W', 'H', 0, /* 913 */ 'R', '9', 'W', 'H', 0, /* 918 */ 'H', 'D', 'I', 0, /* 922 */ 'H', 'S', 'I', 0, /* 926 */ 'H', 'B', 'P', 0, /* 930 */ 'H', 'I', 'P', 0, /* 934 */ 'H', 'S', 'P', 0, /* 938 */ 'H', 'A', 'X', 0, /* 942 */ 'H', 'B', 'X', 0, /* 946 */ 'H', 'C', 'X', 0, /* 950 */ 'H', 'D', 'X', 0, /* 954 */ 'r', '1', '0', 'b', 0, /* 959 */ 'r', '1', '1', 'b', 0, /* 964 */ 'r', '1', '2', 'b', 0, /* 969 */ 'r', '1', '3', 'b', 0, /* 974 */ 'r', '1', '4', 'b', 0, /* 979 */ 'r', '1', '5', 'b', 0, /* 984 */ 'r', '8', 'b', 0, /* 988 */ 'r', '9', 'b', 0, /* 992 */ 'r', '1', '0', 'd', 0, /* 997 */ 'r', '1', '1', 'd', 0, /* 1002 */ 'r', '1', '2', 'd', 0, /* 1007 */ 'r', '1', '3', 'd', 0, /* 1012 */ 'r', '1', '4', 'd', 0, /* 1017 */ 'r', '1', '5', 'd', 0, /* 1022 */ 'r', '8', 'd', 0, /* 1026 */ 'r', '9', 'd', 0, /* 1030 */ 'd', 'i', 'r', 'f', 'l', 'a', 'g', 0, /* 1038 */ 'a', 'h', 0, /* 1041 */ 'b', 'h', 0, /* 1044 */ 'c', 'h', 0, /* 1047 */ 'd', 'h', 0, /* 1050 */ 'e', 'd', 'i', 0, /* 1054 */ 'r', 'd', 'i', 0, /* 1058 */ 'e', 's', 'i', 0, /* 1062 */ 'r', 's', 'i', 0, /* 1066 */ 'a', 'l', 0, /* 1069 */ 'b', 'l', 0, /* 1072 */ 'c', 'l', 0, /* 1075 */ 'd', 'l', 0, /* 1078 */ 'd', 'i', 'l', 0, /* 1082 */ 's', 'i', 'l', 0, /* 1086 */ 'b', 'p', 'l', 0, /* 1090 */ 's', 'p', 'l', 0, /* 1094 */ 'e', 'b', 'p', 0, /* 1098 */ 'r', 'b', 'p', 0, /* 1102 */ 'e', 'i', 'p', 0, /* 1106 */ 'r', 'i', 'p', 0, /* 1110 */ 'e', 's', 'p', 0, /* 1114 */ 'r', 's', 'p', 0, /* 1118 */ 's', 's', 'p', 0, /* 1122 */ 'c', 's', 0, /* 1125 */ 'd', 's', 0, /* 1128 */ 'e', 's', 0, /* 1131 */ 'f', 's', 0, /* 1134 */ 'f', 'l', 'a', 'g', 's', 0, /* 1140 */ 's', 's', 0, /* 1143 */ 'r', '1', '0', 'w', 0, /* 1148 */ 'r', '1', '1', 'w', 0, /* 1153 */ 'r', '1', '2', 'w', 0, /* 1158 */ 'r', '1', '3', 'w', 0, /* 1163 */ 'r', '1', '4', 'w', 0, /* 1168 */ 'r', '1', '5', 'w', 0, /* 1173 */ 'r', '8', 'w', 0, /* 1177 */ 'r', '9', 'w', 0, /* 1181 */ 'f', 'p', 's', 'w', 0, /* 1186 */ 'e', 'a', 'x', 0, /* 1190 */ 'r', 'a', 'x', 0, /* 1194 */ 'e', 'b', 'x', 0, /* 1198 */ 'r', 'b', 'x', 0, /* 1202 */ 'e', 'c', 'x', 0, /* 1206 */ 'r', 'c', 'x', 0, /* 1210 */ 'e', 'd', 'x', 0, /* 1214 */ 'r', 'd', 'x', 0, /* 1218 */ 'e', 'i', 'z', 0, /* 1222 */ 'r', 'i', 'z', 0, }; static const uint16_t RegAsmOffset[] = { 1038, 1066, 1187, 1041, 1069, 1095, 864, 1086, 1195, 1044, 1072, 1122, 1203, 1030, 1047, 1051, 856, 1078, 1075, 1125, 1211, 1186, 1094, 1194, 1202, 1050, 1210, 1134, 1102, 1218, 1128, 1058, 1110, 1181, 1131, 1137, 938, 926, 942, 946, 918, 950, 930, 922, 934, 1103, 1190, 1098, 1198, 1206, 1054, 1214, 1106, 1222, 1062, 1114, 1059, 860, 1082, 1111, 868, 1090, 1140, 1118, 112, 211, 292, 373, 139, 238, 319, 400, 476, 552, 618, 684, 743, 802, 66, 165, 264, 345, 426, 502, 143, 242, 323, 404, 480, 556, 622, 688, 747, 806, 71, 170, 269, 350, 431, 507, 135, 234, 315, 396, 472, 548, 614, 680, 117, 216, 297, 378, 454, 530, 596, 662, 121, 220, 301, 382, 458, 534, 600, 666, 744, 803, 67, 166, 265, 346, 427, 503, 0, 6, 12, 18, 24, 30, 36, 42, 120, 219, 300, 381, 457, 533, 599, 665, 728, 787, 48, 147, 246, 327, 408, 484, 560, 626, 692, 751, 76, 175, 274, 355, 436, 512, 578, 644, 710, 769, 94, 193, 125, 224, 305, 386, 462, 538, 604, 670, 733, 792, 54, 153, 252, 333, 414, 490, 566, 632, 698, 757, 82, 181, 280, 361, 442, 518, 584, 650, 716, 775, 100, 199, 130, 229, 310, 391, 467, 543, 609, 675, 738, 797, 60, 159, 258, 339, 420, 496, 572, 638, 704, 763, 88, 187, 286, 367, 448, 524, 590, 656, 722, 781, 106, 205, 984, 988, 954, 959, 964, 969, 974, 979, 846, 851, 810, 816, 822, 828, 834, 840, 1022, 1026, 992, 997, 1002, 1007, 1012, 1017, 1173, 1177, 1143, 1148, 1153, 1158, 1163, 1168, 908, 913, 872, 878, 884, 890, 896, 902, }; return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/X86/X86ImmSize.inc000064400000000000000000000164020072674642500200660ustar 00000000000000{1, 1, X86_AAD8i8}, {1, 1, X86_AAM8i8}, {2, 2, X86_ADC16i16}, {2, 2, X86_ADC16mi}, {1, 2, X86_ADC16mi8}, {2, 2, X86_ADC16ri}, {1, 2, X86_ADC16ri8}, {4, 4, X86_ADC32i32}, {4, 4, X86_ADC32mi}, {1, 4, X86_ADC32mi8}, {4, 4, X86_ADC32ri}, {1, 4, X86_ADC32ri8}, {4, 8, X86_ADC64i32}, {4, 8, X86_ADC64mi32}, {1, 8, X86_ADC64mi8}, {4, 8, X86_ADC64ri32}, {1, 8, X86_ADC64ri8}, {1, 1, X86_ADC8i8}, {1, 1, X86_ADC8mi}, {1, 1, X86_ADC8mi8}, {1, 1, X86_ADC8ri}, {1, 1, X86_ADC8ri8}, {2, 2, X86_ADD16i16}, {2, 2, X86_ADD16mi}, {1, 2, X86_ADD16mi8}, {2, 2, X86_ADD16ri}, {1, 2, X86_ADD16ri8}, {4, 4, X86_ADD32i32}, {4, 4, X86_ADD32mi}, {1, 4, X86_ADD32mi8}, {4, 4, X86_ADD32ri}, {1, 4, X86_ADD32ri8}, {4, 8, X86_ADD64i32}, {4, 8, X86_ADD64mi32}, {1, 8, X86_ADD64mi8}, {4, 8, X86_ADD64ri32}, {1, 8, X86_ADD64ri8}, {1, 1, X86_ADD8i8}, {1, 1, X86_ADD8mi}, {1, 1, X86_ADD8mi8}, {1, 1, X86_ADD8ri}, {1, 1, X86_ADD8ri8}, {2, 2, X86_AND16i16}, {2, 2, X86_AND16mi}, {1, 2, X86_AND16mi8}, {2, 2, X86_AND16ri}, {1, 2, X86_AND16ri8}, {4, 4, X86_AND32i32}, {4, 4, X86_AND32mi}, {1, 4, X86_AND32mi8}, {4, 4, X86_AND32ri}, {1, 4, X86_AND32ri8}, {4, 8, X86_AND64i32}, {4, 8, X86_AND64mi32}, {1, 8, X86_AND64mi8}, {4, 8, X86_AND64ri32}, {1, 8, X86_AND64ri8}, {1, 1, X86_AND8i8}, {1, 1, X86_AND8mi}, {1, 1, X86_AND8mi8}, {1, 1, X86_AND8ri}, {1, 1, X86_AND8ri8}, {1, 1, X86_BT16mi8}, {1, 1, X86_BT16ri8}, {1, 1, X86_BT32mi8}, {1, 1, X86_BT32ri8}, {1, 1, X86_BT64mi8}, {1, 1, X86_BT64ri8}, {1, 1, X86_BTC16mi8}, {1, 1, X86_BTC16ri8}, {1, 1, X86_BTC32mi8}, {1, 1, X86_BTC32ri8}, {1, 1, X86_BTC64mi8}, {1, 1, X86_BTC64ri8}, {1, 1, X86_BTR16mi8}, {1, 1, X86_BTR16ri8}, {1, 1, X86_BTR32mi8}, {1, 1, X86_BTR32ri8}, {1, 1, X86_BTR64mi8}, {1, 1, X86_BTR64ri8}, {1, 1, X86_BTS16mi8}, {1, 1, X86_BTS16ri8}, {1, 1, X86_BTS32mi8}, {1, 1, X86_BTS32ri8}, {1, 1, X86_BTS64mi8}, {1, 1, X86_BTS64ri8}, {2, 2, X86_CALLpcrel16}, {2, 4, X86_CALLpcrel32}, {2, 2, X86_CMP16i16}, {2, 2, X86_CMP16mi}, {1, 2, X86_CMP16mi8}, {2, 2, X86_CMP16ri}, {1, 2, X86_CMP16ri8}, {4, 4, X86_CMP32i32}, {4, 4, X86_CMP32mi}, {1, 4, X86_CMP32mi8}, {4, 4, X86_CMP32ri}, {1, 4, X86_CMP32ri8}, {4, 8, X86_CMP64i32}, {4, 8, X86_CMP64mi32}, {1, 8, X86_CMP64mi8}, {4, 8, X86_CMP64ri32}, {1, 8, X86_CMP64ri8}, {1, 1, X86_CMP8i8}, {1, 1, X86_CMP8mi}, {1, 1, X86_CMP8mi8}, {1, 1, X86_CMP8ri}, {1, 1, X86_CMP8ri8}, {1, 2, X86_IMUL16rmi8}, {1, 2, X86_IMUL16rri8}, {1, 4, X86_IMUL32rmi8}, {1, 4, X86_IMUL32rri8}, {4, 8, X86_IMUL64rmi32}, {1, 8, X86_IMUL64rmi8}, {4, 8, X86_IMUL64rri32}, {1, 8, X86_IMUL64rri8}, {2, 2, X86_IN16ri}, {4, 4, X86_IN32ri}, {1, 1, X86_IN8ri}, {2, 2, X86_JMP_2}, {2, 2, X86_MOV16mi}, {2, 2, X86_MOV16ri}, {2, 2, X86_MOV16ri_alt}, {4, 4, X86_MOV32mi}, {4, 4, X86_MOV32ri}, {4, 4, X86_MOV32ri_alt}, {4, 8, X86_MOV64mi32}, {8, 8, X86_MOV64ri}, {4, 8, X86_MOV64ri32}, {1, 1, X86_MOV8mi}, {1, 1, X86_MOV8ri}, {1, 1, X86_MOV8ri_alt}, {2, 2, X86_OR16i16}, {2, 2, X86_OR16mi}, {1, 2, X86_OR16mi8}, {2, 2, X86_OR16ri}, {1, 2, X86_OR16ri8}, {4, 4, X86_OR32i32}, {4, 4, X86_OR32mi}, {1, 4, X86_OR32mi8}, {4, 4, X86_OR32ri}, {1, 4, X86_OR32ri8}, {4, 8, X86_OR64i32}, {4, 8, X86_OR64mi32}, {1, 8, X86_OR64mi8}, {4, 8, X86_OR64ri32}, {1, 8, X86_OR64ri8}, {1, 1, X86_OR8i8}, {1, 1, X86_OR8mi}, {1, 1, X86_OR8mi8}, {1, 1, X86_OR8ri}, {1, 1, X86_OR8ri8}, {1, 2, X86_PUSH16i8}, {1, 4, X86_PUSH32i8}, {4, 8, X86_PUSH64i32}, {1, 8, X86_PUSH64i8}, {2, 2, X86_PUSHi16}, {4, 4, X86_PUSHi32}, {1, 1, X86_RCL16mi}, {1, 1, X86_RCL16ri}, {1, 1, X86_RCL32mi}, {1, 1, X86_RCL32ri}, {1, 1, X86_RCL64mi}, {1, 1, X86_RCL64ri}, {1, 1, X86_RCL8mi}, {1, 1, X86_RCL8ri}, {1, 1, X86_RCR16mi}, {1, 1, X86_RCR16ri}, {1, 1, X86_RCR32mi}, {1, 1, X86_RCR32ri}, {1, 1, X86_RCR64mi}, {1, 1, X86_RCR64ri}, {1, 1, X86_RCR8mi}, {1, 1, X86_RCR8ri}, //{4, 4, X86_RELEASE_ADD32mi}, //{4, 8, X86_RELEASE_ADD64mi32}, //{1, 1, X86_RELEASE_ADD8mi}, //{4, 4, X86_RELEASE_AND32mi}, //{4, 8, X86_RELEASE_AND64mi32}, //{1, 1, X86_RELEASE_AND8mi}, //{2, 2, X86_RELEASE_MOV16mi}, //{4, 4, X86_RELEASE_MOV32mi}, //{4, 8, X86_RELEASE_MOV64mi32}, //{1, 1, X86_RELEASE_MOV8mi}, //{4, 4, X86_RELEASE_OR32mi}, //{4, 8, X86_RELEASE_OR64mi32}, //{1, 1, X86_RELEASE_OR8mi}, //{4, 4, X86_RELEASE_XOR32mi}, //{4, 8, X86_RELEASE_XOR64mi32}, //{1, 1, X86_RELEASE_XOR8mi}, {1, 1, X86_ROL16mi}, {1, 1, X86_ROL16ri}, {1, 1, X86_ROL32mi}, {1, 1, X86_ROL32ri}, {1, 1, X86_ROL64mi}, {1, 1, X86_ROL64ri}, {1, 1, X86_ROL8mi}, {1, 1, X86_ROL8ri}, {1, 1, X86_ROR16mi}, {1, 1, X86_ROR16ri}, {1, 1, X86_ROR32mi}, {1, 1, X86_ROR32ri}, {1, 1, X86_ROR64mi}, {1, 1, X86_ROR64ri}, {1, 1, X86_ROR8mi}, {1, 1, X86_ROR8ri}, {4, 4, X86_RORX32mi}, {4, 4, X86_RORX32ri}, {8, 8, X86_RORX64mi}, {8, 8, X86_RORX64ri}, {1, 1, X86_SAL16mi}, {1, 1, X86_SAL16ri}, {1, 1, X86_SAL32mi}, {1, 1, X86_SAL32ri}, {1, 1, X86_SAL64mi}, {1, 1, X86_SAL64ri}, {1, 1, X86_SAL8mi}, {1, 1, X86_SAL8ri}, {1, 1, X86_SAR16mi}, {1, 1, X86_SAR16ri}, {1, 1, X86_SAR32mi}, {1, 1, X86_SAR32ri}, {1, 1, X86_SAR64mi}, {1, 1, X86_SAR64ri}, {1, 1, X86_SAR8mi}, {1, 1, X86_SAR8ri}, {2, 2, X86_SBB16i16}, {2, 2, X86_SBB16mi}, {1, 2, X86_SBB16mi8}, {2, 2, X86_SBB16ri}, {1, 2, X86_SBB16ri8}, {4, 4, X86_SBB32i32}, {4, 4, X86_SBB32mi}, {1, 4, X86_SBB32mi8}, {4, 4, X86_SBB32ri}, {1, 4, X86_SBB32ri8}, {4, 8, X86_SBB64i32}, {4, 8, X86_SBB64mi32}, {1, 8, X86_SBB64mi8}, {4, 8, X86_SBB64ri32}, {1, 8, X86_SBB64ri8}, {1, 1, X86_SBB8i8}, {1, 1, X86_SBB8mi}, {1, 1, X86_SBB8mi8}, {1, 1, X86_SBB8ri}, {1, 1, X86_SBB8ri8}, {1, 1, X86_SHL16mi}, {1, 1, X86_SHL16ri}, {1, 1, X86_SHL32mi}, {1, 1, X86_SHL32ri}, {1, 1, X86_SHL64mi}, {1, 1, X86_SHL64ri}, {1, 1, X86_SHL8mi}, {1, 1, X86_SHL8ri}, {1, 1, X86_SHLD16mri8}, {1, 1, X86_SHLD16rri8}, {1, 1, X86_SHLD32mri8}, {1, 1, X86_SHLD32rri8}, {1, 1, X86_SHLD64mri8}, {1, 1, X86_SHLD64rri8}, {1, 1, X86_SHR16mi}, {1, 1, X86_SHR16ri}, {1, 1, X86_SHR32mi}, {1, 1, X86_SHR32ri}, {1, 1, X86_SHR64mi}, {1, 1, X86_SHR64ri}, {1, 1, X86_SHR8mi}, {1, 1, X86_SHR8ri}, {1, 1, X86_SHRD16mri8}, {1, 1, X86_SHRD16rri8}, {1, 1, X86_SHRD32mri8}, {1, 1, X86_SHRD32rri8}, {1, 1, X86_SHRD64mri8}, {1, 1, X86_SHRD64rri8}, {2, 2, X86_SUB16i16}, {2, 2, X86_SUB16mi}, {1, 2, X86_SUB16mi8}, {2, 2, X86_SUB16ri}, {1, 2, X86_SUB16ri8}, {4, 4, X86_SUB32i32}, {4, 4, X86_SUB32mi}, {1, 4, X86_SUB32mi8}, {4, 4, X86_SUB32ri}, {1, 4, X86_SUB32ri8}, {4, 8, X86_SUB64i32}, {4, 8, X86_SUB64mi32}, {1, 8, X86_SUB64mi8}, {4, 8, X86_SUB64ri32}, {1, 8, X86_SUB64ri8}, {1, 1, X86_SUB8i8}, {1, 1, X86_SUB8mi}, {1, 1, X86_SUB8mi8}, {1, 1, X86_SUB8ri}, {1, 1, X86_SUB8ri8}, {2, 2, X86_TEST16i16}, {2, 2, X86_TEST16mi}, // {2, 2, X86_TEST16mi_alt}, {2, 2, X86_TEST16ri}, //{2, 2, X86_TEST16ri_alt}, {4, 4, X86_TEST32i32}, {4, 4, X86_TEST32mi}, //{4, 4, X86_TEST32mi_alt}, {4, 4, X86_TEST32ri}, //{4, 4, X86_TEST32ri_alt}, {4, 8, X86_TEST64i32}, {4, 8, X86_TEST64mi32}, //{4, 4, X86_TEST64mi32_alt}, {4, 8, X86_TEST64ri32}, //{4, 4, X86_TEST64ri32_alt}, {1, 1, X86_TEST8i8}, {1, 1, X86_TEST8mi}, //{1, 1, X86_TEST8mi_alt}, {1, 1, X86_TEST8ri}, //{1, 1, X86_TEST8ri_NOREX}, //{1, 1, X86_TEST8ri_alt}, {2, 2, X86_XOR16i16}, {2, 2, X86_XOR16mi}, {1, 2, X86_XOR16mi8}, {2, 2, X86_XOR16ri}, {1, 2, X86_XOR16ri8}, {4, 4, X86_XOR32i32}, {4, 4, X86_XOR32mi}, {1, 4, X86_XOR32mi8}, {4, 4, X86_XOR32ri}, {1, 4, X86_XOR32ri8}, {4, 8, X86_XOR64i32}, {4, 8, X86_XOR64mi32}, {1, 8, X86_XOR64mi8}, {4, 8, X86_XOR64ri32}, {1, 8, X86_XOR64ri8}, {1, 1, X86_XOR8i8}, {1, 1, X86_XOR8mi}, {1, 1, X86_XOR8mi8}, {1, 1, X86_XOR8ri}, {1, 1, X86_XOR8ri8}, capstone-sys-0.15.0/capstone/arch/X86/X86InstPrinter.h000064400000000000000000000014770072674642500204560ustar 00000000000000//= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an X86 MCInst to Intel style .s file syntax. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_X86_INSTPRINTER_H #define CS_X86_INSTPRINTER_H #include "../../MCInst.h" #include "../../SStream.h" void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info); void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info); #endif capstone-sys-0.15.0/capstone/arch/X86/X86InstPrinterCommon.c000064400000000000000000000130020072674642500216050ustar 00000000000000//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file includes common code for rendering MCInst instances as Intel-style // and Intel-style assembly. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:4996) // disable MSVC's warning on strncpy() #pragma warning(disable:28719) // disable MSVC's warning on strncpy() #endif #if !defined(CAPSTONE_HAS_OSXKERNEL) #include #endif #include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include #else #include #include #endif #include #include "../../utils.h" #include "../../MCInst.h" #include "../../SStream.h" #include "X86InstPrinterCommon.h" #include "X86Mapping.h" #ifndef CAPSTONE_X86_REDUCE void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O) { uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f); switch (Imm) { default: break;//printf("Invalid avxcc argument!\n"); break; case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break; case 1: SStream_concat0(O, "lt"); op_addAvxCC(MI, X86_AVX_CC_LT); break; case 2: SStream_concat0(O, "le"); op_addAvxCC(MI, X86_AVX_CC_LE); break; case 3: SStream_concat0(O, "unord"); op_addAvxCC(MI, X86_AVX_CC_UNORD); break; case 4: SStream_concat0(O, "neq"); op_addAvxCC(MI, X86_AVX_CC_NEQ); break; case 5: SStream_concat0(O, "nlt"); op_addAvxCC(MI, X86_AVX_CC_NLT); break; case 6: SStream_concat0(O, "nle"); op_addAvxCC(MI, X86_AVX_CC_NLE); break; case 7: SStream_concat0(O, "ord"); op_addAvxCC(MI, X86_AVX_CC_ORD); break; case 8: SStream_concat0(O, "eq_uq"); op_addAvxCC(MI, X86_AVX_CC_EQ_UQ); break; case 9: SStream_concat0(O, "nge"); op_addAvxCC(MI, X86_AVX_CC_NGE); break; case 0xa: SStream_concat0(O, "ngt"); op_addAvxCC(MI, X86_AVX_CC_NGT); break; case 0xb: SStream_concat0(O, "false"); op_addAvxCC(MI, X86_AVX_CC_FALSE); break; case 0xc: SStream_concat0(O, "neq_oq"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OQ); break; case 0xd: SStream_concat0(O, "ge"); op_addAvxCC(MI, X86_AVX_CC_GE); break; case 0xe: SStream_concat0(O, "gt"); op_addAvxCC(MI, X86_AVX_CC_GT); break; case 0xf: SStream_concat0(O, "true"); op_addAvxCC(MI, X86_AVX_CC_TRUE); break; case 0x10: SStream_concat0(O, "eq_os"); op_addAvxCC(MI, X86_AVX_CC_EQ_OS); break; case 0x11: SStream_concat0(O, "lt_oq"); op_addAvxCC(MI, X86_AVX_CC_LT_OQ); break; case 0x12: SStream_concat0(O, "le_oq"); op_addAvxCC(MI, X86_AVX_CC_LE_OQ); break; case 0x13: SStream_concat0(O, "unord_s"); op_addAvxCC(MI, X86_AVX_CC_UNORD_S); break; case 0x14: SStream_concat0(O, "neq_us"); op_addAvxCC(MI, X86_AVX_CC_NEQ_US); break; case 0x15: SStream_concat0(O, "nlt_uq"); op_addAvxCC(MI, X86_AVX_CC_NLT_UQ); break; case 0x16: SStream_concat0(O, "nle_uq"); op_addAvxCC(MI, X86_AVX_CC_NLE_UQ); break; case 0x17: SStream_concat0(O, "ord_s"); op_addAvxCC(MI, X86_AVX_CC_ORD_S); break; case 0x18: SStream_concat0(O, "eq_us"); op_addAvxCC(MI, X86_AVX_CC_EQ_US); break; case 0x19: SStream_concat0(O, "nge_uq"); op_addAvxCC(MI, X86_AVX_CC_NGE_UQ); break; case 0x1a: SStream_concat0(O, "ngt_uq"); op_addAvxCC(MI, X86_AVX_CC_NGT_UQ); break; case 0x1b: SStream_concat0(O, "false_os"); op_addAvxCC(MI, X86_AVX_CC_FALSE_OS); break; case 0x1c: SStream_concat0(O, "neq_os"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OS); break; case 0x1d: SStream_concat0(O, "ge_oq"); op_addAvxCC(MI, X86_AVX_CC_GE_OQ); break; case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break; case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break; } MI->popcode_adjust = Imm + 1; } void printXOPCC(MCInst *MI, unsigned Op, SStream *O) { int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)); switch (Imm) { default: // llvm_unreachable("Invalid xopcc argument!"); case 0: SStream_concat0(O, "lt"); op_addXopCC(MI, X86_XOP_CC_LT); break; case 1: SStream_concat0(O, "le"); op_addXopCC(MI, X86_XOP_CC_LE); break; case 2: SStream_concat0(O, "gt"); op_addXopCC(MI, X86_XOP_CC_GT); break; case 3: SStream_concat0(O, "ge"); op_addXopCC(MI, X86_XOP_CC_GE); break; case 4: SStream_concat0(O, "eq"); op_addXopCC(MI, X86_XOP_CC_EQ); break; case 5: SStream_concat0(O, "neq"); op_addXopCC(MI, X86_XOP_CC_NEQ); break; case 6: SStream_concat0(O, "false"); op_addXopCC(MI, X86_XOP_CC_FALSE); break; case 7: SStream_concat0(O, "true"); op_addXopCC(MI, X86_XOP_CC_TRUE); break; } } void printRoundingControl(MCInst *MI, unsigned Op, SStream *O) { int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3; switch (Imm) { case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break; case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break; case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break; case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break; default: break; // never reach } } #endif capstone-sys-0.15.0/capstone/arch/X86/X86InstPrinterCommon.h000064400000000000000000000006210072674642500216150ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_X86_INSTPRINTERCOMMON_H #define CS_X86_INSTPRINTERCOMMON_H #include "../../MCInst.h" #include "../../SStream.h" void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O); void printXOPCC(MCInst *MI, unsigned Op, SStream *O); void printRoundingControl(MCInst *MI, unsigned Op, SStream *O); #endif capstone-sys-0.15.0/capstone/arch/X86/X86IntelInstPrinter.c000064400000000000000000000716630072674642500214510ustar 00000000000000//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file includes code for rendering MCInst instances as Intel-style // assembly. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_X86 #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:4996) // disable MSVC's warning on strncpy() #pragma warning(disable:28719) // disable MSVC's warning on strncpy() #endif #if !defined(CAPSTONE_HAS_OSXKERNEL) #include #endif #include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include #else #include #include #endif #include #include "../../utils.h" #include "../../MCInst.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "X86InstPrinter.h" #include "X86Mapping.h" #include "X86InstPrinterCommon.h" #define GET_INSTRINFO_ENUM #ifdef CAPSTONE_X86_REDUCE #include "X86GenInstrInfo_reduce.inc" #else #include "X86GenInstrInfo.inc" #endif #define GET_REGINFO_ENUM #include "X86GenRegisterInfo.inc" #include "X86BaseInfo.h" static void printMemReference(MCInst *MI, unsigned Op, SStream *O); static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); static void set_mem_access(MCInst *MI, bool status) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (!status) // done, create the next operand slot MI->flat_insn->detail->x86.op_count++; } static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) { // FIXME: do this with autogen // printf(">>> ID = %u\n", MI->flat_insn->id); switch(MI->flat_insn->id) { default: SStream_concat0(O, "ptr "); break; case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: case X86_INS_FXRSTOR: case X86_INS_FXSAVE: case X86_INS_LJMP: case X86_INS_LCALL: // do not print "ptr" break; } switch(MI->csh->mode) { case CS_MODE_16: switch(MI->flat_insn->id) { default: MI->x86opsize = 2; break; case X86_INS_LJMP: case X86_INS_LCALL: MI->x86opsize = 4; break; case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: MI->x86opsize = 6; break; } break; case CS_MODE_32: switch(MI->flat_insn->id) { default: MI->x86opsize = 4; break; case X86_INS_LJMP: case X86_INS_JMP: case X86_INS_LCALL: case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: MI->x86opsize = 6; break; } break; case CS_MODE_64: switch(MI->flat_insn->id) { default: MI->x86opsize = 8; break; case X86_INS_LJMP: case X86_INS_LCALL: case X86_INS_SGDT: case X86_INS_SIDT: case X86_INS_LGDT: case X86_INS_LIDT: MI->x86opsize = 10; break; } break; default: // never reach break; } printMemReference(MI, OpNo, O); } static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "byte ptr "); MI->x86opsize = 1; printMemReference(MI, OpNo, O); } static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 2; SStream_concat0(O, "word ptr "); printMemReference(MI, OpNo, O); } static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) { MI->x86opsize = 4; SStream_concat0(O, "dword ptr "); printMemReference(MI, OpNo, O); } static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "qword ptr "); MI->x86opsize = 8; printMemReference(MI, OpNo, O); } static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "xmmword ptr "); MI->x86opsize = 16; printMemReference(MI, OpNo, O); } static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "zmmword ptr "); MI->x86opsize = 64; printMemReference(MI, OpNo, O); } #ifndef CAPSTONE_X86_REDUCE static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "ymmword ptr "); MI->x86opsize = 32; printMemReference(MI, OpNo, O); } static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) { switch(MCInst_getOpcode(MI)) { default: SStream_concat0(O, "dword ptr "); MI->x86opsize = 4; break; case X86_FSTENVm: case X86_FLDENVm: // TODO: fix this in tablegen instead switch(MI->csh->mode) { default: // never reach break; case CS_MODE_16: MI->x86opsize = 14; break; case CS_MODE_32: case CS_MODE_64: MI->x86opsize = 28; break; } break; } printMemReference(MI, OpNo, O); } static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) { // TODO: fix COMISD in Tablegen instead (#1456) if (MI->op1_size == 16) { // printf("printf64mem id = %u\n", MCInst_getOpcode(MI)); switch(MCInst_getOpcode(MI)) { default: SStream_concat0(O, "qword ptr "); MI->x86opsize = 8; break; case X86_MOVPQI2QImr: case X86_COMISDrm: SStream_concat0(O, "xmmword ptr "); MI->x86opsize = 16; break; } } else { SStream_concat0(O, "qword ptr "); MI->x86opsize = 8; } printMemReference(MI, OpNo, O); } static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) { switch(MCInst_getOpcode(MI)) { default: SStream_concat0(O, "xword ptr "); break; case X86_FBLDm: case X86_FBSTPm: break; } MI->x86opsize = 10; printMemReference(MI, OpNo, O); } static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "xmmword ptr "); MI->x86opsize = 16; printMemReference(MI, OpNo, O); } static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "ymmword ptr "); MI->x86opsize = 32; printMemReference(MI, OpNo, O); } static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "zmmword ptr "); MI->x86opsize = 64; printMemReference(MI, OpNo, O); } #endif static const char *getRegisterName(unsigned RegNo); static void printRegName(SStream *OS, unsigned RegNo) { SStream_concat0(OS, getRegisterName(RegNo)); } // for MASM syntax, 0x123 = 123h, 0xA123 = 0A123h // this function tell us if we need to have prefix 0 in front of a number static bool need_zero_prefix(uint64_t imm) { // find the first hex letter representing imm while(imm >= 0x10) imm >>= 4; if (imm < 0xa) return false; else // this need 0 prefix return true; } static void printImm(MCInst *MI, SStream *O, int64_t imm, bool positive) { if (positive) { // always print this number in positive form if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) { if (imm < 0) { if (MI->op1_size) { switch(MI->op1_size) { default: break; case 1: imm &= 0xff; break; case 2: imm &= 0xffff; break; case 4: imm &= 0xffffffff; break; } } if (imm == 0x8000000000000000LL) // imm == -imm SStream_concat0(O, "8000000000000000h"); else if (need_zero_prefix(imm)) SStream_concat(O, "0%"PRIx64"h", imm); else SStream_concat(O, "%"PRIx64"h", imm); } else { if (imm > HEX_THRESHOLD) { if (need_zero_prefix(imm)) SStream_concat(O, "0%"PRIx64"h", imm); else SStream_concat(O, "%"PRIx64"h", imm); } else SStream_concat(O, "%"PRIu64, imm); } } else { // Intel syntax if (imm < 0) { if (MI->op1_size) { switch(MI->op1_size) { default: break; case 1: imm &= 0xff; break; case 2: imm &= 0xffff; break; case 4: imm &= 0xffffffff; break; } } SStream_concat(O, "0x%"PRIx64, imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); else SStream_concat(O, "%"PRIu64, imm); } } } else { if (MI->csh->syntax == CS_OPT_SYNTAX_MASM) { if (imm < 0) { if (imm == 0x8000000000000000LL) // imm == -imm SStream_concat0(O, "8000000000000000h"); else if (imm < -HEX_THRESHOLD) { if (need_zero_prefix(imm)) SStream_concat(O, "-0%"PRIx64"h", -imm); else SStream_concat(O, "-%"PRIx64"h", -imm); } else SStream_concat(O, "-%"PRIu64, -imm); } else { if (imm > HEX_THRESHOLD) { if (need_zero_prefix(imm)) SStream_concat(O, "0%"PRIx64"h", imm); else SStream_concat(O, "%"PRIx64"h", imm); } else SStream_concat(O, "%"PRIu64, imm); } } else { // Intel syntax if (imm < 0) { if (imm == 0x8000000000000000LL) // imm == -imm SStream_concat0(O, "0x8000000000000000"); else if (imm < -HEX_THRESHOLD) SStream_concat(O, "-0x%"PRIx64, -imm); else SStream_concat(O, "-%"PRIu64, -imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); else SStream_concat(O, "%"PRIu64, imm); } } } } // local printOperand, without updating public operands static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { printRegName(O, MCOperand_getReg(Op)); } else if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op); printImm(MI, O, imm, MI->csh->imm_unsigned); } } #ifndef CAPSTONE_DIET // copy & normalize access info static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags) { #ifndef CAPSTONE_DIET uint8_t i; const uint8_t *arr = X86_get_op_access(h, id, eflags); if (!arr) { access[0] = 0; return; } // copy to access but zero out CS_AC_IGNORE for(i = 0; arr[i]; i++) { if (arr[i] != CS_AC_IGNORE) access[i] = arr[i]; else access[i] = 0; } // mark the end of array access[i] = 0; #endif } #endif static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) { MCOperand *SegReg; int reg; if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif } SegReg = MCInst_getOperand(MI, Op + 1); reg = MCOperand_getReg(SegReg); // If this has a segment register, print it. if (reg) { _printOperand(MI, Op + 1, O); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); } SStream_concat0(O, ":"); } SStream_concat0(O, "["); set_mem_access(MI, true); printOperand(MI, Op, O); SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) { if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif } // DI accesses are always ES-based on non-64bit mode if (MI->csh->mode != CS_MODE_64) { SStream_concat(O, "es:["); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; } } else SStream_concat(O, "["); set_mem_access(MI, true); printOperand(MI, Op, O); SStream_concat0(O, "]"); set_mem_access(MI, false); } static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "byte ptr "); MI->x86opsize = 1; printSrcIdx(MI, OpNo, O); } static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "word ptr "); MI->x86opsize = 2; printSrcIdx(MI, OpNo, O); } static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "dword ptr "); MI->x86opsize = 4; printSrcIdx(MI, OpNo, O); } static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "qword ptr "); MI->x86opsize = 8; printSrcIdx(MI, OpNo, O); } static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "byte ptr "); MI->x86opsize = 1; printDstIdx(MI, OpNo, O); } static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "word ptr "); MI->x86opsize = 2; printDstIdx(MI, OpNo, O); } static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "dword ptr "); MI->x86opsize = 4; printDstIdx(MI, OpNo, O); } static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "qword ptr "); MI->x86opsize = 8; printDstIdx(MI, OpNo, O); } static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) { MCOperand *DispSpec = MCInst_getOperand(MI, Op); MCOperand *SegReg = MCInst_getOperand(MI, Op + 1); int reg; if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif } // If this has a segment register, print it. reg = MCOperand_getReg(SegReg); if (reg) { _printOperand(MI, Op + 1, O); SStream_concat0(O, ":"); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); } } SStream_concat0(O, "["); if (MCOperand_isImm(DispSpec)) { int64_t imm = MCOperand_getImm(DispSpec); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; if (imm < 0) printImm(MI, O, arch_masks[MI->csh->mode] & imm, true); else printImm(MI, O, imm, true); } SStream_concat0(O, "]"); if (MI->csh->detail) MI->flat_insn->detail->x86.op_count++; if (MI->op1_size == 0) MI->op1_size = MI->x86opsize; } static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) { uint8_t val = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xff; printImm(MI, O, val, true); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = val; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = 1; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif MI->flat_insn->detail->x86.op_count++; } } static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "byte ptr "); MI->x86opsize = 1; printMemOffset(MI, OpNo, O); } static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "word ptr "); MI->x86opsize = 2; printMemOffset(MI, OpNo, O); } static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "dword ptr "); MI->x86opsize = 4; printMemOffset(MI, OpNo, O); } static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) { SStream_concat0(O, "qword ptr "); MI->x86opsize = 8; printMemOffset(MI, OpNo, O); } static void printInstruction(MCInst *MI, SStream *O); void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info) { x86_reg reg, reg2; enum cs_ac_type access1, access2; // printf("opcode = %u\n", MCInst_getOpcode(MI)); // perhaps this instruction does not need printer if (MI->assembly[0]) { strncpy(O->buffer, MI->assembly, sizeof(O->buffer)); return; } X86_lockrep(MI, O); printInstruction(MI, O); reg = X86_insn_reg_intel(MCInst_getOpcode(MI), &access1); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6] = {0}; #endif // first op can be embedded in the asm by llvm. // so we have to add the missing register as the first operand if (reg) { // shift all the ops right to leave 1st slot for this new register op memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[0].reg = reg; MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; MI->flat_insn->detail->x86.operands[0].access = access1; MI->flat_insn->detail->x86.op_count++; } else { if (X86_insn_reg_intel2(MCInst_getOpcode(MI), ®, &access1, ®2, &access2)) { MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[0].reg = reg; MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; MI->flat_insn->detail->x86.operands[0].access = access1; MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[1].reg = reg2; MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; MI->flat_insn->detail->x86.operands[1].access = access2; MI->flat_insn->detail->x86.op_count = 2; } } #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[0].access = access[0]; MI->flat_insn->detail->x86.operands[1].access = access[1]; #endif } if (MI->op1_size == 0 && reg) MI->op1_size = MI->csh->regsize_map[reg]; } /// printPCRelImm - This is used to print an immediate value that ends up /// being encoded as a pc-relative value. static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; uint8_t opsize = X86_immediate_size(MI->Opcode, NULL); // truncat imm for non-64bit if (MI->csh->mode != CS_MODE_64) { imm = imm & 0xffffffff; } printImm(MI, O, imm, true); if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; // if op_count > 0, then this operand's size is taken from the destination op if (MI->flat_insn->detail->x86.op_count > 0) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; else if (opsize > 0) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; else MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif MI->flat_insn->detail->x86.op_count++; } if (MI->op1_size == 0) MI->op1_size = MI->imm_size; } } static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNo); if (MCOperand_isReg(Op)) { unsigned int reg = MCOperand_getReg(Op); printRegName(O, reg); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); } else { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[X86_register_map(reg)]; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif MI->flat_insn->detail->x86.op_count++; } } if (MI->op1_size == 0) MI->op1_size = MI->csh->regsize_map[X86_register_map(reg)]; } else if (MCOperand_isImm(Op)) { uint8_t encsize; int64_t imm = MCOperand_getImm(Op); uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize); if (opsize == 1) // print 1 byte immediate in positive form imm = imm & 0xff; // printf(">>> id = %u\n", MI->flat_insn->id); switch(MI->flat_insn->id) { default: printImm(MI, O, imm, MI->csh->imm_unsigned); break; case X86_INS_MOVABS: case X86_INS_MOV: // do not print number in negative form printImm(MI, O, imm, true); break; case X86_INS_IN: case X86_INS_OUT: case X86_INS_INT: // do not print number in negative form imm = imm & 0xff; printImm(MI, O, imm, true); break; case X86_INS_LCALL: case X86_INS_LJMP: case X86_INS_JMP: // always print address in positive form if (OpNo == 1) { // ptr16 part imm = imm & 0xffff; opsize = 2; } else opsize = 4; printImm(MI, O, imm, true); break; case X86_INS_AND: case X86_INS_OR: case X86_INS_XOR: // do not print number in negative form if (imm >= 0 && imm <= HEX_THRESHOLD) printImm(MI, O, imm, true); else { imm = arch_masks[opsize? opsize : MI->imm_size] & imm; printImm(MI, O, imm, true); } break; case X86_INS_RET: case X86_INS_RETF: // RET imm16 if (imm >= 0 && imm <= HEX_THRESHOLD) printImm(MI, O, imm, true); else { imm = 0xffff & imm; printImm(MI, O, imm, true); } break; } if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; } else { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; if (opsize > 0) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize; MI->flat_insn->detail->x86.encoding.imm_size = encsize; } else if (MI->flat_insn->detail->x86.op_count > 0) { if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; } else MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; } else MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif MI->flat_insn->detail->x86.op_count++; } } } } static void printMemReference(MCInst *MI, unsigned Op, SStream *O) { bool NeedPlus = false; MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); int reg; if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access[6]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(MCOperand_getReg(BaseReg)); if (MCOperand_getReg(IndexReg) != X86_EIZ) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_register_map(MCOperand_getReg(IndexReg)); } MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; #ifndef CAPSTONE_DIET get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags); MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count]; #endif } // If this has a segment register, print it. reg = MCOperand_getReg(SegReg); if (reg) { _printOperand(MI, Op + X86_AddrSegmentReg, O); if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_register_map(reg); } SStream_concat0(O, ":"); } SStream_concat0(O, "["); if (MCOperand_getReg(BaseReg)) { _printOperand(MI, Op + X86_AddrBaseReg, O); NeedPlus = true; } if (MCOperand_getReg(IndexReg) && MCOperand_getReg(IndexReg) != X86_EIZ) { if (NeedPlus) SStream_concat0(O, " + "); _printOperand(MI, Op + X86_AddrIndexReg, O); if (ScaleVal != 1) SStream_concat(O, "*%u", ScaleVal); NeedPlus = true; } if (MCOperand_isImm(DispSpec)) { int64_t DispVal = MCOperand_getImm(DispSpec); if (MI->csh->detail) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; if (DispVal) { if (NeedPlus) { if (DispVal < 0) { SStream_concat0(O, " - "); printImm(MI, O, -DispVal, true); } else { SStream_concat0(O, " + "); printImm(MI, O, DispVal, true); } } else { // memory reference to an immediate address if (MI->csh->mode == CS_MODE_64) MI->op1_size = 8; if (DispVal < 0) { printImm(MI, O, arch_masks[MI->csh->mode] & DispVal, true); } else { printImm(MI, O, DispVal, true); } } } else { // DispVal = 0 if (!NeedPlus) // [0] SStream_concat0(O, "0"); } } SStream_concat0(O, "]"); if (MI->csh->detail) MI->flat_insn->detail->x86.op_count++; if (MI->op1_size == 0) MI->op1_size = MI->x86opsize; } static void printanymem(MCInst *MI, unsigned OpNo, SStream *O) { switch(MI->Opcode) { default: break; case X86_LEA16r: MI->x86opsize = 2; break; case X86_LEA32r: case X86_LEA64_32r: MI->x86opsize = 4; break; case X86_LEA64r: MI->x86opsize = 8; break; case X86_BNDCL32rm: case X86_BNDCN32rm: case X86_BNDCU32rm: case X86_BNDSTXmr: case X86_BNDLDXrm: case X86_BNDCL64rm: case X86_BNDCN64rm: case X86_BNDCU64rm: MI->x86opsize = 16; break; } printMemReference(MI, OpNo, O); } #ifdef CAPSTONE_X86_REDUCE #include "X86GenAsmWriter1_reduce.inc" #else #include "X86GenAsmWriter1.inc" #endif #include "X86GenRegisterName1.inc" #endif capstone-sys-0.15.0/capstone/arch/X86/X86Lookup16.inc000064400000000000000000002645220072674642500201410ustar 00000000000000typedef struct x86_op_id_pair { uint16_t first; uint16_t second; } x86_op_id_pair; static const x86_op_id_pair x86_16_bit_eq_tbl[] = { { 138, 139 }, { 141, 142 }, { 163, 154 }, { 164, 155 }, { 165, 156 }, { 166, 157 }, { 167, 158 }, { 168, 159 }, { 169, 160 }, { 170, 161 }, { 171, 162 }, { 172, 154 }, { 174, 156 }, { 175, 157 }, { 177, 159 }, { 178, 160 }, { 179, 161 }, { 180, 162 }, { 203, 194 }, { 204, 195 }, { 205, 196 }, { 206, 197 }, { 207, 198 }, { 208, 199 }, { 209, 200 }, { 210, 201 }, { 211, 202 }, { 212, 194 }, { 214, 196 }, { 215, 197 }, { 217, 199 }, { 218, 200 }, { 219, 201 }, { 220, 202 }, { 249, 248 }, { 263, 260 }, { 264, 261 }, { 265, 262 }, { 292, 283 }, { 293, 284 }, { 294, 285 }, { 295, 286 }, { 296, 287 }, { 297, 288 }, { 298, 289 }, { 299, 290 }, { 300, 291 }, { 301, 283 }, { 303, 285 }, { 304, 286 }, { 306, 288 }, { 307, 289 }, { 308, 290 }, { 309, 291 }, { 412, 411 }, { 415, 413 }, { 416, 414 }, { 417, 413 }, { 418, 414 }, { 421, 419 }, { 422, 420 }, { 423, 419 }, { 424, 420 }, { 432, 428 }, { 433, 429 }, { 434, 430 }, { 435, 431 }, { 436, 428 }, { 437, 429 }, { 438, 430 }, { 439, 431 }, { 444, 440 }, { 445, 441 }, { 446, 442 }, { 447, 443 }, { 448, 440 }, { 449, 441 }, { 450, 442 }, { 451, 443 }, { 456, 452 }, { 457, 453 }, { 458, 454 }, { 459, 455 }, { 460, 452 }, { 461, 453 }, { 462, 454 }, { 463, 455 }, { 468, 464 }, { 469, 465 }, { 470, 466 }, { 471, 467 }, { 472, 464 }, { 473, 465 }, { 474, 466 }, { 475, 467 }, { 484, 480 }, { 485, 481 }, { 486, 482 }, { 487, 483 }, { 488, 480 }, { 489, 481 }, { 491, 482 }, { 492, 483 }, { 494, 493 }, { 504, 805 }, { 517, 515 }, { 518, 516 }, { 519, 515 }, { 520, 516 }, { 523, 521 }, { 524, 522 }, { 525, 521 }, { 526, 522 }, { 529, 527 }, { 530, 528 }, { 531, 527 }, { 532, 528 }, { 535, 533 }, { 536, 534 }, { 537, 533 }, { 538, 534 }, { 549, 547 }, { 550, 548 }, { 551, 547 }, { 552, 548 }, { 559, 557 }, { 560, 558 }, { 561, 557 }, { 562, 558 }, { 565, 563 }, { 566, 564 }, { 567, 563 }, { 568, 564 }, { 571, 569 }, { 572, 570 }, { 573, 569 }, { 574, 570 }, { 577, 575 }, { 578, 576 }, { 579, 575 }, { 580, 576 }, { 591, 589 }, { 592, 590 }, { 593, 589 }, { 594, 590 }, { 601, 599 }, { 602, 600 }, { 603, 599 }, { 604, 600 }, { 607, 605 }, { 608, 606 }, { 609, 605 }, { 610, 606 }, { 617, 615 }, { 618, 616 }, { 619, 615 }, { 620, 616 }, { 623, 621 }, { 624, 622 }, { 625, 621 }, { 626, 622 }, { 629, 627 }, { 630, 628 }, { 631, 627 }, { 632, 628 }, { 639, 637 }, { 640, 638 }, { 641, 637 }, { 642, 638 }, { 652, 643 }, { 653, 644 }, { 654, 645 }, { 655, 646 }, { 656, 647 }, { 657, 648 }, { 658, 649 }, { 659, 650 }, { 660, 651 }, { 661, 643 }, { 663, 645 }, { 664, 646 }, { 666, 648 }, { 667, 649 }, { 668, 650 }, { 669, 651 }, { 694, 702 }, { 695, 702 }, { 706, 704 }, { 707, 705 }, { 708, 704 }, { 709, 705 }, { 732, 731 }, { 735, 734 }, { 813, 810 }, { 814, 811 }, { 815, 812 }, { 816, 810 }, { 817, 811 }, { 822, 820 }, { 823, 821 }, { 824, 820 }, { 825, 821 }, { 835, 834 }, { 846, 843 }, { 847, 844 }, { 848, 845 }, { 861, 860 }, { 875, 872 }, { 876, 873 }, { 877, 874 }, { 896, 894 }, { 897, 895 }, { 901, 899 }, { 902, 900 }, { 918, 917 }, { 920, 919 }, { 973, 971 }, { 974, 972 }, { 975, 971 }, { 976, 972 }, { 980, 979 }, { 981, 979 }, { 985, 982 }, { 986, 983 }, { 987, 984 }, { 988, 982 }, { 989, 983 }, { 990, 984 }, { 999, 991 }, { 1000, 992 }, { 1001, 993 }, { 1002, 994 }, { 1003, 995 }, { 1004, 996 }, { 1005, 997 }, { 1006, 998 }, { 1007, 991 }, { 1008, 992 }, { 1009, 993 }, { 1011, 995 }, { 1012, 996 }, { 1014, 998 }, { 1019, 1017 }, { 1020, 1018 }, { 1026, 1023 }, { 1027, 1024 }, { 1028, 1025 }, { 1029, 1023 }, { 1030, 1024 }, { 1040, 1041 }, { 1044, 1043 }, { 1057, 1056 }, { 1058, 1056 }, { 1060, 1059 }, { 1061, 1059 }, { 1065, 1062 }, { 1066, 1063 }, { 1067, 1064 }, { 1068, 1062 }, { 1069, 1063 }, { 1070, 1064 }, { 1072, 1071 }, { 1074, 1073 }, { 1075, 1073 }, { 1079, 1076 }, { 1080, 1077 }, { 1081, 1078 }, { 1082, 1076 }, { 1083, 1077 }, { 1084, 1078 }, { 1118, 1114 }, { 1119, 1115 }, { 1120, 1116 }, { 1121, 1117 }, { 1122, 1114 }, { 1123, 1115 }, { 1124, 1116 }, { 1125, 1117 }, { 1153, 1154 }, { 1159, 1160 }, { 1161, 1162 }, { 1173, 1178 }, { 1174, 1179 }, { 1175, 1180 }, { 1176, 1181 }, { 1177, 1182 }, { 1185, 1186 }, { 1189, 1194 }, { 1192, 1193 }, { 1197, 1198 }, { 1201, 1202 }, { 1205, 1206 }, { 1212, 1213 }, { 1216, 1217 }, { 1221, 1219 }, { 1222, 1220 }, { 1223, 1219 }, { 1224, 1220 }, { 1228, 1227 }, { 1248, 1247 }, { 1250, 1247 }, { 1254, 1253 }, { 1257, 1256 }, { 1258, 1256 }, { 1260, 1259 }, { 1261, 1259 }, { 1263, 1262 }, { 1264, 1262 }, { 1266, 1265 }, { 1267, 1265 }, { 1276, 1278 }, { 1277, 1278 }, { 1282, 1284 }, { 1283, 1284 }, { 1285, 1287 }, { 1286, 1287 }, { 1290, 1288 }, { 1291, 1289 }, { 1292, 1288 }, { 1293, 1289 }, { 1295, 1294 }, { 1296, 1294 }, { 1309, 1307 }, { 1310, 1308 }, { 1311, 1307 }, { 1312, 1308 }, { 1404, 1414 }, { 1405, 1415 }, { 1493, 1496 }, { 1494, 1497 }, { 1495, 1498 }, { 1508, 1511 }, { 1509, 1512 }, { 1510, 1513 }, { 1518, 1528 }, { 1519, 1529 }, { 1548, 1547 }, { 1549, 1547 }, { 1554, 1553 }, { 1555, 1553 }, { 1564, 1547 }, { 1565, 1547 }, { 1565, 1548 }, { 1565, 1564 }, { 1566, 1547 }, { 1566, 1549 }, { 1566, 1564 }, { 1569, 1550 }, { 1570, 1551 }, { 1571, 1553 }, { 1572, 1553 }, { 1572, 1554 }, { 1572, 1571 }, { 1573, 1553 }, { 1573, 1555 }, { 1573, 1571 }, { 1576, 1556 }, { 1577, 1557 }, { 1578, 1558 }, { 1579, 1559 }, { 1580, 1560 }, { 1581, 1561 }, { 1582, 1563 }, { 1583, 1547 }, { 1583, 1548 }, { 1584, 1547 }, { 1584, 1549 }, { 1588, 1551 }, { 1589, 1553 }, { 1589, 1554 }, { 1590, 1553 }, { 1590, 1555 }, { 1593, 1556 }, { 1595, 1558 }, { 1596, 1559 }, { 1597, 1560 }, { 1598, 1561 }, { 1599, 1563 }, { 1605, 1604 }, { 1606, 1604 }, { 1611, 1610 }, { 1612, 1610 }, { 1630, 1628 }, { 1631, 1629 }, { 1632, 1628 }, { 1633, 1629 }, { 1641, 1640 }, { 1642, 1640 }, { 1689, 1699 }, { 1692, 1699 }, { 1704, 1700 }, { 1705, 1701 }, { 1707, 1702 }, { 1708, 1703 }, { 1710, 1700 }, { 1711, 1700 }, { 1711, 1710 }, { 1712, 1701 }, { 1713, 1702 }, { 1714, 1702 }, { 1714, 1713 }, { 1715, 1703 }, { 1729, 1725 }, { 1730, 1726 }, { 1732, 1727 }, { 1733, 1728 }, { 1735, 1725 }, { 1736, 1726 }, { 1737, 1727 }, { 1738, 1728 }, { 1743, 1741 }, { 1744, 1742 }, { 1745, 1741 }, { 1746, 1742 }, { 1768, 1767 }, { 1782, 1779 }, { 1783, 1780 }, { 1784, 1781 }, { 1790, 1788 }, { 1791, 1789 }, { 1792, 1788 }, { 1793, 1789 }, { 1797, 1799 }, { 1801, 1803 }, { 1805, 1807 }, { 1809, 1811 }, { 1814, 1821 }, { 1815, 1822 }, { 1816, 1824 }, { 1817, 1825 }, { 1818, 1826 }, { 1819, 1821 }, { 1820, 1826 }, { 1829, 1827 }, { 1830, 1828 }, { 1831, 1827 }, { 1832, 1828 }, { 1844, 1835 }, { 1845, 1836 }, { 1846, 1837 }, { 1847, 1838 }, { 1848, 1839 }, { 1849, 1840 }, { 1850, 1841 }, { 1851, 1842 }, { 1852, 1843 }, { 1853, 1835 }, { 1855, 1837 }, { 1856, 1838 }, { 1858, 1840 }, { 1859, 1841 }, { 1860, 1842 }, { 1861, 1843 }, { 1877, 1875 }, { 1878, 1876 }, { 1882, 1883 }, { 1902, 1912 }, { 1903, 1913 }, { 1937, 1939 }, { 1938, 1940 }, { 1949, 1951 }, { 1950, 1952 }, { 1970, 1972 }, { 1971, 1973 }, { 2035, 2037 }, { 2036, 2038 }, { 2070, 2072 }, { 2071, 2073 }, { 2082, 2084 }, { 2083, 2085 }, { 2111, 2108 }, { 2112, 2109 }, { 2113, 2110 }, { 2114, 2108 }, { 2115, 2109 }, { 2116, 2110 }, { 2118, 2117 }, { 2121, 2119 }, { 2122, 2120 }, { 2123, 2119 }, { 2124, 2120 }, { 2126, 2125 }, { 2128, 2127 }, { 2130, 2129 }, { 2131, 2129 }, { 2133, 2132 }, { 2134, 2132 }, { 2136, 2135 }, { 2137, 2135 }, { 2139, 2138 }, { 2169, 2172 }, { 2170, 2173 }, { 2171, 2174 }, { 2185, 2188 }, { 2186, 2189 }, { 2187, 2190 }, { 2195, 2205 }, { 2196, 2206 }, { 2235, 2231 }, { 2236, 2232 }, { 2237, 2233 }, { 2238, 2234 }, { 2240, 2231 }, { 2241, 2232 }, { 2242, 2233 }, { 2243, 2234 }, { 2245, 2244 }, { 2247, 2246 }, { 2249, 2248 }, { 2251, 2250 }, { 2253, 2252 }, { 2254, 2252 }, { 2256, 2255 }, { 2257, 2255 }, { 2259, 2258 }, { 2260, 2258 }, { 2262, 2261 }, { 2264, 2263 }, { 2273, 2267 }, { 2274, 2268 }, { 2275, 2269 }, { 2276, 2270 }, { 2277, 2271 }, { 2278, 2272 }, { 2279, 2267 }, { 2280, 2268 }, { 2281, 2269 }, { 2282, 2270 }, { 2283, 2271 }, { 2284, 2272 }, { 2303, 2297 }, { 2304, 2298 }, { 2305, 2299 }, { 2306, 2300 }, { 2307, 2301 }, { 2308, 2302 }, { 2309, 2297 }, { 2310, 2298 }, { 2311, 2299 }, { 2312, 2300 }, { 2313, 2301 }, { 2314, 2302 }, { 2331, 2330 }, { 2332, 2330 }, { 2334, 2333 }, { 2335, 2333 }, { 2342, 2344 }, { 2343, 2344 }, { 2345, 2347 }, { 2346, 2347 }, { 2355, 2349 }, { 2356, 2350 }, { 2357, 2351 }, { 2358, 2352 }, { 2359, 2353 }, { 2360, 2354 }, { 2361, 2349 }, { 2362, 2350 }, { 2363, 2351 }, { 2364, 2352 }, { 2365, 2353 }, { 2366, 2354 }, { 2379, 2373 }, { 2380, 2374 }, { 2381, 2375 }, { 2382, 2376 }, { 2383, 2377 }, { 2384, 2378 }, { 2385, 2373 }, { 2386, 2374 }, { 2387, 2375 }, { 2388, 2376 }, { 2389, 2377 }, { 2390, 2378 }, { 2428, 2422 }, { 2429, 2423 }, { 2430, 2424 }, { 2431, 2425 }, { 2432, 2426 }, { 2433, 2427 }, { 2434, 2422 }, { 2435, 2423 }, { 2436, 2424 }, { 2437, 2425 }, { 2438, 2426 }, { 2439, 2427 }, { 2453, 2447 }, { 2454, 2448 }, { 2455, 2449 }, { 2456, 2450 }, { 2457, 2451 }, { 2458, 2452 }, { 2459, 2447 }, { 2460, 2448 }, { 2461, 2449 }, { 2462, 2450 }, { 2463, 2451 }, { 2464, 2452 }, { 2485, 2476 }, { 2486, 2477 }, { 2487, 2478 }, { 2488, 2479 }, { 2489, 2480 }, { 2490, 2481 }, { 2491, 2482 }, { 2492, 2483 }, { 2493, 2484 }, { 2494, 2476 }, { 2496, 2478 }, { 2497, 2479 }, { 2499, 2481 }, { 2500, 2482 }, { 2501, 2483 }, { 2502, 2484 }, { 2513, 2515 }, { 2514, 2515 }, { 2551, 2550 }, { 2552, 2550 }, { 2573, 2567 }, { 2574, 2568 }, { 2575, 2569 }, { 2576, 2570 }, { 2577, 2571 }, { 2578, 2572 }, { 2579, 2567 }, { 2580, 2568 }, { 2581, 2569 }, { 2582, 2570 }, { 2583, 2571 }, { 2584, 2572 }, { 2595, 2591 }, { 2596, 2592 }, { 2597, 2593 }, { 2598, 2594 }, { 2599, 2591 }, { 2600, 2592 }, { 2601, 2593 }, { 2602, 2594 }, { 2613, 2607 }, { 2614, 2608 }, { 2615, 2609 }, { 2616, 2610 }, { 2617, 2611 }, { 2618, 2612 }, { 2619, 2607 }, { 2620, 2608 }, { 2621, 2609 }, { 2622, 2610 }, { 2623, 2611 }, { 2624, 2612 }, { 2635, 2631 }, { 2636, 2632 }, { 2637, 2633 }, { 2638, 2634 }, { 2639, 2631 }, { 2640, 2632 }, { 2641, 2633 }, { 2642, 2634 }, { 2652, 2651 }, { 2653, 2651 }, { 2661, 2660 }, { 2662, 2660 }, { 2667, 2666 }, { 2668, 2666 }, { 2692, 2694 }, { 2693, 2694 }, { 2696, 2695 }, { 2697, 2695 }, { 2726, 2717 }, { 2727, 2718 }, { 2728, 2719 }, { 2729, 2720 }, { 2730, 2721 }, { 2731, 2722 }, { 2732, 2723 }, { 2733, 2724 }, { 2734, 2725 }, { 2735, 2717 }, { 2737, 2719 }, { 2738, 2720 }, { 2740, 2722 }, { 2741, 2723 }, { 2742, 2724 }, { 2743, 2725 }, { 2760, 2759 }, { 2771, 2768 }, { 2772, 2769 }, { 2773, 2770 }, { 2786, 2785 }, { 2800, 2797 }, { 2801, 2798 }, { 2802, 2799 }, { 2822, 2815 }, { 2823, 2816 }, { 2824, 2817 }, { 2825, 2818 }, { 2826, 2819 }, { 2827, 2820 }, { 2828, 2821 }, { 2829, 2815 }, { 2832, 2818 }, { 2835, 2821 }, { 2850, 2848 }, { 2851, 2849 }, { 2852, 2848 }, { 2853, 2849 }, { 2881, 2880 }, { 2882, 2880 }, { 7719, 7686 }, { 7720, 7687 }, { 7721, 7688 }, { 7722, 7689 }, { 7723, 7690 }, { 7724, 7691 }, { 7725, 7692 }, { 7726, 7693 }, { 7727, 7694 }, { 7728, 7695 }, { 7729, 7696 }, { 7730, 7697 }, { 7731, 7698 }, { 7732, 7699 }, { 7733, 7700 }, { 7734, 7701 }, { 7735, 7702 }, { 7736, 7703 }, { 7737, 7704 }, { 7738, 7705 }, { 7739, 7706 }, { 7740, 7707 }, { 7741, 7708 }, { 7742, 7709 }, { 7743, 7710 }, { 7744, 7711 }, { 7745, 7712 }, { 7746, 7713 }, { 7747, 7714 }, { 7748, 7715 }, { 7749, 7716 }, { 7750, 7717 }, { 7751, 7718 }, { 7752, 7686 }, { 7753, 7687 }, { 7754, 7688 }, { 7755, 7689 }, { 7756, 7690 }, { 7757, 7691 }, { 7758, 7692 }, { 7759, 7693 }, { 7760, 7694 }, { 7761, 7695 }, { 7762, 7696 }, { 7763, 7697 }, { 7764, 7698 }, { 7765, 7699 }, { 7766, 7700 }, { 7767, 7701 }, { 7768, 7702 }, { 7769, 7703 }, { 7770, 7704 }, { 7771, 7705 }, { 7772, 7706 }, { 7773, 7707 }, { 7774, 7708 }, { 7775, 7709 }, { 7776, 7710 }, { 7777, 7711 }, { 7778, 7712 }, { 7779, 7713 }, { 7780, 7714 }, { 7781, 7715 }, { 7782, 7716 }, { 7783, 7717 }, { 7784, 7718 }, { 8290, 8319 }, { 8294, 8320 }, { 8295, 8321 }, { 8296, 8322 }, { 8297, 8323 }, { 8298, 8324 }, { 8299, 8325 }, { 8303, 8326 }, { 8304, 8327 }, { 8305, 8328 }, { 8306, 8329 }, { 8307, 8330 }, { 8308, 8331 }, { 8312, 8332 }, { 8313, 8333 }, { 8314, 8334 }, { 8315, 8335 }, { 8316, 8336 }, { 8498, 8617 }, { 8499, 8618 }, { 8500, 8619 }, { 8504, 8620 }, { 8505, 8621 }, { 8506, 8622 }, { 8507, 8623 }, { 8508, 8624 }, { 8509, 8625 }, { 8513, 8626 }, { 8514, 8627 }, { 8515, 8628 }, { 8516, 8629 }, { 8517, 8630 }, { 8518, 8631 }, { 8522, 8632 }, { 8523, 8633 }, { 8524, 8634 }, { 8525, 8635 }, { 8526, 8636 }, { 8527, 8637 }, { 8528, 8638 }, { 8870, 8897 }, { 8874, 8898 }, { 8875, 8899 }, { 8876, 8900 }, { 8877, 8901 }, { 8878, 8902 }, { 8879, 8903 }, { 8883, 8904 }, { 8884, 8905 }, { 8885, 8906 }, { 8886, 8907 }, { 8887, 8908 }, { 8888, 8909 }, { 8892, 8910 }, { 8893, 8911 }, { 8894, 8912 }, { 8895, 8913 }, { 8896, 8914 }, { 8991, 9022 }, { 8992, 9023 }, { 8993, 9024 }, { 8994, 9025 }, { 8995, 9026 }, { 8996, 9027 }, { 8997, 9028 }, { 8998, 9029 }, { 8999, 9030 }, { 9000, 9031 }, { 9001, 9032 }, { 9002, 9033 }, { 9003, 9034 }, { 9004, 9035 }, { 9005, 9036 }, { 9006, 9037 }, { 9007, 9038 }, { 9008, 9039 }, { 9009, 9040 }, { 9010, 9041 }, { 9011, 9042 }, { 9012, 9043 }, { 9013, 9044 }, { 9014, 9045 }, { 9015, 9046 }, { 9016, 9047 }, { 9017, 9048 }, { 9018, 9049 }, { 9019, 9050 }, { 9020, 9051 }, { 9021, 9052 }, { 9169, 9191 }, { 9170, 9192 }, { 9171, 9193 }, { 9174, 9194 }, { 9175, 9195 }, { 9176, 9196 }, { 9177, 9197 }, { 9180, 9198 }, { 9181, 9199 }, { 9182, 9200 }, { 9183, 9201 }, { 9186, 9202 }, { 9187, 9203 }, { 9188, 9204 }, { 9189, 9205 }, { 9190, 9206 }, { 9249, 9271 }, { 9250, 9272 }, { 9251, 9273 }, { 9254, 9274 }, { 9255, 9275 }, { 9256, 9276 }, { 9257, 9277 }, { 9260, 9278 }, { 9261, 9279 }, { 9262, 9280 }, { 9263, 9281 }, { 9266, 9282 }, { 9267, 9283 }, { 9268, 9284 }, { 9269, 9285 }, { 9270, 9286 }, { 9291, 9447 }, { 9292, 9448 }, { 9297, 9449 }, { 9298, 9450 }, { 9299, 9451 }, { 9300, 9452 }, { 9301, 9453 }, { 9302, 9454 }, { 9303, 9455 }, { 9304, 9456 }, { 9309, 9457 }, { 9310, 9458 }, { 9311, 9459 }, { 9312, 9460 }, { 9313, 9461 }, { 9314, 9462 }, { 9315, 9463 }, { 9316, 9464 }, { 9321, 9465 }, { 9322, 9466 }, { 9323, 9467 }, { 9324, 9468 }, { 9325, 9469 }, { 9326, 9470 }, { 9387, 9423 }, { 9388, 9424 }, { 9393, 9425 }, { 9394, 9426 }, { 9395, 9427 }, { 9396, 9428 }, { 9397, 9429 }, { 9398, 9430 }, { 9399, 9431 }, { 9400, 9432 }, { 9405, 9433 }, { 9406, 9434 }, { 9407, 9435 }, { 9408, 9436 }, { 9409, 9437 }, { 9410, 9438 }, { 9411, 9439 }, { 9412, 9440 }, { 9417, 9441 }, { 9418, 9442 }, { 9419, 9443 }, { 9420, 9444 }, { 9421, 9445 }, { 9422, 9446 }, { 9509, 9524 }, { 9510, 9525 }, { 9511, 9526 }, { 9512, 9527 }, { 9513, 9528 }, { 9514, 9529 }, { 9515, 9530 }, { 9516, 9531 }, { 9517, 9532 }, { 9518, 9533 }, { 9519, 9534 }, { 9520, 9535 }, { 9521, 9536 }, { 9522, 9537 }, { 9523, 9538 }, { 9539, 9559 }, { 9540, 9560 }, { 9541, 9561 }, { 9542, 9562 }, { 9551, 9555 }, { 9552, 9556 }, { 9553, 9557 }, { 9554, 9558 }, { 9866, 9893 }, { 9870, 9894 }, { 9871, 9895 }, { 9872, 9896 }, { 9873, 9897 }, { 9874, 9898 }, { 9875, 9899 }, { 9879, 9900 }, { 9880, 9901 }, { 9881, 9902 }, { 9882, 9903 }, { 9883, 9904 }, { 9884, 9905 }, { 9888, 9906 }, { 9889, 9907 }, { 9890, 9908 }, { 9891, 9909 }, { 9892, 9910 }, { 10120, 10297 }, { 10124, 10298 }, { 10125, 10299 }, { 10126, 10300 }, { 10127, 10301 }, { 10128, 10302 }, { 10138, 10303 }, { 10142, 10304 }, { 10143, 10305 }, { 10144, 10306 }, { 10145, 10307 }, { 10146, 10308 }, { 10246, 10273 }, { 10250, 10274 }, { 10251, 10275 }, { 10252, 10276 }, { 10253, 10277 }, { 10254, 10278 }, { 10255, 10279 }, { 10259, 10280 }, { 10260, 10281 }, { 10261, 10282 }, { 10262, 10283 }, { 10263, 10284 }, { 10264, 10285 }, { 10268, 10286 }, { 10269, 10287 }, { 10270, 10288 }, { 10271, 10289 }, { 10272, 10290 }, { 10345, 10363 }, { 10346, 10364 }, { 10347, 10365 }, { 10348, 10366 }, { 10349, 10367 }, { 10350, 10368 }, { 10351, 10369 }, { 10352, 10370 }, { 10353, 10371 }, { 10354, 10372 }, { 10355, 10373 }, { 10356, 10374 }, { 10357, 10375 }, { 10358, 10376 }, { 10359, 10377 }, { 10360, 10378 }, { 10361, 10379 }, { 10362, 10380 }, { 10389, 10393 }, { 10390, 10394 }, { 10391, 10396 }, { 10392, 10397 }, { 10421, 10423 }, { 10422, 10424 }, { 10437, 10439 }, { 10438, 10440 }, { 10483, 10487 }, { 10484, 10488 }, { 10485, 10489 }, { 10486, 10490 }, { 10728, 10757 }, { 10732, 10758 }, { 10733, 10759 }, { 10734, 10760 }, { 10735, 10761 }, { 10736, 10762 }, { 10737, 10763 }, { 10741, 10764 }, { 10742, 10765 }, { 10743, 10766 }, { 10744, 10767 }, { 10745, 10768 }, { 10746, 10769 }, { 10750, 10770 }, { 10751, 10771 }, { 10752, 10772 }, { 10753, 10773 }, { 10754, 10774 }, { 10830, 10859 }, { 10834, 10860 }, { 10835, 10861 }, { 10836, 10862 }, { 10837, 10863 }, { 10838, 10864 }, { 10839, 10865 }, { 10843, 10866 }, { 10844, 10867 }, { 10845, 10868 }, { 10846, 10869 }, { 10847, 10870 }, { 10848, 10871 }, { 10852, 10872 }, { 10853, 10873 }, { 10854, 10874 }, { 10855, 10875 }, { 10856, 10876 }, { 10932, 10961 }, { 10936, 10962 }, { 10937, 10963 }, { 10938, 10964 }, { 10939, 10965 }, { 10940, 10966 }, { 10941, 10967 }, { 10945, 10968 }, { 10946, 10969 }, { 10947, 10970 }, { 10948, 10971 }, { 10949, 10972 }, { 10950, 10973 }, { 10954, 10974 }, { 10955, 10975 }, { 10956, 10976 }, { 10957, 10977 }, { 10958, 10978 }, { 11034, 11063 }, { 11038, 11064 }, { 11039, 11065 }, { 11040, 11066 }, { 11041, 11067 }, { 11042, 11068 }, { 11043, 11069 }, { 11047, 11070 }, { 11048, 11071 }, { 11049, 11072 }, { 11050, 11073 }, { 11051, 11074 }, { 11052, 11075 }, { 11056, 11076 }, { 11057, 11077 }, { 11058, 11078 }, { 11059, 11079 }, { 11060, 11080 }, { 11125, 11128 }, { 11126, 11129 }, { 11127, 11130 }, { 11133, 11493 }, { 11134, 11494 }, { 11135, 11495 }, { 11136, 11496 }, { 11137, 11497 }, { 11138, 11498 }, { 11139, 11499 }, { 11140, 11500 }, { 11141, 11501 }, { 11142, 11502 }, { 11143, 11503 }, { 11144, 11504 }, { 11145, 11505 }, { 11146, 11506 }, { 11147, 11507 }, { 11148, 11508 }, { 11149, 11509 }, { 11150, 11510 }, { 11211, 11256 }, { 11212, 11257 }, { 11213, 11258 }, { 11214, 11259 }, { 11215, 11260 }, { 11216, 11261 }, { 11217, 11262 }, { 11218, 11263 }, { 11219, 11264 }, { 11220, 11265 }, { 11221, 11266 }, { 11222, 11267 }, { 11223, 11268 }, { 11224, 11269 }, { 11225, 11270 }, { 11293, 11315 }, { 11294, 11316 }, { 11295, 11317 }, { 11296, 11318 }, { 11297, 11319 }, { 11298, 11320 }, { 11299, 11321 }, { 11300, 11322 }, { 11301, 11323 }, { 11302, 11324 }, { 11303, 11325 }, { 11304, 11326 }, { 11305, 11327 }, { 11306, 11328 }, { 11307, 11329 }, { 11308, 11330 }, { 11309, 11331 }, { 11310, 11332 }, { 11311, 11333 }, { 11312, 11334 }, { 11313, 11335 }, { 11314, 11336 }, { 11433, 11478 }, { 11434, 11479 }, { 11435, 11480 }, { 11436, 11481 }, { 11437, 11482 }, { 11438, 11483 }, { 11439, 11484 }, { 11440, 11485 }, { 11441, 11486 }, { 11442, 11487 }, { 11443, 11488 }, { 11444, 11489 }, { 11445, 11490 }, { 11446, 11491 }, { 11447, 11492 }, { 11533, 11555 }, { 11534, 11556 }, { 11535, 11557 }, { 11536, 11558 }, { 11537, 11559 }, { 11538, 11560 }, { 11539, 11561 }, { 11540, 11562 }, { 11541, 11563 }, { 11542, 11564 }, { 11543, 11565 }, { 11544, 11566 }, { 11545, 11567 }, { 11546, 11568 }, { 11547, 11569 }, { 11548, 11570 }, { 11549, 11571 }, { 11550, 11572 }, { 11551, 11573 }, { 11552, 11574 }, { 11553, 11575 }, { 11554, 11576 }, { 11771, 11800 }, { 11775, 11801 }, { 11776, 11802 }, { 11777, 11803 }, { 11778, 11804 }, { 11779, 11805 }, { 11780, 11806 }, { 11784, 11807 }, { 11785, 11808 }, { 11786, 11809 }, { 11787, 11810 }, { 11788, 11811 }, { 11789, 11812 }, { 11793, 11813 }, { 11794, 11814 }, { 11795, 11815 }, { 11796, 11816 }, { 11797, 11817 }, { 11923, 11950 }, { 11927, 11951 }, { 11928, 11952 }, { 11929, 11953 }, { 11930, 11954 }, { 11931, 11955 }, { 11932, 11956 }, { 11936, 11957 }, { 11937, 11958 }, { 11938, 11959 }, { 11939, 11960 }, { 11940, 11961 }, { 11941, 11962 }, { 11945, 11963 }, { 11946, 11964 }, { 11947, 11965 }, { 11948, 11966 }, { 11949, 11967 }, { 12258, 12264 }, { 12259, 12265 }, { 12260, 12266 }, { 12261, 12267 }, { 12262, 12268 }, { 12263, 12269 }, { 12300, 12304 }, { 12301, 12305 }, { 12302, 12306 }, { 12303, 12307 }, { 12342, 12438 }, { 12343, 12439 }, { 12344, 12440 }, { 12345, 12441 }, { 12346, 12442 }, { 12347, 12443 }, { 12351, 12444 }, { 12352, 12445 }, { 12353, 12446 }, { 12354, 12447 }, { 12355, 12448 }, { 12356, 12449 }, { 12360, 12450 }, { 12361, 12451 }, { 12362, 12452 }, { 12363, 12453 }, { 12364, 12454 }, { 12365, 12455 }, { 12393, 12420 }, { 12397, 12421 }, { 12398, 12422 }, { 12399, 12423 }, { 12400, 12424 }, { 12401, 12425 }, { 12402, 12426 }, { 12406, 12427 }, { 12407, 12428 }, { 12408, 12429 }, { 12409, 12430 }, { 12410, 12431 }, { 12411, 12432 }, { 12415, 12433 }, { 12416, 12434 }, { 12417, 12435 }, { 12418, 12436 }, { 12419, 12437 }, { 12460, 12464 }, { 12461, 12465 }, { 12462, 12466 }, { 12463, 12467 }, { 12498, 12594 }, { 12499, 12595 }, { 12500, 12596 }, { 12501, 12597 }, { 12502, 12598 }, { 12503, 12599 }, { 12507, 12600 }, { 12508, 12601 }, { 12509, 12602 }, { 12510, 12603 }, { 12511, 12604 }, { 12512, 12605 }, { 12516, 12606 }, { 12517, 12607 }, { 12518, 12608 }, { 12519, 12609 }, { 12520, 12610 }, { 12521, 12611 }, { 12549, 12576 }, { 12553, 12577 }, { 12554, 12578 }, { 12555, 12579 }, { 12556, 12580 }, { 12557, 12581 }, { 12558, 12582 }, { 12562, 12583 }, { 12563, 12584 }, { 12564, 12585 }, { 12565, 12586 }, { 12566, 12587 }, { 12567, 12588 }, { 12571, 12589 }, { 12572, 12590 }, { 12573, 12591 }, { 12574, 12592 }, { 12575, 12593 }, { 12792, 12923 }, { 12793, 12924 }, { 12794, 12925 }, { 12798, 12926 }, { 12799, 12927 }, { 12800, 12928 }, { 12801, 12929 }, { 12802, 12930 }, { 12803, 12931 }, { 12804, 12932 }, { 12805, 12933 }, { 12806, 12934 }, { 12807, 12935 }, { 12808, 12936 }, { 12809, 12937 }, { 12813, 12938 }, { 12814, 12939 }, { 12815, 12940 }, { 12816, 12941 }, { 12817, 12942 }, { 12818, 12943 }, { 12819, 12944 }, { 12820, 12945 }, { 12821, 12946 }, { 12822, 12947 }, { 12823, 12948 }, { 12824, 12949 }, { 12828, 12950 }, { 12829, 12951 }, { 12830, 12952 }, { 12831, 12953 }, { 12832, 12954 }, { 12833, 12955 }, { 12834, 12956 }, { 12835, 12957 }, { 12836, 12958 }, { 12837, 12959 }, { 12838, 12960 }, { 12839, 12961 }, { 12840, 12962 }, { 12841, 12963 }, { 12842, 12964 }, { 12876, 12905 }, { 12880, 12906 }, { 12881, 12907 }, { 12882, 12908 }, { 12883, 12909 }, { 12884, 12910 }, { 12885, 12911 }, { 12889, 12912 }, { 12890, 12913 }, { 12891, 12914 }, { 12892, 12915 }, { 12893, 12916 }, { 12894, 12917 }, { 12898, 12918 }, { 12899, 12919 }, { 12900, 12920 }, { 12901, 12921 }, { 12902, 12922 }, { 13019, 13140 }, { 13020, 13141 }, { 13021, 13142 }, { 13022, 13143 }, { 13023, 13144 }, { 13024, 13145 }, { 13025, 13146 }, { 13026, 13147 }, { 13027, 13148 }, { 13028, 13149 }, { 13029, 13150 }, { 13030, 13151 }, { 13034, 13152 }, { 13035, 13153 }, { 13036, 13154 }, { 13037, 13155 }, { 13038, 13156 }, { 13039, 13157 }, { 13040, 13158 }, { 13041, 13159 }, { 13042, 13160 }, { 13043, 13161 }, { 13044, 13162 }, { 13045, 13163 }, { 13049, 13164 }, { 13050, 13165 }, { 13051, 13166 }, { 13052, 13167 }, { 13053, 13168 }, { 13054, 13169 }, { 13055, 13170 }, { 13056, 13171 }, { 13057, 13172 }, { 13058, 13173 }, { 13059, 13174 }, { 13060, 13175 }, { 13092, 13119 }, { 13096, 13120 }, { 13097, 13121 }, { 13098, 13122 }, { 13099, 13123 }, { 13100, 13124 }, { 13101, 13125 }, { 13105, 13126 }, { 13106, 13127 }, { 13107, 13128 }, { 13108, 13129 }, { 13109, 13130 }, { 13110, 13131 }, { 13114, 13132 }, { 13115, 13133 }, { 13116, 13134 }, { 13117, 13135 }, { 13118, 13136 }, { 13238, 13369 }, { 13239, 13370 }, { 13240, 13371 }, { 13244, 13372 }, { 13245, 13373 }, { 13246, 13374 }, { 13247, 13375 }, { 13248, 13376 }, { 13249, 13377 }, { 13250, 13378 }, { 13251, 13379 }, { 13252, 13380 }, { 13253, 13381 }, { 13254, 13382 }, { 13255, 13383 }, { 13259, 13384 }, { 13260, 13385 }, { 13261, 13386 }, { 13262, 13387 }, { 13263, 13388 }, { 13264, 13389 }, { 13265, 13390 }, { 13266, 13391 }, { 13267, 13392 }, { 13268, 13393 }, { 13269, 13394 }, { 13270, 13395 }, { 13274, 13396 }, { 13275, 13397 }, { 13276, 13398 }, { 13277, 13399 }, { 13278, 13400 }, { 13279, 13401 }, { 13280, 13402 }, { 13281, 13403 }, { 13282, 13404 }, { 13283, 13405 }, { 13284, 13406 }, { 13285, 13407 }, { 13286, 13408 }, { 13287, 13409 }, { 13288, 13410 }, { 13322, 13351 }, { 13326, 13352 }, { 13327, 13353 }, { 13328, 13354 }, { 13329, 13355 }, { 13330, 13356 }, { 13331, 13357 }, { 13335, 13358 }, { 13336, 13359 }, { 13337, 13360 }, { 13338, 13361 }, { 13339, 13362 }, { 13340, 13363 }, { 13344, 13364 }, { 13345, 13365 }, { 13346, 13366 }, { 13347, 13367 }, { 13348, 13368 }, { 13464, 13583 }, { 13465, 13584 }, { 13466, 13585 }, { 13470, 13586 }, { 13471, 13587 }, { 13472, 13588 }, { 13473, 13589 }, { 13474, 13590 }, { 13475, 13591 }, { 13479, 13592 }, { 13480, 13593 }, { 13481, 13594 }, { 13482, 13595 }, { 13483, 13596 }, { 13484, 13597 }, { 13488, 13598 }, { 13489, 13599 }, { 13490, 13600 }, { 13491, 13601 }, { 13492, 13602 }, { 13493, 13603 }, { 13494, 13604 }, { 13689, 13707 }, { 13692, 13708 }, { 13693, 13709 }, { 13694, 13710 }, { 13695, 13711 }, { 13698, 13712 }, { 13699, 13713 }, { 13700, 13714 }, { 13701, 13715 }, { 13704, 13716 }, { 13705, 13717 }, { 13706, 13718 }, { 13749, 13767 }, { 13752, 13768 }, { 13753, 13769 }, { 13754, 13770 }, { 13755, 13771 }, { 13758, 13772 }, { 13759, 13773 }, { 13760, 13774 }, { 13761, 13775 }, { 13764, 13776 }, { 13765, 13777 }, { 13766, 13778 }, { 15199, 15197 }, { 15200, 15198 }, { 15201, 15197 }, { 15202, 15198 }, { 15210, 15207 }, { 15211, 15208 }, { 15212, 15209 }, { 15213, 15207 }, { 15214, 15208 }, { 15215, 15209 }, { 15236, 15227 }, { 15237, 15228 }, { 15238, 15229 }, { 15239, 15230 }, { 15240, 15231 }, { 15241, 15232 }, { 15242, 15233 }, { 15243, 15234 }, { 15244, 15235 }, { 15245, 15227 }, { 15247, 15229 }, { 15248, 15230 }, { 15250, 15232 }, { 15251, 15233 }, { 15252, 15234 }, { 15253, 15235 }, }; static const uint16_t x86_16_bit_eq_lookup[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 0, 13, 14, 0, 15, 16, 17, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 0, 29, 30, 0, 31, 32, 33, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 37, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 0, 49, 50, 0, 51, 52, 53, 54, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 0, 56, 57, 58, 59, 0, 0, 60, 61, 62, 63, 0, 0, 0, 0, 0, 0, 0, 64, 65, 66, 67, 68, 69, 70, 71, 0, 0, 0, 0, 72, 73, 74, 75, 76, 77, 78, 79, 0, 0, 0, 0, 80, 81, 82, 83, 84, 85, 86, 87, 0, 0, 0, 0, 88, 89, 90, 91, 92, 93, 94, 95, 0, 0, 0, 0, 0, 0, 0, 0, 96, 97, 98, 99, 100, 101, 0, 102, 103, 0, 104, 0, 0, 0, 0, 0, 0, 0, 0, 0, 105, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 107, 108, 109, 0, 0, 110, 111, 112, 113, 0, 0, 114, 115, 116, 117, 0, 0, 118, 119, 120, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 122, 123, 124, 125, 0, 0, 0, 0, 0, 0, 126, 127, 128, 129, 0, 0, 130, 131, 132, 133, 0, 0, 134, 135, 136, 137, 0, 0, 138, 139, 140, 141, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 142, 143, 144, 145, 0, 0, 0, 0, 0, 0, 146, 147, 148, 149, 0, 0, 150, 151, 152, 153, 0, 0, 0, 0, 0, 0, 154, 155, 156, 157, 0, 0, 158, 159, 160, 161, 0, 0, 162, 163, 164, 165, 0, 0, 0, 0, 0, 0, 166, 167, 168, 169, 0, 0, 0, 0, 0, 0, 0, 0, 0, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 0, 180, 181, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1554, 1555, 1556, 1557, 0, 0, 0, 0, 0, 0, 0, 1558, 1559, 1560, 1561, 1562, 1563, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1564, 1565, 1566, 1567, 1568, 1569, 1570, 1571, 1572, 1573, 0, 1574, 1575, 0, 1576, 1577, 1578, 1579, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; capstone-sys-0.15.0/capstone/arch/X86/X86Lookup16_reduce.inc000064400000000000000000000427500072674642500214650ustar 00000000000000typedef struct x86_op_id_pair { uint16_t first; uint16_t second; } x86_op_id_pair; static const x86_op_id_pair x86_16_bit_eq_tbl[] = { { 139, 130 }, { 140, 131 }, { 141, 132 }, { 142, 133 }, { 143, 134 }, { 144, 135 }, { 145, 136 }, { 146, 137 }, { 147, 138 }, { 148, 130 }, { 150, 132 }, { 151, 133 }, { 153, 135 }, { 154, 136 }, { 155, 137 }, { 156, 138 }, { 179, 170 }, { 180, 171 }, { 181, 172 }, { 182, 173 }, { 183, 174 }, { 184, 175 }, { 185, 176 }, { 186, 177 }, { 187, 178 }, { 188, 170 }, { 190, 172 }, { 191, 173 }, { 193, 175 }, { 194, 176 }, { 195, 177 }, { 196, 178 }, { 219, 210 }, { 220, 211 }, { 221, 212 }, { 222, 213 }, { 223, 214 }, { 224, 215 }, { 225, 216 }, { 226, 217 }, { 227, 218 }, { 228, 210 }, { 230, 212 }, { 231, 213 }, { 233, 215 }, { 234, 216 }, { 235, 217 }, { 236, 218 }, { 301, 300 }, { 304, 302 }, { 305, 303 }, { 306, 302 }, { 307, 303 }, { 310, 308 }, { 311, 309 }, { 312, 308 }, { 313, 309 }, { 321, 317 }, { 322, 318 }, { 323, 319 }, { 324, 320 }, { 325, 317 }, { 326, 318 }, { 327, 319 }, { 328, 320 }, { 333, 329 }, { 334, 330 }, { 335, 331 }, { 336, 332 }, { 337, 329 }, { 338, 330 }, { 339, 331 }, { 340, 332 }, { 345, 341 }, { 346, 342 }, { 347, 343 }, { 348, 344 }, { 349, 341 }, { 350, 342 }, { 351, 343 }, { 352, 344 }, { 357, 353 }, { 358, 354 }, { 359, 355 }, { 360, 356 }, { 361, 353 }, { 362, 354 }, { 363, 355 }, { 364, 356 }, { 373, 369 }, { 374, 370 }, { 375, 371 }, { 376, 372 }, { 377, 369 }, { 378, 370 }, { 380, 371 }, { 381, 372 }, { 383, 382 }, { 389, 547 }, { 401, 399 }, { 402, 400 }, { 403, 399 }, { 404, 400 }, { 407, 405 }, { 408, 406 }, { 409, 405 }, { 410, 406 }, { 413, 411 }, { 414, 412 }, { 415, 411 }, { 416, 412 }, { 419, 417 }, { 420, 418 }, { 421, 417 }, { 422, 418 }, { 425, 423 }, { 426, 424 }, { 427, 423 }, { 428, 424 }, { 431, 429 }, { 432, 430 }, { 433, 429 }, { 434, 430 }, { 437, 435 }, { 438, 436 }, { 439, 435 }, { 440, 436 }, { 443, 441 }, { 444, 442 }, { 445, 441 }, { 446, 442 }, { 449, 447 }, { 450, 448 }, { 451, 447 }, { 452, 448 }, { 455, 453 }, { 456, 454 }, { 457, 453 }, { 458, 454 }, { 461, 459 }, { 462, 460 }, { 463, 459 }, { 464, 460 }, { 467, 465 }, { 468, 466 }, { 469, 465 }, { 470, 466 }, { 473, 471 }, { 474, 472 }, { 475, 471 }, { 476, 472 }, { 479, 477 }, { 480, 478 }, { 481, 477 }, { 482, 478 }, { 485, 483 }, { 486, 484 }, { 487, 483 }, { 488, 484 }, { 491, 489 }, { 492, 490 }, { 493, 489 }, { 494, 490 }, { 504, 495 }, { 505, 496 }, { 506, 497 }, { 507, 498 }, { 508, 499 }, { 509, 500 }, { 510, 501 }, { 511, 502 }, { 512, 503 }, { 513, 495 }, { 515, 497 }, { 516, 498 }, { 518, 500 }, { 519, 501 }, { 520, 502 }, { 521, 503 }, { 532, 534 }, { 533, 534 }, { 538, 536 }, { 539, 537 }, { 540, 536 }, { 541, 537 }, { 555, 552 }, { 556, 553 }, { 557, 554 }, { 558, 552 }, { 559, 553 }, { 564, 562 }, { 565, 563 }, { 566, 562 }, { 567, 563 }, { 575, 573 }, { 576, 574 }, { 580, 578 }, { 581, 579 }, { 588, 586 }, { 589, 587 }, { 590, 586 }, { 591, 587 }, { 602, 594 }, { 603, 595 }, { 604, 596 }, { 605, 597 }, { 606, 598 }, { 607, 599 }, { 608, 600 }, { 609, 601 }, { 610, 594 }, { 611, 595 }, { 612, 596 }, { 614, 598 }, { 615, 599 }, { 617, 601 }, { 622, 620 }, { 623, 621 }, { 629, 626 }, { 630, 627 }, { 631, 628 }, { 632, 626 }, { 633, 627 }, { 639, 640 }, { 643, 642 }, { 656, 655 }, { 657, 655 }, { 691, 687 }, { 692, 688 }, { 693, 689 }, { 694, 690 }, { 695, 687 }, { 696, 688 }, { 697, 689 }, { 698, 690 }, { 727, 725 }, { 728, 726 }, { 729, 725 }, { 730, 726 }, { 732, 731 }, { 734, 733 }, { 736, 733 }, { 740, 739 }, { 742, 741 }, { 743, 741 }, { 745, 744 }, { 746, 744 }, { 748, 747 }, { 749, 747 }, { 751, 750 }, { 752, 750 }, { 761, 763 }, { 762, 763 }, { 767, 769 }, { 768, 769 }, { 770, 772 }, { 771, 772 }, { 775, 773 }, { 776, 774 }, { 777, 773 }, { 778, 774 }, { 780, 779 }, { 781, 779 }, { 794, 792 }, { 795, 793 }, { 796, 792 }, { 797, 793 }, { 801, 800 }, { 802, 800 }, { 807, 806 }, { 808, 806 }, { 817, 800 }, { 818, 800 }, { 818, 801 }, { 818, 817 }, { 819, 800 }, { 819, 802 }, { 819, 817 }, { 822, 803 }, { 823, 804 }, { 824, 806 }, { 825, 806 }, { 825, 807 }, { 825, 824 }, { 826, 806 }, { 826, 808 }, { 826, 824 }, { 829, 809 }, { 830, 810 }, { 831, 811 }, { 832, 812 }, { 833, 813 }, { 834, 814 }, { 835, 816 }, { 836, 800 }, { 836, 801 }, { 837, 800 }, { 837, 802 }, { 841, 804 }, { 842, 806 }, { 842, 807 }, { 843, 806 }, { 843, 808 }, { 846, 809 }, { 848, 811 }, { 849, 812 }, { 850, 813 }, { 851, 814 }, { 852, 816 }, { 854, 853 }, { 855, 853 }, { 860, 859 }, { 861, 859 }, { 871, 869 }, { 872, 870 }, { 873, 869 }, { 874, 870 }, { 876, 875 }, { 877, 875 }, { 881, 883 }, { 882, 883 }, { 888, 884 }, { 889, 885 }, { 891, 886 }, { 892, 887 }, { 894, 884 }, { 895, 884 }, { 895, 894 }, { 896, 885 }, { 897, 886 }, { 898, 886 }, { 898, 897 }, { 899, 887 }, { 904, 900 }, { 905, 901 }, { 907, 902 }, { 908, 903 }, { 910, 900 }, { 911, 901 }, { 912, 902 }, { 913, 903 }, { 916, 914 }, { 917, 915 }, { 918, 914 }, { 919, 915 }, { 929, 927 }, { 930, 928 }, { 931, 927 }, { 932, 928 }, { 936, 938 }, { 940, 942 }, { 944, 946 }, { 948, 950 }, { 953, 960 }, { 954, 961 }, { 955, 963 }, { 956, 964 }, { 957, 965 }, { 958, 960 }, { 959, 965 }, { 968, 966 }, { 969, 967 }, { 970, 966 }, { 971, 967 }, { 983, 974 }, { 984, 975 }, { 985, 976 }, { 986, 977 }, { 987, 978 }, { 988, 979 }, { 989, 980 }, { 990, 981 }, { 991, 982 }, { 992, 974 }, { 994, 976 }, { 995, 977 }, { 997, 979 }, { 998, 980 }, { 999, 981 }, { 1000, 982 }, { 1012, 1010 }, { 1013, 1011 }, { 1017, 1018 }, { 1031, 1028 }, { 1032, 1029 }, { 1033, 1030 }, { 1034, 1028 }, { 1035, 1029 }, { 1036, 1030 }, { 1038, 1037 }, { 1040, 1039 }, { 1042, 1041 }, { 1044, 1043 }, { 1045, 1043 }, { 1047, 1046 }, { 1048, 1046 }, { 1050, 1049 }, { 1051, 1049 }, { 1053, 1052 }, { 1062, 1058 }, { 1063, 1059 }, { 1064, 1060 }, { 1065, 1061 }, { 1067, 1058 }, { 1068, 1059 }, { 1069, 1060 }, { 1070, 1061 }, { 1072, 1071 }, { 1074, 1073 }, { 1076, 1075 }, { 1078, 1077 }, { 1080, 1079 }, { 1081, 1079 }, { 1083, 1082 }, { 1084, 1082 }, { 1086, 1085 }, { 1087, 1085 }, { 1089, 1088 }, { 1091, 1090 }, { 1098, 1092 }, { 1099, 1093 }, { 1100, 1094 }, { 1101, 1095 }, { 1102, 1096 }, { 1103, 1097 }, { 1104, 1092 }, { 1105, 1093 }, { 1106, 1094 }, { 1107, 1095 }, { 1108, 1096 }, { 1109, 1097 }, { 1122, 1116 }, { 1123, 1117 }, { 1124, 1118 }, { 1125, 1119 }, { 1126, 1120 }, { 1127, 1121 }, { 1128, 1116 }, { 1129, 1117 }, { 1130, 1118 }, { 1131, 1119 }, { 1132, 1120 }, { 1133, 1121 }, { 1150, 1149 }, { 1151, 1149 }, { 1153, 1152 }, { 1154, 1152 }, { 1161, 1163 }, { 1162, 1163 }, { 1164, 1166 }, { 1165, 1166 }, { 1174, 1168 }, { 1175, 1169 }, { 1176, 1170 }, { 1177, 1171 }, { 1178, 1172 }, { 1179, 1173 }, { 1180, 1168 }, { 1181, 1169 }, { 1182, 1170 }, { 1183, 1171 }, { 1184, 1172 }, { 1185, 1173 }, { 1198, 1192 }, { 1199, 1193 }, { 1200, 1194 }, { 1201, 1195 }, { 1202, 1196 }, { 1203, 1197 }, { 1204, 1192 }, { 1205, 1193 }, { 1206, 1194 }, { 1207, 1195 }, { 1208, 1196 }, { 1209, 1197 }, { 1229, 1223 }, { 1230, 1224 }, { 1231, 1225 }, { 1232, 1226 }, { 1233, 1227 }, { 1234, 1228 }, { 1235, 1223 }, { 1236, 1224 }, { 1237, 1225 }, { 1238, 1226 }, { 1239, 1227 }, { 1240, 1228 }, { 1254, 1248 }, { 1255, 1249 }, { 1256, 1250 }, { 1257, 1251 }, { 1258, 1252 }, { 1259, 1253 }, { 1260, 1248 }, { 1261, 1249 }, { 1262, 1250 }, { 1263, 1251 }, { 1264, 1252 }, { 1265, 1253 }, { 1286, 1277 }, { 1287, 1278 }, { 1288, 1279 }, { 1289, 1280 }, { 1290, 1281 }, { 1291, 1282 }, { 1292, 1283 }, { 1293, 1284 }, { 1294, 1285 }, { 1295, 1277 }, { 1297, 1279 }, { 1298, 1280 }, { 1300, 1282 }, { 1301, 1283 }, { 1302, 1284 }, { 1303, 1285 }, { 1314, 1316 }, { 1315, 1316 }, { 1351, 1350 }, { 1352, 1350 }, { 1359, 1353 }, { 1360, 1354 }, { 1361, 1355 }, { 1362, 1356 }, { 1363, 1357 }, { 1364, 1358 }, { 1365, 1353 }, { 1366, 1354 }, { 1367, 1355 }, { 1368, 1356 }, { 1369, 1357 }, { 1370, 1358 }, { 1381, 1377 }, { 1382, 1378 }, { 1383, 1379 }, { 1384, 1380 }, { 1385, 1377 }, { 1386, 1378 }, { 1387, 1379 }, { 1388, 1380 }, { 1399, 1393 }, { 1400, 1394 }, { 1401, 1395 }, { 1402, 1396 }, { 1403, 1397 }, { 1404, 1398 }, { 1405, 1393 }, { 1406, 1394 }, { 1407, 1395 }, { 1408, 1396 }, { 1409, 1397 }, { 1410, 1398 }, { 1421, 1417 }, { 1422, 1418 }, { 1423, 1419 }, { 1424, 1420 }, { 1425, 1417 }, { 1426, 1418 }, { 1427, 1419 }, { 1428, 1420 }, { 1434, 1433 }, { 1435, 1433 }, { 1439, 1438 }, { 1440, 1438 }, { 1445, 1444 }, { 1446, 1444 }, { 1453, 1455 }, { 1454, 1455 }, { 1457, 1456 }, { 1458, 1456 }, { 1469, 1460 }, { 1470, 1461 }, { 1471, 1462 }, { 1472, 1463 }, { 1473, 1464 }, { 1474, 1465 }, { 1475, 1466 }, { 1476, 1467 }, { 1477, 1468 }, { 1478, 1460 }, { 1480, 1462 }, { 1481, 1463 }, { 1483, 1465 }, { 1484, 1466 }, { 1485, 1467 }, { 1486, 1468 }, { 1514, 1507 }, { 1515, 1508 }, { 1516, 1509 }, { 1517, 1510 }, { 1518, 1511 }, { 1519, 1512 }, { 1520, 1513 }, { 1521, 1507 }, { 1524, 1510 }, { 1527, 1513 }, { 1538, 1536 }, { 1539, 1537 }, { 1540, 1536 }, { 1541, 1537 }, { 1550, 1549 }, { 1551, 1549 }, { 1595, 1593 }, { 1596, 1594 }, { 1597, 1593 }, { 1598, 1594 }, { 1604, 1601 }, { 1605, 1602 }, { 1606, 1603 }, { 1607, 1601 }, { 1608, 1602 }, { 1609, 1603 }, { 1628, 1619 }, { 1629, 1620 }, { 1630, 1621 }, { 1631, 1622 }, { 1632, 1623 }, { 1633, 1624 }, { 1634, 1625 }, { 1635, 1626 }, { 1636, 1627 }, { 1637, 1619 }, { 1639, 1621 }, { 1640, 1622 }, { 1642, 1624 }, { 1643, 1625 }, { 1644, 1626 }, { 1645, 1627 }, }; static const uint16_t x86_16_bit_eq_lookup[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 11, 12, 0, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 0, 27, 28, 0, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 0, 43, 44, 0, 45, 46, 47, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 0, 0, 50, 51, 52, 53, 0, 0, 54, 55, 56, 57, 0, 0, 0, 0, 0, 0, 0, 58, 59, 60, 61, 62, 63, 64, 65, 0, 0, 0, 0, 66, 67, 68, 69, 70, 71, 72, 73, 0, 0, 0, 0, 74, 75, 76, 77, 78, 79, 80, 81, 0, 0, 0, 0, 82, 83, 84, 85, 86, 87, 88, 89, 0, 0, 0, 0, 0, 0, 0, 0, 90, 91, 92, 93, 94, 95, 0, 96, 97, 0, 98, 0, 0, 0, 0, 0, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 101, 102, 103, 0, 0, 104, 105, 106, 107, 0, 0, 108, 109, 110, 111, 0, 0, 112, 113, 114, 115, 0, 0, 116, 117, 118, 119, 0, 0, 120, 121, 122, 123, 0, 0, 124, 125, 126, 127, 0, 0, 128, 129, 130, 131, 0, 0, 132, 133, 134, 135, 0, 0, 136, 137, 138, 139, 0, 0, 140, 141, 142, 143, 0, 0, 144, 145, 146, 147, 0, 0, 148, 149, 150, 151, 0, 0, 152, 153, 154, 155, 0, 0, 156, 157, 158, 159, 0, 0, 160, 161, 162, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 0, 174, 175, 0, 176, 177, 178, 179, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 180, 181, 0, 0, 0, 0, 182, 183, 184, 185, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 186, 187, 188, 189, 190, 0, 0, 0, 0, 191, 192, 193, 194, 0, 0, 0, 0, 0, 0, 0, 195, 196, 0, 0, 0, 197, 198, 0, 0, 0, 0, 0, 0, 199, 200, 201, 202, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 0, 214, 215, 0, 216, 0, 0, 0, 0, 217, 218, 0, 0, 0, 0, 0, 219, 220, 221, 222, 223, 0, 0, 0, 0, 0, 224, 0, 0, 0, 225, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 226, 227, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 228, 229, 230, 231, 232, 233, 234, 235, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 236, 237, 238, 239, 0, 240, 0, 241, 0, 242, 0, 0, 0, 243, 0, 244, 245, 0, 246, 247, 0, 248, 249, 0, 250, 251, 0, 0, 0, 0, 0, 0, 0, 0, 252, 253, 0, 0, 0, 0, 254, 255, 0, 256, 257, 0, 0, 0, 258, 259, 260, 261, 0, 262, 263, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 264, 265, 266, 267, 0, 0, 0, 268, 269, 0, 0, 0, 0, 270, 271, 0, 0, 0, 0, 0, 0, 0, 0, 272, 273, 276, 0, 0, 279, 280, 281, 282, 285, 0, 0, 288, 289, 290, 291, 292, 293, 294, 295, 297, 0, 0, 0, 299, 300, 302, 0, 0, 304, 0, 305, 306, 307, 308, 309, 0, 310, 311, 0, 0, 0, 0, 312, 313, 0, 0, 0, 0, 0, 0, 0, 0, 0, 314, 315, 316, 317, 0, 318, 319, 0, 0, 0, 320, 321, 0, 0, 0, 0, 0, 322, 323, 0, 324, 325, 0, 326, 327, 329, 330, 331, 333, 0, 0, 0, 0, 334, 335, 0, 336, 337, 0, 338, 339, 340, 341, 0, 0, 342, 343, 344, 345, 0, 0, 0, 0, 0, 0, 0, 0, 0, 346, 347, 348, 349, 0, 0, 0, 350, 0, 0, 0, 351, 0, 0, 0, 352, 0, 0, 0, 353, 0, 0, 0, 0, 354, 355, 356, 357, 358, 359, 360, 0, 0, 0, 0, 0, 0, 0, 0, 361, 362, 363, 364, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 365, 366, 367, 368, 369, 370, 371, 372, 373, 374, 0, 375, 376, 0, 377, 378, 379, 380, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 381, 382, 0, 0, 0, 383, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 384, 385, 386, 387, 388, 389, 0, 390, 0, 391, 0, 392, 0, 393, 394, 0, 395, 396, 0, 397, 398, 0, 399, 0, 0, 0, 0, 0, 0, 0, 0, 400, 401, 402, 403, 0, 404, 405, 406, 407, 0, 408, 0, 409, 0, 410, 0, 411, 0, 412, 413, 0, 414, 415, 0, 416, 417, 0, 418, 0, 419, 0, 0, 0, 0, 0, 0, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 444, 445, 0, 446, 447, 0, 0, 0, 0, 0, 0, 448, 449, 0, 450, 451, 0, 0, 0, 0, 0, 0, 0, 0, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 0, 510, 511, 0, 512, 513, 514, 515, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 516, 517, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 518, 519, 0, 0, 0, 0, 0, 0, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 532, 533, 534, 535, 536, 537, 538, 539, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 552, 553, 554, 555, 556, 557, 558, 559, 0, 0, 0, 0, 0, 560, 561, 0, 0, 0, 562, 563, 0, 0, 0, 0, 564, 565, 0, 0, 0, 0, 0, 0, 566, 567, 0, 0, 568, 569, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 0, 580, 581, 0, 582, 583, 584, 585, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 586, 587, 588, 589, 590, 591, 592, 593, 0, 0, 594, 0, 0, 595, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 596, 597, 598, 599, 0, 0, 0, 0, 0, 0, 0, 0, 600, 601, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 602, 603, 604, 605, 0, 0, 0, 0, 0, 606, 607, 608, 609, 610, 611, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 612, 613, 614, 615, 616, 617, 618, 619, 620, 621, 0, 622, 623, 0, 624, 625, 626, 627, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; capstone-sys-0.15.0/capstone/arch/X86/X86Mapping.c000064400000000000000000001726220072674642500175640ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef CAPSTONE_HAS_X86 #if defined(CAPSTONE_HAS_OSXKERNEL) #include #endif #include #ifndef CAPSTONE_HAS_OSXKERNEL #include #endif #include "X86Mapping.h" #include "X86DisassemblerDecoder.h" #include "../../utils.h" const uint64_t arch_masks[9] = { 0, 0xff, 0xffff, // 16bit 0, 0xffffffff, // 32bit 0, 0, 0, 0xffffffffffffffffLL // 64bit }; static const x86_reg sib_base_map[] = { X86_REG_INVALID, #define ENTRY(x) X86_REG_##x, ALL_SIB_BASES #undef ENTRY }; // Fill-ins to make the compiler happy. These constants are never actually // assigned; they are just filler to make an automatically-generated switch // statement work. enum { X86_REG_BX_SI = 500, X86_REG_BX_DI = 501, X86_REG_BP_SI = 502, X86_REG_BP_DI = 503, X86_REG_sib = 504, X86_REG_sib64 = 505 }; static const x86_reg sib_index_map[] = { X86_REG_INVALID, #define ENTRY(x) X86_REG_##x, ALL_EA_BASES REGS_XMM REGS_YMM REGS_ZMM #undef ENTRY }; static const x86_reg segment_map[] = { X86_REG_INVALID, X86_REG_CS, X86_REG_SS, X86_REG_DS, X86_REG_ES, X86_REG_FS, X86_REG_GS, }; x86_reg x86_map_sib_base(int r) { return sib_base_map[r]; } x86_reg x86_map_sib_index(int r) { return sib_index_map[r]; } x86_reg x86_map_segment(int r) { return segment_map[r]; } #ifndef CAPSTONE_DIET static const name_map reg_name_maps[] = { { X86_REG_INVALID, NULL }, { X86_REG_AH, "ah" }, { X86_REG_AL, "al" }, { X86_REG_AX, "ax" }, { X86_REG_BH, "bh" }, { X86_REG_BL, "bl" }, { X86_REG_BP, "bp" }, { X86_REG_BPL, "bpl" }, { X86_REG_BX, "bx" }, { X86_REG_CH, "ch" }, { X86_REG_CL, "cl" }, { X86_REG_CS, "cs" }, { X86_REG_CX, "cx" }, { X86_REG_DH, "dh" }, { X86_REG_DI, "di" }, { X86_REG_DIL, "dil" }, { X86_REG_DL, "dl" }, { X86_REG_DS, "ds" }, { X86_REG_DX, "dx" }, { X86_REG_EAX, "eax" }, { X86_REG_EBP, "ebp" }, { X86_REG_EBX, "ebx" }, { X86_REG_ECX, "ecx" }, { X86_REG_EDI, "edi" }, { X86_REG_EDX, "edx" }, { X86_REG_EFLAGS, "flags" }, { X86_REG_EIP, "eip" }, { X86_REG_EIZ, "eiz" }, { X86_REG_ES, "es" }, { X86_REG_ESI, "esi" }, { X86_REG_ESP, "esp" }, { X86_REG_FPSW, "fpsw" }, { X86_REG_FS, "fs" }, { X86_REG_GS, "gs" }, { X86_REG_IP, "ip" }, { X86_REG_RAX, "rax" }, { X86_REG_RBP, "rbp" }, { X86_REG_RBX, "rbx" }, { X86_REG_RCX, "rcx" }, { X86_REG_RDI, "rdi" }, { X86_REG_RDX, "rdx" }, { X86_REG_RIP, "rip" }, { X86_REG_RIZ, "riz" }, { X86_REG_RSI, "rsi" }, { X86_REG_RSP, "rsp" }, { X86_REG_SI, "si" }, { X86_REG_SIL, "sil" }, { X86_REG_SP, "sp" }, { X86_REG_SPL, "spl" }, { X86_REG_SS, "ss" }, { X86_REG_CR0, "cr0" }, { X86_REG_CR1, "cr1" }, { X86_REG_CR2, "cr2" }, { X86_REG_CR3, "cr3" }, { X86_REG_CR4, "cr4" }, { X86_REG_CR5, "cr5" }, { X86_REG_CR6, "cr6" }, { X86_REG_CR7, "cr7" }, { X86_REG_CR8, "cr8" }, { X86_REG_CR9, "cr9" }, { X86_REG_CR10, "cr10" }, { X86_REG_CR11, "cr11" }, { X86_REG_CR12, "cr12" }, { X86_REG_CR13, "cr13" }, { X86_REG_CR14, "cr14" }, { X86_REG_CR15, "cr15" }, { X86_REG_DR0, "dr0" }, { X86_REG_DR1, "dr1" }, { X86_REG_DR2, "dr2" }, { X86_REG_DR3, "dr3" }, { X86_REG_DR4, "dr4" }, { X86_REG_DR5, "dr5" }, { X86_REG_DR6, "dr6" }, { X86_REG_DR7, "dr7" }, { X86_REG_DR8, "dr8" }, { X86_REG_DR9, "dr9" }, { X86_REG_DR10, "dr10" }, { X86_REG_DR11, "dr11" }, { X86_REG_DR12, "dr12" }, { X86_REG_DR13, "dr13" }, { X86_REG_DR14, "dr14" }, { X86_REG_DR15, "dr15" }, { X86_REG_FP0, "fp0" }, { X86_REG_FP1, "fp1" }, { X86_REG_FP2, "fp2" }, { X86_REG_FP3, "fp3" }, { X86_REG_FP4, "fp4" }, { X86_REG_FP5, "fp5" }, { X86_REG_FP6, "fp6" }, { X86_REG_FP7, "fp7" }, { X86_REG_K0, "k0" }, { X86_REG_K1, "k1" }, { X86_REG_K2, "k2" }, { X86_REG_K3, "k3" }, { X86_REG_K4, "k4" }, { X86_REG_K5, "k5" }, { X86_REG_K6, "k6" }, { X86_REG_K7, "k7" }, { X86_REG_MM0, "mm0" }, { X86_REG_MM1, "mm1" }, { X86_REG_MM2, "mm2" }, { X86_REG_MM3, "mm3" }, { X86_REG_MM4, "mm4" }, { X86_REG_MM5, "mm5" }, { X86_REG_MM6, "mm6" }, { X86_REG_MM7, "mm7" }, { X86_REG_R8, "r8" }, { X86_REG_R9, "r9" }, { X86_REG_R10, "r10" }, { X86_REG_R11, "r11" }, { X86_REG_R12, "r12" }, { X86_REG_R13, "r13" }, { X86_REG_R14, "r14" }, { X86_REG_R15, "r15" }, { X86_REG_ST0, "st(0)" }, { X86_REG_ST1, "st(1)" }, { X86_REG_ST2, "st(2)" }, { X86_REG_ST3, "st(3)" }, { X86_REG_ST4, "st(4)" }, { X86_REG_ST5, "st(5)" }, { X86_REG_ST6, "st(6)" }, { X86_REG_ST7, "st(7)" }, { X86_REG_XMM0, "xmm0" }, { X86_REG_XMM1, "xmm1" }, { X86_REG_XMM2, "xmm2" }, { X86_REG_XMM3, "xmm3" }, { X86_REG_XMM4, "xmm4" }, { X86_REG_XMM5, "xmm5" }, { X86_REG_XMM6, "xmm6" }, { X86_REG_XMM7, "xmm7" }, { X86_REG_XMM8, "xmm8" }, { X86_REG_XMM9, "xmm9" }, { X86_REG_XMM10, "xmm10" }, { X86_REG_XMM11, "xmm11" }, { X86_REG_XMM12, "xmm12" }, { X86_REG_XMM13, "xmm13" }, { X86_REG_XMM14, "xmm14" }, { X86_REG_XMM15, "xmm15" }, { X86_REG_XMM16, "xmm16" }, { X86_REG_XMM17, "xmm17" }, { X86_REG_XMM18, "xmm18" }, { X86_REG_XMM19, "xmm19" }, { X86_REG_XMM20, "xmm20" }, { X86_REG_XMM21, "xmm21" }, { X86_REG_XMM22, "xmm22" }, { X86_REG_XMM23, "xmm23" }, { X86_REG_XMM24, "xmm24" }, { X86_REG_XMM25, "xmm25" }, { X86_REG_XMM26, "xmm26" }, { X86_REG_XMM27, "xmm27" }, { X86_REG_XMM28, "xmm28" }, { X86_REG_XMM29, "xmm29" }, { X86_REG_XMM30, "xmm30" }, { X86_REG_XMM31, "xmm31" }, { X86_REG_YMM0, "ymm0" }, { X86_REG_YMM1, "ymm1" }, { X86_REG_YMM2, "ymm2" }, { X86_REG_YMM3, "ymm3" }, { X86_REG_YMM4, "ymm4" }, { X86_REG_YMM5, "ymm5" }, { X86_REG_YMM6, "ymm6" }, { X86_REG_YMM7, "ymm7" }, { X86_REG_YMM8, "ymm8" }, { X86_REG_YMM9, "ymm9" }, { X86_REG_YMM10, "ymm10" }, { X86_REG_YMM11, "ymm11" }, { X86_REG_YMM12, "ymm12" }, { X86_REG_YMM13, "ymm13" }, { X86_REG_YMM14, "ymm14" }, { X86_REG_YMM15, "ymm15" }, { X86_REG_YMM16, "ymm16" }, { X86_REG_YMM17, "ymm17" }, { X86_REG_YMM18, "ymm18" }, { X86_REG_YMM19, "ymm19" }, { X86_REG_YMM20, "ymm20" }, { X86_REG_YMM21, "ymm21" }, { X86_REG_YMM22, "ymm22" }, { X86_REG_YMM23, "ymm23" }, { X86_REG_YMM24, "ymm24" }, { X86_REG_YMM25, "ymm25" }, { X86_REG_YMM26, "ymm26" }, { X86_REG_YMM27, "ymm27" }, { X86_REG_YMM28, "ymm28" }, { X86_REG_YMM29, "ymm29" }, { X86_REG_YMM30, "ymm30" }, { X86_REG_YMM31, "ymm31" }, { X86_REG_ZMM0, "zmm0" }, { X86_REG_ZMM1, "zmm1" }, { X86_REG_ZMM2, "zmm2" }, { X86_REG_ZMM3, "zmm3" }, { X86_REG_ZMM4, "zmm4" }, { X86_REG_ZMM5, "zmm5" }, { X86_REG_ZMM6, "zmm6" }, { X86_REG_ZMM7, "zmm7" }, { X86_REG_ZMM8, "zmm8" }, { X86_REG_ZMM9, "zmm9" }, { X86_REG_ZMM10, "zmm10" }, { X86_REG_ZMM11, "zmm11" }, { X86_REG_ZMM12, "zmm12" }, { X86_REG_ZMM13, "zmm13" }, { X86_REG_ZMM14, "zmm14" }, { X86_REG_ZMM15, "zmm15" }, { X86_REG_ZMM16, "zmm16" }, { X86_REG_ZMM17, "zmm17" }, { X86_REG_ZMM18, "zmm18" }, { X86_REG_ZMM19, "zmm19" }, { X86_REG_ZMM20, "zmm20" }, { X86_REG_ZMM21, "zmm21" }, { X86_REG_ZMM22, "zmm22" }, { X86_REG_ZMM23, "zmm23" }, { X86_REG_ZMM24, "zmm24" }, { X86_REG_ZMM25, "zmm25" }, { X86_REG_ZMM26, "zmm26" }, { X86_REG_ZMM27, "zmm27" }, { X86_REG_ZMM28, "zmm28" }, { X86_REG_ZMM29, "zmm29" }, { X86_REG_ZMM30, "zmm30" }, { X86_REG_ZMM31, "zmm31" }, { X86_REG_R8B, "r8b" }, { X86_REG_R9B, "r9b" }, { X86_REG_R10B, "r10b" }, { X86_REG_R11B, "r11b" }, { X86_REG_R12B, "r12b" }, { X86_REG_R13B, "r13b" }, { X86_REG_R14B, "r14b" }, { X86_REG_R15B, "r15b" }, { X86_REG_R8D, "r8d" }, { X86_REG_R9D, "r9d" }, { X86_REG_R10D, "r10d" }, { X86_REG_R11D, "r11d" }, { X86_REG_R12D, "r12d" }, { X86_REG_R13D, "r13d" }, { X86_REG_R14D, "r14d" }, { X86_REG_R15D, "r15d" }, { X86_REG_R8W, "r8w" }, { X86_REG_R9W, "r9w" }, { X86_REG_R10W, "r10w" }, { X86_REG_R11W, "r11w" }, { X86_REG_R12W, "r12w" }, { X86_REG_R13W, "r13w" }, { X86_REG_R14W, "r14w" }, { X86_REG_R15W, "r15w" }, { X86_REG_BND0, "bnd0" }, { X86_REG_BND1, "bnd1" }, { X86_REG_BND2, "bnd2" }, { X86_REG_BND3, "bnd3" }, }; #endif // register size in non-64bit mode const uint8_t regsize_map_32 [] = { 0, // { X86_REG_INVALID, NULL }, 1, // { X86_REG_AH, "ah" }, 1, // { X86_REG_AL, "al" }, 2, // { X86_REG_AX, "ax" }, 1, // { X86_REG_BH, "bh" }, 1, // { X86_REG_BL, "bl" }, 2, // { X86_REG_BP, "bp" }, 1, // { X86_REG_BPL, "bpl" }, 2, // { X86_REG_BX, "bx" }, 1, // { X86_REG_CH, "ch" }, 1, // { X86_REG_CL, "cl" }, 2, // { X86_REG_CS, "cs" }, 2, // { X86_REG_CX, "cx" }, 1, // { X86_REG_DH, "dh" }, 2, // { X86_REG_DI, "di" }, 1, // { X86_REG_DIL, "dil" }, 1, // { X86_REG_DL, "dl" }, 2, // { X86_REG_DS, "ds" }, 2, // { X86_REG_DX, "dx" }, 4, // { X86_REG_EAX, "eax" }, 4, // { X86_REG_EBP, "ebp" }, 4, // { X86_REG_EBX, "ebx" }, 4, // { X86_REG_ECX, "ecx" }, 4, // { X86_REG_EDI, "edi" }, 4, // { X86_REG_EDX, "edx" }, 4, // { X86_REG_EFLAGS, "flags" }, 4, // { X86_REG_EIP, "eip" }, 4, // { X86_REG_EIZ, "eiz" }, 2, // { X86_REG_ES, "es" }, 4, // { X86_REG_ESI, "esi" }, 4, // { X86_REG_ESP, "esp" }, 10, // { X86_REG_FPSW, "fpsw" }, 2, // { X86_REG_FS, "fs" }, 2, // { X86_REG_GS, "gs" }, 2, // { X86_REG_IP, "ip" }, 8, // { X86_REG_RAX, "rax" }, 8, // { X86_REG_RBP, "rbp" }, 8, // { X86_REG_RBX, "rbx" }, 8, // { X86_REG_RCX, "rcx" }, 8, // { X86_REG_RDI, "rdi" }, 8, // { X86_REG_RDX, "rdx" }, 8, // { X86_REG_RIP, "rip" }, 8, // { X86_REG_RIZ, "riz" }, 8, // { X86_REG_RSI, "rsi" }, 8, // { X86_REG_RSP, "rsp" }, 2, // { X86_REG_SI, "si" }, 1, // { X86_REG_SIL, "sil" }, 2, // { X86_REG_SP, "sp" }, 1, // { X86_REG_SPL, "spl" }, 2, // { X86_REG_SS, "ss" }, 4, // { X86_REG_CR0, "cr0" }, 4, // { X86_REG_CR1, "cr1" }, 4, // { X86_REG_CR2, "cr2" }, 4, // { X86_REG_CR3, "cr3" }, 4, // { X86_REG_CR4, "cr4" }, 8, // { X86_REG_CR5, "cr5" }, 8, // { X86_REG_CR6, "cr6" }, 8, // { X86_REG_CR7, "cr7" }, 8, // { X86_REG_CR8, "cr8" }, 8, // { X86_REG_CR9, "cr9" }, 8, // { X86_REG_CR10, "cr10" }, 8, // { X86_REG_CR11, "cr11" }, 8, // { X86_REG_CR12, "cr12" }, 8, // { X86_REG_CR13, "cr13" }, 8, // { X86_REG_CR14, "cr14" }, 8, // { X86_REG_CR15, "cr15" }, 4, // { X86_REG_DR0, "dr0" }, 4, // { X86_REG_DR1, "dr1" }, 4, // { X86_REG_DR2, "dr2" }, 4, // { X86_REG_DR3, "dr3" }, 4, // { X86_REG_DR4, "dr4" }, 4, // { X86_REG_DR5, "dr5" }, 4, // { X86_REG_DR6, "dr6" }, 4, // { X86_REG_DR7, "dr7" }, 4, // { X86_REG_DR8, "dr8" }, 4, // { X86_REG_DR9, "dr9" }, 4, // { X86_REG_DR10, "dr10" }, 4, // { X86_REG_DR11, "dr11" }, 4, // { X86_REG_DR12, "dr12" }, 4, // { X86_REG_DR13, "dr13" }, 4, // { X86_REG_DR14, "dr14" }, 4, // { X86_REG_DR15, "dr15" }, 10, // { X86_REG_FP0, "fp0" }, 10, // { X86_REG_FP1, "fp1" }, 10, // { X86_REG_FP2, "fp2" }, 10, // { X86_REG_FP3, "fp3" }, 10, // { X86_REG_FP4, "fp4" }, 10, // { X86_REG_FP5, "fp5" }, 10, // { X86_REG_FP6, "fp6" }, 10, // { X86_REG_FP7, "fp7" }, 2, // { X86_REG_K0, "k0" }, 2, // { X86_REG_K1, "k1" }, 2, // { X86_REG_K2, "k2" }, 2, // { X86_REG_K3, "k3" }, 2, // { X86_REG_K4, "k4" }, 2, // { X86_REG_K5, "k5" }, 2, // { X86_REG_K6, "k6" }, 2, // { X86_REG_K7, "k7" }, 8, // { X86_REG_MM0, "mm0" }, 8, // { X86_REG_MM1, "mm1" }, 8, // { X86_REG_MM2, "mm2" }, 8, // { X86_REG_MM3, "mm3" }, 8, // { X86_REG_MM4, "mm4" }, 8, // { X86_REG_MM5, "mm5" }, 8, // { X86_REG_MM6, "mm6" }, 8, // { X86_REG_MM7, "mm7" }, 8, // { X86_REG_R8, "r8" }, 8, // { X86_REG_R9, "r9" }, 8, // { X86_REG_R10, "r10" }, 8, // { X86_REG_R11, "r11" }, 8, // { X86_REG_R12, "r12" }, 8, // { X86_REG_R13, "r13" }, 8, // { X86_REG_R14, "r14" }, 8, // { X86_REG_R15, "r15" }, 10, // { X86_REG_ST0, "st0" }, 10, // { X86_REG_ST1, "st1" }, 10, // { X86_REG_ST2, "st2" }, 10, // { X86_REG_ST3, "st3" }, 10, // { X86_REG_ST4, "st4" }, 10, // { X86_REG_ST5, "st5" }, 10, // { X86_REG_ST6, "st6" }, 10, // { X86_REG_ST7, "st7" }, 16, // { X86_REG_XMM0, "xmm0" }, 16, // { X86_REG_XMM1, "xmm1" }, 16, // { X86_REG_XMM2, "xmm2" }, 16, // { X86_REG_XMM3, "xmm3" }, 16, // { X86_REG_XMM4, "xmm4" }, 16, // { X86_REG_XMM5, "xmm5" }, 16, // { X86_REG_XMM6, "xmm6" }, 16, // { X86_REG_XMM7, "xmm7" }, 16, // { X86_REG_XMM8, "xmm8" }, 16, // { X86_REG_XMM9, "xmm9" }, 16, // { X86_REG_XMM10, "xmm10" }, 16, // { X86_REG_XMM11, "xmm11" }, 16, // { X86_REG_XMM12, "xmm12" }, 16, // { X86_REG_XMM13, "xmm13" }, 16, // { X86_REG_XMM14, "xmm14" }, 16, // { X86_REG_XMM15, "xmm15" }, 16, // { X86_REG_XMM16, "xmm16" }, 16, // { X86_REG_XMM17, "xmm17" }, 16, // { X86_REG_XMM18, "xmm18" }, 16, // { X86_REG_XMM19, "xmm19" }, 16, // { X86_REG_XMM20, "xmm20" }, 16, // { X86_REG_XMM21, "xmm21" }, 16, // { X86_REG_XMM22, "xmm22" }, 16, // { X86_REG_XMM23, "xmm23" }, 16, // { X86_REG_XMM24, "xmm24" }, 16, // { X86_REG_XMM25, "xmm25" }, 16, // { X86_REG_XMM26, "xmm26" }, 16, // { X86_REG_XMM27, "xmm27" }, 16, // { X86_REG_XMM28, "xmm28" }, 16, // { X86_REG_XMM29, "xmm29" }, 16, // { X86_REG_XMM30, "xmm30" }, 16, // { X86_REG_XMM31, "xmm31" }, 32, // { X86_REG_YMM0, "ymm0" }, 32, // { X86_REG_YMM1, "ymm1" }, 32, // { X86_REG_YMM2, "ymm2" }, 32, // { X86_REG_YMM3, "ymm3" }, 32, // { X86_REG_YMM4, "ymm4" }, 32, // { X86_REG_YMM5, "ymm5" }, 32, // { X86_REG_YMM6, "ymm6" }, 32, // { X86_REG_YMM7, "ymm7" }, 32, // { X86_REG_YMM8, "ymm8" }, 32, // { X86_REG_YMM9, "ymm9" }, 32, // { X86_REG_YMM10, "ymm10" }, 32, // { X86_REG_YMM11, "ymm11" }, 32, // { X86_REG_YMM12, "ymm12" }, 32, // { X86_REG_YMM13, "ymm13" }, 32, // { X86_REG_YMM14, "ymm14" }, 32, // { X86_REG_YMM15, "ymm15" }, 32, // { X86_REG_YMM16, "ymm16" }, 32, // { X86_REG_YMM17, "ymm17" }, 32, // { X86_REG_YMM18, "ymm18" }, 32, // { X86_REG_YMM19, "ymm19" }, 32, // { X86_REG_YMM20, "ymm20" }, 32, // { X86_REG_YMM21, "ymm21" }, 32, // { X86_REG_YMM22, "ymm22" }, 32, // { X86_REG_YMM23, "ymm23" }, 32, // { X86_REG_YMM24, "ymm24" }, 32, // { X86_REG_YMM25, "ymm25" }, 32, // { X86_REG_YMM26, "ymm26" }, 32, // { X86_REG_YMM27, "ymm27" }, 32, // { X86_REG_YMM28, "ymm28" }, 32, // { X86_REG_YMM29, "ymm29" }, 32, // { X86_REG_YMM30, "ymm30" }, 32, // { X86_REG_YMM31, "ymm31" }, 64, // { X86_REG_ZMM0, "zmm0" }, 64, // { X86_REG_ZMM1, "zmm1" }, 64, // { X86_REG_ZMM2, "zmm2" }, 64, // { X86_REG_ZMM3, "zmm3" }, 64, // { X86_REG_ZMM4, "zmm4" }, 64, // { X86_REG_ZMM5, "zmm5" }, 64, // { X86_REG_ZMM6, "zmm6" }, 64, // { X86_REG_ZMM7, "zmm7" }, 64, // { X86_REG_ZMM8, "zmm8" }, 64, // { X86_REG_ZMM9, "zmm9" }, 64, // { X86_REG_ZMM10, "zmm10" }, 64, // { X86_REG_ZMM11, "zmm11" }, 64, // { X86_REG_ZMM12, "zmm12" }, 64, // { X86_REG_ZMM13, "zmm13" }, 64, // { X86_REG_ZMM14, "zmm14" }, 64, // { X86_REG_ZMM15, "zmm15" }, 64, // { X86_REG_ZMM16, "zmm16" }, 64, // { X86_REG_ZMM17, "zmm17" }, 64, // { X86_REG_ZMM18, "zmm18" }, 64, // { X86_REG_ZMM19, "zmm19" }, 64, // { X86_REG_ZMM20, "zmm20" }, 64, // { X86_REG_ZMM21, "zmm21" }, 64, // { X86_REG_ZMM22, "zmm22" }, 64, // { X86_REG_ZMM23, "zmm23" }, 64, // { X86_REG_ZMM24, "zmm24" }, 64, // { X86_REG_ZMM25, "zmm25" }, 64, // { X86_REG_ZMM26, "zmm26" }, 64, // { X86_REG_ZMM27, "zmm27" }, 64, // { X86_REG_ZMM28, "zmm28" }, 64, // { X86_REG_ZMM29, "zmm29" }, 64, // { X86_REG_ZMM30, "zmm30" }, 64, // { X86_REG_ZMM31, "zmm31" }, 1, // { X86_REG_R8B, "r8b" }, 1, // { X86_REG_R9B, "r9b" }, 1, // { X86_REG_R10B, "r10b" }, 1, // { X86_REG_R11B, "r11b" }, 1, // { X86_REG_R12B, "r12b" }, 1, // { X86_REG_R13B, "r13b" }, 1, // { X86_REG_R14B, "r14b" }, 1, // { X86_REG_R15B, "r15b" }, 4, // { X86_REG_R8D, "r8d" }, 4, // { X86_REG_R9D, "r9d" }, 4, // { X86_REG_R10D, "r10d" }, 4, // { X86_REG_R11D, "r11d" }, 4, // { X86_REG_R12D, "r12d" }, 4, // { X86_REG_R13D, "r13d" }, 4, // { X86_REG_R14D, "r14d" }, 4, // { X86_REG_R15D, "r15d" }, 2, // { X86_REG_R8W, "r8w" }, 2, // { X86_REG_R9W, "r9w" }, 2, // { X86_REG_R10W, "r10w" }, 2, // { X86_REG_R11W, "r11w" }, 2, // { X86_REG_R12W, "r12w" }, 2, // { X86_REG_R13W, "r13w" }, 2, // { X86_REG_R14W, "r14w" }, 2, // { X86_REG_R15W, "r15w" }, 16, // { X86_REG_BND0, "bnd0" }, 16, // { X86_REG_BND1, "bnd0" }, 16, // { X86_REG_BND2, "bnd0" }, 16, // { X86_REG_BND3, "bnd0" }, }; // register size in 64bit mode const uint8_t regsize_map_64 [] = { 0, // { X86_REG_INVALID, NULL }, 1, // { X86_REG_AH, "ah" }, 1, // { X86_REG_AL, "al" }, 2, // { X86_REG_AX, "ax" }, 1, // { X86_REG_BH, "bh" }, 1, // { X86_REG_BL, "bl" }, 2, // { X86_REG_BP, "bp" }, 1, // { X86_REG_BPL, "bpl" }, 2, // { X86_REG_BX, "bx" }, 1, // { X86_REG_CH, "ch" }, 1, // { X86_REG_CL, "cl" }, 2, // { X86_REG_CS, "cs" }, 2, // { X86_REG_CX, "cx" }, 1, // { X86_REG_DH, "dh" }, 2, // { X86_REG_DI, "di" }, 1, // { X86_REG_DIL, "dil" }, 1, // { X86_REG_DL, "dl" }, 2, // { X86_REG_DS, "ds" }, 2, // { X86_REG_DX, "dx" }, 4, // { X86_REG_EAX, "eax" }, 4, // { X86_REG_EBP, "ebp" }, 4, // { X86_REG_EBX, "ebx" }, 4, // { X86_REG_ECX, "ecx" }, 4, // { X86_REG_EDI, "edi" }, 4, // { X86_REG_EDX, "edx" }, 8, // { X86_REG_EFLAGS, "flags" }, 4, // { X86_REG_EIP, "eip" }, 4, // { X86_REG_EIZ, "eiz" }, 2, // { X86_REG_ES, "es" }, 4, // { X86_REG_ESI, "esi" }, 4, // { X86_REG_ESP, "esp" }, 10, // { X86_REG_FPSW, "fpsw" }, 2, // { X86_REG_FS, "fs" }, 2, // { X86_REG_GS, "gs" }, 2, // { X86_REG_IP, "ip" }, 8, // { X86_REG_RAX, "rax" }, 8, // { X86_REG_RBP, "rbp" }, 8, // { X86_REG_RBX, "rbx" }, 8, // { X86_REG_RCX, "rcx" }, 8, // { X86_REG_RDI, "rdi" }, 8, // { X86_REG_RDX, "rdx" }, 8, // { X86_REG_RIP, "rip" }, 8, // { X86_REG_RIZ, "riz" }, 8, // { X86_REG_RSI, "rsi" }, 8, // { X86_REG_RSP, "rsp" }, 2, // { X86_REG_SI, "si" }, 1, // { X86_REG_SIL, "sil" }, 2, // { X86_REG_SP, "sp" }, 1, // { X86_REG_SPL, "spl" }, 2, // { X86_REG_SS, "ss" }, 8, // { X86_REG_CR0, "cr0" }, 8, // { X86_REG_CR1, "cr1" }, 8, // { X86_REG_CR2, "cr2" }, 8, // { X86_REG_CR3, "cr3" }, 8, // { X86_REG_CR4, "cr4" }, 8, // { X86_REG_CR5, "cr5" }, 8, // { X86_REG_CR6, "cr6" }, 8, // { X86_REG_CR7, "cr7" }, 8, // { X86_REG_CR8, "cr8" }, 8, // { X86_REG_CR9, "cr9" }, 8, // { X86_REG_CR10, "cr10" }, 8, // { X86_REG_CR11, "cr11" }, 8, // { X86_REG_CR12, "cr12" }, 8, // { X86_REG_CR13, "cr13" }, 8, // { X86_REG_CR14, "cr14" }, 8, // { X86_REG_CR15, "cr15" }, 8, // { X86_REG_DR0, "dr0" }, 8, // { X86_REG_DR1, "dr1" }, 8, // { X86_REG_DR2, "dr2" }, 8, // { X86_REG_DR3, "dr3" }, 8, // { X86_REG_DR4, "dr4" }, 8, // { X86_REG_DR5, "dr5" }, 8, // { X86_REG_DR6, "dr6" }, 8, // { X86_REG_DR7, "dr7" }, 8, // { X86_REG_DR8, "dr8" }, 8, // { X86_REG_DR9, "dr9" }, 8, // { X86_REG_DR10, "dr10" }, 8, // { X86_REG_DR11, "dr11" }, 8, // { X86_REG_DR12, "dr12" }, 8, // { X86_REG_DR13, "dr13" }, 8, // { X86_REG_DR14, "dr14" }, 8, // { X86_REG_DR15, "dr15" }, 10, // { X86_REG_FP0, "fp0" }, 10, // { X86_REG_FP1, "fp1" }, 10, // { X86_REG_FP2, "fp2" }, 10, // { X86_REG_FP3, "fp3" }, 10, // { X86_REG_FP4, "fp4" }, 10, // { X86_REG_FP5, "fp5" }, 10, // { X86_REG_FP6, "fp6" }, 10, // { X86_REG_FP7, "fp7" }, 2, // { X86_REG_K0, "k0" }, 2, // { X86_REG_K1, "k1" }, 2, // { X86_REG_K2, "k2" }, 2, // { X86_REG_K3, "k3" }, 2, // { X86_REG_K4, "k4" }, 2, // { X86_REG_K5, "k5" }, 2, // { X86_REG_K6, "k6" }, 2, // { X86_REG_K7, "k7" }, 8, // { X86_REG_MM0, "mm0" }, 8, // { X86_REG_MM1, "mm1" }, 8, // { X86_REG_MM2, "mm2" }, 8, // { X86_REG_MM3, "mm3" }, 8, // { X86_REG_MM4, "mm4" }, 8, // { X86_REG_MM5, "mm5" }, 8, // { X86_REG_MM6, "mm6" }, 8, // { X86_REG_MM7, "mm7" }, 8, // { X86_REG_R8, "r8" }, 8, // { X86_REG_R9, "r9" }, 8, // { X86_REG_R10, "r10" }, 8, // { X86_REG_R11, "r11" }, 8, // { X86_REG_R12, "r12" }, 8, // { X86_REG_R13, "r13" }, 8, // { X86_REG_R14, "r14" }, 8, // { X86_REG_R15, "r15" }, 10, // { X86_REG_ST0, "st0" }, 10, // { X86_REG_ST1, "st1" }, 10, // { X86_REG_ST2, "st2" }, 10, // { X86_REG_ST3, "st3" }, 10, // { X86_REG_ST4, "st4" }, 10, // { X86_REG_ST5, "st5" }, 10, // { X86_REG_ST6, "st6" }, 10, // { X86_REG_ST7, "st7" }, 16, // { X86_REG_XMM0, "xmm0" }, 16, // { X86_REG_XMM1, "xmm1" }, 16, // { X86_REG_XMM2, "xmm2" }, 16, // { X86_REG_XMM3, "xmm3" }, 16, // { X86_REG_XMM4, "xmm4" }, 16, // { X86_REG_XMM5, "xmm5" }, 16, // { X86_REG_XMM6, "xmm6" }, 16, // { X86_REG_XMM7, "xmm7" }, 16, // { X86_REG_XMM8, "xmm8" }, 16, // { X86_REG_XMM9, "xmm9" }, 16, // { X86_REG_XMM10, "xmm10" }, 16, // { X86_REG_XMM11, "xmm11" }, 16, // { X86_REG_XMM12, "xmm12" }, 16, // { X86_REG_XMM13, "xmm13" }, 16, // { X86_REG_XMM14, "xmm14" }, 16, // { X86_REG_XMM15, "xmm15" }, 16, // { X86_REG_XMM16, "xmm16" }, 16, // { X86_REG_XMM17, "xmm17" }, 16, // { X86_REG_XMM18, "xmm18" }, 16, // { X86_REG_XMM19, "xmm19" }, 16, // { X86_REG_XMM20, "xmm20" }, 16, // { X86_REG_XMM21, "xmm21" }, 16, // { X86_REG_XMM22, "xmm22" }, 16, // { X86_REG_XMM23, "xmm23" }, 16, // { X86_REG_XMM24, "xmm24" }, 16, // { X86_REG_XMM25, "xmm25" }, 16, // { X86_REG_XMM26, "xmm26" }, 16, // { X86_REG_XMM27, "xmm27" }, 16, // { X86_REG_XMM28, "xmm28" }, 16, // { X86_REG_XMM29, "xmm29" }, 16, // { X86_REG_XMM30, "xmm30" }, 16, // { X86_REG_XMM31, "xmm31" }, 32, // { X86_REG_YMM0, "ymm0" }, 32, // { X86_REG_YMM1, "ymm1" }, 32, // { X86_REG_YMM2, "ymm2" }, 32, // { X86_REG_YMM3, "ymm3" }, 32, // { X86_REG_YMM4, "ymm4" }, 32, // { X86_REG_YMM5, "ymm5" }, 32, // { X86_REG_YMM6, "ymm6" }, 32, // { X86_REG_YMM7, "ymm7" }, 32, // { X86_REG_YMM8, "ymm8" }, 32, // { X86_REG_YMM9, "ymm9" }, 32, // { X86_REG_YMM10, "ymm10" }, 32, // { X86_REG_YMM11, "ymm11" }, 32, // { X86_REG_YMM12, "ymm12" }, 32, // { X86_REG_YMM13, "ymm13" }, 32, // { X86_REG_YMM14, "ymm14" }, 32, // { X86_REG_YMM15, "ymm15" }, 32, // { X86_REG_YMM16, "ymm16" }, 32, // { X86_REG_YMM17, "ymm17" }, 32, // { X86_REG_YMM18, "ymm18" }, 32, // { X86_REG_YMM19, "ymm19" }, 32, // { X86_REG_YMM20, "ymm20" }, 32, // { X86_REG_YMM21, "ymm21" }, 32, // { X86_REG_YMM22, "ymm22" }, 32, // { X86_REG_YMM23, "ymm23" }, 32, // { X86_REG_YMM24, "ymm24" }, 32, // { X86_REG_YMM25, "ymm25" }, 32, // { X86_REG_YMM26, "ymm26" }, 32, // { X86_REG_YMM27, "ymm27" }, 32, // { X86_REG_YMM28, "ymm28" }, 32, // { X86_REG_YMM29, "ymm29" }, 32, // { X86_REG_YMM30, "ymm30" }, 32, // { X86_REG_YMM31, "ymm31" }, 64, // { X86_REG_ZMM0, "zmm0" }, 64, // { X86_REG_ZMM1, "zmm1" }, 64, // { X86_REG_ZMM2, "zmm2" }, 64, // { X86_REG_ZMM3, "zmm3" }, 64, // { X86_REG_ZMM4, "zmm4" }, 64, // { X86_REG_ZMM5, "zmm5" }, 64, // { X86_REG_ZMM6, "zmm6" }, 64, // { X86_REG_ZMM7, "zmm7" }, 64, // { X86_REG_ZMM8, "zmm8" }, 64, // { X86_REG_ZMM9, "zmm9" }, 64, // { X86_REG_ZMM10, "zmm10" }, 64, // { X86_REG_ZMM11, "zmm11" }, 64, // { X86_REG_ZMM12, "zmm12" }, 64, // { X86_REG_ZMM13, "zmm13" }, 64, // { X86_REG_ZMM14, "zmm14" }, 64, // { X86_REG_ZMM15, "zmm15" }, 64, // { X86_REG_ZMM16, "zmm16" }, 64, // { X86_REG_ZMM17, "zmm17" }, 64, // { X86_REG_ZMM18, "zmm18" }, 64, // { X86_REG_ZMM19, "zmm19" }, 64, // { X86_REG_ZMM20, "zmm20" }, 64, // { X86_REG_ZMM21, "zmm21" }, 64, // { X86_REG_ZMM22, "zmm22" }, 64, // { X86_REG_ZMM23, "zmm23" }, 64, // { X86_REG_ZMM24, "zmm24" }, 64, // { X86_REG_ZMM25, "zmm25" }, 64, // { X86_REG_ZMM26, "zmm26" }, 64, // { X86_REG_ZMM27, "zmm27" }, 64, // { X86_REG_ZMM28, "zmm28" }, 64, // { X86_REG_ZMM29, "zmm29" }, 64, // { X86_REG_ZMM30, "zmm30" }, 64, // { X86_REG_ZMM31, "zmm31" }, 1, // { X86_REG_R8B, "r8b" }, 1, // { X86_REG_R9B, "r9b" }, 1, // { X86_REG_R10B, "r10b" }, 1, // { X86_REG_R11B, "r11b" }, 1, // { X86_REG_R12B, "r12b" }, 1, // { X86_REG_R13B, "r13b" }, 1, // { X86_REG_R14B, "r14b" }, 1, // { X86_REG_R15B, "r15b" }, 4, // { X86_REG_R8D, "r8d" }, 4, // { X86_REG_R9D, "r9d" }, 4, // { X86_REG_R10D, "r10d" }, 4, // { X86_REG_R11D, "r11d" }, 4, // { X86_REG_R12D, "r12d" }, 4, // { X86_REG_R13D, "r13d" }, 4, // { X86_REG_R14D, "r14d" }, 4, // { X86_REG_R15D, "r15d" }, 2, // { X86_REG_R8W, "r8w" }, 2, // { X86_REG_R9W, "r9w" }, 2, // { X86_REG_R10W, "r10w" }, 2, // { X86_REG_R11W, "r11w" }, 2, // { X86_REG_R12W, "r12w" }, 2, // { X86_REG_R13W, "r13w" }, 2, // { X86_REG_R14W, "r14w" }, 2, // { X86_REG_R15W, "r15w" }, 16, // { X86_REG_BND0, "bnd0" }, 16, // { X86_REG_BND1, "bnd0" }, 16, // { X86_REG_BND2, "bnd0" }, 16, // { X86_REG_BND3, "bnd0" }, }; const char *X86_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET cs_struct *ud = (cs_struct *)handle; if (reg >= ARR_SIZE(reg_name_maps)) return NULL; if (reg == X86_REG_EFLAGS) { if (ud->mode & CS_MODE_32) return "eflags"; if (ud->mode & CS_MODE_64) return "rflags"; } return reg_name_maps[reg].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const char * const insn_name_maps[] = { NULL, // X86_INS_INVALID #ifndef CAPSTONE_X86_REDUCE #include "X86MappingInsnName.inc" #else #include "X86MappingInsnName_reduce.inc" #endif }; #endif // NOTE: insn_name_maps[] is sorted in order const char *X86_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET if (id >= ARR_SIZE(insn_name_maps)) return NULL; return insn_name_maps[id]; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { // generic groups { X86_GRP_INVALID, NULL }, { X86_GRP_JUMP, "jump" }, { X86_GRP_CALL, "call" }, { X86_GRP_RET, "ret" }, { X86_GRP_INT, "int" }, { X86_GRP_IRET, "iret" }, { X86_GRP_PRIVILEGE, "privilege" }, { X86_GRP_BRANCH_RELATIVE, "branch_relative" }, // architecture-specific groups { X86_GRP_VM, "vm" }, { X86_GRP_3DNOW, "3dnow" }, { X86_GRP_AES, "aes" }, { X86_GRP_ADX, "adx" }, { X86_GRP_AVX, "avx" }, { X86_GRP_AVX2, "avx2" }, { X86_GRP_AVX512, "avx512" }, { X86_GRP_BMI, "bmi" }, { X86_GRP_BMI2, "bmi2" }, { X86_GRP_CMOV, "cmov" }, { X86_GRP_F16C, "fc16" }, { X86_GRP_FMA, "fma" }, { X86_GRP_FMA4, "fma4" }, { X86_GRP_FSGSBASE, "fsgsbase" }, { X86_GRP_HLE, "hle" }, { X86_GRP_MMX, "mmx" }, { X86_GRP_MODE32, "mode32" }, { X86_GRP_MODE64, "mode64" }, { X86_GRP_RTM, "rtm" }, { X86_GRP_SHA, "sha" }, { X86_GRP_SSE1, "sse1" }, { X86_GRP_SSE2, "sse2" }, { X86_GRP_SSE3, "sse3" }, { X86_GRP_SSE41, "sse41" }, { X86_GRP_SSE42, "sse42" }, { X86_GRP_SSE4A, "sse4a" }, { X86_GRP_SSSE3, "ssse3" }, { X86_GRP_PCLMUL, "pclmul" }, { X86_GRP_XOP, "xop" }, { X86_GRP_CDI, "cdi" }, { X86_GRP_ERI, "eri" }, { X86_GRP_TBM, "tbm" }, { X86_GRP_16BITMODE, "16bitmode" }, { X86_GRP_NOT64BITMODE, "not64bitmode" }, { X86_GRP_SGX, "sgx" }, { X86_GRP_DQI, "dqi" }, { X86_GRP_BWI, "bwi" }, { X86_GRP_PFI, "pfi" }, { X86_GRP_VLX, "vlx" }, { X86_GRP_SMAP, "smap" }, { X86_GRP_NOVLX, "novlx" }, { X86_GRP_FPU, "fpu" }, }; #endif const char *X86_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } #define GET_INSTRINFO_ENUM #ifdef CAPSTONE_X86_REDUCE #include "X86GenInstrInfo_reduce.inc" const insn_map_x86 insns[] = { // reduce x86 instructions #include "X86MappingInsn_reduce.inc" }; #else #include "X86GenInstrInfo.inc" const insn_map_x86 insns[] = { // full x86 instructions #include "X86MappingInsn.inc" }; #endif #ifndef CAPSTONE_DIET // in arr, replace r1 = r2 static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2) { uint8_t i; for(i = 0; i < max; i++) { if (arr[i] == r1) { arr[i] = r2; break; } } } #endif // look for @id in @insns // return -1 if not found unsigned int find_insn(unsigned int id) { // binary searching since the IDs are sorted in order unsigned int left, right, m; unsigned int max = ARR_SIZE(insns); right = max - 1; if (id < insns[0].id || id > insns[right].id) // not found return -1; left = 0; while(left <= right) { m = (left + right) / 2; if (id == insns[m].id) { return m; } if (id < insns[m].id) right = m - 1; else left = m + 1; } // not found // printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id); return -1; } // given internal insn id, return public instruction info void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned int i = find_insn(id); if (i != -1) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); // special cases when regs_write[] depends on arch switch(id) { default: memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); break; case X86_RDTSC: if (h->mode == CS_MODE_64) { memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); } else { insn->detail->regs_write[0] = X86_REG_EAX; insn->detail->regs_write[1] = X86_REG_EDX; insn->detail->regs_write_count = 2; } break; case X86_RDTSCP: if (h->mode == CS_MODE_64) { memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); } else { insn->detail->regs_write[0] = X86_REG_EAX; insn->detail->regs_write[1] = X86_REG_ECX; insn->detail->regs_write[2] = X86_REG_EDX; insn->detail->regs_write_count = 3; } break; } switch(insn->id) { default: break; case X86_INS_LOOP: case X86_INS_LOOPE: case X86_INS_LOOPNE: switch(h->mode) { default: break; case CS_MODE_16: insn->detail->regs_read[0] = X86_REG_CX; insn->detail->regs_read_count = 1; insn->detail->regs_write[0] = X86_REG_CX; insn->detail->regs_write_count = 1; break; case CS_MODE_32: insn->detail->regs_read[0] = X86_REG_ECX; insn->detail->regs_read_count = 1; insn->detail->regs_write[0] = X86_REG_ECX; insn->detail->regs_write_count = 1; break; case CS_MODE_64: insn->detail->regs_read[0] = X86_REG_RCX; insn->detail->regs_read_count = 1; insn->detail->regs_write[0] = X86_REG_RCX; insn->detail->regs_write_count = 1; break; } // LOOPE & LOOPNE also read EFLAGS if (insn->id != X86_INS_LOOP) { insn->detail->regs_read[1] = X86_REG_EFLAGS; insn->detail->regs_read_count = 2; } break; case X86_INS_LODSB: case X86_INS_LODSD: case X86_INS_LODSQ: case X86_INS_LODSW: switch(h->mode) { default: break; case CS_MODE_16: arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI); break; case CS_MODE_64: arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI); break; } break; case X86_INS_SCASB: case X86_INS_SCASW: case X86_INS_SCASQ: case X86_INS_STOSB: case X86_INS_STOSD: case X86_INS_STOSQ: case X86_INS_STOSW: switch(h->mode) { default: break; case CS_MODE_16: arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI); break; case CS_MODE_64: arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI); break; } break; case X86_INS_CMPSB: case X86_INS_CMPSD: case X86_INS_CMPSQ: case X86_INS_CMPSW: case X86_INS_MOVSB: case X86_INS_MOVSW: case X86_INS_MOVSD: case X86_INS_MOVSQ: switch(h->mode) { default: break; case CS_MODE_16: arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI); arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI); break; case CS_MODE_64: arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI); arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI); arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI); break; } break; case X86_INS_RET: switch(h->mode) { case CS_MODE_16: insn->detail->regs_write[0] = X86_REG_SP; insn->detail->regs_read[0] = X86_REG_SP; break; case CS_MODE_32: insn->detail->regs_write[0] = X86_REG_ESP; insn->detail->regs_read[0] = X86_REG_ESP; break; default: // 64-bit insn->detail->regs_write[0] = X86_REG_RSP; insn->detail->regs_read[0] = X86_REG_RSP; break; } insn->detail->regs_write_count = 1; insn->detail->regs_read_count = 1; break; } memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = X86_GRP_JUMP; insn->detail->groups_count++; } switch (insns[i].id) { case X86_OUT8ir: case X86_OUT16ir: case X86_OUT32ir: if (insn->detail->x86.operands[0].imm == -78) { // Writing to port 0xb2 causes an SMI on most platforms // See: http://cs.gmu.edu/~tr-admin/papers/GMU-CS-TR-2011-8.pdf insn->detail->groups[insn->detail->groups_count] = X86_GRP_INT; insn->detail->groups_count++; } break; default: break; } #endif } } } // map special instructions with accumulate registers. // this is needed because LLVM embeds these register names into AsmStrs[], // but not separately in operands struct insn_reg { uint16_t insn; x86_reg reg; enum cs_ac_type access; }; struct insn_reg2 { uint16_t insn; x86_reg reg1, reg2; enum cs_ac_type access1, access2; }; static const struct insn_reg insn_regs_att[] = { { X86_INSB, X86_REG_DX, CS_AC_READ }, { X86_INSL, X86_REG_DX, CS_AC_READ }, { X86_INSW, X86_REG_DX, CS_AC_READ }, { X86_MOV16o16a, X86_REG_AX, CS_AC_READ }, { X86_MOV16o32a, X86_REG_AX, CS_AC_READ }, { X86_MOV16o64a, X86_REG_AX, CS_AC_READ }, { X86_MOV32o16a, X86_REG_EAX, CS_AC_READ }, { X86_MOV32o32a, X86_REG_EAX, CS_AC_READ }, { X86_MOV32o64a, X86_REG_EAX, CS_AC_READ }, { X86_MOV64o32a, X86_REG_RAX, CS_AC_READ }, { X86_MOV64o64a, X86_REG_RAX, CS_AC_READ }, { X86_MOV8o16a, X86_REG_AL, CS_AC_READ }, { X86_MOV8o32a, X86_REG_AL, CS_AC_READ }, { X86_MOV8o64a, X86_REG_AL, CS_AC_READ }, { X86_OUT16ir, X86_REG_AX, CS_AC_READ }, { X86_OUT32ir, X86_REG_EAX, CS_AC_READ }, { X86_OUT8ir, X86_REG_AL, CS_AC_READ }, { X86_POPDS16, X86_REG_DS, CS_AC_WRITE }, { X86_POPDS32, X86_REG_DS, CS_AC_WRITE }, { X86_POPES16, X86_REG_ES, CS_AC_WRITE }, { X86_POPES32, X86_REG_ES, CS_AC_WRITE }, { X86_POPFS16, X86_REG_FS, CS_AC_WRITE }, { X86_POPFS32, X86_REG_FS, CS_AC_WRITE }, { X86_POPFS64, X86_REG_FS, CS_AC_WRITE }, { X86_POPGS16, X86_REG_GS, CS_AC_WRITE }, { X86_POPGS32, X86_REG_GS, CS_AC_WRITE }, { X86_POPGS64, X86_REG_GS, CS_AC_WRITE }, { X86_POPSS16, X86_REG_SS, CS_AC_WRITE }, { X86_POPSS32, X86_REG_SS, CS_AC_WRITE }, { X86_PUSHCS16, X86_REG_CS, CS_AC_READ }, { X86_PUSHCS32, X86_REG_CS, CS_AC_READ }, { X86_PUSHDS16, X86_REG_DS, CS_AC_READ }, { X86_PUSHDS32, X86_REG_DS, CS_AC_READ }, { X86_PUSHES16, X86_REG_ES, CS_AC_READ }, { X86_PUSHES32, X86_REG_ES, CS_AC_READ }, { X86_PUSHFS16, X86_REG_FS, CS_AC_READ }, { X86_PUSHFS32, X86_REG_FS, CS_AC_READ }, { X86_PUSHFS64, X86_REG_FS, CS_AC_READ }, { X86_PUSHGS16, X86_REG_GS, CS_AC_READ }, { X86_PUSHGS32, X86_REG_GS, CS_AC_READ }, { X86_PUSHGS64, X86_REG_GS, CS_AC_READ }, { X86_PUSHSS16, X86_REG_SS, CS_AC_READ }, { X86_PUSHSS32, X86_REG_SS, CS_AC_READ }, { X86_RCL16rCL, X86_REG_CL, CS_AC_READ }, { X86_RCL32rCL, X86_REG_CL, CS_AC_READ }, { X86_RCL64rCL, X86_REG_CL, CS_AC_READ }, { X86_RCL8rCL, X86_REG_CL, CS_AC_READ }, { X86_RCR16rCL, X86_REG_CL, CS_AC_READ }, { X86_RCR32rCL, X86_REG_CL, CS_AC_READ }, { X86_RCR64rCL, X86_REG_CL, CS_AC_READ }, { X86_RCR8rCL, X86_REG_CL, CS_AC_READ }, { X86_ROL16rCL, X86_REG_CL, CS_AC_READ }, { X86_ROL32rCL, X86_REG_CL, CS_AC_READ }, { X86_ROL64rCL, X86_REG_CL, CS_AC_READ }, { X86_ROL8rCL, X86_REG_CL, CS_AC_READ }, { X86_ROR16rCL, X86_REG_CL, CS_AC_READ }, { X86_ROR32rCL, X86_REG_CL, CS_AC_READ }, { X86_ROR64rCL, X86_REG_CL, CS_AC_READ }, { X86_ROR8rCL, X86_REG_CL, CS_AC_READ }, { X86_SAL16rCL, X86_REG_CL, CS_AC_READ }, { X86_SAL32rCL, X86_REG_CL, CS_AC_READ }, { X86_SAL64rCL, X86_REG_CL, CS_AC_READ }, { X86_SAL8rCL, X86_REG_CL, CS_AC_READ }, { X86_SAR16rCL, X86_REG_CL, CS_AC_READ }, { X86_SAR32rCL, X86_REG_CL, CS_AC_READ }, { X86_SAR64rCL, X86_REG_CL, CS_AC_READ }, { X86_SAR8rCL, X86_REG_CL, CS_AC_READ }, { X86_SHL16rCL, X86_REG_CL, CS_AC_READ }, { X86_SHL32rCL, X86_REG_CL, CS_AC_READ }, { X86_SHL64rCL, X86_REG_CL, CS_AC_READ }, { X86_SHL8rCL, X86_REG_CL, CS_AC_READ }, { X86_SHLD16mrCL, X86_REG_CL, CS_AC_READ }, { X86_SHLD16rrCL, X86_REG_CL, CS_AC_READ }, { X86_SHLD32mrCL, X86_REG_CL, CS_AC_READ }, { X86_SHLD32rrCL, X86_REG_CL, CS_AC_READ }, { X86_SHLD64mrCL, X86_REG_CL, CS_AC_READ }, { X86_SHLD64rrCL, X86_REG_CL, CS_AC_READ }, { X86_SHR16rCL, X86_REG_CL, CS_AC_READ }, { X86_SHR32rCL, X86_REG_CL, CS_AC_READ }, { X86_SHR64rCL, X86_REG_CL, CS_AC_READ }, { X86_SHR8rCL, X86_REG_CL, CS_AC_READ }, { X86_SHRD16mrCL, X86_REG_CL, CS_AC_READ }, { X86_SHRD16rrCL, X86_REG_CL, CS_AC_READ }, { X86_SHRD32mrCL, X86_REG_CL, CS_AC_READ }, { X86_SHRD32rrCL, X86_REG_CL, CS_AC_READ }, { X86_SHRD64mrCL, X86_REG_CL, CS_AC_READ }, { X86_SHRD64rrCL, X86_REG_CL, CS_AC_READ }, { X86_XCHG16ar, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_XCHG32ar, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_XCHG64ar, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, }; static const struct insn_reg insn_regs_att_extra[] = { // dummy entry, to avoid empty array { 0, 0 }, #ifndef CAPSTONE_X86_REDUCE { X86_ADD_FrST0, X86_REG_ST0, CS_AC_READ }, { X86_DIVR_FrST0, X86_REG_ST0, CS_AC_READ }, { X86_DIV_FrST0, X86_REG_ST0, CS_AC_READ }, { X86_FNSTSW16r, X86_REG_AX, CS_AC_READ }, { X86_MUL_FrST0, X86_REG_ST0, CS_AC_READ }, { X86_SKINIT, X86_REG_EAX, CS_AC_READ }, { X86_SUBR_FrST0, X86_REG_ST0, CS_AC_READ }, { X86_SUB_FrST0, X86_REG_ST0, CS_AC_READ }, { X86_VMLOAD32, X86_REG_EAX, CS_AC_READ }, { X86_VMLOAD64, X86_REG_RAX, CS_AC_READ }, { X86_VMRUN32, X86_REG_EAX, CS_AC_READ }, { X86_VMRUN64, X86_REG_RAX, CS_AC_READ }, { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ }, { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ }, #endif }; static const struct insn_reg insn_regs_intel[] = { { X86_ADC16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_ADC32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_ADC64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_ADC8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_ADD16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_ADD32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_ADD64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_ADD8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_AND16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_AND32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_AND64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_AND8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_CMP16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_CMP32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_CMP64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_CMP8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_IN16ri, X86_REG_AX, CS_AC_WRITE }, { X86_IN32ri, X86_REG_EAX, CS_AC_WRITE }, { X86_IN8ri, X86_REG_AL, CS_AC_WRITE }, { X86_LODSB, X86_REG_AL, CS_AC_WRITE }, { X86_LODSL, X86_REG_EAX, CS_AC_WRITE }, { X86_LODSQ, X86_REG_RAX, CS_AC_WRITE }, { X86_LODSW, X86_REG_AX, CS_AC_WRITE }, { X86_MOV16ao16, X86_REG_AX, CS_AC_WRITE }, // 16-bit A1 1020 // mov ax, word ptr [0x2010] { X86_MOV16ao32, X86_REG_AX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov ax, word ptr [0x40302010] { X86_MOV16ao64, X86_REG_AX, CS_AC_WRITE }, // 64-bit 66 A1 1020304050607080 // movabs ax, word ptr [0x8070605040302010] { X86_MOV32ao16, X86_REG_EAX, CS_AC_WRITE }, // 32-bit 67 A1 1020 // mov eax, dword ptr [0x2010] { X86_MOV32ao32, X86_REG_EAX, CS_AC_WRITE }, // 32-bit A1 10203040 // mov eax, dword ptr [0x40302010] { X86_MOV32ao64, X86_REG_EAX, CS_AC_WRITE }, // 64-bit A1 1020304050607080 // movabs eax, dword ptr [0x8070605040302010] { X86_MOV64ao32, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 8B04 10203040 // mov rax, qword ptr [0x40302010] { X86_MOV64ao64, X86_REG_RAX, CS_AC_WRITE }, // 64-bit 48 A1 1020304050607080 // movabs rax, qword ptr [0x8070605040302010] { X86_MOV8ao16, X86_REG_AL, CS_AC_WRITE }, // 16-bit A0 1020 // mov al, byte ptr [0x2010] { X86_MOV8ao32, X86_REG_AL, CS_AC_WRITE }, // 32-bit A0 10203040 // mov al, byte ptr [0x40302010] { X86_MOV8ao64, X86_REG_AL, CS_AC_WRITE }, // 64-bit 66 A0 1020304050607080 // movabs al, byte ptr [0x8070605040302010] { X86_OR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_OR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_OR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_OR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_OUTSB, X86_REG_DX, CS_AC_WRITE }, { X86_OUTSL, X86_REG_DX, CS_AC_WRITE }, { X86_OUTSW, X86_REG_DX, CS_AC_WRITE }, { X86_POPDS16, X86_REG_DS, CS_AC_WRITE }, { X86_POPDS32, X86_REG_DS, CS_AC_WRITE }, { X86_POPES16, X86_REG_ES, CS_AC_WRITE }, { X86_POPES32, X86_REG_ES, CS_AC_WRITE }, { X86_POPFS16, X86_REG_FS, CS_AC_WRITE }, { X86_POPFS32, X86_REG_FS, CS_AC_WRITE }, { X86_POPFS64, X86_REG_FS, CS_AC_WRITE }, { X86_POPGS16, X86_REG_GS, CS_AC_WRITE }, { X86_POPGS32, X86_REG_GS, CS_AC_WRITE }, { X86_POPGS64, X86_REG_GS, CS_AC_WRITE }, { X86_POPSS16, X86_REG_SS, CS_AC_WRITE }, { X86_POPSS32, X86_REG_SS, CS_AC_WRITE }, { X86_PUSHCS16, X86_REG_CS, CS_AC_READ }, { X86_PUSHCS32, X86_REG_CS, CS_AC_READ }, { X86_PUSHDS16, X86_REG_DS, CS_AC_READ }, { X86_PUSHDS32, X86_REG_DS, CS_AC_READ }, { X86_PUSHES16, X86_REG_ES, CS_AC_READ }, { X86_PUSHES32, X86_REG_ES, CS_AC_READ }, { X86_PUSHFS16, X86_REG_FS, CS_AC_READ }, { X86_PUSHFS32, X86_REG_FS, CS_AC_READ }, { X86_PUSHFS64, X86_REG_FS, CS_AC_READ }, { X86_PUSHGS16, X86_REG_GS, CS_AC_READ }, { X86_PUSHGS32, X86_REG_GS, CS_AC_READ }, { X86_PUSHGS64, X86_REG_GS, CS_AC_READ }, { X86_PUSHSS16, X86_REG_SS, CS_AC_READ }, { X86_PUSHSS32, X86_REG_SS, CS_AC_READ }, { X86_SBB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_SBB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_SBB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_SBB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_SCASB, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_SCASL, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_SCASQ, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_SCASW, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_SUB16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_SUB32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_SUB64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_SUB8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_TEST16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_TEST32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_TEST64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_TEST8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, { X86_XOR16i16, X86_REG_AX, CS_AC_WRITE | CS_AC_READ }, { X86_XOR32i32, X86_REG_EAX, CS_AC_WRITE | CS_AC_READ }, { X86_XOR64i32, X86_REG_RAX, CS_AC_WRITE | CS_AC_READ }, { X86_XOR8i8, X86_REG_AL, CS_AC_WRITE | CS_AC_READ }, }; static const struct insn_reg insn_regs_intel_extra[] = { // dummy entry, to avoid empty array { 0, 0, 0 }, #ifndef CAPSTONE_X86_REDUCE { X86_CMOVBE_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVB_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVE_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVNBE_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVNB_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVNE_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVNP_F, X86_REG_ST0, CS_AC_WRITE }, { X86_CMOVP_F, X86_REG_ST0, CS_AC_WRITE }, // { X86_COMP_FST0r, X86_REG_ST0, CS_AC_WRITE }, // { X86_COM_FST0r, X86_REG_ST0, CS_AC_WRITE }, { X86_FNSTSW16r, X86_REG_AX, CS_AC_WRITE }, { X86_SKINIT, X86_REG_EAX, CS_AC_WRITE }, { X86_VMLOAD32, X86_REG_EAX, CS_AC_WRITE }, { X86_VMLOAD64, X86_REG_RAX, CS_AC_WRITE }, { X86_VMRUN32, X86_REG_EAX, CS_AC_WRITE }, { X86_VMRUN64, X86_REG_RAX, CS_AC_WRITE }, { X86_VMSAVE32, X86_REG_EAX, CS_AC_READ }, { X86_VMSAVE64, X86_REG_RAX, CS_AC_READ }, { X86_XCH_F, X86_REG_ST0, CS_AC_WRITE }, #endif }; static const struct insn_reg2 insn_regs_intel2[] = { { X86_IN16rr, X86_REG_AX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, { X86_IN32rr, X86_REG_EAX, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, { X86_IN8rr, X86_REG_AL, X86_REG_DX, CS_AC_WRITE, CS_AC_READ }, { X86_INVLPGA32, X86_REG_EAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ }, { X86_INVLPGA64, X86_REG_RAX, X86_REG_ECX, CS_AC_READ, CS_AC_READ }, { X86_OUT16rr, X86_REG_DX, X86_REG_AX, CS_AC_READ, CS_AC_READ }, { X86_OUT32rr, X86_REG_DX, X86_REG_EAX, CS_AC_READ, CS_AC_READ }, { X86_OUT8rr, X86_REG_DX, X86_REG_AL, CS_AC_READ, CS_AC_READ }, }; static int binary_search1(const struct insn_reg *insns, unsigned int max, unsigned int id) { unsigned int first, last, mid; first = 0; last = max -1; if (insns[0].insn > id || insns[last].insn < id) { // not found return -1; } while (first <= last) { mid = (first + last) / 2; if (insns[mid].insn < id) { first = mid + 1; } else if (insns[mid].insn == id) { return mid; } else { if (mid == 0) break; last = mid - 1; } } // not found return -1; } static int binary_search2(const struct insn_reg2 *insns, unsigned int max, unsigned int id) { unsigned int first, last, mid; first = 0; last = max -1; if (insns[0].insn > id || insns[last].insn < id) { // not found return -1; } while (first <= last) { mid = (first + last) / 2; if (insns[mid].insn < id) { first = mid + 1; } else if (insns[mid].insn == id) { return mid; } else { if (mid == 0) break; last = mid - 1; } } // not found return -1; } // return register of given instruction id // return 0 if not found // this is to handle instructions embedding accumulate registers into AsmStrs[] x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access) { int i; i = binary_search1(insn_regs_intel, ARR_SIZE(insn_regs_intel), id); if (i != -1) { if (access) { *access = insn_regs_intel[i].access; } return insn_regs_intel[i].reg; } i = binary_search1(insn_regs_intel_extra, ARR_SIZE(insn_regs_intel_extra), id); if (i != -1) { if (access) { *access = insn_regs_intel_extra[i].access; } return insn_regs_intel_extra[i].reg; } // not found return 0; } bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2) { int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id); if (i != -1) { *reg1 = insn_regs_intel2[i].reg1; *reg2 = insn_regs_intel2[i].reg2; if (access1) *access1 = insn_regs_intel2[i].access1; if (access2) *access2 = insn_regs_intel2[i].access2; return true; } // not found return false; } x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access) { int i; i = binary_search1(insn_regs_att, ARR_SIZE(insn_regs_att), id); if (i != -1) { if (access) *access = insn_regs_att[i].access; return insn_regs_att[i].reg; } i = binary_search1(insn_regs_att_extra, ARR_SIZE(insn_regs_att_extra), id); if (i != -1) { if (access) *access = insn_regs_att_extra[i].access; return insn_regs_att_extra[i].reg; } // not found return 0; } // ATT just reuses Intel data, but with the order of registers reversed bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2) { int i = binary_search2(insn_regs_intel2, ARR_SIZE(insn_regs_intel2), id); if (i != -1) { *reg1 = insn_regs_intel2[i].reg2; *reg2 = insn_regs_intel2[i].reg1; if (access1) *access1 = insn_regs_intel2[i].access2; if (access2) *access2 = insn_regs_intel2[i].access1; return true; } // not found return false; } // given MCInst's id, find out if this insn is valid for REPNE prefix static bool valid_repne(cs_struct *h, unsigned int opcode) { unsigned int id; unsigned int i = find_insn(opcode); if (i != -1) { id = insns[i].mapid; switch(id) { default: return false; case X86_INS_CMPSB: case X86_INS_CMPSS: case X86_INS_CMPSW: case X86_INS_CMPSQ: case X86_INS_SCASB: case X86_INS_SCASW: case X86_INS_SCASQ: case X86_INS_MOVSB: case X86_INS_MOVSS: case X86_INS_MOVSW: case X86_INS_MOVSQ: case X86_INS_LODSB: case X86_INS_LODSW: case X86_INS_LODSD: case X86_INS_LODSQ: case X86_INS_STOSB: case X86_INS_STOSW: case X86_INS_STOSD: case X86_INS_STOSQ: case X86_INS_INSB: case X86_INS_INSW: case X86_INS_INSD: case X86_INS_OUTSB: case X86_INS_OUTSW: case X86_INS_OUTSD: return true; case X86_INS_MOVSD: if (opcode == X86_MOVSW) // REP MOVSB return true; return false; case X86_INS_CMPSD: if (opcode == X86_CMPSL) // REP CMPSD return true; return false; case X86_INS_SCASD: if (opcode == X86_SCASL) // REP SCASD return true; return false; } } // not found return false; } // given MCInst's id, find out if this insn is valid for BND prefix // BND prefix is valid for CALL/JMP/RET #ifndef CAPSTONE_DIET static bool valid_bnd(cs_struct *h, unsigned int opcode) { unsigned int id; unsigned int i = find_insn(opcode); if (i != -1) { id = insns[i].mapid; switch(id) { default: return false; case X86_INS_JAE: case X86_INS_JA: case X86_INS_JBE: case X86_INS_JB: case X86_INS_JCXZ: case X86_INS_JECXZ: case X86_INS_JE: case X86_INS_JGE: case X86_INS_JG: case X86_INS_JLE: case X86_INS_JL: case X86_INS_JMP: case X86_INS_JNE: case X86_INS_JNO: case X86_INS_JNP: case X86_INS_JNS: case X86_INS_JO: case X86_INS_JP: case X86_INS_JRCXZ: case X86_INS_JS: case X86_INS_CALL: case X86_INS_RET: case X86_INS_RETF: case X86_INS_RETFQ: return true; } } // not found return false; } #endif // return true if the opcode is XCHG [mem] static bool xchg_mem(unsigned int opcode) { switch(opcode) { default: return false; case X86_XCHG8rm: case X86_XCHG16rm: case X86_XCHG32rm: case X86_XCHG64rm: return true; } } // given MCInst's id, find out if this insn is valid for REP prefix static bool valid_rep(cs_struct *h, unsigned int opcode) { unsigned int id; unsigned int i = find_insn(opcode); if (i != -1) { id = insns[i].mapid; switch(id) { default: return false; case X86_INS_MOVSB: case X86_INS_MOVSW: case X86_INS_MOVSQ: case X86_INS_LODSB: case X86_INS_LODSW: case X86_INS_LODSQ: case X86_INS_STOSB: case X86_INS_STOSW: case X86_INS_STOSQ: case X86_INS_INSB: case X86_INS_INSW: case X86_INS_INSD: case X86_INS_OUTSB: case X86_INS_OUTSW: case X86_INS_OUTSD: return true; // following are some confused instructions, which have the same // mnemonics in 128bit media instructions. Intel is horribly crazy! case X86_INS_MOVSD: if (opcode == X86_MOVSL) // REP MOVSD return true; return false; case X86_INS_LODSD: if (opcode == X86_LODSL) // REP LODSD return true; return false; case X86_INS_STOSD: if (opcode == X86_STOSL) // REP STOSD return true; return false; } } // not found return false; } // given MCInst's id, find out if this insn is valid for REPE prefix static bool valid_repe(cs_struct *h, unsigned int opcode) { unsigned int id; unsigned int i = find_insn(opcode); if (i != -1) { id = insns[i].mapid; switch(id) { default: return false; case X86_INS_CMPSB: case X86_INS_CMPSW: case X86_INS_CMPSQ: case X86_INS_SCASB: case X86_INS_SCASW: case X86_INS_SCASQ: return true; // following are some confused instructions, which have the same // mnemonics in 128bit media instructions. Intel is horribly crazy! case X86_INS_CMPSD: if (opcode == X86_CMPSL) // REP CMPSD return true; return false; case X86_INS_SCASD: if (opcode == X86_SCASL) // REP SCASD return true; return false; } } // not found return false; } #ifndef CAPSTONE_DIET // add *CX register to regs_read[] & regs_write[] static void add_cx(MCInst *MI) { if (MI->csh->detail) { x86_reg cx; if (MI->csh->mode & CS_MODE_16) cx = X86_REG_CX; else if (MI->csh->mode & CS_MODE_32) cx = X86_REG_ECX; else // 64-bit cx = X86_REG_RCX; MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = cx; MI->flat_insn->detail->regs_read_count++; MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = cx; MI->flat_insn->detail->regs_write_count++; } } #endif // return true if we patch the mnemonic bool X86_lockrep(MCInst *MI, SStream *O) { unsigned int opcode; bool res = false; switch(MI->x86_prefix[0]) { default: break; case 0xf0: #ifndef CAPSTONE_DIET if (MI->xAcquireRelease == 0xf2) SStream_concat(O, "xacquire|lock|"); else if (MI->xAcquireRelease == 0xf3) SStream_concat(O, "xrelease|lock|"); else SStream_concat(O, "lock|"); #endif break; case 0xf2: // repne opcode = MCInst_getOpcode(MI); #ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode if (xchg_mem(opcode) && MI->xAcquireRelease) { SStream_concat(O, "xacquire|"); } else if (valid_repne(MI->csh, opcode)) { SStream_concat(O, "repne|"); add_cx(MI); } else if (valid_bnd(MI->csh, opcode)) { SStream_concat(O, "bnd|"); } else { // invalid prefix MI->x86_prefix[0] = 0; // handle special cases #ifndef CAPSTONE_X86_REDUCE #if 0 if (opcode == X86_MULPDrr) { MCInst_setOpcode(MI, X86_MULSDrr); SStream_concat(O, "mulsd\t"); res = true; } #endif #endif } #else // diet mode -> only patch opcode in special cases if (!valid_repne(MI->csh, opcode)) { MI->x86_prefix[0] = 0; } #ifndef CAPSTONE_X86_REDUCE #if 0 // handle special cases if (opcode == X86_MULPDrr) { MCInst_setOpcode(MI, X86_MULSDrr); } #endif #endif #endif break; case 0xf3: opcode = MCInst_getOpcode(MI); #ifndef CAPSTONE_DIET // only care about memonic in standard (non-diet) mode if (xchg_mem(opcode) && MI->xAcquireRelease) { SStream_concat(O, "xrelease|"); } else if (valid_rep(MI->csh, opcode)) { SStream_concat(O, "rep|"); add_cx(MI); } else if (valid_repe(MI->csh, opcode)) { SStream_concat(O, "repe|"); add_cx(MI); } else { // invalid prefix MI->x86_prefix[0] = 0; // handle special cases #ifndef CAPSTONE_X86_REDUCE #if 0 // FIXME: remove this special case? if (opcode == X86_MULPDrr) { MCInst_setOpcode(MI, X86_MULSSrr); SStream_concat(O, "mulss\t"); res = true; } #endif #endif } #else // diet mode -> only patch opcode in special cases if (!valid_rep(MI->csh, opcode) && !valid_repe(MI->csh, opcode)) { MI->x86_prefix[0] = 0; } #ifndef CAPSTONE_X86_REDUCE #if 0 // handle special cases // FIXME: remove this special case? if (opcode == X86_MULPDrr) { MCInst_setOpcode(MI, X86_MULSSrr); } #endif #endif #endif break; } // copy normalized prefix[] back to x86.prefix[] if (MI->csh->detail) memcpy(MI->flat_insn->detail->x86.prefix, MI->x86_prefix, ARR_SIZE(MI->x86_prefix)); return res; } void op_addReg(MCInst *MI, int reg) { if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg]; MI->flat_insn->detail->x86.op_count++; } if (MI->op1_size == 0) MI->op1_size = MI->csh->regsize_map[reg]; } void op_addImm(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v; // if op_count > 0, then this operand's size is taken from the destination op if (MI->csh->syntax != CS_OPT_SYNTAX_ATT) { if (MI->flat_insn->detail->x86.op_count > 0) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size; else MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; } else MI->has_imm = true; MI->flat_insn->detail->x86.op_count++; } if (MI->op1_size == 0) MI->op1_size = MI->imm_size; } void op_addXopCC(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->x86.xop_cc = v; } } void op_addSseCC(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->x86.sse_cc = v; } } void op_addAvxCC(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->x86.avx_cc = v; } } void op_addAvxRoundingMode(MCInst *MI, int v) { if (MI->csh->detail) { MI->flat_insn->detail->x86.avx_rm = v; } } // below functions supply details to X86GenAsmWriter*.inc void op_addAvxZeroOpmask(MCInst *MI) { if (MI->csh->detail) { // link with the previous operand MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_zero_opmask = true; } } void op_addAvxSae(MCInst *MI) { if (MI->csh->detail) { MI->flat_insn->detail->x86.avx_sae = true; } } void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v) { if (MI->csh->detail) { // link with the previous operand MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].avx_bcast = v; } } #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { uint64_t flags; // how this instruction update EFLAGS(arithmetic instrcutions) of FPU FLAGS(for FPU instructions) uint8_t access[6]; } insn_op; static const insn_op insn_ops[] = { #ifdef CAPSTONE_X86_REDUCE #include "X86MappingInsnOp_reduce.inc" #else #include "X86MappingInsnOp.inc" #endif }; // given internal insn id, return operand access info const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags) { unsigned int i = find_insn(id); if (i != -1) { *eflags = insn_ops[i].flags; return insn_ops[i].access; } return NULL; } void X86_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count) { uint8_t i; uint8_t read_count, write_count; cs_x86 *x86 = &(insn->detail->x86); read_count = insn->detail->regs_read_count; write_count = insn->detail->regs_write_count; // implicit registers memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0])); memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0])); // explicit registers for (i = 0; i < x86->op_count; i++) { cs_x86_op *op = &(x86->operands[i]); switch((int)op->type) { case X86_OP_REG: if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) { regs_read[read_count] = op->reg; read_count++; } if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) { regs_write[write_count] = op->reg; write_count++; } break; case X86_OP_MEM: // registers appeared in memory references always being read if ((op->mem.segment != X86_REG_INVALID)) { regs_read[read_count] = op->mem.segment; read_count++; } if ((op->mem.base != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) { regs_read[read_count] = op->mem.base; read_count++; } if ((op->mem.index != X86_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) { regs_read[read_count] = op->mem.index; read_count++; } default: break; } } *regs_read_count = read_count; *regs_write_count = write_count; } #endif // map immediate size to instruction id // this array is sorted for binary searching static const struct size_id { uint8_t enc_size; uint8_t size; uint16_t id; } x86_imm_size[] = { #include "X86ImmSize.inc" }; // given the instruction name, return the size of its immediate operand (or 0) uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size) { // binary searching since the IDs are sorted in order unsigned int left, right, m; right = ARR_SIZE(x86_imm_size) - 1; if (id < x86_imm_size[0].id || id > x86_imm_size[right].id) // not found return 0; left = 0; while (left <= right) { m = (left + right) / 2; if (id == x86_imm_size[m].id) { if (enc_size != NULL) *enc_size = x86_imm_size[m].enc_size; return x86_imm_size[m].size; } if (id > x86_imm_size[m].id) left = m + 1; else { if (m == 0) break; right = m - 1; } } // not found return 0; } #define GET_REGINFO_ENUM #include "X86GenRegisterInfo.inc" // map internal register id to public register id static const struct register_map { unsigned short id; unsigned short pub_id; } reg_map [] = { // first dummy map { 0, 0 }, #include "X86MappingReg.inc" }; // return 0 on invalid input, or public register ID otherwise // NOTE: reg_map is sorted in order of internal register unsigned short X86_register_map(unsigned short id) { if (id < ARR_SIZE(reg_map)) return reg_map[id].pub_id; return 0; } #endif capstone-sys-0.15.0/capstone/arch/X86/X86Mapping.h000064400000000000000000000057310072674642500175650ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_X86_MAP_H #define CS_X86_MAP_H #include "capstone/capstone.h" #include "../../cs_priv.h" // map instruction to its characteristics typedef struct insn_map_x86 { unsigned short id; unsigned short mapid; unsigned char is64bit; #ifndef CAPSTONE_DIET uint16_t regs_use[12]; // list of implicit registers used by this instruction uint16_t regs_mod[20]; // list of implicit registers modified by this instruction unsigned char groups[8]; // list of group this instruction belong to bool branch; // branch instruction? bool indirect_branch; // indirect branch instruction? #endif } insn_map_x86; extern const insn_map_x86 insns[]; // map sib_base to x86_reg x86_reg x86_map_sib_base(int r); // map sib_index to x86_reg x86_reg x86_map_sib_index(int r); // map seg_override to x86_reg x86_reg x86_map_segment(int r); // return name of regiser in friendly string const char *X86_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); // return insn name, given insn id const char *X86_insn_name(csh handle, unsigned int id); // return group name, given group id const char *X86_group_name(csh handle, unsigned int id); // return register of given instruction id // return 0 if not found // this is to handle instructions embedding accumulate registers into AsmStrs[] x86_reg X86_insn_reg_intel(unsigned int id, enum cs_ac_type *access); x86_reg X86_insn_reg_att(unsigned int id, enum cs_ac_type *access); bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2); bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, enum cs_ac_type *access1, x86_reg *reg2, enum cs_ac_type *access2); extern const uint64_t arch_masks[9]; // handle LOCK/REP/REPNE prefixes // return True if we patch mnemonic, like in MULPD case bool X86_lockrep(MCInst *MI, SStream *O); // map registers to sizes extern const uint8_t regsize_map_32[]; extern const uint8_t regsize_map_64[]; void op_addReg(MCInst *MI, int reg); void op_addImm(MCInst *MI, int v); void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v); void op_addXopCC(MCInst *MI, int v); void op_addSseCC(MCInst *MI, int v); void op_addAvxCC(MCInst *MI, int v); void op_addAvxZeroOpmask(MCInst *MI); void op_addAvxSae(MCInst *MI); void op_addAvxRoundingMode(MCInst *MI, int v); // given internal insn id, return operand access info const uint8_t *X86_get_op_access(cs_struct *h, unsigned int id, uint64_t *eflags); void X86_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); // given the instruction id, return the size of its immediate operand (or 0) uint8_t X86_immediate_size(unsigned int id, uint8_t *enc_size); unsigned short X86_register_map(unsigned short id); unsigned int find_insn(unsigned int id); #endif capstone-sys-0.15.0/capstone/arch/X86/X86MappingInsn.inc000064400000000000000000063461570072674642500207570ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { X86_AAA, X86_INS_AAA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AAD8i8, X86_INS_AAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AAM8i8, X86_INS_AAM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AAS, X86_INS_AAS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ABS_F, X86_INS_FABS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ABS_Fp32, X86_INS_FABS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ABS_Fp64, X86_INS_FABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ABS_Fp80, X86_INS_FABS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16i16, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16mi, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16mi8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16mr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16ri, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16ri8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16rm, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16rr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16rr_REV, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32i32, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32mi, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32mi8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32mr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32ri, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32ri8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32rm, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32rr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32rr_REV, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64i32, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64mi32, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64mi8, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64mr, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64ri32, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64ri8, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64rm, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64rr, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64rr_REV, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8i8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8mi, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8mi8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADC8mr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8ri, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8ri8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADC8rm, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8rr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8rr_REV, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADCX32rm, X86_INS_ADCX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADCX32rr, X86_INS_ADCX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADCX64rm, X86_INS_ADCX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADCX64rr, X86_INS_ADCX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADD16i16, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16mi, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16mi8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16mr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16ri, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16ri8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16rm, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16rr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16rr_REV, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32i32, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32mi, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32mi8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32mr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32ri, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32ri8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32rm, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32rr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32rr_REV, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64i32, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64mi32, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64mi8, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64mr, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64ri32, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64ri8, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64rm, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64rr, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64rr_REV, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8i8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8mi, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8mi8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADD8mr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8ri, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8ri8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADD8rm, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8rr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8rr_REV, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADDPDrm, X86_INS_ADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ADDPDrr, X86_INS_ADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ADDPSrm, X86_INS_ADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ADDPSrr, X86_INS_ADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ADDSDrm, X86_INS_ADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ADDSDrm_Int, X86_INS_ADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ADDSDrr, X86_INS_ADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ADDSDrr_Int, X86_INS_ADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ADDSSrm, X86_INS_ADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ADDSSrm_Int, X86_INS_ADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ADDSSrr, X86_INS_ADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ADDSSrr_Int, X86_INS_ADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ADDSUBPDrm, X86_INS_ADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_ADDSUBPDrr, X86_INS_ADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_ADDSUBPSrm, X86_INS_ADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_ADDSUBPSrr, X86_INS_ADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_ADD_F32m, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADD_F64m, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADD_FI16m, X86_INS_FIADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADD_FI32m, X86_INS_FIADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADD_FPrST0, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADD_FST0r, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADD_Fp32, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp32m, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp64, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp64m, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp64m32, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp80, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp80m32, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_Fp80m64, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FpI16m32, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FpI16m64, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FpI16m80, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FpI32m32, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FpI32m64, X86_INS_FADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FpI32m80, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ADD_FrST0, X86_INS_FADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ADOX32rm, X86_INS_ADOX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADOX32rr, X86_INS_ADOX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADOX64rm, X86_INS_ADOX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADOX64rr, X86_INS_ADOX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_AESDECLASTrm, X86_INS_AESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESDECLASTrr, X86_INS_AESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESDECrm, X86_INS_AESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESDECrr, X86_INS_AESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESENCLASTrm, X86_INS_AESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESENCLASTrr, X86_INS_AESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESENCrm, X86_INS_AESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESENCrr, X86_INS_AESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESIMCrm, X86_INS_AESIMC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESIMCrr, X86_INS_AESIMC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESKEYGENASSIST128rm, X86_INS_AESKEYGENASSIST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AESKEYGENASSIST128rr, X86_INS_AESKEYGENASSIST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_AND16i16, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16mi, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16mi8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16mr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16ri, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16ri8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16rm, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16rr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16rr_REV, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32i32, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32mi, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32mi8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32mr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32ri, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32ri8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32rm, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32rr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32rr_REV, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64i32, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64mi32, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64mi8, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64mr, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64ri32, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64ri8, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64rm, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64rr, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64rr_REV, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8i8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8mi, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8mi8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AND8mr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8ri, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8ri8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AND8rm, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8rr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8rr_REV, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ANDN32rm, X86_INS_ANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDN32rr, X86_INS_ANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDN64rm, X86_INS_ANDN, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDN64rr, X86_INS_ANDN, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDNPDrm, X86_INS_ANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ANDNPDrr, X86_INS_ANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ANDNPSrm, X86_INS_ANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ANDNPSrr, X86_INS_ANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ANDPDrm, X86_INS_ANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ANDPDrr, X86_INS_ANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ANDPSrm, X86_INS_ANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ANDPSrr, X86_INS_ANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ARPL16mr, X86_INS_ARPL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ARPL16rr, X86_INS_ARPL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_BEXTR32rm, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTR32rr, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTR64rm, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTR64rr, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTRI32mi, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BEXTRI32ri, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BEXTRI64mi, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BEXTRI64ri, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL32rm, X86_INS_BLCFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL32rr, X86_INS_BLCFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL64rm, X86_INS_BLCFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL64rr, X86_INS_BLCFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI32rm, X86_INS_BLCI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI32rr, X86_INS_BLCI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI64rm, X86_INS_BLCI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI64rr, X86_INS_BLCI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC32rm, X86_INS_BLCIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC32rr, X86_INS_BLCIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC64rm, X86_INS_BLCIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC64rr, X86_INS_BLCIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK32rm, X86_INS_BLCMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK32rr, X86_INS_BLCMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK64rm, X86_INS_BLCMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK64rr, X86_INS_BLCMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS32rm, X86_INS_BLCS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS32rr, X86_INS_BLCS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS64rm, X86_INS_BLCS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS64rr, X86_INS_BLCS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLENDPDrmi, X86_INS_BLENDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDPDrri, X86_INS_BLENDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDPSrmi, X86_INS_BLENDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDPSrri, X86_INS_BLENDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDVPDrm0, X86_INS_BLENDVPD, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDVPDrr0, X86_INS_BLENDVPD, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDVPSrm0, X86_INS_BLENDVPS, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLENDVPSrr0, X86_INS_BLENDVPS, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_BLSFILL32rm, X86_INS_BLSFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL32rr, X86_INS_BLSFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL64rm, X86_INS_BLSFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL64rr, X86_INS_BLSFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSI32rm, X86_INS_BLSI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSI32rr, X86_INS_BLSI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSI64rm, X86_INS_BLSI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSI64rr, X86_INS_BLSI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSIC32rm, X86_INS_BLSIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSIC32rr, X86_INS_BLSIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSIC64rm, X86_INS_BLSIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSIC64rr, X86_INS_BLSIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSMSK32rm, X86_INS_BLSMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSMSK32rr, X86_INS_BLSMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSMSK64rm, X86_INS_BLSMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSMSK64rr, X86_INS_BLSMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR32rm, X86_INS_BLSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR32rr, X86_INS_BLSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR64rm, X86_INS_BLSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR64rr, X86_INS_BLSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BNDCL32rm, X86_INS_BNDCL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCL32rr, X86_INS_BNDCL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCL64rm, X86_INS_BNDCL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCL64rr, X86_INS_BNDCL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCN32rm, X86_INS_BNDCN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCN32rr, X86_INS_BNDCN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCN64rm, X86_INS_BNDCN, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCN64rr, X86_INS_BNDCN, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCU32rm, X86_INS_BNDCU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCU32rr, X86_INS_BNDCU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCU64rm, X86_INS_BNDCU, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDCU64rr, X86_INS_BNDCU, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDLDXrm, X86_INS_BNDLDX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMK32rm, X86_INS_BNDMK, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMK64rm, X86_INS_BNDMK, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMOV32mr, X86_INS_BNDMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMOV32rm, X86_INS_BNDMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMOV64mr, X86_INS_BNDMOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMOV64rm, X86_INS_BNDMOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMOVrr, X86_INS_BNDMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDMOVrr_REV, X86_INS_BNDMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BNDSTXmr, X86_INS_BNDSTX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BOUNDS16rm, X86_INS_BOUND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_BOUNDS32rm, X86_INS_BOUND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_BSF16rm, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF16rr, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF32rm, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF32rr, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF64rm, X86_INS_BSF, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF64rr, X86_INS_BSF, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR16rm, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR16rr, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR32rm, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR32rr, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR64rm, X86_INS_BSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR64rr, X86_INS_BSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSWAP16r_BAD, X86_INS_BSWAP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BSWAP32r, X86_INS_BSWAP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BSWAP64r, X86_INS_BSWAP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BT16mi8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT16mr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT16ri8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT16rr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32mi8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32mr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32ri8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32rr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64mi8, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64mr, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64ri8, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64rr, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16mi8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16mr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16ri8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16rr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32mi8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32mr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32ri8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32rr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64mi8, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64mr, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64ri8, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64rr, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16mi8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16mr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16ri8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16rr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32mi8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32mr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32ri8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32rr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64mi8, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64mr, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64ri8, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64rr, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16mi8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16mr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16ri8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16rr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32mi8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32mr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32ri8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32rr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64mi8, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64mr, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64ri8, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64rr, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BZHI32rm, X86_INS_BZHI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_BZHI32rr, X86_INS_BZHI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_BZHI64rm, X86_INS_BZHI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_BZHI64rr, X86_INS_BZHI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_CALL16m, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL16m_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL16r, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL16r_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL32m, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL32m_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL32r, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL32r_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL64m, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_CALL64m_NT, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL64pcrel32, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_CALL64r, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_CALL64r_NT, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALLpcrel16, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 #endif }, { X86_CALLpcrel32, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CBW, X86_INS_CBW, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_CDQ, X86_INS_CDQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 #endif }, { X86_CDQE, X86_INS_CDQE, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_RAX, 0 }, { 0 }, 0, 0 #endif }, { X86_CHS_F, X86_INS_FCHS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CHS_Fp32, X86_INS_FCHS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CHS_Fp64, X86_INS_FCHS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CHS_Fp80, X86_INS_FCHS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLAC, X86_INS_CLAC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_CLC, X86_INS_CLC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CLD, X86_INS_CLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CLDEMOTE, X86_INS_CLDEMOTE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLFLUSH, X86_INS_CLFLUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLGI, X86_INS_CLGI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_CLI, X86_INS_CLI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_CLRSSBSY, X86_INS_CLRSSBSY, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLTS, X86_INS_CLTS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLWB, X86_INS_CLWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLZEROr, X86_INS_CLZERO, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMC, X86_INS_CMC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVA16rm, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA16rr, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA32rm, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA32rr, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA64rm, X86_INS_CMOVA, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA64rr, X86_INS_CMOVA, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE16rm, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE16rr, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE32rm, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE32rr, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE64rm, X86_INS_CMOVAE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE64rr, X86_INS_CMOVAE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB16rm, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB16rr, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB32rm, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB32rr, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB64rm, X86_INS_CMOVB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB64rr, X86_INS_CMOVB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE16rm, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE16rr, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE32rm, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE32rr, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE64rm, X86_INS_CMOVBE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE64rr, X86_INS_CMOVBE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE_F, X86_INS_FCMOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVBE_Fp32, X86_INS_FCMOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVBE_Fp64, X86_INS_FCMOVBE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVBE_Fp80, X86_INS_FCMOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVB_F, X86_INS_FCMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVB_Fp32, X86_INS_FCMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVB_Fp64, X86_INS_FCMOVB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVB_Fp80, X86_INS_FCMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVE16rm, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE16rr, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE32rm, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE32rr, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE64rm, X86_INS_CMOVE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE64rr, X86_INS_CMOVE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE_F, X86_INS_FCMOVE, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVE_Fp32, X86_INS_FCMOVE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVE_Fp64, X86_INS_FCMOVE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVE_Fp80, X86_INS_FCMOVE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVG16rm, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG16rr, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG32rm, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG32rr, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG64rm, X86_INS_CMOVG, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG64rr, X86_INS_CMOVG, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE16rm, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE16rr, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE32rm, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE32rr, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE64rm, X86_INS_CMOVGE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE64rr, X86_INS_CMOVGE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL16rm, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL16rr, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL32rm, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL32rr, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL64rm, X86_INS_CMOVL, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL64rr, X86_INS_CMOVL, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE16rm, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE16rr, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE32rm, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE32rr, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE64rm, X86_INS_CMOVLE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE64rr, X86_INS_CMOVLE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNBE_F, X86_INS_FCMOVNBE, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVNBE_Fp32, X86_INS_FCMOVNBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNBE_Fp64, X86_INS_FCMOVNBE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNBE_Fp80, X86_INS_FCMOVNBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNB_F, X86_INS_FCMOVNB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNB_Fp32, X86_INS_FCMOVNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNB_Fp64, X86_INS_FCMOVNB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNB_Fp80, X86_INS_FCMOVNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNE16rm, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE16rr, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE32rm, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE32rr, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE64rm, X86_INS_CMOVNE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE64rr, X86_INS_CMOVNE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE_F, X86_INS_FCMOVNE, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVNE_Fp32, X86_INS_FCMOVNE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNE_Fp64, X86_INS_FCMOVNE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNE_Fp80, X86_INS_FCMOVNE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNO16rm, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO16rr, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO32rm, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO32rr, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO64rm, X86_INS_CMOVNO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO64rr, X86_INS_CMOVNO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP16rm, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP16rr, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP32rm, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP32rr, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP64rm, X86_INS_CMOVNP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP64rr, X86_INS_CMOVNP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP_F, X86_INS_FCMOVNU, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVNP_Fp32, X86_INS_FCMOVNP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNP_Fp64, X86_INS_FCMOVNU, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNP_Fp80, X86_INS_FCMOVNU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVNS16rm, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS16rr, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS32rm, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS32rr, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS64rm, X86_INS_CMOVNS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS64rr, X86_INS_CMOVNS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO16rm, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO16rr, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO32rm, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO32rr, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO64rm, X86_INS_CMOVO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO64rr, X86_INS_CMOVO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP16rm, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP16rr, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP32rm, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP32rr, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP64rm, X86_INS_CMOVP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP64rr, X86_INS_CMOVP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP_F, X86_INS_FCMOVU, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_CMOV, X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_CMOVP_Fp32, X86_INS_FCMOVU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVP_Fp64, X86_INS_FCMOVU, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVP_Fp80, X86_INS_FCMOVU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVS16rm, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS16rr, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS32rm, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS32rr, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS64rm, X86_INS_CMOVS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS64rr, X86_INS_CMOVS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMP16i16, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16mi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16mi8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16mr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16ri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16ri8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16rm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16rr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16rr_REV, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32i32, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32mi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32mi8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32mr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32ri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32ri8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32rm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32rr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32rr_REV, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64i32, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64mi32, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64mi8, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64mr, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64ri32, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64ri8, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64rm, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64rr, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64rr_REV, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8i8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8mi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8mi8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CMP8mr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8ri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8ri8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CMP8rm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8rr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8rr_REV, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPPDrmi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPPDrmi_alt, X86_INS_CMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPPDrri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPPDrri_alt, X86_INS_CMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPPSrmi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPPSrmi_alt, X86_INS_CMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPPSrri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPPSrri_alt, X86_INS_CMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPSB, X86_INS_CMPSB, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSDrm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPSDrm_Int, X86_INS_CMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSDrm_alt, X86_INS_CMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPSDrr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPSDrr_Int, X86_INS_CMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSDrr_alt, X86_INS_CMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CMPSL, X86_INS_CMPSD, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSQ, X86_INS_CMPSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSSrm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPSSrm_Int, X86_INS_CMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSSrm_alt, X86_INS_CMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPSSrr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPSSrr_Int, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSSrr_alt, X86_INS_CMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CMPSW, X86_INS_CMPSW, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG16B, X86_INS_CMPXCHG16B, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG16rm, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG16rr, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG32rm, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG32rr, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG64rm, X86_INS_CMPXCHG, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG64rr, X86_INS_CMPXCHG, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG8B, X86_INS_CMPXCHG8B, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG8rm, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG8rr, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COMISDrm, X86_INS_COMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_COMISDrm_Int, X86_INS_COMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COMISDrr, X86_INS_COMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_COMISDrr_Int, X86_INS_COMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COMISSrm, X86_INS_COMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_COMISSrm_Int, X86_INS_COMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COMISSrr, X86_INS_COMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_COMISSrr_Int, X86_INS_COMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COMP_FST0r, X86_INS_FCOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_COM_FIPr, X86_INS_FCOMPI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_COM_FIr, X86_INS_FCOMI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_COM_FST0r, X86_INS_FCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_COS_F, X86_INS_FCOS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_COS_Fp32, X86_INS_FCOS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COS_Fp64, X86_INS_FCOS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_COS_Fp80, X86_INS_FCOS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CPUID, X86_INS_CPUID, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, 0, 0 #endif }, { X86_CQO, X86_INS_CQO, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 #endif }, { X86_CRC32r32m16, X86_INS_CRC32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r32m32, X86_INS_CRC32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r32m8, X86_INS_CRC32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r32r16, X86_INS_CRC32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r32r32, X86_INS_CRC32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r32r8, X86_INS_CRC32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r64m64, X86_INS_CRC32, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r64m8, X86_INS_CRC32, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r64r64, X86_INS_CRC32, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CRC32r64r8, X86_INS_CRC32, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_CVTDQ2PDrm, X86_INS_CVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTDQ2PDrr, X86_INS_CVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTDQ2PSrm, X86_INS_CVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTDQ2PSrr, X86_INS_CVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPD2DQrm, X86_INS_CVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPD2DQrr, X86_INS_CVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPD2PSrm, X86_INS_CVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPD2PSrr, X86_INS_CVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPS2DQrm, X86_INS_CVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPS2DQrr, X86_INS_CVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPS2PDrm, X86_INS_CVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTPS2PDrr, X86_INS_CVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSD2SI64rm_Int, X86_INS_CVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSD2SI64rr_Int, X86_INS_CVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSD2SIrm_Int, X86_INS_CVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSD2SIrr_Int, X86_INS_CVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSD2SSrm, X86_INS_CVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSD2SSrm_Int, X86_INS_CVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSD2SSrr, X86_INS_CVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSD2SSrr_Int, X86_INS_CVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI2SDrm, X86_INS_CVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSI2SDrm_Int, X86_INS_CVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI2SDrr, X86_INS_CVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSI2SDrr_Int, X86_INS_CVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI2SSrm, X86_INS_CVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CVTSI2SSrm_Int, X86_INS_CVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI2SSrr, X86_INS_CVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CVTSI2SSrr_Int, X86_INS_CVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SDrm, X86_INS_CVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SDrm_Int, X86_INS_CVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SDrr, X86_INS_CVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SDrr_Int, X86_INS_CVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SSrm, X86_INS_CVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SSrm_Int, X86_INS_CVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SSrr, X86_INS_CVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSI642SSrr_Int, X86_INS_CVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSS2SDrm, X86_INS_CVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSS2SDrm_Int, X86_INS_CVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSS2SDrr, X86_INS_CVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTSS2SDrr_Int, X86_INS_CVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSS2SI64rm_Int, X86_INS_CVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSS2SI64rr_Int, X86_INS_CVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSS2SIrm_Int, X86_INS_CVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTSS2SIrr_Int, X86_INS_CVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTPD2DQrm, X86_INS_CVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTPD2DQrr, X86_INS_CVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTPS2DQrm, X86_INS_CVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTPS2DQrr, X86_INS_CVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTSD2SI64rm, X86_INS_CVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTSD2SI64rm_Int, X86_INS_CVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSD2SI64rr, X86_INS_CVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTSD2SI64rr_Int, X86_INS_CVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSD2SIrm, X86_INS_CVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTSD2SIrm_Int, X86_INS_CVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSD2SIrr, X86_INS_CVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_CVTTSD2SIrr_Int, X86_INS_CVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSS2SI64rm, X86_INS_CVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CVTTSS2SI64rm_Int, X86_INS_CVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSS2SI64rr, X86_INS_CVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CVTTSS2SI64rr_Int, X86_INS_CVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSS2SIrm, X86_INS_CVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CVTTSS2SIrm_Int, X86_INS_CVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CVTTSS2SIrr, X86_INS_CVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_CVTTSS2SIrr_Int, X86_INS_CVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CWD, X86_INS_CWD, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, 0 }, { 0 }, 0, 0 #endif }, { X86_CWDE, X86_INS_CWDE, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_DAA, X86_INS_DAA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DAS, X86_INS_DAS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DATA16_PREFIX, X86_INS_DATA16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DEC16m, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC16r, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC16r_alt, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DEC32m, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC32r, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC32r_alt, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DEC64m, X86_INS_DEC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC64r, X86_INS_DEC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC8m, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC8r, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV16m, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV16r, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV32m, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV32r, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV64m, X86_INS_DIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV64r, X86_INS_DIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV8m, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV8r, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIVPDrm, X86_INS_DIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_DIVPDrr, X86_INS_DIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_DIVPSrm, X86_INS_DIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_DIVPSrr, X86_INS_DIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_DIVR_F32m, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVR_F64m, X86_INS_FDIVR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVR_FI16m, X86_INS_FIDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVR_FI32m, X86_INS_FIDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVR_FPrST0, X86_INS_FDIVRP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVR_FST0r, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVR_Fp32m, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_Fp64m, X86_INS_FDIVR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_Fp64m32, X86_INS_FDIVR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_Fp80m32, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_Fp80m64, X86_INS_FDIVR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FpI16m32, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FpI16m64, X86_INS_FDIVR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FpI16m80, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FpI32m32, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FpI32m64, X86_INS_FDIVR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FpI32m80, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIVR_FrST0, X86_INS_FDIVR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIVSDrm, X86_INS_DIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_DIVSDrm_Int, X86_INS_DIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_DIVSDrr, X86_INS_DIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_DIVSDrr_Int, X86_INS_DIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_DIVSSrm, X86_INS_DIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_DIVSSrm_Int, X86_INS_DIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_DIVSSrr, X86_INS_DIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_DIVSSrr_Int, X86_INS_DIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_DIV_F32m, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIV_F64m, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIV_FI16m, X86_INS_FIDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIV_FI32m, X86_INS_FIDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIV_FPrST0, X86_INS_FDIVP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIV_FST0r, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DIV_Fp32, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp32m, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp64, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp64m, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp64m32, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp80, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp80m32, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_Fp80m64, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FpI16m32, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FpI16m64, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FpI16m80, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FpI32m32, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FpI32m64, X86_INS_FDIV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FpI32m80, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DIV_FrST0, X86_INS_FDIV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_DPPDrmi, X86_INS_DPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_DPPDrri, X86_INS_DPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_DPPSrmi, X86_INS_DPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_DPPSrri, X86_INS_DPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ENCLS, X86_INS_ENCLS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENCLU, X86_INS_ENCLU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENCLV, X86_INS_ENCLV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENDBR32, X86_INS_ENDBR32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENDBR64, X86_INS_ENDBR64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENTER, X86_INS_ENTER, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_EXTRACTPSmr, X86_INS_EXTRACTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_EXTRACTPSrr, X86_INS_EXTRACTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_EXTRQ, X86_INS_EXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 #endif }, { X86_EXTRQI, X86_INS_EXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 #endif }, { X86_F2XM1, X86_INS_F2XM1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FARCALL16i, X86_INS_LCALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_FARCALL16m, X86_INS_LCALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_FARCALL32i, X86_INS_LCALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_FARCALL32m, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_FARCALL64, X86_INS_LCALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_FARJMP16i, X86_INS_LJMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_FARJMP16m, X86_INS_LJMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { X86_FARJMP32i, X86_INS_LJMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_FARJMP32m, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { X86_FARJMP64, X86_INS_LJMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { X86_FBLDm, X86_INS_FBLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FBSTPm, X86_INS_FBSTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FCOM32m, X86_INS_FCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FCOM64m, X86_INS_FCOM, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FCOMP32m, X86_INS_FCOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FCOMP64m, X86_INS_FCOMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FCOMPP, X86_INS_FCOMPP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FDECSTP, X86_INS_FDECSTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FDISI8087_NOP, X86_INS_FDISI8087_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FEMMS, X86_INS_FEMMS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_FENI8087_NOP, X86_INS_FENI8087_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FFREE, X86_INS_FFREE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FFREEP, X86_INS_FFREEP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FICOM16m, X86_INS_FICOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FICOM32m, X86_INS_FICOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FICOMP16m, X86_INS_FICOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FICOMP32m, X86_INS_FICOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FINCSTP, X86_INS_FINCSTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FLDCW16m, X86_INS_FLDCW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FLDENVm, X86_INS_FLDENV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FLDL2E, X86_INS_FLDL2E, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FLDL2T, X86_INS_FLDL2T, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FLDLG2, X86_INS_FLDLG2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FLDLN2, X86_INS_FLDLN2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FLDPI, X86_INS_FLDPI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FNCLEX, X86_INS_FNCLEX, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FNINIT, X86_INS_FNINIT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FNOP, X86_INS_FNOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FNSTCW16m, X86_INS_FNSTCW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FNSTSW16r, X86_INS_FNSTSW, 0, #ifndef CAPSTONE_DIET { X86_REG_FPSW, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_FNSTSWm, X86_INS_FNSTSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FPATAN, X86_INS_FPATAN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FPNCEST0r, X86_INS_FSTPNCE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FPREM, X86_INS_FPREM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FPREM1, X86_INS_FPREM1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FPTAN, X86_INS_FPTAN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FRNDINT, X86_INS_FRNDINT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FRSTORm, X86_INS_FRSTOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FSAVEm, X86_INS_FNSAVE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FSCALE, X86_INS_FSCALE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FSETPM, X86_INS_FSETPM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FSINCOS, X86_INS_FSINCOS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FSTENVm, X86_INS_FNSTENV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FXAM, X86_INS_FXAM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FXRSTOR, X86_INS_FXRSTOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FXRSTOR64, X86_INS_FXRSTOR64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_FXSAVE, X86_INS_FXSAVE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FXSAVE64, X86_INS_FXSAVE64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_FXTRACT, X86_INS_FXTRACT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FYL2X, X86_INS_FYL2X, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_FYL2XP1, X86_INS_FYL2XP1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_GETSEC, X86_INS_GETSEC, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, 0 }, { 0 }, 0, 0 #endif }, { X86_GF2P8AFFINEINVQBrmi, X86_INS_GF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_GF2P8AFFINEINVQBrri, X86_INS_GF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_GF2P8AFFINEQBrmi, X86_INS_GF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_GF2P8AFFINEQBrri, X86_INS_GF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_GF2P8MULBrm, X86_INS_GF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_GF2P8MULBrr, X86_INS_GF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_HADDPDrm, X86_INS_HADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HADDPDrr, X86_INS_HADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HADDPSrm, X86_INS_HADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HADDPSrr, X86_INS_HADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HLT, X86_INS_HLT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_HSUBPDrm, X86_INS_HSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HSUBPDrr, X86_INS_HSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HSUBPSrm, X86_INS_HSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_HSUBPSrr, X86_INS_HSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_IDIV16m, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV16r, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV32m, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV32r, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV64m, X86_INS_IDIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV64r, X86_INS_IDIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV8m, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV8r, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_F16m, X86_INS_FILD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ILD_F32m, X86_INS_FILD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ILD_F64m, X86_INS_FILD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ILD_Fp16m32, X86_INS_FILD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp16m64, X86_INS_FILD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp16m80, X86_INS_FILD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp32m32, X86_INS_FILD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp32m64, X86_INS_FILD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp32m80, X86_INS_FILD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp64m32, X86_INS_FILD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp64m64, X86_INS_FILD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ILD_Fp64m80, X86_INS_FILD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16m, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16r, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rm, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rmi, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rmi8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rr, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rri, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rri8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32m, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32r, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rm, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rmi, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rmi8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rr, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rri, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rri8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64m, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64r, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rm, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rmi32, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rmi8, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rr, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rri32, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rri8, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL8m, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL8r, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN16ri, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN16rr, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN32ri, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN32rr, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN8ri, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 #endif }, { X86_IN8rr, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 #endif }, { X86_INC16m, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC16r, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC16r_alt, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INC32m, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC32r, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC32r_alt, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INC64m, X86_INS_INC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC64r, X86_INS_INC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC8m, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC8r, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INCSSPD, X86_INS_INCSSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_INCSSPQ, X86_INS_INCSSPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_INSB, X86_INS_INSB, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_INSERTPSrm, X86_INS_INSERTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_INSERTPSrr, X86_INS_INSERTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_INSERTQ, X86_INS_INSERTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 #endif }, { X86_INSERTQI, X86_INS_INSERTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 #endif }, { X86_INSL, X86_INS_INSD, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_INSW, X86_INS_INSW, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_INT, X86_INS_INT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_INT1, X86_INS_INT1, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_INT3, X86_INS_INT3, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_INTO, X86_INS_INTO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_INT, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVD, X86_INS_INVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_INVEPT32, X86_INS_INVEPT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVEPT64, X86_INS_INVEPT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_INVLPG, X86_INS_INVLPG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_INVLPGA32, X86_INS_INVLPGA, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVLPGA64, X86_INS_INVLPGA, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_INVPCID32, X86_INS_INVPCID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVPCID64, X86_INS_INVPCID, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_INVVPID32, X86_INS_INVVPID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVVPID64, X86_INS_INVVPID, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_IRET16, X86_INS_IRET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_IRET32, X86_INS_IRETD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_IRET64, X86_INS_IRETQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_ISTT_FP16m, X86_INS_FISTTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ISTT_FP32m, X86_INS_FISTTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ISTT_FP64m, X86_INS_FISTTP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ISTT_Fp16m32, X86_INS_FISTTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp16m64, X86_INS_FISTTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp16m80, X86_INS_FISTTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp32m32, X86_INS_FISTTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp32m64, X86_INS_FISTTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp32m80, X86_INS_FISTTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp64m32, X86_INS_FISTTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp64m64, X86_INS_FISTTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ISTT_Fp64m80, X86_INS_FISTTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_F16m, X86_INS_FIST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_IST_F32m, X86_INS_FIST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_IST_FP16m, X86_INS_FISTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_IST_FP32m, X86_INS_FISTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_IST_FP64m, X86_INS_FISTP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_IST_Fp16m32, X86_INS_FISTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp16m64, X86_INS_FISTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp16m80, X86_INS_FISTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp32m32, X86_INS_FISTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp32m64, X86_INS_FISTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp32m80, X86_INS_FISTP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp64m32, X86_INS_FISTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp64m64, X86_INS_FISTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_IST_Fp64m80, X86_INS_FISTP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JAE_1, X86_INS_JAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JAE_2, X86_INS_JAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JAE_4, X86_INS_JAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JA_1, X86_INS_JA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JA_2, X86_INS_JA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JA_4, X86_INS_JA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JBE_1, X86_INS_JBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JBE_2, X86_INS_JBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JBE_4, X86_INS_JBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JB_1, X86_INS_JB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JB_2, X86_INS_JB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JB_4, X86_INS_JB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JCXZ, X86_INS_JCXZ, 0, #ifndef CAPSTONE_DIET { X86_REG_CX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JECXZ, X86_INS_JECXZ, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JE_1, X86_INS_JE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JE_2, X86_INS_JE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JE_4, X86_INS_JE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JGE_1, X86_INS_JGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JGE_2, X86_INS_JGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JGE_4, X86_INS_JGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JG_1, X86_INS_JG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JG_2, X86_INS_JG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JG_4, X86_INS_JG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JLE_1, X86_INS_JLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JLE_2, X86_INS_JLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JLE_4, X86_INS_JLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JL_1, X86_INS_JL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JL_2, X86_INS_JL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JL_4, X86_INS_JL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JMP16m, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP16m_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP16r, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP16r_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP32m, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP32m_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP32r, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP32r_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP64m, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 #endif }, { X86_JMP64m_NT, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP64r, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 #endif }, { X86_JMP64r_NT, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP_1, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JMP_2, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JMP_4, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNE_1, X86_INS_JNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNE_2, X86_INS_JNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNE_4, X86_INS_JNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNO_1, X86_INS_JNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNO_2, X86_INS_JNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNO_4, X86_INS_JNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNP_1, X86_INS_JNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNP_2, X86_INS_JNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNP_4, X86_INS_JNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNS_1, X86_INS_JNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNS_2, X86_INS_JNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JNS_4, X86_INS_JNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JO_1, X86_INS_JO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JO_2, X86_INS_JO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JO_4, X86_INS_JO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JP_1, X86_INS_JP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JP_2, X86_INS_JP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JP_4, X86_INS_JP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JRCXZ, X86_INS_JRCXZ, 0, #ifndef CAPSTONE_DIET { X86_REG_RCX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JS_1, X86_INS_JS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JS_2, X86_INS_JS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_JS_4, X86_INS_JS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, { X86_KADDBrr, X86_INS_KADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KADDDrr, X86_INS_KADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KADDQrr, X86_INS_KADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KADDWrr, X86_INS_KADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KANDBrr, X86_INS_KANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KANDDrr, X86_INS_KANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KANDNBrr, X86_INS_KANDNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KANDNDrr, X86_INS_KANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KANDNQrr, X86_INS_KANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KANDNWrr, X86_INS_KANDNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KANDQrr, X86_INS_KANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KANDWrr, X86_INS_KANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KMOVBkk, X86_INS_KMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KMOVBkm, X86_INS_KMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KMOVBkr, X86_INS_KMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KMOVBmk, X86_INS_KMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KMOVBrk, X86_INS_KMOVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KMOVDkk, X86_INS_KMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVDkm, X86_INS_KMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVDkr, X86_INS_KMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVDmk, X86_INS_KMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVDrk, X86_INS_KMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVQkk, X86_INS_KMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVQkm, X86_INS_KMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVQkr, X86_INS_KMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVQmk, X86_INS_KMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVQrk, X86_INS_KMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KMOVWkk, X86_INS_KMOVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KMOVWkm, X86_INS_KMOVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KMOVWkr, X86_INS_KMOVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KMOVWmk, X86_INS_KMOVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KMOVWrk, X86_INS_KMOVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KNOTBrr, X86_INS_KNOTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KNOTDrr, X86_INS_KNOTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KNOTQrr, X86_INS_KNOTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KNOTWrr, X86_INS_KNOTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KORBrr, X86_INS_KORB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KORDrr, X86_INS_KORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KORQrr, X86_INS_KORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KORTESTBrr, X86_INS_KORTESTB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KORTESTDrr, X86_INS_KORTESTD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KORTESTQrr, X86_INS_KORTESTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KORTESTWrr, X86_INS_KORTESTW, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KORWrr, X86_INS_KORW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KSHIFTLBri, X86_INS_KSHIFTLB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KSHIFTLDri, X86_INS_KSHIFTLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KSHIFTLQri, X86_INS_KSHIFTLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KSHIFTLWri, X86_INS_KSHIFTLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KSHIFTRBri, X86_INS_KSHIFTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KSHIFTRDri, X86_INS_KSHIFTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KSHIFTRQri, X86_INS_KSHIFTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KSHIFTRWri, X86_INS_KSHIFTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KTESTBrr, X86_INS_KTESTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KTESTDrr, X86_INS_KTESTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KTESTQrr, X86_INS_KTESTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KTESTWrr, X86_INS_KTESTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KUNPCKBWrr, X86_INS_KUNPCKBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KUNPCKDQrr, X86_INS_KUNPCKDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KUNPCKWDrr, X86_INS_KUNPCKWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_KXNORBrr, X86_INS_KXNORB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KXNORDrr, X86_INS_KXNORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KXNORQrr, X86_INS_KXNORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KXNORWrr, X86_INS_KXNORW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_KXORBrr, X86_INS_KXORB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_KXORDrr, X86_INS_KXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KXORQrr, X86_INS_KXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_KXORWrr, X86_INS_KXORW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_LAHF, X86_INS_LAHF, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_AH, 0 }, { 0 }, 0, 0 #endif }, { X86_LAR16rm, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR16rr, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR32rm, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR32rr, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR64rm, X86_INS_LAR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR64rr, X86_INS_LAR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LDDQUrm, X86_INS_LDDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_LDMXCSR, X86_INS_LDMXCSR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_LDS16rm, X86_INS_LDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LDS32rm, X86_INS_LDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_F0, X86_INS_FLDZ, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_LD_F1, X86_INS_FLD1, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_LD_F32m, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_LD_F64m, X86_INS_FLD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_LD_F80m, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_LD_Fp032, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp064, X86_INS_FLD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp080, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp132, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp164, X86_INS_FLD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp180, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp32m, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp32m64, X86_INS_FLD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp32m80, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp64m, X86_INS_FLD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp64m80, X86_INS_FLD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Fp80m, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LD_Frr, X86_INS_FLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_LEA16r, X86_INS_LEA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LEA32r, X86_INS_LEA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LEA64_32r, X86_INS_LEA, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LEA64r, X86_INS_LEA, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LEAVE, X86_INS_LEAVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LEAVE64, X86_INS_LEAVE, 1, #ifndef CAPSTONE_DIET { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LES16rm, X86_INS_LES, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LES32rm, X86_INS_LES, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LFENCE, X86_INS_LFENCE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_LFS16rm, X86_INS_LFS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LFS32rm, X86_INS_LFS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LFS64rm, X86_INS_LFS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LGDT16m, X86_INS_LGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LGDT32m, X86_INS_LGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LGDT64m, X86_INS_LGDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LGS16rm, X86_INS_LGS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LGS32rm, X86_INS_LGS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LGS64rm, X86_INS_LGS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LIDT16m, X86_INS_LIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LIDT32m, X86_INS_LIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LIDT64m, X86_INS_LIDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LLDT16m, X86_INS_LLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LLDT16r, X86_INS_LLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LLWPCB, X86_INS_LLWPCB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LLWPCB64, X86_INS_LLWPCB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LMSW16m, X86_INS_LMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LMSW16r, X86_INS_LMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LOCK_PREFIX, X86_INS_LOCK, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LODSB, X86_INS_LODSB, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AL, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LODSL, X86_INS_LODSD, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LODSQ, X86_INS_LODSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_RAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LODSW, X86_INS_LODSW, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AX, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LOOP, X86_INS_LOOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 #endif }, { X86_LOOPE, X86_INS_LOOPE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 #endif }, { X86_LOOPNE, X86_INS_LOOPNE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0 #endif }, { X86_LRETIL, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LRETIQ, X86_INS_RETFQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LRETIW, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LRETL, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LRETQ, X86_INS_RETFQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LRETW, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LSL16rm, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL16rr, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL32rm, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL32rr, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL64rm, X86_INS_LSL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL64rr, X86_INS_LSL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSS16rm, X86_INS_LSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSS32rm, X86_INS_LSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSS64rm, X86_INS_LSS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LTRm, X86_INS_LTR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LTRr, X86_INS_LTR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LWPINS32rmi, X86_INS_LWPINS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPINS32rri, X86_INS_LWPINS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPINS64rmi, X86_INS_LWPINS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPINS64rri, X86_INS_LWPINS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL32rmi, X86_INS_LWPVAL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL32rri, X86_INS_LWPVAL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL64rmi, X86_INS_LWPVAL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL64rri, X86_INS_LWPVAL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT16rm, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT16rr, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT32rm, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT32rr, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT64rm, X86_INS_LZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT64rr, X86_INS_LZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MASKMOVDQU, X86_INS_MASKMOVDQU, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MASKMOVDQU64, X86_INS_MASKMOVDQU, 1, #ifndef CAPSTONE_DIET { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_SSE2, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MAXCPDrm, X86_INS_MAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXCPDrr, X86_INS_MAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXCPSrm, X86_INS_MAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXCPSrr, X86_INS_MAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXCSDrm, X86_INS_MAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXCSDrr, X86_INS_MAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXCSSrm, X86_INS_MAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXCSSrr, X86_INS_MAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXPDrm, X86_INS_MAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXPDrr, X86_INS_MAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXPSrm, X86_INS_MAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXPSrr, X86_INS_MAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXSDrm, X86_INS_MAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXSDrm_Int, X86_INS_MAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXSDrr, X86_INS_MAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXSDrr_Int, X86_INS_MAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MAXSSrm, X86_INS_MAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXSSrm_Int, X86_INS_MAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXSSrr, X86_INS_MAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MAXSSrr_Int, X86_INS_MAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MFENCE, X86_INS_MFENCE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINCPDrm, X86_INS_MINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINCPDrr, X86_INS_MINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINCPSrm, X86_INS_MINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINCPSrr, X86_INS_MINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINCSDrm, X86_INS_MINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINCSDrr, X86_INS_MINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINCSSrm, X86_INS_MINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINCSSrr, X86_INS_MINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINPDrm, X86_INS_MINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINPDrr, X86_INS_MINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINPSrm, X86_INS_MINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINPSrr, X86_INS_MINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINSDrm, X86_INS_MINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINSDrm_Int, X86_INS_MINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINSDrr, X86_INS_MINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINSDrr_Int, X86_INS_MINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MINSSrm, X86_INS_MINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINSSrm_Int, X86_INS_MINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINSSrr, X86_INS_MINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MINSSrr_Int, X86_INS_MINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_CVTPD2PIirm, X86_INS_CVTPD2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_CVTPD2PIirr, X86_INS_CVTPD2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_CVTPI2PDirm, X86_INS_CVTPI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_CVTPI2PDirr, X86_INS_CVTPI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_CVTPI2PSirm, X86_INS_CVTPI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_CVTPI2PSirr, X86_INS_CVTPI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_CVTPS2PIirm, X86_INS_CVTPS2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_CVTPS2PIirr, X86_INS_CVTPS2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_CVTTPD2PIirm, X86_INS_CVTTPD2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_CVTTPD2PIirr, X86_INS_CVTTPD2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_CVTTPS2PIirm, X86_INS_CVTTPS2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_CVTTPS2PIirr, X86_INS_CVTTPS2PI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MMX_EMMS, X86_INS_EMMS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MASKMOVQ, X86_INS_MASKMOVQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MMX_MASKMOVQ64, X86_INS_MASKMOVQ, 1, #ifndef CAPSTONE_DIET { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_MMX, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64from64rm, X86_INS_MOVD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64from64rr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64grr, X86_INS_MOVD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64mr, X86_INS_MOVD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64rm, X86_INS_MOVD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64rr, X86_INS_MOVD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64to64rm, X86_INS_MOVD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVD64to64rr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVDQ2Qrr, X86_INS_MOVDQ2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_MOVFR642Qrr, X86_INS_MOVDQ2Q, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_MOVNTQmr, X86_INS_MOVNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVQ2DQrr, X86_INS_MOVQ2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_MOVQ2FR64rr, X86_INS_MOVQ2DQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MMX_MOVQ64mr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVQ64rm, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVQ64rr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_MOVQ64rr_REV, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PABSBrm, X86_INS_PABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PABSBrr, X86_INS_PABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PABSDrm, X86_INS_PABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PABSDrr, X86_INS_PABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PABSWrm, X86_INS_PABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PABSWrr, X86_INS_PABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PACKSSDWirm, X86_INS_PACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PACKSSDWirr, X86_INS_PACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PACKSSWBirm, X86_INS_PACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PACKSSWBirr, X86_INS_PACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PACKUSWBirm, X86_INS_PACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PACKUSWBirr, X86_INS_PACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDBirm, X86_INS_PADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDBirr, X86_INS_PADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDDirm, X86_INS_PADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDDirr, X86_INS_PADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDQirm, X86_INS_PADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDQirr, X86_INS_PADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDSBirm, X86_INS_PADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDSBirr, X86_INS_PADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDSWirm, X86_INS_PADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDSWirr, X86_INS_PADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDUSBirm, X86_INS_PADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDUSBirr, X86_INS_PADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDUSWirm, X86_INS_PADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDUSWirr, X86_INS_PADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDWirm, X86_INS_PADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PADDWirr, X86_INS_PADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PALIGNRrmi, X86_INS_PALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PALIGNRrri, X86_INS_PALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PANDNirm, X86_INS_PANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PANDNirr, X86_INS_PANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PANDirm, X86_INS_PAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PANDirr, X86_INS_PAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PAVGBirm, X86_INS_PAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PAVGBirr, X86_INS_PAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PAVGWirm, X86_INS_PAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PAVGWirr, X86_INS_PAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPEQBirm, X86_INS_PCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPEQBirr, X86_INS_PCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPEQDirm, X86_INS_PCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPEQDirr, X86_INS_PCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPEQWirm, X86_INS_PCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPEQWirr, X86_INS_PCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPGTBirm, X86_INS_PCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPGTBirr, X86_INS_PCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPGTDirm, X86_INS_PCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPGTDirr, X86_INS_PCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPGTWirm, X86_INS_PCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PCMPGTWirr, X86_INS_PCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PEXTRWrr, X86_INS_PEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHADDDrm, X86_INS_PHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHADDDrr, X86_INS_PHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHADDSWrm, X86_INS_PHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHADDSWrr, X86_INS_PHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHADDWrm, X86_INS_PHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHADDWrr, X86_INS_PHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHSUBDrm, X86_INS_PHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHSUBDrr, X86_INS_PHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHSUBSWrm, X86_INS_PHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHSUBSWrr, X86_INS_PHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHSUBWrm, X86_INS_PHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PHSUBWrr, X86_INS_PHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PINSRWrm, X86_INS_PINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PINSRWrr, X86_INS_PINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PMADDUBSWrm, X86_INS_PMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PMADDUBSWrr, X86_INS_PMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PMADDWDirm, X86_INS_PMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMADDWDirr, X86_INS_PMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMAXSWirm, X86_INS_PMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMAXSWirr, X86_INS_PMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMAXUBirm, X86_INS_PMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMAXUBirr, X86_INS_PMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMINSWirm, X86_INS_PMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMINSWirr, X86_INS_PMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMINUBirm, X86_INS_PMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMINUBirr, X86_INS_PMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMOVMSKBrr, X86_INS_PMOVMSKB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULHRSWrm, X86_INS_PMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PMULHRSWrr, X86_INS_PMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PMULHUWirm, X86_INS_PMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULHUWirr, X86_INS_PMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULHWirm, X86_INS_PMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULHWirr, X86_INS_PMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULLWirm, X86_INS_PMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULLWirr, X86_INS_PMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULUDQirm, X86_INS_PMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PMULUDQirr, X86_INS_PMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PORirm, X86_INS_POR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PORirr, X86_INS_POR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSADBWirm, X86_INS_PSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSADBWirr, X86_INS_PSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSHUFBrm, X86_INS_PSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSHUFBrr, X86_INS_PSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSHUFWmi, X86_INS_PSHUFW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSHUFWri, X86_INS_PSHUFW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSIGNBrm, X86_INS_PSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSIGNBrr, X86_INS_PSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSIGNDrm, X86_INS_PSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSIGNDrr, X86_INS_PSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSIGNWrm, X86_INS_PSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSIGNWrr, X86_INS_PSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MMX_PSLLDri, X86_INS_PSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLDrm, X86_INS_PSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLDrr, X86_INS_PSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLQri, X86_INS_PSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLQrm, X86_INS_PSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLQrr, X86_INS_PSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLWri, X86_INS_PSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLWrm, X86_INS_PSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSLLWrr, X86_INS_PSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRADri, X86_INS_PSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRADrm, X86_INS_PSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRADrr, X86_INS_PSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRAWri, X86_INS_PSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRAWrm, X86_INS_PSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRAWrr, X86_INS_PSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLDri, X86_INS_PSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLDrm, X86_INS_PSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLDrr, X86_INS_PSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLQri, X86_INS_PSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLQrm, X86_INS_PSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLQrr, X86_INS_PSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLWri, X86_INS_PSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLWrm, X86_INS_PSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSRLWrr, X86_INS_PSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBBirm, X86_INS_PSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBBirr, X86_INS_PSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBDirm, X86_INS_PSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBDirr, X86_INS_PSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBQirm, X86_INS_PSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBQirr, X86_INS_PSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBSBirm, X86_INS_PSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBSBirr, X86_INS_PSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBSWirm, X86_INS_PSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBSWirr, X86_INS_PSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBUSBirm, X86_INS_PSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBUSBirr, X86_INS_PSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBUSWirm, X86_INS_PSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBUSWirr, X86_INS_PSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBWirm, X86_INS_PSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PSUBWirr, X86_INS_PSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKHBWirm, X86_INS_PUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKHBWirr, X86_INS_PUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKHDQirm, X86_INS_PUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKHDQirr, X86_INS_PUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKHWDirm, X86_INS_PUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKHWDirr, X86_INS_PUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKLBWirm, X86_INS_PUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKLBWirr, X86_INS_PUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKLDQirm, X86_INS_PUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKLDQirr, X86_INS_PUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKLWDirm, X86_INS_PUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PUNPCKLWDirr, X86_INS_PUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PXORirm, X86_INS_PXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MMX_PXORirr, X86_INS_PXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MMX, 0 }, 0, 0 #endif }, { X86_MONITORXrrr, X86_INS_MONITORX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MONITORrrr, X86_INS_MONITOR, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MONTMUL, X86_INS_MONTMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RSI, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_RSI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ao16, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ao32, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16mi, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16mr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ms, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16o16a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16o32a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ri, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ri_alt, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rr_REV, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rs, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16sm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV16sr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV32ao16, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32ao32, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32cr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32dr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32mi, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32mr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32o16a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32o32a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rc, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32rd, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32ri, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32ri_alt, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rr_REV, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rs, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32sr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV64ao32, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64cr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64dr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64mi32, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64mr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64o32a, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rc, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64rd, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64ri, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64ri32, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rm, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rr_REV, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rs, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64sr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV64toPQIrm, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOV64toPQIrr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOV64toSDrm, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOV64toSDrr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOV8ao16, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ao32, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8mi, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8mr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8mr_NOREX, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8o16a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8o32a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ri, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ri_alt, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rm_NOREX, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rr_NOREX, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rr_REV, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVAPDmr, X86_INS_MOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVAPDrm, X86_INS_MOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVAPDrr, X86_INS_MOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVAPDrr_REV, X86_INS_MOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVAPSmr, X86_INS_MOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVAPSrm, X86_INS_MOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVAPSrr, X86_INS_MOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVAPSrr_REV, X86_INS_MOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVBE16mr, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE16rm, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE32mr, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE32rm, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE64mr, X86_INS_MOVBE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE64rm, X86_INS_MOVBE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDDUPrm, X86_INS_MOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MOVDDUPrr, X86_INS_MOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MOVDI2PDIrm, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDI2PDIrr, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDI2SSrm, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDI2SSrr, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDIR64B16, X86_INS_MOVDIR64B, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIR64B32, X86_INS_MOVDIR64B, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIR64B64, X86_INS_MOVDIR64B, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIRI32, X86_INS_MOVDIRI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIRI64, X86_INS_MOVDIRI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDQAmr, X86_INS_MOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQArm, X86_INS_MOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQArr, X86_INS_MOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQArr_REV, X86_INS_MOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQUmr, X86_INS_MOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQUrm, X86_INS_MOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQUrr, X86_INS_MOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVDQUrr_REV, X86_INS_MOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVHLPSrr, X86_INS_MOVHLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVHPDmr, X86_INS_MOVHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVHPDrm, X86_INS_MOVHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVHPSmr, X86_INS_MOVHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVHPSrm, X86_INS_MOVHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVLHPSrr, X86_INS_MOVLHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVLPDmr, X86_INS_MOVLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVLPDrm, X86_INS_MOVLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVLPSmr, X86_INS_MOVLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVLPSrm, X86_INS_MOVLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVMSKPDrr, X86_INS_MOVMSKPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVMSKPSrr, X86_INS_MOVMSKPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVNTDQArm, X86_INS_MOVNTDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_MOVNTDQmr, X86_INS_MOVNTDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVNTI_64mr, X86_INS_MOVNTI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVNTImr, X86_INS_MOVNTI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVNTPDmr, X86_INS_MOVNTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVNTPSmr, X86_INS_MOVNTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVNTSD, X86_INS_MOVNTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 #endif }, { X86_MOVNTSS, X86_INS_MOVNTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 #endif }, { X86_MOVPDI2DImr, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVPDI2DIrr, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVPQI2QImr, X86_INS_MOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVPQI2QIrr, X86_INS_MOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVPQIto64mr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVPQIto64rr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVQI2PQIrm, X86_INS_MOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSB, X86_INS_MOVSB, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSDmr, X86_INS_MOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSDrm, X86_INS_MOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSDrr, X86_INS_MOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSDrr_REV, X86_INS_MOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSDto64mr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSDto64rr, X86_INS_MOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSHDUPrm, X86_INS_MOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MOVSHDUPrr, X86_INS_MOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MOVSL, X86_INS_MOVSD, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSLDUPrm, X86_INS_MOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MOVSLDUPrr, X86_INS_MOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_MOVSQ, X86_INS_MOVSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSS2DImr, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSS2DIrr, X86_INS_MOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVSSmr, X86_INS_MOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVSSrm, X86_INS_MOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVSSrr, X86_INS_MOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVSSrr_REV, X86_INS_MOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVSW, X86_INS_MOVSW, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rm16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rm8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rr16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rr8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rm16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rm8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rm8_NOREX, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rr16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rr8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rr8_NOREX, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rm16, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rm32, X86_INS_MOVSXD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOVSX64rm8, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rr16, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rr32, X86_INS_MOVSXD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOVSX64rr8, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVUPDmr, X86_INS_MOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVUPDrm, X86_INS_MOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVUPDrr, X86_INS_MOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVUPDrr_REV, X86_INS_MOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVUPSmr, X86_INS_MOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVUPSrm, X86_INS_MOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVUPSrr, X86_INS_MOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVUPSrr_REV, X86_INS_MOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MOVZPQILo2PQIrr, X86_INS_MOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MOVZX16rm16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rm8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rr16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rr8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rm16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rm8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rm8_NOREX, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rr16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rr8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rr8_NOREX, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rm16, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rm8, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rr16, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rr8, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MPSADBWrmi, X86_INS_MPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_MPSADBWrri, X86_INS_MPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_MUL16m, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL16r, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL32m, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL32r, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL64m, X86_INS_MUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL64r, X86_INS_MUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL8m, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL8r, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_MULPDrm, X86_INS_MULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MULPDrr, X86_INS_MULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MULPSrm, X86_INS_MULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MULPSrr, X86_INS_MULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MULSDrm, X86_INS_MULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MULSDrm_Int, X86_INS_MULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MULSDrr, X86_INS_MULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MULSDrr_Int, X86_INS_MULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_MULSSrm, X86_INS_MULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MULSSrm_Int, X86_INS_MULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MULSSrr, X86_INS_MULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MULSSrr_Int, X86_INS_MULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_MULX32rm, X86_INS_MULX, 0, #ifndef CAPSTONE_DIET { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MULX32rr, X86_INS_MULX, 0, #ifndef CAPSTONE_DIET { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MULX64rm, X86_INS_MULX, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MULX64rr, X86_INS_MULX, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MUL_F32m, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MUL_F64m, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MUL_FI16m, X86_INS_FIMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MUL_FI32m, X86_INS_FIMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MUL_FPrST0, X86_INS_FMULP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MUL_FST0r, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MUL_Fp32, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp32m, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp64, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp64m, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp64m32, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp80, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp80m32, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_Fp80m64, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FpI16m32, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FpI16m64, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FpI16m80, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FpI32m32, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FpI32m64, X86_INS_FMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FpI32m80, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL_FrST0, X86_INS_FMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_MWAITXrrr, X86_INS_MWAITX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MWAITrr, X86_INS_MWAIT, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, X86_REG_EAX, 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 #endif }, { X86_NEG16m, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG16r, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG32m, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG32r, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG64m, X86_INS_NEG, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG64r, X86_INS_NEG, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG8m, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG8r, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP19rr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL_19, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL_1d, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL_1e, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPLr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPQ, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPQr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_19, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_1c, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_1d, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_1e, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPWr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT16m, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT16r, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT32m, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT32r, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT64m, X86_INS_NOT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT64r, X86_INS_NOT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT8m, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT8r, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OR16i16, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16mi, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16mi8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16mr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16ri, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16ri8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16rm, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16rr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16rr_REV, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32i32, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32mi, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32mi8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32mr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32ri, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32ri8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32rm, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32rr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32rr_REV, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64i32, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64mi32, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64mi8, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64mr, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64ri32, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64ri8, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64rm, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64rr, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64rr_REV, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8i8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8mi, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8mi8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_OR8mr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8ri, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8ri8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_OR8rm, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8rr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8rr_REV, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ORPDrm, X86_INS_ORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ORPDrr, X86_INS_ORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_ORPSrm, X86_INS_ORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_ORPSrr, X86_INS_ORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_OUT16ir, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT16rr, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT32ir, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT32rr, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT8ir, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT8rr, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUTSB, X86_INS_OUTSB, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_OUTSL, X86_INS_OUTSD, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_OUTSW, X86_INS_OUTSW, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_PABSBrm, X86_INS_PABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PABSBrr, X86_INS_PABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PABSDrm, X86_INS_PABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PABSDrr, X86_INS_PABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PABSWrm, X86_INS_PABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PABSWrr, X86_INS_PABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PACKSSDWrm, X86_INS_PACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PACKSSDWrr, X86_INS_PACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PACKSSWBrm, X86_INS_PACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PACKSSWBrr, X86_INS_PACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PACKUSDWrm, X86_INS_PACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PACKUSDWrr, X86_INS_PACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PACKUSWBrm, X86_INS_PACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PACKUSWBrr, X86_INS_PACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDBrm, X86_INS_PADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDBrr, X86_INS_PADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDDrm, X86_INS_PADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDDrr, X86_INS_PADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDQrm, X86_INS_PADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDQrr, X86_INS_PADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDSBrm, X86_INS_PADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDSBrr, X86_INS_PADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDSWrm, X86_INS_PADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDSWrr, X86_INS_PADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDUSBrm, X86_INS_PADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDUSBrr, X86_INS_PADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDUSWrm, X86_INS_PADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDUSWrr, X86_INS_PADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDWrm, X86_INS_PADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PADDWrr, X86_INS_PADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PALIGNRrmi, X86_INS_PALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PALIGNRrri, X86_INS_PALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PANDNrm, X86_INS_PANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PANDNrr, X86_INS_PANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PANDrm, X86_INS_PAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PANDrr, X86_INS_PAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PAUSE, X86_INS_PAUSE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PAVGBrm, X86_INS_PAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PAVGBrr, X86_INS_PAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PAVGUSBrm, X86_INS_PAVGUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PAVGUSBrr, X86_INS_PAVGUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PAVGWrm, X86_INS_PAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PAVGWrr, X86_INS_PAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PBLENDVBrm0, X86_INS_PBLENDVB, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PBLENDVBrr0, X86_INS_PBLENDVB, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PBLENDWrmi, X86_INS_PBLENDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PBLENDWrri, X86_INS_PBLENDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PCLMULQDQrm, X86_INS_PCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0 #endif }, { X86_PCLMULQDQrr, X86_INS_PCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PCLMUL, 0 }, 0, 0 #endif }, { X86_PCMPEQBrm, X86_INS_PCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPEQBrr, X86_INS_PCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPEQDrm, X86_INS_PCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPEQDrr, X86_INS_PCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPEQQrm, X86_INS_PCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PCMPEQQrr, X86_INS_PCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PCMPEQWrm, X86_INS_PCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPEQWrr, X86_INS_PCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPESTRIrm, X86_INS_PCMPESTRI, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_PCMPESTRIrr, X86_INS_PCMPESTRI, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_PCMPESTRMrm, X86_INS_PCMPESTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PCMPESTRMrr, X86_INS_PCMPESTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PCMPGTBrm, X86_INS_PCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPGTBrr, X86_INS_PCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPGTDrm, X86_INS_PCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPGTDrr, X86_INS_PCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPGTQrm, X86_INS_PCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_PCMPGTQrr, X86_INS_PCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_PCMPGTWrm, X86_INS_PCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPGTWrr, X86_INS_PCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PCMPISTRIrm, X86_INS_PCMPISTRI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_PCMPISTRIrr, X86_INS_PCMPISTRI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_SSE42, 0 }, 0, 0 #endif }, { X86_PCMPISTRMrm, X86_INS_PCMPISTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PCMPISTRMrr, X86_INS_PCMPISTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PCONFIG, X86_INS_PCONFIG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PDEP32rm, X86_INS_PDEP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PDEP32rr, X86_INS_PDEP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PDEP64rm, X86_INS_PDEP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PDEP64rr, X86_INS_PDEP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT32rm, X86_INS_PEXT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT32rr, X86_INS_PEXT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT64rm, X86_INS_PEXT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT64rr, X86_INS_PEXT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXTRBmr, X86_INS_PEXTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRBrr, X86_INS_PEXTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRDmr, X86_INS_PEXTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRDrr, X86_INS_PEXTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRQmr, X86_INS_PEXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRQrr, X86_INS_PEXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRWmr, X86_INS_PEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PEXTRWrr, X86_INS_PEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PEXTRWrr_REV, X86_INS_PEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PF2IDrm, X86_INS_PF2ID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PF2IDrr, X86_INS_PF2ID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PF2IWrm, X86_INS_PF2IW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PF2IWrr, X86_INS_PF2IW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFACCrm, X86_INS_PFACC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFACCrr, X86_INS_PFACC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFADDrm, X86_INS_PFADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFADDrr, X86_INS_PFADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFCMPEQrm, X86_INS_PFCMPEQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFCMPEQrr, X86_INS_PFCMPEQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFCMPGErm, X86_INS_PFCMPGE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFCMPGErr, X86_INS_PFCMPGE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFCMPGTrm, X86_INS_PFCMPGT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFCMPGTrr, X86_INS_PFCMPGT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFMAXrm, X86_INS_PFMAX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFMAXrr, X86_INS_PFMAX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFMINrm, X86_INS_PFMIN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFMINrr, X86_INS_PFMIN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFMULrm, X86_INS_PFMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFMULrr, X86_INS_PFMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFNACCrm, X86_INS_PFNACC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFNACCrr, X86_INS_PFNACC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFPNACCrm, X86_INS_PFPNACC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFPNACCrr, X86_INS_PFPNACC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRCPIT1rm, X86_INS_PFRCPIT1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRCPIT1rr, X86_INS_PFRCPIT1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRCPIT2rm, X86_INS_PFRCPIT2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRCPIT2rr, X86_INS_PFRCPIT2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRCPrm, X86_INS_PFRCP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRCPrr, X86_INS_PFRCP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRSQIT1rm, X86_INS_PFRSQIT1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRSQIT1rr, X86_INS_PFRSQIT1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRSQRTrm, X86_INS_PFRSQRT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFRSQRTrr, X86_INS_PFRSQRT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFSUBRrm, X86_INS_PFSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFSUBRrr, X86_INS_PFSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFSUBrm, X86_INS_PFSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PFSUBrr, X86_INS_PFSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PHADDDrm, X86_INS_PHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHADDDrr, X86_INS_PHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHADDSWrm, X86_INS_PHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PHADDSWrr, X86_INS_PHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PHADDWrm, X86_INS_PHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHADDWrr, X86_INS_PHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHMINPOSUWrm, X86_INS_PHMINPOSUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PHMINPOSUWrr, X86_INS_PHMINPOSUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PHSUBDrm, X86_INS_PHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHSUBDrr, X86_INS_PHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHSUBSWrm, X86_INS_PHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PHSUBSWrr, X86_INS_PHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PHSUBWrm, X86_INS_PHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PHSUBWrr, X86_INS_PHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PI2FDrm, X86_INS_PI2FD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PI2FDrr, X86_INS_PI2FD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PI2FWrm, X86_INS_PI2FW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PI2FWrr, X86_INS_PI2FW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PINSRBrm, X86_INS_PINSRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PINSRBrr, X86_INS_PINSRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PINSRDrm, X86_INS_PINSRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PINSRDrr, X86_INS_PINSRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PINSRQrm, X86_INS_PINSRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PINSRQrr, X86_INS_PINSRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PINSRWrm, X86_INS_PINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PINSRWrr, X86_INS_PINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PMADDUBSWrm, X86_INS_PMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PMADDUBSWrr, X86_INS_PMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PMADDWDrm, X86_INS_PMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMADDWDrr, X86_INS_PMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMAXSBrm, X86_INS_PMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXSBrr, X86_INS_PMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXSDrm, X86_INS_PMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXSDrr, X86_INS_PMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXSWrm, X86_INS_PMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMAXSWrr, X86_INS_PMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMAXUBrm, X86_INS_PMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMAXUBrr, X86_INS_PMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMAXUDrm, X86_INS_PMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXUDrr, X86_INS_PMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXUWrm, X86_INS_PMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMAXUWrr, X86_INS_PMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINSBrm, X86_INS_PMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINSBrr, X86_INS_PMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINSDrm, X86_INS_PMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINSDrr, X86_INS_PMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINSWrm, X86_INS_PMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMINSWrr, X86_INS_PMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMINUBrm, X86_INS_PMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMINUBrr, X86_INS_PMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMINUDrm, X86_INS_PMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINUDrr, X86_INS_PMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINUWrm, X86_INS_PMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMINUWrr, X86_INS_PMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVMSKBrr, X86_INS_PMOVMSKB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMOVSXBDrm, X86_INS_PMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXBDrr, X86_INS_PMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXBQrm, X86_INS_PMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXBQrr, X86_INS_PMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXBWrm, X86_INS_PMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXBWrr, X86_INS_PMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXDQrm, X86_INS_PMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXDQrr, X86_INS_PMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXWDrm, X86_INS_PMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXWDrr, X86_INS_PMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXWQrm, X86_INS_PMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVSXWQrr, X86_INS_PMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXBDrm, X86_INS_PMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXBDrr, X86_INS_PMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXBQrm, X86_INS_PMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXBQrr, X86_INS_PMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXBWrm, X86_INS_PMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXBWrr, X86_INS_PMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXDQrm, X86_INS_PMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXDQrr, X86_INS_PMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXWDrm, X86_INS_PMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXWDrr, X86_INS_PMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXWQrm, X86_INS_PMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMOVZXWQrr, X86_INS_PMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMULDQrm, X86_INS_PMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMULDQrr, X86_INS_PMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMULHRSWrm, X86_INS_PMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PMULHRSWrr, X86_INS_PMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PMULHRWrm, X86_INS_PMULHRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PMULHRWrr, X86_INS_PMULHRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PMULHUWrm, X86_INS_PMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULHUWrr, X86_INS_PMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULHWrm, X86_INS_PMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULHWrr, X86_INS_PMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULLDrm, X86_INS_PMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMULLDrr, X86_INS_PMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PMULLWrm, X86_INS_PMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULLWrr, X86_INS_PMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULUDQrm, X86_INS_PMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PMULUDQrr, X86_INS_PMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_POP16r, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_POP16rmm, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_POP16rmr, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_POP32r, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POP32rmm, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POP32rmr, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POP64r, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POP64rmm, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POP64rmr, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPA16, X86_INS_POPAW, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPA32, X86_INS_POPAL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPCNT16rm, X86_INS_POPCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPCNT16rr, X86_INS_POPCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPCNT32rm, X86_INS_POPCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPCNT32rr, X86_INS_POPCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPCNT64rm, X86_INS_POPCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPCNT64rr, X86_INS_POPCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPDS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPDS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPES16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPES32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPF16, X86_INS_POPF, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPF32, X86_INS_POPFD, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPF64, X86_INS_POPFQ, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPFS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_POPFS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPFS64, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPGS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_POPGS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPGS64, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPSS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPSS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PORrm, X86_INS_POR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PORrr, X86_INS_POR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PREFETCH, X86_INS_PREFETCH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PREFETCHNTA, X86_INS_PREFETCHNTA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_PREFETCHT0, X86_INS_PREFETCHT0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_PREFETCHT1, X86_INS_PREFETCHT1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_PREFETCHT2, X86_INS_PREFETCHT2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_PREFETCHW, X86_INS_PREFETCHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PREFETCHWT1, X86_INS_PREFETCHWT1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PSADBWrm, X86_INS_PSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSADBWrr, X86_INS_PSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSHUFBrm, X86_INS_PSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSHUFBrr, X86_INS_PSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSHUFDmi, X86_INS_PSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSHUFDri, X86_INS_PSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSHUFHWmi, X86_INS_PSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSHUFHWri, X86_INS_PSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSHUFLWmi, X86_INS_PSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSHUFLWri, X86_INS_PSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSIGNBrm, X86_INS_PSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSIGNBrr, X86_INS_PSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSIGNDrm, X86_INS_PSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSIGNDrr, X86_INS_PSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSIGNWrm, X86_INS_PSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSIGNWrr, X86_INS_PSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSSE3, 0 }, 0, 0 #endif }, { X86_PSLLDQri, X86_INS_PSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLDri, X86_INS_PSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLDrm, X86_INS_PSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLDrr, X86_INS_PSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLQri, X86_INS_PSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLQrm, X86_INS_PSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLQrr, X86_INS_PSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLWri, X86_INS_PSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLWrm, X86_INS_PSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSLLWrr, X86_INS_PSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRADri, X86_INS_PSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRADrm, X86_INS_PSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRADrr, X86_INS_PSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRAWri, X86_INS_PSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRAWrm, X86_INS_PSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRAWrr, X86_INS_PSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLDQri, X86_INS_PSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLDri, X86_INS_PSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLDrm, X86_INS_PSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLDrr, X86_INS_PSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLQri, X86_INS_PSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLQrm, X86_INS_PSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLQrr, X86_INS_PSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLWri, X86_INS_PSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLWrm, X86_INS_PSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSRLWrr, X86_INS_PSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBBrm, X86_INS_PSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBBrr, X86_INS_PSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBDrm, X86_INS_PSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBDrr, X86_INS_PSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBQrm, X86_INS_PSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBQrr, X86_INS_PSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBSBrm, X86_INS_PSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBSBrr, X86_INS_PSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBSWrm, X86_INS_PSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBSWrr, X86_INS_PSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBUSBrm, X86_INS_PSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBUSBrr, X86_INS_PSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBUSWrm, X86_INS_PSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBUSWrr, X86_INS_PSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBWrm, X86_INS_PSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSUBWrr, X86_INS_PSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PSWAPDrm, X86_INS_PSWAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PSWAPDrr, X86_INS_PSWAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_3DNOW, 0 }, 0, 0 #endif }, { X86_PTESTrm, X86_INS_PTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PTESTrr, X86_INS_PTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_PTWRITE64m, X86_INS_PTWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PTWRITE64r, X86_INS_PTWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PTWRITEm, X86_INS_PTWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PTWRITEr, X86_INS_PTWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PUNPCKHBWrm, X86_INS_PUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHBWrr, X86_INS_PUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHDQrm, X86_INS_PUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHDQrr, X86_INS_PUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHQDQrm, X86_INS_PUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHQDQrr, X86_INS_PUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHWDrm, X86_INS_PUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKHWDrr, X86_INS_PUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLBWrm, X86_INS_PUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLBWrr, X86_INS_PUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLDQrm, X86_INS_PUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLDQrr, X86_INS_PUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLQDQrm, X86_INS_PUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLQDQrr, X86_INS_PUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLWDrm, X86_INS_PUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUNPCKLWDrr, X86_INS_PUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PUSH16i8, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH16r, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH16rmm, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH16rmr, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH32i8, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH32r, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH32rmm, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH32rmr, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH64i32, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64i8, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64r, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64rmm, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64rmr, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHA16, X86_INS_PUSHAW, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHA32, X86_INS_PUSHAL, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHCS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHCS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHDS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHDS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHES16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHES32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHF16, X86_INS_PUSHF, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSHF32, X86_INS_PUSHFD, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHF64, X86_INS_PUSHFQ, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHFS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PUSHFS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHFS64, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHGS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PUSHGS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHGS64, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHSS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHSS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHi16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHi32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PXORrm, X86_INS_PXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_PXORrr, X86_INS_PXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_RCL16m1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16mCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16mi, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16r1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16rCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16ri, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32m1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32mCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32mi, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32r1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32rCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32ri, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64m1, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64mCL, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64mi, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64r1, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64rCL, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64ri, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8m1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8mCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8mi, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8r1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8rCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8ri, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCPPSm, X86_INS_RCPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RCPPSr, X86_INS_RCPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RCPSSm, X86_INS_RCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RCPSSm_Int, X86_INS_RCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RCPSSr, X86_INS_RCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RCPSSr_Int, X86_INS_RCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16m1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16mCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16mi, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16r1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16rCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16ri, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32m1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32mCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32mi, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32r1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32rCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32ri, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64m1, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64mCL, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64mi, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64r1, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64rCL, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64ri, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8m1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8mCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8mi, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8r1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8rCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8ri, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDFSBASE, X86_INS_RDFSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDFSBASE64, X86_INS_RDFSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDGSBASE, X86_INS_RDGSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDGSBASE64, X86_INS_RDGSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDMSR, X86_INS_RDMSR, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 #endif }, { X86_RDPID32, X86_INS_RDPID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDPID64, X86_INS_RDPID, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDPKRUr, X86_INS_RDPKRU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDPMC, X86_INS_RDPMC, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_RDRAND16r, X86_INS_RDRAND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDRAND32r, X86_INS_RDRAND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDRAND64r, X86_INS_RDRAND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSEED16r, X86_INS_RDSEED, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSEED32r, X86_INS_RDSEED, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSEED64r, X86_INS_RDSEED, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSSPD, X86_INS_RDSSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDSSPQ, X86_INS_RDSSPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDTSC, X86_INS_RDTSC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 #endif }, { X86_RDTSCP, X86_INS_RDTSCP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_REPNE_PREFIX, X86_INS_REPNE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_REP_PREFIX, X86_INS_REP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RETIL, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_RETIQ, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RETIW, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_RETL, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_RETQ, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RETW, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_REX64_PREFIX, X86_INS_REX64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16m1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16mCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16mi, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16r1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16rCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16ri, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32m1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32mCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32mi, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32r1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32rCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32ri, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64m1, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64mCL, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64mi, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64r1, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64rCL, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64ri, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8m1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8mCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8mi, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8r1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8rCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8ri, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16m1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16mCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16mi, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16r1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16rCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16ri, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32m1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32mCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32mi, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32r1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32rCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32ri, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64m1, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64mCL, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64mi, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64r1, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64rCL, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64ri, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8m1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8mCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8mi, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8r1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8rCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8ri, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RORX32mi, X86_INS_RORX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RORX32ri, X86_INS_RORX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RORX64mi, X86_INS_RORX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RORX64ri, X86_INS_RORX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_ROUNDPDm, X86_INS_ROUNDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDPDr, X86_INS_ROUNDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDPSm, X86_INS_ROUNDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDPSr, X86_INS_ROUNDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDSDm, X86_INS_ROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDSDm_Int, X86_INS_ROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ROUNDSDr, X86_INS_ROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDSDr_Int, X86_INS_ROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDSSm, X86_INS_ROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDSSm_Int, X86_INS_ROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ROUNDSSr, X86_INS_ROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_ROUNDSSr_Int, X86_INS_ROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE41, 0 }, 0, 0 #endif }, { X86_RSM, X86_INS_RSM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_RSQRTPSm, X86_INS_RSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RSQRTPSr, X86_INS_RSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RSQRTSSm, X86_INS_RSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RSQRTSSm_Int, X86_INS_RSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RSQRTSSr, X86_INS_RSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_RSQRTSSr_Int, X86_INS_RSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RSTORSSP, X86_INS_RSTORSSP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SAHF, X86_INS_SAHF, 0, #ifndef CAPSTONE_DIET { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16m1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16mCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16mi, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16r1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16rCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16ri, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32m1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32mCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32mi, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32r1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32rCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32ri, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64m1, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64mCL, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64mi, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64r1, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64rCL, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64ri, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8m1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8mCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8mi, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8r1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8rCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8ri, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SALC, X86_INS_SALC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SAR16m1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16mCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16mi, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16r1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16rCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16ri, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32m1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32mCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32mi, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32r1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32rCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32ri, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64m1, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64mCL, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64mi, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64r1, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64rCL, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64ri, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8m1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8mCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8mi, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8r1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8rCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8ri, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SARX32rm, X86_INS_SARX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SARX32rr, X86_INS_SARX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SARX64rm, X86_INS_SARX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SARX64rr, X86_INS_SARX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16i16, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16mi, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16mi8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16mr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16ri, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16ri8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16rm, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16rr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16rr_REV, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32i32, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32mi, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32mi8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32mr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32ri, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32ri8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32rm, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32rr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32rr_REV, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64i32, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64mi32, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64mi8, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64mr, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64ri32, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64ri8, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64rm, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64rr, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64rr_REV, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8i8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8mi, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8mi8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SBB8mr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8ri, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8ri8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SBB8rm, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8rr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8rr_REV, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASB, X86_INS_SCASB, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASL, X86_INS_SCASD, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASQ, X86_INS_SCASQ, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASW, X86_INS_SCASW, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SETAEm, X86_INS_SETAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETAEr, X86_INS_SETAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETAm, X86_INS_SETA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETAr, X86_INS_SETA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBEm, X86_INS_SETBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBEr, X86_INS_SETBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBm, X86_INS_SETB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBr, X86_INS_SETB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETEm, X86_INS_SETE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETEr, X86_INS_SETE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGEm, X86_INS_SETGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGEr, X86_INS_SETGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGm, X86_INS_SETG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGr, X86_INS_SETG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLEm, X86_INS_SETLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLEr, X86_INS_SETLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLm, X86_INS_SETL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLr, X86_INS_SETL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNEm, X86_INS_SETNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNEr, X86_INS_SETNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNOm, X86_INS_SETNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNOr, X86_INS_SETNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNPm, X86_INS_SETNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNPr, X86_INS_SETNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNSm, X86_INS_SETNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNSr, X86_INS_SETNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETOm, X86_INS_SETO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETOr, X86_INS_SETO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETPm, X86_INS_SETP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETPr, X86_INS_SETP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETSSBSY, X86_INS_SETSSBSY, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETSm, X86_INS_SETS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETSr, X86_INS_SETS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SFENCE, X86_INS_SFENCE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SGDT16m, X86_INS_SGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SGDT32m, X86_INS_SGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SGDT64m, X86_INS_SGDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_SHA1MSG1rm, X86_INS_SHA1MSG1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1MSG1rr, X86_INS_SHA1MSG1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1MSG2rm, X86_INS_SHA1MSG2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1MSG2rr, X86_INS_SHA1MSG2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1NEXTErm, X86_INS_SHA1NEXTE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1NEXTErr, X86_INS_SHA1NEXTE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1RNDS4rmi, X86_INS_SHA1RNDS4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA1RNDS4rri, X86_INS_SHA1RNDS4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA256MSG1rm, X86_INS_SHA256MSG1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA256MSG1rr, X86_INS_SHA256MSG1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA256MSG2rm, X86_INS_SHA256MSG2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA256MSG2rr, X86_INS_SHA256MSG2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA256RNDS2rm, X86_INS_SHA256RNDS2, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHA256RNDS2rr, X86_INS_SHA256RNDS2, 0, #ifndef CAPSTONE_DIET { X86_REG_XMM0, 0 }, { 0 }, { X86_GRP_SHA, 0 }, 0, 0 #endif }, { X86_SHL16m1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16mCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16mi, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16r1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16rCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16ri, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32m1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32mCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32mi, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32r1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32rCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32ri, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64m1, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64mCL, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64mi, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64r1, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64rCL, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64ri, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8m1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8mCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8mi, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8r1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8rCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8ri, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16mrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16mri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16rrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16rri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32mrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32mri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32rrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32rri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64mrCL, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64mri8, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64rrCL, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64rri8, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLX32rm, X86_INS_SHLX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHLX32rr, X86_INS_SHLX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHLX64rm, X86_INS_SHLX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHLX64rr, X86_INS_SHLX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHR16m1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16mCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16mi, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16r1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16rCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16ri, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32m1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32mCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32mi, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32r1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32rCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32ri, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64m1, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64mCL, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64mi, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64r1, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64rCL, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64ri, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8m1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8mCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8mi, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8r1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8rCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8ri, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16mrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16mri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16rrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16rri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32mrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32mri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32rrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32rri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64mrCL, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64mri8, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64rrCL, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64rri8, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRX32rm, X86_INS_SHRX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHRX32rr, X86_INS_SHRX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHRX64rm, X86_INS_SHRX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHRX64rr, X86_INS_SHRX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHUFPDrmi, X86_INS_SHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SHUFPDrri, X86_INS_SHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SHUFPSrmi, X86_INS_SHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SHUFPSrri, X86_INS_SHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SIDT16m, X86_INS_SIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SIDT32m, X86_INS_SIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SIDT64m, X86_INS_SIDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_SIN_F, X86_INS_FSIN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SIN_Fp32, X86_INS_FSIN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SIN_Fp64, X86_INS_FSIN, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SIN_Fp80, X86_INS_FSIN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SKINIT, X86_INS_SKINIT, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_SLDT16m, X86_INS_SLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLDT16r, X86_INS_SLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLDT32r, X86_INS_SLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLDT64r, X86_INS_SLDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLWPCB, X86_INS_SLWPCB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLWPCB64, X86_INS_SLWPCB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW16m, X86_INS_SMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW16r, X86_INS_SMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW32r, X86_INS_SMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW64r, X86_INS_SMSW, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRTPDm, X86_INS_SQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SQRTPDr, X86_INS_SQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SQRTPSm, X86_INS_SQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SQRTPSr, X86_INS_SQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SQRTSDm, X86_INS_SQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SQRTSDm_Int, X86_INS_SQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRTSDr, X86_INS_SQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SQRTSDr_Int, X86_INS_SQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRTSSm, X86_INS_SQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SQRTSSm_Int, X86_INS_SQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRTSSr, X86_INS_SQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SQRTSSr_Int, X86_INS_SQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRT_F, X86_INS_FSQRT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SQRT_Fp32, X86_INS_FSQRT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRT_Fp64, X86_INS_FSQRT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SQRT_Fp80, X86_INS_FSQRT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_STAC, X86_INS_STAC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STC, X86_INS_STC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_STD, X86_INS_STD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_STGI, X86_INS_STGI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_STI, X86_INS_STI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STMXCSR, X86_INS_STMXCSR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_STOSB, X86_INS_STOSB, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STOSL, X86_INS_STOSD, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STOSQ, X86_INS_STOSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, X86_REG_EFLAGS, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STOSW, X86_INS_STOSW, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STR16r, X86_INS_STR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STR32r, X86_INS_STR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STR64r, X86_INS_STR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STRm, X86_INS_STR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_ST_F32m, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ST_F64m, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ST_FP32m, X86_INS_FSTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ST_FP64m, X86_INS_FSTP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ST_FP80m, X86_INS_FSTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_ST_FPrr, X86_INS_FSTP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { 0 }, 0, 0 #endif }, { X86_ST_Fp32m, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_Fp64m, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_Fp64m32, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_Fp80m32, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_Fp80m64, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_FpP32m, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_FpP64m, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_FpP64m32, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_FpP80m, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_FpP80m32, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_FpP80m64, X86_INS_FST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ST_Frr, X86_INS_FST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB16i16, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16mi, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16mi8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16mr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16ri, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16ri8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16rm, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16rr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16rr_REV, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32i32, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32mi, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32mi8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32mr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32ri, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32ri8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32rm, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32rr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32rr_REV, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64i32, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64mi32, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64mi8, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64mr, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64ri32, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64ri8, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64rm, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64rr, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64rr_REV, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8i8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8mi, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8mi8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SUB8mr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8ri, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8ri8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SUB8rm, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8rr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8rr_REV, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUBPDrm, X86_INS_SUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SUBPDrr, X86_INS_SUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SUBPSrm, X86_INS_SUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SUBPSrr, X86_INS_SUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SUBR_F32m, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBR_F64m, X86_INS_FSUBR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBR_FI16m, X86_INS_FISUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBR_FI32m, X86_INS_FISUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBR_FPrST0, X86_INS_FSUBRP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBR_FST0r, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBR_Fp32m, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_Fp64m, X86_INS_FSUBR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_Fp64m32, X86_INS_FSUBR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_Fp80m32, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_Fp80m64, X86_INS_FSUBR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FpI16m32, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FpI16m64, X86_INS_FSUBR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FpI16m80, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FpI32m32, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FpI32m64, X86_INS_FSUBR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FpI32m80, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUBR_FrST0, X86_INS_FSUBR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUBSDrm, X86_INS_SUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SUBSDrm_Int, X86_INS_SUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SUBSDrr, X86_INS_SUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SUBSDrr_Int, X86_INS_SUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_SUBSSrm, X86_INS_SUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SUBSSrm_Int, X86_INS_SUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SUBSSrr, X86_INS_SUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SUBSSrr_Int, X86_INS_SUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_SUB_F32m, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB_F64m, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB_FI16m, X86_INS_FISUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB_FI32m, X86_INS_FISUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB_FPrST0, X86_INS_FSUBP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB_FST0r, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SUB_Fp32, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp32m, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp64, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp64m, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp64m32, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp80, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp80m32, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_Fp80m64, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FpI16m32, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FpI16m64, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FpI16m80, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FpI32m32, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FpI32m64, X86_INS_FSUB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FpI32m80, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SUB_FrST0, X86_INS_FSUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_SWAPGS, X86_INS_SWAPGS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_SYSCALL, X86_INS_SYSCALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_SYSENTER, X86_INS_SYSENTER, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_SYSEXIT, X86_INS_SYSEXIT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_SYSEXIT64, X86_INS_SYSEXITQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_SYSRET, X86_INS_SYSRET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_SYSRET64, X86_INS_SYSRETQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_IRET, X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_T1MSKC32rm, X86_INS_T1MSKC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_T1MSKC32rr, X86_INS_T1MSKC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_T1MSKC64rm, X86_INS_T1MSKC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_T1MSKC64rr, X86_INS_T1MSKC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TEST16i16, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16mi, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16mi_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16mr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16ri, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16ri_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16rr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32i32, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32mi, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32mi_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32mr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32ri, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32ri_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32rr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64i32, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64mi32, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64mi32_alt, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64mr, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64ri32, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64ri32_alt, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64rr, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8i8, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8mi, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8mi_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8mr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8ri, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8ri_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8rr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TPAUSE, X86_INS_TPAUSE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TST_F, X86_INS_FTST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_TST_Fp32, X86_INS_FTST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TST_Fp64, X86_INS_FTST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TST_Fp80, X86_INS_FTST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TZCNT16rm, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT16rr, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT32rm, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT32rr, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT64rm, X86_INS_TZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT64rr, X86_INS_TZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZMSK32rm, X86_INS_TZMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TZMSK32rr, X86_INS_TZMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TZMSK64rm, X86_INS_TZMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TZMSK64rr, X86_INS_TZMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_UCOMISDrm, X86_INS_UCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_UCOMISDrm_Int, X86_INS_UCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOMISDrr, X86_INS_UCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_UCOMISDrr_Int, X86_INS_UCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOMISSrm, X86_INS_UCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_UCOMISSrm_Int, X86_INS_UCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOMISSrr, X86_INS_UCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_UCOMISSrr_Int, X86_INS_UCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_FIPr, X86_INS_FUCOMPI, 0, #ifndef CAPSTONE_DIET { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_UCOM_FIr, X86_INS_FUCOMI, 0, #ifndef CAPSTONE_DIET { X86_REG_ST0, 0 }, { X86_REG_EFLAGS, X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_UCOM_FPPr, X86_INS_FUCOMPP, 0, #ifndef CAPSTONE_DIET { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_UCOM_FPr, X86_INS_FUCOMP, 0, #ifndef CAPSTONE_DIET { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_UCOM_FpIr32, X86_INS_FUCOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_FpIr64, X86_INS_FUCOMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_FpIr80, X86_INS_FUCOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_Fpr32, X86_INS_FUCOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_Fpr64, X86_INS_FUCOMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_Fpr80, X86_INS_FUCOMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UCOM_Fr, X86_INS_FUCOM, 0, #ifndef CAPSTONE_DIET { X86_REG_ST0, 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_UD0, X86_INS_UD0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UD1, X86_INS_UD1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UD2, X86_INS_UD2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMONITOR16, X86_INS_UMONITOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMONITOR32, X86_INS_UMONITOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMONITOR64, X86_INS_UMONITOR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMWAIT, X86_INS_UMWAIT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UNPCKHPDrm, X86_INS_UNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_UNPCKHPDrr, X86_INS_UNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_UNPCKHPSrm, X86_INS_UNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_UNPCKHPSrr, X86_INS_UNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_UNPCKLPDrm, X86_INS_UNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_UNPCKLPDrr, X86_INS_UNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_UNPCKLPSrm, X86_INS_UNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_UNPCKLPSrr, X86_INS_UNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_V4FMADDPSrm, X86_INS_V4FMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FMADDPSrmk, X86_INS_V4FMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FMADDPSrmkz, X86_INS_V4FMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FMADDSSrm, X86_INS_V4FMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FMADDSSrmk, X86_INS_V4FMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FMADDSSrmkz, X86_INS_V4FMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FNMADDPSrm, X86_INS_V4FNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FNMADDPSrmk, X86_INS_V4FNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FNMADDPSrmkz, X86_INS_V4FNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FNMADDSSrm, X86_INS_V4FNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FNMADDSSrmk, X86_INS_V4FNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_V4FNMADDSSrmkz, X86_INS_V4FNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPDYrm, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPDYrr, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rm, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rmb, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rmbk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rmbkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rmk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rmkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rr, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rrk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ128rrkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rm, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rmb, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rmbk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rmbkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rmk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rmkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rr, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rrk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZ256rrkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPDZrm, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrmb, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrmbk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrmbkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrmk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrmkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrr, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrrb, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPDZrrbk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPDZrrbkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPDZrrk, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDZrrkz, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPDrm, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPDrr, X86_INS_VADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPSYrm, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPSYrr, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rm, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rmb, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rmbk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rmbkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rmk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rmkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rr, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rrk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ128rrkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rm, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rmb, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rmbk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rmbkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rmk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rmkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rr, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rrk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZ256rrkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VADDPSZrm, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrmb, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrmbk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrmbkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrmk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrmkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrr, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrrb, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPSZrrbk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPSZrrbkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDPSZrrk, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSZrrkz, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDPSrm, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDPSrr, X86_INS_VADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VADDSDZrm, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrm_Int, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrm_Intk, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrm_Intkz, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrr, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrr_Int, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrr_Intk, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrr_Intkz, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSDZrrb_Int, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDSDZrrb_Intk, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDSDZrrb_Intkz, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDSDrm, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSDrm_Int, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSDrr, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSDrr_Int, X86_INS_VADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSSZrm, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrm_Int, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrm_Intk, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrm_Intkz, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrr, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrr_Int, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrr_Intk, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrr_Intkz, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VADDSSZrrb_Int, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDSSZrrb_Intk, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDSSZrrb_Intkz, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VADDSSrm, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSSrm_Int, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSSrr, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSSrr_Int, X86_INS_VADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPDYrm, X86_INS_VADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPDYrr, X86_INS_VADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPDrm, X86_INS_VADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPDrr, X86_INS_VADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPSYrm, X86_INS_VADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPSYrr, X86_INS_VADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPSrm, X86_INS_VADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VADDSUBPSrr, X86_INS_VADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VAESDECLASTYrm, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTYrr, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTZ128rm, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTZ128rr, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTZ256rm, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTZ256rr, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTZrm, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTZrr, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECLASTrm, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESDECLASTrr, X86_INS_VAESDECLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESDECYrm, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECYrr, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECZ128rm, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECZ128rr, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECZ256rm, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECZ256rr, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECZrm, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECZrr, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESDECrm, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESDECrr, X86_INS_VAESDEC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESENCLASTYrm, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTYrr, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTZ128rm, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTZ128rr, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTZ256rm, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTZ256rr, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTZrm, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTZrr, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCLASTrm, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESENCLASTrr, X86_INS_VAESENCLAST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESENCYrm, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCYrr, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCZ128rm, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCZ128rr, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCZ256rm, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCZ256rr, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCZrm, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCZrr, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VAESENCrm, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESENCrr, X86_INS_VAESENC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESIMCrm, X86_INS_VAESIMC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESIMCrr, X86_INS_VAESIMC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESKEYGENASSIST128rm, X86_INS_VAESKEYGENASSIST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VAESKEYGENASSIST128rr, X86_INS_VAESKEYGENASSIST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_AES, 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rmbi, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rmbik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rmbikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rmi, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rmik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rmikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rri, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rrik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ128rrikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rmbi, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rmbik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rmbikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rmi, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rmik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rmikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rri, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rrik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZ256rrikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrmbi, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrmbik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrmbikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrmi, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrmik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrmikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrri, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrrik, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNDZrrikz, X86_INS_VALIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rmbi, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rmbik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rmbikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rmi, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rmik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rmikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rri, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rrik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ128rrikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rmbi, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rmbik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rmbikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rmi, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rmik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rmikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rri, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rrik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZ256rrikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrmbi, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrmbik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrmbikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrmi, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrmik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrmikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrri, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrrik, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VALIGNQZrrikz, X86_INS_VALIGNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDYrm, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPDYrr, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rm, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rmb, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rmbk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rmbkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rmk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rmkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rr, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rrk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ128rrkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rm, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rmb, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rmbk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rmbkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rmk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rmkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rr, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rrk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZ256rrkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrm, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrmb, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrmbk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrmbkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrmk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrmkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrr, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrrk, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDZrrkz, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPDrm, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPDrr, X86_INS_VANDNPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPSYrm, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPSYrr, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rm, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rmb, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rmbk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rmbkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rmk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rmkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rr, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rrk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ128rrkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rm, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rmb, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rmbk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rmbkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rmk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rmkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rr, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rrk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZ256rrkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrm, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrmb, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrmbk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrmbkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrmk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrmkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrr, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrrk, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSZrrkz, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDNPSrm, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDNPSrr, X86_INS_VANDNPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPDYrm, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPDYrr, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPDZ128rm, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rmb, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rmbk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rmbkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rmk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rmkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rr, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rrk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ128rrkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rm, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rmb, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rmbk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rmbkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rmk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rmkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rr, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rrk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZ256rrkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrm, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrmb, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrmbk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrmbkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrmk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrmkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrr, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrrk, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDZrrkz, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPDrm, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPDrr, X86_INS_VANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPSYrm, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPSYrr, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPSZ128rm, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rmb, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rmbk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rmbkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rmk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rmkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rr, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rrk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ128rrkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rm, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rmb, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rmbk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rmbkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rmk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rmkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rr, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rrk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZ256rrkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrm, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrmb, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrmbk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrmbkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrmk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrmkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrr, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrrk, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSZrrkz, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VANDPSrm, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VANDPSrr, X86_INS_VANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rm, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rmb, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rmbk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rmbkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rmk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rmkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rr, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rrk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ128rrkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rm, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rmb, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rmbk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rmbkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rmk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rmkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rr, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rrk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZ256rrkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrm, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrmb, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrmbk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrmbkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrmk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrmkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrr, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrrk, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPDZrrkz, X86_INS_VBLENDMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rm, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rmb, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rmbk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rmbkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rmk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rmkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rr, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rrk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ128rrkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rm, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rmb, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rmbk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rmbkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rmk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rmkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rr, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rrk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZ256rrkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrm, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrmb, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrmbk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrmbkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrmk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrmkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrr, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrrk, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDMPSZrrkz, X86_INS_VBLENDMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBLENDPDYrmi, X86_INS_VBLENDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPDYrri, X86_INS_VBLENDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPDrmi, X86_INS_VBLENDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPDrri, X86_INS_VBLENDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPSYrmi, X86_INS_VBLENDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPSYrri, X86_INS_VBLENDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPSrmi, X86_INS_VBLENDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDPSrri, X86_INS_VBLENDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPDYrm, X86_INS_VBLENDVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPDYrr, X86_INS_VBLENDVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPDrm, X86_INS_VBLENDVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPDrr, X86_INS_VBLENDVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPSYrm, X86_INS_VBLENDVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPSYrr, X86_INS_VBLENDVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPSrm, X86_INS_VBLENDVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBLENDVPSrr, X86_INS_VBLENDVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBROADCASTF128, X86_INS_VBROADCASTF128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Z256m, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Z256mk, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Z256mkz, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Z256r, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Z256rk, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Z256rkz, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Zm, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Zmk, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Zmkz, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Zr, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Zrk, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X2Zrkz, X86_INS_VBROADCASTF32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X4Z256rm, X86_INS_VBROADCASTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X4Z256rmk, X86_INS_VBROADCASTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X4Z256rmkz, X86_INS_VBROADCASTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X4rm, X86_INS_VBROADCASTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X4rmk, X86_INS_VBROADCASTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X4rmkz, X86_INS_VBROADCASTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X8rm, X86_INS_VBROADCASTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X8rmk, X86_INS_VBROADCASTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF32X8rmkz, X86_INS_VBROADCASTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X2Z128rm, X86_INS_VBROADCASTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X2Z128rmk, X86_INS_VBROADCASTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X2Z128rmkz, X86_INS_VBROADCASTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X2rm, X86_INS_VBROADCASTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X2rmk, X86_INS_VBROADCASTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X2rmkz, X86_INS_VBROADCASTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X4rm, X86_INS_VBROADCASTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X4rmk, X86_INS_VBROADCASTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTF64X4rmkz, X86_INS_VBROADCASTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI128, X86_INS_VBROADCASTI128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z128m, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z128mk, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z128mkz, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z128r, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z128rk, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z128rkz, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z256m, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z256mk, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z256mkz, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z256r, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z256rk, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Z256rkz, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Zm, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Zmk, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Zmkz, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Zr, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Zrk, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X2Zrkz, X86_INS_VBROADCASTI32X2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X4Z256rm, X86_INS_VBROADCASTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X4Z256rmk, X86_INS_VBROADCASTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X4Z256rmkz, X86_INS_VBROADCASTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X4rm, X86_INS_VBROADCASTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X4rmk, X86_INS_VBROADCASTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X4rmkz, X86_INS_VBROADCASTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X8rm, X86_INS_VBROADCASTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X8rmk, X86_INS_VBROADCASTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI32X8rmkz, X86_INS_VBROADCASTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X2Z128rm, X86_INS_VBROADCASTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X2Z128rmk, X86_INS_VBROADCASTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X2Z128rmkz, X86_INS_VBROADCASTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X2rm, X86_INS_VBROADCASTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X2rmk, X86_INS_VBROADCASTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X2rmkz, X86_INS_VBROADCASTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X4rm, X86_INS_VBROADCASTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X4rmk, X86_INS_VBROADCASTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTI64X4rmkz, X86_INS_VBROADCASTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VBROADCASTSDYrm, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDYrr, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZ256m, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZ256mk, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZ256mkz, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZ256r, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZ256rk, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZ256rkz, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZm, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZmk, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZmkz, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZr, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZrk, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSDZrkz, X86_INS_VBROADCASTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSYrm, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSYrr, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ128m, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ128mk, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ128mkz, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ128r, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ128rk, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ128rkz, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ256m, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ256mk, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ256mkz, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ256r, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ256rk, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZ256rkz, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZm, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZmk, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZmkz, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZr, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZrk, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSZrkz, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSrm, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VBROADCASTSSrr, X86_INS_VBROADCASTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VCMPPDYrmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDYrmi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDYrri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDYrri_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmbi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmbi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmbi_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmbik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmi_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rmik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rri_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rri_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ128rrik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmbi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmbi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmbi_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmbik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmi_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rmik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rri_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rri_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZ256rrik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrmbi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrmbi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrmbi_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrmbik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPDZrmi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPDZrmi_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrmik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPDZrri_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPDZrri_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrrib, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPDZrrib_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPDZrrib_altk, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrribk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDZrrik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPDrmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDrmi_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDrri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPDrri_alt, X86_INS_VCMPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSYrmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSYrmi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSYrri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSYrri_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmbi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmbi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmbi_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmbik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmi_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rmik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rri_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rri_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ128rrik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmbi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmbi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmbi_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmbik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmi_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rmik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rri_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rri_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZ256rrik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrmbi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrmbi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrmbi_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrmbik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPSZrmi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPSZrmi_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrmik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPSZrri_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPSZrri_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrrib, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPSZrrib_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPPSZrrib_altk, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrribk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSZrrik, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPPSrmi, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSrmi_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSrri, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPPSrri_alt, X86_INS_VCMPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSDZrm, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSDZrm_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrm_Intk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrmi_alt, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSDZrmi_altk, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrr, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSDZrr_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrr_Intk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrrb_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrrb_Intk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrrb_alt, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrrb_altk, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDZrri_alt, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSDZrri_altk, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDrm, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSDrm_Int, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDrm_alt, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSDrr, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSDrr_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSDrr_alt, X86_INS_VCMPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSSZrm, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSSZrm_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrm_Intk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrmi_alt, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSSZrmi_altk, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrr, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSSZrr_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrr_Intk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrrb_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrrb_Intk, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrrb_alt, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrrb_altk, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSZrri_alt, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCMPSSZrri_altk, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSrm, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSSrm_Int, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSrm_alt, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSSrr, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCMPSSrr_Int, X86_INS_VCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCMPSSrr_alt, X86_INS_VCMPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCOMISDZrm, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMISDZrm_Int, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISDZrr, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMISDZrr_Int, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISDZrrb, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISDrm, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCOMISDrm_Int, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISDrr, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCOMISDrr_Int, X86_INS_VCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISSZrm, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMISSZrm_Int, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISSZrr, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMISSZrr_Int, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISSZrrb, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISSrm, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCOMISSrm_Int, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMISSrr, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCOMISSrr_Int, X86_INS_VCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ128mr, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ128mrk, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ128rr, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ128rrk, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ128rrkz, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ256mr, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ256mrk, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ256rr, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ256rrk, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZ256rrkz, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZmr, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZmrk, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZrr, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZrrk, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPDZrrkz, X86_INS_VCOMPRESSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ128mr, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ128mrk, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ128rr, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ128rrk, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ128rrkz, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ256mr, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ256mrk, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ256rr, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ256rrk, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZ256rrkz, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZmr, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZmrk, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZrr, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZrrk, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCOMPRESSPSZrrkz, X86_INS_VCOMPRESSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDYrm, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDYrr, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rm, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rmb, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rmbk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rmbkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rmk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rmkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rr, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rrk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ128rrkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rm, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rmb, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rmbk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rmbkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rmk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rmkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rr, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rrk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZ256rrkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrm, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrmb, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrmbk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrmbkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrmk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrmkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrr, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrrk, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDZrrkz, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDrm, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PDrr, X86_INS_VCVTDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSYrm, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSYrr, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rm, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rmb, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rmbk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rmbkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rmk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rmkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rr, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rrk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ128rrkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rm, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rmb, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rmbk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rmbkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rmk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rmkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rr, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rrk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZ256rrkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrm, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrmb, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrmbk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrmbkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrmk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrmkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrr, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrrb, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrrbk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrrbkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrrk, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSZrrkz, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSrm, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTDQ2PSrr, X86_INS_VCVTDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2DQYrm, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2DQYrr, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rm, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rmb, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rmbk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rmbkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rmk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rmkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rr, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rrk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ128rrkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rm, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rmb, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rmbk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rmbkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rmk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rmkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rr, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rrk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZ256rrkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrm, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrmb, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrmbk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrmbkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrmk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrmkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrr, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrrb, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrrbk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrrbkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrrk, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQZrrkz, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQrm, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2DQrr, X86_INS_VCVTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2PSYrm, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2PSYrr, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rm, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rmb, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rmbk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rmbkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rmk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rmkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rr, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rrk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ128rrkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rm, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rmb, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rmbk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rmbkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rmk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rmkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rr, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rrk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZ256rrkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrm, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrmb, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrmbk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrmbkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrmk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrmkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrr, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrrb, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrrbk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrrbkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrrk, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSZrrkz, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSrm, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2PSrr, X86_INS_VCVTPD2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rm, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rmb, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rmbk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rmbkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rmk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rmkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rr, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rrk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ128rrkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rm, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rmb, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rmbk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rmbkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rmk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rmkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rr, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rrk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZ256rrkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrm, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrmb, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrmbk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrmbkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrmk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrmkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrr, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrrb, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrrbk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrrbkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrrk, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2QQZrrkz, X86_INS_VCVTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rm, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rmb, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rmbk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rmbkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rmk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rmkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rr, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rrk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ128rrkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rm, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rmb, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rmbk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rmbkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rmk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rmkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rr, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rrk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZ256rrkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrm, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrmb, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrmbk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrmbkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrmk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrmkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrr, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrrb, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrrbk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrrbkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrrk, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UDQZrrkz, X86_INS_VCVTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rm, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rmb, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rmbk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rmbkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rmk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rmkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rr, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rrk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ128rrkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rm, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rmb, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rmbk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rmbkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rmk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rmkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rr, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rrk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZ256rrkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrm, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrmb, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrmbk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrmbkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrmk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrmkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrr, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrrb, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrrbk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrrbkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrrk, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPD2UQQZrrkz, X86_INS_VCVTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSYrm, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPH2PSYrr, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ128rm, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ128rmk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ128rmkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ128rr, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ128rrk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ128rrkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ256rm, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ256rmk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ256rmkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ256rr, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ256rrk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZ256rrkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrm, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrmk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrmkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrr, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrrb, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrrbk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrrbkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrrk, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSZrrkz, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPH2PSrm, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPH2PSrr, X86_INS_VCVTPH2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQYrm, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQYrr, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rm, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rmb, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rmbk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rmbkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rmk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rmkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rr, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rrk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ128rrkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rm, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rmb, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rmbk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rmbkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rmk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rmkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rr, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rrk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZ256rrkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrm, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrmb, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrmbk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrmbkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrmk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrmkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrr, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrrb, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrrbk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrrbkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrrk, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQZrrkz, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2DQrm, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2DQrr, X86_INS_VCVTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2PDYrm, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2PDYrr, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rm, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rmb, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rmbk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rmbkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rmk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rmkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rr, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rrk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ128rrkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rm, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rmb, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rmbk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rmbkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rmk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rmkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rr, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rrk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZ256rrkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrm, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrmb, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrmbk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrmbkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrmk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrmkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrr, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrrb, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrrbk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrrbkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrrk, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDZrrkz, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PDrm, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2PDrr, X86_INS_VCVTPS2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTPS2PHYmr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPS2PHYrr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ128mr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ128mrk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ128rr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ128rrk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ128rrkz, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ256mr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ256mrk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ256rr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ256rrk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZ256rrkz, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZmr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZmrk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZrr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZrrb, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZrrbk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZrrbkz, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZrrk, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHZrrkz, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2PHmr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPS2PHrr, X86_INS_VCVTPS2PH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_F16C, 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rm, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rmb, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rmbk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rmbkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rmk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rmkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rr, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rrk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ128rrkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rm, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rmb, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rmbk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rmbkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rmk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rmkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rr, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rrk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZ256rrkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrm, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrmb, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrmbk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrmbkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrmk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrmkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrr, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrrb, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrrbk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrrbkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrrk, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2QQZrrkz, X86_INS_VCVTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rm, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rmb, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rmbk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rmbkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rmk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rmkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rr, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rrk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ128rrkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rm, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rmb, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rmbk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rmbkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rmk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rmkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rr, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rrk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZ256rrkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrm, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrmb, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrmbk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrmbkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrmk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrmkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrr, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrrb, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrrbk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrrbkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrrk, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UDQZrrkz, X86_INS_VCVTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rm, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rmb, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rmbk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rmbkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rmk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rmkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rr, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rrk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ128rrkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rm, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rmb, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rmbk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rmbkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rmk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rmkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rr, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rrk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZ256rrkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrm, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrmb, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrmbk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrmbkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrmk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrmkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrr, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrrb, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrrbk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrrbkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrrk, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTPS2UQQZrrkz, X86_INS_VCVTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rm, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rmb, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rmbk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rmbkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rmk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rmkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rr, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rrk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ128rrkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rm, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rmb, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rmbk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rmbkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rmk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rmkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rr, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rrk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZ256rrkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrm, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrmb, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrmbk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrmbkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrmk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrmkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrr, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrrb, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrrbk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrrbkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrrk, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PDZrrkz, X86_INS_VCVTQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rm, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rmb, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rmbk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rmbkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rmk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rmkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rr, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rrk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ128rrkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rm, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rmb, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rmbk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rmbkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rmk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rmkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rr, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rrk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZ256rrkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrm, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrmb, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrmbk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrmbkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrmk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrmkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrr, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrrb, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrrbk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrrbkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrrk, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTQQ2PSZrrkz, X86_INS_VCVTQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SI64Zrm_Int, X86_INS_VCVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SI64Zrr_Int, X86_INS_VCVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SI64Zrrb_Int, X86_INS_VCVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SI64rm_Int, X86_INS_VCVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SI64rr_Int, X86_INS_VCVTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SIZrm_Int, X86_INS_VCVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SIZrr_Int, X86_INS_VCVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SIZrrb_Int, X86_INS_VCVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SIrm_Int, X86_INS_VCVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SIrr_Int, X86_INS_VCVTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrm, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrm_Int, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrm_Intk, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrm_Intkz, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrr, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrr_Int, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrr_Intk, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrr_Intkz, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrrb_Int, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrrb_Intk, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSZrrb_Intkz, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSrm, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSD2SSrm_Int, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2SSrr, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSD2SSrr_Int, X86_INS_VCVTSD2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2USI64Zrm_Int, X86_INS_VCVTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2USI64Zrr_Int, X86_INS_VCVTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2USI64Zrrb_Int, X86_INS_VCVTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2USIZrm_Int, X86_INS_VCVTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2USIZrr_Int, X86_INS_VCVTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSD2USIZrrb_Int, X86_INS_VCVTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SDZrm, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI2SDZrm_Int, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SDZrr, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI2SDZrr_Int, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SDZrrb_Int, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SDrm, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSI2SDrm_Int, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SDrr, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSI2SDrr_Int, X86_INS_VCVTSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SSZrm, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI2SSZrm_Int, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SSZrr, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI2SSZrr_Int, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SSZrrb_Int, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SSrm, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSI2SSrm_Int, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI2SSrr, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSI2SSrr_Int, X86_INS_VCVTSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDZrm, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI642SDZrm_Int, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDZrr, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI642SDZrr_Int, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDZrrb_Int, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDrm, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDrm_Int, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDrr, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SDrr_Int, X86_INS_VCVTSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSZrm, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI642SSZrm_Int, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSZrr, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSI642SSZrr_Int, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSZrrb_Int, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSrm, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSrm_Int, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSrr, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSI642SSrr_Int, X86_INS_VCVTSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrm, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrm_Int, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrm_Intk, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrm_Intkz, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrr, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrr_Int, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrr_Intk, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrr_Intkz, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrrb_Int, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrrb_Intk, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDZrrb_Intkz, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDrm, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSS2SDrm_Int, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SDrr, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTSS2SDrr_Int, X86_INS_VCVTSS2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SI64Zrm_Int, X86_INS_VCVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SI64Zrr_Int, X86_INS_VCVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SI64Zrrb_Int, X86_INS_VCVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SI64rm_Int, X86_INS_VCVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SI64rr_Int, X86_INS_VCVTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SIZrm_Int, X86_INS_VCVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SIZrr_Int, X86_INS_VCVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SIZrrb_Int, X86_INS_VCVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SIrm_Int, X86_INS_VCVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2SIrr_Int, X86_INS_VCVTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2USI64Zrm_Int, X86_INS_VCVTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2USI64Zrr_Int, X86_INS_VCVTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2USI64Zrrb_Int, X86_INS_VCVTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2USIZrm_Int, X86_INS_VCVTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2USIZrr_Int, X86_INS_VCVTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTSS2USIZrrb_Int, X86_INS_VCVTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQYrm, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQYrr, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rm, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rmb, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rmbk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rmbkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rmk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rmkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rr, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rrk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ128rrkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rm, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rmb, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rmbk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rmbkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rmk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rmkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rr, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rrk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZ256rrkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrm, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrmb, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrmbk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrmbkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrmk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrmkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrr, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrrb, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrrbk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrrbkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrrk, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQZrrkz, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQrm, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2DQrr, X86_INS_VCVTTPD2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rm, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rmb, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rmbk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rmbkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rmk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rmkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rr, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rrk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ128rrkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rm, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rmb, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rmbk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rmbkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rmk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rmkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rr, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rrk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZ256rrkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrm, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrmb, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrmbk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrmbkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrmk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrmkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrr, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrrb, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrrbk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrrbkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrrk, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2QQZrrkz, X86_INS_VCVTTPD2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rm, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rmb, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rmbk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rmbkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rmk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rmkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rr, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rrk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ128rrkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rm, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rmb, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rmbk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rmbkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rmk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rmkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rr, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rrk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZ256rrkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrm, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrmb, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrmbk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrmbkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrmk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrmkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrr, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrrb, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrrbk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrrbkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrrk, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UDQZrrkz, X86_INS_VCVTTPD2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rm, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rmb, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rmbk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rmbkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rmk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rmkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rr, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rrk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ128rrkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rm, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rmb, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rmbk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rmbkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rmk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rmkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rr, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rrk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZ256rrkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrm, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrmb, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrmbk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrmbkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrmk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrmkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrr, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrrb, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrrbk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrrbkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrrk, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPD2UQQZrrkz, X86_INS_VCVTTPD2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQYrm, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQYrr, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rm, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rmb, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rmbk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rmbkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rmk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rmkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rr, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rrk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ128rrkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rm, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rmb, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rmbk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rmbkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rmk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rmkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rr, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rrk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZ256rrkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrm, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrmb, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrmbk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrmbkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrmk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrmkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrr, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrrb, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrrbk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrrbkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrrk, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQZrrkz, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQrm, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPS2DQrr, X86_INS_VCVTTPS2DQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rm, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rmb, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rmbk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rmbkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rmk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rmkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rr, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rrk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ128rrkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rm, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rmb, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rmbk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rmbkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rmk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rmkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rr, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rrk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZ256rrkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrm, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrmb, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrmbk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrmbkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrmk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrmkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrr, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrrb, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrrbk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrrbkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrrk, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2QQZrrkz, X86_INS_VCVTTPS2QQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rm, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rmb, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rmbk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rmbkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rmk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rmkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rr, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rrk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ128rrkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rm, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rmb, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rmbk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rmbkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rmk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rmkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rr, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rrk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZ256rrkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrm, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrmb, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrmbk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrmbkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrmk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrmkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrr, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrrb, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrrbk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrrbkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrrk, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UDQZrrkz, X86_INS_VCVTTPS2UDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rm, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rmb, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rmbk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rmbkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rmk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rmkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rr, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rrk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ128rrkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rm, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rmb, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rmbk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rmbkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rmk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rmkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rr, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rrk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZ256rrkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrm, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrmb, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrmbk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrmbkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrmk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrmkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrr, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrrb, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrrbk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrrbkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrrk, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTPS2UQQZrrkz, X86_INS_VCVTTPS2UQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64Zrm_Int, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64Zrr_Int, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64Zrrb_Int, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64rm_Int, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SI64rr_Int, X86_INS_VCVTTSD2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIZrm_Int, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIZrr_Int, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIZrrb_Int, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIrm_Int, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSD2SIrr_Int, X86_INS_VCVTTSD2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2USI64Zrm_Int, X86_INS_VCVTTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2USI64Zrr_Int, X86_INS_VCVTTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2USI64Zrrb_Int, X86_INS_VCVTTSD2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2USIZrm_Int, X86_INS_VCVTTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSD2USIZrr_Int, X86_INS_VCVTTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSD2USIZrrb_Int, X86_INS_VCVTTSD2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64Zrm_Int, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64Zrr_Int, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64Zrrb_Int, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64rm_Int, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SI64rr_Int, X86_INS_VCVTTSS2SI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIZrm_Int, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIZrr_Int, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIZrrb_Int, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIrm_Int, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VCVTTSS2SIrr_Int, X86_INS_VCVTTSS2SI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2USI64Zrm_Int, X86_INS_VCVTTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2USI64Zrr_Int, X86_INS_VCVTTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2USI64Zrrb_Int, X86_INS_VCVTTSS2USI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2USIZrm_Int, X86_INS_VCVTTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTTSS2USIZrr_Int, X86_INS_VCVTTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTTSS2USIZrrb_Int, X86_INS_VCVTTSS2USI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rm, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rmb, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rmbk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rmbkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rmk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rmkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rr, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rrk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ128rrkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rm, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rmb, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rmbk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rmbkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rmk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rmkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rr, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rrk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZ256rrkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrm, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrmb, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrmbk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrmbkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrmk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrmkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrr, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrrk, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PDZrrkz, X86_INS_VCVTUDQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rm, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rmb, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rmbk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rmbkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rmk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rmkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rr, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rrk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ128rrkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rm, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rmb, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rmbk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rmbkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rmk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rmkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rr, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rrk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZ256rrkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrm, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrmb, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrmbk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrmbkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrmk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrmkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrr, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrrb, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrrbk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrrbkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrrk, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUDQ2PSZrrkz, X86_INS_VCVTUDQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rm, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rmb, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rmbk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rmbkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rmk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rmkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rr, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rrk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ128rrkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rm, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rmb, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rmbk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rmbkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rmk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rmkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rr, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rrk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZ256rrkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrm, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrmb, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrmbk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrmbkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrmk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrmkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrr, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrrb, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrrbk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrrbkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrrk, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PDZrrkz, X86_INS_VCVTUQQ2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rm, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rmb, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rmbk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rmbkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rmk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rmkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rr, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rrk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ128rrkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rm, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rmb, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rmbk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rmbkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rmk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rmkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rr, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rrk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZ256rrkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrm, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrmb, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrmbk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrmbkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrmk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrmkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrr, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrrb, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrrbk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrrbkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrrk, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUQQ2PSZrrkz, X86_INS_VCVTUQQ2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI2SDZrm_Int, X86_INS_VCVTUSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI2SDZrr_Int, X86_INS_VCVTUSI2SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI2SSZrm_Int, X86_INS_VCVTUSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI2SSZrr_Int, X86_INS_VCVTUSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI2SSZrrb_Int, X86_INS_VCVTUSI2SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI642SDZrm, X86_INS_VCVTUSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI642SDZrm_Int, X86_INS_VCVTUSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI642SDZrr, X86_INS_VCVTUSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI642SDZrr_Int, X86_INS_VCVTUSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI642SDZrrb_Int, X86_INS_VCVTUSI2SD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI642SSZrm, X86_INS_VCVTUSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI642SSZrm_Int, X86_INS_VCVTUSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI642SSZrr, X86_INS_VCVTUSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VCVTUSI642SSZrr_Int, X86_INS_VCVTUSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VCVTUSI642SSZrrb_Int, X86_INS_VCVTUSI2SS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ128rmi, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ128rmik, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ128rmikz, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ128rri, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ128rrik, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ128rrikz, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ256rmi, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ256rmik, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ256rmikz, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ256rri, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ256rrik, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZ256rrikz, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZrmi, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZrmik, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZrmikz, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZrri, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZrrik, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDBPSADBWZrrikz, X86_INS_VDBPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPDYrm, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPDYrr, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rm, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rmb, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rmbk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rmbkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rmk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rmkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rr, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rrk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ128rrkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rm, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rmb, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rmbk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rmbkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rmk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rmkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rr, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rrk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZ256rrkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPDZrm, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrmb, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrmbk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrmbkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrmk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrmkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrr, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrrb, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPDZrrbk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPDZrrbkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPDZrrk, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDZrrkz, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPDrm, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPDrr, X86_INS_VDIVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPSYrm, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPSYrr, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rm, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rmb, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rmbk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rmbkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rmk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rmkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rr, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rrk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ128rrkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rm, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rmb, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rmbk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rmbkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rmk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rmkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rr, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rrk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZ256rrkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VDIVPSZrm, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrmb, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrmbk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrmbkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrmk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrmkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrr, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrrb, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPSZrrbk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPSZrrbkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVPSZrrk, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSZrrkz, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVPSrm, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVPSrr, X86_INS_VDIVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VDIVSDZrm, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrm_Int, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrm_Intk, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrm_Intkz, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrr, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrr_Int, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrr_Intk, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrr_Intkz, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSDZrrb_Int, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVSDZrrb_Intk, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVSDZrrb_Intkz, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVSDrm, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSDrm_Int, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSDrr, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSDrr_Int, X86_INS_VDIVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSSZrm, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrm_Int, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrm_Intk, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrm_Intkz, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrr, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrr_Int, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrr_Intk, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrr_Intkz, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VDIVSSZrrb_Int, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVSSZrrb_Intk, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVSSZrrb_Intkz, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VDIVSSrm, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSSrm_Int, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSSrr, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDIVSSrr_Int, X86_INS_VDIVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDPPDrmi, X86_INS_VDPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDPPDrri, X86_INS_VDPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDPPSYrmi, X86_INS_VDPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDPPSYrri, X86_INS_VDPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDPPSrmi, X86_INS_VDPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VDPPSrri, X86_INS_VDPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VERRm, X86_INS_VERR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERRr, X86_INS_VERR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERWm, X86_INS_VERW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERWr, X86_INS_VERW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZm, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZmb, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZmbk, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZmbkz, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZmk, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZmkz, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZr, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZrb, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZrbk, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZrbkz, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZrk, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PDZrkz, X86_INS_VEXP2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZm, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZmb, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZmbk, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZmbkz, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZmk, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZmkz, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZr, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZrb, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZrbk, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZrbkz, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZrk, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXP2PSZrkz, X86_INS_VEXP2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ128rm, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ128rmk, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ128rmkz, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ128rr, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ128rrk, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ128rrkz, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ256rm, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ256rmk, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ256rmkz, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ256rr, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ256rrk, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZ256rrkz, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZrm, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZrmk, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZrmkz, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZrr, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPDZrrk, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPDZrrkz, X86_INS_VEXPANDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ128rm, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ128rmk, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ128rmkz, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ128rr, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ128rrk, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ128rrkz, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ256rm, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ256rmk, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ256rmkz, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ256rr, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ256rrk, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZ256rrkz, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZrm, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPSZrmk, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZrmkz, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZrr, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXPANDPSZrrk, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXPANDPSZrrkz, X86_INS_VEXPANDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VEXTRACTF128mr, X86_INS_VEXTRACTF128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VEXTRACTF128rr, X86_INS_VEXTRACTF128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Z256mr, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Z256mrk, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Z256rr, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Z256rrk, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Z256rrkz, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Zmr, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Zmrk, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Zrr, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Zrrk, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x4Zrrkz, X86_INS_VEXTRACTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x8Zmr, X86_INS_VEXTRACTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x8Zmrk, X86_INS_VEXTRACTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x8Zrr, X86_INS_VEXTRACTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x8Zrrk, X86_INS_VEXTRACTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF32x8Zrrkz, X86_INS_VEXTRACTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Z256mr, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Z256mrk, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Z256rr, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Z256rrk, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Z256rrkz, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Zmr, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Zmrk, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Zrr, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Zrrk, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x2Zrrkz, X86_INS_VEXTRACTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x4Zmr, X86_INS_VEXTRACTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x4Zmrk, X86_INS_VEXTRACTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x4Zrr, X86_INS_VEXTRACTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x4Zrrk, X86_INS_VEXTRACTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTF64x4Zrrkz, X86_INS_VEXTRACTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI128mr, X86_INS_VEXTRACTI128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VEXTRACTI128rr, X86_INS_VEXTRACTI128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Z256mr, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Z256mrk, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Z256rr, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Z256rrk, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Z256rrkz, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Zmr, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Zmrk, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Zrr, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Zrrk, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x4Zrrkz, X86_INS_VEXTRACTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x8Zmr, X86_INS_VEXTRACTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x8Zmrk, X86_INS_VEXTRACTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x8Zrr, X86_INS_VEXTRACTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x8Zrrk, X86_INS_VEXTRACTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI32x8Zrrkz, X86_INS_VEXTRACTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Z256mr, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Z256mrk, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Z256rr, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Z256rrk, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Z256rrkz, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Zmr, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Zmrk, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Zrr, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Zrrk, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x2Zrrkz, X86_INS_VEXTRACTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x4Zmr, X86_INS_VEXTRACTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x4Zmrk, X86_INS_VEXTRACTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x4Zrr, X86_INS_VEXTRACTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x4Zrrk, X86_INS_VEXTRACTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTI64x4Zrrkz, X86_INS_VEXTRACTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTPSZmr, X86_INS_VEXTRACTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTPSZrr, X86_INS_VEXTRACTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VEXTRACTPSmr, X86_INS_VEXTRACTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VEXTRACTPSrr, X86_INS_VEXTRACTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rmbi, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rmbik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rmbikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rmi, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rmik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rmikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rri, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rrik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ128rrikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rmbi, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rmbik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rmbikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rmi, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rmik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rmikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rri, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rrik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZ256rrikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrmbi, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrmbik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrmbikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrmi, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrmik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrmikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrri, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrrib, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrribk, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrribkz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrrik, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPDZrrikz, X86_INS_VFIXUPIMMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rmbi, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rmbik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rmbikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rmi, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rmik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rmikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rri, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rrik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ128rrikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rmbi, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rmbik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rmbikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rmi, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rmik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rmikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rri, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rrik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZ256rrikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrmbi, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrmbik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrmbikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrmi, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrmik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrmikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrri, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrrib, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrribk, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrribkz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrrik, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMPSZrrikz, X86_INS_VFIXUPIMMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrmi, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrmik, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrmikz, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrri, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrrib, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrribk, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrribkz, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrrik, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSDZrrikz, X86_INS_VFIXUPIMMSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrmi, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrmik, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrmikz, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrri, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrrib, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrribk, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrribkz, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrrik, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFIXUPIMMSSZrrikz, X86_INS_VFIXUPIMMSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDYm, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDYr, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128m, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128mb, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128mbk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128mbkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128mk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128mkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128r, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128rk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ128rkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256m, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256mb, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256mbk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256mbkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256mk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256mkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256r, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256rk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZ256rkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZm, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PDZmb, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PDZmbk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZmbkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZmk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZmkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZr, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZrb, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZrbk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZrbkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZrk, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDZrkz, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDm, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PDr, X86_INS_VFMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSYm, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSYr, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128m, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128mb, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128mbk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128mbkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128mk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128mkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128r, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128rk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ128rkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256m, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256mb, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256mbk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256mbkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256mk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256mkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256r, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256rk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZ256rkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZm, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PSZmb, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADD132PSZmbk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZmbkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZmk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZmkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZr, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZrb, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZrbk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZrbkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZrk, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSZrkz, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSm, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132PSr, X86_INS_VFMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZm, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZm_Int, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZm_Intk, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZm_Intkz, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZr, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZr_Int, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZr_Intk, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZr_Intkz, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZrb, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZrb_Int, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZrb_Intk, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDZrb_Intkz, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDm, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDm_Int, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDr, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SDr_Int, X86_INS_VFMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZm, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZm_Int, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZm_Intk, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZm_Intkz, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZr, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZr_Int, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZr_Intk, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZr_Intkz, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZrb, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZrb_Int, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZrb_Intk, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSZrb_Intkz, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSm, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSm_Int, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSr, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD132SSr_Int, X86_INS_VFMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDYm, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDYr, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128m, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128mb, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128mbk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128mbkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128mk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128mkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128r, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128rk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ128rkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256m, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256mb, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256mbk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256mbkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256mk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256mkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256r, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256rk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZ256rkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZm, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZmb, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZmbk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZmbkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZmk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZmkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZr, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZrb, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZrbk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZrbkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZrk, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDZrkz, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDm, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PDr, X86_INS_VFMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSYm, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSYr, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128m, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128mb, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128mbk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128mbkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128mk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128mkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128r, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128rk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ128rkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256m, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256mb, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256mbk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256mbkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256mk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256mkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256r, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256rk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZ256rkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZm, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZmb, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZmbk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZmbkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZmk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZmkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZr, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZrb, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZrbk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZrbkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZrk, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSZrkz, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSm, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213PSr, X86_INS_VFMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZm, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZm_Int, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZm_Intk, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZm_Intkz, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZr, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZr_Int, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZr_Intk, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZr_Intkz, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZrb, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZrb_Int, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZrb_Intk, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDZrb_Intkz, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDm, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDm_Int, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDr, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SDr_Int, X86_INS_VFMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZm, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZm_Int, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZm_Intk, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZm_Intkz, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZr, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZr_Int, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZr_Intk, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZr_Intkz, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZrb, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZrb_Int, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZrb_Intk, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSZrb_Intkz, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSm, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSm_Int, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSr, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD213SSr_Int, X86_INS_VFMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDYm, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDYr, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128m, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128mb, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128mbk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128mbkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128mk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128mkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128r, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128rk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ128rkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256m, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256mb, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256mbk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256mbkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256mk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256mkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256r, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256rk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZ256rkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZm, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZmb, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZmbk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZmbkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZmk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZmkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZr, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZrb, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZrbk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZrbkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZrk, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDZrkz, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDm, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PDr, X86_INS_VFMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSYm, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSYr, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128m, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128mb, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128mbk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128mbkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128mk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128mkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128r, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128rk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ128rkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256m, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256mb, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256mbk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256mbkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256mk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256mkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256r, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256rk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZ256rkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZm, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZmb, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZmbk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZmbkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZmk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZmkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZr, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZrb, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZrbk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZrbkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZrk, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSZrkz, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSm, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231PSr, X86_INS_VFMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZm, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZm_Int, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZm_Intk, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZm_Intkz, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZr, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZr_Int, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZr_Intk, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZr_Intkz, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZrb, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZrb_Int, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZrb_Intk, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDZrb_Intkz, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDm, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDm_Int, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDr, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SDr_Int, X86_INS_VFMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZm, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZm_Int, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZm_Intk, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZm_Intkz, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZr, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZr_Int, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZr_Intk, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZr_Intkz, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZrb, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZrb_Int, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZrb_Intk, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSZrb_Intkz, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSm, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSm_Int, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSr, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADD231SSr_Int, X86_INS_VFMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPD4Ymr, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPD4Yrm, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPD4Yrr, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPD4Yrr_REV, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPD4mr, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPD4rm, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPD4rr, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPD4rr_REV, X86_INS_VFMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPS4Ymr, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPS4Yrm, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPS4Yrr, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPS4Yrr_REV, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDPS4mr, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPS4rm, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPS4rr, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDPS4rr_REV, X86_INS_VFMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4mr, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4mr_Int, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4rm, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4rm_Int, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4rr, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4rr_Int, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSD4rr_Int_REV, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSD4rr_REV, X86_INS_VFMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4mr, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4mr_Int, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4rm, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4rm_Int, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4rr, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4rr_Int, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSS4rr_Int_REV, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSS4rr_REV, X86_INS_VFMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDYm, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDYr, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128m, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128mb, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128mbk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128mbkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128mk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128mkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128r, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128rk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ128rkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256m, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256mb, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256mbk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256mbkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256mk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256mkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256r, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256rk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZ256rkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZm, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZmb, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZmbk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZmbkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZmk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZmkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZr, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZrb, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZrbk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZrbkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZrk, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDZrkz, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDm, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PDr, X86_INS_VFMADDSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSYm, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSYr, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128m, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128mb, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128mbk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128mbkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128mk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128mkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128r, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128rk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ128rkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256m, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256mb, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256mbk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256mbkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256mk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256mkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256r, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256rk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZ256rkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZm, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZmb, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZmbk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZmbkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZmk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZmkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZr, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZrb, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZrbk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZrbkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZrk, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSZrkz, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSm, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB132PSr, X86_INS_VFMADDSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDYm, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDYr, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128m, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128mb, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128mbk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128mbkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128mk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128mkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128r, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128rk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ128rkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256m, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256mb, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256mbk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256mbkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256mk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256mkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256r, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256rk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZ256rkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZm, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZmb, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZmbk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZmbkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZmk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZmkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZr, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZrb, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZrbk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZrbkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZrk, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDZrkz, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDm, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PDr, X86_INS_VFMADDSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSYm, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSYr, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128m, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128mb, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128mbk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128mbkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128mk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128mkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128r, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128rk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ128rkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256m, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256mb, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256mbk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256mbkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256mk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256mkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256r, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256rk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZ256rkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZm, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZmb, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZmbk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZmbkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZmk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZmkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZr, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZrb, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZrbk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZrbkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZrk, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSZrkz, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSm, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB213PSr, X86_INS_VFMADDSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDYm, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDYr, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128m, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128mb, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128mbk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128mbkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128mk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128mkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128r, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128rk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ128rkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256m, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256mb, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256mbk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256mbkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256mk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256mkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256r, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256rk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZ256rkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZm, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZmb, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZmbk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZmbkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZmk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZmkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZr, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZrb, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZrbk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZrbkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZrk, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDZrkz, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDm, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PDr, X86_INS_VFMADDSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSYm, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSYr, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128m, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128mb, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128mbk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128mbkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128mk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128mkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128r, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128rk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ128rkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256m, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256mb, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256mbk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256mbkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256mk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256mkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256r, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256rk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZ256rkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZm, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZmb, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZmbk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZmbkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZmk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZmkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZr, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZrb, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZrbk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZrbkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZrk, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSZrkz, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSm, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUB231PSr, X86_INS_VFMADDSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4Ymr, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4Yrm, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4Yrr, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4Yrr_REV, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4mr, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4rm, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4rr, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPD4rr_REV, X86_INS_VFMADDSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4Ymr, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4Yrm, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4Yrr, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4Yrr_REV, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4mr, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4rm, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4rr, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMADDSUBPS4rr_REV, X86_INS_VFMADDSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDYm, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDYr, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128m, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128mb, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128mbk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128mbkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128mk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128mkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128r, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128rk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ128rkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256m, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256mb, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256mbk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256mbkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256mk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256mkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256r, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256rk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZ256rkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZm, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZmb, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZmbk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZmbkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZmk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZmkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZr, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZrb, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZrbk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZrbkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZrk, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDZrkz, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDm, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PDr, X86_INS_VFMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSYm, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSYr, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128m, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128mb, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128mbk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128mbkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128mk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128mkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128r, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128rk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ128rkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256m, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256mb, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256mbk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256mbkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256mk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256mkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256r, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256rk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZ256rkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZm, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZmb, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZmbk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZmbkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZmk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZmkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZr, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZrb, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZrbk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZrbkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZrk, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSZrkz, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSm, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132PSr, X86_INS_VFMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZm, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZm_Int, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZm_Intk, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZm_Intkz, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZr, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZr_Int, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZr_Intk, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZr_Intkz, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZrb, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZrb_Int, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZrb_Intk, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDZrb_Intkz, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDm, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDm_Int, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDr, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SDr_Int, X86_INS_VFMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZm, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZm_Int, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZm_Intk, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZm_Intkz, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZr, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZr_Int, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZr_Intk, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZr_Intkz, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZrb, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZrb_Int, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZrb_Intk, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSZrb_Intkz, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSm, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSm_Int, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSr, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB132SSr_Int, X86_INS_VFMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDYm, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDYr, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128m, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128mb, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128mbk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128mbkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128mk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128mkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128r, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128rk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ128rkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256m, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256mb, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256mbk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256mbkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256mk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256mkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256r, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256rk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZ256rkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZm, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZmb, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZmbk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZmbkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZmk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZmkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZr, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZrb, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZrbk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZrbkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZrk, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDZrkz, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDm, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PDr, X86_INS_VFMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSYm, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSYr, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128m, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128mb, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128mbk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128mbkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128mk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128mkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128r, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128rk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ128rkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256m, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256mb, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256mbk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256mbkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256mk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256mkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256r, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256rk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZ256rkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZm, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZmb, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZmbk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZmbkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZmk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZmkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZr, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZrb, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZrbk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZrbkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZrk, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSZrkz, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSm, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213PSr, X86_INS_VFMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZm, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZm_Int, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZm_Intk, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZm_Intkz, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZr, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZr_Int, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZr_Intk, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZr_Intkz, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZrb, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZrb_Int, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZrb_Intk, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDZrb_Intkz, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDm, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDm_Int, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDr, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SDr_Int, X86_INS_VFMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZm, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZm_Int, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZm_Intk, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZm_Intkz, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZr, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZr_Int, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZr_Intk, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZr_Intkz, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZrb, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZrb_Int, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZrb_Intk, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSZrb_Intkz, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSm, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSm_Int, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSr, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB213SSr_Int, X86_INS_VFMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDYm, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDYr, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128m, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128mb, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128mbk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128mbkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128mk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128mkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128r, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128rk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ128rkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256m, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256mb, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256mbk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256mbkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256mk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256mkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256r, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256rk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZ256rkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZm, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZmb, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZmbk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZmbkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZmk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZmkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZr, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZrb, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZrbk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZrbkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZrk, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDZrkz, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDm, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PDr, X86_INS_VFMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSYm, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSYr, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128m, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128mb, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128mbk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128mbkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128mk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128mkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128r, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128rk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ128rkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256m, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256mb, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256mbk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256mbkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256mk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256mkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256r, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256rk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZ256rkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZm, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZmb, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZmbk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZmbkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZmk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZmkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZr, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZrb, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZrbk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZrbkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZrk, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSZrkz, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSm, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231PSr, X86_INS_VFMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZm, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZm_Int, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZm_Intk, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZm_Intkz, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZr, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZr_Int, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZr_Intk, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZr_Intkz, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZrb, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZrb_Int, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZrb_Intk, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDZrb_Intkz, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDm, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDm_Int, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDr, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SDr_Int, X86_INS_VFMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZm, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZm_Int, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZm_Intk, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZm_Intkz, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZr, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZr_Int, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZr_Intk, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZr_Intkz, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZrb, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZrb_Int, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZrb_Intk, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSZrb_Intkz, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSm, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSm_Int, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSr, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUB231SSr_Int, X86_INS_VFMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDYm, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDYr, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128m, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128mb, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128mbk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128mbkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128mk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128mkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128r, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128rk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ128rkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256m, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256mb, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256mbk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256mbkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256mk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256mkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256r, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256rk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZ256rkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZm, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZmb, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZmbk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZmbkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZmk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZmkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZr, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZrb, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZrbk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZrbkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZrk, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDZrkz, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDm, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PDr, X86_INS_VFMSUBADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSYm, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSYr, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128m, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128mb, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128mbk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128mbkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128mk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128mkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128r, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128rk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ128rkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256m, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256mb, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256mbk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256mbkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256mk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256mkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256r, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256rk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZ256rkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZm, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZmb, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZmbk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZmbkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZmk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZmkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZr, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZrb, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZrbk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZrbkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZrk, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSZrkz, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSm, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD132PSr, X86_INS_VFMSUBADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDYm, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDYr, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128m, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128mb, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128mbk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128mbkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128mk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128mkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128r, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128rk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ128rkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256m, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256mb, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256mbk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256mbkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256mk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256mkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256r, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256rk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZ256rkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZm, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZmb, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZmbk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZmbkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZmk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZmkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZr, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZrb, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZrbk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZrbkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZrk, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDZrkz, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDm, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PDr, X86_INS_VFMSUBADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSYm, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSYr, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128m, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128mb, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128mbk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128mbkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128mk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128mkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128r, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128rk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ128rkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256m, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256mb, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256mbk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256mbkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256mk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256mkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256r, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256rk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZ256rkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZm, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZmb, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZmbk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZmbkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZmk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZmkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZr, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZrb, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZrbk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZrbkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZrk, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSZrkz, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSm, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD213PSr, X86_INS_VFMSUBADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDYm, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDYr, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128m, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128mb, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128mbk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128mbkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128mk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128mkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128r, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128rk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ128rkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256m, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256mb, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256mbk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256mbkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256mk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256mkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256r, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256rk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZ256rkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZm, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZmb, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZmbk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZmbkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZmk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZmkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZr, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZrb, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZrbk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZrbkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZrk, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDZrkz, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDm, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PDr, X86_INS_VFMSUBADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSYm, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSYr, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128m, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128mb, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128mbk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128mbkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128mk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128mkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128r, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128rk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ128rkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256m, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256mb, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256mbk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256mbkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256mk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256mkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256r, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256rk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZ256rkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZm, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZmb, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZmbk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZmbkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZmk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZmkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZr, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZrb, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZrbk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZrbkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZrk, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSZrkz, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSm, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADD231PSr, X86_INS_VFMSUBADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4Ymr, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4Yrm, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4Yrr, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4Yrr_REV, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4mr, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4rm, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4rr, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPD4rr_REV, X86_INS_VFMSUBADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4Ymr, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4Yrm, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4Yrr, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4Yrr_REV, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4mr, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4rm, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4rr, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBADDPS4rr_REV, X86_INS_VFMSUBADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPD4Ymr, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPD4Yrm, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPD4Yrr, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPD4Yrr_REV, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPD4mr, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPD4rm, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPD4rr, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPD4rr_REV, X86_INS_VFMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPS4Ymr, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPS4Yrm, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPS4Yrr, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPS4Yrr_REV, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBPS4mr, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPS4rm, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPS4rr, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBPS4rr_REV, X86_INS_VFMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4mr, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4mr_Int, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4rm, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4rm_Int, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4rr, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4rr_Int, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSD4rr_Int_REV, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBSD4rr_REV, X86_INS_VFMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4mr, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4mr_Int, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4rm, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4rm_Int, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4rr, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4rr_Int, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFMSUBSS4rr_Int_REV, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFMSUBSS4rr_REV, X86_INS_VFMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDYm, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDYr, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128m, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128mb, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128mbk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128mbkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128mk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128mkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128r, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128rk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ128rkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256m, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256mb, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256mbk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256mbkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256mk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256mkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256r, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256rk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZ256rkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZm, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZmb, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZmbk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZmbkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZmk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZmkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZr, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZrb, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZrbk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZrbkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZrk, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDZrkz, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDm, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PDr, X86_INS_VFNMADD132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSYm, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSYr, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128m, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128mb, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128mbk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128mbkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128mk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128mkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128r, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128rk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ128rkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256m, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256mb, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256mbk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256mbkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256mk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256mkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256r, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256rk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZ256rkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZm, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZmb, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZmbk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZmbkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZmk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZmkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZr, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZrb, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZrbk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZrbkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZrk, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSZrkz, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSm, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132PSr, X86_INS_VFNMADD132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZm, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZm_Int, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZm_Intk, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZm_Intkz, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZr, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZr_Int, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZr_Intk, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZr_Intkz, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZrb, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZrb_Int, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZrb_Intk, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDZrb_Intkz, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDm, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDm_Int, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDr, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SDr_Int, X86_INS_VFNMADD132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZm, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZm_Int, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZm_Intk, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZm_Intkz, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZr, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZr_Int, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZr_Intk, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZr_Intkz, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZrb, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZrb_Int, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZrb_Intk, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSZrb_Intkz, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSm, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSm_Int, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSr, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD132SSr_Int, X86_INS_VFNMADD132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDYm, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDYr, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128m, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128mb, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128mbk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128mbkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128mk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128mkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128r, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128rk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ128rkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256m, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256mb, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256mbk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256mbkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256mk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256mkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256r, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256rk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZ256rkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZm, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZmb, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZmbk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZmbkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZmk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZmkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZr, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZrb, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZrbk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZrbkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZrk, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDZrkz, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDm, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PDr, X86_INS_VFNMADD213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSYm, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSYr, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128m, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128mb, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128mbk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128mbkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128mk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128mkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128r, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128rk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ128rkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256m, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256mb, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256mbk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256mbkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256mk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256mkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256r, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256rk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZ256rkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZm, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZmb, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZmbk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZmbkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZmk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZmkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZr, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZrb, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZrbk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZrbkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZrk, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSZrkz, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSm, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213PSr, X86_INS_VFNMADD213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZm, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZm_Int, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZm_Intk, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZm_Intkz, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZr, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZr_Int, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZr_Intk, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZr_Intkz, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZrb, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZrb_Int, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZrb_Intk, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDZrb_Intkz, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDm, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDm_Int, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDr, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SDr_Int, X86_INS_VFNMADD213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZm, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZm_Int, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZm_Intk, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZm_Intkz, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZr, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZr_Int, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZr_Intk, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZr_Intkz, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZrb, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZrb_Int, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZrb_Intk, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSZrb_Intkz, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSm, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSm_Int, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSr, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD213SSr_Int, X86_INS_VFNMADD213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDYm, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDYr, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128m, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128mb, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128mbk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128mbkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128mk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128mkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128r, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128rk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ128rkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256m, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256mb, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256mbk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256mbkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256mk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256mkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256r, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256rk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZ256rkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZm, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZmb, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZmbk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZmbkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZmk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZmkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZr, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZrb, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZrbk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZrbkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZrk, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDZrkz, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDm, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PDr, X86_INS_VFNMADD231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSYm, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSYr, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128m, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128mb, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128mbk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128mbkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128mk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128mkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128r, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128rk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ128rkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256m, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256mb, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256mbk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256mbkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256mk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256mkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256r, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256rk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZ256rkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZm, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZmb, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZmbk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZmbkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZmk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZmkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZr, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZrb, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZrbk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZrbkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZrk, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSZrkz, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSm, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231PSr, X86_INS_VFNMADD231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZm, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZm_Int, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZm_Intk, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZm_Intkz, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZr, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZr_Int, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZr_Intk, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZr_Intkz, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZrb, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZrb_Int, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZrb_Intk, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDZrb_Intkz, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDm, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDm_Int, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDr, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SDr_Int, X86_INS_VFNMADD231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZm, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZm_Int, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZm_Intk, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZm_Intkz, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZr, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZr_Int, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZr_Intk, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZr_Intkz, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZrb, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZrb_Int, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZrb_Intk, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSZrb_Intkz, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSm, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSm_Int, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSr, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADD231SSr_Int, X86_INS_VFNMADD231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPD4Ymr, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPD4Yrm, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPD4Yrr, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPD4Yrr_REV, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPD4mr, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPD4rm, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPD4rr, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPD4rr_REV, X86_INS_VFNMADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPS4Ymr, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPS4Yrm, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPS4Yrr, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPS4Yrr_REV, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDPS4mr, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPS4rm, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPS4rr, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDPS4rr_REV, X86_INS_VFNMADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4mr, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4mr_Int, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4rm, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4rm_Int, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4rr, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4rr_Int, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSD4rr_Int_REV, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDSD4rr_REV, X86_INS_VFNMADDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4mr, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4mr_Int, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4rm, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4rm_Int, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4rr, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4rr_Int, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMADDSS4rr_Int_REV, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMADDSS4rr_REV, X86_INS_VFNMADDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDYm, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDYr, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128m, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128mb, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128mbk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128mbkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128mk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128mkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128r, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128rk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ128rkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256m, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256mb, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256mbk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256mbkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256mk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256mkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256r, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256rk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZ256rkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZm, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZmb, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZmbk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZmbkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZmk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZmkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZr, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZrb, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZrbk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZrbkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZrk, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDZrkz, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDm, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PDr, X86_INS_VFNMSUB132PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSYm, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSYr, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128m, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128mb, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128mbk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128mbkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128mk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128mkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128r, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128rk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ128rkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256m, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256mb, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256mbk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256mbkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256mk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256mkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256r, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256rk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZ256rkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZm, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZmb, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZmbk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZmbkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZmk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZmkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZr, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZrb, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZrbk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZrbkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZrk, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSZrkz, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSm, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132PSr, X86_INS_VFNMSUB132PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZm, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZm_Int, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZm_Intk, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZm_Intkz, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZr, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZr_Int, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZr_Intk, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZr_Intkz, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZrb, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZrb_Int, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZrb_Intk, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDZrb_Intkz, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDm, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDm_Int, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDr, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SDr_Int, X86_INS_VFNMSUB132SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZm, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZm_Int, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZm_Intk, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZm_Intkz, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZr, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZr_Int, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZr_Intk, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZr_Intkz, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZrb, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZrb_Int, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZrb_Intk, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSZrb_Intkz, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSm, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSm_Int, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSr, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB132SSr_Int, X86_INS_VFNMSUB132SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDYm, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDYr, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128m, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128mb, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128mbk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128mbkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128mk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128mkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128r, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128rk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ128rkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256m, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256mb, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256mbk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256mbkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256mk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256mkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256r, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256rk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZ256rkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZm, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZmb, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZmbk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZmbkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZmk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZmkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZr, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZrb, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZrbk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZrbkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZrk, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDZrkz, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDm, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PDr, X86_INS_VFNMSUB213PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSYm, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSYr, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128m, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128mb, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128mbk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128mbkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128mk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128mkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128r, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128rk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ128rkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256m, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256mb, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256mbk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256mbkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256mk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256mkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256r, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256rk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZ256rkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZm, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZmb, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZmbk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZmbkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZmk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZmkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZr, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZrb, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZrbk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZrbkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZrk, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSZrkz, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSm, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213PSr, X86_INS_VFNMSUB213PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZm, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZm_Int, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZm_Intk, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZm_Intkz, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZr, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZr_Int, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZr_Intk, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZr_Intkz, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZrb, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZrb_Int, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZrb_Intk, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDZrb_Intkz, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDm, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDm_Int, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDr, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SDr_Int, X86_INS_VFNMSUB213SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZm, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZm_Int, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZm_Intk, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZm_Intkz, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZr, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZr_Int, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZr_Intk, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZr_Intkz, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZrb, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZrb_Int, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZrb_Intk, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSZrb_Intkz, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSm, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSm_Int, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSr, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB213SSr_Int, X86_INS_VFNMSUB213SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDYm, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDYr, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128m, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128mb, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128mbk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128mbkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128mk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128mkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128r, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128rk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ128rkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256m, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256mb, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256mbk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256mbkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256mk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256mkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256r, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256rk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZ256rkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZm, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZmb, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZmbk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZmbkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZmk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZmkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZr, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZrb, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZrbk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZrbkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZrk, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDZrkz, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDm, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PDr, X86_INS_VFNMSUB231PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSYm, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSYr, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128m, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128mb, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128mbk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128mbkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128mk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128mkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128r, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128rk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ128rkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256m, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256mb, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256mbk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256mbkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256mk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256mkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256r, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256rk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZ256rkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZm, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZmb, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZmbk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZmbkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZmk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZmkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZr, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZrb, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZrbk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZrbkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZrk, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSZrkz, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSm, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231PSr, X86_INS_VFNMSUB231PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZm, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZm_Int, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZm_Intk, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZm_Intkz, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZr, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZr_Int, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZr_Intk, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZr_Intkz, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZrb, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZrb_Int, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZrb_Intk, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDZrb_Intkz, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDm, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDm_Int, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDr, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SDr_Int, X86_INS_VFNMSUB231SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZm, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZm_Int, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZm_Intk, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZm_Intkz, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZr, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZr_Int, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZr_Intk, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZr_Intkz, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZrb, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZrb_Int, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZrb_Intk, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSZrb_Intkz, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSm, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSm_Int, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSr, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUB231SSr_Int, X86_INS_VFNMSUB231SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4Ymr, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4Yrm, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4Yrr, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4Yrr_REV, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4mr, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4rm, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4rr, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPD4rr_REV, X86_INS_VFNMSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4Ymr, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4Yrm, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4Yrr, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4Yrr_REV, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4mr, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4rm, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4rr, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBPS4rr_REV, X86_INS_VFNMSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4mr, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4mr_Int, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4rm, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4rm_Int, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4rr, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4rr_Int, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4rr_Int_REV, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBSD4rr_REV, X86_INS_VFNMSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4mr, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4mr_Int, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4rm, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4rm_Int, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4rr, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4rr_Int, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4rr_Int_REV, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFNMSUBSS4rr_REV, X86_INS_VFNMSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FMA4, 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ128rm, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ128rmb, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ128rmbk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ128rmk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ128rr, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ128rrk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ256rm, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ256rmb, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ256rmbk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ256rmk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ256rr, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZ256rrk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZrm, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZrmb, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZrmbk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZrmk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZrr, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPDZrrk, X86_INS_VFPCLASSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ128rm, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ128rmb, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ128rmbk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ128rmk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ128rr, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ128rrk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ256rm, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ256rmb, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ256rmbk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ256rmk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ256rr, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZ256rrk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZrm, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZrmb, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZrmbk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZrmk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZrr, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSPSZrrk, X86_INS_VFPCLASSPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSDZrm, X86_INS_VFPCLASSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSDZrmk, X86_INS_VFPCLASSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSDZrr, X86_INS_VFPCLASSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSDZrrk, X86_INS_VFPCLASSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSSZrm, X86_INS_VFPCLASSSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSSZrmk, X86_INS_VFPCLASSSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSSZrr, X86_INS_VFPCLASSSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFPCLASSSSZrrk, X86_INS_VFPCLASSSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFRCZPDYrm, X86_INS_VFRCZPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFRCZPDYrr, X86_INS_VFRCZPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFRCZPDrm, X86_INS_VFRCZPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZPDrr, X86_INS_VFRCZPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZPSYrm, X86_INS_VFRCZPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFRCZPSYrr, X86_INS_VFRCZPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VFRCZPSrm, X86_INS_VFRCZPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZPSrr, X86_INS_VFRCZPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZSDrm, X86_INS_VFRCZSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZSDrr, X86_INS_VFRCZSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZSSrm, X86_INS_VFRCZSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VFRCZSSrr, X86_INS_VFRCZSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VGATHERDPDYrm, X86_INS_VGATHERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERDPDZ128rm, X86_INS_VGATHERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERDPDZ256rm, X86_INS_VGATHERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERDPDZrm, X86_INS_VGATHERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VGATHERDPDrm, X86_INS_VGATHERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERDPSYrm, X86_INS_VGATHERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERDPSZ128rm, X86_INS_VGATHERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERDPSZ256rm, X86_INS_VGATHERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERDPSZrm, X86_INS_VGATHERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VGATHERDPSrm, X86_INS_VGATHERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERPF0DPDm, X86_INS_VGATHERPF0DPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF0DPSm, X86_INS_VGATHERPF0DPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF0QPDm, X86_INS_VGATHERPF0QPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF0QPSm, X86_INS_VGATHERPF0QPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF1DPDm, X86_INS_VGATHERPF1DPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF1DPSm, X86_INS_VGATHERPF1DPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF1QPDm, X86_INS_VGATHERPF1QPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERPF1QPSm, X86_INS_VGATHERPF1QPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VGATHERQPDYrm, X86_INS_VGATHERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERQPDZ128rm, X86_INS_VGATHERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERQPDZ256rm, X86_INS_VGATHERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERQPDZrm, X86_INS_VGATHERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VGATHERQPDrm, X86_INS_VGATHERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERQPSYrm, X86_INS_VGATHERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGATHERQPSZ128rm, X86_INS_VGATHERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERQPSZ256rm, X86_INS_VGATHERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGATHERQPSZrm, X86_INS_VGATHERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VGATHERQPSrm, X86_INS_VGATHERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128m, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128mb, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128mbk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128mbkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128mk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128mkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128r, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128rk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ128rkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256m, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256mb, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256mbk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256mbkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256mk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256mkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256r, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256rk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZ256rkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZm, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZmb, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZmbk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZmbkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZmk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZmkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZr, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZrb, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZrbk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZrbkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZrk, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPDZrkz, X86_INS_VGETEXPPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128m, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128mb, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128mbk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128mbkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128mk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128mkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128r, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128rk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ128rkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256m, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256mb, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256mbk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256mbkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256mk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256mkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256r, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256rk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZ256rkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZm, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZmb, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZmbk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZmbkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZmk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZmkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZr, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZrb, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZrbk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZrbkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZrk, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPPSZrkz, X86_INS_VGETEXPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZm, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZmk, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZmkz, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZr, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZrb, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZrbk, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZrbkz, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZrk, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSDZrkz, X86_INS_VGETEXPSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZm, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZmk, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZmkz, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZr, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZrb, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZrbk, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZrbkz, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZrk, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETEXPSSZrkz, X86_INS_VGETEXPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rmbi, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rmbik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rmbikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rmi, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rmik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rmikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rri, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rrik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ128rrikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rmbi, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rmbik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rmbikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rmi, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rmik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rmikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rri, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rrik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZ256rrikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrmbi, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrmbik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrmbikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrmi, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrmik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrmikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrri, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrrib, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrribk, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrribkz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrrik, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPDZrrikz, X86_INS_VGETMANTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rmbi, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rmbik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rmbikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rmi, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rmik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rmikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rri, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rrik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ128rrikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rmbi, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rmbik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rmbikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rmi, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rmik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rmikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rri, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rrik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZ256rrikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrmbi, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrmbik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrmbikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrmi, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrmik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrmikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrri, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrrib, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrribk, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrribkz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrrik, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTPSZrrikz, X86_INS_VGETMANTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrmi, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrmik, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrmikz, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrri, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrrib, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrribk, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrribkz, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrrik, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSDZrrikz, X86_INS_VGETMANTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrmi, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrmik, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrmikz, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrri, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrrib, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrribk, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrribkz, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrrik, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGETMANTSSZrrikz, X86_INS_VGETMANTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBYrmi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBYrri, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rmbi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rmbik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rmbikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rmi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rmik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rmikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rri, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rrik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ128rrikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rmbi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rmbik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rmbikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rmi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rmik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rmikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rri, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rrik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZ256rrikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrmbi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrmbik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrmbikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrmi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrmik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrmikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrri, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrrik, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBZrrikz, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBrmi, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEINVQBrri, X86_INS_VGF2P8AFFINEINVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBYrmi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBYrri, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rmbi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rmbik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rmbikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rmi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rmik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rmikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rri, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rrik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ128rrikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rmbi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rmbik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rmbikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rmi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rmik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rmikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rri, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rrik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZ256rrikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrmbi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrmbik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrmbikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrmi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrmik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrmikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrri, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrrik, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBZrrikz, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBrmi, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8AFFINEQBrri, X86_INS_VGF2P8AFFINEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBYrm, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBYrr, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ128rm, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ128rmk, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ128rmkz, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ128rr, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ128rrk, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ128rrkz, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ256rm, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ256rmk, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ256rmkz, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ256rr, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ256rrk, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZ256rrkz, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZrm, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZrmk, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZrmkz, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZrr, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZrrk, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBZrrkz, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBrm, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VGF2P8MULBrr, X86_INS_VGF2P8MULB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VHADDPDYrm, X86_INS_VHADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPDYrr, X86_INS_VHADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPDrm, X86_INS_VHADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPDrr, X86_INS_VHADDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPSYrm, X86_INS_VHADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPSYrr, X86_INS_VHADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPSrm, X86_INS_VHADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHADDPSrr, X86_INS_VHADDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPDYrm, X86_INS_VHSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPDYrr, X86_INS_VHSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPDrm, X86_INS_VHSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPDrr, X86_INS_VHSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPSYrm, X86_INS_VHSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPSYrr, X86_INS_VHSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPSrm, X86_INS_VHSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VHSUBPSrr, X86_INS_VHSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VINSERTF128rm, X86_INS_VINSERTF128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VINSERTF128rr, X86_INS_VINSERTF128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Z256rm, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Z256rmk, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Z256rmkz, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Z256rr, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Z256rrk, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Z256rrkz, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Zrm, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Zrmk, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Zrmkz, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Zrr, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Zrrk, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x4Zrrkz, X86_INS_VINSERTF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x8Zrm, X86_INS_VINSERTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x8Zrmk, X86_INS_VINSERTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x8Zrmkz, X86_INS_VINSERTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x8Zrr, X86_INS_VINSERTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x8Zrrk, X86_INS_VINSERTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF32x8Zrrkz, X86_INS_VINSERTF32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Z256rm, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Z256rmk, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Z256rmkz, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Z256rr, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Z256rrk, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Z256rrkz, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Zrm, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Zrmk, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Zrmkz, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Zrr, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Zrrk, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x2Zrrkz, X86_INS_VINSERTF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x4Zrm, X86_INS_VINSERTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x4Zrmk, X86_INS_VINSERTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x4Zrmkz, X86_INS_VINSERTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x4Zrr, X86_INS_VINSERTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x4Zrrk, X86_INS_VINSERTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTF64x4Zrrkz, X86_INS_VINSERTF64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI128rm, X86_INS_VINSERTI128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VINSERTI128rr, X86_INS_VINSERTI128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Z256rm, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Z256rmk, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Z256rmkz, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Z256rr, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Z256rrk, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Z256rrkz, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Zrm, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Zrmk, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Zrmkz, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Zrr, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Zrrk, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x4Zrrkz, X86_INS_VINSERTI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x8Zrm, X86_INS_VINSERTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x8Zrmk, X86_INS_VINSERTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x8Zrmkz, X86_INS_VINSERTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x8Zrr, X86_INS_VINSERTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x8Zrrk, X86_INS_VINSERTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI32x8Zrrkz, X86_INS_VINSERTI32X8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Z256rm, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Z256rmk, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Z256rmkz, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Z256rr, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Z256rrk, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Z256rrkz, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Zrm, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Zrmk, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Zrmkz, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Zrr, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Zrrk, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x2Zrrkz, X86_INS_VINSERTI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x4Zrm, X86_INS_VINSERTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x4Zrmk, X86_INS_VINSERTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x4Zrmkz, X86_INS_VINSERTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x4Zrr, X86_INS_VINSERTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x4Zrrk, X86_INS_VINSERTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTI64x4Zrrkz, X86_INS_VINSERTI64X4, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTPSZrm, X86_INS_VINSERTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTPSZrr, X86_INS_VINSERTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VINSERTPSrm, X86_INS_VINSERTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VINSERTPSrr, X86_INS_VINSERTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VLDDQUYrm, X86_INS_VLDDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VLDDQUrm, X86_INS_VLDDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VLDMXCSR, X86_INS_VLDMXCSR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVDQU, X86_INS_VMASKMOVDQU, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMASKMOVDQU64, X86_INS_VMASKMOVDQU, 1, #ifndef CAPSTONE_DIET { X86_REG_RDI, 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMASKMOVPDYmr, X86_INS_VMASKMOVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPDYrm, X86_INS_VMASKMOVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPDmr, X86_INS_VMASKMOVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPDrm, X86_INS_VMASKMOVPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPSYmr, X86_INS_VMASKMOVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPSYrm, X86_INS_VMASKMOVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPSmr, X86_INS_VMASKMOVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMASKMOVPSrm, X86_INS_VMASKMOVPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXCPDYrm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPDYrr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rmb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rmbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rmbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rmk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rmkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rrk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ128rrkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rmb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rmbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rmbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rmk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rmkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rrk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZ256rrkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrmb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrmbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrmbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrmk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrmkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrrk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDZrrkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPDrm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPDrr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPSYrm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPSYrr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rmb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rmbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rmbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rmk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rmkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rrk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ128rrkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rmb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rmbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rmbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rmk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rmkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rrk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZ256rrkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrmb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrmbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrmbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrmk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrmkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrrk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSZrrkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCPSrm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCPSrr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXCSDZrm, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCSDZrr, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCSDrm, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXCSDrr, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXCSSZrm, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCSSZrr, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXCSSrm, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXCSSrr, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXPDYrm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPDYrr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rmb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rmbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rmbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rmk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rmkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rrk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ128rrkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rmb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rmbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rmbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rmk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rmkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rrk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZ256rrkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPDZrm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrmb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrmbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrmbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrmk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrmkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrrb, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXPDZrrbk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXPDZrrbkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXPDZrrk, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDZrrkz, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPDrm, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPDrr, X86_INS_VMAXPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPSYrm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPSYrr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rmb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rmbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rmbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rmk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rmkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rrk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ128rrkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rmb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rmbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rmbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rmk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rmkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rrk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZ256rrkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMAXPSZrm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrmb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrmbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrmbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrmk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrmkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrrb, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXPSZrrbk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXPSZrrbkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXPSZrrk, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSZrrkz, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXPSrm, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXPSrr, X86_INS_VMAXPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMAXSDZrm, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrm_Int, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrm_Intk, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrm_Intkz, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrr, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrr_Int, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrr_Intk, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrr_Intkz, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSDZrrb_Int, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXSDZrrb_Intk, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXSDZrrb_Intkz, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXSDrm, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSDrm_Int, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSDrr, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSDrr_Int, X86_INS_VMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSSZrm, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrm_Int, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrm_Intk, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrm_Intkz, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrr, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrr_Int, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrr_Intk, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrr_Intkz, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMAXSSZrrb_Int, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXSSZrrb_Intk, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXSSZrrb_Intkz, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMAXSSrm, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSSrm_Int, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSSrr, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMAXSSrr_Int, X86_INS_VMAXSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMCALL, X86_INS_VMCALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMCLEARm, X86_INS_VMCLEAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMFUNC, X86_INS_VMFUNC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMINCPDYrm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPDYrr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rmb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rmbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rmbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rmk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rmkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rrk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ128rrkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rmb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rmbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rmbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rmk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rmkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rrk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZ256rrkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrmb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrmbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrmbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrmk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrmkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrrk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDZrrkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPDrm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPDrr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPSYrm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPSYrr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rmb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rmbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rmbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rmk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rmkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rrk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ128rrkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rmb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rmbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rmbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rmk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rmkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rrk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZ256rrkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrmb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrmbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrmbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrmk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrmkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrrk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSZrrkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCPSrm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCPSrr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINCSDZrm, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCSDZrr, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCSDrm, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINCSDrr, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINCSSZrm, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCSSZrr, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINCSSrm, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINCSSrr, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINPDYrm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPDYrr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rmb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rmbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rmbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rmk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rmkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rrk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ128rrkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rmb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rmbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rmbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rmk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rmkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rrk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZ256rrkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPDZrm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrmb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrmbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrmbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrmk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrmkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrrb, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINPDZrrbk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINPDZrrbkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINPDZrrk, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDZrrkz, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPDrm, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPDrr, X86_INS_VMINPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPSYrm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPSYrr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rmb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rmbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rmbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rmk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rmkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rrk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ128rrkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rmb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rmbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rmbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rmk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rmkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rrk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZ256rrkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMINPSZrm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrmb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrmbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrmbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrmk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrmkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrrb, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINPSZrrbk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINPSZrrbkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINPSZrrk, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSZrrkz, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINPSrm, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINPSrr, X86_INS_VMINPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMINSDZrm, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrm_Int, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrm_Intk, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrm_Intkz, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrr, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrr_Int, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrr_Intk, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrr_Intkz, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSDZrrb_Int, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINSDZrrb_Intk, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINSDZrrb_Intkz, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINSDrm, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSDrm_Int, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSDrr, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSDrr_Int, X86_INS_VMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSSZrm, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrm_Int, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrm_Intk, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrm_Intkz, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrr, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrr_Int, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrr_Intk, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrr_Intkz, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMINSSZrrb_Int, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINSSZrrb_Intk, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINSSZrrb_Intkz, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMINSSrm, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSSrm_Int, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSSrr, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMINSSrr_Int, X86_INS_VMINSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMLAUNCH, X86_INS_VMLAUNCH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMLOAD32, X86_INS_VMLOAD, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMLOAD64, X86_INS_VMLOAD, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMMCALL, X86_INS_VMMCALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMOV64toPQIZrm, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOV64toPQIZrr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOV64toPQIrm, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOV64toPQIrr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOV64toSDZrm, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOV64toSDZrr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOV64toSDrm, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOV64toSDrr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVAPDYmr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDYrm, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDYrr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDYrr_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128mr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128mrk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rm, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rmk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rmkz, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rr_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rrk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rrk_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rrkz, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ128rrkz_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256mr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256mrk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rm, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rmk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rmkz, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rr_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rrk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rrk_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rrkz, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDZ256rrkz_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZmr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZmrk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrm, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrmk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrmkz, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrr_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZrrk, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrrk_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDZrrkz, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPDZrrkz_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPDmr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDrm, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDrr, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPDrr_REV, X86_INS_VMOVAPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVAPSYmr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSYrm, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSYrr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSYrr_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128mr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128mrk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rm, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rmk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rmkz, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rr_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rrk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rrk_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rrkz, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ128rrkz_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256mr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256mrk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rm, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rmk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rmkz, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rr_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rrk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rrk_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rrkz, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSZ256rrkz_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZmr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZmrk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrm, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrmk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrmkz, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrr_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZrrk, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrrk_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSZrrkz, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVAPSZrrkz_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVAPSmr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSrm, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSrr, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVAPSrr_REV, X86_INS_VMOVAPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDDUPYrm, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDDUPYrr, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ128rm, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ128rmk, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ128rmkz, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ128rr, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ128rrk, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ128rrkz, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ256rm, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ256rmk, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ256rmkz, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ256rr, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ256rrk, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZ256rrkz, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZrm, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDDUPZrmk, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZrmkz, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZrr, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDDUPZrrk, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPZrrkz, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDDUPrm, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDDUPrr, X86_INS_VMOVDDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDI2PDIZrm, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDI2PDIZrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDI2PDIrm, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDI2PDIrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDI2SSZrm, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDI2SSZrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDI2SSrm, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDI2SSrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128mr, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128mrk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rm, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rmk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rmkz, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rr, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rr_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rrk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rrk_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rrkz, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z128rrkz_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256mr, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256mrk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rm, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rmk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rmkz, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rr, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rr_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rrk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rrk_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rrkz, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Z256rrkz_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zmr, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zmrk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrm, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrmk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrmkz, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrr, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrr_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrrk, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrrk_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrrkz, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA32Zrrkz_REV, X86_INS_VMOVDQA32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128mr, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128mrk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rm, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rmk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rmkz, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rr, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rr_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rrk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rrk_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rrkz, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z128rrkz_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256mr, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256mrk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rm, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rmk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rmkz, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rr, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rr_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rrk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rrk_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rrkz, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Z256rrkz_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zmr, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zmrk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrm, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrmk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrmkz, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrr, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrr_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrrk, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrrk_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrrkz, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQA64Zrrkz_REV, X86_INS_VMOVDQA64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQAYmr, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQAYrm, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQAYrr, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQAYrr_REV, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQAmr, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQArm, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQArr, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQArr_REV, X86_INS_VMOVDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128mr, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128mrk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rm, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rmk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rmkz, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rr, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rr_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rrk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rrk_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rrkz, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z128rrkz_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256mr, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256mrk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rm, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rmk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rmkz, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rr, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rr_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rrk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rrk_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rrkz, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Z256rrkz_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zmr, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zmrk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrm, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrmk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrmkz, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrr, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrr_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrrk, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrrk_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrrkz, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU16Zrrkz_REV, X86_INS_VMOVDQU16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128mr, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128mrk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rm, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rmk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rmkz, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rr, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rr_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rrk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rrk_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rrkz, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z128rrkz_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256mr, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256mrk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rm, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rmk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rmkz, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rr, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rr_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rrk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rrk_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rrkz, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Z256rrkz_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zmr, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zmrk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrm, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrmk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrmkz, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrr, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrr_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrrk, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrrk_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrrkz, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU32Zrrkz_REV, X86_INS_VMOVDQU32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128mr, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128mrk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rm, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rmk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rmkz, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rr, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rr_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rrk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rrk_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rrkz, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z128rrkz_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256mr, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256mrk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rm, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rmk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rmkz, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rr, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rr_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rrk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rrk_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rrkz, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Z256rrkz_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zmr, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zmrk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrm, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrmk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrmkz, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrr, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrr_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrrk, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrrk_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrrkz, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVDQU64Zrrkz_REV, X86_INS_VMOVDQU64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128mr, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128mrk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rm, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rmk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rmkz, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rr, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rr_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rrk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rrk_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rrkz, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z128rrkz_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256mr, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256mrk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rm, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rmk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rmkz, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rr, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rr_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rrk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rrk_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rrkz, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Z256rrkz_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zmr, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zmrk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrm, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrmk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrmkz, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrr, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrr_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrrk, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrrk_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrrkz, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VMOVDQU8Zrrkz_REV, X86_INS_VMOVDQU8, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVDQUYmr, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUYrm, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUYrr, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUYrr_REV, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUmr, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUrm, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUrr, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVDQUrr_REV, X86_INS_VMOVDQU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVHLPSZrr, X86_INS_VMOVHLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVHLPSrr, X86_INS_VMOVHLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVHPDZ128mr, X86_INS_VMOVHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVHPDZ128rm, X86_INS_VMOVHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVHPDmr, X86_INS_VMOVHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVHPDrm, X86_INS_VMOVHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVHPSZ128mr, X86_INS_VMOVHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVHPSZ128rm, X86_INS_VMOVHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVHPSmr, X86_INS_VMOVHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVHPSrm, X86_INS_VMOVHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVLHPSZrr, X86_INS_VMOVLHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVLHPSrr, X86_INS_VMOVLHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVLPDZ128mr, X86_INS_VMOVLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVLPDZ128rm, X86_INS_VMOVLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVLPDmr, X86_INS_VMOVLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVLPDrm, X86_INS_VMOVLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVLPSZ128mr, X86_INS_VMOVLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVLPSZ128rm, X86_INS_VMOVLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVLPSmr, X86_INS_VMOVLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVLPSrm, X86_INS_VMOVLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVMSKPDYrr, X86_INS_VMOVMSKPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVMSKPDrr, X86_INS_VMOVMSKPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVMSKPSYrr, X86_INS_VMOVMSKPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVMSKPSrr, X86_INS_VMOVMSKPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQAYrm, X86_INS_VMOVNTDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VMOVNTDQAZ128rm, X86_INS_VMOVNTDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQAZ256rm, X86_INS_VMOVNTDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQAZrm, X86_INS_VMOVNTDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVNTDQArm, X86_INS_VMOVNTDQA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQYmr, X86_INS_VMOVNTDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQZ128mr, X86_INS_VMOVNTDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQZ256mr, X86_INS_VMOVNTDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTDQZmr, X86_INS_VMOVNTDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVNTDQmr, X86_INS_VMOVNTDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPDYmr, X86_INS_VMOVNTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPDZ128mr, X86_INS_VMOVNTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPDZ256mr, X86_INS_VMOVNTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPDZmr, X86_INS_VMOVNTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVNTPDmr, X86_INS_VMOVNTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPSYmr, X86_INS_VMOVNTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPSZ128mr, X86_INS_VMOVNTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPSZ256mr, X86_INS_VMOVNTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVNTPSZmr, X86_INS_VMOVNTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVNTPSmr, X86_INS_VMOVNTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVPDI2DIZmr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVPDI2DIZrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVPDI2DImr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVPDI2DIrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVPQI2QIZmr, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVPQI2QIZrr, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVPQI2QImr, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVPQI2QIrr, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVPQIto64Zmr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMOVPQIto64Zrr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMOVPQIto64mr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVPQIto64rr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVQI2PQIZrm, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVQI2PQIrm, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSDZmr, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDZmrk, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDZrm, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDZrmk, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSDZrmkz, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSDZrr, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDZrr_REV, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDZrrk, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDZrrk_REV, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSDZrrkz, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSDZrrkz_REV, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSDmr, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSDrm, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSDrr, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSDrr_REV, X86_INS_VMOVSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSDto64Zmr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDto64Zrr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSDto64mr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSDto64rr, X86_INS_VMOVQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSHDUPYrm, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSHDUPYrr, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ128rm, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ128rmk, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ128rmkz, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ128rr, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ128rrk, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ128rrkz, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ256rm, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ256rmk, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ256rmkz, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ256rr, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ256rrk, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZ256rrkz, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZrm, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZrmk, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZrmkz, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZrr, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZrrk, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPZrrkz, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSHDUPrm, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSHDUPrr, X86_INS_VMOVSHDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSLDUPYrm, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSLDUPYrr, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ128rm, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ128rmk, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ128rmkz, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ128rr, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ128rrk, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ128rrkz, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ256rm, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ256rmk, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ256rmkz, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ256rr, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ256rrk, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZ256rrkz, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZrm, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZrmk, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZrmkz, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZrr, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZrrk, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPZrrkz, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSLDUPrm, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSLDUPrr, X86_INS_VMOVSLDUP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSS2DIZmr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSS2DIZrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSS2DImr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSS2DIrr, X86_INS_VMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSSZmr, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSSZmrk, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSSZrm, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSSZrmk, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSSZrmkz, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSSZrr, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSSZrr_REV, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSSZrrk, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVSSZrrk_REV, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSSZrrkz, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSSZrrkz_REV, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVSSmr, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSSrm, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSSrr, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVSSrr_REV, X86_INS_VMOVSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVUPDYmr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDYrm, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDYrr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDYrr_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128mr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128mrk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rm, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rmk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rmkz, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rr_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rrk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rrk_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rrkz, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ128rrkz_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256mr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256mrk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rm, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rmk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rmkz, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rr_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rrk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rrk_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rrkz, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDZ256rrkz_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZmr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZmrk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrm, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrmk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrmkz, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrr_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZrrk, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrrk_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDZrrkz, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPDZrrkz_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPDmr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDrm, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDrr, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPDrr_REV, X86_INS_VMOVUPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVUPSYmr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSYrm, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSYrr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSYrr_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128mr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128mrk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rm, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rmk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rmkz, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rr_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rrk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rrk_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rrkz, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ128rrkz_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256mr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256mrk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rm, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rmk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rmkz, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rr_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rrk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rrk_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rrkz, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSZ256rrkz_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZmr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZmrk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrm, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrmk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrmkz, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrr_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZrrk, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrrk_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSZrrkz, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVUPSZrrkz_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMOVUPSmr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSrm, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSrr, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMOVUPSrr_REV, X86_INS_VMOVUPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMOVZPQILo2PQIZrr, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMOVZPQILo2PQIrr, X86_INS_VMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMPSADBWYrmi, X86_INS_VMPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VMPSADBWYrri, X86_INS_VMPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VMPSADBWrmi, X86_INS_VMPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMPSADBWrri, X86_INS_VMPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMPTRLDm, X86_INS_VMPTRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMPTRSTm, X86_INS_VMPTRST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMREAD32mr, X86_INS_VMREAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMREAD32rr, X86_INS_VMREAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMREAD64mr, X86_INS_VMREAD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMREAD64rr, X86_INS_VMREAD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMRESUME, X86_INS_VMRESUME, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMRUN32, X86_INS_VMRUN, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMRUN64, X86_INS_VMRUN, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMSAVE32, X86_INS_VMSAVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMSAVE64, X86_INS_VMSAVE, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMULPDYrm, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPDYrr, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rm, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rmb, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rmbk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rmbkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rmk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rmkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rr, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rrk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ128rrkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rm, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rmb, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rmbk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rmbkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rmk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rmkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rr, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rrk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZ256rrkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPDZrm, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrmb, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrmbk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrmbkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrmk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrmkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrr, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrrb, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULPDZrrbk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULPDZrrbkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULPDZrrk, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDZrrkz, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPDrm, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPDrr, X86_INS_VMULPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPSYrm, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPSYrr, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rm, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rmb, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rmbk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rmbkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rmk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rmkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rr, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rrk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ128rrkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rm, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rmb, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rmbk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rmbkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rmk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rmkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rr, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rrk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZ256rrkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VMULPSZrm, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrmb, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrmbk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrmbkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrmk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrmkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrr, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrrb, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULPSZrrbk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULPSZrrbkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULPSZrrk, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSZrrkz, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULPSrm, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULPSrr, X86_INS_VMULPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VMULSDZrm, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrm_Int, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrm_Intk, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrm_Intkz, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrr, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrr_Int, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrr_Intk, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrr_Intkz, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSDZrrb_Int, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULSDZrrb_Intk, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULSDZrrb_Intkz, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULSDrm, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSDrm_Int, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSDrr, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSDrr_Int, X86_INS_VMULSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSSZrm, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrm_Int, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrm_Intk, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrm_Intkz, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrr, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrr_Int, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrr_Intk, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrr_Intkz, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VMULSSZrrb_Int, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULSSZrrb_Intk, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULSSZrrb_Intkz, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMULSSrm, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSSrm_Int, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSSrr, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMULSSrr_Int, X86_INS_VMULSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VMWRITE32rm, X86_INS_VMWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMWRITE32rr, X86_INS_VMWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMWRITE64rm, X86_INS_VMWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMWRITE64rr, X86_INS_VMWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMXOFF, X86_INS_VMXOFF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMXON, X86_INS_VMXON, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VORPDYrm, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPDYrr, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPDZ128rm, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rmb, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rmbk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rmbkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rmk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rmkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rr, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rrk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ128rrkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rm, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rmb, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rmbk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rmbkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rmk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rmkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rr, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rrk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZ256rrkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrm, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrmb, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrmbk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrmbkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrmk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrmkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrr, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrrk, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDZrrkz, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPDrm, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPDrr, X86_INS_VORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPSYrm, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPSYrr, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPSZ128rm, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rmb, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rmbk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rmbkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rmk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rmkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rr, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rrk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ128rrkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rm, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rmb, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rmbk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rmbkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rmk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rmkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rr, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rrk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZ256rrkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrm, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrmb, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrmbk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrmbkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrmk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrmkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrr, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrrk, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSZrrkz, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VORPSrm, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VORPSrr, X86_INS_VORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VP4DPWSSDSrm, X86_INS_VP4DPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VP4DPWSSDSrmk, X86_INS_VP4DPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VP4DPWSSDSrmkz, X86_INS_VP4DPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VP4DPWSSDrm, X86_INS_VP4DPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VP4DPWSSDrmk, X86_INS_VP4DPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VP4DPWSSDrmkz, X86_INS_VP4DPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBYrm, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBYrr, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ128rm, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ128rmk, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ128rmkz, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ128rr, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ128rrk, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ128rrkz, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ256rm, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ256rmk, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ256rmkz, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ256rr, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ256rrk, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZ256rrkz, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZrm, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZrmk, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZrmkz, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZrr, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZrrk, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBZrrkz, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBrm, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSBrr, X86_INS_VPABSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDYrm, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDYrr, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rm, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rmb, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rmbk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rmbkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rmk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rmkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rr, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rrk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ128rrkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rm, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rmb, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rmbk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rmbkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rmk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rmkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rr, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rrk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZ256rrkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDZrm, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrmb, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrmbk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrmbkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrmk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrmkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrr, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrrk, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDZrrkz, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSDrm, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSDrr, X86_INS_VPABSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rm, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rmb, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rmbk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rmbkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rmk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rmkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rr, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rrk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ128rrkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rm, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rmb, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rmbk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rmbkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rmk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rmkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rr, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rrk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZ256rrkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSQZrm, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrmb, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrmbk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrmbkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrmk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrmkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrr, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrrk, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSQZrrkz, X86_INS_VPABSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPABSWYrm, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWYrr, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ128rm, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ128rmk, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ128rmkz, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ128rr, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ128rrk, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ128rrkz, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ256rm, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ256rmk, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ256rmkz, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ256rr, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ256rrk, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZ256rrkz, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZrm, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZrmk, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZrmkz, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZrr, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZrrk, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWZrrkz, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWrm, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPABSWrr, X86_INS_VPABSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWYrm, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKSSDWYrr, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rm, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rmb, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rmbk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rmbkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rmk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rmkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rr, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rrk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ128rrkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rm, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rmb, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rmbk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rmbkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rmk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rmkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rr, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rrk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZ256rrkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrm, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrmb, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrmbk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrmbkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrmk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrmkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrr, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrrk, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWZrrkz, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSDWrm, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKSSDWrr, X86_INS_VPACKSSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKSSWBYrm, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKSSWBYrr, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ128rm, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ128rmk, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ128rmkz, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ128rr, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ128rrk, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ128rrkz, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ256rm, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ256rmk, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ256rmkz, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ256rr, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ256rrk, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZ256rrkz, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZrm, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZrmk, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZrmkz, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZrr, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZrrk, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBZrrkz, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKSSWBrm, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKSSWBrr, X86_INS_VPACKSSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKUSDWYrm, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKUSDWYrr, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rm, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rmb, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rmbk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rmbkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rmk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rmkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rr, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rrk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ128rrkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rm, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rmb, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rmbk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rmbkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rmk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rmkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rr, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rrk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZ256rrkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrm, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrmb, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrmbk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrmbkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrmk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrmkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrr, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrrk, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWZrrkz, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSDWrm, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKUSDWrr, X86_INS_VPACKUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKUSWBYrm, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKUSWBYrr, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ128rm, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ128rmk, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ128rmkz, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ128rr, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ128rrk, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ128rrkz, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ256rm, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ256rmk, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ256rmkz, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ256rr, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ256rrk, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZ256rrkz, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZrm, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZrmk, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZrmkz, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZrr, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZrrk, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBZrrkz, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPACKUSWBrm, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPACKUSWBrr, X86_INS_VPACKUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDBYrm, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDBYrr, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ128rm, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ128rmk, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ128rmkz, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ128rr, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ128rrk, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ128rrkz, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ256rm, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ256rmk, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ256rmkz, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ256rr, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ256rrk, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZ256rrkz, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDBZrm, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDBZrmk, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDBZrmkz, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDBZrr, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDBZrrk, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDBZrrkz, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDBrm, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDBrr, X86_INS_VPADDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDDYrm, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDDYrr, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rm, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rmb, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rmbk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rmbkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rmk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rmkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rr, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rrk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ128rrkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rm, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rmb, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rmbk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rmbkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rmk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rmkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rr, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rrk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZ256rrkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDDZrm, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrmb, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrmbk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrmbkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrmk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrmkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrr, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrrk, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDZrrkz, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDDrm, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDDrr, X86_INS_VPADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDQYrm, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDQYrr, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rm, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rmb, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rmbk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rmbkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rmk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rmkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rr, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rrk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ128rrkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rm, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rmb, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rmbk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rmbkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rmk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rmkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rr, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rrk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZ256rrkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDQZrm, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrmb, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrmbk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrmbkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrmk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrmkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrr, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrrk, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQZrrkz, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPADDQrm, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDQrr, X86_INS_VPADDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDSBYrm, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDSBYrr, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDSBZ128rm, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ128rmk, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ128rmkz, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ128rr, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ128rrk, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ128rrkz, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ256rm, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ256rmk, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ256rmkz, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ256rr, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ256rrk, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZ256rrkz, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZrm, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZrmk, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZrmkz, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZrr, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZrrk, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBZrrkz, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSBrm, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDSBrr, X86_INS_VPADDSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDSWYrm, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDSWYrr, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDSWZ128rm, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ128rmk, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ128rmkz, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ128rr, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ128rrk, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ128rrkz, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ256rm, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ256rmk, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ256rmkz, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ256rr, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ256rrk, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZ256rrkz, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZrm, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZrmk, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZrmkz, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZrr, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZrrk, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWZrrkz, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDSWrm, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDSWrr, X86_INS_VPADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDUSBYrm, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDUSBYrr, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDUSBZ128rm, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ128rmk, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ128rmkz, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ128rr, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ128rrk, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ128rrkz, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ256rm, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ256rmk, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ256rmkz, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ256rr, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ256rrk, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZ256rrkz, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZrm, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZrmk, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZrmkz, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZrr, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZrrk, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBZrrkz, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSBrm, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDUSBrr, X86_INS_VPADDUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDUSWYrm, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDUSWYrr, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPADDUSWZ128rm, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ128rmk, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ128rmkz, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ128rr, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ128rrk, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ128rrkz, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ256rm, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ256rmk, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ256rmkz, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ256rr, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ256rrk, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZ256rrkz, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZrm, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZrmk, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZrmkz, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZrr, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZrrk, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWZrrkz, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPADDUSWrm, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDUSWrr, X86_INS_VPADDUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPADDWYrm, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDWYrr, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ128rm, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ128rmk, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ128rmkz, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ128rr, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ128rrk, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ128rrkz, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ256rm, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ256rmk, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ256rmkz, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ256rr, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ256rrk, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZ256rrkz, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPADDWZrm, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDWZrmk, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDWZrmkz, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDWZrr, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDWZrrk, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDWZrrkz, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPADDWrm, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPADDWrr, X86_INS_VPADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPALIGNRYrmi, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRYrri, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ128rmi, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ128rmik, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ128rmikz, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ128rri, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ128rrik, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ128rrikz, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ256rmi, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ256rmik, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ256rmikz, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ256rri, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ256rrik, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZ256rrikz, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZrmi, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZrmik, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZrmikz, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZrri, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZrrik, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRZrrikz, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRrmi, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPALIGNRrri, X86_INS_VPALIGNR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPANDDZ128rm, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rmb, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rmbk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rmbkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rmk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rmkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rr, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rrk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ128rrkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rm, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rmb, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rmbk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rmbkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rmk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rmkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rr, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rrk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZ256rrkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDDZrm, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrmb, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrmbk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrmbkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrmk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrmkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrr, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrrk, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDDZrrkz, X86_INS_VPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rm, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rmb, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rmbk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rmbkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rmk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rmkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rr, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rrk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ128rrkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rm, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rmb, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rmbk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rmbkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rmk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rmkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rr, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rrk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZ256rrkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNDZrm, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrmb, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrmbk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrmbkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrmk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrmkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrr, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrrk, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNDZrrkz, X86_INS_VPANDND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rm, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rmb, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rmbk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rmbkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rmk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rmkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rr, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rrk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ128rrkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rm, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rmb, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rmbk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rmbkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rmk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rmkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rr, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rrk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZ256rrkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDNQZrm, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrmb, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrmbk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrmbkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrmk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrmkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrr, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrrk, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNQZrrkz, X86_INS_VPANDNQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDNYrm, X86_INS_VPANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDNYrr, X86_INS_VPANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDNrm, X86_INS_VPANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDNrr, X86_INS_VPANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rm, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rmb, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rmbk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rmbkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rmk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rmkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rr, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rrk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ128rrkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rm, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rmb, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rmbk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rmbkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rmk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rmkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rr, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rrk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZ256rrkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPANDQZrm, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrmb, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrmbk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrmbkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrmk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrmkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrr, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrrk, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDQZrrkz, X86_INS_VPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPANDYrm, X86_INS_VPAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDYrr, X86_INS_VPAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDrm, X86_INS_VPAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPANDrr, X86_INS_VPAND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPAVGBYrm, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPAVGBYrr, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPAVGBZ128rm, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ128rmk, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ128rmkz, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ128rr, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ128rrk, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ128rrkz, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ256rm, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ256rmk, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ256rmkz, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ256rr, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ256rrk, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZ256rrkz, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZrm, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZrmk, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZrmkz, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZrr, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZrrk, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBZrrkz, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGBrm, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPAVGBrr, X86_INS_VPAVGB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPAVGWYrm, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPAVGWYrr, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPAVGWZ128rm, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ128rmk, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ128rmkz, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ128rr, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ128rrk, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ128rrkz, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ256rm, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ256rmk, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ256rmkz, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ256rr, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ256rrk, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZ256rrkz, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZrm, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZrmk, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZrmkz, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZrr, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZrrk, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWZrrkz, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPAVGWrm, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPAVGWrr, X86_INS_VPAVGW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPBLENDDYrmi, X86_INS_VPBLENDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDDYrri, X86_INS_VPBLENDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDDrmi, X86_INS_VPBLENDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDDrri, X86_INS_VPBLENDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ128rm, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ128rmk, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ128rmkz, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ128rr, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ128rrk, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ128rrkz, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ256rm, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ256rmk, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ256rmkz, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ256rr, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ256rrk, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZ256rrkz, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZrm, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZrmk, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZrmkz, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZrr, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZrrk, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMBZrrkz, X86_INS_VPBLENDMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rm, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rmb, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rmbk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rmbkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rmk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rmkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rr, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rrk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ128rrkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rm, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rmb, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rmbk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rmbkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rmk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rmkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rr, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rrk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZ256rrkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrm, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrmb, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrmbk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrmbkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrmk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrmkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrr, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrrk, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMDZrrkz, X86_INS_VPBLENDMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rm, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rmb, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rmbk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rmbkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rmk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rmkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rr, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rrk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ128rrkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rm, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rmb, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rmbk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rmbkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rmk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rmkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rr, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rrk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZ256rrkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrm, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrmb, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrmbk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrmbkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrmk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrmkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrr, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrrk, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMQZrrkz, X86_INS_VPBLENDMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ128rm, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ128rmk, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ128rmkz, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ128rr, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ128rrk, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ128rrkz, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ256rm, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ256rmk, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ256rmkz, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ256rr, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ256rrk, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZ256rrkz, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZrm, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZrmk, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZrmkz, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZrr, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZrrk, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDMWZrrkz, X86_INS_VPBLENDMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBLENDVBYrm, X86_INS_VPBLENDVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDVBYrr, X86_INS_VPBLENDVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDVBrm, X86_INS_VPBLENDVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPBLENDVBrr, X86_INS_VPBLENDVB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPBLENDWYrmi, X86_INS_VPBLENDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDWYrri, X86_INS_VPBLENDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBLENDWrmi, X86_INS_VPBLENDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPBLENDWrri, X86_INS_VPBLENDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBYrm, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBYrr, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ128m, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ128mk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ128mkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ128r, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ128rk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ128rkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ256m, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ256mk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ256mkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ256r, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ256rk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZ256rkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZm, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZmk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZmkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZr, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZrk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBZrkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZ128r, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZ128rk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZ128rkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZ256r, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZ256rk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZ256rkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZr, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZrk, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrZrkz, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrm, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTBrr, X86_INS_VPBROADCASTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDYrm, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDYrr, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ128m, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ128mk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ128mkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ128r, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ128rk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ128rkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ256m, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ256mk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ256mkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ256r, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ256rk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZ256rkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZm, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZmk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZmkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZr, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZrk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDZrkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZ128r, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZ128rk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZ128rkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZ256r, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZ256rk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZ256rkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZr, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZrk, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrZrkz, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrm, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTDrr, X86_INS_VPBROADCASTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTMB2QZ128rr, X86_INS_VPBROADCASTMB2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTMB2QZ256rr, X86_INS_VPBROADCASTMB2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTMB2QZrr, X86_INS_VPBROADCASTMB2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTMW2DZ128rr, X86_INS_VPBROADCASTMW2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTMW2DZ256rr, X86_INS_VPBROADCASTMW2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTMW2DZrr, X86_INS_VPBROADCASTMW2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQYrm, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQYrr, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ128m, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ128mk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ128mkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ128r, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ128rk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ128rkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ256m, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ256mk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ256mkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ256r, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ256rk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZ256rkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZm, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZmk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZmkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZr, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZrk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQZrkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZ128r, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZ128rk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZ128rkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZ256r, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZ256rk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZ256rkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZr, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZrk, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrZrkz, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrm, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTQrr, X86_INS_VPBROADCASTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWYrm, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWYrr, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ128m, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ128mk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ128mkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ128r, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ128rk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ128rkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ256m, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ256mk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ256mkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ256r, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ256rk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZ256rkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZm, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZmk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZmkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZr, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZrk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWZrkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZ128r, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZ128rk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZ128rkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZ256r, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZ256rk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZ256rkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZr, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZrk, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrZrkz, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrm, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPBROADCASTWrr, X86_INS_VPBROADCASTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPCLMULQDQYrm, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQYrr, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQZ128rm, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQZ128rr, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQZ256rm, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQZ256rr, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQZrm, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQZrr, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCLMULQDQrm, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0 #endif }, { X86_VPCLMULQDQrr, X86_INS_VPCLMULQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_PCLMUL, 0 }, 0, 0 #endif }, { X86_VPCMOVYrmr, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVYrrm, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVYrrr, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVYrrr_REV, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVrmr, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVrrm, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVrrr, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMOVrrr_REV, X86_INS_VPCMOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rmi_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rmik_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rri_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ128rrik_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rmi_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rmik_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rri_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZ256rrik_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPBZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrmi_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrmik_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrri_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPBZrrik_alt, X86_INS_VPCMPB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmi_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmib_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmibk_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rmik_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rri_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ128rrik_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmi_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmib_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmibk_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rmik_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rri_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZ256rrik_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmi_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmib_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmibk_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrmik_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrri_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPDZrrik_alt, X86_INS_VPCMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQBYrm, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBYrr, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ128rm, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ128rmk, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ128rr, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ128rrk, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ256rm, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ256rmk, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ256rr, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZ256rrk, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZrm, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZrmk, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZrr, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQBZrrk, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQBrm, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQBrr, X86_INS_VPCMPEQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDYrm, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDYrr, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ128rm, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ128rmb, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ128rmbk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ128rmk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ128rr, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ128rrk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ256rm, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ256rmb, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ256rmbk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ256rmk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ256rr, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZ256rrk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZrm, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZrmb, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZrmbk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZrmk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZrr, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQDZrrk, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQDrm, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQDrr, X86_INS_VPCMPEQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQYrm, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPCMPEQQYrr, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ128rm, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ128rmb, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ128rmbk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ128rmk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ128rr, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ128rrk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ256rm, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ256rmb, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ256rmbk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ256rmk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ256rr, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZ256rrk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZrm, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZrmb, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZrmbk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZrmk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZrr, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQQZrrk, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPEQQrm, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQQrr, X86_INS_VPCMPEQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWYrm, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWYrr, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ128rm, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ128rmk, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ128rr, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ128rrk, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ256rm, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ256rmk, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ256rr, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZ256rrk, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZrm, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZrmk, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZrr, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQWZrrk, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPEQWrm, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPEQWrr, X86_INS_VPCMPEQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPESTRIrm, X86_INS_VPCMPESTRI, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPCMPESTRIrr, X86_INS_VPCMPESTRI, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPCMPESTRMrm, X86_INS_VPCMPESTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMPESTRMrr, X86_INS_VPCMPESTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMPGTBYrm, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBYrr, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ128rm, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ128rmk, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ128rr, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ128rrk, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ256rm, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ256rmk, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ256rr, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZ256rrk, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZrm, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZrmk, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZrr, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTBZrrk, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTBrm, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTBrr, X86_INS_VPCMPGTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDYrm, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDYrr, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ128rm, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ128rmb, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ128rmbk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ128rmk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ128rr, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ128rrk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ256rm, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ256rmb, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ256rmbk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ256rmk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ256rr, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZ256rrk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZrm, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZrmb, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZrmbk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZrmk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZrr, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTDZrrk, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTDrm, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTDrr, X86_INS_VPCMPGTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQYrm, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPCMPGTQYrr, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ128rm, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ128rmb, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ128rmbk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ128rmk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ128rr, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ128rrk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ256rm, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ256rmb, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ256rmbk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ256rmk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ256rr, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZ256rrk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZrm, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZrmb, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZrmbk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZrmk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZrr, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTQZrrk, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPGTQrm, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPCMPGTQrr, X86_INS_VPCMPGTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWYrm, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWYrr, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ128rm, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ128rmk, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ128rr, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ128rrk, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ256rm, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ256rmk, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ256rr, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZ256rrk, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZrm, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZrmk, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZrr, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTWZrrk, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPGTWrm, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPGTWrr, X86_INS_VPCMPGTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPCMPISTRIrm, X86_INS_VPCMPISTRI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPCMPISTRIrr, X86_INS_VPCMPISTRI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_ECX, X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPCMPISTRMrm, X86_INS_VPCMPISTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMPISTRMrr, X86_INS_VPCMPISTRM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmi_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmib_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmibk_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rmik_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rri_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ128rrik_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmi_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmib_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmibk_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rmik_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rri_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZ256rrik_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmi_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmib_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmibk_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrmik_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrri_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPQZrrik_alt, X86_INS_VPCMPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rmi_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rmik_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rri_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ128rrik_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rmi_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rmik_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rri_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZ256rrik_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrmi_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrmik_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrri_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUBZrrik_alt, X86_INS_VPCMPUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmi_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmib_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmibk_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rmik_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rri_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ128rrik_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmi_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmib_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmibk_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rmik_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rri_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZ256rrik_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmi_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmib_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmibk_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrmik_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrri_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUDZrrik_alt, X86_INS_VPCMPUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmi_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmib_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmibk_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rmik_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rri_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ128rrik_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmi_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmib_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmibk_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rmik_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rri_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZ256rrik_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmi_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmib, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmib_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmibk, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmibk_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrmik_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrri_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUQZrrik_alt, X86_INS_VPCMPUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rmi_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rmik_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rri_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ128rrik_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rmi_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rmik_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rri_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZ256rrik_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrmi_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrmik_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrri_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPUWZrrik_alt, X86_INS_VPCMPUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rmi_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rmik_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rri_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ128rrik_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rmi_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rmik_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rri_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZ256rrik_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCMPWZrmi, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrmi_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrmik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrmik_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrri, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrri_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrrik, X86_INS_VPCMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCMPWZrrik_alt, X86_INS_VPCMPW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPCOMBmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMBmi_alt, X86_INS_VPCOMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMBri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMBri_alt, X86_INS_VPCOMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMDmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMDmi_alt, X86_INS_VPCOMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMDri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMDri_alt, X86_INS_VPCOMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ128mr, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ128mrk, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ128rr, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ128rrk, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ128rrkz, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ256mr, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ256mrk, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ256rr, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ256rrk, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZ256rrkz, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZmr, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZmrk, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZrr, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZrrk, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSBZrrkz, X86_INS_VPCOMPRESSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ128mr, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ128mrk, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ128rr, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ128rrk, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ128rrkz, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ256mr, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ256mrk, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ256rr, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ256rrk, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZ256rrkz, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZmr, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZmrk, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZrr, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZrrk, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSDZrrkz, X86_INS_VPCOMPRESSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ128mr, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ128mrk, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ128rr, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ128rrk, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ128rrkz, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ256mr, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ256mrk, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ256rr, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ256rrk, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZ256rrkz, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZmr, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZmrk, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZrr, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZrrk, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSQZrrkz, X86_INS_VPCOMPRESSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ128mr, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ128mrk, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ128rr, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ128rrk, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ128rrkz, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ256mr, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ256mrk, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ256rr, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ256rrk, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZ256rrkz, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZmr, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZmrk, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZrr, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZrrk, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMPRESSWZrrkz, X86_INS_VPCOMPRESSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCOMQmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMQmi_alt, X86_INS_VPCOMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMQri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMQri_alt, X86_INS_VPCOMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUBmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUBmi_alt, X86_INS_VPCOMUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUBri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUBri_alt, X86_INS_VPCOMUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUDmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUDmi_alt, X86_INS_VPCOMUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUDri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUDri_alt, X86_INS_VPCOMUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUQmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUQmi_alt, X86_INS_VPCOMUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUQri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUQri_alt, X86_INS_VPCOMUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUWmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUWmi_alt, X86_INS_VPCOMUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUWri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMUWri_alt, X86_INS_VPCOMUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMWmi, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMWmi_alt, X86_INS_VPCOMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMWri, X86_INS_VPCOM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCOMWri_alt, X86_INS_VPCOMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rm, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rmb, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rmbk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rmbkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rmk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rmkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rr, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rrk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ128rrkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rm, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rmb, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rmbk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rmbkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rmk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rmkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rr, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rrk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZ256rrkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrm, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrmb, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrmbk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrmbkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrmk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrmkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrr, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrrk, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTDZrrkz, X86_INS_VPCONFLICTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rm, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rmb, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rmbk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rmbkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rmk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rmkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rr, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rrk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ128rrkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rm, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rmb, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rmbk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rmbkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rmk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rmkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rr, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rrk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZ256rrkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrm, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrmb, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrmbk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrmbkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrmk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrmkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrr, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrrk, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPCONFLICTQZrrkz, X86_INS_VPCONFLICTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128m, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128mb, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128mbk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128mbkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128mk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128mkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128r, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128rk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ128rkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256m, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256mb, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256mbk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256mbkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256mk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256mkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256r, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256rk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZ256rkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZm, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZmb, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZmbk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZmbkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZmk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZmkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZr, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZrk, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDSZrkz, X86_INS_VPDPBUSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128m, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128mb, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128mbk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128mbkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128mk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128mkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128r, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128rk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ128rkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256m, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256mb, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256mbk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256mbkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256mk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256mkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256r, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256rk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZ256rkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZm, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZmb, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZmbk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZmbkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZmk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZmkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZr, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZrk, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPBUSDZrkz, X86_INS_VPDPBUSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128m, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128mb, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128mbk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128mbkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128mk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128mkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128r, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128rk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ128rkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256m, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256mb, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256mbk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256mbkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256mk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256mkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256r, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256rk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZ256rkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZm, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZmb, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZmbk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZmbkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZmk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZmkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZr, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZrk, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDSZrkz, X86_INS_VPDPWSSDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128m, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128mb, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128mbk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128mbkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128mk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128mkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128r, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128rk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ128rkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256m, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256mb, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256mbk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256mbkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256mk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256mkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256r, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256rk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZ256rkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZm, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZmb, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZmbk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZmbkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZmk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZmkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZr, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZrk, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPDPWSSDZrkz, X86_INS_VPDPWSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERM2F128rm, X86_INS_VPERM2F128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERM2F128rr, X86_INS_VPERM2F128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERM2I128rm, X86_INS_VPERM2I128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERM2I128rr, X86_INS_VPERM2I128, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMBZ128rm, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ128rmk, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ128rmkz, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ128rr, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ128rrk, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ128rrkz, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ256rm, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ256rmk, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ256rmkz, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ256rr, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ256rrk, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZ256rrkz, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZrm, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZrmk, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZrmkz, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZrr, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZrrk, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMBZrrkz, X86_INS_VPERMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDYrm, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMDYrr, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMDZ256rm, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rmb, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rmbk, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rmbkz, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rmk, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rmkz, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rr, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rrk, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZ256rrkz, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrm, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMDZrmb, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrmbk, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrmbkz, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrmk, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrmkz, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrr, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMDZrrk, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMDZrrkz, X86_INS_VPERMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B128rm, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B128rmk, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B128rmkz, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B128rr, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B128rrk, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B128rrkz, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B256rm, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B256rmk, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B256rmkz, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B256rr, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B256rrk, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2B256rrkz, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Brm, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Brmk, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Brmkz, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Brr, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Brrk, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Brrkz, X86_INS_VPERMI2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rm, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rmb, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rmbk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rmbkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rmk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rmkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rr, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rrk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D128rrkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rm, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rmb, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rmbk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rmbkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rmk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rmkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rr, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rrk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2D256rrkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Drm, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Drmb, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Drmbk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Drmbkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Drmk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Drmkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Drr, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Drrk, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Drrkz, X86_INS_VPERMI2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rm, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rmb, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rmbk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rmbkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rmk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rmkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rr, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rrk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD128rrkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rm, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rmb, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rmbk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rmbkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rmk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rmkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rr, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rrk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PD256rrkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PDrm, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PDrmb, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PDrmbk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PDrmbkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PDrmk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PDrmkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PDrr, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PDrrk, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PDrrkz, X86_INS_VPERMI2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rm, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rmb, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rmbk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rmbkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rmk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rmkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rr, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rrk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS128rrkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rm, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rmb, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rmbk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rmbkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rmk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rmkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rr, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rrk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PS256rrkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PSrm, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PSrmb, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PSrmbk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PSrmbkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2PSrmk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PSrmkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PSrr, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PSrrk, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2PSrrkz, X86_INS_VPERMI2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rm, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rmb, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rmbk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rmbkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rmk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rmkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rr, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rrk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q128rrkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rm, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rmb, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rmbk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rmbkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rmk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rmkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rr, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rrk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Q256rrkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Qrm, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Qrmb, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Qrmbk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Qrmbkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Qrmk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Qrmkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Qrr, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Qrrk, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2Qrrkz, X86_INS_VPERMI2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMI2W128rm, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W128rmk, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W128rmkz, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W128rr, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W128rrk, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W128rrkz, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W256rm, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W256rmk, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W256rmkz, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W256rr, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W256rrk, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2W256rrkz, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Wrm, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Wrmk, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Wrmkz, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Wrr, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Wrrk, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMI2Wrrkz, X86_INS_VPERMI2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PDYmr, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PDYrm, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PDYrr, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PDYrr_REV, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PDmr, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPERMIL2PDrm, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPERMIL2PDrr, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPERMIL2PDrr_REV, X86_INS_VPERMIL2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PSYmr, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PSYrm, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PSYrr, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PSYrr_REV, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMIL2PSmr, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPERMIL2PSrm, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPERMIL2PSrr, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPERMIL2PSrr_REV, X86_INS_VPERMIL2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDYmi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDYri, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDYrm, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDYrr, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128mbi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128mbik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128mbikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128mi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128mik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128mikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128ri, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rm, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rmb, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rmbk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rmbkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rmk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rmkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rr, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rrk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ128rrkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256mbi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256mbik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256mbikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256mi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256mik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256mikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256ri, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rm, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rmb, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rmbk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rmbkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rmk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rmkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rr, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rrk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZ256rrkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZmbi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZmbik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZmbikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZmi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPDZmik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZmikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZri, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPDZrik, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrikz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrm, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPDZrmb, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrmbk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrmbkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrmk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrmkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrr, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPDZrrk, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDZrrkz, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPDmi, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDri, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDrm, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPDrr, X86_INS_VPERMILPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSYmi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSYri, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSYrm, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSYrr, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128mbi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128mbik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128mbikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128mi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128mik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128mikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128ri, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rm, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rmb, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rmbk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rmbkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rmk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rmkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rr, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rrk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ128rrkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256mbi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256mbik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256mbikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256mi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256mik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256mikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256ri, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rm, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rmb, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rmbk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rmbkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rmk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rmkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rr, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rrk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZ256rrkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZmbi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZmbik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZmbikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZmi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPSZmik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZmikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZri, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPSZrik, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrikz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrm, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPSZrmb, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrmbk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrmbkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrmk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrmkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrr, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMILPSZrrk, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSZrrkz, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMILPSmi, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSri, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSrm, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMILPSrr, X86_INS_VPERMILPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPERMPDYmi, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMPDYri, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMPDZ256mbi, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256mbik, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256mbikz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256mi, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256mik, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256mikz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256ri, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rik, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rikz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rm, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rmb, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rmbk, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rmbkz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rmk, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rmkz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rr, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rrk, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZ256rrkz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZmbi, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZmbik, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZmbikz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZmi, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMPDZmik, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZmikz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZri, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMPDZrik, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrikz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrm, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMPDZrmb, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrmbk, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrmbkz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrmk, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrmkz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrr, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMPDZrrk, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPDZrrkz, X86_INS_VPERMPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSYrm, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMPSYrr, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rm, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rmb, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rmbk, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rmbkz, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rmk, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rmkz, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rr, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rrk, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZ256rrkz, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrm, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMPSZrmb, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrmbk, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrmbkz, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrmk, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrmkz, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrr, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMPSZrrk, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMPSZrrkz, X86_INS_VPERMPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQYmi, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMQYri, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPERMQZ256mbi, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256mbik, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256mbikz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256mi, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256mik, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256mikz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256ri, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rik, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rikz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rm, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rmb, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rmbk, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rmbkz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rmk, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rmkz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rr, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rrk, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZ256rrkz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZmbi, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZmbik, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZmbikz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZmi, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMQZmik, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZmikz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZri, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMQZrik, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrikz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrm, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMQZrmb, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrmbk, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrmbkz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrmk, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrmkz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrr, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMQZrrk, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMQZrrkz, X86_INS_VPERMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B128rm, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B128rmk, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B128rmkz, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B128rr, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B128rrk, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B128rrkz, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B256rm, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B256rmk, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B256rmkz, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B256rr, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B256rrk, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2B256rrkz, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Brm, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Brmk, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Brmkz, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Brr, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Brrk, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Brrkz, X86_INS_VPERMT2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rm, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rmb, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rmbk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rmbkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rmk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rmkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rr, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rrk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D128rrkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rm, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rmb, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rmbk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rmbkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rmk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rmkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rr, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rrk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2D256rrkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Drm, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Drmb, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Drmbk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Drmbkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Drmk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Drmkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Drr, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Drrk, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Drrkz, X86_INS_VPERMT2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rm, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rmb, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rmbk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rmbkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rmk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rmkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rr, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rrk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD128rrkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rm, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rmb, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rmbk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rmbkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rmk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rmkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rr, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rrk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PD256rrkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PDrm, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PDrmb, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PDrmbk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PDrmbkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PDrmk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PDrmkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PDrr, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PDrrk, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PDrrkz, X86_INS_VPERMT2PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rm, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rmb, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rmbk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rmbkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rmk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rmkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rr, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rrk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS128rrkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rm, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rmb, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rmbk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rmbkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rmk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rmkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rr, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rrk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PS256rrkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PSrm, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PSrmb, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PSrmbk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PSrmbkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2PSrmk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PSrmkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PSrr, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PSrrk, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2PSrrkz, X86_INS_VPERMT2PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rm, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rmb, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rmbk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rmbkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rmk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rmkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rr, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rrk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q128rrkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rm, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rmb, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rmbk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rmbkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rmk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rmkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rr, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rrk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Q256rrkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Qrm, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Qrmb, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Qrmbk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Qrmbkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Qrmk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Qrmkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Qrr, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Qrrk, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2Qrrkz, X86_INS_VPERMT2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPERMT2W128rm, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W128rmk, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W128rmkz, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W128rr, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W128rrk, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W128rrkz, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W256rm, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W256rmk, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W256rmkz, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W256rr, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W256rrk, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2W256rrkz, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Wrm, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Wrmk, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Wrmkz, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Wrr, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Wrrk, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMT2Wrrkz, X86_INS_VPERMT2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ128rm, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ128rmk, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ128rmkz, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ128rr, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ128rrk, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ128rrkz, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ256rm, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ256rmk, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ256rmkz, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ256rr, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ256rrk, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZ256rrkz, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZrm, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZrmk, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZrmkz, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZrr, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZrrk, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPERMWZrrkz, X86_INS_VPERMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ128rm, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ128rmk, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ128rmkz, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ128rr, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ128rrk, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ128rrkz, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ256rm, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ256rmk, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ256rmkz, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ256rr, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ256rrk, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZ256rrkz, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZrm, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZrmk, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZrmkz, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZrr, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZrrk, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDBZrrkz, X86_INS_VPEXPANDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ128rm, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ128rmk, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ128rmkz, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ128rr, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ128rrk, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ128rrkz, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ256rm, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ256rmk, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ256rmkz, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ256rr, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ256rrk, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZ256rrkz, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZrm, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZrmk, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZrmkz, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZrr, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDDZrrk, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDDZrrkz, X86_INS_VPEXPANDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ128rm, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ128rmk, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ128rmkz, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ128rr, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ128rrk, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ128rrkz, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ256rm, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ256rmk, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ256rmkz, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ256rr, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ256rrk, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZ256rrkz, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZrm, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDQZrmk, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZrmkz, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZrr, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDQZrrk, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDQZrrkz, X86_INS_VPEXPANDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ128rm, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ128rmk, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ128rmkz, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ128rr, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ128rrk, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ128rrkz, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ256rm, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ256rmk, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ256rmkz, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ256rr, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ256rrk, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZ256rrkz, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZrm, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZrmk, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZrmkz, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZrr, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZrrk, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXPANDWZrrkz, X86_INS_VPEXPANDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRBZmr, X86_INS_VPEXTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRBZrr, X86_INS_VPEXTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRBmr, X86_INS_VPEXTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRBrr, X86_INS_VPEXTRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRDZmr, X86_INS_VPEXTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRDZrr, X86_INS_VPEXTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRDmr, X86_INS_VPEXTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRDrr, X86_INS_VPEXTRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRQZmr, X86_INS_VPEXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRQZrr, X86_INS_VPEXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRQmr, X86_INS_VPEXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRQrr, X86_INS_VPEXTRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRWZmr, X86_INS_VPEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRWZrr, X86_INS_VPEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRWZrr_REV, X86_INS_VPEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRWmr, X86_INS_VPEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPEXTRWrr, X86_INS_VPEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPEXTRWrr_REV, X86_INS_VPEXTRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPGATHERDDYrm, X86_INS_VPGATHERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERDDZ128rm, X86_INS_VPGATHERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERDDZ256rm, X86_INS_VPGATHERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERDDZrm, X86_INS_VPGATHERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPGATHERDDrm, X86_INS_VPGATHERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERDQYrm, X86_INS_VPGATHERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERDQZ128rm, X86_INS_VPGATHERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERDQZ256rm, X86_INS_VPGATHERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERDQZrm, X86_INS_VPGATHERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPGATHERDQrm, X86_INS_VPGATHERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERQDYrm, X86_INS_VPGATHERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERQDZ128rm, X86_INS_VPGATHERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERQDZ256rm, X86_INS_VPGATHERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERQDZrm, X86_INS_VPGATHERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPGATHERQDrm, X86_INS_VPGATHERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERQQYrm, X86_INS_VPGATHERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPGATHERQQZ128rm, X86_INS_VPGATHERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERQQZ256rm, X86_INS_VPGATHERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPGATHERQQZrm, X86_INS_VPGATHERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPGATHERQQrm, X86_INS_VPGATHERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHADDBDrm, X86_INS_VPHADDBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDBDrr, X86_INS_VPHADDBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDBQrm, X86_INS_VPHADDBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDBQrr, X86_INS_VPHADDBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDBWrm, X86_INS_VPHADDBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDBWrr, X86_INS_VPHADDBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDDQrm, X86_INS_VPHADDDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDDQrr, X86_INS_VPHADDDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDDYrm, X86_INS_VPHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHADDDYrr, X86_INS_VPHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHADDDrm, X86_INS_VPHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHADDDrr, X86_INS_VPHADDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHADDSWYrm, X86_INS_VPHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHADDSWYrr, X86_INS_VPHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHADDSWrm, X86_INS_VPHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHADDSWrr, X86_INS_VPHADDSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHADDUBDrm, X86_INS_VPHADDUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUBDrr, X86_INS_VPHADDUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUBQrm, X86_INS_VPHADDUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUBQrr, X86_INS_VPHADDUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUBWrm, X86_INS_VPHADDUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUBWrr, X86_INS_VPHADDUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUDQrm, X86_INS_VPHADDUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUDQrr, X86_INS_VPHADDUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUWDrm, X86_INS_VPHADDUWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUWDrr, X86_INS_VPHADDUWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUWQrm, X86_INS_VPHADDUWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDUWQrr, X86_INS_VPHADDUWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDWDrm, X86_INS_VPHADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDWDrr, X86_INS_VPHADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDWQrm, X86_INS_VPHADDWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDWQrr, X86_INS_VPHADDWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHADDWYrm, X86_INS_VPHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHADDWYrr, X86_INS_VPHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHADDWrm, X86_INS_VPHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHADDWrr, X86_INS_VPHADDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHMINPOSUWrm, X86_INS_VPHMINPOSUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHMINPOSUWrr, X86_INS_VPHMINPOSUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHSUBBWrm, X86_INS_VPHSUBBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHSUBBWrr, X86_INS_VPHSUBBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHSUBDQrm, X86_INS_VPHSUBDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHSUBDQrr, X86_INS_VPHSUBDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHSUBDYrm, X86_INS_VPHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHSUBDYrr, X86_INS_VPHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHSUBDrm, X86_INS_VPHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHSUBDrr, X86_INS_VPHSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHSUBSWYrm, X86_INS_VPHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHSUBSWYrr, X86_INS_VPHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHSUBSWrm, X86_INS_VPHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHSUBSWrr, X86_INS_VPHSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPHSUBWDrm, X86_INS_VPHSUBWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHSUBWDrr, X86_INS_VPHSUBWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPHSUBWYrm, X86_INS_VPHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHSUBWYrr, X86_INS_VPHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPHSUBWrm, X86_INS_VPHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPHSUBWrr, X86_INS_VPHSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRBZrm, X86_INS_VPINSRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRBZrr, X86_INS_VPINSRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRBrm, X86_INS_VPINSRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRBrr, X86_INS_VPINSRB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRDZrm, X86_INS_VPINSRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRDZrr, X86_INS_VPINSRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRDrm, X86_INS_VPINSRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRDrr, X86_INS_VPINSRD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRQZrm, X86_INS_VPINSRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRQZrr, X86_INS_VPINSRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRQrm, X86_INS_VPINSRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRQrr, X86_INS_VPINSRQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPINSRWZrm, X86_INS_VPINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRWZrr, X86_INS_VPINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRWrm, X86_INS_VPINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPINSRWrr, X86_INS_VPINSRW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rm, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rmb, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rmbk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rmbkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rmk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rmkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rr, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rrk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ128rrkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rm, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rmb, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rmbk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rmbkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rmk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rmkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rr, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rrk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZ256rrkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrm, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrmb, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrmbk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrmbkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrmk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrmkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrr, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrrk, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTDZrrkz, X86_INS_VPLZCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rm, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rmb, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rmbk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rmbkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rmk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rmkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rr, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rrk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ128rrkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rm, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rmb, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rmbk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rmbkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rmk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rmkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rr, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rrk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZ256rrkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrm, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrmb, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrmbk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrmbkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrmk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrmkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrr, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrrk, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPLZCNTQZrrkz, X86_INS_VPLZCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMACSDDrm, X86_INS_VPMACSDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSDDrr, X86_INS_VPMACSDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSDQHrm, X86_INS_VPMACSDQH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSDQHrr, X86_INS_VPMACSDQH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSDQLrm, X86_INS_VPMACSDQL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSDQLrr, X86_INS_VPMACSDQL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSDDrm, X86_INS_VPMACSSDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSDDrr, X86_INS_VPMACSSDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSDQHrm, X86_INS_VPMACSSDQH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSDQHrr, X86_INS_VPMACSSDQH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSDQLrm, X86_INS_VPMACSSDQL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSDQLrr, X86_INS_VPMACSSDQL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSWDrm, X86_INS_VPMACSSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSWDrr, X86_INS_VPMACSSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSWWrm, X86_INS_VPMACSSWW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSSWWrr, X86_INS_VPMACSSWW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSWDrm, X86_INS_VPMACSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSWDrr, X86_INS_VPMACSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSWWrm, X86_INS_VPMACSWW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMACSWWrr, X86_INS_VPMACSWW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMADCSSWDrm, X86_INS_VPMADCSSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMADCSSWDrr, X86_INS_VPMADCSSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMADCSWDrm, X86_INS_VPMADCSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMADCSWDrr, X86_INS_VPMADCSWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128m, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128mb, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128mbk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128mbkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128mk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128mkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128r, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128rk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ128rkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256m, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256mb, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256mbk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256mbkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256mk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256mkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256r, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256rk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZ256rkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZm, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZmb, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZmbk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZmbkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZmk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZmkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZr, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZrk, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52HUQZrkz, X86_INS_VPMADD52HUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128m, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128mb, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128mbk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128mbkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128mk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128mkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128r, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128rk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ128rkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256m, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256mb, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256mbk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256mbkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256mk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256mkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256r, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256rk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZ256rkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZm, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZmb, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZmbk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZmbkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZmk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZmkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZr, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZrk, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADD52LUQZrkz, X86_INS_VPMADD52LUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWYrm, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWYrr, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ128rm, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ128rmk, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ128rmkz, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ128rr, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ128rrk, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ128rrkz, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ256rm, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ256rmk, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ256rmkz, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ256rr, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ256rrk, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZ256rrkz, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZrm, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZrmk, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZrmkz, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZrr, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZrrk, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWZrrkz, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWrm, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDUBSWrr, X86_INS_VPMADDUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDYrm, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMADDWDYrr, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMADDWDZ128rm, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ128rmk, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ128rmkz, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ128rr, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ128rrk, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ128rrkz, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ256rm, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ256rmk, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ256rmkz, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ256rr, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ256rrk, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZ256rrkz, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZrm, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZrmk, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZrmkz, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZrr, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZrrk, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDZrrkz, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMADDWDrm, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMADDWDrr, X86_INS_VPMADDWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMASKMOVDYmr, X86_INS_VPMASKMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVDYrm, X86_INS_VPMASKMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVDmr, X86_INS_VPMASKMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVDrm, X86_INS_VPMASKMOVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVQYmr, X86_INS_VPMASKMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVQYrm, X86_INS_VPMASKMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVQmr, X86_INS_VPMASKMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMASKMOVQrm, X86_INS_VPMASKMOVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMAXSBYrm, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBYrr, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ128rm, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ128rmk, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ128rmkz, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ128rr, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ128rrk, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ128rrkz, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ256rm, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ256rmk, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ256rmkz, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ256rr, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ256rrk, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZ256rrkz, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBZrm, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSBZrmk, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSBZrmkz, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSBZrr, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSBZrrk, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSBZrrkz, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSBrm, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSBrr, X86_INS_VPMAXSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDYrm, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDYrr, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rm, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rmb, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rmbk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rmbkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rmk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rmkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rr, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rrk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ128rrkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rm, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rmb, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rmbk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rmbkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rmk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rmkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rr, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rrk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZ256rrkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrm, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrmb, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrmbk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrmbkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrmk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrmkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrr, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrrk, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDZrrkz, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSDrm, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSDrr, X86_INS_VPMAXSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rm, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rmb, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rmbk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rmbkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rmk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rmkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rr, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rrk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ128rrkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rm, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rmb, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rmbk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rmbkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rmk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rmkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rr, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rrk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZ256rrkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrm, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrmb, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrmbk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrmbkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrmk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrmkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrr, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrrk, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSQZrrkz, X86_INS_VPMAXSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXSWYrm, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWYrr, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ128rm, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ128rmk, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ128rmkz, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ128rr, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ128rrk, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ128rrkz, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ256rm, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ256rmk, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ256rmkz, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ256rr, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ256rrk, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZ256rrkz, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWZrm, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSWZrmk, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSWZrmkz, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSWZrr, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSWZrrk, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSWZrrkz, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXSWrm, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXSWrr, X86_INS_VPMAXSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBYrm, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBYrr, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ128rm, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ128rmk, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ128rmkz, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ128rr, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ128rrk, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ128rrkz, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ256rm, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ256rmk, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ256rmkz, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ256rr, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ256rrk, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZ256rrkz, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBZrm, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUBZrmk, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUBZrmkz, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUBZrr, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUBZrrk, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUBZrrkz, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUBrm, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUBrr, X86_INS_VPMAXUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDYrm, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDYrr, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rm, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rmb, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rmbk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rmbkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rmk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rmkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rr, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rrk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ128rrkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rm, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rmb, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rmbk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rmbkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rmk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rmkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rr, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rrk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZ256rrkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrm, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrmb, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrmbk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrmbkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrmk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrmkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrr, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrrk, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDZrrkz, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUDrm, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUDrr, X86_INS_VPMAXUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rm, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rmb, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rmbk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rmbkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rmk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rmkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rr, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rrk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ128rrkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rm, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rmb, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rmbk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rmbkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rmk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rmkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rr, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rrk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZ256rrkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrm, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrmb, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrmbk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrmbkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrmk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrmkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrr, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrrk, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUQZrrkz, X86_INS_VPMAXUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMAXUWYrm, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWYrr, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ128rm, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ128rmk, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ128rmkz, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ128rr, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ128rrk, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ128rrkz, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ256rm, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ256rmk, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ256rmkz, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ256rr, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ256rrk, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZ256rrkz, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWZrm, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUWZrmk, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUWZrmkz, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUWZrr, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUWZrrk, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUWZrrkz, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMAXUWrm, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMAXUWrr, X86_INS_VPMAXUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSBYrm, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSBYrr, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ128rm, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ128rmk, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ128rmkz, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ128rr, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ128rrk, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ128rrkz, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ256rm, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ256rmk, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ256rmkz, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ256rr, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ256rrk, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZ256rrkz, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSBZrm, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSBZrmk, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSBZrmkz, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSBZrr, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSBZrrk, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSBZrrkz, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSBrm, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSBrr, X86_INS_VPMINSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSDYrm, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSDYrr, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rm, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rmb, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rmbk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rmbkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rmk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rmkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rr, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rrk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ128rrkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rm, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rmb, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rmbk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rmbkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rmk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rmkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rr, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rrk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZ256rrkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSDZrm, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrmb, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrmbk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrmbkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrmk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrmkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrr, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrrk, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDZrrkz, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSDrm, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSDrr, X86_INS_VPMINSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rm, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rmb, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rmbk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rmbkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rmk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rmkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rr, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rrk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ128rrkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rm, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rmb, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rmbk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rmbkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rmk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rmkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rr, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rrk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZ256rrkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSQZrm, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrmb, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrmbk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrmbkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrmk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrmkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrr, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrrk, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSQZrrkz, X86_INS_VPMINSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINSWYrm, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSWYrr, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ128rm, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ128rmk, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ128rmkz, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ128rr, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ128rrk, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ128rrkz, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ256rm, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ256rmk, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ256rmkz, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ256rr, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ256rrk, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZ256rrkz, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINSWZrm, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSWZrmk, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSWZrmkz, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSWZrr, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSWZrrk, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSWZrrkz, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINSWrm, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINSWrr, X86_INS_VPMINSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUBYrm, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUBYrr, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ128rm, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ128rmk, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ128rmkz, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ128rr, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ128rrk, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ128rrkz, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ256rm, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ256rmk, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ256rmkz, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ256rr, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ256rrk, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZ256rrkz, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUBZrm, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUBZrmk, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUBZrmkz, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUBZrr, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUBZrrk, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUBZrrkz, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUBrm, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUBrr, X86_INS_VPMINUB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUDYrm, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUDYrr, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rm, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rmb, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rmbk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rmbkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rmk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rmkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rr, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rrk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ128rrkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rm, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rmb, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rmbk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rmbkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rmk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rmkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rr, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rrk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZ256rrkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUDZrm, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrmb, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrmbk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrmbkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrmk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrmkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrr, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrrk, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDZrrkz, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUDrm, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUDrr, X86_INS_VPMINUD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rm, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rmb, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rmbk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rmbkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rmk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rmkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rr, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rrk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ128rrkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rm, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rmb, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rmbk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rmbkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rmk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rmkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rr, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rrk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZ256rrkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUQZrm, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrmb, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrmbk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrmbkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrmk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrmkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrr, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrrk, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUQZrrkz, X86_INS_VPMINUQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMINUWYrm, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUWYrr, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ128rm, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ128rmk, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ128rmkz, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ128rr, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ128rrk, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ128rrkz, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ256rm, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ256rmk, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ256rmkz, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ256rr, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ256rrk, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZ256rrkz, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMINUWZrm, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUWZrmk, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUWZrmkz, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUWZrr, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUWZrrk, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUWZrrkz, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMINUWrm, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMINUWrr, X86_INS_VPMINUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMOVB2MZ128rr, X86_INS_VPMOVB2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVB2MZ256rr, X86_INS_VPMOVB2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVB2MZrr, X86_INS_VPMOVB2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVD2MZ128rr, X86_INS_VPMOVD2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVD2MZ256rr, X86_INS_VPMOVD2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVD2MZrr, X86_INS_VPMOVD2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ128mr, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ128mrk, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ128rr, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ128rrk, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ128rrkz, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ256mr, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ256mrk, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ256rr, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ256rrk, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZ256rrkz, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZmr, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZmrk, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZrr, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZrrk, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDBZrrkz, X86_INS_VPMOVDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ128mr, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ128mrk, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ128rr, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ128rrk, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ128rrkz, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ256mr, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ256mrk, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ256rr, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ256rrk, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZ256rrkz, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZmr, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZmrk, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZrr, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZrrk, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVDWZrrkz, X86_INS_VPMOVDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVM2BZ128rr, X86_INS_VPMOVM2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2BZ256rr, X86_INS_VPMOVM2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2BZrr, X86_INS_VPMOVM2B, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMOVM2DZ128rr, X86_INS_VPMOVM2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2DZ256rr, X86_INS_VPMOVM2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2DZrr, X86_INS_VPMOVM2D, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMOVM2QZ128rr, X86_INS_VPMOVM2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2QZ256rr, X86_INS_VPMOVM2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2QZrr, X86_INS_VPMOVM2Q, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMOVM2WZ128rr, X86_INS_VPMOVM2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2WZ256rr, X86_INS_VPMOVM2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMOVM2WZrr, X86_INS_VPMOVM2W, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMOVMSKBYrr, X86_INS_VPMOVMSKB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVMSKBrr, X86_INS_VPMOVMSKB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVQ2MZ128rr, X86_INS_VPMOVQ2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQ2MZ256rr, X86_INS_VPMOVQ2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQ2MZrr, X86_INS_VPMOVQ2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ128mr, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ128mrk, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ128rr, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ128rrk, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ128rrkz, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ256mr, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ256mrk, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ256rr, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ256rrk, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZ256rrkz, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZmr, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZmrk, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZrr, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZrrk, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQBZrrkz, X86_INS_VPMOVQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ128mr, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ128mrk, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ128rr, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ128rrk, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ128rrkz, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ256mr, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ256mrk, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ256rr, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ256rrk, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZ256rrkz, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZmr, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZmrk, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZrr, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZrrk, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQDZrrkz, X86_INS_VPMOVQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ128mr, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ128mrk, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ128rr, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ128rrk, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ128rrkz, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ256mr, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ256mrk, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ256rr, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ256rrk, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZ256rrkz, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZmr, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZmrk, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZrr, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZrrk, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVQWZrrkz, X86_INS_VPMOVQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ128mr, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ128mrk, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ128rr, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ128rrk, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ128rrkz, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ256mr, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ256mrk, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ256rr, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ256rrk, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZ256rrkz, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZmr, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZmrk, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZrr, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZrrk, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDBZrrkz, X86_INS_VPMOVSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ128mr, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ128mrk, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ128rr, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ128rrk, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ128rrkz, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ256mr, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ256mrk, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ256rr, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ256rrk, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZ256rrkz, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZmr, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZmrk, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZrr, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZrrk, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSDWZrrkz, X86_INS_VPMOVSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ128mr, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ128mrk, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ128rr, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ128rrk, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ128rrkz, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ256mr, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ256mrk, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ256rr, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ256rrk, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZ256rrkz, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZmr, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZmrk, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZrr, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZrrk, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQBZrrkz, X86_INS_VPMOVSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ128mr, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ128mrk, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ128rr, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ128rrk, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ128rrkz, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ256mr, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ256mrk, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ256rr, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ256rrk, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZ256rrkz, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZmr, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZmrk, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZrr, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZrrk, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQDZrrkz, X86_INS_VPMOVSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ128mr, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ128mrk, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ128rr, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ128rrk, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ128rrkz, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ256mr, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ256mrk, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ256rr, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ256rrk, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZ256rrkz, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZmr, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZmrk, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZrr, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZrrk, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSQWZrrkz, X86_INS_VPMOVSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ128mr, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ128mrk, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ128rr, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ128rrk, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ128rrkz, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ256mr, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ256mrk, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ256rr, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ256rrk, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZ256rrkz, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZmr, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZmrk, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZrr, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZrrk, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSWBZrrkz, X86_INS_VPMOVSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDYrm, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDYrr, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ128rm, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ128rmk, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ128rmkz, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ128rr, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ128rrk, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ128rrkz, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ256rm, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ256rmk, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ256rmkz, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ256rr, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ256rrk, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZ256rrkz, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZrm, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZrmk, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZrmkz, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZrr, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZrrk, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDZrrkz, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDrm, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXBDrr, X86_INS_VPMOVSXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQYrm, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQYrr, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ128rm, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ128rmk, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ128rmkz, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ128rr, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ128rrk, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ128rrkz, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ256rm, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ256rmk, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ256rmkz, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ256rr, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ256rrk, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZ256rrkz, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZrm, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZrmk, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZrmkz, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZrr, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZrrk, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQZrrkz, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQrm, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXBQrr, X86_INS_VPMOVSXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXBWYrm, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXBWYrr, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ128rm, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ128rmk, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ128rmkz, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ128rr, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ128rrk, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ128rrkz, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ256rm, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ256rmk, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ256rmkz, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ256rr, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ256rrk, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZ256rrkz, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZrm, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZrmk, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZrmkz, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZrr, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZrrk, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWZrrkz, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXBWrm, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXBWrr, X86_INS_VPMOVSXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQYrm, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQYrr, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ128rm, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ128rmk, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ128rmkz, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ128rr, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ128rrk, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ128rrkz, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ256rm, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ256rmk, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ256rmkz, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ256rr, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ256rrk, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZ256rrkz, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZrm, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZrmk, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZrmkz, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZrr, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZrrk, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQZrrkz, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQrm, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXDQrr, X86_INS_VPMOVSXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDYrm, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDYrr, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ128rm, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ128rmk, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ128rmkz, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ128rr, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ128rrk, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ128rrkz, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ256rm, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ256rmk, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ256rmkz, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ256rr, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ256rrk, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZ256rrkz, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZrm, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZrmk, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZrmkz, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZrr, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZrrk, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDZrrkz, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDrm, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXWDrr, X86_INS_VPMOVSXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQYrm, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQYrr, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ128rm, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ128rmk, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ128rmkz, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ128rr, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ128rrk, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ128rrkz, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ256rm, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ256rmk, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ256rmkz, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ256rr, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ256rrk, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZ256rrkz, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZrm, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZrmk, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZrmkz, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZrr, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZrrk, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQZrrkz, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQrm, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVSXWQrr, X86_INS_VPMOVSXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ128mr, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ128mrk, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ128rr, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ128rrk, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ128rrkz, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ256mr, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ256mrk, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ256rr, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ256rrk, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZ256rrkz, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZmr, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZmrk, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZrr, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZrrk, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDBZrrkz, X86_INS_VPMOVUSDB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ128mr, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ128mrk, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ128rr, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ128rrk, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ128rrkz, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ256mr, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ256mrk, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ256rr, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ256rrk, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZ256rrkz, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZmr, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZmrk, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZrr, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZrrk, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSDWZrrkz, X86_INS_VPMOVUSDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ128mr, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ128mrk, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ128rr, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ128rrk, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ128rrkz, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ256mr, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ256mrk, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ256rr, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ256rrk, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZ256rrkz, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZmr, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZmrk, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZrr, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZrrk, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQBZrrkz, X86_INS_VPMOVUSQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ128mr, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ128mrk, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ128rr, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ128rrk, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ128rrkz, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ256mr, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ256mrk, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ256rr, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ256rrk, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZ256rrkz, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZmr, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZmrk, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZrr, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZrrk, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQDZrrkz, X86_INS_VPMOVUSQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ128mr, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ128mrk, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ128rr, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ128rrk, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ128rrkz, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ256mr, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ256mrk, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ256rr, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ256rrk, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZ256rrkz, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZmr, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZmrk, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZrr, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZrrk, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSQWZrrkz, X86_INS_VPMOVUSQW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ128mr, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ128mrk, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ128rr, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ128rrk, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ128rrkz, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ256mr, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ256mrk, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ256rr, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ256rrk, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZ256rrkz, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZmr, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZmrk, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZrr, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZrrk, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVUSWBZrrkz, X86_INS_VPMOVUSWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVW2MZ128rr, X86_INS_VPMOVW2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVW2MZ256rr, X86_INS_VPMOVW2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVW2MZrr, X86_INS_VPMOVW2M, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ128mr, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ128mrk, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ128rr, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ128rrk, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ128rrkz, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ256mr, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ256mrk, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ256rr, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ256rrk, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZ256rrkz, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZmr, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZmrk, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZrr, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZrrk, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVWBZrrkz, X86_INS_VPMOVWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDYrm, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDYrr, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ128rm, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ128rmk, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ128rmkz, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ128rr, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ128rrk, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ128rrkz, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ256rm, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ256rmk, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ256rmkz, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ256rr, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ256rrk, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZ256rrkz, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZrm, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZrmk, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZrmkz, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZrr, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZrrk, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDZrrkz, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDrm, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXBDrr, X86_INS_VPMOVZXBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQYrm, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQYrr, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ128rm, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ128rmk, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ128rmkz, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ128rr, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ128rrk, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ128rrkz, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ256rm, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ256rmk, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ256rmkz, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ256rr, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ256rrk, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZ256rrkz, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZrm, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZrmk, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZrmkz, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZrr, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZrrk, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQZrrkz, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQrm, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXBQrr, X86_INS_VPMOVZXBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXBWYrm, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXBWYrr, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ128rm, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ128rmk, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ128rmkz, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ128rr, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ128rrk, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ128rrkz, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ256rm, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ256rmk, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ256rmkz, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ256rr, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ256rrk, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZ256rrkz, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZrm, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZrmk, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZrmkz, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZrr, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZrrk, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWZrrkz, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXBWrm, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXBWrr, X86_INS_VPMOVZXBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQYrm, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQYrr, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ128rm, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ128rmk, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ128rmkz, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ128rr, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ128rrk, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ128rrkz, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ256rm, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ256rmk, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ256rmkz, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ256rr, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ256rrk, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZ256rrkz, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZrm, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZrmk, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZrmkz, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZrr, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZrrk, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQZrrkz, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQrm, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXDQrr, X86_INS_VPMOVZXDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDYrm, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDYrr, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ128rm, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ128rmk, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ128rmkz, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ128rr, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ128rrk, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ128rrkz, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ256rm, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ256rmk, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ256rmkz, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ256rr, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ256rrk, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZ256rrkz, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZrm, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZrmk, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZrmkz, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZrr, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZrrk, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDZrrkz, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDrm, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXWDrr, X86_INS_VPMOVZXWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQYrm, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQYrr, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ128rm, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ128rmk, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ128rmkz, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ128rr, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ128rrk, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ128rrkz, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ256rm, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ256rmk, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ256rmkz, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ256rr, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ256rrk, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZ256rrkz, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZrm, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZrmk, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZrmkz, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZrr, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZrrk, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQZrrkz, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQrm, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMOVZXWQrr, X86_INS_VPMOVZXWQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMULDQYrm, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULDQYrr, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rm, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rmb, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rmbk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rmbkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rmk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rmkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rr, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rrk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ128rrkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rm, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rmb, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rmbk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rmbkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rmk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rmkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rr, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rrk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZ256rrkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULDQZrm, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrmb, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrmbk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrmbkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrmk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrmkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrr, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrrk, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQZrrkz, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULDQrm, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULDQrr, X86_INS_VPMULDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHRSWYrm, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWYrr, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ128rm, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ128rmk, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ128rmkz, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ128rr, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ128rrk, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ128rrkz, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ256rm, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ256rmk, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ256rmkz, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ256rr, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ256rrk, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZ256rrkz, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZrm, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZrmk, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZrmkz, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZrr, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZrrk, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWZrrkz, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWrm, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHRSWrr, X86_INS_VPMULHRSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWYrm, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHUWYrr, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHUWZ128rm, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ128rmk, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ128rmkz, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ128rr, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ128rrk, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ128rrkz, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ256rm, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ256rmk, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ256rmkz, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ256rr, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ256rrk, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZ256rrkz, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZrm, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZrmk, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZrmkz, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZrr, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZrrk, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWZrrkz, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHUWrm, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHUWrr, X86_INS_VPMULHUW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHWYrm, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHWYrr, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHWZ128rm, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ128rmk, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ128rmkz, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ128rr, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ128rrk, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ128rrkz, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ256rm, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ256rmk, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ256rmkz, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ256rr, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ256rrk, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZ256rrkz, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZrm, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZrmk, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZrmkz, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZrr, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZrrk, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWZrrkz, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULHWrm, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULHWrr, X86_INS_VPMULHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULLDYrm, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMULLDYrr, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rm, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rmb, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rmbk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rmbkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rmk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rmkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rr, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rrk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ128rrkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rm, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rmb, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rmbk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rmbkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rmk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rmkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rr, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rrk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZ256rrkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLDZrm, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrmb, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrmbk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrmbkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrmk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrmkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrr, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrrk, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDZrrkz, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULLDrm, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULLDrr, X86_INS_VPMULLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rm, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rmb, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rmbk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rmbkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rmk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rmkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rr, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rrk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ128rrkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rm, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rmb, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rmbk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rmbkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rmk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rmkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rr, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rrk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZ256rrkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLQZrm, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrmb, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrmbk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrmbkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrmk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrmkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrr, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrrk, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLQZrrkz, X86_INS_VPMULLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_DQI, 0 }, 0, 0 #endif }, { X86_VPMULLWYrm, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULLWYrr, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ128rm, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ128rmk, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ128rmkz, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ128rr, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ128rrk, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ128rrkz, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ256rm, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ256rmk, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ256rmkz, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ256rr, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ256rrk, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZ256rrkz, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPMULLWZrm, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMULLWZrmk, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMULLWZrmkz, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMULLWZrr, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMULLWZrrk, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMULLWZrrkz, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPMULLWrm, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULLWrr, X86_INS_VPMULLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rm, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rmb, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rmbk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rmbkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rmk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rmkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rr, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rrk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ128rrkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rm, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rmb, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rmbk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rmbkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rmk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rmkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rr, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rrk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZ256rrkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrm, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrmb, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrmbk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrmbkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrmk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrmkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrr, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrrk, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULTISHIFTQBZrrkz, X86_INS_VPMULTISHIFTQB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQYrm, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMULUDQYrr, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rm, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rmb, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rmbk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rmbkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rmk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rmkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rr, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rrk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ128rrkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rm, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rmb, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rmbk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rmbkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rmk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rmkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rr, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rrk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZ256rrkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPMULUDQZrm, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrmb, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrmbk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrmbkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrmk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrmkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrr, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrrk, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQZrrkz, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPMULUDQrm, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPMULUDQrr, X86_INS_VPMULUDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ128rm, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ128rmk, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ128rmkz, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ128rr, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ128rrk, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ128rrkz, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ256rm, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ256rmk, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ256rmkz, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ256rr, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ256rrk, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZ256rrkz, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZrm, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZrmk, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZrmkz, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZrr, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZrrk, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTBZrrkz, X86_INS_VPOPCNTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rm, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rmb, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rmbk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rmbkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rmk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rmkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rr, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rrk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ128rrkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rm, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rmb, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rmbk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rmbkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rmk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rmkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rr, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rrk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZ256rrkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrm, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrmb, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrmbk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrmbkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrmk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrmkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrr, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrrk, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTDZrrkz, X86_INS_VPOPCNTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rm, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rmb, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rmbk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rmbkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rmk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rmkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rr, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rrk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ128rrkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rm, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rmb, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rmbk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rmbkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rmk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rmkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rr, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rrk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZ256rrkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrm, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrmb, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrmbk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrmbkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrmk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrmkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrr, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrrk, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTQZrrkz, X86_INS_VPOPCNTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ128rm, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ128rmk, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ128rmkz, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ128rr, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ128rrk, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ128rrkz, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ256rm, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ256rmk, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ256rmkz, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ256rr, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ256rrk, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZ256rrkz, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZrm, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZrmk, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZrmkz, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZrr, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZrrk, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPOPCNTWZrrkz, X86_INS_VPOPCNTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPORDZ128rm, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rmb, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rmbk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rmbkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rmk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rmkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rr, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rrk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ128rrkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rm, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rmb, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rmbk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rmbkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rmk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rmkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rr, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rrk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZ256rrkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORDZrm, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrmb, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrmbk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrmbkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrmk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrmkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrr, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrrk, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORDZrrkz, X86_INS_VPORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZ128rm, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rmb, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rmbk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rmbkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rmk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rmkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rr, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rrk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ128rrkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rm, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rmb, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rmbk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rmbkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rmk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rmkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rr, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rrk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZ256rrkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPORQZrm, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrmb, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrmbk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrmbkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrmk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrmkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrr, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrrk, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORQZrrkz, X86_INS_VPORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPORYrm, X86_INS_VPOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPORYrr, X86_INS_VPOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPORrm, X86_INS_VPOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPORrr, X86_INS_VPOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPPERMrmr, X86_INS_VPPERM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPPERMrrm, X86_INS_VPPERM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPPERMrrr, X86_INS_VPPERM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPPERMrrr_REV, X86_INS_VPPERM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128mbi, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128mbik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128mbikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128mi, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128mik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128mikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128ri, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128rik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ128rikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256mbi, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256mbik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256mbikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256mi, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256mik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256mikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256ri, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256rik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZ256rikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZmbi, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZmbik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZmbikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZmi, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZmik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZmikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZri, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZrik, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLDZrikz, X86_INS_VPROLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128mbi, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128mbik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128mbikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128mi, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128mik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128mikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128ri, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128rik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ128rikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256mbi, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256mbik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256mbikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256mi, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256mik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256mikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256ri, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256rik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZ256rikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZmbi, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZmbik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZmbikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZmi, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZmik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZmikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZri, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZrik, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLQZrikz, X86_INS_VPROLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rm, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rmb, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rmbk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rmbkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rmk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rmkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rr, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rrk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ128rrkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rm, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rmb, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rmbk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rmbkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rmk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rmkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rr, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rrk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZ256rrkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrm, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrmb, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrmbk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrmbkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrmk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrmkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrr, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrrk, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVDZrrkz, X86_INS_VPROLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rm, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rmb, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rmbk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rmbkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rmk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rmkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rr, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rrk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ128rrkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rm, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rmb, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rmbk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rmbkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rmk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rmkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rr, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rrk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZ256rrkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrm, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrmb, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrmbk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrmbkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrmk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrmkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrr, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrrk, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROLVQZrrkz, X86_INS_VPROLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128mbi, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128mbik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128mbikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128mi, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128mik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128mikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128ri, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128rik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ128rikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256mbi, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256mbik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256mbikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256mi, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256mik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256mikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256ri, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256rik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZ256rikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZmbi, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZmbik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZmbikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZmi, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZmik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZmikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZri, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZrik, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORDZrikz, X86_INS_VPRORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128mbi, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128mbik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128mbikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128mi, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128mik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128mikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128ri, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128rik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ128rikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256mbi, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256mbik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256mbikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256mi, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256mik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256mikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256ri, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256rik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZ256rikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZmbi, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZmbik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZmbikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZmi, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZmik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZmikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZri, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZrik, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORQZrikz, X86_INS_VPRORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rm, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rmb, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rmbk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rmbkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rmk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rmkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rr, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rrk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ128rrkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rm, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rmb, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rmbk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rmbkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rmk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rmkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rr, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rrk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZ256rrkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrm, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrmb, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrmbk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrmbkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrmk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrmkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrr, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrrk, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVDZrrkz, X86_INS_VPRORVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rm, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rmb, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rmbk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rmbkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rmk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rmkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rr, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rrk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ128rrkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rm, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rmb, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rmbk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rmbkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rmk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rmkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rr, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rrk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZ256rrkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrm, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrmb, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrmbk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrmbkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrmk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrmkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrr, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrrk, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPRORVQZrrkz, X86_INS_VPRORVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROTBmi, X86_INS_VPROTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTBmr, X86_INS_VPROTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTBri, X86_INS_VPROTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTBrm, X86_INS_VPROTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTBrr, X86_INS_VPROTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTBrr_REV, X86_INS_VPROTB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROTDmi, X86_INS_VPROTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTDmr, X86_INS_VPROTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTDri, X86_INS_VPROTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTDrm, X86_INS_VPROTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTDrr, X86_INS_VPROTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTDrr_REV, X86_INS_VPROTD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROTQmi, X86_INS_VPROTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTQmr, X86_INS_VPROTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTQri, X86_INS_VPROTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTQrm, X86_INS_VPROTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTQrr, X86_INS_VPROTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTQrr_REV, X86_INS_VPROTQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPROTWmi, X86_INS_VPROTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTWmr, X86_INS_VPROTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTWri, X86_INS_VPROTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTWrm, X86_INS_VPROTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTWrr, X86_INS_VPROTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPROTWrr_REV, X86_INS_VPROTW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWYrm, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSADBWYrr, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSADBWZ128rm, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWZ128rr, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWZ256rm, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWZ256rr, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWZrm, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWZrr, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSADBWrm, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSADBWrr, X86_INS_VPSADBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSCATTERDDZ128mr, X86_INS_VPSCATTERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERDDZ256mr, X86_INS_VPSCATTERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERDDZmr, X86_INS_VPSCATTERDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSCATTERDQZ128mr, X86_INS_VPSCATTERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERDQZ256mr, X86_INS_VPSCATTERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERDQZmr, X86_INS_VPSCATTERDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSCATTERQDZ128mr, X86_INS_VPSCATTERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERQDZ256mr, X86_INS_VPSCATTERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERQDZmr, X86_INS_VPSCATTERQD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSCATTERQQZ128mr, X86_INS_VPSCATTERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERQQZ256mr, X86_INS_VPSCATTERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSCATTERQQZmr, X86_INS_VPSCATTERQQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSHABmr, X86_INS_VPSHAB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHABrm, X86_INS_VPSHAB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHABrr, X86_INS_VPSHAB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHABrr_REV, X86_INS_VPSHAB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHADmr, X86_INS_VPSHAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHADrm, X86_INS_VPSHAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHADrr, X86_INS_VPSHAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHADrr_REV, X86_INS_VPSHAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHAQmr, X86_INS_VPSHAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHAQrm, X86_INS_VPSHAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHAQrr, X86_INS_VPSHAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHAQrr_REV, X86_INS_VPSHAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHAWmr, X86_INS_VPSHAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHAWrm, X86_INS_VPSHAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHAWrr, X86_INS_VPSHAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHAWrr_REV, X86_INS_VPSHAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLBmr, X86_INS_VPSHLB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLBrm, X86_INS_VPSHLB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLBrr, X86_INS_VPSHLB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLBrr_REV, X86_INS_VPSHLB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rmbi, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rmbik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rmbikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rmi, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rmik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rmikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rri, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rrik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ128rrikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rmbi, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rmbik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rmbikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rmi, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rmik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rmikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rri, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rrik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZ256rrikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrmbi, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrmbik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrmbikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrmi, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrmik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrmikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrri, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrrik, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDDZrrikz, X86_INS_VPSHLDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rmbi, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rmbik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rmbikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rmi, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rmik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rmikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rri, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rrik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ128rrikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rmbi, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rmbik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rmbikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rmi, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rmik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rmikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rri, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rrik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZ256rrikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrmbi, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrmbik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrmbikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrmi, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrmik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrmikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrri, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrrik, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDQZrrikz, X86_INS_VPSHLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128m, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128mb, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128mbk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128mbkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128mk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128mkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128r, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128rk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ128rkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256m, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256mb, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256mbk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256mbkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256mk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256mkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256r, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256rk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZ256rkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZm, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZmb, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZmbk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZmbkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZmk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZmkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZr, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZrk, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVDZrkz, X86_INS_VPSHLDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128m, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128mb, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128mbk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128mbkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128mk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128mkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128r, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128rk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ128rkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256m, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256mb, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256mbk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256mbkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256mk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256mkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256r, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256rk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZ256rkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZm, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZmb, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZmbk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZmbkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZmk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZmkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZr, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZrk, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVQZrkz, X86_INS_VPSHLDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ128m, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ128mk, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ128mkz, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ128r, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ128rk, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ128rkz, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ256m, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ256mk, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ256mkz, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ256r, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ256rk, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZ256rkz, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZm, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZmk, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZmkz, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZr, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZrk, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDVWZrkz, X86_INS_VPSHLDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ128rmi, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ128rmik, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ128rmikz, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ128rri, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ128rrik, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ128rrikz, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ256rmi, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ256rmik, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ256rmikz, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ256rri, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ256rrik, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZ256rrikz, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZrmi, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZrmik, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZrmikz, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZrri, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZrrik, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDWZrrikz, X86_INS_VPSHLDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLDmr, X86_INS_VPSHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLDrm, X86_INS_VPSHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLDrr, X86_INS_VPSHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLDrr_REV, X86_INS_VPSHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLQmr, X86_INS_VPSHLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLQrm, X86_INS_VPSHLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLQrr, X86_INS_VPSHLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLQrr_REV, X86_INS_VPSHLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHLWmr, X86_INS_VPSHLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLWrm, X86_INS_VPSHLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLWrr, X86_INS_VPSHLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_XOP, 0 }, 0, 0 #endif }, { X86_VPSHLWrr_REV, X86_INS_VPSHLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rmbi, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rmbik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rmbikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rmi, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rmik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rmikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rri, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rrik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ128rrikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rmbi, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rmbik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rmbikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rmi, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rmik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rmikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rri, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rrik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZ256rrikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrmbi, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrmbik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrmbikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrmi, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrmik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrmikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrri, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrrik, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDDZrrikz, X86_INS_VPSHRDD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rmbi, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rmbik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rmbikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rmi, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rmik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rmikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rri, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rrik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ128rrikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rmbi, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rmbik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rmbikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rmi, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rmik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rmikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rri, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rrik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZ256rrikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrmbi, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrmbik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrmbikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrmi, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrmik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrmikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrri, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrrik, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDQZrrikz, X86_INS_VPSHRDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128m, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128mb, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128mbk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128mbkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128mk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128mkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128r, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128rk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ128rkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256m, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256mb, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256mbk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256mbkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256mk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256mkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256r, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256rk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZ256rkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZm, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZmb, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZmbk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZmbkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZmk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZmkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZr, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZrk, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVDZrkz, X86_INS_VPSHRDVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128m, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128mb, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128mbk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128mbkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128mk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128mkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128r, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128rk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ128rkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256m, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256mb, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256mbk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256mbkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256mk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256mkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256r, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256rk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZ256rkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZm, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZmb, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZmbk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZmbkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZmk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZmkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZr, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZrk, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVQZrkz, X86_INS_VPSHRDVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ128m, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ128mk, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ128mkz, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ128r, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ128rk, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ128rkz, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ256m, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ256mk, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ256mkz, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ256r, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ256rk, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZ256rkz, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZm, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZmk, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZmkz, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZr, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZrk, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDVWZrkz, X86_INS_VPSHRDVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ128rmi, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ128rmik, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ128rmikz, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ128rri, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ128rrik, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ128rrikz, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ256rmi, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ256rmik, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ256rmikz, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ256rri, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ256rrik, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZ256rrikz, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZrmi, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZrmik, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZrmikz, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZrri, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZrrik, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHRDWZrrikz, X86_INS_VPSHRDW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ128rm, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ128rmk, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ128rr, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ128rrk, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ256rm, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ256rmk, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ256rr, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZ256rrk, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZrm, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZrmk, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZrr, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBITQMBZrrk, X86_INS_VPSHUFBITQMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBYrm, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFBYrr, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFBZ128rm, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ128rmk, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ128rmkz, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ128rr, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ128rrk, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ128rrkz, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ256rm, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ256rmk, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ256rmkz, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ256rr, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ256rrk, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZ256rrkz, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZrm, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZrmk, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZrmkz, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZrr, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZrrk, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBZrrkz, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFBrm, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFBrr, X86_INS_VPSHUFB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFDYmi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFDYri, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128mbi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128mbik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128mbikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128mi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128mik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128mikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128ri, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128rik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ128rikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256mbi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256mbik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256mbikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256mi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256mik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256mikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256ri, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256rik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZ256rikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZmbi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZmbik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZmbikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZmi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSHUFDZmik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZmikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZri, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSHUFDZrik, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDZrikz, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFDmi, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFDri, X86_INS_VPSHUFD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFHWYmi, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFHWYri, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ128mi, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ128mik, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ128mikz, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ128ri, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ128rik, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ128rikz, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ256mi, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ256mik, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ256mikz, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ256ri, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ256rik, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZ256rikz, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZmi, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZmik, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZmikz, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZri, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZrik, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWZrikz, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFHWmi, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFHWri, X86_INS_VPSHUFHW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFLWYmi, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFLWYri, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ128mi, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ128mik, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ128mikz, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ128ri, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ128rik, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ128rikz, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ256mi, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ256mik, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ256mikz, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ256ri, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ256rik, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZ256rikz, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZmi, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZmik, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZmikz, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZri, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZrik, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWZrikz, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSHUFLWmi, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSHUFLWri, X86_INS_VPSHUFLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSIGNBYrm, X86_INS_VPSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSIGNBYrr, X86_INS_VPSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSIGNBrm, X86_INS_VPSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSIGNBrr, X86_INS_VPSIGNB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSIGNDYrm, X86_INS_VPSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSIGNDYrr, X86_INS_VPSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSIGNDrm, X86_INS_VPSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSIGNDrr, X86_INS_VPSIGND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSIGNWYrm, X86_INS_VPSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSIGNWYrr, X86_INS_VPSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSIGNWrm, X86_INS_VPSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSIGNWrr, X86_INS_VPSIGNW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLDQYri, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLDQZ128rm, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDQZ128rr, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDQZ256rm, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDQZ256rr, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDQZrm, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDQZrr, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDQri, X86_INS_VPSLLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLDYri, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLDYrm, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLDYrr, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLDZ128mbi, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128mbik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128mbikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128mi, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128mik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128mikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128ri, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rm, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rmk, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rmkz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rr, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rrk, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ128rrkz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256mbi, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256mbik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256mbikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256mi, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256mik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256mikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256ri, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rm, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rmk, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rmkz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rr, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rrk, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZ256rrkz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZmbi, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZmbik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZmbikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLDZmi, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZmik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZmikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZri, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrik, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrikz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrm, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrmk, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrmkz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrr, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrrk, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDZrrkz, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLDri, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLDrm, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLDrr, X86_INS_VPSLLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLQYri, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLQYrm, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLQYrr, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLQZ128mbi, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128mbik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128mbikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128mi, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128mik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128mikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128ri, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rm, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rmk, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rmkz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rr, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rrk, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ128rrkz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256mbi, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256mbik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256mbikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256mi, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256mik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256mikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256ri, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rm, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rmk, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rmkz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rr, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rrk, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZ256rrkz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZmbi, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZmbik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZmbikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLQZmi, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZmik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZmikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZri, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrik, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrikz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrm, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrmk, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrmkz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrr, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrrk, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQZrrkz, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLQri, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLQrm, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLQrr, X86_INS_VPSLLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLVDYrm, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVDYrr, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rm, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rmb, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rmbk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rmbkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rmk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rmkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rr, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rrk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ128rrkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rm, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rmb, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rmbk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rmbkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rmk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rmkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rr, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rrk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZ256rrkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZrm, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVDZrmb, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZrmbk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZrmbkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVDZrmk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVDZrmkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVDZrr, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVDZrrk, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVDZrrkz, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVDrm, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVDrr, X86_INS_VPSLLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVQYrm, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVQYrr, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rm, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rmb, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rmbk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rmbkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rmk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rmkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rr, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rrk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ128rrkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rm, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rmb, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rmbk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rmbkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rmk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rmkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rr, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rrk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZ256rrkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZrm, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVQZrmb, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZrmbk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZrmbkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVQZrmk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVQZrmkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVQZrr, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVQZrrk, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVQZrrkz, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSLLVQrm, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVQrr, X86_INS_VPSLLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLVWZ128rm, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ128rmk, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ128rmkz, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ128rr, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ128rrk, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ128rrkz, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ256rm, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ256rmk, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ256rmkz, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ256rr, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ256rrk, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZ256rrkz, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZrm, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZrmk, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZrmkz, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZrr, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZrrk, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLVWZrrkz, X86_INS_VPSLLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWYri, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLWYrm, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLWYrr, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSLLWZ128mi, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128mik, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128mikz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128ri, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rik, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rikz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rm, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rmk, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rmkz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rr, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rrk, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ128rrkz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256mi, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256mik, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256mikz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256ri, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rik, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rikz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rm, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rmk, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rmkz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rr, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rrk, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZ256rrkz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZmi, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZmik, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZmikz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZri, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrik, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrikz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrm, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrmk, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrmkz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrr, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrrk, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWZrrkz, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSLLWri, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLWrm, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSLLWrr, X86_INS_VPSLLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRADYri, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRADYrm, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRADYrr, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRADZ128mbi, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128mbik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128mbikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128mi, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128mik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128mikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128ri, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rm, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rmk, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rmkz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rr, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rrk, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ128rrkz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256mbi, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256mbik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256mbikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256mi, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256mik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256mikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256ri, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rm, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rmk, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rmkz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rr, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rrk, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZ256rrkz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZmbi, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZmbik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZmbikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRADZmi, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZmik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZmikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZri, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrik, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrikz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrm, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrmk, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrmkz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrr, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrrk, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADZrrkz, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRADri, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRADrm, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRADrr, X86_INS_VPSRAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRAQZ128mbi, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128mbik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128mbikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128mi, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128mik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128mikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128ri, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rm, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rmk, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rmkz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rr, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rrk, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ128rrkz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256mbi, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256mbik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256mbikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256mi, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256mik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256mikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256ri, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rm, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rmk, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rmkz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rr, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rrk, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZ256rrkz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZmbi, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZmbik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZmbikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAQZmi, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZmik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZmikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZri, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrik, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrikz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrm, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrmk, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrmkz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrr, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrrk, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAQZrrkz, X86_INS_VPSRAQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDYrm, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAVDYrr, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rm, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rmb, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rmbk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rmbkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rmk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rmkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rr, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rrk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ128rrkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rm, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rmb, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rmbk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rmbkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rmk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rmkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rr, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rrk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZ256rrkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZrm, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDZrmb, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZrmbk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZrmbkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVDZrmk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDZrmkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDZrr, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDZrrk, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDZrrkz, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVDrm, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAVDrr, X86_INS_VPSRAVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rm, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rmb, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rmbk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rmbkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rmk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rmkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rr, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rrk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ128rrkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rm, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rmb, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rmbk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rmbkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rmk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rmkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rr, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rrk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZ256rrkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZrm, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVQZrmb, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZrmbk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZrmbkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVQZrmk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVQZrmkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVQZrr, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVQZrrk, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVQZrrkz, X86_INS_VPSRAVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRAVWZ128rm, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ128rmk, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ128rmkz, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ128rr, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ128rrk, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ128rrkz, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ256rm, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ256rmk, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ256rmkz, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ256rr, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ256rrk, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZ256rrkz, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZrm, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZrmk, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZrmkz, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZrr, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZrrk, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAVWZrrkz, X86_INS_VPSRAVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWYri, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAWYrm, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAWYrr, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRAWZ128mi, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128mik, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128mikz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128ri, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rik, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rikz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rm, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rmk, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rmkz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rr, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rrk, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ128rrkz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256mi, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256mik, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256mikz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256ri, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rik, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rikz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rm, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rmk, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rmkz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rr, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rrk, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZ256rrkz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZmi, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZmik, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZmikz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZri, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrik, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrikz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrm, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrmk, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrmkz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrr, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrrk, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWZrrkz, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRAWri, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRAWrm, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRAWrr, X86_INS_VPSRAW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLDQYri, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLDQZ128rm, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDQZ128rr, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDQZ256rm, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDQZ256rr, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDQZrm, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDQZrr, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDQri, X86_INS_VPSRLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLDYri, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLDYrm, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLDYrr, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLDZ128mbi, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128mbik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128mbikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128mi, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128mik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128mikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128ri, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rm, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rmk, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rmkz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rr, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rrk, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ128rrkz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256mbi, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256mbik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256mbikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256mi, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256mik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256mikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256ri, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rm, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rmk, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rmkz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rr, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rrk, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZ256rrkz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZmbi, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZmbik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZmbikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLDZmi, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZmik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZmikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZri, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrik, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrikz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrm, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrmk, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrmkz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrr, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrrk, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDZrrkz, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLDri, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLDrm, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLDrr, X86_INS_VPSRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLQYri, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLQYrm, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLQYrr, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLQZ128mbi, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128mbik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128mbikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128mi, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128mik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128mikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128ri, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rm, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rmk, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rmkz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rr, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rrk, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ128rrkz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256mbi, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256mbik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256mbikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256mi, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256mik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256mikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256ri, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rm, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rmk, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rmkz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rr, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rrk, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZ256rrkz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZmbi, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZmbik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZmbikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLQZmi, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZmik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZmikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZri, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrik, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrikz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrm, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrmk, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrmkz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrr, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrrk, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQZrrkz, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLQri, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLQrm, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLQrr, X86_INS_VPSRLQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLVDYrm, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVDYrr, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rm, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rmb, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rmbk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rmbkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rmk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rmkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rr, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rrk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ128rrkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rm, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rmb, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rmbk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rmbkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rmk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rmkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rr, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rrk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZ256rrkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZrm, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVDZrmb, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZrmbk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZrmbkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVDZrmk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVDZrmkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVDZrr, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVDZrrk, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVDZrrkz, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVDrm, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVDrr, X86_INS_VPSRLVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVQYrm, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVQYrr, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rm, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rmb, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rmbk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rmbkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rmk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rmkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rr, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rrk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ128rrkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rm, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rmb, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rmbk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rmbkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rmk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rmkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rr, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rrk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZ256rrkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZrm, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVQZrmb, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZrmbk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZrmbkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVQZrmk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVQZrmkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVQZrr, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVQZrrk, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVQZrrkz, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSRLVQrm, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVQrr, X86_INS_VPSRLVQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLVWZ128rm, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ128rmk, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ128rmkz, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ128rr, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ128rrk, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ128rrkz, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ256rm, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ256rmk, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ256rmkz, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ256rr, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ256rrk, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZ256rrkz, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZrm, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZrmk, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZrmkz, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZrr, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZrrk, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLVWZrrkz, X86_INS_VPSRLVW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWYri, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLWYrm, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLWYrr, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSRLWZ128mi, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128mik, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128mikz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128ri, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rik, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rikz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rm, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rmk, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rmkz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rr, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rrk, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ128rrkz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256mi, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256mik, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256mikz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256ri, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rik, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rikz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rm, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rmk, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rmkz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rr, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rrk, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZ256rrkz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZmi, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZmik, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZmikz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZri, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrik, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrikz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrm, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrmk, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrmkz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrr, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrrk, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWZrrkz, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSRLWri, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLWrm, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSRLWrr, X86_INS_VPSRLW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSUBBYrm, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBBYrr, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ128rm, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ128rmk, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ128rmkz, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ128rr, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ128rrk, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ128rrkz, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ256rm, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ256rmk, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ256rmkz, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ256rr, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ256rrk, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZ256rrkz, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBBZrm, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBBZrmk, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBBZrmkz, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBBZrr, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBBZrrk, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBBZrrkz, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBBrm, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBBrr, X86_INS_VPSUBB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBDYrm, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBDYrr, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rm, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rmb, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rmbk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rmbkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rmk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rmkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rr, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rrk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ128rrkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rm, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rmb, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rmbk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rmbkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rmk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rmkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rr, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rrk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZ256rrkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBDZrm, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrmb, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrmbk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrmbkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrmk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrmkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrr, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrrk, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDZrrkz, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBDrm, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBDrr, X86_INS_VPSUBD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBQYrm, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBQYrr, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rm, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rmb, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rmbk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rmbkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rmk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rmkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rr, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rrk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ128rrkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rm, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rmb, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rmbk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rmbkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rmk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rmkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rr, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rrk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZ256rrkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBQZrm, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrmb, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrmbk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrmbkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrmk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrmkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrr, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrrk, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQZrrkz, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPSUBQrm, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBQrr, X86_INS_VPSUBQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBSBYrm, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSUBSBYrr, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSUBSBZ128rm, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ128rmk, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ128rmkz, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ128rr, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ128rrk, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ128rrkz, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ256rm, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ256rmk, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ256rmkz, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ256rr, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ256rrk, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZ256rrkz, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZrm, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZrmk, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZrmkz, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZrr, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZrrk, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBZrrkz, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSBrm, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSUBSBrr, X86_INS_VPSUBSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSUBSWYrm, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSUBSWYrr, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPSUBSWZ128rm, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ128rmk, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ128rmkz, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ128rr, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ128rrk, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ128rrkz, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ256rm, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ256rmk, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ256rmkz, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ256rr, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ256rrk, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZ256rrkz, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZrm, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZrmk, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZrmkz, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZrr, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZrrk, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWZrrkz, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBSWrm, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSUBSWrr, X86_INS_VPSUBSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPSUBUSBYrm, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSBYrr, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ128rm, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ128rmk, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ128rmkz, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ128rr, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ128rrk, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ128rrkz, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ256rm, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ256rmk, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ256rmkz, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ256rr, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ256rrk, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZ256rrkz, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZrm, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZrmk, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZrmkz, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZrr, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZrrk, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBZrrkz, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSBrm, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSBrr, X86_INS_VPSUBUSB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSWYrm, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSWYrr, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ128rm, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ128rmk, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ128rmkz, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ128rr, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ128rrk, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ128rrkz, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ256rm, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ256rmk, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ256rmkz, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ256rr, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ256rrk, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZ256rrkz, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZrm, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZrmk, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZrmkz, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZrr, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZrrk, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWZrrkz, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPSUBUSWrm, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBUSWrr, X86_INS_VPSUBUSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBWYrm, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBWYrr, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ128rm, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ128rmk, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ128rmkz, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ128rr, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ128rrk, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ128rrkz, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ256rm, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ256rmk, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ256rmkz, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ256rr, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ256rrk, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZ256rrkz, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPSUBWZrm, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBWZrmk, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBWZrmkz, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBWZrr, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBWZrrk, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBWZrrkz, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BWI, 0 }, 0, 0 #endif }, { X86_VPSUBWrm, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPSUBWrr, X86_INS_VPSUBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rmbi, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rmbik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rmbikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rmi, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rmik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rmikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rri, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rrik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ128rrikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rmbi, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rmbik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rmbikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rmi, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rmik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rmikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rri, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rrik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZ256rrikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrmbi, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrmbik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrmbikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrmi, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrmik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrmikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrri, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrrik, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGDZrrikz, X86_INS_VPTERNLOGD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rmbi, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rmbik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rmbikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rmi, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rmik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rmikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rri, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rrik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ128rrikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rmbi, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rmbik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rmbikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rmi, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rmik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rmikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rri, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rrik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZ256rrikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrmbi, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrmbik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrmbikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrmi, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrmik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrmikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrri, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrrik, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTERNLOGQZrrikz, X86_INS_VPTERNLOGQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ128rm, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ128rmk, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ128rr, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ128rrk, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ256rm, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ256rmk, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ256rr, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZ256rrk, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZrm, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZrmk, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZrr, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMBZrrk, X86_INS_VPTESTMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ128rm, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ128rmb, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ128rmbk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ128rmk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ128rr, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ128rrk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ256rm, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ256rmb, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ256rmbk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ256rmk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ256rr, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZ256rrk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZrm, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPTESTMDZrmb, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZrmbk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZrmk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMDZrr, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPTESTMDZrrk, X86_INS_VPTESTMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ128rm, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ128rmb, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ128rmbk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ128rmk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ128rr, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ128rrk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ256rm, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ256rmb, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ256rmbk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ256rmk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ256rr, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZ256rrk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZrm, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPTESTMQZrmb, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZrmbk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZrmk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMQZrr, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPTESTMQZrrk, X86_INS_VPTESTMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ128rm, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ128rmk, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ128rr, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ128rrk, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ256rm, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ256rmk, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ256rr, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZ256rrk, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZrm, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZrmk, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZrr, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTMWZrrk, X86_INS_VPTESTMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ128rm, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ128rmk, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ128rr, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ128rrk, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ256rm, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ256rmk, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ256rr, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZ256rrk, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZrm, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZrmk, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZrr, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMBZrrk, X86_INS_VPTESTNMB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ128rm, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ128rmb, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ128rmbk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ128rmk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ128rr, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ128rrk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ256rm, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ256rmb, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ256rmbk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ256rmk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ256rr, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZ256rrk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZrm, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPTESTNMDZrmb, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZrmbk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZrmk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMDZrr, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPTESTNMDZrrk, X86_INS_VPTESTNMD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ128rm, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ128rmb, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ128rmbk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ128rmk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ128rr, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ128rrk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ256rm, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ256rmb, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ256rmbk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ256rmk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ256rr, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZ256rrk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZrm, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPTESTNMQZrmb, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZrmbk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZrmk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMQZrr, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_CDI, 0 }, 0, 0 #endif }, { X86_VPTESTNMQZrrk, X86_INS_VPTESTNMQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ128rm, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ128rmk, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ128rr, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ128rrk, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ256rm, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ256rmk, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ256rr, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZ256rrk, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZrm, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZrmk, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZrr, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTNMWZrrk, X86_INS_VPTESTNMW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPTESTYrm, X86_INS_VPTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPTESTYrr, X86_INS_VPTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPTESTrm, X86_INS_VPTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPTESTrr, X86_INS_VPTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWYrm, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWYrr, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ128rm, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ128rmk, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ128rmkz, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ128rr, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ128rrk, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ128rrkz, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ256rm, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ256rmk, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ256rmkz, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ256rr, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ256rrk, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZ256rrkz, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZrm, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZrmk, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZrmkz, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZrr, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZrrk, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWZrrkz, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWrm, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHBWrr, X86_INS_VPUNPCKHBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQYrm, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQYrr, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rm, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rmb, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rmbk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rmbkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rmk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rmkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rr, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rrk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ128rrkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rm, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rmb, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rmbk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rmbkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rmk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rmkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rr, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rrk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZ256rrkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrm, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrmb, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrmbk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrmbkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrmk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrmkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrr, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrrk, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQZrrkz, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQrm, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHDQrr, X86_INS_VPUNPCKHDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQYrm, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQYrr, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rm, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rmb, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rmbk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rmbkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rmk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rmkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rr, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rrk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ128rrkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rm, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rmb, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rmbk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rmbkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rmk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rmkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rr, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rrk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZ256rrkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrm, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrmb, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrmbk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrmbkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrmk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrmkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrr, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrrk, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQZrrkz, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQrm, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHQDQrr, X86_INS_VPUNPCKHQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDYrm, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDYrr, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ128rm, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ128rmk, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ128rmkz, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ128rr, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ128rrk, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ128rrkz, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ256rm, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ256rmk, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ256rmkz, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ256rr, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ256rrk, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZ256rrkz, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZrm, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZrmk, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZrmkz, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZrr, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZrrk, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDZrrkz, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDrm, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKHWDrr, X86_INS_VPUNPCKHWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWYrm, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWYrr, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ128rm, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ128rmk, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ128rmkz, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ128rr, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ128rrk, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ128rrkz, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ256rm, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ256rmk, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ256rmkz, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ256rr, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ256rrk, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZ256rrkz, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZrm, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZrmk, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZrmkz, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZrr, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZrrk, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWZrrkz, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWrm, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLBWrr, X86_INS_VPUNPCKLBW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQYrm, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQYrr, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rm, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rmb, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rmbk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rmbkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rmk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rmkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rr, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rrk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ128rrkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rm, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rmb, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rmbk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rmbkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rmk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rmkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rr, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rrk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZ256rrkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrm, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrmb, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrmbk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrmbkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrmk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrmkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrr, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrrk, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQZrrkz, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQrm, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLDQrr, X86_INS_VPUNPCKLDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQYrm, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQYrr, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rm, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rmb, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rmbk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rmbkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rmk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rmkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rr, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rrk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ128rrkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rm, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rmb, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rmbk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rmbkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rmk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rmkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rr, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rrk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZ256rrkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrm, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrmb, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrmbk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrmbkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrmk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrmkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrr, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrrk, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQZrrkz, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQrm, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLQDQrr, X86_INS_VPUNPCKLQDQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDYrm, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDYrr, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ128rm, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ128rmk, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ128rmkz, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ128rr, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ128rrk, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ128rrkz, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ256rm, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ256rmk, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ256rmkz, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ256rr, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ256rrk, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZ256rrkz, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZrm, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZrmk, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZrmkz, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZrr, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZrrk, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDZrrkz, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDrm, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPUNPCKLWDrr, X86_INS_VPUNPCKLWD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rm, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rmb, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rmbk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rmbkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rmk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rmkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rr, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rrk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ128rrkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rm, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rmb, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rmbk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rmbkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rmk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rmkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rr, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rrk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZ256rrkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORDZrm, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrmb, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrmbk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrmbkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrmk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrmkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrr, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrrk, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORDZrrkz, X86_INS_VPXORD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rm, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rmb, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rmbk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rmbkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rmk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rmkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rr, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rrk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ128rrkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rm, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rmb, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rmbk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rmbkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rmk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rmkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rr, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rrk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZ256rrkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VPXORQZrm, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrmb, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrmbk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrmbkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrmk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrmkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrr, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrrk, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORQZrrkz, X86_INS_VPXORQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VPXORYrm, X86_INS_VPXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPXORYrr, X86_INS_VPXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX2, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPXORrm, X86_INS_VPXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VPXORrr, X86_INS_VPXOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rmbi, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rmbik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rmbikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rmi, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rmik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rmikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rri, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rrik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ128rrikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rmbi, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rmbik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rmbikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rmi, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rmik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rmikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rri, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rrik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZ256rrikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrmbi, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrmbik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrmbikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrmi, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrmik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrmikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrri, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrrib, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrribk, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrribkz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrrik, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPDZrrikz, X86_INS_VRANGEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rmbi, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rmbik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rmbikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rmi, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rmik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rmikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rri, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rrik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ128rrikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rmbi, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rmbik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rmbikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rmi, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rmik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rmikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rri, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rrik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZ256rrikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrmbi, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrmbik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrmbikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrmi, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrmik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrmikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrri, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrrib, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrribk, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrribkz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrrik, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGEPSZrrikz, X86_INS_VRANGEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrmi, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrmik, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrmikz, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrri, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrrib, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrribk, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrribkz, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrrik, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESDZrrikz, X86_INS_VRANGESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrmi, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrmik, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrmikz, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrri, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrrib, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrribk, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrribkz, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrrik, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRANGESSZrrikz, X86_INS_VRANGESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128m, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128mb, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128mbk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128mbkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128mk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128mkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128r, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128rk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ128rkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256m, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256mb, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256mbk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256mbkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256mk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256mkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256r, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256rk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZ256rkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PDZm, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZmb, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZmbk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZmbkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZmk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZmkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZr, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZrk, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PDZrkz, X86_INS_VRCP14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128m, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128mb, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128mbk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128mbkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128mk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128mkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128r, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128rk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ128rkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256m, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256mb, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256mbk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256mbkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256mk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256mkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256r, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256rk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZ256rkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRCP14PSZm, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZmb, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZmbk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZmbkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZmk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZmkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZr, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZrk, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14PSZrkz, X86_INS_VRCP14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRCP14SDZrm, X86_INS_VRCP14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SDZrmk, X86_INS_VRCP14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SDZrmkz, X86_INS_VRCP14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SDZrr, X86_INS_VRCP14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SDZrrk, X86_INS_VRCP14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SDZrrkz, X86_INS_VRCP14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SSZrm, X86_INS_VRCP14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SSZrmk, X86_INS_VRCP14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SSZrmkz, X86_INS_VRCP14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SSZrr, X86_INS_VRCP14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SSZrrk, X86_INS_VRCP14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP14SSZrrkz, X86_INS_VRCP14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZm, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZmb, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZmbk, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZmbkz, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZmk, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZmkz, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZr, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZrb, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZrbk, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZrbkz, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZrk, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PDZrkz, X86_INS_VRCP28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZm, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZmb, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZmbk, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZmbkz, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZmk, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZmkz, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZr, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZrb, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZrbk, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZrbkz, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZrk, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28PSZrkz, X86_INS_VRCP28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZm, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZmk, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZmkz, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZr, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZrb, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZrbk, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZrbkz, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZrk, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SDZrkz, X86_INS_VRCP28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZm, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZmk, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZmkz, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZr, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZrb, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZrbk, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZrbkz, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZrk, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCP28SSZrkz, X86_INS_VRCP28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCPPSYm, X86_INS_VRCPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRCPPSYr, X86_INS_VRCPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRCPPSm, X86_INS_VRCPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRCPPSr, X86_INS_VRCPPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRCPSSm, X86_INS_VRCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCPSSm_Int, X86_INS_VRCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCPSSr, X86_INS_VRCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRCPSSr_Int, X86_INS_VRCPSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rmbi, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rmbik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rmbikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rmi, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rmik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rmikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rri, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rrik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ128rrikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rmbi, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rmbik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rmbikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rmi, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rmik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rmikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rri, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rrik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZ256rrikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrmbi, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrmbik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrmbikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrmi, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrmik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrmikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrri, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrrib, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrribk, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrribkz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrrik, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPDZrrikz, X86_INS_VREDUCEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rmbi, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rmbik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rmbikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rmi, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rmik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rmikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rri, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rrik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ128rrikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rmbi, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rmbik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rmbikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rmi, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rmik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rmikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rri, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rrik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZ256rrikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrmbi, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrmbik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrmbikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrmi, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrmik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrmikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrri, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrrib, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrribk, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrribkz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrrik, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCEPSZrrikz, X86_INS_VREDUCEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrmi, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrmik, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrmikz, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrri, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrrib, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrribk, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrribkz, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrrik, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESDZrrikz, X86_INS_VREDUCESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrmi, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrmik, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrmikz, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrri, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrrib, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrribk, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrribkz, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrrik, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VREDUCESSZrrikz, X86_INS_VREDUCESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rmbi, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rmbik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rmbikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rmi, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rmik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rmikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rri, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rrik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ128rrikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rmbi, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rmbik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rmbikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rmi, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rmik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rmikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rri, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rrik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZ256rrikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrmbi, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrmbik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrmbikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrmi, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrmik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrmikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrri, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrrib, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrribk, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrribkz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrrik, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPDZrrikz, X86_INS_VRNDSCALEPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rmbi, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rmbik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rmbikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rmi, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rmik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rmikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rri, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rrik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ128rrikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rmbi, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rmbik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rmbikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rmi, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rmik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rmikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rri, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rrik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZ256rrikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrmbi, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrmbik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrmbikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrmi, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrmik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrmikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrri, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrrib, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrribk, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrribkz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrrik, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALEPSZrrikz, X86_INS_VRNDSCALEPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZm, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZm_Int, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZm_Intk, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZm_Intkz, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZr, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZr_Int, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZr_Intk, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZr_Intkz, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZrb_Int, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZrb_Intk, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESDZrb_Intkz, X86_INS_VRNDSCALESD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZm, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZm_Int, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZm_Intk, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZm_Intkz, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZr, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZr_Int, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZr_Intk, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZr_Intkz, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZrb_Int, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZrb_Intk, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRNDSCALESSZrb_Intkz, X86_INS_VRNDSCALESS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDPDYm, X86_INS_VROUNDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDPDYr, X86_INS_VROUNDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDPDm, X86_INS_VROUNDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDPDr, X86_INS_VROUNDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDPSYm, X86_INS_VROUNDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDPSYr, X86_INS_VROUNDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDPSm, X86_INS_VROUNDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDPSr, X86_INS_VROUNDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDSDm, X86_INS_VROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDSDm_Int, X86_INS_VROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDSDr, X86_INS_VROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDSDr_Int, X86_INS_VROUNDSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDSSm, X86_INS_VROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDSSm_Int, X86_INS_VROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VROUNDSSr, X86_INS_VROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VROUNDSSr_Int, X86_INS_VROUNDSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128m, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128mb, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128mbk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128mbkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128mk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128mkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128r, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128rk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ128rkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256m, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256mb, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256mbk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256mbkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256mk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256mkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256r, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256rk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZ256rkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZm, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZmb, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZmbk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZmbkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZmk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZmkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZr, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZrk, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PDZrkz, X86_INS_VRSQRT14PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128m, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128mb, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128mbk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128mbkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128mk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128mkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128r, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128rk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ128rkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256m, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256mb, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256mbk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256mbkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256mk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256mkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256r, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256rk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZ256rkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZm, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZmb, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZmbk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZmbkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZmk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZmkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZr, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZrk, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14PSZrkz, X86_INS_VRSQRT14PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VRSQRT14SDZrm, X86_INS_VRSQRT14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SDZrmk, X86_INS_VRSQRT14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SDZrmkz, X86_INS_VRSQRT14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SDZrr, X86_INS_VRSQRT14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SDZrrk, X86_INS_VRSQRT14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SDZrrkz, X86_INS_VRSQRT14SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SSZrm, X86_INS_VRSQRT14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SSZrmk, X86_INS_VRSQRT14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SSZrmkz, X86_INS_VRSQRT14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SSZrr, X86_INS_VRSQRT14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SSZrrk, X86_INS_VRSQRT14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT14SSZrrkz, X86_INS_VRSQRT14SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZm, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZmb, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZmbk, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZmbkz, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZmk, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZmkz, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZr, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZrb, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZrbk, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZrbkz, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZrk, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PDZrkz, X86_INS_VRSQRT28PD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZm, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZmb, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZmbk, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZmbkz, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZmk, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZmkz, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZr, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZrb, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZrbk, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZrbkz, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZrk, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28PSZrkz, X86_INS_VRSQRT28PS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZm, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZmk, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZmkz, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZr, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZrb, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZrbk, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZrbkz, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZrk, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SDZrkz, X86_INS_VRSQRT28SD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZm, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZmk, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZmkz, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZr, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZrb, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZrbk, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZrbkz, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZrk, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRT28SSZrkz, X86_INS_VRSQRT28SS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRTPSYm, X86_INS_VRSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRSQRTPSYr, X86_INS_VRSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRSQRTPSm, X86_INS_VRSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRSQRTPSr, X86_INS_VRSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VRSQRTSSm, X86_INS_VRSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRTSSm_Int, X86_INS_VRSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRTSSr, X86_INS_VRSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VRSQRTSSr_Int, X86_INS_VRSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rm, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rmb, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rmbk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rmbkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rmk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rmkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rr, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rrk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ128rrkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rm, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rmb, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rmbk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rmbkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rmk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rmkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rr, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rrk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZ256rrkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrm, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrmb, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrmbk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrmbkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrmk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrmkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrr, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrrb, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrrbk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrrbkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrrk, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPDZrrkz, X86_INS_VSCALEFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rm, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rmb, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rmbk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rmbkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rmk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rmkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rr, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rrk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ128rrkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rm, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rmb, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rmbk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rmbkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rmk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rmkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rr, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rrk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZ256rrkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrm, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrmb, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrmbk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrmbkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrmk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrmkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrr, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrrb, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrrbk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrrbkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrrk, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFPSZrrkz, X86_INS_VSCALEFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrm, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrmk, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrmkz, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrr, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrrb_Int, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrrb_Intk, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrrb_Intkz, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrrk, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSDZrrkz, X86_INS_VSCALEFSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrm, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrmk, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrmkz, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrr, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrrb_Int, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrrb_Intk, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrrb_Intkz, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrrk, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCALEFSSZrrkz, X86_INS_VSCALEFSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERDPDZ128mr, X86_INS_VSCATTERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERDPDZ256mr, X86_INS_VSCATTERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERDPDZmr, X86_INS_VSCATTERDPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSCATTERDPSZ128mr, X86_INS_VSCATTERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERDPSZ256mr, X86_INS_VSCATTERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERDPSZmr, X86_INS_VSCATTERDPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSCATTERPF0DPDm, X86_INS_VSCATTERPF0DPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF0DPSm, X86_INS_VSCATTERPF0DPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF0QPDm, X86_INS_VSCATTERPF0QPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF0QPSm, X86_INS_VSCATTERPF0QPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF1DPDm, X86_INS_VSCATTERPF1DPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF1DPSm, X86_INS_VSCATTERPF1DPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF1QPDm, X86_INS_VSCATTERPF1QPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERPF1QPSm, X86_INS_VSCATTERPF1QPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PFI, 0 }, 0, 0 #endif }, { X86_VSCATTERQPDZ128mr, X86_INS_VSCATTERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERQPDZ256mr, X86_INS_VSCATTERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERQPDZmr, X86_INS_VSCATTERQPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSCATTERQPSZ128mr, X86_INS_VSCATTERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERQPSZ256mr, X86_INS_VSCATTERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSCATTERQPSZmr, X86_INS_VSCATTERQPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rmbi, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rmbik, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rmbikz, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rmi, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rmik, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rmikz, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rri, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rrik, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Z256rrikz, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrmbi, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrmbik, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrmbikz, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrmi, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrmik, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrmikz, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrri, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrrik, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF32X4Zrrikz, X86_INS_VSHUFF32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rmbi, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rmbik, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rmbikz, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rmi, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rmik, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rmikz, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rri, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rrik, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Z256rrikz, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrmbi, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrmbik, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrmbikz, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrmi, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrmik, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrmikz, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrri, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrrik, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFF64X2Zrrikz, X86_INS_VSHUFF64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rmbi, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rmbik, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rmbikz, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rmi, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rmik, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rmikz, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rri, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rrik, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Z256rrikz, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrmbi, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrmbik, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrmbikz, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrmi, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrmik, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrmikz, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrri, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrrik, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI32X4Zrrikz, X86_INS_VSHUFI32X4, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rmbi, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rmbik, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rmbikz, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rmi, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rmik, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rmikz, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rri, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rrik, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Z256rrikz, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrmbi, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrmbik, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrmbikz, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrmi, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrmik, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrmikz, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrri, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrrik, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFI64X2Zrrikz, X86_INS_VSHUFI64X2, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDYrmi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPDYrri, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rmbi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rmbik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rmbikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rmi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rmik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rmikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rri, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rrik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ128rrikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rmbi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rmbik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rmbikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rmi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rmik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rmikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rri, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rrik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZ256rrikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrmbi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrmbik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrmbikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrmi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSHUFPDZrmik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrmikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrri, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSHUFPDZrrik, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDZrrikz, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPDrmi, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPDrri, X86_INS_VSHUFPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPSYrmi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPSYrri, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rmbi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rmbik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rmbikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rmi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rmik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rmikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rri, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rrik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ128rrikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rmbi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rmbik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rmbikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rmi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rmik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rmikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rri, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rrik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZ256rrikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrmbi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrmbik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrmbikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrmi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSHUFPSZrmik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrmikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrri, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSHUFPSZrrik, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSZrrikz, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSHUFPSrmi, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSHUFPSrri, X86_INS_VSHUFPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPDYm, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPDYr, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128m, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128mb, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128mbk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128mbkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128mk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128mkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128r, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128rk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ128rkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256m, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256mb, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256mbk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256mbkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256mk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256mkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256r, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256rk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZ256rkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPDZm, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZmb, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZmbk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZmbkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZmk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZmkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZr, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZrb, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTPDZrbk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTPDZrbkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTPDZrk, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDZrkz, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPDm, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPDr, X86_INS_VSQRTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPSYm, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPSYr, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128m, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128mb, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128mbk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128mbkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128mk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128mkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128r, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128rk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ128rkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256m, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256mb, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256mbk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256mbkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256mk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256mkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256r, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256rk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZ256rkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSQRTPSZm, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZmb, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZmbk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZmbkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZmk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZmkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZr, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZrb, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTPSZrbk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTPSZrbkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTPSZrk, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSZrkz, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTPSm, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTPSr, X86_INS_VSQRTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSQRTSDZm, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSDZm_Int, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSDZm_Intk, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDZm_Intkz, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDZr, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSDZr_Int, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSDZr_Intk, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDZr_Intkz, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDZrb_Int, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDZrb_Intk, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDZrb_Intkz, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDm, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDm_Int, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDr, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSDr_Int, X86_INS_VSQRTSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZm, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSSZm_Int, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSSZm_Intk, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZm_Intkz, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZr, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSSZr_Int, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSQRTSSZr_Intk, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZr_Intkz, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZrb_Int, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZrb_Intk, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSZrb_Intkz, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSm, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSm_Int, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSr, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSQRTSSr_Int, X86_INS_VSQRTSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSTMXCSR, X86_INS_VSTMXCSR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBPDYrm, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPDYrr, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rm, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rmb, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rmbk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rmbkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rmk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rmkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rr, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rrk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ128rrkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rm, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rmb, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rmbk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rmbkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rmk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rmkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rr, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rrk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZ256rrkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPDZrm, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrmb, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrmbk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrmbkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrmk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrmkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrr, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrrb, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBPDZrrbk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBPDZrrbkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBPDZrrk, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDZrrkz, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPDrm, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPDrr, X86_INS_VSUBPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPSYrm, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPSYrr, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rm, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rmb, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rmbk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rmbkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rmk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rmkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rr, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rrk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ128rrkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rm, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rmb, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rmbk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rmbkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rmk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rmkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rr, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rrk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZ256rrkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_VLX, 0 }, 0, 0 #endif }, { X86_VSUBPSZrm, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrmb, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrmbk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrmbkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrmk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrmkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrr, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrrb, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBPSZrrbk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBPSZrrbkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBPSZrrk, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSZrrkz, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBPSrm, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBPSrr, X86_INS_VSUBPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VSUBSDZrm, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrm_Int, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrm_Intk, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrm_Intkz, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrr, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrr_Int, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrr_Intk, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrr_Intkz, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSDZrrb_Int, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBSDZrrb_Intk, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBSDZrrb_Intkz, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBSDrm, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSDrm_Int, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSDrr, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSDrr_Int, X86_INS_VSUBSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSSZrm, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrm_Int, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrm_Intk, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrm_Intkz, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrr, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrr_Int, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrr_Intk, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrr_Intkz, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VSUBSSZrrb_Int, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBSSZrrb_Intk, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBSSZrrb_Intkz, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VSUBSSrm, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSSrm_Int, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSSrr, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VSUBSSrr_Int, X86_INS_VSUBSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPDYrm, X86_INS_VTESTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPDYrr, X86_INS_VTESTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPDrm, X86_INS_VTESTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPDrr, X86_INS_VTESTPD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPSYrm, X86_INS_VTESTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPSYrr, X86_INS_VTESTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPSrm, X86_INS_VTESTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VTESTPSrr, X86_INS_VTESTPS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUCOMISDZrm, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUCOMISDZrm_Int, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISDZrr, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUCOMISDZrr_Int, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISDZrrb, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISDrm, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUCOMISDrm_Int, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISDrr, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUCOMISDrr_Int, X86_INS_VUCOMISD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISSZrm, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUCOMISSZrm_Int, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISSZrr, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUCOMISSZrr_Int, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISSZrrb, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISSrm, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUCOMISSrm_Int, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUCOMISSrr, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUCOMISSrr_Int, X86_INS_VUCOMISS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDYrm, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPDYrr, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rm, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rmb, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rmbk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rmbkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rmk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rmkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rr, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rrk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ128rrkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rm, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rmb, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rmbk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rmbkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rmk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rmkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rr, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rrk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZ256rrkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrm, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrmb, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrmbk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrmbkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrmk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrmkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrr, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrrk, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDZrrkz, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPDrm, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPDrr, X86_INS_VUNPCKHPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPSYrm, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPSYrr, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rm, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rmb, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rmbk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rmbkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rmk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rmkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rr, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rrk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ128rrkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rm, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rmb, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rmbk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rmbkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rmk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rmkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rr, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rrk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZ256rrkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrm, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrmb, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrmbk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrmbkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrmk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrmkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrr, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrrk, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSZrrkz, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKHPSrm, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKHPSrr, X86_INS_VUNPCKHPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPDYrm, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPDYrr, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rm, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rmb, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rmbk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rmbkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rmk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rmkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rr, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rrk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ128rrkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rm, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rmb, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rmbk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rmbkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rmk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rmkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rr, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rrk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZ256rrkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrm, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrmb, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrmbk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrmbkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrmk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrmkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrr, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrrk, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDZrrkz, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPDrm, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPDrr, X86_INS_VUNPCKLPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPSYrm, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPSYrr, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rm, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rmb, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rmbk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rmbkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rmk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rmkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rr, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rrk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ128rrkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rm, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rmb, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rmbk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rmbkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rmk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rmkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rr, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rrk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZ256rrkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrm, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrmb, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrmbk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrmbkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrmk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrmkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrr, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX512, 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrrk, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSZrrkz, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VUNPCKLPSrm, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VUNPCKLPSrr, X86_INS_VUNPCKLPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VXORPDYrm, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPDYrr, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPDZ128rm, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rmb, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rmbk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rmbkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rmk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rmkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rr, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rrk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ128rrkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rm, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rmb, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rmbk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rmbkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rmk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rmkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rr, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rrk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZ256rrkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrm, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrmb, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrmbk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrmbkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrmk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrmkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrr, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrrk, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDZrrkz, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPDrm, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPDrr, X86_INS_VXORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPSYrm, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPSYrr, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPSZ128rm, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rmb, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rmbk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rmbkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rmk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rmkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rr, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rrk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ128rrkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rm, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rmb, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rmbk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rmbkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rmk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rmkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rr, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rrk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZ256rrkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrm, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrmb, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrmbk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrmbkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrmk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrmkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrr, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrrk, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSZrrkz, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VXORPSrm, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VXORPSrr, X86_INS_VXORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_AVX, X86_GRP_NOVLX, 0 }, 0, 0 #endif }, { X86_VZEROALL, X86_INS_VZEROALL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_VZEROUPPER, X86_INS_VZEROUPPER, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, 0 }, { X86_GRP_AVX, 0 }, 0, 0 #endif }, { X86_WAIT, X86_INS_WAIT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_WBINVD, X86_INS_WBINVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_WBNOINVD, X86_INS_WBNOINVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRFSBASE, X86_INS_WRFSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRFSBASE64, X86_INS_WRFSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRGSBASE, X86_INS_WRGSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRGSBASE64, X86_INS_WRGSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRMSR, X86_INS_WRMSR, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_WRPKRUr, X86_INS_WRPKRU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRSSD, X86_INS_WRSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRSSQ, X86_INS_WRSSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRUSSD, X86_INS_WRUSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRUSSQ, X86_INS_WRUSSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XABORT, X86_INS_XABORT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0 #endif }, { X86_XACQUIRE_PREFIX, X86_INS_XACQUIRE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0 #endif }, { X86_XADD16rm, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD16rr, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD32rm, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD32rr, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD64rm, X86_INS_XADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD64rr, X86_INS_XADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD8rm, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD8rr, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XBEGIN_2, X86_INS_XBEGIN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EAX, 0 }, { X86_GRP_BRANCH_RELATIVE, X86_GRP_RTM, 0 }, 1, 0 #endif }, { X86_XBEGIN_4, X86_INS_XBEGIN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EAX, 0 }, { X86_GRP_BRANCH_RELATIVE, X86_GRP_RTM, 0 }, 1, 0 #endif }, { X86_XCHG16ar, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG16rm, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG16rr, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG32ar, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_XCHG32rm, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG32rr, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG64ar, X86_INS_XCHG, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG64rm, X86_INS_XCHG, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG64rr, X86_INS_XCHG, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG8rm, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG8rr, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCH_F, X86_INS_FXCH, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_FPSW, 0 }, { X86_GRP_FPU, 0 }, 0, 0 #endif }, { X86_XCRYPTCBC, X86_INS_XCRYPTCBC, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTCFB, X86_INS_XCRYPTCFB, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTCTR, X86_INS_XCRYPTCTR, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTECB, X86_INS_XCRYPTECB, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTOFB, X86_INS_XCRYPTOFB, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XEND, X86_INS_XEND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RTM, 0 }, 0, 0 #endif }, { X86_XGETBV, X86_INS_XGETBV, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { X86_REG_EDX, X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_XLAT, X86_INS_XLATB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16i16, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16mi, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16mi8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16mr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16ri, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16ri8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16rm, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16rr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16rr_REV, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32i32, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32mi, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32mi8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32mr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32ri, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32ri8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32rm, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32rr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32rr_REV, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64i32, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64mi32, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64mi8, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64mr, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64ri32, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64ri8, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64rm, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64rr, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64rr_REV, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8i8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8mi, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8mi8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_XOR8mr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8ri, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8ri8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_XOR8rm, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8rr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8rr_REV, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XORPDrm, X86_INS_XORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_XORPDrr, X86_INS_XORPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 #endif }, { X86_XORPSrm, X86_INS_XORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_XORPSrr, X86_INS_XORPS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 #endif }, { X86_XRELEASE_PREFIX, X86_INS_XRELEASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_HLE, 0 }, 0, 0 #endif }, { X86_XRSTOR, X86_INS_XRSTOR, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XRSTOR64, X86_INS_XRSTOR64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XRSTORS, X86_INS_XRSTORS, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_XRSTORS64, X86_INS_XRSTORS64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVE, X86_INS_XSAVE, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVE64, X86_INS_XSAVE64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVEC, X86_INS_XSAVEC, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVEC64, X86_INS_XSAVEC64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVEOPT, X86_INS_XSAVEOPT, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVEOPT64, X86_INS_XSAVEOPT64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVES, X86_INS_XSAVES, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVES64, X86_INS_XSAVES64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSETBV, X86_INS_XSETBV, 0, #ifndef CAPSTONE_DIET { X86_REG_EDX, X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_XSHA1, X86_INS_XSHA1, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XSHA256, X86_INS_XSHA256, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XSTORE, X86_INS_XSTORE, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XTEST, X86_INS_XTEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/X86/X86MappingInsnName.inc000064400000000000000000001356620072674642500215470ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ "aaa", // X86_INS_AAA "aad", // X86_INS_AAD "aam", // X86_INS_AAM "aas", // X86_INS_AAS "fabs", // X86_INS_FABS "adc", // X86_INS_ADC "adcx", // X86_INS_ADCX "add", // X86_INS_ADD "addpd", // X86_INS_ADDPD "addps", // X86_INS_ADDPS "addsd", // X86_INS_ADDSD "addss", // X86_INS_ADDSS "addsubpd", // X86_INS_ADDSUBPD "addsubps", // X86_INS_ADDSUBPS "fadd", // X86_INS_FADD "fiadd", // X86_INS_FIADD "adox", // X86_INS_ADOX "aesdeclast", // X86_INS_AESDECLAST "aesdec", // X86_INS_AESDEC "aesenclast", // X86_INS_AESENCLAST "aesenc", // X86_INS_AESENC "aesimc", // X86_INS_AESIMC "aeskeygenassist", // X86_INS_AESKEYGENASSIST "and", // X86_INS_AND "andn", // X86_INS_ANDN "andnpd", // X86_INS_ANDNPD "andnps", // X86_INS_ANDNPS "andpd", // X86_INS_ANDPD "andps", // X86_INS_ANDPS "arpl", // X86_INS_ARPL "bextr", // X86_INS_BEXTR "blcfill", // X86_INS_BLCFILL "blci", // X86_INS_BLCI "blcic", // X86_INS_BLCIC "blcmsk", // X86_INS_BLCMSK "blcs", // X86_INS_BLCS "blendpd", // X86_INS_BLENDPD "blendps", // X86_INS_BLENDPS "blendvpd", // X86_INS_BLENDVPD "blendvps", // X86_INS_BLENDVPS "blsfill", // X86_INS_BLSFILL "blsi", // X86_INS_BLSI "blsic", // X86_INS_BLSIC "blsmsk", // X86_INS_BLSMSK "blsr", // X86_INS_BLSR "bndcl", // X86_INS_BNDCL "bndcn", // X86_INS_BNDCN "bndcu", // X86_INS_BNDCU "bndldx", // X86_INS_BNDLDX "bndmk", // X86_INS_BNDMK "bndmov", // X86_INS_BNDMOV "bndstx", // X86_INS_BNDSTX "bound", // X86_INS_BOUND "bsf", // X86_INS_BSF "bsr", // X86_INS_BSR "bswap", // X86_INS_BSWAP "bt", // X86_INS_BT "btc", // X86_INS_BTC "btr", // X86_INS_BTR "bts", // X86_INS_BTS "bzhi", // X86_INS_BZHI "call", // X86_INS_CALL "cbw", // X86_INS_CBW "cdq", // X86_INS_CDQ "cdqe", // X86_INS_CDQE "fchs", // X86_INS_FCHS "clac", // X86_INS_CLAC "clc", // X86_INS_CLC "cld", // X86_INS_CLD "cldemote", // X86_INS_CLDEMOTE "clflush", // X86_INS_CLFLUSH "clflushopt", // X86_INS_CLFLUSHOPT "clgi", // X86_INS_CLGI "cli", // X86_INS_CLI "clrssbsy", // X86_INS_CLRSSBSY "clts", // X86_INS_CLTS "clwb", // X86_INS_CLWB "clzero", // X86_INS_CLZERO "cmc", // X86_INS_CMC "cmova", // X86_INS_CMOVA "cmovae", // X86_INS_CMOVAE "cmovb", // X86_INS_CMOVB "cmovbe", // X86_INS_CMOVBE "fcmovbe", // X86_INS_FCMOVBE "fcmovb", // X86_INS_FCMOVB "cmove", // X86_INS_CMOVE "fcmove", // X86_INS_FCMOVE "cmovg", // X86_INS_CMOVG "cmovge", // X86_INS_CMOVGE "cmovl", // X86_INS_CMOVL "cmovle", // X86_INS_CMOVLE "fcmovnbe", // X86_INS_FCMOVNBE "fcmovnb", // X86_INS_FCMOVNB "cmovne", // X86_INS_CMOVNE "fcmovne", // X86_INS_FCMOVNE "cmovno", // X86_INS_CMOVNO "cmovnp", // X86_INS_CMOVNP "fcmovnu", // X86_INS_FCMOVNU "fcmovnp", // X86_INS_FCMOVNP "cmovns", // X86_INS_CMOVNS "cmovo", // X86_INS_CMOVO "cmovp", // X86_INS_CMOVP "fcmovu", // X86_INS_FCMOVU "cmovs", // X86_INS_CMOVS "cmp", // X86_INS_CMP "cmppd", // X86_INS_CMPPD "cmpps", // X86_INS_CMPPS "cmpsb", // X86_INS_CMPSB "cmpsd", // X86_INS_CMPSD "cmpsq", // X86_INS_CMPSQ "cmpss", // X86_INS_CMPSS "cmpsw", // X86_INS_CMPSW "cmpxchg16b", // X86_INS_CMPXCHG16B "cmpxchg", // X86_INS_CMPXCHG "cmpxchg8b", // X86_INS_CMPXCHG8B "comisd", // X86_INS_COMISD "comiss", // X86_INS_COMISS "fcomp", // X86_INS_FCOMP "fcompi", // X86_INS_FCOMPI "fcomi", // X86_INS_FCOMI "fcom", // X86_INS_FCOM "fcos", // X86_INS_FCOS "cpuid", // X86_INS_CPUID "cqo", // X86_INS_CQO "crc32", // X86_INS_CRC32 "cvtdq2pd", // X86_INS_CVTDQ2PD "cvtdq2ps", // X86_INS_CVTDQ2PS "cvtpd2dq", // X86_INS_CVTPD2DQ "cvtpd2ps", // X86_INS_CVTPD2PS "cvtps2dq", // X86_INS_CVTPS2DQ "cvtps2pd", // X86_INS_CVTPS2PD "cvtsd2si", // X86_INS_CVTSD2SI "cvtsd2ss", // X86_INS_CVTSD2SS "cvtsi2sd", // X86_INS_CVTSI2SD "cvtsi2ss", // X86_INS_CVTSI2SS "cvtss2sd", // X86_INS_CVTSS2SD "cvtss2si", // X86_INS_CVTSS2SI "cvttpd2dq", // X86_INS_CVTTPD2DQ "cvttps2dq", // X86_INS_CVTTPS2DQ "cvttsd2si", // X86_INS_CVTTSD2SI "cvttss2si", // X86_INS_CVTTSS2SI "cwd", // X86_INS_CWD "cwde", // X86_INS_CWDE "daa", // X86_INS_DAA "das", // X86_INS_DAS "data16", // X86_INS_DATA16 "dec", // X86_INS_DEC "div", // X86_INS_DIV "divpd", // X86_INS_DIVPD "divps", // X86_INS_DIVPS "fdivr", // X86_INS_FDIVR "fidivr", // X86_INS_FIDIVR "fdivrp", // X86_INS_FDIVRP "divsd", // X86_INS_DIVSD "divss", // X86_INS_DIVSS "fdiv", // X86_INS_FDIV "fidiv", // X86_INS_FIDIV "fdivp", // X86_INS_FDIVP "dppd", // X86_INS_DPPD "dpps", // X86_INS_DPPS "encls", // X86_INS_ENCLS "enclu", // X86_INS_ENCLU "enclv", // X86_INS_ENCLV "endbr32", // X86_INS_ENDBR32 "endbr64", // X86_INS_ENDBR64 "enter", // X86_INS_ENTER "extractps", // X86_INS_EXTRACTPS "extrq", // X86_INS_EXTRQ "f2xm1", // X86_INS_F2XM1 "lcall", // X86_INS_LCALL "ljmp", // X86_INS_LJMP "jmp", // X86_INS_JMP "fbld", // X86_INS_FBLD "fbstp", // X86_INS_FBSTP "fcompp", // X86_INS_FCOMPP "fdecstp", // X86_INS_FDECSTP "fdisi8087_nop", // X86_INS_FDISI8087_NOP "femms", // X86_INS_FEMMS "feni8087_nop", // X86_INS_FENI8087_NOP "ffree", // X86_INS_FFREE "ffreep", // X86_INS_FFREEP "ficom", // X86_INS_FICOM "ficomp", // X86_INS_FICOMP "fincstp", // X86_INS_FINCSTP "fldcw", // X86_INS_FLDCW "fldenv", // X86_INS_FLDENV "fldl2e", // X86_INS_FLDL2E "fldl2t", // X86_INS_FLDL2T "fldlg2", // X86_INS_FLDLG2 "fldln2", // X86_INS_FLDLN2 "fldpi", // X86_INS_FLDPI "fnclex", // X86_INS_FNCLEX "fninit", // X86_INS_FNINIT "fnop", // X86_INS_FNOP "fnstcw", // X86_INS_FNSTCW "fnstsw", // X86_INS_FNSTSW "fpatan", // X86_INS_FPATAN "fstpnce", // X86_INS_FSTPNCE "fprem", // X86_INS_FPREM "fprem1", // X86_INS_FPREM1 "fptan", // X86_INS_FPTAN "frndint", // X86_INS_FRNDINT "frstor", // X86_INS_FRSTOR "fnsave", // X86_INS_FNSAVE "fscale", // X86_INS_FSCALE "fsetpm", // X86_INS_FSETPM "fsincos", // X86_INS_FSINCOS "fnstenv", // X86_INS_FNSTENV "fxam", // X86_INS_FXAM "fxrstor", // X86_INS_FXRSTOR "fxrstor64", // X86_INS_FXRSTOR64 "fxsave", // X86_INS_FXSAVE "fxsave64", // X86_INS_FXSAVE64 "fxtract", // X86_INS_FXTRACT "fyl2x", // X86_INS_FYL2X "fyl2xp1", // X86_INS_FYL2XP1 "getsec", // X86_INS_GETSEC "gf2p8affineinvqb", // X86_INS_GF2P8AFFINEINVQB "gf2p8affineqb", // X86_INS_GF2P8AFFINEQB "gf2p8mulb", // X86_INS_GF2P8MULB "haddpd", // X86_INS_HADDPD "haddps", // X86_INS_HADDPS "hlt", // X86_INS_HLT "hsubpd", // X86_INS_HSUBPD "hsubps", // X86_INS_HSUBPS "idiv", // X86_INS_IDIV "fild", // X86_INS_FILD "imul", // X86_INS_IMUL "in", // X86_INS_IN "inc", // X86_INS_INC "incsspd", // X86_INS_INCSSPD "incsspq", // X86_INS_INCSSPQ "insb", // X86_INS_INSB "insertps", // X86_INS_INSERTPS "insertq", // X86_INS_INSERTQ "insd", // X86_INS_INSD "insw", // X86_INS_INSW "int", // X86_INS_INT "int1", // X86_INS_INT1 "int3", // X86_INS_INT3 "into", // X86_INS_INTO "invd", // X86_INS_INVD "invept", // X86_INS_INVEPT "invlpg", // X86_INS_INVLPG "invlpga", // X86_INS_INVLPGA "invpcid", // X86_INS_INVPCID "invvpid", // X86_INS_INVVPID "iret", // X86_INS_IRET "iretd", // X86_INS_IRETD "iretq", // X86_INS_IRETQ "fisttp", // X86_INS_FISTTP "fist", // X86_INS_FIST "fistp", // X86_INS_FISTP "jae", // X86_INS_JAE "ja", // X86_INS_JA "jbe", // X86_INS_JBE "jb", // X86_INS_JB "jcxz", // X86_INS_JCXZ "jecxz", // X86_INS_JECXZ "je", // X86_INS_JE "jge", // X86_INS_JGE "jg", // X86_INS_JG "jle", // X86_INS_JLE "jl", // X86_INS_JL "jne", // X86_INS_JNE "jno", // X86_INS_JNO "jnp", // X86_INS_JNP "jns", // X86_INS_JNS "jo", // X86_INS_JO "jp", // X86_INS_JP "jrcxz", // X86_INS_JRCXZ "js", // X86_INS_JS "kaddb", // X86_INS_KADDB "kaddd", // X86_INS_KADDD "kaddq", // X86_INS_KADDQ "kaddw", // X86_INS_KADDW "kandb", // X86_INS_KANDB "kandd", // X86_INS_KANDD "kandnb", // X86_INS_KANDNB "kandnd", // X86_INS_KANDND "kandnq", // X86_INS_KANDNQ "kandnw", // X86_INS_KANDNW "kandq", // X86_INS_KANDQ "kandw", // X86_INS_KANDW "kmovb", // X86_INS_KMOVB "kmovd", // X86_INS_KMOVD "kmovq", // X86_INS_KMOVQ "kmovw", // X86_INS_KMOVW "knotb", // X86_INS_KNOTB "knotd", // X86_INS_KNOTD "knotq", // X86_INS_KNOTQ "knotw", // X86_INS_KNOTW "korb", // X86_INS_KORB "kord", // X86_INS_KORD "korq", // X86_INS_KORQ "kortestb", // X86_INS_KORTESTB "kortestd", // X86_INS_KORTESTD "kortestq", // X86_INS_KORTESTQ "kortestw", // X86_INS_KORTESTW "korw", // X86_INS_KORW "kshiftlb", // X86_INS_KSHIFTLB "kshiftld", // X86_INS_KSHIFTLD "kshiftlq", // X86_INS_KSHIFTLQ "kshiftlw", // X86_INS_KSHIFTLW "kshiftrb", // X86_INS_KSHIFTRB "kshiftrd", // X86_INS_KSHIFTRD "kshiftrq", // X86_INS_KSHIFTRQ "kshiftrw", // X86_INS_KSHIFTRW "ktestb", // X86_INS_KTESTB "ktestd", // X86_INS_KTESTD "ktestq", // X86_INS_KTESTQ "ktestw", // X86_INS_KTESTW "kunpckbw", // X86_INS_KUNPCKBW "kunpckdq", // X86_INS_KUNPCKDQ "kunpckwd", // X86_INS_KUNPCKWD "kxnorb", // X86_INS_KXNORB "kxnord", // X86_INS_KXNORD "kxnorq", // X86_INS_KXNORQ "kxnorw", // X86_INS_KXNORW "kxorb", // X86_INS_KXORB "kxord", // X86_INS_KXORD "kxorq", // X86_INS_KXORQ "kxorw", // X86_INS_KXORW "lahf", // X86_INS_LAHF "lar", // X86_INS_LAR "lddqu", // X86_INS_LDDQU "ldmxcsr", // X86_INS_LDMXCSR "lds", // X86_INS_LDS "fldz", // X86_INS_FLDZ "fld1", // X86_INS_FLD1 "fld", // X86_INS_FLD "lea", // X86_INS_LEA "leave", // X86_INS_LEAVE "les", // X86_INS_LES "lfence", // X86_INS_LFENCE "lfs", // X86_INS_LFS "lgdt", // X86_INS_LGDT "lgs", // X86_INS_LGS "lidt", // X86_INS_LIDT "lldt", // X86_INS_LLDT "llwpcb", // X86_INS_LLWPCB "lmsw", // X86_INS_LMSW "lock", // X86_INS_LOCK "lodsb", // X86_INS_LODSB "lodsd", // X86_INS_LODSD "lodsq", // X86_INS_LODSQ "lodsw", // X86_INS_LODSW "loop", // X86_INS_LOOP "loope", // X86_INS_LOOPE "loopne", // X86_INS_LOOPNE "retf", // X86_INS_RETF "retfq", // X86_INS_RETFQ "lsl", // X86_INS_LSL "lss", // X86_INS_LSS "ltr", // X86_INS_LTR "lwpins", // X86_INS_LWPINS "lwpval", // X86_INS_LWPVAL "lzcnt", // X86_INS_LZCNT "maskmovdqu", // X86_INS_MASKMOVDQU "maxpd", // X86_INS_MAXPD "maxps", // X86_INS_MAXPS "maxsd", // X86_INS_MAXSD "maxss", // X86_INS_MAXSS "mfence", // X86_INS_MFENCE "minpd", // X86_INS_MINPD "minps", // X86_INS_MINPS "minsd", // X86_INS_MINSD "minss", // X86_INS_MINSS "cvtpd2pi", // X86_INS_CVTPD2PI "cvtpi2pd", // X86_INS_CVTPI2PD "cvtpi2ps", // X86_INS_CVTPI2PS "cvtps2pi", // X86_INS_CVTPS2PI "cvttpd2pi", // X86_INS_CVTTPD2PI "cvttps2pi", // X86_INS_CVTTPS2PI "emms", // X86_INS_EMMS "maskmovq", // X86_INS_MASKMOVQ "movd", // X86_INS_MOVD "movq", // X86_INS_MOVQ "movdq2q", // X86_INS_MOVDQ2Q "movntq", // X86_INS_MOVNTQ "movq2dq", // X86_INS_MOVQ2DQ "pabsb", // X86_INS_PABSB "pabsd", // X86_INS_PABSD "pabsw", // X86_INS_PABSW "packssdw", // X86_INS_PACKSSDW "packsswb", // X86_INS_PACKSSWB "packuswb", // X86_INS_PACKUSWB "paddb", // X86_INS_PADDB "paddd", // X86_INS_PADDD "paddq", // X86_INS_PADDQ "paddsb", // X86_INS_PADDSB "paddsw", // X86_INS_PADDSW "paddusb", // X86_INS_PADDUSB "paddusw", // X86_INS_PADDUSW "paddw", // X86_INS_PADDW "palignr", // X86_INS_PALIGNR "pandn", // X86_INS_PANDN "pand", // X86_INS_PAND "pavgb", // X86_INS_PAVGB "pavgw", // X86_INS_PAVGW "pcmpeqb", // X86_INS_PCMPEQB "pcmpeqd", // X86_INS_PCMPEQD "pcmpeqw", // X86_INS_PCMPEQW "pcmpgtb", // X86_INS_PCMPGTB "pcmpgtd", // X86_INS_PCMPGTD "pcmpgtw", // X86_INS_PCMPGTW "pextrw", // X86_INS_PEXTRW "phaddd", // X86_INS_PHADDD "phaddsw", // X86_INS_PHADDSW "phaddw", // X86_INS_PHADDW "phsubd", // X86_INS_PHSUBD "phsubsw", // X86_INS_PHSUBSW "phsubw", // X86_INS_PHSUBW "pinsrw", // X86_INS_PINSRW "pmaddubsw", // X86_INS_PMADDUBSW "pmaddwd", // X86_INS_PMADDWD "pmaxsw", // X86_INS_PMAXSW "pmaxub", // X86_INS_PMAXUB "pminsw", // X86_INS_PMINSW "pminub", // X86_INS_PMINUB "pmovmskb", // X86_INS_PMOVMSKB "pmulhrsw", // X86_INS_PMULHRSW "pmulhuw", // X86_INS_PMULHUW "pmulhw", // X86_INS_PMULHW "pmullw", // X86_INS_PMULLW "pmuludq", // X86_INS_PMULUDQ "por", // X86_INS_POR "psadbw", // X86_INS_PSADBW "pshufb", // X86_INS_PSHUFB "pshufw", // X86_INS_PSHUFW "psignb", // X86_INS_PSIGNB "psignd", // X86_INS_PSIGND "psignw", // X86_INS_PSIGNW "pslld", // X86_INS_PSLLD "psllq", // X86_INS_PSLLQ "psllw", // X86_INS_PSLLW "psrad", // X86_INS_PSRAD "psraw", // X86_INS_PSRAW "psrld", // X86_INS_PSRLD "psrlq", // X86_INS_PSRLQ "psrlw", // X86_INS_PSRLW "psubb", // X86_INS_PSUBB "psubd", // X86_INS_PSUBD "psubq", // X86_INS_PSUBQ "psubsb", // X86_INS_PSUBSB "psubsw", // X86_INS_PSUBSW "psubusb", // X86_INS_PSUBUSB "psubusw", // X86_INS_PSUBUSW "psubw", // X86_INS_PSUBW "punpckhbw", // X86_INS_PUNPCKHBW "punpckhdq", // X86_INS_PUNPCKHDQ "punpckhwd", // X86_INS_PUNPCKHWD "punpcklbw", // X86_INS_PUNPCKLBW "punpckldq", // X86_INS_PUNPCKLDQ "punpcklwd", // X86_INS_PUNPCKLWD "pxor", // X86_INS_PXOR "monitorx", // X86_INS_MONITORX "monitor", // X86_INS_MONITOR "montmul", // X86_INS_MONTMUL "mov", // X86_INS_MOV "movabs", // X86_INS_MOVABS "movapd", // X86_INS_MOVAPD "movaps", // X86_INS_MOVAPS "movbe", // X86_INS_MOVBE "movddup", // X86_INS_MOVDDUP "movdir64b", // X86_INS_MOVDIR64B "movdiri", // X86_INS_MOVDIRI "movdqa", // X86_INS_MOVDQA "movdqu", // X86_INS_MOVDQU "movhlps", // X86_INS_MOVHLPS "movhpd", // X86_INS_MOVHPD "movhps", // X86_INS_MOVHPS "movlhps", // X86_INS_MOVLHPS "movlpd", // X86_INS_MOVLPD "movlps", // X86_INS_MOVLPS "movmskpd", // X86_INS_MOVMSKPD "movmskps", // X86_INS_MOVMSKPS "movntdqa", // X86_INS_MOVNTDQA "movntdq", // X86_INS_MOVNTDQ "movnti", // X86_INS_MOVNTI "movntpd", // X86_INS_MOVNTPD "movntps", // X86_INS_MOVNTPS "movntsd", // X86_INS_MOVNTSD "movntss", // X86_INS_MOVNTSS "movsb", // X86_INS_MOVSB "movsd", // X86_INS_MOVSD "movshdup", // X86_INS_MOVSHDUP "movsldup", // X86_INS_MOVSLDUP "movsq", // X86_INS_MOVSQ "movss", // X86_INS_MOVSS "movsw", // X86_INS_MOVSW "movsx", // X86_INS_MOVSX "movsxd", // X86_INS_MOVSXD "movupd", // X86_INS_MOVUPD "movups", // X86_INS_MOVUPS "movzx", // X86_INS_MOVZX "mpsadbw", // X86_INS_MPSADBW "mul", // X86_INS_MUL "mulpd", // X86_INS_MULPD "mulps", // X86_INS_MULPS "mulsd", // X86_INS_MULSD "mulss", // X86_INS_MULSS "mulx", // X86_INS_MULX "fmul", // X86_INS_FMUL "fimul", // X86_INS_FIMUL "fmulp", // X86_INS_FMULP "mwaitx", // X86_INS_MWAITX "mwait", // X86_INS_MWAIT "neg", // X86_INS_NEG "nop", // X86_INS_NOP "not", // X86_INS_NOT "or", // X86_INS_OR "orpd", // X86_INS_ORPD "orps", // X86_INS_ORPS "out", // X86_INS_OUT "outsb", // X86_INS_OUTSB "outsd", // X86_INS_OUTSD "outsw", // X86_INS_OUTSW "packusdw", // X86_INS_PACKUSDW "pause", // X86_INS_PAUSE "pavgusb", // X86_INS_PAVGUSB "pblendvb", // X86_INS_PBLENDVB "pblendw", // X86_INS_PBLENDW "pclmulqdq", // X86_INS_PCLMULQDQ "pcmpeqq", // X86_INS_PCMPEQQ "pcmpestri", // X86_INS_PCMPESTRI "pcmpestrm", // X86_INS_PCMPESTRM "pcmpgtq", // X86_INS_PCMPGTQ "pcmpistri", // X86_INS_PCMPISTRI "pcmpistrm", // X86_INS_PCMPISTRM "pconfig", // X86_INS_PCONFIG "pdep", // X86_INS_PDEP "pext", // X86_INS_PEXT "pextrb", // X86_INS_PEXTRB "pextrd", // X86_INS_PEXTRD "pextrq", // X86_INS_PEXTRQ "pf2id", // X86_INS_PF2ID "pf2iw", // X86_INS_PF2IW "pfacc", // X86_INS_PFACC "pfadd", // X86_INS_PFADD "pfcmpeq", // X86_INS_PFCMPEQ "pfcmpge", // X86_INS_PFCMPGE "pfcmpgt", // X86_INS_PFCMPGT "pfmax", // X86_INS_PFMAX "pfmin", // X86_INS_PFMIN "pfmul", // X86_INS_PFMUL "pfnacc", // X86_INS_PFNACC "pfpnacc", // X86_INS_PFPNACC "pfrcpit1", // X86_INS_PFRCPIT1 "pfrcpit2", // X86_INS_PFRCPIT2 "pfrcp", // X86_INS_PFRCP "pfrsqit1", // X86_INS_PFRSQIT1 "pfrsqrt", // X86_INS_PFRSQRT "pfsubr", // X86_INS_PFSUBR "pfsub", // X86_INS_PFSUB "phminposuw", // X86_INS_PHMINPOSUW "pi2fd", // X86_INS_PI2FD "pi2fw", // X86_INS_PI2FW "pinsrb", // X86_INS_PINSRB "pinsrd", // X86_INS_PINSRD "pinsrq", // X86_INS_PINSRQ "pmaxsb", // X86_INS_PMAXSB "pmaxsd", // X86_INS_PMAXSD "pmaxud", // X86_INS_PMAXUD "pmaxuw", // X86_INS_PMAXUW "pminsb", // X86_INS_PMINSB "pminsd", // X86_INS_PMINSD "pminud", // X86_INS_PMINUD "pminuw", // X86_INS_PMINUW "pmovsxbd", // X86_INS_PMOVSXBD "pmovsxbq", // X86_INS_PMOVSXBQ "pmovsxbw", // X86_INS_PMOVSXBW "pmovsxdq", // X86_INS_PMOVSXDQ "pmovsxwd", // X86_INS_PMOVSXWD "pmovsxwq", // X86_INS_PMOVSXWQ "pmovzxbd", // X86_INS_PMOVZXBD "pmovzxbq", // X86_INS_PMOVZXBQ "pmovzxbw", // X86_INS_PMOVZXBW "pmovzxdq", // X86_INS_PMOVZXDQ "pmovzxwd", // X86_INS_PMOVZXWD "pmovzxwq", // X86_INS_PMOVZXWQ "pmuldq", // X86_INS_PMULDQ "pmulhrw", // X86_INS_PMULHRW "pmulld", // X86_INS_PMULLD "pop", // X86_INS_POP "popaw", // X86_INS_POPAW "popal", // X86_INS_POPAL "popcnt", // X86_INS_POPCNT "popf", // X86_INS_POPF "popfd", // X86_INS_POPFD "popfq", // X86_INS_POPFQ "prefetch", // X86_INS_PREFETCH "prefetchnta", // X86_INS_PREFETCHNTA "prefetcht0", // X86_INS_PREFETCHT0 "prefetcht1", // X86_INS_PREFETCHT1 "prefetcht2", // X86_INS_PREFETCHT2 "prefetchw", // X86_INS_PREFETCHW "prefetchwt1", // X86_INS_PREFETCHWT1 "pshufd", // X86_INS_PSHUFD "pshufhw", // X86_INS_PSHUFHW "pshuflw", // X86_INS_PSHUFLW "pslldq", // X86_INS_PSLLDQ "psrldq", // X86_INS_PSRLDQ "pswapd", // X86_INS_PSWAPD "ptest", // X86_INS_PTEST "ptwrite", // X86_INS_PTWRITE "punpckhqdq", // X86_INS_PUNPCKHQDQ "punpcklqdq", // X86_INS_PUNPCKLQDQ "push", // X86_INS_PUSH "pushaw", // X86_INS_PUSHAW "pushal", // X86_INS_PUSHAL "pushf", // X86_INS_PUSHF "pushfd", // X86_INS_PUSHFD "pushfq", // X86_INS_PUSHFQ "rcl", // X86_INS_RCL "rcpps", // X86_INS_RCPPS "rcpss", // X86_INS_RCPSS "rcr", // X86_INS_RCR "rdfsbase", // X86_INS_RDFSBASE "rdgsbase", // X86_INS_RDGSBASE "rdmsr", // X86_INS_RDMSR "rdpid", // X86_INS_RDPID "rdpkru", // X86_INS_RDPKRU "rdpmc", // X86_INS_RDPMC "rdrand", // X86_INS_RDRAND "rdseed", // X86_INS_RDSEED "rdsspd", // X86_INS_RDSSPD "rdsspq", // X86_INS_RDSSPQ "rdtsc", // X86_INS_RDTSC "rdtscp", // X86_INS_RDTSCP "repne", // X86_INS_REPNE "rep", // X86_INS_REP "ret", // X86_INS_RET "rex64", // X86_INS_REX64 "rol", // X86_INS_ROL "ror", // X86_INS_ROR "rorx", // X86_INS_RORX "roundpd", // X86_INS_ROUNDPD "roundps", // X86_INS_ROUNDPS "roundsd", // X86_INS_ROUNDSD "roundss", // X86_INS_ROUNDSS "rsm", // X86_INS_RSM "rsqrtps", // X86_INS_RSQRTPS "rsqrtss", // X86_INS_RSQRTSS "rstorssp", // X86_INS_RSTORSSP "sahf", // X86_INS_SAHF "sal", // X86_INS_SAL "salc", // X86_INS_SALC "sar", // X86_INS_SAR "sarx", // X86_INS_SARX "saveprevssp", // X86_INS_SAVEPREVSSP "sbb", // X86_INS_SBB "scasb", // X86_INS_SCASB "scasd", // X86_INS_SCASD "scasq", // X86_INS_SCASQ "scasw", // X86_INS_SCASW "setae", // X86_INS_SETAE "seta", // X86_INS_SETA "setbe", // X86_INS_SETBE "setb", // X86_INS_SETB "sete", // X86_INS_SETE "setge", // X86_INS_SETGE "setg", // X86_INS_SETG "setle", // X86_INS_SETLE "setl", // X86_INS_SETL "setne", // X86_INS_SETNE "setno", // X86_INS_SETNO "setnp", // X86_INS_SETNP "setns", // X86_INS_SETNS "seto", // X86_INS_SETO "setp", // X86_INS_SETP "setssbsy", // X86_INS_SETSSBSY "sets", // X86_INS_SETS "sfence", // X86_INS_SFENCE "sgdt", // X86_INS_SGDT "sha1msg1", // X86_INS_SHA1MSG1 "sha1msg2", // X86_INS_SHA1MSG2 "sha1nexte", // X86_INS_SHA1NEXTE "sha1rnds4", // X86_INS_SHA1RNDS4 "sha256msg1", // X86_INS_SHA256MSG1 "sha256msg2", // X86_INS_SHA256MSG2 "sha256rnds2", // X86_INS_SHA256RNDS2 "shl", // X86_INS_SHL "shld", // X86_INS_SHLD "shlx", // X86_INS_SHLX "shr", // X86_INS_SHR "shrd", // X86_INS_SHRD "shrx", // X86_INS_SHRX "shufpd", // X86_INS_SHUFPD "shufps", // X86_INS_SHUFPS "sidt", // X86_INS_SIDT "fsin", // X86_INS_FSIN "skinit", // X86_INS_SKINIT "sldt", // X86_INS_SLDT "slwpcb", // X86_INS_SLWPCB "smsw", // X86_INS_SMSW "sqrtpd", // X86_INS_SQRTPD "sqrtps", // X86_INS_SQRTPS "sqrtsd", // X86_INS_SQRTSD "sqrtss", // X86_INS_SQRTSS "fsqrt", // X86_INS_FSQRT "stac", // X86_INS_STAC "stc", // X86_INS_STC "std", // X86_INS_STD "stgi", // X86_INS_STGI "sti", // X86_INS_STI "stmxcsr", // X86_INS_STMXCSR "stosb", // X86_INS_STOSB "stosd", // X86_INS_STOSD "stosq", // X86_INS_STOSQ "stosw", // X86_INS_STOSW "str", // X86_INS_STR "fst", // X86_INS_FST "fstp", // X86_INS_FSTP "sub", // X86_INS_SUB "subpd", // X86_INS_SUBPD "subps", // X86_INS_SUBPS "fsubr", // X86_INS_FSUBR "fisubr", // X86_INS_FISUBR "fsubrp", // X86_INS_FSUBRP "subsd", // X86_INS_SUBSD "subss", // X86_INS_SUBSS "fsub", // X86_INS_FSUB "fisub", // X86_INS_FISUB "fsubp", // X86_INS_FSUBP "swapgs", // X86_INS_SWAPGS "syscall", // X86_INS_SYSCALL "sysenter", // X86_INS_SYSENTER "sysexit", // X86_INS_SYSEXIT "sysexitq", // X86_INS_SYSEXITQ "sysret", // X86_INS_SYSRET "sysretq", // X86_INS_SYSRETQ "t1mskc", // X86_INS_T1MSKC "test", // X86_INS_TEST "tpause", // X86_INS_TPAUSE "ftst", // X86_INS_FTST "tzcnt", // X86_INS_TZCNT "tzmsk", // X86_INS_TZMSK "ucomisd", // X86_INS_UCOMISD "ucomiss", // X86_INS_UCOMISS "fucompi", // X86_INS_FUCOMPI "fucomi", // X86_INS_FUCOMI "fucompp", // X86_INS_FUCOMPP "fucomp", // X86_INS_FUCOMP "fucom", // X86_INS_FUCOM "ud0", // X86_INS_UD0 "ud1", // X86_INS_UD1 "ud2", // X86_INS_UD2 "umonitor", // X86_INS_UMONITOR "umwait", // X86_INS_UMWAIT "unpckhpd", // X86_INS_UNPCKHPD "unpckhps", // X86_INS_UNPCKHPS "unpcklpd", // X86_INS_UNPCKLPD "unpcklps", // X86_INS_UNPCKLPS "v4fmaddps", // X86_INS_V4FMADDPS "v4fmaddss", // X86_INS_V4FMADDSS "v4fnmaddps", // X86_INS_V4FNMADDPS "v4fnmaddss", // X86_INS_V4FNMADDSS "vaddpd", // X86_INS_VADDPD "vaddps", // X86_INS_VADDPS "vaddsd", // X86_INS_VADDSD "vaddss", // X86_INS_VADDSS "vaddsubpd", // X86_INS_VADDSUBPD "vaddsubps", // X86_INS_VADDSUBPS "vaesdeclast", // X86_INS_VAESDECLAST "vaesdec", // X86_INS_VAESDEC "vaesenclast", // X86_INS_VAESENCLAST "vaesenc", // X86_INS_VAESENC "vaesimc", // X86_INS_VAESIMC "vaeskeygenassist", // X86_INS_VAESKEYGENASSIST "valignd", // X86_INS_VALIGND "valignq", // X86_INS_VALIGNQ "vandnpd", // X86_INS_VANDNPD "vandnps", // X86_INS_VANDNPS "vandpd", // X86_INS_VANDPD "vandps", // X86_INS_VANDPS "vblendmpd", // X86_INS_VBLENDMPD "vblendmps", // X86_INS_VBLENDMPS "vblendpd", // X86_INS_VBLENDPD "vblendps", // X86_INS_VBLENDPS "vblendvpd", // X86_INS_VBLENDVPD "vblendvps", // X86_INS_VBLENDVPS "vbroadcastf128", // X86_INS_VBROADCASTF128 "vbroadcastf32x2", // X86_INS_VBROADCASTF32X2 "vbroadcastf32x4", // X86_INS_VBROADCASTF32X4 "vbroadcastf32x8", // X86_INS_VBROADCASTF32X8 "vbroadcastf64x2", // X86_INS_VBROADCASTF64X2 "vbroadcastf64x4", // X86_INS_VBROADCASTF64X4 "vbroadcasti128", // X86_INS_VBROADCASTI128 "vbroadcasti32x2", // X86_INS_VBROADCASTI32X2 "vbroadcasti32x4", // X86_INS_VBROADCASTI32X4 "vbroadcasti32x8", // X86_INS_VBROADCASTI32X8 "vbroadcasti64x2", // X86_INS_VBROADCASTI64X2 "vbroadcasti64x4", // X86_INS_VBROADCASTI64X4 "vbroadcastsd", // X86_INS_VBROADCASTSD "vbroadcastss", // X86_INS_VBROADCASTSS "vcmp", // X86_INS_VCMP "vcmppd", // X86_INS_VCMPPD "vcmpps", // X86_INS_VCMPPS "vcmpsd", // X86_INS_VCMPSD "vcmpss", // X86_INS_VCMPSS "vcomisd", // X86_INS_VCOMISD "vcomiss", // X86_INS_VCOMISS "vcompresspd", // X86_INS_VCOMPRESSPD "vcompressps", // X86_INS_VCOMPRESSPS "vcvtdq2pd", // X86_INS_VCVTDQ2PD "vcvtdq2ps", // X86_INS_VCVTDQ2PS "vcvtpd2dq", // X86_INS_VCVTPD2DQ "vcvtpd2ps", // X86_INS_VCVTPD2PS "vcvtpd2qq", // X86_INS_VCVTPD2QQ "vcvtpd2udq", // X86_INS_VCVTPD2UDQ "vcvtpd2uqq", // X86_INS_VCVTPD2UQQ "vcvtph2ps", // X86_INS_VCVTPH2PS "vcvtps2dq", // X86_INS_VCVTPS2DQ "vcvtps2pd", // X86_INS_VCVTPS2PD "vcvtps2ph", // X86_INS_VCVTPS2PH "vcvtps2qq", // X86_INS_VCVTPS2QQ "vcvtps2udq", // X86_INS_VCVTPS2UDQ "vcvtps2uqq", // X86_INS_VCVTPS2UQQ "vcvtqq2pd", // X86_INS_VCVTQQ2PD "vcvtqq2ps", // X86_INS_VCVTQQ2PS "vcvtsd2si", // X86_INS_VCVTSD2SI "vcvtsd2ss", // X86_INS_VCVTSD2SS "vcvtsd2usi", // X86_INS_VCVTSD2USI "vcvtsi2sd", // X86_INS_VCVTSI2SD "vcvtsi2ss", // X86_INS_VCVTSI2SS "vcvtss2sd", // X86_INS_VCVTSS2SD "vcvtss2si", // X86_INS_VCVTSS2SI "vcvtss2usi", // X86_INS_VCVTSS2USI "vcvttpd2dq", // X86_INS_VCVTTPD2DQ "vcvttpd2qq", // X86_INS_VCVTTPD2QQ "vcvttpd2udq", // X86_INS_VCVTTPD2UDQ "vcvttpd2uqq", // X86_INS_VCVTTPD2UQQ "vcvttps2dq", // X86_INS_VCVTTPS2DQ "vcvttps2qq", // X86_INS_VCVTTPS2QQ "vcvttps2udq", // X86_INS_VCVTTPS2UDQ "vcvttps2uqq", // X86_INS_VCVTTPS2UQQ "vcvttsd2si", // X86_INS_VCVTTSD2SI "vcvttsd2usi", // X86_INS_VCVTTSD2USI "vcvttss2si", // X86_INS_VCVTTSS2SI "vcvttss2usi", // X86_INS_VCVTTSS2USI "vcvtudq2pd", // X86_INS_VCVTUDQ2PD "vcvtudq2ps", // X86_INS_VCVTUDQ2PS "vcvtuqq2pd", // X86_INS_VCVTUQQ2PD "vcvtuqq2ps", // X86_INS_VCVTUQQ2PS "vcvtusi2sd", // X86_INS_VCVTUSI2SD "vcvtusi2ss", // X86_INS_VCVTUSI2SS "vdbpsadbw", // X86_INS_VDBPSADBW "vdivpd", // X86_INS_VDIVPD "vdivps", // X86_INS_VDIVPS "vdivsd", // X86_INS_VDIVSD "vdivss", // X86_INS_VDIVSS "vdppd", // X86_INS_VDPPD "vdpps", // X86_INS_VDPPS "verr", // X86_INS_VERR "verw", // X86_INS_VERW "vexp2pd", // X86_INS_VEXP2PD "vexp2ps", // X86_INS_VEXP2PS "vexpandpd", // X86_INS_VEXPANDPD "vexpandps", // X86_INS_VEXPANDPS "vextractf128", // X86_INS_VEXTRACTF128 "vextractf32x4", // X86_INS_VEXTRACTF32X4 "vextractf32x8", // X86_INS_VEXTRACTF32X8 "vextractf64x2", // X86_INS_VEXTRACTF64X2 "vextractf64x4", // X86_INS_VEXTRACTF64X4 "vextracti128", // X86_INS_VEXTRACTI128 "vextracti32x4", // X86_INS_VEXTRACTI32X4 "vextracti32x8", // X86_INS_VEXTRACTI32X8 "vextracti64x2", // X86_INS_VEXTRACTI64X2 "vextracti64x4", // X86_INS_VEXTRACTI64X4 "vextractps", // X86_INS_VEXTRACTPS "vfixupimmpd", // X86_INS_VFIXUPIMMPD "vfixupimmps", // X86_INS_VFIXUPIMMPS "vfixupimmsd", // X86_INS_VFIXUPIMMSD "vfixupimmss", // X86_INS_VFIXUPIMMSS "vfmadd132pd", // X86_INS_VFMADD132PD "vfmadd132ps", // X86_INS_VFMADD132PS "vfmadd132sd", // X86_INS_VFMADD132SD "vfmadd132ss", // X86_INS_VFMADD132SS "vfmadd213pd", // X86_INS_VFMADD213PD "vfmadd213ps", // X86_INS_VFMADD213PS "vfmadd213sd", // X86_INS_VFMADD213SD "vfmadd213ss", // X86_INS_VFMADD213SS "vfmadd231pd", // X86_INS_VFMADD231PD "vfmadd231ps", // X86_INS_VFMADD231PS "vfmadd231sd", // X86_INS_VFMADD231SD "vfmadd231ss", // X86_INS_VFMADD231SS "vfmaddpd", // X86_INS_VFMADDPD "vfmaddps", // X86_INS_VFMADDPS "vfmaddsd", // X86_INS_VFMADDSD "vfmaddss", // X86_INS_VFMADDSS "vfmaddsub132pd", // X86_INS_VFMADDSUB132PD "vfmaddsub132ps", // X86_INS_VFMADDSUB132PS "vfmaddsub213pd", // X86_INS_VFMADDSUB213PD "vfmaddsub213ps", // X86_INS_VFMADDSUB213PS "vfmaddsub231pd", // X86_INS_VFMADDSUB231PD "vfmaddsub231ps", // X86_INS_VFMADDSUB231PS "vfmaddsubpd", // X86_INS_VFMADDSUBPD "vfmaddsubps", // X86_INS_VFMADDSUBPS "vfmsub132pd", // X86_INS_VFMSUB132PD "vfmsub132ps", // X86_INS_VFMSUB132PS "vfmsub132sd", // X86_INS_VFMSUB132SD "vfmsub132ss", // X86_INS_VFMSUB132SS "vfmsub213pd", // X86_INS_VFMSUB213PD "vfmsub213ps", // X86_INS_VFMSUB213PS "vfmsub213sd", // X86_INS_VFMSUB213SD "vfmsub213ss", // X86_INS_VFMSUB213SS "vfmsub231pd", // X86_INS_VFMSUB231PD "vfmsub231ps", // X86_INS_VFMSUB231PS "vfmsub231sd", // X86_INS_VFMSUB231SD "vfmsub231ss", // X86_INS_VFMSUB231SS "vfmsubadd132pd", // X86_INS_VFMSUBADD132PD "vfmsubadd132ps", // X86_INS_VFMSUBADD132PS "vfmsubadd213pd", // X86_INS_VFMSUBADD213PD "vfmsubadd213ps", // X86_INS_VFMSUBADD213PS "vfmsubadd231pd", // X86_INS_VFMSUBADD231PD "vfmsubadd231ps", // X86_INS_VFMSUBADD231PS "vfmsubaddpd", // X86_INS_VFMSUBADDPD "vfmsubaddps", // X86_INS_VFMSUBADDPS "vfmsubpd", // X86_INS_VFMSUBPD "vfmsubps", // X86_INS_VFMSUBPS "vfmsubsd", // X86_INS_VFMSUBSD "vfmsubss", // X86_INS_VFMSUBSS "vfnmadd132pd", // X86_INS_VFNMADD132PD "vfnmadd132ps", // X86_INS_VFNMADD132PS "vfnmadd132sd", // X86_INS_VFNMADD132SD "vfnmadd132ss", // X86_INS_VFNMADD132SS "vfnmadd213pd", // X86_INS_VFNMADD213PD "vfnmadd213ps", // X86_INS_VFNMADD213PS "vfnmadd213sd", // X86_INS_VFNMADD213SD "vfnmadd213ss", // X86_INS_VFNMADD213SS "vfnmadd231pd", // X86_INS_VFNMADD231PD "vfnmadd231ps", // X86_INS_VFNMADD231PS "vfnmadd231sd", // X86_INS_VFNMADD231SD "vfnmadd231ss", // X86_INS_VFNMADD231SS "vfnmaddpd", // X86_INS_VFNMADDPD "vfnmaddps", // X86_INS_VFNMADDPS "vfnmaddsd", // X86_INS_VFNMADDSD "vfnmaddss", // X86_INS_VFNMADDSS "vfnmsub132pd", // X86_INS_VFNMSUB132PD "vfnmsub132ps", // X86_INS_VFNMSUB132PS "vfnmsub132sd", // X86_INS_VFNMSUB132SD "vfnmsub132ss", // X86_INS_VFNMSUB132SS "vfnmsub213pd", // X86_INS_VFNMSUB213PD "vfnmsub213ps", // X86_INS_VFNMSUB213PS "vfnmsub213sd", // X86_INS_VFNMSUB213SD "vfnmsub213ss", // X86_INS_VFNMSUB213SS "vfnmsub231pd", // X86_INS_VFNMSUB231PD "vfnmsub231ps", // X86_INS_VFNMSUB231PS "vfnmsub231sd", // X86_INS_VFNMSUB231SD "vfnmsub231ss", // X86_INS_VFNMSUB231SS "vfnmsubpd", // X86_INS_VFNMSUBPD "vfnmsubps", // X86_INS_VFNMSUBPS "vfnmsubsd", // X86_INS_VFNMSUBSD "vfnmsubss", // X86_INS_VFNMSUBSS "vfpclasspd", // X86_INS_VFPCLASSPD "vfpclassps", // X86_INS_VFPCLASSPS "vfpclasssd", // X86_INS_VFPCLASSSD "vfpclassss", // X86_INS_VFPCLASSSS "vfrczpd", // X86_INS_VFRCZPD "vfrczps", // X86_INS_VFRCZPS "vfrczsd", // X86_INS_VFRCZSD "vfrczss", // X86_INS_VFRCZSS "vgatherdpd", // X86_INS_VGATHERDPD "vgatherdps", // X86_INS_VGATHERDPS "vgatherpf0dpd", // X86_INS_VGATHERPF0DPD "vgatherpf0dps", // X86_INS_VGATHERPF0DPS "vgatherpf0qpd", // X86_INS_VGATHERPF0QPD "vgatherpf0qps", // X86_INS_VGATHERPF0QPS "vgatherpf1dpd", // X86_INS_VGATHERPF1DPD "vgatherpf1dps", // X86_INS_VGATHERPF1DPS "vgatherpf1qpd", // X86_INS_VGATHERPF1QPD "vgatherpf1qps", // X86_INS_VGATHERPF1QPS "vgatherqpd", // X86_INS_VGATHERQPD "vgatherqps", // X86_INS_VGATHERQPS "vgetexppd", // X86_INS_VGETEXPPD "vgetexpps", // X86_INS_VGETEXPPS "vgetexpsd", // X86_INS_VGETEXPSD "vgetexpss", // X86_INS_VGETEXPSS "vgetmantpd", // X86_INS_VGETMANTPD "vgetmantps", // X86_INS_VGETMANTPS "vgetmantsd", // X86_INS_VGETMANTSD "vgetmantss", // X86_INS_VGETMANTSS "vgf2p8affineinvqb", // X86_INS_VGF2P8AFFINEINVQB "vgf2p8affineqb", // X86_INS_VGF2P8AFFINEQB "vgf2p8mulb", // X86_INS_VGF2P8MULB "vhaddpd", // X86_INS_VHADDPD "vhaddps", // X86_INS_VHADDPS "vhsubpd", // X86_INS_VHSUBPD "vhsubps", // X86_INS_VHSUBPS "vinsertf128", // X86_INS_VINSERTF128 "vinsertf32x4", // X86_INS_VINSERTF32X4 "vinsertf32x8", // X86_INS_VINSERTF32X8 "vinsertf64x2", // X86_INS_VINSERTF64X2 "vinsertf64x4", // X86_INS_VINSERTF64X4 "vinserti128", // X86_INS_VINSERTI128 "vinserti32x4", // X86_INS_VINSERTI32X4 "vinserti32x8", // X86_INS_VINSERTI32X8 "vinserti64x2", // X86_INS_VINSERTI64X2 "vinserti64x4", // X86_INS_VINSERTI64X4 "vinsertps", // X86_INS_VINSERTPS "vlddqu", // X86_INS_VLDDQU "vldmxcsr", // X86_INS_VLDMXCSR "vmaskmovdqu", // X86_INS_VMASKMOVDQU "vmaskmovpd", // X86_INS_VMASKMOVPD "vmaskmovps", // X86_INS_VMASKMOVPS "vmaxpd", // X86_INS_VMAXPD "vmaxps", // X86_INS_VMAXPS "vmaxsd", // X86_INS_VMAXSD "vmaxss", // X86_INS_VMAXSS "vmcall", // X86_INS_VMCALL "vmclear", // X86_INS_VMCLEAR "vmfunc", // X86_INS_VMFUNC "vminpd", // X86_INS_VMINPD "vminps", // X86_INS_VMINPS "vminsd", // X86_INS_VMINSD "vminss", // X86_INS_VMINSS "vmlaunch", // X86_INS_VMLAUNCH "vmload", // X86_INS_VMLOAD "vmmcall", // X86_INS_VMMCALL "vmovq", // X86_INS_VMOVQ "vmovapd", // X86_INS_VMOVAPD "vmovaps", // X86_INS_VMOVAPS "vmovddup", // X86_INS_VMOVDDUP "vmovd", // X86_INS_VMOVD "vmovdqa32", // X86_INS_VMOVDQA32 "vmovdqa64", // X86_INS_VMOVDQA64 "vmovdqa", // X86_INS_VMOVDQA "vmovdqu16", // X86_INS_VMOVDQU16 "vmovdqu32", // X86_INS_VMOVDQU32 "vmovdqu64", // X86_INS_VMOVDQU64 "vmovdqu8", // X86_INS_VMOVDQU8 "vmovdqu", // X86_INS_VMOVDQU "vmovhlps", // X86_INS_VMOVHLPS "vmovhpd", // X86_INS_VMOVHPD "vmovhps", // X86_INS_VMOVHPS "vmovlhps", // X86_INS_VMOVLHPS "vmovlpd", // X86_INS_VMOVLPD "vmovlps", // X86_INS_VMOVLPS "vmovmskpd", // X86_INS_VMOVMSKPD "vmovmskps", // X86_INS_VMOVMSKPS "vmovntdqa", // X86_INS_VMOVNTDQA "vmovntdq", // X86_INS_VMOVNTDQ "vmovntpd", // X86_INS_VMOVNTPD "vmovntps", // X86_INS_VMOVNTPS "vmovsd", // X86_INS_VMOVSD "vmovshdup", // X86_INS_VMOVSHDUP "vmovsldup", // X86_INS_VMOVSLDUP "vmovss", // X86_INS_VMOVSS "vmovupd", // X86_INS_VMOVUPD "vmovups", // X86_INS_VMOVUPS "vmpsadbw", // X86_INS_VMPSADBW "vmptrld", // X86_INS_VMPTRLD "vmptrst", // X86_INS_VMPTRST "vmread", // X86_INS_VMREAD "vmresume", // X86_INS_VMRESUME "vmrun", // X86_INS_VMRUN "vmsave", // X86_INS_VMSAVE "vmulpd", // X86_INS_VMULPD "vmulps", // X86_INS_VMULPS "vmulsd", // X86_INS_VMULSD "vmulss", // X86_INS_VMULSS "vmwrite", // X86_INS_VMWRITE "vmxoff", // X86_INS_VMXOFF "vmxon", // X86_INS_VMXON "vorpd", // X86_INS_VORPD "vorps", // X86_INS_VORPS "vp4dpwssds", // X86_INS_VP4DPWSSDS "vp4dpwssd", // X86_INS_VP4DPWSSD "vpabsb", // X86_INS_VPABSB "vpabsd", // X86_INS_VPABSD "vpabsq", // X86_INS_VPABSQ "vpabsw", // X86_INS_VPABSW "vpackssdw", // X86_INS_VPACKSSDW "vpacksswb", // X86_INS_VPACKSSWB "vpackusdw", // X86_INS_VPACKUSDW "vpackuswb", // X86_INS_VPACKUSWB "vpaddb", // X86_INS_VPADDB "vpaddd", // X86_INS_VPADDD "vpaddq", // X86_INS_VPADDQ "vpaddsb", // X86_INS_VPADDSB "vpaddsw", // X86_INS_VPADDSW "vpaddusb", // X86_INS_VPADDUSB "vpaddusw", // X86_INS_VPADDUSW "vpaddw", // X86_INS_VPADDW "vpalignr", // X86_INS_VPALIGNR "vpandd", // X86_INS_VPANDD "vpandnd", // X86_INS_VPANDND "vpandnq", // X86_INS_VPANDNQ "vpandn", // X86_INS_VPANDN "vpandq", // X86_INS_VPANDQ "vpand", // X86_INS_VPAND "vpavgb", // X86_INS_VPAVGB "vpavgw", // X86_INS_VPAVGW "vpblendd", // X86_INS_VPBLENDD "vpblendmb", // X86_INS_VPBLENDMB "vpblendmd", // X86_INS_VPBLENDMD "vpblendmq", // X86_INS_VPBLENDMQ "vpblendmw", // X86_INS_VPBLENDMW "vpblendvb", // X86_INS_VPBLENDVB "vpblendw", // X86_INS_VPBLENDW "vpbroadcastb", // X86_INS_VPBROADCASTB "vpbroadcastd", // X86_INS_VPBROADCASTD "vpbroadcastmb2q", // X86_INS_VPBROADCASTMB2Q "vpbroadcastmw2d", // X86_INS_VPBROADCASTMW2D "vpbroadcastq", // X86_INS_VPBROADCASTQ "vpbroadcastw", // X86_INS_VPBROADCASTW "vpclmulqdq", // X86_INS_VPCLMULQDQ "vpcmov", // X86_INS_VPCMOV "vpcmp", // X86_INS_VPCMP "vpcmpb", // X86_INS_VPCMPB "vpcmpd", // X86_INS_VPCMPD "vpcmpeqb", // X86_INS_VPCMPEQB "vpcmpeqd", // X86_INS_VPCMPEQD "vpcmpeqq", // X86_INS_VPCMPEQQ "vpcmpeqw", // X86_INS_VPCMPEQW "vpcmpestri", // X86_INS_VPCMPESTRI "vpcmpestrm", // X86_INS_VPCMPESTRM "vpcmpgtb", // X86_INS_VPCMPGTB "vpcmpgtd", // X86_INS_VPCMPGTD "vpcmpgtq", // X86_INS_VPCMPGTQ "vpcmpgtw", // X86_INS_VPCMPGTW "vpcmpistri", // X86_INS_VPCMPISTRI "vpcmpistrm", // X86_INS_VPCMPISTRM "vpcmpq", // X86_INS_VPCMPQ "vpcmpub", // X86_INS_VPCMPUB "vpcmpud", // X86_INS_VPCMPUD "vpcmpuq", // X86_INS_VPCMPUQ "vpcmpuw", // X86_INS_VPCMPUW "vpcmpw", // X86_INS_VPCMPW "vpcom", // X86_INS_VPCOM "vpcomb", // X86_INS_VPCOMB "vpcomd", // X86_INS_VPCOMD "vpcompressb", // X86_INS_VPCOMPRESSB "vpcompressd", // X86_INS_VPCOMPRESSD "vpcompressq", // X86_INS_VPCOMPRESSQ "vpcompressw", // X86_INS_VPCOMPRESSW "vpcomq", // X86_INS_VPCOMQ "vpcomub", // X86_INS_VPCOMUB "vpcomud", // X86_INS_VPCOMUD "vpcomuq", // X86_INS_VPCOMUQ "vpcomuw", // X86_INS_VPCOMUW "vpcomw", // X86_INS_VPCOMW "vpconflictd", // X86_INS_VPCONFLICTD "vpconflictq", // X86_INS_VPCONFLICTQ "vpdpbusds", // X86_INS_VPDPBUSDS "vpdpbusd", // X86_INS_VPDPBUSD "vpdpwssds", // X86_INS_VPDPWSSDS "vpdpwssd", // X86_INS_VPDPWSSD "vperm2f128", // X86_INS_VPERM2F128 "vperm2i128", // X86_INS_VPERM2I128 "vpermb", // X86_INS_VPERMB "vpermd", // X86_INS_VPERMD "vpermi2b", // X86_INS_VPERMI2B "vpermi2d", // X86_INS_VPERMI2D "vpermi2pd", // X86_INS_VPERMI2PD "vpermi2ps", // X86_INS_VPERMI2PS "vpermi2q", // X86_INS_VPERMI2Q "vpermi2w", // X86_INS_VPERMI2W "vpermil2pd", // X86_INS_VPERMIL2PD "vpermilpd", // X86_INS_VPERMILPD "vpermil2ps", // X86_INS_VPERMIL2PS "vpermilps", // X86_INS_VPERMILPS "vpermpd", // X86_INS_VPERMPD "vpermps", // X86_INS_VPERMPS "vpermq", // X86_INS_VPERMQ "vpermt2b", // X86_INS_VPERMT2B "vpermt2d", // X86_INS_VPERMT2D "vpermt2pd", // X86_INS_VPERMT2PD "vpermt2ps", // X86_INS_VPERMT2PS "vpermt2q", // X86_INS_VPERMT2Q "vpermt2w", // X86_INS_VPERMT2W "vpermw", // X86_INS_VPERMW "vpexpandb", // X86_INS_VPEXPANDB "vpexpandd", // X86_INS_VPEXPANDD "vpexpandq", // X86_INS_VPEXPANDQ "vpexpandw", // X86_INS_VPEXPANDW "vpextrb", // X86_INS_VPEXTRB "vpextrd", // X86_INS_VPEXTRD "vpextrq", // X86_INS_VPEXTRQ "vpextrw", // X86_INS_VPEXTRW "vpgatherdd", // X86_INS_VPGATHERDD "vpgatherdq", // X86_INS_VPGATHERDQ "vpgatherqd", // X86_INS_VPGATHERQD "vpgatherqq", // X86_INS_VPGATHERQQ "vphaddbd", // X86_INS_VPHADDBD "vphaddbq", // X86_INS_VPHADDBQ "vphaddbw", // X86_INS_VPHADDBW "vphadddq", // X86_INS_VPHADDDQ "vphaddd", // X86_INS_VPHADDD "vphaddsw", // X86_INS_VPHADDSW "vphaddubd", // X86_INS_VPHADDUBD "vphaddubq", // X86_INS_VPHADDUBQ "vphaddubw", // X86_INS_VPHADDUBW "vphaddudq", // X86_INS_VPHADDUDQ "vphadduwd", // X86_INS_VPHADDUWD "vphadduwq", // X86_INS_VPHADDUWQ "vphaddwd", // X86_INS_VPHADDWD "vphaddwq", // X86_INS_VPHADDWQ "vphaddw", // X86_INS_VPHADDW "vphminposuw", // X86_INS_VPHMINPOSUW "vphsubbw", // X86_INS_VPHSUBBW "vphsubdq", // X86_INS_VPHSUBDQ "vphsubd", // X86_INS_VPHSUBD "vphsubsw", // X86_INS_VPHSUBSW "vphsubwd", // X86_INS_VPHSUBWD "vphsubw", // X86_INS_VPHSUBW "vpinsrb", // X86_INS_VPINSRB "vpinsrd", // X86_INS_VPINSRD "vpinsrq", // X86_INS_VPINSRQ "vpinsrw", // X86_INS_VPINSRW "vplzcntd", // X86_INS_VPLZCNTD "vplzcntq", // X86_INS_VPLZCNTQ "vpmacsdd", // X86_INS_VPMACSDD "vpmacsdqh", // X86_INS_VPMACSDQH "vpmacsdql", // X86_INS_VPMACSDQL "vpmacssdd", // X86_INS_VPMACSSDD "vpmacssdqh", // X86_INS_VPMACSSDQH "vpmacssdql", // X86_INS_VPMACSSDQL "vpmacsswd", // X86_INS_VPMACSSWD "vpmacssww", // X86_INS_VPMACSSWW "vpmacswd", // X86_INS_VPMACSWD "vpmacsww", // X86_INS_VPMACSWW "vpmadcsswd", // X86_INS_VPMADCSSWD "vpmadcswd", // X86_INS_VPMADCSWD "vpmadd52huq", // X86_INS_VPMADD52HUQ "vpmadd52luq", // X86_INS_VPMADD52LUQ "vpmaddubsw", // X86_INS_VPMADDUBSW "vpmaddwd", // X86_INS_VPMADDWD "vpmaskmovd", // X86_INS_VPMASKMOVD "vpmaskmovq", // X86_INS_VPMASKMOVQ "vpmaxsb", // X86_INS_VPMAXSB "vpmaxsd", // X86_INS_VPMAXSD "vpmaxsq", // X86_INS_VPMAXSQ "vpmaxsw", // X86_INS_VPMAXSW "vpmaxub", // X86_INS_VPMAXUB "vpmaxud", // X86_INS_VPMAXUD "vpmaxuq", // X86_INS_VPMAXUQ "vpmaxuw", // X86_INS_VPMAXUW "vpminsb", // X86_INS_VPMINSB "vpminsd", // X86_INS_VPMINSD "vpminsq", // X86_INS_VPMINSQ "vpminsw", // X86_INS_VPMINSW "vpminub", // X86_INS_VPMINUB "vpminud", // X86_INS_VPMINUD "vpminuq", // X86_INS_VPMINUQ "vpminuw", // X86_INS_VPMINUW "vpmovb2m", // X86_INS_VPMOVB2M "vpmovd2m", // X86_INS_VPMOVD2M "vpmovdb", // X86_INS_VPMOVDB "vpmovdw", // X86_INS_VPMOVDW "vpmovm2b", // X86_INS_VPMOVM2B "vpmovm2d", // X86_INS_VPMOVM2D "vpmovm2q", // X86_INS_VPMOVM2Q "vpmovm2w", // X86_INS_VPMOVM2W "vpmovmskb", // X86_INS_VPMOVMSKB "vpmovq2m", // X86_INS_VPMOVQ2M "vpmovqb", // X86_INS_VPMOVQB "vpmovqd", // X86_INS_VPMOVQD "vpmovqw", // X86_INS_VPMOVQW "vpmovsdb", // X86_INS_VPMOVSDB "vpmovsdw", // X86_INS_VPMOVSDW "vpmovsqb", // X86_INS_VPMOVSQB "vpmovsqd", // X86_INS_VPMOVSQD "vpmovsqw", // X86_INS_VPMOVSQW "vpmovswb", // X86_INS_VPMOVSWB "vpmovsxbd", // X86_INS_VPMOVSXBD "vpmovsxbq", // X86_INS_VPMOVSXBQ "vpmovsxbw", // X86_INS_VPMOVSXBW "vpmovsxdq", // X86_INS_VPMOVSXDQ "vpmovsxwd", // X86_INS_VPMOVSXWD "vpmovsxwq", // X86_INS_VPMOVSXWQ "vpmovusdb", // X86_INS_VPMOVUSDB "vpmovusdw", // X86_INS_VPMOVUSDW "vpmovusqb", // X86_INS_VPMOVUSQB "vpmovusqd", // X86_INS_VPMOVUSQD "vpmovusqw", // X86_INS_VPMOVUSQW "vpmovuswb", // X86_INS_VPMOVUSWB "vpmovw2m", // X86_INS_VPMOVW2M "vpmovwb", // X86_INS_VPMOVWB "vpmovzxbd", // X86_INS_VPMOVZXBD "vpmovzxbq", // X86_INS_VPMOVZXBQ "vpmovzxbw", // X86_INS_VPMOVZXBW "vpmovzxdq", // X86_INS_VPMOVZXDQ "vpmovzxwd", // X86_INS_VPMOVZXWD "vpmovzxwq", // X86_INS_VPMOVZXWQ "vpmuldq", // X86_INS_VPMULDQ "vpmulhrsw", // X86_INS_VPMULHRSW "vpmulhuw", // X86_INS_VPMULHUW "vpmulhw", // X86_INS_VPMULHW "vpmulld", // X86_INS_VPMULLD "vpmullq", // X86_INS_VPMULLQ "vpmullw", // X86_INS_VPMULLW "vpmultishiftqb", // X86_INS_VPMULTISHIFTQB "vpmuludq", // X86_INS_VPMULUDQ "vpopcntb", // X86_INS_VPOPCNTB "vpopcntd", // X86_INS_VPOPCNTD "vpopcntq", // X86_INS_VPOPCNTQ "vpopcntw", // X86_INS_VPOPCNTW "vpord", // X86_INS_VPORD "vporq", // X86_INS_VPORQ "vpor", // X86_INS_VPOR "vpperm", // X86_INS_VPPERM "vprold", // X86_INS_VPROLD "vprolq", // X86_INS_VPROLQ "vprolvd", // X86_INS_VPROLVD "vprolvq", // X86_INS_VPROLVQ "vprord", // X86_INS_VPRORD "vprorq", // X86_INS_VPRORQ "vprorvd", // X86_INS_VPRORVD "vprorvq", // X86_INS_VPRORVQ "vprotb", // X86_INS_VPROTB "vprotd", // X86_INS_VPROTD "vprotq", // X86_INS_VPROTQ "vprotw", // X86_INS_VPROTW "vpsadbw", // X86_INS_VPSADBW "vpscatterdd", // X86_INS_VPSCATTERDD "vpscatterdq", // X86_INS_VPSCATTERDQ "vpscatterqd", // X86_INS_VPSCATTERQD "vpscatterqq", // X86_INS_VPSCATTERQQ "vpshab", // X86_INS_VPSHAB "vpshad", // X86_INS_VPSHAD "vpshaq", // X86_INS_VPSHAQ "vpshaw", // X86_INS_VPSHAW "vpshlb", // X86_INS_VPSHLB "vpshldd", // X86_INS_VPSHLDD "vpshldq", // X86_INS_VPSHLDQ "vpshldvd", // X86_INS_VPSHLDVD "vpshldvq", // X86_INS_VPSHLDVQ "vpshldvw", // X86_INS_VPSHLDVW "vpshldw", // X86_INS_VPSHLDW "vpshld", // X86_INS_VPSHLD "vpshlq", // X86_INS_VPSHLQ "vpshlw", // X86_INS_VPSHLW "vpshrdd", // X86_INS_VPSHRDD "vpshrdq", // X86_INS_VPSHRDQ "vpshrdvd", // X86_INS_VPSHRDVD "vpshrdvq", // X86_INS_VPSHRDVQ "vpshrdvw", // X86_INS_VPSHRDVW "vpshrdw", // X86_INS_VPSHRDW "vpshufbitqmb", // X86_INS_VPSHUFBITQMB "vpshufb", // X86_INS_VPSHUFB "vpshufd", // X86_INS_VPSHUFD "vpshufhw", // X86_INS_VPSHUFHW "vpshuflw", // X86_INS_VPSHUFLW "vpsignb", // X86_INS_VPSIGNB "vpsignd", // X86_INS_VPSIGND "vpsignw", // X86_INS_VPSIGNW "vpslldq", // X86_INS_VPSLLDQ "vpslld", // X86_INS_VPSLLD "vpsllq", // X86_INS_VPSLLQ "vpsllvd", // X86_INS_VPSLLVD "vpsllvq", // X86_INS_VPSLLVQ "vpsllvw", // X86_INS_VPSLLVW "vpsllw", // X86_INS_VPSLLW "vpsrad", // X86_INS_VPSRAD "vpsraq", // X86_INS_VPSRAQ "vpsravd", // X86_INS_VPSRAVD "vpsravq", // X86_INS_VPSRAVQ "vpsravw", // X86_INS_VPSRAVW "vpsraw", // X86_INS_VPSRAW "vpsrldq", // X86_INS_VPSRLDQ "vpsrld", // X86_INS_VPSRLD "vpsrlq", // X86_INS_VPSRLQ "vpsrlvd", // X86_INS_VPSRLVD "vpsrlvq", // X86_INS_VPSRLVQ "vpsrlvw", // X86_INS_VPSRLVW "vpsrlw", // X86_INS_VPSRLW "vpsubb", // X86_INS_VPSUBB "vpsubd", // X86_INS_VPSUBD "vpsubq", // X86_INS_VPSUBQ "vpsubsb", // X86_INS_VPSUBSB "vpsubsw", // X86_INS_VPSUBSW "vpsubusb", // X86_INS_VPSUBUSB "vpsubusw", // X86_INS_VPSUBUSW "vpsubw", // X86_INS_VPSUBW "vpternlogd", // X86_INS_VPTERNLOGD "vpternlogq", // X86_INS_VPTERNLOGQ "vptestmb", // X86_INS_VPTESTMB "vptestmd", // X86_INS_VPTESTMD "vptestmq", // X86_INS_VPTESTMQ "vptestmw", // X86_INS_VPTESTMW "vptestnmb", // X86_INS_VPTESTNMB "vptestnmd", // X86_INS_VPTESTNMD "vptestnmq", // X86_INS_VPTESTNMQ "vptestnmw", // X86_INS_VPTESTNMW "vptest", // X86_INS_VPTEST "vpunpckhbw", // X86_INS_VPUNPCKHBW "vpunpckhdq", // X86_INS_VPUNPCKHDQ "vpunpckhqdq", // X86_INS_VPUNPCKHQDQ "vpunpckhwd", // X86_INS_VPUNPCKHWD "vpunpcklbw", // X86_INS_VPUNPCKLBW "vpunpckldq", // X86_INS_VPUNPCKLDQ "vpunpcklqdq", // X86_INS_VPUNPCKLQDQ "vpunpcklwd", // X86_INS_VPUNPCKLWD "vpxord", // X86_INS_VPXORD "vpxorq", // X86_INS_VPXORQ "vpxor", // X86_INS_VPXOR "vrangepd", // X86_INS_VRANGEPD "vrangeps", // X86_INS_VRANGEPS "vrangesd", // X86_INS_VRANGESD "vrangess", // X86_INS_VRANGESS "vrcp14pd", // X86_INS_VRCP14PD "vrcp14ps", // X86_INS_VRCP14PS "vrcp14sd", // X86_INS_VRCP14SD "vrcp14ss", // X86_INS_VRCP14SS "vrcp28pd", // X86_INS_VRCP28PD "vrcp28ps", // X86_INS_VRCP28PS "vrcp28sd", // X86_INS_VRCP28SD "vrcp28ss", // X86_INS_VRCP28SS "vrcpps", // X86_INS_VRCPPS "vrcpss", // X86_INS_VRCPSS "vreducepd", // X86_INS_VREDUCEPD "vreduceps", // X86_INS_VREDUCEPS "vreducesd", // X86_INS_VREDUCESD "vreducess", // X86_INS_VREDUCESS "vrndscalepd", // X86_INS_VRNDSCALEPD "vrndscaleps", // X86_INS_VRNDSCALEPS "vrndscalesd", // X86_INS_VRNDSCALESD "vrndscaless", // X86_INS_VRNDSCALESS "vroundpd", // X86_INS_VROUNDPD "vroundps", // X86_INS_VROUNDPS "vroundsd", // X86_INS_VROUNDSD "vroundss", // X86_INS_VROUNDSS "vrsqrt14pd", // X86_INS_VRSQRT14PD "vrsqrt14ps", // X86_INS_VRSQRT14PS "vrsqrt14sd", // X86_INS_VRSQRT14SD "vrsqrt14ss", // X86_INS_VRSQRT14SS "vrsqrt28pd", // X86_INS_VRSQRT28PD "vrsqrt28ps", // X86_INS_VRSQRT28PS "vrsqrt28sd", // X86_INS_VRSQRT28SD "vrsqrt28ss", // X86_INS_VRSQRT28SS "vrsqrtps", // X86_INS_VRSQRTPS "vrsqrtss", // X86_INS_VRSQRTSS "vscalefpd", // X86_INS_VSCALEFPD "vscalefps", // X86_INS_VSCALEFPS "vscalefsd", // X86_INS_VSCALEFSD "vscalefss", // X86_INS_VSCALEFSS "vscatterdpd", // X86_INS_VSCATTERDPD "vscatterdps", // X86_INS_VSCATTERDPS "vscatterpf0dpd", // X86_INS_VSCATTERPF0DPD "vscatterpf0dps", // X86_INS_VSCATTERPF0DPS "vscatterpf0qpd", // X86_INS_VSCATTERPF0QPD "vscatterpf0qps", // X86_INS_VSCATTERPF0QPS "vscatterpf1dpd", // X86_INS_VSCATTERPF1DPD "vscatterpf1dps", // X86_INS_VSCATTERPF1DPS "vscatterpf1qpd", // X86_INS_VSCATTERPF1QPD "vscatterpf1qps", // X86_INS_VSCATTERPF1QPS "vscatterqpd", // X86_INS_VSCATTERQPD "vscatterqps", // X86_INS_VSCATTERQPS "vshuff32x4", // X86_INS_VSHUFF32X4 "vshuff64x2", // X86_INS_VSHUFF64X2 "vshufi32x4", // X86_INS_VSHUFI32X4 "vshufi64x2", // X86_INS_VSHUFI64X2 "vshufpd", // X86_INS_VSHUFPD "vshufps", // X86_INS_VSHUFPS "vsqrtpd", // X86_INS_VSQRTPD "vsqrtps", // X86_INS_VSQRTPS "vsqrtsd", // X86_INS_VSQRTSD "vsqrtss", // X86_INS_VSQRTSS "vstmxcsr", // X86_INS_VSTMXCSR "vsubpd", // X86_INS_VSUBPD "vsubps", // X86_INS_VSUBPS "vsubsd", // X86_INS_VSUBSD "vsubss", // X86_INS_VSUBSS "vtestpd", // X86_INS_VTESTPD "vtestps", // X86_INS_VTESTPS "vucomisd", // X86_INS_VUCOMISD "vucomiss", // X86_INS_VUCOMISS "vunpckhpd", // X86_INS_VUNPCKHPD "vunpckhps", // X86_INS_VUNPCKHPS "vunpcklpd", // X86_INS_VUNPCKLPD "vunpcklps", // X86_INS_VUNPCKLPS "vxorpd", // X86_INS_VXORPD "vxorps", // X86_INS_VXORPS "vzeroall", // X86_INS_VZEROALL "vzeroupper", // X86_INS_VZEROUPPER "wait", // X86_INS_WAIT "wbinvd", // X86_INS_WBINVD "wbnoinvd", // X86_INS_WBNOINVD "wrfsbase", // X86_INS_WRFSBASE "wrgsbase", // X86_INS_WRGSBASE "wrmsr", // X86_INS_WRMSR "wrpkru", // X86_INS_WRPKRU "wrssd", // X86_INS_WRSSD "wrssq", // X86_INS_WRSSQ "wrussd", // X86_INS_WRUSSD "wrussq", // X86_INS_WRUSSQ "xabort", // X86_INS_XABORT "xacquire", // X86_INS_XACQUIRE "xadd", // X86_INS_XADD "xbegin", // X86_INS_XBEGIN "xchg", // X86_INS_XCHG "fxch", // X86_INS_FXCH "xcryptcbc", // X86_INS_XCRYPTCBC "xcryptcfb", // X86_INS_XCRYPTCFB "xcryptctr", // X86_INS_XCRYPTCTR "xcryptecb", // X86_INS_XCRYPTECB "xcryptofb", // X86_INS_XCRYPTOFB "xend", // X86_INS_XEND "xgetbv", // X86_INS_XGETBV "xlatb", // X86_INS_XLATB "xor", // X86_INS_XOR "xorpd", // X86_INS_XORPD "xorps", // X86_INS_XORPS "xrelease", // X86_INS_XRELEASE "xrstor", // X86_INS_XRSTOR "xrstor64", // X86_INS_XRSTOR64 "xrstors", // X86_INS_XRSTORS "xrstors64", // X86_INS_XRSTORS64 "xsave", // X86_INS_XSAVE "xsave64", // X86_INS_XSAVE64 "xsavec", // X86_INS_XSAVEC "xsavec64", // X86_INS_XSAVEC64 "xsaveopt", // X86_INS_XSAVEOPT "xsaveopt64", // X86_INS_XSAVEOPT64 "xsaves", // X86_INS_XSAVES "xsaves64", // X86_INS_XSAVES64 "xsetbv", // X86_INS_XSETBV "xsha1", // X86_INS_XSHA1 "xsha256", // X86_INS_XSHA256 "xstore", // X86_INS_XSTORE "xtest", // X86_INS_XTEST capstone-sys-0.15.0/capstone/arch/X86/X86MappingInsnName_reduce.inc000064400000000000000000000223270072674642500230670ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ "aaa", // X86_INS_AAA "aad", // X86_INS_AAD "aam", // X86_INS_AAM "aas", // X86_INS_AAS "adc", // X86_INS_ADC "adcx", // X86_INS_ADCX "add", // X86_INS_ADD "adox", // X86_INS_ADOX "and", // X86_INS_AND "andn", // X86_INS_ANDN "arpl", // X86_INS_ARPL "bextr", // X86_INS_BEXTR "blcfill", // X86_INS_BLCFILL "blci", // X86_INS_BLCI "blcic", // X86_INS_BLCIC "blcmsk", // X86_INS_BLCMSK "blcs", // X86_INS_BLCS "blsfill", // X86_INS_BLSFILL "blsi", // X86_INS_BLSI "blsic", // X86_INS_BLSIC "blsmsk", // X86_INS_BLSMSK "blsr", // X86_INS_BLSR "bound", // X86_INS_BOUND "bsf", // X86_INS_BSF "bsr", // X86_INS_BSR "bswap", // X86_INS_BSWAP "bt", // X86_INS_BT "btc", // X86_INS_BTC "btr", // X86_INS_BTR "bts", // X86_INS_BTS "bzhi", // X86_INS_BZHI "call", // X86_INS_CALL "cbw", // X86_INS_CBW "cdq", // X86_INS_CDQ "cdqe", // X86_INS_CDQE "clac", // X86_INS_CLAC "clc", // X86_INS_CLC "cld", // X86_INS_CLD "cldemote", // X86_INS_CLDEMOTE "clflushopt", // X86_INS_CLFLUSHOPT "clgi", // X86_INS_CLGI "cli", // X86_INS_CLI "clrssbsy", // X86_INS_CLRSSBSY "clts", // X86_INS_CLTS "clwb", // X86_INS_CLWB "clzero", // X86_INS_CLZERO "cmc", // X86_INS_CMC "cmova", // X86_INS_CMOVA "cmovae", // X86_INS_CMOVAE "cmovb", // X86_INS_CMOVB "cmovbe", // X86_INS_CMOVBE "cmove", // X86_INS_CMOVE "cmovg", // X86_INS_CMOVG "cmovge", // X86_INS_CMOVGE "cmovl", // X86_INS_CMOVL "cmovle", // X86_INS_CMOVLE "cmovne", // X86_INS_CMOVNE "cmovno", // X86_INS_CMOVNO "cmovnp", // X86_INS_CMOVNP "cmovns", // X86_INS_CMOVNS "cmovo", // X86_INS_CMOVO "cmovp", // X86_INS_CMOVP "cmovs", // X86_INS_CMOVS "cmp", // X86_INS_CMP "cmpsb", // X86_INS_CMPSB "cmpsd", // X86_INS_CMPSD "cmpsq", // X86_INS_CMPSQ "cmpsw", // X86_INS_CMPSW "cmpxchg16b", // X86_INS_CMPXCHG16B "cmpxchg", // X86_INS_CMPXCHG "cmpxchg8b", // X86_INS_CMPXCHG8B "cpuid", // X86_INS_CPUID "cqo", // X86_INS_CQO "cwd", // X86_INS_CWD "cwde", // X86_INS_CWDE "daa", // X86_INS_DAA "das", // X86_INS_DAS "data16", // X86_INS_DATA16 "dec", // X86_INS_DEC "div", // X86_INS_DIV "endbr32", // X86_INS_ENDBR32 "endbr64", // X86_INS_ENDBR64 "enter", // X86_INS_ENTER "lcall", // X86_INS_LCALL "ljmp", // X86_INS_LJMP "jmp", // X86_INS_JMP "fsetpm", // X86_INS_FSETPM "getsec", // X86_INS_GETSEC "hlt", // X86_INS_HLT "idiv", // X86_INS_IDIV "imul", // X86_INS_IMUL "in", // X86_INS_IN "inc", // X86_INS_INC "incsspd", // X86_INS_INCSSPD "incsspq", // X86_INS_INCSSPQ "insb", // X86_INS_INSB "insd", // X86_INS_INSD "insw", // X86_INS_INSW "int", // X86_INS_INT "int1", // X86_INS_INT1 "int3", // X86_INS_INT3 "into", // X86_INS_INTO "invd", // X86_INS_INVD "invept", // X86_INS_INVEPT "invlpg", // X86_INS_INVLPG "invlpga", // X86_INS_INVLPGA "invpcid", // X86_INS_INVPCID "invvpid", // X86_INS_INVVPID "iret", // X86_INS_IRET "iretd", // X86_INS_IRETD "iretq", // X86_INS_IRETQ "jae", // X86_INS_JAE "ja", // X86_INS_JA "jbe", // X86_INS_JBE "jb", // X86_INS_JB "jcxz", // X86_INS_JCXZ "jecxz", // X86_INS_JECXZ "je", // X86_INS_JE "jge", // X86_INS_JGE "jg", // X86_INS_JG "jle", // X86_INS_JLE "jl", // X86_INS_JL "jne", // X86_INS_JNE "jno", // X86_INS_JNO "jnp", // X86_INS_JNP "jns", // X86_INS_JNS "jo", // X86_INS_JO "jp", // X86_INS_JP "jrcxz", // X86_INS_JRCXZ "js", // X86_INS_JS "lahf", // X86_INS_LAHF "lar", // X86_INS_LAR "lds", // X86_INS_LDS "lea", // X86_INS_LEA "leave", // X86_INS_LEAVE "les", // X86_INS_LES "lfs", // X86_INS_LFS "lgdt", // X86_INS_LGDT "lgs", // X86_INS_LGS "lidt", // X86_INS_LIDT "lldt", // X86_INS_LLDT "llwpcb", // X86_INS_LLWPCB "lmsw", // X86_INS_LMSW "lock", // X86_INS_LOCK "lodsb", // X86_INS_LODSB "lodsd", // X86_INS_LODSD "lodsq", // X86_INS_LODSQ "lodsw", // X86_INS_LODSW "loop", // X86_INS_LOOP "loope", // X86_INS_LOOPE "loopne", // X86_INS_LOOPNE "retf", // X86_INS_RETF "retfq", // X86_INS_RETFQ "lsl", // X86_INS_LSL "lss", // X86_INS_LSS "ltr", // X86_INS_LTR "lwpins", // X86_INS_LWPINS "lwpval", // X86_INS_LWPVAL "lzcnt", // X86_INS_LZCNT "monitorx", // X86_INS_MONITORX "montmul", // X86_INS_MONTMUL "mov", // X86_INS_MOV "movabs", // X86_INS_MOVABS "movbe", // X86_INS_MOVBE "movdir64b", // X86_INS_MOVDIR64B "movdiri", // X86_INS_MOVDIRI "movsb", // X86_INS_MOVSB "movsd", // X86_INS_MOVSD "movsq", // X86_INS_MOVSQ "movsw", // X86_INS_MOVSW "movsx", // X86_INS_MOVSX "movsxd", // X86_INS_MOVSXD "movzx", // X86_INS_MOVZX "mul", // X86_INS_MUL "mulx", // X86_INS_MULX "mwaitx", // X86_INS_MWAITX "neg", // X86_INS_NEG "nop", // X86_INS_NOP "not", // X86_INS_NOT "or", // X86_INS_OR "out", // X86_INS_OUT "outsb", // X86_INS_OUTSB "outsd", // X86_INS_OUTSD "outsw", // X86_INS_OUTSW "pconfig", // X86_INS_PCONFIG "pdep", // X86_INS_PDEP "pext", // X86_INS_PEXT "pop", // X86_INS_POP "popaw", // X86_INS_POPAW "popal", // X86_INS_POPAL "popf", // X86_INS_POPF "popfd", // X86_INS_POPFD "popfq", // X86_INS_POPFQ "ptwrite", // X86_INS_PTWRITE "push", // X86_INS_PUSH "pushaw", // X86_INS_PUSHAW "pushal", // X86_INS_PUSHAL "pushf", // X86_INS_PUSHF "pushfd", // X86_INS_PUSHFD "pushfq", // X86_INS_PUSHFQ "rcl", // X86_INS_RCL "rcr", // X86_INS_RCR "rdfsbase", // X86_INS_RDFSBASE "rdgsbase", // X86_INS_RDGSBASE "rdmsr", // X86_INS_RDMSR "rdpid", // X86_INS_RDPID "rdpkru", // X86_INS_RDPKRU "rdpmc", // X86_INS_RDPMC "rdrand", // X86_INS_RDRAND "rdseed", // X86_INS_RDSEED "rdsspd", // X86_INS_RDSSPD "rdsspq", // X86_INS_RDSSPQ "rdtsc", // X86_INS_RDTSC "rdtscp", // X86_INS_RDTSCP "repne", // X86_INS_REPNE "rep", // X86_INS_REP "ret", // X86_INS_RET "rex64", // X86_INS_REX64 "rol", // X86_INS_ROL "ror", // X86_INS_ROR "rorx", // X86_INS_RORX "rsm", // X86_INS_RSM "rstorssp", // X86_INS_RSTORSSP "sahf", // X86_INS_SAHF "sal", // X86_INS_SAL "salc", // X86_INS_SALC "sar", // X86_INS_SAR "sarx", // X86_INS_SARX "saveprevssp", // X86_INS_SAVEPREVSSP "sbb", // X86_INS_SBB "scasb", // X86_INS_SCASB "scasd", // X86_INS_SCASD "scasq", // X86_INS_SCASQ "scasw", // X86_INS_SCASW "setae", // X86_INS_SETAE "seta", // X86_INS_SETA "setbe", // X86_INS_SETBE "setb", // X86_INS_SETB "sete", // X86_INS_SETE "setge", // X86_INS_SETGE "setg", // X86_INS_SETG "setle", // X86_INS_SETLE "setl", // X86_INS_SETL "setne", // X86_INS_SETNE "setno", // X86_INS_SETNO "setnp", // X86_INS_SETNP "setns", // X86_INS_SETNS "seto", // X86_INS_SETO "setp", // X86_INS_SETP "setssbsy", // X86_INS_SETSSBSY "sets", // X86_INS_SETS "sgdt", // X86_INS_SGDT "shl", // X86_INS_SHL "shld", // X86_INS_SHLD "shlx", // X86_INS_SHLX "shr", // X86_INS_SHR "shrd", // X86_INS_SHRD "shrx", // X86_INS_SHRX "sidt", // X86_INS_SIDT "skinit", // X86_INS_SKINIT "sldt", // X86_INS_SLDT "slwpcb", // X86_INS_SLWPCB "smsw", // X86_INS_SMSW "stac", // X86_INS_STAC "stc", // X86_INS_STC "std", // X86_INS_STD "stgi", // X86_INS_STGI "sti", // X86_INS_STI "stosb", // X86_INS_STOSB "stosd", // X86_INS_STOSD "stosq", // X86_INS_STOSQ "stosw", // X86_INS_STOSW "str", // X86_INS_STR "sub", // X86_INS_SUB "swapgs", // X86_INS_SWAPGS "syscall", // X86_INS_SYSCALL "sysenter", // X86_INS_SYSENTER "sysexit", // X86_INS_SYSEXIT "sysexitq", // X86_INS_SYSEXITQ "sysret", // X86_INS_SYSRET "sysretq", // X86_INS_SYSRETQ "t1mskc", // X86_INS_T1MSKC "test", // X86_INS_TEST "tpause", // X86_INS_TPAUSE "tzcnt", // X86_INS_TZCNT "tzmsk", // X86_INS_TZMSK "ud0", // X86_INS_UD0 "ud1", // X86_INS_UD1 "ud2", // X86_INS_UD2 "umonitor", // X86_INS_UMONITOR "umwait", // X86_INS_UMWAIT "verr", // X86_INS_VERR "verw", // X86_INS_VERW "vmcall", // X86_INS_VMCALL "vmclear", // X86_INS_VMCLEAR "vmfunc", // X86_INS_VMFUNC "vmlaunch", // X86_INS_VMLAUNCH "vmload", // X86_INS_VMLOAD "vmmcall", // X86_INS_VMMCALL "vmptrld", // X86_INS_VMPTRLD "vmptrst", // X86_INS_VMPTRST "vmread", // X86_INS_VMREAD "vmresume", // X86_INS_VMRESUME "vmrun", // X86_INS_VMRUN "vmsave", // X86_INS_VMSAVE "vmwrite", // X86_INS_VMWRITE "vmxoff", // X86_INS_VMXOFF "vmxon", // X86_INS_VMXON "wbinvd", // X86_INS_WBINVD "wbnoinvd", // X86_INS_WBNOINVD "wrfsbase", // X86_INS_WRFSBASE "wrgsbase", // X86_INS_WRGSBASE "wrmsr", // X86_INS_WRMSR "wrpkru", // X86_INS_WRPKRU "wrssd", // X86_INS_WRSSD "wrssq", // X86_INS_WRSSQ "wrussd", // X86_INS_WRUSSD "wrussq", // X86_INS_WRUSSQ "xadd", // X86_INS_XADD "xchg", // X86_INS_XCHG "xcryptcbc", // X86_INS_XCRYPTCBC "xcryptcfb", // X86_INS_XCRYPTCFB "xcryptctr", // X86_INS_XCRYPTCTR "xcryptecb", // X86_INS_XCRYPTECB "xcryptofb", // X86_INS_XCRYPTOFB "xgetbv", // X86_INS_XGETBV "xlatb", // X86_INS_XLATB "xor", // X86_INS_XOR "xrstor", // X86_INS_XRSTOR "xrstor64", // X86_INS_XRSTOR64 "xrstors", // X86_INS_XRSTORS "xrstors64", // X86_INS_XRSTORS64 "xsave", // X86_INS_XSAVE "xsave64", // X86_INS_XSAVE64 "xsavec", // X86_INS_XSAVEC "xsavec64", // X86_INS_XSAVEC64 "xsaveopt", // X86_INS_XSAVEOPT "xsaveopt64", // X86_INS_XSAVEOPT64 "xsaves", // X86_INS_XSAVES "xsaves64", // X86_INS_XSAVES64 "xsetbv", // X86_INS_XSETBV "xsha1", // X86_INS_XSHA1 "xsha256", // X86_INS_XSHA256 "xstore", // X86_INS_XSTORE capstone-sys-0.15.0/capstone/arch/X86/X86MappingInsnOp.inc000064400000000000000000052445250072674642500212510ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { /* X86_AAA, X86_INS_AAA: aaa */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_AAD8i8, X86_INS_AAD: aad */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_IGNORE, 0 } }, { /* X86_AAM8i8, X86_INS_AAM: aam */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_IGNORE, 0 } }, { /* X86_AAS, X86_INS_AAS: aas */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_ABS_F, X86_INS_FABS: fabs */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_ABS_Fp32, X86_INS_FABS: fabs */ 0, { 0 } }, { /* X86_ABS_Fp64, X86_INS_FABS: fabs */ 0, { 0 } }, { /* X86_ABS_Fp80, X86_INS_FABS: fabs */ 0, { 0 } }, { /* X86_ADC16i16, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16mi, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16mi8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC16ri, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16ri8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC16rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC16rr_REV, X86_INS_ADC: adc{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32i32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32mi, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32mi8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32ri, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32ri8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32rr_REV, X86_INS_ADC: adc{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64i32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64mi32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64mi8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64ri32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64ri8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64rr_REV, X86_INS_ADC: adc{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8i8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8mi, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8mi8, X86_INS_ADC: adc{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8ri, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8ri8, X86_INS_ADC: adc{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8rr_REV, X86_INS_ADC: adc{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX32rm, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX32rr, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX64rm, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX64rr, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16i16, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16mi, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16mi8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16ri, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16ri8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16rr_REV, X86_INS_ADD: add{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32i32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32mi, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32mi8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32ri, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32ri8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32rr_REV, X86_INS_ADD: add{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64i32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64mi32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64mi8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64ri32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64ri8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64rr_REV, X86_INS_ADD: add{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8i8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8mi, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8mi8, X86_INS_ADD: add{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8ri, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8ri8, X86_INS_ADD: add{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8rr_REV, X86_INS_ADD: add{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDPDrm, X86_INS_ADDPD: addpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDPDrr, X86_INS_ADDPD: addpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDPSrm, X86_INS_ADDPS: addps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDPSrr, X86_INS_ADDPS: addps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSDrm, X86_INS_ADDSD: addsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSDrm_Int, X86_INS_ADDSD: addsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADDSDrr, X86_INS_ADDSD: addsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSDrr_Int, X86_INS_ADDSD: addsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSSrm, X86_INS_ADDSS: addss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSSrm_Int, X86_INS_ADDSS: addss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADDSSrr, X86_INS_ADDSS: addss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSSrr_Int, X86_INS_ADDSS: addss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSUBPDrm, X86_INS_ADDSUBPD: addsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSUBPDrr, X86_INS_ADDSUBPD: addsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSUBPSrm, X86_INS_ADDSUBPS: addsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADDSUBPSrr, X86_INS_ADDSUBPS: addsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD_F32m, X86_INS_FADD: fadd */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ADD_F64m, X86_INS_FADD: fadd */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ADD_FI16m, X86_INS_FIADD: fiadd */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ADD_FI32m, X86_INS_FIADD: fiadd */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ADD_FPrST0, X86_INS_FADD: faddp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ADD_FST0r, X86_INS_FADD: fadd */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ADD_Fp32, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp32m, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp64, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp64m, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp64m32, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp80, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp80m32, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_Fp80m64, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FpI16m32, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FpI16m64, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FpI16m80, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FpI32m32, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FpI32m64, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FpI32m80, X86_INS_FADD: fadd */ 0, { 0 } }, { /* X86_ADD_FrST0, X86_INS_FADD: fadd */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ADOX32rm, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX32rr, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX64rm, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX64rr, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESDECLASTrm, X86_INS_AESDECLAST: aesdeclast */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESDECLASTrr, X86_INS_AESDECLAST: aesdeclast */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESDECrm, X86_INS_AESDEC: aesdec */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESDECrr, X86_INS_AESDEC: aesdec */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESENCLASTrm, X86_INS_AESENCLAST: aesenclast */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESENCLASTrr, X86_INS_AESENCLAST: aesenclast */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESENCrm, X86_INS_AESENC: aesenc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESENCrr, X86_INS_AESENC: aesenc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESIMCrm, X86_INS_AESIMC: aesimc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESIMCrr, X86_INS_AESIMC: aesimc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AESKEYGENASSIST128rm, X86_INS_AESKEYGENASSIST: aeskeygenassist */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_AESKEYGENASSIST128rr, X86_INS_AESKEYGENASSIST: aeskeygenassist */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_AND16i16, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16mi, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16mi8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16ri, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16ri8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16rr_REV, X86_INS_AND: and{w} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32i32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32mi, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32mi8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32ri, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32ri8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32rr_REV, X86_INS_AND: and{l} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64i32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64mi32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64mi8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64ri32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64ri8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64rr_REV, X86_INS_AND: and{q} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8i8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8mi, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8mi8, X86_INS_AND: and{b} $dst $src */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8ri, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8ri8, X86_INS_AND: and{b} $src1 $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8rr_REV, X86_INS_AND: and{b} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDN32rm, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDN32rr, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDN64rm, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDN64rr, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDNPDrm, X86_INS_ANDNPD: andnpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDNPDrr, X86_INS_ANDNPD: andnpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDNPSrm, X86_INS_ANDNPS: andnps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDNPSrr, X86_INS_ANDNPS: andnps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDPDrm, X86_INS_ANDPD: andpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDPDrr, X86_INS_ANDPD: andpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDPSrm, X86_INS_ANDPS: andps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDPSrr, X86_INS_ANDPS: andps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ARPL16mr, X86_INS_ARPL: arpl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ARPL16rr, X86_INS_ARPL: arpl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BEXTR32rm, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTR32rr, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTR64rm, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTR64rr, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTRI32mi, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BEXTRI32ri, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BEXTRI64mi, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BEXTRI64ri, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BLCFILL32rm, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCFILL32rr, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCFILL64rm, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCFILL64rr, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI32rm, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI32rr, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI64rm, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI64rr, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC32rm, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC32rr, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC64rm, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC64rr, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK32rm, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK32rr, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK64rm, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK64rr, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS32rm, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS32rr, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS64rm, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS64rr, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLENDPDrmi, X86_INS_BLENDPD: blendpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BLENDPDrri, X86_INS_BLENDPD: blendpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BLENDPSrmi, X86_INS_BLENDPS: blendps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BLENDPSrri, X86_INS_BLENDPS: blendps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BLENDVPDrm0, X86_INS_BLENDVPD: blendvpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLENDVPDrr0, X86_INS_BLENDVPD: blendvpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLENDVPSrm0, X86_INS_BLENDVPS: blendvps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLENDVPSrr0, X86_INS_BLENDVPS: blendvps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL32rm, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL32rr, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL64rm, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL64rr, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI32rm, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI32rr, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI64rm, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI64rr, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC32rm, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC32rr, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC64rm, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC64rr, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK32rm, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK32rr, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK64rm, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK64rr, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR32rm, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR32rr, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR64rm, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR64rr, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDCL32rm, X86_INS_BNDCL: bndcl */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCL32rr, X86_INS_BNDCL: bndcl */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCL64rm, X86_INS_BNDCL: bndcl */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCL64rr, X86_INS_BNDCL: bndcl */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCN32rm, X86_INS_BNDCN: bndcn */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCN32rr, X86_INS_BNDCN: bndcn */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCN64rm, X86_INS_BNDCN: bndcn */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCN64rr, X86_INS_BNDCN: bndcn */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCU32rm, X86_INS_BNDCU: bndcu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCU32rr, X86_INS_BNDCU: bndcu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCU64rm, X86_INS_BNDCU: bndcu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDCU64rr, X86_INS_BNDCU: bndcu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BNDLDXrm, X86_INS_BNDLDX: bndldx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMK32rm, X86_INS_BNDMK: bndmk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMK64rm, X86_INS_BNDMK: bndmk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMOV32mr, X86_INS_BNDMOV: bndmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMOV32rm, X86_INS_BNDMOV: bndmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMOV64mr, X86_INS_BNDMOV: bndmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMOV64rm, X86_INS_BNDMOV: bndmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMOVrr, X86_INS_BNDMOV: bndmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDMOVrr_REV, X86_INS_BNDMOV: bndmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BNDSTXmr, X86_INS_BNDSTX: bndstx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BOUNDS16rm, X86_INS_BOUND: bound */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BOUNDS32rm, X86_INS_BOUND: bound */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF16rm, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF16rr, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF32rm, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF32rr, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF64rm, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF64rr, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR16rm, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR16rr, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR32rm, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR32rr, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR64rm, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR64rr, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSWAP16r_BAD, X86_INS_BSWAP: bswap */ 0, { 0 } }, { /* X86_BSWAP32r, X86_INS_BSWAP: bswap */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_BSWAP64r, X86_INS_BSWAP: bswap */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_BT16mi8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT16mr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT16ri8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT16rr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT32mi8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT32mr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT32ri8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT32rr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT64mi8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT64mr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT64ri8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT64rr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BTC16mi8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC16mr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC16ri8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC16rr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC32mi8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC32mr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC32ri8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC32rr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC64mi8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC64mr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC64ri8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC64rr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR16mi8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR16mr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR16ri8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR16rr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR32mi8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR32mr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR32ri8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR32rr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR64mi8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR64mr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR64ri8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR64rr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS16mi8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS16mr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS16ri8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS16rr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS32mi8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS32mr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS32ri8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS32rr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS64mi8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS64mr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS64ri8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS64rr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BZHI32rm, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BZHI32rr, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BZHI64rm, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BZHI64rr, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CALL16m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL16m_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL16r, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL16r_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL32m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL32m_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL32r, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL32r_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL64m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL64m_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL64pcrel32, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALL64r, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL64r_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALLpcrel16, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALLpcrel32, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CBW, X86_INS_CBW: cbw */ 0, { 0 } }, { /* X86_CDQ, X86_INS_CDQ: cdq */ 0, { 0 } }, { /* X86_CDQE, X86_INS_CDQE: cdqe */ 0, { 0 } }, { /* X86_CHS_F, X86_INS_FCHS: fchs */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_CHS_Fp32, X86_INS_FCHS: fchs */ 0, { 0 } }, { /* X86_CHS_Fp64, X86_INS_FCHS: fchs */ 0, { 0 } }, { /* X86_CHS_Fp80, X86_INS_FCHS: fchs */ 0, { 0 } }, { /* X86_CLAC, X86_INS_CLAC: clac */ X86_EFLAGS_RESET_AC, { 0 } }, { /* X86_CLC, X86_INS_CLC: clc */ X86_EFLAGS_RESET_CF, { 0 } }, { /* X86_CLD, X86_INS_CLD: cld */ X86_EFLAGS_RESET_DF, { 0 } }, { /* X86_CLDEMOTE, X86_INS_CLDEMOTE: cldemote */ 0, { 0 } }, { /* X86_CLFLUSH, X86_INS_CLFLUSH: clflush */ 0, { CS_AC_READ, 0 } }, { /* X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT: clflushopt */ 0, { CS_AC_READ, 0 } }, { /* X86_CLGI, X86_INS_CLGI: clgi */ 0, { 0 } }, { /* X86_CLI, X86_INS_CLI: cli */ X86_EFLAGS_RESET_IF, { 0 } }, { /* X86_CLRSSBSY, X86_INS_CLRSSBSY: clrssbsy */ 0, { 0 } }, { /* X86_CLTS, X86_INS_CLTS: clts */ 0, { 0 } }, { /* X86_CLWB, X86_INS_CLWB: clwb */ 0, { CS_AC_READ, 0 } }, { /* X86_CLZEROr, X86_INS_CLZERO: clzero */ 0, { 0 } }, { /* X86_CMC, X86_INS_CMC: cmc */ X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_CMOVA16rm, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA16rr, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA32rm, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA32rr, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA64rm, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA64rr, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE16rm, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE16rr, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE32rm, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE32rr, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE64rm, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE64rr, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB16rm, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB16rr, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB32rm, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB32rr, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB64rm, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB64rr, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE16rm, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE16rr, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE32rm, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE32rr, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE64rm, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE64rr, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE_F, X86_INS_FCMOVBE: fcmovbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVBE_Fp32, X86_INS_FCMOVBE: fcmovbe */ 0, { 0 } }, { /* X86_CMOVBE_Fp64, X86_INS_FCMOVBE: fcmovbe */ 0, { 0 } }, { /* X86_CMOVBE_Fp80, X86_INS_FCMOVBE: fcmovbe */ 0, { 0 } }, { /* X86_CMOVB_F, X86_INS_FCMOVB: fcmovb */ X86_EFLAGS_TEST_CF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVB_Fp32, X86_INS_FCMOVB: fcmovb */ 0, { 0 } }, { /* X86_CMOVB_Fp64, X86_INS_FCMOVB: fcmovb */ 0, { 0 } }, { /* X86_CMOVB_Fp80, X86_INS_FCMOVB: fcmovb */ 0, { 0 } }, { /* X86_CMOVE16rm, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE16rr, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE32rm, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE32rr, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE64rm, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE64rr, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE_F, X86_INS_FCMOVE: fcmove */ X86_EFLAGS_TEST_ZF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVE_Fp32, X86_INS_FCMOVE: fcmove */ 0, { 0 } }, { /* X86_CMOVE_Fp64, X86_INS_FCMOVE: fcmove */ 0, { 0 } }, { /* X86_CMOVE_Fp80, X86_INS_FCMOVE: fcmove */ 0, { 0 } }, { /* X86_CMOVG16rm, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG16rr, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG32rm, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG32rr, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG64rm, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG64rr, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE16rm, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE16rr, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE32rm, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE32rr, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE64rm, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE64rr, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL16rm, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL16rr, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL32rm, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL32rr, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL64rm, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL64rr, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE16rm, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE16rr, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE32rm, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE32rr, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE64rm, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE64rr, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNBE_F, X86_INS_FCMOVNBE: fcmovnbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVNBE_Fp32, X86_INS_FCMOVNBE: fcmovnbe */ 0, { 0 } }, { /* X86_CMOVNBE_Fp64, X86_INS_FCMOVNBE: fcmovnbe */ 0, { 0 } }, { /* X86_CMOVNBE_Fp80, X86_INS_FCMOVNBE: fcmovnbe */ 0, { 0 } }, { /* X86_CMOVNB_F, X86_INS_FCMOVNB: fcmovnb */ X86_EFLAGS_TEST_CF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVNB_Fp32, X86_INS_FCMOVNB: fcmovnb */ 0, { 0 } }, { /* X86_CMOVNB_Fp64, X86_INS_FCMOVNB: fcmovnb */ 0, { 0 } }, { /* X86_CMOVNB_Fp80, X86_INS_FCMOVNB: fcmovnb */ 0, { 0 } }, { /* X86_CMOVNE16rm, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE16rr, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE32rm, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE32rr, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE64rm, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE64rr, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE_F, X86_INS_FCMOVNE: fcmovne */ X86_EFLAGS_TEST_ZF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVNE_Fp32, X86_INS_FCMOVNE: fcmovne */ 0, { 0 } }, { /* X86_CMOVNE_Fp64, X86_INS_FCMOVNE: fcmovne */ 0, { 0 } }, { /* X86_CMOVNE_Fp80, X86_INS_FCMOVNE: fcmovne */ 0, { 0 } }, { /* X86_CMOVNO16rm, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO16rr, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO32rm, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO32rr, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO64rm, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO64rr, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP16rm, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP16rr, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP32rm, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP32rr, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP64rm, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP64rr, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP_F, X86_INS_FCMOVNU: fcmovnu */ X86_EFLAGS_TEST_PF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVNP_Fp32, X86_INS_FCMOVNP: fcmovnp */ 0, { 0 } }, { /* X86_CMOVNP_Fp64, X86_INS_FCMOVNU: fcmovnu */ 0, { 0 } }, { /* X86_CMOVNP_Fp80, X86_INS_FCMOVNU: fcmovnu */ 0, { 0 } }, { /* X86_CMOVNS16rm, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS16rr, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS32rm, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS32rr, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS64rm, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS64rr, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO16rm, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO16rr, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO32rm, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO32rr, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO64rm, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO64rr, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP16rm, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP16rr, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP32rm, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP32rr, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP64rm, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP64rr, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP_F, X86_INS_FCMOVU: fcmovu */ X86_EFLAGS_TEST_PF, { CS_AC_READ, CS_AC_WRITE, 0 } }, { /* X86_CMOVP_Fp32, X86_INS_FCMOVU: fcmovu */ 0, { 0 } }, { /* X86_CMOVP_Fp64, X86_INS_FCMOVU: fcmovu */ 0, { 0 } }, { /* X86_CMOVP_Fp80, X86_INS_FCMOVU: fcmovu */ 0, { 0 } }, { /* X86_CMOVS16rm, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS16rr, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS32rm, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS32rr, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS64rm, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS64rr, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMP16i16, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16mi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16mi8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP16ri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16ri8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP16rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP16rr_REV, X86_INS_CMP: cmp{w} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32i32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32mi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32mi8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32ri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32ri8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32rr_REV, X86_INS_CMP: cmp{l} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64i32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64mi32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64mi8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64ri32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64ri8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64rr_REV, X86_INS_CMP: cmp{q} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8i8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8mi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8mi8, X86_INS_CMP: cmp{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8ri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8ri8, X86_INS_CMP: cmp{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8rr_REV, X86_INS_CMP: cmp{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPPDrmi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPPDrmi_alt, X86_INS_CMPPD: cmppd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPPDrri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPPDrri_alt, X86_INS_CMPPD: cmppd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPPSrmi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPPSrmi_alt, X86_INS_CMPPS: cmpps */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPPSrri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPPSrri_alt, X86_INS_CMPPS: cmpps */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPSB, X86_INS_CMPSB: cmpsb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPSDrm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPSDrm_Int, X86_INS_CMPSD: cmpsd */ 0, { 0 } }, { /* X86_CMPSDrm_alt, X86_INS_CMPSD: cmpsd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPSDrr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPSDrr_Int, X86_INS_CMPSD: cmpsd */ 0, { 0 } }, { /* X86_CMPSDrr_alt, X86_INS_CMPSD: cmpsd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPSL, X86_INS_CMPSD: cmpsd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_CMPSQ, X86_INS_CMPSQ: cmpsq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPSSrm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPSSrm_Int, X86_INS_CMPSS: cmpss */ 0, { 0 } }, { /* X86_CMPSSrm_alt, X86_INS_CMPSS: cmpss */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPSSrr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPSSrr_Int, X86_INS_CMP: cmp */ 0, { 0 } }, { /* X86_CMPSSrr_alt, X86_INS_CMPSS: cmpss */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMPSW, X86_INS_CMPSW: cmpsw */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG16B, X86_INS_CMPXCHG16B: cmpxchg16b */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_CMPXCHG16rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG16rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPXCHG32rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG32rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPXCHG64rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG64rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPXCHG8B, X86_INS_CMPXCHG8B: cmpxchg8b */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_CMPXCHG8rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG8rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_COMISDrm, X86_INS_COMISD: comisd */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_COMISDrm_Int, X86_INS_COMISD: comisd */ 0, { 0 } }, { /* X86_COMISDrr, X86_INS_COMISD: comisd */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_COMISDrr_Int, X86_INS_COMISD: comisd */ 0, { 0 } }, { /* X86_COMISSrm, X86_INS_COMISS: comiss */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_COMISSrm_Int, X86_INS_COMISS: comiss */ 0, { 0 } }, { /* X86_COMISSrr, X86_INS_COMISS: comiss */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_COMISSrr_Int, X86_INS_COMISS: comiss */ 0, { 0 } }, { /* X86_COMP_FST0r, X86_INS_FCOMP: fcomp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_COM_FIPr, X86_INS_FCOMPI: fcompi */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_COM_FIr, X86_INS_FCOMI: fcomi */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_COM_FST0r, X86_INS_FCOM: fcom */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_COS_F, X86_INS_FCOS: fcos */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_COS_Fp32, X86_INS_FCOS: fcos */ 0, { 0 } }, { /* X86_COS_Fp64, X86_INS_FCOS: fcos */ 0, { 0 } }, { /* X86_COS_Fp80, X86_INS_FCOS: fcos */ 0, { 0 } }, { /* X86_CPUID, X86_INS_CPUID: cpuid */ 0, { 0 } }, { /* X86_CQO, X86_INS_CQO: cqo */ 0, { 0 } }, { /* X86_CRC32r32m16, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r32m32, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r32m8, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r32r16, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r32r32, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r32r8, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r64m64, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r64m8, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r64r64, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CRC32r64r8, X86_INS_CRC32: crc32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTDQ2PDrm, X86_INS_CVTDQ2PD: cvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTDQ2PDrr, X86_INS_CVTDQ2PD: cvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTDQ2PSrm, X86_INS_CVTDQ2PS: cvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTDQ2PSrr, X86_INS_CVTDQ2PS: cvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPD2DQrm, X86_INS_CVTPD2DQ: cvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPD2DQrr, X86_INS_CVTPD2DQ: cvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPD2PSrm, X86_INS_CVTPD2PS: cvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPD2PSrr, X86_INS_CVTPD2PS: cvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPS2DQrm, X86_INS_CVTPS2DQ: cvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPS2DQrr, X86_INS_CVTPS2DQ: cvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPS2PDrm, X86_INS_CVTPS2PD: cvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTPS2PDrr, X86_INS_CVTPS2PD: cvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSD2SI64rm_Int, X86_INS_CVTSD2SI: cvtsd2si */ 0, { 0 } }, { /* X86_CVTSD2SI64rr_Int, X86_INS_CVTSD2SI: cvtsd2si */ 0, { 0 } }, { /* X86_CVTSD2SIrm_Int, X86_INS_CVTSD2SI: cvtsd2si */ 0, { 0 } }, { /* X86_CVTSD2SIrr_Int, X86_INS_CVTSD2SI: cvtsd2si */ 0, { 0 } }, { /* X86_CVTSD2SSrm, X86_INS_CVTSD2SS: cvtsd2ss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSD2SSrm_Int, X86_INS_CVTSD2SS: cvtsd2ss */ 0, { 0 } }, { /* X86_CVTSD2SSrr, X86_INS_CVTSD2SS: cvtsd2ss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSD2SSrr_Int, X86_INS_CVTSD2SS: cvtsd2ss */ 0, { 0 } }, { /* X86_CVTSI2SDrm, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSI2SDrm_Int, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { 0 } }, { /* X86_CVTSI2SDrr, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSI2SDrr_Int, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { 0 } }, { /* X86_CVTSI2SSrm, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSI2SSrm_Int, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { 0 } }, { /* X86_CVTSI2SSrr, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSI2SSrr_Int, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { 0 } }, { /* X86_CVTSI642SDrm, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { 0 } }, { /* X86_CVTSI642SDrm_Int, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { 0 } }, { /* X86_CVTSI642SDrr, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { 0 } }, { /* X86_CVTSI642SDrr_Int, X86_INS_CVTSI2SD: cvtsi2sd */ 0, { 0 } }, { /* X86_CVTSI642SSrm, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { 0 } }, { /* X86_CVTSI642SSrm_Int, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { 0 } }, { /* X86_CVTSI642SSrr, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { 0 } }, { /* X86_CVTSI642SSrr_Int, X86_INS_CVTSI2SS: cvtsi2ss */ 0, { 0 } }, { /* X86_CVTSS2SDrm, X86_INS_CVTSS2SD: cvtss2sd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSS2SDrm_Int, X86_INS_CVTSS2SD: cvtss2sd */ 0, { 0 } }, { /* X86_CVTSS2SDrr, X86_INS_CVTSS2SD: cvtss2sd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTSS2SDrr_Int, X86_INS_CVTSS2SD: cvtss2sd */ 0, { 0 } }, { /* X86_CVTSS2SI64rm_Int, X86_INS_CVTSS2SI: cvtss2si */ 0, { 0 } }, { /* X86_CVTSS2SI64rr_Int, X86_INS_CVTSS2SI: cvtss2si */ 0, { 0 } }, { /* X86_CVTSS2SIrm_Int, X86_INS_CVTSS2SI: cvtss2si */ 0, { 0 } }, { /* X86_CVTSS2SIrr_Int, X86_INS_CVTSS2SI: cvtss2si */ 0, { 0 } }, { /* X86_CVTTPD2DQrm, X86_INS_CVTTPD2DQ: cvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTPD2DQrr, X86_INS_CVTTPD2DQ: cvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTPS2DQrm, X86_INS_CVTTPS2DQ: cvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTPS2DQrr, X86_INS_CVTTPS2DQ: cvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSD2SI64rm, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSD2SI64rm_Int, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { 0 } }, { /* X86_CVTTSD2SI64rr, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSD2SI64rr_Int, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { 0 } }, { /* X86_CVTTSD2SIrm, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSD2SIrm_Int, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { 0 } }, { /* X86_CVTTSD2SIrr, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSD2SIrr_Int, X86_INS_CVTTSD2SI: cvttsd2si */ 0, { 0 } }, { /* X86_CVTTSS2SI64rm, X86_INS_CVTTSS2SI: cvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSS2SI64rm_Int, X86_INS_CVTTSS2SI: cvttss2si */ 0, { 0 } }, { /* X86_CVTTSS2SI64rr, X86_INS_CVTTSS2SI: cvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSS2SI64rr_Int, X86_INS_CVTTSS2SI: cvttss2si */ 0, { 0 } }, { /* X86_CVTTSS2SIrm, X86_INS_CVTTSS2SI: cvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSS2SIrm_Int, X86_INS_CVTTSS2SI: cvttss2si */ 0, { 0 } }, { /* X86_CVTTSS2SIrr, X86_INS_CVTTSS2SI: cvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CVTTSS2SIrr_Int, X86_INS_CVTTSS2SI: cvttss2si */ 0, { 0 } }, { /* X86_CWD, X86_INS_CWD: cwd */ 0, { 0 } }, { /* X86_CWDE, X86_INS_CWDE: cwde */ 0, { 0 } }, { /* X86_DAA, X86_INS_DAA: daa */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_DAS, X86_INS_DAS: das */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_DATA16_PREFIX, X86_INS_DATA16: data16 */ 0, { 0 } }, { /* X86_DEC16m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC16r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC16r_alt, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC32m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC32r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC32r_alt, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC64m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC64r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC8m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC8r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DIV16m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV16r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV32m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV32r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV64m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV64r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV8m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV8r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIVPDrm, X86_INS_DIVPD: divpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVPDrr, X86_INS_DIVPD: divpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVPSrm, X86_INS_DIVPS: divps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVPSrr, X86_INS_DIVPS: divps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVR_F32m, X86_INS_FDIVR: fdivr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIVR_F64m, X86_INS_FDIVR: fdivr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIVR_FI16m, X86_INS_FIDIVR: fidivr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIVR_FI32m, X86_INS_FIDIVR: fidivr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIVR_FPrST0, X86_INS_FDIVRP: fdivrp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIVR_FST0r, X86_INS_FDIVR: fdivr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIVR_Fp32m, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_Fp64m, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_Fp64m32, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_Fp80m32, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_Fp80m64, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FpI16m32, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FpI16m64, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FpI16m80, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FpI32m32, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FpI32m64, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FpI32m80, X86_INS_FDIVR: fdivr */ 0, { 0 } }, { /* X86_DIVR_FrST0, X86_INS_FDIVR: fdivr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_DIVSDrm, X86_INS_DIVSD: divsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVSDrm_Int, X86_INS_DIVSD: divsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_DIVSDrr, X86_INS_DIVSD: divsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVSDrr_Int, X86_INS_DIVSD: divsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVSSrm, X86_INS_DIVSS: divss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVSSrm_Int, X86_INS_DIVSS: divss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_DIVSSrr, X86_INS_DIVSS: divss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIVSSrr_Int, X86_INS_DIVSS: divss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_DIV_F32m, X86_INS_FDIV: fdiv */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIV_F64m, X86_INS_FDIV: fdiv */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIV_FI16m, X86_INS_FIDIV: fidiv */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIV_FI32m, X86_INS_FIDIV: fidiv */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIV_FPrST0, X86_INS_FDIVP: fdivp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIV_FST0r, X86_INS_FDIV: fdiv */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_DIV_Fp32, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp32m, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp64, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp64m, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp64m32, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp80, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp80m32, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_Fp80m64, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FpI16m32, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FpI16m64, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FpI16m80, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FpI32m32, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FpI32m64, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FpI32m80, X86_INS_FDIV: fdiv */ 0, { 0 } }, { /* X86_DIV_FrST0, X86_INS_FDIV: fdiv */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_DPPDrmi, X86_INS_DPPD: dppd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_DPPDrri, X86_INS_DPPD: dppd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_DPPSrmi, X86_INS_DPPS: dpps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_DPPSrri, X86_INS_DPPS: dpps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ENCLS, X86_INS_ENCLS: encls */ 0, { 0 } }, { /* X86_ENCLU, X86_INS_ENCLU: enclu */ 0, { 0 } }, { /* X86_ENCLV, X86_INS_ENCLV: enclv */ 0, { 0 } }, { /* X86_ENDBR32, X86_INS_ENDBR32: endbr32 */ 0, { 0 } }, { /* X86_ENDBR64, X86_INS_ENDBR64: endbr64 */ 0, { 0 } }, { /* X86_ENTER, X86_INS_ENTER: enter */ 0, { CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_EXTRACTPSmr, X86_INS_EXTRACTPS: extractps */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_EXTRACTPSrr, X86_INS_EXTRACTPS: extractps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_EXTRQ, X86_INS_EXTRQ: extrq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_EXTRQI, X86_INS_EXTRQ: extrq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_F2XM1, X86_INS_F2XM1: f2xm1 */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FARCALL16i, X86_INS_LCALL: lcall{w} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARCALL16m, X86_INS_LCALL: lcall */ 0, { CS_AC_READ, 0 } }, { /* X86_FARCALL32i, X86_INS_LCALL: lcall{l} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARCALL32m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_FARCALL64, X86_INS_LCALL: lcall */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARJMP16i, X86_INS_LJMP: ljmp{w} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARJMP16m, X86_INS_LJMP: ljmp{w} {*}$dst */ 0, { CS_AC_READ, 0 } }, { /* X86_FARJMP32i, X86_INS_LJMP: ljmp{l} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARJMP32m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_FARJMP64, X86_INS_LJMP: ljmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FBLDm, X86_INS_FBLD: fbld */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_FBSTPm, X86_INS_FBSTP: fbstp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_FCOM32m, X86_INS_FCOM: fcom */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FCOM64m, X86_INS_FCOM: fcom */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FCOMP32m, X86_INS_FCOMP: fcomp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FCOMP64m, X86_INS_FCOMP: fcomp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FCOMPP, X86_INS_FCOMPP: fcompp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { 0 } }, { /* X86_FDECSTP, X86_INS_FDECSTP: fdecstp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FDISI8087_NOP, X86_INS_FDISI8087_NOP: fdisi8087_nop */ 0, { 0 } }, { /* X86_FEMMS, X86_INS_FEMMS: femms */ 0, { 0 } }, { /* X86_FENI8087_NOP, X86_INS_FENI8087_NOP: feni8087_nop */ 0, { 0 } }, { /* X86_FFREE, X86_INS_FFREE: ffree */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_FFREEP, X86_INS_FFREEP: ffreep */ 0, { 0 } }, { /* X86_FICOM16m, X86_INS_FICOM: ficom */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FICOM32m, X86_INS_FICOM: ficom */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FICOMP16m, X86_INS_FICOMP: ficomp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FICOMP32m, X86_INS_FICOMP: ficomp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_FINCSTP, X86_INS_FINCSTP: fincstp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FLDCW16m, X86_INS_FLDCW: fldcw */ X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_FLDENVm, X86_INS_FLDENV: fldenv */ 0, { CS_AC_READ, 0 } }, { /* X86_FLDL2E, X86_INS_FLDL2E: fldl2e */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FLDL2T, X86_INS_FLDL2T: fldl2t */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FLDLG2, X86_INS_FLDLG2: fldlg2 */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FLDLN2, X86_INS_FLDLN2: fldln2 */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FLDPI, X86_INS_FLDPI: fldpi */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FNCLEX, X86_INS_FNCLEX: fnclex */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FNINIT, X86_INS_FNINIT: fninit */ X86_FPU_FLAGS_RESET_C0 | X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_RESET_C2 | X86_FPU_FLAGS_RESET_C3, { 0 } }, { /* X86_FNOP, X86_INS_FNOP: fnop */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FNSTCW16m, X86_INS_FNSTCW: fnstcw */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_FNSTSW16r, X86_INS_FNSTSW: fnstsw */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_FNSTSWm, X86_INS_FNSTSW: fnstsw */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_FPATAN, X86_INS_FPATAN: fpatan */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FPNCEST0r, X86_INS_FSTPNCE: fstpnce */ 0, { 0 } }, { /* X86_FPREM, X86_INS_FPREM: fprem */ X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { 0 } }, { /* X86_FPREM1, X86_INS_FPREM1: fprem1 */ X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { 0 } }, { /* X86_FPTAN, X86_INS_FPTAN: fptan */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FRNDINT, X86_INS_FRNDINT: frndint */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FRSTORm, X86_INS_FRSTOR: frstor */ 0, { CS_AC_WRITE, 0 } }, { /* X86_FSAVEm, X86_INS_FNSAVE: fnsave */ X86_FPU_FLAGS_RESET_C0 | X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_RESET_C2 | X86_FPU_FLAGS_RESET_C3, { CS_AC_WRITE, 0 } }, { /* X86_FSCALE, X86_INS_FSCALE: fscale */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FSETPM, X86_INS_FSETPM: fsetpm */ 0, { 0 } }, { /* X86_FSINCOS, X86_INS_FSINCOS: fsincos */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FSTENVm, X86_INS_FNSTENV: fnstenv */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_FXAM, X86_INS_FXAM: fxam */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { 0 } }, { /* X86_FXRSTOR, X86_INS_FXRSTOR: fxrstor */ 0, { CS_AC_READ, 0 } }, { /* X86_FXRSTOR64, X86_INS_FXRSTOR64: fxrstor64 */ 0, { CS_AC_READ, 0 } }, { /* X86_FXSAVE, X86_INS_FXSAVE: fxsave */ 0, { CS_AC_WRITE, 0 } }, { /* X86_FXSAVE64, X86_INS_FXSAVE64: fxsave64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_FXTRACT, X86_INS_FXTRACT: fxtract */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FYL2X, X86_INS_FYL2X: fyl2x */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_FYL2XP1, X86_INS_FYL2XP1: fyl2xp1 */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_GETSEC, X86_INS_GETSEC: getsec */ 0, { 0 } }, { /* X86_GF2P8AFFINEINVQBrmi, X86_INS_GF2P8AFFINEINVQB: gf2p8affineinvqb */ 0, { 0 } }, { /* X86_GF2P8AFFINEINVQBrri, X86_INS_GF2P8AFFINEINVQB: gf2p8affineinvqb */ 0, { 0 } }, { /* X86_GF2P8AFFINEQBrmi, X86_INS_GF2P8AFFINEQB: gf2p8affineqb */ 0, { 0 } }, { /* X86_GF2P8AFFINEQBrri, X86_INS_GF2P8AFFINEQB: gf2p8affineqb */ 0, { 0 } }, { /* X86_GF2P8MULBrm, X86_INS_GF2P8MULB: gf2p8mulb */ 0, { 0 } }, { /* X86_GF2P8MULBrr, X86_INS_GF2P8MULB: gf2p8mulb */ 0, { 0 } }, { /* X86_HADDPDrm, X86_INS_HADDPD: haddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HADDPDrr, X86_INS_HADDPD: haddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HADDPSrm, X86_INS_HADDPS: haddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HADDPSrr, X86_INS_HADDPS: haddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HLT, X86_INS_HLT: hlt */ 0, { 0 } }, { /* X86_HSUBPDrm, X86_INS_HSUBPD: hsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HSUBPDrr, X86_INS_HSUBPD: hsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HSUBPSrm, X86_INS_HSUBPS: hsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_HSUBPSrr, X86_INS_HSUBPS: hsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IDIV16m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV16r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV32m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV32r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV64m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV64r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV8m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV8r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_ILD_F16m, X86_INS_FILD: fild */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ILD_F32m, X86_INS_FILD: fild */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ILD_F64m, X86_INS_FILD: fild */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ILD_Fp16m32, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp16m64, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp16m80, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp32m32, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp32m64, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp32m80, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp64m32, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp64m64, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_ILD_Fp64m80, X86_INS_FILD: fild */ 0, { 0 } }, { /* X86_IMUL16m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL16r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL16rm, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL16rmi, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL16rmi8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL16rr, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL16rri, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL16rri8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL32r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL32rm, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL32rmi, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32rmi8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32rr, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL32rri, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32rri8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL64r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL64rm, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL64rmi32, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64rmi8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64rr, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL64rri32, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64rri8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL8m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL8r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IN16ri, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_IN16rr, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IN32ri, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_IN32rr, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IN8ri, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_IN8rr, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_INC16m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC16r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC16r_alt, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC32m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC32r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC32r_alt, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC64m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC64r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC8m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC8r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INCSSPD, X86_INS_INCSSPD: incsspd */ 0, { 0 } }, { /* X86_INCSSPQ, X86_INS_INCSSPQ: incsspq */ 0, { 0 } }, { /* X86_INSB, X86_INS_INSB: insb */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_INSERTPSrm, X86_INS_INSERTPS: insertps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_INSERTPSrr, X86_INS_INSERTPS: insertps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_INSERTQ, X86_INS_INSERTQ: insertq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_INSERTQI, X86_INS_INSERTQ: insertq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_INSL, X86_INS_INSD: insd */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_INSW, X86_INS_INSW: insw */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_INT, X86_INS_INT: int */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { CS_AC_IGNORE, 0 } }, { /* X86_INT1, X86_INS_INT1: int1 */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_INT3, X86_INS_INT3: int3 */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_INTO, X86_INS_INTO: into */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_INVD, X86_INS_INVD: invd */ 0, { 0 } }, { /* X86_INVEPT32, X86_INS_INVEPT: invept */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVEPT64, X86_INS_INVEPT: invept */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVLPG, X86_INS_INVLPG: invlpg */ 0, { CS_AC_READ, 0 } }, { /* X86_INVLPGA32, X86_INS_INVLPGA: invlpga */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVLPGA64, X86_INS_INVLPGA: invlpga */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVPCID32, X86_INS_INVPCID: invpcid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVPCID64, X86_INS_INVPCID: invpcid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVVPID32, X86_INS_INVVPID: invvpid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVVPID64, X86_INS_INVVPID: invvpid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_IRET16, X86_INS_IRET: iret */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_IRET32, X86_INS_IRETD: iretd */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_IRET64, X86_INS_IRETQ: iretq */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_ISTT_FP16m, X86_INS_FISTTP: fisttp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ISTT_FP32m, X86_INS_FISTTP: fisttp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ISTT_FP64m, X86_INS_FISTTP: fisttp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ISTT_Fp16m32, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp16m64, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp16m80, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp32m32, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp32m64, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp32m80, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp64m32, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp64m64, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_ISTT_Fp64m80, X86_INS_FISTTP: fisttp */ 0, { 0 } }, { /* X86_IST_F16m, X86_INS_FIST: fist */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_IST_F32m, X86_INS_FIST: fist */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_IST_FP16m, X86_INS_FISTP: fistp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_IST_FP32m, X86_INS_FISTP: fistp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_IST_FP64m, X86_INS_FISTP: fistp */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_IST_Fp16m32, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp16m64, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp16m80, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp32m32, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp32m64, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp32m80, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp64m32, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp64m64, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_IST_Fp64m80, X86_INS_FISTP: fistp */ 0, { 0 } }, { /* X86_JAE_1, X86_INS_JAE: jae */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JAE_2, X86_INS_JAE: jae $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JAE_4, X86_INS_JAE: jae $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JA_1, X86_INS_JA: ja */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JA_2, X86_INS_JA: ja $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JA_4, X86_INS_JA: ja $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JBE_1, X86_INS_JBE: jbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JBE_2, X86_INS_JBE: jbe $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JBE_4, X86_INS_JBE: jbe $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JB_1, X86_INS_JB: jb */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JB_2, X86_INS_JB: jb $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JB_4, X86_INS_JB: jb $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JCXZ, X86_INS_JCXZ: jcxz */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JECXZ, X86_INS_JECXZ: jecxz */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JE_1, X86_INS_JE: je */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JE_2, X86_INS_JE: je $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JE_4, X86_INS_JE: je $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JGE_1, X86_INS_JGE: jge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JGE_2, X86_INS_JGE: jge $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JGE_4, X86_INS_JGE: jge $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JG_1, X86_INS_JG: jg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JG_2, X86_INS_JG: jg $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JG_4, X86_INS_JG: jg $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JLE_1, X86_INS_JLE: jle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JLE_2, X86_INS_JLE: jle $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JLE_4, X86_INS_JLE: jle $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JL_1, X86_INS_JL: jl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JL_2, X86_INS_JL: jl $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JL_4, X86_INS_JL: jl $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JMP16m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP16m_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP16r, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP16r_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP32m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP32m_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP32r, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP32r_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP64m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP64m_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP64r, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP64r_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP_1, X86_INS_JMP: jmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP_2, X86_INS_JMP: jmp $dst */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP_4, X86_INS_JMP: jmp $dst */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JNE_1, X86_INS_JNE: jne */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JNE_2, X86_INS_JNE: jne $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JNE_4, X86_INS_JNE: jne $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JNO_1, X86_INS_JNO: jno */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JNO_2, X86_INS_JNO: jno $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JNO_4, X86_INS_JNO: jno $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JNP_1, X86_INS_JNP: jnp */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JNP_2, X86_INS_JNP: jnp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JNP_4, X86_INS_JNP: jnp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JNS_1, X86_INS_JNS: jns */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JNS_2, X86_INS_JNS: jns $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JNS_4, X86_INS_JNS: jns $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JO_1, X86_INS_JO: jo */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JO_2, X86_INS_JO: jo $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JO_4, X86_INS_JO: jo $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JP_1, X86_INS_JP: jp */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JP_2, X86_INS_JP: jp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JP_4, X86_INS_JP: jp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JRCXZ, X86_INS_JRCXZ: jrcxz */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JS_1, X86_INS_JS: js */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JS_2, X86_INS_JS: js $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JS_4, X86_INS_JS: js $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_KADDBrr, X86_INS_KADDB: kaddb */ 0, { 0 } }, { /* X86_KADDDrr, X86_INS_KADDD: kaddd */ 0, { 0 } }, { /* X86_KADDQrr, X86_INS_KADDQ: kaddq */ 0, { 0 } }, { /* X86_KADDWrr, X86_INS_KADDW: kaddw */ 0, { 0 } }, { /* X86_KANDBrr, X86_INS_KANDB: kandb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDDrr, X86_INS_KANDD: kandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDNBrr, X86_INS_KANDNB: kandnb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDNDrr, X86_INS_KANDND: kandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDNQrr, X86_INS_KANDNQ: kandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDNWrr, X86_INS_KANDNW: kandnw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDQrr, X86_INS_KANDQ: kandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KANDWrr, X86_INS_KANDW: kandw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KMOVBkk, X86_INS_KMOVB: kmovb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVBkm, X86_INS_KMOVB: kmovb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVBkr, X86_INS_KMOVB: kmovb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVBmk, X86_INS_KMOVB: kmovb */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KMOVBrk, X86_INS_KMOVB: kmovb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVDkk, X86_INS_KMOVD: kmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVDkm, X86_INS_KMOVD: kmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVDkr, X86_INS_KMOVD: kmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVDmk, X86_INS_KMOVD: kmovd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KMOVDrk, X86_INS_KMOVD: kmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVQkk, X86_INS_KMOVQ: kmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVQkm, X86_INS_KMOVQ: kmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVQkr, X86_INS_KMOVQ: kmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVQmk, X86_INS_KMOVQ: kmovq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KMOVQrk, X86_INS_KMOVQ: kmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVWkk, X86_INS_KMOVW: kmovw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVWkm, X86_INS_KMOVW: kmovw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVWkr, X86_INS_KMOVW: kmovw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KMOVWmk, X86_INS_KMOVW: kmovw */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KMOVWrk, X86_INS_KMOVW: kmovw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KNOTBrr, X86_INS_KNOTB: knotb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KNOTDrr, X86_INS_KNOTD: knotd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KNOTQrr, X86_INS_KNOTQ: knotq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KNOTWrr, X86_INS_KNOTW: knotw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_KORBrr, X86_INS_KORB: korb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORDrr, X86_INS_KORD: kord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORQrr, X86_INS_KORQ: korq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORTESTBrr, X86_INS_KORTESTB: kortestb */ X86_REG_EFLAGS, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORTESTDrr, X86_INS_KORTESTD: kortestd */ X86_REG_EFLAGS, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORTESTQrr, X86_INS_KORTESTQ: kortestq */ X86_REG_EFLAGS, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORTESTWrr, X86_INS_KORTESTW: kortestw */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KORWrr, X86_INS_KORW: korw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KSHIFTLBri, X86_INS_KSHIFTLB: kshiftlb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTLDri, X86_INS_KSHIFTLD: kshiftld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTLQri, X86_INS_KSHIFTLQ: kshiftlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTLWri, X86_INS_KSHIFTLW: kshiftlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTRBri, X86_INS_KSHIFTRB: kshiftrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTRDri, X86_INS_KSHIFTRD: kshiftrd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTRQri, X86_INS_KSHIFTRQ: kshiftrq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KSHIFTRWri, X86_INS_KSHIFTRW: kshiftrw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_KTESTBrr, X86_INS_KTESTB: ktestb */ 0, { 0 } }, { /* X86_KTESTDrr, X86_INS_KTESTD: ktestd */ 0, { 0 } }, { /* X86_KTESTQrr, X86_INS_KTESTQ: ktestq */ 0, { 0 } }, { /* X86_KTESTWrr, X86_INS_KTESTW: ktestw */ 0, { 0 } }, { /* X86_KUNPCKBWrr, X86_INS_KUNPCKBW: kunpckbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KUNPCKDQrr, X86_INS_KUNPCKDQ: kunpckdq */ 0, { 0 } }, { /* X86_KUNPCKWDrr, X86_INS_KUNPCKWD: kunpckwd */ 0, { 0 } }, { /* X86_KXNORBrr, X86_INS_KXNORB: kxnorb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXNORDrr, X86_INS_KXNORD: kxnord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXNORQrr, X86_INS_KXNORQ: kxnorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXNORWrr, X86_INS_KXNORW: kxnorw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXORBrr, X86_INS_KXORB: kxorb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXORDrr, X86_INS_KXORD: kxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXORQrr, X86_INS_KXORQ: kxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_KXORWrr, X86_INS_KXORW: kxorw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_LAHF, X86_INS_LAHF: lahf */ 0, { 0 } }, { /* X86_LAR16rm, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR16rr, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR32rm, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR32rr, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR64rm, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR64rr, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LDDQUrm, X86_INS_LDDQU: lddqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LDMXCSR, X86_INS_LDMXCSR: ldmxcsr */ 0, { CS_AC_READ, 0 } }, { /* X86_LDS16rm, X86_INS_LDS: lds */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LDS32rm, X86_INS_LDS: lds */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LD_F0, X86_INS_FLDZ: fldz */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_LD_F1, X86_INS_FLD1: fld1 */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_LD_F32m, X86_INS_FLD: fld */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_LD_F64m, X86_INS_FLD: fld */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_LD_F80m, X86_INS_FLD: fld */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_LD_Fp032, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp064, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp080, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp132, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp164, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp180, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp32m, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp32m64, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp32m80, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp64m, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp64m80, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Fp80m, X86_INS_FLD: fld */ 0, { 0 } }, { /* X86_LD_Frr, X86_INS_FLD: fld */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_LEA16r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LEA32r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LEA64_32r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LEA64r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LEAVE, X86_INS_LEAVE: leave */ 0, { 0 } }, { /* X86_LEAVE64, X86_INS_LEAVE: leave */ 0, { 0 } }, { /* X86_LES16rm, X86_INS_LES: les */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LES32rm, X86_INS_LES: les */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LFENCE, X86_INS_LFENCE: lfence */ 0, { 0 } }, { /* X86_LFS16rm, X86_INS_LFS: lfs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LFS32rm, X86_INS_LFS: lfs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LFS64rm, X86_INS_LFS: lfs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LGDT16m, X86_INS_LGDT: lgdt */ 0, { CS_AC_READ, 0 } }, { /* X86_LGDT32m, X86_INS_LGDT: lgdt */ 0, { CS_AC_READ, 0 } }, { /* X86_LGDT64m, X86_INS_LGDT: lgdt */ 0, { CS_AC_READ, 0 } }, { /* X86_LGS16rm, X86_INS_LGS: lgs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LGS32rm, X86_INS_LGS: lgs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LGS64rm, X86_INS_LGS: lgs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LIDT16m, X86_INS_LIDT: lidt */ 0, { CS_AC_READ, 0 } }, { /* X86_LIDT32m, X86_INS_LIDT: lidt */ 0, { CS_AC_READ, 0 } }, { /* X86_LIDT64m, X86_INS_LIDT: lidt */ 0, { CS_AC_READ, 0 } }, { /* X86_LLDT16m, X86_INS_LLDT: lldt */ 0, { CS_AC_READ, 0 } }, { /* X86_LLDT16r, X86_INS_LLDT: lldt */ 0, { CS_AC_READ, 0 } }, { /* X86_LLWPCB, X86_INS_LLWPCB: llwpcb */ 0, { 0 } }, { /* X86_LLWPCB64, X86_INS_LLWPCB: llwpcb */ 0, { 0 } }, { /* X86_LMSW16m, X86_INS_LMSW: lmsw */ 0, { CS_AC_READ, 0 } }, { /* X86_LMSW16r, X86_INS_LMSW: lmsw */ 0, { CS_AC_READ, 0 } }, { /* X86_LOCK_PREFIX, X86_INS_LOCK: lock */ 0, { 0 } }, { /* X86_LODSB, X86_INS_LODSB: lodsb */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LODSL, X86_INS_LODSD: lodsd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LODSQ, X86_INS_LODSQ: lodsq */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LODSW, X86_INS_LODSW: lodsw */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LOOP, X86_INS_LOOP: loop */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LOOPE, X86_INS_LOOPE: loope */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_LOOPNE, X86_INS_LOOPNE: loopne */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_LRETIL, X86_INS_RETF: retf */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LRETIQ, X86_INS_RETFQ: retfq */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LRETIW, X86_INS_RETF: retf */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LRETL, X86_INS_RETF: retf */ 0, { 0 } }, { /* X86_LRETQ, X86_INS_RETFQ: retfq */ 0, { 0 } }, { /* X86_LRETW, X86_INS_RETF: retf */ 0, { 0 } }, { /* X86_LSL16rm, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL16rr, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL32rm, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL32rr, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL64rm, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL64rr, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSS16rm, X86_INS_LSS: lss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSS32rm, X86_INS_LSS: lss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSS64rm, X86_INS_LSS: lss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LTRm, X86_INS_LTR: ltr */ 0, { CS_AC_READ, 0 } }, { /* X86_LTRr, X86_INS_LTR: ltr */ 0, { CS_AC_READ, 0 } }, { /* X86_LWPINS32rmi, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPINS32rri, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPINS64rmi, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPINS64rri, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPVAL32rmi, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LWPVAL32rri, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LWPVAL64rmi, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LWPVAL64rri, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LZCNT16rm, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT16rr, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT32rm, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT32rr, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT64rm, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT64rr, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MASKMOVDQU, X86_INS_MASKMOVDQU: maskmovdqu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MASKMOVDQU64, X86_INS_MASKMOVDQU: maskmovdqu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MAXCPDrm, X86_INS_MAXPD: maxpd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCPDrr, X86_INS_MAXPD: maxpd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCPSrm, X86_INS_MAXPS: maxps $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCPSrr, X86_INS_MAXPS: maxps $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCSDrm, X86_INS_MAXSD: maxsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCSDrr, X86_INS_MAXSD: maxsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCSSrm, X86_INS_MAXSS: maxss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXCSSrr, X86_INS_MAXSS: maxss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXPDrm, X86_INS_MAXPD: maxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXPDrr, X86_INS_MAXPD: maxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXPSrm, X86_INS_MAXPS: maxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXPSrr, X86_INS_MAXPS: maxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXSDrm, X86_INS_MAXSD: maxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXSDrm_Int, X86_INS_MAXSD: maxsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MAXSDrr, X86_INS_MAXSD: maxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXSDrr_Int, X86_INS_MAXSD: maxsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXSSrm, X86_INS_MAXSS: maxss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXSSrm_Int, X86_INS_MAXSS: maxss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MAXSSrr, X86_INS_MAXSS: maxss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MAXSSrr_Int, X86_INS_MAXSS: maxss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MFENCE, X86_INS_MFENCE: mfence */ 0, { 0 } }, { /* X86_MINCPDrm, X86_INS_MINPD: minpd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCPDrr, X86_INS_MINPD: minpd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCPSrm, X86_INS_MINPS: minps $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCPSrr, X86_INS_MINPS: minps $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCSDrm, X86_INS_MINSD: minsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCSDrr, X86_INS_MINSD: minsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCSSrm, X86_INS_MINSS: minss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINCSSrr, X86_INS_MINSS: minss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINPDrm, X86_INS_MINPD: minpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINPDrr, X86_INS_MINPD: minpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINPSrm, X86_INS_MINPS: minps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINPSrr, X86_INS_MINPS: minps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINSDrm, X86_INS_MINSD: minsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINSDrm_Int, X86_INS_MINSD: minsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MINSDrr, X86_INS_MINSD: minsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINSDrr_Int, X86_INS_MINSD: minsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINSSrm, X86_INS_MINSS: minss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINSSrm_Int, X86_INS_MINSS: minss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MINSSrr, X86_INS_MINSS: minss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MINSSrr_Int, X86_INS_MINSS: minss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPD2PIirm, X86_INS_CVTPD2PI: cvtpd2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPD2PIirr, X86_INS_CVTPD2PI: cvtpd2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPI2PDirm, X86_INS_CVTPI2PD: cvtpi2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPI2PDirr, X86_INS_CVTPI2PD: cvtpi2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPI2PSirm, X86_INS_CVTPI2PS: cvtpi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPI2PSirr, X86_INS_CVTPI2PS: cvtpi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPS2PIirm, X86_INS_CVTPS2PI: cvtps2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTPS2PIirr, X86_INS_CVTPS2PI: cvtps2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTTPD2PIirm, X86_INS_CVTTPD2PI: cvttpd2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTTPD2PIirr, X86_INS_CVTTPD2PI: cvttpd2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTTPS2PIirm, X86_INS_CVTTPS2PI: cvttps2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_CVTTPS2PIirr, X86_INS_CVTTPS2PI: cvttps2pi */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_EMMS, X86_INS_EMMS: emms */ 0, { 0 } }, { /* X86_MMX_MASKMOVQ, X86_INS_MASKMOVQ: maskmovq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MMX_MASKMOVQ64, X86_INS_MASKMOVQ: maskmovq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64from64rm, X86_INS_MOVD: movd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64from64rr, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64grr, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64mr, X86_INS_MOVD: movd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64rm, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64rr, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64to64rm, X86_INS_MOVD: movd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVD64to64rr, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVDQ2Qrr, X86_INS_MOVDQ2Q: movdq2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVFR642Qrr, X86_INS_MOVDQ2Q: movdq2q $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVNTQmr, X86_INS_MOVNTQ: movntq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MMX_MOVQ2DQrr, X86_INS_MOVQ2DQ: movq2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVQ2FR64rr, X86_INS_MOVQ2DQ: movq2dq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVQ64mr, X86_INS_MOVQ: movq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MMX_MOVQ64rm, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVQ64rr, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_MOVQ64rr_REV, X86_INS_MOVQ: movq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PABSBrm, X86_INS_PABSB: pabsb */ 0, { 0 } }, { /* X86_MMX_PABSBrr, X86_INS_PABSB: pabsb */ 0, { 0 } }, { /* X86_MMX_PABSDrm, X86_INS_PABSD: pabsd */ 0, { 0 } }, { /* X86_MMX_PABSDrr, X86_INS_PABSD: pabsd */ 0, { 0 } }, { /* X86_MMX_PABSWrm, X86_INS_PABSW: pabsw */ 0, { 0 } }, { /* X86_MMX_PABSWrr, X86_INS_PABSW: pabsw */ 0, { 0 } }, { /* X86_MMX_PACKSSDWirm, X86_INS_PACKSSDW: packssdw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PACKSSDWirr, X86_INS_PACKSSDW: packssdw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PACKSSWBirm, X86_INS_PACKSSWB: packsswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PACKSSWBirr, X86_INS_PACKSSWB: packsswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PACKUSWBirm, X86_INS_PACKUSWB: packuswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PACKUSWBirr, X86_INS_PACKUSWB: packuswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDBirm, X86_INS_PADDB: paddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDBirr, X86_INS_PADDB: paddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDDirm, X86_INS_PADDD: paddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDDirr, X86_INS_PADDD: paddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDQirm, X86_INS_PADDQ: paddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDQirr, X86_INS_PADDQ: paddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDSBirm, X86_INS_PADDSB: paddsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDSBirr, X86_INS_PADDSB: paddsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDSWirm, X86_INS_PADDSW: paddsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDSWirr, X86_INS_PADDSW: paddsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDUSBirm, X86_INS_PADDUSB: paddusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDUSBirr, X86_INS_PADDUSB: paddusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDUSWirm, X86_INS_PADDUSW: paddusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDUSWirr, X86_INS_PADDUSW: paddusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDWirm, X86_INS_PADDW: paddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PADDWirr, X86_INS_PADDW: paddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PALIGNRrmi, X86_INS_PALIGNR: palignr */ 0, { 0 } }, { /* X86_MMX_PALIGNRrri, X86_INS_PALIGNR: palignr */ 0, { 0 } }, { /* X86_MMX_PANDNirm, X86_INS_PANDN: pandn */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PANDNirr, X86_INS_PANDN: pandn */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PANDirm, X86_INS_PAND: pand */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PANDirr, X86_INS_PAND: pand */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PAVGBirm, X86_INS_PAVGB: pavgb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PAVGBirr, X86_INS_PAVGB: pavgb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PAVGWirm, X86_INS_PAVGW: pavgw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PAVGWirr, X86_INS_PAVGW: pavgw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPEQBirm, X86_INS_PCMPEQB: pcmpeqb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPEQBirr, X86_INS_PCMPEQB: pcmpeqb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPEQDirm, X86_INS_PCMPEQD: pcmpeqd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPEQDirr, X86_INS_PCMPEQD: pcmpeqd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPEQWirm, X86_INS_PCMPEQW: pcmpeqw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPEQWirr, X86_INS_PCMPEQW: pcmpeqw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPGTBirm, X86_INS_PCMPGTB: pcmpgtb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPGTBirr, X86_INS_PCMPGTB: pcmpgtb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPGTDirm, X86_INS_PCMPGTD: pcmpgtd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPGTDirr, X86_INS_PCMPGTD: pcmpgtd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPGTWirm, X86_INS_PCMPGTW: pcmpgtw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PCMPGTWirr, X86_INS_PCMPGTW: pcmpgtw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PEXTRWrr, X86_INS_PEXTRW: pextrw */ 0, { 0 } }, { /* X86_MMX_PHADDDrm, X86_INS_PHADDD: phaddd */ 0, { 0 } }, { /* X86_MMX_PHADDDrr, X86_INS_PHADDD: phaddd */ 0, { 0 } }, { /* X86_MMX_PHADDSWrm, X86_INS_PHADDSW: phaddsw */ 0, { 0 } }, { /* X86_MMX_PHADDSWrr, X86_INS_PHADDSW: phaddsw */ 0, { 0 } }, { /* X86_MMX_PHADDWrm, X86_INS_PHADDW: phaddw */ 0, { 0 } }, { /* X86_MMX_PHADDWrr, X86_INS_PHADDW: phaddw */ 0, { 0 } }, { /* X86_MMX_PHSUBDrm, X86_INS_PHSUBD: phsubd */ 0, { 0 } }, { /* X86_MMX_PHSUBDrr, X86_INS_PHSUBD: phsubd */ 0, { 0 } }, { /* X86_MMX_PHSUBSWrm, X86_INS_PHSUBSW: phsubsw */ 0, { 0 } }, { /* X86_MMX_PHSUBSWrr, X86_INS_PHSUBSW: phsubsw */ 0, { 0 } }, { /* X86_MMX_PHSUBWrm, X86_INS_PHSUBW: phsubw */ 0, { 0 } }, { /* X86_MMX_PHSUBWrr, X86_INS_PHSUBW: phsubw */ 0, { 0 } }, { /* X86_MMX_PINSRWrm, X86_INS_PINSRW: pinsrw */ 0, { 0 } }, { /* X86_MMX_PINSRWrr, X86_INS_PINSRW: pinsrw */ 0, { 0 } }, { /* X86_MMX_PMADDUBSWrm, X86_INS_PMADDUBSW: pmaddubsw */ 0, { 0 } }, { /* X86_MMX_PMADDUBSWrr, X86_INS_PMADDUBSW: pmaddubsw */ 0, { 0 } }, { /* X86_MMX_PMADDWDirm, X86_INS_PMADDWD: pmaddwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMADDWDirr, X86_INS_PMADDWD: pmaddwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMAXSWirm, X86_INS_PMAXSW: pmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMAXSWirr, X86_INS_PMAXSW: pmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMAXUBirm, X86_INS_PMAXUB: pmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMAXUBirr, X86_INS_PMAXUB: pmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMINSWirm, X86_INS_PMINSW: pminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMINSWirr, X86_INS_PMINSW: pminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMINUBirm, X86_INS_PMINUB: pminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMINUBirr, X86_INS_PMINUB: pminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMOVMSKBrr, X86_INS_PMOVMSKB: pmovmskb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULHRSWrm, X86_INS_PMULHRSW: pmulhrsw */ 0, { 0 } }, { /* X86_MMX_PMULHRSWrr, X86_INS_PMULHRSW: pmulhrsw */ 0, { 0 } }, { /* X86_MMX_PMULHUWirm, X86_INS_PMULHUW: pmulhuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULHUWirr, X86_INS_PMULHUW: pmulhuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULHWirm, X86_INS_PMULHW: pmulhw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULHWirr, X86_INS_PMULHW: pmulhw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULLWirm, X86_INS_PMULLW: pmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULLWirr, X86_INS_PMULLW: pmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULUDQirm, X86_INS_PMULUDQ: pmuludq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PMULUDQirr, X86_INS_PMULUDQ: pmuludq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PORirm, X86_INS_POR: por */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PORirr, X86_INS_POR: por */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSADBWirm, X86_INS_PSADBW: psadbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSADBWirr, X86_INS_PSADBW: psadbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSHUFBrm, X86_INS_PSHUFB: pshufb */ 0, { 0 } }, { /* X86_MMX_PSHUFBrr, X86_INS_PSHUFB: pshufb */ 0, { 0 } }, { /* X86_MMX_PSHUFWmi, X86_INS_PSHUFW: pshufw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSHUFWri, X86_INS_PSHUFW: pshufw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSIGNBrm, X86_INS_PSIGNB: psignb */ 0, { 0 } }, { /* X86_MMX_PSIGNBrr, X86_INS_PSIGNB: psignb */ 0, { 0 } }, { /* X86_MMX_PSIGNDrm, X86_INS_PSIGND: psignd */ 0, { 0 } }, { /* X86_MMX_PSIGNDrr, X86_INS_PSIGND: psignd */ 0, { 0 } }, { /* X86_MMX_PSIGNWrm, X86_INS_PSIGNW: psignw */ 0, { 0 } }, { /* X86_MMX_PSIGNWrr, X86_INS_PSIGNW: psignw */ 0, { 0 } }, { /* X86_MMX_PSLLDri, X86_INS_PSLLD: pslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSLLDrm, X86_INS_PSLLD: pslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSLLDrr, X86_INS_PSLLD: pslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSLLQri, X86_INS_PSLLQ: psllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSLLQrm, X86_INS_PSLLQ: psllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSLLQrr, X86_INS_PSLLQ: psllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSLLWri, X86_INS_PSLLW: psllw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSLLWrm, X86_INS_PSLLW: psllw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSLLWrr, X86_INS_PSLLW: psllw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRADri, X86_INS_PSRAD: psrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSRADrm, X86_INS_PSRAD: psrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRADrr, X86_INS_PSRAD: psrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRAWri, X86_INS_PSRAW: psraw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSRAWrm, X86_INS_PSRAW: psraw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRAWrr, X86_INS_PSRAW: psraw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRLDri, X86_INS_PSRLD: psrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSRLDrm, X86_INS_PSRLD: psrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRLDrr, X86_INS_PSRLD: psrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRLQri, X86_INS_PSRLQ: psrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSRLQrm, X86_INS_PSRLQ: psrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRLQrr, X86_INS_PSRLQ: psrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRLWri, X86_INS_PSRLW: psrlw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MMX_PSRLWrm, X86_INS_PSRLW: psrlw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSRLWrr, X86_INS_PSRLW: psrlw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBBirm, X86_INS_PSUBB: psubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBBirr, X86_INS_PSUBB: psubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBDirm, X86_INS_PSUBD: psubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBDirr, X86_INS_PSUBD: psubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBQirm, X86_INS_PSUBQ: psubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBQirr, X86_INS_PSUBQ: psubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBSBirm, X86_INS_PSUBSB: psubsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBSBirr, X86_INS_PSUBSB: psubsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBSWirm, X86_INS_PSUBSW: psubsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBSWirr, X86_INS_PSUBSW: psubsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBUSBirm, X86_INS_PSUBUSB: psubusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBUSBirr, X86_INS_PSUBUSB: psubusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBUSWirm, X86_INS_PSUBUSW: psubusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBUSWirr, X86_INS_PSUBUSW: psubusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBWirm, X86_INS_PSUBW: psubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PSUBWirr, X86_INS_PSUBW: psubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKHBWirm, X86_INS_PUNPCKHBW: punpckhbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKHBWirr, X86_INS_PUNPCKHBW: punpckhbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKHDQirm, X86_INS_PUNPCKHDQ: punpckhdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKHDQirr, X86_INS_PUNPCKHDQ: punpckhdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKHWDirm, X86_INS_PUNPCKHWD: punpckhwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKHWDirr, X86_INS_PUNPCKHWD: punpckhwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKLBWirm, X86_INS_PUNPCKLBW: punpcklbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKLBWirr, X86_INS_PUNPCKLBW: punpcklbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKLDQirm, X86_INS_PUNPCKLDQ: punpckldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKLDQirr, X86_INS_PUNPCKLDQ: punpckldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKLWDirm, X86_INS_PUNPCKLWD: punpcklwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PUNPCKLWDirr, X86_INS_PUNPCKLWD: punpcklwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PXORirm, X86_INS_PXOR: pxor */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MMX_PXORirr, X86_INS_PXOR: pxor */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MONITORXrrr, X86_INS_MONITORX: monitorx */ 0, { 0 } }, { /* X86_MONITORrrr, X86_INS_MONITOR: monitor */ 0, { 0 } }, { /* X86_MONTMUL, X86_INS_MONTMUL: montmul */ 0, { 0 } }, { /* X86_MOV16ao16, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16mi, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV16mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ms, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16o16a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ri, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV16ri_alt, X86_INS_MOV: mov{w} $dst $src */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV16rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16rr_REV, X86_INS_MOV: mov{w} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16rs, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16sm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16sr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ao16, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32cr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32dr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32mi, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV32mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32o16a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rc, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rd, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ri, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV32ri_alt, X86_INS_MOV: mov{l} $dst $src */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV32rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rr_REV, X86_INS_MOV: mov{l} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rs, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32sr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64cr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64dr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64mi32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV64mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rc, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rd, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64ri, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV64ri32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV64rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rr_REV, X86_INS_MOV: mov{q} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rs, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64sr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64toPQIrm, X86_INS_MOVQ: mov{d|q} {$src $dst|$dst $src} */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64toPQIrr, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64toSDrm, X86_INS_MOVQ: movq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64toSDrr, X86_INS_MOVQ: mov{d|q} {$src $dst|$dst $src} */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ao16, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8mi, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV8mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8mr_NOREX, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8o16a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ri, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV8ri_alt, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV8rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rm_NOREX, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rr_NOREX, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rr_REV, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPDmr, X86_INS_MOVAPD: movapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPDrm, X86_INS_MOVAPD: movapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPDrr, X86_INS_MOVAPD: movapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPDrr_REV, X86_INS_MOVAPD: movapd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPSmr, X86_INS_MOVAPS: movaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPSrm, X86_INS_MOVAPS: movaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPSrr, X86_INS_MOVAPS: movaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVAPSrr_REV, X86_INS_MOVAPS: movaps $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE16mr, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE16rm, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE32mr, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE32rm, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE64mr, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE64rm, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDDUPrm, X86_INS_MOVDDUP: movddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDDUPrr, X86_INS_MOVDDUP: movddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDI2PDIrm, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDI2PDIrr, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDI2SSrm, X86_INS_MOVD: movd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDI2SSrr, X86_INS_MOVD: movd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDIR64B16, X86_INS_MOVDIR64B: movdir64b */ 0, { 0 } }, { /* X86_MOVDIR64B32, X86_INS_MOVDIR64B: movdir64b */ 0, { 0 } }, { /* X86_MOVDIR64B64, X86_INS_MOVDIR64B: movdir64b */ 0, { 0 } }, { /* X86_MOVDIRI32, X86_INS_MOVDIRI: movdiri */ 0, { 0 } }, { /* X86_MOVDIRI64, X86_INS_MOVDIRI: movdiri */ 0, { 0 } }, { /* X86_MOVDQAmr, X86_INS_MOVDQA: movdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQArm, X86_INS_MOVDQA: movdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQArr, X86_INS_MOVDQA: movdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQArr_REV, X86_INS_MOVDQA: movdqa $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQUmr, X86_INS_MOVDQU: movdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQUrm, X86_INS_MOVDQU: movdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQUrr, X86_INS_MOVDQU: movdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDQUrr_REV, X86_INS_MOVDQU: movdqu $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVHLPSrr, X86_INS_MOVHLPS: movhlps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVHPDmr, X86_INS_MOVHPD: movhpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVHPDrm, X86_INS_MOVHPD: movhpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVHPSmr, X86_INS_MOVHPS: movhps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVHPSrm, X86_INS_MOVHPS: movhps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVLHPSrr, X86_INS_MOVLHPS: movlhps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVLPDmr, X86_INS_MOVLPD: movlpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVLPDrm, X86_INS_MOVLPD: movlpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVLPSmr, X86_INS_MOVLPS: movlps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVLPSrm, X86_INS_MOVLPS: movlps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVMSKPDrr, X86_INS_MOVMSKPD: movmskpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVMSKPSrr, X86_INS_MOVMSKPS: movmskps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVNTDQArm, X86_INS_MOVNTDQA: movntdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVNTDQmr, X86_INS_MOVNTDQ: movntdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVNTI_64mr, X86_INS_MOVNTI: movnti */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVNTImr, X86_INS_MOVNTI: movnti */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVNTPDmr, X86_INS_MOVNTPD: movntpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVNTPSmr, X86_INS_MOVNTPS: movntps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVNTSD, X86_INS_MOVNTSD: movntsd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVNTSS, X86_INS_MOVNTSS: movntss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVPDI2DImr, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVPDI2DIrr, X86_INS_MOVD: movd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVPQI2QImr, X86_INS_MOVQ: movq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVPQI2QIrr, X86_INS_MOVQ: movq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVPQIto64mr, X86_INS_MOVQ: movq */ 0, { 0 } }, { /* X86_MOVPQIto64rr, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVQI2PQIrm, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSB, X86_INS_MOVSB: movsb */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSDmr, X86_INS_MOVSD: movsd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSDrm, X86_INS_MOVSD: movsd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSDrr, X86_INS_MOVSD: movsd */ X86_EFLAGS_TEST_DF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSDrr_REV, X86_INS_MOVSD: movsd $dst $src2 */ X86_EFLAGS_TEST_DF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSDto64mr, X86_INS_MOVQ: movq $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVSDto64rr, X86_INS_MOVQ: mov{d|q} {$src $dst|$dst $src} */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSHDUPrm, X86_INS_MOVSHDUP: movshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSHDUPrr, X86_INS_MOVSHDUP: movshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSL, X86_INS_MOVSD: movsd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSLDUPrm, X86_INS_MOVSLDUP: movsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSLDUPrr, X86_INS_MOVSLDUP: movsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSQ, X86_INS_MOVSQ: movsq */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSS2DImr, X86_INS_MOVD: movd $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVSS2DIrr, X86_INS_MOVD: movd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSSmr, X86_INS_MOVSS: movss */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSSrm, X86_INS_MOVSS: movss */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSSrr, X86_INS_MOVSS: movss */ X86_EFLAGS_TEST_DF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSSrr_REV, X86_INS_MOVSS: movss $dst $src2 */ X86_EFLAGS_TEST_DF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSW, X86_INS_MOVSW: movsw */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX16rm16, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX16rm8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX16rr16, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX16rr8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rm16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rm8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rm8_NOREX, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX32rr16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rr8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rr8_NOREX, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX64rm16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rm32, X86_INS_MOVSXD: movsxd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rm8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rr16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rr32, X86_INS_MOVSXD: movsxd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rr8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVUPDmr, X86_INS_MOVUPD: movupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVUPDrm, X86_INS_MOVUPD: movupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVUPDrr, X86_INS_MOVUPD: movupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVUPDrr_REV, X86_INS_MOVUPD: movupd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVUPSmr, X86_INS_MOVUPS: movups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MOVUPSrm, X86_INS_MOVUPS: movups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVUPSrr, X86_INS_MOVUPS: movups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVUPSrr_REV, X86_INS_MOVUPS: movups $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZPQILo2PQIrr, X86_INS_MOVQ: movq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX16rm16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX16rm8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX16rr16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX16rr8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rm16, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rm8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rm8_NOREX, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX32rr16, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rr8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rr8_NOREX, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rm16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rm8, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rr16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rr8, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MPSADBWrmi, X86_INS_MPSADBW: mpsadbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_MPSADBWrri, X86_INS_MPSADBW: mpsadbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_MUL16m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL16r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL32m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL32r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL64m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL64r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL8m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL8r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MULPDrm, X86_INS_MULPD: mulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULPDrr, X86_INS_MULPD: mulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULPSrm, X86_INS_MULPS: mulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULPSrr, X86_INS_MULPS: mulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULSDrm, X86_INS_MULSD: mulsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULSDrm_Int, X86_INS_MULSD: mulsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MULSDrr, X86_INS_MULSD: mulsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULSDrr_Int, X86_INS_MULSD: mulsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULSSrm, X86_INS_MULSS: mulss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULSSrm_Int, X86_INS_MULSS: mulss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MULSSrr, X86_INS_MULSS: mulss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULSSrr_Int, X86_INS_MULSS: mulss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX32rm, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX32rr, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX64rm, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX64rr, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MUL_F32m, X86_INS_FMUL: fmul */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_MUL_F64m, X86_INS_FMUL: fmul */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_MUL_FI16m, X86_INS_FIMUL: fimul */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_MUL_FI32m, X86_INS_FIMUL: fimul */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_MUL_FPrST0, X86_INS_FMULP: fmulp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_MUL_FST0r, X86_INS_FMUL: fmul */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_MUL_Fp32, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp32m, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp64, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp64m, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp64m32, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp80, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp80m32, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_Fp80m64, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FpI16m32, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FpI16m64, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FpI16m80, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FpI32m32, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FpI32m64, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FpI32m80, X86_INS_FMUL: fmul */ 0, { 0 } }, { /* X86_MUL_FrST0, X86_INS_FMUL: fmul */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_MWAITXrrr, X86_INS_MWAITX: mwaitx */ 0, { 0 } }, { /* X86_MWAITrr, X86_INS_MWAIT: mwait */ 0, { 0 } }, { /* X86_NEG16m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG16r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG32m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG32r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG64m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG64r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG8m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG8r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOOP, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOP18_16m4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16m5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16m6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16m7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP19rr, X86_INS_NOP: nop */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_NOOPL, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPL_19, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPL_1d, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPL_1e, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPLr, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOPQ, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOPQr, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOPW, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_19, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_1c, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_1d, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_1e, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPWr, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOT16m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT16r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT32m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT32r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT64m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT64r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT8m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT8r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_OR16i16, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16mi, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16mi8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR16ri, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16ri8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR16rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR16rr_REV, X86_INS_OR: or{w} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32i32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32mi, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32mi8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32ri, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32ri8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32rr_REV, X86_INS_OR: or{l} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64i32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64mi32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64mi8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64ri32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64ri8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64rr_REV, X86_INS_OR: or{q} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8i8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8mi, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8mi8, X86_INS_OR: or{b} $dst $src */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8ri, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8ri8, X86_INS_OR: or{b} $src1 $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8rr_REV, X86_INS_OR: or{b} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ORPDrm, X86_INS_ORPD: orpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ORPDrr, X86_INS_ORPD: orpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ORPSrm, X86_INS_ORPS: orps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ORPSrr, X86_INS_ORPS: orps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OUT16ir, X86_INS_OUT: out */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_OUT16rr, X86_INS_OUT: out */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_OUT32ir, X86_INS_OUT: out */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_OUT32rr, X86_INS_OUT: out */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_OUT8ir, X86_INS_OUT: out */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_OUT8rr, X86_INS_OUT: out */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_OUTSB, X86_INS_OUTSB: outsb */ X86_EFLAGS_TEST_DF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_OUTSL, X86_INS_OUTSD: outsd */ X86_EFLAGS_TEST_DF, { CS_AC_IGNORE, 0 } }, { /* X86_OUTSW, X86_INS_OUTSW: outsw */ X86_EFLAGS_TEST_DF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PABSBrm, X86_INS_PABSB: pabsb */ 0, { 0 } }, { /* X86_PABSBrr, X86_INS_PABSB: pabsb */ 0, { 0 } }, { /* X86_PABSDrm, X86_INS_PABSD: pabsd */ 0, { 0 } }, { /* X86_PABSDrr, X86_INS_PABSD: pabsd */ 0, { 0 } }, { /* X86_PABSWrm, X86_INS_PABSW: pabsw */ 0, { 0 } }, { /* X86_PABSWrr, X86_INS_PABSW: pabsw */ 0, { 0 } }, { /* X86_PACKSSDWrm, X86_INS_PACKSSDW: packssdw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKSSDWrr, X86_INS_PACKSSDW: packssdw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKSSWBrm, X86_INS_PACKSSWB: packsswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKSSWBrr, X86_INS_PACKSSWB: packsswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKUSDWrm, X86_INS_PACKUSDW: packusdw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKUSDWrr, X86_INS_PACKUSDW: packusdw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKUSWBrm, X86_INS_PACKUSWB: packuswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PACKUSWBrr, X86_INS_PACKUSWB: packuswb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDBrm, X86_INS_PADDB: paddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDBrr, X86_INS_PADDB: paddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDDrm, X86_INS_PADDD: paddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDDrr, X86_INS_PADDD: paddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDQrm, X86_INS_PADDQ: paddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDQrr, X86_INS_PADDQ: paddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDSBrm, X86_INS_PADDSB: paddsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDSBrr, X86_INS_PADDSB: paddsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDSWrm, X86_INS_PADDSW: paddsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDSWrr, X86_INS_PADDSW: paddsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDUSBrm, X86_INS_PADDUSB: paddusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDUSBrr, X86_INS_PADDUSB: paddusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDUSWrm, X86_INS_PADDUSW: paddusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDUSWrr, X86_INS_PADDUSW: paddusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDWrm, X86_INS_PADDW: paddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PADDWrr, X86_INS_PADDW: paddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PALIGNRrmi, X86_INS_PALIGNR: palignr */ 0, { 0 } }, { /* X86_PALIGNRrri, X86_INS_PALIGNR: palignr */ 0, { 0 } }, { /* X86_PANDNrm, X86_INS_PANDN: pandn */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PANDNrr, X86_INS_PANDN: pandn */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PANDrm, X86_INS_PAND: pand */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PANDrr, X86_INS_PAND: pand */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PAUSE, X86_INS_PAUSE: pause */ 0, { 0 } }, { /* X86_PAVGBrm, X86_INS_PAVGB: pavgb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PAVGBrr, X86_INS_PAVGB: pavgb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PAVGUSBrm, X86_INS_PAVGUSB: pavgusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PAVGUSBrr, X86_INS_PAVGUSB: pavgusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PAVGWrm, X86_INS_PAVGW: pavgw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PAVGWrr, X86_INS_PAVGW: pavgw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PBLENDVBrm0, X86_INS_PBLENDVB: pblendvb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PBLENDVBrr0, X86_INS_PBLENDVB: pblendvb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PBLENDWrmi, X86_INS_PBLENDW: pblendw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PBLENDWrri, X86_INS_PBLENDW: pblendw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCLMULQDQrm, X86_INS_PCLMULQDQ: pclmulqdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCLMULQDQrr, X86_INS_PCLMULQDQ: pclmulqdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCMPEQBrm, X86_INS_PCMPEQB: pcmpeqb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQBrr, X86_INS_PCMPEQB: pcmpeqb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQDrm, X86_INS_PCMPEQD: pcmpeqd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQDrr, X86_INS_PCMPEQD: pcmpeqd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQQrm, X86_INS_PCMPEQQ: pcmpeqq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQQrr, X86_INS_PCMPEQQ: pcmpeqq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQWrm, X86_INS_PCMPEQW: pcmpeqw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPEQWrr, X86_INS_PCMPEQW: pcmpeqw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPESTRIrm, X86_INS_PCMPESTRI: pcmpestri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCMPESTRIrr, X86_INS_PCMPESTRI: pcmpestri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCMPESTRMrm, X86_INS_PCMPESTRM: pcmpestrm */ 0, { 0 } }, { /* X86_PCMPESTRMrr, X86_INS_PCMPESTRM: pcmpestrm */ 0, { 0 } }, { /* X86_PCMPGTBrm, X86_INS_PCMPGTB: pcmpgtb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTBrr, X86_INS_PCMPGTB: pcmpgtb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTDrm, X86_INS_PCMPGTD: pcmpgtd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTDrr, X86_INS_PCMPGTD: pcmpgtd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTQrm, X86_INS_PCMPGTQ: pcmpgtq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTQrr, X86_INS_PCMPGTQ: pcmpgtq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTWrm, X86_INS_PCMPGTW: pcmpgtw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPGTWrr, X86_INS_PCMPGTW: pcmpgtw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PCMPISTRIrm, X86_INS_PCMPISTRI: pcmpistri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCMPISTRIrr, X86_INS_PCMPISTRI: pcmpistri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCMPISTRMrm, X86_INS_PCMPISTRM: pcmpistrm */ 0, { 0 } }, { /* X86_PCMPISTRMrr, X86_INS_PCMPISTRM: pcmpistrm */ 0, { 0 } }, { /* X86_PCONFIG, X86_INS_PCONFIG: pconfig */ 0, { 0 } }, { /* X86_PDEP32rm, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PDEP32rr, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PDEP64rm, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PDEP64rr, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT32rm, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT32rr, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT64rm, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT64rr, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXTRBmr, X86_INS_PEXTRB: pextrb */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRBrr, X86_INS_PEXTRB: pextrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRDmr, X86_INS_PEXTRD: pextrd */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRDrr, X86_INS_PEXTRD: pextrd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRQmr, X86_INS_PEXTRQ: pextrq */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRQrr, X86_INS_PEXTRQ: pextrq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRWmr, X86_INS_PEXTRW: pextrw */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PEXTRWrr, X86_INS_PEXTRW: pextrw */ 0, { 0 } }, { /* X86_PEXTRWrr_REV, X86_INS_PEXTRW: pextrw $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PF2IDrm, X86_INS_PF2ID: pf2id */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PF2IDrr, X86_INS_PF2ID: pf2id */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PF2IWrm, X86_INS_PF2IW: pf2iw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PF2IWrr, X86_INS_PF2IW: pf2iw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFACCrm, X86_INS_PFACC: pfacc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFACCrr, X86_INS_PFACC: pfacc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFADDrm, X86_INS_PFADD: pfadd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFADDrr, X86_INS_PFADD: pfadd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFCMPEQrm, X86_INS_PFCMPEQ: pfcmpeq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFCMPEQrr, X86_INS_PFCMPEQ: pfcmpeq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFCMPGErm, X86_INS_PFCMPGE: pfcmpge */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFCMPGErr, X86_INS_PFCMPGE: pfcmpge */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFCMPGTrm, X86_INS_PFCMPGT: pfcmpgt */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFCMPGTrr, X86_INS_PFCMPGT: pfcmpgt */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFMAXrm, X86_INS_PFMAX: pfmax */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFMAXrr, X86_INS_PFMAX: pfmax */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFMINrm, X86_INS_PFMIN: pfmin */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFMINrr, X86_INS_PFMIN: pfmin */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFMULrm, X86_INS_PFMUL: pfmul */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFMULrr, X86_INS_PFMUL: pfmul */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFNACCrm, X86_INS_PFNACC: pfnacc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFNACCrr, X86_INS_PFNACC: pfnacc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFPNACCrm, X86_INS_PFPNACC: pfpnacc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFPNACCrr, X86_INS_PFPNACC: pfpnacc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRCPIT1rm, X86_INS_PFRCPIT1: pfrcpit1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRCPIT1rr, X86_INS_PFRCPIT1: pfrcpit1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRCPIT2rm, X86_INS_PFRCPIT2: pfrcpit2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRCPIT2rr, X86_INS_PFRCPIT2: pfrcpit2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRCPrm, X86_INS_PFRCP: pfrcp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRCPrr, X86_INS_PFRCP: pfrcp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRSQIT1rm, X86_INS_PFRSQIT1: pfrsqit1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRSQIT1rr, X86_INS_PFRSQIT1: pfrsqit1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRSQRTrm, X86_INS_PFRSQRT: pfrsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFRSQRTrr, X86_INS_PFRSQRT: pfrsqrt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFSUBRrm, X86_INS_PFSUBR: pfsubr */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFSUBRrr, X86_INS_PFSUBR: pfsubr */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFSUBrm, X86_INS_PFSUB: pfsub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PFSUBrr, X86_INS_PFSUB: pfsub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHADDDrm, X86_INS_PHADDD: phaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHADDDrr, X86_INS_PHADDD: phaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHADDSWrm, X86_INS_PHADDSW: phaddsw */ 0, { 0 } }, { /* X86_PHADDSWrr, X86_INS_PHADDSW: phaddsw */ 0, { 0 } }, { /* X86_PHADDWrm, X86_INS_PHADDW: phaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHADDWrr, X86_INS_PHADDW: phaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHMINPOSUWrm, X86_INS_PHMINPOSUW: phminposuw */ 0, { 0 } }, { /* X86_PHMINPOSUWrr, X86_INS_PHMINPOSUW: phminposuw */ 0, { 0 } }, { /* X86_PHSUBDrm, X86_INS_PHSUBD: phsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHSUBDrr, X86_INS_PHSUBD: phsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHSUBSWrm, X86_INS_PHSUBSW: phsubsw */ 0, { 0 } }, { /* X86_PHSUBSWrr, X86_INS_PHSUBSW: phsubsw */ 0, { 0 } }, { /* X86_PHSUBWrm, X86_INS_PHSUBW: phsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PHSUBWrr, X86_INS_PHSUBW: phsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PI2FDrm, X86_INS_PI2FD: pi2fd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PI2FDrr, X86_INS_PI2FD: pi2fd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PI2FWrm, X86_INS_PI2FW: pi2fw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PI2FWrr, X86_INS_PI2FW: pi2fw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PINSRBrm, X86_INS_PINSRB: pinsrb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PINSRBrr, X86_INS_PINSRB: pinsrb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PINSRDrm, X86_INS_PINSRD: pinsrd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PINSRDrr, X86_INS_PINSRD: pinsrd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PINSRQrm, X86_INS_PINSRQ: pinsrq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PINSRQrr, X86_INS_PINSRQ: pinsrq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PINSRWrm, X86_INS_PINSRW: pinsrw */ 0, { 0 } }, { /* X86_PINSRWrr, X86_INS_PINSRW: pinsrw */ 0, { 0 } }, { /* X86_PMADDUBSWrm, X86_INS_PMADDUBSW: pmaddubsw */ 0, { 0 } }, { /* X86_PMADDUBSWrr, X86_INS_PMADDUBSW: pmaddubsw */ 0, { 0 } }, { /* X86_PMADDWDrm, X86_INS_PMADDWD: pmaddwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMADDWDrr, X86_INS_PMADDWD: pmaddwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXSBrm, X86_INS_PMAXSB: pmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXSBrr, X86_INS_PMAXSB: pmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXSDrm, X86_INS_PMAXSD: pmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXSDrr, X86_INS_PMAXSD: pmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXSWrm, X86_INS_PMAXSW: pmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXSWrr, X86_INS_PMAXSW: pmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXUBrm, X86_INS_PMAXUB: pmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXUBrr, X86_INS_PMAXUB: pmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXUDrm, X86_INS_PMAXUD: pmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXUDrr, X86_INS_PMAXUD: pmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXUWrm, X86_INS_PMAXUW: pmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMAXUWrr, X86_INS_PMAXUW: pmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINSBrm, X86_INS_PMINSB: pminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINSBrr, X86_INS_PMINSB: pminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINSDrm, X86_INS_PMINSD: pminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINSDrr, X86_INS_PMINSD: pminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINSWrm, X86_INS_PMINSW: pminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINSWrr, X86_INS_PMINSW: pminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINUBrm, X86_INS_PMINUB: pminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINUBrr, X86_INS_PMINUB: pminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINUDrm, X86_INS_PMINUD: pminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINUDrr, X86_INS_PMINUD: pminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINUWrm, X86_INS_PMINUW: pminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMINUWrr, X86_INS_PMINUW: pminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVMSKBrr, X86_INS_PMOVMSKB: pmovmskb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXBDrm, X86_INS_PMOVSXBD: pmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXBDrr, X86_INS_PMOVSXBD: pmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXBQrm, X86_INS_PMOVSXBQ: pmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXBQrr, X86_INS_PMOVSXBQ: pmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXBWrm, X86_INS_PMOVSXBW: pmovsxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXBWrr, X86_INS_PMOVSXBW: pmovsxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXDQrm, X86_INS_PMOVSXDQ: pmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXDQrr, X86_INS_PMOVSXDQ: pmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXWDrm, X86_INS_PMOVSXWD: pmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXWDrr, X86_INS_PMOVSXWD: pmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXWQrm, X86_INS_PMOVSXWQ: pmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVSXWQrr, X86_INS_PMOVSXWQ: pmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXBDrm, X86_INS_PMOVZXBD: pmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXBDrr, X86_INS_PMOVZXBD: pmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXBQrm, X86_INS_PMOVZXBQ: pmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXBQrr, X86_INS_PMOVZXBQ: pmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXBWrm, X86_INS_PMOVZXBW: pmovzxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXBWrr, X86_INS_PMOVZXBW: pmovzxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXDQrm, X86_INS_PMOVZXDQ: pmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXDQrr, X86_INS_PMOVZXDQ: pmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXWDrm, X86_INS_PMOVZXWD: pmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXWDrr, X86_INS_PMOVZXWD: pmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXWQrm, X86_INS_PMOVZXWQ: pmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMOVZXWQrr, X86_INS_PMOVZXWQ: pmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULDQrm, X86_INS_PMULDQ: pmuldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULDQrr, X86_INS_PMULDQ: pmuldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULHRSWrm, X86_INS_PMULHRSW: pmulhrsw */ 0, { 0 } }, { /* X86_PMULHRSWrr, X86_INS_PMULHRSW: pmulhrsw */ 0, { 0 } }, { /* X86_PMULHRWrm, X86_INS_PMULHRW: pmulhrw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULHRWrr, X86_INS_PMULHRW: pmulhrw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULHUWrm, X86_INS_PMULHUW: pmulhuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULHUWrr, X86_INS_PMULHUW: pmulhuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULHWrm, X86_INS_PMULHW: pmulhw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULHWrr, X86_INS_PMULHW: pmulhw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULLDrm, X86_INS_PMULLD: pmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULLDrr, X86_INS_PMULLD: pmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULLWrm, X86_INS_PMULLW: pmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULLWrr, X86_INS_PMULLW: pmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULUDQrm, X86_INS_PMULUDQ: pmuludq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PMULUDQrr, X86_INS_PMULUDQ: pmuludq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POP16r, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP16rmm, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP16rmr, X86_INS_POP: pop{w} $reg */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP32r, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP32rmm, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP32rmr, X86_INS_POP: pop{l} $reg */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP64r, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP64rmm, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP64rmr, X86_INS_POP: pop{q} $reg */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPA16, X86_INS_POPAW: popaw */ 0, { 0 } }, { /* X86_POPA32, X86_INS_POPAL: popal */ 0, { 0 } }, { /* X86_POPCNT16rm, X86_INS_POPCNT: popcnt */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POPCNT16rr, X86_INS_POPCNT: popcnt */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POPCNT32rm, X86_INS_POPCNT: popcnt */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POPCNT32rr, X86_INS_POPCNT: popcnt */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POPCNT64rm, X86_INS_POPCNT: popcnt */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POPCNT64rr, X86_INS_POPCNT: popcnt */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_POPDS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPDS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPES16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPES32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPF16, X86_INS_POPF: popf */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_POPF32, X86_INS_POPFD: popfd */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_POPF64, X86_INS_POPFQ: popfq */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_POPFS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPFS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPFS64, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPGS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPGS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPGS64, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPSS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPSS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_PORrm, X86_INS_POR: por */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PORrr, X86_INS_POR: por */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PREFETCH, X86_INS_PREFETCH: prefetch */ 0, { CS_AC_READ, 0 } }, { /* X86_PREFETCHNTA, X86_INS_PREFETCHNTA: prefetchnta */ 0, { CS_AC_READ, 0 } }, { /* X86_PREFETCHT0, X86_INS_PREFETCHT0: prefetcht0 */ 0, { CS_AC_READ, 0 } }, { /* X86_PREFETCHT1, X86_INS_PREFETCHT1: prefetcht1 */ 0, { CS_AC_READ, 0 } }, { /* X86_PREFETCHT2, X86_INS_PREFETCHT2: prefetcht2 */ 0, { CS_AC_READ, 0 } }, { /* X86_PREFETCHW, X86_INS_PREFETCHW: prefetchw */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { CS_AC_READ, 0 } }, { /* X86_PREFETCHWT1, X86_INS_PREFETCHWT1: prefetchwt1 */ 0, { 0 } }, { /* X86_PSADBWrm, X86_INS_PSADBW: psadbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSADBWrr, X86_INS_PSADBW: psadbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSHUFBrm, X86_INS_PSHUFB: pshufb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSHUFBrr, X86_INS_PSHUFB: pshufb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSHUFDmi, X86_INS_PSHUFD: pshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PSHUFDri, X86_INS_PSHUFD: pshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PSHUFHWmi, X86_INS_PSHUFHW: pshufhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PSHUFHWri, X86_INS_PSHUFHW: pshufhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PSHUFLWmi, X86_INS_PSHUFLW: pshuflw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PSHUFLWri, X86_INS_PSHUFLW: pshuflw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PSIGNBrm, X86_INS_PSIGNB: psignb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSIGNBrr, X86_INS_PSIGNB: psignb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSIGNDrm, X86_INS_PSIGND: psignd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSIGNDrr, X86_INS_PSIGND: psignd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSIGNWrm, X86_INS_PSIGNW: psignw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSIGNWrr, X86_INS_PSIGNW: psignw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSLLDQri, X86_INS_PSLLDQ: pslldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSLLDri, X86_INS_PSLLD: pslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSLLDrm, X86_INS_PSLLD: pslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSLLDrr, X86_INS_PSLLD: pslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSLLQri, X86_INS_PSLLQ: psllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSLLQrm, X86_INS_PSLLQ: psllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSLLQrr, X86_INS_PSLLQ: psllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSLLWri, X86_INS_PSLLW: psllw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSLLWrm, X86_INS_PSLLW: psllw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSLLWrr, X86_INS_PSLLW: psllw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRADri, X86_INS_PSRAD: psrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSRADrm, X86_INS_PSRAD: psrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRADrr, X86_INS_PSRAD: psrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRAWri, X86_INS_PSRAW: psraw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSRAWrm, X86_INS_PSRAW: psraw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRAWrr, X86_INS_PSRAW: psraw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRLDQri, X86_INS_PSRLDQ: psrldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSRLDri, X86_INS_PSRLD: psrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSRLDrm, X86_INS_PSRLD: psrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRLDrr, X86_INS_PSRLD: psrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRLQri, X86_INS_PSRLQ: psrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSRLQrm, X86_INS_PSRLQ: psrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRLQrr, X86_INS_PSRLQ: psrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRLWri, X86_INS_PSRLW: psrlw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_PSRLWrm, X86_INS_PSRLW: psrlw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSRLWrr, X86_INS_PSRLW: psrlw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBBrm, X86_INS_PSUBB: psubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBBrr, X86_INS_PSUBB: psubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBDrm, X86_INS_PSUBD: psubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBDrr, X86_INS_PSUBD: psubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBQrm, X86_INS_PSUBQ: psubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBQrr, X86_INS_PSUBQ: psubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBSBrm, X86_INS_PSUBSB: psubsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBSBrr, X86_INS_PSUBSB: psubsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBSWrm, X86_INS_PSUBSW: psubsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBSWrr, X86_INS_PSUBSW: psubsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBUSBrm, X86_INS_PSUBUSB: psubusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBUSBrr, X86_INS_PSUBUSB: psubusb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBUSWrm, X86_INS_PSUBUSW: psubusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBUSWrr, X86_INS_PSUBUSW: psubusw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBWrm, X86_INS_PSUBW: psubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSUBWrr, X86_INS_PSUBW: psubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSWAPDrm, X86_INS_PSWAPD: pswapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PSWAPDrr, X86_INS_PSWAPD: pswapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PTESTrm, X86_INS_PTEST: ptest */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PTESTrr, X86_INS_PTEST: ptest */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PTWRITE64m, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PTWRITE64r, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PTWRITEm, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PTWRITEr, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PUNPCKHBWrm, X86_INS_PUNPCKHBW: punpckhbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHBWrr, X86_INS_PUNPCKHBW: punpckhbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHDQrm, X86_INS_PUNPCKHDQ: punpckhdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHDQrr, X86_INS_PUNPCKHDQ: punpckhdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHQDQrm, X86_INS_PUNPCKHQDQ: punpckhqdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHQDQrr, X86_INS_PUNPCKHQDQ: punpckhqdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHWDrm, X86_INS_PUNPCKHWD: punpckhwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKHWDrr, X86_INS_PUNPCKHWD: punpckhwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLBWrm, X86_INS_PUNPCKLBW: punpcklbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLBWrr, X86_INS_PUNPCKLBW: punpcklbw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLDQrm, X86_INS_PUNPCKLDQ: punpckldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLDQrr, X86_INS_PUNPCKLDQ: punpckldq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLQDQrm, X86_INS_PUNPCKLQDQ: punpcklqdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLQDQrr, X86_INS_PUNPCKLQDQ: punpcklqdq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLWDrm, X86_INS_PUNPCKLWD: punpcklwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUNPCKLWDrr, X86_INS_PUNPCKLWD: punpcklwd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PUSH16i8, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH16r, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH16rmm, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH16rmr, X86_INS_PUSH: push{w} $reg */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH32i8, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH32r, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH32rmm, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH32rmr, X86_INS_PUSH: push{l} $reg */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH64i32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH64i8, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH64r, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH64rmm, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH64rmr, X86_INS_PUSH: push{q} $reg */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSHA16, X86_INS_PUSHAW: pushaw */ 0, { 0 } }, { /* X86_PUSHA32, X86_INS_PUSHAL: pushal */ 0, { 0 } }, { /* X86_PUSHCS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHCS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHDS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHDS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHES16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHES32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHF16, X86_INS_PUSHF: pushf */ 0, { 0 } }, { /* X86_PUSHF32, X86_INS_PUSHFD: pushfd */ 0, { 0 } }, { /* X86_PUSHF64, X86_INS_PUSHFQ: pushfq */ 0, { 0 } }, { /* X86_PUSHFS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHFS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHFS64, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHGS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHGS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHGS64, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHSS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHSS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHi16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHi32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PXORrm, X86_INS_PXOR: pxor */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_PXORrr, X86_INS_PXOR: pxor */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL16m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL16mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL16mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL16r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL16rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL16ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL32m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL32mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL32mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL32r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL32rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL32ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL64m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL64mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL64mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL64r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL64rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL64ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL8m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL8mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL8mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL8r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL8rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL8ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCPPSm, X86_INS_RCPPS: rcpps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCPPSr, X86_INS_RCPPS: rcpps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCPSSm, X86_INS_RCPSS: rcpss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCPSSm_Int, X86_INS_RCPSS: rcpss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCPSSr, X86_INS_RCPSS: rcpss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCPSSr_Int, X86_INS_RCPSS: rcpss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR16m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR16mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR16mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR16r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR16rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR16ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR32m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR32mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR32mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR32r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR32rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR32ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR64m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR64mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR64mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR64r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR64rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR64ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR8m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR8mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR8mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR8r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR8rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR8ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RDFSBASE, X86_INS_RDFSBASE: rdfsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDFSBASE64, X86_INS_RDFSBASE: rdfsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDGSBASE, X86_INS_RDGSBASE: rdgsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDGSBASE64, X86_INS_RDGSBASE: rdgsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDMSR, X86_INS_RDMSR: rdmsr */ 0, { 0 } }, { /* X86_RDPID32, X86_INS_RDPID: rdpid */ 0, { 0 } }, { /* X86_RDPID64, X86_INS_RDPID: rdpid */ 0, { 0 } }, { /* X86_RDPKRUr, X86_INS_RDPKRU: rdpkru */ 0, { 0 } }, { /* X86_RDPMC, X86_INS_RDPMC: rdpmc */ 0, { 0 } }, { /* X86_RDRAND16r, X86_INS_RDRAND: rdrand */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDRAND32r, X86_INS_RDRAND: rdrand */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDRAND64r, X86_INS_RDRAND: rdrand */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSEED16r, X86_INS_RDSEED: rdseed */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSEED32r, X86_INS_RDSEED: rdseed */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSEED64r, X86_INS_RDSEED: rdseed */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSSPD, X86_INS_RDSSPD: rdsspd */ 0, { 0 } }, { /* X86_RDSSPQ, X86_INS_RDSSPQ: rdsspq */ 0, { 0 } }, { /* X86_RDTSC, X86_INS_RDTSC: rdtsc */ 0, { 0 } }, { /* X86_RDTSCP, X86_INS_RDTSCP: rdtscp */ 0, { 0 } }, { /* X86_REPNE_PREFIX, X86_INS_REPNE: repne */ 0, { 0 } }, { /* X86_REP_PREFIX, X86_INS_REP: rep */ 0, { 0 } }, { /* X86_RETIL, X86_INS_RET: ret */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RETIQ, X86_INS_RET: ret */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RETIW, X86_INS_RET: ret */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RETL, X86_INS_RET: ret */ 0, { 0 } }, { /* X86_RETQ, X86_INS_RET: ret */ 0, { 0 } }, { /* X86_RETW, X86_INS_RET: ret */ 0, { 0 } }, { /* X86_REX64_PREFIX, X86_INS_REX64: rex64 */ 0, { 0 } }, { /* X86_ROL16m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL16mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL16mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL16r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL16rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL16ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL32m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL32mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL32mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL32r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL32rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL32ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL64m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL64mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL64mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL64r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL64rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL64ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL8m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL8mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL8mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL8r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL8rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL8ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR16m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR16mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR16mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR16r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR16rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR16ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR32m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR32mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR32mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR32r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR32rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR32ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR64m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR64mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR64mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR64r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR64rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR64ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR8m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR8mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR8mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR8r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR8rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR8ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RORX32mi, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RORX32ri, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RORX64mi, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RORX64ri, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDPDm, X86_INS_ROUNDPD: roundpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDPDr, X86_INS_ROUNDPD: roundpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDPSm, X86_INS_ROUNDPS: roundps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDPSr, X86_INS_ROUNDPS: roundps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDSDm, X86_INS_ROUNDSD: roundsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDSDm_Int, X86_INS_ROUNDSD: roundsd */ 0, { 0 } }, { /* X86_ROUNDSDr, X86_INS_ROUNDSD: roundsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDSDr_Int, X86_INS_ROUNDSD: roundsd $dst $src2 $src3 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDSSm, X86_INS_ROUNDSS: roundss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDSSm_Int, X86_INS_ROUNDSS: roundss */ 0, { 0 } }, { /* X86_ROUNDSSr, X86_INS_ROUNDSS: roundss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROUNDSSr_Int, X86_INS_ROUNDSS: roundss $dst $src2 $src3 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RSM, X86_INS_RSM: rsm */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_RSQRTPSm, X86_INS_RSQRTPS: rsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RSQRTPSr, X86_INS_RSQRTPS: rsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RSQRTSSm, X86_INS_RSQRTSS: rsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RSQRTSSm_Int, X86_INS_RSQRTSS: rsqrtss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RSQRTSSr, X86_INS_RSQRTSS: rsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RSQRTSSr_Int, X86_INS_RSQRTSS: rsqrtss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RSTORSSP, X86_INS_RSTORSSP: rstorssp */ 0, { 0 } }, { /* X86_SAHF, X86_INS_SAHF: sahf */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_SAL16m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL16mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL16mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL16r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL16rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL16ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL32mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL32ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL64mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL64ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL8mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL8ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SALC, X86_INS_SALC: salc */ 0, { 0 } }, { /* X86_SAR16m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR16mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR16mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR16r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR16rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR16ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR32mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR32ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR64mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR64ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR8mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR8ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SARX32rm, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SARX32rr, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SARX64rm, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SARX64rr, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP: saveprevssp */ 0, { 0 } }, { /* X86_SBB16i16, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16mi, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16mi8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB16ri, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16ri8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB16rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB16rr_REV, X86_INS_SBB: sbb{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32i32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32mi, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32mi8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32ri, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32ri8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32rr_REV, X86_INS_SBB: sbb{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64i32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64mi32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64mi8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64ri32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64ri8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64rr_REV, X86_INS_SBB: sbb{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8i8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8mi, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8mi8, X86_INS_SBB: sbb{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8ri, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8ri8, X86_INS_SBB: sbb{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8rr_REV, X86_INS_SBB: sbb{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SCASB, X86_INS_SCASB: scasb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SCASL, X86_INS_SCASD: scasd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SCASQ, X86_INS_SCASQ: scasq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SCASW, X86_INS_SCASW: scasw */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SETAEm, X86_INS_SETAE: setae */ X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETAEr, X86_INS_SETAE: setae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETAm, X86_INS_SETA: seta */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETAr, X86_INS_SETA: seta */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETBEm, X86_INS_SETBE: setbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETBEr, X86_INS_SETBE: setbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETBm, X86_INS_SETB: setb */ X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETBr, X86_INS_SETB: setb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETEm, X86_INS_SETE: sete */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETEr, X86_INS_SETE: sete */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETGEm, X86_INS_SETGE: setge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETGEr, X86_INS_SETGE: setge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SETGm, X86_INS_SETG: setg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_READ, 0 } }, { /* X86_SETGr, X86_INS_SETG: setg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETLEm, X86_INS_SETLE: setle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_READ, 0 } }, { /* X86_SETLEr, X86_INS_SETLE: setle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETLm, X86_INS_SETL: setl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETLr, X86_INS_SETL: setl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SETNEm, X86_INS_SETNE: setne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETNEr, X86_INS_SETNE: setne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETNOm, X86_INS_SETNO: setno */ X86_EFLAGS_TEST_OF, { CS_AC_READ, 0 } }, { /* X86_SETNOr, X86_INS_SETNO: setno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, 0 } }, { /* X86_SETNPm, X86_INS_SETNP: setnp */ X86_EFLAGS_TEST_PF, { CS_AC_READ, 0 } }, { /* X86_SETNPr, X86_INS_SETNP: setnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, 0 } }, { /* X86_SETNSm, X86_INS_SETNS: setns */ X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETNSr, X86_INS_SETNS: setns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SETOm, X86_INS_SETO: seto */ X86_EFLAGS_TEST_OF, { CS_AC_READ, 0 } }, { /* X86_SETOr, X86_INS_SETO: seto */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, 0 } }, { /* X86_SETPm, X86_INS_SETP: setp */ X86_EFLAGS_TEST_PF, { CS_AC_READ, 0 } }, { /* X86_SETPr, X86_INS_SETP: setp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, 0 } }, { /* X86_SETSSBSY, X86_INS_SETSSBSY: setssbsy */ 0, { 0 } }, { /* X86_SETSm, X86_INS_SETS: sets */ X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETSr, X86_INS_SETS: sets */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SFENCE, X86_INS_SFENCE: sfence */ 0, { 0 } }, { /* X86_SGDT16m, X86_INS_SGDT: sgdt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SGDT32m, X86_INS_SGDT: sgdt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SGDT64m, X86_INS_SGDT: sgdt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SHA1MSG1rm, X86_INS_SHA1MSG1: sha1msg1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA1MSG1rr, X86_INS_SHA1MSG1: sha1msg1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA1MSG2rm, X86_INS_SHA1MSG2: sha1msg2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA1MSG2rr, X86_INS_SHA1MSG2: sha1msg2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA1NEXTErm, X86_INS_SHA1NEXTE: sha1nexte */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA1NEXTErr, X86_INS_SHA1NEXTE: sha1nexte */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA1RNDS4rmi, X86_INS_SHA1RNDS4: sha1rnds4 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHA1RNDS4rri, X86_INS_SHA1RNDS4: sha1rnds4 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHA256MSG1rm, X86_INS_SHA256MSG1: sha256msg1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA256MSG1rr, X86_INS_SHA256MSG1: sha256msg1 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA256MSG2rm, X86_INS_SHA256MSG2: sha256msg2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA256MSG2rr, X86_INS_SHA256MSG2: sha256msg2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA256RNDS2rm, X86_INS_SHA256RNDS2: sha256rnds2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHA256RNDS2rr, X86_INS_SHA256RNDS2: sha256rnds2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL16m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL16mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL16mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL16r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL16rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL16ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL32mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL32ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL64mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL64ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL8mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL8ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHLD16mrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD16mri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD16rrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD16rri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD32mrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD32mri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD32rrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD32rri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD64mrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD64mri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD64rrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD64rri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLX32rm, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLX32rr, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLX64rm, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLX64rr, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHR16m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR16mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR16mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR16r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR16rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR16ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR32mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR32ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR64mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR64ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR8mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR8ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHRD16mrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD16mri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD16rrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD16rri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD32mrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD32mri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD32rrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD32rri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD64mrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD64mri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD64rrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD64rri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRX32rm, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRX32rr, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRX64rm, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRX64rr, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHUFPDrmi, X86_INS_SHUFPD: shufpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHUFPDrri, X86_INS_SHUFPD: shufpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHUFPSrmi, X86_INS_SHUFPS: shufps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHUFPSrri, X86_INS_SHUFPS: shufps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SIDT16m, X86_INS_SIDT: sidt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SIDT32m, X86_INS_SIDT: sidt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SIDT64m, X86_INS_SIDT: sidt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SIN_F, X86_INS_FSIN: fsin */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_SIN_Fp32, X86_INS_FSIN: fsin */ 0, { 0 } }, { /* X86_SIN_Fp64, X86_INS_FSIN: fsin */ 0, { 0 } }, { /* X86_SIN_Fp80, X86_INS_FSIN: fsin */ 0, { 0 } }, { /* X86_SKINIT, X86_INS_SKINIT: skinit */ 0, { CS_AC_READ, 0 } }, { /* X86_SLDT16m, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLDT16r, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLDT32r, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLDT64r, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLWPCB, X86_INS_SLWPCB: slwpcb */ 0, { 0 } }, { /* X86_SLWPCB64, X86_INS_SLWPCB: slwpcb */ 0, { 0 } }, { /* X86_SMSW16m, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SMSW16r, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SMSW32r, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SMSW64r, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SQRTPDm, X86_INS_SQRTPD: sqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTPDr, X86_INS_SQRTPD: sqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTPSm, X86_INS_SQRTPS: sqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTPSr, X86_INS_SQRTPS: sqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTSDm, X86_INS_SQRTSD: sqrtsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTSDm_Int, X86_INS_SQRTSD: sqrtsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SQRTSDr, X86_INS_SQRTSD: sqrtsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTSDr_Int, X86_INS_SQRTSD: sqrtsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTSSm, X86_INS_SQRTSS: sqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTSSm_Int, X86_INS_SQRTSS: sqrtss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SQRTSSr, X86_INS_SQRTSS: sqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRTSSr_Int, X86_INS_SQRTSS: sqrtss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SQRT_F, X86_INS_FSQRT: fsqrt */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_SQRT_Fp32, X86_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* X86_SQRT_Fp64, X86_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* X86_SQRT_Fp80, X86_INS_FSQRT: fsqrt */ 0, { 0 } }, { /* X86_STAC, X86_INS_STAC: stac */ 0, { 0 } }, { /* X86_STC, X86_INS_STC: stc */ X86_EFLAGS_SET_CF, { 0 } }, { /* X86_STD, X86_INS_STD: std */ X86_EFLAGS_SET_DF, { 0 } }, { /* X86_STGI, X86_INS_STGI: stgi */ 0, { 0 } }, { /* X86_STI, X86_INS_STI: sti */ X86_EFLAGS_SET_IF, { 0 } }, { /* X86_STMXCSR, X86_INS_STMXCSR: stmxcsr */ 0, { CS_AC_READ, 0 } }, { /* X86_STOSB, X86_INS_STOSB: stosb */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STOSL, X86_INS_STOSD: stosd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STOSQ, X86_INS_STOSQ: stosq */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STOSW, X86_INS_STOSW: stosw */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STR16r, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STR32r, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STR64r, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STRm, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_ST_F32m, X86_INS_FST: fst */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ST_F64m, X86_INS_FST: fst */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ST_FP32m, X86_INS_FSTP: fstp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ST_FP64m, X86_INS_FSTP: fstp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_ST_FP80m, X86_INS_FSTP: fstp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_ST_FPrr, X86_INS_FSTP: fstp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_WRITE, 0 } }, { /* X86_ST_Fp32m, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_Fp64m, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_Fp64m32, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_Fp80m32, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_Fp80m64, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_FpP32m, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_FpP64m, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_FpP64m32, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_FpP80m, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_FpP80m32, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_FpP80m64, X86_INS_FST: fst */ 0, { 0 } }, { /* X86_ST_Frr, X86_INS_FST: fst */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB16i16, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16mi, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16mi8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB16ri, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16ri8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB16rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB16rr_REV, X86_INS_SUB: sub{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32i32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32mi, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32mi8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32ri, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32ri8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32rr_REV, X86_INS_SUB: sub{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64i32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64mi32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64mi8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64ri32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64ri8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64rr_REV, X86_INS_SUB: sub{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8i8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8mi, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8mi8, X86_INS_SUB: sub{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8ri, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8ri8, X86_INS_SUB: sub{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8rr_REV, X86_INS_SUB: sub{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBPDrm, X86_INS_SUBPD: subpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBPDrr, X86_INS_SUBPD: subpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBPSrm, X86_INS_SUBPS: subps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBPSrr, X86_INS_SUBPS: subps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBR_F32m, X86_INS_FSUBR: fsubr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUBR_F64m, X86_INS_FSUBR: fsubr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUBR_FI16m, X86_INS_FISUBR: fisubr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUBR_FI32m, X86_INS_FISUBR: fisubr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUBR_FPrST0, X86_INS_FSUBRP: fsubrp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUBR_FST0r, X86_INS_FSUBR: fsubr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUBR_Fp32m, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_Fp64m, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_Fp64m32, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_Fp80m32, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_Fp80m64, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FpI16m32, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FpI16m64, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FpI16m80, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FpI32m32, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FpI32m64, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FpI32m80, X86_INS_FSUBR: fsubr */ 0, { 0 } }, { /* X86_SUBR_FrST0, X86_INS_FSUBR: fsubr */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SUBSDrm, X86_INS_SUBSD: subsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBSDrm_Int, X86_INS_SUBSD: subsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUBSDrr, X86_INS_SUBSD: subsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBSDrr_Int, X86_INS_SUBSD: subsd $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBSSrm, X86_INS_SUBSS: subss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBSSrm_Int, X86_INS_SUBSS: subss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUBSSrr, X86_INS_SUBSS: subss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUBSSrr_Int, X86_INS_SUBSS: subss $dst $src2 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB_F32m, X86_INS_FSUB: fsub */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB_F64m, X86_INS_FSUB: fsub */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB_FI16m, X86_INS_FISUB: fisub */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB_FI32m, X86_INS_FISUB: fisub */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB_FPrST0, X86_INS_FSUBP: fsubp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB_FST0r, X86_INS_FSUB: fsub */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_SUB_Fp32, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp32m, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp64, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp64m, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp64m32, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp80, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp80m32, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_Fp80m64, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FpI16m32, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FpI16m64, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FpI16m80, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FpI32m32, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FpI32m64, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FpI32m80, X86_INS_FSUB: fsub */ 0, { 0 } }, { /* X86_SUB_FrST0, X86_INS_FSUB: fsub */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SWAPGS, X86_INS_SWAPGS: swapgs */ 0, { 0 } }, { /* X86_SYSCALL, X86_INS_SYSCALL: syscall */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSENTER, X86_INS_SYSENTER: sysenter */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSEXIT, X86_INS_SYSEXIT: sysexit */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSEXIT64, X86_INS_SYSEXITQ: sysexitq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSRET, X86_INS_SYSRET: sysret */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSRET64, X86_INS_SYSRETQ: sysretq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_T1MSKC32rm, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_T1MSKC32rr, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_T1MSKC64rm, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_T1MSKC64rr, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TEST16i16, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST16mi, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST16mi_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST16mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST16ri, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST16ri_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST16rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST32i32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST32mi, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST32mi_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST32mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST32ri, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST32ri_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST32rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST64i32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST64mi32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST64mi32_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST64mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST64ri32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST64ri32_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST64rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST8i8, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST8mi, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST8mi_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST8mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST8ri, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST8ri_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST8rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TPAUSE, X86_INS_TPAUSE: tpause */ 0, { 0 } }, { /* X86_TST_F, X86_INS_FTST: ftst */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { 0 } }, { /* X86_TST_Fp32, X86_INS_FTST: ftst */ 0, { 0 } }, { /* X86_TST_Fp64, X86_INS_FTST: ftst */ 0, { 0 } }, { /* X86_TST_Fp80, X86_INS_FTST: ftst */ 0, { 0 } }, { /* X86_TZCNT16rm, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT16rr, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT32rm, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT32rr, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT64rm, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT64rr, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK32rm, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK32rr, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK64rm, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK64rr, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UCOMISDrm, X86_INS_UCOMISD: ucomisd */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_UCOMISDrm_Int, X86_INS_UCOMISD: ucomisd */ 0, { 0 } }, { /* X86_UCOMISDrr, X86_INS_UCOMISD: ucomisd */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_UCOMISDrr_Int, X86_INS_UCOMISD: ucomisd */ 0, { 0 } }, { /* X86_UCOMISSrm, X86_INS_UCOMISS: ucomiss */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_UCOMISSrm_Int, X86_INS_UCOMISS: ucomiss */ 0, { 0 } }, { /* X86_UCOMISSrr, X86_INS_UCOMISS: ucomiss */ X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_UCOMISSrr_Int, X86_INS_UCOMISS: ucomiss */ 0, { 0 } }, { /* X86_UCOM_FIPr, X86_INS_FUCOMPI: fucompi */ 0, { CS_AC_READ, 0 } }, { /* X86_UCOM_FIr, X86_INS_FUCOMI: fucomi */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_UCOM_FPPr, X86_INS_FUCOMPP: fucompp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { 0 } }, { /* X86_UCOM_FPr, X86_INS_FUCOMP: fucomp */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_UCOM_FpIr32, X86_INS_FUCOMP: fucomp */ 0, { 0 } }, { /* X86_UCOM_FpIr64, X86_INS_FUCOMP: fucomp */ 0, { 0 } }, { /* X86_UCOM_FpIr80, X86_INS_FUCOMP: fucomp */ 0, { 0 } }, { /* X86_UCOM_Fpr32, X86_INS_FUCOMP: fucomp */ 0, { 0 } }, { /* X86_UCOM_Fpr64, X86_INS_FUCOMP: fucomp */ 0, { 0 } }, { /* X86_UCOM_Fpr80, X86_INS_FUCOMP: fucomp */ 0, { 0 } }, { /* X86_UCOM_Fr, X86_INS_FUCOM: fucom */ X86_FPU_FLAGS_MODIFY_C1 | X86_FPU_FLAGS_MODIFY_C0 | X86_FPU_FLAGS_MODIFY_C2 | X86_FPU_FLAGS_MODIFY_C3, { CS_AC_READ, 0 } }, { /* X86_UD0, X86_INS_UD0: ud0 */ 0, { 0 } }, { /* X86_UD1, X86_INS_UD1: ud1 */ 0, { 0 } }, { /* X86_UD2, X86_INS_UD2: ud2 */ 0, { 0 } }, { /* X86_UMONITOR16, X86_INS_UMONITOR: umonitor */ 0, { 0 } }, { /* X86_UMONITOR32, X86_INS_UMONITOR: umonitor */ 0, { 0 } }, { /* X86_UMONITOR64, X86_INS_UMONITOR: umonitor */ 0, { 0 } }, { /* X86_UMWAIT, X86_INS_UMWAIT: umwait */ 0, { 0 } }, { /* X86_UNPCKHPDrm, X86_INS_UNPCKHPD: unpckhpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKHPDrr, X86_INS_UNPCKHPD: unpckhpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKHPSrm, X86_INS_UNPCKHPS: unpckhps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKHPSrr, X86_INS_UNPCKHPS: unpckhps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKLPDrm, X86_INS_UNPCKLPD: unpcklpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKLPDrr, X86_INS_UNPCKLPD: unpcklpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKLPSrm, X86_INS_UNPCKLPS: unpcklps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UNPCKLPSrr, X86_INS_UNPCKLPS: unpcklps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_V4FMADDPSrm, X86_INS_V4FMADDPS: v4fmaddps */ 0, { 0 } }, { /* X86_V4FMADDPSrmk, X86_INS_V4FMADDPS: v4fmaddps */ 0, { 0 } }, { /* X86_V4FMADDPSrmkz, X86_INS_V4FMADDPS: v4fmaddps */ 0, { 0 } }, { /* X86_V4FMADDSSrm, X86_INS_V4FMADDSS: v4fmaddss */ 0, { 0 } }, { /* X86_V4FMADDSSrmk, X86_INS_V4FMADDSS: v4fmaddss */ 0, { 0 } }, { /* X86_V4FMADDSSrmkz, X86_INS_V4FMADDSS: v4fmaddss */ 0, { 0 } }, { /* X86_V4FNMADDPSrm, X86_INS_V4FNMADDPS: v4fnmaddps */ 0, { 0 } }, { /* X86_V4FNMADDPSrmk, X86_INS_V4FNMADDPS: v4fnmaddps */ 0, { 0 } }, { /* X86_V4FNMADDPSrmkz, X86_INS_V4FNMADDPS: v4fnmaddps */ 0, { 0 } }, { /* X86_V4FNMADDSSrm, X86_INS_V4FNMADDSS: v4fnmaddss */ 0, { 0 } }, { /* X86_V4FNMADDSSrmk, X86_INS_V4FNMADDSS: v4fnmaddss */ 0, { 0 } }, { /* X86_V4FNMADDSSrmkz, X86_INS_V4FNMADDSS: v4fnmaddss */ 0, { 0 } }, { /* X86_VADDPDYrm, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDYrr, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rm, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rmb, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rmbk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rmbkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rmk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rmkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rr, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rrk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ128rrkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rm, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rmb, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rmbk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rmbkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rmk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rmkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rr, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rrk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZ256rrkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrm, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrmb, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrmbk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrmbkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrmk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrmkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrr, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrrb, X86_INS_VADDPD: vaddpd */ 0, { 0 } }, { /* X86_VADDPDZrrbk, X86_INS_VADDPD: vaddpd */ 0, { 0 } }, { /* X86_VADDPDZrrbkz, X86_INS_VADDPD: vaddpd */ 0, { 0 } }, { /* X86_VADDPDZrrk, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDZrrkz, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDrm, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPDrr, X86_INS_VADDPD: vaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSYrm, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSYrr, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rm, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rmb, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rmbk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rmbkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rmk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rmkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rr, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rrk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ128rrkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rm, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rmb, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rmbk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rmbkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rmk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rmkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rr, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rrk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZ256rrkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrm, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrmb, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrmbk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrmbkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrmk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrmkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrr, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrrb, X86_INS_VADDPS: vaddps */ 0, { 0 } }, { /* X86_VADDPSZrrbk, X86_INS_VADDPS: vaddps */ 0, { 0 } }, { /* X86_VADDPSZrrbkz, X86_INS_VADDPS: vaddps */ 0, { 0 } }, { /* X86_VADDPSZrrk, X86_INS_VADDPS: vaddps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSZrrkz, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSrm, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDPSrr, X86_INS_VADDPS: vaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrm, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrm_Int, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrm_Intk, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrm_Intkz, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrr, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrr_Int, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrr_Intk, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrr_Intkz, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDZrrb_Int, X86_INS_VADDSD: vaddsd */ 0, { 0 } }, { /* X86_VADDSDZrrb_Intk, X86_INS_VADDSD: vaddsd */ 0, { 0 } }, { /* X86_VADDSDZrrb_Intkz, X86_INS_VADDSD: vaddsd */ 0, { 0 } }, { /* X86_VADDSDrm, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDrm_Int, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VADDSDrr, X86_INS_VADDSD: vaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSDrr_Int, X86_INS_VADDSD: vaddsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrm, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrm_Int, X86_INS_VADDSS: vaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrm_Intk, X86_INS_VADDSS: vaddss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrm_Intkz, X86_INS_VADDSS: vaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrr, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrr_Int, X86_INS_VADDSS: vaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrr_Intk, X86_INS_VADDSS: vaddss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrr_Intkz, X86_INS_VADDSS: vaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSZrrb_Int, X86_INS_VADDSS: vaddss */ 0, { 0 } }, { /* X86_VADDSSZrrb_Intk, X86_INS_VADDSS: vaddss */ 0, { 0 } }, { /* X86_VADDSSZrrb_Intkz, X86_INS_VADDSS: vaddss */ 0, { 0 } }, { /* X86_VADDSSrm, X86_INS_VADDSS: vaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSrm_Int, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VADDSSrr, X86_INS_VADDSS: vaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSSrr_Int, X86_INS_VADDSS: vaddss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPDYrm, X86_INS_VADDSUBPD: vaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPDYrr, X86_INS_VADDSUBPD: vaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPDrm, X86_INS_VADDSUBPD: vaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPDrr, X86_INS_VADDSUBPD: vaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPSYrm, X86_INS_VADDSUBPS: vaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPSYrr, X86_INS_VADDSUBPS: vaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPSrm, X86_INS_VADDSUBPS: vaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VADDSUBPSrr, X86_INS_VADDSUBPS: vaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESDECLASTYrm, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTYrr, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTZ128rm, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTZ128rr, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTZ256rm, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTZ256rr, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTZrm, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTZrr, X86_INS_VAESDECLAST: vaesdeclast */ 0, { 0 } }, { /* X86_VAESDECLASTrm, X86_INS_VAESDECLAST: vaesdeclast */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESDECLASTrr, X86_INS_VAESDECLAST: vaesdeclast */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESDECYrm, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECYrr, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECZ128rm, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECZ128rr, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECZ256rm, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECZ256rr, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECZrm, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECZrr, X86_INS_VAESDEC: vaesdec */ 0, { 0 } }, { /* X86_VAESDECrm, X86_INS_VAESDEC: vaesdec */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESDECrr, X86_INS_VAESDEC: vaesdec */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESENCLASTYrm, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTYrr, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTZ128rm, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTZ128rr, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTZ256rm, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTZ256rr, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTZrm, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTZrr, X86_INS_VAESENCLAST: vaesenclast */ 0, { 0 } }, { /* X86_VAESENCLASTrm, X86_INS_VAESENCLAST: vaesenclast */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESENCLASTrr, X86_INS_VAESENCLAST: vaesenclast */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESENCYrm, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCYrr, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCZ128rm, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCZ128rr, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCZ256rm, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCZ256rr, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCZrm, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCZrr, X86_INS_VAESENC: vaesenc */ 0, { 0 } }, { /* X86_VAESENCrm, X86_INS_VAESENC: vaesenc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESENCrr, X86_INS_VAESENC: vaesenc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VAESIMCrm, X86_INS_VAESIMC: vaesimc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VAESIMCrr, X86_INS_VAESIMC: vaesimc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VAESKEYGENASSIST128rm, X86_INS_VAESKEYGENASSIST: vaeskeygenassist */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VAESKEYGENASSIST128rr, X86_INS_VAESKEYGENASSIST: vaeskeygenassist */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VALIGNDZ128rmbi, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rmbik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rmbikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rmi, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rmik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rmikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rri, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rrik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ128rrikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rmbi, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rmbik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rmbikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rmi, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rmik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rmikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rri, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rrik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZ256rrikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrmbi, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrmbik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrmbikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrmi, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrmik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrmikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrri, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrrik, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNDZrrikz, X86_INS_VALIGND: valignd */ 0, { 0 } }, { /* X86_VALIGNQZ128rmbi, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rmbik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rmbikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rmi, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rmik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rmikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rri, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rrik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ128rrikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rmbi, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rmbik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rmbikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rmi, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rmik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rmikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rri, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rrik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZ256rrikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrmbi, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrmbik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrmbikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrmi, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrmik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrmikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrri, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrrik, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VALIGNQZrrikz, X86_INS_VALIGNQ: valignq */ 0, { 0 } }, { /* X86_VANDNPDYrm, X86_INS_VANDNPD: vandnpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPDYrr, X86_INS_VANDNPD: vandnpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPDZ128rm, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rmb, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rmbk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rmbkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rmk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rmkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rr, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rrk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ128rrkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rm, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rmb, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rmbk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rmbkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rmk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rmkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rr, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rrk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZ256rrkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrm, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrmb, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrmbk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrmbkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrmk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrmkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrr, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrrk, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDZrrkz, X86_INS_VANDNPD: vandnpd */ 0, { 0 } }, { /* X86_VANDNPDrm, X86_INS_VANDNPD: vandnpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPDrr, X86_INS_VANDNPD: vandnpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPSYrm, X86_INS_VANDNPS: vandnps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPSYrr, X86_INS_VANDNPS: vandnps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPSZ128rm, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rmb, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rmbk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rmbkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rmk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rmkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rr, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rrk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ128rrkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rm, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rmb, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rmbk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rmbkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rmk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rmkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rr, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rrk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZ256rrkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrm, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrmb, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrmbk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrmbkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrmk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrmkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrr, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrrk, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSZrrkz, X86_INS_VANDNPS: vandnps */ 0, { 0 } }, { /* X86_VANDNPSrm, X86_INS_VANDNPS: vandnps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDNPSrr, X86_INS_VANDNPS: vandnps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPDYrm, X86_INS_VANDPD: vandpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPDYrr, X86_INS_VANDPD: vandpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPDZ128rm, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rmb, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rmbk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rmbkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rmk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rmkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rr, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rrk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ128rrkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rm, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rmb, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rmbk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rmbkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rmk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rmkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rr, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rrk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZ256rrkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrm, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrmb, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrmbk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrmbkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrmk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrmkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrr, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrrk, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDZrrkz, X86_INS_VANDPD: vandpd */ 0, { 0 } }, { /* X86_VANDPDrm, X86_INS_VANDPD: vandpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPDrr, X86_INS_VANDPD: vandpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPSYrm, X86_INS_VANDPS: vandps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPSYrr, X86_INS_VANDPS: vandps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPSZ128rm, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rmb, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rmbk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rmbkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rmk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rmkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rr, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rrk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ128rrkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rm, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rmb, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rmbk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rmbkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rmk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rmkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rr, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rrk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZ256rrkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrm, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrmb, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrmbk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrmbkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrmk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrmkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrr, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrrk, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSZrrkz, X86_INS_VANDPS: vandps */ 0, { 0 } }, { /* X86_VANDPSrm, X86_INS_VANDPS: vandps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VANDPSrr, X86_INS_VANDPS: vandps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rm, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rmb, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rmbk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rmbkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { 0 } }, { /* X86_VBLENDMPDZ128rmk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rmkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rr, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rrk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ128rrkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rm, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rmb, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rmbk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rmbkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { 0 } }, { /* X86_VBLENDMPDZ256rmk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rmkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rr, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rrk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZ256rrkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrm, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrmb, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrmbk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrmbkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { 0 } }, { /* X86_VBLENDMPDZrmk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrmkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrr, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrrk, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPDZrrkz, X86_INS_VBLENDMPD: vblendmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rm, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rmb, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rmbk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rmbkz, X86_INS_VBLENDMPS: vblendmps */ 0, { 0 } }, { /* X86_VBLENDMPSZ128rmk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rmkz, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rr, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rrk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ128rrkz, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rm, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rmb, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rmbk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rmbkz, X86_INS_VBLENDMPS: vblendmps */ 0, { 0 } }, { /* X86_VBLENDMPSZ256rmk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rmkz, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rr, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rrk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZ256rrkz, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrm, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrmb, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrmbk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrmbkz, X86_INS_VBLENDMPS: vblendmps */ 0, { 0 } }, { /* X86_VBLENDMPSZrmk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrmkz, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrr, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrrk, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDMPSZrrkz, X86_INS_VBLENDMPS: vblendmps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDPDYrmi, X86_INS_VBLENDPD: vblendpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPDYrri, X86_INS_VBLENDPD: vblendpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPDrmi, X86_INS_VBLENDPD: vblendpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPDrri, X86_INS_VBLENDPD: vblendpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPSYrmi, X86_INS_VBLENDPS: vblendps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPSYrri, X86_INS_VBLENDPS: vblendps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPSrmi, X86_INS_VBLENDPS: vblendps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDPSrri, X86_INS_VBLENDPS: vblendps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VBLENDVPDYrm, X86_INS_VBLENDVPD: vblendvpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPDYrr, X86_INS_VBLENDVPD: vblendvpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPDrm, X86_INS_VBLENDVPD: vblendvpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPDrr, X86_INS_VBLENDVPD: vblendvpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPSYrm, X86_INS_VBLENDVPS: vblendvps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPSYrr, X86_INS_VBLENDVPS: vblendvps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPSrm, X86_INS_VBLENDVPS: vblendvps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBLENDVPSrr, X86_INS_VBLENDVPS: vblendvps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VBROADCASTF128, X86_INS_VBROADCASTF128: vbroadcastf128 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTF32X2Z256m, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Z256mk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Z256mkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Z256r, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Z256rk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Z256rkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Zm, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Zmk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Zmkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Zr, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Zrk, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X2Zrkz, X86_INS_VBROADCASTF32X2: vbroadcastf32x2 */ 0, { 0 } }, { /* X86_VBROADCASTF32X4Z256rm, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ 0, { 0 } }, { /* X86_VBROADCASTF32X4Z256rmk, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ 0, { 0 } }, { /* X86_VBROADCASTF32X4Z256rmkz, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ 0, { 0 } }, { /* X86_VBROADCASTF32X4rm, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ 0, { 0 } }, { /* X86_VBROADCASTF32X4rmk, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ 0, { 0 } }, { /* X86_VBROADCASTF32X4rmkz, X86_INS_VBROADCASTF32X4: vbroadcastf32x4 */ 0, { 0 } }, { /* X86_VBROADCASTF32X8rm, X86_INS_VBROADCASTF32X8: vbroadcastf32x8 */ 0, { 0 } }, { /* X86_VBROADCASTF32X8rmk, X86_INS_VBROADCASTF32X8: vbroadcastf32x8 */ 0, { 0 } }, { /* X86_VBROADCASTF32X8rmkz, X86_INS_VBROADCASTF32X8: vbroadcastf32x8 */ 0, { 0 } }, { /* X86_VBROADCASTF64X2Z128rm, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ 0, { 0 } }, { /* X86_VBROADCASTF64X2Z128rmk, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ 0, { 0 } }, { /* X86_VBROADCASTF64X2Z128rmkz, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ 0, { 0 } }, { /* X86_VBROADCASTF64X2rm, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ 0, { 0 } }, { /* X86_VBROADCASTF64X2rmk, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ 0, { 0 } }, { /* X86_VBROADCASTF64X2rmkz, X86_INS_VBROADCASTF64X2: vbroadcastf64x2 */ 0, { 0 } }, { /* X86_VBROADCASTF64X4rm, X86_INS_VBROADCASTF64X4: vbroadcastf64x4 */ 0, { 0 } }, { /* X86_VBROADCASTF64X4rmk, X86_INS_VBROADCASTF64X4: vbroadcastf64x4 */ 0, { 0 } }, { /* X86_VBROADCASTF64X4rmkz, X86_INS_VBROADCASTF64X4: vbroadcastf64x4 */ 0, { 0 } }, { /* X86_VBROADCASTI128, X86_INS_VBROADCASTI128: vbroadcasti128 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z128m, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z128mk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z128mkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z128r, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z128rk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z128rkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z256m, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z256mk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z256mkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z256r, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z256rk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Z256rkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Zm, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Zmk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Zmkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Zr, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Zrk, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X2Zrkz, X86_INS_VBROADCASTI32X2: vbroadcasti32x2 */ 0, { 0 } }, { /* X86_VBROADCASTI32X4Z256rm, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ 0, { 0 } }, { /* X86_VBROADCASTI32X4Z256rmk, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ 0, { 0 } }, { /* X86_VBROADCASTI32X4Z256rmkz, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ 0, { 0 } }, { /* X86_VBROADCASTI32X4rm, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTI32X4rmk, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ 0, { 0 } }, { /* X86_VBROADCASTI32X4rmkz, X86_INS_VBROADCASTI32X4: vbroadcasti32x4 */ 0, { 0 } }, { /* X86_VBROADCASTI32X8rm, X86_INS_VBROADCASTI32X8: vbroadcasti32x8 */ 0, { 0 } }, { /* X86_VBROADCASTI32X8rmk, X86_INS_VBROADCASTI32X8: vbroadcasti32x8 */ 0, { 0 } }, { /* X86_VBROADCASTI32X8rmkz, X86_INS_VBROADCASTI32X8: vbroadcasti32x8 */ 0, { 0 } }, { /* X86_VBROADCASTI64X2Z128rm, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ 0, { 0 } }, { /* X86_VBROADCASTI64X2Z128rmk, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ 0, { 0 } }, { /* X86_VBROADCASTI64X2Z128rmkz, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ 0, { 0 } }, { /* X86_VBROADCASTI64X2rm, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ 0, { 0 } }, { /* X86_VBROADCASTI64X2rmk, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ 0, { 0 } }, { /* X86_VBROADCASTI64X2rmkz, X86_INS_VBROADCASTI64X2: vbroadcasti64x2 */ 0, { 0 } }, { /* X86_VBROADCASTI64X4rm, X86_INS_VBROADCASTI64X4: vbroadcasti64x4 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTI64X4rmk, X86_INS_VBROADCASTI64X4: vbroadcasti64x4 */ 0, { 0 } }, { /* X86_VBROADCASTI64X4rmkz, X86_INS_VBROADCASTI64X4: vbroadcasti64x4 */ 0, { 0 } }, { /* X86_VBROADCASTSDYrm, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDYrr, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZ256m, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZ256mk, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZ256mkz, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZ256r, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZ256rk, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZ256rkz, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZm, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZmk, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZmkz, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZr, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZrk, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSDZrkz, X86_INS_VBROADCASTSD: vbroadcastsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSYrm, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSYrr, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ128m, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ128mk, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ128mkz, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ128r, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ128rk, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ128rkz, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ256m, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ256mk, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ256mkz, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ256r, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ256rk, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZ256rkz, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZm, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZmk, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZmkz, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZr, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZrk, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSZrkz, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSrm, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VBROADCASTSSrr, X86_INS_VBROADCASTSS: vbroadcastss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCMPPDYrmi, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPDYrmi_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDYrri, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPDYrri_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDZ128rmbi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ128rmbi_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ128rmbi_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ128rmbik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ128rmi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ128rmi_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ128rmi_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ128rmik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ128rri, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ128rri_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ128rri_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ128rrik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ256rmbi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ256rmbi_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ256rmbi_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ256rmbik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ256rmi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ256rmi_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ256rmi_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ256rmik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ256rri, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZ256rri_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ256rri_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZ256rrik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZrmbi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZrmbi_alt, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZrmbi_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZrmbik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZrmi, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDZrmi_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDZrmi_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZrmik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZrri, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPDZrri_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDZrri_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZrrib, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPDZrrib_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDZrrib_altk, X86_INS_VCMPPD: vcmppd */ 0, { 0 } }, { /* X86_VCMPPDZrribk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDZrrik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPDrmi, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPDrmi_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPDrri, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPDrri_alt, X86_INS_VCMPPD: vcmppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSYrmi, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPSYrmi_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSYrri, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPSYrri_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSZ128rmbi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ128rmbi_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ128rmbi_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ128rmbik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ128rmi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ128rmi_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ128rmi_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ128rmik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ128rri, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ128rri_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ128rri_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ128rrik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ256rmbi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ256rmbi_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ256rmbi_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ256rmbik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ256rmi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ256rmi_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ256rmi_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ256rmik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ256rri, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZ256rri_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ256rri_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZ256rrik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZrmbi, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZrmbi_alt, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZrmbi_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZrmbik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZrmi, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSZrmi_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSZrmi_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZrmik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZrri, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPSZrri_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSZrri_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZrrib, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPSZrrib_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSZrrib_altk, X86_INS_VCMPPS: vcmpps */ 0, { 0 } }, { /* X86_VCMPPSZrribk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSZrrik, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPPSrmi, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPSrmi_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPPSrri, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPPSrri_alt, X86_INS_VCMPPS: vcmpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSDZrm, X86_INS_VCMPSD: vcmp${cc}sd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSDZrm_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDZrm_Intk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDZrmi_alt, X86_INS_VCMPSD: vcmpsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSDZrmi_altk, X86_INS_VCMPSD: vcmpsd */ 0, { 0 } }, { /* X86_VCMPSDZrr, X86_INS_VCMPSD: vcmp${cc}sd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSDZrr_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDZrr_Intk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDZrrb_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDZrrb_Intk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDZrrb_alt, X86_INS_VCMPSD: vcmpsd */ 0, { 0 } }, { /* X86_VCMPSDZrrb_altk, X86_INS_VCMPSD: vcmpsd */ 0, { 0 } }, { /* X86_VCMPSDZrri_alt, X86_INS_VCMPSD: vcmpsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSDZrri_altk, X86_INS_VCMPSD: vcmpsd */ 0, { 0 } }, { /* X86_VCMPSDrm, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSDrm_Int, X86_INS_VCMPSD: vcmpsd */ 0, { 0 } }, { /* X86_VCMPSDrm_alt, X86_INS_VCMPSD: vcmpsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSDrr, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSDrr_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSDrr_alt, X86_INS_VCMPSD: vcmpsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSSZrm, X86_INS_VCMPSS: vcmp${cc}ss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSSZrm_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSZrm_Intk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSZrmi_alt, X86_INS_VCMPSS: vcmpss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSSZrmi_altk, X86_INS_VCMPSS: vcmpss */ 0, { 0 } }, { /* X86_VCMPSSZrr, X86_INS_VCMPSS: vcmp${cc}ss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSSZrr_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSZrr_Intk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSZrrb_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSZrrb_Intk, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSZrrb_alt, X86_INS_VCMPSS: vcmpss */ 0, { 0 } }, { /* X86_VCMPSSZrrb_altk, X86_INS_VCMPSS: vcmpss */ 0, { 0 } }, { /* X86_VCMPSSZrri_alt, X86_INS_VCMPSS: vcmpss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSSZrri_altk, X86_INS_VCMPSS: vcmpss */ 0, { 0 } }, { /* X86_VCMPSSrm, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSSrm_Int, X86_INS_VCMPSS: vcmpss */ 0, { 0 } }, { /* X86_VCMPSSrm_alt, X86_INS_VCMPSS: vcmpss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCMPSSrr, X86_INS_VCMP: vcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSSrr_Int, X86_INS_VCMP: vcmp */ 0, { 0 } }, { /* X86_VCMPSSrr_alt, X86_INS_VCMPSS: vcmpss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCOMISDZrm, X86_INS_VCOMISD: vcomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISDZrm_Int, X86_INS_VCOMISD: vcomisd */ 0, { 0 } }, { /* X86_VCOMISDZrr, X86_INS_VCOMISD: vcomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISDZrr_Int, X86_INS_VCOMISD: vcomisd */ 0, { 0 } }, { /* X86_VCOMISDZrrb, X86_INS_VCOMISD: vcomisd */ 0, { 0 } }, { /* X86_VCOMISDrm, X86_INS_VCOMISD: vcomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISDrm_Int, X86_INS_VCOMISD: vcomisd */ 0, { 0 } }, { /* X86_VCOMISDrr, X86_INS_VCOMISD: vcomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISDrr_Int, X86_INS_VCOMISD: vcomisd */ 0, { 0 } }, { /* X86_VCOMISSZrm, X86_INS_VCOMISS: vcomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISSZrm_Int, X86_INS_VCOMISS: vcomiss */ 0, { 0 } }, { /* X86_VCOMISSZrr, X86_INS_VCOMISS: vcomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISSZrr_Int, X86_INS_VCOMISS: vcomiss */ 0, { 0 } }, { /* X86_VCOMISSZrrb, X86_INS_VCOMISS: vcomiss */ 0, { 0 } }, { /* X86_VCOMISSrm, X86_INS_VCOMISS: vcomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISSrm_Int, X86_INS_VCOMISS: vcomiss */ 0, { 0 } }, { /* X86_VCOMISSrr, X86_INS_VCOMISS: vcomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMISSrr_Int, X86_INS_VCOMISS: vcomiss */ 0, { 0 } }, { /* X86_VCOMPRESSPDZ128mr, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { 0 } }, { /* X86_VCOMPRESSPDZ128mrk, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZ128rr, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { 0 } }, { /* X86_VCOMPRESSPDZ128rrk, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZ128rrkz, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZ256mr, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { 0 } }, { /* X86_VCOMPRESSPDZ256mrk, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZ256rr, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { 0 } }, { /* X86_VCOMPRESSPDZ256rrk, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZ256rrkz, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZmr, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { 0 } }, { /* X86_VCOMPRESSPDZmrk, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZrr, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { 0 } }, { /* X86_VCOMPRESSPDZrrk, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPDZrrkz, X86_INS_VCOMPRESSPD: vcompresspd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZ128mr, X86_INS_VCOMPRESSPS: vcompressps */ 0, { 0 } }, { /* X86_VCOMPRESSPSZ128mrk, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZ128rr, X86_INS_VCOMPRESSPS: vcompressps */ 0, { 0 } }, { /* X86_VCOMPRESSPSZ128rrk, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZ128rrkz, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZ256mr, X86_INS_VCOMPRESSPS: vcompressps */ 0, { 0 } }, { /* X86_VCOMPRESSPSZ256mrk, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZ256rr, X86_INS_VCOMPRESSPS: vcompressps */ 0, { 0 } }, { /* X86_VCOMPRESSPSZ256rrk, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZ256rrkz, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZmr, X86_INS_VCOMPRESSPS: vcompressps */ 0, { 0 } }, { /* X86_VCOMPRESSPSZmrk, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZrr, X86_INS_VCOMPRESSPS: vcompressps */ 0, { 0 } }, { /* X86_VCOMPRESSPSZrrk, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCOMPRESSPSZrrkz, X86_INS_VCOMPRESSPS: vcompressps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PDYrm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PDYrr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PDZ128rm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rmb, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rmbk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rmbkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rmk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rmkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rrk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ128rrkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rmb, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rmbk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rmbkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rmk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rmkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rrk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZ256rrkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PDZrmb, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrmbk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrmbkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrmk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrmkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PDZrrk, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDZrrkz, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { 0 } }, { /* X86_VCVTDQ2PDrm, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PDrr, X86_INS_VCVTDQ2PD: vcvtdq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PSYrm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PSYrr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PSZ128rm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rmb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rmbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rmbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rmk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rmkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rrk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ128rrkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rmb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rmbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rmbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rmk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rmkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rrk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZ256rrkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PSZrmb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrmbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrmbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrmk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrmkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PSZrrb, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTDQ2PSZrrbk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrrbkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrrk, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSZrrkz, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { 0 } }, { /* X86_VCVTDQ2PSrm, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTDQ2PSrr, X86_INS_VCVTDQ2PS: vcvtdq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2DQYrm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2DQYrr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2DQZ128rm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rmb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rmbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rmbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rmk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rmkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rrk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ128rrkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rmb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rmbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rmbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rmk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rmkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rrk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZ256rrkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2DQZrmb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrmbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrmbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrmk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrmkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2DQZrrb, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPD2DQZrrbk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrrbkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrrk, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQZrrkz, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQrm, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { 0 } }, { /* X86_VCVTPD2DQrr, X86_INS_VCVTPD2DQ: vcvtpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2PSYrm, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2PSYrr, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2PSZ128rm, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rmb, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rmbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rmbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rmk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rmkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rr, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rrk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ128rrkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rm, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rmb, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rmbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rmbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rmk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rmkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rr, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rrk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZ256rrkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrm, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2PSZrmb, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrmbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrmbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrmk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrmkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrr, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2PSZrrb, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPD2PSZrrbk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrrbkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrrk, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSZrrkz, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSrm, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { 0 } }, { /* X86_VCVTPD2PSrr, X86_INS_VCVTPD2PS: vcvtpd2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2QQZ128rm, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rmb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rmbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rmbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rmk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rmkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rr, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rrk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ128rrkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rm, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rmb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rmbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rmbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rmk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rmkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rr, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rrk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZ256rrkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrm, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrmb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrmbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrmbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrmk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrmkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrr, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrrb, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrrbk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrrbkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrrk, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2QQZrrkz, X86_INS_VCVTPD2QQ: vcvtpd2qq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rm, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rmb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rmbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rmbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rmk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rmkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rr, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rrk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ128rrkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rm, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rmb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rmbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rmbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rmk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rmkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rr, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rrk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZ256rrkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrm, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2UDQZrmb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrmbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrmbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrmk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrmkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrr, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPD2UDQZrrb, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPD2UDQZrrbk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrrbkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrrk, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UDQZrrkz, X86_INS_VCVTPD2UDQ: vcvtpd2udq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rm, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rmb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rmbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rmbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rmk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rmkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rr, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rrk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ128rrkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rm, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rmb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rmbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rmbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rmk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rmkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rr, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rrk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZ256rrkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrm, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrmb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrmbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrmbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrmk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrmkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrr, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrrb, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrrbk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrrbkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrrk, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPD2UQQZrrkz, X86_INS_VCVTPD2UQQ: vcvtpd2uqq */ 0, { 0 } }, { /* X86_VCVTPH2PSYrm, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPH2PSYrr, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPH2PSZ128rm, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ128rmk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ128rmkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ128rr, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ128rrk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ128rrkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ256rm, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ256rmk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ256rmkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ256rr, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ256rrk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZ256rrkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrm, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPH2PSZrmk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrmkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrr, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPH2PSZrrb, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrrbk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrrbkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrrk, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSZrrkz, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { 0 } }, { /* X86_VCVTPH2PSrm, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPH2PSrr, X86_INS_VCVTPH2PS: vcvtph2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2DQYrm, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2DQYrr, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2DQZ128rm, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rmb, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rmbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rmbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rmk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rmkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rr, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rrk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ128rrkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rm, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rmb, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rmbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rmbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rmk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rmkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rr, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rrk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZ256rrkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrm, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2DQZrmb, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrmbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrmbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrmk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrmkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrr, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2DQZrrb, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2DQZrrbk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrrbkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrrk, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQZrrkz, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { 0 } }, { /* X86_VCVTPS2DQrm, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2DQrr, X86_INS_VCVTPS2DQ: vcvtps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PDYrm, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PDYrr, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PDZ128rm, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rmb, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rmbk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rmbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rmk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rmkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rr, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rrk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ128rrkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rm, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rmb, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rmbk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rmbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rmk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rmkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rr, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rrk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZ256rrkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrm, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PDZrmb, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrmbk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrmbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrmk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrmkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrr, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PDZrrb, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrrbk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrrbkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrrk, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDZrrkz, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { 0 } }, { /* X86_VCVTPS2PDrm, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PDrr, X86_INS_VCVTPS2PD: vcvtps2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2PHYmr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2PHYrr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2PHZ128mr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ128mrk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ128rr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ128rrk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ128rrkz, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ256mr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ256mrk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ256rr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ256rrk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZ256rrkz, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZmr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2PHZmrk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZrr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2PHZrrb, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZrrbk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZrrbkz, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZrrk, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHZrrkz, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { 0 } }, { /* X86_VCVTPS2PHmr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2PHrr, X86_INS_VCVTPS2PH: vcvtps2ph */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2QQZ128rm, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rmb, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rmbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rmbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rmk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rmkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rr, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rrk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ128rrkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rm, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rmb, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rmbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rmbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rmk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rmkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rr, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rrk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZ256rrkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrm, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrmb, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrmbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrmbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrmk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrmkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrr, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrrb, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrrbk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrrbkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrrk, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2QQZrrkz, X86_INS_VCVTPS2QQ: vcvtps2qq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rm, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rmb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rmbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rmbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rmk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rmkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rr, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rrk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ128rrkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rm, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rmb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rmbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rmbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rmk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rmkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rr, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rrk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZ256rrkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrm, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2UDQZrmb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrmbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrmbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrmk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrmkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrr, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTPS2UDQZrrb, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTPS2UDQZrrbk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrrbkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrrk, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UDQZrrkz, X86_INS_VCVTPS2UDQ: vcvtps2udq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rm, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rmb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rmbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rmbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rmk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rmkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rr, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rrk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ128rrkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rm, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rmb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rmbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rmbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rmk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rmkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rr, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rrk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZ256rrkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrm, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrmb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrmbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrmbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrmk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrmkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrr, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrrb, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrrbk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrrbkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrrk, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTPS2UQQZrrkz, X86_INS_VCVTPS2UQQ: vcvtps2uqq */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rm, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rmb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rmbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rmbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rmk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rmkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rr, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rrk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ128rrkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rm, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rmb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rmbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rmbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rmk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rmkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rr, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rrk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZ256rrkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrm, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrmb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrmbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrmbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrmk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrmkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrr, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrrb, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrrbk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrrbkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrrk, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PDZrrkz, X86_INS_VCVTQQ2PD: vcvtqq2pd */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rm, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rmb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rmbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rmbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rmk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rmkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rr, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rrk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ128rrkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rm, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rmb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rmbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rmbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rmk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rmkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rr, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rrk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZ256rrkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrm, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrmb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrmbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrmbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrmk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrmkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrr, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrrb, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrrbk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrrbkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrrk, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTQQ2PSZrrkz, X86_INS_VCVTQQ2PS: vcvtqq2ps */ 0, { 0 } }, { /* X86_VCVTSD2SI64Zrm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SI64Zrr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SI64Zrrb_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SI64rm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SI64rr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SIZrm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SIZrr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SIZrrb_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SIrm_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SIrr_Int, X86_INS_VCVTSD2SI: vcvtsd2si */ 0, { 0 } }, { /* X86_VCVTSD2SSZrm, X86_INS_VCVTSD2SS: vcvtsd2ss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSD2SSZrm_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrm_Intk, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrm_Intkz, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrr, X86_INS_VCVTSD2SS: vcvtsd2ss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSD2SSZrr_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrr_Intk, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrr_Intkz, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrrb_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrrb_Intk, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSZrrb_Intkz, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSrm, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSD2SSrm_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2SSrr, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSD2SSrr_Int, X86_INS_VCVTSD2SS: vcvtsd2ss */ 0, { 0 } }, { /* X86_VCVTSD2USI64Zrm_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ 0, { 0 } }, { /* X86_VCVTSD2USI64Zrr_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ 0, { 0 } }, { /* X86_VCVTSD2USI64Zrrb_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ 0, { 0 } }, { /* X86_VCVTSD2USIZrm_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ 0, { 0 } }, { /* X86_VCVTSD2USIZrr_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ 0, { 0 } }, { /* X86_VCVTSD2USIZrrb_Int, X86_INS_VCVTSD2USI: vcvtsd2usi */ 0, { 0 } }, { /* X86_VCVTSI2SDZrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SDZrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI2SDZrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SDZrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI2SDZrrb_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI2SDrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SDrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI2SDrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SDrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI2SSZrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SSZrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI2SSZrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SSZrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI2SSZrrb_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI2SSrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SSrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI2SSrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI2SSrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SDZrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI642SDZrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SDZrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI642SDZrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SDZrrb_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SDrm, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SDrm_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SDrr, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SDrr_Int, X86_INS_VCVTSI2SD: vcvtsi2sd */ 0, { 0 } }, { /* X86_VCVTSI642SSZrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI642SSZrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SSZrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSI642SSZrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SSZrrb_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SSrm, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SSrm_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SSrr, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSI642SSrr_Int, X86_INS_VCVTSI2SS: vcvtsi2ss */ 0, { 0 } }, { /* X86_VCVTSS2SDZrm, X86_INS_VCVTSS2SD: vcvtss2sd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSS2SDZrm_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrm_Intk, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrm_Intkz, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrr, X86_INS_VCVTSS2SD: vcvtss2sd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSS2SDZrr_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrr_Intk, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrr_Intkz, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrrb_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrrb_Intk, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDZrrb_Intkz, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDrm, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSS2SDrm_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SDrr, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTSS2SDrr_Int, X86_INS_VCVTSS2SD: vcvtss2sd */ 0, { 0 } }, { /* X86_VCVTSS2SI64Zrm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SI64Zrr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SI64Zrrb_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SI64rm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SI64rr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SIZrm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SIZrr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SIZrrb_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SIrm_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2SIrr_Int, X86_INS_VCVTSS2SI: vcvtss2si */ 0, { 0 } }, { /* X86_VCVTSS2USI64Zrm_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ 0, { 0 } }, { /* X86_VCVTSS2USI64Zrr_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ 0, { 0 } }, { /* X86_VCVTSS2USI64Zrrb_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ 0, { 0 } }, { /* X86_VCVTSS2USIZrm_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ 0, { 0 } }, { /* X86_VCVTSS2USIZrr_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ 0, { 0 } }, { /* X86_VCVTSS2USIZrrb_Int, X86_INS_VCVTSS2USI: vcvtss2usi */ 0, { 0 } }, { /* X86_VCVTTPD2DQYrm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2DQYrr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2DQZ128rm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rmb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rmbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rmbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rmk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rmkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rrk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ128rrkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rmb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rmbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rmbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rmk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rmkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rrk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZ256rrkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2DQZrmb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrmbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrmbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrmk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrmkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2DQZrrb, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrrbk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrrbkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrrk, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQZrrkz, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQrm, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { 0 } }, { /* X86_VCVTTPD2DQrr, X86_INS_VCVTTPD2DQ: vcvttpd2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2QQZ128rm, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rmb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rmbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rmbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rmk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rmkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rr, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rrk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ128rrkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rm, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rmb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rmbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rmbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rmk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rmkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rr, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rrk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZ256rrkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrm, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrmb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrmbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrmbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrmk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrmkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrr, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrrb, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrrbk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrrbkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrrk, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2QQZrrkz, X86_INS_VCVTTPD2QQ: vcvttpd2qq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rm, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rmb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rmbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rmbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rmk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rmkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rr, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rrk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ128rrkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rm, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rmb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rmbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rmbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rmk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rmkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rr, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rrk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZ256rrkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrm, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2UDQZrmb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrmbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrmbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrmk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrmkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrr, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPD2UDQZrrb, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrrbk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrrbkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrrk, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UDQZrrkz, X86_INS_VCVTTPD2UDQ: vcvttpd2udq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rm, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rmb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rmbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rmbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rmk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rmkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rr, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rrk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ128rrkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rm, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rmb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rmbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rmbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rmk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rmkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rr, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rrk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZ256rrkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrm, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrmb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrmbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrmbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrmk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrmkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrr, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrrb, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrrbk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrrbkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrrk, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPD2UQQZrrkz, X86_INS_VCVTTPD2UQQ: vcvttpd2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2DQYrm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2DQYrr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2DQZ128rm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rmb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rmbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rmbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rmk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rmkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rrk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ128rrkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rmb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rmbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rmbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rmk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rmkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rrk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZ256rrkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2DQZrmb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrmbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrmbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrmk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrmkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2DQZrrb, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrrbk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrrbkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrrk, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQZrrkz, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { 0 } }, { /* X86_VCVTTPS2DQrm, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2DQrr, X86_INS_VCVTTPS2DQ: vcvttps2dq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2QQZ128rm, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rmb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rmbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rmbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rmk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rmkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rr, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rrk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ128rrkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rm, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rmb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rmbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rmbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rmk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rmkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rr, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rrk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZ256rrkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrm, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrmb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrmbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrmbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrmk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrmkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrr, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrrb, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrrbk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrrbkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrrk, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2QQZrrkz, X86_INS_VCVTTPS2QQ: vcvttps2qq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rm, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rmb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rmbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rmbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rmk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rmkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rr, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rrk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ128rrkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rm, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rmb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rmbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rmbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rmk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rmkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rr, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rrk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZ256rrkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrm, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2UDQZrmb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrmbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrmbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrmk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrmkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrr, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTPS2UDQZrrb, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrrbk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrrbkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrrk, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UDQZrrkz, X86_INS_VCVTTPS2UDQ: vcvttps2udq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rm, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rmb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rmbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rmbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rmk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rmkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rr, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rrk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ128rrkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rm, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rmb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rmbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rmbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rmk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rmkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rr, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rrk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZ256rrkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrm, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrmb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrmbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrmbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrmk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrmkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrr, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrrb, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrrbk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrrbkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrrk, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTPS2UQQZrrkz, X86_INS_VCVTTPS2UQQ: vcvttps2uqq */ 0, { 0 } }, { /* X86_VCVTTSD2SI64Zrm, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SI64Zrm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SI64Zrr, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SI64Zrr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SI64Zrrb_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SI64rm, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SI64rm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SI64rr, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SI64rr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SIZrm, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SIZrm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SIZrr, X86_INS_VCVTTSD2SI: vcvttsd2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SIZrr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SIZrrb_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SIrm, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SIrm_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2SIrr, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2SIrr_Int, X86_INS_VCVTTSD2SI: vcvttsd2si */ 0, { 0 } }, { /* X86_VCVTTSD2USI64Zrm, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2USI64Zrm_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ 0, { 0 } }, { /* X86_VCVTTSD2USI64Zrr, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2USI64Zrr_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ 0, { 0 } }, { /* X86_VCVTTSD2USI64Zrrb_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ 0, { 0 } }, { /* X86_VCVTTSD2USIZrm, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2USIZrm_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ 0, { 0 } }, { /* X86_VCVTTSD2USIZrr, X86_INS_VCVTTSD2USI: vcvttsd2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSD2USIZrr_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ 0, { 0 } }, { /* X86_VCVTTSD2USIZrrb_Int, X86_INS_VCVTTSD2USI: vcvttsd2usi */ 0, { 0 } }, { /* X86_VCVTTSS2SI64Zrm, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SI64Zrm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SI64Zrr, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SI64Zrr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SI64Zrrb_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SI64rm, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SI64rm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SI64rr, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SI64rr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SIZrm, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SIZrm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SIZrr, X86_INS_VCVTTSS2SI: vcvttss2si $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SIZrr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SIZrrb_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SIrm, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SIrm_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2SIrr, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2SIrr_Int, X86_INS_VCVTTSS2SI: vcvttss2si */ 0, { 0 } }, { /* X86_VCVTTSS2USI64Zrm, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2USI64Zrm_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ 0, { 0 } }, { /* X86_VCVTTSS2USI64Zrr, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2USI64Zrr_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ 0, { 0 } }, { /* X86_VCVTTSS2USI64Zrrb_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ 0, { 0 } }, { /* X86_VCVTTSS2USIZrm, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2USIZrm_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ 0, { 0 } }, { /* X86_VCVTTSS2USIZrr, X86_INS_VCVTTSS2USI: vcvttss2usi $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTTSS2USIZrr_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ 0, { 0 } }, { /* X86_VCVTTSS2USIZrrb_Int, X86_INS_VCVTTSS2USI: vcvttss2usi */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rm, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rmb, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rmbk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rmbkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rmk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rmkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rr, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rrk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ128rrkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rm, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rmb, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rmbk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rmbkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rmk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rmkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rr, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rrk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZ256rrkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrm, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTUDQ2PDZrmb, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrmbk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrmbkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrmk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrmkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrr, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTUDQ2PDZrrk, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PDZrrkz, X86_INS_VCVTUDQ2PD: vcvtudq2pd */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rm, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rmb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rmbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rmbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rmk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rmkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rr, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rrk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ128rrkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rm, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rmb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rmbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rmbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rmk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rmkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rr, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rrk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZ256rrkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrm, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTUDQ2PSZrmb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrmbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrmbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrmk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrmkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrr, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VCVTUDQ2PSZrrb, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VCVTUDQ2PSZrrbk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrrbkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrrk, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUDQ2PSZrrkz, X86_INS_VCVTUDQ2PS: vcvtudq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rm, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rmb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rmbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rmbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rmk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rmkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rr, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rrk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ128rrkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rm, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rmb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rmbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rmbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rmk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rmkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rr, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rrk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZ256rrkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrm, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrmb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrmbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrmbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrmk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrmkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrr, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrrb, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrrbk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrrbkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrrk, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PDZrrkz, X86_INS_VCVTUQQ2PD: vcvtuqq2pd */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rm, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rmb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rmbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rmbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rmk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rmkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rr, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rrk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ128rrkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rm, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rmb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rmbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rmbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rmk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rmkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rr, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rrk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZ256rrkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrm, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrmb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrmbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrmbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrmk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrmkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrr, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrrb, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrrbk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrrbkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrrk, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUQQ2PSZrrkz, X86_INS_VCVTUQQ2PS: vcvtuqq2ps */ 0, { 0 } }, { /* X86_VCVTUSI2SDZrm, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI2SDZrm_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { 0 } }, { /* X86_VCVTUSI2SDZrr, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI2SDZrr_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { 0 } }, { /* X86_VCVTUSI2SSZrm, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI2SSZrm_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { 0 } }, { /* X86_VCVTUSI2SSZrr, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI2SSZrr_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { 0 } }, { /* X86_VCVTUSI2SSZrrb_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { 0 } }, { /* X86_VCVTUSI642SDZrm, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI642SDZrm_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { 0 } }, { /* X86_VCVTUSI642SDZrr, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI642SDZrr_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { 0 } }, { /* X86_VCVTUSI642SDZrrb_Int, X86_INS_VCVTUSI2SD: vcvtusi2sd */ 0, { 0 } }, { /* X86_VCVTUSI642SSZrm, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI642SSZrm_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { 0 } }, { /* X86_VCVTUSI642SSZrr, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCVTUSI642SSZrr_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { 0 } }, { /* X86_VCVTUSI642SSZrrb_Int, X86_INS_VCVTUSI2SS: vcvtusi2ss */ 0, { 0 } }, { /* X86_VDBPSADBWZ128rmi, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ128rmik, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ128rmikz, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ128rri, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ128rrik, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ128rrikz, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ256rmi, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ256rmik, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ256rmikz, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ256rri, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ256rrik, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZ256rrikz, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZrmi, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZrmik, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZrmikz, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZrri, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZrrik, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDBPSADBWZrrikz, X86_INS_VDBPSADBW: vdbpsadbw */ 0, { 0 } }, { /* X86_VDIVPDYrm, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDYrr, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rm, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rmb, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rmbk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rmbkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rmk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rmkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rr, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rrk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ128rrkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rm, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rmb, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rmbk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rmbkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rmk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rmkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rr, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rrk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZ256rrkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrm, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrmb, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrmbk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrmbkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrmk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrmkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrr, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrrb, X86_INS_VDIVPD: vdivpd */ 0, { 0 } }, { /* X86_VDIVPDZrrbk, X86_INS_VDIVPD: vdivpd */ 0, { 0 } }, { /* X86_VDIVPDZrrbkz, X86_INS_VDIVPD: vdivpd */ 0, { 0 } }, { /* X86_VDIVPDZrrk, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDZrrkz, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDrm, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPDrr, X86_INS_VDIVPD: vdivpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSYrm, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSYrr, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rm, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rmb, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rmbk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rmbkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rmk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rmkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rr, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rrk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ128rrkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rm, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rmb, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rmbk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rmbkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rmk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rmkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rr, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rrk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZ256rrkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrm, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrmb, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrmbk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrmbkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrmk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrmkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrr, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrrb, X86_INS_VDIVPS: vdivps */ 0, { 0 } }, { /* X86_VDIVPSZrrbk, X86_INS_VDIVPS: vdivps */ 0, { 0 } }, { /* X86_VDIVPSZrrbkz, X86_INS_VDIVPS: vdivps */ 0, { 0 } }, { /* X86_VDIVPSZrrk, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSZrrkz, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSrm, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVPSrr, X86_INS_VDIVPS: vdivps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrm, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrm_Int, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrm_Intk, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrm_Intkz, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrr, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrr_Int, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrr_Intk, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrr_Intkz, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDZrrb_Int, X86_INS_VDIVSD: vdivsd */ 0, { 0 } }, { /* X86_VDIVSDZrrb_Intk, X86_INS_VDIVSD: vdivsd */ 0, { 0 } }, { /* X86_VDIVSDZrrb_Intkz, X86_INS_VDIVSD: vdivsd */ 0, { 0 } }, { /* X86_VDIVSDrm, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDrm_Int, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDIVSDrr, X86_INS_VDIVSD: vdivsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSDrr_Int, X86_INS_VDIVSD: vdivsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrm, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrm_Int, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrm_Intk, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrm_Intkz, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrr, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrr_Int, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrr_Intk, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrr_Intkz, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSZrrb_Int, X86_INS_VDIVSS: vdivss */ 0, { 0 } }, { /* X86_VDIVSSZrrb_Intk, X86_INS_VDIVSS: vdivss */ 0, { 0 } }, { /* X86_VDIVSSZrrb_Intkz, X86_INS_VDIVSS: vdivss */ 0, { 0 } }, { /* X86_VDIVSSrm, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSrm_Int, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDIVSSrr, X86_INS_VDIVSS: vdivss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDIVSSrr_Int, X86_INS_VDIVSS: vdivss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VDPPDrmi, X86_INS_VDPPD: vdppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDPPDrri, X86_INS_VDPPD: vdppd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDPPSYrmi, X86_INS_VDPPS: vdpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDPPSYrri, X86_INS_VDPPS: vdpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDPPSrmi, X86_INS_VDPPS: vdpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VDPPSrri, X86_INS_VDPPS: vdpps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VERRm, X86_INS_VERR: verr */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VERRr, X86_INS_VERR: verr */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VERWm, X86_INS_VERW: verw */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VERWr, X86_INS_VERW: verw */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VEXP2PDZm, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZmb, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZmbk, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZmbkz, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZmk, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZmkz, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZr, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZrb, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZrbk, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZrbkz, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZrk, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PDZrkz, X86_INS_VEXP2PD: vexp2pd */ 0, { 0 } }, { /* X86_VEXP2PSZm, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZmb, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZmbk, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZmbkz, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZmk, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZmkz, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZr, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZrb, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZrbk, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZrbkz, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZrk, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXP2PSZrkz, X86_INS_VEXP2PS: vexp2ps */ 0, { 0 } }, { /* X86_VEXPANDPDZ128rm, X86_INS_VEXPANDPD: vexpandpd */ 0, { 0 } }, { /* X86_VEXPANDPDZ128rmk, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ128rmkz, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ128rr, X86_INS_VEXPANDPD: vexpandpd */ 0, { 0 } }, { /* X86_VEXPANDPDZ128rrk, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ128rrkz, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ256rm, X86_INS_VEXPANDPD: vexpandpd */ 0, { 0 } }, { /* X86_VEXPANDPDZ256rmk, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ256rmkz, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ256rr, X86_INS_VEXPANDPD: vexpandpd */ 0, { 0 } }, { /* X86_VEXPANDPDZ256rrk, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZ256rrkz, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZrm, X86_INS_VEXPANDPD: vexpandpd */ 0, { 0 } }, { /* X86_VEXPANDPDZrmk, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZrmkz, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZrr, X86_INS_VEXPANDPD: vexpandpd */ 0, { 0 } }, { /* X86_VEXPANDPDZrrk, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPDZrrkz, X86_INS_VEXPANDPD: vexpandpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ128rm, X86_INS_VEXPANDPS: vexpandps */ 0, { 0 } }, { /* X86_VEXPANDPSZ128rmk, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ128rmkz, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ128rr, X86_INS_VEXPANDPS: vexpandps */ 0, { 0 } }, { /* X86_VEXPANDPSZ128rrk, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ128rrkz, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ256rm, X86_INS_VEXPANDPS: vexpandps */ 0, { 0 } }, { /* X86_VEXPANDPSZ256rmk, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ256rmkz, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ256rr, X86_INS_VEXPANDPS: vexpandps */ 0, { 0 } }, { /* X86_VEXPANDPSZ256rrk, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZ256rrkz, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZrm, X86_INS_VEXPANDPS: vexpandps */ 0, { 0 } }, { /* X86_VEXPANDPSZrmk, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZrmkz, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZrr, X86_INS_VEXPANDPS: vexpandps */ 0, { 0 } }, { /* X86_VEXPANDPSZrrk, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXPANDPSZrrkz, X86_INS_VEXPANDPS: vexpandps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VEXTRACTF128mr, X86_INS_VEXTRACTF128: vextractf128 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VEXTRACTF128rr, X86_INS_VEXTRACTF128: vextractf128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VEXTRACTF32x4Z256mr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Z256mrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Z256rr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Z256rrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Z256rrkz, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Zmr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Zmrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Zrr, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Zrrk, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x4Zrrkz, X86_INS_VEXTRACTF32X4: vextractf32x4 */ 0, { 0 } }, { /* X86_VEXTRACTF32x8Zmr, X86_INS_VEXTRACTF32X8: vextractf32x8 */ 0, { 0 } }, { /* X86_VEXTRACTF32x8Zmrk, X86_INS_VEXTRACTF32X8: vextractf32x8 */ 0, { 0 } }, { /* X86_VEXTRACTF32x8Zrr, X86_INS_VEXTRACTF32X8: vextractf32x8 */ 0, { 0 } }, { /* X86_VEXTRACTF32x8Zrrk, X86_INS_VEXTRACTF32X8: vextractf32x8 */ 0, { 0 } }, { /* X86_VEXTRACTF32x8Zrrkz, X86_INS_VEXTRACTF32X8: vextractf32x8 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Z256mr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Z256mrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Z256rr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Z256rrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Z256rrkz, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Zmr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Zmrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Zrr, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Zrrk, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x2Zrrkz, X86_INS_VEXTRACTF64X2: vextractf64x2 */ 0, { 0 } }, { /* X86_VEXTRACTF64x4Zmr, X86_INS_VEXTRACTF64X4: vextractf64x4 */ 0, { 0 } }, { /* X86_VEXTRACTF64x4Zmrk, X86_INS_VEXTRACTF64X4: vextractf64x4 */ 0, { 0 } }, { /* X86_VEXTRACTF64x4Zrr, X86_INS_VEXTRACTF64X4: vextractf64x4 */ 0, { 0 } }, { /* X86_VEXTRACTF64x4Zrrk, X86_INS_VEXTRACTF64X4: vextractf64x4 */ 0, { 0 } }, { /* X86_VEXTRACTF64x4Zrrkz, X86_INS_VEXTRACTF64X4: vextractf64x4 */ 0, { 0 } }, { /* X86_VEXTRACTI128mr, X86_INS_VEXTRACTI128: vextracti128 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VEXTRACTI128rr, X86_INS_VEXTRACTI128: vextracti128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VEXTRACTI32x4Z256mr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Z256mrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Z256rr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Z256rrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Z256rrkz, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Zmr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Zmrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Zrr, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Zrrk, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x4Zrrkz, X86_INS_VEXTRACTI32X4: vextracti32x4 */ 0, { 0 } }, { /* X86_VEXTRACTI32x8Zmr, X86_INS_VEXTRACTI32X8: vextracti32x8 */ 0, { 0 } }, { /* X86_VEXTRACTI32x8Zmrk, X86_INS_VEXTRACTI32X8: vextracti32x8 */ 0, { 0 } }, { /* X86_VEXTRACTI32x8Zrr, X86_INS_VEXTRACTI32X8: vextracti32x8 */ 0, { 0 } }, { /* X86_VEXTRACTI32x8Zrrk, X86_INS_VEXTRACTI32X8: vextracti32x8 */ 0, { 0 } }, { /* X86_VEXTRACTI32x8Zrrkz, X86_INS_VEXTRACTI32X8: vextracti32x8 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Z256mr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Z256mrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Z256rr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Z256rrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Z256rrkz, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Zmr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Zmrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Zrr, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Zrrk, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x2Zrrkz, X86_INS_VEXTRACTI64X2: vextracti64x2 */ 0, { 0 } }, { /* X86_VEXTRACTI64x4Zmr, X86_INS_VEXTRACTI64X4: vextracti64x4 */ 0, { 0 } }, { /* X86_VEXTRACTI64x4Zmrk, X86_INS_VEXTRACTI64X4: vextracti64x4 */ 0, { 0 } }, { /* X86_VEXTRACTI64x4Zrr, X86_INS_VEXTRACTI64X4: vextracti64x4 */ 0, { 0 } }, { /* X86_VEXTRACTI64x4Zrrk, X86_INS_VEXTRACTI64X4: vextracti64x4 */ 0, { 0 } }, { /* X86_VEXTRACTI64x4Zrrkz, X86_INS_VEXTRACTI64X4: vextracti64x4 */ 0, { 0 } }, { /* X86_VEXTRACTPSZmr, X86_INS_VEXTRACTPS: vextractps */ 0, { 0 } }, { /* X86_VEXTRACTPSZrr, X86_INS_VEXTRACTPS: vextractps */ 0, { 0 } }, { /* X86_VEXTRACTPSmr, X86_INS_VEXTRACTPS: vextractps */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VEXTRACTPSrr, X86_INS_VEXTRACTPS: vextractps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFIXUPIMMPDZ128rmbi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rmbik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rmbikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rmi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rmik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rmikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rri, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rrik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ128rrikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rmbi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rmbik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rmbikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rmi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rmik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rmikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rri, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rrik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZ256rrikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrmbi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrmbik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrmbikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrmi, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrmik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrmikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrri, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrrib, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrribk, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrribkz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrrik, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPDZrrikz, X86_INS_VFIXUPIMMPD: vfixupimmpd */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rmbi, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rmbik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rmbikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rmi, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rmik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rmikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rri, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rrik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ128rrikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rmbi, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rmbik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rmbikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rmi, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rmik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rmikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rri, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rrik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZ256rrikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrmbi, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrmbik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrmbikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrmi, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrmik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrmikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrri, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrrib, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrribk, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrribkz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrrik, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMPSZrrikz, X86_INS_VFIXUPIMMPS: vfixupimmps */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrmi, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrmik, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrmikz, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrri, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrrib, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrribk, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrribkz, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrrik, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSDZrrikz, X86_INS_VFIXUPIMMSD: vfixupimmsd */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrmi, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrmik, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrmikz, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrri, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrrib, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrribk, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrribkz, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrrik, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFIXUPIMMSSZrrikz, X86_INS_VFIXUPIMMSS: vfixupimmss */ 0, { 0 } }, { /* X86_VFMADD132PDYm, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDYr, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128m, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PDZ128mb, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PDZ128mbk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128mbkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128mk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128mkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128r, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128rk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ128rkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256m, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PDZ256mb, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PDZ256mbk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256mbkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256mk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256mkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256r, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256rk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZ256rkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZm, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PDZmb, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PDZmbk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZmbkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZmk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZmkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZr, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZrb, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZrbk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZrbkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZrk, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDZrkz, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDm, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PDr, X86_INS_VFMADD132PD: vfmadd132pd */ 0, { 0 } }, { /* X86_VFMADD132PSYm, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSYr, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128m, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PSZ128mb, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PSZ128mbk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128mbkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128mk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128mkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128r, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128rk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ128rkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256m, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PSZ256mb, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PSZ256mbk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256mbkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256mk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256mkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256r, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256rk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZ256rkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZm, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PSZmb, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADD132PSZmbk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZmbkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZmk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZmkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZr, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZrb, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZrbk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZrbkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZrk, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSZrkz, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSm, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132PSr, X86_INS_VFMADD132PS: vfmadd132ps */ 0, { 0 } }, { /* X86_VFMADD132SDZm, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZm_Int, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZm_Intk, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZm_Intkz, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZr, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZr_Int, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZr_Intk, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZr_Intkz, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZrb, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZrb_Int, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZrb_Intk, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDZrb_Intkz, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDm, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDm_Int, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDr, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SDr_Int, X86_INS_VFMADD132SD: vfmadd132sd */ 0, { 0 } }, { /* X86_VFMADD132SSZm, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZm_Int, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZm_Intk, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZm_Intkz, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZr, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZr_Int, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZr_Intk, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZr_Intkz, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZrb, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZrb_Int, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZrb_Intk, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSZrb_Intkz, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSm, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSm_Int, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSr, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD132SSr_Int, X86_INS_VFMADD132SS: vfmadd132ss */ 0, { 0 } }, { /* X86_VFMADD213PDYm, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDYr, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128m, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128mb, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128mbk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128mbkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128mk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128mkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128r, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128rk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ128rkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256m, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256mb, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256mbk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256mbkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256mk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256mkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256r, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256rk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZ256rkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZm, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZmb, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZmbk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZmbkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZmk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZmkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZr, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZrb, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZrbk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZrbkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZrk, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDZrkz, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDm, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PDr, X86_INS_VFMADD213PD: vfmadd213pd */ 0, { 0 } }, { /* X86_VFMADD213PSYm, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSYr, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128m, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128mb, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128mbk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128mbkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128mk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128mkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128r, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128rk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ128rkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256m, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256mb, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256mbk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256mbkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256mk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256mkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256r, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256rk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZ256rkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZm, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZmb, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZmbk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZmbkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZmk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZmkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZr, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZrb, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZrbk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZrbkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZrk, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSZrkz, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSm, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213PSr, X86_INS_VFMADD213PS: vfmadd213ps */ 0, { 0 } }, { /* X86_VFMADD213SDZm, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZm_Int, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZm_Intk, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZm_Intkz, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZr, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZr_Int, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZr_Intk, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZr_Intkz, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZrb, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZrb_Int, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZrb_Intk, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDZrb_Intkz, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDm, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDm_Int, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDr, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SDr_Int, X86_INS_VFMADD213SD: vfmadd213sd */ 0, { 0 } }, { /* X86_VFMADD213SSZm, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZm_Int, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZm_Intk, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZm_Intkz, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZr, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZr_Int, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZr_Intk, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZr_Intkz, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZrb, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZrb_Int, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZrb_Intk, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSZrb_Intkz, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSm, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSm_Int, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSr, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD213SSr_Int, X86_INS_VFMADD213SS: vfmadd213ss */ 0, { 0 } }, { /* X86_VFMADD231PDYm, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDYr, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128m, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128mb, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128mbk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128mbkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128mk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128mkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128r, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128rk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ128rkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256m, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256mb, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256mbk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256mbkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256mk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256mkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256r, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256rk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZ256rkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZm, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZmb, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZmbk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZmbkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZmk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZmkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZr, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZrb, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZrbk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZrbkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZrk, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDZrkz, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDm, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PDr, X86_INS_VFMADD231PD: vfmadd231pd */ 0, { 0 } }, { /* X86_VFMADD231PSYm, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSYr, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128m, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128mb, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128mbk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128mbkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128mk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128mkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128r, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128rk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ128rkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256m, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256mb, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256mbk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256mbkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256mk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256mkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256r, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256rk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZ256rkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZm, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZmb, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZmbk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZmbkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZmk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZmkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZr, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZrb, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZrbk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZrbkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZrk, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSZrkz, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSm, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231PSr, X86_INS_VFMADD231PS: vfmadd231ps */ 0, { 0 } }, { /* X86_VFMADD231SDZm, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZm_Int, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZm_Intk, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZm_Intkz, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZr, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZr_Int, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZr_Intk, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZr_Intkz, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZrb, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZrb_Int, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZrb_Intk, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDZrb_Intkz, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDm, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDm_Int, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDr, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SDr_Int, X86_INS_VFMADD231SD: vfmadd231sd */ 0, { 0 } }, { /* X86_VFMADD231SSZm, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZm_Int, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZm_Intk, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZm_Intkz, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZr, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZr_Int, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZr_Intk, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZr_Intkz, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZrb, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZrb_Int, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZrb_Intk, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSZrb_Intkz, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSm, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSm_Int, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSr, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADD231SSr_Int, X86_INS_VFMADD231SS: vfmadd231ss */ 0, { 0 } }, { /* X86_VFMADDPD4Ymr, X86_INS_VFMADDPD: vfmaddpd */ 0, { 0 } }, { /* X86_VFMADDPD4Yrm, X86_INS_VFMADDPD: vfmaddpd */ 0, { 0 } }, { /* X86_VFMADDPD4Yrr, X86_INS_VFMADDPD: vfmaddpd */ 0, { 0 } }, { /* X86_VFMADDPD4Yrr_REV, X86_INS_VFMADDPD: vfmaddpd */ 0, { 0 } }, { /* X86_VFMADDPD4mr, X86_INS_VFMADDPD: vfmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPD4rm, X86_INS_VFMADDPD: vfmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPD4rr, X86_INS_VFMADDPD: vfmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPD4rr_REV, X86_INS_VFMADDPD: vfmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPS4Ymr, X86_INS_VFMADDPS: vfmaddps */ 0, { 0 } }, { /* X86_VFMADDPS4Yrm, X86_INS_VFMADDPS: vfmaddps */ 0, { 0 } }, { /* X86_VFMADDPS4Yrr, X86_INS_VFMADDPS: vfmaddps */ 0, { 0 } }, { /* X86_VFMADDPS4Yrr_REV, X86_INS_VFMADDPS: vfmaddps */ 0, { 0 } }, { /* X86_VFMADDPS4mr, X86_INS_VFMADDPS: vfmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPS4rm, X86_INS_VFMADDPS: vfmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPS4rr, X86_INS_VFMADDPS: vfmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDPS4rr_REV, X86_INS_VFMADDPS: vfmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSD4mr, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSD4mr_Int, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFMADDSD4rm, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSD4rm_Int, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFMADDSD4rr, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSD4rr_Int, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSD4rr_Int_REV, X86_INS_VFMADDSD: vfmaddsd */ 0, { 0 } }, { /* X86_VFMADDSD4rr_REV, X86_INS_VFMADDSD: vfmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSS4mr, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSS4mr_Int, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFMADDSS4rm, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSS4rm_Int, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFMADDSS4rr, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSS4rr_Int, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSS4rr_Int_REV, X86_INS_VFMADDSS: vfmaddss */ 0, { 0 } }, { /* X86_VFMADDSS4rr_REV, X86_INS_VFMADDSS: vfmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDYm, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDYr, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128m, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDZ128mb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDZ128mbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128mbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128mk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128mkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128r, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128rk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ128rkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256m, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDZ256mb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDZ256mbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256mbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256mk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256mkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256r, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256rk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZ256rkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZm, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDZmb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PDZmbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZmbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZmk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZmkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZr, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZrb, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZrbk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZrbkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZrk, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDZrkz, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDm, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PDr, X86_INS_VFMADDSUB132PD: vfmaddsub132pd */ 0, { 0 } }, { /* X86_VFMADDSUB132PSYm, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSYr, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128m, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PSZ128mb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PSZ128mbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128mbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128mk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128mkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128r, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128rk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ128rkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256m, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PSZ256mb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PSZ256mbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256mbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256mk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256mkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256r, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256rk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZ256rkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZm, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PSZmb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUB132PSZmbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZmbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZmk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZmkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZr, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZrb, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZrbk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZrbkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZrk, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSZrkz, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSm, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB132PSr, X86_INS_VFMADDSUB132PS: vfmaddsub132ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PDYm, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDYr, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128m, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128mb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128mbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128mbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128mk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128mkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128r, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128rk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ128rkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256m, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256mb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256mbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256mbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256mk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256mkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256r, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256rk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZ256rkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZm, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZmb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZmbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZmbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZmk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZmkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZr, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZrb, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZrbk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZrbkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZrk, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDZrkz, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDm, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PDr, X86_INS_VFMADDSUB213PD: vfmaddsub213pd */ 0, { 0 } }, { /* X86_VFMADDSUB213PSYm, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSYr, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128m, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128mb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128mbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128mbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128mk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128mkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128r, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128rk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ128rkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256m, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256mb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256mbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256mbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256mk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256mkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256r, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256rk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZ256rkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZm, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZmb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZmbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZmbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZmk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZmkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZr, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZrb, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZrbk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZrbkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZrk, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSZrkz, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSm, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB213PSr, X86_INS_VFMADDSUB213PS: vfmaddsub213ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PDYm, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDYr, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128m, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128mb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128mbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128mbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128mk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128mkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128r, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128rk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ128rkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256m, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256mb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256mbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256mbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256mk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256mkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256r, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256rk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZ256rkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZm, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZmb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZmbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZmbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZmk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZmkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZr, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZrb, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZrbk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZrbkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZrk, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDZrkz, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDm, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PDr, X86_INS_VFMADDSUB231PD: vfmaddsub231pd */ 0, { 0 } }, { /* X86_VFMADDSUB231PSYm, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSYr, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128m, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128mb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128mbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128mbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128mk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128mkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128r, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128rk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ128rkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256m, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256mb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256mbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256mbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256mk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256mkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256r, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256rk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZ256rkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZm, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZmb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZmbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZmbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZmk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZmkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZr, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZrb, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZrbk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZrbkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZrk, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSZrkz, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSm, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUB231PSr, X86_INS_VFMADDSUB231PS: vfmaddsub231ps */ 0, { 0 } }, { /* X86_VFMADDSUBPD4Ymr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { 0 } }, { /* X86_VFMADDSUBPD4Yrm, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { 0 } }, { /* X86_VFMADDSUBPD4Yrr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { 0 } }, { /* X86_VFMADDSUBPD4Yrr_REV, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { 0 } }, { /* X86_VFMADDSUBPD4mr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPD4rm, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPD4rr, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPD4rr_REV, X86_INS_VFMADDSUBPD: vfmaddsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPS4Ymr, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { 0 } }, { /* X86_VFMADDSUBPS4Yrm, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { 0 } }, { /* X86_VFMADDSUBPS4Yrr, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { 0 } }, { /* X86_VFMADDSUBPS4Yrr_REV, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { 0 } }, { /* X86_VFMADDSUBPS4mr, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPS4rm, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPS4rr, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMADDSUBPS4rr_REV, X86_INS_VFMADDSUBPS: vfmaddsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDYm, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDYr, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128m, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDZ128mb, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDZ128mbk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128mbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128mk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128mkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128r, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128rk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ128rkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256m, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDZ256mb, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDZ256mbk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256mbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256mk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256mkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256r, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256rk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZ256rkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZm, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDZmb, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PDZmbk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZmbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZmk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZmkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZr, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZrb, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZrbk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZrbkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZrk, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDZrkz, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDm, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PDr, X86_INS_VFMSUB132PD: vfmsub132pd */ 0, { 0 } }, { /* X86_VFMSUB132PSYm, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSYr, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128m, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PSZ128mb, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PSZ128mbk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128mbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128mk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128mkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128r, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128rk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ128rkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256m, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PSZ256mb, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PSZ256mbk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256mbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256mk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256mkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256r, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256rk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZ256rkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZm, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PSZmb, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUB132PSZmbk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZmbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZmk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZmkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZr, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZrb, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZrbk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZrbkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZrk, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSZrkz, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSm, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132PSr, X86_INS_VFMSUB132PS: vfmsub132ps */ 0, { 0 } }, { /* X86_VFMSUB132SDZm, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZm_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZm_Intk, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZm_Intkz, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZr, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZr_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZr_Intk, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZr_Intkz, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZrb, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZrb_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZrb_Intk, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDZrb_Intkz, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDm, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDm_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDr, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SDr_Int, X86_INS_VFMSUB132SD: vfmsub132sd */ 0, { 0 } }, { /* X86_VFMSUB132SSZm, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZm_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZm_Intk, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZm_Intkz, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZr, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZr_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZr_Intk, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZr_Intkz, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZrb, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZrb_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZrb_Intk, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSZrb_Intkz, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSm, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSm_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSr, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB132SSr_Int, X86_INS_VFMSUB132SS: vfmsub132ss */ 0, { 0 } }, { /* X86_VFMSUB213PDYm, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDYr, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128m, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128mb, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128mbk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128mbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128mk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128mkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128r, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128rk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ128rkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256m, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256mb, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256mbk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256mbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256mk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256mkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256r, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256rk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZ256rkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZm, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZmb, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZmbk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZmbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZmk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZmkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZr, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZrb, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZrbk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZrbkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZrk, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDZrkz, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDm, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PDr, X86_INS_VFMSUB213PD: vfmsub213pd */ 0, { 0 } }, { /* X86_VFMSUB213PSYm, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSYr, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128m, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128mb, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128mbk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128mbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128mk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128mkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128r, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128rk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ128rkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256m, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256mb, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256mbk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256mbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256mk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256mkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256r, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256rk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZ256rkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZm, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZmb, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZmbk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZmbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZmk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZmkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZr, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZrb, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZrbk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZrbkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZrk, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSZrkz, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSm, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213PSr, X86_INS_VFMSUB213PS: vfmsub213ps */ 0, { 0 } }, { /* X86_VFMSUB213SDZm, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZm_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZm_Intk, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZm_Intkz, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZr, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZr_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZr_Intk, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZr_Intkz, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZrb, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZrb_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZrb_Intk, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDZrb_Intkz, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDm, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDm_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDr, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SDr_Int, X86_INS_VFMSUB213SD: vfmsub213sd */ 0, { 0 } }, { /* X86_VFMSUB213SSZm, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZm_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZm_Intk, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZm_Intkz, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZr, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZr_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZr_Intk, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZr_Intkz, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZrb, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZrb_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZrb_Intk, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSZrb_Intkz, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSm, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSm_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSr, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB213SSr_Int, X86_INS_VFMSUB213SS: vfmsub213ss */ 0, { 0 } }, { /* X86_VFMSUB231PDYm, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDYr, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128m, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128mb, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128mbk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128mbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128mk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128mkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128r, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128rk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ128rkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256m, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256mb, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256mbk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256mbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256mk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256mkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256r, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256rk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZ256rkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZm, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZmb, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZmbk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZmbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZmk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZmkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZr, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZrb, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZrbk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZrbkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZrk, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDZrkz, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDm, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PDr, X86_INS_VFMSUB231PD: vfmsub231pd */ 0, { 0 } }, { /* X86_VFMSUB231PSYm, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSYr, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128m, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128mb, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128mbk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128mbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128mk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128mkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128r, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128rk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ128rkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256m, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256mb, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256mbk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256mbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256mk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256mkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256r, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256rk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZ256rkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZm, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZmb, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZmbk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZmbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZmk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZmkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZr, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZrb, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZrbk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZrbkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZrk, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSZrkz, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSm, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231PSr, X86_INS_VFMSUB231PS: vfmsub231ps */ 0, { 0 } }, { /* X86_VFMSUB231SDZm, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZm_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZm_Intk, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZm_Intkz, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZr, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZr_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZr_Intk, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZr_Intkz, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZrb, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZrb_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZrb_Intk, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDZrb_Intkz, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDm, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDm_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDr, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SDr_Int, X86_INS_VFMSUB231SD: vfmsub231sd */ 0, { 0 } }, { /* X86_VFMSUB231SSZm, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZm_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZm_Intk, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZm_Intkz, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZr, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZr_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZr_Intk, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZr_Intkz, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZrb, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZrb_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZrb_Intk, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSZrb_Intkz, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSm, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSm_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSr, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUB231SSr_Int, X86_INS_VFMSUB231SS: vfmsub231ss */ 0, { 0 } }, { /* X86_VFMSUBADD132PDYm, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDYr, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128m, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PDZ128mb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PDZ128mbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128mbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128mk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128mkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128r, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128rk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ128rkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256m, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PDZ256mb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PDZ256mbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256mbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256mk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256mkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256r, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256rk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZ256rkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZm, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PDZmb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PDZmbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZmbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZmk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZmkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZr, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZrb, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZrbk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZrbkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZrk, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDZrkz, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDm, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PDr, X86_INS_VFMSUBADD132PD: vfmsubadd132pd */ 0, { 0 } }, { /* X86_VFMSUBADD132PSYm, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSYr, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128m, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PSZ128mb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PSZ128mbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128mbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128mk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128mkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128r, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128rk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ128rkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256m, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PSZ256mb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PSZ256mbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256mbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256mk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256mkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256r, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256rk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZ256rkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZm, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PSZmb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADD132PSZmbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZmbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZmk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZmkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZr, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZrb, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZrbk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZrbkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZrk, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSZrkz, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSm, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD132PSr, X86_INS_VFMSUBADD132PS: vfmsubadd132ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PDYm, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDYr, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128m, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128mb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128mbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128mbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128mk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128mkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128r, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128rk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ128rkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256m, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256mb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256mbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256mbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256mk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256mkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256r, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256rk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZ256rkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZm, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZmb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZmbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZmbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZmk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZmkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZr, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZrb, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZrbk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZrbkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZrk, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDZrkz, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDm, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PDr, X86_INS_VFMSUBADD213PD: vfmsubadd213pd */ 0, { 0 } }, { /* X86_VFMSUBADD213PSYm, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSYr, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128m, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128mb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128mbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128mbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128mk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128mkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128r, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128rk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ128rkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256m, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256mb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256mbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256mbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256mk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256mkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256r, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256rk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZ256rkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZm, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZmb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZmbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZmbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZmk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZmkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZr, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZrb, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZrbk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZrbkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZrk, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSZrkz, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSm, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD213PSr, X86_INS_VFMSUBADD213PS: vfmsubadd213ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PDYm, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDYr, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128m, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128mb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128mbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128mbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128mk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128mkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128r, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128rk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ128rkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256m, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256mb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256mbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256mbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256mk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256mkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256r, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256rk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZ256rkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZm, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZmb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZmbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZmbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZmk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZmkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZr, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZrb, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZrbk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZrbkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZrk, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDZrkz, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDm, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PDr, X86_INS_VFMSUBADD231PD: vfmsubadd231pd */ 0, { 0 } }, { /* X86_VFMSUBADD231PSYm, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSYr, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128m, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128mb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128mbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128mbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128mk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128mkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128r, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128rk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ128rkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256m, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256mb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256mbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256mbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256mk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256mkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256r, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256rk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZ256rkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZm, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZmb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZmbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZmbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZmk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZmkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZr, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZrb, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZrbk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZrbkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZrk, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSZrkz, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSm, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADD231PSr, X86_INS_VFMSUBADD231PS: vfmsubadd231ps */ 0, { 0 } }, { /* X86_VFMSUBADDPD4Ymr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { 0 } }, { /* X86_VFMSUBADDPD4Yrm, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { 0 } }, { /* X86_VFMSUBADDPD4Yrr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { 0 } }, { /* X86_VFMSUBADDPD4Yrr_REV, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { 0 } }, { /* X86_VFMSUBADDPD4mr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPD4rm, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPD4rr, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPD4rr_REV, X86_INS_VFMSUBADDPD: vfmsubaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPS4Ymr, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { 0 } }, { /* X86_VFMSUBADDPS4Yrm, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { 0 } }, { /* X86_VFMSUBADDPS4Yrr, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { 0 } }, { /* X86_VFMSUBADDPS4Yrr_REV, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { 0 } }, { /* X86_VFMSUBADDPS4mr, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPS4rm, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPS4rr, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBADDPS4rr_REV, X86_INS_VFMSUBADDPS: vfmsubaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPD4Ymr, X86_INS_VFMSUBPD: vfmsubpd */ 0, { 0 } }, { /* X86_VFMSUBPD4Yrm, X86_INS_VFMSUBPD: vfmsubpd */ 0, { 0 } }, { /* X86_VFMSUBPD4Yrr, X86_INS_VFMSUBPD: vfmsubpd */ 0, { 0 } }, { /* X86_VFMSUBPD4Yrr_REV, X86_INS_VFMSUBPD: vfmsubpd */ 0, { 0 } }, { /* X86_VFMSUBPD4mr, X86_INS_VFMSUBPD: vfmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPD4rm, X86_INS_VFMSUBPD: vfmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPD4rr, X86_INS_VFMSUBPD: vfmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPD4rr_REV, X86_INS_VFMSUBPD: vfmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPS4Ymr, X86_INS_VFMSUBPS: vfmsubps */ 0, { 0 } }, { /* X86_VFMSUBPS4Yrm, X86_INS_VFMSUBPS: vfmsubps */ 0, { 0 } }, { /* X86_VFMSUBPS4Yrr, X86_INS_VFMSUBPS: vfmsubps */ 0, { 0 } }, { /* X86_VFMSUBPS4Yrr_REV, X86_INS_VFMSUBPS: vfmsubps */ 0, { 0 } }, { /* X86_VFMSUBPS4mr, X86_INS_VFMSUBPS: vfmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPS4rm, X86_INS_VFMSUBPS: vfmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPS4rr, X86_INS_VFMSUBPS: vfmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBPS4rr_REV, X86_INS_VFMSUBPS: vfmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSD4mr, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSD4mr_Int, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFMSUBSD4rm, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSD4rm_Int, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFMSUBSD4rr, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSD4rr_Int, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSD4rr_Int_REV, X86_INS_VFMSUBSD: vfmsubsd */ 0, { 0 } }, { /* X86_VFMSUBSD4rr_REV, X86_INS_VFMSUBSD: vfmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSS4mr, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSS4mr_Int, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFMSUBSS4rm, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSS4rm_Int, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFMSUBSS4rr, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSS4rr_Int, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFMSUBSS4rr_Int_REV, X86_INS_VFMSUBSS: vfmsubss */ 0, { 0 } }, { /* X86_VFMSUBSS4rr_REV, X86_INS_VFMSUBSS: vfmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDYm, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDYr, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128m, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDZ128mb, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDZ128mbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128mbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128mk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128mkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128r, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128rk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ128rkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256m, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDZ256mb, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDZ256mbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256mbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256mk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256mkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256r, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256rk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZ256rkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZm, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDZmb, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PDZmbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZmbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZmk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZmkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZr, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZrb, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZrbk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZrbkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZrk, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDZrkz, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDm, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PDr, X86_INS_VFNMADD132PD: vfnmadd132pd */ 0, { 0 } }, { /* X86_VFNMADD132PSYm, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSYr, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128m, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PSZ128mb, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PSZ128mbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128mbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128mk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128mkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128r, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128rk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ128rkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256m, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PSZ256mb, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PSZ256mbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256mbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256mk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256mkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256r, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256rk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZ256rkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZm, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PSZmb, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADD132PSZmbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZmbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZmk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZmkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZr, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZrb, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZrbk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZrbkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZrk, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSZrkz, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSm, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132PSr, X86_INS_VFNMADD132PS: vfnmadd132ps */ 0, { 0 } }, { /* X86_VFNMADD132SDZm, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZm_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZm_Intk, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZm_Intkz, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZr, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZr_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZr_Intk, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZr_Intkz, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZrb, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZrb_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZrb_Intk, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDZrb_Intkz, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDm, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDm_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDr, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SDr_Int, X86_INS_VFNMADD132SD: vfnmadd132sd */ 0, { 0 } }, { /* X86_VFNMADD132SSZm, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZm_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZm_Intk, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZm_Intkz, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZr, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZr_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZr_Intk, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZr_Intkz, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZrb, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZrb_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZrb_Intk, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSZrb_Intkz, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSm, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSm_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSr, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD132SSr_Int, X86_INS_VFNMADD132SS: vfnmadd132ss */ 0, { 0 } }, { /* X86_VFNMADD213PDYm, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDYr, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128m, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128mb, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128mbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128mbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128mk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128mkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128r, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128rk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ128rkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256m, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256mb, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256mbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256mbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256mk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256mkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256r, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256rk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZ256rkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZm, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZmb, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZmbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZmbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZmk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZmkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZr, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZrb, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZrbk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZrbkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZrk, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDZrkz, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDm, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PDr, X86_INS_VFNMADD213PD: vfnmadd213pd */ 0, { 0 } }, { /* X86_VFNMADD213PSYm, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSYr, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128m, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128mb, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128mbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128mbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128mk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128mkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128r, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128rk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ128rkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256m, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256mb, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256mbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256mbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256mk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256mkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256r, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256rk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZ256rkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZm, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZmb, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZmbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZmbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZmk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZmkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZr, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZrb, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZrbk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZrbkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZrk, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSZrkz, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSm, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213PSr, X86_INS_VFNMADD213PS: vfnmadd213ps */ 0, { 0 } }, { /* X86_VFNMADD213SDZm, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZm_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZm_Intk, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZm_Intkz, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZr, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZr_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZr_Intk, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZr_Intkz, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZrb, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZrb_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZrb_Intk, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDZrb_Intkz, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDm, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDm_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDr, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SDr_Int, X86_INS_VFNMADD213SD: vfnmadd213sd */ 0, { 0 } }, { /* X86_VFNMADD213SSZm, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZm_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZm_Intk, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZm_Intkz, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZr, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZr_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZr_Intk, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZr_Intkz, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZrb, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZrb_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZrb_Intk, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSZrb_Intkz, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSm, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSm_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSr, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD213SSr_Int, X86_INS_VFNMADD213SS: vfnmadd213ss */ 0, { 0 } }, { /* X86_VFNMADD231PDYm, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDYr, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128m, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128mb, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128mbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128mbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128mk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128mkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128r, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128rk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ128rkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256m, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256mb, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256mbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256mbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256mk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256mkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256r, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256rk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZ256rkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZm, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZmb, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZmbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZmbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZmk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZmkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZr, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZrb, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZrbk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZrbkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZrk, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDZrkz, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDm, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PDr, X86_INS_VFNMADD231PD: vfnmadd231pd */ 0, { 0 } }, { /* X86_VFNMADD231PSYm, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSYr, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128m, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128mb, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128mbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128mbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128mk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128mkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128r, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128rk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ128rkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256m, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256mb, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256mbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256mbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256mk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256mkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256r, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256rk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZ256rkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZm, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZmb, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZmbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZmbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZmk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZmkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZr, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZrb, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZrbk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZrbkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZrk, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSZrkz, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSm, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231PSr, X86_INS_VFNMADD231PS: vfnmadd231ps */ 0, { 0 } }, { /* X86_VFNMADD231SDZm, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZm_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZm_Intk, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZm_Intkz, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZr, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZr_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZr_Intk, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZr_Intkz, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZrb, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZrb_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZrb_Intk, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDZrb_Intkz, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDm, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDm_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDr, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SDr_Int, X86_INS_VFNMADD231SD: vfnmadd231sd */ 0, { 0 } }, { /* X86_VFNMADD231SSZm, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZm_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZm_Intk, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZm_Intkz, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZr, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZr_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZr_Intk, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZr_Intkz, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZrb, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZrb_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZrb_Intk, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSZrb_Intkz, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSm, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSm_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSr, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADD231SSr_Int, X86_INS_VFNMADD231SS: vfnmadd231ss */ 0, { 0 } }, { /* X86_VFNMADDPD4Ymr, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { 0 } }, { /* X86_VFNMADDPD4Yrm, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { 0 } }, { /* X86_VFNMADDPD4Yrr, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { 0 } }, { /* X86_VFNMADDPD4Yrr_REV, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { 0 } }, { /* X86_VFNMADDPD4mr, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPD4rm, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPD4rr, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPD4rr_REV, X86_INS_VFNMADDPD: vfnmaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPS4Ymr, X86_INS_VFNMADDPS: vfnmaddps */ 0, { 0 } }, { /* X86_VFNMADDPS4Yrm, X86_INS_VFNMADDPS: vfnmaddps */ 0, { 0 } }, { /* X86_VFNMADDPS4Yrr, X86_INS_VFNMADDPS: vfnmaddps */ 0, { 0 } }, { /* X86_VFNMADDPS4Yrr_REV, X86_INS_VFNMADDPS: vfnmaddps */ 0, { 0 } }, { /* X86_VFNMADDPS4mr, X86_INS_VFNMADDPS: vfnmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPS4rm, X86_INS_VFNMADDPS: vfnmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPS4rr, X86_INS_VFNMADDPS: vfnmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDPS4rr_REV, X86_INS_VFNMADDPS: vfnmaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSD4mr, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSD4mr_Int, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFNMADDSD4rm, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSD4rm_Int, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFNMADDSD4rr, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSD4rr_Int, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSD4rr_Int_REV, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { 0 } }, { /* X86_VFNMADDSD4rr_REV, X86_INS_VFNMADDSD: vfnmaddsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSS4mr, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSS4mr_Int, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFNMADDSS4rm, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSS4rm_Int, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFNMADDSS4rr, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSS4rr_Int, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMADDSS4rr_Int_REV, X86_INS_VFNMADDSS: vfnmaddss */ 0, { 0 } }, { /* X86_VFNMADDSS4rr_REV, X86_INS_VFNMADDSS: vfnmaddss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDYm, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDYr, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128m, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDZ128mb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDZ128mbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128mbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128mk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128mkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128r, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128rk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ128rkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256m, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDZ256mb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDZ256mbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256mbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256mk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256mkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256r, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256rk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZ256rkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZm, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDZmb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PDZmbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZmbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZmk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZmkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZr, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZrb, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZrbk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZrbkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZrk, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDZrkz, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDm, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PDr, X86_INS_VFNMSUB132PD: vfnmsub132pd */ 0, { 0 } }, { /* X86_VFNMSUB132PSYm, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSYr, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128m, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PSZ128mb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PSZ128mbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128mbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128mk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128mkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128r, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128rk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ128rkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256m, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PSZ256mb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PSZ256mbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256mbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256mk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256mkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256r, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256rk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZ256rkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZm, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PSZmb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUB132PSZmbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZmbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZmk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZmkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZr, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZrb, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZrbk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZrbkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZrk, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSZrkz, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSm, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132PSr, X86_INS_VFNMSUB132PS: vfnmsub132ps */ 0, { 0 } }, { /* X86_VFNMSUB132SDZm, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZm_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZm_Intk, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZm_Intkz, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZr, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZr_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZr_Intk, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZr_Intkz, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZrb, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZrb_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZrb_Intk, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDZrb_Intkz, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDm, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDm_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDr, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SDr_Int, X86_INS_VFNMSUB132SD: vfnmsub132sd */ 0, { 0 } }, { /* X86_VFNMSUB132SSZm, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZm_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZm_Intk, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZm_Intkz, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZr, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZr_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZr_Intk, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZr_Intkz, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZrb, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZrb_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZrb_Intk, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSZrb_Intkz, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSm, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSm_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSr, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB132SSr_Int, X86_INS_VFNMSUB132SS: vfnmsub132ss */ 0, { 0 } }, { /* X86_VFNMSUB213PDYm, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDYr, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128m, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128mb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128mbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128mbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128mk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128mkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128r, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128rk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ128rkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256m, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256mb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256mbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256mbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256mk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256mkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256r, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256rk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZ256rkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZm, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZmb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZmbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZmbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZmk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZmkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZr, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZrb, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZrbk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZrbkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZrk, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDZrkz, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDm, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PDr, X86_INS_VFNMSUB213PD: vfnmsub213pd */ 0, { 0 } }, { /* X86_VFNMSUB213PSYm, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSYr, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128m, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128mb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128mbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128mbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128mk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128mkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128r, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128rk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ128rkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256m, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256mb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256mbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256mbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256mk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256mkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256r, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256rk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZ256rkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZm, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZmb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZmbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZmbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZmk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZmkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZr, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZrb, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZrbk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZrbkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZrk, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSZrkz, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSm, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213PSr, X86_INS_VFNMSUB213PS: vfnmsub213ps */ 0, { 0 } }, { /* X86_VFNMSUB213SDZm, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZm_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZm_Intk, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZm_Intkz, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZr, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZr_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZr_Intk, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZr_Intkz, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZrb, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZrb_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZrb_Intk, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDZrb_Intkz, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDm, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDm_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDr, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SDr_Int, X86_INS_VFNMSUB213SD: vfnmsub213sd */ 0, { 0 } }, { /* X86_VFNMSUB213SSZm, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZm_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZm_Intk, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZm_Intkz, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZr, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZr_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZr_Intk, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZr_Intkz, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZrb, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZrb_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZrb_Intk, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSZrb_Intkz, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSm, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSm_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSr, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB213SSr_Int, X86_INS_VFNMSUB213SS: vfnmsub213ss */ 0, { 0 } }, { /* X86_VFNMSUB231PDYm, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDYr, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128m, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128mb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128mbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128mbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128mk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128mkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128r, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128rk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ128rkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256m, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256mb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256mbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256mbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256mk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256mkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256r, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256rk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZ256rkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZm, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZmb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZmbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZmbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZmk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZmkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZr, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZrb, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZrbk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZrbkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZrk, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDZrkz, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDm, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PDr, X86_INS_VFNMSUB231PD: vfnmsub231pd */ 0, { 0 } }, { /* X86_VFNMSUB231PSYm, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSYr, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128m, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128mb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128mbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128mbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128mk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128mkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128r, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128rk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ128rkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256m, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256mb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256mbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256mbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256mk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256mkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256r, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256rk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZ256rkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZm, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZmb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZmbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZmbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZmk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZmkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZr, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZrb, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZrbk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZrbkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZrk, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSZrkz, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSm, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231PSr, X86_INS_VFNMSUB231PS: vfnmsub231ps */ 0, { 0 } }, { /* X86_VFNMSUB231SDZm, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZm_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZm_Intk, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZm_Intkz, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZr, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZr_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZr_Intk, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZr_Intkz, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZrb, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZrb_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZrb_Intk, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDZrb_Intkz, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDm, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDm_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDr, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SDr_Int, X86_INS_VFNMSUB231SD: vfnmsub231sd */ 0, { 0 } }, { /* X86_VFNMSUB231SSZm, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZm_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZm_Intk, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZm_Intkz, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZr, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZr_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZr_Intk, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZr_Intkz, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZrb, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZrb_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZrb_Intk, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSZrb_Intkz, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSm, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSm_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSr, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUB231SSr_Int, X86_INS_VFNMSUB231SS: vfnmsub231ss */ 0, { 0 } }, { /* X86_VFNMSUBPD4Ymr, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { 0 } }, { /* X86_VFNMSUBPD4Yrm, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { 0 } }, { /* X86_VFNMSUBPD4Yrr, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { 0 } }, { /* X86_VFNMSUBPD4Yrr_REV, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { 0 } }, { /* X86_VFNMSUBPD4mr, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPD4rm, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPD4rr, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPD4rr_REV, X86_INS_VFNMSUBPD: vfnmsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPS4Ymr, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { 0 } }, { /* X86_VFNMSUBPS4Yrm, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { 0 } }, { /* X86_VFNMSUBPS4Yrr, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { 0 } }, { /* X86_VFNMSUBPS4Yrr_REV, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { 0 } }, { /* X86_VFNMSUBPS4mr, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPS4rm, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPS4rr, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBPS4rr_REV, X86_INS_VFNMSUBPS: vfnmsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSD4mr, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSD4mr_Int, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSD4rm, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSD4rm_Int, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFNMSUBSD4rr, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSD4rr_Int, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSD4rr_Int_REV, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { 0 } }, { /* X86_VFNMSUBSD4rr_REV, X86_INS_VFNMSUBSD: vfnmsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSS4mr, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSS4mr_Int, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSS4rm, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSS4rm_Int, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VFNMSUBSS4rr, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSS4rr_Int, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFNMSUBSS4rr_Int_REV, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { 0 } }, { /* X86_VFNMSUBSS4rr_REV, X86_INS_VFNMSUBSS: vfnmsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VFPCLASSPDZ128rm, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ128rmb, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ128rmbk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ128rmk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ128rr, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ128rrk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ256rm, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ256rmb, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ256rmbk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ256rmk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ256rr, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZ256rrk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZrm, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZrmb, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZrmbk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZrmk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZrr, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPDZrrk, X86_INS_VFPCLASSPD: vfpclasspd */ 0, { 0 } }, { /* X86_VFPCLASSPSZ128rm, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ128rmb, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ128rmbk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ128rmk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ128rr, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ128rrk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ256rm, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ256rmb, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ256rmbk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ256rmk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ256rr, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZ256rrk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZrm, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZrmb, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZrmbk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZrmk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZrr, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSPSZrrk, X86_INS_VFPCLASSPS: vfpclassps */ 0, { 0 } }, { /* X86_VFPCLASSSDZrm, X86_INS_VFPCLASSSD: vfpclasssd */ 0, { 0 } }, { /* X86_VFPCLASSSDZrmk, X86_INS_VFPCLASSSD: vfpclasssd */ 0, { 0 } }, { /* X86_VFPCLASSSDZrr, X86_INS_VFPCLASSSD: vfpclasssd */ 0, { 0 } }, { /* X86_VFPCLASSSDZrrk, X86_INS_VFPCLASSSD: vfpclasssd */ 0, { 0 } }, { /* X86_VFPCLASSSSZrm, X86_INS_VFPCLASSSS: vfpclassss */ 0, { 0 } }, { /* X86_VFPCLASSSSZrmk, X86_INS_VFPCLASSSS: vfpclassss */ 0, { 0 } }, { /* X86_VFPCLASSSSZrr, X86_INS_VFPCLASSSS: vfpclassss */ 0, { 0 } }, { /* X86_VFPCLASSSSZrrk, X86_INS_VFPCLASSSS: vfpclassss */ 0, { 0 } }, { /* X86_VFRCZPDYrm, X86_INS_VFRCZPD: vfrczpd */ 0, { 0 } }, { /* X86_VFRCZPDYrr, X86_INS_VFRCZPD: vfrczpd */ 0, { 0 } }, { /* X86_VFRCZPDrm, X86_INS_VFRCZPD: vfrczpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VFRCZPDrr, X86_INS_VFRCZPD: vfrczpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VFRCZPSYrm, X86_INS_VFRCZPS: vfrczps */ 0, { 0 } }, { /* X86_VFRCZPSYrr, X86_INS_VFRCZPS: vfrczps */ 0, { 0 } }, { /* X86_VFRCZPSrm, X86_INS_VFRCZPS: vfrczps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VFRCZPSrr, X86_INS_VFRCZPS: vfrczps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VFRCZSDrm, X86_INS_VFRCZSD: vfrczsd */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_VFRCZSDrr, X86_INS_VFRCZSD: vfrczsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VFRCZSSrm, X86_INS_VFRCZSS: vfrczss */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_VFRCZSSrr, X86_INS_VFRCZSS: vfrczss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VGATHERDPDYrm, X86_INS_VGATHERDPD: vgatherdpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERDPDZ128rm, X86_INS_VGATHERDPD: vgatherdpd */ 0, { 0 } }, { /* X86_VGATHERDPDZ256rm, X86_INS_VGATHERDPD: vgatherdpd */ 0, { 0 } }, { /* X86_VGATHERDPDZrm, X86_INS_VGATHERDPD: vgatherdpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VGATHERDPDrm, X86_INS_VGATHERDPD: vgatherdpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERDPSYrm, X86_INS_VGATHERDPS: vgatherdps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERDPSZ128rm, X86_INS_VGATHERDPS: vgatherdps */ 0, { 0 } }, { /* X86_VGATHERDPSZ256rm, X86_INS_VGATHERDPS: vgatherdps */ 0, { 0 } }, { /* X86_VGATHERDPSZrm, X86_INS_VGATHERDPS: vgatherdps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VGATHERDPSrm, X86_INS_VGATHERDPS: vgatherdps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERPF0DPDm, X86_INS_VGATHERPF0DPD: vgatherpf0dpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF0DPSm, X86_INS_VGATHERPF0DPS: vgatherpf0dps */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF0QPDm, X86_INS_VGATHERPF0QPD: vgatherpf0qpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF0QPSm, X86_INS_VGATHERPF0QPS: vgatherpf0qps */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF1DPDm, X86_INS_VGATHERPF1DPD: vgatherpf1dpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF1DPSm, X86_INS_VGATHERPF1DPS: vgatherpf1dps */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF1QPDm, X86_INS_VGATHERPF1QPD: vgatherpf1qpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERPF1QPSm, X86_INS_VGATHERPF1QPS: vgatherpf1qps */ 0, { CS_AC_READ, 0 } }, { /* X86_VGATHERQPDYrm, X86_INS_VGATHERQPD: vgatherqpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERQPDZ128rm, X86_INS_VGATHERQPD: vgatherqpd */ 0, { 0 } }, { /* X86_VGATHERQPDZ256rm, X86_INS_VGATHERQPD: vgatherqpd */ 0, { 0 } }, { /* X86_VGATHERQPDZrm, X86_INS_VGATHERQPD: vgatherqpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VGATHERQPDrm, X86_INS_VGATHERQPD: vgatherqpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERQPSYrm, X86_INS_VGATHERQPS: vgatherqps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGATHERQPSZ128rm, X86_INS_VGATHERQPS: vgatherqps */ 0, { 0 } }, { /* X86_VGATHERQPSZ256rm, X86_INS_VGATHERQPS: vgatherqps */ 0, { 0 } }, { /* X86_VGATHERQPSZrm, X86_INS_VGATHERQPS: vgatherqps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VGATHERQPSrm, X86_INS_VGATHERQPS: vgatherqps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VGETEXPPDZ128m, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128mb, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128mbk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128mbkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128mk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128mkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128r, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128rk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ128rkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256m, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256mb, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256mbk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256mbkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256mk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256mkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256r, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256rk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZ256rkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZm, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZmb, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZmbk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZmbkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZmk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZmkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZr, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZrb, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZrbk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZrbkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZrk, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPDZrkz, X86_INS_VGETEXPPD: vgetexppd */ 0, { 0 } }, { /* X86_VGETEXPPSZ128m, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128mb, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128mbk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128mbkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128mk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128mkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128r, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128rk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ128rkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256m, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256mb, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256mbk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256mbkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256mk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256mkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256r, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256rk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZ256rkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZm, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZmb, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZmbk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZmbkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZmk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZmkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZr, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZrb, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZrbk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZrbkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZrk, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPPSZrkz, X86_INS_VGETEXPPS: vgetexpps */ 0, { 0 } }, { /* X86_VGETEXPSDZm, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZmk, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZmkz, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZr, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZrb, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZrbk, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZrbkz, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZrk, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSDZrkz, X86_INS_VGETEXPSD: vgetexpsd */ 0, { 0 } }, { /* X86_VGETEXPSSZm, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZmk, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZmkz, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZr, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZrb, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZrbk, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZrbkz, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZrk, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETEXPSSZrkz, X86_INS_VGETEXPSS: vgetexpss */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rmbi, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rmbik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rmbikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rmi, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rmik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rmikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rri, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rrik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ128rrikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rmbi, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rmbik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rmbikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rmi, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rmik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rmikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rri, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rrik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZ256rrikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrmbi, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrmbik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrmbikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrmi, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrmik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrmikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrri, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrrib, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrribk, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrribkz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrrik, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPDZrrikz, X86_INS_VGETMANTPD: vgetmantpd */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rmbi, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rmbik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rmbikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rmi, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rmik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rmikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rri, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rrik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ128rrikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rmbi, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rmbik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rmbikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rmi, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rmik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rmikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rri, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rrik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZ256rrikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrmbi, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrmbik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrmbikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrmi, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrmik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrmikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrri, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrrib, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrribk, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrribkz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrrik, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTPSZrrikz, X86_INS_VGETMANTPS: vgetmantps */ 0, { 0 } }, { /* X86_VGETMANTSDZrmi, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrmik, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrmikz, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrri, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrrib, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrribk, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrribkz, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrrik, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSDZrrikz, X86_INS_VGETMANTSD: vgetmantsd */ 0, { 0 } }, { /* X86_VGETMANTSSZrmi, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrmik, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrmikz, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrri, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrrib, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrribk, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrribkz, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrrik, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGETMANTSSZrrikz, X86_INS_VGETMANTSS: vgetmantss */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBYrmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBYrri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rmbi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rmbik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rmbikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rmik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rmikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rrik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ128rrikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rmbi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rmbik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rmbikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rmik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rmikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rrik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZ256rrikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrmbi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrmbik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrmbikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrmik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrmikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrrik, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBZrrikz, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBrmi, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEINVQBrri, X86_INS_VGF2P8AFFINEINVQB: vgf2p8affineinvqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBYrmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBYrri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rmbi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rmbik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rmbikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rmik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rmikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rrik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ128rrikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rmbi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rmbik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rmbikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rmik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rmikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rrik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZ256rrikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrmbi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrmbik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrmbikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrmik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrmikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrrik, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBZrrikz, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBrmi, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8AFFINEQBrri, X86_INS_VGF2P8AFFINEQB: vgf2p8affineqb */ 0, { 0 } }, { /* X86_VGF2P8MULBYrm, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBYrr, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ128rm, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ128rmk, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ128rmkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ128rr, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ128rrk, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ128rrkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ256rm, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ256rmk, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ256rmkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ256rr, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ256rrk, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZ256rrkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZrm, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZrmk, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZrmkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZrr, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZrrk, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBZrrkz, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBrm, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VGF2P8MULBrr, X86_INS_VGF2P8MULB: vgf2p8mulb */ 0, { 0 } }, { /* X86_VHADDPDYrm, X86_INS_VHADDPD: vhaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPDYrr, X86_INS_VHADDPD: vhaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPDrm, X86_INS_VHADDPD: vhaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPDrr, X86_INS_VHADDPD: vhaddpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPSYrm, X86_INS_VHADDPS: vhaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPSYrr, X86_INS_VHADDPS: vhaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPSrm, X86_INS_VHADDPS: vhaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHADDPSrr, X86_INS_VHADDPS: vhaddps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPDYrm, X86_INS_VHSUBPD: vhsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPDYrr, X86_INS_VHSUBPD: vhsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPDrm, X86_INS_VHSUBPD: vhsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPDrr, X86_INS_VHSUBPD: vhsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPSYrm, X86_INS_VHSUBPS: vhsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPSYrr, X86_INS_VHSUBPS: vhsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPSrm, X86_INS_VHSUBPS: vhsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VHSUBPSrr, X86_INS_VHSUBPS: vhsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VINSERTF128rm, X86_INS_VINSERTF128: vinsertf128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VINSERTF128rr, X86_INS_VINSERTF128: vinsertf128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VINSERTF32x4Z256rm, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Z256rmk, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Z256rmkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Z256rr, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Z256rrk, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Z256rrkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Zrm, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Zrmk, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Zrmkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Zrr, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Zrrk, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x4Zrrkz, X86_INS_VINSERTF32X4: vinsertf32x4 */ 0, { 0 } }, { /* X86_VINSERTF32x8Zrm, X86_INS_VINSERTF32X8: vinsertf32x8 */ 0, { 0 } }, { /* X86_VINSERTF32x8Zrmk, X86_INS_VINSERTF32X8: vinsertf32x8 */ 0, { 0 } }, { /* X86_VINSERTF32x8Zrmkz, X86_INS_VINSERTF32X8: vinsertf32x8 */ 0, { 0 } }, { /* X86_VINSERTF32x8Zrr, X86_INS_VINSERTF32X8: vinsertf32x8 */ 0, { 0 } }, { /* X86_VINSERTF32x8Zrrk, X86_INS_VINSERTF32X8: vinsertf32x8 */ 0, { 0 } }, { /* X86_VINSERTF32x8Zrrkz, X86_INS_VINSERTF32X8: vinsertf32x8 */ 0, { 0 } }, { /* X86_VINSERTF64x2Z256rm, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Z256rmk, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Z256rmkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Z256rr, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Z256rrk, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Z256rrkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Zrm, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Zrmk, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Zrmkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Zrr, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Zrrk, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x2Zrrkz, X86_INS_VINSERTF64X2: vinsertf64x2 */ 0, { 0 } }, { /* X86_VINSERTF64x4Zrm, X86_INS_VINSERTF64X4: vinsertf64x4 */ 0, { 0 } }, { /* X86_VINSERTF64x4Zrmk, X86_INS_VINSERTF64X4: vinsertf64x4 */ 0, { 0 } }, { /* X86_VINSERTF64x4Zrmkz, X86_INS_VINSERTF64X4: vinsertf64x4 */ 0, { 0 } }, { /* X86_VINSERTF64x4Zrr, X86_INS_VINSERTF64X4: vinsertf64x4 */ 0, { 0 } }, { /* X86_VINSERTF64x4Zrrk, X86_INS_VINSERTF64X4: vinsertf64x4 */ 0, { 0 } }, { /* X86_VINSERTF64x4Zrrkz, X86_INS_VINSERTF64X4: vinsertf64x4 */ 0, { 0 } }, { /* X86_VINSERTI128rm, X86_INS_VINSERTI128: vinserti128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VINSERTI128rr, X86_INS_VINSERTI128: vinserti128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VINSERTI32x4Z256rm, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Z256rmk, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Z256rmkz, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Z256rr, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Z256rrk, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Z256rrkz, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Zrm, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Zrmk, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Zrmkz, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Zrr, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Zrrk, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x4Zrrkz, X86_INS_VINSERTI32X4: vinserti32x4 */ 0, { 0 } }, { /* X86_VINSERTI32x8Zrm, X86_INS_VINSERTI32X8: vinserti32x8 */ 0, { 0 } }, { /* X86_VINSERTI32x8Zrmk, X86_INS_VINSERTI32X8: vinserti32x8 */ 0, { 0 } }, { /* X86_VINSERTI32x8Zrmkz, X86_INS_VINSERTI32X8: vinserti32x8 */ 0, { 0 } }, { /* X86_VINSERTI32x8Zrr, X86_INS_VINSERTI32X8: vinserti32x8 */ 0, { 0 } }, { /* X86_VINSERTI32x8Zrrk, X86_INS_VINSERTI32X8: vinserti32x8 */ 0, { 0 } }, { /* X86_VINSERTI32x8Zrrkz, X86_INS_VINSERTI32X8: vinserti32x8 */ 0, { 0 } }, { /* X86_VINSERTI64x2Z256rm, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Z256rmk, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Z256rmkz, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Z256rr, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Z256rrk, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Z256rrkz, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Zrm, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Zrmk, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Zrmkz, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Zrr, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Zrrk, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x2Zrrkz, X86_INS_VINSERTI64X2: vinserti64x2 */ 0, { 0 } }, { /* X86_VINSERTI64x4Zrm, X86_INS_VINSERTI64X4: vinserti64x4 */ 0, { 0 } }, { /* X86_VINSERTI64x4Zrmk, X86_INS_VINSERTI64X4: vinserti64x4 */ 0, { 0 } }, { /* X86_VINSERTI64x4Zrmkz, X86_INS_VINSERTI64X4: vinserti64x4 */ 0, { 0 } }, { /* X86_VINSERTI64x4Zrr, X86_INS_VINSERTI64X4: vinserti64x4 */ 0, { 0 } }, { /* X86_VINSERTI64x4Zrrk, X86_INS_VINSERTI64X4: vinserti64x4 */ 0, { 0 } }, { /* X86_VINSERTI64x4Zrrkz, X86_INS_VINSERTI64X4: vinserti64x4 */ 0, { 0 } }, { /* X86_VINSERTPSZrm, X86_INS_VINSERTPS: vinsertps */ 0, { 0 } }, { /* X86_VINSERTPSZrr, X86_INS_VINSERTPS: vinsertps */ 0, { 0 } }, { /* X86_VINSERTPSrm, X86_INS_VINSERTPS: vinsertps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VINSERTPSrr, X86_INS_VINSERTPS: vinsertps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VLDDQUYrm, X86_INS_VLDDQU: vlddqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VLDDQUrm, X86_INS_VLDDQU: vlddqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VLDMXCSR, X86_INS_VLDMXCSR: vldmxcsr */ 0, { CS_AC_READ, 0 } }, { /* X86_VMASKMOVDQU, X86_INS_VMASKMOVDQU: vmaskmovdqu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVDQU64, X86_INS_VMASKMOVDQU: vmaskmovdqu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPDYmr, X86_INS_VMASKMOVPD: vmaskmovpd */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPDYrm, X86_INS_VMASKMOVPD: vmaskmovpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPDmr, X86_INS_VMASKMOVPD: vmaskmovpd */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPDrm, X86_INS_VMASKMOVPD: vmaskmovpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPSYmr, X86_INS_VMASKMOVPS: vmaskmovps */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPSYrm, X86_INS_VMASKMOVPS: vmaskmovps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPSmr, X86_INS_VMASKMOVPS: vmaskmovps */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMASKMOVPSrm, X86_INS_VMASKMOVPS: vmaskmovps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPDYrm, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPDYrr, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPDZ128rm, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rmb, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rmbk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rmbkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rmk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rmkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rr, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rrk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ128rrkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rm, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rmb, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rmbk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rmbkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rmk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rmkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rr, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rrk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZ256rrkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrm, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrmb, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrmbk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrmbkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrmk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrmkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrr, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrrk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDZrrkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXCPDrm, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPDrr, X86_INS_VMAXPD: vmaxpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPSYrm, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPSYrr, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPSZ128rm, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rmb, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rmbk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rmbkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rmk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rmkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rr, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rrk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ128rrkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rm, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rmb, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rmbk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rmbkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rmk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rmkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rr, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rrk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZ256rrkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrm, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrmb, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrmbk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrmbkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrmk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrmkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrr, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrrk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSZrrkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXCPSrm, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCPSrr, X86_INS_VMAXPS: vmaxps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCSDZrm, X86_INS_VMAXSD: vmaxsd */ 0, { 0 } }, { /* X86_VMAXCSDZrr, X86_INS_VMAXSD: vmaxsd */ 0, { 0 } }, { /* X86_VMAXCSDrm, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCSDrr, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCSSZrm, X86_INS_VMAXSS: vmaxss */ 0, { 0 } }, { /* X86_VMAXCSSZrr, X86_INS_VMAXSS: vmaxss */ 0, { 0 } }, { /* X86_VMAXCSSrm, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXCSSrr, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDYrm, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDYrr, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rm, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rmb, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rmbk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rmbkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rmk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rmkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rr, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rrk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ128rrkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rm, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rmb, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rmbk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rmbkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rmk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rmkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rr, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rrk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZ256rrkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrm, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrmb, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrmbk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrmbkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrmk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrmkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrr, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrrb, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXPDZrrbk, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXPDZrrbkz, X86_INS_VMAXPD: vmaxpd */ 0, { 0 } }, { /* X86_VMAXPDZrrk, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDZrrkz, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDrm, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPDrr, X86_INS_VMAXPD: vmaxpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSYrm, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSYrr, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rm, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rmb, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rmbk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rmbkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rmk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rmkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rr, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rrk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ128rrkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rm, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rmb, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rmbk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rmbkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rmk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rmkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rr, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rrk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZ256rrkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrm, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrmb, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrmbk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrmbkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrmk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrmkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrr, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrrb, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXPSZrrbk, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXPSZrrbkz, X86_INS_VMAXPS: vmaxps */ 0, { 0 } }, { /* X86_VMAXPSZrrk, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSZrrkz, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSrm, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXPSrr, X86_INS_VMAXPS: vmaxps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrm, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrm_Int, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrm_Intk, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrm_Intkz, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrr, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrr_Int, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrr_Intk, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrr_Intkz, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDZrrb_Int, X86_INS_VMAXSD: vmaxsd */ 0, { 0 } }, { /* X86_VMAXSDZrrb_Intk, X86_INS_VMAXSD: vmaxsd */ 0, { 0 } }, { /* X86_VMAXSDZrrb_Intkz, X86_INS_VMAXSD: vmaxsd */ 0, { 0 } }, { /* X86_VMAXSDrm, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDrm_Int, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMAXSDrr, X86_INS_VMAXSD: vmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSDrr_Int, X86_INS_VMAXSD: vmaxsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrm, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrm_Int, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrm_Intk, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrm_Intkz, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrr, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrr_Int, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrr_Intk, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrr_Intkz, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSZrrb_Int, X86_INS_VMAXSS: vmaxss */ 0, { 0 } }, { /* X86_VMAXSSZrrb_Intk, X86_INS_VMAXSS: vmaxss */ 0, { 0 } }, { /* X86_VMAXSSZrrb_Intkz, X86_INS_VMAXSS: vmaxss */ 0, { 0 } }, { /* X86_VMAXSSrm, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSrm_Int, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMAXSSrr, X86_INS_VMAXSS: vmaxss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMAXSSrr_Int, X86_INS_VMAXSS: vmaxss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMCALL, X86_INS_VMCALL: vmcall */ 0, { 0 } }, { /* X86_VMCLEARm, X86_INS_VMCLEAR: vmclear */ 0, { CS_AC_READ, 0 } }, { /* X86_VMFUNC, X86_INS_VMFUNC: vmfunc */ 0, { 0 } }, { /* X86_VMINCPDYrm, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPDYrr, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPDZ128rm, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rmb, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rmbk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rmbkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rmk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rmkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rr, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rrk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ128rrkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rm, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rmb, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rmbk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rmbkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rmk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rmkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rr, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rrk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZ256rrkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrm, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrmb, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrmbk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrmbkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrmk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrmkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrr, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrrk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDZrrkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINCPDrm, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPDrr, X86_INS_VMINPD: vminpd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPSYrm, X86_INS_VMINPS: vminps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPSYrr, X86_INS_VMINPS: vminps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPSZ128rm, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rmb, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rmbk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rmbkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rmk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rmkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rr, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rrk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ128rrkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rm, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rmb, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rmbk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rmbkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rmk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rmkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rr, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rrk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZ256rrkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrm, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrmb, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrmbk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrmbkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrmk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrmkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrr, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrrk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSZrrkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINCPSrm, X86_INS_VMINPS: vminps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCPSrr, X86_INS_VMINPS: vminps $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCSDZrm, X86_INS_VMINSD: vminsd */ 0, { 0 } }, { /* X86_VMINCSDZrr, X86_INS_VMINSD: vminsd */ 0, { 0 } }, { /* X86_VMINCSDrm, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCSDrr, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCSSZrm, X86_INS_VMINSS: vminss */ 0, { 0 } }, { /* X86_VMINCSSZrr, X86_INS_VMINSS: vminss */ 0, { 0 } }, { /* X86_VMINCSSrm, X86_INS_VMINSS: vminss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINCSSrr, X86_INS_VMINSS: vminss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDYrm, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDYrr, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rm, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rmb, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rmbk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rmbkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rmk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rmkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rr, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rrk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ128rrkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rm, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rmb, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rmbk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rmbkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rmk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rmkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rr, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rrk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZ256rrkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrm, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrmb, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrmbk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrmbkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrmk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrmkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrr, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrrb, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINPDZrrbk, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINPDZrrbkz, X86_INS_VMINPD: vminpd */ 0, { 0 } }, { /* X86_VMINPDZrrk, X86_INS_VMINPD: vminpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDZrrkz, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDrm, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPDrr, X86_INS_VMINPD: vminpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSYrm, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSYrr, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rm, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rmb, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rmbk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rmbkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rmk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rmkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rr, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rrk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ128rrkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rm, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rmb, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rmbk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rmbkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rmk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rmkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rr, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rrk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZ256rrkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrm, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrmb, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrmbk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrmbkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrmk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrmkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrr, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrrb, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINPSZrrbk, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINPSZrrbkz, X86_INS_VMINPS: vminps */ 0, { 0 } }, { /* X86_VMINPSZrrk, X86_INS_VMINPS: vminps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSZrrkz, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSrm, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINPSrr, X86_INS_VMINPS: vminps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrm, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrm_Int, X86_INS_VMINSD: vminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrm_Intk, X86_INS_VMINSD: vminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrm_Intkz, X86_INS_VMINSD: vminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrr, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrr_Int, X86_INS_VMINSD: vminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrr_Intk, X86_INS_VMINSD: vminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrr_Intkz, X86_INS_VMINSD: vminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDZrrb_Int, X86_INS_VMINSD: vminsd */ 0, { 0 } }, { /* X86_VMINSDZrrb_Intk, X86_INS_VMINSD: vminsd */ 0, { 0 } }, { /* X86_VMINSDZrrb_Intkz, X86_INS_VMINSD: vminsd */ 0, { 0 } }, { /* X86_VMINSDrm, X86_INS_VMINSD: vminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDrm_Int, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMINSDrr, X86_INS_VMINSD: vminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSDrr_Int, X86_INS_VMINSD: vminsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrm, X86_INS_VMINSS: vminss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrm_Int, X86_INS_VMINSS: vminss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrm_Intk, X86_INS_VMINSS: vminss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrm_Intkz, X86_INS_VMINSS: vminss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrr, X86_INS_VMINSS: vminss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrr_Int, X86_INS_VMINSS: vminss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrr_Intk, X86_INS_VMINSS: vminss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrr_Intkz, X86_INS_VMINSS: vminss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSZrrb_Int, X86_INS_VMINSS: vminss */ 0, { 0 } }, { /* X86_VMINSSZrrb_Intk, X86_INS_VMINSS: vminss */ 0, { 0 } }, { /* X86_VMINSSZrrb_Intkz, X86_INS_VMINSS: vminss */ 0, { 0 } }, { /* X86_VMINSSrm, X86_INS_VMINSS: vminss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSrm_Int, X86_INS_VMINSS: vminss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMINSSrr, X86_INS_VMINSS: vminss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMINSSrr_Int, X86_INS_VMINSS: vminss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMLAUNCH, X86_INS_VMLAUNCH: vmlaunch */ 0, { 0 } }, { /* X86_VMLOAD32, X86_INS_VMLOAD: vmload */ 0, { CS_AC_READ, 0 } }, { /* X86_VMLOAD64, X86_INS_VMLOAD: vmload */ 0, { CS_AC_READ, 0 } }, { /* X86_VMMCALL, X86_INS_VMMCALL: vmmcall */ 0, { 0 } }, { /* X86_VMOV64toPQIZrm, X86_INS_VMOVQ: vmovq */ 0, { 0 } }, { /* X86_VMOV64toPQIZrr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOV64toPQIrm, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOV64toPQIrr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOV64toSDZrm, X86_INS_VMOVQ: vmovq */ 0, { 0 } }, { /* X86_VMOV64toSDZrr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOV64toSDrm, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOV64toSDrr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDYmr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDYrm, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDYrr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDYrr_REV, X86_INS_VMOVAPD: vmovapd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128mr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128mrk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rm, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rmk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rmkz, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rr_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZ128rrk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rrk_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZ128rrkz, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ128rrkz_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZ256mr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256mrk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rm, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rmk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rmkz, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rr_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZ256rrk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rrk_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZ256rrkz, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZ256rrkz_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZmr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZmrk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrm, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrmk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrmkz, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrr_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZrrk, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrrk_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDZrrkz, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDZrrkz_REV, X86_INS_VMOVAPD: vmovapd */ 0, { 0 } }, { /* X86_VMOVAPDmr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPDrm, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDrr, X86_INS_VMOVAPD: vmovapd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPDrr_REV, X86_INS_VMOVAPD: vmovapd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSYmr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSYrm, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSYrr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSYrr_REV, X86_INS_VMOVAPS: vmovaps $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128mr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128mrk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rm, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rmk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rmkz, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rr_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZ128rrk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rrk_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZ128rrkz, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ128rrkz_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZ256mr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256mrk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rm, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rmk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rmkz, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rr_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZ256rrk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rrk_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZ256rrkz, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZ256rrkz_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZmr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZmrk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrm, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrmk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrmkz, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrr_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZrrk, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrrk_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSZrrkz, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSZrrkz_REV, X86_INS_VMOVAPS: vmovaps */ 0, { 0 } }, { /* X86_VMOVAPSmr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVAPSrm, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSrr, X86_INS_VMOVAPS: vmovaps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVAPSrr_REV, X86_INS_VMOVAPS: vmovaps $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDDUPYrm, X86_INS_VMOVDDUP: vmovddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDDUPYrr, X86_INS_VMOVDDUP: vmovddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDDUPZ128rm, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ128rmk, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ128rmkz, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ128rr, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ128rrk, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ128rrkz, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ256rm, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ256rmk, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ256rmkz, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ256rr, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ256rrk, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZ256rrkz, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZrm, X86_INS_VMOVDDUP: vmovddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDDUPZrmk, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZrmkz, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZrr, X86_INS_VMOVDDUP: vmovddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDDUPZrrk, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPZrrkz, X86_INS_VMOVDDUP: vmovddup */ 0, { 0 } }, { /* X86_VMOVDDUPrm, X86_INS_VMOVDDUP: vmovddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDDUPrr, X86_INS_VMOVDDUP: vmovddup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2PDIZrm, X86_INS_VMOVD: vmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2PDIZrr, X86_INS_VMOVD: vmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2PDIrm, X86_INS_VMOVD: vmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2PDIrr, X86_INS_VMOVD: vmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2SSZrm, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2SSZrr, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2SSrm, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDI2SSrr, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128mr, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128mrk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rm, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rmk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rmkz, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rr, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rr_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Z128rrk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rrk_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Z128rrkz, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z128rrkz_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Z256mr, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256mrk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rm, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rmk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rmkz, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rr, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rr_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Z256rrk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rrk_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Z256rrkz, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Z256rrkz_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Zmr, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zmrk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrm, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrmk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrmkz, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrr, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrr_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Zrrk, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrrk_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA32Zrrkz, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA32Zrrkz_REV, X86_INS_VMOVDQA32: vmovdqa32 */ 0, { 0 } }, { /* X86_VMOVDQA64Z128mr, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128mrk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rm, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rmk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rmkz, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rr, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rr_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Z128rrk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rrk_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Z128rrkz, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z128rrkz_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Z256mr, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256mrk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rm, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rmk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rmkz, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rr, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rr_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Z256rrk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rrk_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Z256rrkz, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Z256rrkz_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Zmr, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zmrk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrm, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrmk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrmkz, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrr, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrr_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Zrrk, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrrk_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQA64Zrrkz, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQA64Zrrkz_REV, X86_INS_VMOVDQA64: vmovdqa64 */ 0, { 0 } }, { /* X86_VMOVDQAYmr, X86_INS_VMOVDQA: vmovdqa */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQAYrm, X86_INS_VMOVDQA: vmovdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQAYrr, X86_INS_VMOVDQA: vmovdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQAYrr_REV, X86_INS_VMOVDQA: vmovdqa $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQAmr, X86_INS_VMOVDQA: vmovdqa */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQArm, X86_INS_VMOVDQA: vmovdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQArr, X86_INS_VMOVDQA: vmovdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQArr_REV, X86_INS_VMOVDQA: vmovdqa $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128mr, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128mrk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rm, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rmk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rmkz, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rr, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rr_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Z128rrk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rrk_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Z128rrkz, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z128rrkz_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Z256mr, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256mrk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rm, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rmk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rmkz, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rr, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rr_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Z256rrk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rrk_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Z256rrkz, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Z256rrkz_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Zmr, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zmrk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrm, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrmk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrmkz, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrr, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrr_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Zrrk, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrrk_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU16Zrrkz, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU16Zrrkz_REV, X86_INS_VMOVDQU16: vmovdqu16 */ 0, { 0 } }, { /* X86_VMOVDQU32Z128mr, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128mrk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rm, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rmk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rmkz, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rr, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rr_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Z128rrk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rrk_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Z128rrkz, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z128rrkz_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Z256mr, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256mrk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rm, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rmk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rmkz, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rr, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rr_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Z256rrk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rrk_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Z256rrkz, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Z256rrkz_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Zmr, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zmrk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrm, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrmk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrmkz, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrr, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrr_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Zrrk, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrrk_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU32Zrrkz, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU32Zrrkz_REV, X86_INS_VMOVDQU32: vmovdqu32 */ 0, { 0 } }, { /* X86_VMOVDQU64Z128mr, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128mrk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rm, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rmk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rmkz, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rr, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rr_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Z128rrk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rrk_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Z128rrkz, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z128rrkz_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Z256mr, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256mrk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rm, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rmk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rmkz, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rr, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rr_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Z256rrk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rrk_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Z256rrkz, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Z256rrkz_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Zmr, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zmrk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrm, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrmk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrmkz, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrr, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrr_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Zrrk, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrrk_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU64Zrrkz, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU64Zrrkz_REV, X86_INS_VMOVDQU64: vmovdqu64 */ 0, { 0 } }, { /* X86_VMOVDQU8Z128mr, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128mrk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rm, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rmk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rmkz, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rr, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rr_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Z128rrk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rrk_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Z128rrkz, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z128rrkz_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Z256mr, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256mrk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rm, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rmk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rmkz, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rr, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rr_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Z256rrk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rrk_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Z256rrkz, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Z256rrkz_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Zmr, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zmrk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrm, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrmk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrmkz, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrr, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrr_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Zrrk, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrrk_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQU8Zrrkz, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQU8Zrrkz_REV, X86_INS_VMOVDQU8: vmovdqu8 */ 0, { 0 } }, { /* X86_VMOVDQUYmr, X86_INS_VMOVDQU: vmovdqu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQUYrm, X86_INS_VMOVDQU: vmovdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQUYrr, X86_INS_VMOVDQU: vmovdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQUYrr_REV, X86_INS_VMOVDQU: vmovdqu $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQUmr, X86_INS_VMOVDQU: vmovdqu */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVDQUrm, X86_INS_VMOVDQU: vmovdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQUrr, X86_INS_VMOVDQU: vmovdqu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVDQUrr_REV, X86_INS_VMOVDQU: vmovdqu $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVHLPSZrr, X86_INS_VMOVHLPS: vmovhlps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVHLPSrr, X86_INS_VMOVHLPS: vmovhlps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVHPDZ128mr, X86_INS_VMOVHPD: vmovhpd */ 0, { 0 } }, { /* X86_VMOVHPDZ128rm, X86_INS_VMOVHPD: vmovhpd */ 0, { 0 } }, { /* X86_VMOVHPDmr, X86_INS_VMOVHPD: vmovhpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVHPDrm, X86_INS_VMOVHPD: vmovhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVHPSZ128mr, X86_INS_VMOVHPS: vmovhps */ 0, { 0 } }, { /* X86_VMOVHPSZ128rm, X86_INS_VMOVHPS: vmovhps */ 0, { 0 } }, { /* X86_VMOVHPSmr, X86_INS_VMOVHPS: vmovhps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVHPSrm, X86_INS_VMOVHPS: vmovhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVLHPSZrr, X86_INS_VMOVLHPS: vmovlhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVLHPSrr, X86_INS_VMOVLHPS: vmovlhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVLPDZ128mr, X86_INS_VMOVLPD: vmovlpd */ 0, { 0 } }, { /* X86_VMOVLPDZ128rm, X86_INS_VMOVLPD: vmovlpd */ 0, { 0 } }, { /* X86_VMOVLPDmr, X86_INS_VMOVLPD: vmovlpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVLPDrm, X86_INS_VMOVLPD: vmovlpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVLPSZ128mr, X86_INS_VMOVLPS: vmovlps */ 0, { 0 } }, { /* X86_VMOVLPSZ128rm, X86_INS_VMOVLPS: vmovlps */ 0, { 0 } }, { /* X86_VMOVLPSmr, X86_INS_VMOVLPS: vmovlps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVLPSrm, X86_INS_VMOVLPS: vmovlps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVMSKPDYrr, X86_INS_VMOVMSKPD: vmovmskpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVMSKPDrr, X86_INS_VMOVMSKPD: vmovmskpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVMSKPSYrr, X86_INS_VMOVMSKPS: vmovmskps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVMSKPSrr, X86_INS_VMOVMSKPS: vmovmskps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQAYrm, X86_INS_VMOVNTDQA: vmovntdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQAZ128rm, X86_INS_VMOVNTDQA: vmovntdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQAZ256rm, X86_INS_VMOVNTDQA: vmovntdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQAZrm, X86_INS_VMOVNTDQA: vmovntdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQArm, X86_INS_VMOVNTDQA: vmovntdqa */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQYmr, X86_INS_VMOVNTDQ: vmovntdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQZ128mr, X86_INS_VMOVNTDQ: vmovntdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQZ256mr, X86_INS_VMOVNTDQ: vmovntdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQZmr, X86_INS_VMOVNTDQ: vmovntdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTDQmr, X86_INS_VMOVNTDQ: vmovntdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPDYmr, X86_INS_VMOVNTPD: vmovntpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPDZ128mr, X86_INS_VMOVNTPD: vmovntpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPDZ256mr, X86_INS_VMOVNTPD: vmovntpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPDZmr, X86_INS_VMOVNTPD: vmovntpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPDmr, X86_INS_VMOVNTPD: vmovntpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPSYmr, X86_INS_VMOVNTPS: vmovntps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPSZ128mr, X86_INS_VMOVNTPS: vmovntps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPSZ256mr, X86_INS_VMOVNTPS: vmovntps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPSZmr, X86_INS_VMOVNTPS: vmovntps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVNTPSmr, X86_INS_VMOVNTPS: vmovntps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVPDI2DIZmr, X86_INS_VMOVD: vmovd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVPDI2DIZrr, X86_INS_VMOVD: vmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVPDI2DImr, X86_INS_VMOVD: vmovd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVPDI2DIrr, X86_INS_VMOVD: vmovd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVPQI2QIZmr, X86_INS_VMOVQ: vmovq */ 0, { 0 } }, { /* X86_VMOVPQI2QIZrr, X86_INS_VMOVQ: vmovq */ 0, { 0 } }, { /* X86_VMOVPQI2QImr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVPQI2QIrr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVPQIto64Zmr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVPQIto64Zrr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVPQIto64mr, X86_INS_VMOVQ: vmovq */ 0, { 0 } }, { /* X86_VMOVPQIto64rr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVQI2PQIZrm, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVQI2PQIrm, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSDZmr, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDZmrk, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDZrm, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSDZrmk, X86_INS_VMOVSD: vmovsd */ 0, { 0 } }, { /* X86_VMOVSDZrmkz, X86_INS_VMOVSD: vmovsd */ 0, { 0 } }, { /* X86_VMOVSDZrr, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDZrr_REV, X86_INS_VMOVSD: vmovsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDZrrk, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDZrrk_REV, X86_INS_VMOVSD: vmovsd */ 0, { 0 } }, { /* X86_VMOVSDZrrkz, X86_INS_VMOVSD: vmovsd */ 0, { 0 } }, { /* X86_VMOVSDZrrkz_REV, X86_INS_VMOVSD: vmovsd */ 0, { 0 } }, { /* X86_VMOVSDmr, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDrm, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSDrr, X86_INS_VMOVSD: vmovsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDrr_REV, X86_INS_VMOVSD: vmovsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDto64Zmr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDto64Zrr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSDto64mr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSDto64rr, X86_INS_VMOVQ: vmovq $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSHDUPYrm, X86_INS_VMOVSHDUP: vmovshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSHDUPYrr, X86_INS_VMOVSHDUP: vmovshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSHDUPZ128rm, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ128rmk, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ128rmkz, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ128rr, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ128rrk, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ128rrkz, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ256rm, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ256rmk, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ256rmkz, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ256rr, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ256rrk, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZ256rrkz, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZrm, X86_INS_VMOVSHDUP: vmovshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSHDUPZrmk, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZrmkz, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZrr, X86_INS_VMOVSHDUP: vmovshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSHDUPZrrk, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPZrrkz, X86_INS_VMOVSHDUP: vmovshdup */ 0, { 0 } }, { /* X86_VMOVSHDUPrm, X86_INS_VMOVSHDUP: vmovshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSHDUPrr, X86_INS_VMOVSHDUP: vmovshdup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSLDUPYrm, X86_INS_VMOVSLDUP: vmovsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSLDUPYrr, X86_INS_VMOVSLDUP: vmovsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSLDUPZ128rm, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ128rmk, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ128rmkz, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ128rr, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ128rrk, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ128rrkz, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ256rm, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ256rmk, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ256rmkz, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ256rr, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ256rrk, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZ256rrkz, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZrm, X86_INS_VMOVSLDUP: vmovsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSLDUPZrmk, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZrmkz, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZrr, X86_INS_VMOVSLDUP: vmovsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSLDUPZrrk, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPZrrkz, X86_INS_VMOVSLDUP: vmovsldup */ 0, { 0 } }, { /* X86_VMOVSLDUPrm, X86_INS_VMOVSLDUP: vmovsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSLDUPrr, X86_INS_VMOVSLDUP: vmovsldup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSS2DIZmr, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSS2DIZrr, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSS2DImr, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSS2DIrr, X86_INS_VMOVD: vmovd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSSZmr, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSZmrk, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSZrm, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSSZrmk, X86_INS_VMOVSS: vmovss */ 0, { 0 } }, { /* X86_VMOVSSZrmkz, X86_INS_VMOVSS: vmovss */ 0, { 0 } }, { /* X86_VMOVSSZrr, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSZrr_REV, X86_INS_VMOVSS: vmovss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSZrrk, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSZrrk_REV, X86_INS_VMOVSS: vmovss */ 0, { 0 } }, { /* X86_VMOVSSZrrkz, X86_INS_VMOVSS: vmovss */ 0, { 0 } }, { /* X86_VMOVSSZrrkz_REV, X86_INS_VMOVSS: vmovss */ 0, { 0 } }, { /* X86_VMOVSSmr, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSrm, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVSSrr, X86_INS_VMOVSS: vmovss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVSSrr_REV, X86_INS_VMOVSS: vmovss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDYmr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDYrm, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDYrr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDYrr_REV, X86_INS_VMOVUPD: vmovupd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128mr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128mrk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rm, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rmk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rmkz, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rr_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZ128rrk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rrk_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZ128rrkz, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ128rrkz_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZ256mr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256mrk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rm, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rmk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rmkz, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rr_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZ256rrk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rrk_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZ256rrkz, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZ256rrkz_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZmr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZmrk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrm, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrmk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrmkz, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrr_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZrrk, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrrk_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDZrrkz, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDZrrkz_REV, X86_INS_VMOVUPD: vmovupd */ 0, { 0 } }, { /* X86_VMOVUPDmr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPDrm, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDrr, X86_INS_VMOVUPD: vmovupd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPDrr_REV, X86_INS_VMOVUPD: vmovupd $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSYmr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSYrm, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSYrr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSYrr_REV, X86_INS_VMOVUPS: vmovups $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128mr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128mrk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rm, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rmk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rmkz, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rr_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZ128rrk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rrk_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZ128rrkz, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ128rrkz_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZ256mr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256mrk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rm, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rmk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rmkz, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rr_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZ256rrk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rrk_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZ256rrkz, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZ256rrkz_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZmr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZmrk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrm, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrmk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrmkz, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrr_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZrrk, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrrk_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSZrrkz, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSZrrkz_REV, X86_INS_VMOVUPS: vmovups */ 0, { 0 } }, { /* X86_VMOVUPSmr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMOVUPSrm, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSrr, X86_INS_VMOVUPS: vmovups */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVUPSrr_REV, X86_INS_VMOVUPS: vmovups $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVZPQILo2PQIZrr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMOVZPQILo2PQIrr, X86_INS_VMOVQ: vmovq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMPSADBWYrmi, X86_INS_VMPSADBW: vmpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMPSADBWYrri, X86_INS_VMPSADBW: vmpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMPSADBWrmi, X86_INS_VMPSADBW: vmpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMPSADBWrri, X86_INS_VMPSADBW: vmpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMPTRLDm, X86_INS_VMPTRLD: vmptrld */ 0, { CS_AC_READ, 0 } }, { /* X86_VMPTRSTm, X86_INS_VMPTRST: vmptrst */ 0, { CS_AC_WRITE, 0 } }, { /* X86_VMREAD32mr, X86_INS_VMREAD: vmread */ 0, { 0 } }, { /* X86_VMREAD32rr, X86_INS_VMREAD: vmread */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMREAD64mr, X86_INS_VMREAD: vmread */ 0, { 0 } }, { /* X86_VMREAD64rr, X86_INS_VMREAD: vmread */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMRESUME, X86_INS_VMRESUME: vmresume */ 0, { 0 } }, { /* X86_VMRUN32, X86_INS_VMRUN: vmrun */ 0, { CS_AC_READ, 0 } }, { /* X86_VMRUN64, X86_INS_VMRUN: vmrun */ 0, { CS_AC_READ, 0 } }, { /* X86_VMSAVE32, X86_INS_VMSAVE: vmsave */ 0, { CS_AC_READ, 0 } }, { /* X86_VMSAVE64, X86_INS_VMSAVE: vmsave */ 0, { CS_AC_READ, 0 } }, { /* X86_VMULPDYrm, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDYrr, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rm, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rmb, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rmbk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rmbkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rmk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rmkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rr, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rrk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ128rrkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rm, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rmb, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rmbk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rmbkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rmk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rmkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rr, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rrk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZ256rrkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrm, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrmb, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrmbk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrmbkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrmk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrmkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrr, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrrb, X86_INS_VMULPD: vmulpd */ 0, { 0 } }, { /* X86_VMULPDZrrbk, X86_INS_VMULPD: vmulpd */ 0, { 0 } }, { /* X86_VMULPDZrrbkz, X86_INS_VMULPD: vmulpd */ 0, { 0 } }, { /* X86_VMULPDZrrk, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDZrrkz, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDrm, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPDrr, X86_INS_VMULPD: vmulpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSYrm, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSYrr, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rm, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rmb, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rmbk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rmbkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rmk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rmkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rr, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rrk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ128rrkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rm, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rmb, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rmbk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rmbkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rmk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rmkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rr, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rrk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZ256rrkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrm, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrmb, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrmbk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrmbkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrmk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrmkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrr, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrrb, X86_INS_VMULPS: vmulps */ 0, { 0 } }, { /* X86_VMULPSZrrbk, X86_INS_VMULPS: vmulps */ 0, { 0 } }, { /* X86_VMULPSZrrbkz, X86_INS_VMULPS: vmulps */ 0, { 0 } }, { /* X86_VMULPSZrrk, X86_INS_VMULPS: vmulps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSZrrkz, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSrm, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULPSrr, X86_INS_VMULPS: vmulps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrm, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrm_Int, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrm_Intk, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrm_Intkz, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrr, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrr_Int, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrr_Intk, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrr_Intkz, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDZrrb_Int, X86_INS_VMULSD: vmulsd */ 0, { 0 } }, { /* X86_VMULSDZrrb_Intk, X86_INS_VMULSD: vmulsd */ 0, { 0 } }, { /* X86_VMULSDZrrb_Intkz, X86_INS_VMULSD: vmulsd */ 0, { 0 } }, { /* X86_VMULSDrm, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDrm_Int, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMULSDrr, X86_INS_VMULSD: vmulsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSDrr_Int, X86_INS_VMULSD: vmulsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrm, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrm_Int, X86_INS_VMULSS: vmulss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrm_Intk, X86_INS_VMULSS: vmulss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrm_Intkz, X86_INS_VMULSS: vmulss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrr, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrr_Int, X86_INS_VMULSS: vmulss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrr_Intk, X86_INS_VMULSS: vmulss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrr_Intkz, X86_INS_VMULSS: vmulss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSZrrb_Int, X86_INS_VMULSS: vmulss */ 0, { 0 } }, { /* X86_VMULSSZrrb_Intk, X86_INS_VMULSS: vmulss */ 0, { 0 } }, { /* X86_VMULSSZrrb_Intkz, X86_INS_VMULSS: vmulss */ 0, { 0 } }, { /* X86_VMULSSrm, X86_INS_VMULSS: vmulss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSrm_Int, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VMULSSrr, X86_INS_VMULSS: vmulss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMULSSrr_Int, X86_INS_VMULSS: vmulss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VMWRITE32rm, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMWRITE32rr, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMWRITE64rm, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMWRITE64rr, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMXOFF, X86_INS_VMXOFF: vmxoff */ 0, { 0 } }, { /* X86_VMXON, X86_INS_VMXON: vmxon */ 0, { CS_AC_READ, 0 } }, { /* X86_VORPDYrm, X86_INS_VORPD: vorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPDYrr, X86_INS_VORPD: vorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPDZ128rm, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rmb, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rmbk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rmbkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rmk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rmkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rr, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rrk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ128rrkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rm, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rmb, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rmbk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rmbkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rmk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rmkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rr, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rrk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZ256rrkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrm, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrmb, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrmbk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrmbkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrmk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrmkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrr, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrrk, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDZrrkz, X86_INS_VORPD: vorpd */ 0, { 0 } }, { /* X86_VORPDrm, X86_INS_VORPD: vorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPDrr, X86_INS_VORPD: vorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPSYrm, X86_INS_VORPS: vorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPSYrr, X86_INS_VORPS: vorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPSZ128rm, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rmb, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rmbk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rmbkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rmk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rmkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rr, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rrk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ128rrkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rm, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rmb, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rmbk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rmbkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rmk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rmkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rr, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rrk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZ256rrkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrm, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrmb, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrmbk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrmbkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrmk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrmkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrr, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrrk, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSZrrkz, X86_INS_VORPS: vorps */ 0, { 0 } }, { /* X86_VORPSrm, X86_INS_VORPS: vorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VORPSrr, X86_INS_VORPS: vorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VP4DPWSSDSrm, X86_INS_VP4DPWSSDS: vp4dpwssds */ 0, { 0 } }, { /* X86_VP4DPWSSDSrmk, X86_INS_VP4DPWSSDS: vp4dpwssds */ 0, { 0 } }, { /* X86_VP4DPWSSDSrmkz, X86_INS_VP4DPWSSDS: vp4dpwssds */ 0, { 0 } }, { /* X86_VP4DPWSSDrm, X86_INS_VP4DPWSSD: vp4dpwssd */ 0, { 0 } }, { /* X86_VP4DPWSSDrmk, X86_INS_VP4DPWSSD: vp4dpwssd */ 0, { 0 } }, { /* X86_VP4DPWSSDrmkz, X86_INS_VP4DPWSSD: vp4dpwssd */ 0, { 0 } }, { /* X86_VPABSBYrm, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBYrr, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ128rm, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ128rmk, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ128rmkz, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ128rr, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ128rrk, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ128rrkz, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ256rm, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ256rmk, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ256rmkz, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ256rr, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ256rrk, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZ256rrkz, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZrm, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZrmk, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZrmkz, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZrr, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZrrk, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBZrrkz, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBrm, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSBrr, X86_INS_VPABSB: vpabsb */ 0, { 0 } }, { /* X86_VPABSDYrm, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDYrr, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rm, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rmb, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rmbk, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rmbkz, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rmk, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rmkz, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rr, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rrk, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ128rrkz, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rm, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rmb, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rmbk, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rmbkz, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rmk, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rmkz, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rr, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rrk, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZ256rrkz, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDZrm, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrmb, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrmbk, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrmbkz, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrmk, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrmkz, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrr, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrrk, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDZrrkz, X86_INS_VPABSD: vpabsd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSDrm, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSDrr, X86_INS_VPABSD: vpabsd */ 0, { 0 } }, { /* X86_VPABSQZ128rm, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rmb, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rmbk, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rmbkz, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rmk, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rmkz, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rr, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rrk, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ128rrkz, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rm, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rmb, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rmbk, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rmbkz, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rmk, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rmkz, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rr, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rrk, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZ256rrkz, X86_INS_VPABSQ: vpabsq */ 0, { 0 } }, { /* X86_VPABSQZrm, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrmb, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrmbk, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrmbkz, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrmk, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrmkz, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrr, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrrk, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSQZrrkz, X86_INS_VPABSQ: vpabsq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPABSWYrm, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWYrr, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ128rm, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ128rmk, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ128rmkz, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ128rr, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ128rrk, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ128rrkz, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ256rm, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ256rmk, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ256rmkz, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ256rr, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ256rrk, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZ256rrkz, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZrm, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZrmk, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZrmkz, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZrr, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZrrk, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWZrrkz, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWrm, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPABSWrr, X86_INS_VPABSW: vpabsw */ 0, { 0 } }, { /* X86_VPACKSSDWYrm, X86_INS_VPACKSSDW: vpackssdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSDWYrr, X86_INS_VPACKSSDW: vpackssdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSDWZ128rm, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rmb, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rmbk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rmbkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rmk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rmkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rr, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rrk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ128rrkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rm, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rmb, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rmbk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rmbkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rmk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rmkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rr, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rrk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZ256rrkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrm, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrmb, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrmbk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrmbkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrmk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrmkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrr, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrrk, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWZrrkz, X86_INS_VPACKSSDW: vpackssdw */ 0, { 0 } }, { /* X86_VPACKSSDWrm, X86_INS_VPACKSSDW: vpackssdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSDWrr, X86_INS_VPACKSSDW: vpackssdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSWBYrm, X86_INS_VPACKSSWB: vpacksswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSWBYrr, X86_INS_VPACKSSWB: vpacksswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSWBZ128rm, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ128rmk, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ128rmkz, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ128rr, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ128rrk, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ128rrkz, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ256rm, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ256rmk, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ256rmkz, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ256rr, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ256rrk, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZ256rrkz, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZrm, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZrmk, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZrmkz, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZrr, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZrrk, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBZrrkz, X86_INS_VPACKSSWB: vpacksswb */ 0, { 0 } }, { /* X86_VPACKSSWBrm, X86_INS_VPACKSSWB: vpacksswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKSSWBrr, X86_INS_VPACKSSWB: vpacksswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSDWYrm, X86_INS_VPACKUSDW: vpackusdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSDWYrr, X86_INS_VPACKUSDW: vpackusdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSDWZ128rm, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rmb, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rmbk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rmbkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rmk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rmkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rr, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rrk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ128rrkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rm, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rmb, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rmbk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rmbkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rmk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rmkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rr, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rrk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZ256rrkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrm, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrmb, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrmbk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrmbkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrmk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrmkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrr, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrrk, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWZrrkz, X86_INS_VPACKUSDW: vpackusdw */ 0, { 0 } }, { /* X86_VPACKUSDWrm, X86_INS_VPACKUSDW: vpackusdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSDWrr, X86_INS_VPACKUSDW: vpackusdw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSWBYrm, X86_INS_VPACKUSWB: vpackuswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSWBYrr, X86_INS_VPACKUSWB: vpackuswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSWBZ128rm, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ128rmk, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ128rmkz, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ128rr, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ128rrk, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ128rrkz, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ256rm, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ256rmk, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ256rmkz, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ256rr, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ256rrk, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZ256rrkz, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZrm, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZrmk, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZrmkz, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZrr, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZrrk, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBZrrkz, X86_INS_VPACKUSWB: vpackuswb */ 0, { 0 } }, { /* X86_VPACKUSWBrm, X86_INS_VPACKUSWB: vpackuswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPACKUSWBrr, X86_INS_VPACKUSWB: vpackuswb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBYrm, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBYrr, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ128rm, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ128rmk, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ128rmkz, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ128rr, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ128rrk, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ128rrkz, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ256rm, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ256rmk, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ256rmkz, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ256rr, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ256rrk, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZ256rrkz, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZrm, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZrmk, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZrmkz, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZrr, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZrrk, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBZrrkz, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBrm, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDBrr, X86_INS_VPADDB: vpaddb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDYrm, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDYrr, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rm, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rmb, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rmbk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rmbkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rmk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rmkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rr, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rrk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ128rrkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rm, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rmb, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rmbk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rmbkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rmk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rmkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rr, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rrk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZ256rrkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrm, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrmb, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrmbk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrmbkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrmk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrmkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrr, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrrk, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDZrrkz, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDrm, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDDrr, X86_INS_VPADDD: vpaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQYrm, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQYrr, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rm, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rmb, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rmbk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rmbkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rmk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rmkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rr, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rrk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ128rrkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rm, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rmb, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rmbk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rmbkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rmk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rmkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rr, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rrk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZ256rrkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrm, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrmb, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrmbk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrmbkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrmk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrmkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrr, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrrk, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQZrrkz, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQrm, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDQrr, X86_INS_VPADDQ: vpaddq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSBYrm, X86_INS_VPADDSB: vpaddsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSBYrr, X86_INS_VPADDSB: vpaddsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSBZ128rm, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ128rmk, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ128rmkz, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ128rr, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ128rrk, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ128rrkz, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ256rm, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ256rmk, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ256rmkz, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ256rr, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ256rrk, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZ256rrkz, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZrm, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZrmk, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZrmkz, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZrr, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZrrk, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBZrrkz, X86_INS_VPADDSB: vpaddsb */ 0, { 0 } }, { /* X86_VPADDSBrm, X86_INS_VPADDSB: vpaddsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSBrr, X86_INS_VPADDSB: vpaddsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSWYrm, X86_INS_VPADDSW: vpaddsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSWYrr, X86_INS_VPADDSW: vpaddsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSWZ128rm, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ128rmk, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ128rmkz, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ128rr, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ128rrk, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ128rrkz, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ256rm, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ256rmk, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ256rmkz, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ256rr, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ256rrk, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZ256rrkz, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZrm, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZrmk, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZrmkz, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZrr, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZrrk, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWZrrkz, X86_INS_VPADDSW: vpaddsw */ 0, { 0 } }, { /* X86_VPADDSWrm, X86_INS_VPADDSW: vpaddsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDSWrr, X86_INS_VPADDSW: vpaddsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSBYrm, X86_INS_VPADDUSB: vpaddusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSBYrr, X86_INS_VPADDUSB: vpaddusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSBZ128rm, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ128rmk, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ128rmkz, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ128rr, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ128rrk, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ128rrkz, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ256rm, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ256rmk, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ256rmkz, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ256rr, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ256rrk, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZ256rrkz, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZrm, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZrmk, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZrmkz, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZrr, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZrrk, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBZrrkz, X86_INS_VPADDUSB: vpaddusb */ 0, { 0 } }, { /* X86_VPADDUSBrm, X86_INS_VPADDUSB: vpaddusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSBrr, X86_INS_VPADDUSB: vpaddusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSWYrm, X86_INS_VPADDUSW: vpaddusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSWYrr, X86_INS_VPADDUSW: vpaddusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSWZ128rm, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ128rmk, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ128rmkz, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ128rr, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ128rrk, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ128rrkz, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ256rm, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ256rmk, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ256rmkz, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ256rr, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ256rrk, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZ256rrkz, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZrm, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZrmk, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZrmkz, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZrr, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZrrk, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWZrrkz, X86_INS_VPADDUSW: vpaddusw */ 0, { 0 } }, { /* X86_VPADDUSWrm, X86_INS_VPADDUSW: vpaddusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDUSWrr, X86_INS_VPADDUSW: vpaddusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWYrm, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWYrr, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ128rm, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ128rmk, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ128rmkz, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ128rr, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ128rrk, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ128rrkz, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ256rm, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ256rmk, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ256rmkz, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ256rr, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ256rrk, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZ256rrkz, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZrm, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZrmk, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZrmkz, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZrr, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZrrk, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWZrrkz, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWrm, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPADDWrr, X86_INS_VPADDW: vpaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPALIGNRYrmi, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRYrri, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ128rmi, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ128rmik, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ128rmikz, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ128rri, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ128rrik, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ128rrikz, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ256rmi, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ256rmik, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ256rmikz, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ256rri, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ256rrik, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZ256rrikz, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZrmi, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZrmik, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZrmikz, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZrri, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZrrik, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRZrrikz, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRrmi, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPALIGNRrri, X86_INS_VPALIGNR: vpalignr */ 0, { 0 } }, { /* X86_VPANDDZ128rm, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rmb, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rmbk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rmbkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rmk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rmkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rr, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rrk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ128rrkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rm, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rmb, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rmbk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rmbkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rmk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rmkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rr, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rrk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZ256rrkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrm, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrmb, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrmbk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrmbkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrmk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrmkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrr, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrrk, X86_INS_VPANDD: vpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDDZrrkz, X86_INS_VPANDD: vpandd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rm, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rmb, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rmbk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rmbkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rmk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rmkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rr, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rrk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ128rrkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rm, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rmb, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rmbk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rmbkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rmk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rmkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rr, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rrk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZ256rrkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrm, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrmb, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrmbk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrmbkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrmk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrmkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrr, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrrk, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNDZrrkz, X86_INS_VPANDND: vpandnd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rm, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rmb, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rmbk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rmbkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rmk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rmkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rr, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rrk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ128rrkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rm, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rmb, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rmbk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rmbkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rmk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rmkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rr, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rrk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZ256rrkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrm, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrmb, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrmbk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrmbkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrmk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrmkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrr, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrrk, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNQZrrkz, X86_INS_VPANDNQ: vpandnq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNYrm, X86_INS_VPANDN: vpandn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNYrr, X86_INS_VPANDN: vpandn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNrm, X86_INS_VPANDN: vpandn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDNrr, X86_INS_VPANDN: vpandn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rm, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rmb, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rmbk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rmbkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rmk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rmkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rr, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rrk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ128rrkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rm, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rmb, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rmbk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rmbkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rmk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rmkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rr, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rrk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZ256rrkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrm, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrmb, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrmbk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrmbkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrmk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrmkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrr, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrrk, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDQZrrkz, X86_INS_VPANDQ: vpandq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDYrm, X86_INS_VPAND: vpand */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDYrr, X86_INS_VPAND: vpand */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDrm, X86_INS_VPAND: vpand */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPANDrr, X86_INS_VPAND: vpand */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGBYrm, X86_INS_VPAVGB: vpavgb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGBYrr, X86_INS_VPAVGB: vpavgb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGBZ128rm, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ128rmk, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ128rmkz, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ128rr, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ128rrk, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ128rrkz, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ256rm, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ256rmk, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ256rmkz, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ256rr, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ256rrk, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZ256rrkz, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZrm, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZrmk, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZrmkz, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZrr, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZrrk, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBZrrkz, X86_INS_VPAVGB: vpavgb */ 0, { 0 } }, { /* X86_VPAVGBrm, X86_INS_VPAVGB: vpavgb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGBrr, X86_INS_VPAVGB: vpavgb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGWYrm, X86_INS_VPAVGW: vpavgw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGWYrr, X86_INS_VPAVGW: vpavgw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGWZ128rm, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ128rmk, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ128rmkz, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ128rr, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ128rrk, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ128rrkz, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ256rm, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ256rmk, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ256rmkz, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ256rr, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ256rrk, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZ256rrkz, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZrm, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZrmk, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZrmkz, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZrr, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZrrk, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWZrrkz, X86_INS_VPAVGW: vpavgw */ 0, { 0 } }, { /* X86_VPAVGWrm, X86_INS_VPAVGW: vpavgw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPAVGWrr, X86_INS_VPAVGW: vpavgw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDDYrmi, X86_INS_VPBLENDD: vpblendd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDDYrri, X86_INS_VPBLENDD: vpblendd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDDrmi, X86_INS_VPBLENDD: vpblendd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDDrri, X86_INS_VPBLENDD: vpblendd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDMBZ128rm, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ128rmk, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ128rmkz, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ128rr, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ128rrk, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ128rrkz, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ256rm, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ256rmk, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ256rmkz, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ256rr, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ256rrk, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZ256rrkz, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZrm, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZrmk, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZrmkz, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZrr, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZrrk, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMBZrrkz, X86_INS_VPBLENDMB: vpblendmb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rm, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rmb, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rmbk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rmbkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { 0 } }, { /* X86_VPBLENDMDZ128rmk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rmkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rr, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rrk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ128rrkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rm, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rmb, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rmbk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rmbkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { 0 } }, { /* X86_VPBLENDMDZ256rmk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rmkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rr, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rrk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZ256rrkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrm, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrmb, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrmbk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrmbkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { 0 } }, { /* X86_VPBLENDMDZrmk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrmkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrr, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrrk, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMDZrrkz, X86_INS_VPBLENDMD: vpblendmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rm, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rmb, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rmbk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rmbkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { 0 } }, { /* X86_VPBLENDMQZ128rmk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rmkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rr, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rrk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ128rrkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rm, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rmb, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rmbk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rmbkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { 0 } }, { /* X86_VPBLENDMQZ256rmk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rmkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rr, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rrk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZ256rrkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrm, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrmb, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrmbk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrmbkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { 0 } }, { /* X86_VPBLENDMQZrmk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrmkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrr, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrrk, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMQZrrkz, X86_INS_VPBLENDMQ: vpblendmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ128rm, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ128rmk, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ128rmkz, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ128rr, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ128rrk, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ128rrkz, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ256rm, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ256rmk, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ256rmkz, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ256rr, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ256rrk, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZ256rrkz, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZrm, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZrmk, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZrmkz, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZrr, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZrrk, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDMWZrrkz, X86_INS_VPBLENDMW: vpblendmw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDVBYrm, X86_INS_VPBLENDVB: vpblendvb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDVBYrr, X86_INS_VPBLENDVB: vpblendvb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDVBrm, X86_INS_VPBLENDVB: vpblendvb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDVBrr, X86_INS_VPBLENDVB: vpblendvb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPBLENDWYrmi, X86_INS_VPBLENDW: vpblendw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDWYrri, X86_INS_VPBLENDW: vpblendw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDWrmi, X86_INS_VPBLENDW: vpblendw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBLENDWrri, X86_INS_VPBLENDW: vpblendw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPBROADCASTBYrm, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBYrr, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBZ128m, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ128mk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ128mkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ128r, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ128rk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ128rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ256m, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ256mk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ256mkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ256r, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ256rk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZ256rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZm, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZmk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZmkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZr, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZrk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBZrkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { 0 } }, { /* X86_VPBROADCASTBrZ128r, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZ128rk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZ128rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZ256r, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZ256rk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZ256rkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZr, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZrk, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrZrkz, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrm, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTBrr, X86_INS_VPBROADCASTB: vpbroadcastb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDYrm, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDYrr, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDZ128m, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ128mk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ128mkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ128r, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ128rk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ128rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ256m, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ256mk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ256mkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ256r, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ256rk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZ256rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZm, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZmk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZmkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZr, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZrk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDZrkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { 0 } }, { /* X86_VPBROADCASTDrZ128r, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZ128rk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZ128rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZ256r, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZ256rk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZ256rkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZr, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZrk, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrZrkz, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrm, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTDrr, X86_INS_VPBROADCASTD: vpbroadcastd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTMB2QZ128rr, X86_INS_VPBROADCASTMB2Q: vpbroadcastmb2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTMB2QZ256rr, X86_INS_VPBROADCASTMB2Q: vpbroadcastmb2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTMB2QZrr, X86_INS_VPBROADCASTMB2Q: vpbroadcastmb2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTMW2DZ128rr, X86_INS_VPBROADCASTMW2D: vpbroadcastmw2d */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTMW2DZ256rr, X86_INS_VPBROADCASTMW2D: vpbroadcastmw2d */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTMW2DZrr, X86_INS_VPBROADCASTMW2D: vpbroadcastmw2d */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQYrm, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQYrr, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQZ128m, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ128mk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ128mkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ128r, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ128rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ128rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ256m, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ256mk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ256mkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ256r, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ256rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZ256rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZm, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZmk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZmkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZr, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZrk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQZrkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { 0 } }, { /* X86_VPBROADCASTQrZ128r, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZ128rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZ128rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZ256r, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZ256rk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZ256rkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZr, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZrk, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrZrkz, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrm, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTQrr, X86_INS_VPBROADCASTQ: vpbroadcastq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWYrm, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWYrr, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWZ128m, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ128mk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ128mkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ128r, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ128rk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ128rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ256m, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ256mk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ256mkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ256r, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ256rk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZ256rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZm, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZmk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZmkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZr, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZrk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWZrkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { 0 } }, { /* X86_VPBROADCASTWrZ128r, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZ128rk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZ128rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZ256r, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZ256rk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZ256rkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZr, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZrk, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrZrkz, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrm, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPBROADCASTWrr, X86_INS_VPBROADCASTW: vpbroadcastw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCLMULQDQYrm, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQYrr, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQZ128rm, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQZ128rr, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQZ256rm, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQZ256rr, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQZrm, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQZrr, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { 0 } }, { /* X86_VPCLMULQDQrm, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCLMULQDQrr, X86_INS_VPCLMULQDQ: vpclmulqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMOVYrmr, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVYrrm, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVYrrr, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVYrrr_REV, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVrmr, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVrrm, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVrrr, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMOVrrr_REV, X86_INS_VPCMOV: vpcmov */ 0, { 0 } }, { /* X86_VPCMPBZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ128rmi_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ128rmik_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ128rri_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ128rrik_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ256rmi_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ256rmik_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ256rri_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZ256rrik_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZrmi_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZrmik_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZrri_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPBZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPBZrrik_alt, X86_INS_VPCMPB: vpcmpb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ128rmi_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ128rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ128rmib_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ128rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ128rmibk_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ128rmik_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ128rri_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ128rrik_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ256rmi_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ256rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ256rmib_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ256rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ256rmibk_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ256rmik_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ256rri_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZ256rrik_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZrmi_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZrmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZrmib_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZrmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZrmibk_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZrmik_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZrri_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPDZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPDZrrik_alt, X86_INS_VPCMPD: vpcmpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPEQBYrm, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBYrr, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ128rm, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ128rmk, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ128rr, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ128rrk, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ256rm, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ256rmk, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ256rr, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZ256rrk, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZrm, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZrmk, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZrr, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBZrrk, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBrm, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQBrr, X86_INS_VPCMPEQB: vpcmpeqb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDYrm, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDYrr, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ128rm, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ128rmb, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ128rmbk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ128rmk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ128rr, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ128rrk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ256rm, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ256rmb, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ256rmbk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ256rmk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ256rr, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZ256rrk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZrm, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZrmb, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZrmbk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZrmk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZrr, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDZrrk, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDrm, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQDrr, X86_INS_VPCMPEQD: vpcmpeqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQYrm, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQYrr, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ128rm, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ128rmb, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ128rmbk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ128rmk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ128rr, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ128rrk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ256rm, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ256rmb, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ256rmbk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ256rmk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ256rr, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZ256rrk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZrm, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZrmb, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZrmbk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZrmk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZrr, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQZrrk, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQrm, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQQrr, X86_INS_VPCMPEQQ: vpcmpeqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWYrm, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWYrr, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ128rm, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ128rmk, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ128rr, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ128rrk, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ256rm, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ256rmk, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ256rr, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZ256rrk, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZrm, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZrmk, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZrr, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWZrrk, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWrm, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPEQWrr, X86_INS_VPCMPEQW: vpcmpeqw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPESTRIrm, X86_INS_VPCMPESTRI: vpcmpestri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPESTRIrr, X86_INS_VPCMPESTRI: vpcmpestri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPESTRMrm, X86_INS_VPCMPESTRM: vpcmpestrm */ 0, { 0 } }, { /* X86_VPCMPESTRMrr, X86_INS_VPCMPESTRM: vpcmpestrm */ 0, { 0 } }, { /* X86_VPCMPGTBYrm, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBYrr, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ128rm, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ128rmk, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ128rr, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ128rrk, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ256rm, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ256rmk, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ256rr, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZ256rrk, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZrm, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZrmk, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZrr, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBZrrk, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBrm, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTBrr, X86_INS_VPCMPGTB: vpcmpgtb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDYrm, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDYrr, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ128rm, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ128rmb, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ128rmbk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ128rmk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ128rr, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ128rrk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ256rm, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ256rmb, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ256rmbk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ256rmk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ256rr, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZ256rrk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZrm, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZrmb, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZrmbk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZrmk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZrr, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDZrrk, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDrm, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTDrr, X86_INS_VPCMPGTD: vpcmpgtd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQYrm, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQYrr, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ128rm, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ128rmb, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ128rmbk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ128rmk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ128rr, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ128rrk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ256rm, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ256rmb, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ256rmbk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ256rmk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ256rr, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZ256rrk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZrm, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZrmb, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZrmbk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZrmk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZrr, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQZrrk, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQrm, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTQrr, X86_INS_VPCMPGTQ: vpcmpgtq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWYrm, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWYrr, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ128rm, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ128rmk, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ128rr, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ128rrk, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ256rm, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ256rmk, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ256rr, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZ256rrk, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZrm, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZrmk, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZrr, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWZrrk, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWrm, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPGTWrr, X86_INS_VPCMPGTW: vpcmpgtw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPISTRIrm, X86_INS_VPCMPISTRI: vpcmpistri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPISTRIrr, X86_INS_VPCMPISTRI: vpcmpistri */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPISTRMrm, X86_INS_VPCMPISTRM: vpcmpistrm */ 0, { 0 } }, { /* X86_VPCMPISTRMrr, X86_INS_VPCMPISTRM: vpcmpistrm */ 0, { 0 } }, { /* X86_VPCMPQZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ128rmi_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ128rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ128rmib_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ128rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ128rmibk_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ128rmik_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ128rri_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ128rrik_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ256rmi_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ256rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ256rmib_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ256rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ256rmibk_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ256rmik_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ256rri_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZ256rrik_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZrmi_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZrmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZrmib_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZrmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZrmibk_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZrmik_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZrri_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPQZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPQZrrik_alt, X86_INS_VPCMPQ: vpcmpq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ128rmi_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ128rmik_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ128rri_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ128rrik_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ256rmi_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ256rmik_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ256rri_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZ256rrik_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZrmi_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZrmik_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZrri_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUBZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUBZrrik_alt, X86_INS_VPCMPUB: vpcmpub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ128rmi_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ128rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ128rmib_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ128rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ128rmibk_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ128rmik_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ128rri_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ128rrik_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ256rmi_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ256rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ256rmib_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ256rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ256rmibk_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ256rmik_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ256rri_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZ256rrik_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZrmi_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZrmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZrmib_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZrmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZrmibk_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZrmik_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZrri_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUDZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUDZrrik_alt, X86_INS_VPCMPUD: vpcmpud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ128rmi_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ128rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ128rmib_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ128rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ128rmibk_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ128rmik_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ128rri_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ128rrik_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ256rmi_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ256rmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ256rmib_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ256rmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ256rmibk_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ256rmik_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ256rri_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZ256rrik_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZrmi_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZrmib, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZrmib_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZrmibk, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZrmibk_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZrmik_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZrri_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUQZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUQZrrik_alt, X86_INS_VPCMPUQ: vpcmpuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ128rmi_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ128rmik_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ128rri_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ128rrik_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ256rmi_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ256rmik_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ256rri_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZ256rrik_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZrmi_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZrmik_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZrri_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPUWZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPUWZrrik_alt, X86_INS_VPCMPUW: vpcmpuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ128rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ128rmi_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ128rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ128rmik_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ128rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ128rri_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ128rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ128rrik_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ256rmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ256rmi_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ256rmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ256rmik_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ256rri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ256rri_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZ256rrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZ256rrik_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZrmi, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZrmi_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZrmik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZrmik_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZrri, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZrri_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCMPWZrrik, X86_INS_VPCMP: vpcmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCMPWZrrik_alt, X86_INS_VPCMPW: vpcmpw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMBmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMBmi_alt, X86_INS_VPCOMB: vpcomb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMBri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMBri_alt, X86_INS_VPCOMB: vpcomb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMDmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMDmi_alt, X86_INS_VPCOMD: vpcomd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMDri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMDri_alt, X86_INS_VPCOMD: vpcomd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMPRESSBZ128mr, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ128mrk, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ128rr, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ128rrk, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ128rrkz, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ256mr, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ256mrk, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ256rr, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ256rrk, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZ256rrkz, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZmr, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZmrk, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZrr, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZrrk, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSBZrrkz, X86_INS_VPCOMPRESSB: vpcompressb */ 0, { 0 } }, { /* X86_VPCOMPRESSDZ128mr, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { 0 } }, { /* X86_VPCOMPRESSDZ128mrk, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZ128rr, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { 0 } }, { /* X86_VPCOMPRESSDZ128rrk, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZ128rrkz, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZ256mr, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { 0 } }, { /* X86_VPCOMPRESSDZ256mrk, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZ256rr, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { 0 } }, { /* X86_VPCOMPRESSDZ256rrk, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZ256rrkz, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZmr, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { 0 } }, { /* X86_VPCOMPRESSDZmrk, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZrr, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { 0 } }, { /* X86_VPCOMPRESSDZrrk, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSDZrrkz, X86_INS_VPCOMPRESSD: vpcompressd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZ128mr, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { 0 } }, { /* X86_VPCOMPRESSQZ128mrk, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZ128rr, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { 0 } }, { /* X86_VPCOMPRESSQZ128rrk, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZ128rrkz, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZ256mr, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { 0 } }, { /* X86_VPCOMPRESSQZ256mrk, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZ256rr, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { 0 } }, { /* X86_VPCOMPRESSQZ256rrk, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZ256rrkz, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZmr, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { 0 } }, { /* X86_VPCOMPRESSQZmrk, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZrr, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { 0 } }, { /* X86_VPCOMPRESSQZrrk, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSQZrrkz, X86_INS_VPCOMPRESSQ: vpcompressq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPCOMPRESSWZ128mr, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ128mrk, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ128rr, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ128rrk, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ128rrkz, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ256mr, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ256mrk, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ256rr, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ256rrk, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZ256rrkz, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZmr, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZmrk, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZrr, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZrrk, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMPRESSWZrrkz, X86_INS_VPCOMPRESSW: vpcompressw */ 0, { 0 } }, { /* X86_VPCOMQmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMQmi_alt, X86_INS_VPCOMQ: vpcomq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMQri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMQri_alt, X86_INS_VPCOMQ: vpcomq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUBmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUBmi_alt, X86_INS_VPCOMUB: vpcomub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUBri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUBri_alt, X86_INS_VPCOMUB: vpcomub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUDmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUDmi_alt, X86_INS_VPCOMUD: vpcomud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUDri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUDri_alt, X86_INS_VPCOMUD: vpcomud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUQmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUQmi_alt, X86_INS_VPCOMUQ: vpcomuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUQri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUQri_alt, X86_INS_VPCOMUQ: vpcomuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUWmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUWmi_alt, X86_INS_VPCOMUW: vpcomuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMUWri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMUWri_alt, X86_INS_VPCOMUW: vpcomuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMWmi, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMWmi_alt, X86_INS_VPCOMW: vpcomw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCOMWri, X86_INS_VPCOM: vpcom */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPCOMWri_alt, X86_INS_VPCOMW: vpcomw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPCONFLICTDZ128rm, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rmb, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rmbk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rmbkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rmk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rmkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rr, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rrk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ128rrkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rm, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rmb, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rmbk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rmbkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rmk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rmkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rr, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rrk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZ256rrkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrm, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrmb, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrmbk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrmbkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrmk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrmkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrr, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrrk, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTDZrrkz, X86_INS_VPCONFLICTD: vpconflictd */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rm, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rmb, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rmbk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rmbkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rmk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rmkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rr, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rrk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ128rrkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rm, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rmb, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rmbk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rmbkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rmk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rmkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rr, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rrk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZ256rrkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrm, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrmb, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrmbk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrmbkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrmk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrmkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrr, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrrk, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPCONFLICTQZrrkz, X86_INS_VPCONFLICTQ: vpconflictq */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128m, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128mb, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128mbk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128mbkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128mk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128mkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128r, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128rk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ128rkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256m, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256mb, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256mbk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256mbkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256mk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256mkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256r, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256rk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZ256rkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZm, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZmb, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZmbk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZmbkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZmk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZmkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZr, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZrk, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDSZrkz, X86_INS_VPDPBUSDS: vpdpbusds */ 0, { 0 } }, { /* X86_VPDPBUSDZ128m, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128mb, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128mbk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128mbkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128mk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128mkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128r, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128rk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ128rkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256m, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256mb, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256mbk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256mbkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256mk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256mkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256r, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256rk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZ256rkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZm, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZmb, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZmbk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZmbkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZmk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZmkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZr, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZrk, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPBUSDZrkz, X86_INS_VPDPBUSD: vpdpbusd */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128m, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128mb, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128mbk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128mbkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128mk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128mkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128r, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128rk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ128rkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256m, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256mb, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256mbk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256mbkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256mk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256mkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256r, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256rk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZ256rkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZm, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZmb, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZmbk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZmbkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZmk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZmkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZr, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZrk, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDSZrkz, X86_INS_VPDPWSSDS: vpdpwssds */ 0, { 0 } }, { /* X86_VPDPWSSDZ128m, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128mb, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128mbk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128mbkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128mk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128mkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128r, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128rk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ128rkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256m, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256mb, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256mbk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256mbkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256mk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256mkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256r, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256rk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZ256rkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZm, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZmb, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZmbk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZmbkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZmk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZmkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZr, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZrk, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPDPWSSDZrkz, X86_INS_VPDPWSSD: vpdpwssd */ 0, { 0 } }, { /* X86_VPERM2F128rm, X86_INS_VPERM2F128: vperm2f128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERM2F128rr, X86_INS_VPERM2F128: vperm2f128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERM2I128rm, X86_INS_VPERM2I128: vperm2i128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERM2I128rr, X86_INS_VPERM2I128: vperm2i128 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMBZ128rm, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ128rmk, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ128rmkz, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ128rr, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ128rrk, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ128rrkz, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ256rm, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ256rmk, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ256rmkz, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ256rr, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ256rrk, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZ256rrkz, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZrm, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZrmk, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZrmkz, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZrr, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZrrk, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMBZrrkz, X86_INS_VPERMB: vpermb */ 0, { 0 } }, { /* X86_VPERMDYrm, X86_INS_VPERMD: vpermd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMDYrr, X86_INS_VPERMD: vpermd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMDZ256rm, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rmb, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rmbk, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rmbkz, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rmk, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rmkz, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rr, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rrk, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZ256rrkz, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrm, X86_INS_VPERMD: vpermd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMDZrmb, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrmbk, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrmbkz, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrmk, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrmkz, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrr, X86_INS_VPERMD: vpermd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMDZrrk, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMDZrrkz, X86_INS_VPERMD: vpermd */ 0, { 0 } }, { /* X86_VPERMI2B128rm, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B128rmk, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B128rmkz, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B128rr, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B128rrk, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B128rrkz, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B256rm, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B256rmk, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B256rmkz, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B256rr, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B256rrk, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2B256rrkz, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2Brm, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2Brmk, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2Brmkz, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2Brr, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2Brrk, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2Brrkz, X86_INS_VPERMI2B: vpermi2b */ 0, { 0 } }, { /* X86_VPERMI2D128rm, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rmb, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rmbk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rmbkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rmk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rmkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rr, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rrk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D128rrkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rm, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rmb, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rmbk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rmbkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rmk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rmkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rr, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rrk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2D256rrkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2Drm, X86_INS_VPERMI2D: vpermi2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Drmb, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2Drmbk, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2Drmbkz, X86_INS_VPERMI2D: vpermi2d */ 0, { 0 } }, { /* X86_VPERMI2Drmk, X86_INS_VPERMI2D: vpermi2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Drmkz, X86_INS_VPERMI2D: vpermi2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Drr, X86_INS_VPERMI2D: vpermi2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Drrk, X86_INS_VPERMI2D: vpermi2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Drrkz, X86_INS_VPERMI2D: vpermi2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PD128rm, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rmb, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rmbk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rmbkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rmk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rmkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rr, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rrk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD128rrkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rm, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rmb, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rmbk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rmbkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rmk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rmkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rr, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rrk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PD256rrkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PDrm, X86_INS_VPERMI2PD: vpermi2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PDrmb, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PDrmbk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PDrmbkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { 0 } }, { /* X86_VPERMI2PDrmk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PDrmkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PDrr, X86_INS_VPERMI2PD: vpermi2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PDrrk, X86_INS_VPERMI2PD: vpermi2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PDrrkz, X86_INS_VPERMI2PD: vpermi2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PS128rm, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rmb, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rmbk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rmbkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rmk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rmkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rr, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rrk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS128rrkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rm, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rmb, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rmbk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rmbkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rmk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rmkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rr, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rrk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PS256rrkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PSrm, X86_INS_VPERMI2PS: vpermi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PSrmb, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PSrmbk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PSrmbkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { 0 } }, { /* X86_VPERMI2PSrmk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PSrmkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PSrr, X86_INS_VPERMI2PS: vpermi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PSrrk, X86_INS_VPERMI2PS: vpermi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2PSrrkz, X86_INS_VPERMI2PS: vpermi2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Q128rm, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rmb, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rmbk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rmbkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rmk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rmkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rr, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rrk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q128rrkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rm, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rmb, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rmbk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rmbkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rmk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rmkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rr, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rrk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Q256rrkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Qrm, X86_INS_VPERMI2Q: vpermi2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Qrmb, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Qrmbk, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Qrmbkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { 0 } }, { /* X86_VPERMI2Qrmk, X86_INS_VPERMI2Q: vpermi2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Qrmkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Qrr, X86_INS_VPERMI2Q: vpermi2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Qrrk, X86_INS_VPERMI2Q: vpermi2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2Qrrkz, X86_INS_VPERMI2Q: vpermi2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMI2W128rm, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W128rmk, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W128rmkz, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W128rr, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W128rrk, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W128rrkz, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W256rm, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W256rmk, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W256rmkz, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W256rr, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W256rrk, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2W256rrkz, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2Wrm, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2Wrmk, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2Wrmkz, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2Wrr, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2Wrrk, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMI2Wrrkz, X86_INS_VPERMI2W: vpermi2w */ 0, { 0 } }, { /* X86_VPERMIL2PDYmr, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { 0 } }, { /* X86_VPERMIL2PDYrm, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { 0 } }, { /* X86_VPERMIL2PDYrr, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { 0 } }, { /* X86_VPERMIL2PDYrr_REV, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMIL2PDmr, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMIL2PDrm, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMIL2PDrr, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMIL2PDrr_REV, X86_INS_VPERMIL2PD: vpermil2pd */ 0, { 0 } }, { /* X86_VPERMIL2PSYmr, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { 0 } }, { /* X86_VPERMIL2PSYrm, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { 0 } }, { /* X86_VPERMIL2PSYrr, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { 0 } }, { /* X86_VPERMIL2PSYrr_REV, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMIL2PSmr, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMIL2PSrm, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMIL2PSrr, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMIL2PSrr_REV, X86_INS_VPERMIL2PS: vpermil2ps */ 0, { 0 } }, { /* X86_VPERMILPDYmi, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPDYri, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPDYrm, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPDYrr, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPDZ128mbi, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128mbik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128mbikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128mi, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128mik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128mikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128ri, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rm, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rmb, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rmbk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rmbkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rmk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rmkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rr, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rrk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ128rrkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256mbi, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256mbik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256mbikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256mi, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256mik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256mikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256ri, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rm, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rmb, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rmbk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rmbkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rmk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rmkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rr, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rrk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZ256rrkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZmbi, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZmbik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZmbikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZmi, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPDZmik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZmikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZri, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPDZrik, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrikz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrm, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPDZrmb, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrmbk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrmbkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrmk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrmkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrr, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPDZrrk, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDZrrkz, X86_INS_VPERMILPD: vpermilpd */ 0, { 0 } }, { /* X86_VPERMILPDmi, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPDri, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPDrm, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPDrr, X86_INS_VPERMILPD: vpermilpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPSYmi, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPSYri, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPSYrm, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPSYrr, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPSZ128mbi, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128mbik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128mbikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128mi, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128mik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128mikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128ri, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rm, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rmb, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rmbk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rmbkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rmk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rmkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rr, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rrk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ128rrkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256mbi, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256mbik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256mbikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256mi, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256mik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256mikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256ri, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rm, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rmb, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rmbk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rmbkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rmk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rmkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rr, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rrk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZ256rrkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZmbi, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZmbik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZmbikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZmi, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPSZmik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZmikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZri, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPSZrik, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrikz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrm, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPSZrmb, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrmbk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrmbkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrmk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrmkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrr, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPSZrrk, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSZrrkz, X86_INS_VPERMILPS: vpermilps */ 0, { 0 } }, { /* X86_VPERMILPSmi, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPSri, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMILPSrm, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMILPSrr, X86_INS_VPERMILPS: vpermilps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPDYmi, X86_INS_VPERMPD: vpermpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMPDYri, X86_INS_VPERMPD: vpermpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMPDZ256mbi, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256mbik, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256mbikz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256mi, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256mik, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256mikz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256ri, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rik, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rikz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rm, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rmb, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rmbk, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rmbkz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rmk, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rmkz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rr, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rrk, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZ256rrkz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZmbi, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZmbik, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZmbikz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZmi, X86_INS_VPERMPD: vpermpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMPDZmik, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZmikz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZri, X86_INS_VPERMPD: vpermpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMPDZrik, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrikz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrm, X86_INS_VPERMPD: vpermpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPDZrmb, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrmbk, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrmbkz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrmk, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrmkz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrr, X86_INS_VPERMPD: vpermpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPDZrrk, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPDZrrkz, X86_INS_VPERMPD: vpermpd */ 0, { 0 } }, { /* X86_VPERMPSYrm, X86_INS_VPERMPS: vpermps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPSYrr, X86_INS_VPERMPS: vpermps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPSZ256rm, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rmb, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rmbk, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rmbkz, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rmk, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rmkz, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rr, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rrk, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZ256rrkz, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrm, X86_INS_VPERMPS: vpermps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPSZrmb, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrmbk, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrmbkz, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrmk, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrmkz, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrr, X86_INS_VPERMPS: vpermps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMPSZrrk, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMPSZrrkz, X86_INS_VPERMPS: vpermps */ 0, { 0 } }, { /* X86_VPERMQYmi, X86_INS_VPERMQ: vpermq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMQYri, X86_INS_VPERMQ: vpermq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMQZ256mbi, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256mbik, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256mbikz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256mi, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256mik, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256mikz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256ri, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rik, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rikz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rm, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rmb, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rmbk, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rmbkz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rmk, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rmkz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rr, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rrk, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZ256rrkz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZmbi, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZmbik, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZmbikz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZmi, X86_INS_VPERMQ: vpermq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMQZmik, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZmikz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZri, X86_INS_VPERMQ: vpermq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPERMQZrik, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrikz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrm, X86_INS_VPERMQ: vpermq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMQZrmb, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrmbk, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrmbkz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrmk, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrmkz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrr, X86_INS_VPERMQ: vpermq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMQZrrk, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMQZrrkz, X86_INS_VPERMQ: vpermq */ 0, { 0 } }, { /* X86_VPERMT2B128rm, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B128rmk, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B128rmkz, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B128rr, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B128rrk, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B128rrkz, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B256rm, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B256rmk, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B256rmkz, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B256rr, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B256rrk, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2B256rrkz, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2Brm, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2Brmk, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2Brmkz, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2Brr, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2Brrk, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2Brrkz, X86_INS_VPERMT2B: vpermt2b */ 0, { 0 } }, { /* X86_VPERMT2D128rm, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rmb, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rmbk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rmbkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rmk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rmkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rr, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rrk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D128rrkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rm, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rmb, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rmbk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rmbkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rmk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rmkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rr, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rrk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2D256rrkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2Drm, X86_INS_VPERMT2D: vpermt2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Drmb, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2Drmbk, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2Drmbkz, X86_INS_VPERMT2D: vpermt2d */ 0, { 0 } }, { /* X86_VPERMT2Drmk, X86_INS_VPERMT2D: vpermt2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Drmkz, X86_INS_VPERMT2D: vpermt2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Drr, X86_INS_VPERMT2D: vpermt2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Drrk, X86_INS_VPERMT2D: vpermt2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Drrkz, X86_INS_VPERMT2D: vpermt2d */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PD128rm, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rmb, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rmbk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rmbkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rmk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rmkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rr, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rrk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD128rrkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rm, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rmb, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rmbk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rmbkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rmk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rmkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rr, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rrk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PD256rrkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PDrm, X86_INS_VPERMT2PD: vpermt2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PDrmb, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PDrmbk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PDrmbkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { 0 } }, { /* X86_VPERMT2PDrmk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PDrmkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PDrr, X86_INS_VPERMT2PD: vpermt2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PDrrk, X86_INS_VPERMT2PD: vpermt2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PDrrkz, X86_INS_VPERMT2PD: vpermt2pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PS128rm, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rmb, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rmbk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rmbkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rmk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rmkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rr, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rrk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS128rrkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rm, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rmb, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rmbk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rmbkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rmk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rmkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rr, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rrk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PS256rrkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PSrm, X86_INS_VPERMT2PS: vpermt2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PSrmb, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PSrmbk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PSrmbkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { 0 } }, { /* X86_VPERMT2PSrmk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PSrmkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PSrr, X86_INS_VPERMT2PS: vpermt2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PSrrk, X86_INS_VPERMT2PS: vpermt2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2PSrrkz, X86_INS_VPERMT2PS: vpermt2ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Q128rm, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rmb, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rmbk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rmbkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rmk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rmkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rr, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rrk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q128rrkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rm, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rmb, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rmbk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rmbkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rmk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rmkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rr, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rrk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Q256rrkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Qrm, X86_INS_VPERMT2Q: vpermt2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Qrmb, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Qrmbk, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Qrmbkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { 0 } }, { /* X86_VPERMT2Qrmk, X86_INS_VPERMT2Q: vpermt2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Qrmkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Qrr, X86_INS_VPERMT2Q: vpermt2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Qrrk, X86_INS_VPERMT2Q: vpermt2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2Qrrkz, X86_INS_VPERMT2Q: vpermt2q */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPERMT2W128rm, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W128rmk, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W128rmkz, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W128rr, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W128rrk, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W128rrkz, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W256rm, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W256rmk, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W256rmkz, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W256rr, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W256rrk, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2W256rrkz, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2Wrm, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2Wrmk, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2Wrmkz, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2Wrr, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2Wrrk, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMT2Wrrkz, X86_INS_VPERMT2W: vpermt2w */ 0, { 0 } }, { /* X86_VPERMWZ128rm, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ128rmk, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ128rmkz, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ128rr, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ128rrk, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ128rrkz, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ256rm, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ256rmk, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ256rmkz, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ256rr, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ256rrk, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZ256rrkz, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZrm, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZrmk, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZrmkz, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZrr, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZrrk, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPERMWZrrkz, X86_INS_VPERMW: vpermw */ 0, { 0 } }, { /* X86_VPEXPANDBZ128rm, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ128rmk, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ128rmkz, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ128rr, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ128rrk, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ128rrkz, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ256rm, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ256rmk, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ256rmkz, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ256rr, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ256rrk, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZ256rrkz, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZrm, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZrmk, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZrmkz, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZrr, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZrrk, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDBZrrkz, X86_INS_VPEXPANDB: vpexpandb */ 0, { 0 } }, { /* X86_VPEXPANDDZ128rm, X86_INS_VPEXPANDD: vpexpandd */ 0, { 0 } }, { /* X86_VPEXPANDDZ128rmk, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ128rmkz, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ128rr, X86_INS_VPEXPANDD: vpexpandd */ 0, { 0 } }, { /* X86_VPEXPANDDZ128rrk, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ128rrkz, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ256rm, X86_INS_VPEXPANDD: vpexpandd */ 0, { 0 } }, { /* X86_VPEXPANDDZ256rmk, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ256rmkz, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ256rr, X86_INS_VPEXPANDD: vpexpandd */ 0, { 0 } }, { /* X86_VPEXPANDDZ256rrk, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZ256rrkz, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZrm, X86_INS_VPEXPANDD: vpexpandd */ 0, { 0 } }, { /* X86_VPEXPANDDZrmk, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZrmkz, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZrr, X86_INS_VPEXPANDD: vpexpandd */ 0, { 0 } }, { /* X86_VPEXPANDDZrrk, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDDZrrkz, X86_INS_VPEXPANDD: vpexpandd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ128rm, X86_INS_VPEXPANDQ: vpexpandq */ 0, { 0 } }, { /* X86_VPEXPANDQZ128rmk, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ128rmkz, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ128rr, X86_INS_VPEXPANDQ: vpexpandq */ 0, { 0 } }, { /* X86_VPEXPANDQZ128rrk, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ128rrkz, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ256rm, X86_INS_VPEXPANDQ: vpexpandq */ 0, { 0 } }, { /* X86_VPEXPANDQZ256rmk, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ256rmkz, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ256rr, X86_INS_VPEXPANDQ: vpexpandq */ 0, { 0 } }, { /* X86_VPEXPANDQZ256rrk, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZ256rrkz, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZrm, X86_INS_VPEXPANDQ: vpexpandq */ 0, { 0 } }, { /* X86_VPEXPANDQZrmk, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZrmkz, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZrr, X86_INS_VPEXPANDQ: vpexpandq */ 0, { 0 } }, { /* X86_VPEXPANDQZrrk, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDQZrrkz, X86_INS_VPEXPANDQ: vpexpandq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPEXPANDWZ128rm, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ128rmk, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ128rmkz, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ128rr, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ128rrk, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ128rrkz, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ256rm, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ256rmk, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ256rmkz, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ256rr, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ256rrk, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZ256rrkz, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZrm, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZrmk, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZrmkz, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZrr, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZrrk, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXPANDWZrrkz, X86_INS_VPEXPANDW: vpexpandw */ 0, { 0 } }, { /* X86_VPEXTRBZmr, X86_INS_VPEXTRB: vpextrb */ 0, { 0 } }, { /* X86_VPEXTRBZrr, X86_INS_VPEXTRB: vpextrb */ 0, { 0 } }, { /* X86_VPEXTRBmr, X86_INS_VPEXTRB: vpextrb */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRBrr, X86_INS_VPEXTRB: vpextrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRDZmr, X86_INS_VPEXTRD: vpextrd */ 0, { 0 } }, { /* X86_VPEXTRDZrr, X86_INS_VPEXTRD: vpextrd */ 0, { 0 } }, { /* X86_VPEXTRDmr, X86_INS_VPEXTRD: vpextrd */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRDrr, X86_INS_VPEXTRD: vpextrd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRQZmr, X86_INS_VPEXTRQ: vpextrq */ 0, { 0 } }, { /* X86_VPEXTRQZrr, X86_INS_VPEXTRQ: vpextrq */ 0, { 0 } }, { /* X86_VPEXTRQmr, X86_INS_VPEXTRQ: vpextrq */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRQrr, X86_INS_VPEXTRQ: vpextrq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRWZmr, X86_INS_VPEXTRW: vpextrw */ 0, { 0 } }, { /* X86_VPEXTRWZrr, X86_INS_VPEXTRW: vpextrw */ 0, { 0 } }, { /* X86_VPEXTRWZrr_REV, X86_INS_VPEXTRW: vpextrw */ 0, { 0 } }, { /* X86_VPEXTRWmr, X86_INS_VPEXTRW: vpextrw */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPEXTRWrr, X86_INS_VPEXTRW: vpextrw */ 0, { 0 } }, { /* X86_VPEXTRWrr_REV, X86_INS_VPEXTRW: vpextrw $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPGATHERDDYrm, X86_INS_VPGATHERDD: vpgatherdd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERDDZ128rm, X86_INS_VPGATHERDD: vpgatherdd */ 0, { 0 } }, { /* X86_VPGATHERDDZ256rm, X86_INS_VPGATHERDD: vpgatherdd */ 0, { 0 } }, { /* X86_VPGATHERDDZrm, X86_INS_VPGATHERDD: vpgatherdd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPGATHERDDrm, X86_INS_VPGATHERDD: vpgatherdd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERDQYrm, X86_INS_VPGATHERDQ: vpgatherdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERDQZ128rm, X86_INS_VPGATHERDQ: vpgatherdq */ 0, { 0 } }, { /* X86_VPGATHERDQZ256rm, X86_INS_VPGATHERDQ: vpgatherdq */ 0, { 0 } }, { /* X86_VPGATHERDQZrm, X86_INS_VPGATHERDQ: vpgatherdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPGATHERDQrm, X86_INS_VPGATHERDQ: vpgatherdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERQDYrm, X86_INS_VPGATHERQD: vpgatherqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERQDZ128rm, X86_INS_VPGATHERQD: vpgatherqd */ 0, { 0 } }, { /* X86_VPGATHERQDZ256rm, X86_INS_VPGATHERQD: vpgatherqd */ 0, { 0 } }, { /* X86_VPGATHERQDZrm, X86_INS_VPGATHERQD: vpgatherqd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPGATHERQDrm, X86_INS_VPGATHERQD: vpgatherqd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERQQYrm, X86_INS_VPGATHERQQ: vpgatherqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPGATHERQQZ128rm, X86_INS_VPGATHERQQ: vpgatherqq */ 0, { 0 } }, { /* X86_VPGATHERQQZ256rm, X86_INS_VPGATHERQQ: vpgatherqq */ 0, { 0 } }, { /* X86_VPGATHERQQZrm, X86_INS_VPGATHERQQ: vpgatherqq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPGATHERQQrm, X86_INS_VPGATHERQQ: vpgatherqq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDBDrm, X86_INS_VPHADDBD: vphaddbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDBDrr, X86_INS_VPHADDBD: vphaddbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDBQrm, X86_INS_VPHADDBQ: vphaddbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDBQrr, X86_INS_VPHADDBQ: vphaddbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDBWrm, X86_INS_VPHADDBW: vphaddbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDBWrr, X86_INS_VPHADDBW: vphaddbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDDQrm, X86_INS_VPHADDDQ: vphadddq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDDQrr, X86_INS_VPHADDDQ: vphadddq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDDYrm, X86_INS_VPHADDD: vphaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDDYrr, X86_INS_VPHADDD: vphaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDDrm, X86_INS_VPHADDD: vphaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDDrr, X86_INS_VPHADDD: vphaddd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDSWYrm, X86_INS_VPHADDSW: vphaddsw */ 0, { 0 } }, { /* X86_VPHADDSWYrr, X86_INS_VPHADDSW: vphaddsw */ 0, { 0 } }, { /* X86_VPHADDSWrm, X86_INS_VPHADDSW: vphaddsw */ 0, { 0 } }, { /* X86_VPHADDSWrr, X86_INS_VPHADDSW: vphaddsw */ 0, { 0 } }, { /* X86_VPHADDUBDrm, X86_INS_VPHADDUBD: vphaddubd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUBDrr, X86_INS_VPHADDUBD: vphaddubd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUBQrm, X86_INS_VPHADDUBQ: vphaddubq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUBQrr, X86_INS_VPHADDUBQ: vphaddubq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUBWrm, X86_INS_VPHADDUBW: vphaddubw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUBWrr, X86_INS_VPHADDUBW: vphaddubw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUDQrm, X86_INS_VPHADDUDQ: vphaddudq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUDQrr, X86_INS_VPHADDUDQ: vphaddudq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUWDrm, X86_INS_VPHADDUWD: vphadduwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUWDrr, X86_INS_VPHADDUWD: vphadduwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUWQrm, X86_INS_VPHADDUWQ: vphadduwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDUWQrr, X86_INS_VPHADDUWQ: vphadduwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDWDrm, X86_INS_VPHADDWD: vphaddwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDWDrr, X86_INS_VPHADDWD: vphaddwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDWQrm, X86_INS_VPHADDWQ: vphaddwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDWQrr, X86_INS_VPHADDWQ: vphaddwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHADDWYrm, X86_INS_VPHADDW: vphaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDWYrr, X86_INS_VPHADDW: vphaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDWrm, X86_INS_VPHADDW: vphaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHADDWrr, X86_INS_VPHADDW: vphaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHMINPOSUWrm, X86_INS_VPHMINPOSUW: vphminposuw */ 0, { 0 } }, { /* X86_VPHMINPOSUWrr, X86_INS_VPHMINPOSUW: vphminposuw */ 0, { 0 } }, { /* X86_VPHSUBBWrm, X86_INS_VPHSUBBW: vphsubbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHSUBBWrr, X86_INS_VPHSUBBW: vphsubbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHSUBDQrm, X86_INS_VPHSUBDQ: vphsubdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHSUBDQrr, X86_INS_VPHSUBDQ: vphsubdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHSUBDYrm, X86_INS_VPHSUBD: vphsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBDYrr, X86_INS_VPHSUBD: vphsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBDrm, X86_INS_VPHSUBD: vphsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBDrr, X86_INS_VPHSUBD: vphsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBSWYrm, X86_INS_VPHSUBSW: vphsubsw */ 0, { 0 } }, { /* X86_VPHSUBSWYrr, X86_INS_VPHSUBSW: vphsubsw */ 0, { 0 } }, { /* X86_VPHSUBSWrm, X86_INS_VPHSUBSW: vphsubsw */ 0, { 0 } }, { /* X86_VPHSUBSWrr, X86_INS_VPHSUBSW: vphsubsw */ 0, { 0 } }, { /* X86_VPHSUBWDrm, X86_INS_VPHSUBWD: vphsubwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHSUBWDrr, X86_INS_VPHSUBWD: vphsubwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPHSUBWYrm, X86_INS_VPHSUBW: vphsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBWYrr, X86_INS_VPHSUBW: vphsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBWrm, X86_INS_VPHSUBW: vphsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPHSUBWrr, X86_INS_VPHSUBW: vphsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPINSRBZrm, X86_INS_VPINSRB: vpinsrb */ 0, { 0 } }, { /* X86_VPINSRBZrr, X86_INS_VPINSRB: vpinsrb */ 0, { 0 } }, { /* X86_VPINSRBrm, X86_INS_VPINSRB: vpinsrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPINSRBrr, X86_INS_VPINSRB: vpinsrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPINSRDZrm, X86_INS_VPINSRD: vpinsrd */ 0, { 0 } }, { /* X86_VPINSRDZrr, X86_INS_VPINSRD: vpinsrd */ 0, { 0 } }, { /* X86_VPINSRDrm, X86_INS_VPINSRD: vpinsrd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPINSRDrr, X86_INS_VPINSRD: vpinsrd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPINSRQZrm, X86_INS_VPINSRQ: vpinsrq */ 0, { 0 } }, { /* X86_VPINSRQZrr, X86_INS_VPINSRQ: vpinsrq */ 0, { 0 } }, { /* X86_VPINSRQrm, X86_INS_VPINSRQ: vpinsrq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPINSRQrr, X86_INS_VPINSRQ: vpinsrq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPINSRWZrm, X86_INS_VPINSRW: vpinsrw */ 0, { 0 } }, { /* X86_VPINSRWZrr, X86_INS_VPINSRW: vpinsrw */ 0, { 0 } }, { /* X86_VPINSRWrm, X86_INS_VPINSRW: vpinsrw */ 0, { 0 } }, { /* X86_VPINSRWrr, X86_INS_VPINSRW: vpinsrw */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rm, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rmb, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rmbk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rmbkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rmk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rmkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rr, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rrk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ128rrkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rm, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rmb, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rmbk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rmbkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rmk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rmkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rr, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rrk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZ256rrkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrm, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrmb, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrmbk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrmbkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrmk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrmkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrr, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrrk, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTDZrrkz, X86_INS_VPLZCNTD: vplzcntd */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rm, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rmb, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rmbk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rmbkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rmk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rmkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rr, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rrk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ128rrkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rm, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rmb, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rmbk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rmbkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rmk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rmkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rr, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rrk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZ256rrkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrm, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrmb, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrmbk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrmbkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrmk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrmkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrr, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrrk, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPLZCNTQZrrkz, X86_INS_VPLZCNTQ: vplzcntq */ 0, { 0 } }, { /* X86_VPMACSDDrm, X86_INS_VPMACSDD: vpmacsdd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSDDrr, X86_INS_VPMACSDD: vpmacsdd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSDQHrm, X86_INS_VPMACSDQH: vpmacsdqh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSDQHrr, X86_INS_VPMACSDQH: vpmacsdqh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSDQLrm, X86_INS_VPMACSDQL: vpmacsdql */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSDQLrr, X86_INS_VPMACSDQL: vpmacsdql */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSDDrm, X86_INS_VPMACSSDD: vpmacssdd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSDDrr, X86_INS_VPMACSSDD: vpmacssdd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSDQHrm, X86_INS_VPMACSSDQH: vpmacssdqh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSDQHrr, X86_INS_VPMACSSDQH: vpmacssdqh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSDQLrm, X86_INS_VPMACSSDQL: vpmacssdql */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSDQLrr, X86_INS_VPMACSSDQL: vpmacssdql */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSWDrm, X86_INS_VPMACSSWD: vpmacsswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSWDrr, X86_INS_VPMACSSWD: vpmacsswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSWWrm, X86_INS_VPMACSSWW: vpmacssww */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSSWWrr, X86_INS_VPMACSSWW: vpmacssww */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSWDrm, X86_INS_VPMACSWD: vpmacswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSWDrr, X86_INS_VPMACSWD: vpmacswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSWWrm, X86_INS_VPMACSWW: vpmacsww */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMACSWWrr, X86_INS_VPMACSWW: vpmacsww */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADCSSWDrm, X86_INS_VPMADCSSWD: vpmadcsswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADCSSWDrr, X86_INS_VPMADCSSWD: vpmadcsswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADCSWDrm, X86_INS_VPMADCSWD: vpmadcswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADCSWDrr, X86_INS_VPMADCSWD: vpmadcswd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADD52HUQZ128m, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128mb, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128mbk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128mbkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128mk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128mkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128r, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128rk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ128rkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256m, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256mb, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256mbk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256mbkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256mk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256mkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256r, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256rk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZ256rkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZm, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZmb, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZmbk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZmbkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZmk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZmkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZr, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZrk, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52HUQZrkz, X86_INS_VPMADD52HUQ: vpmadd52huq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128m, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128mb, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128mbk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128mbkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128mk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128mkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128r, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128rk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ128rkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256m, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256mb, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256mbk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256mbkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256mk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256mkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256r, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256rk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZ256rkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZm, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZmb, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZmbk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZmbkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZmk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZmkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZr, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZrk, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADD52LUQZrkz, X86_INS_VPMADD52LUQ: vpmadd52luq */ 0, { 0 } }, { /* X86_VPMADDUBSWYrm, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWYrr, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ128rm, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ128rmk, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ128rmkz, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ128rr, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ128rrk, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ128rrkz, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ256rm, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ256rmk, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ256rmkz, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ256rr, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ256rrk, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZ256rrkz, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZrm, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZrmk, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZrmkz, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZrr, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZrrk, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWZrrkz, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWrm, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDUBSWrr, X86_INS_VPMADDUBSW: vpmaddubsw */ 0, { 0 } }, { /* X86_VPMADDWDYrm, X86_INS_VPMADDWD: vpmaddwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADDWDYrr, X86_INS_VPMADDWD: vpmaddwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADDWDZ128rm, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ128rmk, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ128rmkz, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ128rr, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ128rrk, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ128rrkz, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ256rm, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ256rmk, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ256rmkz, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ256rr, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ256rrk, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZ256rrkz, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZrm, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZrmk, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZrmkz, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZrr, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZrrk, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDZrrkz, X86_INS_VPMADDWD: vpmaddwd */ 0, { 0 } }, { /* X86_VPMADDWDrm, X86_INS_VPMADDWD: vpmaddwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMADDWDrr, X86_INS_VPMADDWD: vpmaddwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVDYmr, X86_INS_VPMASKMOVD: vpmaskmovd */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVDYrm, X86_INS_VPMASKMOVD: vpmaskmovd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVDmr, X86_INS_VPMASKMOVD: vpmaskmovd */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVDrm, X86_INS_VPMASKMOVD: vpmaskmovd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVQYmr, X86_INS_VPMASKMOVQ: vpmaskmovq */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVQYrm, X86_INS_VPMASKMOVQ: vpmaskmovq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVQmr, X86_INS_VPMASKMOVQ: vpmaskmovq */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMASKMOVQrm, X86_INS_VPMASKMOVQ: vpmaskmovq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBYrm, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBYrr, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ128rm, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ128rmk, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ128rmkz, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ128rr, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ128rrk, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ128rrkz, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ256rm, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ256rmk, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ256rmkz, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ256rr, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ256rrk, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZ256rrkz, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZrm, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZrmk, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZrmkz, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZrr, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZrrk, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBZrrkz, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBrm, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSBrr, X86_INS_VPMAXSB: vpmaxsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDYrm, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDYrr, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rm, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rmb, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rmbk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rmbkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rmk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rmkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rr, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rrk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ128rrkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rm, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rmb, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rmbk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rmbkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rmk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rmkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rr, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rrk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZ256rrkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrm, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrmb, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrmbk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrmbkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrmk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrmkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrr, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrrk, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDZrrkz, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDrm, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSDrr, X86_INS_VPMAXSD: vpmaxsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rm, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rmb, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rmbk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rmbkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rmk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rmkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rr, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rrk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ128rrkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rm, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rmb, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rmbk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rmbkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rmk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rmkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rr, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rrk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZ256rrkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrm, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrmb, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrmbk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrmbkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrmk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrmkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrr, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrrk, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSQZrrkz, X86_INS_VPMAXSQ: vpmaxsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWYrm, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWYrr, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ128rm, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ128rmk, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ128rmkz, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ128rr, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ128rrk, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ128rrkz, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ256rm, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ256rmk, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ256rmkz, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ256rr, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ256rrk, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZ256rrkz, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZrm, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZrmk, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZrmkz, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZrr, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZrrk, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWZrrkz, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWrm, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXSWrr, X86_INS_VPMAXSW: vpmaxsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBYrm, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBYrr, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ128rm, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ128rmk, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ128rmkz, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ128rr, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ128rrk, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ128rrkz, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ256rm, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ256rmk, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ256rmkz, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ256rr, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ256rrk, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZ256rrkz, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZrm, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZrmk, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZrmkz, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZrr, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZrrk, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBZrrkz, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBrm, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUBrr, X86_INS_VPMAXUB: vpmaxub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDYrm, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDYrr, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rm, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rmb, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rmbk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rmbkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rmk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rmkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rr, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rrk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ128rrkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rm, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rmb, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rmbk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rmbkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rmk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rmkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rr, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rrk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZ256rrkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrm, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrmb, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrmbk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrmbkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrmk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrmkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrr, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrrk, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDZrrkz, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDrm, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUDrr, X86_INS_VPMAXUD: vpmaxud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rm, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rmb, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rmbk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rmbkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rmk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rmkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rr, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rrk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ128rrkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rm, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rmb, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rmbk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rmbkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rmk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rmkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rr, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rrk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZ256rrkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrm, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrmb, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrmbk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrmbkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrmk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrmkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrr, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrrk, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUQZrrkz, X86_INS_VPMAXUQ: vpmaxuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWYrm, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWYrr, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ128rm, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ128rmk, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ128rmkz, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ128rr, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ128rrk, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ128rrkz, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ256rm, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ256rmk, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ256rmkz, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ256rr, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ256rrk, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZ256rrkz, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZrm, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZrmk, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZrmkz, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZrr, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZrrk, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWZrrkz, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWrm, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMAXUWrr, X86_INS_VPMAXUW: vpmaxuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBYrm, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBYrr, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ128rm, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ128rmk, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ128rmkz, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ128rr, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ128rrk, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ128rrkz, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ256rm, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ256rmk, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ256rmkz, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ256rr, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ256rrk, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZ256rrkz, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZrm, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZrmk, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZrmkz, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZrr, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZrrk, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBZrrkz, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBrm, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSBrr, X86_INS_VPMINSB: vpminsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDYrm, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDYrr, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rm, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rmb, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rmbk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rmbkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rmk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rmkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rr, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rrk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ128rrkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rm, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rmb, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rmbk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rmbkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rmk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rmkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rr, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rrk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZ256rrkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrm, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrmb, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrmbk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrmbkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrmk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrmkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrr, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrrk, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDZrrkz, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDrm, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSDrr, X86_INS_VPMINSD: vpminsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rm, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rmb, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rmbk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rmbkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rmk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rmkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rr, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rrk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ128rrkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rm, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rmb, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rmbk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rmbkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rmk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rmkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rr, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rrk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZ256rrkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrm, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrmb, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrmbk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrmbkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrmk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrmkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrr, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrrk, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSQZrrkz, X86_INS_VPMINSQ: vpminsq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWYrm, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWYrr, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ128rm, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ128rmk, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ128rmkz, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ128rr, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ128rrk, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ128rrkz, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ256rm, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ256rmk, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ256rmkz, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ256rr, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ256rrk, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZ256rrkz, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZrm, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZrmk, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZrmkz, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZrr, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZrrk, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWZrrkz, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWrm, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINSWrr, X86_INS_VPMINSW: vpminsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBYrm, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBYrr, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ128rm, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ128rmk, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ128rmkz, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ128rr, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ128rrk, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ128rrkz, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ256rm, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ256rmk, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ256rmkz, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ256rr, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ256rrk, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZ256rrkz, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZrm, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZrmk, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZrmkz, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZrr, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZrrk, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBZrrkz, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBrm, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUBrr, X86_INS_VPMINUB: vpminub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDYrm, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDYrr, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rm, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rmb, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rmbk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rmbkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rmk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rmkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rr, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rrk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ128rrkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rm, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rmb, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rmbk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rmbkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rmk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rmkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rr, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rrk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZ256rrkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrm, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrmb, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrmbk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrmbkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrmk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrmkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrr, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrrk, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDZrrkz, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDrm, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUDrr, X86_INS_VPMINUD: vpminud */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rm, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rmb, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rmbk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rmbkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rmk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rmkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rr, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rrk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ128rrkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rm, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rmb, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rmbk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rmbkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rmk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rmkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rr, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rrk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZ256rrkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrm, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrmb, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrmbk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrmbkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrmk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrmkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrr, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrrk, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUQZrrkz, X86_INS_VPMINUQ: vpminuq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWYrm, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWYrr, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ128rm, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ128rmk, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ128rmkz, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ128rr, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ128rrk, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ128rrkz, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ256rm, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ256rmk, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ256rmkz, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ256rr, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ256rrk, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZ256rrkz, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZrm, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZrmk, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZrmkz, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZrr, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZrrk, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWZrrkz, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWrm, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMINUWrr, X86_INS_VPMINUW: vpminuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMOVB2MZ128rr, X86_INS_VPMOVB2M: vpmovb2m */ 0, { 0 } }, { /* X86_VPMOVB2MZ256rr, X86_INS_VPMOVB2M: vpmovb2m */ 0, { 0 } }, { /* X86_VPMOVB2MZrr, X86_INS_VPMOVB2M: vpmovb2m */ 0, { 0 } }, { /* X86_VPMOVD2MZ128rr, X86_INS_VPMOVD2M: vpmovd2m */ 0, { 0 } }, { /* X86_VPMOVD2MZ256rr, X86_INS_VPMOVD2M: vpmovd2m */ 0, { 0 } }, { /* X86_VPMOVD2MZrr, X86_INS_VPMOVD2M: vpmovd2m */ 0, { 0 } }, { /* X86_VPMOVDBZ128mr, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ128mrk, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ128rr, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ128rrk, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ128rrkz, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ256mr, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ256mrk, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ256rr, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ256rrk, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZ256rrkz, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZmr, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZmrk, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZrr, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZrrk, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDBZrrkz, X86_INS_VPMOVDB: vpmovdb */ 0, { 0 } }, { /* X86_VPMOVDWZ128mr, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ128mrk, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ128rr, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ128rrk, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ128rrkz, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ256mr, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ256mrk, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ256rr, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ256rrk, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZ256rrkz, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZmr, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZmrk, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZrr, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZrrk, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVDWZrrkz, X86_INS_VPMOVDW: vpmovdw */ 0, { 0 } }, { /* X86_VPMOVM2BZ128rr, X86_INS_VPMOVM2B: vpmovm2b */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2BZ256rr, X86_INS_VPMOVM2B: vpmovm2b */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2BZrr, X86_INS_VPMOVM2B: vpmovm2b */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2DZ128rr, X86_INS_VPMOVM2D: vpmovm2d */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2DZ256rr, X86_INS_VPMOVM2D: vpmovm2d */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2DZrr, X86_INS_VPMOVM2D: vpmovm2d */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2QZ128rr, X86_INS_VPMOVM2Q: vpmovm2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2QZ256rr, X86_INS_VPMOVM2Q: vpmovm2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2QZrr, X86_INS_VPMOVM2Q: vpmovm2q */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2WZ128rr, X86_INS_VPMOVM2W: vpmovm2w */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2WZ256rr, X86_INS_VPMOVM2W: vpmovm2w */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVM2WZrr, X86_INS_VPMOVM2W: vpmovm2w */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVMSKBYrr, X86_INS_VPMOVMSKB: vpmovmskb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVMSKBrr, X86_INS_VPMOVMSKB: vpmovmskb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVQ2MZ128rr, X86_INS_VPMOVQ2M: vpmovq2m */ 0, { 0 } }, { /* X86_VPMOVQ2MZ256rr, X86_INS_VPMOVQ2M: vpmovq2m */ 0, { 0 } }, { /* X86_VPMOVQ2MZrr, X86_INS_VPMOVQ2M: vpmovq2m */ 0, { 0 } }, { /* X86_VPMOVQBZ128mr, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ128mrk, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ128rr, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ128rrk, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ128rrkz, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ256mr, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ256mrk, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ256rr, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ256rrk, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZ256rrkz, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZmr, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZmrk, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZrr, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZrrk, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQBZrrkz, X86_INS_VPMOVQB: vpmovqb */ 0, { 0 } }, { /* X86_VPMOVQDZ128mr, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ128mrk, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ128rr, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ128rrk, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ128rrkz, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ256mr, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ256mrk, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ256rr, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ256rrk, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZ256rrkz, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZmr, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZmrk, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZrr, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZrrk, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQDZrrkz, X86_INS_VPMOVQD: vpmovqd */ 0, { 0 } }, { /* X86_VPMOVQWZ128mr, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ128mrk, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ128rr, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ128rrk, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ128rrkz, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ256mr, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ256mrk, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ256rr, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ256rrk, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZ256rrkz, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZmr, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZmrk, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZrr, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZrrk, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVQWZrrkz, X86_INS_VPMOVQW: vpmovqw */ 0, { 0 } }, { /* X86_VPMOVSDBZ128mr, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ128mrk, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ128rr, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ128rrk, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ128rrkz, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ256mr, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ256mrk, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ256rr, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ256rrk, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZ256rrkz, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZmr, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZmrk, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZrr, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZrrk, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDBZrrkz, X86_INS_VPMOVSDB: vpmovsdb */ 0, { 0 } }, { /* X86_VPMOVSDWZ128mr, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ128mrk, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ128rr, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ128rrk, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ128rrkz, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ256mr, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ256mrk, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ256rr, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ256rrk, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZ256rrkz, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZmr, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZmrk, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZrr, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZrrk, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSDWZrrkz, X86_INS_VPMOVSDW: vpmovsdw */ 0, { 0 } }, { /* X86_VPMOVSQBZ128mr, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ128mrk, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ128rr, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ128rrk, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ128rrkz, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ256mr, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ256mrk, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ256rr, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ256rrk, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZ256rrkz, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZmr, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZmrk, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZrr, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZrrk, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQBZrrkz, X86_INS_VPMOVSQB: vpmovsqb */ 0, { 0 } }, { /* X86_VPMOVSQDZ128mr, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ128mrk, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ128rr, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ128rrk, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ128rrkz, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ256mr, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ256mrk, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ256rr, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ256rrk, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZ256rrkz, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZmr, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZmrk, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZrr, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZrrk, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQDZrrkz, X86_INS_VPMOVSQD: vpmovsqd */ 0, { 0 } }, { /* X86_VPMOVSQWZ128mr, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ128mrk, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ128rr, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ128rrk, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ128rrkz, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ256mr, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ256mrk, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ256rr, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ256rrk, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZ256rrkz, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZmr, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZmrk, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZrr, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZrrk, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSQWZrrkz, X86_INS_VPMOVSQW: vpmovsqw */ 0, { 0 } }, { /* X86_VPMOVSWBZ128mr, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ128mrk, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ128rr, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ128rrk, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ128rrkz, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ256mr, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ256mrk, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ256rr, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ256rrk, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZ256rrkz, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZmr, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZmrk, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZrr, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZrrk, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSWBZrrkz, X86_INS_VPMOVSWB: vpmovswb */ 0, { 0 } }, { /* X86_VPMOVSXBDYrm, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDYrr, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDZ128rm, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ128rmk, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ128rmkz, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ128rr, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ128rrk, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ128rrkz, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ256rm, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ256rmk, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ256rmkz, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ256rr, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ256rrk, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZ256rrkz, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { 0 } }, { /* X86_VPMOVSXBDZrm, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDZrmk, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDZrmkz, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDZrr, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDZrrk, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDZrrkz, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDrm, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBDrr, X86_INS_VPMOVSXBD: vpmovsxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQYrm, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQYrr, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQZ128rm, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ128rmk, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ128rmkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ128rr, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ128rrk, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ128rrkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ256rm, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ256rmk, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ256rmkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ256rr, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ256rrk, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZ256rrkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { 0 } }, { /* X86_VPMOVSXBQZrm, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQZrmk, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQZrmkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQZrr, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQZrrk, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQZrrkz, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQrm, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBQrr, X86_INS_VPMOVSXBQ: vpmovsxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBWYrm, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBWYrr, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBWZ128rm, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ128rmk, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ128rmkz, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ128rr, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ128rrk, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ128rrkz, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ256rm, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ256rmk, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ256rmkz, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ256rr, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ256rrk, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZ256rrkz, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZrm, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZrmk, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZrmkz, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZrr, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZrrk, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWZrrkz, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { 0 } }, { /* X86_VPMOVSXBWrm, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXBWrr, X86_INS_VPMOVSXBW: vpmovsxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQYrm, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQYrr, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQZ128rm, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ128rmk, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ128rmkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ128rr, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ128rrk, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ128rrkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ256rm, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ256rmk, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ256rmkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ256rr, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ256rrk, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZ256rrkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { 0 } }, { /* X86_VPMOVSXDQZrm, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQZrmk, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQZrmkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQZrr, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQZrrk, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQZrrkz, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQrm, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXDQrr, X86_INS_VPMOVSXDQ: vpmovsxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDYrm, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDYrr, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDZ128rm, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ128rmk, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ128rmkz, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ128rr, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ128rrk, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ128rrkz, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ256rm, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ256rmk, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ256rmkz, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ256rr, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ256rrk, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZ256rrkz, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { 0 } }, { /* X86_VPMOVSXWDZrm, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDZrmk, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDZrmkz, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDZrr, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDZrrk, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDZrrkz, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDrm, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWDrr, X86_INS_VPMOVSXWD: vpmovsxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQYrm, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQYrr, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQZ128rm, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ128rmk, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ128rmkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ128rr, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ128rrk, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ128rrkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ256rm, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ256rmk, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ256rmkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ256rr, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ256rrk, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZ256rrkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { 0 } }, { /* X86_VPMOVSXWQZrm, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQZrmk, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQZrmkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQZrr, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQZrrk, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQZrrkz, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQrm, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVSXWQrr, X86_INS_VPMOVSXWQ: vpmovsxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVUSDBZ128mr, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ128mrk, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ128rr, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ128rrk, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ128rrkz, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ256mr, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ256mrk, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ256rr, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ256rrk, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZ256rrkz, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZmr, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZmrk, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZrr, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZrrk, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDBZrrkz, X86_INS_VPMOVUSDB: vpmovusdb */ 0, { 0 } }, { /* X86_VPMOVUSDWZ128mr, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ128mrk, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ128rr, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ128rrk, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ128rrkz, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ256mr, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ256mrk, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ256rr, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ256rrk, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZ256rrkz, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZmr, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZmrk, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZrr, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZrrk, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSDWZrrkz, X86_INS_VPMOVUSDW: vpmovusdw */ 0, { 0 } }, { /* X86_VPMOVUSQBZ128mr, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ128mrk, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ128rr, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ128rrk, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ128rrkz, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ256mr, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ256mrk, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ256rr, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ256rrk, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZ256rrkz, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZmr, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZmrk, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZrr, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZrrk, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQBZrrkz, X86_INS_VPMOVUSQB: vpmovusqb */ 0, { 0 } }, { /* X86_VPMOVUSQDZ128mr, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ128mrk, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ128rr, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ128rrk, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ128rrkz, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ256mr, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ256mrk, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ256rr, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ256rrk, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZ256rrkz, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZmr, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZmrk, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZrr, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZrrk, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQDZrrkz, X86_INS_VPMOVUSQD: vpmovusqd */ 0, { 0 } }, { /* X86_VPMOVUSQWZ128mr, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ128mrk, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ128rr, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ128rrk, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ128rrkz, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ256mr, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ256mrk, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ256rr, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ256rrk, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZ256rrkz, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZmr, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZmrk, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZrr, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZrrk, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSQWZrrkz, X86_INS_VPMOVUSQW: vpmovusqw */ 0, { 0 } }, { /* X86_VPMOVUSWBZ128mr, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ128mrk, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ128rr, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ128rrk, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ128rrkz, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ256mr, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ256mrk, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ256rr, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ256rrk, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZ256rrkz, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZmr, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZmrk, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZrr, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZrrk, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVUSWBZrrkz, X86_INS_VPMOVUSWB: vpmovuswb */ 0, { 0 } }, { /* X86_VPMOVW2MZ128rr, X86_INS_VPMOVW2M: vpmovw2m */ 0, { 0 } }, { /* X86_VPMOVW2MZ256rr, X86_INS_VPMOVW2M: vpmovw2m */ 0, { 0 } }, { /* X86_VPMOVW2MZrr, X86_INS_VPMOVW2M: vpmovw2m */ 0, { 0 } }, { /* X86_VPMOVWBZ128mr, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ128mrk, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ128rr, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ128rrk, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ128rrkz, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ256mr, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ256mrk, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ256rr, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ256rrk, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZ256rrkz, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZmr, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZmrk, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZrr, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZrrk, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVWBZrrkz, X86_INS_VPMOVWB: vpmovwb */ 0, { 0 } }, { /* X86_VPMOVZXBDYrm, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDYrr, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDZ128rm, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ128rmk, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ128rmkz, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ128rr, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ128rrk, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ128rrkz, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ256rm, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ256rmk, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ256rmkz, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ256rr, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ256rrk, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZ256rrkz, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { 0 } }, { /* X86_VPMOVZXBDZrm, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDZrmk, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDZrmkz, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDZrr, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDZrrk, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDZrrkz, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDrm, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBDrr, X86_INS_VPMOVZXBD: vpmovzxbd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQYrm, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQYrr, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQZ128rm, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ128rmk, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ128rmkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ128rr, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ128rrk, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ128rrkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ256rm, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ256rmk, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ256rmkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ256rr, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ256rrk, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZ256rrkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { 0 } }, { /* X86_VPMOVZXBQZrm, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQZrmk, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQZrmkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQZrr, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQZrrk, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQZrrkz, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQrm, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBQrr, X86_INS_VPMOVZXBQ: vpmovzxbq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBWYrm, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBWYrr, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBWZ128rm, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ128rmk, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ128rmkz, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ128rr, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ128rrk, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ128rrkz, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ256rm, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ256rmk, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ256rmkz, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ256rr, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ256rrk, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZ256rrkz, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZrm, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZrmk, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZrmkz, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZrr, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZrrk, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWZrrkz, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { 0 } }, { /* X86_VPMOVZXBWrm, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXBWrr, X86_INS_VPMOVZXBW: vpmovzxbw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQYrm, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQYrr, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQZ128rm, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ128rmk, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ128rmkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ128rr, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ128rrk, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ128rrkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ256rm, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ256rmk, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ256rmkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ256rr, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ256rrk, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZ256rrkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { 0 } }, { /* X86_VPMOVZXDQZrm, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQZrmk, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQZrmkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQZrr, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQZrrk, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQZrrkz, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQrm, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXDQrr, X86_INS_VPMOVZXDQ: vpmovzxdq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDYrm, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDYrr, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDZ128rm, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ128rmk, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ128rmkz, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ128rr, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ128rrk, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ128rrkz, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ256rm, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ256rmk, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ256rmkz, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ256rr, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ256rrk, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZ256rrkz, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { 0 } }, { /* X86_VPMOVZXWDZrm, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDZrmk, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDZrmkz, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDZrr, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDZrrk, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDZrrkz, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDrm, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWDrr, X86_INS_VPMOVZXWD: vpmovzxwd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQYrm, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQYrr, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQZ128rm, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ128rmk, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ128rmkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ128rr, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ128rrk, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ128rrkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ256rm, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ256rmk, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ256rmkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ256rr, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ256rrk, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZ256rrkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { 0 } }, { /* X86_VPMOVZXWQZrm, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQZrmk, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQZrmkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQZrr, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQZrrk, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQZrrkz, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQrm, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMOVZXWQrr, X86_INS_VPMOVZXWQ: vpmovzxwq */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VPMULDQYrm, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQYrr, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZ128rm, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rmb, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rmbk, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rmbkz, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rmk, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rmkz, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rr, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rrk, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ128rrkz, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rm, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rmb, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rmbk, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rmbkz, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rmk, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rmkz, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rr, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rrk, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZ256rrkz, X86_INS_VPMULDQ: vpmuldq */ 0, { 0 } }, { /* X86_VPMULDQZrm, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrmb, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrmbk, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrmbkz, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrmk, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrmkz, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrr, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrrk, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQZrrkz, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQrm, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULDQrr, X86_INS_VPMULDQ: vpmuldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHRSWYrm, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWYrr, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ128rm, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ128rmk, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ128rmkz, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ128rr, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ128rrk, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ128rrkz, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ256rm, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ256rmk, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ256rmkz, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ256rr, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ256rrk, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZ256rrkz, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZrm, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZrmk, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZrmkz, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZrr, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZrrk, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWZrrkz, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWrm, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHRSWrr, X86_INS_VPMULHRSW: vpmulhrsw */ 0, { 0 } }, { /* X86_VPMULHUWYrm, X86_INS_VPMULHUW: vpmulhuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHUWYrr, X86_INS_VPMULHUW: vpmulhuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHUWZ128rm, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ128rmk, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ128rmkz, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ128rr, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ128rrk, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ128rrkz, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ256rm, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ256rmk, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ256rmkz, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ256rr, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ256rrk, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZ256rrkz, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZrm, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZrmk, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZrmkz, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZrr, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZrrk, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWZrrkz, X86_INS_VPMULHUW: vpmulhuw */ 0, { 0 } }, { /* X86_VPMULHUWrm, X86_INS_VPMULHUW: vpmulhuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHUWrr, X86_INS_VPMULHUW: vpmulhuw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHWYrm, X86_INS_VPMULHW: vpmulhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHWYrr, X86_INS_VPMULHW: vpmulhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHWZ128rm, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ128rmk, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ128rmkz, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ128rr, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ128rrk, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ128rrkz, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ256rm, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ256rmk, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ256rmkz, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ256rr, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ256rrk, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZ256rrkz, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZrm, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZrmk, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZrmkz, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZrr, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZrrk, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWZrrkz, X86_INS_VPMULHW: vpmulhw */ 0, { 0 } }, { /* X86_VPMULHWrm, X86_INS_VPMULHW: vpmulhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULHWrr, X86_INS_VPMULHW: vpmulhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDYrm, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDYrr, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rm, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rmb, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rmbk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rmbkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rmk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rmkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rr, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rrk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ128rrkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rm, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rmb, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rmbk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rmbkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rmk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rmkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rr, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rrk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZ256rrkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrm, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrmb, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrmbk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrmbkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrmk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrmkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrr, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrrk, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDZrrkz, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDrm, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLDrr, X86_INS_VPMULLD: vpmulld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rm, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rmb, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rmbk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rmbkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rmk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rmkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rr, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rrk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ128rrkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rm, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rmb, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rmbk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rmbkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rmk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rmkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rr, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rrk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZ256rrkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrm, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrmb, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrmbk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrmbkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrmk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrmkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrr, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrrk, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLQZrrkz, X86_INS_VPMULLQ: vpmullq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWYrm, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWYrr, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ128rm, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ128rmk, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ128rmkz, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ128rr, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ128rrk, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ128rrkz, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ256rm, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ256rmk, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ256rmkz, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ256rr, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ256rrk, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZ256rrkz, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZrm, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZrmk, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZrmkz, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZrr, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZrrk, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWZrrkz, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWrm, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULLWrr, X86_INS_VPMULLW: vpmullw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULTISHIFTQBZ128rm, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rmb, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rmbk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rmbkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rmk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rmkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rr, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rrk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ128rrkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rm, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rmb, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rmbk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rmbkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rmk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rmkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rr, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rrk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZ256rrkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrm, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrmb, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrmbk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrmbkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrmk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrmkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrr, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrrk, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULTISHIFTQBZrrkz, X86_INS_VPMULTISHIFTQB: vpmultishiftqb */ 0, { 0 } }, { /* X86_VPMULUDQYrm, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQYrr, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZ128rm, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rmb, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rmbk, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rmbkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rmk, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rmkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rr, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rrk, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ128rrkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rm, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rmb, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rmbk, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rmbkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rmk, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rmkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rr, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rrk, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZ256rrkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { 0 } }, { /* X86_VPMULUDQZrm, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrmb, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrmbk, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrmbkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrmk, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrmkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrr, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrrk, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQZrrkz, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQrm, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPMULUDQrr, X86_INS_VPMULUDQ: vpmuludq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPOPCNTBZ128rm, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ128rmk, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ128rmkz, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ128rr, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ128rrk, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ128rrkz, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ256rm, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ256rmk, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ256rmkz, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ256rr, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ256rrk, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZ256rrkz, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZrm, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZrmk, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZrmkz, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZrr, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZrrk, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTBZrrkz, X86_INS_VPOPCNTB: vpopcntb */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rm, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rmb, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rmbk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rmbkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rmk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rmkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rr, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rrk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ128rrkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rm, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rmb, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rmbk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rmbkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rmk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rmkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rr, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rrk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZ256rrkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrm, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrmb, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrmbk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrmbkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrmk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrmkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrr, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrrk, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTDZrrkz, X86_INS_VPOPCNTD: vpopcntd */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rm, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rmb, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rmbk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rmbkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rmk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rmkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rr, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rrk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ128rrkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rm, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rmb, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rmbk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rmbkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rmk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rmkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rr, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rrk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZ256rrkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrm, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrmb, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrmbk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrmbkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrmk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrmkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrr, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrrk, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTQZrrkz, X86_INS_VPOPCNTQ: vpopcntq */ 0, { 0 } }, { /* X86_VPOPCNTWZ128rm, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ128rmk, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ128rmkz, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ128rr, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ128rrk, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ128rrkz, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ256rm, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ256rmk, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ256rmkz, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ256rr, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ256rrk, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZ256rrkz, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZrm, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZrmk, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZrmkz, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZrr, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZrrk, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPOPCNTWZrrkz, X86_INS_VPOPCNTW: vpopcntw */ 0, { 0 } }, { /* X86_VPORDZ128rm, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rmb, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rmbk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rmbkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rmk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rmkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rr, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rrk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ128rrkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rm, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rmb, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rmbk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rmbkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rmk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rmkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rr, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rrk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZ256rrkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrm, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrmb, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrmbk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrmbkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrmk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrmkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrr, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrrk, X86_INS_VPORD: vpord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORDZrrkz, X86_INS_VPORD: vpord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rm, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rmb, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rmbk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rmbkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rmk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rmkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rr, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rrk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ128rrkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rm, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rmb, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rmbk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rmbkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rmk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rmkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rr, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rrk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZ256rrkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrm, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrmb, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrmbk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrmbkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrmk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrmkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrr, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrrk, X86_INS_VPORQ: vporq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORQZrrkz, X86_INS_VPORQ: vporq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORYrm, X86_INS_VPOR: vpor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORYrr, X86_INS_VPOR: vpor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORrm, X86_INS_VPOR: vpor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPORrr, X86_INS_VPOR: vpor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPPERMrmr, X86_INS_VPPERM: vpperm */ 0, { 0 } }, { /* X86_VPPERMrrm, X86_INS_VPPERM: vpperm */ 0, { 0 } }, { /* X86_VPPERMrrr, X86_INS_VPPERM: vpperm */ 0, { 0 } }, { /* X86_VPPERMrrr_REV, X86_INS_VPPERM: vpperm */ 0, { 0 } }, { /* X86_VPROLDZ128mbi, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128mbik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128mbikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128mi, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128mik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128mikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128ri, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128rik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ128rikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256mbi, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256mbik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256mbikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256mi, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256mik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256mikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256ri, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256rik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZ256rikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZmbi, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZmbik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZmbikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZmi, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZmik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZmikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZri, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZrik, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLDZrikz, X86_INS_VPROLD: vprold */ 0, { 0 } }, { /* X86_VPROLQZ128mbi, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128mbik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128mbikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128mi, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128mik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128mikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128ri, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128rik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ128rikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256mbi, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256mbik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256mbikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256mi, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256mik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256mikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256ri, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256rik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZ256rikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZmbi, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZmbik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZmbikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZmi, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZmik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZmikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZri, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZrik, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLQZrikz, X86_INS_VPROLQ: vprolq */ 0, { 0 } }, { /* X86_VPROLVDZ128rm, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rmb, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rmbk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rmbkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rmk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rmkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rr, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rrk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ128rrkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rm, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rmb, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rmbk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rmbkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rmk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rmkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rr, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rrk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZ256rrkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrm, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrmb, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrmbk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrmbkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrmk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrmkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrr, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrrk, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVDZrrkz, X86_INS_VPROLVD: vprolvd */ 0, { 0 } }, { /* X86_VPROLVQZ128rm, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rmb, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rmbk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rmbkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rmk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rmkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rr, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rrk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ128rrkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rm, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rmb, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rmbk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rmbkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rmk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rmkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rr, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rrk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZ256rrkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrm, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrmb, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrmbk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrmbkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrmk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrmkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrr, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrrk, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPROLVQZrrkz, X86_INS_VPROLVQ: vprolvq */ 0, { 0 } }, { /* X86_VPRORDZ128mbi, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128mbik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128mbikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128mi, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128mik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128mikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128ri, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128rik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ128rikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256mbi, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256mbik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256mbikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256mi, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256mik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256mikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256ri, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256rik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZ256rikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZmbi, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZmbik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZmbikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZmi, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZmik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZmikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZri, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZrik, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORDZrikz, X86_INS_VPRORD: vprord */ 0, { 0 } }, { /* X86_VPRORQZ128mbi, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128mbik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128mbikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128mi, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128mik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128mikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128ri, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128rik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ128rikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256mbi, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256mbik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256mbikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256mi, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256mik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256mikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256ri, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256rik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZ256rikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZmbi, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZmbik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZmbikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZmi, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZmik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZmikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZri, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZrik, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORQZrikz, X86_INS_VPRORQ: vprorq */ 0, { 0 } }, { /* X86_VPRORVDZ128rm, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rmb, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rmbk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rmbkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rmk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rmkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rr, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rrk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ128rrkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rm, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rmb, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rmbk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rmbkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rmk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rmkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rr, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rrk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZ256rrkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrm, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrmb, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrmbk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrmbkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrmk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrmkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrr, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrrk, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVDZrrkz, X86_INS_VPRORVD: vprorvd */ 0, { 0 } }, { /* X86_VPRORVQZ128rm, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rmb, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rmbk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rmbkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rmk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rmkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rr, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rrk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ128rrkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rm, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rmb, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rmbk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rmbkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rmk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rmkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rr, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rrk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZ256rrkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrm, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrmb, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrmbk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrmbkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrmk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrmkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrr, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrrk, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPRORVQZrrkz, X86_INS_VPRORVQ: vprorvq */ 0, { 0 } }, { /* X86_VPROTBmi, X86_INS_VPROTB: vprotb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTBmr, X86_INS_VPROTB: vprotb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTBri, X86_INS_VPROTB: vprotb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTBrm, X86_INS_VPROTB: vprotb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTBrr, X86_INS_VPROTB: vprotb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTBrr_REV, X86_INS_VPROTB: vprotb */ 0, { 0 } }, { /* X86_VPROTDmi, X86_INS_VPROTD: vprotd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTDmr, X86_INS_VPROTD: vprotd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTDri, X86_INS_VPROTD: vprotd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTDrm, X86_INS_VPROTD: vprotd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTDrr, X86_INS_VPROTD: vprotd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTDrr_REV, X86_INS_VPROTD: vprotd */ 0, { 0 } }, { /* X86_VPROTQmi, X86_INS_VPROTQ: vprotq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTQmr, X86_INS_VPROTQ: vprotq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTQri, X86_INS_VPROTQ: vprotq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTQrm, X86_INS_VPROTQ: vprotq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTQrr, X86_INS_VPROTQ: vprotq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTQrr_REV, X86_INS_VPROTQ: vprotq */ 0, { 0 } }, { /* X86_VPROTWmi, X86_INS_VPROTW: vprotw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTWmr, X86_INS_VPROTW: vprotw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTWri, X86_INS_VPROTW: vprotw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPROTWrm, X86_INS_VPROTW: vprotw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTWrr, X86_INS_VPROTW: vprotw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPROTWrr_REV, X86_INS_VPROTW: vprotw */ 0, { 0 } }, { /* X86_VPSADBWYrm, X86_INS_VPSADBW: vpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSADBWYrr, X86_INS_VPSADBW: vpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSADBWZ128rm, X86_INS_VPSADBW: vpsadbw */ 0, { 0 } }, { /* X86_VPSADBWZ128rr, X86_INS_VPSADBW: vpsadbw */ 0, { 0 } }, { /* X86_VPSADBWZ256rm, X86_INS_VPSADBW: vpsadbw */ 0, { 0 } }, { /* X86_VPSADBWZ256rr, X86_INS_VPSADBW: vpsadbw */ 0, { 0 } }, { /* X86_VPSADBWZrm, X86_INS_VPSADBW: vpsadbw */ 0, { 0 } }, { /* X86_VPSADBWZrr, X86_INS_VPSADBW: vpsadbw */ 0, { 0 } }, { /* X86_VPSADBWrm, X86_INS_VPSADBW: vpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSADBWrr, X86_INS_VPSADBW: vpsadbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSCATTERDDZ128mr, X86_INS_VPSCATTERDD: vpscatterdd */ 0, { 0 } }, { /* X86_VPSCATTERDDZ256mr, X86_INS_VPSCATTERDD: vpscatterdd */ 0, { 0 } }, { /* X86_VPSCATTERDDZmr, X86_INS_VPSCATTERDD: vpscatterdd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSCATTERDQZ128mr, X86_INS_VPSCATTERDQ: vpscatterdq */ 0, { 0 } }, { /* X86_VPSCATTERDQZ256mr, X86_INS_VPSCATTERDQ: vpscatterdq */ 0, { 0 } }, { /* X86_VPSCATTERDQZmr, X86_INS_VPSCATTERDQ: vpscatterdq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSCATTERQDZ128mr, X86_INS_VPSCATTERQD: vpscatterqd */ 0, { 0 } }, { /* X86_VPSCATTERQDZ256mr, X86_INS_VPSCATTERQD: vpscatterqd */ 0, { 0 } }, { /* X86_VPSCATTERQDZmr, X86_INS_VPSCATTERQD: vpscatterqd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSCATTERQQZ128mr, X86_INS_VPSCATTERQQ: vpscatterqq */ 0, { 0 } }, { /* X86_VPSCATTERQQZ256mr, X86_INS_VPSCATTERQQ: vpscatterqq */ 0, { 0 } }, { /* X86_VPSCATTERQQZmr, X86_INS_VPSCATTERQQ: vpscatterqq */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHABmr, X86_INS_VPSHAB: vpshab */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHABrm, X86_INS_VPSHAB: vpshab */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHABrr, X86_INS_VPSHAB: vpshab */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHABrr_REV, X86_INS_VPSHAB: vpshab */ 0, { 0 } }, { /* X86_VPSHADmr, X86_INS_VPSHAD: vpshad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHADrm, X86_INS_VPSHAD: vpshad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHADrr, X86_INS_VPSHAD: vpshad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHADrr_REV, X86_INS_VPSHAD: vpshad */ 0, { 0 } }, { /* X86_VPSHAQmr, X86_INS_VPSHAQ: vpshaq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHAQrm, X86_INS_VPSHAQ: vpshaq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHAQrr, X86_INS_VPSHAQ: vpshaq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHAQrr_REV, X86_INS_VPSHAQ: vpshaq */ 0, { 0 } }, { /* X86_VPSHAWmr, X86_INS_VPSHAW: vpshaw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHAWrm, X86_INS_VPSHAW: vpshaw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHAWrr, X86_INS_VPSHAW: vpshaw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHAWrr_REV, X86_INS_VPSHAW: vpshaw */ 0, { 0 } }, { /* X86_VPSHLBmr, X86_INS_VPSHLB: vpshlb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLBrm, X86_INS_VPSHLB: vpshlb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLBrr, X86_INS_VPSHLB: vpshlb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLBrr_REV, X86_INS_VPSHLB: vpshlb */ 0, { 0 } }, { /* X86_VPSHLDDZ128rmbi, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rmbik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rmbikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rmi, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rmik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rmikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rri, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rrik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ128rrikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rmbi, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rmbik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rmbikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rmi, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rmik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rmikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rri, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rrik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZ256rrikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrmbi, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrmbik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrmbikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrmi, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrmik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrmikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrri, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrrik, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDDZrrikz, X86_INS_VPSHLDD: vpshldd */ 0, { 0 } }, { /* X86_VPSHLDQZ128rmbi, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rmbik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rmbikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rmi, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rmik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rmikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rri, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rrik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ128rrikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rmbi, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rmbik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rmbikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rmi, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rmik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rmikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rri, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rrik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZ256rrikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrmbi, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrmbik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrmbikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrmi, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrmik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrmikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrri, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrrik, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDQZrrikz, X86_INS_VPSHLDQ: vpshldq */ 0, { 0 } }, { /* X86_VPSHLDVDZ128m, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128mb, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128mbk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128mbkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128mk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128mkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128r, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128rk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ128rkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256m, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256mb, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256mbk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256mbkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256mk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256mkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256r, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256rk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZ256rkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZm, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZmb, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZmbk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZmbkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZmk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZmkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZr, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZrk, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVDZrkz, X86_INS_VPSHLDVD: vpshldvd */ 0, { 0 } }, { /* X86_VPSHLDVQZ128m, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128mb, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128mbk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128mbkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128mk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128mkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128r, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128rk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ128rkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256m, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256mb, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256mbk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256mbkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256mk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256mkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256r, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256rk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZ256rkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZm, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZmb, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZmbk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZmbkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZmk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZmkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZr, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZrk, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVQZrkz, X86_INS_VPSHLDVQ: vpshldvq */ 0, { 0 } }, { /* X86_VPSHLDVWZ128m, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ128mk, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ128mkz, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ128r, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ128rk, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ128rkz, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ256m, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ256mk, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ256mkz, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ256r, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ256rk, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZ256rkz, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZm, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZmk, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZmkz, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZr, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZrk, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDVWZrkz, X86_INS_VPSHLDVW: vpshldvw */ 0, { 0 } }, { /* X86_VPSHLDWZ128rmi, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ128rmik, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ128rmikz, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ128rri, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ128rrik, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ128rrikz, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ256rmi, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ256rmik, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ256rmikz, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ256rri, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ256rrik, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZ256rrikz, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZrmi, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZrmik, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZrmikz, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZrri, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZrrik, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDWZrrikz, X86_INS_VPSHLDW: vpshldw */ 0, { 0 } }, { /* X86_VPSHLDmr, X86_INS_VPSHLD: vpshld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLDrm, X86_INS_VPSHLD: vpshld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLDrr, X86_INS_VPSHLD: vpshld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLDrr_REV, X86_INS_VPSHLD: vpshld */ 0, { 0 } }, { /* X86_VPSHLQmr, X86_INS_VPSHLQ: vpshlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLQrm, X86_INS_VPSHLQ: vpshlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLQrr, X86_INS_VPSHLQ: vpshlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLQrr_REV, X86_INS_VPSHLQ: vpshlq */ 0, { 0 } }, { /* X86_VPSHLWmr, X86_INS_VPSHLW: vpshlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLWrm, X86_INS_VPSHLW: vpshlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLWrr, X86_INS_VPSHLW: vpshlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHLWrr_REV, X86_INS_VPSHLW: vpshlw */ 0, { 0 } }, { /* X86_VPSHRDDZ128rmbi, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rmbik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rmbikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rmi, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rmik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rmikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rri, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rrik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ128rrikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rmbi, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rmbik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rmbikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rmi, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rmik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rmikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rri, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rrik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZ256rrikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrmbi, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrmbik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrmbikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrmi, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrmik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrmikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrri, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrrik, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDDZrrikz, X86_INS_VPSHRDD: vpshrdd */ 0, { 0 } }, { /* X86_VPSHRDQZ128rmbi, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rmbik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rmbikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rmi, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rmik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rmikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rri, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rrik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ128rrikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rmbi, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rmbik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rmbikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rmi, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rmik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rmikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rri, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rrik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZ256rrikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrmbi, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrmbik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrmbikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrmi, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrmik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrmikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrri, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrrik, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDQZrrikz, X86_INS_VPSHRDQ: vpshrdq */ 0, { 0 } }, { /* X86_VPSHRDVDZ128m, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128mb, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128mbk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128mbkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128mk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128mkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128r, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128rk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ128rkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256m, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256mb, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256mbk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256mbkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256mk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256mkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256r, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256rk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZ256rkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZm, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZmb, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZmbk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZmbkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZmk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZmkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZr, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZrk, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVDZrkz, X86_INS_VPSHRDVD: vpshrdvd */ 0, { 0 } }, { /* X86_VPSHRDVQZ128m, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128mb, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128mbk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128mbkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128mk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128mkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128r, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128rk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ128rkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256m, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256mb, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256mbk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256mbkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256mk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256mkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256r, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256rk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZ256rkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZm, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZmb, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZmbk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZmbkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZmk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZmkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZr, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZrk, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVQZrkz, X86_INS_VPSHRDVQ: vpshrdvq */ 0, { 0 } }, { /* X86_VPSHRDVWZ128m, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ128mk, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ128mkz, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ128r, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ128rk, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ128rkz, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ256m, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ256mk, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ256mkz, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ256r, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ256rk, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZ256rkz, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZm, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZmk, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZmkz, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZr, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZrk, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDVWZrkz, X86_INS_VPSHRDVW: vpshrdvw */ 0, { 0 } }, { /* X86_VPSHRDWZ128rmi, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ128rmik, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ128rmikz, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ128rri, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ128rrik, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ128rrikz, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ256rmi, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ256rmik, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ256rmikz, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ256rri, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ256rrik, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZ256rrikz, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZrmi, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZrmik, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZrmikz, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZrri, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZrrik, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHRDWZrrikz, X86_INS_VPSHRDW: vpshrdw */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ128rm, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ128rmk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ128rr, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ128rrk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ256rm, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ256rmk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ256rr, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZ256rrk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZrm, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZrmk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZrr, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBITQMBZrrk, X86_INS_VPSHUFBITQMB: vpshufbitqmb */ 0, { 0 } }, { /* X86_VPSHUFBYrm, X86_INS_VPSHUFB: vpshufb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHUFBYrr, X86_INS_VPSHUFB: vpshufb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHUFBZ128rm, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ128rmk, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ128rmkz, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ128rr, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ128rrk, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ128rrkz, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ256rm, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ256rmk, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ256rmkz, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ256rr, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ256rrk, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZ256rrkz, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZrm, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZrmk, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZrmkz, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZrr, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZrrk, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBZrrkz, X86_INS_VPSHUFB: vpshufb */ 0, { 0 } }, { /* X86_VPSHUFBrm, X86_INS_VPSHUFB: vpshufb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHUFBrr, X86_INS_VPSHUFB: vpshufb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSHUFDYmi, X86_INS_VPSHUFD: vpshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFDYri, X86_INS_VPSHUFD: vpshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFDZ128mbi, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128mbik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128mbikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128mi, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128mik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128mikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128ri, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128rik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ128rikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256mbi, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256mbik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256mbikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256mi, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256mik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256mikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256ri, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256rik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZ256rikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZmbi, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZmbik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZmbikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZmi, X86_INS_VPSHUFD: vpshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFDZmik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZmikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZri, X86_INS_VPSHUFD: vpshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFDZrik, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDZrikz, X86_INS_VPSHUFD: vpshufd */ 0, { 0 } }, { /* X86_VPSHUFDmi, X86_INS_VPSHUFD: vpshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFDri, X86_INS_VPSHUFD: vpshufd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFHWYmi, X86_INS_VPSHUFHW: vpshufhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFHWYri, X86_INS_VPSHUFHW: vpshufhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFHWZ128mi, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ128mik, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ128mikz, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ128ri, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ128rik, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ128rikz, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ256mi, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ256mik, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ256mikz, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ256ri, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ256rik, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZ256rikz, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZmi, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZmik, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZmikz, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZri, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZrik, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWZrikz, X86_INS_VPSHUFHW: vpshufhw */ 0, { 0 } }, { /* X86_VPSHUFHWmi, X86_INS_VPSHUFHW: vpshufhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFHWri, X86_INS_VPSHUFHW: vpshufhw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFLWYmi, X86_INS_VPSHUFLW: vpshuflw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFLWYri, X86_INS_VPSHUFLW: vpshuflw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFLWZ128mi, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ128mik, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ128mikz, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ128ri, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ128rik, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ128rikz, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ256mi, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ256mik, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ256mikz, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ256ri, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ256rik, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZ256rikz, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZmi, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZmik, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZmikz, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZri, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZrik, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWZrikz, X86_INS_VPSHUFLW: vpshuflw */ 0, { 0 } }, { /* X86_VPSHUFLWmi, X86_INS_VPSHUFLW: vpshuflw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSHUFLWri, X86_INS_VPSHUFLW: vpshuflw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSIGNBYrm, X86_INS_VPSIGNB: vpsignb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNBYrr, X86_INS_VPSIGNB: vpsignb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNBrm, X86_INS_VPSIGNB: vpsignb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNBrr, X86_INS_VPSIGNB: vpsignb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNDYrm, X86_INS_VPSIGND: vpsignd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNDYrr, X86_INS_VPSIGND: vpsignd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNDrm, X86_INS_VPSIGND: vpsignd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNDrr, X86_INS_VPSIGND: vpsignd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNWYrm, X86_INS_VPSIGNW: vpsignw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNWYrr, X86_INS_VPSIGNW: vpsignw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNWrm, X86_INS_VPSIGNW: vpsignw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSIGNWrr, X86_INS_VPSIGNW: vpsignw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDQYri, X86_INS_VPSLLDQ: vpslldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDQZ128rm, X86_INS_VPSLLDQ: vpslldq */ 0, { 0 } }, { /* X86_VPSLLDQZ128rr, X86_INS_VPSLLDQ: vpslldq */ 0, { 0 } }, { /* X86_VPSLLDQZ256rm, X86_INS_VPSLLDQ: vpslldq */ 0, { 0 } }, { /* X86_VPSLLDQZ256rr, X86_INS_VPSLLDQ: vpslldq */ 0, { 0 } }, { /* X86_VPSLLDQZrm, X86_INS_VPSLLDQ: vpslldq */ 0, { 0 } }, { /* X86_VPSLLDQZrr, X86_INS_VPSLLDQ: vpslldq */ 0, { 0 } }, { /* X86_VPSLLDQri, X86_INS_VPSLLDQ: vpslldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDYri, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDYrm, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDYrr, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDZ128mbi, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128mbik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128mbikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128mi, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128mik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128mikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128ri, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rm, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rmk, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rmkz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rr, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rrk, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ128rrkz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256mbi, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256mbik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256mbikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256mi, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256mik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256mikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256ri, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rm, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rmk, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rmkz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rr, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rrk, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZ256rrkz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZmbi, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZmbik, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZmbikz, X86_INS_VPSLLD: vpslld */ 0, { 0 } }, { /* X86_VPSLLDZmi, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDZmik, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDZmikz, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDZri, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDZrik, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDZrikz, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDZrm, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDZrmk, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDZrmkz, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDZrr, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDZrrk, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDZrrkz, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDri, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLDrm, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLDrr, X86_INS_VPSLLD: vpslld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQYri, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQYrm, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQYrr, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQZ128mbi, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128mbik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128mbikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128mi, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128mik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128mikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128ri, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rm, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rmk, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rmkz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rr, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rrk, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ128rrkz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256mbi, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256mbik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256mbikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256mi, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256mik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256mikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256ri, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rm, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rmk, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rmkz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rr, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rrk, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZ256rrkz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZmbi, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZmbik, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZmbikz, X86_INS_VPSLLQ: vpsllq */ 0, { 0 } }, { /* X86_VPSLLQZmi, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQZmik, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQZmikz, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQZri, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQZrik, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQZrikz, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQZrm, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQZrmk, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQZrmkz, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQZrr, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQZrrk, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQZrrkz, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQri, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLQrm, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLQrr, X86_INS_VPSLLQ: vpsllq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDYrm, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDYrr, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDZ128rm, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rmb, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rmbk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rmbkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rmk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rmkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rr, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rrk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ128rrkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rm, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rmb, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rmbk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rmbkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rmk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rmkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rr, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rrk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZ256rrkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZrm, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDZrmb, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZrmbk, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZrmbkz, X86_INS_VPSLLVD: vpsllvd */ 0, { 0 } }, { /* X86_VPSLLVDZrmk, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDZrmkz, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDZrr, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDZrrk, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDZrrkz, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDrm, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVDrr, X86_INS_VPSLLVD: vpsllvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQYrm, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQYrr, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQZ128rm, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rmb, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rmbk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rmbkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rmk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rmkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rr, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rrk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ128rrkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rm, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rmb, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rmbk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rmbkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rmk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rmkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rr, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rrk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZ256rrkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZrm, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQZrmb, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZrmbk, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZrmbkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { 0 } }, { /* X86_VPSLLVQZrmk, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQZrmkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQZrr, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQZrrk, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQZrrkz, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQrm, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVQrr, X86_INS_VPSLLVQ: vpsllvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLVWZ128rm, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ128rmk, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ128rmkz, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ128rr, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ128rrk, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ128rrkz, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ256rm, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ256rmk, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ256rmkz, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ256rr, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ256rrk, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZ256rrkz, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZrm, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZrmk, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZrmkz, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZrr, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZrrk, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLVWZrrkz, X86_INS_VPSLLVW: vpsllvw */ 0, { 0 } }, { /* X86_VPSLLWYri, X86_INS_VPSLLW: vpsllw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLWYrm, X86_INS_VPSLLW: vpsllw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLWYrr, X86_INS_VPSLLW: vpsllw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLWZ128mi, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128mik, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128mikz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128ri, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rik, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rikz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rm, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rmk, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rmkz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rr, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rrk, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ128rrkz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256mi, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256mik, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256mikz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256ri, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rik, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rikz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rm, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rmk, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rmkz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rr, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rrk, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZ256rrkz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZmi, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZmik, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZmikz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZri, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrik, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrikz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrm, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrmk, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrmkz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrr, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrrk, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWZrrkz, X86_INS_VPSLLW: vpsllw */ 0, { 0 } }, { /* X86_VPSLLWri, X86_INS_VPSLLW: vpsllw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSLLWrm, X86_INS_VPSLLW: vpsllw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSLLWrr, X86_INS_VPSLLW: vpsllw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADYri, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADYrm, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADYrr, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADZ128mbi, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128mbik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128mbikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128mi, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128mik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128mikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128ri, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rm, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rmk, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rmkz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rr, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rrk, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ128rrkz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256mbi, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256mbik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256mbikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256mi, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256mik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256mikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256ri, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rm, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rmk, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rmkz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rr, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rrk, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZ256rrkz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZmbi, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZmbik, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZmbikz, X86_INS_VPSRAD: vpsrad */ 0, { 0 } }, { /* X86_VPSRADZmi, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADZmik, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADZmikz, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADZri, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADZrik, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADZrikz, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADZrm, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADZrmk, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADZrmkz, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADZrr, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADZrrk, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADZrrkz, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADri, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRADrm, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRADrr, X86_INS_VPSRAD: vpsrad */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAQZ128mbi, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128mbik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128mbikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128mi, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128mik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128mikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128ri, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rm, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rmk, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rmkz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rr, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rrk, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ128rrkz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256mbi, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256mbik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256mbikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256mi, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256mik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256mikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256ri, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rm, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rmk, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rmkz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rr, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rrk, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZ256rrkz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZmbi, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZmbik, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZmbikz, X86_INS_VPSRAQ: vpsraq */ 0, { 0 } }, { /* X86_VPSRAQZmi, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAQZmik, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAQZmikz, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAQZri, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAQZrik, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAQZrikz, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAQZrm, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAQZrmk, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAQZrmkz, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAQZrr, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAQZrrk, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAQZrrkz, X86_INS_VPSRAQ: vpsraq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDYrm, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDYrr, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDZ128rm, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rmb, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rmbk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rmbkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rmk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rmkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rr, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rrk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ128rrkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rm, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rmb, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rmbk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rmbkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rmk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rmkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rr, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rrk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZ256rrkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZrm, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDZrmb, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZrmbk, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZrmbkz, X86_INS_VPSRAVD: vpsravd */ 0, { 0 } }, { /* X86_VPSRAVDZrmk, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDZrmkz, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDZrr, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDZrrk, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDZrrkz, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDrm, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVDrr, X86_INS_VPSRAVD: vpsravd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVQZ128rm, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rmb, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rmbk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rmbkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rmk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rmkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rr, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rrk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ128rrkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rm, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rmb, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rmbk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rmbkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rmk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rmkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rr, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rrk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZ256rrkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZrm, X86_INS_VPSRAVQ: vpsravq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVQZrmb, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZrmbk, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZrmbkz, X86_INS_VPSRAVQ: vpsravq */ 0, { 0 } }, { /* X86_VPSRAVQZrmk, X86_INS_VPSRAVQ: vpsravq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVQZrmkz, X86_INS_VPSRAVQ: vpsravq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVQZrr, X86_INS_VPSRAVQ: vpsravq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVQZrrk, X86_INS_VPSRAVQ: vpsravq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVQZrrkz, X86_INS_VPSRAVQ: vpsravq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAVWZ128rm, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ128rmk, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ128rmkz, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ128rr, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ128rrk, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ128rrkz, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ256rm, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ256rmk, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ256rmkz, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ256rr, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ256rrk, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZ256rrkz, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZrm, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZrmk, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZrmkz, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZrr, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZrrk, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAVWZrrkz, X86_INS_VPSRAVW: vpsravw */ 0, { 0 } }, { /* X86_VPSRAWYri, X86_INS_VPSRAW: vpsraw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAWYrm, X86_INS_VPSRAW: vpsraw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAWYrr, X86_INS_VPSRAW: vpsraw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAWZ128mi, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128mik, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128mikz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128ri, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rik, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rikz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rm, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rmk, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rmkz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rr, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rrk, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ128rrkz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256mi, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256mik, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256mikz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256ri, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rik, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rikz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rm, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rmk, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rmkz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rr, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rrk, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZ256rrkz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZmi, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZmik, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZmikz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZri, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrik, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrikz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrm, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrmk, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrmkz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrr, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrrk, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWZrrkz, X86_INS_VPSRAW: vpsraw */ 0, { 0 } }, { /* X86_VPSRAWri, X86_INS_VPSRAW: vpsraw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRAWrm, X86_INS_VPSRAW: vpsraw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRAWrr, X86_INS_VPSRAW: vpsraw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDQYri, X86_INS_VPSRLDQ: vpsrldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDQZ128rm, X86_INS_VPSRLDQ: vpsrldq */ 0, { 0 } }, { /* X86_VPSRLDQZ128rr, X86_INS_VPSRLDQ: vpsrldq */ 0, { 0 } }, { /* X86_VPSRLDQZ256rm, X86_INS_VPSRLDQ: vpsrldq */ 0, { 0 } }, { /* X86_VPSRLDQZ256rr, X86_INS_VPSRLDQ: vpsrldq */ 0, { 0 } }, { /* X86_VPSRLDQZrm, X86_INS_VPSRLDQ: vpsrldq */ 0, { 0 } }, { /* X86_VPSRLDQZrr, X86_INS_VPSRLDQ: vpsrldq */ 0, { 0 } }, { /* X86_VPSRLDQri, X86_INS_VPSRLDQ: vpsrldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDYri, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDYrm, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDYrr, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDZ128mbi, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128mbik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128mbikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128mi, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128mik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128mikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128ri, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rm, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rmk, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rmkz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rr, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rrk, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ128rrkz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256mbi, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256mbik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256mbikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256mi, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256mik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256mikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256ri, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rm, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rmk, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rmkz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rr, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rrk, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZ256rrkz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZmbi, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZmbik, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZmbikz, X86_INS_VPSRLD: vpsrld */ 0, { 0 } }, { /* X86_VPSRLDZmi, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDZmik, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDZmikz, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDZri, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDZrik, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDZrikz, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDZrm, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDZrmk, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDZrmkz, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDZrr, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDZrrk, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDZrrkz, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDri, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLDrm, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLDrr, X86_INS_VPSRLD: vpsrld */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQYri, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQYrm, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQYrr, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQZ128mbi, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128mbik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128mbikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128mi, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128mik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128mikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128ri, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rm, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rmk, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rmkz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rr, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rrk, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ128rrkz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256mbi, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256mbik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256mbikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256mi, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256mik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256mikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256ri, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rm, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rmk, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rmkz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rr, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rrk, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZ256rrkz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZmbi, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZmbik, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZmbikz, X86_INS_VPSRLQ: vpsrlq */ 0, { 0 } }, { /* X86_VPSRLQZmi, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQZmik, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQZmikz, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQZri, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQZrik, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQZrikz, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQZrm, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQZrmk, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQZrmkz, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQZrr, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQZrrk, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQZrrkz, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQri, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLQrm, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLQrr, X86_INS_VPSRLQ: vpsrlq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDYrm, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDYrr, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDZ128rm, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rmb, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rmbk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rmbkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rmk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rmkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rr, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rrk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ128rrkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rm, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rmb, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rmbk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rmbkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rmk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rmkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rr, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rrk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZ256rrkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZrm, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDZrmb, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZrmbk, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZrmbkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { 0 } }, { /* X86_VPSRLVDZrmk, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDZrmkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDZrr, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDZrrk, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDZrrkz, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDrm, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVDrr, X86_INS_VPSRLVD: vpsrlvd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQYrm, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQYrr, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQZ128rm, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rmb, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rmbk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rmbkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rmk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rmkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rr, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rrk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ128rrkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rm, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rmb, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rmbk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rmbkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rmk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rmkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rr, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rrk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZ256rrkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZrm, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQZrmb, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZrmbk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZrmbkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { 0 } }, { /* X86_VPSRLVQZrmk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQZrmkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQZrr, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQZrrk, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQZrrkz, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQrm, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVQrr, X86_INS_VPSRLVQ: vpsrlvq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLVWZ128rm, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ128rmk, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ128rmkz, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ128rr, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ128rrk, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ128rrkz, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ256rm, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ256rmk, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ256rmkz, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ256rr, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ256rrk, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZ256rrkz, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZrm, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZrmk, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZrmkz, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZrr, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZrrk, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLVWZrrkz, X86_INS_VPSRLVW: vpsrlvw */ 0, { 0 } }, { /* X86_VPSRLWYri, X86_INS_VPSRLW: vpsrlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLWYrm, X86_INS_VPSRLW: vpsrlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLWYrr, X86_INS_VPSRLW: vpsrlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLWZ128mi, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128mik, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128mikz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128ri, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rik, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rikz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rm, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rmk, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rmkz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rr, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rrk, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ128rrkz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256mi, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256mik, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256mikz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256ri, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rik, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rikz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rm, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rmk, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rmkz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rr, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rrk, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZ256rrkz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZmi, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZmik, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZmikz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZri, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrik, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrikz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrm, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrmk, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrmkz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrr, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrrk, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWZrrkz, X86_INS_VPSRLW: vpsrlw */ 0, { 0 } }, { /* X86_VPSRLWri, X86_INS_VPSRLW: vpsrlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VPSRLWrm, X86_INS_VPSRLW: vpsrlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSRLWrr, X86_INS_VPSRLW: vpsrlw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBYrm, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBYrr, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ128rm, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ128rmk, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ128rmkz, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ128rr, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ128rrk, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ128rrkz, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ256rm, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ256rmk, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ256rmkz, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ256rr, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ256rrk, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZ256rrkz, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZrm, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZrmk, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZrmkz, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZrr, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZrrk, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBZrrkz, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBrm, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBBrr, X86_INS_VPSUBB: vpsubb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDYrm, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDYrr, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rm, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rmb, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rmbk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rmbkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rmk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rmkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rr, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rrk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ128rrkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rm, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rmb, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rmbk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rmbkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rmk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rmkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rr, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rrk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZ256rrkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrm, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrmb, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrmbk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrmbkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrmk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrmkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrr, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrrk, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDZrrkz, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDrm, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBDrr, X86_INS_VPSUBD: vpsubd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQYrm, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQYrr, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rm, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rmb, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rmbk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rmbkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rmk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rmkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rr, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rrk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ128rrkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rm, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rmb, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rmbk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rmbkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rmk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rmkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rr, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rrk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZ256rrkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrm, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrmb, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrmbk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrmbkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrmk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrmkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrr, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrrk, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQZrrkz, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQrm, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBQrr, X86_INS_VPSUBQ: vpsubq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSBYrm, X86_INS_VPSUBSB: vpsubsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSBYrr, X86_INS_VPSUBSB: vpsubsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSBZ128rm, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ128rmk, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ128rmkz, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ128rr, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ128rrk, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ128rrkz, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ256rm, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ256rmk, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ256rmkz, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ256rr, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ256rrk, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZ256rrkz, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZrm, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZrmk, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZrmkz, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZrr, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZrrk, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBZrrkz, X86_INS_VPSUBSB: vpsubsb */ 0, { 0 } }, { /* X86_VPSUBSBrm, X86_INS_VPSUBSB: vpsubsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSBrr, X86_INS_VPSUBSB: vpsubsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSWYrm, X86_INS_VPSUBSW: vpsubsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSWYrr, X86_INS_VPSUBSW: vpsubsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSWZ128rm, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ128rmk, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ128rmkz, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ128rr, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ128rrk, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ128rrkz, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ256rm, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ256rmk, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ256rmkz, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ256rr, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ256rrk, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZ256rrkz, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZrm, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZrmk, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZrmkz, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZrr, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZrrk, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWZrrkz, X86_INS_VPSUBSW: vpsubsw */ 0, { 0 } }, { /* X86_VPSUBSWrm, X86_INS_VPSUBSW: vpsubsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBSWrr, X86_INS_VPSUBSW: vpsubsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSBYrm, X86_INS_VPSUBUSB: vpsubusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSBYrr, X86_INS_VPSUBUSB: vpsubusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSBZ128rm, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ128rmk, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ128rmkz, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ128rr, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ128rrk, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ128rrkz, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ256rm, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ256rmk, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ256rmkz, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ256rr, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ256rrk, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZ256rrkz, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZrm, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZrmk, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZrmkz, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZrr, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZrrk, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBZrrkz, X86_INS_VPSUBUSB: vpsubusb */ 0, { 0 } }, { /* X86_VPSUBUSBrm, X86_INS_VPSUBUSB: vpsubusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSBrr, X86_INS_VPSUBUSB: vpsubusb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSWYrm, X86_INS_VPSUBUSW: vpsubusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSWYrr, X86_INS_VPSUBUSW: vpsubusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSWZ128rm, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ128rmk, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ128rmkz, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ128rr, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ128rrk, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ128rrkz, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ256rm, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ256rmk, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ256rmkz, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ256rr, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ256rrk, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZ256rrkz, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZrm, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZrmk, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZrmkz, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZrr, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZrrk, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWZrrkz, X86_INS_VPSUBUSW: vpsubusw */ 0, { 0 } }, { /* X86_VPSUBUSWrm, X86_INS_VPSUBUSW: vpsubusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBUSWrr, X86_INS_VPSUBUSW: vpsubusw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWYrm, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWYrr, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ128rm, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ128rmk, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ128rmkz, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ128rr, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ128rrk, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ128rrkz, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ256rm, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ256rmk, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ256rmkz, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ256rr, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ256rrk, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZ256rrkz, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZrm, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZrmk, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZrmkz, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZrr, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZrrk, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWZrrkz, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWrm, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPSUBWrr, X86_INS_VPSUBW: vpsubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTERNLOGDZ128rmbi, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rmbik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rmbikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rmi, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rmik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rmikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rri, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rrik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ128rrikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rmbi, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rmbik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rmbikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rmi, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rmik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rmikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rri, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rrik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZ256rrikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrmbi, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrmbik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrmbikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrmi, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrmik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrmikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrri, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrrik, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGDZrrikz, X86_INS_VPTERNLOGD: vpternlogd */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rmbi, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rmbik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rmbikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rmi, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rmik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rmikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rri, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rrik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ128rrikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rmbi, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rmbik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rmbikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rmi, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rmik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rmikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rri, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rrik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZ256rrikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrmbi, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrmbik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrmbikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrmi, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrmik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrmikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrri, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrrik, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTERNLOGQZrrikz, X86_INS_VPTERNLOGQ: vpternlogq */ 0, { 0 } }, { /* X86_VPTESTMBZ128rm, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ128rmk, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ128rr, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ128rrk, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ256rm, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ256rmk, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ256rr, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZ256rrk, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZrm, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZrmk, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZrr, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMBZrrk, X86_INS_VPTESTMB: vptestmb */ 0, { 0 } }, { /* X86_VPTESTMDZ128rm, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ128rmb, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ128rmbk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ128rmk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ128rr, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ128rrk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ256rm, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ256rmb, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ256rmbk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ256rmk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ256rr, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZ256rrk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZrm, X86_INS_VPTESTMD: vptestmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTMDZrmb, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZrmbk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZrmk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMDZrr, X86_INS_VPTESTMD: vptestmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTMDZrrk, X86_INS_VPTESTMD: vptestmd */ 0, { 0 } }, { /* X86_VPTESTMQZ128rm, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ128rmb, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ128rmbk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ128rmk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ128rr, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ128rrk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ256rm, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ256rmb, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ256rmbk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ256rmk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ256rr, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZ256rrk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZrm, X86_INS_VPTESTMQ: vptestmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTMQZrmb, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZrmbk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZrmk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMQZrr, X86_INS_VPTESTMQ: vptestmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTMQZrrk, X86_INS_VPTESTMQ: vptestmq */ 0, { 0 } }, { /* X86_VPTESTMWZ128rm, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ128rmk, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ128rr, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ128rrk, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ256rm, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ256rmk, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ256rr, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZ256rrk, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZrm, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZrmk, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZrr, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTMWZrrk, X86_INS_VPTESTMW: vptestmw */ 0, { 0 } }, { /* X86_VPTESTNMBZ128rm, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ128rmk, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ128rr, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ128rrk, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ256rm, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ256rmk, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ256rr, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZ256rrk, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZrm, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZrmk, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZrr, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMBZrrk, X86_INS_VPTESTNMB: vptestnmb */ 0, { 0 } }, { /* X86_VPTESTNMDZ128rm, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ128rmb, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ128rmbk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ128rmk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ128rr, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ128rrk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ256rm, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ256rmb, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ256rmbk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ256rmk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ256rr, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZ256rrk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZrm, X86_INS_VPTESTNMD: vptestnmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTNMDZrmb, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZrmbk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZrmk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMDZrr, X86_INS_VPTESTNMD: vptestnmd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTNMDZrrk, X86_INS_VPTESTNMD: vptestnmd */ 0, { 0 } }, { /* X86_VPTESTNMQZ128rm, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ128rmb, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ128rmbk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ128rmk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ128rr, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ128rrk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ256rm, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ256rmb, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ256rmbk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ256rmk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ256rr, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZ256rrk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZrm, X86_INS_VPTESTNMQ: vptestnmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTNMQZrmb, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZrmbk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZrmk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMQZrr, X86_INS_VPTESTNMQ: vptestnmq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTNMQZrrk, X86_INS_VPTESTNMQ: vptestnmq */ 0, { 0 } }, { /* X86_VPTESTNMWZ128rm, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ128rmk, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ128rr, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ128rrk, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ256rm, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ256rmk, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ256rr, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZ256rrk, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZrm, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZrmk, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZrr, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTNMWZrrk, X86_INS_VPTESTNMW: vptestnmw */ 0, { 0 } }, { /* X86_VPTESTYrm, X86_INS_VPTEST: vptest */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTYrr, X86_INS_VPTEST: vptest */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTrm, X86_INS_VPTEST: vptest */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPTESTrr, X86_INS_VPTEST: vptest */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHBWYrm, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHBWYrr, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHBWZ128rm, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ128rmk, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ128rmkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ128rr, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ128rrk, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ128rrkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ256rm, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ256rmk, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ256rmkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ256rr, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ256rrk, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZ256rrkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZrm, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZrmk, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZrmkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZrr, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZrrk, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWZrrkz, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { 0 } }, { /* X86_VPUNPCKHBWrm, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHBWrr, X86_INS_VPUNPCKHBW: vpunpckhbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHDQYrm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHDQYrr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHDQZ128rm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rmb, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rmbk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rmbkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rmk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rmkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rrk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ128rrkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rmb, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rmbk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rmbkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rmk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rmkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rrk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZ256rrkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHDQZrmb, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrmbk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrmbkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrmk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrmkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHDQZrrk, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQZrrkz, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { 0 } }, { /* X86_VPUNPCKHDQrm, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHDQrr, X86_INS_VPUNPCKHDQ: vpunpckhdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHQDQYrm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHQDQYrr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHQDQZ128rm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rmb, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rmbk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rmbkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rmk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rmkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rrk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ128rrkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rmb, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rmbk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rmbkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rmk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rmkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rrk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZ256rrkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHQDQZrmb, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrmbk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrmbkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrmk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrmkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHQDQZrrk, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQZrrkz, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { 0 } }, { /* X86_VPUNPCKHQDQrm, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHQDQrr, X86_INS_VPUNPCKHQDQ: vpunpckhqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHWDYrm, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHWDYrr, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHWDZ128rm, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ128rmk, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ128rmkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ128rr, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ128rrk, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ128rrkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ256rm, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ256rmk, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ256rmkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ256rr, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ256rrk, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZ256rrkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZrm, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZrmk, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZrmkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZrr, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZrrk, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDZrrkz, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { 0 } }, { /* X86_VPUNPCKHWDrm, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKHWDrr, X86_INS_VPUNPCKHWD: vpunpckhwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLBWYrm, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLBWYrr, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLBWZ128rm, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ128rmk, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ128rmkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ128rr, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ128rrk, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ128rrkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ256rm, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ256rmk, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ256rmkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ256rr, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ256rrk, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZ256rrkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZrm, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZrmk, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZrmkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZrr, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZrrk, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWZrrkz, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { 0 } }, { /* X86_VPUNPCKLBWrm, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLBWrr, X86_INS_VPUNPCKLBW: vpunpcklbw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLDQYrm, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLDQYrr, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLDQZ128rm, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rmb, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rmbk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rmbkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rmk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rmkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rr, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rrk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ128rrkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rm, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rmb, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rmbk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rmbkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rmk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rmkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rr, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rrk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZ256rrkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrm, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLDQZrmb, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrmbk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrmbkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrmk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrmkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrr, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLDQZrrk, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQZrrkz, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { 0 } }, { /* X86_VPUNPCKLDQrm, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLDQrr, X86_INS_VPUNPCKLDQ: vpunpckldq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLQDQYrm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLQDQYrr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLQDQZ128rm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rmb, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rmbk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rmbkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rmk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rmkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rrk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ128rrkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rmb, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rmbk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rmbkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rmk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rmkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rrk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZ256rrkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLQDQZrmb, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrmbk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrmbkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrmk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrmkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLQDQZrrk, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQZrrkz, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { 0 } }, { /* X86_VPUNPCKLQDQrm, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLQDQrr, X86_INS_VPUNPCKLQDQ: vpunpcklqdq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLWDYrm, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLWDYrr, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLWDZ128rm, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ128rmk, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ128rmkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ128rr, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ128rrk, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ128rrkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ256rm, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ256rmk, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ256rmkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ256rr, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ256rrk, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZ256rrkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZrm, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZrmk, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZrmkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZrr, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZrrk, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDZrrkz, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { 0 } }, { /* X86_VPUNPCKLWDrm, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPUNPCKLWDrr, X86_INS_VPUNPCKLWD: vpunpcklwd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rm, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rmb, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rmbk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rmbkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rmk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rmkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rr, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rrk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ128rrkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rm, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rmb, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rmbk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rmbkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rmk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rmkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rr, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rrk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZ256rrkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrm, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrmb, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrmbk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrmbkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrmk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrmkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrr, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrrk, X86_INS_VPXORD: vpxord */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORDZrrkz, X86_INS_VPXORD: vpxord */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rm, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rmb, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rmbk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rmbkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rmk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rmkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rr, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rrk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ128rrkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rm, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rmb, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rmbk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rmbkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rmk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rmkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rr, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rrk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZ256rrkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrm, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrmb, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrmbk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrmbkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrmk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrmkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrr, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrrk, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORQZrrkz, X86_INS_VPXORQ: vpxorq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORYrm, X86_INS_VPXOR: vpxor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORYrr, X86_INS_VPXOR: vpxor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORrm, X86_INS_VPXOR: vpxor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VPXORrr, X86_INS_VPXOR: vpxor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VRANGEPDZ128rmbi, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rmbik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rmbikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rmi, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rmik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rmikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rri, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rrik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ128rrikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rmbi, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rmbik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rmbikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rmi, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rmik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rmikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rri, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rrik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZ256rrikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrmbi, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrmbik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrmbikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrmi, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrmik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrmikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrri, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrrib, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrribk, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrribkz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrrik, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPDZrrikz, X86_INS_VRANGEPD: vrangepd */ 0, { 0 } }, { /* X86_VRANGEPSZ128rmbi, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rmbik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rmbikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rmi, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rmik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rmikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rri, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rrik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ128rrikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rmbi, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rmbik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rmbikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rmi, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rmik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rmikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rri, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rrik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZ256rrikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrmbi, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrmbik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrmbikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrmi, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrmik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrmikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrri, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrrib, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrribk, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrribkz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrrik, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGEPSZrrikz, X86_INS_VRANGEPS: vrangeps */ 0, { 0 } }, { /* X86_VRANGESDZrmi, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrmik, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrmikz, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrri, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrrib, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrribk, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrribkz, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrrik, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESDZrrikz, X86_INS_VRANGESD: vrangesd */ 0, { 0 } }, { /* X86_VRANGESSZrmi, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrmik, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrmikz, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrri, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrrib, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrribk, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrribkz, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrrik, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRANGESSZrrikz, X86_INS_VRANGESS: vrangess */ 0, { 0 } }, { /* X86_VRCP14PDZ128m, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128mb, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128mbk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128mbkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128mk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128mkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128r, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128rk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ128rkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256m, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256mb, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256mbk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256mbkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256mk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256mkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256r, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256rk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZ256rkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZm, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZmb, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZmbk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZmbkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZmk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZmkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZr, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZrk, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PDZrkz, X86_INS_VRCP14PD: vrcp14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128m, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128mb, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128mbk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128mbkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128mk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128mkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128r, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128rk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ128rkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256m, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256mb, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256mbk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256mbkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256mk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256mkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256r, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256rk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZ256rkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZm, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZmb, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZmbk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZmbkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZmk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZmkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZr, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZrk, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14PSZrkz, X86_INS_VRCP14PS: vrcp14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCP14SDZrm, X86_INS_VRCP14SD: vrcp14sd */ 0, { 0 } }, { /* X86_VRCP14SDZrmk, X86_INS_VRCP14SD: vrcp14sd */ 0, { 0 } }, { /* X86_VRCP14SDZrmkz, X86_INS_VRCP14SD: vrcp14sd */ 0, { 0 } }, { /* X86_VRCP14SDZrr, X86_INS_VRCP14SD: vrcp14sd */ 0, { 0 } }, { /* X86_VRCP14SDZrrk, X86_INS_VRCP14SD: vrcp14sd */ 0, { 0 } }, { /* X86_VRCP14SDZrrkz, X86_INS_VRCP14SD: vrcp14sd */ 0, { 0 } }, { /* X86_VRCP14SSZrm, X86_INS_VRCP14SS: vrcp14ss */ 0, { 0 } }, { /* X86_VRCP14SSZrmk, X86_INS_VRCP14SS: vrcp14ss */ 0, { 0 } }, { /* X86_VRCP14SSZrmkz, X86_INS_VRCP14SS: vrcp14ss */ 0, { 0 } }, { /* X86_VRCP14SSZrr, X86_INS_VRCP14SS: vrcp14ss */ 0, { 0 } }, { /* X86_VRCP14SSZrrk, X86_INS_VRCP14SS: vrcp14ss */ 0, { 0 } }, { /* X86_VRCP14SSZrrkz, X86_INS_VRCP14SS: vrcp14ss */ 0, { 0 } }, { /* X86_VRCP28PDZm, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZmb, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZmbk, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZmbkz, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZmk, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZmkz, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZr, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZrb, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZrbk, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZrbkz, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZrk, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PDZrkz, X86_INS_VRCP28PD: vrcp28pd */ 0, { 0 } }, { /* X86_VRCP28PSZm, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZmb, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZmbk, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZmbkz, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZmk, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZmkz, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZr, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZrb, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZrbk, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZrbkz, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZrk, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28PSZrkz, X86_INS_VRCP28PS: vrcp28ps */ 0, { 0 } }, { /* X86_VRCP28SDZm, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZmk, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZmkz, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZr, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZrb, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZrbk, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZrbkz, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZrk, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SDZrkz, X86_INS_VRCP28SD: vrcp28sd */ 0, { 0 } }, { /* X86_VRCP28SSZm, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZmk, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZmkz, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZr, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZrb, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZrbk, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZrbkz, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZrk, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCP28SSZrkz, X86_INS_VRCP28SS: vrcp28ss */ 0, { 0 } }, { /* X86_VRCPPSYm, X86_INS_VRCPPS: vrcpps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCPPSYr, X86_INS_VRCPPS: vrcpps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCPPSm, X86_INS_VRCPPS: vrcpps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCPPSr, X86_INS_VRCPPS: vrcpps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRCPSSm, X86_INS_VRCPSS: vrcpss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VRCPSSm_Int, X86_INS_VRCPSS: vrcpss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VRCPSSr, X86_INS_VRCPSS: vrcpss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VRCPSSr_Int, X86_INS_VRCPSS: vrcpss */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rmbi, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rmbik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rmbikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rmi, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rmik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rmikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rri, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rrik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ128rrikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rmbi, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rmbik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rmbikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rmi, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rmik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rmikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rri, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rrik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZ256rrikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrmbi, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrmbik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrmbikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrmi, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrmik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrmikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrri, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrrib, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrribk, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrribkz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrrik, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPDZrrikz, X86_INS_VREDUCEPD: vreducepd */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rmbi, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rmbik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rmbikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rmi, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rmik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rmikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rri, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rrik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ128rrikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rmbi, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rmbik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rmbikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rmi, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rmik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rmikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rri, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rrik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZ256rrikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrmbi, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrmbik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrmbikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrmi, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrmik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrmikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrri, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrrib, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrribk, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrribkz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrrik, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCEPSZrrikz, X86_INS_VREDUCEPS: vreduceps */ 0, { 0 } }, { /* X86_VREDUCESDZrmi, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrmik, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrmikz, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrri, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrrib, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrribk, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrribkz, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrrik, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESDZrrikz, X86_INS_VREDUCESD: vreducesd */ 0, { 0 } }, { /* X86_VREDUCESSZrmi, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrmik, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrmikz, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrri, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrrib, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrribk, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrribkz, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrrik, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VREDUCESSZrrikz, X86_INS_VREDUCESS: vreducess */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rmbi, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rmbik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rmbikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rmi, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rmik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rmikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rri, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rrik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ128rrikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rmbi, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rmbik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rmbikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rmi, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rmik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rmikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rri, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rrik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZ256rrikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrmbi, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrmbik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrmbikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrmi, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrmik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrmikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrri, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrrib, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrribk, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrribkz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrrik, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPDZrrikz, X86_INS_VRNDSCALEPD: vrndscalepd */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rmbi, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rmbik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rmbikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rmi, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rmik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rmikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rri, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rrik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ128rrikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rmbi, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rmbik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rmbikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rmi, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rmik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rmikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rri, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rrik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZ256rrikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrmbi, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrmbik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrmbikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrmi, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrmik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrmikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrri, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrrib, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrribk, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrribkz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrrik, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALEPSZrrikz, X86_INS_VRNDSCALEPS: vrndscaleps */ 0, { 0 } }, { /* X86_VRNDSCALESDZm, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZm_Int, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZm_Intk, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZm_Intkz, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZr, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZr_Int, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZr_Intk, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZr_Intkz, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZrb_Int, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZrb_Intk, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESDZrb_Intkz, X86_INS_VRNDSCALESD: vrndscalesd */ 0, { 0 } }, { /* X86_VRNDSCALESSZm, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZm_Int, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZm_Intk, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZm_Intkz, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZr, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZr_Int, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZr_Intk, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZr_Intkz, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZrb_Int, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZrb_Intk, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VRNDSCALESSZrb_Intkz, X86_INS_VRNDSCALESS: vrndscaless */ 0, { 0 } }, { /* X86_VROUNDPDYm, X86_INS_VROUNDPD: vroundpd */ 0, { 0 } }, { /* X86_VROUNDPDYr, X86_INS_VROUNDPD: vroundpd */ 0, { 0 } }, { /* X86_VROUNDPDm, X86_INS_VROUNDPD: vroundpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDPDr, X86_INS_VROUNDPD: vroundpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDPSYm, X86_INS_VROUNDPS: vroundps */ 0, { 0 } }, { /* X86_VROUNDPSYr, X86_INS_VROUNDPS: vroundps */ 0, { 0 } }, { /* X86_VROUNDPSm, X86_INS_VROUNDPS: vroundps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDPSr, X86_INS_VROUNDPS: vroundps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDSDm, X86_INS_VROUNDSD: vroundsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDSDm_Int, X86_INS_VROUNDSD: vroundsd */ 0, { 0 } }, { /* X86_VROUNDSDr, X86_INS_VROUNDSD: vroundsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDSDr_Int, X86_INS_VROUNDSD: vroundsd $dst $src1 $src2 $src3 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDSSm, X86_INS_VROUNDSS: vroundss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDSSm_Int, X86_INS_VROUNDSS: vroundss */ 0, { 0 } }, { /* X86_VROUNDSSr, X86_INS_VROUNDSS: vroundss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VROUNDSSr_Int, X86_INS_VROUNDSS: vroundss $dst $src1 $src2 $src3 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VRSQRT14PDZ128m, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128mb, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128mbk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128mbkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128mk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128mkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128r, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128rk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ128rkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256m, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256mb, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256mbk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256mbkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256mk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256mkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256r, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256rk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZ256rkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZm, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZmb, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZmbk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZmbkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZmk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZmkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZr, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZrk, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PDZrkz, X86_INS_VRSQRT14PD: vrsqrt14pd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128m, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128mb, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128mbk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128mbkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128mk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128mkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128r, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128rk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ128rkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256m, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256mb, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256mbk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256mbkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256mk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256mkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256r, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256rk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZ256rkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZm, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZmb, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZmbk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZmbkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZmk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZmkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZr, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZrk, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14PSZrkz, X86_INS_VRSQRT14PS: vrsqrt14ps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRT14SDZrm, X86_INS_VRSQRT14SD: vrsqrt14sd */ 0, { 0 } }, { /* X86_VRSQRT14SDZrmk, X86_INS_VRSQRT14SD: vrsqrt14sd */ 0, { 0 } }, { /* X86_VRSQRT14SDZrmkz, X86_INS_VRSQRT14SD: vrsqrt14sd */ 0, { 0 } }, { /* X86_VRSQRT14SDZrr, X86_INS_VRSQRT14SD: vrsqrt14sd */ 0, { 0 } }, { /* X86_VRSQRT14SDZrrk, X86_INS_VRSQRT14SD: vrsqrt14sd */ 0, { 0 } }, { /* X86_VRSQRT14SDZrrkz, X86_INS_VRSQRT14SD: vrsqrt14sd */ 0, { 0 } }, { /* X86_VRSQRT14SSZrm, X86_INS_VRSQRT14SS: vrsqrt14ss */ 0, { 0 } }, { /* X86_VRSQRT14SSZrmk, X86_INS_VRSQRT14SS: vrsqrt14ss */ 0, { 0 } }, { /* X86_VRSQRT14SSZrmkz, X86_INS_VRSQRT14SS: vrsqrt14ss */ 0, { 0 } }, { /* X86_VRSQRT14SSZrr, X86_INS_VRSQRT14SS: vrsqrt14ss */ 0, { 0 } }, { /* X86_VRSQRT14SSZrrk, X86_INS_VRSQRT14SS: vrsqrt14ss */ 0, { 0 } }, { /* X86_VRSQRT14SSZrrkz, X86_INS_VRSQRT14SS: vrsqrt14ss */ 0, { 0 } }, { /* X86_VRSQRT28PDZm, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZmb, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZmbk, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZmbkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZmk, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZmkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZr, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZrb, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZrbk, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZrbkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZrk, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PDZrkz, X86_INS_VRSQRT28PD: vrsqrt28pd */ 0, { 0 } }, { /* X86_VRSQRT28PSZm, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZmb, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZmbk, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZmbkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZmk, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZmkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZr, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZrb, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZrbk, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZrbkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZrk, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28PSZrkz, X86_INS_VRSQRT28PS: vrsqrt28ps */ 0, { 0 } }, { /* X86_VRSQRT28SDZm, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZmk, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZmkz, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZr, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZrb, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZrbk, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZrbkz, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZrk, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SDZrkz, X86_INS_VRSQRT28SD: vrsqrt28sd */ 0, { 0 } }, { /* X86_VRSQRT28SSZm, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZmk, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZmkz, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZr, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZrb, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZrbk, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZrbkz, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZrk, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRT28SSZrkz, X86_INS_VRSQRT28SS: vrsqrt28ss */ 0, { 0 } }, { /* X86_VRSQRTPSYm, X86_INS_VRSQRTPS: vrsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRTPSYr, X86_INS_VRSQRTPS: vrsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRTPSm, X86_INS_VRSQRTPS: vrsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRTPSr, X86_INS_VRSQRTPS: vrsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VRSQRTSSm, X86_INS_VRSQRTSS: vrsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VRSQRTSSm_Int, X86_INS_VRSQRTSS: vrsqrtss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VRSQRTSSr, X86_INS_VRSQRTSS: vrsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VRSQRTSSr_Int, X86_INS_VRSQRTSS: vrsqrtss */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rm, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rmb, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rmbk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rmbkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rmk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rmkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rr, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rrk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ128rrkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rm, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rmb, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rmbk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rmbkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rmk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rmkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rr, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rrk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZ256rrkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrm, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrmb, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrmbk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrmbkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrmk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrmkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrr, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrrb, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrrbk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrrbkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrrk, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPDZrrkz, X86_INS_VSCALEFPD: vscalefpd */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rm, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rmb, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rmbk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rmbkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rmk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rmkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rr, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rrk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ128rrkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rm, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rmb, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rmbk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rmbkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rmk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rmkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rr, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rrk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZ256rrkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrm, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrmb, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrmbk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrmbkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrmk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrmkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrr, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrrb, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrrbk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrrbkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrrk, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFPSZrrkz, X86_INS_VSCALEFPS: vscalefps */ 0, { 0 } }, { /* X86_VSCALEFSDZrm, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrmk, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrmkz, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrr, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrrb_Int, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrrb_Intk, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrrb_Intkz, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrrk, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSDZrrkz, X86_INS_VSCALEFSD: vscalefsd */ 0, { 0 } }, { /* X86_VSCALEFSSZrm, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrmk, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrmkz, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrr, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrrb_Int, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrrb_Intk, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrrb_Intkz, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrrk, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCALEFSSZrrkz, X86_INS_VSCALEFSS: vscalefss */ 0, { 0 } }, { /* X86_VSCATTERDPDZ128mr, X86_INS_VSCATTERDPD: vscatterdpd */ 0, { 0 } }, { /* X86_VSCATTERDPDZ256mr, X86_INS_VSCATTERDPD: vscatterdpd */ 0, { 0 } }, { /* X86_VSCATTERDPDZmr, X86_INS_VSCATTERDPD: vscatterdpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSCATTERDPSZ128mr, X86_INS_VSCATTERDPS: vscatterdps */ 0, { 0 } }, { /* X86_VSCATTERDPSZ256mr, X86_INS_VSCATTERDPS: vscatterdps */ 0, { 0 } }, { /* X86_VSCATTERDPSZmr, X86_INS_VSCATTERDPS: vscatterdps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSCATTERPF0DPDm, X86_INS_VSCATTERPF0DPD: vscatterpf0dpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF0DPSm, X86_INS_VSCATTERPF0DPS: vscatterpf0dps */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF0QPDm, X86_INS_VSCATTERPF0QPD: vscatterpf0qpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF0QPSm, X86_INS_VSCATTERPF0QPS: vscatterpf0qps */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF1DPDm, X86_INS_VSCATTERPF1DPD: vscatterpf1dpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF1DPSm, X86_INS_VSCATTERPF1DPS: vscatterpf1dps */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF1QPDm, X86_INS_VSCATTERPF1QPD: vscatterpf1qpd */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERPF1QPSm, X86_INS_VSCATTERPF1QPS: vscatterpf1qps */ 0, { CS_AC_READ, 0 } }, { /* X86_VSCATTERQPDZ128mr, X86_INS_VSCATTERQPD: vscatterqpd */ 0, { 0 } }, { /* X86_VSCATTERQPDZ256mr, X86_INS_VSCATTERQPD: vscatterqpd */ 0, { 0 } }, { /* X86_VSCATTERQPDZmr, X86_INS_VSCATTERQPD: vscatterqpd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSCATTERQPSZ128mr, X86_INS_VSCATTERQPS: vscatterqps */ 0, { 0 } }, { /* X86_VSCATTERQPSZ256mr, X86_INS_VSCATTERQPS: vscatterqps */ 0, { 0 } }, { /* X86_VSCATTERQPSZmr, X86_INS_VSCATTERQPS: vscatterqps */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSHUFF32X4Z256rmbi, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rmbik, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rmbikz, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rmi, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rmik, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rmikz, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rri, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rrik, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Z256rrikz, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrmbi, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrmbik, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrmbikz, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrmi, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrmik, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrmikz, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrri, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrrik, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF32X4Zrrikz, X86_INS_VSHUFF32X4: vshuff32x4 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rmbi, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rmbik, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rmbikz, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rmi, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rmik, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rmikz, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rri, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rrik, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Z256rrikz, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrmbi, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrmbik, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrmbikz, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrmi, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrmik, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrmikz, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrri, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrrik, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFF64X2Zrrikz, X86_INS_VSHUFF64X2: vshuff64x2 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rmbi, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rmbik, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rmbikz, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rmi, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rmik, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rmikz, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rri, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rrik, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Z256rrikz, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrmbi, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrmbik, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrmbikz, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrmi, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrmik, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrmikz, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrri, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrrik, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI32X4Zrrikz, X86_INS_VSHUFI32X4: vshufi32x4 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rmbi, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rmbik, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rmbikz, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rmi, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rmik, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rmikz, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rri, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rrik, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Z256rrikz, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrmbi, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrmbik, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrmbikz, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrmi, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrmik, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrmikz, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrri, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrrik, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFI64X2Zrrikz, X86_INS_VSHUFI64X2: vshufi64x2 */ 0, { 0 } }, { /* X86_VSHUFPDYrmi, X86_INS_VSHUFPD: vshufpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPDYrri, X86_INS_VSHUFPD: vshufpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPDZ128rmbi, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rmbik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rmbikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rmi, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rmik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rmikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rri, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rrik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ128rrikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rmbi, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rmbik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rmbikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rmi, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rmik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rmikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rri, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rrik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZ256rrikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrmbi, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrmbik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrmbikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrmi, X86_INS_VSHUFPD: vshufpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPDZrmik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrmikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrri, X86_INS_VSHUFPD: vshufpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPDZrrik, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDZrrikz, X86_INS_VSHUFPD: vshufpd */ 0, { 0 } }, { /* X86_VSHUFPDrmi, X86_INS_VSHUFPD: vshufpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPDrri, X86_INS_VSHUFPD: vshufpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPSYrmi, X86_INS_VSHUFPS: vshufps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPSYrri, X86_INS_VSHUFPS: vshufps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPSZ128rmbi, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rmbik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rmbikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rmi, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rmik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rmikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rri, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rrik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ128rrikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rmbi, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rmbik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rmbikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rmi, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rmik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rmikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rri, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rrik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZ256rrikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrmbi, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrmbik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrmbikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrmi, X86_INS_VSHUFPS: vshufps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPSZrmik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrmikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrri, X86_INS_VSHUFPS: vshufps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPSZrrik, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSZrrikz, X86_INS_VSHUFPS: vshufps */ 0, { 0 } }, { /* X86_VSHUFPSrmi, X86_INS_VSHUFPS: vshufps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSHUFPSrri, X86_INS_VSHUFPS: vshufps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSQRTPDYm, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDYr, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128m, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128mb, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128mbk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128mbkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128mk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128mkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128r, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128rk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ128rkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256m, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256mb, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256mbk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256mbkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256mk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256mkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256r, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256rk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZ256rkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZm, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZmb, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZmbk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZmbkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZmk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZmkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZr, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZrb, X86_INS_VSQRTPD: vsqrtpd */ 0, { 0 } }, { /* X86_VSQRTPDZrbk, X86_INS_VSQRTPD: vsqrtpd */ 0, { 0 } }, { /* X86_VSQRTPDZrbkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { 0 } }, { /* X86_VSQRTPDZrk, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDZrkz, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDm, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPDr, X86_INS_VSQRTPD: vsqrtpd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSYm, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSYr, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128m, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128mb, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128mbk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128mbkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128mk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128mkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128r, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128rk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ128rkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256m, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256mb, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256mbk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256mbkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256mk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256mkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256r, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256rk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZ256rkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZm, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZmb, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZmbk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZmbkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZmk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZmkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZr, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZrb, X86_INS_VSQRTPS: vsqrtps */ 0, { 0 } }, { /* X86_VSQRTPSZrbk, X86_INS_VSQRTPS: vsqrtps */ 0, { 0 } }, { /* X86_VSQRTPSZrbkz, X86_INS_VSQRTPS: vsqrtps */ 0, { 0 } }, { /* X86_VSQRTPSZrk, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSZrkz, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSm, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTPSr, X86_INS_VSQRTPS: vsqrtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VSQRTSDZm, X86_INS_VSQRTSD: vsqrtsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSDZm_Int, X86_INS_VSQRTSD: vsqrtsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSQRTSDZm_Intk, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDZm_Intkz, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDZr, X86_INS_VSQRTSD: vsqrtsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSDZr_Int, X86_INS_VSQRTSD: vsqrtsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSDZr_Intk, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDZr_Intkz, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDZrb_Int, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDZrb_Intk, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDZrb_Intkz, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSDm, X86_INS_VSQRTSD: vsqrtsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSDm_Int, X86_INS_VSQRTSD: vsqrtsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSQRTSDr, X86_INS_VSQRTSD: vsqrtsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSDr_Int, X86_INS_VSQRTSD: vsqrtsd */ 0, { 0 } }, { /* X86_VSQRTSSZm, X86_INS_VSQRTSS: vsqrtss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSSZm_Int, X86_INS_VSQRTSS: vsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSQRTSSZm_Intk, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSZm_Intkz, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSZr, X86_INS_VSQRTSS: vsqrtss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSSZr_Int, X86_INS_VSQRTSS: vsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSSZr_Intk, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSZr_Intkz, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSZrb_Int, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSZrb_Intk, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSZrb_Intkz, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSQRTSSm, X86_INS_VSQRTSS: vsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSSm_Int, X86_INS_VSQRTSS: vsqrtss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSQRTSSr, X86_INS_VSQRTSS: vsqrtss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSQRTSSr_Int, X86_INS_VSQRTSS: vsqrtss */ 0, { 0 } }, { /* X86_VSTMXCSR, X86_INS_VSTMXCSR: vstmxcsr */ 0, { CS_AC_READ, 0 } }, { /* X86_VSUBPDYrm, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDYrr, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rm, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rmb, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rmbk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rmbkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rmk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rmkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rr, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rrk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ128rrkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rm, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rmb, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rmbk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rmbkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rmk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rmkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rr, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rrk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZ256rrkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrm, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrmb, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrmbk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrmbkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrmk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrmkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrr, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrrb, X86_INS_VSUBPD: vsubpd */ 0, { 0 } }, { /* X86_VSUBPDZrrbk, X86_INS_VSUBPD: vsubpd */ 0, { 0 } }, { /* X86_VSUBPDZrrbkz, X86_INS_VSUBPD: vsubpd */ 0, { 0 } }, { /* X86_VSUBPDZrrk, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDZrrkz, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDrm, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPDrr, X86_INS_VSUBPD: vsubpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSYrm, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSYrr, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rm, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rmb, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rmbk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rmbkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rmk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rmkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rr, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rrk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ128rrkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rm, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rmb, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rmbk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rmbkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rmk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rmkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rr, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rrk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZ256rrkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrm, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrmb, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrmbk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrmbkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrmk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrmkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrr, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrrb, X86_INS_VSUBPS: vsubps */ 0, { 0 } }, { /* X86_VSUBPSZrrbk, X86_INS_VSUBPS: vsubps */ 0, { 0 } }, { /* X86_VSUBPSZrrbkz, X86_INS_VSUBPS: vsubps */ 0, { 0 } }, { /* X86_VSUBPSZrrk, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSZrrkz, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSrm, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBPSrr, X86_INS_VSUBPS: vsubps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrm, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrm_Int, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrm_Intk, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrm_Intkz, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrr, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrr_Int, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrr_Intk, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrr_Intkz, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDZrrb_Int, X86_INS_VSUBSD: vsubsd */ 0, { 0 } }, { /* X86_VSUBSDZrrb_Intk, X86_INS_VSUBSD: vsubsd */ 0, { 0 } }, { /* X86_VSUBSDZrrb_Intkz, X86_INS_VSUBSD: vsubsd */ 0, { 0 } }, { /* X86_VSUBSDrm, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDrm_Int, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSUBSDrr, X86_INS_VSUBSD: vsubsd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSDrr_Int, X86_INS_VSUBSD: vsubsd $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrm, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrm_Int, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrm_Intk, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrm_Intkz, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrr, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrr_Int, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrr_Intk, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrr_Intkz, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSZrrb_Int, X86_INS_VSUBSS: vsubss */ 0, { 0 } }, { /* X86_VSUBSSZrrb_Intk, X86_INS_VSUBSS: vsubss */ 0, { 0 } }, { /* X86_VSUBSSZrrb_Intkz, X86_INS_VSUBSS: vsubss */ 0, { 0 } }, { /* X86_VSUBSSrm, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSrm_Int, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_VSUBSSrr, X86_INS_VSUBSS: vsubss */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VSUBSSrr_Int, X86_INS_VSUBSS: vsubss $dst $src1 $src2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPDYrm, X86_INS_VTESTPD: vtestpd */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPDYrr, X86_INS_VTESTPD: vtestpd */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPDrm, X86_INS_VTESTPD: vtestpd */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPDrr, X86_INS_VTESTPD: vtestpd */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPSYrm, X86_INS_VTESTPS: vtestps */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPSYrr, X86_INS_VTESTPS: vtestps */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPSrm, X86_INS_VTESTPS: vtestps */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VTESTPSrr, X86_INS_VTESTPS: vtestps */ X86_EFLAGS_RESET_0F | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISDZrm, X86_INS_VUCOMISD: vucomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISDZrm_Int, X86_INS_VUCOMISD: vucomisd */ 0, { 0 } }, { /* X86_VUCOMISDZrr, X86_INS_VUCOMISD: vucomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISDZrr_Int, X86_INS_VUCOMISD: vucomisd */ 0, { 0 } }, { /* X86_VUCOMISDZrrb, X86_INS_VUCOMISD: vucomisd */ 0, { 0 } }, { /* X86_VUCOMISDrm, X86_INS_VUCOMISD: vucomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISDrm_Int, X86_INS_VUCOMISD: vucomisd */ 0, { 0 } }, { /* X86_VUCOMISDrr, X86_INS_VUCOMISD: vucomisd */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISDrr_Int, X86_INS_VUCOMISD: vucomisd */ 0, { 0 } }, { /* X86_VUCOMISSZrm, X86_INS_VUCOMISS: vucomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISSZrm_Int, X86_INS_VUCOMISS: vucomiss */ 0, { 0 } }, { /* X86_VUCOMISSZrr, X86_INS_VUCOMISS: vucomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISSZrr_Int, X86_INS_VUCOMISS: vucomiss */ 0, { 0 } }, { /* X86_VUCOMISSZrrb, X86_INS_VUCOMISS: vucomiss */ 0, { 0 } }, { /* X86_VUCOMISSrm, X86_INS_VUCOMISS: vucomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISSrm_Int, X86_INS_VUCOMISS: vucomiss */ 0, { 0 } }, { /* X86_VUCOMISSrr, X86_INS_VUCOMISS: vucomiss */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUCOMISSrr_Int, X86_INS_VUCOMISS: vucomiss */ 0, { 0 } }, { /* X86_VUNPCKHPDYrm, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPDYrr, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPDZ128rm, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rmb, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rmbk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rmbkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rmk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rmkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rr, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rrk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ128rrkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rm, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rmb, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rmbk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rmbkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rmk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rmkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rr, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rrk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZ256rrkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrm, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPDZrmb, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrmbk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrmbkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrmk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrmkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrr, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPDZrrk, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDZrrkz, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { 0 } }, { /* X86_VUNPCKHPDrm, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPDrr, X86_INS_VUNPCKHPD: vunpckhpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPSYrm, X86_INS_VUNPCKHPS: vunpckhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPSYrr, X86_INS_VUNPCKHPS: vunpckhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPSZ128rm, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rmb, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rmbk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rmbkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rmk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rmkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rr, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rrk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ128rrkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rm, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rmb, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rmbk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rmbkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rmk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rmkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rr, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rrk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZ256rrkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrm, X86_INS_VUNPCKHPS: vunpckhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPSZrmb, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrmbk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrmbkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrmk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrmkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrr, X86_INS_VUNPCKHPS: vunpckhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPSZrrk, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSZrrkz, X86_INS_VUNPCKHPS: vunpckhps */ 0, { 0 } }, { /* X86_VUNPCKHPSrm, X86_INS_VUNPCKHPS: vunpckhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKHPSrr, X86_INS_VUNPCKHPS: vunpckhps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPDYrm, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPDYrr, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPDZ128rm, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rmb, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rmbk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rmbkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rmk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rmkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rr, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rrk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ128rrkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rm, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rmb, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rmbk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rmbkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rmk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rmkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rr, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rrk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZ256rrkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrm, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPDZrmb, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrmbk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrmbkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrmk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrmkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrr, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPDZrrk, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDZrrkz, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { 0 } }, { /* X86_VUNPCKLPDrm, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPDrr, X86_INS_VUNPCKLPD: vunpcklpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPSYrm, X86_INS_VUNPCKLPS: vunpcklps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPSYrr, X86_INS_VUNPCKLPS: vunpcklps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPSZ128rm, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rmb, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rmbk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rmbkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rmk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rmkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rr, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rrk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ128rrkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rm, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rmb, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rmbk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rmbkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rmk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rmkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rr, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rrk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZ256rrkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrm, X86_INS_VUNPCKLPS: vunpcklps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPSZrmb, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrmbk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrmbkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrmk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrmkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrr, X86_INS_VUNPCKLPS: vunpcklps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPSZrrk, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSZrrkz, X86_INS_VUNPCKLPS: vunpcklps */ 0, { 0 } }, { /* X86_VUNPCKLPSrm, X86_INS_VUNPCKLPS: vunpcklps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VUNPCKLPSrr, X86_INS_VUNPCKLPS: vunpcklps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPDYrm, X86_INS_VXORPD: vxorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPDYrr, X86_INS_VXORPD: vxorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPDZ128rm, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rmb, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rmbk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rmbkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rmk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rmkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rr, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rrk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ128rrkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rm, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rmb, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rmbk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rmbkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rmk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rmkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rr, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rrk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZ256rrkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrm, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrmb, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrmbk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrmbkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrmk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrmkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrr, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrrk, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDZrrkz, X86_INS_VXORPD: vxorpd */ 0, { 0 } }, { /* X86_VXORPDrm, X86_INS_VXORPD: vxorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPDrr, X86_INS_VXORPD: vxorpd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPSYrm, X86_INS_VXORPS: vxorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPSYrr, X86_INS_VXORPS: vxorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPSZ128rm, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rmb, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rmbk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rmbkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rmk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rmkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rr, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rrk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ128rrkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rm, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rmb, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rmbk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rmbkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rmk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rmkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rr, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rrk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZ256rrkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrm, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrmb, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrmbk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrmbkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrmk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrmkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrr, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrrk, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSZrrkz, X86_INS_VXORPS: vxorps */ 0, { 0 } }, { /* X86_VXORPSrm, X86_INS_VXORPS: vxorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VXORPSrr, X86_INS_VXORPS: vxorps */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VZEROALL, X86_INS_VZEROALL: vzeroall */ 0, { 0 } }, { /* X86_VZEROUPPER, X86_INS_VZEROUPPER: vzeroupper */ 0, { 0 } }, { /* X86_WAIT, X86_INS_WAIT: wait */ X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C1 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { 0 } }, { /* X86_WBINVD, X86_INS_WBINVD: wbinvd */ 0, { 0 } }, { /* X86_WBNOINVD, X86_INS_WBNOINVD: wbnoinvd */ 0, { 0 } }, { /* X86_WRFSBASE, X86_INS_WRFSBASE: wrfsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRFSBASE64, X86_INS_WRFSBASE: wrfsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRGSBASE, X86_INS_WRGSBASE: wrgsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRGSBASE64, X86_INS_WRGSBASE: wrgsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRMSR, X86_INS_WRMSR: wrmsr */ 0, { 0 } }, { /* X86_WRPKRUr, X86_INS_WRPKRU: wrpkru */ 0, { 0 } }, { /* X86_WRSSD, X86_INS_WRSSD: wrssd */ 0, { 0 } }, { /* X86_WRSSQ, X86_INS_WRSSQ: wrssq */ 0, { 0 } }, { /* X86_WRUSSD, X86_INS_WRUSSD: wrussd */ 0, { 0 } }, { /* X86_WRUSSQ, X86_INS_WRUSSQ: wrussq */ 0, { 0 } }, { /* X86_XABORT, X86_INS_XABORT: xabort */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_XACQUIRE_PREFIX, X86_INS_XACQUIRE: xacquire */ 0, { 0 } }, { /* X86_XADD16rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD16rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD32rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD32rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD64rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD64rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD8rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD8rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XBEGIN_2, X86_INS_XBEGIN: xbegin */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_XBEGIN_4, X86_INS_XBEGIN: xbegin */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_XCHG16ar, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG16rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG16rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG32ar, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG32rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG32rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG64ar, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG64rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG64rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG8rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG8rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCH_F, X86_INS_FXCH: fxch */ X86_FPU_FLAGS_RESET_C1 | X86_FPU_FLAGS_UNDEFINED_C0 | X86_FPU_FLAGS_UNDEFINED_C2 | X86_FPU_FLAGS_UNDEFINED_C3, { CS_AC_READ, 0 } }, { /* X86_XCRYPTCBC, X86_INS_XCRYPTCBC: xcryptcbc */ 0, { 0 } }, { /* X86_XCRYPTCFB, X86_INS_XCRYPTCFB: xcryptcfb */ 0, { 0 } }, { /* X86_XCRYPTCTR, X86_INS_XCRYPTCTR: xcryptctr */ 0, { 0 } }, { /* X86_XCRYPTECB, X86_INS_XCRYPTECB: xcryptecb */ 0, { 0 } }, { /* X86_XCRYPTOFB, X86_INS_XCRYPTOFB: xcryptofb */ 0, { 0 } }, { /* X86_XEND, X86_INS_XEND: xend */ 0, { 0 } }, { /* X86_XGETBV, X86_INS_XGETBV: xgetbv */ 0, { 0 } }, { /* X86_XLAT, X86_INS_XLATB: xlatb */ 0, { 0 } }, { /* X86_XOR16i16, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16mi, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16mi8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR16ri, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16ri8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR16rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR16rr_REV, X86_INS_XOR: xor{w} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32i32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32mi, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32mi8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32ri, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32ri8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32rr_REV, X86_INS_XOR: xor{l} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64i32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64mi32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64mi8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64ri32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64ri8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64rr_REV, X86_INS_XOR: xor{q} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8i8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8mi, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8mi8, X86_INS_XOR: xor{b} $dst $src */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8ri, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8ri8, X86_INS_XOR: xor{b} $src1 $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8rr_REV, X86_INS_XOR: xor{b} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XORPDrm, X86_INS_XORPD: xorpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XORPDrr, X86_INS_XORPD: xorpd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XORPSrm, X86_INS_XORPS: xorps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XORPSrr, X86_INS_XORPS: xorps */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XRELEASE_PREFIX, X86_INS_XRELEASE: xrelease */ 0, { 0 } }, { /* X86_XRSTOR, X86_INS_XRSTOR: xrstor */ 0, { CS_AC_READ, 0 } }, { /* X86_XRSTOR64, X86_INS_XRSTOR64: xrstor64 */ 0, { CS_AC_READ, 0 } }, { /* X86_XRSTORS, X86_INS_XRSTORS: xrstors */ 0, { CS_AC_READ, 0 } }, { /* X86_XRSTORS64, X86_INS_XRSTORS64: xrstors64 */ 0, { CS_AC_READ, 0 } }, { /* X86_XSAVE, X86_INS_XSAVE: xsave */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVE64, X86_INS_XSAVE64: xsave64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEC, X86_INS_XSAVEC: xsavec */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEC64, X86_INS_XSAVEC64: xsavec64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEOPT, X86_INS_XSAVEOPT: xsaveopt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEOPT64, X86_INS_XSAVEOPT64: xsaveopt64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVES, X86_INS_XSAVES: xsaves */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVES64, X86_INS_XSAVES64: xsaves64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSETBV, X86_INS_XSETBV: xsetbv */ 0, { 0 } }, { /* X86_XSHA1, X86_INS_XSHA1: xsha1 */ 0, { 0 } }, { /* X86_XSHA256, X86_INS_XSHA256: xsha256 */ 0, { 0 } }, { /* X86_XSTORE, X86_INS_XSTORE: xstore */ 0, { 0 } }, { /* X86_XTEST, X86_INS_XTEST: xtest */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_AF, { 0 } }, capstone-sys-0.15.0/capstone/arch/X86/X86MappingInsnOp_reduce.inc000064400000000000000000007072340072674642500225740ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { /* X86_AAA, X86_INS_AAA: aaa */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_AAD8i8, X86_INS_AAD: aad */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_IGNORE, 0 } }, { /* X86_AAM8i8, X86_INS_AAM: aam */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_IGNORE, 0 } }, { /* X86_AAS, X86_INS_AAS: aas */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_ADC16i16, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16mi, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16mi8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC16ri, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16ri8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC16rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC16rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC16rr_REV, X86_INS_ADC: adc{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32i32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32mi, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32mi8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32ri, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32ri8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC32rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC32rr_REV, X86_INS_ADC: adc{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64i32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64mi32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64mi8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64ri32, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64ri8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC64rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC64rr_REV, X86_INS_ADC: adc{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8i8, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8mi, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8mi8, X86_INS_ADC: adc{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8mr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8ri, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8ri8, X86_INS_ADC: adc{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADC8rm, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8rr, X86_INS_ADC: adc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADC8rr_REV, X86_INS_ADC: adc{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX32rm, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX32rr, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX64rm, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADCX64rr, X86_INS_ADCX: adcx */ X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16i16, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16mi, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16mi8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16ri, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16ri8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD16rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD16rr_REV, X86_INS_ADD: add{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32i32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32mi, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32mi8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32ri, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32ri8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD32rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD32rr_REV, X86_INS_ADD: add{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64i32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64mi32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64mi8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64ri32, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64ri8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD64rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD64rr_REV, X86_INS_ADD: add{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8i8, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8mi, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8mi8, X86_INS_ADD: add{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8mr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8ri, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8ri8, X86_INS_ADD: add{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ADD8rm, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8rr, X86_INS_ADD: add */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADD8rr_REV, X86_INS_ADD: add{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX32rm, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX32rr, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX64rm, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ADOX64rr, X86_INS_ADOX: adox */ X86_EFLAGS_MODIFY_OF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16i16, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16mi, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16mi8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16ri, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16ri8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND16rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND16rr_REV, X86_INS_AND: and{w} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32i32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32mi, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32mi8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32ri, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32ri8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND32rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND32rr_REV, X86_INS_AND: and{l} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64i32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64mi32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64mi8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64ri32, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64ri8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND64rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND64rr_REV, X86_INS_AND: and{q} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8i8, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8mi, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8mi8, X86_INS_AND: and{b} $dst $src */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8mr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8ri, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8ri8, X86_INS_AND: and{b} $src1 $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_AND8rm, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8rr, X86_INS_AND: and */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_AND8rr_REV, X86_INS_AND: and{b} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ANDN32rm, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDN32rr, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDN64rm, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ANDN64rr, X86_INS_ANDN: andn */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_CF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ARPL16mr, X86_INS_ARPL: arpl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ARPL16rr, X86_INS_ARPL: arpl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BEXTR32rm, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTR32rr, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTR64rm, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTR64rr, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BEXTRI32mi, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BEXTRI32ri, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BEXTRI64mi, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BEXTRI64ri, X86_INS_BEXTR: bextr */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_TF | X86_EFLAGS_RESET_IF | X86_EFLAGS_RESET_DF | X86_EFLAGS_RESET_NT | X86_EFLAGS_RESET_RF, { 0 }, }, { /* X86_BLCFILL32rm, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCFILL32rr, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCFILL64rm, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCFILL64rr, X86_INS_BLCFILL: blcfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI32rm, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI32rr, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI64rm, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCI64rr, X86_INS_BLCI: blci */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC32rm, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC32rr, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC64rm, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCIC64rr, X86_INS_BLCIC: blcic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK32rm, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK32rr, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK64rm, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCMSK64rr, X86_INS_BLCMSK: blcmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS32rm, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS32rr, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS64rm, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLCS64rr, X86_INS_BLCS: blcs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL32rm, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL32rr, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL64rm, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSFILL64rr, X86_INS_BLSFILL: blsfill */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI32rm, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI32rr, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI64rm, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSI64rr, X86_INS_BLSI: blsi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC32rm, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC32rr, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC64rm, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSIC64rr, X86_INS_BLSIC: blsic */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK32rm, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK32rr, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK64rm, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSMSK64rr, X86_INS_BLSMSK: blsmsk */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR32rm, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR32rr, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR64rm, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BLSR64rr, X86_INS_BLSR: blsr */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BOUNDS16rm, X86_INS_BOUND: bound */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BOUNDS32rm, X86_INS_BOUND: bound */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF16rm, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF16rr, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF32rm, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF32rr, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF64rm, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSF64rr, X86_INS_BSF: bsf */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR16rm, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR16rr, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR32rm, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR32rr, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR64rm, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSR64rr, X86_INS_BSR: bsr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BSWAP16r_BAD, X86_INS_BSWAP: bswap */ 0, { 0 } }, { /* X86_BSWAP32r, X86_INS_BSWAP: bswap */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_BSWAP64r, X86_INS_BSWAP: bswap */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_BT16mi8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT16mr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT16ri8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT16rr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT32mi8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT32mr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT32ri8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT32rr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT64mi8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT64mr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BT64ri8, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_BT64rr, X86_INS_BT: bt */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BTC16mi8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC16mr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC16ri8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC16rr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC32mi8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC32mr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC32ri8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC32rr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC64mi8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC64mr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTC64ri8, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTC64rr, X86_INS_BTC: btc */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR16mi8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR16mr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR16ri8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR16rr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR32mi8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR32mr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR32ri8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR32rr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR64mi8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR64mr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTR64ri8, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTR64rr, X86_INS_BTR: btr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS16mi8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS16mr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS16ri8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS16rr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS32mi8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS32mr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS32ri8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS32rr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS64mi8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS64mr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BTS64ri8, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_BTS64rr, X86_INS_BTS: bts */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_BZHI32rm, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BZHI32rr, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BZHI64rm, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_BZHI64rr, X86_INS_BZHI: bzhi */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_RESET_OF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CALL16m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL16m_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL16r, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL16r_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL32m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_CALL32m_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL32r, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALL32r_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL64m, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALL64m_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALL64pcrel32, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALL64r, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALL64r_NT, X86_INS_CALL: call */ 0, { 0 } }, { /* X86_CALLpcrel16, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CALLpcrel32, X86_INS_CALL: call */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_CBW, X86_INS_CBW: cbw */ 0, { 0 } }, { /* X86_CDQ, X86_INS_CDQ: cdq */ 0, { 0 } }, { /* X86_CDQE, X86_INS_CDQE: cdqe */ 0, { 0 } }, { /* X86_CLAC, X86_INS_CLAC: clac */ X86_EFLAGS_RESET_AC, { 0 } }, { /* X86_CLC, X86_INS_CLC: clc */ X86_EFLAGS_RESET_CF, { 0 } }, { /* X86_CLD, X86_INS_CLD: cld */ X86_EFLAGS_RESET_DF, { 0 } }, { /* X86_CLDEMOTE, X86_INS_CLDEMOTE: cldemote */ 0, { 0 } }, { /* X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT: clflushopt */ 0, { CS_AC_READ, 0 } }, { /* X86_CLGI, X86_INS_CLGI: clgi */ 0, { 0 } }, { /* X86_CLI, X86_INS_CLI: cli */ X86_EFLAGS_RESET_IF, { 0 } }, { /* X86_CLRSSBSY, X86_INS_CLRSSBSY: clrssbsy */ 0, { 0 } }, { /* X86_CLTS, X86_INS_CLTS: clts */ 0, { 0 } }, { /* X86_CLWB, X86_INS_CLWB: clwb */ 0, { CS_AC_READ, 0 } }, { /* X86_CLZEROr, X86_INS_CLZERO: clzero */ 0, { 0 } }, { /* X86_CMC, X86_INS_CMC: cmc */ X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_CMOVA16rm, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA16rr, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA32rm, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA32rr, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA64rm, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVA64rr, X86_INS_CMOVA: cmova */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE16rm, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE16rr, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE32rm, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE32rr, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE64rm, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVAE64rr, X86_INS_CMOVAE: cmovae */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB16rm, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB16rr, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB32rm, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB32rr, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB64rm, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVB64rr, X86_INS_CMOVB: cmovb */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE16rm, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE16rr, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE32rm, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE32rr, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE64rm, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVBE64rr, X86_INS_CMOVBE: cmovbe */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE16rm, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE16rr, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE32rm, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE32rr, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE64rm, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVE64rr, X86_INS_CMOVE: cmove */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG16rm, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG16rr, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG32rm, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG32rr, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG64rm, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVG64rr, X86_INS_CMOVG: cmovg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE16rm, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE16rr, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE32rm, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE32rr, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE64rm, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVGE64rr, X86_INS_CMOVGE: cmovge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL16rm, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL16rr, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL32rm, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL32rr, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL64rm, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVL64rr, X86_INS_CMOVL: cmovl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE16rm, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE16rr, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE32rm, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE32rr, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE64rm, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVLE64rr, X86_INS_CMOVLE: cmovle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE16rm, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE16rr, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE32rm, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE32rr, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE64rm, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNE64rr, X86_INS_CMOVNE: cmovne */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO16rm, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO16rr, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO32rm, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO32rr, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO64rm, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNO64rr, X86_INS_CMOVNO: cmovno */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP16rm, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP16rr, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP32rm, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP32rr, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP64rm, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNP64rr, X86_INS_CMOVNP: cmovnp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS16rm, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS16rr, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS32rm, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS32rr, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS64rm, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVNS64rr, X86_INS_CMOVNS: cmovns */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO16rm, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO16rr, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO32rm, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO32rr, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO64rm, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVO64rr, X86_INS_CMOVO: cmovo */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP16rm, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP16rr, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP32rm, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP32rr, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP64rm, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVP64rr, X86_INS_CMOVP: cmovp */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS16rm, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS16rr, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS32rm, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS32rr, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS64rm, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMOVS64rr, X86_INS_CMOVS: cmovs */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMP16i16, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16mi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16mi8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP16ri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16ri8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP16rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP16rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP16rr_REV, X86_INS_CMP: cmp{w} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32i32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32mi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32mi8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32ri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32ri8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP32rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP32rr_REV, X86_INS_CMP: cmp{l} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64i32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64mi32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64mi8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64ri32, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64ri8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP64rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP64rr_REV, X86_INS_CMP: cmp{q} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8i8, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8mi, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8mi8, X86_INS_CMP: cmp{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8mr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8ri, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8ri8, X86_INS_CMP: cmp{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_CMP8rm, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8rr, X86_INS_CMP: cmp */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMP8rr_REV, X86_INS_CMP: cmp{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPSB, X86_INS_CMPSB: cmpsb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPSL, X86_INS_CMPSD: cmpsd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_CMPSQ, X86_INS_CMPSQ: cmpsq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPSW, X86_INS_CMPSW: cmpsw */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG16B, X86_INS_CMPXCHG16B: cmpxchg16b */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_CMPXCHG16rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG16rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPXCHG32rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG32rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPXCHG64rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG64rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CMPXCHG8B, X86_INS_CMPXCHG8B: cmpxchg8b */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_CMPXCHG8rm, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_CMPXCHG8rr, X86_INS_CMPXCHG: cmpxchg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_CPUID, X86_INS_CPUID: cpuid */ 0, { 0 } }, { /* X86_CQO, X86_INS_CQO: cqo */ 0, { 0 } }, { /* X86_CWD, X86_INS_CWD: cwd */ 0, { 0 } }, { /* X86_CWDE, X86_INS_CWDE: cwde */ 0, { 0 } }, { /* X86_DAA, X86_INS_DAA: daa */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_DAS, X86_INS_DAS: das */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_DATA16_PREFIX, X86_INS_DATA16: data16 */ 0, { 0 } }, { /* X86_DEC16m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC16r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC16r_alt, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC32m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC32r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC32r_alt, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC64m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC64r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC8m, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DEC8r, X86_INS_DEC: dec */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_DIV16m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV16r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV32m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV32r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV64m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV64r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV8m, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_DIV8r, X86_INS_DIV: div */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_ENDBR32, X86_INS_ENDBR32: endbr32 */ 0, { 0 } }, { /* X86_ENDBR64, X86_INS_ENDBR64: endbr64 */ 0, { 0 } }, { /* X86_ENTER, X86_INS_ENTER: enter */ 0, { CS_AC_IGNORE, CS_AC_IGNORE, 0 } }, { /* X86_FARCALL16i, X86_INS_LCALL: lcall{w} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARCALL16m, X86_INS_LCALL: lcall */ 0, { CS_AC_READ, 0 } }, { /* X86_FARCALL32i, X86_INS_LCALL: lcall{l} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARCALL32m, X86_INS_CALL: call */ 0, { CS_AC_READ, 0 } }, { /* X86_FARCALL64, X86_INS_LCALL: lcall */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARJMP16i, X86_INS_LJMP: ljmp{w} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARJMP16m, X86_INS_LJMP: ljmp{w} {*}$dst */ 0, { CS_AC_READ, 0 } }, { /* X86_FARJMP32i, X86_INS_LJMP: ljmp{l} $seg : $off */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FARJMP32m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_FARJMP64, X86_INS_LJMP: ljmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_FSETPM, X86_INS_FSETPM: fsetpm */ 0, { 0 } }, { /* X86_GETSEC, X86_INS_GETSEC: getsec */ 0, { 0 } }, { /* X86_HLT, X86_INS_HLT: hlt */ 0, { 0 } }, { /* X86_IDIV16m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV16r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV32m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV32r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV64m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV64r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV8m, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IDIV8r, X86_INS_IDIV: idiv */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_CF, { CS_AC_READ, 0 } }, { /* X86_IMUL16m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL16r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL16rm, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL16rmi, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL16rmi8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL16rr, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL16rri, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL16rri8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL32r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL32rm, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL32rmi, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32rmi8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32rr, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL32rri, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL32rri8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL64r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL64rm, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL64rmi32, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64rmi8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64rr, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IMUL64rri32, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL64rri8, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_IMUL8m, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IMUL8r, X86_INS_IMUL: imul */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF, { CS_AC_READ, 0 } }, { /* X86_IN16ri, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_IN16rr, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IN32ri, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_IN32rr, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_IN8ri, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_IN8rr, X86_INS_IN: in */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_INC16m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC16r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC16r_alt, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC32m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC32r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC32r_alt, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC64m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC64r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC8m, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INC8r, X86_INS_INC: inc */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_INCSSPD, X86_INS_INCSSPD: incsspd */ 0, { 0 } }, { /* X86_INCSSPQ, X86_INS_INCSSPQ: incsspq */ 0, { 0 } }, { /* X86_INSB, X86_INS_INSB: insb */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_INSL, X86_INS_INSD: insd */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_INSW, X86_INS_INSW: insw */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_INT, X86_INS_INT: int */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { CS_AC_IGNORE, 0 } }, { /* X86_INT1, X86_INS_INT1: int1 */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_INT3, X86_INS_INT3: int3 */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_INTO, X86_INS_INTO: into */ X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_INVD, X86_INS_INVD: invd */ 0, { 0 } }, { /* X86_INVEPT32, X86_INS_INVEPT: invept */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVEPT64, X86_INS_INVEPT: invept */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVLPG, X86_INS_INVLPG: invlpg */ 0, { CS_AC_READ, 0 } }, { /* X86_INVLPGA32, X86_INS_INVLPGA: invlpga */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVLPGA64, X86_INS_INVLPGA: invlpga */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVPCID32, X86_INS_INVPCID: invpcid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVPCID64, X86_INS_INVPCID: invpcid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVVPID32, X86_INS_INVVPID: invvpid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_INVVPID64, X86_INS_INVVPID: invvpid */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_IRET16, X86_INS_IRET: iret */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_IRET32, X86_INS_IRETD: iretd */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_IRET64, X86_INS_IRETQ: iretq */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_JAE_1, X86_INS_JAE: jae */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JAE_2, X86_INS_JAE: jae $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JAE_4, X86_INS_JAE: jae $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JA_1, X86_INS_JA: ja */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JA_2, X86_INS_JA: ja $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JA_4, X86_INS_JA: ja $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JBE_1, X86_INS_JBE: jbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JBE_2, X86_INS_JBE: jbe $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JBE_4, X86_INS_JBE: jbe $dst */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JB_1, X86_INS_JB: jb */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JB_2, X86_INS_JB: jb $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JB_4, X86_INS_JB: jb $dst */ X86_EFLAGS_TEST_CF, { CS_AC_IGNORE, 0 } }, { /* X86_JCXZ, X86_INS_JCXZ: jcxz */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JECXZ, X86_INS_JECXZ: jecxz */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JE_1, X86_INS_JE: je */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JE_2, X86_INS_JE: je $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JE_4, X86_INS_JE: je $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JGE_1, X86_INS_JGE: jge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JGE_2, X86_INS_JGE: jge $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JGE_4, X86_INS_JGE: jge $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JG_1, X86_INS_JG: jg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JG_2, X86_INS_JG: jg $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JG_4, X86_INS_JG: jg $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JLE_1, X86_INS_JLE: jle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JLE_2, X86_INS_JLE: jle $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JLE_4, X86_INS_JLE: jle $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JL_1, X86_INS_JL: jl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JL_2, X86_INS_JL: jl $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JL_4, X86_INS_JL: jl $dst */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JMP16m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP16m_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP16r, X86_INS_JMP: jmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP16r_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP32m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP32m_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP32r, X86_INS_JMP: jmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP32r_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP64m, X86_INS_JMP: jmp */ 0, { CS_AC_READ, 0 } }, { /* X86_JMP64m_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP64r, X86_INS_JMP: jmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP64r_NT, X86_INS_JMP: jmp */ 0, { 0 } }, { /* X86_JMP_1, X86_INS_JMP: jmp */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP_2, X86_INS_JMP: jmp $dst */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JMP_4, X86_INS_JMP: jmp $dst */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JNE_1, X86_INS_JNE: jne */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JNE_2, X86_INS_JNE: jne $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JNE_4, X86_INS_JNE: jne $dst */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_JNO_1, X86_INS_JNO: jno */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JNO_2, X86_INS_JNO: jno $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JNO_4, X86_INS_JNO: jno $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JNP_1, X86_INS_JNP: jnp */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JNP_2, X86_INS_JNP: jnp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JNP_4, X86_INS_JNP: jnp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JNS_1, X86_INS_JNS: jns */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JNS_2, X86_INS_JNS: jns $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JNS_4, X86_INS_JNS: jns $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JO_1, X86_INS_JO: jo */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JO_2, X86_INS_JO: jo $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JO_4, X86_INS_JO: jo $dst */ X86_EFLAGS_TEST_OF, { CS_AC_IGNORE, 0 } }, { /* X86_JP_1, X86_INS_JP: jp */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JP_2, X86_INS_JP: jp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JP_4, X86_INS_JP: jp $dst */ X86_EFLAGS_TEST_PF, { CS_AC_IGNORE, 0 } }, { /* X86_JRCXZ, X86_INS_JRCXZ: jrcxz */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_JS_1, X86_INS_JS: js */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JS_2, X86_INS_JS: js $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_JS_4, X86_INS_JS: js $dst */ X86_EFLAGS_TEST_SF, { CS_AC_IGNORE, 0 } }, { /* X86_LAHF, X86_INS_LAHF: lahf */ 0, { 0 } }, { /* X86_LAR16rm, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR16rr, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR32rm, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR32rr, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR64rm, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LAR64rr, X86_INS_LAR: lar */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LDS16rm, X86_INS_LDS: lds */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LDS32rm, X86_INS_LDS: lds */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LEA16r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_LEA32r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_LEA64_32r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_LEA64r, X86_INS_LEA: lea */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_LEAVE, X86_INS_LEAVE: leave */ 0, { 0 } }, { /* X86_LEAVE64, X86_INS_LEAVE: leave */ 0, { 0 } }, { /* X86_LES16rm, X86_INS_LES: les */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LES32rm, X86_INS_LES: les */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LFS16rm, X86_INS_LFS: lfs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LFS32rm, X86_INS_LFS: lfs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LFS64rm, X86_INS_LFS: lfs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LGDT16m, X86_INS_LGDT: lgdt */ 0, { CS_AC_READ, 0 } }, { /* X86_LGDT32m, X86_INS_LGDT: lgdt */ 0, { CS_AC_READ, 0 } }, { /* X86_LGDT64m, X86_INS_LGDT: lgdt */ 0, { CS_AC_READ, 0 } }, { /* X86_LGS16rm, X86_INS_LGS: lgs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LGS32rm, X86_INS_LGS: lgs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LGS64rm, X86_INS_LGS: lgs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LIDT16m, X86_INS_LIDT: lidt */ 0, { CS_AC_READ, 0 } }, { /* X86_LIDT32m, X86_INS_LIDT: lidt */ 0, { CS_AC_READ, 0 } }, { /* X86_LIDT64m, X86_INS_LIDT: lidt */ 0, { CS_AC_READ, 0 } }, { /* X86_LLDT16m, X86_INS_LLDT: lldt */ 0, { CS_AC_READ, 0 } }, { /* X86_LLDT16r, X86_INS_LLDT: lldt */ 0, { CS_AC_READ, 0 } }, { /* X86_LLWPCB, X86_INS_LLWPCB: llwpcb */ 0, { 0 } }, { /* X86_LLWPCB64, X86_INS_LLWPCB: llwpcb */ 0, { 0 } }, { /* X86_LMSW16m, X86_INS_LMSW: lmsw */ 0, { CS_AC_READ, 0 } }, { /* X86_LMSW16r, X86_INS_LMSW: lmsw */ 0, { CS_AC_READ, 0 } }, { /* X86_LOCK_PREFIX, X86_INS_LOCK: lock */ 0, { 0 } }, { /* X86_LODSB, X86_INS_LODSB: lodsb */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LODSL, X86_INS_LODSD: lodsd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LODSQ, X86_INS_LODSQ: lodsq */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LODSW, X86_INS_LODSW: lodsw */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LOOP, X86_INS_LOOP: loop */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LOOPE, X86_INS_LOOPE: loope */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_LOOPNE, X86_INS_LOOPNE: loopne */ X86_EFLAGS_TEST_ZF, { CS_AC_IGNORE, 0 } }, { /* X86_LRETIL, X86_INS_RETF: retf */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LRETIQ, X86_INS_RETFQ: retfq */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LRETIW, X86_INS_RETF: retf */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_LRETL, X86_INS_RETF: retf */ 0, { 0 } }, { /* X86_LRETQ, X86_INS_RETFQ: retfq */ 0, { 0 } }, { /* X86_LRETW, X86_INS_RETF: retf */ 0, { 0 } }, { /* X86_LSL16rm, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL16rr, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL32rm, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL32rr, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL64rm, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSL64rr, X86_INS_LSL: lsl */ X86_EFLAGS_MODIFY_ZF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSS16rm, X86_INS_LSS: lss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSS32rm, X86_INS_LSS: lss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LSS64rm, X86_INS_LSS: lss */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LTRm, X86_INS_LTR: ltr */ 0, { CS_AC_READ, 0 } }, { /* X86_LTRr, X86_INS_LTR: ltr */ 0, { CS_AC_READ, 0 } }, { /* X86_LWPINS32rmi, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPINS32rri, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPINS64rmi, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPINS64rri, X86_INS_LWPINS: lwpins */ 0, { 0 } }, { /* X86_LWPVAL32rmi, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LWPVAL32rri, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LWPVAL64rmi, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LWPVAL64rri, X86_INS_LWPVAL: lwpval */ 0, { 0 } }, { /* X86_LZCNT16rm, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT16rr, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT32rm, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT32rr, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT64rm, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_LZCNT64rr, X86_INS_LZCNT: lzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MONITORXrrr, X86_INS_MONITORX: monitorx */ 0, { 0 } }, { /* X86_MONTMUL, X86_INS_MONTMUL: montmul */ 0, { 0 } }, { /* X86_MOV16ao16, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16mi, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV16mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ms, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16o16a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16ri, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV16ri_alt, X86_INS_MOV: mov{w} $dst $src */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV16rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16rr_REV, X86_INS_MOV: mov{w} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16rs, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16sm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV16sr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ao16, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32cr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32dr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32mi, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV32mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32o16a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rc, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rd, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32ri, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV32ri_alt, X86_INS_MOV: mov{l} $dst $src */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV32rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rr_REV, X86_INS_MOV: mov{l} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32rs, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV32sr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64cr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64dr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64mi32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV64mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rc, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rd, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64ri, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV64ri32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV64rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rr_REV, X86_INS_MOV: mov{q} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64rs, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV64sr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ao16, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ao32, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ao64, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8mi, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV8mr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8mr_NOREX, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8o16a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8o32a, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8o64a, X86_INS_MOVABS: movabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8ri, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV8ri_alt, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_MOV8rm, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rm_NOREX, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rr, X86_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rr_NOREX, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOV8rr_REV, X86_INS_MOV: mov{b} $dst $src */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE16mr, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE16rm, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE32mr, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE32rm, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE64mr, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVBE64rm, X86_INS_MOVBE: movbe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVDIR64B16, X86_INS_MOVDIR64B: movdir64b */ 0, { 0 } }, { /* X86_MOVDIR64B32, X86_INS_MOVDIR64B: movdir64b */ 0, { 0 } }, { /* X86_MOVDIR64B64, X86_INS_MOVDIR64B: movdir64b */ 0, { 0 } }, { /* X86_MOVDIRI32, X86_INS_MOVDIRI: movdiri */ 0, { 0 } }, { /* X86_MOVDIRI64, X86_INS_MOVDIRI: movdiri */ 0, { 0 } }, { /* X86_MOVSB, X86_INS_MOVSB: movsb */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSL, X86_INS_MOVSD: movsd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSQ, X86_INS_MOVSQ: movsq */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSW, X86_INS_MOVSW: movsw */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX16rm16, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX16rm8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX16rr16, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX16rr8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rm16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rm8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rm8_NOREX, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX32rr16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rr8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX32rr8_NOREX, X86_INS_MOVSX: movsx */ 0, { 0 } }, { /* X86_MOVSX64rm16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rm32, X86_INS_MOVSXD: movsxd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rm8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rr16, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rr32, X86_INS_MOVSXD: movsxd */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVSX64rr8, X86_INS_MOVSX: movsx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX16rm16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX16rm8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX16rr16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX16rr8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rm16, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rm8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rm8_NOREX, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX32rr16, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rr8, X86_INS_MOVZX: movzx */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MOVZX32rr8_NOREX, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rm16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rm8, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rr16, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MOVZX64rr8, X86_INS_MOVZX: movzx */ 0, { 0 } }, { /* X86_MUL16m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL16r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL32m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL32r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL64m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL64r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL8m, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MUL8r, X86_INS_MUL: mul */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, 0 } }, { /* X86_MULX32rm, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX32rr, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX64rm, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MULX64rr, X86_INS_MULX: mulx */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_MWAITXrrr, X86_INS_MWAITX: mwaitx */ 0, { 0 } }, { /* X86_NEG16m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG16r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG32m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG32r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG64m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG64r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG8m, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NEG8r, X86_INS_NEG: neg */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOOP, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOP18_16m4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16m5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16m6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16m7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_16r7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_m7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r4, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r5, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r6, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP18_r7, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOP19rr, X86_INS_NOP: nop */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_NOOPL, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPL_19, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPL_1d, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPL_1e, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPLr, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOPQ, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOPQr, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOOPW, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_19, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_1c, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_1d, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPW_1e, X86_INS_NOP: nop */ 0, { CS_AC_READ, 0 } }, { /* X86_NOOPWr, X86_INS_NOP: nop */ 0, { 0 } }, { /* X86_NOT16m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT16r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT32m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT32r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT64m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT64r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT8m, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_NOT8r, X86_INS_NOT: not */ 0, { CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_OR16i16, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16mi, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16mi8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR16ri, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16ri8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR16rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR16rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR16rr_REV, X86_INS_OR: or{w} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32i32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32mi, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32mi8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32ri, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32ri8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR32rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR32rr_REV, X86_INS_OR: or{l} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64i32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64mi32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64mi8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64ri32, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64ri8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR64rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR64rr_REV, X86_INS_OR: or{q} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8i8, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8mi, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8mi8, X86_INS_OR: or{b} $dst $src */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8mr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8ri, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8ri8, X86_INS_OR: or{b} $src1 $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_OR8rm, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8rr, X86_INS_OR: or */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OR8rr_REV, X86_INS_OR: or{b} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_OUT16ir, X86_INS_OUT: out */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_OUT16rr, X86_INS_OUT: out */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_OUT32ir, X86_INS_OUT: out */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_OUT32rr, X86_INS_OUT: out */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_OUT8ir, X86_INS_OUT: out */ 0, { CS_AC_IGNORE, CS_AC_READ, 0 } }, { /* X86_OUT8rr, X86_INS_OUT: out */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_OUTSB, X86_INS_OUTSB: outsb */ X86_EFLAGS_TEST_DF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_OUTSL, X86_INS_OUTSD: outsd */ X86_EFLAGS_TEST_DF, { CS_AC_IGNORE, 0 } }, { /* X86_OUTSW, X86_INS_OUTSW: outsw */ X86_EFLAGS_TEST_DF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_PCONFIG, X86_INS_PCONFIG: pconfig */ 0, { 0 } }, { /* X86_PDEP32rm, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PDEP32rr, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PDEP64rm, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PDEP64rr, X86_INS_PDEP: pdep */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT32rm, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT32rr, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT64rm, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_PEXT64rr, X86_INS_PEXT: pext */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_POP16r, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP16rmm, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP16rmr, X86_INS_POP: pop{w} $reg */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP32r, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP32rmm, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP32rmr, X86_INS_POP: pop{l} $reg */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP64r, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP64rmm, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POP64rmr, X86_INS_POP: pop{q} $reg */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPA16, X86_INS_POPAW: popaw */ 0, { 0 } }, { /* X86_POPA32, X86_INS_POPAL: popal */ 0, { 0 } }, { /* X86_POPDS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPDS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPES16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPES32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPF16, X86_INS_POPF: popf */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_POPF32, X86_INS_POPFD: popfd */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_POPF64, X86_INS_POPFQ: popfq */ X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_POPFS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPFS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPFS64, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPGS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPGS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPGS64, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPSS16, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_POPSS32, X86_INS_POP: pop */ 0, { CS_AC_WRITE, 0 } }, { /* X86_PTWRITE64m, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PTWRITE64r, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PTWRITEm, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PTWRITEr, X86_INS_PTWRITE: ptwrite */ 0, { 0 } }, { /* X86_PUSH16i8, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH16r, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH16rmm, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH16rmr, X86_INS_PUSH: push{w} $reg */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH32i8, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH32r, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH32rmm, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH32rmr, X86_INS_PUSH: push{l} $reg */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH64i32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH64i8, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSH64r, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH64rmm, X86_INS_PUSH: push */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSH64rmr, X86_INS_PUSH: push{q} $reg */ 0, { CS_AC_READ, 0 } }, { /* X86_PUSHA16, X86_INS_PUSHAW: pushaw */ 0, { 0 } }, { /* X86_PUSHA32, X86_INS_PUSHAL: pushal */ 0, { 0 } }, { /* X86_PUSHCS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHCS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHDS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHDS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHES16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHES32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHF16, X86_INS_PUSHF: pushf */ 0, { 0 } }, { /* X86_PUSHF32, X86_INS_PUSHFD: pushfd */ 0, { 0 } }, { /* X86_PUSHF64, X86_INS_PUSHFQ: pushfq */ 0, { 0 } }, { /* X86_PUSHFS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHFS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHFS64, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHGS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHGS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHGS64, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHSS16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHSS32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHi16, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_PUSHi32, X86_INS_PUSH: push */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RCL16m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL16mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL16mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL16r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL16rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL16ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL32m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL32mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL32mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL32r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL32rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL32ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL64m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL64mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL64mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL64r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL64rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL64ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL8m1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL8mCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCL8mi, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCL8r1, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCL8rCL, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCL8ri, X86_INS_RCL: rcl */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR16m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR16mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR16mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR16r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR16rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR16ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR32m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR32mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR32mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR32r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR32rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR32ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR64m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR64mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR64mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR64r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR64rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR64ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR8m1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR8mCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_RCR8mi, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RCR8r1, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RCR8rCL, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_RCR8ri, X86_INS_RCR: rcr */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RDFSBASE, X86_INS_RDFSBASE: rdfsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDFSBASE64, X86_INS_RDFSBASE: rdfsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDGSBASE, X86_INS_RDGSBASE: rdgsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDGSBASE64, X86_INS_RDGSBASE: rdgsbase */ 0, { CS_AC_WRITE, 0 } }, { /* X86_RDMSR, X86_INS_RDMSR: rdmsr */ 0, { 0 } }, { /* X86_RDPID32, X86_INS_RDPID: rdpid */ 0, { 0 } }, { /* X86_RDPID64, X86_INS_RDPID: rdpid */ 0, { 0 } }, { /* X86_RDPKRUr, X86_INS_RDPKRU: rdpkru */ 0, { 0 } }, { /* X86_RDPMC, X86_INS_RDPMC: rdpmc */ 0, { 0 } }, { /* X86_RDRAND16r, X86_INS_RDRAND: rdrand */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDRAND32r, X86_INS_RDRAND: rdrand */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDRAND64r, X86_INS_RDRAND: rdrand */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSEED16r, X86_INS_RDSEED: rdseed */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSEED32r, X86_INS_RDSEED: rdseed */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSEED64r, X86_INS_RDSEED: rdseed */ X86_EFLAGS_MODIFY_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_ZF | X86_EFLAGS_RESET_AF | X86_EFLAGS_RESET_PF, { CS_AC_WRITE, 0 } }, { /* X86_RDSSPD, X86_INS_RDSSPD: rdsspd */ 0, { 0 } }, { /* X86_RDSSPQ, X86_INS_RDSSPQ: rdsspq */ 0, { 0 } }, { /* X86_RDTSC, X86_INS_RDTSC: rdtsc */ 0, { 0 } }, { /* X86_RDTSCP, X86_INS_RDTSCP: rdtscp */ 0, { 0 } }, { /* X86_REPNE_PREFIX, X86_INS_REPNE: repne */ 0, { 0 } }, { /* X86_REP_PREFIX, X86_INS_REP: rep */ 0, { 0 } }, { /* X86_RETIL, X86_INS_RET: ret */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RETIQ, X86_INS_RET: ret */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RETIW, X86_INS_RET: ret */ 0, { CS_AC_IGNORE, 0 } }, { /* X86_RETL, X86_INS_RET: ret */ 0, { 0 } }, { /* X86_RETQ, X86_INS_RET: ret */ 0, { 0 } }, { /* X86_RETW, X86_INS_RET: ret */ 0, { 0 } }, { /* X86_REX64_PREFIX, X86_INS_REX64: rex64 */ 0, { 0 } }, { /* X86_ROL16m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL16mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL16mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL16r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL16rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL16ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL32m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL32mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL32mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL32r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL32rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL32ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL64m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL64mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL64mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL64r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL64rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL64ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL8m1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL8mCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROL8mi, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROL8r1, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROL8rCL, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROL8ri, X86_INS_ROL: rol */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR16m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR16mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR16mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR16r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR16rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR16ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR32m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR32mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR32mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR32r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR32rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR32ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR64m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR64mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR64mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR64r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR64rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR64ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR8m1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR8mCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_ROR8mi, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_ROR8r1, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_ROR8rCL, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_ROR8ri, X86_INS_ROR: ror */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_RORX32mi, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RORX32ri, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RORX64mi, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RORX64ri, X86_INS_RORX: rorx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_RSM, X86_INS_RSM: rsm */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_RSTORSSP, X86_INS_RSTORSSP: rstorssp */ 0, { 0 } }, { /* X86_SAHF, X86_INS_SAHF: sahf */ X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { 0 } }, { /* X86_SAL16m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL16mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL16mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL16r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL16rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL16ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL32mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL32rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL32ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL64mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL64rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL64ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8m1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8mCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL8mi, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8r1, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAL8rCL, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAL8ri, X86_INS_SAL: sal */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SALC, X86_INS_SALC: salc */ 0, { 0 } }, { /* X86_SAR16m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR16mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR16mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR16r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR16rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR16ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR32mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR32rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR32ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR64mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR64rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR64ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8m1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8mCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR8mi, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8r1, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SAR8rCL, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SAR8ri, X86_INS_SAR: sar */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SARX32rm, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SARX32rr, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SARX64rm, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SARX64rr, X86_INS_SARX: sarx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP: saveprevssp */ 0, { 0 } }, { /* X86_SBB16i16, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16mi, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16mi8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB16ri, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16ri8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB16rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB16rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB16rr_REV, X86_INS_SBB: sbb{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32i32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32mi, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32mi8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32ri, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32ri8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB32rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB32rr_REV, X86_INS_SBB: sbb{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64i32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64mi32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64mi8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64ri32, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64ri8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB64rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB64rr_REV, X86_INS_SBB: sbb{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8i8, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8mi, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8mi8, X86_INS_SBB: sbb{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8mr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8ri, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8ri8, X86_INS_SBB: sbb{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SBB8rm, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8rr, X86_INS_SBB: sbb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SBB8rr_REV, X86_INS_SBB: sbb{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SCASB, X86_INS_SCASB: scasb */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SCASL, X86_INS_SCASD: scasd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SCASQ, X86_INS_SCASQ: scasq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SCASW, X86_INS_SCASW: scasw */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SETAEm, X86_INS_SETAE: setae */ X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETAEr, X86_INS_SETAE: setae */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETAm, X86_INS_SETA: seta */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETAr, X86_INS_SETA: seta */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETBEm, X86_INS_SETBE: setbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETBEr, X86_INS_SETBE: setbe */ X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETBm, X86_INS_SETB: setb */ X86_EFLAGS_TEST_CF, { CS_AC_READ, 0 } }, { /* X86_SETBr, X86_INS_SETB: setb */ X86_EFLAGS_TEST_CF, { CS_AC_WRITE, 0 } }, { /* X86_SETEm, X86_INS_SETE: sete */ X86_EFLAGS_TEST_ZF, { CS_AC_READ, 0 } }, { /* X86_SETEr, X86_INS_SETE: sete */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETGEm, X86_INS_SETGE: setge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETGEr, X86_INS_SETGE: setge */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SETGm, X86_INS_SETG: setg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_READ, 0 } }, { /* X86_SETGr, X86_INS_SETG: setg */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETLEm, X86_INS_SETLE: setle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_READ, 0 } }, { /* X86_SETLEr, X86_INS_SETLE: setle */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETLm, X86_INS_SETL: setl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETLr, X86_INS_SETL: setl */ X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SETNEm, X86_INS_SETNE: setne */ X86_EFLAGS_TEST_ZF, { CS_AC_READ, 0 } }, { /* X86_SETNEr, X86_INS_SETNE: setne */ X86_EFLAGS_TEST_ZF, { CS_AC_WRITE, 0 } }, { /* X86_SETNOm, X86_INS_SETNO: setno */ X86_EFLAGS_TEST_OF, { CS_AC_READ, 0 } }, { /* X86_SETNOr, X86_INS_SETNO: setno */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, 0 } }, { /* X86_SETNPm, X86_INS_SETNP: setnp */ X86_EFLAGS_TEST_PF, { CS_AC_READ, 0 } }, { /* X86_SETNPr, X86_INS_SETNP: setnp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, 0 } }, { /* X86_SETNSm, X86_INS_SETNS: setns */ X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETNSr, X86_INS_SETNS: setns */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SETOm, X86_INS_SETO: seto */ X86_EFLAGS_TEST_OF, { CS_AC_READ, 0 } }, { /* X86_SETOr, X86_INS_SETO: seto */ X86_EFLAGS_TEST_OF, { CS_AC_WRITE, 0 } }, { /* X86_SETPm, X86_INS_SETP: setp */ X86_EFLAGS_TEST_PF, { CS_AC_READ, 0 } }, { /* X86_SETPr, X86_INS_SETP: setp */ X86_EFLAGS_TEST_PF, { CS_AC_WRITE, 0 } }, { /* X86_SETSSBSY, X86_INS_SETSSBSY: setssbsy */ 0, { 0 } }, { /* X86_SETSm, X86_INS_SETS: sets */ X86_EFLAGS_TEST_SF, { CS_AC_READ, 0 } }, { /* X86_SETSr, X86_INS_SETS: sets */ X86_EFLAGS_TEST_SF, { CS_AC_WRITE, 0 } }, { /* X86_SGDT16m, X86_INS_SGDT: sgdt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SGDT32m, X86_INS_SGDT: sgdt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SGDT64m, X86_INS_SGDT: sgdt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SHL16m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL16mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL16mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL16r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL16rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL16ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL32mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL32rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL32ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL64mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL64rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL64ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8m1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8mCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL8mi, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8r1, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHL8rCL, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHL8ri, X86_INS_SHL: shl */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHLD16mrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD16mri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD16rrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD16rri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD32mrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD32mri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD32rrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD32rri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD64mrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD64mri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLD64rrCL, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLD64rri8, X86_INS_SHLD: shld */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHLX32rm, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLX32rr, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLX64rm, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHLX64rr, X86_INS_SHLX: shlx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHR16m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR16mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR16mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR16r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR16rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR16ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR32mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR32rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR32ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR64mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR64rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR64ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8m1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8mCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR8mi, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8r1, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHR8rCL, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SHR8ri, X86_INS_SHR: shr */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SHRD16mrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD16mri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD16rrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD16rri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD32mrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD32mri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD32rrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD32rri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD64mrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD64mri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRD64rrCL, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRD64rri8, X86_INS_SHRD: shrd */ X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_SHRX32rm, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRX32rr, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRX64rm, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SHRX64rr, X86_INS_SHRX: shrx */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_SIDT16m, X86_INS_SIDT: sidt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SIDT32m, X86_INS_SIDT: sidt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SIDT64m, X86_INS_SIDT: sidt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SKINIT, X86_INS_SKINIT: skinit */ 0, { CS_AC_READ, 0 } }, { /* X86_SLDT16m, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLDT16r, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLDT32r, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLDT64r, X86_INS_SLDT: sldt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SLWPCB, X86_INS_SLWPCB: slwpcb */ 0, { 0 } }, { /* X86_SLWPCB64, X86_INS_SLWPCB: slwpcb */ 0, { 0 } }, { /* X86_SMSW16m, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SMSW16r, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SMSW32r, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SMSW64r, X86_INS_SMSW: smsw */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STAC, X86_INS_STAC: stac */ 0, { 0 } }, { /* X86_STC, X86_INS_STC: stc */ X86_EFLAGS_SET_CF, { 0 } }, { /* X86_STD, X86_INS_STD: std */ X86_EFLAGS_SET_DF, { 0 } }, { /* X86_STGI, X86_INS_STGI: stgi */ 0, { 0 } }, { /* X86_STI, X86_INS_STI: sti */ X86_EFLAGS_SET_IF, { 0 } }, { /* X86_STOSB, X86_INS_STOSB: stosb */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STOSL, X86_INS_STOSD: stosd */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STOSQ, X86_INS_STOSQ: stosq */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STOSW, X86_INS_STOSW: stosw */ X86_EFLAGS_TEST_DF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_STR16r, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STR32r, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STR64r, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_STRm, X86_INS_STR: str */ 0, { CS_AC_WRITE, 0 } }, { /* X86_SUB16i16, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16mi, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16mi8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB16ri, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16ri8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB16rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB16rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB16rr_REV, X86_INS_SUB: sub{w} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32i32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32mi, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32mi8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32ri, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32ri8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB32rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB32rr_REV, X86_INS_SUB: sub{l} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64i32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64mi32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64mi8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64ri32, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64ri8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB64rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB64rr_REV, X86_INS_SUB: sub{q} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8i8, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8mi, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8mi8, X86_INS_SUB: sub{b} $dst $src */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8mr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8ri, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8ri8, X86_INS_SUB: sub{b} $src1 $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_SUB8rm, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8rr, X86_INS_SUB: sub */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SUB8rr_REV, X86_INS_SUB: sub{b} $dst $src2 */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_SWAPGS, X86_INS_SWAPGS: swapgs */ 0, { 0 } }, { /* X86_SYSCALL, X86_INS_SYSCALL: syscall */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSENTER, X86_INS_SYSENTER: sysenter */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSEXIT, X86_INS_SYSEXIT: sysexit */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSEXIT64, X86_INS_SYSEXITQ: sysexitq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSRET, X86_INS_SYSRET: sysret */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_SYSRET64, X86_INS_SYSRETQ: sysretq */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_MODIFY_TF | X86_EFLAGS_MODIFY_IF | X86_EFLAGS_MODIFY_DF | X86_EFLAGS_MODIFY_NT | X86_EFLAGS_MODIFY_RF, { 0 } }, { /* X86_T1MSKC32rm, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_T1MSKC32rr, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_T1MSKC64rm, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_T1MSKC64rr, X86_INS_T1MSKC: t1mskc */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TEST16i16, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST16mi, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST16mi_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST16mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST16ri, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST16ri_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST16rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST32i32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST32mi, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST32mi_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST32mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST32ri, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST32ri_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST32rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST64i32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST64mi32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST64mi32_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST64mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST64ri32, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST64ri32_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST64rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST8i8, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST8mi, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_TEST8mi_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST8mr, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST8ri, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_IGNORE, 0 } }, { /* X86_TEST8ri_alt, X86_INS_TEST: test */ 0, { 0 } }, { /* X86_TEST8rr, X86_INS_TEST: test */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TPAUSE, X86_INS_TPAUSE: tpause */ 0, { 0 } }, { /* X86_TZCNT16rm, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT16rr, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT32rm, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT32rr, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT64rm, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZCNT64rr, X86_INS_TZCNT: tzcnt */ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_CF | X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_UNDEFINED_AF, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK32rm, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK32rr, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK64rm, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_TZMSK64rr, X86_INS_TZMSK: tzmsk */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_UD0, X86_INS_UD0: ud0 */ 0, { 0 } }, { /* X86_UD1, X86_INS_UD1: ud1 */ 0, { 0 } }, { /* X86_UD2, X86_INS_UD2: ud2 */ 0, { 0 } }, { /* X86_UMONITOR16, X86_INS_UMONITOR: umonitor */ 0, { 0 } }, { /* X86_UMONITOR32, X86_INS_UMONITOR: umonitor */ 0, { 0 } }, { /* X86_UMONITOR64, X86_INS_UMONITOR: umonitor */ 0, { 0 } }, { /* X86_UMWAIT, X86_INS_UMWAIT: umwait */ 0, { 0 } }, { /* X86_VERRm, X86_INS_VERR: verr */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VERRr, X86_INS_VERR: verr */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VERWm, X86_INS_VERW: verw */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VERWr, X86_INS_VERW: verw */ X86_EFLAGS_MODIFY_ZF, { CS_AC_READ, 0 } }, { /* X86_VMCALL, X86_INS_VMCALL: vmcall */ 0, { 0 } }, { /* X86_VMCLEARm, X86_INS_VMCLEAR: vmclear */ 0, { CS_AC_READ, 0 } }, { /* X86_VMFUNC, X86_INS_VMFUNC: vmfunc */ 0, { 0 } }, { /* X86_VMLAUNCH, X86_INS_VMLAUNCH: vmlaunch */ 0, { 0 } }, { /* X86_VMLOAD32, X86_INS_VMLOAD: vmload */ 0, { CS_AC_READ, 0 } }, { /* X86_VMLOAD64, X86_INS_VMLOAD: vmload */ 0, { CS_AC_READ, 0 } }, { /* X86_VMMCALL, X86_INS_VMMCALL: vmmcall */ 0, { 0 } }, { /* X86_VMPTRLDm, X86_INS_VMPTRLD: vmptrld */ 0, { CS_AC_READ, 0 } }, { /* X86_VMPTRSTm, X86_INS_VMPTRST: vmptrst */ 0, { CS_AC_WRITE, 0 } }, { /* X86_VMREAD32mr, X86_INS_VMREAD: vmread */ 0, { 0 } }, { /* X86_VMREAD32rr, X86_INS_VMREAD: vmread */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMREAD64mr, X86_INS_VMREAD: vmread */ 0, { 0 } }, { /* X86_VMREAD64rr, X86_INS_VMREAD: vmread */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMRESUME, X86_INS_VMRESUME: vmresume */ 0, { 0 } }, { /* X86_VMRUN32, X86_INS_VMRUN: vmrun */ 0, { CS_AC_READ, 0 } }, { /* X86_VMRUN64, X86_INS_VMRUN: vmrun */ 0, { CS_AC_READ, 0 } }, { /* X86_VMSAVE32, X86_INS_VMSAVE: vmsave */ 0, { CS_AC_READ, 0 } }, { /* X86_VMSAVE64, X86_INS_VMSAVE: vmsave */ 0, { CS_AC_READ, 0 } }, { /* X86_VMWRITE32rm, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMWRITE32rr, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMWRITE64rm, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMWRITE64rr, X86_INS_VMWRITE: vmwrite */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_VMXOFF, X86_INS_VMXOFF: vmxoff */ 0, { 0 } }, { /* X86_VMXON, X86_INS_VMXON: vmxon */ 0, { CS_AC_READ, 0 } }, { /* X86_WBINVD, X86_INS_WBINVD: wbinvd */ 0, { 0 } }, { /* X86_WBNOINVD, X86_INS_WBNOINVD: wbnoinvd */ 0, { 0 } }, { /* X86_WRFSBASE, X86_INS_WRFSBASE: wrfsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRFSBASE64, X86_INS_WRFSBASE: wrfsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRGSBASE, X86_INS_WRGSBASE: wrgsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRGSBASE64, X86_INS_WRGSBASE: wrgsbase */ 0, { CS_AC_READ, 0 } }, { /* X86_WRMSR, X86_INS_WRMSR: wrmsr */ 0, { 0 } }, { /* X86_WRPKRUr, X86_INS_WRPKRU: wrpkru */ 0, { 0 } }, { /* X86_WRSSD, X86_INS_WRSSD: wrssd */ 0, { 0 } }, { /* X86_WRSSQ, X86_INS_WRSSQ: wrssq */ 0, { 0 } }, { /* X86_WRUSSD, X86_INS_WRUSSD: wrussd */ 0, { 0 } }, { /* X86_WRUSSQ, X86_INS_WRUSSQ: wrussq */ 0, { 0 } }, { /* X86_XADD16rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD16rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD32rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD32rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD64rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD64rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD8rm, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XADD8rr, X86_INS_XADD: xadd */ X86_EFLAGS_MODIFY_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_MODIFY_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG16ar, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG16rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG16rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG32ar, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG32rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG32rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG64ar, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG64rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG64rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG8rm, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCHG8rr, X86_INS_XCHG: xchg */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } }, { /* X86_XCRYPTCBC, X86_INS_XCRYPTCBC: xcryptcbc */ 0, { 0 } }, { /* X86_XCRYPTCFB, X86_INS_XCRYPTCFB: xcryptcfb */ 0, { 0 } }, { /* X86_XCRYPTCTR, X86_INS_XCRYPTCTR: xcryptctr */ 0, { 0 } }, { /* X86_XCRYPTECB, X86_INS_XCRYPTECB: xcryptecb */ 0, { 0 } }, { /* X86_XCRYPTOFB, X86_INS_XCRYPTOFB: xcryptofb */ 0, { 0 } }, { /* X86_XGETBV, X86_INS_XGETBV: xgetbv */ 0, { 0 } }, { /* X86_XLAT, X86_INS_XLATB: xlatb */ 0, { 0 } }, { /* X86_XOR16i16, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16mi, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16mi8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR16ri, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16ri8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR16rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR16rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR16rr_REV, X86_INS_XOR: xor{w} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32i32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32mi, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32mi8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32ri, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32ri8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR32rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR32rr_REV, X86_INS_XOR: xor{l} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64i32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64mi32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64mi8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64ri32, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64ri8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR64rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR64rr_REV, X86_INS_XOR: xor{q} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8i8, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8mi, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8mi8, X86_INS_XOR: xor{b} $dst $src */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8mr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8ri, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8ri8, X86_INS_XOR: xor{b} $src1 $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_IGNORE, 0 } }, { /* X86_XOR8rm, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8rr, X86_INS_XOR: xor */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XOR8rr_REV, X86_INS_XOR: xor{b} $dst $src2 */ X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, { /* X86_XRSTOR, X86_INS_XRSTOR: xrstor */ 0, { CS_AC_READ, 0 } }, { /* X86_XRSTOR64, X86_INS_XRSTOR64: xrstor64 */ 0, { CS_AC_READ, 0 } }, { /* X86_XRSTORS, X86_INS_XRSTORS: xrstors */ 0, { CS_AC_READ, 0 } }, { /* X86_XRSTORS64, X86_INS_XRSTORS64: xrstors64 */ 0, { CS_AC_READ, 0 } }, { /* X86_XSAVE, X86_INS_XSAVE: xsave */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVE64, X86_INS_XSAVE64: xsave64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEC, X86_INS_XSAVEC: xsavec */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEC64, X86_INS_XSAVEC64: xsavec64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEOPT, X86_INS_XSAVEOPT: xsaveopt */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVEOPT64, X86_INS_XSAVEOPT64: xsaveopt64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVES, X86_INS_XSAVES: xsaves */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSAVES64, X86_INS_XSAVES64: xsaves64 */ 0, { CS_AC_WRITE, 0 } }, { /* X86_XSETBV, X86_INS_XSETBV: xsetbv */ 0, { 0 } }, { /* X86_XSHA1, X86_INS_XSHA1: xsha1 */ 0, { 0 } }, { /* X86_XSHA256, X86_INS_XSHA256: xsha256 */ 0, { 0 } }, { /* X86_XSTORE, X86_INS_XSTORE: xstore */ 0, { 0 } }, capstone-sys-0.15.0/capstone/arch/X86/X86MappingInsn_reduce.inc000064400000000000000000005333760072674642500223010ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { X86_AAA, X86_INS_AAA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AAD8i8, X86_INS_AAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AAM8i8, X86_INS_AAM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AAS, X86_INS_AAS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADC16i16, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16mi, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16mi8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16mr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16ri, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16ri8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16rm, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16rr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC16rr_REV, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32i32, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32mi, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32mi8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32mr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32ri, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32ri8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32rm, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32rr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC32rr_REV, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64i32, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64mi32, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64mi8, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64mr, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64ri32, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64ri8, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64rm, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64rr, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC64rr_REV, X86_INS_ADC, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8i8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8mi, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8mi8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADC8mr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8ri, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8ri8, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADC8rm, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8rr, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADC8rr_REV, X86_INS_ADC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADCX32rm, X86_INS_ADCX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADCX32rr, X86_INS_ADCX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADCX64rm, X86_INS_ADCX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADCX64rr, X86_INS_ADCX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADD16i16, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16mi, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16mi8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16mr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16ri, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16ri8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16rm, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16rr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD16rr_REV, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32i32, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32mi, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32mi8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32mr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32ri, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32ri8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32rm, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32rr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD32rr_REV, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64i32, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64mi32, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64mi8, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64mr, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64ri32, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64ri8, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64rm, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64rr, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD64rr_REV, X86_INS_ADD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8i8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8mi, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8mi8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADD8mr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8ri, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8ri8, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ADD8rm, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8rr, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADD8rr_REV, X86_INS_ADD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ADOX32rm, X86_INS_ADOX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADOX32rr, X86_INS_ADOX, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADOX64rm, X86_INS_ADOX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_ADOX64rr, X86_INS_ADOX, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_ADX, 0 }, 0, 0 #endif }, { X86_AND16i16, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16mi, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16mi8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16mr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16ri, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16ri8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16rm, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16rr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND16rr_REV, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32i32, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32mi, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32mi8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32mr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32ri, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32ri8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32rm, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32rr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND32rr_REV, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64i32, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64mi32, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64mi8, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64mr, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64ri32, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64ri8, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64rm, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64rr, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND64rr_REV, X86_INS_AND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8i8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8mi, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8mi8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AND8mr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8ri, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8ri8, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_AND8rm, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8rr, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_AND8rr_REV, X86_INS_AND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ANDN32rm, X86_INS_ANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDN32rr, X86_INS_ANDN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDN64rm, X86_INS_ANDN, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ANDN64rr, X86_INS_ANDN, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_ARPL16mr, X86_INS_ARPL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_ARPL16rr, X86_INS_ARPL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_BEXTR32rm, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTR32rr, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTR64rm, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTR64rr, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BEXTRI32mi, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BEXTRI32ri, X86_INS_BEXTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BEXTRI64mi, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BEXTRI64ri, X86_INS_BEXTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL32rm, X86_INS_BLCFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL32rr, X86_INS_BLCFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL64rm, X86_INS_BLCFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCFILL64rr, X86_INS_BLCFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI32rm, X86_INS_BLCI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI32rr, X86_INS_BLCI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI64rm, X86_INS_BLCI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCI64rr, X86_INS_BLCI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC32rm, X86_INS_BLCIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC32rr, X86_INS_BLCIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC64rm, X86_INS_BLCIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCIC64rr, X86_INS_BLCIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK32rm, X86_INS_BLCMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK32rr, X86_INS_BLCMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK64rm, X86_INS_BLCMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCMSK64rr, X86_INS_BLCMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS32rm, X86_INS_BLCS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS32rr, X86_INS_BLCS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS64rm, X86_INS_BLCS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLCS64rr, X86_INS_BLCS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL32rm, X86_INS_BLSFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL32rr, X86_INS_BLSFILL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL64rm, X86_INS_BLSFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSFILL64rr, X86_INS_BLSFILL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSI32rm, X86_INS_BLSI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSI32rr, X86_INS_BLSI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSI64rm, X86_INS_BLSI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSI64rr, X86_INS_BLSI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSIC32rm, X86_INS_BLSIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSIC32rr, X86_INS_BLSIC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSIC64rm, X86_INS_BLSIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSIC64rr, X86_INS_BLSIC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_BLSMSK32rm, X86_INS_BLSMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSMSK32rr, X86_INS_BLSMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSMSK64rm, X86_INS_BLSMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSMSK64rr, X86_INS_BLSMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR32rm, X86_INS_BLSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR32rr, X86_INS_BLSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR64rm, X86_INS_BLSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BLSR64rr, X86_INS_BLSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_BOUNDS16rm, X86_INS_BOUND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_BOUNDS32rm, X86_INS_BOUND, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_BSF16rm, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF16rr, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF32rm, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF32rr, X86_INS_BSF, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF64rm, X86_INS_BSF, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSF64rr, X86_INS_BSF, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR16rm, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR16rr, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR32rm, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR32rr, X86_INS_BSR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR64rm, X86_INS_BSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSR64rr, X86_INS_BSR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BSWAP16r_BAD, X86_INS_BSWAP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BSWAP32r, X86_INS_BSWAP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BSWAP64r, X86_INS_BSWAP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_BT16mi8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT16mr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT16ri8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT16rr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32mi8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32mr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32ri8, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT32rr, X86_INS_BT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64mi8, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64mr, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64ri8, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BT64rr, X86_INS_BT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16mi8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16mr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16ri8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC16rr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32mi8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32mr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32ri8, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC32rr, X86_INS_BTC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64mi8, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64mr, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64ri8, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTC64rr, X86_INS_BTC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16mi8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16mr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16ri8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR16rr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32mi8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32mr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32ri8, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR32rr, X86_INS_BTR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64mi8, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64mr, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64ri8, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTR64rr, X86_INS_BTR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16mi8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16mr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16ri8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS16rr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32mi8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32mr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32ri8, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS32rr, X86_INS_BTS, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64mi8, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64mr, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64ri8, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BTS64rr, X86_INS_BTS, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_BZHI32rm, X86_INS_BZHI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_BZHI32rr, X86_INS_BZHI, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_BZHI64rm, X86_INS_BZHI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_BZHI64rr, X86_INS_BZHI, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_CALL16m, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL16m_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL16r, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL16r_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL32m, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL32m_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL32r, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CALL32r_NT, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL64m, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_CALL64m_NT, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALL64pcrel32, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, X86_REG_RIP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_CALL64r, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_CALL64r_NT, X86_INS_CALL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CALLpcrel16, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_CALLpcrel32, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CBW, X86_INS_CBW, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_CDQ, X86_INS_CDQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 #endif }, { X86_CDQE, X86_INS_CDQE, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_RAX, 0 }, { 0 }, 0, 0 #endif }, { X86_CLAC, X86_INS_CLAC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_CLC, X86_INS_CLC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CLD, X86_INS_CLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CLDEMOTE, X86_INS_CLDEMOTE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLFLUSHOPT, X86_INS_CLFLUSHOPT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLGI, X86_INS_CLGI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_CLI, X86_INS_CLI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_CLRSSBSY, X86_INS_CLRSSBSY, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLTS, X86_INS_CLTS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLWB, X86_INS_CLWB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CLZEROr, X86_INS_CLZERO, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMC, X86_INS_CMC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMOVA16rm, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA16rr, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA32rm, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA32rr, X86_INS_CMOVA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA64rm, X86_INS_CMOVA, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVA64rr, X86_INS_CMOVA, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE16rm, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE16rr, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE32rm, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE32rr, X86_INS_CMOVAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE64rm, X86_INS_CMOVAE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVAE64rr, X86_INS_CMOVAE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB16rm, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB16rr, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB32rm, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB32rr, X86_INS_CMOVB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB64rm, X86_INS_CMOVB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVB64rr, X86_INS_CMOVB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE16rm, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE16rr, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE32rm, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE32rr, X86_INS_CMOVBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE64rm, X86_INS_CMOVBE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVBE64rr, X86_INS_CMOVBE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE16rm, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE16rr, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE32rm, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE32rr, X86_INS_CMOVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE64rm, X86_INS_CMOVE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVE64rr, X86_INS_CMOVE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG16rm, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG16rr, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG32rm, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG32rr, X86_INS_CMOVG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG64rm, X86_INS_CMOVG, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVG64rr, X86_INS_CMOVG, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE16rm, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE16rr, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE32rm, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE32rr, X86_INS_CMOVGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE64rm, X86_INS_CMOVGE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVGE64rr, X86_INS_CMOVGE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL16rm, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL16rr, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL32rm, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL32rr, X86_INS_CMOVL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL64rm, X86_INS_CMOVL, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVL64rr, X86_INS_CMOVL, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE16rm, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE16rr, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE32rm, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE32rr, X86_INS_CMOVLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE64rm, X86_INS_CMOVLE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVLE64rr, X86_INS_CMOVLE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE16rm, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE16rr, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE32rm, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE32rr, X86_INS_CMOVNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE64rm, X86_INS_CMOVNE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNE64rr, X86_INS_CMOVNE, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO16rm, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO16rr, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO32rm, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO32rr, X86_INS_CMOVNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO64rm, X86_INS_CMOVNO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNO64rr, X86_INS_CMOVNO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP16rm, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP16rr, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP32rm, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP32rr, X86_INS_CMOVNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP64rm, X86_INS_CMOVNP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNP64rr, X86_INS_CMOVNP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS16rm, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS16rr, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS32rm, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS32rr, X86_INS_CMOVNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS64rm, X86_INS_CMOVNS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVNS64rr, X86_INS_CMOVNS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO16rm, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO16rr, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO32rm, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO32rr, X86_INS_CMOVO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO64rm, X86_INS_CMOVO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVO64rr, X86_INS_CMOVO, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP16rm, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP16rr, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP32rm, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP32rr, X86_INS_CMOVP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP64rm, X86_INS_CMOVP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVP64rr, X86_INS_CMOVP, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS16rm, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS16rr, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS32rm, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS32rr, X86_INS_CMOVS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS64rm, X86_INS_CMOVS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMOVS64rr, X86_INS_CMOVS, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_CMOV, 0 }, 0, 0 #endif }, { X86_CMP16i16, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16mi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16mi8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16mr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16ri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16ri8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16rm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16rr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP16rr_REV, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32i32, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32mi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32mi8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32mr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32ri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32ri8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32rm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32rr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP32rr_REV, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64i32, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64mi32, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64mi8, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64mr, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64ri32, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64ri8, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64rm, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64rr, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP64rr_REV, X86_INS_CMP, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8i8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8mi, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8mi8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CMP8mr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8ri, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8ri8, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_CMP8rm, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8rr, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMP8rr_REV, X86_INS_CMP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSB, X86_INS_CMPSB, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSL, X86_INS_CMPSD, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSQ, X86_INS_CMPSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPSW, X86_INS_CMPSW, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG16B, X86_INS_CMPXCHG16B, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG16rm, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG16rr, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG32rm, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG32rr, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG64rm, X86_INS_CMPXCHG, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG64rr, X86_INS_CMPXCHG, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG8B, X86_INS_CMPXCHG8B, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG8rm, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CMPXCHG8rr, X86_INS_CMPXCHG, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_CPUID, X86_INS_CPUID, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EBX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, 0, 0 #endif }, { X86_CQO, X86_INS_CQO, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 #endif }, { X86_CWD, X86_INS_CWD, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, 0 }, { 0 }, 0, 0 #endif }, { X86_CWDE, X86_INS_CWDE, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_DAA, X86_INS_DAA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DAS, X86_INS_DAS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DATA16_PREFIX, X86_INS_DATA16, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_DEC16m, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC16r, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC16r_alt, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DEC32m, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC32r, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC32r_alt, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_DEC64m, X86_INS_DEC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC64r, X86_INS_DEC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC8m, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DEC8r, X86_INS_DEC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV16m, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV16r, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV32m, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV32r, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV64m, X86_INS_DIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV64r, X86_INS_DIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV8m, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_DIV8r, X86_INS_DIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ENDBR32, X86_INS_ENDBR32, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENDBR64, X86_INS_ENDBR64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ENTER, X86_INS_ENTER, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_FARCALL16i, X86_INS_LCALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_FARCALL16m, X86_INS_LCALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_FARCALL32i, X86_INS_LCALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_FARCALL32m, X86_INS_CALL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_FARCALL64, X86_INS_LCALL, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { 0 }, { X86_GRP_CALL, 0 }, 0, 0 #endif }, { X86_FARJMP16i, X86_INS_LJMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_FARJMP16m, X86_INS_LJMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { X86_FARJMP32i, X86_INS_LJMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_FARJMP32m, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { X86_FARJMP64, X86_INS_LJMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { X86_FSETPM, X86_INS_FSETPM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_GETSEC, X86_INS_GETSEC, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RBX, X86_REG_RCX, 0 }, { 0 }, 0, 0 #endif }, { X86_HLT, X86_INS_HLT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_IDIV16m, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV16r, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_DX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV32m, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV32r, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV64m, X86_INS_IDIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV64r, X86_INS_IDIV, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV8m, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IDIV8r, X86_INS_IDIV, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AL, X86_REG_AH, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16m, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16r, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rm, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rmi, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rmi8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rr, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rri, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL16rri8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32m, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32r, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rm, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rmi, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rmi8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rr, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rri, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL32rri8, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64m, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64r, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rm, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rmi32, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rmi8, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rr, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rri32, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL64rri8, X86_INS_IMUL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL8m, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IMUL8r, X86_INS_IMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN16ri, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN16rr, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, 0 }, { X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN32ri, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN32rr, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, 0 }, { X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_IN8ri, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 #endif }, { X86_IN8rr, X86_INS_IN, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 #endif }, { X86_INC16m, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC16r, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC16r_alt, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INC32m, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC32r, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC32r_alt, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INC64m, X86_INS_INC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC64r, X86_INS_INC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC8m, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INC8r, X86_INS_INC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_INCSSPD, X86_INS_INCSSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_INCSSPQ, X86_INS_INCSSPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_INSB, X86_INS_INSB, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_INSL, X86_INS_INSD, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_INSW, X86_INS_INSW, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_INT, X86_INS_INT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_INT1, X86_INS_INT1, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_INT3, X86_INS_INT3, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_INTO, X86_INS_INTO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_INT, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVD, X86_INS_INVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_INVEPT32, X86_INS_INVEPT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVEPT64, X86_INS_INVEPT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_INVLPG, X86_INS_INVLPG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_INVLPGA32, X86_INS_INVLPGA, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVLPGA64, X86_INS_INVLPGA, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_INVPCID32, X86_INS_INVPCID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVPCID64, X86_INS_INVPCID, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_INVVPID32, X86_INS_INVVPID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_INVVPID64, X86_INS_INVVPID, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_IRET16, X86_INS_IRET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_IRET32, X86_INS_IRETD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_IRET64, X86_INS_IRETQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_JAE_1, X86_INS_JAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JAE_2, X86_INS_JAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JAE_4, X86_INS_JAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JA_1, X86_INS_JA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JA_2, X86_INS_JA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JA_4, X86_INS_JA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JBE_1, X86_INS_JBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JBE_2, X86_INS_JBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JBE_4, X86_INS_JBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JB_1, X86_INS_JB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JB_2, X86_INS_JB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JB_4, X86_INS_JB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JCXZ, X86_INS_JCXZ, 0, #ifndef CAPSTONE_DIET { X86_REG_CX, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JECXZ, X86_INS_JECXZ, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JE_1, X86_INS_JE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JE_2, X86_INS_JE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JE_4, X86_INS_JE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JGE_1, X86_INS_JGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JGE_2, X86_INS_JGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JGE_4, X86_INS_JGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JG_1, X86_INS_JG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JG_2, X86_INS_JG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JG_4, X86_INS_JG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JLE_1, X86_INS_JLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JLE_2, X86_INS_JLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JLE_4, X86_INS_JLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JL_1, X86_INS_JL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JL_2, X86_INS_JL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JL_4, X86_INS_JL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JMP16m, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP16m_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP16r, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP16r_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP32m, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP32m_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP32r, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 1, 1 #endif }, { X86_JMP32r_NT, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP64m, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 #endif }, { X86_JMP64m_NT, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP64r, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 1, 1 #endif }, { X86_JMP64r_NT, X86_INS_JMP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_JMP_1, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JMP_2, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JMP_4, X86_INS_JMP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNE_1, X86_INS_JNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNE_2, X86_INS_JNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNE_4, X86_INS_JNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNO_1, X86_INS_JNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNO_2, X86_INS_JNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNO_4, X86_INS_JNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNP_1, X86_INS_JNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNP_2, X86_INS_JNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNP_4, X86_INS_JNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNS_1, X86_INS_JNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNS_2, X86_INS_JNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JNS_4, X86_INS_JNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JO_1, X86_INS_JO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JO_2, X86_INS_JO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JO_4, X86_INS_JO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JP_1, X86_INS_JP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JP_2, X86_INS_JP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JP_4, X86_INS_JP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JRCXZ, X86_INS_JRCXZ, 0, #ifndef CAPSTONE_DIET { X86_REG_RCX, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JS_1, X86_INS_JS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JS_2, X86_INS_JS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_JS_4, X86_INS_JS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0 #endif }, { X86_LAHF, X86_INS_LAHF, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_AH, 0 }, { 0 }, 0, 0 #endif }, { X86_LAR16rm, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR16rr, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR32rm, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR32rr, X86_INS_LAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR64rm, X86_INS_LAR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LAR64rr, X86_INS_LAR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LDS16rm, X86_INS_LDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LDS32rm, X86_INS_LDS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LEA16r, X86_INS_LEA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LEA32r, X86_INS_LEA, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LEA64_32r, X86_INS_LEA, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LEA64r, X86_INS_LEA, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LEAVE, X86_INS_LEAVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_REG_EBP, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LEAVE64, X86_INS_LEAVE, 1, #ifndef CAPSTONE_DIET { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_REG_RBP, X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LES16rm, X86_INS_LES, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LES32rm, X86_INS_LES, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LFS16rm, X86_INS_LFS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LFS32rm, X86_INS_LFS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LFS64rm, X86_INS_LFS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LGDT16m, X86_INS_LGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LGDT32m, X86_INS_LGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LGDT64m, X86_INS_LGDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LGS16rm, X86_INS_LGS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LGS32rm, X86_INS_LGS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LGS64rm, X86_INS_LGS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LIDT16m, X86_INS_LIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LIDT32m, X86_INS_LIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_LIDT64m, X86_INS_LIDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LLDT16m, X86_INS_LLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LLDT16r, X86_INS_LLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LLWPCB, X86_INS_LLWPCB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LLWPCB64, X86_INS_LLWPCB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LMSW16m, X86_INS_LMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LMSW16r, X86_INS_LMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LOCK_PREFIX, X86_INS_LOCK, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LODSB, X86_INS_LODSB, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AL, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LODSL, X86_INS_LODSD, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LODSQ, X86_INS_LODSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_RAX, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LODSW, X86_INS_LODSW, 0, #ifndef CAPSTONE_DIET { X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_AX, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_LOOP, X86_INS_LOOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LOOPE, X86_INS_LOOPE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LOOPNE, X86_INS_LOOPNE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LRETIL, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LRETIQ, X86_INS_RETFQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LRETIW, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LRETL, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LRETQ, X86_INS_RETFQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_LRETW, X86_INS_RETF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_LSL16rm, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL16rr, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL32rm, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL32rr, X86_INS_LSL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL64rm, X86_INS_LSL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSL64rr, X86_INS_LSL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSS16rm, X86_INS_LSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSS32rm, X86_INS_LSS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LSS64rm, X86_INS_LSS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LTRm, X86_INS_LTR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LTRr, X86_INS_LTR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_LWPINS32rmi, X86_INS_LWPINS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPINS32rri, X86_INS_LWPINS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPINS64rmi, X86_INS_LWPINS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPINS64rri, X86_INS_LWPINS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL32rmi, X86_INS_LWPVAL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL32rri, X86_INS_LWPVAL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL64rmi, X86_INS_LWPVAL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LWPVAL64rri, X86_INS_LWPVAL, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT16rm, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT16rr, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT32rm, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT32rr, X86_INS_LZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT64rm, X86_INS_LZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_LZCNT64rr, X86_INS_LZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MONITORXrrr, X86_INS_MONITORX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MONTMUL, X86_INS_MONTMUL, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RSI, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_RSI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ao16, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ao32, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16mi, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16mr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ms, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16o16a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16o32a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ri, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16ri_alt, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rr_REV, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16rs, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV16sm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV16sr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV32ao16, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32ao32, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32cr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32dr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32mi, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32mr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32o16a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32o32a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rc, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32rd, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_MOV32ri, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32ri_alt, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rr_REV, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32rs, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV32sr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV64ao32, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64cr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64dr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64mi32, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64mr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64o32a, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rc, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64rd, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOV64ri, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64ri32, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rm, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rr_REV, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64rs, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV64sr, X86_INS_MOV, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_MOV8ao16, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ao32, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ao64, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8mi, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8mr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8mr_NOREX, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8o16a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8o32a, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8o64a, X86_INS_MOVABS, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ri, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8ri_alt, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rm, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rm_NOREX, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rr, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rr_NOREX, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOV8rr_REV, X86_INS_MOV, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE16mr, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE16rm, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE32mr, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE32rm, X86_INS_MOVBE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE64mr, X86_INS_MOVBE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVBE64rm, X86_INS_MOVBE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIR64B16, X86_INS_MOVDIR64B, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIR64B32, X86_INS_MOVDIR64B, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIR64B64, X86_INS_MOVDIR64B, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIRI32, X86_INS_MOVDIRI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVDIRI64, X86_INS_MOVDIRI, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSB, X86_INS_MOVSB, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSL, X86_INS_MOVSD, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSQ, X86_INS_MOVSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSW, X86_INS_MOVSW, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rm16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rm8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rr16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX16rr8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rm16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rm8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rm8_NOREX, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rr16, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rr8, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX32rr8_NOREX, X86_INS_MOVSX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rm16, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rm32, X86_INS_MOVSXD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOVSX64rm8, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rr16, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVSX64rr32, X86_INS_MOVSXD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_MOVSX64rr8, X86_INS_MOVSX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rm16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rm8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rr16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX16rr8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rm16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rm8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rm8_NOREX, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rr16, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rr8, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX32rr8_NOREX, X86_INS_MOVZX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rm16, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rm8, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rr16, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MOVZX64rr8, X86_INS_MOVZX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_MUL16m, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL16r, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { X86_REG_AX, X86_REG_DX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL32m, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL32r, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { X86_REG_EAX, X86_REG_EDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL64m, X86_INS_MUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL64r, X86_INS_MUL, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { X86_REG_RAX, X86_REG_RDX, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL8m, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_MUL8r, X86_INS_MUL, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { X86_REG_AL, X86_REG_EFLAGS, X86_REG_AX, 0 }, { 0 }, 0, 0 #endif }, { X86_MULX32rm, X86_INS_MULX, 0, #ifndef CAPSTONE_DIET { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MULX32rr, X86_INS_MULX, 0, #ifndef CAPSTONE_DIET { X86_REG_EDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MULX64rm, X86_INS_MULX, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MULX64rr, X86_INS_MULX, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_MWAITXrrr, X86_INS_MWAITX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NEG16m, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG16r, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG32m, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG32r, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG64m, X86_INS_NEG, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG64r, X86_INS_NEG, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG8m, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NEG8r, X86_INS_NEG, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16m7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_16r7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_m7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r4, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r5, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r6, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP18_r7, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOP19rr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL_19, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL_1d, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPL_1e, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPLr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPQ, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPQr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_19, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_1c, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_1d, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPW_1e, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOOPWr, X86_INS_NOP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT16m, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT16r, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT32m, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT32r, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT64m, X86_INS_NOT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT64r, X86_INS_NOT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT8m, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_NOT8r, X86_INS_NOT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OR16i16, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16mi, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16mi8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16mr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16ri, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16ri8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16rm, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16rr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR16rr_REV, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32i32, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32mi, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32mi8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32mr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32ri, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32ri8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32rm, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32rr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR32rr_REV, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64i32, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64mi32, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64mi8, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64mr, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64ri32, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64ri8, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64rm, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64rr, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR64rr_REV, X86_INS_OR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8i8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8mi, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8mi8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_OR8mr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8ri, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8ri8, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_OR8rm, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8rr, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OR8rr_REV, X86_INS_OR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_OUT16ir, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT16rr, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_AX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT32ir, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT32rr, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT8ir, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUT8rr, X86_INS_OUT, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_AL, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_OUTSB, X86_INS_OUTSB, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_OUTSL, X86_INS_OUTSD, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_OUTSW, X86_INS_OUTSW, 0, #ifndef CAPSTONE_DIET { X86_REG_DX, X86_REG_ESI, X86_REG_EFLAGS, 0 }, { X86_REG_ESI, 0 }, { 0 }, 0, 0 #endif }, { X86_PCONFIG, X86_INS_PCONFIG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PDEP32rm, X86_INS_PDEP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PDEP32rr, X86_INS_PDEP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PDEP64rm, X86_INS_PDEP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PDEP64rr, X86_INS_PDEP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT32rm, X86_INS_PEXT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT32rr, X86_INS_PEXT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT64rm, X86_INS_PEXT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_PEXT64rr, X86_INS_PEXT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_POP16r, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_POP16rmm, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_POP16rmr, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_POP32r, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POP32rmm, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POP32rmr, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POP64r, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POP64rmm, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POP64rmr, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPA16, X86_INS_POPAW, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPA32, X86_INS_POPAL, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPDS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPDS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPES16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPES32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPF16, X86_INS_POPF, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_POPF32, X86_INS_POPFD, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPF64, X86_INS_POPFQ, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPFS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_POPFS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPFS64, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPGS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_POPGS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPGS64, X86_INS_POP, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_POPSS16, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_POPSS32, X86_INS_POP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PTWRITE64m, X86_INS_PTWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PTWRITE64r, X86_INS_PTWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PTWRITEm, X86_INS_PTWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PTWRITEr, X86_INS_PTWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH16i8, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH16r, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH16rmm, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH16rmr, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSH32i8, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH32r, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH32rmm, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH32rmr, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSH64i32, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64i8, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64r, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64rmm, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSH64rmr, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHA16, X86_INS_PUSHAW, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHA32, X86_INS_PUSHAL, 0, #ifndef CAPSTONE_DIET { X86_REG_EDI, X86_REG_ESI, X86_REG_EBP, X86_REG_EBX, X86_REG_EDX, X86_REG_ECX, X86_REG_EAX, X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHCS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHCS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHDS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHDS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHES16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHES32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHF16, X86_INS_PUSHF, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { 0 }, 0, 0 #endif }, { X86_PUSHF32, X86_INS_PUSHFD, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, X86_REG_EFLAGS, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHF64, X86_INS_PUSHFQ, 1, #ifndef CAPSTONE_DIET { X86_REG_RSP, X86_REG_EFLAGS, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHFS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PUSHFS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHFS64, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHGS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_PUSHGS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHGS64, X86_INS_PUSH, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_PUSHSS16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHSS32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHi16, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_PUSHi32, X86_INS_PUSH, 0, #ifndef CAPSTONE_DIET { X86_REG_ESP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_RCL16m1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16mCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16mi, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16r1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16rCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL16ri, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32m1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32mCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32mi, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32r1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32rCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL32ri, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64m1, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64mCL, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64mi, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64r1, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64rCL, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL64ri, X86_INS_RCL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8m1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8mCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8mi, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8r1, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8rCL, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCL8ri, X86_INS_RCL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16m1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16mCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16mi, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16r1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16rCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR16ri, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32m1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32mCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32mi, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32r1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32rCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR32ri, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64m1, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64mCL, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64mi, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64r1, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64rCL, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR64ri, X86_INS_RCR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8m1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8mCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8mi, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8r1, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8rCL, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RCR8ri, X86_INS_RCR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDFSBASE, X86_INS_RDFSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDFSBASE64, X86_INS_RDFSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDGSBASE, X86_INS_RDGSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDGSBASE64, X86_INS_RDGSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RDMSR, X86_INS_RDMSR, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { X86_REG_EAX, X86_REG_EDX, 0 }, { 0 }, 0, 0 #endif }, { X86_RDPID32, X86_INS_RDPID, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDPID64, X86_INS_RDPID, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDPKRUr, X86_INS_RDPKRU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDPMC, X86_INS_RDPMC, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_RDRAND16r, X86_INS_RDRAND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDRAND32r, X86_INS_RDRAND, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDRAND64r, X86_INS_RDRAND, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSEED16r, X86_INS_RDSEED, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSEED32r, X86_INS_RDSEED, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSEED64r, X86_INS_RDSEED, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RDSSPD, X86_INS_RDSSPD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDSSPQ, X86_INS_RDSSPQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RDTSC, X86_INS_RDTSC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_RAX, X86_REG_RDX, 0 }, { 0 }, 0, 0 #endif }, { X86_RDTSCP, X86_INS_RDTSCP, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_RAX, X86_REG_RCX, X86_REG_RDX, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_REPNE_PREFIX, X86_INS_REPNE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_REP_PREFIX, X86_INS_REP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_RETIL, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_RETIQ, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RETIW, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_RETL, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_RETQ, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_RETW, X86_INS_RET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_RET, 0 }, 0, 0 #endif }, { X86_REX64_PREFIX, X86_INS_REX64, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16m1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16mCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16mi, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16r1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16rCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL16ri, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32m1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32mCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32mi, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32r1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32rCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL32ri, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64m1, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64mCL, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64mi, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64r1, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64rCL, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL64ri, X86_INS_ROL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8m1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8mCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8mi, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8r1, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8rCL, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROL8ri, X86_INS_ROL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16m1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16mCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16mi, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16r1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16rCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR16ri, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32m1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32mCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32mi, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32r1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32rCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR32ri, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64m1, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64mCL, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64mi, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64r1, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64rCL, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR64ri, X86_INS_ROR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8m1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8mCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8mi, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8r1, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8rCL, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_ROR8ri, X86_INS_ROR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_RORX32mi, X86_INS_RORX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RORX32ri, X86_INS_RORX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RORX64mi, X86_INS_RORX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RORX64ri, X86_INS_RORX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_RSM, X86_INS_RSM, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_RSTORSSP, X86_INS_RSTORSSP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SAHF, X86_INS_SAHF, 0, #ifndef CAPSTONE_DIET { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16m1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16mCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16mi, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16r1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16rCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL16ri, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32m1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32mCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32mi, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32r1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32rCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL32ri, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64m1, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64mCL, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64mi, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64r1, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64rCL, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL64ri, X86_INS_SAL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8m1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8mCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8mi, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8r1, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8rCL, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAL8ri, X86_INS_SAL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SALC, X86_INS_SALC, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SAR16m1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16mCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16mi, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16r1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16rCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR16ri, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32m1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32mCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32mi, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32r1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32rCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR32ri, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64m1, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64mCL, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64mi, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64r1, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64rCL, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR64ri, X86_INS_SAR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8m1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8mCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8mi, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8r1, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8rCL, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SAR8ri, X86_INS_SAR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SARX32rm, X86_INS_SARX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SARX32rr, X86_INS_SARX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SARX64rm, X86_INS_SARX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SARX64rr, X86_INS_SARX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SAVEPREVSSP, X86_INS_SAVEPREVSSP, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16i16, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16mi, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16mi8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16mr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16ri, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16ri8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16rm, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16rr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB16rr_REV, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32i32, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32mi, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32mi8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32mr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32ri, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32ri8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32rm, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32rr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB32rr_REV, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64i32, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64mi32, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64mi8, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64mr, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64ri32, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64ri8, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64rm, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64rr, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB64rr_REV, X86_INS_SBB, 1, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8i8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8mi, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8mi8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SBB8mr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8ri, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8ri8, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SBB8rm, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8rr, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SBB8rr_REV, X86_INS_SBB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASB, X86_INS_SCASB, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASL, X86_INS_SCASD, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASQ, X86_INS_SCASQ, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SCASW, X86_INS_SCASW, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SETAEm, X86_INS_SETAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETAEr, X86_INS_SETAE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETAm, X86_INS_SETA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETAr, X86_INS_SETA, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBEm, X86_INS_SETBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBEr, X86_INS_SETBE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBm, X86_INS_SETB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETBr, X86_INS_SETB, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETEm, X86_INS_SETE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETEr, X86_INS_SETE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGEm, X86_INS_SETGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGEr, X86_INS_SETGE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGm, X86_INS_SETG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETGr, X86_INS_SETG, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLEm, X86_INS_SETLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLEr, X86_INS_SETLE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLm, X86_INS_SETL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETLr, X86_INS_SETL, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNEm, X86_INS_SETNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNEr, X86_INS_SETNE, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNOm, X86_INS_SETNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNOr, X86_INS_SETNO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNPm, X86_INS_SETNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNPr, X86_INS_SETNP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNSm, X86_INS_SETNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETNSr, X86_INS_SETNS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETOm, X86_INS_SETO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETOr, X86_INS_SETO, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETPm, X86_INS_SETP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETPr, X86_INS_SETP, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETSSBSY, X86_INS_SETSSBSY, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETSm, X86_INS_SETS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SETSr, X86_INS_SETS, 0, #ifndef CAPSTONE_DIET { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SGDT16m, X86_INS_SGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SGDT32m, X86_INS_SGDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SGDT64m, X86_INS_SGDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_SHL16m1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16mCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16mi, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16r1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16rCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL16ri, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32m1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32mCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32mi, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32r1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32rCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL32ri, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64m1, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64mCL, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64mi, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64r1, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64rCL, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL64ri, X86_INS_SHL, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8m1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8mCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8mi, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8r1, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8rCL, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHL8ri, X86_INS_SHL, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16mrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16mri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16rrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD16rri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32mrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32mri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32rrCL, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD32rri8, X86_INS_SHLD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64mrCL, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64mri8, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64rrCL, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLD64rri8, X86_INS_SHLD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHLX32rm, X86_INS_SHLX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHLX32rr, X86_INS_SHLX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHLX64rm, X86_INS_SHLX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHLX64rr, X86_INS_SHLX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHR16m1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16mCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16mi, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16r1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16rCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR16ri, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32m1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32mCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32mi, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32r1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32rCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR32ri, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64m1, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64mCL, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64mi, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64r1, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64rCL, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR64ri, X86_INS_SHR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8m1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8mCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8mi, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8r1, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8rCL, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHR8ri, X86_INS_SHR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16mrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16mri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16rrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD16rri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32mrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32mri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32rrCL, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD32rri8, X86_INS_SHRD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64mrCL, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64mri8, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64rrCL, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRD64rri8, X86_INS_SHRD, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SHRX32rm, X86_INS_SHRX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHRX32rr, X86_INS_SHRX, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHRX64rm, X86_INS_SHRX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SHRX64rr, X86_INS_SHRX, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_BMI2, 0 }, 0, 0 #endif }, { X86_SIDT16m, X86_INS_SIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SIDT32m, X86_INS_SIDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SIDT64m, X86_INS_SIDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_SKINIT, X86_INS_SKINIT, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_SLDT16m, X86_INS_SLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLDT16r, X86_INS_SLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLDT32r, X86_INS_SLDT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLDT64r, X86_INS_SLDT, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLWPCB, X86_INS_SLWPCB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SLWPCB64, X86_INS_SLWPCB, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW16m, X86_INS_SMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW16r, X86_INS_SMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW32r, X86_INS_SMSW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_SMSW64r, X86_INS_SMSW, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_STAC, X86_INS_STAC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STC, X86_INS_STC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_STD, X86_INS_STD, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_STGI, X86_INS_STGI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_STI, X86_INS_STI, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STOSB, X86_INS_STOSB, 0, #ifndef CAPSTONE_DIET { X86_REG_AL, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STOSL, X86_INS_STOSD, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STOSQ, X86_INS_STOSQ, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RCX, X86_REG_RDI, X86_REG_EFLAGS, 0 }, { X86_REG_RCX, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STOSW, X86_INS_STOSW, 0, #ifndef CAPSTONE_DIET { X86_REG_AX, X86_REG_EDI, X86_REG_EFLAGS, 0 }, { X86_REG_EDI, 0 }, { 0 }, 0, 0 #endif }, { X86_STR16r, X86_INS_STR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STR32r, X86_INS_STR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STR64r, X86_INS_STR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_STRm, X86_INS_STR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_SUB16i16, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16mi, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16mi8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16mr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16ri, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16ri8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16rm, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16rr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB16rr_REV, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32i32, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32mi, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32mi8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32mr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32ri, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32ri8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32rm, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32rr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB32rr_REV, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64i32, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64mi32, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64mi8, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64mr, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64ri32, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64ri8, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64rm, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64rr, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB64rr_REV, X86_INS_SUB, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8i8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8mi, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8mi8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SUB8mr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8ri, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8ri8, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_SUB8rm, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8rr, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SUB8rr_REV, X86_INS_SUB, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_SWAPGS, X86_INS_SWAPGS, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_SYSCALL, X86_INS_SYSCALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_SYSENTER, X86_INS_SYSENTER, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_INT, 0 }, 0, 0 #endif }, { X86_SYSEXIT, X86_INS_SYSEXIT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_SYSEXIT64, X86_INS_SYSEXITQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_SYSRET, X86_INS_SYSRET, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_IRET, 0 }, 0, 0 #endif }, { X86_SYSRET64, X86_INS_SYSRETQ, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_IRET, X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_T1MSKC32rm, X86_INS_T1MSKC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_T1MSKC32rr, X86_INS_T1MSKC, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_T1MSKC64rm, X86_INS_T1MSKC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_T1MSKC64rr, X86_INS_T1MSKC, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TEST16i16, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16mi, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16mi_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16mr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16ri, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16ri_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST16rr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32i32, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32mi, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32mi_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32mr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32ri, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32ri_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST32rr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64i32, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64mi32, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64mi32_alt, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64mr, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64ri32, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64ri32_alt, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST64rr, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8i8, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8mi, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8mi_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8mr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8ri, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8ri_alt, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TEST8rr, X86_INS_TEST, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_TPAUSE, X86_INS_TPAUSE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_TZCNT16rm, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT16rr, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT32rm, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT32rr, X86_INS_TZCNT, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT64rm, X86_INS_TZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZCNT64rr, X86_INS_TZCNT, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_BMI, 0 }, 0, 0 #endif }, { X86_TZMSK32rm, X86_INS_TZMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TZMSK32rr, X86_INS_TZMSK, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TZMSK64rm, X86_INS_TZMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_TZMSK64rr, X86_INS_TZMSK, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_TBM, 0 }, 0, 0 #endif }, { X86_UD0, X86_INS_UD0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UD1, X86_INS_UD1, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UD2, X86_INS_UD2, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMONITOR16, X86_INS_UMONITOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMONITOR32, X86_INS_UMONITOR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMONITOR64, X86_INS_UMONITOR, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_UMWAIT, X86_INS_UMWAIT, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERRm, X86_INS_VERR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERRr, X86_INS_VERR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERWm, X86_INS_VERW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VERWr, X86_INS_VERW, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMCALL, X86_INS_VMCALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMCLEARm, X86_INS_VMCLEAR, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMFUNC, X86_INS_VMFUNC, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMLAUNCH, X86_INS_VMLAUNCH, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMLOAD32, X86_INS_VMLOAD, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMLOAD64, X86_INS_VMLOAD, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMMCALL, X86_INS_VMMCALL, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMPTRLDm, X86_INS_VMPTRLD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMPTRSTm, X86_INS_VMPTRST, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMREAD32mr, X86_INS_VMREAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMREAD32rr, X86_INS_VMREAD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMREAD64mr, X86_INS_VMREAD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_VMREAD64rr, X86_INS_VMREAD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMRESUME, X86_INS_VMRESUME, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMRUN32, X86_INS_VMRUN, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMRUN64, X86_INS_VMRUN, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMSAVE32, X86_INS_VMSAVE, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMSAVE64, X86_INS_VMSAVE, 1, #ifndef CAPSTONE_DIET { X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMWRITE32rm, X86_INS_VMWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMWRITE32rr, X86_INS_VMWRITE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_VMWRITE64rm, X86_INS_VMWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMWRITE64rr, X86_INS_VMWRITE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_VMXOFF, X86_INS_VMXOFF, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_VMXON, X86_INS_VMXON, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_VM, 0 }, 0, 0 #endif }, { X86_WBINVD, X86_INS_WBINVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_WBNOINVD, X86_INS_WBNOINVD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRFSBASE, X86_INS_WRFSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRFSBASE64, X86_INS_WRFSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRGSBASE, X86_INS_WRGSBASE, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRGSBASE64, X86_INS_WRGSBASE, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_FSGSBASE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_WRMSR, X86_INS_WRMSR, 0, #ifndef CAPSTONE_DIET { X86_REG_EAX, X86_REG_ECX, X86_REG_EDX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_WRPKRUr, X86_INS_WRPKRU, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRSSD, X86_INS_WRSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRSSQ, X86_INS_WRSSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRUSSD, X86_INS_WRUSSD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_WRUSSQ, X86_INS_WRUSSQ, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD16rm, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD16rr, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD32rm, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD32rr, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD64rm, X86_INS_XADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD64rr, X86_INS_XADD, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD8rm, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XADD8rr, X86_INS_XADD, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG16ar, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG16rm, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG16rr, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG32ar, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_XCHG32rm, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG32rr, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG64ar, X86_INS_XCHG, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG64rm, X86_INS_XCHG, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG64rr, X86_INS_XCHG, 1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG8rm, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCHG8rr, X86_INS_XCHG, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTCBC, X86_INS_XCRYPTCBC, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTCFB, X86_INS_XCRYPTCFB, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTCTR, X86_INS_XCRYPTCTR, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTECB, X86_INS_XCRYPTECB, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XCRYPTOFB, X86_INS_XCRYPTOFB, 0, #ifndef CAPSTONE_DIET { X86_REG_RBX, X86_REG_RDX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XGETBV, X86_INS_XGETBV, 0, #ifndef CAPSTONE_DIET { X86_REG_ECX, 0 }, { X86_REG_EDX, X86_REG_EAX, 0 }, { 0 }, 0, 0 #endif }, { X86_XLAT, X86_INS_XLATB, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16i16, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16mi, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16mi8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16mr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16ri, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16ri8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16rm, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16rr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR16rr_REV, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32i32, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32mi, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32mi8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32mr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32ri, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32ri8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32rm, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32rr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR32rr_REV, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64i32, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64mi32, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64mi8, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64mr, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64ri32, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64ri8, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64rm, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64rr, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR64rr_REV, X86_INS_XOR, 1, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8i8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8mi, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8mi8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_XOR8mr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8ri, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8ri8, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 #endif }, { X86_XOR8rm, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8rr, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XOR8rr_REV, X86_INS_XOR, 0, #ifndef CAPSTONE_DIET { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, { X86_XRSTOR, X86_INS_XRSTOR, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XRSTOR64, X86_INS_XRSTOR64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XRSTORS, X86_INS_XRSTORS, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_XRSTORS64, X86_INS_XRSTORS64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVE, X86_INS_XSAVE, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVE64, X86_INS_XSAVE64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVEC, X86_INS_XSAVEC, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVEC64, X86_INS_XSAVEC64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVEOPT, X86_INS_XSAVEOPT, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVEOPT64, X86_INS_XSAVEOPT64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSAVES, X86_INS_XSAVES, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { X86_XSAVES64, X86_INS_XSAVES64, 1, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RAX, 0 }, { 0 }, { X86_GRP_MODE64, 0 }, 0, 0 #endif }, { X86_XSETBV, X86_INS_XSETBV, 0, #ifndef CAPSTONE_DIET { X86_REG_EDX, X86_REG_EAX, X86_REG_ECX, 0 }, { 0 }, { X86_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, { X86_XSHA1, X86_INS_XSHA1, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XSHA256, X86_INS_XSHA256, 0, #ifndef CAPSTONE_DIET { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RSI, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, { X86_XSTORE, X86_INS_XSTORE, 0, #ifndef CAPSTONE_DIET { X86_REG_RDX, X86_REG_RDI, 0 }, { X86_REG_RAX, X86_REG_RDI, 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/X86/X86MappingReg.inc000064400000000000000000000164140072674642500205450ustar 00000000000000/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ { X86_AH, X86_REG_AH }, { X86_AL, X86_REG_AL }, { X86_AX, X86_REG_AX }, { X86_BH, X86_REG_BH }, { X86_BL, X86_REG_BL }, { X86_BP, X86_REG_BP }, { X86_BPH, 0 }, { X86_BPL, X86_REG_BPL }, { X86_BX, X86_REG_BX }, { X86_CH, X86_REG_CH }, { X86_CL, X86_REG_CL }, { X86_CS, X86_REG_CS }, { X86_CX, X86_REG_CX }, { X86_DF, 0 }, { X86_DH, X86_REG_DH }, { X86_DI, X86_REG_DI }, { X86_DIH, 0 }, { X86_DIL, X86_REG_DIL }, { X86_DL, X86_REG_DL }, { X86_DS, X86_REG_DS }, { X86_DX, X86_REG_DX }, { X86_EAX, X86_REG_EAX }, { X86_EBP, X86_REG_EBP }, { X86_EBX, X86_REG_EBX }, { X86_ECX, X86_REG_ECX }, { X86_EDI, X86_REG_EDI }, { X86_EDX, X86_REG_EDX }, { X86_EFLAGS, X86_REG_EFLAGS }, { X86_EIP, X86_REG_EIP }, { X86_EIZ, X86_REG_EIZ }, { X86_ES, X86_REG_ES }, { X86_ESI, X86_REG_ESI }, { X86_ESP, X86_REG_ESP }, { X86_FPSW, X86_REG_FPSW }, { X86_FS, X86_REG_FS }, { X86_GS, X86_REG_GS }, { X86_HAX, 0 }, { X86_HBP, 0 }, { X86_HBX, 0 }, { X86_HCX, 0 }, { X86_HDI, 0 }, { X86_HDX, 0 }, { X86_HIP, 0 }, { X86_HSI, 0 }, { X86_HSP, 0 }, { X86_IP, X86_REG_IP }, { X86_RAX, X86_REG_RAX }, { X86_RBP, X86_REG_RBP }, { X86_RBX, X86_REG_RBX }, { X86_RCX, X86_REG_RCX }, { X86_RDI, X86_REG_RDI }, { X86_RDX, X86_REG_RDX }, { X86_RIP, X86_REG_RIP }, { X86_RIZ, X86_REG_RIZ }, { X86_RSI, X86_REG_RSI }, { X86_RSP, X86_REG_RSP }, { X86_SI, X86_REG_SI }, { X86_SIH, 0 }, { X86_SIL, X86_REG_SIL }, { X86_SP, X86_REG_SP }, { X86_SPH, 0 }, { X86_SPL, X86_REG_SPL }, { X86_SS, X86_REG_SS }, { X86_SSP, 0 }, { X86_BND0, X86_REG_BND0 }, { X86_BND1, X86_REG_BND1 }, { X86_BND2, X86_REG_BND2 }, { X86_BND3, X86_REG_BND3 }, { X86_CR0, X86_REG_CR0 }, { X86_CR1, X86_REG_CR1 }, { X86_CR2, X86_REG_CR2 }, { X86_CR3, X86_REG_CR3 }, { X86_CR4, X86_REG_CR4 }, { X86_CR5, X86_REG_CR5 }, { X86_CR6, X86_REG_CR6 }, { X86_CR7, X86_REG_CR7 }, { X86_CR8, X86_REG_CR8 }, { X86_CR9, X86_REG_CR9 }, { X86_CR10, X86_REG_CR10 }, { X86_CR11, X86_REG_CR11 }, { X86_CR12, X86_REG_CR12 }, { X86_CR13, X86_REG_CR13 }, { X86_CR14, X86_REG_CR14 }, { X86_CR15, X86_REG_CR15 }, { X86_DR0, X86_REG_DR0 }, { X86_DR1, X86_REG_DR1 }, { X86_DR2, X86_REG_DR2 }, { X86_DR3, X86_REG_DR3 }, { X86_DR4, X86_REG_DR4 }, { X86_DR5, X86_REG_DR5 }, { X86_DR6, X86_REG_DR6 }, { X86_DR7, X86_REG_DR7 }, { X86_DR8, X86_REG_DR8 }, { X86_DR9, X86_REG_DR9 }, { X86_DR10, X86_REG_DR10 }, { X86_DR11, X86_REG_DR11 }, { X86_DR12, X86_REG_DR12 }, { X86_DR13, X86_REG_DR13 }, { X86_DR14, X86_REG_DR14 }, { X86_DR15, X86_REG_DR15 }, { X86_FP0, X86_REG_FP0 }, { X86_FP1, X86_REG_FP1 }, { X86_FP2, X86_REG_FP2 }, { X86_FP3, X86_REG_FP3 }, { X86_FP4, X86_REG_FP4 }, { X86_FP5, X86_REG_FP5 }, { X86_FP6, X86_REG_FP6 }, { X86_FP7, X86_REG_FP7 }, { X86_K0, X86_REG_K0 }, { X86_K1, X86_REG_K1 }, { X86_K2, X86_REG_K2 }, { X86_K3, X86_REG_K3 }, { X86_K4, X86_REG_K4 }, { X86_K5, X86_REG_K5 }, { X86_K6, X86_REG_K6 }, { X86_K7, X86_REG_K7 }, { X86_MM0, X86_REG_MM0 }, { X86_MM1, X86_REG_MM1 }, { X86_MM2, X86_REG_MM2 }, { X86_MM3, X86_REG_MM3 }, { X86_MM4, X86_REG_MM4 }, { X86_MM5, X86_REG_MM5 }, { X86_MM6, X86_REG_MM6 }, { X86_MM7, X86_REG_MM7 }, { X86_R8, X86_REG_R8 }, { X86_R9, X86_REG_R9 }, { X86_R10, X86_REG_R10 }, { X86_R11, X86_REG_R11 }, { X86_R12, X86_REG_R12 }, { X86_R13, X86_REG_R13 }, { X86_R14, X86_REG_R14 }, { X86_R15, X86_REG_R15 }, { X86_ST0, X86_REG_ST0 }, { X86_ST1, X86_REG_ST1 }, { X86_ST2, X86_REG_ST2 }, { X86_ST3, X86_REG_ST3 }, { X86_ST4, X86_REG_ST4 }, { X86_ST5, X86_REG_ST5 }, { X86_ST6, X86_REG_ST6 }, { X86_ST7, X86_REG_ST7 }, { X86_XMM0, X86_REG_XMM0 }, { X86_XMM1, X86_REG_XMM1 }, { X86_XMM2, X86_REG_XMM2 }, { X86_XMM3, X86_REG_XMM3 }, { X86_XMM4, X86_REG_XMM4 }, { X86_XMM5, X86_REG_XMM5 }, { X86_XMM6, X86_REG_XMM6 }, { X86_XMM7, X86_REG_XMM7 }, { X86_XMM8, X86_REG_XMM8 }, { X86_XMM9, X86_REG_XMM9 }, { X86_XMM10, X86_REG_XMM10 }, { X86_XMM11, X86_REG_XMM11 }, { X86_XMM12, X86_REG_XMM12 }, { X86_XMM13, X86_REG_XMM13 }, { X86_XMM14, X86_REG_XMM14 }, { X86_XMM15, X86_REG_XMM15 }, { X86_XMM16, X86_REG_XMM16 }, { X86_XMM17, X86_REG_XMM17 }, { X86_XMM18, X86_REG_XMM18 }, { X86_XMM19, X86_REG_XMM19 }, { X86_XMM20, X86_REG_XMM20 }, { X86_XMM21, X86_REG_XMM21 }, { X86_XMM22, X86_REG_XMM22 }, { X86_XMM23, X86_REG_XMM23 }, { X86_XMM24, X86_REG_XMM24 }, { X86_XMM25, X86_REG_XMM25 }, { X86_XMM26, X86_REG_XMM26 }, { X86_XMM27, X86_REG_XMM27 }, { X86_XMM28, X86_REG_XMM28 }, { X86_XMM29, X86_REG_XMM29 }, { X86_XMM30, X86_REG_XMM30 }, { X86_XMM31, X86_REG_XMM31 }, { X86_YMM0, X86_REG_YMM0 }, { X86_YMM1, X86_REG_YMM1 }, { X86_YMM2, X86_REG_YMM2 }, { X86_YMM3, X86_REG_YMM3 }, { X86_YMM4, X86_REG_YMM4 }, { X86_YMM5, X86_REG_YMM5 }, { X86_YMM6, X86_REG_YMM6 }, { X86_YMM7, X86_REG_YMM7 }, { X86_YMM8, X86_REG_YMM8 }, { X86_YMM9, X86_REG_YMM9 }, { X86_YMM10, X86_REG_YMM10 }, { X86_YMM11, X86_REG_YMM11 }, { X86_YMM12, X86_REG_YMM12 }, { X86_YMM13, X86_REG_YMM13 }, { X86_YMM14, X86_REG_YMM14 }, { X86_YMM15, X86_REG_YMM15 }, { X86_YMM16, X86_REG_YMM16 }, { X86_YMM17, X86_REG_YMM17 }, { X86_YMM18, X86_REG_YMM18 }, { X86_YMM19, X86_REG_YMM19 }, { X86_YMM20, X86_REG_YMM20 }, { X86_YMM21, X86_REG_YMM21 }, { X86_YMM22, X86_REG_YMM22 }, { X86_YMM23, X86_REG_YMM23 }, { X86_YMM24, X86_REG_YMM24 }, { X86_YMM25, X86_REG_YMM25 }, { X86_YMM26, X86_REG_YMM26 }, { X86_YMM27, X86_REG_YMM27 }, { X86_YMM28, X86_REG_YMM28 }, { X86_YMM29, X86_REG_YMM29 }, { X86_YMM30, X86_REG_YMM30 }, { X86_YMM31, X86_REG_YMM31 }, { X86_ZMM0, X86_REG_ZMM0 }, { X86_ZMM1, X86_REG_ZMM1 }, { X86_ZMM2, X86_REG_ZMM2 }, { X86_ZMM3, X86_REG_ZMM3 }, { X86_ZMM4, X86_REG_ZMM4 }, { X86_ZMM5, X86_REG_ZMM5 }, { X86_ZMM6, X86_REG_ZMM6 }, { X86_ZMM7, X86_REG_ZMM7 }, { X86_ZMM8, X86_REG_ZMM8 }, { X86_ZMM9, X86_REG_ZMM9 }, { X86_ZMM10, X86_REG_ZMM10 }, { X86_ZMM11, X86_REG_ZMM11 }, { X86_ZMM12, X86_REG_ZMM12 }, { X86_ZMM13, X86_REG_ZMM13 }, { X86_ZMM14, X86_REG_ZMM14 }, { X86_ZMM15, X86_REG_ZMM15 }, { X86_ZMM16, X86_REG_ZMM16 }, { X86_ZMM17, X86_REG_ZMM17 }, { X86_ZMM18, X86_REG_ZMM18 }, { X86_ZMM19, X86_REG_ZMM19 }, { X86_ZMM20, X86_REG_ZMM20 }, { X86_ZMM21, X86_REG_ZMM21 }, { X86_ZMM22, X86_REG_ZMM22 }, { X86_ZMM23, X86_REG_ZMM23 }, { X86_ZMM24, X86_REG_ZMM24 }, { X86_ZMM25, X86_REG_ZMM25 }, { X86_ZMM26, X86_REG_ZMM26 }, { X86_ZMM27, X86_REG_ZMM27 }, { X86_ZMM28, X86_REG_ZMM28 }, { X86_ZMM29, X86_REG_ZMM29 }, { X86_ZMM30, X86_REG_ZMM30 }, { X86_ZMM31, X86_REG_ZMM31 }, { X86_R8B, X86_REG_R8B }, { X86_R9B, X86_REG_R9B }, { X86_R10B, X86_REG_R10B }, { X86_R11B, X86_REG_R11B }, { X86_R12B, X86_REG_R12B }, { X86_R13B, X86_REG_R13B }, { X86_R14B, X86_REG_R14B }, { X86_R15B, X86_REG_R15B }, { X86_R8BH, 0 }, { X86_R9BH, 0 }, { X86_R10BH, 0 }, { X86_R11BH, 0 }, { X86_R12BH, 0 }, { X86_R13BH, 0 }, { X86_R14BH, 0 }, { X86_R15BH, 0 }, { X86_R8D, X86_REG_R8D }, { X86_R9D, X86_REG_R9D }, { X86_R10D, X86_REG_R10D }, { X86_R11D, X86_REG_R11D }, { X86_R12D, X86_REG_R12D }, { X86_R13D, X86_REG_R13D }, { X86_R14D, X86_REG_R14D }, { X86_R15D, X86_REG_R15D }, { X86_R8W, X86_REG_R8W }, { X86_R9W, X86_REG_R9W }, { X86_R10W, X86_REG_R10W }, { X86_R11W, X86_REG_R11W }, { X86_R12W, X86_REG_R12W }, { X86_R13W, X86_REG_R13W }, { X86_R14W, X86_REG_R14W }, { X86_R15W, X86_REG_R15W }, { X86_R8WH, 0 }, { X86_R9WH, 0 }, { X86_R10WH, 0 }, { X86_R11WH, 0 }, { X86_R12WH, 0 }, { X86_R13WH, 0 }, { X86_R14WH, 0 }, { X86_R15WH, 0 }, capstone-sys-0.15.0/capstone/arch/X86/X86Module.c000064400000000000000000000041710072674642500174070ustar 00000000000000/* Capstone Disassembly Engine */ /* By Dang Hoang Vu 2013 */ #ifdef CAPSTONE_HAS_X86 #include "../../cs_priv.h" #include "../../MCRegisterInfo.h" #include "X86Disassembler.h" #include "X86InstPrinter.h" #include "X86Mapping.h" #include "X86Module.h" cs_err X86_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); X86_init(mri); // by default, we use Intel syntax ud->printer = X86_Intel_printInst; ud->syntax = CS_OPT_SYNTAX_INTEL; ud->printer_info = mri; ud->disasm = X86_getInstruction; ud->reg_name = X86_reg_name; ud->insn_id = X86_get_insn_id; ud->insn_name = X86_insn_name; ud->group_name = X86_group_name; ud->post_printer = NULL;; #ifndef CAPSTONE_DIET ud->reg_access = X86_reg_access; #endif if (ud->mode == CS_MODE_64) ud->regsize_map = regsize_map_64; else ud->regsize_map = regsize_map_32; return CS_ERR_OK; } cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value) { switch(type) { default: break; case CS_OPT_MODE: if (value == CS_MODE_64) handle->regsize_map = regsize_map_64; else handle->regsize_map = regsize_map_32; handle->mode = (cs_mode)value; break; case CS_OPT_SYNTAX: switch(value) { default: // wrong syntax value handle->errnum = CS_ERR_OPTION; return CS_ERR_OPTION; case CS_OPT_SYNTAX_DEFAULT: case CS_OPT_SYNTAX_INTEL: handle->syntax = CS_OPT_SYNTAX_INTEL; handle->printer = X86_Intel_printInst; break; case CS_OPT_SYNTAX_MASM: handle->printer = X86_Intel_printInst; handle->syntax = (int)value; break; case CS_OPT_SYNTAX_ATT: #if !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) handle->printer = X86_ATT_printInst; handle->syntax = CS_OPT_SYNTAX_ATT; break; #elif !defined(CAPSTONE_DIET) && defined(CAPSTONE_X86_ATT_DISABLE) // ATT syntax is unsupported handle->errnum = CS_ERR_X86_ATT; return CS_ERR_X86_ATT; #else // CAPSTONE_DIET // this is irrelevant in CAPSTONE_DIET mode handle->errnum = CS_ERR_DIET; return CS_ERR_DIET; #endif } break; } return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/X86/X86Module.h000064400000000000000000000004310072674642500174070ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_X86_MODULE_H #define CS_X86_MODULE_H #include "../../utils.h" cs_err X86_global_init(cs_struct *ud); cs_err X86_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreDisassembler.c000064400000000000000000000601160072674642500216660ustar 00000000000000//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_XCORE #include // DEBUG #include #include #include "../../cs_priv.h" #include "../../utils.h" #include "XCoreDisassembler.h" #include "../../MCInst.h" #include "../../MCInstrDesc.h" #include "../../MCFixedLenDisassembler.h" #include "../../MCRegisterInfo.h" #include "../../MCDisassembler.h" #include "../../MathExtras.h" static uint64_t getFeatureBits(int mode) { // support everything return (uint64_t)-1; } static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn) { if (code_len < 2) // insufficient data return false; // Encoded as a little-endian 16-bit word in the stream. *insn = (code[0] << 0) | (code[1] << 8); return true; } static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn) { if (code_len < 4) // insufficient data return false; // Encoded as a little-endian 32-bit word in the stream. *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24); return true; } static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) { const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); return rc->RegsBegin[RegNo]; } static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder); #include "XCoreGenDisassemblerTables.inc" #define GET_REGINFO_ENUM #define GET_REGINFO_MC_DESC #include "XCoreGenRegisterInfo.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 11) return MCDisassembler_Fail; Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { unsigned Reg; if (RegNo > 15) return MCDisassembler_Fail; Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo); MCOperand_CreateReg0(Inst, Reg); return MCDisassembler_Success; } static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { static const unsigned Values[] = { 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 }; if (Val > 11) return MCDisassembler_Fail; MCOperand_CreateImm0(Inst, Values[Val]); return MCDisassembler_Success; } static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, -(int64_t)Val); return MCDisassembler_Success; } static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2) { unsigned Op1High, Op2High; unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); if (Combined < 27) return MCDisassembler_Fail; if (fieldFromInstruction_4(Insn, 5, 1)) { if (Combined == 31) return MCDisassembler_Fail; Combined += 5; } Combined -= 27; Op1High = Combined % 3; Op2High = Combined / 3; *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2); *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2); return MCDisassembler_Success; } static DecodeStatus Decode3OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2, unsigned *Op3) { unsigned Op1High, Op2High, Op3High; unsigned Combined = fieldFromInstruction_4(Insn, 6, 5); if (Combined >= 27) return MCDisassembler_Fail; Op1High = Combined % 3; Op2High = (Combined / 3) % 3; Op3High = Combined / 9; *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2); *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2); *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2); return MCDisassembler_Success; } #define GET_INSTRINFO_ENUM #include "XCoreGenInstrInfo.inc" static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { // Try and decode as a 3R instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); switch (Opcode) { case 0x0: MCInst_setOpcode(Inst, XCore_STW_2rus); return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x1: MCInst_setOpcode(Inst, XCore_LDW_2rus); return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x2: MCInst_setOpcode(Inst, XCore_ADD_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x3: MCInst_setOpcode(Inst, XCore_SUB_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x4: MCInst_setOpcode(Inst, XCore_SHL_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x5: MCInst_setOpcode(Inst, XCore_SHR_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x6: MCInst_setOpcode(Inst, XCore_EQ_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x7: MCInst_setOpcode(Inst, XCore_AND_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x8: MCInst_setOpcode(Inst, XCore_OR_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x9: MCInst_setOpcode(Inst, XCore_LDW_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x10: MCInst_setOpcode(Inst, XCore_LD16S_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x11: MCInst_setOpcode(Inst, XCore_LD8U_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x12: MCInst_setOpcode(Inst, XCore_ADD_2rus); return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x13: MCInst_setOpcode(Inst, XCore_SUB_2rus); return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x14: MCInst_setOpcode(Inst, XCore_SHL_2rus); return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x15: MCInst_setOpcode(Inst, XCore_SHR_2rus); return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x16: MCInst_setOpcode(Inst, XCore_EQ_2rus); return Decode2RUSInstruction(Inst, Insn, Address, Decoder); case 0x17: MCInst_setOpcode(Inst, XCore_TSETR_3r); return Decode3RImmInstruction(Inst, Insn, Address, Decoder); case 0x18: MCInst_setOpcode(Inst, XCore_LSS_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); case 0x19: MCInst_setOpcode(Inst, XCore_LSU_3r); return Decode3RInstruction(Inst, Insn, Address, Decoder); } return MCDisassembler_Fail; } static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); MCOperand_CreateImm0(Inst, Op1); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); MCOperand_CreateImm0(Inst, Op2); return S; } static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeBitpOperand(Inst, Op2, Address, Decoder); return S; } static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2); if (S != MCDisassembler_Success) return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeBitpOperand(Inst, Op2, Address, Decoder); return S; } static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { // Try and decode as a L3R / L2RUS instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | fieldFromInstruction_4(Insn, 27, 5) << 4; switch (Opcode) { case 0x0c: MCInst_setOpcode(Inst, XCore_STW_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x1c: MCInst_setOpcode(Inst, XCore_XOR_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x2c: MCInst_setOpcode(Inst, XCore_ASHR_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x3c: MCInst_setOpcode(Inst, XCore_LDAWF_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x4c: MCInst_setOpcode(Inst, XCore_LDAWB_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x5c: MCInst_setOpcode(Inst, XCore_LDA16F_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x6c: MCInst_setOpcode(Inst, XCore_LDA16B_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x7c: MCInst_setOpcode(Inst, XCore_MUL_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x8c: MCInst_setOpcode(Inst, XCore_DIVS_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x9c: MCInst_setOpcode(Inst, XCore_DIVU_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x10c: MCInst_setOpcode(Inst, XCore_ST16_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x11c: MCInst_setOpcode(Inst, XCore_ST8_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x12c: MCInst_setOpcode(Inst, XCore_ASHR_l2rus); return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x12d: MCInst_setOpcode(Inst, XCore_OUTPW_l2rus); return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x12e: MCInst_setOpcode(Inst, XCore_INPW_l2rus); return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); case 0x13c: MCInst_setOpcode(Inst, XCore_LDAWF_l2rus); return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); case 0x14c: MCInst_setOpcode(Inst, XCore_LDAWB_l2rus); return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); case 0x15c: MCInst_setOpcode(Inst, XCore_CRC_l3r); return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); case 0x18c: MCInst_setOpcode(Inst, XCore_REMS_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x19c: MCInst_setOpcode(Inst, XCore_REMU_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); } return MCDisassembler_Fail; } static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); if (S != MCDisassembler_Success) return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); return S; } static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2; DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2); if (S != MCDisassembler_Success) return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); return S; } static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { MCOperand_CreateImm0(Inst, Op1); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); MCOperand_CreateImm0(Inst, Op3); } return S; } static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeBitpOperand(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); MCOperand_CreateImm0(Inst, Op3); } return S; } static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeBitpOperand(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3, Op4, Op5, Op6; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S != MCDisassembler_Success) return S; S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6); if (S != MCDisassembler_Success) return S; DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); return S; } static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Opcode; // Try and decode as a L6R instruction. MCInst_clear(Inst); Opcode = fieldFromInstruction_4(Insn, 27, 5); switch (Opcode) { default: break; case 0x00: MCInst_setOpcode(Inst, XCore_LMUL_l6r); return DecodeL6RInstruction(Inst, Insn, Address, Decoder); } return MCDisassembler_Fail; } static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3, Op4, Op5; DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S != MCDisassembler_Success) return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5); if (S != MCDisassembler_Success) return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); return S; } static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); } if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { unsigned Op1, Op2, Op3; unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4); DecodeStatus S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3); if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); } if (S == MCDisassembler_Success) { DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); } return S; } #define GET_SUBTARGETINFO_ENUM #include "XCoreGenInstrInfo.inc" bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, uint16_t *size, uint64_t address, void *info) { uint16_t insn16; uint32_t insn32; DecodeStatus Result; if (!readInstruction16(code, code_len, &insn16)) { return false; } if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore)); } // Calling the auto-generated decoder function. Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0); if (Result != MCDisassembler_Fail) { *size = 2; return true; } if (!readInstruction32(code, code_len, &insn32)) { return false; } // Calling the auto-generated decoder function. Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0); if (Result != MCDisassembler_Fail) { *size = 4; return true; } return false; } void XCore_init(MCRegisterInfo *MRI) { /* InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, XCoreMCRegisterClasses, 2, XCoreRegUnitRoots, 16, XCoreRegDiffLists, XCoreRegStrings, XCoreSubRegIdxLists, 1, XCoreSubRegIdxRanges, XCoreRegEncodingTable); */ MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17, 0, 0, XCoreMCRegisterClasses, 2, 0, 0, XCoreRegDiffLists, 0, XCoreSubRegIdxLists, 1, 0); } #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreDisassembler.h000064400000000000000000000006560072674642500216760ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_XCOREDISASSEMBLER_H #define CS_XCOREDISASSEMBLER_H #include "capstone/capstone.h" #include "../../MCRegisterInfo.h" #include "../../MCInst.h" void XCore_init(MCRegisterInfo *MRI); bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreGenAsmWriter.inc000064400000000000000000000564060072674642500221560ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include // debug #include /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { static const uint32_t OpInfo[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 665U, // DBG_VALUE 0U, // REG_SEQUENCE 0U, // COPY 658U, // BUNDLE 687U, // LIFETIME_START 645U, // LIFETIME_END 0U, // STACKMAP 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT 0U, // FRAME_ALLOC 2250U, // ADD_2rus 2250U, // ADD_3r 10363U, // ADJCALLSTACKDOWN 10383U, // ADJCALLSTACKUP 2361840U, // ANDNOT_2r 2255U, // AND_3r 2404U, // ASHR_l2rus 2404U, // ASHR_l3r 10769U, // BAU_1r 2099777U, // BITREV_l2r 19161U, // BLACP_lu10 19161U, // BLACP_u10 10672U, // BLAT_lu6 10672U, // BLAT_u6 10425U, // BLA_1r 10510U, // BLRB_lu10 10510U, // BLRB_u10 10510U, // BLRF_lu10 10510U, // BLRF_u10 2099418U, // BRBF_lru6 2099418U, // BRBF_ru6 2099638U, // BRBT_lru6 2099638U, // BRBT_ru6 10774U, // BRBU_lu6 10774U, // BRBU_u6 2099418U, // BRFF_lru6 2099418U, // BRFF_ru6 2099638U, // BRFT_lru6 2099638U, // BRFT_ru6 10774U, // BRFU_lu6 10774U, // BRFU_u6 10791U, // BRU_1r 553511U, // BR_JT 815655U, // BR_JT32 2099768U, // BYTEREV_l2r 2132815U, // CHKCT_2r 2132815U, // CHKCT_rus 1163U, // CLRE_0R 19301U, // CLRPT_1R 10614U, // CLRSR_branch_lu6 10614U, // CLRSR_branch_u6 10614U, // CLRSR_lu6 10614U, // CLRSR_u6 2099807U, // CLZ_l2r 5247047U, // CRC8_l4r 17041459U, // CRC_l3r 1168U, // DCALL_0R 1200U, // DENTSP_0R 10488U, // DGETREG_1r 2474U, // DIVS_l3r 2610U, // DIVU_l3r 1207U, // DRESTSP_0R 1242U, // DRET_0R 10475U, // ECALLF_1r 10723U, // ECALLT_1r 19342U, // EDU_1r 6334686U, // EEF_2r 6334929U, // EET_2r 19351U, // EEU_1r 2099310U, // EH_RETURN 6334765U, // ENDIN_2r 10569U, // ENTSP_lu6 10569U, // ENTSP_u6 2400U, // EQ_2rus 2400U, // EQ_3r 10554U, // EXTDP_lu6 10554U, // EXTDP_u6 10585U, // EXTSP_lu6 10585U, // EXTSP_u6 10401U, // FRAME_TO_ARGS_OFFSET 19256U, // FREER_1r 1236U, // FREET_0R 6334676U, // GETD_l2r 1139U, // GETED_0R 1224U, // GETET_0R 1151U, // GETID_0R 1174U, // GETKEP_0R 1187U, // GETKSP_0R 6334772U, // GETN_l2r 51670U, // GETPS_l2r 2099588U, // GETR_rus 10252U, // GETSR_lu6 10252U, // GETSR_u6 6334968U, // GETST_2r 6334883U, // GETTS_2r 6334906U, // INCT_2r 62438U, // INITCP_2r 70630U, // INITDP_2r 78822U, // INITLR_l2r 87014U, // INITPC_2r 95206U, // INITSP_2r 8432212U, // INPW_l2rus 6596970U, // INSHR_2r 6334955U, // INT_2r 6334768U, // IN_2r 675U, // Int_MemBarrier 10528U, // KCALL_1r 10528U, // KCALL_lu6 10528U, // KCALL_u6 10568U, // KENTSP_lu6 10568U, // KENTSP_u6 10576U, // KRESTSP_lu6 10576U, // KRESTSP_u6 1247U, // KRET_0R 45093065U, // LADD_l5r 12585354U, // LD16S_3r 12585483U, // LD8U_3r 14682170U, // LDA16B_l3r 12585018U, // LDA16F_l3r 10241U, // LDAPB_lu10 10241U, // LDAPB_u10 10241U, // LDAPF_lu10 10241U, // LDAPF_lu10_ba 10241U, // LDAPF_u10 14682697U, // LDAWB_l2rus 14682697U, // LDAWB_l3r 19134U, // LDAWCP_lu6 19134U, // LDAWCP_u6 100937U, // LDAWDP_lru6 100937U, // LDAWDP_ru6 2099282U, // LDAWFI 12585545U, // LDAWF_l2rus 12585545U, // LDAWF_l3r 109129U, // LDAWSP_lru6 109129U, // LDAWSP_ru6 2099396U, // LDC_lru6 2099396U, // LDC_ru6 1105U, // LDET_0R 184551985U, // LDIVU_l5r 1075U, // LDSED_0R 1015U, // LDSPC_0R 1045U, // LDSSR_0R 117327U, // LDWCP_lru6 19148U, // LDWCP_lu10 117327U, // LDWCP_ru6 19148U, // LDWCP_u10 100943U, // LDWDP_lru6 100943U, // LDWDP_ru6 2099292U, // LDWFI 109135U, // LDWSP_lru6 109135U, // LDWSP_ru6 12585551U, // LDW_2rus 12585551U, // LDW_3r 268437799U, // LMUL_l6r 2462U, // LSS_3r 45093054U, // LSUB_l5r 2604U, // LSU_3r 452987281U, // MACCS_l4r 452987418U, // MACCU_l4r 19224U, // MJOIN_1r 2099463U, // MKMSK_2r 2099463U, // MKMSK_rus 19169U, // MSYNC_1r 2344U, // MUL_l3r 2099443U, // NEG 2099699U, // NOT 2418U, // OR_3r 2132826U, // OUTCT_2r 2132826U, // OUTCT_rus 78681013U, // OUTPW_l2rus 2136899U, // OUTSHR_2r 2132859U, // OUTT_2r 2132869U, // OUT_2r 6334721U, // PEEK_2r 2456U, // REMS_l3r 2593U, // REMU_l3r 10561U, // RETSP_lu6 10561U, // RETSP_u6 612U, // SELECT_CC 2132748U, // SETCLK_l2r 10264U, // SETCP_1r 2132728U, // SETC_l2r 2132728U, // SETC_lru6 2132728U, // SETC_ru6 10273U, // SETDP_1r 2132738U, // SETD_2r 125856U, // SETEV_1r 632U, // SETKEP_0R 2132771U, // SETN_l2r 2132716U, // SETPSC_2r 2132951U, // SETPS_l2r 2132848U, // SETPT_2r 2132939U, // SETRDY_l2r 10282U, // SETSP_1r 10621U, // SETSR_branch_lu6 10621U, // SETSR_branch_u6 10621U, // SETSR_lu6 10621U, // SETSR_u6 2132928U, // SETTW_l2r 125867U, // SETV_1r 2361855U, // SEXT_2r 2361855U, // SEXT_rus 2331U, // SHL_2rus 2331U, // SHL_3r 2405U, // SHR_2rus 2405U, // SHR_3r 1133U, // SSYNC_0r 12585025U, // ST16_l3r 12585037U, // ST8_l3r 1119U, // STET_0R 1090U, // STSED_0R 1030U, // STSPC_0R 1060U, // STSSR_0R 100954U, // STWDP_lru6 100954U, // STWDP_ru6 2099301U, // STWFI 109146U, // STWSP_lru6 109146U, // STWSP_ru6 12585562U, // STW_2rus 12585562U, // STW_l3r 2239U, // SUB_2rus 2239U, // SUB_3r 19245U, // SYNCR_1r 6334912U, // TESTCT_2r 6334738U, // TESTLCL_l2r 6334920U, // TESTWCT_2r 2100415U, // TSETMR_2r 138207U, // TSETR_3r 19438U, // TSTART_1R 10467U, // WAITEF_1R 10715U, // WAITET_1R 1252U, // WAITEU_0R 2417U, // XOR_l3r 2361861U, // ZEXT_2r 2361861U, // ZEXT_rus 0U }; static const char AsmStrs[] = { /* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0, /* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0, /* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0, /* 32 */ 's', 'e', 't', 32, 'd', 'p', ',', 32, 0, /* 41 */ 's', 'e', 't', 32, 's', 'p', ',', 32, 0, /* 50 */ 'c', 'r', 'c', '3', '2', 32, 0, /* 57 */ 'l', 'd', 'a', '1', '6', 32, 0, /* 64 */ 's', 't', '1', '6', 32, 0, /* 70 */ 'c', 'r', 'c', '8', 32, 0, /* 76 */ 's', 't', '8', 32, 0, /* 81 */ '#', 32, 'L', 'D', 'A', 'W', 'F', 'I', 32, 0, /* 91 */ '#', 32, 'L', 'D', 'W', 'F', 'I', 32, 0, /* 100 */ '#', 32, 'S', 'T', 'W', 'F', 'I', 32, 0, /* 109 */ '#', 32, 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 32, 0, /* 122 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0, /* 142 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0, /* 160 */ '#', 32, 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 32, 0, /* 184 */ 'b', 'l', 'a', 32, 0, /* 189 */ 'l', 's', 'u', 'b', 32, 0, /* 195 */ 'l', 'd', 'c', 32, 0, /* 200 */ 'l', 'a', 'd', 'd', 32, 0, /* 206 */ 'a', 'n', 'd', 32, 0, /* 211 */ 'g', 'e', 't', 'd', 32, 0, /* 217 */ 'b', 'f', 32, 0, /* 221 */ 'e', 'e', 'f', 32, 0, /* 226 */ 'w', 'a', 'i', 't', 'e', 'f', 32, 0, /* 234 */ 'e', 'c', 'a', 'l', 'l', 'f', 32, 0, /* 242 */ 'n', 'e', 'g', 32, 0, /* 247 */ 'd', 'g', 'e', 't', 'r', 'e', 'g', 32, 0, /* 256 */ 'p', 'e', 'e', 'k', 32, 0, /* 262 */ 'm', 'k', 'm', 's', 'k', 32, 0, /* 269 */ 'b', 'l', 32, 0, /* 273 */ 't', 'e', 's', 't', 'l', 'c', 'l', 32, 0, /* 282 */ 's', 'h', 'l', 32, 0, /* 287 */ 'k', 'c', 'a', 'l', 'l', 32, 0, /* 294 */ 'l', 'm', 'u', 'l', 32, 0, /* 300 */ 'e', 'n', 'd', 'i', 'n', 32, 0, /* 307 */ 'g', 'e', 't', 'n', 32, 0, /* 313 */ 'e', 'x', 't', 'd', 'p', 32, 0, /* 320 */ 'r', 'e', 't', 's', 'p', 32, 0, /* 327 */ 'k', 'e', 'n', 't', 's', 'p', 32, 0, /* 335 */ 'k', 'r', 'e', 's', 't', 's', 'p', 32, 0, /* 344 */ 'e', 'x', 't', 's', 'p', 32, 0, /* 351 */ 'e', 'q', 32, 0, /* 355 */ 'a', 's', 'h', 'r', 32, 0, /* 361 */ 'i', 'n', 's', 'h', 'r', 32, 0, /* 368 */ 'x', 'o', 'r', 32, 0, /* 373 */ 'c', 'l', 'r', 's', 'r', 32, 0, /* 380 */ 's', 'e', 't', 's', 'r', 32, 0, /* 387 */ 'g', 'e', 't', 'r', 32, 0, /* 393 */ 'l', 'd', '1', '6', 's', 32, 0, /* 400 */ 'm', 'a', 'c', 'c', 's', 32, 0, /* 407 */ 'r', 'e', 'm', 's', 32, 0, /* 413 */ 'l', 's', 's', 32, 0, /* 418 */ 'g', 'e', 't', 't', 's', 32, 0, /* 425 */ 'd', 'i', 'v', 's', 32, 0, /* 431 */ 'b', 'l', 'a', 't', 32, 0, /* 437 */ 'b', 't', 32, 0, /* 441 */ 'i', 'n', 'c', 't', 32, 0, /* 447 */ 't', 'e', 's', 't', 'c', 't', 32, 0, /* 455 */ 't', 'e', 's', 't', 'w', 'c', 't', 32, 0, /* 464 */ 'e', 'e', 't', 32, 0, /* 469 */ 'g', 'e', 't', 32, 0, /* 474 */ 'w', 'a', 'i', 't', 'e', 't', 32, 0, /* 482 */ 'e', 'c', 'a', 'l', 'l', 't', 32, 0, /* 490 */ 'i', 'n', 't', 32, 0, /* 495 */ 'a', 'n', 'd', 'n', 'o', 't', 32, 0, /* 503 */ 'g', 'e', 't', 's', 't', 32, 0, /* 510 */ 's', 'e', 'x', 't', 32, 0, /* 516 */ 'z', 'e', 'x', 't', 32, 0, /* 522 */ 'l', 'd', '8', 'u', 32, 0, /* 528 */ 'b', 'a', 'u', 32, 0, /* 533 */ 'b', 'u', 32, 0, /* 537 */ 'm', 'a', 'c', 'c', 'u', 32, 0, /* 544 */ 'r', 'e', 'm', 'u', 32, 0, /* 550 */ 'b', 'r', 'u', 32, 0, /* 555 */ 'l', 's', 'u', 32, 0, /* 560 */ 'l', 'd', 'i', 'v', 'u', 32, 0, /* 567 */ 'b', 'y', 't', 'e', 'r', 'e', 'v', 32, 0, /* 576 */ 'b', 'i', 't', 'r', 'e', 'v', 32, 0, /* 584 */ 'l', 'd', 'a', 'w', 32, 0, /* 590 */ 'l', 'd', 'w', 32, 0, /* 595 */ 'i', 'n', 'p', 'w', 32, 0, /* 601 */ 's', 't', 'w', 32, 0, /* 606 */ 'c', 'l', 'z', 32, 0, /* 611 */ '#', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, /* 631 */ 's', 'e', 't', 32, 'k', 'e', 'p', ',', 32, 'r', '1', '1', 0, /* 644 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, /* 657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, /* 664 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, /* 674 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, /* 686 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, /* 701 */ 'l', 'd', 'a', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0, /* 715 */ 'l', 'd', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0, /* 728 */ 'b', 'l', 'a', 32, 'c', 'p', '[', 0, /* 736 */ 'm', 's', 'y', 'n', 'c', 32, 'r', 'e', 's', '[', 0, /* 747 */ 's', 'e', 't', 'p', 's', 'c', 32, 'r', 'e', 's', '[', 0, /* 759 */ 's', 'e', 't', 'c', 32, 'r', 'e', 's', '[', 0, /* 769 */ 's', 'e', 't', 'd', 32, 'r', 'e', 's', '[', 0, /* 779 */ 's', 'e', 't', 'c', 'l', 'k', 32, 'r', 'e', 's', '[', 0, /* 791 */ 'm', 'j', 'o', 'i', 'n', 32, 'r', 'e', 's', '[', 0, /* 802 */ 's', 'e', 't', 'n', 32, 'r', 'e', 's', '[', 0, /* 812 */ 's', 'y', 'n', 'c', 'r', 32, 'r', 'e', 's', '[', 0, /* 823 */ 'f', 'r', 'e', 'e', 'r', 32, 'r', 'e', 's', '[', 0, /* 834 */ 'o', 'u', 't', 's', 'h', 'r', 32, 'r', 'e', 's', '[', 0, /* 846 */ 'c', 'h', 'k', 'c', 't', 32, 'r', 'e', 's', '[', 0, /* 857 */ 'o', 'u', 't', 'c', 't', 32, 'r', 'e', 's', '[', 0, /* 868 */ 'c', 'l', 'r', 'p', 't', 32, 'r', 'e', 's', '[', 0, /* 879 */ 's', 'e', 't', 'p', 't', 32, 'r', 'e', 's', '[', 0, /* 890 */ 'o', 'u', 't', 't', 32, 'r', 'e', 's', '[', 0, /* 900 */ 'o', 'u', 't', 32, 'r', 'e', 's', '[', 0, /* 909 */ 'e', 'd', 'u', 32, 'r', 'e', 's', '[', 0, /* 918 */ 'e', 'e', 'u', 32, 'r', 'e', 's', '[', 0, /* 927 */ 's', 'e', 't', 'e', 'v', 32, 'r', 'e', 's', '[', 0, /* 938 */ 's', 'e', 't', 'v', 32, 'r', 'e', 's', '[', 0, /* 948 */ 'o', 'u', 't', 'p', 'w', 32, 'r', 'e', 's', '[', 0, /* 959 */ 's', 'e', 't', 't', 'w', 32, 'r', 'e', 's', '[', 0, /* 970 */ 's', 'e', 't', 'r', 'd', 'y', 32, 'r', 'e', 's', '[', 0, /* 982 */ 's', 'e', 't', 32, 'p', 's', '[', 0, /* 990 */ 's', 'e', 't', 32, 't', '[', 0, /* 997 */ 'i', 'n', 'i', 't', 32, 't', '[', 0, /* 1005 */ 's', 't', 'a', 'r', 't', 32, 't', '[', 0, /* 1014 */ 'l', 'd', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0, /* 1029 */ 's', 't', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0, /* 1044 */ 'l', 'd', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0, /* 1059 */ 's', 't', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0, /* 1074 */ 'l', 'd', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0, /* 1089 */ 's', 't', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0, /* 1104 */ 'l', 'd', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0, /* 1118 */ 's', 't', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0, /* 1132 */ 's', 's', 'y', 'n', 'c', 0, /* 1138 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 'd', 0, /* 1150 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'i', 'd', 0, /* 1162 */ 'c', 'l', 'r', 'e', 0, /* 1167 */ 'd', 'c', 'a', 'l', 'l', 0, /* 1173 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 'e', 'p', 0, /* 1186 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 's', 'p', 0, /* 1199 */ 'd', 'e', 'n', 't', 's', 'p', 0, /* 1206 */ 'd', 'r', 'e', 's', 't', 's', 'p', 0, /* 1214 */ 't', 's', 'e', 't', 'm', 'r', 32, 'r', 0, /* 1223 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 't', 0, /* 1235 */ 'f', 'r', 'e', 'e', 't', 0, /* 1241 */ 'd', 'r', 'e', 't', 0, /* 1246 */ 'k', 'r', 'e', 't', 0, /* 1251 */ 'w', 'a', 'i', 't', 'e', 'u', 0, }; // Emit the opcode for the instruction. uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; // assert(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 2047)-1); #endif if (strchr((const char *)AsmStrs+(Bits & 2047)-1, '[')) { set_mem_access(MI, true, 0); } // Fragment 0 encoded into 2 bits for 4 unique commands. //printf(">>%s\n", AsmStrs+(Bits & 2047)-1); //printf("Frag-0: %u\n", (Bits >> 11) & 3); switch ((Bits >> 11) & 3) { default: // unreachable. case 0: // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLRE_0R, DCALL_0R, DE... // already done. this means we have to extract details out ourself. XCore_insn_extract(MI, (const char *)AsmStrs+(Bits & 2047)-1); return; break; case 1: // ADD_2rus, ADD_3r, ADJCALLSTACKDOWN, ADJCALLSTACKUP, ANDNOT_2r, AND_3r,... printOperand(MI, 0, O); break; case 2: // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,... printOperand(MI, 1, O); break; case 3: // OUTSHR_2r, TSETR_3r printOperand(MI, 2, O); break; } // Fragment 1 encoded into 5 bits for 17 unique commands. //printf("Frag-1: %u\n", (Bits >> 13) & 31); switch ((Bits >> 13) & 31) { default: // unreachable. case 0: // ADD_2rus, ADD_3r, ANDNOT_2r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r,... SStream_concat0(O, ", "); break; case 1: // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1r, B... return; break; case 2: // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,... SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 3: // BR_JT, BR_JT32 SStream_concat0(O, "\n"); break; case 4: // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT... SStream_concat0(O, "], "); set_mem_access(MI, false, 0); break; case 5: // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... SStream_concat0(O, ", res["); set_mem_access(MI, true, 0); break; case 6: // GETPS_l2r SStream_concat0(O, ", ps["); set_mem_access(MI, true, 0); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 7: // INITCP_2r SStream_concat0(O, "]:cp, "); set_mem_access(MI, false, XCORE_REG_CP); printOperand(MI, 0, O); return; break; case 8: // INITDP_2r SStream_concat0(O, "]:dp, "); set_mem_access(MI, false, XCORE_REG_DP); printOperand(MI, 0, O); return; break; case 9: // INITLR_l2r SStream_concat0(O, "]:lr, "); set_mem_access(MI, false, XCORE_REG_LR); printOperand(MI, 0, O); return; break; case 10: // INITPC_2r SStream_concat0(O, "]:pc, "); set_mem_access(MI, false, XCORE_REG_PC); printOperand(MI, 0, O); return; break; case 11: // INITSP_2r SStream_concat0(O, "]:sp, "); set_mem_access(MI, false, XCORE_REG_SP); printOperand(MI, 0, O); return; break; case 12: // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6 SStream_concat0(O, ", dp["); set_mem_access(MI, true, XCORE_REG_DP); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 13: // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6 SStream_concat0(O, ", sp["); set_mem_access(MI, true, XCORE_REG_SP); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 14: // LDWCP_lru6, LDWCP_ru6 SStream_concat0(O, ", cp["); set_mem_access(MI, true, XCORE_REG_CP); printOperand(MI, 1, O); SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 15: // SETEV_1r, SETV_1r SStream_concat0(O, "], r11"); set_mem_access(MI, false, 0); return; break; case 16: // TSETR_3r SStream_concat0(O, "]:r"); set_mem_access(MI, false, 0); printOperand(MI, 0, O); SStream_concat0(O, ", "); printOperand(MI, 1, O); return; break; } // Fragment 2 encoded into 3 bits for 5 unique commands. //printf("Frag-2: %u\n", (Bits >> 18) & 7); switch ((Bits >> 18) & 7) { default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r, BRBF_lru6,... printOperand(MI, 1, O); break; case 1: // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus printOperand(MI, 2, O); break; case 2: // BR_JT printInlineJT(MI, 0, O); return; break; case 3: // BR_JT32 printInlineJT32(MI, 0, O); return; break; case 4: // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus printOperand(MI, 0, O); SStream_concat0(O, ", "); break; } // Fragment 3 encoded into 3 bits for 8 unique commands. //printf("Frag-3: %u\n", (Bits >> 21) & 7); switch ((Bits >> 21) & 7) { default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV... SStream_concat0(O, ", "); break; case 1: // ANDNOT_2r, BITREV_l2r, BRBF_lru6, BRBF_ru6, BRBT_lru6, BRBT_ru6, BRFF_... return; break; case 2: // CRC8_l4r printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 4, O); return; break; case 3: // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT... SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 4: // INPW_l2rus SStream_concat0(O, "], "); set_mem_access(MI, false, 0); printOperand(MI, 2, O); return; break; case 5: // LADD_l5r, LSUB_l5r, OUTPW_l2rus printOperand(MI, 2, O); break; case 6: // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3... SStream_concat0(O, "["); set_mem_access(MI, true, 0xffff); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; case 7: // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r SStream_concat0(O, "[-"); set_mem_access(MI, true, -0xffff); printOperand(MI, 2, O); SStream_concat0(O, "]"); set_mem_access(MI, false, 0); return; break; } // Fragment 4 encoded into 3 bits for 5 unique commands. //printf("Frag-4: %u\n", (Bits >> 24) & 7); switch ((Bits >> 24) & 7) { default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... printOperand(MI, 2, O); break; case 1: // CRC_l3r printOperand(MI, 3, O); return; break; case 2: // LADD_l5r, LSUB_l5r SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 4, O); return; break; case 3: // LDIVU_l5r, MACCS_l4r, MACCU_l4r printOperand(MI, 4, O); SStream_concat0(O, ", "); break; case 4: // OUTPW_l2rus return; break; } // Fragment 5 encoded into 2 bits for 4 unique commands. //printf("Frag-5: %u\n", (Bits >> 27) & 3); switch ((Bits >> 27) & 3) { default: // unreachable. case 0: // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ... return; break; case 1: // LDIVU_l5r printOperand(MI, 2, O); SStream_concat0(O, ", "); printOperand(MI, 3, O); return; break; case 2: // LMUL_l6r SStream_concat0(O, ", "); printOperand(MI, 3, O); SStream_concat0(O, ", "); printOperand(MI, 4, O); SStream_concat0(O, ", "); printOperand(MI, 5, O); return; break; case 3: // MACCS_l4r, MACCU_l4r printOperand(MI, 5, O); return; break; } } /// getRegisterName - This method is automatically generated by tblgen /// from the register set description. This returns the assembler name /// for the specified register. static const char *getRegisterName(unsigned RegNo) { // assert(RegNo && RegNo < 17 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrs[] = { /* 0 */ 'r', '1', '0', 0, /* 4 */ 'r', '0', 0, /* 7 */ 'r', '1', '1', 0, /* 11 */ 'r', '1', 0, /* 14 */ 'r', '2', 0, /* 17 */ 'r', '3', 0, /* 20 */ 'r', '4', 0, /* 23 */ 'r', '5', 0, /* 26 */ 'r', '6', 0, /* 29 */ 'r', '7', 0, /* 32 */ 'r', '8', 0, /* 35 */ 'r', '9', 0, /* 38 */ 'c', 'p', 0, /* 41 */ 'd', 'p', 0, /* 44 */ 's', 'p', 0, /* 47 */ 'l', 'r', 0, }; static const uint8_t RegAsmOffset[] = { 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35, 0, 7, }; //int i; //for (i = 0; i < sizeof(RegAsmOffset); i++) // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); //printf("*************************\n"); return AsmStrs+RegAsmOffset[RegNo-1]; #else return NULL; #endif } capstone-sys-0.15.0/capstone/arch/XCore/XCoreGenDisassemblerTables.inc000064400000000000000000001313460072674642500240060ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* * XCore Disassembler *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #include "../../MCInst.h" #include "../../LEB128.h" // Helper function for extracting fields from encoded instructions. #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ if (numBits == sizeof(InsnType)*8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ return (insn & fieldMask) >> startBit; \ } static const uint8_t DecoderTable16[] = { /* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... /* 3 */ MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115 /* 7 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... /* 10 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 19 /* 15 */ MCD_OPC_Decode, 243, 1, 0, // Opcode: WAITEU_0R /* 19 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 27 /* 24 */ MCD_OPC_Decode, 59, 0, // Opcode: CLRE_0R /* 27 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 36 /* 32 */ MCD_OPC_Decode, 218, 1, 0, // Opcode: SSYNC_0r /* 36 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 44 /* 41 */ MCD_OPC_Decode, 93, 0, // Opcode: FREET_0R /* 44 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 52 /* 49 */ MCD_OPC_Decode, 68, 0, // Opcode: DCALL_0R /* 52 */ MCD_OPC_FilterValue, 253, 15, 3, 0, // Skip to: 60 /* 57 */ MCD_OPC_Decode, 125, 0, // Opcode: KRET_0R /* 60 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 68 /* 65 */ MCD_OPC_Decode, 74, 0, // Opcode: DRET_0R /* 68 */ MCD_OPC_FilterValue, 255, 15, 4, 0, // Skip to: 77 /* 73 */ MCD_OPC_Decode, 199, 1, 0, // Opcode: SETKEP_0R /* 77 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 80 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 87 /* 84 */ MCD_OPC_Decode, 77, 1, // Opcode: EDU_1r /* 87 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 94 /* 91 */ MCD_OPC_Decode, 80, 1, // Opcode: EEU_1r /* 94 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 97 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 104 /* 101 */ MCD_OPC_Decode, 111, 2, // Opcode: INITPC_2r /* 104 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 111 /* 108 */ MCD_OPC_Decode, 105, 2, // Opcode: GETST_2r /* 111 */ MCD_OPC_Decode, 230, 1, 3, // Opcode: STW_2rus /* 115 */ MCD_OPC_FilterValue, 1, 114, 0, // Skip to: 233 /* 119 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... /* 122 */ MCD_OPC_FilterValue, 236, 15, 4, 0, // Skip to: 131 /* 127 */ MCD_OPC_Decode, 152, 1, 0, // Opcode: LDSPC_0R /* 131 */ MCD_OPC_FilterValue, 237, 15, 4, 0, // Skip to: 140 /* 136 */ MCD_OPC_Decode, 223, 1, 0, // Opcode: STSPC_0R /* 140 */ MCD_OPC_FilterValue, 238, 15, 4, 0, // Skip to: 149 /* 145 */ MCD_OPC_Decode, 153, 1, 0, // Opcode: LDSSR_0R /* 149 */ MCD_OPC_FilterValue, 239, 15, 4, 0, // Skip to: 158 /* 154 */ MCD_OPC_Decode, 224, 1, 0, // Opcode: STSSR_0R /* 158 */ MCD_OPC_FilterValue, 252, 15, 4, 0, // Skip to: 167 /* 163 */ MCD_OPC_Decode, 222, 1, 0, // Opcode: STSED_0R /* 167 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 176 /* 172 */ MCD_OPC_Decode, 221, 1, 0, // Opcode: STET_0R /* 176 */ MCD_OPC_FilterValue, 254, 15, 3, 0, // Skip to: 184 /* 181 */ MCD_OPC_Decode, 95, 0, // Opcode: GETED_0R /* 184 */ MCD_OPC_FilterValue, 255, 15, 3, 0, // Skip to: 192 /* 189 */ MCD_OPC_Decode, 96, 0, // Opcode: GETET_0R /* 192 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 195 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 203 /* 199 */ MCD_OPC_Decode, 242, 1, 1, // Opcode: WAITET_1R /* 203 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 211 /* 207 */ MCD_OPC_Decode, 241, 1, 1, // Opcode: WAITEF_1R /* 211 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 214 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 221 /* 218 */ MCD_OPC_Decode, 109, 2, // Opcode: INITDP_2r /* 221 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 229 /* 225 */ MCD_OPC_Decode, 183, 1, 4, // Opcode: OUTT_2r /* 229 */ MCD_OPC_Decode, 163, 1, 3, // Opcode: LDW_2rus /* 233 */ MCD_OPC_FilterValue, 2, 100, 0, // Skip to: 337 /* 237 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... /* 240 */ MCD_OPC_FilterValue, 236, 15, 3, 0, // Skip to: 248 /* 245 */ MCD_OPC_Decode, 69, 0, // Opcode: DENTSP_0R /* 248 */ MCD_OPC_FilterValue, 237, 15, 3, 0, // Skip to: 256 /* 253 */ MCD_OPC_Decode, 73, 0, // Opcode: DRESTSP_0R /* 256 */ MCD_OPC_FilterValue, 238, 15, 3, 0, // Skip to: 264 /* 261 */ MCD_OPC_Decode, 97, 0, // Opcode: GETID_0R /* 264 */ MCD_OPC_FilterValue, 239, 15, 3, 0, // Skip to: 272 /* 269 */ MCD_OPC_Decode, 98, 0, // Opcode: GETKEP_0R /* 272 */ MCD_OPC_FilterValue, 252, 15, 3, 0, // Skip to: 280 /* 277 */ MCD_OPC_Decode, 99, 0, // Opcode: GETKSP_0R /* 280 */ MCD_OPC_FilterValue, 253, 15, 4, 0, // Skip to: 289 /* 285 */ MCD_OPC_Decode, 151, 1, 0, // Opcode: LDSED_0R /* 289 */ MCD_OPC_FilterValue, 254, 15, 4, 0, // Skip to: 298 /* 294 */ MCD_OPC_Decode, 149, 1, 0, // Opcode: LDET_0R /* 298 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 301 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 308 /* 305 */ MCD_OPC_Decode, 92, 1, // Opcode: FREER_1r /* 308 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 316 /* 312 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: MJOIN_1r /* 316 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 319 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 326 /* 323 */ MCD_OPC_Decode, 112, 2, // Opcode: INITSP_2r /* 326 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 334 /* 330 */ MCD_OPC_Decode, 197, 1, 4, // Opcode: SETD_2r /* 334 */ MCD_OPC_Decode, 23, 5, // Opcode: ADD_3r /* 337 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 382 /* 341 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 344 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 352 /* 348 */ MCD_OPC_Decode, 240, 1, 1, // Opcode: TSTART_1R /* 352 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 360 /* 356 */ MCD_OPC_Decode, 174, 1, 1, // Opcode: MSYNC_1r /* 360 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 363 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 370 /* 367 */ MCD_OPC_Decode, 108, 2, // Opcode: INITCP_2r /* 370 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 378 /* 374 */ MCD_OPC_Decode, 238, 1, 6, // Opcode: TSETMR_2r /* 378 */ MCD_OPC_Decode, 233, 1, 5, // Opcode: SUB_3r /* 382 */ MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 416 /* 386 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 389 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 396 /* 393 */ MCD_OPC_Decode, 36, 1, // Opcode: BLA_1r /* 396 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 403 /* 400 */ MCD_OPC_Decode, 30, 1, // Opcode: BAU_1r /* 403 */ MCD_OPC_CheckField, 4, 1, 1, 3, 0, // Skip to: 412 /* 409 */ MCD_OPC_Decode, 79, 2, // Opcode: EET_2r /* 412 */ MCD_OPC_Decode, 215, 1, 5, // Opcode: SHL_3r /* 416 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 459 /* 420 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 423 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 430 /* 427 */ MCD_OPC_Decode, 53, 1, // Opcode: BRU_1r /* 430 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 438 /* 434 */ MCD_OPC_Decode, 205, 1, 1, // Opcode: SETSP_1r /* 438 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 441 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 448 /* 445 */ MCD_OPC_Decode, 26, 7, // Opcode: ANDNOT_2r /* 448 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 455 /* 452 */ MCD_OPC_Decode, 78, 2, // Opcode: EEF_2r /* 455 */ MCD_OPC_Decode, 217, 1, 5, // Opcode: SHR_3r /* 459 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 504 /* 463 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 466 */ MCD_OPC_FilterValue, 126, 4, 0, // Skip to: 474 /* 470 */ MCD_OPC_Decode, 196, 1, 1, // Opcode: SETDP_1r /* 474 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 482 /* 478 */ MCD_OPC_Decode, 192, 1, 1, // Opcode: SETCP_1r /* 482 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 485 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 493 /* 489 */ MCD_OPC_Decode, 212, 1, 7, // Opcode: SEXT_2r /* 493 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 501 /* 497 */ MCD_OPC_Decode, 213, 1, 8, // Opcode: SEXT_rus /* 501 */ MCD_OPC_Decode, 86, 5, // Opcode: EQ_3r /* 504 */ MCD_OPC_FilterValue, 7, 39, 0, // Skip to: 547 /* 508 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 511 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 518 /* 515 */ MCD_OPC_Decode, 70, 1, // Opcode: DGETREG_1r /* 518 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 526 /* 522 */ MCD_OPC_Decode, 198, 1, 1, // Opcode: SETEV_1r /* 526 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 529 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 536 /* 533 */ MCD_OPC_Decode, 106, 2, // Opcode: GETTS_2r /* 536 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 544 /* 540 */ MCD_OPC_Decode, 203, 1, 4, // Opcode: SETPT_2r /* 544 */ MCD_OPC_Decode, 27, 5, // Opcode: AND_3r /* 547 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 592 /* 551 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 554 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 561 /* 558 */ MCD_OPC_Decode, 118, 1, // Opcode: KCALL_1r /* 561 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 569 /* 565 */ MCD_OPC_Decode, 211, 1, 1, // Opcode: SETV_1r /* 569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 572 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 580 /* 576 */ MCD_OPC_Decode, 245, 1, 7, // Opcode: ZEXT_2r /* 580 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 588 /* 584 */ MCD_OPC_Decode, 246, 1, 8, // Opcode: ZEXT_rus /* 588 */ MCD_OPC_Decode, 178, 1, 5, // Opcode: OR_3r /* 592 */ MCD_OPC_FilterValue, 9, 40, 0, // Skip to: 636 /* 596 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 599 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 606 /* 603 */ MCD_OPC_Decode, 75, 1, // Opcode: ECALLF_1r /* 606 */ MCD_OPC_FilterValue, 127, 3, 0, // Skip to: 613 /* 610 */ MCD_OPC_Decode, 76, 1, // Opcode: ECALLT_1r /* 613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 616 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 624 /* 620 */ MCD_OPC_Decode, 179, 1, 2, // Opcode: OUTCT_2r /* 624 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 632 /* 628 */ MCD_OPC_Decode, 180, 1, 9, // Opcode: OUTCT_rus /* 632 */ MCD_OPC_Decode, 164, 1, 5, // Opcode: LDW_3r /* 636 */ MCD_OPC_FilterValue, 10, 19, 0, // Skip to: 659 /* 640 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 643 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 651 /* 647 */ MCD_OPC_Decode, 226, 1, 10, // Opcode: STWDP_ru6 /* 651 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 1221 /* 655 */ MCD_OPC_Decode, 229, 1, 10, // Opcode: STWSP_ru6 /* 659 */ MCD_OPC_FilterValue, 11, 19, 0, // Skip to: 682 /* 663 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 666 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 674 /* 670 */ MCD_OPC_Decode, 159, 1, 10, // Opcode: LDWDP_ru6 /* 674 */ MCD_OPC_FilterValue, 1, 31, 2, // Skip to: 1221 /* 678 */ MCD_OPC_Decode, 162, 1, 10, // Opcode: LDWSP_ru6 /* 682 */ MCD_OPC_FilterValue, 12, 19, 0, // Skip to: 705 /* 686 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 689 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 697 /* 693 */ MCD_OPC_Decode, 141, 1, 10, // Opcode: LDAWDP_ru6 /* 697 */ MCD_OPC_FilterValue, 1, 8, 2, // Skip to: 1221 /* 701 */ MCD_OPC_Decode, 146, 1, 10, // Opcode: LDAWSP_ru6 /* 705 */ MCD_OPC_FilterValue, 13, 19, 0, // Skip to: 728 /* 709 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 712 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 720 /* 716 */ MCD_OPC_Decode, 148, 1, 10, // Opcode: LDC_ru6 /* 720 */ MCD_OPC_FilterValue, 1, 241, 1, // Skip to: 1221 /* 724 */ MCD_OPC_Decode, 156, 1, 10, // Opcode: LDWCP_ru6 /* 728 */ MCD_OPC_FilterValue, 14, 80, 0, // Skip to: 812 /* 732 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 735 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 773 /* 739 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 742 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 749 /* 746 */ MCD_OPC_Decode, 52, 11, // Opcode: BRFU_u6 /* 749 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 756 /* 753 */ MCD_OPC_Decode, 35, 11, // Opcode: BLAT_u6 /* 756 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 763 /* 760 */ MCD_OPC_Decode, 88, 11, // Opcode: EXTDP_u6 /* 763 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 770 /* 767 */ MCD_OPC_Decode, 120, 11, // Opcode: KCALL_u6 /* 770 */ MCD_OPC_Decode, 50, 12, // Opcode: BRFT_ru6 /* 773 */ MCD_OPC_FilterValue, 1, 188, 1, // Skip to: 1221 /* 777 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 780 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 787 /* 784 */ MCD_OPC_Decode, 46, 13, // Opcode: BRBU_u6 /* 787 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 794 /* 791 */ MCD_OPC_Decode, 84, 11, // Opcode: ENTSP_u6 /* 794 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 801 /* 798 */ MCD_OPC_Decode, 90, 11, // Opcode: EXTSP_u6 /* 801 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 809 /* 805 */ MCD_OPC_Decode, 189, 1, 11, // Opcode: RETSP_u6 /* 809 */ MCD_OPC_Decode, 44, 14, // Opcode: BRBT_ru6 /* 812 */ MCD_OPC_FilterValue, 15, 67, 0, // Skip to: 883 /* 816 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 819 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 858 /* 823 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 826 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 833 /* 830 */ MCD_OPC_Decode, 64, 11, // Opcode: CLRSR_u6 /* 833 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 841 /* 837 */ MCD_OPC_Decode, 209, 1, 11, // Opcode: SETSR_u6 /* 841 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 848 /* 845 */ MCD_OPC_Decode, 122, 11, // Opcode: KENTSP_u6 /* 848 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 855 /* 852 */ MCD_OPC_Decode, 124, 11, // Opcode: KRESTSP_u6 /* 855 */ MCD_OPC_Decode, 48, 12, // Opcode: BRFF_ru6 /* 858 */ MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 1221 /* 862 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... /* 865 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 872 /* 869 */ MCD_OPC_Decode, 104, 11, // Opcode: GETSR_u6 /* 872 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 880 /* 876 */ MCD_OPC_Decode, 139, 1, 11, // Opcode: LDAWCP_u6 /* 880 */ MCD_OPC_Decode, 42, 14, // Opcode: BRBF_ru6 /* 883 */ MCD_OPC_FilterValue, 16, 38, 0, // Skip to: 925 /* 887 */ MCD_OPC_ExtractField, 4, 7, // Inst{10-4} ... /* 890 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 897 /* 894 */ MCD_OPC_Decode, 60, 1, // Opcode: CLRPT_1R /* 897 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 905 /* 901 */ MCD_OPC_Decode, 234, 1, 1, // Opcode: SYNCR_1r /* 905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 908 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 915 /* 912 */ MCD_OPC_Decode, 102, 9, // Opcode: GETR_rus /* 915 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 922 /* 919 */ MCD_OPC_Decode, 107, 2, // Opcode: INCT_2r /* 922 */ MCD_OPC_Decode, 127, 5, // Opcode: LD16S_3r /* 925 */ MCD_OPC_FilterValue, 17, 22, 0, // Skip to: 951 /* 929 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 932 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 940 /* 936 */ MCD_OPC_Decode, 177, 1, 2, // Opcode: NOT /* 940 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 947 /* 944 */ MCD_OPC_Decode, 115, 2, // Opcode: INT_2r /* 947 */ MCD_OPC_Decode, 128, 1, 5, // Opcode: LD8U_3r /* 951 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 976 /* 955 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 958 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 966 /* 962 */ MCD_OPC_Decode, 176, 1, 2, // Opcode: NEG /* 966 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 973 /* 970 */ MCD_OPC_Decode, 82, 2, // Opcode: ENDIN_2r /* 973 */ MCD_OPC_Decode, 22, 3, // Opcode: ADD_2rus /* 976 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 984 /* 980 */ MCD_OPC_Decode, 232, 1, 3, // Opcode: SUB_2rus /* 984 */ MCD_OPC_FilterValue, 20, 23, 0, // Skip to: 1011 /* 988 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 991 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 999 /* 995 */ MCD_OPC_Decode, 172, 1, 2, // Opcode: MKMSK_2r /* 999 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1007 /* 1003 */ MCD_OPC_Decode, 173, 1, 15, // Opcode: MKMSK_rus /* 1007 */ MCD_OPC_Decode, 214, 1, 16, // Opcode: SHL_2rus /* 1011 */ MCD_OPC_FilterValue, 21, 23, 0, // Skip to: 1038 /* 1015 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1018 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1026 /* 1022 */ MCD_OPC_Decode, 184, 1, 4, // Opcode: OUT_2r /* 1026 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1034 /* 1030 */ MCD_OPC_Decode, 182, 1, 7, // Opcode: OUTSHR_2r /* 1034 */ MCD_OPC_Decode, 216, 1, 16, // Opcode: SHR_2rus /* 1038 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 1062 /* 1042 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1045 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1052 /* 1049 */ MCD_OPC_Decode, 116, 2, // Opcode: IN_2r /* 1052 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1059 /* 1056 */ MCD_OPC_Decode, 114, 7, // Opcode: INSHR_2r /* 1059 */ MCD_OPC_Decode, 85, 3, // Opcode: EQ_2rus /* 1062 */ MCD_OPC_FilterValue, 23, 23, 0, // Skip to: 1089 /* 1066 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1069 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1077 /* 1073 */ MCD_OPC_Decode, 185, 1, 2, // Opcode: PEEK_2r /* 1077 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1085 /* 1081 */ MCD_OPC_Decode, 235, 1, 2, // Opcode: TESTCT_2r /* 1085 */ MCD_OPC_Decode, 239, 1, 17, // Opcode: TSETR_3r /* 1089 */ MCD_OPC_FilterValue, 24, 23, 0, // Skip to: 1116 /* 1093 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1096 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1104 /* 1100 */ MCD_OPC_Decode, 201, 1, 4, // Opcode: SETPSC_2r /* 1104 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1112 /* 1108 */ MCD_OPC_Decode, 237, 1, 2, // Opcode: TESTWCT_2r /* 1112 */ MCD_OPC_Decode, 166, 1, 5, // Opcode: LSS_3r /* 1116 */ MCD_OPC_FilterValue, 25, 21, 0, // Skip to: 1141 /* 1120 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 1123 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1130 /* 1127 */ MCD_OPC_Decode, 57, 2, // Opcode: CHKCT_2r /* 1130 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 1137 /* 1134 */ MCD_OPC_Decode, 58, 15, // Opcode: CHKCT_rus /* 1137 */ MCD_OPC_Decode, 168, 1, 5, // Opcode: LSU_3r /* 1141 */ MCD_OPC_FilterValue, 26, 17, 0, // Skip to: 1162 /* 1145 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 1148 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1155 /* 1152 */ MCD_OPC_Decode, 40, 18, // Opcode: BLRF_u10 /* 1155 */ MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 1221 /* 1159 */ MCD_OPC_Decode, 38, 19, // Opcode: BLRB_u10 /* 1162 */ MCD_OPC_FilterValue, 27, 19, 0, // Skip to: 1185 /* 1166 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 1169 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1177 /* 1173 */ MCD_OPC_Decode, 135, 1, 18, // Opcode: LDAPF_u10 /* 1177 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 1221 /* 1181 */ MCD_OPC_Decode, 132, 1, 19, // Opcode: LDAPB_u10 /* 1185 */ MCD_OPC_FilterValue, 28, 18, 0, // Skip to: 1207 /* 1189 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... /* 1192 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1199 /* 1196 */ MCD_OPC_Decode, 33, 18, // Opcode: BLACP_u10 /* 1199 */ MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 1221 /* 1203 */ MCD_OPC_Decode, 157, 1, 18, // Opcode: LDWCP_u10 /* 1207 */ MCD_OPC_FilterValue, 29, 10, 0, // Skip to: 1221 /* 1211 */ MCD_OPC_CheckField, 10, 1, 0, 4, 0, // Skip to: 1221 /* 1217 */ MCD_OPC_Decode, 195, 1, 12, // Opcode: SETC_ru6 /* 1221 */ MCD_OPC_Fail, 0 }; static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... /* 3 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96 /* 7 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... /* 10 */ MCD_OPC_FilterValue, 31, 216, 3, // Skip to: 998 /* 14 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 17 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31 /* 21 */ MCD_OPC_CheckField, 16, 11, 236, 15, 17, 0, // Skip to: 45 /* 28 */ MCD_OPC_Decode, 31, 20, // Opcode: BITREV_l2r /* 31 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 45 /* 35 */ MCD_OPC_CheckField, 16, 11, 236, 15, 3, 0, // Skip to: 45 /* 42 */ MCD_OPC_Decode, 56, 20, // Opcode: BYTEREV_l2r /* 45 */ MCD_OPC_CheckField, 16, 11, 236, 15, 4, 0, // Skip to: 56 /* 52 */ MCD_OPC_Decode, 231, 1, 21, // Opcode: STW_l3r /* 56 */ MCD_OPC_ExtractField, 20, 7, // Inst{26-20} ... /* 59 */ MCD_OPC_FilterValue, 126, 3, 0, // Skip to: 66 /* 63 */ MCD_OPC_Decode, 66, 22, // Opcode: CRC8_l4r /* 66 */ MCD_OPC_FilterValue, 127, 4, 0, // Skip to: 74 /* 70 */ MCD_OPC_Decode, 170, 1, 23, // Opcode: MACCU_l4r /* 74 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 77 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 85 /* 81 */ MCD_OPC_Decode, 150, 1, 24, // Opcode: LDIVU_l5r /* 85 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 92 /* 89 */ MCD_OPC_Decode, 126, 24, // Opcode: LADD_l5r /* 92 */ MCD_OPC_Decode, 165, 1, 25, // Opcode: LMUL_l6r /* 96 */ MCD_OPC_FilterValue, 1, 86, 0, // Skip to: 186 /* 100 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... /* 103 */ MCD_OPC_FilterValue, 31, 123, 3, // Skip to: 998 /* 107 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... /* 110 */ MCD_OPC_FilterValue, 0, 116, 3, // Skip to: 998 /* 114 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 117 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 136 /* 121 */ MCD_OPC_CheckField, 21, 6, 63, 29, 0, // Skip to: 156 /* 127 */ MCD_OPC_CheckField, 16, 4, 12, 23, 0, // Skip to: 156 /* 133 */ MCD_OPC_Decode, 65, 20, // Opcode: CLZ_l2r /* 136 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 156 /* 140 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 156 /* 146 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 156 /* 152 */ MCD_OPC_Decode, 191, 1, 26, // Opcode: SETCLK_l2r /* 156 */ MCD_OPC_CheckField, 21, 6, 63, 10, 0, // Skip to: 172 /* 162 */ MCD_OPC_CheckField, 16, 4, 12, 4, 0, // Skip to: 172 /* 168 */ MCD_OPC_Decode, 244, 1, 21, // Opcode: XOR_l3r /* 172 */ MCD_OPC_CheckField, 21, 6, 63, 4, 0, // Skip to: 182 /* 178 */ MCD_OPC_Decode, 169, 1, 23, // Opcode: MACCS_l4r /* 182 */ MCD_OPC_Decode, 167, 1, 24, // Opcode: LSUB_l5r /* 186 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 219 /* 190 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... /* 193 */ MCD_OPC_FilterValue, 159, 251, 3, 31, 3, // Skip to: 998 /* 199 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 202 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 209 /* 206 */ MCD_OPC_Decode, 110, 20, // Opcode: INITLR_l2r /* 209 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 216 /* 213 */ MCD_OPC_Decode, 101, 20, // Opcode: GETPS_l2r /* 216 */ MCD_OPC_Decode, 29, 21, // Opcode: ASHR_l3r /* 219 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 254 /* 223 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... /* 226 */ MCD_OPC_FilterValue, 159, 251, 3, 254, 2, // Skip to: 998 /* 232 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 235 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 243 /* 239 */ MCD_OPC_Decode, 202, 1, 26, // Opcode: SETPS_l2r /* 243 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 250 /* 247 */ MCD_OPC_Decode, 94, 20, // Opcode: GETD_l2r /* 250 */ MCD_OPC_Decode, 144, 1, 21, // Opcode: LDAWF_l3r /* 254 */ MCD_OPC_FilterValue, 4, 32, 0, // Skip to: 290 /* 258 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... /* 261 */ MCD_OPC_FilterValue, 159, 251, 3, 219, 2, // Skip to: 998 /* 267 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 270 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 278 /* 274 */ MCD_OPC_Decode, 236, 1, 20, // Opcode: TESTLCL_l2r /* 278 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 286 /* 282 */ MCD_OPC_Decode, 210, 1, 26, // Opcode: SETTW_l2r /* 286 */ MCD_OPC_Decode, 137, 1, 21, // Opcode: LDAWB_l3r /* 290 */ MCD_OPC_FilterValue, 5, 32, 0, // Skip to: 326 /* 294 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... /* 297 */ MCD_OPC_FilterValue, 159, 251, 3, 183, 2, // Skip to: 998 /* 303 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 306 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 314 /* 310 */ MCD_OPC_Decode, 204, 1, 26, // Opcode: SETRDY_l2r /* 314 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 322 /* 318 */ MCD_OPC_Decode, 193, 1, 20, // Opcode: SETC_l2r /* 322 */ MCD_OPC_Decode, 130, 1, 21, // Opcode: LDA16F_l3r /* 326 */ MCD_OPC_FilterValue, 6, 31, 0, // Skip to: 361 /* 330 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... /* 333 */ MCD_OPC_FilterValue, 159, 251, 3, 147, 2, // Skip to: 998 /* 339 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... /* 342 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 350 /* 346 */ MCD_OPC_Decode, 200, 1, 26, // Opcode: SETN_l2r /* 350 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 357 /* 354 */ MCD_OPC_Decode, 100, 20, // Opcode: GETN_l2r /* 357 */ MCD_OPC_Decode, 129, 1, 21, // Opcode: LDA16B_l3r /* 361 */ MCD_OPC_FilterValue, 7, 12, 0, // Skip to: 377 /* 365 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 113, 2, // Skip to: 998 /* 373 */ MCD_OPC_Decode, 175, 1, 21, // Opcode: MUL_l3r /* 377 */ MCD_OPC_FilterValue, 8, 11, 0, // Skip to: 392 /* 381 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 97, 2, // Skip to: 998 /* 389 */ MCD_OPC_Decode, 71, 21, // Opcode: DIVS_l3r /* 392 */ MCD_OPC_FilterValue, 9, 11, 0, // Skip to: 407 /* 396 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 82, 2, // Skip to: 998 /* 404 */ MCD_OPC_Decode, 72, 21, // Opcode: DIVU_l3r /* 407 */ MCD_OPC_FilterValue, 10, 31, 0, // Skip to: 442 /* 411 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 414 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 428 /* 418 */ MCD_OPC_CheckField, 10, 6, 60, 62, 2, // Skip to: 998 /* 424 */ MCD_OPC_Decode, 225, 1, 27, // Opcode: STWDP_lru6 /* 428 */ MCD_OPC_FilterValue, 1, 54, 2, // Skip to: 998 /* 432 */ MCD_OPC_CheckField, 10, 6, 60, 48, 2, // Skip to: 998 /* 438 */ MCD_OPC_Decode, 228, 1, 27, // Opcode: STWSP_lru6 /* 442 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 477 /* 446 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 449 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 463 /* 453 */ MCD_OPC_CheckField, 10, 6, 60, 27, 2, // Skip to: 998 /* 459 */ MCD_OPC_Decode, 158, 1, 27, // Opcode: LDWDP_lru6 /* 463 */ MCD_OPC_FilterValue, 1, 19, 2, // Skip to: 998 /* 467 */ MCD_OPC_CheckField, 10, 6, 60, 13, 2, // Skip to: 998 /* 473 */ MCD_OPC_Decode, 161, 1, 27, // Opcode: LDWSP_lru6 /* 477 */ MCD_OPC_FilterValue, 12, 31, 0, // Skip to: 512 /* 481 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 484 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 498 /* 488 */ MCD_OPC_CheckField, 10, 6, 60, 248, 1, // Skip to: 998 /* 494 */ MCD_OPC_Decode, 140, 1, 27, // Opcode: LDAWDP_lru6 /* 498 */ MCD_OPC_FilterValue, 1, 240, 1, // Skip to: 998 /* 502 */ MCD_OPC_CheckField, 10, 6, 60, 234, 1, // Skip to: 998 /* 508 */ MCD_OPC_Decode, 145, 1, 27, // Opcode: LDAWSP_lru6 /* 512 */ MCD_OPC_FilterValue, 13, 31, 0, // Skip to: 547 /* 516 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 519 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 533 /* 523 */ MCD_OPC_CheckField, 10, 6, 60, 213, 1, // Skip to: 998 /* 529 */ MCD_OPC_Decode, 147, 1, 27, // Opcode: LDC_lru6 /* 533 */ MCD_OPC_FilterValue, 1, 205, 1, // Skip to: 998 /* 537 */ MCD_OPC_CheckField, 10, 6, 60, 199, 1, // Skip to: 998 /* 543 */ MCD_OPC_Decode, 154, 1, 27, // Opcode: LDWCP_lru6 /* 547 */ MCD_OPC_FilterValue, 14, 94, 0, // Skip to: 645 /* 551 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 554 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 599 /* 558 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 561 */ MCD_OPC_FilterValue, 60, 177, 1, // Skip to: 998 /* 565 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 568 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 575 /* 572 */ MCD_OPC_Decode, 51, 28, // Opcode: BRFU_lu6 /* 575 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 582 /* 579 */ MCD_OPC_Decode, 34, 28, // Opcode: BLAT_lu6 /* 582 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 589 /* 586 */ MCD_OPC_Decode, 87, 28, // Opcode: EXTDP_lu6 /* 589 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 596 /* 593 */ MCD_OPC_Decode, 119, 28, // Opcode: KCALL_lu6 /* 596 */ MCD_OPC_Decode, 49, 29, // Opcode: BRFT_lru6 /* 599 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 998 /* 603 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 606 */ MCD_OPC_FilterValue, 60, 132, 1, // Skip to: 998 /* 610 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 613 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 620 /* 617 */ MCD_OPC_Decode, 45, 30, // Opcode: BRBU_lu6 /* 620 */ MCD_OPC_FilterValue, 13, 3, 0, // Skip to: 627 /* 624 */ MCD_OPC_Decode, 83, 28, // Opcode: ENTSP_lu6 /* 627 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 634 /* 631 */ MCD_OPC_Decode, 89, 28, // Opcode: EXTSP_lu6 /* 634 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 642 /* 638 */ MCD_OPC_Decode, 188, 1, 28, // Opcode: RETSP_lu6 /* 642 */ MCD_OPC_Decode, 43, 31, // Opcode: BRBT_lru6 /* 645 */ MCD_OPC_FilterValue, 15, 81, 0, // Skip to: 730 /* 649 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 652 */ MCD_OPC_FilterValue, 0, 42, 0, // Skip to: 698 /* 656 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 659 */ MCD_OPC_FilterValue, 60, 79, 1, // Skip to: 998 /* 663 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 666 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 673 /* 670 */ MCD_OPC_Decode, 63, 28, // Opcode: CLRSR_lu6 /* 673 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 681 /* 677 */ MCD_OPC_Decode, 208, 1, 28, // Opcode: SETSR_lu6 /* 681 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 688 /* 685 */ MCD_OPC_Decode, 121, 28, // Opcode: KENTSP_lu6 /* 688 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 695 /* 692 */ MCD_OPC_Decode, 123, 28, // Opcode: KRESTSP_lu6 /* 695 */ MCD_OPC_Decode, 47, 29, // Opcode: BRFF_lru6 /* 698 */ MCD_OPC_FilterValue, 1, 40, 1, // Skip to: 998 /* 702 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... /* 705 */ MCD_OPC_FilterValue, 60, 33, 1, // Skip to: 998 /* 709 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... /* 712 */ MCD_OPC_FilterValue, 12, 3, 0, // Skip to: 719 /* 716 */ MCD_OPC_Decode, 103, 28, // Opcode: GETSR_lu6 /* 719 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 727 /* 723 */ MCD_OPC_Decode, 138, 1, 28, // Opcode: LDAWCP_lu6 /* 727 */ MCD_OPC_Decode, 41, 31, // Opcode: BRBF_lru6 /* 730 */ MCD_OPC_FilterValue, 16, 12, 0, // Skip to: 746 /* 734 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 0, 1, // Skip to: 998 /* 742 */ MCD_OPC_Decode, 219, 1, 21, // Opcode: ST16_l3r /* 746 */ MCD_OPC_FilterValue, 17, 12, 0, // Skip to: 762 /* 750 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 240, 0, // Skip to: 998 /* 758 */ MCD_OPC_Decode, 220, 1, 21, // Opcode: ST8_l3r /* 762 */ MCD_OPC_FilterValue, 18, 31, 0, // Skip to: 797 /* 766 */ MCD_OPC_ExtractField, 11, 16, // Inst{26-11} ... /* 769 */ MCD_OPC_FilterValue, 159, 251, 3, 3, 0, // Skip to: 778 /* 775 */ MCD_OPC_Decode, 28, 32, // Opcode: ASHR_l2rus /* 778 */ MCD_OPC_FilterValue, 191, 251, 3, 4, 0, // Skip to: 788 /* 784 */ MCD_OPC_Decode, 181, 1, 32, // Opcode: OUTPW_l2rus /* 788 */ MCD_OPC_FilterValue, 223, 251, 3, 204, 0, // Skip to: 998 /* 794 */ MCD_OPC_Decode, 113, 32, // Opcode: INPW_l2rus /* 797 */ MCD_OPC_FilterValue, 19, 12, 0, // Skip to: 813 /* 801 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 189, 0, // Skip to: 998 /* 809 */ MCD_OPC_Decode, 143, 1, 33, // Opcode: LDAWF_l2rus /* 813 */ MCD_OPC_FilterValue, 20, 12, 0, // Skip to: 829 /* 817 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 173, 0, // Skip to: 998 /* 825 */ MCD_OPC_Decode, 136, 1, 33, // Opcode: LDAWB_l2rus /* 829 */ MCD_OPC_FilterValue, 21, 11, 0, // Skip to: 844 /* 833 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 157, 0, // Skip to: 998 /* 841 */ MCD_OPC_Decode, 67, 34, // Opcode: CRC_l3r /* 844 */ MCD_OPC_FilterValue, 24, 12, 0, // Skip to: 860 /* 848 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 142, 0, // Skip to: 998 /* 856 */ MCD_OPC_Decode, 186, 1, 21, // Opcode: REMS_l3r /* 860 */ MCD_OPC_FilterValue, 25, 12, 0, // Skip to: 876 /* 864 */ MCD_OPC_CheckField, 11, 16, 159, 251, 3, 126, 0, // Skip to: 998 /* 872 */ MCD_OPC_Decode, 187, 1, 21, // Opcode: REMU_l3r /* 876 */ MCD_OPC_FilterValue, 26, 29, 0, // Skip to: 909 /* 880 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 883 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 896 /* 887 */ MCD_OPC_CheckField, 10, 6, 60, 105, 0, // Skip to: 998 /* 893 */ MCD_OPC_Decode, 39, 35, // Opcode: BLRF_lu10 /* 896 */ MCD_OPC_FilterValue, 1, 98, 0, // Skip to: 998 /* 900 */ MCD_OPC_CheckField, 10, 6, 60, 92, 0, // Skip to: 998 /* 906 */ MCD_OPC_Decode, 37, 36, // Opcode: BLRB_lu10 /* 909 */ MCD_OPC_FilterValue, 27, 31, 0, // Skip to: 944 /* 913 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 916 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 930 /* 920 */ MCD_OPC_CheckField, 10, 6, 60, 72, 0, // Skip to: 998 /* 926 */ MCD_OPC_Decode, 133, 1, 35, // Opcode: LDAPF_lu10 /* 930 */ MCD_OPC_FilterValue, 1, 64, 0, // Skip to: 998 /* 934 */ MCD_OPC_CheckField, 10, 6, 60, 58, 0, // Skip to: 998 /* 940 */ MCD_OPC_Decode, 131, 1, 36, // Opcode: LDAPB_lu10 /* 944 */ MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 978 /* 948 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... /* 951 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 964 /* 955 */ MCD_OPC_CheckField, 10, 6, 60, 37, 0, // Skip to: 998 /* 961 */ MCD_OPC_Decode, 32, 35, // Opcode: BLACP_lu10 /* 964 */ MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 998 /* 968 */ MCD_OPC_CheckField, 10, 6, 60, 24, 0, // Skip to: 998 /* 974 */ MCD_OPC_Decode, 155, 1, 35, // Opcode: LDWCP_lu10 /* 978 */ MCD_OPC_FilterValue, 29, 16, 0, // Skip to: 998 /* 982 */ MCD_OPC_CheckField, 26, 1, 0, 10, 0, // Skip to: 998 /* 988 */ MCD_OPC_CheckField, 10, 6, 60, 4, 0, // Skip to: 998 /* 994 */ MCD_OPC_Decode, 194, 1, 29, // Opcode: SETC_lru6 /* 998 */ MCD_OPC_Fail, 0 }; static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { return true; //llvm_unreachable("Invalid index!"); } #define DecodeToMCInst(fname,fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ uint64_t Address, const void *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ default: \ case 0: \ return S; \ case 1: \ tmp = fieldname(insn, 0, 4); \ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 2: \ if (Decode2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 3: \ if (Decode2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 4: \ if (DecodeR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 5: \ if (Decode3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 6: \ if (Decode2RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 7: \ if (Decode2RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 8: \ if (DecodeRUSSrcDstBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 9: \ if (DecodeRUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 10: \ tmp = fieldname(insn, 6, 4); \ if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 11: \ tmp = fieldname(insn, 0, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 12: \ tmp = fieldname(insn, 6, 4); \ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 6); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 13: \ tmp = fieldname(insn, 0, 6); \ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 14: \ tmp = fieldname(insn, 6, 4); \ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 6); \ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 15: \ if (DecodeRUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 16: \ if (Decode2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 17: \ if (Decode3RImmInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 18: \ tmp = fieldname(insn, 0, 10); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 19: \ tmp = fieldname(insn, 0, 10); \ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 20: \ if (DecodeL2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 21: \ if (DecodeL3RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 22: \ if (DecodeL4RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 23: \ if (DecodeL4RSrcDstSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 24: \ if (DecodeL5RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 25: \ if (DecodeL6RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 26: \ if (DecodeLR2RInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 27: \ tmp = fieldname(insn, 22, 4); \ if (DecodeRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 6); \ tmp |= (fieldname(insn, 16, 6) << 0); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 28: \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 6); \ tmp |= (fieldname(insn, 16, 6) << 0); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 29: \ tmp = fieldname(insn, 22, 4); \ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 6); \ tmp |= (fieldname(insn, 16, 6) << 0); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 30: \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 6); \ tmp |= (fieldname(insn, 16, 6) << 0); \ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 31: \ tmp = fieldname(insn, 22, 4); \ if (DecodeGRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 6); \ tmp |= (fieldname(insn, 16, 6) << 0); \ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 32: \ if (DecodeL2RUSBitpInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 33: \ if (DecodeL2RUSInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 34: \ if (DecodeL3RSrcDstInstruction(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ case 35: \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 10); \ tmp |= (fieldname(insn, 16, 10) << 0); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 36: \ tmp = 0; \ tmp |= (fieldname(insn, 0, 10) << 10); \ tmp |= (fieldname(insn, 16, 10) << 0); \ if (DecodeNegImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ { \ uint64_t Bits = getFeatureBits(feature); \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0, ExpectedValue; \ DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ bool Pred, Fail; \ for (;;) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ case MCD_OPC_ExtractField: { \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckField: { \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ Pred = checkDecoderPredicate(PIdx, Bits); \ if (!Pred) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ MCInst_setOpcode(MI, Opc); \ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ } \ case MCD_OPC_SoftFail: { \ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ S = MCDisassembler_SoftFail; \ break; \ } \ case MCD_OPC_Fail: { \ return MCDisassembler_Fail; \ } \ } \ } \ } FieldFromInstruction(fieldFromInstruction_2, uint16_t) DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) capstone-sys-0.15.0/capstone/arch/XCore/XCoreGenInstrInfo.inc000064400000000000000000000161370072674642500221510ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Instruction Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { XCore_PHI = 0, XCore_INLINEASM = 1, XCore_CFI_INSTRUCTION = 2, XCore_EH_LABEL = 3, XCore_GC_LABEL = 4, XCore_KILL = 5, XCore_EXTRACT_SUBREG = 6, XCore_INSERT_SUBREG = 7, XCore_IMPLICIT_DEF = 8, XCore_SUBREG_TO_REG = 9, XCore_COPY_TO_REGCLASS = 10, XCore_DBG_VALUE = 11, XCore_REG_SEQUENCE = 12, XCore_COPY = 13, XCore_BUNDLE = 14, XCore_LIFETIME_START = 15, XCore_LIFETIME_END = 16, XCore_STACKMAP = 17, XCore_PATCHPOINT = 18, XCore_LOAD_STACK_GUARD = 19, XCore_STATEPOINT = 20, XCore_FRAME_ALLOC = 21, XCore_ADD_2rus = 22, XCore_ADD_3r = 23, XCore_ADJCALLSTACKDOWN = 24, XCore_ADJCALLSTACKUP = 25, XCore_ANDNOT_2r = 26, XCore_AND_3r = 27, XCore_ASHR_l2rus = 28, XCore_ASHR_l3r = 29, XCore_BAU_1r = 30, XCore_BITREV_l2r = 31, XCore_BLACP_lu10 = 32, XCore_BLACP_u10 = 33, XCore_BLAT_lu6 = 34, XCore_BLAT_u6 = 35, XCore_BLA_1r = 36, XCore_BLRB_lu10 = 37, XCore_BLRB_u10 = 38, XCore_BLRF_lu10 = 39, XCore_BLRF_u10 = 40, XCore_BRBF_lru6 = 41, XCore_BRBF_ru6 = 42, XCore_BRBT_lru6 = 43, XCore_BRBT_ru6 = 44, XCore_BRBU_lu6 = 45, XCore_BRBU_u6 = 46, XCore_BRFF_lru6 = 47, XCore_BRFF_ru6 = 48, XCore_BRFT_lru6 = 49, XCore_BRFT_ru6 = 50, XCore_BRFU_lu6 = 51, XCore_BRFU_u6 = 52, XCore_BRU_1r = 53, XCore_BR_JT = 54, XCore_BR_JT32 = 55, XCore_BYTEREV_l2r = 56, XCore_CHKCT_2r = 57, XCore_CHKCT_rus = 58, XCore_CLRE_0R = 59, XCore_CLRPT_1R = 60, XCore_CLRSR_branch_lu6 = 61, XCore_CLRSR_branch_u6 = 62, XCore_CLRSR_lu6 = 63, XCore_CLRSR_u6 = 64, XCore_CLZ_l2r = 65, XCore_CRC8_l4r = 66, XCore_CRC_l3r = 67, XCore_DCALL_0R = 68, XCore_DENTSP_0R = 69, XCore_DGETREG_1r = 70, XCore_DIVS_l3r = 71, XCore_DIVU_l3r = 72, XCore_DRESTSP_0R = 73, XCore_DRET_0R = 74, XCore_ECALLF_1r = 75, XCore_ECALLT_1r = 76, XCore_EDU_1r = 77, XCore_EEF_2r = 78, XCore_EET_2r = 79, XCore_EEU_1r = 80, XCore_EH_RETURN = 81, XCore_ENDIN_2r = 82, XCore_ENTSP_lu6 = 83, XCore_ENTSP_u6 = 84, XCore_EQ_2rus = 85, XCore_EQ_3r = 86, XCore_EXTDP_lu6 = 87, XCore_EXTDP_u6 = 88, XCore_EXTSP_lu6 = 89, XCore_EXTSP_u6 = 90, XCore_FRAME_TO_ARGS_OFFSET = 91, XCore_FREER_1r = 92, XCore_FREET_0R = 93, XCore_GETD_l2r = 94, XCore_GETED_0R = 95, XCore_GETET_0R = 96, XCore_GETID_0R = 97, XCore_GETKEP_0R = 98, XCore_GETKSP_0R = 99, XCore_GETN_l2r = 100, XCore_GETPS_l2r = 101, XCore_GETR_rus = 102, XCore_GETSR_lu6 = 103, XCore_GETSR_u6 = 104, XCore_GETST_2r = 105, XCore_GETTS_2r = 106, XCore_INCT_2r = 107, XCore_INITCP_2r = 108, XCore_INITDP_2r = 109, XCore_INITLR_l2r = 110, XCore_INITPC_2r = 111, XCore_INITSP_2r = 112, XCore_INPW_l2rus = 113, XCore_INSHR_2r = 114, XCore_INT_2r = 115, XCore_IN_2r = 116, XCore_Int_MemBarrier = 117, XCore_KCALL_1r = 118, XCore_KCALL_lu6 = 119, XCore_KCALL_u6 = 120, XCore_KENTSP_lu6 = 121, XCore_KENTSP_u6 = 122, XCore_KRESTSP_lu6 = 123, XCore_KRESTSP_u6 = 124, XCore_KRET_0R = 125, XCore_LADD_l5r = 126, XCore_LD16S_3r = 127, XCore_LD8U_3r = 128, XCore_LDA16B_l3r = 129, XCore_LDA16F_l3r = 130, XCore_LDAPB_lu10 = 131, XCore_LDAPB_u10 = 132, XCore_LDAPF_lu10 = 133, XCore_LDAPF_lu10_ba = 134, XCore_LDAPF_u10 = 135, XCore_LDAWB_l2rus = 136, XCore_LDAWB_l3r = 137, XCore_LDAWCP_lu6 = 138, XCore_LDAWCP_u6 = 139, XCore_LDAWDP_lru6 = 140, XCore_LDAWDP_ru6 = 141, XCore_LDAWFI = 142, XCore_LDAWF_l2rus = 143, XCore_LDAWF_l3r = 144, XCore_LDAWSP_lru6 = 145, XCore_LDAWSP_ru6 = 146, XCore_LDC_lru6 = 147, XCore_LDC_ru6 = 148, XCore_LDET_0R = 149, XCore_LDIVU_l5r = 150, XCore_LDSED_0R = 151, XCore_LDSPC_0R = 152, XCore_LDSSR_0R = 153, XCore_LDWCP_lru6 = 154, XCore_LDWCP_lu10 = 155, XCore_LDWCP_ru6 = 156, XCore_LDWCP_u10 = 157, XCore_LDWDP_lru6 = 158, XCore_LDWDP_ru6 = 159, XCore_LDWFI = 160, XCore_LDWSP_lru6 = 161, XCore_LDWSP_ru6 = 162, XCore_LDW_2rus = 163, XCore_LDW_3r = 164, XCore_LMUL_l6r = 165, XCore_LSS_3r = 166, XCore_LSUB_l5r = 167, XCore_LSU_3r = 168, XCore_MACCS_l4r = 169, XCore_MACCU_l4r = 170, XCore_MJOIN_1r = 171, XCore_MKMSK_2r = 172, XCore_MKMSK_rus = 173, XCore_MSYNC_1r = 174, XCore_MUL_l3r = 175, XCore_NEG = 176, XCore_NOT = 177, XCore_OR_3r = 178, XCore_OUTCT_2r = 179, XCore_OUTCT_rus = 180, XCore_OUTPW_l2rus = 181, XCore_OUTSHR_2r = 182, XCore_OUTT_2r = 183, XCore_OUT_2r = 184, XCore_PEEK_2r = 185, XCore_REMS_l3r = 186, XCore_REMU_l3r = 187, XCore_RETSP_lu6 = 188, XCore_RETSP_u6 = 189, XCore_SELECT_CC = 190, XCore_SETCLK_l2r = 191, XCore_SETCP_1r = 192, XCore_SETC_l2r = 193, XCore_SETC_lru6 = 194, XCore_SETC_ru6 = 195, XCore_SETDP_1r = 196, XCore_SETD_2r = 197, XCore_SETEV_1r = 198, XCore_SETKEP_0R = 199, XCore_SETN_l2r = 200, XCore_SETPSC_2r = 201, XCore_SETPS_l2r = 202, XCore_SETPT_2r = 203, XCore_SETRDY_l2r = 204, XCore_SETSP_1r = 205, XCore_SETSR_branch_lu6 = 206, XCore_SETSR_branch_u6 = 207, XCore_SETSR_lu6 = 208, XCore_SETSR_u6 = 209, XCore_SETTW_l2r = 210, XCore_SETV_1r = 211, XCore_SEXT_2r = 212, XCore_SEXT_rus = 213, XCore_SHL_2rus = 214, XCore_SHL_3r = 215, XCore_SHR_2rus = 216, XCore_SHR_3r = 217, XCore_SSYNC_0r = 218, XCore_ST16_l3r = 219, XCore_ST8_l3r = 220, XCore_STET_0R = 221, XCore_STSED_0R = 222, XCore_STSPC_0R = 223, XCore_STSSR_0R = 224, XCore_STWDP_lru6 = 225, XCore_STWDP_ru6 = 226, XCore_STWFI = 227, XCore_STWSP_lru6 = 228, XCore_STWSP_ru6 = 229, XCore_STW_2rus = 230, XCore_STW_l3r = 231, XCore_SUB_2rus = 232, XCore_SUB_3r = 233, XCore_SYNCR_1r = 234, XCore_TESTCT_2r = 235, XCore_TESTLCL_l2r = 236, XCore_TESTWCT_2r = 237, XCore_TSETMR_2r = 238, XCore_TSETR_3r = 239, XCore_TSTART_1R = 240, XCore_WAITEF_1R = 241, XCore_WAITET_1R = 242, XCore_WAITEU_0R = 243, XCore_XOR_l3r = 244, XCore_ZEXT_2r = 245, XCore_ZEXT_rus = 246, XCore_INSTRUCTION_LIST_END = 247 }; #endif // GET_INSTRINFO_ENUM capstone-sys-0.15.0/capstone/arch/XCore/XCoreGenRegisterInfo.inc000064400000000000000000000061730072674642500226350ustar 00000000000000/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { XCore_NoRegister, XCore_CP = 1, XCore_DP = 2, XCore_LR = 3, XCore_SP = 4, XCore_R0 = 5, XCore_R1 = 6, XCore_R2 = 7, XCore_R3 = 8, XCore_R4 = 9, XCore_R5 = 10, XCore_R6 = 11, XCore_R7 = 12, XCore_R8 = 13, XCore_R9 = 14, XCore_R10 = 15, XCore_R11 = 16, XCore_NUM_TARGET_REGS // 17 }; // Register classes enum { XCore_RRegsRegClassID = 0, XCore_GRRegsRegClassID = 1 }; #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |*MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC static const MCPhysReg XCoreRegDiffLists[] = { /* 0 */ 65535, 0, }; static const uint16_t XCoreSubRegIdxLists[] = { /* 0 */ 0, }; static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors { 3, 0, 0, 0, 0, 0 }, { 38, 1, 1, 0, 1, 0 }, { 41, 1, 1, 0, 1, 0 }, { 47, 1, 1, 0, 1, 0 }, { 44, 1, 1, 0, 1, 0 }, { 4, 1, 1, 0, 1, 0 }, { 11, 1, 1, 0, 1, 0 }, { 14, 1, 1, 0, 1, 0 }, { 17, 1, 1, 0, 1, 0 }, { 20, 1, 1, 0, 1, 0 }, { 23, 1, 1, 0, 1, 0 }, { 26, 1, 1, 0, 1, 0 }, { 29, 1, 1, 0, 1, 0 }, { 32, 1, 1, 0, 1, 0 }, { 35, 1, 1, 0, 1, 0 }, { 0, 1, 1, 0, 1, 0 }, { 7, 1, 1, 0, 1, 0 }, }; // RRegs Register Class... static const MCPhysReg RRegs[] = { XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR, }; // RRegs Bit set. static const uint8_t RRegsBits[] = { 0xfe, 0xff, 0x01, }; // GRRegs Register Class... static const MCPhysReg GRRegs[] = { XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, }; // GRRegs Bit set. static const uint8_t GRRegsBits[] = { 0xe0, 0xff, 0x01, }; static const MCRegisterClass XCoreMCRegisterClasses[] = { { RRegs, RRegsBits, sizeof(RRegsBits) }, { GRRegs, GRRegsBits, sizeof(GRRegsBits) }, }; #endif // GET_REGINFO_MC_DESC capstone-sys-0.15.0/capstone/arch/XCore/XCoreInstPrinter.c000064400000000000000000000175060072674642500215370ustar 00000000000000//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax --------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This class prints an XCore MCInst to a .s file. // //===----------------------------------------------------------------------===// /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_XCORE #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable : 4996) // disable MSVC's warning on strcpy() #pragma warning(disable : 28719) // disable MSVC's warning on strcpy() #endif #include #include #include #include #include "XCoreInstPrinter.h" #include "../../MCInst.h" #include "../../utils.h" #include "../../SStream.h" #include "../../MCRegisterInfo.h" #include "../../MathExtras.h" #include "XCoreMapping.h" static const char *getRegisterName(unsigned RegNo); void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { /* if (((cs_struct *)ud)->detail != CS_OPT_ON) return; */ } // stw sed, sp[3] void XCore_insn_extract(MCInst *MI, const char *code) { int id; char *p, *p2; char tmp[128]; strcpy(tmp, code); // safe because code is way shorter than 128 bytes // find the first space p = strchr(tmp, ' '); if (p) { p++; // find the next ',' p2 = strchr(p, ','); if (p2) { *p2 = '\0'; id = XCore_reg_id(p); if (id) { // register if (MI->csh->detail) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; MI->flat_insn->detail->xcore.op_count++; } } // next should be register, or memory? // skip space p2++; while(*p2 && *p2 == ' ') p2++; if (*p2) { // find '[' p = p2; while(*p && *p != '[') p++; if (*p) { // this is '[' *p = '\0'; id = XCore_reg_id(p2); if (id) { // base register if (MI->csh->detail) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; } p++; p2 = p; // until ']' while(*p && *p != ']') p++; if (*p) { *p = '\0'; // p2 is either index, or disp id = XCore_reg_id(p2); if (id) { // index register if (MI->csh->detail) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id; } } else { // a number means disp if (MI->csh->detail) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2); } } } if (MI->csh->detail) { MI->flat_insn->detail->xcore.op_count++; } } } else { // a register? id = XCore_reg_id(p2); if (id) { // register if (MI->csh->detail) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; MI->flat_insn->detail->xcore.op_count++; } } } } } else { id = XCore_reg_id(p); if (id) { // register if (MI->csh->detail) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; MI->flat_insn->detail->xcore.op_count++; } } } } } static void set_mem_access(MCInst *MI, bool status, int reg) { if (MI->csh->detail != CS_OPT_ON) return; MI->csh->doing_mem = status; if (status) { if (reg != 0xffff && reg != -0xffff) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; if (reg) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; } else { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID; } MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; } else { // the last op should be the memory base MI->flat_insn->detail->xcore.op_count--; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; if (reg > 0) MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1; else MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = -1; } } else { if (reg) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg; // done, create the next operand slot MI->flat_insn->detail->xcore.op_count++; } } } static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O) { if (MCOperand_isReg(MO)) { unsigned reg; reg = MCOperand_getReg(MO); SStream_concat0(O, getRegisterName(reg)); if (MI->csh->detail) { if (MI->csh->doing_mem) { if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID) MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg; else MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg; } else { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg; MI->flat_insn->detail->xcore.op_count++; } } } else if (MCOperand_isImm(MO)) { int32_t Imm = (int32_t)MCOperand_getImm(MO); printInt32(O, Imm); if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm; } else { MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM; MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm; MI->flat_insn->detail->xcore.op_count++; } } } } static void printOperand(MCInst *MI, int OpNum, SStream *O) { if (OpNum >= MI->size) return; _printOperand(MI, MCInst_getOperand(MI, OpNum), O); } static void printInlineJT(MCInst *MI, int OpNum, SStream *O) { } static void printInlineJT32(MCInst *MI, int OpNum, SStream *O) { } #define PRINT_ALIAS_INSTR #include "XCoreGenAsmWriter.inc" void XCore_printInst(MCInst *MI, SStream *O, void *Info) { printInstruction(MI, O, Info); set_mem_access(MI, false, 0); } #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreInstPrinter.h000064400000000000000000000007440072674642500215400ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_XCOREINSTPRINTER_H #define CS_XCOREINSTPRINTER_H #include "../../MCInst.h" #include "../../MCRegisterInfo.h" #include "../../SStream.h" void XCore_printInst(MCInst *MI, SStream *O, void *Info); void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci); // extract details from assembly code @code void XCore_insn_extract(MCInst *MI, const char *code); #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreMapping.c000064400000000000000000000161300072674642500206410ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_XCORE #include // debug #include #include "../../utils.h" #include "XCoreMapping.h" #define GET_INSTRINFO_ENUM #include "XCoreGenInstrInfo.inc" static const name_map reg_name_maps[] = { { XCORE_REG_INVALID, NULL }, { XCORE_REG_CP, "cp" }, { XCORE_REG_DP, "dp" }, { XCORE_REG_LR, "lr" }, { XCORE_REG_SP, "sp" }, { XCORE_REG_R0, "r0" }, { XCORE_REG_R1, "r1" }, { XCORE_REG_R2, "r2" }, { XCORE_REG_R3, "r3" }, { XCORE_REG_R4, "r4" }, { XCORE_REG_R5, "r5" }, { XCORE_REG_R6, "r6" }, { XCORE_REG_R7, "r7" }, { XCORE_REG_R8, "r8" }, { XCORE_REG_R9, "r9" }, { XCORE_REG_R10, "r10" }, { XCORE_REG_R11, "r11" }, // pseudo registers { XCORE_REG_PC, "pc" }, { XCORE_REG_SCP, "scp" }, { XCORE_REG_SSR, "ssr" }, { XCORE_REG_ET, "et" }, { XCORE_REG_ED, "ed" }, { XCORE_REG_SED, "sed" }, { XCORE_REG_KEP, "kep" }, { XCORE_REG_KSP, "ksp" }, { XCORE_REG_ID, "id" }, }; const char *XCore_reg_name(csh handle, unsigned int reg) { #ifndef CAPSTONE_DIET if (reg >= ARR_SIZE(reg_name_maps)) return NULL; return reg_name_maps[reg].name; #else return NULL; #endif } xcore_reg XCore_reg_id(char *name) { int i; for(i = 1; i < ARR_SIZE(reg_name_maps); i++) { if (!strcmp(name, reg_name_maps[i].name)) return reg_name_maps[i].id; } // not found return 0; } static const insn_map insns[] = { // dummy item { 0, 0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, #include "XCoreMappingInsn.inc" }; // given internal insn id, return public instruction info void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { unsigned short i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { insn->id = insns[i].mapid; if (h->detail) { #ifndef CAPSTONE_DIET memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group insn->detail->groups[insn->detail->groups_count] = XCORE_GRP_JUMP; insn->detail->groups_count++; } #endif } } } #ifndef CAPSTONE_DIET static const name_map insn_name_maps[] = { { XCORE_INS_INVALID, NULL }, { XCORE_INS_ADD, "add" }, { XCORE_INS_ANDNOT, "andnot" }, { XCORE_INS_AND, "and" }, { XCORE_INS_ASHR, "ashr" }, { XCORE_INS_BAU, "bau" }, { XCORE_INS_BITREV, "bitrev" }, { XCORE_INS_BLA, "bla" }, { XCORE_INS_BLAT, "blat" }, { XCORE_INS_BL, "bl" }, { XCORE_INS_BF, "bf" }, { XCORE_INS_BT, "bt" }, { XCORE_INS_BU, "bu" }, { XCORE_INS_BRU, "bru" }, { XCORE_INS_BYTEREV, "byterev" }, { XCORE_INS_CHKCT, "chkct" }, { XCORE_INS_CLRE, "clre" }, { XCORE_INS_CLRPT, "clrpt" }, { XCORE_INS_CLRSR, "clrsr" }, { XCORE_INS_CLZ, "clz" }, { XCORE_INS_CRC8, "crc8" }, { XCORE_INS_CRC32, "crc32" }, { XCORE_INS_DCALL, "dcall" }, { XCORE_INS_DENTSP, "dentsp" }, { XCORE_INS_DGETREG, "dgetreg" }, { XCORE_INS_DIVS, "divs" }, { XCORE_INS_DIVU, "divu" }, { XCORE_INS_DRESTSP, "drestsp" }, { XCORE_INS_DRET, "dret" }, { XCORE_INS_ECALLF, "ecallf" }, { XCORE_INS_ECALLT, "ecallt" }, { XCORE_INS_EDU, "edu" }, { XCORE_INS_EEF, "eef" }, { XCORE_INS_EET, "eet" }, { XCORE_INS_EEU, "eeu" }, { XCORE_INS_ENDIN, "endin" }, { XCORE_INS_ENTSP, "entsp" }, { XCORE_INS_EQ, "eq" }, { XCORE_INS_EXTDP, "extdp" }, { XCORE_INS_EXTSP, "extsp" }, { XCORE_INS_FREER, "freer" }, { XCORE_INS_FREET, "freet" }, { XCORE_INS_GETD, "getd" }, { XCORE_INS_GET, "get" }, { XCORE_INS_GETN, "getn" }, { XCORE_INS_GETR, "getr" }, { XCORE_INS_GETSR, "getsr" }, { XCORE_INS_GETST, "getst" }, { XCORE_INS_GETTS, "getts" }, { XCORE_INS_INCT, "inct" }, { XCORE_INS_INIT, "init" }, { XCORE_INS_INPW, "inpw" }, { XCORE_INS_INSHR, "inshr" }, { XCORE_INS_INT, "int" }, { XCORE_INS_IN, "in" }, { XCORE_INS_KCALL, "kcall" }, { XCORE_INS_KENTSP, "kentsp" }, { XCORE_INS_KRESTSP, "krestsp" }, { XCORE_INS_KRET, "kret" }, { XCORE_INS_LADD, "ladd" }, { XCORE_INS_LD16S, "ld16s" }, { XCORE_INS_LD8U, "ld8u" }, { XCORE_INS_LDA16, "lda16" }, { XCORE_INS_LDAP, "ldap" }, { XCORE_INS_LDAW, "ldaw" }, { XCORE_INS_LDC, "ldc" }, { XCORE_INS_LDW, "ldw" }, { XCORE_INS_LDIVU, "ldivu" }, { XCORE_INS_LMUL, "lmul" }, { XCORE_INS_LSS, "lss" }, { XCORE_INS_LSUB, "lsub" }, { XCORE_INS_LSU, "lsu" }, { XCORE_INS_MACCS, "maccs" }, { XCORE_INS_MACCU, "maccu" }, { XCORE_INS_MJOIN, "mjoin" }, { XCORE_INS_MKMSK, "mkmsk" }, { XCORE_INS_MSYNC, "msync" }, { XCORE_INS_MUL, "mul" }, { XCORE_INS_NEG, "neg" }, { XCORE_INS_NOT, "not" }, { XCORE_INS_OR, "or" }, { XCORE_INS_OUTCT, "outct" }, { XCORE_INS_OUTPW, "outpw" }, { XCORE_INS_OUTSHR, "outshr" }, { XCORE_INS_OUTT, "outt" }, { XCORE_INS_OUT, "out" }, { XCORE_INS_PEEK, "peek" }, { XCORE_INS_REMS, "rems" }, { XCORE_INS_REMU, "remu" }, { XCORE_INS_RETSP, "retsp" }, { XCORE_INS_SETCLK, "setclk" }, { XCORE_INS_SET, "set" }, { XCORE_INS_SETC, "setc" }, { XCORE_INS_SETD, "setd" }, { XCORE_INS_SETEV, "setev" }, { XCORE_INS_SETN, "setn" }, { XCORE_INS_SETPSC, "setpsc" }, { XCORE_INS_SETPT, "setpt" }, { XCORE_INS_SETRDY, "setrdy" }, { XCORE_INS_SETSR, "setsr" }, { XCORE_INS_SETTW, "settw" }, { XCORE_INS_SETV, "setv" }, { XCORE_INS_SEXT, "sext" }, { XCORE_INS_SHL, "shl" }, { XCORE_INS_SHR, "shr" }, { XCORE_INS_SSYNC, "ssync" }, { XCORE_INS_ST16, "st16" }, { XCORE_INS_ST8, "st8" }, { XCORE_INS_STW, "stw" }, { XCORE_INS_SUB, "sub" }, { XCORE_INS_SYNCR, "syncr" }, { XCORE_INS_TESTCT, "testct" }, { XCORE_INS_TESTLCL, "testlcl" }, { XCORE_INS_TESTWCT, "testwct" }, { XCORE_INS_TSETMR, "tsetmr" }, { XCORE_INS_START, "start" }, { XCORE_INS_WAITEF, "waitef" }, { XCORE_INS_WAITET, "waitet" }, { XCORE_INS_WAITEU, "waiteu" }, { XCORE_INS_XOR, "xor" }, { XCORE_INS_ZEXT, "zext" }, }; // special alias insn static const name_map alias_insn_names[] = { { 0, NULL } }; #endif const char *XCore_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET unsigned int i; if (id >= XCORE_INS_ENDING) return NULL; // handle special alias first for (i = 0; i < ARR_SIZE(alias_insn_names); i++) { if (alias_insn_names[i].id == id) return alias_insn_names[i].name; } return insn_name_maps[id].name; #else return NULL; #endif } #ifndef CAPSTONE_DIET static const name_map group_name_maps[] = { { XCORE_GRP_INVALID, NULL }, { XCORE_GRP_JUMP, "jump" }, }; #endif const char *XCore_group_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); #else return NULL; #endif } // map internal raw register to 'public' register xcore_reg XCore_map_register(unsigned int r) { static const unsigned int map[] = { 0, }; if (r < ARR_SIZE(map)) return map[r]; // cannot find this register return 0; } #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreMapping.h000064400000000000000000000012740072674642500206510ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifndef CS_XCORE_MAP_H #define CS_XCORE_MAP_H #include "capstone/capstone.h" // return name of regiser in friendly string const char *XCore_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); const char *XCore_insn_name(csh handle, unsigned int id); const char *XCore_group_name(csh handle, unsigned int id); // map internal raw register to 'public' register xcore_reg XCore_map_register(unsigned int r); // map register name to register ID xcore_reg XCore_reg_id(char *name); #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreMappingInsn.inc000064400000000000000000000525560072674642500220340ustar 00000000000000// This is auto-gen data for Capstone engine (www.capstone-engine.org) // By Nguyen Anh Quynh { XCore_ADD_2rus, XCORE_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ADD_3r, XCORE_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ANDNOT_2r, XCORE_INS_ANDNOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_AND_3r, XCORE_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ASHR_l2rus, XCORE_INS_ASHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ASHR_l3r, XCORE_INS_ASHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_BAU_1r, XCORE_INS_BAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_BITREV_l2r, XCORE_INS_BITREV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_BLACP_lu10, XCORE_INS_BLA, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BLACP_u10, XCORE_INS_BLA, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BLAT_lu6, XCORE_INS_BLAT, #ifndef CAPSTONE_DIET { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_BLAT_u6, XCORE_INS_BLAT, #ifndef CAPSTONE_DIET { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_BLA_1r, XCORE_INS_BLA, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BLRB_lu10, XCORE_INS_BL, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BLRB_u10, XCORE_INS_BL, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BLRF_lu10, XCORE_INS_BL, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BLRF_u10, XCORE_INS_BL, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R11, XCORE_REG_LR, 0 }, { 0 }, 0, 0 #endif }, { XCore_BRBF_lru6, XCORE_INS_BF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRBF_ru6, XCORE_INS_BF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRBT_lru6, XCORE_INS_BT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRBT_ru6, XCORE_INS_BT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRBU_lu6, XCORE_INS_BU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRBU_u6, XCORE_INS_BU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRFF_lru6, XCORE_INS_BF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRFF_ru6, XCORE_INS_BF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRFT_lru6, XCORE_INS_BT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRFT_ru6, XCORE_INS_BT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRFU_lu6, XCORE_INS_BU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRFU_u6, XCORE_INS_BU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 0 #endif }, { XCore_BRU_1r, XCORE_INS_BRU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_BYTEREV_l2r, XCORE_INS_BYTEREV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CHKCT_2r, XCORE_INS_CHKCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CHKCT_rus, XCORE_INS_CHKCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CLRE_0R, XCORE_INS_CLRE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CLRPT_1R, XCORE_INS_CLRPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CLRSR_branch_lu6, XCORE_INS_CLRSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_CLRSR_branch_u6, XCORE_INS_CLRSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_CLRSR_lu6, XCORE_INS_CLRSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CLRSR_u6, XCORE_INS_CLRSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CLZ_l2r, XCORE_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CRC8_l4r, XCORE_INS_CRC8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_CRC_l3r, XCORE_INS_CRC32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_DCALL_0R, XCORE_INS_DCALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_DENTSP_0R, XCORE_INS_DENTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_DGETREG_1r, XCORE_INS_DGETREG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_DIVS_l3r, XCORE_INS_DIVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_DIVU_l3r, XCORE_INS_DIVU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_DRESTSP_0R, XCORE_INS_DRESTSP, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_DRET_0R, XCORE_INS_DRET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ECALLF_1r, XCORE_INS_ECALLF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ECALLT_1r, XCORE_INS_ECALLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EDU_1r, XCORE_INS_EDU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EEF_2r, XCORE_INS_EEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EET_2r, XCORE_INS_EET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EEU_1r, XCORE_INS_EEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ENDIN_2r, XCORE_INS_ENDIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ENTSP_lu6, XCORE_INS_ENTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_ENTSP_u6, XCORE_INS_ENTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_EQ_2rus, XCORE_INS_EQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EQ_3r, XCORE_INS_EQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EXTDP_lu6, XCORE_INS_EXTDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EXTDP_u6, XCORE_INS_EXTDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_EXTSP_lu6, XCORE_INS_EXTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_EXTSP_u6, XCORE_INS_EXTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_FREER_1r, XCORE_INS_FREER, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_FREET_0R, XCORE_INS_FREET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_GETD_l2r, XCORE_INS_GETD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_GETED_0R, XCORE_INS_GET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETET_0R, XCORE_INS_GET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETID_0R, XCORE_INS_GET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETKEP_0R, XCORE_INS_GET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETKSP_0R, XCORE_INS_GET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETN_l2r, XCORE_INS_GETN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_GETPS_l2r, XCORE_INS_GET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_GETR_rus, XCORE_INS_GETR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_GETSR_lu6, XCORE_INS_GETSR, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETSR_u6, XCORE_INS_GETSR, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_GETST_2r, XCORE_INS_GETST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_GETTS_2r, XCORE_INS_GETTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INCT_2r, XCORE_INS_INCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INITCP_2r, XCORE_INS_INIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INITDP_2r, XCORE_INS_INIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INITLR_l2r, XCORE_INS_INIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INITPC_2r, XCORE_INS_INIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INITSP_2r, XCORE_INS_INIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INPW_l2rus, XCORE_INS_INPW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INSHR_2r, XCORE_INS_INSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_INT_2r, XCORE_INS_INT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_IN_2r, XCORE_INS_IN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_KCALL_1r, XCORE_INS_KCALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_KCALL_lu6, XCORE_INS_KCALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_KCALL_u6, XCORE_INS_KCALL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_KENTSP_lu6, XCORE_INS_KENTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_KENTSP_u6, XCORE_INS_KENTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_KRESTSP_lu6, XCORE_INS_KRESTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_KRESTSP_u6, XCORE_INS_KRESTSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_KRET_0R, XCORE_INS_KRET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_LADD_l5r, XCORE_INS_LADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LD16S_3r, XCORE_INS_LD16S, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LD8U_3r, XCORE_INS_LD8U, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDA16B_l3r, XCORE_INS_LDA16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDA16F_l3r, XCORE_INS_LDA16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAPB_lu10, XCORE_INS_LDAP, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAPB_u10, XCORE_INS_LDAP, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAPF_lu10, XCORE_INS_LDAP, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAPF_lu10_ba, XCORE_INS_LDAP, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAPF_u10, XCORE_INS_LDAP, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWB_l2rus, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWB_l3r, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWCP_lu6, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWCP_u6, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWDP_lru6, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWDP_ru6, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWF_l2rus, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWF_l3r, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWSP_lru6, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDAWSP_ru6, XCORE_INS_LDAW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDC_lru6, XCORE_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDC_ru6, XCORE_INS_LDC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDET_0R, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDIVU_l5r, XCORE_INS_LDIVU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDSED_0R, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDSPC_0R, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDSSR_0R, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWCP_lru6, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWCP_lu10, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWCP_ru6, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWCP_u10, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_R11, 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWDP_lru6, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWDP_ru6, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWSP_lru6, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDWSP_ru6, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDW_2rus, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LDW_3r, XCORE_INS_LDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LMUL_l6r, XCORE_INS_LMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LSS_3r, XCORE_INS_LSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LSUB_l5r, XCORE_INS_LSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_LSU_3r, XCORE_INS_LSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MACCS_l4r, XCORE_INS_MACCS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MACCU_l4r, XCORE_INS_MACCU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MJOIN_1r, XCORE_INS_MJOIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MKMSK_2r, XCORE_INS_MKMSK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MKMSK_rus, XCORE_INS_MKMSK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MSYNC_1r, XCORE_INS_MSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_MUL_l3r, XCORE_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_NEG, XCORE_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_NOT, XCORE_INS_NOT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OR_3r, XCORE_INS_OR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OUTCT_2r, XCORE_INS_OUTCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OUTCT_rus, XCORE_INS_OUTCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OUTPW_l2rus, XCORE_INS_OUTPW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OUTSHR_2r, XCORE_INS_OUTSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OUTT_2r, XCORE_INS_OUTT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_OUT_2r, XCORE_INS_OUT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_PEEK_2r, XCORE_INS_PEEK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_REMS_l3r, XCORE_INS_REMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_REMU_l3r, XCORE_INS_REMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_RETSP_lu6, XCORE_INS_RETSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_RETSP_u6, XCORE_INS_RETSP, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_SETCLK_l2r, XCORE_INS_SETCLK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETCP_1r, XCORE_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETC_l2r, XCORE_INS_SETC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETC_lru6, XCORE_INS_SETC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETC_ru6, XCORE_INS_SETC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETDP_1r, XCORE_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETD_2r, XCORE_INS_SETD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETEV_1r, XCORE_INS_SETEV, #ifndef CAPSTONE_DIET { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETKEP_0R, XCORE_INS_SET, #ifndef CAPSTONE_DIET { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETN_l2r, XCORE_INS_SETN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETPSC_2r, XCORE_INS_SETPSC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETPS_l2r, XCORE_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETPT_2r, XCORE_INS_SETPT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETRDY_l2r, XCORE_INS_SETRDY, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETSP_1r, XCORE_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { XCORE_REG_SP, 0 }, { 0 }, 0, 0 #endif }, { XCore_SETSR_branch_lu6, XCORE_INS_SETSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_SETSR_branch_u6, XCORE_INS_SETSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_SETSR_lu6, XCORE_INS_SETSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETSR_u6, XCORE_INS_SETSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETTW_l2r, XCORE_INS_SETTW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SETV_1r, XCORE_INS_SETV, #ifndef CAPSTONE_DIET { XCORE_REG_R11, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SEXT_2r, XCORE_INS_SEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SEXT_rus, XCORE_INS_SEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SHL_2rus, XCORE_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SHL_3r, XCORE_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SHR_2rus, XCORE_INS_SHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SHR_3r, XCORE_INS_SHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SSYNC_0r, XCORE_INS_SSYNC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ST16_l3r, XCORE_INS_ST16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ST8_l3r, XCORE_INS_ST8, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STET_0R, XCORE_INS_STW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STSED_0R, XCORE_INS_STW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STSPC_0R, XCORE_INS_STW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STSSR_0R, XCORE_INS_STW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STWDP_lru6, XCORE_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STWDP_ru6, XCORE_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STWSP_lru6, XCORE_INS_STW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STWSP_ru6, XCORE_INS_STW, #ifndef CAPSTONE_DIET { XCORE_REG_SP, 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STW_2rus, XCORE_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_STW_l3r, XCORE_INS_STW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SUB_2rus, XCORE_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SUB_3r, XCORE_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_SYNCR_1r, XCORE_INS_SYNCR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_TESTCT_2r, XCORE_INS_TESTCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_TESTLCL_l2r, XCORE_INS_TESTLCL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_TESTWCT_2r, XCORE_INS_TESTWCT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_TSETMR_2r, XCORE_INS_TSETMR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_TSETR_3r, XCORE_INS_SET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_TSTART_1R, XCORE_INS_START, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_WAITEF_1R, XCORE_INS_WAITEF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_WAITET_1R, XCORE_INS_WAITET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_WAITEU_0R, XCORE_INS_WAITEU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 1, 1 #endif }, { XCore_XOR_l3r, XCORE_INS_XOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ZEXT_2r, XCORE_INS_ZEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, { XCore_ZEXT_rus, XCORE_INS_ZEXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, capstone-sys-0.15.0/capstone/arch/XCore/XCoreModule.c000064400000000000000000000016710072674642500204770ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef CAPSTONE_HAS_XCORE #include "../../utils.h" #include "../../MCRegisterInfo.h" #include "XCoreDisassembler.h" #include "XCoreInstPrinter.h" #include "XCoreMapping.h" #include "XCoreModule.h" cs_err XCore_global_init(cs_struct *ud) { MCRegisterInfo *mri; mri = cs_mem_malloc(sizeof(*mri)); XCore_init(mri); ud->printer = XCore_printInst; ud->printer_info = mri; ud->getinsn_info = mri; ud->disasm = XCore_getInstruction; ud->post_printer = XCore_post_printer; ud->reg_name = XCore_reg_name; ud->insn_id = XCore_get_insn_id; ud->insn_name = XCore_insn_name; ud->group_name = XCore_group_name; return CS_ERR_OK; } cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value) { // Do not set mode because only CS_MODE_BIG_ENDIAN is valid; we cannot // test for CS_MODE_LITTLE_ENDIAN because it is 0 return CS_ERR_OK; } #endif capstone-sys-0.15.0/capstone/arch/XCore/XCoreModule.h000064400000000000000000000004410072674642500204760ustar 00000000000000/* Capstone Disassembly Engine */ /* By Travis Finkenauer , 2018 */ #ifndef CS_XCORE_MODULE_H #define CS_XCORE_MODULE_H #include "../../utils.h" cs_err XCore_global_init(cs_struct *ud); cs_err XCore_option(cs_struct *handle, cs_opt_type type, size_t value); #endif capstone-sys-0.15.0/capstone/bindings/Makefile000064400000000000000000000057600072674642500174500ustar 00000000000000TMPDIR = /tmp/capstone_test DIFF = diff -u -w TEST = $(TMPDIR)/test TEST_ARM = $(TMPDIR)/test_arm TEST_ARM64 = $(TMPDIR)/test_arm64 TEST_M68K = $(TMPDIR)/test_m68k TEST_MIPS = $(TMPDIR)/test_mips TEST_MOS65XX = $(TMPDIR)/test_mos65xx TEST_PPC = $(TMPDIR)/test_ppc TEST_SPARC = $(TMPDIR)/test_sparc TEST_SYSZ = $(TMPDIR)/test_systemz TEST_X86 = $(TMPDIR)/test_x86 TEST_XCORE = $(TMPDIR)/test_xcore TEST_BPF = $(TMPDIR)/test_bpf TEST_RISCV = $(TMPDIR)/test_riscv PYTHON2 ?= python .PHONY: all expected python java ocaml all: cd python && $(MAKE) gen_const cd java && $(MAKE) gen_const cd ocaml && $(MAKE) gen_const tests: expected python java #oclma ruby test_java: expected java test_python: expected python expected: cd ../tests && $(MAKE) mkdir -p $(TMPDIR) ../tests/test > $(TEST)_e ../tests/test_arm > $(TEST_ARM)_e ../tests/test_arm64 > $(TEST_ARM64)_e ../tests/test_m68k > $(TEST_M68K)_e ../tests/test_mips > $(TEST_MIPS)_e ../tests/test_mos65xx > $(TEST_MOS65XX)_e ../tests/test_ppc > $(TEST_PPC)_e ../tests/test_sparc > $(TEST_SPARC)_e ../tests/test_systemz > $(TEST_SYSZ)_e ../tests/test_x86 > $(TEST_X86)_e ../tests/test_xcore > $(TEST_XCORE)_e ../tests/test_bpf > $(TEST_BPF)_e ../tests/test_riscv > $(TEST_RISCV)_e python: FORCE cd python && $(MAKE) $(PYTHON2) python/test.py > $(TEST)_o $(PYTHON2) python/test_arm.py > $(TEST_ARM)_o $(PYTHON2) python/test_arm64.py > $(TEST_ARM64)_o $(PYTHON2) python/test_m68k.py > $(TEST_M68K)_o $(PYTHON2) python/test_mips.py > $(TEST_MIPS)_o $(PYTHON2) python/test_mos65xx.py > $(TEST_MOS65XX)_o $(PYTHON2) python/test_ppc.py > $(TEST_PPC)_o $(PYTHON2) python/test_sparc.py > $(TEST_SPARC)_o $(PYTHON2) python/test_systemz.py > $(TEST_SYSZ)_o $(PYTHON2) python/test_x86.py > $(TEST_X86)_o $(PYTHON2) python/test_xcore.py > $(TEST_XCORE)_o $(PYTHON2) python/test_bpf.py > $(TEST_BPF)_o $(PYTHON2) python/test_riscv.py > $(TEST_RISCV)_o $(MAKE) test_diff java: FORCE cd java && $(MAKE) cd java && ./run.sh > $(TEST)_o cd java && ./run.sh arm > $(TEST_ARM)_o cd java && ./run.sh arm64 > $(TEST_ARM64)_o cd java && ./run.sh mips > $(TEST_MIPS)_o cd java && ./run.sh ppc > $(TEST_PPC)_o cd java && ./run.sh sparc > $(TEST_SPARC)_o cd java && ./run.sh systemz > $(TEST_SYSZ)_o cd java && ./run.sh x86 > $(TEST_X86)_o cd java && ./run.sh xcore > $(TEST_XCORE)_o $(MAKE) test_diff ocaml: FORCE test_diff: FORCE $(DIFF) $(TEST)_e $(TEST)_o $(DIFF) $(TEST_ARM)_e $(TEST_ARM)_o $(DIFF) $(TEST_ARM64)_e $(TEST_ARM64)_o $(DIFF) $(TEST_M68K)_e $(TEST_M68K)_o $(DIFF) $(TEST_MIPS)_e $(TEST_MIPS)_o $(DIFF) $(TEST_MOS65XX)_e $(TEST_MOS65XX)_o $(DIFF) $(TEST_PPC)_e $(TEST_PPC)_o $(DIFF) $(TEST_SPARC)_e $(TEST_SPARC)_o $(DIFF) $(TEST_SYSZ)_e $(TEST_SYSZ)_o $(DIFF) $(TEST_X86)_e $(TEST_X86)_o $(DIFF) $(TEST_XCORE)_e $(TEST_XCORE)_o $(DIFF) $(TEST_BPF)_e $(TEST_BPF)_o clean: rm -rf $(TMPDIR) cd java && $(MAKE) clean cd python && $(MAKE) clean cd ocaml && $(MAKE) clean check: make -C ocaml check make -C python check make -C java check FORCE: capstone-sys-0.15.0/capstone/bindings/README000064400000000000000000000036030072674642500166620ustar 00000000000000This directory contains bindings & test code for Python, Java & OCaml. See /README for how to compile & install each binding. More bindings created & maintained by the community are available as followings. - Gapstone: Go binding (by Scott Knight). https://github.com/knightsc/gapstone - Crabstone: Ruby binding for Capstone 3+ (by david942j). https://github.com/david942j/crabstone - Crabstone: Ruby binding (by Ben Nagy). https://github.com/bnagy/crabstone - Capstone-Vala: Vala binding (by Pancake). https://github.com/radare/capstone-vala - Node-Capstone: NodeJS binding (by Jason Oster). https://github.com/parasyte/node-capstone - CCcapstone: C++ binding (by Peter Hlavaty). https://github.com/zer0mem/cccapstone - LuaCapstone: Lua binding (by Antonio Davide). https://github.com/Dax89/LuaCapstone - Capstone-RS: Rust binding (by Richo Healey). https://github.com/capstone-rust/capstone-rs - Capstone.NET: .NET framework binding (by Ahmed Garhy). https://github.com/9ee1/Capstone.NET - CapstoneJ: High level Java wrapper for Capstone-java (by Keve Müller). https://github.com/kevemueller/capstonej - Hapstone: Haskell binding (by ibabushkin) https://github.com/ibabushkin/hapstone - CL-Capstone: Common Lisp bindings (by GrammaTech). https://github.com/GrammaTech/cl-capstone - Emacs-capstone: Emacs (elisp) binding (by Bas Alberts) https://github.com/collarchoke/emacs-capstone - C# binding (by Matt Graeber). Note: this is only for Capstone v2.0. https://github.com/mattifestation/capstone - PowerShell binding (by Ruben Boonen). https://github.com/aquynh/capstone/tree/master/bindings/powershell - PHP binding (by Fadhil Mandaga). https://github.com/firodj/php-capstone - capstone-d: D binding (by Dimitri Bohlender) https://github.com/bohlender/capstone-d - Swift binding (by Jesús A. Álvarez) https://github.com/zydeco/capstone-swift capstone-sys-0.15.0/capstone/bindings/const_generator.py000064400000000000000000000346670072674642500215660ustar 00000000000000# Capstone Disassembler Engine # By Dang Hoang Vu, 2013 from __future__ import print_function import sys, re INCL_DIR = '../include/capstone/' include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h' ] template = { 'java': { 'header': "// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT\npackage capstone;\n\npublic class %s_const {\n", 'footer': "}", 'line_format': '\tpublic static final int %s = %s;\n', 'out_file': './java/capstone/%s_const.java', # prefixes for constant filenames of all archs - case sensitive 'arm.h': 'Arm', 'arm64.h': 'Arm64', 'm68k.h': 'M68k', 'mips.h': 'Mips', 'x86.h': 'X86', 'ppc.h': 'Ppc', 'sparc.h': 'Sparc', 'systemz.h': 'Sysz', 'xcore.h': 'Xcore', 'tms320c64x.h': 'TMS320C64x', 'm680x.h': 'M680x', 'evm.h': 'Evm', 'wasm.h': 'Wasm', 'comment_open': '\t//', 'comment_close': '', }, 'python': { 'header': "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n", 'footer': "", 'line_format': '%s = %s\n', 'out_file': './python/capstone/%s_const.py', # prefixes for constant filenames of all archs - case sensitive 'arm.h': 'arm', 'arm64.h': 'arm64', 'm68k.h': 'm68k', 'mips.h': 'mips', 'x86.h': 'x86', 'ppc.h': 'ppc', 'sparc.h': 'sparc', 'systemz.h': 'sysz', 'xcore.h': 'xcore', 'tms320c64x.h': 'tms320c64x', 'm680x.h': 'm680x', 'evm.h': 'evm', 'wasm.h': 'wasm', 'mos65xx.h': 'mos65xx', 'bpf.h': 'bpf', 'riscv.h': 'riscv', 'comment_open': '#', 'comment_close': '', }, 'ocaml': { 'header': "(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.ml] *)\n", 'footer': "", 'line_format': 'let _%s = %s;;\n', 'out_file': './ocaml/%s_const.ml', # prefixes for constant filenames of all archs - case sensitive 'arm.h': 'arm', 'arm64.h': 'arm64', 'mips.h': 'mips', 'm68k.h': 'm68k', 'x86.h': 'x86', 'ppc.h': 'ppc', 'sparc.h': 'sparc', 'systemz.h': 'sysz', 'xcore.h': 'xcore', 'tms320c64x.h': 'tms320c64x', 'm680x.h': 'm680x', 'evm.h': 'evm', 'wasm.h': 'wasm', 'comment_open': '(*', 'comment_close': ' *)', }, 'swift': { 'header': "// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT (%s)\n\n", 'footer': "", 'enum_doc': '/// %s\n', 'enum_header': 'public enum %s: %s {\n', 'enum_default_type': 'UInt32', 'enum_types': { 'UInt16': r'^\w+Reg$', 'UInt8': r'^\w+Grp$' }, 'option_set_header': 'public struct %s: OptionSet {\n public typealias RawValue = %s\n public let rawValue: RawValue\n public init(rawValue: RawValue) { self.rawValue = rawValue }\n', 'option_sets': { 'X86Eflags': 'UInt64', 'X86FpuFlags': 'UInt64', 'SparcHint': 'UInt32', 'M680xIdx': 'UInt8', 'M680xOpFlags': 'UInt8', }, 'rename': { r'^M680X_(\w+_OP_IN_MNEM)$': r'M680X_OP_FLAGS_\1', }, 'option_format': ' public static let {option} = {type}(rawValue: {value})\n', 'enum_extra_options': { # swift enum != OptionSet, so options must be specified 'ArmSysreg': { 'spsrCx': 'spsrC + spsrX', 'spsrCs': 'spsrC + spsrS', 'spsrXs': 'spsrX + spsrS', 'spsrCxs': 'spsrC + spsrX + spsrS', 'spsrCf': 'spsrC + spsrF', 'spsrXf': 'spsrX + spsrF', 'spsrCxf': 'spsrC + spsrX + spsrF', 'spsrSf': 'spsrS + spsrF', 'spsrCsf': 'spsrC + spsrS + spsrF', 'spsrXsf': 'spsrX + spsrS + spsrF', 'spsrCxsf': 'spsrC + spsrX + spsrS + spsrF', 'cpsrCx': 'cpsrC + cpsrX', 'cpsrCs': 'cpsrC + cpsrS', 'cpsrXs': 'cpsrX + cpsrS', 'cpsrCxs': 'cpsrC + cpsrX + cpsrS', 'cpsrCf': 'cpsrC + cpsrF', 'cpsrXf': 'cpsrX + cpsrF', 'cpsrCxf': 'cpsrC + cpsrX + cpsrF', 'cpsrSf': 'cpsrS + cpsrF', 'cpsrCsf': 'cpsrC + cpsrS + cpsrF', 'cpsrXsf': 'cpsrX + cpsrS + cpsrF', 'cpsrCxsf': 'cpsrC + cpsrX + cpsrS + cpsrF', } }, 'enum_footer': '}\n\n', 'doc_line_format': ' /// %s\n', 'line_format': ' case %s = %s\n', 'dup_line_format': ' public static let %s = %s\n', 'out_file': './swift/Sources/Capstone/%sEnums.swift', 'reserved_words': [ 'break', 'class', 'for', 'false', 'in', 'init', 'return', 'true' ], 'reserved_word_format': '`%s`', # prefixes for constant filenames of all archs - case sensitive 'arm.h': 'Arm', 'arm64.h': 'Arm64', 'm68k.h': 'M68k', 'mips.h': 'Mips', 'x86.h': 'X86', 'ppc.h': 'Ppc', 'sparc.h': 'Sparc', 'systemz.h': 'Sysz', 'xcore.h': 'Xcore', 'tms320c64x.h': 'TMS320C64x', 'm680x.h': 'M680x', 'evm.h': 'Evm', 'mos65xx.h': 'Mos65xx', 'comment_open': '\t//', 'comment_close': '', }, } # markup for comments to be added to autogen files MARKUP = '//>' def camelize(name): parts = name.split('_') return parts[0].lower() + ''.join(map(str.capitalize, parts[1:])) def pascalize(name): parts = name.split('_') return ''.join(map(str.capitalize, parts)) def pascalize_const(name): parts = name.split('_',2) match = re.match('^(CC|DISP|MOD|DIR|BCAST|RM|FLAGS|SIZE|BR_DISP_SIZE)_', parts[2]) if match: parts = name.split('_', 2 + match.group(0).count('_')) item = camelize(parts[-1]) if item[0].isdigit(): item = parts[-2].lower() + item return (pascalize('_'.join(parts[0:-1])), item) def enum_type(name, templ): for enum_type, pattern in templ['enum_types'].items(): if re.match(pattern, name): return enum_type return templ['enum_default_type'] def write_enum_extra_options(outfile, templ, enum, enum_values): if 'enum_extra_options' in templ and enum in templ['enum_extra_options']: for name, value in templ['enum_extra_options'][enum].items(): if type(value) is str: # evaluate within existing enum value = eval(value, None, enum_values) outfile.write((templ['line_format'] %(name, value)).encode("utf-8")) def gen(lang): global include, INCL_DIR print('Generating bindings for', lang) templ = template[lang] print('Generating bindings for', lang) for target in include: if target not in templ: print("Warning: No binding found for %s" % target) continue prefix = templ[target] outfile = open(templ['out_file'] %(prefix), 'wb') # open as binary prevents windows newlines outfile.write((templ['header'] % (prefix)).encode("utf-8")) lines = open(INCL_DIR + target).readlines() enums = {} values = {} doc_lines = [] count = 0 for line in lines: line = line.strip() if line.startswith(MARKUP): # markup for comments outfile.write(("\n%s%s%s\n" %(templ['comment_open'], \ line.replace(MARKUP, ''), \ templ['comment_close']) ).encode("utf-8")) continue if line.startswith('/// ') and 'enum_doc' in templ: doc_lines.append(line[4: ]) continue elif line.startswith('}') or line.startswith('#'): doc_lines = [] pass if line == '' or line.startswith('//'): continue if line.startswith('#define '): line = line[8:] #cut off define xline = re.split('\s+', line, 1) #split to at most 2 express if len(xline) != 2: continue if '(' in xline[0] or ')' in xline[0]: #does it look like a function continue xline.insert(1, '=') # insert an = so the expression below can parse it line = ' '.join(xline) if not line.startswith(prefix.upper()): continue tmp = line.strip().split(',') for t in tmp: t = t.strip() if not t or t.startswith('//'): continue # hacky: remove type cast (uint64_t) t = t.replace('(uint64_t)', '') t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t) # (1ULL<<1) to 1 << 1 f = re.split('\s+', t) if f[0].startswith(prefix.upper()): if len(f) > 1 and f[1] not in ('//', '///<', '='): print("Error: Unable to convert %s" % f) continue elif len(f) > 1 and f[1] == '=': rhs = ''.join(f[2:]) else: rhs = str(count) count += 1 try: count = int(rhs) + 1 if (count == 1): outfile.write(("\n").encode("utf-8")) except ValueError: if lang == 'ocaml': # ocaml uses lsl for '<<', lor for '|' rhs = rhs.replace('<<', ' lsl ') rhs = rhs.replace('|', ' lor ') # ocaml variable has _ as prefix if rhs[0].isalpha(): rhs = '_' + rhs if lang == 'swift': value = eval(rhs, None, values) exec('%s = %d' %(f[0].strip(), value), None, values) else: value = rhs name = f[0].strip() if 'rename' in templ: # constant renaming for pattern, replacement in templ['rename'].items(): if re.match(pattern, name): name = re.sub(pattern, replacement, name) break if 'enum_header' in templ: # separate constants by enums based on name enum, name = pascalize_const(name) if enum not in enums: if len(enums) > 0: write_enum_extra_options(outfile, templ, last_enum, enums[last_enum]) outfile.write((templ['enum_footer']).encode("utf-8")) last_enum = enum if 'enum_doc' in templ: for doc_line in doc_lines: outfile.write((templ['enum_doc'] %(doc_line)).encode("utf-8")) doc_lines = [] if 'option_sets' in templ and enum in templ['option_sets']: outfile.write((templ['option_set_header'] %(enum, templ['option_sets'][enum])).encode("utf-8")) else: outfile.write((templ['enum_header'] %(enum, enum_type(enum, templ))).encode("utf-8")) enums[enum] = {} if 'option_sets' in templ and enum in templ['option_sets']: # option set format line_format = templ['option_format'].format(option='%s',type=enum,value='%s') if value == 0: continue # skip empty option # option set values need not be literals value = rhs elif 'dup_line_format' in templ and value in enums[enum].values(): # different format for duplicate values? line_format = templ['dup_line_format'] else: line_format = templ['line_format'] enums[enum][name] = value # escape reserved words if 'reserved_words' in templ and name in templ['reserved_words']: name = templ['reserved_word_format'] %(name) # print documentation? if 'doc_line_format' in templ and '///<' in line: doc = line.split('///<')[1].strip() outfile.write((templ['doc_line_format'] %(doc)).encode("utf-8")) else: line_format = templ['line_format'] outfile.write((line_format %(name, value)).encode("utf-8")) if 'enum_footer' in templ: write_enum_extra_options(outfile, templ, enum, enums[enum]) outfile.write((templ['enum_footer']).encode("utf-8")) outfile.write((templ['footer']).encode("utf-8")) outfile.close() def main(): try: if sys.argv[1] == 'all': for key in template.keys(): gen(key) else: gen(sys.argv[1]) except: raise RuntimeError("Unsupported binding %s" % sys.argv[1]) if __name__ == "__main__": if len(sys.argv) < 2: print("Usage:", sys.argv[0], " ") sys.exit(1) main() capstone-sys-0.15.0/capstone/bindings/java/.gitignore000064400000000000000000000000150072674642500207050ustar 00000000000000*.class tags capstone-sys-0.15.0/capstone/bindings/java/Makefile000064400000000000000000000033760072674642500203720ustar 00000000000000# Capstone Disassembler Engine # By Nguyen Anh Quynh , 2013> ifndef BUILDDIR BLDIR = . OBJDIR = . else BLDIR = $(abspath $(BUILDDIR))/bindings/java OBJDIR = $(abspath $(BUILDDIR))/obj/bindings/java endif JNA = /usr/share/java/jna/jna.jar ifneq ($(wildcard $(JNA)),) else ifneq ($(wildcard /usr/share/java/jna.jar),) JNA = /usr/share/java/jna.jar else JNA = endif endif PYTHON2 ?= python CAPSTONE_JAVA = Capstone.java Arm_const.java Arm64_const.java Mips_const.java \ X86_const.java Xcore_const.java Ppc_const.java Sparc_const.java\ Sysz_const.java M680x_const.java \ Arm.java Arm64.java Mips.java X86.java Xcore.java Ppc.java\ Sparc.java Systemz.java M680x.java all: gen_const capstone tests capstone: capstone_class @mkdir -p $(BLDIR) cd $(OBJDIR) && jar cf $(BLDIR)/capstone.jar capstone/*.class capstone_class: jna ifdef BUILDDIR @mkdir -p $(OBJDIR) cd capstone && javac -d $(OBJDIR) -classpath $(JNA) $(CAPSTONE_JAVA) else cd capstone && javac -classpath $(JNA) $(CAPSTONE_JAVA) endif tests: capstone_class jna @mkdir -p $(OBJDIR) javac -d $(OBJDIR) -classpath "$(JNA):$(BLDIR)/capstone.jar" TestBasic.java\ TestArm.java TestArm64.java TestMips.java TestX86.java TestXcore.java\ TestPpc.java TestSparc.java TestSystemz.java TestM680x.java gen_const: cd ../ && $(PYTHON2) const_generator.py java jna: @if [ ! $(JNA) ]; then echo "*** Unable to find JNA ***"; exit 1; fi clean: rm -rf $(OBJDIR)/capstone/*.class rm -rf $(OBJDIR)/*.class $(OBJDIR)/*.log $(BLDIR)/*.jar ifdef BUILDDIR rm -rf $(BLDIR) rm -rf $(OBJDIR) endif TESTS = testbasic arm arm64 m680x mips ppc sparc systemz x86 xcore check: @for t in $(TESTS); do \ echo Check $$t ... ; \ ./run.sh $$t > /dev/null && echo OK || echo FAILED; \ done capstone-sys-0.15.0/capstone/bindings/java/README000064400000000000000000000014760072674642500176110ustar 00000000000000This has been tested with OpenJDK version 6 & 7 on Ubuntu-12.04 and Arch Linux-3.11, 64-bit. - OpenJDK is required to compile and run this test code. For example, install OpenJDK 6 with: $ sudo apt-get install openjdk-6-jre-headless openjdk-6-jdk - Java Native Access is required to run the code, you can install it with: $ sudo apt-get install libjna-java - To compile and run this Java test code: $ make $ ./run.sh This directory contains some test code to show how to use Capstone API. - TestBasic.java This code shows the most simple form of API where we only want to get basic information out of disassembled instruction, such as address, mnemonic and operand string. - Test.java These code show how to retrieve architecture-specific information for each architecture. capstone-sys-0.15.0/capstone/bindings/java/TestArm.java000064400000000000000000000134300072674642500211440ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 import capstone.Capstone; import capstone.Arm; import static capstone.Arm_const.*; public class TestArm { static byte[] hexString2Byte(String s) { // from http://stackoverflow.com/questions/140131/convert-a-string-representation-of-a-hex-dump-to-a-byte-array-using-java int len = s.length(); byte[] data = new byte[len / 2]; for (int i = 0; i < len; i += 2) { data[i / 2] = (byte) ((Character.digit(s.charAt(i), 16) << 4) + Character.digit(s.charAt(i+1), 16)); } return data; } static final String ARM_CODE = "EDFFFFEB04e02de500000000e08322e5f102030e0000a0e30230c1e7000053e3000201f10540d0e8"; static final String ARM_CODE2 = "d1e800f0f02404071f3cf2c000004ff00001466c"; static final String THUMB_CODE2 = "4ff00001bde80088d1e800f018bfadbff3ff0b0c86f3008980f3008c4ffa99f6d0ffa201"; static final String THUMB_CODE = "7047eb4683b0c9681fb130bfaff32084"; public static Capstone cs; private static String hex(int i) { return Integer.toString(i, 16); } private static String hex(long i) { return Long.toString(i, 16); } public static void print_ins_detail(Capstone.CsInsn ins) { System.out.printf("0x%x:\t%s\t%s\n", ins.address, ins.mnemonic, ins.opStr); Arm.OpInfo operands = (Arm.OpInfo) ins.operands; if (operands.op.length != 0) { System.out.printf("\top_count: %d\n", operands.op.length); for (int c=0; c 0) System.out.printf("\t\t\toperands[%d].vector_index = %d\n", c, (i.vector_index)); if (i.shift.type != ARM_SFT_INVALID && i.shift.value > 0) System.out.printf("\t\t\tShift: %d = %d\n", i.shift.type, i.shift.value); if (i.subtracted) System.out.printf("\t\t\toperands[%d].subtracted = True\n", c); } } if (operands.writeback) System.out.println("\tWrite-back: True"); if (operands.updateFlags) System.out.println("\tUpdate-flags: True"); if (operands.cc != ARM_CC_AL && operands.cc != ARM_CC_INVALID) System.out.printf("\tCode condition: %d\n", operands.cc); if (operands.cpsMode > 0) System.out.printf("\tCPSI-mode: %d\n", operands.cpsMode); if (operands.cpsFlag > 0) System.out.printf("\tCPSI-flag: %d\n", operands.cpsFlag); if (operands.vectorData > 0) System.out.printf("\tVector-data: %d\n", operands.vectorData); if (operands.vectorSize > 0) System.out.printf("\tVector-size: %d\n", operands.vectorSize); if (operands.usermode) System.out.printf("\tUser-mode: True\n"); } public static void main(String argv[]) { final TestBasic.platform[] all_tests = { new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_ARM, hexString2Byte(ARM_CODE), "ARM"), new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, hexString2Byte(THUMB_CODE), "Thumb"), new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, hexString2Byte(ARM_CODE2), "Thumb-mixed"), new TestBasic.platform(Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, Capstone.CS_OPT_SYNTAX_NOREGNAME, hexString2Byte(THUMB_CODE2), "Thumb-2 & register named with numbers"), }; for (int i=0; i 0) System.out.printf("\t\t\tShift: type = %d, value = %d\n", i.shift.type, i.shift.value); if (i.ext != ARM64_EXT_INVALID) System.out.printf("\t\t\tExt: %d\n", i.ext); if (i.vas != ARM64_VAS_INVALID) System.out.printf("\t\t\tVector Arrangement Specifier: 0x%x\n", i.vas); if (i.vector_index != -1) System.out.printf("\t\t\tVector Index: %d\n", i.vector_index); } } if (operands.writeback) System.out.println("\tWrite-back: True"); if (operands.updateFlags) System.out.println("\tUpdate-flags: True"); if (operands.cc != ARM64_CC_AL && operands.cc != ARM64_CC_INVALID) System.out.printf("\tCode-condition: %d\n", operands.cc); } public static void main(String argv[]) { final TestBasic.platform[] all_tests = { new TestBasic.platform(Capstone.CS_ARCH_ARM64, Capstone.CS_MODE_ARM, hexString2Byte(ARM64_CODE), "ARM-64"), }; for (int i=0; i, 2013> */ import capstone.Capstone; public class TestBasic { public static class platform { public int arch; public int mode; public int syntax; public byte[] code; public String comment; public platform(int a, int m, int syt, byte[] c, String s) { arch = a; mode = m; code = c; comment = s; syntax = syt; } public platform(int a, int m, byte[] c, String s) { arch = a; mode = m; code = c; comment = s; } }; static public String stringToHex(byte[] code) { StringBuilder buf = new StringBuilder(200); for (byte ch: code) { if (buf.length() > 0) buf.append(' '); buf.append(String.format("0x%02x", ch)); } return buf.toString(); } public static final byte[] PPC_CODE = new byte[] {(byte)0x80, (byte)0x20, (byte)0x00, (byte)0x00, (byte)0x80, (byte)0x3f, (byte)0x00, (byte)0x00, (byte)0x10, (byte)0x43, (byte)0x23, (byte)0x0e, (byte)0xd0, (byte)0x44, (byte)0x00, (byte)0x80, (byte)0x4c, (byte)0x43, (byte)0x22, (byte)0x02, (byte)0x2d, (byte)0x03, (byte)0x00, (byte)0x80, (byte)0x7c, (byte)0x43, (byte)0x20, (byte)0x14, (byte)0x7c, (byte)0x43, (byte)0x20, (byte)0x93, (byte)0x4f, (byte)0x20, (byte)0x00, (byte)0x21, (byte)0x4c, (byte)0xc8, (byte)0x00, (byte)0x21 }; public static final byte[] X86_CODE = new byte[] { (byte)0x8d, (byte)0x4c, (byte)0x32, (byte)0x08, (byte)0x01, (byte)0xd8, (byte)0x81, (byte)0xc6, (byte)0x34, (byte)0x12, (byte)0x00, (byte)0x00 }; public static final byte[] SPARC_CODE = new byte[] { (byte)0x80, (byte)0xa0, (byte)0x40, (byte)0x02, (byte)0x85, (byte)0xc2, (byte)0x60, (byte)0x08, (byte)0x85, (byte)0xe8, (byte)0x20, (byte)0x01, (byte)0x81, (byte)0xe8, (byte)0x00, (byte)0x00, (byte)0x90, (byte)0x10, (byte)0x20, (byte)0x01, (byte)0xd5, (byte)0xf6, (byte)0x10, (byte)0x16, (byte)0x21, (byte)0x00, (byte)0x00, (byte)0x0a, (byte)0x86, (byte)0x00, (byte)0x40, (byte)0x02, (byte)0x01, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x12, (byte)0xbf, (byte)0xff, (byte)0xff, (byte)0x10, (byte)0xbf, (byte)0xff, (byte)0xff, (byte)0xa0, (byte)0x02, (byte)0x00, (byte)0x09, (byte)0x0d, (byte)0xbf, (byte)0xff, (byte)0xff, (byte)0xd4, (byte)0x20, (byte)0x60, (byte)0x00, (byte)0xd4, (byte)0x4e, (byte)0x00, (byte)0x16, (byte)0x2a, (byte)0xc2, (byte)0x80, (byte)0x03 }; public static final byte[] SYSZ_CODE = new byte[] { (byte)0xed, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x1a, (byte)0x5a, (byte)0x0f, (byte)0x1f, (byte)0xff, (byte)0xc2, (byte)0x09, (byte)0x80, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x07, (byte)0xf7, (byte)0xeb, (byte)0x2a, (byte)0xff, (byte)0xff, (byte)0x7f, (byte)0x57, (byte)0xe3, (byte)0x01, (byte)0xff, (byte)0xff, (byte)0x7f, (byte)0x57, (byte)0xeb, (byte)0x00, (byte)0xf0, (byte)0x00, (byte)0x00, (byte)0x24, (byte)0xb2, (byte)0x4f, (byte)0x00, (byte)0x78 }; public static final byte[] SPARCV9_CODE = new byte[] { (byte)0x81, (byte)0xa8, (byte)0x0a, (byte)0x24, (byte)0x89, (byte)0xa0, (byte)0x10, (byte)0x20, (byte)0x89, (byte)0xa0, (byte)0x1a, (byte)0x60, (byte)0x89, (byte)0xa0, (byte)0x00, (byte)0xe0 }; public static final byte[] XCORE_CODE = new byte[] { (byte)0xfe, (byte)0x0f, (byte)0xfe, (byte)0x17, (byte)0x13, (byte)0x17, (byte)0xc6, (byte)0xfe, (byte)0xec, (byte)0x17, (byte)0x97, (byte)0xf8, (byte)0xec, (byte)0x4f, (byte)0x1f, (byte)0xfd, (byte)0xec, (byte)0x37, (byte)0x07, (byte)0xf2, (byte)0x45, (byte)0x5b, (byte)0xf9, (byte)0xfa, (byte)0x02, (byte)0x06, (byte)0x1b, (byte)0x10 }; static public void main(String argv[]) { platform[] platforms = { new platform( Capstone.CS_ARCH_X86, Capstone.CS_MODE_16, Capstone.CS_OPT_SYNTAX_INTEL, new byte[] { (byte)0x8d, (byte)0x4c, (byte)0x32, (byte)0x08, (byte)0x01, (byte)0xd8, (byte)0x81, (byte)0xc6, (byte)0x34, (byte)0x12, (byte)0x00, (byte)0x00 }, "X86 16bit (Intel syntax)" ), new platform( Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, Capstone.CS_OPT_SYNTAX_ATT, X86_CODE, "X86 32bit (ATT syntax)" ), new platform( Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, X86_CODE, "X86 32 (Intel syntax)" ), new platform( Capstone.CS_ARCH_X86, Capstone.CS_MODE_64, new byte[] {(byte)0x55, (byte)0x48, (byte)0x8b, (byte)0x05, (byte)0xb8, (byte)0x13, (byte)0x00, (byte)0x00 }, "X86 64 (Intel syntax)" ), new platform( Capstone.CS_ARCH_ARM, Capstone.CS_MODE_ARM, new byte[] { (byte)0xED, (byte)0xFF, (byte)0xFF, (byte)0xEB, (byte)0x04, (byte)0xe0, (byte)0x2d, (byte)0xe5, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0xe0, (byte)0x83, (byte)0x22, (byte)0xe5, (byte)0xf1, (byte)0x02, (byte)0x03, (byte)0x0e, (byte)0x00, (byte)0x00, (byte)0xa0, (byte)0xe3, (byte)0x02, (byte)0x30, (byte)0xc1, (byte)0xe7, (byte)0x00, (byte)0x00, (byte)0x53, (byte)0xe3 }, "ARM" ), new platform( Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, new byte[] {(byte)0x4f, (byte)0xf0, (byte)0x00, (byte)0x01, (byte)0xbd, (byte)0xe8, (byte)0x00, (byte)0x88, (byte)0xd1, (byte)0xe8, (byte)0x00, (byte)0xf0 }, "THUMB-2" ), new platform( Capstone.CS_ARCH_ARM, Capstone.CS_MODE_ARM, new byte[] {(byte)0x10, (byte)0xf1, (byte)0x10, (byte)0xe7, (byte)0x11, (byte)0xf2, (byte)0x31, (byte)0xe7, (byte)0xdc, (byte)0xa1, (byte)0x2e, (byte)0xf3, (byte)0xe8, (byte)0x4e, (byte)0x62, (byte)0xf3 }, "ARM: Cortex-A15 + NEON" ), new platform( Capstone.CS_ARCH_ARM, Capstone.CS_MODE_THUMB, new byte[] {(byte)0x70, (byte)0x47, (byte)0xeb, (byte)0x46, (byte)0x83, (byte)0xb0, (byte)0xc9, (byte)0x68 }, "THUMB" ), new platform( Capstone.CS_ARCH_MIPS, Capstone.CS_MODE_MIPS32 + Capstone.CS_MODE_BIG_ENDIAN, new byte[] {(byte)0x0C, (byte)0x10, (byte)0x00, (byte)0x97, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x00, (byte)0x24, (byte)0x02, (byte)0x00, (byte)0x0c, (byte)0x8f, (byte)0xa2, (byte)0x00, (byte)0x00, (byte)0x34, (byte)0x21, (byte)0x34, (byte)0x56 }, "MIPS-32 (Big-endian)" ), new platform( Capstone.CS_ARCH_MIPS, Capstone.CS_MODE_MIPS64+ Capstone.CS_MODE_LITTLE_ENDIAN, new byte[] {(byte)0x56, (byte)0x34, (byte)0x21, (byte)0x34, (byte)0xc2, (byte)0x17, (byte)0x01, (byte)0x00 }, "MIPS-64-EL (Little-endian)" ), new platform( Capstone.CS_ARCH_ARM64, Capstone.CS_MODE_ARM, new byte [] { 0x21, 0x7c, 0x02, (byte)0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, (byte)0xe1, 0x0b, 0x40, (byte)0xb9 }, "ARM-64" ), new platform ( Capstone.CS_ARCH_PPC, Capstone.CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64" ), new platform ( Capstone.CS_ARCH_PPC, Capstone.CS_MODE_BIG_ENDIAN, Capstone.CS_OPT_SYNTAX_NOREGNAME, PPC_CODE, "PPC-64, print register with number only" ), new platform ( Capstone.CS_ARCH_SPARC, Capstone.CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc" ), new platform ( Capstone.CS_ARCH_SPARC, Capstone.CS_MODE_BIG_ENDIAN + Capstone.CS_MODE_V9, SPARCV9_CODE, "SparcV9" ), new platform ( Capstone.CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ" ), new platform ( Capstone.CS_ARCH_XCORE, 0, XCORE_CODE, "XCore" ), }; for (int j = 0; j < platforms.length; j++) { System.out.println("****************"); System.out.println(String.format("Platform: %s", platforms[j].comment)); System.out.println(String.format("Code: %s", stringToHex(platforms[j].code))); System.out.println("Disasm:"); Capstone cs = new Capstone(platforms[j].arch, platforms[j].mode); if (platforms[j].syntax != 0) cs.setSyntax(platforms[j].syntax); Capstone.CsInsn[] all_insn = cs.disasm(platforms[j].code, 0x1000); for (int i = 0; i < all_insn.length; i++) { System.out.println(String.format("0x%x: \t%s\t%s", all_insn[i].address, all_insn[i].mnemonic, all_insn[i].opStr)); } System.out.printf("0x%x:\n\n", all_insn[all_insn.length-1].address + all_insn[all_insn.length-1].size); // Close when done cs.close(); } } } capstone-sys-0.15.0/capstone/bindings/java/TestM680x.java000064400000000000000000000211670072674642500212550ustar 00000000000000// Capstone Java binding /* M680X Backend by Wolfgang Schwotzer 2017 */ import java.lang.*; import capstone.Capstone; import capstone.M680x; import static capstone.M680x_const.*; public class TestM680x { static final String sAccess[] = { "UNCHANGED", "READ", "WRITE", "READ | WRITE", }; static final String M6800_CODE = "010936647f7410009010A410b6100039"; static final String M6801_CODE = "04053c3d389310ec10ed1039"; static final String M6805_CODE = "047f00172228002e0040425a708e979ca015ad00c31000da1234e57ffe"; static final String M6808_CODE = "31220035224510004b005110525e226265123472848586878a8b8c9495a710af109e607f9e6b7f009ed610009ee67f"; static final String HD6301_CODE = "6b100071100072101039"; static final String M6809_CODE = "0610191a551e0123e931063455a681a7897fffa69d1000a791a69f100011ac99100039A607A627A647A667A60FA610A680A681A682A683A684A685A686A6887FA68880A6897FFFA6898000A68BA68C10A68D1000A691A693A694A695A696A6987FA69880A6997FFFA6998000A69BA69C10A69D1000A69F1000"; static final String M6811_CODE = "0203127f100013990800147f02157f011e7f20008fcf18081830183c1867188c1000188f18ce100018ff10001aa37f1aac1aee7f1aef7fcdac7f"; static final String CPU12_CODE = "000401000c00800e008000111e100080003b4a1000044b01044f7f80008f1000b752b7b1a667a6fea6f71802e23039e21000180c30391000181118121000181900181e00183e183f00"; static final String HD6309_CODE = "0110106210107b101000cd499602d21030231038103b1053105d1130431011372510113812113923113b34118e100011af1011ab1011f68000"; static final String HCS08_CODE = "3210009eae9ece7f9ebe10009efe7f3e10009ef37f9610009eff7f82"; static byte[] hexString2Byte(String s) { // from http://stackoverflow.com/questions/140131/convert-a-string-representation-of-a-hex-dump-to-a-byte-array-using-java int len = s.length(); byte[] data = new byte[len / 2]; for (int i = 0; i < len; i += 2) { data[i / 2] = (byte) ((Character.digit(s.charAt(i), 16) << 4) + Character.digit(s.charAt(i+1), 16)); } return data; } static public String stringToHexUc(byte[] code) { StringBuilder buf = new StringBuilder(800); for (byte ch: code) { buf.append(String.format(" 0x%02x", ch)); } return buf.toString(); } static public String stringToHexShortUc(byte[] code) { StringBuilder buf = new StringBuilder(800); for (byte ch: code) { buf.append(String.format("%02x", ch)); } return buf.toString(); } public static Capstone cs; /* private static String hex(int i) { return Integer.toString(i, 16); } private static String hex(long i) { return Long.toString(i, 16); } */ public static void print_ins_detail(Capstone.CsInsn ins) { String bytes = stringToHexShortUc(ins.bytes); System.out.printf("0x%04x:\t%s\t%s\t%s\n", ins.address, bytes, ins.mnemonic, ins.opStr); M680x.OpInfo operands = (M680x.OpInfo) ins.operands; if (operands.op.length != 0) { System.out.printf("\top_count: %d\n", operands.op.length); for (int c = 0; c < operands.op.length; c++) { M680x.Operand i = (M680x.Operand) operands.op[c]; if (i.type == M680X_OP_REGISTER) { String comment = ""; if ((c == 0 && ((operands.flags & M680X_FIRST_OP_IN_MNEM) != 0)) || (c == 1 && ((operands.flags & M680X_SECOND_OP_IN_MNEM) != 0))) comment = " (in mnemonic)"; System.out.printf("\t\toperands[%d].type: REGISTER = %s%s\n", c, ins.regName(i.value.reg), comment); } if (i.type == M680X_OP_CONSTANT) System.out.printf("\t\toperands[%d].type: CONSTANT = %d\n", c, i.value.const_val); if (i.type == M680X_OP_IMMEDIATE) System.out.printf("\t\toperands[%d].type: IMMEDIATE = #%d\n", c, i.value.imm); if (i.type == M680X_OP_DIRECT) System.out.printf("\t\toperands[%d].type: DIRECT = 0x%02x\n", c, i.value.direct_addr); if (i.type == M680X_OP_EXTENDED) System.out.printf("\t\toperands[%d].type: EXTENDED %s = 0x%04x\n", c, i.value.ext.indirect != 0 ? "INDIRECT" : "", i.value.ext.address); if (i.type == M680X_OP_RELATIVE) System.out.printf("\t\toperands[%d].type: RELATIVE = 0x%04x\n", c, i.value.rel.address ); if (i.type == M680X_OP_INDEXED) { System.out.printf("\t\toperands[%d].type: INDEXED%s\n", c, (i.value.idx.flags & M680X_IDX_INDIRECT) != 0 ? " INDIRECT" : ""); if (i.value.idx.base_reg != M680X_REG_INVALID) { String regName = ins.regName(i.value.idx.base_reg); if (regName != null) System.out.printf("\t\t\tbase register: %s\n", regName); } if (i.value.idx.offset_reg != M680X_REG_INVALID) { String regName = ins.regName(i.value.idx.offset_reg); if (regName != null) System.out.printf("\t\t\toffset register: %s\n", regName); } if ((i.value.idx.offset_bits != 0) && (i.value.idx.offset_reg == M680X_REG_INVALID) && (i.value.idx.inc_dec == 0)) { System.out.printf("\t\t\toffset: %d\n", i.value.idx.offset); if (i.value.idx.base_reg == M680X_REG_PC) System.out.printf("\t\t\toffset address: 0x%04x\n", i.value.idx.offset_addr); System.out.printf("\t\t\toffset bits: %d\n", i.value.idx.offset_bits); } if (i.value.idx.inc_dec != 0) { String post_pre = (i.value.idx.flags & M680X_IDX_POST_INC_DEC) != 0 ? "post" : "pre"; String inc_dec = i.value.idx.inc_dec > 0 ? "increment" : "decrement"; System.out.printf("\t\t\t%s %s: %d\n", post_pre, inc_dec, Math.abs(i.value.idx.inc_dec)); } } if (i.size != 0) System.out.printf("\t\t\tsize: %d\n", i.size); if (i.access != Capstone.CS_AC_INVALID) System.out.printf("\t\t\taccess: %s\n", sAccess[i.access]); } } if (ins.regsRead.length > 0) { System.out.printf("\tRegisters read:"); for (int c = 0; c < ins.regsRead.length; c++) { System.out.printf(" %s", ins.regName(ins.regsRead[c])); } System.out.printf("\n"); } if (ins.regsWrite.length > 0) { System.out.printf("\tRegisters modified:"); for (int c = 0; c < ins.regsWrite.length; c++) { System.out.printf(" %s", ins.regName(ins.regsWrite[c])); } System.out.printf("\n"); } if (ins.groups.length > 0) System.out.printf("\tgroups_count: %d\n", ins.groups.length); } public static void main(String argv[]) { final TestBasic.platform[] all_tests = { new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6301, hexString2Byte(HD6301_CODE), "M680X_HD6301"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6309, hexString2Byte(HD6309_CODE), "M680X_HD6309"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6800, hexString2Byte(M6800_CODE), "M680X_M6800"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6801, hexString2Byte(M6801_CODE), "M680X_M6801"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6805, hexString2Byte(M6805_CODE), "M680X_M68HC05"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6808, hexString2Byte(M6808_CODE), "M680X_M68HC08"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6809, hexString2Byte(M6809_CODE), "M680X_M6809"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_6811, hexString2Byte(M6811_CODE), "M680X_M68HC11"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_CPU12, hexString2Byte(CPU12_CODE), "M680X_CPU12"), new TestBasic.platform(Capstone.CS_ARCH_M680X, Capstone.CS_MODE_M680X_HCS08, hexString2Byte(HCS08_CODE), "M680X_HCS08"), }; for (int i=0; i 0) { System.out.printf("\timm_count: %d\n", count); System.out.printf("\timm offset: 0x%x\n", operands.encoding.immOffset); System.out.printf("\timm size: 0x%x\n", operands.encoding.immSize); for (int i=0; i 0) { System.out.printf("\tRegisters read:"); for (int i = 0; i < regsRead.length; i++) { System.out.printf(" %s", ins.regName(regsRead[i])); } System.out.print("\n"); } if (regsWrite.length > 0) { System.out.printf("\tRegister modified:"); for (int i = 0; i < regsWrite.length; i++) { System.out.printf(" %s", ins.regName(regsWrite[i])); } System.out.print("\n"); } } } } public static void main(String argv[]) { final TestBasic.platform[] all_tests = { new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_16, hexString2Byte(X86_CODE16), "X86 16bit (Intel syntax)"), new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, Capstone.CS_OPT_SYNTAX_ATT, hexString2Byte(X86_CODE32), "X86 32 (AT&T syntax)"), new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, hexString2Byte(X86_CODE32), "X86 32 (Intel syntax)"), new TestBasic.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_64, hexString2Byte(X86_CODE64), "X86 64 (Intel syntax)"), }; for (int i=0; i 0); writeback = (op_info.writeback > 0); memBarrier = op_info.mem_barrier; op = op_info.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/Arm64.java000064400000000000000000000057560072674642500223060ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.Arm64_const.*; public class Arm64 { public static class MemType extends Structure { public int base; public int index; public int disp; @Override public List getFieldOrder() { return Arrays.asList("base", "index", "disp"); } } public static class OpValue extends Union { public int reg; public long imm; public double fp; public MemType mem; public int pstate; public int sys; public int prefetch; public int barrier; @Override public List getFieldOrder() { return Arrays.asList("reg", "imm", "fp", "mem", "pstate", "sys", "prefetch", "barrier"); } } public static class OpShift extends Structure { public int type; public int value; @Override public List getFieldOrder() { return Arrays.asList("type","value"); } } public static class Operand extends Structure { public int vector_index; public int vas; public OpShift shift; public int ext; public int type; public OpValue value; public void read() { readField("type"); if (type == ARM64_OP_MEM) value.setType(MemType.class); if (type == ARM64_OP_FP) value.setType(Double.TYPE); if (type == ARM64_OP_IMM || type == ARM64_OP_CIMM || type == ARM64_OP_REG || type == ARM64_OP_REG_MRS || type == ARM64_OP_REG_MSR || type == ARM64_OP_PSTATE || type == ARM64_OP_SYS || type == ARM64_OP_PREFETCH || type == ARM64_OP_BARRIER) value.setType(Integer.TYPE); if (type == ARM64_OP_INVALID) return; readField("value"); readField("ext"); readField("shift"); readField("vas"); readField("vector_index"); } @Override public List getFieldOrder() { return Arrays.asList("vector_index", "vas", "shift", "ext", "type", "value"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public int cc; public byte _update_flags; public byte _writeback; public byte op_count; public Operand [] op; public UnionOpInfo() { op = new Operand[8]; } public void read() { readField("cc"); readField("_update_flags"); readField("_writeback"); readField("op_count"); op = new Operand[op_count]; if (op_count != 0) readField("op"); } @Override public List getFieldOrder() { return Arrays.asList("cc", "_update_flags", "_writeback", "op_count", "op"); } } public static class OpInfo extends Capstone.OpInfo { public int cc; public boolean updateFlags; public boolean writeback; public Operand [] op = null; public OpInfo(UnionOpInfo op_info) { cc = op_info.cc; updateFlags = (op_info._update_flags > 0); writeback = (op_info._writeback > 0); op = op_info.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/Arm64_const.java000064400000000000000000003416320072674642500235100ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Arm64_const { public static final int ARM64_SFT_INVALID = 0; public static final int ARM64_SFT_LSL = 1; public static final int ARM64_SFT_MSL = 2; public static final int ARM64_SFT_LSR = 3; public static final int ARM64_SFT_ASR = 4; public static final int ARM64_SFT_ROR = 5; public static final int ARM64_EXT_INVALID = 0; public static final int ARM64_EXT_UXTB = 1; public static final int ARM64_EXT_UXTH = 2; public static final int ARM64_EXT_UXTW = 3; public static final int ARM64_EXT_UXTX = 4; public static final int ARM64_EXT_SXTB = 5; public static final int ARM64_EXT_SXTH = 6; public static final int ARM64_EXT_SXTW = 7; public static final int ARM64_EXT_SXTX = 8; public static final int ARM64_CC_INVALID = 0; public static final int ARM64_CC_EQ = 1; public static final int ARM64_CC_NE = 2; public static final int ARM64_CC_HS = 3; public static final int ARM64_CC_LO = 4; public static final int ARM64_CC_MI = 5; public static final int ARM64_CC_PL = 6; public static final int ARM64_CC_VS = 7; public static final int ARM64_CC_VC = 8; public static final int ARM64_CC_HI = 9; public static final int ARM64_CC_LS = 10; public static final int ARM64_CC_GE = 11; public static final int ARM64_CC_LT = 12; public static final int ARM64_CC_GT = 13; public static final int ARM64_CC_LE = 14; public static final int ARM64_CC_AL = 15; public static final int ARM64_CC_NV = 16; public static final int ARM64_SYSREG_INVALID = 0; public static final int ARM64_SYSREG_MDCCSR_EL0 = 0x9808; public static final int ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828; public static final int ARM64_SYSREG_MDRAR_EL1 = 0x8080; public static final int ARM64_SYSREG_OSLSR_EL1 = 0x808C; public static final int ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6; public static final int ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6; public static final int ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7; public static final int ARM64_SYSREG_MIDR_EL1 = 0xC000; public static final int ARM64_SYSREG_CCSIDR_EL1 = 0xC800; public static final int ARM64_SYSREG_CCSIDR2_EL1 = 0xC802; public static final int ARM64_SYSREG_CLIDR_EL1 = 0xC801; public static final int ARM64_SYSREG_CTR_EL0 = 0xD801; public static final int ARM64_SYSREG_MPIDR_EL1 = 0xC005; public static final int ARM64_SYSREG_REVIDR_EL1 = 0xC006; public static final int ARM64_SYSREG_AIDR_EL1 = 0xC807; public static final int ARM64_SYSREG_DCZID_EL0 = 0xD807; public static final int ARM64_SYSREG_ID_PFR0_EL1 = 0xC008; public static final int ARM64_SYSREG_ID_PFR1_EL1 = 0xC009; public static final int ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A; public static final int ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B; public static final int ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C; public static final int ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D; public static final int ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E; public static final int ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F; public static final int ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010; public static final int ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011; public static final int ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012; public static final int ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013; public static final int ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014; public static final int ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015; public static final int ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017; public static final int ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020; public static final int ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021; public static final int ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028; public static final int ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029; public static final int ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C; public static final int ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D; public static final int ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030; public static final int ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031; public static final int ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038; public static final int ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039; public static final int ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A; public static final int ARM64_SYSREG_MVFR0_EL1 = 0xC018; public static final int ARM64_SYSREG_MVFR1_EL1 = 0xC019; public static final int ARM64_SYSREG_MVFR2_EL1 = 0xC01A; public static final int ARM64_SYSREG_RVBAR_EL1 = 0xC601; public static final int ARM64_SYSREG_RVBAR_EL2 = 0xE601; public static final int ARM64_SYSREG_RVBAR_EL3 = 0xF601; public static final int ARM64_SYSREG_ISR_EL1 = 0xC608; public static final int ARM64_SYSREG_CNTPCT_EL0 = 0xDF01; public static final int ARM64_SYSREG_CNTVCT_EL0 = 0xDF02; public static final int ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016; public static final int ARM64_SYSREG_TRCSTATR = 0x8818; public static final int ARM64_SYSREG_TRCIDR8 = 0x8806; public static final int ARM64_SYSREG_TRCIDR9 = 0x880E; public static final int ARM64_SYSREG_TRCIDR10 = 0x8816; public static final int ARM64_SYSREG_TRCIDR11 = 0x881E; public static final int ARM64_SYSREG_TRCIDR12 = 0x8826; public static final int ARM64_SYSREG_TRCIDR13 = 0x882E; public static final int ARM64_SYSREG_TRCIDR0 = 0x8847; public static final int ARM64_SYSREG_TRCIDR1 = 0x884F; public static final int ARM64_SYSREG_TRCIDR2 = 0x8857; public static final int ARM64_SYSREG_TRCIDR3 = 0x885F; public static final int ARM64_SYSREG_TRCIDR4 = 0x8867; public static final int ARM64_SYSREG_TRCIDR5 = 0x886F; public static final int ARM64_SYSREG_TRCIDR6 = 0x8877; public static final int ARM64_SYSREG_TRCIDR7 = 0x887F; public static final int ARM64_SYSREG_TRCOSLSR = 0x888C; public static final int ARM64_SYSREG_TRCPDSR = 0x88AC; public static final int ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6; public static final int ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE; public static final int ARM64_SYSREG_TRCLSR = 0x8BEE; public static final int ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6; public static final int ARM64_SYSREG_TRCDEVARCH = 0x8BFE; public static final int ARM64_SYSREG_TRCDEVID = 0x8B97; public static final int ARM64_SYSREG_TRCDEVTYPE = 0x8B9F; public static final int ARM64_SYSREG_TRCPIDR4 = 0x8BA7; public static final int ARM64_SYSREG_TRCPIDR5 = 0x8BAF; public static final int ARM64_SYSREG_TRCPIDR6 = 0x8BB7; public static final int ARM64_SYSREG_TRCPIDR7 = 0x8BBF; public static final int ARM64_SYSREG_TRCPIDR0 = 0x8BC7; public static final int ARM64_SYSREG_TRCPIDR1 = 0x8BCF; public static final int ARM64_SYSREG_TRCPIDR2 = 0x8BD7; public static final int ARM64_SYSREG_TRCPIDR3 = 0x8BDF; public static final int ARM64_SYSREG_TRCCIDR0 = 0x8BE7; public static final int ARM64_SYSREG_TRCCIDR1 = 0x8BEF; public static final int ARM64_SYSREG_TRCCIDR2 = 0x8BF7; public static final int ARM64_SYSREG_TRCCIDR3 = 0x8BFF; public static final int ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660; public static final int ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640; public static final int ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662; public static final int ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642; public static final int ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B; public static final int ARM64_SYSREG_ICH_VTR_EL2 = 0xE659; public static final int ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B; public static final int ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D; public static final int ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024; public static final int ARM64_SYSREG_LORID_EL1 = 0xC527; public static final int ARM64_SYSREG_ERRIDR_EL1 = 0xC298; public static final int ARM64_SYSREG_ERXFR_EL1 = 0xC2A0; public static final int ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828; public static final int ARM64_SYSREG_OSLAR_EL1 = 0x8084; public static final int ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4; public static final int ARM64_SYSREG_TRCOSLAR = 0x8884; public static final int ARM64_SYSREG_TRCLAR = 0x8BE6; public static final int ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661; public static final int ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641; public static final int ARM64_SYSREG_ICC_DIR_EL1 = 0xC659; public static final int ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D; public static final int ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E; public static final int ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F; public static final int ARM64_SYSREG_OSDTRRX_EL1 = 0x8002; public static final int ARM64_SYSREG_OSDTRTX_EL1 = 0x801A; public static final int ARM64_SYSREG_TEECR32_EL1 = 0x9000; public static final int ARM64_SYSREG_MDCCINT_EL1 = 0x8010; public static final int ARM64_SYSREG_MDSCR_EL1 = 0x8012; public static final int ARM64_SYSREG_DBGDTR_EL0 = 0x9820; public static final int ARM64_SYSREG_OSECCR_EL1 = 0x8032; public static final int ARM64_SYSREG_DBGVCR32_EL2 = 0xA038; public static final int ARM64_SYSREG_DBGBVR0_EL1 = 0x8004; public static final int ARM64_SYSREG_DBGBVR1_EL1 = 0x800C; public static final int ARM64_SYSREG_DBGBVR2_EL1 = 0x8014; public static final int ARM64_SYSREG_DBGBVR3_EL1 = 0x801C; public static final int ARM64_SYSREG_DBGBVR4_EL1 = 0x8024; public static final int ARM64_SYSREG_DBGBVR5_EL1 = 0x802C; public static final int ARM64_SYSREG_DBGBVR6_EL1 = 0x8034; public static final int ARM64_SYSREG_DBGBVR7_EL1 = 0x803C; public static final int ARM64_SYSREG_DBGBVR8_EL1 = 0x8044; public static final int ARM64_SYSREG_DBGBVR9_EL1 = 0x804C; public static final int ARM64_SYSREG_DBGBVR10_EL1 = 0x8054; public static final int ARM64_SYSREG_DBGBVR11_EL1 = 0x805C; public static final int ARM64_SYSREG_DBGBVR12_EL1 = 0x8064; public static final int ARM64_SYSREG_DBGBVR13_EL1 = 0x806C; public static final int ARM64_SYSREG_DBGBVR14_EL1 = 0x8074; public static final int ARM64_SYSREG_DBGBVR15_EL1 = 0x807C; public static final int ARM64_SYSREG_DBGBCR0_EL1 = 0x8005; public static final int ARM64_SYSREG_DBGBCR1_EL1 = 0x800D; public static final int ARM64_SYSREG_DBGBCR2_EL1 = 0x8015; public static final int ARM64_SYSREG_DBGBCR3_EL1 = 0x801D; public static final int ARM64_SYSREG_DBGBCR4_EL1 = 0x8025; public static final int ARM64_SYSREG_DBGBCR5_EL1 = 0x802D; public static final int ARM64_SYSREG_DBGBCR6_EL1 = 0x8035; public static final int ARM64_SYSREG_DBGBCR7_EL1 = 0x803D; public static final int ARM64_SYSREG_DBGBCR8_EL1 = 0x8045; public static final int ARM64_SYSREG_DBGBCR9_EL1 = 0x804D; public static final int ARM64_SYSREG_DBGBCR10_EL1 = 0x8055; public static final int ARM64_SYSREG_DBGBCR11_EL1 = 0x805D; public static final int ARM64_SYSREG_DBGBCR12_EL1 = 0x8065; public static final int ARM64_SYSREG_DBGBCR13_EL1 = 0x806D; public static final int ARM64_SYSREG_DBGBCR14_EL1 = 0x8075; public static final int ARM64_SYSREG_DBGBCR15_EL1 = 0x807D; public static final int ARM64_SYSREG_DBGWVR0_EL1 = 0x8006; public static final int ARM64_SYSREG_DBGWVR1_EL1 = 0x800E; public static final int ARM64_SYSREG_DBGWVR2_EL1 = 0x8016; public static final int ARM64_SYSREG_DBGWVR3_EL1 = 0x801E; public static final int ARM64_SYSREG_DBGWVR4_EL1 = 0x8026; public static final int ARM64_SYSREG_DBGWVR5_EL1 = 0x802E; public static final int ARM64_SYSREG_DBGWVR6_EL1 = 0x8036; public static final int ARM64_SYSREG_DBGWVR7_EL1 = 0x803E; public static final int ARM64_SYSREG_DBGWVR8_EL1 = 0x8046; public static final int ARM64_SYSREG_DBGWVR9_EL1 = 0x804E; public static final int ARM64_SYSREG_DBGWVR10_EL1 = 0x8056; public static final int ARM64_SYSREG_DBGWVR11_EL1 = 0x805E; public static final int ARM64_SYSREG_DBGWVR12_EL1 = 0x8066; public static final int ARM64_SYSREG_DBGWVR13_EL1 = 0x806E; public static final int ARM64_SYSREG_DBGWVR14_EL1 = 0x8076; public static final int ARM64_SYSREG_DBGWVR15_EL1 = 0x807E; public static final int ARM64_SYSREG_DBGWCR0_EL1 = 0x8007; public static final int ARM64_SYSREG_DBGWCR1_EL1 = 0x800F; public static final int ARM64_SYSREG_DBGWCR2_EL1 = 0x8017; public static final int ARM64_SYSREG_DBGWCR3_EL1 = 0x801F; public static final int ARM64_SYSREG_DBGWCR4_EL1 = 0x8027; public static final int ARM64_SYSREG_DBGWCR5_EL1 = 0x802F; public static final int ARM64_SYSREG_DBGWCR6_EL1 = 0x8037; public static final int ARM64_SYSREG_DBGWCR7_EL1 = 0x803F; public static final int ARM64_SYSREG_DBGWCR8_EL1 = 0x8047; public static final int ARM64_SYSREG_DBGWCR9_EL1 = 0x804F; public static final int ARM64_SYSREG_DBGWCR10_EL1 = 0x8057; public static final int ARM64_SYSREG_DBGWCR11_EL1 = 0x805F; public static final int ARM64_SYSREG_DBGWCR12_EL1 = 0x8067; public static final int ARM64_SYSREG_DBGWCR13_EL1 = 0x806F; public static final int ARM64_SYSREG_DBGWCR14_EL1 = 0x8077; public static final int ARM64_SYSREG_DBGWCR15_EL1 = 0x807F; public static final int ARM64_SYSREG_TEEHBR32_EL1 = 0x9080; public static final int ARM64_SYSREG_OSDLR_EL1 = 0x809C; public static final int ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4; public static final int ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6; public static final int ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE; public static final int ARM64_SYSREG_CSSELR_EL1 = 0xD000; public static final int ARM64_SYSREG_VPIDR_EL2 = 0xE000; public static final int ARM64_SYSREG_VMPIDR_EL2 = 0xE005; public static final int ARM64_SYSREG_CPACR_EL1 = 0xC082; public static final int ARM64_SYSREG_SCTLR_EL1 = 0xC080; public static final int ARM64_SYSREG_SCTLR_EL2 = 0xE080; public static final int ARM64_SYSREG_SCTLR_EL3 = 0xF080; public static final int ARM64_SYSREG_ACTLR_EL1 = 0xC081; public static final int ARM64_SYSREG_ACTLR_EL2 = 0xE081; public static final int ARM64_SYSREG_ACTLR_EL3 = 0xF081; public static final int ARM64_SYSREG_HCR_EL2 = 0xE088; public static final int ARM64_SYSREG_SCR_EL3 = 0xF088; public static final int ARM64_SYSREG_MDCR_EL2 = 0xE089; public static final int ARM64_SYSREG_SDER32_EL3 = 0xF089; public static final int ARM64_SYSREG_CPTR_EL2 = 0xE08A; public static final int ARM64_SYSREG_CPTR_EL3 = 0xF08A; public static final int ARM64_SYSREG_HSTR_EL2 = 0xE08B; public static final int ARM64_SYSREG_HACR_EL2 = 0xE08F; public static final int ARM64_SYSREG_MDCR_EL3 = 0xF099; public static final int ARM64_SYSREG_TTBR0_EL1 = 0xC100; public static final int ARM64_SYSREG_TTBR0_EL2 = 0xE100; public static final int ARM64_SYSREG_TTBR0_EL3 = 0xF100; public static final int ARM64_SYSREG_TTBR1_EL1 = 0xC101; public static final int ARM64_SYSREG_TCR_EL1 = 0xC102; public static final int ARM64_SYSREG_TCR_EL2 = 0xE102; public static final int ARM64_SYSREG_TCR_EL3 = 0xF102; public static final int ARM64_SYSREG_VTTBR_EL2 = 0xE108; public static final int ARM64_SYSREG_VTCR_EL2 = 0xE10A; public static final int ARM64_SYSREG_DACR32_EL2 = 0xE180; public static final int ARM64_SYSREG_SPSR_EL1 = 0xC200; public static final int ARM64_SYSREG_SPSR_EL2 = 0xE200; public static final int ARM64_SYSREG_SPSR_EL3 = 0xF200; public static final int ARM64_SYSREG_ELR_EL1 = 0xC201; public static final int ARM64_SYSREG_ELR_EL2 = 0xE201; public static final int ARM64_SYSREG_ELR_EL3 = 0xF201; public static final int ARM64_SYSREG_SP_EL0 = 0xC208; public static final int ARM64_SYSREG_SP_EL1 = 0xE208; public static final int ARM64_SYSREG_SP_EL2 = 0xF208; public static final int ARM64_SYSREG_SPSEL = 0xC210; public static final int ARM64_SYSREG_NZCV = 0xDA10; public static final int ARM64_SYSREG_DAIF = 0xDA11; public static final int ARM64_SYSREG_CURRENTEL = 0xC212; public static final int ARM64_SYSREG_SPSR_IRQ = 0xE218; public static final int ARM64_SYSREG_SPSR_ABT = 0xE219; public static final int ARM64_SYSREG_SPSR_UND = 0xE21A; public static final int ARM64_SYSREG_SPSR_FIQ = 0xE21B; public static final int ARM64_SYSREG_FPCR = 0xDA20; public static final int ARM64_SYSREG_FPSR = 0xDA21; public static final int ARM64_SYSREG_DSPSR_EL0 = 0xDA28; public static final int ARM64_SYSREG_DLR_EL0 = 0xDA29; public static final int ARM64_SYSREG_IFSR32_EL2 = 0xE281; public static final int ARM64_SYSREG_AFSR0_EL1 = 0xC288; public static final int ARM64_SYSREG_AFSR0_EL2 = 0xE288; public static final int ARM64_SYSREG_AFSR0_EL3 = 0xF288; public static final int ARM64_SYSREG_AFSR1_EL1 = 0xC289; public static final int ARM64_SYSREG_AFSR1_EL2 = 0xE289; public static final int ARM64_SYSREG_AFSR1_EL3 = 0xF289; public static final int ARM64_SYSREG_ESR_EL1 = 0xC290; public static final int ARM64_SYSREG_ESR_EL2 = 0xE290; public static final int ARM64_SYSREG_ESR_EL3 = 0xF290; public static final int ARM64_SYSREG_FPEXC32_EL2 = 0xE298; public static final int ARM64_SYSREG_FAR_EL1 = 0xC300; public static final int ARM64_SYSREG_FAR_EL2 = 0xE300; public static final int ARM64_SYSREG_FAR_EL3 = 0xF300; public static final int ARM64_SYSREG_HPFAR_EL2 = 0xE304; public static final int ARM64_SYSREG_PAR_EL1 = 0xC3A0; public static final int ARM64_SYSREG_PMCR_EL0 = 0xDCE0; public static final int ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1; public static final int ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2; public static final int ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3; public static final int ARM64_SYSREG_PMSELR_EL0 = 0xDCE5; public static final int ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8; public static final int ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9; public static final int ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA; public static final int ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0; public static final int ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1; public static final int ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2; public static final int ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3; public static final int ARM64_SYSREG_MAIR_EL1 = 0xC510; public static final int ARM64_SYSREG_MAIR_EL2 = 0xE510; public static final int ARM64_SYSREG_MAIR_EL3 = 0xF510; public static final int ARM64_SYSREG_AMAIR_EL1 = 0xC518; public static final int ARM64_SYSREG_AMAIR_EL2 = 0xE518; public static final int ARM64_SYSREG_AMAIR_EL3 = 0xF518; public static final int ARM64_SYSREG_VBAR_EL1 = 0xC600; public static final int ARM64_SYSREG_VBAR_EL2 = 0xE600; public static final int ARM64_SYSREG_VBAR_EL3 = 0xF600; public static final int ARM64_SYSREG_RMR_EL1 = 0xC602; public static final int ARM64_SYSREG_RMR_EL2 = 0xE602; public static final int ARM64_SYSREG_RMR_EL3 = 0xF602; public static final int ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681; public static final int ARM64_SYSREG_TPIDR_EL0 = 0xDE82; public static final int ARM64_SYSREG_TPIDR_EL2 = 0xE682; public static final int ARM64_SYSREG_TPIDR_EL3 = 0xF682; public static final int ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83; public static final int ARM64_SYSREG_TPIDR_EL1 = 0xC684; public static final int ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00; public static final int ARM64_SYSREG_CNTVOFF_EL2 = 0xE703; public static final int ARM64_SYSREG_CNTKCTL_EL1 = 0xC708; public static final int ARM64_SYSREG_CNTHCTL_EL2 = 0xE708; public static final int ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10; public static final int ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710; public static final int ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10; public static final int ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11; public static final int ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711; public static final int ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11; public static final int ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12; public static final int ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712; public static final int ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12; public static final int ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18; public static final int ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19; public static final int ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A; public static final int ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40; public static final int ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41; public static final int ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42; public static final int ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43; public static final int ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44; public static final int ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45; public static final int ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46; public static final int ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47; public static final int ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48; public static final int ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49; public static final int ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A; public static final int ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B; public static final int ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C; public static final int ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D; public static final int ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E; public static final int ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F; public static final int ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50; public static final int ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51; public static final int ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52; public static final int ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53; public static final int ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54; public static final int ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55; public static final int ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56; public static final int ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57; public static final int ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58; public static final int ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59; public static final int ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A; public static final int ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B; public static final int ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C; public static final int ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D; public static final int ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E; public static final int ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F; public static final int ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60; public static final int ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61; public static final int ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62; public static final int ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63; public static final int ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64; public static final int ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65; public static final int ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66; public static final int ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67; public static final int ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68; public static final int ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69; public static final int ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A; public static final int ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B; public static final int ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C; public static final int ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D; public static final int ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E; public static final int ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F; public static final int ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70; public static final int ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71; public static final int ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72; public static final int ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73; public static final int ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74; public static final int ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75; public static final int ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76; public static final int ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77; public static final int ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78; public static final int ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79; public static final int ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A; public static final int ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B; public static final int ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C; public static final int ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D; public static final int ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E; public static final int ARM64_SYSREG_TRCPRGCTLR = 0x8808; public static final int ARM64_SYSREG_TRCPROCSELR = 0x8810; public static final int ARM64_SYSREG_TRCCONFIGR = 0x8820; public static final int ARM64_SYSREG_TRCAUXCTLR = 0x8830; public static final int ARM64_SYSREG_TRCEVENTCTL0R = 0x8840; public static final int ARM64_SYSREG_TRCEVENTCTL1R = 0x8848; public static final int ARM64_SYSREG_TRCSTALLCTLR = 0x8858; public static final int ARM64_SYSREG_TRCTSCTLR = 0x8860; public static final int ARM64_SYSREG_TRCSYNCPR = 0x8868; public static final int ARM64_SYSREG_TRCCCCTLR = 0x8870; public static final int ARM64_SYSREG_TRCBBCTLR = 0x8878; public static final int ARM64_SYSREG_TRCTRACEIDR = 0x8801; public static final int ARM64_SYSREG_TRCQCTLR = 0x8809; public static final int ARM64_SYSREG_TRCVICTLR = 0x8802; public static final int ARM64_SYSREG_TRCVIIECTLR = 0x880A; public static final int ARM64_SYSREG_TRCVISSCTLR = 0x8812; public static final int ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A; public static final int ARM64_SYSREG_TRCVDCTLR = 0x8842; public static final int ARM64_SYSREG_TRCVDSACCTLR = 0x884A; public static final int ARM64_SYSREG_TRCVDARCCTLR = 0x8852; public static final int ARM64_SYSREG_TRCSEQEVR0 = 0x8804; public static final int ARM64_SYSREG_TRCSEQEVR1 = 0x880C; public static final int ARM64_SYSREG_TRCSEQEVR2 = 0x8814; public static final int ARM64_SYSREG_TRCSEQRSTEVR = 0x8834; public static final int ARM64_SYSREG_TRCSEQSTR = 0x883C; public static final int ARM64_SYSREG_TRCEXTINSELR = 0x8844; public static final int ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805; public static final int ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D; public static final int ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815; public static final int ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D; public static final int ARM64_SYSREG_TRCCNTCTLR0 = 0x8825; public static final int ARM64_SYSREG_TRCCNTCTLR1 = 0x882D; public static final int ARM64_SYSREG_TRCCNTCTLR2 = 0x8835; public static final int ARM64_SYSREG_TRCCNTCTLR3 = 0x883D; public static final int ARM64_SYSREG_TRCCNTVR0 = 0x8845; public static final int ARM64_SYSREG_TRCCNTVR1 = 0x884D; public static final int ARM64_SYSREG_TRCCNTVR2 = 0x8855; public static final int ARM64_SYSREG_TRCCNTVR3 = 0x885D; public static final int ARM64_SYSREG_TRCIMSPEC0 = 0x8807; public static final int ARM64_SYSREG_TRCIMSPEC1 = 0x880F; public static final int ARM64_SYSREG_TRCIMSPEC2 = 0x8817; public static final int ARM64_SYSREG_TRCIMSPEC3 = 0x881F; public static final int ARM64_SYSREG_TRCIMSPEC4 = 0x8827; public static final int ARM64_SYSREG_TRCIMSPEC5 = 0x882F; public static final int ARM64_SYSREG_TRCIMSPEC6 = 0x8837; public static final int ARM64_SYSREG_TRCIMSPEC7 = 0x883F; public static final int ARM64_SYSREG_TRCRSCTLR2 = 0x8890; public static final int ARM64_SYSREG_TRCRSCTLR3 = 0x8898; public static final int ARM64_SYSREG_TRCRSCTLR4 = 0x88A0; public static final int ARM64_SYSREG_TRCRSCTLR5 = 0x88A8; public static final int ARM64_SYSREG_TRCRSCTLR6 = 0x88B0; public static final int ARM64_SYSREG_TRCRSCTLR7 = 0x88B8; public static final int ARM64_SYSREG_TRCRSCTLR8 = 0x88C0; public static final int ARM64_SYSREG_TRCRSCTLR9 = 0x88C8; public static final int ARM64_SYSREG_TRCRSCTLR10 = 0x88D0; public static final int ARM64_SYSREG_TRCRSCTLR11 = 0x88D8; public static final int ARM64_SYSREG_TRCRSCTLR12 = 0x88E0; public static final int ARM64_SYSREG_TRCRSCTLR13 = 0x88E8; public static final int ARM64_SYSREG_TRCRSCTLR14 = 0x88F0; public static final int ARM64_SYSREG_TRCRSCTLR15 = 0x88F8; public static final int ARM64_SYSREG_TRCRSCTLR16 = 0x8881; public static final int ARM64_SYSREG_TRCRSCTLR17 = 0x8889; public static final int ARM64_SYSREG_TRCRSCTLR18 = 0x8891; public static final int ARM64_SYSREG_TRCRSCTLR19 = 0x8899; public static final int ARM64_SYSREG_TRCRSCTLR20 = 0x88A1; public static final int ARM64_SYSREG_TRCRSCTLR21 = 0x88A9; public static final int ARM64_SYSREG_TRCRSCTLR22 = 0x88B1; public static final int ARM64_SYSREG_TRCRSCTLR23 = 0x88B9; public static final int ARM64_SYSREG_TRCRSCTLR24 = 0x88C1; public static final int ARM64_SYSREG_TRCRSCTLR25 = 0x88C9; public static final int ARM64_SYSREG_TRCRSCTLR26 = 0x88D1; public static final int ARM64_SYSREG_TRCRSCTLR27 = 0x88D9; public static final int ARM64_SYSREG_TRCRSCTLR28 = 0x88E1; public static final int ARM64_SYSREG_TRCRSCTLR29 = 0x88E9; public static final int ARM64_SYSREG_TRCRSCTLR30 = 0x88F1; public static final int ARM64_SYSREG_TRCRSCTLR31 = 0x88F9; public static final int ARM64_SYSREG_TRCSSCCR0 = 0x8882; public static final int ARM64_SYSREG_TRCSSCCR1 = 0x888A; public static final int ARM64_SYSREG_TRCSSCCR2 = 0x8892; public static final int ARM64_SYSREG_TRCSSCCR3 = 0x889A; public static final int ARM64_SYSREG_TRCSSCCR4 = 0x88A2; public static final int ARM64_SYSREG_TRCSSCCR5 = 0x88AA; public static final int ARM64_SYSREG_TRCSSCCR6 = 0x88B2; public static final int ARM64_SYSREG_TRCSSCCR7 = 0x88BA; public static final int ARM64_SYSREG_TRCSSCSR0 = 0x88C2; public static final int ARM64_SYSREG_TRCSSCSR1 = 0x88CA; public static final int ARM64_SYSREG_TRCSSCSR2 = 0x88D2; public static final int ARM64_SYSREG_TRCSSCSR3 = 0x88DA; public static final int ARM64_SYSREG_TRCSSCSR4 = 0x88E2; public static final int ARM64_SYSREG_TRCSSCSR5 = 0x88EA; public static final int ARM64_SYSREG_TRCSSCSR6 = 0x88F2; public static final int ARM64_SYSREG_TRCSSCSR7 = 0x88FA; public static final int ARM64_SYSREG_TRCSSPCICR0 = 0x8883; public static final int ARM64_SYSREG_TRCSSPCICR1 = 0x888B; public static final int ARM64_SYSREG_TRCSSPCICR2 = 0x8893; public static final int ARM64_SYSREG_TRCSSPCICR3 = 0x889B; public static final int ARM64_SYSREG_TRCSSPCICR4 = 0x88A3; public static final int ARM64_SYSREG_TRCSSPCICR5 = 0x88AB; public static final int ARM64_SYSREG_TRCSSPCICR6 = 0x88B3; public static final int ARM64_SYSREG_TRCSSPCICR7 = 0x88BB; public static final int ARM64_SYSREG_TRCPDCR = 0x88A4; public static final int ARM64_SYSREG_TRCACVR0 = 0x8900; public static final int ARM64_SYSREG_TRCACVR1 = 0x8910; public static final int ARM64_SYSREG_TRCACVR2 = 0x8920; public static final int ARM64_SYSREG_TRCACVR3 = 0x8930; public static final int ARM64_SYSREG_TRCACVR4 = 0x8940; public static final int ARM64_SYSREG_TRCACVR5 = 0x8950; public static final int ARM64_SYSREG_TRCACVR6 = 0x8960; public static final int ARM64_SYSREG_TRCACVR7 = 0x8970; public static final int ARM64_SYSREG_TRCACVR8 = 0x8901; public static final int ARM64_SYSREG_TRCACVR9 = 0x8911; public static final int ARM64_SYSREG_TRCACVR10 = 0x8921; public static final int ARM64_SYSREG_TRCACVR11 = 0x8931; public static final int ARM64_SYSREG_TRCACVR12 = 0x8941; public static final int ARM64_SYSREG_TRCACVR13 = 0x8951; public static final int ARM64_SYSREG_TRCACVR14 = 0x8961; public static final int ARM64_SYSREG_TRCACVR15 = 0x8971; public static final int ARM64_SYSREG_TRCACATR0 = 0x8902; public static final int ARM64_SYSREG_TRCACATR1 = 0x8912; public static final int ARM64_SYSREG_TRCACATR2 = 0x8922; public static final int ARM64_SYSREG_TRCACATR3 = 0x8932; public static final int ARM64_SYSREG_TRCACATR4 = 0x8942; public static final int ARM64_SYSREG_TRCACATR5 = 0x8952; public static final int ARM64_SYSREG_TRCACATR6 = 0x8962; public static final int ARM64_SYSREG_TRCACATR7 = 0x8972; public static final int ARM64_SYSREG_TRCACATR8 = 0x8903; public static final int ARM64_SYSREG_TRCACATR9 = 0x8913; public static final int ARM64_SYSREG_TRCACATR10 = 0x8923; public static final int ARM64_SYSREG_TRCACATR11 = 0x8933; public static final int ARM64_SYSREG_TRCACATR12 = 0x8943; public static final int ARM64_SYSREG_TRCACATR13 = 0x8953; public static final int ARM64_SYSREG_TRCACATR14 = 0x8963; public static final int ARM64_SYSREG_TRCACATR15 = 0x8973; public static final int ARM64_SYSREG_TRCDVCVR0 = 0x8904; public static final int ARM64_SYSREG_TRCDVCVR1 = 0x8924; public static final int ARM64_SYSREG_TRCDVCVR2 = 0x8944; public static final int ARM64_SYSREG_TRCDVCVR3 = 0x8964; public static final int ARM64_SYSREG_TRCDVCVR4 = 0x8905; public static final int ARM64_SYSREG_TRCDVCVR5 = 0x8925; public static final int ARM64_SYSREG_TRCDVCVR6 = 0x8945; public static final int ARM64_SYSREG_TRCDVCVR7 = 0x8965; public static final int ARM64_SYSREG_TRCDVCMR0 = 0x8906; public static final int ARM64_SYSREG_TRCDVCMR1 = 0x8926; public static final int ARM64_SYSREG_TRCDVCMR2 = 0x8946; public static final int ARM64_SYSREG_TRCDVCMR3 = 0x8966; public static final int ARM64_SYSREG_TRCDVCMR4 = 0x8907; public static final int ARM64_SYSREG_TRCDVCMR5 = 0x8927; public static final int ARM64_SYSREG_TRCDVCMR6 = 0x8947; public static final int ARM64_SYSREG_TRCDVCMR7 = 0x8967; public static final int ARM64_SYSREG_TRCCIDCVR0 = 0x8980; public static final int ARM64_SYSREG_TRCCIDCVR1 = 0x8990; public static final int ARM64_SYSREG_TRCCIDCVR2 = 0x89A0; public static final int ARM64_SYSREG_TRCCIDCVR3 = 0x89B0; public static final int ARM64_SYSREG_TRCCIDCVR4 = 0x89C0; public static final int ARM64_SYSREG_TRCCIDCVR5 = 0x89D0; public static final int ARM64_SYSREG_TRCCIDCVR6 = 0x89E0; public static final int ARM64_SYSREG_TRCCIDCVR7 = 0x89F0; public static final int ARM64_SYSREG_TRCVMIDCVR0 = 0x8981; public static final int ARM64_SYSREG_TRCVMIDCVR1 = 0x8991; public static final int ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1; public static final int ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1; public static final int ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1; public static final int ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1; public static final int ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1; public static final int ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1; public static final int ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982; public static final int ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A; public static final int ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992; public static final int ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A; public static final int ARM64_SYSREG_TRCITCTRL = 0x8B84; public static final int ARM64_SYSREG_TRCCLAIMSET = 0x8BC6; public static final int ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE; public static final int ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663; public static final int ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643; public static final int ARM64_SYSREG_ICC_PMR_EL1 = 0xC230; public static final int ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664; public static final int ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664; public static final int ARM64_SYSREG_ICC_SRE_EL1 = 0xC665; public static final int ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D; public static final int ARM64_SYSREG_ICC_SRE_EL3 = 0xF665; public static final int ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666; public static final int ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667; public static final int ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667; public static final int ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668; public static final int ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644; public static final int ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645; public static final int ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646; public static final int ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647; public static final int ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648; public static final int ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649; public static final int ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A; public static final int ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B; public static final int ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640; public static final int ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641; public static final int ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642; public static final int ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643; public static final int ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648; public static final int ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649; public static final int ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A; public static final int ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B; public static final int ARM64_SYSREG_ICH_HCR_EL2 = 0xE658; public static final int ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A; public static final int ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F; public static final int ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C; public static final int ARM64_SYSREG_ICH_LR0_EL2 = 0xE660; public static final int ARM64_SYSREG_ICH_LR1_EL2 = 0xE661; public static final int ARM64_SYSREG_ICH_LR2_EL2 = 0xE662; public static final int ARM64_SYSREG_ICH_LR3_EL2 = 0xE663; public static final int ARM64_SYSREG_ICH_LR4_EL2 = 0xE664; public static final int ARM64_SYSREG_ICH_LR5_EL2 = 0xE665; public static final int ARM64_SYSREG_ICH_LR6_EL2 = 0xE666; public static final int ARM64_SYSREG_ICH_LR7_EL2 = 0xE667; public static final int ARM64_SYSREG_ICH_LR8_EL2 = 0xE668; public static final int ARM64_SYSREG_ICH_LR9_EL2 = 0xE669; public static final int ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A; public static final int ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B; public static final int ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C; public static final int ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D; public static final int ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E; public static final int ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F; public static final int ARM64_SYSREG_PAN = 0xC213; public static final int ARM64_SYSREG_LORSA_EL1 = 0xC520; public static final int ARM64_SYSREG_LOREA_EL1 = 0xC521; public static final int ARM64_SYSREG_LORN_EL1 = 0xC522; public static final int ARM64_SYSREG_LORC_EL1 = 0xC523; public static final int ARM64_SYSREG_TTBR1_EL2 = 0xE101; public static final int ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681; public static final int ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718; public static final int ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A; public static final int ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719; public static final int ARM64_SYSREG_SCTLR_EL12 = 0xE880; public static final int ARM64_SYSREG_CPACR_EL12 = 0xE882; public static final int ARM64_SYSREG_TTBR0_EL12 = 0xE900; public static final int ARM64_SYSREG_TTBR1_EL12 = 0xE901; public static final int ARM64_SYSREG_TCR_EL12 = 0xE902; public static final int ARM64_SYSREG_AFSR0_EL12 = 0xEA88; public static final int ARM64_SYSREG_AFSR1_EL12 = 0xEA89; public static final int ARM64_SYSREG_ESR_EL12 = 0xEA90; public static final int ARM64_SYSREG_FAR_EL12 = 0xEB00; public static final int ARM64_SYSREG_MAIR_EL12 = 0xED10; public static final int ARM64_SYSREG_AMAIR_EL12 = 0xED18; public static final int ARM64_SYSREG_VBAR_EL12 = 0xEE00; public static final int ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81; public static final int ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08; public static final int ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10; public static final int ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11; public static final int ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12; public static final int ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18; public static final int ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19; public static final int ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A; public static final int ARM64_SYSREG_SPSR_EL12 = 0xEA00; public static final int ARM64_SYSREG_ELR_EL12 = 0xEA01; public static final int ARM64_SYSREG_UAO = 0xC214; public static final int ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0; public static final int ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1; public static final int ARM64_SYSREG_PMBSR_EL1 = 0xC4D3; public static final int ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7; public static final int ARM64_SYSREG_PMSCR_EL2 = 0xE4C8; public static final int ARM64_SYSREG_PMSCR_EL12 = 0xECC8; public static final int ARM64_SYSREG_PMSCR_EL1 = 0xC4C8; public static final int ARM64_SYSREG_PMSICR_EL1 = 0xC4CA; public static final int ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB; public static final int ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC; public static final int ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD; public static final int ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE; public static final int ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF; public static final int ARM64_SYSREG_ERRSELR_EL1 = 0xC299; public static final int ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1; public static final int ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2; public static final int ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3; public static final int ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8; public static final int ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9; public static final int ARM64_SYSREG_DISR_EL1 = 0xC609; public static final int ARM64_SYSREG_VDISR_EL2 = 0xE609; public static final int ARM64_SYSREG_VSESR_EL2 = 0xE293; public static final int ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108; public static final int ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109; public static final int ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A; public static final int ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B; public static final int ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110; public static final int ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111; public static final int ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112; public static final int ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113; public static final int ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118; public static final int ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119; public static final int ARM64_SYSREG_VSTCR_EL2 = 0xE132; public static final int ARM64_SYSREG_VSTTBR_EL2 = 0xE130; public static final int ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720; public static final int ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722; public static final int ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721; public static final int ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728; public static final int ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A; public static final int ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729; public static final int ARM64_SYSREG_SDER32_EL2 = 0xE099; public static final int ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5; public static final int ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6; public static final int ARM64_SYSREG_ERXTS_EL1 = 0xC2AF; public static final int ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA; public static final int ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB; public static final int ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4; public static final int ARM64_SYSREG_MPAM0_EL1 = 0xC529; public static final int ARM64_SYSREG_MPAM1_EL1 = 0xC528; public static final int ARM64_SYSREG_MPAM2_EL2 = 0xE528; public static final int ARM64_SYSREG_MPAM3_EL3 = 0xF528; public static final int ARM64_SYSREG_MPAM1_EL12 = 0xED28; public static final int ARM64_SYSREG_MPAMHCR_EL2 = 0xE520; public static final int ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521; public static final int ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530; public static final int ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531; public static final int ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532; public static final int ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533; public static final int ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534; public static final int ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535; public static final int ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536; public static final int ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537; public static final int ARM64_SYSREG_MPAMIDR_EL1 = 0xC524; public static final int ARM64_SYSREG_AMCR_EL0 = 0xDE90; public static final int ARM64_SYSREG_AMCFGR_EL0 = 0xDE91; public static final int ARM64_SYSREG_AMCGCR_EL0 = 0xDE92; public static final int ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93; public static final int ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94; public static final int ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95; public static final int ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0; public static final int ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1; public static final int ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2; public static final int ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3; public static final int ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0; public static final int ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1; public static final int ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2; public static final int ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3; public static final int ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98; public static final int ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99; public static final int ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0; public static final int ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1; public static final int ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2; public static final int ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3; public static final int ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4; public static final int ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5; public static final int ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6; public static final int ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7; public static final int ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8; public static final int ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9; public static final int ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA; public static final int ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB; public static final int ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC; public static final int ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED; public static final int ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE; public static final int ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF; public static final int ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0; public static final int ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1; public static final int ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2; public static final int ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3; public static final int ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4; public static final int ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5; public static final int ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6; public static final int ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7; public static final int ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8; public static final int ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9; public static final int ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA; public static final int ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB; public static final int ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC; public static final int ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD; public static final int ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE; public static final int ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF; public static final int ARM64_SYSREG_TRFCR_EL1 = 0xC091; public static final int ARM64_SYSREG_TRFCR_EL2 = 0xE091; public static final int ARM64_SYSREG_TRFCR_EL12 = 0xE891; public static final int ARM64_SYSREG_DIT = 0xDA15; public static final int ARM64_SYSREG_VNCR_EL2 = 0xE110; public static final int ARM64_SYSREG_ZCR_EL1 = 0xC090; public static final int ARM64_SYSREG_ZCR_EL2 = 0xE090; public static final int ARM64_SYSREG_ZCR_EL3 = 0xF090; public static final int ARM64_SYSREG_ZCR_EL12 = 0xE890; public static final int ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90; public static final int ARM64_PSTATE_INVALID = 0; public static final int ARM64_PSTATE_SPSEL = 0x05; public static final int ARM64_PSTATE_DAIFSET = 0x1e; public static final int ARM64_PSTATE_DAIFCLR = 0x1f; public static final int ARM64_PSTATE_PAN = 0x4; public static final int ARM64_PSTATE_UAO = 0x3; public static final int ARM64_PSTATE_DIT = 0x1a; public static final int ARM64_VAS_INVALID = 0; public static final int ARM64_VAS_16B = 1; public static final int ARM64_VAS_8B = 2; public static final int ARM64_VAS_4B = 3; public static final int ARM64_VAS_1B = 4; public static final int ARM64_VAS_8H = 5; public static final int ARM64_VAS_4H = 6; public static final int ARM64_VAS_2H = 7; public static final int ARM64_VAS_1H = 8; public static final int ARM64_VAS_4S = 9; public static final int ARM64_VAS_2S = 10; public static final int ARM64_VAS_1S = 11; public static final int ARM64_VAS_2D = 12; public static final int ARM64_VAS_1D = 13; public static final int ARM64_VAS_1Q = 14; public static final int ARM64_BARRIER_INVALID = 0; public static final int ARM64_BARRIER_OSHLD = 0x1; public static final int ARM64_BARRIER_OSHST = 0x2; public static final int ARM64_BARRIER_OSH = 0x3; public static final int ARM64_BARRIER_NSHLD = 0x5; public static final int ARM64_BARRIER_NSHST = 0x6; public static final int ARM64_BARRIER_NSH = 0x7; public static final int ARM64_BARRIER_ISHLD = 0x9; public static final int ARM64_BARRIER_ISHST = 0xa; public static final int ARM64_BARRIER_ISH = 0xb; public static final int ARM64_BARRIER_LD = 0xd; public static final int ARM64_BARRIER_ST = 0xe; public static final int ARM64_BARRIER_SY = 0xf; public static final int ARM64_OP_INVALID = 0; public static final int ARM64_OP_REG = 1; public static final int ARM64_OP_IMM = 2; public static final int ARM64_OP_MEM = 3; public static final int ARM64_OP_FP = 4; public static final int ARM64_OP_CIMM = 64; public static final int ARM64_OP_REG_MRS = 65; public static final int ARM64_OP_REG_MSR = 66; public static final int ARM64_OP_PSTATE = 67; public static final int ARM64_OP_SYS = 68; public static final int ARM64_OP_PREFETCH = 69; public static final int ARM64_OP_BARRIER = 70; public static final int ARM64_TLBI_INVALID = 0; public static final int ARM64_TLBI_IPAS2E1IS = 1; public static final int ARM64_TLBI_IPAS2LE1IS = 2; public static final int ARM64_TLBI_VMALLE1IS = 3; public static final int ARM64_TLBI_ALLE2IS = 4; public static final int ARM64_TLBI_ALLE3IS = 5; public static final int ARM64_TLBI_VAE1IS = 6; public static final int ARM64_TLBI_VAE2IS = 7; public static final int ARM64_TLBI_VAE3IS = 8; public static final int ARM64_TLBI_ASIDE1IS = 9; public static final int ARM64_TLBI_VAAE1IS = 10; public static final int ARM64_TLBI_ALLE1IS = 11; public static final int ARM64_TLBI_VALE1IS = 12; public static final int ARM64_TLBI_VALE2IS = 13; public static final int ARM64_TLBI_VALE3IS = 14; public static final int ARM64_TLBI_VMALLS12E1IS = 15; public static final int ARM64_TLBI_VAALE1IS = 16; public static final int ARM64_TLBI_IPAS2E1 = 17; public static final int ARM64_TLBI_IPAS2LE1 = 18; public static final int ARM64_TLBI_VMALLE1 = 19; public static final int ARM64_TLBI_ALLE2 = 20; public static final int ARM64_TLBI_ALLE3 = 21; public static final int ARM64_TLBI_VAE1 = 22; public static final int ARM64_TLBI_VAE2 = 23; public static final int ARM64_TLBI_VAE3 = 24; public static final int ARM64_TLBI_ASIDE1 = 25; public static final int ARM64_TLBI_VAAE1 = 26; public static final int ARM64_TLBI_ALLE1 = 27; public static final int ARM64_TLBI_VALE1 = 28; public static final int ARM64_TLBI_VALE2 = 29; public static final int ARM64_TLBI_VALE3 = 30; public static final int ARM64_TLBI_VMALLS12E1 = 31; public static final int ARM64_TLBI_VAALE1 = 32; public static final int ARM64_TLBI_VMALLE1OS = 33; public static final int ARM64_TLBI_VAE1OS = 34; public static final int ARM64_TLBI_ASIDE1OS = 35; public static final int ARM64_TLBI_VAAE1OS = 36; public static final int ARM64_TLBI_VALE1OS = 37; public static final int ARM64_TLBI_VAALE1OS = 38; public static final int ARM64_TLBI_IPAS2E1OS = 39; public static final int ARM64_TLBI_IPAS2LE1OS = 40; public static final int ARM64_TLBI_VAE2OS = 41; public static final int ARM64_TLBI_VALE2OS = 42; public static final int ARM64_TLBI_VMALLS12E1OS = 43; public static final int ARM64_TLBI_VAE3OS = 44; public static final int ARM64_TLBI_VALE3OS = 45; public static final int ARM64_TLBI_ALLE2OS = 46; public static final int ARM64_TLBI_ALLE1OS = 47; public static final int ARM64_TLBI_ALLE3OS = 48; public static final int ARM64_TLBI_RVAE1 = 49; public static final int ARM64_TLBI_RVAAE1 = 50; public static final int ARM64_TLBI_RVALE1 = 51; public static final int ARM64_TLBI_RVAALE1 = 52; public static final int ARM64_TLBI_RVAE1IS = 53; public static final int ARM64_TLBI_RVAAE1IS = 54; public static final int ARM64_TLBI_RVALE1IS = 55; public static final int ARM64_TLBI_RVAALE1IS = 56; public static final int ARM64_TLBI_RVAE1OS = 57; public static final int ARM64_TLBI_RVAAE1OS = 58; public static final int ARM64_TLBI_RVALE1OS = 59; public static final int ARM64_TLBI_RVAALE1OS = 60; public static final int ARM64_TLBI_RIPAS2E1IS = 61; public static final int ARM64_TLBI_RIPAS2LE1IS = 62; public static final int ARM64_TLBI_RIPAS2E1 = 63; public static final int ARM64_TLBI_RIPAS2LE1 = 64; public static final int ARM64_TLBI_RIPAS2E1OS = 65; public static final int ARM64_TLBI_RIPAS2LE1OS = 66; public static final int ARM64_TLBI_RVAE2 = 67; public static final int ARM64_TLBI_RVALE2 = 68; public static final int ARM64_TLBI_RVAE2IS = 69; public static final int ARM64_TLBI_RVALE2IS = 70; public static final int ARM64_TLBI_RVAE2OS = 71; public static final int ARM64_TLBI_RVALE2OS = 72; public static final int ARM64_TLBI_RVAE3 = 73; public static final int ARM64_TLBI_RVALE3 = 74; public static final int ARM64_TLBI_RVAE3IS = 75; public static final int ARM64_TLBI_RVALE3IS = 76; public static final int ARM64_TLBI_RVAE3OS = 77; public static final int ARM64_TLBI_RVALE3OS = 78; public static final int ARM64_AT_S1E1R = 79; public static final int ARM64_AT_S1E2R = 80; public static final int ARM64_AT_S1E3R = 81; public static final int ARM64_AT_S1E1W = 82; public static final int ARM64_AT_S1E2W = 83; public static final int ARM64_AT_S1E3W = 84; public static final int ARM64_AT_S1E0R = 85; public static final int ARM64_AT_S1E0W = 86; public static final int ARM64_AT_S12E1R = 87; public static final int ARM64_AT_S12E1W = 88; public static final int ARM64_AT_S12E0R = 89; public static final int ARM64_AT_S12E0W = 90; public static final int ARM64_AT_S1E1RP = 91; public static final int ARM64_AT_S1E1WP = 92; public static final int ARM64_DC_INVALID = 0; public static final int ARM64_DC_ZVA = 1; public static final int ARM64_DC_IVAC = 2; public static final int ARM64_DC_ISW = 3; public static final int ARM64_DC_CVAC = 4; public static final int ARM64_DC_CSW = 5; public static final int ARM64_DC_CVAU = 6; public static final int ARM64_DC_CIVAC = 7; public static final int ARM64_DC_CISW = 8; public static final int ARM64_DC_CVAP = 9; public static final int ARM64_IC_INVALID = 0; public static final int ARM64_IC_IALLUIS = 1; public static final int ARM64_IC_IALLU = 2; public static final int ARM64_IC_IVAU = 3; public static final int ARM64_PRFM_INVALID = 0; public static final int ARM64_PRFM_PLDL1KEEP = 0x00+1; public static final int ARM64_PRFM_PLDL1STRM = 0x01+1; public static final int ARM64_PRFM_PLDL2KEEP = 0x02+1; public static final int ARM64_PRFM_PLDL2STRM = 0x03+1; public static final int ARM64_PRFM_PLDL3KEEP = 0x04+1; public static final int ARM64_PRFM_PLDL3STRM = 0x05+1; public static final int ARM64_PRFM_PLIL1KEEP = 0x08+1; public static final int ARM64_PRFM_PLIL1STRM = 0x09+1; public static final int ARM64_PRFM_PLIL2KEEP = 0x0a+1; public static final int ARM64_PRFM_PLIL2STRM = 0x0b+1; public static final int ARM64_PRFM_PLIL3KEEP = 0x0c+1; public static final int ARM64_PRFM_PLIL3STRM = 0x0d+1; public static final int ARM64_PRFM_PSTL1KEEP = 0x10+1; public static final int ARM64_PRFM_PSTL1STRM = 0x11+1; public static final int ARM64_PRFM_PSTL2KEEP = 0x12+1; public static final int ARM64_PRFM_PSTL2STRM = 0x13+1; public static final int ARM64_PRFM_PSTL3KEEP = 0x14+1; public static final int ARM64_PRFM_PSTL3STRM = 0x15+1; public static final int ARM64_REG_INVALID = 0; public static final int ARM64_REG_FFR = 1; public static final int ARM64_REG_FP = 2; public static final int ARM64_REG_LR = 3; public static final int ARM64_REG_NZCV = 4; public static final int ARM64_REG_SP = 5; public static final int ARM64_REG_WSP = 6; public static final int ARM64_REG_WZR = 7; public static final int ARM64_REG_XZR = 8; public static final int ARM64_REG_B0 = 9; public static final int ARM64_REG_B1 = 10; public static final int ARM64_REG_B2 = 11; public static final int ARM64_REG_B3 = 12; public static final int ARM64_REG_B4 = 13; public static final int ARM64_REG_B5 = 14; public static final int ARM64_REG_B6 = 15; public static final int ARM64_REG_B7 = 16; public static final int ARM64_REG_B8 = 17; public static final int ARM64_REG_B9 = 18; public static final int ARM64_REG_B10 = 19; public static final int ARM64_REG_B11 = 20; public static final int ARM64_REG_B12 = 21; public static final int ARM64_REG_B13 = 22; public static final int ARM64_REG_B14 = 23; public static final int ARM64_REG_B15 = 24; public static final int ARM64_REG_B16 = 25; public static final int ARM64_REG_B17 = 26; public static final int ARM64_REG_B18 = 27; public static final int ARM64_REG_B19 = 28; public static final int ARM64_REG_B20 = 29; public static final int ARM64_REG_B21 = 30; public static final int ARM64_REG_B22 = 31; public static final int ARM64_REG_B23 = 32; public static final int ARM64_REG_B24 = 33; public static final int ARM64_REG_B25 = 34; public static final int ARM64_REG_B26 = 35; public static final int ARM64_REG_B27 = 36; public static final int ARM64_REG_B28 = 37; public static final int ARM64_REG_B29 = 38; public static final int ARM64_REG_B30 = 39; public static final int ARM64_REG_B31 = 40; public static final int ARM64_REG_D0 = 41; public static final int ARM64_REG_D1 = 42; public static final int ARM64_REG_D2 = 43; public static final int ARM64_REG_D3 = 44; public static final int ARM64_REG_D4 = 45; public static final int ARM64_REG_D5 = 46; public static final int ARM64_REG_D6 = 47; public static final int ARM64_REG_D7 = 48; public static final int ARM64_REG_D8 = 49; public static final int ARM64_REG_D9 = 50; public static final int ARM64_REG_D10 = 51; public static final int ARM64_REG_D11 = 52; public static final int ARM64_REG_D12 = 53; public static final int ARM64_REG_D13 = 54; public static final int ARM64_REG_D14 = 55; public static final int ARM64_REG_D15 = 56; public static final int ARM64_REG_D16 = 57; public static final int ARM64_REG_D17 = 58; public static final int ARM64_REG_D18 = 59; public static final int ARM64_REG_D19 = 60; public static final int ARM64_REG_D20 = 61; public static final int ARM64_REG_D21 = 62; public static final int ARM64_REG_D22 = 63; public static final int ARM64_REG_D23 = 64; public static final int ARM64_REG_D24 = 65; public static final int ARM64_REG_D25 = 66; public static final int ARM64_REG_D26 = 67; public static final int ARM64_REG_D27 = 68; public static final int ARM64_REG_D28 = 69; public static final int ARM64_REG_D29 = 70; public static final int ARM64_REG_D30 = 71; public static final int ARM64_REG_D31 = 72; public static final int ARM64_REG_H0 = 73; public static final int ARM64_REG_H1 = 74; public static final int ARM64_REG_H2 = 75; public static final int ARM64_REG_H3 = 76; public static final int ARM64_REG_H4 = 77; public static final int ARM64_REG_H5 = 78; public static final int ARM64_REG_H6 = 79; public static final int ARM64_REG_H7 = 80; public static final int ARM64_REG_H8 = 81; public static final int ARM64_REG_H9 = 82; public static final int ARM64_REG_H10 = 83; public static final int ARM64_REG_H11 = 84; public static final int ARM64_REG_H12 = 85; public static final int ARM64_REG_H13 = 86; public static final int ARM64_REG_H14 = 87; public static final int ARM64_REG_H15 = 88; public static final int ARM64_REG_H16 = 89; public static final int ARM64_REG_H17 = 90; public static final int ARM64_REG_H18 = 91; public static final int ARM64_REG_H19 = 92; public static final int ARM64_REG_H20 = 93; public static final int ARM64_REG_H21 = 94; public static final int ARM64_REG_H22 = 95; public static final int ARM64_REG_H23 = 96; public static final int ARM64_REG_H24 = 97; public static final int ARM64_REG_H25 = 98; public static final int ARM64_REG_H26 = 99; public static final int ARM64_REG_H27 = 100; public static final int ARM64_REG_H28 = 101; public static final int ARM64_REG_H29 = 102; public static final int ARM64_REG_H30 = 103; public static final int ARM64_REG_H31 = 104; public static final int ARM64_REG_P0 = 105; public static final int ARM64_REG_P1 = 106; public static final int ARM64_REG_P2 = 107; public static final int ARM64_REG_P3 = 108; public static final int ARM64_REG_P4 = 109; public static final int ARM64_REG_P5 = 110; public static final int ARM64_REG_P6 = 111; public static final int ARM64_REG_P7 = 112; public static final int ARM64_REG_P8 = 113; public static final int ARM64_REG_P9 = 114; public static final int ARM64_REG_P10 = 115; public static final int ARM64_REG_P11 = 116; public static final int ARM64_REG_P12 = 117; public static final int ARM64_REG_P13 = 118; public static final int ARM64_REG_P14 = 119; public static final int ARM64_REG_P15 = 120; public static final int ARM64_REG_Q0 = 121; public static final int ARM64_REG_Q1 = 122; public static final int ARM64_REG_Q2 = 123; public static final int ARM64_REG_Q3 = 124; public static final int ARM64_REG_Q4 = 125; public static final int ARM64_REG_Q5 = 126; public static final int ARM64_REG_Q6 = 127; public static final int ARM64_REG_Q7 = 128; public static final int ARM64_REG_Q8 = 129; public static final int ARM64_REG_Q9 = 130; public static final int ARM64_REG_Q10 = 131; public static final int ARM64_REG_Q11 = 132; public static final int ARM64_REG_Q12 = 133; public static final int ARM64_REG_Q13 = 134; public static final int ARM64_REG_Q14 = 135; public static final int ARM64_REG_Q15 = 136; public static final int ARM64_REG_Q16 = 137; public static final int ARM64_REG_Q17 = 138; public static final int ARM64_REG_Q18 = 139; public static final int ARM64_REG_Q19 = 140; public static final int ARM64_REG_Q20 = 141; public static final int ARM64_REG_Q21 = 142; public static final int ARM64_REG_Q22 = 143; public static final int ARM64_REG_Q23 = 144; public static final int ARM64_REG_Q24 = 145; public static final int ARM64_REG_Q25 = 146; public static final int ARM64_REG_Q26 = 147; public static final int ARM64_REG_Q27 = 148; public static final int ARM64_REG_Q28 = 149; public static final int ARM64_REG_Q29 = 150; public static final int ARM64_REG_Q30 = 151; public static final int ARM64_REG_Q31 = 152; public static final int ARM64_REG_S0 = 153; public static final int ARM64_REG_S1 = 154; public static final int ARM64_REG_S2 = 155; public static final int ARM64_REG_S3 = 156; public static final int ARM64_REG_S4 = 157; public static final int ARM64_REG_S5 = 158; public static final int ARM64_REG_S6 = 159; public static final int ARM64_REG_S7 = 160; public static final int ARM64_REG_S8 = 161; public static final int ARM64_REG_S9 = 162; public static final int ARM64_REG_S10 = 163; public static final int ARM64_REG_S11 = 164; public static final int ARM64_REG_S12 = 165; public static final int ARM64_REG_S13 = 166; public static final int ARM64_REG_S14 = 167; public static final int ARM64_REG_S15 = 168; public static final int ARM64_REG_S16 = 169; public static final int ARM64_REG_S17 = 170; public static final int ARM64_REG_S18 = 171; public static final int ARM64_REG_S19 = 172; public static final int ARM64_REG_S20 = 173; public static final int ARM64_REG_S21 = 174; public static final int ARM64_REG_S22 = 175; public static final int ARM64_REG_S23 = 176; public static final int ARM64_REG_S24 = 177; public static final int ARM64_REG_S25 = 178; public static final int ARM64_REG_S26 = 179; public static final int ARM64_REG_S27 = 180; public static final int ARM64_REG_S28 = 181; public static final int ARM64_REG_S29 = 182; public static final int ARM64_REG_S30 = 183; public static final int ARM64_REG_S31 = 184; public static final int ARM64_REG_W0 = 185; public static final int ARM64_REG_W1 = 186; public static final int ARM64_REG_W2 = 187; public static final int ARM64_REG_W3 = 188; public static final int ARM64_REG_W4 = 189; public static final int ARM64_REG_W5 = 190; public static final int ARM64_REG_W6 = 191; public static final int ARM64_REG_W7 = 192; public static final int ARM64_REG_W8 = 193; public static final int ARM64_REG_W9 = 194; public static final int ARM64_REG_W10 = 195; public static final int ARM64_REG_W11 = 196; public static final int ARM64_REG_W12 = 197; public static final int ARM64_REG_W13 = 198; public static final int ARM64_REG_W14 = 199; public static final int ARM64_REG_W15 = 200; public static final int ARM64_REG_W16 = 201; public static final int ARM64_REG_W17 = 202; public static final int ARM64_REG_W18 = 203; public static final int ARM64_REG_W19 = 204; public static final int ARM64_REG_W20 = 205; public static final int ARM64_REG_W21 = 206; public static final int ARM64_REG_W22 = 207; public static final int ARM64_REG_W23 = 208; public static final int ARM64_REG_W24 = 209; public static final int ARM64_REG_W25 = 210; public static final int ARM64_REG_W26 = 211; public static final int ARM64_REG_W27 = 212; public static final int ARM64_REG_W28 = 213; public static final int ARM64_REG_W29 = 214; public static final int ARM64_REG_W30 = 215; public static final int ARM64_REG_X0 = 216; public static final int ARM64_REG_X1 = 217; public static final int ARM64_REG_X2 = 218; public static final int ARM64_REG_X3 = 219; public static final int ARM64_REG_X4 = 220; public static final int ARM64_REG_X5 = 221; public static final int ARM64_REG_X6 = 222; public static final int ARM64_REG_X7 = 223; public static final int ARM64_REG_X8 = 224; public static final int ARM64_REG_X9 = 225; public static final int ARM64_REG_X10 = 226; public static final int ARM64_REG_X11 = 227; public static final int ARM64_REG_X12 = 228; public static final int ARM64_REG_X13 = 229; public static final int ARM64_REG_X14 = 230; public static final int ARM64_REG_X15 = 231; public static final int ARM64_REG_X16 = 232; public static final int ARM64_REG_X17 = 233; public static final int ARM64_REG_X18 = 234; public static final int ARM64_REG_X19 = 235; public static final int ARM64_REG_X20 = 236; public static final int ARM64_REG_X21 = 237; public static final int ARM64_REG_X22 = 238; public static final int ARM64_REG_X23 = 239; public static final int ARM64_REG_X24 = 240; public static final int ARM64_REG_X25 = 241; public static final int ARM64_REG_X26 = 242; public static final int ARM64_REG_X27 = 243; public static final int ARM64_REG_X28 = 244; public static final int ARM64_REG_Z0 = 245; public static final int ARM64_REG_Z1 = 246; public static final int ARM64_REG_Z2 = 247; public static final int ARM64_REG_Z3 = 248; public static final int ARM64_REG_Z4 = 249; public static final int ARM64_REG_Z5 = 250; public static final int ARM64_REG_Z6 = 251; public static final int ARM64_REG_Z7 = 252; public static final int ARM64_REG_Z8 = 253; public static final int ARM64_REG_Z9 = 254; public static final int ARM64_REG_Z10 = 255; public static final int ARM64_REG_Z11 = 256; public static final int ARM64_REG_Z12 = 257; public static final int ARM64_REG_Z13 = 258; public static final int ARM64_REG_Z14 = 259; public static final int ARM64_REG_Z15 = 260; public static final int ARM64_REG_Z16 = 261; public static final int ARM64_REG_Z17 = 262; public static final int ARM64_REG_Z18 = 263; public static final int ARM64_REG_Z19 = 264; public static final int ARM64_REG_Z20 = 265; public static final int ARM64_REG_Z21 = 266; public static final int ARM64_REG_Z22 = 267; public static final int ARM64_REG_Z23 = 268; public static final int ARM64_REG_Z24 = 269; public static final int ARM64_REG_Z25 = 270; public static final int ARM64_REG_Z26 = 271; public static final int ARM64_REG_Z27 = 272; public static final int ARM64_REG_Z28 = 273; public static final int ARM64_REG_Z29 = 274; public static final int ARM64_REG_Z30 = 275; public static final int ARM64_REG_Z31 = 276; public static final int ARM64_REG_V0 = 277; public static final int ARM64_REG_V1 = 278; public static final int ARM64_REG_V2 = 279; public static final int ARM64_REG_V3 = 280; public static final int ARM64_REG_V4 = 281; public static final int ARM64_REG_V5 = 282; public static final int ARM64_REG_V6 = 283; public static final int ARM64_REG_V7 = 284; public static final int ARM64_REG_V8 = 285; public static final int ARM64_REG_V9 = 286; public static final int ARM64_REG_V10 = 287; public static final int ARM64_REG_V11 = 288; public static final int ARM64_REG_V12 = 289; public static final int ARM64_REG_V13 = 290; public static final int ARM64_REG_V14 = 291; public static final int ARM64_REG_V15 = 292; public static final int ARM64_REG_V16 = 293; public static final int ARM64_REG_V17 = 294; public static final int ARM64_REG_V18 = 295; public static final int ARM64_REG_V19 = 296; public static final int ARM64_REG_V20 = 297; public static final int ARM64_REG_V21 = 298; public static final int ARM64_REG_V22 = 299; public static final int ARM64_REG_V23 = 300; public static final int ARM64_REG_V24 = 301; public static final int ARM64_REG_V25 = 302; public static final int ARM64_REG_V26 = 303; public static final int ARM64_REG_V27 = 304; public static final int ARM64_REG_V28 = 305; public static final int ARM64_REG_V29 = 306; public static final int ARM64_REG_V30 = 307; public static final int ARM64_REG_V31 = 308; public static final int ARM64_REG_ENDING = 309; public static final int ARM64_REG_IP0 = ARM64_REG_X16; public static final int ARM64_REG_IP1 = ARM64_REG_X17; public static final int ARM64_REG_X29 = ARM64_REG_FP; public static final int ARM64_REG_X30 = ARM64_REG_LR; public static final int ARM64_INS_INVALID = 0; public static final int ARM64_INS_ABS = 1; public static final int ARM64_INS_ADC = 2; public static final int ARM64_INS_ADCS = 3; public static final int ARM64_INS_ADD = 4; public static final int ARM64_INS_ADDHN = 5; public static final int ARM64_INS_ADDHN2 = 6; public static final int ARM64_INS_ADDP = 7; public static final int ARM64_INS_ADDPL = 8; public static final int ARM64_INS_ADDS = 9; public static final int ARM64_INS_ADDV = 10; public static final int ARM64_INS_ADDVL = 11; public static final int ARM64_INS_ADR = 12; public static final int ARM64_INS_ADRP = 13; public static final int ARM64_INS_AESD = 14; public static final int ARM64_INS_AESE = 15; public static final int ARM64_INS_AESIMC = 16; public static final int ARM64_INS_AESMC = 17; public static final int ARM64_INS_AND = 18; public static final int ARM64_INS_ANDS = 19; public static final int ARM64_INS_ANDV = 20; public static final int ARM64_INS_ASR = 21; public static final int ARM64_INS_ASRD = 22; public static final int ARM64_INS_ASRR = 23; public static final int ARM64_INS_ASRV = 24; public static final int ARM64_INS_AUTDA = 25; public static final int ARM64_INS_AUTDB = 26; public static final int ARM64_INS_AUTDZA = 27; public static final int ARM64_INS_AUTDZB = 28; public static final int ARM64_INS_AUTIA = 29; public static final int ARM64_INS_AUTIA1716 = 30; public static final int ARM64_INS_AUTIASP = 31; public static final int ARM64_INS_AUTIAZ = 32; public static final int ARM64_INS_AUTIB = 33; public static final int ARM64_INS_AUTIB1716 = 34; public static final int ARM64_INS_AUTIBSP = 35; public static final int ARM64_INS_AUTIBZ = 36; public static final int ARM64_INS_AUTIZA = 37; public static final int ARM64_INS_AUTIZB = 38; public static final int ARM64_INS_B = 39; public static final int ARM64_INS_BCAX = 40; public static final int ARM64_INS_BFM = 41; public static final int ARM64_INS_BIC = 42; public static final int ARM64_INS_BICS = 43; public static final int ARM64_INS_BIF = 44; public static final int ARM64_INS_BIT = 45; public static final int ARM64_INS_BL = 46; public static final int ARM64_INS_BLR = 47; public static final int ARM64_INS_BLRAA = 48; public static final int ARM64_INS_BLRAAZ = 49; public static final int ARM64_INS_BLRAB = 50; public static final int ARM64_INS_BLRABZ = 51; public static final int ARM64_INS_BR = 52; public static final int ARM64_INS_BRAA = 53; public static final int ARM64_INS_BRAAZ = 54; public static final int ARM64_INS_BRAB = 55; public static final int ARM64_INS_BRABZ = 56; public static final int ARM64_INS_BRK = 57; public static final int ARM64_INS_BRKA = 58; public static final int ARM64_INS_BRKAS = 59; public static final int ARM64_INS_BRKB = 60; public static final int ARM64_INS_BRKBS = 61; public static final int ARM64_INS_BRKN = 62; public static final int ARM64_INS_BRKNS = 63; public static final int ARM64_INS_BRKPA = 64; public static final int ARM64_INS_BRKPAS = 65; public static final int ARM64_INS_BRKPB = 66; public static final int ARM64_INS_BRKPBS = 67; public static final int ARM64_INS_BSL = 68; public static final int ARM64_INS_CAS = 69; public static final int ARM64_INS_CASA = 70; public static final int ARM64_INS_CASAB = 71; public static final int ARM64_INS_CASAH = 72; public static final int ARM64_INS_CASAL = 73; public static final int ARM64_INS_CASALB = 74; public static final int ARM64_INS_CASALH = 75; public static final int ARM64_INS_CASB = 76; public static final int ARM64_INS_CASH = 77; public static final int ARM64_INS_CASL = 78; public static final int ARM64_INS_CASLB = 79; public static final int ARM64_INS_CASLH = 80; public static final int ARM64_INS_CASP = 81; public static final int ARM64_INS_CASPA = 82; public static final int ARM64_INS_CASPAL = 83; public static final int ARM64_INS_CASPL = 84; public static final int ARM64_INS_CBNZ = 85; public static final int ARM64_INS_CBZ = 86; public static final int ARM64_INS_CCMN = 87; public static final int ARM64_INS_CCMP = 88; public static final int ARM64_INS_CFINV = 89; public static final int ARM64_INS_CINC = 90; public static final int ARM64_INS_CINV = 91; public static final int ARM64_INS_CLASTA = 92; public static final int ARM64_INS_CLASTB = 93; public static final int ARM64_INS_CLREX = 94; public static final int ARM64_INS_CLS = 95; public static final int ARM64_INS_CLZ = 96; public static final int ARM64_INS_CMEQ = 97; public static final int ARM64_INS_CMGE = 98; public static final int ARM64_INS_CMGT = 99; public static final int ARM64_INS_CMHI = 100; public static final int ARM64_INS_CMHS = 101; public static final int ARM64_INS_CMLE = 102; public static final int ARM64_INS_CMLO = 103; public static final int ARM64_INS_CMLS = 104; public static final int ARM64_INS_CMLT = 105; public static final int ARM64_INS_CMN = 106; public static final int ARM64_INS_CMP = 107; public static final int ARM64_INS_CMPEQ = 108; public static final int ARM64_INS_CMPGE = 109; public static final int ARM64_INS_CMPGT = 110; public static final int ARM64_INS_CMPHI = 111; public static final int ARM64_INS_CMPHS = 112; public static final int ARM64_INS_CMPLE = 113; public static final int ARM64_INS_CMPLO = 114; public static final int ARM64_INS_CMPLS = 115; public static final int ARM64_INS_CMPLT = 116; public static final int ARM64_INS_CMPNE = 117; public static final int ARM64_INS_CMTST = 118; public static final int ARM64_INS_CNEG = 119; public static final int ARM64_INS_CNOT = 120; public static final int ARM64_INS_CNT = 121; public static final int ARM64_INS_CNTB = 122; public static final int ARM64_INS_CNTD = 123; public static final int ARM64_INS_CNTH = 124; public static final int ARM64_INS_CNTP = 125; public static final int ARM64_INS_CNTW = 126; public static final int ARM64_INS_COMPACT = 127; public static final int ARM64_INS_CPY = 128; public static final int ARM64_INS_CRC32B = 129; public static final int ARM64_INS_CRC32CB = 130; public static final int ARM64_INS_CRC32CH = 131; public static final int ARM64_INS_CRC32CW = 132; public static final int ARM64_INS_CRC32CX = 133; public static final int ARM64_INS_CRC32H = 134; public static final int ARM64_INS_CRC32W = 135; public static final int ARM64_INS_CRC32X = 136; public static final int ARM64_INS_CSDB = 137; public static final int ARM64_INS_CSEL = 138; public static final int ARM64_INS_CSET = 139; public static final int ARM64_INS_CSETM = 140; public static final int ARM64_INS_CSINC = 141; public static final int ARM64_INS_CSINV = 142; public static final int ARM64_INS_CSNEG = 143; public static final int ARM64_INS_CTERMEQ = 144; public static final int ARM64_INS_CTERMNE = 145; public static final int ARM64_INS_DCPS1 = 146; public static final int ARM64_INS_DCPS2 = 147; public static final int ARM64_INS_DCPS3 = 148; public static final int ARM64_INS_DECB = 149; public static final int ARM64_INS_DECD = 150; public static final int ARM64_INS_DECH = 151; public static final int ARM64_INS_DECP = 152; public static final int ARM64_INS_DECW = 153; public static final int ARM64_INS_DMB = 154; public static final int ARM64_INS_DRPS = 155; public static final int ARM64_INS_DSB = 156; public static final int ARM64_INS_DUP = 157; public static final int ARM64_INS_DUPM = 158; public static final int ARM64_INS_EON = 159; public static final int ARM64_INS_EOR = 160; public static final int ARM64_INS_EOR3 = 161; public static final int ARM64_INS_EORS = 162; public static final int ARM64_INS_EORV = 163; public static final int ARM64_INS_ERET = 164; public static final int ARM64_INS_ERETAA = 165; public static final int ARM64_INS_ERETAB = 166; public static final int ARM64_INS_ESB = 167; public static final int ARM64_INS_EXT = 168; public static final int ARM64_INS_EXTR = 169; public static final int ARM64_INS_FABD = 170; public static final int ARM64_INS_FABS = 171; public static final int ARM64_INS_FACGE = 172; public static final int ARM64_INS_FACGT = 173; public static final int ARM64_INS_FACLE = 174; public static final int ARM64_INS_FACLT = 175; public static final int ARM64_INS_FADD = 176; public static final int ARM64_INS_FADDA = 177; public static final int ARM64_INS_FADDP = 178; public static final int ARM64_INS_FADDV = 179; public static final int ARM64_INS_FCADD = 180; public static final int ARM64_INS_FCCMP = 181; public static final int ARM64_INS_FCCMPE = 182; public static final int ARM64_INS_FCMEQ = 183; public static final int ARM64_INS_FCMGE = 184; public static final int ARM64_INS_FCMGT = 185; public static final int ARM64_INS_FCMLA = 186; public static final int ARM64_INS_FCMLE = 187; public static final int ARM64_INS_FCMLT = 188; public static final int ARM64_INS_FCMNE = 189; public static final int ARM64_INS_FCMP = 190; public static final int ARM64_INS_FCMPE = 191; public static final int ARM64_INS_FCMUO = 192; public static final int ARM64_INS_FCPY = 193; public static final int ARM64_INS_FCSEL = 194; public static final int ARM64_INS_FCVT = 195; public static final int ARM64_INS_FCVTAS = 196; public static final int ARM64_INS_FCVTAU = 197; public static final int ARM64_INS_FCVTL = 198; public static final int ARM64_INS_FCVTL2 = 199; public static final int ARM64_INS_FCVTMS = 200; public static final int ARM64_INS_FCVTMU = 201; public static final int ARM64_INS_FCVTN = 202; public static final int ARM64_INS_FCVTN2 = 203; public static final int ARM64_INS_FCVTNS = 204; public static final int ARM64_INS_FCVTNU = 205; public static final int ARM64_INS_FCVTPS = 206; public static final int ARM64_INS_FCVTPU = 207; public static final int ARM64_INS_FCVTXN = 208; public static final int ARM64_INS_FCVTXN2 = 209; public static final int ARM64_INS_FCVTZS = 210; public static final int ARM64_INS_FCVTZU = 211; public static final int ARM64_INS_FDIV = 212; public static final int ARM64_INS_FDIVR = 213; public static final int ARM64_INS_FDUP = 214; public static final int ARM64_INS_FEXPA = 215; public static final int ARM64_INS_FJCVTZS = 216; public static final int ARM64_INS_FMAD = 217; public static final int ARM64_INS_FMADD = 218; public static final int ARM64_INS_FMAX = 219; public static final int ARM64_INS_FMAXNM = 220; public static final int ARM64_INS_FMAXNMP = 221; public static final int ARM64_INS_FMAXNMV = 222; public static final int ARM64_INS_FMAXP = 223; public static final int ARM64_INS_FMAXV = 224; public static final int ARM64_INS_FMIN = 225; public static final int ARM64_INS_FMINNM = 226; public static final int ARM64_INS_FMINNMP = 227; public static final int ARM64_INS_FMINNMV = 228; public static final int ARM64_INS_FMINP = 229; public static final int ARM64_INS_FMINV = 230; public static final int ARM64_INS_FMLA = 231; public static final int ARM64_INS_FMLS = 232; public static final int ARM64_INS_FMOV = 233; public static final int ARM64_INS_FMSB = 234; public static final int ARM64_INS_FMSUB = 235; public static final int ARM64_INS_FMUL = 236; public static final int ARM64_INS_FMULX = 237; public static final int ARM64_INS_FNEG = 238; public static final int ARM64_INS_FNMAD = 239; public static final int ARM64_INS_FNMADD = 240; public static final int ARM64_INS_FNMLA = 241; public static final int ARM64_INS_FNMLS = 242; public static final int ARM64_INS_FNMSB = 243; public static final int ARM64_INS_FNMSUB = 244; public static final int ARM64_INS_FNMUL = 245; public static final int ARM64_INS_FRECPE = 246; public static final int ARM64_INS_FRECPS = 247; public static final int ARM64_INS_FRECPX = 248; public static final int ARM64_INS_FRINTA = 249; public static final int ARM64_INS_FRINTI = 250; public static final int ARM64_INS_FRINTM = 251; public static final int ARM64_INS_FRINTN = 252; public static final int ARM64_INS_FRINTP = 253; public static final int ARM64_INS_FRINTX = 254; public static final int ARM64_INS_FRINTZ = 255; public static final int ARM64_INS_FRSQRTE = 256; public static final int ARM64_INS_FRSQRTS = 257; public static final int ARM64_INS_FSCALE = 258; public static final int ARM64_INS_FSQRT = 259; public static final int ARM64_INS_FSUB = 260; public static final int ARM64_INS_FSUBR = 261; public static final int ARM64_INS_FTMAD = 262; public static final int ARM64_INS_FTSMUL = 263; public static final int ARM64_INS_FTSSEL = 264; public static final int ARM64_INS_HINT = 265; public static final int ARM64_INS_HLT = 266; public static final int ARM64_INS_HVC = 267; public static final int ARM64_INS_INCB = 268; public static final int ARM64_INS_INCD = 269; public static final int ARM64_INS_INCH = 270; public static final int ARM64_INS_INCP = 271; public static final int ARM64_INS_INCW = 272; public static final int ARM64_INS_INDEX = 273; public static final int ARM64_INS_INS = 274; public static final int ARM64_INS_INSR = 275; public static final int ARM64_INS_ISB = 276; public static final int ARM64_INS_LASTA = 277; public static final int ARM64_INS_LASTB = 278; public static final int ARM64_INS_LD1 = 279; public static final int ARM64_INS_LD1B = 280; public static final int ARM64_INS_LD1D = 281; public static final int ARM64_INS_LD1H = 282; public static final int ARM64_INS_LD1R = 283; public static final int ARM64_INS_LD1RB = 284; public static final int ARM64_INS_LD1RD = 285; public static final int ARM64_INS_LD1RH = 286; public static final int ARM64_INS_LD1RQB = 287; public static final int ARM64_INS_LD1RQD = 288; public static final int ARM64_INS_LD1RQH = 289; public static final int ARM64_INS_LD1RQW = 290; public static final int ARM64_INS_LD1RSB = 291; public static final int ARM64_INS_LD1RSH = 292; public static final int ARM64_INS_LD1RSW = 293; public static final int ARM64_INS_LD1RW = 294; public static final int ARM64_INS_LD1SB = 295; public static final int ARM64_INS_LD1SH = 296; public static final int ARM64_INS_LD1SW = 297; public static final int ARM64_INS_LD1W = 298; public static final int ARM64_INS_LD2 = 299; public static final int ARM64_INS_LD2B = 300; public static final int ARM64_INS_LD2D = 301; public static final int ARM64_INS_LD2H = 302; public static final int ARM64_INS_LD2R = 303; public static final int ARM64_INS_LD2W = 304; public static final int ARM64_INS_LD3 = 305; public static final int ARM64_INS_LD3B = 306; public static final int ARM64_INS_LD3D = 307; public static final int ARM64_INS_LD3H = 308; public static final int ARM64_INS_LD3R = 309; public static final int ARM64_INS_LD3W = 310; public static final int ARM64_INS_LD4 = 311; public static final int ARM64_INS_LD4B = 312; public static final int ARM64_INS_LD4D = 313; public static final int ARM64_INS_LD4H = 314; public static final int ARM64_INS_LD4R = 315; public static final int ARM64_INS_LD4W = 316; public static final int ARM64_INS_LDADD = 317; public static final int ARM64_INS_LDADDA = 318; public static final int ARM64_INS_LDADDAB = 319; public static final int ARM64_INS_LDADDAH = 320; public static final int ARM64_INS_LDADDAL = 321; public static final int ARM64_INS_LDADDALB = 322; public static final int ARM64_INS_LDADDALH = 323; public static final int ARM64_INS_LDADDB = 324; public static final int ARM64_INS_LDADDH = 325; public static final int ARM64_INS_LDADDL = 326; public static final int ARM64_INS_LDADDLB = 327; public static final int ARM64_INS_LDADDLH = 328; public static final int ARM64_INS_LDAPR = 329; public static final int ARM64_INS_LDAPRB = 330; public static final int ARM64_INS_LDAPRH = 331; public static final int ARM64_INS_LDAPUR = 332; public static final int ARM64_INS_LDAPURB = 333; public static final int ARM64_INS_LDAPURH = 334; public static final int ARM64_INS_LDAPURSB = 335; public static final int ARM64_INS_LDAPURSH = 336; public static final int ARM64_INS_LDAPURSW = 337; public static final int ARM64_INS_LDAR = 338; public static final int ARM64_INS_LDARB = 339; public static final int ARM64_INS_LDARH = 340; public static final int ARM64_INS_LDAXP = 341; public static final int ARM64_INS_LDAXR = 342; public static final int ARM64_INS_LDAXRB = 343; public static final int ARM64_INS_LDAXRH = 344; public static final int ARM64_INS_LDCLR = 345; public static final int ARM64_INS_LDCLRA = 346; public static final int ARM64_INS_LDCLRAB = 347; public static final int ARM64_INS_LDCLRAH = 348; public static final int ARM64_INS_LDCLRAL = 349; public static final int ARM64_INS_LDCLRALB = 350; public static final int ARM64_INS_LDCLRALH = 351; public static final int ARM64_INS_LDCLRB = 352; public static final int ARM64_INS_LDCLRH = 353; public static final int ARM64_INS_LDCLRL = 354; public static final int ARM64_INS_LDCLRLB = 355; public static final int ARM64_INS_LDCLRLH = 356; public static final int ARM64_INS_LDEOR = 357; public static final int ARM64_INS_LDEORA = 358; public static final int ARM64_INS_LDEORAB = 359; public static final int ARM64_INS_LDEORAH = 360; public static final int ARM64_INS_LDEORAL = 361; public static final int ARM64_INS_LDEORALB = 362; public static final int ARM64_INS_LDEORALH = 363; public static final int ARM64_INS_LDEORB = 364; public static final int ARM64_INS_LDEORH = 365; public static final int ARM64_INS_LDEORL = 366; public static final int ARM64_INS_LDEORLB = 367; public static final int ARM64_INS_LDEORLH = 368; public static final int ARM64_INS_LDFF1B = 369; public static final int ARM64_INS_LDFF1D = 370; public static final int ARM64_INS_LDFF1H = 371; public static final int ARM64_INS_LDFF1SB = 372; public static final int ARM64_INS_LDFF1SH = 373; public static final int ARM64_INS_LDFF1SW = 374; public static final int ARM64_INS_LDFF1W = 375; public static final int ARM64_INS_LDLAR = 376; public static final int ARM64_INS_LDLARB = 377; public static final int ARM64_INS_LDLARH = 378; public static final int ARM64_INS_LDNF1B = 379; public static final int ARM64_INS_LDNF1D = 380; public static final int ARM64_INS_LDNF1H = 381; public static final int ARM64_INS_LDNF1SB = 382; public static final int ARM64_INS_LDNF1SH = 383; public static final int ARM64_INS_LDNF1SW = 384; public static final int ARM64_INS_LDNF1W = 385; public static final int ARM64_INS_LDNP = 386; public static final int ARM64_INS_LDNT1B = 387; public static final int ARM64_INS_LDNT1D = 388; public static final int ARM64_INS_LDNT1H = 389; public static final int ARM64_INS_LDNT1W = 390; public static final int ARM64_INS_LDP = 391; public static final int ARM64_INS_LDPSW = 392; public static final int ARM64_INS_LDR = 393; public static final int ARM64_INS_LDRAA = 394; public static final int ARM64_INS_LDRAB = 395; public static final int ARM64_INS_LDRB = 396; public static final int ARM64_INS_LDRH = 397; public static final int ARM64_INS_LDRSB = 398; public static final int ARM64_INS_LDRSH = 399; public static final int ARM64_INS_LDRSW = 400; public static final int ARM64_INS_LDSET = 401; public static final int ARM64_INS_LDSETA = 402; public static final int ARM64_INS_LDSETAB = 403; public static final int ARM64_INS_LDSETAH = 404; public static final int ARM64_INS_LDSETAL = 405; public static final int ARM64_INS_LDSETALB = 406; public static final int ARM64_INS_LDSETALH = 407; public static final int ARM64_INS_LDSETB = 408; public static final int ARM64_INS_LDSETH = 409; public static final int ARM64_INS_LDSETL = 410; public static final int ARM64_INS_LDSETLB = 411; public static final int ARM64_INS_LDSETLH = 412; public static final int ARM64_INS_LDSMAX = 413; public static final int ARM64_INS_LDSMAXA = 414; public static final int ARM64_INS_LDSMAXAB = 415; public static final int ARM64_INS_LDSMAXAH = 416; public static final int ARM64_INS_LDSMAXAL = 417; public static final int ARM64_INS_LDSMAXALB = 418; public static final int ARM64_INS_LDSMAXALH = 419; public static final int ARM64_INS_LDSMAXB = 420; public static final int ARM64_INS_LDSMAXH = 421; public static final int ARM64_INS_LDSMAXL = 422; public static final int ARM64_INS_LDSMAXLB = 423; public static final int ARM64_INS_LDSMAXLH = 424; public static final int ARM64_INS_LDSMIN = 425; public static final int ARM64_INS_LDSMINA = 426; public static final int ARM64_INS_LDSMINAB = 427; public static final int ARM64_INS_LDSMINAH = 428; public static final int ARM64_INS_LDSMINAL = 429; public static final int ARM64_INS_LDSMINALB = 430; public static final int ARM64_INS_LDSMINALH = 431; public static final int ARM64_INS_LDSMINB = 432; public static final int ARM64_INS_LDSMINH = 433; public static final int ARM64_INS_LDSMINL = 434; public static final int ARM64_INS_LDSMINLB = 435; public static final int ARM64_INS_LDSMINLH = 436; public static final int ARM64_INS_LDTR = 437; public static final int ARM64_INS_LDTRB = 438; public static final int ARM64_INS_LDTRH = 439; public static final int ARM64_INS_LDTRSB = 440; public static final int ARM64_INS_LDTRSH = 441; public static final int ARM64_INS_LDTRSW = 442; public static final int ARM64_INS_LDUMAX = 443; public static final int ARM64_INS_LDUMAXA = 444; public static final int ARM64_INS_LDUMAXAB = 445; public static final int ARM64_INS_LDUMAXAH = 446; public static final int ARM64_INS_LDUMAXAL = 447; public static final int ARM64_INS_LDUMAXALB = 448; public static final int ARM64_INS_LDUMAXALH = 449; public static final int ARM64_INS_LDUMAXB = 450; public static final int ARM64_INS_LDUMAXH = 451; public static final int ARM64_INS_LDUMAXL = 452; public static final int ARM64_INS_LDUMAXLB = 453; public static final int ARM64_INS_LDUMAXLH = 454; public static final int ARM64_INS_LDUMIN = 455; public static final int ARM64_INS_LDUMINA = 456; public static final int ARM64_INS_LDUMINAB = 457; public static final int ARM64_INS_LDUMINAH = 458; public static final int ARM64_INS_LDUMINAL = 459; public static final int ARM64_INS_LDUMINALB = 460; public static final int ARM64_INS_LDUMINALH = 461; public static final int ARM64_INS_LDUMINB = 462; public static final int ARM64_INS_LDUMINH = 463; public static final int ARM64_INS_LDUMINL = 464; public static final int ARM64_INS_LDUMINLB = 465; public static final int ARM64_INS_LDUMINLH = 466; public static final int ARM64_INS_LDUR = 467; public static final int ARM64_INS_LDURB = 468; public static final int ARM64_INS_LDURH = 469; public static final int ARM64_INS_LDURSB = 470; public static final int ARM64_INS_LDURSH = 471; public static final int ARM64_INS_LDURSW = 472; public static final int ARM64_INS_LDXP = 473; public static final int ARM64_INS_LDXR = 474; public static final int ARM64_INS_LDXRB = 475; public static final int ARM64_INS_LDXRH = 476; public static final int ARM64_INS_LSL = 477; public static final int ARM64_INS_LSLR = 478; public static final int ARM64_INS_LSLV = 479; public static final int ARM64_INS_LSR = 480; public static final int ARM64_INS_LSRR = 481; public static final int ARM64_INS_LSRV = 482; public static final int ARM64_INS_MAD = 483; public static final int ARM64_INS_MADD = 484; public static final int ARM64_INS_MLA = 485; public static final int ARM64_INS_MLS = 486; public static final int ARM64_INS_MNEG = 487; public static final int ARM64_INS_MOV = 488; public static final int ARM64_INS_MOVI = 489; public static final int ARM64_INS_MOVK = 490; public static final int ARM64_INS_MOVN = 491; public static final int ARM64_INS_MOVPRFX = 492; public static final int ARM64_INS_MOVS = 493; public static final int ARM64_INS_MOVZ = 494; public static final int ARM64_INS_MRS = 495; public static final int ARM64_INS_MSB = 496; public static final int ARM64_INS_MSR = 497; public static final int ARM64_INS_MSUB = 498; public static final int ARM64_INS_MUL = 499; public static final int ARM64_INS_MVN = 500; public static final int ARM64_INS_MVNI = 501; public static final int ARM64_INS_NAND = 502; public static final int ARM64_INS_NANDS = 503; public static final int ARM64_INS_NEG = 504; public static final int ARM64_INS_NEGS = 505; public static final int ARM64_INS_NGC = 506; public static final int ARM64_INS_NGCS = 507; public static final int ARM64_INS_NOP = 508; public static final int ARM64_INS_NOR = 509; public static final int ARM64_INS_NORS = 510; public static final int ARM64_INS_NOT = 511; public static final int ARM64_INS_NOTS = 512; public static final int ARM64_INS_ORN = 513; public static final int ARM64_INS_ORNS = 514; public static final int ARM64_INS_ORR = 515; public static final int ARM64_INS_ORRS = 516; public static final int ARM64_INS_ORV = 517; public static final int ARM64_INS_PACDA = 518; public static final int ARM64_INS_PACDB = 519; public static final int ARM64_INS_PACDZA = 520; public static final int ARM64_INS_PACDZB = 521; public static final int ARM64_INS_PACGA = 522; public static final int ARM64_INS_PACIA = 523; public static final int ARM64_INS_PACIA1716 = 524; public static final int ARM64_INS_PACIASP = 525; public static final int ARM64_INS_PACIAZ = 526; public static final int ARM64_INS_PACIB = 527; public static final int ARM64_INS_PACIB1716 = 528; public static final int ARM64_INS_PACIBSP = 529; public static final int ARM64_INS_PACIBZ = 530; public static final int ARM64_INS_PACIZA = 531; public static final int ARM64_INS_PACIZB = 532; public static final int ARM64_INS_PFALSE = 533; public static final int ARM64_INS_PFIRST = 534; public static final int ARM64_INS_PMUL = 535; public static final int ARM64_INS_PMULL = 536; public static final int ARM64_INS_PMULL2 = 537; public static final int ARM64_INS_PNEXT = 538; public static final int ARM64_INS_PRFB = 539; public static final int ARM64_INS_PRFD = 540; public static final int ARM64_INS_PRFH = 541; public static final int ARM64_INS_PRFM = 542; public static final int ARM64_INS_PRFUM = 543; public static final int ARM64_INS_PRFW = 544; public static final int ARM64_INS_PSB = 545; public static final int ARM64_INS_PTEST = 546; public static final int ARM64_INS_PTRUE = 547; public static final int ARM64_INS_PTRUES = 548; public static final int ARM64_INS_PUNPKHI = 549; public static final int ARM64_INS_PUNPKLO = 550; public static final int ARM64_INS_RADDHN = 551; public static final int ARM64_INS_RADDHN2 = 552; public static final int ARM64_INS_RAX1 = 553; public static final int ARM64_INS_RBIT = 554; public static final int ARM64_INS_RDFFR = 555; public static final int ARM64_INS_RDFFRS = 556; public static final int ARM64_INS_RDVL = 557; public static final int ARM64_INS_RET = 558; public static final int ARM64_INS_RETAA = 559; public static final int ARM64_INS_RETAB = 560; public static final int ARM64_INS_REV = 561; public static final int ARM64_INS_REV16 = 562; public static final int ARM64_INS_REV32 = 563; public static final int ARM64_INS_REV64 = 564; public static final int ARM64_INS_REVB = 565; public static final int ARM64_INS_REVH = 566; public static final int ARM64_INS_REVW = 567; public static final int ARM64_INS_RMIF = 568; public static final int ARM64_INS_ROR = 569; public static final int ARM64_INS_RORV = 570; public static final int ARM64_INS_RSHRN = 571; public static final int ARM64_INS_RSHRN2 = 572; public static final int ARM64_INS_RSUBHN = 573; public static final int ARM64_INS_RSUBHN2 = 574; public static final int ARM64_INS_SABA = 575; public static final int ARM64_INS_SABAL = 576; public static final int ARM64_INS_SABAL2 = 577; public static final int ARM64_INS_SABD = 578; public static final int ARM64_INS_SABDL = 579; public static final int ARM64_INS_SABDL2 = 580; public static final int ARM64_INS_SADALP = 581; public static final int ARM64_INS_SADDL = 582; public static final int ARM64_INS_SADDL2 = 583; public static final int ARM64_INS_SADDLP = 584; public static final int ARM64_INS_SADDLV = 585; public static final int ARM64_INS_SADDV = 586; public static final int ARM64_INS_SADDW = 587; public static final int ARM64_INS_SADDW2 = 588; public static final int ARM64_INS_SBC = 589; public static final int ARM64_INS_SBCS = 590; public static final int ARM64_INS_SBFM = 591; public static final int ARM64_INS_SCVTF = 592; public static final int ARM64_INS_SDIV = 593; public static final int ARM64_INS_SDIVR = 594; public static final int ARM64_INS_SDOT = 595; public static final int ARM64_INS_SEL = 596; public static final int ARM64_INS_SETF16 = 597; public static final int ARM64_INS_SETF8 = 598; public static final int ARM64_INS_SETFFR = 599; public static final int ARM64_INS_SEV = 600; public static final int ARM64_INS_SEVL = 601; public static final int ARM64_INS_SHA1C = 602; public static final int ARM64_INS_SHA1H = 603; public static final int ARM64_INS_SHA1M = 604; public static final int ARM64_INS_SHA1P = 605; public static final int ARM64_INS_SHA1SU0 = 606; public static final int ARM64_INS_SHA1SU1 = 607; public static final int ARM64_INS_SHA256H = 608; public static final int ARM64_INS_SHA256H2 = 609; public static final int ARM64_INS_SHA256SU0 = 610; public static final int ARM64_INS_SHA256SU1 = 611; public static final int ARM64_INS_SHA512H = 612; public static final int ARM64_INS_SHA512H2 = 613; public static final int ARM64_INS_SHA512SU0 = 614; public static final int ARM64_INS_SHA512SU1 = 615; public static final int ARM64_INS_SHADD = 616; public static final int ARM64_INS_SHL = 617; public static final int ARM64_INS_SHLL = 618; public static final int ARM64_INS_SHLL2 = 619; public static final int ARM64_INS_SHRN = 620; public static final int ARM64_INS_SHRN2 = 621; public static final int ARM64_INS_SHSUB = 622; public static final int ARM64_INS_SLI = 623; public static final int ARM64_INS_SM3PARTW1 = 624; public static final int ARM64_INS_SM3PARTW2 = 625; public static final int ARM64_INS_SM3SS1 = 626; public static final int ARM64_INS_SM3TT1A = 627; public static final int ARM64_INS_SM3TT1B = 628; public static final int ARM64_INS_SM3TT2A = 629; public static final int ARM64_INS_SM3TT2B = 630; public static final int ARM64_INS_SM4E = 631; public static final int ARM64_INS_SM4EKEY = 632; public static final int ARM64_INS_SMADDL = 633; public static final int ARM64_INS_SMAX = 634; public static final int ARM64_INS_SMAXP = 635; public static final int ARM64_INS_SMAXV = 636; public static final int ARM64_INS_SMC = 637; public static final int ARM64_INS_SMIN = 638; public static final int ARM64_INS_SMINP = 639; public static final int ARM64_INS_SMINV = 640; public static final int ARM64_INS_SMLAL = 641; public static final int ARM64_INS_SMLAL2 = 642; public static final int ARM64_INS_SMLSL = 643; public static final int ARM64_INS_SMLSL2 = 644; public static final int ARM64_INS_SMNEGL = 645; public static final int ARM64_INS_SMOV = 646; public static final int ARM64_INS_SMSUBL = 647; public static final int ARM64_INS_SMULH = 648; public static final int ARM64_INS_SMULL = 649; public static final int ARM64_INS_SMULL2 = 650; public static final int ARM64_INS_SPLICE = 651; public static final int ARM64_INS_SQABS = 652; public static final int ARM64_INS_SQADD = 653; public static final int ARM64_INS_SQDECB = 654; public static final int ARM64_INS_SQDECD = 655; public static final int ARM64_INS_SQDECH = 656; public static final int ARM64_INS_SQDECP = 657; public static final int ARM64_INS_SQDECW = 658; public static final int ARM64_INS_SQDMLAL = 659; public static final int ARM64_INS_SQDMLAL2 = 660; public static final int ARM64_INS_SQDMLSL = 661; public static final int ARM64_INS_SQDMLSL2 = 662; public static final int ARM64_INS_SQDMULH = 663; public static final int ARM64_INS_SQDMULL = 664; public static final int ARM64_INS_SQDMULL2 = 665; public static final int ARM64_INS_SQINCB = 666; public static final int ARM64_INS_SQINCD = 667; public static final int ARM64_INS_SQINCH = 668; public static final int ARM64_INS_SQINCP = 669; public static final int ARM64_INS_SQINCW = 670; public static final int ARM64_INS_SQNEG = 671; public static final int ARM64_INS_SQRDMLAH = 672; public static final int ARM64_INS_SQRDMLSH = 673; public static final int ARM64_INS_SQRDMULH = 674; public static final int ARM64_INS_SQRSHL = 675; public static final int ARM64_INS_SQRSHRN = 676; public static final int ARM64_INS_SQRSHRN2 = 677; public static final int ARM64_INS_SQRSHRUN = 678; public static final int ARM64_INS_SQRSHRUN2 = 679; public static final int ARM64_INS_SQSHL = 680; public static final int ARM64_INS_SQSHLU = 681; public static final int ARM64_INS_SQSHRN = 682; public static final int ARM64_INS_SQSHRN2 = 683; public static final int ARM64_INS_SQSHRUN = 684; public static final int ARM64_INS_SQSHRUN2 = 685; public static final int ARM64_INS_SQSUB = 686; public static final int ARM64_INS_SQXTN = 687; public static final int ARM64_INS_SQXTN2 = 688; public static final int ARM64_INS_SQXTUN = 689; public static final int ARM64_INS_SQXTUN2 = 690; public static final int ARM64_INS_SRHADD = 691; public static final int ARM64_INS_SRI = 692; public static final int ARM64_INS_SRSHL = 693; public static final int ARM64_INS_SRSHR = 694; public static final int ARM64_INS_SRSRA = 695; public static final int ARM64_INS_SSHL = 696; public static final int ARM64_INS_SSHLL = 697; public static final int ARM64_INS_SSHLL2 = 698; public static final int ARM64_INS_SSHR = 699; public static final int ARM64_INS_SSRA = 700; public static final int ARM64_INS_SSUBL = 701; public static final int ARM64_INS_SSUBL2 = 702; public static final int ARM64_INS_SSUBW = 703; public static final int ARM64_INS_SSUBW2 = 704; public static final int ARM64_INS_ST1 = 705; public static final int ARM64_INS_ST1B = 706; public static final int ARM64_INS_ST1D = 707; public static final int ARM64_INS_ST1H = 708; public static final int ARM64_INS_ST1W = 709; public static final int ARM64_INS_ST2 = 710; public static final int ARM64_INS_ST2B = 711; public static final int ARM64_INS_ST2D = 712; public static final int ARM64_INS_ST2H = 713; public static final int ARM64_INS_ST2W = 714; public static final int ARM64_INS_ST3 = 715; public static final int ARM64_INS_ST3B = 716; public static final int ARM64_INS_ST3D = 717; public static final int ARM64_INS_ST3H = 718; public static final int ARM64_INS_ST3W = 719; public static final int ARM64_INS_ST4 = 720; public static final int ARM64_INS_ST4B = 721; public static final int ARM64_INS_ST4D = 722; public static final int ARM64_INS_ST4H = 723; public static final int ARM64_INS_ST4W = 724; public static final int ARM64_INS_STADD = 725; public static final int ARM64_INS_STADDB = 726; public static final int ARM64_INS_STADDH = 727; public static final int ARM64_INS_STADDL = 728; public static final int ARM64_INS_STADDLB = 729; public static final int ARM64_INS_STADDLH = 730; public static final int ARM64_INS_STCLR = 731; public static final int ARM64_INS_STCLRB = 732; public static final int ARM64_INS_STCLRH = 733; public static final int ARM64_INS_STCLRL = 734; public static final int ARM64_INS_STCLRLB = 735; public static final int ARM64_INS_STCLRLH = 736; public static final int ARM64_INS_STEOR = 737; public static final int ARM64_INS_STEORB = 738; public static final int ARM64_INS_STEORH = 739; public static final int ARM64_INS_STEORL = 740; public static final int ARM64_INS_STEORLB = 741; public static final int ARM64_INS_STEORLH = 742; public static final int ARM64_INS_STLLR = 743; public static final int ARM64_INS_STLLRB = 744; public static final int ARM64_INS_STLLRH = 745; public static final int ARM64_INS_STLR = 746; public static final int ARM64_INS_STLRB = 747; public static final int ARM64_INS_STLRH = 748; public static final int ARM64_INS_STLUR = 749; public static final int ARM64_INS_STLURB = 750; public static final int ARM64_INS_STLURH = 751; public static final int ARM64_INS_STLXP = 752; public static final int ARM64_INS_STLXR = 753; public static final int ARM64_INS_STLXRB = 754; public static final int ARM64_INS_STLXRH = 755; public static final int ARM64_INS_STNP = 756; public static final int ARM64_INS_STNT1B = 757; public static final int ARM64_INS_STNT1D = 758; public static final int ARM64_INS_STNT1H = 759; public static final int ARM64_INS_STNT1W = 760; public static final int ARM64_INS_STP = 761; public static final int ARM64_INS_STR = 762; public static final int ARM64_INS_STRB = 763; public static final int ARM64_INS_STRH = 764; public static final int ARM64_INS_STSET = 765; public static final int ARM64_INS_STSETB = 766; public static final int ARM64_INS_STSETH = 767; public static final int ARM64_INS_STSETL = 768; public static final int ARM64_INS_STSETLB = 769; public static final int ARM64_INS_STSETLH = 770; public static final int ARM64_INS_STSMAX = 771; public static final int ARM64_INS_STSMAXB = 772; public static final int ARM64_INS_STSMAXH = 773; public static final int ARM64_INS_STSMAXL = 774; public static final int ARM64_INS_STSMAXLB = 775; public static final int ARM64_INS_STSMAXLH = 776; public static final int ARM64_INS_STSMIN = 777; public static final int ARM64_INS_STSMINB = 778; public static final int ARM64_INS_STSMINH = 779; public static final int ARM64_INS_STSMINL = 780; public static final int ARM64_INS_STSMINLB = 781; public static final int ARM64_INS_STSMINLH = 782; public static final int ARM64_INS_STTR = 783; public static final int ARM64_INS_STTRB = 784; public static final int ARM64_INS_STTRH = 785; public static final int ARM64_INS_STUMAX = 786; public static final int ARM64_INS_STUMAXB = 787; public static final int ARM64_INS_STUMAXH = 788; public static final int ARM64_INS_STUMAXL = 789; public static final int ARM64_INS_STUMAXLB = 790; public static final int ARM64_INS_STUMAXLH = 791; public static final int ARM64_INS_STUMIN = 792; public static final int ARM64_INS_STUMINB = 793; public static final int ARM64_INS_STUMINH = 794; public static final int ARM64_INS_STUMINL = 795; public static final int ARM64_INS_STUMINLB = 796; public static final int ARM64_INS_STUMINLH = 797; public static final int ARM64_INS_STUR = 798; public static final int ARM64_INS_STURB = 799; public static final int ARM64_INS_STURH = 800; public static final int ARM64_INS_STXP = 801; public static final int ARM64_INS_STXR = 802; public static final int ARM64_INS_STXRB = 803; public static final int ARM64_INS_STXRH = 804; public static final int ARM64_INS_SUB = 805; public static final int ARM64_INS_SUBHN = 806; public static final int ARM64_INS_SUBHN2 = 807; public static final int ARM64_INS_SUBR = 808; public static final int ARM64_INS_SUBS = 809; public static final int ARM64_INS_SUNPKHI = 810; public static final int ARM64_INS_SUNPKLO = 811; public static final int ARM64_INS_SUQADD = 812; public static final int ARM64_INS_SVC = 813; public static final int ARM64_INS_SWP = 814; public static final int ARM64_INS_SWPA = 815; public static final int ARM64_INS_SWPAB = 816; public static final int ARM64_INS_SWPAH = 817; public static final int ARM64_INS_SWPAL = 818; public static final int ARM64_INS_SWPALB = 819; public static final int ARM64_INS_SWPALH = 820; public static final int ARM64_INS_SWPB = 821; public static final int ARM64_INS_SWPH = 822; public static final int ARM64_INS_SWPL = 823; public static final int ARM64_INS_SWPLB = 824; public static final int ARM64_INS_SWPLH = 825; public static final int ARM64_INS_SXTB = 826; public static final int ARM64_INS_SXTH = 827; public static final int ARM64_INS_SXTL = 828; public static final int ARM64_INS_SXTL2 = 829; public static final int ARM64_INS_SXTW = 830; public static final int ARM64_INS_SYS = 831; public static final int ARM64_INS_SYSL = 832; public static final int ARM64_INS_TBL = 833; public static final int ARM64_INS_TBNZ = 834; public static final int ARM64_INS_TBX = 835; public static final int ARM64_INS_TBZ = 836; public static final int ARM64_INS_TRN1 = 837; public static final int ARM64_INS_TRN2 = 838; public static final int ARM64_INS_TSB = 839; public static final int ARM64_INS_TST = 840; public static final int ARM64_INS_UABA = 841; public static final int ARM64_INS_UABAL = 842; public static final int ARM64_INS_UABAL2 = 843; public static final int ARM64_INS_UABD = 844; public static final int ARM64_INS_UABDL = 845; public static final int ARM64_INS_UABDL2 = 846; public static final int ARM64_INS_UADALP = 847; public static final int ARM64_INS_UADDL = 848; public static final int ARM64_INS_UADDL2 = 849; public static final int ARM64_INS_UADDLP = 850; public static final int ARM64_INS_UADDLV = 851; public static final int ARM64_INS_UADDV = 852; public static final int ARM64_INS_UADDW = 853; public static final int ARM64_INS_UADDW2 = 854; public static final int ARM64_INS_UBFM = 855; public static final int ARM64_INS_UCVTF = 856; public static final int ARM64_INS_UDIV = 857; public static final int ARM64_INS_UDIVR = 858; public static final int ARM64_INS_UDOT = 859; public static final int ARM64_INS_UHADD = 860; public static final int ARM64_INS_UHSUB = 861; public static final int ARM64_INS_UMADDL = 862; public static final int ARM64_INS_UMAX = 863; public static final int ARM64_INS_UMAXP = 864; public static final int ARM64_INS_UMAXV = 865; public static final int ARM64_INS_UMIN = 866; public static final int ARM64_INS_UMINP = 867; public static final int ARM64_INS_UMINV = 868; public static final int ARM64_INS_UMLAL = 869; public static final int ARM64_INS_UMLAL2 = 870; public static final int ARM64_INS_UMLSL = 871; public static final int ARM64_INS_UMLSL2 = 872; public static final int ARM64_INS_UMNEGL = 873; public static final int ARM64_INS_UMOV = 874; public static final int ARM64_INS_UMSUBL = 875; public static final int ARM64_INS_UMULH = 876; public static final int ARM64_INS_UMULL = 877; public static final int ARM64_INS_UMULL2 = 878; public static final int ARM64_INS_UQADD = 879; public static final int ARM64_INS_UQDECB = 880; public static final int ARM64_INS_UQDECD = 881; public static final int ARM64_INS_UQDECH = 882; public static final int ARM64_INS_UQDECP = 883; public static final int ARM64_INS_UQDECW = 884; public static final int ARM64_INS_UQINCB = 885; public static final int ARM64_INS_UQINCD = 886; public static final int ARM64_INS_UQINCH = 887; public static final int ARM64_INS_UQINCP = 888; public static final int ARM64_INS_UQINCW = 889; public static final int ARM64_INS_UQRSHL = 890; public static final int ARM64_INS_UQRSHRN = 891; public static final int ARM64_INS_UQRSHRN2 = 892; public static final int ARM64_INS_UQSHL = 893; public static final int ARM64_INS_UQSHRN = 894; public static final int ARM64_INS_UQSHRN2 = 895; public static final int ARM64_INS_UQSUB = 896; public static final int ARM64_INS_UQXTN = 897; public static final int ARM64_INS_UQXTN2 = 898; public static final int ARM64_INS_URECPE = 899; public static final int ARM64_INS_URHADD = 900; public static final int ARM64_INS_URSHL = 901; public static final int ARM64_INS_URSHR = 902; public static final int ARM64_INS_URSQRTE = 903; public static final int ARM64_INS_URSRA = 904; public static final int ARM64_INS_USHL = 905; public static final int ARM64_INS_USHLL = 906; public static final int ARM64_INS_USHLL2 = 907; public static final int ARM64_INS_USHR = 908; public static final int ARM64_INS_USQADD = 909; public static final int ARM64_INS_USRA = 910; public static final int ARM64_INS_USUBL = 911; public static final int ARM64_INS_USUBL2 = 912; public static final int ARM64_INS_USUBW = 913; public static final int ARM64_INS_USUBW2 = 914; public static final int ARM64_INS_UUNPKHI = 915; public static final int ARM64_INS_UUNPKLO = 916; public static final int ARM64_INS_UXTB = 917; public static final int ARM64_INS_UXTH = 918; public static final int ARM64_INS_UXTL = 919; public static final int ARM64_INS_UXTL2 = 920; public static final int ARM64_INS_UXTW = 921; public static final int ARM64_INS_UZP1 = 922; public static final int ARM64_INS_UZP2 = 923; public static final int ARM64_INS_WFE = 924; public static final int ARM64_INS_WFI = 925; public static final int ARM64_INS_WHILELE = 926; public static final int ARM64_INS_WHILELO = 927; public static final int ARM64_INS_WHILELS = 928; public static final int ARM64_INS_WHILELT = 929; public static final int ARM64_INS_WRFFR = 930; public static final int ARM64_INS_XAR = 931; public static final int ARM64_INS_XPACD = 932; public static final int ARM64_INS_XPACI = 933; public static final int ARM64_INS_XPACLRI = 934; public static final int ARM64_INS_XTN = 935; public static final int ARM64_INS_XTN2 = 936; public static final int ARM64_INS_YIELD = 937; public static final int ARM64_INS_ZIP1 = 938; public static final int ARM64_INS_ZIP2 = 939; public static final int ARM64_INS_SBFIZ = 940; public static final int ARM64_INS_UBFIZ = 941; public static final int ARM64_INS_SBFX = 942; public static final int ARM64_INS_UBFX = 943; public static final int ARM64_INS_BFI = 944; public static final int ARM64_INS_BFXIL = 945; public static final int ARM64_INS_IC = 946; public static final int ARM64_INS_DC = 947; public static final int ARM64_INS_AT = 948; public static final int ARM64_INS_TLBI = 949; public static final int ARM64_INS_ENDING = 950; public static final int ARM64_GRP_INVALID = 0; public static final int ARM64_GRP_JUMP = 1; public static final int ARM64_GRP_CALL = 2; public static final int ARM64_GRP_RET = 3; public static final int ARM64_GRP_INT = 4; public static final int ARM64_GRP_PRIVILEGE = 6; public static final int ARM64_GRP_BRANCH_RELATIVE = 7; public static final int ARM64_GRP_PAC = 8; public static final int ARM64_GRP_CRYPTO = 128; public static final int ARM64_GRP_FPARMV8 = 129; public static final int ARM64_GRP_NEON = 130; public static final int ARM64_GRP_CRC = 131; public static final int ARM64_GRP_AES = 132; public static final int ARM64_GRP_DOTPROD = 133; public static final int ARM64_GRP_FULLFP16 = 134; public static final int ARM64_GRP_LSE = 135; public static final int ARM64_GRP_RCPC = 136; public static final int ARM64_GRP_RDM = 137; public static final int ARM64_GRP_SHA2 = 138; public static final int ARM64_GRP_SHA3 = 139; public static final int ARM64_GRP_SM4 = 140; public static final int ARM64_GRP_SVE = 141; public static final int ARM64_GRP_V8_1A = 142; public static final int ARM64_GRP_V8_3A = 143; public static final int ARM64_GRP_V8_4A = 144; public static final int ARM64_GRP_ENDING = 145; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Arm_const.java000064400000000000000000001114540072674642500233330ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Arm_const { public static final int ARM_SFT_INVALID = 0; public static final int ARM_SFT_ASR = 1; public static final int ARM_SFT_LSL = 2; public static final int ARM_SFT_LSR = 3; public static final int ARM_SFT_ROR = 4; public static final int ARM_SFT_RRX = 5; public static final int ARM_SFT_ASR_REG = 6; public static final int ARM_SFT_LSL_REG = 7; public static final int ARM_SFT_LSR_REG = 8; public static final int ARM_SFT_ROR_REG = 9; public static final int ARM_SFT_RRX_REG = 10; public static final int ARM_CC_INVALID = 0; public static final int ARM_CC_EQ = 1; public static final int ARM_CC_NE = 2; public static final int ARM_CC_HS = 3; public static final int ARM_CC_LO = 4; public static final int ARM_CC_MI = 5; public static final int ARM_CC_PL = 6; public static final int ARM_CC_VS = 7; public static final int ARM_CC_VC = 8; public static final int ARM_CC_HI = 9; public static final int ARM_CC_LS = 10; public static final int ARM_CC_GE = 11; public static final int ARM_CC_LT = 12; public static final int ARM_CC_GT = 13; public static final int ARM_CC_LE = 14; public static final int ARM_CC_AL = 15; public static final int ARM_SYSREG_INVALID = 0; public static final int ARM_SYSREG_SPSR_C = 1; public static final int ARM_SYSREG_SPSR_X = 2; public static final int ARM_SYSREG_SPSR_S = 4; public static final int ARM_SYSREG_SPSR_F = 8; public static final int ARM_SYSREG_CPSR_C = 16; public static final int ARM_SYSREG_CPSR_X = 32; public static final int ARM_SYSREG_CPSR_S = 64; public static final int ARM_SYSREG_CPSR_F = 128; public static final int ARM_SYSREG_APSR = 256; public static final int ARM_SYSREG_APSR_G = 257; public static final int ARM_SYSREG_APSR_NZCVQ = 258; public static final int ARM_SYSREG_APSR_NZCVQG = 259; public static final int ARM_SYSREG_IAPSR = 260; public static final int ARM_SYSREG_IAPSR_G = 261; public static final int ARM_SYSREG_IAPSR_NZCVQG = 262; public static final int ARM_SYSREG_IAPSR_NZCVQ = 263; public static final int ARM_SYSREG_EAPSR = 264; public static final int ARM_SYSREG_EAPSR_G = 265; public static final int ARM_SYSREG_EAPSR_NZCVQG = 266; public static final int ARM_SYSREG_EAPSR_NZCVQ = 267; public static final int ARM_SYSREG_XPSR = 268; public static final int ARM_SYSREG_XPSR_G = 269; public static final int ARM_SYSREG_XPSR_NZCVQG = 270; public static final int ARM_SYSREG_XPSR_NZCVQ = 271; public static final int ARM_SYSREG_IPSR = 272; public static final int ARM_SYSREG_EPSR = 273; public static final int ARM_SYSREG_IEPSR = 274; public static final int ARM_SYSREG_MSP = 275; public static final int ARM_SYSREG_PSP = 276; public static final int ARM_SYSREG_PRIMASK = 277; public static final int ARM_SYSREG_BASEPRI = 278; public static final int ARM_SYSREG_BASEPRI_MAX = 279; public static final int ARM_SYSREG_FAULTMASK = 280; public static final int ARM_SYSREG_CONTROL = 281; public static final int ARM_SYSREG_MSPLIM = 282; public static final int ARM_SYSREG_PSPLIM = 283; public static final int ARM_SYSREG_MSP_NS = 284; public static final int ARM_SYSREG_PSP_NS = 285; public static final int ARM_SYSREG_MSPLIM_NS = 286; public static final int ARM_SYSREG_PSPLIM_NS = 287; public static final int ARM_SYSREG_PRIMASK_NS = 288; public static final int ARM_SYSREG_BASEPRI_NS = 289; public static final int ARM_SYSREG_FAULTMASK_NS = 290; public static final int ARM_SYSREG_CONTROL_NS = 291; public static final int ARM_SYSREG_SP_NS = 292; public static final int ARM_SYSREG_R8_USR = 293; public static final int ARM_SYSREG_R9_USR = 294; public static final int ARM_SYSREG_R10_USR = 295; public static final int ARM_SYSREG_R11_USR = 296; public static final int ARM_SYSREG_R12_USR = 297; public static final int ARM_SYSREG_SP_USR = 298; public static final int ARM_SYSREG_LR_USR = 299; public static final int ARM_SYSREG_R8_FIQ = 300; public static final int ARM_SYSREG_R9_FIQ = 301; public static final int ARM_SYSREG_R10_FIQ = 302; public static final int ARM_SYSREG_R11_FIQ = 303; public static final int ARM_SYSREG_R12_FIQ = 304; public static final int ARM_SYSREG_SP_FIQ = 305; public static final int ARM_SYSREG_LR_FIQ = 306; public static final int ARM_SYSREG_LR_IRQ = 307; public static final int ARM_SYSREG_SP_IRQ = 308; public static final int ARM_SYSREG_LR_SVC = 309; public static final int ARM_SYSREG_SP_SVC = 310; public static final int ARM_SYSREG_LR_ABT = 311; public static final int ARM_SYSREG_SP_ABT = 312; public static final int ARM_SYSREG_LR_UND = 313; public static final int ARM_SYSREG_SP_UND = 314; public static final int ARM_SYSREG_LR_MON = 315; public static final int ARM_SYSREG_SP_MON = 316; public static final int ARM_SYSREG_ELR_HYP = 317; public static final int ARM_SYSREG_SP_HYP = 318; public static final int ARM_SYSREG_SPSR_FIQ = 319; public static final int ARM_SYSREG_SPSR_IRQ = 320; public static final int ARM_SYSREG_SPSR_SVC = 321; public static final int ARM_SYSREG_SPSR_ABT = 322; public static final int ARM_SYSREG_SPSR_UND = 323; public static final int ARM_SYSREG_SPSR_MON = 324; public static final int ARM_SYSREG_SPSR_HYP = 325; public static final int ARM_MB_INVALID = 0; public static final int ARM_MB_RESERVED_0 = 1; public static final int ARM_MB_OSHLD = 2; public static final int ARM_MB_OSHST = 3; public static final int ARM_MB_OSH = 4; public static final int ARM_MB_RESERVED_4 = 5; public static final int ARM_MB_NSHLD = 6; public static final int ARM_MB_NSHST = 7; public static final int ARM_MB_NSH = 8; public static final int ARM_MB_RESERVED_8 = 9; public static final int ARM_MB_ISHLD = 10; public static final int ARM_MB_ISHST = 11; public static final int ARM_MB_ISH = 12; public static final int ARM_MB_RESERVED_12 = 13; public static final int ARM_MB_LD = 14; public static final int ARM_MB_ST = 15; public static final int ARM_MB_SY = 16; public static final int ARM_OP_INVALID = 0; public static final int ARM_OP_REG = 1; public static final int ARM_OP_IMM = 2; public static final int ARM_OP_MEM = 3; public static final int ARM_OP_FP = 4; public static final int ARM_OP_CIMM = 64; public static final int ARM_OP_PIMM = 65; public static final int ARM_OP_SETEND = 66; public static final int ARM_OP_SYSREG = 67; public static final int ARM_SETEND_INVALID = 0; public static final int ARM_SETEND_BE = 1; public static final int ARM_SETEND_LE = 2; public static final int ARM_CPSMODE_INVALID = 0; public static final int ARM_CPSMODE_IE = 2; public static final int ARM_CPSMODE_ID = 3; public static final int ARM_CPSFLAG_INVALID = 0; public static final int ARM_CPSFLAG_F = 1; public static final int ARM_CPSFLAG_I = 2; public static final int ARM_CPSFLAG_A = 4; public static final int ARM_CPSFLAG_NONE = 16; public static final int ARM_VECTORDATA_INVALID = 0; public static final int ARM_VECTORDATA_I8 = 1; public static final int ARM_VECTORDATA_I16 = 2; public static final int ARM_VECTORDATA_I32 = 3; public static final int ARM_VECTORDATA_I64 = 4; public static final int ARM_VECTORDATA_S8 = 5; public static final int ARM_VECTORDATA_S16 = 6; public static final int ARM_VECTORDATA_S32 = 7; public static final int ARM_VECTORDATA_S64 = 8; public static final int ARM_VECTORDATA_U8 = 9; public static final int ARM_VECTORDATA_U16 = 10; public static final int ARM_VECTORDATA_U32 = 11; public static final int ARM_VECTORDATA_U64 = 12; public static final int ARM_VECTORDATA_P8 = 13; public static final int ARM_VECTORDATA_F16 = 14; public static final int ARM_VECTORDATA_F32 = 15; public static final int ARM_VECTORDATA_F64 = 16; public static final int ARM_VECTORDATA_F16F64 = 17; public static final int ARM_VECTORDATA_F64F16 = 18; public static final int ARM_VECTORDATA_F32F16 = 19; public static final int ARM_VECTORDATA_F16F32 = 20; public static final int ARM_VECTORDATA_F64F32 = 21; public static final int ARM_VECTORDATA_F32F64 = 22; public static final int ARM_VECTORDATA_S32F32 = 23; public static final int ARM_VECTORDATA_U32F32 = 24; public static final int ARM_VECTORDATA_F32S32 = 25; public static final int ARM_VECTORDATA_F32U32 = 26; public static final int ARM_VECTORDATA_F64S16 = 27; public static final int ARM_VECTORDATA_F32S16 = 28; public static final int ARM_VECTORDATA_F64S32 = 29; public static final int ARM_VECTORDATA_S16F64 = 30; public static final int ARM_VECTORDATA_S16F32 = 31; public static final int ARM_VECTORDATA_S32F64 = 32; public static final int ARM_VECTORDATA_U16F64 = 33; public static final int ARM_VECTORDATA_U16F32 = 34; public static final int ARM_VECTORDATA_U32F64 = 35; public static final int ARM_VECTORDATA_F64U16 = 36; public static final int ARM_VECTORDATA_F32U16 = 37; public static final int ARM_VECTORDATA_F64U32 = 38; public static final int ARM_VECTORDATA_F16U16 = 39; public static final int ARM_VECTORDATA_U16F16 = 40; public static final int ARM_VECTORDATA_F16U32 = 41; public static final int ARM_VECTORDATA_U32F16 = 42; public static final int ARM_REG_INVALID = 0; public static final int ARM_REG_APSR = 1; public static final int ARM_REG_APSR_NZCV = 2; public static final int ARM_REG_CPSR = 3; public static final int ARM_REG_FPEXC = 4; public static final int ARM_REG_FPINST = 5; public static final int ARM_REG_FPSCR = 6; public static final int ARM_REG_FPSCR_NZCV = 7; public static final int ARM_REG_FPSID = 8; public static final int ARM_REG_ITSTATE = 9; public static final int ARM_REG_LR = 10; public static final int ARM_REG_PC = 11; public static final int ARM_REG_SP = 12; public static final int ARM_REG_SPSR = 13; public static final int ARM_REG_D0 = 14; public static final int ARM_REG_D1 = 15; public static final int ARM_REG_D2 = 16; public static final int ARM_REG_D3 = 17; public static final int ARM_REG_D4 = 18; public static final int ARM_REG_D5 = 19; public static final int ARM_REG_D6 = 20; public static final int ARM_REG_D7 = 21; public static final int ARM_REG_D8 = 22; public static final int ARM_REG_D9 = 23; public static final int ARM_REG_D10 = 24; public static final int ARM_REG_D11 = 25; public static final int ARM_REG_D12 = 26; public static final int ARM_REG_D13 = 27; public static final int ARM_REG_D14 = 28; public static final int ARM_REG_D15 = 29; public static final int ARM_REG_D16 = 30; public static final int ARM_REG_D17 = 31; public static final int ARM_REG_D18 = 32; public static final int ARM_REG_D19 = 33; public static final int ARM_REG_D20 = 34; public static final int ARM_REG_D21 = 35; public static final int ARM_REG_D22 = 36; public static final int ARM_REG_D23 = 37; public static final int ARM_REG_D24 = 38; public static final int ARM_REG_D25 = 39; public static final int ARM_REG_D26 = 40; public static final int ARM_REG_D27 = 41; public static final int ARM_REG_D28 = 42; public static final int ARM_REG_D29 = 43; public static final int ARM_REG_D30 = 44; public static final int ARM_REG_D31 = 45; public static final int ARM_REG_FPINST2 = 46; public static final int ARM_REG_MVFR0 = 47; public static final int ARM_REG_MVFR1 = 48; public static final int ARM_REG_MVFR2 = 49; public static final int ARM_REG_Q0 = 50; public static final int ARM_REG_Q1 = 51; public static final int ARM_REG_Q2 = 52; public static final int ARM_REG_Q3 = 53; public static final int ARM_REG_Q4 = 54; public static final int ARM_REG_Q5 = 55; public static final int ARM_REG_Q6 = 56; public static final int ARM_REG_Q7 = 57; public static final int ARM_REG_Q8 = 58; public static final int ARM_REG_Q9 = 59; public static final int ARM_REG_Q10 = 60; public static final int ARM_REG_Q11 = 61; public static final int ARM_REG_Q12 = 62; public static final int ARM_REG_Q13 = 63; public static final int ARM_REG_Q14 = 64; public static final int ARM_REG_Q15 = 65; public static final int ARM_REG_R0 = 66; public static final int ARM_REG_R1 = 67; public static final int ARM_REG_R2 = 68; public static final int ARM_REG_R3 = 69; public static final int ARM_REG_R4 = 70; public static final int ARM_REG_R5 = 71; public static final int ARM_REG_R6 = 72; public static final int ARM_REG_R7 = 73; public static final int ARM_REG_R8 = 74; public static final int ARM_REG_R9 = 75; public static final int ARM_REG_R10 = 76; public static final int ARM_REG_R11 = 77; public static final int ARM_REG_R12 = 78; public static final int ARM_REG_S0 = 79; public static final int ARM_REG_S1 = 80; public static final int ARM_REG_S2 = 81; public static final int ARM_REG_S3 = 82; public static final int ARM_REG_S4 = 83; public static final int ARM_REG_S5 = 84; public static final int ARM_REG_S6 = 85; public static final int ARM_REG_S7 = 86; public static final int ARM_REG_S8 = 87; public static final int ARM_REG_S9 = 88; public static final int ARM_REG_S10 = 89; public static final int ARM_REG_S11 = 90; public static final int ARM_REG_S12 = 91; public static final int ARM_REG_S13 = 92; public static final int ARM_REG_S14 = 93; public static final int ARM_REG_S15 = 94; public static final int ARM_REG_S16 = 95; public static final int ARM_REG_S17 = 96; public static final int ARM_REG_S18 = 97; public static final int ARM_REG_S19 = 98; public static final int ARM_REG_S20 = 99; public static final int ARM_REG_S21 = 100; public static final int ARM_REG_S22 = 101; public static final int ARM_REG_S23 = 102; public static final int ARM_REG_S24 = 103; public static final int ARM_REG_S25 = 104; public static final int ARM_REG_S26 = 105; public static final int ARM_REG_S27 = 106; public static final int ARM_REG_S28 = 107; public static final int ARM_REG_S29 = 108; public static final int ARM_REG_S30 = 109; public static final int ARM_REG_S31 = 110; public static final int ARM_REG_ENDING = 111; public static final int ARM_REG_R13 = ARM_REG_SP; public static final int ARM_REG_R14 = ARM_REG_LR; public static final int ARM_REG_R15 = ARM_REG_PC; public static final int ARM_REG_SB = ARM_REG_R9; public static final int ARM_REG_SL = ARM_REG_R10; public static final int ARM_REG_FP = ARM_REG_R11; public static final int ARM_REG_IP = ARM_REG_R12; public static final int ARM_INS_INVALID = 0; public static final int ARM_INS_ADC = 1; public static final int ARM_INS_ADD = 2; public static final int ARM_INS_ADDW = 3; public static final int ARM_INS_ADR = 4; public static final int ARM_INS_AESD = 5; public static final int ARM_INS_AESE = 6; public static final int ARM_INS_AESIMC = 7; public static final int ARM_INS_AESMC = 8; public static final int ARM_INS_AND = 9; public static final int ARM_INS_ASR = 10; public static final int ARM_INS_B = 11; public static final int ARM_INS_BFC = 12; public static final int ARM_INS_BFI = 13; public static final int ARM_INS_BIC = 14; public static final int ARM_INS_BKPT = 15; public static final int ARM_INS_BL = 16; public static final int ARM_INS_BLX = 17; public static final int ARM_INS_BLXNS = 18; public static final int ARM_INS_BX = 19; public static final int ARM_INS_BXJ = 20; public static final int ARM_INS_BXNS = 21; public static final int ARM_INS_CBNZ = 22; public static final int ARM_INS_CBZ = 23; public static final int ARM_INS_CDP = 24; public static final int ARM_INS_CDP2 = 25; public static final int ARM_INS_CLREX = 26; public static final int ARM_INS_CLZ = 27; public static final int ARM_INS_CMN = 28; public static final int ARM_INS_CMP = 29; public static final int ARM_INS_CPS = 30; public static final int ARM_INS_CRC32B = 31; public static final int ARM_INS_CRC32CB = 32; public static final int ARM_INS_CRC32CH = 33; public static final int ARM_INS_CRC32CW = 34; public static final int ARM_INS_CRC32H = 35; public static final int ARM_INS_CRC32W = 36; public static final int ARM_INS_CSDB = 37; public static final int ARM_INS_DBG = 38; public static final int ARM_INS_DCPS1 = 39; public static final int ARM_INS_DCPS2 = 40; public static final int ARM_INS_DCPS3 = 41; public static final int ARM_INS_DFB = 42; public static final int ARM_INS_DMB = 43; public static final int ARM_INS_DSB = 44; public static final int ARM_INS_EOR = 45; public static final int ARM_INS_ERET = 46; public static final int ARM_INS_ESB = 47; public static final int ARM_INS_FADDD = 48; public static final int ARM_INS_FADDS = 49; public static final int ARM_INS_FCMPZD = 50; public static final int ARM_INS_FCMPZS = 51; public static final int ARM_INS_FCONSTD = 52; public static final int ARM_INS_FCONSTS = 53; public static final int ARM_INS_FLDMDBX = 54; public static final int ARM_INS_FLDMIAX = 55; public static final int ARM_INS_FMDHR = 56; public static final int ARM_INS_FMDLR = 57; public static final int ARM_INS_FMSTAT = 58; public static final int ARM_INS_FSTMDBX = 59; public static final int ARM_INS_FSTMIAX = 60; public static final int ARM_INS_FSUBD = 61; public static final int ARM_INS_FSUBS = 62; public static final int ARM_INS_HINT = 63; public static final int ARM_INS_HLT = 64; public static final int ARM_INS_HVC = 65; public static final int ARM_INS_ISB = 66; public static final int ARM_INS_IT = 67; public static final int ARM_INS_LDA = 68; public static final int ARM_INS_LDAB = 69; public static final int ARM_INS_LDAEX = 70; public static final int ARM_INS_LDAEXB = 71; public static final int ARM_INS_LDAEXD = 72; public static final int ARM_INS_LDAEXH = 73; public static final int ARM_INS_LDAH = 74; public static final int ARM_INS_LDC = 75; public static final int ARM_INS_LDC2 = 76; public static final int ARM_INS_LDC2L = 77; public static final int ARM_INS_LDCL = 78; public static final int ARM_INS_LDM = 79; public static final int ARM_INS_LDMDA = 80; public static final int ARM_INS_LDMDB = 81; public static final int ARM_INS_LDMIB = 82; public static final int ARM_INS_LDR = 83; public static final int ARM_INS_LDRB = 84; public static final int ARM_INS_LDRBT = 85; public static final int ARM_INS_LDRD = 86; public static final int ARM_INS_LDREX = 87; public static final int ARM_INS_LDREXB = 88; public static final int ARM_INS_LDREXD = 89; public static final int ARM_INS_LDREXH = 90; public static final int ARM_INS_LDRH = 91; public static final int ARM_INS_LDRHT = 92; public static final int ARM_INS_LDRSB = 93; public static final int ARM_INS_LDRSBT = 94; public static final int ARM_INS_LDRSH = 95; public static final int ARM_INS_LDRSHT = 96; public static final int ARM_INS_LDRT = 97; public static final int ARM_INS_LSL = 98; public static final int ARM_INS_LSR = 99; public static final int ARM_INS_MCR = 100; public static final int ARM_INS_MCR2 = 101; public static final int ARM_INS_MCRR = 102; public static final int ARM_INS_MCRR2 = 103; public static final int ARM_INS_MLA = 104; public static final int ARM_INS_MLS = 105; public static final int ARM_INS_MOV = 106; public static final int ARM_INS_MOVS = 107; public static final int ARM_INS_MOVT = 108; public static final int ARM_INS_MOVW = 109; public static final int ARM_INS_MRC = 110; public static final int ARM_INS_MRC2 = 111; public static final int ARM_INS_MRRC = 112; public static final int ARM_INS_MRRC2 = 113; public static final int ARM_INS_MRS = 114; public static final int ARM_INS_MSR = 115; public static final int ARM_INS_MUL = 116; public static final int ARM_INS_MVN = 117; public static final int ARM_INS_NEG = 118; public static final int ARM_INS_NOP = 119; public static final int ARM_INS_ORN = 120; public static final int ARM_INS_ORR = 121; public static final int ARM_INS_PKHBT = 122; public static final int ARM_INS_PKHTB = 123; public static final int ARM_INS_PLD = 124; public static final int ARM_INS_PLDW = 125; public static final int ARM_INS_PLI = 126; public static final int ARM_INS_POP = 127; public static final int ARM_INS_PUSH = 128; public static final int ARM_INS_QADD = 129; public static final int ARM_INS_QADD16 = 130; public static final int ARM_INS_QADD8 = 131; public static final int ARM_INS_QASX = 132; public static final int ARM_INS_QDADD = 133; public static final int ARM_INS_QDSUB = 134; public static final int ARM_INS_QSAX = 135; public static final int ARM_INS_QSUB = 136; public static final int ARM_INS_QSUB16 = 137; public static final int ARM_INS_QSUB8 = 138; public static final int ARM_INS_RBIT = 139; public static final int ARM_INS_REV = 140; public static final int ARM_INS_REV16 = 141; public static final int ARM_INS_REVSH = 142; public static final int ARM_INS_RFEDA = 143; public static final int ARM_INS_RFEDB = 144; public static final int ARM_INS_RFEIA = 145; public static final int ARM_INS_RFEIB = 146; public static final int ARM_INS_ROR = 147; public static final int ARM_INS_RRX = 148; public static final int ARM_INS_RSB = 149; public static final int ARM_INS_RSC = 150; public static final int ARM_INS_SADD16 = 151; public static final int ARM_INS_SADD8 = 152; public static final int ARM_INS_SASX = 153; public static final int ARM_INS_SBC = 154; public static final int ARM_INS_SBFX = 155; public static final int ARM_INS_SDIV = 156; public static final int ARM_INS_SEL = 157; public static final int ARM_INS_SETEND = 158; public static final int ARM_INS_SETPAN = 159; public static final int ARM_INS_SEV = 160; public static final int ARM_INS_SEVL = 161; public static final int ARM_INS_SG = 162; public static final int ARM_INS_SHA1C = 163; public static final int ARM_INS_SHA1H = 164; public static final int ARM_INS_SHA1M = 165; public static final int ARM_INS_SHA1P = 166; public static final int ARM_INS_SHA1SU0 = 167; public static final int ARM_INS_SHA1SU1 = 168; public static final int ARM_INS_SHA256H = 169; public static final int ARM_INS_SHA256H2 = 170; public static final int ARM_INS_SHA256SU0 = 171; public static final int ARM_INS_SHA256SU1 = 172; public static final int ARM_INS_SHADD16 = 173; public static final int ARM_INS_SHADD8 = 174; public static final int ARM_INS_SHASX = 175; public static final int ARM_INS_SHSAX = 176; public static final int ARM_INS_SHSUB16 = 177; public static final int ARM_INS_SHSUB8 = 178; public static final int ARM_INS_SMC = 179; public static final int ARM_INS_SMLABB = 180; public static final int ARM_INS_SMLABT = 181; public static final int ARM_INS_SMLAD = 182; public static final int ARM_INS_SMLADX = 183; public static final int ARM_INS_SMLAL = 184; public static final int ARM_INS_SMLALBB = 185; public static final int ARM_INS_SMLALBT = 186; public static final int ARM_INS_SMLALD = 187; public static final int ARM_INS_SMLALDX = 188; public static final int ARM_INS_SMLALTB = 189; public static final int ARM_INS_SMLALTT = 190; public static final int ARM_INS_SMLATB = 191; public static final int ARM_INS_SMLATT = 192; public static final int ARM_INS_SMLAWB = 193; public static final int ARM_INS_SMLAWT = 194; public static final int ARM_INS_SMLSD = 195; public static final int ARM_INS_SMLSDX = 196; public static final int ARM_INS_SMLSLD = 197; public static final int ARM_INS_SMLSLDX = 198; public static final int ARM_INS_SMMLA = 199; public static final int ARM_INS_SMMLAR = 200; public static final int ARM_INS_SMMLS = 201; public static final int ARM_INS_SMMLSR = 202; public static final int ARM_INS_SMMUL = 203; public static final int ARM_INS_SMMULR = 204; public static final int ARM_INS_SMUAD = 205; public static final int ARM_INS_SMUADX = 206; public static final int ARM_INS_SMULBB = 207; public static final int ARM_INS_SMULBT = 208; public static final int ARM_INS_SMULL = 209; public static final int ARM_INS_SMULTB = 210; public static final int ARM_INS_SMULTT = 211; public static final int ARM_INS_SMULWB = 212; public static final int ARM_INS_SMULWT = 213; public static final int ARM_INS_SMUSD = 214; public static final int ARM_INS_SMUSDX = 215; public static final int ARM_INS_SRSDA = 216; public static final int ARM_INS_SRSDB = 217; public static final int ARM_INS_SRSIA = 218; public static final int ARM_INS_SRSIB = 219; public static final int ARM_INS_SSAT = 220; public static final int ARM_INS_SSAT16 = 221; public static final int ARM_INS_SSAX = 222; public static final int ARM_INS_SSUB16 = 223; public static final int ARM_INS_SSUB8 = 224; public static final int ARM_INS_STC = 225; public static final int ARM_INS_STC2 = 226; public static final int ARM_INS_STC2L = 227; public static final int ARM_INS_STCL = 228; public static final int ARM_INS_STL = 229; public static final int ARM_INS_STLB = 230; public static final int ARM_INS_STLEX = 231; public static final int ARM_INS_STLEXB = 232; public static final int ARM_INS_STLEXD = 233; public static final int ARM_INS_STLEXH = 234; public static final int ARM_INS_STLH = 235; public static final int ARM_INS_STM = 236; public static final int ARM_INS_STMDA = 237; public static final int ARM_INS_STMDB = 238; public static final int ARM_INS_STMIB = 239; public static final int ARM_INS_STR = 240; public static final int ARM_INS_STRB = 241; public static final int ARM_INS_STRBT = 242; public static final int ARM_INS_STRD = 243; public static final int ARM_INS_STREX = 244; public static final int ARM_INS_STREXB = 245; public static final int ARM_INS_STREXD = 246; public static final int ARM_INS_STREXH = 247; public static final int ARM_INS_STRH = 248; public static final int ARM_INS_STRHT = 249; public static final int ARM_INS_STRT = 250; public static final int ARM_INS_SUB = 251; public static final int ARM_INS_SUBS = 252; public static final int ARM_INS_SUBW = 253; public static final int ARM_INS_SVC = 254; public static final int ARM_INS_SWP = 255; public static final int ARM_INS_SWPB = 256; public static final int ARM_INS_SXTAB = 257; public static final int ARM_INS_SXTAB16 = 258; public static final int ARM_INS_SXTAH = 259; public static final int ARM_INS_SXTB = 260; public static final int ARM_INS_SXTB16 = 261; public static final int ARM_INS_SXTH = 262; public static final int ARM_INS_TBB = 263; public static final int ARM_INS_TBH = 264; public static final int ARM_INS_TEQ = 265; public static final int ARM_INS_TRAP = 266; public static final int ARM_INS_TSB = 267; public static final int ARM_INS_TST = 268; public static final int ARM_INS_TT = 269; public static final int ARM_INS_TTA = 270; public static final int ARM_INS_TTAT = 271; public static final int ARM_INS_TTT = 272; public static final int ARM_INS_UADD16 = 273; public static final int ARM_INS_UADD8 = 274; public static final int ARM_INS_UASX = 275; public static final int ARM_INS_UBFX = 276; public static final int ARM_INS_UDF = 277; public static final int ARM_INS_UDIV = 278; public static final int ARM_INS_UHADD16 = 279; public static final int ARM_INS_UHADD8 = 280; public static final int ARM_INS_UHASX = 281; public static final int ARM_INS_UHSAX = 282; public static final int ARM_INS_UHSUB16 = 283; public static final int ARM_INS_UHSUB8 = 284; public static final int ARM_INS_UMAAL = 285; public static final int ARM_INS_UMLAL = 286; public static final int ARM_INS_UMULL = 287; public static final int ARM_INS_UQADD16 = 288; public static final int ARM_INS_UQADD8 = 289; public static final int ARM_INS_UQASX = 290; public static final int ARM_INS_UQSAX = 291; public static final int ARM_INS_UQSUB16 = 292; public static final int ARM_INS_UQSUB8 = 293; public static final int ARM_INS_USAD8 = 294; public static final int ARM_INS_USADA8 = 295; public static final int ARM_INS_USAT = 296; public static final int ARM_INS_USAT16 = 297; public static final int ARM_INS_USAX = 298; public static final int ARM_INS_USUB16 = 299; public static final int ARM_INS_USUB8 = 300; public static final int ARM_INS_UXTAB = 301; public static final int ARM_INS_UXTAB16 = 302; public static final int ARM_INS_UXTAH = 303; public static final int ARM_INS_UXTB = 304; public static final int ARM_INS_UXTB16 = 305; public static final int ARM_INS_UXTH = 306; public static final int ARM_INS_VABA = 307; public static final int ARM_INS_VABAL = 308; public static final int ARM_INS_VABD = 309; public static final int ARM_INS_VABDL = 310; public static final int ARM_INS_VABS = 311; public static final int ARM_INS_VACGE = 312; public static final int ARM_INS_VACGT = 313; public static final int ARM_INS_VACLE = 314; public static final int ARM_INS_VACLT = 315; public static final int ARM_INS_VADD = 316; public static final int ARM_INS_VADDHN = 317; public static final int ARM_INS_VADDL = 318; public static final int ARM_INS_VADDW = 319; public static final int ARM_INS_VAND = 320; public static final int ARM_INS_VBIC = 321; public static final int ARM_INS_VBIF = 322; public static final int ARM_INS_VBIT = 323; public static final int ARM_INS_VBSL = 324; public static final int ARM_INS_VCADD = 325; public static final int ARM_INS_VCEQ = 326; public static final int ARM_INS_VCGE = 327; public static final int ARM_INS_VCGT = 328; public static final int ARM_INS_VCLE = 329; public static final int ARM_INS_VCLS = 330; public static final int ARM_INS_VCLT = 331; public static final int ARM_INS_VCLZ = 332; public static final int ARM_INS_VCMLA = 333; public static final int ARM_INS_VCMP = 334; public static final int ARM_INS_VCMPE = 335; public static final int ARM_INS_VCNT = 336; public static final int ARM_INS_VCVT = 337; public static final int ARM_INS_VCVTA = 338; public static final int ARM_INS_VCVTB = 339; public static final int ARM_INS_VCVTM = 340; public static final int ARM_INS_VCVTN = 341; public static final int ARM_INS_VCVTP = 342; public static final int ARM_INS_VCVTR = 343; public static final int ARM_INS_VCVTT = 344; public static final int ARM_INS_VDIV = 345; public static final int ARM_INS_VDUP = 346; public static final int ARM_INS_VEOR = 347; public static final int ARM_INS_VEXT = 348; public static final int ARM_INS_VFMA = 349; public static final int ARM_INS_VFMS = 350; public static final int ARM_INS_VFNMA = 351; public static final int ARM_INS_VFNMS = 352; public static final int ARM_INS_VHADD = 353; public static final int ARM_INS_VHSUB = 354; public static final int ARM_INS_VINS = 355; public static final int ARM_INS_VJCVT = 356; public static final int ARM_INS_VLD1 = 357; public static final int ARM_INS_VLD2 = 358; public static final int ARM_INS_VLD3 = 359; public static final int ARM_INS_VLD4 = 360; public static final int ARM_INS_VLDMDB = 361; public static final int ARM_INS_VLDMIA = 362; public static final int ARM_INS_VLDR = 363; public static final int ARM_INS_VLLDM = 364; public static final int ARM_INS_VLSTM = 365; public static final int ARM_INS_VMAX = 366; public static final int ARM_INS_VMAXNM = 367; public static final int ARM_INS_VMIN = 368; public static final int ARM_INS_VMINNM = 369; public static final int ARM_INS_VMLA = 370; public static final int ARM_INS_VMLAL = 371; public static final int ARM_INS_VMLS = 372; public static final int ARM_INS_VMLSL = 373; public static final int ARM_INS_VMOV = 374; public static final int ARM_INS_VMOVL = 375; public static final int ARM_INS_VMOVN = 376; public static final int ARM_INS_VMOVX = 377; public static final int ARM_INS_VMRS = 378; public static final int ARM_INS_VMSR = 379; public static final int ARM_INS_VMUL = 380; public static final int ARM_INS_VMULL = 381; public static final int ARM_INS_VMVN = 382; public static final int ARM_INS_VNEG = 383; public static final int ARM_INS_VNMLA = 384; public static final int ARM_INS_VNMLS = 385; public static final int ARM_INS_VNMUL = 386; public static final int ARM_INS_VORN = 387; public static final int ARM_INS_VORR = 388; public static final int ARM_INS_VPADAL = 389; public static final int ARM_INS_VPADD = 390; public static final int ARM_INS_VPADDL = 391; public static final int ARM_INS_VPMAX = 392; public static final int ARM_INS_VPMIN = 393; public static final int ARM_INS_VPOP = 394; public static final int ARM_INS_VPUSH = 395; public static final int ARM_INS_VQABS = 396; public static final int ARM_INS_VQADD = 397; public static final int ARM_INS_VQDMLAL = 398; public static final int ARM_INS_VQDMLSL = 399; public static final int ARM_INS_VQDMULH = 400; public static final int ARM_INS_VQDMULL = 401; public static final int ARM_INS_VQMOVN = 402; public static final int ARM_INS_VQMOVUN = 403; public static final int ARM_INS_VQNEG = 404; public static final int ARM_INS_VQRDMLAH = 405; public static final int ARM_INS_VQRDMLSH = 406; public static final int ARM_INS_VQRDMULH = 407; public static final int ARM_INS_VQRSHL = 408; public static final int ARM_INS_VQRSHRN = 409; public static final int ARM_INS_VQRSHRUN = 410; public static final int ARM_INS_VQSHL = 411; public static final int ARM_INS_VQSHLU = 412; public static final int ARM_INS_VQSHRN = 413; public static final int ARM_INS_VQSHRUN = 414; public static final int ARM_INS_VQSUB = 415; public static final int ARM_INS_VRADDHN = 416; public static final int ARM_INS_VRECPE = 417; public static final int ARM_INS_VRECPS = 418; public static final int ARM_INS_VREV16 = 419; public static final int ARM_INS_VREV32 = 420; public static final int ARM_INS_VREV64 = 421; public static final int ARM_INS_VRHADD = 422; public static final int ARM_INS_VRINTA = 423; public static final int ARM_INS_VRINTM = 424; public static final int ARM_INS_VRINTN = 425; public static final int ARM_INS_VRINTP = 426; public static final int ARM_INS_VRINTR = 427; public static final int ARM_INS_VRINTX = 428; public static final int ARM_INS_VRINTZ = 429; public static final int ARM_INS_VRSHL = 430; public static final int ARM_INS_VRSHR = 431; public static final int ARM_INS_VRSHRN = 432; public static final int ARM_INS_VRSQRTE = 433; public static final int ARM_INS_VRSQRTS = 434; public static final int ARM_INS_VRSRA = 435; public static final int ARM_INS_VRSUBHN = 436; public static final int ARM_INS_VSDOT = 437; public static final int ARM_INS_VSELEQ = 438; public static final int ARM_INS_VSELGE = 439; public static final int ARM_INS_VSELGT = 440; public static final int ARM_INS_VSELVS = 441; public static final int ARM_INS_VSHL = 442; public static final int ARM_INS_VSHLL = 443; public static final int ARM_INS_VSHR = 444; public static final int ARM_INS_VSHRN = 445; public static final int ARM_INS_VSLI = 446; public static final int ARM_INS_VSQRT = 447; public static final int ARM_INS_VSRA = 448; public static final int ARM_INS_VSRI = 449; public static final int ARM_INS_VST1 = 450; public static final int ARM_INS_VST2 = 451; public static final int ARM_INS_VST3 = 452; public static final int ARM_INS_VST4 = 453; public static final int ARM_INS_VSTMDB = 454; public static final int ARM_INS_VSTMIA = 455; public static final int ARM_INS_VSTR = 456; public static final int ARM_INS_VSUB = 457; public static final int ARM_INS_VSUBHN = 458; public static final int ARM_INS_VSUBL = 459; public static final int ARM_INS_VSUBW = 460; public static final int ARM_INS_VSWP = 461; public static final int ARM_INS_VTBL = 462; public static final int ARM_INS_VTBX = 463; public static final int ARM_INS_VTRN = 464; public static final int ARM_INS_VTST = 465; public static final int ARM_INS_VUDOT = 466; public static final int ARM_INS_VUZP = 467; public static final int ARM_INS_VZIP = 468; public static final int ARM_INS_WFE = 469; public static final int ARM_INS_WFI = 470; public static final int ARM_INS_YIELD = 471; public static final int ARM_INS_ENDING = 472; public static final int ARM_GRP_INVALID = 0; public static final int ARM_GRP_JUMP = 1; public static final int ARM_GRP_CALL = 2; public static final int ARM_GRP_INT = 4; public static final int ARM_GRP_PRIVILEGE = 6; public static final int ARM_GRP_BRANCH_RELATIVE = 7; public static final int ARM_GRP_CRYPTO = 128; public static final int ARM_GRP_DATABARRIER = 129; public static final int ARM_GRP_DIVIDE = 130; public static final int ARM_GRP_FPARMV8 = 131; public static final int ARM_GRP_MULTPRO = 132; public static final int ARM_GRP_NEON = 133; public static final int ARM_GRP_T2EXTRACTPACK = 134; public static final int ARM_GRP_THUMB2DSP = 135; public static final int ARM_GRP_TRUSTZONE = 136; public static final int ARM_GRP_V4T = 137; public static final int ARM_GRP_V5T = 138; public static final int ARM_GRP_V5TE = 139; public static final int ARM_GRP_V6 = 140; public static final int ARM_GRP_V6T2 = 141; public static final int ARM_GRP_V7 = 142; public static final int ARM_GRP_V8 = 143; public static final int ARM_GRP_VFP2 = 144; public static final int ARM_GRP_VFP3 = 145; public static final int ARM_GRP_VFP4 = 146; public static final int ARM_GRP_ARM = 147; public static final int ARM_GRP_MCLASS = 148; public static final int ARM_GRP_NOTMCLASS = 149; public static final int ARM_GRP_THUMB = 150; public static final int ARM_GRP_THUMB1ONLY = 151; public static final int ARM_GRP_THUMB2 = 152; public static final int ARM_GRP_PREV8 = 153; public static final int ARM_GRP_FPVMLX = 154; public static final int ARM_GRP_MULOPS = 155; public static final int ARM_GRP_CRC = 156; public static final int ARM_GRP_DPVFP = 157; public static final int ARM_GRP_V6M = 158; public static final int ARM_GRP_VIRTUALIZATION = 159; public static final int ARM_GRP_ENDING = 160; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Capstone.java000064400000000000000000000504160072674642500231620ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Library; import com.sun.jna.Memory; import com.sun.jna.Native; import com.sun.jna.NativeLong; import com.sun.jna.ptr.ByteByReference; import com.sun.jna.ptr.NativeLongByReference; import com.sun.jna.Structure; import com.sun.jna.Union; import com.sun.jna.Pointer; import com.sun.jna.ptr.PointerByReference; import com.sun.jna.ptr.IntByReference; import java.util.List; import java.util.Arrays; import java.lang.RuntimeException; public class Capstone { protected static abstract class OpInfo {}; protected static abstract class UnionOpInfo extends Structure {}; public static class UnionArch extends Union { public static class ByValue extends UnionArch implements Union.ByValue {}; public Arm.UnionOpInfo arm; public Arm64.UnionOpInfo arm64; public X86.UnionOpInfo x86; public Mips.UnionOpInfo mips; public Ppc.UnionOpInfo ppc; public Sparc.UnionOpInfo sparc; public Systemz.UnionOpInfo sysz; public Xcore.UnionOpInfo xcore; public M680x.UnionOpInfo m680x; } protected static class _cs_insn extends Structure { // instruction ID. public int id; // instruction address. public long address; // instruction size. public short size; // machine bytes of instruction. public byte[] bytes; // instruction mnemonic. NOTE: irrelevant for diet engine. public byte[] mnemonic; // instruction operands. NOTE: irrelevant for diet engine. public byte[] op_str; // detail information of instruction. public _cs_detail.ByReference cs_detail; public _cs_insn() { bytes = new byte[24]; mnemonic = new byte[32]; op_str = new byte[160]; java.util.Arrays.fill(mnemonic, (byte) 0); java.util.Arrays.fill(op_str, (byte) 0); } public _cs_insn(Pointer p) { this(); useMemory(p); read(); } @Override public List getFieldOrder() { return Arrays.asList("id", "address", "size", "bytes", "mnemonic", "op_str", "cs_detail"); } } protected static class _cs_detail extends Structure { public static class ByReference extends _cs_detail implements Structure.ByReference {}; // list of all implicit registers being read. public short[] regs_read = new short[16]; public byte regs_read_count; // list of all implicit registers being written. public short[] regs_write = new short[20]; public byte regs_write_count; // list of semantic groups this instruction belongs to. public byte[] groups = new byte[8]; public byte groups_count; public UnionArch arch; @Override public List getFieldOrder() { return Arrays.asList("regs_read", "regs_read_count", "regs_write", "regs_write_count", "groups", "groups_count", "arch"); } } public static class CsInsn { private Pointer csh; private CS cs; private _cs_insn raw; private int arch; // instruction ID. public int id; // instruction address. public long address; // instruction size. public short size; // Machine bytes of this instruction, with number of bytes indicated by size above public byte[] bytes; // instruction mnemonic. NOTE: irrelevant for diet engine. public String mnemonic; // instruction operands. NOTE: irrelevant for diet engine. public String opStr; // list of all implicit registers being read. public short[] regsRead; // list of all implicit registers being written. public short[] regsWrite; // list of semantic groups this instruction belongs to. public byte[] groups; public OpInfo operands; public CsInsn (_cs_insn insn, int _arch, Pointer _csh, CS _cs, boolean diet) { id = insn.id; address = insn.address; size = insn.size; if (!diet) { int lm = 0; while (insn.mnemonic[lm++] != 0); int lo = 0; while (insn.op_str[lo++] != 0); mnemonic = new String(insn.mnemonic, 0, lm-1); opStr = new String(insn.op_str, 0, lo-1); bytes = Arrays.copyOf(insn.bytes, insn.size); } cs = _cs; arch = _arch; raw = insn; csh = _csh; if (insn.cs_detail != null) { if (!diet) { regsRead = new short[insn.cs_detail.regs_read_count]; for (int i=0; i 2017 */ package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.M680x_const.*; public class M680x { public static class OpIndexed extends Structure { public int base_reg; public int offset_reg; public short offset; public short offset_addr; public byte offset_bits; public byte inc_dec; public byte flags; @Override public List getFieldOrder() { return Arrays.asList("base_reg", "offset_reg", "offset", "offset_addr", "offset_bits", "inc_dec", "flags"); } } public static class OpRelative extends Structure { public short address; public short offset; @Override public List getFieldOrder() { return Arrays.asList("address", "offset"); } } public static class OpExtended extends Structure { public short address; public byte indirect; @Override public List getFieldOrder() { return Arrays.asList("address", "indirect"); } } public static class OpValue extends Union { public int imm; public int reg; public OpIndexed idx; public OpRelative rel; public OpExtended ext; public byte direct_addr; public byte const_val; @Override public List getFieldOrder() { return Arrays.asList("imm", "reg", "idx", "rel", "ext", "direct_addr", "const_val"); } } public static class Operand extends Structure { public int type; public OpValue value; public byte size; public byte access; public void read() { readField("type"); if (type == M680X_OP_IMMEDIATE) value.setType(Integer.TYPE); if (type == M680X_OP_REGISTER) value.setType(Integer.TYPE); if (type == M680X_OP_INDEXED) value.setType(OpIndexed.class); if (type == M680X_OP_RELATIVE) value.setType(OpRelative.class); if (type == M680X_OP_EXTENDED) value.setType(OpExtended.class); if (type == M680X_OP_DIRECT) value.setType(Integer.TYPE); if (type == M680X_OP_INVALID) return; readField("value"); readField("size"); readField("access"); } @Override public List getFieldOrder() { return Arrays.asList("type", "value", "size", "access"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public byte flags; public byte op_count; public Operand [] op; public UnionOpInfo() { op = new Operand[9]; } public void read() { readField("flags"); readField("op_count"); op = new Operand[op_count]; if (op_count != 0) readField("op"); } @Override public List getFieldOrder() { return Arrays.asList("flags", "op_count", "op"); } } public static class OpInfo extends Capstone.OpInfo { public byte flags; public Operand [] op = null; public OpInfo(UnionOpInfo op_info) { flags = op_info.flags; op = op_info.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/M680x_const.java000064400000000000000000000452010072674642500234320ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class M680x_const { public static final int M680X_OPERAND_COUNT = 9; public static final int M680X_REG_INVALID = 0; public static final int M680X_REG_A = 1; public static final int M680X_REG_B = 2; public static final int M680X_REG_E = 3; public static final int M680X_REG_F = 4; public static final int M680X_REG_0 = 5; public static final int M680X_REG_D = 6; public static final int M680X_REG_W = 7; public static final int M680X_REG_CC = 8; public static final int M680X_REG_DP = 9; public static final int M680X_REG_MD = 10; public static final int M680X_REG_HX = 11; public static final int M680X_REG_H = 12; public static final int M680X_REG_X = 13; public static final int M680X_REG_Y = 14; public static final int M680X_REG_S = 15; public static final int M680X_REG_U = 16; public static final int M680X_REG_V = 17; public static final int M680X_REG_Q = 18; public static final int M680X_REG_PC = 19; public static final int M680X_REG_TMP2 = 20; public static final int M680X_REG_TMP3 = 21; public static final int M680X_REG_ENDING = 22; public static final int M680X_OP_INVALID = 0; public static final int M680X_OP_REGISTER = 1; public static final int M680X_OP_IMMEDIATE = 2; public static final int M680X_OP_INDEXED = 3; public static final int M680X_OP_EXTENDED = 4; public static final int M680X_OP_DIRECT = 5; public static final int M680X_OP_RELATIVE = 6; public static final int M680X_OP_CONSTANT = 7; public static final int M680X_OFFSET_NONE = 0; public static final int M680X_OFFSET_BITS_5 = 5; public static final int M680X_OFFSET_BITS_8 = 8; public static final int M680X_OFFSET_BITS_9 = 9; public static final int M680X_OFFSET_BITS_16 = 16; public static final int M680X_IDX_INDIRECT = 1; public static final int M680X_IDX_NO_COMMA = 2; public static final int M680X_IDX_POST_INC_DEC = 4; public static final int M680X_GRP_INVALID = 0; public static final int M680X_GRP_JUMP = 1; public static final int M680X_GRP_CALL = 2; public static final int M680X_GRP_RET = 3; public static final int M680X_GRP_INT = 4; public static final int M680X_GRP_IRET = 5; public static final int M680X_GRP_PRIV = 6; public static final int M680X_GRP_BRAREL = 7; public static final int M680X_GRP_ENDING = 8; public static final int M680X_FIRST_OP_IN_MNEM = 1; public static final int M680X_SECOND_OP_IN_MNEM = 2; public static final int M680X_INS_INVLD = 0; public static final int M680X_INS_ABA = 1; public static final int M680X_INS_ABX = 2; public static final int M680X_INS_ABY = 3; public static final int M680X_INS_ADC = 4; public static final int M680X_INS_ADCA = 5; public static final int M680X_INS_ADCB = 6; public static final int M680X_INS_ADCD = 7; public static final int M680X_INS_ADCR = 8; public static final int M680X_INS_ADD = 9; public static final int M680X_INS_ADDA = 10; public static final int M680X_INS_ADDB = 11; public static final int M680X_INS_ADDD = 12; public static final int M680X_INS_ADDE = 13; public static final int M680X_INS_ADDF = 14; public static final int M680X_INS_ADDR = 15; public static final int M680X_INS_ADDW = 16; public static final int M680X_INS_AIM = 17; public static final int M680X_INS_AIS = 18; public static final int M680X_INS_AIX = 19; public static final int M680X_INS_AND = 20; public static final int M680X_INS_ANDA = 21; public static final int M680X_INS_ANDB = 22; public static final int M680X_INS_ANDCC = 23; public static final int M680X_INS_ANDD = 24; public static final int M680X_INS_ANDR = 25; public static final int M680X_INS_ASL = 26; public static final int M680X_INS_ASLA = 27; public static final int M680X_INS_ASLB = 28; public static final int M680X_INS_ASLD = 29; public static final int M680X_INS_ASR = 30; public static final int M680X_INS_ASRA = 31; public static final int M680X_INS_ASRB = 32; public static final int M680X_INS_ASRD = 33; public static final int M680X_INS_ASRX = 34; public static final int M680X_INS_BAND = 35; public static final int M680X_INS_BCC = 36; public static final int M680X_INS_BCLR = 37; public static final int M680X_INS_BCS = 38; public static final int M680X_INS_BEOR = 39; public static final int M680X_INS_BEQ = 40; public static final int M680X_INS_BGE = 41; public static final int M680X_INS_BGND = 42; public static final int M680X_INS_BGT = 43; public static final int M680X_INS_BHCC = 44; public static final int M680X_INS_BHCS = 45; public static final int M680X_INS_BHI = 46; public static final int M680X_INS_BIAND = 47; public static final int M680X_INS_BIEOR = 48; public static final int M680X_INS_BIH = 49; public static final int M680X_INS_BIL = 50; public static final int M680X_INS_BIOR = 51; public static final int M680X_INS_BIT = 52; public static final int M680X_INS_BITA = 53; public static final int M680X_INS_BITB = 54; public static final int M680X_INS_BITD = 55; public static final int M680X_INS_BITMD = 56; public static final int M680X_INS_BLE = 57; public static final int M680X_INS_BLS = 58; public static final int M680X_INS_BLT = 59; public static final int M680X_INS_BMC = 60; public static final int M680X_INS_BMI = 61; public static final int M680X_INS_BMS = 62; public static final int M680X_INS_BNE = 63; public static final int M680X_INS_BOR = 64; public static final int M680X_INS_BPL = 65; public static final int M680X_INS_BRCLR = 66; public static final int M680X_INS_BRSET = 67; public static final int M680X_INS_BRA = 68; public static final int M680X_INS_BRN = 69; public static final int M680X_INS_BSET = 70; public static final int M680X_INS_BSR = 71; public static final int M680X_INS_BVC = 72; public static final int M680X_INS_BVS = 73; public static final int M680X_INS_CALL = 74; public static final int M680X_INS_CBA = 75; public static final int M680X_INS_CBEQ = 76; public static final int M680X_INS_CBEQA = 77; public static final int M680X_INS_CBEQX = 78; public static final int M680X_INS_CLC = 79; public static final int M680X_INS_CLI = 80; public static final int M680X_INS_CLR = 81; public static final int M680X_INS_CLRA = 82; public static final int M680X_INS_CLRB = 83; public static final int M680X_INS_CLRD = 84; public static final int M680X_INS_CLRE = 85; public static final int M680X_INS_CLRF = 86; public static final int M680X_INS_CLRH = 87; public static final int M680X_INS_CLRW = 88; public static final int M680X_INS_CLRX = 89; public static final int M680X_INS_CLV = 90; public static final int M680X_INS_CMP = 91; public static final int M680X_INS_CMPA = 92; public static final int M680X_INS_CMPB = 93; public static final int M680X_INS_CMPD = 94; public static final int M680X_INS_CMPE = 95; public static final int M680X_INS_CMPF = 96; public static final int M680X_INS_CMPR = 97; public static final int M680X_INS_CMPS = 98; public static final int M680X_INS_CMPU = 99; public static final int M680X_INS_CMPW = 100; public static final int M680X_INS_CMPX = 101; public static final int M680X_INS_CMPY = 102; public static final int M680X_INS_COM = 103; public static final int M680X_INS_COMA = 104; public static final int M680X_INS_COMB = 105; public static final int M680X_INS_COMD = 106; public static final int M680X_INS_COME = 107; public static final int M680X_INS_COMF = 108; public static final int M680X_INS_COMW = 109; public static final int M680X_INS_COMX = 110; public static final int M680X_INS_CPD = 111; public static final int M680X_INS_CPHX = 112; public static final int M680X_INS_CPS = 113; public static final int M680X_INS_CPX = 114; public static final int M680X_INS_CPY = 115; public static final int M680X_INS_CWAI = 116; public static final int M680X_INS_DAA = 117; public static final int M680X_INS_DBEQ = 118; public static final int M680X_INS_DBNE = 119; public static final int M680X_INS_DBNZ = 120; public static final int M680X_INS_DBNZA = 121; public static final int M680X_INS_DBNZX = 122; public static final int M680X_INS_DEC = 123; public static final int M680X_INS_DECA = 124; public static final int M680X_INS_DECB = 125; public static final int M680X_INS_DECD = 126; public static final int M680X_INS_DECE = 127; public static final int M680X_INS_DECF = 128; public static final int M680X_INS_DECW = 129; public static final int M680X_INS_DECX = 130; public static final int M680X_INS_DES = 131; public static final int M680X_INS_DEX = 132; public static final int M680X_INS_DEY = 133; public static final int M680X_INS_DIV = 134; public static final int M680X_INS_DIVD = 135; public static final int M680X_INS_DIVQ = 136; public static final int M680X_INS_EDIV = 137; public static final int M680X_INS_EDIVS = 138; public static final int M680X_INS_EIM = 139; public static final int M680X_INS_EMACS = 140; public static final int M680X_INS_EMAXD = 141; public static final int M680X_INS_EMAXM = 142; public static final int M680X_INS_EMIND = 143; public static final int M680X_INS_EMINM = 144; public static final int M680X_INS_EMUL = 145; public static final int M680X_INS_EMULS = 146; public static final int M680X_INS_EOR = 147; public static final int M680X_INS_EORA = 148; public static final int M680X_INS_EORB = 149; public static final int M680X_INS_EORD = 150; public static final int M680X_INS_EORR = 151; public static final int M680X_INS_ETBL = 152; public static final int M680X_INS_EXG = 153; public static final int M680X_INS_FDIV = 154; public static final int M680X_INS_IBEQ = 155; public static final int M680X_INS_IBNE = 156; public static final int M680X_INS_IDIV = 157; public static final int M680X_INS_IDIVS = 158; public static final int M680X_INS_ILLGL = 159; public static final int M680X_INS_INC = 160; public static final int M680X_INS_INCA = 161; public static final int M680X_INS_INCB = 162; public static final int M680X_INS_INCD = 163; public static final int M680X_INS_INCE = 164; public static final int M680X_INS_INCF = 165; public static final int M680X_INS_INCW = 166; public static final int M680X_INS_INCX = 167; public static final int M680X_INS_INS = 168; public static final int M680X_INS_INX = 169; public static final int M680X_INS_INY = 170; public static final int M680X_INS_JMP = 171; public static final int M680X_INS_JSR = 172; public static final int M680X_INS_LBCC = 173; public static final int M680X_INS_LBCS = 174; public static final int M680X_INS_LBEQ = 175; public static final int M680X_INS_LBGE = 176; public static final int M680X_INS_LBGT = 177; public static final int M680X_INS_LBHI = 178; public static final int M680X_INS_LBLE = 179; public static final int M680X_INS_LBLS = 180; public static final int M680X_INS_LBLT = 181; public static final int M680X_INS_LBMI = 182; public static final int M680X_INS_LBNE = 183; public static final int M680X_INS_LBPL = 184; public static final int M680X_INS_LBRA = 185; public static final int M680X_INS_LBRN = 186; public static final int M680X_INS_LBSR = 187; public static final int M680X_INS_LBVC = 188; public static final int M680X_INS_LBVS = 189; public static final int M680X_INS_LDA = 190; public static final int M680X_INS_LDAA = 191; public static final int M680X_INS_LDAB = 192; public static final int M680X_INS_LDB = 193; public static final int M680X_INS_LDBT = 194; public static final int M680X_INS_LDD = 195; public static final int M680X_INS_LDE = 196; public static final int M680X_INS_LDF = 197; public static final int M680X_INS_LDHX = 198; public static final int M680X_INS_LDMD = 199; public static final int M680X_INS_LDQ = 200; public static final int M680X_INS_LDS = 201; public static final int M680X_INS_LDU = 202; public static final int M680X_INS_LDW = 203; public static final int M680X_INS_LDX = 204; public static final int M680X_INS_LDY = 205; public static final int M680X_INS_LEAS = 206; public static final int M680X_INS_LEAU = 207; public static final int M680X_INS_LEAX = 208; public static final int M680X_INS_LEAY = 209; public static final int M680X_INS_LSL = 210; public static final int M680X_INS_LSLA = 211; public static final int M680X_INS_LSLB = 212; public static final int M680X_INS_LSLD = 213; public static final int M680X_INS_LSLX = 214; public static final int M680X_INS_LSR = 215; public static final int M680X_INS_LSRA = 216; public static final int M680X_INS_LSRB = 217; public static final int M680X_INS_LSRD = 218; public static final int M680X_INS_LSRW = 219; public static final int M680X_INS_LSRX = 220; public static final int M680X_INS_MAXA = 221; public static final int M680X_INS_MAXM = 222; public static final int M680X_INS_MEM = 223; public static final int M680X_INS_MINA = 224; public static final int M680X_INS_MINM = 225; public static final int M680X_INS_MOV = 226; public static final int M680X_INS_MOVB = 227; public static final int M680X_INS_MOVW = 228; public static final int M680X_INS_MUL = 229; public static final int M680X_INS_MULD = 230; public static final int M680X_INS_NEG = 231; public static final int M680X_INS_NEGA = 232; public static final int M680X_INS_NEGB = 233; public static final int M680X_INS_NEGD = 234; public static final int M680X_INS_NEGX = 235; public static final int M680X_INS_NOP = 236; public static final int M680X_INS_NSA = 237; public static final int M680X_INS_OIM = 238; public static final int M680X_INS_ORA = 239; public static final int M680X_INS_ORAA = 240; public static final int M680X_INS_ORAB = 241; public static final int M680X_INS_ORB = 242; public static final int M680X_INS_ORCC = 243; public static final int M680X_INS_ORD = 244; public static final int M680X_INS_ORR = 245; public static final int M680X_INS_PSHA = 246; public static final int M680X_INS_PSHB = 247; public static final int M680X_INS_PSHC = 248; public static final int M680X_INS_PSHD = 249; public static final int M680X_INS_PSHH = 250; public static final int M680X_INS_PSHS = 251; public static final int M680X_INS_PSHSW = 252; public static final int M680X_INS_PSHU = 253; public static final int M680X_INS_PSHUW = 254; public static final int M680X_INS_PSHX = 255; public static final int M680X_INS_PSHY = 256; public static final int M680X_INS_PULA = 257; public static final int M680X_INS_PULB = 258; public static final int M680X_INS_PULC = 259; public static final int M680X_INS_PULD = 260; public static final int M680X_INS_PULH = 261; public static final int M680X_INS_PULS = 262; public static final int M680X_INS_PULSW = 263; public static final int M680X_INS_PULU = 264; public static final int M680X_INS_PULUW = 265; public static final int M680X_INS_PULX = 266; public static final int M680X_INS_PULY = 267; public static final int M680X_INS_REV = 268; public static final int M680X_INS_REVW = 269; public static final int M680X_INS_ROL = 270; public static final int M680X_INS_ROLA = 271; public static final int M680X_INS_ROLB = 272; public static final int M680X_INS_ROLD = 273; public static final int M680X_INS_ROLW = 274; public static final int M680X_INS_ROLX = 275; public static final int M680X_INS_ROR = 276; public static final int M680X_INS_RORA = 277; public static final int M680X_INS_RORB = 278; public static final int M680X_INS_RORD = 279; public static final int M680X_INS_RORW = 280; public static final int M680X_INS_RORX = 281; public static final int M680X_INS_RSP = 282; public static final int M680X_INS_RTC = 283; public static final int M680X_INS_RTI = 284; public static final int M680X_INS_RTS = 285; public static final int M680X_INS_SBA = 286; public static final int M680X_INS_SBC = 287; public static final int M680X_INS_SBCA = 288; public static final int M680X_INS_SBCB = 289; public static final int M680X_INS_SBCD = 290; public static final int M680X_INS_SBCR = 291; public static final int M680X_INS_SEC = 292; public static final int M680X_INS_SEI = 293; public static final int M680X_INS_SEV = 294; public static final int M680X_INS_SEX = 295; public static final int M680X_INS_SEXW = 296; public static final int M680X_INS_SLP = 297; public static final int M680X_INS_STA = 298; public static final int M680X_INS_STAA = 299; public static final int M680X_INS_STAB = 300; public static final int M680X_INS_STB = 301; public static final int M680X_INS_STBT = 302; public static final int M680X_INS_STD = 303; public static final int M680X_INS_STE = 304; public static final int M680X_INS_STF = 305; public static final int M680X_INS_STOP = 306; public static final int M680X_INS_STHX = 307; public static final int M680X_INS_STQ = 308; public static final int M680X_INS_STS = 309; public static final int M680X_INS_STU = 310; public static final int M680X_INS_STW = 311; public static final int M680X_INS_STX = 312; public static final int M680X_INS_STY = 313; public static final int M680X_INS_SUB = 314; public static final int M680X_INS_SUBA = 315; public static final int M680X_INS_SUBB = 316; public static final int M680X_INS_SUBD = 317; public static final int M680X_INS_SUBE = 318; public static final int M680X_INS_SUBF = 319; public static final int M680X_INS_SUBR = 320; public static final int M680X_INS_SUBW = 321; public static final int M680X_INS_SWI = 322; public static final int M680X_INS_SWI2 = 323; public static final int M680X_INS_SWI3 = 324; public static final int M680X_INS_SYNC = 325; public static final int M680X_INS_TAB = 326; public static final int M680X_INS_TAP = 327; public static final int M680X_INS_TAX = 328; public static final int M680X_INS_TBA = 329; public static final int M680X_INS_TBEQ = 330; public static final int M680X_INS_TBL = 331; public static final int M680X_INS_TBNE = 332; public static final int M680X_INS_TEST = 333; public static final int M680X_INS_TFM = 334; public static final int M680X_INS_TFR = 335; public static final int M680X_INS_TIM = 336; public static final int M680X_INS_TPA = 337; public static final int M680X_INS_TST = 338; public static final int M680X_INS_TSTA = 339; public static final int M680X_INS_TSTB = 340; public static final int M680X_INS_TSTD = 341; public static final int M680X_INS_TSTE = 342; public static final int M680X_INS_TSTF = 343; public static final int M680X_INS_TSTW = 344; public static final int M680X_INS_TSTX = 345; public static final int M680X_INS_TSX = 346; public static final int M680X_INS_TSY = 347; public static final int M680X_INS_TXA = 348; public static final int M680X_INS_TXS = 349; public static final int M680X_INS_TYS = 350; public static final int M680X_INS_WAI = 351; public static final int M680X_INS_WAIT = 352; public static final int M680X_INS_WAV = 353; public static final int M680X_INS_WAVR = 354; public static final int M680X_INS_XGDX = 355; public static final int M680X_INS_XGDY = 356; public static final int M680X_INS_ENDING = 357; }capstone-sys-0.15.0/capstone/bindings/java/capstone/M68k_const.java000064400000000000000000000534630072674642500233460ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class M68k_const { public static final int M68K_OPERAND_COUNT = 4; public static final int M68K_REG_INVALID = 0; public static final int M68K_REG_D0 = 1; public static final int M68K_REG_D1 = 2; public static final int M68K_REG_D2 = 3; public static final int M68K_REG_D3 = 4; public static final int M68K_REG_D4 = 5; public static final int M68K_REG_D5 = 6; public static final int M68K_REG_D6 = 7; public static final int M68K_REG_D7 = 8; public static final int M68K_REG_A0 = 9; public static final int M68K_REG_A1 = 10; public static final int M68K_REG_A2 = 11; public static final int M68K_REG_A3 = 12; public static final int M68K_REG_A4 = 13; public static final int M68K_REG_A5 = 14; public static final int M68K_REG_A6 = 15; public static final int M68K_REG_A7 = 16; public static final int M68K_REG_FP0 = 17; public static final int M68K_REG_FP1 = 18; public static final int M68K_REG_FP2 = 19; public static final int M68K_REG_FP3 = 20; public static final int M68K_REG_FP4 = 21; public static final int M68K_REG_FP5 = 22; public static final int M68K_REG_FP6 = 23; public static final int M68K_REG_FP7 = 24; public static final int M68K_REG_PC = 25; public static final int M68K_REG_SR = 26; public static final int M68K_REG_CCR = 27; public static final int M68K_REG_SFC = 28; public static final int M68K_REG_DFC = 29; public static final int M68K_REG_USP = 30; public static final int M68K_REG_VBR = 31; public static final int M68K_REG_CACR = 32; public static final int M68K_REG_CAAR = 33; public static final int M68K_REG_MSP = 34; public static final int M68K_REG_ISP = 35; public static final int M68K_REG_TC = 36; public static final int M68K_REG_ITT0 = 37; public static final int M68K_REG_ITT1 = 38; public static final int M68K_REG_DTT0 = 39; public static final int M68K_REG_DTT1 = 40; public static final int M68K_REG_MMUSR = 41; public static final int M68K_REG_URP = 42; public static final int M68K_REG_SRP = 43; public static final int M68K_REG_FPCR = 44; public static final int M68K_REG_FPSR = 45; public static final int M68K_REG_FPIAR = 46; public static final int M68K_REG_ENDING = 47; public static final int M68K_AM_NONE = 0; public static final int M68K_AM_REG_DIRECT_DATA = 1; public static final int M68K_AM_REG_DIRECT_ADDR = 2; public static final int M68K_AM_REGI_ADDR = 3; public static final int M68K_AM_REGI_ADDR_POST_INC = 4; public static final int M68K_AM_REGI_ADDR_PRE_DEC = 5; public static final int M68K_AM_REGI_ADDR_DISP = 6; public static final int M68K_AM_AREGI_INDEX_8_BIT_DISP = 7; public static final int M68K_AM_AREGI_INDEX_BASE_DISP = 8; public static final int M68K_AM_MEMI_POST_INDEX = 9; public static final int M68K_AM_MEMI_PRE_INDEX = 10; public static final int M68K_AM_PCI_DISP = 11; public static final int M68K_AM_PCI_INDEX_8_BIT_DISP = 12; public static final int M68K_AM_PCI_INDEX_BASE_DISP = 13; public static final int M68K_AM_PC_MEMI_POST_INDEX = 14; public static final int M68K_AM_PC_MEMI_PRE_INDEX = 15; public static final int M68K_AM_ABSOLUTE_DATA_SHORT = 16; public static final int M68K_AM_ABSOLUTE_DATA_LONG = 17; public static final int M68K_AM_IMMEDIATE = 18; public static final int M68K_AM_BRANCH_DISPLACEMENT = 19; public static final int M68K_OP_INVALID = 0; public static final int M68K_OP_REG = 1; public static final int M68K_OP_IMM = 2; public static final int M68K_OP_MEM = 3; public static final int M68K_OP_FP_SINGLE = 4; public static final int M68K_OP_FP_DOUBLE = 5; public static final int M68K_OP_REG_BITS = 6; public static final int M68K_OP_REG_PAIR = 7; public static final int M68K_OP_BR_DISP = 8; public static final int M68K_OP_BR_DISP_SIZE_INVALID = 0; public static final int M68K_OP_BR_DISP_SIZE_BYTE = 1; public static final int M68K_OP_BR_DISP_SIZE_WORD = 2; public static final int M68K_OP_BR_DISP_SIZE_LONG = 4; public static final int M68K_CPU_SIZE_NONE = 0; public static final int M68K_CPU_SIZE_BYTE = 1; public static final int M68K_CPU_SIZE_WORD = 2; public static final int M68K_CPU_SIZE_LONG = 4; public static final int M68K_FPU_SIZE_NONE = 0; public static final int M68K_FPU_SIZE_SINGLE = 4; public static final int M68K_FPU_SIZE_DOUBLE = 8; public static final int M68K_FPU_SIZE_EXTENDED = 12; public static final int M68K_SIZE_TYPE_INVALID = 0; public static final int M68K_SIZE_TYPE_CPU = 1; public static final int M68K_SIZE_TYPE_FPU = 2; public static final int M68K_INS_INVALID = 0; public static final int M68K_INS_ABCD = 1; public static final int M68K_INS_ADD = 2; public static final int M68K_INS_ADDA = 3; public static final int M68K_INS_ADDI = 4; public static final int M68K_INS_ADDQ = 5; public static final int M68K_INS_ADDX = 6; public static final int M68K_INS_AND = 7; public static final int M68K_INS_ANDI = 8; public static final int M68K_INS_ASL = 9; public static final int M68K_INS_ASR = 10; public static final int M68K_INS_BHS = 11; public static final int M68K_INS_BLO = 12; public static final int M68K_INS_BHI = 13; public static final int M68K_INS_BLS = 14; public static final int M68K_INS_BCC = 15; public static final int M68K_INS_BCS = 16; public static final int M68K_INS_BNE = 17; public static final int M68K_INS_BEQ = 18; public static final int M68K_INS_BVC = 19; public static final int M68K_INS_BVS = 20; public static final int M68K_INS_BPL = 21; public static final int M68K_INS_BMI = 22; public static final int M68K_INS_BGE = 23; public static final int M68K_INS_BLT = 24; public static final int M68K_INS_BGT = 25; public static final int M68K_INS_BLE = 26; public static final int M68K_INS_BRA = 27; public static final int M68K_INS_BSR = 28; public static final int M68K_INS_BCHG = 29; public static final int M68K_INS_BCLR = 30; public static final int M68K_INS_BSET = 31; public static final int M68K_INS_BTST = 32; public static final int M68K_INS_BFCHG = 33; public static final int M68K_INS_BFCLR = 34; public static final int M68K_INS_BFEXTS = 35; public static final int M68K_INS_BFEXTU = 36; public static final int M68K_INS_BFFFO = 37; public static final int M68K_INS_BFINS = 38; public static final int M68K_INS_BFSET = 39; public static final int M68K_INS_BFTST = 40; public static final int M68K_INS_BKPT = 41; public static final int M68K_INS_CALLM = 42; public static final int M68K_INS_CAS = 43; public static final int M68K_INS_CAS2 = 44; public static final int M68K_INS_CHK = 45; public static final int M68K_INS_CHK2 = 46; public static final int M68K_INS_CLR = 47; public static final int M68K_INS_CMP = 48; public static final int M68K_INS_CMPA = 49; public static final int M68K_INS_CMPI = 50; public static final int M68K_INS_CMPM = 51; public static final int M68K_INS_CMP2 = 52; public static final int M68K_INS_CINVL = 53; public static final int M68K_INS_CINVP = 54; public static final int M68K_INS_CINVA = 55; public static final int M68K_INS_CPUSHL = 56; public static final int M68K_INS_CPUSHP = 57; public static final int M68K_INS_CPUSHA = 58; public static final int M68K_INS_DBT = 59; public static final int M68K_INS_DBF = 60; public static final int M68K_INS_DBHI = 61; public static final int M68K_INS_DBLS = 62; public static final int M68K_INS_DBCC = 63; public static final int M68K_INS_DBCS = 64; public static final int M68K_INS_DBNE = 65; public static final int M68K_INS_DBEQ = 66; public static final int M68K_INS_DBVC = 67; public static final int M68K_INS_DBVS = 68; public static final int M68K_INS_DBPL = 69; public static final int M68K_INS_DBMI = 70; public static final int M68K_INS_DBGE = 71; public static final int M68K_INS_DBLT = 72; public static final int M68K_INS_DBGT = 73; public static final int M68K_INS_DBLE = 74; public static final int M68K_INS_DBRA = 75; public static final int M68K_INS_DIVS = 76; public static final int M68K_INS_DIVSL = 77; public static final int M68K_INS_DIVU = 78; public static final int M68K_INS_DIVUL = 79; public static final int M68K_INS_EOR = 80; public static final int M68K_INS_EORI = 81; public static final int M68K_INS_EXG = 82; public static final int M68K_INS_EXT = 83; public static final int M68K_INS_EXTB = 84; public static final int M68K_INS_FABS = 85; public static final int M68K_INS_FSABS = 86; public static final int M68K_INS_FDABS = 87; public static final int M68K_INS_FACOS = 88; public static final int M68K_INS_FADD = 89; public static final int M68K_INS_FSADD = 90; public static final int M68K_INS_FDADD = 91; public static final int M68K_INS_FASIN = 92; public static final int M68K_INS_FATAN = 93; public static final int M68K_INS_FATANH = 94; public static final int M68K_INS_FBF = 95; public static final int M68K_INS_FBEQ = 96; public static final int M68K_INS_FBOGT = 97; public static final int M68K_INS_FBOGE = 98; public static final int M68K_INS_FBOLT = 99; public static final int M68K_INS_FBOLE = 100; public static final int M68K_INS_FBOGL = 101; public static final int M68K_INS_FBOR = 102; public static final int M68K_INS_FBUN = 103; public static final int M68K_INS_FBUEQ = 104; public static final int M68K_INS_FBUGT = 105; public static final int M68K_INS_FBUGE = 106; public static final int M68K_INS_FBULT = 107; public static final int M68K_INS_FBULE = 108; public static final int M68K_INS_FBNE = 109; public static final int M68K_INS_FBT = 110; public static final int M68K_INS_FBSF = 111; public static final int M68K_INS_FBSEQ = 112; public static final int M68K_INS_FBGT = 113; public static final int M68K_INS_FBGE = 114; public static final int M68K_INS_FBLT = 115; public static final int M68K_INS_FBLE = 116; public static final int M68K_INS_FBGL = 117; public static final int M68K_INS_FBGLE = 118; public static final int M68K_INS_FBNGLE = 119; public static final int M68K_INS_FBNGL = 120; public static final int M68K_INS_FBNLE = 121; public static final int M68K_INS_FBNLT = 122; public static final int M68K_INS_FBNGE = 123; public static final int M68K_INS_FBNGT = 124; public static final int M68K_INS_FBSNE = 125; public static final int M68K_INS_FBST = 126; public static final int M68K_INS_FCMP = 127; public static final int M68K_INS_FCOS = 128; public static final int M68K_INS_FCOSH = 129; public static final int M68K_INS_FDBF = 130; public static final int M68K_INS_FDBEQ = 131; public static final int M68K_INS_FDBOGT = 132; public static final int M68K_INS_FDBOGE = 133; public static final int M68K_INS_FDBOLT = 134; public static final int M68K_INS_FDBOLE = 135; public static final int M68K_INS_FDBOGL = 136; public static final int M68K_INS_FDBOR = 137; public static final int M68K_INS_FDBUN = 138; public static final int M68K_INS_FDBUEQ = 139; public static final int M68K_INS_FDBUGT = 140; public static final int M68K_INS_FDBUGE = 141; public static final int M68K_INS_FDBULT = 142; public static final int M68K_INS_FDBULE = 143; public static final int M68K_INS_FDBNE = 144; public static final int M68K_INS_FDBT = 145; public static final int M68K_INS_FDBSF = 146; public static final int M68K_INS_FDBSEQ = 147; public static final int M68K_INS_FDBGT = 148; public static final int M68K_INS_FDBGE = 149; public static final int M68K_INS_FDBLT = 150; public static final int M68K_INS_FDBLE = 151; public static final int M68K_INS_FDBGL = 152; public static final int M68K_INS_FDBGLE = 153; public static final int M68K_INS_FDBNGLE = 154; public static final int M68K_INS_FDBNGL = 155; public static final int M68K_INS_FDBNLE = 156; public static final int M68K_INS_FDBNLT = 157; public static final int M68K_INS_FDBNGE = 158; public static final int M68K_INS_FDBNGT = 159; public static final int M68K_INS_FDBSNE = 160; public static final int M68K_INS_FDBST = 161; public static final int M68K_INS_FDIV = 162; public static final int M68K_INS_FSDIV = 163; public static final int M68K_INS_FDDIV = 164; public static final int M68K_INS_FETOX = 165; public static final int M68K_INS_FETOXM1 = 166; public static final int M68K_INS_FGETEXP = 167; public static final int M68K_INS_FGETMAN = 168; public static final int M68K_INS_FINT = 169; public static final int M68K_INS_FINTRZ = 170; public static final int M68K_INS_FLOG10 = 171; public static final int M68K_INS_FLOG2 = 172; public static final int M68K_INS_FLOGN = 173; public static final int M68K_INS_FLOGNP1 = 174; public static final int M68K_INS_FMOD = 175; public static final int M68K_INS_FMOVE = 176; public static final int M68K_INS_FSMOVE = 177; public static final int M68K_INS_FDMOVE = 178; public static final int M68K_INS_FMOVECR = 179; public static final int M68K_INS_FMOVEM = 180; public static final int M68K_INS_FMUL = 181; public static final int M68K_INS_FSMUL = 182; public static final int M68K_INS_FDMUL = 183; public static final int M68K_INS_FNEG = 184; public static final int M68K_INS_FSNEG = 185; public static final int M68K_INS_FDNEG = 186; public static final int M68K_INS_FNOP = 187; public static final int M68K_INS_FREM = 188; public static final int M68K_INS_FRESTORE = 189; public static final int M68K_INS_FSAVE = 190; public static final int M68K_INS_FSCALE = 191; public static final int M68K_INS_FSGLDIV = 192; public static final int M68K_INS_FSGLMUL = 193; public static final int M68K_INS_FSIN = 194; public static final int M68K_INS_FSINCOS = 195; public static final int M68K_INS_FSINH = 196; public static final int M68K_INS_FSQRT = 197; public static final int M68K_INS_FSSQRT = 198; public static final int M68K_INS_FDSQRT = 199; public static final int M68K_INS_FSF = 200; public static final int M68K_INS_FSBEQ = 201; public static final int M68K_INS_FSOGT = 202; public static final int M68K_INS_FSOGE = 203; public static final int M68K_INS_FSOLT = 204; public static final int M68K_INS_FSOLE = 205; public static final int M68K_INS_FSOGL = 206; public static final int M68K_INS_FSOR = 207; public static final int M68K_INS_FSUN = 208; public static final int M68K_INS_FSUEQ = 209; public static final int M68K_INS_FSUGT = 210; public static final int M68K_INS_FSUGE = 211; public static final int M68K_INS_FSULT = 212; public static final int M68K_INS_FSULE = 213; public static final int M68K_INS_FSNE = 214; public static final int M68K_INS_FST = 215; public static final int M68K_INS_FSSF = 216; public static final int M68K_INS_FSSEQ = 217; public static final int M68K_INS_FSGT = 218; public static final int M68K_INS_FSGE = 219; public static final int M68K_INS_FSLT = 220; public static final int M68K_INS_FSLE = 221; public static final int M68K_INS_FSGL = 222; public static final int M68K_INS_FSGLE = 223; public static final int M68K_INS_FSNGLE = 224; public static final int M68K_INS_FSNGL = 225; public static final int M68K_INS_FSNLE = 226; public static final int M68K_INS_FSNLT = 227; public static final int M68K_INS_FSNGE = 228; public static final int M68K_INS_FSNGT = 229; public static final int M68K_INS_FSSNE = 230; public static final int M68K_INS_FSST = 231; public static final int M68K_INS_FSUB = 232; public static final int M68K_INS_FSSUB = 233; public static final int M68K_INS_FDSUB = 234; public static final int M68K_INS_FTAN = 235; public static final int M68K_INS_FTANH = 236; public static final int M68K_INS_FTENTOX = 237; public static final int M68K_INS_FTRAPF = 238; public static final int M68K_INS_FTRAPEQ = 239; public static final int M68K_INS_FTRAPOGT = 240; public static final int M68K_INS_FTRAPOGE = 241; public static final int M68K_INS_FTRAPOLT = 242; public static final int M68K_INS_FTRAPOLE = 243; public static final int M68K_INS_FTRAPOGL = 244; public static final int M68K_INS_FTRAPOR = 245; public static final int M68K_INS_FTRAPUN = 246; public static final int M68K_INS_FTRAPUEQ = 247; public static final int M68K_INS_FTRAPUGT = 248; public static final int M68K_INS_FTRAPUGE = 249; public static final int M68K_INS_FTRAPULT = 250; public static final int M68K_INS_FTRAPULE = 251; public static final int M68K_INS_FTRAPNE = 252; public static final int M68K_INS_FTRAPT = 253; public static final int M68K_INS_FTRAPSF = 254; public static final int M68K_INS_FTRAPSEQ = 255; public static final int M68K_INS_FTRAPGT = 256; public static final int M68K_INS_FTRAPGE = 257; public static final int M68K_INS_FTRAPLT = 258; public static final int M68K_INS_FTRAPLE = 259; public static final int M68K_INS_FTRAPGL = 260; public static final int M68K_INS_FTRAPGLE = 261; public static final int M68K_INS_FTRAPNGLE = 262; public static final int M68K_INS_FTRAPNGL = 263; public static final int M68K_INS_FTRAPNLE = 264; public static final int M68K_INS_FTRAPNLT = 265; public static final int M68K_INS_FTRAPNGE = 266; public static final int M68K_INS_FTRAPNGT = 267; public static final int M68K_INS_FTRAPSNE = 268; public static final int M68K_INS_FTRAPST = 269; public static final int M68K_INS_FTST = 270; public static final int M68K_INS_FTWOTOX = 271; public static final int M68K_INS_HALT = 272; public static final int M68K_INS_ILLEGAL = 273; public static final int M68K_INS_JMP = 274; public static final int M68K_INS_JSR = 275; public static final int M68K_INS_LEA = 276; public static final int M68K_INS_LINK = 277; public static final int M68K_INS_LPSTOP = 278; public static final int M68K_INS_LSL = 279; public static final int M68K_INS_LSR = 280; public static final int M68K_INS_MOVE = 281; public static final int M68K_INS_MOVEA = 282; public static final int M68K_INS_MOVEC = 283; public static final int M68K_INS_MOVEM = 284; public static final int M68K_INS_MOVEP = 285; public static final int M68K_INS_MOVEQ = 286; public static final int M68K_INS_MOVES = 287; public static final int M68K_INS_MOVE16 = 288; public static final int M68K_INS_MULS = 289; public static final int M68K_INS_MULU = 290; public static final int M68K_INS_NBCD = 291; public static final int M68K_INS_NEG = 292; public static final int M68K_INS_NEGX = 293; public static final int M68K_INS_NOP = 294; public static final int M68K_INS_NOT = 295; public static final int M68K_INS_OR = 296; public static final int M68K_INS_ORI = 297; public static final int M68K_INS_PACK = 298; public static final int M68K_INS_PEA = 299; public static final int M68K_INS_PFLUSH = 300; public static final int M68K_INS_PFLUSHA = 301; public static final int M68K_INS_PFLUSHAN = 302; public static final int M68K_INS_PFLUSHN = 303; public static final int M68K_INS_PLOADR = 304; public static final int M68K_INS_PLOADW = 305; public static final int M68K_INS_PLPAR = 306; public static final int M68K_INS_PLPAW = 307; public static final int M68K_INS_PMOVE = 308; public static final int M68K_INS_PMOVEFD = 309; public static final int M68K_INS_PTESTR = 310; public static final int M68K_INS_PTESTW = 311; public static final int M68K_INS_PULSE = 312; public static final int M68K_INS_REMS = 313; public static final int M68K_INS_REMU = 314; public static final int M68K_INS_RESET = 315; public static final int M68K_INS_ROL = 316; public static final int M68K_INS_ROR = 317; public static final int M68K_INS_ROXL = 318; public static final int M68K_INS_ROXR = 319; public static final int M68K_INS_RTD = 320; public static final int M68K_INS_RTE = 321; public static final int M68K_INS_RTM = 322; public static final int M68K_INS_RTR = 323; public static final int M68K_INS_RTS = 324; public static final int M68K_INS_SBCD = 325; public static final int M68K_INS_ST = 326; public static final int M68K_INS_SF = 327; public static final int M68K_INS_SHI = 328; public static final int M68K_INS_SLS = 329; public static final int M68K_INS_SCC = 330; public static final int M68K_INS_SHS = 331; public static final int M68K_INS_SCS = 332; public static final int M68K_INS_SLO = 333; public static final int M68K_INS_SNE = 334; public static final int M68K_INS_SEQ = 335; public static final int M68K_INS_SVC = 336; public static final int M68K_INS_SVS = 337; public static final int M68K_INS_SPL = 338; public static final int M68K_INS_SMI = 339; public static final int M68K_INS_SGE = 340; public static final int M68K_INS_SLT = 341; public static final int M68K_INS_SGT = 342; public static final int M68K_INS_SLE = 343; public static final int M68K_INS_STOP = 344; public static final int M68K_INS_SUB = 345; public static final int M68K_INS_SUBA = 346; public static final int M68K_INS_SUBI = 347; public static final int M68K_INS_SUBQ = 348; public static final int M68K_INS_SUBX = 349; public static final int M68K_INS_SWAP = 350; public static final int M68K_INS_TAS = 351; public static final int M68K_INS_TRAP = 352; public static final int M68K_INS_TRAPV = 353; public static final int M68K_INS_TRAPT = 354; public static final int M68K_INS_TRAPF = 355; public static final int M68K_INS_TRAPHI = 356; public static final int M68K_INS_TRAPLS = 357; public static final int M68K_INS_TRAPCC = 358; public static final int M68K_INS_TRAPHS = 359; public static final int M68K_INS_TRAPCS = 360; public static final int M68K_INS_TRAPLO = 361; public static final int M68K_INS_TRAPNE = 362; public static final int M68K_INS_TRAPEQ = 363; public static final int M68K_INS_TRAPVC = 364; public static final int M68K_INS_TRAPVS = 365; public static final int M68K_INS_TRAPPL = 366; public static final int M68K_INS_TRAPMI = 367; public static final int M68K_INS_TRAPGE = 368; public static final int M68K_INS_TRAPLT = 369; public static final int M68K_INS_TRAPGT = 370; public static final int M68K_INS_TRAPLE = 371; public static final int M68K_INS_TST = 372; public static final int M68K_INS_UNLK = 373; public static final int M68K_INS_UNPK = 374; public static final int M68K_INS_ENDING = 375; public static final int M68K_GRP_INVALID = 0; public static final int M68K_GRP_JUMP = 1; public static final int M68K_GRP_RET = 3; public static final int M68K_GRP_IRET = 5; public static final int M68K_GRP_BRANCH_RELATIVE = 7; public static final int M68K_GRP_ENDING = 8; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Mips.java000064400000000000000000000033660072674642500223200ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.Mips_const.*; public class Mips { public static class MemType extends Structure { public int base; public long disp; @Override public List getFieldOrder() { return Arrays.asList("base", "disp"); } } public static class OpValue extends Union { public int reg; public long imm; public MemType mem; @Override public List getFieldOrder() { return Arrays.asList("reg", "imm", "mem"); } } public static class Operand extends Structure { public int type; public OpValue value; public void read() { super.read(); if (type == MIPS_OP_MEM) value.setType(MemType.class); if (type == MIPS_OP_IMM) value.setType(Long.TYPE); if (type == MIPS_OP_REG) value.setType(Integer.TYPE); if (type == MIPS_OP_INVALID) return; readField("value"); } @Override public List getFieldOrder() { return Arrays.asList("type", "value"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public byte op_count; public Operand [] op; public UnionOpInfo() { op = new Operand[10]; } public void read() { readField("op_count"); op = new Operand[op_count]; if (op_count != 0) readField("op"); } @Override public List getFieldOrder() { return Arrays.asList("op_count", "op"); } } public static class OpInfo extends Capstone.OpInfo { public Operand [] op; public OpInfo(UnionOpInfo e) { op = e.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/Mips_const.java000064400000000000000000001156600072674642500235270ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Mips_const { public static final int MIPS_OP_INVALID = 0; public static final int MIPS_OP_REG = 1; public static final int MIPS_OP_IMM = 2; public static final int MIPS_OP_MEM = 3; public static final int MIPS_REG_INVALID = 0; public static final int MIPS_REG_PC = 1; public static final int MIPS_REG_0 = 2; public static final int MIPS_REG_1 = 3; public static final int MIPS_REG_2 = 4; public static final int MIPS_REG_3 = 5; public static final int MIPS_REG_4 = 6; public static final int MIPS_REG_5 = 7; public static final int MIPS_REG_6 = 8; public static final int MIPS_REG_7 = 9; public static final int MIPS_REG_8 = 10; public static final int MIPS_REG_9 = 11; public static final int MIPS_REG_10 = 12; public static final int MIPS_REG_11 = 13; public static final int MIPS_REG_12 = 14; public static final int MIPS_REG_13 = 15; public static final int MIPS_REG_14 = 16; public static final int MIPS_REG_15 = 17; public static final int MIPS_REG_16 = 18; public static final int MIPS_REG_17 = 19; public static final int MIPS_REG_18 = 20; public static final int MIPS_REG_19 = 21; public static final int MIPS_REG_20 = 22; public static final int MIPS_REG_21 = 23; public static final int MIPS_REG_22 = 24; public static final int MIPS_REG_23 = 25; public static final int MIPS_REG_24 = 26; public static final int MIPS_REG_25 = 27; public static final int MIPS_REG_26 = 28; public static final int MIPS_REG_27 = 29; public static final int MIPS_REG_28 = 30; public static final int MIPS_REG_29 = 31; public static final int MIPS_REG_30 = 32; public static final int MIPS_REG_31 = 33; public static final int MIPS_REG_DSPCCOND = 34; public static final int MIPS_REG_DSPCARRY = 35; public static final int MIPS_REG_DSPEFI = 36; public static final int MIPS_REG_DSPOUTFLAG = 37; public static final int MIPS_REG_DSPOUTFLAG16_19 = 38; public static final int MIPS_REG_DSPOUTFLAG20 = 39; public static final int MIPS_REG_DSPOUTFLAG21 = 40; public static final int MIPS_REG_DSPOUTFLAG22 = 41; public static final int MIPS_REG_DSPOUTFLAG23 = 42; public static final int MIPS_REG_DSPPOS = 43; public static final int MIPS_REG_DSPSCOUNT = 44; public static final int MIPS_REG_AC0 = 45; public static final int MIPS_REG_AC1 = 46; public static final int MIPS_REG_AC2 = 47; public static final int MIPS_REG_AC3 = 48; public static final int MIPS_REG_CC0 = 49; public static final int MIPS_REG_CC1 = 50; public static final int MIPS_REG_CC2 = 51; public static final int MIPS_REG_CC3 = 52; public static final int MIPS_REG_CC4 = 53; public static final int MIPS_REG_CC5 = 54; public static final int MIPS_REG_CC6 = 55; public static final int MIPS_REG_CC7 = 56; public static final int MIPS_REG_F0 = 57; public static final int MIPS_REG_F1 = 58; public static final int MIPS_REG_F2 = 59; public static final int MIPS_REG_F3 = 60; public static final int MIPS_REG_F4 = 61; public static final int MIPS_REG_F5 = 62; public static final int MIPS_REG_F6 = 63; public static final int MIPS_REG_F7 = 64; public static final int MIPS_REG_F8 = 65; public static final int MIPS_REG_F9 = 66; public static final int MIPS_REG_F10 = 67; public static final int MIPS_REG_F11 = 68; public static final int MIPS_REG_F12 = 69; public static final int MIPS_REG_F13 = 70; public static final int MIPS_REG_F14 = 71; public static final int MIPS_REG_F15 = 72; public static final int MIPS_REG_F16 = 73; public static final int MIPS_REG_F17 = 74; public static final int MIPS_REG_F18 = 75; public static final int MIPS_REG_F19 = 76; public static final int MIPS_REG_F20 = 77; public static final int MIPS_REG_F21 = 78; public static final int MIPS_REG_F22 = 79; public static final int MIPS_REG_F23 = 80; public static final int MIPS_REG_F24 = 81; public static final int MIPS_REG_F25 = 82; public static final int MIPS_REG_F26 = 83; public static final int MIPS_REG_F27 = 84; public static final int MIPS_REG_F28 = 85; public static final int MIPS_REG_F29 = 86; public static final int MIPS_REG_F30 = 87; public static final int MIPS_REG_F31 = 88; public static final int MIPS_REG_FCC0 = 89; public static final int MIPS_REG_FCC1 = 90; public static final int MIPS_REG_FCC2 = 91; public static final int MIPS_REG_FCC3 = 92; public static final int MIPS_REG_FCC4 = 93; public static final int MIPS_REG_FCC5 = 94; public static final int MIPS_REG_FCC6 = 95; public static final int MIPS_REG_FCC7 = 96; public static final int MIPS_REG_W0 = 97; public static final int MIPS_REG_W1 = 98; public static final int MIPS_REG_W2 = 99; public static final int MIPS_REG_W3 = 100; public static final int MIPS_REG_W4 = 101; public static final int MIPS_REG_W5 = 102; public static final int MIPS_REG_W6 = 103; public static final int MIPS_REG_W7 = 104; public static final int MIPS_REG_W8 = 105; public static final int MIPS_REG_W9 = 106; public static final int MIPS_REG_W10 = 107; public static final int MIPS_REG_W11 = 108; public static final int MIPS_REG_W12 = 109; public static final int MIPS_REG_W13 = 110; public static final int MIPS_REG_W14 = 111; public static final int MIPS_REG_W15 = 112; public static final int MIPS_REG_W16 = 113; public static final int MIPS_REG_W17 = 114; public static final int MIPS_REG_W18 = 115; public static final int MIPS_REG_W19 = 116; public static final int MIPS_REG_W20 = 117; public static final int MIPS_REG_W21 = 118; public static final int MIPS_REG_W22 = 119; public static final int MIPS_REG_W23 = 120; public static final int MIPS_REG_W24 = 121; public static final int MIPS_REG_W25 = 122; public static final int MIPS_REG_W26 = 123; public static final int MIPS_REG_W27 = 124; public static final int MIPS_REG_W28 = 125; public static final int MIPS_REG_W29 = 126; public static final int MIPS_REG_W30 = 127; public static final int MIPS_REG_W31 = 128; public static final int MIPS_REG_HI = 129; public static final int MIPS_REG_LO = 130; public static final int MIPS_REG_P0 = 131; public static final int MIPS_REG_P1 = 132; public static final int MIPS_REG_P2 = 133; public static final int MIPS_REG_MPL0 = 134; public static final int MIPS_REG_MPL1 = 135; public static final int MIPS_REG_MPL2 = 136; public static final int MIPS_REG_ENDING = 137; public static final int MIPS_REG_ZERO = MIPS_REG_0; public static final int MIPS_REG_AT = MIPS_REG_1; public static final int MIPS_REG_V0 = MIPS_REG_2; public static final int MIPS_REG_V1 = MIPS_REG_3; public static final int MIPS_REG_A0 = MIPS_REG_4; public static final int MIPS_REG_A1 = MIPS_REG_5; public static final int MIPS_REG_A2 = MIPS_REG_6; public static final int MIPS_REG_A3 = MIPS_REG_7; public static final int MIPS_REG_T0 = MIPS_REG_8; public static final int MIPS_REG_T1 = MIPS_REG_9; public static final int MIPS_REG_T2 = MIPS_REG_10; public static final int MIPS_REG_T3 = MIPS_REG_11; public static final int MIPS_REG_T4 = MIPS_REG_12; public static final int MIPS_REG_T5 = MIPS_REG_13; public static final int MIPS_REG_T6 = MIPS_REG_14; public static final int MIPS_REG_T7 = MIPS_REG_15; public static final int MIPS_REG_S0 = MIPS_REG_16; public static final int MIPS_REG_S1 = MIPS_REG_17; public static final int MIPS_REG_S2 = MIPS_REG_18; public static final int MIPS_REG_S3 = MIPS_REG_19; public static final int MIPS_REG_S4 = MIPS_REG_20; public static final int MIPS_REG_S5 = MIPS_REG_21; public static final int MIPS_REG_S6 = MIPS_REG_22; public static final int MIPS_REG_S7 = MIPS_REG_23; public static final int MIPS_REG_T8 = MIPS_REG_24; public static final int MIPS_REG_T9 = MIPS_REG_25; public static final int MIPS_REG_K0 = MIPS_REG_26; public static final int MIPS_REG_K1 = MIPS_REG_27; public static final int MIPS_REG_GP = MIPS_REG_28; public static final int MIPS_REG_SP = MIPS_REG_29; public static final int MIPS_REG_FP = MIPS_REG_30; public static final int MIPS_REG_S8 = MIPS_REG_30; public static final int MIPS_REG_RA = MIPS_REG_31; public static final int MIPS_REG_HI0 = MIPS_REG_AC0; public static final int MIPS_REG_HI1 = MIPS_REG_AC1; public static final int MIPS_REG_HI2 = MIPS_REG_AC2; public static final int MIPS_REG_HI3 = MIPS_REG_AC3; public static final int MIPS_REG_LO0 = MIPS_REG_HI0; public static final int MIPS_REG_LO1 = MIPS_REG_HI1; public static final int MIPS_REG_LO2 = MIPS_REG_HI2; public static final int MIPS_REG_LO3 = MIPS_REG_HI3; public static final int MIPS_INS_INVALID = 0; public static final int MIPS_INS_ABSQ_S = 1; public static final int MIPS_INS_ADD = 2; public static final int MIPS_INS_ADDIUPC = 3; public static final int MIPS_INS_ADDIUR1SP = 4; public static final int MIPS_INS_ADDIUR2 = 5; public static final int MIPS_INS_ADDIUS5 = 6; public static final int MIPS_INS_ADDIUSP = 7; public static final int MIPS_INS_ADDQH = 8; public static final int MIPS_INS_ADDQH_R = 9; public static final int MIPS_INS_ADDQ = 10; public static final int MIPS_INS_ADDQ_S = 11; public static final int MIPS_INS_ADDSC = 12; public static final int MIPS_INS_ADDS_A = 13; public static final int MIPS_INS_ADDS_S = 14; public static final int MIPS_INS_ADDS_U = 15; public static final int MIPS_INS_ADDU16 = 16; public static final int MIPS_INS_ADDUH = 17; public static final int MIPS_INS_ADDUH_R = 18; public static final int MIPS_INS_ADDU = 19; public static final int MIPS_INS_ADDU_S = 20; public static final int MIPS_INS_ADDVI = 21; public static final int MIPS_INS_ADDV = 22; public static final int MIPS_INS_ADDWC = 23; public static final int MIPS_INS_ADD_A = 24; public static final int MIPS_INS_ADDI = 25; public static final int MIPS_INS_ADDIU = 26; public static final int MIPS_INS_ALIGN = 27; public static final int MIPS_INS_ALUIPC = 28; public static final int MIPS_INS_AND = 29; public static final int MIPS_INS_AND16 = 30; public static final int MIPS_INS_ANDI16 = 31; public static final int MIPS_INS_ANDI = 32; public static final int MIPS_INS_APPEND = 33; public static final int MIPS_INS_ASUB_S = 34; public static final int MIPS_INS_ASUB_U = 35; public static final int MIPS_INS_AUI = 36; public static final int MIPS_INS_AUIPC = 37; public static final int MIPS_INS_AVER_S = 38; public static final int MIPS_INS_AVER_U = 39; public static final int MIPS_INS_AVE_S = 40; public static final int MIPS_INS_AVE_U = 41; public static final int MIPS_INS_B16 = 42; public static final int MIPS_INS_BADDU = 43; public static final int MIPS_INS_BAL = 44; public static final int MIPS_INS_BALC = 45; public static final int MIPS_INS_BALIGN = 46; public static final int MIPS_INS_BBIT0 = 47; public static final int MIPS_INS_BBIT032 = 48; public static final int MIPS_INS_BBIT1 = 49; public static final int MIPS_INS_BBIT132 = 50; public static final int MIPS_INS_BC = 51; public static final int MIPS_INS_BC0F = 52; public static final int MIPS_INS_BC0FL = 53; public static final int MIPS_INS_BC0T = 54; public static final int MIPS_INS_BC0TL = 55; public static final int MIPS_INS_BC1EQZ = 56; public static final int MIPS_INS_BC1F = 57; public static final int MIPS_INS_BC1FL = 58; public static final int MIPS_INS_BC1NEZ = 59; public static final int MIPS_INS_BC1T = 60; public static final int MIPS_INS_BC1TL = 61; public static final int MIPS_INS_BC2EQZ = 62; public static final int MIPS_INS_BC2F = 63; public static final int MIPS_INS_BC2FL = 64; public static final int MIPS_INS_BC2NEZ = 65; public static final int MIPS_INS_BC2T = 66; public static final int MIPS_INS_BC2TL = 67; public static final int MIPS_INS_BC3F = 68; public static final int MIPS_INS_BC3FL = 69; public static final int MIPS_INS_BC3T = 70; public static final int MIPS_INS_BC3TL = 71; public static final int MIPS_INS_BCLRI = 72; public static final int MIPS_INS_BCLR = 73; public static final int MIPS_INS_BEQ = 74; public static final int MIPS_INS_BEQC = 75; public static final int MIPS_INS_BEQL = 76; public static final int MIPS_INS_BEQZ16 = 77; public static final int MIPS_INS_BEQZALC = 78; public static final int MIPS_INS_BEQZC = 79; public static final int MIPS_INS_BGEC = 80; public static final int MIPS_INS_BGEUC = 81; public static final int MIPS_INS_BGEZ = 82; public static final int MIPS_INS_BGEZAL = 83; public static final int MIPS_INS_BGEZALC = 84; public static final int MIPS_INS_BGEZALL = 85; public static final int MIPS_INS_BGEZALS = 86; public static final int MIPS_INS_BGEZC = 87; public static final int MIPS_INS_BGEZL = 88; public static final int MIPS_INS_BGTZ = 89; public static final int MIPS_INS_BGTZALC = 90; public static final int MIPS_INS_BGTZC = 91; public static final int MIPS_INS_BGTZL = 92; public static final int MIPS_INS_BINSLI = 93; public static final int MIPS_INS_BINSL = 94; public static final int MIPS_INS_BINSRI = 95; public static final int MIPS_INS_BINSR = 96; public static final int MIPS_INS_BITREV = 97; public static final int MIPS_INS_BITSWAP = 98; public static final int MIPS_INS_BLEZ = 99; public static final int MIPS_INS_BLEZALC = 100; public static final int MIPS_INS_BLEZC = 101; public static final int MIPS_INS_BLEZL = 102; public static final int MIPS_INS_BLTC = 103; public static final int MIPS_INS_BLTUC = 104; public static final int MIPS_INS_BLTZ = 105; public static final int MIPS_INS_BLTZAL = 106; public static final int MIPS_INS_BLTZALC = 107; public static final int MIPS_INS_BLTZALL = 108; public static final int MIPS_INS_BLTZALS = 109; public static final int MIPS_INS_BLTZC = 110; public static final int MIPS_INS_BLTZL = 111; public static final int MIPS_INS_BMNZI = 112; public static final int MIPS_INS_BMNZ = 113; public static final int MIPS_INS_BMZI = 114; public static final int MIPS_INS_BMZ = 115; public static final int MIPS_INS_BNE = 116; public static final int MIPS_INS_BNEC = 117; public static final int MIPS_INS_BNEGI = 118; public static final int MIPS_INS_BNEG = 119; public static final int MIPS_INS_BNEL = 120; public static final int MIPS_INS_BNEZ16 = 121; public static final int MIPS_INS_BNEZALC = 122; public static final int MIPS_INS_BNEZC = 123; public static final int MIPS_INS_BNVC = 124; public static final int MIPS_INS_BNZ = 125; public static final int MIPS_INS_BOVC = 126; public static final int MIPS_INS_BPOSGE32 = 127; public static final int MIPS_INS_BREAK = 128; public static final int MIPS_INS_BREAK16 = 129; public static final int MIPS_INS_BSELI = 130; public static final int MIPS_INS_BSEL = 131; public static final int MIPS_INS_BSETI = 132; public static final int MIPS_INS_BSET = 133; public static final int MIPS_INS_BZ = 134; public static final int MIPS_INS_BEQZ = 135; public static final int MIPS_INS_B = 136; public static final int MIPS_INS_BNEZ = 137; public static final int MIPS_INS_BTEQZ = 138; public static final int MIPS_INS_BTNEZ = 139; public static final int MIPS_INS_CACHE = 140; public static final int MIPS_INS_CEIL = 141; public static final int MIPS_INS_CEQI = 142; public static final int MIPS_INS_CEQ = 143; public static final int MIPS_INS_CFC1 = 144; public static final int MIPS_INS_CFCMSA = 145; public static final int MIPS_INS_CINS = 146; public static final int MIPS_INS_CINS32 = 147; public static final int MIPS_INS_CLASS = 148; public static final int MIPS_INS_CLEI_S = 149; public static final int MIPS_INS_CLEI_U = 150; public static final int MIPS_INS_CLE_S = 151; public static final int MIPS_INS_CLE_U = 152; public static final int MIPS_INS_CLO = 153; public static final int MIPS_INS_CLTI_S = 154; public static final int MIPS_INS_CLTI_U = 155; public static final int MIPS_INS_CLT_S = 156; public static final int MIPS_INS_CLT_U = 157; public static final int MIPS_INS_CLZ = 158; public static final int MIPS_INS_CMPGDU = 159; public static final int MIPS_INS_CMPGU = 160; public static final int MIPS_INS_CMPU = 161; public static final int MIPS_INS_CMP = 162; public static final int MIPS_INS_COPY_S = 163; public static final int MIPS_INS_COPY_U = 164; public static final int MIPS_INS_CTC1 = 165; public static final int MIPS_INS_CTCMSA = 166; public static final int MIPS_INS_CVT = 167; public static final int MIPS_INS_C = 168; public static final int MIPS_INS_CMPI = 169; public static final int MIPS_INS_DADD = 170; public static final int MIPS_INS_DADDI = 171; public static final int MIPS_INS_DADDIU = 172; public static final int MIPS_INS_DADDU = 173; public static final int MIPS_INS_DAHI = 174; public static final int MIPS_INS_DALIGN = 175; public static final int MIPS_INS_DATI = 176; public static final int MIPS_INS_DAUI = 177; public static final int MIPS_INS_DBITSWAP = 178; public static final int MIPS_INS_DCLO = 179; public static final int MIPS_INS_DCLZ = 180; public static final int MIPS_INS_DDIV = 181; public static final int MIPS_INS_DDIVU = 182; public static final int MIPS_INS_DERET = 183; public static final int MIPS_INS_DEXT = 184; public static final int MIPS_INS_DEXTM = 185; public static final int MIPS_INS_DEXTU = 186; public static final int MIPS_INS_DI = 187; public static final int MIPS_INS_DINS = 188; public static final int MIPS_INS_DINSM = 189; public static final int MIPS_INS_DINSU = 190; public static final int MIPS_INS_DIV = 191; public static final int MIPS_INS_DIVU = 192; public static final int MIPS_INS_DIV_S = 193; public static final int MIPS_INS_DIV_U = 194; public static final int MIPS_INS_DLSA = 195; public static final int MIPS_INS_DMFC0 = 196; public static final int MIPS_INS_DMFC1 = 197; public static final int MIPS_INS_DMFC2 = 198; public static final int MIPS_INS_DMOD = 199; public static final int MIPS_INS_DMODU = 200; public static final int MIPS_INS_DMTC0 = 201; public static final int MIPS_INS_DMTC1 = 202; public static final int MIPS_INS_DMTC2 = 203; public static final int MIPS_INS_DMUH = 204; public static final int MIPS_INS_DMUHU = 205; public static final int MIPS_INS_DMUL = 206; public static final int MIPS_INS_DMULT = 207; public static final int MIPS_INS_DMULTU = 208; public static final int MIPS_INS_DMULU = 209; public static final int MIPS_INS_DOTP_S = 210; public static final int MIPS_INS_DOTP_U = 211; public static final int MIPS_INS_DPADD_S = 212; public static final int MIPS_INS_DPADD_U = 213; public static final int MIPS_INS_DPAQX_SA = 214; public static final int MIPS_INS_DPAQX_S = 215; public static final int MIPS_INS_DPAQ_SA = 216; public static final int MIPS_INS_DPAQ_S = 217; public static final int MIPS_INS_DPAU = 218; public static final int MIPS_INS_DPAX = 219; public static final int MIPS_INS_DPA = 220; public static final int MIPS_INS_DPOP = 221; public static final int MIPS_INS_DPSQX_SA = 222; public static final int MIPS_INS_DPSQX_S = 223; public static final int MIPS_INS_DPSQ_SA = 224; public static final int MIPS_INS_DPSQ_S = 225; public static final int MIPS_INS_DPSUB_S = 226; public static final int MIPS_INS_DPSUB_U = 227; public static final int MIPS_INS_DPSU = 228; public static final int MIPS_INS_DPSX = 229; public static final int MIPS_INS_DPS = 230; public static final int MIPS_INS_DROTR = 231; public static final int MIPS_INS_DROTR32 = 232; public static final int MIPS_INS_DROTRV = 233; public static final int MIPS_INS_DSBH = 234; public static final int MIPS_INS_DSHD = 235; public static final int MIPS_INS_DSLL = 236; public static final int MIPS_INS_DSLL32 = 237; public static final int MIPS_INS_DSLLV = 238; public static final int MIPS_INS_DSRA = 239; public static final int MIPS_INS_DSRA32 = 240; public static final int MIPS_INS_DSRAV = 241; public static final int MIPS_INS_DSRL = 242; public static final int MIPS_INS_DSRL32 = 243; public static final int MIPS_INS_DSRLV = 244; public static final int MIPS_INS_DSUB = 245; public static final int MIPS_INS_DSUBU = 246; public static final int MIPS_INS_EHB = 247; public static final int MIPS_INS_EI = 248; public static final int MIPS_INS_ERET = 249; public static final int MIPS_INS_EXT = 250; public static final int MIPS_INS_EXTP = 251; public static final int MIPS_INS_EXTPDP = 252; public static final int MIPS_INS_EXTPDPV = 253; public static final int MIPS_INS_EXTPV = 254; public static final int MIPS_INS_EXTRV_RS = 255; public static final int MIPS_INS_EXTRV_R = 256; public static final int MIPS_INS_EXTRV_S = 257; public static final int MIPS_INS_EXTRV = 258; public static final int MIPS_INS_EXTR_RS = 259; public static final int MIPS_INS_EXTR_R = 260; public static final int MIPS_INS_EXTR_S = 261; public static final int MIPS_INS_EXTR = 262; public static final int MIPS_INS_EXTS = 263; public static final int MIPS_INS_EXTS32 = 264; public static final int MIPS_INS_ABS = 265; public static final int MIPS_INS_FADD = 266; public static final int MIPS_INS_FCAF = 267; public static final int MIPS_INS_FCEQ = 268; public static final int MIPS_INS_FCLASS = 269; public static final int MIPS_INS_FCLE = 270; public static final int MIPS_INS_FCLT = 271; public static final int MIPS_INS_FCNE = 272; public static final int MIPS_INS_FCOR = 273; public static final int MIPS_INS_FCUEQ = 274; public static final int MIPS_INS_FCULE = 275; public static final int MIPS_INS_FCULT = 276; public static final int MIPS_INS_FCUNE = 277; public static final int MIPS_INS_FCUN = 278; public static final int MIPS_INS_FDIV = 279; public static final int MIPS_INS_FEXDO = 280; public static final int MIPS_INS_FEXP2 = 281; public static final int MIPS_INS_FEXUPL = 282; public static final int MIPS_INS_FEXUPR = 283; public static final int MIPS_INS_FFINT_S = 284; public static final int MIPS_INS_FFINT_U = 285; public static final int MIPS_INS_FFQL = 286; public static final int MIPS_INS_FFQR = 287; public static final int MIPS_INS_FILL = 288; public static final int MIPS_INS_FLOG2 = 289; public static final int MIPS_INS_FLOOR = 290; public static final int MIPS_INS_FMADD = 291; public static final int MIPS_INS_FMAX_A = 292; public static final int MIPS_INS_FMAX = 293; public static final int MIPS_INS_FMIN_A = 294; public static final int MIPS_INS_FMIN = 295; public static final int MIPS_INS_MOV = 296; public static final int MIPS_INS_FMSUB = 297; public static final int MIPS_INS_FMUL = 298; public static final int MIPS_INS_MUL = 299; public static final int MIPS_INS_NEG = 300; public static final int MIPS_INS_FRCP = 301; public static final int MIPS_INS_FRINT = 302; public static final int MIPS_INS_FRSQRT = 303; public static final int MIPS_INS_FSAF = 304; public static final int MIPS_INS_FSEQ = 305; public static final int MIPS_INS_FSLE = 306; public static final int MIPS_INS_FSLT = 307; public static final int MIPS_INS_FSNE = 308; public static final int MIPS_INS_FSOR = 309; public static final int MIPS_INS_FSQRT = 310; public static final int MIPS_INS_SQRT = 311; public static final int MIPS_INS_FSUB = 312; public static final int MIPS_INS_SUB = 313; public static final int MIPS_INS_FSUEQ = 314; public static final int MIPS_INS_FSULE = 315; public static final int MIPS_INS_FSULT = 316; public static final int MIPS_INS_FSUNE = 317; public static final int MIPS_INS_FSUN = 318; public static final int MIPS_INS_FTINT_S = 319; public static final int MIPS_INS_FTINT_U = 320; public static final int MIPS_INS_FTQ = 321; public static final int MIPS_INS_FTRUNC_S = 322; public static final int MIPS_INS_FTRUNC_U = 323; public static final int MIPS_INS_HADD_S = 324; public static final int MIPS_INS_HADD_U = 325; public static final int MIPS_INS_HSUB_S = 326; public static final int MIPS_INS_HSUB_U = 327; public static final int MIPS_INS_ILVEV = 328; public static final int MIPS_INS_ILVL = 329; public static final int MIPS_INS_ILVOD = 330; public static final int MIPS_INS_ILVR = 331; public static final int MIPS_INS_INS = 332; public static final int MIPS_INS_INSERT = 333; public static final int MIPS_INS_INSV = 334; public static final int MIPS_INS_INSVE = 335; public static final int MIPS_INS_J = 336; public static final int MIPS_INS_JAL = 337; public static final int MIPS_INS_JALR = 338; public static final int MIPS_INS_JALRS16 = 339; public static final int MIPS_INS_JALRS = 340; public static final int MIPS_INS_JALS = 341; public static final int MIPS_INS_JALX = 342; public static final int MIPS_INS_JIALC = 343; public static final int MIPS_INS_JIC = 344; public static final int MIPS_INS_JR = 345; public static final int MIPS_INS_JR16 = 346; public static final int MIPS_INS_JRADDIUSP = 347; public static final int MIPS_INS_JRC = 348; public static final int MIPS_INS_JALRC = 349; public static final int MIPS_INS_LB = 350; public static final int MIPS_INS_LBU16 = 351; public static final int MIPS_INS_LBUX = 352; public static final int MIPS_INS_LBU = 353; public static final int MIPS_INS_LD = 354; public static final int MIPS_INS_LDC1 = 355; public static final int MIPS_INS_LDC2 = 356; public static final int MIPS_INS_LDC3 = 357; public static final int MIPS_INS_LDI = 358; public static final int MIPS_INS_LDL = 359; public static final int MIPS_INS_LDPC = 360; public static final int MIPS_INS_LDR = 361; public static final int MIPS_INS_LDXC1 = 362; public static final int MIPS_INS_LH = 363; public static final int MIPS_INS_LHU16 = 364; public static final int MIPS_INS_LHX = 365; public static final int MIPS_INS_LHU = 366; public static final int MIPS_INS_LI16 = 367; public static final int MIPS_INS_LL = 368; public static final int MIPS_INS_LLD = 369; public static final int MIPS_INS_LSA = 370; public static final int MIPS_INS_LUXC1 = 371; public static final int MIPS_INS_LUI = 372; public static final int MIPS_INS_LW = 373; public static final int MIPS_INS_LW16 = 374; public static final int MIPS_INS_LWC1 = 375; public static final int MIPS_INS_LWC2 = 376; public static final int MIPS_INS_LWC3 = 377; public static final int MIPS_INS_LWL = 378; public static final int MIPS_INS_LWM16 = 379; public static final int MIPS_INS_LWM32 = 380; public static final int MIPS_INS_LWPC = 381; public static final int MIPS_INS_LWP = 382; public static final int MIPS_INS_LWR = 383; public static final int MIPS_INS_LWUPC = 384; public static final int MIPS_INS_LWU = 385; public static final int MIPS_INS_LWX = 386; public static final int MIPS_INS_LWXC1 = 387; public static final int MIPS_INS_LWXS = 388; public static final int MIPS_INS_LI = 389; public static final int MIPS_INS_MADD = 390; public static final int MIPS_INS_MADDF = 391; public static final int MIPS_INS_MADDR_Q = 392; public static final int MIPS_INS_MADDU = 393; public static final int MIPS_INS_MADDV = 394; public static final int MIPS_INS_MADD_Q = 395; public static final int MIPS_INS_MAQ_SA = 396; public static final int MIPS_INS_MAQ_S = 397; public static final int MIPS_INS_MAXA = 398; public static final int MIPS_INS_MAXI_S = 399; public static final int MIPS_INS_MAXI_U = 400; public static final int MIPS_INS_MAX_A = 401; public static final int MIPS_INS_MAX = 402; public static final int MIPS_INS_MAX_S = 403; public static final int MIPS_INS_MAX_U = 404; public static final int MIPS_INS_MFC0 = 405; public static final int MIPS_INS_MFC1 = 406; public static final int MIPS_INS_MFC2 = 407; public static final int MIPS_INS_MFHC1 = 408; public static final int MIPS_INS_MFHI = 409; public static final int MIPS_INS_MFLO = 410; public static final int MIPS_INS_MINA = 411; public static final int MIPS_INS_MINI_S = 412; public static final int MIPS_INS_MINI_U = 413; public static final int MIPS_INS_MIN_A = 414; public static final int MIPS_INS_MIN = 415; public static final int MIPS_INS_MIN_S = 416; public static final int MIPS_INS_MIN_U = 417; public static final int MIPS_INS_MOD = 418; public static final int MIPS_INS_MODSUB = 419; public static final int MIPS_INS_MODU = 420; public static final int MIPS_INS_MOD_S = 421; public static final int MIPS_INS_MOD_U = 422; public static final int MIPS_INS_MOVE = 423; public static final int MIPS_INS_MOVEP = 424; public static final int MIPS_INS_MOVF = 425; public static final int MIPS_INS_MOVN = 426; public static final int MIPS_INS_MOVT = 427; public static final int MIPS_INS_MOVZ = 428; public static final int MIPS_INS_MSUB = 429; public static final int MIPS_INS_MSUBF = 430; public static final int MIPS_INS_MSUBR_Q = 431; public static final int MIPS_INS_MSUBU = 432; public static final int MIPS_INS_MSUBV = 433; public static final int MIPS_INS_MSUB_Q = 434; public static final int MIPS_INS_MTC0 = 435; public static final int MIPS_INS_MTC1 = 436; public static final int MIPS_INS_MTC2 = 437; public static final int MIPS_INS_MTHC1 = 438; public static final int MIPS_INS_MTHI = 439; public static final int MIPS_INS_MTHLIP = 440; public static final int MIPS_INS_MTLO = 441; public static final int MIPS_INS_MTM0 = 442; public static final int MIPS_INS_MTM1 = 443; public static final int MIPS_INS_MTM2 = 444; public static final int MIPS_INS_MTP0 = 445; public static final int MIPS_INS_MTP1 = 446; public static final int MIPS_INS_MTP2 = 447; public static final int MIPS_INS_MUH = 448; public static final int MIPS_INS_MUHU = 449; public static final int MIPS_INS_MULEQ_S = 450; public static final int MIPS_INS_MULEU_S = 451; public static final int MIPS_INS_MULQ_RS = 452; public static final int MIPS_INS_MULQ_S = 453; public static final int MIPS_INS_MULR_Q = 454; public static final int MIPS_INS_MULSAQ_S = 455; public static final int MIPS_INS_MULSA = 456; public static final int MIPS_INS_MULT = 457; public static final int MIPS_INS_MULTU = 458; public static final int MIPS_INS_MULU = 459; public static final int MIPS_INS_MULV = 460; public static final int MIPS_INS_MUL_Q = 461; public static final int MIPS_INS_MUL_S = 462; public static final int MIPS_INS_NLOC = 463; public static final int MIPS_INS_NLZC = 464; public static final int MIPS_INS_NMADD = 465; public static final int MIPS_INS_NMSUB = 466; public static final int MIPS_INS_NOR = 467; public static final int MIPS_INS_NORI = 468; public static final int MIPS_INS_NOT16 = 469; public static final int MIPS_INS_NOT = 470; public static final int MIPS_INS_OR = 471; public static final int MIPS_INS_OR16 = 472; public static final int MIPS_INS_ORI = 473; public static final int MIPS_INS_PACKRL = 474; public static final int MIPS_INS_PAUSE = 475; public static final int MIPS_INS_PCKEV = 476; public static final int MIPS_INS_PCKOD = 477; public static final int MIPS_INS_PCNT = 478; public static final int MIPS_INS_PICK = 479; public static final int MIPS_INS_POP = 480; public static final int MIPS_INS_PRECEQU = 481; public static final int MIPS_INS_PRECEQ = 482; public static final int MIPS_INS_PRECEU = 483; public static final int MIPS_INS_PRECRQU_S = 484; public static final int MIPS_INS_PRECRQ = 485; public static final int MIPS_INS_PRECRQ_RS = 486; public static final int MIPS_INS_PRECR = 487; public static final int MIPS_INS_PRECR_SRA = 488; public static final int MIPS_INS_PRECR_SRA_R = 489; public static final int MIPS_INS_PREF = 490; public static final int MIPS_INS_PREPEND = 491; public static final int MIPS_INS_RADDU = 492; public static final int MIPS_INS_RDDSP = 493; public static final int MIPS_INS_RDHWR = 494; public static final int MIPS_INS_REPLV = 495; public static final int MIPS_INS_REPL = 496; public static final int MIPS_INS_RINT = 497; public static final int MIPS_INS_ROTR = 498; public static final int MIPS_INS_ROTRV = 499; public static final int MIPS_INS_ROUND = 500; public static final int MIPS_INS_SAT_S = 501; public static final int MIPS_INS_SAT_U = 502; public static final int MIPS_INS_SB = 503; public static final int MIPS_INS_SB16 = 504; public static final int MIPS_INS_SC = 505; public static final int MIPS_INS_SCD = 506; public static final int MIPS_INS_SD = 507; public static final int MIPS_INS_SDBBP = 508; public static final int MIPS_INS_SDBBP16 = 509; public static final int MIPS_INS_SDC1 = 510; public static final int MIPS_INS_SDC2 = 511; public static final int MIPS_INS_SDC3 = 512; public static final int MIPS_INS_SDL = 513; public static final int MIPS_INS_SDR = 514; public static final int MIPS_INS_SDXC1 = 515; public static final int MIPS_INS_SEB = 516; public static final int MIPS_INS_SEH = 517; public static final int MIPS_INS_SELEQZ = 518; public static final int MIPS_INS_SELNEZ = 519; public static final int MIPS_INS_SEL = 520; public static final int MIPS_INS_SEQ = 521; public static final int MIPS_INS_SEQI = 522; public static final int MIPS_INS_SH = 523; public static final int MIPS_INS_SH16 = 524; public static final int MIPS_INS_SHF = 525; public static final int MIPS_INS_SHILO = 526; public static final int MIPS_INS_SHILOV = 527; public static final int MIPS_INS_SHLLV = 528; public static final int MIPS_INS_SHLLV_S = 529; public static final int MIPS_INS_SHLL = 530; public static final int MIPS_INS_SHLL_S = 531; public static final int MIPS_INS_SHRAV = 532; public static final int MIPS_INS_SHRAV_R = 533; public static final int MIPS_INS_SHRA = 534; public static final int MIPS_INS_SHRA_R = 535; public static final int MIPS_INS_SHRLV = 536; public static final int MIPS_INS_SHRL = 537; public static final int MIPS_INS_SLDI = 538; public static final int MIPS_INS_SLD = 539; public static final int MIPS_INS_SLL = 540; public static final int MIPS_INS_SLL16 = 541; public static final int MIPS_INS_SLLI = 542; public static final int MIPS_INS_SLLV = 543; public static final int MIPS_INS_SLT = 544; public static final int MIPS_INS_SLTI = 545; public static final int MIPS_INS_SLTIU = 546; public static final int MIPS_INS_SLTU = 547; public static final int MIPS_INS_SNE = 548; public static final int MIPS_INS_SNEI = 549; public static final int MIPS_INS_SPLATI = 550; public static final int MIPS_INS_SPLAT = 551; public static final int MIPS_INS_SRA = 552; public static final int MIPS_INS_SRAI = 553; public static final int MIPS_INS_SRARI = 554; public static final int MIPS_INS_SRAR = 555; public static final int MIPS_INS_SRAV = 556; public static final int MIPS_INS_SRL = 557; public static final int MIPS_INS_SRL16 = 558; public static final int MIPS_INS_SRLI = 559; public static final int MIPS_INS_SRLRI = 560; public static final int MIPS_INS_SRLR = 561; public static final int MIPS_INS_SRLV = 562; public static final int MIPS_INS_SSNOP = 563; public static final int MIPS_INS_ST = 564; public static final int MIPS_INS_SUBQH = 565; public static final int MIPS_INS_SUBQH_R = 566; public static final int MIPS_INS_SUBQ = 567; public static final int MIPS_INS_SUBQ_S = 568; public static final int MIPS_INS_SUBSUS_U = 569; public static final int MIPS_INS_SUBSUU_S = 570; public static final int MIPS_INS_SUBS_S = 571; public static final int MIPS_INS_SUBS_U = 572; public static final int MIPS_INS_SUBU16 = 573; public static final int MIPS_INS_SUBUH = 574; public static final int MIPS_INS_SUBUH_R = 575; public static final int MIPS_INS_SUBU = 576; public static final int MIPS_INS_SUBU_S = 577; public static final int MIPS_INS_SUBVI = 578; public static final int MIPS_INS_SUBV = 579; public static final int MIPS_INS_SUXC1 = 580; public static final int MIPS_INS_SW = 581; public static final int MIPS_INS_SW16 = 582; public static final int MIPS_INS_SWC1 = 583; public static final int MIPS_INS_SWC2 = 584; public static final int MIPS_INS_SWC3 = 585; public static final int MIPS_INS_SWL = 586; public static final int MIPS_INS_SWM16 = 587; public static final int MIPS_INS_SWM32 = 588; public static final int MIPS_INS_SWP = 589; public static final int MIPS_INS_SWR = 590; public static final int MIPS_INS_SWXC1 = 591; public static final int MIPS_INS_SYNC = 592; public static final int MIPS_INS_SYNCI = 593; public static final int MIPS_INS_SYSCALL = 594; public static final int MIPS_INS_TEQ = 595; public static final int MIPS_INS_TEQI = 596; public static final int MIPS_INS_TGE = 597; public static final int MIPS_INS_TGEI = 598; public static final int MIPS_INS_TGEIU = 599; public static final int MIPS_INS_TGEU = 600; public static final int MIPS_INS_TLBP = 601; public static final int MIPS_INS_TLBR = 602; public static final int MIPS_INS_TLBWI = 603; public static final int MIPS_INS_TLBWR = 604; public static final int MIPS_INS_TLT = 605; public static final int MIPS_INS_TLTI = 606; public static final int MIPS_INS_TLTIU = 607; public static final int MIPS_INS_TLTU = 608; public static final int MIPS_INS_TNE = 609; public static final int MIPS_INS_TNEI = 610; public static final int MIPS_INS_TRUNC = 611; public static final int MIPS_INS_V3MULU = 612; public static final int MIPS_INS_VMM0 = 613; public static final int MIPS_INS_VMULU = 614; public static final int MIPS_INS_VSHF = 615; public static final int MIPS_INS_WAIT = 616; public static final int MIPS_INS_WRDSP = 617; public static final int MIPS_INS_WSBH = 618; public static final int MIPS_INS_XOR = 619; public static final int MIPS_INS_XOR16 = 620; public static final int MIPS_INS_XORI = 621; // some alias instructions public static final int MIPS_INS_NOP = 622; public static final int MIPS_INS_NEGU = 623; // special instructions public static final int MIPS_INS_JALR_HB = 624; public static final int MIPS_INS_JR_HB = 625; public static final int MIPS_INS_ENDING = 626; public static final int MIPS_GRP_INVALID = 0; public static final int MIPS_GRP_JUMP = 1; public static final int MIPS_GRP_CALL = 2; public static final int MIPS_GRP_RET = 3; public static final int MIPS_GRP_INT = 4; public static final int MIPS_GRP_IRET = 5; public static final int MIPS_GRP_PRIVILEGE = 6; public static final int MIPS_GRP_BRANCH_RELATIVE = 7; public static final int MIPS_GRP_BITCOUNT = 128; public static final int MIPS_GRP_DSP = 129; public static final int MIPS_GRP_DSPR2 = 130; public static final int MIPS_GRP_FPIDX = 131; public static final int MIPS_GRP_MSA = 132; public static final int MIPS_GRP_MIPS32R2 = 133; public static final int MIPS_GRP_MIPS64 = 134; public static final int MIPS_GRP_MIPS64R2 = 135; public static final int MIPS_GRP_SEINREG = 136; public static final int MIPS_GRP_STDENC = 137; public static final int MIPS_GRP_SWAP = 138; public static final int MIPS_GRP_MICROMIPS = 139; public static final int MIPS_GRP_MIPS16MODE = 140; public static final int MIPS_GRP_FP64BIT = 141; public static final int MIPS_GRP_NONANSFPMATH = 142; public static final int MIPS_GRP_NOTFP64BIT = 143; public static final int MIPS_GRP_NOTINMICROMIPS = 144; public static final int MIPS_GRP_NOTNACL = 145; public static final int MIPS_GRP_NOTMIPS32R6 = 146; public static final int MIPS_GRP_NOTMIPS64R6 = 147; public static final int MIPS_GRP_CNMIPS = 148; public static final int MIPS_GRP_MIPS32 = 149; public static final int MIPS_GRP_MIPS32R6 = 150; public static final int MIPS_GRP_MIPS64R6 = 151; public static final int MIPS_GRP_MIPS2 = 152; public static final int MIPS_GRP_MIPS3 = 153; public static final int MIPS_GRP_MIPS3_32 = 154; public static final int MIPS_GRP_MIPS3_32R2 = 155; public static final int MIPS_GRP_MIPS4_32 = 156; public static final int MIPS_GRP_MIPS4_32R2 = 157; public static final int MIPS_GRP_MIPS5_32R2 = 158; public static final int MIPS_GRP_GP32BIT = 159; public static final int MIPS_GRP_GP64BIT = 160; public static final int MIPS_GRP_ENDING = 161; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Ppc.java000064400000000000000000000043630072674642500221300ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.Ppc_const.*; public class Ppc { public static class MemType extends Structure { public int base; public int disp; @Override public List getFieldOrder() { return Arrays.asList("base", "disp"); } } public static class CrxType extends Structure { public int scale; public int reg; public int cond; @Override public List getFieldOrder() { return Arrays.asList("scale", "reg", "cond"); } } public static class OpValue extends Union { public int reg; public long imm; public MemType mem; public CrxType crx; } public static class Operand extends Structure { public int type; public OpValue value; public void read() { readField("type"); if (type == PPC_OP_MEM) value.setType(MemType.class); if (type == PPC_OP_CRX) value.setType(CrxType.class); if (type == PPC_OP_IMM || type == PPC_OP_REG) value.setType(Integer.TYPE); if (type == PPC_OP_INVALID) return; readField("value"); } @Override public List getFieldOrder() { return Arrays.asList("type", "value"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public int bc; public int bh; public byte update_cr0; public byte op_count; public Operand [] op; public UnionOpInfo() { op = new Operand[8]; } public void read() { readField("bc"); readField("bh"); readField("update_cr0"); readField("op_count"); op = new Operand[op_count]; if (op_count != 0) readField("op"); } @Override public List getFieldOrder() { return Arrays.asList("bc", "bh", "update_cr0", "op_count", "op"); } } public static class OpInfo extends Capstone.OpInfo { public int bc; public int bh; public boolean updateCr0; public Operand [] op; public OpInfo(UnionOpInfo op_info) { bc = op_info.bc; bh = op_info.bh; updateCr0 = (op_info.update_cr0 > 0); op = op_info.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/Ppc_const.java000064400000000000000000002661250072674642500233440ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Ppc_const { public static final int PPC_BC_INVALID = 0; public static final int PPC_BC_LT = (0<<5)|12; public static final int PPC_BC_LE = (1<<5)|4; public static final int PPC_BC_EQ = (2<<5)|12; public static final int PPC_BC_GE = (0<<5)|4; public static final int PPC_BC_GT = (1<<5)|12; public static final int PPC_BC_NE = (2<<5)|4; public static final int PPC_BC_UN = (3<<5)|12; public static final int PPC_BC_NU = (3<<5)|4; public static final int PPC_BC_SO = (4<<5)|12; public static final int PPC_BC_NS = (4<<5)|4; public static final int PPC_BH_INVALID = 0; public static final int PPC_BH_PLUS = 1; public static final int PPC_BH_MINUS = 2; public static final int PPC_OP_INVALID = 0; public static final int PPC_OP_REG = 1; public static final int PPC_OP_IMM = 2; public static final int PPC_OP_MEM = 3; public static final int PPC_OP_CRX = 64; public static final int PPC_REG_INVALID = 0; public static final int PPC_REG_CARRY = 2; public static final int PPC_REG_CTR = 3; public static final int PPC_REG_LR = 5; public static final int PPC_REG_RM = 6; public static final int PPC_REG_VRSAVE = 8; public static final int PPC_REG_XER = 9; public static final int PPC_REG_ZERO = 10; public static final int PPC_REG_CR0 = 12; public static final int PPC_REG_CR1 = 13; public static final int PPC_REG_CR2 = 14; public static final int PPC_REG_CR3 = 15; public static final int PPC_REG_CR4 = 16; public static final int PPC_REG_CR5 = 17; public static final int PPC_REG_CR6 = 18; public static final int PPC_REG_CR7 = 19; public static final int PPC_REG_CTR8 = 20; public static final int PPC_REG_F0 = 21; public static final int PPC_REG_F1 = 22; public static final int PPC_REG_F2 = 23; public static final int PPC_REG_F3 = 24; public static final int PPC_REG_F4 = 25; public static final int PPC_REG_F5 = 26; public static final int PPC_REG_F6 = 27; public static final int PPC_REG_F7 = 28; public static final int PPC_REG_F8 = 29; public static final int PPC_REG_F9 = 30; public static final int PPC_REG_F10 = 31; public static final int PPC_REG_F11 = 32; public static final int PPC_REG_F12 = 33; public static final int PPC_REG_F13 = 34; public static final int PPC_REG_F14 = 35; public static final int PPC_REG_F15 = 36; public static final int PPC_REG_F16 = 37; public static final int PPC_REG_F17 = 38; public static final int PPC_REG_F18 = 39; public static final int PPC_REG_F19 = 40; public static final int PPC_REG_F20 = 41; public static final int PPC_REG_F21 = 42; public static final int PPC_REG_F22 = 43; public static final int PPC_REG_F23 = 44; public static final int PPC_REG_F24 = 45; public static final int PPC_REG_F25 = 46; public static final int PPC_REG_F26 = 47; public static final int PPC_REG_F27 = 48; public static final int PPC_REG_F28 = 49; public static final int PPC_REG_F29 = 50; public static final int PPC_REG_F30 = 51; public static final int PPC_REG_F31 = 52; public static final int PPC_REG_LR8 = 54; public static final int PPC_REG_Q0 = 55; public static final int PPC_REG_Q1 = 56; public static final int PPC_REG_Q2 = 57; public static final int PPC_REG_Q3 = 58; public static final int PPC_REG_Q4 = 59; public static final int PPC_REG_Q5 = 60; public static final int PPC_REG_Q6 = 61; public static final int PPC_REG_Q7 = 62; public static final int PPC_REG_Q8 = 63; public static final int PPC_REG_Q9 = 64; public static final int PPC_REG_Q10 = 65; public static final int PPC_REG_Q11 = 66; public static final int PPC_REG_Q12 = 67; public static final int PPC_REG_Q13 = 68; public static final int PPC_REG_Q14 = 69; public static final int PPC_REG_Q15 = 70; public static final int PPC_REG_Q16 = 71; public static final int PPC_REG_Q17 = 72; public static final int PPC_REG_Q18 = 73; public static final int PPC_REG_Q19 = 74; public static final int PPC_REG_Q20 = 75; public static final int PPC_REG_Q21 = 76; public static final int PPC_REG_Q22 = 77; public static final int PPC_REG_Q23 = 78; public static final int PPC_REG_Q24 = 79; public static final int PPC_REG_Q25 = 80; public static final int PPC_REG_Q26 = 81; public static final int PPC_REG_Q27 = 82; public static final int PPC_REG_Q28 = 83; public static final int PPC_REG_Q29 = 84; public static final int PPC_REG_Q30 = 85; public static final int PPC_REG_Q31 = 86; public static final int PPC_REG_R0 = 87; public static final int PPC_REG_R1 = 88; public static final int PPC_REG_R2 = 89; public static final int PPC_REG_R3 = 90; public static final int PPC_REG_R4 = 91; public static final int PPC_REG_R5 = 92; public static final int PPC_REG_R6 = 93; public static final int PPC_REG_R7 = 94; public static final int PPC_REG_R8 = 95; public static final int PPC_REG_R9 = 96; public static final int PPC_REG_R10 = 97; public static final int PPC_REG_R11 = 98; public static final int PPC_REG_R12 = 99; public static final int PPC_REG_R13 = 100; public static final int PPC_REG_R14 = 101; public static final int PPC_REG_R15 = 102; public static final int PPC_REG_R16 = 103; public static final int PPC_REG_R17 = 104; public static final int PPC_REG_R18 = 105; public static final int PPC_REG_R19 = 106; public static final int PPC_REG_R20 = 107; public static final int PPC_REG_R21 = 108; public static final int PPC_REG_R22 = 109; public static final int PPC_REG_R23 = 110; public static final int PPC_REG_R24 = 111; public static final int PPC_REG_R25 = 112; public static final int PPC_REG_R26 = 113; public static final int PPC_REG_R27 = 114; public static final int PPC_REG_R28 = 115; public static final int PPC_REG_R29 = 116; public static final int PPC_REG_R30 = 117; public static final int PPC_REG_R31 = 118; public static final int PPC_REG_V0 = 151; public static final int PPC_REG_V1 = 152; public static final int PPC_REG_V2 = 153; public static final int PPC_REG_V3 = 154; public static final int PPC_REG_V4 = 155; public static final int PPC_REG_V5 = 156; public static final int PPC_REG_V6 = 157; public static final int PPC_REG_V7 = 158; public static final int PPC_REG_V8 = 159; public static final int PPC_REG_V9 = 160; public static final int PPC_REG_V10 = 161; public static final int PPC_REG_V11 = 162; public static final int PPC_REG_V12 = 163; public static final int PPC_REG_V13 = 164; public static final int PPC_REG_V14 = 165; public static final int PPC_REG_V15 = 166; public static final int PPC_REG_V16 = 167; public static final int PPC_REG_V17 = 168; public static final int PPC_REG_V18 = 169; public static final int PPC_REG_V19 = 170; public static final int PPC_REG_V20 = 171; public static final int PPC_REG_V21 = 172; public static final int PPC_REG_V22 = 173; public static final int PPC_REG_V23 = 174; public static final int PPC_REG_V24 = 175; public static final int PPC_REG_V25 = 176; public static final int PPC_REG_V26 = 177; public static final int PPC_REG_V27 = 178; public static final int PPC_REG_V28 = 179; public static final int PPC_REG_V29 = 180; public static final int PPC_REG_V30 = 181; public static final int PPC_REG_V31 = 182; public static final int PPC_REG_VS0 = 215; public static final int PPC_REG_VS1 = 216; public static final int PPC_REG_VS2 = 217; public static final int PPC_REG_VS3 = 218; public static final int PPC_REG_VS4 = 219; public static final int PPC_REG_VS5 = 220; public static final int PPC_REG_VS6 = 221; public static final int PPC_REG_VS7 = 222; public static final int PPC_REG_VS8 = 223; public static final int PPC_REG_VS9 = 224; public static final int PPC_REG_VS10 = 225; public static final int PPC_REG_VS11 = 226; public static final int PPC_REG_VS12 = 227; public static final int PPC_REG_VS13 = 228; public static final int PPC_REG_VS14 = 229; public static final int PPC_REG_VS15 = 230; public static final int PPC_REG_VS16 = 231; public static final int PPC_REG_VS17 = 232; public static final int PPC_REG_VS18 = 233; public static final int PPC_REG_VS19 = 234; public static final int PPC_REG_VS20 = 235; public static final int PPC_REG_VS21 = 236; public static final int PPC_REG_VS22 = 237; public static final int PPC_REG_VS23 = 238; public static final int PPC_REG_VS24 = 239; public static final int PPC_REG_VS25 = 240; public static final int PPC_REG_VS26 = 241; public static final int PPC_REG_VS27 = 242; public static final int PPC_REG_VS28 = 243; public static final int PPC_REG_VS29 = 244; public static final int PPC_REG_VS30 = 245; public static final int PPC_REG_VS31 = 246; public static final int PPC_REG_VS32 = 247; public static final int PPC_REG_VS33 = 248; public static final int PPC_REG_VS34 = 249; public static final int PPC_REG_VS35 = 250; public static final int PPC_REG_VS36 = 251; public static final int PPC_REG_VS37 = 252; public static final int PPC_REG_VS38 = 253; public static final int PPC_REG_VS39 = 254; public static final int PPC_REG_VS40 = 255; public static final int PPC_REG_VS41 = 256; public static final int PPC_REG_VS42 = 257; public static final int PPC_REG_VS43 = 258; public static final int PPC_REG_VS44 = 259; public static final int PPC_REG_VS45 = 260; public static final int PPC_REG_VS46 = 261; public static final int PPC_REG_VS47 = 262; public static final int PPC_REG_VS48 = 263; public static final int PPC_REG_VS49 = 264; public static final int PPC_REG_VS50 = 265; public static final int PPC_REG_VS51 = 266; public static final int PPC_REG_VS52 = 267; public static final int PPC_REG_VS53 = 268; public static final int PPC_REG_VS54 = 269; public static final int PPC_REG_VS55 = 270; public static final int PPC_REG_VS56 = 271; public static final int PPC_REG_VS57 = 272; public static final int PPC_REG_VS58 = 273; public static final int PPC_REG_VS59 = 274; public static final int PPC_REG_VS60 = 275; public static final int PPC_REG_VS61 = 276; public static final int PPC_REG_VS62 = 277; public static final int PPC_REG_VS63 = 278; public static final int PPC_REG_CR0EQ = 312; public static final int PPC_REG_CR1EQ = 313; public static final int PPC_REG_CR2EQ = 314; public static final int PPC_REG_CR3EQ = 315; public static final int PPC_REG_CR4EQ = 316; public static final int PPC_REG_CR5EQ = 317; public static final int PPC_REG_CR6EQ = 318; public static final int PPC_REG_CR7EQ = 319; public static final int PPC_REG_CR0GT = 320; public static final int PPC_REG_CR1GT = 321; public static final int PPC_REG_CR2GT = 322; public static final int PPC_REG_CR3GT = 323; public static final int PPC_REG_CR4GT = 324; public static final int PPC_REG_CR5GT = 325; public static final int PPC_REG_CR6GT = 326; public static final int PPC_REG_CR7GT = 327; public static final int PPC_REG_CR0LT = 328; public static final int PPC_REG_CR1LT = 329; public static final int PPC_REG_CR2LT = 330; public static final int PPC_REG_CR3LT = 331; public static final int PPC_REG_CR4LT = 332; public static final int PPC_REG_CR5LT = 333; public static final int PPC_REG_CR6LT = 334; public static final int PPC_REG_CR7LT = 335; public static final int PPC_REG_CR0UN = 336; public static final int PPC_REG_CR1UN = 337; public static final int PPC_REG_CR2UN = 338; public static final int PPC_REG_CR3UN = 339; public static final int PPC_REG_CR4UN = 340; public static final int PPC_REG_CR5UN = 341; public static final int PPC_REG_CR6UN = 342; public static final int PPC_REG_CR7UN = 343; public static final int PPC_REG_ENDING = 344; public static final int PPC_INS_INVALID = 0; public static final int PPC_INS_ADD = 1; public static final int PPC_INS_ADDC = 2; public static final int PPC_INS_ADDE = 3; public static final int PPC_INS_ADDI = 4; public static final int PPC_INS_ADDIC = 5; public static final int PPC_INS_ADDIS = 6; public static final int PPC_INS_ADDME = 7; public static final int PPC_INS_ADDPCIS = 8; public static final int PPC_INS_ADDZE = 9; public static final int PPC_INS_AND = 10; public static final int PPC_INS_ANDC = 11; public static final int PPC_INS_ANDI = 12; public static final int PPC_INS_ANDIS = 13; public static final int PPC_INS_ATTN = 14; public static final int PPC_INS_B = 15; public static final int PPC_INS_BA = 16; public static final int PPC_INS_BC = 17; public static final int PPC_INS_BCA = 18; public static final int PPC_INS_BCCTR = 19; public static final int PPC_INS_BCCTRL = 20; public static final int PPC_INS_BCDCFN = 21; public static final int PPC_INS_BCDCFSQ = 22; public static final int PPC_INS_BCDCFZ = 23; public static final int PPC_INS_BCDCPSGN = 24; public static final int PPC_INS_BCDCTN = 25; public static final int PPC_INS_BCDCTSQ = 26; public static final int PPC_INS_BCDCTZ = 27; public static final int PPC_INS_BCDS = 28; public static final int PPC_INS_BCDSETSGN = 29; public static final int PPC_INS_BCDSR = 30; public static final int PPC_INS_BCDTRUNC = 31; public static final int PPC_INS_BCDUS = 32; public static final int PPC_INS_BCDUTRUNC = 33; public static final int PPC_INS_BCL = 34; public static final int PPC_INS_BCLA = 35; public static final int PPC_INS_BCLR = 36; public static final int PPC_INS_BCLRL = 37; public static final int PPC_INS_BCTR = 38; public static final int PPC_INS_BCTRL = 39; public static final int PPC_INS_BDNZ = 40; public static final int PPC_INS_BDNZA = 41; public static final int PPC_INS_BDNZF = 42; public static final int PPC_INS_BDNZFA = 43; public static final int PPC_INS_BDNZFL = 44; public static final int PPC_INS_BDNZFLA = 45; public static final int PPC_INS_BDNZFLR = 46; public static final int PPC_INS_BDNZFLRL = 47; public static final int PPC_INS_BDNZL = 48; public static final int PPC_INS_BDNZLA = 49; public static final int PPC_INS_BDNZLR = 50; public static final int PPC_INS_BDNZLRL = 51; public static final int PPC_INS_BDNZT = 52; public static final int PPC_INS_BDNZTA = 53; public static final int PPC_INS_BDNZTL = 54; public static final int PPC_INS_BDNZTLA = 55; public static final int PPC_INS_BDNZTLR = 56; public static final int PPC_INS_BDNZTLRL = 57; public static final int PPC_INS_BDZ = 58; public static final int PPC_INS_BDZA = 59; public static final int PPC_INS_BDZF = 60; public static final int PPC_INS_BDZFA = 61; public static final int PPC_INS_BDZFL = 62; public static final int PPC_INS_BDZFLA = 63; public static final int PPC_INS_BDZFLR = 64; public static final int PPC_INS_BDZFLRL = 65; public static final int PPC_INS_BDZL = 66; public static final int PPC_INS_BDZLA = 67; public static final int PPC_INS_BDZLR = 68; public static final int PPC_INS_BDZLRL = 69; public static final int PPC_INS_BDZT = 70; public static final int PPC_INS_BDZTA = 71; public static final int PPC_INS_BDZTL = 72; public static final int PPC_INS_BDZTLA = 73; public static final int PPC_INS_BDZTLR = 74; public static final int PPC_INS_BDZTLRL = 75; public static final int PPC_INS_BEQ = 76; public static final int PPC_INS_BEQA = 77; public static final int PPC_INS_BEQCTR = 78; public static final int PPC_INS_BEQCTRL = 79; public static final int PPC_INS_BEQL = 80; public static final int PPC_INS_BEQLA = 81; public static final int PPC_INS_BEQLR = 82; public static final int PPC_INS_BEQLRL = 83; public static final int PPC_INS_BF = 84; public static final int PPC_INS_BFA = 85; public static final int PPC_INS_BFCTR = 86; public static final int PPC_INS_BFCTRL = 87; public static final int PPC_INS_BFL = 88; public static final int PPC_INS_BFLA = 89; public static final int PPC_INS_BFLR = 90; public static final int PPC_INS_BFLRL = 91; public static final int PPC_INS_BGE = 92; public static final int PPC_INS_BGEA = 93; public static final int PPC_INS_BGECTR = 94; public static final int PPC_INS_BGECTRL = 95; public static final int PPC_INS_BGEL = 96; public static final int PPC_INS_BGELA = 97; public static final int PPC_INS_BGELR = 98; public static final int PPC_INS_BGELRL = 99; public static final int PPC_INS_BGT = 100; public static final int PPC_INS_BGTA = 101; public static final int PPC_INS_BGTCTR = 102; public static final int PPC_INS_BGTCTRL = 103; public static final int PPC_INS_BGTL = 104; public static final int PPC_INS_BGTLA = 105; public static final int PPC_INS_BGTLR = 106; public static final int PPC_INS_BGTLRL = 107; public static final int PPC_INS_BL = 108; public static final int PPC_INS_BLA = 109; public static final int PPC_INS_BLE = 110; public static final int PPC_INS_BLEA = 111; public static final int PPC_INS_BLECTR = 112; public static final int PPC_INS_BLECTRL = 113; public static final int PPC_INS_BLEL = 114; public static final int PPC_INS_BLELA = 115; public static final int PPC_INS_BLELR = 116; public static final int PPC_INS_BLELRL = 117; public static final int PPC_INS_BLR = 118; public static final int PPC_INS_BLRL = 119; public static final int PPC_INS_BLT = 120; public static final int PPC_INS_BLTA = 121; public static final int PPC_INS_BLTCTR = 122; public static final int PPC_INS_BLTCTRL = 123; public static final int PPC_INS_BLTL = 124; public static final int PPC_INS_BLTLA = 125; public static final int PPC_INS_BLTLR = 126; public static final int PPC_INS_BLTLRL = 127; public static final int PPC_INS_BNE = 128; public static final int PPC_INS_BNEA = 129; public static final int PPC_INS_BNECTR = 130; public static final int PPC_INS_BNECTRL = 131; public static final int PPC_INS_BNEL = 132; public static final int PPC_INS_BNELA = 133; public static final int PPC_INS_BNELR = 134; public static final int PPC_INS_BNELRL = 135; public static final int PPC_INS_BNG = 136; public static final int PPC_INS_BNGA = 137; public static final int PPC_INS_BNGCTR = 138; public static final int PPC_INS_BNGCTRL = 139; public static final int PPC_INS_BNGL = 140; public static final int PPC_INS_BNGLA = 141; public static final int PPC_INS_BNGLR = 142; public static final int PPC_INS_BNGLRL = 143; public static final int PPC_INS_BNL = 144; public static final int PPC_INS_BNLA = 145; public static final int PPC_INS_BNLCTR = 146; public static final int PPC_INS_BNLCTRL = 147; public static final int PPC_INS_BNLL = 148; public static final int PPC_INS_BNLLA = 149; public static final int PPC_INS_BNLLR = 150; public static final int PPC_INS_BNLLRL = 151; public static final int PPC_INS_BNS = 152; public static final int PPC_INS_BNSA = 153; public static final int PPC_INS_BNSCTR = 154; public static final int PPC_INS_BNSCTRL = 155; public static final int PPC_INS_BNSL = 156; public static final int PPC_INS_BNSLA = 157; public static final int PPC_INS_BNSLR = 158; public static final int PPC_INS_BNSLRL = 159; public static final int PPC_INS_BNU = 160; public static final int PPC_INS_BNUA = 161; public static final int PPC_INS_BNUCTR = 162; public static final int PPC_INS_BNUCTRL = 163; public static final int PPC_INS_BNUL = 164; public static final int PPC_INS_BNULA = 165; public static final int PPC_INS_BNULR = 166; public static final int PPC_INS_BNULRL = 167; public static final int PPC_INS_BPERMD = 168; public static final int PPC_INS_BRINC = 169; public static final int PPC_INS_BSO = 170; public static final int PPC_INS_BSOA = 171; public static final int PPC_INS_BSOCTR = 172; public static final int PPC_INS_BSOCTRL = 173; public static final int PPC_INS_BSOL = 174; public static final int PPC_INS_BSOLA = 175; public static final int PPC_INS_BSOLR = 176; public static final int PPC_INS_BSOLRL = 177; public static final int PPC_INS_BT = 178; public static final int PPC_INS_BTA = 179; public static final int PPC_INS_BTCTR = 180; public static final int PPC_INS_BTCTRL = 181; public static final int PPC_INS_BTL = 182; public static final int PPC_INS_BTLA = 183; public static final int PPC_INS_BTLR = 184; public static final int PPC_INS_BTLRL = 185; public static final int PPC_INS_BUN = 186; public static final int PPC_INS_BUNA = 187; public static final int PPC_INS_BUNCTR = 188; public static final int PPC_INS_BUNCTRL = 189; public static final int PPC_INS_BUNL = 190; public static final int PPC_INS_BUNLA = 191; public static final int PPC_INS_BUNLR = 192; public static final int PPC_INS_BUNLRL = 193; public static final int PPC_INS_CLRBHRB = 194; public static final int PPC_INS_CLRLDI = 195; public static final int PPC_INS_CLRLSLDI = 196; public static final int PPC_INS_CLRLSLWI = 197; public static final int PPC_INS_CLRLWI = 198; public static final int PPC_INS_CLRRDI = 199; public static final int PPC_INS_CLRRWI = 200; public static final int PPC_INS_CMP = 201; public static final int PPC_INS_CMPB = 202; public static final int PPC_INS_CMPD = 203; public static final int PPC_INS_CMPDI = 204; public static final int PPC_INS_CMPEQB = 205; public static final int PPC_INS_CMPI = 206; public static final int PPC_INS_CMPL = 207; public static final int PPC_INS_CMPLD = 208; public static final int PPC_INS_CMPLDI = 209; public static final int PPC_INS_CMPLI = 210; public static final int PPC_INS_CMPLW = 211; public static final int PPC_INS_CMPLWI = 212; public static final int PPC_INS_CMPRB = 213; public static final int PPC_INS_CMPW = 214; public static final int PPC_INS_CMPWI = 215; public static final int PPC_INS_CNTLZD = 216; public static final int PPC_INS_CNTLZW = 217; public static final int PPC_INS_CNTTZD = 218; public static final int PPC_INS_CNTTZW = 219; public static final int PPC_INS_COPY = 220; public static final int PPC_INS_COPY_FIRST = 221; public static final int PPC_INS_CP_ABORT = 222; public static final int PPC_INS_CRAND = 223; public static final int PPC_INS_CRANDC = 224; public static final int PPC_INS_CRCLR = 225; public static final int PPC_INS_CREQV = 226; public static final int PPC_INS_CRMOVE = 227; public static final int PPC_INS_CRNAND = 228; public static final int PPC_INS_CRNOR = 229; public static final int PPC_INS_CRNOT = 230; public static final int PPC_INS_CROR = 231; public static final int PPC_INS_CRORC = 232; public static final int PPC_INS_CRSET = 233; public static final int PPC_INS_CRXOR = 234; public static final int PPC_INS_DARN = 235; public static final int PPC_INS_DCBA = 236; public static final int PPC_INS_DCBF = 237; public static final int PPC_INS_DCBFEP = 238; public static final int PPC_INS_DCBFL = 239; public static final int PPC_INS_DCBFLP = 240; public static final int PPC_INS_DCBI = 241; public static final int PPC_INS_DCBST = 242; public static final int PPC_INS_DCBSTEP = 243; public static final int PPC_INS_DCBT = 244; public static final int PPC_INS_DCBTCT = 245; public static final int PPC_INS_DCBTDS = 246; public static final int PPC_INS_DCBTEP = 247; public static final int PPC_INS_DCBTST = 248; public static final int PPC_INS_DCBTSTCT = 249; public static final int PPC_INS_DCBTSTDS = 250; public static final int PPC_INS_DCBTSTEP = 251; public static final int PPC_INS_DCBTSTT = 252; public static final int PPC_INS_DCBTT = 253; public static final int PPC_INS_DCBZ = 254; public static final int PPC_INS_DCBZEP = 255; public static final int PPC_INS_DCBZL = 256; public static final int PPC_INS_DCBZLEP = 257; public static final int PPC_INS_DCCCI = 258; public static final int PPC_INS_DCI = 259; public static final int PPC_INS_DIVD = 260; public static final int PPC_INS_DIVDE = 261; public static final int PPC_INS_DIVDEU = 262; public static final int PPC_INS_DIVDU = 263; public static final int PPC_INS_DIVW = 264; public static final int PPC_INS_DIVWE = 265; public static final int PPC_INS_DIVWEU = 266; public static final int PPC_INS_DIVWU = 267; public static final int PPC_INS_DSS = 268; public static final int PPC_INS_DSSALL = 269; public static final int PPC_INS_DST = 270; public static final int PPC_INS_DSTST = 271; public static final int PPC_INS_DSTSTT = 272; public static final int PPC_INS_DSTT = 273; public static final int PPC_INS_EFDABS = 274; public static final int PPC_INS_EFDADD = 275; public static final int PPC_INS_EFDCFS = 276; public static final int PPC_INS_EFDCFSF = 277; public static final int PPC_INS_EFDCFSI = 278; public static final int PPC_INS_EFDCFSID = 279; public static final int PPC_INS_EFDCFUF = 280; public static final int PPC_INS_EFDCFUI = 281; public static final int PPC_INS_EFDCFUID = 282; public static final int PPC_INS_EFDCMPEQ = 283; public static final int PPC_INS_EFDCMPGT = 284; public static final int PPC_INS_EFDCMPLT = 285; public static final int PPC_INS_EFDCTSF = 286; public static final int PPC_INS_EFDCTSI = 287; public static final int PPC_INS_EFDCTSIDZ = 288; public static final int PPC_INS_EFDCTSIZ = 289; public static final int PPC_INS_EFDCTUF = 290; public static final int PPC_INS_EFDCTUI = 291; public static final int PPC_INS_EFDCTUIDZ = 292; public static final int PPC_INS_EFDCTUIZ = 293; public static final int PPC_INS_EFDDIV = 294; public static final int PPC_INS_EFDMUL = 295; public static final int PPC_INS_EFDNABS = 296; public static final int PPC_INS_EFDNEG = 297; public static final int PPC_INS_EFDSUB = 298; public static final int PPC_INS_EFDTSTEQ = 299; public static final int PPC_INS_EFDTSTGT = 300; public static final int PPC_INS_EFDTSTLT = 301; public static final int PPC_INS_EFSABS = 302; public static final int PPC_INS_EFSADD = 303; public static final int PPC_INS_EFSCFD = 304; public static final int PPC_INS_EFSCFSF = 305; public static final int PPC_INS_EFSCFSI = 306; public static final int PPC_INS_EFSCFUF = 307; public static final int PPC_INS_EFSCFUI = 308; public static final int PPC_INS_EFSCMPEQ = 309; public static final int PPC_INS_EFSCMPGT = 310; public static final int PPC_INS_EFSCMPLT = 311; public static final int PPC_INS_EFSCTSF = 312; public static final int PPC_INS_EFSCTSI = 313; public static final int PPC_INS_EFSCTSIZ = 314; public static final int PPC_INS_EFSCTUF = 315; public static final int PPC_INS_EFSCTUI = 316; public static final int PPC_INS_EFSCTUIZ = 317; public static final int PPC_INS_EFSDIV = 318; public static final int PPC_INS_EFSMUL = 319; public static final int PPC_INS_EFSNABS = 320; public static final int PPC_INS_EFSNEG = 321; public static final int PPC_INS_EFSSUB = 322; public static final int PPC_INS_EFSTSTEQ = 323; public static final int PPC_INS_EFSTSTGT = 324; public static final int PPC_INS_EFSTSTLT = 325; public static final int PPC_INS_EIEIO = 326; public static final int PPC_INS_EQV = 327; public static final int PPC_INS_EVABS = 328; public static final int PPC_INS_EVADDIW = 329; public static final int PPC_INS_EVADDSMIAAW = 330; public static final int PPC_INS_EVADDSSIAAW = 331; public static final int PPC_INS_EVADDUMIAAW = 332; public static final int PPC_INS_EVADDUSIAAW = 333; public static final int PPC_INS_EVADDW = 334; public static final int PPC_INS_EVAND = 335; public static final int PPC_INS_EVANDC = 336; public static final int PPC_INS_EVCMPEQ = 337; public static final int PPC_INS_EVCMPGTS = 338; public static final int PPC_INS_EVCMPGTU = 339; public static final int PPC_INS_EVCMPLTS = 340; public static final int PPC_INS_EVCMPLTU = 341; public static final int PPC_INS_EVCNTLSW = 342; public static final int PPC_INS_EVCNTLZW = 343; public static final int PPC_INS_EVDIVWS = 344; public static final int PPC_INS_EVDIVWU = 345; public static final int PPC_INS_EVEQV = 346; public static final int PPC_INS_EVEXTSB = 347; public static final int PPC_INS_EVEXTSH = 348; public static final int PPC_INS_EVFSABS = 349; public static final int PPC_INS_EVFSADD = 350; public static final int PPC_INS_EVFSCFSF = 351; public static final int PPC_INS_EVFSCFSI = 352; public static final int PPC_INS_EVFSCFUF = 353; public static final int PPC_INS_EVFSCFUI = 354; public static final int PPC_INS_EVFSCMPEQ = 355; public static final int PPC_INS_EVFSCMPGT = 356; public static final int PPC_INS_EVFSCMPLT = 357; public static final int PPC_INS_EVFSCTSF = 358; public static final int PPC_INS_EVFSCTSI = 359; public static final int PPC_INS_EVFSCTSIZ = 360; public static final int PPC_INS_EVFSCTUI = 361; public static final int PPC_INS_EVFSDIV = 362; public static final int PPC_INS_EVFSMUL = 363; public static final int PPC_INS_EVFSNABS = 364; public static final int PPC_INS_EVFSNEG = 365; public static final int PPC_INS_EVFSSUB = 366; public static final int PPC_INS_EVFSTSTEQ = 367; public static final int PPC_INS_EVFSTSTGT = 368; public static final int PPC_INS_EVFSTSTLT = 369; public static final int PPC_INS_EVLDD = 370; public static final int PPC_INS_EVLDDX = 371; public static final int PPC_INS_EVLDH = 372; public static final int PPC_INS_EVLDHX = 373; public static final int PPC_INS_EVLDW = 374; public static final int PPC_INS_EVLDWX = 375; public static final int PPC_INS_EVLHHESPLAT = 376; public static final int PPC_INS_EVLHHESPLATX = 377; public static final int PPC_INS_EVLHHOSSPLAT = 378; public static final int PPC_INS_EVLHHOSSPLATX = 379; public static final int PPC_INS_EVLHHOUSPLAT = 380; public static final int PPC_INS_EVLHHOUSPLATX = 381; public static final int PPC_INS_EVLWHE = 382; public static final int PPC_INS_EVLWHEX = 383; public static final int PPC_INS_EVLWHOS = 384; public static final int PPC_INS_EVLWHOSX = 385; public static final int PPC_INS_EVLWHOU = 386; public static final int PPC_INS_EVLWHOUX = 387; public static final int PPC_INS_EVLWHSPLAT = 388; public static final int PPC_INS_EVLWHSPLATX = 389; public static final int PPC_INS_EVLWWSPLAT = 390; public static final int PPC_INS_EVLWWSPLATX = 391; public static final int PPC_INS_EVMERGEHI = 392; public static final int PPC_INS_EVMERGEHILO = 393; public static final int PPC_INS_EVMERGELO = 394; public static final int PPC_INS_EVMERGELOHI = 395; public static final int PPC_INS_EVMHEGSMFAA = 396; public static final int PPC_INS_EVMHEGSMFAN = 397; public static final int PPC_INS_EVMHEGSMIAA = 398; public static final int PPC_INS_EVMHEGSMIAN = 399; public static final int PPC_INS_EVMHEGUMIAA = 400; public static final int PPC_INS_EVMHEGUMIAN = 401; public static final int PPC_INS_EVMHESMF = 402; public static final int PPC_INS_EVMHESMFA = 403; public static final int PPC_INS_EVMHESMFAAW = 404; public static final int PPC_INS_EVMHESMFANW = 405; public static final int PPC_INS_EVMHESMI = 406; public static final int PPC_INS_EVMHESMIA = 407; public static final int PPC_INS_EVMHESMIAAW = 408; public static final int PPC_INS_EVMHESMIANW = 409; public static final int PPC_INS_EVMHESSF = 410; public static final int PPC_INS_EVMHESSFA = 411; public static final int PPC_INS_EVMHESSFAAW = 412; public static final int PPC_INS_EVMHESSFANW = 413; public static final int PPC_INS_EVMHESSIAAW = 414; public static final int PPC_INS_EVMHESSIANW = 415; public static final int PPC_INS_EVMHEUMI = 416; public static final int PPC_INS_EVMHEUMIA = 417; public static final int PPC_INS_EVMHEUMIAAW = 418; public static final int PPC_INS_EVMHEUMIANW = 419; public static final int PPC_INS_EVMHEUSIAAW = 420; public static final int PPC_INS_EVMHEUSIANW = 421; public static final int PPC_INS_EVMHOGSMFAA = 422; public static final int PPC_INS_EVMHOGSMFAN = 423; public static final int PPC_INS_EVMHOGSMIAA = 424; public static final int PPC_INS_EVMHOGSMIAN = 425; public static final int PPC_INS_EVMHOGUMIAA = 426; public static final int PPC_INS_EVMHOGUMIAN = 427; public static final int PPC_INS_EVMHOSMF = 428; public static final int PPC_INS_EVMHOSMFA = 429; public static final int PPC_INS_EVMHOSMFAAW = 430; public static final int PPC_INS_EVMHOSMFANW = 431; public static final int PPC_INS_EVMHOSMI = 432; public static final int PPC_INS_EVMHOSMIA = 433; public static final int PPC_INS_EVMHOSMIAAW = 434; public static final int PPC_INS_EVMHOSMIANW = 435; public static final int PPC_INS_EVMHOSSF = 436; public static final int PPC_INS_EVMHOSSFA = 437; public static final int PPC_INS_EVMHOSSFAAW = 438; public static final int PPC_INS_EVMHOSSFANW = 439; public static final int PPC_INS_EVMHOSSIAAW = 440; public static final int PPC_INS_EVMHOSSIANW = 441; public static final int PPC_INS_EVMHOUMI = 442; public static final int PPC_INS_EVMHOUMIA = 443; public static final int PPC_INS_EVMHOUMIAAW = 444; public static final int PPC_INS_EVMHOUMIANW = 445; public static final int PPC_INS_EVMHOUSIAAW = 446; public static final int PPC_INS_EVMHOUSIANW = 447; public static final int PPC_INS_EVMRA = 448; public static final int PPC_INS_EVMWHSMF = 449; public static final int PPC_INS_EVMWHSMFA = 450; public static final int PPC_INS_EVMWHSMI = 451; public static final int PPC_INS_EVMWHSMIA = 452; public static final int PPC_INS_EVMWHSSF = 453; public static final int PPC_INS_EVMWHSSFA = 454; public static final int PPC_INS_EVMWHUMI = 455; public static final int PPC_INS_EVMWHUMIA = 456; public static final int PPC_INS_EVMWLSMIAAW = 457; public static final int PPC_INS_EVMWLSMIANW = 458; public static final int PPC_INS_EVMWLSSIAAW = 459; public static final int PPC_INS_EVMWLSSIANW = 460; public static final int PPC_INS_EVMWLUMI = 461; public static final int PPC_INS_EVMWLUMIA = 462; public static final int PPC_INS_EVMWLUMIAAW = 463; public static final int PPC_INS_EVMWLUMIANW = 464; public static final int PPC_INS_EVMWLUSIAAW = 465; public static final int PPC_INS_EVMWLUSIANW = 466; public static final int PPC_INS_EVMWSMF = 467; public static final int PPC_INS_EVMWSMFA = 468; public static final int PPC_INS_EVMWSMFAA = 469; public static final int PPC_INS_EVMWSMFAN = 470; public static final int PPC_INS_EVMWSMI = 471; public static final int PPC_INS_EVMWSMIA = 472; public static final int PPC_INS_EVMWSMIAA = 473; public static final int PPC_INS_EVMWSMIAN = 474; public static final int PPC_INS_EVMWSSF = 475; public static final int PPC_INS_EVMWSSFA = 476; public static final int PPC_INS_EVMWSSFAA = 477; public static final int PPC_INS_EVMWSSFAN = 478; public static final int PPC_INS_EVMWUMI = 479; public static final int PPC_INS_EVMWUMIA = 480; public static final int PPC_INS_EVMWUMIAA = 481; public static final int PPC_INS_EVMWUMIAN = 482; public static final int PPC_INS_EVNAND = 483; public static final int PPC_INS_EVNEG = 484; public static final int PPC_INS_EVNOR = 485; public static final int PPC_INS_EVOR = 486; public static final int PPC_INS_EVORC = 487; public static final int PPC_INS_EVRLW = 488; public static final int PPC_INS_EVRLWI = 489; public static final int PPC_INS_EVRNDW = 490; public static final int PPC_INS_EVSEL = 491; public static final int PPC_INS_EVSLW = 492; public static final int PPC_INS_EVSLWI = 493; public static final int PPC_INS_EVSPLATFI = 494; public static final int PPC_INS_EVSPLATI = 495; public static final int PPC_INS_EVSRWIS = 496; public static final int PPC_INS_EVSRWIU = 497; public static final int PPC_INS_EVSRWS = 498; public static final int PPC_INS_EVSRWU = 499; public static final int PPC_INS_EVSTDD = 500; public static final int PPC_INS_EVSTDDX = 501; public static final int PPC_INS_EVSTDH = 502; public static final int PPC_INS_EVSTDHX = 503; public static final int PPC_INS_EVSTDW = 504; public static final int PPC_INS_EVSTDWX = 505; public static final int PPC_INS_EVSTWHE = 506; public static final int PPC_INS_EVSTWHEX = 507; public static final int PPC_INS_EVSTWHO = 508; public static final int PPC_INS_EVSTWHOX = 509; public static final int PPC_INS_EVSTWWE = 510; public static final int PPC_INS_EVSTWWEX = 511; public static final int PPC_INS_EVSTWWO = 512; public static final int PPC_INS_EVSTWWOX = 513; public static final int PPC_INS_EVSUBFSMIAAW = 514; public static final int PPC_INS_EVSUBFSSIAAW = 515; public static final int PPC_INS_EVSUBFUMIAAW = 516; public static final int PPC_INS_EVSUBFUSIAAW = 517; public static final int PPC_INS_EVSUBFW = 518; public static final int PPC_INS_EVSUBIFW = 519; public static final int PPC_INS_EVXOR = 520; public static final int PPC_INS_EXTLDI = 521; public static final int PPC_INS_EXTLWI = 522; public static final int PPC_INS_EXTRDI = 523; public static final int PPC_INS_EXTRWI = 524; public static final int PPC_INS_EXTSB = 525; public static final int PPC_INS_EXTSH = 526; public static final int PPC_INS_EXTSW = 527; public static final int PPC_INS_EXTSWSLI = 528; public static final int PPC_INS_FABS = 529; public static final int PPC_INS_FADD = 530; public static final int PPC_INS_FADDS = 531; public static final int PPC_INS_FCFID = 532; public static final int PPC_INS_FCFIDS = 533; public static final int PPC_INS_FCFIDU = 534; public static final int PPC_INS_FCFIDUS = 535; public static final int PPC_INS_FCMPU = 536; public static final int PPC_INS_FCPSGN = 537; public static final int PPC_INS_FCTID = 538; public static final int PPC_INS_FCTIDU = 539; public static final int PPC_INS_FCTIDUZ = 540; public static final int PPC_INS_FCTIDZ = 541; public static final int PPC_INS_FCTIW = 542; public static final int PPC_INS_FCTIWU = 543; public static final int PPC_INS_FCTIWUZ = 544; public static final int PPC_INS_FCTIWZ = 545; public static final int PPC_INS_FDIV = 546; public static final int PPC_INS_FDIVS = 547; public static final int PPC_INS_FMADD = 548; public static final int PPC_INS_FMADDS = 549; public static final int PPC_INS_FMR = 550; public static final int PPC_INS_FMSUB = 551; public static final int PPC_INS_FMSUBS = 552; public static final int PPC_INS_FMUL = 553; public static final int PPC_INS_FMULS = 554; public static final int PPC_INS_FNABS = 555; public static final int PPC_INS_FNEG = 556; public static final int PPC_INS_FNMADD = 557; public static final int PPC_INS_FNMADDS = 558; public static final int PPC_INS_FNMSUB = 559; public static final int PPC_INS_FNMSUBS = 560; public static final int PPC_INS_FRE = 561; public static final int PPC_INS_FRES = 562; public static final int PPC_INS_FRIM = 563; public static final int PPC_INS_FRIN = 564; public static final int PPC_INS_FRIP = 565; public static final int PPC_INS_FRIZ = 566; public static final int PPC_INS_FRSP = 567; public static final int PPC_INS_FRSQRTE = 568; public static final int PPC_INS_FRSQRTES = 569; public static final int PPC_INS_FSEL = 570; public static final int PPC_INS_FSQRT = 571; public static final int PPC_INS_FSQRTS = 572; public static final int PPC_INS_FSUB = 573; public static final int PPC_INS_FSUBS = 574; public static final int PPC_INS_FTDIV = 575; public static final int PPC_INS_FTSQRT = 576; public static final int PPC_INS_HRFID = 577; public static final int PPC_INS_ICBI = 578; public static final int PPC_INS_ICBIEP = 579; public static final int PPC_INS_ICBLC = 580; public static final int PPC_INS_ICBLQ = 581; public static final int PPC_INS_ICBT = 582; public static final int PPC_INS_ICBTLS = 583; public static final int PPC_INS_ICCCI = 584; public static final int PPC_INS_ICI = 585; public static final int PPC_INS_INSLWI = 586; public static final int PPC_INS_INSRDI = 587; public static final int PPC_INS_INSRWI = 588; public static final int PPC_INS_ISEL = 589; public static final int PPC_INS_ISYNC = 590; public static final int PPC_INS_LA = 591; public static final int PPC_INS_LBARX = 592; public static final int PPC_INS_LBEPX = 593; public static final int PPC_INS_LBZ = 594; public static final int PPC_INS_LBZCIX = 595; public static final int PPC_INS_LBZU = 596; public static final int PPC_INS_LBZUX = 597; public static final int PPC_INS_LBZX = 598; public static final int PPC_INS_LD = 599; public static final int PPC_INS_LDARX = 600; public static final int PPC_INS_LDAT = 601; public static final int PPC_INS_LDBRX = 602; public static final int PPC_INS_LDCIX = 603; public static final int PPC_INS_LDMX = 604; public static final int PPC_INS_LDU = 605; public static final int PPC_INS_LDUX = 606; public static final int PPC_INS_LDX = 607; public static final int PPC_INS_LFD = 608; public static final int PPC_INS_LFDEPX = 609; public static final int PPC_INS_LFDU = 610; public static final int PPC_INS_LFDUX = 611; public static final int PPC_INS_LFDX = 612; public static final int PPC_INS_LFIWAX = 613; public static final int PPC_INS_LFIWZX = 614; public static final int PPC_INS_LFS = 615; public static final int PPC_INS_LFSU = 616; public static final int PPC_INS_LFSUX = 617; public static final int PPC_INS_LFSX = 618; public static final int PPC_INS_LHA = 619; public static final int PPC_INS_LHARX = 620; public static final int PPC_INS_LHAU = 621; public static final int PPC_INS_LHAUX = 622; public static final int PPC_INS_LHAX = 623; public static final int PPC_INS_LHBRX = 624; public static final int PPC_INS_LHEPX = 625; public static final int PPC_INS_LHZ = 626; public static final int PPC_INS_LHZCIX = 627; public static final int PPC_INS_LHZU = 628; public static final int PPC_INS_LHZUX = 629; public static final int PPC_INS_LHZX = 630; public static final int PPC_INS_LI = 631; public static final int PPC_INS_LIS = 632; public static final int PPC_INS_LMW = 633; public static final int PPC_INS_LNIA = 634; public static final int PPC_INS_LSWI = 635; public static final int PPC_INS_LVEBX = 636; public static final int PPC_INS_LVEHX = 637; public static final int PPC_INS_LVEWX = 638; public static final int PPC_INS_LVSL = 639; public static final int PPC_INS_LVSR = 640; public static final int PPC_INS_LVX = 641; public static final int PPC_INS_LVXL = 642; public static final int PPC_INS_LWA = 643; public static final int PPC_INS_LWARX = 644; public static final int PPC_INS_LWAT = 645; public static final int PPC_INS_LWAUX = 646; public static final int PPC_INS_LWAX = 647; public static final int PPC_INS_LWBRX = 648; public static final int PPC_INS_LWEPX = 649; public static final int PPC_INS_LWSYNC = 650; public static final int PPC_INS_LWZ = 651; public static final int PPC_INS_LWZCIX = 652; public static final int PPC_INS_LWZU = 653; public static final int PPC_INS_LWZUX = 654; public static final int PPC_INS_LWZX = 655; public static final int PPC_INS_LXSD = 656; public static final int PPC_INS_LXSDX = 657; public static final int PPC_INS_LXSIBZX = 658; public static final int PPC_INS_LXSIHZX = 659; public static final int PPC_INS_LXSIWAX = 660; public static final int PPC_INS_LXSIWZX = 661; public static final int PPC_INS_LXSSP = 662; public static final int PPC_INS_LXSSPX = 663; public static final int PPC_INS_LXV = 664; public static final int PPC_INS_LXVB16X = 665; public static final int PPC_INS_LXVD2X = 666; public static final int PPC_INS_LXVDSX = 667; public static final int PPC_INS_LXVH8X = 668; public static final int PPC_INS_LXVL = 669; public static final int PPC_INS_LXVLL = 670; public static final int PPC_INS_LXVW4X = 671; public static final int PPC_INS_LXVWSX = 672; public static final int PPC_INS_LXVX = 673; public static final int PPC_INS_MADDHD = 674; public static final int PPC_INS_MADDHDU = 675; public static final int PPC_INS_MADDLD = 676; public static final int PPC_INS_MBAR = 677; public static final int PPC_INS_MCRF = 678; public static final int PPC_INS_MCRFS = 679; public static final int PPC_INS_MCRXRX = 680; public static final int PPC_INS_MFAMR = 681; public static final int PPC_INS_MFASR = 682; public static final int PPC_INS_MFBHRBE = 683; public static final int PPC_INS_MFBR0 = 684; public static final int PPC_INS_MFBR1 = 685; public static final int PPC_INS_MFBR2 = 686; public static final int PPC_INS_MFBR3 = 687; public static final int PPC_INS_MFBR4 = 688; public static final int PPC_INS_MFBR5 = 689; public static final int PPC_INS_MFBR6 = 690; public static final int PPC_INS_MFBR7 = 691; public static final int PPC_INS_MFCFAR = 692; public static final int PPC_INS_MFCR = 693; public static final int PPC_INS_MFCTR = 694; public static final int PPC_INS_MFDAR = 695; public static final int PPC_INS_MFDBATL = 696; public static final int PPC_INS_MFDBATU = 697; public static final int PPC_INS_MFDCCR = 698; public static final int PPC_INS_MFDCR = 699; public static final int PPC_INS_MFDEAR = 700; public static final int PPC_INS_MFDEC = 701; public static final int PPC_INS_MFDSCR = 702; public static final int PPC_INS_MFDSISR = 703; public static final int PPC_INS_MFESR = 704; public static final int PPC_INS_MFFPRD = 705; public static final int PPC_INS_MFFS = 706; public static final int PPC_INS_MFFSCDRN = 707; public static final int PPC_INS_MFFSCDRNI = 708; public static final int PPC_INS_MFFSCE = 709; public static final int PPC_INS_MFFSCRN = 710; public static final int PPC_INS_MFFSCRNI = 711; public static final int PPC_INS_MFFSL = 712; public static final int PPC_INS_MFIBATL = 713; public static final int PPC_INS_MFIBATU = 714; public static final int PPC_INS_MFICCR = 715; public static final int PPC_INS_MFLR = 716; public static final int PPC_INS_MFMSR = 717; public static final int PPC_INS_MFOCRF = 718; public static final int PPC_INS_MFPID = 719; public static final int PPC_INS_MFPMR = 720; public static final int PPC_INS_MFPVR = 721; public static final int PPC_INS_MFRTCL = 722; public static final int PPC_INS_MFRTCU = 723; public static final int PPC_INS_MFSDR1 = 724; public static final int PPC_INS_MFSPEFSCR = 725; public static final int PPC_INS_MFSPR = 726; public static final int PPC_INS_MFSPRG = 727; public static final int PPC_INS_MFSPRG0 = 728; public static final int PPC_INS_MFSPRG1 = 729; public static final int PPC_INS_MFSPRG2 = 730; public static final int PPC_INS_MFSPRG3 = 731; public static final int PPC_INS_MFSPRG4 = 732; public static final int PPC_INS_MFSPRG5 = 733; public static final int PPC_INS_MFSPRG6 = 734; public static final int PPC_INS_MFSPRG7 = 735; public static final int PPC_INS_MFSR = 736; public static final int PPC_INS_MFSRIN = 737; public static final int PPC_INS_MFSRR0 = 738; public static final int PPC_INS_MFSRR1 = 739; public static final int PPC_INS_MFSRR2 = 740; public static final int PPC_INS_MFSRR3 = 741; public static final int PPC_INS_MFTB = 742; public static final int PPC_INS_MFTBHI = 743; public static final int PPC_INS_MFTBL = 744; public static final int PPC_INS_MFTBLO = 745; public static final int PPC_INS_MFTBU = 746; public static final int PPC_INS_MFTCR = 747; public static final int PPC_INS_MFVRD = 748; public static final int PPC_INS_MFVRSAVE = 749; public static final int PPC_INS_MFVSCR = 750; public static final int PPC_INS_MFVSRD = 751; public static final int PPC_INS_MFVSRLD = 752; public static final int PPC_INS_MFVSRWZ = 753; public static final int PPC_INS_MFXER = 754; public static final int PPC_INS_MODSD = 755; public static final int PPC_INS_MODSW = 756; public static final int PPC_INS_MODUD = 757; public static final int PPC_INS_MODUW = 758; public static final int PPC_INS_MR = 759; public static final int PPC_INS_MSGSYNC = 760; public static final int PPC_INS_MSYNC = 761; public static final int PPC_INS_MTAMR = 762; public static final int PPC_INS_MTASR = 763; public static final int PPC_INS_MTBR0 = 764; public static final int PPC_INS_MTBR1 = 765; public static final int PPC_INS_MTBR2 = 766; public static final int PPC_INS_MTBR3 = 767; public static final int PPC_INS_MTBR4 = 768; public static final int PPC_INS_MTBR5 = 769; public static final int PPC_INS_MTBR6 = 770; public static final int PPC_INS_MTBR7 = 771; public static final int PPC_INS_MTCFAR = 772; public static final int PPC_INS_MTCR = 773; public static final int PPC_INS_MTCRF = 774; public static final int PPC_INS_MTCTR = 775; public static final int PPC_INS_MTDAR = 776; public static final int PPC_INS_MTDBATL = 777; public static final int PPC_INS_MTDBATU = 778; public static final int PPC_INS_MTDCCR = 779; public static final int PPC_INS_MTDCR = 780; public static final int PPC_INS_MTDEAR = 781; public static final int PPC_INS_MTDEC = 782; public static final int PPC_INS_MTDSCR = 783; public static final int PPC_INS_MTDSISR = 784; public static final int PPC_INS_MTESR = 785; public static final int PPC_INS_MTFSB0 = 786; public static final int PPC_INS_MTFSB1 = 787; public static final int PPC_INS_MTFSF = 788; public static final int PPC_INS_MTFSFI = 789; public static final int PPC_INS_MTIBATL = 790; public static final int PPC_INS_MTIBATU = 791; public static final int PPC_INS_MTICCR = 792; public static final int PPC_INS_MTLR = 793; public static final int PPC_INS_MTMSR = 794; public static final int PPC_INS_MTMSRD = 795; public static final int PPC_INS_MTOCRF = 796; public static final int PPC_INS_MTPID = 797; public static final int PPC_INS_MTPMR = 798; public static final int PPC_INS_MTSDR1 = 799; public static final int PPC_INS_MTSPEFSCR = 800; public static final int PPC_INS_MTSPR = 801; public static final int PPC_INS_MTSPRG = 802; public static final int PPC_INS_MTSPRG0 = 803; public static final int PPC_INS_MTSPRG1 = 804; public static final int PPC_INS_MTSPRG2 = 805; public static final int PPC_INS_MTSPRG3 = 806; public static final int PPC_INS_MTSPRG4 = 807; public static final int PPC_INS_MTSPRG5 = 808; public static final int PPC_INS_MTSPRG6 = 809; public static final int PPC_INS_MTSPRG7 = 810; public static final int PPC_INS_MTSR = 811; public static final int PPC_INS_MTSRIN = 812; public static final int PPC_INS_MTSRR0 = 813; public static final int PPC_INS_MTSRR1 = 814; public static final int PPC_INS_MTSRR2 = 815; public static final int PPC_INS_MTSRR3 = 816; public static final int PPC_INS_MTTBHI = 817; public static final int PPC_INS_MTTBL = 818; public static final int PPC_INS_MTTBLO = 819; public static final int PPC_INS_MTTBU = 820; public static final int PPC_INS_MTTCR = 821; public static final int PPC_INS_MTVRSAVE = 822; public static final int PPC_INS_MTVSCR = 823; public static final int PPC_INS_MTVSRD = 824; public static final int PPC_INS_MTVSRDD = 825; public static final int PPC_INS_MTVSRWA = 826; public static final int PPC_INS_MTVSRWS = 827; public static final int PPC_INS_MTVSRWZ = 828; public static final int PPC_INS_MTXER = 829; public static final int PPC_INS_MULHD = 830; public static final int PPC_INS_MULHDU = 831; public static final int PPC_INS_MULHW = 832; public static final int PPC_INS_MULHWU = 833; public static final int PPC_INS_MULLD = 834; public static final int PPC_INS_MULLI = 835; public static final int PPC_INS_MULLW = 836; public static final int PPC_INS_NAND = 837; public static final int PPC_INS_NAP = 838; public static final int PPC_INS_NEG = 839; public static final int PPC_INS_NOP = 840; public static final int PPC_INS_NOR = 841; public static final int PPC_INS_NOT = 842; public static final int PPC_INS_OR = 843; public static final int PPC_INS_ORC = 844; public static final int PPC_INS_ORI = 845; public static final int PPC_INS_ORIS = 846; public static final int PPC_INS_PASTE = 847; public static final int PPC_INS_PASTE_LAST = 848; public static final int PPC_INS_POPCNTB = 849; public static final int PPC_INS_POPCNTD = 850; public static final int PPC_INS_POPCNTW = 851; public static final int PPC_INS_PTESYNC = 852; public static final int PPC_INS_QVALIGNI = 853; public static final int PPC_INS_QVESPLATI = 854; public static final int PPC_INS_QVFABS = 855; public static final int PPC_INS_QVFADD = 856; public static final int PPC_INS_QVFADDS = 857; public static final int PPC_INS_QVFAND = 858; public static final int PPC_INS_QVFANDC = 859; public static final int PPC_INS_QVFCFID = 860; public static final int PPC_INS_QVFCFIDS = 861; public static final int PPC_INS_QVFCFIDU = 862; public static final int PPC_INS_QVFCFIDUS = 863; public static final int PPC_INS_QVFCLR = 864; public static final int PPC_INS_QVFCMPEQ = 865; public static final int PPC_INS_QVFCMPGT = 866; public static final int PPC_INS_QVFCMPLT = 867; public static final int PPC_INS_QVFCPSGN = 868; public static final int PPC_INS_QVFCTFB = 869; public static final int PPC_INS_QVFCTID = 870; public static final int PPC_INS_QVFCTIDU = 871; public static final int PPC_INS_QVFCTIDUZ = 872; public static final int PPC_INS_QVFCTIDZ = 873; public static final int PPC_INS_QVFCTIW = 874; public static final int PPC_INS_QVFCTIWU = 875; public static final int PPC_INS_QVFCTIWUZ = 876; public static final int PPC_INS_QVFCTIWZ = 877; public static final int PPC_INS_QVFEQU = 878; public static final int PPC_INS_QVFLOGICAL = 879; public static final int PPC_INS_QVFMADD = 880; public static final int PPC_INS_QVFMADDS = 881; public static final int PPC_INS_QVFMR = 882; public static final int PPC_INS_QVFMSUB = 883; public static final int PPC_INS_QVFMSUBS = 884; public static final int PPC_INS_QVFMUL = 885; public static final int PPC_INS_QVFMULS = 886; public static final int PPC_INS_QVFNABS = 887; public static final int PPC_INS_QVFNAND = 888; public static final int PPC_INS_QVFNEG = 889; public static final int PPC_INS_QVFNMADD = 890; public static final int PPC_INS_QVFNMADDS = 891; public static final int PPC_INS_QVFNMSUB = 892; public static final int PPC_INS_QVFNMSUBS = 893; public static final int PPC_INS_QVFNOR = 894; public static final int PPC_INS_QVFNOT = 895; public static final int PPC_INS_QVFOR = 896; public static final int PPC_INS_QVFORC = 897; public static final int PPC_INS_QVFPERM = 898; public static final int PPC_INS_QVFRE = 899; public static final int PPC_INS_QVFRES = 900; public static final int PPC_INS_QVFRIM = 901; public static final int PPC_INS_QVFRIN = 902; public static final int PPC_INS_QVFRIP = 903; public static final int PPC_INS_QVFRIZ = 904; public static final int PPC_INS_QVFRSP = 905; public static final int PPC_INS_QVFRSQRTE = 906; public static final int PPC_INS_QVFRSQRTES = 907; public static final int PPC_INS_QVFSEL = 908; public static final int PPC_INS_QVFSET = 909; public static final int PPC_INS_QVFSUB = 910; public static final int PPC_INS_QVFSUBS = 911; public static final int PPC_INS_QVFTSTNAN = 912; public static final int PPC_INS_QVFXMADD = 913; public static final int PPC_INS_QVFXMADDS = 914; public static final int PPC_INS_QVFXMUL = 915; public static final int PPC_INS_QVFXMULS = 916; public static final int PPC_INS_QVFXOR = 917; public static final int PPC_INS_QVFXXCPNMADD = 918; public static final int PPC_INS_QVFXXCPNMADDS = 919; public static final int PPC_INS_QVFXXMADD = 920; public static final int PPC_INS_QVFXXMADDS = 921; public static final int PPC_INS_QVFXXNPMADD = 922; public static final int PPC_INS_QVFXXNPMADDS = 923; public static final int PPC_INS_QVGPCI = 924; public static final int PPC_INS_QVLFCDUX = 925; public static final int PPC_INS_QVLFCDUXA = 926; public static final int PPC_INS_QVLFCDX = 927; public static final int PPC_INS_QVLFCDXA = 928; public static final int PPC_INS_QVLFCSUX = 929; public static final int PPC_INS_QVLFCSUXA = 930; public static final int PPC_INS_QVLFCSX = 931; public static final int PPC_INS_QVLFCSXA = 932; public static final int PPC_INS_QVLFDUX = 933; public static final int PPC_INS_QVLFDUXA = 934; public static final int PPC_INS_QVLFDX = 935; public static final int PPC_INS_QVLFDXA = 936; public static final int PPC_INS_QVLFIWAX = 937; public static final int PPC_INS_QVLFIWAXA = 938; public static final int PPC_INS_QVLFIWZX = 939; public static final int PPC_INS_QVLFIWZXA = 940; public static final int PPC_INS_QVLFSUX = 941; public static final int PPC_INS_QVLFSUXA = 942; public static final int PPC_INS_QVLFSX = 943; public static final int PPC_INS_QVLFSXA = 944; public static final int PPC_INS_QVLPCLDX = 945; public static final int PPC_INS_QVLPCLSX = 946; public static final int PPC_INS_QVLPCRDX = 947; public static final int PPC_INS_QVLPCRSX = 948; public static final int PPC_INS_QVSTFCDUX = 949; public static final int PPC_INS_QVSTFCDUXA = 950; public static final int PPC_INS_QVSTFCDUXI = 951; public static final int PPC_INS_QVSTFCDUXIA = 952; public static final int PPC_INS_QVSTFCDX = 953; public static final int PPC_INS_QVSTFCDXA = 954; public static final int PPC_INS_QVSTFCDXI = 955; public static final int PPC_INS_QVSTFCDXIA = 956; public static final int PPC_INS_QVSTFCSUX = 957; public static final int PPC_INS_QVSTFCSUXA = 958; public static final int PPC_INS_QVSTFCSUXI = 959; public static final int PPC_INS_QVSTFCSUXIA = 960; public static final int PPC_INS_QVSTFCSX = 961; public static final int PPC_INS_QVSTFCSXA = 962; public static final int PPC_INS_QVSTFCSXI = 963; public static final int PPC_INS_QVSTFCSXIA = 964; public static final int PPC_INS_QVSTFDUX = 965; public static final int PPC_INS_QVSTFDUXA = 966; public static final int PPC_INS_QVSTFDUXI = 967; public static final int PPC_INS_QVSTFDUXIA = 968; public static final int PPC_INS_QVSTFDX = 969; public static final int PPC_INS_QVSTFDXA = 970; public static final int PPC_INS_QVSTFDXI = 971; public static final int PPC_INS_QVSTFDXIA = 972; public static final int PPC_INS_QVSTFIWX = 973; public static final int PPC_INS_QVSTFIWXA = 974; public static final int PPC_INS_QVSTFSUX = 975; public static final int PPC_INS_QVSTFSUXA = 976; public static final int PPC_INS_QVSTFSUXI = 977; public static final int PPC_INS_QVSTFSUXIA = 978; public static final int PPC_INS_QVSTFSX = 979; public static final int PPC_INS_QVSTFSXA = 980; public static final int PPC_INS_QVSTFSXI = 981; public static final int PPC_INS_QVSTFSXIA = 982; public static final int PPC_INS_RFCI = 983; public static final int PPC_INS_RFDI = 984; public static final int PPC_INS_RFEBB = 985; public static final int PPC_INS_RFI = 986; public static final int PPC_INS_RFID = 987; public static final int PPC_INS_RFMCI = 988; public static final int PPC_INS_RLDCL = 989; public static final int PPC_INS_RLDCR = 990; public static final int PPC_INS_RLDIC = 991; public static final int PPC_INS_RLDICL = 992; public static final int PPC_INS_RLDICR = 993; public static final int PPC_INS_RLDIMI = 994; public static final int PPC_INS_RLWIMI = 995; public static final int PPC_INS_RLWINM = 996; public static final int PPC_INS_RLWNM = 997; public static final int PPC_INS_ROTLD = 998; public static final int PPC_INS_ROTLDI = 999; public static final int PPC_INS_ROTLW = 1000; public static final int PPC_INS_ROTLWI = 1001; public static final int PPC_INS_ROTRDI = 1002; public static final int PPC_INS_ROTRWI = 1003; public static final int PPC_INS_SC = 1004; public static final int PPC_INS_SETB = 1005; public static final int PPC_INS_SLBIA = 1006; public static final int PPC_INS_SLBIE = 1007; public static final int PPC_INS_SLBIEG = 1008; public static final int PPC_INS_SLBMFEE = 1009; public static final int PPC_INS_SLBMFEV = 1010; public static final int PPC_INS_SLBMTE = 1011; public static final int PPC_INS_SLBSYNC = 1012; public static final int PPC_INS_SLD = 1013; public static final int PPC_INS_SLDI = 1014; public static final int PPC_INS_SLW = 1015; public static final int PPC_INS_SLWI = 1016; public static final int PPC_INS_SRAD = 1017; public static final int PPC_INS_SRADI = 1018; public static final int PPC_INS_SRAW = 1019; public static final int PPC_INS_SRAWI = 1020; public static final int PPC_INS_SRD = 1021; public static final int PPC_INS_SRDI = 1022; public static final int PPC_INS_SRW = 1023; public static final int PPC_INS_SRWI = 1024; public static final int PPC_INS_STB = 1025; public static final int PPC_INS_STBCIX = 1026; public static final int PPC_INS_STBCX = 1027; public static final int PPC_INS_STBEPX = 1028; public static final int PPC_INS_STBU = 1029; public static final int PPC_INS_STBUX = 1030; public static final int PPC_INS_STBX = 1031; public static final int PPC_INS_STD = 1032; public static final int PPC_INS_STDAT = 1033; public static final int PPC_INS_STDBRX = 1034; public static final int PPC_INS_STDCIX = 1035; public static final int PPC_INS_STDCX = 1036; public static final int PPC_INS_STDU = 1037; public static final int PPC_INS_STDUX = 1038; public static final int PPC_INS_STDX = 1039; public static final int PPC_INS_STFD = 1040; public static final int PPC_INS_STFDEPX = 1041; public static final int PPC_INS_STFDU = 1042; public static final int PPC_INS_STFDUX = 1043; public static final int PPC_INS_STFDX = 1044; public static final int PPC_INS_STFIWX = 1045; public static final int PPC_INS_STFS = 1046; public static final int PPC_INS_STFSU = 1047; public static final int PPC_INS_STFSUX = 1048; public static final int PPC_INS_STFSX = 1049; public static final int PPC_INS_STH = 1050; public static final int PPC_INS_STHBRX = 1051; public static final int PPC_INS_STHCIX = 1052; public static final int PPC_INS_STHCX = 1053; public static final int PPC_INS_STHEPX = 1054; public static final int PPC_INS_STHU = 1055; public static final int PPC_INS_STHUX = 1056; public static final int PPC_INS_STHX = 1057; public static final int PPC_INS_STMW = 1058; public static final int PPC_INS_STOP = 1059; public static final int PPC_INS_STSWI = 1060; public static final int PPC_INS_STVEBX = 1061; public static final int PPC_INS_STVEHX = 1062; public static final int PPC_INS_STVEWX = 1063; public static final int PPC_INS_STVX = 1064; public static final int PPC_INS_STVXL = 1065; public static final int PPC_INS_STW = 1066; public static final int PPC_INS_STWAT = 1067; public static final int PPC_INS_STWBRX = 1068; public static final int PPC_INS_STWCIX = 1069; public static final int PPC_INS_STWCX = 1070; public static final int PPC_INS_STWEPX = 1071; public static final int PPC_INS_STWU = 1072; public static final int PPC_INS_STWUX = 1073; public static final int PPC_INS_STWX = 1074; public static final int PPC_INS_STXSD = 1075; public static final int PPC_INS_STXSDX = 1076; public static final int PPC_INS_STXSIBX = 1077; public static final int PPC_INS_STXSIHX = 1078; public static final int PPC_INS_STXSIWX = 1079; public static final int PPC_INS_STXSSP = 1080; public static final int PPC_INS_STXSSPX = 1081; public static final int PPC_INS_STXV = 1082; public static final int PPC_INS_STXVB16X = 1083; public static final int PPC_INS_STXVD2X = 1084; public static final int PPC_INS_STXVH8X = 1085; public static final int PPC_INS_STXVL = 1086; public static final int PPC_INS_STXVLL = 1087; public static final int PPC_INS_STXVW4X = 1088; public static final int PPC_INS_STXVX = 1089; public static final int PPC_INS_SUB = 1090; public static final int PPC_INS_SUBC = 1091; public static final int PPC_INS_SUBF = 1092; public static final int PPC_INS_SUBFC = 1093; public static final int PPC_INS_SUBFE = 1094; public static final int PPC_INS_SUBFIC = 1095; public static final int PPC_INS_SUBFME = 1096; public static final int PPC_INS_SUBFZE = 1097; public static final int PPC_INS_SUBI = 1098; public static final int PPC_INS_SUBIC = 1099; public static final int PPC_INS_SUBIS = 1100; public static final int PPC_INS_SUBPCIS = 1101; public static final int PPC_INS_SYNC = 1102; public static final int PPC_INS_TABORT = 1103; public static final int PPC_INS_TABORTDC = 1104; public static final int PPC_INS_TABORTDCI = 1105; public static final int PPC_INS_TABORTWC = 1106; public static final int PPC_INS_TABORTWCI = 1107; public static final int PPC_INS_TBEGIN = 1108; public static final int PPC_INS_TCHECK = 1109; public static final int PPC_INS_TD = 1110; public static final int PPC_INS_TDEQ = 1111; public static final int PPC_INS_TDEQI = 1112; public static final int PPC_INS_TDGE = 1113; public static final int PPC_INS_TDGEI = 1114; public static final int PPC_INS_TDGT = 1115; public static final int PPC_INS_TDGTI = 1116; public static final int PPC_INS_TDI = 1117; public static final int PPC_INS_TDLE = 1118; public static final int PPC_INS_TDLEI = 1119; public static final int PPC_INS_TDLGE = 1120; public static final int PPC_INS_TDLGEI = 1121; public static final int PPC_INS_TDLGT = 1122; public static final int PPC_INS_TDLGTI = 1123; public static final int PPC_INS_TDLLE = 1124; public static final int PPC_INS_TDLLEI = 1125; public static final int PPC_INS_TDLLT = 1126; public static final int PPC_INS_TDLLTI = 1127; public static final int PPC_INS_TDLNG = 1128; public static final int PPC_INS_TDLNGI = 1129; public static final int PPC_INS_TDLNL = 1130; public static final int PPC_INS_TDLNLI = 1131; public static final int PPC_INS_TDLT = 1132; public static final int PPC_INS_TDLTI = 1133; public static final int PPC_INS_TDNE = 1134; public static final int PPC_INS_TDNEI = 1135; public static final int PPC_INS_TDNG = 1136; public static final int PPC_INS_TDNGI = 1137; public static final int PPC_INS_TDNL = 1138; public static final int PPC_INS_TDNLI = 1139; public static final int PPC_INS_TDU = 1140; public static final int PPC_INS_TDUI = 1141; public static final int PPC_INS_TEND = 1142; public static final int PPC_INS_TLBIA = 1143; public static final int PPC_INS_TLBIE = 1144; public static final int PPC_INS_TLBIEL = 1145; public static final int PPC_INS_TLBIVAX = 1146; public static final int PPC_INS_TLBLD = 1147; public static final int PPC_INS_TLBLI = 1148; public static final int PPC_INS_TLBRE = 1149; public static final int PPC_INS_TLBREHI = 1150; public static final int PPC_INS_TLBRELO = 1151; public static final int PPC_INS_TLBSX = 1152; public static final int PPC_INS_TLBSYNC = 1153; public static final int PPC_INS_TLBWE = 1154; public static final int PPC_INS_TLBWEHI = 1155; public static final int PPC_INS_TLBWELO = 1156; public static final int PPC_INS_TRAP = 1157; public static final int PPC_INS_TRECHKPT = 1158; public static final int PPC_INS_TRECLAIM = 1159; public static final int PPC_INS_TSR = 1160; public static final int PPC_INS_TW = 1161; public static final int PPC_INS_TWEQ = 1162; public static final int PPC_INS_TWEQI = 1163; public static final int PPC_INS_TWGE = 1164; public static final int PPC_INS_TWGEI = 1165; public static final int PPC_INS_TWGT = 1166; public static final int PPC_INS_TWGTI = 1167; public static final int PPC_INS_TWI = 1168; public static final int PPC_INS_TWLE = 1169; public static final int PPC_INS_TWLEI = 1170; public static final int PPC_INS_TWLGE = 1171; public static final int PPC_INS_TWLGEI = 1172; public static final int PPC_INS_TWLGT = 1173; public static final int PPC_INS_TWLGTI = 1174; public static final int PPC_INS_TWLLE = 1175; public static final int PPC_INS_TWLLEI = 1176; public static final int PPC_INS_TWLLT = 1177; public static final int PPC_INS_TWLLTI = 1178; public static final int PPC_INS_TWLNG = 1179; public static final int PPC_INS_TWLNGI = 1180; public static final int PPC_INS_TWLNL = 1181; public static final int PPC_INS_TWLNLI = 1182; public static final int PPC_INS_TWLT = 1183; public static final int PPC_INS_TWLTI = 1184; public static final int PPC_INS_TWNE = 1185; public static final int PPC_INS_TWNEI = 1186; public static final int PPC_INS_TWNG = 1187; public static final int PPC_INS_TWNGI = 1188; public static final int PPC_INS_TWNL = 1189; public static final int PPC_INS_TWNLI = 1190; public static final int PPC_INS_TWU = 1191; public static final int PPC_INS_TWUI = 1192; public static final int PPC_INS_VABSDUB = 1193; public static final int PPC_INS_VABSDUH = 1194; public static final int PPC_INS_VABSDUW = 1195; public static final int PPC_INS_VADDCUQ = 1196; public static final int PPC_INS_VADDCUW = 1197; public static final int PPC_INS_VADDECUQ = 1198; public static final int PPC_INS_VADDEUQM = 1199; public static final int PPC_INS_VADDFP = 1200; public static final int PPC_INS_VADDSBS = 1201; public static final int PPC_INS_VADDSHS = 1202; public static final int PPC_INS_VADDSWS = 1203; public static final int PPC_INS_VADDUBM = 1204; public static final int PPC_INS_VADDUBS = 1205; public static final int PPC_INS_VADDUDM = 1206; public static final int PPC_INS_VADDUHM = 1207; public static final int PPC_INS_VADDUHS = 1208; public static final int PPC_INS_VADDUQM = 1209; public static final int PPC_INS_VADDUWM = 1210; public static final int PPC_INS_VADDUWS = 1211; public static final int PPC_INS_VAND = 1212; public static final int PPC_INS_VANDC = 1213; public static final int PPC_INS_VAVGSB = 1214; public static final int PPC_INS_VAVGSH = 1215; public static final int PPC_INS_VAVGSW = 1216; public static final int PPC_INS_VAVGUB = 1217; public static final int PPC_INS_VAVGUH = 1218; public static final int PPC_INS_VAVGUW = 1219; public static final int PPC_INS_VBPERMD = 1220; public static final int PPC_INS_VBPERMQ = 1221; public static final int PPC_INS_VCFSX = 1222; public static final int PPC_INS_VCFUX = 1223; public static final int PPC_INS_VCIPHER = 1224; public static final int PPC_INS_VCIPHERLAST = 1225; public static final int PPC_INS_VCLZB = 1226; public static final int PPC_INS_VCLZD = 1227; public static final int PPC_INS_VCLZH = 1228; public static final int PPC_INS_VCLZLSBB = 1229; public static final int PPC_INS_VCLZW = 1230; public static final int PPC_INS_VCMPBFP = 1231; public static final int PPC_INS_VCMPEQFP = 1232; public static final int PPC_INS_VCMPEQUB = 1233; public static final int PPC_INS_VCMPEQUD = 1234; public static final int PPC_INS_VCMPEQUH = 1235; public static final int PPC_INS_VCMPEQUW = 1236; public static final int PPC_INS_VCMPGEFP = 1237; public static final int PPC_INS_VCMPGTFP = 1238; public static final int PPC_INS_VCMPGTSB = 1239; public static final int PPC_INS_VCMPGTSD = 1240; public static final int PPC_INS_VCMPGTSH = 1241; public static final int PPC_INS_VCMPGTSW = 1242; public static final int PPC_INS_VCMPGTUB = 1243; public static final int PPC_INS_VCMPGTUD = 1244; public static final int PPC_INS_VCMPGTUH = 1245; public static final int PPC_INS_VCMPGTUW = 1246; public static final int PPC_INS_VCMPNEB = 1247; public static final int PPC_INS_VCMPNEH = 1248; public static final int PPC_INS_VCMPNEW = 1249; public static final int PPC_INS_VCMPNEZB = 1250; public static final int PPC_INS_VCMPNEZH = 1251; public static final int PPC_INS_VCMPNEZW = 1252; public static final int PPC_INS_VCTSXS = 1253; public static final int PPC_INS_VCTUXS = 1254; public static final int PPC_INS_VCTZB = 1255; public static final int PPC_INS_VCTZD = 1256; public static final int PPC_INS_VCTZH = 1257; public static final int PPC_INS_VCTZLSBB = 1258; public static final int PPC_INS_VCTZW = 1259; public static final int PPC_INS_VEQV = 1260; public static final int PPC_INS_VEXPTEFP = 1261; public static final int PPC_INS_VEXTRACTD = 1262; public static final int PPC_INS_VEXTRACTUB = 1263; public static final int PPC_INS_VEXTRACTUH = 1264; public static final int PPC_INS_VEXTRACTUW = 1265; public static final int PPC_INS_VEXTSB2D = 1266; public static final int PPC_INS_VEXTSB2W = 1267; public static final int PPC_INS_VEXTSH2D = 1268; public static final int PPC_INS_VEXTSH2W = 1269; public static final int PPC_INS_VEXTSW2D = 1270; public static final int PPC_INS_VEXTUBLX = 1271; public static final int PPC_INS_VEXTUBRX = 1272; public static final int PPC_INS_VEXTUHLX = 1273; public static final int PPC_INS_VEXTUHRX = 1274; public static final int PPC_INS_VEXTUWLX = 1275; public static final int PPC_INS_VEXTUWRX = 1276; public static final int PPC_INS_VGBBD = 1277; public static final int PPC_INS_VINSERTB = 1278; public static final int PPC_INS_VINSERTD = 1279; public static final int PPC_INS_VINSERTH = 1280; public static final int PPC_INS_VINSERTW = 1281; public static final int PPC_INS_VLOGEFP = 1282; public static final int PPC_INS_VMADDFP = 1283; public static final int PPC_INS_VMAXFP = 1284; public static final int PPC_INS_VMAXSB = 1285; public static final int PPC_INS_VMAXSD = 1286; public static final int PPC_INS_VMAXSH = 1287; public static final int PPC_INS_VMAXSW = 1288; public static final int PPC_INS_VMAXUB = 1289; public static final int PPC_INS_VMAXUD = 1290; public static final int PPC_INS_VMAXUH = 1291; public static final int PPC_INS_VMAXUW = 1292; public static final int PPC_INS_VMHADDSHS = 1293; public static final int PPC_INS_VMHRADDSHS = 1294; public static final int PPC_INS_VMINFP = 1295; public static final int PPC_INS_VMINSB = 1296; public static final int PPC_INS_VMINSD = 1297; public static final int PPC_INS_VMINSH = 1298; public static final int PPC_INS_VMINSW = 1299; public static final int PPC_INS_VMINUB = 1300; public static final int PPC_INS_VMINUD = 1301; public static final int PPC_INS_VMINUH = 1302; public static final int PPC_INS_VMINUW = 1303; public static final int PPC_INS_VMLADDUHM = 1304; public static final int PPC_INS_VMR = 1305; public static final int PPC_INS_VMRGEW = 1306; public static final int PPC_INS_VMRGHB = 1307; public static final int PPC_INS_VMRGHH = 1308; public static final int PPC_INS_VMRGHW = 1309; public static final int PPC_INS_VMRGLB = 1310; public static final int PPC_INS_VMRGLH = 1311; public static final int PPC_INS_VMRGLW = 1312; public static final int PPC_INS_VMRGOW = 1313; public static final int PPC_INS_VMSUMMBM = 1314; public static final int PPC_INS_VMSUMSHM = 1315; public static final int PPC_INS_VMSUMSHS = 1316; public static final int PPC_INS_VMSUMUBM = 1317; public static final int PPC_INS_VMSUMUHM = 1318; public static final int PPC_INS_VMSUMUHS = 1319; public static final int PPC_INS_VMUL10CUQ = 1320; public static final int PPC_INS_VMUL10ECUQ = 1321; public static final int PPC_INS_VMUL10EUQ = 1322; public static final int PPC_INS_VMUL10UQ = 1323; public static final int PPC_INS_VMULESB = 1324; public static final int PPC_INS_VMULESH = 1325; public static final int PPC_INS_VMULESW = 1326; public static final int PPC_INS_VMULEUB = 1327; public static final int PPC_INS_VMULEUH = 1328; public static final int PPC_INS_VMULEUW = 1329; public static final int PPC_INS_VMULOSB = 1330; public static final int PPC_INS_VMULOSH = 1331; public static final int PPC_INS_VMULOSW = 1332; public static final int PPC_INS_VMULOUB = 1333; public static final int PPC_INS_VMULOUH = 1334; public static final int PPC_INS_VMULOUW = 1335; public static final int PPC_INS_VMULUWM = 1336; public static final int PPC_INS_VNAND = 1337; public static final int PPC_INS_VNCIPHER = 1338; public static final int PPC_INS_VNCIPHERLAST = 1339; public static final int PPC_INS_VNEGD = 1340; public static final int PPC_INS_VNEGW = 1341; public static final int PPC_INS_VNMSUBFP = 1342; public static final int PPC_INS_VNOR = 1343; public static final int PPC_INS_VNOT = 1344; public static final int PPC_INS_VOR = 1345; public static final int PPC_INS_VORC = 1346; public static final int PPC_INS_VPERM = 1347; public static final int PPC_INS_VPERMR = 1348; public static final int PPC_INS_VPERMXOR = 1349; public static final int PPC_INS_VPKPX = 1350; public static final int PPC_INS_VPKSDSS = 1351; public static final int PPC_INS_VPKSDUS = 1352; public static final int PPC_INS_VPKSHSS = 1353; public static final int PPC_INS_VPKSHUS = 1354; public static final int PPC_INS_VPKSWSS = 1355; public static final int PPC_INS_VPKSWUS = 1356; public static final int PPC_INS_VPKUDUM = 1357; public static final int PPC_INS_VPKUDUS = 1358; public static final int PPC_INS_VPKUHUM = 1359; public static final int PPC_INS_VPKUHUS = 1360; public static final int PPC_INS_VPKUWUM = 1361; public static final int PPC_INS_VPKUWUS = 1362; public static final int PPC_INS_VPMSUMB = 1363; public static final int PPC_INS_VPMSUMD = 1364; public static final int PPC_INS_VPMSUMH = 1365; public static final int PPC_INS_VPMSUMW = 1366; public static final int PPC_INS_VPOPCNTB = 1367; public static final int PPC_INS_VPOPCNTD = 1368; public static final int PPC_INS_VPOPCNTH = 1369; public static final int PPC_INS_VPOPCNTW = 1370; public static final int PPC_INS_VPRTYBD = 1371; public static final int PPC_INS_VPRTYBQ = 1372; public static final int PPC_INS_VPRTYBW = 1373; public static final int PPC_INS_VREFP = 1374; public static final int PPC_INS_VRFIM = 1375; public static final int PPC_INS_VRFIN = 1376; public static final int PPC_INS_VRFIP = 1377; public static final int PPC_INS_VRFIZ = 1378; public static final int PPC_INS_VRLB = 1379; public static final int PPC_INS_VRLD = 1380; public static final int PPC_INS_VRLDMI = 1381; public static final int PPC_INS_VRLDNM = 1382; public static final int PPC_INS_VRLH = 1383; public static final int PPC_INS_VRLW = 1384; public static final int PPC_INS_VRLWMI = 1385; public static final int PPC_INS_VRLWNM = 1386; public static final int PPC_INS_VRSQRTEFP = 1387; public static final int PPC_INS_VSBOX = 1388; public static final int PPC_INS_VSEL = 1389; public static final int PPC_INS_VSHASIGMAD = 1390; public static final int PPC_INS_VSHASIGMAW = 1391; public static final int PPC_INS_VSL = 1392; public static final int PPC_INS_VSLB = 1393; public static final int PPC_INS_VSLD = 1394; public static final int PPC_INS_VSLDOI = 1395; public static final int PPC_INS_VSLH = 1396; public static final int PPC_INS_VSLO = 1397; public static final int PPC_INS_VSLV = 1398; public static final int PPC_INS_VSLW = 1399; public static final int PPC_INS_VSPLTB = 1400; public static final int PPC_INS_VSPLTH = 1401; public static final int PPC_INS_VSPLTISB = 1402; public static final int PPC_INS_VSPLTISH = 1403; public static final int PPC_INS_VSPLTISW = 1404; public static final int PPC_INS_VSPLTW = 1405; public static final int PPC_INS_VSR = 1406; public static final int PPC_INS_VSRAB = 1407; public static final int PPC_INS_VSRAD = 1408; public static final int PPC_INS_VSRAH = 1409; public static final int PPC_INS_VSRAW = 1410; public static final int PPC_INS_VSRB = 1411; public static final int PPC_INS_VSRD = 1412; public static final int PPC_INS_VSRH = 1413; public static final int PPC_INS_VSRO = 1414; public static final int PPC_INS_VSRV = 1415; public static final int PPC_INS_VSRW = 1416; public static final int PPC_INS_VSUBCUQ = 1417; public static final int PPC_INS_VSUBCUW = 1418; public static final int PPC_INS_VSUBECUQ = 1419; public static final int PPC_INS_VSUBEUQM = 1420; public static final int PPC_INS_VSUBFP = 1421; public static final int PPC_INS_VSUBSBS = 1422; public static final int PPC_INS_VSUBSHS = 1423; public static final int PPC_INS_VSUBSWS = 1424; public static final int PPC_INS_VSUBUBM = 1425; public static final int PPC_INS_VSUBUBS = 1426; public static final int PPC_INS_VSUBUDM = 1427; public static final int PPC_INS_VSUBUHM = 1428; public static final int PPC_INS_VSUBUHS = 1429; public static final int PPC_INS_VSUBUQM = 1430; public static final int PPC_INS_VSUBUWM = 1431; public static final int PPC_INS_VSUBUWS = 1432; public static final int PPC_INS_VSUM2SWS = 1433; public static final int PPC_INS_VSUM4SBS = 1434; public static final int PPC_INS_VSUM4SHS = 1435; public static final int PPC_INS_VSUM4UBS = 1436; public static final int PPC_INS_VSUMSWS = 1437; public static final int PPC_INS_VUPKHPX = 1438; public static final int PPC_INS_VUPKHSB = 1439; public static final int PPC_INS_VUPKHSH = 1440; public static final int PPC_INS_VUPKHSW = 1441; public static final int PPC_INS_VUPKLPX = 1442; public static final int PPC_INS_VUPKLSB = 1443; public static final int PPC_INS_VUPKLSH = 1444; public static final int PPC_INS_VUPKLSW = 1445; public static final int PPC_INS_VXOR = 1446; public static final int PPC_INS_WAIT = 1447; public static final int PPC_INS_WAITIMPL = 1448; public static final int PPC_INS_WAITRSV = 1449; public static final int PPC_INS_WRTEE = 1450; public static final int PPC_INS_WRTEEI = 1451; public static final int PPC_INS_XNOP = 1452; public static final int PPC_INS_XOR = 1453; public static final int PPC_INS_XORI = 1454; public static final int PPC_INS_XORIS = 1455; public static final int PPC_INS_XSABSDP = 1456; public static final int PPC_INS_XSABSQP = 1457; public static final int PPC_INS_XSADDDP = 1458; public static final int PPC_INS_XSADDQP = 1459; public static final int PPC_INS_XSADDQPO = 1460; public static final int PPC_INS_XSADDSP = 1461; public static final int PPC_INS_XSCMPEQDP = 1462; public static final int PPC_INS_XSCMPEXPDP = 1463; public static final int PPC_INS_XSCMPEXPQP = 1464; public static final int PPC_INS_XSCMPGEDP = 1465; public static final int PPC_INS_XSCMPGTDP = 1466; public static final int PPC_INS_XSCMPODP = 1467; public static final int PPC_INS_XSCMPOQP = 1468; public static final int PPC_INS_XSCMPUDP = 1469; public static final int PPC_INS_XSCMPUQP = 1470; public static final int PPC_INS_XSCPSGNDP = 1471; public static final int PPC_INS_XSCPSGNQP = 1472; public static final int PPC_INS_XSCVDPHP = 1473; public static final int PPC_INS_XSCVDPQP = 1474; public static final int PPC_INS_XSCVDPSP = 1475; public static final int PPC_INS_XSCVDPSPN = 1476; public static final int PPC_INS_XSCVDPSXDS = 1477; public static final int PPC_INS_XSCVDPSXWS = 1478; public static final int PPC_INS_XSCVDPUXDS = 1479; public static final int PPC_INS_XSCVDPUXWS = 1480; public static final int PPC_INS_XSCVHPDP = 1481; public static final int PPC_INS_XSCVQPDP = 1482; public static final int PPC_INS_XSCVQPDPO = 1483; public static final int PPC_INS_XSCVQPSDZ = 1484; public static final int PPC_INS_XSCVQPSWZ = 1485; public static final int PPC_INS_XSCVQPUDZ = 1486; public static final int PPC_INS_XSCVQPUWZ = 1487; public static final int PPC_INS_XSCVSDQP = 1488; public static final int PPC_INS_XSCVSPDP = 1489; public static final int PPC_INS_XSCVSPDPN = 1490; public static final int PPC_INS_XSCVSXDDP = 1491; public static final int PPC_INS_XSCVSXDSP = 1492; public static final int PPC_INS_XSCVUDQP = 1493; public static final int PPC_INS_XSCVUXDDP = 1494; public static final int PPC_INS_XSCVUXDSP = 1495; public static final int PPC_INS_XSDIVDP = 1496; public static final int PPC_INS_XSDIVQP = 1497; public static final int PPC_INS_XSDIVQPO = 1498; public static final int PPC_INS_XSDIVSP = 1499; public static final int PPC_INS_XSIEXPDP = 1500; public static final int PPC_INS_XSIEXPQP = 1501; public static final int PPC_INS_XSMADDADP = 1502; public static final int PPC_INS_XSMADDASP = 1503; public static final int PPC_INS_XSMADDMDP = 1504; public static final int PPC_INS_XSMADDMSP = 1505; public static final int PPC_INS_XSMADDQP = 1506; public static final int PPC_INS_XSMADDQPO = 1507; public static final int PPC_INS_XSMAXCDP = 1508; public static final int PPC_INS_XSMAXDP = 1509; public static final int PPC_INS_XSMAXJDP = 1510; public static final int PPC_INS_XSMINCDP = 1511; public static final int PPC_INS_XSMINDP = 1512; public static final int PPC_INS_XSMINJDP = 1513; public static final int PPC_INS_XSMSUBADP = 1514; public static final int PPC_INS_XSMSUBASP = 1515; public static final int PPC_INS_XSMSUBMDP = 1516; public static final int PPC_INS_XSMSUBMSP = 1517; public static final int PPC_INS_XSMSUBQP = 1518; public static final int PPC_INS_XSMSUBQPO = 1519; public static final int PPC_INS_XSMULDP = 1520; public static final int PPC_INS_XSMULQP = 1521; public static final int PPC_INS_XSMULQPO = 1522; public static final int PPC_INS_XSMULSP = 1523; public static final int PPC_INS_XSNABSDP = 1524; public static final int PPC_INS_XSNABSQP = 1525; public static final int PPC_INS_XSNEGDP = 1526; public static final int PPC_INS_XSNEGQP = 1527; public static final int PPC_INS_XSNMADDADP = 1528; public static final int PPC_INS_XSNMADDASP = 1529; public static final int PPC_INS_XSNMADDMDP = 1530; public static final int PPC_INS_XSNMADDMSP = 1531; public static final int PPC_INS_XSNMADDQP = 1532; public static final int PPC_INS_XSNMADDQPO = 1533; public static final int PPC_INS_XSNMSUBADP = 1534; public static final int PPC_INS_XSNMSUBASP = 1535; public static final int PPC_INS_XSNMSUBMDP = 1536; public static final int PPC_INS_XSNMSUBMSP = 1537; public static final int PPC_INS_XSNMSUBQP = 1538; public static final int PPC_INS_XSNMSUBQPO = 1539; public static final int PPC_INS_XSRDPI = 1540; public static final int PPC_INS_XSRDPIC = 1541; public static final int PPC_INS_XSRDPIM = 1542; public static final int PPC_INS_XSRDPIP = 1543; public static final int PPC_INS_XSRDPIZ = 1544; public static final int PPC_INS_XSREDP = 1545; public static final int PPC_INS_XSRESP = 1546; public static final int PPC_INS_XSRQPI = 1547; public static final int PPC_INS_XSRQPIX = 1548; public static final int PPC_INS_XSRQPXP = 1549; public static final int PPC_INS_XSRSP = 1550; public static final int PPC_INS_XSRSQRTEDP = 1551; public static final int PPC_INS_XSRSQRTESP = 1552; public static final int PPC_INS_XSSQRTDP = 1553; public static final int PPC_INS_XSSQRTQP = 1554; public static final int PPC_INS_XSSQRTQPO = 1555; public static final int PPC_INS_XSSQRTSP = 1556; public static final int PPC_INS_XSSUBDP = 1557; public static final int PPC_INS_XSSUBQP = 1558; public static final int PPC_INS_XSSUBQPO = 1559; public static final int PPC_INS_XSSUBSP = 1560; public static final int PPC_INS_XSTDIVDP = 1561; public static final int PPC_INS_XSTSQRTDP = 1562; public static final int PPC_INS_XSTSTDCDP = 1563; public static final int PPC_INS_XSTSTDCQP = 1564; public static final int PPC_INS_XSTSTDCSP = 1565; public static final int PPC_INS_XSXEXPDP = 1566; public static final int PPC_INS_XSXEXPQP = 1567; public static final int PPC_INS_XSXSIGDP = 1568; public static final int PPC_INS_XSXSIGQP = 1569; public static final int PPC_INS_XVABSDP = 1570; public static final int PPC_INS_XVABSSP = 1571; public static final int PPC_INS_XVADDDP = 1572; public static final int PPC_INS_XVADDSP = 1573; public static final int PPC_INS_XVCMPEQDP = 1574; public static final int PPC_INS_XVCMPEQSP = 1575; public static final int PPC_INS_XVCMPGEDP = 1576; public static final int PPC_INS_XVCMPGESP = 1577; public static final int PPC_INS_XVCMPGTDP = 1578; public static final int PPC_INS_XVCMPGTSP = 1579; public static final int PPC_INS_XVCPSGNDP = 1580; public static final int PPC_INS_XVCPSGNSP = 1581; public static final int PPC_INS_XVCVDPSP = 1582; public static final int PPC_INS_XVCVDPSXDS = 1583; public static final int PPC_INS_XVCVDPSXWS = 1584; public static final int PPC_INS_XVCVDPUXDS = 1585; public static final int PPC_INS_XVCVDPUXWS = 1586; public static final int PPC_INS_XVCVHPSP = 1587; public static final int PPC_INS_XVCVSPDP = 1588; public static final int PPC_INS_XVCVSPHP = 1589; public static final int PPC_INS_XVCVSPSXDS = 1590; public static final int PPC_INS_XVCVSPSXWS = 1591; public static final int PPC_INS_XVCVSPUXDS = 1592; public static final int PPC_INS_XVCVSPUXWS = 1593; public static final int PPC_INS_XVCVSXDDP = 1594; public static final int PPC_INS_XVCVSXDSP = 1595; public static final int PPC_INS_XVCVSXWDP = 1596; public static final int PPC_INS_XVCVSXWSP = 1597; public static final int PPC_INS_XVCVUXDDP = 1598; public static final int PPC_INS_XVCVUXDSP = 1599; public static final int PPC_INS_XVCVUXWDP = 1600; public static final int PPC_INS_XVCVUXWSP = 1601; public static final int PPC_INS_XVDIVDP = 1602; public static final int PPC_INS_XVDIVSP = 1603; public static final int PPC_INS_XVIEXPDP = 1604; public static final int PPC_INS_XVIEXPSP = 1605; public static final int PPC_INS_XVMADDADP = 1606; public static final int PPC_INS_XVMADDASP = 1607; public static final int PPC_INS_XVMADDMDP = 1608; public static final int PPC_INS_XVMADDMSP = 1609; public static final int PPC_INS_XVMAXDP = 1610; public static final int PPC_INS_XVMAXSP = 1611; public static final int PPC_INS_XVMINDP = 1612; public static final int PPC_INS_XVMINSP = 1613; public static final int PPC_INS_XVMOVDP = 1614; public static final int PPC_INS_XVMOVSP = 1615; public static final int PPC_INS_XVMSUBADP = 1616; public static final int PPC_INS_XVMSUBASP = 1617; public static final int PPC_INS_XVMSUBMDP = 1618; public static final int PPC_INS_XVMSUBMSP = 1619; public static final int PPC_INS_XVMULDP = 1620; public static final int PPC_INS_XVMULSP = 1621; public static final int PPC_INS_XVNABSDP = 1622; public static final int PPC_INS_XVNABSSP = 1623; public static final int PPC_INS_XVNEGDP = 1624; public static final int PPC_INS_XVNEGSP = 1625; public static final int PPC_INS_XVNMADDADP = 1626; public static final int PPC_INS_XVNMADDASP = 1627; public static final int PPC_INS_XVNMADDMDP = 1628; public static final int PPC_INS_XVNMADDMSP = 1629; public static final int PPC_INS_XVNMSUBADP = 1630; public static final int PPC_INS_XVNMSUBASP = 1631; public static final int PPC_INS_XVNMSUBMDP = 1632; public static final int PPC_INS_XVNMSUBMSP = 1633; public static final int PPC_INS_XVRDPI = 1634; public static final int PPC_INS_XVRDPIC = 1635; public static final int PPC_INS_XVRDPIM = 1636; public static final int PPC_INS_XVRDPIP = 1637; public static final int PPC_INS_XVRDPIZ = 1638; public static final int PPC_INS_XVREDP = 1639; public static final int PPC_INS_XVRESP = 1640; public static final int PPC_INS_XVRSPI = 1641; public static final int PPC_INS_XVRSPIC = 1642; public static final int PPC_INS_XVRSPIM = 1643; public static final int PPC_INS_XVRSPIP = 1644; public static final int PPC_INS_XVRSPIZ = 1645; public static final int PPC_INS_XVRSQRTEDP = 1646; public static final int PPC_INS_XVRSQRTESP = 1647; public static final int PPC_INS_XVSQRTDP = 1648; public static final int PPC_INS_XVSQRTSP = 1649; public static final int PPC_INS_XVSUBDP = 1650; public static final int PPC_INS_XVSUBSP = 1651; public static final int PPC_INS_XVTDIVDP = 1652; public static final int PPC_INS_XVTDIVSP = 1653; public static final int PPC_INS_XVTSQRTDP = 1654; public static final int PPC_INS_XVTSQRTSP = 1655; public static final int PPC_INS_XVTSTDCDP = 1656; public static final int PPC_INS_XVTSTDCSP = 1657; public static final int PPC_INS_XVXEXPDP = 1658; public static final int PPC_INS_XVXEXPSP = 1659; public static final int PPC_INS_XVXSIGDP = 1660; public static final int PPC_INS_XVXSIGSP = 1661; public static final int PPC_INS_XXBRD = 1662; public static final int PPC_INS_XXBRH = 1663; public static final int PPC_INS_XXBRQ = 1664; public static final int PPC_INS_XXBRW = 1665; public static final int PPC_INS_XXEXTRACTUW = 1666; public static final int PPC_INS_XXINSERTW = 1667; public static final int PPC_INS_XXLAND = 1668; public static final int PPC_INS_XXLANDC = 1669; public static final int PPC_INS_XXLEQV = 1670; public static final int PPC_INS_XXLNAND = 1671; public static final int PPC_INS_XXLNOR = 1672; public static final int PPC_INS_XXLOR = 1673; public static final int PPC_INS_XXLORC = 1674; public static final int PPC_INS_XXLXOR = 1675; public static final int PPC_INS_XXMRGHD = 1676; public static final int PPC_INS_XXMRGHW = 1677; public static final int PPC_INS_XXMRGLD = 1678; public static final int PPC_INS_XXMRGLW = 1679; public static final int PPC_INS_XXPERM = 1680; public static final int PPC_INS_XXPERMDI = 1681; public static final int PPC_INS_XXPERMR = 1682; public static final int PPC_INS_XXSEL = 1683; public static final int PPC_INS_XXSLDWI = 1684; public static final int PPC_INS_XXSPLTD = 1685; public static final int PPC_INS_XXSPLTIB = 1686; public static final int PPC_INS_XXSPLTW = 1687; public static final int PPC_INS_XXSWAPD = 1688; public static final int PPC_INS_ENDING = 1689; public static final int PPC_GRP_INVALID = 0; public static final int PPC_GRP_JUMP = 1; public static final int PPC_GRP_ALTIVEC = 128; public static final int PPC_GRP_MODE32 = 129; public static final int PPC_GRP_MODE64 = 130; public static final int PPC_GRP_BOOKE = 131; public static final int PPC_GRP_NOTBOOKE = 132; public static final int PPC_GRP_SPE = 133; public static final int PPC_GRP_VSX = 134; public static final int PPC_GRP_E500 = 135; public static final int PPC_GRP_PPC4XX = 136; public static final int PPC_GRP_PPC6XX = 137; public static final int PPC_GRP_ICBT = 138; public static final int PPC_GRP_P8ALTIVEC = 139; public static final int PPC_GRP_P8VECTOR = 140; public static final int PPC_GRP_QPX = 141; public static final int PPC_GRP_ENDING = 142; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Sparc.java000064400000000000000000000035330072674642500224540ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.Sparc_const.*; public class Sparc { public static class MemType extends Structure { public byte base; public byte index; public int disp; @Override public List getFieldOrder() { return Arrays.asList("base", "index", "disp"); } } public static class OpValue extends Union { public int reg; public int imm; public MemType mem; } public static class Operand extends Structure { public int type; public OpValue value; public void read() { readField("type"); if (type == SPARC_OP_MEM) value.setType(MemType.class); if (type == SPARC_OP_IMM || type == SPARC_OP_REG) value.setType(Integer.TYPE); if (type == SPARC_OP_INVALID) return; readField("value"); } @Override public List getFieldOrder() { return Arrays.asList("type", "value"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public int cc; public int hint; public byte op_count; public Operand [] op; public UnionOpInfo() { op = new Operand[4]; } public void read() { readField("cc"); readField("hint"); readField("op_count"); op = new Operand[op_count]; if (op_count != 0) readField("op"); } @Override public List getFieldOrder() { return Arrays.asList("cc", "hint", "op_count", "op"); } } public static class OpInfo extends Capstone.OpInfo { public int cc; public int hint; public Operand [] op; public OpInfo(UnionOpInfo op_info) { cc = op_info.cc; hint = op_info.hint; op = op_info.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/Sparc_const.java000064400000000000000000000474320072674642500236700ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Sparc_const { public static final int SPARC_CC_INVALID = 0; public static final int SPARC_CC_ICC_A = 8+256; public static final int SPARC_CC_ICC_N = 0+256; public static final int SPARC_CC_ICC_NE = 9+256; public static final int SPARC_CC_ICC_E = 1+256; public static final int SPARC_CC_ICC_G = 10+256; public static final int SPARC_CC_ICC_LE = 2+256; public static final int SPARC_CC_ICC_GE = 11+256; public static final int SPARC_CC_ICC_L = 3+256; public static final int SPARC_CC_ICC_GU = 12+256; public static final int SPARC_CC_ICC_LEU = 4+256; public static final int SPARC_CC_ICC_CC = 13+256; public static final int SPARC_CC_ICC_CS = 5+256; public static final int SPARC_CC_ICC_POS = 14+256; public static final int SPARC_CC_ICC_NEG = 6+256; public static final int SPARC_CC_ICC_VC = 15+256; public static final int SPARC_CC_ICC_VS = 7+256; public static final int SPARC_CC_FCC_A = 8+16+256; public static final int SPARC_CC_FCC_N = 0+16+256; public static final int SPARC_CC_FCC_U = 7+16+256; public static final int SPARC_CC_FCC_G = 6+16+256; public static final int SPARC_CC_FCC_UG = 5+16+256; public static final int SPARC_CC_FCC_L = 4+16+256; public static final int SPARC_CC_FCC_UL = 3+16+256; public static final int SPARC_CC_FCC_LG = 2+16+256; public static final int SPARC_CC_FCC_NE = 1+16+256; public static final int SPARC_CC_FCC_E = 9+16+256; public static final int SPARC_CC_FCC_UE = 10+16+256; public static final int SPARC_CC_FCC_GE = 11+16+256; public static final int SPARC_CC_FCC_UGE = 12+16+256; public static final int SPARC_CC_FCC_LE = 13+16+256; public static final int SPARC_CC_FCC_ULE = 14+16+256; public static final int SPARC_CC_FCC_O = 15+16+256; public static final int SPARC_HINT_INVALID = 0; public static final int SPARC_HINT_A = 1<<0; public static final int SPARC_HINT_PT = 1<<1; public static final int SPARC_HINT_PN = 1<<2; public static final int SPARC_OP_INVALID = 0; public static final int SPARC_OP_REG = 1; public static final int SPARC_OP_IMM = 2; public static final int SPARC_OP_MEM = 3; public static final int SPARC_REG_INVALID = 0; public static final int SPARC_REG_F0 = 1; public static final int SPARC_REG_F1 = 2; public static final int SPARC_REG_F2 = 3; public static final int SPARC_REG_F3 = 4; public static final int SPARC_REG_F4 = 5; public static final int SPARC_REG_F5 = 6; public static final int SPARC_REG_F6 = 7; public static final int SPARC_REG_F7 = 8; public static final int SPARC_REG_F8 = 9; public static final int SPARC_REG_F9 = 10; public static final int SPARC_REG_F10 = 11; public static final int SPARC_REG_F11 = 12; public static final int SPARC_REG_F12 = 13; public static final int SPARC_REG_F13 = 14; public static final int SPARC_REG_F14 = 15; public static final int SPARC_REG_F15 = 16; public static final int SPARC_REG_F16 = 17; public static final int SPARC_REG_F17 = 18; public static final int SPARC_REG_F18 = 19; public static final int SPARC_REG_F19 = 20; public static final int SPARC_REG_F20 = 21; public static final int SPARC_REG_F21 = 22; public static final int SPARC_REG_F22 = 23; public static final int SPARC_REG_F23 = 24; public static final int SPARC_REG_F24 = 25; public static final int SPARC_REG_F25 = 26; public static final int SPARC_REG_F26 = 27; public static final int SPARC_REG_F27 = 28; public static final int SPARC_REG_F28 = 29; public static final int SPARC_REG_F29 = 30; public static final int SPARC_REG_F30 = 31; public static final int SPARC_REG_F31 = 32; public static final int SPARC_REG_F32 = 33; public static final int SPARC_REG_F34 = 34; public static final int SPARC_REG_F36 = 35; public static final int SPARC_REG_F38 = 36; public static final int SPARC_REG_F40 = 37; public static final int SPARC_REG_F42 = 38; public static final int SPARC_REG_F44 = 39; public static final int SPARC_REG_F46 = 40; public static final int SPARC_REG_F48 = 41; public static final int SPARC_REG_F50 = 42; public static final int SPARC_REG_F52 = 43; public static final int SPARC_REG_F54 = 44; public static final int SPARC_REG_F56 = 45; public static final int SPARC_REG_F58 = 46; public static final int SPARC_REG_F60 = 47; public static final int SPARC_REG_F62 = 48; public static final int SPARC_REG_FCC0 = 49; public static final int SPARC_REG_FCC1 = 50; public static final int SPARC_REG_FCC2 = 51; public static final int SPARC_REG_FCC3 = 52; public static final int SPARC_REG_FP = 53; public static final int SPARC_REG_G0 = 54; public static final int SPARC_REG_G1 = 55; public static final int SPARC_REG_G2 = 56; public static final int SPARC_REG_G3 = 57; public static final int SPARC_REG_G4 = 58; public static final int SPARC_REG_G5 = 59; public static final int SPARC_REG_G6 = 60; public static final int SPARC_REG_G7 = 61; public static final int SPARC_REG_I0 = 62; public static final int SPARC_REG_I1 = 63; public static final int SPARC_REG_I2 = 64; public static final int SPARC_REG_I3 = 65; public static final int SPARC_REG_I4 = 66; public static final int SPARC_REG_I5 = 67; public static final int SPARC_REG_I7 = 68; public static final int SPARC_REG_ICC = 69; public static final int SPARC_REG_L0 = 70; public static final int SPARC_REG_L1 = 71; public static final int SPARC_REG_L2 = 72; public static final int SPARC_REG_L3 = 73; public static final int SPARC_REG_L4 = 74; public static final int SPARC_REG_L5 = 75; public static final int SPARC_REG_L6 = 76; public static final int SPARC_REG_L7 = 77; public static final int SPARC_REG_O0 = 78; public static final int SPARC_REG_O1 = 79; public static final int SPARC_REG_O2 = 80; public static final int SPARC_REG_O3 = 81; public static final int SPARC_REG_O4 = 82; public static final int SPARC_REG_O5 = 83; public static final int SPARC_REG_O7 = 84; public static final int SPARC_REG_SP = 85; public static final int SPARC_REG_Y = 86; public static final int SPARC_REG_XCC = 87; public static final int SPARC_REG_ENDING = 88; public static final int SPARC_REG_O6 = SPARC_REG_SP; public static final int SPARC_REG_I6 = SPARC_REG_FP; public static final int SPARC_INS_INVALID = 0; public static final int SPARC_INS_ADDCC = 1; public static final int SPARC_INS_ADDX = 2; public static final int SPARC_INS_ADDXCC = 3; public static final int SPARC_INS_ADDXC = 4; public static final int SPARC_INS_ADDXCCC = 5; public static final int SPARC_INS_ADD = 6; public static final int SPARC_INS_ALIGNADDR = 7; public static final int SPARC_INS_ALIGNADDRL = 8; public static final int SPARC_INS_ANDCC = 9; public static final int SPARC_INS_ANDNCC = 10; public static final int SPARC_INS_ANDN = 11; public static final int SPARC_INS_AND = 12; public static final int SPARC_INS_ARRAY16 = 13; public static final int SPARC_INS_ARRAY32 = 14; public static final int SPARC_INS_ARRAY8 = 15; public static final int SPARC_INS_B = 16; public static final int SPARC_INS_JMP = 17; public static final int SPARC_INS_BMASK = 18; public static final int SPARC_INS_FB = 19; public static final int SPARC_INS_BRGEZ = 20; public static final int SPARC_INS_BRGZ = 21; public static final int SPARC_INS_BRLEZ = 22; public static final int SPARC_INS_BRLZ = 23; public static final int SPARC_INS_BRNZ = 24; public static final int SPARC_INS_BRZ = 25; public static final int SPARC_INS_BSHUFFLE = 26; public static final int SPARC_INS_CALL = 27; public static final int SPARC_INS_CASX = 28; public static final int SPARC_INS_CAS = 29; public static final int SPARC_INS_CMASK16 = 30; public static final int SPARC_INS_CMASK32 = 31; public static final int SPARC_INS_CMASK8 = 32; public static final int SPARC_INS_CMP = 33; public static final int SPARC_INS_EDGE16 = 34; public static final int SPARC_INS_EDGE16L = 35; public static final int SPARC_INS_EDGE16LN = 36; public static final int SPARC_INS_EDGE16N = 37; public static final int SPARC_INS_EDGE32 = 38; public static final int SPARC_INS_EDGE32L = 39; public static final int SPARC_INS_EDGE32LN = 40; public static final int SPARC_INS_EDGE32N = 41; public static final int SPARC_INS_EDGE8 = 42; public static final int SPARC_INS_EDGE8L = 43; public static final int SPARC_INS_EDGE8LN = 44; public static final int SPARC_INS_EDGE8N = 45; public static final int SPARC_INS_FABSD = 46; public static final int SPARC_INS_FABSQ = 47; public static final int SPARC_INS_FABSS = 48; public static final int SPARC_INS_FADDD = 49; public static final int SPARC_INS_FADDQ = 50; public static final int SPARC_INS_FADDS = 51; public static final int SPARC_INS_FALIGNDATA = 52; public static final int SPARC_INS_FAND = 53; public static final int SPARC_INS_FANDNOT1 = 54; public static final int SPARC_INS_FANDNOT1S = 55; public static final int SPARC_INS_FANDNOT2 = 56; public static final int SPARC_INS_FANDNOT2S = 57; public static final int SPARC_INS_FANDS = 58; public static final int SPARC_INS_FCHKSM16 = 59; public static final int SPARC_INS_FCMPD = 60; public static final int SPARC_INS_FCMPEQ16 = 61; public static final int SPARC_INS_FCMPEQ32 = 62; public static final int SPARC_INS_FCMPGT16 = 63; public static final int SPARC_INS_FCMPGT32 = 64; public static final int SPARC_INS_FCMPLE16 = 65; public static final int SPARC_INS_FCMPLE32 = 66; public static final int SPARC_INS_FCMPNE16 = 67; public static final int SPARC_INS_FCMPNE32 = 68; public static final int SPARC_INS_FCMPQ = 69; public static final int SPARC_INS_FCMPS = 70; public static final int SPARC_INS_FDIVD = 71; public static final int SPARC_INS_FDIVQ = 72; public static final int SPARC_INS_FDIVS = 73; public static final int SPARC_INS_FDMULQ = 74; public static final int SPARC_INS_FDTOI = 75; public static final int SPARC_INS_FDTOQ = 76; public static final int SPARC_INS_FDTOS = 77; public static final int SPARC_INS_FDTOX = 78; public static final int SPARC_INS_FEXPAND = 79; public static final int SPARC_INS_FHADDD = 80; public static final int SPARC_INS_FHADDS = 81; public static final int SPARC_INS_FHSUBD = 82; public static final int SPARC_INS_FHSUBS = 83; public static final int SPARC_INS_FITOD = 84; public static final int SPARC_INS_FITOQ = 85; public static final int SPARC_INS_FITOS = 86; public static final int SPARC_INS_FLCMPD = 87; public static final int SPARC_INS_FLCMPS = 88; public static final int SPARC_INS_FLUSHW = 89; public static final int SPARC_INS_FMEAN16 = 90; public static final int SPARC_INS_FMOVD = 91; public static final int SPARC_INS_FMOVQ = 92; public static final int SPARC_INS_FMOVRDGEZ = 93; public static final int SPARC_INS_FMOVRQGEZ = 94; public static final int SPARC_INS_FMOVRSGEZ = 95; public static final int SPARC_INS_FMOVRDGZ = 96; public static final int SPARC_INS_FMOVRQGZ = 97; public static final int SPARC_INS_FMOVRSGZ = 98; public static final int SPARC_INS_FMOVRDLEZ = 99; public static final int SPARC_INS_FMOVRQLEZ = 100; public static final int SPARC_INS_FMOVRSLEZ = 101; public static final int SPARC_INS_FMOVRDLZ = 102; public static final int SPARC_INS_FMOVRQLZ = 103; public static final int SPARC_INS_FMOVRSLZ = 104; public static final int SPARC_INS_FMOVRDNZ = 105; public static final int SPARC_INS_FMOVRQNZ = 106; public static final int SPARC_INS_FMOVRSNZ = 107; public static final int SPARC_INS_FMOVRDZ = 108; public static final int SPARC_INS_FMOVRQZ = 109; public static final int SPARC_INS_FMOVRSZ = 110; public static final int SPARC_INS_FMOVS = 111; public static final int SPARC_INS_FMUL8SUX16 = 112; public static final int SPARC_INS_FMUL8ULX16 = 113; public static final int SPARC_INS_FMUL8X16 = 114; public static final int SPARC_INS_FMUL8X16AL = 115; public static final int SPARC_INS_FMUL8X16AU = 116; public static final int SPARC_INS_FMULD = 117; public static final int SPARC_INS_FMULD8SUX16 = 118; public static final int SPARC_INS_FMULD8ULX16 = 119; public static final int SPARC_INS_FMULQ = 120; public static final int SPARC_INS_FMULS = 121; public static final int SPARC_INS_FNADDD = 122; public static final int SPARC_INS_FNADDS = 123; public static final int SPARC_INS_FNAND = 124; public static final int SPARC_INS_FNANDS = 125; public static final int SPARC_INS_FNEGD = 126; public static final int SPARC_INS_FNEGQ = 127; public static final int SPARC_INS_FNEGS = 128; public static final int SPARC_INS_FNHADDD = 129; public static final int SPARC_INS_FNHADDS = 130; public static final int SPARC_INS_FNOR = 131; public static final int SPARC_INS_FNORS = 132; public static final int SPARC_INS_FNOT1 = 133; public static final int SPARC_INS_FNOT1S = 134; public static final int SPARC_INS_FNOT2 = 135; public static final int SPARC_INS_FNOT2S = 136; public static final int SPARC_INS_FONE = 137; public static final int SPARC_INS_FONES = 138; public static final int SPARC_INS_FOR = 139; public static final int SPARC_INS_FORNOT1 = 140; public static final int SPARC_INS_FORNOT1S = 141; public static final int SPARC_INS_FORNOT2 = 142; public static final int SPARC_INS_FORNOT2S = 143; public static final int SPARC_INS_FORS = 144; public static final int SPARC_INS_FPACK16 = 145; public static final int SPARC_INS_FPACK32 = 146; public static final int SPARC_INS_FPACKFIX = 147; public static final int SPARC_INS_FPADD16 = 148; public static final int SPARC_INS_FPADD16S = 149; public static final int SPARC_INS_FPADD32 = 150; public static final int SPARC_INS_FPADD32S = 151; public static final int SPARC_INS_FPADD64 = 152; public static final int SPARC_INS_FPMERGE = 153; public static final int SPARC_INS_FPSUB16 = 154; public static final int SPARC_INS_FPSUB16S = 155; public static final int SPARC_INS_FPSUB32 = 156; public static final int SPARC_INS_FPSUB32S = 157; public static final int SPARC_INS_FQTOD = 158; public static final int SPARC_INS_FQTOI = 159; public static final int SPARC_INS_FQTOS = 160; public static final int SPARC_INS_FQTOX = 161; public static final int SPARC_INS_FSLAS16 = 162; public static final int SPARC_INS_FSLAS32 = 163; public static final int SPARC_INS_FSLL16 = 164; public static final int SPARC_INS_FSLL32 = 165; public static final int SPARC_INS_FSMULD = 166; public static final int SPARC_INS_FSQRTD = 167; public static final int SPARC_INS_FSQRTQ = 168; public static final int SPARC_INS_FSQRTS = 169; public static final int SPARC_INS_FSRA16 = 170; public static final int SPARC_INS_FSRA32 = 171; public static final int SPARC_INS_FSRC1 = 172; public static final int SPARC_INS_FSRC1S = 173; public static final int SPARC_INS_FSRC2 = 174; public static final int SPARC_INS_FSRC2S = 175; public static final int SPARC_INS_FSRL16 = 176; public static final int SPARC_INS_FSRL32 = 177; public static final int SPARC_INS_FSTOD = 178; public static final int SPARC_INS_FSTOI = 179; public static final int SPARC_INS_FSTOQ = 180; public static final int SPARC_INS_FSTOX = 181; public static final int SPARC_INS_FSUBD = 182; public static final int SPARC_INS_FSUBQ = 183; public static final int SPARC_INS_FSUBS = 184; public static final int SPARC_INS_FXNOR = 185; public static final int SPARC_INS_FXNORS = 186; public static final int SPARC_INS_FXOR = 187; public static final int SPARC_INS_FXORS = 188; public static final int SPARC_INS_FXTOD = 189; public static final int SPARC_INS_FXTOQ = 190; public static final int SPARC_INS_FXTOS = 191; public static final int SPARC_INS_FZERO = 192; public static final int SPARC_INS_FZEROS = 193; public static final int SPARC_INS_JMPL = 194; public static final int SPARC_INS_LDD = 195; public static final int SPARC_INS_LD = 196; public static final int SPARC_INS_LDQ = 197; public static final int SPARC_INS_LDSB = 198; public static final int SPARC_INS_LDSH = 199; public static final int SPARC_INS_LDSW = 200; public static final int SPARC_INS_LDUB = 201; public static final int SPARC_INS_LDUH = 202; public static final int SPARC_INS_LDX = 203; public static final int SPARC_INS_LZCNT = 204; public static final int SPARC_INS_MEMBAR = 205; public static final int SPARC_INS_MOVDTOX = 206; public static final int SPARC_INS_MOV = 207; public static final int SPARC_INS_MOVRGEZ = 208; public static final int SPARC_INS_MOVRGZ = 209; public static final int SPARC_INS_MOVRLEZ = 210; public static final int SPARC_INS_MOVRLZ = 211; public static final int SPARC_INS_MOVRNZ = 212; public static final int SPARC_INS_MOVRZ = 213; public static final int SPARC_INS_MOVSTOSW = 214; public static final int SPARC_INS_MOVSTOUW = 215; public static final int SPARC_INS_MULX = 216; public static final int SPARC_INS_NOP = 217; public static final int SPARC_INS_ORCC = 218; public static final int SPARC_INS_ORNCC = 219; public static final int SPARC_INS_ORN = 220; public static final int SPARC_INS_OR = 221; public static final int SPARC_INS_PDIST = 222; public static final int SPARC_INS_PDISTN = 223; public static final int SPARC_INS_POPC = 224; public static final int SPARC_INS_RD = 225; public static final int SPARC_INS_RESTORE = 226; public static final int SPARC_INS_RETT = 227; public static final int SPARC_INS_SAVE = 228; public static final int SPARC_INS_SDIVCC = 229; public static final int SPARC_INS_SDIVX = 230; public static final int SPARC_INS_SDIV = 231; public static final int SPARC_INS_SETHI = 232; public static final int SPARC_INS_SHUTDOWN = 233; public static final int SPARC_INS_SIAM = 234; public static final int SPARC_INS_SLLX = 235; public static final int SPARC_INS_SLL = 236; public static final int SPARC_INS_SMULCC = 237; public static final int SPARC_INS_SMUL = 238; public static final int SPARC_INS_SRAX = 239; public static final int SPARC_INS_SRA = 240; public static final int SPARC_INS_SRLX = 241; public static final int SPARC_INS_SRL = 242; public static final int SPARC_INS_STBAR = 243; public static final int SPARC_INS_STB = 244; public static final int SPARC_INS_STD = 245; public static final int SPARC_INS_ST = 246; public static final int SPARC_INS_STH = 247; public static final int SPARC_INS_STQ = 248; public static final int SPARC_INS_STX = 249; public static final int SPARC_INS_SUBCC = 250; public static final int SPARC_INS_SUBX = 251; public static final int SPARC_INS_SUBXCC = 252; public static final int SPARC_INS_SUB = 253; public static final int SPARC_INS_SWAP = 254; public static final int SPARC_INS_TADDCCTV = 255; public static final int SPARC_INS_TADDCC = 256; public static final int SPARC_INS_T = 257; public static final int SPARC_INS_TSUBCCTV = 258; public static final int SPARC_INS_TSUBCC = 259; public static final int SPARC_INS_UDIVCC = 260; public static final int SPARC_INS_UDIVX = 261; public static final int SPARC_INS_UDIV = 262; public static final int SPARC_INS_UMULCC = 263; public static final int SPARC_INS_UMULXHI = 264; public static final int SPARC_INS_UMUL = 265; public static final int SPARC_INS_UNIMP = 266; public static final int SPARC_INS_FCMPED = 267; public static final int SPARC_INS_FCMPEQ = 268; public static final int SPARC_INS_FCMPES = 269; public static final int SPARC_INS_WR = 270; public static final int SPARC_INS_XMULX = 271; public static final int SPARC_INS_XMULXHI = 272; public static final int SPARC_INS_XNORCC = 273; public static final int SPARC_INS_XNOR = 274; public static final int SPARC_INS_XORCC = 275; public static final int SPARC_INS_XOR = 276; public static final int SPARC_INS_RET = 277; public static final int SPARC_INS_RETL = 278; public static final int SPARC_INS_ENDING = 279; public static final int SPARC_GRP_INVALID = 0; public static final int SPARC_GRP_JUMP = 1; public static final int SPARC_GRP_HARDQUAD = 128; public static final int SPARC_GRP_V9 = 129; public static final int SPARC_GRP_VIS = 130; public static final int SPARC_GRP_VIS2 = 131; public static final int SPARC_GRP_VIS3 = 132; public static final int SPARC_GRP_32BIT = 133; public static final int SPARC_GRP_64BIT = 134; public static final int SPARC_GRP_ENDING = 135; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Systemz.java000064400000000000000000000035310072674642500230600ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.Sysz_const.*; public class Systemz { public static class MemType extends Structure { public byte base; public byte index; public long length; public long disp; @Override public List getFieldOrder() { return Arrays.asList("base", "index", "length", "disp"); } } public static class OpValue extends Union { public int reg; public long imm; public MemType mem; } public static class Operand extends Structure { public int type; public OpValue value; public void read() { readField("type"); if (type == SYSZ_OP_MEM) value.setType(MemType.class); if (type == SYSZ_OP_IMM) value.setType(Long.TYPE); if (type == SYSZ_OP_REG || type == SYSZ_OP_ACREG) value.setType(Integer.TYPE); if (type == SYSZ_OP_INVALID) return; readField("value"); } @Override public List getFieldOrder() { return Arrays.asList("type", "value"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public int cc; public byte op_count; public Operand [] op; public UnionOpInfo() { op = new Operand[6]; } public void read() { readField("cc"); readField("op_count"); op = new Operand[op_count]; if (op_count != 0) readField("op"); } @Override public List getFieldOrder() { return Arrays.asList("cc", "op_count", "op"); } } public static class OpInfo extends Capstone.OpInfo { public int cc; public Operand [] op; public OpInfo(UnionOpInfo op_info) { cc = op_info.cc; op = op_info.op; } } } capstone-sys-0.15.0/capstone/bindings/java/capstone/Sysz_const.java000064400000000000000000003506130072674642500235660ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Sysz_const { public static final int SYSZ_CC_INVALID = 0; public static final int SYSZ_CC_O = 1; public static final int SYSZ_CC_H = 2; public static final int SYSZ_CC_NLE = 3; public static final int SYSZ_CC_L = 4; public static final int SYSZ_CC_NHE = 5; public static final int SYSZ_CC_LH = 6; public static final int SYSZ_CC_NE = 7; public static final int SYSZ_CC_E = 8; public static final int SYSZ_CC_NLH = 9; public static final int SYSZ_CC_HE = 10; public static final int SYSZ_CC_NL = 11; public static final int SYSZ_CC_LE = 12; public static final int SYSZ_CC_NH = 13; public static final int SYSZ_CC_NO = 14; public static final int SYSZ_OP_INVALID = 0; public static final int SYSZ_OP_REG = 1; public static final int SYSZ_OP_IMM = 2; public static final int SYSZ_OP_MEM = 3; public static final int SYSZ_OP_ACREG = 64; public static final int SYSZ_REG_INVALID = 0; public static final int SYSZ_REG_0 = 1; public static final int SYSZ_REG_1 = 2; public static final int SYSZ_REG_2 = 3; public static final int SYSZ_REG_3 = 4; public static final int SYSZ_REG_4 = 5; public static final int SYSZ_REG_5 = 6; public static final int SYSZ_REG_6 = 7; public static final int SYSZ_REG_7 = 8; public static final int SYSZ_REG_8 = 9; public static final int SYSZ_REG_9 = 10; public static final int SYSZ_REG_10 = 11; public static final int SYSZ_REG_11 = 12; public static final int SYSZ_REG_12 = 13; public static final int SYSZ_REG_13 = 14; public static final int SYSZ_REG_14 = 15; public static final int SYSZ_REG_15 = 16; public static final int SYSZ_REG_CC = 17; public static final int SYSZ_REG_F0 = 18; public static final int SYSZ_REG_F1 = 19; public static final int SYSZ_REG_F2 = 20; public static final int SYSZ_REG_F3 = 21; public static final int SYSZ_REG_F4 = 22; public static final int SYSZ_REG_F5 = 23; public static final int SYSZ_REG_F6 = 24; public static final int SYSZ_REG_F7 = 25; public static final int SYSZ_REG_F8 = 26; public static final int SYSZ_REG_F9 = 27; public static final int SYSZ_REG_F10 = 28; public static final int SYSZ_REG_F11 = 29; public static final int SYSZ_REG_F12 = 30; public static final int SYSZ_REG_F13 = 31; public static final int SYSZ_REG_F14 = 32; public static final int SYSZ_REG_F15 = 33; public static final int SYSZ_REG_R0L = 34; public static final int SYSZ_REG_A0 = 35; public static final int SYSZ_REG_A1 = 36; public static final int SYSZ_REG_A2 = 37; public static final int SYSZ_REG_A3 = 38; public static final int SYSZ_REG_A4 = 39; public static final int SYSZ_REG_A5 = 40; public static final int SYSZ_REG_A6 = 41; public static final int SYSZ_REG_A7 = 42; public static final int SYSZ_REG_A8 = 43; public static final int SYSZ_REG_A9 = 44; public static final int SYSZ_REG_A10 = 45; public static final int SYSZ_REG_A11 = 46; public static final int SYSZ_REG_A12 = 47; public static final int SYSZ_REG_A13 = 48; public static final int SYSZ_REG_A14 = 49; public static final int SYSZ_REG_A15 = 50; public static final int SYSZ_REG_C0 = 51; public static final int SYSZ_REG_C1 = 52; public static final int SYSZ_REG_C2 = 53; public static final int SYSZ_REG_C3 = 54; public static final int SYSZ_REG_C4 = 55; public static final int SYSZ_REG_C5 = 56; public static final int SYSZ_REG_C6 = 57; public static final int SYSZ_REG_C7 = 58; public static final int SYSZ_REG_C8 = 59; public static final int SYSZ_REG_C9 = 60; public static final int SYSZ_REG_C10 = 61; public static final int SYSZ_REG_C11 = 62; public static final int SYSZ_REG_C12 = 63; public static final int SYSZ_REG_C13 = 64; public static final int SYSZ_REG_C14 = 65; public static final int SYSZ_REG_C15 = 66; public static final int SYSZ_REG_V0 = 67; public static final int SYSZ_REG_V1 = 68; public static final int SYSZ_REG_V2 = 69; public static final int SYSZ_REG_V3 = 70; public static final int SYSZ_REG_V4 = 71; public static final int SYSZ_REG_V5 = 72; public static final int SYSZ_REG_V6 = 73; public static final int SYSZ_REG_V7 = 74; public static final int SYSZ_REG_V8 = 75; public static final int SYSZ_REG_V9 = 76; public static final int SYSZ_REG_V10 = 77; public static final int SYSZ_REG_V11 = 78; public static final int SYSZ_REG_V12 = 79; public static final int SYSZ_REG_V13 = 80; public static final int SYSZ_REG_V14 = 81; public static final int SYSZ_REG_V15 = 82; public static final int SYSZ_REG_V16 = 83; public static final int SYSZ_REG_V17 = 84; public static final int SYSZ_REG_V18 = 85; public static final int SYSZ_REG_V19 = 86; public static final int SYSZ_REG_V20 = 87; public static final int SYSZ_REG_V21 = 88; public static final int SYSZ_REG_V22 = 89; public static final int SYSZ_REG_V23 = 90; public static final int SYSZ_REG_V24 = 91; public static final int SYSZ_REG_V25 = 92; public static final int SYSZ_REG_V26 = 93; public static final int SYSZ_REG_V27 = 94; public static final int SYSZ_REG_V28 = 95; public static final int SYSZ_REG_V29 = 96; public static final int SYSZ_REG_V30 = 97; public static final int SYSZ_REG_V31 = 98; public static final int SYSZ_REG_F16 = 99; public static final int SYSZ_REG_F17 = 100; public static final int SYSZ_REG_F18 = 101; public static final int SYSZ_REG_F19 = 102; public static final int SYSZ_REG_F20 = 103; public static final int SYSZ_REG_F21 = 104; public static final int SYSZ_REG_F22 = 105; public static final int SYSZ_REG_F23 = 106; public static final int SYSZ_REG_F24 = 107; public static final int SYSZ_REG_F25 = 108; public static final int SYSZ_REG_F26 = 109; public static final int SYSZ_REG_F27 = 110; public static final int SYSZ_REG_F28 = 111; public static final int SYSZ_REG_F29 = 112; public static final int SYSZ_REG_F30 = 113; public static final int SYSZ_REG_F31 = 114; public static final int SYSZ_REG_F0Q = 115; public static final int SYSZ_REG_F4Q = 116; public static final int SYSZ_REG_ENDING = 117; public static final int SYSZ_INS_INVALID = 0; public static final int SYSZ_INS_A = 1; public static final int SYSZ_INS_ADB = 2; public static final int SYSZ_INS_ADBR = 3; public static final int SYSZ_INS_AEB = 4; public static final int SYSZ_INS_AEBR = 5; public static final int SYSZ_INS_AFI = 6; public static final int SYSZ_INS_AG = 7; public static final int SYSZ_INS_AGF = 8; public static final int SYSZ_INS_AGFI = 9; public static final int SYSZ_INS_AGFR = 10; public static final int SYSZ_INS_AGHI = 11; public static final int SYSZ_INS_AGHIK = 12; public static final int SYSZ_INS_AGR = 13; public static final int SYSZ_INS_AGRK = 14; public static final int SYSZ_INS_AGSI = 15; public static final int SYSZ_INS_AH = 16; public static final int SYSZ_INS_AHI = 17; public static final int SYSZ_INS_AHIK = 18; public static final int SYSZ_INS_AHY = 19; public static final int SYSZ_INS_AIH = 20; public static final int SYSZ_INS_AL = 21; public static final int SYSZ_INS_ALC = 22; public static final int SYSZ_INS_ALCG = 23; public static final int SYSZ_INS_ALCGR = 24; public static final int SYSZ_INS_ALCR = 25; public static final int SYSZ_INS_ALFI = 26; public static final int SYSZ_INS_ALG = 27; public static final int SYSZ_INS_ALGF = 28; public static final int SYSZ_INS_ALGFI = 29; public static final int SYSZ_INS_ALGFR = 30; public static final int SYSZ_INS_ALGHSIK = 31; public static final int SYSZ_INS_ALGR = 32; public static final int SYSZ_INS_ALGRK = 33; public static final int SYSZ_INS_ALHSIK = 34; public static final int SYSZ_INS_ALR = 35; public static final int SYSZ_INS_ALRK = 36; public static final int SYSZ_INS_ALY = 37; public static final int SYSZ_INS_AR = 38; public static final int SYSZ_INS_ARK = 39; public static final int SYSZ_INS_ASI = 40; public static final int SYSZ_INS_AXBR = 41; public static final int SYSZ_INS_AY = 42; public static final int SYSZ_INS_BCR = 43; public static final int SYSZ_INS_BRC = 44; public static final int SYSZ_INS_BRCL = 45; public static final int SYSZ_INS_CGIJ = 46; public static final int SYSZ_INS_CGRJ = 47; public static final int SYSZ_INS_CIJ = 48; public static final int SYSZ_INS_CLGIJ = 49; public static final int SYSZ_INS_CLGRJ = 50; public static final int SYSZ_INS_CLIJ = 51; public static final int SYSZ_INS_CLRJ = 52; public static final int SYSZ_INS_CRJ = 53; public static final int SYSZ_INS_BER = 54; public static final int SYSZ_INS_JE = 55; public static final int SYSZ_INS_JGE = 56; public static final int SYSZ_INS_LOCE = 57; public static final int SYSZ_INS_LOCGE = 58; public static final int SYSZ_INS_LOCGRE = 59; public static final int SYSZ_INS_LOCRE = 60; public static final int SYSZ_INS_STOCE = 61; public static final int SYSZ_INS_STOCGE = 62; public static final int SYSZ_INS_BHR = 63; public static final int SYSZ_INS_BHER = 64; public static final int SYSZ_INS_JHE = 65; public static final int SYSZ_INS_JGHE = 66; public static final int SYSZ_INS_LOCHE = 67; public static final int SYSZ_INS_LOCGHE = 68; public static final int SYSZ_INS_LOCGRHE = 69; public static final int SYSZ_INS_LOCRHE = 70; public static final int SYSZ_INS_STOCHE = 71; public static final int SYSZ_INS_STOCGHE = 72; public static final int SYSZ_INS_JH = 73; public static final int SYSZ_INS_JGH = 74; public static final int SYSZ_INS_LOCH = 75; public static final int SYSZ_INS_LOCGH = 76; public static final int SYSZ_INS_LOCGRH = 77; public static final int SYSZ_INS_LOCRH = 78; public static final int SYSZ_INS_STOCH = 79; public static final int SYSZ_INS_STOCGH = 80; public static final int SYSZ_INS_CGIJNLH = 81; public static final int SYSZ_INS_CGRJNLH = 82; public static final int SYSZ_INS_CIJNLH = 83; public static final int SYSZ_INS_CLGIJNLH = 84; public static final int SYSZ_INS_CLGRJNLH = 85; public static final int SYSZ_INS_CLIJNLH = 86; public static final int SYSZ_INS_CLRJNLH = 87; public static final int SYSZ_INS_CRJNLH = 88; public static final int SYSZ_INS_CGIJE = 89; public static final int SYSZ_INS_CGRJE = 90; public static final int SYSZ_INS_CIJE = 91; public static final int SYSZ_INS_CLGIJE = 92; public static final int SYSZ_INS_CLGRJE = 93; public static final int SYSZ_INS_CLIJE = 94; public static final int SYSZ_INS_CLRJE = 95; public static final int SYSZ_INS_CRJE = 96; public static final int SYSZ_INS_CGIJNLE = 97; public static final int SYSZ_INS_CGRJNLE = 98; public static final int SYSZ_INS_CIJNLE = 99; public static final int SYSZ_INS_CLGIJNLE = 100; public static final int SYSZ_INS_CLGRJNLE = 101; public static final int SYSZ_INS_CLIJNLE = 102; public static final int SYSZ_INS_CLRJNLE = 103; public static final int SYSZ_INS_CRJNLE = 104; public static final int SYSZ_INS_CGIJH = 105; public static final int SYSZ_INS_CGRJH = 106; public static final int SYSZ_INS_CIJH = 107; public static final int SYSZ_INS_CLGIJH = 108; public static final int SYSZ_INS_CLGRJH = 109; public static final int SYSZ_INS_CLIJH = 110; public static final int SYSZ_INS_CLRJH = 111; public static final int SYSZ_INS_CRJH = 112; public static final int SYSZ_INS_CGIJNL = 113; public static final int SYSZ_INS_CGRJNL = 114; public static final int SYSZ_INS_CIJNL = 115; public static final int SYSZ_INS_CLGIJNL = 116; public static final int SYSZ_INS_CLGRJNL = 117; public static final int SYSZ_INS_CLIJNL = 118; public static final int SYSZ_INS_CLRJNL = 119; public static final int SYSZ_INS_CRJNL = 120; public static final int SYSZ_INS_CGIJHE = 121; public static final int SYSZ_INS_CGRJHE = 122; public static final int SYSZ_INS_CIJHE = 123; public static final int SYSZ_INS_CLGIJHE = 124; public static final int SYSZ_INS_CLGRJHE = 125; public static final int SYSZ_INS_CLIJHE = 126; public static final int SYSZ_INS_CLRJHE = 127; public static final int SYSZ_INS_CRJHE = 128; public static final int SYSZ_INS_CGIJNHE = 129; public static final int SYSZ_INS_CGRJNHE = 130; public static final int SYSZ_INS_CIJNHE = 131; public static final int SYSZ_INS_CLGIJNHE = 132; public static final int SYSZ_INS_CLGRJNHE = 133; public static final int SYSZ_INS_CLIJNHE = 134; public static final int SYSZ_INS_CLRJNHE = 135; public static final int SYSZ_INS_CRJNHE = 136; public static final int SYSZ_INS_CGIJL = 137; public static final int SYSZ_INS_CGRJL = 138; public static final int SYSZ_INS_CIJL = 139; public static final int SYSZ_INS_CLGIJL = 140; public static final int SYSZ_INS_CLGRJL = 141; public static final int SYSZ_INS_CLIJL = 142; public static final int SYSZ_INS_CLRJL = 143; public static final int SYSZ_INS_CRJL = 144; public static final int SYSZ_INS_CGIJNH = 145; public static final int SYSZ_INS_CGRJNH = 146; public static final int SYSZ_INS_CIJNH = 147; public static final int SYSZ_INS_CLGIJNH = 148; public static final int SYSZ_INS_CLGRJNH = 149; public static final int SYSZ_INS_CLIJNH = 150; public static final int SYSZ_INS_CLRJNH = 151; public static final int SYSZ_INS_CRJNH = 152; public static final int SYSZ_INS_CGIJLE = 153; public static final int SYSZ_INS_CGRJLE = 154; public static final int SYSZ_INS_CIJLE = 155; public static final int SYSZ_INS_CLGIJLE = 156; public static final int SYSZ_INS_CLGRJLE = 157; public static final int SYSZ_INS_CLIJLE = 158; public static final int SYSZ_INS_CLRJLE = 159; public static final int SYSZ_INS_CRJLE = 160; public static final int SYSZ_INS_CGIJNE = 161; public static final int SYSZ_INS_CGRJNE = 162; public static final int SYSZ_INS_CIJNE = 163; public static final int SYSZ_INS_CLGIJNE = 164; public static final int SYSZ_INS_CLGRJNE = 165; public static final int SYSZ_INS_CLIJNE = 166; public static final int SYSZ_INS_CLRJNE = 167; public static final int SYSZ_INS_CRJNE = 168; public static final int SYSZ_INS_CGIJLH = 169; public static final int SYSZ_INS_CGRJLH = 170; public static final int SYSZ_INS_CIJLH = 171; public static final int SYSZ_INS_CLGIJLH = 172; public static final int SYSZ_INS_CLGRJLH = 173; public static final int SYSZ_INS_CLIJLH = 174; public static final int SYSZ_INS_CLRJLH = 175; public static final int SYSZ_INS_CRJLH = 176; public static final int SYSZ_INS_BLR = 177; public static final int SYSZ_INS_BLER = 178; public static final int SYSZ_INS_JLE = 179; public static final int SYSZ_INS_JGLE = 180; public static final int SYSZ_INS_LOCLE = 181; public static final int SYSZ_INS_LOCGLE = 182; public static final int SYSZ_INS_LOCGRLE = 183; public static final int SYSZ_INS_LOCRLE = 184; public static final int SYSZ_INS_STOCLE = 185; public static final int SYSZ_INS_STOCGLE = 186; public static final int SYSZ_INS_BLHR = 187; public static final int SYSZ_INS_JLH = 188; public static final int SYSZ_INS_JGLH = 189; public static final int SYSZ_INS_LOCLH = 190; public static final int SYSZ_INS_LOCGLH = 191; public static final int SYSZ_INS_LOCGRLH = 192; public static final int SYSZ_INS_LOCRLH = 193; public static final int SYSZ_INS_STOCLH = 194; public static final int SYSZ_INS_STOCGLH = 195; public static final int SYSZ_INS_JL = 196; public static final int SYSZ_INS_JGL = 197; public static final int SYSZ_INS_LOCL = 198; public static final int SYSZ_INS_LOCGL = 199; public static final int SYSZ_INS_LOCGRL = 200; public static final int SYSZ_INS_LOCRL = 201; public static final int SYSZ_INS_LOC = 202; public static final int SYSZ_INS_LOCG = 203; public static final int SYSZ_INS_LOCGR = 204; public static final int SYSZ_INS_LOCR = 205; public static final int SYSZ_INS_STOCL = 206; public static final int SYSZ_INS_STOCGL = 207; public static final int SYSZ_INS_BNER = 208; public static final int SYSZ_INS_JNE = 209; public static final int SYSZ_INS_JGNE = 210; public static final int SYSZ_INS_LOCNE = 211; public static final int SYSZ_INS_LOCGNE = 212; public static final int SYSZ_INS_LOCGRNE = 213; public static final int SYSZ_INS_LOCRNE = 214; public static final int SYSZ_INS_STOCNE = 215; public static final int SYSZ_INS_STOCGNE = 216; public static final int SYSZ_INS_BNHR = 217; public static final int SYSZ_INS_BNHER = 218; public static final int SYSZ_INS_JNHE = 219; public static final int SYSZ_INS_JGNHE = 220; public static final int SYSZ_INS_LOCNHE = 221; public static final int SYSZ_INS_LOCGNHE = 222; public static final int SYSZ_INS_LOCGRNHE = 223; public static final int SYSZ_INS_LOCRNHE = 224; public static final int SYSZ_INS_STOCNHE = 225; public static final int SYSZ_INS_STOCGNHE = 226; public static final int SYSZ_INS_JNH = 227; public static final int SYSZ_INS_JGNH = 228; public static final int SYSZ_INS_LOCNH = 229; public static final int SYSZ_INS_LOCGNH = 230; public static final int SYSZ_INS_LOCGRNH = 231; public static final int SYSZ_INS_LOCRNH = 232; public static final int SYSZ_INS_STOCNH = 233; public static final int SYSZ_INS_STOCGNH = 234; public static final int SYSZ_INS_BNLR = 235; public static final int SYSZ_INS_BNLER = 236; public static final int SYSZ_INS_JNLE = 237; public static final int SYSZ_INS_JGNLE = 238; public static final int SYSZ_INS_LOCNLE = 239; public static final int SYSZ_INS_LOCGNLE = 240; public static final int SYSZ_INS_LOCGRNLE = 241; public static final int SYSZ_INS_LOCRNLE = 242; public static final int SYSZ_INS_STOCNLE = 243; public static final int SYSZ_INS_STOCGNLE = 244; public static final int SYSZ_INS_BNLHR = 245; public static final int SYSZ_INS_JNLH = 246; public static final int SYSZ_INS_JGNLH = 247; public static final int SYSZ_INS_LOCNLH = 248; public static final int SYSZ_INS_LOCGNLH = 249; public static final int SYSZ_INS_LOCGRNLH = 250; public static final int SYSZ_INS_LOCRNLH = 251; public static final int SYSZ_INS_STOCNLH = 252; public static final int SYSZ_INS_STOCGNLH = 253; public static final int SYSZ_INS_JNL = 254; public static final int SYSZ_INS_JGNL = 255; public static final int SYSZ_INS_LOCNL = 256; public static final int SYSZ_INS_LOCGNL = 257; public static final int SYSZ_INS_LOCGRNL = 258; public static final int SYSZ_INS_LOCRNL = 259; public static final int SYSZ_INS_STOCNL = 260; public static final int SYSZ_INS_STOCGNL = 261; public static final int SYSZ_INS_BNOR = 262; public static final int SYSZ_INS_JNO = 263; public static final int SYSZ_INS_JGNO = 264; public static final int SYSZ_INS_LOCNO = 265; public static final int SYSZ_INS_LOCGNO = 266; public static final int SYSZ_INS_LOCGRNO = 267; public static final int SYSZ_INS_LOCRNO = 268; public static final int SYSZ_INS_STOCNO = 269; public static final int SYSZ_INS_STOCGNO = 270; public static final int SYSZ_INS_BOR = 271; public static final int SYSZ_INS_JO = 272; public static final int SYSZ_INS_JGO = 273; public static final int SYSZ_INS_LOCO = 274; public static final int SYSZ_INS_LOCGO = 275; public static final int SYSZ_INS_LOCGRO = 276; public static final int SYSZ_INS_LOCRO = 277; public static final int SYSZ_INS_STOCO = 278; public static final int SYSZ_INS_STOCGO = 279; public static final int SYSZ_INS_STOC = 280; public static final int SYSZ_INS_STOCG = 281; public static final int SYSZ_INS_BASR = 282; public static final int SYSZ_INS_BR = 283; public static final int SYSZ_INS_BRAS = 284; public static final int SYSZ_INS_BRASL = 285; public static final int SYSZ_INS_J = 286; public static final int SYSZ_INS_JG = 287; public static final int SYSZ_INS_BRCT = 288; public static final int SYSZ_INS_BRCTG = 289; public static final int SYSZ_INS_C = 290; public static final int SYSZ_INS_CDB = 291; public static final int SYSZ_INS_CDBR = 292; public static final int SYSZ_INS_CDFBR = 293; public static final int SYSZ_INS_CDGBR = 294; public static final int SYSZ_INS_CDLFBR = 295; public static final int SYSZ_INS_CDLGBR = 296; public static final int SYSZ_INS_CEB = 297; public static final int SYSZ_INS_CEBR = 298; public static final int SYSZ_INS_CEFBR = 299; public static final int SYSZ_INS_CEGBR = 300; public static final int SYSZ_INS_CELFBR = 301; public static final int SYSZ_INS_CELGBR = 302; public static final int SYSZ_INS_CFDBR = 303; public static final int SYSZ_INS_CFEBR = 304; public static final int SYSZ_INS_CFI = 305; public static final int SYSZ_INS_CFXBR = 306; public static final int SYSZ_INS_CG = 307; public static final int SYSZ_INS_CGDBR = 308; public static final int SYSZ_INS_CGEBR = 309; public static final int SYSZ_INS_CGF = 310; public static final int SYSZ_INS_CGFI = 311; public static final int SYSZ_INS_CGFR = 312; public static final int SYSZ_INS_CGFRL = 313; public static final int SYSZ_INS_CGH = 314; public static final int SYSZ_INS_CGHI = 315; public static final int SYSZ_INS_CGHRL = 316; public static final int SYSZ_INS_CGHSI = 317; public static final int SYSZ_INS_CGR = 318; public static final int SYSZ_INS_CGRL = 319; public static final int SYSZ_INS_CGXBR = 320; public static final int SYSZ_INS_CH = 321; public static final int SYSZ_INS_CHF = 322; public static final int SYSZ_INS_CHHSI = 323; public static final int SYSZ_INS_CHI = 324; public static final int SYSZ_INS_CHRL = 325; public static final int SYSZ_INS_CHSI = 326; public static final int SYSZ_INS_CHY = 327; public static final int SYSZ_INS_CIH = 328; public static final int SYSZ_INS_CL = 329; public static final int SYSZ_INS_CLC = 330; public static final int SYSZ_INS_CLFDBR = 331; public static final int SYSZ_INS_CLFEBR = 332; public static final int SYSZ_INS_CLFHSI = 333; public static final int SYSZ_INS_CLFI = 334; public static final int SYSZ_INS_CLFXBR = 335; public static final int SYSZ_INS_CLG = 336; public static final int SYSZ_INS_CLGDBR = 337; public static final int SYSZ_INS_CLGEBR = 338; public static final int SYSZ_INS_CLGF = 339; public static final int SYSZ_INS_CLGFI = 340; public static final int SYSZ_INS_CLGFR = 341; public static final int SYSZ_INS_CLGFRL = 342; public static final int SYSZ_INS_CLGHRL = 343; public static final int SYSZ_INS_CLGHSI = 344; public static final int SYSZ_INS_CLGR = 345; public static final int SYSZ_INS_CLGRL = 346; public static final int SYSZ_INS_CLGXBR = 347; public static final int SYSZ_INS_CLHF = 348; public static final int SYSZ_INS_CLHHSI = 349; public static final int SYSZ_INS_CLHRL = 350; public static final int SYSZ_INS_CLI = 351; public static final int SYSZ_INS_CLIH = 352; public static final int SYSZ_INS_CLIY = 353; public static final int SYSZ_INS_CLR = 354; public static final int SYSZ_INS_CLRL = 355; public static final int SYSZ_INS_CLST = 356; public static final int SYSZ_INS_CLY = 357; public static final int SYSZ_INS_CPSDR = 358; public static final int SYSZ_INS_CR = 359; public static final int SYSZ_INS_CRL = 360; public static final int SYSZ_INS_CS = 361; public static final int SYSZ_INS_CSG = 362; public static final int SYSZ_INS_CSY = 363; public static final int SYSZ_INS_CXBR = 364; public static final int SYSZ_INS_CXFBR = 365; public static final int SYSZ_INS_CXGBR = 366; public static final int SYSZ_INS_CXLFBR = 367; public static final int SYSZ_INS_CXLGBR = 368; public static final int SYSZ_INS_CY = 369; public static final int SYSZ_INS_DDB = 370; public static final int SYSZ_INS_DDBR = 371; public static final int SYSZ_INS_DEB = 372; public static final int SYSZ_INS_DEBR = 373; public static final int SYSZ_INS_DL = 374; public static final int SYSZ_INS_DLG = 375; public static final int SYSZ_INS_DLGR = 376; public static final int SYSZ_INS_DLR = 377; public static final int SYSZ_INS_DSG = 378; public static final int SYSZ_INS_DSGF = 379; public static final int SYSZ_INS_DSGFR = 380; public static final int SYSZ_INS_DSGR = 381; public static final int SYSZ_INS_DXBR = 382; public static final int SYSZ_INS_EAR = 383; public static final int SYSZ_INS_FIDBR = 384; public static final int SYSZ_INS_FIDBRA = 385; public static final int SYSZ_INS_FIEBR = 386; public static final int SYSZ_INS_FIEBRA = 387; public static final int SYSZ_INS_FIXBR = 388; public static final int SYSZ_INS_FIXBRA = 389; public static final int SYSZ_INS_FLOGR = 390; public static final int SYSZ_INS_IC = 391; public static final int SYSZ_INS_ICY = 392; public static final int SYSZ_INS_IIHF = 393; public static final int SYSZ_INS_IIHH = 394; public static final int SYSZ_INS_IIHL = 395; public static final int SYSZ_INS_IILF = 396; public static final int SYSZ_INS_IILH = 397; public static final int SYSZ_INS_IILL = 398; public static final int SYSZ_INS_IPM = 399; public static final int SYSZ_INS_L = 400; public static final int SYSZ_INS_LA = 401; public static final int SYSZ_INS_LAA = 402; public static final int SYSZ_INS_LAAG = 403; public static final int SYSZ_INS_LAAL = 404; public static final int SYSZ_INS_LAALG = 405; public static final int SYSZ_INS_LAN = 406; public static final int SYSZ_INS_LANG = 407; public static final int SYSZ_INS_LAO = 408; public static final int SYSZ_INS_LAOG = 409; public static final int SYSZ_INS_LARL = 410; public static final int SYSZ_INS_LAX = 411; public static final int SYSZ_INS_LAXG = 412; public static final int SYSZ_INS_LAY = 413; public static final int SYSZ_INS_LB = 414; public static final int SYSZ_INS_LBH = 415; public static final int SYSZ_INS_LBR = 416; public static final int SYSZ_INS_LCDBR = 417; public static final int SYSZ_INS_LCEBR = 418; public static final int SYSZ_INS_LCGFR = 419; public static final int SYSZ_INS_LCGR = 420; public static final int SYSZ_INS_LCR = 421; public static final int SYSZ_INS_LCXBR = 422; public static final int SYSZ_INS_LD = 423; public static final int SYSZ_INS_LDEB = 424; public static final int SYSZ_INS_LDEBR = 425; public static final int SYSZ_INS_LDGR = 426; public static final int SYSZ_INS_LDR = 427; public static final int SYSZ_INS_LDXBR = 428; public static final int SYSZ_INS_LDXBRA = 429; public static final int SYSZ_INS_LDY = 430; public static final int SYSZ_INS_LE = 431; public static final int SYSZ_INS_LEDBR = 432; public static final int SYSZ_INS_LEDBRA = 433; public static final int SYSZ_INS_LER = 434; public static final int SYSZ_INS_LEXBR = 435; public static final int SYSZ_INS_LEXBRA = 436; public static final int SYSZ_INS_LEY = 437; public static final int SYSZ_INS_LFH = 438; public static final int SYSZ_INS_LG = 439; public static final int SYSZ_INS_LGB = 440; public static final int SYSZ_INS_LGBR = 441; public static final int SYSZ_INS_LGDR = 442; public static final int SYSZ_INS_LGF = 443; public static final int SYSZ_INS_LGFI = 444; public static final int SYSZ_INS_LGFR = 445; public static final int SYSZ_INS_LGFRL = 446; public static final int SYSZ_INS_LGH = 447; public static final int SYSZ_INS_LGHI = 448; public static final int SYSZ_INS_LGHR = 449; public static final int SYSZ_INS_LGHRL = 450; public static final int SYSZ_INS_LGR = 451; public static final int SYSZ_INS_LGRL = 452; public static final int SYSZ_INS_LH = 453; public static final int SYSZ_INS_LHH = 454; public static final int SYSZ_INS_LHI = 455; public static final int SYSZ_INS_LHR = 456; public static final int SYSZ_INS_LHRL = 457; public static final int SYSZ_INS_LHY = 458; public static final int SYSZ_INS_LLC = 459; public static final int SYSZ_INS_LLCH = 460; public static final int SYSZ_INS_LLCR = 461; public static final int SYSZ_INS_LLGC = 462; public static final int SYSZ_INS_LLGCR = 463; public static final int SYSZ_INS_LLGF = 464; public static final int SYSZ_INS_LLGFR = 465; public static final int SYSZ_INS_LLGFRL = 466; public static final int SYSZ_INS_LLGH = 467; public static final int SYSZ_INS_LLGHR = 468; public static final int SYSZ_INS_LLGHRL = 469; public static final int SYSZ_INS_LLH = 470; public static final int SYSZ_INS_LLHH = 471; public static final int SYSZ_INS_LLHR = 472; public static final int SYSZ_INS_LLHRL = 473; public static final int SYSZ_INS_LLIHF = 474; public static final int SYSZ_INS_LLIHH = 475; public static final int SYSZ_INS_LLIHL = 476; public static final int SYSZ_INS_LLILF = 477; public static final int SYSZ_INS_LLILH = 478; public static final int SYSZ_INS_LLILL = 479; public static final int SYSZ_INS_LMG = 480; public static final int SYSZ_INS_LNDBR = 481; public static final int SYSZ_INS_LNEBR = 482; public static final int SYSZ_INS_LNGFR = 483; public static final int SYSZ_INS_LNGR = 484; public static final int SYSZ_INS_LNR = 485; public static final int SYSZ_INS_LNXBR = 486; public static final int SYSZ_INS_LPDBR = 487; public static final int SYSZ_INS_LPEBR = 488; public static final int SYSZ_INS_LPGFR = 489; public static final int SYSZ_INS_LPGR = 490; public static final int SYSZ_INS_LPR = 491; public static final int SYSZ_INS_LPXBR = 492; public static final int SYSZ_INS_LR = 493; public static final int SYSZ_INS_LRL = 494; public static final int SYSZ_INS_LRV = 495; public static final int SYSZ_INS_LRVG = 496; public static final int SYSZ_INS_LRVGR = 497; public static final int SYSZ_INS_LRVR = 498; public static final int SYSZ_INS_LT = 499; public static final int SYSZ_INS_LTDBR = 500; public static final int SYSZ_INS_LTEBR = 501; public static final int SYSZ_INS_LTG = 502; public static final int SYSZ_INS_LTGF = 503; public static final int SYSZ_INS_LTGFR = 504; public static final int SYSZ_INS_LTGR = 505; public static final int SYSZ_INS_LTR = 506; public static final int SYSZ_INS_LTXBR = 507; public static final int SYSZ_INS_LXDB = 508; public static final int SYSZ_INS_LXDBR = 509; public static final int SYSZ_INS_LXEB = 510; public static final int SYSZ_INS_LXEBR = 511; public static final int SYSZ_INS_LXR = 512; public static final int SYSZ_INS_LY = 513; public static final int SYSZ_INS_LZDR = 514; public static final int SYSZ_INS_LZER = 515; public static final int SYSZ_INS_LZXR = 516; public static final int SYSZ_INS_MADB = 517; public static final int SYSZ_INS_MADBR = 518; public static final int SYSZ_INS_MAEB = 519; public static final int SYSZ_INS_MAEBR = 520; public static final int SYSZ_INS_MDB = 521; public static final int SYSZ_INS_MDBR = 522; public static final int SYSZ_INS_MDEB = 523; public static final int SYSZ_INS_MDEBR = 524; public static final int SYSZ_INS_MEEB = 525; public static final int SYSZ_INS_MEEBR = 526; public static final int SYSZ_INS_MGHI = 527; public static final int SYSZ_INS_MH = 528; public static final int SYSZ_INS_MHI = 529; public static final int SYSZ_INS_MHY = 530; public static final int SYSZ_INS_MLG = 531; public static final int SYSZ_INS_MLGR = 532; public static final int SYSZ_INS_MS = 533; public static final int SYSZ_INS_MSDB = 534; public static final int SYSZ_INS_MSDBR = 535; public static final int SYSZ_INS_MSEB = 536; public static final int SYSZ_INS_MSEBR = 537; public static final int SYSZ_INS_MSFI = 538; public static final int SYSZ_INS_MSG = 539; public static final int SYSZ_INS_MSGF = 540; public static final int SYSZ_INS_MSGFI = 541; public static final int SYSZ_INS_MSGFR = 542; public static final int SYSZ_INS_MSGR = 543; public static final int SYSZ_INS_MSR = 544; public static final int SYSZ_INS_MSY = 545; public static final int SYSZ_INS_MVC = 546; public static final int SYSZ_INS_MVGHI = 547; public static final int SYSZ_INS_MVHHI = 548; public static final int SYSZ_INS_MVHI = 549; public static final int SYSZ_INS_MVI = 550; public static final int SYSZ_INS_MVIY = 551; public static final int SYSZ_INS_MVST = 552; public static final int SYSZ_INS_MXBR = 553; public static final int SYSZ_INS_MXDB = 554; public static final int SYSZ_INS_MXDBR = 555; public static final int SYSZ_INS_N = 556; public static final int SYSZ_INS_NC = 557; public static final int SYSZ_INS_NG = 558; public static final int SYSZ_INS_NGR = 559; public static final int SYSZ_INS_NGRK = 560; public static final int SYSZ_INS_NI = 561; public static final int SYSZ_INS_NIHF = 562; public static final int SYSZ_INS_NIHH = 563; public static final int SYSZ_INS_NIHL = 564; public static final int SYSZ_INS_NILF = 565; public static final int SYSZ_INS_NILH = 566; public static final int SYSZ_INS_NILL = 567; public static final int SYSZ_INS_NIY = 568; public static final int SYSZ_INS_NR = 569; public static final int SYSZ_INS_NRK = 570; public static final int SYSZ_INS_NY = 571; public static final int SYSZ_INS_O = 572; public static final int SYSZ_INS_OC = 573; public static final int SYSZ_INS_OG = 574; public static final int SYSZ_INS_OGR = 575; public static final int SYSZ_INS_OGRK = 576; public static final int SYSZ_INS_OI = 577; public static final int SYSZ_INS_OIHF = 578; public static final int SYSZ_INS_OIHH = 579; public static final int SYSZ_INS_OIHL = 580; public static final int SYSZ_INS_OILF = 581; public static final int SYSZ_INS_OILH = 582; public static final int SYSZ_INS_OILL = 583; public static final int SYSZ_INS_OIY = 584; public static final int SYSZ_INS_OR = 585; public static final int SYSZ_INS_ORK = 586; public static final int SYSZ_INS_OY = 587; public static final int SYSZ_INS_PFD = 588; public static final int SYSZ_INS_PFDRL = 589; public static final int SYSZ_INS_RISBG = 590; public static final int SYSZ_INS_RISBHG = 591; public static final int SYSZ_INS_RISBLG = 592; public static final int SYSZ_INS_RLL = 593; public static final int SYSZ_INS_RLLG = 594; public static final int SYSZ_INS_RNSBG = 595; public static final int SYSZ_INS_ROSBG = 596; public static final int SYSZ_INS_RXSBG = 597; public static final int SYSZ_INS_S = 598; public static final int SYSZ_INS_SDB = 599; public static final int SYSZ_INS_SDBR = 600; public static final int SYSZ_INS_SEB = 601; public static final int SYSZ_INS_SEBR = 602; public static final int SYSZ_INS_SG = 603; public static final int SYSZ_INS_SGF = 604; public static final int SYSZ_INS_SGFR = 605; public static final int SYSZ_INS_SGR = 606; public static final int SYSZ_INS_SGRK = 607; public static final int SYSZ_INS_SH = 608; public static final int SYSZ_INS_SHY = 609; public static final int SYSZ_INS_SL = 610; public static final int SYSZ_INS_SLB = 611; public static final int SYSZ_INS_SLBG = 612; public static final int SYSZ_INS_SLBR = 613; public static final int SYSZ_INS_SLFI = 614; public static final int SYSZ_INS_SLG = 615; public static final int SYSZ_INS_SLBGR = 616; public static final int SYSZ_INS_SLGF = 617; public static final int SYSZ_INS_SLGFI = 618; public static final int SYSZ_INS_SLGFR = 619; public static final int SYSZ_INS_SLGR = 620; public static final int SYSZ_INS_SLGRK = 621; public static final int SYSZ_INS_SLL = 622; public static final int SYSZ_INS_SLLG = 623; public static final int SYSZ_INS_SLLK = 624; public static final int SYSZ_INS_SLR = 625; public static final int SYSZ_INS_SLRK = 626; public static final int SYSZ_INS_SLY = 627; public static final int SYSZ_INS_SQDB = 628; public static final int SYSZ_INS_SQDBR = 629; public static final int SYSZ_INS_SQEB = 630; public static final int SYSZ_INS_SQEBR = 631; public static final int SYSZ_INS_SQXBR = 632; public static final int SYSZ_INS_SR = 633; public static final int SYSZ_INS_SRA = 634; public static final int SYSZ_INS_SRAG = 635; public static final int SYSZ_INS_SRAK = 636; public static final int SYSZ_INS_SRK = 637; public static final int SYSZ_INS_SRL = 638; public static final int SYSZ_INS_SRLG = 639; public static final int SYSZ_INS_SRLK = 640; public static final int SYSZ_INS_SRST = 641; public static final int SYSZ_INS_ST = 642; public static final int SYSZ_INS_STC = 643; public static final int SYSZ_INS_STCH = 644; public static final int SYSZ_INS_STCY = 645; public static final int SYSZ_INS_STD = 646; public static final int SYSZ_INS_STDY = 647; public static final int SYSZ_INS_STE = 648; public static final int SYSZ_INS_STEY = 649; public static final int SYSZ_INS_STFH = 650; public static final int SYSZ_INS_STG = 651; public static final int SYSZ_INS_STGRL = 652; public static final int SYSZ_INS_STH = 653; public static final int SYSZ_INS_STHH = 654; public static final int SYSZ_INS_STHRL = 655; public static final int SYSZ_INS_STHY = 656; public static final int SYSZ_INS_STMG = 657; public static final int SYSZ_INS_STRL = 658; public static final int SYSZ_INS_STRV = 659; public static final int SYSZ_INS_STRVG = 660; public static final int SYSZ_INS_STY = 661; public static final int SYSZ_INS_SXBR = 662; public static final int SYSZ_INS_SY = 663; public static final int SYSZ_INS_TM = 664; public static final int SYSZ_INS_TMHH = 665; public static final int SYSZ_INS_TMHL = 666; public static final int SYSZ_INS_TMLH = 667; public static final int SYSZ_INS_TMLL = 668; public static final int SYSZ_INS_TMY = 669; public static final int SYSZ_INS_X = 670; public static final int SYSZ_INS_XC = 671; public static final int SYSZ_INS_XG = 672; public static final int SYSZ_INS_XGR = 673; public static final int SYSZ_INS_XGRK = 674; public static final int SYSZ_INS_XI = 675; public static final int SYSZ_INS_XIHF = 676; public static final int SYSZ_INS_XILF = 677; public static final int SYSZ_INS_XIY = 678; public static final int SYSZ_INS_XR = 679; public static final int SYSZ_INS_XRK = 680; public static final int SYSZ_INS_XY = 681; public static final int SYSZ_INS_AD = 682; public static final int SYSZ_INS_ADR = 683; public static final int SYSZ_INS_ADTR = 684; public static final int SYSZ_INS_ADTRA = 685; public static final int SYSZ_INS_AE = 686; public static final int SYSZ_INS_AER = 687; public static final int SYSZ_INS_AGH = 688; public static final int SYSZ_INS_AHHHR = 689; public static final int SYSZ_INS_AHHLR = 690; public static final int SYSZ_INS_ALGSI = 691; public static final int SYSZ_INS_ALHHHR = 692; public static final int SYSZ_INS_ALHHLR = 693; public static final int SYSZ_INS_ALSI = 694; public static final int SYSZ_INS_ALSIH = 695; public static final int SYSZ_INS_ALSIHN = 696; public static final int SYSZ_INS_AP = 697; public static final int SYSZ_INS_AU = 698; public static final int SYSZ_INS_AUR = 699; public static final int SYSZ_INS_AW = 700; public static final int SYSZ_INS_AWR = 701; public static final int SYSZ_INS_AXR = 702; public static final int SYSZ_INS_AXTR = 703; public static final int SYSZ_INS_AXTRA = 704; public static final int SYSZ_INS_B = 705; public static final int SYSZ_INS_BAKR = 706; public static final int SYSZ_INS_BAL = 707; public static final int SYSZ_INS_BALR = 708; public static final int SYSZ_INS_BAS = 709; public static final int SYSZ_INS_BASSM = 710; public static final int SYSZ_INS_BC = 711; public static final int SYSZ_INS_BCT = 712; public static final int SYSZ_INS_BCTG = 713; public static final int SYSZ_INS_BCTGR = 714; public static final int SYSZ_INS_BCTR = 715; public static final int SYSZ_INS_BE = 716; public static final int SYSZ_INS_BH = 717; public static final int SYSZ_INS_BHE = 718; public static final int SYSZ_INS_BI = 719; public static final int SYSZ_INS_BIC = 720; public static final int SYSZ_INS_BIE = 721; public static final int SYSZ_INS_BIH = 722; public static final int SYSZ_INS_BIHE = 723; public static final int SYSZ_INS_BIL = 724; public static final int SYSZ_INS_BILE = 725; public static final int SYSZ_INS_BILH = 726; public static final int SYSZ_INS_BIM = 727; public static final int SYSZ_INS_BINE = 728; public static final int SYSZ_INS_BINH = 729; public static final int SYSZ_INS_BINHE = 730; public static final int SYSZ_INS_BINL = 731; public static final int SYSZ_INS_BINLE = 732; public static final int SYSZ_INS_BINLH = 733; public static final int SYSZ_INS_BINM = 734; public static final int SYSZ_INS_BINO = 735; public static final int SYSZ_INS_BINP = 736; public static final int SYSZ_INS_BINZ = 737; public static final int SYSZ_INS_BIO = 738; public static final int SYSZ_INS_BIP = 739; public static final int SYSZ_INS_BIZ = 740; public static final int SYSZ_INS_BL = 741; public static final int SYSZ_INS_BLE = 742; public static final int SYSZ_INS_BLH = 743; public static final int SYSZ_INS_BM = 744; public static final int SYSZ_INS_BMR = 745; public static final int SYSZ_INS_BNE = 746; public static final int SYSZ_INS_BNH = 747; public static final int SYSZ_INS_BNHE = 748; public static final int SYSZ_INS_BNL = 749; public static final int SYSZ_INS_BNLE = 750; public static final int SYSZ_INS_BNLH = 751; public static final int SYSZ_INS_BNM = 752; public static final int SYSZ_INS_BNMR = 753; public static final int SYSZ_INS_BNO = 754; public static final int SYSZ_INS_BNP = 755; public static final int SYSZ_INS_BNPR = 756; public static final int SYSZ_INS_BNZ = 757; public static final int SYSZ_INS_BNZR = 758; public static final int SYSZ_INS_BO = 759; public static final int SYSZ_INS_BP = 760; public static final int SYSZ_INS_BPP = 761; public static final int SYSZ_INS_BPR = 762; public static final int SYSZ_INS_BPRP = 763; public static final int SYSZ_INS_BRCTH = 764; public static final int SYSZ_INS_BRXH = 765; public static final int SYSZ_INS_BRXHG = 766; public static final int SYSZ_INS_BRXLE = 767; public static final int SYSZ_INS_BRXLG = 768; public static final int SYSZ_INS_BSA = 769; public static final int SYSZ_INS_BSG = 770; public static final int SYSZ_INS_BSM = 771; public static final int SYSZ_INS_BXH = 772; public static final int SYSZ_INS_BXHG = 773; public static final int SYSZ_INS_BXLE = 774; public static final int SYSZ_INS_BXLEG = 775; public static final int SYSZ_INS_BZ = 776; public static final int SYSZ_INS_BZR = 777; public static final int SYSZ_INS_CD = 778; public static final int SYSZ_INS_CDFBRA = 779; public static final int SYSZ_INS_CDFR = 780; public static final int SYSZ_INS_CDFTR = 781; public static final int SYSZ_INS_CDGBRA = 782; public static final int SYSZ_INS_CDGR = 783; public static final int SYSZ_INS_CDGTR = 784; public static final int SYSZ_INS_CDGTRA = 785; public static final int SYSZ_INS_CDLFTR = 786; public static final int SYSZ_INS_CDLGTR = 787; public static final int SYSZ_INS_CDPT = 788; public static final int SYSZ_INS_CDR = 789; public static final int SYSZ_INS_CDS = 790; public static final int SYSZ_INS_CDSG = 791; public static final int SYSZ_INS_CDSTR = 792; public static final int SYSZ_INS_CDSY = 793; public static final int SYSZ_INS_CDTR = 794; public static final int SYSZ_INS_CDUTR = 795; public static final int SYSZ_INS_CDZT = 796; public static final int SYSZ_INS_CE = 797; public static final int SYSZ_INS_CEDTR = 798; public static final int SYSZ_INS_CEFBRA = 799; public static final int SYSZ_INS_CEFR = 800; public static final int SYSZ_INS_CEGBRA = 801; public static final int SYSZ_INS_CEGR = 802; public static final int SYSZ_INS_CER = 803; public static final int SYSZ_INS_CEXTR = 804; public static final int SYSZ_INS_CFC = 805; public static final int SYSZ_INS_CFDBRA = 806; public static final int SYSZ_INS_CFDR = 807; public static final int SYSZ_INS_CFDTR = 808; public static final int SYSZ_INS_CFEBRA = 809; public static final int SYSZ_INS_CFER = 810; public static final int SYSZ_INS_CFXBRA = 811; public static final int SYSZ_INS_CFXR = 812; public static final int SYSZ_INS_CFXTR = 813; public static final int SYSZ_INS_CGDBRA = 814; public static final int SYSZ_INS_CGDR = 815; public static final int SYSZ_INS_CGDTR = 816; public static final int SYSZ_INS_CGDTRA = 817; public static final int SYSZ_INS_CGEBRA = 818; public static final int SYSZ_INS_CGER = 819; public static final int SYSZ_INS_CGIB = 820; public static final int SYSZ_INS_CGIBE = 821; public static final int SYSZ_INS_CGIBH = 822; public static final int SYSZ_INS_CGIBHE = 823; public static final int SYSZ_INS_CGIBL = 824; public static final int SYSZ_INS_CGIBLE = 825; public static final int SYSZ_INS_CGIBLH = 826; public static final int SYSZ_INS_CGIBNE = 827; public static final int SYSZ_INS_CGIBNH = 828; public static final int SYSZ_INS_CGIBNHE = 829; public static final int SYSZ_INS_CGIBNL = 830; public static final int SYSZ_INS_CGIBNLE = 831; public static final int SYSZ_INS_CGIBNLH = 832; public static final int SYSZ_INS_CGIT = 833; public static final int SYSZ_INS_CGITE = 834; public static final int SYSZ_INS_CGITH = 835; public static final int SYSZ_INS_CGITHE = 836; public static final int SYSZ_INS_CGITL = 837; public static final int SYSZ_INS_CGITLE = 838; public static final int SYSZ_INS_CGITLH = 839; public static final int SYSZ_INS_CGITNE = 840; public static final int SYSZ_INS_CGITNH = 841; public static final int SYSZ_INS_CGITNHE = 842; public static final int SYSZ_INS_CGITNL = 843; public static final int SYSZ_INS_CGITNLE = 844; public static final int SYSZ_INS_CGITNLH = 845; public static final int SYSZ_INS_CGRB = 846; public static final int SYSZ_INS_CGRBE = 847; public static final int SYSZ_INS_CGRBH = 848; public static final int SYSZ_INS_CGRBHE = 849; public static final int SYSZ_INS_CGRBL = 850; public static final int SYSZ_INS_CGRBLE = 851; public static final int SYSZ_INS_CGRBLH = 852; public static final int SYSZ_INS_CGRBNE = 853; public static final int SYSZ_INS_CGRBNH = 854; public static final int SYSZ_INS_CGRBNHE = 855; public static final int SYSZ_INS_CGRBNL = 856; public static final int SYSZ_INS_CGRBNLE = 857; public static final int SYSZ_INS_CGRBNLH = 858; public static final int SYSZ_INS_CGRT = 859; public static final int SYSZ_INS_CGRTE = 860; public static final int SYSZ_INS_CGRTH = 861; public static final int SYSZ_INS_CGRTHE = 862; public static final int SYSZ_INS_CGRTL = 863; public static final int SYSZ_INS_CGRTLE = 864; public static final int SYSZ_INS_CGRTLH = 865; public static final int SYSZ_INS_CGRTNE = 866; public static final int SYSZ_INS_CGRTNH = 867; public static final int SYSZ_INS_CGRTNHE = 868; public static final int SYSZ_INS_CGRTNL = 869; public static final int SYSZ_INS_CGRTNLE = 870; public static final int SYSZ_INS_CGRTNLH = 871; public static final int SYSZ_INS_CGXBRA = 872; public static final int SYSZ_INS_CGXR = 873; public static final int SYSZ_INS_CGXTR = 874; public static final int SYSZ_INS_CGXTRA = 875; public static final int SYSZ_INS_CHHR = 876; public static final int SYSZ_INS_CHLR = 877; public static final int SYSZ_INS_CIB = 878; public static final int SYSZ_INS_CIBE = 879; public static final int SYSZ_INS_CIBH = 880; public static final int SYSZ_INS_CIBHE = 881; public static final int SYSZ_INS_CIBL = 882; public static final int SYSZ_INS_CIBLE = 883; public static final int SYSZ_INS_CIBLH = 884; public static final int SYSZ_INS_CIBNE = 885; public static final int SYSZ_INS_CIBNH = 886; public static final int SYSZ_INS_CIBNHE = 887; public static final int SYSZ_INS_CIBNL = 888; public static final int SYSZ_INS_CIBNLE = 889; public static final int SYSZ_INS_CIBNLH = 890; public static final int SYSZ_INS_CIT = 891; public static final int SYSZ_INS_CITE = 892; public static final int SYSZ_INS_CITH = 893; public static final int SYSZ_INS_CITHE = 894; public static final int SYSZ_INS_CITL = 895; public static final int SYSZ_INS_CITLE = 896; public static final int SYSZ_INS_CITLH = 897; public static final int SYSZ_INS_CITNE = 898; public static final int SYSZ_INS_CITNH = 899; public static final int SYSZ_INS_CITNHE = 900; public static final int SYSZ_INS_CITNL = 901; public static final int SYSZ_INS_CITNLE = 902; public static final int SYSZ_INS_CITNLH = 903; public static final int SYSZ_INS_CKSM = 904; public static final int SYSZ_INS_CLCL = 905; public static final int SYSZ_INS_CLCLE = 906; public static final int SYSZ_INS_CLCLU = 907; public static final int SYSZ_INS_CLFDTR = 908; public static final int SYSZ_INS_CLFIT = 909; public static final int SYSZ_INS_CLFITE = 910; public static final int SYSZ_INS_CLFITH = 911; public static final int SYSZ_INS_CLFITHE = 912; public static final int SYSZ_INS_CLFITL = 913; public static final int SYSZ_INS_CLFITLE = 914; public static final int SYSZ_INS_CLFITLH = 915; public static final int SYSZ_INS_CLFITNE = 916; public static final int SYSZ_INS_CLFITNH = 917; public static final int SYSZ_INS_CLFITNHE = 918; public static final int SYSZ_INS_CLFITNL = 919; public static final int SYSZ_INS_CLFITNLE = 920; public static final int SYSZ_INS_CLFITNLH = 921; public static final int SYSZ_INS_CLFXTR = 922; public static final int SYSZ_INS_CLGDTR = 923; public static final int SYSZ_INS_CLGIB = 924; public static final int SYSZ_INS_CLGIBE = 925; public static final int SYSZ_INS_CLGIBH = 926; public static final int SYSZ_INS_CLGIBHE = 927; public static final int SYSZ_INS_CLGIBL = 928; public static final int SYSZ_INS_CLGIBLE = 929; public static final int SYSZ_INS_CLGIBLH = 930; public static final int SYSZ_INS_CLGIBNE = 931; public static final int SYSZ_INS_CLGIBNH = 932; public static final int SYSZ_INS_CLGIBNHE = 933; public static final int SYSZ_INS_CLGIBNL = 934; public static final int SYSZ_INS_CLGIBNLE = 935; public static final int SYSZ_INS_CLGIBNLH = 936; public static final int SYSZ_INS_CLGIT = 937; public static final int SYSZ_INS_CLGITE = 938; public static final int SYSZ_INS_CLGITH = 939; public static final int SYSZ_INS_CLGITHE = 940; public static final int SYSZ_INS_CLGITL = 941; public static final int SYSZ_INS_CLGITLE = 942; public static final int SYSZ_INS_CLGITLH = 943; public static final int SYSZ_INS_CLGITNE = 944; public static final int SYSZ_INS_CLGITNH = 945; public static final int SYSZ_INS_CLGITNHE = 946; public static final int SYSZ_INS_CLGITNL = 947; public static final int SYSZ_INS_CLGITNLE = 948; public static final int SYSZ_INS_CLGITNLH = 949; public static final int SYSZ_INS_CLGRB = 950; public static final int SYSZ_INS_CLGRBE = 951; public static final int SYSZ_INS_CLGRBH = 952; public static final int SYSZ_INS_CLGRBHE = 953; public static final int SYSZ_INS_CLGRBL = 954; public static final int SYSZ_INS_CLGRBLE = 955; public static final int SYSZ_INS_CLGRBLH = 956; public static final int SYSZ_INS_CLGRBNE = 957; public static final int SYSZ_INS_CLGRBNH = 958; public static final int SYSZ_INS_CLGRBNHE = 959; public static final int SYSZ_INS_CLGRBNL = 960; public static final int SYSZ_INS_CLGRBNLE = 961; public static final int SYSZ_INS_CLGRBNLH = 962; public static final int SYSZ_INS_CLGRT = 963; public static final int SYSZ_INS_CLGRTE = 964; public static final int SYSZ_INS_CLGRTH = 965; public static final int SYSZ_INS_CLGRTHE = 966; public static final int SYSZ_INS_CLGRTL = 967; public static final int SYSZ_INS_CLGRTLE = 968; public static final int SYSZ_INS_CLGRTLH = 969; public static final int SYSZ_INS_CLGRTNE = 970; public static final int SYSZ_INS_CLGRTNH = 971; public static final int SYSZ_INS_CLGRTNHE = 972; public static final int SYSZ_INS_CLGRTNL = 973; public static final int SYSZ_INS_CLGRTNLE = 974; public static final int SYSZ_INS_CLGRTNLH = 975; public static final int SYSZ_INS_CLGT = 976; public static final int SYSZ_INS_CLGTE = 977; public static final int SYSZ_INS_CLGTH = 978; public static final int SYSZ_INS_CLGTHE = 979; public static final int SYSZ_INS_CLGTL = 980; public static final int SYSZ_INS_CLGTLE = 981; public static final int SYSZ_INS_CLGTLH = 982; public static final int SYSZ_INS_CLGTNE = 983; public static final int SYSZ_INS_CLGTNH = 984; public static final int SYSZ_INS_CLGTNHE = 985; public static final int SYSZ_INS_CLGTNL = 986; public static final int SYSZ_INS_CLGTNLE = 987; public static final int SYSZ_INS_CLGTNLH = 988; public static final int SYSZ_INS_CLGXTR = 989; public static final int SYSZ_INS_CLHHR = 990; public static final int SYSZ_INS_CLHLR = 991; public static final int SYSZ_INS_CLIB = 992; public static final int SYSZ_INS_CLIBE = 993; public static final int SYSZ_INS_CLIBH = 994; public static final int SYSZ_INS_CLIBHE = 995; public static final int SYSZ_INS_CLIBL = 996; public static final int SYSZ_INS_CLIBLE = 997; public static final int SYSZ_INS_CLIBLH = 998; public static final int SYSZ_INS_CLIBNE = 999; public static final int SYSZ_INS_CLIBNH = 1000; public static final int SYSZ_INS_CLIBNHE = 1001; public static final int SYSZ_INS_CLIBNL = 1002; public static final int SYSZ_INS_CLIBNLE = 1003; public static final int SYSZ_INS_CLIBNLH = 1004; public static final int SYSZ_INS_CLM = 1005; public static final int SYSZ_INS_CLMH = 1006; public static final int SYSZ_INS_CLMY = 1007; public static final int SYSZ_INS_CLRB = 1008; public static final int SYSZ_INS_CLRBE = 1009; public static final int SYSZ_INS_CLRBH = 1010; public static final int SYSZ_INS_CLRBHE = 1011; public static final int SYSZ_INS_CLRBL = 1012; public static final int SYSZ_INS_CLRBLE = 1013; public static final int SYSZ_INS_CLRBLH = 1014; public static final int SYSZ_INS_CLRBNE = 1015; public static final int SYSZ_INS_CLRBNH = 1016; public static final int SYSZ_INS_CLRBNHE = 1017; public static final int SYSZ_INS_CLRBNL = 1018; public static final int SYSZ_INS_CLRBNLE = 1019; public static final int SYSZ_INS_CLRBNLH = 1020; public static final int SYSZ_INS_CLRT = 1021; public static final int SYSZ_INS_CLRTE = 1022; public static final int SYSZ_INS_CLRTH = 1023; public static final int SYSZ_INS_CLRTHE = 1024; public static final int SYSZ_INS_CLRTL = 1025; public static final int SYSZ_INS_CLRTLE = 1026; public static final int SYSZ_INS_CLRTLH = 1027; public static final int SYSZ_INS_CLRTNE = 1028; public static final int SYSZ_INS_CLRTNH = 1029; public static final int SYSZ_INS_CLRTNHE = 1030; public static final int SYSZ_INS_CLRTNL = 1031; public static final int SYSZ_INS_CLRTNLE = 1032; public static final int SYSZ_INS_CLRTNLH = 1033; public static final int SYSZ_INS_CLT = 1034; public static final int SYSZ_INS_CLTE = 1035; public static final int SYSZ_INS_CLTH = 1036; public static final int SYSZ_INS_CLTHE = 1037; public static final int SYSZ_INS_CLTL = 1038; public static final int SYSZ_INS_CLTLE = 1039; public static final int SYSZ_INS_CLTLH = 1040; public static final int SYSZ_INS_CLTNE = 1041; public static final int SYSZ_INS_CLTNH = 1042; public static final int SYSZ_INS_CLTNHE = 1043; public static final int SYSZ_INS_CLTNL = 1044; public static final int SYSZ_INS_CLTNLE = 1045; public static final int SYSZ_INS_CLTNLH = 1046; public static final int SYSZ_INS_CMPSC = 1047; public static final int SYSZ_INS_CP = 1048; public static final int SYSZ_INS_CPDT = 1049; public static final int SYSZ_INS_CPXT = 1050; public static final int SYSZ_INS_CPYA = 1051; public static final int SYSZ_INS_CRB = 1052; public static final int SYSZ_INS_CRBE = 1053; public static final int SYSZ_INS_CRBH = 1054; public static final int SYSZ_INS_CRBHE = 1055; public static final int SYSZ_INS_CRBL = 1056; public static final int SYSZ_INS_CRBLE = 1057; public static final int SYSZ_INS_CRBLH = 1058; public static final int SYSZ_INS_CRBNE = 1059; public static final int SYSZ_INS_CRBNH = 1060; public static final int SYSZ_INS_CRBNHE = 1061; public static final int SYSZ_INS_CRBNL = 1062; public static final int SYSZ_INS_CRBNLE = 1063; public static final int SYSZ_INS_CRBNLH = 1064; public static final int SYSZ_INS_CRDTE = 1065; public static final int SYSZ_INS_CRT = 1066; public static final int SYSZ_INS_CRTE = 1067; public static final int SYSZ_INS_CRTH = 1068; public static final int SYSZ_INS_CRTHE = 1069; public static final int SYSZ_INS_CRTL = 1070; public static final int SYSZ_INS_CRTLE = 1071; public static final int SYSZ_INS_CRTLH = 1072; public static final int SYSZ_INS_CRTNE = 1073; public static final int SYSZ_INS_CRTNH = 1074; public static final int SYSZ_INS_CRTNHE = 1075; public static final int SYSZ_INS_CRTNL = 1076; public static final int SYSZ_INS_CRTNLE = 1077; public static final int SYSZ_INS_CRTNLH = 1078; public static final int SYSZ_INS_CSCH = 1079; public static final int SYSZ_INS_CSDTR = 1080; public static final int SYSZ_INS_CSP = 1081; public static final int SYSZ_INS_CSPG = 1082; public static final int SYSZ_INS_CSST = 1083; public static final int SYSZ_INS_CSXTR = 1084; public static final int SYSZ_INS_CU12 = 1085; public static final int SYSZ_INS_CU14 = 1086; public static final int SYSZ_INS_CU21 = 1087; public static final int SYSZ_INS_CU24 = 1088; public static final int SYSZ_INS_CU41 = 1089; public static final int SYSZ_INS_CU42 = 1090; public static final int SYSZ_INS_CUDTR = 1091; public static final int SYSZ_INS_CUSE = 1092; public static final int SYSZ_INS_CUTFU = 1093; public static final int SYSZ_INS_CUUTF = 1094; public static final int SYSZ_INS_CUXTR = 1095; public static final int SYSZ_INS_CVB = 1096; public static final int SYSZ_INS_CVBG = 1097; public static final int SYSZ_INS_CVBY = 1098; public static final int SYSZ_INS_CVD = 1099; public static final int SYSZ_INS_CVDG = 1100; public static final int SYSZ_INS_CVDY = 1101; public static final int SYSZ_INS_CXFBRA = 1102; public static final int SYSZ_INS_CXFR = 1103; public static final int SYSZ_INS_CXFTR = 1104; public static final int SYSZ_INS_CXGBRA = 1105; public static final int SYSZ_INS_CXGR = 1106; public static final int SYSZ_INS_CXGTR = 1107; public static final int SYSZ_INS_CXGTRA = 1108; public static final int SYSZ_INS_CXLFTR = 1109; public static final int SYSZ_INS_CXLGTR = 1110; public static final int SYSZ_INS_CXPT = 1111; public static final int SYSZ_INS_CXR = 1112; public static final int SYSZ_INS_CXSTR = 1113; public static final int SYSZ_INS_CXTR = 1114; public static final int SYSZ_INS_CXUTR = 1115; public static final int SYSZ_INS_CXZT = 1116; public static final int SYSZ_INS_CZDT = 1117; public static final int SYSZ_INS_CZXT = 1118; public static final int SYSZ_INS_D = 1119; public static final int SYSZ_INS_DD = 1120; public static final int SYSZ_INS_DDR = 1121; public static final int SYSZ_INS_DDTR = 1122; public static final int SYSZ_INS_DDTRA = 1123; public static final int SYSZ_INS_DE = 1124; public static final int SYSZ_INS_DER = 1125; public static final int SYSZ_INS_DIAG = 1126; public static final int SYSZ_INS_DIDBR = 1127; public static final int SYSZ_INS_DIEBR = 1128; public static final int SYSZ_INS_DP = 1129; public static final int SYSZ_INS_DR = 1130; public static final int SYSZ_INS_DXR = 1131; public static final int SYSZ_INS_DXTR = 1132; public static final int SYSZ_INS_DXTRA = 1133; public static final int SYSZ_INS_ECAG = 1134; public static final int SYSZ_INS_ECCTR = 1135; public static final int SYSZ_INS_ECPGA = 1136; public static final int SYSZ_INS_ECTG = 1137; public static final int SYSZ_INS_ED = 1138; public static final int SYSZ_INS_EDMK = 1139; public static final int SYSZ_INS_EEDTR = 1140; public static final int SYSZ_INS_EEXTR = 1141; public static final int SYSZ_INS_EFPC = 1142; public static final int SYSZ_INS_EPAIR = 1143; public static final int SYSZ_INS_EPAR = 1144; public static final int SYSZ_INS_EPCTR = 1145; public static final int SYSZ_INS_EPSW = 1146; public static final int SYSZ_INS_EREG = 1147; public static final int SYSZ_INS_EREGG = 1148; public static final int SYSZ_INS_ESAIR = 1149; public static final int SYSZ_INS_ESAR = 1150; public static final int SYSZ_INS_ESDTR = 1151; public static final int SYSZ_INS_ESEA = 1152; public static final int SYSZ_INS_ESTA = 1153; public static final int SYSZ_INS_ESXTR = 1154; public static final int SYSZ_INS_ETND = 1155; public static final int SYSZ_INS_EX = 1156; public static final int SYSZ_INS_EXRL = 1157; public static final int SYSZ_INS_FIDR = 1158; public static final int SYSZ_INS_FIDTR = 1159; public static final int SYSZ_INS_FIER = 1160; public static final int SYSZ_INS_FIXR = 1161; public static final int SYSZ_INS_FIXTR = 1162; public static final int SYSZ_INS_HDR = 1163; public static final int SYSZ_INS_HER = 1164; public static final int SYSZ_INS_HSCH = 1165; public static final int SYSZ_INS_IAC = 1166; public static final int SYSZ_INS_ICM = 1167; public static final int SYSZ_INS_ICMH = 1168; public static final int SYSZ_INS_ICMY = 1169; public static final int SYSZ_INS_IDTE = 1170; public static final int SYSZ_INS_IEDTR = 1171; public static final int SYSZ_INS_IEXTR = 1172; public static final int SYSZ_INS_IPK = 1173; public static final int SYSZ_INS_IPTE = 1174; public static final int SYSZ_INS_IRBM = 1175; public static final int SYSZ_INS_ISKE = 1176; public static final int SYSZ_INS_IVSK = 1177; public static final int SYSZ_INS_JGM = 1178; public static final int SYSZ_INS_JGNM = 1179; public static final int SYSZ_INS_JGNP = 1180; public static final int SYSZ_INS_JGNZ = 1181; public static final int SYSZ_INS_JGP = 1182; public static final int SYSZ_INS_JGZ = 1183; public static final int SYSZ_INS_JM = 1184; public static final int SYSZ_INS_JNM = 1185; public static final int SYSZ_INS_JNP = 1186; public static final int SYSZ_INS_JNZ = 1187; public static final int SYSZ_INS_JP = 1188; public static final int SYSZ_INS_JZ = 1189; public static final int SYSZ_INS_KDB = 1190; public static final int SYSZ_INS_KDBR = 1191; public static final int SYSZ_INS_KDTR = 1192; public static final int SYSZ_INS_KEB = 1193; public static final int SYSZ_INS_KEBR = 1194; public static final int SYSZ_INS_KIMD = 1195; public static final int SYSZ_INS_KLMD = 1196; public static final int SYSZ_INS_KM = 1197; public static final int SYSZ_INS_KMA = 1198; public static final int SYSZ_INS_KMAC = 1199; public static final int SYSZ_INS_KMC = 1200; public static final int SYSZ_INS_KMCTR = 1201; public static final int SYSZ_INS_KMF = 1202; public static final int SYSZ_INS_KMO = 1203; public static final int SYSZ_INS_KXBR = 1204; public static final int SYSZ_INS_KXTR = 1205; public static final int SYSZ_INS_LAE = 1206; public static final int SYSZ_INS_LAEY = 1207; public static final int SYSZ_INS_LAM = 1208; public static final int SYSZ_INS_LAMY = 1209; public static final int SYSZ_INS_LASP = 1210; public static final int SYSZ_INS_LAT = 1211; public static final int SYSZ_INS_LCBB = 1212; public static final int SYSZ_INS_LCCTL = 1213; public static final int SYSZ_INS_LCDFR = 1214; public static final int SYSZ_INS_LCDR = 1215; public static final int SYSZ_INS_LCER = 1216; public static final int SYSZ_INS_LCTL = 1217; public static final int SYSZ_INS_LCTLG = 1218; public static final int SYSZ_INS_LCXR = 1219; public static final int SYSZ_INS_LDE = 1220; public static final int SYSZ_INS_LDER = 1221; public static final int SYSZ_INS_LDETR = 1222; public static final int SYSZ_INS_LDXR = 1223; public static final int SYSZ_INS_LDXTR = 1224; public static final int SYSZ_INS_LEDR = 1225; public static final int SYSZ_INS_LEDTR = 1226; public static final int SYSZ_INS_LEXR = 1227; public static final int SYSZ_INS_LFAS = 1228; public static final int SYSZ_INS_LFHAT = 1229; public static final int SYSZ_INS_LFPC = 1230; public static final int SYSZ_INS_LGAT = 1231; public static final int SYSZ_INS_LGG = 1232; public static final int SYSZ_INS_LGSC = 1233; public static final int SYSZ_INS_LLGFAT = 1234; public static final int SYSZ_INS_LLGFSG = 1235; public static final int SYSZ_INS_LLGT = 1236; public static final int SYSZ_INS_LLGTAT = 1237; public static final int SYSZ_INS_LLGTR = 1238; public static final int SYSZ_INS_LLZRGF = 1239; public static final int SYSZ_INS_LM = 1240; public static final int SYSZ_INS_LMD = 1241; public static final int SYSZ_INS_LMH = 1242; public static final int SYSZ_INS_LMY = 1243; public static final int SYSZ_INS_LNDFR = 1244; public static final int SYSZ_INS_LNDR = 1245; public static final int SYSZ_INS_LNER = 1246; public static final int SYSZ_INS_LNXR = 1247; public static final int SYSZ_INS_LOCFH = 1248; public static final int SYSZ_INS_LOCFHE = 1249; public static final int SYSZ_INS_LOCFHH = 1250; public static final int SYSZ_INS_LOCFHHE = 1251; public static final int SYSZ_INS_LOCFHL = 1252; public static final int SYSZ_INS_LOCFHLE = 1253; public static final int SYSZ_INS_LOCFHLH = 1254; public static final int SYSZ_INS_LOCFHM = 1255; public static final int SYSZ_INS_LOCFHNE = 1256; public static final int SYSZ_INS_LOCFHNH = 1257; public static final int SYSZ_INS_LOCFHNHE = 1258; public static final int SYSZ_INS_LOCFHNL = 1259; public static final int SYSZ_INS_LOCFHNLE = 1260; public static final int SYSZ_INS_LOCFHNLH = 1261; public static final int SYSZ_INS_LOCFHNM = 1262; public static final int SYSZ_INS_LOCFHNO = 1263; public static final int SYSZ_INS_LOCFHNP = 1264; public static final int SYSZ_INS_LOCFHNZ = 1265; public static final int SYSZ_INS_LOCFHO = 1266; public static final int SYSZ_INS_LOCFHP = 1267; public static final int SYSZ_INS_LOCFHR = 1268; public static final int SYSZ_INS_LOCFHRE = 1269; public static final int SYSZ_INS_LOCFHRH = 1270; public static final int SYSZ_INS_LOCFHRHE = 1271; public static final int SYSZ_INS_LOCFHRL = 1272; public static final int SYSZ_INS_LOCFHRLE = 1273; public static final int SYSZ_INS_LOCFHRLH = 1274; public static final int SYSZ_INS_LOCFHRM = 1275; public static final int SYSZ_INS_LOCFHRNE = 1276; public static final int SYSZ_INS_LOCFHRNH = 1277; public static final int SYSZ_INS_LOCFHRNHE = 1278; public static final int SYSZ_INS_LOCFHRNL = 1279; public static final int SYSZ_INS_LOCFHRNLE = 1280; public static final int SYSZ_INS_LOCFHRNLH = 1281; public static final int SYSZ_INS_LOCFHRNM = 1282; public static final int SYSZ_INS_LOCFHRNO = 1283; public static final int SYSZ_INS_LOCFHRNP = 1284; public static final int SYSZ_INS_LOCFHRNZ = 1285; public static final int SYSZ_INS_LOCFHRO = 1286; public static final int SYSZ_INS_LOCFHRP = 1287; public static final int SYSZ_INS_LOCFHRZ = 1288; public static final int SYSZ_INS_LOCFHZ = 1289; public static final int SYSZ_INS_LOCGHI = 1290; public static final int SYSZ_INS_LOCGHIE = 1291; public static final int SYSZ_INS_LOCGHIH = 1292; public static final int SYSZ_INS_LOCGHIHE = 1293; public static final int SYSZ_INS_LOCGHIL = 1294; public static final int SYSZ_INS_LOCGHILE = 1295; public static final int SYSZ_INS_LOCGHILH = 1296; public static final int SYSZ_INS_LOCGHIM = 1297; public static final int SYSZ_INS_LOCGHINE = 1298; public static final int SYSZ_INS_LOCGHINH = 1299; public static final int SYSZ_INS_LOCGHINHE = 1300; public static final int SYSZ_INS_LOCGHINL = 1301; public static final int SYSZ_INS_LOCGHINLE = 1302; public static final int SYSZ_INS_LOCGHINLH = 1303; public static final int SYSZ_INS_LOCGHINM = 1304; public static final int SYSZ_INS_LOCGHINO = 1305; public static final int SYSZ_INS_LOCGHINP = 1306; public static final int SYSZ_INS_LOCGHINZ = 1307; public static final int SYSZ_INS_LOCGHIO = 1308; public static final int SYSZ_INS_LOCGHIP = 1309; public static final int SYSZ_INS_LOCGHIZ = 1310; public static final int SYSZ_INS_LOCGM = 1311; public static final int SYSZ_INS_LOCGNM = 1312; public static final int SYSZ_INS_LOCGNP = 1313; public static final int SYSZ_INS_LOCGNZ = 1314; public static final int SYSZ_INS_LOCGP = 1315; public static final int SYSZ_INS_LOCGRM = 1316; public static final int SYSZ_INS_LOCGRNM = 1317; public static final int SYSZ_INS_LOCGRNP = 1318; public static final int SYSZ_INS_LOCGRNZ = 1319; public static final int SYSZ_INS_LOCGRP = 1320; public static final int SYSZ_INS_LOCGRZ = 1321; public static final int SYSZ_INS_LOCGZ = 1322; public static final int SYSZ_INS_LOCHHI = 1323; public static final int SYSZ_INS_LOCHHIE = 1324; public static final int SYSZ_INS_LOCHHIH = 1325; public static final int SYSZ_INS_LOCHHIHE = 1326; public static final int SYSZ_INS_LOCHHIL = 1327; public static final int SYSZ_INS_LOCHHILE = 1328; public static final int SYSZ_INS_LOCHHILH = 1329; public static final int SYSZ_INS_LOCHHIM = 1330; public static final int SYSZ_INS_LOCHHINE = 1331; public static final int SYSZ_INS_LOCHHINH = 1332; public static final int SYSZ_INS_LOCHHINHE = 1333; public static final int SYSZ_INS_LOCHHINL = 1334; public static final int SYSZ_INS_LOCHHINLE = 1335; public static final int SYSZ_INS_LOCHHINLH = 1336; public static final int SYSZ_INS_LOCHHINM = 1337; public static final int SYSZ_INS_LOCHHINO = 1338; public static final int SYSZ_INS_LOCHHINP = 1339; public static final int SYSZ_INS_LOCHHINZ = 1340; public static final int SYSZ_INS_LOCHHIO = 1341; public static final int SYSZ_INS_LOCHHIP = 1342; public static final int SYSZ_INS_LOCHHIZ = 1343; public static final int SYSZ_INS_LOCHI = 1344; public static final int SYSZ_INS_LOCHIE = 1345; public static final int SYSZ_INS_LOCHIH = 1346; public static final int SYSZ_INS_LOCHIHE = 1347; public static final int SYSZ_INS_LOCHIL = 1348; public static final int SYSZ_INS_LOCHILE = 1349; public static final int SYSZ_INS_LOCHILH = 1350; public static final int SYSZ_INS_LOCHIM = 1351; public static final int SYSZ_INS_LOCHINE = 1352; public static final int SYSZ_INS_LOCHINH = 1353; public static final int SYSZ_INS_LOCHINHE = 1354; public static final int SYSZ_INS_LOCHINL = 1355; public static final int SYSZ_INS_LOCHINLE = 1356; public static final int SYSZ_INS_LOCHINLH = 1357; public static final int SYSZ_INS_LOCHINM = 1358; public static final int SYSZ_INS_LOCHINO = 1359; public static final int SYSZ_INS_LOCHINP = 1360; public static final int SYSZ_INS_LOCHINZ = 1361; public static final int SYSZ_INS_LOCHIO = 1362; public static final int SYSZ_INS_LOCHIP = 1363; public static final int SYSZ_INS_LOCHIZ = 1364; public static final int SYSZ_INS_LOCM = 1365; public static final int SYSZ_INS_LOCNM = 1366; public static final int SYSZ_INS_LOCNP = 1367; public static final int SYSZ_INS_LOCNZ = 1368; public static final int SYSZ_INS_LOCP = 1369; public static final int SYSZ_INS_LOCRM = 1370; public static final int SYSZ_INS_LOCRNM = 1371; public static final int SYSZ_INS_LOCRNP = 1372; public static final int SYSZ_INS_LOCRNZ = 1373; public static final int SYSZ_INS_LOCRP = 1374; public static final int SYSZ_INS_LOCRZ = 1375; public static final int SYSZ_INS_LOCZ = 1376; public static final int SYSZ_INS_LPCTL = 1377; public static final int SYSZ_INS_LPD = 1378; public static final int SYSZ_INS_LPDFR = 1379; public static final int SYSZ_INS_LPDG = 1380; public static final int SYSZ_INS_LPDR = 1381; public static final int SYSZ_INS_LPER = 1382; public static final int SYSZ_INS_LPP = 1383; public static final int SYSZ_INS_LPQ = 1384; public static final int SYSZ_INS_LPSW = 1385; public static final int SYSZ_INS_LPSWE = 1386; public static final int SYSZ_INS_LPTEA = 1387; public static final int SYSZ_INS_LPXR = 1388; public static final int SYSZ_INS_LRA = 1389; public static final int SYSZ_INS_LRAG = 1390; public static final int SYSZ_INS_LRAY = 1391; public static final int SYSZ_INS_LRDR = 1392; public static final int SYSZ_INS_LRER = 1393; public static final int SYSZ_INS_LRVH = 1394; public static final int SYSZ_INS_LSCTL = 1395; public static final int SYSZ_INS_LTDR = 1396; public static final int SYSZ_INS_LTDTR = 1397; public static final int SYSZ_INS_LTER = 1398; public static final int SYSZ_INS_LTXR = 1399; public static final int SYSZ_INS_LTXTR = 1400; public static final int SYSZ_INS_LURA = 1401; public static final int SYSZ_INS_LURAG = 1402; public static final int SYSZ_INS_LXD = 1403; public static final int SYSZ_INS_LXDR = 1404; public static final int SYSZ_INS_LXDTR = 1405; public static final int SYSZ_INS_LXE = 1406; public static final int SYSZ_INS_LXER = 1407; public static final int SYSZ_INS_LZRF = 1408; public static final int SYSZ_INS_LZRG = 1409; public static final int SYSZ_INS_M = 1410; public static final int SYSZ_INS_MAD = 1411; public static final int SYSZ_INS_MADR = 1412; public static final int SYSZ_INS_MAE = 1413; public static final int SYSZ_INS_MAER = 1414; public static final int SYSZ_INS_MAY = 1415; public static final int SYSZ_INS_MAYH = 1416; public static final int SYSZ_INS_MAYHR = 1417; public static final int SYSZ_INS_MAYL = 1418; public static final int SYSZ_INS_MAYLR = 1419; public static final int SYSZ_INS_MAYR = 1420; public static final int SYSZ_INS_MC = 1421; public static final int SYSZ_INS_MD = 1422; public static final int SYSZ_INS_MDE = 1423; public static final int SYSZ_INS_MDER = 1424; public static final int SYSZ_INS_MDR = 1425; public static final int SYSZ_INS_MDTR = 1426; public static final int SYSZ_INS_MDTRA = 1427; public static final int SYSZ_INS_ME = 1428; public static final int SYSZ_INS_MEE = 1429; public static final int SYSZ_INS_MEER = 1430; public static final int SYSZ_INS_MER = 1431; public static final int SYSZ_INS_MFY = 1432; public static final int SYSZ_INS_MG = 1433; public static final int SYSZ_INS_MGH = 1434; public static final int SYSZ_INS_MGRK = 1435; public static final int SYSZ_INS_ML = 1436; public static final int SYSZ_INS_MLR = 1437; public static final int SYSZ_INS_MP = 1438; public static final int SYSZ_INS_MR = 1439; public static final int SYSZ_INS_MSC = 1440; public static final int SYSZ_INS_MSCH = 1441; public static final int SYSZ_INS_MSD = 1442; public static final int SYSZ_INS_MSDR = 1443; public static final int SYSZ_INS_MSE = 1444; public static final int SYSZ_INS_MSER = 1445; public static final int SYSZ_INS_MSGC = 1446; public static final int SYSZ_INS_MSGRKC = 1447; public static final int SYSZ_INS_MSRKC = 1448; public static final int SYSZ_INS_MSTA = 1449; public static final int SYSZ_INS_MVCDK = 1450; public static final int SYSZ_INS_MVCIN = 1451; public static final int SYSZ_INS_MVCK = 1452; public static final int SYSZ_INS_MVCL = 1453; public static final int SYSZ_INS_MVCLE = 1454; public static final int SYSZ_INS_MVCLU = 1455; public static final int SYSZ_INS_MVCOS = 1456; public static final int SYSZ_INS_MVCP = 1457; public static final int SYSZ_INS_MVCS = 1458; public static final int SYSZ_INS_MVCSK = 1459; public static final int SYSZ_INS_MVN = 1460; public static final int SYSZ_INS_MVO = 1461; public static final int SYSZ_INS_MVPG = 1462; public static final int SYSZ_INS_MVZ = 1463; public static final int SYSZ_INS_MXD = 1464; public static final int SYSZ_INS_MXDR = 1465; public static final int SYSZ_INS_MXR = 1466; public static final int SYSZ_INS_MXTR = 1467; public static final int SYSZ_INS_MXTRA = 1468; public static final int SYSZ_INS_MY = 1469; public static final int SYSZ_INS_MYH = 1470; public static final int SYSZ_INS_MYHR = 1471; public static final int SYSZ_INS_MYL = 1472; public static final int SYSZ_INS_MYLR = 1473; public static final int SYSZ_INS_MYR = 1474; public static final int SYSZ_INS_NIAI = 1475; public static final int SYSZ_INS_NTSTG = 1476; public static final int SYSZ_INS_PACK = 1477; public static final int SYSZ_INS_PALB = 1478; public static final int SYSZ_INS_PC = 1479; public static final int SYSZ_INS_PCC = 1480; public static final int SYSZ_INS_PCKMO = 1481; public static final int SYSZ_INS_PFMF = 1482; public static final int SYSZ_INS_PFPO = 1483; public static final int SYSZ_INS_PGIN = 1484; public static final int SYSZ_INS_PGOUT = 1485; public static final int SYSZ_INS_PKA = 1486; public static final int SYSZ_INS_PKU = 1487; public static final int SYSZ_INS_PLO = 1488; public static final int SYSZ_INS_POPCNT = 1489; public static final int SYSZ_INS_PPA = 1490; public static final int SYSZ_INS_PPNO = 1491; public static final int SYSZ_INS_PR = 1492; public static final int SYSZ_INS_PRNO = 1493; public static final int SYSZ_INS_PT = 1494; public static final int SYSZ_INS_PTF = 1495; public static final int SYSZ_INS_PTFF = 1496; public static final int SYSZ_INS_PTI = 1497; public static final int SYSZ_INS_PTLB = 1498; public static final int SYSZ_INS_QADTR = 1499; public static final int SYSZ_INS_QAXTR = 1500; public static final int SYSZ_INS_QCTRI = 1501; public static final int SYSZ_INS_QSI = 1502; public static final int SYSZ_INS_RCHP = 1503; public static final int SYSZ_INS_RISBGN = 1504; public static final int SYSZ_INS_RP = 1505; public static final int SYSZ_INS_RRBE = 1506; public static final int SYSZ_INS_RRBM = 1507; public static final int SYSZ_INS_RRDTR = 1508; public static final int SYSZ_INS_RRXTR = 1509; public static final int SYSZ_INS_RSCH = 1510; public static final int SYSZ_INS_SAC = 1511; public static final int SYSZ_INS_SACF = 1512; public static final int SYSZ_INS_SAL = 1513; public static final int SYSZ_INS_SAM24 = 1514; public static final int SYSZ_INS_SAM31 = 1515; public static final int SYSZ_INS_SAM64 = 1516; public static final int SYSZ_INS_SAR = 1517; public static final int SYSZ_INS_SCCTR = 1518; public static final int SYSZ_INS_SCHM = 1519; public static final int SYSZ_INS_SCK = 1520; public static final int SYSZ_INS_SCKC = 1521; public static final int SYSZ_INS_SCKPF = 1522; public static final int SYSZ_INS_SD = 1523; public static final int SYSZ_INS_SDR = 1524; public static final int SYSZ_INS_SDTR = 1525; public static final int SYSZ_INS_SDTRA = 1526; public static final int SYSZ_INS_SE = 1527; public static final int SYSZ_INS_SER = 1528; public static final int SYSZ_INS_SFASR = 1529; public static final int SYSZ_INS_SFPC = 1530; public static final int SYSZ_INS_SGH = 1531; public static final int SYSZ_INS_SHHHR = 1532; public static final int SYSZ_INS_SHHLR = 1533; public static final int SYSZ_INS_SIE = 1534; public static final int SYSZ_INS_SIGA = 1535; public static final int SYSZ_INS_SIGP = 1536; public static final int SYSZ_INS_SLA = 1537; public static final int SYSZ_INS_SLAG = 1538; public static final int SYSZ_INS_SLAK = 1539; public static final int SYSZ_INS_SLDA = 1540; public static final int SYSZ_INS_SLDL = 1541; public static final int SYSZ_INS_SLDT = 1542; public static final int SYSZ_INS_SLHHHR = 1543; public static final int SYSZ_INS_SLHHLR = 1544; public static final int SYSZ_INS_SLXT = 1545; public static final int SYSZ_INS_SP = 1546; public static final int SYSZ_INS_SPCTR = 1547; public static final int SYSZ_INS_SPKA = 1548; public static final int SYSZ_INS_SPM = 1549; public static final int SYSZ_INS_SPT = 1550; public static final int SYSZ_INS_SPX = 1551; public static final int SYSZ_INS_SQD = 1552; public static final int SYSZ_INS_SQDR = 1553; public static final int SYSZ_INS_SQE = 1554; public static final int SYSZ_INS_SQER = 1555; public static final int SYSZ_INS_SQXR = 1556; public static final int SYSZ_INS_SRDA = 1557; public static final int SYSZ_INS_SRDL = 1558; public static final int SYSZ_INS_SRDT = 1559; public static final int SYSZ_INS_SRNM = 1560; public static final int SYSZ_INS_SRNMB = 1561; public static final int SYSZ_INS_SRNMT = 1562; public static final int SYSZ_INS_SRP = 1563; public static final int SYSZ_INS_SRSTU = 1564; public static final int SYSZ_INS_SRXT = 1565; public static final int SYSZ_INS_SSAIR = 1566; public static final int SYSZ_INS_SSAR = 1567; public static final int SYSZ_INS_SSCH = 1568; public static final int SYSZ_INS_SSKE = 1569; public static final int SYSZ_INS_SSM = 1570; public static final int SYSZ_INS_STAM = 1571; public static final int SYSZ_INS_STAMY = 1572; public static final int SYSZ_INS_STAP = 1573; public static final int SYSZ_INS_STCK = 1574; public static final int SYSZ_INS_STCKC = 1575; public static final int SYSZ_INS_STCKE = 1576; public static final int SYSZ_INS_STCKF = 1577; public static final int SYSZ_INS_STCM = 1578; public static final int SYSZ_INS_STCMH = 1579; public static final int SYSZ_INS_STCMY = 1580; public static final int SYSZ_INS_STCPS = 1581; public static final int SYSZ_INS_STCRW = 1582; public static final int SYSZ_INS_STCTG = 1583; public static final int SYSZ_INS_STCTL = 1584; public static final int SYSZ_INS_STFL = 1585; public static final int SYSZ_INS_STFLE = 1586; public static final int SYSZ_INS_STFPC = 1587; public static final int SYSZ_INS_STGSC = 1588; public static final int SYSZ_INS_STIDP = 1589; public static final int SYSZ_INS_STM = 1590; public static final int SYSZ_INS_STMH = 1591; public static final int SYSZ_INS_STMY = 1592; public static final int SYSZ_INS_STNSM = 1593; public static final int SYSZ_INS_STOCFH = 1594; public static final int SYSZ_INS_STOCFHE = 1595; public static final int SYSZ_INS_STOCFHH = 1596; public static final int SYSZ_INS_STOCFHHE = 1597; public static final int SYSZ_INS_STOCFHL = 1598; public static final int SYSZ_INS_STOCFHLE = 1599; public static final int SYSZ_INS_STOCFHLH = 1600; public static final int SYSZ_INS_STOCFHM = 1601; public static final int SYSZ_INS_STOCFHNE = 1602; public static final int SYSZ_INS_STOCFHNH = 1603; public static final int SYSZ_INS_STOCFHNHE = 1604; public static final int SYSZ_INS_STOCFHNL = 1605; public static final int SYSZ_INS_STOCFHNLE = 1606; public static final int SYSZ_INS_STOCFHNLH = 1607; public static final int SYSZ_INS_STOCFHNM = 1608; public static final int SYSZ_INS_STOCFHNO = 1609; public static final int SYSZ_INS_STOCFHNP = 1610; public static final int SYSZ_INS_STOCFHNZ = 1611; public static final int SYSZ_INS_STOCFHO = 1612; public static final int SYSZ_INS_STOCFHP = 1613; public static final int SYSZ_INS_STOCFHZ = 1614; public static final int SYSZ_INS_STOCGM = 1615; public static final int SYSZ_INS_STOCGNM = 1616; public static final int SYSZ_INS_STOCGNP = 1617; public static final int SYSZ_INS_STOCGNZ = 1618; public static final int SYSZ_INS_STOCGP = 1619; public static final int SYSZ_INS_STOCGZ = 1620; public static final int SYSZ_INS_STOCM = 1621; public static final int SYSZ_INS_STOCNM = 1622; public static final int SYSZ_INS_STOCNP = 1623; public static final int SYSZ_INS_STOCNZ = 1624; public static final int SYSZ_INS_STOCP = 1625; public static final int SYSZ_INS_STOCZ = 1626; public static final int SYSZ_INS_STOSM = 1627; public static final int SYSZ_INS_STPQ = 1628; public static final int SYSZ_INS_STPT = 1629; public static final int SYSZ_INS_STPX = 1630; public static final int SYSZ_INS_STRAG = 1631; public static final int SYSZ_INS_STRVH = 1632; public static final int SYSZ_INS_STSCH = 1633; public static final int SYSZ_INS_STSI = 1634; public static final int SYSZ_INS_STURA = 1635; public static final int SYSZ_INS_STURG = 1636; public static final int SYSZ_INS_SU = 1637; public static final int SYSZ_INS_SUR = 1638; public static final int SYSZ_INS_SVC = 1639; public static final int SYSZ_INS_SW = 1640; public static final int SYSZ_INS_SWR = 1641; public static final int SYSZ_INS_SXR = 1642; public static final int SYSZ_INS_SXTR = 1643; public static final int SYSZ_INS_SXTRA = 1644; public static final int SYSZ_INS_TABORT = 1645; public static final int SYSZ_INS_TAM = 1646; public static final int SYSZ_INS_TAR = 1647; public static final int SYSZ_INS_TB = 1648; public static final int SYSZ_INS_TBDR = 1649; public static final int SYSZ_INS_TBEDR = 1650; public static final int SYSZ_INS_TBEGIN = 1651; public static final int SYSZ_INS_TBEGINC = 1652; public static final int SYSZ_INS_TCDB = 1653; public static final int SYSZ_INS_TCEB = 1654; public static final int SYSZ_INS_TCXB = 1655; public static final int SYSZ_INS_TDCDT = 1656; public static final int SYSZ_INS_TDCET = 1657; public static final int SYSZ_INS_TDCXT = 1658; public static final int SYSZ_INS_TDGDT = 1659; public static final int SYSZ_INS_TDGET = 1660; public static final int SYSZ_INS_TDGXT = 1661; public static final int SYSZ_INS_TEND = 1662; public static final int SYSZ_INS_THDER = 1663; public static final int SYSZ_INS_THDR = 1664; public static final int SYSZ_INS_TP = 1665; public static final int SYSZ_INS_TPI = 1666; public static final int SYSZ_INS_TPROT = 1667; public static final int SYSZ_INS_TR = 1668; public static final int SYSZ_INS_TRACE = 1669; public static final int SYSZ_INS_TRACG = 1670; public static final int SYSZ_INS_TRAP2 = 1671; public static final int SYSZ_INS_TRAP4 = 1672; public static final int SYSZ_INS_TRE = 1673; public static final int SYSZ_INS_TROO = 1674; public static final int SYSZ_INS_TROT = 1675; public static final int SYSZ_INS_TRT = 1676; public static final int SYSZ_INS_TRTE = 1677; public static final int SYSZ_INS_TRTO = 1678; public static final int SYSZ_INS_TRTR = 1679; public static final int SYSZ_INS_TRTRE = 1680; public static final int SYSZ_INS_TRTT = 1681; public static final int SYSZ_INS_TS = 1682; public static final int SYSZ_INS_TSCH = 1683; public static final int SYSZ_INS_UNPK = 1684; public static final int SYSZ_INS_UNPKA = 1685; public static final int SYSZ_INS_UNPKU = 1686; public static final int SYSZ_INS_UPT = 1687; public static final int SYSZ_INS_VA = 1688; public static final int SYSZ_INS_VAB = 1689; public static final int SYSZ_INS_VAC = 1690; public static final int SYSZ_INS_VACC = 1691; public static final int SYSZ_INS_VACCB = 1692; public static final int SYSZ_INS_VACCC = 1693; public static final int SYSZ_INS_VACCCQ = 1694; public static final int SYSZ_INS_VACCF = 1695; public static final int SYSZ_INS_VACCG = 1696; public static final int SYSZ_INS_VACCH = 1697; public static final int SYSZ_INS_VACCQ = 1698; public static final int SYSZ_INS_VACQ = 1699; public static final int SYSZ_INS_VAF = 1700; public static final int SYSZ_INS_VAG = 1701; public static final int SYSZ_INS_VAH = 1702; public static final int SYSZ_INS_VAP = 1703; public static final int SYSZ_INS_VAQ = 1704; public static final int SYSZ_INS_VAVG = 1705; public static final int SYSZ_INS_VAVGB = 1706; public static final int SYSZ_INS_VAVGF = 1707; public static final int SYSZ_INS_VAVGG = 1708; public static final int SYSZ_INS_VAVGH = 1709; public static final int SYSZ_INS_VAVGL = 1710; public static final int SYSZ_INS_VAVGLB = 1711; public static final int SYSZ_INS_VAVGLF = 1712; public static final int SYSZ_INS_VAVGLG = 1713; public static final int SYSZ_INS_VAVGLH = 1714; public static final int SYSZ_INS_VBPERM = 1715; public static final int SYSZ_INS_VCDG = 1716; public static final int SYSZ_INS_VCDGB = 1717; public static final int SYSZ_INS_VCDLG = 1718; public static final int SYSZ_INS_VCDLGB = 1719; public static final int SYSZ_INS_VCEQ = 1720; public static final int SYSZ_INS_VCEQB = 1721; public static final int SYSZ_INS_VCEQBS = 1722; public static final int SYSZ_INS_VCEQF = 1723; public static final int SYSZ_INS_VCEQFS = 1724; public static final int SYSZ_INS_VCEQG = 1725; public static final int SYSZ_INS_VCEQGS = 1726; public static final int SYSZ_INS_VCEQH = 1727; public static final int SYSZ_INS_VCEQHS = 1728; public static final int SYSZ_INS_VCGD = 1729; public static final int SYSZ_INS_VCGDB = 1730; public static final int SYSZ_INS_VCH = 1731; public static final int SYSZ_INS_VCHB = 1732; public static final int SYSZ_INS_VCHBS = 1733; public static final int SYSZ_INS_VCHF = 1734; public static final int SYSZ_INS_VCHFS = 1735; public static final int SYSZ_INS_VCHG = 1736; public static final int SYSZ_INS_VCHGS = 1737; public static final int SYSZ_INS_VCHH = 1738; public static final int SYSZ_INS_VCHHS = 1739; public static final int SYSZ_INS_VCHL = 1740; public static final int SYSZ_INS_VCHLB = 1741; public static final int SYSZ_INS_VCHLBS = 1742; public static final int SYSZ_INS_VCHLF = 1743; public static final int SYSZ_INS_VCHLFS = 1744; public static final int SYSZ_INS_VCHLG = 1745; public static final int SYSZ_INS_VCHLGS = 1746; public static final int SYSZ_INS_VCHLH = 1747; public static final int SYSZ_INS_VCHLHS = 1748; public static final int SYSZ_INS_VCKSM = 1749; public static final int SYSZ_INS_VCLGD = 1750; public static final int SYSZ_INS_VCLGDB = 1751; public static final int SYSZ_INS_VCLZ = 1752; public static final int SYSZ_INS_VCLZB = 1753; public static final int SYSZ_INS_VCLZF = 1754; public static final int SYSZ_INS_VCLZG = 1755; public static final int SYSZ_INS_VCLZH = 1756; public static final int SYSZ_INS_VCP = 1757; public static final int SYSZ_INS_VCTZ = 1758; public static final int SYSZ_INS_VCTZB = 1759; public static final int SYSZ_INS_VCTZF = 1760; public static final int SYSZ_INS_VCTZG = 1761; public static final int SYSZ_INS_VCTZH = 1762; public static final int SYSZ_INS_VCVB = 1763; public static final int SYSZ_INS_VCVBG = 1764; public static final int SYSZ_INS_VCVD = 1765; public static final int SYSZ_INS_VCVDG = 1766; public static final int SYSZ_INS_VDP = 1767; public static final int SYSZ_INS_VEC = 1768; public static final int SYSZ_INS_VECB = 1769; public static final int SYSZ_INS_VECF = 1770; public static final int SYSZ_INS_VECG = 1771; public static final int SYSZ_INS_VECH = 1772; public static final int SYSZ_INS_VECL = 1773; public static final int SYSZ_INS_VECLB = 1774; public static final int SYSZ_INS_VECLF = 1775; public static final int SYSZ_INS_VECLG = 1776; public static final int SYSZ_INS_VECLH = 1777; public static final int SYSZ_INS_VERIM = 1778; public static final int SYSZ_INS_VERIMB = 1779; public static final int SYSZ_INS_VERIMF = 1780; public static final int SYSZ_INS_VERIMG = 1781; public static final int SYSZ_INS_VERIMH = 1782; public static final int SYSZ_INS_VERLL = 1783; public static final int SYSZ_INS_VERLLB = 1784; public static final int SYSZ_INS_VERLLF = 1785; public static final int SYSZ_INS_VERLLG = 1786; public static final int SYSZ_INS_VERLLH = 1787; public static final int SYSZ_INS_VERLLV = 1788; public static final int SYSZ_INS_VERLLVB = 1789; public static final int SYSZ_INS_VERLLVF = 1790; public static final int SYSZ_INS_VERLLVG = 1791; public static final int SYSZ_INS_VERLLVH = 1792; public static final int SYSZ_INS_VESL = 1793; public static final int SYSZ_INS_VESLB = 1794; public static final int SYSZ_INS_VESLF = 1795; public static final int SYSZ_INS_VESLG = 1796; public static final int SYSZ_INS_VESLH = 1797; public static final int SYSZ_INS_VESLV = 1798; public static final int SYSZ_INS_VESLVB = 1799; public static final int SYSZ_INS_VESLVF = 1800; public static final int SYSZ_INS_VESLVG = 1801; public static final int SYSZ_INS_VESLVH = 1802; public static final int SYSZ_INS_VESRA = 1803; public static final int SYSZ_INS_VESRAB = 1804; public static final int SYSZ_INS_VESRAF = 1805; public static final int SYSZ_INS_VESRAG = 1806; public static final int SYSZ_INS_VESRAH = 1807; public static final int SYSZ_INS_VESRAV = 1808; public static final int SYSZ_INS_VESRAVB = 1809; public static final int SYSZ_INS_VESRAVF = 1810; public static final int SYSZ_INS_VESRAVG = 1811; public static final int SYSZ_INS_VESRAVH = 1812; public static final int SYSZ_INS_VESRL = 1813; public static final int SYSZ_INS_VESRLB = 1814; public static final int SYSZ_INS_VESRLF = 1815; public static final int SYSZ_INS_VESRLG = 1816; public static final int SYSZ_INS_VESRLH = 1817; public static final int SYSZ_INS_VESRLV = 1818; public static final int SYSZ_INS_VESRLVB = 1819; public static final int SYSZ_INS_VESRLVF = 1820; public static final int SYSZ_INS_VESRLVG = 1821; public static final int SYSZ_INS_VESRLVH = 1822; public static final int SYSZ_INS_VFA = 1823; public static final int SYSZ_INS_VFADB = 1824; public static final int SYSZ_INS_VFAE = 1825; public static final int SYSZ_INS_VFAEB = 1826; public static final int SYSZ_INS_VFAEBS = 1827; public static final int SYSZ_INS_VFAEF = 1828; public static final int SYSZ_INS_VFAEFS = 1829; public static final int SYSZ_INS_VFAEH = 1830; public static final int SYSZ_INS_VFAEHS = 1831; public static final int SYSZ_INS_VFAEZB = 1832; public static final int SYSZ_INS_VFAEZBS = 1833; public static final int SYSZ_INS_VFAEZF = 1834; public static final int SYSZ_INS_VFAEZFS = 1835; public static final int SYSZ_INS_VFAEZH = 1836; public static final int SYSZ_INS_VFAEZHS = 1837; public static final int SYSZ_INS_VFASB = 1838; public static final int SYSZ_INS_VFCE = 1839; public static final int SYSZ_INS_VFCEDB = 1840; public static final int SYSZ_INS_VFCEDBS = 1841; public static final int SYSZ_INS_VFCESB = 1842; public static final int SYSZ_INS_VFCESBS = 1843; public static final int SYSZ_INS_VFCH = 1844; public static final int SYSZ_INS_VFCHDB = 1845; public static final int SYSZ_INS_VFCHDBS = 1846; public static final int SYSZ_INS_VFCHE = 1847; public static final int SYSZ_INS_VFCHEDB = 1848; public static final int SYSZ_INS_VFCHEDBS = 1849; public static final int SYSZ_INS_VFCHESB = 1850; public static final int SYSZ_INS_VFCHESBS = 1851; public static final int SYSZ_INS_VFCHSB = 1852; public static final int SYSZ_INS_VFCHSBS = 1853; public static final int SYSZ_INS_VFD = 1854; public static final int SYSZ_INS_VFDDB = 1855; public static final int SYSZ_INS_VFDSB = 1856; public static final int SYSZ_INS_VFEE = 1857; public static final int SYSZ_INS_VFEEB = 1858; public static final int SYSZ_INS_VFEEBS = 1859; public static final int SYSZ_INS_VFEEF = 1860; public static final int SYSZ_INS_VFEEFS = 1861; public static final int SYSZ_INS_VFEEH = 1862; public static final int SYSZ_INS_VFEEHS = 1863; public static final int SYSZ_INS_VFEEZB = 1864; public static final int SYSZ_INS_VFEEZBS = 1865; public static final int SYSZ_INS_VFEEZF = 1866; public static final int SYSZ_INS_VFEEZFS = 1867; public static final int SYSZ_INS_VFEEZH = 1868; public static final int SYSZ_INS_VFEEZHS = 1869; public static final int SYSZ_INS_VFENE = 1870; public static final int SYSZ_INS_VFENEB = 1871; public static final int SYSZ_INS_VFENEBS = 1872; public static final int SYSZ_INS_VFENEF = 1873; public static final int SYSZ_INS_VFENEFS = 1874; public static final int SYSZ_INS_VFENEH = 1875; public static final int SYSZ_INS_VFENEHS = 1876; public static final int SYSZ_INS_VFENEZB = 1877; public static final int SYSZ_INS_VFENEZBS = 1878; public static final int SYSZ_INS_VFENEZF = 1879; public static final int SYSZ_INS_VFENEZFS = 1880; public static final int SYSZ_INS_VFENEZH = 1881; public static final int SYSZ_INS_VFENEZHS = 1882; public static final int SYSZ_INS_VFI = 1883; public static final int SYSZ_INS_VFIDB = 1884; public static final int SYSZ_INS_VFISB = 1885; public static final int SYSZ_INS_VFKEDB = 1886; public static final int SYSZ_INS_VFKEDBS = 1887; public static final int SYSZ_INS_VFKESB = 1888; public static final int SYSZ_INS_VFKESBS = 1889; public static final int SYSZ_INS_VFKHDB = 1890; public static final int SYSZ_INS_VFKHDBS = 1891; public static final int SYSZ_INS_VFKHEDB = 1892; public static final int SYSZ_INS_VFKHEDBS = 1893; public static final int SYSZ_INS_VFKHESB = 1894; public static final int SYSZ_INS_VFKHESBS = 1895; public static final int SYSZ_INS_VFKHSB = 1896; public static final int SYSZ_INS_VFKHSBS = 1897; public static final int SYSZ_INS_VFLCDB = 1898; public static final int SYSZ_INS_VFLCSB = 1899; public static final int SYSZ_INS_VFLL = 1900; public static final int SYSZ_INS_VFLLS = 1901; public static final int SYSZ_INS_VFLNDB = 1902; public static final int SYSZ_INS_VFLNSB = 1903; public static final int SYSZ_INS_VFLPDB = 1904; public static final int SYSZ_INS_VFLPSB = 1905; public static final int SYSZ_INS_VFLR = 1906; public static final int SYSZ_INS_VFLRD = 1907; public static final int SYSZ_INS_VFM = 1908; public static final int SYSZ_INS_VFMA = 1909; public static final int SYSZ_INS_VFMADB = 1910; public static final int SYSZ_INS_VFMASB = 1911; public static final int SYSZ_INS_VFMAX = 1912; public static final int SYSZ_INS_VFMAXDB = 1913; public static final int SYSZ_INS_VFMAXSB = 1914; public static final int SYSZ_INS_VFMDB = 1915; public static final int SYSZ_INS_VFMIN = 1916; public static final int SYSZ_INS_VFMINDB = 1917; public static final int SYSZ_INS_VFMINSB = 1918; public static final int SYSZ_INS_VFMS = 1919; public static final int SYSZ_INS_VFMSB = 1920; public static final int SYSZ_INS_VFMSDB = 1921; public static final int SYSZ_INS_VFMSSB = 1922; public static final int SYSZ_INS_VFNMA = 1923; public static final int SYSZ_INS_VFNMADB = 1924; public static final int SYSZ_INS_VFNMASB = 1925; public static final int SYSZ_INS_VFNMS = 1926; public static final int SYSZ_INS_VFNMSDB = 1927; public static final int SYSZ_INS_VFNMSSB = 1928; public static final int SYSZ_INS_VFPSO = 1929; public static final int SYSZ_INS_VFPSODB = 1930; public static final int SYSZ_INS_VFPSOSB = 1931; public static final int SYSZ_INS_VFS = 1932; public static final int SYSZ_INS_VFSDB = 1933; public static final int SYSZ_INS_VFSQ = 1934; public static final int SYSZ_INS_VFSQDB = 1935; public static final int SYSZ_INS_VFSQSB = 1936; public static final int SYSZ_INS_VFSSB = 1937; public static final int SYSZ_INS_VFTCI = 1938; public static final int SYSZ_INS_VFTCIDB = 1939; public static final int SYSZ_INS_VFTCISB = 1940; public static final int SYSZ_INS_VGBM = 1941; public static final int SYSZ_INS_VGEF = 1942; public static final int SYSZ_INS_VGEG = 1943; public static final int SYSZ_INS_VGFM = 1944; public static final int SYSZ_INS_VGFMA = 1945; public static final int SYSZ_INS_VGFMAB = 1946; public static final int SYSZ_INS_VGFMAF = 1947; public static final int SYSZ_INS_VGFMAG = 1948; public static final int SYSZ_INS_VGFMAH = 1949; public static final int SYSZ_INS_VGFMB = 1950; public static final int SYSZ_INS_VGFMF = 1951; public static final int SYSZ_INS_VGFMG = 1952; public static final int SYSZ_INS_VGFMH = 1953; public static final int SYSZ_INS_VGM = 1954; public static final int SYSZ_INS_VGMB = 1955; public static final int SYSZ_INS_VGMF = 1956; public static final int SYSZ_INS_VGMG = 1957; public static final int SYSZ_INS_VGMH = 1958; public static final int SYSZ_INS_VISTR = 1959; public static final int SYSZ_INS_VISTRB = 1960; public static final int SYSZ_INS_VISTRBS = 1961; public static final int SYSZ_INS_VISTRF = 1962; public static final int SYSZ_INS_VISTRFS = 1963; public static final int SYSZ_INS_VISTRH = 1964; public static final int SYSZ_INS_VISTRHS = 1965; public static final int SYSZ_INS_VL = 1966; public static final int SYSZ_INS_VLBB = 1967; public static final int SYSZ_INS_VLC = 1968; public static final int SYSZ_INS_VLCB = 1969; public static final int SYSZ_INS_VLCF = 1970; public static final int SYSZ_INS_VLCG = 1971; public static final int SYSZ_INS_VLCH = 1972; public static final int SYSZ_INS_VLDE = 1973; public static final int SYSZ_INS_VLDEB = 1974; public static final int SYSZ_INS_VLEB = 1975; public static final int SYSZ_INS_VLED = 1976; public static final int SYSZ_INS_VLEDB = 1977; public static final int SYSZ_INS_VLEF = 1978; public static final int SYSZ_INS_VLEG = 1979; public static final int SYSZ_INS_VLEH = 1980; public static final int SYSZ_INS_VLEIB = 1981; public static final int SYSZ_INS_VLEIF = 1982; public static final int SYSZ_INS_VLEIG = 1983; public static final int SYSZ_INS_VLEIH = 1984; public static final int SYSZ_INS_VLGV = 1985; public static final int SYSZ_INS_VLGVB = 1986; public static final int SYSZ_INS_VLGVF = 1987; public static final int SYSZ_INS_VLGVG = 1988; public static final int SYSZ_INS_VLGVH = 1989; public static final int SYSZ_INS_VLIP = 1990; public static final int SYSZ_INS_VLL = 1991; public static final int SYSZ_INS_VLLEZ = 1992; public static final int SYSZ_INS_VLLEZB = 1993; public static final int SYSZ_INS_VLLEZF = 1994; public static final int SYSZ_INS_VLLEZG = 1995; public static final int SYSZ_INS_VLLEZH = 1996; public static final int SYSZ_INS_VLLEZLF = 1997; public static final int SYSZ_INS_VLM = 1998; public static final int SYSZ_INS_VLP = 1999; public static final int SYSZ_INS_VLPB = 2000; public static final int SYSZ_INS_VLPF = 2001; public static final int SYSZ_INS_VLPG = 2002; public static final int SYSZ_INS_VLPH = 2003; public static final int SYSZ_INS_VLR = 2004; public static final int SYSZ_INS_VLREP = 2005; public static final int SYSZ_INS_VLREPB = 2006; public static final int SYSZ_INS_VLREPF = 2007; public static final int SYSZ_INS_VLREPG = 2008; public static final int SYSZ_INS_VLREPH = 2009; public static final int SYSZ_INS_VLRL = 2010; public static final int SYSZ_INS_VLRLR = 2011; public static final int SYSZ_INS_VLVG = 2012; public static final int SYSZ_INS_VLVGB = 2013; public static final int SYSZ_INS_VLVGF = 2014; public static final int SYSZ_INS_VLVGG = 2015; public static final int SYSZ_INS_VLVGH = 2016; public static final int SYSZ_INS_VLVGP = 2017; public static final int SYSZ_INS_VMAE = 2018; public static final int SYSZ_INS_VMAEB = 2019; public static final int SYSZ_INS_VMAEF = 2020; public static final int SYSZ_INS_VMAEH = 2021; public static final int SYSZ_INS_VMAH = 2022; public static final int SYSZ_INS_VMAHB = 2023; public static final int SYSZ_INS_VMAHF = 2024; public static final int SYSZ_INS_VMAHH = 2025; public static final int SYSZ_INS_VMAL = 2026; public static final int SYSZ_INS_VMALB = 2027; public static final int SYSZ_INS_VMALE = 2028; public static final int SYSZ_INS_VMALEB = 2029; public static final int SYSZ_INS_VMALEF = 2030; public static final int SYSZ_INS_VMALEH = 2031; public static final int SYSZ_INS_VMALF = 2032; public static final int SYSZ_INS_VMALH = 2033; public static final int SYSZ_INS_VMALHB = 2034; public static final int SYSZ_INS_VMALHF = 2035; public static final int SYSZ_INS_VMALHH = 2036; public static final int SYSZ_INS_VMALHW = 2037; public static final int SYSZ_INS_VMALO = 2038; public static final int SYSZ_INS_VMALOB = 2039; public static final int SYSZ_INS_VMALOF = 2040; public static final int SYSZ_INS_VMALOH = 2041; public static final int SYSZ_INS_VMAO = 2042; public static final int SYSZ_INS_VMAOB = 2043; public static final int SYSZ_INS_VMAOF = 2044; public static final int SYSZ_INS_VMAOH = 2045; public static final int SYSZ_INS_VME = 2046; public static final int SYSZ_INS_VMEB = 2047; public static final int SYSZ_INS_VMEF = 2048; public static final int SYSZ_INS_VMEH = 2049; public static final int SYSZ_INS_VMH = 2050; public static final int SYSZ_INS_VMHB = 2051; public static final int SYSZ_INS_VMHF = 2052; public static final int SYSZ_INS_VMHH = 2053; public static final int SYSZ_INS_VML = 2054; public static final int SYSZ_INS_VMLB = 2055; public static final int SYSZ_INS_VMLE = 2056; public static final int SYSZ_INS_VMLEB = 2057; public static final int SYSZ_INS_VMLEF = 2058; public static final int SYSZ_INS_VMLEH = 2059; public static final int SYSZ_INS_VMLF = 2060; public static final int SYSZ_INS_VMLH = 2061; public static final int SYSZ_INS_VMLHB = 2062; public static final int SYSZ_INS_VMLHF = 2063; public static final int SYSZ_INS_VMLHH = 2064; public static final int SYSZ_INS_VMLHW = 2065; public static final int SYSZ_INS_VMLO = 2066; public static final int SYSZ_INS_VMLOB = 2067; public static final int SYSZ_INS_VMLOF = 2068; public static final int SYSZ_INS_VMLOH = 2069; public static final int SYSZ_INS_VMN = 2070; public static final int SYSZ_INS_VMNB = 2071; public static final int SYSZ_INS_VMNF = 2072; public static final int SYSZ_INS_VMNG = 2073; public static final int SYSZ_INS_VMNH = 2074; public static final int SYSZ_INS_VMNL = 2075; public static final int SYSZ_INS_VMNLB = 2076; public static final int SYSZ_INS_VMNLF = 2077; public static final int SYSZ_INS_VMNLG = 2078; public static final int SYSZ_INS_VMNLH = 2079; public static final int SYSZ_INS_VMO = 2080; public static final int SYSZ_INS_VMOB = 2081; public static final int SYSZ_INS_VMOF = 2082; public static final int SYSZ_INS_VMOH = 2083; public static final int SYSZ_INS_VMP = 2084; public static final int SYSZ_INS_VMRH = 2085; public static final int SYSZ_INS_VMRHB = 2086; public static final int SYSZ_INS_VMRHF = 2087; public static final int SYSZ_INS_VMRHG = 2088; public static final int SYSZ_INS_VMRHH = 2089; public static final int SYSZ_INS_VMRL = 2090; public static final int SYSZ_INS_VMRLB = 2091; public static final int SYSZ_INS_VMRLF = 2092; public static final int SYSZ_INS_VMRLG = 2093; public static final int SYSZ_INS_VMRLH = 2094; public static final int SYSZ_INS_VMSL = 2095; public static final int SYSZ_INS_VMSLG = 2096; public static final int SYSZ_INS_VMSP = 2097; public static final int SYSZ_INS_VMX = 2098; public static final int SYSZ_INS_VMXB = 2099; public static final int SYSZ_INS_VMXF = 2100; public static final int SYSZ_INS_VMXG = 2101; public static final int SYSZ_INS_VMXH = 2102; public static final int SYSZ_INS_VMXL = 2103; public static final int SYSZ_INS_VMXLB = 2104; public static final int SYSZ_INS_VMXLF = 2105; public static final int SYSZ_INS_VMXLG = 2106; public static final int SYSZ_INS_VMXLH = 2107; public static final int SYSZ_INS_VN = 2108; public static final int SYSZ_INS_VNC = 2109; public static final int SYSZ_INS_VNN = 2110; public static final int SYSZ_INS_VNO = 2111; public static final int SYSZ_INS_VNX = 2112; public static final int SYSZ_INS_VO = 2113; public static final int SYSZ_INS_VOC = 2114; public static final int SYSZ_INS_VONE = 2115; public static final int SYSZ_INS_VPDI = 2116; public static final int SYSZ_INS_VPERM = 2117; public static final int SYSZ_INS_VPK = 2118; public static final int SYSZ_INS_VPKF = 2119; public static final int SYSZ_INS_VPKG = 2120; public static final int SYSZ_INS_VPKH = 2121; public static final int SYSZ_INS_VPKLS = 2122; public static final int SYSZ_INS_VPKLSF = 2123; public static final int SYSZ_INS_VPKLSFS = 2124; public static final int SYSZ_INS_VPKLSG = 2125; public static final int SYSZ_INS_VPKLSGS = 2126; public static final int SYSZ_INS_VPKLSH = 2127; public static final int SYSZ_INS_VPKLSHS = 2128; public static final int SYSZ_INS_VPKS = 2129; public static final int SYSZ_INS_VPKSF = 2130; public static final int SYSZ_INS_VPKSFS = 2131; public static final int SYSZ_INS_VPKSG = 2132; public static final int SYSZ_INS_VPKSGS = 2133; public static final int SYSZ_INS_VPKSH = 2134; public static final int SYSZ_INS_VPKSHS = 2135; public static final int SYSZ_INS_VPKZ = 2136; public static final int SYSZ_INS_VPOPCT = 2137; public static final int SYSZ_INS_VPOPCTB = 2138; public static final int SYSZ_INS_VPOPCTF = 2139; public static final int SYSZ_INS_VPOPCTG = 2140; public static final int SYSZ_INS_VPOPCTH = 2141; public static final int SYSZ_INS_VPSOP = 2142; public static final int SYSZ_INS_VREP = 2143; public static final int SYSZ_INS_VREPB = 2144; public static final int SYSZ_INS_VREPF = 2145; public static final int SYSZ_INS_VREPG = 2146; public static final int SYSZ_INS_VREPH = 2147; public static final int SYSZ_INS_VREPI = 2148; public static final int SYSZ_INS_VREPIB = 2149; public static final int SYSZ_INS_VREPIF = 2150; public static final int SYSZ_INS_VREPIG = 2151; public static final int SYSZ_INS_VREPIH = 2152; public static final int SYSZ_INS_VRP = 2153; public static final int SYSZ_INS_VS = 2154; public static final int SYSZ_INS_VSB = 2155; public static final int SYSZ_INS_VSBCBI = 2156; public static final int SYSZ_INS_VSBCBIQ = 2157; public static final int SYSZ_INS_VSBI = 2158; public static final int SYSZ_INS_VSBIQ = 2159; public static final int SYSZ_INS_VSCBI = 2160; public static final int SYSZ_INS_VSCBIB = 2161; public static final int SYSZ_INS_VSCBIF = 2162; public static final int SYSZ_INS_VSCBIG = 2163; public static final int SYSZ_INS_VSCBIH = 2164; public static final int SYSZ_INS_VSCBIQ = 2165; public static final int SYSZ_INS_VSCEF = 2166; public static final int SYSZ_INS_VSCEG = 2167; public static final int SYSZ_INS_VSDP = 2168; public static final int SYSZ_INS_VSEG = 2169; public static final int SYSZ_INS_VSEGB = 2170; public static final int SYSZ_INS_VSEGF = 2171; public static final int SYSZ_INS_VSEGH = 2172; public static final int SYSZ_INS_VSEL = 2173; public static final int SYSZ_INS_VSF = 2174; public static final int SYSZ_INS_VSG = 2175; public static final int SYSZ_INS_VSH = 2176; public static final int SYSZ_INS_VSL = 2177; public static final int SYSZ_INS_VSLB = 2178; public static final int SYSZ_INS_VSLDB = 2179; public static final int SYSZ_INS_VSP = 2180; public static final int SYSZ_INS_VSQ = 2181; public static final int SYSZ_INS_VSRA = 2182; public static final int SYSZ_INS_VSRAB = 2183; public static final int SYSZ_INS_VSRL = 2184; public static final int SYSZ_INS_VSRLB = 2185; public static final int SYSZ_INS_VSRP = 2186; public static final int SYSZ_INS_VST = 2187; public static final int SYSZ_INS_VSTEB = 2188; public static final int SYSZ_INS_VSTEF = 2189; public static final int SYSZ_INS_VSTEG = 2190; public static final int SYSZ_INS_VSTEH = 2191; public static final int SYSZ_INS_VSTL = 2192; public static final int SYSZ_INS_VSTM = 2193; public static final int SYSZ_INS_VSTRC = 2194; public static final int SYSZ_INS_VSTRCB = 2195; public static final int SYSZ_INS_VSTRCBS = 2196; public static final int SYSZ_INS_VSTRCF = 2197; public static final int SYSZ_INS_VSTRCFS = 2198; public static final int SYSZ_INS_VSTRCH = 2199; public static final int SYSZ_INS_VSTRCHS = 2200; public static final int SYSZ_INS_VSTRCZB = 2201; public static final int SYSZ_INS_VSTRCZBS = 2202; public static final int SYSZ_INS_VSTRCZF = 2203; public static final int SYSZ_INS_VSTRCZFS = 2204; public static final int SYSZ_INS_VSTRCZH = 2205; public static final int SYSZ_INS_VSTRCZHS = 2206; public static final int SYSZ_INS_VSTRL = 2207; public static final int SYSZ_INS_VSTRLR = 2208; public static final int SYSZ_INS_VSUM = 2209; public static final int SYSZ_INS_VSUMB = 2210; public static final int SYSZ_INS_VSUMG = 2211; public static final int SYSZ_INS_VSUMGF = 2212; public static final int SYSZ_INS_VSUMGH = 2213; public static final int SYSZ_INS_VSUMH = 2214; public static final int SYSZ_INS_VSUMQ = 2215; public static final int SYSZ_INS_VSUMQF = 2216; public static final int SYSZ_INS_VSUMQG = 2217; public static final int SYSZ_INS_VTM = 2218; public static final int SYSZ_INS_VTP = 2219; public static final int SYSZ_INS_VUPH = 2220; public static final int SYSZ_INS_VUPHB = 2221; public static final int SYSZ_INS_VUPHF = 2222; public static final int SYSZ_INS_VUPHH = 2223; public static final int SYSZ_INS_VUPKZ = 2224; public static final int SYSZ_INS_VUPL = 2225; public static final int SYSZ_INS_VUPLB = 2226; public static final int SYSZ_INS_VUPLF = 2227; public static final int SYSZ_INS_VUPLH = 2228; public static final int SYSZ_INS_VUPLHB = 2229; public static final int SYSZ_INS_VUPLHF = 2230; public static final int SYSZ_INS_VUPLHH = 2231; public static final int SYSZ_INS_VUPLHW = 2232; public static final int SYSZ_INS_VUPLL = 2233; public static final int SYSZ_INS_VUPLLB = 2234; public static final int SYSZ_INS_VUPLLF = 2235; public static final int SYSZ_INS_VUPLLH = 2236; public static final int SYSZ_INS_VX = 2237; public static final int SYSZ_INS_VZERO = 2238; public static final int SYSZ_INS_WCDGB = 2239; public static final int SYSZ_INS_WCDLGB = 2240; public static final int SYSZ_INS_WCGDB = 2241; public static final int SYSZ_INS_WCLGDB = 2242; public static final int SYSZ_INS_WFADB = 2243; public static final int SYSZ_INS_WFASB = 2244; public static final int SYSZ_INS_WFAXB = 2245; public static final int SYSZ_INS_WFC = 2246; public static final int SYSZ_INS_WFCDB = 2247; public static final int SYSZ_INS_WFCEDB = 2248; public static final int SYSZ_INS_WFCEDBS = 2249; public static final int SYSZ_INS_WFCESB = 2250; public static final int SYSZ_INS_WFCESBS = 2251; public static final int SYSZ_INS_WFCEXB = 2252; public static final int SYSZ_INS_WFCEXBS = 2253; public static final int SYSZ_INS_WFCHDB = 2254; public static final int SYSZ_INS_WFCHDBS = 2255; public static final int SYSZ_INS_WFCHEDB = 2256; public static final int SYSZ_INS_WFCHEDBS = 2257; public static final int SYSZ_INS_WFCHESB = 2258; public static final int SYSZ_INS_WFCHESBS = 2259; public static final int SYSZ_INS_WFCHEXB = 2260; public static final int SYSZ_INS_WFCHEXBS = 2261; public static final int SYSZ_INS_WFCHSB = 2262; public static final int SYSZ_INS_WFCHSBS = 2263; public static final int SYSZ_INS_WFCHXB = 2264; public static final int SYSZ_INS_WFCHXBS = 2265; public static final int SYSZ_INS_WFCSB = 2266; public static final int SYSZ_INS_WFCXB = 2267; public static final int SYSZ_INS_WFDDB = 2268; public static final int SYSZ_INS_WFDSB = 2269; public static final int SYSZ_INS_WFDXB = 2270; public static final int SYSZ_INS_WFIDB = 2271; public static final int SYSZ_INS_WFISB = 2272; public static final int SYSZ_INS_WFIXB = 2273; public static final int SYSZ_INS_WFK = 2274; public static final int SYSZ_INS_WFKDB = 2275; public static final int SYSZ_INS_WFKEDB = 2276; public static final int SYSZ_INS_WFKEDBS = 2277; public static final int SYSZ_INS_WFKESB = 2278; public static final int SYSZ_INS_WFKESBS = 2279; public static final int SYSZ_INS_WFKEXB = 2280; public static final int SYSZ_INS_WFKEXBS = 2281; public static final int SYSZ_INS_WFKHDB = 2282; public static final int SYSZ_INS_WFKHDBS = 2283; public static final int SYSZ_INS_WFKHEDB = 2284; public static final int SYSZ_INS_WFKHEDBS = 2285; public static final int SYSZ_INS_WFKHESB = 2286; public static final int SYSZ_INS_WFKHESBS = 2287; public static final int SYSZ_INS_WFKHEXB = 2288; public static final int SYSZ_INS_WFKHEXBS = 2289; public static final int SYSZ_INS_WFKHSB = 2290; public static final int SYSZ_INS_WFKHSBS = 2291; public static final int SYSZ_INS_WFKHXB = 2292; public static final int SYSZ_INS_WFKHXBS = 2293; public static final int SYSZ_INS_WFKSB = 2294; public static final int SYSZ_INS_WFKXB = 2295; public static final int SYSZ_INS_WFLCDB = 2296; public static final int SYSZ_INS_WFLCSB = 2297; public static final int SYSZ_INS_WFLCXB = 2298; public static final int SYSZ_INS_WFLLD = 2299; public static final int SYSZ_INS_WFLLS = 2300; public static final int SYSZ_INS_WFLNDB = 2301; public static final int SYSZ_INS_WFLNSB = 2302; public static final int SYSZ_INS_WFLNXB = 2303; public static final int SYSZ_INS_WFLPDB = 2304; public static final int SYSZ_INS_WFLPSB = 2305; public static final int SYSZ_INS_WFLPXB = 2306; public static final int SYSZ_INS_WFLRD = 2307; public static final int SYSZ_INS_WFLRX = 2308; public static final int SYSZ_INS_WFMADB = 2309; public static final int SYSZ_INS_WFMASB = 2310; public static final int SYSZ_INS_WFMAXB = 2311; public static final int SYSZ_INS_WFMAXDB = 2312; public static final int SYSZ_INS_WFMAXSB = 2313; public static final int SYSZ_INS_WFMAXXB = 2314; public static final int SYSZ_INS_WFMDB = 2315; public static final int SYSZ_INS_WFMINDB = 2316; public static final int SYSZ_INS_WFMINSB = 2317; public static final int SYSZ_INS_WFMINXB = 2318; public static final int SYSZ_INS_WFMSB = 2319; public static final int SYSZ_INS_WFMSDB = 2320; public static final int SYSZ_INS_WFMSSB = 2321; public static final int SYSZ_INS_WFMSXB = 2322; public static final int SYSZ_INS_WFMXB = 2323; public static final int SYSZ_INS_WFNMADB = 2324; public static final int SYSZ_INS_WFNMASB = 2325; public static final int SYSZ_INS_WFNMAXB = 2326; public static final int SYSZ_INS_WFNMSDB = 2327; public static final int SYSZ_INS_WFNMSSB = 2328; public static final int SYSZ_INS_WFNMSXB = 2329; public static final int SYSZ_INS_WFPSODB = 2330; public static final int SYSZ_INS_WFPSOSB = 2331; public static final int SYSZ_INS_WFPSOXB = 2332; public static final int SYSZ_INS_WFSDB = 2333; public static final int SYSZ_INS_WFSQDB = 2334; public static final int SYSZ_INS_WFSQSB = 2335; public static final int SYSZ_INS_WFSQXB = 2336; public static final int SYSZ_INS_WFSSB = 2337; public static final int SYSZ_INS_WFSXB = 2338; public static final int SYSZ_INS_WFTCIDB = 2339; public static final int SYSZ_INS_WFTCISB = 2340; public static final int SYSZ_INS_WFTCIXB = 2341; public static final int SYSZ_INS_WLDEB = 2342; public static final int SYSZ_INS_WLEDB = 2343; public static final int SYSZ_INS_XSCH = 2344; public static final int SYSZ_INS_ZAP = 2345; public static final int SYSZ_INS_ENDING = 2346; public static final int SYSZ_GRP_INVALID = 0; public static final int SYSZ_GRP_JUMP = 1; public static final int SYSZ_GRP_DISTINCTOPS = 128; public static final int SYSZ_GRP_FPEXTENSION = 129; public static final int SYSZ_GRP_HIGHWORD = 130; public static final int SYSZ_GRP_INTERLOCKEDACCESS1 = 131; public static final int SYSZ_GRP_LOADSTOREONCOND = 132; public static final int SYSZ_GRP_DFPPACKEDCONVERSION = 133; public static final int SYSZ_GRP_DFPZONEDCONVERSION = 134; public static final int SYSZ_GRP_ENHANCEDDAT2 = 135; public static final int SYSZ_GRP_EXECUTIONHINT = 136; public static final int SYSZ_GRP_GUARDEDSTORAGE = 137; public static final int SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138; public static final int SYSZ_GRP_LOADANDTRAP = 139; public static final int SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140; public static final int SYSZ_GRP_LOADSTOREONCOND2 = 141; public static final int SYSZ_GRP_MESSAGESECURITYASSIST3 = 142; public static final int SYSZ_GRP_MESSAGESECURITYASSIST4 = 143; public static final int SYSZ_GRP_MESSAGESECURITYASSIST5 = 144; public static final int SYSZ_GRP_MESSAGESECURITYASSIST7 = 145; public static final int SYSZ_GRP_MESSAGESECURITYASSIST8 = 146; public static final int SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147; public static final int SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148; public static final int SYSZ_GRP_NOVECTOR = 149; public static final int SYSZ_GRP_POPULATIONCOUNT = 150; public static final int SYSZ_GRP_PROCESSORASSIST = 151; public static final int SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152; public static final int SYSZ_GRP_TRANSACTIONALEXECUTION = 153; public static final int SYSZ_GRP_VECTOR = 154; public static final int SYSZ_GRP_VECTORENHANCEMENTS1 = 155; public static final int SYSZ_GRP_VECTORPACKEDDECIMAL = 156; public static final int SYSZ_GRP_ENDING = 157; }capstone-sys-0.15.0/capstone/bindings/java/capstone/TMS320C64x_const.java000064400000000000000000000331350072674642500241500ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class TMS320C64x_const { public static final int TMS320C64X_OP_INVALID = 0; public static final int TMS320C64X_OP_REG = 1; public static final int TMS320C64X_OP_IMM = 2; public static final int TMS320C64X_OP_MEM = 3; public static final int TMS320C64X_OP_REGPAIR = 64; public static final int TMS320C64X_MEM_DISP_INVALID = 0; public static final int TMS320C64X_MEM_DISP_CONSTANT = 1; public static final int TMS320C64X_MEM_DISP_REGISTER = 2; public static final int TMS320C64X_MEM_DIR_INVALID = 0; public static final int TMS320C64X_MEM_DIR_FW = 1; public static final int TMS320C64X_MEM_DIR_BW = 2; public static final int TMS320C64X_MEM_MOD_INVALID = 0; public static final int TMS320C64X_MEM_MOD_NO = 1; public static final int TMS320C64X_MEM_MOD_PRE = 2; public static final int TMS320C64X_MEM_MOD_POST = 3; public static final int TMS320C64X_REG_INVALID = 0; public static final int TMS320C64X_REG_AMR = 1; public static final int TMS320C64X_REG_CSR = 2; public static final int TMS320C64X_REG_DIER = 3; public static final int TMS320C64X_REG_DNUM = 4; public static final int TMS320C64X_REG_ECR = 5; public static final int TMS320C64X_REG_GFPGFR = 6; public static final int TMS320C64X_REG_GPLYA = 7; public static final int TMS320C64X_REG_GPLYB = 8; public static final int TMS320C64X_REG_ICR = 9; public static final int TMS320C64X_REG_IER = 10; public static final int TMS320C64X_REG_IERR = 11; public static final int TMS320C64X_REG_ILC = 12; public static final int TMS320C64X_REG_IRP = 13; public static final int TMS320C64X_REG_ISR = 14; public static final int TMS320C64X_REG_ISTP = 15; public static final int TMS320C64X_REG_ITSR = 16; public static final int TMS320C64X_REG_NRP = 17; public static final int TMS320C64X_REG_NTSR = 18; public static final int TMS320C64X_REG_REP = 19; public static final int TMS320C64X_REG_RILC = 20; public static final int TMS320C64X_REG_SSR = 21; public static final int TMS320C64X_REG_TSCH = 22; public static final int TMS320C64X_REG_TSCL = 23; public static final int TMS320C64X_REG_TSR = 24; public static final int TMS320C64X_REG_A0 = 25; public static final int TMS320C64X_REG_A1 = 26; public static final int TMS320C64X_REG_A2 = 27; public static final int TMS320C64X_REG_A3 = 28; public static final int TMS320C64X_REG_A4 = 29; public static final int TMS320C64X_REG_A5 = 30; public static final int TMS320C64X_REG_A6 = 31; public static final int TMS320C64X_REG_A7 = 32; public static final int TMS320C64X_REG_A8 = 33; public static final int TMS320C64X_REG_A9 = 34; public static final int TMS320C64X_REG_A10 = 35; public static final int TMS320C64X_REG_A11 = 36; public static final int TMS320C64X_REG_A12 = 37; public static final int TMS320C64X_REG_A13 = 38; public static final int TMS320C64X_REG_A14 = 39; public static final int TMS320C64X_REG_A15 = 40; public static final int TMS320C64X_REG_A16 = 41; public static final int TMS320C64X_REG_A17 = 42; public static final int TMS320C64X_REG_A18 = 43; public static final int TMS320C64X_REG_A19 = 44; public static final int TMS320C64X_REG_A20 = 45; public static final int TMS320C64X_REG_A21 = 46; public static final int TMS320C64X_REG_A22 = 47; public static final int TMS320C64X_REG_A23 = 48; public static final int TMS320C64X_REG_A24 = 49; public static final int TMS320C64X_REG_A25 = 50; public static final int TMS320C64X_REG_A26 = 51; public static final int TMS320C64X_REG_A27 = 52; public static final int TMS320C64X_REG_A28 = 53; public static final int TMS320C64X_REG_A29 = 54; public static final int TMS320C64X_REG_A30 = 55; public static final int TMS320C64X_REG_A31 = 56; public static final int TMS320C64X_REG_B0 = 57; public static final int TMS320C64X_REG_B1 = 58; public static final int TMS320C64X_REG_B2 = 59; public static final int TMS320C64X_REG_B3 = 60; public static final int TMS320C64X_REG_B4 = 61; public static final int TMS320C64X_REG_B5 = 62; public static final int TMS320C64X_REG_B6 = 63; public static final int TMS320C64X_REG_B7 = 64; public static final int TMS320C64X_REG_B8 = 65; public static final int TMS320C64X_REG_B9 = 66; public static final int TMS320C64X_REG_B10 = 67; public static final int TMS320C64X_REG_B11 = 68; public static final int TMS320C64X_REG_B12 = 69; public static final int TMS320C64X_REG_B13 = 70; public static final int TMS320C64X_REG_B14 = 71; public static final int TMS320C64X_REG_B15 = 72; public static final int TMS320C64X_REG_B16 = 73; public static final int TMS320C64X_REG_B17 = 74; public static final int TMS320C64X_REG_B18 = 75; public static final int TMS320C64X_REG_B19 = 76; public static final int TMS320C64X_REG_B20 = 77; public static final int TMS320C64X_REG_B21 = 78; public static final int TMS320C64X_REG_B22 = 79; public static final int TMS320C64X_REG_B23 = 80; public static final int TMS320C64X_REG_B24 = 81; public static final int TMS320C64X_REG_B25 = 82; public static final int TMS320C64X_REG_B26 = 83; public static final int TMS320C64X_REG_B27 = 84; public static final int TMS320C64X_REG_B28 = 85; public static final int TMS320C64X_REG_B29 = 86; public static final int TMS320C64X_REG_B30 = 87; public static final int TMS320C64X_REG_B31 = 88; public static final int TMS320C64X_REG_PCE1 = 89; public static final int TMS320C64X_REG_ENDING = 90; public static final int TMS320C64X_REG_EFR = TMS320C64X_REG_ECR; public static final int TMS320C64X_REG_IFR = TMS320C64X_REG_ISR; public static final int TMS320C64X_INS_INVALID = 0; public static final int TMS320C64X_INS_ABS = 1; public static final int TMS320C64X_INS_ABS2 = 2; public static final int TMS320C64X_INS_ADD = 3; public static final int TMS320C64X_INS_ADD2 = 4; public static final int TMS320C64X_INS_ADD4 = 5; public static final int TMS320C64X_INS_ADDAB = 6; public static final int TMS320C64X_INS_ADDAD = 7; public static final int TMS320C64X_INS_ADDAH = 8; public static final int TMS320C64X_INS_ADDAW = 9; public static final int TMS320C64X_INS_ADDK = 10; public static final int TMS320C64X_INS_ADDKPC = 11; public static final int TMS320C64X_INS_ADDU = 12; public static final int TMS320C64X_INS_AND = 13; public static final int TMS320C64X_INS_ANDN = 14; public static final int TMS320C64X_INS_AVG2 = 15; public static final int TMS320C64X_INS_AVGU4 = 16; public static final int TMS320C64X_INS_B = 17; public static final int TMS320C64X_INS_BDEC = 18; public static final int TMS320C64X_INS_BITC4 = 19; public static final int TMS320C64X_INS_BNOP = 20; public static final int TMS320C64X_INS_BPOS = 21; public static final int TMS320C64X_INS_CLR = 22; public static final int TMS320C64X_INS_CMPEQ = 23; public static final int TMS320C64X_INS_CMPEQ2 = 24; public static final int TMS320C64X_INS_CMPEQ4 = 25; public static final int TMS320C64X_INS_CMPGT = 26; public static final int TMS320C64X_INS_CMPGT2 = 27; public static final int TMS320C64X_INS_CMPGTU4 = 28; public static final int TMS320C64X_INS_CMPLT = 29; public static final int TMS320C64X_INS_CMPLTU = 30; public static final int TMS320C64X_INS_DEAL = 31; public static final int TMS320C64X_INS_DOTP2 = 32; public static final int TMS320C64X_INS_DOTPN2 = 33; public static final int TMS320C64X_INS_DOTPNRSU2 = 34; public static final int TMS320C64X_INS_DOTPRSU2 = 35; public static final int TMS320C64X_INS_DOTPSU4 = 36; public static final int TMS320C64X_INS_DOTPU4 = 37; public static final int TMS320C64X_INS_EXT = 38; public static final int TMS320C64X_INS_EXTU = 39; public static final int TMS320C64X_INS_GMPGTU = 40; public static final int TMS320C64X_INS_GMPY4 = 41; public static final int TMS320C64X_INS_LDB = 42; public static final int TMS320C64X_INS_LDBU = 43; public static final int TMS320C64X_INS_LDDW = 44; public static final int TMS320C64X_INS_LDH = 45; public static final int TMS320C64X_INS_LDHU = 46; public static final int TMS320C64X_INS_LDNDW = 47; public static final int TMS320C64X_INS_LDNW = 48; public static final int TMS320C64X_INS_LDW = 49; public static final int TMS320C64X_INS_LMBD = 50; public static final int TMS320C64X_INS_MAX2 = 51; public static final int TMS320C64X_INS_MAXU4 = 52; public static final int TMS320C64X_INS_MIN2 = 53; public static final int TMS320C64X_INS_MINU4 = 54; public static final int TMS320C64X_INS_MPY = 55; public static final int TMS320C64X_INS_MPY2 = 56; public static final int TMS320C64X_INS_MPYH = 57; public static final int TMS320C64X_INS_MPYHI = 58; public static final int TMS320C64X_INS_MPYHIR = 59; public static final int TMS320C64X_INS_MPYHL = 60; public static final int TMS320C64X_INS_MPYHLU = 61; public static final int TMS320C64X_INS_MPYHSLU = 62; public static final int TMS320C64X_INS_MPYHSU = 63; public static final int TMS320C64X_INS_MPYHU = 64; public static final int TMS320C64X_INS_MPYHULS = 65; public static final int TMS320C64X_INS_MPYHUS = 66; public static final int TMS320C64X_INS_MPYLH = 67; public static final int TMS320C64X_INS_MPYLHU = 68; public static final int TMS320C64X_INS_MPYLI = 69; public static final int TMS320C64X_INS_MPYLIR = 70; public static final int TMS320C64X_INS_MPYLSHU = 71; public static final int TMS320C64X_INS_MPYLUHS = 72; public static final int TMS320C64X_INS_MPYSU = 73; public static final int TMS320C64X_INS_MPYSU4 = 74; public static final int TMS320C64X_INS_MPYU = 75; public static final int TMS320C64X_INS_MPYU4 = 76; public static final int TMS320C64X_INS_MPYUS = 77; public static final int TMS320C64X_INS_MVC = 78; public static final int TMS320C64X_INS_MVD = 79; public static final int TMS320C64X_INS_MVK = 80; public static final int TMS320C64X_INS_MVKL = 81; public static final int TMS320C64X_INS_MVKLH = 82; public static final int TMS320C64X_INS_NOP = 83; public static final int TMS320C64X_INS_NORM = 84; public static final int TMS320C64X_INS_OR = 85; public static final int TMS320C64X_INS_PACK2 = 86; public static final int TMS320C64X_INS_PACKH2 = 87; public static final int TMS320C64X_INS_PACKH4 = 88; public static final int TMS320C64X_INS_PACKHL2 = 89; public static final int TMS320C64X_INS_PACKL4 = 90; public static final int TMS320C64X_INS_PACKLH2 = 91; public static final int TMS320C64X_INS_ROTL = 92; public static final int TMS320C64X_INS_SADD = 93; public static final int TMS320C64X_INS_SADD2 = 94; public static final int TMS320C64X_INS_SADDU4 = 95; public static final int TMS320C64X_INS_SADDUS2 = 96; public static final int TMS320C64X_INS_SAT = 97; public static final int TMS320C64X_INS_SET = 98; public static final int TMS320C64X_INS_SHFL = 99; public static final int TMS320C64X_INS_SHL = 100; public static final int TMS320C64X_INS_SHLMB = 101; public static final int TMS320C64X_INS_SHR = 102; public static final int TMS320C64X_INS_SHR2 = 103; public static final int TMS320C64X_INS_SHRMB = 104; public static final int TMS320C64X_INS_SHRU = 105; public static final int TMS320C64X_INS_SHRU2 = 106; public static final int TMS320C64X_INS_SMPY = 107; public static final int TMS320C64X_INS_SMPY2 = 108; public static final int TMS320C64X_INS_SMPYH = 109; public static final int TMS320C64X_INS_SMPYHL = 110; public static final int TMS320C64X_INS_SMPYLH = 111; public static final int TMS320C64X_INS_SPACK2 = 112; public static final int TMS320C64X_INS_SPACKU4 = 113; public static final int TMS320C64X_INS_SSHL = 114; public static final int TMS320C64X_INS_SSHVL = 115; public static final int TMS320C64X_INS_SSHVR = 116; public static final int TMS320C64X_INS_SSUB = 117; public static final int TMS320C64X_INS_STB = 118; public static final int TMS320C64X_INS_STDW = 119; public static final int TMS320C64X_INS_STH = 120; public static final int TMS320C64X_INS_STNDW = 121; public static final int TMS320C64X_INS_STNW = 122; public static final int TMS320C64X_INS_STW = 123; public static final int TMS320C64X_INS_SUB = 124; public static final int TMS320C64X_INS_SUB2 = 125; public static final int TMS320C64X_INS_SUB4 = 126; public static final int TMS320C64X_INS_SUBAB = 127; public static final int TMS320C64X_INS_SUBABS4 = 128; public static final int TMS320C64X_INS_SUBAH = 129; public static final int TMS320C64X_INS_SUBAW = 130; public static final int TMS320C64X_INS_SUBC = 131; public static final int TMS320C64X_INS_SUBU = 132; public static final int TMS320C64X_INS_SWAP4 = 133; public static final int TMS320C64X_INS_UNPKHU4 = 134; public static final int TMS320C64X_INS_UNPKLU4 = 135; public static final int TMS320C64X_INS_XOR = 136; public static final int TMS320C64X_INS_XPND2 = 137; public static final int TMS320C64X_INS_XPND4 = 138; public static final int TMS320C64X_INS_IDLE = 139; public static final int TMS320C64X_INS_MV = 140; public static final int TMS320C64X_INS_NEG = 141; public static final int TMS320C64X_INS_NOT = 142; public static final int TMS320C64X_INS_SWAP2 = 143; public static final int TMS320C64X_INS_ZERO = 144; public static final int TMS320C64X_INS_ENDING = 145; public static final int TMS320C64X_GRP_INVALID = 0; public static final int TMS320C64X_GRP_JUMP = 1; public static final int TMS320C64X_GRP_FUNIT_D = 128; public static final int TMS320C64X_GRP_FUNIT_L = 129; public static final int TMS320C64X_GRP_FUNIT_M = 130; public static final int TMS320C64X_GRP_FUNIT_S = 131; public static final int TMS320C64X_GRP_FUNIT_NO = 132; public static final int TMS320C64X_GRP_ENDING = 133; public static final int TMS320C64X_FUNIT_INVALID = 0; public static final int TMS320C64X_FUNIT_D = 1; public static final int TMS320C64X_FUNIT_L = 2; public static final int TMS320C64X_FUNIT_M = 3; public static final int TMS320C64X_FUNIT_S = 4; public static final int TMS320C64X_FUNIT_NO = 5; }capstone-sys-0.15.0/capstone/bindings/java/capstone/Wasm_const.java000064400000000000000000000231060072674642500235170ustar 00000000000000// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT package capstone; public class Wasm_const { public static final int WASM_OP_INVALID = 0; public static final int WASM_OP_NONE = 1; public static final int WASM_OP_INT7 = 2; public static final int WASM_OP_VARUINT32 = 3; public static final int WASM_OP_VARUINT64 = 4; public static final int WASM_OP_UINT32 = 5; public static final int WASM_OP_UINT64 = 6; public static final int WASM_OP_IMM = 7; public static final int WASM_OP_BRTABLE = 8; public static final int WASM_INS_UNREACHABLE = 0x0; public static final int WASM_INS_NOP = 0x1; public static final int WASM_INS_BLOCK = 0x2; public static final int WASM_INS_LOOP = 0x3; public static final int WASM_INS_IF = 0x4; public static final int WASM_INS_ELSE = 0x5; public static final int WASM_INS_END = 0xb; public static final int WASM_INS_BR = 0xc; public static final int WASM_INS_BR_IF = 0xd; public static final int WASM_INS_BR_TABLE = 0xe; public static final int WASM_INS_RETURN = 0xf; public static final int WASM_INS_CALL = 0x10; public static final int WASM_INS_CALL_INDIRECT = 0x11; public static final int WASM_INS_DROP = 0x1a; public static final int WASM_INS_SELECT = 0x1b; public static final int WASM_INS_GET_LOCAL = 0x20; public static final int WASM_INS_SET_LOCAL = 0x21; public static final int WASM_INS_TEE_LOCAL = 0x22; public static final int WASM_INS_GET_GLOBAL = 0x23; public static final int WASM_INS_SET_GLOBAL = 0x24; public static final int WASM_INS_I32_LOAD = 0x28; public static final int WASM_INS_I64_LOAD = 0x29; public static final int WASM_INS_F32_LOAD = 0x2a; public static final int WASM_INS_F64_LOAD = 0x2b; public static final int WASM_INS_I32_LOAD8_S = 0x2c; public static final int WASM_INS_I32_LOAD8_U = 0x2d; public static final int WASM_INS_I32_LOAD16_S = 0x2e; public static final int WASM_INS_I32_LOAD16_U = 0x2f; public static final int WASM_INS_I64_LOAD8_S = 0x30; public static final int WASM_INS_I64_LOAD8_U = 0x31; public static final int WASM_INS_I64_LOAD16_S = 0x32; public static final int WASM_INS_I64_LOAD16_U = 0x33; public static final int WASM_INS_I64_LOAD32_S = 0x34; public static final int WASM_INS_I64_LOAD32_U = 0x35; public static final int WASM_INS_I32_STORE = 0x36; public static final int WASM_INS_I64_STORE = 0x37; public static final int WASM_INS_F32_STORE = 0x38; public static final int WASM_INS_F64_STORE = 0x39; public static final int WASM_INS_I32_STORE8 = 0x3a; public static final int WASM_INS_I32_STORE16 = 0x3b; public static final int WASM_INS_I64_STORE8 = 0x3c; public static final int WASM_INS_I64_STORE16 = 0x3d; public static final int WASM_INS_I64_STORE32 = 0x3e; public static final int WASM_INS_CURRENT_MEMORY = 0x3f; public static final int WASM_INS_GROW_MEMORY = 0x40; public static final int WASM_INS_I32_CONST = 0x41; public static final int WASM_INS_I64_CONST = 0x42; public static final int WASM_INS_F32_CONST = 0x43; public static final int WASM_INS_F64_CONST = 0x44; public static final int WASM_INS_I32_EQZ = 0x45; public static final int WASM_INS_I32_EQ = 0x46; public static final int WASM_INS_I32_NE = 0x47; public static final int WASM_INS_I32_LT_S = 0x48; public static final int WASM_INS_I32_LT_U = 0x49; public static final int WASM_INS_I32_GT_S = 0x4a; public static final int WASM_INS_I32_GT_U = 0x4b; public static final int WASM_INS_I32_LE_S = 0x4c; public static final int WASM_INS_I32_LE_U = 0x4d; public static final int WASM_INS_I32_GE_S = 0x4e; public static final int WASM_INS_I32_GE_U = 0x4f; public static final int WASM_INS_I64_EQZ = 0x50; public static final int WASM_INS_I64_EQ = 0x51; public static final int WASM_INS_I64_NE = 0x52; public static final int WASM_INS_I64_LT_S = 0x53; public static final int WASM_INS_I64_LT_U = 0x54; public static final int WASM_INS_I64_GT_U = 0x56; public static final int WASM_INS_I64_LE_S = 0x57; public static final int WASM_INS_I64_LE_U = 0x58; public static final int WASM_INS_I64_GE_S = 0x59; public static final int WASM_INS_I64_GE_U = 0x5a; public static final int WASM_INS_F32_EQ = 0x5b; public static final int WASM_INS_F32_NE = 0x5c; public static final int WASM_INS_F32_LT = 0x5d; public static final int WASM_INS_F32_GT = 0x5e; public static final int WASM_INS_F32_LE = 0x5f; public static final int WASM_INS_F32_GE = 0x60; public static final int WASM_INS_F64_EQ = 0x61; public static final int WASM_INS_F64_NE = 0x62; public static final int WASM_INS_F64_LT = 0x63; public static final int WASM_INS_F64_GT = 0x64; public static final int WASM_INS_F64_LE = 0x65; public static final int WASM_INS_F64_GE = 0x66; public static final int WASM_INS_I32_CLZ = 0x67; public static final int WASM_INS_I32_CTZ = 0x68; public static final int WASM_INS_I32_POPCNT = 0x69; public static final int WASM_INS_I32_ADD = 0x6a; public static final int WASM_INS_I32_SUB = 0x6b; public static final int WASM_INS_I32_MUL = 0x6c; public static final int WASM_INS_I32_DIV_S = 0x6d; public static final int WASM_INS_I32_DIV_U = 0x6e; public static final int WASM_INS_I32_REM_S = 0x6f; public static final int WASM_INS_I32_REM_U = 0x70; public static final int WASM_INS_I32_AND = 0x71; public static final int WASM_INS_I32_OR = 0x72; public static final int WASM_INS_I32_XOR = 0x73; public static final int WASM_INS_I32_SHL = 0x74; public static final int WASM_INS_I32_SHR_S = 0x75; public static final int WASM_INS_I32_SHR_U = 0x76; public static final int WASM_INS_I32_ROTL = 0x77; public static final int WASM_INS_I32_ROTR = 0x78; public static final int WASM_INS_I64_CLZ = 0x79; public static final int WASM_INS_I64_CTZ = 0x7a; public static final int WASM_INS_I64_POPCNT = 0x7b; public static final int WASM_INS_I64_ADD = 0x7c; public static final int WASM_INS_I64_SUB = 0x7d; public static final int WASM_INS_I64_MUL = 0x7e; public static final int WASM_INS_I64_DIV_S = 0x7f; public static final int WASM_INS_I64_DIV_U = 0x80; public static final int WASM_INS_I64_REM_S = 0x81; public static final int WASM_INS_I64_REM_U = 0x82; public static final int WASM_INS_I64_AND = 0x83; public static final int WASM_INS_I64_OR = 0x84; public static final int WASM_INS_I64_XOR = 0x85; public static final int WASM_INS_I64_SHL = 0x86; public static final int WASM_INS_I64_SHR_S = 0x87; public static final int WASM_INS_I64_SHR_U = 0x88; public static final int WASM_INS_I64_ROTL = 0x89; public static final int WASM_INS_I64_ROTR = 0x8a; public static final int WASM_INS_F32_ABS = 0x8b; public static final int WASM_INS_F32_NEG = 0x8c; public static final int WASM_INS_F32_CEIL = 0x8d; public static final int WASM_INS_F32_FLOOR = 0x8e; public static final int WASM_INS_F32_TRUNC = 0x8f; public static final int WASM_INS_F32_NEAREST = 0x90; public static final int WASM_INS_F32_SQRT = 0x91; public static final int WASM_INS_F32_ADD = 0x92; public static final int WASM_INS_F32_SUB = 0x93; public static final int WASM_INS_F32_MUL = 0x94; public static final int WASM_INS_F32_DIV = 0x95; public static final int WASM_INS_F32_MIN = 0x96; public static final int WASM_INS_F32_MAX = 0x97; public static final int WASM_INS_F32_COPYSIGN = 0x98; public static final int WASM_INS_F64_ABS = 0x99; public static final int WASM_INS_F64_NEG = 0x9a; public static final int WASM_INS_F64_CEIL = 0x9b; public static final int WASM_INS_F64_FLOOR = 0x9c; public static final int WASM_INS_F64_TRUNC = 0x9d; public static final int WASM_INS_F64_NEAREST = 0x9e; public static final int WASM_INS_F64_SQRT = 0x9f; public static final int WASM_INS_F64_ADD = 0xa0; public static final int WASM_INS_F64_SUB = 0xa1; public static final int WASM_INS_F64_MUL = 0xa2; public static final int WASM_INS_F64_DIV = 0xa3; public static final int WASM_INS_F64_MIN = 0xa4; public static final int WASM_INS_F64_MAX = 0xa5; public static final int WASM_INS_F64_COPYSIGN = 0xa6; public static final int WASM_INS_I32_WARP_I64 = 0xa7; public static final int WASM_INS_I32_TRUNC_U_F32 = 0xa9; public static final int WASM_INS_I32_TRUNC_S_F64 = 0xaa; public static final int WASM_INS_I32_TRUNC_U_F64 = 0xab; public static final int WASM_INS_I64_EXTEND_S_I32 = 0xac; public static final int WASM_INS_I64_EXTEND_U_I32 = 0xad; public static final int WASM_INS_I64_TRUNC_S_F32 = 0xae; public static final int WASM_INS_I64_TRUNC_U_F32 = 0xaf; public static final int WASM_INS_I64_TRUNC_S_F64 = 0xb0; public static final int WASM_INS_I64_TRUNC_U_F64 = 0xb1; public static final int WASM_INS_F32_CONVERT_S_I32 = 0xb2; public static final int WASM_INS_F32_CONVERT_U_I32 = 0xb3; public static final int WASM_INS_F32_CONVERT_S_I64 = 0xb4; public static final int WASM_INS_F32_CONVERT_U_I64 = 0xb5; public static final int WASM_INS_F32_DEMOTE_F64 = 0xb6; public static final int WASM_INS_F64_CONVERT_S_I32 = 0xb7; public static final int WASM_INS_F64_CONVERT_U_I32 = 0xb8; public static final int WASM_INS_F64_CONVERT_S_I64 = 0xb9; public static final int WASM_INS_F64_CONVERT_U_I64 = 0xba; public static final int WASM_INS_F64_PROMOTE_F32 = 0xbb; public static final int WASM_INS_I32_REINTERPRET_F32 = 0xbc; public static final int WASM_INS_I64_REINTERPRET_F64 = 0xbd; public static final int WASM_INS_F32_REINTERPRET_I32 = 0xbe; public static final int WASM_INS_F64_REINTERPRET_I64 = 0xbf; public static final int WASM_INS_INVALID = 512; public static final int WASM_INS_ENDING = 513; public static final int WASM_GRP_INVALID = 0; public static final int WASM_GRP_NUMBERIC = 8; public static final int WASM_GRP_PARAMETRIC = 9; public static final int WASM_GRP_VARIABLE = 10; public static final int WASM_GRP_MEMORY = 11; public static final int WASM_GRP_CONTROL = 12; public static final int WASM_GRP_ENDING = 13; }capstone-sys-0.15.0/capstone/bindings/java/capstone/X86.java000064400000000000000000000074670072674642500220030ustar 00000000000000// Capstone Java binding // By Nguyen Anh Quynh & Dang Hoang Vu, 2013 package capstone; import com.sun.jna.Structure; import com.sun.jna.Union; import java.util.List; import java.util.Arrays; import static capstone.X86_const.*; public class X86 { public static class MemType extends Structure { public int segment; public int base; public int index; public int scale; public long disp; @Override public List getFieldOrder() { return Arrays.asList("segment", "base", "index", "scale", "disp"); } } public static class Encoding extends Structure { public byte modrmOffset; public byte dispOffset; public byte dispSize; public byte immOffset; public byte immSize; @Override public List getFieldOrder() { return Arrays.asList("modrmOffset", "dispOffset", "dispSize", "immOffset", "immSize"); } } public static class OpValue extends Union { public int reg; public long imm; public MemType mem; @Override public List getFieldOrder() { return Arrays.asList("reg", "imm", "mem"); } } public static class Operand extends Structure { public int type; public OpValue value; public byte size; public byte access; public int avx_bcast; public boolean avx_zero_opmask; public void read() { super.read(); if (type == X86_OP_MEM) value.setType(MemType.class); if (type == X86_OP_IMM) value.setType(Long.TYPE); if (type == X86_OP_REG) value.setType(Integer.TYPE); if (type == X86_OP_INVALID) return; readField("value"); } @Override public List getFieldOrder() { return Arrays.asList("type", "value", "size", "access", "avx_bcast", "avx_zero_opmask"); } } public static class UnionOpInfo extends Capstone.UnionOpInfo { public byte [] prefix; public byte [] opcode; public byte rex; public byte addr_size; public byte modrm; public byte sib; public long disp; public int sib_index; public byte sib_scale; public int sib_base; public int xop_cc; public int sse_cc; public int avx_cc; public byte avx_sae; public int avx_rm; public long eflags; public byte op_count; public Operand [] op; public Encoding encoding; public UnionOpInfo() { op = new Operand[8]; opcode = new byte[4]; prefix = new byte[4]; } @Override public List getFieldOrder() { return Arrays.asList("prefix", "opcode", "rex", "addr_size", "modrm", "sib", "disp", "sib_index", "sib_scale", "sib_base", "xop_cc", "sse_cc", "avx_cc", "avx_sae", "avx_rm", "eflags", "op_count", "op", "encoding"); } } public static class OpInfo extends Capstone.OpInfo { public byte [] prefix; public byte [] opcode; public byte opSize; public byte rex; public byte addrSize; public byte dispSize; public byte immSize; public byte modrm; public byte sib; public long disp; public int sibIndex; public byte sibScale; public int sibBase; public int xopCC; public int sseCC; public int avxCC; public boolean avxSae; public int avxRm; public long eflags; public Operand[] op; public Encoding encoding; public OpInfo(UnionOpInfo e) { prefix = e.prefix; opcode = e.opcode; rex = e.rex; addrSize = e.addr_size; modrm = e.modrm; sib = e.sib; disp = e.disp; sibIndex = e.sib_index; sibScale = e.sib_scale; sibBase = e.sib_base; xopCC = e.xop_cc; sseCC = e.sse_cc; avxCC = e.avx_cc; avxSae = e.avx_sae > 0; avxRm = e.avx_rm; eflags = e.eflags; op = new Operand[e.op_count]; for (int i=0; i, 2013-2015 LIB = capstone FLAGS = '-Wall -Wextra -Wwrite-strings' PYTHON2 ?= python all: arm_const.cmxa arm64_const.cmxa m680x_const.cmxa mips_const.cmxa ppc_const.cmxa sparc_const.cmxa sysz_const.cmxa x86_const.cmxa xcore_const.cmxa arm.cmxa arm64.cmxa m680x.cmxa mips.cmxa ppc.cmxa x86.cmxa sparc.cmxa systemz.cmxa xcore.cmxa capstone.cmxa test_basic.cmx test_detail.cmx test_x86.cmx test_arm.cmx test_arm64.cmx test_mips.cmx test_ppc.cmx test_sparc.cmx test_systemz.cmx test_xcore.cmx test_m680x.cmx ocaml.o ocamlopt -o test_basic -ccopt $(FLAGS) ocaml.o capstone.cmx test_basic.cmx -cclib -l$(LIB) ocamlopt -o test_detail -ccopt $(FLAGS) capstone.cmx ocaml.o test_detail.cmx -cclib -l$(LIB) ocamlopt -o test_x86 -ccopt $(FLAGS) capstone.cmx ocaml.o x86.cmx x86_const.cmx test_x86.cmx -cclib -l$(LIB) ocamlopt -o test_arm -ccopt $(FLAGS) capstone.cmx ocaml.o arm.cmx arm_const.cmx test_arm.cmx -cclib -l$(LIB) ocamlopt -o test_arm64 -ccopt $(FLAGS) capstone.cmx ocaml.o arm64.cmx arm64_const.cmx test_arm64.cmx -cclib -l$(LIB) ocamlopt -o test_mips -ccopt $(FLAGS) capstone.cmx ocaml.o mips.cmx mips_const.cmx test_mips.cmx -cclib -l$(LIB) ocamlopt -o test_ppc -ccopt $(FLAGS) capstone.cmx ocaml.o ppc.cmx ppc_const.cmx test_ppc.cmx -cclib -l$(LIB) ocamlopt -o test_sparc -ccopt $(FLAGS) capstone.cmx ocaml.o sparc.cmx sparc_const.cmx test_sparc.cmx -cclib -l$(LIB) ocamlopt -o test_systemz -ccopt $(FLAGS) capstone.cmx ocaml.o systemz.cmx sysz_const.cmx test_systemz.cmx -cclib -l$(LIB) ocamlopt -o test_xcore -ccopt $(FLAGS) capstone.cmx ocaml.o xcore.cmx xcore_const.cmx test_xcore.cmx -cclib -l$(LIB) ocamlopt -o test_m680x -ccopt $(FLAGS) capstone.cmx ocaml.o m680x.cmx m680x_const.cmx test_m680x.cmx -cclib -l$(LIB) test_basic.cmx: test_basic.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_detail.cmx: test_detail.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_x86.cmx: test_x86.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_arm.cmx: test_arm.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_arm64.cmx: test_arm64.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_mips.cmx: test_mips.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_ppc.cmx: test_ppc.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_sparc.cmx: test_sparc.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_systemz.cmx: test_systemz.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_xcore.cmx: test_xcore.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) test_m680x.cmx: test_m680x.ml ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) ocaml.o: ocaml.c ocamlc -ccopt $(FLAGS) -c $< capstone.mli: capstone.ml ocamlc -ccopt $(FLAGS) -i $< > $@ capstone.cmi: capstone.mli ocamlc -ccopt $(FLAGS) -c $< capstone.cmx: capstone.ml capstone.cmi ocamlopt -ccopt $(FLAGS) -c $< -cclib -l$(LIB) capstone.cmxa: capstone.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< -cclib -lsb_ocaml -cclib -l$(LIB) x86.mli: x86.ml ocamlc -ccopt $(FLAGS) -i $< > $@ x86.cmi: x86.mli ocamlc -ccopt $(FLAGS) -c $< x86.cmx: x86.ml x86.cmi ocamlopt -ccopt $(FLAGS) -c $< x86.cmxa: x86.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< x86_const.mli: x86_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ x86_const.cmi: x86_const.mli ocamlc -ccopt $(FLAGS) -c $< x86_const.cmx: x86_const.ml x86_const.cmi ocamlopt -ccopt $(FLAGS) -c $< x86_const.cmxa: x86_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< arm.mli: arm.ml ocamlc -ccopt $(FLAGS) -i $< > $@ arm.cmi: arm.mli ocamlc -ccopt $(FLAGS) -c $< arm.cmx: arm.ml arm.cmi ocamlopt -ccopt $(FLAGS) -c $< arm.cmxa: arm.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< arm_const.mli: arm_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ arm_const.cmi: arm_const.mli ocamlc -ccopt $(FLAGS) -c $< arm_const.cmx: arm_const.ml arm_const.cmi ocamlopt -ccopt $(FLAGS) -c $< arm_const.cmxa: arm_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< arm64.mli: arm64.ml ocamlc -ccopt $(FLAGS) -i $< > $@ arm64.cmi: arm64.mli ocamlc -ccopt $(FLAGS) -c $< arm64.cmx: arm64.ml arm64.cmi ocamlopt -ccopt $(FLAGS) -c $< arm64.cmxa: arm64.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< arm64_const.mli: arm64_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ arm64_const.cmi: arm64_const.mli ocamlc -ccopt $(FLAGS) -c $< arm64_const.cmx: arm64_const.ml arm64_const.cmi ocamlopt -ccopt $(FLAGS) -c $< arm64_const.cmxa: arm64_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< m680x.mli: m680x.ml ocamlc -ccopt $(FLAGS) -i $< > $@ m680x.cmi: m680x.mli ocamlc -ccopt $(FLAGS) -c $< m680x.cmx: m680x.ml m680x.cmi ocamlopt -ccopt $(FLAGS) -c $< m680x.cmxa: m680x.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< m680x_const.mli: m680x_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ m680x_const.cmi: m680x_const.mli ocamlc -ccopt $(FLAGS) -c $< m680x_const.cmx: m680x_const.ml m680x_const.cmi ocamlopt -ccopt $(FLAGS) -c $< m680x_const.cmxa: m680x_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< mips.mli: mips.ml ocamlc -ccopt $(FLAGS) -i $< > $@ mips.cmi: mips.mli ocamlc -ccopt $(FLAGS) -c $< mips.cmx: mips.ml mips.cmi ocamlopt -ccopt $(FLAGS) -c $< mips.cmxa: mips.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< mips_const.mli: mips_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ mips_const.cmi: mips_const.mli ocamlc -ccopt $(FLAGS) -c $< mips_const.cmx: mips_const.ml mips_const.cmi ocamlopt -ccopt $(FLAGS) -c $< mips_const.cmxa: mips_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< ppc.mli: ppc.ml ocamlc -ccopt $(FLAGS) -i $< > $@ ppc.cmi: ppc.mli ocamlc -ccopt $(FLAGS) -c $< ppc.cmx: ppc.ml ppc.cmi ocamlopt -ccopt $(FLAGS) -c $< ppc.cmxa: ppc.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< ppc_const.mli: ppc_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ ppc_const.cmi: ppc_const.mli ocamlc -ccopt $(FLAGS) -c $< ppc_const.cmx: ppc_const.ml ppc_const.cmi ocamlopt -ccopt $(FLAGS) -c $< ppc_const.cmxa: ppc_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< sparc.mli: sparc.ml ocamlc -ccopt $(FLAGS) -i $< > $@ sparc.cmi: sparc.mli ocamlc -ccopt $(FLAGS) -c $< sparc.cmx: sparc.ml sparc.cmi ocamlopt -ccopt $(FLAGS) -c $< sparc.cmxa: sparc.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< sparc_const.mli: sparc_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ sparc_const.cmi: sparc_const.mli ocamlc -ccopt $(FLAGS) -c $< sparc_const.cmx: sparc_const.ml sparc_const.cmi ocamlopt -ccopt $(FLAGS) -c $< sparc_const.cmxa: sparc_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< systemz.mli: systemz.ml ocamlc -ccopt $(FLAGS) -i $< > $@ systemz.cmi: systemz.mli ocamlc -ccopt $(FLAGS) -c $< systemz.cmx: systemz.ml systemz.cmi ocamlopt -ccopt $(FLAGS) -c $< systemz.cmxa: systemz.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< sysz_const.mli: sysz_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ sysz_const.cmi: sysz_const.mli ocamlc -ccopt $(FLAGS) -c $< sysz_const.cmx: sysz_const.ml sysz_const.cmi ocamlopt -ccopt $(FLAGS) -c $< sysz_const.cmxa: sysz_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< xcore.mli: xcore.ml ocamlc -ccopt $(FLAGS) -i $< > $@ xcore.cmi: xcore.mli ocamlc -ccopt $(FLAGS) -c $< xcore.cmx: xcore.ml xcore.cmi ocamlopt -ccopt $(FLAGS) -c $< xcore.cmxa: xcore.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< xcore_const.mli: xcore_const.ml ocamlc -ccopt $(FLAGS) -i $< > $@ xcore_const.cmi: xcore_const.mli ocamlc -ccopt $(FLAGS) -c $< xcore_const.cmx: xcore_const.ml xcore_const.cmi ocamlopt -ccopt $(FLAGS) -c $< xcore_const.cmxa: xcore_const.cmx ocamlopt -ccopt $(FLAGS) -a -o $@ $< clean: rm -f *.[oa] *.so *.cm[ixoa] *.cmxa *.mli test_basic test_detail test_x86 test_arm test_arm64 test_mips test_ppc test_sparc test_systemz test_xcore test_m680x gen_const: cd .. && $(PYTHON2) const_generator.py ocaml TESTS = test_basic test_detail test_arm test_arm64 test_m680x test_mips test_ppc TESTS += test_sparc test_systemz test_x86 test_xcore check: @for t in $(TESTS); do \ echo Check $$t ... ; \ ./$$t > /dev/null && echo OK || echo FAILED; \ done capstone-sys-0.15.0/capstone/bindings/ocaml/README000064400000000000000000000014410072674642500177530ustar 00000000000000To compile Ocaml binding, Ocaml toolchain is needed. On Ubuntu Linux, you can install Ocaml with: $ sudo apt-get install ocaml-nox To compile Ocaml binding, simply run "make" on the command line. This directory also contains some test code to show how to use Capstone API. - test_basic.ml This code shows the most simple form of API where we only want to get basic information out of disassembled instruction, such as address, mnemonic and operand string. - test_detail.ml: This code shows how to access to architecture-neutral information in disassembled instructions, such as implicit registers read/written, or groups of instructions that this instruction belong to. - test_.ml These code show how to access architecture-specific information for each architecture. capstone-sys-0.15.0/capstone/bindings/ocaml/arm.ml000064400000000000000000000020040072674642500202000ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Arm_const let _CS_OP_ARCH = 5;; let _CS_OP_CIMM = _CS_OP_ARCH (* C-Immediate *) let _CS_OP_PIMM = _CS_OP_ARCH + 1 (* P-Immediate *) (* architecture specific info of instruction *) type arm_op_shift = { shift_type: int; (* TODO: covert this to pattern like arm_op_value? *) shift_value: int; } type arm_op_mem = { base: int; index: int; scale: int; disp: int; lshift: int; } type arm_op_value = | ARM_OP_INVALID of int | ARM_OP_REG of int | ARM_OP_CIMM of int | ARM_OP_PIMM of int | ARM_OP_IMM of int | ARM_OP_FP of float | ARM_OP_MEM of arm_op_mem | ARM_OP_SETEND of int type arm_op = { vector_index: int; shift: arm_op_shift; value: arm_op_value; subtracted: bool; access: int; neon_lane: int; } type cs_arm = { usermode: bool; vector_size: int; vector_data: int; cps_mode: int; cps_flag: int; cc: int; update_flags: bool; writeback: bool; mem_barrier: int; operands: arm_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/arm64.ml000064400000000000000000000014640072674642500203630ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Arm64_const (* architecture specific info of instruction *) type arm64_op_shift = { shift_type: int; shift_value: int; } type arm64_op_mem = { base: int; index: int; disp: int } type arm64_op_value = | ARM64_OP_INVALID of int | ARM64_OP_REG of int | ARM64_OP_CIMM of int | ARM64_OP_IMM of int | ARM64_OP_FP of float | ARM64_OP_MEM of arm64_op_mem | ARM64_OP_REG_MRS of int | ARM64_OP_REG_MSR of int | ARM64_OP_PSTATE of int | ARM64_OP_SYS of int | ARM64_OP_PREFETCH of int | ARM64_OP_BARRIER of int type arm64_op = { vector_index: int; vas: int; shift: arm64_op_shift; ext: int; value: arm64_op_value; } type cs_arm64 = { cc: int; update_flags: bool; writeback: bool; operands: arm64_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/arm64_const.ml000064400000000000000000002166650072674642500216040ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.ml] *) let _ARM64_SFT_INVALID = 0;; let _ARM64_SFT_LSL = 1;; let _ARM64_SFT_MSL = 2;; let _ARM64_SFT_LSR = 3;; let _ARM64_SFT_ASR = 4;; let _ARM64_SFT_ROR = 5;; let _ARM64_EXT_INVALID = 0;; let _ARM64_EXT_UXTB = 1;; let _ARM64_EXT_UXTH = 2;; let _ARM64_EXT_UXTW = 3;; let _ARM64_EXT_UXTX = 4;; let _ARM64_EXT_SXTB = 5;; let _ARM64_EXT_SXTH = 6;; let _ARM64_EXT_SXTW = 7;; let _ARM64_EXT_SXTX = 8;; let _ARM64_CC_INVALID = 0;; let _ARM64_CC_EQ = 1;; let _ARM64_CC_NE = 2;; let _ARM64_CC_HS = 3;; let _ARM64_CC_LO = 4;; let _ARM64_CC_MI = 5;; let _ARM64_CC_PL = 6;; let _ARM64_CC_VS = 7;; let _ARM64_CC_VC = 8;; let _ARM64_CC_HI = 9;; let _ARM64_CC_LS = 10;; let _ARM64_CC_GE = 11;; let _ARM64_CC_LT = 12;; let _ARM64_CC_GT = 13;; let _ARM64_CC_LE = 14;; let _ARM64_CC_AL = 15;; let _ARM64_CC_NV = 16;; let _ARM64_SYSREG_INVALID = 0;; let _ARM64_SYSREG_MDCCSR_EL0 = 0x9808;; let _ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828;; let _ARM64_SYSREG_MDRAR_EL1 = 0x8080;; let _ARM64_SYSREG_OSLSR_EL1 = 0x808C;; let _ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6;; let _ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6;; let _ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7;; let _ARM64_SYSREG_MIDR_EL1 = 0xC000;; let _ARM64_SYSREG_CCSIDR_EL1 = 0xC800;; let _ARM64_SYSREG_CCSIDR2_EL1 = 0xC802;; let _ARM64_SYSREG_CLIDR_EL1 = 0xC801;; let _ARM64_SYSREG_CTR_EL0 = 0xD801;; let _ARM64_SYSREG_MPIDR_EL1 = 0xC005;; let _ARM64_SYSREG_REVIDR_EL1 = 0xC006;; let _ARM64_SYSREG_AIDR_EL1 = 0xC807;; let _ARM64_SYSREG_DCZID_EL0 = 0xD807;; let _ARM64_SYSREG_ID_PFR0_EL1 = 0xC008;; let _ARM64_SYSREG_ID_PFR1_EL1 = 0xC009;; let _ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A;; let _ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B;; let _ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C;; let _ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D;; let _ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E;; let _ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F;; let _ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010;; let _ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011;; let _ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012;; let _ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013;; let _ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014;; let _ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015;; let _ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017;; let _ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020;; let _ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021;; let _ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028;; let _ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029;; let _ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C;; let _ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D;; let _ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030;; let _ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031;; let _ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038;; let _ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039;; let _ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A;; let _ARM64_SYSREG_MVFR0_EL1 = 0xC018;; let _ARM64_SYSREG_MVFR1_EL1 = 0xC019;; let _ARM64_SYSREG_MVFR2_EL1 = 0xC01A;; let _ARM64_SYSREG_RVBAR_EL1 = 0xC601;; let _ARM64_SYSREG_RVBAR_EL2 = 0xE601;; let _ARM64_SYSREG_RVBAR_EL3 = 0xF601;; let _ARM64_SYSREG_ISR_EL1 = 0xC608;; let _ARM64_SYSREG_CNTPCT_EL0 = 0xDF01;; let _ARM64_SYSREG_CNTVCT_EL0 = 0xDF02;; let _ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016;; let _ARM64_SYSREG_TRCSTATR = 0x8818;; let _ARM64_SYSREG_TRCIDR8 = 0x8806;; let _ARM64_SYSREG_TRCIDR9 = 0x880E;; let _ARM64_SYSREG_TRCIDR10 = 0x8816;; let _ARM64_SYSREG_TRCIDR11 = 0x881E;; let _ARM64_SYSREG_TRCIDR12 = 0x8826;; let _ARM64_SYSREG_TRCIDR13 = 0x882E;; let _ARM64_SYSREG_TRCIDR0 = 0x8847;; let _ARM64_SYSREG_TRCIDR1 = 0x884F;; let _ARM64_SYSREG_TRCIDR2 = 0x8857;; let _ARM64_SYSREG_TRCIDR3 = 0x885F;; let _ARM64_SYSREG_TRCIDR4 = 0x8867;; let _ARM64_SYSREG_TRCIDR5 = 0x886F;; let _ARM64_SYSREG_TRCIDR6 = 0x8877;; let _ARM64_SYSREG_TRCIDR7 = 0x887F;; let _ARM64_SYSREG_TRCOSLSR = 0x888C;; let _ARM64_SYSREG_TRCPDSR = 0x88AC;; let _ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6;; let _ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE;; let _ARM64_SYSREG_TRCLSR = 0x8BEE;; let _ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6;; let _ARM64_SYSREG_TRCDEVARCH = 0x8BFE;; let _ARM64_SYSREG_TRCDEVID = 0x8B97;; let _ARM64_SYSREG_TRCDEVTYPE = 0x8B9F;; let _ARM64_SYSREG_TRCPIDR4 = 0x8BA7;; let _ARM64_SYSREG_TRCPIDR5 = 0x8BAF;; let _ARM64_SYSREG_TRCPIDR6 = 0x8BB7;; let _ARM64_SYSREG_TRCPIDR7 = 0x8BBF;; let _ARM64_SYSREG_TRCPIDR0 = 0x8BC7;; let _ARM64_SYSREG_TRCPIDR1 = 0x8BCF;; let _ARM64_SYSREG_TRCPIDR2 = 0x8BD7;; let _ARM64_SYSREG_TRCPIDR3 = 0x8BDF;; let _ARM64_SYSREG_TRCCIDR0 = 0x8BE7;; let _ARM64_SYSREG_TRCCIDR1 = 0x8BEF;; let _ARM64_SYSREG_TRCCIDR2 = 0x8BF7;; let _ARM64_SYSREG_TRCCIDR3 = 0x8BFF;; let _ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660;; let _ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640;; let _ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662;; let _ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642;; let _ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B;; let _ARM64_SYSREG_ICH_VTR_EL2 = 0xE659;; let _ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B;; let _ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D;; let _ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024;; let _ARM64_SYSREG_LORID_EL1 = 0xC527;; let _ARM64_SYSREG_ERRIDR_EL1 = 0xC298;; let _ARM64_SYSREG_ERXFR_EL1 = 0xC2A0;; let _ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;; let _ARM64_SYSREG_OSLAR_EL1 = 0x8084;; let _ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4;; let _ARM64_SYSREG_TRCOSLAR = 0x8884;; let _ARM64_SYSREG_TRCLAR = 0x8BE6;; let _ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661;; let _ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641;; let _ARM64_SYSREG_ICC_DIR_EL1 = 0xC659;; let _ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D;; let _ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E;; let _ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F;; let _ARM64_SYSREG_OSDTRRX_EL1 = 0x8002;; let _ARM64_SYSREG_OSDTRTX_EL1 = 0x801A;; let _ARM64_SYSREG_TEECR32_EL1 = 0x9000;; let _ARM64_SYSREG_MDCCINT_EL1 = 0x8010;; let _ARM64_SYSREG_MDSCR_EL1 = 0x8012;; let _ARM64_SYSREG_DBGDTR_EL0 = 0x9820;; let _ARM64_SYSREG_OSECCR_EL1 = 0x8032;; let _ARM64_SYSREG_DBGVCR32_EL2 = 0xA038;; let _ARM64_SYSREG_DBGBVR0_EL1 = 0x8004;; let _ARM64_SYSREG_DBGBVR1_EL1 = 0x800C;; let _ARM64_SYSREG_DBGBVR2_EL1 = 0x8014;; let _ARM64_SYSREG_DBGBVR3_EL1 = 0x801C;; let _ARM64_SYSREG_DBGBVR4_EL1 = 0x8024;; let _ARM64_SYSREG_DBGBVR5_EL1 = 0x802C;; let _ARM64_SYSREG_DBGBVR6_EL1 = 0x8034;; let _ARM64_SYSREG_DBGBVR7_EL1 = 0x803C;; let _ARM64_SYSREG_DBGBVR8_EL1 = 0x8044;; let _ARM64_SYSREG_DBGBVR9_EL1 = 0x804C;; let _ARM64_SYSREG_DBGBVR10_EL1 = 0x8054;; let _ARM64_SYSREG_DBGBVR11_EL1 = 0x805C;; let _ARM64_SYSREG_DBGBVR12_EL1 = 0x8064;; let _ARM64_SYSREG_DBGBVR13_EL1 = 0x806C;; let _ARM64_SYSREG_DBGBVR14_EL1 = 0x8074;; let _ARM64_SYSREG_DBGBVR15_EL1 = 0x807C;; let _ARM64_SYSREG_DBGBCR0_EL1 = 0x8005;; let _ARM64_SYSREG_DBGBCR1_EL1 = 0x800D;; let _ARM64_SYSREG_DBGBCR2_EL1 = 0x8015;; let _ARM64_SYSREG_DBGBCR3_EL1 = 0x801D;; let _ARM64_SYSREG_DBGBCR4_EL1 = 0x8025;; let _ARM64_SYSREG_DBGBCR5_EL1 = 0x802D;; let _ARM64_SYSREG_DBGBCR6_EL1 = 0x8035;; let _ARM64_SYSREG_DBGBCR7_EL1 = 0x803D;; let _ARM64_SYSREG_DBGBCR8_EL1 = 0x8045;; let _ARM64_SYSREG_DBGBCR9_EL1 = 0x804D;; let _ARM64_SYSREG_DBGBCR10_EL1 = 0x8055;; let _ARM64_SYSREG_DBGBCR11_EL1 = 0x805D;; let _ARM64_SYSREG_DBGBCR12_EL1 = 0x8065;; let _ARM64_SYSREG_DBGBCR13_EL1 = 0x806D;; let _ARM64_SYSREG_DBGBCR14_EL1 = 0x8075;; let _ARM64_SYSREG_DBGBCR15_EL1 = 0x807D;; let _ARM64_SYSREG_DBGWVR0_EL1 = 0x8006;; let _ARM64_SYSREG_DBGWVR1_EL1 = 0x800E;; let _ARM64_SYSREG_DBGWVR2_EL1 = 0x8016;; let _ARM64_SYSREG_DBGWVR3_EL1 = 0x801E;; let _ARM64_SYSREG_DBGWVR4_EL1 = 0x8026;; let _ARM64_SYSREG_DBGWVR5_EL1 = 0x802E;; let _ARM64_SYSREG_DBGWVR6_EL1 = 0x8036;; let _ARM64_SYSREG_DBGWVR7_EL1 = 0x803E;; let _ARM64_SYSREG_DBGWVR8_EL1 = 0x8046;; let _ARM64_SYSREG_DBGWVR9_EL1 = 0x804E;; let _ARM64_SYSREG_DBGWVR10_EL1 = 0x8056;; let _ARM64_SYSREG_DBGWVR11_EL1 = 0x805E;; let _ARM64_SYSREG_DBGWVR12_EL1 = 0x8066;; let _ARM64_SYSREG_DBGWVR13_EL1 = 0x806E;; let _ARM64_SYSREG_DBGWVR14_EL1 = 0x8076;; let _ARM64_SYSREG_DBGWVR15_EL1 = 0x807E;; let _ARM64_SYSREG_DBGWCR0_EL1 = 0x8007;; let _ARM64_SYSREG_DBGWCR1_EL1 = 0x800F;; let _ARM64_SYSREG_DBGWCR2_EL1 = 0x8017;; let _ARM64_SYSREG_DBGWCR3_EL1 = 0x801F;; let _ARM64_SYSREG_DBGWCR4_EL1 = 0x8027;; let _ARM64_SYSREG_DBGWCR5_EL1 = 0x802F;; let _ARM64_SYSREG_DBGWCR6_EL1 = 0x8037;; let _ARM64_SYSREG_DBGWCR7_EL1 = 0x803F;; let _ARM64_SYSREG_DBGWCR8_EL1 = 0x8047;; let _ARM64_SYSREG_DBGWCR9_EL1 = 0x804F;; let _ARM64_SYSREG_DBGWCR10_EL1 = 0x8057;; let _ARM64_SYSREG_DBGWCR11_EL1 = 0x805F;; let _ARM64_SYSREG_DBGWCR12_EL1 = 0x8067;; let _ARM64_SYSREG_DBGWCR13_EL1 = 0x806F;; let _ARM64_SYSREG_DBGWCR14_EL1 = 0x8077;; let _ARM64_SYSREG_DBGWCR15_EL1 = 0x807F;; let _ARM64_SYSREG_TEEHBR32_EL1 = 0x9080;; let _ARM64_SYSREG_OSDLR_EL1 = 0x809C;; let _ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4;; let _ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6;; let _ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE;; let _ARM64_SYSREG_CSSELR_EL1 = 0xD000;; let _ARM64_SYSREG_VPIDR_EL2 = 0xE000;; let _ARM64_SYSREG_VMPIDR_EL2 = 0xE005;; let _ARM64_SYSREG_CPACR_EL1 = 0xC082;; let _ARM64_SYSREG_SCTLR_EL1 = 0xC080;; let _ARM64_SYSREG_SCTLR_EL2 = 0xE080;; let _ARM64_SYSREG_SCTLR_EL3 = 0xF080;; let _ARM64_SYSREG_ACTLR_EL1 = 0xC081;; let _ARM64_SYSREG_ACTLR_EL2 = 0xE081;; let _ARM64_SYSREG_ACTLR_EL3 = 0xF081;; let _ARM64_SYSREG_HCR_EL2 = 0xE088;; let _ARM64_SYSREG_SCR_EL3 = 0xF088;; let _ARM64_SYSREG_MDCR_EL2 = 0xE089;; let _ARM64_SYSREG_SDER32_EL3 = 0xF089;; let _ARM64_SYSREG_CPTR_EL2 = 0xE08A;; let _ARM64_SYSREG_CPTR_EL3 = 0xF08A;; let _ARM64_SYSREG_HSTR_EL2 = 0xE08B;; let _ARM64_SYSREG_HACR_EL2 = 0xE08F;; let _ARM64_SYSREG_MDCR_EL3 = 0xF099;; let _ARM64_SYSREG_TTBR0_EL1 = 0xC100;; let _ARM64_SYSREG_TTBR0_EL2 = 0xE100;; let _ARM64_SYSREG_TTBR0_EL3 = 0xF100;; let _ARM64_SYSREG_TTBR1_EL1 = 0xC101;; let _ARM64_SYSREG_TCR_EL1 = 0xC102;; let _ARM64_SYSREG_TCR_EL2 = 0xE102;; let _ARM64_SYSREG_TCR_EL3 = 0xF102;; let _ARM64_SYSREG_VTTBR_EL2 = 0xE108;; let _ARM64_SYSREG_VTCR_EL2 = 0xE10A;; let _ARM64_SYSREG_DACR32_EL2 = 0xE180;; let _ARM64_SYSREG_SPSR_EL1 = 0xC200;; let _ARM64_SYSREG_SPSR_EL2 = 0xE200;; let _ARM64_SYSREG_SPSR_EL3 = 0xF200;; let _ARM64_SYSREG_ELR_EL1 = 0xC201;; let _ARM64_SYSREG_ELR_EL2 = 0xE201;; let _ARM64_SYSREG_ELR_EL3 = 0xF201;; let _ARM64_SYSREG_SP_EL0 = 0xC208;; let _ARM64_SYSREG_SP_EL1 = 0xE208;; let _ARM64_SYSREG_SP_EL2 = 0xF208;; let _ARM64_SYSREG_SPSEL = 0xC210;; let _ARM64_SYSREG_NZCV = 0xDA10;; let _ARM64_SYSREG_DAIF = 0xDA11;; let _ARM64_SYSREG_CURRENTEL = 0xC212;; let _ARM64_SYSREG_SPSR_IRQ = 0xE218;; let _ARM64_SYSREG_SPSR_ABT = 0xE219;; let _ARM64_SYSREG_SPSR_UND = 0xE21A;; let _ARM64_SYSREG_SPSR_FIQ = 0xE21B;; let _ARM64_SYSREG_FPCR = 0xDA20;; let _ARM64_SYSREG_FPSR = 0xDA21;; let _ARM64_SYSREG_DSPSR_EL0 = 0xDA28;; let _ARM64_SYSREG_DLR_EL0 = 0xDA29;; let _ARM64_SYSREG_IFSR32_EL2 = 0xE281;; let _ARM64_SYSREG_AFSR0_EL1 = 0xC288;; let _ARM64_SYSREG_AFSR0_EL2 = 0xE288;; let _ARM64_SYSREG_AFSR0_EL3 = 0xF288;; let _ARM64_SYSREG_AFSR1_EL1 = 0xC289;; let _ARM64_SYSREG_AFSR1_EL2 = 0xE289;; let _ARM64_SYSREG_AFSR1_EL3 = 0xF289;; let _ARM64_SYSREG_ESR_EL1 = 0xC290;; let _ARM64_SYSREG_ESR_EL2 = 0xE290;; let _ARM64_SYSREG_ESR_EL3 = 0xF290;; let _ARM64_SYSREG_FPEXC32_EL2 = 0xE298;; let _ARM64_SYSREG_FAR_EL1 = 0xC300;; let _ARM64_SYSREG_FAR_EL2 = 0xE300;; let _ARM64_SYSREG_FAR_EL3 = 0xF300;; let _ARM64_SYSREG_HPFAR_EL2 = 0xE304;; let _ARM64_SYSREG_PAR_EL1 = 0xC3A0;; let _ARM64_SYSREG_PMCR_EL0 = 0xDCE0;; let _ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1;; let _ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2;; let _ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3;; let _ARM64_SYSREG_PMSELR_EL0 = 0xDCE5;; let _ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8;; let _ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9;; let _ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA;; let _ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0;; let _ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1;; let _ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2;; let _ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3;; let _ARM64_SYSREG_MAIR_EL1 = 0xC510;; let _ARM64_SYSREG_MAIR_EL2 = 0xE510;; let _ARM64_SYSREG_MAIR_EL3 = 0xF510;; let _ARM64_SYSREG_AMAIR_EL1 = 0xC518;; let _ARM64_SYSREG_AMAIR_EL2 = 0xE518;; let _ARM64_SYSREG_AMAIR_EL3 = 0xF518;; let _ARM64_SYSREG_VBAR_EL1 = 0xC600;; let _ARM64_SYSREG_VBAR_EL2 = 0xE600;; let _ARM64_SYSREG_VBAR_EL3 = 0xF600;; let _ARM64_SYSREG_RMR_EL1 = 0xC602;; let _ARM64_SYSREG_RMR_EL2 = 0xE602;; let _ARM64_SYSREG_RMR_EL3 = 0xF602;; let _ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681;; let _ARM64_SYSREG_TPIDR_EL0 = 0xDE82;; let _ARM64_SYSREG_TPIDR_EL2 = 0xE682;; let _ARM64_SYSREG_TPIDR_EL3 = 0xF682;; let _ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83;; let _ARM64_SYSREG_TPIDR_EL1 = 0xC684;; let _ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00;; let _ARM64_SYSREG_CNTVOFF_EL2 = 0xE703;; let _ARM64_SYSREG_CNTKCTL_EL1 = 0xC708;; let _ARM64_SYSREG_CNTHCTL_EL2 = 0xE708;; let _ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10;; let _ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710;; let _ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10;; let _ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11;; let _ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711;; let _ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11;; let _ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12;; let _ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712;; let _ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12;; let _ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18;; let _ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19;; let _ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A;; let _ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40;; let _ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41;; let _ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42;; let _ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43;; let _ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44;; let _ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45;; let _ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46;; let _ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47;; let _ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48;; let _ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49;; let _ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A;; let _ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B;; let _ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C;; let _ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D;; let _ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E;; let _ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F;; let _ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50;; let _ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51;; let _ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52;; let _ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53;; let _ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54;; let _ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55;; let _ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56;; let _ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57;; let _ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58;; let _ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59;; let _ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A;; let _ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B;; let _ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C;; let _ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D;; let _ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E;; let _ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F;; let _ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60;; let _ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61;; let _ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62;; let _ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63;; let _ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64;; let _ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65;; let _ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66;; let _ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67;; let _ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68;; let _ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69;; let _ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A;; let _ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B;; let _ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C;; let _ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D;; let _ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E;; let _ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F;; let _ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70;; let _ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71;; let _ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72;; let _ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73;; let _ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74;; let _ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75;; let _ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76;; let _ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77;; let _ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78;; let _ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79;; let _ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A;; let _ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B;; let _ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C;; let _ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D;; let _ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E;; let _ARM64_SYSREG_TRCPRGCTLR = 0x8808;; let _ARM64_SYSREG_TRCPROCSELR = 0x8810;; let _ARM64_SYSREG_TRCCONFIGR = 0x8820;; let _ARM64_SYSREG_TRCAUXCTLR = 0x8830;; let _ARM64_SYSREG_TRCEVENTCTL0R = 0x8840;; let _ARM64_SYSREG_TRCEVENTCTL1R = 0x8848;; let _ARM64_SYSREG_TRCSTALLCTLR = 0x8858;; let _ARM64_SYSREG_TRCTSCTLR = 0x8860;; let _ARM64_SYSREG_TRCSYNCPR = 0x8868;; let _ARM64_SYSREG_TRCCCCTLR = 0x8870;; let _ARM64_SYSREG_TRCBBCTLR = 0x8878;; let _ARM64_SYSREG_TRCTRACEIDR = 0x8801;; let _ARM64_SYSREG_TRCQCTLR = 0x8809;; let _ARM64_SYSREG_TRCVICTLR = 0x8802;; let _ARM64_SYSREG_TRCVIIECTLR = 0x880A;; let _ARM64_SYSREG_TRCVISSCTLR = 0x8812;; let _ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A;; let _ARM64_SYSREG_TRCVDCTLR = 0x8842;; let _ARM64_SYSREG_TRCVDSACCTLR = 0x884A;; let _ARM64_SYSREG_TRCVDARCCTLR = 0x8852;; let _ARM64_SYSREG_TRCSEQEVR0 = 0x8804;; let _ARM64_SYSREG_TRCSEQEVR1 = 0x880C;; let _ARM64_SYSREG_TRCSEQEVR2 = 0x8814;; let _ARM64_SYSREG_TRCSEQRSTEVR = 0x8834;; let _ARM64_SYSREG_TRCSEQSTR = 0x883C;; let _ARM64_SYSREG_TRCEXTINSELR = 0x8844;; let _ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805;; let _ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D;; let _ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815;; let _ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D;; let _ARM64_SYSREG_TRCCNTCTLR0 = 0x8825;; let _ARM64_SYSREG_TRCCNTCTLR1 = 0x882D;; let _ARM64_SYSREG_TRCCNTCTLR2 = 0x8835;; let _ARM64_SYSREG_TRCCNTCTLR3 = 0x883D;; let _ARM64_SYSREG_TRCCNTVR0 = 0x8845;; let _ARM64_SYSREG_TRCCNTVR1 = 0x884D;; let _ARM64_SYSREG_TRCCNTVR2 = 0x8855;; let _ARM64_SYSREG_TRCCNTVR3 = 0x885D;; let _ARM64_SYSREG_TRCIMSPEC0 = 0x8807;; let _ARM64_SYSREG_TRCIMSPEC1 = 0x880F;; let _ARM64_SYSREG_TRCIMSPEC2 = 0x8817;; let _ARM64_SYSREG_TRCIMSPEC3 = 0x881F;; let _ARM64_SYSREG_TRCIMSPEC4 = 0x8827;; let _ARM64_SYSREG_TRCIMSPEC5 = 0x882F;; let _ARM64_SYSREG_TRCIMSPEC6 = 0x8837;; let _ARM64_SYSREG_TRCIMSPEC7 = 0x883F;; let _ARM64_SYSREG_TRCRSCTLR2 = 0x8890;; let _ARM64_SYSREG_TRCRSCTLR3 = 0x8898;; let _ARM64_SYSREG_TRCRSCTLR4 = 0x88A0;; let _ARM64_SYSREG_TRCRSCTLR5 = 0x88A8;; let _ARM64_SYSREG_TRCRSCTLR6 = 0x88B0;; let _ARM64_SYSREG_TRCRSCTLR7 = 0x88B8;; let _ARM64_SYSREG_TRCRSCTLR8 = 0x88C0;; let _ARM64_SYSREG_TRCRSCTLR9 = 0x88C8;; let _ARM64_SYSREG_TRCRSCTLR10 = 0x88D0;; let _ARM64_SYSREG_TRCRSCTLR11 = 0x88D8;; let _ARM64_SYSREG_TRCRSCTLR12 = 0x88E0;; let _ARM64_SYSREG_TRCRSCTLR13 = 0x88E8;; let _ARM64_SYSREG_TRCRSCTLR14 = 0x88F0;; let _ARM64_SYSREG_TRCRSCTLR15 = 0x88F8;; let _ARM64_SYSREG_TRCRSCTLR16 = 0x8881;; let _ARM64_SYSREG_TRCRSCTLR17 = 0x8889;; let _ARM64_SYSREG_TRCRSCTLR18 = 0x8891;; let _ARM64_SYSREG_TRCRSCTLR19 = 0x8899;; let _ARM64_SYSREG_TRCRSCTLR20 = 0x88A1;; let _ARM64_SYSREG_TRCRSCTLR21 = 0x88A9;; let _ARM64_SYSREG_TRCRSCTLR22 = 0x88B1;; let _ARM64_SYSREG_TRCRSCTLR23 = 0x88B9;; let _ARM64_SYSREG_TRCRSCTLR24 = 0x88C1;; let _ARM64_SYSREG_TRCRSCTLR25 = 0x88C9;; let _ARM64_SYSREG_TRCRSCTLR26 = 0x88D1;; let _ARM64_SYSREG_TRCRSCTLR27 = 0x88D9;; let _ARM64_SYSREG_TRCRSCTLR28 = 0x88E1;; let _ARM64_SYSREG_TRCRSCTLR29 = 0x88E9;; let _ARM64_SYSREG_TRCRSCTLR30 = 0x88F1;; let _ARM64_SYSREG_TRCRSCTLR31 = 0x88F9;; let _ARM64_SYSREG_TRCSSCCR0 = 0x8882;; let _ARM64_SYSREG_TRCSSCCR1 = 0x888A;; let _ARM64_SYSREG_TRCSSCCR2 = 0x8892;; let _ARM64_SYSREG_TRCSSCCR3 = 0x889A;; let _ARM64_SYSREG_TRCSSCCR4 = 0x88A2;; let _ARM64_SYSREG_TRCSSCCR5 = 0x88AA;; let _ARM64_SYSREG_TRCSSCCR6 = 0x88B2;; let _ARM64_SYSREG_TRCSSCCR7 = 0x88BA;; let _ARM64_SYSREG_TRCSSCSR0 = 0x88C2;; let _ARM64_SYSREG_TRCSSCSR1 = 0x88CA;; let _ARM64_SYSREG_TRCSSCSR2 = 0x88D2;; let _ARM64_SYSREG_TRCSSCSR3 = 0x88DA;; let _ARM64_SYSREG_TRCSSCSR4 = 0x88E2;; let _ARM64_SYSREG_TRCSSCSR5 = 0x88EA;; let _ARM64_SYSREG_TRCSSCSR6 = 0x88F2;; let _ARM64_SYSREG_TRCSSCSR7 = 0x88FA;; let _ARM64_SYSREG_TRCSSPCICR0 = 0x8883;; let _ARM64_SYSREG_TRCSSPCICR1 = 0x888B;; let _ARM64_SYSREG_TRCSSPCICR2 = 0x8893;; let _ARM64_SYSREG_TRCSSPCICR3 = 0x889B;; let _ARM64_SYSREG_TRCSSPCICR4 = 0x88A3;; let _ARM64_SYSREG_TRCSSPCICR5 = 0x88AB;; let _ARM64_SYSREG_TRCSSPCICR6 = 0x88B3;; let _ARM64_SYSREG_TRCSSPCICR7 = 0x88BB;; let _ARM64_SYSREG_TRCPDCR = 0x88A4;; let _ARM64_SYSREG_TRCACVR0 = 0x8900;; let _ARM64_SYSREG_TRCACVR1 = 0x8910;; let _ARM64_SYSREG_TRCACVR2 = 0x8920;; let _ARM64_SYSREG_TRCACVR3 = 0x8930;; let _ARM64_SYSREG_TRCACVR4 = 0x8940;; let _ARM64_SYSREG_TRCACVR5 = 0x8950;; let _ARM64_SYSREG_TRCACVR6 = 0x8960;; let _ARM64_SYSREG_TRCACVR7 = 0x8970;; let _ARM64_SYSREG_TRCACVR8 = 0x8901;; let _ARM64_SYSREG_TRCACVR9 = 0x8911;; let _ARM64_SYSREG_TRCACVR10 = 0x8921;; let _ARM64_SYSREG_TRCACVR11 = 0x8931;; let _ARM64_SYSREG_TRCACVR12 = 0x8941;; let _ARM64_SYSREG_TRCACVR13 = 0x8951;; let _ARM64_SYSREG_TRCACVR14 = 0x8961;; let _ARM64_SYSREG_TRCACVR15 = 0x8971;; let _ARM64_SYSREG_TRCACATR0 = 0x8902;; let _ARM64_SYSREG_TRCACATR1 = 0x8912;; let _ARM64_SYSREG_TRCACATR2 = 0x8922;; let _ARM64_SYSREG_TRCACATR3 = 0x8932;; let _ARM64_SYSREG_TRCACATR4 = 0x8942;; let _ARM64_SYSREG_TRCACATR5 = 0x8952;; let _ARM64_SYSREG_TRCACATR6 = 0x8962;; let _ARM64_SYSREG_TRCACATR7 = 0x8972;; let _ARM64_SYSREG_TRCACATR8 = 0x8903;; let _ARM64_SYSREG_TRCACATR9 = 0x8913;; let _ARM64_SYSREG_TRCACATR10 = 0x8923;; let _ARM64_SYSREG_TRCACATR11 = 0x8933;; let _ARM64_SYSREG_TRCACATR12 = 0x8943;; let _ARM64_SYSREG_TRCACATR13 = 0x8953;; let _ARM64_SYSREG_TRCACATR14 = 0x8963;; let _ARM64_SYSREG_TRCACATR15 = 0x8973;; let _ARM64_SYSREG_TRCDVCVR0 = 0x8904;; let _ARM64_SYSREG_TRCDVCVR1 = 0x8924;; let _ARM64_SYSREG_TRCDVCVR2 = 0x8944;; let _ARM64_SYSREG_TRCDVCVR3 = 0x8964;; let _ARM64_SYSREG_TRCDVCVR4 = 0x8905;; let _ARM64_SYSREG_TRCDVCVR5 = 0x8925;; let _ARM64_SYSREG_TRCDVCVR6 = 0x8945;; let _ARM64_SYSREG_TRCDVCVR7 = 0x8965;; let _ARM64_SYSREG_TRCDVCMR0 = 0x8906;; let _ARM64_SYSREG_TRCDVCMR1 = 0x8926;; let _ARM64_SYSREG_TRCDVCMR2 = 0x8946;; let _ARM64_SYSREG_TRCDVCMR3 = 0x8966;; let _ARM64_SYSREG_TRCDVCMR4 = 0x8907;; let _ARM64_SYSREG_TRCDVCMR5 = 0x8927;; let _ARM64_SYSREG_TRCDVCMR6 = 0x8947;; let _ARM64_SYSREG_TRCDVCMR7 = 0x8967;; let _ARM64_SYSREG_TRCCIDCVR0 = 0x8980;; let _ARM64_SYSREG_TRCCIDCVR1 = 0x8990;; let _ARM64_SYSREG_TRCCIDCVR2 = 0x89A0;; let _ARM64_SYSREG_TRCCIDCVR3 = 0x89B0;; let _ARM64_SYSREG_TRCCIDCVR4 = 0x89C0;; let _ARM64_SYSREG_TRCCIDCVR5 = 0x89D0;; let _ARM64_SYSREG_TRCCIDCVR6 = 0x89E0;; let _ARM64_SYSREG_TRCCIDCVR7 = 0x89F0;; let _ARM64_SYSREG_TRCVMIDCVR0 = 0x8981;; let _ARM64_SYSREG_TRCVMIDCVR1 = 0x8991;; let _ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1;; let _ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1;; let _ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1;; let _ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1;; let _ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1;; let _ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1;; let _ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982;; let _ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A;; let _ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992;; let _ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A;; let _ARM64_SYSREG_TRCITCTRL = 0x8B84;; let _ARM64_SYSREG_TRCCLAIMSET = 0x8BC6;; let _ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE;; let _ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663;; let _ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643;; let _ARM64_SYSREG_ICC_PMR_EL1 = 0xC230;; let _ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664;; let _ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664;; let _ARM64_SYSREG_ICC_SRE_EL1 = 0xC665;; let _ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D;; let _ARM64_SYSREG_ICC_SRE_EL3 = 0xF665;; let _ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666;; let _ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667;; let _ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667;; let _ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668;; let _ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644;; let _ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645;; let _ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646;; let _ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647;; let _ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648;; let _ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649;; let _ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A;; let _ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B;; let _ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640;; let _ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641;; let _ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642;; let _ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643;; let _ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648;; let _ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649;; let _ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A;; let _ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B;; let _ARM64_SYSREG_ICH_HCR_EL2 = 0xE658;; let _ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A;; let _ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F;; let _ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C;; let _ARM64_SYSREG_ICH_LR0_EL2 = 0xE660;; let _ARM64_SYSREG_ICH_LR1_EL2 = 0xE661;; let _ARM64_SYSREG_ICH_LR2_EL2 = 0xE662;; let _ARM64_SYSREG_ICH_LR3_EL2 = 0xE663;; let _ARM64_SYSREG_ICH_LR4_EL2 = 0xE664;; let _ARM64_SYSREG_ICH_LR5_EL2 = 0xE665;; let _ARM64_SYSREG_ICH_LR6_EL2 = 0xE666;; let _ARM64_SYSREG_ICH_LR7_EL2 = 0xE667;; let _ARM64_SYSREG_ICH_LR8_EL2 = 0xE668;; let _ARM64_SYSREG_ICH_LR9_EL2 = 0xE669;; let _ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A;; let _ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B;; let _ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C;; let _ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D;; let _ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E;; let _ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F;; let _ARM64_SYSREG_PAN = 0xC213;; let _ARM64_SYSREG_LORSA_EL1 = 0xC520;; let _ARM64_SYSREG_LOREA_EL1 = 0xC521;; let _ARM64_SYSREG_LORN_EL1 = 0xC522;; let _ARM64_SYSREG_LORC_EL1 = 0xC523;; let _ARM64_SYSREG_TTBR1_EL2 = 0xE101;; let _ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681;; let _ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718;; let _ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A;; let _ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719;; let _ARM64_SYSREG_SCTLR_EL12 = 0xE880;; let _ARM64_SYSREG_CPACR_EL12 = 0xE882;; let _ARM64_SYSREG_TTBR0_EL12 = 0xE900;; let _ARM64_SYSREG_TTBR1_EL12 = 0xE901;; let _ARM64_SYSREG_TCR_EL12 = 0xE902;; let _ARM64_SYSREG_AFSR0_EL12 = 0xEA88;; let _ARM64_SYSREG_AFSR1_EL12 = 0xEA89;; let _ARM64_SYSREG_ESR_EL12 = 0xEA90;; let _ARM64_SYSREG_FAR_EL12 = 0xEB00;; let _ARM64_SYSREG_MAIR_EL12 = 0xED10;; let _ARM64_SYSREG_AMAIR_EL12 = 0xED18;; let _ARM64_SYSREG_VBAR_EL12 = 0xEE00;; let _ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81;; let _ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08;; let _ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10;; let _ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11;; let _ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12;; let _ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18;; let _ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19;; let _ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A;; let _ARM64_SYSREG_SPSR_EL12 = 0xEA00;; let _ARM64_SYSREG_ELR_EL12 = 0xEA01;; let _ARM64_SYSREG_UAO = 0xC214;; let _ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0;; let _ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1;; let _ARM64_SYSREG_PMBSR_EL1 = 0xC4D3;; let _ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7;; let _ARM64_SYSREG_PMSCR_EL2 = 0xE4C8;; let _ARM64_SYSREG_PMSCR_EL12 = 0xECC8;; let _ARM64_SYSREG_PMSCR_EL1 = 0xC4C8;; let _ARM64_SYSREG_PMSICR_EL1 = 0xC4CA;; let _ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB;; let _ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC;; let _ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD;; let _ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE;; let _ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF;; let _ARM64_SYSREG_ERRSELR_EL1 = 0xC299;; let _ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1;; let _ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2;; let _ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3;; let _ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8;; let _ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9;; let _ARM64_SYSREG_DISR_EL1 = 0xC609;; let _ARM64_SYSREG_VDISR_EL2 = 0xE609;; let _ARM64_SYSREG_VSESR_EL2 = 0xE293;; let _ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108;; let _ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109;; let _ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A;; let _ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B;; let _ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110;; let _ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111;; let _ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112;; let _ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113;; let _ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118;; let _ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119;; let _ARM64_SYSREG_VSTCR_EL2 = 0xE132;; let _ARM64_SYSREG_VSTTBR_EL2 = 0xE130;; let _ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720;; let _ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722;; let _ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721;; let _ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728;; let _ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A;; let _ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729;; let _ARM64_SYSREG_SDER32_EL2 = 0xE099;; let _ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5;; let _ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6;; let _ARM64_SYSREG_ERXTS_EL1 = 0xC2AF;; let _ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA;; let _ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB;; let _ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4;; let _ARM64_SYSREG_MPAM0_EL1 = 0xC529;; let _ARM64_SYSREG_MPAM1_EL1 = 0xC528;; let _ARM64_SYSREG_MPAM2_EL2 = 0xE528;; let _ARM64_SYSREG_MPAM3_EL3 = 0xF528;; let _ARM64_SYSREG_MPAM1_EL12 = 0xED28;; let _ARM64_SYSREG_MPAMHCR_EL2 = 0xE520;; let _ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521;; let _ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530;; let _ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531;; let _ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532;; let _ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533;; let _ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534;; let _ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535;; let _ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536;; let _ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537;; let _ARM64_SYSREG_MPAMIDR_EL1 = 0xC524;; let _ARM64_SYSREG_AMCR_EL0 = 0xDE90;; let _ARM64_SYSREG_AMCFGR_EL0 = 0xDE91;; let _ARM64_SYSREG_AMCGCR_EL0 = 0xDE92;; let _ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93;; let _ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94;; let _ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95;; let _ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0;; let _ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1;; let _ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2;; let _ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3;; let _ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0;; let _ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1;; let _ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2;; let _ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3;; let _ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98;; let _ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99;; let _ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0;; let _ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1;; let _ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2;; let _ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3;; let _ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4;; let _ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5;; let _ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6;; let _ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7;; let _ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8;; let _ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9;; let _ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA;; let _ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB;; let _ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC;; let _ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED;; let _ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE;; let _ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF;; let _ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0;; let _ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1;; let _ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2;; let _ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3;; let _ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4;; let _ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5;; let _ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6;; let _ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7;; let _ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8;; let _ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9;; let _ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA;; let _ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB;; let _ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC;; let _ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD;; let _ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE;; let _ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF;; let _ARM64_SYSREG_TRFCR_EL1 = 0xC091;; let _ARM64_SYSREG_TRFCR_EL2 = 0xE091;; let _ARM64_SYSREG_TRFCR_EL12 = 0xE891;; let _ARM64_SYSREG_DIT = 0xDA15;; let _ARM64_SYSREG_VNCR_EL2 = 0xE110;; let _ARM64_SYSREG_ZCR_EL1 = 0xC090;; let _ARM64_SYSREG_ZCR_EL2 = 0xE090;; let _ARM64_SYSREG_ZCR_EL3 = 0xF090;; let _ARM64_SYSREG_ZCR_EL12 = 0xE890;; let _ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90;; let _ARM64_PSTATE_INVALID = 0;; let _ARM64_PSTATE_SPSEL = 0x05;; let _ARM64_PSTATE_DAIFSET = 0x1e;; let _ARM64_PSTATE_DAIFCLR = 0x1f;; let _ARM64_PSTATE_PAN = 0x4;; let _ARM64_PSTATE_UAO = 0x3;; let _ARM64_PSTATE_DIT = 0x1a;; let _ARM64_VAS_INVALID = 0;; let _ARM64_VAS_16B = 1;; let _ARM64_VAS_8B = 2;; let _ARM64_VAS_4B = 3;; let _ARM64_VAS_1B = 4;; let _ARM64_VAS_8H = 5;; let _ARM64_VAS_4H = 6;; let _ARM64_VAS_2H = 7;; let _ARM64_VAS_1H = 8;; let _ARM64_VAS_4S = 9;; let _ARM64_VAS_2S = 10;; let _ARM64_VAS_1S = 11;; let _ARM64_VAS_2D = 12;; let _ARM64_VAS_1D = 13;; let _ARM64_VAS_1Q = 14;; let _ARM64_BARRIER_INVALID = 0;; let _ARM64_BARRIER_OSHLD = 0x1;; let _ARM64_BARRIER_OSHST = 0x2;; let _ARM64_BARRIER_OSH = 0x3;; let _ARM64_BARRIER_NSHLD = 0x5;; let _ARM64_BARRIER_NSHST = 0x6;; let _ARM64_BARRIER_NSH = 0x7;; let _ARM64_BARRIER_ISHLD = 0x9;; let _ARM64_BARRIER_ISHST = 0xa;; let _ARM64_BARRIER_ISH = 0xb;; let _ARM64_BARRIER_LD = 0xd;; let _ARM64_BARRIER_ST = 0xe;; let _ARM64_BARRIER_SY = 0xf;; let _ARM64_OP_INVALID = 0;; let _ARM64_OP_REG = 1;; let _ARM64_OP_IMM = 2;; let _ARM64_OP_MEM = 3;; let _ARM64_OP_FP = 4;; let _ARM64_OP_CIMM = 64;; let _ARM64_OP_REG_MRS = 65;; let _ARM64_OP_REG_MSR = 66;; let _ARM64_OP_PSTATE = 67;; let _ARM64_OP_SYS = 68;; let _ARM64_OP_PREFETCH = 69;; let _ARM64_OP_BARRIER = 70;; let _ARM64_TLBI_INVALID = 0;; let _ARM64_TLBI_IPAS2E1IS = 1;; let _ARM64_TLBI_IPAS2LE1IS = 2;; let _ARM64_TLBI_VMALLE1IS = 3;; let _ARM64_TLBI_ALLE2IS = 4;; let _ARM64_TLBI_ALLE3IS = 5;; let _ARM64_TLBI_VAE1IS = 6;; let _ARM64_TLBI_VAE2IS = 7;; let _ARM64_TLBI_VAE3IS = 8;; let _ARM64_TLBI_ASIDE1IS = 9;; let _ARM64_TLBI_VAAE1IS = 10;; let _ARM64_TLBI_ALLE1IS = 11;; let _ARM64_TLBI_VALE1IS = 12;; let _ARM64_TLBI_VALE2IS = 13;; let _ARM64_TLBI_VALE3IS = 14;; let _ARM64_TLBI_VMALLS12E1IS = 15;; let _ARM64_TLBI_VAALE1IS = 16;; let _ARM64_TLBI_IPAS2E1 = 17;; let _ARM64_TLBI_IPAS2LE1 = 18;; let _ARM64_TLBI_VMALLE1 = 19;; let _ARM64_TLBI_ALLE2 = 20;; let _ARM64_TLBI_ALLE3 = 21;; let _ARM64_TLBI_VAE1 = 22;; let _ARM64_TLBI_VAE2 = 23;; let _ARM64_TLBI_VAE3 = 24;; let _ARM64_TLBI_ASIDE1 = 25;; let _ARM64_TLBI_VAAE1 = 26;; let _ARM64_TLBI_ALLE1 = 27;; let _ARM64_TLBI_VALE1 = 28;; let _ARM64_TLBI_VALE2 = 29;; let _ARM64_TLBI_VALE3 = 30;; let _ARM64_TLBI_VMALLS12E1 = 31;; let _ARM64_TLBI_VAALE1 = 32;; let _ARM64_TLBI_VMALLE1OS = 33;; let _ARM64_TLBI_VAE1OS = 34;; let _ARM64_TLBI_ASIDE1OS = 35;; let _ARM64_TLBI_VAAE1OS = 36;; let _ARM64_TLBI_VALE1OS = 37;; let _ARM64_TLBI_VAALE1OS = 38;; let _ARM64_TLBI_IPAS2E1OS = 39;; let _ARM64_TLBI_IPAS2LE1OS = 40;; let _ARM64_TLBI_VAE2OS = 41;; let _ARM64_TLBI_VALE2OS = 42;; let _ARM64_TLBI_VMALLS12E1OS = 43;; let _ARM64_TLBI_VAE3OS = 44;; let _ARM64_TLBI_VALE3OS = 45;; let _ARM64_TLBI_ALLE2OS = 46;; let _ARM64_TLBI_ALLE1OS = 47;; let _ARM64_TLBI_ALLE3OS = 48;; let _ARM64_TLBI_RVAE1 = 49;; let _ARM64_TLBI_RVAAE1 = 50;; let _ARM64_TLBI_RVALE1 = 51;; let _ARM64_TLBI_RVAALE1 = 52;; let _ARM64_TLBI_RVAE1IS = 53;; let _ARM64_TLBI_RVAAE1IS = 54;; let _ARM64_TLBI_RVALE1IS = 55;; let _ARM64_TLBI_RVAALE1IS = 56;; let _ARM64_TLBI_RVAE1OS = 57;; let _ARM64_TLBI_RVAAE1OS = 58;; let _ARM64_TLBI_RVALE1OS = 59;; let _ARM64_TLBI_RVAALE1OS = 60;; let _ARM64_TLBI_RIPAS2E1IS = 61;; let _ARM64_TLBI_RIPAS2LE1IS = 62;; let _ARM64_TLBI_RIPAS2E1 = 63;; let _ARM64_TLBI_RIPAS2LE1 = 64;; let _ARM64_TLBI_RIPAS2E1OS = 65;; let _ARM64_TLBI_RIPAS2LE1OS = 66;; let _ARM64_TLBI_RVAE2 = 67;; let _ARM64_TLBI_RVALE2 = 68;; let _ARM64_TLBI_RVAE2IS = 69;; let _ARM64_TLBI_RVALE2IS = 70;; let _ARM64_TLBI_RVAE2OS = 71;; let _ARM64_TLBI_RVALE2OS = 72;; let _ARM64_TLBI_RVAE3 = 73;; let _ARM64_TLBI_RVALE3 = 74;; let _ARM64_TLBI_RVAE3IS = 75;; let _ARM64_TLBI_RVALE3IS = 76;; let _ARM64_TLBI_RVAE3OS = 77;; let _ARM64_TLBI_RVALE3OS = 78;; let _ARM64_AT_S1E1R = 79;; let _ARM64_AT_S1E2R = 80;; let _ARM64_AT_S1E3R = 81;; let _ARM64_AT_S1E1W = 82;; let _ARM64_AT_S1E2W = 83;; let _ARM64_AT_S1E3W = 84;; let _ARM64_AT_S1E0R = 85;; let _ARM64_AT_S1E0W = 86;; let _ARM64_AT_S12E1R = 87;; let _ARM64_AT_S12E1W = 88;; let _ARM64_AT_S12E0R = 89;; let _ARM64_AT_S12E0W = 90;; let _ARM64_AT_S1E1RP = 91;; let _ARM64_AT_S1E1WP = 92;; let _ARM64_DC_INVALID = 0;; let _ARM64_DC_ZVA = 1;; let _ARM64_DC_IVAC = 2;; let _ARM64_DC_ISW = 3;; let _ARM64_DC_CVAC = 4;; let _ARM64_DC_CSW = 5;; let _ARM64_DC_CVAU = 6;; let _ARM64_DC_CIVAC = 7;; let _ARM64_DC_CISW = 8;; let _ARM64_DC_CVAP = 9;; let _ARM64_IC_INVALID = 0;; let _ARM64_IC_IALLUIS = 1;; let _ARM64_IC_IALLU = 2;; let _ARM64_IC_IVAU = 3;; let _ARM64_PRFM_INVALID = 0;; let _ARM64_PRFM_PLDL1KEEP = 0x00+1;; let _ARM64_PRFM_PLDL1STRM = 0x01+1;; let _ARM64_PRFM_PLDL2KEEP = 0x02+1;; let _ARM64_PRFM_PLDL2STRM = 0x03+1;; let _ARM64_PRFM_PLDL3KEEP = 0x04+1;; let _ARM64_PRFM_PLDL3STRM = 0x05+1;; let _ARM64_PRFM_PLIL1KEEP = 0x08+1;; let _ARM64_PRFM_PLIL1STRM = 0x09+1;; let _ARM64_PRFM_PLIL2KEEP = 0x0a+1;; let _ARM64_PRFM_PLIL2STRM = 0x0b+1;; let _ARM64_PRFM_PLIL3KEEP = 0x0c+1;; let _ARM64_PRFM_PLIL3STRM = 0x0d+1;; let _ARM64_PRFM_PSTL1KEEP = 0x10+1;; let _ARM64_PRFM_PSTL1STRM = 0x11+1;; let _ARM64_PRFM_PSTL2KEEP = 0x12+1;; let _ARM64_PRFM_PSTL2STRM = 0x13+1;; let _ARM64_PRFM_PSTL3KEEP = 0x14+1;; let _ARM64_PRFM_PSTL3STRM = 0x15+1;; let _ARM64_REG_INVALID = 0;; let _ARM64_REG_FFR = 1;; let _ARM64_REG_FP = 2;; let _ARM64_REG_LR = 3;; let _ARM64_REG_NZCV = 4;; let _ARM64_REG_SP = 5;; let _ARM64_REG_WSP = 6;; let _ARM64_REG_WZR = 7;; let _ARM64_REG_XZR = 8;; let _ARM64_REG_B0 = 9;; let _ARM64_REG_B1 = 10;; let _ARM64_REG_B2 = 11;; let _ARM64_REG_B3 = 12;; let _ARM64_REG_B4 = 13;; let _ARM64_REG_B5 = 14;; let _ARM64_REG_B6 = 15;; let _ARM64_REG_B7 = 16;; let _ARM64_REG_B8 = 17;; let _ARM64_REG_B9 = 18;; let _ARM64_REG_B10 = 19;; let _ARM64_REG_B11 = 20;; let _ARM64_REG_B12 = 21;; let _ARM64_REG_B13 = 22;; let _ARM64_REG_B14 = 23;; let _ARM64_REG_B15 = 24;; let _ARM64_REG_B16 = 25;; let _ARM64_REG_B17 = 26;; let _ARM64_REG_B18 = 27;; let _ARM64_REG_B19 = 28;; let _ARM64_REG_B20 = 29;; let _ARM64_REG_B21 = 30;; let _ARM64_REG_B22 = 31;; let _ARM64_REG_B23 = 32;; let _ARM64_REG_B24 = 33;; let _ARM64_REG_B25 = 34;; let _ARM64_REG_B26 = 35;; let _ARM64_REG_B27 = 36;; let _ARM64_REG_B28 = 37;; let _ARM64_REG_B29 = 38;; let _ARM64_REG_B30 = 39;; let _ARM64_REG_B31 = 40;; let _ARM64_REG_D0 = 41;; let _ARM64_REG_D1 = 42;; let _ARM64_REG_D2 = 43;; let _ARM64_REG_D3 = 44;; let _ARM64_REG_D4 = 45;; let _ARM64_REG_D5 = 46;; let _ARM64_REG_D6 = 47;; let _ARM64_REG_D7 = 48;; let _ARM64_REG_D8 = 49;; let _ARM64_REG_D9 = 50;; let _ARM64_REG_D10 = 51;; let _ARM64_REG_D11 = 52;; let _ARM64_REG_D12 = 53;; let _ARM64_REG_D13 = 54;; let _ARM64_REG_D14 = 55;; let _ARM64_REG_D15 = 56;; let _ARM64_REG_D16 = 57;; let _ARM64_REG_D17 = 58;; let _ARM64_REG_D18 = 59;; let _ARM64_REG_D19 = 60;; let _ARM64_REG_D20 = 61;; let _ARM64_REG_D21 = 62;; let _ARM64_REG_D22 = 63;; let _ARM64_REG_D23 = 64;; let _ARM64_REG_D24 = 65;; let _ARM64_REG_D25 = 66;; let _ARM64_REG_D26 = 67;; let _ARM64_REG_D27 = 68;; let _ARM64_REG_D28 = 69;; let _ARM64_REG_D29 = 70;; let _ARM64_REG_D30 = 71;; let _ARM64_REG_D31 = 72;; let _ARM64_REG_H0 = 73;; let _ARM64_REG_H1 = 74;; let _ARM64_REG_H2 = 75;; let _ARM64_REG_H3 = 76;; let _ARM64_REG_H4 = 77;; let _ARM64_REG_H5 = 78;; let _ARM64_REG_H6 = 79;; let _ARM64_REG_H7 = 80;; let _ARM64_REG_H8 = 81;; let _ARM64_REG_H9 = 82;; let _ARM64_REG_H10 = 83;; let _ARM64_REG_H11 = 84;; let _ARM64_REG_H12 = 85;; let _ARM64_REG_H13 = 86;; let _ARM64_REG_H14 = 87;; let _ARM64_REG_H15 = 88;; let _ARM64_REG_H16 = 89;; let _ARM64_REG_H17 = 90;; let _ARM64_REG_H18 = 91;; let _ARM64_REG_H19 = 92;; let _ARM64_REG_H20 = 93;; let _ARM64_REG_H21 = 94;; let _ARM64_REG_H22 = 95;; let _ARM64_REG_H23 = 96;; let _ARM64_REG_H24 = 97;; let _ARM64_REG_H25 = 98;; let _ARM64_REG_H26 = 99;; let _ARM64_REG_H27 = 100;; let _ARM64_REG_H28 = 101;; let _ARM64_REG_H29 = 102;; let _ARM64_REG_H30 = 103;; let _ARM64_REG_H31 = 104;; let _ARM64_REG_P0 = 105;; let _ARM64_REG_P1 = 106;; let _ARM64_REG_P2 = 107;; let _ARM64_REG_P3 = 108;; let _ARM64_REG_P4 = 109;; let _ARM64_REG_P5 = 110;; let _ARM64_REG_P6 = 111;; let _ARM64_REG_P7 = 112;; let _ARM64_REG_P8 = 113;; let _ARM64_REG_P9 = 114;; let _ARM64_REG_P10 = 115;; let _ARM64_REG_P11 = 116;; let _ARM64_REG_P12 = 117;; let _ARM64_REG_P13 = 118;; let _ARM64_REG_P14 = 119;; let _ARM64_REG_P15 = 120;; let _ARM64_REG_Q0 = 121;; let _ARM64_REG_Q1 = 122;; let _ARM64_REG_Q2 = 123;; let _ARM64_REG_Q3 = 124;; let _ARM64_REG_Q4 = 125;; let _ARM64_REG_Q5 = 126;; let _ARM64_REG_Q6 = 127;; let _ARM64_REG_Q7 = 128;; let _ARM64_REG_Q8 = 129;; let _ARM64_REG_Q9 = 130;; let _ARM64_REG_Q10 = 131;; let _ARM64_REG_Q11 = 132;; let _ARM64_REG_Q12 = 133;; let _ARM64_REG_Q13 = 134;; let _ARM64_REG_Q14 = 135;; let _ARM64_REG_Q15 = 136;; let _ARM64_REG_Q16 = 137;; let _ARM64_REG_Q17 = 138;; let _ARM64_REG_Q18 = 139;; let _ARM64_REG_Q19 = 140;; let _ARM64_REG_Q20 = 141;; let _ARM64_REG_Q21 = 142;; let _ARM64_REG_Q22 = 143;; let _ARM64_REG_Q23 = 144;; let _ARM64_REG_Q24 = 145;; let _ARM64_REG_Q25 = 146;; let _ARM64_REG_Q26 = 147;; let _ARM64_REG_Q27 = 148;; let _ARM64_REG_Q28 = 149;; let _ARM64_REG_Q29 = 150;; let _ARM64_REG_Q30 = 151;; let _ARM64_REG_Q31 = 152;; let _ARM64_REG_S0 = 153;; let _ARM64_REG_S1 = 154;; let _ARM64_REG_S2 = 155;; let _ARM64_REG_S3 = 156;; let _ARM64_REG_S4 = 157;; let _ARM64_REG_S5 = 158;; let _ARM64_REG_S6 = 159;; let _ARM64_REG_S7 = 160;; let _ARM64_REG_S8 = 161;; let _ARM64_REG_S9 = 162;; let _ARM64_REG_S10 = 163;; let _ARM64_REG_S11 = 164;; let _ARM64_REG_S12 = 165;; let _ARM64_REG_S13 = 166;; let _ARM64_REG_S14 = 167;; let _ARM64_REG_S15 = 168;; let _ARM64_REG_S16 = 169;; let _ARM64_REG_S17 = 170;; let _ARM64_REG_S18 = 171;; let _ARM64_REG_S19 = 172;; let _ARM64_REG_S20 = 173;; let _ARM64_REG_S21 = 174;; let _ARM64_REG_S22 = 175;; let _ARM64_REG_S23 = 176;; let _ARM64_REG_S24 = 177;; let _ARM64_REG_S25 = 178;; let _ARM64_REG_S26 = 179;; let _ARM64_REG_S27 = 180;; let _ARM64_REG_S28 = 181;; let _ARM64_REG_S29 = 182;; let _ARM64_REG_S30 = 183;; let _ARM64_REG_S31 = 184;; let _ARM64_REG_W0 = 185;; let _ARM64_REG_W1 = 186;; let _ARM64_REG_W2 = 187;; let _ARM64_REG_W3 = 188;; let _ARM64_REG_W4 = 189;; let _ARM64_REG_W5 = 190;; let _ARM64_REG_W6 = 191;; let _ARM64_REG_W7 = 192;; let _ARM64_REG_W8 = 193;; let _ARM64_REG_W9 = 194;; let _ARM64_REG_W10 = 195;; let _ARM64_REG_W11 = 196;; let _ARM64_REG_W12 = 197;; let _ARM64_REG_W13 = 198;; let _ARM64_REG_W14 = 199;; let _ARM64_REG_W15 = 200;; let _ARM64_REG_W16 = 201;; let _ARM64_REG_W17 = 202;; let _ARM64_REG_W18 = 203;; let _ARM64_REG_W19 = 204;; let _ARM64_REG_W20 = 205;; let _ARM64_REG_W21 = 206;; let _ARM64_REG_W22 = 207;; let _ARM64_REG_W23 = 208;; let _ARM64_REG_W24 = 209;; let _ARM64_REG_W25 = 210;; let _ARM64_REG_W26 = 211;; let _ARM64_REG_W27 = 212;; let _ARM64_REG_W28 = 213;; let _ARM64_REG_W29 = 214;; let _ARM64_REG_W30 = 215;; let _ARM64_REG_X0 = 216;; let _ARM64_REG_X1 = 217;; let _ARM64_REG_X2 = 218;; let _ARM64_REG_X3 = 219;; let _ARM64_REG_X4 = 220;; let _ARM64_REG_X5 = 221;; let _ARM64_REG_X6 = 222;; let _ARM64_REG_X7 = 223;; let _ARM64_REG_X8 = 224;; let _ARM64_REG_X9 = 225;; let _ARM64_REG_X10 = 226;; let _ARM64_REG_X11 = 227;; let _ARM64_REG_X12 = 228;; let _ARM64_REG_X13 = 229;; let _ARM64_REG_X14 = 230;; let _ARM64_REG_X15 = 231;; let _ARM64_REG_X16 = 232;; let _ARM64_REG_X17 = 233;; let _ARM64_REG_X18 = 234;; let _ARM64_REG_X19 = 235;; let _ARM64_REG_X20 = 236;; let _ARM64_REG_X21 = 237;; let _ARM64_REG_X22 = 238;; let _ARM64_REG_X23 = 239;; let _ARM64_REG_X24 = 240;; let _ARM64_REG_X25 = 241;; let _ARM64_REG_X26 = 242;; let _ARM64_REG_X27 = 243;; let _ARM64_REG_X28 = 244;; let _ARM64_REG_Z0 = 245;; let _ARM64_REG_Z1 = 246;; let _ARM64_REG_Z2 = 247;; let _ARM64_REG_Z3 = 248;; let _ARM64_REG_Z4 = 249;; let _ARM64_REG_Z5 = 250;; let _ARM64_REG_Z6 = 251;; let _ARM64_REG_Z7 = 252;; let _ARM64_REG_Z8 = 253;; let _ARM64_REG_Z9 = 254;; let _ARM64_REG_Z10 = 255;; let _ARM64_REG_Z11 = 256;; let _ARM64_REG_Z12 = 257;; let _ARM64_REG_Z13 = 258;; let _ARM64_REG_Z14 = 259;; let _ARM64_REG_Z15 = 260;; let _ARM64_REG_Z16 = 261;; let _ARM64_REG_Z17 = 262;; let _ARM64_REG_Z18 = 263;; let _ARM64_REG_Z19 = 264;; let _ARM64_REG_Z20 = 265;; let _ARM64_REG_Z21 = 266;; let _ARM64_REG_Z22 = 267;; let _ARM64_REG_Z23 = 268;; let _ARM64_REG_Z24 = 269;; let _ARM64_REG_Z25 = 270;; let _ARM64_REG_Z26 = 271;; let _ARM64_REG_Z27 = 272;; let _ARM64_REG_Z28 = 273;; let _ARM64_REG_Z29 = 274;; let _ARM64_REG_Z30 = 275;; let _ARM64_REG_Z31 = 276;; let _ARM64_REG_V0 = 277;; let _ARM64_REG_V1 = 278;; let _ARM64_REG_V2 = 279;; let _ARM64_REG_V3 = 280;; let _ARM64_REG_V4 = 281;; let _ARM64_REG_V5 = 282;; let _ARM64_REG_V6 = 283;; let _ARM64_REG_V7 = 284;; let _ARM64_REG_V8 = 285;; let _ARM64_REG_V9 = 286;; let _ARM64_REG_V10 = 287;; let _ARM64_REG_V11 = 288;; let _ARM64_REG_V12 = 289;; let _ARM64_REG_V13 = 290;; let _ARM64_REG_V14 = 291;; let _ARM64_REG_V15 = 292;; let _ARM64_REG_V16 = 293;; let _ARM64_REG_V17 = 294;; let _ARM64_REG_V18 = 295;; let _ARM64_REG_V19 = 296;; let _ARM64_REG_V20 = 297;; let _ARM64_REG_V21 = 298;; let _ARM64_REG_V22 = 299;; let _ARM64_REG_V23 = 300;; let _ARM64_REG_V24 = 301;; let _ARM64_REG_V25 = 302;; let _ARM64_REG_V26 = 303;; let _ARM64_REG_V27 = 304;; let _ARM64_REG_V28 = 305;; let _ARM64_REG_V29 = 306;; let _ARM64_REG_V30 = 307;; let _ARM64_REG_V31 = 308;; let _ARM64_REG_ENDING = 309;; let _ARM64_REG_IP0 = _ARM64_REG_X16;; let _ARM64_REG_IP1 = _ARM64_REG_X17;; let _ARM64_REG_X29 = _ARM64_REG_FP;; let _ARM64_REG_X30 = _ARM64_REG_LR;; let _ARM64_INS_INVALID = 0;; let _ARM64_INS_ABS = 1;; let _ARM64_INS_ADC = 2;; let _ARM64_INS_ADCS = 3;; let _ARM64_INS_ADD = 4;; let _ARM64_INS_ADDHN = 5;; let _ARM64_INS_ADDHN2 = 6;; let _ARM64_INS_ADDP = 7;; let _ARM64_INS_ADDPL = 8;; let _ARM64_INS_ADDS = 9;; let _ARM64_INS_ADDV = 10;; let _ARM64_INS_ADDVL = 11;; let _ARM64_INS_ADR = 12;; let _ARM64_INS_ADRP = 13;; let _ARM64_INS_AESD = 14;; let _ARM64_INS_AESE = 15;; let _ARM64_INS_AESIMC = 16;; let _ARM64_INS_AESMC = 17;; let _ARM64_INS_AND = 18;; let _ARM64_INS_ANDS = 19;; let _ARM64_INS_ANDV = 20;; let _ARM64_INS_ASR = 21;; let _ARM64_INS_ASRD = 22;; let _ARM64_INS_ASRR = 23;; let _ARM64_INS_ASRV = 24;; let _ARM64_INS_AUTDA = 25;; let _ARM64_INS_AUTDB = 26;; let _ARM64_INS_AUTDZA = 27;; let _ARM64_INS_AUTDZB = 28;; let _ARM64_INS_AUTIA = 29;; let _ARM64_INS_AUTIA1716 = 30;; let _ARM64_INS_AUTIASP = 31;; let _ARM64_INS_AUTIAZ = 32;; let _ARM64_INS_AUTIB = 33;; let _ARM64_INS_AUTIB1716 = 34;; let _ARM64_INS_AUTIBSP = 35;; let _ARM64_INS_AUTIBZ = 36;; let _ARM64_INS_AUTIZA = 37;; let _ARM64_INS_AUTIZB = 38;; let _ARM64_INS_B = 39;; let _ARM64_INS_BCAX = 40;; let _ARM64_INS_BFM = 41;; let _ARM64_INS_BIC = 42;; let _ARM64_INS_BICS = 43;; let _ARM64_INS_BIF = 44;; let _ARM64_INS_BIT = 45;; let _ARM64_INS_BL = 46;; let _ARM64_INS_BLR = 47;; let _ARM64_INS_BLRAA = 48;; let _ARM64_INS_BLRAAZ = 49;; let _ARM64_INS_BLRAB = 50;; let _ARM64_INS_BLRABZ = 51;; let _ARM64_INS_BR = 52;; let _ARM64_INS_BRAA = 53;; let _ARM64_INS_BRAAZ = 54;; let _ARM64_INS_BRAB = 55;; let _ARM64_INS_BRABZ = 56;; let _ARM64_INS_BRK = 57;; let _ARM64_INS_BRKA = 58;; let _ARM64_INS_BRKAS = 59;; let _ARM64_INS_BRKB = 60;; let _ARM64_INS_BRKBS = 61;; let _ARM64_INS_BRKN = 62;; let _ARM64_INS_BRKNS = 63;; let _ARM64_INS_BRKPA = 64;; let _ARM64_INS_BRKPAS = 65;; let _ARM64_INS_BRKPB = 66;; let _ARM64_INS_BRKPBS = 67;; let _ARM64_INS_BSL = 68;; let _ARM64_INS_CAS = 69;; let _ARM64_INS_CASA = 70;; let _ARM64_INS_CASAB = 71;; let _ARM64_INS_CASAH = 72;; let _ARM64_INS_CASAL = 73;; let _ARM64_INS_CASALB = 74;; let _ARM64_INS_CASALH = 75;; let _ARM64_INS_CASB = 76;; let _ARM64_INS_CASH = 77;; let _ARM64_INS_CASL = 78;; let _ARM64_INS_CASLB = 79;; let _ARM64_INS_CASLH = 80;; let _ARM64_INS_CASP = 81;; let _ARM64_INS_CASPA = 82;; let _ARM64_INS_CASPAL = 83;; let _ARM64_INS_CASPL = 84;; let _ARM64_INS_CBNZ = 85;; let _ARM64_INS_CBZ = 86;; let _ARM64_INS_CCMN = 87;; let _ARM64_INS_CCMP = 88;; let _ARM64_INS_CFINV = 89;; let _ARM64_INS_CINC = 90;; let _ARM64_INS_CINV = 91;; let _ARM64_INS_CLASTA = 92;; let _ARM64_INS_CLASTB = 93;; let _ARM64_INS_CLREX = 94;; let _ARM64_INS_CLS = 95;; let _ARM64_INS_CLZ = 96;; let _ARM64_INS_CMEQ = 97;; let _ARM64_INS_CMGE = 98;; let _ARM64_INS_CMGT = 99;; let _ARM64_INS_CMHI = 100;; let _ARM64_INS_CMHS = 101;; let _ARM64_INS_CMLE = 102;; let _ARM64_INS_CMLO = 103;; let _ARM64_INS_CMLS = 104;; let _ARM64_INS_CMLT = 105;; let _ARM64_INS_CMN = 106;; let _ARM64_INS_CMP = 107;; let _ARM64_INS_CMPEQ = 108;; let _ARM64_INS_CMPGE = 109;; let _ARM64_INS_CMPGT = 110;; let _ARM64_INS_CMPHI = 111;; let _ARM64_INS_CMPHS = 112;; let _ARM64_INS_CMPLE = 113;; let _ARM64_INS_CMPLO = 114;; let _ARM64_INS_CMPLS = 115;; let _ARM64_INS_CMPLT = 116;; let _ARM64_INS_CMPNE = 117;; let _ARM64_INS_CMTST = 118;; let _ARM64_INS_CNEG = 119;; let _ARM64_INS_CNOT = 120;; let _ARM64_INS_CNT = 121;; let _ARM64_INS_CNTB = 122;; let _ARM64_INS_CNTD = 123;; let _ARM64_INS_CNTH = 124;; let _ARM64_INS_CNTP = 125;; let _ARM64_INS_CNTW = 126;; let _ARM64_INS_COMPACT = 127;; let _ARM64_INS_CPY = 128;; let _ARM64_INS_CRC32B = 129;; let _ARM64_INS_CRC32CB = 130;; let _ARM64_INS_CRC32CH = 131;; let _ARM64_INS_CRC32CW = 132;; let _ARM64_INS_CRC32CX = 133;; let _ARM64_INS_CRC32H = 134;; let _ARM64_INS_CRC32W = 135;; let _ARM64_INS_CRC32X = 136;; let _ARM64_INS_CSDB = 137;; let _ARM64_INS_CSEL = 138;; let _ARM64_INS_CSET = 139;; let _ARM64_INS_CSETM = 140;; let _ARM64_INS_CSINC = 141;; let _ARM64_INS_CSINV = 142;; let _ARM64_INS_CSNEG = 143;; let _ARM64_INS_CTERMEQ = 144;; let _ARM64_INS_CTERMNE = 145;; let _ARM64_INS_DCPS1 = 146;; let _ARM64_INS_DCPS2 = 147;; let _ARM64_INS_DCPS3 = 148;; let _ARM64_INS_DECB = 149;; let _ARM64_INS_DECD = 150;; let _ARM64_INS_DECH = 151;; let _ARM64_INS_DECP = 152;; let _ARM64_INS_DECW = 153;; let _ARM64_INS_DMB = 154;; let _ARM64_INS_DRPS = 155;; let _ARM64_INS_DSB = 156;; let _ARM64_INS_DUP = 157;; let _ARM64_INS_DUPM = 158;; let _ARM64_INS_EON = 159;; let _ARM64_INS_EOR = 160;; let _ARM64_INS_EOR3 = 161;; let _ARM64_INS_EORS = 162;; let _ARM64_INS_EORV = 163;; let _ARM64_INS_ERET = 164;; let _ARM64_INS_ERETAA = 165;; let _ARM64_INS_ERETAB = 166;; let _ARM64_INS_ESB = 167;; let _ARM64_INS_EXT = 168;; let _ARM64_INS_EXTR = 169;; let _ARM64_INS_FABD = 170;; let _ARM64_INS_FABS = 171;; let _ARM64_INS_FACGE = 172;; let _ARM64_INS_FACGT = 173;; let _ARM64_INS_FACLE = 174;; let _ARM64_INS_FACLT = 175;; let _ARM64_INS_FADD = 176;; let _ARM64_INS_FADDA = 177;; let _ARM64_INS_FADDP = 178;; let _ARM64_INS_FADDV = 179;; let _ARM64_INS_FCADD = 180;; let _ARM64_INS_FCCMP = 181;; let _ARM64_INS_FCCMPE = 182;; let _ARM64_INS_FCMEQ = 183;; let _ARM64_INS_FCMGE = 184;; let _ARM64_INS_FCMGT = 185;; let _ARM64_INS_FCMLA = 186;; let _ARM64_INS_FCMLE = 187;; let _ARM64_INS_FCMLT = 188;; let _ARM64_INS_FCMNE = 189;; let _ARM64_INS_FCMP = 190;; let _ARM64_INS_FCMPE = 191;; let _ARM64_INS_FCMUO = 192;; let _ARM64_INS_FCPY = 193;; let _ARM64_INS_FCSEL = 194;; let _ARM64_INS_FCVT = 195;; let _ARM64_INS_FCVTAS = 196;; let _ARM64_INS_FCVTAU = 197;; let _ARM64_INS_FCVTL = 198;; let _ARM64_INS_FCVTL2 = 199;; let _ARM64_INS_FCVTMS = 200;; let _ARM64_INS_FCVTMU = 201;; let _ARM64_INS_FCVTN = 202;; let _ARM64_INS_FCVTN2 = 203;; let _ARM64_INS_FCVTNS = 204;; let _ARM64_INS_FCVTNU = 205;; let _ARM64_INS_FCVTPS = 206;; let _ARM64_INS_FCVTPU = 207;; let _ARM64_INS_FCVTXN = 208;; let _ARM64_INS_FCVTXN2 = 209;; let _ARM64_INS_FCVTZS = 210;; let _ARM64_INS_FCVTZU = 211;; let _ARM64_INS_FDIV = 212;; let _ARM64_INS_FDIVR = 213;; let _ARM64_INS_FDUP = 214;; let _ARM64_INS_FEXPA = 215;; let _ARM64_INS_FJCVTZS = 216;; let _ARM64_INS_FMAD = 217;; let _ARM64_INS_FMADD = 218;; let _ARM64_INS_FMAX = 219;; let _ARM64_INS_FMAXNM = 220;; let _ARM64_INS_FMAXNMP = 221;; let _ARM64_INS_FMAXNMV = 222;; let _ARM64_INS_FMAXP = 223;; let _ARM64_INS_FMAXV = 224;; let _ARM64_INS_FMIN = 225;; let _ARM64_INS_FMINNM = 226;; let _ARM64_INS_FMINNMP = 227;; let _ARM64_INS_FMINNMV = 228;; let _ARM64_INS_FMINP = 229;; let _ARM64_INS_FMINV = 230;; let _ARM64_INS_FMLA = 231;; let _ARM64_INS_FMLS = 232;; let _ARM64_INS_FMOV = 233;; let _ARM64_INS_FMSB = 234;; let _ARM64_INS_FMSUB = 235;; let _ARM64_INS_FMUL = 236;; let _ARM64_INS_FMULX = 237;; let _ARM64_INS_FNEG = 238;; let _ARM64_INS_FNMAD = 239;; let _ARM64_INS_FNMADD = 240;; let _ARM64_INS_FNMLA = 241;; let _ARM64_INS_FNMLS = 242;; let _ARM64_INS_FNMSB = 243;; let _ARM64_INS_FNMSUB = 244;; let _ARM64_INS_FNMUL = 245;; let _ARM64_INS_FRECPE = 246;; let _ARM64_INS_FRECPS = 247;; let _ARM64_INS_FRECPX = 248;; let _ARM64_INS_FRINTA = 249;; let _ARM64_INS_FRINTI = 250;; let _ARM64_INS_FRINTM = 251;; let _ARM64_INS_FRINTN = 252;; let _ARM64_INS_FRINTP = 253;; let _ARM64_INS_FRINTX = 254;; let _ARM64_INS_FRINTZ = 255;; let _ARM64_INS_FRSQRTE = 256;; let _ARM64_INS_FRSQRTS = 257;; let _ARM64_INS_FSCALE = 258;; let _ARM64_INS_FSQRT = 259;; let _ARM64_INS_FSUB = 260;; let _ARM64_INS_FSUBR = 261;; let _ARM64_INS_FTMAD = 262;; let _ARM64_INS_FTSMUL = 263;; let _ARM64_INS_FTSSEL = 264;; let _ARM64_INS_HINT = 265;; let _ARM64_INS_HLT = 266;; let _ARM64_INS_HVC = 267;; let _ARM64_INS_INCB = 268;; let _ARM64_INS_INCD = 269;; let _ARM64_INS_INCH = 270;; let _ARM64_INS_INCP = 271;; let _ARM64_INS_INCW = 272;; let _ARM64_INS_INDEX = 273;; let _ARM64_INS_INS = 274;; let _ARM64_INS_INSR = 275;; let _ARM64_INS_ISB = 276;; let _ARM64_INS_LASTA = 277;; let _ARM64_INS_LASTB = 278;; let _ARM64_INS_LD1 = 279;; let _ARM64_INS_LD1B = 280;; let _ARM64_INS_LD1D = 281;; let _ARM64_INS_LD1H = 282;; let _ARM64_INS_LD1R = 283;; let _ARM64_INS_LD1RB = 284;; let _ARM64_INS_LD1RD = 285;; let _ARM64_INS_LD1RH = 286;; let _ARM64_INS_LD1RQB = 287;; let _ARM64_INS_LD1RQD = 288;; let _ARM64_INS_LD1RQH = 289;; let _ARM64_INS_LD1RQW = 290;; let _ARM64_INS_LD1RSB = 291;; let _ARM64_INS_LD1RSH = 292;; let _ARM64_INS_LD1RSW = 293;; let _ARM64_INS_LD1RW = 294;; let _ARM64_INS_LD1SB = 295;; let _ARM64_INS_LD1SH = 296;; let _ARM64_INS_LD1SW = 297;; let _ARM64_INS_LD1W = 298;; let _ARM64_INS_LD2 = 299;; let _ARM64_INS_LD2B = 300;; let _ARM64_INS_LD2D = 301;; let _ARM64_INS_LD2H = 302;; let _ARM64_INS_LD2R = 303;; let _ARM64_INS_LD2W = 304;; let _ARM64_INS_LD3 = 305;; let _ARM64_INS_LD3B = 306;; let _ARM64_INS_LD3D = 307;; let _ARM64_INS_LD3H = 308;; let _ARM64_INS_LD3R = 309;; let _ARM64_INS_LD3W = 310;; let _ARM64_INS_LD4 = 311;; let _ARM64_INS_LD4B = 312;; let _ARM64_INS_LD4D = 313;; let _ARM64_INS_LD4H = 314;; let _ARM64_INS_LD4R = 315;; let _ARM64_INS_LD4W = 316;; let _ARM64_INS_LDADD = 317;; let _ARM64_INS_LDADDA = 318;; let _ARM64_INS_LDADDAB = 319;; let _ARM64_INS_LDADDAH = 320;; let _ARM64_INS_LDADDAL = 321;; let _ARM64_INS_LDADDALB = 322;; let _ARM64_INS_LDADDALH = 323;; let _ARM64_INS_LDADDB = 324;; let _ARM64_INS_LDADDH = 325;; let _ARM64_INS_LDADDL = 326;; let _ARM64_INS_LDADDLB = 327;; let _ARM64_INS_LDADDLH = 328;; let _ARM64_INS_LDAPR = 329;; let _ARM64_INS_LDAPRB = 330;; let _ARM64_INS_LDAPRH = 331;; let _ARM64_INS_LDAPUR = 332;; let _ARM64_INS_LDAPURB = 333;; let _ARM64_INS_LDAPURH = 334;; let _ARM64_INS_LDAPURSB = 335;; let _ARM64_INS_LDAPURSH = 336;; let _ARM64_INS_LDAPURSW = 337;; let _ARM64_INS_LDAR = 338;; let _ARM64_INS_LDARB = 339;; let _ARM64_INS_LDARH = 340;; let _ARM64_INS_LDAXP = 341;; let _ARM64_INS_LDAXR = 342;; let _ARM64_INS_LDAXRB = 343;; let _ARM64_INS_LDAXRH = 344;; let _ARM64_INS_LDCLR = 345;; let _ARM64_INS_LDCLRA = 346;; let _ARM64_INS_LDCLRAB = 347;; let _ARM64_INS_LDCLRAH = 348;; let _ARM64_INS_LDCLRAL = 349;; let _ARM64_INS_LDCLRALB = 350;; let _ARM64_INS_LDCLRALH = 351;; let _ARM64_INS_LDCLRB = 352;; let _ARM64_INS_LDCLRH = 353;; let _ARM64_INS_LDCLRL = 354;; let _ARM64_INS_LDCLRLB = 355;; let _ARM64_INS_LDCLRLH = 356;; let _ARM64_INS_LDEOR = 357;; let _ARM64_INS_LDEORA = 358;; let _ARM64_INS_LDEORAB = 359;; let _ARM64_INS_LDEORAH = 360;; let _ARM64_INS_LDEORAL = 361;; let _ARM64_INS_LDEORALB = 362;; let _ARM64_INS_LDEORALH = 363;; let _ARM64_INS_LDEORB = 364;; let _ARM64_INS_LDEORH = 365;; let _ARM64_INS_LDEORL = 366;; let _ARM64_INS_LDEORLB = 367;; let _ARM64_INS_LDEORLH = 368;; let _ARM64_INS_LDFF1B = 369;; let _ARM64_INS_LDFF1D = 370;; let _ARM64_INS_LDFF1H = 371;; let _ARM64_INS_LDFF1SB = 372;; let _ARM64_INS_LDFF1SH = 373;; let _ARM64_INS_LDFF1SW = 374;; let _ARM64_INS_LDFF1W = 375;; let _ARM64_INS_LDLAR = 376;; let _ARM64_INS_LDLARB = 377;; let _ARM64_INS_LDLARH = 378;; let _ARM64_INS_LDNF1B = 379;; let _ARM64_INS_LDNF1D = 380;; let _ARM64_INS_LDNF1H = 381;; let _ARM64_INS_LDNF1SB = 382;; let _ARM64_INS_LDNF1SH = 383;; let _ARM64_INS_LDNF1SW = 384;; let _ARM64_INS_LDNF1W = 385;; let _ARM64_INS_LDNP = 386;; let _ARM64_INS_LDNT1B = 387;; let _ARM64_INS_LDNT1D = 388;; let _ARM64_INS_LDNT1H = 389;; let _ARM64_INS_LDNT1W = 390;; let _ARM64_INS_LDP = 391;; let _ARM64_INS_LDPSW = 392;; let _ARM64_INS_LDR = 393;; let _ARM64_INS_LDRAA = 394;; let _ARM64_INS_LDRAB = 395;; let _ARM64_INS_LDRB = 396;; let _ARM64_INS_LDRH = 397;; let _ARM64_INS_LDRSB = 398;; let _ARM64_INS_LDRSH = 399;; let _ARM64_INS_LDRSW = 400;; let _ARM64_INS_LDSET = 401;; let _ARM64_INS_LDSETA = 402;; let _ARM64_INS_LDSETAB = 403;; let _ARM64_INS_LDSETAH = 404;; let _ARM64_INS_LDSETAL = 405;; let _ARM64_INS_LDSETALB = 406;; let _ARM64_INS_LDSETALH = 407;; let _ARM64_INS_LDSETB = 408;; let _ARM64_INS_LDSETH = 409;; let _ARM64_INS_LDSETL = 410;; let _ARM64_INS_LDSETLB = 411;; let _ARM64_INS_LDSETLH = 412;; let _ARM64_INS_LDSMAX = 413;; let _ARM64_INS_LDSMAXA = 414;; let _ARM64_INS_LDSMAXAB = 415;; let _ARM64_INS_LDSMAXAH = 416;; let _ARM64_INS_LDSMAXAL = 417;; let _ARM64_INS_LDSMAXALB = 418;; let _ARM64_INS_LDSMAXALH = 419;; let _ARM64_INS_LDSMAXB = 420;; let _ARM64_INS_LDSMAXH = 421;; let _ARM64_INS_LDSMAXL = 422;; let _ARM64_INS_LDSMAXLB = 423;; let _ARM64_INS_LDSMAXLH = 424;; let _ARM64_INS_LDSMIN = 425;; let _ARM64_INS_LDSMINA = 426;; let _ARM64_INS_LDSMINAB = 427;; let _ARM64_INS_LDSMINAH = 428;; let _ARM64_INS_LDSMINAL = 429;; let _ARM64_INS_LDSMINALB = 430;; let _ARM64_INS_LDSMINALH = 431;; let _ARM64_INS_LDSMINB = 432;; let _ARM64_INS_LDSMINH = 433;; let _ARM64_INS_LDSMINL = 434;; let _ARM64_INS_LDSMINLB = 435;; let _ARM64_INS_LDSMINLH = 436;; let _ARM64_INS_LDTR = 437;; let _ARM64_INS_LDTRB = 438;; let _ARM64_INS_LDTRH = 439;; let _ARM64_INS_LDTRSB = 440;; let _ARM64_INS_LDTRSH = 441;; let _ARM64_INS_LDTRSW = 442;; let _ARM64_INS_LDUMAX = 443;; let _ARM64_INS_LDUMAXA = 444;; let _ARM64_INS_LDUMAXAB = 445;; let _ARM64_INS_LDUMAXAH = 446;; let _ARM64_INS_LDUMAXAL = 447;; let _ARM64_INS_LDUMAXALB = 448;; let _ARM64_INS_LDUMAXALH = 449;; let _ARM64_INS_LDUMAXB = 450;; let _ARM64_INS_LDUMAXH = 451;; let _ARM64_INS_LDUMAXL = 452;; let _ARM64_INS_LDUMAXLB = 453;; let _ARM64_INS_LDUMAXLH = 454;; let _ARM64_INS_LDUMIN = 455;; let _ARM64_INS_LDUMINA = 456;; let _ARM64_INS_LDUMINAB = 457;; let _ARM64_INS_LDUMINAH = 458;; let _ARM64_INS_LDUMINAL = 459;; let _ARM64_INS_LDUMINALB = 460;; let _ARM64_INS_LDUMINALH = 461;; let _ARM64_INS_LDUMINB = 462;; let _ARM64_INS_LDUMINH = 463;; let _ARM64_INS_LDUMINL = 464;; let _ARM64_INS_LDUMINLB = 465;; let _ARM64_INS_LDUMINLH = 466;; let _ARM64_INS_LDUR = 467;; let _ARM64_INS_LDURB = 468;; let _ARM64_INS_LDURH = 469;; let _ARM64_INS_LDURSB = 470;; let _ARM64_INS_LDURSH = 471;; let _ARM64_INS_LDURSW = 472;; let _ARM64_INS_LDXP = 473;; let _ARM64_INS_LDXR = 474;; let _ARM64_INS_LDXRB = 475;; let _ARM64_INS_LDXRH = 476;; let _ARM64_INS_LSL = 477;; let _ARM64_INS_LSLR = 478;; let _ARM64_INS_LSLV = 479;; let _ARM64_INS_LSR = 480;; let _ARM64_INS_LSRR = 481;; let _ARM64_INS_LSRV = 482;; let _ARM64_INS_MAD = 483;; let _ARM64_INS_MADD = 484;; let _ARM64_INS_MLA = 485;; let _ARM64_INS_MLS = 486;; let _ARM64_INS_MNEG = 487;; let _ARM64_INS_MOV = 488;; let _ARM64_INS_MOVI = 489;; let _ARM64_INS_MOVK = 490;; let _ARM64_INS_MOVN = 491;; let _ARM64_INS_MOVPRFX = 492;; let _ARM64_INS_MOVS = 493;; let _ARM64_INS_MOVZ = 494;; let _ARM64_INS_MRS = 495;; let _ARM64_INS_MSB = 496;; let _ARM64_INS_MSR = 497;; let _ARM64_INS_MSUB = 498;; let _ARM64_INS_MUL = 499;; let _ARM64_INS_MVN = 500;; let _ARM64_INS_MVNI = 501;; let _ARM64_INS_NAND = 502;; let _ARM64_INS_NANDS = 503;; let _ARM64_INS_NEG = 504;; let _ARM64_INS_NEGS = 505;; let _ARM64_INS_NGC = 506;; let _ARM64_INS_NGCS = 507;; let _ARM64_INS_NOP = 508;; let _ARM64_INS_NOR = 509;; let _ARM64_INS_NORS = 510;; let _ARM64_INS_NOT = 511;; let _ARM64_INS_NOTS = 512;; let _ARM64_INS_ORN = 513;; let _ARM64_INS_ORNS = 514;; let _ARM64_INS_ORR = 515;; let _ARM64_INS_ORRS = 516;; let _ARM64_INS_ORV = 517;; let _ARM64_INS_PACDA = 518;; let _ARM64_INS_PACDB = 519;; let _ARM64_INS_PACDZA = 520;; let _ARM64_INS_PACDZB = 521;; let _ARM64_INS_PACGA = 522;; let _ARM64_INS_PACIA = 523;; let _ARM64_INS_PACIA1716 = 524;; let _ARM64_INS_PACIASP = 525;; let _ARM64_INS_PACIAZ = 526;; let _ARM64_INS_PACIB = 527;; let _ARM64_INS_PACIB1716 = 528;; let _ARM64_INS_PACIBSP = 529;; let _ARM64_INS_PACIBZ = 530;; let _ARM64_INS_PACIZA = 531;; let _ARM64_INS_PACIZB = 532;; let _ARM64_INS_PFALSE = 533;; let _ARM64_INS_PFIRST = 534;; let _ARM64_INS_PMUL = 535;; let _ARM64_INS_PMULL = 536;; let _ARM64_INS_PMULL2 = 537;; let _ARM64_INS_PNEXT = 538;; let _ARM64_INS_PRFB = 539;; let _ARM64_INS_PRFD = 540;; let _ARM64_INS_PRFH = 541;; let _ARM64_INS_PRFM = 542;; let _ARM64_INS_PRFUM = 543;; let _ARM64_INS_PRFW = 544;; let _ARM64_INS_PSB = 545;; let _ARM64_INS_PTEST = 546;; let _ARM64_INS_PTRUE = 547;; let _ARM64_INS_PTRUES = 548;; let _ARM64_INS_PUNPKHI = 549;; let _ARM64_INS_PUNPKLO = 550;; let _ARM64_INS_RADDHN = 551;; let _ARM64_INS_RADDHN2 = 552;; let _ARM64_INS_RAX1 = 553;; let _ARM64_INS_RBIT = 554;; let _ARM64_INS_RDFFR = 555;; let _ARM64_INS_RDFFRS = 556;; let _ARM64_INS_RDVL = 557;; let _ARM64_INS_RET = 558;; let _ARM64_INS_RETAA = 559;; let _ARM64_INS_RETAB = 560;; let _ARM64_INS_REV = 561;; let _ARM64_INS_REV16 = 562;; let _ARM64_INS_REV32 = 563;; let _ARM64_INS_REV64 = 564;; let _ARM64_INS_REVB = 565;; let _ARM64_INS_REVH = 566;; let _ARM64_INS_REVW = 567;; let _ARM64_INS_RMIF = 568;; let _ARM64_INS_ROR = 569;; let _ARM64_INS_RORV = 570;; let _ARM64_INS_RSHRN = 571;; let _ARM64_INS_RSHRN2 = 572;; let _ARM64_INS_RSUBHN = 573;; let _ARM64_INS_RSUBHN2 = 574;; let _ARM64_INS_SABA = 575;; let _ARM64_INS_SABAL = 576;; let _ARM64_INS_SABAL2 = 577;; let _ARM64_INS_SABD = 578;; let _ARM64_INS_SABDL = 579;; let _ARM64_INS_SABDL2 = 580;; let _ARM64_INS_SADALP = 581;; let _ARM64_INS_SADDL = 582;; let _ARM64_INS_SADDL2 = 583;; let _ARM64_INS_SADDLP = 584;; let _ARM64_INS_SADDLV = 585;; let _ARM64_INS_SADDV = 586;; let _ARM64_INS_SADDW = 587;; let _ARM64_INS_SADDW2 = 588;; let _ARM64_INS_SBC = 589;; let _ARM64_INS_SBCS = 590;; let _ARM64_INS_SBFM = 591;; let _ARM64_INS_SCVTF = 592;; let _ARM64_INS_SDIV = 593;; let _ARM64_INS_SDIVR = 594;; let _ARM64_INS_SDOT = 595;; let _ARM64_INS_SEL = 596;; let _ARM64_INS_SETF16 = 597;; let _ARM64_INS_SETF8 = 598;; let _ARM64_INS_SETFFR = 599;; let _ARM64_INS_SEV = 600;; let _ARM64_INS_SEVL = 601;; let _ARM64_INS_SHA1C = 602;; let _ARM64_INS_SHA1H = 603;; let _ARM64_INS_SHA1M = 604;; let _ARM64_INS_SHA1P = 605;; let _ARM64_INS_SHA1SU0 = 606;; let _ARM64_INS_SHA1SU1 = 607;; let _ARM64_INS_SHA256H = 608;; let _ARM64_INS_SHA256H2 = 609;; let _ARM64_INS_SHA256SU0 = 610;; let _ARM64_INS_SHA256SU1 = 611;; let _ARM64_INS_SHA512H = 612;; let _ARM64_INS_SHA512H2 = 613;; let _ARM64_INS_SHA512SU0 = 614;; let _ARM64_INS_SHA512SU1 = 615;; let _ARM64_INS_SHADD = 616;; let _ARM64_INS_SHL = 617;; let _ARM64_INS_SHLL = 618;; let _ARM64_INS_SHLL2 = 619;; let _ARM64_INS_SHRN = 620;; let _ARM64_INS_SHRN2 = 621;; let _ARM64_INS_SHSUB = 622;; let _ARM64_INS_SLI = 623;; let _ARM64_INS_SM3PARTW1 = 624;; let _ARM64_INS_SM3PARTW2 = 625;; let _ARM64_INS_SM3SS1 = 626;; let _ARM64_INS_SM3TT1A = 627;; let _ARM64_INS_SM3TT1B = 628;; let _ARM64_INS_SM3TT2A = 629;; let _ARM64_INS_SM3TT2B = 630;; let _ARM64_INS_SM4E = 631;; let _ARM64_INS_SM4EKEY = 632;; let _ARM64_INS_SMADDL = 633;; let _ARM64_INS_SMAX = 634;; let _ARM64_INS_SMAXP = 635;; let _ARM64_INS_SMAXV = 636;; let _ARM64_INS_SMC = 637;; let _ARM64_INS_SMIN = 638;; let _ARM64_INS_SMINP = 639;; let _ARM64_INS_SMINV = 640;; let _ARM64_INS_SMLAL = 641;; let _ARM64_INS_SMLAL2 = 642;; let _ARM64_INS_SMLSL = 643;; let _ARM64_INS_SMLSL2 = 644;; let _ARM64_INS_SMNEGL = 645;; let _ARM64_INS_SMOV = 646;; let _ARM64_INS_SMSUBL = 647;; let _ARM64_INS_SMULH = 648;; let _ARM64_INS_SMULL = 649;; let _ARM64_INS_SMULL2 = 650;; let _ARM64_INS_SPLICE = 651;; let _ARM64_INS_SQABS = 652;; let _ARM64_INS_SQADD = 653;; let _ARM64_INS_SQDECB = 654;; let _ARM64_INS_SQDECD = 655;; let _ARM64_INS_SQDECH = 656;; let _ARM64_INS_SQDECP = 657;; let _ARM64_INS_SQDECW = 658;; let _ARM64_INS_SQDMLAL = 659;; let _ARM64_INS_SQDMLAL2 = 660;; let _ARM64_INS_SQDMLSL = 661;; let _ARM64_INS_SQDMLSL2 = 662;; let _ARM64_INS_SQDMULH = 663;; let _ARM64_INS_SQDMULL = 664;; let _ARM64_INS_SQDMULL2 = 665;; let _ARM64_INS_SQINCB = 666;; let _ARM64_INS_SQINCD = 667;; let _ARM64_INS_SQINCH = 668;; let _ARM64_INS_SQINCP = 669;; let _ARM64_INS_SQINCW = 670;; let _ARM64_INS_SQNEG = 671;; let _ARM64_INS_SQRDMLAH = 672;; let _ARM64_INS_SQRDMLSH = 673;; let _ARM64_INS_SQRDMULH = 674;; let _ARM64_INS_SQRSHL = 675;; let _ARM64_INS_SQRSHRN = 676;; let _ARM64_INS_SQRSHRN2 = 677;; let _ARM64_INS_SQRSHRUN = 678;; let _ARM64_INS_SQRSHRUN2 = 679;; let _ARM64_INS_SQSHL = 680;; let _ARM64_INS_SQSHLU = 681;; let _ARM64_INS_SQSHRN = 682;; let _ARM64_INS_SQSHRN2 = 683;; let _ARM64_INS_SQSHRUN = 684;; let _ARM64_INS_SQSHRUN2 = 685;; let _ARM64_INS_SQSUB = 686;; let _ARM64_INS_SQXTN = 687;; let _ARM64_INS_SQXTN2 = 688;; let _ARM64_INS_SQXTUN = 689;; let _ARM64_INS_SQXTUN2 = 690;; let _ARM64_INS_SRHADD = 691;; let _ARM64_INS_SRI = 692;; let _ARM64_INS_SRSHL = 693;; let _ARM64_INS_SRSHR = 694;; let _ARM64_INS_SRSRA = 695;; let _ARM64_INS_SSHL = 696;; let _ARM64_INS_SSHLL = 697;; let _ARM64_INS_SSHLL2 = 698;; let _ARM64_INS_SSHR = 699;; let _ARM64_INS_SSRA = 700;; let _ARM64_INS_SSUBL = 701;; let _ARM64_INS_SSUBL2 = 702;; let _ARM64_INS_SSUBW = 703;; let _ARM64_INS_SSUBW2 = 704;; let _ARM64_INS_ST1 = 705;; let _ARM64_INS_ST1B = 706;; let _ARM64_INS_ST1D = 707;; let _ARM64_INS_ST1H = 708;; let _ARM64_INS_ST1W = 709;; let _ARM64_INS_ST2 = 710;; let _ARM64_INS_ST2B = 711;; let _ARM64_INS_ST2D = 712;; let _ARM64_INS_ST2H = 713;; let _ARM64_INS_ST2W = 714;; let _ARM64_INS_ST3 = 715;; let _ARM64_INS_ST3B = 716;; let _ARM64_INS_ST3D = 717;; let _ARM64_INS_ST3H = 718;; let _ARM64_INS_ST3W = 719;; let _ARM64_INS_ST4 = 720;; let _ARM64_INS_ST4B = 721;; let _ARM64_INS_ST4D = 722;; let _ARM64_INS_ST4H = 723;; let _ARM64_INS_ST4W = 724;; let _ARM64_INS_STADD = 725;; let _ARM64_INS_STADDB = 726;; let _ARM64_INS_STADDH = 727;; let _ARM64_INS_STADDL = 728;; let _ARM64_INS_STADDLB = 729;; let _ARM64_INS_STADDLH = 730;; let _ARM64_INS_STCLR = 731;; let _ARM64_INS_STCLRB = 732;; let _ARM64_INS_STCLRH = 733;; let _ARM64_INS_STCLRL = 734;; let _ARM64_INS_STCLRLB = 735;; let _ARM64_INS_STCLRLH = 736;; let _ARM64_INS_STEOR = 737;; let _ARM64_INS_STEORB = 738;; let _ARM64_INS_STEORH = 739;; let _ARM64_INS_STEORL = 740;; let _ARM64_INS_STEORLB = 741;; let _ARM64_INS_STEORLH = 742;; let _ARM64_INS_STLLR = 743;; let _ARM64_INS_STLLRB = 744;; let _ARM64_INS_STLLRH = 745;; let _ARM64_INS_STLR = 746;; let _ARM64_INS_STLRB = 747;; let _ARM64_INS_STLRH = 748;; let _ARM64_INS_STLUR = 749;; let _ARM64_INS_STLURB = 750;; let _ARM64_INS_STLURH = 751;; let _ARM64_INS_STLXP = 752;; let _ARM64_INS_STLXR = 753;; let _ARM64_INS_STLXRB = 754;; let _ARM64_INS_STLXRH = 755;; let _ARM64_INS_STNP = 756;; let _ARM64_INS_STNT1B = 757;; let _ARM64_INS_STNT1D = 758;; let _ARM64_INS_STNT1H = 759;; let _ARM64_INS_STNT1W = 760;; let _ARM64_INS_STP = 761;; let _ARM64_INS_STR = 762;; let _ARM64_INS_STRB = 763;; let _ARM64_INS_STRH = 764;; let _ARM64_INS_STSET = 765;; let _ARM64_INS_STSETB = 766;; let _ARM64_INS_STSETH = 767;; let _ARM64_INS_STSETL = 768;; let _ARM64_INS_STSETLB = 769;; let _ARM64_INS_STSETLH = 770;; let _ARM64_INS_STSMAX = 771;; let _ARM64_INS_STSMAXB = 772;; let _ARM64_INS_STSMAXH = 773;; let _ARM64_INS_STSMAXL = 774;; let _ARM64_INS_STSMAXLB = 775;; let _ARM64_INS_STSMAXLH = 776;; let _ARM64_INS_STSMIN = 777;; let _ARM64_INS_STSMINB = 778;; let _ARM64_INS_STSMINH = 779;; let _ARM64_INS_STSMINL = 780;; let _ARM64_INS_STSMINLB = 781;; let _ARM64_INS_STSMINLH = 782;; let _ARM64_INS_STTR = 783;; let _ARM64_INS_STTRB = 784;; let _ARM64_INS_STTRH = 785;; let _ARM64_INS_STUMAX = 786;; let _ARM64_INS_STUMAXB = 787;; let _ARM64_INS_STUMAXH = 788;; let _ARM64_INS_STUMAXL = 789;; let _ARM64_INS_STUMAXLB = 790;; let _ARM64_INS_STUMAXLH = 791;; let _ARM64_INS_STUMIN = 792;; let _ARM64_INS_STUMINB = 793;; let _ARM64_INS_STUMINH = 794;; let _ARM64_INS_STUMINL = 795;; let _ARM64_INS_STUMINLB = 796;; let _ARM64_INS_STUMINLH = 797;; let _ARM64_INS_STUR = 798;; let _ARM64_INS_STURB = 799;; let _ARM64_INS_STURH = 800;; let _ARM64_INS_STXP = 801;; let _ARM64_INS_STXR = 802;; let _ARM64_INS_STXRB = 803;; let _ARM64_INS_STXRH = 804;; let _ARM64_INS_SUB = 805;; let _ARM64_INS_SUBHN = 806;; let _ARM64_INS_SUBHN2 = 807;; let _ARM64_INS_SUBR = 808;; let _ARM64_INS_SUBS = 809;; let _ARM64_INS_SUNPKHI = 810;; let _ARM64_INS_SUNPKLO = 811;; let _ARM64_INS_SUQADD = 812;; let _ARM64_INS_SVC = 813;; let _ARM64_INS_SWP = 814;; let _ARM64_INS_SWPA = 815;; let _ARM64_INS_SWPAB = 816;; let _ARM64_INS_SWPAH = 817;; let _ARM64_INS_SWPAL = 818;; let _ARM64_INS_SWPALB = 819;; let _ARM64_INS_SWPALH = 820;; let _ARM64_INS_SWPB = 821;; let _ARM64_INS_SWPH = 822;; let _ARM64_INS_SWPL = 823;; let _ARM64_INS_SWPLB = 824;; let _ARM64_INS_SWPLH = 825;; let _ARM64_INS_SXTB = 826;; let _ARM64_INS_SXTH = 827;; let _ARM64_INS_SXTL = 828;; let _ARM64_INS_SXTL2 = 829;; let _ARM64_INS_SXTW = 830;; let _ARM64_INS_SYS = 831;; let _ARM64_INS_SYSL = 832;; let _ARM64_INS_TBL = 833;; let _ARM64_INS_TBNZ = 834;; let _ARM64_INS_TBX = 835;; let _ARM64_INS_TBZ = 836;; let _ARM64_INS_TRN1 = 837;; let _ARM64_INS_TRN2 = 838;; let _ARM64_INS_TSB = 839;; let _ARM64_INS_TST = 840;; let _ARM64_INS_UABA = 841;; let _ARM64_INS_UABAL = 842;; let _ARM64_INS_UABAL2 = 843;; let _ARM64_INS_UABD = 844;; let _ARM64_INS_UABDL = 845;; let _ARM64_INS_UABDL2 = 846;; let _ARM64_INS_UADALP = 847;; let _ARM64_INS_UADDL = 848;; let _ARM64_INS_UADDL2 = 849;; let _ARM64_INS_UADDLP = 850;; let _ARM64_INS_UADDLV = 851;; let _ARM64_INS_UADDV = 852;; let _ARM64_INS_UADDW = 853;; let _ARM64_INS_UADDW2 = 854;; let _ARM64_INS_UBFM = 855;; let _ARM64_INS_UCVTF = 856;; let _ARM64_INS_UDIV = 857;; let _ARM64_INS_UDIVR = 858;; let _ARM64_INS_UDOT = 859;; let _ARM64_INS_UHADD = 860;; let _ARM64_INS_UHSUB = 861;; let _ARM64_INS_UMADDL = 862;; let _ARM64_INS_UMAX = 863;; let _ARM64_INS_UMAXP = 864;; let _ARM64_INS_UMAXV = 865;; let _ARM64_INS_UMIN = 866;; let _ARM64_INS_UMINP = 867;; let _ARM64_INS_UMINV = 868;; let _ARM64_INS_UMLAL = 869;; let _ARM64_INS_UMLAL2 = 870;; let _ARM64_INS_UMLSL = 871;; let _ARM64_INS_UMLSL2 = 872;; let _ARM64_INS_UMNEGL = 873;; let _ARM64_INS_UMOV = 874;; let _ARM64_INS_UMSUBL = 875;; let _ARM64_INS_UMULH = 876;; let _ARM64_INS_UMULL = 877;; let _ARM64_INS_UMULL2 = 878;; let _ARM64_INS_UQADD = 879;; let _ARM64_INS_UQDECB = 880;; let _ARM64_INS_UQDECD = 881;; let _ARM64_INS_UQDECH = 882;; let _ARM64_INS_UQDECP = 883;; let _ARM64_INS_UQDECW = 884;; let _ARM64_INS_UQINCB = 885;; let _ARM64_INS_UQINCD = 886;; let _ARM64_INS_UQINCH = 887;; let _ARM64_INS_UQINCP = 888;; let _ARM64_INS_UQINCW = 889;; let _ARM64_INS_UQRSHL = 890;; let _ARM64_INS_UQRSHRN = 891;; let _ARM64_INS_UQRSHRN2 = 892;; let _ARM64_INS_UQSHL = 893;; let _ARM64_INS_UQSHRN = 894;; let _ARM64_INS_UQSHRN2 = 895;; let _ARM64_INS_UQSUB = 896;; let _ARM64_INS_UQXTN = 897;; let _ARM64_INS_UQXTN2 = 898;; let _ARM64_INS_URECPE = 899;; let _ARM64_INS_URHADD = 900;; let _ARM64_INS_URSHL = 901;; let _ARM64_INS_URSHR = 902;; let _ARM64_INS_URSQRTE = 903;; let _ARM64_INS_URSRA = 904;; let _ARM64_INS_USHL = 905;; let _ARM64_INS_USHLL = 906;; let _ARM64_INS_USHLL2 = 907;; let _ARM64_INS_USHR = 908;; let _ARM64_INS_USQADD = 909;; let _ARM64_INS_USRA = 910;; let _ARM64_INS_USUBL = 911;; let _ARM64_INS_USUBL2 = 912;; let _ARM64_INS_USUBW = 913;; let _ARM64_INS_USUBW2 = 914;; let _ARM64_INS_UUNPKHI = 915;; let _ARM64_INS_UUNPKLO = 916;; let _ARM64_INS_UXTB = 917;; let _ARM64_INS_UXTH = 918;; let _ARM64_INS_UXTL = 919;; let _ARM64_INS_UXTL2 = 920;; let _ARM64_INS_UXTW = 921;; let _ARM64_INS_UZP1 = 922;; let _ARM64_INS_UZP2 = 923;; let _ARM64_INS_WFE = 924;; let _ARM64_INS_WFI = 925;; let _ARM64_INS_WHILELE = 926;; let _ARM64_INS_WHILELO = 927;; let _ARM64_INS_WHILELS = 928;; let _ARM64_INS_WHILELT = 929;; let _ARM64_INS_WRFFR = 930;; let _ARM64_INS_XAR = 931;; let _ARM64_INS_XPACD = 932;; let _ARM64_INS_XPACI = 933;; let _ARM64_INS_XPACLRI = 934;; let _ARM64_INS_XTN = 935;; let _ARM64_INS_XTN2 = 936;; let _ARM64_INS_YIELD = 937;; let _ARM64_INS_ZIP1 = 938;; let _ARM64_INS_ZIP2 = 939;; let _ARM64_INS_SBFIZ = 940;; let _ARM64_INS_UBFIZ = 941;; let _ARM64_INS_SBFX = 942;; let _ARM64_INS_UBFX = 943;; let _ARM64_INS_BFI = 944;; let _ARM64_INS_BFXIL = 945;; let _ARM64_INS_IC = 946;; let _ARM64_INS_DC = 947;; let _ARM64_INS_AT = 948;; let _ARM64_INS_TLBI = 949;; let _ARM64_INS_ENDING = 950;; let _ARM64_GRP_INVALID = 0;; let _ARM64_GRP_JUMP = 1;; let _ARM64_GRP_CALL = 2;; let _ARM64_GRP_RET = 3;; let _ARM64_GRP_INT = 4;; let _ARM64_GRP_PRIVILEGE = 6;; let _ARM64_GRP_BRANCH_RELATIVE = 7;; let _ARM64_GRP_PAC = 8;; let _ARM64_GRP_CRYPTO = 128;; let _ARM64_GRP_FPARMV8 = 129;; let _ARM64_GRP_NEON = 130;; let _ARM64_GRP_CRC = 131;; let _ARM64_GRP_AES = 132;; let _ARM64_GRP_DOTPROD = 133;; let _ARM64_GRP_FULLFP16 = 134;; let _ARM64_GRP_LSE = 135;; let _ARM64_GRP_RCPC = 136;; let _ARM64_GRP_RDM = 137;; let _ARM64_GRP_SHA2 = 138;; let _ARM64_GRP_SHA3 = 139;; let _ARM64_GRP_SM4 = 140;; let _ARM64_GRP_SVE = 141;; let _ARM64_GRP_V8_1A = 142;; let _ARM64_GRP_V8_3A = 143;; let _ARM64_GRP_V8_4A = 144;; let _ARM64_GRP_ENDING = 145;; capstone-sys-0.15.0/capstone/bindings/ocaml/arm_const.ml000064400000000000000000000531650072674642500214240ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.ml] *) let _ARM_SFT_INVALID = 0;; let _ARM_SFT_ASR = 1;; let _ARM_SFT_LSL = 2;; let _ARM_SFT_LSR = 3;; let _ARM_SFT_ROR = 4;; let _ARM_SFT_RRX = 5;; let _ARM_SFT_ASR_REG = 6;; let _ARM_SFT_LSL_REG = 7;; let _ARM_SFT_LSR_REG = 8;; let _ARM_SFT_ROR_REG = 9;; let _ARM_SFT_RRX_REG = 10;; let _ARM_CC_INVALID = 0;; let _ARM_CC_EQ = 1;; let _ARM_CC_NE = 2;; let _ARM_CC_HS = 3;; let _ARM_CC_LO = 4;; let _ARM_CC_MI = 5;; let _ARM_CC_PL = 6;; let _ARM_CC_VS = 7;; let _ARM_CC_VC = 8;; let _ARM_CC_HI = 9;; let _ARM_CC_LS = 10;; let _ARM_CC_GE = 11;; let _ARM_CC_LT = 12;; let _ARM_CC_GT = 13;; let _ARM_CC_LE = 14;; let _ARM_CC_AL = 15;; let _ARM_SYSREG_INVALID = 0;; let _ARM_SYSREG_SPSR_C = 1;; let _ARM_SYSREG_SPSR_X = 2;; let _ARM_SYSREG_SPSR_S = 4;; let _ARM_SYSREG_SPSR_F = 8;; let _ARM_SYSREG_CPSR_C = 16;; let _ARM_SYSREG_CPSR_X = 32;; let _ARM_SYSREG_CPSR_S = 64;; let _ARM_SYSREG_CPSR_F = 128;; let _ARM_SYSREG_APSR = 256;; let _ARM_SYSREG_APSR_G = 257;; let _ARM_SYSREG_APSR_NZCVQ = 258;; let _ARM_SYSREG_APSR_NZCVQG = 259;; let _ARM_SYSREG_IAPSR = 260;; let _ARM_SYSREG_IAPSR_G = 261;; let _ARM_SYSREG_IAPSR_NZCVQG = 262;; let _ARM_SYSREG_IAPSR_NZCVQ = 263;; let _ARM_SYSREG_EAPSR = 264;; let _ARM_SYSREG_EAPSR_G = 265;; let _ARM_SYSREG_EAPSR_NZCVQG = 266;; let _ARM_SYSREG_EAPSR_NZCVQ = 267;; let _ARM_SYSREG_XPSR = 268;; let _ARM_SYSREG_XPSR_G = 269;; let _ARM_SYSREG_XPSR_NZCVQG = 270;; let _ARM_SYSREG_XPSR_NZCVQ = 271;; let _ARM_SYSREG_IPSR = 272;; let _ARM_SYSREG_EPSR = 273;; let _ARM_SYSREG_IEPSR = 274;; let _ARM_SYSREG_MSP = 275;; let _ARM_SYSREG_PSP = 276;; let _ARM_SYSREG_PRIMASK = 277;; let _ARM_SYSREG_BASEPRI = 278;; let _ARM_SYSREG_BASEPRI_MAX = 279;; let _ARM_SYSREG_FAULTMASK = 280;; let _ARM_SYSREG_CONTROL = 281;; let _ARM_SYSREG_MSPLIM = 282;; let _ARM_SYSREG_PSPLIM = 283;; let _ARM_SYSREG_MSP_NS = 284;; let _ARM_SYSREG_PSP_NS = 285;; let _ARM_SYSREG_MSPLIM_NS = 286;; let _ARM_SYSREG_PSPLIM_NS = 287;; let _ARM_SYSREG_PRIMASK_NS = 288;; let _ARM_SYSREG_BASEPRI_NS = 289;; let _ARM_SYSREG_FAULTMASK_NS = 290;; let _ARM_SYSREG_CONTROL_NS = 291;; let _ARM_SYSREG_SP_NS = 292;; let _ARM_SYSREG_R8_USR = 293;; let _ARM_SYSREG_R9_USR = 294;; let _ARM_SYSREG_R10_USR = 295;; let _ARM_SYSREG_R11_USR = 296;; let _ARM_SYSREG_R12_USR = 297;; let _ARM_SYSREG_SP_USR = 298;; let _ARM_SYSREG_LR_USR = 299;; let _ARM_SYSREG_R8_FIQ = 300;; let _ARM_SYSREG_R9_FIQ = 301;; let _ARM_SYSREG_R10_FIQ = 302;; let _ARM_SYSREG_R11_FIQ = 303;; let _ARM_SYSREG_R12_FIQ = 304;; let _ARM_SYSREG_SP_FIQ = 305;; let _ARM_SYSREG_LR_FIQ = 306;; let _ARM_SYSREG_LR_IRQ = 307;; let _ARM_SYSREG_SP_IRQ = 308;; let _ARM_SYSREG_LR_SVC = 309;; let _ARM_SYSREG_SP_SVC = 310;; let _ARM_SYSREG_LR_ABT = 311;; let _ARM_SYSREG_SP_ABT = 312;; let _ARM_SYSREG_LR_UND = 313;; let _ARM_SYSREG_SP_UND = 314;; let _ARM_SYSREG_LR_MON = 315;; let _ARM_SYSREG_SP_MON = 316;; let _ARM_SYSREG_ELR_HYP = 317;; let _ARM_SYSREG_SP_HYP = 318;; let _ARM_SYSREG_SPSR_FIQ = 319;; let _ARM_SYSREG_SPSR_IRQ = 320;; let _ARM_SYSREG_SPSR_SVC = 321;; let _ARM_SYSREG_SPSR_ABT = 322;; let _ARM_SYSREG_SPSR_UND = 323;; let _ARM_SYSREG_SPSR_MON = 324;; let _ARM_SYSREG_SPSR_HYP = 325;; let _ARM_MB_INVALID = 0;; let _ARM_MB_RESERVED_0 = 1;; let _ARM_MB_OSHLD = 2;; let _ARM_MB_OSHST = 3;; let _ARM_MB_OSH = 4;; let _ARM_MB_RESERVED_4 = 5;; let _ARM_MB_NSHLD = 6;; let _ARM_MB_NSHST = 7;; let _ARM_MB_NSH = 8;; let _ARM_MB_RESERVED_8 = 9;; let _ARM_MB_ISHLD = 10;; let _ARM_MB_ISHST = 11;; let _ARM_MB_ISH = 12;; let _ARM_MB_RESERVED_12 = 13;; let _ARM_MB_LD = 14;; let _ARM_MB_ST = 15;; let _ARM_MB_SY = 16;; let _ARM_OP_INVALID = 0;; let _ARM_OP_REG = 1;; let _ARM_OP_IMM = 2;; let _ARM_OP_MEM = 3;; let _ARM_OP_FP = 4;; let _ARM_OP_CIMM = 64;; let _ARM_OP_PIMM = 65;; let _ARM_OP_SETEND = 66;; let _ARM_OP_SYSREG = 67;; let _ARM_SETEND_INVALID = 0;; let _ARM_SETEND_BE = 1;; let _ARM_SETEND_LE = 2;; let _ARM_CPSMODE_INVALID = 0;; let _ARM_CPSMODE_IE = 2;; let _ARM_CPSMODE_ID = 3;; let _ARM_CPSFLAG_INVALID = 0;; let _ARM_CPSFLAG_F = 1;; let _ARM_CPSFLAG_I = 2;; let _ARM_CPSFLAG_A = 4;; let _ARM_CPSFLAG_NONE = 16;; let _ARM_VECTORDATA_INVALID = 0;; let _ARM_VECTORDATA_I8 = 1;; let _ARM_VECTORDATA_I16 = 2;; let _ARM_VECTORDATA_I32 = 3;; let _ARM_VECTORDATA_I64 = 4;; let _ARM_VECTORDATA_S8 = 5;; let _ARM_VECTORDATA_S16 = 6;; let _ARM_VECTORDATA_S32 = 7;; let _ARM_VECTORDATA_S64 = 8;; let _ARM_VECTORDATA_U8 = 9;; let _ARM_VECTORDATA_U16 = 10;; let _ARM_VECTORDATA_U32 = 11;; let _ARM_VECTORDATA_U64 = 12;; let _ARM_VECTORDATA_P8 = 13;; let _ARM_VECTORDATA_F16 = 14;; let _ARM_VECTORDATA_F32 = 15;; let _ARM_VECTORDATA_F64 = 16;; let _ARM_VECTORDATA_F16F64 = 17;; let _ARM_VECTORDATA_F64F16 = 18;; let _ARM_VECTORDATA_F32F16 = 19;; let _ARM_VECTORDATA_F16F32 = 20;; let _ARM_VECTORDATA_F64F32 = 21;; let _ARM_VECTORDATA_F32F64 = 22;; let _ARM_VECTORDATA_S32F32 = 23;; let _ARM_VECTORDATA_U32F32 = 24;; let _ARM_VECTORDATA_F32S32 = 25;; let _ARM_VECTORDATA_F32U32 = 26;; let _ARM_VECTORDATA_F64S16 = 27;; let _ARM_VECTORDATA_F32S16 = 28;; let _ARM_VECTORDATA_F64S32 = 29;; let _ARM_VECTORDATA_S16F64 = 30;; let _ARM_VECTORDATA_S16F32 = 31;; let _ARM_VECTORDATA_S32F64 = 32;; let _ARM_VECTORDATA_U16F64 = 33;; let _ARM_VECTORDATA_U16F32 = 34;; let _ARM_VECTORDATA_U32F64 = 35;; let _ARM_VECTORDATA_F64U16 = 36;; let _ARM_VECTORDATA_F32U16 = 37;; let _ARM_VECTORDATA_F64U32 = 38;; let _ARM_VECTORDATA_F16U16 = 39;; let _ARM_VECTORDATA_U16F16 = 40;; let _ARM_VECTORDATA_F16U32 = 41;; let _ARM_VECTORDATA_U32F16 = 42;; let _ARM_REG_INVALID = 0;; let _ARM_REG_APSR = 1;; let _ARM_REG_APSR_NZCV = 2;; let _ARM_REG_CPSR = 3;; let _ARM_REG_FPEXC = 4;; let _ARM_REG_FPINST = 5;; let _ARM_REG_FPSCR = 6;; let _ARM_REG_FPSCR_NZCV = 7;; let _ARM_REG_FPSID = 8;; let _ARM_REG_ITSTATE = 9;; let _ARM_REG_LR = 10;; let _ARM_REG_PC = 11;; let _ARM_REG_SP = 12;; let _ARM_REG_SPSR = 13;; let _ARM_REG_D0 = 14;; let _ARM_REG_D1 = 15;; let _ARM_REG_D2 = 16;; let _ARM_REG_D3 = 17;; let _ARM_REG_D4 = 18;; let _ARM_REG_D5 = 19;; let _ARM_REG_D6 = 20;; let _ARM_REG_D7 = 21;; let _ARM_REG_D8 = 22;; let _ARM_REG_D9 = 23;; let _ARM_REG_D10 = 24;; let _ARM_REG_D11 = 25;; let _ARM_REG_D12 = 26;; let _ARM_REG_D13 = 27;; let _ARM_REG_D14 = 28;; let _ARM_REG_D15 = 29;; let _ARM_REG_D16 = 30;; let _ARM_REG_D17 = 31;; let _ARM_REG_D18 = 32;; let _ARM_REG_D19 = 33;; let _ARM_REG_D20 = 34;; let _ARM_REG_D21 = 35;; let _ARM_REG_D22 = 36;; let _ARM_REG_D23 = 37;; let _ARM_REG_D24 = 38;; let _ARM_REG_D25 = 39;; let _ARM_REG_D26 = 40;; let _ARM_REG_D27 = 41;; let _ARM_REG_D28 = 42;; let _ARM_REG_D29 = 43;; let _ARM_REG_D30 = 44;; let _ARM_REG_D31 = 45;; let _ARM_REG_FPINST2 = 46;; let _ARM_REG_MVFR0 = 47;; let _ARM_REG_MVFR1 = 48;; let _ARM_REG_MVFR2 = 49;; let _ARM_REG_Q0 = 50;; let _ARM_REG_Q1 = 51;; let _ARM_REG_Q2 = 52;; let _ARM_REG_Q3 = 53;; let _ARM_REG_Q4 = 54;; let _ARM_REG_Q5 = 55;; let _ARM_REG_Q6 = 56;; let _ARM_REG_Q7 = 57;; let _ARM_REG_Q8 = 58;; let _ARM_REG_Q9 = 59;; let _ARM_REG_Q10 = 60;; let _ARM_REG_Q11 = 61;; let _ARM_REG_Q12 = 62;; let _ARM_REG_Q13 = 63;; let _ARM_REG_Q14 = 64;; let _ARM_REG_Q15 = 65;; let _ARM_REG_R0 = 66;; let _ARM_REG_R1 = 67;; let _ARM_REG_R2 = 68;; let _ARM_REG_R3 = 69;; let _ARM_REG_R4 = 70;; let _ARM_REG_R5 = 71;; let _ARM_REG_R6 = 72;; let _ARM_REG_R7 = 73;; let _ARM_REG_R8 = 74;; let _ARM_REG_R9 = 75;; let _ARM_REG_R10 = 76;; let _ARM_REG_R11 = 77;; let _ARM_REG_R12 = 78;; let _ARM_REG_S0 = 79;; let _ARM_REG_S1 = 80;; let _ARM_REG_S2 = 81;; let _ARM_REG_S3 = 82;; let _ARM_REG_S4 = 83;; let _ARM_REG_S5 = 84;; let _ARM_REG_S6 = 85;; let _ARM_REG_S7 = 86;; let _ARM_REG_S8 = 87;; let _ARM_REG_S9 = 88;; let _ARM_REG_S10 = 89;; let _ARM_REG_S11 = 90;; let _ARM_REG_S12 = 91;; let _ARM_REG_S13 = 92;; let _ARM_REG_S14 = 93;; let _ARM_REG_S15 = 94;; let _ARM_REG_S16 = 95;; let _ARM_REG_S17 = 96;; let _ARM_REG_S18 = 97;; let _ARM_REG_S19 = 98;; let _ARM_REG_S20 = 99;; let _ARM_REG_S21 = 100;; let _ARM_REG_S22 = 101;; let _ARM_REG_S23 = 102;; let _ARM_REG_S24 = 103;; let _ARM_REG_S25 = 104;; let _ARM_REG_S26 = 105;; let _ARM_REG_S27 = 106;; let _ARM_REG_S28 = 107;; let _ARM_REG_S29 = 108;; let _ARM_REG_S30 = 109;; let _ARM_REG_S31 = 110;; let _ARM_REG_ENDING = 111;; let _ARM_REG_R13 = _ARM_REG_SP;; let _ARM_REG_R14 = _ARM_REG_LR;; let _ARM_REG_R15 = _ARM_REG_PC;; let _ARM_REG_SB = _ARM_REG_R9;; let _ARM_REG_SL = _ARM_REG_R10;; let _ARM_REG_FP = _ARM_REG_R11;; let _ARM_REG_IP = _ARM_REG_R12;; let _ARM_INS_INVALID = 0;; let _ARM_INS_ADC = 1;; let _ARM_INS_ADD = 2;; let _ARM_INS_ADDW = 3;; let _ARM_INS_ADR = 4;; let _ARM_INS_AESD = 5;; let _ARM_INS_AESE = 6;; let _ARM_INS_AESIMC = 7;; let _ARM_INS_AESMC = 8;; let _ARM_INS_AND = 9;; let _ARM_INS_ASR = 10;; let _ARM_INS_B = 11;; let _ARM_INS_BFC = 12;; let _ARM_INS_BFI = 13;; let _ARM_INS_BIC = 14;; let _ARM_INS_BKPT = 15;; let _ARM_INS_BL = 16;; let _ARM_INS_BLX = 17;; let _ARM_INS_BLXNS = 18;; let _ARM_INS_BX = 19;; let _ARM_INS_BXJ = 20;; let _ARM_INS_BXNS = 21;; let _ARM_INS_CBNZ = 22;; let _ARM_INS_CBZ = 23;; let _ARM_INS_CDP = 24;; let _ARM_INS_CDP2 = 25;; let _ARM_INS_CLREX = 26;; let _ARM_INS_CLZ = 27;; let _ARM_INS_CMN = 28;; let _ARM_INS_CMP = 29;; let _ARM_INS_CPS = 30;; let _ARM_INS_CRC32B = 31;; let _ARM_INS_CRC32CB = 32;; let _ARM_INS_CRC32CH = 33;; let _ARM_INS_CRC32CW = 34;; let _ARM_INS_CRC32H = 35;; let _ARM_INS_CRC32W = 36;; let _ARM_INS_CSDB = 37;; let _ARM_INS_DBG = 38;; let _ARM_INS_DCPS1 = 39;; let _ARM_INS_DCPS2 = 40;; let _ARM_INS_DCPS3 = 41;; let _ARM_INS_DFB = 42;; let _ARM_INS_DMB = 43;; let _ARM_INS_DSB = 44;; let _ARM_INS_EOR = 45;; let _ARM_INS_ERET = 46;; let _ARM_INS_ESB = 47;; let _ARM_INS_FADDD = 48;; let _ARM_INS_FADDS = 49;; let _ARM_INS_FCMPZD = 50;; let _ARM_INS_FCMPZS = 51;; let _ARM_INS_FCONSTD = 52;; let _ARM_INS_FCONSTS = 53;; let _ARM_INS_FLDMDBX = 54;; let _ARM_INS_FLDMIAX = 55;; let _ARM_INS_FMDHR = 56;; let _ARM_INS_FMDLR = 57;; let _ARM_INS_FMSTAT = 58;; let _ARM_INS_FSTMDBX = 59;; let _ARM_INS_FSTMIAX = 60;; let _ARM_INS_FSUBD = 61;; let _ARM_INS_FSUBS = 62;; let _ARM_INS_HINT = 63;; let _ARM_INS_HLT = 64;; let _ARM_INS_HVC = 65;; let _ARM_INS_ISB = 66;; let _ARM_INS_IT = 67;; let _ARM_INS_LDA = 68;; let _ARM_INS_LDAB = 69;; let _ARM_INS_LDAEX = 70;; let _ARM_INS_LDAEXB = 71;; let _ARM_INS_LDAEXD = 72;; let _ARM_INS_LDAEXH = 73;; let _ARM_INS_LDAH = 74;; let _ARM_INS_LDC = 75;; let _ARM_INS_LDC2 = 76;; let _ARM_INS_LDC2L = 77;; let _ARM_INS_LDCL = 78;; let _ARM_INS_LDM = 79;; let _ARM_INS_LDMDA = 80;; let _ARM_INS_LDMDB = 81;; let _ARM_INS_LDMIB = 82;; let _ARM_INS_LDR = 83;; let _ARM_INS_LDRB = 84;; let _ARM_INS_LDRBT = 85;; let _ARM_INS_LDRD = 86;; let _ARM_INS_LDREX = 87;; let _ARM_INS_LDREXB = 88;; let _ARM_INS_LDREXD = 89;; let _ARM_INS_LDREXH = 90;; let _ARM_INS_LDRH = 91;; let _ARM_INS_LDRHT = 92;; let _ARM_INS_LDRSB = 93;; let _ARM_INS_LDRSBT = 94;; let _ARM_INS_LDRSH = 95;; let _ARM_INS_LDRSHT = 96;; let _ARM_INS_LDRT = 97;; let _ARM_INS_LSL = 98;; let _ARM_INS_LSR = 99;; let _ARM_INS_MCR = 100;; let _ARM_INS_MCR2 = 101;; let _ARM_INS_MCRR = 102;; let _ARM_INS_MCRR2 = 103;; let _ARM_INS_MLA = 104;; let _ARM_INS_MLS = 105;; let _ARM_INS_MOV = 106;; let _ARM_INS_MOVS = 107;; let _ARM_INS_MOVT = 108;; let _ARM_INS_MOVW = 109;; let _ARM_INS_MRC = 110;; let _ARM_INS_MRC2 = 111;; let _ARM_INS_MRRC = 112;; let _ARM_INS_MRRC2 = 113;; let _ARM_INS_MRS = 114;; let _ARM_INS_MSR = 115;; let _ARM_INS_MUL = 116;; let _ARM_INS_MVN = 117;; let _ARM_INS_NEG = 118;; let _ARM_INS_NOP = 119;; let _ARM_INS_ORN = 120;; let _ARM_INS_ORR = 121;; let _ARM_INS_PKHBT = 122;; let _ARM_INS_PKHTB = 123;; let _ARM_INS_PLD = 124;; let _ARM_INS_PLDW = 125;; let _ARM_INS_PLI = 126;; let _ARM_INS_POP = 127;; let _ARM_INS_PUSH = 128;; let _ARM_INS_QADD = 129;; let _ARM_INS_QADD16 = 130;; let _ARM_INS_QADD8 = 131;; let _ARM_INS_QASX = 132;; let _ARM_INS_QDADD = 133;; let _ARM_INS_QDSUB = 134;; let _ARM_INS_QSAX = 135;; let _ARM_INS_QSUB = 136;; let _ARM_INS_QSUB16 = 137;; let _ARM_INS_QSUB8 = 138;; let _ARM_INS_RBIT = 139;; let _ARM_INS_REV = 140;; let _ARM_INS_REV16 = 141;; let _ARM_INS_REVSH = 142;; let _ARM_INS_RFEDA = 143;; let _ARM_INS_RFEDB = 144;; let _ARM_INS_RFEIA = 145;; let _ARM_INS_RFEIB = 146;; let _ARM_INS_ROR = 147;; let _ARM_INS_RRX = 148;; let _ARM_INS_RSB = 149;; let _ARM_INS_RSC = 150;; let _ARM_INS_SADD16 = 151;; let _ARM_INS_SADD8 = 152;; let _ARM_INS_SASX = 153;; let _ARM_INS_SBC = 154;; let _ARM_INS_SBFX = 155;; let _ARM_INS_SDIV = 156;; let _ARM_INS_SEL = 157;; let _ARM_INS_SETEND = 158;; let _ARM_INS_SETPAN = 159;; let _ARM_INS_SEV = 160;; let _ARM_INS_SEVL = 161;; let _ARM_INS_SG = 162;; let _ARM_INS_SHA1C = 163;; let _ARM_INS_SHA1H = 164;; let _ARM_INS_SHA1M = 165;; let _ARM_INS_SHA1P = 166;; let _ARM_INS_SHA1SU0 = 167;; let _ARM_INS_SHA1SU1 = 168;; let _ARM_INS_SHA256H = 169;; let _ARM_INS_SHA256H2 = 170;; let _ARM_INS_SHA256SU0 = 171;; let _ARM_INS_SHA256SU1 = 172;; let _ARM_INS_SHADD16 = 173;; let _ARM_INS_SHADD8 = 174;; let _ARM_INS_SHASX = 175;; let _ARM_INS_SHSAX = 176;; let _ARM_INS_SHSUB16 = 177;; let _ARM_INS_SHSUB8 = 178;; let _ARM_INS_SMC = 179;; let _ARM_INS_SMLABB = 180;; let _ARM_INS_SMLABT = 181;; let _ARM_INS_SMLAD = 182;; let _ARM_INS_SMLADX = 183;; let _ARM_INS_SMLAL = 184;; let _ARM_INS_SMLALBB = 185;; let _ARM_INS_SMLALBT = 186;; let _ARM_INS_SMLALD = 187;; let _ARM_INS_SMLALDX = 188;; let _ARM_INS_SMLALTB = 189;; let _ARM_INS_SMLALTT = 190;; let _ARM_INS_SMLATB = 191;; let _ARM_INS_SMLATT = 192;; let _ARM_INS_SMLAWB = 193;; let _ARM_INS_SMLAWT = 194;; let _ARM_INS_SMLSD = 195;; let _ARM_INS_SMLSDX = 196;; let _ARM_INS_SMLSLD = 197;; let _ARM_INS_SMLSLDX = 198;; let _ARM_INS_SMMLA = 199;; let _ARM_INS_SMMLAR = 200;; let _ARM_INS_SMMLS = 201;; let _ARM_INS_SMMLSR = 202;; let _ARM_INS_SMMUL = 203;; let _ARM_INS_SMMULR = 204;; let _ARM_INS_SMUAD = 205;; let _ARM_INS_SMUADX = 206;; let _ARM_INS_SMULBB = 207;; let _ARM_INS_SMULBT = 208;; let _ARM_INS_SMULL = 209;; let _ARM_INS_SMULTB = 210;; let _ARM_INS_SMULTT = 211;; let _ARM_INS_SMULWB = 212;; let _ARM_INS_SMULWT = 213;; let _ARM_INS_SMUSD = 214;; let _ARM_INS_SMUSDX = 215;; let _ARM_INS_SRSDA = 216;; let _ARM_INS_SRSDB = 217;; let _ARM_INS_SRSIA = 218;; let _ARM_INS_SRSIB = 219;; let _ARM_INS_SSAT = 220;; let _ARM_INS_SSAT16 = 221;; let _ARM_INS_SSAX = 222;; let _ARM_INS_SSUB16 = 223;; let _ARM_INS_SSUB8 = 224;; let _ARM_INS_STC = 225;; let _ARM_INS_STC2 = 226;; let _ARM_INS_STC2L = 227;; let _ARM_INS_STCL = 228;; let _ARM_INS_STL = 229;; let _ARM_INS_STLB = 230;; let _ARM_INS_STLEX = 231;; let _ARM_INS_STLEXB = 232;; let _ARM_INS_STLEXD = 233;; let _ARM_INS_STLEXH = 234;; let _ARM_INS_STLH = 235;; let _ARM_INS_STM = 236;; let _ARM_INS_STMDA = 237;; let _ARM_INS_STMDB = 238;; let _ARM_INS_STMIB = 239;; let _ARM_INS_STR = 240;; let _ARM_INS_STRB = 241;; let _ARM_INS_STRBT = 242;; let _ARM_INS_STRD = 243;; let _ARM_INS_STREX = 244;; let _ARM_INS_STREXB = 245;; let _ARM_INS_STREXD = 246;; let _ARM_INS_STREXH = 247;; let _ARM_INS_STRH = 248;; let _ARM_INS_STRHT = 249;; let _ARM_INS_STRT = 250;; let _ARM_INS_SUB = 251;; let _ARM_INS_SUBS = 252;; let _ARM_INS_SUBW = 253;; let _ARM_INS_SVC = 254;; let _ARM_INS_SWP = 255;; let _ARM_INS_SWPB = 256;; let _ARM_INS_SXTAB = 257;; let _ARM_INS_SXTAB16 = 258;; let _ARM_INS_SXTAH = 259;; let _ARM_INS_SXTB = 260;; let _ARM_INS_SXTB16 = 261;; let _ARM_INS_SXTH = 262;; let _ARM_INS_TBB = 263;; let _ARM_INS_TBH = 264;; let _ARM_INS_TEQ = 265;; let _ARM_INS_TRAP = 266;; let _ARM_INS_TSB = 267;; let _ARM_INS_TST = 268;; let _ARM_INS_TT = 269;; let _ARM_INS_TTA = 270;; let _ARM_INS_TTAT = 271;; let _ARM_INS_TTT = 272;; let _ARM_INS_UADD16 = 273;; let _ARM_INS_UADD8 = 274;; let _ARM_INS_UASX = 275;; let _ARM_INS_UBFX = 276;; let _ARM_INS_UDF = 277;; let _ARM_INS_UDIV = 278;; let _ARM_INS_UHADD16 = 279;; let _ARM_INS_UHADD8 = 280;; let _ARM_INS_UHASX = 281;; let _ARM_INS_UHSAX = 282;; let _ARM_INS_UHSUB16 = 283;; let _ARM_INS_UHSUB8 = 284;; let _ARM_INS_UMAAL = 285;; let _ARM_INS_UMLAL = 286;; let _ARM_INS_UMULL = 287;; let _ARM_INS_UQADD16 = 288;; let _ARM_INS_UQADD8 = 289;; let _ARM_INS_UQASX = 290;; let _ARM_INS_UQSAX = 291;; let _ARM_INS_UQSUB16 = 292;; let _ARM_INS_UQSUB8 = 293;; let _ARM_INS_USAD8 = 294;; let _ARM_INS_USADA8 = 295;; let _ARM_INS_USAT = 296;; let _ARM_INS_USAT16 = 297;; let _ARM_INS_USAX = 298;; let _ARM_INS_USUB16 = 299;; let _ARM_INS_USUB8 = 300;; let _ARM_INS_UXTAB = 301;; let _ARM_INS_UXTAB16 = 302;; let _ARM_INS_UXTAH = 303;; let _ARM_INS_UXTB = 304;; let _ARM_INS_UXTB16 = 305;; let _ARM_INS_UXTH = 306;; let _ARM_INS_VABA = 307;; let _ARM_INS_VABAL = 308;; let _ARM_INS_VABD = 309;; let _ARM_INS_VABDL = 310;; let _ARM_INS_VABS = 311;; let _ARM_INS_VACGE = 312;; let _ARM_INS_VACGT = 313;; let _ARM_INS_VACLE = 314;; let _ARM_INS_VACLT = 315;; let _ARM_INS_VADD = 316;; let _ARM_INS_VADDHN = 317;; let _ARM_INS_VADDL = 318;; let _ARM_INS_VADDW = 319;; let _ARM_INS_VAND = 320;; let _ARM_INS_VBIC = 321;; let _ARM_INS_VBIF = 322;; let _ARM_INS_VBIT = 323;; let _ARM_INS_VBSL = 324;; let _ARM_INS_VCADD = 325;; let _ARM_INS_VCEQ = 326;; let _ARM_INS_VCGE = 327;; let _ARM_INS_VCGT = 328;; let _ARM_INS_VCLE = 329;; let _ARM_INS_VCLS = 330;; let _ARM_INS_VCLT = 331;; let _ARM_INS_VCLZ = 332;; let _ARM_INS_VCMLA = 333;; let _ARM_INS_VCMP = 334;; let _ARM_INS_VCMPE = 335;; let _ARM_INS_VCNT = 336;; let _ARM_INS_VCVT = 337;; let _ARM_INS_VCVTA = 338;; let _ARM_INS_VCVTB = 339;; let _ARM_INS_VCVTM = 340;; let _ARM_INS_VCVTN = 341;; let _ARM_INS_VCVTP = 342;; let _ARM_INS_VCVTR = 343;; let _ARM_INS_VCVTT = 344;; let _ARM_INS_VDIV = 345;; let _ARM_INS_VDUP = 346;; let _ARM_INS_VEOR = 347;; let _ARM_INS_VEXT = 348;; let _ARM_INS_VFMA = 349;; let _ARM_INS_VFMS = 350;; let _ARM_INS_VFNMA = 351;; let _ARM_INS_VFNMS = 352;; let _ARM_INS_VHADD = 353;; let _ARM_INS_VHSUB = 354;; let _ARM_INS_VINS = 355;; let _ARM_INS_VJCVT = 356;; let _ARM_INS_VLD1 = 357;; let _ARM_INS_VLD2 = 358;; let _ARM_INS_VLD3 = 359;; let _ARM_INS_VLD4 = 360;; let _ARM_INS_VLDMDB = 361;; let _ARM_INS_VLDMIA = 362;; let _ARM_INS_VLDR = 363;; let _ARM_INS_VLLDM = 364;; let _ARM_INS_VLSTM = 365;; let _ARM_INS_VMAX = 366;; let _ARM_INS_VMAXNM = 367;; let _ARM_INS_VMIN = 368;; let _ARM_INS_VMINNM = 369;; let _ARM_INS_VMLA = 370;; let _ARM_INS_VMLAL = 371;; let _ARM_INS_VMLS = 372;; let _ARM_INS_VMLSL = 373;; let _ARM_INS_VMOV = 374;; let _ARM_INS_VMOVL = 375;; let _ARM_INS_VMOVN = 376;; let _ARM_INS_VMOVX = 377;; let _ARM_INS_VMRS = 378;; let _ARM_INS_VMSR = 379;; let _ARM_INS_VMUL = 380;; let _ARM_INS_VMULL = 381;; let _ARM_INS_VMVN = 382;; let _ARM_INS_VNEG = 383;; let _ARM_INS_VNMLA = 384;; let _ARM_INS_VNMLS = 385;; let _ARM_INS_VNMUL = 386;; let _ARM_INS_VORN = 387;; let _ARM_INS_VORR = 388;; let _ARM_INS_VPADAL = 389;; let _ARM_INS_VPADD = 390;; let _ARM_INS_VPADDL = 391;; let _ARM_INS_VPMAX = 392;; let _ARM_INS_VPMIN = 393;; let _ARM_INS_VPOP = 394;; let _ARM_INS_VPUSH = 395;; let _ARM_INS_VQABS = 396;; let _ARM_INS_VQADD = 397;; let _ARM_INS_VQDMLAL = 398;; let _ARM_INS_VQDMLSL = 399;; let _ARM_INS_VQDMULH = 400;; let _ARM_INS_VQDMULL = 401;; let _ARM_INS_VQMOVN = 402;; let _ARM_INS_VQMOVUN = 403;; let _ARM_INS_VQNEG = 404;; let _ARM_INS_VQRDMLAH = 405;; let _ARM_INS_VQRDMLSH = 406;; let _ARM_INS_VQRDMULH = 407;; let _ARM_INS_VQRSHL = 408;; let _ARM_INS_VQRSHRN = 409;; let _ARM_INS_VQRSHRUN = 410;; let _ARM_INS_VQSHL = 411;; let _ARM_INS_VQSHLU = 412;; let _ARM_INS_VQSHRN = 413;; let _ARM_INS_VQSHRUN = 414;; let _ARM_INS_VQSUB = 415;; let _ARM_INS_VRADDHN = 416;; let _ARM_INS_VRECPE = 417;; let _ARM_INS_VRECPS = 418;; let _ARM_INS_VREV16 = 419;; let _ARM_INS_VREV32 = 420;; let _ARM_INS_VREV64 = 421;; let _ARM_INS_VRHADD = 422;; let _ARM_INS_VRINTA = 423;; let _ARM_INS_VRINTM = 424;; let _ARM_INS_VRINTN = 425;; let _ARM_INS_VRINTP = 426;; let _ARM_INS_VRINTR = 427;; let _ARM_INS_VRINTX = 428;; let _ARM_INS_VRINTZ = 429;; let _ARM_INS_VRSHL = 430;; let _ARM_INS_VRSHR = 431;; let _ARM_INS_VRSHRN = 432;; let _ARM_INS_VRSQRTE = 433;; let _ARM_INS_VRSQRTS = 434;; let _ARM_INS_VRSRA = 435;; let _ARM_INS_VRSUBHN = 436;; let _ARM_INS_VSDOT = 437;; let _ARM_INS_VSELEQ = 438;; let _ARM_INS_VSELGE = 439;; let _ARM_INS_VSELGT = 440;; let _ARM_INS_VSELVS = 441;; let _ARM_INS_VSHL = 442;; let _ARM_INS_VSHLL = 443;; let _ARM_INS_VSHR = 444;; let _ARM_INS_VSHRN = 445;; let _ARM_INS_VSLI = 446;; let _ARM_INS_VSQRT = 447;; let _ARM_INS_VSRA = 448;; let _ARM_INS_VSRI = 449;; let _ARM_INS_VST1 = 450;; let _ARM_INS_VST2 = 451;; let _ARM_INS_VST3 = 452;; let _ARM_INS_VST4 = 453;; let _ARM_INS_VSTMDB = 454;; let _ARM_INS_VSTMIA = 455;; let _ARM_INS_VSTR = 456;; let _ARM_INS_VSUB = 457;; let _ARM_INS_VSUBHN = 458;; let _ARM_INS_VSUBL = 459;; let _ARM_INS_VSUBW = 460;; let _ARM_INS_VSWP = 461;; let _ARM_INS_VTBL = 462;; let _ARM_INS_VTBX = 463;; let _ARM_INS_VTRN = 464;; let _ARM_INS_VTST = 465;; let _ARM_INS_VUDOT = 466;; let _ARM_INS_VUZP = 467;; let _ARM_INS_VZIP = 468;; let _ARM_INS_WFE = 469;; let _ARM_INS_WFI = 470;; let _ARM_INS_YIELD = 471;; let _ARM_INS_ENDING = 472;; let _ARM_GRP_INVALID = 0;; let _ARM_GRP_JUMP = 1;; let _ARM_GRP_CALL = 2;; let _ARM_GRP_INT = 4;; let _ARM_GRP_PRIVILEGE = 6;; let _ARM_GRP_BRANCH_RELATIVE = 7;; let _ARM_GRP_CRYPTO = 128;; let _ARM_GRP_DATABARRIER = 129;; let _ARM_GRP_DIVIDE = 130;; let _ARM_GRP_FPARMV8 = 131;; let _ARM_GRP_MULTPRO = 132;; let _ARM_GRP_NEON = 133;; let _ARM_GRP_T2EXTRACTPACK = 134;; let _ARM_GRP_THUMB2DSP = 135;; let _ARM_GRP_TRUSTZONE = 136;; let _ARM_GRP_V4T = 137;; let _ARM_GRP_V5T = 138;; let _ARM_GRP_V5TE = 139;; let _ARM_GRP_V6 = 140;; let _ARM_GRP_V6T2 = 141;; let _ARM_GRP_V7 = 142;; let _ARM_GRP_V8 = 143;; let _ARM_GRP_VFP2 = 144;; let _ARM_GRP_VFP3 = 145;; let _ARM_GRP_VFP4 = 146;; let _ARM_GRP_ARM = 147;; let _ARM_GRP_MCLASS = 148;; let _ARM_GRP_NOTMCLASS = 149;; let _ARM_GRP_THUMB = 150;; let _ARM_GRP_THUMB1ONLY = 151;; let _ARM_GRP_THUMB2 = 152;; let _ARM_GRP_PREV8 = 153;; let _ARM_GRP_FPVMLX = 154;; let _ARM_GRP_MULOPS = 155;; let _ARM_GRP_CRC = 156;; let _ARM_GRP_DPVFP = 157;; let _ARM_GRP_V6M = 158;; let _ARM_GRP_VIRTUALIZATION = 159;; let _ARM_GRP_ENDING = 160;; capstone-sys-0.15.0/capstone/bindings/ocaml/capstone.ml000064400000000000000000000163300072674642500212440ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Arm open Arm64 open Mips open Ppc open X86 open Sparc open Systemz open Xcore open M680x open Printf (* debug *) (* Hardware architectures *) type arch = | CS_ARCH_ARM | CS_ARCH_ARM64 | CS_ARCH_MIPS | CS_ARCH_X86 | CS_ARCH_PPC | CS_ARCH_SPARC | CS_ARCH_SYSZ | CS_ARCH_XCORE | CS_ARCH_M68K | CS_ARCH_TMS320C64X | CS_ARCH_M680X (* Hardware modes *) type mode = | CS_MODE_LITTLE_ENDIAN (* little-endian mode (default mode) *) | CS_MODE_ARM (* ARM mode *) | CS_MODE_16 (* 16-bit mode (for X86) *) | CS_MODE_32 (* 32-bit mode (for X86) *) | CS_MODE_64 (* 64-bit mode (for X86, PPC) *) | CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *) | CS_MODE_MCLASS (* ARM's MClass mode *) | CS_MODE_V8 (* ARMv8 A32 encodings for ARM *) | CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *) | CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *) | CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *) | CS_MODE_MIPS2 (* Mips2 mode (MIPS architecture) *) | CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *) | CS_MODE_BIG_ENDIAN (* big-endian mode *) | CS_MODE_MIPS32 (* Mips32 mode (for Mips) *) | CS_MODE_MIPS64 (* Mips64 mode (for Mips) *) | CS_MODE_QPX (* Quad Processing eXtensions mode (PowerPC) *) | CS_MODE_M680X_6301 (* M680X Hitachi 6301,6303 mode *) | CS_MODE_M680X_6309 (* M680X Hitachi 6309 mode *) | CS_MODE_M680X_6800 (* M680X Motorola 6800,6802 mode *) | CS_MODE_M680X_6801 (* M680X Motorola 6801,6803 mode *) | CS_MODE_M680X_6805 (* M680X Motorola 6805 mode *) | CS_MODE_M680X_6808 (* M680X Motorola 6808 mode *) | CS_MODE_M680X_6809 (* M680X Motorola 6809 mode *) | CS_MODE_M680X_6811 (* M680X Motorola/Freescale 68HC11 mode *) | CS_MODE_M680X_CPU12 (* M680X Motorola/Freescale/NXP CPU12 mode *) | CS_MODE_M680X_HCS08 (* M680X Freescale HCS08 mode *) (* Runtime option for the disassembled engine *) type opt_type = | CS_OPT_SYNTAX (* Asssembly output syntax *) | CS_OPT_DETAIL (* Break down instruction structure into details *) | CS_OPT_MODE (* Change engine's mode at run-time *) | CS_OPT_MEM (* User-defined dynamic memory related functions *) | CS_OPT_SKIPDATA (* Skip data when disassembling. Then engine is in SKIPDATA mode. *) | CS_OPT_SKIPDATA_SETUP (* Setup user-defined function for SKIPDATA option *) (* Common instruction operand access types - to be consistent across all architectures. *) (* It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE *) let _CS_AC_INVALID = 0;; (* Uninitialized/invalid access type. *) let _CS_AC_READ = 1 lsl 0;; (* Operand read from memory or register. *) let _CS_AC_WRITE = 1 lsl 1;; (* Operand write to memory or register. *) (* Runtime option value (associated with option type above) *) let _CS_OPT_OFF = 0L;; (* Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. *) let _CS_OPT_ON = 3L;; (* Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). *) let _CS_OPT_SYNTAX_DEFAULT = 0L;; (* Default asm syntax (CS_OPT_SYNTAX). *) let _CS_OPT_SYNTAX_INTEL = 1L;; (* X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). *) let _CS_OPT_SYNTAX_ATT = 2L;; (* X86 ATT asm syntax (CS_OPT_SYNTAX). *) let _CS_OPT_SYNTAX_NOREGNAME = 3L;; (* Prints register name with only number (CS_OPT_SYNTAX) *) (* Common instruction operand types - to be consistent across all architectures. *) let _CS_OP_INVALID = 0;; (* uninitialized/invalid operand. *) let _CS_OP_REG = 1;; (* Register operand. *) let _CS_OP_IMM = 2;; (* Immediate operand. *) let _CS_OP_MEM = 3;; (* Memory operand. *) let _CS_OP_FP = 4;; (* Floating-Point operand. *) (* Common instruction groups - to be consistent across all architectures. *) let _CS_GRP_INVALID = 0;; (* uninitialized/invalid group. *) let _CS_GRP_JUMP = 1;; (* all jump instructions (conditional+direct+indirect jumps) *) let _CS_GRP_CALL = 2;; (* all call instructions *) let _CS_GRP_RET = 3;; (* all return instructions *) let _CS_GRP_INT = 4;; (* all interrupt instructions (int+syscall) *) let _CS_GRP_IRET = 5;; (* all interrupt return instructions *) let _CS_GRP_PRIVILEGE = 6;; (* all privileged instructions *) type cs_arch = | CS_INFO_ARM of cs_arm | CS_INFO_ARM64 of cs_arm64 | CS_INFO_MIPS of cs_mips | CS_INFO_X86 of cs_x86 | CS_INFO_PPC of cs_ppc | CS_INFO_SPARC of cs_sparc | CS_INFO_SYSZ of cs_sysz | CS_INFO_XCORE of cs_xcore | CS_INFO_M680X of cs_m680x type csh = { h: Int64.t; a: arch; } type cs_insn0 = { id: int; address: int; size: int; bytes: int array; mnemonic: string; op_str: string; regs_read: int array; regs_write: int array; groups: int array; arch: cs_arch; } external _cs_open: arch -> mode list -> Int64.t option = "ocaml_open" external cs_disasm_quick: arch -> mode list -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm" external _cs_disasm_internal: arch -> Int64.t -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm_internal" external _cs_reg_name: Int64.t -> int -> string = "ocaml_register_name" external _cs_insn_name: Int64.t -> int -> string = "ocaml_instruction_name" external _cs_group_name: Int64.t -> int -> string = "ocaml_group_name" external cs_version: unit -> int = "ocaml_version" external _cs_option: Int64.t -> opt_type -> Int64.t -> int = "ocaml_option" external _cs_close: Int64.t -> int = "ocaml_close" let cs_open _arch _mode: csh = ( let _handle = _cs_open _arch _mode in ( match _handle with | None -> { h = 0L; a = _arch } | Some v -> { h = v; a = _arch } ); );; let cs_close handle = ( _cs_close handle.h; ) let cs_option handle opt value = ( _cs_option handle.h opt value; );; let cs_disasm handle code address count = ( _cs_disasm_internal handle.a handle.h code address count; );; let cs_reg_name handle id = ( _cs_reg_name handle.h id; );; let cs_insn_name handle id = ( _cs_insn_name handle.h id; );; let cs_group_name handle id = ( _cs_group_name handle.h id; );; class cs_insn c a = let csh = c in let (id, address, size, bytes, mnemonic, op_str, regs_read, regs_write, groups, arch) = (a.id, a.address, a.size, a.bytes, a.mnemonic, a.op_str, a.regs_read, a.regs_write, a.groups, a.arch) in object method id = id; method address = address; method size = size; method bytes = bytes; method mnemonic = mnemonic; method op_str = op_str; method regs_read = regs_read; method regs_write = regs_write; method groups = groups; method arch = arch; method reg_name id = _cs_reg_name csh.h id; method insn_name id = _cs_insn_name csh.h id; method group_name id = _cs_group_name csh.h id; end;; let cs_insn_group handle insn group_id = List.exists (fun g -> g == group_id) (Array.to_list insn.groups);; let cs_reg_read handle insn reg_id = List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_read);; let cs_reg_write handle insn reg_id = List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_write);; class cs a m = let mode = m and arch = a in let handle = cs_open arch mode in object method disasm code offset count = let insns = (_cs_disasm_internal arch handle.h code offset count) in List.map (fun x -> new cs_insn handle x) insns; end;; capstone-sys-0.15.0/capstone/bindings/ocaml/evm_const.ml000064400000000000000000000100270072674642500214220ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.ml] *) let _EVM_INS_STOP = 0;; let _EVM_INS_ADD = 1;; let _EVM_INS_MUL = 2;; let _EVM_INS_SUB = 3;; let _EVM_INS_DIV = 4;; let _EVM_INS_SDIV = 5;; let _EVM_INS_MOD = 6;; let _EVM_INS_SMOD = 7;; let _EVM_INS_ADDMOD = 8;; let _EVM_INS_MULMOD = 9;; let _EVM_INS_EXP = 10;; let _EVM_INS_SIGNEXTEND = 11;; let _EVM_INS_LT = 16;; let _EVM_INS_GT = 17;; let _EVM_INS_SLT = 18;; let _EVM_INS_SGT = 19;; let _EVM_INS_EQ = 20;; let _EVM_INS_ISZERO = 21;; let _EVM_INS_AND = 22;; let _EVM_INS_OR = 23;; let _EVM_INS_XOR = 24;; let _EVM_INS_NOT = 25;; let _EVM_INS_BYTE = 26;; let _EVM_INS_SHA3 = 32;; let _EVM_INS_ADDRESS = 48;; let _EVM_INS_BALANCE = 49;; let _EVM_INS_ORIGIN = 50;; let _EVM_INS_CALLER = 51;; let _EVM_INS_CALLVALUE = 52;; let _EVM_INS_CALLDATALOAD = 53;; let _EVM_INS_CALLDATASIZE = 54;; let _EVM_INS_CALLDATACOPY = 55;; let _EVM_INS_CODESIZE = 56;; let _EVM_INS_CODECOPY = 57;; let _EVM_INS_GASPRICE = 58;; let _EVM_INS_EXTCODESIZE = 59;; let _EVM_INS_EXTCODECOPY = 60;; let _EVM_INS_RETURNDATASIZE = 61;; let _EVM_INS_RETURNDATACOPY = 62;; let _EVM_INS_BLOCKHASH = 64;; let _EVM_INS_COINBASE = 65;; let _EVM_INS_TIMESTAMP = 66;; let _EVM_INS_NUMBER = 67;; let _EVM_INS_DIFFICULTY = 68;; let _EVM_INS_GASLIMIT = 69;; let _EVM_INS_POP = 80;; let _EVM_INS_MLOAD = 81;; let _EVM_INS_MSTORE = 82;; let _EVM_INS_MSTORE8 = 83;; let _EVM_INS_SLOAD = 84;; let _EVM_INS_SSTORE = 85;; let _EVM_INS_JUMP = 86;; let _EVM_INS_JUMPI = 87;; let _EVM_INS_PC = 88;; let _EVM_INS_MSIZE = 89;; let _EVM_INS_GAS = 90;; let _EVM_INS_JUMPDEST = 91;; let _EVM_INS_PUSH1 = 96;; let _EVM_INS_PUSH2 = 97;; let _EVM_INS_PUSH3 = 98;; let _EVM_INS_PUSH4 = 99;; let _EVM_INS_PUSH5 = 100;; let _EVM_INS_PUSH6 = 101;; let _EVM_INS_PUSH7 = 102;; let _EVM_INS_PUSH8 = 103;; let _EVM_INS_PUSH9 = 104;; let _EVM_INS_PUSH10 = 105;; let _EVM_INS_PUSH11 = 106;; let _EVM_INS_PUSH12 = 107;; let _EVM_INS_PUSH13 = 108;; let _EVM_INS_PUSH14 = 109;; let _EVM_INS_PUSH15 = 110;; let _EVM_INS_PUSH16 = 111;; let _EVM_INS_PUSH17 = 112;; let _EVM_INS_PUSH18 = 113;; let _EVM_INS_PUSH19 = 114;; let _EVM_INS_PUSH20 = 115;; let _EVM_INS_PUSH21 = 116;; let _EVM_INS_PUSH22 = 117;; let _EVM_INS_PUSH23 = 118;; let _EVM_INS_PUSH24 = 119;; let _EVM_INS_PUSH25 = 120;; let _EVM_INS_PUSH26 = 121;; let _EVM_INS_PUSH27 = 122;; let _EVM_INS_PUSH28 = 123;; let _EVM_INS_PUSH29 = 124;; let _EVM_INS_PUSH30 = 125;; let _EVM_INS_PUSH31 = 126;; let _EVM_INS_PUSH32 = 127;; let _EVM_INS_DUP1 = 128;; let _EVM_INS_DUP2 = 129;; let _EVM_INS_DUP3 = 130;; let _EVM_INS_DUP4 = 131;; let _EVM_INS_DUP5 = 132;; let _EVM_INS_DUP6 = 133;; let _EVM_INS_DUP7 = 134;; let _EVM_INS_DUP8 = 135;; let _EVM_INS_DUP9 = 136;; let _EVM_INS_DUP10 = 137;; let _EVM_INS_DUP11 = 138;; let _EVM_INS_DUP12 = 139;; let _EVM_INS_DUP13 = 140;; let _EVM_INS_DUP14 = 141;; let _EVM_INS_DUP15 = 142;; let _EVM_INS_DUP16 = 143;; let _EVM_INS_SWAP1 = 144;; let _EVM_INS_SWAP2 = 145;; let _EVM_INS_SWAP3 = 146;; let _EVM_INS_SWAP4 = 147;; let _EVM_INS_SWAP5 = 148;; let _EVM_INS_SWAP6 = 149;; let _EVM_INS_SWAP7 = 150;; let _EVM_INS_SWAP8 = 151;; let _EVM_INS_SWAP9 = 152;; let _EVM_INS_SWAP10 = 153;; let _EVM_INS_SWAP11 = 154;; let _EVM_INS_SWAP12 = 155;; let _EVM_INS_SWAP13 = 156;; let _EVM_INS_SWAP14 = 157;; let _EVM_INS_SWAP15 = 158;; let _EVM_INS_SWAP16 = 159;; let _EVM_INS_LOG0 = 160;; let _EVM_INS_LOG1 = 161;; let _EVM_INS_LOG2 = 162;; let _EVM_INS_LOG3 = 163;; let _EVM_INS_LOG4 = 164;; let _EVM_INS_CREATE = 240;; let _EVM_INS_CALL = 241;; let _EVM_INS_CALLCODE = 242;; let _EVM_INS_RETURN = 243;; let _EVM_INS_DELEGATECALL = 244;; let _EVM_INS_CALLBLACKBOX = 245;; let _EVM_INS_STATICCALL = 250;; let _EVM_INS_REVERT = 253;; let _EVM_INS_SUICIDE = 255;; let _EVM_INS_INVALID = 512;; let _EVM_INS_ENDING = 513;; let _EVM_GRP_INVALID = 0;; let _EVM_GRP_JUMP = 1;; let _EVM_GRP_MATH = 8;; let _EVM_GRP_STACK_WRITE = 9;; let _EVM_GRP_STACK_READ = 10;; let _EVM_GRP_MEM_WRITE = 11;; let _EVM_GRP_MEM_READ = 12;; let _EVM_GRP_STORE_WRITE = 13;; let _EVM_GRP_STORE_READ = 14;; let _EVM_GRP_HALT = 15;; let _EVM_GRP_ENDING = 16;; capstone-sys-0.15.0/capstone/bindings/ocaml/m680x.ml000064400000000000000000000014760072674642500203170ustar 00000000000000(* Capstone Disassembly Engine * M680X Backend by Wolfgang Schwotzer 2017 *) open M680x_const (* architecture specific info of instruction *) type m680x_op_idx = { base_reg: int; offset_reg: int; offset: int; offset_addr: int; offset_bits: int; inc_dec: int; flags: int; } type m680x_op_rel = { addr_rel: int; offset: int; } type m680x_op_ext = { addr_ext: int; indirect: bool; } type m680x_op_value = | M680X_OP_INVALID of int | M680X_OP_IMMEDIATE of int | M680X_OP_REGISTER of int | M680X_OP_INDEXED of m680x_op_idx | M680X_OP_RELATIVE of m680x_op_rel | M680X_OP_EXTENDED of m680x_op_ext | M680X_OP_DIRECT of int | M680X_OP_CONSTANT of int type m680x_op = { value: m680x_op_value; size: int; access: int; } type cs_m680x = { flags: int; operands: m680x_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/m680x_const.ml000064400000000000000000000260130072674642500215170ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.ml] *) let _M680X_OPERAND_COUNT = 9;; let _M680X_REG_INVALID = 0;; let _M680X_REG_A = 1;; let _M680X_REG_B = 2;; let _M680X_REG_E = 3;; let _M680X_REG_F = 4;; let _M680X_REG_0 = 5;; let _M680X_REG_D = 6;; let _M680X_REG_W = 7;; let _M680X_REG_CC = 8;; let _M680X_REG_DP = 9;; let _M680X_REG_MD = 10;; let _M680X_REG_HX = 11;; let _M680X_REG_H = 12;; let _M680X_REG_X = 13;; let _M680X_REG_Y = 14;; let _M680X_REG_S = 15;; let _M680X_REG_U = 16;; let _M680X_REG_V = 17;; let _M680X_REG_Q = 18;; let _M680X_REG_PC = 19;; let _M680X_REG_TMP2 = 20;; let _M680X_REG_TMP3 = 21;; let _M680X_REG_ENDING = 22;; let _M680X_OP_INVALID = 0;; let _M680X_OP_REGISTER = 1;; let _M680X_OP_IMMEDIATE = 2;; let _M680X_OP_INDEXED = 3;; let _M680X_OP_EXTENDED = 4;; let _M680X_OP_DIRECT = 5;; let _M680X_OP_RELATIVE = 6;; let _M680X_OP_CONSTANT = 7;; let _M680X_OFFSET_NONE = 0;; let _M680X_OFFSET_BITS_5 = 5;; let _M680X_OFFSET_BITS_8 = 8;; let _M680X_OFFSET_BITS_9 = 9;; let _M680X_OFFSET_BITS_16 = 16;; let _M680X_IDX_INDIRECT = 1;; let _M680X_IDX_NO_COMMA = 2;; let _M680X_IDX_POST_INC_DEC = 4;; let _M680X_GRP_INVALID = 0;; let _M680X_GRP_JUMP = 1;; let _M680X_GRP_CALL = 2;; let _M680X_GRP_RET = 3;; let _M680X_GRP_INT = 4;; let _M680X_GRP_IRET = 5;; let _M680X_GRP_PRIV = 6;; let _M680X_GRP_BRAREL = 7;; let _M680X_GRP_ENDING = 8;; let _M680X_FIRST_OP_IN_MNEM = 1;; let _M680X_SECOND_OP_IN_MNEM = 2;; let _M680X_INS_INVLD = 0;; let _M680X_INS_ABA = 1;; let _M680X_INS_ABX = 2;; let _M680X_INS_ABY = 3;; let _M680X_INS_ADC = 4;; let _M680X_INS_ADCA = 5;; let _M680X_INS_ADCB = 6;; let _M680X_INS_ADCD = 7;; let _M680X_INS_ADCR = 8;; let _M680X_INS_ADD = 9;; let _M680X_INS_ADDA = 10;; let _M680X_INS_ADDB = 11;; let _M680X_INS_ADDD = 12;; let _M680X_INS_ADDE = 13;; let _M680X_INS_ADDF = 14;; let _M680X_INS_ADDR = 15;; let _M680X_INS_ADDW = 16;; let _M680X_INS_AIM = 17;; let _M680X_INS_AIS = 18;; let _M680X_INS_AIX = 19;; let _M680X_INS_AND = 20;; let _M680X_INS_ANDA = 21;; let _M680X_INS_ANDB = 22;; let _M680X_INS_ANDCC = 23;; let _M680X_INS_ANDD = 24;; let _M680X_INS_ANDR = 25;; let _M680X_INS_ASL = 26;; let _M680X_INS_ASLA = 27;; let _M680X_INS_ASLB = 28;; let _M680X_INS_ASLD = 29;; let _M680X_INS_ASR = 30;; let _M680X_INS_ASRA = 31;; let _M680X_INS_ASRB = 32;; let _M680X_INS_ASRD = 33;; let _M680X_INS_ASRX = 34;; let _M680X_INS_BAND = 35;; let _M680X_INS_BCC = 36;; let _M680X_INS_BCLR = 37;; let _M680X_INS_BCS = 38;; let _M680X_INS_BEOR = 39;; let _M680X_INS_BEQ = 40;; let _M680X_INS_BGE = 41;; let _M680X_INS_BGND = 42;; let _M680X_INS_BGT = 43;; let _M680X_INS_BHCC = 44;; let _M680X_INS_BHCS = 45;; let _M680X_INS_BHI = 46;; let _M680X_INS_BIAND = 47;; let _M680X_INS_BIEOR = 48;; let _M680X_INS_BIH = 49;; let _M680X_INS_BIL = 50;; let _M680X_INS_BIOR = 51;; let _M680X_INS_BIT = 52;; let _M680X_INS_BITA = 53;; let _M680X_INS_BITB = 54;; let _M680X_INS_BITD = 55;; let _M680X_INS_BITMD = 56;; let _M680X_INS_BLE = 57;; let _M680X_INS_BLS = 58;; let _M680X_INS_BLT = 59;; let _M680X_INS_BMC = 60;; let _M680X_INS_BMI = 61;; let _M680X_INS_BMS = 62;; let _M680X_INS_BNE = 63;; let _M680X_INS_BOR = 64;; let _M680X_INS_BPL = 65;; let _M680X_INS_BRCLR = 66;; let _M680X_INS_BRSET = 67;; let _M680X_INS_BRA = 68;; let _M680X_INS_BRN = 69;; let _M680X_INS_BSET = 70;; let _M680X_INS_BSR = 71;; let _M680X_INS_BVC = 72;; let _M680X_INS_BVS = 73;; let _M680X_INS_CALL = 74;; let _M680X_INS_CBA = 75;; let _M680X_INS_CBEQ = 76;; let _M680X_INS_CBEQA = 77;; let _M680X_INS_CBEQX = 78;; let _M680X_INS_CLC = 79;; let _M680X_INS_CLI = 80;; let _M680X_INS_CLR = 81;; let _M680X_INS_CLRA = 82;; let _M680X_INS_CLRB = 83;; let _M680X_INS_CLRD = 84;; let _M680X_INS_CLRE = 85;; let _M680X_INS_CLRF = 86;; let _M680X_INS_CLRH = 87;; let _M680X_INS_CLRW = 88;; let _M680X_INS_CLRX = 89;; let _M680X_INS_CLV = 90;; let _M680X_INS_CMP = 91;; let _M680X_INS_CMPA = 92;; let _M680X_INS_CMPB = 93;; let _M680X_INS_CMPD = 94;; let _M680X_INS_CMPE = 95;; let _M680X_INS_CMPF = 96;; let _M680X_INS_CMPR = 97;; let _M680X_INS_CMPS = 98;; let _M680X_INS_CMPU = 99;; let _M680X_INS_CMPW = 100;; let _M680X_INS_CMPX = 101;; let _M680X_INS_CMPY = 102;; let _M680X_INS_COM = 103;; let _M680X_INS_COMA = 104;; let _M680X_INS_COMB = 105;; let _M680X_INS_COMD = 106;; let _M680X_INS_COME = 107;; let _M680X_INS_COMF = 108;; let _M680X_INS_COMW = 109;; let _M680X_INS_COMX = 110;; let _M680X_INS_CPD = 111;; let _M680X_INS_CPHX = 112;; let _M680X_INS_CPS = 113;; let _M680X_INS_CPX = 114;; let _M680X_INS_CPY = 115;; let _M680X_INS_CWAI = 116;; let _M680X_INS_DAA = 117;; let _M680X_INS_DBEQ = 118;; let _M680X_INS_DBNE = 119;; let _M680X_INS_DBNZ = 120;; let _M680X_INS_DBNZA = 121;; let _M680X_INS_DBNZX = 122;; let _M680X_INS_DEC = 123;; let _M680X_INS_DECA = 124;; let _M680X_INS_DECB = 125;; let _M680X_INS_DECD = 126;; let _M680X_INS_DECE = 127;; let _M680X_INS_DECF = 128;; let _M680X_INS_DECW = 129;; let _M680X_INS_DECX = 130;; let _M680X_INS_DES = 131;; let _M680X_INS_DEX = 132;; let _M680X_INS_DEY = 133;; let _M680X_INS_DIV = 134;; let _M680X_INS_DIVD = 135;; let _M680X_INS_DIVQ = 136;; let _M680X_INS_EDIV = 137;; let _M680X_INS_EDIVS = 138;; let _M680X_INS_EIM = 139;; let _M680X_INS_EMACS = 140;; let _M680X_INS_EMAXD = 141;; let _M680X_INS_EMAXM = 142;; let _M680X_INS_EMIND = 143;; let _M680X_INS_EMINM = 144;; let _M680X_INS_EMUL = 145;; let _M680X_INS_EMULS = 146;; let _M680X_INS_EOR = 147;; let _M680X_INS_EORA = 148;; let _M680X_INS_EORB = 149;; let _M680X_INS_EORD = 150;; let _M680X_INS_EORR = 151;; let _M680X_INS_ETBL = 152;; let _M680X_INS_EXG = 153;; let _M680X_INS_FDIV = 154;; let _M680X_INS_IBEQ = 155;; let _M680X_INS_IBNE = 156;; let _M680X_INS_IDIV = 157;; let _M680X_INS_IDIVS = 158;; let _M680X_INS_ILLGL = 159;; let _M680X_INS_INC = 160;; let _M680X_INS_INCA = 161;; let _M680X_INS_INCB = 162;; let _M680X_INS_INCD = 163;; let _M680X_INS_INCE = 164;; let _M680X_INS_INCF = 165;; let _M680X_INS_INCW = 166;; let _M680X_INS_INCX = 167;; let _M680X_INS_INS = 168;; let _M680X_INS_INX = 169;; let _M680X_INS_INY = 170;; let _M680X_INS_JMP = 171;; let _M680X_INS_JSR = 172;; let _M680X_INS_LBCC = 173;; let _M680X_INS_LBCS = 174;; let _M680X_INS_LBEQ = 175;; let _M680X_INS_LBGE = 176;; let _M680X_INS_LBGT = 177;; let _M680X_INS_LBHI = 178;; let _M680X_INS_LBLE = 179;; let _M680X_INS_LBLS = 180;; let _M680X_INS_LBLT = 181;; let _M680X_INS_LBMI = 182;; let _M680X_INS_LBNE = 183;; let _M680X_INS_LBPL = 184;; let _M680X_INS_LBRA = 185;; let _M680X_INS_LBRN = 186;; let _M680X_INS_LBSR = 187;; let _M680X_INS_LBVC = 188;; let _M680X_INS_LBVS = 189;; let _M680X_INS_LDA = 190;; let _M680X_INS_LDAA = 191;; let _M680X_INS_LDAB = 192;; let _M680X_INS_LDB = 193;; let _M680X_INS_LDBT = 194;; let _M680X_INS_LDD = 195;; let _M680X_INS_LDE = 196;; let _M680X_INS_LDF = 197;; let _M680X_INS_LDHX = 198;; let _M680X_INS_LDMD = 199;; let _M680X_INS_LDQ = 200;; let _M680X_INS_LDS = 201;; let _M680X_INS_LDU = 202;; let _M680X_INS_LDW = 203;; let _M680X_INS_LDX = 204;; let _M680X_INS_LDY = 205;; let _M680X_INS_LEAS = 206;; let _M680X_INS_LEAU = 207;; let _M680X_INS_LEAX = 208;; let _M680X_INS_LEAY = 209;; let _M680X_INS_LSL = 210;; let _M680X_INS_LSLA = 211;; let _M680X_INS_LSLB = 212;; let _M680X_INS_LSLD = 213;; let _M680X_INS_LSLX = 214;; let _M680X_INS_LSR = 215;; let _M680X_INS_LSRA = 216;; let _M680X_INS_LSRB = 217;; let _M680X_INS_LSRD = 218;; let _M680X_INS_LSRW = 219;; let _M680X_INS_LSRX = 220;; let _M680X_INS_MAXA = 221;; let _M680X_INS_MAXM = 222;; let _M680X_INS_MEM = 223;; let _M680X_INS_MINA = 224;; let _M680X_INS_MINM = 225;; let _M680X_INS_MOV = 226;; let _M680X_INS_MOVB = 227;; let _M680X_INS_MOVW = 228;; let _M680X_INS_MUL = 229;; let _M680X_INS_MULD = 230;; let _M680X_INS_NEG = 231;; let _M680X_INS_NEGA = 232;; let _M680X_INS_NEGB = 233;; let _M680X_INS_NEGD = 234;; let _M680X_INS_NEGX = 235;; let _M680X_INS_NOP = 236;; let _M680X_INS_NSA = 237;; let _M680X_INS_OIM = 238;; let _M680X_INS_ORA = 239;; let _M680X_INS_ORAA = 240;; let _M680X_INS_ORAB = 241;; let _M680X_INS_ORB = 242;; let _M680X_INS_ORCC = 243;; let _M680X_INS_ORD = 244;; let _M680X_INS_ORR = 245;; let _M680X_INS_PSHA = 246;; let _M680X_INS_PSHB = 247;; let _M680X_INS_PSHC = 248;; let _M680X_INS_PSHD = 249;; let _M680X_INS_PSHH = 250;; let _M680X_INS_PSHS = 251;; let _M680X_INS_PSHSW = 252;; let _M680X_INS_PSHU = 253;; let _M680X_INS_PSHUW = 254;; let _M680X_INS_PSHX = 255;; let _M680X_INS_PSHY = 256;; let _M680X_INS_PULA = 257;; let _M680X_INS_PULB = 258;; let _M680X_INS_PULC = 259;; let _M680X_INS_PULD = 260;; let _M680X_INS_PULH = 261;; let _M680X_INS_PULS = 262;; let _M680X_INS_PULSW = 263;; let _M680X_INS_PULU = 264;; let _M680X_INS_PULUW = 265;; let _M680X_INS_PULX = 266;; let _M680X_INS_PULY = 267;; let _M680X_INS_REV = 268;; let _M680X_INS_REVW = 269;; let _M680X_INS_ROL = 270;; let _M680X_INS_ROLA = 271;; let _M680X_INS_ROLB = 272;; let _M680X_INS_ROLD = 273;; let _M680X_INS_ROLW = 274;; let _M680X_INS_ROLX = 275;; let _M680X_INS_ROR = 276;; let _M680X_INS_RORA = 277;; let _M680X_INS_RORB = 278;; let _M680X_INS_RORD = 279;; let _M680X_INS_RORW = 280;; let _M680X_INS_RORX = 281;; let _M680X_INS_RSP = 282;; let _M680X_INS_RTC = 283;; let _M680X_INS_RTI = 284;; let _M680X_INS_RTS = 285;; let _M680X_INS_SBA = 286;; let _M680X_INS_SBC = 287;; let _M680X_INS_SBCA = 288;; let _M680X_INS_SBCB = 289;; let _M680X_INS_SBCD = 290;; let _M680X_INS_SBCR = 291;; let _M680X_INS_SEC = 292;; let _M680X_INS_SEI = 293;; let _M680X_INS_SEV = 294;; let _M680X_INS_SEX = 295;; let _M680X_INS_SEXW = 296;; let _M680X_INS_SLP = 297;; let _M680X_INS_STA = 298;; let _M680X_INS_STAA = 299;; let _M680X_INS_STAB = 300;; let _M680X_INS_STB = 301;; let _M680X_INS_STBT = 302;; let _M680X_INS_STD = 303;; let _M680X_INS_STE = 304;; let _M680X_INS_STF = 305;; let _M680X_INS_STOP = 306;; let _M680X_INS_STHX = 307;; let _M680X_INS_STQ = 308;; let _M680X_INS_STS = 309;; let _M680X_INS_STU = 310;; let _M680X_INS_STW = 311;; let _M680X_INS_STX = 312;; let _M680X_INS_STY = 313;; let _M680X_INS_SUB = 314;; let _M680X_INS_SUBA = 315;; let _M680X_INS_SUBB = 316;; let _M680X_INS_SUBD = 317;; let _M680X_INS_SUBE = 318;; let _M680X_INS_SUBF = 319;; let _M680X_INS_SUBR = 320;; let _M680X_INS_SUBW = 321;; let _M680X_INS_SWI = 322;; let _M680X_INS_SWI2 = 323;; let _M680X_INS_SWI3 = 324;; let _M680X_INS_SYNC = 325;; let _M680X_INS_TAB = 326;; let _M680X_INS_TAP = 327;; let _M680X_INS_TAX = 328;; let _M680X_INS_TBA = 329;; let _M680X_INS_TBEQ = 330;; let _M680X_INS_TBL = 331;; let _M680X_INS_TBNE = 332;; let _M680X_INS_TEST = 333;; let _M680X_INS_TFM = 334;; let _M680X_INS_TFR = 335;; let _M680X_INS_TIM = 336;; let _M680X_INS_TPA = 337;; let _M680X_INS_TST = 338;; let _M680X_INS_TSTA = 339;; let _M680X_INS_TSTB = 340;; let _M680X_INS_TSTD = 341;; let _M680X_INS_TSTE = 342;; let _M680X_INS_TSTF = 343;; let _M680X_INS_TSTW = 344;; let _M680X_INS_TSTX = 345;; let _M680X_INS_TSX = 346;; let _M680X_INS_TSY = 347;; let _M680X_INS_TXA = 348;; let _M680X_INS_TXS = 349;; let _M680X_INS_TYS = 350;; let _M680X_INS_WAI = 351;; let _M680X_INS_WAIT = 352;; let _M680X_INS_WAV = 353;; let _M680X_INS_WAVR = 354;; let _M680X_INS_XGDX = 355;; let _M680X_INS_XGDY = 356;; let _M680X_INS_ENDING = 357;; capstone-sys-0.15.0/capstone/bindings/ocaml/m68k_const.ml000064400000000000000000000317270072674642500214320ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.ml] *) let _M68K_OPERAND_COUNT = 4;; let _M68K_REG_INVALID = 0;; let _M68K_REG_D0 = 1;; let _M68K_REG_D1 = 2;; let _M68K_REG_D2 = 3;; let _M68K_REG_D3 = 4;; let _M68K_REG_D4 = 5;; let _M68K_REG_D5 = 6;; let _M68K_REG_D6 = 7;; let _M68K_REG_D7 = 8;; let _M68K_REG_A0 = 9;; let _M68K_REG_A1 = 10;; let _M68K_REG_A2 = 11;; let _M68K_REG_A3 = 12;; let _M68K_REG_A4 = 13;; let _M68K_REG_A5 = 14;; let _M68K_REG_A6 = 15;; let _M68K_REG_A7 = 16;; let _M68K_REG_FP0 = 17;; let _M68K_REG_FP1 = 18;; let _M68K_REG_FP2 = 19;; let _M68K_REG_FP3 = 20;; let _M68K_REG_FP4 = 21;; let _M68K_REG_FP5 = 22;; let _M68K_REG_FP6 = 23;; let _M68K_REG_FP7 = 24;; let _M68K_REG_PC = 25;; let _M68K_REG_SR = 26;; let _M68K_REG_CCR = 27;; let _M68K_REG_SFC = 28;; let _M68K_REG_DFC = 29;; let _M68K_REG_USP = 30;; let _M68K_REG_VBR = 31;; let _M68K_REG_CACR = 32;; let _M68K_REG_CAAR = 33;; let _M68K_REG_MSP = 34;; let _M68K_REG_ISP = 35;; let _M68K_REG_TC = 36;; let _M68K_REG_ITT0 = 37;; let _M68K_REG_ITT1 = 38;; let _M68K_REG_DTT0 = 39;; let _M68K_REG_DTT1 = 40;; let _M68K_REG_MMUSR = 41;; let _M68K_REG_URP = 42;; let _M68K_REG_SRP = 43;; let _M68K_REG_FPCR = 44;; let _M68K_REG_FPSR = 45;; let _M68K_REG_FPIAR = 46;; let _M68K_REG_ENDING = 47;; let _M68K_AM_NONE = 0;; let _M68K_AM_REG_DIRECT_DATA = 1;; let _M68K_AM_REG_DIRECT_ADDR = 2;; let _M68K_AM_REGI_ADDR = 3;; let _M68K_AM_REGI_ADDR_POST_INC = 4;; let _M68K_AM_REGI_ADDR_PRE_DEC = 5;; let _M68K_AM_REGI_ADDR_DISP = 6;; let _M68K_AM_AREGI_INDEX_8_BIT_DISP = 7;; let _M68K_AM_AREGI_INDEX_BASE_DISP = 8;; let _M68K_AM_MEMI_POST_INDEX = 9;; let _M68K_AM_MEMI_PRE_INDEX = 10;; let _M68K_AM_PCI_DISP = 11;; let _M68K_AM_PCI_INDEX_8_BIT_DISP = 12;; let _M68K_AM_PCI_INDEX_BASE_DISP = 13;; let _M68K_AM_PC_MEMI_POST_INDEX = 14;; let _M68K_AM_PC_MEMI_PRE_INDEX = 15;; let _M68K_AM_ABSOLUTE_DATA_SHORT = 16;; let _M68K_AM_ABSOLUTE_DATA_LONG = 17;; let _M68K_AM_IMMEDIATE = 18;; let _M68K_AM_BRANCH_DISPLACEMENT = 19;; let _M68K_OP_INVALID = 0;; let _M68K_OP_REG = 1;; let _M68K_OP_IMM = 2;; let _M68K_OP_MEM = 3;; let _M68K_OP_FP_SINGLE = 4;; let _M68K_OP_FP_DOUBLE = 5;; let _M68K_OP_REG_BITS = 6;; let _M68K_OP_REG_PAIR = 7;; let _M68K_OP_BR_DISP = 8;; let _M68K_OP_BR_DISP_SIZE_INVALID = 0;; let _M68K_OP_BR_DISP_SIZE_BYTE = 1;; let _M68K_OP_BR_DISP_SIZE_WORD = 2;; let _M68K_OP_BR_DISP_SIZE_LONG = 4;; let _M68K_CPU_SIZE_NONE = 0;; let _M68K_CPU_SIZE_BYTE = 1;; let _M68K_CPU_SIZE_WORD = 2;; let _M68K_CPU_SIZE_LONG = 4;; let _M68K_FPU_SIZE_NONE = 0;; let _M68K_FPU_SIZE_SINGLE = 4;; let _M68K_FPU_SIZE_DOUBLE = 8;; let _M68K_FPU_SIZE_EXTENDED = 12;; let _M68K_SIZE_TYPE_INVALID = 0;; let _M68K_SIZE_TYPE_CPU = 1;; let _M68K_SIZE_TYPE_FPU = 2;; let _M68K_INS_INVALID = 0;; let _M68K_INS_ABCD = 1;; let _M68K_INS_ADD = 2;; let _M68K_INS_ADDA = 3;; let _M68K_INS_ADDI = 4;; let _M68K_INS_ADDQ = 5;; let _M68K_INS_ADDX = 6;; let _M68K_INS_AND = 7;; let _M68K_INS_ANDI = 8;; let _M68K_INS_ASL = 9;; let _M68K_INS_ASR = 10;; let _M68K_INS_BHS = 11;; let _M68K_INS_BLO = 12;; let _M68K_INS_BHI = 13;; let _M68K_INS_BLS = 14;; let _M68K_INS_BCC = 15;; let _M68K_INS_BCS = 16;; let _M68K_INS_BNE = 17;; let _M68K_INS_BEQ = 18;; let _M68K_INS_BVC = 19;; let _M68K_INS_BVS = 20;; let _M68K_INS_BPL = 21;; let _M68K_INS_BMI = 22;; let _M68K_INS_BGE = 23;; let _M68K_INS_BLT = 24;; let _M68K_INS_BGT = 25;; let _M68K_INS_BLE = 26;; let _M68K_INS_BRA = 27;; let _M68K_INS_BSR = 28;; let _M68K_INS_BCHG = 29;; let _M68K_INS_BCLR = 30;; let _M68K_INS_BSET = 31;; let _M68K_INS_BTST = 32;; let _M68K_INS_BFCHG = 33;; let _M68K_INS_BFCLR = 34;; let _M68K_INS_BFEXTS = 35;; let _M68K_INS_BFEXTU = 36;; let _M68K_INS_BFFFO = 37;; let _M68K_INS_BFINS = 38;; let _M68K_INS_BFSET = 39;; let _M68K_INS_BFTST = 40;; let _M68K_INS_BKPT = 41;; let _M68K_INS_CALLM = 42;; let _M68K_INS_CAS = 43;; let _M68K_INS_CAS2 = 44;; let _M68K_INS_CHK = 45;; let _M68K_INS_CHK2 = 46;; let _M68K_INS_CLR = 47;; let _M68K_INS_CMP = 48;; let _M68K_INS_CMPA = 49;; let _M68K_INS_CMPI = 50;; let _M68K_INS_CMPM = 51;; let _M68K_INS_CMP2 = 52;; let _M68K_INS_CINVL = 53;; let _M68K_INS_CINVP = 54;; let _M68K_INS_CINVA = 55;; let _M68K_INS_CPUSHL = 56;; let _M68K_INS_CPUSHP = 57;; let _M68K_INS_CPUSHA = 58;; let _M68K_INS_DBT = 59;; let _M68K_INS_DBF = 60;; let _M68K_INS_DBHI = 61;; let _M68K_INS_DBLS = 62;; let _M68K_INS_DBCC = 63;; let _M68K_INS_DBCS = 64;; let _M68K_INS_DBNE = 65;; let _M68K_INS_DBEQ = 66;; let _M68K_INS_DBVC = 67;; let _M68K_INS_DBVS = 68;; let _M68K_INS_DBPL = 69;; let _M68K_INS_DBMI = 70;; let _M68K_INS_DBGE = 71;; let _M68K_INS_DBLT = 72;; let _M68K_INS_DBGT = 73;; let _M68K_INS_DBLE = 74;; let _M68K_INS_DBRA = 75;; let _M68K_INS_DIVS = 76;; let _M68K_INS_DIVSL = 77;; let _M68K_INS_DIVU = 78;; let _M68K_INS_DIVUL = 79;; let _M68K_INS_EOR = 80;; let _M68K_INS_EORI = 81;; let _M68K_INS_EXG = 82;; let _M68K_INS_EXT = 83;; let _M68K_INS_EXTB = 84;; let _M68K_INS_FABS = 85;; let _M68K_INS_FSABS = 86;; let _M68K_INS_FDABS = 87;; let _M68K_INS_FACOS = 88;; let _M68K_INS_FADD = 89;; let _M68K_INS_FSADD = 90;; let _M68K_INS_FDADD = 91;; let _M68K_INS_FASIN = 92;; let _M68K_INS_FATAN = 93;; let _M68K_INS_FATANH = 94;; let _M68K_INS_FBF = 95;; let _M68K_INS_FBEQ = 96;; let _M68K_INS_FBOGT = 97;; let _M68K_INS_FBOGE = 98;; let _M68K_INS_FBOLT = 99;; let _M68K_INS_FBOLE = 100;; let _M68K_INS_FBOGL = 101;; let _M68K_INS_FBOR = 102;; let _M68K_INS_FBUN = 103;; let _M68K_INS_FBUEQ = 104;; let _M68K_INS_FBUGT = 105;; let _M68K_INS_FBUGE = 106;; let _M68K_INS_FBULT = 107;; let _M68K_INS_FBULE = 108;; let _M68K_INS_FBNE = 109;; let _M68K_INS_FBT = 110;; let _M68K_INS_FBSF = 111;; let _M68K_INS_FBSEQ = 112;; let _M68K_INS_FBGT = 113;; let _M68K_INS_FBGE = 114;; let _M68K_INS_FBLT = 115;; let _M68K_INS_FBLE = 116;; let _M68K_INS_FBGL = 117;; let _M68K_INS_FBGLE = 118;; let _M68K_INS_FBNGLE = 119;; let _M68K_INS_FBNGL = 120;; let _M68K_INS_FBNLE = 121;; let _M68K_INS_FBNLT = 122;; let _M68K_INS_FBNGE = 123;; let _M68K_INS_FBNGT = 124;; let _M68K_INS_FBSNE = 125;; let _M68K_INS_FBST = 126;; let _M68K_INS_FCMP = 127;; let _M68K_INS_FCOS = 128;; let _M68K_INS_FCOSH = 129;; let _M68K_INS_FDBF = 130;; let _M68K_INS_FDBEQ = 131;; let _M68K_INS_FDBOGT = 132;; let _M68K_INS_FDBOGE = 133;; let _M68K_INS_FDBOLT = 134;; let _M68K_INS_FDBOLE = 135;; let _M68K_INS_FDBOGL = 136;; let _M68K_INS_FDBOR = 137;; let _M68K_INS_FDBUN = 138;; let _M68K_INS_FDBUEQ = 139;; let _M68K_INS_FDBUGT = 140;; let _M68K_INS_FDBUGE = 141;; let _M68K_INS_FDBULT = 142;; let _M68K_INS_FDBULE = 143;; let _M68K_INS_FDBNE = 144;; let _M68K_INS_FDBT = 145;; let _M68K_INS_FDBSF = 146;; let _M68K_INS_FDBSEQ = 147;; let _M68K_INS_FDBGT = 148;; let _M68K_INS_FDBGE = 149;; let _M68K_INS_FDBLT = 150;; let _M68K_INS_FDBLE = 151;; let _M68K_INS_FDBGL = 152;; let _M68K_INS_FDBGLE = 153;; let _M68K_INS_FDBNGLE = 154;; let _M68K_INS_FDBNGL = 155;; let _M68K_INS_FDBNLE = 156;; let _M68K_INS_FDBNLT = 157;; let _M68K_INS_FDBNGE = 158;; let _M68K_INS_FDBNGT = 159;; let _M68K_INS_FDBSNE = 160;; let _M68K_INS_FDBST = 161;; let _M68K_INS_FDIV = 162;; let _M68K_INS_FSDIV = 163;; let _M68K_INS_FDDIV = 164;; let _M68K_INS_FETOX = 165;; let _M68K_INS_FETOXM1 = 166;; let _M68K_INS_FGETEXP = 167;; let _M68K_INS_FGETMAN = 168;; let _M68K_INS_FINT = 169;; let _M68K_INS_FINTRZ = 170;; let _M68K_INS_FLOG10 = 171;; let _M68K_INS_FLOG2 = 172;; let _M68K_INS_FLOGN = 173;; let _M68K_INS_FLOGNP1 = 174;; let _M68K_INS_FMOD = 175;; let _M68K_INS_FMOVE = 176;; let _M68K_INS_FSMOVE = 177;; let _M68K_INS_FDMOVE = 178;; let _M68K_INS_FMOVECR = 179;; let _M68K_INS_FMOVEM = 180;; let _M68K_INS_FMUL = 181;; let _M68K_INS_FSMUL = 182;; let _M68K_INS_FDMUL = 183;; let _M68K_INS_FNEG = 184;; let _M68K_INS_FSNEG = 185;; let _M68K_INS_FDNEG = 186;; let _M68K_INS_FNOP = 187;; let _M68K_INS_FREM = 188;; let _M68K_INS_FRESTORE = 189;; let _M68K_INS_FSAVE = 190;; let _M68K_INS_FSCALE = 191;; let _M68K_INS_FSGLDIV = 192;; let _M68K_INS_FSGLMUL = 193;; let _M68K_INS_FSIN = 194;; let _M68K_INS_FSINCOS = 195;; let _M68K_INS_FSINH = 196;; let _M68K_INS_FSQRT = 197;; let _M68K_INS_FSSQRT = 198;; let _M68K_INS_FDSQRT = 199;; let _M68K_INS_FSF = 200;; let _M68K_INS_FSBEQ = 201;; let _M68K_INS_FSOGT = 202;; let _M68K_INS_FSOGE = 203;; let _M68K_INS_FSOLT = 204;; let _M68K_INS_FSOLE = 205;; let _M68K_INS_FSOGL = 206;; let _M68K_INS_FSOR = 207;; let _M68K_INS_FSUN = 208;; let _M68K_INS_FSUEQ = 209;; let _M68K_INS_FSUGT = 210;; let _M68K_INS_FSUGE = 211;; let _M68K_INS_FSULT = 212;; let _M68K_INS_FSULE = 213;; let _M68K_INS_FSNE = 214;; let _M68K_INS_FST = 215;; let _M68K_INS_FSSF = 216;; let _M68K_INS_FSSEQ = 217;; let _M68K_INS_FSGT = 218;; let _M68K_INS_FSGE = 219;; let _M68K_INS_FSLT = 220;; let _M68K_INS_FSLE = 221;; let _M68K_INS_FSGL = 222;; let _M68K_INS_FSGLE = 223;; let _M68K_INS_FSNGLE = 224;; let _M68K_INS_FSNGL = 225;; let _M68K_INS_FSNLE = 226;; let _M68K_INS_FSNLT = 227;; let _M68K_INS_FSNGE = 228;; let _M68K_INS_FSNGT = 229;; let _M68K_INS_FSSNE = 230;; let _M68K_INS_FSST = 231;; let _M68K_INS_FSUB = 232;; let _M68K_INS_FSSUB = 233;; let _M68K_INS_FDSUB = 234;; let _M68K_INS_FTAN = 235;; let _M68K_INS_FTANH = 236;; let _M68K_INS_FTENTOX = 237;; let _M68K_INS_FTRAPF = 238;; let _M68K_INS_FTRAPEQ = 239;; let _M68K_INS_FTRAPOGT = 240;; let _M68K_INS_FTRAPOGE = 241;; let _M68K_INS_FTRAPOLT = 242;; let _M68K_INS_FTRAPOLE = 243;; let _M68K_INS_FTRAPOGL = 244;; let _M68K_INS_FTRAPOR = 245;; let _M68K_INS_FTRAPUN = 246;; let _M68K_INS_FTRAPUEQ = 247;; let _M68K_INS_FTRAPUGT = 248;; let _M68K_INS_FTRAPUGE = 249;; let _M68K_INS_FTRAPULT = 250;; let _M68K_INS_FTRAPULE = 251;; let _M68K_INS_FTRAPNE = 252;; let _M68K_INS_FTRAPT = 253;; let _M68K_INS_FTRAPSF = 254;; let _M68K_INS_FTRAPSEQ = 255;; let _M68K_INS_FTRAPGT = 256;; let _M68K_INS_FTRAPGE = 257;; let _M68K_INS_FTRAPLT = 258;; let _M68K_INS_FTRAPLE = 259;; let _M68K_INS_FTRAPGL = 260;; let _M68K_INS_FTRAPGLE = 261;; let _M68K_INS_FTRAPNGLE = 262;; let _M68K_INS_FTRAPNGL = 263;; let _M68K_INS_FTRAPNLE = 264;; let _M68K_INS_FTRAPNLT = 265;; let _M68K_INS_FTRAPNGE = 266;; let _M68K_INS_FTRAPNGT = 267;; let _M68K_INS_FTRAPSNE = 268;; let _M68K_INS_FTRAPST = 269;; let _M68K_INS_FTST = 270;; let _M68K_INS_FTWOTOX = 271;; let _M68K_INS_HALT = 272;; let _M68K_INS_ILLEGAL = 273;; let _M68K_INS_JMP = 274;; let _M68K_INS_JSR = 275;; let _M68K_INS_LEA = 276;; let _M68K_INS_LINK = 277;; let _M68K_INS_LPSTOP = 278;; let _M68K_INS_LSL = 279;; let _M68K_INS_LSR = 280;; let _M68K_INS_MOVE = 281;; let _M68K_INS_MOVEA = 282;; let _M68K_INS_MOVEC = 283;; let _M68K_INS_MOVEM = 284;; let _M68K_INS_MOVEP = 285;; let _M68K_INS_MOVEQ = 286;; let _M68K_INS_MOVES = 287;; let _M68K_INS_MOVE16 = 288;; let _M68K_INS_MULS = 289;; let _M68K_INS_MULU = 290;; let _M68K_INS_NBCD = 291;; let _M68K_INS_NEG = 292;; let _M68K_INS_NEGX = 293;; let _M68K_INS_NOP = 294;; let _M68K_INS_NOT = 295;; let _M68K_INS_OR = 296;; let _M68K_INS_ORI = 297;; let _M68K_INS_PACK = 298;; let _M68K_INS_PEA = 299;; let _M68K_INS_PFLUSH = 300;; let _M68K_INS_PFLUSHA = 301;; let _M68K_INS_PFLUSHAN = 302;; let _M68K_INS_PFLUSHN = 303;; let _M68K_INS_PLOADR = 304;; let _M68K_INS_PLOADW = 305;; let _M68K_INS_PLPAR = 306;; let _M68K_INS_PLPAW = 307;; let _M68K_INS_PMOVE = 308;; let _M68K_INS_PMOVEFD = 309;; let _M68K_INS_PTESTR = 310;; let _M68K_INS_PTESTW = 311;; let _M68K_INS_PULSE = 312;; let _M68K_INS_REMS = 313;; let _M68K_INS_REMU = 314;; let _M68K_INS_RESET = 315;; let _M68K_INS_ROL = 316;; let _M68K_INS_ROR = 317;; let _M68K_INS_ROXL = 318;; let _M68K_INS_ROXR = 319;; let _M68K_INS_RTD = 320;; let _M68K_INS_RTE = 321;; let _M68K_INS_RTM = 322;; let _M68K_INS_RTR = 323;; let _M68K_INS_RTS = 324;; let _M68K_INS_SBCD = 325;; let _M68K_INS_ST = 326;; let _M68K_INS_SF = 327;; let _M68K_INS_SHI = 328;; let _M68K_INS_SLS = 329;; let _M68K_INS_SCC = 330;; let _M68K_INS_SHS = 331;; let _M68K_INS_SCS = 332;; let _M68K_INS_SLO = 333;; let _M68K_INS_SNE = 334;; let _M68K_INS_SEQ = 335;; let _M68K_INS_SVC = 336;; let _M68K_INS_SVS = 337;; let _M68K_INS_SPL = 338;; let _M68K_INS_SMI = 339;; let _M68K_INS_SGE = 340;; let _M68K_INS_SLT = 341;; let _M68K_INS_SGT = 342;; let _M68K_INS_SLE = 343;; let _M68K_INS_STOP = 344;; let _M68K_INS_SUB = 345;; let _M68K_INS_SUBA = 346;; let _M68K_INS_SUBI = 347;; let _M68K_INS_SUBQ = 348;; let _M68K_INS_SUBX = 349;; let _M68K_INS_SWAP = 350;; let _M68K_INS_TAS = 351;; let _M68K_INS_TRAP = 352;; let _M68K_INS_TRAPV = 353;; let _M68K_INS_TRAPT = 354;; let _M68K_INS_TRAPF = 355;; let _M68K_INS_TRAPHI = 356;; let _M68K_INS_TRAPLS = 357;; let _M68K_INS_TRAPCC = 358;; let _M68K_INS_TRAPHS = 359;; let _M68K_INS_TRAPCS = 360;; let _M68K_INS_TRAPLO = 361;; let _M68K_INS_TRAPNE = 362;; let _M68K_INS_TRAPEQ = 363;; let _M68K_INS_TRAPVC = 364;; let _M68K_INS_TRAPVS = 365;; let _M68K_INS_TRAPPL = 366;; let _M68K_INS_TRAPMI = 367;; let _M68K_INS_TRAPGE = 368;; let _M68K_INS_TRAPLT = 369;; let _M68K_INS_TRAPGT = 370;; let _M68K_INS_TRAPLE = 371;; let _M68K_INS_TST = 372;; let _M68K_INS_UNLK = 373;; let _M68K_INS_UNPK = 374;; let _M68K_INS_ENDING = 375;; let _M68K_GRP_INVALID = 0;; let _M68K_GRP_JUMP = 1;; let _M68K_GRP_RET = 3;; let _M68K_GRP_IRET = 5;; let _M68K_GRP_BRANCH_RELATIVE = 7;; let _M68K_GRP_ENDING = 8;; capstone-sys-0.15.0/capstone/bindings/ocaml/mips.ml000064400000000000000000000006320072674642500203760ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Mips_const (* architecture specific info of instruction *) type mips_op_mem = { base: int; disp: int } type mips_op_value = | MIPS_OP_INVALID of int | MIPS_OP_REG of int | MIPS_OP_IMM of int | MIPS_OP_MEM of mips_op_mem type mips_op = { value: mips_op_value; } type cs_mips = { operands: mips_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/mips_const.ml000064400000000000000000000562060072674642500216140ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.ml] *) let _MIPS_OP_INVALID = 0;; let _MIPS_OP_REG = 1;; let _MIPS_OP_IMM = 2;; let _MIPS_OP_MEM = 3;; let _MIPS_REG_INVALID = 0;; let _MIPS_REG_PC = 1;; let _MIPS_REG_0 = 2;; let _MIPS_REG_1 = 3;; let _MIPS_REG_2 = 4;; let _MIPS_REG_3 = 5;; let _MIPS_REG_4 = 6;; let _MIPS_REG_5 = 7;; let _MIPS_REG_6 = 8;; let _MIPS_REG_7 = 9;; let _MIPS_REG_8 = 10;; let _MIPS_REG_9 = 11;; let _MIPS_REG_10 = 12;; let _MIPS_REG_11 = 13;; let _MIPS_REG_12 = 14;; let _MIPS_REG_13 = 15;; let _MIPS_REG_14 = 16;; let _MIPS_REG_15 = 17;; let _MIPS_REG_16 = 18;; let _MIPS_REG_17 = 19;; let _MIPS_REG_18 = 20;; let _MIPS_REG_19 = 21;; let _MIPS_REG_20 = 22;; let _MIPS_REG_21 = 23;; let _MIPS_REG_22 = 24;; let _MIPS_REG_23 = 25;; let _MIPS_REG_24 = 26;; let _MIPS_REG_25 = 27;; let _MIPS_REG_26 = 28;; let _MIPS_REG_27 = 29;; let _MIPS_REG_28 = 30;; let _MIPS_REG_29 = 31;; let _MIPS_REG_30 = 32;; let _MIPS_REG_31 = 33;; let _MIPS_REG_DSPCCOND = 34;; let _MIPS_REG_DSPCARRY = 35;; let _MIPS_REG_DSPEFI = 36;; let _MIPS_REG_DSPOUTFLAG = 37;; let _MIPS_REG_DSPOUTFLAG16_19 = 38;; let _MIPS_REG_DSPOUTFLAG20 = 39;; let _MIPS_REG_DSPOUTFLAG21 = 40;; let _MIPS_REG_DSPOUTFLAG22 = 41;; let _MIPS_REG_DSPOUTFLAG23 = 42;; let _MIPS_REG_DSPPOS = 43;; let _MIPS_REG_DSPSCOUNT = 44;; let _MIPS_REG_AC0 = 45;; let _MIPS_REG_AC1 = 46;; let _MIPS_REG_AC2 = 47;; let _MIPS_REG_AC3 = 48;; let _MIPS_REG_CC0 = 49;; let _MIPS_REG_CC1 = 50;; let _MIPS_REG_CC2 = 51;; let _MIPS_REG_CC3 = 52;; let _MIPS_REG_CC4 = 53;; let _MIPS_REG_CC5 = 54;; let _MIPS_REG_CC6 = 55;; let _MIPS_REG_CC7 = 56;; let _MIPS_REG_F0 = 57;; let _MIPS_REG_F1 = 58;; let _MIPS_REG_F2 = 59;; let _MIPS_REG_F3 = 60;; let _MIPS_REG_F4 = 61;; let _MIPS_REG_F5 = 62;; let _MIPS_REG_F6 = 63;; let _MIPS_REG_F7 = 64;; let _MIPS_REG_F8 = 65;; let _MIPS_REG_F9 = 66;; let _MIPS_REG_F10 = 67;; let _MIPS_REG_F11 = 68;; let _MIPS_REG_F12 = 69;; let _MIPS_REG_F13 = 70;; let _MIPS_REG_F14 = 71;; let _MIPS_REG_F15 = 72;; let _MIPS_REG_F16 = 73;; let _MIPS_REG_F17 = 74;; let _MIPS_REG_F18 = 75;; let _MIPS_REG_F19 = 76;; let _MIPS_REG_F20 = 77;; let _MIPS_REG_F21 = 78;; let _MIPS_REG_F22 = 79;; let _MIPS_REG_F23 = 80;; let _MIPS_REG_F24 = 81;; let _MIPS_REG_F25 = 82;; let _MIPS_REG_F26 = 83;; let _MIPS_REG_F27 = 84;; let _MIPS_REG_F28 = 85;; let _MIPS_REG_F29 = 86;; let _MIPS_REG_F30 = 87;; let _MIPS_REG_F31 = 88;; let _MIPS_REG_FCC0 = 89;; let _MIPS_REG_FCC1 = 90;; let _MIPS_REG_FCC2 = 91;; let _MIPS_REG_FCC3 = 92;; let _MIPS_REG_FCC4 = 93;; let _MIPS_REG_FCC5 = 94;; let _MIPS_REG_FCC6 = 95;; let _MIPS_REG_FCC7 = 96;; let _MIPS_REG_W0 = 97;; let _MIPS_REG_W1 = 98;; let _MIPS_REG_W2 = 99;; let _MIPS_REG_W3 = 100;; let _MIPS_REG_W4 = 101;; let _MIPS_REG_W5 = 102;; let _MIPS_REG_W6 = 103;; let _MIPS_REG_W7 = 104;; let _MIPS_REG_W8 = 105;; let _MIPS_REG_W9 = 106;; let _MIPS_REG_W10 = 107;; let _MIPS_REG_W11 = 108;; let _MIPS_REG_W12 = 109;; let _MIPS_REG_W13 = 110;; let _MIPS_REG_W14 = 111;; let _MIPS_REG_W15 = 112;; let _MIPS_REG_W16 = 113;; let _MIPS_REG_W17 = 114;; let _MIPS_REG_W18 = 115;; let _MIPS_REG_W19 = 116;; let _MIPS_REG_W20 = 117;; let _MIPS_REG_W21 = 118;; let _MIPS_REG_W22 = 119;; let _MIPS_REG_W23 = 120;; let _MIPS_REG_W24 = 121;; let _MIPS_REG_W25 = 122;; let _MIPS_REG_W26 = 123;; let _MIPS_REG_W27 = 124;; let _MIPS_REG_W28 = 125;; let _MIPS_REG_W29 = 126;; let _MIPS_REG_W30 = 127;; let _MIPS_REG_W31 = 128;; let _MIPS_REG_HI = 129;; let _MIPS_REG_LO = 130;; let _MIPS_REG_P0 = 131;; let _MIPS_REG_P1 = 132;; let _MIPS_REG_P2 = 133;; let _MIPS_REG_MPL0 = 134;; let _MIPS_REG_MPL1 = 135;; let _MIPS_REG_MPL2 = 136;; let _MIPS_REG_ENDING = 137;; let _MIPS_REG_ZERO = _MIPS_REG_0;; let _MIPS_REG_AT = _MIPS_REG_1;; let _MIPS_REG_V0 = _MIPS_REG_2;; let _MIPS_REG_V1 = _MIPS_REG_3;; let _MIPS_REG_A0 = _MIPS_REG_4;; let _MIPS_REG_A1 = _MIPS_REG_5;; let _MIPS_REG_A2 = _MIPS_REG_6;; let _MIPS_REG_A3 = _MIPS_REG_7;; let _MIPS_REG_T0 = _MIPS_REG_8;; let _MIPS_REG_T1 = _MIPS_REG_9;; let _MIPS_REG_T2 = _MIPS_REG_10;; let _MIPS_REG_T3 = _MIPS_REG_11;; let _MIPS_REG_T4 = _MIPS_REG_12;; let _MIPS_REG_T5 = _MIPS_REG_13;; let _MIPS_REG_T6 = _MIPS_REG_14;; let _MIPS_REG_T7 = _MIPS_REG_15;; let _MIPS_REG_S0 = _MIPS_REG_16;; let _MIPS_REG_S1 = _MIPS_REG_17;; let _MIPS_REG_S2 = _MIPS_REG_18;; let _MIPS_REG_S3 = _MIPS_REG_19;; let _MIPS_REG_S4 = _MIPS_REG_20;; let _MIPS_REG_S5 = _MIPS_REG_21;; let _MIPS_REG_S6 = _MIPS_REG_22;; let _MIPS_REG_S7 = _MIPS_REG_23;; let _MIPS_REG_T8 = _MIPS_REG_24;; let _MIPS_REG_T9 = _MIPS_REG_25;; let _MIPS_REG_K0 = _MIPS_REG_26;; let _MIPS_REG_K1 = _MIPS_REG_27;; let _MIPS_REG_GP = _MIPS_REG_28;; let _MIPS_REG_SP = _MIPS_REG_29;; let _MIPS_REG_FP = _MIPS_REG_30;; let _MIPS_REG_S8 = _MIPS_REG_30;; let _MIPS_REG_RA = _MIPS_REG_31;; let _MIPS_REG_HI0 = _MIPS_REG_AC0;; let _MIPS_REG_HI1 = _MIPS_REG_AC1;; let _MIPS_REG_HI2 = _MIPS_REG_AC2;; let _MIPS_REG_HI3 = _MIPS_REG_AC3;; let _MIPS_REG_LO0 = _MIPS_REG_HI0;; let _MIPS_REG_LO1 = _MIPS_REG_HI1;; let _MIPS_REG_LO2 = _MIPS_REG_HI2;; let _MIPS_REG_LO3 = _MIPS_REG_HI3;; let _MIPS_INS_INVALID = 0;; let _MIPS_INS_ABSQ_S = 1;; let _MIPS_INS_ADD = 2;; let _MIPS_INS_ADDIUPC = 3;; let _MIPS_INS_ADDIUR1SP = 4;; let _MIPS_INS_ADDIUR2 = 5;; let _MIPS_INS_ADDIUS5 = 6;; let _MIPS_INS_ADDIUSP = 7;; let _MIPS_INS_ADDQH = 8;; let _MIPS_INS_ADDQH_R = 9;; let _MIPS_INS_ADDQ = 10;; let _MIPS_INS_ADDQ_S = 11;; let _MIPS_INS_ADDSC = 12;; let _MIPS_INS_ADDS_A = 13;; let _MIPS_INS_ADDS_S = 14;; let _MIPS_INS_ADDS_U = 15;; let _MIPS_INS_ADDU16 = 16;; let _MIPS_INS_ADDUH = 17;; let _MIPS_INS_ADDUH_R = 18;; let _MIPS_INS_ADDU = 19;; let _MIPS_INS_ADDU_S = 20;; let _MIPS_INS_ADDVI = 21;; let _MIPS_INS_ADDV = 22;; let _MIPS_INS_ADDWC = 23;; let _MIPS_INS_ADD_A = 24;; let _MIPS_INS_ADDI = 25;; let _MIPS_INS_ADDIU = 26;; let _MIPS_INS_ALIGN = 27;; let _MIPS_INS_ALUIPC = 28;; let _MIPS_INS_AND = 29;; let _MIPS_INS_AND16 = 30;; let _MIPS_INS_ANDI16 = 31;; let _MIPS_INS_ANDI = 32;; let _MIPS_INS_APPEND = 33;; let _MIPS_INS_ASUB_S = 34;; let _MIPS_INS_ASUB_U = 35;; let _MIPS_INS_AUI = 36;; let _MIPS_INS_AUIPC = 37;; let _MIPS_INS_AVER_S = 38;; let _MIPS_INS_AVER_U = 39;; let _MIPS_INS_AVE_S = 40;; let _MIPS_INS_AVE_U = 41;; let _MIPS_INS_B16 = 42;; let _MIPS_INS_BADDU = 43;; let _MIPS_INS_BAL = 44;; let _MIPS_INS_BALC = 45;; let _MIPS_INS_BALIGN = 46;; let _MIPS_INS_BBIT0 = 47;; let _MIPS_INS_BBIT032 = 48;; let _MIPS_INS_BBIT1 = 49;; let _MIPS_INS_BBIT132 = 50;; let _MIPS_INS_BC = 51;; let _MIPS_INS_BC0F = 52;; let _MIPS_INS_BC0FL = 53;; let _MIPS_INS_BC0T = 54;; let _MIPS_INS_BC0TL = 55;; let _MIPS_INS_BC1EQZ = 56;; let _MIPS_INS_BC1F = 57;; let _MIPS_INS_BC1FL = 58;; let _MIPS_INS_BC1NEZ = 59;; let _MIPS_INS_BC1T = 60;; let _MIPS_INS_BC1TL = 61;; let _MIPS_INS_BC2EQZ = 62;; let _MIPS_INS_BC2F = 63;; let _MIPS_INS_BC2FL = 64;; let _MIPS_INS_BC2NEZ = 65;; let _MIPS_INS_BC2T = 66;; let _MIPS_INS_BC2TL = 67;; let _MIPS_INS_BC3F = 68;; let _MIPS_INS_BC3FL = 69;; let _MIPS_INS_BC3T = 70;; let _MIPS_INS_BC3TL = 71;; let _MIPS_INS_BCLRI = 72;; let _MIPS_INS_BCLR = 73;; let _MIPS_INS_BEQ = 74;; let _MIPS_INS_BEQC = 75;; let _MIPS_INS_BEQL = 76;; let _MIPS_INS_BEQZ16 = 77;; let _MIPS_INS_BEQZALC = 78;; let _MIPS_INS_BEQZC = 79;; let _MIPS_INS_BGEC = 80;; let _MIPS_INS_BGEUC = 81;; let _MIPS_INS_BGEZ = 82;; let _MIPS_INS_BGEZAL = 83;; let _MIPS_INS_BGEZALC = 84;; let _MIPS_INS_BGEZALL = 85;; let _MIPS_INS_BGEZALS = 86;; let _MIPS_INS_BGEZC = 87;; let _MIPS_INS_BGEZL = 88;; let _MIPS_INS_BGTZ = 89;; let _MIPS_INS_BGTZALC = 90;; let _MIPS_INS_BGTZC = 91;; let _MIPS_INS_BGTZL = 92;; let _MIPS_INS_BINSLI = 93;; let _MIPS_INS_BINSL = 94;; let _MIPS_INS_BINSRI = 95;; let _MIPS_INS_BINSR = 96;; let _MIPS_INS_BITREV = 97;; let _MIPS_INS_BITSWAP = 98;; let _MIPS_INS_BLEZ = 99;; let _MIPS_INS_BLEZALC = 100;; let _MIPS_INS_BLEZC = 101;; let _MIPS_INS_BLEZL = 102;; let _MIPS_INS_BLTC = 103;; let _MIPS_INS_BLTUC = 104;; let _MIPS_INS_BLTZ = 105;; let _MIPS_INS_BLTZAL = 106;; let _MIPS_INS_BLTZALC = 107;; let _MIPS_INS_BLTZALL = 108;; let _MIPS_INS_BLTZALS = 109;; let _MIPS_INS_BLTZC = 110;; let _MIPS_INS_BLTZL = 111;; let _MIPS_INS_BMNZI = 112;; let _MIPS_INS_BMNZ = 113;; let _MIPS_INS_BMZI = 114;; let _MIPS_INS_BMZ = 115;; let _MIPS_INS_BNE = 116;; let _MIPS_INS_BNEC = 117;; let _MIPS_INS_BNEGI = 118;; let _MIPS_INS_BNEG = 119;; let _MIPS_INS_BNEL = 120;; let _MIPS_INS_BNEZ16 = 121;; let _MIPS_INS_BNEZALC = 122;; let _MIPS_INS_BNEZC = 123;; let _MIPS_INS_BNVC = 124;; let _MIPS_INS_BNZ = 125;; let _MIPS_INS_BOVC = 126;; let _MIPS_INS_BPOSGE32 = 127;; let _MIPS_INS_BREAK = 128;; let _MIPS_INS_BREAK16 = 129;; let _MIPS_INS_BSELI = 130;; let _MIPS_INS_BSEL = 131;; let _MIPS_INS_BSETI = 132;; let _MIPS_INS_BSET = 133;; let _MIPS_INS_BZ = 134;; let _MIPS_INS_BEQZ = 135;; let _MIPS_INS_B = 136;; let _MIPS_INS_BNEZ = 137;; let _MIPS_INS_BTEQZ = 138;; let _MIPS_INS_BTNEZ = 139;; let _MIPS_INS_CACHE = 140;; let _MIPS_INS_CEIL = 141;; let _MIPS_INS_CEQI = 142;; let _MIPS_INS_CEQ = 143;; let _MIPS_INS_CFC1 = 144;; let _MIPS_INS_CFCMSA = 145;; let _MIPS_INS_CINS = 146;; let _MIPS_INS_CINS32 = 147;; let _MIPS_INS_CLASS = 148;; let _MIPS_INS_CLEI_S = 149;; let _MIPS_INS_CLEI_U = 150;; let _MIPS_INS_CLE_S = 151;; let _MIPS_INS_CLE_U = 152;; let _MIPS_INS_CLO = 153;; let _MIPS_INS_CLTI_S = 154;; let _MIPS_INS_CLTI_U = 155;; let _MIPS_INS_CLT_S = 156;; let _MIPS_INS_CLT_U = 157;; let _MIPS_INS_CLZ = 158;; let _MIPS_INS_CMPGDU = 159;; let _MIPS_INS_CMPGU = 160;; let _MIPS_INS_CMPU = 161;; let _MIPS_INS_CMP = 162;; let _MIPS_INS_COPY_S = 163;; let _MIPS_INS_COPY_U = 164;; let _MIPS_INS_CTC1 = 165;; let _MIPS_INS_CTCMSA = 166;; let _MIPS_INS_CVT = 167;; let _MIPS_INS_C = 168;; let _MIPS_INS_CMPI = 169;; let _MIPS_INS_DADD = 170;; let _MIPS_INS_DADDI = 171;; let _MIPS_INS_DADDIU = 172;; let _MIPS_INS_DADDU = 173;; let _MIPS_INS_DAHI = 174;; let _MIPS_INS_DALIGN = 175;; let _MIPS_INS_DATI = 176;; let _MIPS_INS_DAUI = 177;; let _MIPS_INS_DBITSWAP = 178;; let _MIPS_INS_DCLO = 179;; let _MIPS_INS_DCLZ = 180;; let _MIPS_INS_DDIV = 181;; let _MIPS_INS_DDIVU = 182;; let _MIPS_INS_DERET = 183;; let _MIPS_INS_DEXT = 184;; let _MIPS_INS_DEXTM = 185;; let _MIPS_INS_DEXTU = 186;; let _MIPS_INS_DI = 187;; let _MIPS_INS_DINS = 188;; let _MIPS_INS_DINSM = 189;; let _MIPS_INS_DINSU = 190;; let _MIPS_INS_DIV = 191;; let _MIPS_INS_DIVU = 192;; let _MIPS_INS_DIV_S = 193;; let _MIPS_INS_DIV_U = 194;; let _MIPS_INS_DLSA = 195;; let _MIPS_INS_DMFC0 = 196;; let _MIPS_INS_DMFC1 = 197;; let _MIPS_INS_DMFC2 = 198;; let _MIPS_INS_DMOD = 199;; let _MIPS_INS_DMODU = 200;; let _MIPS_INS_DMTC0 = 201;; let _MIPS_INS_DMTC1 = 202;; let _MIPS_INS_DMTC2 = 203;; let _MIPS_INS_DMUH = 204;; let _MIPS_INS_DMUHU = 205;; let _MIPS_INS_DMUL = 206;; let _MIPS_INS_DMULT = 207;; let _MIPS_INS_DMULTU = 208;; let _MIPS_INS_DMULU = 209;; let _MIPS_INS_DOTP_S = 210;; let _MIPS_INS_DOTP_U = 211;; let _MIPS_INS_DPADD_S = 212;; let _MIPS_INS_DPADD_U = 213;; let _MIPS_INS_DPAQX_SA = 214;; let _MIPS_INS_DPAQX_S = 215;; let _MIPS_INS_DPAQ_SA = 216;; let _MIPS_INS_DPAQ_S = 217;; let _MIPS_INS_DPAU = 218;; let _MIPS_INS_DPAX = 219;; let _MIPS_INS_DPA = 220;; let _MIPS_INS_DPOP = 221;; let _MIPS_INS_DPSQX_SA = 222;; let _MIPS_INS_DPSQX_S = 223;; let _MIPS_INS_DPSQ_SA = 224;; let _MIPS_INS_DPSQ_S = 225;; let _MIPS_INS_DPSUB_S = 226;; let _MIPS_INS_DPSUB_U = 227;; let _MIPS_INS_DPSU = 228;; let _MIPS_INS_DPSX = 229;; let _MIPS_INS_DPS = 230;; let _MIPS_INS_DROTR = 231;; let _MIPS_INS_DROTR32 = 232;; let _MIPS_INS_DROTRV = 233;; let _MIPS_INS_DSBH = 234;; let _MIPS_INS_DSHD = 235;; let _MIPS_INS_DSLL = 236;; let _MIPS_INS_DSLL32 = 237;; let _MIPS_INS_DSLLV = 238;; let _MIPS_INS_DSRA = 239;; let _MIPS_INS_DSRA32 = 240;; let _MIPS_INS_DSRAV = 241;; let _MIPS_INS_DSRL = 242;; let _MIPS_INS_DSRL32 = 243;; let _MIPS_INS_DSRLV = 244;; let _MIPS_INS_DSUB = 245;; let _MIPS_INS_DSUBU = 246;; let _MIPS_INS_EHB = 247;; let _MIPS_INS_EI = 248;; let _MIPS_INS_ERET = 249;; let _MIPS_INS_EXT = 250;; let _MIPS_INS_EXTP = 251;; let _MIPS_INS_EXTPDP = 252;; let _MIPS_INS_EXTPDPV = 253;; let _MIPS_INS_EXTPV = 254;; let _MIPS_INS_EXTRV_RS = 255;; let _MIPS_INS_EXTRV_R = 256;; let _MIPS_INS_EXTRV_S = 257;; let _MIPS_INS_EXTRV = 258;; let _MIPS_INS_EXTR_RS = 259;; let _MIPS_INS_EXTR_R = 260;; let _MIPS_INS_EXTR_S = 261;; let _MIPS_INS_EXTR = 262;; let _MIPS_INS_EXTS = 263;; let _MIPS_INS_EXTS32 = 264;; let _MIPS_INS_ABS = 265;; let _MIPS_INS_FADD = 266;; let _MIPS_INS_FCAF = 267;; let _MIPS_INS_FCEQ = 268;; let _MIPS_INS_FCLASS = 269;; let _MIPS_INS_FCLE = 270;; let _MIPS_INS_FCLT = 271;; let _MIPS_INS_FCNE = 272;; let _MIPS_INS_FCOR = 273;; let _MIPS_INS_FCUEQ = 274;; let _MIPS_INS_FCULE = 275;; let _MIPS_INS_FCULT = 276;; let _MIPS_INS_FCUNE = 277;; let _MIPS_INS_FCUN = 278;; let _MIPS_INS_FDIV = 279;; let _MIPS_INS_FEXDO = 280;; let _MIPS_INS_FEXP2 = 281;; let _MIPS_INS_FEXUPL = 282;; let _MIPS_INS_FEXUPR = 283;; let _MIPS_INS_FFINT_S = 284;; let _MIPS_INS_FFINT_U = 285;; let _MIPS_INS_FFQL = 286;; let _MIPS_INS_FFQR = 287;; let _MIPS_INS_FILL = 288;; let _MIPS_INS_FLOG2 = 289;; let _MIPS_INS_FLOOR = 290;; let _MIPS_INS_FMADD = 291;; let _MIPS_INS_FMAX_A = 292;; let _MIPS_INS_FMAX = 293;; let _MIPS_INS_FMIN_A = 294;; let _MIPS_INS_FMIN = 295;; let _MIPS_INS_MOV = 296;; let _MIPS_INS_FMSUB = 297;; let _MIPS_INS_FMUL = 298;; let _MIPS_INS_MUL = 299;; let _MIPS_INS_NEG = 300;; let _MIPS_INS_FRCP = 301;; let _MIPS_INS_FRINT = 302;; let _MIPS_INS_FRSQRT = 303;; let _MIPS_INS_FSAF = 304;; let _MIPS_INS_FSEQ = 305;; let _MIPS_INS_FSLE = 306;; let _MIPS_INS_FSLT = 307;; let _MIPS_INS_FSNE = 308;; let _MIPS_INS_FSOR = 309;; let _MIPS_INS_FSQRT = 310;; let _MIPS_INS_SQRT = 311;; let _MIPS_INS_FSUB = 312;; let _MIPS_INS_SUB = 313;; let _MIPS_INS_FSUEQ = 314;; let _MIPS_INS_FSULE = 315;; let _MIPS_INS_FSULT = 316;; let _MIPS_INS_FSUNE = 317;; let _MIPS_INS_FSUN = 318;; let _MIPS_INS_FTINT_S = 319;; let _MIPS_INS_FTINT_U = 320;; let _MIPS_INS_FTQ = 321;; let _MIPS_INS_FTRUNC_S = 322;; let _MIPS_INS_FTRUNC_U = 323;; let _MIPS_INS_HADD_S = 324;; let _MIPS_INS_HADD_U = 325;; let _MIPS_INS_HSUB_S = 326;; let _MIPS_INS_HSUB_U = 327;; let _MIPS_INS_ILVEV = 328;; let _MIPS_INS_ILVL = 329;; let _MIPS_INS_ILVOD = 330;; let _MIPS_INS_ILVR = 331;; let _MIPS_INS_INS = 332;; let _MIPS_INS_INSERT = 333;; let _MIPS_INS_INSV = 334;; let _MIPS_INS_INSVE = 335;; let _MIPS_INS_J = 336;; let _MIPS_INS_JAL = 337;; let _MIPS_INS_JALR = 338;; let _MIPS_INS_JALRS16 = 339;; let _MIPS_INS_JALRS = 340;; let _MIPS_INS_JALS = 341;; let _MIPS_INS_JALX = 342;; let _MIPS_INS_JIALC = 343;; let _MIPS_INS_JIC = 344;; let _MIPS_INS_JR = 345;; let _MIPS_INS_JR16 = 346;; let _MIPS_INS_JRADDIUSP = 347;; let _MIPS_INS_JRC = 348;; let _MIPS_INS_JALRC = 349;; let _MIPS_INS_LB = 350;; let _MIPS_INS_LBU16 = 351;; let _MIPS_INS_LBUX = 352;; let _MIPS_INS_LBU = 353;; let _MIPS_INS_LD = 354;; let _MIPS_INS_LDC1 = 355;; let _MIPS_INS_LDC2 = 356;; let _MIPS_INS_LDC3 = 357;; let _MIPS_INS_LDI = 358;; let _MIPS_INS_LDL = 359;; let _MIPS_INS_LDPC = 360;; let _MIPS_INS_LDR = 361;; let _MIPS_INS_LDXC1 = 362;; let _MIPS_INS_LH = 363;; let _MIPS_INS_LHU16 = 364;; let _MIPS_INS_LHX = 365;; let _MIPS_INS_LHU = 366;; let _MIPS_INS_LI16 = 367;; let _MIPS_INS_LL = 368;; let _MIPS_INS_LLD = 369;; let _MIPS_INS_LSA = 370;; let _MIPS_INS_LUXC1 = 371;; let _MIPS_INS_LUI = 372;; let _MIPS_INS_LW = 373;; let _MIPS_INS_LW16 = 374;; let _MIPS_INS_LWC1 = 375;; let _MIPS_INS_LWC2 = 376;; let _MIPS_INS_LWC3 = 377;; let _MIPS_INS_LWL = 378;; let _MIPS_INS_LWM16 = 379;; let _MIPS_INS_LWM32 = 380;; let _MIPS_INS_LWPC = 381;; let _MIPS_INS_LWP = 382;; let _MIPS_INS_LWR = 383;; let _MIPS_INS_LWUPC = 384;; let _MIPS_INS_LWU = 385;; let _MIPS_INS_LWX = 386;; let _MIPS_INS_LWXC1 = 387;; let _MIPS_INS_LWXS = 388;; let _MIPS_INS_LI = 389;; let _MIPS_INS_MADD = 390;; let _MIPS_INS_MADDF = 391;; let _MIPS_INS_MADDR_Q = 392;; let _MIPS_INS_MADDU = 393;; let _MIPS_INS_MADDV = 394;; let _MIPS_INS_MADD_Q = 395;; let _MIPS_INS_MAQ_SA = 396;; let _MIPS_INS_MAQ_S = 397;; let _MIPS_INS_MAXA = 398;; let _MIPS_INS_MAXI_S = 399;; let _MIPS_INS_MAXI_U = 400;; let _MIPS_INS_MAX_A = 401;; let _MIPS_INS_MAX = 402;; let _MIPS_INS_MAX_S = 403;; let _MIPS_INS_MAX_U = 404;; let _MIPS_INS_MFC0 = 405;; let _MIPS_INS_MFC1 = 406;; let _MIPS_INS_MFC2 = 407;; let _MIPS_INS_MFHC1 = 408;; let _MIPS_INS_MFHI = 409;; let _MIPS_INS_MFLO = 410;; let _MIPS_INS_MINA = 411;; let _MIPS_INS_MINI_S = 412;; let _MIPS_INS_MINI_U = 413;; let _MIPS_INS_MIN_A = 414;; let _MIPS_INS_MIN = 415;; let _MIPS_INS_MIN_S = 416;; let _MIPS_INS_MIN_U = 417;; let _MIPS_INS_MOD = 418;; let _MIPS_INS_MODSUB = 419;; let _MIPS_INS_MODU = 420;; let _MIPS_INS_MOD_S = 421;; let _MIPS_INS_MOD_U = 422;; let _MIPS_INS_MOVE = 423;; let _MIPS_INS_MOVEP = 424;; let _MIPS_INS_MOVF = 425;; let _MIPS_INS_MOVN = 426;; let _MIPS_INS_MOVT = 427;; let _MIPS_INS_MOVZ = 428;; let _MIPS_INS_MSUB = 429;; let _MIPS_INS_MSUBF = 430;; let _MIPS_INS_MSUBR_Q = 431;; let _MIPS_INS_MSUBU = 432;; let _MIPS_INS_MSUBV = 433;; let _MIPS_INS_MSUB_Q = 434;; let _MIPS_INS_MTC0 = 435;; let _MIPS_INS_MTC1 = 436;; let _MIPS_INS_MTC2 = 437;; let _MIPS_INS_MTHC1 = 438;; let _MIPS_INS_MTHI = 439;; let _MIPS_INS_MTHLIP = 440;; let _MIPS_INS_MTLO = 441;; let _MIPS_INS_MTM0 = 442;; let _MIPS_INS_MTM1 = 443;; let _MIPS_INS_MTM2 = 444;; let _MIPS_INS_MTP0 = 445;; let _MIPS_INS_MTP1 = 446;; let _MIPS_INS_MTP2 = 447;; let _MIPS_INS_MUH = 448;; let _MIPS_INS_MUHU = 449;; let _MIPS_INS_MULEQ_S = 450;; let _MIPS_INS_MULEU_S = 451;; let _MIPS_INS_MULQ_RS = 452;; let _MIPS_INS_MULQ_S = 453;; let _MIPS_INS_MULR_Q = 454;; let _MIPS_INS_MULSAQ_S = 455;; let _MIPS_INS_MULSA = 456;; let _MIPS_INS_MULT = 457;; let _MIPS_INS_MULTU = 458;; let _MIPS_INS_MULU = 459;; let _MIPS_INS_MULV = 460;; let _MIPS_INS_MUL_Q = 461;; let _MIPS_INS_MUL_S = 462;; let _MIPS_INS_NLOC = 463;; let _MIPS_INS_NLZC = 464;; let _MIPS_INS_NMADD = 465;; let _MIPS_INS_NMSUB = 466;; let _MIPS_INS_NOR = 467;; let _MIPS_INS_NORI = 468;; let _MIPS_INS_NOT16 = 469;; let _MIPS_INS_NOT = 470;; let _MIPS_INS_OR = 471;; let _MIPS_INS_OR16 = 472;; let _MIPS_INS_ORI = 473;; let _MIPS_INS_PACKRL = 474;; let _MIPS_INS_PAUSE = 475;; let _MIPS_INS_PCKEV = 476;; let _MIPS_INS_PCKOD = 477;; let _MIPS_INS_PCNT = 478;; let _MIPS_INS_PICK = 479;; let _MIPS_INS_POP = 480;; let _MIPS_INS_PRECEQU = 481;; let _MIPS_INS_PRECEQ = 482;; let _MIPS_INS_PRECEU = 483;; let _MIPS_INS_PRECRQU_S = 484;; let _MIPS_INS_PRECRQ = 485;; let _MIPS_INS_PRECRQ_RS = 486;; let _MIPS_INS_PRECR = 487;; let _MIPS_INS_PRECR_SRA = 488;; let _MIPS_INS_PRECR_SRA_R = 489;; let _MIPS_INS_PREF = 490;; let _MIPS_INS_PREPEND = 491;; let _MIPS_INS_RADDU = 492;; let _MIPS_INS_RDDSP = 493;; let _MIPS_INS_RDHWR = 494;; let _MIPS_INS_REPLV = 495;; let _MIPS_INS_REPL = 496;; let _MIPS_INS_RINT = 497;; let _MIPS_INS_ROTR = 498;; let _MIPS_INS_ROTRV = 499;; let _MIPS_INS_ROUND = 500;; let _MIPS_INS_SAT_S = 501;; let _MIPS_INS_SAT_U = 502;; let _MIPS_INS_SB = 503;; let _MIPS_INS_SB16 = 504;; let _MIPS_INS_SC = 505;; let _MIPS_INS_SCD = 506;; let _MIPS_INS_SD = 507;; let _MIPS_INS_SDBBP = 508;; let _MIPS_INS_SDBBP16 = 509;; let _MIPS_INS_SDC1 = 510;; let _MIPS_INS_SDC2 = 511;; let _MIPS_INS_SDC3 = 512;; let _MIPS_INS_SDL = 513;; let _MIPS_INS_SDR = 514;; let _MIPS_INS_SDXC1 = 515;; let _MIPS_INS_SEB = 516;; let _MIPS_INS_SEH = 517;; let _MIPS_INS_SELEQZ = 518;; let _MIPS_INS_SELNEZ = 519;; let _MIPS_INS_SEL = 520;; let _MIPS_INS_SEQ = 521;; let _MIPS_INS_SEQI = 522;; let _MIPS_INS_SH = 523;; let _MIPS_INS_SH16 = 524;; let _MIPS_INS_SHF = 525;; let _MIPS_INS_SHILO = 526;; let _MIPS_INS_SHILOV = 527;; let _MIPS_INS_SHLLV = 528;; let _MIPS_INS_SHLLV_S = 529;; let _MIPS_INS_SHLL = 530;; let _MIPS_INS_SHLL_S = 531;; let _MIPS_INS_SHRAV = 532;; let _MIPS_INS_SHRAV_R = 533;; let _MIPS_INS_SHRA = 534;; let _MIPS_INS_SHRA_R = 535;; let _MIPS_INS_SHRLV = 536;; let _MIPS_INS_SHRL = 537;; let _MIPS_INS_SLDI = 538;; let _MIPS_INS_SLD = 539;; let _MIPS_INS_SLL = 540;; let _MIPS_INS_SLL16 = 541;; let _MIPS_INS_SLLI = 542;; let _MIPS_INS_SLLV = 543;; let _MIPS_INS_SLT = 544;; let _MIPS_INS_SLTI = 545;; let _MIPS_INS_SLTIU = 546;; let _MIPS_INS_SLTU = 547;; let _MIPS_INS_SNE = 548;; let _MIPS_INS_SNEI = 549;; let _MIPS_INS_SPLATI = 550;; let _MIPS_INS_SPLAT = 551;; let _MIPS_INS_SRA = 552;; let _MIPS_INS_SRAI = 553;; let _MIPS_INS_SRARI = 554;; let _MIPS_INS_SRAR = 555;; let _MIPS_INS_SRAV = 556;; let _MIPS_INS_SRL = 557;; let _MIPS_INS_SRL16 = 558;; let _MIPS_INS_SRLI = 559;; let _MIPS_INS_SRLRI = 560;; let _MIPS_INS_SRLR = 561;; let _MIPS_INS_SRLV = 562;; let _MIPS_INS_SSNOP = 563;; let _MIPS_INS_ST = 564;; let _MIPS_INS_SUBQH = 565;; let _MIPS_INS_SUBQH_R = 566;; let _MIPS_INS_SUBQ = 567;; let _MIPS_INS_SUBQ_S = 568;; let _MIPS_INS_SUBSUS_U = 569;; let _MIPS_INS_SUBSUU_S = 570;; let _MIPS_INS_SUBS_S = 571;; let _MIPS_INS_SUBS_U = 572;; let _MIPS_INS_SUBU16 = 573;; let _MIPS_INS_SUBUH = 574;; let _MIPS_INS_SUBUH_R = 575;; let _MIPS_INS_SUBU = 576;; let _MIPS_INS_SUBU_S = 577;; let _MIPS_INS_SUBVI = 578;; let _MIPS_INS_SUBV = 579;; let _MIPS_INS_SUXC1 = 580;; let _MIPS_INS_SW = 581;; let _MIPS_INS_SW16 = 582;; let _MIPS_INS_SWC1 = 583;; let _MIPS_INS_SWC2 = 584;; let _MIPS_INS_SWC3 = 585;; let _MIPS_INS_SWL = 586;; let _MIPS_INS_SWM16 = 587;; let _MIPS_INS_SWM32 = 588;; let _MIPS_INS_SWP = 589;; let _MIPS_INS_SWR = 590;; let _MIPS_INS_SWXC1 = 591;; let _MIPS_INS_SYNC = 592;; let _MIPS_INS_SYNCI = 593;; let _MIPS_INS_SYSCALL = 594;; let _MIPS_INS_TEQ = 595;; let _MIPS_INS_TEQI = 596;; let _MIPS_INS_TGE = 597;; let _MIPS_INS_TGEI = 598;; let _MIPS_INS_TGEIU = 599;; let _MIPS_INS_TGEU = 600;; let _MIPS_INS_TLBP = 601;; let _MIPS_INS_TLBR = 602;; let _MIPS_INS_TLBWI = 603;; let _MIPS_INS_TLBWR = 604;; let _MIPS_INS_TLT = 605;; let _MIPS_INS_TLTI = 606;; let _MIPS_INS_TLTIU = 607;; let _MIPS_INS_TLTU = 608;; let _MIPS_INS_TNE = 609;; let _MIPS_INS_TNEI = 610;; let _MIPS_INS_TRUNC = 611;; let _MIPS_INS_V3MULU = 612;; let _MIPS_INS_VMM0 = 613;; let _MIPS_INS_VMULU = 614;; let _MIPS_INS_VSHF = 615;; let _MIPS_INS_WAIT = 616;; let _MIPS_INS_WRDSP = 617;; let _MIPS_INS_WSBH = 618;; let _MIPS_INS_XOR = 619;; let _MIPS_INS_XOR16 = 620;; let _MIPS_INS_XORI = 621;; (* some alias instructions *) let _MIPS_INS_NOP = 622;; let _MIPS_INS_NEGU = 623;; (* special instructions *) let _MIPS_INS_JALR_HB = 624;; let _MIPS_INS_JR_HB = 625;; let _MIPS_INS_ENDING = 626;; let _MIPS_GRP_INVALID = 0;; let _MIPS_GRP_JUMP = 1;; let _MIPS_GRP_CALL = 2;; let _MIPS_GRP_RET = 3;; let _MIPS_GRP_INT = 4;; let _MIPS_GRP_IRET = 5;; let _MIPS_GRP_PRIVILEGE = 6;; let _MIPS_GRP_BRANCH_RELATIVE = 7;; let _MIPS_GRP_BITCOUNT = 128;; let _MIPS_GRP_DSP = 129;; let _MIPS_GRP_DSPR2 = 130;; let _MIPS_GRP_FPIDX = 131;; let _MIPS_GRP_MSA = 132;; let _MIPS_GRP_MIPS32R2 = 133;; let _MIPS_GRP_MIPS64 = 134;; let _MIPS_GRP_MIPS64R2 = 135;; let _MIPS_GRP_SEINREG = 136;; let _MIPS_GRP_STDENC = 137;; let _MIPS_GRP_SWAP = 138;; let _MIPS_GRP_MICROMIPS = 139;; let _MIPS_GRP_MIPS16MODE = 140;; let _MIPS_GRP_FP64BIT = 141;; let _MIPS_GRP_NONANSFPMATH = 142;; let _MIPS_GRP_NOTFP64BIT = 143;; let _MIPS_GRP_NOTINMICROMIPS = 144;; let _MIPS_GRP_NOTNACL = 145;; let _MIPS_GRP_NOTMIPS32R6 = 146;; let _MIPS_GRP_NOTMIPS64R6 = 147;; let _MIPS_GRP_CNMIPS = 148;; let _MIPS_GRP_MIPS32 = 149;; let _MIPS_GRP_MIPS32R6 = 150;; let _MIPS_GRP_MIPS64R6 = 151;; let _MIPS_GRP_MIPS2 = 152;; let _MIPS_GRP_MIPS3 = 153;; let _MIPS_GRP_MIPS3_32 = 154;; let _MIPS_GRP_MIPS3_32R2 = 155;; let _MIPS_GRP_MIPS4_32 = 156;; let _MIPS_GRP_MIPS4_32R2 = 157;; let _MIPS_GRP_MIPS5_32R2 = 158;; let _MIPS_GRP_GP32BIT = 159;; let _MIPS_GRP_GP64BIT = 160;; let _MIPS_GRP_ENDING = 161;; capstone-sys-0.15.0/capstone/bindings/ocaml/ocaml.c000064400000000000000000001002210072674642500203260ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013> */ #include // debug #include #include #include #include #include #include "capstone/capstone.h" #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) // count the number of positive members in @list static unsigned int list_count(uint8_t *list, unsigned int max) { unsigned int i; for(i = 0; i < max; i++) if (list[i] == 0) return i; return max; } CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t code_len, uint64_t addr, size_t count) { CAMLparam0(); CAMLlocal5(list, cons, rec_insn, array, tmp); CAMLlocal4(arch_info, op_info_val, tmp2, tmp3); cs_insn *insn; size_t c; list = Val_emptylist; c = cs_disasm(handle, code, code_len, addr, count, &insn); if (c) { //printf("Found %lu insn, addr: %lx\n", c, addr); uint64_t j; for (j = c; j > 0; j--) { unsigned int lcount, i; cons = caml_alloc(2, 0); rec_insn = caml_alloc(10, 0); Store_field(rec_insn, 0, Val_int(insn[j-1].id)); Store_field(rec_insn, 1, Val_int(insn[j-1].address)); Store_field(rec_insn, 2, Val_int(insn[j-1].size)); // copy raw bytes of instruction lcount = insn[j-1].size; if (lcount) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { Store_field(array, i, Val_int(insn[j-1].bytes[i])); } } else array = Atom(0); // empty list Store_field(rec_insn, 3, array); Store_field(rec_insn, 4, caml_copy_string(insn[j-1].mnemonic)); Store_field(rec_insn, 5, caml_copy_string(insn[j-1].op_str)); // copy read registers if (insn[0].detail) { lcount = (insn[j-1]).detail->regs_read_count; if (lcount) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { Store_field(array, i, Val_int(insn[j-1].detail->regs_read[i])); } } else array = Atom(0); // empty list } else array = Atom(0); // empty list Store_field(rec_insn, 6, array); if (insn[0].detail) { lcount = (insn[j-1]).detail->regs_write_count; if (lcount) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { Store_field(array, i, Val_int(insn[j-1].detail->regs_write[i])); } } else array = Atom(0); // empty list } else array = Atom(0); // empty list Store_field(rec_insn, 7, array); if (insn[0].detail) { lcount = (insn[j-1]).detail->groups_count; if (lcount) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { Store_field(array, i, Val_int(insn[j-1].detail->groups[i])); } } else array = Atom(0); // empty list } else array = Atom(0); // empty list Store_field(rec_insn, 8, array); if (insn[j-1].detail) { switch(arch) { case CS_ARCH_ARM: arch_info = caml_alloc(1, 0); op_info_val = caml_alloc(10, 0); Store_field(op_info_val, 0, Val_bool(insn[j-1].detail->arm.usermode)); Store_field(op_info_val, 1, Val_int(insn[j-1].detail->arm.vector_size)); Store_field(op_info_val, 2, Val_int(insn[j-1].detail->arm.vector_data)); Store_field(op_info_val, 3, Val_int(insn[j-1].detail->arm.cps_mode)); Store_field(op_info_val, 4, Val_int(insn[j-1].detail->arm.cps_flag)); Store_field(op_info_val, 5, Val_int(insn[j-1].detail->arm.cc)); Store_field(op_info_val, 6, Val_bool(insn[j-1].detail->arm.update_flags)); Store_field(op_info_val, 7, Val_bool(insn[j-1].detail->arm.writeback)); Store_field(op_info_val, 8, Val_int(insn[j-1].detail->arm.mem_barrier)); lcount = insn[j-1].detail->arm.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(5, 0); switch(insn[j-1].detail->arm.operands[i].type) { case ARM_OP_REG: case ARM_OP_SYSREG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].reg)); break; case ARM_OP_CIMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm)); break; case ARM_OP_PIMM: tmp = caml_alloc(1, 3); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm)); break; case ARM_OP_IMM: tmp = caml_alloc(1, 4); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].imm)); break; case ARM_OP_FP: tmp = caml_alloc(1, 5); Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->arm.operands[i].fp)); break; case ARM_OP_MEM: tmp = caml_alloc(1, 6); tmp3 = caml_alloc(5, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm.operands[i].mem.index)); Store_field(tmp3, 2, Val_int(insn[j-1].detail->arm.operands[i].mem.scale)); Store_field(tmp3, 3, Val_int(insn[j-1].detail->arm.operands[i].mem.disp)); Store_field(tmp3, 4, Val_int(insn[j-1].detail->arm.operands[i].mem.lshift)); Store_field(tmp, 0, tmp3); break; case ARM_OP_SETEND: tmp = caml_alloc(1, 7); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm.operands[i].setend)); break; default: break; } tmp3 = caml_alloc(2, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm.operands[i].shift.type)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm.operands[i].shift.value)); Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm.operands[i].vector_index)); Store_field(tmp2, 1, tmp3); Store_field(tmp2, 2, tmp); Store_field(tmp2, 3, Val_bool(insn[j-1].detail->arm.operands[i].subtracted)); Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm.operands[i].access)); Store_field(tmp2, 5, Val_int(insn[j-1].detail->arm.operands[i].neon_lane)); Store_field(array, i, tmp2); } } else // empty list array = Atom(0); Store_field(op_info_val, 9, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_ARM64: arch_info = caml_alloc(1, 1); op_info_val = caml_alloc(4, 0); Store_field(op_info_val, 0, Val_int(insn[j-1].detail->arm64.cc)); Store_field(op_info_val, 1, Val_bool(insn[j-1].detail->arm64.update_flags)); Store_field(op_info_val, 2, Val_bool(insn[j-1].detail->arm64.writeback)); lcount = insn[j-1].detail->arm64.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(6, 0); switch(insn[j-1].detail->arm64.operands[i].type) { case ARM64_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg)); break; case ARM64_OP_CIMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].imm)); break; case ARM64_OP_IMM: tmp = caml_alloc(1, 3); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].imm)); break; case ARM64_OP_FP: tmp = caml_alloc(1, 4); Store_field(tmp, 0, caml_copy_double(insn[j-1].detail->arm64.operands[i].fp)); break; case ARM64_OP_MEM: tmp = caml_alloc(1, 5); tmp3 = caml_alloc(3, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm64.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm64.operands[i].mem.index)); Store_field(tmp3, 2, Val_int(insn[j-1].detail->arm64.operands[i].mem.disp)); Store_field(tmp, 0, tmp3); break; case ARM64_OP_REG_MRS: tmp = caml_alloc(1, 6); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg)); break; case ARM64_OP_REG_MSR: tmp = caml_alloc(1, 7); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].reg)); break; case ARM64_OP_PSTATE: tmp = caml_alloc(1, 8); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].pstate)); break; case ARM64_OP_SYS: tmp = caml_alloc(1, 9); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].sys)); break; case ARM64_OP_PREFETCH: tmp = caml_alloc(1, 10); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].prefetch)); break; case ARM64_OP_BARRIER: tmp = caml_alloc(1, 11); Store_field(tmp, 0, Val_int(insn[j-1].detail->arm64.operands[i].barrier)); break; default: break; } tmp3 = caml_alloc(2, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->arm64.operands[i].shift.type)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->arm64.operands[i].shift.value)); Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm64.operands[i].vector_index)); Store_field(tmp2, 1, Val_int(insn[j-1].detail->arm64.operands[i].vas)); Store_field(tmp2, 2, tmp3); Store_field(tmp2, 3, Val_int(insn[j-1].detail->arm64.operands[i].ext)); Store_field(tmp2, 4, tmp); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 3, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_MIPS: arch_info = caml_alloc(1, 2); op_info_val = caml_alloc(1, 0); lcount = insn[j-1].detail->mips.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(1, 0); switch(insn[j-1].detail->mips.operands[i].type) { case MIPS_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->mips.operands[i].reg)); break; case MIPS_OP_IMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->mips.operands[i].imm)); break; case MIPS_OP_MEM: tmp = caml_alloc(1, 3); tmp3 = caml_alloc(2, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->mips.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->mips.operands[i].mem.disp)); Store_field(tmp, 0, tmp3); break; default: break; } Store_field(tmp2, 0, tmp); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 0, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_X86: arch_info = caml_alloc(1, 3); op_info_val = caml_alloc(17, 0); // fill prefix lcount = list_count(insn[j-1].detail->x86.prefix, ARR_SIZE(insn[j-1].detail->x86.prefix)); if (lcount) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { Store_field(array, i, Val_int(insn[j-1].detail->x86.prefix[i])); } } else array = Atom(0); Store_field(op_info_val, 0, array); // fill opcode lcount = list_count(insn[j-1].detail->x86.opcode, ARR_SIZE(insn[j-1].detail->x86.opcode)); if (lcount) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { Store_field(array, i, Val_int(insn[j-1].detail->x86.opcode[i])); } } else array = Atom(0); Store_field(op_info_val, 1, array); Store_field(op_info_val, 2, Val_int(insn[j-1].detail->x86.rex)); Store_field(op_info_val, 3, Val_int(insn[j-1].detail->x86.addr_size)); Store_field(op_info_val, 4, Val_int(insn[j-1].detail->x86.modrm)); Store_field(op_info_val, 5, Val_int(insn[j-1].detail->x86.sib)); Store_field(op_info_val, 6, Val_int(insn[j-1].detail->x86.disp)); Store_field(op_info_val, 7, Val_int(insn[j-1].detail->x86.sib_index)); Store_field(op_info_val, 8, Val_int(insn[j-1].detail->x86.sib_scale)); Store_field(op_info_val, 9, Val_int(insn[j-1].detail->x86.sib_base)); Store_field(op_info_val, 10, Val_int(insn[j-1].detail->x86.xop_cc)); Store_field(op_info_val, 11, Val_int(insn[j-1].detail->x86.sse_cc)); Store_field(op_info_val, 12, Val_int(insn[j-1].detail->x86.avx_cc)); Store_field(op_info_val, 13, Val_int(insn[j-1].detail->x86.avx_sae)); Store_field(op_info_val, 14, Val_int(insn[j-1].detail->x86.avx_rm)); Store_field(op_info_val, 15, Val_int(insn[j-1].detail->x86.eflags)); lcount = insn[j-1].detail->x86.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { switch(insn[j-1].detail->x86.operands[i].type) { case X86_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].reg)); break; case X86_OP_IMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->x86.operands[i].imm)); break; case X86_OP_MEM: tmp = caml_alloc(1, 3); tmp2 = caml_alloc(5, 0); Store_field(tmp2, 0, Val_int(insn[j-1].detail->x86.operands[i].mem.segment)); Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].mem.base)); Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].mem.index)); Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].mem.scale)); Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].mem.disp)); Store_field(tmp, 0, tmp2); break; default: tmp = caml_alloc(1, 0); // X86_OP_INVALID break; } tmp2 = caml_alloc(5, 0); Store_field(tmp2, 0, tmp); Store_field(tmp2, 1, Val_int(insn[j-1].detail->x86.operands[i].size)); Store_field(tmp2, 2, Val_int(insn[j-1].detail->x86.operands[i].access)); Store_field(tmp2, 3, Val_int(insn[j-1].detail->x86.operands[i].avx_bcast)); Store_field(tmp2, 4, Val_int(insn[j-1].detail->x86.operands[i].avx_zero_opmask)); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 16, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_PPC: arch_info = caml_alloc(1, 4); op_info_val = caml_alloc(4, 0); Store_field(op_info_val, 0, Val_int(insn[j-1].detail->ppc.bc)); Store_field(op_info_val, 1, Val_int(insn[j-1].detail->ppc.bh)); Store_field(op_info_val, 2, Val_bool(insn[j-1].detail->ppc.update_cr0)); lcount = insn[j-1].detail->ppc.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(1, 0); switch(insn[j-1].detail->ppc.operands[i].type) { case PPC_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->ppc.operands[i].reg)); break; case PPC_OP_IMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->ppc.operands[i].imm)); break; case PPC_OP_MEM: tmp = caml_alloc(1, 3); tmp3 = caml_alloc(2, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->ppc.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->ppc.operands[i].mem.disp)); Store_field(tmp, 0, tmp3); break; case PPC_OP_CRX: tmp = caml_alloc(1, 4); tmp3 = caml_alloc(3, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->ppc.operands[i].crx.scale)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->ppc.operands[i].crx.reg)); Store_field(tmp3, 2, Val_int(insn[j-1].detail->ppc.operands[i].crx.cond)); Store_field(tmp, 0, tmp3); break; default: break; } Store_field(tmp2, 0, tmp); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 3, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_SPARC: arch_info = caml_alloc(1, 5); op_info_val = caml_alloc(3, 0); Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sparc.cc)); Store_field(op_info_val, 1, Val_int(insn[j-1].detail->sparc.hint)); lcount = insn[j-1].detail->sparc.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(1, 0); switch(insn[j-1].detail->sparc.operands[i].type) { case SPARC_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].reg)); break; case SPARC_OP_IMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->sparc.operands[i].imm)); break; case SPARC_OP_MEM: tmp = caml_alloc(1, 3); tmp3 = caml_alloc(3, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->sparc.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->sparc.operands[i].mem.index)); Store_field(tmp3, 2, Val_int(insn[j-1].detail->sparc.operands[i].mem.disp)); Store_field(tmp, 0, tmp3); break; default: break; } Store_field(tmp2, 0, tmp); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 2, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_SYSZ: arch_info = caml_alloc(1, 6); op_info_val = caml_alloc(2, 0); Store_field(op_info_val, 0, Val_int(insn[j-1].detail->sysz.cc)); lcount = insn[j-1].detail->sysz.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(1, 0); switch(insn[j-1].detail->sysz.operands[i].type) { case SYSZ_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg)); break; case SYSZ_OP_ACREG: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].reg)); break; case SYSZ_OP_IMM: tmp = caml_alloc(1, 3); Store_field(tmp, 0, Val_int(insn[j-1].detail->sysz.operands[i].imm)); break; case SYSZ_OP_MEM: tmp = caml_alloc(1, 4); tmp3 = caml_alloc(4, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->sysz.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->sysz.operands[i].mem.index)); Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.length)); Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->sysz.operands[i].mem.disp)); Store_field(tmp, 0, tmp3); break; default: break; } Store_field(tmp2, 0, tmp); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 1, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_XCORE: arch_info = caml_alloc(1, 7); op_info_val = caml_alloc(1, 0); lcount = insn[j-1].detail->xcore.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(1, 0); switch(insn[j-1].detail->xcore.operands[i].type) { case XCORE_OP_REG: tmp = caml_alloc(1, 1); Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].reg)); break; case XCORE_OP_IMM: tmp = caml_alloc(1, 2); Store_field(tmp, 0, Val_int(insn[j-1].detail->xcore.operands[i].imm)); break; case XCORE_OP_MEM: tmp = caml_alloc(1, 3); tmp3 = caml_alloc(4, 0); Store_field(tmp3, 0, Val_int(insn[j-1].detail->xcore.operands[i].mem.base)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->xcore.operands[i].mem.index)); Store_field(tmp3, 2, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.disp)); Store_field(tmp3, 3, caml_copy_int64(insn[j-1].detail->xcore.operands[i].mem.direct)); Store_field(tmp, 0, tmp3); break; default: break; } Store_field(tmp2, 0, tmp); Store_field(array, i, tmp2); } } else // empty array array = Atom(0); Store_field(op_info_val, 0, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; case CS_ARCH_M680X: arch_info = caml_alloc(1, 8); op_info_val = caml_alloc(2, 0); // struct cs_m680x Store_field(op_info_val, 0, Val_int(insn[j-1].detail->m680x.flags)); lcount = insn[j-1].detail->m680x.op_count; if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { tmp2 = caml_alloc(3, 0); // m680x_op switch(insn[j-1].detail->m680x.operands[i].type) { case M680X_OP_IMMEDIATE: tmp = caml_alloc(1, 1); // imm Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].imm)); break; case M680X_OP_REGISTER: tmp = caml_alloc(1, 2); // reg Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].reg)); break; case M680X_OP_INDEXED: tmp = caml_alloc(1, 3); tmp3 = caml_alloc(7, 0); // m680x_op_idx Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].idx.base_reg)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_reg)); Store_field(tmp3, 2, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset)); Store_field(tmp3, 3, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_addr)); Store_field(tmp3, 4, Val_int(insn[j-1].detail->m680x.operands[i].idx.offset_bits)); Store_field(tmp3, 5, Val_int(insn[j-1].detail->m680x.operands[i].idx.inc_dec)); Store_field(tmp3, 6, Val_int(insn[j-1].detail->m680x.operands[i].idx.flags)); Store_field(tmp, 0, tmp3); break; case M680X_OP_RELATIVE: tmp = caml_alloc(1, 4); tmp3 = caml_alloc(2, 0); // m680x_op_rel Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].rel.address)); Store_field(tmp3, 1, Val_int(insn[j-1].detail->m680x.operands[i].rel.offset)); Store_field(tmp, 0, tmp3); break; case M680X_OP_EXTENDED: tmp = caml_alloc(1, 5); tmp3 = caml_alloc(2, 0); // m680x_op_ext Store_field(tmp3, 0, Val_int(insn[j-1].detail->m680x.operands[i].ext.address)); Store_field(tmp3, 1, Val_bool(insn[j-1].detail->m680x.operands[i].ext.indirect)); Store_field(tmp, 0, tmp3); break; case M680X_OP_DIRECT: tmp = caml_alloc(1, 6); // direct_addr Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].direct_addr)); break; case M680X_OP_CONSTANT: tmp = caml_alloc(1, 7); // const_val Store_field(tmp, 0, Val_int(insn[j-1].detail->m680x.operands[i].const_val)); break; default: break; } Store_field(tmp2, 0, tmp); // add union Store_field(tmp2, 1, Val_int(insn[j-1].detail->m680x.operands[i].size)); Store_field(tmp2, 2, Val_int(insn[j-1].detail->m680x.operands[i].access)); Store_field(array, i, tmp2); // add operand to operand array } } else // empty list array = Atom(0); Store_field(op_info_val, 1, array); // finally, insert this into arch_info Store_field(arch_info, 0, op_info_val); Store_field(rec_insn, 9, arch_info); break; default: break; } } Store_field(cons, 0, rec_insn); // head Store_field(cons, 1, list); // tail list = cons; } cs_free(insn, count); } // do not free the handle here //cs_close(&handle); CAMLreturn(list); } CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _addr, value _count) { CAMLparam5(_arch, _mode, _code, _addr, _count); CAMLlocal1(head); csh handle; cs_arch arch; cs_mode mode = 0; const uint8_t *code; uint64_t addr; size_t count, code_len; switch (Int_val(_arch)) { case 0: arch = CS_ARCH_ARM; break; case 1: arch = CS_ARCH_ARM64; break; case 2: arch = CS_ARCH_MIPS; break; case 3: arch = CS_ARCH_X86; break; case 4: arch = CS_ARCH_PPC; break; case 5: arch = CS_ARCH_SPARC; break; case 6: arch = CS_ARCH_SYSZ; break; case 7: arch = CS_ARCH_XCORE; break; case 8: arch = CS_ARCH_M68K; break; case 9: arch = CS_ARCH_TMS320C64X; break; case 10: arch = CS_ARCH_M680X; break; default: caml_invalid_argument("Invalid arch"); return Val_emptylist; } while (_mode != Val_emptylist) { head = Field(_mode, 0); /* accessing the head */ switch (Int_val(head)) { case 0: mode |= CS_MODE_LITTLE_ENDIAN; break; case 1: mode |= CS_MODE_ARM; break; case 2: mode |= CS_MODE_16; break; case 3: mode |= CS_MODE_32; break; case 4: mode |= CS_MODE_64; break; case 5: mode |= CS_MODE_THUMB; break; case 6: mode |= CS_MODE_MCLASS; break; case 7: mode |= CS_MODE_V8; break; case 8: mode |= CS_MODE_MICRO; break; case 9: mode |= CS_MODE_MIPS3; break; case 10: mode |= CS_MODE_MIPS32R6; break; case 11: mode |= CS_MODE_MIPS2; break; case 12: mode |= CS_MODE_V9; break; case 13: mode |= CS_MODE_BIG_ENDIAN; break; case 14: mode |= CS_MODE_MIPS32; break; case 15: mode |= CS_MODE_MIPS64; break; case 16: mode |= CS_MODE_QPX; break; case 17: mode |= CS_MODE_M680X_6301; break; case 18: mode |= CS_MODE_M680X_6309; break; case 19: mode |= CS_MODE_M680X_6800; break; case 20: mode |= CS_MODE_M680X_6801; break; case 21: mode |= CS_MODE_M680X_6805; break; case 22: mode |= CS_MODE_M680X_6808; break; case 23: mode |= CS_MODE_M680X_6809; break; case 24: mode |= CS_MODE_M680X_6811; break; case 25: mode |= CS_MODE_M680X_CPU12; break; case 26: mode |= CS_MODE_M680X_HCS08; break; default: caml_invalid_argument("Invalid mode"); return Val_emptylist; } _mode = Field(_mode, 1); /* point to the tail for next loop */ } cs_err ret = cs_open(arch, mode, &handle); if (ret != CS_ERR_OK) { return Val_emptylist; } code = (uint8_t *)String_val(_code); code_len = caml_string_length(_code); addr = Int64_val(_addr); count = Int64_val(_count); CAMLreturn(_cs_disasm(arch, handle, code, code_len, addr, count)); } CAMLprim value ocaml_cs_disasm_internal(value _arch, value _handle, value _code, value _addr, value _count) { CAMLparam5(_arch, _handle, _code, _addr, _count); csh handle; cs_arch arch; const uint8_t *code; uint64_t addr, count, code_len; handle = Int64_val(_handle); arch = Int_val(_arch); code = (uint8_t *)String_val(_code); code_len = caml_string_length(_code); addr = Int64_val(_addr); count = Int64_val(_count); CAMLreturn(_cs_disasm(arch, handle, code, code_len, addr, count)); } CAMLprim value ocaml_open(value _arch, value _mode) { CAMLparam2(_arch, _mode); CAMLlocal2(list, head); csh handle; cs_arch arch; cs_mode mode = 0; list = Val_emptylist; switch (Int_val(_arch)) { case 0: arch = CS_ARCH_ARM; break; case 1: arch = CS_ARCH_ARM64; break; case 2: arch = CS_ARCH_MIPS; break; case 3: arch = CS_ARCH_X86; break; case 4: arch = CS_ARCH_PPC; break; case 5: arch = CS_ARCH_SPARC; break; case 6: arch = CS_ARCH_SYSZ; break; case 7: arch = CS_ARCH_XCORE; break; case 8: arch = CS_ARCH_M68K; break; case 9: arch = CS_ARCH_TMS320C64X; break; case 10: arch = CS_ARCH_M680X; break; default: caml_invalid_argument("Invalid arch"); return Val_emptylist; } while (_mode != Val_emptylist) { head = Field(_mode, 0); /* accessing the head */ switch (Int_val(head)) { case 0: mode |= CS_MODE_LITTLE_ENDIAN; break; case 1: mode |= CS_MODE_ARM; break; case 2: mode |= CS_MODE_16; break; case 3: mode |= CS_MODE_32; break; case 4: mode |= CS_MODE_64; break; case 5: mode |= CS_MODE_THUMB; break; case 6: mode |= CS_MODE_MCLASS; break; case 7: mode |= CS_MODE_V8; break; case 8: mode |= CS_MODE_MICRO; break; case 9: mode |= CS_MODE_MIPS3; break; case 10: mode |= CS_MODE_MIPS32R6; break; case 11: mode |= CS_MODE_MIPS2; break; case 12: mode |= CS_MODE_V9; break; case 13: mode |= CS_MODE_BIG_ENDIAN; break; case 14: mode |= CS_MODE_MIPS32; break; case 15: mode |= CS_MODE_MIPS64; break; case 16: mode |= CS_MODE_QPX; break; case 17: mode |= CS_MODE_M680X_6301; break; case 18: mode |= CS_MODE_M680X_6309; break; case 19: mode |= CS_MODE_M680X_6800; break; case 20: mode |= CS_MODE_M680X_6801; break; case 21: mode |= CS_MODE_M680X_6805; break; case 22: mode |= CS_MODE_M680X_6808; break; case 23: mode |= CS_MODE_M680X_6809; break; case 24: mode |= CS_MODE_M680X_6811; break; case 25: mode |= CS_MODE_M680X_CPU12; break; case 26: mode |= CS_MODE_M680X_HCS08; break; default: caml_invalid_argument("Invalid mode"); return Val_emptylist; } _mode = Field(_mode, 1); /* point to the tail for next loop */ } if (cs_open(arch, mode, &handle) != 0) CAMLreturn(Val_int(0)); CAMLlocal1(result); result = caml_alloc(1, 0); Store_field(result, 0, caml_copy_int64(handle)); CAMLreturn(result); } CAMLprim value ocaml_option(value _handle, value _opt, value _value) { CAMLparam3(_handle, _opt, _value); cs_opt_type opt; int err; switch (Int_val(_opt)) { case 0: opt = CS_OPT_SYNTAX; break; case 1: opt = CS_OPT_DETAIL; break; case 2: opt = CS_OPT_MODE; break; case 3: opt = CS_OPT_MEM; break; case 4: opt = CS_OPT_SKIPDATA; break; case 5: opt = CS_OPT_SKIPDATA_SETUP; break; default: caml_invalid_argument("Invalid option"); CAMLreturn(Val_int(CS_ERR_OPTION)); } err = cs_option(Int64_val(_handle), opt, Int64_val(_value)); CAMLreturn(Val_int(err)); } CAMLprim value ocaml_register_name(value _handle, value _reg) { const char *name = cs_reg_name(Int64_val(_handle), Int_val(_reg)); if (!name) { caml_invalid_argument("invalid reg_id"); name = "invalid"; } return caml_copy_string(name); } CAMLprim value ocaml_instruction_name(value _handle, value _insn) { const char *name = cs_insn_name(Int64_val(_handle), Int_val(_insn)); if (!name) { caml_invalid_argument("invalid insn_id"); name = "invalid"; } return caml_copy_string(name); } CAMLprim value ocaml_group_name(value _handle, value _insn) { const char *name = cs_group_name(Int64_val(_handle), Int_val(_insn)); if (!name) { caml_invalid_argument("invalid insn_id"); name = "invalid"; } return caml_copy_string(name); } CAMLprim value ocaml_version(void) { int version = cs_version(NULL, NULL); return Val_int(version); } CAMLprim value ocaml_close(value _handle) { CAMLparam1(_handle); csh h; h = Int64_val(_handle); CAMLreturn(Val_int(cs_close(&h))); } capstone-sys-0.15.0/capstone/bindings/ocaml/ppc.ml000064400000000000000000000007470072674642500202170ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Ppc_const type ppc_op_mem = { base: int; disp: int; } type ppc_op_crx = { scale: int; reg: int; cond: int; } type ppc_op_value = | PPC_OP_INVALID of int | PPC_OP_REG of int | PPC_OP_IMM of int | PPC_OP_MEM of ppc_op_mem | PPC_OP_CRX of ppc_op_crx type ppc_op = { value: ppc_op_value; } type cs_ppc = { bc: int; bh: int; update_cr0: bool; operands: ppc_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/ppc_const.ml000064400000000000000000001551350072674642500214270ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.ml] *) let _PPC_BC_INVALID = 0;; let _PPC_BC_LT = (0 lsl 5) lor 12;; let _PPC_BC_LE = (1 lsl 5) lor 4;; let _PPC_BC_EQ = (2 lsl 5) lor 12;; let _PPC_BC_GE = (0 lsl 5) lor 4;; let _PPC_BC_GT = (1 lsl 5) lor 12;; let _PPC_BC_NE = (2 lsl 5) lor 4;; let _PPC_BC_UN = (3 lsl 5) lor 12;; let _PPC_BC_NU = (3 lsl 5) lor 4;; let _PPC_BC_SO = (4 lsl 5) lor 12;; let _PPC_BC_NS = (4 lsl 5) lor 4;; let _PPC_BH_INVALID = 0;; let _PPC_BH_PLUS = 1;; let _PPC_BH_MINUS = 2;; let _PPC_OP_INVALID = 0;; let _PPC_OP_REG = 1;; let _PPC_OP_IMM = 2;; let _PPC_OP_MEM = 3;; let _PPC_OP_CRX = 64;; let _PPC_REG_INVALID = 0;; let _PPC_REG_CARRY = 2;; let _PPC_REG_CTR = 3;; let _PPC_REG_LR = 5;; let _PPC_REG_RM = 6;; let _PPC_REG_VRSAVE = 8;; let _PPC_REG_XER = 9;; let _PPC_REG_ZERO = 10;; let _PPC_REG_CR0 = 12;; let _PPC_REG_CR1 = 13;; let _PPC_REG_CR2 = 14;; let _PPC_REG_CR3 = 15;; let _PPC_REG_CR4 = 16;; let _PPC_REG_CR5 = 17;; let _PPC_REG_CR6 = 18;; let _PPC_REG_CR7 = 19;; let _PPC_REG_CTR8 = 20;; let _PPC_REG_F0 = 21;; let _PPC_REG_F1 = 22;; let _PPC_REG_F2 = 23;; let _PPC_REG_F3 = 24;; let _PPC_REG_F4 = 25;; let _PPC_REG_F5 = 26;; let _PPC_REG_F6 = 27;; let _PPC_REG_F7 = 28;; let _PPC_REG_F8 = 29;; let _PPC_REG_F9 = 30;; let _PPC_REG_F10 = 31;; let _PPC_REG_F11 = 32;; let _PPC_REG_F12 = 33;; let _PPC_REG_F13 = 34;; let _PPC_REG_F14 = 35;; let _PPC_REG_F15 = 36;; let _PPC_REG_F16 = 37;; let _PPC_REG_F17 = 38;; let _PPC_REG_F18 = 39;; let _PPC_REG_F19 = 40;; let _PPC_REG_F20 = 41;; let _PPC_REG_F21 = 42;; let _PPC_REG_F22 = 43;; let _PPC_REG_F23 = 44;; let _PPC_REG_F24 = 45;; let _PPC_REG_F25 = 46;; let _PPC_REG_F26 = 47;; let _PPC_REG_F27 = 48;; let _PPC_REG_F28 = 49;; let _PPC_REG_F29 = 50;; let _PPC_REG_F30 = 51;; let _PPC_REG_F31 = 52;; let _PPC_REG_LR8 = 54;; let _PPC_REG_Q0 = 55;; let _PPC_REG_Q1 = 56;; let _PPC_REG_Q2 = 57;; let _PPC_REG_Q3 = 58;; let _PPC_REG_Q4 = 59;; let _PPC_REG_Q5 = 60;; let _PPC_REG_Q6 = 61;; let _PPC_REG_Q7 = 62;; let _PPC_REG_Q8 = 63;; let _PPC_REG_Q9 = 64;; let _PPC_REG_Q10 = 65;; let _PPC_REG_Q11 = 66;; let _PPC_REG_Q12 = 67;; let _PPC_REG_Q13 = 68;; let _PPC_REG_Q14 = 69;; let _PPC_REG_Q15 = 70;; let _PPC_REG_Q16 = 71;; let _PPC_REG_Q17 = 72;; let _PPC_REG_Q18 = 73;; let _PPC_REG_Q19 = 74;; let _PPC_REG_Q20 = 75;; let _PPC_REG_Q21 = 76;; let _PPC_REG_Q22 = 77;; let _PPC_REG_Q23 = 78;; let _PPC_REG_Q24 = 79;; let _PPC_REG_Q25 = 80;; let _PPC_REG_Q26 = 81;; let _PPC_REG_Q27 = 82;; let _PPC_REG_Q28 = 83;; let _PPC_REG_Q29 = 84;; let _PPC_REG_Q30 = 85;; let _PPC_REG_Q31 = 86;; let _PPC_REG_R0 = 87;; let _PPC_REG_R1 = 88;; let _PPC_REG_R2 = 89;; let _PPC_REG_R3 = 90;; let _PPC_REG_R4 = 91;; let _PPC_REG_R5 = 92;; let _PPC_REG_R6 = 93;; let _PPC_REG_R7 = 94;; let _PPC_REG_R8 = 95;; let _PPC_REG_R9 = 96;; let _PPC_REG_R10 = 97;; let _PPC_REG_R11 = 98;; let _PPC_REG_R12 = 99;; let _PPC_REG_R13 = 100;; let _PPC_REG_R14 = 101;; let _PPC_REG_R15 = 102;; let _PPC_REG_R16 = 103;; let _PPC_REG_R17 = 104;; let _PPC_REG_R18 = 105;; let _PPC_REG_R19 = 106;; let _PPC_REG_R20 = 107;; let _PPC_REG_R21 = 108;; let _PPC_REG_R22 = 109;; let _PPC_REG_R23 = 110;; let _PPC_REG_R24 = 111;; let _PPC_REG_R25 = 112;; let _PPC_REG_R26 = 113;; let _PPC_REG_R27 = 114;; let _PPC_REG_R28 = 115;; let _PPC_REG_R29 = 116;; let _PPC_REG_R30 = 117;; let _PPC_REG_R31 = 118;; let _PPC_REG_V0 = 151;; let _PPC_REG_V1 = 152;; let _PPC_REG_V2 = 153;; let _PPC_REG_V3 = 154;; let _PPC_REG_V4 = 155;; let _PPC_REG_V5 = 156;; let _PPC_REG_V6 = 157;; let _PPC_REG_V7 = 158;; let _PPC_REG_V8 = 159;; let _PPC_REG_V9 = 160;; let _PPC_REG_V10 = 161;; let _PPC_REG_V11 = 162;; let _PPC_REG_V12 = 163;; let _PPC_REG_V13 = 164;; let _PPC_REG_V14 = 165;; let _PPC_REG_V15 = 166;; let _PPC_REG_V16 = 167;; let _PPC_REG_V17 = 168;; let _PPC_REG_V18 = 169;; let _PPC_REG_V19 = 170;; let _PPC_REG_V20 = 171;; let _PPC_REG_V21 = 172;; let _PPC_REG_V22 = 173;; let _PPC_REG_V23 = 174;; let _PPC_REG_V24 = 175;; let _PPC_REG_V25 = 176;; let _PPC_REG_V26 = 177;; let _PPC_REG_V27 = 178;; let _PPC_REG_V28 = 179;; let _PPC_REG_V29 = 180;; let _PPC_REG_V30 = 181;; let _PPC_REG_V31 = 182;; let _PPC_REG_VS0 = 215;; let _PPC_REG_VS1 = 216;; let _PPC_REG_VS2 = 217;; let _PPC_REG_VS3 = 218;; let _PPC_REG_VS4 = 219;; let _PPC_REG_VS5 = 220;; let _PPC_REG_VS6 = 221;; let _PPC_REG_VS7 = 222;; let _PPC_REG_VS8 = 223;; let _PPC_REG_VS9 = 224;; let _PPC_REG_VS10 = 225;; let _PPC_REG_VS11 = 226;; let _PPC_REG_VS12 = 227;; let _PPC_REG_VS13 = 228;; let _PPC_REG_VS14 = 229;; let _PPC_REG_VS15 = 230;; let _PPC_REG_VS16 = 231;; let _PPC_REG_VS17 = 232;; let _PPC_REG_VS18 = 233;; let _PPC_REG_VS19 = 234;; let _PPC_REG_VS20 = 235;; let _PPC_REG_VS21 = 236;; let _PPC_REG_VS22 = 237;; let _PPC_REG_VS23 = 238;; let _PPC_REG_VS24 = 239;; let _PPC_REG_VS25 = 240;; let _PPC_REG_VS26 = 241;; let _PPC_REG_VS27 = 242;; let _PPC_REG_VS28 = 243;; let _PPC_REG_VS29 = 244;; let _PPC_REG_VS30 = 245;; let _PPC_REG_VS31 = 246;; let _PPC_REG_VS32 = 247;; let _PPC_REG_VS33 = 248;; let _PPC_REG_VS34 = 249;; let _PPC_REG_VS35 = 250;; let _PPC_REG_VS36 = 251;; let _PPC_REG_VS37 = 252;; let _PPC_REG_VS38 = 253;; let _PPC_REG_VS39 = 254;; let _PPC_REG_VS40 = 255;; let _PPC_REG_VS41 = 256;; let _PPC_REG_VS42 = 257;; let _PPC_REG_VS43 = 258;; let _PPC_REG_VS44 = 259;; let _PPC_REG_VS45 = 260;; let _PPC_REG_VS46 = 261;; let _PPC_REG_VS47 = 262;; let _PPC_REG_VS48 = 263;; let _PPC_REG_VS49 = 264;; let _PPC_REG_VS50 = 265;; let _PPC_REG_VS51 = 266;; let _PPC_REG_VS52 = 267;; let _PPC_REG_VS53 = 268;; let _PPC_REG_VS54 = 269;; let _PPC_REG_VS55 = 270;; let _PPC_REG_VS56 = 271;; let _PPC_REG_VS57 = 272;; let _PPC_REG_VS58 = 273;; let _PPC_REG_VS59 = 274;; let _PPC_REG_VS60 = 275;; let _PPC_REG_VS61 = 276;; let _PPC_REG_VS62 = 277;; let _PPC_REG_VS63 = 278;; let _PPC_REG_CR0EQ = 312;; let _PPC_REG_CR1EQ = 313;; let _PPC_REG_CR2EQ = 314;; let _PPC_REG_CR3EQ = 315;; let _PPC_REG_CR4EQ = 316;; let _PPC_REG_CR5EQ = 317;; let _PPC_REG_CR6EQ = 318;; let _PPC_REG_CR7EQ = 319;; let _PPC_REG_CR0GT = 320;; let _PPC_REG_CR1GT = 321;; let _PPC_REG_CR2GT = 322;; let _PPC_REG_CR3GT = 323;; let _PPC_REG_CR4GT = 324;; let _PPC_REG_CR5GT = 325;; let _PPC_REG_CR6GT = 326;; let _PPC_REG_CR7GT = 327;; let _PPC_REG_CR0LT = 328;; let _PPC_REG_CR1LT = 329;; let _PPC_REG_CR2LT = 330;; let _PPC_REG_CR3LT = 331;; let _PPC_REG_CR4LT = 332;; let _PPC_REG_CR5LT = 333;; let _PPC_REG_CR6LT = 334;; let _PPC_REG_CR7LT = 335;; let _PPC_REG_CR0UN = 336;; let _PPC_REG_CR1UN = 337;; let _PPC_REG_CR2UN = 338;; let _PPC_REG_CR3UN = 339;; let _PPC_REG_CR4UN = 340;; let _PPC_REG_CR5UN = 341;; let _PPC_REG_CR6UN = 342;; let _PPC_REG_CR7UN = 343;; let _PPC_REG_ENDING = 344;; let _PPC_INS_INVALID = 0;; let _PPC_INS_ADD = 1;; let _PPC_INS_ADDC = 2;; let _PPC_INS_ADDE = 3;; let _PPC_INS_ADDI = 4;; let _PPC_INS_ADDIC = 5;; let _PPC_INS_ADDIS = 6;; let _PPC_INS_ADDME = 7;; let _PPC_INS_ADDPCIS = 8;; let _PPC_INS_ADDZE = 9;; let _PPC_INS_AND = 10;; let _PPC_INS_ANDC = 11;; let _PPC_INS_ANDI = 12;; let _PPC_INS_ANDIS = 13;; let _PPC_INS_ATTN = 14;; let _PPC_INS_B = 15;; let _PPC_INS_BA = 16;; let _PPC_INS_BC = 17;; let _PPC_INS_BCA = 18;; let _PPC_INS_BCCTR = 19;; let _PPC_INS_BCCTRL = 20;; let _PPC_INS_BCDCFN = 21;; let _PPC_INS_BCDCFSQ = 22;; let _PPC_INS_BCDCFZ = 23;; let _PPC_INS_BCDCPSGN = 24;; let _PPC_INS_BCDCTN = 25;; let _PPC_INS_BCDCTSQ = 26;; let _PPC_INS_BCDCTZ = 27;; let _PPC_INS_BCDS = 28;; let _PPC_INS_BCDSETSGN = 29;; let _PPC_INS_BCDSR = 30;; let _PPC_INS_BCDTRUNC = 31;; let _PPC_INS_BCDUS = 32;; let _PPC_INS_BCDUTRUNC = 33;; let _PPC_INS_BCL = 34;; let _PPC_INS_BCLA = 35;; let _PPC_INS_BCLR = 36;; let _PPC_INS_BCLRL = 37;; let _PPC_INS_BCTR = 38;; let _PPC_INS_BCTRL = 39;; let _PPC_INS_BDNZ = 40;; let _PPC_INS_BDNZA = 41;; let _PPC_INS_BDNZF = 42;; let _PPC_INS_BDNZFA = 43;; let _PPC_INS_BDNZFL = 44;; let _PPC_INS_BDNZFLA = 45;; let _PPC_INS_BDNZFLR = 46;; let _PPC_INS_BDNZFLRL = 47;; let _PPC_INS_BDNZL = 48;; let _PPC_INS_BDNZLA = 49;; let _PPC_INS_BDNZLR = 50;; let _PPC_INS_BDNZLRL = 51;; let _PPC_INS_BDNZT = 52;; let _PPC_INS_BDNZTA = 53;; let _PPC_INS_BDNZTL = 54;; let _PPC_INS_BDNZTLA = 55;; let _PPC_INS_BDNZTLR = 56;; let _PPC_INS_BDNZTLRL = 57;; let _PPC_INS_BDZ = 58;; let _PPC_INS_BDZA = 59;; let _PPC_INS_BDZF = 60;; let _PPC_INS_BDZFA = 61;; let _PPC_INS_BDZFL = 62;; let _PPC_INS_BDZFLA = 63;; let _PPC_INS_BDZFLR = 64;; let _PPC_INS_BDZFLRL = 65;; let _PPC_INS_BDZL = 66;; let _PPC_INS_BDZLA = 67;; let _PPC_INS_BDZLR = 68;; let _PPC_INS_BDZLRL = 69;; let _PPC_INS_BDZT = 70;; let _PPC_INS_BDZTA = 71;; let _PPC_INS_BDZTL = 72;; let _PPC_INS_BDZTLA = 73;; let _PPC_INS_BDZTLR = 74;; let _PPC_INS_BDZTLRL = 75;; let _PPC_INS_BEQ = 76;; let _PPC_INS_BEQA = 77;; let _PPC_INS_BEQCTR = 78;; let _PPC_INS_BEQCTRL = 79;; let _PPC_INS_BEQL = 80;; let _PPC_INS_BEQLA = 81;; let _PPC_INS_BEQLR = 82;; let _PPC_INS_BEQLRL = 83;; let _PPC_INS_BF = 84;; let _PPC_INS_BFA = 85;; let _PPC_INS_BFCTR = 86;; let _PPC_INS_BFCTRL = 87;; let _PPC_INS_BFL = 88;; let _PPC_INS_BFLA = 89;; let _PPC_INS_BFLR = 90;; let _PPC_INS_BFLRL = 91;; let _PPC_INS_BGE = 92;; let _PPC_INS_BGEA = 93;; let _PPC_INS_BGECTR = 94;; let _PPC_INS_BGECTRL = 95;; let _PPC_INS_BGEL = 96;; let _PPC_INS_BGELA = 97;; let _PPC_INS_BGELR = 98;; let _PPC_INS_BGELRL = 99;; let _PPC_INS_BGT = 100;; let _PPC_INS_BGTA = 101;; let _PPC_INS_BGTCTR = 102;; let _PPC_INS_BGTCTRL = 103;; let _PPC_INS_BGTL = 104;; let _PPC_INS_BGTLA = 105;; let _PPC_INS_BGTLR = 106;; let _PPC_INS_BGTLRL = 107;; let _PPC_INS_BL = 108;; let _PPC_INS_BLA = 109;; let _PPC_INS_BLE = 110;; let _PPC_INS_BLEA = 111;; let _PPC_INS_BLECTR = 112;; let _PPC_INS_BLECTRL = 113;; let _PPC_INS_BLEL = 114;; let _PPC_INS_BLELA = 115;; let _PPC_INS_BLELR = 116;; let _PPC_INS_BLELRL = 117;; let _PPC_INS_BLR = 118;; let _PPC_INS_BLRL = 119;; let _PPC_INS_BLT = 120;; let _PPC_INS_BLTA = 121;; let _PPC_INS_BLTCTR = 122;; let _PPC_INS_BLTCTRL = 123;; let _PPC_INS_BLTL = 124;; let _PPC_INS_BLTLA = 125;; let _PPC_INS_BLTLR = 126;; let _PPC_INS_BLTLRL = 127;; let _PPC_INS_BNE = 128;; let _PPC_INS_BNEA = 129;; let _PPC_INS_BNECTR = 130;; let _PPC_INS_BNECTRL = 131;; let _PPC_INS_BNEL = 132;; let _PPC_INS_BNELA = 133;; let _PPC_INS_BNELR = 134;; let _PPC_INS_BNELRL = 135;; let _PPC_INS_BNG = 136;; let _PPC_INS_BNGA = 137;; let _PPC_INS_BNGCTR = 138;; let _PPC_INS_BNGCTRL = 139;; let _PPC_INS_BNGL = 140;; let _PPC_INS_BNGLA = 141;; let _PPC_INS_BNGLR = 142;; let _PPC_INS_BNGLRL = 143;; let _PPC_INS_BNL = 144;; let _PPC_INS_BNLA = 145;; let _PPC_INS_BNLCTR = 146;; let _PPC_INS_BNLCTRL = 147;; let _PPC_INS_BNLL = 148;; let _PPC_INS_BNLLA = 149;; let _PPC_INS_BNLLR = 150;; let _PPC_INS_BNLLRL = 151;; let _PPC_INS_BNS = 152;; let _PPC_INS_BNSA = 153;; let _PPC_INS_BNSCTR = 154;; let _PPC_INS_BNSCTRL = 155;; let _PPC_INS_BNSL = 156;; let _PPC_INS_BNSLA = 157;; let _PPC_INS_BNSLR = 158;; let _PPC_INS_BNSLRL = 159;; let _PPC_INS_BNU = 160;; let _PPC_INS_BNUA = 161;; let _PPC_INS_BNUCTR = 162;; let _PPC_INS_BNUCTRL = 163;; let _PPC_INS_BNUL = 164;; let _PPC_INS_BNULA = 165;; let _PPC_INS_BNULR = 166;; let _PPC_INS_BNULRL = 167;; let _PPC_INS_BPERMD = 168;; let _PPC_INS_BRINC = 169;; let _PPC_INS_BSO = 170;; let _PPC_INS_BSOA = 171;; let _PPC_INS_BSOCTR = 172;; let _PPC_INS_BSOCTRL = 173;; let _PPC_INS_BSOL = 174;; let _PPC_INS_BSOLA = 175;; let _PPC_INS_BSOLR = 176;; let _PPC_INS_BSOLRL = 177;; let _PPC_INS_BT = 178;; let _PPC_INS_BTA = 179;; let _PPC_INS_BTCTR = 180;; let _PPC_INS_BTCTRL = 181;; let _PPC_INS_BTL = 182;; let _PPC_INS_BTLA = 183;; let _PPC_INS_BTLR = 184;; let _PPC_INS_BTLRL = 185;; let _PPC_INS_BUN = 186;; let _PPC_INS_BUNA = 187;; let _PPC_INS_BUNCTR = 188;; let _PPC_INS_BUNCTRL = 189;; let _PPC_INS_BUNL = 190;; let _PPC_INS_BUNLA = 191;; let _PPC_INS_BUNLR = 192;; let _PPC_INS_BUNLRL = 193;; let _PPC_INS_CLRBHRB = 194;; let _PPC_INS_CLRLDI = 195;; let _PPC_INS_CLRLSLDI = 196;; let _PPC_INS_CLRLSLWI = 197;; let _PPC_INS_CLRLWI = 198;; let _PPC_INS_CLRRDI = 199;; let _PPC_INS_CLRRWI = 200;; let _PPC_INS_CMP = 201;; let _PPC_INS_CMPB = 202;; let _PPC_INS_CMPD = 203;; let _PPC_INS_CMPDI = 204;; let _PPC_INS_CMPEQB = 205;; let _PPC_INS_CMPI = 206;; let _PPC_INS_CMPL = 207;; let _PPC_INS_CMPLD = 208;; let _PPC_INS_CMPLDI = 209;; let _PPC_INS_CMPLI = 210;; let _PPC_INS_CMPLW = 211;; let _PPC_INS_CMPLWI = 212;; let _PPC_INS_CMPRB = 213;; let _PPC_INS_CMPW = 214;; let _PPC_INS_CMPWI = 215;; let _PPC_INS_CNTLZD = 216;; let _PPC_INS_CNTLZW = 217;; let _PPC_INS_CNTTZD = 218;; let _PPC_INS_CNTTZW = 219;; let _PPC_INS_COPY = 220;; let _PPC_INS_COPY_FIRST = 221;; let _PPC_INS_CP_ABORT = 222;; let _PPC_INS_CRAND = 223;; let _PPC_INS_CRANDC = 224;; let _PPC_INS_CRCLR = 225;; let _PPC_INS_CREQV = 226;; let _PPC_INS_CRMOVE = 227;; let _PPC_INS_CRNAND = 228;; let _PPC_INS_CRNOR = 229;; let _PPC_INS_CRNOT = 230;; let _PPC_INS_CROR = 231;; let _PPC_INS_CRORC = 232;; let _PPC_INS_CRSET = 233;; let _PPC_INS_CRXOR = 234;; let _PPC_INS_DARN = 235;; let _PPC_INS_DCBA = 236;; let _PPC_INS_DCBF = 237;; let _PPC_INS_DCBFEP = 238;; let _PPC_INS_DCBFL = 239;; let _PPC_INS_DCBFLP = 240;; let _PPC_INS_DCBI = 241;; let _PPC_INS_DCBST = 242;; let _PPC_INS_DCBSTEP = 243;; let _PPC_INS_DCBT = 244;; let _PPC_INS_DCBTCT = 245;; let _PPC_INS_DCBTDS = 246;; let _PPC_INS_DCBTEP = 247;; let _PPC_INS_DCBTST = 248;; let _PPC_INS_DCBTSTCT = 249;; let _PPC_INS_DCBTSTDS = 250;; let _PPC_INS_DCBTSTEP = 251;; let _PPC_INS_DCBTSTT = 252;; let _PPC_INS_DCBTT = 253;; let _PPC_INS_DCBZ = 254;; let _PPC_INS_DCBZEP = 255;; let _PPC_INS_DCBZL = 256;; let _PPC_INS_DCBZLEP = 257;; let _PPC_INS_DCCCI = 258;; let _PPC_INS_DCI = 259;; let _PPC_INS_DIVD = 260;; let _PPC_INS_DIVDE = 261;; let _PPC_INS_DIVDEU = 262;; let _PPC_INS_DIVDU = 263;; let _PPC_INS_DIVW = 264;; let _PPC_INS_DIVWE = 265;; let _PPC_INS_DIVWEU = 266;; let _PPC_INS_DIVWU = 267;; let _PPC_INS_DSS = 268;; let _PPC_INS_DSSALL = 269;; let _PPC_INS_DST = 270;; let _PPC_INS_DSTST = 271;; let _PPC_INS_DSTSTT = 272;; let _PPC_INS_DSTT = 273;; let _PPC_INS_EFDABS = 274;; let _PPC_INS_EFDADD = 275;; let _PPC_INS_EFDCFS = 276;; let _PPC_INS_EFDCFSF = 277;; let _PPC_INS_EFDCFSI = 278;; let _PPC_INS_EFDCFSID = 279;; let _PPC_INS_EFDCFUF = 280;; let _PPC_INS_EFDCFUI = 281;; let _PPC_INS_EFDCFUID = 282;; let _PPC_INS_EFDCMPEQ = 283;; let _PPC_INS_EFDCMPGT = 284;; let _PPC_INS_EFDCMPLT = 285;; let _PPC_INS_EFDCTSF = 286;; let _PPC_INS_EFDCTSI = 287;; let _PPC_INS_EFDCTSIDZ = 288;; let _PPC_INS_EFDCTSIZ = 289;; let _PPC_INS_EFDCTUF = 290;; let _PPC_INS_EFDCTUI = 291;; let _PPC_INS_EFDCTUIDZ = 292;; let _PPC_INS_EFDCTUIZ = 293;; let _PPC_INS_EFDDIV = 294;; let _PPC_INS_EFDMUL = 295;; let _PPC_INS_EFDNABS = 296;; let _PPC_INS_EFDNEG = 297;; let _PPC_INS_EFDSUB = 298;; let _PPC_INS_EFDTSTEQ = 299;; let _PPC_INS_EFDTSTGT = 300;; let _PPC_INS_EFDTSTLT = 301;; let _PPC_INS_EFSABS = 302;; let _PPC_INS_EFSADD = 303;; let _PPC_INS_EFSCFD = 304;; let _PPC_INS_EFSCFSF = 305;; let _PPC_INS_EFSCFSI = 306;; let _PPC_INS_EFSCFUF = 307;; let _PPC_INS_EFSCFUI = 308;; let _PPC_INS_EFSCMPEQ = 309;; let _PPC_INS_EFSCMPGT = 310;; let _PPC_INS_EFSCMPLT = 311;; let _PPC_INS_EFSCTSF = 312;; let _PPC_INS_EFSCTSI = 313;; let _PPC_INS_EFSCTSIZ = 314;; let _PPC_INS_EFSCTUF = 315;; let _PPC_INS_EFSCTUI = 316;; let _PPC_INS_EFSCTUIZ = 317;; let _PPC_INS_EFSDIV = 318;; let _PPC_INS_EFSMUL = 319;; let _PPC_INS_EFSNABS = 320;; let _PPC_INS_EFSNEG = 321;; let _PPC_INS_EFSSUB = 322;; let _PPC_INS_EFSTSTEQ = 323;; let _PPC_INS_EFSTSTGT = 324;; let _PPC_INS_EFSTSTLT = 325;; let _PPC_INS_EIEIO = 326;; let _PPC_INS_EQV = 327;; let _PPC_INS_EVABS = 328;; let _PPC_INS_EVADDIW = 329;; let _PPC_INS_EVADDSMIAAW = 330;; let _PPC_INS_EVADDSSIAAW = 331;; let _PPC_INS_EVADDUMIAAW = 332;; let _PPC_INS_EVADDUSIAAW = 333;; let _PPC_INS_EVADDW = 334;; let _PPC_INS_EVAND = 335;; let _PPC_INS_EVANDC = 336;; let _PPC_INS_EVCMPEQ = 337;; let _PPC_INS_EVCMPGTS = 338;; let _PPC_INS_EVCMPGTU = 339;; let _PPC_INS_EVCMPLTS = 340;; let _PPC_INS_EVCMPLTU = 341;; let _PPC_INS_EVCNTLSW = 342;; let _PPC_INS_EVCNTLZW = 343;; let _PPC_INS_EVDIVWS = 344;; let _PPC_INS_EVDIVWU = 345;; let _PPC_INS_EVEQV = 346;; let _PPC_INS_EVEXTSB = 347;; let _PPC_INS_EVEXTSH = 348;; let _PPC_INS_EVFSABS = 349;; let _PPC_INS_EVFSADD = 350;; let _PPC_INS_EVFSCFSF = 351;; let _PPC_INS_EVFSCFSI = 352;; let _PPC_INS_EVFSCFUF = 353;; let _PPC_INS_EVFSCFUI = 354;; let _PPC_INS_EVFSCMPEQ = 355;; let _PPC_INS_EVFSCMPGT = 356;; let _PPC_INS_EVFSCMPLT = 357;; let _PPC_INS_EVFSCTSF = 358;; let _PPC_INS_EVFSCTSI = 359;; let _PPC_INS_EVFSCTSIZ = 360;; let _PPC_INS_EVFSCTUI = 361;; let _PPC_INS_EVFSDIV = 362;; let _PPC_INS_EVFSMUL = 363;; let _PPC_INS_EVFSNABS = 364;; let _PPC_INS_EVFSNEG = 365;; let _PPC_INS_EVFSSUB = 366;; let _PPC_INS_EVFSTSTEQ = 367;; let _PPC_INS_EVFSTSTGT = 368;; let _PPC_INS_EVFSTSTLT = 369;; let _PPC_INS_EVLDD = 370;; let _PPC_INS_EVLDDX = 371;; let _PPC_INS_EVLDH = 372;; let _PPC_INS_EVLDHX = 373;; let _PPC_INS_EVLDW = 374;; let _PPC_INS_EVLDWX = 375;; let _PPC_INS_EVLHHESPLAT = 376;; let _PPC_INS_EVLHHESPLATX = 377;; let _PPC_INS_EVLHHOSSPLAT = 378;; let _PPC_INS_EVLHHOSSPLATX = 379;; let _PPC_INS_EVLHHOUSPLAT = 380;; let _PPC_INS_EVLHHOUSPLATX = 381;; let _PPC_INS_EVLWHE = 382;; let _PPC_INS_EVLWHEX = 383;; let _PPC_INS_EVLWHOS = 384;; let _PPC_INS_EVLWHOSX = 385;; let _PPC_INS_EVLWHOU = 386;; let _PPC_INS_EVLWHOUX = 387;; let _PPC_INS_EVLWHSPLAT = 388;; let _PPC_INS_EVLWHSPLATX = 389;; let _PPC_INS_EVLWWSPLAT = 390;; let _PPC_INS_EVLWWSPLATX = 391;; let _PPC_INS_EVMERGEHI = 392;; let _PPC_INS_EVMERGEHILO = 393;; let _PPC_INS_EVMERGELO = 394;; let _PPC_INS_EVMERGELOHI = 395;; let _PPC_INS_EVMHEGSMFAA = 396;; let _PPC_INS_EVMHEGSMFAN = 397;; let _PPC_INS_EVMHEGSMIAA = 398;; let _PPC_INS_EVMHEGSMIAN = 399;; let _PPC_INS_EVMHEGUMIAA = 400;; let _PPC_INS_EVMHEGUMIAN = 401;; let _PPC_INS_EVMHESMF = 402;; let _PPC_INS_EVMHESMFA = 403;; let _PPC_INS_EVMHESMFAAW = 404;; let _PPC_INS_EVMHESMFANW = 405;; let _PPC_INS_EVMHESMI = 406;; let _PPC_INS_EVMHESMIA = 407;; let _PPC_INS_EVMHESMIAAW = 408;; let _PPC_INS_EVMHESMIANW = 409;; let _PPC_INS_EVMHESSF = 410;; let _PPC_INS_EVMHESSFA = 411;; let _PPC_INS_EVMHESSFAAW = 412;; let _PPC_INS_EVMHESSFANW = 413;; let _PPC_INS_EVMHESSIAAW = 414;; let _PPC_INS_EVMHESSIANW = 415;; let _PPC_INS_EVMHEUMI = 416;; let _PPC_INS_EVMHEUMIA = 417;; let _PPC_INS_EVMHEUMIAAW = 418;; let _PPC_INS_EVMHEUMIANW = 419;; let _PPC_INS_EVMHEUSIAAW = 420;; let _PPC_INS_EVMHEUSIANW = 421;; let _PPC_INS_EVMHOGSMFAA = 422;; let _PPC_INS_EVMHOGSMFAN = 423;; let _PPC_INS_EVMHOGSMIAA = 424;; let _PPC_INS_EVMHOGSMIAN = 425;; let _PPC_INS_EVMHOGUMIAA = 426;; let _PPC_INS_EVMHOGUMIAN = 427;; let _PPC_INS_EVMHOSMF = 428;; let _PPC_INS_EVMHOSMFA = 429;; let _PPC_INS_EVMHOSMFAAW = 430;; let _PPC_INS_EVMHOSMFANW = 431;; let _PPC_INS_EVMHOSMI = 432;; let _PPC_INS_EVMHOSMIA = 433;; let _PPC_INS_EVMHOSMIAAW = 434;; let _PPC_INS_EVMHOSMIANW = 435;; let _PPC_INS_EVMHOSSF = 436;; let _PPC_INS_EVMHOSSFA = 437;; let _PPC_INS_EVMHOSSFAAW = 438;; let _PPC_INS_EVMHOSSFANW = 439;; let _PPC_INS_EVMHOSSIAAW = 440;; let _PPC_INS_EVMHOSSIANW = 441;; let _PPC_INS_EVMHOUMI = 442;; let _PPC_INS_EVMHOUMIA = 443;; let _PPC_INS_EVMHOUMIAAW = 444;; let _PPC_INS_EVMHOUMIANW = 445;; let _PPC_INS_EVMHOUSIAAW = 446;; let _PPC_INS_EVMHOUSIANW = 447;; let _PPC_INS_EVMRA = 448;; let _PPC_INS_EVMWHSMF = 449;; let _PPC_INS_EVMWHSMFA = 450;; let _PPC_INS_EVMWHSMI = 451;; let _PPC_INS_EVMWHSMIA = 452;; let _PPC_INS_EVMWHSSF = 453;; let _PPC_INS_EVMWHSSFA = 454;; let _PPC_INS_EVMWHUMI = 455;; let _PPC_INS_EVMWHUMIA = 456;; let _PPC_INS_EVMWLSMIAAW = 457;; let _PPC_INS_EVMWLSMIANW = 458;; let _PPC_INS_EVMWLSSIAAW = 459;; let _PPC_INS_EVMWLSSIANW = 460;; let _PPC_INS_EVMWLUMI = 461;; let _PPC_INS_EVMWLUMIA = 462;; let _PPC_INS_EVMWLUMIAAW = 463;; let _PPC_INS_EVMWLUMIANW = 464;; let _PPC_INS_EVMWLUSIAAW = 465;; let _PPC_INS_EVMWLUSIANW = 466;; let _PPC_INS_EVMWSMF = 467;; let _PPC_INS_EVMWSMFA = 468;; let _PPC_INS_EVMWSMFAA = 469;; let _PPC_INS_EVMWSMFAN = 470;; let _PPC_INS_EVMWSMI = 471;; let _PPC_INS_EVMWSMIA = 472;; let _PPC_INS_EVMWSMIAA = 473;; let _PPC_INS_EVMWSMIAN = 474;; let _PPC_INS_EVMWSSF = 475;; let _PPC_INS_EVMWSSFA = 476;; let _PPC_INS_EVMWSSFAA = 477;; let _PPC_INS_EVMWSSFAN = 478;; let _PPC_INS_EVMWUMI = 479;; let _PPC_INS_EVMWUMIA = 480;; let _PPC_INS_EVMWUMIAA = 481;; let _PPC_INS_EVMWUMIAN = 482;; let _PPC_INS_EVNAND = 483;; let _PPC_INS_EVNEG = 484;; let _PPC_INS_EVNOR = 485;; let _PPC_INS_EVOR = 486;; let _PPC_INS_EVORC = 487;; let _PPC_INS_EVRLW = 488;; let _PPC_INS_EVRLWI = 489;; let _PPC_INS_EVRNDW = 490;; let _PPC_INS_EVSEL = 491;; let _PPC_INS_EVSLW = 492;; let _PPC_INS_EVSLWI = 493;; let _PPC_INS_EVSPLATFI = 494;; let _PPC_INS_EVSPLATI = 495;; let _PPC_INS_EVSRWIS = 496;; let _PPC_INS_EVSRWIU = 497;; let _PPC_INS_EVSRWS = 498;; let _PPC_INS_EVSRWU = 499;; let _PPC_INS_EVSTDD = 500;; let _PPC_INS_EVSTDDX = 501;; let _PPC_INS_EVSTDH = 502;; let _PPC_INS_EVSTDHX = 503;; let _PPC_INS_EVSTDW = 504;; let _PPC_INS_EVSTDWX = 505;; let _PPC_INS_EVSTWHE = 506;; let _PPC_INS_EVSTWHEX = 507;; let _PPC_INS_EVSTWHO = 508;; let _PPC_INS_EVSTWHOX = 509;; let _PPC_INS_EVSTWWE = 510;; let _PPC_INS_EVSTWWEX = 511;; let _PPC_INS_EVSTWWO = 512;; let _PPC_INS_EVSTWWOX = 513;; let _PPC_INS_EVSUBFSMIAAW = 514;; let _PPC_INS_EVSUBFSSIAAW = 515;; let _PPC_INS_EVSUBFUMIAAW = 516;; let _PPC_INS_EVSUBFUSIAAW = 517;; let _PPC_INS_EVSUBFW = 518;; let _PPC_INS_EVSUBIFW = 519;; let _PPC_INS_EVXOR = 520;; let _PPC_INS_EXTLDI = 521;; let _PPC_INS_EXTLWI = 522;; let _PPC_INS_EXTRDI = 523;; let _PPC_INS_EXTRWI = 524;; let _PPC_INS_EXTSB = 525;; let _PPC_INS_EXTSH = 526;; let _PPC_INS_EXTSW = 527;; let _PPC_INS_EXTSWSLI = 528;; let _PPC_INS_FABS = 529;; let _PPC_INS_FADD = 530;; let _PPC_INS_FADDS = 531;; let _PPC_INS_FCFID = 532;; let _PPC_INS_FCFIDS = 533;; let _PPC_INS_FCFIDU = 534;; let _PPC_INS_FCFIDUS = 535;; let _PPC_INS_FCMPU = 536;; let _PPC_INS_FCPSGN = 537;; let _PPC_INS_FCTID = 538;; let _PPC_INS_FCTIDU = 539;; let _PPC_INS_FCTIDUZ = 540;; let _PPC_INS_FCTIDZ = 541;; let _PPC_INS_FCTIW = 542;; let _PPC_INS_FCTIWU = 543;; let _PPC_INS_FCTIWUZ = 544;; let _PPC_INS_FCTIWZ = 545;; let _PPC_INS_FDIV = 546;; let _PPC_INS_FDIVS = 547;; let _PPC_INS_FMADD = 548;; let _PPC_INS_FMADDS = 549;; let _PPC_INS_FMR = 550;; let _PPC_INS_FMSUB = 551;; let _PPC_INS_FMSUBS = 552;; let _PPC_INS_FMUL = 553;; let _PPC_INS_FMULS = 554;; let _PPC_INS_FNABS = 555;; let _PPC_INS_FNEG = 556;; let _PPC_INS_FNMADD = 557;; let _PPC_INS_FNMADDS = 558;; let _PPC_INS_FNMSUB = 559;; let _PPC_INS_FNMSUBS = 560;; let _PPC_INS_FRE = 561;; let _PPC_INS_FRES = 562;; let _PPC_INS_FRIM = 563;; let _PPC_INS_FRIN = 564;; let _PPC_INS_FRIP = 565;; let _PPC_INS_FRIZ = 566;; let _PPC_INS_FRSP = 567;; let _PPC_INS_FRSQRTE = 568;; let _PPC_INS_FRSQRTES = 569;; let _PPC_INS_FSEL = 570;; let _PPC_INS_FSQRT = 571;; let _PPC_INS_FSQRTS = 572;; let _PPC_INS_FSUB = 573;; let _PPC_INS_FSUBS = 574;; let _PPC_INS_FTDIV = 575;; let _PPC_INS_FTSQRT = 576;; let _PPC_INS_HRFID = 577;; let _PPC_INS_ICBI = 578;; let _PPC_INS_ICBIEP = 579;; let _PPC_INS_ICBLC = 580;; let _PPC_INS_ICBLQ = 581;; let _PPC_INS_ICBT = 582;; let _PPC_INS_ICBTLS = 583;; let _PPC_INS_ICCCI = 584;; let _PPC_INS_ICI = 585;; let _PPC_INS_INSLWI = 586;; let _PPC_INS_INSRDI = 587;; let _PPC_INS_INSRWI = 588;; let _PPC_INS_ISEL = 589;; let _PPC_INS_ISYNC = 590;; let _PPC_INS_LA = 591;; let _PPC_INS_LBARX = 592;; let _PPC_INS_LBEPX = 593;; let _PPC_INS_LBZ = 594;; let _PPC_INS_LBZCIX = 595;; let _PPC_INS_LBZU = 596;; let _PPC_INS_LBZUX = 597;; let _PPC_INS_LBZX = 598;; let _PPC_INS_LD = 599;; let _PPC_INS_LDARX = 600;; let _PPC_INS_LDAT = 601;; let _PPC_INS_LDBRX = 602;; let _PPC_INS_LDCIX = 603;; let _PPC_INS_LDMX = 604;; let _PPC_INS_LDU = 605;; let _PPC_INS_LDUX = 606;; let _PPC_INS_LDX = 607;; let _PPC_INS_LFD = 608;; let _PPC_INS_LFDEPX = 609;; let _PPC_INS_LFDU = 610;; let _PPC_INS_LFDUX = 611;; let _PPC_INS_LFDX = 612;; let _PPC_INS_LFIWAX = 613;; let _PPC_INS_LFIWZX = 614;; let _PPC_INS_LFS = 615;; let _PPC_INS_LFSU = 616;; let _PPC_INS_LFSUX = 617;; let _PPC_INS_LFSX = 618;; let _PPC_INS_LHA = 619;; let _PPC_INS_LHARX = 620;; let _PPC_INS_LHAU = 621;; let _PPC_INS_LHAUX = 622;; let _PPC_INS_LHAX = 623;; let _PPC_INS_LHBRX = 624;; let _PPC_INS_LHEPX = 625;; let _PPC_INS_LHZ = 626;; let _PPC_INS_LHZCIX = 627;; let _PPC_INS_LHZU = 628;; let _PPC_INS_LHZUX = 629;; let _PPC_INS_LHZX = 630;; let _PPC_INS_LI = 631;; let _PPC_INS_LIS = 632;; let _PPC_INS_LMW = 633;; let _PPC_INS_LNIA = 634;; let _PPC_INS_LSWI = 635;; let _PPC_INS_LVEBX = 636;; let _PPC_INS_LVEHX = 637;; let _PPC_INS_LVEWX = 638;; let _PPC_INS_LVSL = 639;; let _PPC_INS_LVSR = 640;; let _PPC_INS_LVX = 641;; let _PPC_INS_LVXL = 642;; let _PPC_INS_LWA = 643;; let _PPC_INS_LWARX = 644;; let _PPC_INS_LWAT = 645;; let _PPC_INS_LWAUX = 646;; let _PPC_INS_LWAX = 647;; let _PPC_INS_LWBRX = 648;; let _PPC_INS_LWEPX = 649;; let _PPC_INS_LWSYNC = 650;; let _PPC_INS_LWZ = 651;; let _PPC_INS_LWZCIX = 652;; let _PPC_INS_LWZU = 653;; let _PPC_INS_LWZUX = 654;; let _PPC_INS_LWZX = 655;; let _PPC_INS_LXSD = 656;; let _PPC_INS_LXSDX = 657;; let _PPC_INS_LXSIBZX = 658;; let _PPC_INS_LXSIHZX = 659;; let _PPC_INS_LXSIWAX = 660;; let _PPC_INS_LXSIWZX = 661;; let _PPC_INS_LXSSP = 662;; let _PPC_INS_LXSSPX = 663;; let _PPC_INS_LXV = 664;; let _PPC_INS_LXVB16X = 665;; let _PPC_INS_LXVD2X = 666;; let _PPC_INS_LXVDSX = 667;; let _PPC_INS_LXVH8X = 668;; let _PPC_INS_LXVL = 669;; let _PPC_INS_LXVLL = 670;; let _PPC_INS_LXVW4X = 671;; let _PPC_INS_LXVWSX = 672;; let _PPC_INS_LXVX = 673;; let _PPC_INS_MADDHD = 674;; let _PPC_INS_MADDHDU = 675;; let _PPC_INS_MADDLD = 676;; let _PPC_INS_MBAR = 677;; let _PPC_INS_MCRF = 678;; let _PPC_INS_MCRFS = 679;; let _PPC_INS_MCRXRX = 680;; let _PPC_INS_MFAMR = 681;; let _PPC_INS_MFASR = 682;; let _PPC_INS_MFBHRBE = 683;; let _PPC_INS_MFBR0 = 684;; let _PPC_INS_MFBR1 = 685;; let _PPC_INS_MFBR2 = 686;; let _PPC_INS_MFBR3 = 687;; let _PPC_INS_MFBR4 = 688;; let _PPC_INS_MFBR5 = 689;; let _PPC_INS_MFBR6 = 690;; let _PPC_INS_MFBR7 = 691;; let _PPC_INS_MFCFAR = 692;; let _PPC_INS_MFCR = 693;; let _PPC_INS_MFCTR = 694;; let _PPC_INS_MFDAR = 695;; let _PPC_INS_MFDBATL = 696;; let _PPC_INS_MFDBATU = 697;; let _PPC_INS_MFDCCR = 698;; let _PPC_INS_MFDCR = 699;; let _PPC_INS_MFDEAR = 700;; let _PPC_INS_MFDEC = 701;; let _PPC_INS_MFDSCR = 702;; let _PPC_INS_MFDSISR = 703;; let _PPC_INS_MFESR = 704;; let _PPC_INS_MFFPRD = 705;; let _PPC_INS_MFFS = 706;; let _PPC_INS_MFFSCDRN = 707;; let _PPC_INS_MFFSCDRNI = 708;; let _PPC_INS_MFFSCE = 709;; let _PPC_INS_MFFSCRN = 710;; let _PPC_INS_MFFSCRNI = 711;; let _PPC_INS_MFFSL = 712;; let _PPC_INS_MFIBATL = 713;; let _PPC_INS_MFIBATU = 714;; let _PPC_INS_MFICCR = 715;; let _PPC_INS_MFLR = 716;; let _PPC_INS_MFMSR = 717;; let _PPC_INS_MFOCRF = 718;; let _PPC_INS_MFPID = 719;; let _PPC_INS_MFPMR = 720;; let _PPC_INS_MFPVR = 721;; let _PPC_INS_MFRTCL = 722;; let _PPC_INS_MFRTCU = 723;; let _PPC_INS_MFSDR1 = 724;; let _PPC_INS_MFSPEFSCR = 725;; let _PPC_INS_MFSPR = 726;; let _PPC_INS_MFSPRG = 727;; let _PPC_INS_MFSPRG0 = 728;; let _PPC_INS_MFSPRG1 = 729;; let _PPC_INS_MFSPRG2 = 730;; let _PPC_INS_MFSPRG3 = 731;; let _PPC_INS_MFSPRG4 = 732;; let _PPC_INS_MFSPRG5 = 733;; let _PPC_INS_MFSPRG6 = 734;; let _PPC_INS_MFSPRG7 = 735;; let _PPC_INS_MFSR = 736;; let _PPC_INS_MFSRIN = 737;; let _PPC_INS_MFSRR0 = 738;; let _PPC_INS_MFSRR1 = 739;; let _PPC_INS_MFSRR2 = 740;; let _PPC_INS_MFSRR3 = 741;; let _PPC_INS_MFTB = 742;; let _PPC_INS_MFTBHI = 743;; let _PPC_INS_MFTBL = 744;; let _PPC_INS_MFTBLO = 745;; let _PPC_INS_MFTBU = 746;; let _PPC_INS_MFTCR = 747;; let _PPC_INS_MFVRD = 748;; let _PPC_INS_MFVRSAVE = 749;; let _PPC_INS_MFVSCR = 750;; let _PPC_INS_MFVSRD = 751;; let _PPC_INS_MFVSRLD = 752;; let _PPC_INS_MFVSRWZ = 753;; let _PPC_INS_MFXER = 754;; let _PPC_INS_MODSD = 755;; let _PPC_INS_MODSW = 756;; let _PPC_INS_MODUD = 757;; let _PPC_INS_MODUW = 758;; let _PPC_INS_MR = 759;; let _PPC_INS_MSGSYNC = 760;; let _PPC_INS_MSYNC = 761;; let _PPC_INS_MTAMR = 762;; let _PPC_INS_MTASR = 763;; let _PPC_INS_MTBR0 = 764;; let _PPC_INS_MTBR1 = 765;; let _PPC_INS_MTBR2 = 766;; let _PPC_INS_MTBR3 = 767;; let _PPC_INS_MTBR4 = 768;; let _PPC_INS_MTBR5 = 769;; let _PPC_INS_MTBR6 = 770;; let _PPC_INS_MTBR7 = 771;; let _PPC_INS_MTCFAR = 772;; let _PPC_INS_MTCR = 773;; let _PPC_INS_MTCRF = 774;; let _PPC_INS_MTCTR = 775;; let _PPC_INS_MTDAR = 776;; let _PPC_INS_MTDBATL = 777;; let _PPC_INS_MTDBATU = 778;; let _PPC_INS_MTDCCR = 779;; let _PPC_INS_MTDCR = 780;; let _PPC_INS_MTDEAR = 781;; let _PPC_INS_MTDEC = 782;; let _PPC_INS_MTDSCR = 783;; let _PPC_INS_MTDSISR = 784;; let _PPC_INS_MTESR = 785;; let _PPC_INS_MTFSB0 = 786;; let _PPC_INS_MTFSB1 = 787;; let _PPC_INS_MTFSF = 788;; let _PPC_INS_MTFSFI = 789;; let _PPC_INS_MTIBATL = 790;; let _PPC_INS_MTIBATU = 791;; let _PPC_INS_MTICCR = 792;; let _PPC_INS_MTLR = 793;; let _PPC_INS_MTMSR = 794;; let _PPC_INS_MTMSRD = 795;; let _PPC_INS_MTOCRF = 796;; let _PPC_INS_MTPID = 797;; let _PPC_INS_MTPMR = 798;; let _PPC_INS_MTSDR1 = 799;; let _PPC_INS_MTSPEFSCR = 800;; let _PPC_INS_MTSPR = 801;; let _PPC_INS_MTSPRG = 802;; let _PPC_INS_MTSPRG0 = 803;; let _PPC_INS_MTSPRG1 = 804;; let _PPC_INS_MTSPRG2 = 805;; let _PPC_INS_MTSPRG3 = 806;; let _PPC_INS_MTSPRG4 = 807;; let _PPC_INS_MTSPRG5 = 808;; let _PPC_INS_MTSPRG6 = 809;; let _PPC_INS_MTSPRG7 = 810;; let _PPC_INS_MTSR = 811;; let _PPC_INS_MTSRIN = 812;; let _PPC_INS_MTSRR0 = 813;; let _PPC_INS_MTSRR1 = 814;; let _PPC_INS_MTSRR2 = 815;; let _PPC_INS_MTSRR3 = 816;; let _PPC_INS_MTTBHI = 817;; let _PPC_INS_MTTBL = 818;; let _PPC_INS_MTTBLO = 819;; let _PPC_INS_MTTBU = 820;; let _PPC_INS_MTTCR = 821;; let _PPC_INS_MTVRSAVE = 822;; let _PPC_INS_MTVSCR = 823;; let _PPC_INS_MTVSRD = 824;; let _PPC_INS_MTVSRDD = 825;; let _PPC_INS_MTVSRWA = 826;; let _PPC_INS_MTVSRWS = 827;; let _PPC_INS_MTVSRWZ = 828;; let _PPC_INS_MTXER = 829;; let _PPC_INS_MULHD = 830;; let _PPC_INS_MULHDU = 831;; let _PPC_INS_MULHW = 832;; let _PPC_INS_MULHWU = 833;; let _PPC_INS_MULLD = 834;; let _PPC_INS_MULLI = 835;; let _PPC_INS_MULLW = 836;; let _PPC_INS_NAND = 837;; let _PPC_INS_NAP = 838;; let _PPC_INS_NEG = 839;; let _PPC_INS_NOP = 840;; let _PPC_INS_NOR = 841;; let _PPC_INS_NOT = 842;; let _PPC_INS_OR = 843;; let _PPC_INS_ORC = 844;; let _PPC_INS_ORI = 845;; let _PPC_INS_ORIS = 846;; let _PPC_INS_PASTE = 847;; let _PPC_INS_PASTE_LAST = 848;; let _PPC_INS_POPCNTB = 849;; let _PPC_INS_POPCNTD = 850;; let _PPC_INS_POPCNTW = 851;; let _PPC_INS_PTESYNC = 852;; let _PPC_INS_QVALIGNI = 853;; let _PPC_INS_QVESPLATI = 854;; let _PPC_INS_QVFABS = 855;; let _PPC_INS_QVFADD = 856;; let _PPC_INS_QVFADDS = 857;; let _PPC_INS_QVFAND = 858;; let _PPC_INS_QVFANDC = 859;; let _PPC_INS_QVFCFID = 860;; let _PPC_INS_QVFCFIDS = 861;; let _PPC_INS_QVFCFIDU = 862;; let _PPC_INS_QVFCFIDUS = 863;; let _PPC_INS_QVFCLR = 864;; let _PPC_INS_QVFCMPEQ = 865;; let _PPC_INS_QVFCMPGT = 866;; let _PPC_INS_QVFCMPLT = 867;; let _PPC_INS_QVFCPSGN = 868;; let _PPC_INS_QVFCTFB = 869;; let _PPC_INS_QVFCTID = 870;; let _PPC_INS_QVFCTIDU = 871;; let _PPC_INS_QVFCTIDUZ = 872;; let _PPC_INS_QVFCTIDZ = 873;; let _PPC_INS_QVFCTIW = 874;; let _PPC_INS_QVFCTIWU = 875;; let _PPC_INS_QVFCTIWUZ = 876;; let _PPC_INS_QVFCTIWZ = 877;; let _PPC_INS_QVFEQU = 878;; let _PPC_INS_QVFLOGICAL = 879;; let _PPC_INS_QVFMADD = 880;; let _PPC_INS_QVFMADDS = 881;; let _PPC_INS_QVFMR = 882;; let _PPC_INS_QVFMSUB = 883;; let _PPC_INS_QVFMSUBS = 884;; let _PPC_INS_QVFMUL = 885;; let _PPC_INS_QVFMULS = 886;; let _PPC_INS_QVFNABS = 887;; let _PPC_INS_QVFNAND = 888;; let _PPC_INS_QVFNEG = 889;; let _PPC_INS_QVFNMADD = 890;; let _PPC_INS_QVFNMADDS = 891;; let _PPC_INS_QVFNMSUB = 892;; let _PPC_INS_QVFNMSUBS = 893;; let _PPC_INS_QVFNOR = 894;; let _PPC_INS_QVFNOT = 895;; let _PPC_INS_QVFOR = 896;; let _PPC_INS_QVFORC = 897;; let _PPC_INS_QVFPERM = 898;; let _PPC_INS_QVFRE = 899;; let _PPC_INS_QVFRES = 900;; let _PPC_INS_QVFRIM = 901;; let _PPC_INS_QVFRIN = 902;; let _PPC_INS_QVFRIP = 903;; let _PPC_INS_QVFRIZ = 904;; let _PPC_INS_QVFRSP = 905;; let _PPC_INS_QVFRSQRTE = 906;; let _PPC_INS_QVFRSQRTES = 907;; let _PPC_INS_QVFSEL = 908;; let _PPC_INS_QVFSET = 909;; let _PPC_INS_QVFSUB = 910;; let _PPC_INS_QVFSUBS = 911;; let _PPC_INS_QVFTSTNAN = 912;; let _PPC_INS_QVFXMADD = 913;; let _PPC_INS_QVFXMADDS = 914;; let _PPC_INS_QVFXMUL = 915;; let _PPC_INS_QVFXMULS = 916;; let _PPC_INS_QVFXOR = 917;; let _PPC_INS_QVFXXCPNMADD = 918;; let _PPC_INS_QVFXXCPNMADDS = 919;; let _PPC_INS_QVFXXMADD = 920;; let _PPC_INS_QVFXXMADDS = 921;; let _PPC_INS_QVFXXNPMADD = 922;; let _PPC_INS_QVFXXNPMADDS = 923;; let _PPC_INS_QVGPCI = 924;; let _PPC_INS_QVLFCDUX = 925;; let _PPC_INS_QVLFCDUXA = 926;; let _PPC_INS_QVLFCDX = 927;; let _PPC_INS_QVLFCDXA = 928;; let _PPC_INS_QVLFCSUX = 929;; let _PPC_INS_QVLFCSUXA = 930;; let _PPC_INS_QVLFCSX = 931;; let _PPC_INS_QVLFCSXA = 932;; let _PPC_INS_QVLFDUX = 933;; let _PPC_INS_QVLFDUXA = 934;; let _PPC_INS_QVLFDX = 935;; let _PPC_INS_QVLFDXA = 936;; let _PPC_INS_QVLFIWAX = 937;; let _PPC_INS_QVLFIWAXA = 938;; let _PPC_INS_QVLFIWZX = 939;; let _PPC_INS_QVLFIWZXA = 940;; let _PPC_INS_QVLFSUX = 941;; let _PPC_INS_QVLFSUXA = 942;; let _PPC_INS_QVLFSX = 943;; let _PPC_INS_QVLFSXA = 944;; let _PPC_INS_QVLPCLDX = 945;; let _PPC_INS_QVLPCLSX = 946;; let _PPC_INS_QVLPCRDX = 947;; let _PPC_INS_QVLPCRSX = 948;; let _PPC_INS_QVSTFCDUX = 949;; let _PPC_INS_QVSTFCDUXA = 950;; let _PPC_INS_QVSTFCDUXI = 951;; let _PPC_INS_QVSTFCDUXIA = 952;; let _PPC_INS_QVSTFCDX = 953;; let _PPC_INS_QVSTFCDXA = 954;; let _PPC_INS_QVSTFCDXI = 955;; let _PPC_INS_QVSTFCDXIA = 956;; let _PPC_INS_QVSTFCSUX = 957;; let _PPC_INS_QVSTFCSUXA = 958;; let _PPC_INS_QVSTFCSUXI = 959;; let _PPC_INS_QVSTFCSUXIA = 960;; let _PPC_INS_QVSTFCSX = 961;; let _PPC_INS_QVSTFCSXA = 962;; let _PPC_INS_QVSTFCSXI = 963;; let _PPC_INS_QVSTFCSXIA = 964;; let _PPC_INS_QVSTFDUX = 965;; let _PPC_INS_QVSTFDUXA = 966;; let _PPC_INS_QVSTFDUXI = 967;; let _PPC_INS_QVSTFDUXIA = 968;; let _PPC_INS_QVSTFDX = 969;; let _PPC_INS_QVSTFDXA = 970;; let _PPC_INS_QVSTFDXI = 971;; let _PPC_INS_QVSTFDXIA = 972;; let _PPC_INS_QVSTFIWX = 973;; let _PPC_INS_QVSTFIWXA = 974;; let _PPC_INS_QVSTFSUX = 975;; let _PPC_INS_QVSTFSUXA = 976;; let _PPC_INS_QVSTFSUXI = 977;; let _PPC_INS_QVSTFSUXIA = 978;; let _PPC_INS_QVSTFSX = 979;; let _PPC_INS_QVSTFSXA = 980;; let _PPC_INS_QVSTFSXI = 981;; let _PPC_INS_QVSTFSXIA = 982;; let _PPC_INS_RFCI = 983;; let _PPC_INS_RFDI = 984;; let _PPC_INS_RFEBB = 985;; let _PPC_INS_RFI = 986;; let _PPC_INS_RFID = 987;; let _PPC_INS_RFMCI = 988;; let _PPC_INS_RLDCL = 989;; let _PPC_INS_RLDCR = 990;; let _PPC_INS_RLDIC = 991;; let _PPC_INS_RLDICL = 992;; let _PPC_INS_RLDICR = 993;; let _PPC_INS_RLDIMI = 994;; let _PPC_INS_RLWIMI = 995;; let _PPC_INS_RLWINM = 996;; let _PPC_INS_RLWNM = 997;; let _PPC_INS_ROTLD = 998;; let _PPC_INS_ROTLDI = 999;; let _PPC_INS_ROTLW = 1000;; let _PPC_INS_ROTLWI = 1001;; let _PPC_INS_ROTRDI = 1002;; let _PPC_INS_ROTRWI = 1003;; let _PPC_INS_SC = 1004;; let _PPC_INS_SETB = 1005;; let _PPC_INS_SLBIA = 1006;; let _PPC_INS_SLBIE = 1007;; let _PPC_INS_SLBIEG = 1008;; let _PPC_INS_SLBMFEE = 1009;; let _PPC_INS_SLBMFEV = 1010;; let _PPC_INS_SLBMTE = 1011;; let _PPC_INS_SLBSYNC = 1012;; let _PPC_INS_SLD = 1013;; let _PPC_INS_SLDI = 1014;; let _PPC_INS_SLW = 1015;; let _PPC_INS_SLWI = 1016;; let _PPC_INS_SRAD = 1017;; let _PPC_INS_SRADI = 1018;; let _PPC_INS_SRAW = 1019;; let _PPC_INS_SRAWI = 1020;; let _PPC_INS_SRD = 1021;; let _PPC_INS_SRDI = 1022;; let _PPC_INS_SRW = 1023;; let _PPC_INS_SRWI = 1024;; let _PPC_INS_STB = 1025;; let _PPC_INS_STBCIX = 1026;; let _PPC_INS_STBCX = 1027;; let _PPC_INS_STBEPX = 1028;; let _PPC_INS_STBU = 1029;; let _PPC_INS_STBUX = 1030;; let _PPC_INS_STBX = 1031;; let _PPC_INS_STD = 1032;; let _PPC_INS_STDAT = 1033;; let _PPC_INS_STDBRX = 1034;; let _PPC_INS_STDCIX = 1035;; let _PPC_INS_STDCX = 1036;; let _PPC_INS_STDU = 1037;; let _PPC_INS_STDUX = 1038;; let _PPC_INS_STDX = 1039;; let _PPC_INS_STFD = 1040;; let _PPC_INS_STFDEPX = 1041;; let _PPC_INS_STFDU = 1042;; let _PPC_INS_STFDUX = 1043;; let _PPC_INS_STFDX = 1044;; let _PPC_INS_STFIWX = 1045;; let _PPC_INS_STFS = 1046;; let _PPC_INS_STFSU = 1047;; let _PPC_INS_STFSUX = 1048;; let _PPC_INS_STFSX = 1049;; let _PPC_INS_STH = 1050;; let _PPC_INS_STHBRX = 1051;; let _PPC_INS_STHCIX = 1052;; let _PPC_INS_STHCX = 1053;; let _PPC_INS_STHEPX = 1054;; let _PPC_INS_STHU = 1055;; let _PPC_INS_STHUX = 1056;; let _PPC_INS_STHX = 1057;; let _PPC_INS_STMW = 1058;; let _PPC_INS_STOP = 1059;; let _PPC_INS_STSWI = 1060;; let _PPC_INS_STVEBX = 1061;; let _PPC_INS_STVEHX = 1062;; let _PPC_INS_STVEWX = 1063;; let _PPC_INS_STVX = 1064;; let _PPC_INS_STVXL = 1065;; let _PPC_INS_STW = 1066;; let _PPC_INS_STWAT = 1067;; let _PPC_INS_STWBRX = 1068;; let _PPC_INS_STWCIX = 1069;; let _PPC_INS_STWCX = 1070;; let _PPC_INS_STWEPX = 1071;; let _PPC_INS_STWU = 1072;; let _PPC_INS_STWUX = 1073;; let _PPC_INS_STWX = 1074;; let _PPC_INS_STXSD = 1075;; let _PPC_INS_STXSDX = 1076;; let _PPC_INS_STXSIBX = 1077;; let _PPC_INS_STXSIHX = 1078;; let _PPC_INS_STXSIWX = 1079;; let _PPC_INS_STXSSP = 1080;; let _PPC_INS_STXSSPX = 1081;; let _PPC_INS_STXV = 1082;; let _PPC_INS_STXVB16X = 1083;; let _PPC_INS_STXVD2X = 1084;; let _PPC_INS_STXVH8X = 1085;; let _PPC_INS_STXVL = 1086;; let _PPC_INS_STXVLL = 1087;; let _PPC_INS_STXVW4X = 1088;; let _PPC_INS_STXVX = 1089;; let _PPC_INS_SUB = 1090;; let _PPC_INS_SUBC = 1091;; let _PPC_INS_SUBF = 1092;; let _PPC_INS_SUBFC = 1093;; let _PPC_INS_SUBFE = 1094;; let _PPC_INS_SUBFIC = 1095;; let _PPC_INS_SUBFME = 1096;; let _PPC_INS_SUBFZE = 1097;; let _PPC_INS_SUBI = 1098;; let _PPC_INS_SUBIC = 1099;; let _PPC_INS_SUBIS = 1100;; let _PPC_INS_SUBPCIS = 1101;; let _PPC_INS_SYNC = 1102;; let _PPC_INS_TABORT = 1103;; let _PPC_INS_TABORTDC = 1104;; let _PPC_INS_TABORTDCI = 1105;; let _PPC_INS_TABORTWC = 1106;; let _PPC_INS_TABORTWCI = 1107;; let _PPC_INS_TBEGIN = 1108;; let _PPC_INS_TCHECK = 1109;; let _PPC_INS_TD = 1110;; let _PPC_INS_TDEQ = 1111;; let _PPC_INS_TDEQI = 1112;; let _PPC_INS_TDGE = 1113;; let _PPC_INS_TDGEI = 1114;; let _PPC_INS_TDGT = 1115;; let _PPC_INS_TDGTI = 1116;; let _PPC_INS_TDI = 1117;; let _PPC_INS_TDLE = 1118;; let _PPC_INS_TDLEI = 1119;; let _PPC_INS_TDLGE = 1120;; let _PPC_INS_TDLGEI = 1121;; let _PPC_INS_TDLGT = 1122;; let _PPC_INS_TDLGTI = 1123;; let _PPC_INS_TDLLE = 1124;; let _PPC_INS_TDLLEI = 1125;; let _PPC_INS_TDLLT = 1126;; let _PPC_INS_TDLLTI = 1127;; let _PPC_INS_TDLNG = 1128;; let _PPC_INS_TDLNGI = 1129;; let _PPC_INS_TDLNL = 1130;; let _PPC_INS_TDLNLI = 1131;; let _PPC_INS_TDLT = 1132;; let _PPC_INS_TDLTI = 1133;; let _PPC_INS_TDNE = 1134;; let _PPC_INS_TDNEI = 1135;; let _PPC_INS_TDNG = 1136;; let _PPC_INS_TDNGI = 1137;; let _PPC_INS_TDNL = 1138;; let _PPC_INS_TDNLI = 1139;; let _PPC_INS_TDU = 1140;; let _PPC_INS_TDUI = 1141;; let _PPC_INS_TEND = 1142;; let _PPC_INS_TLBIA = 1143;; let _PPC_INS_TLBIE = 1144;; let _PPC_INS_TLBIEL = 1145;; let _PPC_INS_TLBIVAX = 1146;; let _PPC_INS_TLBLD = 1147;; let _PPC_INS_TLBLI = 1148;; let _PPC_INS_TLBRE = 1149;; let _PPC_INS_TLBREHI = 1150;; let _PPC_INS_TLBRELO = 1151;; let _PPC_INS_TLBSX = 1152;; let _PPC_INS_TLBSYNC = 1153;; let _PPC_INS_TLBWE = 1154;; let _PPC_INS_TLBWEHI = 1155;; let _PPC_INS_TLBWELO = 1156;; let _PPC_INS_TRAP = 1157;; let _PPC_INS_TRECHKPT = 1158;; let _PPC_INS_TRECLAIM = 1159;; let _PPC_INS_TSR = 1160;; let _PPC_INS_TW = 1161;; let _PPC_INS_TWEQ = 1162;; let _PPC_INS_TWEQI = 1163;; let _PPC_INS_TWGE = 1164;; let _PPC_INS_TWGEI = 1165;; let _PPC_INS_TWGT = 1166;; let _PPC_INS_TWGTI = 1167;; let _PPC_INS_TWI = 1168;; let _PPC_INS_TWLE = 1169;; let _PPC_INS_TWLEI = 1170;; let _PPC_INS_TWLGE = 1171;; let _PPC_INS_TWLGEI = 1172;; let _PPC_INS_TWLGT = 1173;; let _PPC_INS_TWLGTI = 1174;; let _PPC_INS_TWLLE = 1175;; let _PPC_INS_TWLLEI = 1176;; let _PPC_INS_TWLLT = 1177;; let _PPC_INS_TWLLTI = 1178;; let _PPC_INS_TWLNG = 1179;; let _PPC_INS_TWLNGI = 1180;; let _PPC_INS_TWLNL = 1181;; let _PPC_INS_TWLNLI = 1182;; let _PPC_INS_TWLT = 1183;; let _PPC_INS_TWLTI = 1184;; let _PPC_INS_TWNE = 1185;; let _PPC_INS_TWNEI = 1186;; let _PPC_INS_TWNG = 1187;; let _PPC_INS_TWNGI = 1188;; let _PPC_INS_TWNL = 1189;; let _PPC_INS_TWNLI = 1190;; let _PPC_INS_TWU = 1191;; let _PPC_INS_TWUI = 1192;; let _PPC_INS_VABSDUB = 1193;; let _PPC_INS_VABSDUH = 1194;; let _PPC_INS_VABSDUW = 1195;; let _PPC_INS_VADDCUQ = 1196;; let _PPC_INS_VADDCUW = 1197;; let _PPC_INS_VADDECUQ = 1198;; let _PPC_INS_VADDEUQM = 1199;; let _PPC_INS_VADDFP = 1200;; let _PPC_INS_VADDSBS = 1201;; let _PPC_INS_VADDSHS = 1202;; let _PPC_INS_VADDSWS = 1203;; let _PPC_INS_VADDUBM = 1204;; let _PPC_INS_VADDUBS = 1205;; let _PPC_INS_VADDUDM = 1206;; let _PPC_INS_VADDUHM = 1207;; let _PPC_INS_VADDUHS = 1208;; let _PPC_INS_VADDUQM = 1209;; let _PPC_INS_VADDUWM = 1210;; let _PPC_INS_VADDUWS = 1211;; let _PPC_INS_VAND = 1212;; let _PPC_INS_VANDC = 1213;; let _PPC_INS_VAVGSB = 1214;; let _PPC_INS_VAVGSH = 1215;; let _PPC_INS_VAVGSW = 1216;; let _PPC_INS_VAVGUB = 1217;; let _PPC_INS_VAVGUH = 1218;; let _PPC_INS_VAVGUW = 1219;; let _PPC_INS_VBPERMD = 1220;; let _PPC_INS_VBPERMQ = 1221;; let _PPC_INS_VCFSX = 1222;; let _PPC_INS_VCFUX = 1223;; let _PPC_INS_VCIPHER = 1224;; let _PPC_INS_VCIPHERLAST = 1225;; let _PPC_INS_VCLZB = 1226;; let _PPC_INS_VCLZD = 1227;; let _PPC_INS_VCLZH = 1228;; let _PPC_INS_VCLZLSBB = 1229;; let _PPC_INS_VCLZW = 1230;; let _PPC_INS_VCMPBFP = 1231;; let _PPC_INS_VCMPEQFP = 1232;; let _PPC_INS_VCMPEQUB = 1233;; let _PPC_INS_VCMPEQUD = 1234;; let _PPC_INS_VCMPEQUH = 1235;; let _PPC_INS_VCMPEQUW = 1236;; let _PPC_INS_VCMPGEFP = 1237;; let _PPC_INS_VCMPGTFP = 1238;; let _PPC_INS_VCMPGTSB = 1239;; let _PPC_INS_VCMPGTSD = 1240;; let _PPC_INS_VCMPGTSH = 1241;; let _PPC_INS_VCMPGTSW = 1242;; let _PPC_INS_VCMPGTUB = 1243;; let _PPC_INS_VCMPGTUD = 1244;; let _PPC_INS_VCMPGTUH = 1245;; let _PPC_INS_VCMPGTUW = 1246;; let _PPC_INS_VCMPNEB = 1247;; let _PPC_INS_VCMPNEH = 1248;; let _PPC_INS_VCMPNEW = 1249;; let _PPC_INS_VCMPNEZB = 1250;; let _PPC_INS_VCMPNEZH = 1251;; let _PPC_INS_VCMPNEZW = 1252;; let _PPC_INS_VCTSXS = 1253;; let _PPC_INS_VCTUXS = 1254;; let _PPC_INS_VCTZB = 1255;; let _PPC_INS_VCTZD = 1256;; let _PPC_INS_VCTZH = 1257;; let _PPC_INS_VCTZLSBB = 1258;; let _PPC_INS_VCTZW = 1259;; let _PPC_INS_VEQV = 1260;; let _PPC_INS_VEXPTEFP = 1261;; let _PPC_INS_VEXTRACTD = 1262;; let _PPC_INS_VEXTRACTUB = 1263;; let _PPC_INS_VEXTRACTUH = 1264;; let _PPC_INS_VEXTRACTUW = 1265;; let _PPC_INS_VEXTSB2D = 1266;; let _PPC_INS_VEXTSB2W = 1267;; let _PPC_INS_VEXTSH2D = 1268;; let _PPC_INS_VEXTSH2W = 1269;; let _PPC_INS_VEXTSW2D = 1270;; let _PPC_INS_VEXTUBLX = 1271;; let _PPC_INS_VEXTUBRX = 1272;; let _PPC_INS_VEXTUHLX = 1273;; let _PPC_INS_VEXTUHRX = 1274;; let _PPC_INS_VEXTUWLX = 1275;; let _PPC_INS_VEXTUWRX = 1276;; let _PPC_INS_VGBBD = 1277;; let _PPC_INS_VINSERTB = 1278;; let _PPC_INS_VINSERTD = 1279;; let _PPC_INS_VINSERTH = 1280;; let _PPC_INS_VINSERTW = 1281;; let _PPC_INS_VLOGEFP = 1282;; let _PPC_INS_VMADDFP = 1283;; let _PPC_INS_VMAXFP = 1284;; let _PPC_INS_VMAXSB = 1285;; let _PPC_INS_VMAXSD = 1286;; let _PPC_INS_VMAXSH = 1287;; let _PPC_INS_VMAXSW = 1288;; let _PPC_INS_VMAXUB = 1289;; let _PPC_INS_VMAXUD = 1290;; let _PPC_INS_VMAXUH = 1291;; let _PPC_INS_VMAXUW = 1292;; let _PPC_INS_VMHADDSHS = 1293;; let _PPC_INS_VMHRADDSHS = 1294;; let _PPC_INS_VMINFP = 1295;; let _PPC_INS_VMINSB = 1296;; let _PPC_INS_VMINSD = 1297;; let _PPC_INS_VMINSH = 1298;; let _PPC_INS_VMINSW = 1299;; let _PPC_INS_VMINUB = 1300;; let _PPC_INS_VMINUD = 1301;; let _PPC_INS_VMINUH = 1302;; let _PPC_INS_VMINUW = 1303;; let _PPC_INS_VMLADDUHM = 1304;; let _PPC_INS_VMR = 1305;; let _PPC_INS_VMRGEW = 1306;; let _PPC_INS_VMRGHB = 1307;; let _PPC_INS_VMRGHH = 1308;; let _PPC_INS_VMRGHW = 1309;; let _PPC_INS_VMRGLB = 1310;; let _PPC_INS_VMRGLH = 1311;; let _PPC_INS_VMRGLW = 1312;; let _PPC_INS_VMRGOW = 1313;; let _PPC_INS_VMSUMMBM = 1314;; let _PPC_INS_VMSUMSHM = 1315;; let _PPC_INS_VMSUMSHS = 1316;; let _PPC_INS_VMSUMUBM = 1317;; let _PPC_INS_VMSUMUHM = 1318;; let _PPC_INS_VMSUMUHS = 1319;; let _PPC_INS_VMUL10CUQ = 1320;; let _PPC_INS_VMUL10ECUQ = 1321;; let _PPC_INS_VMUL10EUQ = 1322;; let _PPC_INS_VMUL10UQ = 1323;; let _PPC_INS_VMULESB = 1324;; let _PPC_INS_VMULESH = 1325;; let _PPC_INS_VMULESW = 1326;; let _PPC_INS_VMULEUB = 1327;; let _PPC_INS_VMULEUH = 1328;; let _PPC_INS_VMULEUW = 1329;; let _PPC_INS_VMULOSB = 1330;; let _PPC_INS_VMULOSH = 1331;; let _PPC_INS_VMULOSW = 1332;; let _PPC_INS_VMULOUB = 1333;; let _PPC_INS_VMULOUH = 1334;; let _PPC_INS_VMULOUW = 1335;; let _PPC_INS_VMULUWM = 1336;; let _PPC_INS_VNAND = 1337;; let _PPC_INS_VNCIPHER = 1338;; let _PPC_INS_VNCIPHERLAST = 1339;; let _PPC_INS_VNEGD = 1340;; let _PPC_INS_VNEGW = 1341;; let _PPC_INS_VNMSUBFP = 1342;; let _PPC_INS_VNOR = 1343;; let _PPC_INS_VNOT = 1344;; let _PPC_INS_VOR = 1345;; let _PPC_INS_VORC = 1346;; let _PPC_INS_VPERM = 1347;; let _PPC_INS_VPERMR = 1348;; let _PPC_INS_VPERMXOR = 1349;; let _PPC_INS_VPKPX = 1350;; let _PPC_INS_VPKSDSS = 1351;; let _PPC_INS_VPKSDUS = 1352;; let _PPC_INS_VPKSHSS = 1353;; let _PPC_INS_VPKSHUS = 1354;; let _PPC_INS_VPKSWSS = 1355;; let _PPC_INS_VPKSWUS = 1356;; let _PPC_INS_VPKUDUM = 1357;; let _PPC_INS_VPKUDUS = 1358;; let _PPC_INS_VPKUHUM = 1359;; let _PPC_INS_VPKUHUS = 1360;; let _PPC_INS_VPKUWUM = 1361;; let _PPC_INS_VPKUWUS = 1362;; let _PPC_INS_VPMSUMB = 1363;; let _PPC_INS_VPMSUMD = 1364;; let _PPC_INS_VPMSUMH = 1365;; let _PPC_INS_VPMSUMW = 1366;; let _PPC_INS_VPOPCNTB = 1367;; let _PPC_INS_VPOPCNTD = 1368;; let _PPC_INS_VPOPCNTH = 1369;; let _PPC_INS_VPOPCNTW = 1370;; let _PPC_INS_VPRTYBD = 1371;; let _PPC_INS_VPRTYBQ = 1372;; let _PPC_INS_VPRTYBW = 1373;; let _PPC_INS_VREFP = 1374;; let _PPC_INS_VRFIM = 1375;; let _PPC_INS_VRFIN = 1376;; let _PPC_INS_VRFIP = 1377;; let _PPC_INS_VRFIZ = 1378;; let _PPC_INS_VRLB = 1379;; let _PPC_INS_VRLD = 1380;; let _PPC_INS_VRLDMI = 1381;; let _PPC_INS_VRLDNM = 1382;; let _PPC_INS_VRLH = 1383;; let _PPC_INS_VRLW = 1384;; let _PPC_INS_VRLWMI = 1385;; let _PPC_INS_VRLWNM = 1386;; let _PPC_INS_VRSQRTEFP = 1387;; let _PPC_INS_VSBOX = 1388;; let _PPC_INS_VSEL = 1389;; let _PPC_INS_VSHASIGMAD = 1390;; let _PPC_INS_VSHASIGMAW = 1391;; let _PPC_INS_VSL = 1392;; let _PPC_INS_VSLB = 1393;; let _PPC_INS_VSLD = 1394;; let _PPC_INS_VSLDOI = 1395;; let _PPC_INS_VSLH = 1396;; let _PPC_INS_VSLO = 1397;; let _PPC_INS_VSLV = 1398;; let _PPC_INS_VSLW = 1399;; let _PPC_INS_VSPLTB = 1400;; let _PPC_INS_VSPLTH = 1401;; let _PPC_INS_VSPLTISB = 1402;; let _PPC_INS_VSPLTISH = 1403;; let _PPC_INS_VSPLTISW = 1404;; let _PPC_INS_VSPLTW = 1405;; let _PPC_INS_VSR = 1406;; let _PPC_INS_VSRAB = 1407;; let _PPC_INS_VSRAD = 1408;; let _PPC_INS_VSRAH = 1409;; let _PPC_INS_VSRAW = 1410;; let _PPC_INS_VSRB = 1411;; let _PPC_INS_VSRD = 1412;; let _PPC_INS_VSRH = 1413;; let _PPC_INS_VSRO = 1414;; let _PPC_INS_VSRV = 1415;; let _PPC_INS_VSRW = 1416;; let _PPC_INS_VSUBCUQ = 1417;; let _PPC_INS_VSUBCUW = 1418;; let _PPC_INS_VSUBECUQ = 1419;; let _PPC_INS_VSUBEUQM = 1420;; let _PPC_INS_VSUBFP = 1421;; let _PPC_INS_VSUBSBS = 1422;; let _PPC_INS_VSUBSHS = 1423;; let _PPC_INS_VSUBSWS = 1424;; let _PPC_INS_VSUBUBM = 1425;; let _PPC_INS_VSUBUBS = 1426;; let _PPC_INS_VSUBUDM = 1427;; let _PPC_INS_VSUBUHM = 1428;; let _PPC_INS_VSUBUHS = 1429;; let _PPC_INS_VSUBUQM = 1430;; let _PPC_INS_VSUBUWM = 1431;; let _PPC_INS_VSUBUWS = 1432;; let _PPC_INS_VSUM2SWS = 1433;; let _PPC_INS_VSUM4SBS = 1434;; let _PPC_INS_VSUM4SHS = 1435;; let _PPC_INS_VSUM4UBS = 1436;; let _PPC_INS_VSUMSWS = 1437;; let _PPC_INS_VUPKHPX = 1438;; let _PPC_INS_VUPKHSB = 1439;; let _PPC_INS_VUPKHSH = 1440;; let _PPC_INS_VUPKHSW = 1441;; let _PPC_INS_VUPKLPX = 1442;; let _PPC_INS_VUPKLSB = 1443;; let _PPC_INS_VUPKLSH = 1444;; let _PPC_INS_VUPKLSW = 1445;; let _PPC_INS_VXOR = 1446;; let _PPC_INS_WAIT = 1447;; let _PPC_INS_WAITIMPL = 1448;; let _PPC_INS_WAITRSV = 1449;; let _PPC_INS_WRTEE = 1450;; let _PPC_INS_WRTEEI = 1451;; let _PPC_INS_XNOP = 1452;; let _PPC_INS_XOR = 1453;; let _PPC_INS_XORI = 1454;; let _PPC_INS_XORIS = 1455;; let _PPC_INS_XSABSDP = 1456;; let _PPC_INS_XSABSQP = 1457;; let _PPC_INS_XSADDDP = 1458;; let _PPC_INS_XSADDQP = 1459;; let _PPC_INS_XSADDQPO = 1460;; let _PPC_INS_XSADDSP = 1461;; let _PPC_INS_XSCMPEQDP = 1462;; let _PPC_INS_XSCMPEXPDP = 1463;; let _PPC_INS_XSCMPEXPQP = 1464;; let _PPC_INS_XSCMPGEDP = 1465;; let _PPC_INS_XSCMPGTDP = 1466;; let _PPC_INS_XSCMPODP = 1467;; let _PPC_INS_XSCMPOQP = 1468;; let _PPC_INS_XSCMPUDP = 1469;; let _PPC_INS_XSCMPUQP = 1470;; let _PPC_INS_XSCPSGNDP = 1471;; let _PPC_INS_XSCPSGNQP = 1472;; let _PPC_INS_XSCVDPHP = 1473;; let _PPC_INS_XSCVDPQP = 1474;; let _PPC_INS_XSCVDPSP = 1475;; let _PPC_INS_XSCVDPSPN = 1476;; let _PPC_INS_XSCVDPSXDS = 1477;; let _PPC_INS_XSCVDPSXWS = 1478;; let _PPC_INS_XSCVDPUXDS = 1479;; let _PPC_INS_XSCVDPUXWS = 1480;; let _PPC_INS_XSCVHPDP = 1481;; let _PPC_INS_XSCVQPDP = 1482;; let _PPC_INS_XSCVQPDPO = 1483;; let _PPC_INS_XSCVQPSDZ = 1484;; let _PPC_INS_XSCVQPSWZ = 1485;; let _PPC_INS_XSCVQPUDZ = 1486;; let _PPC_INS_XSCVQPUWZ = 1487;; let _PPC_INS_XSCVSDQP = 1488;; let _PPC_INS_XSCVSPDP = 1489;; let _PPC_INS_XSCVSPDPN = 1490;; let _PPC_INS_XSCVSXDDP = 1491;; let _PPC_INS_XSCVSXDSP = 1492;; let _PPC_INS_XSCVUDQP = 1493;; let _PPC_INS_XSCVUXDDP = 1494;; let _PPC_INS_XSCVUXDSP = 1495;; let _PPC_INS_XSDIVDP = 1496;; let _PPC_INS_XSDIVQP = 1497;; let _PPC_INS_XSDIVQPO = 1498;; let _PPC_INS_XSDIVSP = 1499;; let _PPC_INS_XSIEXPDP = 1500;; let _PPC_INS_XSIEXPQP = 1501;; let _PPC_INS_XSMADDADP = 1502;; let _PPC_INS_XSMADDASP = 1503;; let _PPC_INS_XSMADDMDP = 1504;; let _PPC_INS_XSMADDMSP = 1505;; let _PPC_INS_XSMADDQP = 1506;; let _PPC_INS_XSMADDQPO = 1507;; let _PPC_INS_XSMAXCDP = 1508;; let _PPC_INS_XSMAXDP = 1509;; let _PPC_INS_XSMAXJDP = 1510;; let _PPC_INS_XSMINCDP = 1511;; let _PPC_INS_XSMINDP = 1512;; let _PPC_INS_XSMINJDP = 1513;; let _PPC_INS_XSMSUBADP = 1514;; let _PPC_INS_XSMSUBASP = 1515;; let _PPC_INS_XSMSUBMDP = 1516;; let _PPC_INS_XSMSUBMSP = 1517;; let _PPC_INS_XSMSUBQP = 1518;; let _PPC_INS_XSMSUBQPO = 1519;; let _PPC_INS_XSMULDP = 1520;; let _PPC_INS_XSMULQP = 1521;; let _PPC_INS_XSMULQPO = 1522;; let _PPC_INS_XSMULSP = 1523;; let _PPC_INS_XSNABSDP = 1524;; let _PPC_INS_XSNABSQP = 1525;; let _PPC_INS_XSNEGDP = 1526;; let _PPC_INS_XSNEGQP = 1527;; let _PPC_INS_XSNMADDADP = 1528;; let _PPC_INS_XSNMADDASP = 1529;; let _PPC_INS_XSNMADDMDP = 1530;; let _PPC_INS_XSNMADDMSP = 1531;; let _PPC_INS_XSNMADDQP = 1532;; let _PPC_INS_XSNMADDQPO = 1533;; let _PPC_INS_XSNMSUBADP = 1534;; let _PPC_INS_XSNMSUBASP = 1535;; let _PPC_INS_XSNMSUBMDP = 1536;; let _PPC_INS_XSNMSUBMSP = 1537;; let _PPC_INS_XSNMSUBQP = 1538;; let _PPC_INS_XSNMSUBQPO = 1539;; let _PPC_INS_XSRDPI = 1540;; let _PPC_INS_XSRDPIC = 1541;; let _PPC_INS_XSRDPIM = 1542;; let _PPC_INS_XSRDPIP = 1543;; let _PPC_INS_XSRDPIZ = 1544;; let _PPC_INS_XSREDP = 1545;; let _PPC_INS_XSRESP = 1546;; let _PPC_INS_XSRQPI = 1547;; let _PPC_INS_XSRQPIX = 1548;; let _PPC_INS_XSRQPXP = 1549;; let _PPC_INS_XSRSP = 1550;; let _PPC_INS_XSRSQRTEDP = 1551;; let _PPC_INS_XSRSQRTESP = 1552;; let _PPC_INS_XSSQRTDP = 1553;; let _PPC_INS_XSSQRTQP = 1554;; let _PPC_INS_XSSQRTQPO = 1555;; let _PPC_INS_XSSQRTSP = 1556;; let _PPC_INS_XSSUBDP = 1557;; let _PPC_INS_XSSUBQP = 1558;; let _PPC_INS_XSSUBQPO = 1559;; let _PPC_INS_XSSUBSP = 1560;; let _PPC_INS_XSTDIVDP = 1561;; let _PPC_INS_XSTSQRTDP = 1562;; let _PPC_INS_XSTSTDCDP = 1563;; let _PPC_INS_XSTSTDCQP = 1564;; let _PPC_INS_XSTSTDCSP = 1565;; let _PPC_INS_XSXEXPDP = 1566;; let _PPC_INS_XSXEXPQP = 1567;; let _PPC_INS_XSXSIGDP = 1568;; let _PPC_INS_XSXSIGQP = 1569;; let _PPC_INS_XVABSDP = 1570;; let _PPC_INS_XVABSSP = 1571;; let _PPC_INS_XVADDDP = 1572;; let _PPC_INS_XVADDSP = 1573;; let _PPC_INS_XVCMPEQDP = 1574;; let _PPC_INS_XVCMPEQSP = 1575;; let _PPC_INS_XVCMPGEDP = 1576;; let _PPC_INS_XVCMPGESP = 1577;; let _PPC_INS_XVCMPGTDP = 1578;; let _PPC_INS_XVCMPGTSP = 1579;; let _PPC_INS_XVCPSGNDP = 1580;; let _PPC_INS_XVCPSGNSP = 1581;; let _PPC_INS_XVCVDPSP = 1582;; let _PPC_INS_XVCVDPSXDS = 1583;; let _PPC_INS_XVCVDPSXWS = 1584;; let _PPC_INS_XVCVDPUXDS = 1585;; let _PPC_INS_XVCVDPUXWS = 1586;; let _PPC_INS_XVCVHPSP = 1587;; let _PPC_INS_XVCVSPDP = 1588;; let _PPC_INS_XVCVSPHP = 1589;; let _PPC_INS_XVCVSPSXDS = 1590;; let _PPC_INS_XVCVSPSXWS = 1591;; let _PPC_INS_XVCVSPUXDS = 1592;; let _PPC_INS_XVCVSPUXWS = 1593;; let _PPC_INS_XVCVSXDDP = 1594;; let _PPC_INS_XVCVSXDSP = 1595;; let _PPC_INS_XVCVSXWDP = 1596;; let _PPC_INS_XVCVSXWSP = 1597;; let _PPC_INS_XVCVUXDDP = 1598;; let _PPC_INS_XVCVUXDSP = 1599;; let _PPC_INS_XVCVUXWDP = 1600;; let _PPC_INS_XVCVUXWSP = 1601;; let _PPC_INS_XVDIVDP = 1602;; let _PPC_INS_XVDIVSP = 1603;; let _PPC_INS_XVIEXPDP = 1604;; let _PPC_INS_XVIEXPSP = 1605;; let _PPC_INS_XVMADDADP = 1606;; let _PPC_INS_XVMADDASP = 1607;; let _PPC_INS_XVMADDMDP = 1608;; let _PPC_INS_XVMADDMSP = 1609;; let _PPC_INS_XVMAXDP = 1610;; let _PPC_INS_XVMAXSP = 1611;; let _PPC_INS_XVMINDP = 1612;; let _PPC_INS_XVMINSP = 1613;; let _PPC_INS_XVMOVDP = 1614;; let _PPC_INS_XVMOVSP = 1615;; let _PPC_INS_XVMSUBADP = 1616;; let _PPC_INS_XVMSUBASP = 1617;; let _PPC_INS_XVMSUBMDP = 1618;; let _PPC_INS_XVMSUBMSP = 1619;; let _PPC_INS_XVMULDP = 1620;; let _PPC_INS_XVMULSP = 1621;; let _PPC_INS_XVNABSDP = 1622;; let _PPC_INS_XVNABSSP = 1623;; let _PPC_INS_XVNEGDP = 1624;; let _PPC_INS_XVNEGSP = 1625;; let _PPC_INS_XVNMADDADP = 1626;; let _PPC_INS_XVNMADDASP = 1627;; let _PPC_INS_XVNMADDMDP = 1628;; let _PPC_INS_XVNMADDMSP = 1629;; let _PPC_INS_XVNMSUBADP = 1630;; let _PPC_INS_XVNMSUBASP = 1631;; let _PPC_INS_XVNMSUBMDP = 1632;; let _PPC_INS_XVNMSUBMSP = 1633;; let _PPC_INS_XVRDPI = 1634;; let _PPC_INS_XVRDPIC = 1635;; let _PPC_INS_XVRDPIM = 1636;; let _PPC_INS_XVRDPIP = 1637;; let _PPC_INS_XVRDPIZ = 1638;; let _PPC_INS_XVREDP = 1639;; let _PPC_INS_XVRESP = 1640;; let _PPC_INS_XVRSPI = 1641;; let _PPC_INS_XVRSPIC = 1642;; let _PPC_INS_XVRSPIM = 1643;; let _PPC_INS_XVRSPIP = 1644;; let _PPC_INS_XVRSPIZ = 1645;; let _PPC_INS_XVRSQRTEDP = 1646;; let _PPC_INS_XVRSQRTESP = 1647;; let _PPC_INS_XVSQRTDP = 1648;; let _PPC_INS_XVSQRTSP = 1649;; let _PPC_INS_XVSUBDP = 1650;; let _PPC_INS_XVSUBSP = 1651;; let _PPC_INS_XVTDIVDP = 1652;; let _PPC_INS_XVTDIVSP = 1653;; let _PPC_INS_XVTSQRTDP = 1654;; let _PPC_INS_XVTSQRTSP = 1655;; let _PPC_INS_XVTSTDCDP = 1656;; let _PPC_INS_XVTSTDCSP = 1657;; let _PPC_INS_XVXEXPDP = 1658;; let _PPC_INS_XVXEXPSP = 1659;; let _PPC_INS_XVXSIGDP = 1660;; let _PPC_INS_XVXSIGSP = 1661;; let _PPC_INS_XXBRD = 1662;; let _PPC_INS_XXBRH = 1663;; let _PPC_INS_XXBRQ = 1664;; let _PPC_INS_XXBRW = 1665;; let _PPC_INS_XXEXTRACTUW = 1666;; let _PPC_INS_XXINSERTW = 1667;; let _PPC_INS_XXLAND = 1668;; let _PPC_INS_XXLANDC = 1669;; let _PPC_INS_XXLEQV = 1670;; let _PPC_INS_XXLNAND = 1671;; let _PPC_INS_XXLNOR = 1672;; let _PPC_INS_XXLOR = 1673;; let _PPC_INS_XXLORC = 1674;; let _PPC_INS_XXLXOR = 1675;; let _PPC_INS_XXMRGHD = 1676;; let _PPC_INS_XXMRGHW = 1677;; let _PPC_INS_XXMRGLD = 1678;; let _PPC_INS_XXMRGLW = 1679;; let _PPC_INS_XXPERM = 1680;; let _PPC_INS_XXPERMDI = 1681;; let _PPC_INS_XXPERMR = 1682;; let _PPC_INS_XXSEL = 1683;; let _PPC_INS_XXSLDWI = 1684;; let _PPC_INS_XXSPLTD = 1685;; let _PPC_INS_XXSPLTIB = 1686;; let _PPC_INS_XXSPLTW = 1687;; let _PPC_INS_XXSWAPD = 1688;; let _PPC_INS_ENDING = 1689;; let _PPC_GRP_INVALID = 0;; let _PPC_GRP_JUMP = 1;; let _PPC_GRP_ALTIVEC = 128;; let _PPC_GRP_MODE32 = 129;; let _PPC_GRP_MODE64 = 130;; let _PPC_GRP_BOOKE = 131;; let _PPC_GRP_NOTBOOKE = 132;; let _PPC_GRP_SPE = 133;; let _PPC_GRP_VSX = 134;; let _PPC_GRP_E500 = 135;; let _PPC_GRP_PPC4XX = 136;; let _PPC_GRP_PPC6XX = 137;; let _PPC_GRP_ICBT = 138;; let _PPC_GRP_P8ALTIVEC = 139;; let _PPC_GRP_P8VECTOR = 140;; let _PPC_GRP_QPX = 141;; let _PPC_GRP_ENDING = 142;; capstone-sys-0.15.0/capstone/bindings/ocaml/sparc.ml000064400000000000000000000006440072674642500205410ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Sparc_const type sparc_op_mem = { base: int; index: int; disp: int; } type sparc_op_value = | SPARC_OP_INVALID of int | SPARC_OP_REG of int | SPARC_OP_IMM of int | SPARC_OP_MEM of sparc_op_mem type sparc_op = { value: sparc_op_value; } type cs_sparc = { cc: int; hint: int; operands: sparc_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/sparc_const.ml000064400000000000000000000276700072674642500217570ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.ml] *) let _SPARC_CC_INVALID = 0;; let _SPARC_CC_ICC_A = 8+256;; let _SPARC_CC_ICC_N = 0+256;; let _SPARC_CC_ICC_NE = 9+256;; let _SPARC_CC_ICC_E = 1+256;; let _SPARC_CC_ICC_G = 10+256;; let _SPARC_CC_ICC_LE = 2+256;; let _SPARC_CC_ICC_GE = 11+256;; let _SPARC_CC_ICC_L = 3+256;; let _SPARC_CC_ICC_GU = 12+256;; let _SPARC_CC_ICC_LEU = 4+256;; let _SPARC_CC_ICC_CC = 13+256;; let _SPARC_CC_ICC_CS = 5+256;; let _SPARC_CC_ICC_POS = 14+256;; let _SPARC_CC_ICC_NEG = 6+256;; let _SPARC_CC_ICC_VC = 15+256;; let _SPARC_CC_ICC_VS = 7+256;; let _SPARC_CC_FCC_A = 8+16+256;; let _SPARC_CC_FCC_N = 0+16+256;; let _SPARC_CC_FCC_U = 7+16+256;; let _SPARC_CC_FCC_G = 6+16+256;; let _SPARC_CC_FCC_UG = 5+16+256;; let _SPARC_CC_FCC_L = 4+16+256;; let _SPARC_CC_FCC_UL = 3+16+256;; let _SPARC_CC_FCC_LG = 2+16+256;; let _SPARC_CC_FCC_NE = 1+16+256;; let _SPARC_CC_FCC_E = 9+16+256;; let _SPARC_CC_FCC_UE = 10+16+256;; let _SPARC_CC_FCC_GE = 11+16+256;; let _SPARC_CC_FCC_UGE = 12+16+256;; let _SPARC_CC_FCC_LE = 13+16+256;; let _SPARC_CC_FCC_ULE = 14+16+256;; let _SPARC_CC_FCC_O = 15+16+256;; let _SPARC_HINT_INVALID = 0;; let _SPARC_HINT_A = 1 lsl 0;; let _SPARC_HINT_PT = 1 lsl 1;; let _SPARC_HINT_PN = 1 lsl 2;; let _SPARC_OP_INVALID = 0;; let _SPARC_OP_REG = 1;; let _SPARC_OP_IMM = 2;; let _SPARC_OP_MEM = 3;; let _SPARC_REG_INVALID = 0;; let _SPARC_REG_F0 = 1;; let _SPARC_REG_F1 = 2;; let _SPARC_REG_F2 = 3;; let _SPARC_REG_F3 = 4;; let _SPARC_REG_F4 = 5;; let _SPARC_REG_F5 = 6;; let _SPARC_REG_F6 = 7;; let _SPARC_REG_F7 = 8;; let _SPARC_REG_F8 = 9;; let _SPARC_REG_F9 = 10;; let _SPARC_REG_F10 = 11;; let _SPARC_REG_F11 = 12;; let _SPARC_REG_F12 = 13;; let _SPARC_REG_F13 = 14;; let _SPARC_REG_F14 = 15;; let _SPARC_REG_F15 = 16;; let _SPARC_REG_F16 = 17;; let _SPARC_REG_F17 = 18;; let _SPARC_REG_F18 = 19;; let _SPARC_REG_F19 = 20;; let _SPARC_REG_F20 = 21;; let _SPARC_REG_F21 = 22;; let _SPARC_REG_F22 = 23;; let _SPARC_REG_F23 = 24;; let _SPARC_REG_F24 = 25;; let _SPARC_REG_F25 = 26;; let _SPARC_REG_F26 = 27;; let _SPARC_REG_F27 = 28;; let _SPARC_REG_F28 = 29;; let _SPARC_REG_F29 = 30;; let _SPARC_REG_F30 = 31;; let _SPARC_REG_F31 = 32;; let _SPARC_REG_F32 = 33;; let _SPARC_REG_F34 = 34;; let _SPARC_REG_F36 = 35;; let _SPARC_REG_F38 = 36;; let _SPARC_REG_F40 = 37;; let _SPARC_REG_F42 = 38;; let _SPARC_REG_F44 = 39;; let _SPARC_REG_F46 = 40;; let _SPARC_REG_F48 = 41;; let _SPARC_REG_F50 = 42;; let _SPARC_REG_F52 = 43;; let _SPARC_REG_F54 = 44;; let _SPARC_REG_F56 = 45;; let _SPARC_REG_F58 = 46;; let _SPARC_REG_F60 = 47;; let _SPARC_REG_F62 = 48;; let _SPARC_REG_FCC0 = 49;; let _SPARC_REG_FCC1 = 50;; let _SPARC_REG_FCC2 = 51;; let _SPARC_REG_FCC3 = 52;; let _SPARC_REG_FP = 53;; let _SPARC_REG_G0 = 54;; let _SPARC_REG_G1 = 55;; let _SPARC_REG_G2 = 56;; let _SPARC_REG_G3 = 57;; let _SPARC_REG_G4 = 58;; let _SPARC_REG_G5 = 59;; let _SPARC_REG_G6 = 60;; let _SPARC_REG_G7 = 61;; let _SPARC_REG_I0 = 62;; let _SPARC_REG_I1 = 63;; let _SPARC_REG_I2 = 64;; let _SPARC_REG_I3 = 65;; let _SPARC_REG_I4 = 66;; let _SPARC_REG_I5 = 67;; let _SPARC_REG_I7 = 68;; let _SPARC_REG_ICC = 69;; let _SPARC_REG_L0 = 70;; let _SPARC_REG_L1 = 71;; let _SPARC_REG_L2 = 72;; let _SPARC_REG_L3 = 73;; let _SPARC_REG_L4 = 74;; let _SPARC_REG_L5 = 75;; let _SPARC_REG_L6 = 76;; let _SPARC_REG_L7 = 77;; let _SPARC_REG_O0 = 78;; let _SPARC_REG_O1 = 79;; let _SPARC_REG_O2 = 80;; let _SPARC_REG_O3 = 81;; let _SPARC_REG_O4 = 82;; let _SPARC_REG_O5 = 83;; let _SPARC_REG_O7 = 84;; let _SPARC_REG_SP = 85;; let _SPARC_REG_Y = 86;; let _SPARC_REG_XCC = 87;; let _SPARC_REG_ENDING = 88;; let _SPARC_REG_O6 = _SPARC_REG_SP;; let _SPARC_REG_I6 = _SPARC_REG_FP;; let _SPARC_INS_INVALID = 0;; let _SPARC_INS_ADDCC = 1;; let _SPARC_INS_ADDX = 2;; let _SPARC_INS_ADDXCC = 3;; let _SPARC_INS_ADDXC = 4;; let _SPARC_INS_ADDXCCC = 5;; let _SPARC_INS_ADD = 6;; let _SPARC_INS_ALIGNADDR = 7;; let _SPARC_INS_ALIGNADDRL = 8;; let _SPARC_INS_ANDCC = 9;; let _SPARC_INS_ANDNCC = 10;; let _SPARC_INS_ANDN = 11;; let _SPARC_INS_AND = 12;; let _SPARC_INS_ARRAY16 = 13;; let _SPARC_INS_ARRAY32 = 14;; let _SPARC_INS_ARRAY8 = 15;; let _SPARC_INS_B = 16;; let _SPARC_INS_JMP = 17;; let _SPARC_INS_BMASK = 18;; let _SPARC_INS_FB = 19;; let _SPARC_INS_BRGEZ = 20;; let _SPARC_INS_BRGZ = 21;; let _SPARC_INS_BRLEZ = 22;; let _SPARC_INS_BRLZ = 23;; let _SPARC_INS_BRNZ = 24;; let _SPARC_INS_BRZ = 25;; let _SPARC_INS_BSHUFFLE = 26;; let _SPARC_INS_CALL = 27;; let _SPARC_INS_CASX = 28;; let _SPARC_INS_CAS = 29;; let _SPARC_INS_CMASK16 = 30;; let _SPARC_INS_CMASK32 = 31;; let _SPARC_INS_CMASK8 = 32;; let _SPARC_INS_CMP = 33;; let _SPARC_INS_EDGE16 = 34;; let _SPARC_INS_EDGE16L = 35;; let _SPARC_INS_EDGE16LN = 36;; let _SPARC_INS_EDGE16N = 37;; let _SPARC_INS_EDGE32 = 38;; let _SPARC_INS_EDGE32L = 39;; let _SPARC_INS_EDGE32LN = 40;; let _SPARC_INS_EDGE32N = 41;; let _SPARC_INS_EDGE8 = 42;; let _SPARC_INS_EDGE8L = 43;; let _SPARC_INS_EDGE8LN = 44;; let _SPARC_INS_EDGE8N = 45;; let _SPARC_INS_FABSD = 46;; let _SPARC_INS_FABSQ = 47;; let _SPARC_INS_FABSS = 48;; let _SPARC_INS_FADDD = 49;; let _SPARC_INS_FADDQ = 50;; let _SPARC_INS_FADDS = 51;; let _SPARC_INS_FALIGNDATA = 52;; let _SPARC_INS_FAND = 53;; let _SPARC_INS_FANDNOT1 = 54;; let _SPARC_INS_FANDNOT1S = 55;; let _SPARC_INS_FANDNOT2 = 56;; let _SPARC_INS_FANDNOT2S = 57;; let _SPARC_INS_FANDS = 58;; let _SPARC_INS_FCHKSM16 = 59;; let _SPARC_INS_FCMPD = 60;; let _SPARC_INS_FCMPEQ16 = 61;; let _SPARC_INS_FCMPEQ32 = 62;; let _SPARC_INS_FCMPGT16 = 63;; let _SPARC_INS_FCMPGT32 = 64;; let _SPARC_INS_FCMPLE16 = 65;; let _SPARC_INS_FCMPLE32 = 66;; let _SPARC_INS_FCMPNE16 = 67;; let _SPARC_INS_FCMPNE32 = 68;; let _SPARC_INS_FCMPQ = 69;; let _SPARC_INS_FCMPS = 70;; let _SPARC_INS_FDIVD = 71;; let _SPARC_INS_FDIVQ = 72;; let _SPARC_INS_FDIVS = 73;; let _SPARC_INS_FDMULQ = 74;; let _SPARC_INS_FDTOI = 75;; let _SPARC_INS_FDTOQ = 76;; let _SPARC_INS_FDTOS = 77;; let _SPARC_INS_FDTOX = 78;; let _SPARC_INS_FEXPAND = 79;; let _SPARC_INS_FHADDD = 80;; let _SPARC_INS_FHADDS = 81;; let _SPARC_INS_FHSUBD = 82;; let _SPARC_INS_FHSUBS = 83;; let _SPARC_INS_FITOD = 84;; let _SPARC_INS_FITOQ = 85;; let _SPARC_INS_FITOS = 86;; let _SPARC_INS_FLCMPD = 87;; let _SPARC_INS_FLCMPS = 88;; let _SPARC_INS_FLUSHW = 89;; let _SPARC_INS_FMEAN16 = 90;; let _SPARC_INS_FMOVD = 91;; let _SPARC_INS_FMOVQ = 92;; let _SPARC_INS_FMOVRDGEZ = 93;; let _SPARC_INS_FMOVRQGEZ = 94;; let _SPARC_INS_FMOVRSGEZ = 95;; let _SPARC_INS_FMOVRDGZ = 96;; let _SPARC_INS_FMOVRQGZ = 97;; let _SPARC_INS_FMOVRSGZ = 98;; let _SPARC_INS_FMOVRDLEZ = 99;; let _SPARC_INS_FMOVRQLEZ = 100;; let _SPARC_INS_FMOVRSLEZ = 101;; let _SPARC_INS_FMOVRDLZ = 102;; let _SPARC_INS_FMOVRQLZ = 103;; let _SPARC_INS_FMOVRSLZ = 104;; let _SPARC_INS_FMOVRDNZ = 105;; let _SPARC_INS_FMOVRQNZ = 106;; let _SPARC_INS_FMOVRSNZ = 107;; let _SPARC_INS_FMOVRDZ = 108;; let _SPARC_INS_FMOVRQZ = 109;; let _SPARC_INS_FMOVRSZ = 110;; let _SPARC_INS_FMOVS = 111;; let _SPARC_INS_FMUL8SUX16 = 112;; let _SPARC_INS_FMUL8ULX16 = 113;; let _SPARC_INS_FMUL8X16 = 114;; let _SPARC_INS_FMUL8X16AL = 115;; let _SPARC_INS_FMUL8X16AU = 116;; let _SPARC_INS_FMULD = 117;; let _SPARC_INS_FMULD8SUX16 = 118;; let _SPARC_INS_FMULD8ULX16 = 119;; let _SPARC_INS_FMULQ = 120;; let _SPARC_INS_FMULS = 121;; let _SPARC_INS_FNADDD = 122;; let _SPARC_INS_FNADDS = 123;; let _SPARC_INS_FNAND = 124;; let _SPARC_INS_FNANDS = 125;; let _SPARC_INS_FNEGD = 126;; let _SPARC_INS_FNEGQ = 127;; let _SPARC_INS_FNEGS = 128;; let _SPARC_INS_FNHADDD = 129;; let _SPARC_INS_FNHADDS = 130;; let _SPARC_INS_FNOR = 131;; let _SPARC_INS_FNORS = 132;; let _SPARC_INS_FNOT1 = 133;; let _SPARC_INS_FNOT1S = 134;; let _SPARC_INS_FNOT2 = 135;; let _SPARC_INS_FNOT2S = 136;; let _SPARC_INS_FONE = 137;; let _SPARC_INS_FONES = 138;; let _SPARC_INS_FOR = 139;; let _SPARC_INS_FORNOT1 = 140;; let _SPARC_INS_FORNOT1S = 141;; let _SPARC_INS_FORNOT2 = 142;; let _SPARC_INS_FORNOT2S = 143;; let _SPARC_INS_FORS = 144;; let _SPARC_INS_FPACK16 = 145;; let _SPARC_INS_FPACK32 = 146;; let _SPARC_INS_FPACKFIX = 147;; let _SPARC_INS_FPADD16 = 148;; let _SPARC_INS_FPADD16S = 149;; let _SPARC_INS_FPADD32 = 150;; let _SPARC_INS_FPADD32S = 151;; let _SPARC_INS_FPADD64 = 152;; let _SPARC_INS_FPMERGE = 153;; let _SPARC_INS_FPSUB16 = 154;; let _SPARC_INS_FPSUB16S = 155;; let _SPARC_INS_FPSUB32 = 156;; let _SPARC_INS_FPSUB32S = 157;; let _SPARC_INS_FQTOD = 158;; let _SPARC_INS_FQTOI = 159;; let _SPARC_INS_FQTOS = 160;; let _SPARC_INS_FQTOX = 161;; let _SPARC_INS_FSLAS16 = 162;; let _SPARC_INS_FSLAS32 = 163;; let _SPARC_INS_FSLL16 = 164;; let _SPARC_INS_FSLL32 = 165;; let _SPARC_INS_FSMULD = 166;; let _SPARC_INS_FSQRTD = 167;; let _SPARC_INS_FSQRTQ = 168;; let _SPARC_INS_FSQRTS = 169;; let _SPARC_INS_FSRA16 = 170;; let _SPARC_INS_FSRA32 = 171;; let _SPARC_INS_FSRC1 = 172;; let _SPARC_INS_FSRC1S = 173;; let _SPARC_INS_FSRC2 = 174;; let _SPARC_INS_FSRC2S = 175;; let _SPARC_INS_FSRL16 = 176;; let _SPARC_INS_FSRL32 = 177;; let _SPARC_INS_FSTOD = 178;; let _SPARC_INS_FSTOI = 179;; let _SPARC_INS_FSTOQ = 180;; let _SPARC_INS_FSTOX = 181;; let _SPARC_INS_FSUBD = 182;; let _SPARC_INS_FSUBQ = 183;; let _SPARC_INS_FSUBS = 184;; let _SPARC_INS_FXNOR = 185;; let _SPARC_INS_FXNORS = 186;; let _SPARC_INS_FXOR = 187;; let _SPARC_INS_FXORS = 188;; let _SPARC_INS_FXTOD = 189;; let _SPARC_INS_FXTOQ = 190;; let _SPARC_INS_FXTOS = 191;; let _SPARC_INS_FZERO = 192;; let _SPARC_INS_FZEROS = 193;; let _SPARC_INS_JMPL = 194;; let _SPARC_INS_LDD = 195;; let _SPARC_INS_LD = 196;; let _SPARC_INS_LDQ = 197;; let _SPARC_INS_LDSB = 198;; let _SPARC_INS_LDSH = 199;; let _SPARC_INS_LDSW = 200;; let _SPARC_INS_LDUB = 201;; let _SPARC_INS_LDUH = 202;; let _SPARC_INS_LDX = 203;; let _SPARC_INS_LZCNT = 204;; let _SPARC_INS_MEMBAR = 205;; let _SPARC_INS_MOVDTOX = 206;; let _SPARC_INS_MOV = 207;; let _SPARC_INS_MOVRGEZ = 208;; let _SPARC_INS_MOVRGZ = 209;; let _SPARC_INS_MOVRLEZ = 210;; let _SPARC_INS_MOVRLZ = 211;; let _SPARC_INS_MOVRNZ = 212;; let _SPARC_INS_MOVRZ = 213;; let _SPARC_INS_MOVSTOSW = 214;; let _SPARC_INS_MOVSTOUW = 215;; let _SPARC_INS_MULX = 216;; let _SPARC_INS_NOP = 217;; let _SPARC_INS_ORCC = 218;; let _SPARC_INS_ORNCC = 219;; let _SPARC_INS_ORN = 220;; let _SPARC_INS_OR = 221;; let _SPARC_INS_PDIST = 222;; let _SPARC_INS_PDISTN = 223;; let _SPARC_INS_POPC = 224;; let _SPARC_INS_RD = 225;; let _SPARC_INS_RESTORE = 226;; let _SPARC_INS_RETT = 227;; let _SPARC_INS_SAVE = 228;; let _SPARC_INS_SDIVCC = 229;; let _SPARC_INS_SDIVX = 230;; let _SPARC_INS_SDIV = 231;; let _SPARC_INS_SETHI = 232;; let _SPARC_INS_SHUTDOWN = 233;; let _SPARC_INS_SIAM = 234;; let _SPARC_INS_SLLX = 235;; let _SPARC_INS_SLL = 236;; let _SPARC_INS_SMULCC = 237;; let _SPARC_INS_SMUL = 238;; let _SPARC_INS_SRAX = 239;; let _SPARC_INS_SRA = 240;; let _SPARC_INS_SRLX = 241;; let _SPARC_INS_SRL = 242;; let _SPARC_INS_STBAR = 243;; let _SPARC_INS_STB = 244;; let _SPARC_INS_STD = 245;; let _SPARC_INS_ST = 246;; let _SPARC_INS_STH = 247;; let _SPARC_INS_STQ = 248;; let _SPARC_INS_STX = 249;; let _SPARC_INS_SUBCC = 250;; let _SPARC_INS_SUBX = 251;; let _SPARC_INS_SUBXCC = 252;; let _SPARC_INS_SUB = 253;; let _SPARC_INS_SWAP = 254;; let _SPARC_INS_TADDCCTV = 255;; let _SPARC_INS_TADDCC = 256;; let _SPARC_INS_T = 257;; let _SPARC_INS_TSUBCCTV = 258;; let _SPARC_INS_TSUBCC = 259;; let _SPARC_INS_UDIVCC = 260;; let _SPARC_INS_UDIVX = 261;; let _SPARC_INS_UDIV = 262;; let _SPARC_INS_UMULCC = 263;; let _SPARC_INS_UMULXHI = 264;; let _SPARC_INS_UMUL = 265;; let _SPARC_INS_UNIMP = 266;; let _SPARC_INS_FCMPED = 267;; let _SPARC_INS_FCMPEQ = 268;; let _SPARC_INS_FCMPES = 269;; let _SPARC_INS_WR = 270;; let _SPARC_INS_XMULX = 271;; let _SPARC_INS_XMULXHI = 272;; let _SPARC_INS_XNORCC = 273;; let _SPARC_INS_XNOR = 274;; let _SPARC_INS_XORCC = 275;; let _SPARC_INS_XOR = 276;; let _SPARC_INS_RET = 277;; let _SPARC_INS_RETL = 278;; let _SPARC_INS_ENDING = 279;; let _SPARC_GRP_INVALID = 0;; let _SPARC_GRP_JUMP = 1;; let _SPARC_GRP_HARDQUAD = 128;; let _SPARC_GRP_V9 = 129;; let _SPARC_GRP_VIS = 130;; let _SPARC_GRP_VIS2 = 131;; let _SPARC_GRP_VIS3 = 132;; let _SPARC_GRP_32BIT = 133;; let _SPARC_GRP_64BIT = 134;; let _SPARC_GRP_ENDING = 135;; capstone-sys-0.15.0/capstone/bindings/ocaml/systemz.ml000064400000000000000000000006650072674642500211520ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Sysz_const type sysz_op_mem = { base: int; index: int; length: int64; disp: int64; } type sysz_op_value = | SYSZ_OP_INVALID of int | SYSZ_OP_REG of int | SYSZ_OP_ACREG of int | SYSZ_OP_IMM of int | SYSZ_OP_MEM of sysz_op_mem type sysz_op = { value: sysz_op_value; } type cs_sysz = { cc: int; operands: sysz_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/sysz_const.ml000064400000000000000000002132410072674642500216460ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.ml] *) let _SYSZ_CC_INVALID = 0;; let _SYSZ_CC_O = 1;; let _SYSZ_CC_H = 2;; let _SYSZ_CC_NLE = 3;; let _SYSZ_CC_L = 4;; let _SYSZ_CC_NHE = 5;; let _SYSZ_CC_LH = 6;; let _SYSZ_CC_NE = 7;; let _SYSZ_CC_E = 8;; let _SYSZ_CC_NLH = 9;; let _SYSZ_CC_HE = 10;; let _SYSZ_CC_NL = 11;; let _SYSZ_CC_LE = 12;; let _SYSZ_CC_NH = 13;; let _SYSZ_CC_NO = 14;; let _SYSZ_OP_INVALID = 0;; let _SYSZ_OP_REG = 1;; let _SYSZ_OP_IMM = 2;; let _SYSZ_OP_MEM = 3;; let _SYSZ_OP_ACREG = 64;; let _SYSZ_REG_INVALID = 0;; let _SYSZ_REG_0 = 1;; let _SYSZ_REG_1 = 2;; let _SYSZ_REG_2 = 3;; let _SYSZ_REG_3 = 4;; let _SYSZ_REG_4 = 5;; let _SYSZ_REG_5 = 6;; let _SYSZ_REG_6 = 7;; let _SYSZ_REG_7 = 8;; let _SYSZ_REG_8 = 9;; let _SYSZ_REG_9 = 10;; let _SYSZ_REG_10 = 11;; let _SYSZ_REG_11 = 12;; let _SYSZ_REG_12 = 13;; let _SYSZ_REG_13 = 14;; let _SYSZ_REG_14 = 15;; let _SYSZ_REG_15 = 16;; let _SYSZ_REG_CC = 17;; let _SYSZ_REG_F0 = 18;; let _SYSZ_REG_F1 = 19;; let _SYSZ_REG_F2 = 20;; let _SYSZ_REG_F3 = 21;; let _SYSZ_REG_F4 = 22;; let _SYSZ_REG_F5 = 23;; let _SYSZ_REG_F6 = 24;; let _SYSZ_REG_F7 = 25;; let _SYSZ_REG_F8 = 26;; let _SYSZ_REG_F9 = 27;; let _SYSZ_REG_F10 = 28;; let _SYSZ_REG_F11 = 29;; let _SYSZ_REG_F12 = 30;; let _SYSZ_REG_F13 = 31;; let _SYSZ_REG_F14 = 32;; let _SYSZ_REG_F15 = 33;; let _SYSZ_REG_R0L = 34;; let _SYSZ_REG_A0 = 35;; let _SYSZ_REG_A1 = 36;; let _SYSZ_REG_A2 = 37;; let _SYSZ_REG_A3 = 38;; let _SYSZ_REG_A4 = 39;; let _SYSZ_REG_A5 = 40;; let _SYSZ_REG_A6 = 41;; let _SYSZ_REG_A7 = 42;; let _SYSZ_REG_A8 = 43;; let _SYSZ_REG_A9 = 44;; let _SYSZ_REG_A10 = 45;; let _SYSZ_REG_A11 = 46;; let _SYSZ_REG_A12 = 47;; let _SYSZ_REG_A13 = 48;; let _SYSZ_REG_A14 = 49;; let _SYSZ_REG_A15 = 50;; let _SYSZ_REG_C0 = 51;; let _SYSZ_REG_C1 = 52;; let _SYSZ_REG_C2 = 53;; let _SYSZ_REG_C3 = 54;; let _SYSZ_REG_C4 = 55;; let _SYSZ_REG_C5 = 56;; let _SYSZ_REG_C6 = 57;; let _SYSZ_REG_C7 = 58;; let _SYSZ_REG_C8 = 59;; let _SYSZ_REG_C9 = 60;; let _SYSZ_REG_C10 = 61;; let _SYSZ_REG_C11 = 62;; let _SYSZ_REG_C12 = 63;; let _SYSZ_REG_C13 = 64;; let _SYSZ_REG_C14 = 65;; let _SYSZ_REG_C15 = 66;; let _SYSZ_REG_V0 = 67;; let _SYSZ_REG_V1 = 68;; let _SYSZ_REG_V2 = 69;; let _SYSZ_REG_V3 = 70;; let _SYSZ_REG_V4 = 71;; let _SYSZ_REG_V5 = 72;; let _SYSZ_REG_V6 = 73;; let _SYSZ_REG_V7 = 74;; let _SYSZ_REG_V8 = 75;; let _SYSZ_REG_V9 = 76;; let _SYSZ_REG_V10 = 77;; let _SYSZ_REG_V11 = 78;; let _SYSZ_REG_V12 = 79;; let _SYSZ_REG_V13 = 80;; let _SYSZ_REG_V14 = 81;; let _SYSZ_REG_V15 = 82;; let _SYSZ_REG_V16 = 83;; let _SYSZ_REG_V17 = 84;; let _SYSZ_REG_V18 = 85;; let _SYSZ_REG_V19 = 86;; let _SYSZ_REG_V20 = 87;; let _SYSZ_REG_V21 = 88;; let _SYSZ_REG_V22 = 89;; let _SYSZ_REG_V23 = 90;; let _SYSZ_REG_V24 = 91;; let _SYSZ_REG_V25 = 92;; let _SYSZ_REG_V26 = 93;; let _SYSZ_REG_V27 = 94;; let _SYSZ_REG_V28 = 95;; let _SYSZ_REG_V29 = 96;; let _SYSZ_REG_V30 = 97;; let _SYSZ_REG_V31 = 98;; let _SYSZ_REG_F16 = 99;; let _SYSZ_REG_F17 = 100;; let _SYSZ_REG_F18 = 101;; let _SYSZ_REG_F19 = 102;; let _SYSZ_REG_F20 = 103;; let _SYSZ_REG_F21 = 104;; let _SYSZ_REG_F22 = 105;; let _SYSZ_REG_F23 = 106;; let _SYSZ_REG_F24 = 107;; let _SYSZ_REG_F25 = 108;; let _SYSZ_REG_F26 = 109;; let _SYSZ_REG_F27 = 110;; let _SYSZ_REG_F28 = 111;; let _SYSZ_REG_F29 = 112;; let _SYSZ_REG_F30 = 113;; let _SYSZ_REG_F31 = 114;; let _SYSZ_REG_F0Q = 115;; let _SYSZ_REG_F4Q = 116;; let _SYSZ_REG_ENDING = 117;; let _SYSZ_INS_INVALID = 0;; let _SYSZ_INS_A = 1;; let _SYSZ_INS_ADB = 2;; let _SYSZ_INS_ADBR = 3;; let _SYSZ_INS_AEB = 4;; let _SYSZ_INS_AEBR = 5;; let _SYSZ_INS_AFI = 6;; let _SYSZ_INS_AG = 7;; let _SYSZ_INS_AGF = 8;; let _SYSZ_INS_AGFI = 9;; let _SYSZ_INS_AGFR = 10;; let _SYSZ_INS_AGHI = 11;; let _SYSZ_INS_AGHIK = 12;; let _SYSZ_INS_AGR = 13;; let _SYSZ_INS_AGRK = 14;; let _SYSZ_INS_AGSI = 15;; let _SYSZ_INS_AH = 16;; let _SYSZ_INS_AHI = 17;; let _SYSZ_INS_AHIK = 18;; let _SYSZ_INS_AHY = 19;; let _SYSZ_INS_AIH = 20;; let _SYSZ_INS_AL = 21;; let _SYSZ_INS_ALC = 22;; let _SYSZ_INS_ALCG = 23;; let _SYSZ_INS_ALCGR = 24;; let _SYSZ_INS_ALCR = 25;; let _SYSZ_INS_ALFI = 26;; let _SYSZ_INS_ALG = 27;; let _SYSZ_INS_ALGF = 28;; let _SYSZ_INS_ALGFI = 29;; let _SYSZ_INS_ALGFR = 30;; let _SYSZ_INS_ALGHSIK = 31;; let _SYSZ_INS_ALGR = 32;; let _SYSZ_INS_ALGRK = 33;; let _SYSZ_INS_ALHSIK = 34;; let _SYSZ_INS_ALR = 35;; let _SYSZ_INS_ALRK = 36;; let _SYSZ_INS_ALY = 37;; let _SYSZ_INS_AR = 38;; let _SYSZ_INS_ARK = 39;; let _SYSZ_INS_ASI = 40;; let _SYSZ_INS_AXBR = 41;; let _SYSZ_INS_AY = 42;; let _SYSZ_INS_BCR = 43;; let _SYSZ_INS_BRC = 44;; let _SYSZ_INS_BRCL = 45;; let _SYSZ_INS_CGIJ = 46;; let _SYSZ_INS_CGRJ = 47;; let _SYSZ_INS_CIJ = 48;; let _SYSZ_INS_CLGIJ = 49;; let _SYSZ_INS_CLGRJ = 50;; let _SYSZ_INS_CLIJ = 51;; let _SYSZ_INS_CLRJ = 52;; let _SYSZ_INS_CRJ = 53;; let _SYSZ_INS_BER = 54;; let _SYSZ_INS_JE = 55;; let _SYSZ_INS_JGE = 56;; let _SYSZ_INS_LOCE = 57;; let _SYSZ_INS_LOCGE = 58;; let _SYSZ_INS_LOCGRE = 59;; let _SYSZ_INS_LOCRE = 60;; let _SYSZ_INS_STOCE = 61;; let _SYSZ_INS_STOCGE = 62;; let _SYSZ_INS_BHR = 63;; let _SYSZ_INS_BHER = 64;; let _SYSZ_INS_JHE = 65;; let _SYSZ_INS_JGHE = 66;; let _SYSZ_INS_LOCHE = 67;; let _SYSZ_INS_LOCGHE = 68;; let _SYSZ_INS_LOCGRHE = 69;; let _SYSZ_INS_LOCRHE = 70;; let _SYSZ_INS_STOCHE = 71;; let _SYSZ_INS_STOCGHE = 72;; let _SYSZ_INS_JH = 73;; let _SYSZ_INS_JGH = 74;; let _SYSZ_INS_LOCH = 75;; let _SYSZ_INS_LOCGH = 76;; let _SYSZ_INS_LOCGRH = 77;; let _SYSZ_INS_LOCRH = 78;; let _SYSZ_INS_STOCH = 79;; let _SYSZ_INS_STOCGH = 80;; let _SYSZ_INS_CGIJNLH = 81;; let _SYSZ_INS_CGRJNLH = 82;; let _SYSZ_INS_CIJNLH = 83;; let _SYSZ_INS_CLGIJNLH = 84;; let _SYSZ_INS_CLGRJNLH = 85;; let _SYSZ_INS_CLIJNLH = 86;; let _SYSZ_INS_CLRJNLH = 87;; let _SYSZ_INS_CRJNLH = 88;; let _SYSZ_INS_CGIJE = 89;; let _SYSZ_INS_CGRJE = 90;; let _SYSZ_INS_CIJE = 91;; let _SYSZ_INS_CLGIJE = 92;; let _SYSZ_INS_CLGRJE = 93;; let _SYSZ_INS_CLIJE = 94;; let _SYSZ_INS_CLRJE = 95;; let _SYSZ_INS_CRJE = 96;; let _SYSZ_INS_CGIJNLE = 97;; let _SYSZ_INS_CGRJNLE = 98;; let _SYSZ_INS_CIJNLE = 99;; let _SYSZ_INS_CLGIJNLE = 100;; let _SYSZ_INS_CLGRJNLE = 101;; let _SYSZ_INS_CLIJNLE = 102;; let _SYSZ_INS_CLRJNLE = 103;; let _SYSZ_INS_CRJNLE = 104;; let _SYSZ_INS_CGIJH = 105;; let _SYSZ_INS_CGRJH = 106;; let _SYSZ_INS_CIJH = 107;; let _SYSZ_INS_CLGIJH = 108;; let _SYSZ_INS_CLGRJH = 109;; let _SYSZ_INS_CLIJH = 110;; let _SYSZ_INS_CLRJH = 111;; let _SYSZ_INS_CRJH = 112;; let _SYSZ_INS_CGIJNL = 113;; let _SYSZ_INS_CGRJNL = 114;; let _SYSZ_INS_CIJNL = 115;; let _SYSZ_INS_CLGIJNL = 116;; let _SYSZ_INS_CLGRJNL = 117;; let _SYSZ_INS_CLIJNL = 118;; let _SYSZ_INS_CLRJNL = 119;; let _SYSZ_INS_CRJNL = 120;; let _SYSZ_INS_CGIJHE = 121;; let _SYSZ_INS_CGRJHE = 122;; let _SYSZ_INS_CIJHE = 123;; let _SYSZ_INS_CLGIJHE = 124;; let _SYSZ_INS_CLGRJHE = 125;; let _SYSZ_INS_CLIJHE = 126;; let _SYSZ_INS_CLRJHE = 127;; let _SYSZ_INS_CRJHE = 128;; let _SYSZ_INS_CGIJNHE = 129;; let _SYSZ_INS_CGRJNHE = 130;; let _SYSZ_INS_CIJNHE = 131;; let _SYSZ_INS_CLGIJNHE = 132;; let _SYSZ_INS_CLGRJNHE = 133;; let _SYSZ_INS_CLIJNHE = 134;; let _SYSZ_INS_CLRJNHE = 135;; let _SYSZ_INS_CRJNHE = 136;; let _SYSZ_INS_CGIJL = 137;; let _SYSZ_INS_CGRJL = 138;; let _SYSZ_INS_CIJL = 139;; let _SYSZ_INS_CLGIJL = 140;; let _SYSZ_INS_CLGRJL = 141;; let _SYSZ_INS_CLIJL = 142;; let _SYSZ_INS_CLRJL = 143;; let _SYSZ_INS_CRJL = 144;; let _SYSZ_INS_CGIJNH = 145;; let _SYSZ_INS_CGRJNH = 146;; let _SYSZ_INS_CIJNH = 147;; let _SYSZ_INS_CLGIJNH = 148;; let _SYSZ_INS_CLGRJNH = 149;; let _SYSZ_INS_CLIJNH = 150;; let _SYSZ_INS_CLRJNH = 151;; let _SYSZ_INS_CRJNH = 152;; let _SYSZ_INS_CGIJLE = 153;; let _SYSZ_INS_CGRJLE = 154;; let _SYSZ_INS_CIJLE = 155;; let _SYSZ_INS_CLGIJLE = 156;; let _SYSZ_INS_CLGRJLE = 157;; let _SYSZ_INS_CLIJLE = 158;; let _SYSZ_INS_CLRJLE = 159;; let _SYSZ_INS_CRJLE = 160;; let _SYSZ_INS_CGIJNE = 161;; let _SYSZ_INS_CGRJNE = 162;; let _SYSZ_INS_CIJNE = 163;; let _SYSZ_INS_CLGIJNE = 164;; let _SYSZ_INS_CLGRJNE = 165;; let _SYSZ_INS_CLIJNE = 166;; let _SYSZ_INS_CLRJNE = 167;; let _SYSZ_INS_CRJNE = 168;; let _SYSZ_INS_CGIJLH = 169;; let _SYSZ_INS_CGRJLH = 170;; let _SYSZ_INS_CIJLH = 171;; let _SYSZ_INS_CLGIJLH = 172;; let _SYSZ_INS_CLGRJLH = 173;; let _SYSZ_INS_CLIJLH = 174;; let _SYSZ_INS_CLRJLH = 175;; let _SYSZ_INS_CRJLH = 176;; let _SYSZ_INS_BLR = 177;; let _SYSZ_INS_BLER = 178;; let _SYSZ_INS_JLE = 179;; let _SYSZ_INS_JGLE = 180;; let _SYSZ_INS_LOCLE = 181;; let _SYSZ_INS_LOCGLE = 182;; let _SYSZ_INS_LOCGRLE = 183;; let _SYSZ_INS_LOCRLE = 184;; let _SYSZ_INS_STOCLE = 185;; let _SYSZ_INS_STOCGLE = 186;; let _SYSZ_INS_BLHR = 187;; let _SYSZ_INS_JLH = 188;; let _SYSZ_INS_JGLH = 189;; let _SYSZ_INS_LOCLH = 190;; let _SYSZ_INS_LOCGLH = 191;; let _SYSZ_INS_LOCGRLH = 192;; let _SYSZ_INS_LOCRLH = 193;; let _SYSZ_INS_STOCLH = 194;; let _SYSZ_INS_STOCGLH = 195;; let _SYSZ_INS_JL = 196;; let _SYSZ_INS_JGL = 197;; let _SYSZ_INS_LOCL = 198;; let _SYSZ_INS_LOCGL = 199;; let _SYSZ_INS_LOCGRL = 200;; let _SYSZ_INS_LOCRL = 201;; let _SYSZ_INS_LOC = 202;; let _SYSZ_INS_LOCG = 203;; let _SYSZ_INS_LOCGR = 204;; let _SYSZ_INS_LOCR = 205;; let _SYSZ_INS_STOCL = 206;; let _SYSZ_INS_STOCGL = 207;; let _SYSZ_INS_BNER = 208;; let _SYSZ_INS_JNE = 209;; let _SYSZ_INS_JGNE = 210;; let _SYSZ_INS_LOCNE = 211;; let _SYSZ_INS_LOCGNE = 212;; let _SYSZ_INS_LOCGRNE = 213;; let _SYSZ_INS_LOCRNE = 214;; let _SYSZ_INS_STOCNE = 215;; let _SYSZ_INS_STOCGNE = 216;; let _SYSZ_INS_BNHR = 217;; let _SYSZ_INS_BNHER = 218;; let _SYSZ_INS_JNHE = 219;; let _SYSZ_INS_JGNHE = 220;; let _SYSZ_INS_LOCNHE = 221;; let _SYSZ_INS_LOCGNHE = 222;; let _SYSZ_INS_LOCGRNHE = 223;; let _SYSZ_INS_LOCRNHE = 224;; let _SYSZ_INS_STOCNHE = 225;; let _SYSZ_INS_STOCGNHE = 226;; let _SYSZ_INS_JNH = 227;; let _SYSZ_INS_JGNH = 228;; let _SYSZ_INS_LOCNH = 229;; let _SYSZ_INS_LOCGNH = 230;; let _SYSZ_INS_LOCGRNH = 231;; let _SYSZ_INS_LOCRNH = 232;; let _SYSZ_INS_STOCNH = 233;; let _SYSZ_INS_STOCGNH = 234;; let _SYSZ_INS_BNLR = 235;; let _SYSZ_INS_BNLER = 236;; let _SYSZ_INS_JNLE = 237;; let _SYSZ_INS_JGNLE = 238;; let _SYSZ_INS_LOCNLE = 239;; let _SYSZ_INS_LOCGNLE = 240;; let _SYSZ_INS_LOCGRNLE = 241;; let _SYSZ_INS_LOCRNLE = 242;; let _SYSZ_INS_STOCNLE = 243;; let _SYSZ_INS_STOCGNLE = 244;; let _SYSZ_INS_BNLHR = 245;; let _SYSZ_INS_JNLH = 246;; let _SYSZ_INS_JGNLH = 247;; let _SYSZ_INS_LOCNLH = 248;; let _SYSZ_INS_LOCGNLH = 249;; let _SYSZ_INS_LOCGRNLH = 250;; let _SYSZ_INS_LOCRNLH = 251;; let _SYSZ_INS_STOCNLH = 252;; let _SYSZ_INS_STOCGNLH = 253;; let _SYSZ_INS_JNL = 254;; let _SYSZ_INS_JGNL = 255;; let _SYSZ_INS_LOCNL = 256;; let _SYSZ_INS_LOCGNL = 257;; let _SYSZ_INS_LOCGRNL = 258;; let _SYSZ_INS_LOCRNL = 259;; let _SYSZ_INS_STOCNL = 260;; let _SYSZ_INS_STOCGNL = 261;; let _SYSZ_INS_BNOR = 262;; let _SYSZ_INS_JNO = 263;; let _SYSZ_INS_JGNO = 264;; let _SYSZ_INS_LOCNO = 265;; let _SYSZ_INS_LOCGNO = 266;; let _SYSZ_INS_LOCGRNO = 267;; let _SYSZ_INS_LOCRNO = 268;; let _SYSZ_INS_STOCNO = 269;; let _SYSZ_INS_STOCGNO = 270;; let _SYSZ_INS_BOR = 271;; let _SYSZ_INS_JO = 272;; let _SYSZ_INS_JGO = 273;; let _SYSZ_INS_LOCO = 274;; let _SYSZ_INS_LOCGO = 275;; let _SYSZ_INS_LOCGRO = 276;; let _SYSZ_INS_LOCRO = 277;; let _SYSZ_INS_STOCO = 278;; let _SYSZ_INS_STOCGO = 279;; let _SYSZ_INS_STOC = 280;; let _SYSZ_INS_STOCG = 281;; let _SYSZ_INS_BASR = 282;; let _SYSZ_INS_BR = 283;; let _SYSZ_INS_BRAS = 284;; let _SYSZ_INS_BRASL = 285;; let _SYSZ_INS_J = 286;; let _SYSZ_INS_JG = 287;; let _SYSZ_INS_BRCT = 288;; let _SYSZ_INS_BRCTG = 289;; let _SYSZ_INS_C = 290;; let _SYSZ_INS_CDB = 291;; let _SYSZ_INS_CDBR = 292;; let _SYSZ_INS_CDFBR = 293;; let _SYSZ_INS_CDGBR = 294;; let _SYSZ_INS_CDLFBR = 295;; let _SYSZ_INS_CDLGBR = 296;; let _SYSZ_INS_CEB = 297;; let _SYSZ_INS_CEBR = 298;; let _SYSZ_INS_CEFBR = 299;; let _SYSZ_INS_CEGBR = 300;; let _SYSZ_INS_CELFBR = 301;; let _SYSZ_INS_CELGBR = 302;; let _SYSZ_INS_CFDBR = 303;; let _SYSZ_INS_CFEBR = 304;; let _SYSZ_INS_CFI = 305;; let _SYSZ_INS_CFXBR = 306;; let _SYSZ_INS_CG = 307;; let _SYSZ_INS_CGDBR = 308;; let _SYSZ_INS_CGEBR = 309;; let _SYSZ_INS_CGF = 310;; let _SYSZ_INS_CGFI = 311;; let _SYSZ_INS_CGFR = 312;; let _SYSZ_INS_CGFRL = 313;; let _SYSZ_INS_CGH = 314;; let _SYSZ_INS_CGHI = 315;; let _SYSZ_INS_CGHRL = 316;; let _SYSZ_INS_CGHSI = 317;; let _SYSZ_INS_CGR = 318;; let _SYSZ_INS_CGRL = 319;; let _SYSZ_INS_CGXBR = 320;; let _SYSZ_INS_CH = 321;; let _SYSZ_INS_CHF = 322;; let _SYSZ_INS_CHHSI = 323;; let _SYSZ_INS_CHI = 324;; let _SYSZ_INS_CHRL = 325;; let _SYSZ_INS_CHSI = 326;; let _SYSZ_INS_CHY = 327;; let _SYSZ_INS_CIH = 328;; let _SYSZ_INS_CL = 329;; let _SYSZ_INS_CLC = 330;; let _SYSZ_INS_CLFDBR = 331;; let _SYSZ_INS_CLFEBR = 332;; let _SYSZ_INS_CLFHSI = 333;; let _SYSZ_INS_CLFI = 334;; let _SYSZ_INS_CLFXBR = 335;; let _SYSZ_INS_CLG = 336;; let _SYSZ_INS_CLGDBR = 337;; let _SYSZ_INS_CLGEBR = 338;; let _SYSZ_INS_CLGF = 339;; let _SYSZ_INS_CLGFI = 340;; let _SYSZ_INS_CLGFR = 341;; let _SYSZ_INS_CLGFRL = 342;; let _SYSZ_INS_CLGHRL = 343;; let _SYSZ_INS_CLGHSI = 344;; let _SYSZ_INS_CLGR = 345;; let _SYSZ_INS_CLGRL = 346;; let _SYSZ_INS_CLGXBR = 347;; let _SYSZ_INS_CLHF = 348;; let _SYSZ_INS_CLHHSI = 349;; let _SYSZ_INS_CLHRL = 350;; let _SYSZ_INS_CLI = 351;; let _SYSZ_INS_CLIH = 352;; let _SYSZ_INS_CLIY = 353;; let _SYSZ_INS_CLR = 354;; let _SYSZ_INS_CLRL = 355;; let _SYSZ_INS_CLST = 356;; let _SYSZ_INS_CLY = 357;; let _SYSZ_INS_CPSDR = 358;; let _SYSZ_INS_CR = 359;; let _SYSZ_INS_CRL = 360;; let _SYSZ_INS_CS = 361;; let _SYSZ_INS_CSG = 362;; let _SYSZ_INS_CSY = 363;; let _SYSZ_INS_CXBR = 364;; let _SYSZ_INS_CXFBR = 365;; let _SYSZ_INS_CXGBR = 366;; let _SYSZ_INS_CXLFBR = 367;; let _SYSZ_INS_CXLGBR = 368;; let _SYSZ_INS_CY = 369;; let _SYSZ_INS_DDB = 370;; let _SYSZ_INS_DDBR = 371;; let _SYSZ_INS_DEB = 372;; let _SYSZ_INS_DEBR = 373;; let _SYSZ_INS_DL = 374;; let _SYSZ_INS_DLG = 375;; let _SYSZ_INS_DLGR = 376;; let _SYSZ_INS_DLR = 377;; let _SYSZ_INS_DSG = 378;; let _SYSZ_INS_DSGF = 379;; let _SYSZ_INS_DSGFR = 380;; let _SYSZ_INS_DSGR = 381;; let _SYSZ_INS_DXBR = 382;; let _SYSZ_INS_EAR = 383;; let _SYSZ_INS_FIDBR = 384;; let _SYSZ_INS_FIDBRA = 385;; let _SYSZ_INS_FIEBR = 386;; let _SYSZ_INS_FIEBRA = 387;; let _SYSZ_INS_FIXBR = 388;; let _SYSZ_INS_FIXBRA = 389;; let _SYSZ_INS_FLOGR = 390;; let _SYSZ_INS_IC = 391;; let _SYSZ_INS_ICY = 392;; let _SYSZ_INS_IIHF = 393;; let _SYSZ_INS_IIHH = 394;; let _SYSZ_INS_IIHL = 395;; let _SYSZ_INS_IILF = 396;; let _SYSZ_INS_IILH = 397;; let _SYSZ_INS_IILL = 398;; let _SYSZ_INS_IPM = 399;; let _SYSZ_INS_L = 400;; let _SYSZ_INS_LA = 401;; let _SYSZ_INS_LAA = 402;; let _SYSZ_INS_LAAG = 403;; let _SYSZ_INS_LAAL = 404;; let _SYSZ_INS_LAALG = 405;; let _SYSZ_INS_LAN = 406;; let _SYSZ_INS_LANG = 407;; let _SYSZ_INS_LAO = 408;; let _SYSZ_INS_LAOG = 409;; let _SYSZ_INS_LARL = 410;; let _SYSZ_INS_LAX = 411;; let _SYSZ_INS_LAXG = 412;; let _SYSZ_INS_LAY = 413;; let _SYSZ_INS_LB = 414;; let _SYSZ_INS_LBH = 415;; let _SYSZ_INS_LBR = 416;; let _SYSZ_INS_LCDBR = 417;; let _SYSZ_INS_LCEBR = 418;; let _SYSZ_INS_LCGFR = 419;; let _SYSZ_INS_LCGR = 420;; let _SYSZ_INS_LCR = 421;; let _SYSZ_INS_LCXBR = 422;; let _SYSZ_INS_LD = 423;; let _SYSZ_INS_LDEB = 424;; let _SYSZ_INS_LDEBR = 425;; let _SYSZ_INS_LDGR = 426;; let _SYSZ_INS_LDR = 427;; let _SYSZ_INS_LDXBR = 428;; let _SYSZ_INS_LDXBRA = 429;; let _SYSZ_INS_LDY = 430;; let _SYSZ_INS_LE = 431;; let _SYSZ_INS_LEDBR = 432;; let _SYSZ_INS_LEDBRA = 433;; let _SYSZ_INS_LER = 434;; let _SYSZ_INS_LEXBR = 435;; let _SYSZ_INS_LEXBRA = 436;; let _SYSZ_INS_LEY = 437;; let _SYSZ_INS_LFH = 438;; let _SYSZ_INS_LG = 439;; let _SYSZ_INS_LGB = 440;; let _SYSZ_INS_LGBR = 441;; let _SYSZ_INS_LGDR = 442;; let _SYSZ_INS_LGF = 443;; let _SYSZ_INS_LGFI = 444;; let _SYSZ_INS_LGFR = 445;; let _SYSZ_INS_LGFRL = 446;; let _SYSZ_INS_LGH = 447;; let _SYSZ_INS_LGHI = 448;; let _SYSZ_INS_LGHR = 449;; let _SYSZ_INS_LGHRL = 450;; let _SYSZ_INS_LGR = 451;; let _SYSZ_INS_LGRL = 452;; let _SYSZ_INS_LH = 453;; let _SYSZ_INS_LHH = 454;; let _SYSZ_INS_LHI = 455;; let _SYSZ_INS_LHR = 456;; let _SYSZ_INS_LHRL = 457;; let _SYSZ_INS_LHY = 458;; let _SYSZ_INS_LLC = 459;; let _SYSZ_INS_LLCH = 460;; let _SYSZ_INS_LLCR = 461;; let _SYSZ_INS_LLGC = 462;; let _SYSZ_INS_LLGCR = 463;; let _SYSZ_INS_LLGF = 464;; let _SYSZ_INS_LLGFR = 465;; let _SYSZ_INS_LLGFRL = 466;; let _SYSZ_INS_LLGH = 467;; let _SYSZ_INS_LLGHR = 468;; let _SYSZ_INS_LLGHRL = 469;; let _SYSZ_INS_LLH = 470;; let _SYSZ_INS_LLHH = 471;; let _SYSZ_INS_LLHR = 472;; let _SYSZ_INS_LLHRL = 473;; let _SYSZ_INS_LLIHF = 474;; let _SYSZ_INS_LLIHH = 475;; let _SYSZ_INS_LLIHL = 476;; let _SYSZ_INS_LLILF = 477;; let _SYSZ_INS_LLILH = 478;; let _SYSZ_INS_LLILL = 479;; let _SYSZ_INS_LMG = 480;; let _SYSZ_INS_LNDBR = 481;; let _SYSZ_INS_LNEBR = 482;; let _SYSZ_INS_LNGFR = 483;; let _SYSZ_INS_LNGR = 484;; let _SYSZ_INS_LNR = 485;; let _SYSZ_INS_LNXBR = 486;; let _SYSZ_INS_LPDBR = 487;; let _SYSZ_INS_LPEBR = 488;; let _SYSZ_INS_LPGFR = 489;; let _SYSZ_INS_LPGR = 490;; let _SYSZ_INS_LPR = 491;; let _SYSZ_INS_LPXBR = 492;; let _SYSZ_INS_LR = 493;; let _SYSZ_INS_LRL = 494;; let _SYSZ_INS_LRV = 495;; let _SYSZ_INS_LRVG = 496;; let _SYSZ_INS_LRVGR = 497;; let _SYSZ_INS_LRVR = 498;; let _SYSZ_INS_LT = 499;; let _SYSZ_INS_LTDBR = 500;; let _SYSZ_INS_LTEBR = 501;; let _SYSZ_INS_LTG = 502;; let _SYSZ_INS_LTGF = 503;; let _SYSZ_INS_LTGFR = 504;; let _SYSZ_INS_LTGR = 505;; let _SYSZ_INS_LTR = 506;; let _SYSZ_INS_LTXBR = 507;; let _SYSZ_INS_LXDB = 508;; let _SYSZ_INS_LXDBR = 509;; let _SYSZ_INS_LXEB = 510;; let _SYSZ_INS_LXEBR = 511;; let _SYSZ_INS_LXR = 512;; let _SYSZ_INS_LY = 513;; let _SYSZ_INS_LZDR = 514;; let _SYSZ_INS_LZER = 515;; let _SYSZ_INS_LZXR = 516;; let _SYSZ_INS_MADB = 517;; let _SYSZ_INS_MADBR = 518;; let _SYSZ_INS_MAEB = 519;; let _SYSZ_INS_MAEBR = 520;; let _SYSZ_INS_MDB = 521;; let _SYSZ_INS_MDBR = 522;; let _SYSZ_INS_MDEB = 523;; let _SYSZ_INS_MDEBR = 524;; let _SYSZ_INS_MEEB = 525;; let _SYSZ_INS_MEEBR = 526;; let _SYSZ_INS_MGHI = 527;; let _SYSZ_INS_MH = 528;; let _SYSZ_INS_MHI = 529;; let _SYSZ_INS_MHY = 530;; let _SYSZ_INS_MLG = 531;; let _SYSZ_INS_MLGR = 532;; let _SYSZ_INS_MS = 533;; let _SYSZ_INS_MSDB = 534;; let _SYSZ_INS_MSDBR = 535;; let _SYSZ_INS_MSEB = 536;; let _SYSZ_INS_MSEBR = 537;; let _SYSZ_INS_MSFI = 538;; let _SYSZ_INS_MSG = 539;; let _SYSZ_INS_MSGF = 540;; let _SYSZ_INS_MSGFI = 541;; let _SYSZ_INS_MSGFR = 542;; let _SYSZ_INS_MSGR = 543;; let _SYSZ_INS_MSR = 544;; let _SYSZ_INS_MSY = 545;; let _SYSZ_INS_MVC = 546;; let _SYSZ_INS_MVGHI = 547;; let _SYSZ_INS_MVHHI = 548;; let _SYSZ_INS_MVHI = 549;; let _SYSZ_INS_MVI = 550;; let _SYSZ_INS_MVIY = 551;; let _SYSZ_INS_MVST = 552;; let _SYSZ_INS_MXBR = 553;; let _SYSZ_INS_MXDB = 554;; let _SYSZ_INS_MXDBR = 555;; let _SYSZ_INS_N = 556;; let _SYSZ_INS_NC = 557;; let _SYSZ_INS_NG = 558;; let _SYSZ_INS_NGR = 559;; let _SYSZ_INS_NGRK = 560;; let _SYSZ_INS_NI = 561;; let _SYSZ_INS_NIHF = 562;; let _SYSZ_INS_NIHH = 563;; let _SYSZ_INS_NIHL = 564;; let _SYSZ_INS_NILF = 565;; let _SYSZ_INS_NILH = 566;; let _SYSZ_INS_NILL = 567;; let _SYSZ_INS_NIY = 568;; let _SYSZ_INS_NR = 569;; let _SYSZ_INS_NRK = 570;; let _SYSZ_INS_NY = 571;; let _SYSZ_INS_O = 572;; let _SYSZ_INS_OC = 573;; let _SYSZ_INS_OG = 574;; let _SYSZ_INS_OGR = 575;; let _SYSZ_INS_OGRK = 576;; let _SYSZ_INS_OI = 577;; let _SYSZ_INS_OIHF = 578;; let _SYSZ_INS_OIHH = 579;; let _SYSZ_INS_OIHL = 580;; let _SYSZ_INS_OILF = 581;; let _SYSZ_INS_OILH = 582;; let _SYSZ_INS_OILL = 583;; let _SYSZ_INS_OIY = 584;; let _SYSZ_INS_OR = 585;; let _SYSZ_INS_ORK = 586;; let _SYSZ_INS_OY = 587;; let _SYSZ_INS_PFD = 588;; let _SYSZ_INS_PFDRL = 589;; let _SYSZ_INS_RISBG = 590;; let _SYSZ_INS_RISBHG = 591;; let _SYSZ_INS_RISBLG = 592;; let _SYSZ_INS_RLL = 593;; let _SYSZ_INS_RLLG = 594;; let _SYSZ_INS_RNSBG = 595;; let _SYSZ_INS_ROSBG = 596;; let _SYSZ_INS_RXSBG = 597;; let _SYSZ_INS_S = 598;; let _SYSZ_INS_SDB = 599;; let _SYSZ_INS_SDBR = 600;; let _SYSZ_INS_SEB = 601;; let _SYSZ_INS_SEBR = 602;; let _SYSZ_INS_SG = 603;; let _SYSZ_INS_SGF = 604;; let _SYSZ_INS_SGFR = 605;; let _SYSZ_INS_SGR = 606;; let _SYSZ_INS_SGRK = 607;; let _SYSZ_INS_SH = 608;; let _SYSZ_INS_SHY = 609;; let _SYSZ_INS_SL = 610;; let _SYSZ_INS_SLB = 611;; let _SYSZ_INS_SLBG = 612;; let _SYSZ_INS_SLBR = 613;; let _SYSZ_INS_SLFI = 614;; let _SYSZ_INS_SLG = 615;; let _SYSZ_INS_SLBGR = 616;; let _SYSZ_INS_SLGF = 617;; let _SYSZ_INS_SLGFI = 618;; let _SYSZ_INS_SLGFR = 619;; let _SYSZ_INS_SLGR = 620;; let _SYSZ_INS_SLGRK = 621;; let _SYSZ_INS_SLL = 622;; let _SYSZ_INS_SLLG = 623;; let _SYSZ_INS_SLLK = 624;; let _SYSZ_INS_SLR = 625;; let _SYSZ_INS_SLRK = 626;; let _SYSZ_INS_SLY = 627;; let _SYSZ_INS_SQDB = 628;; let _SYSZ_INS_SQDBR = 629;; let _SYSZ_INS_SQEB = 630;; let _SYSZ_INS_SQEBR = 631;; let _SYSZ_INS_SQXBR = 632;; let _SYSZ_INS_SR = 633;; let _SYSZ_INS_SRA = 634;; let _SYSZ_INS_SRAG = 635;; let _SYSZ_INS_SRAK = 636;; let _SYSZ_INS_SRK = 637;; let _SYSZ_INS_SRL = 638;; let _SYSZ_INS_SRLG = 639;; let _SYSZ_INS_SRLK = 640;; let _SYSZ_INS_SRST = 641;; let _SYSZ_INS_ST = 642;; let _SYSZ_INS_STC = 643;; let _SYSZ_INS_STCH = 644;; let _SYSZ_INS_STCY = 645;; let _SYSZ_INS_STD = 646;; let _SYSZ_INS_STDY = 647;; let _SYSZ_INS_STE = 648;; let _SYSZ_INS_STEY = 649;; let _SYSZ_INS_STFH = 650;; let _SYSZ_INS_STG = 651;; let _SYSZ_INS_STGRL = 652;; let _SYSZ_INS_STH = 653;; let _SYSZ_INS_STHH = 654;; let _SYSZ_INS_STHRL = 655;; let _SYSZ_INS_STHY = 656;; let _SYSZ_INS_STMG = 657;; let _SYSZ_INS_STRL = 658;; let _SYSZ_INS_STRV = 659;; let _SYSZ_INS_STRVG = 660;; let _SYSZ_INS_STY = 661;; let _SYSZ_INS_SXBR = 662;; let _SYSZ_INS_SY = 663;; let _SYSZ_INS_TM = 664;; let _SYSZ_INS_TMHH = 665;; let _SYSZ_INS_TMHL = 666;; let _SYSZ_INS_TMLH = 667;; let _SYSZ_INS_TMLL = 668;; let _SYSZ_INS_TMY = 669;; let _SYSZ_INS_X = 670;; let _SYSZ_INS_XC = 671;; let _SYSZ_INS_XG = 672;; let _SYSZ_INS_XGR = 673;; let _SYSZ_INS_XGRK = 674;; let _SYSZ_INS_XI = 675;; let _SYSZ_INS_XIHF = 676;; let _SYSZ_INS_XILF = 677;; let _SYSZ_INS_XIY = 678;; let _SYSZ_INS_XR = 679;; let _SYSZ_INS_XRK = 680;; let _SYSZ_INS_XY = 681;; let _SYSZ_INS_AD = 682;; let _SYSZ_INS_ADR = 683;; let _SYSZ_INS_ADTR = 684;; let _SYSZ_INS_ADTRA = 685;; let _SYSZ_INS_AE = 686;; let _SYSZ_INS_AER = 687;; let _SYSZ_INS_AGH = 688;; let _SYSZ_INS_AHHHR = 689;; let _SYSZ_INS_AHHLR = 690;; let _SYSZ_INS_ALGSI = 691;; let _SYSZ_INS_ALHHHR = 692;; let _SYSZ_INS_ALHHLR = 693;; let _SYSZ_INS_ALSI = 694;; let _SYSZ_INS_ALSIH = 695;; let _SYSZ_INS_ALSIHN = 696;; let _SYSZ_INS_AP = 697;; let _SYSZ_INS_AU = 698;; let _SYSZ_INS_AUR = 699;; let _SYSZ_INS_AW = 700;; let _SYSZ_INS_AWR = 701;; let _SYSZ_INS_AXR = 702;; let _SYSZ_INS_AXTR = 703;; let _SYSZ_INS_AXTRA = 704;; let _SYSZ_INS_B = 705;; let _SYSZ_INS_BAKR = 706;; let _SYSZ_INS_BAL = 707;; let _SYSZ_INS_BALR = 708;; let _SYSZ_INS_BAS = 709;; let _SYSZ_INS_BASSM = 710;; let _SYSZ_INS_BC = 711;; let _SYSZ_INS_BCT = 712;; let _SYSZ_INS_BCTG = 713;; let _SYSZ_INS_BCTGR = 714;; let _SYSZ_INS_BCTR = 715;; let _SYSZ_INS_BE = 716;; let _SYSZ_INS_BH = 717;; let _SYSZ_INS_BHE = 718;; let _SYSZ_INS_BI = 719;; let _SYSZ_INS_BIC = 720;; let _SYSZ_INS_BIE = 721;; let _SYSZ_INS_BIH = 722;; let _SYSZ_INS_BIHE = 723;; let _SYSZ_INS_BIL = 724;; let _SYSZ_INS_BILE = 725;; let _SYSZ_INS_BILH = 726;; let _SYSZ_INS_BIM = 727;; let _SYSZ_INS_BINE = 728;; let _SYSZ_INS_BINH = 729;; let _SYSZ_INS_BINHE = 730;; let _SYSZ_INS_BINL = 731;; let _SYSZ_INS_BINLE = 732;; let _SYSZ_INS_BINLH = 733;; let _SYSZ_INS_BINM = 734;; let _SYSZ_INS_BINO = 735;; let _SYSZ_INS_BINP = 736;; let _SYSZ_INS_BINZ = 737;; let _SYSZ_INS_BIO = 738;; let _SYSZ_INS_BIP = 739;; let _SYSZ_INS_BIZ = 740;; let _SYSZ_INS_BL = 741;; let _SYSZ_INS_BLE = 742;; let _SYSZ_INS_BLH = 743;; let _SYSZ_INS_BM = 744;; let _SYSZ_INS_BMR = 745;; let _SYSZ_INS_BNE = 746;; let _SYSZ_INS_BNH = 747;; let _SYSZ_INS_BNHE = 748;; let _SYSZ_INS_BNL = 749;; let _SYSZ_INS_BNLE = 750;; let _SYSZ_INS_BNLH = 751;; let _SYSZ_INS_BNM = 752;; let _SYSZ_INS_BNMR = 753;; let _SYSZ_INS_BNO = 754;; let _SYSZ_INS_BNP = 755;; let _SYSZ_INS_BNPR = 756;; let _SYSZ_INS_BNZ = 757;; let _SYSZ_INS_BNZR = 758;; let _SYSZ_INS_BO = 759;; let _SYSZ_INS_BP = 760;; let _SYSZ_INS_BPP = 761;; let _SYSZ_INS_BPR = 762;; let _SYSZ_INS_BPRP = 763;; let _SYSZ_INS_BRCTH = 764;; let _SYSZ_INS_BRXH = 765;; let _SYSZ_INS_BRXHG = 766;; let _SYSZ_INS_BRXLE = 767;; let _SYSZ_INS_BRXLG = 768;; let _SYSZ_INS_BSA = 769;; let _SYSZ_INS_BSG = 770;; let _SYSZ_INS_BSM = 771;; let _SYSZ_INS_BXH = 772;; let _SYSZ_INS_BXHG = 773;; let _SYSZ_INS_BXLE = 774;; let _SYSZ_INS_BXLEG = 775;; let _SYSZ_INS_BZ = 776;; let _SYSZ_INS_BZR = 777;; let _SYSZ_INS_CD = 778;; let _SYSZ_INS_CDFBRA = 779;; let _SYSZ_INS_CDFR = 780;; let _SYSZ_INS_CDFTR = 781;; let _SYSZ_INS_CDGBRA = 782;; let _SYSZ_INS_CDGR = 783;; let _SYSZ_INS_CDGTR = 784;; let _SYSZ_INS_CDGTRA = 785;; let _SYSZ_INS_CDLFTR = 786;; let _SYSZ_INS_CDLGTR = 787;; let _SYSZ_INS_CDPT = 788;; let _SYSZ_INS_CDR = 789;; let _SYSZ_INS_CDS = 790;; let _SYSZ_INS_CDSG = 791;; let _SYSZ_INS_CDSTR = 792;; let _SYSZ_INS_CDSY = 793;; let _SYSZ_INS_CDTR = 794;; let _SYSZ_INS_CDUTR = 795;; let _SYSZ_INS_CDZT = 796;; let _SYSZ_INS_CE = 797;; let _SYSZ_INS_CEDTR = 798;; let _SYSZ_INS_CEFBRA = 799;; let _SYSZ_INS_CEFR = 800;; let _SYSZ_INS_CEGBRA = 801;; let _SYSZ_INS_CEGR = 802;; let _SYSZ_INS_CER = 803;; let _SYSZ_INS_CEXTR = 804;; let _SYSZ_INS_CFC = 805;; let _SYSZ_INS_CFDBRA = 806;; let _SYSZ_INS_CFDR = 807;; let _SYSZ_INS_CFDTR = 808;; let _SYSZ_INS_CFEBRA = 809;; let _SYSZ_INS_CFER = 810;; let _SYSZ_INS_CFXBRA = 811;; let _SYSZ_INS_CFXR = 812;; let _SYSZ_INS_CFXTR = 813;; let _SYSZ_INS_CGDBRA = 814;; let _SYSZ_INS_CGDR = 815;; let _SYSZ_INS_CGDTR = 816;; let _SYSZ_INS_CGDTRA = 817;; let _SYSZ_INS_CGEBRA = 818;; let _SYSZ_INS_CGER = 819;; let _SYSZ_INS_CGIB = 820;; let _SYSZ_INS_CGIBE = 821;; let _SYSZ_INS_CGIBH = 822;; let _SYSZ_INS_CGIBHE = 823;; let _SYSZ_INS_CGIBL = 824;; let _SYSZ_INS_CGIBLE = 825;; let _SYSZ_INS_CGIBLH = 826;; let _SYSZ_INS_CGIBNE = 827;; let _SYSZ_INS_CGIBNH = 828;; let _SYSZ_INS_CGIBNHE = 829;; let _SYSZ_INS_CGIBNL = 830;; let _SYSZ_INS_CGIBNLE = 831;; let _SYSZ_INS_CGIBNLH = 832;; let _SYSZ_INS_CGIT = 833;; let _SYSZ_INS_CGITE = 834;; let _SYSZ_INS_CGITH = 835;; let _SYSZ_INS_CGITHE = 836;; let _SYSZ_INS_CGITL = 837;; let _SYSZ_INS_CGITLE = 838;; let _SYSZ_INS_CGITLH = 839;; let _SYSZ_INS_CGITNE = 840;; let _SYSZ_INS_CGITNH = 841;; let _SYSZ_INS_CGITNHE = 842;; let _SYSZ_INS_CGITNL = 843;; let _SYSZ_INS_CGITNLE = 844;; let _SYSZ_INS_CGITNLH = 845;; let _SYSZ_INS_CGRB = 846;; let _SYSZ_INS_CGRBE = 847;; let _SYSZ_INS_CGRBH = 848;; let _SYSZ_INS_CGRBHE = 849;; let _SYSZ_INS_CGRBL = 850;; let _SYSZ_INS_CGRBLE = 851;; let _SYSZ_INS_CGRBLH = 852;; let _SYSZ_INS_CGRBNE = 853;; let _SYSZ_INS_CGRBNH = 854;; let _SYSZ_INS_CGRBNHE = 855;; let _SYSZ_INS_CGRBNL = 856;; let _SYSZ_INS_CGRBNLE = 857;; let _SYSZ_INS_CGRBNLH = 858;; let _SYSZ_INS_CGRT = 859;; let _SYSZ_INS_CGRTE = 860;; let _SYSZ_INS_CGRTH = 861;; let _SYSZ_INS_CGRTHE = 862;; let _SYSZ_INS_CGRTL = 863;; let _SYSZ_INS_CGRTLE = 864;; let _SYSZ_INS_CGRTLH = 865;; let _SYSZ_INS_CGRTNE = 866;; let _SYSZ_INS_CGRTNH = 867;; let _SYSZ_INS_CGRTNHE = 868;; let _SYSZ_INS_CGRTNL = 869;; let _SYSZ_INS_CGRTNLE = 870;; let _SYSZ_INS_CGRTNLH = 871;; let _SYSZ_INS_CGXBRA = 872;; let _SYSZ_INS_CGXR = 873;; let _SYSZ_INS_CGXTR = 874;; let _SYSZ_INS_CGXTRA = 875;; let _SYSZ_INS_CHHR = 876;; let _SYSZ_INS_CHLR = 877;; let _SYSZ_INS_CIB = 878;; let _SYSZ_INS_CIBE = 879;; let _SYSZ_INS_CIBH = 880;; let _SYSZ_INS_CIBHE = 881;; let _SYSZ_INS_CIBL = 882;; let _SYSZ_INS_CIBLE = 883;; let _SYSZ_INS_CIBLH = 884;; let _SYSZ_INS_CIBNE = 885;; let _SYSZ_INS_CIBNH = 886;; let _SYSZ_INS_CIBNHE = 887;; let _SYSZ_INS_CIBNL = 888;; let _SYSZ_INS_CIBNLE = 889;; let _SYSZ_INS_CIBNLH = 890;; let _SYSZ_INS_CIT = 891;; let _SYSZ_INS_CITE = 892;; let _SYSZ_INS_CITH = 893;; let _SYSZ_INS_CITHE = 894;; let _SYSZ_INS_CITL = 895;; let _SYSZ_INS_CITLE = 896;; let _SYSZ_INS_CITLH = 897;; let _SYSZ_INS_CITNE = 898;; let _SYSZ_INS_CITNH = 899;; let _SYSZ_INS_CITNHE = 900;; let _SYSZ_INS_CITNL = 901;; let _SYSZ_INS_CITNLE = 902;; let _SYSZ_INS_CITNLH = 903;; let _SYSZ_INS_CKSM = 904;; let _SYSZ_INS_CLCL = 905;; let _SYSZ_INS_CLCLE = 906;; let _SYSZ_INS_CLCLU = 907;; let _SYSZ_INS_CLFDTR = 908;; let _SYSZ_INS_CLFIT = 909;; let _SYSZ_INS_CLFITE = 910;; let _SYSZ_INS_CLFITH = 911;; let _SYSZ_INS_CLFITHE = 912;; let _SYSZ_INS_CLFITL = 913;; let _SYSZ_INS_CLFITLE = 914;; let _SYSZ_INS_CLFITLH = 915;; let _SYSZ_INS_CLFITNE = 916;; let _SYSZ_INS_CLFITNH = 917;; let _SYSZ_INS_CLFITNHE = 918;; let _SYSZ_INS_CLFITNL = 919;; let _SYSZ_INS_CLFITNLE = 920;; let _SYSZ_INS_CLFITNLH = 921;; let _SYSZ_INS_CLFXTR = 922;; let _SYSZ_INS_CLGDTR = 923;; let _SYSZ_INS_CLGIB = 924;; let _SYSZ_INS_CLGIBE = 925;; let _SYSZ_INS_CLGIBH = 926;; let _SYSZ_INS_CLGIBHE = 927;; let _SYSZ_INS_CLGIBL = 928;; let _SYSZ_INS_CLGIBLE = 929;; let _SYSZ_INS_CLGIBLH = 930;; let _SYSZ_INS_CLGIBNE = 931;; let _SYSZ_INS_CLGIBNH = 932;; let _SYSZ_INS_CLGIBNHE = 933;; let _SYSZ_INS_CLGIBNL = 934;; let _SYSZ_INS_CLGIBNLE = 935;; let _SYSZ_INS_CLGIBNLH = 936;; let _SYSZ_INS_CLGIT = 937;; let _SYSZ_INS_CLGITE = 938;; let _SYSZ_INS_CLGITH = 939;; let _SYSZ_INS_CLGITHE = 940;; let _SYSZ_INS_CLGITL = 941;; let _SYSZ_INS_CLGITLE = 942;; let _SYSZ_INS_CLGITLH = 943;; let _SYSZ_INS_CLGITNE = 944;; let _SYSZ_INS_CLGITNH = 945;; let _SYSZ_INS_CLGITNHE = 946;; let _SYSZ_INS_CLGITNL = 947;; let _SYSZ_INS_CLGITNLE = 948;; let _SYSZ_INS_CLGITNLH = 949;; let _SYSZ_INS_CLGRB = 950;; let _SYSZ_INS_CLGRBE = 951;; let _SYSZ_INS_CLGRBH = 952;; let _SYSZ_INS_CLGRBHE = 953;; let _SYSZ_INS_CLGRBL = 954;; let _SYSZ_INS_CLGRBLE = 955;; let _SYSZ_INS_CLGRBLH = 956;; let _SYSZ_INS_CLGRBNE = 957;; let _SYSZ_INS_CLGRBNH = 958;; let _SYSZ_INS_CLGRBNHE = 959;; let _SYSZ_INS_CLGRBNL = 960;; let _SYSZ_INS_CLGRBNLE = 961;; let _SYSZ_INS_CLGRBNLH = 962;; let _SYSZ_INS_CLGRT = 963;; let _SYSZ_INS_CLGRTE = 964;; let _SYSZ_INS_CLGRTH = 965;; let _SYSZ_INS_CLGRTHE = 966;; let _SYSZ_INS_CLGRTL = 967;; let _SYSZ_INS_CLGRTLE = 968;; let _SYSZ_INS_CLGRTLH = 969;; let _SYSZ_INS_CLGRTNE = 970;; let _SYSZ_INS_CLGRTNH = 971;; let _SYSZ_INS_CLGRTNHE = 972;; let _SYSZ_INS_CLGRTNL = 973;; let _SYSZ_INS_CLGRTNLE = 974;; let _SYSZ_INS_CLGRTNLH = 975;; let _SYSZ_INS_CLGT = 976;; let _SYSZ_INS_CLGTE = 977;; let _SYSZ_INS_CLGTH = 978;; let _SYSZ_INS_CLGTHE = 979;; let _SYSZ_INS_CLGTL = 980;; let _SYSZ_INS_CLGTLE = 981;; let _SYSZ_INS_CLGTLH = 982;; let _SYSZ_INS_CLGTNE = 983;; let _SYSZ_INS_CLGTNH = 984;; let _SYSZ_INS_CLGTNHE = 985;; let _SYSZ_INS_CLGTNL = 986;; let _SYSZ_INS_CLGTNLE = 987;; let _SYSZ_INS_CLGTNLH = 988;; let _SYSZ_INS_CLGXTR = 989;; let _SYSZ_INS_CLHHR = 990;; let _SYSZ_INS_CLHLR = 991;; let _SYSZ_INS_CLIB = 992;; let _SYSZ_INS_CLIBE = 993;; let _SYSZ_INS_CLIBH = 994;; let _SYSZ_INS_CLIBHE = 995;; let _SYSZ_INS_CLIBL = 996;; let _SYSZ_INS_CLIBLE = 997;; let _SYSZ_INS_CLIBLH = 998;; let _SYSZ_INS_CLIBNE = 999;; let _SYSZ_INS_CLIBNH = 1000;; let _SYSZ_INS_CLIBNHE = 1001;; let _SYSZ_INS_CLIBNL = 1002;; let _SYSZ_INS_CLIBNLE = 1003;; let _SYSZ_INS_CLIBNLH = 1004;; let _SYSZ_INS_CLM = 1005;; let _SYSZ_INS_CLMH = 1006;; let _SYSZ_INS_CLMY = 1007;; let _SYSZ_INS_CLRB = 1008;; let _SYSZ_INS_CLRBE = 1009;; let _SYSZ_INS_CLRBH = 1010;; let _SYSZ_INS_CLRBHE = 1011;; let _SYSZ_INS_CLRBL = 1012;; let _SYSZ_INS_CLRBLE = 1013;; let _SYSZ_INS_CLRBLH = 1014;; let _SYSZ_INS_CLRBNE = 1015;; let _SYSZ_INS_CLRBNH = 1016;; let _SYSZ_INS_CLRBNHE = 1017;; let _SYSZ_INS_CLRBNL = 1018;; let _SYSZ_INS_CLRBNLE = 1019;; let _SYSZ_INS_CLRBNLH = 1020;; let _SYSZ_INS_CLRT = 1021;; let _SYSZ_INS_CLRTE = 1022;; let _SYSZ_INS_CLRTH = 1023;; let _SYSZ_INS_CLRTHE = 1024;; let _SYSZ_INS_CLRTL = 1025;; let _SYSZ_INS_CLRTLE = 1026;; let _SYSZ_INS_CLRTLH = 1027;; let _SYSZ_INS_CLRTNE = 1028;; let _SYSZ_INS_CLRTNH = 1029;; let _SYSZ_INS_CLRTNHE = 1030;; let _SYSZ_INS_CLRTNL = 1031;; let _SYSZ_INS_CLRTNLE = 1032;; let _SYSZ_INS_CLRTNLH = 1033;; let _SYSZ_INS_CLT = 1034;; let _SYSZ_INS_CLTE = 1035;; let _SYSZ_INS_CLTH = 1036;; let _SYSZ_INS_CLTHE = 1037;; let _SYSZ_INS_CLTL = 1038;; let _SYSZ_INS_CLTLE = 1039;; let _SYSZ_INS_CLTLH = 1040;; let _SYSZ_INS_CLTNE = 1041;; let _SYSZ_INS_CLTNH = 1042;; let _SYSZ_INS_CLTNHE = 1043;; let _SYSZ_INS_CLTNL = 1044;; let _SYSZ_INS_CLTNLE = 1045;; let _SYSZ_INS_CLTNLH = 1046;; let _SYSZ_INS_CMPSC = 1047;; let _SYSZ_INS_CP = 1048;; let _SYSZ_INS_CPDT = 1049;; let _SYSZ_INS_CPXT = 1050;; let _SYSZ_INS_CPYA = 1051;; let _SYSZ_INS_CRB = 1052;; let _SYSZ_INS_CRBE = 1053;; let _SYSZ_INS_CRBH = 1054;; let _SYSZ_INS_CRBHE = 1055;; let _SYSZ_INS_CRBL = 1056;; let _SYSZ_INS_CRBLE = 1057;; let _SYSZ_INS_CRBLH = 1058;; let _SYSZ_INS_CRBNE = 1059;; let _SYSZ_INS_CRBNH = 1060;; let _SYSZ_INS_CRBNHE = 1061;; let _SYSZ_INS_CRBNL = 1062;; let _SYSZ_INS_CRBNLE = 1063;; let _SYSZ_INS_CRBNLH = 1064;; let _SYSZ_INS_CRDTE = 1065;; let _SYSZ_INS_CRT = 1066;; let _SYSZ_INS_CRTE = 1067;; let _SYSZ_INS_CRTH = 1068;; let _SYSZ_INS_CRTHE = 1069;; let _SYSZ_INS_CRTL = 1070;; let _SYSZ_INS_CRTLE = 1071;; let _SYSZ_INS_CRTLH = 1072;; let _SYSZ_INS_CRTNE = 1073;; let _SYSZ_INS_CRTNH = 1074;; let _SYSZ_INS_CRTNHE = 1075;; let _SYSZ_INS_CRTNL = 1076;; let _SYSZ_INS_CRTNLE = 1077;; let _SYSZ_INS_CRTNLH = 1078;; let _SYSZ_INS_CSCH = 1079;; let _SYSZ_INS_CSDTR = 1080;; let _SYSZ_INS_CSP = 1081;; let _SYSZ_INS_CSPG = 1082;; let _SYSZ_INS_CSST = 1083;; let _SYSZ_INS_CSXTR = 1084;; let _SYSZ_INS_CU12 = 1085;; let _SYSZ_INS_CU14 = 1086;; let _SYSZ_INS_CU21 = 1087;; let _SYSZ_INS_CU24 = 1088;; let _SYSZ_INS_CU41 = 1089;; let _SYSZ_INS_CU42 = 1090;; let _SYSZ_INS_CUDTR = 1091;; let _SYSZ_INS_CUSE = 1092;; let _SYSZ_INS_CUTFU = 1093;; let _SYSZ_INS_CUUTF = 1094;; let _SYSZ_INS_CUXTR = 1095;; let _SYSZ_INS_CVB = 1096;; let _SYSZ_INS_CVBG = 1097;; let _SYSZ_INS_CVBY = 1098;; let _SYSZ_INS_CVD = 1099;; let _SYSZ_INS_CVDG = 1100;; let _SYSZ_INS_CVDY = 1101;; let _SYSZ_INS_CXFBRA = 1102;; let _SYSZ_INS_CXFR = 1103;; let _SYSZ_INS_CXFTR = 1104;; let _SYSZ_INS_CXGBRA = 1105;; let _SYSZ_INS_CXGR = 1106;; let _SYSZ_INS_CXGTR = 1107;; let _SYSZ_INS_CXGTRA = 1108;; let _SYSZ_INS_CXLFTR = 1109;; let _SYSZ_INS_CXLGTR = 1110;; let _SYSZ_INS_CXPT = 1111;; let _SYSZ_INS_CXR = 1112;; let _SYSZ_INS_CXSTR = 1113;; let _SYSZ_INS_CXTR = 1114;; let _SYSZ_INS_CXUTR = 1115;; let _SYSZ_INS_CXZT = 1116;; let _SYSZ_INS_CZDT = 1117;; let _SYSZ_INS_CZXT = 1118;; let _SYSZ_INS_D = 1119;; let _SYSZ_INS_DD = 1120;; let _SYSZ_INS_DDR = 1121;; let _SYSZ_INS_DDTR = 1122;; let _SYSZ_INS_DDTRA = 1123;; let _SYSZ_INS_DE = 1124;; let _SYSZ_INS_DER = 1125;; let _SYSZ_INS_DIAG = 1126;; let _SYSZ_INS_DIDBR = 1127;; let _SYSZ_INS_DIEBR = 1128;; let _SYSZ_INS_DP = 1129;; let _SYSZ_INS_DR = 1130;; let _SYSZ_INS_DXR = 1131;; let _SYSZ_INS_DXTR = 1132;; let _SYSZ_INS_DXTRA = 1133;; let _SYSZ_INS_ECAG = 1134;; let _SYSZ_INS_ECCTR = 1135;; let _SYSZ_INS_ECPGA = 1136;; let _SYSZ_INS_ECTG = 1137;; let _SYSZ_INS_ED = 1138;; let _SYSZ_INS_EDMK = 1139;; let _SYSZ_INS_EEDTR = 1140;; let _SYSZ_INS_EEXTR = 1141;; let _SYSZ_INS_EFPC = 1142;; let _SYSZ_INS_EPAIR = 1143;; let _SYSZ_INS_EPAR = 1144;; let _SYSZ_INS_EPCTR = 1145;; let _SYSZ_INS_EPSW = 1146;; let _SYSZ_INS_EREG = 1147;; let _SYSZ_INS_EREGG = 1148;; let _SYSZ_INS_ESAIR = 1149;; let _SYSZ_INS_ESAR = 1150;; let _SYSZ_INS_ESDTR = 1151;; let _SYSZ_INS_ESEA = 1152;; let _SYSZ_INS_ESTA = 1153;; let _SYSZ_INS_ESXTR = 1154;; let _SYSZ_INS_ETND = 1155;; let _SYSZ_INS_EX = 1156;; let _SYSZ_INS_EXRL = 1157;; let _SYSZ_INS_FIDR = 1158;; let _SYSZ_INS_FIDTR = 1159;; let _SYSZ_INS_FIER = 1160;; let _SYSZ_INS_FIXR = 1161;; let _SYSZ_INS_FIXTR = 1162;; let _SYSZ_INS_HDR = 1163;; let _SYSZ_INS_HER = 1164;; let _SYSZ_INS_HSCH = 1165;; let _SYSZ_INS_IAC = 1166;; let _SYSZ_INS_ICM = 1167;; let _SYSZ_INS_ICMH = 1168;; let _SYSZ_INS_ICMY = 1169;; let _SYSZ_INS_IDTE = 1170;; let _SYSZ_INS_IEDTR = 1171;; let _SYSZ_INS_IEXTR = 1172;; let _SYSZ_INS_IPK = 1173;; let _SYSZ_INS_IPTE = 1174;; let _SYSZ_INS_IRBM = 1175;; let _SYSZ_INS_ISKE = 1176;; let _SYSZ_INS_IVSK = 1177;; let _SYSZ_INS_JGM = 1178;; let _SYSZ_INS_JGNM = 1179;; let _SYSZ_INS_JGNP = 1180;; let _SYSZ_INS_JGNZ = 1181;; let _SYSZ_INS_JGP = 1182;; let _SYSZ_INS_JGZ = 1183;; let _SYSZ_INS_JM = 1184;; let _SYSZ_INS_JNM = 1185;; let _SYSZ_INS_JNP = 1186;; let _SYSZ_INS_JNZ = 1187;; let _SYSZ_INS_JP = 1188;; let _SYSZ_INS_JZ = 1189;; let _SYSZ_INS_KDB = 1190;; let _SYSZ_INS_KDBR = 1191;; let _SYSZ_INS_KDTR = 1192;; let _SYSZ_INS_KEB = 1193;; let _SYSZ_INS_KEBR = 1194;; let _SYSZ_INS_KIMD = 1195;; let _SYSZ_INS_KLMD = 1196;; let _SYSZ_INS_KM = 1197;; let _SYSZ_INS_KMA = 1198;; let _SYSZ_INS_KMAC = 1199;; let _SYSZ_INS_KMC = 1200;; let _SYSZ_INS_KMCTR = 1201;; let _SYSZ_INS_KMF = 1202;; let _SYSZ_INS_KMO = 1203;; let _SYSZ_INS_KXBR = 1204;; let _SYSZ_INS_KXTR = 1205;; let _SYSZ_INS_LAE = 1206;; let _SYSZ_INS_LAEY = 1207;; let _SYSZ_INS_LAM = 1208;; let _SYSZ_INS_LAMY = 1209;; let _SYSZ_INS_LASP = 1210;; let _SYSZ_INS_LAT = 1211;; let _SYSZ_INS_LCBB = 1212;; let _SYSZ_INS_LCCTL = 1213;; let _SYSZ_INS_LCDFR = 1214;; let _SYSZ_INS_LCDR = 1215;; let _SYSZ_INS_LCER = 1216;; let _SYSZ_INS_LCTL = 1217;; let _SYSZ_INS_LCTLG = 1218;; let _SYSZ_INS_LCXR = 1219;; let _SYSZ_INS_LDE = 1220;; let _SYSZ_INS_LDER = 1221;; let _SYSZ_INS_LDETR = 1222;; let _SYSZ_INS_LDXR = 1223;; let _SYSZ_INS_LDXTR = 1224;; let _SYSZ_INS_LEDR = 1225;; let _SYSZ_INS_LEDTR = 1226;; let _SYSZ_INS_LEXR = 1227;; let _SYSZ_INS_LFAS = 1228;; let _SYSZ_INS_LFHAT = 1229;; let _SYSZ_INS_LFPC = 1230;; let _SYSZ_INS_LGAT = 1231;; let _SYSZ_INS_LGG = 1232;; let _SYSZ_INS_LGSC = 1233;; let _SYSZ_INS_LLGFAT = 1234;; let _SYSZ_INS_LLGFSG = 1235;; let _SYSZ_INS_LLGT = 1236;; let _SYSZ_INS_LLGTAT = 1237;; let _SYSZ_INS_LLGTR = 1238;; let _SYSZ_INS_LLZRGF = 1239;; let _SYSZ_INS_LM = 1240;; let _SYSZ_INS_LMD = 1241;; let _SYSZ_INS_LMH = 1242;; let _SYSZ_INS_LMY = 1243;; let _SYSZ_INS_LNDFR = 1244;; let _SYSZ_INS_LNDR = 1245;; let _SYSZ_INS_LNER = 1246;; let _SYSZ_INS_LNXR = 1247;; let _SYSZ_INS_LOCFH = 1248;; let _SYSZ_INS_LOCFHE = 1249;; let _SYSZ_INS_LOCFHH = 1250;; let _SYSZ_INS_LOCFHHE = 1251;; let _SYSZ_INS_LOCFHL = 1252;; let _SYSZ_INS_LOCFHLE = 1253;; let _SYSZ_INS_LOCFHLH = 1254;; let _SYSZ_INS_LOCFHM = 1255;; let _SYSZ_INS_LOCFHNE = 1256;; let _SYSZ_INS_LOCFHNH = 1257;; let _SYSZ_INS_LOCFHNHE = 1258;; let _SYSZ_INS_LOCFHNL = 1259;; let _SYSZ_INS_LOCFHNLE = 1260;; let _SYSZ_INS_LOCFHNLH = 1261;; let _SYSZ_INS_LOCFHNM = 1262;; let _SYSZ_INS_LOCFHNO = 1263;; let _SYSZ_INS_LOCFHNP = 1264;; let _SYSZ_INS_LOCFHNZ = 1265;; let _SYSZ_INS_LOCFHO = 1266;; let _SYSZ_INS_LOCFHP = 1267;; let _SYSZ_INS_LOCFHR = 1268;; let _SYSZ_INS_LOCFHRE = 1269;; let _SYSZ_INS_LOCFHRH = 1270;; let _SYSZ_INS_LOCFHRHE = 1271;; let _SYSZ_INS_LOCFHRL = 1272;; let _SYSZ_INS_LOCFHRLE = 1273;; let _SYSZ_INS_LOCFHRLH = 1274;; let _SYSZ_INS_LOCFHRM = 1275;; let _SYSZ_INS_LOCFHRNE = 1276;; let _SYSZ_INS_LOCFHRNH = 1277;; let _SYSZ_INS_LOCFHRNHE = 1278;; let _SYSZ_INS_LOCFHRNL = 1279;; let _SYSZ_INS_LOCFHRNLE = 1280;; let _SYSZ_INS_LOCFHRNLH = 1281;; let _SYSZ_INS_LOCFHRNM = 1282;; let _SYSZ_INS_LOCFHRNO = 1283;; let _SYSZ_INS_LOCFHRNP = 1284;; let _SYSZ_INS_LOCFHRNZ = 1285;; let _SYSZ_INS_LOCFHRO = 1286;; let _SYSZ_INS_LOCFHRP = 1287;; let _SYSZ_INS_LOCFHRZ = 1288;; let _SYSZ_INS_LOCFHZ = 1289;; let _SYSZ_INS_LOCGHI = 1290;; let _SYSZ_INS_LOCGHIE = 1291;; let _SYSZ_INS_LOCGHIH = 1292;; let _SYSZ_INS_LOCGHIHE = 1293;; let _SYSZ_INS_LOCGHIL = 1294;; let _SYSZ_INS_LOCGHILE = 1295;; let _SYSZ_INS_LOCGHILH = 1296;; let _SYSZ_INS_LOCGHIM = 1297;; let _SYSZ_INS_LOCGHINE = 1298;; let _SYSZ_INS_LOCGHINH = 1299;; let _SYSZ_INS_LOCGHINHE = 1300;; let _SYSZ_INS_LOCGHINL = 1301;; let _SYSZ_INS_LOCGHINLE = 1302;; let _SYSZ_INS_LOCGHINLH = 1303;; let _SYSZ_INS_LOCGHINM = 1304;; let _SYSZ_INS_LOCGHINO = 1305;; let _SYSZ_INS_LOCGHINP = 1306;; let _SYSZ_INS_LOCGHINZ = 1307;; let _SYSZ_INS_LOCGHIO = 1308;; let _SYSZ_INS_LOCGHIP = 1309;; let _SYSZ_INS_LOCGHIZ = 1310;; let _SYSZ_INS_LOCGM = 1311;; let _SYSZ_INS_LOCGNM = 1312;; let _SYSZ_INS_LOCGNP = 1313;; let _SYSZ_INS_LOCGNZ = 1314;; let _SYSZ_INS_LOCGP = 1315;; let _SYSZ_INS_LOCGRM = 1316;; let _SYSZ_INS_LOCGRNM = 1317;; let _SYSZ_INS_LOCGRNP = 1318;; let _SYSZ_INS_LOCGRNZ = 1319;; let _SYSZ_INS_LOCGRP = 1320;; let _SYSZ_INS_LOCGRZ = 1321;; let _SYSZ_INS_LOCGZ = 1322;; let _SYSZ_INS_LOCHHI = 1323;; let _SYSZ_INS_LOCHHIE = 1324;; let _SYSZ_INS_LOCHHIH = 1325;; let _SYSZ_INS_LOCHHIHE = 1326;; let _SYSZ_INS_LOCHHIL = 1327;; let _SYSZ_INS_LOCHHILE = 1328;; let _SYSZ_INS_LOCHHILH = 1329;; let _SYSZ_INS_LOCHHIM = 1330;; let _SYSZ_INS_LOCHHINE = 1331;; let _SYSZ_INS_LOCHHINH = 1332;; let _SYSZ_INS_LOCHHINHE = 1333;; let _SYSZ_INS_LOCHHINL = 1334;; let _SYSZ_INS_LOCHHINLE = 1335;; let _SYSZ_INS_LOCHHINLH = 1336;; let _SYSZ_INS_LOCHHINM = 1337;; let _SYSZ_INS_LOCHHINO = 1338;; let _SYSZ_INS_LOCHHINP = 1339;; let _SYSZ_INS_LOCHHINZ = 1340;; let _SYSZ_INS_LOCHHIO = 1341;; let _SYSZ_INS_LOCHHIP = 1342;; let _SYSZ_INS_LOCHHIZ = 1343;; let _SYSZ_INS_LOCHI = 1344;; let _SYSZ_INS_LOCHIE = 1345;; let _SYSZ_INS_LOCHIH = 1346;; let _SYSZ_INS_LOCHIHE = 1347;; let _SYSZ_INS_LOCHIL = 1348;; let _SYSZ_INS_LOCHILE = 1349;; let _SYSZ_INS_LOCHILH = 1350;; let _SYSZ_INS_LOCHIM = 1351;; let _SYSZ_INS_LOCHINE = 1352;; let _SYSZ_INS_LOCHINH = 1353;; let _SYSZ_INS_LOCHINHE = 1354;; let _SYSZ_INS_LOCHINL = 1355;; let _SYSZ_INS_LOCHINLE = 1356;; let _SYSZ_INS_LOCHINLH = 1357;; let _SYSZ_INS_LOCHINM = 1358;; let _SYSZ_INS_LOCHINO = 1359;; let _SYSZ_INS_LOCHINP = 1360;; let _SYSZ_INS_LOCHINZ = 1361;; let _SYSZ_INS_LOCHIO = 1362;; let _SYSZ_INS_LOCHIP = 1363;; let _SYSZ_INS_LOCHIZ = 1364;; let _SYSZ_INS_LOCM = 1365;; let _SYSZ_INS_LOCNM = 1366;; let _SYSZ_INS_LOCNP = 1367;; let _SYSZ_INS_LOCNZ = 1368;; let _SYSZ_INS_LOCP = 1369;; let _SYSZ_INS_LOCRM = 1370;; let _SYSZ_INS_LOCRNM = 1371;; let _SYSZ_INS_LOCRNP = 1372;; let _SYSZ_INS_LOCRNZ = 1373;; let _SYSZ_INS_LOCRP = 1374;; let _SYSZ_INS_LOCRZ = 1375;; let _SYSZ_INS_LOCZ = 1376;; let _SYSZ_INS_LPCTL = 1377;; let _SYSZ_INS_LPD = 1378;; let _SYSZ_INS_LPDFR = 1379;; let _SYSZ_INS_LPDG = 1380;; let _SYSZ_INS_LPDR = 1381;; let _SYSZ_INS_LPER = 1382;; let _SYSZ_INS_LPP = 1383;; let _SYSZ_INS_LPQ = 1384;; let _SYSZ_INS_LPSW = 1385;; let _SYSZ_INS_LPSWE = 1386;; let _SYSZ_INS_LPTEA = 1387;; let _SYSZ_INS_LPXR = 1388;; let _SYSZ_INS_LRA = 1389;; let _SYSZ_INS_LRAG = 1390;; let _SYSZ_INS_LRAY = 1391;; let _SYSZ_INS_LRDR = 1392;; let _SYSZ_INS_LRER = 1393;; let _SYSZ_INS_LRVH = 1394;; let _SYSZ_INS_LSCTL = 1395;; let _SYSZ_INS_LTDR = 1396;; let _SYSZ_INS_LTDTR = 1397;; let _SYSZ_INS_LTER = 1398;; let _SYSZ_INS_LTXR = 1399;; let _SYSZ_INS_LTXTR = 1400;; let _SYSZ_INS_LURA = 1401;; let _SYSZ_INS_LURAG = 1402;; let _SYSZ_INS_LXD = 1403;; let _SYSZ_INS_LXDR = 1404;; let _SYSZ_INS_LXDTR = 1405;; let _SYSZ_INS_LXE = 1406;; let _SYSZ_INS_LXER = 1407;; let _SYSZ_INS_LZRF = 1408;; let _SYSZ_INS_LZRG = 1409;; let _SYSZ_INS_M = 1410;; let _SYSZ_INS_MAD = 1411;; let _SYSZ_INS_MADR = 1412;; let _SYSZ_INS_MAE = 1413;; let _SYSZ_INS_MAER = 1414;; let _SYSZ_INS_MAY = 1415;; let _SYSZ_INS_MAYH = 1416;; let _SYSZ_INS_MAYHR = 1417;; let _SYSZ_INS_MAYL = 1418;; let _SYSZ_INS_MAYLR = 1419;; let _SYSZ_INS_MAYR = 1420;; let _SYSZ_INS_MC = 1421;; let _SYSZ_INS_MD = 1422;; let _SYSZ_INS_MDE = 1423;; let _SYSZ_INS_MDER = 1424;; let _SYSZ_INS_MDR = 1425;; let _SYSZ_INS_MDTR = 1426;; let _SYSZ_INS_MDTRA = 1427;; let _SYSZ_INS_ME = 1428;; let _SYSZ_INS_MEE = 1429;; let _SYSZ_INS_MEER = 1430;; let _SYSZ_INS_MER = 1431;; let _SYSZ_INS_MFY = 1432;; let _SYSZ_INS_MG = 1433;; let _SYSZ_INS_MGH = 1434;; let _SYSZ_INS_MGRK = 1435;; let _SYSZ_INS_ML = 1436;; let _SYSZ_INS_MLR = 1437;; let _SYSZ_INS_MP = 1438;; let _SYSZ_INS_MR = 1439;; let _SYSZ_INS_MSC = 1440;; let _SYSZ_INS_MSCH = 1441;; let _SYSZ_INS_MSD = 1442;; let _SYSZ_INS_MSDR = 1443;; let _SYSZ_INS_MSE = 1444;; let _SYSZ_INS_MSER = 1445;; let _SYSZ_INS_MSGC = 1446;; let _SYSZ_INS_MSGRKC = 1447;; let _SYSZ_INS_MSRKC = 1448;; let _SYSZ_INS_MSTA = 1449;; let _SYSZ_INS_MVCDK = 1450;; let _SYSZ_INS_MVCIN = 1451;; let _SYSZ_INS_MVCK = 1452;; let _SYSZ_INS_MVCL = 1453;; let _SYSZ_INS_MVCLE = 1454;; let _SYSZ_INS_MVCLU = 1455;; let _SYSZ_INS_MVCOS = 1456;; let _SYSZ_INS_MVCP = 1457;; let _SYSZ_INS_MVCS = 1458;; let _SYSZ_INS_MVCSK = 1459;; let _SYSZ_INS_MVN = 1460;; let _SYSZ_INS_MVO = 1461;; let _SYSZ_INS_MVPG = 1462;; let _SYSZ_INS_MVZ = 1463;; let _SYSZ_INS_MXD = 1464;; let _SYSZ_INS_MXDR = 1465;; let _SYSZ_INS_MXR = 1466;; let _SYSZ_INS_MXTR = 1467;; let _SYSZ_INS_MXTRA = 1468;; let _SYSZ_INS_MY = 1469;; let _SYSZ_INS_MYH = 1470;; let _SYSZ_INS_MYHR = 1471;; let _SYSZ_INS_MYL = 1472;; let _SYSZ_INS_MYLR = 1473;; let _SYSZ_INS_MYR = 1474;; let _SYSZ_INS_NIAI = 1475;; let _SYSZ_INS_NTSTG = 1476;; let _SYSZ_INS_PACK = 1477;; let _SYSZ_INS_PALB = 1478;; let _SYSZ_INS_PC = 1479;; let _SYSZ_INS_PCC = 1480;; let _SYSZ_INS_PCKMO = 1481;; let _SYSZ_INS_PFMF = 1482;; let _SYSZ_INS_PFPO = 1483;; let _SYSZ_INS_PGIN = 1484;; let _SYSZ_INS_PGOUT = 1485;; let _SYSZ_INS_PKA = 1486;; let _SYSZ_INS_PKU = 1487;; let _SYSZ_INS_PLO = 1488;; let _SYSZ_INS_POPCNT = 1489;; let _SYSZ_INS_PPA = 1490;; let _SYSZ_INS_PPNO = 1491;; let _SYSZ_INS_PR = 1492;; let _SYSZ_INS_PRNO = 1493;; let _SYSZ_INS_PT = 1494;; let _SYSZ_INS_PTF = 1495;; let _SYSZ_INS_PTFF = 1496;; let _SYSZ_INS_PTI = 1497;; let _SYSZ_INS_PTLB = 1498;; let _SYSZ_INS_QADTR = 1499;; let _SYSZ_INS_QAXTR = 1500;; let _SYSZ_INS_QCTRI = 1501;; let _SYSZ_INS_QSI = 1502;; let _SYSZ_INS_RCHP = 1503;; let _SYSZ_INS_RISBGN = 1504;; let _SYSZ_INS_RP = 1505;; let _SYSZ_INS_RRBE = 1506;; let _SYSZ_INS_RRBM = 1507;; let _SYSZ_INS_RRDTR = 1508;; let _SYSZ_INS_RRXTR = 1509;; let _SYSZ_INS_RSCH = 1510;; let _SYSZ_INS_SAC = 1511;; let _SYSZ_INS_SACF = 1512;; let _SYSZ_INS_SAL = 1513;; let _SYSZ_INS_SAM24 = 1514;; let _SYSZ_INS_SAM31 = 1515;; let _SYSZ_INS_SAM64 = 1516;; let _SYSZ_INS_SAR = 1517;; let _SYSZ_INS_SCCTR = 1518;; let _SYSZ_INS_SCHM = 1519;; let _SYSZ_INS_SCK = 1520;; let _SYSZ_INS_SCKC = 1521;; let _SYSZ_INS_SCKPF = 1522;; let _SYSZ_INS_SD = 1523;; let _SYSZ_INS_SDR = 1524;; let _SYSZ_INS_SDTR = 1525;; let _SYSZ_INS_SDTRA = 1526;; let _SYSZ_INS_SE = 1527;; let _SYSZ_INS_SER = 1528;; let _SYSZ_INS_SFASR = 1529;; let _SYSZ_INS_SFPC = 1530;; let _SYSZ_INS_SGH = 1531;; let _SYSZ_INS_SHHHR = 1532;; let _SYSZ_INS_SHHLR = 1533;; let _SYSZ_INS_SIE = 1534;; let _SYSZ_INS_SIGA = 1535;; let _SYSZ_INS_SIGP = 1536;; let _SYSZ_INS_SLA = 1537;; let _SYSZ_INS_SLAG = 1538;; let _SYSZ_INS_SLAK = 1539;; let _SYSZ_INS_SLDA = 1540;; let _SYSZ_INS_SLDL = 1541;; let _SYSZ_INS_SLDT = 1542;; let _SYSZ_INS_SLHHHR = 1543;; let _SYSZ_INS_SLHHLR = 1544;; let _SYSZ_INS_SLXT = 1545;; let _SYSZ_INS_SP = 1546;; let _SYSZ_INS_SPCTR = 1547;; let _SYSZ_INS_SPKA = 1548;; let _SYSZ_INS_SPM = 1549;; let _SYSZ_INS_SPT = 1550;; let _SYSZ_INS_SPX = 1551;; let _SYSZ_INS_SQD = 1552;; let _SYSZ_INS_SQDR = 1553;; let _SYSZ_INS_SQE = 1554;; let _SYSZ_INS_SQER = 1555;; let _SYSZ_INS_SQXR = 1556;; let _SYSZ_INS_SRDA = 1557;; let _SYSZ_INS_SRDL = 1558;; let _SYSZ_INS_SRDT = 1559;; let _SYSZ_INS_SRNM = 1560;; let _SYSZ_INS_SRNMB = 1561;; let _SYSZ_INS_SRNMT = 1562;; let _SYSZ_INS_SRP = 1563;; let _SYSZ_INS_SRSTU = 1564;; let _SYSZ_INS_SRXT = 1565;; let _SYSZ_INS_SSAIR = 1566;; let _SYSZ_INS_SSAR = 1567;; let _SYSZ_INS_SSCH = 1568;; let _SYSZ_INS_SSKE = 1569;; let _SYSZ_INS_SSM = 1570;; let _SYSZ_INS_STAM = 1571;; let _SYSZ_INS_STAMY = 1572;; let _SYSZ_INS_STAP = 1573;; let _SYSZ_INS_STCK = 1574;; let _SYSZ_INS_STCKC = 1575;; let _SYSZ_INS_STCKE = 1576;; let _SYSZ_INS_STCKF = 1577;; let _SYSZ_INS_STCM = 1578;; let _SYSZ_INS_STCMH = 1579;; let _SYSZ_INS_STCMY = 1580;; let _SYSZ_INS_STCPS = 1581;; let _SYSZ_INS_STCRW = 1582;; let _SYSZ_INS_STCTG = 1583;; let _SYSZ_INS_STCTL = 1584;; let _SYSZ_INS_STFL = 1585;; let _SYSZ_INS_STFLE = 1586;; let _SYSZ_INS_STFPC = 1587;; let _SYSZ_INS_STGSC = 1588;; let _SYSZ_INS_STIDP = 1589;; let _SYSZ_INS_STM = 1590;; let _SYSZ_INS_STMH = 1591;; let _SYSZ_INS_STMY = 1592;; let _SYSZ_INS_STNSM = 1593;; let _SYSZ_INS_STOCFH = 1594;; let _SYSZ_INS_STOCFHE = 1595;; let _SYSZ_INS_STOCFHH = 1596;; let _SYSZ_INS_STOCFHHE = 1597;; let _SYSZ_INS_STOCFHL = 1598;; let _SYSZ_INS_STOCFHLE = 1599;; let _SYSZ_INS_STOCFHLH = 1600;; let _SYSZ_INS_STOCFHM = 1601;; let _SYSZ_INS_STOCFHNE = 1602;; let _SYSZ_INS_STOCFHNH = 1603;; let _SYSZ_INS_STOCFHNHE = 1604;; let _SYSZ_INS_STOCFHNL = 1605;; let _SYSZ_INS_STOCFHNLE = 1606;; let _SYSZ_INS_STOCFHNLH = 1607;; let _SYSZ_INS_STOCFHNM = 1608;; let _SYSZ_INS_STOCFHNO = 1609;; let _SYSZ_INS_STOCFHNP = 1610;; let _SYSZ_INS_STOCFHNZ = 1611;; let _SYSZ_INS_STOCFHO = 1612;; let _SYSZ_INS_STOCFHP = 1613;; let _SYSZ_INS_STOCFHZ = 1614;; let _SYSZ_INS_STOCGM = 1615;; let _SYSZ_INS_STOCGNM = 1616;; let _SYSZ_INS_STOCGNP = 1617;; let _SYSZ_INS_STOCGNZ = 1618;; let _SYSZ_INS_STOCGP = 1619;; let _SYSZ_INS_STOCGZ = 1620;; let _SYSZ_INS_STOCM = 1621;; let _SYSZ_INS_STOCNM = 1622;; let _SYSZ_INS_STOCNP = 1623;; let _SYSZ_INS_STOCNZ = 1624;; let _SYSZ_INS_STOCP = 1625;; let _SYSZ_INS_STOCZ = 1626;; let _SYSZ_INS_STOSM = 1627;; let _SYSZ_INS_STPQ = 1628;; let _SYSZ_INS_STPT = 1629;; let _SYSZ_INS_STPX = 1630;; let _SYSZ_INS_STRAG = 1631;; let _SYSZ_INS_STRVH = 1632;; let _SYSZ_INS_STSCH = 1633;; let _SYSZ_INS_STSI = 1634;; let _SYSZ_INS_STURA = 1635;; let _SYSZ_INS_STURG = 1636;; let _SYSZ_INS_SU = 1637;; let _SYSZ_INS_SUR = 1638;; let _SYSZ_INS_SVC = 1639;; let _SYSZ_INS_SW = 1640;; let _SYSZ_INS_SWR = 1641;; let _SYSZ_INS_SXR = 1642;; let _SYSZ_INS_SXTR = 1643;; let _SYSZ_INS_SXTRA = 1644;; let _SYSZ_INS_TABORT = 1645;; let _SYSZ_INS_TAM = 1646;; let _SYSZ_INS_TAR = 1647;; let _SYSZ_INS_TB = 1648;; let _SYSZ_INS_TBDR = 1649;; let _SYSZ_INS_TBEDR = 1650;; let _SYSZ_INS_TBEGIN = 1651;; let _SYSZ_INS_TBEGINC = 1652;; let _SYSZ_INS_TCDB = 1653;; let _SYSZ_INS_TCEB = 1654;; let _SYSZ_INS_TCXB = 1655;; let _SYSZ_INS_TDCDT = 1656;; let _SYSZ_INS_TDCET = 1657;; let _SYSZ_INS_TDCXT = 1658;; let _SYSZ_INS_TDGDT = 1659;; let _SYSZ_INS_TDGET = 1660;; let _SYSZ_INS_TDGXT = 1661;; let _SYSZ_INS_TEND = 1662;; let _SYSZ_INS_THDER = 1663;; let _SYSZ_INS_THDR = 1664;; let _SYSZ_INS_TP = 1665;; let _SYSZ_INS_TPI = 1666;; let _SYSZ_INS_TPROT = 1667;; let _SYSZ_INS_TR = 1668;; let _SYSZ_INS_TRACE = 1669;; let _SYSZ_INS_TRACG = 1670;; let _SYSZ_INS_TRAP2 = 1671;; let _SYSZ_INS_TRAP4 = 1672;; let _SYSZ_INS_TRE = 1673;; let _SYSZ_INS_TROO = 1674;; let _SYSZ_INS_TROT = 1675;; let _SYSZ_INS_TRT = 1676;; let _SYSZ_INS_TRTE = 1677;; let _SYSZ_INS_TRTO = 1678;; let _SYSZ_INS_TRTR = 1679;; let _SYSZ_INS_TRTRE = 1680;; let _SYSZ_INS_TRTT = 1681;; let _SYSZ_INS_TS = 1682;; let _SYSZ_INS_TSCH = 1683;; let _SYSZ_INS_UNPK = 1684;; let _SYSZ_INS_UNPKA = 1685;; let _SYSZ_INS_UNPKU = 1686;; let _SYSZ_INS_UPT = 1687;; let _SYSZ_INS_VA = 1688;; let _SYSZ_INS_VAB = 1689;; let _SYSZ_INS_VAC = 1690;; let _SYSZ_INS_VACC = 1691;; let _SYSZ_INS_VACCB = 1692;; let _SYSZ_INS_VACCC = 1693;; let _SYSZ_INS_VACCCQ = 1694;; let _SYSZ_INS_VACCF = 1695;; let _SYSZ_INS_VACCG = 1696;; let _SYSZ_INS_VACCH = 1697;; let _SYSZ_INS_VACCQ = 1698;; let _SYSZ_INS_VACQ = 1699;; let _SYSZ_INS_VAF = 1700;; let _SYSZ_INS_VAG = 1701;; let _SYSZ_INS_VAH = 1702;; let _SYSZ_INS_VAP = 1703;; let _SYSZ_INS_VAQ = 1704;; let _SYSZ_INS_VAVG = 1705;; let _SYSZ_INS_VAVGB = 1706;; let _SYSZ_INS_VAVGF = 1707;; let _SYSZ_INS_VAVGG = 1708;; let _SYSZ_INS_VAVGH = 1709;; let _SYSZ_INS_VAVGL = 1710;; let _SYSZ_INS_VAVGLB = 1711;; let _SYSZ_INS_VAVGLF = 1712;; let _SYSZ_INS_VAVGLG = 1713;; let _SYSZ_INS_VAVGLH = 1714;; let _SYSZ_INS_VBPERM = 1715;; let _SYSZ_INS_VCDG = 1716;; let _SYSZ_INS_VCDGB = 1717;; let _SYSZ_INS_VCDLG = 1718;; let _SYSZ_INS_VCDLGB = 1719;; let _SYSZ_INS_VCEQ = 1720;; let _SYSZ_INS_VCEQB = 1721;; let _SYSZ_INS_VCEQBS = 1722;; let _SYSZ_INS_VCEQF = 1723;; let _SYSZ_INS_VCEQFS = 1724;; let _SYSZ_INS_VCEQG = 1725;; let _SYSZ_INS_VCEQGS = 1726;; let _SYSZ_INS_VCEQH = 1727;; let _SYSZ_INS_VCEQHS = 1728;; let _SYSZ_INS_VCGD = 1729;; let _SYSZ_INS_VCGDB = 1730;; let _SYSZ_INS_VCH = 1731;; let _SYSZ_INS_VCHB = 1732;; let _SYSZ_INS_VCHBS = 1733;; let _SYSZ_INS_VCHF = 1734;; let _SYSZ_INS_VCHFS = 1735;; let _SYSZ_INS_VCHG = 1736;; let _SYSZ_INS_VCHGS = 1737;; let _SYSZ_INS_VCHH = 1738;; let _SYSZ_INS_VCHHS = 1739;; let _SYSZ_INS_VCHL = 1740;; let _SYSZ_INS_VCHLB = 1741;; let _SYSZ_INS_VCHLBS = 1742;; let _SYSZ_INS_VCHLF = 1743;; let _SYSZ_INS_VCHLFS = 1744;; let _SYSZ_INS_VCHLG = 1745;; let _SYSZ_INS_VCHLGS = 1746;; let _SYSZ_INS_VCHLH = 1747;; let _SYSZ_INS_VCHLHS = 1748;; let _SYSZ_INS_VCKSM = 1749;; let _SYSZ_INS_VCLGD = 1750;; let _SYSZ_INS_VCLGDB = 1751;; let _SYSZ_INS_VCLZ = 1752;; let _SYSZ_INS_VCLZB = 1753;; let _SYSZ_INS_VCLZF = 1754;; let _SYSZ_INS_VCLZG = 1755;; let _SYSZ_INS_VCLZH = 1756;; let _SYSZ_INS_VCP = 1757;; let _SYSZ_INS_VCTZ = 1758;; let _SYSZ_INS_VCTZB = 1759;; let _SYSZ_INS_VCTZF = 1760;; let _SYSZ_INS_VCTZG = 1761;; let _SYSZ_INS_VCTZH = 1762;; let _SYSZ_INS_VCVB = 1763;; let _SYSZ_INS_VCVBG = 1764;; let _SYSZ_INS_VCVD = 1765;; let _SYSZ_INS_VCVDG = 1766;; let _SYSZ_INS_VDP = 1767;; let _SYSZ_INS_VEC = 1768;; let _SYSZ_INS_VECB = 1769;; let _SYSZ_INS_VECF = 1770;; let _SYSZ_INS_VECG = 1771;; let _SYSZ_INS_VECH = 1772;; let _SYSZ_INS_VECL = 1773;; let _SYSZ_INS_VECLB = 1774;; let _SYSZ_INS_VECLF = 1775;; let _SYSZ_INS_VECLG = 1776;; let _SYSZ_INS_VECLH = 1777;; let _SYSZ_INS_VERIM = 1778;; let _SYSZ_INS_VERIMB = 1779;; let _SYSZ_INS_VERIMF = 1780;; let _SYSZ_INS_VERIMG = 1781;; let _SYSZ_INS_VERIMH = 1782;; let _SYSZ_INS_VERLL = 1783;; let _SYSZ_INS_VERLLB = 1784;; let _SYSZ_INS_VERLLF = 1785;; let _SYSZ_INS_VERLLG = 1786;; let _SYSZ_INS_VERLLH = 1787;; let _SYSZ_INS_VERLLV = 1788;; let _SYSZ_INS_VERLLVB = 1789;; let _SYSZ_INS_VERLLVF = 1790;; let _SYSZ_INS_VERLLVG = 1791;; let _SYSZ_INS_VERLLVH = 1792;; let _SYSZ_INS_VESL = 1793;; let _SYSZ_INS_VESLB = 1794;; let _SYSZ_INS_VESLF = 1795;; let _SYSZ_INS_VESLG = 1796;; let _SYSZ_INS_VESLH = 1797;; let _SYSZ_INS_VESLV = 1798;; let _SYSZ_INS_VESLVB = 1799;; let _SYSZ_INS_VESLVF = 1800;; let _SYSZ_INS_VESLVG = 1801;; let _SYSZ_INS_VESLVH = 1802;; let _SYSZ_INS_VESRA = 1803;; let _SYSZ_INS_VESRAB = 1804;; let _SYSZ_INS_VESRAF = 1805;; let _SYSZ_INS_VESRAG = 1806;; let _SYSZ_INS_VESRAH = 1807;; let _SYSZ_INS_VESRAV = 1808;; let _SYSZ_INS_VESRAVB = 1809;; let _SYSZ_INS_VESRAVF = 1810;; let _SYSZ_INS_VESRAVG = 1811;; let _SYSZ_INS_VESRAVH = 1812;; let _SYSZ_INS_VESRL = 1813;; let _SYSZ_INS_VESRLB = 1814;; let _SYSZ_INS_VESRLF = 1815;; let _SYSZ_INS_VESRLG = 1816;; let _SYSZ_INS_VESRLH = 1817;; let _SYSZ_INS_VESRLV = 1818;; let _SYSZ_INS_VESRLVB = 1819;; let _SYSZ_INS_VESRLVF = 1820;; let _SYSZ_INS_VESRLVG = 1821;; let _SYSZ_INS_VESRLVH = 1822;; let _SYSZ_INS_VFA = 1823;; let _SYSZ_INS_VFADB = 1824;; let _SYSZ_INS_VFAE = 1825;; let _SYSZ_INS_VFAEB = 1826;; let _SYSZ_INS_VFAEBS = 1827;; let _SYSZ_INS_VFAEF = 1828;; let _SYSZ_INS_VFAEFS = 1829;; let _SYSZ_INS_VFAEH = 1830;; let _SYSZ_INS_VFAEHS = 1831;; let _SYSZ_INS_VFAEZB = 1832;; let _SYSZ_INS_VFAEZBS = 1833;; let _SYSZ_INS_VFAEZF = 1834;; let _SYSZ_INS_VFAEZFS = 1835;; let _SYSZ_INS_VFAEZH = 1836;; let _SYSZ_INS_VFAEZHS = 1837;; let _SYSZ_INS_VFASB = 1838;; let _SYSZ_INS_VFCE = 1839;; let _SYSZ_INS_VFCEDB = 1840;; let _SYSZ_INS_VFCEDBS = 1841;; let _SYSZ_INS_VFCESB = 1842;; let _SYSZ_INS_VFCESBS = 1843;; let _SYSZ_INS_VFCH = 1844;; let _SYSZ_INS_VFCHDB = 1845;; let _SYSZ_INS_VFCHDBS = 1846;; let _SYSZ_INS_VFCHE = 1847;; let _SYSZ_INS_VFCHEDB = 1848;; let _SYSZ_INS_VFCHEDBS = 1849;; let _SYSZ_INS_VFCHESB = 1850;; let _SYSZ_INS_VFCHESBS = 1851;; let _SYSZ_INS_VFCHSB = 1852;; let _SYSZ_INS_VFCHSBS = 1853;; let _SYSZ_INS_VFD = 1854;; let _SYSZ_INS_VFDDB = 1855;; let _SYSZ_INS_VFDSB = 1856;; let _SYSZ_INS_VFEE = 1857;; let _SYSZ_INS_VFEEB = 1858;; let _SYSZ_INS_VFEEBS = 1859;; let _SYSZ_INS_VFEEF = 1860;; let _SYSZ_INS_VFEEFS = 1861;; let _SYSZ_INS_VFEEH = 1862;; let _SYSZ_INS_VFEEHS = 1863;; let _SYSZ_INS_VFEEZB = 1864;; let _SYSZ_INS_VFEEZBS = 1865;; let _SYSZ_INS_VFEEZF = 1866;; let _SYSZ_INS_VFEEZFS = 1867;; let _SYSZ_INS_VFEEZH = 1868;; let _SYSZ_INS_VFEEZHS = 1869;; let _SYSZ_INS_VFENE = 1870;; let _SYSZ_INS_VFENEB = 1871;; let _SYSZ_INS_VFENEBS = 1872;; let _SYSZ_INS_VFENEF = 1873;; let _SYSZ_INS_VFENEFS = 1874;; let _SYSZ_INS_VFENEH = 1875;; let _SYSZ_INS_VFENEHS = 1876;; let _SYSZ_INS_VFENEZB = 1877;; let _SYSZ_INS_VFENEZBS = 1878;; let _SYSZ_INS_VFENEZF = 1879;; let _SYSZ_INS_VFENEZFS = 1880;; let _SYSZ_INS_VFENEZH = 1881;; let _SYSZ_INS_VFENEZHS = 1882;; let _SYSZ_INS_VFI = 1883;; let _SYSZ_INS_VFIDB = 1884;; let _SYSZ_INS_VFISB = 1885;; let _SYSZ_INS_VFKEDB = 1886;; let _SYSZ_INS_VFKEDBS = 1887;; let _SYSZ_INS_VFKESB = 1888;; let _SYSZ_INS_VFKESBS = 1889;; let _SYSZ_INS_VFKHDB = 1890;; let _SYSZ_INS_VFKHDBS = 1891;; let _SYSZ_INS_VFKHEDB = 1892;; let _SYSZ_INS_VFKHEDBS = 1893;; let _SYSZ_INS_VFKHESB = 1894;; let _SYSZ_INS_VFKHESBS = 1895;; let _SYSZ_INS_VFKHSB = 1896;; let _SYSZ_INS_VFKHSBS = 1897;; let _SYSZ_INS_VFLCDB = 1898;; let _SYSZ_INS_VFLCSB = 1899;; let _SYSZ_INS_VFLL = 1900;; let _SYSZ_INS_VFLLS = 1901;; let _SYSZ_INS_VFLNDB = 1902;; let _SYSZ_INS_VFLNSB = 1903;; let _SYSZ_INS_VFLPDB = 1904;; let _SYSZ_INS_VFLPSB = 1905;; let _SYSZ_INS_VFLR = 1906;; let _SYSZ_INS_VFLRD = 1907;; let _SYSZ_INS_VFM = 1908;; let _SYSZ_INS_VFMA = 1909;; let _SYSZ_INS_VFMADB = 1910;; let _SYSZ_INS_VFMASB = 1911;; let _SYSZ_INS_VFMAX = 1912;; let _SYSZ_INS_VFMAXDB = 1913;; let _SYSZ_INS_VFMAXSB = 1914;; let _SYSZ_INS_VFMDB = 1915;; let _SYSZ_INS_VFMIN = 1916;; let _SYSZ_INS_VFMINDB = 1917;; let _SYSZ_INS_VFMINSB = 1918;; let _SYSZ_INS_VFMS = 1919;; let _SYSZ_INS_VFMSB = 1920;; let _SYSZ_INS_VFMSDB = 1921;; let _SYSZ_INS_VFMSSB = 1922;; let _SYSZ_INS_VFNMA = 1923;; let _SYSZ_INS_VFNMADB = 1924;; let _SYSZ_INS_VFNMASB = 1925;; let _SYSZ_INS_VFNMS = 1926;; let _SYSZ_INS_VFNMSDB = 1927;; let _SYSZ_INS_VFNMSSB = 1928;; let _SYSZ_INS_VFPSO = 1929;; let _SYSZ_INS_VFPSODB = 1930;; let _SYSZ_INS_VFPSOSB = 1931;; let _SYSZ_INS_VFS = 1932;; let _SYSZ_INS_VFSDB = 1933;; let _SYSZ_INS_VFSQ = 1934;; let _SYSZ_INS_VFSQDB = 1935;; let _SYSZ_INS_VFSQSB = 1936;; let _SYSZ_INS_VFSSB = 1937;; let _SYSZ_INS_VFTCI = 1938;; let _SYSZ_INS_VFTCIDB = 1939;; let _SYSZ_INS_VFTCISB = 1940;; let _SYSZ_INS_VGBM = 1941;; let _SYSZ_INS_VGEF = 1942;; let _SYSZ_INS_VGEG = 1943;; let _SYSZ_INS_VGFM = 1944;; let _SYSZ_INS_VGFMA = 1945;; let _SYSZ_INS_VGFMAB = 1946;; let _SYSZ_INS_VGFMAF = 1947;; let _SYSZ_INS_VGFMAG = 1948;; let _SYSZ_INS_VGFMAH = 1949;; let _SYSZ_INS_VGFMB = 1950;; let _SYSZ_INS_VGFMF = 1951;; let _SYSZ_INS_VGFMG = 1952;; let _SYSZ_INS_VGFMH = 1953;; let _SYSZ_INS_VGM = 1954;; let _SYSZ_INS_VGMB = 1955;; let _SYSZ_INS_VGMF = 1956;; let _SYSZ_INS_VGMG = 1957;; let _SYSZ_INS_VGMH = 1958;; let _SYSZ_INS_VISTR = 1959;; let _SYSZ_INS_VISTRB = 1960;; let _SYSZ_INS_VISTRBS = 1961;; let _SYSZ_INS_VISTRF = 1962;; let _SYSZ_INS_VISTRFS = 1963;; let _SYSZ_INS_VISTRH = 1964;; let _SYSZ_INS_VISTRHS = 1965;; let _SYSZ_INS_VL = 1966;; let _SYSZ_INS_VLBB = 1967;; let _SYSZ_INS_VLC = 1968;; let _SYSZ_INS_VLCB = 1969;; let _SYSZ_INS_VLCF = 1970;; let _SYSZ_INS_VLCG = 1971;; let _SYSZ_INS_VLCH = 1972;; let _SYSZ_INS_VLDE = 1973;; let _SYSZ_INS_VLDEB = 1974;; let _SYSZ_INS_VLEB = 1975;; let _SYSZ_INS_VLED = 1976;; let _SYSZ_INS_VLEDB = 1977;; let _SYSZ_INS_VLEF = 1978;; let _SYSZ_INS_VLEG = 1979;; let _SYSZ_INS_VLEH = 1980;; let _SYSZ_INS_VLEIB = 1981;; let _SYSZ_INS_VLEIF = 1982;; let _SYSZ_INS_VLEIG = 1983;; let _SYSZ_INS_VLEIH = 1984;; let _SYSZ_INS_VLGV = 1985;; let _SYSZ_INS_VLGVB = 1986;; let _SYSZ_INS_VLGVF = 1987;; let _SYSZ_INS_VLGVG = 1988;; let _SYSZ_INS_VLGVH = 1989;; let _SYSZ_INS_VLIP = 1990;; let _SYSZ_INS_VLL = 1991;; let _SYSZ_INS_VLLEZ = 1992;; let _SYSZ_INS_VLLEZB = 1993;; let _SYSZ_INS_VLLEZF = 1994;; let _SYSZ_INS_VLLEZG = 1995;; let _SYSZ_INS_VLLEZH = 1996;; let _SYSZ_INS_VLLEZLF = 1997;; let _SYSZ_INS_VLM = 1998;; let _SYSZ_INS_VLP = 1999;; let _SYSZ_INS_VLPB = 2000;; let _SYSZ_INS_VLPF = 2001;; let _SYSZ_INS_VLPG = 2002;; let _SYSZ_INS_VLPH = 2003;; let _SYSZ_INS_VLR = 2004;; let _SYSZ_INS_VLREP = 2005;; let _SYSZ_INS_VLREPB = 2006;; let _SYSZ_INS_VLREPF = 2007;; let _SYSZ_INS_VLREPG = 2008;; let _SYSZ_INS_VLREPH = 2009;; let _SYSZ_INS_VLRL = 2010;; let _SYSZ_INS_VLRLR = 2011;; let _SYSZ_INS_VLVG = 2012;; let _SYSZ_INS_VLVGB = 2013;; let _SYSZ_INS_VLVGF = 2014;; let _SYSZ_INS_VLVGG = 2015;; let _SYSZ_INS_VLVGH = 2016;; let _SYSZ_INS_VLVGP = 2017;; let _SYSZ_INS_VMAE = 2018;; let _SYSZ_INS_VMAEB = 2019;; let _SYSZ_INS_VMAEF = 2020;; let _SYSZ_INS_VMAEH = 2021;; let _SYSZ_INS_VMAH = 2022;; let _SYSZ_INS_VMAHB = 2023;; let _SYSZ_INS_VMAHF = 2024;; let _SYSZ_INS_VMAHH = 2025;; let _SYSZ_INS_VMAL = 2026;; let _SYSZ_INS_VMALB = 2027;; let _SYSZ_INS_VMALE = 2028;; let _SYSZ_INS_VMALEB = 2029;; let _SYSZ_INS_VMALEF = 2030;; let _SYSZ_INS_VMALEH = 2031;; let _SYSZ_INS_VMALF = 2032;; let _SYSZ_INS_VMALH = 2033;; let _SYSZ_INS_VMALHB = 2034;; let _SYSZ_INS_VMALHF = 2035;; let _SYSZ_INS_VMALHH = 2036;; let _SYSZ_INS_VMALHW = 2037;; let _SYSZ_INS_VMALO = 2038;; let _SYSZ_INS_VMALOB = 2039;; let _SYSZ_INS_VMALOF = 2040;; let _SYSZ_INS_VMALOH = 2041;; let _SYSZ_INS_VMAO = 2042;; let _SYSZ_INS_VMAOB = 2043;; let _SYSZ_INS_VMAOF = 2044;; let _SYSZ_INS_VMAOH = 2045;; let _SYSZ_INS_VME = 2046;; let _SYSZ_INS_VMEB = 2047;; let _SYSZ_INS_VMEF = 2048;; let _SYSZ_INS_VMEH = 2049;; let _SYSZ_INS_VMH = 2050;; let _SYSZ_INS_VMHB = 2051;; let _SYSZ_INS_VMHF = 2052;; let _SYSZ_INS_VMHH = 2053;; let _SYSZ_INS_VML = 2054;; let _SYSZ_INS_VMLB = 2055;; let _SYSZ_INS_VMLE = 2056;; let _SYSZ_INS_VMLEB = 2057;; let _SYSZ_INS_VMLEF = 2058;; let _SYSZ_INS_VMLEH = 2059;; let _SYSZ_INS_VMLF = 2060;; let _SYSZ_INS_VMLH = 2061;; let _SYSZ_INS_VMLHB = 2062;; let _SYSZ_INS_VMLHF = 2063;; let _SYSZ_INS_VMLHH = 2064;; let _SYSZ_INS_VMLHW = 2065;; let _SYSZ_INS_VMLO = 2066;; let _SYSZ_INS_VMLOB = 2067;; let _SYSZ_INS_VMLOF = 2068;; let _SYSZ_INS_VMLOH = 2069;; let _SYSZ_INS_VMN = 2070;; let _SYSZ_INS_VMNB = 2071;; let _SYSZ_INS_VMNF = 2072;; let _SYSZ_INS_VMNG = 2073;; let _SYSZ_INS_VMNH = 2074;; let _SYSZ_INS_VMNL = 2075;; let _SYSZ_INS_VMNLB = 2076;; let _SYSZ_INS_VMNLF = 2077;; let _SYSZ_INS_VMNLG = 2078;; let _SYSZ_INS_VMNLH = 2079;; let _SYSZ_INS_VMO = 2080;; let _SYSZ_INS_VMOB = 2081;; let _SYSZ_INS_VMOF = 2082;; let _SYSZ_INS_VMOH = 2083;; let _SYSZ_INS_VMP = 2084;; let _SYSZ_INS_VMRH = 2085;; let _SYSZ_INS_VMRHB = 2086;; let _SYSZ_INS_VMRHF = 2087;; let _SYSZ_INS_VMRHG = 2088;; let _SYSZ_INS_VMRHH = 2089;; let _SYSZ_INS_VMRL = 2090;; let _SYSZ_INS_VMRLB = 2091;; let _SYSZ_INS_VMRLF = 2092;; let _SYSZ_INS_VMRLG = 2093;; let _SYSZ_INS_VMRLH = 2094;; let _SYSZ_INS_VMSL = 2095;; let _SYSZ_INS_VMSLG = 2096;; let _SYSZ_INS_VMSP = 2097;; let _SYSZ_INS_VMX = 2098;; let _SYSZ_INS_VMXB = 2099;; let _SYSZ_INS_VMXF = 2100;; let _SYSZ_INS_VMXG = 2101;; let _SYSZ_INS_VMXH = 2102;; let _SYSZ_INS_VMXL = 2103;; let _SYSZ_INS_VMXLB = 2104;; let _SYSZ_INS_VMXLF = 2105;; let _SYSZ_INS_VMXLG = 2106;; let _SYSZ_INS_VMXLH = 2107;; let _SYSZ_INS_VN = 2108;; let _SYSZ_INS_VNC = 2109;; let _SYSZ_INS_VNN = 2110;; let _SYSZ_INS_VNO = 2111;; let _SYSZ_INS_VNX = 2112;; let _SYSZ_INS_VO = 2113;; let _SYSZ_INS_VOC = 2114;; let _SYSZ_INS_VONE = 2115;; let _SYSZ_INS_VPDI = 2116;; let _SYSZ_INS_VPERM = 2117;; let _SYSZ_INS_VPK = 2118;; let _SYSZ_INS_VPKF = 2119;; let _SYSZ_INS_VPKG = 2120;; let _SYSZ_INS_VPKH = 2121;; let _SYSZ_INS_VPKLS = 2122;; let _SYSZ_INS_VPKLSF = 2123;; let _SYSZ_INS_VPKLSFS = 2124;; let _SYSZ_INS_VPKLSG = 2125;; let _SYSZ_INS_VPKLSGS = 2126;; let _SYSZ_INS_VPKLSH = 2127;; let _SYSZ_INS_VPKLSHS = 2128;; let _SYSZ_INS_VPKS = 2129;; let _SYSZ_INS_VPKSF = 2130;; let _SYSZ_INS_VPKSFS = 2131;; let _SYSZ_INS_VPKSG = 2132;; let _SYSZ_INS_VPKSGS = 2133;; let _SYSZ_INS_VPKSH = 2134;; let _SYSZ_INS_VPKSHS = 2135;; let _SYSZ_INS_VPKZ = 2136;; let _SYSZ_INS_VPOPCT = 2137;; let _SYSZ_INS_VPOPCTB = 2138;; let _SYSZ_INS_VPOPCTF = 2139;; let _SYSZ_INS_VPOPCTG = 2140;; let _SYSZ_INS_VPOPCTH = 2141;; let _SYSZ_INS_VPSOP = 2142;; let _SYSZ_INS_VREP = 2143;; let _SYSZ_INS_VREPB = 2144;; let _SYSZ_INS_VREPF = 2145;; let _SYSZ_INS_VREPG = 2146;; let _SYSZ_INS_VREPH = 2147;; let _SYSZ_INS_VREPI = 2148;; let _SYSZ_INS_VREPIB = 2149;; let _SYSZ_INS_VREPIF = 2150;; let _SYSZ_INS_VREPIG = 2151;; let _SYSZ_INS_VREPIH = 2152;; let _SYSZ_INS_VRP = 2153;; let _SYSZ_INS_VS = 2154;; let _SYSZ_INS_VSB = 2155;; let _SYSZ_INS_VSBCBI = 2156;; let _SYSZ_INS_VSBCBIQ = 2157;; let _SYSZ_INS_VSBI = 2158;; let _SYSZ_INS_VSBIQ = 2159;; let _SYSZ_INS_VSCBI = 2160;; let _SYSZ_INS_VSCBIB = 2161;; let _SYSZ_INS_VSCBIF = 2162;; let _SYSZ_INS_VSCBIG = 2163;; let _SYSZ_INS_VSCBIH = 2164;; let _SYSZ_INS_VSCBIQ = 2165;; let _SYSZ_INS_VSCEF = 2166;; let _SYSZ_INS_VSCEG = 2167;; let _SYSZ_INS_VSDP = 2168;; let _SYSZ_INS_VSEG = 2169;; let _SYSZ_INS_VSEGB = 2170;; let _SYSZ_INS_VSEGF = 2171;; let _SYSZ_INS_VSEGH = 2172;; let _SYSZ_INS_VSEL = 2173;; let _SYSZ_INS_VSF = 2174;; let _SYSZ_INS_VSG = 2175;; let _SYSZ_INS_VSH = 2176;; let _SYSZ_INS_VSL = 2177;; let _SYSZ_INS_VSLB = 2178;; let _SYSZ_INS_VSLDB = 2179;; let _SYSZ_INS_VSP = 2180;; let _SYSZ_INS_VSQ = 2181;; let _SYSZ_INS_VSRA = 2182;; let _SYSZ_INS_VSRAB = 2183;; let _SYSZ_INS_VSRL = 2184;; let _SYSZ_INS_VSRLB = 2185;; let _SYSZ_INS_VSRP = 2186;; let _SYSZ_INS_VST = 2187;; let _SYSZ_INS_VSTEB = 2188;; let _SYSZ_INS_VSTEF = 2189;; let _SYSZ_INS_VSTEG = 2190;; let _SYSZ_INS_VSTEH = 2191;; let _SYSZ_INS_VSTL = 2192;; let _SYSZ_INS_VSTM = 2193;; let _SYSZ_INS_VSTRC = 2194;; let _SYSZ_INS_VSTRCB = 2195;; let _SYSZ_INS_VSTRCBS = 2196;; let _SYSZ_INS_VSTRCF = 2197;; let _SYSZ_INS_VSTRCFS = 2198;; let _SYSZ_INS_VSTRCH = 2199;; let _SYSZ_INS_VSTRCHS = 2200;; let _SYSZ_INS_VSTRCZB = 2201;; let _SYSZ_INS_VSTRCZBS = 2202;; let _SYSZ_INS_VSTRCZF = 2203;; let _SYSZ_INS_VSTRCZFS = 2204;; let _SYSZ_INS_VSTRCZH = 2205;; let _SYSZ_INS_VSTRCZHS = 2206;; let _SYSZ_INS_VSTRL = 2207;; let _SYSZ_INS_VSTRLR = 2208;; let _SYSZ_INS_VSUM = 2209;; let _SYSZ_INS_VSUMB = 2210;; let _SYSZ_INS_VSUMG = 2211;; let _SYSZ_INS_VSUMGF = 2212;; let _SYSZ_INS_VSUMGH = 2213;; let _SYSZ_INS_VSUMH = 2214;; let _SYSZ_INS_VSUMQ = 2215;; let _SYSZ_INS_VSUMQF = 2216;; let _SYSZ_INS_VSUMQG = 2217;; let _SYSZ_INS_VTM = 2218;; let _SYSZ_INS_VTP = 2219;; let _SYSZ_INS_VUPH = 2220;; let _SYSZ_INS_VUPHB = 2221;; let _SYSZ_INS_VUPHF = 2222;; let _SYSZ_INS_VUPHH = 2223;; let _SYSZ_INS_VUPKZ = 2224;; let _SYSZ_INS_VUPL = 2225;; let _SYSZ_INS_VUPLB = 2226;; let _SYSZ_INS_VUPLF = 2227;; let _SYSZ_INS_VUPLH = 2228;; let _SYSZ_INS_VUPLHB = 2229;; let _SYSZ_INS_VUPLHF = 2230;; let _SYSZ_INS_VUPLHH = 2231;; let _SYSZ_INS_VUPLHW = 2232;; let _SYSZ_INS_VUPLL = 2233;; let _SYSZ_INS_VUPLLB = 2234;; let _SYSZ_INS_VUPLLF = 2235;; let _SYSZ_INS_VUPLLH = 2236;; let _SYSZ_INS_VX = 2237;; let _SYSZ_INS_VZERO = 2238;; let _SYSZ_INS_WCDGB = 2239;; let _SYSZ_INS_WCDLGB = 2240;; let _SYSZ_INS_WCGDB = 2241;; let _SYSZ_INS_WCLGDB = 2242;; let _SYSZ_INS_WFADB = 2243;; let _SYSZ_INS_WFASB = 2244;; let _SYSZ_INS_WFAXB = 2245;; let _SYSZ_INS_WFC = 2246;; let _SYSZ_INS_WFCDB = 2247;; let _SYSZ_INS_WFCEDB = 2248;; let _SYSZ_INS_WFCEDBS = 2249;; let _SYSZ_INS_WFCESB = 2250;; let _SYSZ_INS_WFCESBS = 2251;; let _SYSZ_INS_WFCEXB = 2252;; let _SYSZ_INS_WFCEXBS = 2253;; let _SYSZ_INS_WFCHDB = 2254;; let _SYSZ_INS_WFCHDBS = 2255;; let _SYSZ_INS_WFCHEDB = 2256;; let _SYSZ_INS_WFCHEDBS = 2257;; let _SYSZ_INS_WFCHESB = 2258;; let _SYSZ_INS_WFCHESBS = 2259;; let _SYSZ_INS_WFCHEXB = 2260;; let _SYSZ_INS_WFCHEXBS = 2261;; let _SYSZ_INS_WFCHSB = 2262;; let _SYSZ_INS_WFCHSBS = 2263;; let _SYSZ_INS_WFCHXB = 2264;; let _SYSZ_INS_WFCHXBS = 2265;; let _SYSZ_INS_WFCSB = 2266;; let _SYSZ_INS_WFCXB = 2267;; let _SYSZ_INS_WFDDB = 2268;; let _SYSZ_INS_WFDSB = 2269;; let _SYSZ_INS_WFDXB = 2270;; let _SYSZ_INS_WFIDB = 2271;; let _SYSZ_INS_WFISB = 2272;; let _SYSZ_INS_WFIXB = 2273;; let _SYSZ_INS_WFK = 2274;; let _SYSZ_INS_WFKDB = 2275;; let _SYSZ_INS_WFKEDB = 2276;; let _SYSZ_INS_WFKEDBS = 2277;; let _SYSZ_INS_WFKESB = 2278;; let _SYSZ_INS_WFKESBS = 2279;; let _SYSZ_INS_WFKEXB = 2280;; let _SYSZ_INS_WFKEXBS = 2281;; let _SYSZ_INS_WFKHDB = 2282;; let _SYSZ_INS_WFKHDBS = 2283;; let _SYSZ_INS_WFKHEDB = 2284;; let _SYSZ_INS_WFKHEDBS = 2285;; let _SYSZ_INS_WFKHESB = 2286;; let _SYSZ_INS_WFKHESBS = 2287;; let _SYSZ_INS_WFKHEXB = 2288;; let _SYSZ_INS_WFKHEXBS = 2289;; let _SYSZ_INS_WFKHSB = 2290;; let _SYSZ_INS_WFKHSBS = 2291;; let _SYSZ_INS_WFKHXB = 2292;; let _SYSZ_INS_WFKHXBS = 2293;; let _SYSZ_INS_WFKSB = 2294;; let _SYSZ_INS_WFKXB = 2295;; let _SYSZ_INS_WFLCDB = 2296;; let _SYSZ_INS_WFLCSB = 2297;; let _SYSZ_INS_WFLCXB = 2298;; let _SYSZ_INS_WFLLD = 2299;; let _SYSZ_INS_WFLLS = 2300;; let _SYSZ_INS_WFLNDB = 2301;; let _SYSZ_INS_WFLNSB = 2302;; let _SYSZ_INS_WFLNXB = 2303;; let _SYSZ_INS_WFLPDB = 2304;; let _SYSZ_INS_WFLPSB = 2305;; let _SYSZ_INS_WFLPXB = 2306;; let _SYSZ_INS_WFLRD = 2307;; let _SYSZ_INS_WFLRX = 2308;; let _SYSZ_INS_WFMADB = 2309;; let _SYSZ_INS_WFMASB = 2310;; let _SYSZ_INS_WFMAXB = 2311;; let _SYSZ_INS_WFMAXDB = 2312;; let _SYSZ_INS_WFMAXSB = 2313;; let _SYSZ_INS_WFMAXXB = 2314;; let _SYSZ_INS_WFMDB = 2315;; let _SYSZ_INS_WFMINDB = 2316;; let _SYSZ_INS_WFMINSB = 2317;; let _SYSZ_INS_WFMINXB = 2318;; let _SYSZ_INS_WFMSB = 2319;; let _SYSZ_INS_WFMSDB = 2320;; let _SYSZ_INS_WFMSSB = 2321;; let _SYSZ_INS_WFMSXB = 2322;; let _SYSZ_INS_WFMXB = 2323;; let _SYSZ_INS_WFNMADB = 2324;; let _SYSZ_INS_WFNMASB = 2325;; let _SYSZ_INS_WFNMAXB = 2326;; let _SYSZ_INS_WFNMSDB = 2327;; let _SYSZ_INS_WFNMSSB = 2328;; let _SYSZ_INS_WFNMSXB = 2329;; let _SYSZ_INS_WFPSODB = 2330;; let _SYSZ_INS_WFPSOSB = 2331;; let _SYSZ_INS_WFPSOXB = 2332;; let _SYSZ_INS_WFSDB = 2333;; let _SYSZ_INS_WFSQDB = 2334;; let _SYSZ_INS_WFSQSB = 2335;; let _SYSZ_INS_WFSQXB = 2336;; let _SYSZ_INS_WFSSB = 2337;; let _SYSZ_INS_WFSXB = 2338;; let _SYSZ_INS_WFTCIDB = 2339;; let _SYSZ_INS_WFTCISB = 2340;; let _SYSZ_INS_WFTCIXB = 2341;; let _SYSZ_INS_WLDEB = 2342;; let _SYSZ_INS_WLEDB = 2343;; let _SYSZ_INS_XSCH = 2344;; let _SYSZ_INS_ZAP = 2345;; let _SYSZ_INS_ENDING = 2346;; let _SYSZ_GRP_INVALID = 0;; let _SYSZ_GRP_JUMP = 1;; let _SYSZ_GRP_DISTINCTOPS = 128;; let _SYSZ_GRP_FPEXTENSION = 129;; let _SYSZ_GRP_HIGHWORD = 130;; let _SYSZ_GRP_INTERLOCKEDACCESS1 = 131;; let _SYSZ_GRP_LOADSTOREONCOND = 132;; let _SYSZ_GRP_DFPPACKEDCONVERSION = 133;; let _SYSZ_GRP_DFPZONEDCONVERSION = 134;; let _SYSZ_GRP_ENHANCEDDAT2 = 135;; let _SYSZ_GRP_EXECUTIONHINT = 136;; let _SYSZ_GRP_GUARDEDSTORAGE = 137;; let _SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138;; let _SYSZ_GRP_LOADANDTRAP = 139;; let _SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140;; let _SYSZ_GRP_LOADSTOREONCOND2 = 141;; let _SYSZ_GRP_MESSAGESECURITYASSIST3 = 142;; let _SYSZ_GRP_MESSAGESECURITYASSIST4 = 143;; let _SYSZ_GRP_MESSAGESECURITYASSIST5 = 144;; let _SYSZ_GRP_MESSAGESECURITYASSIST7 = 145;; let _SYSZ_GRP_MESSAGESECURITYASSIST8 = 146;; let _SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147;; let _SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148;; let _SYSZ_GRP_NOVECTOR = 149;; let _SYSZ_GRP_POPULATIONCOUNT = 150;; let _SYSZ_GRP_PROCESSORASSIST = 151;; let _SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152;; let _SYSZ_GRP_TRANSACTIONALEXECUTION = 153;; let _SYSZ_GRP_VECTOR = 154;; let _SYSZ_GRP_VECTORENHANCEMENTS1 = 155;; let _SYSZ_GRP_VECTORPACKEDDECIMAL = 156;; let _SYSZ_GRP_ENDING = 157;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_arm.ml000064400000000000000000000063620072674642500212520ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Printf open Capstone open Arm open Arm_const let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3";; let _ARM_CODE2 = "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c";; let _THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0";; let _THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1";; let all_tests = [ (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM"); (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "Thumb"); (CS_ARCH_ARM, [CS_MODE_THUMB], _ARM_CODE2, "Thumb-mixed"); (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "Thumb-2"); ];; let print_op handle i op = ( match op.value with | ARM_OP_INVALID _ -> (); (* this would never happens *) | ARM_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | ARM_OP_CIMM imm -> printf "\t\top[%d]: C-IMM = %u\n" i imm; | ARM_OP_PIMM imm -> printf "\t\top[%d]: P-IMM = %u\n" i imm; | ARM_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | ARM_OP_FP fp -> printf "\t\top[%d]: FP = %f\n" i fp; | ARM_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then printf "\t\t\toperands[%u].mem.index: REG = %s\n" i (cs_reg_name handle mem.index); if mem.scale != 1 then printf "\t\t\toperands[%u].mem.scale: %d\n" i mem.scale; if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; if mem.lshift != 0 then printf "\t\t\toperands[%u].mem.lshift: 0x%x\n" i mem.lshift; ); | ARM_OP_SETEND sd -> printf "\t\top[%d]: SETEND = %u\n" i sd; ); if op.shift.shift_type != _ARM_SFT_INVALID && op.shift.shift_value > 0 then printf "\t\t\tShift: type = %u, value = %u\n" op.shift.shift_type op.shift.shift_value; ();; let print_detail handle insn = match insn.arch with | CS_INFO_ARM arm -> ( if arm.cc != _ARM_CC_AL && arm.cc != _ARM_CC_INVALID then printf "\tCode condition: %u\n" arm.cc; if arm.update_flags then printf "\tUpdate-flags: True\n"; if arm.writeback then printf "\tWriteback: True\n"; (* print all operands info (type & value) *) if (Array.length arm.operands) > 0 then ( printf "\top_count: %d\n" (Array.length arm.operands); Array.iteri (print_op handle) arm.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_arm64.ml000064400000000000000000000057720072674642500214300ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Printf open Capstone open Arm64 open Arm64_const let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b";; let all_tests = [ (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64"); ];; let print_op handle i op = ( match op.value with | ARM64_OP_INVALID _ -> (); (* this would never happens *) | ARM64_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | ARM64_OP_CIMM imm -> printf "\t\top[%d]: C-IMM = %u\n" i imm; | ARM64_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | ARM64_OP_FP fp -> printf "\t\top[%d]: FP = %f\n" i fp; | ARM64_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then printf "\t\t\toperands[%u].mem.index: REG = %s\n" i (cs_reg_name handle mem.index); if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; ); | ARM64_OP_REG_MRS reg -> printf "\t\top[%d]: REG_MRS = %u\n" i reg; | ARM64_OP_REG_MSR reg -> printf "\t\top[%d]: REG_MSR = %u\n" i reg; | ARM64_OP_PSTATE v -> printf "\t\top[%d]: PSTATE = %u\n" i v; | ARM64_OP_SYS v -> printf "\t\top[%d]: SYS = %u\n" i v; | ARM64_OP_PREFETCH v -> printf "\t\top[%d]: PREFETCH = %u\n" i v; | ARM64_OP_BARRIER v -> printf "\t\top[%d]: BARRIER = %u\n" i v; ); if op.shift.shift_type != _ARM64_SFT_INVALID && op.shift.shift_value > 0 then printf "\t\t\tShift: type = %u, value = %u\n" op.shift.shift_type op.shift.shift_value; if op.ext != _ARM64_EXT_INVALID then printf "\t\t\tExt: %u\n" op.ext; ();; let print_detail handle insn = match insn.arch with | CS_INFO_ARM64 arm64 -> ( if arm64.cc != _ARM64_CC_AL && arm64.cc != _ARM64_CC_INVALID then printf "\tCode condition: %u\n" arm64.cc; if arm64.update_flags then printf "\tUpdate-flags: True\n"; if arm64.writeback then printf "\tWriteback: True\n"; (* print all operands info (type & value) *) if (Array.length arm64.operands) > 0 then ( printf "\top_count: %d\n" (Array.length arm64.operands); Array.iteri (print_op handle) arm64.operands; ); printf "\n"; ) | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_basic.ml000064400000000000000000000071530072674642500215530ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Printf open List open Capstone let _X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; let _X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; let _X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00";; let _ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3";; let _ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3";; let _THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68";; let _THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88";; let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";; let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";; let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9";; let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";; let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";; let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";; let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";; let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";; let all_tests = [ (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0L); (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", _CS_OPT_SYNTAX_ATT); (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0L); (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0L); (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM", 0L); (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON", 0L); (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0L); (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0L); (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0L); (CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0L); (CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0L); (CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0L); (CS_ARCH_PPC, [CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64, print register with number only", 0L); (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0L); (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0L); (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0L); (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore", 0L); ];; let print_insn insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str;; let print_arch x = let (arch, mode, code, comment, syntax) = x in let handle = cs_open arch mode in ( if syntax != 0L then ( let err = cs_option handle CS_OPT_SYNTAX syntax in match err with | _ -> (); ); let insns = cs_disasm handle code 0x1000L 0L in ( printf "*************\n"; printf "Platform: %s\n" comment; List.iter print_insn insns; ); match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; );; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_detail.ml000064400000000000000000000101260072674642500217260ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Printf open List open Capstone let _X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; let _X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; let _X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00";; let _ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3";; let _ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3";; let _THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68";; let _THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88";; let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";; let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";; let _ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9";; let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";; let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";; let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";; let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";; let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";; let all_tests = [ (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0); (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", 0); (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0); (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0); (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE, "ARM", 0); (CS_ARCH_ARM, [CS_MODE_ARM], _ARM_CODE2, "ARM: Cortex-A15 + NEON", 0); (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE, "THUMB", 0); (CS_ARCH_ARM, [CS_MODE_THUMB], _THUMB_CODE2, "THUMB-2", 0); (CS_ARCH_ARM64, [CS_MODE_ARM], _ARM64_CODE, "ARM-64", 0); (CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)", 0); (CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0); (CS_ARCH_PPC, [CS_MODE_64; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64", 0); (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc", 0); (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9", 0); (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ", 0); (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore", 0); ];; let print_detail handle insn = (* print immediate operands *) if (Array.length insn.regs_read) > 0 then begin printf "\tImplicit registers read: "; Array.iter (fun x -> printf "%s "(cs_reg_name handle x)) insn.regs_read; printf "\n"; end; if (Array.length insn.regs_write) > 0 then begin printf "\tImplicit registers written: "; Array.iter (fun x -> printf "%s "(cs_reg_name handle x)) insn.regs_write; printf "\n"; end; if (Array.length insn.groups) > 0 then begin printf "\tThis instruction belongs to groups: "; Array.iter (printf "%u ") insn.groups; printf "\n"; end; printf "\n";; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment, syntax) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_m680x.ml000064400000000000000000000155660072674642500213630ustar 00000000000000(* Capstone Disassembly Engine * M680X Backend by Wolfgang Schwotzer 2017 *) open Printf open Capstone open M680x open M680x_const let print_char_hex ch = printf " 0x%02x" (Char.code ch) let print_int_hex_short value = printf "%02x" value let print_string_hex comment str = printf "%s" comment; String.iter print_char_hex str; printf "\n" let print_array_hex_short arr = Array.iter print_int_hex_short arr let s_access = [ "UNCHANGED"; "READ"; "WRITE"; "READ | WRITE" ];; let _M6800_CODE = "\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39";; let _M6801_CODE = "\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39";; let _M6805_CODE = "\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe";; let _M6808_CODE = "\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f";; let _HD6301_CODE = "\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39";; let _M6809_CODE = "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00";; let _HD6309_CODE = "\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00";; let _M6811_CODE = "\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f\x18\xce\x10\x00\x18\xff\x10\x00\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f";; let _CPU12_CODE = "\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00\x18\x3e\x18\x3f\x00";; let _HCS08_CODE = "\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82";; let bit_set value mask = value land mask != 0 let all_tests = [ (CS_ARCH_M680X, [CS_MODE_M680X_6301], _HD6301_CODE, "M680X_HD6301"); (CS_ARCH_M680X, [CS_MODE_M680X_6309], _HD6309_CODE, "M680X_HD6309"); (CS_ARCH_M680X, [CS_MODE_M680X_6800], _M6800_CODE, "M680X_M6800"); (CS_ARCH_M680X, [CS_MODE_M680X_6801], _M6801_CODE, "M680X_M6801"); (CS_ARCH_M680X, [CS_MODE_M680X_6805], _M6805_CODE, "M680X_M68HC05"); (CS_ARCH_M680X, [CS_MODE_M680X_6808], _M6808_CODE, "M680X_M68HC08"); (CS_ARCH_M680X, [CS_MODE_M680X_6809], _M6809_CODE, "M680X_M6809"); (CS_ARCH_M680X, [CS_MODE_M680X_6811], _M6811_CODE, "M680X_M68HC11"); (CS_ARCH_M680X, [CS_MODE_M680X_CPU12], _CPU12_CODE, "M680X_CPU12"); (CS_ARCH_M680X, [CS_MODE_M680X_HCS08], _HCS08_CODE, "M680X_HCS08"); ];; let print_inc_dec inc_dec is_post = ( printf "\t\t\t"; if is_post then printf "post" else printf "pre"; if inc_dec > 0 then printf " increment: %d\n" inc_dec else printf " decrement: %d\n" (abs inc_dec); ); ();; let print_op handle flags i op = ( match op.value with | M680X_OP_INVALID _ -> (); (* this would never happens *) | M680X_OP_REGISTER reg -> ( printf "\t\toperands[%d].type: REGISTER = %s" i (cs_reg_name handle reg); if (((i == 0) && (bit_set flags _M680X_FIRST_OP_IN_MNEM)) || ((i == 1) && (bit_set flags _M680X_SECOND_OP_IN_MNEM))) then printf " (in mnemonic)"; printf "\n"; ); | M680X_OP_IMMEDIATE imm -> printf "\t\toperands[%d].type: IMMEDIATE = #%d\n" i imm; | M680X_OP_DIRECT direct_addr -> printf "\t\toperands[%d].type: DIRECT = 0x%02x\n" i direct_addr; | M680X_OP_EXTENDED ext -> ( printf "\t\toperands[%d].type: EXTENDED " i; if ext.indirect then printf "INDIRECT"; printf " = 0x%04x\n" ext.addr_ext; ); | M680X_OP_RELATIVE rel -> printf "\t\toperands[%d].type: RELATIVE = 0x%04x\n" i rel.addr_rel; | M680X_OP_INDEXED idx -> ( printf "\t\toperands[%d].type: INDEXED" i; if (bit_set idx.flags _M680X_IDX_INDIRECT) then printf " INDIRECT"; printf "\n"; if idx.base_reg != _M680X_REG_INVALID then printf "\t\t\tbase register: %s\n" (cs_reg_name handle idx.base_reg); if idx.offset_reg != _M680X_REG_INVALID then printf "\t\t\toffset register: %s\n" (cs_reg_name handle idx.offset_reg); if idx.offset_bits != 0 && idx.offset_reg == 0 && idx.inc_dec == 0 then begin printf "\t\t\toffset: %d\n" idx.offset; if idx.base_reg == _M680X_REG_PC then printf "\t\t\toffset address: 0x%x\n" idx.offset_addr; printf "\t\t\toffset bits: %u\n" idx.offset_bits; end; if idx.inc_dec != 0 then print_inc_dec idx.inc_dec (bit_set idx.flags _M680X_IDX_POST_INC_DEC); ); | M680X_OP_CONSTANT const_val -> printf "\t\toperands[%d].type: CONSTANT = %d\n" i const_val; ); if op.size != 0 then printf "\t\t\tsize: %d\n" op.size; if op.access != _CS_AC_INVALID then printf "\t\t\taccess: %s\n" (List.nth s_access op.access); ();; let print_detail handle insn = match insn.arch with | CS_INFO_M680X m680x -> ( (* print all operands info (type & value) *) if (Array.length m680x.operands) > 0 then ( printf "\top_count: %d\n" (Array.length m680x.operands); Array.iteri (print_op handle m680x.flags) m680x.operands; ); ); | _ -> (); ;; let print_reg handle reg = printf " %s" (cs_reg_name handle reg) let print_insn handle insn = printf "0x%04x:\t" insn.address; print_array_hex_short insn.bytes; printf "\t%s\t%s\n" insn.mnemonic insn.op_str; print_detail handle insn; if (Array.length insn.regs_read) > 0 then begin printf "\tRegisters read:"; Array.iter (print_reg handle) insn.regs_read; printf "\n"; end; if (Array.length insn.regs_write) > 0 then begin printf "\tRegisters modified:"; Array.iter (print_reg handle) insn.regs_write; printf "\n"; end; if (Array.length insn.groups) > 0 then printf "\tgroups_count: %d\n" (Array.length insn.groups); printf "\n" let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "********************\n"; printf "Platform: %s\n" comment; print_string_hex "Code: " code; printf "Disasm:\n"; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_mips.ml000064400000000000000000000040310072674642500214320ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Printf open Capstone open Mips let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56";; let _MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00";; let all_tests = [ (CS_ARCH_MIPS, [CS_MODE_MIPS32; CS_MODE_BIG_ENDIAN], _MIPS_CODE, "MIPS-32 (Big-endian)"); (CS_ARCH_MIPS, [CS_MODE_MIPS64; CS_MODE_LITTLE_ENDIAN], _MIPS_CODE2, "MIPS-64-EL (Little-endian)"); ];; let print_op handle i op = ( match op.value with | MIPS_OP_INVALID _ -> (); (* this would never happens *) | MIPS_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | MIPS_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | MIPS_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; ); ); ();; let print_detail handle insn = match insn.arch with | CS_INFO_MIPS mips -> ( (* print all operands info (type & value) *) if (Array.length mips.operands) > 0 then ( printf "\top_count: %d\n" (Array.length mips.operands); Array.iteri (print_op handle) mips.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_ppc.ml000064400000000000000000000043760072674642500212600ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Printf open Capstone open Ppc let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21";; let all_tests = [ (CS_ARCH_PPC, [CS_MODE_64; CS_MODE_BIG_ENDIAN], _PPC_CODE, "PPC-64"); ];; let print_op handle i op = ( match op.value with | PPC_OP_INVALID _ -> (); (* this would never happens *) | PPC_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | PPC_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | PPC_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; ); | PPC_OP_CRX crx -> ( printf "\t\top[%d]: CRX\n" i; if crx.scale != 0 then printf "\t\t\toperands[%u].crx.scale = %u\n" i crx.scale; if crx.reg != 0 then printf "\t\t\toperands[%u].crx.reg = %s\n" i (cs_reg_name handle crx.reg); if crx.cond != 0 then printf "\t\t\toperands[%u].crx.cond = 0x%x\n" i crx.cond; ); ); ();; let print_detail handle insn = match insn.arch with | CS_INFO_PPC ppc -> ( (* print all operands info (type & value) *) if (Array.length ppc.operands) > 0 then ( printf "\top_count: %d\n" (Array.length ppc.operands); Array.iteri (print_op handle) ppc.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_sparc.ml000064400000000000000000000044570072674642500216060ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Printf open Capstone open Sparc let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _SPARC_CODE = "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03";; let _SPARCV9_CODE = "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0";; let all_tests = [ (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN], _SPARC_CODE, "Sparc"); (CS_ARCH_SPARC, [CS_MODE_BIG_ENDIAN; CS_MODE_V9], _SPARCV9_CODE, "SparcV9"); ];; let print_op handle i op = ( match op.value with | SPARC_OP_INVALID _ -> (); (* this would never happens *) | SPARC_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | SPARC_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | SPARC_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index; if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; ); ); ();; let print_detail handle insn = match insn.arch with | CS_INFO_SPARC sparc -> ( (* print all operands info (type & value) *) if (Array.length sparc.operands) > 0 then ( printf "\top_count: %d\n" (Array.length sparc.operands); Array.iteri (print_op handle) sparc.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_systemz.ml000064400000000000000000000042640072674642500222100ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Printf open Capstone open Systemz let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _SYSZ_CODE = "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78";; let all_tests = [ (CS_ARCH_SYSZ, [CS_MODE_LITTLE_ENDIAN], _SYSZ_CODE, "SystemZ"); ];; let print_op handle i op = ( match op.value with | SYSZ_OP_INVALID _ -> (); (* this would never happens *) | SYSZ_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | SYSZ_OP_ACREG reg -> printf "\t\top[%d]: ACREG = %u\n" i reg; | SYSZ_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | SYSZ_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index; if mem.length != 0L then printf "\t\t\toperands[%u].mem.length: 0x%Lx\n" i mem.length; if mem.disp != 0L then printf "\t\t\toperands[%u].mem.disp: 0x%Lx\n" i mem.disp; ); ); ();; let print_detail handle insn = match insn.arch with | CS_INFO_SYSZ sysz -> ( (* print all operands info (type & value) *) if (Array.length sysz.operands) > 0 then ( printf "\top_count: %d\n" (Array.length sysz.operands); Array.iteri (print_op handle) sysz.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_x86.ml000064400000000000000000000066010072674642500211140ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open Printf open Capstone open X86 open X86_const let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; let _X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00";; let _X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00";; let all_tests = [ (CS_ARCH_X86, [CS_MODE_16], _X86_CODE16, "X86 16bit (Intel syntax)", 0L); (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32bit (ATT syntax)", _CS_OPT_SYNTAX_ATT); (CS_ARCH_X86, [CS_MODE_32], _X86_CODE32, "X86 32 (Intel syntax)", 0L); (CS_ARCH_X86, [CS_MODE_64], _X86_CODE64, "X86 64 (Intel syntax)", 0L); ];; let print_op handle i op = ( match op.value with | X86_OP_INVALID _ -> (); (* this would never happens *) | X86_OP_REG reg -> printf "\t\top[%d]: REG = %s [sz=%d]\n" i (cs_reg_name handle reg) op.size; | X86_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x [sz=%d]\n" i imm op.size; | X86_OP_MEM mem -> ( printf "\t\top[%d]: MEM [sz=%d]\n" i op.size; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then printf "\t\t\toperands[%u].mem.index: REG = %s\n" i (cs_reg_name handle mem.index); if mem.scale != 1 then printf "\t\t\toperands[%u].mem.scale: %d\n" i mem.scale; if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; ); ); ();; let print_detail handle mode insn = match insn.arch with | CS_INFO_X86 x86 -> ( print_string_hex "\tPrefix: " x86.prefix; (* print instruction's opcode *) print_string_hex "\tOpcode: " x86.opcode; (* print operand's size, address size, displacement size & immediate size *) printf "\taddr_size: %u\n" x86.addr_size; (* print modRM byte *) printf "\tmodrm: 0x%x\n" x86.modrm; (* print displacement value *) if x86.disp != 0 then printf "\tdisp: 0x%x\n" x86.disp; (* SIB is invalid in 16-bit mode *) if not (List.mem CS_MODE_16 mode) then ( (* print SIB byte *) printf "\tsib: 0x%x\n" x86.sib; (* print sib index/scale/base (if applicable) *) if x86.sib_index != _X86_REG_INVALID then printf "\tsib_index: %s, sib_scale: %u, sib_base: %s\n" (cs_reg_name handle x86.sib_index) x86.sib_scale (cs_reg_name handle x86.sib_base); ); (* print all operands info (type & value) *) if (Array.length x86.operands) > 0 then ( printf "\top_count: %d\n" (Array.length x86.operands); Array.iteri (print_op handle) x86.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle mode insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle mode insn let print_arch x = let (arch, mode, code, comment, syntax) = x in let handle = cs_open arch mode in ( if syntax != 0L then ( let err = cs_option handle CS_OPT_SYNTAX syntax in match err with | _ -> (); ); let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in ( printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle mode) insns; ); match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; );; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/test_xcore.ml000064400000000000000000000041150072674642500216050ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Printf open Capstone open Xcore let print_string_hex comment str = printf "%s" comment; for i = 0 to (Array.length str - 1) do printf "0x%02x " str.(i) done; printf "\n" let _XCORE_CODE = "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10";; let all_tests = [ (CS_ARCH_XCORE, [CS_MODE_LITTLE_ENDIAN], _XCORE_CODE, "XCore"); ];; let print_op handle i op = ( match op.value with | XCORE_OP_INVALID _ -> (); (* this would never happens *) | XCORE_OP_REG reg -> printf "\t\top[%d]: REG = %s\n" i (cs_reg_name handle reg); | XCORE_OP_IMM imm -> printf "\t\top[%d]: IMM = 0x%x\n" i imm; | XCORE_OP_MEM mem -> ( printf "\t\top[%d]: MEM\n" i; if mem.base != 0 then printf "\t\t\toperands[%u].mem.base: REG = %s\n" i (cs_reg_name handle mem.base); if mem.index != 0 then printf "\t\t\toperands[%u].mem.index: 0x%x\n" i mem.index; if mem.disp != 0 then printf "\t\t\toperands[%u].mem.disp: 0x%x\n" i mem.disp; if mem.direct != 0 then printf "\t\t\toperands[%u].mem.direct: 0x%x\n" i mem.direct; ); ); ();; let print_detail handle insn = match insn.arch with | CS_INFO_XCORE xcore -> ( (* print all operands info (type & value) *) if (Array.length xcore.operands) > 0 then ( printf "\top_count: %d\n" (Array.length xcore.operands); Array.iteri (print_op handle) xcore.operands; ); printf "\n"; ); | _ -> (); ;; let print_insn handle insn = printf "0x%x\t%s\t%s\n" insn.address insn.mnemonic insn.op_str; print_detail handle insn let print_arch x = let (arch, mode, code, comment) = x in let handle = cs_open arch mode in let err = cs_option handle CS_OPT_DETAIL _CS_OPT_ON in match err with | _ -> (); let insns = cs_disasm handle code 0x1000L 0L in printf "*************\n"; printf "Platform: %s\n" comment; List.iter (print_insn handle) insns; match cs_close handle with | 0 -> (); | _ -> printf "Failed to close handle"; ;; List.iter print_arch all_tests;; capstone-sys-0.15.0/capstone/bindings/ocaml/tms320c64x_const.ml000064400000000000000000000211400072674642500223660ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.ml] *) let _TMS320C64X_OP_INVALID = 0;; let _TMS320C64X_OP_REG = 1;; let _TMS320C64X_OP_IMM = 2;; let _TMS320C64X_OP_MEM = 3;; let _TMS320C64X_OP_REGPAIR = 64;; let _TMS320C64X_MEM_DISP_INVALID = 0;; let _TMS320C64X_MEM_DISP_CONSTANT = 1;; let _TMS320C64X_MEM_DISP_REGISTER = 2;; let _TMS320C64X_MEM_DIR_INVALID = 0;; let _TMS320C64X_MEM_DIR_FW = 1;; let _TMS320C64X_MEM_DIR_BW = 2;; let _TMS320C64X_MEM_MOD_INVALID = 0;; let _TMS320C64X_MEM_MOD_NO = 1;; let _TMS320C64X_MEM_MOD_PRE = 2;; let _TMS320C64X_MEM_MOD_POST = 3;; let _TMS320C64X_REG_INVALID = 0;; let _TMS320C64X_REG_AMR = 1;; let _TMS320C64X_REG_CSR = 2;; let _TMS320C64X_REG_DIER = 3;; let _TMS320C64X_REG_DNUM = 4;; let _TMS320C64X_REG_ECR = 5;; let _TMS320C64X_REG_GFPGFR = 6;; let _TMS320C64X_REG_GPLYA = 7;; let _TMS320C64X_REG_GPLYB = 8;; let _TMS320C64X_REG_ICR = 9;; let _TMS320C64X_REG_IER = 10;; let _TMS320C64X_REG_IERR = 11;; let _TMS320C64X_REG_ILC = 12;; let _TMS320C64X_REG_IRP = 13;; let _TMS320C64X_REG_ISR = 14;; let _TMS320C64X_REG_ISTP = 15;; let _TMS320C64X_REG_ITSR = 16;; let _TMS320C64X_REG_NRP = 17;; let _TMS320C64X_REG_NTSR = 18;; let _TMS320C64X_REG_REP = 19;; let _TMS320C64X_REG_RILC = 20;; let _TMS320C64X_REG_SSR = 21;; let _TMS320C64X_REG_TSCH = 22;; let _TMS320C64X_REG_TSCL = 23;; let _TMS320C64X_REG_TSR = 24;; let _TMS320C64X_REG_A0 = 25;; let _TMS320C64X_REG_A1 = 26;; let _TMS320C64X_REG_A2 = 27;; let _TMS320C64X_REG_A3 = 28;; let _TMS320C64X_REG_A4 = 29;; let _TMS320C64X_REG_A5 = 30;; let _TMS320C64X_REG_A6 = 31;; let _TMS320C64X_REG_A7 = 32;; let _TMS320C64X_REG_A8 = 33;; let _TMS320C64X_REG_A9 = 34;; let _TMS320C64X_REG_A10 = 35;; let _TMS320C64X_REG_A11 = 36;; let _TMS320C64X_REG_A12 = 37;; let _TMS320C64X_REG_A13 = 38;; let _TMS320C64X_REG_A14 = 39;; let _TMS320C64X_REG_A15 = 40;; let _TMS320C64X_REG_A16 = 41;; let _TMS320C64X_REG_A17 = 42;; let _TMS320C64X_REG_A18 = 43;; let _TMS320C64X_REG_A19 = 44;; let _TMS320C64X_REG_A20 = 45;; let _TMS320C64X_REG_A21 = 46;; let _TMS320C64X_REG_A22 = 47;; let _TMS320C64X_REG_A23 = 48;; let _TMS320C64X_REG_A24 = 49;; let _TMS320C64X_REG_A25 = 50;; let _TMS320C64X_REG_A26 = 51;; let _TMS320C64X_REG_A27 = 52;; let _TMS320C64X_REG_A28 = 53;; let _TMS320C64X_REG_A29 = 54;; let _TMS320C64X_REG_A30 = 55;; let _TMS320C64X_REG_A31 = 56;; let _TMS320C64X_REG_B0 = 57;; let _TMS320C64X_REG_B1 = 58;; let _TMS320C64X_REG_B2 = 59;; let _TMS320C64X_REG_B3 = 60;; let _TMS320C64X_REG_B4 = 61;; let _TMS320C64X_REG_B5 = 62;; let _TMS320C64X_REG_B6 = 63;; let _TMS320C64X_REG_B7 = 64;; let _TMS320C64X_REG_B8 = 65;; let _TMS320C64X_REG_B9 = 66;; let _TMS320C64X_REG_B10 = 67;; let _TMS320C64X_REG_B11 = 68;; let _TMS320C64X_REG_B12 = 69;; let _TMS320C64X_REG_B13 = 70;; let _TMS320C64X_REG_B14 = 71;; let _TMS320C64X_REG_B15 = 72;; let _TMS320C64X_REG_B16 = 73;; let _TMS320C64X_REG_B17 = 74;; let _TMS320C64X_REG_B18 = 75;; let _TMS320C64X_REG_B19 = 76;; let _TMS320C64X_REG_B20 = 77;; let _TMS320C64X_REG_B21 = 78;; let _TMS320C64X_REG_B22 = 79;; let _TMS320C64X_REG_B23 = 80;; let _TMS320C64X_REG_B24 = 81;; let _TMS320C64X_REG_B25 = 82;; let _TMS320C64X_REG_B26 = 83;; let _TMS320C64X_REG_B27 = 84;; let _TMS320C64X_REG_B28 = 85;; let _TMS320C64X_REG_B29 = 86;; let _TMS320C64X_REG_B30 = 87;; let _TMS320C64X_REG_B31 = 88;; let _TMS320C64X_REG_PCE1 = 89;; let _TMS320C64X_REG_ENDING = 90;; let _TMS320C64X_REG_EFR = _TMS320C64X_REG_ECR;; let _TMS320C64X_REG_IFR = _TMS320C64X_REG_ISR;; let _TMS320C64X_INS_INVALID = 0;; let _TMS320C64X_INS_ABS = 1;; let _TMS320C64X_INS_ABS2 = 2;; let _TMS320C64X_INS_ADD = 3;; let _TMS320C64X_INS_ADD2 = 4;; let _TMS320C64X_INS_ADD4 = 5;; let _TMS320C64X_INS_ADDAB = 6;; let _TMS320C64X_INS_ADDAD = 7;; let _TMS320C64X_INS_ADDAH = 8;; let _TMS320C64X_INS_ADDAW = 9;; let _TMS320C64X_INS_ADDK = 10;; let _TMS320C64X_INS_ADDKPC = 11;; let _TMS320C64X_INS_ADDU = 12;; let _TMS320C64X_INS_AND = 13;; let _TMS320C64X_INS_ANDN = 14;; let _TMS320C64X_INS_AVG2 = 15;; let _TMS320C64X_INS_AVGU4 = 16;; let _TMS320C64X_INS_B = 17;; let _TMS320C64X_INS_BDEC = 18;; let _TMS320C64X_INS_BITC4 = 19;; let _TMS320C64X_INS_BNOP = 20;; let _TMS320C64X_INS_BPOS = 21;; let _TMS320C64X_INS_CLR = 22;; let _TMS320C64X_INS_CMPEQ = 23;; let _TMS320C64X_INS_CMPEQ2 = 24;; let _TMS320C64X_INS_CMPEQ4 = 25;; let _TMS320C64X_INS_CMPGT = 26;; let _TMS320C64X_INS_CMPGT2 = 27;; let _TMS320C64X_INS_CMPGTU4 = 28;; let _TMS320C64X_INS_CMPLT = 29;; let _TMS320C64X_INS_CMPLTU = 30;; let _TMS320C64X_INS_DEAL = 31;; let _TMS320C64X_INS_DOTP2 = 32;; let _TMS320C64X_INS_DOTPN2 = 33;; let _TMS320C64X_INS_DOTPNRSU2 = 34;; let _TMS320C64X_INS_DOTPRSU2 = 35;; let _TMS320C64X_INS_DOTPSU4 = 36;; let _TMS320C64X_INS_DOTPU4 = 37;; let _TMS320C64X_INS_EXT = 38;; let _TMS320C64X_INS_EXTU = 39;; let _TMS320C64X_INS_GMPGTU = 40;; let _TMS320C64X_INS_GMPY4 = 41;; let _TMS320C64X_INS_LDB = 42;; let _TMS320C64X_INS_LDBU = 43;; let _TMS320C64X_INS_LDDW = 44;; let _TMS320C64X_INS_LDH = 45;; let _TMS320C64X_INS_LDHU = 46;; let _TMS320C64X_INS_LDNDW = 47;; let _TMS320C64X_INS_LDNW = 48;; let _TMS320C64X_INS_LDW = 49;; let _TMS320C64X_INS_LMBD = 50;; let _TMS320C64X_INS_MAX2 = 51;; let _TMS320C64X_INS_MAXU4 = 52;; let _TMS320C64X_INS_MIN2 = 53;; let _TMS320C64X_INS_MINU4 = 54;; let _TMS320C64X_INS_MPY = 55;; let _TMS320C64X_INS_MPY2 = 56;; let _TMS320C64X_INS_MPYH = 57;; let _TMS320C64X_INS_MPYHI = 58;; let _TMS320C64X_INS_MPYHIR = 59;; let _TMS320C64X_INS_MPYHL = 60;; let _TMS320C64X_INS_MPYHLU = 61;; let _TMS320C64X_INS_MPYHSLU = 62;; let _TMS320C64X_INS_MPYHSU = 63;; let _TMS320C64X_INS_MPYHU = 64;; let _TMS320C64X_INS_MPYHULS = 65;; let _TMS320C64X_INS_MPYHUS = 66;; let _TMS320C64X_INS_MPYLH = 67;; let _TMS320C64X_INS_MPYLHU = 68;; let _TMS320C64X_INS_MPYLI = 69;; let _TMS320C64X_INS_MPYLIR = 70;; let _TMS320C64X_INS_MPYLSHU = 71;; let _TMS320C64X_INS_MPYLUHS = 72;; let _TMS320C64X_INS_MPYSU = 73;; let _TMS320C64X_INS_MPYSU4 = 74;; let _TMS320C64X_INS_MPYU = 75;; let _TMS320C64X_INS_MPYU4 = 76;; let _TMS320C64X_INS_MPYUS = 77;; let _TMS320C64X_INS_MVC = 78;; let _TMS320C64X_INS_MVD = 79;; let _TMS320C64X_INS_MVK = 80;; let _TMS320C64X_INS_MVKL = 81;; let _TMS320C64X_INS_MVKLH = 82;; let _TMS320C64X_INS_NOP = 83;; let _TMS320C64X_INS_NORM = 84;; let _TMS320C64X_INS_OR = 85;; let _TMS320C64X_INS_PACK2 = 86;; let _TMS320C64X_INS_PACKH2 = 87;; let _TMS320C64X_INS_PACKH4 = 88;; let _TMS320C64X_INS_PACKHL2 = 89;; let _TMS320C64X_INS_PACKL4 = 90;; let _TMS320C64X_INS_PACKLH2 = 91;; let _TMS320C64X_INS_ROTL = 92;; let _TMS320C64X_INS_SADD = 93;; let _TMS320C64X_INS_SADD2 = 94;; let _TMS320C64X_INS_SADDU4 = 95;; let _TMS320C64X_INS_SADDUS2 = 96;; let _TMS320C64X_INS_SAT = 97;; let _TMS320C64X_INS_SET = 98;; let _TMS320C64X_INS_SHFL = 99;; let _TMS320C64X_INS_SHL = 100;; let _TMS320C64X_INS_SHLMB = 101;; let _TMS320C64X_INS_SHR = 102;; let _TMS320C64X_INS_SHR2 = 103;; let _TMS320C64X_INS_SHRMB = 104;; let _TMS320C64X_INS_SHRU = 105;; let _TMS320C64X_INS_SHRU2 = 106;; let _TMS320C64X_INS_SMPY = 107;; let _TMS320C64X_INS_SMPY2 = 108;; let _TMS320C64X_INS_SMPYH = 109;; let _TMS320C64X_INS_SMPYHL = 110;; let _TMS320C64X_INS_SMPYLH = 111;; let _TMS320C64X_INS_SPACK2 = 112;; let _TMS320C64X_INS_SPACKU4 = 113;; let _TMS320C64X_INS_SSHL = 114;; let _TMS320C64X_INS_SSHVL = 115;; let _TMS320C64X_INS_SSHVR = 116;; let _TMS320C64X_INS_SSUB = 117;; let _TMS320C64X_INS_STB = 118;; let _TMS320C64X_INS_STDW = 119;; let _TMS320C64X_INS_STH = 120;; let _TMS320C64X_INS_STNDW = 121;; let _TMS320C64X_INS_STNW = 122;; let _TMS320C64X_INS_STW = 123;; let _TMS320C64X_INS_SUB = 124;; let _TMS320C64X_INS_SUB2 = 125;; let _TMS320C64X_INS_SUB4 = 126;; let _TMS320C64X_INS_SUBAB = 127;; let _TMS320C64X_INS_SUBABS4 = 128;; let _TMS320C64X_INS_SUBAH = 129;; let _TMS320C64X_INS_SUBAW = 130;; let _TMS320C64X_INS_SUBC = 131;; let _TMS320C64X_INS_SUBU = 132;; let _TMS320C64X_INS_SWAP4 = 133;; let _TMS320C64X_INS_UNPKHU4 = 134;; let _TMS320C64X_INS_UNPKLU4 = 135;; let _TMS320C64X_INS_XOR = 136;; let _TMS320C64X_INS_XPND2 = 137;; let _TMS320C64X_INS_XPND4 = 138;; let _TMS320C64X_INS_IDLE = 139;; let _TMS320C64X_INS_MV = 140;; let _TMS320C64X_INS_NEG = 141;; let _TMS320C64X_INS_NOT = 142;; let _TMS320C64X_INS_SWAP2 = 143;; let _TMS320C64X_INS_ZERO = 144;; let _TMS320C64X_INS_ENDING = 145;; let _TMS320C64X_GRP_INVALID = 0;; let _TMS320C64X_GRP_JUMP = 1;; let _TMS320C64X_GRP_FUNIT_D = 128;; let _TMS320C64X_GRP_FUNIT_L = 129;; let _TMS320C64X_GRP_FUNIT_M = 130;; let _TMS320C64X_GRP_FUNIT_S = 131;; let _TMS320C64X_GRP_FUNIT_NO = 132;; let _TMS320C64X_GRP_ENDING = 133;; let _TMS320C64X_FUNIT_INVALID = 0;; let _TMS320C64X_FUNIT_D = 1;; let _TMS320C64X_FUNIT_L = 2;; let _TMS320C64X_FUNIT_M = 3;; let _TMS320C64X_FUNIT_S = 4;; let _TMS320C64X_FUNIT_NO = 5;; capstone-sys-0.15.0/capstone/bindings/ocaml/wasm_const.ml000064400000000000000000000140670072674642500216120ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.ml] *) let _WASM_OP_INVALID = 0;; let _WASM_OP_NONE = 1;; let _WASM_OP_INT7 = 2;; let _WASM_OP_VARUINT32 = 3;; let _WASM_OP_VARUINT64 = 4;; let _WASM_OP_UINT32 = 5;; let _WASM_OP_UINT64 = 6;; let _WASM_OP_IMM = 7;; let _WASM_OP_BRTABLE = 8;; let _WASM_INS_UNREACHABLE = 0x0;; let _WASM_INS_NOP = 0x1;; let _WASM_INS_BLOCK = 0x2;; let _WASM_INS_LOOP = 0x3;; let _WASM_INS_IF = 0x4;; let _WASM_INS_ELSE = 0x5;; let _WASM_INS_END = 0xb;; let _WASM_INS_BR = 0xc;; let _WASM_INS_BR_IF = 0xd;; let _WASM_INS_BR_TABLE = 0xe;; let _WASM_INS_RETURN = 0xf;; let _WASM_INS_CALL = 0x10;; let _WASM_INS_CALL_INDIRECT = 0x11;; let _WASM_INS_DROP = 0x1a;; let _WASM_INS_SELECT = 0x1b;; let _WASM_INS_GET_LOCAL = 0x20;; let _WASM_INS_SET_LOCAL = 0x21;; let _WASM_INS_TEE_LOCAL = 0x22;; let _WASM_INS_GET_GLOBAL = 0x23;; let _WASM_INS_SET_GLOBAL = 0x24;; let _WASM_INS_I32_LOAD = 0x28;; let _WASM_INS_I64_LOAD = 0x29;; let _WASM_INS_F32_LOAD = 0x2a;; let _WASM_INS_F64_LOAD = 0x2b;; let _WASM_INS_I32_LOAD8_S = 0x2c;; let _WASM_INS_I32_LOAD8_U = 0x2d;; let _WASM_INS_I32_LOAD16_S = 0x2e;; let _WASM_INS_I32_LOAD16_U = 0x2f;; let _WASM_INS_I64_LOAD8_S = 0x30;; let _WASM_INS_I64_LOAD8_U = 0x31;; let _WASM_INS_I64_LOAD16_S = 0x32;; let _WASM_INS_I64_LOAD16_U = 0x33;; let _WASM_INS_I64_LOAD32_S = 0x34;; let _WASM_INS_I64_LOAD32_U = 0x35;; let _WASM_INS_I32_STORE = 0x36;; let _WASM_INS_I64_STORE = 0x37;; let _WASM_INS_F32_STORE = 0x38;; let _WASM_INS_F64_STORE = 0x39;; let _WASM_INS_I32_STORE8 = 0x3a;; let _WASM_INS_I32_STORE16 = 0x3b;; let _WASM_INS_I64_STORE8 = 0x3c;; let _WASM_INS_I64_STORE16 = 0x3d;; let _WASM_INS_I64_STORE32 = 0x3e;; let _WASM_INS_CURRENT_MEMORY = 0x3f;; let _WASM_INS_GROW_MEMORY = 0x40;; let _WASM_INS_I32_CONST = 0x41;; let _WASM_INS_I64_CONST = 0x42;; let _WASM_INS_F32_CONST = 0x43;; let _WASM_INS_F64_CONST = 0x44;; let _WASM_INS_I32_EQZ = 0x45;; let _WASM_INS_I32_EQ = 0x46;; let _WASM_INS_I32_NE = 0x47;; let _WASM_INS_I32_LT_S = 0x48;; let _WASM_INS_I32_LT_U = 0x49;; let _WASM_INS_I32_GT_S = 0x4a;; let _WASM_INS_I32_GT_U = 0x4b;; let _WASM_INS_I32_LE_S = 0x4c;; let _WASM_INS_I32_LE_U = 0x4d;; let _WASM_INS_I32_GE_S = 0x4e;; let _WASM_INS_I32_GE_U = 0x4f;; let _WASM_INS_I64_EQZ = 0x50;; let _WASM_INS_I64_EQ = 0x51;; let _WASM_INS_I64_NE = 0x52;; let _WASM_INS_I64_LT_S = 0x53;; let _WASM_INS_I64_LT_U = 0x54;; let _WASM_INS_I64_GT_U = 0x56;; let _WASM_INS_I64_LE_S = 0x57;; let _WASM_INS_I64_LE_U = 0x58;; let _WASM_INS_I64_GE_S = 0x59;; let _WASM_INS_I64_GE_U = 0x5a;; let _WASM_INS_F32_EQ = 0x5b;; let _WASM_INS_F32_NE = 0x5c;; let _WASM_INS_F32_LT = 0x5d;; let _WASM_INS_F32_GT = 0x5e;; let _WASM_INS_F32_LE = 0x5f;; let _WASM_INS_F32_GE = 0x60;; let _WASM_INS_F64_EQ = 0x61;; let _WASM_INS_F64_NE = 0x62;; let _WASM_INS_F64_LT = 0x63;; let _WASM_INS_F64_GT = 0x64;; let _WASM_INS_F64_LE = 0x65;; let _WASM_INS_F64_GE = 0x66;; let _WASM_INS_I32_CLZ = 0x67;; let _WASM_INS_I32_CTZ = 0x68;; let _WASM_INS_I32_POPCNT = 0x69;; let _WASM_INS_I32_ADD = 0x6a;; let _WASM_INS_I32_SUB = 0x6b;; let _WASM_INS_I32_MUL = 0x6c;; let _WASM_INS_I32_DIV_S = 0x6d;; let _WASM_INS_I32_DIV_U = 0x6e;; let _WASM_INS_I32_REM_S = 0x6f;; let _WASM_INS_I32_REM_U = 0x70;; let _WASM_INS_I32_AND = 0x71;; let _WASM_INS_I32_OR = 0x72;; let _WASM_INS_I32_XOR = 0x73;; let _WASM_INS_I32_SHL = 0x74;; let _WASM_INS_I32_SHR_S = 0x75;; let _WASM_INS_I32_SHR_U = 0x76;; let _WASM_INS_I32_ROTL = 0x77;; let _WASM_INS_I32_ROTR = 0x78;; let _WASM_INS_I64_CLZ = 0x79;; let _WASM_INS_I64_CTZ = 0x7a;; let _WASM_INS_I64_POPCNT = 0x7b;; let _WASM_INS_I64_ADD = 0x7c;; let _WASM_INS_I64_SUB = 0x7d;; let _WASM_INS_I64_MUL = 0x7e;; let _WASM_INS_I64_DIV_S = 0x7f;; let _WASM_INS_I64_DIV_U = 0x80;; let _WASM_INS_I64_REM_S = 0x81;; let _WASM_INS_I64_REM_U = 0x82;; let _WASM_INS_I64_AND = 0x83;; let _WASM_INS_I64_OR = 0x84;; let _WASM_INS_I64_XOR = 0x85;; let _WASM_INS_I64_SHL = 0x86;; let _WASM_INS_I64_SHR_S = 0x87;; let _WASM_INS_I64_SHR_U = 0x88;; let _WASM_INS_I64_ROTL = 0x89;; let _WASM_INS_I64_ROTR = 0x8a;; let _WASM_INS_F32_ABS = 0x8b;; let _WASM_INS_F32_NEG = 0x8c;; let _WASM_INS_F32_CEIL = 0x8d;; let _WASM_INS_F32_FLOOR = 0x8e;; let _WASM_INS_F32_TRUNC = 0x8f;; let _WASM_INS_F32_NEAREST = 0x90;; let _WASM_INS_F32_SQRT = 0x91;; let _WASM_INS_F32_ADD = 0x92;; let _WASM_INS_F32_SUB = 0x93;; let _WASM_INS_F32_MUL = 0x94;; let _WASM_INS_F32_DIV = 0x95;; let _WASM_INS_F32_MIN = 0x96;; let _WASM_INS_F32_MAX = 0x97;; let _WASM_INS_F32_COPYSIGN = 0x98;; let _WASM_INS_F64_ABS = 0x99;; let _WASM_INS_F64_NEG = 0x9a;; let _WASM_INS_F64_CEIL = 0x9b;; let _WASM_INS_F64_FLOOR = 0x9c;; let _WASM_INS_F64_TRUNC = 0x9d;; let _WASM_INS_F64_NEAREST = 0x9e;; let _WASM_INS_F64_SQRT = 0x9f;; let _WASM_INS_F64_ADD = 0xa0;; let _WASM_INS_F64_SUB = 0xa1;; let _WASM_INS_F64_MUL = 0xa2;; let _WASM_INS_F64_DIV = 0xa3;; let _WASM_INS_F64_MIN = 0xa4;; let _WASM_INS_F64_MAX = 0xa5;; let _WASM_INS_F64_COPYSIGN = 0xa6;; let _WASM_INS_I32_WARP_I64 = 0xa7;; let _WASM_INS_I32_TRUNC_U_F32 = 0xa9;; let _WASM_INS_I32_TRUNC_S_F64 = 0xaa;; let _WASM_INS_I32_TRUNC_U_F64 = 0xab;; let _WASM_INS_I64_EXTEND_S_I32 = 0xac;; let _WASM_INS_I64_EXTEND_U_I32 = 0xad;; let _WASM_INS_I64_TRUNC_S_F32 = 0xae;; let _WASM_INS_I64_TRUNC_U_F32 = 0xaf;; let _WASM_INS_I64_TRUNC_S_F64 = 0xb0;; let _WASM_INS_I64_TRUNC_U_F64 = 0xb1;; let _WASM_INS_F32_CONVERT_S_I32 = 0xb2;; let _WASM_INS_F32_CONVERT_U_I32 = 0xb3;; let _WASM_INS_F32_CONVERT_S_I64 = 0xb4;; let _WASM_INS_F32_CONVERT_U_I64 = 0xb5;; let _WASM_INS_F32_DEMOTE_F64 = 0xb6;; let _WASM_INS_F64_CONVERT_S_I32 = 0xb7;; let _WASM_INS_F64_CONVERT_U_I32 = 0xb8;; let _WASM_INS_F64_CONVERT_S_I64 = 0xb9;; let _WASM_INS_F64_CONVERT_U_I64 = 0xba;; let _WASM_INS_F64_PROMOTE_F32 = 0xbb;; let _WASM_INS_I32_REINTERPRET_F32 = 0xbc;; let _WASM_INS_I64_REINTERPRET_F64 = 0xbd;; let _WASM_INS_F32_REINTERPRET_I32 = 0xbe;; let _WASM_INS_F64_REINTERPRET_I64 = 0xbf;; let _WASM_INS_INVALID = 512;; let _WASM_INS_ENDING = 513;; let _WASM_GRP_INVALID = 0;; let _WASM_GRP_NUMBERIC = 8;; let _WASM_GRP_PARAMETRIC = 9;; let _WASM_GRP_VARIABLE = 10;; let _WASM_GRP_MEMORY = 11;; let _WASM_GRP_CONTROL = 12;; let _WASM_GRP_ENDING = 13;; capstone-sys-0.15.0/capstone/bindings/ocaml/x86.ml000064400000000000000000000013520072674642500200530ustar 00000000000000(* Capstone Disassembly Engine * By Nguyen Anh Quynh , 2013-2014 *) open X86_const (* architecture specific info of instruction *) type x86_op_mem = { segment: int; base: int; index: int; scale: int; disp: int; } type x86_op_value = | X86_OP_INVALID of int | X86_OP_REG of int | X86_OP_IMM of int | X86_OP_MEM of x86_op_mem type x86_op = { value: x86_op_value; size: int; access: int; avx_bcast: int; avx_zero_opmask: int; } type cs_x86 = { prefix: int array; opcode: int array; rex: int; addr_size: int; modrm: int; sib: int; disp: int; sib_index: int; sib_scale: int; sib_base: int; xop_cc: int; sse_cc: int; avx_cc: int; avx_sae: int; avx_rm: int; eflags: int; operands: x86_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/x86_const.ml000064400000000000000000001607070072674642500212730ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.ml] *) let _X86_REG_INVALID = 0;; let _X86_REG_AH = 1;; let _X86_REG_AL = 2;; let _X86_REG_AX = 3;; let _X86_REG_BH = 4;; let _X86_REG_BL = 5;; let _X86_REG_BP = 6;; let _X86_REG_BPL = 7;; let _X86_REG_BX = 8;; let _X86_REG_CH = 9;; let _X86_REG_CL = 10;; let _X86_REG_CS = 11;; let _X86_REG_CX = 12;; let _X86_REG_DH = 13;; let _X86_REG_DI = 14;; let _X86_REG_DIL = 15;; let _X86_REG_DL = 16;; let _X86_REG_DS = 17;; let _X86_REG_DX = 18;; let _X86_REG_EAX = 19;; let _X86_REG_EBP = 20;; let _X86_REG_EBX = 21;; let _X86_REG_ECX = 22;; let _X86_REG_EDI = 23;; let _X86_REG_EDX = 24;; let _X86_REG_EFLAGS = 25;; let _X86_REG_EIP = 26;; let _X86_REG_EIZ = 27;; let _X86_REG_ES = 28;; let _X86_REG_ESI = 29;; let _X86_REG_ESP = 30;; let _X86_REG_FPSW = 31;; let _X86_REG_FS = 32;; let _X86_REG_GS = 33;; let _X86_REG_IP = 34;; let _X86_REG_RAX = 35;; let _X86_REG_RBP = 36;; let _X86_REG_RBX = 37;; let _X86_REG_RCX = 38;; let _X86_REG_RDI = 39;; let _X86_REG_RDX = 40;; let _X86_REG_RIP = 41;; let _X86_REG_RIZ = 42;; let _X86_REG_RSI = 43;; let _X86_REG_RSP = 44;; let _X86_REG_SI = 45;; let _X86_REG_SIL = 46;; let _X86_REG_SP = 47;; let _X86_REG_SPL = 48;; let _X86_REG_SS = 49;; let _X86_REG_CR0 = 50;; let _X86_REG_CR1 = 51;; let _X86_REG_CR2 = 52;; let _X86_REG_CR3 = 53;; let _X86_REG_CR4 = 54;; let _X86_REG_CR5 = 55;; let _X86_REG_CR6 = 56;; let _X86_REG_CR7 = 57;; let _X86_REG_CR8 = 58;; let _X86_REG_CR9 = 59;; let _X86_REG_CR10 = 60;; let _X86_REG_CR11 = 61;; let _X86_REG_CR12 = 62;; let _X86_REG_CR13 = 63;; let _X86_REG_CR14 = 64;; let _X86_REG_CR15 = 65;; let _X86_REG_DR0 = 66;; let _X86_REG_DR1 = 67;; let _X86_REG_DR2 = 68;; let _X86_REG_DR3 = 69;; let _X86_REG_DR4 = 70;; let _X86_REG_DR5 = 71;; let _X86_REG_DR6 = 72;; let _X86_REG_DR7 = 73;; let _X86_REG_DR8 = 74;; let _X86_REG_DR9 = 75;; let _X86_REG_DR10 = 76;; let _X86_REG_DR11 = 77;; let _X86_REG_DR12 = 78;; let _X86_REG_DR13 = 79;; let _X86_REG_DR14 = 80;; let _X86_REG_DR15 = 81;; let _X86_REG_FP0 = 82;; let _X86_REG_FP1 = 83;; let _X86_REG_FP2 = 84;; let _X86_REG_FP3 = 85;; let _X86_REG_FP4 = 86;; let _X86_REG_FP5 = 87;; let _X86_REG_FP6 = 88;; let _X86_REG_FP7 = 89;; let _X86_REG_K0 = 90;; let _X86_REG_K1 = 91;; let _X86_REG_K2 = 92;; let _X86_REG_K3 = 93;; let _X86_REG_K4 = 94;; let _X86_REG_K5 = 95;; let _X86_REG_K6 = 96;; let _X86_REG_K7 = 97;; let _X86_REG_MM0 = 98;; let _X86_REG_MM1 = 99;; let _X86_REG_MM2 = 100;; let _X86_REG_MM3 = 101;; let _X86_REG_MM4 = 102;; let _X86_REG_MM5 = 103;; let _X86_REG_MM6 = 104;; let _X86_REG_MM7 = 105;; let _X86_REG_R8 = 106;; let _X86_REG_R9 = 107;; let _X86_REG_R10 = 108;; let _X86_REG_R11 = 109;; let _X86_REG_R12 = 110;; let _X86_REG_R13 = 111;; let _X86_REG_R14 = 112;; let _X86_REG_R15 = 113;; let _X86_REG_ST0 = 114;; let _X86_REG_ST1 = 115;; let _X86_REG_ST2 = 116;; let _X86_REG_ST3 = 117;; let _X86_REG_ST4 = 118;; let _X86_REG_ST5 = 119;; let _X86_REG_ST6 = 120;; let _X86_REG_ST7 = 121;; let _X86_REG_XMM0 = 122;; let _X86_REG_XMM1 = 123;; let _X86_REG_XMM2 = 124;; let _X86_REG_XMM3 = 125;; let _X86_REG_XMM4 = 126;; let _X86_REG_XMM5 = 127;; let _X86_REG_XMM6 = 128;; let _X86_REG_XMM7 = 129;; let _X86_REG_XMM8 = 130;; let _X86_REG_XMM9 = 131;; let _X86_REG_XMM10 = 132;; let _X86_REG_XMM11 = 133;; let _X86_REG_XMM12 = 134;; let _X86_REG_XMM13 = 135;; let _X86_REG_XMM14 = 136;; let _X86_REG_XMM15 = 137;; let _X86_REG_XMM16 = 138;; let _X86_REG_XMM17 = 139;; let _X86_REG_XMM18 = 140;; let _X86_REG_XMM19 = 141;; let _X86_REG_XMM20 = 142;; let _X86_REG_XMM21 = 143;; let _X86_REG_XMM22 = 144;; let _X86_REG_XMM23 = 145;; let _X86_REG_XMM24 = 146;; let _X86_REG_XMM25 = 147;; let _X86_REG_XMM26 = 148;; let _X86_REG_XMM27 = 149;; let _X86_REG_XMM28 = 150;; let _X86_REG_XMM29 = 151;; let _X86_REG_XMM30 = 152;; let _X86_REG_XMM31 = 153;; let _X86_REG_YMM0 = 154;; let _X86_REG_YMM1 = 155;; let _X86_REG_YMM2 = 156;; let _X86_REG_YMM3 = 157;; let _X86_REG_YMM4 = 158;; let _X86_REG_YMM5 = 159;; let _X86_REG_YMM6 = 160;; let _X86_REG_YMM7 = 161;; let _X86_REG_YMM8 = 162;; let _X86_REG_YMM9 = 163;; let _X86_REG_YMM10 = 164;; let _X86_REG_YMM11 = 165;; let _X86_REG_YMM12 = 166;; let _X86_REG_YMM13 = 167;; let _X86_REG_YMM14 = 168;; let _X86_REG_YMM15 = 169;; let _X86_REG_YMM16 = 170;; let _X86_REG_YMM17 = 171;; let _X86_REG_YMM18 = 172;; let _X86_REG_YMM19 = 173;; let _X86_REG_YMM20 = 174;; let _X86_REG_YMM21 = 175;; let _X86_REG_YMM22 = 176;; let _X86_REG_YMM23 = 177;; let _X86_REG_YMM24 = 178;; let _X86_REG_YMM25 = 179;; let _X86_REG_YMM26 = 180;; let _X86_REG_YMM27 = 181;; let _X86_REG_YMM28 = 182;; let _X86_REG_YMM29 = 183;; let _X86_REG_YMM30 = 184;; let _X86_REG_YMM31 = 185;; let _X86_REG_ZMM0 = 186;; let _X86_REG_ZMM1 = 187;; let _X86_REG_ZMM2 = 188;; let _X86_REG_ZMM3 = 189;; let _X86_REG_ZMM4 = 190;; let _X86_REG_ZMM5 = 191;; let _X86_REG_ZMM6 = 192;; let _X86_REG_ZMM7 = 193;; let _X86_REG_ZMM8 = 194;; let _X86_REG_ZMM9 = 195;; let _X86_REG_ZMM10 = 196;; let _X86_REG_ZMM11 = 197;; let _X86_REG_ZMM12 = 198;; let _X86_REG_ZMM13 = 199;; let _X86_REG_ZMM14 = 200;; let _X86_REG_ZMM15 = 201;; let _X86_REG_ZMM16 = 202;; let _X86_REG_ZMM17 = 203;; let _X86_REG_ZMM18 = 204;; let _X86_REG_ZMM19 = 205;; let _X86_REG_ZMM20 = 206;; let _X86_REG_ZMM21 = 207;; let _X86_REG_ZMM22 = 208;; let _X86_REG_ZMM23 = 209;; let _X86_REG_ZMM24 = 210;; let _X86_REG_ZMM25 = 211;; let _X86_REG_ZMM26 = 212;; let _X86_REG_ZMM27 = 213;; let _X86_REG_ZMM28 = 214;; let _X86_REG_ZMM29 = 215;; let _X86_REG_ZMM30 = 216;; let _X86_REG_ZMM31 = 217;; let _X86_REG_R8B = 218;; let _X86_REG_R9B = 219;; let _X86_REG_R10B = 220;; let _X86_REG_R11B = 221;; let _X86_REG_R12B = 222;; let _X86_REG_R13B = 223;; let _X86_REG_R14B = 224;; let _X86_REG_R15B = 225;; let _X86_REG_R8D = 226;; let _X86_REG_R9D = 227;; let _X86_REG_R10D = 228;; let _X86_REG_R11D = 229;; let _X86_REG_R12D = 230;; let _X86_REG_R13D = 231;; let _X86_REG_R14D = 232;; let _X86_REG_R15D = 233;; let _X86_REG_R8W = 234;; let _X86_REG_R9W = 235;; let _X86_REG_R10W = 236;; let _X86_REG_R11W = 237;; let _X86_REG_R12W = 238;; let _X86_REG_R13W = 239;; let _X86_REG_R14W = 240;; let _X86_REG_R15W = 241;; let _X86_REG_BND0 = 242;; let _X86_REG_BND1 = 243;; let _X86_REG_BND2 = 244;; let _X86_REG_BND3 = 245;; let _X86_REG_ENDING = 246;; let _X86_EFLAGS_MODIFY_AF = 1 lsl 0;; let _X86_EFLAGS_MODIFY_CF = 1 lsl 1;; let _X86_EFLAGS_MODIFY_SF = 1 lsl 2;; let _X86_EFLAGS_MODIFY_ZF = 1 lsl 3;; let _X86_EFLAGS_MODIFY_PF = 1 lsl 4;; let _X86_EFLAGS_MODIFY_OF = 1 lsl 5;; let _X86_EFLAGS_MODIFY_TF = 1 lsl 6;; let _X86_EFLAGS_MODIFY_IF = 1 lsl 7;; let _X86_EFLAGS_MODIFY_DF = 1 lsl 8;; let _X86_EFLAGS_MODIFY_NT = 1 lsl 9;; let _X86_EFLAGS_MODIFY_RF = 1 lsl 10;; let _X86_EFLAGS_PRIOR_OF = 1 lsl 11;; let _X86_EFLAGS_PRIOR_SF = 1 lsl 12;; let _X86_EFLAGS_PRIOR_ZF = 1 lsl 13;; let _X86_EFLAGS_PRIOR_AF = 1 lsl 14;; let _X86_EFLAGS_PRIOR_PF = 1 lsl 15;; let _X86_EFLAGS_PRIOR_CF = 1 lsl 16;; let _X86_EFLAGS_PRIOR_TF = 1 lsl 17;; let _X86_EFLAGS_PRIOR_IF = 1 lsl 18;; let _X86_EFLAGS_PRIOR_DF = 1 lsl 19;; let _X86_EFLAGS_PRIOR_NT = 1 lsl 20;; let _X86_EFLAGS_RESET_OF = 1 lsl 21;; let _X86_EFLAGS_RESET_CF = 1 lsl 22;; let _X86_EFLAGS_RESET_DF = 1 lsl 23;; let _X86_EFLAGS_RESET_IF = 1 lsl 24;; let _X86_EFLAGS_RESET_SF = 1 lsl 25;; let _X86_EFLAGS_RESET_AF = 1 lsl 26;; let _X86_EFLAGS_RESET_TF = 1 lsl 27;; let _X86_EFLAGS_RESET_NT = 1 lsl 28;; let _X86_EFLAGS_RESET_PF = 1 lsl 29;; let _X86_EFLAGS_SET_CF = 1 lsl 30;; let _X86_EFLAGS_SET_DF = 1 lsl 31;; let _X86_EFLAGS_SET_IF = 1 lsl 32;; let _X86_EFLAGS_TEST_OF = 1 lsl 33;; let _X86_EFLAGS_TEST_SF = 1 lsl 34;; let _X86_EFLAGS_TEST_ZF = 1 lsl 35;; let _X86_EFLAGS_TEST_PF = 1 lsl 36;; let _X86_EFLAGS_TEST_CF = 1 lsl 37;; let _X86_EFLAGS_TEST_NT = 1 lsl 38;; let _X86_EFLAGS_TEST_DF = 1 lsl 39;; let _X86_EFLAGS_UNDEFINED_OF = 1 lsl 40;; let _X86_EFLAGS_UNDEFINED_SF = 1 lsl 41;; let _X86_EFLAGS_UNDEFINED_ZF = 1 lsl 42;; let _X86_EFLAGS_UNDEFINED_PF = 1 lsl 43;; let _X86_EFLAGS_UNDEFINED_AF = 1 lsl 44;; let _X86_EFLAGS_UNDEFINED_CF = 1 lsl 45;; let _X86_EFLAGS_RESET_RF = 1 lsl 46;; let _X86_EFLAGS_TEST_RF = 1 lsl 47;; let _X86_EFLAGS_TEST_IF = 1 lsl 48;; let _X86_EFLAGS_TEST_TF = 1 lsl 49;; let _X86_EFLAGS_TEST_AF = 1 lsl 50;; let _X86_EFLAGS_RESET_ZF = 1 lsl 51;; let _X86_EFLAGS_SET_OF = 1 lsl 52;; let _X86_EFLAGS_SET_SF = 1 lsl 53;; let _X86_EFLAGS_SET_ZF = 1 lsl 54;; let _X86_EFLAGS_SET_AF = 1 lsl 55;; let _X86_EFLAGS_SET_PF = 1 lsl 56;; let _X86_EFLAGS_RESET_0F = 1 lsl 57;; let _X86_EFLAGS_RESET_AC = 1 lsl 58;; let _X86_FPU_FLAGS_MODIFY_C0 = 1 lsl 0;; let _X86_FPU_FLAGS_MODIFY_C1 = 1 lsl 1;; let _X86_FPU_FLAGS_MODIFY_C2 = 1 lsl 2;; let _X86_FPU_FLAGS_MODIFY_C3 = 1 lsl 3;; let _X86_FPU_FLAGS_RESET_C0 = 1 lsl 4;; let _X86_FPU_FLAGS_RESET_C1 = 1 lsl 5;; let _X86_FPU_FLAGS_RESET_C2 = 1 lsl 6;; let _X86_FPU_FLAGS_RESET_C3 = 1 lsl 7;; let _X86_FPU_FLAGS_SET_C0 = 1 lsl 8;; let _X86_FPU_FLAGS_SET_C1 = 1 lsl 9;; let _X86_FPU_FLAGS_SET_C2 = 1 lsl 10;; let _X86_FPU_FLAGS_SET_C3 = 1 lsl 11;; let _X86_FPU_FLAGS_UNDEFINED_C0 = 1 lsl 12;; let _X86_FPU_FLAGS_UNDEFINED_C1 = 1 lsl 13;; let _X86_FPU_FLAGS_UNDEFINED_C2 = 1 lsl 14;; let _X86_FPU_FLAGS_UNDEFINED_C3 = 1 lsl 15;; let _X86_FPU_FLAGS_TEST_C0 = 1 lsl 16;; let _X86_FPU_FLAGS_TEST_C1 = 1 lsl 17;; let _X86_FPU_FLAGS_TEST_C2 = 1 lsl 18;; let _X86_FPU_FLAGS_TEST_C3 = 1 lsl 19;; let _X86_OP_INVALID = 0;; let _X86_OP_REG = 1;; let _X86_OP_IMM = 2;; let _X86_OP_MEM = 3;; let _X86_XOP_CC_INVALID = 0;; let _X86_XOP_CC_LT = 1;; let _X86_XOP_CC_LE = 2;; let _X86_XOP_CC_GT = 3;; let _X86_XOP_CC_GE = 4;; let _X86_XOP_CC_EQ = 5;; let _X86_XOP_CC_NEQ = 6;; let _X86_XOP_CC_FALSE = 7;; let _X86_XOP_CC_TRUE = 8;; let _X86_AVX_BCAST_INVALID = 0;; let _X86_AVX_BCAST_2 = 1;; let _X86_AVX_BCAST_4 = 2;; let _X86_AVX_BCAST_8 = 3;; let _X86_AVX_BCAST_16 = 4;; let _X86_SSE_CC_INVALID = 0;; let _X86_SSE_CC_EQ = 1;; let _X86_SSE_CC_LT = 2;; let _X86_SSE_CC_LE = 3;; let _X86_SSE_CC_UNORD = 4;; let _X86_SSE_CC_NEQ = 5;; let _X86_SSE_CC_NLT = 6;; let _X86_SSE_CC_NLE = 7;; let _X86_SSE_CC_ORD = 8;; let _X86_AVX_CC_INVALID = 0;; let _X86_AVX_CC_EQ = 1;; let _X86_AVX_CC_LT = 2;; let _X86_AVX_CC_LE = 3;; let _X86_AVX_CC_UNORD = 4;; let _X86_AVX_CC_NEQ = 5;; let _X86_AVX_CC_NLT = 6;; let _X86_AVX_CC_NLE = 7;; let _X86_AVX_CC_ORD = 8;; let _X86_AVX_CC_EQ_UQ = 9;; let _X86_AVX_CC_NGE = 10;; let _X86_AVX_CC_NGT = 11;; let _X86_AVX_CC_FALSE = 12;; let _X86_AVX_CC_NEQ_OQ = 13;; let _X86_AVX_CC_GE = 14;; let _X86_AVX_CC_GT = 15;; let _X86_AVX_CC_TRUE = 16;; let _X86_AVX_CC_EQ_OS = 17;; let _X86_AVX_CC_LT_OQ = 18;; let _X86_AVX_CC_LE_OQ = 19;; let _X86_AVX_CC_UNORD_S = 20;; let _X86_AVX_CC_NEQ_US = 21;; let _X86_AVX_CC_NLT_UQ = 22;; let _X86_AVX_CC_NLE_UQ = 23;; let _X86_AVX_CC_ORD_S = 24;; let _X86_AVX_CC_EQ_US = 25;; let _X86_AVX_CC_NGE_UQ = 26;; let _X86_AVX_CC_NGT_UQ = 27;; let _X86_AVX_CC_FALSE_OS = 28;; let _X86_AVX_CC_NEQ_OS = 29;; let _X86_AVX_CC_GE_OQ = 30;; let _X86_AVX_CC_GT_OQ = 31;; let _X86_AVX_CC_TRUE_US = 32;; let _X86_AVX_RM_INVALID = 0;; let _X86_AVX_RM_RN = 1;; let _X86_AVX_RM_RD = 2;; let _X86_AVX_RM_RU = 3;; let _X86_AVX_RM_RZ = 4;; let _X86_PREFIX_LOCK = 0xf0;; let _X86_PREFIX_REP = 0xf3;; let _X86_PREFIX_REPE = 0xf3;; let _X86_PREFIX_REPNE = 0xf2;; let _X86_PREFIX_CS = 0x2e;; let _X86_PREFIX_SS = 0x36;; let _X86_PREFIX_DS = 0x3e;; let _X86_PREFIX_ES = 0x26;; let _X86_PREFIX_FS = 0x64;; let _X86_PREFIX_GS = 0x65;; let _X86_PREFIX_OPSIZE = 0x66;; let _X86_PREFIX_ADDRSIZE = 0x67;; let _X86_INS_INVALID = 0;; let _X86_INS_AAA = 1;; let _X86_INS_AAD = 2;; let _X86_INS_AAM = 3;; let _X86_INS_AAS = 4;; let _X86_INS_FABS = 5;; let _X86_INS_ADC = 6;; let _X86_INS_ADCX = 7;; let _X86_INS_ADD = 8;; let _X86_INS_ADDPD = 9;; let _X86_INS_ADDPS = 10;; let _X86_INS_ADDSD = 11;; let _X86_INS_ADDSS = 12;; let _X86_INS_ADDSUBPD = 13;; let _X86_INS_ADDSUBPS = 14;; let _X86_INS_FADD = 15;; let _X86_INS_FIADD = 16;; let _X86_INS_ADOX = 17;; let _X86_INS_AESDECLAST = 18;; let _X86_INS_AESDEC = 19;; let _X86_INS_AESENCLAST = 20;; let _X86_INS_AESENC = 21;; let _X86_INS_AESIMC = 22;; let _X86_INS_AESKEYGENASSIST = 23;; let _X86_INS_AND = 24;; let _X86_INS_ANDN = 25;; let _X86_INS_ANDNPD = 26;; let _X86_INS_ANDNPS = 27;; let _X86_INS_ANDPD = 28;; let _X86_INS_ANDPS = 29;; let _X86_INS_ARPL = 30;; let _X86_INS_BEXTR = 31;; let _X86_INS_BLCFILL = 32;; let _X86_INS_BLCI = 33;; let _X86_INS_BLCIC = 34;; let _X86_INS_BLCMSK = 35;; let _X86_INS_BLCS = 36;; let _X86_INS_BLENDPD = 37;; let _X86_INS_BLENDPS = 38;; let _X86_INS_BLENDVPD = 39;; let _X86_INS_BLENDVPS = 40;; let _X86_INS_BLSFILL = 41;; let _X86_INS_BLSI = 42;; let _X86_INS_BLSIC = 43;; let _X86_INS_BLSMSK = 44;; let _X86_INS_BLSR = 45;; let _X86_INS_BNDCL = 46;; let _X86_INS_BNDCN = 47;; let _X86_INS_BNDCU = 48;; let _X86_INS_BNDLDX = 49;; let _X86_INS_BNDMK = 50;; let _X86_INS_BNDMOV = 51;; let _X86_INS_BNDSTX = 52;; let _X86_INS_BOUND = 53;; let _X86_INS_BSF = 54;; let _X86_INS_BSR = 55;; let _X86_INS_BSWAP = 56;; let _X86_INS_BT = 57;; let _X86_INS_BTC = 58;; let _X86_INS_BTR = 59;; let _X86_INS_BTS = 60;; let _X86_INS_BZHI = 61;; let _X86_INS_CALL = 62;; let _X86_INS_CBW = 63;; let _X86_INS_CDQ = 64;; let _X86_INS_CDQE = 65;; let _X86_INS_FCHS = 66;; let _X86_INS_CLAC = 67;; let _X86_INS_CLC = 68;; let _X86_INS_CLD = 69;; let _X86_INS_CLDEMOTE = 70;; let _X86_INS_CLFLUSH = 71;; let _X86_INS_CLFLUSHOPT = 72;; let _X86_INS_CLGI = 73;; let _X86_INS_CLI = 74;; let _X86_INS_CLRSSBSY = 75;; let _X86_INS_CLTS = 76;; let _X86_INS_CLWB = 77;; let _X86_INS_CLZERO = 78;; let _X86_INS_CMC = 79;; let _X86_INS_CMOVA = 80;; let _X86_INS_CMOVAE = 81;; let _X86_INS_CMOVB = 82;; let _X86_INS_CMOVBE = 83;; let _X86_INS_FCMOVBE = 84;; let _X86_INS_FCMOVB = 85;; let _X86_INS_CMOVE = 86;; let _X86_INS_FCMOVE = 87;; let _X86_INS_CMOVG = 88;; let _X86_INS_CMOVGE = 89;; let _X86_INS_CMOVL = 90;; let _X86_INS_CMOVLE = 91;; let _X86_INS_FCMOVNBE = 92;; let _X86_INS_FCMOVNB = 93;; let _X86_INS_CMOVNE = 94;; let _X86_INS_FCMOVNE = 95;; let _X86_INS_CMOVNO = 96;; let _X86_INS_CMOVNP = 97;; let _X86_INS_FCMOVNU = 98;; let _X86_INS_FCMOVNP = 99;; let _X86_INS_CMOVNS = 100;; let _X86_INS_CMOVO = 101;; let _X86_INS_CMOVP = 102;; let _X86_INS_FCMOVU = 103;; let _X86_INS_CMOVS = 104;; let _X86_INS_CMP = 105;; let _X86_INS_CMPPD = 106;; let _X86_INS_CMPPS = 107;; let _X86_INS_CMPSB = 108;; let _X86_INS_CMPSD = 109;; let _X86_INS_CMPSQ = 110;; let _X86_INS_CMPSS = 111;; let _X86_INS_CMPSW = 112;; let _X86_INS_CMPXCHG16B = 113;; let _X86_INS_CMPXCHG = 114;; let _X86_INS_CMPXCHG8B = 115;; let _X86_INS_COMISD = 116;; let _X86_INS_COMISS = 117;; let _X86_INS_FCOMP = 118;; let _X86_INS_FCOMPI = 119;; let _X86_INS_FCOMI = 120;; let _X86_INS_FCOM = 121;; let _X86_INS_FCOS = 122;; let _X86_INS_CPUID = 123;; let _X86_INS_CQO = 124;; let _X86_INS_CRC32 = 125;; let _X86_INS_CVTDQ2PD = 126;; let _X86_INS_CVTDQ2PS = 127;; let _X86_INS_CVTPD2DQ = 128;; let _X86_INS_CVTPD2PS = 129;; let _X86_INS_CVTPS2DQ = 130;; let _X86_INS_CVTPS2PD = 131;; let _X86_INS_CVTSD2SI = 132;; let _X86_INS_CVTSD2SS = 133;; let _X86_INS_CVTSI2SD = 134;; let _X86_INS_CVTSI2SS = 135;; let _X86_INS_CVTSS2SD = 136;; let _X86_INS_CVTSS2SI = 137;; let _X86_INS_CVTTPD2DQ = 138;; let _X86_INS_CVTTPS2DQ = 139;; let _X86_INS_CVTTSD2SI = 140;; let _X86_INS_CVTTSS2SI = 141;; let _X86_INS_CWD = 142;; let _X86_INS_CWDE = 143;; let _X86_INS_DAA = 144;; let _X86_INS_DAS = 145;; let _X86_INS_DATA16 = 146;; let _X86_INS_DEC = 147;; let _X86_INS_DIV = 148;; let _X86_INS_DIVPD = 149;; let _X86_INS_DIVPS = 150;; let _X86_INS_FDIVR = 151;; let _X86_INS_FIDIVR = 152;; let _X86_INS_FDIVRP = 153;; let _X86_INS_DIVSD = 154;; let _X86_INS_DIVSS = 155;; let _X86_INS_FDIV = 156;; let _X86_INS_FIDIV = 157;; let _X86_INS_FDIVP = 158;; let _X86_INS_DPPD = 159;; let _X86_INS_DPPS = 160;; let _X86_INS_ENCLS = 161;; let _X86_INS_ENCLU = 162;; let _X86_INS_ENCLV = 163;; let _X86_INS_ENDBR32 = 164;; let _X86_INS_ENDBR64 = 165;; let _X86_INS_ENTER = 166;; let _X86_INS_EXTRACTPS = 167;; let _X86_INS_EXTRQ = 168;; let _X86_INS_F2XM1 = 169;; let _X86_INS_LCALL = 170;; let _X86_INS_LJMP = 171;; let _X86_INS_JMP = 172;; let _X86_INS_FBLD = 173;; let _X86_INS_FBSTP = 174;; let _X86_INS_FCOMPP = 175;; let _X86_INS_FDECSTP = 176;; let _X86_INS_FDISI8087_NOP = 177;; let _X86_INS_FEMMS = 178;; let _X86_INS_FENI8087_NOP = 179;; let _X86_INS_FFREE = 180;; let _X86_INS_FFREEP = 181;; let _X86_INS_FICOM = 182;; let _X86_INS_FICOMP = 183;; let _X86_INS_FINCSTP = 184;; let _X86_INS_FLDCW = 185;; let _X86_INS_FLDENV = 186;; let _X86_INS_FLDL2E = 187;; let _X86_INS_FLDL2T = 188;; let _X86_INS_FLDLG2 = 189;; let _X86_INS_FLDLN2 = 190;; let _X86_INS_FLDPI = 191;; let _X86_INS_FNCLEX = 192;; let _X86_INS_FNINIT = 193;; let _X86_INS_FNOP = 194;; let _X86_INS_FNSTCW = 195;; let _X86_INS_FNSTSW = 196;; let _X86_INS_FPATAN = 197;; let _X86_INS_FSTPNCE = 198;; let _X86_INS_FPREM = 199;; let _X86_INS_FPREM1 = 200;; let _X86_INS_FPTAN = 201;; let _X86_INS_FRNDINT = 202;; let _X86_INS_FRSTOR = 203;; let _X86_INS_FNSAVE = 204;; let _X86_INS_FSCALE = 205;; let _X86_INS_FSETPM = 206;; let _X86_INS_FSINCOS = 207;; let _X86_INS_FNSTENV = 208;; let _X86_INS_FXAM = 209;; let _X86_INS_FXRSTOR = 210;; let _X86_INS_FXRSTOR64 = 211;; let _X86_INS_FXSAVE = 212;; let _X86_INS_FXSAVE64 = 213;; let _X86_INS_FXTRACT = 214;; let _X86_INS_FYL2X = 215;; let _X86_INS_FYL2XP1 = 216;; let _X86_INS_GETSEC = 217;; let _X86_INS_GF2P8AFFINEINVQB = 218;; let _X86_INS_GF2P8AFFINEQB = 219;; let _X86_INS_GF2P8MULB = 220;; let _X86_INS_HADDPD = 221;; let _X86_INS_HADDPS = 222;; let _X86_INS_HLT = 223;; let _X86_INS_HSUBPD = 224;; let _X86_INS_HSUBPS = 225;; let _X86_INS_IDIV = 226;; let _X86_INS_FILD = 227;; let _X86_INS_IMUL = 228;; let _X86_INS_IN = 229;; let _X86_INS_INC = 230;; let _X86_INS_INCSSPD = 231;; let _X86_INS_INCSSPQ = 232;; let _X86_INS_INSB = 233;; let _X86_INS_INSERTPS = 234;; let _X86_INS_INSERTQ = 235;; let _X86_INS_INSD = 236;; let _X86_INS_INSW = 237;; let _X86_INS_INT = 238;; let _X86_INS_INT1 = 239;; let _X86_INS_INT3 = 240;; let _X86_INS_INTO = 241;; let _X86_INS_INVD = 242;; let _X86_INS_INVEPT = 243;; let _X86_INS_INVLPG = 244;; let _X86_INS_INVLPGA = 245;; let _X86_INS_INVPCID = 246;; let _X86_INS_INVVPID = 247;; let _X86_INS_IRET = 248;; let _X86_INS_IRETD = 249;; let _X86_INS_IRETQ = 250;; let _X86_INS_FISTTP = 251;; let _X86_INS_FIST = 252;; let _X86_INS_FISTP = 253;; let _X86_INS_JAE = 254;; let _X86_INS_JA = 255;; let _X86_INS_JBE = 256;; let _X86_INS_JB = 257;; let _X86_INS_JCXZ = 258;; let _X86_INS_JECXZ = 259;; let _X86_INS_JE = 260;; let _X86_INS_JGE = 261;; let _X86_INS_JG = 262;; let _X86_INS_JLE = 263;; let _X86_INS_JL = 264;; let _X86_INS_JNE = 265;; let _X86_INS_JNO = 266;; let _X86_INS_JNP = 267;; let _X86_INS_JNS = 268;; let _X86_INS_JO = 269;; let _X86_INS_JP = 270;; let _X86_INS_JRCXZ = 271;; let _X86_INS_JS = 272;; let _X86_INS_KADDB = 273;; let _X86_INS_KADDD = 274;; let _X86_INS_KADDQ = 275;; let _X86_INS_KADDW = 276;; let _X86_INS_KANDB = 277;; let _X86_INS_KANDD = 278;; let _X86_INS_KANDNB = 279;; let _X86_INS_KANDND = 280;; let _X86_INS_KANDNQ = 281;; let _X86_INS_KANDNW = 282;; let _X86_INS_KANDQ = 283;; let _X86_INS_KANDW = 284;; let _X86_INS_KMOVB = 285;; let _X86_INS_KMOVD = 286;; let _X86_INS_KMOVQ = 287;; let _X86_INS_KMOVW = 288;; let _X86_INS_KNOTB = 289;; let _X86_INS_KNOTD = 290;; let _X86_INS_KNOTQ = 291;; let _X86_INS_KNOTW = 292;; let _X86_INS_KORB = 293;; let _X86_INS_KORD = 294;; let _X86_INS_KORQ = 295;; let _X86_INS_KORTESTB = 296;; let _X86_INS_KORTESTD = 297;; let _X86_INS_KORTESTQ = 298;; let _X86_INS_KORTESTW = 299;; let _X86_INS_KORW = 300;; let _X86_INS_KSHIFTLB = 301;; let _X86_INS_KSHIFTLD = 302;; let _X86_INS_KSHIFTLQ = 303;; let _X86_INS_KSHIFTLW = 304;; let _X86_INS_KSHIFTRB = 305;; let _X86_INS_KSHIFTRD = 306;; let _X86_INS_KSHIFTRQ = 307;; let _X86_INS_KSHIFTRW = 308;; let _X86_INS_KTESTB = 309;; let _X86_INS_KTESTD = 310;; let _X86_INS_KTESTQ = 311;; let _X86_INS_KTESTW = 312;; let _X86_INS_KUNPCKBW = 313;; let _X86_INS_KUNPCKDQ = 314;; let _X86_INS_KUNPCKWD = 315;; let _X86_INS_KXNORB = 316;; let _X86_INS_KXNORD = 317;; let _X86_INS_KXNORQ = 318;; let _X86_INS_KXNORW = 319;; let _X86_INS_KXORB = 320;; let _X86_INS_KXORD = 321;; let _X86_INS_KXORQ = 322;; let _X86_INS_KXORW = 323;; let _X86_INS_LAHF = 324;; let _X86_INS_LAR = 325;; let _X86_INS_LDDQU = 326;; let _X86_INS_LDMXCSR = 327;; let _X86_INS_LDS = 328;; let _X86_INS_FLDZ = 329;; let _X86_INS_FLD1 = 330;; let _X86_INS_FLD = 331;; let _X86_INS_LEA = 332;; let _X86_INS_LEAVE = 333;; let _X86_INS_LES = 334;; let _X86_INS_LFENCE = 335;; let _X86_INS_LFS = 336;; let _X86_INS_LGDT = 337;; let _X86_INS_LGS = 338;; let _X86_INS_LIDT = 339;; let _X86_INS_LLDT = 340;; let _X86_INS_LLWPCB = 341;; let _X86_INS_LMSW = 342;; let _X86_INS_LOCK = 343;; let _X86_INS_LODSB = 344;; let _X86_INS_LODSD = 345;; let _X86_INS_LODSQ = 346;; let _X86_INS_LODSW = 347;; let _X86_INS_LOOP = 348;; let _X86_INS_LOOPE = 349;; let _X86_INS_LOOPNE = 350;; let _X86_INS_RETF = 351;; let _X86_INS_RETFQ = 352;; let _X86_INS_LSL = 353;; let _X86_INS_LSS = 354;; let _X86_INS_LTR = 355;; let _X86_INS_LWPINS = 356;; let _X86_INS_LWPVAL = 357;; let _X86_INS_LZCNT = 358;; let _X86_INS_MASKMOVDQU = 359;; let _X86_INS_MAXPD = 360;; let _X86_INS_MAXPS = 361;; let _X86_INS_MAXSD = 362;; let _X86_INS_MAXSS = 363;; let _X86_INS_MFENCE = 364;; let _X86_INS_MINPD = 365;; let _X86_INS_MINPS = 366;; let _X86_INS_MINSD = 367;; let _X86_INS_MINSS = 368;; let _X86_INS_CVTPD2PI = 369;; let _X86_INS_CVTPI2PD = 370;; let _X86_INS_CVTPI2PS = 371;; let _X86_INS_CVTPS2PI = 372;; let _X86_INS_CVTTPD2PI = 373;; let _X86_INS_CVTTPS2PI = 374;; let _X86_INS_EMMS = 375;; let _X86_INS_MASKMOVQ = 376;; let _X86_INS_MOVD = 377;; let _X86_INS_MOVQ = 378;; let _X86_INS_MOVDQ2Q = 379;; let _X86_INS_MOVNTQ = 380;; let _X86_INS_MOVQ2DQ = 381;; let _X86_INS_PABSB = 382;; let _X86_INS_PABSD = 383;; let _X86_INS_PABSW = 384;; let _X86_INS_PACKSSDW = 385;; let _X86_INS_PACKSSWB = 386;; let _X86_INS_PACKUSWB = 387;; let _X86_INS_PADDB = 388;; let _X86_INS_PADDD = 389;; let _X86_INS_PADDQ = 390;; let _X86_INS_PADDSB = 391;; let _X86_INS_PADDSW = 392;; let _X86_INS_PADDUSB = 393;; let _X86_INS_PADDUSW = 394;; let _X86_INS_PADDW = 395;; let _X86_INS_PALIGNR = 396;; let _X86_INS_PANDN = 397;; let _X86_INS_PAND = 398;; let _X86_INS_PAVGB = 399;; let _X86_INS_PAVGW = 400;; let _X86_INS_PCMPEQB = 401;; let _X86_INS_PCMPEQD = 402;; let _X86_INS_PCMPEQW = 403;; let _X86_INS_PCMPGTB = 404;; let _X86_INS_PCMPGTD = 405;; let _X86_INS_PCMPGTW = 406;; let _X86_INS_PEXTRW = 407;; let _X86_INS_PHADDD = 408;; let _X86_INS_PHADDSW = 409;; let _X86_INS_PHADDW = 410;; let _X86_INS_PHSUBD = 411;; let _X86_INS_PHSUBSW = 412;; let _X86_INS_PHSUBW = 413;; let _X86_INS_PINSRW = 414;; let _X86_INS_PMADDUBSW = 415;; let _X86_INS_PMADDWD = 416;; let _X86_INS_PMAXSW = 417;; let _X86_INS_PMAXUB = 418;; let _X86_INS_PMINSW = 419;; let _X86_INS_PMINUB = 420;; let _X86_INS_PMOVMSKB = 421;; let _X86_INS_PMULHRSW = 422;; let _X86_INS_PMULHUW = 423;; let _X86_INS_PMULHW = 424;; let _X86_INS_PMULLW = 425;; let _X86_INS_PMULUDQ = 426;; let _X86_INS_POR = 427;; let _X86_INS_PSADBW = 428;; let _X86_INS_PSHUFB = 429;; let _X86_INS_PSHUFW = 430;; let _X86_INS_PSIGNB = 431;; let _X86_INS_PSIGND = 432;; let _X86_INS_PSIGNW = 433;; let _X86_INS_PSLLD = 434;; let _X86_INS_PSLLQ = 435;; let _X86_INS_PSLLW = 436;; let _X86_INS_PSRAD = 437;; let _X86_INS_PSRAW = 438;; let _X86_INS_PSRLD = 439;; let _X86_INS_PSRLQ = 440;; let _X86_INS_PSRLW = 441;; let _X86_INS_PSUBB = 442;; let _X86_INS_PSUBD = 443;; let _X86_INS_PSUBQ = 444;; let _X86_INS_PSUBSB = 445;; let _X86_INS_PSUBSW = 446;; let _X86_INS_PSUBUSB = 447;; let _X86_INS_PSUBUSW = 448;; let _X86_INS_PSUBW = 449;; let _X86_INS_PUNPCKHBW = 450;; let _X86_INS_PUNPCKHDQ = 451;; let _X86_INS_PUNPCKHWD = 452;; let _X86_INS_PUNPCKLBW = 453;; let _X86_INS_PUNPCKLDQ = 454;; let _X86_INS_PUNPCKLWD = 455;; let _X86_INS_PXOR = 456;; let _X86_INS_MONITORX = 457;; let _X86_INS_MONITOR = 458;; let _X86_INS_MONTMUL = 459;; let _X86_INS_MOV = 460;; let _X86_INS_MOVABS = 461;; let _X86_INS_MOVAPD = 462;; let _X86_INS_MOVAPS = 463;; let _X86_INS_MOVBE = 464;; let _X86_INS_MOVDDUP = 465;; let _X86_INS_MOVDIR64B = 466;; let _X86_INS_MOVDIRI = 467;; let _X86_INS_MOVDQA = 468;; let _X86_INS_MOVDQU = 469;; let _X86_INS_MOVHLPS = 470;; let _X86_INS_MOVHPD = 471;; let _X86_INS_MOVHPS = 472;; let _X86_INS_MOVLHPS = 473;; let _X86_INS_MOVLPD = 474;; let _X86_INS_MOVLPS = 475;; let _X86_INS_MOVMSKPD = 476;; let _X86_INS_MOVMSKPS = 477;; let _X86_INS_MOVNTDQA = 478;; let _X86_INS_MOVNTDQ = 479;; let _X86_INS_MOVNTI = 480;; let _X86_INS_MOVNTPD = 481;; let _X86_INS_MOVNTPS = 482;; let _X86_INS_MOVNTSD = 483;; let _X86_INS_MOVNTSS = 484;; let _X86_INS_MOVSB = 485;; let _X86_INS_MOVSD = 486;; let _X86_INS_MOVSHDUP = 487;; let _X86_INS_MOVSLDUP = 488;; let _X86_INS_MOVSQ = 489;; let _X86_INS_MOVSS = 490;; let _X86_INS_MOVSW = 491;; let _X86_INS_MOVSX = 492;; let _X86_INS_MOVSXD = 493;; let _X86_INS_MOVUPD = 494;; let _X86_INS_MOVUPS = 495;; let _X86_INS_MOVZX = 496;; let _X86_INS_MPSADBW = 497;; let _X86_INS_MUL = 498;; let _X86_INS_MULPD = 499;; let _X86_INS_MULPS = 500;; let _X86_INS_MULSD = 501;; let _X86_INS_MULSS = 502;; let _X86_INS_MULX = 503;; let _X86_INS_FMUL = 504;; let _X86_INS_FIMUL = 505;; let _X86_INS_FMULP = 506;; let _X86_INS_MWAITX = 507;; let _X86_INS_MWAIT = 508;; let _X86_INS_NEG = 509;; let _X86_INS_NOP = 510;; let _X86_INS_NOT = 511;; let _X86_INS_OR = 512;; let _X86_INS_ORPD = 513;; let _X86_INS_ORPS = 514;; let _X86_INS_OUT = 515;; let _X86_INS_OUTSB = 516;; let _X86_INS_OUTSD = 517;; let _X86_INS_OUTSW = 518;; let _X86_INS_PACKUSDW = 519;; let _X86_INS_PAUSE = 520;; let _X86_INS_PAVGUSB = 521;; let _X86_INS_PBLENDVB = 522;; let _X86_INS_PBLENDW = 523;; let _X86_INS_PCLMULQDQ = 524;; let _X86_INS_PCMPEQQ = 525;; let _X86_INS_PCMPESTRI = 526;; let _X86_INS_PCMPESTRM = 527;; let _X86_INS_PCMPGTQ = 528;; let _X86_INS_PCMPISTRI = 529;; let _X86_INS_PCMPISTRM = 530;; let _X86_INS_PCONFIG = 531;; let _X86_INS_PDEP = 532;; let _X86_INS_PEXT = 533;; let _X86_INS_PEXTRB = 534;; let _X86_INS_PEXTRD = 535;; let _X86_INS_PEXTRQ = 536;; let _X86_INS_PF2ID = 537;; let _X86_INS_PF2IW = 538;; let _X86_INS_PFACC = 539;; let _X86_INS_PFADD = 540;; let _X86_INS_PFCMPEQ = 541;; let _X86_INS_PFCMPGE = 542;; let _X86_INS_PFCMPGT = 543;; let _X86_INS_PFMAX = 544;; let _X86_INS_PFMIN = 545;; let _X86_INS_PFMUL = 546;; let _X86_INS_PFNACC = 547;; let _X86_INS_PFPNACC = 548;; let _X86_INS_PFRCPIT1 = 549;; let _X86_INS_PFRCPIT2 = 550;; let _X86_INS_PFRCP = 551;; let _X86_INS_PFRSQIT1 = 552;; let _X86_INS_PFRSQRT = 553;; let _X86_INS_PFSUBR = 554;; let _X86_INS_PFSUB = 555;; let _X86_INS_PHMINPOSUW = 556;; let _X86_INS_PI2FD = 557;; let _X86_INS_PI2FW = 558;; let _X86_INS_PINSRB = 559;; let _X86_INS_PINSRD = 560;; let _X86_INS_PINSRQ = 561;; let _X86_INS_PMAXSB = 562;; let _X86_INS_PMAXSD = 563;; let _X86_INS_PMAXUD = 564;; let _X86_INS_PMAXUW = 565;; let _X86_INS_PMINSB = 566;; let _X86_INS_PMINSD = 567;; let _X86_INS_PMINUD = 568;; let _X86_INS_PMINUW = 569;; let _X86_INS_PMOVSXBD = 570;; let _X86_INS_PMOVSXBQ = 571;; let _X86_INS_PMOVSXBW = 572;; let _X86_INS_PMOVSXDQ = 573;; let _X86_INS_PMOVSXWD = 574;; let _X86_INS_PMOVSXWQ = 575;; let _X86_INS_PMOVZXBD = 576;; let _X86_INS_PMOVZXBQ = 577;; let _X86_INS_PMOVZXBW = 578;; let _X86_INS_PMOVZXDQ = 579;; let _X86_INS_PMOVZXWD = 580;; let _X86_INS_PMOVZXWQ = 581;; let _X86_INS_PMULDQ = 582;; let _X86_INS_PMULHRW = 583;; let _X86_INS_PMULLD = 584;; let _X86_INS_POP = 585;; let _X86_INS_POPAW = 586;; let _X86_INS_POPAL = 587;; let _X86_INS_POPCNT = 588;; let _X86_INS_POPF = 589;; let _X86_INS_POPFD = 590;; let _X86_INS_POPFQ = 591;; let _X86_INS_PREFETCH = 592;; let _X86_INS_PREFETCHNTA = 593;; let _X86_INS_PREFETCHT0 = 594;; let _X86_INS_PREFETCHT1 = 595;; let _X86_INS_PREFETCHT2 = 596;; let _X86_INS_PREFETCHW = 597;; let _X86_INS_PREFETCHWT1 = 598;; let _X86_INS_PSHUFD = 599;; let _X86_INS_PSHUFHW = 600;; let _X86_INS_PSHUFLW = 601;; let _X86_INS_PSLLDQ = 602;; let _X86_INS_PSRLDQ = 603;; let _X86_INS_PSWAPD = 604;; let _X86_INS_PTEST = 605;; let _X86_INS_PTWRITE = 606;; let _X86_INS_PUNPCKHQDQ = 607;; let _X86_INS_PUNPCKLQDQ = 608;; let _X86_INS_PUSH = 609;; let _X86_INS_PUSHAW = 610;; let _X86_INS_PUSHAL = 611;; let _X86_INS_PUSHF = 612;; let _X86_INS_PUSHFD = 613;; let _X86_INS_PUSHFQ = 614;; let _X86_INS_RCL = 615;; let _X86_INS_RCPPS = 616;; let _X86_INS_RCPSS = 617;; let _X86_INS_RCR = 618;; let _X86_INS_RDFSBASE = 619;; let _X86_INS_RDGSBASE = 620;; let _X86_INS_RDMSR = 621;; let _X86_INS_RDPID = 622;; let _X86_INS_RDPKRU = 623;; let _X86_INS_RDPMC = 624;; let _X86_INS_RDRAND = 625;; let _X86_INS_RDSEED = 626;; let _X86_INS_RDSSPD = 627;; let _X86_INS_RDSSPQ = 628;; let _X86_INS_RDTSC = 629;; let _X86_INS_RDTSCP = 630;; let _X86_INS_REPNE = 631;; let _X86_INS_REP = 632;; let _X86_INS_RET = 633;; let _X86_INS_REX64 = 634;; let _X86_INS_ROL = 635;; let _X86_INS_ROR = 636;; let _X86_INS_RORX = 637;; let _X86_INS_ROUNDPD = 638;; let _X86_INS_ROUNDPS = 639;; let _X86_INS_ROUNDSD = 640;; let _X86_INS_ROUNDSS = 641;; let _X86_INS_RSM = 642;; let _X86_INS_RSQRTPS = 643;; let _X86_INS_RSQRTSS = 644;; let _X86_INS_RSTORSSP = 645;; let _X86_INS_SAHF = 646;; let _X86_INS_SAL = 647;; let _X86_INS_SALC = 648;; let _X86_INS_SAR = 649;; let _X86_INS_SARX = 650;; let _X86_INS_SAVEPREVSSP = 651;; let _X86_INS_SBB = 652;; let _X86_INS_SCASB = 653;; let _X86_INS_SCASD = 654;; let _X86_INS_SCASQ = 655;; let _X86_INS_SCASW = 656;; let _X86_INS_SETAE = 657;; let _X86_INS_SETA = 658;; let _X86_INS_SETBE = 659;; let _X86_INS_SETB = 660;; let _X86_INS_SETE = 661;; let _X86_INS_SETGE = 662;; let _X86_INS_SETG = 663;; let _X86_INS_SETLE = 664;; let _X86_INS_SETL = 665;; let _X86_INS_SETNE = 666;; let _X86_INS_SETNO = 667;; let _X86_INS_SETNP = 668;; let _X86_INS_SETNS = 669;; let _X86_INS_SETO = 670;; let _X86_INS_SETP = 671;; let _X86_INS_SETSSBSY = 672;; let _X86_INS_SETS = 673;; let _X86_INS_SFENCE = 674;; let _X86_INS_SGDT = 675;; let _X86_INS_SHA1MSG1 = 676;; let _X86_INS_SHA1MSG2 = 677;; let _X86_INS_SHA1NEXTE = 678;; let _X86_INS_SHA1RNDS4 = 679;; let _X86_INS_SHA256MSG1 = 680;; let _X86_INS_SHA256MSG2 = 681;; let _X86_INS_SHA256RNDS2 = 682;; let _X86_INS_SHL = 683;; let _X86_INS_SHLD = 684;; let _X86_INS_SHLX = 685;; let _X86_INS_SHR = 686;; let _X86_INS_SHRD = 687;; let _X86_INS_SHRX = 688;; let _X86_INS_SHUFPD = 689;; let _X86_INS_SHUFPS = 690;; let _X86_INS_SIDT = 691;; let _X86_INS_FSIN = 692;; let _X86_INS_SKINIT = 693;; let _X86_INS_SLDT = 694;; let _X86_INS_SLWPCB = 695;; let _X86_INS_SMSW = 696;; let _X86_INS_SQRTPD = 697;; let _X86_INS_SQRTPS = 698;; let _X86_INS_SQRTSD = 699;; let _X86_INS_SQRTSS = 700;; let _X86_INS_FSQRT = 701;; let _X86_INS_STAC = 702;; let _X86_INS_STC = 703;; let _X86_INS_STD = 704;; let _X86_INS_STGI = 705;; let _X86_INS_STI = 706;; let _X86_INS_STMXCSR = 707;; let _X86_INS_STOSB = 708;; let _X86_INS_STOSD = 709;; let _X86_INS_STOSQ = 710;; let _X86_INS_STOSW = 711;; let _X86_INS_STR = 712;; let _X86_INS_FST = 713;; let _X86_INS_FSTP = 714;; let _X86_INS_SUB = 715;; let _X86_INS_SUBPD = 716;; let _X86_INS_SUBPS = 717;; let _X86_INS_FSUBR = 718;; let _X86_INS_FISUBR = 719;; let _X86_INS_FSUBRP = 720;; let _X86_INS_SUBSD = 721;; let _X86_INS_SUBSS = 722;; let _X86_INS_FSUB = 723;; let _X86_INS_FISUB = 724;; let _X86_INS_FSUBP = 725;; let _X86_INS_SWAPGS = 726;; let _X86_INS_SYSCALL = 727;; let _X86_INS_SYSENTER = 728;; let _X86_INS_SYSEXIT = 729;; let _X86_INS_SYSEXITQ = 730;; let _X86_INS_SYSRET = 731;; let _X86_INS_SYSRETQ = 732;; let _X86_INS_T1MSKC = 733;; let _X86_INS_TEST = 734;; let _X86_INS_TPAUSE = 735;; let _X86_INS_FTST = 736;; let _X86_INS_TZCNT = 737;; let _X86_INS_TZMSK = 738;; let _X86_INS_UCOMISD = 739;; let _X86_INS_UCOMISS = 740;; let _X86_INS_FUCOMPI = 741;; let _X86_INS_FUCOMI = 742;; let _X86_INS_FUCOMPP = 743;; let _X86_INS_FUCOMP = 744;; let _X86_INS_FUCOM = 745;; let _X86_INS_UD0 = 746;; let _X86_INS_UD1 = 747;; let _X86_INS_UD2 = 748;; let _X86_INS_UMONITOR = 749;; let _X86_INS_UMWAIT = 750;; let _X86_INS_UNPCKHPD = 751;; let _X86_INS_UNPCKHPS = 752;; let _X86_INS_UNPCKLPD = 753;; let _X86_INS_UNPCKLPS = 754;; let _X86_INS_V4FMADDPS = 755;; let _X86_INS_V4FMADDSS = 756;; let _X86_INS_V4FNMADDPS = 757;; let _X86_INS_V4FNMADDSS = 758;; let _X86_INS_VADDPD = 759;; let _X86_INS_VADDPS = 760;; let _X86_INS_VADDSD = 761;; let _X86_INS_VADDSS = 762;; let _X86_INS_VADDSUBPD = 763;; let _X86_INS_VADDSUBPS = 764;; let _X86_INS_VAESDECLAST = 765;; let _X86_INS_VAESDEC = 766;; let _X86_INS_VAESENCLAST = 767;; let _X86_INS_VAESENC = 768;; let _X86_INS_VAESIMC = 769;; let _X86_INS_VAESKEYGENASSIST = 770;; let _X86_INS_VALIGND = 771;; let _X86_INS_VALIGNQ = 772;; let _X86_INS_VANDNPD = 773;; let _X86_INS_VANDNPS = 774;; let _X86_INS_VANDPD = 775;; let _X86_INS_VANDPS = 776;; let _X86_INS_VBLENDMPD = 777;; let _X86_INS_VBLENDMPS = 778;; let _X86_INS_VBLENDPD = 779;; let _X86_INS_VBLENDPS = 780;; let _X86_INS_VBLENDVPD = 781;; let _X86_INS_VBLENDVPS = 782;; let _X86_INS_VBROADCASTF128 = 783;; let _X86_INS_VBROADCASTF32X2 = 784;; let _X86_INS_VBROADCASTF32X4 = 785;; let _X86_INS_VBROADCASTF32X8 = 786;; let _X86_INS_VBROADCASTF64X2 = 787;; let _X86_INS_VBROADCASTF64X4 = 788;; let _X86_INS_VBROADCASTI128 = 789;; let _X86_INS_VBROADCASTI32X2 = 790;; let _X86_INS_VBROADCASTI32X4 = 791;; let _X86_INS_VBROADCASTI32X8 = 792;; let _X86_INS_VBROADCASTI64X2 = 793;; let _X86_INS_VBROADCASTI64X4 = 794;; let _X86_INS_VBROADCASTSD = 795;; let _X86_INS_VBROADCASTSS = 796;; let _X86_INS_VCMP = 797;; let _X86_INS_VCMPPD = 798;; let _X86_INS_VCMPPS = 799;; let _X86_INS_VCMPSD = 800;; let _X86_INS_VCMPSS = 801;; let _X86_INS_VCOMISD = 802;; let _X86_INS_VCOMISS = 803;; let _X86_INS_VCOMPRESSPD = 804;; let _X86_INS_VCOMPRESSPS = 805;; let _X86_INS_VCVTDQ2PD = 806;; let _X86_INS_VCVTDQ2PS = 807;; let _X86_INS_VCVTPD2DQ = 808;; let _X86_INS_VCVTPD2PS = 809;; let _X86_INS_VCVTPD2QQ = 810;; let _X86_INS_VCVTPD2UDQ = 811;; let _X86_INS_VCVTPD2UQQ = 812;; let _X86_INS_VCVTPH2PS = 813;; let _X86_INS_VCVTPS2DQ = 814;; let _X86_INS_VCVTPS2PD = 815;; let _X86_INS_VCVTPS2PH = 816;; let _X86_INS_VCVTPS2QQ = 817;; let _X86_INS_VCVTPS2UDQ = 818;; let _X86_INS_VCVTPS2UQQ = 819;; let _X86_INS_VCVTQQ2PD = 820;; let _X86_INS_VCVTQQ2PS = 821;; let _X86_INS_VCVTSD2SI = 822;; let _X86_INS_VCVTSD2SS = 823;; let _X86_INS_VCVTSD2USI = 824;; let _X86_INS_VCVTSI2SD = 825;; let _X86_INS_VCVTSI2SS = 826;; let _X86_INS_VCVTSS2SD = 827;; let _X86_INS_VCVTSS2SI = 828;; let _X86_INS_VCVTSS2USI = 829;; let _X86_INS_VCVTTPD2DQ = 830;; let _X86_INS_VCVTTPD2QQ = 831;; let _X86_INS_VCVTTPD2UDQ = 832;; let _X86_INS_VCVTTPD2UQQ = 833;; let _X86_INS_VCVTTPS2DQ = 834;; let _X86_INS_VCVTTPS2QQ = 835;; let _X86_INS_VCVTTPS2UDQ = 836;; let _X86_INS_VCVTTPS2UQQ = 837;; let _X86_INS_VCVTTSD2SI = 838;; let _X86_INS_VCVTTSD2USI = 839;; let _X86_INS_VCVTTSS2SI = 840;; let _X86_INS_VCVTTSS2USI = 841;; let _X86_INS_VCVTUDQ2PD = 842;; let _X86_INS_VCVTUDQ2PS = 843;; let _X86_INS_VCVTUQQ2PD = 844;; let _X86_INS_VCVTUQQ2PS = 845;; let _X86_INS_VCVTUSI2SD = 846;; let _X86_INS_VCVTUSI2SS = 847;; let _X86_INS_VDBPSADBW = 848;; let _X86_INS_VDIVPD = 849;; let _X86_INS_VDIVPS = 850;; let _X86_INS_VDIVSD = 851;; let _X86_INS_VDIVSS = 852;; let _X86_INS_VDPPD = 853;; let _X86_INS_VDPPS = 854;; let _X86_INS_VERR = 855;; let _X86_INS_VERW = 856;; let _X86_INS_VEXP2PD = 857;; let _X86_INS_VEXP2PS = 858;; let _X86_INS_VEXPANDPD = 859;; let _X86_INS_VEXPANDPS = 860;; let _X86_INS_VEXTRACTF128 = 861;; let _X86_INS_VEXTRACTF32X4 = 862;; let _X86_INS_VEXTRACTF32X8 = 863;; let _X86_INS_VEXTRACTF64X2 = 864;; let _X86_INS_VEXTRACTF64X4 = 865;; let _X86_INS_VEXTRACTI128 = 866;; let _X86_INS_VEXTRACTI32X4 = 867;; let _X86_INS_VEXTRACTI32X8 = 868;; let _X86_INS_VEXTRACTI64X2 = 869;; let _X86_INS_VEXTRACTI64X4 = 870;; let _X86_INS_VEXTRACTPS = 871;; let _X86_INS_VFIXUPIMMPD = 872;; let _X86_INS_VFIXUPIMMPS = 873;; let _X86_INS_VFIXUPIMMSD = 874;; let _X86_INS_VFIXUPIMMSS = 875;; let _X86_INS_VFMADD132PD = 876;; let _X86_INS_VFMADD132PS = 877;; let _X86_INS_VFMADD132SD = 878;; let _X86_INS_VFMADD132SS = 879;; let _X86_INS_VFMADD213PD = 880;; let _X86_INS_VFMADD213PS = 881;; let _X86_INS_VFMADD213SD = 882;; let _X86_INS_VFMADD213SS = 883;; let _X86_INS_VFMADD231PD = 884;; let _X86_INS_VFMADD231PS = 885;; let _X86_INS_VFMADD231SD = 886;; let _X86_INS_VFMADD231SS = 887;; let _X86_INS_VFMADDPD = 888;; let _X86_INS_VFMADDPS = 889;; let _X86_INS_VFMADDSD = 890;; let _X86_INS_VFMADDSS = 891;; let _X86_INS_VFMADDSUB132PD = 892;; let _X86_INS_VFMADDSUB132PS = 893;; let _X86_INS_VFMADDSUB213PD = 894;; let _X86_INS_VFMADDSUB213PS = 895;; let _X86_INS_VFMADDSUB231PD = 896;; let _X86_INS_VFMADDSUB231PS = 897;; let _X86_INS_VFMADDSUBPD = 898;; let _X86_INS_VFMADDSUBPS = 899;; let _X86_INS_VFMSUB132PD = 900;; let _X86_INS_VFMSUB132PS = 901;; let _X86_INS_VFMSUB132SD = 902;; let _X86_INS_VFMSUB132SS = 903;; let _X86_INS_VFMSUB213PD = 904;; let _X86_INS_VFMSUB213PS = 905;; let _X86_INS_VFMSUB213SD = 906;; let _X86_INS_VFMSUB213SS = 907;; let _X86_INS_VFMSUB231PD = 908;; let _X86_INS_VFMSUB231PS = 909;; let _X86_INS_VFMSUB231SD = 910;; let _X86_INS_VFMSUB231SS = 911;; let _X86_INS_VFMSUBADD132PD = 912;; let _X86_INS_VFMSUBADD132PS = 913;; let _X86_INS_VFMSUBADD213PD = 914;; let _X86_INS_VFMSUBADD213PS = 915;; let _X86_INS_VFMSUBADD231PD = 916;; let _X86_INS_VFMSUBADD231PS = 917;; let _X86_INS_VFMSUBADDPD = 918;; let _X86_INS_VFMSUBADDPS = 919;; let _X86_INS_VFMSUBPD = 920;; let _X86_INS_VFMSUBPS = 921;; let _X86_INS_VFMSUBSD = 922;; let _X86_INS_VFMSUBSS = 923;; let _X86_INS_VFNMADD132PD = 924;; let _X86_INS_VFNMADD132PS = 925;; let _X86_INS_VFNMADD132SD = 926;; let _X86_INS_VFNMADD132SS = 927;; let _X86_INS_VFNMADD213PD = 928;; let _X86_INS_VFNMADD213PS = 929;; let _X86_INS_VFNMADD213SD = 930;; let _X86_INS_VFNMADD213SS = 931;; let _X86_INS_VFNMADD231PD = 932;; let _X86_INS_VFNMADD231PS = 933;; let _X86_INS_VFNMADD231SD = 934;; let _X86_INS_VFNMADD231SS = 935;; let _X86_INS_VFNMADDPD = 936;; let _X86_INS_VFNMADDPS = 937;; let _X86_INS_VFNMADDSD = 938;; let _X86_INS_VFNMADDSS = 939;; let _X86_INS_VFNMSUB132PD = 940;; let _X86_INS_VFNMSUB132PS = 941;; let _X86_INS_VFNMSUB132SD = 942;; let _X86_INS_VFNMSUB132SS = 943;; let _X86_INS_VFNMSUB213PD = 944;; let _X86_INS_VFNMSUB213PS = 945;; let _X86_INS_VFNMSUB213SD = 946;; let _X86_INS_VFNMSUB213SS = 947;; let _X86_INS_VFNMSUB231PD = 948;; let _X86_INS_VFNMSUB231PS = 949;; let _X86_INS_VFNMSUB231SD = 950;; let _X86_INS_VFNMSUB231SS = 951;; let _X86_INS_VFNMSUBPD = 952;; let _X86_INS_VFNMSUBPS = 953;; let _X86_INS_VFNMSUBSD = 954;; let _X86_INS_VFNMSUBSS = 955;; let _X86_INS_VFPCLASSPD = 956;; let _X86_INS_VFPCLASSPS = 957;; let _X86_INS_VFPCLASSSD = 958;; let _X86_INS_VFPCLASSSS = 959;; let _X86_INS_VFRCZPD = 960;; let _X86_INS_VFRCZPS = 961;; let _X86_INS_VFRCZSD = 962;; let _X86_INS_VFRCZSS = 963;; let _X86_INS_VGATHERDPD = 964;; let _X86_INS_VGATHERDPS = 965;; let _X86_INS_VGATHERPF0DPD = 966;; let _X86_INS_VGATHERPF0DPS = 967;; let _X86_INS_VGATHERPF0QPD = 968;; let _X86_INS_VGATHERPF0QPS = 969;; let _X86_INS_VGATHERPF1DPD = 970;; let _X86_INS_VGATHERPF1DPS = 971;; let _X86_INS_VGATHERPF1QPD = 972;; let _X86_INS_VGATHERPF1QPS = 973;; let _X86_INS_VGATHERQPD = 974;; let _X86_INS_VGATHERQPS = 975;; let _X86_INS_VGETEXPPD = 976;; let _X86_INS_VGETEXPPS = 977;; let _X86_INS_VGETEXPSD = 978;; let _X86_INS_VGETEXPSS = 979;; let _X86_INS_VGETMANTPD = 980;; let _X86_INS_VGETMANTPS = 981;; let _X86_INS_VGETMANTSD = 982;; let _X86_INS_VGETMANTSS = 983;; let _X86_INS_VGF2P8AFFINEINVQB = 984;; let _X86_INS_VGF2P8AFFINEQB = 985;; let _X86_INS_VGF2P8MULB = 986;; let _X86_INS_VHADDPD = 987;; let _X86_INS_VHADDPS = 988;; let _X86_INS_VHSUBPD = 989;; let _X86_INS_VHSUBPS = 990;; let _X86_INS_VINSERTF128 = 991;; let _X86_INS_VINSERTF32X4 = 992;; let _X86_INS_VINSERTF32X8 = 993;; let _X86_INS_VINSERTF64X2 = 994;; let _X86_INS_VINSERTF64X4 = 995;; let _X86_INS_VINSERTI128 = 996;; let _X86_INS_VINSERTI32X4 = 997;; let _X86_INS_VINSERTI32X8 = 998;; let _X86_INS_VINSERTI64X2 = 999;; let _X86_INS_VINSERTI64X4 = 1000;; let _X86_INS_VINSERTPS = 1001;; let _X86_INS_VLDDQU = 1002;; let _X86_INS_VLDMXCSR = 1003;; let _X86_INS_VMASKMOVDQU = 1004;; let _X86_INS_VMASKMOVPD = 1005;; let _X86_INS_VMASKMOVPS = 1006;; let _X86_INS_VMAXPD = 1007;; let _X86_INS_VMAXPS = 1008;; let _X86_INS_VMAXSD = 1009;; let _X86_INS_VMAXSS = 1010;; let _X86_INS_VMCALL = 1011;; let _X86_INS_VMCLEAR = 1012;; let _X86_INS_VMFUNC = 1013;; let _X86_INS_VMINPD = 1014;; let _X86_INS_VMINPS = 1015;; let _X86_INS_VMINSD = 1016;; let _X86_INS_VMINSS = 1017;; let _X86_INS_VMLAUNCH = 1018;; let _X86_INS_VMLOAD = 1019;; let _X86_INS_VMMCALL = 1020;; let _X86_INS_VMOVQ = 1021;; let _X86_INS_VMOVAPD = 1022;; let _X86_INS_VMOVAPS = 1023;; let _X86_INS_VMOVDDUP = 1024;; let _X86_INS_VMOVD = 1025;; let _X86_INS_VMOVDQA32 = 1026;; let _X86_INS_VMOVDQA64 = 1027;; let _X86_INS_VMOVDQA = 1028;; let _X86_INS_VMOVDQU16 = 1029;; let _X86_INS_VMOVDQU32 = 1030;; let _X86_INS_VMOVDQU64 = 1031;; let _X86_INS_VMOVDQU8 = 1032;; let _X86_INS_VMOVDQU = 1033;; let _X86_INS_VMOVHLPS = 1034;; let _X86_INS_VMOVHPD = 1035;; let _X86_INS_VMOVHPS = 1036;; let _X86_INS_VMOVLHPS = 1037;; let _X86_INS_VMOVLPD = 1038;; let _X86_INS_VMOVLPS = 1039;; let _X86_INS_VMOVMSKPD = 1040;; let _X86_INS_VMOVMSKPS = 1041;; let _X86_INS_VMOVNTDQA = 1042;; let _X86_INS_VMOVNTDQ = 1043;; let _X86_INS_VMOVNTPD = 1044;; let _X86_INS_VMOVNTPS = 1045;; let _X86_INS_VMOVSD = 1046;; let _X86_INS_VMOVSHDUP = 1047;; let _X86_INS_VMOVSLDUP = 1048;; let _X86_INS_VMOVSS = 1049;; let _X86_INS_VMOVUPD = 1050;; let _X86_INS_VMOVUPS = 1051;; let _X86_INS_VMPSADBW = 1052;; let _X86_INS_VMPTRLD = 1053;; let _X86_INS_VMPTRST = 1054;; let _X86_INS_VMREAD = 1055;; let _X86_INS_VMRESUME = 1056;; let _X86_INS_VMRUN = 1057;; let _X86_INS_VMSAVE = 1058;; let _X86_INS_VMULPD = 1059;; let _X86_INS_VMULPS = 1060;; let _X86_INS_VMULSD = 1061;; let _X86_INS_VMULSS = 1062;; let _X86_INS_VMWRITE = 1063;; let _X86_INS_VMXOFF = 1064;; let _X86_INS_VMXON = 1065;; let _X86_INS_VORPD = 1066;; let _X86_INS_VORPS = 1067;; let _X86_INS_VP4DPWSSDS = 1068;; let _X86_INS_VP4DPWSSD = 1069;; let _X86_INS_VPABSB = 1070;; let _X86_INS_VPABSD = 1071;; let _X86_INS_VPABSQ = 1072;; let _X86_INS_VPABSW = 1073;; let _X86_INS_VPACKSSDW = 1074;; let _X86_INS_VPACKSSWB = 1075;; let _X86_INS_VPACKUSDW = 1076;; let _X86_INS_VPACKUSWB = 1077;; let _X86_INS_VPADDB = 1078;; let _X86_INS_VPADDD = 1079;; let _X86_INS_VPADDQ = 1080;; let _X86_INS_VPADDSB = 1081;; let _X86_INS_VPADDSW = 1082;; let _X86_INS_VPADDUSB = 1083;; let _X86_INS_VPADDUSW = 1084;; let _X86_INS_VPADDW = 1085;; let _X86_INS_VPALIGNR = 1086;; let _X86_INS_VPANDD = 1087;; let _X86_INS_VPANDND = 1088;; let _X86_INS_VPANDNQ = 1089;; let _X86_INS_VPANDN = 1090;; let _X86_INS_VPANDQ = 1091;; let _X86_INS_VPAND = 1092;; let _X86_INS_VPAVGB = 1093;; let _X86_INS_VPAVGW = 1094;; let _X86_INS_VPBLENDD = 1095;; let _X86_INS_VPBLENDMB = 1096;; let _X86_INS_VPBLENDMD = 1097;; let _X86_INS_VPBLENDMQ = 1098;; let _X86_INS_VPBLENDMW = 1099;; let _X86_INS_VPBLENDVB = 1100;; let _X86_INS_VPBLENDW = 1101;; let _X86_INS_VPBROADCASTB = 1102;; let _X86_INS_VPBROADCASTD = 1103;; let _X86_INS_VPBROADCASTMB2Q = 1104;; let _X86_INS_VPBROADCASTMW2D = 1105;; let _X86_INS_VPBROADCASTQ = 1106;; let _X86_INS_VPBROADCASTW = 1107;; let _X86_INS_VPCLMULQDQ = 1108;; let _X86_INS_VPCMOV = 1109;; let _X86_INS_VPCMP = 1110;; let _X86_INS_VPCMPB = 1111;; let _X86_INS_VPCMPD = 1112;; let _X86_INS_VPCMPEQB = 1113;; let _X86_INS_VPCMPEQD = 1114;; let _X86_INS_VPCMPEQQ = 1115;; let _X86_INS_VPCMPEQW = 1116;; let _X86_INS_VPCMPESTRI = 1117;; let _X86_INS_VPCMPESTRM = 1118;; let _X86_INS_VPCMPGTB = 1119;; let _X86_INS_VPCMPGTD = 1120;; let _X86_INS_VPCMPGTQ = 1121;; let _X86_INS_VPCMPGTW = 1122;; let _X86_INS_VPCMPISTRI = 1123;; let _X86_INS_VPCMPISTRM = 1124;; let _X86_INS_VPCMPQ = 1125;; let _X86_INS_VPCMPUB = 1126;; let _X86_INS_VPCMPUD = 1127;; let _X86_INS_VPCMPUQ = 1128;; let _X86_INS_VPCMPUW = 1129;; let _X86_INS_VPCMPW = 1130;; let _X86_INS_VPCOM = 1131;; let _X86_INS_VPCOMB = 1132;; let _X86_INS_VPCOMD = 1133;; let _X86_INS_VPCOMPRESSB = 1134;; let _X86_INS_VPCOMPRESSD = 1135;; let _X86_INS_VPCOMPRESSQ = 1136;; let _X86_INS_VPCOMPRESSW = 1137;; let _X86_INS_VPCOMQ = 1138;; let _X86_INS_VPCOMUB = 1139;; let _X86_INS_VPCOMUD = 1140;; let _X86_INS_VPCOMUQ = 1141;; let _X86_INS_VPCOMUW = 1142;; let _X86_INS_VPCOMW = 1143;; let _X86_INS_VPCONFLICTD = 1144;; let _X86_INS_VPCONFLICTQ = 1145;; let _X86_INS_VPDPBUSDS = 1146;; let _X86_INS_VPDPBUSD = 1147;; let _X86_INS_VPDPWSSDS = 1148;; let _X86_INS_VPDPWSSD = 1149;; let _X86_INS_VPERM2F128 = 1150;; let _X86_INS_VPERM2I128 = 1151;; let _X86_INS_VPERMB = 1152;; let _X86_INS_VPERMD = 1153;; let _X86_INS_VPERMI2B = 1154;; let _X86_INS_VPERMI2D = 1155;; let _X86_INS_VPERMI2PD = 1156;; let _X86_INS_VPERMI2PS = 1157;; let _X86_INS_VPERMI2Q = 1158;; let _X86_INS_VPERMI2W = 1159;; let _X86_INS_VPERMIL2PD = 1160;; let _X86_INS_VPERMILPD = 1161;; let _X86_INS_VPERMIL2PS = 1162;; let _X86_INS_VPERMILPS = 1163;; let _X86_INS_VPERMPD = 1164;; let _X86_INS_VPERMPS = 1165;; let _X86_INS_VPERMQ = 1166;; let _X86_INS_VPERMT2B = 1167;; let _X86_INS_VPERMT2D = 1168;; let _X86_INS_VPERMT2PD = 1169;; let _X86_INS_VPERMT2PS = 1170;; let _X86_INS_VPERMT2Q = 1171;; let _X86_INS_VPERMT2W = 1172;; let _X86_INS_VPERMW = 1173;; let _X86_INS_VPEXPANDB = 1174;; let _X86_INS_VPEXPANDD = 1175;; let _X86_INS_VPEXPANDQ = 1176;; let _X86_INS_VPEXPANDW = 1177;; let _X86_INS_VPEXTRB = 1178;; let _X86_INS_VPEXTRD = 1179;; let _X86_INS_VPEXTRQ = 1180;; let _X86_INS_VPEXTRW = 1181;; let _X86_INS_VPGATHERDD = 1182;; let _X86_INS_VPGATHERDQ = 1183;; let _X86_INS_VPGATHERQD = 1184;; let _X86_INS_VPGATHERQQ = 1185;; let _X86_INS_VPHADDBD = 1186;; let _X86_INS_VPHADDBQ = 1187;; let _X86_INS_VPHADDBW = 1188;; let _X86_INS_VPHADDDQ = 1189;; let _X86_INS_VPHADDD = 1190;; let _X86_INS_VPHADDSW = 1191;; let _X86_INS_VPHADDUBD = 1192;; let _X86_INS_VPHADDUBQ = 1193;; let _X86_INS_VPHADDUBW = 1194;; let _X86_INS_VPHADDUDQ = 1195;; let _X86_INS_VPHADDUWD = 1196;; let _X86_INS_VPHADDUWQ = 1197;; let _X86_INS_VPHADDWD = 1198;; let _X86_INS_VPHADDWQ = 1199;; let _X86_INS_VPHADDW = 1200;; let _X86_INS_VPHMINPOSUW = 1201;; let _X86_INS_VPHSUBBW = 1202;; let _X86_INS_VPHSUBDQ = 1203;; let _X86_INS_VPHSUBD = 1204;; let _X86_INS_VPHSUBSW = 1205;; let _X86_INS_VPHSUBWD = 1206;; let _X86_INS_VPHSUBW = 1207;; let _X86_INS_VPINSRB = 1208;; let _X86_INS_VPINSRD = 1209;; let _X86_INS_VPINSRQ = 1210;; let _X86_INS_VPINSRW = 1211;; let _X86_INS_VPLZCNTD = 1212;; let _X86_INS_VPLZCNTQ = 1213;; let _X86_INS_VPMACSDD = 1214;; let _X86_INS_VPMACSDQH = 1215;; let _X86_INS_VPMACSDQL = 1216;; let _X86_INS_VPMACSSDD = 1217;; let _X86_INS_VPMACSSDQH = 1218;; let _X86_INS_VPMACSSDQL = 1219;; let _X86_INS_VPMACSSWD = 1220;; let _X86_INS_VPMACSSWW = 1221;; let _X86_INS_VPMACSWD = 1222;; let _X86_INS_VPMACSWW = 1223;; let _X86_INS_VPMADCSSWD = 1224;; let _X86_INS_VPMADCSWD = 1225;; let _X86_INS_VPMADD52HUQ = 1226;; let _X86_INS_VPMADD52LUQ = 1227;; let _X86_INS_VPMADDUBSW = 1228;; let _X86_INS_VPMADDWD = 1229;; let _X86_INS_VPMASKMOVD = 1230;; let _X86_INS_VPMASKMOVQ = 1231;; let _X86_INS_VPMAXSB = 1232;; let _X86_INS_VPMAXSD = 1233;; let _X86_INS_VPMAXSQ = 1234;; let _X86_INS_VPMAXSW = 1235;; let _X86_INS_VPMAXUB = 1236;; let _X86_INS_VPMAXUD = 1237;; let _X86_INS_VPMAXUQ = 1238;; let _X86_INS_VPMAXUW = 1239;; let _X86_INS_VPMINSB = 1240;; let _X86_INS_VPMINSD = 1241;; let _X86_INS_VPMINSQ = 1242;; let _X86_INS_VPMINSW = 1243;; let _X86_INS_VPMINUB = 1244;; let _X86_INS_VPMINUD = 1245;; let _X86_INS_VPMINUQ = 1246;; let _X86_INS_VPMINUW = 1247;; let _X86_INS_VPMOVB2M = 1248;; let _X86_INS_VPMOVD2M = 1249;; let _X86_INS_VPMOVDB = 1250;; let _X86_INS_VPMOVDW = 1251;; let _X86_INS_VPMOVM2B = 1252;; let _X86_INS_VPMOVM2D = 1253;; let _X86_INS_VPMOVM2Q = 1254;; let _X86_INS_VPMOVM2W = 1255;; let _X86_INS_VPMOVMSKB = 1256;; let _X86_INS_VPMOVQ2M = 1257;; let _X86_INS_VPMOVQB = 1258;; let _X86_INS_VPMOVQD = 1259;; let _X86_INS_VPMOVQW = 1260;; let _X86_INS_VPMOVSDB = 1261;; let _X86_INS_VPMOVSDW = 1262;; let _X86_INS_VPMOVSQB = 1263;; let _X86_INS_VPMOVSQD = 1264;; let _X86_INS_VPMOVSQW = 1265;; let _X86_INS_VPMOVSWB = 1266;; let _X86_INS_VPMOVSXBD = 1267;; let _X86_INS_VPMOVSXBQ = 1268;; let _X86_INS_VPMOVSXBW = 1269;; let _X86_INS_VPMOVSXDQ = 1270;; let _X86_INS_VPMOVSXWD = 1271;; let _X86_INS_VPMOVSXWQ = 1272;; let _X86_INS_VPMOVUSDB = 1273;; let _X86_INS_VPMOVUSDW = 1274;; let _X86_INS_VPMOVUSQB = 1275;; let _X86_INS_VPMOVUSQD = 1276;; let _X86_INS_VPMOVUSQW = 1277;; let _X86_INS_VPMOVUSWB = 1278;; let _X86_INS_VPMOVW2M = 1279;; let _X86_INS_VPMOVWB = 1280;; let _X86_INS_VPMOVZXBD = 1281;; let _X86_INS_VPMOVZXBQ = 1282;; let _X86_INS_VPMOVZXBW = 1283;; let _X86_INS_VPMOVZXDQ = 1284;; let _X86_INS_VPMOVZXWD = 1285;; let _X86_INS_VPMOVZXWQ = 1286;; let _X86_INS_VPMULDQ = 1287;; let _X86_INS_VPMULHRSW = 1288;; let _X86_INS_VPMULHUW = 1289;; let _X86_INS_VPMULHW = 1290;; let _X86_INS_VPMULLD = 1291;; let _X86_INS_VPMULLQ = 1292;; let _X86_INS_VPMULLW = 1293;; let _X86_INS_VPMULTISHIFTQB = 1294;; let _X86_INS_VPMULUDQ = 1295;; let _X86_INS_VPOPCNTB = 1296;; let _X86_INS_VPOPCNTD = 1297;; let _X86_INS_VPOPCNTQ = 1298;; let _X86_INS_VPOPCNTW = 1299;; let _X86_INS_VPORD = 1300;; let _X86_INS_VPORQ = 1301;; let _X86_INS_VPOR = 1302;; let _X86_INS_VPPERM = 1303;; let _X86_INS_VPROLD = 1304;; let _X86_INS_VPROLQ = 1305;; let _X86_INS_VPROLVD = 1306;; let _X86_INS_VPROLVQ = 1307;; let _X86_INS_VPRORD = 1308;; let _X86_INS_VPRORQ = 1309;; let _X86_INS_VPRORVD = 1310;; let _X86_INS_VPRORVQ = 1311;; let _X86_INS_VPROTB = 1312;; let _X86_INS_VPROTD = 1313;; let _X86_INS_VPROTQ = 1314;; let _X86_INS_VPROTW = 1315;; let _X86_INS_VPSADBW = 1316;; let _X86_INS_VPSCATTERDD = 1317;; let _X86_INS_VPSCATTERDQ = 1318;; let _X86_INS_VPSCATTERQD = 1319;; let _X86_INS_VPSCATTERQQ = 1320;; let _X86_INS_VPSHAB = 1321;; let _X86_INS_VPSHAD = 1322;; let _X86_INS_VPSHAQ = 1323;; let _X86_INS_VPSHAW = 1324;; let _X86_INS_VPSHLB = 1325;; let _X86_INS_VPSHLDD = 1326;; let _X86_INS_VPSHLDQ = 1327;; let _X86_INS_VPSHLDVD = 1328;; let _X86_INS_VPSHLDVQ = 1329;; let _X86_INS_VPSHLDVW = 1330;; let _X86_INS_VPSHLDW = 1331;; let _X86_INS_VPSHLD = 1332;; let _X86_INS_VPSHLQ = 1333;; let _X86_INS_VPSHLW = 1334;; let _X86_INS_VPSHRDD = 1335;; let _X86_INS_VPSHRDQ = 1336;; let _X86_INS_VPSHRDVD = 1337;; let _X86_INS_VPSHRDVQ = 1338;; let _X86_INS_VPSHRDVW = 1339;; let _X86_INS_VPSHRDW = 1340;; let _X86_INS_VPSHUFBITQMB = 1341;; let _X86_INS_VPSHUFB = 1342;; let _X86_INS_VPSHUFD = 1343;; let _X86_INS_VPSHUFHW = 1344;; let _X86_INS_VPSHUFLW = 1345;; let _X86_INS_VPSIGNB = 1346;; let _X86_INS_VPSIGND = 1347;; let _X86_INS_VPSIGNW = 1348;; let _X86_INS_VPSLLDQ = 1349;; let _X86_INS_VPSLLD = 1350;; let _X86_INS_VPSLLQ = 1351;; let _X86_INS_VPSLLVD = 1352;; let _X86_INS_VPSLLVQ = 1353;; let _X86_INS_VPSLLVW = 1354;; let _X86_INS_VPSLLW = 1355;; let _X86_INS_VPSRAD = 1356;; let _X86_INS_VPSRAQ = 1357;; let _X86_INS_VPSRAVD = 1358;; let _X86_INS_VPSRAVQ = 1359;; let _X86_INS_VPSRAVW = 1360;; let _X86_INS_VPSRAW = 1361;; let _X86_INS_VPSRLDQ = 1362;; let _X86_INS_VPSRLD = 1363;; let _X86_INS_VPSRLQ = 1364;; let _X86_INS_VPSRLVD = 1365;; let _X86_INS_VPSRLVQ = 1366;; let _X86_INS_VPSRLVW = 1367;; let _X86_INS_VPSRLW = 1368;; let _X86_INS_VPSUBB = 1369;; let _X86_INS_VPSUBD = 1370;; let _X86_INS_VPSUBQ = 1371;; let _X86_INS_VPSUBSB = 1372;; let _X86_INS_VPSUBSW = 1373;; let _X86_INS_VPSUBUSB = 1374;; let _X86_INS_VPSUBUSW = 1375;; let _X86_INS_VPSUBW = 1376;; let _X86_INS_VPTERNLOGD = 1377;; let _X86_INS_VPTERNLOGQ = 1378;; let _X86_INS_VPTESTMB = 1379;; let _X86_INS_VPTESTMD = 1380;; let _X86_INS_VPTESTMQ = 1381;; let _X86_INS_VPTESTMW = 1382;; let _X86_INS_VPTESTNMB = 1383;; let _X86_INS_VPTESTNMD = 1384;; let _X86_INS_VPTESTNMQ = 1385;; let _X86_INS_VPTESTNMW = 1386;; let _X86_INS_VPTEST = 1387;; let _X86_INS_VPUNPCKHBW = 1388;; let _X86_INS_VPUNPCKHDQ = 1389;; let _X86_INS_VPUNPCKHQDQ = 1390;; let _X86_INS_VPUNPCKHWD = 1391;; let _X86_INS_VPUNPCKLBW = 1392;; let _X86_INS_VPUNPCKLDQ = 1393;; let _X86_INS_VPUNPCKLQDQ = 1394;; let _X86_INS_VPUNPCKLWD = 1395;; let _X86_INS_VPXORD = 1396;; let _X86_INS_VPXORQ = 1397;; let _X86_INS_VPXOR = 1398;; let _X86_INS_VRANGEPD = 1399;; let _X86_INS_VRANGEPS = 1400;; let _X86_INS_VRANGESD = 1401;; let _X86_INS_VRANGESS = 1402;; let _X86_INS_VRCP14PD = 1403;; let _X86_INS_VRCP14PS = 1404;; let _X86_INS_VRCP14SD = 1405;; let _X86_INS_VRCP14SS = 1406;; let _X86_INS_VRCP28PD = 1407;; let _X86_INS_VRCP28PS = 1408;; let _X86_INS_VRCP28SD = 1409;; let _X86_INS_VRCP28SS = 1410;; let _X86_INS_VRCPPS = 1411;; let _X86_INS_VRCPSS = 1412;; let _X86_INS_VREDUCEPD = 1413;; let _X86_INS_VREDUCEPS = 1414;; let _X86_INS_VREDUCESD = 1415;; let _X86_INS_VREDUCESS = 1416;; let _X86_INS_VRNDSCALEPD = 1417;; let _X86_INS_VRNDSCALEPS = 1418;; let _X86_INS_VRNDSCALESD = 1419;; let _X86_INS_VRNDSCALESS = 1420;; let _X86_INS_VROUNDPD = 1421;; let _X86_INS_VROUNDPS = 1422;; let _X86_INS_VROUNDSD = 1423;; let _X86_INS_VROUNDSS = 1424;; let _X86_INS_VRSQRT14PD = 1425;; let _X86_INS_VRSQRT14PS = 1426;; let _X86_INS_VRSQRT14SD = 1427;; let _X86_INS_VRSQRT14SS = 1428;; let _X86_INS_VRSQRT28PD = 1429;; let _X86_INS_VRSQRT28PS = 1430;; let _X86_INS_VRSQRT28SD = 1431;; let _X86_INS_VRSQRT28SS = 1432;; let _X86_INS_VRSQRTPS = 1433;; let _X86_INS_VRSQRTSS = 1434;; let _X86_INS_VSCALEFPD = 1435;; let _X86_INS_VSCALEFPS = 1436;; let _X86_INS_VSCALEFSD = 1437;; let _X86_INS_VSCALEFSS = 1438;; let _X86_INS_VSCATTERDPD = 1439;; let _X86_INS_VSCATTERDPS = 1440;; let _X86_INS_VSCATTERPF0DPD = 1441;; let _X86_INS_VSCATTERPF0DPS = 1442;; let _X86_INS_VSCATTERPF0QPD = 1443;; let _X86_INS_VSCATTERPF0QPS = 1444;; let _X86_INS_VSCATTERPF1DPD = 1445;; let _X86_INS_VSCATTERPF1DPS = 1446;; let _X86_INS_VSCATTERPF1QPD = 1447;; let _X86_INS_VSCATTERPF1QPS = 1448;; let _X86_INS_VSCATTERQPD = 1449;; let _X86_INS_VSCATTERQPS = 1450;; let _X86_INS_VSHUFF32X4 = 1451;; let _X86_INS_VSHUFF64X2 = 1452;; let _X86_INS_VSHUFI32X4 = 1453;; let _X86_INS_VSHUFI64X2 = 1454;; let _X86_INS_VSHUFPD = 1455;; let _X86_INS_VSHUFPS = 1456;; let _X86_INS_VSQRTPD = 1457;; let _X86_INS_VSQRTPS = 1458;; let _X86_INS_VSQRTSD = 1459;; let _X86_INS_VSQRTSS = 1460;; let _X86_INS_VSTMXCSR = 1461;; let _X86_INS_VSUBPD = 1462;; let _X86_INS_VSUBPS = 1463;; let _X86_INS_VSUBSD = 1464;; let _X86_INS_VSUBSS = 1465;; let _X86_INS_VTESTPD = 1466;; let _X86_INS_VTESTPS = 1467;; let _X86_INS_VUCOMISD = 1468;; let _X86_INS_VUCOMISS = 1469;; let _X86_INS_VUNPCKHPD = 1470;; let _X86_INS_VUNPCKHPS = 1471;; let _X86_INS_VUNPCKLPD = 1472;; let _X86_INS_VUNPCKLPS = 1473;; let _X86_INS_VXORPD = 1474;; let _X86_INS_VXORPS = 1475;; let _X86_INS_VZEROALL = 1476;; let _X86_INS_VZEROUPPER = 1477;; let _X86_INS_WAIT = 1478;; let _X86_INS_WBINVD = 1479;; let _X86_INS_WBNOINVD = 1480;; let _X86_INS_WRFSBASE = 1481;; let _X86_INS_WRGSBASE = 1482;; let _X86_INS_WRMSR = 1483;; let _X86_INS_WRPKRU = 1484;; let _X86_INS_WRSSD = 1485;; let _X86_INS_WRSSQ = 1486;; let _X86_INS_WRUSSD = 1487;; let _X86_INS_WRUSSQ = 1488;; let _X86_INS_XABORT = 1489;; let _X86_INS_XACQUIRE = 1490;; let _X86_INS_XADD = 1491;; let _X86_INS_XBEGIN = 1492;; let _X86_INS_XCHG = 1493;; let _X86_INS_FXCH = 1494;; let _X86_INS_XCRYPTCBC = 1495;; let _X86_INS_XCRYPTCFB = 1496;; let _X86_INS_XCRYPTCTR = 1497;; let _X86_INS_XCRYPTECB = 1498;; let _X86_INS_XCRYPTOFB = 1499;; let _X86_INS_XEND = 1500;; let _X86_INS_XGETBV = 1501;; let _X86_INS_XLATB = 1502;; let _X86_INS_XOR = 1503;; let _X86_INS_XORPD = 1504;; let _X86_INS_XORPS = 1505;; let _X86_INS_XRELEASE = 1506;; let _X86_INS_XRSTOR = 1507;; let _X86_INS_XRSTOR64 = 1508;; let _X86_INS_XRSTORS = 1509;; let _X86_INS_XRSTORS64 = 1510;; let _X86_INS_XSAVE = 1511;; let _X86_INS_XSAVE64 = 1512;; let _X86_INS_XSAVEC = 1513;; let _X86_INS_XSAVEC64 = 1514;; let _X86_INS_XSAVEOPT = 1515;; let _X86_INS_XSAVEOPT64 = 1516;; let _X86_INS_XSAVES = 1517;; let _X86_INS_XSAVES64 = 1518;; let _X86_INS_XSETBV = 1519;; let _X86_INS_XSHA1 = 1520;; let _X86_INS_XSHA256 = 1521;; let _X86_INS_XSTORE = 1522;; let _X86_INS_XTEST = 1523;; let _X86_INS_ENDING = 1524;; let _X86_GRP_INVALID = 0;; let _X86_GRP_JUMP = 1;; let _X86_GRP_CALL = 2;; let _X86_GRP_RET = 3;; let _X86_GRP_INT = 4;; let _X86_GRP_IRET = 5;; let _X86_GRP_PRIVILEGE = 6;; let _X86_GRP_BRANCH_RELATIVE = 7;; let _X86_GRP_VM = 128;; let _X86_GRP_3DNOW = 129;; let _X86_GRP_AES = 130;; let _X86_GRP_ADX = 131;; let _X86_GRP_AVX = 132;; let _X86_GRP_AVX2 = 133;; let _X86_GRP_AVX512 = 134;; let _X86_GRP_BMI = 135;; let _X86_GRP_BMI2 = 136;; let _X86_GRP_CMOV = 137;; let _X86_GRP_F16C = 138;; let _X86_GRP_FMA = 139;; let _X86_GRP_FMA4 = 140;; let _X86_GRP_FSGSBASE = 141;; let _X86_GRP_HLE = 142;; let _X86_GRP_MMX = 143;; let _X86_GRP_MODE32 = 144;; let _X86_GRP_MODE64 = 145;; let _X86_GRP_RTM = 146;; let _X86_GRP_SHA = 147;; let _X86_GRP_SSE1 = 148;; let _X86_GRP_SSE2 = 149;; let _X86_GRP_SSE3 = 150;; let _X86_GRP_SSE41 = 151;; let _X86_GRP_SSE42 = 152;; let _X86_GRP_SSE4A = 153;; let _X86_GRP_SSSE3 = 154;; let _X86_GRP_PCLMUL = 155;; let _X86_GRP_XOP = 156;; let _X86_GRP_CDI = 157;; let _X86_GRP_ERI = 158;; let _X86_GRP_TBM = 159;; let _X86_GRP_16BITMODE = 160;; let _X86_GRP_NOT64BITMODE = 161;; let _X86_GRP_SGX = 162;; let _X86_GRP_DQI = 163;; let _X86_GRP_BWI = 164;; let _X86_GRP_PFI = 165;; let _X86_GRP_VLX = 166;; let _X86_GRP_SMAP = 167;; let _X86_GRP_NOVLX = 168;; let _X86_GRP_FPU = 169;; let _X86_GRP_ENDING = 170;; capstone-sys-0.15.0/capstone/bindings/ocaml/xcore.ml000064400000000000000000000006330072674642500205470ustar 00000000000000(* Capstone Disassembly Engine * By Guillaume Jeanne , 2014> *) open Xcore_const type xcore_op_mem = { base: int; index: int; disp: int; direct: int; } type xcore_op_value = | XCORE_OP_INVALID of int | XCORE_OP_REG of int | XCORE_OP_IMM of int | XCORE_OP_MEM of xcore_op_mem type xcore_op = { value: xcore_op_value; } type cs_xcore = { operands: xcore_op array; } capstone-sys-0.15.0/capstone/bindings/ocaml/xcore_const.ml000064400000000000000000000103110072674642500217470ustar 00000000000000(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.ml] *) let _XCORE_OP_INVALID = 0;; let _XCORE_OP_REG = 1;; let _XCORE_OP_IMM = 2;; let _XCORE_OP_MEM = 3;; let _XCORE_REG_INVALID = 0;; let _XCORE_REG_CP = 1;; let _XCORE_REG_DP = 2;; let _XCORE_REG_LR = 3;; let _XCORE_REG_SP = 4;; let _XCORE_REG_R0 = 5;; let _XCORE_REG_R1 = 6;; let _XCORE_REG_R2 = 7;; let _XCORE_REG_R3 = 8;; let _XCORE_REG_R4 = 9;; let _XCORE_REG_R5 = 10;; let _XCORE_REG_R6 = 11;; let _XCORE_REG_R7 = 12;; let _XCORE_REG_R8 = 13;; let _XCORE_REG_R9 = 14;; let _XCORE_REG_R10 = 15;; let _XCORE_REG_R11 = 16;; let _XCORE_REG_PC = 17;; let _XCORE_REG_SCP = 18;; let _XCORE_REG_SSR = 19;; let _XCORE_REG_ET = 20;; let _XCORE_REG_ED = 21;; let _XCORE_REG_SED = 22;; let _XCORE_REG_KEP = 23;; let _XCORE_REG_KSP = 24;; let _XCORE_REG_ID = 25;; let _XCORE_REG_ENDING = 26;; let _XCORE_INS_INVALID = 0;; let _XCORE_INS_ADD = 1;; let _XCORE_INS_ANDNOT = 2;; let _XCORE_INS_AND = 3;; let _XCORE_INS_ASHR = 4;; let _XCORE_INS_BAU = 5;; let _XCORE_INS_BITREV = 6;; let _XCORE_INS_BLA = 7;; let _XCORE_INS_BLAT = 8;; let _XCORE_INS_BL = 9;; let _XCORE_INS_BF = 10;; let _XCORE_INS_BT = 11;; let _XCORE_INS_BU = 12;; let _XCORE_INS_BRU = 13;; let _XCORE_INS_BYTEREV = 14;; let _XCORE_INS_CHKCT = 15;; let _XCORE_INS_CLRE = 16;; let _XCORE_INS_CLRPT = 17;; let _XCORE_INS_CLRSR = 18;; let _XCORE_INS_CLZ = 19;; let _XCORE_INS_CRC8 = 20;; let _XCORE_INS_CRC32 = 21;; let _XCORE_INS_DCALL = 22;; let _XCORE_INS_DENTSP = 23;; let _XCORE_INS_DGETREG = 24;; let _XCORE_INS_DIVS = 25;; let _XCORE_INS_DIVU = 26;; let _XCORE_INS_DRESTSP = 27;; let _XCORE_INS_DRET = 28;; let _XCORE_INS_ECALLF = 29;; let _XCORE_INS_ECALLT = 30;; let _XCORE_INS_EDU = 31;; let _XCORE_INS_EEF = 32;; let _XCORE_INS_EET = 33;; let _XCORE_INS_EEU = 34;; let _XCORE_INS_ENDIN = 35;; let _XCORE_INS_ENTSP = 36;; let _XCORE_INS_EQ = 37;; let _XCORE_INS_EXTDP = 38;; let _XCORE_INS_EXTSP = 39;; let _XCORE_INS_FREER = 40;; let _XCORE_INS_FREET = 41;; let _XCORE_INS_GETD = 42;; let _XCORE_INS_GET = 43;; let _XCORE_INS_GETN = 44;; let _XCORE_INS_GETR = 45;; let _XCORE_INS_GETSR = 46;; let _XCORE_INS_GETST = 47;; let _XCORE_INS_GETTS = 48;; let _XCORE_INS_INCT = 49;; let _XCORE_INS_INIT = 50;; let _XCORE_INS_INPW = 51;; let _XCORE_INS_INSHR = 52;; let _XCORE_INS_INT = 53;; let _XCORE_INS_IN = 54;; let _XCORE_INS_KCALL = 55;; let _XCORE_INS_KENTSP = 56;; let _XCORE_INS_KRESTSP = 57;; let _XCORE_INS_KRET = 58;; let _XCORE_INS_LADD = 59;; let _XCORE_INS_LD16S = 60;; let _XCORE_INS_LD8U = 61;; let _XCORE_INS_LDA16 = 62;; let _XCORE_INS_LDAP = 63;; let _XCORE_INS_LDAW = 64;; let _XCORE_INS_LDC = 65;; let _XCORE_INS_LDW = 66;; let _XCORE_INS_LDIVU = 67;; let _XCORE_INS_LMUL = 68;; let _XCORE_INS_LSS = 69;; let _XCORE_INS_LSUB = 70;; let _XCORE_INS_LSU = 71;; let _XCORE_INS_MACCS = 72;; let _XCORE_INS_MACCU = 73;; let _XCORE_INS_MJOIN = 74;; let _XCORE_INS_MKMSK = 75;; let _XCORE_INS_MSYNC = 76;; let _XCORE_INS_MUL = 77;; let _XCORE_INS_NEG = 78;; let _XCORE_INS_NOT = 79;; let _XCORE_INS_OR = 80;; let _XCORE_INS_OUTCT = 81;; let _XCORE_INS_OUTPW = 82;; let _XCORE_INS_OUTSHR = 83;; let _XCORE_INS_OUTT = 84;; let _XCORE_INS_OUT = 85;; let _XCORE_INS_PEEK = 86;; let _XCORE_INS_REMS = 87;; let _XCORE_INS_REMU = 88;; let _XCORE_INS_RETSP = 89;; let _XCORE_INS_SETCLK = 90;; let _XCORE_INS_SET = 91;; let _XCORE_INS_SETC = 92;; let _XCORE_INS_SETD = 93;; let _XCORE_INS_SETEV = 94;; let _XCORE_INS_SETN = 95;; let _XCORE_INS_SETPSC = 96;; let _XCORE_INS_SETPT = 97;; let _XCORE_INS_SETRDY = 98;; let _XCORE_INS_SETSR = 99;; let _XCORE_INS_SETTW = 100;; let _XCORE_INS_SETV = 101;; let _XCORE_INS_SEXT = 102;; let _XCORE_INS_SHL = 103;; let _XCORE_INS_SHR = 104;; let _XCORE_INS_SSYNC = 105;; let _XCORE_INS_ST16 = 106;; let _XCORE_INS_ST8 = 107;; let _XCORE_INS_STW = 108;; let _XCORE_INS_SUB = 109;; let _XCORE_INS_SYNCR = 110;; let _XCORE_INS_TESTCT = 111;; let _XCORE_INS_TESTLCL = 112;; let _XCORE_INS_TESTWCT = 113;; let _XCORE_INS_TSETMR = 114;; let _XCORE_INS_START = 115;; let _XCORE_INS_WAITEF = 116;; let _XCORE_INS_WAITET = 117;; let _XCORE_INS_WAITEU = 118;; let _XCORE_INS_XOR = 119;; let _XCORE_INS_ZEXT = 120;; let _XCORE_INS_ENDING = 121;; let _XCORE_GRP_INVALID = 0;; let _XCORE_GRP_JUMP = 1;; let _XCORE_GRP_ENDING = 2;; capstone-sys-0.15.0/capstone/capstone-config.cmake.in000064400000000000000000000003630072674642500206730ustar 00000000000000@PACKAGE_INIT@ set_and_check(capstone_INCLUDE_DIR "${PACKAGE_PREFIX_DIR}/@CMAKE_INSTALL_INCLUDEDIR@") set_and_check(capstone_LIB_DIR "${PACKAGE_PREFIX_DIR}/@CMAKE_INSTALL_LIBDIR@") include("${CMAKE_CURRENT_LIST_DIR}/capstone-targets.cmake") capstone-sys-0.15.0/capstone/capstone.pc.in000064400000000000000000000005550072674642500167550ustar 00000000000000prefix=@CMAKE_INSTALL_PREFIX@ exec_prefix=${prefix} libdir=${prefix}/@CMAKE_INSTALL_LIBDIR@ includedir=${prefix}/include/capstone Name: capstone Description: Capstone disassembly engine Version: @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@ URL: http://www.capstone-engine.org archive=${libdir}/libcapstone.a Libs: -L${libdir} -lcapstone Cflags: -I${includedir} capstone-sys-0.15.0/capstone/cmake.sh000075500000000000000000000020630072674642500156230ustar 00000000000000#!/bin/sh # Capstone disassembler engine (www.capstone-engine.org) # Build Capstone libs for specified architecture, or all if none is specified (libcapstone.so & libcapstone.a) on *nix with CMake & make # By Nguyen Anh Quynh, Jorn Vernee, 2019 FLAGS="-DCMAKE_BUILD_TYPE=Release" # Uncomment below line to compile in Diet mode # FLAGS+=" -DCAPSTONE_BUILD_DIET=ON" case $1 in ARM) ARCH=ARM ;; ARM64) ARCH=ARM64 ;; M68K) ARCH=M68K ;; MIPS) ARCH=MIPS ;; PowerPC) ARCH=PPC ;; Sparc) ARCH=SPARC ;; SystemZ) ARCH=SYSZ ;; XCore) ARCH=XCORE ;; x86) ARCH=X86 ;; TMS320C64x) ARCH=TMS320C64X ;; M680x) ARCH=M680X ;; EVM) ARCH=EVM ;; MOS65XX) ARCH=MOS65XX ;; WASM) ARCH=WASM ;; BPF) ARCH=BPF ;; RISCV) ARCH=RISCV ;; *) ;; esac if [ "x${ARCH}" = "x" ]; then FLAGS+=" -DCAPSTONE_ARCHITECTURE_DEFAULT=ON" else FLAGS+=" -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_${ARCH}_SUPPORT=ON" fi cmake $FLAGS .. make -j8 capstone-sys-0.15.0/capstone/config.mk000064400000000000000000000065150072674642500160100ustar 00000000000000# This file contains all customized compile options for Capstone. # Consult COMPILE.TXT & docs/README for details. ################################################################################ # Specify which archs you want to compile in. By default, we build all archs. CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf ################################################################################ # Comment out the line below ('CAPSTONE_USE_SYS_DYN_MEM = yes'), or change it to # 'CAPSTONE_USE_SYS_DYN_MEM = no' if do NOT use malloc/calloc/realloc/free/ # vsnprintf() provided by system for internal dynamic memory management. # # NOTE: in that case, specify your own malloc/calloc/realloc/free/vsnprintf() # functions in your program via API cs_option(), using CS_OPT_MEM option type. CAPSTONE_USE_SYS_DYN_MEM ?= yes ################################################################################ # Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library # more compact: use less memory & smaller in binary size. # This setup will remove the @mnemonic & @op_str data, plus semantic information # such as @regs_read/write & @group. The amount of binary size reduced is # up to 50% in some individual archs. # # NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read, # @regs_write, @groups, etc in fields in cs_insn structure regardless, but they # will not be updated (i.e empty), thus become irrelevant. CAPSTONE_DIET ?= no ################################################################################ # Change 'CAPSTONE_X86_REDUCE = no' to 'CAPSTONE_X86_REDUCE = yes' to remove # non-critical instruction sets of X86, making the binary size smaller by ~60%. # This is desired in special cases, such as OS kernel, where these kind of # instructions are not used. # # The list of instruction sets to be removed includes: # - Floating Point Unit (FPU) # - MultiMedia eXtension (MMX) # - Streaming SIMD Extensions (SSE) # - 3DNow # - Advanced Vector Extensions (AVX) # - Fused Multiply Add Operations (FMA) # - eXtended Operations (XOP) # - Transactional Synchronization Extensions (TSX) # # Due to this removal, the related instructions are nolonger supported. # # By default, Capstone is compiled with 'CAPSTONE_X86_REDUCE = no', # thus supports complete X86 instructions. CAPSTONE_X86_REDUCE ?= no ################################################################################ # Change 'CAPSTONE_X86_ATT_DISABLE = no' to 'CAPSTONE_X86_ATT_DISABLE = yes' to # disable AT&T syntax on x86 to reduce library size. CAPSTONE_X86_ATT_DISABLE ?= no ################################################################################ # Change 'CAPSTONE_STATIC = yes' to 'CAPSTONE_STATIC = no' to avoid building # a static library. CAPSTONE_STATIC ?= yes ################################################################################ # Change 'CAPSTONE_SHARED = yes' to 'CAPSTONE_SHARED = no' to avoid building # a shared library. CAPSTONE_SHARED ?= yes ################################################################################ # Change 'CAPSTONE_HAS_OSXKERNEL = no' to 'CAPSTONE_HAS_OSXKERNEL = yes' to # enable OS X kernel embedding support. If 'CAPSTONE_USE_SYS_DYN_MEM = yes', # then kern_os_* functions are used for memory management. CAPSTONE_HAS_OSXKERNEL ?= no capstone-sys-0.15.0/capstone/cs.c000064400000000000000000001152650072674642500147660ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) #pragma warning(disable:4996) // disable MSVC's warning on strcpy() #pragma warning(disable:28719) // disable MSVC's warning on strcpy() #endif #if defined(CAPSTONE_HAS_OSXKERNEL) #include #include #else #include #include #include #endif #include #include #include "utils.h" #include "MCRegisterInfo.h" #if defined(_KERNEL_MODE) #include "windows\winkernel_mm.h" #endif // Issue #681: Windows kernel does not support formatting float point #if defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET) #if defined(CAPSTONE_HAS_ARM) || defined(CAPSTONE_HAS_ARM64) || defined(CAPSTONE_HAS_M68K) #define CAPSTONE_STR_INTERNAL(x) #x #define CAPSTONE_STR(x) CAPSTONE_STR_INTERNAL(x) #define CAPSTONE_MSVC_WRANING_PREFIX __FILE__ "("CAPSTONE_STR(__LINE__)") : warning message : " #pragma message(CAPSTONE_MSVC_WRANING_PREFIX "Windows driver does not support full features for selected architecture(s). Define CAPSTONE_DIET to compile Capstone with only supported features. See issue #681 for details.") #undef CAPSTONE_MSVC_WRANING_PREFIX #undef CAPSTONE_STR #undef CAPSTONE_STR_INTERNAL #endif #endif // defined(_KERNEL_MODE) && !defined(CAPSTONE_DIET) #if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(CAPSTONE_DIET) && !defined(_KERNEL_MODE) #define INSN_CACHE_SIZE 32 #else // reduce stack variable size for kernel/firmware #define INSN_CACHE_SIZE 8 #endif // default SKIPDATA mnemonic #ifndef CAPSTONE_DIET #define SKIPDATA_MNEM ".byte" #else // No printing is available in diet mode #define SKIPDATA_MNEM NULL #endif #include "arch/AArch64/AArch64Module.h" #include "arch/ARM/ARMModule.h" #include "arch/EVM/EVMModule.h" #include "arch/WASM/WASMModule.h" #include "arch/M680X/M680XModule.h" #include "arch/M68K/M68KModule.h" #include "arch/Mips/MipsModule.h" #include "arch/PowerPC/PPCModule.h" #include "arch/Sparc/SparcModule.h" #include "arch/SystemZ/SystemZModule.h" #include "arch/TMS320C64x/TMS320C64xModule.h" #include "arch/X86/X86Module.h" #include "arch/XCore/XCoreModule.h" #include "arch/RISCV/RISCVModule.h" #include "arch/MOS65XX/MOS65XXModule.h" #include "arch/BPF/BPFModule.h" static const struct { // constructor initialization cs_err (*arch_init)(cs_struct *); // support cs_option() cs_err (*arch_option)(cs_struct *, cs_opt_type, size_t value); // bitmask for finding disallowed modes for an arch: // to be called in cs_open()/cs_option() cs_mode arch_disallowed_mode_mask; } arch_configs[MAX_ARCH] = { #ifdef CAPSTONE_HAS_ARM { ARM_global_init, ARM_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_V8 | CS_MODE_MCLASS | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN) }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_ARM64 { AArch64_global_init, AArch64_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_MIPS { Mips_global_init, Mips_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO | CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MIPS2 | CS_MODE_MIPS3), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_X86 { X86_global_init, X86_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_16), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_POWERPC { PPC_global_init, PPC_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_SPARC { Sparc_global_init, Sparc_option, ~(CS_MODE_BIG_ENDIAN | CS_MODE_V9), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_SYSZ { SystemZ_global_init, SystemZ_option, ~(CS_MODE_BIG_ENDIAN), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_XCORE { XCore_global_init, XCore_option, ~(CS_MODE_BIG_ENDIAN), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_M68K { M68K_global_init, M68K_option, ~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_000 | CS_MODE_M68K_010 | CS_MODE_M68K_020 | CS_MODE_M68K_030 | CS_MODE_M68K_040 | CS_MODE_M68K_060), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_TMS320C64X { TMS320C64x_global_init, TMS320C64x_option, ~(CS_MODE_BIG_ENDIAN), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_M680X { M680X_global_init, M680X_option, ~(CS_MODE_M680X_6301 | CS_MODE_M680X_6309 | CS_MODE_M680X_6800 | CS_MODE_M680X_6801 | CS_MODE_M680X_6805 | CS_MODE_M680X_6808 | CS_MODE_M680X_6809 | CS_MODE_M680X_6811 | CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_EVM { EVM_global_init, EVM_option, 0, }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_MOS65XX { MOS65XX_global_init, MOS65XX_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_MOS65XX_6502 | CS_MODE_MOS65XX_65C02 | CS_MODE_MOS65XX_W65C02 | CS_MODE_MOS65XX_65816_LONG_MX), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_WASM { WASM_global_init, WASM_option, 0, }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_BPF { BPF_global_init, BPF_option, ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC | CS_MODE_BPF_EXTENDED | CS_MODE_BIG_ENDIAN), }, #else { NULL, NULL, 0 }, #endif #ifdef CAPSTONE_HAS_RISCV { RISCV_global_init, RISCV_option, ~(CS_MODE_RISCV32 | CS_MODE_RISCV64 | CS_MODE_RISCVC), }, #else { NULL, NULL, 0 }, #endif }; // bitmask of enabled architectures static const uint32_t all_arch = 0 #ifdef CAPSTONE_HAS_ARM | (1 << CS_ARCH_ARM) #endif #ifdef CAPSTONE_HAS_ARM64 | (1 << CS_ARCH_ARM64) #endif #ifdef CAPSTONE_HAS_MIPS | (1 << CS_ARCH_MIPS) #endif #ifdef CAPSTONE_HAS_X86 | (1 << CS_ARCH_X86) #endif #ifdef CAPSTONE_HAS_POWERPC | (1 << CS_ARCH_PPC) #endif #ifdef CAPSTONE_HAS_SPARC | (1 << CS_ARCH_SPARC) #endif #ifdef CAPSTONE_HAS_SYSZ | (1 << CS_ARCH_SYSZ) #endif #ifdef CAPSTONE_HAS_XCORE | (1 << CS_ARCH_XCORE) #endif #ifdef CAPSTONE_HAS_M68K | (1 << CS_ARCH_M68K) #endif #ifdef CAPSTONE_HAS_TMS320C64X | (1 << CS_ARCH_TMS320C64X) #endif #ifdef CAPSTONE_HAS_M680X | (1 << CS_ARCH_M680X) #endif #ifdef CAPSTONE_HAS_EVM | (1 << CS_ARCH_EVM) #endif #ifdef CAPSTONE_HAS_MOS65XX | (1 << CS_ARCH_MOS65XX) #endif #ifdef CAPSTONE_HAS_WASM | (1 << CS_ARCH_WASM) #endif #ifdef CAPSTONE_HAS_BPF | (1 << CS_ARCH_BPF) #endif #ifdef CAPSTONE_HAS_RISCV | (1 << CS_ARCH_RISCV) #endif ; #if defined(CAPSTONE_USE_SYS_DYN_MEM) #if !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE) // default cs_malloc_t cs_mem_malloc = malloc; cs_calloc_t cs_mem_calloc = calloc; cs_realloc_t cs_mem_realloc = realloc; cs_free_t cs_mem_free = free; #if defined(_WIN32_WCE) cs_vsnprintf_t cs_vsnprintf = _vsnprintf; #else cs_vsnprintf_t cs_vsnprintf = vsnprintf; #endif // defined(_WIN32_WCE) #elif defined(_KERNEL_MODE) // Windows driver cs_malloc_t cs_mem_malloc = cs_winkernel_malloc; cs_calloc_t cs_mem_calloc = cs_winkernel_calloc; cs_realloc_t cs_mem_realloc = cs_winkernel_realloc; cs_free_t cs_mem_free = cs_winkernel_free; cs_vsnprintf_t cs_vsnprintf = cs_winkernel_vsnprintf; #else // OSX kernel extern void* kern_os_malloc(size_t size); extern void kern_os_free(void* addr); extern void* kern_os_realloc(void* addr, size_t nsize); static void* cs_kern_os_calloc(size_t num, size_t size) { return kern_os_malloc(num * size); // malloc bzeroes the buffer } cs_malloc_t cs_mem_malloc = kern_os_malloc; cs_calloc_t cs_mem_calloc = cs_kern_os_calloc; cs_realloc_t cs_mem_realloc = kern_os_realloc; cs_free_t cs_mem_free = kern_os_free; cs_vsnprintf_t cs_vsnprintf = vsnprintf; #endif // !defined(CAPSTONE_HAS_OSXKERNEL) && !defined(_KERNEL_MODE) #else // User-defined cs_malloc_t cs_mem_malloc = NULL; cs_calloc_t cs_mem_calloc = NULL; cs_realloc_t cs_mem_realloc = NULL; cs_free_t cs_mem_free = NULL; cs_vsnprintf_t cs_vsnprintf = NULL; #endif // defined(CAPSTONE_USE_SYS_DYN_MEM) CAPSTONE_EXPORT unsigned int CAPSTONE_API cs_version(int *major, int *minor) { if (major != NULL && minor != NULL) { *major = CS_API_MAJOR; *minor = CS_API_MINOR; } return (CS_API_MAJOR << 8) + CS_API_MINOR; } CAPSTONE_EXPORT bool CAPSTONE_API cs_support(int query) { if (query == CS_ARCH_ALL) return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) | (1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) | (1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) | (1 << CS_ARCH_SYSZ) | (1 << CS_ARCH_XCORE) | (1 << CS_ARCH_M68K) | (1 << CS_ARCH_TMS320C64X) | (1 << CS_ARCH_M680X) | (1 << CS_ARCH_EVM) | (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) | (1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF)); if ((unsigned int)query < CS_ARCH_MAX) return all_arch & (1 << query); if (query == CS_SUPPORT_DIET) { #ifdef CAPSTONE_DIET return true; #else return false; #endif } if (query == CS_SUPPORT_X86_REDUCE) { #if defined(CAPSTONE_HAS_X86) && defined(CAPSTONE_X86_REDUCE) return true; #else return false; #endif } // unsupported query return false; } CAPSTONE_EXPORT cs_err CAPSTONE_API cs_errno(csh handle) { struct cs_struct *ud; if (!handle) return CS_ERR_CSH; ud = (struct cs_struct *)(uintptr_t)handle; return ud->errnum; } CAPSTONE_EXPORT const char * CAPSTONE_API cs_strerror(cs_err code) { switch(code) { default: return "Unknown error code"; case CS_ERR_OK: return "OK (CS_ERR_OK)"; case CS_ERR_MEM: return "Out of memory (CS_ERR_MEM)"; case CS_ERR_ARCH: return "Invalid/unsupported architecture(CS_ERR_ARCH)"; case CS_ERR_HANDLE: return "Invalid handle (CS_ERR_HANDLE)"; case CS_ERR_CSH: return "Invalid csh (CS_ERR_CSH)"; case CS_ERR_MODE: return "Invalid mode (CS_ERR_MODE)"; case CS_ERR_OPTION: return "Invalid option (CS_ERR_OPTION)"; case CS_ERR_DETAIL: return "Details are unavailable (CS_ERR_DETAIL)"; case CS_ERR_MEMSETUP: return "Dynamic memory management uninitialized (CS_ERR_MEMSETUP)"; case CS_ERR_VERSION: return "Different API version between core & binding (CS_ERR_VERSION)"; case CS_ERR_DIET: return "Information irrelevant in diet engine (CS_ERR_DIET)"; case CS_ERR_SKIPDATA: return "Information irrelevant for 'data' instruction in SKIPDATA mode (CS_ERR_SKIPDATA)"; case CS_ERR_X86_ATT: return "AT&T syntax is unavailable (CS_ERR_X86_ATT)"; case CS_ERR_X86_INTEL: return "INTEL syntax is unavailable (CS_ERR_X86_INTEL)"; case CS_ERR_X86_MASM: return "MASM syntax is unavailable (CS_ERR_X86_MASM)"; } } CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle) { cs_err err; struct cs_struct *ud; if (!cs_mem_malloc || !cs_mem_calloc || !cs_mem_realloc || !cs_mem_free || !cs_vsnprintf) // Error: before cs_open(), dynamic memory management must be initialized // with cs_option(CS_OPT_MEM) return CS_ERR_MEMSETUP; if (arch < CS_ARCH_MAX && arch_configs[arch].arch_init) { // verify if requested mode is valid if (mode & arch_configs[arch].arch_disallowed_mode_mask) { *handle = 0; return CS_ERR_MODE; } ud = cs_mem_calloc(1, sizeof(*ud)); if (!ud) { // memory insufficient return CS_ERR_MEM; } ud->errnum = CS_ERR_OK; ud->arch = arch; ud->mode = mode; // by default, do not break instruction into details ud->detail = CS_OPT_OFF; // default skipdata setup ud->skipdata_setup.mnemonic = SKIPDATA_MNEM; err = arch_configs[ud->arch].arch_init(ud); if (err) { cs_mem_free(ud); *handle = 0; return err; } *handle = (uintptr_t)ud; return CS_ERR_OK; } else { *handle = 0; return CS_ERR_ARCH; } } CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle) { struct cs_struct *ud; struct insn_mnem *next, *tmp; if (*handle == 0) // invalid handle return CS_ERR_CSH; ud = (struct cs_struct *)(*handle); if (ud->printer_info) cs_mem_free(ud->printer_info); // free the linked list of customized mnemonic tmp = ud->mnem_list; while(tmp) { next = tmp->next; cs_mem_free(tmp); tmp = next; } cs_mem_free(ud->insn_cache); memset(ud, 0, sizeof(*ud)); cs_mem_free(ud); // invalidate this handle by ZERO out its value. // this is to make sure it is unusable after cs_close() *handle = 0; return CS_ERR_OK; } // replace str1 in target with str2; target starts with str1 // output is put into result (which is array of char with size CS_MNEMONIC_SIZE) // return 0 on success, -1 on failure static int str_replace(char *result, char *target, const char *str1, char *str2) { // only perform replacement if the output fits into result if (strlen(target) - strlen(str1) + strlen(str2) < CS_MNEMONIC_SIZE - 1) { // copy str2 to begining of result strcpy(result, str2); // skip str1 - already replaced by str2 strcat(result, target + strlen(str1)); return 0; } else return -1; } // fill insn with mnemonic & operands info static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci, PostPrinter_t postprinter, const uint8_t *code) { #ifndef CAPSTONE_DIET char *sp, *mnem; #endif uint16_t copy_size = MIN(sizeof(insn->bytes), insn->size); // fill the instruction bytes. // we might skip some redundant bytes in front in the case of X86 memcpy(insn->bytes, code + insn->size - copy_size, copy_size); insn->size = copy_size; // alias instruction might have ID saved in OpcodePub if (MCInst_getOpcodePub(mci)) insn->id = MCInst_getOpcodePub(mci); // post printer handles some corner cases (hacky) if (postprinter) postprinter((csh)handle, insn, buffer, mci); #ifndef CAPSTONE_DIET // fill in mnemonic & operands // find first space or tab mnem = insn->mnemonic; for (sp = buffer; *sp; sp++) { if (*sp == ' '|| *sp == '\t') break; if (*sp == '|') // lock|rep prefix for x86 *sp = ' '; // copy to @mnemonic *mnem = *sp; mnem++; } *mnem = '\0'; // we might have customized mnemonic if (handle->mnem_list) { struct insn_mnem *tmp = handle->mnem_list; while(tmp) { if (tmp->insn.id == insn->id) { char str[CS_MNEMONIC_SIZE]; if (!str_replace(str, insn->mnemonic, cs_insn_name((csh)handle, insn->id), tmp->insn.mnemonic)) { // copy result to mnemonic (void)strncpy(insn->mnemonic, str, sizeof(insn->mnemonic) - 1); insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0'; } break; } tmp = tmp->next; } } // copy @op_str if (*sp) { // find the next non-space char sp++; for (; ((*sp == ' ') || (*sp == '\t')); sp++); strncpy(insn->op_str, sp, sizeof(insn->op_str) - 1); insn->op_str[sizeof(insn->op_str) - 1] = '\0'; } else insn->op_str[0] = '\0'; #endif } // how many bytes will we skip when encountering data (CS_OPT_SKIPDATA)? // this very much depends on instruction alignment requirement of each arch. static uint8_t skipdata_size(cs_struct *handle) { switch(handle->arch) { default: // should never reach return (uint8_t)-1; case CS_ARCH_ARM: // skip 2 bytes on Thumb mode. if (handle->mode & CS_MODE_THUMB) return 2; // otherwise, skip 4 bytes return 4; case CS_ARCH_ARM64: case CS_ARCH_MIPS: case CS_ARCH_PPC: case CS_ARCH_SPARC: // skip 4 bytes return 4; case CS_ARCH_SYSZ: // SystemZ instruction's length can be 2, 4 or 6 bytes, // so we just skip 2 bytes return 2; case CS_ARCH_X86: // X86 has no restriction on instruction alignment return 1; case CS_ARCH_XCORE: // XCore instruction's length can be 2 or 4 bytes, // so we just skip 2 bytes return 2; case CS_ARCH_M68K: // M68K has 2 bytes instruction alignment but contain multibyte instruction so we skip 2 bytes return 2; case CS_ARCH_TMS320C64X: // TMS320C64x alignment is 4. return 4; case CS_ARCH_M680X: // M680X alignment is 1. return 1; case CS_ARCH_EVM: // EVM alignment is 1. return 1; case CS_ARCH_WASM: //WASM alignment is 1 return 1; case CS_ARCH_MOS65XX: // MOS65XX alignment is 1. return 1; case CS_ARCH_BPF: // both classic and extended BPF have alignment 8. return 8; case CS_ARCH_RISCV: // special compress mode if (handle->mode & CS_MODE_RISCVC) return 2; return 4; } } CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value) { struct cs_struct *handle; cs_opt_mnem *opt; // cs_option() can be called with NULL handle just for CS_OPT_MEM // This is supposed to be executed before all other APIs (even cs_open()) if (type == CS_OPT_MEM) { cs_opt_mem *mem = (cs_opt_mem *)value; cs_mem_malloc = mem->malloc; cs_mem_calloc = mem->calloc; cs_mem_realloc = mem->realloc; cs_mem_free = mem->free; cs_vsnprintf = mem->vsnprintf; return CS_ERR_OK; } handle = (struct cs_struct *)(uintptr_t)ud; if (!handle) return CS_ERR_CSH; switch(type) { default: break; case CS_OPT_UNSIGNED: handle->imm_unsigned = (cs_opt_value)value; return CS_ERR_OK; case CS_OPT_DETAIL: handle->detail = (cs_opt_value)value; return CS_ERR_OK; case CS_OPT_SKIPDATA: handle->skipdata = (value == CS_OPT_ON); if (handle->skipdata) { if (handle->skipdata_size == 0) { // set the default skipdata size handle->skipdata_size = skipdata_size(handle); } } return CS_ERR_OK; case CS_OPT_SKIPDATA_SETUP: if (value) { handle->skipdata_setup = *((cs_opt_skipdata *)value); if (handle->skipdata_setup.mnemonic == NULL) { handle->skipdata_setup.mnemonic = SKIPDATA_MNEM; } } return CS_ERR_OK; case CS_OPT_MNEMONIC: opt = (cs_opt_mnem *)value; if (opt->id) { if (opt->mnemonic) { struct insn_mnem *tmp; // add new instruction, or replace existing instruction // 1. find if we already had this insn in the linked list tmp = handle->mnem_list; while(tmp) { if (tmp->insn.id == opt->id) { // found this instruction, so replace its mnemonic (void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1); tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0'; break; } tmp = tmp->next; } // 2. add this instruction if we have not had it yet if (!tmp) { tmp = cs_mem_malloc(sizeof(*tmp)); tmp->insn.id = opt->id; (void)strncpy(tmp->insn.mnemonic, opt->mnemonic, sizeof(tmp->insn.mnemonic) - 1); tmp->insn.mnemonic[sizeof(tmp->insn.mnemonic) - 1] = '\0'; // this new instruction is heading the list tmp->next = handle->mnem_list; handle->mnem_list = tmp; } return CS_ERR_OK; } else { struct insn_mnem *prev, *tmp; // we want to delete an existing instruction // iterate the list to find the instruction to remove it tmp = handle->mnem_list; prev = tmp; while(tmp) { if (tmp->insn.id == opt->id) { // delete this instruction if (tmp == prev) { // head of the list handle->mnem_list = tmp->next; } else { prev->next = tmp->next; } cs_mem_free(tmp); break; } prev = tmp; tmp = tmp->next; } } } return CS_ERR_OK; case CS_OPT_MODE: // verify if requested mode is valid if (value & arch_configs[handle->arch].arch_disallowed_mode_mask) { return CS_ERR_OPTION; } break; } return arch_configs[handle->arch].arch_option(handle, type, value); } // generate @op_str for data instruction of SKIPDATA #ifndef CAPSTONE_DIET static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size) { char *p = opstr; int len; size_t i; size_t available = sizeof(((cs_insn*)NULL)->op_str); if (!size) { opstr[0] = '\0'; return; } len = cs_snprintf(p, available, "0x%02x", buffer[0]); p+= len; available -= len; for(i = 1; i < size; i++) { len = cs_snprintf(p, available, ", 0x%02x", buffer[i]); if (len < 0) { break; } if ((size_t)len > available - 1) { break; } p+= len; available -= len; } } #endif // dynamicly allocate memory to contain disasm insn // NOTE: caller must free() the allocated memory itself to avoid memory leaking CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) { struct cs_struct *handle; MCInst mci; uint16_t insn_size; size_t c = 0, i; unsigned int f = 0; // index of the next instruction in the cache cs_insn *insn_cache; // cache contains disassembled instructions void *total = NULL; size_t total_size = 0; // total size of output buffer containing all insns bool r; void *tmp; size_t skipdata_bytes; uint64_t offset_org; // save all the original info of the buffer size_t size_org; const uint8_t *buffer_org; unsigned int cache_size = INSN_CACHE_SIZE; size_t next_offset; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle) { // FIXME: how to handle this case: // handle->errnum = CS_ERR_HANDLE; return 0; } handle->errnum = CS_ERR_OK; // reset IT block of ARM structure if (handle->arch == CS_ARCH_ARM) handle->ITBlock.size = 0; #ifdef CAPSTONE_USE_SYS_DYN_MEM if (count > 0 && count <= INSN_CACHE_SIZE) cache_size = (unsigned int) count; #endif // save the original offset for SKIPDATA buffer_org = buffer; offset_org = offset; size_org = size; total_size = sizeof(cs_insn) * cache_size; total = cs_mem_malloc(total_size); if (total == NULL) { // insufficient memory handle->errnum = CS_ERR_MEM; return 0; } insn_cache = total; while (size > 0) { MCInst_Init(&mci); mci.csh = handle; // relative branches need to know the address & size of current insn mci.address = offset; if (handle->detail) { // allocate memory for @detail pointer insn_cache->detail = cs_mem_malloc(sizeof(cs_detail)); } else { insn_cache->detail = NULL; } // save all the information for non-detailed mode mci.flat_insn = insn_cache; mci.flat_insn->address = offset; #ifdef CAPSTONE_DIET // zero out mnemonic & op_str mci.flat_insn->mnemonic[0] = '\0'; mci.flat_insn->op_str[0] = '\0'; #endif r = handle->disasm(ud, buffer, size, &mci, &insn_size, offset, handle->getinsn_info); if (r) { SStream ss; SStream_Init(&ss); mci.flat_insn->size = insn_size; // map internal instruction opcode to public insn ID handle->insn_id(handle, insn_cache, mci.Opcode); handle->printer(&mci, &ss, handle->printer_info); fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer); // adjust for pseudo opcode (X86) if (handle->arch == CS_ARCH_X86) insn_cache->id += mci.popcode_adjust; next_offset = insn_size; } else { // encounter a broken instruction // free memory of @detail pointer if (handle->detail) { cs_mem_free(insn_cache->detail); } // if there is no request to skip data, or remaining data is too small, // then bail out if (!handle->skipdata || handle->skipdata_size > size) break; if (handle->skipdata_setup.callback) { skipdata_bytes = handle->skipdata_setup.callback(buffer_org, size_org, (size_t)(offset - offset_org), handle->skipdata_setup.user_data); if (skipdata_bytes > size) // remaining data is not enough break; if (!skipdata_bytes) // user requested not to skip data, so bail out break; } else skipdata_bytes = handle->skipdata_size; // we have to skip some amount of data, depending on arch & mode insn_cache->id = 0; // invalid ID for this "data" instruction insn_cache->address = offset; insn_cache->size = (uint16_t)skipdata_bytes; memcpy(insn_cache->bytes, buffer, skipdata_bytes); #ifdef CAPSTONE_DIET insn_cache->mnemonic[0] = '\0'; insn_cache->op_str[0] = '\0'; #else strncpy(insn_cache->mnemonic, handle->skipdata_setup.mnemonic, sizeof(insn_cache->mnemonic) - 1); skipdata_opstr(insn_cache->op_str, buffer, skipdata_bytes); #endif insn_cache->detail = NULL; next_offset = skipdata_bytes; } // one more instruction entering the cache f++; // one more instruction disassembled c++; if (count > 0 && c == count) // already got requested number of instructions break; if (f == cache_size) { // full cache, so expand the cache to contain incoming insns cache_size = cache_size * 8 / 5; // * 1.6 ~ golden ratio total_size += (sizeof(cs_insn) * cache_size); tmp = cs_mem_realloc(total, total_size); if (tmp == NULL) { // insufficient memory if (handle->detail) { insn_cache = (cs_insn *)total; for (i = 0; i < c; i++, insn_cache++) cs_mem_free(insn_cache->detail); } cs_mem_free(total); *insn = NULL; handle->errnum = CS_ERR_MEM; return 0; } total = tmp; // continue to fill in the cache after the last instruction insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c); // reset f back to 0, so we fill in the cache from begining f = 0; } else insn_cache++; buffer += next_offset; size -= next_offset; offset += next_offset; } if (!c) { // we did not disassemble any instruction cs_mem_free(total); total = NULL; } else if (f != cache_size) { // total did not fully use the last cache, so downsize it tmp = cs_mem_realloc(total, total_size - (cache_size - f) * sizeof(*insn_cache)); if (tmp == NULL) { // insufficient memory // free all detail pointers if (handle->detail) { insn_cache = (cs_insn *)total; for (i = 0; i < c; i++, insn_cache++) cs_mem_free(insn_cache->detail); } cs_mem_free(total); *insn = NULL; handle->errnum = CS_ERR_MEM; return 0; } total = tmp; } *insn = total; return c; } CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count) { size_t i; // free all detail pointers for (i = 0; i < count; i++) cs_mem_free(insn[i].detail); // then free pointer to cs_insn array cs_mem_free(insn); } CAPSTONE_EXPORT cs_insn * CAPSTONE_API cs_malloc(csh ud) { cs_insn *insn; struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; insn = cs_mem_malloc(sizeof(cs_insn)); if (!insn) { // insufficient memory handle->errnum = CS_ERR_MEM; return NULL; } else { if (handle->detail) { // allocate memory for @detail pointer insn->detail = cs_mem_malloc(sizeof(cs_detail)); if (insn->detail == NULL) { // insufficient memory cs_mem_free(insn); handle->errnum = CS_ERR_MEM; return NULL; } } else insn->detail = NULL; } return insn; } // iterator for instruction "single-stepping" CAPSTONE_EXPORT bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn) { struct cs_struct *handle; uint16_t insn_size; MCInst mci; bool r; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle) { return false; } handle->errnum = CS_ERR_OK; MCInst_Init(&mci); mci.csh = handle; // relative branches need to know the address & size of current insn mci.address = *address; // save all the information for non-detailed mode mci.flat_insn = insn; mci.flat_insn->address = *address; #ifdef CAPSTONE_DIET // zero out mnemonic & op_str mci.flat_insn->mnemonic[0] = '\0'; mci.flat_insn->op_str[0] = '\0'; #endif r = handle->disasm(ud, *code, *size, &mci, &insn_size, *address, handle->getinsn_info); if (r) { SStream ss; SStream_Init(&ss); mci.flat_insn->size = insn_size; // map internal instruction opcode to public insn ID handle->insn_id(handle, insn, mci.Opcode); handle->printer(&mci, &ss, handle->printer_info); fill_insn(handle, insn, ss.buffer, &mci, handle->post_printer, *code); // adjust for pseudo opcode (X86) if (handle->arch == CS_ARCH_X86) insn->id += mci.popcode_adjust; *code += insn_size; *size -= insn_size; *address += insn_size; } else { // encounter a broken instruction size_t skipdata_bytes; // if there is no request to skip data, or remaining data is too small, // then bail out if (!handle->skipdata || handle->skipdata_size > *size) return false; if (handle->skipdata_setup.callback) { skipdata_bytes = handle->skipdata_setup.callback(*code, *size, 0, handle->skipdata_setup.user_data); if (skipdata_bytes > *size) // remaining data is not enough return false; if (!skipdata_bytes) // user requested not to skip data, so bail out return false; } else skipdata_bytes = handle->skipdata_size; // we have to skip some amount of data, depending on arch & mode insn->id = 0; // invalid ID for this "data" instruction insn->address = *address; insn->size = (uint16_t)skipdata_bytes; #ifdef CAPSTONE_DIET insn->mnemonic[0] = '\0'; insn->op_str[0] = '\0'; #else memcpy(insn->bytes, *code, skipdata_bytes); strncpy(insn->mnemonic, handle->skipdata_setup.mnemonic, sizeof(insn->mnemonic) - 1); skipdata_opstr(insn->op_str, *code, skipdata_bytes); #endif *code += skipdata_bytes; *size -= skipdata_bytes; *address += skipdata_bytes; } return true; } // return friendly name of regiser in a string CAPSTONE_EXPORT const char * CAPSTONE_API cs_reg_name(csh ud, unsigned int reg) { struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; if (!handle || handle->reg_name == NULL) { return NULL; } return handle->reg_name(ud, reg); } CAPSTONE_EXPORT const char * CAPSTONE_API cs_insn_name(csh ud, unsigned int insn) { struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; if (!handle || handle->insn_name == NULL) { return NULL; } return handle->insn_name(ud, insn); } CAPSTONE_EXPORT const char * CAPSTONE_API cs_group_name(csh ud, unsigned int group) { struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud; if (!handle || handle->group_name == NULL) { return NULL; } return handle->group_name(ud, group); } CAPSTONE_EXPORT bool CAPSTONE_API cs_insn_group(csh ud, const cs_insn *insn, unsigned int group_id) { struct cs_struct *handle; if (!ud) return false; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle->detail) { handle->errnum = CS_ERR_DETAIL; return false; } if (!insn->id) { handle->errnum = CS_ERR_SKIPDATA; return false; } if (!insn->detail) { handle->errnum = CS_ERR_DETAIL; return false; } return arr_exist8(insn->detail->groups, insn->detail->groups_count, group_id); } CAPSTONE_EXPORT bool CAPSTONE_API cs_reg_read(csh ud, const cs_insn *insn, unsigned int reg_id) { struct cs_struct *handle; if (!ud) return false; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle->detail) { handle->errnum = CS_ERR_DETAIL; return false; } if (!insn->id) { handle->errnum = CS_ERR_SKIPDATA; return false; } if (!insn->detail) { handle->errnum = CS_ERR_DETAIL; return false; } return arr_exist(insn->detail->regs_read, insn->detail->regs_read_count, reg_id); } CAPSTONE_EXPORT bool CAPSTONE_API cs_reg_write(csh ud, const cs_insn *insn, unsigned int reg_id) { struct cs_struct *handle; if (!ud) return false; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle->detail) { handle->errnum = CS_ERR_DETAIL; return false; } if (!insn->id) { handle->errnum = CS_ERR_SKIPDATA; return false; } if (!insn->detail) { handle->errnum = CS_ERR_DETAIL; return false; } return arr_exist(insn->detail->regs_write, insn->detail->regs_write_count, reg_id); } CAPSTONE_EXPORT int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) { struct cs_struct *handle; unsigned int count = 0, i; if (!ud) return -1; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle->detail) { handle->errnum = CS_ERR_DETAIL; return -1; } if (!insn->id) { handle->errnum = CS_ERR_SKIPDATA; return -1; } if (!insn->detail) { handle->errnum = CS_ERR_DETAIL; return -1; } handle->errnum = CS_ERR_OK; switch (handle->arch) { default: handle->errnum = CS_ERR_HANDLE; return -1; case CS_ARCH_ARM: for (i = 0; i < insn->detail->arm.op_count; i++) if (insn->detail->arm.operands[i].type == (arm_op_type)op_type) count++; break; case CS_ARCH_ARM64: for (i = 0; i < insn->detail->arm64.op_count; i++) if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type) count++; break; case CS_ARCH_X86: for (i = 0; i < insn->detail->x86.op_count; i++) if (insn->detail->x86.operands[i].type == (x86_op_type)op_type) count++; break; case CS_ARCH_MIPS: for (i = 0; i < insn->detail->mips.op_count; i++) if (insn->detail->mips.operands[i].type == (mips_op_type)op_type) count++; break; case CS_ARCH_PPC: for (i = 0; i < insn->detail->ppc.op_count; i++) if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) count++; break; case CS_ARCH_SPARC: for (i = 0; i < insn->detail->sparc.op_count; i++) if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) count++; break; case CS_ARCH_SYSZ: for (i = 0; i < insn->detail->sysz.op_count; i++) if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) count++; break; case CS_ARCH_XCORE: for (i = 0; i < insn->detail->xcore.op_count; i++) if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type) count++; break; case CS_ARCH_M68K: for (i = 0; i < insn->detail->m68k.op_count; i++) if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type) count++; break; case CS_ARCH_TMS320C64X: for (i = 0; i < insn->detail->tms320c64x.op_count; i++) if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type) count++; break; case CS_ARCH_M680X: for (i = 0; i < insn->detail->m680x.op_count; i++) if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type) count++; break; case CS_ARCH_EVM: break; case CS_ARCH_MOS65XX: for (i = 0; i < insn->detail->mos65xx.op_count; i++) if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type) count++; break; case CS_ARCH_WASM: for (i = 0; i < insn->detail->wasm.op_count; i++) if (insn->detail->wasm.operands[i].type == (wasm_op_type)op_type) count++; break; case CS_ARCH_BPF: for (i = 0; i < insn->detail->bpf.op_count; i++) if (insn->detail->bpf.operands[i].type == (bpf_op_type)op_type) count++; break; case CS_ARCH_RISCV: for (i = 0; i < insn->detail->riscv.op_count; i++) if (insn->detail->riscv.operands[i].type == (riscv_op_type)op_type) count++; break; } return count; } CAPSTONE_EXPORT int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, unsigned int post) { struct cs_struct *handle; unsigned int count = 0, i; if (!ud) return -1; handle = (struct cs_struct *)(uintptr_t)ud; if (!handle->detail) { handle->errnum = CS_ERR_DETAIL; return -1; } if (!insn->id) { handle->errnum = CS_ERR_SKIPDATA; return -1; } if (!insn->detail) { handle->errnum = CS_ERR_DETAIL; return -1; } handle->errnum = CS_ERR_OK; switch (handle->arch) { default: handle->errnum = CS_ERR_HANDLE; return -1; case CS_ARCH_ARM: for (i = 0; i < insn->detail->arm.op_count; i++) { if (insn->detail->arm.operands[i].type == (arm_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_ARM64: for (i = 0; i < insn->detail->arm64.op_count; i++) { if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_X86: for (i = 0; i < insn->detail->x86.op_count; i++) { if (insn->detail->x86.operands[i].type == (x86_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_MIPS: for (i = 0; i < insn->detail->mips.op_count; i++) { if (insn->detail->mips.operands[i].type == (mips_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_PPC: for (i = 0; i < insn->detail->ppc.op_count; i++) { if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_SPARC: for (i = 0; i < insn->detail->sparc.op_count; i++) { if (insn->detail->sparc.operands[i].type == (sparc_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_SYSZ: for (i = 0; i < insn->detail->sysz.op_count; i++) { if (insn->detail->sysz.operands[i].type == (sysz_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_XCORE: for (i = 0; i < insn->detail->xcore.op_count; i++) { if (insn->detail->xcore.operands[i].type == (xcore_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_M68K: for (i = 0; i < insn->detail->m68k.op_count; i++) { if (insn->detail->m68k.operands[i].type == (m68k_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_TMS320C64X: for (i = 0; i < insn->detail->tms320c64x.op_count; i++) { if (insn->detail->tms320c64x.operands[i].type == (tms320c64x_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_M680X: for (i = 0; i < insn->detail->m680x.op_count; i++) { if (insn->detail->m680x.operands[i].type == (m680x_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_EVM: #if 0 for (i = 0; i < insn->detail->evm.op_count; i++) { if (insn->detail->evm.operands[i].type == (evm_op_type)op_type) count++; if (count == post) return i; } #endif break; case CS_ARCH_MOS65XX: for (i = 0; i < insn->detail->mos65xx.op_count; i++) { if (insn->detail->mos65xx.operands[i].type == (mos65xx_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_WASM: for (i = 0; i < insn->detail->wasm.op_count; i++) { if (insn->detail->wasm.operands[i].type == (wasm_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_BPF: for (i = 0; i < insn->detail->bpf.op_count; i++) { if (insn->detail->bpf.operands[i].type == (bpf_op_type)op_type) count++; if (count == post) return i; } break; case CS_ARCH_RISCV: for (i = 0; i < insn->detail->riscv.op_count; i++) { if (insn->detail->riscv.operands[i].type == (riscv_op_type)op_type) count++; if (count == post) return i; } break; } return -1; } CAPSTONE_EXPORT cs_err CAPSTONE_API cs_regs_access(csh ud, const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count) { struct cs_struct *handle; if (!ud) return -1; handle = (struct cs_struct *)(uintptr_t)ud; #ifdef CAPSTONE_DIET // This API does not work in DIET mode handle->errnum = CS_ERR_DIET; return CS_ERR_DIET; #else if (!handle->detail) { handle->errnum = CS_ERR_DETAIL; return CS_ERR_DETAIL; } if (!insn->id) { handle->errnum = CS_ERR_SKIPDATA; return CS_ERR_SKIPDATA; } if (!insn->detail) { handle->errnum = CS_ERR_DETAIL; return CS_ERR_DETAIL; } if (handle->reg_access) { handle->reg_access(insn, regs_read, regs_read_count, regs_write, regs_write_count); } else { // this arch is unsupported yet handle->errnum = CS_ERR_ARCH; return CS_ERR_ARCH; } return CS_ERR_OK; #endif } capstone-sys-0.15.0/capstone/cs_priv.h000064400000000000000000000060270072674642500160260ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ #ifndef CS_PRIV_H #define CS_PRIV_H #ifdef CAPSTONE_DEBUG #include #endif #include #include "MCInst.h" #include "SStream.h" typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info); // function to be called after Printer_t // this is the best time to gather insn's characteristics typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci); typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); typedef const char *(*GetName_t)(csh handle, unsigned int id); typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id); // return register name, given register ID typedef const char *(*GetRegisterName_t)(unsigned RegNo); // return registers accessed by instruction typedef void (*GetRegisterAccess_t)(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); // for ARM only typedef struct ARM_ITStatus { unsigned char ITStates[8]; unsigned int size; } ARM_ITStatus; // Customize mnemonic for instructions with alternative name. struct customized_mnem { // ID of instruction to be customized. unsigned int id; // Customized instruction mnemonic. char mnemonic[CS_MNEMONIC_SIZE]; }; struct insn_mnem { struct customized_mnem insn; struct insn_mnem *next; // linked list of customized mnemonics }; struct cs_struct { cs_arch arch; cs_mode mode; Printer_t printer; // asm printer void *printer_info; // aux info for printer Disasm_t disasm; // disassembler void *getinsn_info; // auxiliary info for printer GetName_t reg_name; GetName_t insn_name; GetName_t group_name; GetID_t insn_id; PostPrinter_t post_printer; cs_err errnum; ARM_ITStatus ITBlock; // for Arm only cs_opt_value detail, imm_unsigned; int syntax; // asm syntax for simple printer such as ARM, Mips & PPC bool doing_mem; // handling memory operand in InstPrinter code unsigned short *insn_cache; // index caching for mapping.c GetRegisterName_t get_regname; bool skipdata; // set this to True if we skip data when disassembling uint8_t skipdata_size; // how many bytes to skip cs_opt_skipdata skipdata_setup; // user-defined skipdata setup const uint8_t *regsize_map; // map to register size (x86-only for now) GetRegisterAccess_t reg_access; struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic }; #define MAX_ARCH CS_ARCH_MAX // Returns a bool (0 or 1) whether big endian is enabled for a mode #define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0) extern cs_malloc_t cs_mem_malloc; extern cs_calloc_t cs_mem_calloc; extern cs_realloc_t cs_mem_realloc; extern cs_free_t cs_mem_free; extern cs_vsnprintf_t cs_vsnprintf; // By defining CAPSTONE_DEBUG assertions can be used. // For any release build CAPSTONE_DEBUG has to be undefined. #ifdef CAPSTONE_DEBUG #define CS_ASSERT(expr) assert(expr) #else #define CS_ASSERT(expr) #endif #endif capstone-sys-0.15.0/capstone/cstool/Makefile000064400000000000000000000016030072674642500171460ustar 00000000000000# Makefile for Cstool of Capstone Disassembly Engine include ../functions.mk .PHONY: clean all LIBNAME = capstone CFLAGS += -I../include -I. LDFLAGS += -O3 -Wall -L.. -l$(LIBNAME) TARGET = cstool SOURCES := $(wildcard *.c) OBJECTS := $(SOURCES:.c=.o) LIBCAPSTONE = libcapstone.a IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l) ifeq ($(IS_CYGWIN),1) LIBCAPSTONE = capstone.lib else IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l) ifeq ($(IS_MINGW),1) LIBCAPSTONE = capstone.lib endif endif all: $(TARGET) $(TARGET): ../$(LIBCAPSTONE) $(OBJECTS) ifeq ($(V), 0) $(call log,LINK,$@) @${CC} $(OBJECTS) $(LDFLAGS) -o $@ else ${CC} $(OBJECTS) $(LDFLAGS) -o $@ endif clean: ${RM} -rf *.o $(TARGET) ${RM} -f *.d %.o: %.c ifeq ($(V), 0) $(call log,CC,$@) @${CC} $(CFLAGS) -c $< -o $@ else ${CC} $(CFLAGS) -c $< -o $@ endif capstone-sys-0.15.0/capstone/cstool/README000064400000000000000000000024330072674642500163700ustar 00000000000000This directory contains cstool of Capstone Engine. Cstool is a command-line tool to disassemble assembly hex-string. For example, to decode a hexcode string for Intel 32bit, run: $ cstool x32 "90 91" 0 90 nop 1 91 xchg eax, ecx Cstool disassembles the input and prints out the assembly instructions. On each line, the first column is the instruction offset, the second column is opcodes, and the rest is the instruction itself. Cstool is flexible enough to accept all kind of hexcode format. The following inputs have the same output with the example above. $ cstool x32 "0x90 0x91" $ cstool x32 "\x90\x91" $ cstool x32 "90,91" $ cstool x32 "90;91" $ cstool x32 "90+91" $ cstool x32 "90:91" To print out instruction details, run Cstool with -d option, like below. $ cstool -d x32 "01 d8" 0 01d8 add eax, ebx Prefix:0x00 0x00 0x00 0x00 Opcode:0x01 0x00 0x00 0x00 rex: 0x0 addr_size: 4 modrm: 0xd8 disp: 0x0 sib: 0x0 op_count: 2 operands[0].type: REG = eax operands[0].size: 4 operands[0].access: READ | WRITE operands[1].type: REG = ebx operands[1].size: 4 operands[1].access: READ Registers read: eax ebx Registers modified: eflags eax EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF To see all the supported options, run ./cstool capstone-sys-0.15.0/capstone/cstool/cstool.c000064400000000000000000000402470072674642500171640ustar 00000000000000/* Tang Yuhang 2016 */ /* pancake 2017 */ #include #include #include #include "getopt.h" #include void print_string_hex(const char *comment, unsigned char *str, size_t len); static struct { const char *name; cs_arch arch; cs_mode mode; } all_archs[] = { { "arm", CS_ARCH_ARM, CS_MODE_ARM }, { "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, { "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, { "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, { "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN }, { "armv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 }, { "thumbv8", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 }, { "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, { "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN }, { "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, { "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, { "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN }, { "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN }, { "arm64", CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN }, { "arm64be", CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN }, { "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN }, { "mipsmicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO }, { "mipsbemicro", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN }, { "mipsbe32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN}, { "mipsbe32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN | CS_MODE_MICRO }, { "mips32r6", CS_ARCH_MIPS, CS_MODE_MIPS32R6 }, { "mips32r6micro", CS_ARCH_MIPS, CS_MODE_MIPS32R6 | CS_MODE_MICRO }, { "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN }, { "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN }, { "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN }, { "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 { "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT { "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32 { "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT { "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64 { "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT { "ppc32", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_LITTLE_ENDIAN }, { "ppc32be", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN }, { "ppc32qpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, { "ppc32beqpx", CS_ARCH_PPC, CS_MODE_32 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, { "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN }, { "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN }, { "ppc64qpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_LITTLE_ENDIAN }, { "ppc64beqpx", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_QPX | CS_MODE_BIG_ENDIAN }, { "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN }, { "sparcv9", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN | CS_MODE_V9 }, { "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, { "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, { "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN }, { "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN }, { "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN }, { "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 }, { "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, { "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 }, { "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 }, { "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 }, { "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 }, { "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 }, { "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 }, { "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 }, { "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 }, { "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 }, { "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 }, { "evm", CS_ARCH_EVM, 0 }, { "wasm", CS_ARCH_WASM, 0 }, { "bpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC }, { "bpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC }, { "ebpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED }, { "ebpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED }, { "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 }, { "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 }, { "6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 }, { "65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 }, { "w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 }, { "65816", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX }, { NULL } }; void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins); void print_insn_detail_arm(csh handle, cs_insn *ins); void print_insn_detail_arm64(csh handle, cs_insn *ins); void print_insn_detail_mips(csh handle, cs_insn *ins); void print_insn_detail_ppc(csh handle, cs_insn *ins); void print_insn_detail_sparc(csh handle, cs_insn *ins); void print_insn_detail_sysz(csh handle, cs_insn *ins); void print_insn_detail_xcore(csh handle, cs_insn *ins); void print_insn_detail_m68k(csh handle, cs_insn *ins); void print_insn_detail_tms320c64x(csh handle, cs_insn *ins); void print_insn_detail_m680x(csh handle, cs_insn *ins); void print_insn_detail_evm(csh handle, cs_insn *ins); void print_insn_detail_riscv(csh handle, cs_insn *ins); void print_insn_detail_wasm(csh handle, cs_insn *ins); void print_insn_detail_mos65xx(csh handle, cs_insn *ins); void print_insn_detail_bpf(csh handle, cs_insn *ins); static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins); void print_string_hex(const char *comment, unsigned char *str, size_t len) { unsigned char *c; printf("%s", comment); for (c = str; c < str + len; c++) { printf("0x%02x ", *c & 0xff); } printf("\n"); } // convert hexchar to hexnum static uint8_t char_to_hexnum(char c) { if (c >= '0' && c <= '9') { return (uint8_t)(c - '0'); } if (c >= 'a' && c <= 'f') { return (uint8_t)(10 + c - 'a'); } // c >= 'A' && c <= 'F' return (uint8_t)(10 + c - 'A'); } // convert user input (char[]) to uint8_t[], each element of which is // valid hexadecimal, and return actual length of uint8_t[] in @size. static uint8_t *preprocess(char *code, size_t *size) { size_t i = 0, j = 0; uint8_t high, low; uint8_t *result; if (strlen(code) == 0) return NULL; result = (uint8_t *)malloc(strlen(code)); if (result != NULL) { while (code[i] != '\0') { if (isxdigit(code[i]) && isxdigit(code[i+1])) { high = 16 * char_to_hexnum(code[i]); low = char_to_hexnum(code[i+1]); result[j] = high + low; i++; j++; } i++; } *size = j; } return result; } static void usage(char *prog) { printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); printf("Syntax: %s [-d|-s|-u|-v] [start-address-in-hex-format]\n", prog); printf("\nThe following options are supported:\n"); if (cs_support(CS_ARCH_X86)) { printf(" x16 16-bit mode (X86)\n"); printf(" x32 32-bit mode (X86)\n"); printf(" x64 64-bit mode (X86)\n"); printf(" x16att 16-bit mode (X86), syntax AT&T\n"); printf(" x32att 32-bit mode (X86), syntax AT&T\n"); printf(" x64att 64-bit mode (X86), syntax AT&T\n"); } if (cs_support(CS_ARCH_ARM)) { printf(" arm arm\n"); printf(" armbe arm + big endian\n"); printf(" thumb thumb mode\n"); printf(" thumbbe thumb + big endian\n"); printf(" cortexm thumb + cortex-m extensions\n"); printf(" armv8 arm v8\n"); printf(" thumbv8 thumb v8\n"); printf(" armv8be arm v8 + big endian\n"); printf(" thumbv8be thumb v8 + big endian\n"); } if (cs_support(CS_ARCH_ARM64)) { printf(" arm64 aarch64 mode\n"); printf(" arm64be aarch64 + big endian\n"); } if (cs_support(CS_ARCH_MIPS)) { printf(" mips mips32 + little endian\n"); printf(" mipsbe mips32 + big endian\n"); printf(" mips64 mips64 + little endian\n"); printf(" mips64be mips64 + big endian\n"); } if (cs_support(CS_ARCH_PPC)) { printf(" ppc32 ppc32 + little endian\n"); printf(" ppc32be ppc32 + big endian\n"); printf(" ppc32qpx ppc32 + qpx + little endian\n"); printf(" ppc32beqpx ppc32 + qpx + big endian\n"); printf(" ppc64 ppc64 + little endian\n"); printf(" ppc64be ppc64 + big endian\n"); printf(" ppc64qpx ppc64 + qpx + little endian\n"); printf(" ppc64beqpx ppc64 + qpx + big endian\n"); } if (cs_support(CS_ARCH_SPARC)) { printf(" sparc sparc\n"); } if (cs_support(CS_ARCH_SYSZ)) { printf(" systemz systemz (s390x)\n"); } if (cs_support(CS_ARCH_XCORE)) { printf(" xcore xcore\n"); } if (cs_support(CS_ARCH_M68K)) { printf(" m68k m68k + big endian\n"); printf(" m68k40 m68k_040\n"); } if (cs_support(CS_ARCH_TMS320C64X)) { printf(" tms320c64x TMS320C64x\n"); } if (cs_support(CS_ARCH_M680X)) { printf(" m6800 M6800/2\n"); printf(" m6801 M6801/3\n"); printf(" m6805 M6805\n"); printf(" m6808 M68HC08\n"); printf(" m6809 M6809\n"); printf(" m6811 M68HC11\n"); printf(" cpu12 M68HC12/HCS12\n"); printf(" hd6301 HD6301/3\n"); printf(" hd6309 HD6309\n"); printf(" hcs08 HCS08\n"); } if (cs_support(CS_ARCH_EVM)) { printf(" evm Ethereum Virtual Machine\n"); } if (cs_support(CS_ARCH_MOS65XX)) { printf(" 6502 MOS 6502\n"); printf(" 65c02 WDC 65c02\n"); printf(" w65c02 WDC w65c02\n"); printf(" 65816 WDC 65816 (long m/x)\n"); } if (cs_support(CS_ARCH_WASM)) { printf(" wasm: Web Assembly\n"); } if (cs_support(CS_ARCH_BPF)) { printf(" bpf Classic BPF\n"); printf(" bpfbe Classic BPF + big endian\n"); printf(" ebpf Extended BPF\n"); printf(" ebpfbe Extended BPF + big endian\n"); } if (cs_support(CS_ARCH_RISCV)) { printf(" riscv32 riscv32\n"); printf(" riscv64 riscv64\n"); } printf("\nExtra options:\n"); printf(" -d show detailed information of the instructions\n"); printf(" -s decode in SKIPDATA mode\n"); printf(" -u show immediates as unsigned\n"); printf(" -v show version & Capstone core build info\n\n"); } static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) { printf("\tID: %u (%s)\n", ins->id, cs_insn_name(handle, ins->id)); switch(arch) { case CS_ARCH_X86: print_insn_detail_x86(handle, md, ins); break; case CS_ARCH_ARM: print_insn_detail_arm(handle, ins); break; case CS_ARCH_ARM64: print_insn_detail_arm64(handle, ins); break; case CS_ARCH_MIPS: print_insn_detail_mips(handle, ins); break; case CS_ARCH_PPC: print_insn_detail_ppc(handle, ins); break; case CS_ARCH_SPARC: print_insn_detail_sparc(handle, ins); break; case CS_ARCH_SYSZ: print_insn_detail_sysz(handle, ins); break; case CS_ARCH_XCORE: print_insn_detail_xcore(handle, ins); break; case CS_ARCH_M68K: print_insn_detail_m68k(handle, ins); break; case CS_ARCH_TMS320C64X: print_insn_detail_tms320c64x(handle, ins); break; case CS_ARCH_M680X: print_insn_detail_m680x(handle, ins); break; case CS_ARCH_EVM: print_insn_detail_evm(handle, ins); break; case CS_ARCH_WASM: print_insn_detail_wasm(handle, ins); break; case CS_ARCH_MOS65XX: print_insn_detail_mos65xx(handle, ins); break; case CS_ARCH_BPF: print_insn_detail_bpf(handle, ins); break; case CS_ARCH_RISCV: print_insn_detail_riscv(handle, ins); break; default: break; } if (ins->detail->groups_count) { int j; printf("\tGroups: "); for(j = 0; j < ins->detail->groups_count; j++) { printf("%s ", cs_group_name(handle, ins->detail->groups[j])); } printf("\n"); } printf("\n"); } int main(int argc, char **argv) { int i, c; csh handle; char *mode; uint8_t *assembly; size_t count, size; uint64_t address = 0LL; cs_insn *insn; cs_err err; cs_mode md; cs_arch arch = CS_ARCH_ALL; bool detail_flag = false; bool unsigned_flag = false; bool skipdata = false; int args_left; while ((c = getopt (argc, argv, "sudhv")) != -1) { switch (c) { case 's': skipdata = true; break; case 'u': unsigned_flag = true; break; case 'd': detail_flag = true; break; case 'v': printf("cstool for Capstone Disassembler, v%u.%u.%u\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA); printf("Capstone build: "); if (cs_support(CS_ARCH_X86)) { printf("x86=1 "); } if (cs_support(CS_ARCH_ARM)) { printf("arm=1 "); } if (cs_support(CS_ARCH_ARM64)) { printf("arm64=1 "); } if (cs_support(CS_ARCH_MIPS)) { printf("mips=1 "); } if (cs_support(CS_ARCH_PPC)) { printf("ppc=1 "); } if (cs_support(CS_ARCH_SPARC)) { printf("sparc=1 "); } if (cs_support(CS_ARCH_SYSZ)) { printf("sysz=1 "); } if (cs_support(CS_ARCH_XCORE)) { printf("xcore=1 "); } if (cs_support(CS_ARCH_M68K)) { printf("m68k=1 "); } if (cs_support(CS_ARCH_TMS320C64X)) { printf("tms320c64x=1 "); } if (cs_support(CS_ARCH_M680X)) { printf("m680x=1 "); } if (cs_support(CS_ARCH_EVM)) { printf("evm=1 "); } if (cs_support(CS_ARCH_WASM)) { printf("wasm=1 "); } if (cs_support(CS_ARCH_MOS65XX)) { printf("mos65xx=1 "); } if (cs_support(CS_ARCH_BPF)) { printf("bpf=1 "); } if (cs_support(CS_ARCH_RISCV)) { printf("riscv=1 "); } if (cs_support(CS_SUPPORT_DIET)) { printf("diet=1 "); } if (cs_support(CS_SUPPORT_X86_REDUCE)) { printf("x86_reduce=1 "); } printf("\n"); return 0; case 'h': usage(argv[0]); return 0; default: usage(argv[0]); return -1; } } args_left = argc - optind; if (args_left < 2 || args_left > 3) { usage(argv[0]); return -1; } mode = argv[optind]; assembly = preprocess(argv[optind + 1], &size); if (!assembly) { usage(argv[0]); return -1; } if (args_left == 3) { char *temp, *src = argv[optind + 2]; address = strtoull(src, &temp, 16); if (temp == src || *temp != '\0' || errno == ERANGE) { printf("ERROR: invalid address argument, quit!\n"); return -2; } } for (i = 0; all_archs[i].name; i++) { if (!strcmp(all_archs[i].name, mode)) { arch = all_archs[i].arch; err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle); if (!err) { md = all_archs[i].mode; if (strstr (mode, "att")) { cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); } // turn on SKIPDATA mode if (skipdata) cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON); } break; } } if (arch == CS_ARCH_ALL) { printf("ERROR: Invalid : \"%s\", quit!\n", mode); usage(argv[0]); return -1; } if (err) { printf("ERROR: Failed on cs_open(), quit!\n"); usage(argv[0]); return -1; } if (detail_flag) { cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); } if (unsigned_flag) { cs_option(handle, CS_OPT_UNSIGNED, CS_OPT_ON); } count = cs_disasm(handle, assembly, size, address, 0, &insn); if (count > 0) { size_t i; for (i = 0; i < count; i++) { int j; printf("%2"PRIx64" ", insn[i].address); for (j = 0; j < insn[i].size; j++) { if (j > 0) putchar(' '); printf("%02x", insn[i].bytes[j]); } // X86 and s390 instruction sizes are variable. // align assembly instruction after the opcode if (arch == CS_ARCH_X86) { for (; j < 16; j++) { printf(" "); } } else if (arch == CS_ARCH_SYSZ) { for (; j < 6; j++) { printf(" "); } } printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str); if (detail_flag) { print_details(handle, arch, md, &insn[i]); } } cs_free(insn, count); } else { printf("ERROR: invalid assembly code\n"); return(-4); } cs_close(&handle); free(assembly); return 0; } capstone-sys-0.15.0/capstone/cstool/cstool_arm.c000064400000000000000000000103360072674642500200170ustar 00000000000000#include #include #include void print_insn_detail_arm(csh handle, cs_insn *ins); void print_insn_detail_arm(csh handle, cs_insn *ins) { cs_arm *arm; int i; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; arm = &(ins->detail->arm); if (arm->op_count) printf("\top_count: %u\n", arm->op_count); for (i = 0; i < arm->op_count; i++) { cs_arm_op *op = &(arm->operands[i]); switch((int)op->type) { default: break; case ARM_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case ARM_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); break; case ARM_OP_FP: #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point printf("\t\toperands[%u].type: FP = \n", i); #else printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); #endif break; case ARM_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != ARM_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.index != ARM_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.scale != 1) printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); if (op->mem.lshift != 0) printf("\t\t\toperands[%u].mem.lshift: 0x%x\n", i, op->mem.lshift); break; case ARM_OP_PIMM: printf("\t\toperands[%u].type: P-IMM = %u\n", i, op->imm); break; case ARM_OP_CIMM: printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm); break; case ARM_OP_SETEND: printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le"); break; case ARM_OP_SYSREG: printf("\t\toperands[%u].type: SYSREG = %u\n", i, op->reg); break; } if (op->neon_lane != -1) { printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane); } switch(op->access) { default: break; case CS_AC_READ: printf("\t\toperands[%u].access: READ\n", i); break; case CS_AC_WRITE: printf("\t\toperands[%u].access: WRITE\n", i); break; case CS_AC_READ | CS_AC_WRITE: printf("\t\toperands[%u].access: READ | WRITE\n", i); break; } if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { if (op->shift.type < ARM_SFT_ASR_REG) // shift with constant value printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); else // shift with register printf("\t\t\tShift: %u = %s\n", op->shift.type, cs_reg_name(handle, op->shift.value)); } if (op->vector_index != -1) { printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index); } if (op->subtracted) printf("\t\tSubtracted: True\n"); } if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) printf("\tCode condition: %u\n", arm->cc); if (arm->update_flags) printf("\tUpdate-flags: True\n"); if (arm->writeback) printf("\tWrite-back: True\n"); if (arm->cps_mode) printf("\tCPSI-mode: %u\n", arm->cps_mode); if (arm->cps_flag) printf("\tCPSI-flag: %u\n", arm->cps_flag); if (arm->vector_data) printf("\tVector-data: %u\n", arm->vector_data); if (arm->vector_size) printf("\tVector-size: %u\n", arm->vector_size); if (arm->usermode) printf("\tUser-mode: True\n"); if (arm->mem_barrier) printf("\tMemory-barrier: %u\n", arm->mem_barrier); // Print out all registers accessed by this instruction (either implicit or explicit) if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { printf("\tRegisters read:"); for(i = 0; i < regs_read_count; i++) { printf(" %s", cs_reg_name(handle, regs_read[i])); } printf("\n"); } if (regs_write_count) { printf("\tRegisters modified:"); for(i = 0; i < regs_write_count; i++) { printf(" %s", cs_reg_name(handle, regs_write[i])); } printf("\n"); } } } capstone-sys-0.15.0/capstone/cstool/cstool_arm64.c000064400000000000000000000075260072674642500202000ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013> */ #include #include #include void print_insn_detail_arm64(csh handle, cs_insn *ins); void print_insn_detail_arm64(csh handle, cs_insn *ins) { cs_arm64 *arm64; int i; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; uint8_t access; // detail can be NULL if SKIPDATA option is turned ON if (ins->detail == NULL) return; arm64 = &(ins->detail->arm64); if (arm64->op_count) printf("\top_count: %u\n", arm64->op_count); for (i = 0; i < arm64->op_count; i++) { cs_arm64_op *op = &(arm64->operands[i]); switch(op->type) { default: break; case ARM64_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case ARM64_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); break; case ARM64_OP_FP: #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point printf("\t\toperands[%u].type: FP = \n", i); #else printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); #endif break; case ARM64_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != ARM64_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.index != ARM64_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); break; case ARM64_OP_CIMM: printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm); break; case ARM64_OP_REG_MRS: printf("\t\toperands[%u].type: REG_MRS = 0x%x\n", i, op->reg); break; case ARM64_OP_REG_MSR: printf("\t\toperands[%u].type: REG_MSR = 0x%x\n", i, op->reg); break; case ARM64_OP_PSTATE: printf("\t\toperands[%u].type: PSTATE = 0x%x\n", i, op->pstate); break; case ARM64_OP_SYS: printf("\t\toperands[%u].type: SYS = 0x%x\n", i, op->sys); break; case ARM64_OP_PREFETCH: printf("\t\toperands[%u].type: PREFETCH = 0x%x\n", i, op->prefetch); break; case ARM64_OP_BARRIER: printf("\t\toperands[%u].type: BARRIER = 0x%x\n", i, op->barrier); break; } access = op->access; switch(access) { default: break; case CS_AC_READ: printf("\t\toperands[%u].access: READ\n", i); break; case CS_AC_WRITE: printf("\t\toperands[%u].access: WRITE\n", i); break; case CS_AC_READ | CS_AC_WRITE: printf("\t\toperands[%u].access: READ | WRITE\n", i); break; } if (op->shift.type != ARM64_SFT_INVALID && op->shift.value) printf("\t\t\tShift: type = %u, value = %u\n", op->shift.type, op->shift.value); if (op->ext != ARM64_EXT_INVALID) printf("\t\t\tExt: %u\n", op->ext); if (op->vas != ARM64_VAS_INVALID) printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas); if (op->vector_index != -1) printf("\t\t\tVector Index: %u\n", op->vector_index); } if (arm64->update_flags) printf("\tUpdate-flags: True\n"); if (arm64->writeback) printf("\tWrite-back: True\n"); if (arm64->cc) printf("\tCode-condition: %u\n", arm64->cc); // Print out all registers accessed by this instruction (either implicit or explicit) if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { printf("\tRegisters read:"); for(i = 0; i < regs_read_count; i++) { printf(" %s", cs_reg_name(handle, regs_read[i])); } printf("\n"); } if (regs_write_count) { printf("\tRegisters modified:"); for(i = 0; i < regs_write_count; i++) { printf(" %s", cs_reg_name(handle, regs_write[i])); } printf("\n"); } } } capstone-sys-0.15.0/capstone/cstool/cstool_bpf.c000064400000000000000000000036760072674642500200200ustar 00000000000000#include #include #include static const char * ext_name[] = { [BPF_EXT_LEN] = "#len", }; void print_insn_detail_bpf(csh handle, cs_insn *ins); void print_insn_detail_bpf(csh handle, cs_insn *ins) { unsigned i; cs_bpf *bpf; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; bpf = &(ins->detail->bpf); printf("\tOperand count: %u\n", bpf->op_count); for (i = 0; i < bpf->op_count; i++) { cs_bpf_op *op = &(bpf->operands[i]); printf("\t\toperands[%u].type: ", i); switch (op->type) { case BPF_OP_INVALID: printf("INVALID\n"); break; case BPF_OP_REG: printf("REG = %s\n", cs_reg_name(handle, op->reg)); break; case BPF_OP_IMM: printf("IMM = 0x%" PRIx64 "\n", op->imm); break; case BPF_OP_OFF: printf("OFF = +0x%x\n", op->off); break; case BPF_OP_MEM: printf("MEM\n"); if (op->mem.base != BPF_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); break; case BPF_OP_MMEM: printf("MMEM = M[0x%x]\n", op->mmem); break; case BPF_OP_MSH: printf("MSH = 4*([0x%x]&0xf)\n", op->msh); break; case BPF_OP_EXT: printf("EXT = %s\n", ext_name[op->ext]); break; } } /* print all registers that are involved in this instruction */ if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { printf("\tRegisters read:"); for(i = 0; i < regs_read_count; i++) printf(" %s", cs_reg_name(handle, regs_read[i])); printf("\n"); } if (regs_write_count) { printf("\tRegisters modified:"); for(i = 0; i < regs_write_count; i++) printf(" %s", cs_reg_name(handle, regs_write[i])); printf("\n"); } } } capstone-sys-0.15.0/capstone/cstool/cstool_evm.c000064400000000000000000000007740072674642500200340ustar 00000000000000#include #include #include void print_insn_detail_evm(csh handle, cs_insn *ins); void print_insn_detail_evm(csh handle, cs_insn *ins) { cs_evm *evm; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; evm = &(ins->detail->evm); if (evm->pop) printf("\tPop: %u\n", evm->pop); if (evm->push) printf("\tPush: %u\n", evm->push); if (evm->fee) printf("\tGas fee: %u\n", evm->fee); } capstone-sys-0.15.0/capstone/cstool/cstool_m680x.c000064400000000000000000000067310072674642500201260ustar 00000000000000/* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #include #include void print_insn_detail_m680x(csh handle, cs_insn *insn); static const char *s_access[] = { "UNCHANGED", "READ", "WRITE", "READ | WRITE", }; static void print_read_write_regs(csh handle, cs_detail *detail) { int i; if (detail->regs_read_count > 0) { printf("\treading from regs: "); for (i = 0; i < detail->regs_read_count; ++i) { if (i > 0) printf(", "); printf("%s", cs_reg_name(handle, detail->regs_read[i])); } printf("\n"); } if (detail->regs_write_count > 0) { printf("\twriting to regs: "); for (i = 0; i < detail->regs_write_count; ++i) { if (i > 0) printf(", "); printf("%s", cs_reg_name(handle, detail->regs_write[i])); } printf("\n"); } } void print_insn_detail_m680x(csh handle, cs_insn *insn) { cs_detail *detail = insn->detail; cs_m680x *m680x = NULL; int i; // detail can be NULL on "data" instruction if SKIPDATA option is // turned ON if (detail == NULL) return; m680x = &detail->m680x; if (m680x->op_count) printf("\top_count: %u\n", m680x->op_count); for (i = 0; i < m680x->op_count; i++) { cs_m680x_op *op = &(m680x->operands[i]); const char *comment; switch ((int)op->type) { default: break; case M680X_OP_REGISTER: comment = ""; if ((i == 0 && m680x->flags & M680X_FIRST_OP_IN_MNEM) || (i == 1 && m680x->flags & M680X_SECOND_OP_IN_MNEM)) comment = " (in mnemonic)"; printf("\t\toperands[%u].type: REGISTER = %s%s\n", i, cs_reg_name(handle, op->reg), comment); break; case M680X_OP_CONSTANT: printf("\t\toperands[%u].type: CONSTANT = %u\n", i, op->const_val); break; case M680X_OP_IMMEDIATE: printf("\t\toperands[%u].type: IMMEDIATE = #%d\n", i, op->imm); break; case M680X_OP_DIRECT: printf("\t\toperands[%u].type: DIRECT = 0x%02x\n", i, op->direct_addr); break; case M680X_OP_EXTENDED: printf("\t\toperands[%u].type: EXTENDED %s = 0x%04x\n", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address); break; case M680X_OP_RELATIVE: printf("\t\toperands[%u].type: RELATIVE = 0x%04x\n", i, op->rel.address); break; case M680X_OP_INDEXED: printf("\t\toperands[%u].type: INDEXED%s\n", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : ""); if (op->idx.base_reg != M680X_REG_INVALID) printf("\t\t\tbase register: %s\n", cs_reg_name(handle, op->idx.base_reg)); if (op->idx.offset_reg != M680X_REG_INVALID) printf("\t\t\toffset register: %s\n", cs_reg_name(handle, op->idx.offset_reg)); if ((op->idx.offset_bits != 0) && (op->idx.offset_reg == M680X_REG_INVALID) && !op->idx.inc_dec) { printf("\t\t\toffset: %d\n", op->idx.offset); if (op->idx.base_reg == M680X_REG_PC) printf("\t\t\toffset address: 0x%x\n", op->idx.offset_addr); printf("\t\t\toffset bits: %u\n", op->idx.offset_bits); } if (op->idx.inc_dec) { const char *post_pre = op->idx.flags & M680X_IDX_POST_INC_DEC ? "post" : "pre"; const char *inc_dec = (op->idx.inc_dec > 0) ? "increment" : "decrement"; printf("\t\t\t%s %s: %d\n", post_pre, inc_dec, abs(op->idx.inc_dec)); } break; } if (op->size != 0) printf("\t\t\tsize: %u\n", op->size); if (op->access != CS_AC_INVALID) printf("\t\t\taccess: %s\n", s_access[op->access]); } print_read_write_regs(handle, detail); } capstone-sys-0.15.0/capstone/cstool/cstool_m68k.c000064400000000000000000000064560072674642500200350ustar 00000000000000// // cstool_m68k.c // // // Created by YUHANG TANG on 26/10/16. // // #include #include void print_insn_detail_m68k(csh handle, cs_insn *ins); static const char* s_addressing_modes[] = { "", "Register Direct - Data", "Register Direct - Address", "Register Indirect - Address", "Register Indirect - Address with Postincrement", "Register Indirect - Address with Predecrement", "Register Indirect - Address with Displacement", "Address Register Indirect With Index - 8-bit displacement", "Address Register Indirect With Index - Base displacement", "Memory indirect - Postindex", "Memory indirect - Preindex", "Program Counter Indirect - with Displacement", "Program Counter Indirect with Index - with 8-Bit Displacement", "Program Counter Indirect with Index - with Base Displacement", "Program Counter Memory Indirect - Postindexed", "Program Counter Memory Indirect - Preindexed", "Absolute Data Addressing - Short", "Absolute Data Addressing - Long", "Immediate value", }; static void print_read_write_regs(cs_detail* detail, csh handle) { int i; for (i = 0; i < detail->regs_read_count; ++i) { uint16_t reg_id = detail->regs_read[i]; const char* reg_name = cs_reg_name(handle, reg_id); printf("\treading from reg: %s\n", reg_name); } for (i = 0; i < detail->regs_write_count; ++i) { uint16_t reg_id = detail->regs_write[i]; const char* reg_name = cs_reg_name(handle, reg_id); printf("\twriting to reg: %s\n", reg_name); } } void print_insn_detail_m68k(csh handle, cs_insn *ins) { cs_m68k* m68k; cs_detail* detail; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; detail = ins->detail; m68k = &detail->m68k; if (m68k->op_count) printf("\top_count: %u\n", m68k->op_count); print_read_write_regs(detail, handle); printf("\tgroups_count: %u\n", detail->groups_count); for (i = 0; i < m68k->op_count; i++) { cs_m68k_op* op = &(m68k->operands[i]); switch((int)op->type) { default: break; case M68K_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case M68K_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%x\n", i, (int)op->imm); break; case M68K_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base_reg != M68K_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base_reg)); if (op->mem.index_reg != M68K_REG_INVALID) { printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index_reg)); printf("\t\t\toperands[%u].mem.index: size = %c\n", i, op->mem.index_size ? 'l' : 'w'); } if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); if (op->mem.scale != 0) printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale); printf("\t\taddress mode: %s\n", s_addressing_modes[op->address_mode]); break; case M68K_OP_FP_SINGLE: printf("\t\toperands[%u].type: FP_SINGLE\n", i); printf("\t\t\toperands[%u].simm: %f\n", i, op->simm); break; case M68K_OP_FP_DOUBLE: printf("\t\toperands[%u].type: FP_DOUBLE\n", i); printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm); break; } } } capstone-sys-0.15.0/capstone/cstool/cstool_mips.c000064400000000000000000000022550072674642500202110ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013> */ #include #include #include void print_insn_detail_mips(csh handle, cs_insn *ins); void print_insn_detail_mips(csh handle, cs_insn *ins) { int i; cs_mips *mips; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; mips = &(ins->detail->mips); if (mips->op_count) printf("\top_count: %u\n", mips->op_count); for (i = 0; i < mips->op_count; i++) { cs_mips_op *op = &(mips->operands[i]); switch((int)op->type) { default: break; case MIPS_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case MIPS_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); break; case MIPS_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != MIPS_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); break; } } } capstone-sys-0.15.0/capstone/cstool/cstool_mos65xx.c000064400000000000000000000052160072674642500205720ustar 00000000000000#include #include #include void print_insn_detail_mos65xx(csh handle, cs_insn *ins); static const char *get_am_name(mos65xx_address_mode mode) { switch(mode) { default: case MOS65XX_AM_NONE: return "No address mode"; case MOS65XX_AM_IMP: return "implied"; case MOS65XX_AM_ACC: return "accumulator"; case MOS65XX_AM_IMM: return "immediate value"; case MOS65XX_AM_REL: return "relative"; case MOS65XX_AM_INT: return "interrupt signature"; case MOS65XX_AM_BLOCK: return "block move"; case MOS65XX_AM_ZP: return "zero page"; case MOS65XX_AM_ZP_X: return "zero page indexed with x"; case MOS65XX_AM_ZP_Y: return "zero page indexed with y"; case MOS65XX_AM_ZP_REL: return "relative bit branch"; case MOS65XX_AM_ZP_IND: return "zero page indirect"; case MOS65XX_AM_ZP_X_IND: return "zero page indexed with x indirect"; case MOS65XX_AM_ZP_IND_Y: return "zero page indirect indexed with y"; case MOS65XX_AM_ZP_IND_LONG: return "zero page indirect long"; case MOS65XX_AM_ZP_IND_LONG_Y: return "zero page indirect long indexed with y"; case MOS65XX_AM_ABS: return "absolute"; case MOS65XX_AM_ABS_X: return "absolute indexed with x"; case MOS65XX_AM_ABS_Y: return "absolute indexed with y"; case MOS65XX_AM_ABS_IND: return "absolute indirect"; case MOS65XX_AM_ABS_X_IND: return "absolute indexed with x indirect"; case MOS65XX_AM_ABS_IND_LONG: return "absolute indirect long"; case MOS65XX_AM_ABS_LONG: return "absolute long"; case MOS65XX_AM_ABS_LONG_X: return "absolute long indexed with x"; case MOS65XX_AM_SR: return "stack relative"; case MOS65XX_AM_SR_IND_Y: return "stack relative indirect indexed with y"; } } void print_insn_detail_mos65xx(csh handle, cs_insn *ins) { int i; cs_mos65xx *mos65xx; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; mos65xx = &(ins->detail->mos65xx); printf("\taddress mode: %s\n", get_am_name(mos65xx->am)); printf("\tmodifies flags: %s\n", mos65xx->modifies_flags ? "true": "false"); if (mos65xx->op_count) printf("\top_count: %u\n", mos65xx->op_count); for (i = 0; i < mos65xx->op_count; i++) { cs_mos65xx_op *op = &(mos65xx->operands[i]); switch((int)op->type) { default: break; case MOS65XX_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case MOS65XX_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); break; case MOS65XX_OP_MEM: printf("\t\toperands[%u].type: MEM = 0x%x\n", i, op->mem); break; } } } capstone-sys-0.15.0/capstone/cstool/cstool_ppc.c000064400000000000000000000041060072674642500200200ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013> */ #include #include void print_insn_detail_ppc(csh handle, cs_insn *ins); static const char* get_bc_name(int bc) { switch(bc) { default: case PPC_BC_INVALID: return ("invalid"); case PPC_BC_LT: return ("lt"); case PPC_BC_LE: return ("le"); case PPC_BC_EQ: return ("eq"); case PPC_BC_GE: return ("ge"); case PPC_BC_GT: return ("gt"); case PPC_BC_NE: return ("ne"); case PPC_BC_UN: return ("un"); case PPC_BC_NU: return ("nu"); case PPC_BC_SO: return ("so"); case PPC_BC_NS: return ("ns"); } } void print_insn_detail_ppc(csh handle, cs_insn *ins) { cs_ppc *ppc; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; ppc = &(ins->detail->ppc); if (ppc->op_count) printf("\top_count: %u\n", ppc->op_count); for (i = 0; i < ppc->op_count; i++) { cs_ppc_op *op = &(ppc->operands[i]); switch((int)op->type) { default: break; case PPC_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case PPC_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%"PRIx64"\n", i, op->imm); break; case PPC_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != PPC_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); break; case PPC_OP_CRX: printf("\t\toperands[%u].type: CRX\n", i); printf("\t\t\toperands[%u].crx.scale: %d\n", i, op->crx.scale); printf("\t\t\toperands[%u].crx.reg: %s\n", i, cs_reg_name(handle, op->crx.reg)); printf("\t\t\toperands[%u].crx.cond: %s\n", i, get_bc_name(op->crx.cond)); break; } } if (ppc->bc != 0) printf("\tBranch code: %u\n", ppc->bc); if (ppc->bh != 0) printf("\tBranch hint: %u\n", ppc->bh); if (ppc->update_cr0) printf("\tUpdate-CR0: True\n"); } capstone-sys-0.15.0/capstone/cstool/cstool_riscv.c000064400000000000000000000022640072674642500203670ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013-2014 */ #include #include void print_insn_detail_riscv(csh handle, cs_insn *ins); void print_insn_detail_riscv(csh handle, cs_insn *ins) { cs_riscv *riscv; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; riscv = &(ins->detail->riscv); if (riscv->op_count) printf("\top_count: %u\n", riscv->op_count); for (i = 0; i < riscv->op_count; i++) { cs_riscv_op *op = &(riscv->operands[i]); switch((int)op->type) { default: break; case RISCV_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case RISCV_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%lx\n", i, (long)op->imm); break; case RISCV_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != RISCV_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%lx\n", i, (long)op->mem.disp); break; } } printf("\n"); } capstone-sys-0.15.0/capstone/cstool/cstool_sparc.c000064400000000000000000000026710072674642500203530ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013-2014 */ #include #include void print_insn_detail_sparc(csh handle, cs_insn *ins); void print_insn_detail_sparc(csh handle, cs_insn *ins) { cs_sparc *sparc; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; sparc = &(ins->detail->sparc); if (sparc->op_count) printf("\top_count: %u\n", sparc->op_count); for (i = 0; i < sparc->op_count; i++) { cs_sparc_op *op = &(sparc->operands[i]); switch((int)op->type) { default: break; case SPARC_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case SPARC_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); break; case SPARC_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != X86_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.index != X86_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); break; } } if (sparc->cc != 0) printf("\tCode condition: %u\n", sparc->cc); if (sparc->hint != 0) printf("\tHint code: %u\n", sparc->hint); } capstone-sys-0.15.0/capstone/cstool/cstool_systemz.c000064400000000000000000000030770072674642500207620ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013-2014 */ #include #include void print_insn_detail_sysz(csh handle, cs_insn *ins); void print_insn_detail_sysz(csh handle, cs_insn *ins) { cs_sysz *sysz; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; sysz = &(ins->detail->sysz); if (sysz->op_count) printf("\top_count: %u\n", sysz->op_count); for (i = 0; i < sysz->op_count; i++) { cs_sysz_op *op = &(sysz->operands[i]); switch((int)op->type) { default: break; case SYSZ_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case SYSZ_OP_ACREG: printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg); break; case SYSZ_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); break; case SYSZ_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != SYSZ_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.index != SYSZ_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.length != 0) printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); break; } } if (sysz->cc != 0) printf("\tCode condition: %u\n", sysz->cc); } capstone-sys-0.15.0/capstone/cstool/cstool_tms320c64x.c000064400000000000000000000067360072674642500210060ustar 00000000000000/* Capstone Disassembler Engine */ /* By Fotis Loukos , 2017 */ #include #include void print_insn_detail_tms320c64x(csh handle, cs_insn *ins); void print_insn_detail_tms320c64x(csh handle, cs_insn *ins) { cs_tms320c64x *tms320c64x; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; tms320c64x = &(ins->detail->tms320c64x); if (tms320c64x->op_count) printf("\top_count: %u\n", tms320c64x->op_count); for (i = 0; i < tms320c64x->op_count; i++) { cs_tms320c64x_op *op = &(tms320c64x->operands[i]); switch((int)op->type) { default: break; case TMS320C64X_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case TMS320C64X_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); break; case TMS320C64X_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != TMS320C64X_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); printf("\t\t\toperands[%u].mem.disptype: ", i); if(op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { printf("Invalid\n"); printf("\t\t\toperands[%u].mem.disp: %u\n", i, op->mem.disp); } if(op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { printf("Constant\n"); printf("\t\t\toperands[%u].mem.disp: %u\n", i, op->mem.disp); } if(op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { printf("Register\n"); printf("\t\t\toperands[%u].mem.disp: %s\n", i, cs_reg_name(handle, op->mem.disp)); } printf("\t\t\toperands[%u].mem.unit: %u\n", i, op->mem.unit); printf("\t\t\toperands[%u].mem.direction: ", i); if(op->mem.direction == TMS320C64X_MEM_DIR_INVALID) printf("Invalid\n"); if(op->mem.direction == TMS320C64X_MEM_DIR_FW) printf("Forward\n"); if(op->mem.direction == TMS320C64X_MEM_DIR_BW) printf("Backward\n"); printf("\t\t\toperands[%u].mem.modify: ", i); if(op->mem.modify == TMS320C64X_MEM_MOD_INVALID) printf("Invalid\n"); if(op->mem.modify == TMS320C64X_MEM_MOD_NO) printf("No\n"); if(op->mem.modify == TMS320C64X_MEM_MOD_PRE) printf("Pre\n"); if(op->mem.modify == TMS320C64X_MEM_MOD_POST) printf("Post\n"); printf("\t\t\toperands[%u].mem.scaled: %u\n", i, op->mem.scaled); break; case TMS320C64X_OP_REGPAIR: printf("\t\toperands[%u].type: REGPAIR = %s:%s\n", i, cs_reg_name(handle, op->reg + 1), cs_reg_name(handle, op->reg)); break; } } printf("\tFunctional unit: "); switch(tms320c64x->funit.unit) { case TMS320C64X_FUNIT_D: printf("D%u\n", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_L: printf("L%u\n", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_M: printf("M%u\n", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_S: printf("S%u\n", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_NO: printf("No Functional Unit\n"); break; default: printf("Unknown (Unit %u, Side %u)\n", tms320c64x->funit.unit, tms320c64x->funit.side); break; } if(tms320c64x->funit.crosspath == 1) printf("\tCrosspath: 1\n"); if(tms320c64x->condition.reg != TMS320C64X_REG_INVALID) printf("\tCondition: [%c%s]\n", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(handle, tms320c64x->condition.reg)); printf("\tParallel: %s\n", (tms320c64x->parallel == 1) ? "true" : "false"); printf("\n"); } capstone-sys-0.15.0/capstone/cstool/cstool_wasm.c000064400000000000000000000026730072674642500202140ustar 00000000000000#include #include #include void print_insn_detail_wasm(csh handle, cs_insn *ins); void print_insn_detail_wasm(csh handle, cs_insn *ins) { cs_wasm *wasm; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; wasm = &(ins->detail->wasm); if (wasm->op_count > 0) { unsigned int i; printf("\tOperand count: %d\n", wasm->op_count); for (i = 0; i < wasm->op_count; i++) { switch (wasm->operands[i].type) { default: break; case WASM_OP_INT7: printf("\t\tOperand[%u] type: int7\n", i); printf("\t\tOperand[%u] value: %d\n", i, wasm->operands[i].int7); break; case WASM_OP_UINT32: printf("\t\tOperand[%u] type: uint32\n", i); printf("\t\tOperand[%u] value: 0x%x\n", i, wasm->operands[i].uint32); break; case WASM_OP_UINT64: printf("\t\tOperand[%u] type: uint64\n", i); printf("\t\tOperand[%u] value: 0x%" PRIx64 "\n", i, wasm->operands[i].uint64); break; case WASM_OP_VARUINT32: printf("\t\tOperand[%u] type: varuint32\n", i); printf("\t\tOperand[%u] value: 0x%x\n", i, wasm->operands[i].varuint32); break; case WASM_OP_VARUINT64: printf("\t\tOperand[%u] type: varuint64\n", i); printf("\t\tOperand[%u] value: 0x%" PRIx64 "\n", i, wasm->operands[i].varuint64); break; } printf("\t\tOperand[%u] size: %u\n", i, wasm->operands[i].size); } } } capstone-sys-0.15.0/capstone/cstool/cstool_x86.c000064400000000000000000000215130072674642500176640ustar 00000000000000/* By Nguyen Anh Quynh , 2013> */ #include #include #include void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins); void print_string_hex(const char *comment, unsigned char *str, size_t len); static const char *get_eflag_name(uint64_t flag) { switch(flag) { default: return NULL; case X86_EFLAGS_UNDEFINED_OF: return "UNDEF_OF"; case X86_EFLAGS_UNDEFINED_SF: return "UNDEF_SF"; case X86_EFLAGS_UNDEFINED_ZF: return "UNDEF_ZF"; case X86_EFLAGS_MODIFY_AF: return "MOD_AF"; case X86_EFLAGS_UNDEFINED_PF: return "UNDEF_PF"; case X86_EFLAGS_MODIFY_CF: return "MOD_CF"; case X86_EFLAGS_MODIFY_SF: return "MOD_SF"; case X86_EFLAGS_MODIFY_ZF: return "MOD_ZF"; case X86_EFLAGS_UNDEFINED_AF: return "UNDEF_AF"; case X86_EFLAGS_MODIFY_PF: return "MOD_PF"; case X86_EFLAGS_UNDEFINED_CF: return "UNDEF_CF"; case X86_EFLAGS_MODIFY_OF: return "MOD_OF"; case X86_EFLAGS_RESET_OF: return "RESET_OF"; case X86_EFLAGS_RESET_CF: return "RESET_CF"; case X86_EFLAGS_RESET_DF: return "RESET_DF"; case X86_EFLAGS_RESET_IF: return "RESET_IF"; case X86_EFLAGS_RESET_ZF: return "RESET_ZF"; case X86_EFLAGS_TEST_OF: return "TEST_OF"; case X86_EFLAGS_TEST_SF: return "TEST_SF"; case X86_EFLAGS_TEST_ZF: return "TEST_ZF"; case X86_EFLAGS_TEST_PF: return "TEST_PF"; case X86_EFLAGS_TEST_CF: return "TEST_CF"; case X86_EFLAGS_RESET_SF: return "RESET_SF"; case X86_EFLAGS_RESET_AF: return "RESET_AF"; case X86_EFLAGS_RESET_TF: return "RESET_TF"; case X86_EFLAGS_RESET_NT: return "RESET_NT"; case X86_EFLAGS_PRIOR_OF: return "PRIOR_OF"; case X86_EFLAGS_PRIOR_SF: return "PRIOR_SF"; case X86_EFLAGS_PRIOR_ZF: return "PRIOR_ZF"; case X86_EFLAGS_PRIOR_AF: return "PRIOR_AF"; case X86_EFLAGS_PRIOR_PF: return "PRIOR_PF"; case X86_EFLAGS_PRIOR_CF: return "PRIOR_CF"; case X86_EFLAGS_PRIOR_TF: return "PRIOR_TF"; case X86_EFLAGS_PRIOR_IF: return "PRIOR_IF"; case X86_EFLAGS_PRIOR_DF: return "PRIOR_DF"; case X86_EFLAGS_TEST_NT: return "TEST_NT"; case X86_EFLAGS_TEST_DF: return "TEST_DF"; case X86_EFLAGS_RESET_PF: return "RESET_PF"; case X86_EFLAGS_PRIOR_NT: return "PRIOR_NT"; case X86_EFLAGS_MODIFY_TF: return "MOD_TF"; case X86_EFLAGS_MODIFY_IF: return "MOD_IF"; case X86_EFLAGS_MODIFY_DF: return "MOD_DF"; case X86_EFLAGS_MODIFY_NT: return "MOD_NT"; case X86_EFLAGS_MODIFY_RF: return "MOD_RF"; case X86_EFLAGS_SET_CF: return "SET_CF"; case X86_EFLAGS_SET_DF: return "SET_DF"; case X86_EFLAGS_SET_IF: return "SET_IF"; case X86_EFLAGS_SET_OF: return "SET_OF"; case X86_EFLAGS_SET_SF: return "SET_SF"; case X86_EFLAGS_SET_ZF: return "SET_ZF"; case X86_EFLAGS_SET_AF: return "SET_AF"; case X86_EFLAGS_SET_PF: return "SET_PF"; case X86_EFLAGS_TEST_AF: return "TEST_AF"; case X86_EFLAGS_TEST_TF: return "TEST_TF"; case X86_EFLAGS_TEST_RF: return "TEST_RF"; case X86_EFLAGS_RESET_0F: return "RESET_0F"; case X86_EFLAGS_RESET_AC: return "RESET_AC"; } } static const char *get_fpu_flag_name(uint64_t flag) { switch (flag) { default: return NULL; case X86_FPU_FLAGS_MODIFY_C0: return "MOD_C0"; case X86_FPU_FLAGS_MODIFY_C1: return "MOD_C1"; case X86_FPU_FLAGS_MODIFY_C2: return "MOD_C2"; case X86_FPU_FLAGS_MODIFY_C3: return "MOD_C3"; case X86_FPU_FLAGS_RESET_C0: return "RESET_C0"; case X86_FPU_FLAGS_RESET_C1: return "RESET_C1"; case X86_FPU_FLAGS_RESET_C2: return "RESET_C2"; case X86_FPU_FLAGS_RESET_C3: return "RESET_C3"; case X86_FPU_FLAGS_SET_C0: return "SET_C0"; case X86_FPU_FLAGS_SET_C1: return "SET_C1"; case X86_FPU_FLAGS_SET_C2: return "SET_C2"; case X86_FPU_FLAGS_SET_C3: return "SET_C3"; case X86_FPU_FLAGS_UNDEFINED_C0: return "UNDEF_C0"; case X86_FPU_FLAGS_UNDEFINED_C1: return "UNDEF_C1"; case X86_FPU_FLAGS_UNDEFINED_C2: return "UNDEF_C2"; case X86_FPU_FLAGS_UNDEFINED_C3: return "UNDEF_C3"; case X86_FPU_FLAGS_TEST_C0: return "TEST_C0"; case X86_FPU_FLAGS_TEST_C1: return "TEST_C1"; case X86_FPU_FLAGS_TEST_C2: return "TEST_C2"; case X86_FPU_FLAGS_TEST_C3: return "TEST_C3"; } } void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins) { int count, i; cs_x86 *x86; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; x86 = &(ins->detail->x86); print_string_hex("\tPrefix:", x86->prefix, 4); print_string_hex("\tOpcode:", x86->opcode, 4); printf("\trex: 0x%x\n", x86->rex); printf("\taddr_size: %u\n", x86->addr_size); printf("\tmodrm: 0x%x\n", x86->modrm); printf("\tdisp: 0x%" PRIx64 "\n", x86->disp); // SIB is not available in 16-bit mode if ((mode & CS_MODE_16) == 0) { printf("\tsib: 0x%x\n", x86->sib); if (x86->sib_base != X86_REG_INVALID) printf("\t\tsib_base: %s\n", cs_reg_name(ud, x86->sib_base)); if (x86->sib_index != X86_REG_INVALID) printf("\t\tsib_index: %s\n", cs_reg_name(ud, x86->sib_index)); if (x86->sib_scale != 0) printf("\t\tsib_scale: %d\n", x86->sib_scale); } // XOP code condition if (x86->xop_cc != X86_XOP_CC_INVALID) { printf("\txop_cc: %u\n", x86->xop_cc); } // SSE code condition if (x86->sse_cc != X86_SSE_CC_INVALID) { printf("\tsse_cc: %u\n", x86->sse_cc); } // AVX code condition if (x86->avx_cc != X86_AVX_CC_INVALID) { printf("\tavx_cc: %u\n", x86->avx_cc); } // AVX Suppress All Exception if (x86->avx_sae) { printf("\tavx_sae: %u\n", x86->avx_sae); } // AVX Rounding Mode if (x86->avx_rm != X86_AVX_RM_INVALID) { printf("\tavx_rm: %u\n", x86->avx_rm); } // Print out all immediate operands count = cs_op_count(ud, ins, X86_OP_IMM); if (count > 0) { printf("\timm_count: %u\n", count); for (i = 1; i < count + 1; i++) { int index = cs_op_index(ud, ins, X86_OP_IMM, i); printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm); } } if (x86->op_count) printf("\top_count: %u\n", x86->op_count); // Print out all operands for (i = 0; i < x86->op_count; i++) { cs_x86_op *op = &(x86->operands[i]); switch((int)op->type) { case X86_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(ud, op->reg)); break; case X86_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm); break; case X86_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.segment != X86_REG_INVALID) printf("\t\t\toperands[%u].mem.segment: REG = %s\n", i, cs_reg_name(ud, op->mem.segment)); if (op->mem.base != X86_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(ud, op->mem.base)); if (op->mem.index != X86_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(ud, op->mem.index)); if (op->mem.scale != 1) printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp); break; default: break; } // AVX broadcast type if (op->avx_bcast != X86_AVX_BCAST_INVALID) printf("\t\toperands[%u].avx_bcast: %u\n", i, op->avx_bcast); // AVX zero opmask {z} if (op->avx_zero_opmask != false) printf("\t\toperands[%u].avx_zero_opmask: TRUE\n", i); printf("\t\toperands[%u].size: %u\n", i, op->size); switch(op->access) { default: break; case CS_AC_READ: printf("\t\toperands[%u].access: READ\n", i); break; case CS_AC_WRITE: printf("\t\toperands[%u].access: WRITE\n", i); break; case CS_AC_READ | CS_AC_WRITE: printf("\t\toperands[%u].access: READ | WRITE\n", i); break; } } // Print out all registers accessed by this instruction (either implicit or explicit) if (!cs_regs_access(ud, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { printf("\tRegisters read:"); for(i = 0; i < regs_read_count; i++) { printf(" %s", cs_reg_name(ud, regs_read[i])); } printf("\n"); } if (regs_write_count) { printf("\tRegisters modified:"); for(i = 0; i < regs_write_count; i++) { printf(" %s", cs_reg_name(ud, regs_write[i])); } printf("\n"); } } if (x86->eflags || x86->fpu_flags) { for(i = 0; i < ins->detail->groups_count; i++) { if (ins->detail->groups[i] == X86_GRP_FPU) { printf("\tFPU_FLAGS:"); for(i = 0; i <= 63; i++) if (x86->fpu_flags & ((uint64_t)1 << i)) { printf(" %s", get_fpu_flag_name((uint64_t)1 << i)); } printf("\n"); break; } } if (i == ins->detail->groups_count) { printf("\tEFLAGS:"); for(i = 0; i <= 63; i++) if (x86->eflags & ((uint64_t)1 << i)) { printf(" %s", get_eflag_name((uint64_t)1 << i)); } printf("\n"); } } } capstone-sys-0.15.0/capstone/cstool/cstool_xcore.c000064400000000000000000000026160072674642500203620ustar 00000000000000/* Capstone Disassembler Engine */ /* By Nguyen Anh Quynh , 2013-2014 */ #include #include void print_insn_detail_xcore(csh handle, cs_insn *ins); void print_insn_detail_xcore(csh handle, cs_insn *ins) { cs_xcore *xcore; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; xcore = &(ins->detail->xcore); if (xcore->op_count) printf("\top_count: %u\n", xcore->op_count); for (i = 0; i < xcore->op_count; i++) { cs_xcore_op *op = &(xcore->operands[i]); switch((int)op->type) { default: break; case XCORE_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case XCORE_OP_IMM: printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); break; case XCORE_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != XCORE_REG_INVALID) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.index != XCORE_REG_INVALID) printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.disp != 0) printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); if (op->mem.direct != 1) printf("\t\t\toperands[%u].mem.direct: -1\n", i); break; } } printf("\n"); } capstone-sys-0.15.0/capstone/cstool/getopt.c000064400000000000000000000036570072674642500171670ustar 00000000000000#include #include #include "getopt.h" int opterr = 1, /* if error message should be printed */ optind = 1, /* index into parent argv vector */ optopt, /* character checked for validity */ optreset; /* reset getopt */ const char *optarg; /* argument associated with option */ #define BADCH (int)'?' #define BADARG (int)':' #define EMSG "" /* * getopt -- * Parse argc/argv argument vector. */ int getopt (int nargc, char * const nargv[], const char *ostr) { static const char *place = EMSG; /* option letter processing */ const char *oli; /* option letter list index */ if (optreset || !*place) { /* update scanning pointer */ optreset = 0; if (optind >= nargc || *(place = nargv[optind]) != '-') { place = EMSG; return (-1); } if (place[1] && *++place == '-') { /* found "--" */ ++optind; place = EMSG; return (-1); } } /* option letter okay? */ if ((optopt = (int)*place++) == (int)':' || !(oli = strchr (ostr, optopt))) { /* * if the user didn't specify '-' as an option, * assume it means -1. */ if (optopt == (int)'-') return (-1); if (!*place) ++optind; if (opterr && *ostr != ':') (void)printf ("illegal option -- %c\n", optopt); return (BADCH); } if (*++oli != ':') { /* don't need argument */ optarg = NULL; if (!*place) ++optind; } else { /* need an argument */ if (*place) /* no white space */ optarg = place; else if (nargc <= ++optind) { /* no arg */ place = EMSG; if (*ostr == ':') return (BADARG); if (opterr) (void)printf ("option requires an argument -- %c\n", optopt); return (BADCH); } else /* white space */ optarg = nargv[optind]; place = EMSG; ++optind; } return optopt; /* dump back option letter */ } capstone-sys-0.15.0/capstone/cstool/getopt.h000064400000000000000000000005670072674642500171710ustar 00000000000000#ifndef CSTOOL_GETOPT_H #define CSTOOL_GETOPT_H // global extern int opterr, /* if error message should be printed */ optind, /* index into parent argv vector */ optopt, /* character checked for validity */ optreset; /* reset getopt */ extern const char *optarg; /* argument associated with option */ int getopt (int nargc, char *const nargv[], const char *ostr); #endif capstone-sys-0.15.0/capstone/functions.mk000064400000000000000000000004060072674642500165440ustar 00000000000000# Capstone Disassembly Engine # Common functions used by Makefile & tests/Makefile define compile @$(CC) -MM -MP -MT $@ -MT $(@:.o=.d) $(CFLAGS) $< > $(@:.o=.d) ${CC} ${CFLAGS} -c $< -o $@ endef define log @printf " %-7s %s\n" "$(1)" "$(2)" endef capstone-sys-0.15.0/capstone/include/capstone/arm.h000064400000000000000000000465130072674642500204030ustar 00000000000000#ifndef CAPSTONE_ARM_H #define CAPSTONE_ARM_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// ARM shift type typedef enum arm_shifter { ARM_SFT_INVALID = 0, ARM_SFT_ASR, ///< shift with immediate const ARM_SFT_LSL, ///< shift with immediate const ARM_SFT_LSR, ///< shift with immediate const ARM_SFT_ROR, ///< shift with immediate const ARM_SFT_RRX, ///< shift with immediate const ARM_SFT_ASR_REG, ///< shift with register ARM_SFT_LSL_REG, ///< shift with register ARM_SFT_LSR_REG, ///< shift with register ARM_SFT_ROR_REG, ///< shift with register ARM_SFT_RRX_REG, ///< shift with register } arm_shifter; /// ARM condition code typedef enum arm_cc { ARM_CC_INVALID = 0, ARM_CC_EQ, ///< Equal Equal ARM_CC_NE, ///< Not equal Not equal, or unordered ARM_CC_HS, ///< Carry set >, ==, or unordered ARM_CC_LO, ///< Carry clear Less than ARM_CC_MI, ///< Minus, negative Less than ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered ARM_CC_VS, ///< Overflow Unordered ARM_CC_VC, ///< No overflow Not unordered ARM_CC_HI, ///< Unsigned higher Greater than, or unordered ARM_CC_LS, ///< Unsigned lower or same Less than or equal ARM_CC_GE, ///< Greater than or equal Greater than or equal ARM_CC_LT, ///< Less than Less than, or unordered ARM_CC_GT, ///< Greater than Greater than ARM_CC_LE, ///< Less than or equal <, ==, or unordered ARM_CC_AL ///< Always (unconditional) Always (unconditional) } arm_cc; typedef enum arm_sysreg { /// Special registers for MSR ARM_SYSREG_INVALID = 0, // SPSR* registers can be OR combined ARM_SYSREG_SPSR_C = 1, ARM_SYSREG_SPSR_X = 2, ARM_SYSREG_SPSR_S = 4, ARM_SYSREG_SPSR_F = 8, // CPSR* registers can be OR combined ARM_SYSREG_CPSR_C = 16, ARM_SYSREG_CPSR_X = 32, ARM_SYSREG_CPSR_S = 64, ARM_SYSREG_CPSR_F = 128, // independent registers ARM_SYSREG_APSR = 256, ARM_SYSREG_APSR_G, ARM_SYSREG_APSR_NZCVQ, ARM_SYSREG_APSR_NZCVQG, ARM_SYSREG_IAPSR, ARM_SYSREG_IAPSR_G, ARM_SYSREG_IAPSR_NZCVQG, ARM_SYSREG_IAPSR_NZCVQ, ARM_SYSREG_EAPSR, ARM_SYSREG_EAPSR_G, ARM_SYSREG_EAPSR_NZCVQG, ARM_SYSREG_EAPSR_NZCVQ, ARM_SYSREG_XPSR, ARM_SYSREG_XPSR_G, ARM_SYSREG_XPSR_NZCVQG, ARM_SYSREG_XPSR_NZCVQ, ARM_SYSREG_IPSR, ARM_SYSREG_EPSR, ARM_SYSREG_IEPSR, ARM_SYSREG_MSP, ARM_SYSREG_PSP, ARM_SYSREG_PRIMASK, ARM_SYSREG_BASEPRI, ARM_SYSREG_BASEPRI_MAX, ARM_SYSREG_FAULTMASK, ARM_SYSREG_CONTROL, ARM_SYSREG_MSPLIM, ARM_SYSREG_PSPLIM, ARM_SYSREG_MSP_NS, ARM_SYSREG_PSP_NS, ARM_SYSREG_MSPLIM_NS, ARM_SYSREG_PSPLIM_NS, ARM_SYSREG_PRIMASK_NS, ARM_SYSREG_BASEPRI_NS, ARM_SYSREG_FAULTMASK_NS, ARM_SYSREG_CONTROL_NS, ARM_SYSREG_SP_NS, // Banked Registers ARM_SYSREG_R8_USR, ARM_SYSREG_R9_USR, ARM_SYSREG_R10_USR, ARM_SYSREG_R11_USR, ARM_SYSREG_R12_USR, ARM_SYSREG_SP_USR, ARM_SYSREG_LR_USR, ARM_SYSREG_R8_FIQ, ARM_SYSREG_R9_FIQ, ARM_SYSREG_R10_FIQ, ARM_SYSREG_R11_FIQ, ARM_SYSREG_R12_FIQ, ARM_SYSREG_SP_FIQ, ARM_SYSREG_LR_FIQ, ARM_SYSREG_LR_IRQ, ARM_SYSREG_SP_IRQ, ARM_SYSREG_LR_SVC, ARM_SYSREG_SP_SVC, ARM_SYSREG_LR_ABT, ARM_SYSREG_SP_ABT, ARM_SYSREG_LR_UND, ARM_SYSREG_SP_UND, ARM_SYSREG_LR_MON, ARM_SYSREG_SP_MON, ARM_SYSREG_ELR_HYP, ARM_SYSREG_SP_HYP, ARM_SYSREG_SPSR_FIQ, ARM_SYSREG_SPSR_IRQ, ARM_SYSREG_SPSR_SVC, ARM_SYSREG_SPSR_ABT, ARM_SYSREG_SPSR_UND, ARM_SYSREG_SPSR_MON, ARM_SYSREG_SPSR_HYP, } arm_sysreg; /// The memory barrier constants map directly to the 4-bit encoding of /// the option field for Memory Barrier operations. typedef enum arm_mem_barrier { ARM_MB_INVALID = 0, ARM_MB_RESERVED_0, ARM_MB_OSHLD, ARM_MB_OSHST, ARM_MB_OSH, ARM_MB_RESERVED_4, ARM_MB_NSHLD, ARM_MB_NSHST, ARM_MB_NSH, ARM_MB_RESERVED_8, ARM_MB_ISHLD, ARM_MB_ISHST, ARM_MB_ISH, ARM_MB_RESERVED_12, ARM_MB_LD, ARM_MB_ST, ARM_MB_SY, } arm_mem_barrier; /// Operand type for instruction's operands typedef enum arm_op_type { ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). ARM_OP_REG, ///< = CS_OP_REG (Register operand). ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand). ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand). ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand). ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers) ARM_OP_PIMM, ///< P-Immediate (coprocessor registers) ARM_OP_SETEND, ///< operand for SETEND instruction ARM_OP_SYSREG, ///< MSR/MRS special register operand } arm_op_type; /// Operand type for SETEND instruction typedef enum arm_setend_type { ARM_SETEND_INVALID = 0, ///< Uninitialized. ARM_SETEND_BE, ///< BE operand. ARM_SETEND_LE, ///< LE operand } arm_setend_type; typedef enum arm_cpsmode_type { ARM_CPSMODE_INVALID = 0, ARM_CPSMODE_IE = 2, ARM_CPSMODE_ID = 3 } arm_cpsmode_type; /// Operand type for SETEND instruction typedef enum arm_cpsflag_type { ARM_CPSFLAG_INVALID = 0, ARM_CPSFLAG_F = 1, ARM_CPSFLAG_I = 2, ARM_CPSFLAG_A = 4, ARM_CPSFLAG_NONE = 16, ///< no flag } arm_cpsflag_type; /// Data type for elements of vector instructions. typedef enum arm_vectordata_type { ARM_VECTORDATA_INVALID = 0, // Integer type ARM_VECTORDATA_I8, ARM_VECTORDATA_I16, ARM_VECTORDATA_I32, ARM_VECTORDATA_I64, // Signed integer type ARM_VECTORDATA_S8, ARM_VECTORDATA_S16, ARM_VECTORDATA_S32, ARM_VECTORDATA_S64, // Unsigned integer type ARM_VECTORDATA_U8, ARM_VECTORDATA_U16, ARM_VECTORDATA_U32, ARM_VECTORDATA_U64, // Data type for VMUL/VMULL ARM_VECTORDATA_P8, // Floating type ARM_VECTORDATA_F16, ARM_VECTORDATA_F32, ARM_VECTORDATA_F64, // Convert float <-> float ARM_VECTORDATA_F16F64, // f16.f64 ARM_VECTORDATA_F64F16, // f64.f16 ARM_VECTORDATA_F32F16, // f32.f16 ARM_VECTORDATA_F16F32, // f32.f16 ARM_VECTORDATA_F64F32, // f64.f32 ARM_VECTORDATA_F32F64, // f32.f64 // Convert integer <-> float ARM_VECTORDATA_S32F32, // s32.f32 ARM_VECTORDATA_U32F32, // u32.f32 ARM_VECTORDATA_F32S32, // f32.s32 ARM_VECTORDATA_F32U32, // f32.u32 ARM_VECTORDATA_F64S16, // f64.s16 ARM_VECTORDATA_F32S16, // f32.s16 ARM_VECTORDATA_F64S32, // f64.s32 ARM_VECTORDATA_S16F64, // s16.f64 ARM_VECTORDATA_S16F32, // s16.f64 ARM_VECTORDATA_S32F64, // s32.f64 ARM_VECTORDATA_U16F64, // u16.f64 ARM_VECTORDATA_U16F32, // u16.f32 ARM_VECTORDATA_U32F64, // u32.f64 ARM_VECTORDATA_F64U16, // f64.u16 ARM_VECTORDATA_F32U16, // f32.u16 ARM_VECTORDATA_F64U32, // f64.u32 ARM_VECTORDATA_F16U16, // f16.u16 ARM_VECTORDATA_U16F16, // u16.f16 ARM_VECTORDATA_F16U32, // f16.u32 ARM_VECTORDATA_U32F16, // u32.f16 } arm_vectordata_type; /// ARM registers typedef enum arm_reg { ARM_REG_INVALID = 0, ARM_REG_APSR, ARM_REG_APSR_NZCV, ARM_REG_CPSR, ARM_REG_FPEXC, ARM_REG_FPINST, ARM_REG_FPSCR, ARM_REG_FPSCR_NZCV, ARM_REG_FPSID, ARM_REG_ITSTATE, ARM_REG_LR, ARM_REG_PC, ARM_REG_SP, ARM_REG_SPSR, ARM_REG_D0, ARM_REG_D1, ARM_REG_D2, ARM_REG_D3, ARM_REG_D4, ARM_REG_D5, ARM_REG_D6, ARM_REG_D7, ARM_REG_D8, ARM_REG_D9, ARM_REG_D10, ARM_REG_D11, ARM_REG_D12, ARM_REG_D13, ARM_REG_D14, ARM_REG_D15, ARM_REG_D16, ARM_REG_D17, ARM_REG_D18, ARM_REG_D19, ARM_REG_D20, ARM_REG_D21, ARM_REG_D22, ARM_REG_D23, ARM_REG_D24, ARM_REG_D25, ARM_REG_D26, ARM_REG_D27, ARM_REG_D28, ARM_REG_D29, ARM_REG_D30, ARM_REG_D31, ARM_REG_FPINST2, ARM_REG_MVFR0, ARM_REG_MVFR1, ARM_REG_MVFR2, ARM_REG_Q0, ARM_REG_Q1, ARM_REG_Q2, ARM_REG_Q3, ARM_REG_Q4, ARM_REG_Q5, ARM_REG_Q6, ARM_REG_Q7, ARM_REG_Q8, ARM_REG_Q9, ARM_REG_Q10, ARM_REG_Q11, ARM_REG_Q12, ARM_REG_Q13, ARM_REG_Q14, ARM_REG_Q15, ARM_REG_R0, ARM_REG_R1, ARM_REG_R2, ARM_REG_R3, ARM_REG_R4, ARM_REG_R5, ARM_REG_R6, ARM_REG_R7, ARM_REG_R8, ARM_REG_R9, ARM_REG_R10, ARM_REG_R11, ARM_REG_R12, ARM_REG_S0, ARM_REG_S1, ARM_REG_S2, ARM_REG_S3, ARM_REG_S4, ARM_REG_S5, ARM_REG_S6, ARM_REG_S7, ARM_REG_S8, ARM_REG_S9, ARM_REG_S10, ARM_REG_S11, ARM_REG_S12, ARM_REG_S13, ARM_REG_S14, ARM_REG_S15, ARM_REG_S16, ARM_REG_S17, ARM_REG_S18, ARM_REG_S19, ARM_REG_S20, ARM_REG_S21, ARM_REG_S22, ARM_REG_S23, ARM_REG_S24, ARM_REG_S25, ARM_REG_S26, ARM_REG_S27, ARM_REG_S28, ARM_REG_S29, ARM_REG_S30, ARM_REG_S31, ARM_REG_ENDING, // <-- mark the end of the list or registers // alias registers ARM_REG_R13 = ARM_REG_SP, ARM_REG_R14 = ARM_REG_LR, ARM_REG_R15 = ARM_REG_PC, ARM_REG_SB = ARM_REG_R9, ARM_REG_SL = ARM_REG_R10, ARM_REG_FP = ARM_REG_R11, ARM_REG_IP = ARM_REG_R12, } arm_reg; /// Instruction's operand referring to memory /// This is associated with ARM_OP_MEM operand type above typedef struct arm_op_mem { arm_reg base; ///< base register arm_reg index; ///< index register int scale; ///< scale for index register (can be 1, or -1) int disp; ///< displacement/offset value /// left-shift on index register, or 0 if irrelevant /// NOTE: this value can also be fetched via operand.shift.value int lshift; } arm_op_mem; /// Instruction operand typedef struct cs_arm_op { int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) struct { arm_shifter type; unsigned int value; } shift; arm_op_type type; ///< operand type union { int reg; ///< register value for REG/SYSREG operand int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand double fp; ///< floating point value for FP operand arm_op_mem mem; ///< base/index/scale/disp value for MEM operand arm_setend_type setend; ///< SETEND instruction's operand type }; /// in some instructions, an operand can be subtracted or added to /// the base register, /// if TRUE, this operand is subtracted. otherwise, it is added. bool subtracted; /// How is this operand accessed? (READ, WRITE or READ|WRITE) /// This field is combined of cs_ac_type. /// NOTE: this field is irrelevant if engine is compiled in DIET mode. uint8_t access; /// Neon lane index for NEON instructions (or -1 if irrelevant) int8_t neon_lane; } cs_arm_op; /// Instruction structure typedef struct cs_arm { bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions) int vector_size; ///< Scalar size for vector instructions arm_vectordata_type vector_data; ///< Data type for elements of vector instructions arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction arm_cc cc; ///< conditional code for this insn bool update_flags; ///< does this insn update flags? bool writeback; ///< does this insn write-back? arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_arm_op operands[36]; ///< operands for this instruction. } cs_arm; /// ARM instruction typedef enum arm_insn { ARM_INS_INVALID = 0, ARM_INS_ADC, ARM_INS_ADD, ARM_INS_ADDW, ARM_INS_ADR, ARM_INS_AESD, ARM_INS_AESE, ARM_INS_AESIMC, ARM_INS_AESMC, ARM_INS_AND, ARM_INS_ASR, ARM_INS_B, ARM_INS_BFC, ARM_INS_BFI, ARM_INS_BIC, ARM_INS_BKPT, ARM_INS_BL, ARM_INS_BLX, ARM_INS_BLXNS, ARM_INS_BX, ARM_INS_BXJ, ARM_INS_BXNS, ARM_INS_CBNZ, ARM_INS_CBZ, ARM_INS_CDP, ARM_INS_CDP2, ARM_INS_CLREX, ARM_INS_CLZ, ARM_INS_CMN, ARM_INS_CMP, ARM_INS_CPS, ARM_INS_CRC32B, ARM_INS_CRC32CB, ARM_INS_CRC32CH, ARM_INS_CRC32CW, ARM_INS_CRC32H, ARM_INS_CRC32W, ARM_INS_CSDB, ARM_INS_DBG, ARM_INS_DCPS1, ARM_INS_DCPS2, ARM_INS_DCPS3, ARM_INS_DFB, ARM_INS_DMB, ARM_INS_DSB, ARM_INS_EOR, ARM_INS_ERET, ARM_INS_ESB, ARM_INS_FADDD, ARM_INS_FADDS, ARM_INS_FCMPZD, ARM_INS_FCMPZS, ARM_INS_FCONSTD, ARM_INS_FCONSTS, ARM_INS_FLDMDBX, ARM_INS_FLDMIAX, ARM_INS_FMDHR, ARM_INS_FMDLR, ARM_INS_FMSTAT, ARM_INS_FSTMDBX, ARM_INS_FSTMIAX, ARM_INS_FSUBD, ARM_INS_FSUBS, ARM_INS_HINT, ARM_INS_HLT, ARM_INS_HVC, ARM_INS_ISB, ARM_INS_IT, ARM_INS_LDA, ARM_INS_LDAB, ARM_INS_LDAEX, ARM_INS_LDAEXB, ARM_INS_LDAEXD, ARM_INS_LDAEXH, ARM_INS_LDAH, ARM_INS_LDC, ARM_INS_LDC2, ARM_INS_LDC2L, ARM_INS_LDCL, ARM_INS_LDM, ARM_INS_LDMDA, ARM_INS_LDMDB, ARM_INS_LDMIB, ARM_INS_LDR, ARM_INS_LDRB, ARM_INS_LDRBT, ARM_INS_LDRD, ARM_INS_LDREX, ARM_INS_LDREXB, ARM_INS_LDREXD, ARM_INS_LDREXH, ARM_INS_LDRH, ARM_INS_LDRHT, ARM_INS_LDRSB, ARM_INS_LDRSBT, ARM_INS_LDRSH, ARM_INS_LDRSHT, ARM_INS_LDRT, ARM_INS_LSL, ARM_INS_LSR, ARM_INS_MCR, ARM_INS_MCR2, ARM_INS_MCRR, ARM_INS_MCRR2, ARM_INS_MLA, ARM_INS_MLS, ARM_INS_MOV, ARM_INS_MOVS, ARM_INS_MOVT, ARM_INS_MOVW, ARM_INS_MRC, ARM_INS_MRC2, ARM_INS_MRRC, ARM_INS_MRRC2, ARM_INS_MRS, ARM_INS_MSR, ARM_INS_MUL, ARM_INS_MVN, ARM_INS_NEG, ARM_INS_NOP, ARM_INS_ORN, ARM_INS_ORR, ARM_INS_PKHBT, ARM_INS_PKHTB, ARM_INS_PLD, ARM_INS_PLDW, ARM_INS_PLI, ARM_INS_POP, ARM_INS_PUSH, ARM_INS_QADD, ARM_INS_QADD16, ARM_INS_QADD8, ARM_INS_QASX, ARM_INS_QDADD, ARM_INS_QDSUB, ARM_INS_QSAX, ARM_INS_QSUB, ARM_INS_QSUB16, ARM_INS_QSUB8, ARM_INS_RBIT, ARM_INS_REV, ARM_INS_REV16, ARM_INS_REVSH, ARM_INS_RFEDA, ARM_INS_RFEDB, ARM_INS_RFEIA, ARM_INS_RFEIB, ARM_INS_ROR, ARM_INS_RRX, ARM_INS_RSB, ARM_INS_RSC, ARM_INS_SADD16, ARM_INS_SADD8, ARM_INS_SASX, ARM_INS_SBC, ARM_INS_SBFX, ARM_INS_SDIV, ARM_INS_SEL, ARM_INS_SETEND, ARM_INS_SETPAN, ARM_INS_SEV, ARM_INS_SEVL, ARM_INS_SG, ARM_INS_SHA1C, ARM_INS_SHA1H, ARM_INS_SHA1M, ARM_INS_SHA1P, ARM_INS_SHA1SU0, ARM_INS_SHA1SU1, ARM_INS_SHA256H, ARM_INS_SHA256H2, ARM_INS_SHA256SU0, ARM_INS_SHA256SU1, ARM_INS_SHADD16, ARM_INS_SHADD8, ARM_INS_SHASX, ARM_INS_SHSAX, ARM_INS_SHSUB16, ARM_INS_SHSUB8, ARM_INS_SMC, ARM_INS_SMLABB, ARM_INS_SMLABT, ARM_INS_SMLAD, ARM_INS_SMLADX, ARM_INS_SMLAL, ARM_INS_SMLALBB, ARM_INS_SMLALBT, ARM_INS_SMLALD, ARM_INS_SMLALDX, ARM_INS_SMLALTB, ARM_INS_SMLALTT, ARM_INS_SMLATB, ARM_INS_SMLATT, ARM_INS_SMLAWB, ARM_INS_SMLAWT, ARM_INS_SMLSD, ARM_INS_SMLSDX, ARM_INS_SMLSLD, ARM_INS_SMLSLDX, ARM_INS_SMMLA, ARM_INS_SMMLAR, ARM_INS_SMMLS, ARM_INS_SMMLSR, ARM_INS_SMMUL, ARM_INS_SMMULR, ARM_INS_SMUAD, ARM_INS_SMUADX, ARM_INS_SMULBB, ARM_INS_SMULBT, ARM_INS_SMULL, ARM_INS_SMULTB, ARM_INS_SMULTT, ARM_INS_SMULWB, ARM_INS_SMULWT, ARM_INS_SMUSD, ARM_INS_SMUSDX, ARM_INS_SRSDA, ARM_INS_SRSDB, ARM_INS_SRSIA, ARM_INS_SRSIB, ARM_INS_SSAT, ARM_INS_SSAT16, ARM_INS_SSAX, ARM_INS_SSUB16, ARM_INS_SSUB8, ARM_INS_STC, ARM_INS_STC2, ARM_INS_STC2L, ARM_INS_STCL, ARM_INS_STL, ARM_INS_STLB, ARM_INS_STLEX, ARM_INS_STLEXB, ARM_INS_STLEXD, ARM_INS_STLEXH, ARM_INS_STLH, ARM_INS_STM, ARM_INS_STMDA, ARM_INS_STMDB, ARM_INS_STMIB, ARM_INS_STR, ARM_INS_STRB, ARM_INS_STRBT, ARM_INS_STRD, ARM_INS_STREX, ARM_INS_STREXB, ARM_INS_STREXD, ARM_INS_STREXH, ARM_INS_STRH, ARM_INS_STRHT, ARM_INS_STRT, ARM_INS_SUB, ARM_INS_SUBS, ARM_INS_SUBW, ARM_INS_SVC, ARM_INS_SWP, ARM_INS_SWPB, ARM_INS_SXTAB, ARM_INS_SXTAB16, ARM_INS_SXTAH, ARM_INS_SXTB, ARM_INS_SXTB16, ARM_INS_SXTH, ARM_INS_TBB, ARM_INS_TBH, ARM_INS_TEQ, ARM_INS_TRAP, ARM_INS_TSB, ARM_INS_TST, ARM_INS_TT, ARM_INS_TTA, ARM_INS_TTAT, ARM_INS_TTT, ARM_INS_UADD16, ARM_INS_UADD8, ARM_INS_UASX, ARM_INS_UBFX, ARM_INS_UDF, ARM_INS_UDIV, ARM_INS_UHADD16, ARM_INS_UHADD8, ARM_INS_UHASX, ARM_INS_UHSAX, ARM_INS_UHSUB16, ARM_INS_UHSUB8, ARM_INS_UMAAL, ARM_INS_UMLAL, ARM_INS_UMULL, ARM_INS_UQADD16, ARM_INS_UQADD8, ARM_INS_UQASX, ARM_INS_UQSAX, ARM_INS_UQSUB16, ARM_INS_UQSUB8, ARM_INS_USAD8, ARM_INS_USADA8, ARM_INS_USAT, ARM_INS_USAT16, ARM_INS_USAX, ARM_INS_USUB16, ARM_INS_USUB8, ARM_INS_UXTAB, ARM_INS_UXTAB16, ARM_INS_UXTAH, ARM_INS_UXTB, ARM_INS_UXTB16, ARM_INS_UXTH, ARM_INS_VABA, ARM_INS_VABAL, ARM_INS_VABD, ARM_INS_VABDL, ARM_INS_VABS, ARM_INS_VACGE, ARM_INS_VACGT, ARM_INS_VACLE, ARM_INS_VACLT, ARM_INS_VADD, ARM_INS_VADDHN, ARM_INS_VADDL, ARM_INS_VADDW, ARM_INS_VAND, ARM_INS_VBIC, ARM_INS_VBIF, ARM_INS_VBIT, ARM_INS_VBSL, ARM_INS_VCADD, ARM_INS_VCEQ, ARM_INS_VCGE, ARM_INS_VCGT, ARM_INS_VCLE, ARM_INS_VCLS, ARM_INS_VCLT, ARM_INS_VCLZ, ARM_INS_VCMLA, ARM_INS_VCMP, ARM_INS_VCMPE, ARM_INS_VCNT, ARM_INS_VCVT, ARM_INS_VCVTA, ARM_INS_VCVTB, ARM_INS_VCVTM, ARM_INS_VCVTN, ARM_INS_VCVTP, ARM_INS_VCVTR, ARM_INS_VCVTT, ARM_INS_VDIV, ARM_INS_VDUP, ARM_INS_VEOR, ARM_INS_VEXT, ARM_INS_VFMA, ARM_INS_VFMS, ARM_INS_VFNMA, ARM_INS_VFNMS, ARM_INS_VHADD, ARM_INS_VHSUB, ARM_INS_VINS, ARM_INS_VJCVT, ARM_INS_VLD1, ARM_INS_VLD2, ARM_INS_VLD3, ARM_INS_VLD4, ARM_INS_VLDMDB, ARM_INS_VLDMIA, ARM_INS_VLDR, ARM_INS_VLLDM, ARM_INS_VLSTM, ARM_INS_VMAX, ARM_INS_VMAXNM, ARM_INS_VMIN, ARM_INS_VMINNM, ARM_INS_VMLA, ARM_INS_VMLAL, ARM_INS_VMLS, ARM_INS_VMLSL, ARM_INS_VMOV, ARM_INS_VMOVL, ARM_INS_VMOVN, ARM_INS_VMOVX, ARM_INS_VMRS, ARM_INS_VMSR, ARM_INS_VMUL, ARM_INS_VMULL, ARM_INS_VMVN, ARM_INS_VNEG, ARM_INS_VNMLA, ARM_INS_VNMLS, ARM_INS_VNMUL, ARM_INS_VORN, ARM_INS_VORR, ARM_INS_VPADAL, ARM_INS_VPADD, ARM_INS_VPADDL, ARM_INS_VPMAX, ARM_INS_VPMIN, ARM_INS_VPOP, ARM_INS_VPUSH, ARM_INS_VQABS, ARM_INS_VQADD, ARM_INS_VQDMLAL, ARM_INS_VQDMLSL, ARM_INS_VQDMULH, ARM_INS_VQDMULL, ARM_INS_VQMOVN, ARM_INS_VQMOVUN, ARM_INS_VQNEG, ARM_INS_VQRDMLAH, ARM_INS_VQRDMLSH, ARM_INS_VQRDMULH, ARM_INS_VQRSHL, ARM_INS_VQRSHRN, ARM_INS_VQRSHRUN, ARM_INS_VQSHL, ARM_INS_VQSHLU, ARM_INS_VQSHRN, ARM_INS_VQSHRUN, ARM_INS_VQSUB, ARM_INS_VRADDHN, ARM_INS_VRECPE, ARM_INS_VRECPS, ARM_INS_VREV16, ARM_INS_VREV32, ARM_INS_VREV64, ARM_INS_VRHADD, ARM_INS_VRINTA, ARM_INS_VRINTM, ARM_INS_VRINTN, ARM_INS_VRINTP, ARM_INS_VRINTR, ARM_INS_VRINTX, ARM_INS_VRINTZ, ARM_INS_VRSHL, ARM_INS_VRSHR, ARM_INS_VRSHRN, ARM_INS_VRSQRTE, ARM_INS_VRSQRTS, ARM_INS_VRSRA, ARM_INS_VRSUBHN, ARM_INS_VSDOT, ARM_INS_VSELEQ, ARM_INS_VSELGE, ARM_INS_VSELGT, ARM_INS_VSELVS, ARM_INS_VSHL, ARM_INS_VSHLL, ARM_INS_VSHR, ARM_INS_VSHRN, ARM_INS_VSLI, ARM_INS_VSQRT, ARM_INS_VSRA, ARM_INS_VSRI, ARM_INS_VST1, ARM_INS_VST2, ARM_INS_VST3, ARM_INS_VST4, ARM_INS_VSTMDB, ARM_INS_VSTMIA, ARM_INS_VSTR, ARM_INS_VSUB, ARM_INS_VSUBHN, ARM_INS_VSUBL, ARM_INS_VSUBW, ARM_INS_VSWP, ARM_INS_VTBL, ARM_INS_VTBX, ARM_INS_VTRN, ARM_INS_VTST, ARM_INS_VUDOT, ARM_INS_VUZP, ARM_INS_VZIP, ARM_INS_WFE, ARM_INS_WFI, ARM_INS_YIELD, ARM_INS_ENDING, // <-- mark the end of the list of instructions } arm_insn; /// Group of ARM instructions typedef enum arm_insn_group { ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) ARM_GRP_JUMP, ///< = CS_GRP_JUMP ARM_GRP_CALL, ///< = CS_GRP_CALL ARM_GRP_INT = 4, ///< = CS_GRP_INT ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE // Architecture-specific groups ARM_GRP_CRYPTO = 128, ARM_GRP_DATABARRIER, ARM_GRP_DIVIDE, ARM_GRP_FPARMV8, ARM_GRP_MULTPRO, ARM_GRP_NEON, ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2DSP, ARM_GRP_TRUSTZONE, ARM_GRP_V4T, ARM_GRP_V5T, ARM_GRP_V5TE, ARM_GRP_V6, ARM_GRP_V6T2, ARM_GRP_V7, ARM_GRP_V8, ARM_GRP_VFP2, ARM_GRP_VFP3, ARM_GRP_VFP4, ARM_GRP_ARM, ARM_GRP_MCLASS, ARM_GRP_NOTMCLASS, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_THUMB2, ARM_GRP_PREV8, ARM_GRP_FPVMLX, ARM_GRP_MULOPS, ARM_GRP_CRC, ARM_GRP_DPVFP, ARM_GRP_V6M, ARM_GRP_VIRTUALIZATION, ARM_GRP_ENDING, } arm_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/arm64.h000064400000000000000000001661460072674642500205620ustar 00000000000000#ifndef CAPSTONE_ARM64_H #define CAPSTONE_ARM64_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// ARM64 shift type typedef enum arm64_shifter { ARM64_SFT_INVALID = 0, ARM64_SFT_LSL = 1, ARM64_SFT_MSL = 2, ARM64_SFT_LSR = 3, ARM64_SFT_ASR = 4, ARM64_SFT_ROR = 5, } arm64_shifter; /// ARM64 extender type typedef enum arm64_extender { ARM64_EXT_INVALID = 0, ARM64_EXT_UXTB = 1, ARM64_EXT_UXTH = 2, ARM64_EXT_UXTW = 3, ARM64_EXT_UXTX = 4, ARM64_EXT_SXTB = 5, ARM64_EXT_SXTH = 6, ARM64_EXT_SXTW = 7, ARM64_EXT_SXTX = 8, } arm64_extender; /// ARM64 condition code typedef enum arm64_cc { ARM64_CC_INVALID = 0, ARM64_CC_EQ = 1, ///< Equal ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than ARM64_CC_MI = 5, ///< Minus, negative: Less than ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered ARM64_CC_VS = 7, ///< Overflow: Unordered ARM64_CC_VC = 8, ///< No overflow: Ordered ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal ARM64_CC_LT = 12, ///< Less than: Less than, or unordered ARM64_CC_GT = 13, ///< Signed greater than: Greater than ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional) ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional) //< Note the NV exists purely to disassemble 0b1111. Execution is "always". } arm64_cc; /// System registers typedef enum arm64_sysreg { // System registers for MRS ARM64_SYSREG_INVALID = 0, ARM64_SYSREG_MDCCSR_EL0 = 0x9808, ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, ARM64_SYSREG_MDRAR_EL1 = 0x8080, ARM64_SYSREG_OSLSR_EL1 = 0x808C, ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6, ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6, ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7, ARM64_SYSREG_MIDR_EL1 = 0xC000, ARM64_SYSREG_CCSIDR_EL1 = 0xC800, ARM64_SYSREG_CCSIDR2_EL1 = 0xC802, ARM64_SYSREG_CLIDR_EL1 = 0xC801, ARM64_SYSREG_CTR_EL0 = 0xD801, ARM64_SYSREG_MPIDR_EL1 = 0xC005, ARM64_SYSREG_REVIDR_EL1 = 0xC006, ARM64_SYSREG_AIDR_EL1 = 0xC807, ARM64_SYSREG_DCZID_EL0 = 0xD807, ARM64_SYSREG_ID_PFR0_EL1 = 0xC008, ARM64_SYSREG_ID_PFR1_EL1 = 0xC009, ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A, ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B, ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C, ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D, ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E, ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F, ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010, ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011, ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012, ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013, ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014, ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015, ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017, ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020, ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021, ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028, ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029, ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C, ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D, ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030, ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031, ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038, ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039, ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A, ARM64_SYSREG_MVFR0_EL1 = 0xC018, ARM64_SYSREG_MVFR1_EL1 = 0xC019, ARM64_SYSREG_MVFR2_EL1 = 0xC01A, ARM64_SYSREG_RVBAR_EL1 = 0xC601, ARM64_SYSREG_RVBAR_EL2 = 0xE601, ARM64_SYSREG_RVBAR_EL3 = 0xF601, ARM64_SYSREG_ISR_EL1 = 0xC608, ARM64_SYSREG_CNTPCT_EL0 = 0xDF01, ARM64_SYSREG_CNTVCT_EL0 = 0xDF02, ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016, ARM64_SYSREG_TRCSTATR = 0x8818, ARM64_SYSREG_TRCIDR8 = 0x8806, ARM64_SYSREG_TRCIDR9 = 0x880E, ARM64_SYSREG_TRCIDR10 = 0x8816, ARM64_SYSREG_TRCIDR11 = 0x881E, ARM64_SYSREG_TRCIDR12 = 0x8826, ARM64_SYSREG_TRCIDR13 = 0x882E, ARM64_SYSREG_TRCIDR0 = 0x8847, ARM64_SYSREG_TRCIDR1 = 0x884F, ARM64_SYSREG_TRCIDR2 = 0x8857, ARM64_SYSREG_TRCIDR3 = 0x885F, ARM64_SYSREG_TRCIDR4 = 0x8867, ARM64_SYSREG_TRCIDR5 = 0x886F, ARM64_SYSREG_TRCIDR6 = 0x8877, ARM64_SYSREG_TRCIDR7 = 0x887F, ARM64_SYSREG_TRCOSLSR = 0x888C, ARM64_SYSREG_TRCPDSR = 0x88AC, ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6, ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE, ARM64_SYSREG_TRCLSR = 0x8BEE, ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6, ARM64_SYSREG_TRCDEVARCH = 0x8BFE, ARM64_SYSREG_TRCDEVID = 0x8B97, ARM64_SYSREG_TRCDEVTYPE = 0x8B9F, ARM64_SYSREG_TRCPIDR4 = 0x8BA7, ARM64_SYSREG_TRCPIDR5 = 0x8BAF, ARM64_SYSREG_TRCPIDR6 = 0x8BB7, ARM64_SYSREG_TRCPIDR7 = 0x8BBF, ARM64_SYSREG_TRCPIDR0 = 0x8BC7, ARM64_SYSREG_TRCPIDR1 = 0x8BCF, ARM64_SYSREG_TRCPIDR2 = 0x8BD7, ARM64_SYSREG_TRCPIDR3 = 0x8BDF, ARM64_SYSREG_TRCCIDR0 = 0x8BE7, ARM64_SYSREG_TRCCIDR1 = 0x8BEF, ARM64_SYSREG_TRCCIDR2 = 0x8BF7, ARM64_SYSREG_TRCCIDR3 = 0x8BFF, ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660, ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640, ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662, ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642, ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B, ARM64_SYSREG_ICH_VTR_EL2 = 0xE659, ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B, ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D, ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024, ARM64_SYSREG_LORID_EL1 = 0xC527, ARM64_SYSREG_ERRIDR_EL1 = 0xC298, ARM64_SYSREG_ERXFR_EL1 = 0xC2A0, ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, ARM64_SYSREG_OSLAR_EL1 = 0x8084, ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4, ARM64_SYSREG_TRCOSLAR = 0x8884, ARM64_SYSREG_TRCLAR = 0x8BE6, ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661, ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641, ARM64_SYSREG_ICC_DIR_EL1 = 0xC659, ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D, ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E, ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F, ARM64_SYSREG_OSDTRRX_EL1 = 0x8002, ARM64_SYSREG_OSDTRTX_EL1 = 0x801A, ARM64_SYSREG_TEECR32_EL1 = 0x9000, ARM64_SYSREG_MDCCINT_EL1 = 0x8010, ARM64_SYSREG_MDSCR_EL1 = 0x8012, ARM64_SYSREG_DBGDTR_EL0 = 0x9820, ARM64_SYSREG_OSECCR_EL1 = 0x8032, ARM64_SYSREG_DBGVCR32_EL2 = 0xA038, ARM64_SYSREG_DBGBVR0_EL1 = 0x8004, ARM64_SYSREG_DBGBVR1_EL1 = 0x800C, ARM64_SYSREG_DBGBVR2_EL1 = 0x8014, ARM64_SYSREG_DBGBVR3_EL1 = 0x801C, ARM64_SYSREG_DBGBVR4_EL1 = 0x8024, ARM64_SYSREG_DBGBVR5_EL1 = 0x802C, ARM64_SYSREG_DBGBVR6_EL1 = 0x8034, ARM64_SYSREG_DBGBVR7_EL1 = 0x803C, ARM64_SYSREG_DBGBVR8_EL1 = 0x8044, ARM64_SYSREG_DBGBVR9_EL1 = 0x804C, ARM64_SYSREG_DBGBVR10_EL1 = 0x8054, ARM64_SYSREG_DBGBVR11_EL1 = 0x805C, ARM64_SYSREG_DBGBVR12_EL1 = 0x8064, ARM64_SYSREG_DBGBVR13_EL1 = 0x806C, ARM64_SYSREG_DBGBVR14_EL1 = 0x8074, ARM64_SYSREG_DBGBVR15_EL1 = 0x807C, ARM64_SYSREG_DBGBCR0_EL1 = 0x8005, ARM64_SYSREG_DBGBCR1_EL1 = 0x800D, ARM64_SYSREG_DBGBCR2_EL1 = 0x8015, ARM64_SYSREG_DBGBCR3_EL1 = 0x801D, ARM64_SYSREG_DBGBCR4_EL1 = 0x8025, ARM64_SYSREG_DBGBCR5_EL1 = 0x802D, ARM64_SYSREG_DBGBCR6_EL1 = 0x8035, ARM64_SYSREG_DBGBCR7_EL1 = 0x803D, ARM64_SYSREG_DBGBCR8_EL1 = 0x8045, ARM64_SYSREG_DBGBCR9_EL1 = 0x804D, ARM64_SYSREG_DBGBCR10_EL1 = 0x8055, ARM64_SYSREG_DBGBCR11_EL1 = 0x805D, ARM64_SYSREG_DBGBCR12_EL1 = 0x8065, ARM64_SYSREG_DBGBCR13_EL1 = 0x806D, ARM64_SYSREG_DBGBCR14_EL1 = 0x8075, ARM64_SYSREG_DBGBCR15_EL1 = 0x807D, ARM64_SYSREG_DBGWVR0_EL1 = 0x8006, ARM64_SYSREG_DBGWVR1_EL1 = 0x800E, ARM64_SYSREG_DBGWVR2_EL1 = 0x8016, ARM64_SYSREG_DBGWVR3_EL1 = 0x801E, ARM64_SYSREG_DBGWVR4_EL1 = 0x8026, ARM64_SYSREG_DBGWVR5_EL1 = 0x802E, ARM64_SYSREG_DBGWVR6_EL1 = 0x8036, ARM64_SYSREG_DBGWVR7_EL1 = 0x803E, ARM64_SYSREG_DBGWVR8_EL1 = 0x8046, ARM64_SYSREG_DBGWVR9_EL1 = 0x804E, ARM64_SYSREG_DBGWVR10_EL1 = 0x8056, ARM64_SYSREG_DBGWVR11_EL1 = 0x805E, ARM64_SYSREG_DBGWVR12_EL1 = 0x8066, ARM64_SYSREG_DBGWVR13_EL1 = 0x806E, ARM64_SYSREG_DBGWVR14_EL1 = 0x8076, ARM64_SYSREG_DBGWVR15_EL1 = 0x807E, ARM64_SYSREG_DBGWCR0_EL1 = 0x8007, ARM64_SYSREG_DBGWCR1_EL1 = 0x800F, ARM64_SYSREG_DBGWCR2_EL1 = 0x8017, ARM64_SYSREG_DBGWCR3_EL1 = 0x801F, ARM64_SYSREG_DBGWCR4_EL1 = 0x8027, ARM64_SYSREG_DBGWCR5_EL1 = 0x802F, ARM64_SYSREG_DBGWCR6_EL1 = 0x8037, ARM64_SYSREG_DBGWCR7_EL1 = 0x803F, ARM64_SYSREG_DBGWCR8_EL1 = 0x8047, ARM64_SYSREG_DBGWCR9_EL1 = 0x804F, ARM64_SYSREG_DBGWCR10_EL1 = 0x8057, ARM64_SYSREG_DBGWCR11_EL1 = 0x805F, ARM64_SYSREG_DBGWCR12_EL1 = 0x8067, ARM64_SYSREG_DBGWCR13_EL1 = 0x806F, ARM64_SYSREG_DBGWCR14_EL1 = 0x8077, ARM64_SYSREG_DBGWCR15_EL1 = 0x807F, ARM64_SYSREG_TEEHBR32_EL1 = 0x9080, ARM64_SYSREG_OSDLR_EL1 = 0x809C, ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4, ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6, ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE, ARM64_SYSREG_CSSELR_EL1 = 0xD000, ARM64_SYSREG_VPIDR_EL2 = 0xE000, ARM64_SYSREG_VMPIDR_EL2 = 0xE005, ARM64_SYSREG_CPACR_EL1 = 0xC082, ARM64_SYSREG_SCTLR_EL1 = 0xC080, ARM64_SYSREG_SCTLR_EL2 = 0xE080, ARM64_SYSREG_SCTLR_EL3 = 0xF080, ARM64_SYSREG_ACTLR_EL1 = 0xC081, ARM64_SYSREG_ACTLR_EL2 = 0xE081, ARM64_SYSREG_ACTLR_EL3 = 0xF081, ARM64_SYSREG_HCR_EL2 = 0xE088, ARM64_SYSREG_SCR_EL3 = 0xF088, ARM64_SYSREG_MDCR_EL2 = 0xE089, ARM64_SYSREG_SDER32_EL3 = 0xF089, ARM64_SYSREG_CPTR_EL2 = 0xE08A, ARM64_SYSREG_CPTR_EL3 = 0xF08A, ARM64_SYSREG_HSTR_EL2 = 0xE08B, ARM64_SYSREG_HACR_EL2 = 0xE08F, ARM64_SYSREG_MDCR_EL3 = 0xF099, ARM64_SYSREG_TTBR0_EL1 = 0xC100, ARM64_SYSREG_TTBR0_EL2 = 0xE100, ARM64_SYSREG_TTBR0_EL3 = 0xF100, ARM64_SYSREG_TTBR1_EL1 = 0xC101, ARM64_SYSREG_TCR_EL1 = 0xC102, ARM64_SYSREG_TCR_EL2 = 0xE102, ARM64_SYSREG_TCR_EL3 = 0xF102, ARM64_SYSREG_VTTBR_EL2 = 0xE108, ARM64_SYSREG_VTCR_EL2 = 0xE10A, ARM64_SYSREG_DACR32_EL2 = 0xE180, ARM64_SYSREG_SPSR_EL1 = 0xC200, ARM64_SYSREG_SPSR_EL2 = 0xE200, ARM64_SYSREG_SPSR_EL3 = 0xF200, ARM64_SYSREG_ELR_EL1 = 0xC201, ARM64_SYSREG_ELR_EL2 = 0xE201, ARM64_SYSREG_ELR_EL3 = 0xF201, ARM64_SYSREG_SP_EL0 = 0xC208, ARM64_SYSREG_SP_EL1 = 0xE208, ARM64_SYSREG_SP_EL2 = 0xF208, ARM64_SYSREG_SPSEL = 0xC210, ARM64_SYSREG_NZCV = 0xDA10, ARM64_SYSREG_DAIF = 0xDA11, ARM64_SYSREG_CURRENTEL = 0xC212, ARM64_SYSREG_SPSR_IRQ = 0xE218, ARM64_SYSREG_SPSR_ABT = 0xE219, ARM64_SYSREG_SPSR_UND = 0xE21A, ARM64_SYSREG_SPSR_FIQ = 0xE21B, ARM64_SYSREG_FPCR = 0xDA20, ARM64_SYSREG_FPSR = 0xDA21, ARM64_SYSREG_DSPSR_EL0 = 0xDA28, ARM64_SYSREG_DLR_EL0 = 0xDA29, ARM64_SYSREG_IFSR32_EL2 = 0xE281, ARM64_SYSREG_AFSR0_EL1 = 0xC288, ARM64_SYSREG_AFSR0_EL2 = 0xE288, ARM64_SYSREG_AFSR0_EL3 = 0xF288, ARM64_SYSREG_AFSR1_EL1 = 0xC289, ARM64_SYSREG_AFSR1_EL2 = 0xE289, ARM64_SYSREG_AFSR1_EL3 = 0xF289, ARM64_SYSREG_ESR_EL1 = 0xC290, ARM64_SYSREG_ESR_EL2 = 0xE290, ARM64_SYSREG_ESR_EL3 = 0xF290, ARM64_SYSREG_FPEXC32_EL2 = 0xE298, ARM64_SYSREG_FAR_EL1 = 0xC300, ARM64_SYSREG_FAR_EL2 = 0xE300, ARM64_SYSREG_FAR_EL3 = 0xF300, ARM64_SYSREG_HPFAR_EL2 = 0xE304, ARM64_SYSREG_PAR_EL1 = 0xC3A0, ARM64_SYSREG_PMCR_EL0 = 0xDCE0, ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1, ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2, ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3, ARM64_SYSREG_PMSELR_EL0 = 0xDCE5, ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8, ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9, ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA, ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0, ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1, ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2, ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3, ARM64_SYSREG_MAIR_EL1 = 0xC510, ARM64_SYSREG_MAIR_EL2 = 0xE510, ARM64_SYSREG_MAIR_EL3 = 0xF510, ARM64_SYSREG_AMAIR_EL1 = 0xC518, ARM64_SYSREG_AMAIR_EL2 = 0xE518, ARM64_SYSREG_AMAIR_EL3 = 0xF518, ARM64_SYSREG_VBAR_EL1 = 0xC600, ARM64_SYSREG_VBAR_EL2 = 0xE600, ARM64_SYSREG_VBAR_EL3 = 0xF600, ARM64_SYSREG_RMR_EL1 = 0xC602, ARM64_SYSREG_RMR_EL2 = 0xE602, ARM64_SYSREG_RMR_EL3 = 0xF602, ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681, ARM64_SYSREG_TPIDR_EL0 = 0xDE82, ARM64_SYSREG_TPIDR_EL2 = 0xE682, ARM64_SYSREG_TPIDR_EL3 = 0xF682, ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83, ARM64_SYSREG_TPIDR_EL1 = 0xC684, ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00, ARM64_SYSREG_CNTVOFF_EL2 = 0xE703, ARM64_SYSREG_CNTKCTL_EL1 = 0xC708, ARM64_SYSREG_CNTHCTL_EL2 = 0xE708, ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10, ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710, ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10, ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11, ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711, ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11, ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12, ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712, ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12, ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18, ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19, ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A, ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40, ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41, ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42, ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43, ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44, ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45, ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46, ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47, ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48, ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49, ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A, ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B, ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C, ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D, ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E, ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F, ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50, ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51, ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52, ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53, ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54, ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55, ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56, ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57, ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58, ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59, ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A, ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B, ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C, ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D, ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E, ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F, ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60, ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61, ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62, ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63, ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64, ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65, ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66, ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67, ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68, ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69, ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A, ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B, ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C, ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D, ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E, ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F, ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70, ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71, ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72, ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73, ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74, ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75, ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76, ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77, ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78, ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79, ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A, ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B, ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C, ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D, ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E, ARM64_SYSREG_TRCPRGCTLR = 0x8808, ARM64_SYSREG_TRCPROCSELR = 0x8810, ARM64_SYSREG_TRCCONFIGR = 0x8820, ARM64_SYSREG_TRCAUXCTLR = 0x8830, ARM64_SYSREG_TRCEVENTCTL0R = 0x8840, ARM64_SYSREG_TRCEVENTCTL1R = 0x8848, ARM64_SYSREG_TRCSTALLCTLR = 0x8858, ARM64_SYSREG_TRCTSCTLR = 0x8860, ARM64_SYSREG_TRCSYNCPR = 0x8868, ARM64_SYSREG_TRCCCCTLR = 0x8870, ARM64_SYSREG_TRCBBCTLR = 0x8878, ARM64_SYSREG_TRCTRACEIDR = 0x8801, ARM64_SYSREG_TRCQCTLR = 0x8809, ARM64_SYSREG_TRCVICTLR = 0x8802, ARM64_SYSREG_TRCVIIECTLR = 0x880A, ARM64_SYSREG_TRCVISSCTLR = 0x8812, ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A, ARM64_SYSREG_TRCVDCTLR = 0x8842, ARM64_SYSREG_TRCVDSACCTLR = 0x884A, ARM64_SYSREG_TRCVDARCCTLR = 0x8852, ARM64_SYSREG_TRCSEQEVR0 = 0x8804, ARM64_SYSREG_TRCSEQEVR1 = 0x880C, ARM64_SYSREG_TRCSEQEVR2 = 0x8814, ARM64_SYSREG_TRCSEQRSTEVR = 0x8834, ARM64_SYSREG_TRCSEQSTR = 0x883C, ARM64_SYSREG_TRCEXTINSELR = 0x8844, ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805, ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D, ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815, ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D, ARM64_SYSREG_TRCCNTCTLR0 = 0x8825, ARM64_SYSREG_TRCCNTCTLR1 = 0x882D, ARM64_SYSREG_TRCCNTCTLR2 = 0x8835, ARM64_SYSREG_TRCCNTCTLR3 = 0x883D, ARM64_SYSREG_TRCCNTVR0 = 0x8845, ARM64_SYSREG_TRCCNTVR1 = 0x884D, ARM64_SYSREG_TRCCNTVR2 = 0x8855, ARM64_SYSREG_TRCCNTVR3 = 0x885D, ARM64_SYSREG_TRCIMSPEC0 = 0x8807, ARM64_SYSREG_TRCIMSPEC1 = 0x880F, ARM64_SYSREG_TRCIMSPEC2 = 0x8817, ARM64_SYSREG_TRCIMSPEC3 = 0x881F, ARM64_SYSREG_TRCIMSPEC4 = 0x8827, ARM64_SYSREG_TRCIMSPEC5 = 0x882F, ARM64_SYSREG_TRCIMSPEC6 = 0x8837, ARM64_SYSREG_TRCIMSPEC7 = 0x883F, ARM64_SYSREG_TRCRSCTLR2 = 0x8890, ARM64_SYSREG_TRCRSCTLR3 = 0x8898, ARM64_SYSREG_TRCRSCTLR4 = 0x88A0, ARM64_SYSREG_TRCRSCTLR5 = 0x88A8, ARM64_SYSREG_TRCRSCTLR6 = 0x88B0, ARM64_SYSREG_TRCRSCTLR7 = 0x88B8, ARM64_SYSREG_TRCRSCTLR8 = 0x88C0, ARM64_SYSREG_TRCRSCTLR9 = 0x88C8, ARM64_SYSREG_TRCRSCTLR10 = 0x88D0, ARM64_SYSREG_TRCRSCTLR11 = 0x88D8, ARM64_SYSREG_TRCRSCTLR12 = 0x88E0, ARM64_SYSREG_TRCRSCTLR13 = 0x88E8, ARM64_SYSREG_TRCRSCTLR14 = 0x88F0, ARM64_SYSREG_TRCRSCTLR15 = 0x88F8, ARM64_SYSREG_TRCRSCTLR16 = 0x8881, ARM64_SYSREG_TRCRSCTLR17 = 0x8889, ARM64_SYSREG_TRCRSCTLR18 = 0x8891, ARM64_SYSREG_TRCRSCTLR19 = 0x8899, ARM64_SYSREG_TRCRSCTLR20 = 0x88A1, ARM64_SYSREG_TRCRSCTLR21 = 0x88A9, ARM64_SYSREG_TRCRSCTLR22 = 0x88B1, ARM64_SYSREG_TRCRSCTLR23 = 0x88B9, ARM64_SYSREG_TRCRSCTLR24 = 0x88C1, ARM64_SYSREG_TRCRSCTLR25 = 0x88C9, ARM64_SYSREG_TRCRSCTLR26 = 0x88D1, ARM64_SYSREG_TRCRSCTLR27 = 0x88D9, ARM64_SYSREG_TRCRSCTLR28 = 0x88E1, ARM64_SYSREG_TRCRSCTLR29 = 0x88E9, ARM64_SYSREG_TRCRSCTLR30 = 0x88F1, ARM64_SYSREG_TRCRSCTLR31 = 0x88F9, ARM64_SYSREG_TRCSSCCR0 = 0x8882, ARM64_SYSREG_TRCSSCCR1 = 0x888A, ARM64_SYSREG_TRCSSCCR2 = 0x8892, ARM64_SYSREG_TRCSSCCR3 = 0x889A, ARM64_SYSREG_TRCSSCCR4 = 0x88A2, ARM64_SYSREG_TRCSSCCR5 = 0x88AA, ARM64_SYSREG_TRCSSCCR6 = 0x88B2, ARM64_SYSREG_TRCSSCCR7 = 0x88BA, ARM64_SYSREG_TRCSSCSR0 = 0x88C2, ARM64_SYSREG_TRCSSCSR1 = 0x88CA, ARM64_SYSREG_TRCSSCSR2 = 0x88D2, ARM64_SYSREG_TRCSSCSR3 = 0x88DA, ARM64_SYSREG_TRCSSCSR4 = 0x88E2, ARM64_SYSREG_TRCSSCSR5 = 0x88EA, ARM64_SYSREG_TRCSSCSR6 = 0x88F2, ARM64_SYSREG_TRCSSCSR7 = 0x88FA, ARM64_SYSREG_TRCSSPCICR0 = 0x8883, ARM64_SYSREG_TRCSSPCICR1 = 0x888B, ARM64_SYSREG_TRCSSPCICR2 = 0x8893, ARM64_SYSREG_TRCSSPCICR3 = 0x889B, ARM64_SYSREG_TRCSSPCICR4 = 0x88A3, ARM64_SYSREG_TRCSSPCICR5 = 0x88AB, ARM64_SYSREG_TRCSSPCICR6 = 0x88B3, ARM64_SYSREG_TRCSSPCICR7 = 0x88BB, ARM64_SYSREG_TRCPDCR = 0x88A4, ARM64_SYSREG_TRCACVR0 = 0x8900, ARM64_SYSREG_TRCACVR1 = 0x8910, ARM64_SYSREG_TRCACVR2 = 0x8920, ARM64_SYSREG_TRCACVR3 = 0x8930, ARM64_SYSREG_TRCACVR4 = 0x8940, ARM64_SYSREG_TRCACVR5 = 0x8950, ARM64_SYSREG_TRCACVR6 = 0x8960, ARM64_SYSREG_TRCACVR7 = 0x8970, ARM64_SYSREG_TRCACVR8 = 0x8901, ARM64_SYSREG_TRCACVR9 = 0x8911, ARM64_SYSREG_TRCACVR10 = 0x8921, ARM64_SYSREG_TRCACVR11 = 0x8931, ARM64_SYSREG_TRCACVR12 = 0x8941, ARM64_SYSREG_TRCACVR13 = 0x8951, ARM64_SYSREG_TRCACVR14 = 0x8961, ARM64_SYSREG_TRCACVR15 = 0x8971, ARM64_SYSREG_TRCACATR0 = 0x8902, ARM64_SYSREG_TRCACATR1 = 0x8912, ARM64_SYSREG_TRCACATR2 = 0x8922, ARM64_SYSREG_TRCACATR3 = 0x8932, ARM64_SYSREG_TRCACATR4 = 0x8942, ARM64_SYSREG_TRCACATR5 = 0x8952, ARM64_SYSREG_TRCACATR6 = 0x8962, ARM64_SYSREG_TRCACATR7 = 0x8972, ARM64_SYSREG_TRCACATR8 = 0x8903, ARM64_SYSREG_TRCACATR9 = 0x8913, ARM64_SYSREG_TRCACATR10 = 0x8923, ARM64_SYSREG_TRCACATR11 = 0x8933, ARM64_SYSREG_TRCACATR12 = 0x8943, ARM64_SYSREG_TRCACATR13 = 0x8953, ARM64_SYSREG_TRCACATR14 = 0x8963, ARM64_SYSREG_TRCACATR15 = 0x8973, ARM64_SYSREG_TRCDVCVR0 = 0x8904, ARM64_SYSREG_TRCDVCVR1 = 0x8924, ARM64_SYSREG_TRCDVCVR2 = 0x8944, ARM64_SYSREG_TRCDVCVR3 = 0x8964, ARM64_SYSREG_TRCDVCVR4 = 0x8905, ARM64_SYSREG_TRCDVCVR5 = 0x8925, ARM64_SYSREG_TRCDVCVR6 = 0x8945, ARM64_SYSREG_TRCDVCVR7 = 0x8965, ARM64_SYSREG_TRCDVCMR0 = 0x8906, ARM64_SYSREG_TRCDVCMR1 = 0x8926, ARM64_SYSREG_TRCDVCMR2 = 0x8946, ARM64_SYSREG_TRCDVCMR3 = 0x8966, ARM64_SYSREG_TRCDVCMR4 = 0x8907, ARM64_SYSREG_TRCDVCMR5 = 0x8927, ARM64_SYSREG_TRCDVCMR6 = 0x8947, ARM64_SYSREG_TRCDVCMR7 = 0x8967, ARM64_SYSREG_TRCCIDCVR0 = 0x8980, ARM64_SYSREG_TRCCIDCVR1 = 0x8990, ARM64_SYSREG_TRCCIDCVR2 = 0x89A0, ARM64_SYSREG_TRCCIDCVR3 = 0x89B0, ARM64_SYSREG_TRCCIDCVR4 = 0x89C0, ARM64_SYSREG_TRCCIDCVR5 = 0x89D0, ARM64_SYSREG_TRCCIDCVR6 = 0x89E0, ARM64_SYSREG_TRCCIDCVR7 = 0x89F0, ARM64_SYSREG_TRCVMIDCVR0 = 0x8981, ARM64_SYSREG_TRCVMIDCVR1 = 0x8991, ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1, ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1, ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1, ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1, ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1, ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1, ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982, ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A, ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992, ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A, ARM64_SYSREG_TRCITCTRL = 0x8B84, ARM64_SYSREG_TRCCLAIMSET = 0x8BC6, ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE, ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663, ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643, ARM64_SYSREG_ICC_PMR_EL1 = 0xC230, ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664, ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664, ARM64_SYSREG_ICC_SRE_EL1 = 0xC665, ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D, ARM64_SYSREG_ICC_SRE_EL3 = 0xF665, ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666, ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667, ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667, ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668, ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644, ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645, ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646, ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647, ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648, ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649, ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A, ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B, ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640, ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641, ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642, ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643, ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648, ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649, ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A, ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B, ARM64_SYSREG_ICH_HCR_EL2 = 0xE658, ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A, ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F, ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C, ARM64_SYSREG_ICH_LR0_EL2 = 0xE660, ARM64_SYSREG_ICH_LR1_EL2 = 0xE661, ARM64_SYSREG_ICH_LR2_EL2 = 0xE662, ARM64_SYSREG_ICH_LR3_EL2 = 0xE663, ARM64_SYSREG_ICH_LR4_EL2 = 0xE664, ARM64_SYSREG_ICH_LR5_EL2 = 0xE665, ARM64_SYSREG_ICH_LR6_EL2 = 0xE666, ARM64_SYSREG_ICH_LR7_EL2 = 0xE667, ARM64_SYSREG_ICH_LR8_EL2 = 0xE668, ARM64_SYSREG_ICH_LR9_EL2 = 0xE669, ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A, ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B, ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C, ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D, ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E, ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F, ARM64_SYSREG_PAN = 0xC213, ARM64_SYSREG_LORSA_EL1 = 0xC520, ARM64_SYSREG_LOREA_EL1 = 0xC521, ARM64_SYSREG_LORN_EL1 = 0xC522, ARM64_SYSREG_LORC_EL1 = 0xC523, ARM64_SYSREG_TTBR1_EL2 = 0xE101, ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681, ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718, ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A, ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719, ARM64_SYSREG_SCTLR_EL12 = 0xE880, ARM64_SYSREG_CPACR_EL12 = 0xE882, ARM64_SYSREG_TTBR0_EL12 = 0xE900, ARM64_SYSREG_TTBR1_EL12 = 0xE901, ARM64_SYSREG_TCR_EL12 = 0xE902, ARM64_SYSREG_AFSR0_EL12 = 0xEA88, ARM64_SYSREG_AFSR1_EL12 = 0xEA89, ARM64_SYSREG_ESR_EL12 = 0xEA90, ARM64_SYSREG_FAR_EL12 = 0xEB00, ARM64_SYSREG_MAIR_EL12 = 0xED10, ARM64_SYSREG_AMAIR_EL12 = 0xED18, ARM64_SYSREG_VBAR_EL12 = 0xEE00, ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81, ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08, ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10, ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11, ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12, ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18, ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19, ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A, ARM64_SYSREG_SPSR_EL12 = 0xEA00, ARM64_SYSREG_ELR_EL12 = 0xEA01, ARM64_SYSREG_UAO = 0xC214, ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0, ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1, ARM64_SYSREG_PMBSR_EL1 = 0xC4D3, ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7, ARM64_SYSREG_PMSCR_EL2 = 0xE4C8, ARM64_SYSREG_PMSCR_EL12 = 0xECC8, ARM64_SYSREG_PMSCR_EL1 = 0xC4C8, ARM64_SYSREG_PMSICR_EL1 = 0xC4CA, ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB, ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC, ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD, ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE, ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF, ARM64_SYSREG_ERRSELR_EL1 = 0xC299, ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1, ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2, ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3, ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8, ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9, ARM64_SYSREG_DISR_EL1 = 0xC609, ARM64_SYSREG_VDISR_EL2 = 0xE609, ARM64_SYSREG_VSESR_EL2 = 0xE293, ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108, ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109, ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A, ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B, ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110, ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111, ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112, ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113, ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118, ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119, ARM64_SYSREG_VSTCR_EL2 = 0xE132, ARM64_SYSREG_VSTTBR_EL2 = 0xE130, ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720, ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722, ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721, ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728, ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A, ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729, ARM64_SYSREG_SDER32_EL2 = 0xE099, ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5, ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6, ARM64_SYSREG_ERXTS_EL1 = 0xC2AF, ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA, ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB, ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4, ARM64_SYSREG_MPAM0_EL1 = 0xC529, ARM64_SYSREG_MPAM1_EL1 = 0xC528, ARM64_SYSREG_MPAM2_EL2 = 0xE528, ARM64_SYSREG_MPAM3_EL3 = 0xF528, ARM64_SYSREG_MPAM1_EL12 = 0xED28, ARM64_SYSREG_MPAMHCR_EL2 = 0xE520, ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521, ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530, ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531, ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532, ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533, ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534, ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535, ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536, ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537, ARM64_SYSREG_MPAMIDR_EL1 = 0xC524, ARM64_SYSREG_AMCR_EL0 = 0xDE90, ARM64_SYSREG_AMCFGR_EL0 = 0xDE91, ARM64_SYSREG_AMCGCR_EL0 = 0xDE92, ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93, ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94, ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95, ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0, ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1, ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2, ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3, ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0, ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1, ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2, ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3, ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98, ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99, ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0, ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1, ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2, ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3, ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4, ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5, ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6, ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7, ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8, ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9, ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA, ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB, ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC, ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED, ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE, ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF, ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0, ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1, ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2, ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3, ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4, ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5, ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6, ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7, ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8, ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9, ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA, ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB, ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC, ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD, ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE, ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF, ARM64_SYSREG_TRFCR_EL1 = 0xC091, ARM64_SYSREG_TRFCR_EL2 = 0xE091, ARM64_SYSREG_TRFCR_EL12 = 0xE891, ARM64_SYSREG_DIT = 0xDA15, ARM64_SYSREG_VNCR_EL2 = 0xE110, ARM64_SYSREG_ZCR_EL1 = 0xC090, ARM64_SYSREG_ZCR_EL2 = 0xE090, ARM64_SYSREG_ZCR_EL3 = 0xF090, ARM64_SYSREG_ZCR_EL12 = 0xE890, ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90, } arm64_sysreg; /// System PState Field (MSR instruction) typedef enum arm64_pstate { ARM64_PSTATE_INVALID = 0, ARM64_PSTATE_SPSEL = 0x05, ARM64_PSTATE_DAIFSET = 0x1e, ARM64_PSTATE_DAIFCLR = 0x1f, ARM64_PSTATE_PAN = 0x4, ARM64_PSTATE_UAO = 0x3, ARM64_PSTATE_DIT = 0x1a, } arm64_pstate; /// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) typedef enum arm64_vas { ARM64_VAS_INVALID = 0, ARM64_VAS_16B, ARM64_VAS_8B, ARM64_VAS_4B, ARM64_VAS_1B, ARM64_VAS_8H, ARM64_VAS_4H, ARM64_VAS_2H, ARM64_VAS_1H, ARM64_VAS_4S, ARM64_VAS_2S, ARM64_VAS_1S, ARM64_VAS_2D, ARM64_VAS_1D, ARM64_VAS_1Q, } arm64_vas; /// Memory barrier operands typedef enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0, ARM64_BARRIER_OSHLD = 0x1, ARM64_BARRIER_OSHST = 0x2, ARM64_BARRIER_OSH = 0x3, ARM64_BARRIER_NSHLD = 0x5, ARM64_BARRIER_NSHST = 0x6, ARM64_BARRIER_NSH = 0x7, ARM64_BARRIER_ISHLD = 0x9, ARM64_BARRIER_ISHST = 0xa, ARM64_BARRIER_ISH = 0xb, ARM64_BARRIER_LD = 0xd, ARM64_BARRIER_ST = 0xe, ARM64_BARRIER_SY = 0xf } arm64_barrier_op; /// Operand type for instruction's operands typedef enum arm64_op_type { ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). ARM64_OP_REG, ///< = CS_OP_REG (Register operand). ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand). ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand). ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand). ARM64_OP_CIMM = 64, ///< C-Immediate ARM64_OP_REG_MRS, ///< MRS register operand. ARM64_OP_REG_MSR, ///< MSR register operand. ARM64_OP_PSTATE, ///< PState operand. ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions. ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM). ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions). } arm64_op_type; /// TLBI operations typedef enum arm64_tlbi_op { ARM64_TLBI_INVALID = 0, ARM64_TLBI_IPAS2E1IS, ARM64_TLBI_IPAS2LE1IS, ARM64_TLBI_VMALLE1IS, ARM64_TLBI_ALLE2IS, ARM64_TLBI_ALLE3IS, ARM64_TLBI_VAE1IS, ARM64_TLBI_VAE2IS, ARM64_TLBI_VAE3IS, ARM64_TLBI_ASIDE1IS, ARM64_TLBI_VAAE1IS, ARM64_TLBI_ALLE1IS, ARM64_TLBI_VALE1IS, ARM64_TLBI_VALE2IS, ARM64_TLBI_VALE3IS, ARM64_TLBI_VMALLS12E1IS, ARM64_TLBI_VAALE1IS, ARM64_TLBI_IPAS2E1, ARM64_TLBI_IPAS2LE1, ARM64_TLBI_VMALLE1, ARM64_TLBI_ALLE2, ARM64_TLBI_ALLE3, ARM64_TLBI_VAE1, ARM64_TLBI_VAE2, ARM64_TLBI_VAE3, ARM64_TLBI_ASIDE1, ARM64_TLBI_VAAE1, ARM64_TLBI_ALLE1, ARM64_TLBI_VALE1, ARM64_TLBI_VALE2, ARM64_TLBI_VALE3, ARM64_TLBI_VMALLS12E1, ARM64_TLBI_VAALE1, ARM64_TLBI_VMALLE1OS, ARM64_TLBI_VAE1OS, ARM64_TLBI_ASIDE1OS, ARM64_TLBI_VAAE1OS, ARM64_TLBI_VALE1OS, ARM64_TLBI_VAALE1OS, ARM64_TLBI_IPAS2E1OS, ARM64_TLBI_IPAS2LE1OS, ARM64_TLBI_VAE2OS, ARM64_TLBI_VALE2OS, ARM64_TLBI_VMALLS12E1OS, ARM64_TLBI_VAE3OS, ARM64_TLBI_VALE3OS, ARM64_TLBI_ALLE2OS, ARM64_TLBI_ALLE1OS, ARM64_TLBI_ALLE3OS, ARM64_TLBI_RVAE1, ARM64_TLBI_RVAAE1, ARM64_TLBI_RVALE1, ARM64_TLBI_RVAALE1, ARM64_TLBI_RVAE1IS, ARM64_TLBI_RVAAE1IS, ARM64_TLBI_RVALE1IS, ARM64_TLBI_RVAALE1IS, ARM64_TLBI_RVAE1OS, ARM64_TLBI_RVAAE1OS, ARM64_TLBI_RVALE1OS, ARM64_TLBI_RVAALE1OS, ARM64_TLBI_RIPAS2E1IS, ARM64_TLBI_RIPAS2LE1IS, ARM64_TLBI_RIPAS2E1, ARM64_TLBI_RIPAS2LE1, ARM64_TLBI_RIPAS2E1OS, ARM64_TLBI_RIPAS2LE1OS, ARM64_TLBI_RVAE2, ARM64_TLBI_RVALE2, ARM64_TLBI_RVAE2IS, ARM64_TLBI_RVALE2IS, ARM64_TLBI_RVAE2OS, ARM64_TLBI_RVALE2OS, ARM64_TLBI_RVAE3, ARM64_TLBI_RVALE3, ARM64_TLBI_RVAE3IS, ARM64_TLBI_RVALE3IS, ARM64_TLBI_RVAE3OS, ARM64_TLBI_RVALE3OS, } arm64_tlbi_op; /// AT operations typedef enum arm64_at_op { ARM64_AT_S1E1R, ARM64_AT_S1E2R, ARM64_AT_S1E3R, ARM64_AT_S1E1W, ARM64_AT_S1E2W, ARM64_AT_S1E3W, ARM64_AT_S1E0R, ARM64_AT_S1E0W, ARM64_AT_S12E1R, ARM64_AT_S12E1W, ARM64_AT_S12E0R, ARM64_AT_S12E0W, ARM64_AT_S1E1RP, ARM64_AT_S1E1WP, } arm64_at_op; /// DC operations typedef enum arm64_dc_op { ARM64_DC_INVALID = 0, ARM64_DC_ZVA, ARM64_DC_IVAC, ARM64_DC_ISW, ARM64_DC_CVAC, ARM64_DC_CSW, ARM64_DC_CVAU, ARM64_DC_CIVAC, ARM64_DC_CISW, ARM64_DC_CVAP, } arm64_dc_op; /// IC operations typedef enum arm64_ic_op { ARM64_IC_INVALID = 0, ARM64_IC_IALLUIS, ARM64_IC_IALLU, ARM64_IC_IVAU, } arm64_ic_op; /// Prefetch operations (PRFM) typedef enum arm64_prefetch_op { ARM64_PRFM_INVALID = 0, ARM64_PRFM_PLDL1KEEP = 0x00 + 1, ARM64_PRFM_PLDL1STRM = 0x01 + 1, ARM64_PRFM_PLDL2KEEP = 0x02 + 1, ARM64_PRFM_PLDL2STRM = 0x03 + 1, ARM64_PRFM_PLDL3KEEP = 0x04 + 1, ARM64_PRFM_PLDL3STRM = 0x05 + 1, ARM64_PRFM_PLIL1KEEP = 0x08 + 1, ARM64_PRFM_PLIL1STRM = 0x09 + 1, ARM64_PRFM_PLIL2KEEP = 0x0a + 1, ARM64_PRFM_PLIL2STRM = 0x0b + 1, ARM64_PRFM_PLIL3KEEP = 0x0c + 1, ARM64_PRFM_PLIL3STRM = 0x0d + 1, ARM64_PRFM_PSTL1KEEP = 0x10 + 1, ARM64_PRFM_PSTL1STRM = 0x11 + 1, ARM64_PRFM_PSTL2KEEP = 0x12 + 1, ARM64_PRFM_PSTL2STRM = 0x13 + 1, ARM64_PRFM_PSTL3KEEP = 0x14 + 1, ARM64_PRFM_PSTL3STRM = 0x15 + 1, } arm64_prefetch_op; /// ARM64 registers typedef enum arm64_reg { ARM64_REG_INVALID = 0, ARM64_REG_FFR = 1, ARM64_REG_FP = 2, ARM64_REG_LR = 3, ARM64_REG_NZCV = 4, ARM64_REG_SP = 5, ARM64_REG_WSP = 6, ARM64_REG_WZR = 7, ARM64_REG_XZR = 8, ARM64_REG_B0 = 9, ARM64_REG_B1 = 10, ARM64_REG_B2 = 11, ARM64_REG_B3 = 12, ARM64_REG_B4 = 13, ARM64_REG_B5 = 14, ARM64_REG_B6 = 15, ARM64_REG_B7 = 16, ARM64_REG_B8 = 17, ARM64_REG_B9 = 18, ARM64_REG_B10 = 19, ARM64_REG_B11 = 20, ARM64_REG_B12 = 21, ARM64_REG_B13 = 22, ARM64_REG_B14 = 23, ARM64_REG_B15 = 24, ARM64_REG_B16 = 25, ARM64_REG_B17 = 26, ARM64_REG_B18 = 27, ARM64_REG_B19 = 28, ARM64_REG_B20 = 29, ARM64_REG_B21 = 30, ARM64_REG_B22 = 31, ARM64_REG_B23 = 32, ARM64_REG_B24 = 33, ARM64_REG_B25 = 34, ARM64_REG_B26 = 35, ARM64_REG_B27 = 36, ARM64_REG_B28 = 37, ARM64_REG_B29 = 38, ARM64_REG_B30 = 39, ARM64_REG_B31 = 40, ARM64_REG_D0 = 41, ARM64_REG_D1 = 42, ARM64_REG_D2 = 43, ARM64_REG_D3 = 44, ARM64_REG_D4 = 45, ARM64_REG_D5 = 46, ARM64_REG_D6 = 47, ARM64_REG_D7 = 48, ARM64_REG_D8 = 49, ARM64_REG_D9 = 50, ARM64_REG_D10 = 51, ARM64_REG_D11 = 52, ARM64_REG_D12 = 53, ARM64_REG_D13 = 54, ARM64_REG_D14 = 55, ARM64_REG_D15 = 56, ARM64_REG_D16 = 57, ARM64_REG_D17 = 58, ARM64_REG_D18 = 59, ARM64_REG_D19 = 60, ARM64_REG_D20 = 61, ARM64_REG_D21 = 62, ARM64_REG_D22 = 63, ARM64_REG_D23 = 64, ARM64_REG_D24 = 65, ARM64_REG_D25 = 66, ARM64_REG_D26 = 67, ARM64_REG_D27 = 68, ARM64_REG_D28 = 69, ARM64_REG_D29 = 70, ARM64_REG_D30 = 71, ARM64_REG_D31 = 72, ARM64_REG_H0 = 73, ARM64_REG_H1 = 74, ARM64_REG_H2 = 75, ARM64_REG_H3 = 76, ARM64_REG_H4 = 77, ARM64_REG_H5 = 78, ARM64_REG_H6 = 79, ARM64_REG_H7 = 80, ARM64_REG_H8 = 81, ARM64_REG_H9 = 82, ARM64_REG_H10 = 83, ARM64_REG_H11 = 84, ARM64_REG_H12 = 85, ARM64_REG_H13 = 86, ARM64_REG_H14 = 87, ARM64_REG_H15 = 88, ARM64_REG_H16 = 89, ARM64_REG_H17 = 90, ARM64_REG_H18 = 91, ARM64_REG_H19 = 92, ARM64_REG_H20 = 93, ARM64_REG_H21 = 94, ARM64_REG_H22 = 95, ARM64_REG_H23 = 96, ARM64_REG_H24 = 97, ARM64_REG_H25 = 98, ARM64_REG_H26 = 99, ARM64_REG_H27 = 100, ARM64_REG_H28 = 101, ARM64_REG_H29 = 102, ARM64_REG_H30 = 103, ARM64_REG_H31 = 104, ARM64_REG_P0 = 105, ARM64_REG_P1 = 106, ARM64_REG_P2 = 107, ARM64_REG_P3 = 108, ARM64_REG_P4 = 109, ARM64_REG_P5 = 110, ARM64_REG_P6 = 111, ARM64_REG_P7 = 112, ARM64_REG_P8 = 113, ARM64_REG_P9 = 114, ARM64_REG_P10 = 115, ARM64_REG_P11 = 116, ARM64_REG_P12 = 117, ARM64_REG_P13 = 118, ARM64_REG_P14 = 119, ARM64_REG_P15 = 120, ARM64_REG_Q0 = 121, ARM64_REG_Q1 = 122, ARM64_REG_Q2 = 123, ARM64_REG_Q3 = 124, ARM64_REG_Q4 = 125, ARM64_REG_Q5 = 126, ARM64_REG_Q6 = 127, ARM64_REG_Q7 = 128, ARM64_REG_Q8 = 129, ARM64_REG_Q9 = 130, ARM64_REG_Q10 = 131, ARM64_REG_Q11 = 132, ARM64_REG_Q12 = 133, ARM64_REG_Q13 = 134, ARM64_REG_Q14 = 135, ARM64_REG_Q15 = 136, ARM64_REG_Q16 = 137, ARM64_REG_Q17 = 138, ARM64_REG_Q18 = 139, ARM64_REG_Q19 = 140, ARM64_REG_Q20 = 141, ARM64_REG_Q21 = 142, ARM64_REG_Q22 = 143, ARM64_REG_Q23 = 144, ARM64_REG_Q24 = 145, ARM64_REG_Q25 = 146, ARM64_REG_Q26 = 147, ARM64_REG_Q27 = 148, ARM64_REG_Q28 = 149, ARM64_REG_Q29 = 150, ARM64_REG_Q30 = 151, ARM64_REG_Q31 = 152, ARM64_REG_S0 = 153, ARM64_REG_S1 = 154, ARM64_REG_S2 = 155, ARM64_REG_S3 = 156, ARM64_REG_S4 = 157, ARM64_REG_S5 = 158, ARM64_REG_S6 = 159, ARM64_REG_S7 = 160, ARM64_REG_S8 = 161, ARM64_REG_S9 = 162, ARM64_REG_S10 = 163, ARM64_REG_S11 = 164, ARM64_REG_S12 = 165, ARM64_REG_S13 = 166, ARM64_REG_S14 = 167, ARM64_REG_S15 = 168, ARM64_REG_S16 = 169, ARM64_REG_S17 = 170, ARM64_REG_S18 = 171, ARM64_REG_S19 = 172, ARM64_REG_S20 = 173, ARM64_REG_S21 = 174, ARM64_REG_S22 = 175, ARM64_REG_S23 = 176, ARM64_REG_S24 = 177, ARM64_REG_S25 = 178, ARM64_REG_S26 = 179, ARM64_REG_S27 = 180, ARM64_REG_S28 = 181, ARM64_REG_S29 = 182, ARM64_REG_S30 = 183, ARM64_REG_S31 = 184, ARM64_REG_W0 = 185, ARM64_REG_W1 = 186, ARM64_REG_W2 = 187, ARM64_REG_W3 = 188, ARM64_REG_W4 = 189, ARM64_REG_W5 = 190, ARM64_REG_W6 = 191, ARM64_REG_W7 = 192, ARM64_REG_W8 = 193, ARM64_REG_W9 = 194, ARM64_REG_W10 = 195, ARM64_REG_W11 = 196, ARM64_REG_W12 = 197, ARM64_REG_W13 = 198, ARM64_REG_W14 = 199, ARM64_REG_W15 = 200, ARM64_REG_W16 = 201, ARM64_REG_W17 = 202, ARM64_REG_W18 = 203, ARM64_REG_W19 = 204, ARM64_REG_W20 = 205, ARM64_REG_W21 = 206, ARM64_REG_W22 = 207, ARM64_REG_W23 = 208, ARM64_REG_W24 = 209, ARM64_REG_W25 = 210, ARM64_REG_W26 = 211, ARM64_REG_W27 = 212, ARM64_REG_W28 = 213, ARM64_REG_W29 = 214, ARM64_REG_W30 = 215, ARM64_REG_X0 = 216, ARM64_REG_X1 = 217, ARM64_REG_X2 = 218, ARM64_REG_X3 = 219, ARM64_REG_X4 = 220, ARM64_REG_X5 = 221, ARM64_REG_X6 = 222, ARM64_REG_X7 = 223, ARM64_REG_X8 = 224, ARM64_REG_X9 = 225, ARM64_REG_X10 = 226, ARM64_REG_X11 = 227, ARM64_REG_X12 = 228, ARM64_REG_X13 = 229, ARM64_REG_X14 = 230, ARM64_REG_X15 = 231, ARM64_REG_X16 = 232, ARM64_REG_X17 = 233, ARM64_REG_X18 = 234, ARM64_REG_X19 = 235, ARM64_REG_X20 = 236, ARM64_REG_X21 = 237, ARM64_REG_X22 = 238, ARM64_REG_X23 = 239, ARM64_REG_X24 = 240, ARM64_REG_X25 = 241, ARM64_REG_X26 = 242, ARM64_REG_X27 = 243, ARM64_REG_X28 = 244, ARM64_REG_Z0 = 245, ARM64_REG_Z1 = 246, ARM64_REG_Z2 = 247, ARM64_REG_Z3 = 248, ARM64_REG_Z4 = 249, ARM64_REG_Z5 = 250, ARM64_REG_Z6 = 251, ARM64_REG_Z7 = 252, ARM64_REG_Z8 = 253, ARM64_REG_Z9 = 254, ARM64_REG_Z10 = 255, ARM64_REG_Z11 = 256, ARM64_REG_Z12 = 257, ARM64_REG_Z13 = 258, ARM64_REG_Z14 = 259, ARM64_REG_Z15 = 260, ARM64_REG_Z16 = 261, ARM64_REG_Z17 = 262, ARM64_REG_Z18 = 263, ARM64_REG_Z19 = 264, ARM64_REG_Z20 = 265, ARM64_REG_Z21 = 266, ARM64_REG_Z22 = 267, ARM64_REG_Z23 = 268, ARM64_REG_Z24 = 269, ARM64_REG_Z25 = 270, ARM64_REG_Z26 = 271, ARM64_REG_Z27 = 272, ARM64_REG_Z28 = 273, ARM64_REG_Z29 = 274, ARM64_REG_Z30 = 275, ARM64_REG_Z31 = 276, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_ENDING, // <-- mark the end of the list of registers // alias registers ARM64_REG_IP0 = ARM64_REG_X16, ARM64_REG_IP1 = ARM64_REG_X17, ARM64_REG_X29 = ARM64_REG_FP, ARM64_REG_X30 = ARM64_REG_LR, } arm64_reg; /// Instruction's operand referring to memory /// This is associated with ARM64_OP_MEM operand type above typedef struct arm64_op_mem { arm64_reg base; ///< base register arm64_reg index; ///< index register int32_t disp; ///< displacement/offset value } arm64_op_mem; /// Instruction operand typedef struct cs_arm64_op { int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) arm64_vas vas; ///< Vector Arrangement Specifier struct { arm64_shifter type; ///< shifter type of this operand unsigned int value; ///< shifter value of this operand } shift; arm64_extender ext; ///< extender type of this operand arm64_op_type type; ///< operand type union { arm64_reg reg; ///< register value for REG operand int64_t imm; ///< immediate value, or index for C-IMM or IMM operand double fp; ///< floating point value for FP operand arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand arm64_pstate pstate; ///< PState field of MSR instruction. unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op) arm64_prefetch_op prefetch; ///< PRFM operation. arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions). }; /// How is this operand accessed? (READ, WRITE or READ|WRITE) /// This field is combined of cs_ac_type. /// NOTE: this field is irrelevant if engine is compiled in DIET mode. uint8_t access; } cs_arm64_op; /// Instruction structure typedef struct cs_arm64 { arm64_cc cc; ///< conditional code for this insn bool update_flags; ///< does this insn update flags? bool writeback; ///< does this insn request writeback? 'True' means 'yes' /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_arm64_op operands[8]; ///< operands for this instruction. } cs_arm64; /// ARM64 instruction typedef enum arm64_insn { ARM64_INS_INVALID = 0, ARM64_INS_ABS, ARM64_INS_ADC, ARM64_INS_ADCS, ARM64_INS_ADD, ARM64_INS_ADDHN, ARM64_INS_ADDHN2, ARM64_INS_ADDP, ARM64_INS_ADDPL, ARM64_INS_ADDS, ARM64_INS_ADDV, ARM64_INS_ADDVL, ARM64_INS_ADR, ARM64_INS_ADRP, ARM64_INS_AESD, ARM64_INS_AESE, ARM64_INS_AESIMC, ARM64_INS_AESMC, ARM64_INS_AND, ARM64_INS_ANDS, ARM64_INS_ANDV, ARM64_INS_ASR, ARM64_INS_ASRD, ARM64_INS_ASRR, ARM64_INS_ASRV, ARM64_INS_AUTDA, ARM64_INS_AUTDB, ARM64_INS_AUTDZA, ARM64_INS_AUTDZB, ARM64_INS_AUTIA, ARM64_INS_AUTIA1716, ARM64_INS_AUTIASP, ARM64_INS_AUTIAZ, ARM64_INS_AUTIB, ARM64_INS_AUTIB1716, ARM64_INS_AUTIBSP, ARM64_INS_AUTIBZ, ARM64_INS_AUTIZA, ARM64_INS_AUTIZB, ARM64_INS_B, ARM64_INS_BCAX, ARM64_INS_BFM, ARM64_INS_BIC, ARM64_INS_BICS, ARM64_INS_BIF, ARM64_INS_BIT, ARM64_INS_BL, ARM64_INS_BLR, ARM64_INS_BLRAA, ARM64_INS_BLRAAZ, ARM64_INS_BLRAB, ARM64_INS_BLRABZ, ARM64_INS_BR, ARM64_INS_BRAA, ARM64_INS_BRAAZ, ARM64_INS_BRAB, ARM64_INS_BRABZ, ARM64_INS_BRK, ARM64_INS_BRKA, ARM64_INS_BRKAS, ARM64_INS_BRKB, ARM64_INS_BRKBS, ARM64_INS_BRKN, ARM64_INS_BRKNS, ARM64_INS_BRKPA, ARM64_INS_BRKPAS, ARM64_INS_BRKPB, ARM64_INS_BRKPBS, ARM64_INS_BSL, ARM64_INS_CAS, ARM64_INS_CASA, ARM64_INS_CASAB, ARM64_INS_CASAH, ARM64_INS_CASAL, ARM64_INS_CASALB, ARM64_INS_CASALH, ARM64_INS_CASB, ARM64_INS_CASH, ARM64_INS_CASL, ARM64_INS_CASLB, ARM64_INS_CASLH, ARM64_INS_CASP, ARM64_INS_CASPA, ARM64_INS_CASPAL, ARM64_INS_CASPL, ARM64_INS_CBNZ, ARM64_INS_CBZ, ARM64_INS_CCMN, ARM64_INS_CCMP, ARM64_INS_CFINV, ARM64_INS_CINC, ARM64_INS_CINV, ARM64_INS_CLASTA, ARM64_INS_CLASTB, ARM64_INS_CLREX, ARM64_INS_CLS, ARM64_INS_CLZ, ARM64_INS_CMEQ, ARM64_INS_CMGE, ARM64_INS_CMGT, ARM64_INS_CMHI, ARM64_INS_CMHS, ARM64_INS_CMLE, ARM64_INS_CMLO, ARM64_INS_CMLS, ARM64_INS_CMLT, ARM64_INS_CMN, ARM64_INS_CMP, ARM64_INS_CMPEQ, ARM64_INS_CMPGE, ARM64_INS_CMPGT, ARM64_INS_CMPHI, ARM64_INS_CMPHS, ARM64_INS_CMPLE, ARM64_INS_CMPLO, ARM64_INS_CMPLS, ARM64_INS_CMPLT, ARM64_INS_CMPNE, ARM64_INS_CMTST, ARM64_INS_CNEG, ARM64_INS_CNOT, ARM64_INS_CNT, ARM64_INS_CNTB, ARM64_INS_CNTD, ARM64_INS_CNTH, ARM64_INS_CNTP, ARM64_INS_CNTW, ARM64_INS_COMPACT, ARM64_INS_CPY, ARM64_INS_CRC32B, ARM64_INS_CRC32CB, ARM64_INS_CRC32CH, ARM64_INS_CRC32CW, ARM64_INS_CRC32CX, ARM64_INS_CRC32H, ARM64_INS_CRC32W, ARM64_INS_CRC32X, ARM64_INS_CSDB, ARM64_INS_CSEL, ARM64_INS_CSET, ARM64_INS_CSETM, ARM64_INS_CSINC, ARM64_INS_CSINV, ARM64_INS_CSNEG, ARM64_INS_CTERMEQ, ARM64_INS_CTERMNE, ARM64_INS_DCPS1, ARM64_INS_DCPS2, ARM64_INS_DCPS3, ARM64_INS_DECB, ARM64_INS_DECD, ARM64_INS_DECH, ARM64_INS_DECP, ARM64_INS_DECW, ARM64_INS_DMB, ARM64_INS_DRPS, ARM64_INS_DSB, ARM64_INS_DUP, ARM64_INS_DUPM, ARM64_INS_EON, ARM64_INS_EOR, ARM64_INS_EOR3, ARM64_INS_EORS, ARM64_INS_EORV, ARM64_INS_ERET, ARM64_INS_ERETAA, ARM64_INS_ERETAB, ARM64_INS_ESB, ARM64_INS_EXT, ARM64_INS_EXTR, ARM64_INS_FABD, ARM64_INS_FABS, ARM64_INS_FACGE, ARM64_INS_FACGT, ARM64_INS_FACLE, ARM64_INS_FACLT, ARM64_INS_FADD, ARM64_INS_FADDA, ARM64_INS_FADDP, ARM64_INS_FADDV, ARM64_INS_FCADD, ARM64_INS_FCCMP, ARM64_INS_FCCMPE, ARM64_INS_FCMEQ, ARM64_INS_FCMGE, ARM64_INS_FCMGT, ARM64_INS_FCMLA, ARM64_INS_FCMLE, ARM64_INS_FCMLT, ARM64_INS_FCMNE, ARM64_INS_FCMP, ARM64_INS_FCMPE, ARM64_INS_FCMUO, ARM64_INS_FCPY, ARM64_INS_FCSEL, ARM64_INS_FCVT, ARM64_INS_FCVTAS, ARM64_INS_FCVTAU, ARM64_INS_FCVTL, ARM64_INS_FCVTL2, ARM64_INS_FCVTMS, ARM64_INS_FCVTMU, ARM64_INS_FCVTN, ARM64_INS_FCVTN2, ARM64_INS_FCVTNS, ARM64_INS_FCVTNU, ARM64_INS_FCVTPS, ARM64_INS_FCVTPU, ARM64_INS_FCVTXN, ARM64_INS_FCVTXN2, ARM64_INS_FCVTZS, ARM64_INS_FCVTZU, ARM64_INS_FDIV, ARM64_INS_FDIVR, ARM64_INS_FDUP, ARM64_INS_FEXPA, ARM64_INS_FJCVTZS, ARM64_INS_FMAD, ARM64_INS_FMADD, ARM64_INS_FMAX, ARM64_INS_FMAXNM, ARM64_INS_FMAXNMP, ARM64_INS_FMAXNMV, ARM64_INS_FMAXP, ARM64_INS_FMAXV, ARM64_INS_FMIN, ARM64_INS_FMINNM, ARM64_INS_FMINNMP, ARM64_INS_FMINNMV, ARM64_INS_FMINP, ARM64_INS_FMINV, ARM64_INS_FMLA, ARM64_INS_FMLS, ARM64_INS_FMOV, ARM64_INS_FMSB, ARM64_INS_FMSUB, ARM64_INS_FMUL, ARM64_INS_FMULX, ARM64_INS_FNEG, ARM64_INS_FNMAD, ARM64_INS_FNMADD, ARM64_INS_FNMLA, ARM64_INS_FNMLS, ARM64_INS_FNMSB, ARM64_INS_FNMSUB, ARM64_INS_FNMUL, ARM64_INS_FRECPE, ARM64_INS_FRECPS, ARM64_INS_FRECPX, ARM64_INS_FRINTA, ARM64_INS_FRINTI, ARM64_INS_FRINTM, ARM64_INS_FRINTN, ARM64_INS_FRINTP, ARM64_INS_FRINTX, ARM64_INS_FRINTZ, ARM64_INS_FRSQRTE, ARM64_INS_FRSQRTS, ARM64_INS_FSCALE, ARM64_INS_FSQRT, ARM64_INS_FSUB, ARM64_INS_FSUBR, ARM64_INS_FTMAD, ARM64_INS_FTSMUL, ARM64_INS_FTSSEL, ARM64_INS_HINT, ARM64_INS_HLT, ARM64_INS_HVC, ARM64_INS_INCB, ARM64_INS_INCD, ARM64_INS_INCH, ARM64_INS_INCP, ARM64_INS_INCW, ARM64_INS_INDEX, ARM64_INS_INS, ARM64_INS_INSR, ARM64_INS_ISB, ARM64_INS_LASTA, ARM64_INS_LASTB, ARM64_INS_LD1, ARM64_INS_LD1B, ARM64_INS_LD1D, ARM64_INS_LD1H, ARM64_INS_LD1R, ARM64_INS_LD1RB, ARM64_INS_LD1RD, ARM64_INS_LD1RH, ARM64_INS_LD1RQB, ARM64_INS_LD1RQD, ARM64_INS_LD1RQH, ARM64_INS_LD1RQW, ARM64_INS_LD1RSB, ARM64_INS_LD1RSH, ARM64_INS_LD1RSW, ARM64_INS_LD1RW, ARM64_INS_LD1SB, ARM64_INS_LD1SH, ARM64_INS_LD1SW, ARM64_INS_LD1W, ARM64_INS_LD2, ARM64_INS_LD2B, ARM64_INS_LD2D, ARM64_INS_LD2H, ARM64_INS_LD2R, ARM64_INS_LD2W, ARM64_INS_LD3, ARM64_INS_LD3B, ARM64_INS_LD3D, ARM64_INS_LD3H, ARM64_INS_LD3R, ARM64_INS_LD3W, ARM64_INS_LD4, ARM64_INS_LD4B, ARM64_INS_LD4D, ARM64_INS_LD4H, ARM64_INS_LD4R, ARM64_INS_LD4W, ARM64_INS_LDADD, ARM64_INS_LDADDA, ARM64_INS_LDADDAB, ARM64_INS_LDADDAH, ARM64_INS_LDADDAL, ARM64_INS_LDADDALB, ARM64_INS_LDADDALH, ARM64_INS_LDADDB, ARM64_INS_LDADDH, ARM64_INS_LDADDL, ARM64_INS_LDADDLB, ARM64_INS_LDADDLH, ARM64_INS_LDAPR, ARM64_INS_LDAPRB, ARM64_INS_LDAPRH, ARM64_INS_LDAPUR, ARM64_INS_LDAPURB, ARM64_INS_LDAPURH, ARM64_INS_LDAPURSB, ARM64_INS_LDAPURSH, ARM64_INS_LDAPURSW, ARM64_INS_LDAR, ARM64_INS_LDARB, ARM64_INS_LDARH, ARM64_INS_LDAXP, ARM64_INS_LDAXR, ARM64_INS_LDAXRB, ARM64_INS_LDAXRH, ARM64_INS_LDCLR, ARM64_INS_LDCLRA, ARM64_INS_LDCLRAB, ARM64_INS_LDCLRAH, ARM64_INS_LDCLRAL, ARM64_INS_LDCLRALB, ARM64_INS_LDCLRALH, ARM64_INS_LDCLRB, ARM64_INS_LDCLRH, ARM64_INS_LDCLRL, ARM64_INS_LDCLRLB, ARM64_INS_LDCLRLH, ARM64_INS_LDEOR, ARM64_INS_LDEORA, ARM64_INS_LDEORAB, ARM64_INS_LDEORAH, ARM64_INS_LDEORAL, ARM64_INS_LDEORALB, ARM64_INS_LDEORALH, ARM64_INS_LDEORB, ARM64_INS_LDEORH, ARM64_INS_LDEORL, ARM64_INS_LDEORLB, ARM64_INS_LDEORLH, ARM64_INS_LDFF1B, ARM64_INS_LDFF1D, ARM64_INS_LDFF1H, ARM64_INS_LDFF1SB, ARM64_INS_LDFF1SH, ARM64_INS_LDFF1SW, ARM64_INS_LDFF1W, ARM64_INS_LDLAR, ARM64_INS_LDLARB, ARM64_INS_LDLARH, ARM64_INS_LDNF1B, ARM64_INS_LDNF1D, ARM64_INS_LDNF1H, ARM64_INS_LDNF1SB, ARM64_INS_LDNF1SH, ARM64_INS_LDNF1SW, ARM64_INS_LDNF1W, ARM64_INS_LDNP, ARM64_INS_LDNT1B, ARM64_INS_LDNT1D, ARM64_INS_LDNT1H, ARM64_INS_LDNT1W, ARM64_INS_LDP, ARM64_INS_LDPSW, ARM64_INS_LDR, ARM64_INS_LDRAA, ARM64_INS_LDRAB, ARM64_INS_LDRB, ARM64_INS_LDRH, ARM64_INS_LDRSB, ARM64_INS_LDRSH, ARM64_INS_LDRSW, ARM64_INS_LDSET, ARM64_INS_LDSETA, ARM64_INS_LDSETAB, ARM64_INS_LDSETAH, ARM64_INS_LDSETAL, ARM64_INS_LDSETALB, ARM64_INS_LDSETALH, ARM64_INS_LDSETB, ARM64_INS_LDSETH, ARM64_INS_LDSETL, ARM64_INS_LDSETLB, ARM64_INS_LDSETLH, ARM64_INS_LDSMAX, ARM64_INS_LDSMAXA, ARM64_INS_LDSMAXAB, ARM64_INS_LDSMAXAH, ARM64_INS_LDSMAXAL, ARM64_INS_LDSMAXALB, ARM64_INS_LDSMAXALH, ARM64_INS_LDSMAXB, ARM64_INS_LDSMAXH, ARM64_INS_LDSMAXL, ARM64_INS_LDSMAXLB, ARM64_INS_LDSMAXLH, ARM64_INS_LDSMIN, ARM64_INS_LDSMINA, ARM64_INS_LDSMINAB, ARM64_INS_LDSMINAH, ARM64_INS_LDSMINAL, ARM64_INS_LDSMINALB, ARM64_INS_LDSMINALH, ARM64_INS_LDSMINB, ARM64_INS_LDSMINH, ARM64_INS_LDSMINL, ARM64_INS_LDSMINLB, ARM64_INS_LDSMINLH, ARM64_INS_LDTR, ARM64_INS_LDTRB, ARM64_INS_LDTRH, ARM64_INS_LDTRSB, ARM64_INS_LDTRSH, ARM64_INS_LDTRSW, ARM64_INS_LDUMAX, ARM64_INS_LDUMAXA, ARM64_INS_LDUMAXAB, ARM64_INS_LDUMAXAH, ARM64_INS_LDUMAXAL, ARM64_INS_LDUMAXALB, ARM64_INS_LDUMAXALH, ARM64_INS_LDUMAXB, ARM64_INS_LDUMAXH, ARM64_INS_LDUMAXL, ARM64_INS_LDUMAXLB, ARM64_INS_LDUMAXLH, ARM64_INS_LDUMIN, ARM64_INS_LDUMINA, ARM64_INS_LDUMINAB, ARM64_INS_LDUMINAH, ARM64_INS_LDUMINAL, ARM64_INS_LDUMINALB, ARM64_INS_LDUMINALH, ARM64_INS_LDUMINB, ARM64_INS_LDUMINH, ARM64_INS_LDUMINL, ARM64_INS_LDUMINLB, ARM64_INS_LDUMINLH, ARM64_INS_LDUR, ARM64_INS_LDURB, ARM64_INS_LDURH, ARM64_INS_LDURSB, ARM64_INS_LDURSH, ARM64_INS_LDURSW, ARM64_INS_LDXP, ARM64_INS_LDXR, ARM64_INS_LDXRB, ARM64_INS_LDXRH, ARM64_INS_LSL, ARM64_INS_LSLR, ARM64_INS_LSLV, ARM64_INS_LSR, ARM64_INS_LSRR, ARM64_INS_LSRV, ARM64_INS_MAD, ARM64_INS_MADD, ARM64_INS_MLA, ARM64_INS_MLS, ARM64_INS_MNEG, ARM64_INS_MOV, ARM64_INS_MOVI, ARM64_INS_MOVK, ARM64_INS_MOVN, ARM64_INS_MOVPRFX, ARM64_INS_MOVS, ARM64_INS_MOVZ, ARM64_INS_MRS, ARM64_INS_MSB, ARM64_INS_MSR, ARM64_INS_MSUB, ARM64_INS_MUL, ARM64_INS_MVN, ARM64_INS_MVNI, ARM64_INS_NAND, ARM64_INS_NANDS, ARM64_INS_NEG, ARM64_INS_NEGS, ARM64_INS_NGC, ARM64_INS_NGCS, ARM64_INS_NOP, ARM64_INS_NOR, ARM64_INS_NORS, ARM64_INS_NOT, ARM64_INS_NOTS, ARM64_INS_ORN, ARM64_INS_ORNS, ARM64_INS_ORR, ARM64_INS_ORRS, ARM64_INS_ORV, ARM64_INS_PACDA, ARM64_INS_PACDB, ARM64_INS_PACDZA, ARM64_INS_PACDZB, ARM64_INS_PACGA, ARM64_INS_PACIA, ARM64_INS_PACIA1716, ARM64_INS_PACIASP, ARM64_INS_PACIAZ, ARM64_INS_PACIB, ARM64_INS_PACIB1716, ARM64_INS_PACIBSP, ARM64_INS_PACIBZ, ARM64_INS_PACIZA, ARM64_INS_PACIZB, ARM64_INS_PFALSE, ARM64_INS_PFIRST, ARM64_INS_PMUL, ARM64_INS_PMULL, ARM64_INS_PMULL2, ARM64_INS_PNEXT, ARM64_INS_PRFB, ARM64_INS_PRFD, ARM64_INS_PRFH, ARM64_INS_PRFM, ARM64_INS_PRFUM, ARM64_INS_PRFW, ARM64_INS_PSB, ARM64_INS_PTEST, ARM64_INS_PTRUE, ARM64_INS_PTRUES, ARM64_INS_PUNPKHI, ARM64_INS_PUNPKLO, ARM64_INS_RADDHN, ARM64_INS_RADDHN2, ARM64_INS_RAX1, ARM64_INS_RBIT, ARM64_INS_RDFFR, ARM64_INS_RDFFRS, ARM64_INS_RDVL, ARM64_INS_RET, ARM64_INS_RETAA, ARM64_INS_RETAB, ARM64_INS_REV, ARM64_INS_REV16, ARM64_INS_REV32, ARM64_INS_REV64, ARM64_INS_REVB, ARM64_INS_REVH, ARM64_INS_REVW, ARM64_INS_RMIF, ARM64_INS_ROR, ARM64_INS_RORV, ARM64_INS_RSHRN, ARM64_INS_RSHRN2, ARM64_INS_RSUBHN, ARM64_INS_RSUBHN2, ARM64_INS_SABA, ARM64_INS_SABAL, ARM64_INS_SABAL2, ARM64_INS_SABD, ARM64_INS_SABDL, ARM64_INS_SABDL2, ARM64_INS_SADALP, ARM64_INS_SADDL, ARM64_INS_SADDL2, ARM64_INS_SADDLP, ARM64_INS_SADDLV, ARM64_INS_SADDV, ARM64_INS_SADDW, ARM64_INS_SADDW2, ARM64_INS_SBC, ARM64_INS_SBCS, ARM64_INS_SBFM, ARM64_INS_SCVTF, ARM64_INS_SDIV, ARM64_INS_SDIVR, ARM64_INS_SDOT, ARM64_INS_SEL, ARM64_INS_SETF16, ARM64_INS_SETF8, ARM64_INS_SETFFR, ARM64_INS_SEV, ARM64_INS_SEVL, ARM64_INS_SHA1C, ARM64_INS_SHA1H, ARM64_INS_SHA1M, ARM64_INS_SHA1P, ARM64_INS_SHA1SU0, ARM64_INS_SHA1SU1, ARM64_INS_SHA256H, ARM64_INS_SHA256H2, ARM64_INS_SHA256SU0, ARM64_INS_SHA256SU1, ARM64_INS_SHA512H, ARM64_INS_SHA512H2, ARM64_INS_SHA512SU0, ARM64_INS_SHA512SU1, ARM64_INS_SHADD, ARM64_INS_SHL, ARM64_INS_SHLL, ARM64_INS_SHLL2, ARM64_INS_SHRN, ARM64_INS_SHRN2, ARM64_INS_SHSUB, ARM64_INS_SLI, ARM64_INS_SM3PARTW1, ARM64_INS_SM3PARTW2, ARM64_INS_SM3SS1, ARM64_INS_SM3TT1A, ARM64_INS_SM3TT1B, ARM64_INS_SM3TT2A, ARM64_INS_SM3TT2B, ARM64_INS_SM4E, ARM64_INS_SM4EKEY, ARM64_INS_SMADDL, ARM64_INS_SMAX, ARM64_INS_SMAXP, ARM64_INS_SMAXV, ARM64_INS_SMC, ARM64_INS_SMIN, ARM64_INS_SMINP, ARM64_INS_SMINV, ARM64_INS_SMLAL, ARM64_INS_SMLAL2, ARM64_INS_SMLSL, ARM64_INS_SMLSL2, ARM64_INS_SMNEGL, ARM64_INS_SMOV, ARM64_INS_SMSUBL, ARM64_INS_SMULH, ARM64_INS_SMULL, ARM64_INS_SMULL2, ARM64_INS_SPLICE, ARM64_INS_SQABS, ARM64_INS_SQADD, ARM64_INS_SQDECB, ARM64_INS_SQDECD, ARM64_INS_SQDECH, ARM64_INS_SQDECP, ARM64_INS_SQDECW, ARM64_INS_SQDMLAL, ARM64_INS_SQDMLAL2, ARM64_INS_SQDMLSL, ARM64_INS_SQDMLSL2, ARM64_INS_SQDMULH, ARM64_INS_SQDMULL, ARM64_INS_SQDMULL2, ARM64_INS_SQINCB, ARM64_INS_SQINCD, ARM64_INS_SQINCH, ARM64_INS_SQINCP, ARM64_INS_SQINCW, ARM64_INS_SQNEG, ARM64_INS_SQRDMLAH, ARM64_INS_SQRDMLSH, ARM64_INS_SQRDMULH, ARM64_INS_SQRSHL, ARM64_INS_SQRSHRN, ARM64_INS_SQRSHRN2, ARM64_INS_SQRSHRUN, ARM64_INS_SQRSHRUN2, ARM64_INS_SQSHL, ARM64_INS_SQSHLU, ARM64_INS_SQSHRN, ARM64_INS_SQSHRN2, ARM64_INS_SQSHRUN, ARM64_INS_SQSHRUN2, ARM64_INS_SQSUB, ARM64_INS_SQXTN, ARM64_INS_SQXTN2, ARM64_INS_SQXTUN, ARM64_INS_SQXTUN2, ARM64_INS_SRHADD, ARM64_INS_SRI, ARM64_INS_SRSHL, ARM64_INS_SRSHR, ARM64_INS_SRSRA, ARM64_INS_SSHL, ARM64_INS_SSHLL, ARM64_INS_SSHLL2, ARM64_INS_SSHR, ARM64_INS_SSRA, ARM64_INS_SSUBL, ARM64_INS_SSUBL2, ARM64_INS_SSUBW, ARM64_INS_SSUBW2, ARM64_INS_ST1, ARM64_INS_ST1B, ARM64_INS_ST1D, ARM64_INS_ST1H, ARM64_INS_ST1W, ARM64_INS_ST2, ARM64_INS_ST2B, ARM64_INS_ST2D, ARM64_INS_ST2H, ARM64_INS_ST2W, ARM64_INS_ST3, ARM64_INS_ST3B, ARM64_INS_ST3D, ARM64_INS_ST3H, ARM64_INS_ST3W, ARM64_INS_ST4, ARM64_INS_ST4B, ARM64_INS_ST4D, ARM64_INS_ST4H, ARM64_INS_ST4W, ARM64_INS_STADD, ARM64_INS_STADDB, ARM64_INS_STADDH, ARM64_INS_STADDL, ARM64_INS_STADDLB, ARM64_INS_STADDLH, ARM64_INS_STCLR, ARM64_INS_STCLRB, ARM64_INS_STCLRH, ARM64_INS_STCLRL, ARM64_INS_STCLRLB, ARM64_INS_STCLRLH, ARM64_INS_STEOR, ARM64_INS_STEORB, ARM64_INS_STEORH, ARM64_INS_STEORL, ARM64_INS_STEORLB, ARM64_INS_STEORLH, ARM64_INS_STLLR, ARM64_INS_STLLRB, ARM64_INS_STLLRH, ARM64_INS_STLR, ARM64_INS_STLRB, ARM64_INS_STLRH, ARM64_INS_STLUR, ARM64_INS_STLURB, ARM64_INS_STLURH, ARM64_INS_STLXP, ARM64_INS_STLXR, ARM64_INS_STLXRB, ARM64_INS_STLXRH, ARM64_INS_STNP, ARM64_INS_STNT1B, ARM64_INS_STNT1D, ARM64_INS_STNT1H, ARM64_INS_STNT1W, ARM64_INS_STP, ARM64_INS_STR, ARM64_INS_STRB, ARM64_INS_STRH, ARM64_INS_STSET, ARM64_INS_STSETB, ARM64_INS_STSETH, ARM64_INS_STSETL, ARM64_INS_STSETLB, ARM64_INS_STSETLH, ARM64_INS_STSMAX, ARM64_INS_STSMAXB, ARM64_INS_STSMAXH, ARM64_INS_STSMAXL, ARM64_INS_STSMAXLB, ARM64_INS_STSMAXLH, ARM64_INS_STSMIN, ARM64_INS_STSMINB, ARM64_INS_STSMINH, ARM64_INS_STSMINL, ARM64_INS_STSMINLB, ARM64_INS_STSMINLH, ARM64_INS_STTR, ARM64_INS_STTRB, ARM64_INS_STTRH, ARM64_INS_STUMAX, ARM64_INS_STUMAXB, ARM64_INS_STUMAXH, ARM64_INS_STUMAXL, ARM64_INS_STUMAXLB, ARM64_INS_STUMAXLH, ARM64_INS_STUMIN, ARM64_INS_STUMINB, ARM64_INS_STUMINH, ARM64_INS_STUMINL, ARM64_INS_STUMINLB, ARM64_INS_STUMINLH, ARM64_INS_STUR, ARM64_INS_STURB, ARM64_INS_STURH, ARM64_INS_STXP, ARM64_INS_STXR, ARM64_INS_STXRB, ARM64_INS_STXRH, ARM64_INS_SUB, ARM64_INS_SUBHN, ARM64_INS_SUBHN2, ARM64_INS_SUBR, ARM64_INS_SUBS, ARM64_INS_SUNPKHI, ARM64_INS_SUNPKLO, ARM64_INS_SUQADD, ARM64_INS_SVC, ARM64_INS_SWP, ARM64_INS_SWPA, ARM64_INS_SWPAB, ARM64_INS_SWPAH, ARM64_INS_SWPAL, ARM64_INS_SWPALB, ARM64_INS_SWPALH, ARM64_INS_SWPB, ARM64_INS_SWPH, ARM64_INS_SWPL, ARM64_INS_SWPLB, ARM64_INS_SWPLH, ARM64_INS_SXTB, ARM64_INS_SXTH, ARM64_INS_SXTL, ARM64_INS_SXTL2, ARM64_INS_SXTW, ARM64_INS_SYS, ARM64_INS_SYSL, ARM64_INS_TBL, ARM64_INS_TBNZ, ARM64_INS_TBX, ARM64_INS_TBZ, ARM64_INS_TRN1, ARM64_INS_TRN2, ARM64_INS_TSB, ARM64_INS_TST, ARM64_INS_UABA, ARM64_INS_UABAL, ARM64_INS_UABAL2, ARM64_INS_UABD, ARM64_INS_UABDL, ARM64_INS_UABDL2, ARM64_INS_UADALP, ARM64_INS_UADDL, ARM64_INS_UADDL2, ARM64_INS_UADDLP, ARM64_INS_UADDLV, ARM64_INS_UADDV, ARM64_INS_UADDW, ARM64_INS_UADDW2, ARM64_INS_UBFM, ARM64_INS_UCVTF, ARM64_INS_UDIV, ARM64_INS_UDIVR, ARM64_INS_UDOT, ARM64_INS_UHADD, ARM64_INS_UHSUB, ARM64_INS_UMADDL, ARM64_INS_UMAX, ARM64_INS_UMAXP, ARM64_INS_UMAXV, ARM64_INS_UMIN, ARM64_INS_UMINP, ARM64_INS_UMINV, ARM64_INS_UMLAL, ARM64_INS_UMLAL2, ARM64_INS_UMLSL, ARM64_INS_UMLSL2, ARM64_INS_UMNEGL, ARM64_INS_UMOV, ARM64_INS_UMSUBL, ARM64_INS_UMULH, ARM64_INS_UMULL, ARM64_INS_UMULL2, ARM64_INS_UQADD, ARM64_INS_UQDECB, ARM64_INS_UQDECD, ARM64_INS_UQDECH, ARM64_INS_UQDECP, ARM64_INS_UQDECW, ARM64_INS_UQINCB, ARM64_INS_UQINCD, ARM64_INS_UQINCH, ARM64_INS_UQINCP, ARM64_INS_UQINCW, ARM64_INS_UQRSHL, ARM64_INS_UQRSHRN, ARM64_INS_UQRSHRN2, ARM64_INS_UQSHL, ARM64_INS_UQSHRN, ARM64_INS_UQSHRN2, ARM64_INS_UQSUB, ARM64_INS_UQXTN, ARM64_INS_UQXTN2, ARM64_INS_URECPE, ARM64_INS_URHADD, ARM64_INS_URSHL, ARM64_INS_URSHR, ARM64_INS_URSQRTE, ARM64_INS_URSRA, ARM64_INS_USHL, ARM64_INS_USHLL, ARM64_INS_USHLL2, ARM64_INS_USHR, ARM64_INS_USQADD, ARM64_INS_USRA, ARM64_INS_USUBL, ARM64_INS_USUBL2, ARM64_INS_USUBW, ARM64_INS_USUBW2, ARM64_INS_UUNPKHI, ARM64_INS_UUNPKLO, ARM64_INS_UXTB, ARM64_INS_UXTH, ARM64_INS_UXTL, ARM64_INS_UXTL2, ARM64_INS_UXTW, ARM64_INS_UZP1, ARM64_INS_UZP2, ARM64_INS_WFE, ARM64_INS_WFI, ARM64_INS_WHILELE, ARM64_INS_WHILELO, ARM64_INS_WHILELS, ARM64_INS_WHILELT, ARM64_INS_WRFFR, ARM64_INS_XAR, ARM64_INS_XPACD, ARM64_INS_XPACI, ARM64_INS_XPACLRI, ARM64_INS_XTN, ARM64_INS_XTN2, ARM64_INS_YIELD, ARM64_INS_ZIP1, ARM64_INS_ZIP2, // alias insn ARM64_INS_SBFIZ, ARM64_INS_UBFIZ, ARM64_INS_SBFX, ARM64_INS_UBFX, ARM64_INS_BFI, ARM64_INS_BFXIL, ARM64_INS_IC, ARM64_INS_DC, ARM64_INS_AT, ARM64_INS_TLBI, ARM64_INS_ENDING, // <-- mark the end of the list of insn } arm64_insn; /// Group of ARM64 instructions typedef enum arm64_insn_group { ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) ARM64_GRP_JUMP, ///< = CS_GRP_JUMP ARM64_GRP_CALL, ARM64_GRP_RET, ARM64_GRP_INT, ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE ARM64_GRP_PAC, // Architecture-specific groups ARM64_GRP_CRYPTO = 128, ARM64_GRP_FPARMV8, ARM64_GRP_NEON, ARM64_GRP_CRC, ARM64_GRP_AES, ARM64_GRP_DOTPROD, ARM64_GRP_FULLFP16, ARM64_GRP_LSE, ARM64_GRP_RCPC, ARM64_GRP_RDM, ARM64_GRP_SHA2, ARM64_GRP_SHA3, ARM64_GRP_SM4, ARM64_GRP_SVE, ARM64_GRP_V8_1A, ARM64_GRP_V8_3A, ARM64_GRP_V8_4A, ARM64_GRP_ENDING, // <-- mark the end of the list of groups } arm64_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/bpf.h000064400000000000000000000077440072674642500203760ustar 00000000000000/* Capstone Disassembly Engine */ /* BPF Backend by david942j , 2019 */ #ifndef CAPSTONE_BPF_H #define CAPSTONE_BPF_H #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// Operand type for instruction's operands typedef enum bpf_op_type { BPF_OP_INVALID = 0, BPF_OP_REG, BPF_OP_IMM, BPF_OP_OFF, BPF_OP_MEM, BPF_OP_MMEM, ///< M[k] in cBPF BPF_OP_MSH, ///< corresponds to cBPF's BPF_MSH mode BPF_OP_EXT, ///< cBPF's extension (not eBPF) } bpf_op_type; /// BPF registers typedef enum bpf_reg { BPF_REG_INVALID = 0, ///< cBPF BPF_REG_A, BPF_REG_X, ///< eBPF BPF_REG_R0, BPF_REG_R1, BPF_REG_R2, BPF_REG_R3, BPF_REG_R4, BPF_REG_R5, BPF_REG_R6, BPF_REG_R7, BPF_REG_R8, BPF_REG_R9, BPF_REG_R10, BPF_REG_ENDING, } bpf_reg; /// Instruction's operand referring to memory /// This is associated with BPF_OP_MEM operand type above typedef struct bpf_op_mem { bpf_reg base; ///< base register uint32_t disp; ///< offset value } bpf_op_mem; typedef enum bpf_ext_type { BPF_EXT_INVALID = 0, BPF_EXT_LEN, } bpf_ext_type; /// Instruction operand typedef struct cs_bpf_op { bpf_op_type type; union { uint8_t reg; ///< register value for REG operand uint64_t imm; ///< immediate value IMM operand uint32_t off; ///< offset value, used in jump & call bpf_op_mem mem; ///< base/disp value for MEM operand /* cBPF only */ uint32_t mmem; ///< M[k] in cBPF uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode uint32_t ext; ///< cBPF's extension (not eBPF) }; /// How is this operand accessed? (READ, WRITE or READ|WRITE) /// This field is combined of cs_ac_type. /// NOTE: this field is irrelevant if engine is compiled in DIET mode. uint8_t access; } cs_bpf_op; /// Instruction structure typedef struct cs_bpf { uint8_t op_count; cs_bpf_op operands[4]; } cs_bpf; /// BPF instruction typedef enum bpf_insn { BPF_INS_INVALID = 0, ///< ALU BPF_INS_ADD, BPF_INS_SUB, BPF_INS_MUL, BPF_INS_DIV, BPF_INS_OR, BPF_INS_AND, BPF_INS_LSH, BPF_INS_RSH, BPF_INS_NEG, BPF_INS_MOD, BPF_INS_XOR, BPF_INS_MOV, ///< eBPF only BPF_INS_ARSH, ///< eBPF only ///< ALU64, eBPF only BPF_INS_ADD64, BPF_INS_SUB64, BPF_INS_MUL64, BPF_INS_DIV64, BPF_INS_OR64, BPF_INS_AND64, BPF_INS_LSH64, BPF_INS_RSH64, BPF_INS_NEG64, BPF_INS_MOD64, BPF_INS_XOR64, BPF_INS_MOV64, BPF_INS_ARSH64, ///< Byteswap, eBPF only BPF_INS_LE16, BPF_INS_LE32, BPF_INS_LE64, BPF_INS_BE16, BPF_INS_BE32, BPF_INS_BE64, ///< Load BPF_INS_LDW, ///< eBPF only BPF_INS_LDH, BPF_INS_LDB, BPF_INS_LDDW, ///< eBPF only: load 64-bit imm BPF_INS_LDXW, ///< eBPF only BPF_INS_LDXH, ///< eBPF only BPF_INS_LDXB, ///< eBPF only BPF_INS_LDXDW, ///< eBPF only ///< Store BPF_INS_STW, ///< eBPF only BPF_INS_STH, ///< eBPF only BPF_INS_STB, ///< eBPF only BPF_INS_STDW, ///< eBPF only BPF_INS_STXW, ///< eBPF only BPF_INS_STXH, ///< eBPF only BPF_INS_STXB, ///< eBPF only BPF_INS_STXDW, ///< eBPF only BPF_INS_XADDW, ///< eBPF only BPF_INS_XADDDW, ///< eBPF only ///< Jump BPF_INS_JMP, BPF_INS_JEQ, BPF_INS_JGT, BPF_INS_JGE, BPF_INS_JSET, BPF_INS_JNE, ///< eBPF only BPF_INS_JSGT, ///< eBPF only BPF_INS_JSGE, ///< eBPF only BPF_INS_CALL, ///< eBPF only BPF_INS_EXIT, ///< eBPF only BPF_INS_JLT, ///< eBPF only BPF_INS_JLE, ///< eBPF only BPF_INS_JSLT, ///< eBPF only BPF_INS_JSLE, ///< eBPF only ///< Return, cBPF only BPF_INS_RET, ///< Misc, cBPF only BPF_INS_TAX, BPF_INS_TXA, BPF_INS_ENDING, // alias instructions BPF_INS_LD = BPF_INS_LDW, ///< cBPF only BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only BPF_INS_ST = BPF_INS_STW, ///< cBPF only BPF_INS_STX = BPF_INS_STXW, ///< cBPF only } bpf_insn; /// Group of BPF instructions typedef enum bpf_insn_group { BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID BPF_GRP_LOAD, BPF_GRP_STORE, BPF_GRP_ALU, BPF_GRP_JUMP, BPF_GRP_CALL, ///< eBPF only BPF_GRP_RETURN, BPF_GRP_MISC, ///< cBPF only BPF_GRP_ENDING, } bpf_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/capstone.h000064400000000000000000000742230072674642500214370ustar 00000000000000#ifndef CAPSTONE_ENGINE_H #define CAPSTONE_ENGINE_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2016 */ #ifdef __cplusplus extern "C" { #endif #include #if defined(CAPSTONE_HAS_OSXKERNEL) #include #else #include #include #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #pragma warning(disable:4100) #define CAPSTONE_API __cdecl #ifdef CAPSTONE_SHARED #define CAPSTONE_EXPORT __declspec(dllexport) #else // defined(CAPSTONE_STATIC) #define CAPSTONE_EXPORT #endif #else #define CAPSTONE_API #if (defined(__GNUC__) || defined(__IBMC__)) && !defined(CAPSTONE_STATIC) #define CAPSTONE_EXPORT __attribute__((visibility("default"))) #else // defined(CAPSTONE_STATIC) #define CAPSTONE_EXPORT #endif #endif #if (defined(__GNUC__) || defined(__IBMC__)) #define CAPSTONE_DEPRECATED __attribute__((deprecated)) #elif defined(_MSC_VER) #define CAPSTONE_DEPRECATED __declspec(deprecated) #else #pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler") #define CAPSTONE_DEPRECATED #endif // Capstone API version #define CS_API_MAJOR 5 #define CS_API_MINOR 0 // Version for bleeding edge code of the Github's "next" branch. // Use this if you want the absolutely latest development code. // This version number will be bumped up whenever we have a new major change. #define CS_NEXT_VERSION 5 // Capstone package version #define CS_VERSION_MAJOR CS_API_MAJOR #define CS_VERSION_MINOR CS_API_MINOR #define CS_VERSION_EXTRA 0 /// Macro to create combined version which can be compared to /// result of cs_version() API. #define CS_MAKE_VERSION(major, minor) ((major << 8) + minor) /// Maximum size of an instruction mnemonic string. #define CS_MNEMONIC_SIZE 32 // Handle using with all API typedef size_t csh; /// Architecture type typedef enum cs_arch { CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2) CS_ARCH_ARM64, ///< ARM-64, also called AArch64 CS_ARCH_MIPS, ///< Mips architecture CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64) CS_ARCH_PPC, ///< PowerPC architecture CS_ARCH_SPARC, ///< Sparc architecture CS_ARCH_SYSZ, ///< SystemZ architecture CS_ARCH_XCORE, ///< XCore architecture CS_ARCH_M68K, ///< 68K architecture CS_ARCH_TMS320C64X, ///< TMS320C64x architecture CS_ARCH_M680X, ///< 680X architecture CS_ARCH_EVM, ///< Ethereum architecture CS_ARCH_MOS65XX, ///< MOS65XX architecture (including MOS6502) CS_ARCH_WASM, ///< WebAssembly architecture CS_ARCH_BPF, ///< Berkeley Packet Filter architecture (including eBPF) CS_ARCH_RISCV, ///< RISCV architecture CS_ARCH_MAX, CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support() } cs_arch; // Support value to verify diet mode of the engine. // If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled // in diet mode. #define CS_SUPPORT_DIET (CS_ARCH_ALL + 1) // Support value to verify X86 reduce mode of the engine. // If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled // in X86 reduce mode. #define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2) /// Mode type typedef enum cs_mode { CS_MODE_LITTLE_ENDIAN = 0, ///< little-endian mode (default mode) CS_MODE_ARM = 0, ///< 32-bit ARM CS_MODE_16 = 1 << 1, ///< 16-bit mode (X86) CS_MODE_32 = 1 << 2, ///< 32-bit mode (X86) CS_MODE_64 = 1 << 3, ///< 64-bit mode (X86, PPC) CS_MODE_THUMB = 1 << 4, ///< ARM's Thumb mode, including Thumb-2 CS_MODE_MCLASS = 1 << 5, ///< ARM's Cortex-M series CS_MODE_V8 = 1 << 6, ///< ARMv8 A32 encodings for ARM CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS) CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc) CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC) CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC) CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC) CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode CS_MODE_MIPS32 = CS_MODE_32, ///< Mips32 ISA (Mips) CS_MODE_MIPS64 = CS_MODE_64, ///< Mips64 ISA (Mips) CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12 ///< used on M68HC12/HCS12 CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode CS_MODE_BPF_CLASSIC = 0, ///< Classic BPF mode (default) CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502 CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02 CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02 CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X, } cs_mode; typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size); typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size); typedef void (CAPSTONE_API *cs_free_t)(void *ptr); typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap); /// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf() /// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf(). typedef struct cs_opt_mem { cs_malloc_t malloc; cs_calloc_t calloc; cs_realloc_t realloc; cs_free_t free; cs_vsnprintf_t vsnprintf; } cs_opt_mem; /// Customize mnemonic for instructions with alternative name. /// To reset existing customized instruction to its default mnemonic, /// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value /// for @mnemonic. typedef struct cs_opt_mnem { /// ID of instruction to be customized. unsigned int id; /// Customized instruction mnemonic. const char *mnemonic; } cs_opt_mnem; /// Runtime option for the disassembled engine typedef enum cs_opt_type { CS_OPT_INVALID = 0, ///< No option specified CS_OPT_SYNTAX, ///< Assembly output syntax CS_OPT_DETAIL, ///< Break down instruction structure into details CS_OPT_MODE, ///< Change engine's mode at run-time CS_OPT_MEM, ///< User-defined dynamic memory related functions CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode. CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option CS_OPT_MNEMONIC, ///< Customize instruction mnemonic CS_OPT_UNSIGNED, ///< print immediate operands in unsigned form } cs_opt_type; /// Runtime option value (associated with option type above) typedef enum cs_opt_value { CS_OPT_OFF = 0, ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED. CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX). CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). CS_OPT_SYNTAX_ATT, ///< X86 ATT asm syntax (CS_OPT_SYNTAX). CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX) CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX). CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix } cs_opt_value; /// Common instruction operand types - to be consistent across all architectures. typedef enum cs_op_type { CS_OP_INVALID = 0, ///< uninitialized/invalid operand. CS_OP_REG, ///< Register operand. CS_OP_IMM, ///< Immediate operand. CS_OP_MEM, ///< Memory operand. CS_OP_FP, ///< Floating-Point operand. } cs_op_type; /// Common instruction operand access types - to be consistent across all architectures. /// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE typedef enum cs_ac_type { CS_AC_INVALID = 0, ///< Uninitialized/invalid access type. CS_AC_READ = 1 << 0, ///< Operand read from memory or register. CS_AC_WRITE = 1 << 1, ///< Operand write to memory or register. } cs_ac_type; /// Common instruction groups - to be consistent across all architectures. typedef enum cs_group_type { CS_GRP_INVALID = 0, ///< uninitialized/invalid group. CS_GRP_JUMP, ///< all jump instructions (conditional+direct+indirect jumps) CS_GRP_CALL, ///< all call instructions CS_GRP_RET, ///< all return instructions CS_GRP_INT, ///< all interrupt instructions (int+syscall) CS_GRP_IRET, ///< all interrupt return instructions CS_GRP_PRIVILEGE, ///< all privileged instructions CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions } cs_group_type; /** User-defined callback function for SKIPDATA option. See tests/test_skipdata.c for sample code demonstrating this API. @code: the input buffer containing code to be disassembled. This is the same buffer passed to cs_disasm(). @code_size: size (in bytes) of the above @code buffer. @offset: the position of the currently-examining byte in the input buffer @code mentioned above. @user_data: user-data passed to cs_option() via @user_data field in cs_opt_skipdata struct below. @return: return number of bytes to skip, or 0 to immediately stop disassembling. */ typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data); /// User-customized setup for SKIPDATA option typedef struct cs_opt_skipdata { /// Capstone considers data to skip as special "instructions". /// User can specify the string for this instruction's "mnemonic" here. /// By default (if @mnemonic is NULL), Capstone use ".byte". const char *mnemonic; /// User-defined callback function to be called when Capstone hits data. /// If the returned value from this callback is positive (>0), Capstone /// will skip exactly that number of bytes & continue. Otherwise, if /// the callback returns 0, Capstone stops disassembling and returns /// immediately from cs_disasm() /// NOTE: if this callback pointer is NULL, Capstone would skip a number /// of bytes depending on architectures, as following: /// Arm: 2 bytes (Thumb mode) or 4 bytes. /// Arm64: 4 bytes. /// Mips: 4 bytes. /// M680x: 1 byte. /// PowerPC: 4 bytes. /// Sparc: 4 bytes. /// SystemZ: 2 bytes. /// X86: 1 bytes. /// XCore: 2 bytes. /// EVM: 1 bytes. /// RISCV: 4 bytes. /// WASM: 1 bytes. /// MOS65XX: 1 bytes. /// BPF: 8 bytes. cs_skipdata_cb_t callback; // default value is NULL /// User-defined data to be passed to @callback function pointer. void *user_data; } cs_opt_skipdata; #include "arm.h" #include "arm64.h" #include "m68k.h" #include "mips.h" #include "ppc.h" #include "sparc.h" #include "systemz.h" #include "x86.h" #include "xcore.h" #include "tms320c64x.h" #include "m680x.h" #include "evm.h" #include "riscv.h" #include "wasm.h" #include "mos65xx.h" #include "bpf.h" /// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON /// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH)) /// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c /// if cs_detail changes, in particular if a field is added after the union, /// then update arch/ARCH/ARCHDisassembler.c accordingly typedef struct cs_detail { uint16_t regs_read[16]; ///< list of implicit registers read by this insn uint8_t regs_read_count; ///< number of implicit registers read by this insn uint16_t regs_write[20]; ///< list of implicit registers modified by this insn uint8_t regs_write_count; ///< number of implicit registers modified by this insn uint8_t groups[8]; ///< list of group this instruction belong to uint8_t groups_count; ///< number of groups this insn belongs to /// Architecture-specific instruction info union { cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode cs_arm64 arm64; ///< ARM64 architecture (aka AArch64) cs_arm arm; ///< ARM architecture (including Thumb/Thumb2) cs_m68k m68k; ///< M68K architecture cs_mips mips; ///< MIPS architecture cs_ppc ppc; ///< PowerPC architecture cs_sparc sparc; ///< Sparc architecture cs_sysz sysz; ///< SystemZ architecture cs_xcore xcore; ///< XCore architecture cs_tms320c64x tms320c64x; ///< TMS320C64x architecture cs_m680x m680x; ///< M680X architecture cs_evm evm; ///< Ethereum architecture cs_mos65xx mos65xx; ///< MOS65XX architecture (including MOS6502) cs_wasm wasm; ///< Web Assembly architecture cs_bpf bpf; ///< Berkeley Packet Filter architecture (including eBPF) cs_riscv riscv; ///< RISCV architecture }; } cs_detail; /// Detail information of disassembled instruction typedef struct cs_insn { /// Instruction ID (basically a numeric ID for the instruction mnemonic) /// Find the instruction id in the '[ARCH]_insn' enum in the header file /// of corresponding architecture, such as 'arm_insn' in arm.h for ARM, /// 'x86_insn' in x86.h for X86, etc... /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF /// NOTE: in Skipdata mode, "data" instruction has 0 for this id field. unsigned int id; /// Address (EIP) of this instruction /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF uint64_t address; /// Size of this instruction /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF uint16_t size; /// Machine bytes of this instruction, with number of bytes indicated by @size above /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF uint8_t bytes[24]; /// Ascii text of instruction mnemonic /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF char mnemonic[CS_MNEMONIC_SIZE]; /// Ascii text of instruction operands /// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF char op_str[160]; /// Pointer to cs_detail. /// NOTE: detail pointer is only valid when both requirements below are met: /// (1) CS_OP_DETAIL = CS_OPT_ON /// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON) /// /// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer /// is not NULL, its content is still irrelevant. cs_detail *detail; } cs_insn; /// Calculate the offset of a disassembled instruction in its buffer, given its position /// in its array of disassembled insn /// NOTE: this macro works with position (>=1), not index #define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address) /// All type of errors encountered by Capstone API. /// These are values returned by cs_errno() typedef enum cs_err { CS_ERR_OK = 0, ///< No error: everything was fine CS_ERR_MEM, ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter() CS_ERR_ARCH, ///< Unsupported architecture: cs_open() CS_ERR_HANDLE, ///< Invalid handle: cs_op_count(), cs_op_index() CS_ERR_CSH, ///< Invalid csh argument: cs_close(), cs_errno(), cs_option() CS_ERR_MODE, ///< Invalid/unsupported mode: cs_open() CS_ERR_OPTION, ///< Invalid/unsupported option: cs_option() CS_ERR_DETAIL, ///< Information is unavailable because detail option is OFF CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM) CS_ERR_VERSION, ///< Unsupported version (bindings) CS_ERR_DIET, ///< Access irrelevant data in "diet" engine CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode CS_ERR_X86_ATT, ///< X86 AT&T syntax is unsupported (opt-out at compile time) CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time) CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time) } cs_err; /** Return combined API version & major and minor version numbers. @major: major number of API version @minor: minor number of API version @return hexical number as (major << 8 | minor), which encodes both major & minor versions. NOTE: This returned value can be compared with version number made with macro CS_MAKE_VERSION For example, second API version would return 1 in @major, and 1 in @minor The return value would be 0x0101 NOTE: if you only care about returned value, but not major and minor values, set both @major & @minor arguments to NULL. */ CAPSTONE_EXPORT unsigned int CAPSTONE_API cs_version(int *major, int *minor); /** This API can be used to either ask for archs supported by this library, or check to see if the library was compile with 'diet' option (or called in 'diet' mode). To check if a particular arch is supported by this library, set @query to arch mode (CS_ARCH_* value). To verify if this library supports all the archs, use CS_ARCH_ALL. To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET. @return True if this library supports the given arch, or in 'diet' mode. */ CAPSTONE_EXPORT bool CAPSTONE_API cs_support(int query); /** Initialize CS handle: this must be done before any usage of CS. @arch: architecture type (CS_ARCH_*) @mode: hardware mode. This is combined of CS_MODE_* @handle: pointer to handle, which will be updated at return time @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum for detailed error). */ CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle); /** Close CS handle: MUST do to release the handle when it is not used anymore. NOTE: this must be only called when there is no longer usage of Capstone, not even access to cs_insn array. The reason is the this API releases some cached memory, thus access to any Capstone API after cs_close() might crash your application. In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0). @handle: pointer to a handle returned by cs_open() @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum for detailed error). */ CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle); /** Set option for disassembling engine at runtime @handle: handle returned by cs_open() @type: type of option to be set @value: option value corresponding with @type @return: CS_ERR_OK on success, or other value on failure. Refer to cs_err enum for detailed error. NOTE: in the case of CS_OPT_MEM, handle's value can be anything, so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called even before cs_open() */ CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value); /** Report the last error number when some API function fail. Like glibc's errno, cs_errno might not retain its old value once accessed. @handle: handle returned by cs_open() @return: error code of cs_err enum type (CS_ERR_*, see above) */ CAPSTONE_EXPORT cs_err CAPSTONE_API cs_errno(csh handle); /** Return a string describing given error code. @code: error code (see CS_ERR_* above) @return: returns a pointer to a string that describes the error code passed in the argument @code */ CAPSTONE_EXPORT const char * CAPSTONE_API cs_strerror(cs_err code); /** Disassemble binary code, given the code buffer, size, address and number of instructions to be decoded. This API dynamically allocate memory to contain disassembled instruction. Resulting instructions will be put into @*insn NOTE 1: this API will automatically determine memory needed to contain output disassembled instructions in @insn. NOTE 2: caller must free the allocated memory itself to avoid memory leaking. NOTE 3: for system with scarce memory to be dynamically allocated such as OS kernel or firmware, the API cs_disasm_iter() might be a better choice than cs_disasm(). The reason is that with cs_disasm(), based on limited available memory, we have to calculate in advance how many instructions to be disassembled, which complicates things. This is especially troublesome for the case @count=0, when cs_disasm() runs uncontrollably (until either end of input buffer, or when it encounters an invalid instruction). @handle: handle returned by cs_open() @code: buffer containing raw binary code to be disassembled. @code_size: size of the above code buffer. @address: address of the first instruction in given raw code buffer. @insn: array of instructions filled in by this API. NOTE: @insn will be allocated by this function, and should be freed with cs_free() API. @count: number of instructions to be disassembled, or 0 to get all of them @return: the number of successfully disassembled instructions, or 0 if this function failed to disassemble the given code On failure, call cs_errno() for error code. */ CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh handle, const uint8_t *code, size_t code_size, uint64_t address, size_t count, cs_insn **insn); /** Free memory allocated by cs_malloc() or cs_disasm() (argument @insn) @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc() @count: number of cs_insn structures returned by cs_disasm(), or 1 to free memory allocated by cs_malloc(). */ CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count); /** Allocate memory for 1 instruction to be used by cs_disasm_iter(). @handle: handle returned by cs_open() NOTE: when no longer in use, you can reclaim the memory allocated for this instruction with cs_free(insn, 1) */ CAPSTONE_EXPORT cs_insn * CAPSTONE_API cs_malloc(csh handle); /** Fast API to disassemble binary code, given the code buffer, size, address and number of instructions to be decoded. This API puts the resulting instruction into a given cache in @insn. See tests/test_iter.c for sample code demonstrating this API. NOTE 1: this API will update @code, @size & @address to point to the next instruction in the input buffer. Therefore, it is convenient to use cs_disasm_iter() inside a loop to quickly iterate all the instructions. While decoding one instruction at a time can also be achieved with cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30% faster on random input. NOTE 2: the cache in @insn can be created with cs_malloc() API. NOTE 3: for system with scarce memory to be dynamically allocated such as OS kernel or firmware, this API is recommended over cs_disasm(), which allocates memory based on the number of instructions to be disassembled. The reason is that with cs_disasm(), based on limited available memory, we have to calculate in advance how many instructions to be disassembled, which complicates things. This is especially troublesome for the case @count=0, when cs_disasm() runs uncontrollably (until either end of input buffer, or when it encounters an invalid instruction). @handle: handle returned by cs_open() @code: buffer containing raw binary code to be disassembled @size: size of above code @address: address of the first insn in given raw code buffer @insn: pointer to instruction to be filled in by this API. @return: true if this API successfully decode 1 instruction, or false otherwise. On failure, call cs_errno() for error code. */ CAPSTONE_EXPORT bool CAPSTONE_API cs_disasm_iter(csh handle, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn); /** Return friendly name of register in a string. Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) WARN: when in 'diet' mode, this API is irrelevant because engine does not store register name. @handle: handle returned by cs_open() @reg_id: register id @return: string name of the register, or NULL if @reg_id is invalid. */ CAPSTONE_EXPORT const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id); /** Return friendly name of an instruction in a string. Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) WARN: when in 'diet' mode, this API is irrelevant because the engine does not store instruction name. @handle: handle returned by cs_open() @insn_id: instruction id @return: string name of the instruction, or NULL if @insn_id is invalid. */ CAPSTONE_EXPORT const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id); /** Return friendly name of a group id (that an instruction can belong to) Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) WARN: when in 'diet' mode, this API is irrelevant because the engine does not store group name. @handle: handle returned by cs_open() @group_id: group id @return: string name of the group, or NULL if @group_id is invalid. */ CAPSTONE_EXPORT const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id); /** Check if a disassembled instruction belong to a particular group. Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) Internally, this simply verifies if @group_id matches any member of insn->groups array. NOTE: this API is only valid when detail option is ON (which is OFF by default). WARN: when in 'diet' mode, this API is irrelevant because the engine does not update @groups array. @handle: handle returned by cs_open() @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() @group_id: group that you want to check if this instruction belong to. @return: true if this instruction indeed belongs to the given group, or false otherwise. */ CAPSTONE_EXPORT bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id); /** Check if a disassembled instruction IMPLICITLY used a particular register. Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) Internally, this simply verifies if @reg_id matches any member of insn->regs_read array. NOTE: this API is only valid when detail option is ON (which is OFF by default) WARN: when in 'diet' mode, this API is irrelevant because the engine does not update @regs_read array. @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() @reg_id: register that you want to check if this instruction used it. @return: true if this instruction indeed implicitly used the given register, or false otherwise. */ CAPSTONE_EXPORT bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id); /** Check if a disassembled instruction IMPLICITLY modified a particular register. Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) Internally, this simply verifies if @reg_id matches any member of insn->regs_write array. NOTE: this API is only valid when detail option is ON (which is OFF by default) WARN: when in 'diet' mode, this API is irrelevant because the engine does not update @regs_write array. @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() @reg_id: register that you want to check if this instruction modified it. @return: true if this instruction indeed implicitly modified the given register, or false otherwise. */ CAPSTONE_EXPORT bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id); /** Count the number of operands of a given type. Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) NOTE: this API is only valid when detail option is ON (which is OFF by default) @handle: handle returned by cs_open() @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() @op_type: Operand type to be found. @return: number of operands of given type @op_type in instruction @insn, or -1 on failure. */ CAPSTONE_EXPORT int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type); /** Retrieve the position of operand of given type in .operands[] array. Later, the operand can be accessed using the returned position. Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...) NOTE: this API is only valid when detail option is ON (which is OFF by default) @handle: handle returned by cs_open() @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter() @op_type: Operand type to be found. @position: position of the operand to be found. This must be in the range [1, cs_op_count(handle, insn, op_type)] @return: index of operand of given type @op_type in .operands[] array in instruction @insn, or -1 on failure. */ CAPSTONE_EXPORT int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type, unsigned int position); /// Type of array to keep the list of registers typedef uint16_t cs_regs[64]; /** Retrieve all the registers accessed by an instruction, either explicitly or implicitly. WARN: when in 'diet' mode, this API is irrelevant because engine does not store registers. @handle: handle returned by cs_open() @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter() @regs_read: on return, this array contains all registers read by instruction. @regs_read_count: number of registers kept inside @regs_read array. @regs_write: on return, this array contains all registers written by instruction. @regs_write_count: number of registers kept inside @regs_write array. @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum for detailed error). */ CAPSTONE_EXPORT cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/evm.h000064400000000000000000000104420072674642500204030ustar 00000000000000#ifndef CAPSTONE_EVM_H #define CAPSTONE_EVM_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2018 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// Instruction structure typedef struct cs_evm { unsigned char pop; ///< number of items popped from the stack unsigned char push; ///< number of items pushed into the stack unsigned int fee; ///< gas fee for the instruction } cs_evm; /// EVM instruction typedef enum evm_insn { EVM_INS_STOP = 0, EVM_INS_ADD = 1, EVM_INS_MUL = 2, EVM_INS_SUB = 3, EVM_INS_DIV = 4, EVM_INS_SDIV = 5, EVM_INS_MOD = 6, EVM_INS_SMOD = 7, EVM_INS_ADDMOD = 8, EVM_INS_MULMOD = 9, EVM_INS_EXP = 10, EVM_INS_SIGNEXTEND = 11, EVM_INS_LT = 16, EVM_INS_GT = 17, EVM_INS_SLT = 18, EVM_INS_SGT = 19, EVM_INS_EQ = 20, EVM_INS_ISZERO = 21, EVM_INS_AND = 22, EVM_INS_OR = 23, EVM_INS_XOR = 24, EVM_INS_NOT = 25, EVM_INS_BYTE = 26, EVM_INS_SHA3 = 32, EVM_INS_ADDRESS = 48, EVM_INS_BALANCE = 49, EVM_INS_ORIGIN = 50, EVM_INS_CALLER = 51, EVM_INS_CALLVALUE = 52, EVM_INS_CALLDATALOAD = 53, EVM_INS_CALLDATASIZE = 54, EVM_INS_CALLDATACOPY = 55, EVM_INS_CODESIZE = 56, EVM_INS_CODECOPY = 57, EVM_INS_GASPRICE = 58, EVM_INS_EXTCODESIZE = 59, EVM_INS_EXTCODECOPY = 60, EVM_INS_RETURNDATASIZE = 61, EVM_INS_RETURNDATACOPY = 62, EVM_INS_BLOCKHASH = 64, EVM_INS_COINBASE = 65, EVM_INS_TIMESTAMP = 66, EVM_INS_NUMBER = 67, EVM_INS_DIFFICULTY = 68, EVM_INS_GASLIMIT = 69, EVM_INS_POP = 80, EVM_INS_MLOAD = 81, EVM_INS_MSTORE = 82, EVM_INS_MSTORE8 = 83, EVM_INS_SLOAD = 84, EVM_INS_SSTORE = 85, EVM_INS_JUMP = 86, EVM_INS_JUMPI = 87, EVM_INS_PC = 88, EVM_INS_MSIZE = 89, EVM_INS_GAS = 90, EVM_INS_JUMPDEST = 91, EVM_INS_PUSH1 = 96, EVM_INS_PUSH2 = 97, EVM_INS_PUSH3 = 98, EVM_INS_PUSH4 = 99, EVM_INS_PUSH5 = 100, EVM_INS_PUSH6 = 101, EVM_INS_PUSH7 = 102, EVM_INS_PUSH8 = 103, EVM_INS_PUSH9 = 104, EVM_INS_PUSH10 = 105, EVM_INS_PUSH11 = 106, EVM_INS_PUSH12 = 107, EVM_INS_PUSH13 = 108, EVM_INS_PUSH14 = 109, EVM_INS_PUSH15 = 110, EVM_INS_PUSH16 = 111, EVM_INS_PUSH17 = 112, EVM_INS_PUSH18 = 113, EVM_INS_PUSH19 = 114, EVM_INS_PUSH20 = 115, EVM_INS_PUSH21 = 116, EVM_INS_PUSH22 = 117, EVM_INS_PUSH23 = 118, EVM_INS_PUSH24 = 119, EVM_INS_PUSH25 = 120, EVM_INS_PUSH26 = 121, EVM_INS_PUSH27 = 122, EVM_INS_PUSH28 = 123, EVM_INS_PUSH29 = 124, EVM_INS_PUSH30 = 125, EVM_INS_PUSH31 = 126, EVM_INS_PUSH32 = 127, EVM_INS_DUP1 = 128, EVM_INS_DUP2 = 129, EVM_INS_DUP3 = 130, EVM_INS_DUP4 = 131, EVM_INS_DUP5 = 132, EVM_INS_DUP6 = 133, EVM_INS_DUP7 = 134, EVM_INS_DUP8 = 135, EVM_INS_DUP9 = 136, EVM_INS_DUP10 = 137, EVM_INS_DUP11 = 138, EVM_INS_DUP12 = 139, EVM_INS_DUP13 = 140, EVM_INS_DUP14 = 141, EVM_INS_DUP15 = 142, EVM_INS_DUP16 = 143, EVM_INS_SWAP1 = 144, EVM_INS_SWAP2 = 145, EVM_INS_SWAP3 = 146, EVM_INS_SWAP4 = 147, EVM_INS_SWAP5 = 148, EVM_INS_SWAP6 = 149, EVM_INS_SWAP7 = 150, EVM_INS_SWAP8 = 151, EVM_INS_SWAP9 = 152, EVM_INS_SWAP10 = 153, EVM_INS_SWAP11 = 154, EVM_INS_SWAP12 = 155, EVM_INS_SWAP13 = 156, EVM_INS_SWAP14 = 157, EVM_INS_SWAP15 = 158, EVM_INS_SWAP16 = 159, EVM_INS_LOG0 = 160, EVM_INS_LOG1 = 161, EVM_INS_LOG2 = 162, EVM_INS_LOG3 = 163, EVM_INS_LOG4 = 164, EVM_INS_CREATE = 240, EVM_INS_CALL = 241, EVM_INS_CALLCODE = 242, EVM_INS_RETURN = 243, EVM_INS_DELEGATECALL = 244, EVM_INS_CALLBLACKBOX = 245, EVM_INS_STATICCALL = 250, EVM_INS_REVERT = 253, EVM_INS_SUICIDE = 255, EVM_INS_INVALID = 512, EVM_INS_ENDING, // <-- mark the end of the list of instructions } evm_insn; /// Group of EVM instructions typedef enum evm_insn_group { EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID EVM_GRP_JUMP, ///< all jump instructions EVM_GRP_MATH = 8, ///< math instructions EVM_GRP_STACK_WRITE, ///< instructions write to stack EVM_GRP_STACK_READ, ///< instructions read from stack EVM_GRP_MEM_WRITE, ///< instructions write to memory EVM_GRP_MEM_READ, ///< instructions read from memory EVM_GRP_STORE_WRITE, ///< instructions write to storage EVM_GRP_STORE_READ, ///< instructions read from storage EVM_GRP_HALT, ///< instructions halt execution EVM_GRP_ENDING, ///< <-- mark the end of the list of groups } evm_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/m680x.h000064400000000000000000000300400072674642500204720ustar 00000000000000#ifndef CAPSTONE_M680X_H #define CAPSTONE_M680X_H /* Capstone Disassembly Engine */ /* M680X Backend by Wolfgang Schwotzer 2017 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif #define M680X_OPERAND_COUNT 9 /// M680X registers and special registers typedef enum m680x_reg { M680X_REG_INVALID = 0, M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9 M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9 M680X_REG_E, ///< HD6309 M680X_REG_F, ///< HD6309 M680X_REG_0, ///< HD6309 M680X_REG_D, ///< M6801/3/9, HD6301/9 M680X_REG_W, ///< HD6309 M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9 M680X_REG_DP, ///< M6809/M6309 M680X_REG_MD, ///< M6309 M680X_REG_HX, ///< M6808 M680X_REG_H, ///< M6808 M680X_REG_X, ///< M6800/1/2/3/9, M6301/9 M680X_REG_Y, ///< M6809/M6309 M680X_REG_S, ///< M6809/M6309 M680X_REG_U, ///< M6809/M6309 M680X_REG_V, ///< M6309 M680X_REG_Q, ///< M6309 M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9 M680X_REG_TMP2, ///< CPU12 M680X_REG_TMP3, ///< CPU12 M680X_REG_ENDING, ///< <-- mark the end of the list of registers } m680x_reg; /// Operand type for instruction's operands typedef enum m680x_op_type { M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). M680X_OP_REGISTER, ///< = Register operand. M680X_OP_IMMEDIATE, ///< = Immediate operand. M680X_OP_INDEXED, ///< = Indexed addressing operand. M680X_OP_EXTENDED, ///< = Extended addressing operand. M680X_OP_DIRECT, ///< = Direct addressing operand. M680X_OP_RELATIVE, ///< = Relative addressing operand. M680X_OP_CONSTANT, ///< = constant operand (Displayed as number only). ///< Used e.g. for a bit index or page number. } m680x_op_type; // Supported bit values for mem.idx.offset_bits #define M680X_OFFSET_NONE 0 #define M680X_OFFSET_BITS_5 5 #define M680X_OFFSET_BITS_8 8 #define M680X_OFFSET_BITS_9 9 #define M680X_OFFSET_BITS_16 16 // Supported bit flags for mem.idx.flags // These flags can be combined #define M680X_IDX_INDIRECT 1 #define M680X_IDX_NO_COMMA 2 #define M680X_IDX_POST_INC_DEC 4 /// Instruction's operand referring to indexed addressing typedef struct m680x_op_idx { m680x_reg base_reg; ///< base register (or M680X_REG_INVALID if ///< irrelevant) m680x_reg offset_reg; ///< offset register (or M680X_REG_INVALID if ///< irrelevant) int16_t offset; ///< 5-,8- or 16-bit offset. See also offset_bits. uint16_t offset_addr; ///< = offset addr. if base_reg == M680X_REG_PC. ///< calculated as offset + PC uint8_t offset_bits; ///< offset width in bits for indexed addressing int8_t inc_dec; ///< inc. or dec. value: ///< 0: no inc-/decrement ///< 1 .. 8: increment by 1 .. 8 ///< -1 .. -8: decrement by 1 .. 8 ///< if flag M680X_IDX_POST_INC_DEC set it is post ///< inc-/decrement otherwise pre inc-/decrement uint8_t flags; ///< 8-bit flags (see above) } m680x_op_idx; /// Instruction's memory operand referring to relative addressing (Bcc/LBcc) typedef struct m680x_op_rel { uint16_t address; ///< The absolute address. ///< calculated as PC + offset. PC is the first ///< address after the instruction. int16_t offset; ///< the offset/displacement value } m680x_op_rel; /// Instruction's operand referring to extended addressing typedef struct m680x_op_ext { uint16_t address; ///< The absolute address bool indirect; ///< true if extended indirect addressing } m680x_op_ext; /// Instruction operand typedef struct cs_m680x_op { m680x_op_type type; union { int32_t imm; ///< immediate value for IMM operand m680x_reg reg; ///< register value for REG operand m680x_op_idx idx; ///< Indexed addressing operand m680x_op_rel rel; ///< Relative address. operand (Bcc/LBcc) m680x_op_ext ext; ///< Extended address uint8_t direct_addr; ///<, 2015-2016 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif #define M68K_OPERAND_COUNT 4 /// M68K registers and special registers typedef enum m68k_reg { M68K_REG_INVALID = 0, M68K_REG_D0, M68K_REG_D1, M68K_REG_D2, M68K_REG_D3, M68K_REG_D4, M68K_REG_D5, M68K_REG_D6, M68K_REG_D7, M68K_REG_A0, M68K_REG_A1, M68K_REG_A2, M68K_REG_A3, M68K_REG_A4, M68K_REG_A5, M68K_REG_A6, M68K_REG_A7, M68K_REG_FP0, M68K_REG_FP1, M68K_REG_FP2, M68K_REG_FP3, M68K_REG_FP4, M68K_REG_FP5, M68K_REG_FP6, M68K_REG_FP7, M68K_REG_PC, M68K_REG_SR, M68K_REG_CCR, M68K_REG_SFC, M68K_REG_DFC, M68K_REG_USP, M68K_REG_VBR, M68K_REG_CACR, M68K_REG_CAAR, M68K_REG_MSP, M68K_REG_ISP, M68K_REG_TC, M68K_REG_ITT0, M68K_REG_ITT1, M68K_REG_DTT0, M68K_REG_DTT1, M68K_REG_MMUSR, M68K_REG_URP, M68K_REG_SRP, M68K_REG_FPCR, M68K_REG_FPSR, M68K_REG_FPIAR, M68K_REG_ENDING, // <-- mark the end of the list of registers } m68k_reg; /// M68K Addressing Modes typedef enum m68k_address_mode { M68K_AM_NONE = 0, ///< No address mode. M68K_AM_REG_DIRECT_DATA, ///< Register Direct - Data M68K_AM_REG_DIRECT_ADDR, ///< Register Direct - Address M68K_AM_REGI_ADDR, ///< Register Indirect - Address M68K_AM_REGI_ADDR_POST_INC, ///< Register Indirect - Address with Postincrement M68K_AM_REGI_ADDR_PRE_DEC, ///< Register Indirect - Address with Predecrement M68K_AM_REGI_ADDR_DISP, ///< Register Indirect - Address with Displacement M68K_AM_AREGI_INDEX_8_BIT_DISP, ///< Address Register Indirect With Index- 8-bit displacement M68K_AM_AREGI_INDEX_BASE_DISP, ///< Address Register Indirect With Index- Base displacement M68K_AM_MEMI_POST_INDEX, ///< Memory indirect - Postindex M68K_AM_MEMI_PRE_INDEX, ///< Memory indirect - Preindex M68K_AM_PCI_DISP, ///< Program Counter Indirect - with Displacement M68K_AM_PCI_INDEX_8_BIT_DISP, ///< Program Counter Indirect with Index - with 8-Bit Displacement M68K_AM_PCI_INDEX_BASE_DISP, ///< Program Counter Indirect with Index - with Base Displacement M68K_AM_PC_MEMI_POST_INDEX, ///< Program Counter Memory Indirect - Postindexed M68K_AM_PC_MEMI_PRE_INDEX, ///< Program Counter Memory Indirect - Preindexed M68K_AM_ABSOLUTE_DATA_SHORT, ///< Absolute Data Addressing - Short M68K_AM_ABSOLUTE_DATA_LONG, ///< Absolute Data Addressing - Long M68K_AM_IMMEDIATE, ///< Immediate value M68K_AM_BRANCH_DISPLACEMENT, ///< Address as displacement from (PC+2) used by branches } m68k_address_mode; /// Operand type for instruction's operands typedef enum m68k_op_type { M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). M68K_OP_REG, ///< = CS_OP_REG (Register operand). M68K_OP_IMM, ///< = CS_OP_IMM (Immediate operand). M68K_OP_MEM, ///< = CS_OP_MEM (Memory operand). M68K_OP_FP_SINGLE, ///< single precision Floating-Point operand M68K_OP_FP_DOUBLE, ///< double precision Floating-Point operand M68K_OP_REG_BITS, ///< Register bits move M68K_OP_REG_PAIR, ///< Register pair in the same op (upper 4 bits for first reg, lower for second) M68K_OP_BR_DISP, ///< Branch displacement } m68k_op_type; /// Instruction's operand referring to memory /// This is associated with M68K_OP_MEM operand type above typedef struct m68k_op_mem { m68k_reg base_reg; ///< base register (or M68K_REG_INVALID if irrelevant) m68k_reg index_reg; ///< index register (or M68K_REG_INVALID if irrelevant) m68k_reg in_base_reg; ///< indirect base register (or M68K_REG_INVALID if irrelevant) uint32_t in_disp; ///< indirect displacement uint32_t out_disp; ///< other displacement int16_t disp; ///< displacement value uint8_t scale; ///< scale for index register uint8_t bitfield; ///< set to true if the two values below should be used uint8_t width; ///< used for bf* instructions uint8_t offset; ///< used for bf* instructions uint8_t index_size; ///< 0 = w, 1 = l } m68k_op_mem; /// Operand type for instruction's operands typedef enum m68k_op_br_disp_size { M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). M68K_OP_BR_DISP_SIZE_BYTE = 1, ///< signed 8-bit displacement M68K_OP_BR_DISP_SIZE_WORD = 2, ///< signed 16-bit displacement M68K_OP_BR_DISP_SIZE_LONG = 4, ///< signed 32-bit displacement } m68k_op_br_disp_size; typedef struct m68k_op_br_disp { int32_t disp; ///< displacement value uint8_t disp_size; ///< Size from m68k_op_br_disp_size type above } m68k_op_br_disp; /// Register pair in one operand. typedef struct cs_m68k_op_reg_pair { m68k_reg reg_0; m68k_reg reg_1; } cs_m68k_op_reg_pair; /// Instruction operand typedef struct cs_m68k_op { union { uint64_t imm; ///< immediate value for IMM operand double dimm; ///< double imm float simm; ///< float imm m68k_reg reg; ///< register value for REG operand cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand }; m68k_op_mem mem; ///< data when operand is targeting memory m68k_op_br_disp br_disp; ///< data when operand is a branch displacement uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order) m68k_op_type type; m68k_address_mode address_mode; ///< M68K addressing mode for this op } cs_m68k_op; /// Operation size of the CPU instructions typedef enum m68k_cpu_size { M68K_CPU_SIZE_NONE = 0, ///< unsized or unspecified M68K_CPU_SIZE_BYTE = 1, ///< 1 byte in size M68K_CPU_SIZE_WORD = 2, ///< 2 bytes in size M68K_CPU_SIZE_LONG = 4, ///< 4 bytes in size } m68k_cpu_size; /// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed) typedef enum m68k_fpu_size { M68K_FPU_SIZE_NONE = 0, ///< unsized like fsave/frestore M68K_FPU_SIZE_SINGLE = 4, ///< 4 byte in size (single float) M68K_FPU_SIZE_DOUBLE = 8, ///< 8 byte in size (double) M68K_FPU_SIZE_EXTENDED = 12, ///< 12 byte in size (extended real format) } m68k_fpu_size; /// Type of size that is being used for the current instruction typedef enum m68k_size_type { M68K_SIZE_TYPE_INVALID = 0, M68K_SIZE_TYPE_CPU, M68K_SIZE_TYPE_FPU, } m68k_size_type; /// Operation size of the current instruction (NOT the actually size of instruction) typedef struct m68k_op_size { m68k_size_type type; union { m68k_cpu_size cpu_size; m68k_fpu_size fpu_size; }; } m68k_op_size; /// The M68K instruction and it's operands typedef struct cs_m68k { // Number of operands of this instruction or 0 when instruction has no operand. cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction. m68k_op_size op_size; ///< size of data operand works on in bytes (.b, .w, .l, etc) uint8_t op_count; ///< number of operands for the instruction } cs_m68k; /// M68K instruction typedef enum m68k_insn { M68K_INS_INVALID = 0, M68K_INS_ABCD, M68K_INS_ADD, M68K_INS_ADDA, M68K_INS_ADDI, M68K_INS_ADDQ, M68K_INS_ADDX, M68K_INS_AND, M68K_INS_ANDI, M68K_INS_ASL, M68K_INS_ASR, M68K_INS_BHS, M68K_INS_BLO, M68K_INS_BHI, M68K_INS_BLS, M68K_INS_BCC, M68K_INS_BCS, M68K_INS_BNE, M68K_INS_BEQ, M68K_INS_BVC, M68K_INS_BVS, M68K_INS_BPL, M68K_INS_BMI, M68K_INS_BGE, M68K_INS_BLT, M68K_INS_BGT, M68K_INS_BLE, M68K_INS_BRA, M68K_INS_BSR, M68K_INS_BCHG, M68K_INS_BCLR, M68K_INS_BSET, M68K_INS_BTST, M68K_INS_BFCHG, M68K_INS_BFCLR, M68K_INS_BFEXTS, M68K_INS_BFEXTU, M68K_INS_BFFFO, M68K_INS_BFINS, M68K_INS_BFSET, M68K_INS_BFTST, M68K_INS_BKPT, M68K_INS_CALLM, M68K_INS_CAS, M68K_INS_CAS2, M68K_INS_CHK, M68K_INS_CHK2, M68K_INS_CLR, M68K_INS_CMP, M68K_INS_CMPA, M68K_INS_CMPI, M68K_INS_CMPM, M68K_INS_CMP2, M68K_INS_CINVL, M68K_INS_CINVP, M68K_INS_CINVA, M68K_INS_CPUSHL, M68K_INS_CPUSHP, M68K_INS_CPUSHA, M68K_INS_DBT, M68K_INS_DBF, M68K_INS_DBHI, M68K_INS_DBLS, M68K_INS_DBCC, M68K_INS_DBCS, M68K_INS_DBNE, M68K_INS_DBEQ, M68K_INS_DBVC, M68K_INS_DBVS, M68K_INS_DBPL, M68K_INS_DBMI, M68K_INS_DBGE, M68K_INS_DBLT, M68K_INS_DBGT, M68K_INS_DBLE, M68K_INS_DBRA, M68K_INS_DIVS, M68K_INS_DIVSL, M68K_INS_DIVU, M68K_INS_DIVUL, M68K_INS_EOR, M68K_INS_EORI, M68K_INS_EXG, M68K_INS_EXT, M68K_INS_EXTB, M68K_INS_FABS, M68K_INS_FSABS, M68K_INS_FDABS, M68K_INS_FACOS, M68K_INS_FADD, M68K_INS_FSADD, M68K_INS_FDADD, M68K_INS_FASIN, M68K_INS_FATAN, M68K_INS_FATANH, M68K_INS_FBF, M68K_INS_FBEQ, M68K_INS_FBOGT, M68K_INS_FBOGE, M68K_INS_FBOLT, M68K_INS_FBOLE, M68K_INS_FBOGL, M68K_INS_FBOR, M68K_INS_FBUN, M68K_INS_FBUEQ, M68K_INS_FBUGT, M68K_INS_FBUGE, M68K_INS_FBULT, M68K_INS_FBULE, M68K_INS_FBNE, M68K_INS_FBT, M68K_INS_FBSF, M68K_INS_FBSEQ, M68K_INS_FBGT, M68K_INS_FBGE, M68K_INS_FBLT, M68K_INS_FBLE, M68K_INS_FBGL, M68K_INS_FBGLE, M68K_INS_FBNGLE, M68K_INS_FBNGL, M68K_INS_FBNLE, M68K_INS_FBNLT, M68K_INS_FBNGE, M68K_INS_FBNGT, M68K_INS_FBSNE, M68K_INS_FBST, M68K_INS_FCMP, M68K_INS_FCOS, M68K_INS_FCOSH, M68K_INS_FDBF, M68K_INS_FDBEQ, M68K_INS_FDBOGT, M68K_INS_FDBOGE, M68K_INS_FDBOLT, M68K_INS_FDBOLE, M68K_INS_FDBOGL, M68K_INS_FDBOR, M68K_INS_FDBUN, M68K_INS_FDBUEQ, M68K_INS_FDBUGT, M68K_INS_FDBUGE, M68K_INS_FDBULT, M68K_INS_FDBULE, M68K_INS_FDBNE, M68K_INS_FDBT, M68K_INS_FDBSF, M68K_INS_FDBSEQ, M68K_INS_FDBGT, M68K_INS_FDBGE, M68K_INS_FDBLT, M68K_INS_FDBLE, M68K_INS_FDBGL, M68K_INS_FDBGLE, M68K_INS_FDBNGLE, M68K_INS_FDBNGL, M68K_INS_FDBNLE, M68K_INS_FDBNLT, M68K_INS_FDBNGE, M68K_INS_FDBNGT, M68K_INS_FDBSNE, M68K_INS_FDBST, M68K_INS_FDIV, M68K_INS_FSDIV, M68K_INS_FDDIV, M68K_INS_FETOX, M68K_INS_FETOXM1, M68K_INS_FGETEXP, M68K_INS_FGETMAN, M68K_INS_FINT, M68K_INS_FINTRZ, M68K_INS_FLOG10, M68K_INS_FLOG2, M68K_INS_FLOGN, M68K_INS_FLOGNP1, M68K_INS_FMOD, M68K_INS_FMOVE, M68K_INS_FSMOVE, M68K_INS_FDMOVE, M68K_INS_FMOVECR, M68K_INS_FMOVEM, M68K_INS_FMUL, M68K_INS_FSMUL, M68K_INS_FDMUL, M68K_INS_FNEG, M68K_INS_FSNEG, M68K_INS_FDNEG, M68K_INS_FNOP, M68K_INS_FREM, M68K_INS_FRESTORE, M68K_INS_FSAVE, M68K_INS_FSCALE, M68K_INS_FSGLDIV, M68K_INS_FSGLMUL, M68K_INS_FSIN, M68K_INS_FSINCOS, M68K_INS_FSINH, M68K_INS_FSQRT, M68K_INS_FSSQRT, M68K_INS_FDSQRT, M68K_INS_FSF, M68K_INS_FSBEQ, M68K_INS_FSOGT, M68K_INS_FSOGE, M68K_INS_FSOLT, M68K_INS_FSOLE, M68K_INS_FSOGL, M68K_INS_FSOR, M68K_INS_FSUN, M68K_INS_FSUEQ, M68K_INS_FSUGT, M68K_INS_FSUGE, M68K_INS_FSULT, M68K_INS_FSULE, M68K_INS_FSNE, M68K_INS_FST, M68K_INS_FSSF, M68K_INS_FSSEQ, M68K_INS_FSGT, M68K_INS_FSGE, M68K_INS_FSLT, M68K_INS_FSLE, M68K_INS_FSGL, M68K_INS_FSGLE, M68K_INS_FSNGLE, M68K_INS_FSNGL, M68K_INS_FSNLE, M68K_INS_FSNLT, M68K_INS_FSNGE, M68K_INS_FSNGT, M68K_INS_FSSNE, M68K_INS_FSST, M68K_INS_FSUB, M68K_INS_FSSUB, M68K_INS_FDSUB, M68K_INS_FTAN, M68K_INS_FTANH, M68K_INS_FTENTOX, M68K_INS_FTRAPF, M68K_INS_FTRAPEQ, M68K_INS_FTRAPOGT, M68K_INS_FTRAPOGE, M68K_INS_FTRAPOLT, M68K_INS_FTRAPOLE, M68K_INS_FTRAPOGL, M68K_INS_FTRAPOR, M68K_INS_FTRAPUN, M68K_INS_FTRAPUEQ, M68K_INS_FTRAPUGT, M68K_INS_FTRAPUGE, M68K_INS_FTRAPULT, M68K_INS_FTRAPULE, M68K_INS_FTRAPNE, M68K_INS_FTRAPT, M68K_INS_FTRAPSF, M68K_INS_FTRAPSEQ, M68K_INS_FTRAPGT, M68K_INS_FTRAPGE, M68K_INS_FTRAPLT, M68K_INS_FTRAPLE, M68K_INS_FTRAPGL, M68K_INS_FTRAPGLE, M68K_INS_FTRAPNGLE, M68K_INS_FTRAPNGL, M68K_INS_FTRAPNLE, M68K_INS_FTRAPNLT, M68K_INS_FTRAPNGE, M68K_INS_FTRAPNGT, M68K_INS_FTRAPSNE, M68K_INS_FTRAPST, M68K_INS_FTST, M68K_INS_FTWOTOX, M68K_INS_HALT, M68K_INS_ILLEGAL, M68K_INS_JMP, M68K_INS_JSR, M68K_INS_LEA, M68K_INS_LINK, M68K_INS_LPSTOP, M68K_INS_LSL, M68K_INS_LSR, M68K_INS_MOVE, M68K_INS_MOVEA, M68K_INS_MOVEC, M68K_INS_MOVEM, M68K_INS_MOVEP, M68K_INS_MOVEQ, M68K_INS_MOVES, M68K_INS_MOVE16, M68K_INS_MULS, M68K_INS_MULU, M68K_INS_NBCD, M68K_INS_NEG, M68K_INS_NEGX, M68K_INS_NOP, M68K_INS_NOT, M68K_INS_OR, M68K_INS_ORI, M68K_INS_PACK, M68K_INS_PEA, M68K_INS_PFLUSH, M68K_INS_PFLUSHA, M68K_INS_PFLUSHAN, M68K_INS_PFLUSHN, M68K_INS_PLOADR, M68K_INS_PLOADW, M68K_INS_PLPAR, M68K_INS_PLPAW, M68K_INS_PMOVE, M68K_INS_PMOVEFD, M68K_INS_PTESTR, M68K_INS_PTESTW, M68K_INS_PULSE, M68K_INS_REMS, M68K_INS_REMU, M68K_INS_RESET, M68K_INS_ROL, M68K_INS_ROR, M68K_INS_ROXL, M68K_INS_ROXR, M68K_INS_RTD, M68K_INS_RTE, M68K_INS_RTM, M68K_INS_RTR, M68K_INS_RTS, M68K_INS_SBCD, M68K_INS_ST, M68K_INS_SF, M68K_INS_SHI, M68K_INS_SLS, M68K_INS_SCC, M68K_INS_SHS, M68K_INS_SCS, M68K_INS_SLO, M68K_INS_SNE, M68K_INS_SEQ, M68K_INS_SVC, M68K_INS_SVS, M68K_INS_SPL, M68K_INS_SMI, M68K_INS_SGE, M68K_INS_SLT, M68K_INS_SGT, M68K_INS_SLE, M68K_INS_STOP, M68K_INS_SUB, M68K_INS_SUBA, M68K_INS_SUBI, M68K_INS_SUBQ, M68K_INS_SUBX, M68K_INS_SWAP, M68K_INS_TAS, M68K_INS_TRAP, M68K_INS_TRAPV, M68K_INS_TRAPT, M68K_INS_TRAPF, M68K_INS_TRAPHI, M68K_INS_TRAPLS, M68K_INS_TRAPCC, M68K_INS_TRAPHS, M68K_INS_TRAPCS, M68K_INS_TRAPLO, M68K_INS_TRAPNE, M68K_INS_TRAPEQ, M68K_INS_TRAPVC, M68K_INS_TRAPVS, M68K_INS_TRAPPL, M68K_INS_TRAPMI, M68K_INS_TRAPGE, M68K_INS_TRAPLT, M68K_INS_TRAPGT, M68K_INS_TRAPLE, M68K_INS_TST, M68K_INS_UNLK, M68K_INS_UNPK, M68K_INS_ENDING, // <-- mark the end of the list of instructions } m68k_insn; /// Group of M68K instructions typedef enum m68k_group_type { M68K_GRP_INVALID = 0, ///< CS_GRUP_INVALID M68K_GRP_JUMP, ///< = CS_GRP_JUMP M68K_GRP_RET = 3, ///< = CS_GRP_RET M68K_GRP_IRET = 5, ///< = CS_GRP_IRET M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE M68K_GRP_ENDING,// <-- mark the end of the list of groups } m68k_group_type; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/mips.h000064400000000000000000000412240072674642500205660ustar 00000000000000#ifndef CAPSTONE_MIPS_H #define CAPSTONE_MIPS_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" // GCC MIPS toolchain has a default macro called "mips" which breaks // compilation #undef mips #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// Operand type for instruction's operands typedef enum mips_op_type { MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). MIPS_OP_REG, ///< = CS_OP_REG (Register operand). MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand). MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand). } mips_op_type; /// MIPS registers typedef enum mips_reg { MIPS_REG_INVALID = 0, // General purpose registers MIPS_REG_PC, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, // DSP registers MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, // ACC registers MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, // COP registers MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, // FPU registers MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, MIPS_REG_FCC6, MIPS_REG_FCC7, // AFPR128 MIPS_REG_W0, MIPS_REG_W1, MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, MIPS_REG_HI, MIPS_REG_LO, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_ENDING, // <-- mark the end of the list or registers // alias registers MIPS_REG_ZERO = MIPS_REG_0, MIPS_REG_AT = MIPS_REG_1, MIPS_REG_V0 = MIPS_REG_2, MIPS_REG_V1 = MIPS_REG_3, MIPS_REG_A0 = MIPS_REG_4, MIPS_REG_A1 = MIPS_REG_5, MIPS_REG_A2 = MIPS_REG_6, MIPS_REG_A3 = MIPS_REG_7, MIPS_REG_T0 = MIPS_REG_8, MIPS_REG_T1 = MIPS_REG_9, MIPS_REG_T2 = MIPS_REG_10, MIPS_REG_T3 = MIPS_REG_11, MIPS_REG_T4 = MIPS_REG_12, MIPS_REG_T5 = MIPS_REG_13, MIPS_REG_T6 = MIPS_REG_14, MIPS_REG_T7 = MIPS_REG_15, MIPS_REG_S0 = MIPS_REG_16, MIPS_REG_S1 = MIPS_REG_17, MIPS_REG_S2 = MIPS_REG_18, MIPS_REG_S3 = MIPS_REG_19, MIPS_REG_S4 = MIPS_REG_20, MIPS_REG_S5 = MIPS_REG_21, MIPS_REG_S6 = MIPS_REG_22, MIPS_REG_S7 = MIPS_REG_23, MIPS_REG_T8 = MIPS_REG_24, MIPS_REG_T9 = MIPS_REG_25, MIPS_REG_K0 = MIPS_REG_26, MIPS_REG_K1 = MIPS_REG_27, MIPS_REG_GP = MIPS_REG_28, MIPS_REG_SP = MIPS_REG_29, MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30, MIPS_REG_RA = MIPS_REG_31, MIPS_REG_HI0 = MIPS_REG_AC0, MIPS_REG_HI1 = MIPS_REG_AC1, MIPS_REG_HI2 = MIPS_REG_AC2, MIPS_REG_HI3 = MIPS_REG_AC3, MIPS_REG_LO0 = MIPS_REG_HI0, MIPS_REG_LO1 = MIPS_REG_HI1, MIPS_REG_LO2 = MIPS_REG_HI2, MIPS_REG_LO3 = MIPS_REG_HI3, } mips_reg; /// Instruction's operand referring to memory /// This is associated with MIPS_OP_MEM operand type above typedef struct mips_op_mem { mips_reg base; ///< base register int64_t disp; ///< displacement/offset value } mips_op_mem; /// Instruction operand typedef struct cs_mips_op { mips_op_type type; ///< operand type union { mips_reg reg; ///< register id for REG operand int64_t imm; ///< immediate value for IMM operand mips_op_mem mem; ///< base/index/scale/disp value for MEM operand }; } cs_mips_op; /// Instruction structure typedef struct cs_mips { /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_mips_op operands[10]; ///< operands for this instruction. } cs_mips; /// MIPS instruction typedef enum mips_insn { MIPS_INS_INVALID = 0, MIPS_INS_ABSQ_S, MIPS_INS_ADD, MIPS_INS_ADDIUPC, MIPS_INS_ADDIUR1SP, MIPS_INS_ADDIUR2, MIPS_INS_ADDIUS5, MIPS_INS_ADDIUSP, MIPS_INS_ADDQH, MIPS_INS_ADDQH_R, MIPS_INS_ADDQ, MIPS_INS_ADDQ_S, MIPS_INS_ADDSC, MIPS_INS_ADDS_A, MIPS_INS_ADDS_S, MIPS_INS_ADDS_U, MIPS_INS_ADDU16, MIPS_INS_ADDUH, MIPS_INS_ADDUH_R, MIPS_INS_ADDU, MIPS_INS_ADDU_S, MIPS_INS_ADDVI, MIPS_INS_ADDV, MIPS_INS_ADDWC, MIPS_INS_ADD_A, MIPS_INS_ADDI, MIPS_INS_ADDIU, MIPS_INS_ALIGN, MIPS_INS_ALUIPC, MIPS_INS_AND, MIPS_INS_AND16, MIPS_INS_ANDI16, MIPS_INS_ANDI, MIPS_INS_APPEND, MIPS_INS_ASUB_S, MIPS_INS_ASUB_U, MIPS_INS_AUI, MIPS_INS_AUIPC, MIPS_INS_AVER_S, MIPS_INS_AVER_U, MIPS_INS_AVE_S, MIPS_INS_AVE_U, MIPS_INS_B16, MIPS_INS_BADDU, MIPS_INS_BAL, MIPS_INS_BALC, MIPS_INS_BALIGN, MIPS_INS_BBIT0, MIPS_INS_BBIT032, MIPS_INS_BBIT1, MIPS_INS_BBIT132, MIPS_INS_BC, MIPS_INS_BC0F, MIPS_INS_BC0FL, MIPS_INS_BC0T, MIPS_INS_BC0TL, MIPS_INS_BC1EQZ, MIPS_INS_BC1F, MIPS_INS_BC1FL, MIPS_INS_BC1NEZ, MIPS_INS_BC1T, MIPS_INS_BC1TL, MIPS_INS_BC2EQZ, MIPS_INS_BC2F, MIPS_INS_BC2FL, MIPS_INS_BC2NEZ, MIPS_INS_BC2T, MIPS_INS_BC2TL, MIPS_INS_BC3F, MIPS_INS_BC3FL, MIPS_INS_BC3T, MIPS_INS_BC3TL, MIPS_INS_BCLRI, MIPS_INS_BCLR, MIPS_INS_BEQ, MIPS_INS_BEQC, MIPS_INS_BEQL, MIPS_INS_BEQZ16, MIPS_INS_BEQZALC, MIPS_INS_BEQZC, MIPS_INS_BGEC, MIPS_INS_BGEUC, MIPS_INS_BGEZ, MIPS_INS_BGEZAL, MIPS_INS_BGEZALC, MIPS_INS_BGEZALL, MIPS_INS_BGEZALS, MIPS_INS_BGEZC, MIPS_INS_BGEZL, MIPS_INS_BGTZ, MIPS_INS_BGTZALC, MIPS_INS_BGTZC, MIPS_INS_BGTZL, MIPS_INS_BINSLI, MIPS_INS_BINSL, MIPS_INS_BINSRI, MIPS_INS_BINSR, MIPS_INS_BITREV, MIPS_INS_BITSWAP, MIPS_INS_BLEZ, MIPS_INS_BLEZALC, MIPS_INS_BLEZC, MIPS_INS_BLEZL, MIPS_INS_BLTC, MIPS_INS_BLTUC, MIPS_INS_BLTZ, MIPS_INS_BLTZAL, MIPS_INS_BLTZALC, MIPS_INS_BLTZALL, MIPS_INS_BLTZALS, MIPS_INS_BLTZC, MIPS_INS_BLTZL, MIPS_INS_BMNZI, MIPS_INS_BMNZ, MIPS_INS_BMZI, MIPS_INS_BMZ, MIPS_INS_BNE, MIPS_INS_BNEC, MIPS_INS_BNEGI, MIPS_INS_BNEG, MIPS_INS_BNEL, MIPS_INS_BNEZ16, MIPS_INS_BNEZALC, MIPS_INS_BNEZC, MIPS_INS_BNVC, MIPS_INS_BNZ, MIPS_INS_BOVC, MIPS_INS_BPOSGE32, MIPS_INS_BREAK, MIPS_INS_BREAK16, MIPS_INS_BSELI, MIPS_INS_BSEL, MIPS_INS_BSETI, MIPS_INS_BSET, MIPS_INS_BZ, MIPS_INS_BEQZ, MIPS_INS_B, MIPS_INS_BNEZ, MIPS_INS_BTEQZ, MIPS_INS_BTNEZ, MIPS_INS_CACHE, MIPS_INS_CEIL, MIPS_INS_CEQI, MIPS_INS_CEQ, MIPS_INS_CFC1, MIPS_INS_CFCMSA, MIPS_INS_CINS, MIPS_INS_CINS32, MIPS_INS_CLASS, MIPS_INS_CLEI_S, MIPS_INS_CLEI_U, MIPS_INS_CLE_S, MIPS_INS_CLE_U, MIPS_INS_CLO, MIPS_INS_CLTI_S, MIPS_INS_CLTI_U, MIPS_INS_CLT_S, MIPS_INS_CLT_U, MIPS_INS_CLZ, MIPS_INS_CMPGDU, MIPS_INS_CMPGU, MIPS_INS_CMPU, MIPS_INS_CMP, MIPS_INS_COPY_S, MIPS_INS_COPY_U, MIPS_INS_CTC1, MIPS_INS_CTCMSA, MIPS_INS_CVT, MIPS_INS_C, MIPS_INS_CMPI, MIPS_INS_DADD, MIPS_INS_DADDI, MIPS_INS_DADDIU, MIPS_INS_DADDU, MIPS_INS_DAHI, MIPS_INS_DALIGN, MIPS_INS_DATI, MIPS_INS_DAUI, MIPS_INS_DBITSWAP, MIPS_INS_DCLO, MIPS_INS_DCLZ, MIPS_INS_DDIV, MIPS_INS_DDIVU, MIPS_INS_DERET, MIPS_INS_DEXT, MIPS_INS_DEXTM, MIPS_INS_DEXTU, MIPS_INS_DI, MIPS_INS_DINS, MIPS_INS_DINSM, MIPS_INS_DINSU, MIPS_INS_DIV, MIPS_INS_DIVU, MIPS_INS_DIV_S, MIPS_INS_DIV_U, MIPS_INS_DLSA, MIPS_INS_DMFC0, MIPS_INS_DMFC1, MIPS_INS_DMFC2, MIPS_INS_DMOD, MIPS_INS_DMODU, MIPS_INS_DMTC0, MIPS_INS_DMTC1, MIPS_INS_DMTC2, MIPS_INS_DMUH, MIPS_INS_DMUHU, MIPS_INS_DMUL, MIPS_INS_DMULT, MIPS_INS_DMULTU, MIPS_INS_DMULU, MIPS_INS_DOTP_S, MIPS_INS_DOTP_U, MIPS_INS_DPADD_S, MIPS_INS_DPADD_U, MIPS_INS_DPAQX_SA, MIPS_INS_DPAQX_S, MIPS_INS_DPAQ_SA, MIPS_INS_DPAQ_S, MIPS_INS_DPAU, MIPS_INS_DPAX, MIPS_INS_DPA, MIPS_INS_DPOP, MIPS_INS_DPSQX_SA, MIPS_INS_DPSQX_S, MIPS_INS_DPSQ_SA, MIPS_INS_DPSQ_S, MIPS_INS_DPSUB_S, MIPS_INS_DPSUB_U, MIPS_INS_DPSU, MIPS_INS_DPSX, MIPS_INS_DPS, MIPS_INS_DROTR, MIPS_INS_DROTR32, MIPS_INS_DROTRV, MIPS_INS_DSBH, MIPS_INS_DSHD, MIPS_INS_DSLL, MIPS_INS_DSLL32, MIPS_INS_DSLLV, MIPS_INS_DSRA, MIPS_INS_DSRA32, MIPS_INS_DSRAV, MIPS_INS_DSRL, MIPS_INS_DSRL32, MIPS_INS_DSRLV, MIPS_INS_DSUB, MIPS_INS_DSUBU, MIPS_INS_EHB, MIPS_INS_EI, MIPS_INS_ERET, MIPS_INS_EXT, MIPS_INS_EXTP, MIPS_INS_EXTPDP, MIPS_INS_EXTPDPV, MIPS_INS_EXTPV, MIPS_INS_EXTRV_RS, MIPS_INS_EXTRV_R, MIPS_INS_EXTRV_S, MIPS_INS_EXTRV, MIPS_INS_EXTR_RS, MIPS_INS_EXTR_R, MIPS_INS_EXTR_S, MIPS_INS_EXTR, MIPS_INS_EXTS, MIPS_INS_EXTS32, MIPS_INS_ABS, MIPS_INS_FADD, MIPS_INS_FCAF, MIPS_INS_FCEQ, MIPS_INS_FCLASS, MIPS_INS_FCLE, MIPS_INS_FCLT, MIPS_INS_FCNE, MIPS_INS_FCOR, MIPS_INS_FCUEQ, MIPS_INS_FCULE, MIPS_INS_FCULT, MIPS_INS_FCUNE, MIPS_INS_FCUN, MIPS_INS_FDIV, MIPS_INS_FEXDO, MIPS_INS_FEXP2, MIPS_INS_FEXUPL, MIPS_INS_FEXUPR, MIPS_INS_FFINT_S, MIPS_INS_FFINT_U, MIPS_INS_FFQL, MIPS_INS_FFQR, MIPS_INS_FILL, MIPS_INS_FLOG2, MIPS_INS_FLOOR, MIPS_INS_FMADD, MIPS_INS_FMAX_A, MIPS_INS_FMAX, MIPS_INS_FMIN_A, MIPS_INS_FMIN, MIPS_INS_MOV, MIPS_INS_FMSUB, MIPS_INS_FMUL, MIPS_INS_MUL, MIPS_INS_NEG, MIPS_INS_FRCP, MIPS_INS_FRINT, MIPS_INS_FRSQRT, MIPS_INS_FSAF, MIPS_INS_FSEQ, MIPS_INS_FSLE, MIPS_INS_FSLT, MIPS_INS_FSNE, MIPS_INS_FSOR, MIPS_INS_FSQRT, MIPS_INS_SQRT, MIPS_INS_FSUB, MIPS_INS_SUB, MIPS_INS_FSUEQ, MIPS_INS_FSULE, MIPS_INS_FSULT, MIPS_INS_FSUNE, MIPS_INS_FSUN, MIPS_INS_FTINT_S, MIPS_INS_FTINT_U, MIPS_INS_FTQ, MIPS_INS_FTRUNC_S, MIPS_INS_FTRUNC_U, MIPS_INS_HADD_S, MIPS_INS_HADD_U, MIPS_INS_HSUB_S, MIPS_INS_HSUB_U, MIPS_INS_ILVEV, MIPS_INS_ILVL, MIPS_INS_ILVOD, MIPS_INS_ILVR, MIPS_INS_INS, MIPS_INS_INSERT, MIPS_INS_INSV, MIPS_INS_INSVE, MIPS_INS_J, MIPS_INS_JAL, MIPS_INS_JALR, MIPS_INS_JALRS16, MIPS_INS_JALRS, MIPS_INS_JALS, MIPS_INS_JALX, MIPS_INS_JIALC, MIPS_INS_JIC, MIPS_INS_JR, MIPS_INS_JR16, MIPS_INS_JRADDIUSP, MIPS_INS_JRC, MIPS_INS_JALRC, MIPS_INS_LB, MIPS_INS_LBU16, MIPS_INS_LBUX, MIPS_INS_LBU, MIPS_INS_LD, MIPS_INS_LDC1, MIPS_INS_LDC2, MIPS_INS_LDC3, MIPS_INS_LDI, MIPS_INS_LDL, MIPS_INS_LDPC, MIPS_INS_LDR, MIPS_INS_LDXC1, MIPS_INS_LH, MIPS_INS_LHU16, MIPS_INS_LHX, MIPS_INS_LHU, MIPS_INS_LI16, MIPS_INS_LL, MIPS_INS_LLD, MIPS_INS_LSA, MIPS_INS_LUXC1, MIPS_INS_LUI, MIPS_INS_LW, MIPS_INS_LW16, MIPS_INS_LWC1, MIPS_INS_LWC2, MIPS_INS_LWC3, MIPS_INS_LWL, MIPS_INS_LWM16, MIPS_INS_LWM32, MIPS_INS_LWPC, MIPS_INS_LWP, MIPS_INS_LWR, MIPS_INS_LWUPC, MIPS_INS_LWU, MIPS_INS_LWX, MIPS_INS_LWXC1, MIPS_INS_LWXS, MIPS_INS_LI, MIPS_INS_MADD, MIPS_INS_MADDF, MIPS_INS_MADDR_Q, MIPS_INS_MADDU, MIPS_INS_MADDV, MIPS_INS_MADD_Q, MIPS_INS_MAQ_SA, MIPS_INS_MAQ_S, MIPS_INS_MAXA, MIPS_INS_MAXI_S, MIPS_INS_MAXI_U, MIPS_INS_MAX_A, MIPS_INS_MAX, MIPS_INS_MAX_S, MIPS_INS_MAX_U, MIPS_INS_MFC0, MIPS_INS_MFC1, MIPS_INS_MFC2, MIPS_INS_MFHC1, MIPS_INS_MFHI, MIPS_INS_MFLO, MIPS_INS_MINA, MIPS_INS_MINI_S, MIPS_INS_MINI_U, MIPS_INS_MIN_A, MIPS_INS_MIN, MIPS_INS_MIN_S, MIPS_INS_MIN_U, MIPS_INS_MOD, MIPS_INS_MODSUB, MIPS_INS_MODU, MIPS_INS_MOD_S, MIPS_INS_MOD_U, MIPS_INS_MOVE, MIPS_INS_MOVEP, MIPS_INS_MOVF, MIPS_INS_MOVN, MIPS_INS_MOVT, MIPS_INS_MOVZ, MIPS_INS_MSUB, MIPS_INS_MSUBF, MIPS_INS_MSUBR_Q, MIPS_INS_MSUBU, MIPS_INS_MSUBV, MIPS_INS_MSUB_Q, MIPS_INS_MTC0, MIPS_INS_MTC1, MIPS_INS_MTC2, MIPS_INS_MTHC1, MIPS_INS_MTHI, MIPS_INS_MTHLIP, MIPS_INS_MTLO, MIPS_INS_MTM0, MIPS_INS_MTM1, MIPS_INS_MTM2, MIPS_INS_MTP0, MIPS_INS_MTP1, MIPS_INS_MTP2, MIPS_INS_MUH, MIPS_INS_MUHU, MIPS_INS_MULEQ_S, MIPS_INS_MULEU_S, MIPS_INS_MULQ_RS, MIPS_INS_MULQ_S, MIPS_INS_MULR_Q, MIPS_INS_MULSAQ_S, MIPS_INS_MULSA, MIPS_INS_MULT, MIPS_INS_MULTU, MIPS_INS_MULU, MIPS_INS_MULV, MIPS_INS_MUL_Q, MIPS_INS_MUL_S, MIPS_INS_NLOC, MIPS_INS_NLZC, MIPS_INS_NMADD, MIPS_INS_NMSUB, MIPS_INS_NOR, MIPS_INS_NORI, MIPS_INS_NOT16, MIPS_INS_NOT, MIPS_INS_OR, MIPS_INS_OR16, MIPS_INS_ORI, MIPS_INS_PACKRL, MIPS_INS_PAUSE, MIPS_INS_PCKEV, MIPS_INS_PCKOD, MIPS_INS_PCNT, MIPS_INS_PICK, MIPS_INS_POP, MIPS_INS_PRECEQU, MIPS_INS_PRECEQ, MIPS_INS_PRECEU, MIPS_INS_PRECRQU_S, MIPS_INS_PRECRQ, MIPS_INS_PRECRQ_RS, MIPS_INS_PRECR, MIPS_INS_PRECR_SRA, MIPS_INS_PRECR_SRA_R, MIPS_INS_PREF, MIPS_INS_PREPEND, MIPS_INS_RADDU, MIPS_INS_RDDSP, MIPS_INS_RDHWR, MIPS_INS_REPLV, MIPS_INS_REPL, MIPS_INS_RINT, MIPS_INS_ROTR, MIPS_INS_ROTRV, MIPS_INS_ROUND, MIPS_INS_SAT_S, MIPS_INS_SAT_U, MIPS_INS_SB, MIPS_INS_SB16, MIPS_INS_SC, MIPS_INS_SCD, MIPS_INS_SD, MIPS_INS_SDBBP, MIPS_INS_SDBBP16, MIPS_INS_SDC1, MIPS_INS_SDC2, MIPS_INS_SDC3, MIPS_INS_SDL, MIPS_INS_SDR, MIPS_INS_SDXC1, MIPS_INS_SEB, MIPS_INS_SEH, MIPS_INS_SELEQZ, MIPS_INS_SELNEZ, MIPS_INS_SEL, MIPS_INS_SEQ, MIPS_INS_SEQI, MIPS_INS_SH, MIPS_INS_SH16, MIPS_INS_SHF, MIPS_INS_SHILO, MIPS_INS_SHILOV, MIPS_INS_SHLLV, MIPS_INS_SHLLV_S, MIPS_INS_SHLL, MIPS_INS_SHLL_S, MIPS_INS_SHRAV, MIPS_INS_SHRAV_R, MIPS_INS_SHRA, MIPS_INS_SHRA_R, MIPS_INS_SHRLV, MIPS_INS_SHRL, MIPS_INS_SLDI, MIPS_INS_SLD, MIPS_INS_SLL, MIPS_INS_SLL16, MIPS_INS_SLLI, MIPS_INS_SLLV, MIPS_INS_SLT, MIPS_INS_SLTI, MIPS_INS_SLTIU, MIPS_INS_SLTU, MIPS_INS_SNE, MIPS_INS_SNEI, MIPS_INS_SPLATI, MIPS_INS_SPLAT, MIPS_INS_SRA, MIPS_INS_SRAI, MIPS_INS_SRARI, MIPS_INS_SRAR, MIPS_INS_SRAV, MIPS_INS_SRL, MIPS_INS_SRL16, MIPS_INS_SRLI, MIPS_INS_SRLRI, MIPS_INS_SRLR, MIPS_INS_SRLV, MIPS_INS_SSNOP, MIPS_INS_ST, MIPS_INS_SUBQH, MIPS_INS_SUBQH_R, MIPS_INS_SUBQ, MIPS_INS_SUBQ_S, MIPS_INS_SUBSUS_U, MIPS_INS_SUBSUU_S, MIPS_INS_SUBS_S, MIPS_INS_SUBS_U, MIPS_INS_SUBU16, MIPS_INS_SUBUH, MIPS_INS_SUBUH_R, MIPS_INS_SUBU, MIPS_INS_SUBU_S, MIPS_INS_SUBVI, MIPS_INS_SUBV, MIPS_INS_SUXC1, MIPS_INS_SW, MIPS_INS_SW16, MIPS_INS_SWC1, MIPS_INS_SWC2, MIPS_INS_SWC3, MIPS_INS_SWL, MIPS_INS_SWM16, MIPS_INS_SWM32, MIPS_INS_SWP, MIPS_INS_SWR, MIPS_INS_SWXC1, MIPS_INS_SYNC, MIPS_INS_SYNCI, MIPS_INS_SYSCALL, MIPS_INS_TEQ, MIPS_INS_TEQI, MIPS_INS_TGE, MIPS_INS_TGEI, MIPS_INS_TGEIU, MIPS_INS_TGEU, MIPS_INS_TLBP, MIPS_INS_TLBR, MIPS_INS_TLBWI, MIPS_INS_TLBWR, MIPS_INS_TLT, MIPS_INS_TLTI, MIPS_INS_TLTIU, MIPS_INS_TLTU, MIPS_INS_TNE, MIPS_INS_TNEI, MIPS_INS_TRUNC, MIPS_INS_V3MULU, MIPS_INS_VMM0, MIPS_INS_VMULU, MIPS_INS_VSHF, MIPS_INS_WAIT, MIPS_INS_WRDSP, MIPS_INS_WSBH, MIPS_INS_XOR, MIPS_INS_XOR16, MIPS_INS_XORI, //> some alias instructions MIPS_INS_NOP, MIPS_INS_NEGU, //> special instructions MIPS_INS_JALR_HB, // jump and link with Hazard Barrier MIPS_INS_JR_HB, // jump register with Hazard Barrier MIPS_INS_ENDING, } mips_insn; /// Group of MIPS instructions typedef enum mips_insn_group { MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) MIPS_GRP_JUMP, ///< = CS_GRP_JUMP // all call instructions MIPS_GRP_CALL, ///< = CS_GRP_CALL // all return instructions MIPS_GRP_RET, ///< = CS_GRP_RET // all interrupt instructions (int+syscall) MIPS_GRP_INT, ///< = CS_GRP_INT // all interrupt return instructions MIPS_GRP_IRET, ///< = CS_GRP_IRET // all privileged instructions MIPS_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE // all relative branching instructions MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE // Architecture-specific groups MIPS_GRP_BITCOUNT = 128, MIPS_GRP_DSP, MIPS_GRP_DSPR2, MIPS_GRP_FPIDX, MIPS_GRP_MSA, MIPS_GRP_MIPS32R2, MIPS_GRP_MIPS64, MIPS_GRP_MIPS64R2, MIPS_GRP_SEINREG, MIPS_GRP_STDENC, MIPS_GRP_SWAP, MIPS_GRP_MICROMIPS, MIPS_GRP_MIPS16MODE, MIPS_GRP_FP64BIT, MIPS_GRP_NONANSFPMATH, MIPS_GRP_NOTFP64BIT, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_CNMIPS, MIPS_GRP_MIPS32, MIPS_GRP_MIPS32R6, MIPS_GRP_MIPS64R6, MIPS_GRP_MIPS2, MIPS_GRP_MIPS3, MIPS_GRP_MIPS3_32, MIPS_GRP_MIPS3_32R2, MIPS_GRP_MIPS4_32, MIPS_GRP_MIPS4_32R2, MIPS_GRP_MIPS5_32R2, MIPS_GRP_GP32BIT, MIPS_GRP_GP64BIT, MIPS_GRP_ENDING, } mips_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/mos65xx.h000064400000000000000000000132330072674642500211460ustar 00000000000000#ifndef CAPSTONE_MOS65XX_H #define CAPSTONE_MOS65XX_H /* Capstone Disassembly Engine */ /* By Sebastian Macke C99 is supported #include #endif // (_MSC_VER < 1800) || defined(_KERNEL_MODE) #else // not MSVC -> C99 is supported #include #endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) // handle inttypes.h / stdint.h compatibility #if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) #include "windowsce/stdint.h" #endif // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) #if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) // this system does not have inttypes.h #if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) // this system does not have stdint.h typedef signed char int8_t; typedef signed short int16_t; typedef signed int int32_t; typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; #endif // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE)) #if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) #define INT8_MIN (-127i8 - 1) #define INT16_MIN (-32767i16 - 1) #define INT32_MIN (-2147483647i32 - 1) #define INT64_MIN (-9223372036854775807i64 - 1) #define INT8_MAX 127i8 #define INT16_MAX 32767i16 #define INT32_MAX 2147483647i32 #define INT64_MAX 9223372036854775807i64 #define UINT8_MAX 0xffui8 #define UINT16_MAX 0xffffui16 #define UINT32_MAX 0xffffffffui32 #define UINT64_MAX 0xffffffffffffffffui64 #endif // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) #ifdef CAPSTONE_HAS_OSXKERNEL // this system has stdint.h #include #endif #define __PRI_8_LENGTH_MODIFIER__ "hh" #define __PRI_64_LENGTH_MODIFIER__ "ll" #define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" #define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" #define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" #define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" #define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" #define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" #define PRId16 "hd" #define PRIi16 "hi" #define PRIo16 "ho" #define PRIu16 "hu" #define PRIx16 "hx" #define PRIX16 "hX" #if defined(_MSC_VER) && _MSC_VER <= 1700 #define PRId32 "ld" #define PRIi32 "li" #define PRIo32 "lo" #define PRIu32 "lu" #define PRIx32 "lx" #define PRIX32 "lX" #else // OSX #define PRId32 "d" #define PRIi32 "i" #define PRIo32 "o" #define PRIu32 "u" #define PRIx32 "x" #define PRIX32 "X" #endif // defined(_MSC_VER) && _MSC_VER <= 1700 #if defined(_MSC_VER) && _MSC_VER <= 1700 // redefine functions from inttypes.h used in cstool #define strtoull _strtoui64 #endif #define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" #define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" #define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" #define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" #define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" #define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" #else // this system has inttypes.h by default #include #endif // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) #endif capstone-sys-0.15.0/capstone/include/capstone/ppc.h000064400000000000000000001112700072674642500203770ustar 00000000000000#ifndef CAPSTONE_PPC_H #define CAPSTONE_PPC_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// PPC branch codes for some branch instructions typedef enum ppc_bc { PPC_BC_INVALID = 0, PPC_BC_LT = (0 << 5) | 12, PPC_BC_LE = (1 << 5) | 4, PPC_BC_EQ = (2 << 5) | 12, PPC_BC_GE = (0 << 5) | 4, PPC_BC_GT = (1 << 5) | 12, PPC_BC_NE = (2 << 5) | 4, PPC_BC_UN = (3 << 5) | 12, PPC_BC_NU = (3 << 5) | 4, // extra conditions PPC_BC_SO = (4 << 5) | 12, ///< summary overflow PPC_BC_NS = (4 << 5) | 4, ///< not summary overflow } ppc_bc; /// PPC branch hint for some branch instructions typedef enum ppc_bh { PPC_BH_INVALID = 0, ///< no hint PPC_BH_PLUS, ///< PLUS hint PPC_BH_MINUS, ///< MINUS hint } ppc_bh; /// Operand type for instruction's operands typedef enum ppc_op_type { PPC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). PPC_OP_REG, ///< = CS_OP_REG (Register operand). PPC_OP_IMM, ///< = CS_OP_IMM (Immediate operand). PPC_OP_MEM, ///< = CS_OP_MEM (Memory operand). PPC_OP_CRX = 64, ///< Condition Register field } ppc_op_type; /// PPC registers typedef enum ppc_reg { PPC_REG_INVALID = 0, PPC_REG_CARRY = 2, PPC_REG_CTR = 3, PPC_REG_LR = 5, PPC_REG_RM = 6, PPC_REG_VRSAVE = 8, PPC_REG_XER = 9, PPC_REG_ZERO = 10, PPC_REG_CR0 = 12, PPC_REG_CR1 = 13, PPC_REG_CR2 = 14, PPC_REG_CR3 = 15, PPC_REG_CR4 = 16, PPC_REG_CR5 = 17, PPC_REG_CR6 = 18, PPC_REG_CR7 = 19, PPC_REG_CTR8 = 20, PPC_REG_F0 = 21, PPC_REG_F1 = 22, PPC_REG_F2 = 23, PPC_REG_F3 = 24, PPC_REG_F4 = 25, PPC_REG_F5 = 26, PPC_REG_F6 = 27, PPC_REG_F7 = 28, PPC_REG_F8 = 29, PPC_REG_F9 = 30, PPC_REG_F10 = 31, PPC_REG_F11 = 32, PPC_REG_F12 = 33, PPC_REG_F13 = 34, PPC_REG_F14 = 35, PPC_REG_F15 = 36, PPC_REG_F16 = 37, PPC_REG_F17 = 38, PPC_REG_F18 = 39, PPC_REG_F19 = 40, PPC_REG_F20 = 41, PPC_REG_F21 = 42, PPC_REG_F22 = 43, PPC_REG_F23 = 44, PPC_REG_F24 = 45, PPC_REG_F25 = 46, PPC_REG_F26 = 47, PPC_REG_F27 = 48, PPC_REG_F28 = 49, PPC_REG_F29 = 50, PPC_REG_F30 = 51, PPC_REG_F31 = 52, PPC_REG_LR8 = 54, PPC_REG_Q0 = 55, PPC_REG_Q1 = 56, PPC_REG_Q2 = 57, PPC_REG_Q3 = 58, PPC_REG_Q4 = 59, PPC_REG_Q5 = 60, PPC_REG_Q6 = 61, PPC_REG_Q7 = 62, PPC_REG_Q8 = 63, PPC_REG_Q9 = 64, PPC_REG_Q10 = 65, PPC_REG_Q11 = 66, PPC_REG_Q12 = 67, PPC_REG_Q13 = 68, PPC_REG_Q14 = 69, PPC_REG_Q15 = 70, PPC_REG_Q16 = 71, PPC_REG_Q17 = 72, PPC_REG_Q18 = 73, PPC_REG_Q19 = 74, PPC_REG_Q20 = 75, PPC_REG_Q21 = 76, PPC_REG_Q22 = 77, PPC_REG_Q23 = 78, PPC_REG_Q24 = 79, PPC_REG_Q25 = 80, PPC_REG_Q26 = 81, PPC_REG_Q27 = 82, PPC_REG_Q28 = 83, PPC_REG_Q29 = 84, PPC_REG_Q30 = 85, PPC_REG_Q31 = 86, PPC_REG_R0 = 87, PPC_REG_R1 = 88, PPC_REG_R2 = 89, PPC_REG_R3 = 90, PPC_REG_R4 = 91, PPC_REG_R5 = 92, PPC_REG_R6 = 93, PPC_REG_R7 = 94, PPC_REG_R8 = 95, PPC_REG_R9 = 96, PPC_REG_R10 = 97, PPC_REG_R11 = 98, PPC_REG_R12 = 99, PPC_REG_R13 = 100, PPC_REG_R14 = 101, PPC_REG_R15 = 102, PPC_REG_R16 = 103, PPC_REG_R17 = 104, PPC_REG_R18 = 105, PPC_REG_R19 = 106, PPC_REG_R20 = 107, PPC_REG_R21 = 108, PPC_REG_R22 = 109, PPC_REG_R23 = 110, PPC_REG_R24 = 111, PPC_REG_R25 = 112, PPC_REG_R26 = 113, PPC_REG_R27 = 114, PPC_REG_R28 = 115, PPC_REG_R29 = 116, PPC_REG_R30 = 117, PPC_REG_R31 = 118, PPC_REG_V0 = 151, PPC_REG_V1 = 152, PPC_REG_V2 = 153, PPC_REG_V3 = 154, PPC_REG_V4 = 155, PPC_REG_V5 = 156, PPC_REG_V6 = 157, PPC_REG_V7 = 158, PPC_REG_V8 = 159, PPC_REG_V9 = 160, PPC_REG_V10 = 161, PPC_REG_V11 = 162, PPC_REG_V12 = 163, PPC_REG_V13 = 164, PPC_REG_V14 = 165, PPC_REG_V15 = 166, PPC_REG_V16 = 167, PPC_REG_V17 = 168, PPC_REG_V18 = 169, PPC_REG_V19 = 170, PPC_REG_V20 = 171, PPC_REG_V21 = 172, PPC_REG_V22 = 173, PPC_REG_V23 = 174, PPC_REG_V24 = 175, PPC_REG_V25 = 176, PPC_REG_V26 = 177, PPC_REG_V27 = 178, PPC_REG_V28 = 179, PPC_REG_V29 = 180, PPC_REG_V30 = 181, PPC_REG_V31 = 182, PPC_REG_VS0 = 215, PPC_REG_VS1 = 216, PPC_REG_VS2 = 217, PPC_REG_VS3 = 218, PPC_REG_VS4 = 219, PPC_REG_VS5 = 220, PPC_REG_VS6 = 221, PPC_REG_VS7 = 222, PPC_REG_VS8 = 223, PPC_REG_VS9 = 224, PPC_REG_VS10 = 225, PPC_REG_VS11 = 226, PPC_REG_VS12 = 227, PPC_REG_VS13 = 228, PPC_REG_VS14 = 229, PPC_REG_VS15 = 230, PPC_REG_VS16 = 231, PPC_REG_VS17 = 232, PPC_REG_VS18 = 233, PPC_REG_VS19 = 234, PPC_REG_VS20 = 235, PPC_REG_VS21 = 236, PPC_REG_VS22 = 237, PPC_REG_VS23 = 238, PPC_REG_VS24 = 239, PPC_REG_VS25 = 240, PPC_REG_VS26 = 241, PPC_REG_VS27 = 242, PPC_REG_VS28 = 243, PPC_REG_VS29 = 244, PPC_REG_VS30 = 245, PPC_REG_VS31 = 246, PPC_REG_VS32 = 247, PPC_REG_VS33 = 248, PPC_REG_VS34 = 249, PPC_REG_VS35 = 250, PPC_REG_VS36 = 251, PPC_REG_VS37 = 252, PPC_REG_VS38 = 253, PPC_REG_VS39 = 254, PPC_REG_VS40 = 255, PPC_REG_VS41 = 256, PPC_REG_VS42 = 257, PPC_REG_VS43 = 258, PPC_REG_VS44 = 259, PPC_REG_VS45 = 260, PPC_REG_VS46 = 261, PPC_REG_VS47 = 262, PPC_REG_VS48 = 263, PPC_REG_VS49 = 264, PPC_REG_VS50 = 265, PPC_REG_VS51 = 266, PPC_REG_VS52 = 267, PPC_REG_VS53 = 268, PPC_REG_VS54 = 269, PPC_REG_VS55 = 270, PPC_REG_VS56 = 271, PPC_REG_VS57 = 272, PPC_REG_VS58 = 273, PPC_REG_VS59 = 274, PPC_REG_VS60 = 275, PPC_REG_VS61 = 276, PPC_REG_VS62 = 277, PPC_REG_VS63 = 278, PPC_REG_CR0EQ = 312, PPC_REG_CR1EQ = 313, PPC_REG_CR2EQ = 314, PPC_REG_CR3EQ = 315, PPC_REG_CR4EQ = 316, PPC_REG_CR5EQ = 317, PPC_REG_CR6EQ = 318, PPC_REG_CR7EQ = 319, PPC_REG_CR0GT = 320, PPC_REG_CR1GT = 321, PPC_REG_CR2GT = 322, PPC_REG_CR3GT = 323, PPC_REG_CR4GT = 324, PPC_REG_CR5GT = 325, PPC_REG_CR6GT = 326, PPC_REG_CR7GT = 327, PPC_REG_CR0LT = 328, PPC_REG_CR1LT = 329, PPC_REG_CR2LT = 330, PPC_REG_CR3LT = 331, PPC_REG_CR4LT = 332, PPC_REG_CR5LT = 333, PPC_REG_CR6LT = 334, PPC_REG_CR7LT = 335, PPC_REG_CR0UN = 336, PPC_REG_CR1UN = 337, PPC_REG_CR2UN = 338, PPC_REG_CR3UN = 339, PPC_REG_CR4UN = 340, PPC_REG_CR5UN = 341, PPC_REG_CR6UN = 342, PPC_REG_CR7UN = 343, PPC_REG_ENDING, // <-- mark the end of the list of registers } ppc_reg; /// Instruction's operand referring to memory /// This is associated with PPC_OP_MEM operand type above typedef struct ppc_op_mem { ppc_reg base; ///< base register int32_t disp; ///< displacement/offset value } ppc_op_mem; typedef struct ppc_op_crx { unsigned int scale; ppc_reg reg; ppc_bc cond; } ppc_op_crx; /// Instruction operand typedef struct cs_ppc_op { ppc_op_type type; ///< operand type union { ppc_reg reg; ///< register value for REG operand int64_t imm; ///< immediate value for IMM operand ppc_op_mem mem; ///< base/disp value for MEM operand ppc_op_crx crx; ///< operand with condition register }; } cs_ppc_op; /// Instruction structure typedef struct cs_ppc { /// branch code for branch instructions ppc_bc bc; /// branch hint for branch instructions ppc_bh bh; /// if update_cr0 = True, then this 'dot' insn updates CR0 bool update_cr0; /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_ppc_op operands[8]; ///< operands for this instruction. } cs_ppc; /// PPC instruction typedef enum ppc_insn { PPC_INS_INVALID = 0, PPC_INS_ADD, PPC_INS_ADDC, PPC_INS_ADDE, PPC_INS_ADDI, PPC_INS_ADDIC, PPC_INS_ADDIS, PPC_INS_ADDME, PPC_INS_ADDPCIS, PPC_INS_ADDZE, PPC_INS_AND, PPC_INS_ANDC, PPC_INS_ANDI, PPC_INS_ANDIS, PPC_INS_ATTN, PPC_INS_B, PPC_INS_BA, PPC_INS_BC, PPC_INS_BCA, PPC_INS_BCCTR, PPC_INS_BCCTRL, PPC_INS_BCDCFN, PPC_INS_BCDCFSQ, PPC_INS_BCDCFZ, PPC_INS_BCDCPSGN, PPC_INS_BCDCTN, PPC_INS_BCDCTSQ, PPC_INS_BCDCTZ, PPC_INS_BCDS, PPC_INS_BCDSETSGN, PPC_INS_BCDSR, PPC_INS_BCDTRUNC, PPC_INS_BCDUS, PPC_INS_BCDUTRUNC, PPC_INS_BCL, PPC_INS_BCLA, PPC_INS_BCLR, PPC_INS_BCLRL, PPC_INS_BCTR, PPC_INS_BCTRL, PPC_INS_BDNZ, PPC_INS_BDNZA, PPC_INS_BDNZF, PPC_INS_BDNZFA, PPC_INS_BDNZFL, PPC_INS_BDNZFLA, PPC_INS_BDNZFLR, PPC_INS_BDNZFLRL, PPC_INS_BDNZL, PPC_INS_BDNZLA, PPC_INS_BDNZLR, PPC_INS_BDNZLRL, PPC_INS_BDNZT, PPC_INS_BDNZTA, PPC_INS_BDNZTL, PPC_INS_BDNZTLA, PPC_INS_BDNZTLR, PPC_INS_BDNZTLRL, PPC_INS_BDZ, PPC_INS_BDZA, PPC_INS_BDZF, PPC_INS_BDZFA, PPC_INS_BDZFL, PPC_INS_BDZFLA, PPC_INS_BDZFLR, PPC_INS_BDZFLRL, PPC_INS_BDZL, PPC_INS_BDZLA, PPC_INS_BDZLR, PPC_INS_BDZLRL, PPC_INS_BDZT, PPC_INS_BDZTA, PPC_INS_BDZTL, PPC_INS_BDZTLA, PPC_INS_BDZTLR, PPC_INS_BDZTLRL, PPC_INS_BEQ, PPC_INS_BEQA, PPC_INS_BEQCTR, PPC_INS_BEQCTRL, PPC_INS_BEQL, PPC_INS_BEQLA, PPC_INS_BEQLR, PPC_INS_BEQLRL, PPC_INS_BF, PPC_INS_BFA, PPC_INS_BFCTR, PPC_INS_BFCTRL, PPC_INS_BFL, PPC_INS_BFLA, PPC_INS_BFLR, PPC_INS_BFLRL, PPC_INS_BGE, PPC_INS_BGEA, PPC_INS_BGECTR, PPC_INS_BGECTRL, PPC_INS_BGEL, PPC_INS_BGELA, PPC_INS_BGELR, PPC_INS_BGELRL, PPC_INS_BGT, PPC_INS_BGTA, PPC_INS_BGTCTR, PPC_INS_BGTCTRL, PPC_INS_BGTL, PPC_INS_BGTLA, PPC_INS_BGTLR, PPC_INS_BGTLRL, PPC_INS_BL, PPC_INS_BLA, PPC_INS_BLE, PPC_INS_BLEA, PPC_INS_BLECTR, PPC_INS_BLECTRL, PPC_INS_BLEL, PPC_INS_BLELA, PPC_INS_BLELR, PPC_INS_BLELRL, PPC_INS_BLR, PPC_INS_BLRL, PPC_INS_BLT, PPC_INS_BLTA, PPC_INS_BLTCTR, PPC_INS_BLTCTRL, PPC_INS_BLTL, PPC_INS_BLTLA, PPC_INS_BLTLR, PPC_INS_BLTLRL, PPC_INS_BNE, PPC_INS_BNEA, PPC_INS_BNECTR, PPC_INS_BNECTRL, PPC_INS_BNEL, PPC_INS_BNELA, PPC_INS_BNELR, PPC_INS_BNELRL, PPC_INS_BNG, PPC_INS_BNGA, PPC_INS_BNGCTR, PPC_INS_BNGCTRL, PPC_INS_BNGL, PPC_INS_BNGLA, PPC_INS_BNGLR, PPC_INS_BNGLRL, PPC_INS_BNL, PPC_INS_BNLA, PPC_INS_BNLCTR, PPC_INS_BNLCTRL, PPC_INS_BNLL, PPC_INS_BNLLA, PPC_INS_BNLLR, PPC_INS_BNLLRL, PPC_INS_BNS, PPC_INS_BNSA, PPC_INS_BNSCTR, PPC_INS_BNSCTRL, PPC_INS_BNSL, PPC_INS_BNSLA, PPC_INS_BNSLR, PPC_INS_BNSLRL, PPC_INS_BNU, PPC_INS_BNUA, PPC_INS_BNUCTR, PPC_INS_BNUCTRL, PPC_INS_BNUL, PPC_INS_BNULA, PPC_INS_BNULR, PPC_INS_BNULRL, PPC_INS_BPERMD, PPC_INS_BRINC, PPC_INS_BSO, PPC_INS_BSOA, PPC_INS_BSOCTR, PPC_INS_BSOCTRL, PPC_INS_BSOL, PPC_INS_BSOLA, PPC_INS_BSOLR, PPC_INS_BSOLRL, PPC_INS_BT, PPC_INS_BTA, PPC_INS_BTCTR, PPC_INS_BTCTRL, PPC_INS_BTL, PPC_INS_BTLA, PPC_INS_BTLR, PPC_INS_BTLRL, PPC_INS_BUN, PPC_INS_BUNA, PPC_INS_BUNCTR, PPC_INS_BUNCTRL, PPC_INS_BUNL, PPC_INS_BUNLA, PPC_INS_BUNLR, PPC_INS_BUNLRL, PPC_INS_CLRBHRB, PPC_INS_CLRLDI, PPC_INS_CLRLSLDI, PPC_INS_CLRLSLWI, PPC_INS_CLRLWI, PPC_INS_CLRRDI, PPC_INS_CLRRWI, PPC_INS_CMP, PPC_INS_CMPB, PPC_INS_CMPD, PPC_INS_CMPDI, PPC_INS_CMPEQB, PPC_INS_CMPI, PPC_INS_CMPL, PPC_INS_CMPLD, PPC_INS_CMPLDI, PPC_INS_CMPLI, PPC_INS_CMPLW, PPC_INS_CMPLWI, PPC_INS_CMPRB, PPC_INS_CMPW, PPC_INS_CMPWI, PPC_INS_CNTLZD, PPC_INS_CNTLZW, PPC_INS_CNTTZD, PPC_INS_CNTTZW, PPC_INS_COPY, PPC_INS_COPY_FIRST, PPC_INS_CP_ABORT, PPC_INS_CRAND, PPC_INS_CRANDC, PPC_INS_CRCLR, PPC_INS_CREQV, PPC_INS_CRMOVE, PPC_INS_CRNAND, PPC_INS_CRNOR, PPC_INS_CRNOT, PPC_INS_CROR, PPC_INS_CRORC, PPC_INS_CRSET, PPC_INS_CRXOR, PPC_INS_DARN, PPC_INS_DCBA, PPC_INS_DCBF, PPC_INS_DCBFEP, PPC_INS_DCBFL, PPC_INS_DCBFLP, PPC_INS_DCBI, PPC_INS_DCBST, PPC_INS_DCBSTEP, PPC_INS_DCBT, PPC_INS_DCBTCT, PPC_INS_DCBTDS, PPC_INS_DCBTEP, PPC_INS_DCBTST, PPC_INS_DCBTSTCT, PPC_INS_DCBTSTDS, PPC_INS_DCBTSTEP, PPC_INS_DCBTSTT, PPC_INS_DCBTT, PPC_INS_DCBZ, PPC_INS_DCBZEP, PPC_INS_DCBZL, PPC_INS_DCBZLEP, PPC_INS_DCCCI, PPC_INS_DCI, PPC_INS_DIVD, PPC_INS_DIVDE, PPC_INS_DIVDEU, PPC_INS_DIVDU, PPC_INS_DIVW, PPC_INS_DIVWE, PPC_INS_DIVWEU, PPC_INS_DIVWU, PPC_INS_DSS, PPC_INS_DSSALL, PPC_INS_DST, PPC_INS_DSTST, PPC_INS_DSTSTT, PPC_INS_DSTT, PPC_INS_EFDABS, PPC_INS_EFDADD, PPC_INS_EFDCFS, PPC_INS_EFDCFSF, PPC_INS_EFDCFSI, PPC_INS_EFDCFSID, PPC_INS_EFDCFUF, PPC_INS_EFDCFUI, PPC_INS_EFDCFUID, PPC_INS_EFDCMPEQ, PPC_INS_EFDCMPGT, PPC_INS_EFDCMPLT, PPC_INS_EFDCTSF, PPC_INS_EFDCTSI, PPC_INS_EFDCTSIDZ, PPC_INS_EFDCTSIZ, PPC_INS_EFDCTUF, PPC_INS_EFDCTUI, PPC_INS_EFDCTUIDZ, PPC_INS_EFDCTUIZ, PPC_INS_EFDDIV, PPC_INS_EFDMUL, PPC_INS_EFDNABS, PPC_INS_EFDNEG, PPC_INS_EFDSUB, PPC_INS_EFDTSTEQ, PPC_INS_EFDTSTGT, PPC_INS_EFDTSTLT, PPC_INS_EFSABS, PPC_INS_EFSADD, PPC_INS_EFSCFD, PPC_INS_EFSCFSF, PPC_INS_EFSCFSI, PPC_INS_EFSCFUF, PPC_INS_EFSCFUI, PPC_INS_EFSCMPEQ, PPC_INS_EFSCMPGT, PPC_INS_EFSCMPLT, PPC_INS_EFSCTSF, PPC_INS_EFSCTSI, PPC_INS_EFSCTSIZ, PPC_INS_EFSCTUF, PPC_INS_EFSCTUI, PPC_INS_EFSCTUIZ, PPC_INS_EFSDIV, PPC_INS_EFSMUL, PPC_INS_EFSNABS, PPC_INS_EFSNEG, PPC_INS_EFSSUB, PPC_INS_EFSTSTEQ, PPC_INS_EFSTSTGT, PPC_INS_EFSTSTLT, PPC_INS_EIEIO, PPC_INS_EQV, PPC_INS_EVABS, PPC_INS_EVADDIW, PPC_INS_EVADDSMIAAW, PPC_INS_EVADDSSIAAW, PPC_INS_EVADDUMIAAW, PPC_INS_EVADDUSIAAW, PPC_INS_EVADDW, PPC_INS_EVAND, PPC_INS_EVANDC, PPC_INS_EVCMPEQ, PPC_INS_EVCMPGTS, PPC_INS_EVCMPGTU, PPC_INS_EVCMPLTS, PPC_INS_EVCMPLTU, PPC_INS_EVCNTLSW, PPC_INS_EVCNTLZW, PPC_INS_EVDIVWS, PPC_INS_EVDIVWU, PPC_INS_EVEQV, PPC_INS_EVEXTSB, PPC_INS_EVEXTSH, PPC_INS_EVFSABS, PPC_INS_EVFSADD, PPC_INS_EVFSCFSF, PPC_INS_EVFSCFSI, PPC_INS_EVFSCFUF, PPC_INS_EVFSCFUI, PPC_INS_EVFSCMPEQ, PPC_INS_EVFSCMPGT, PPC_INS_EVFSCMPLT, PPC_INS_EVFSCTSF, PPC_INS_EVFSCTSI, PPC_INS_EVFSCTSIZ, PPC_INS_EVFSCTUI, PPC_INS_EVFSDIV, PPC_INS_EVFSMUL, PPC_INS_EVFSNABS, PPC_INS_EVFSNEG, PPC_INS_EVFSSUB, PPC_INS_EVFSTSTEQ, PPC_INS_EVFSTSTGT, PPC_INS_EVFSTSTLT, PPC_INS_EVLDD, PPC_INS_EVLDDX, PPC_INS_EVLDH, PPC_INS_EVLDHX, PPC_INS_EVLDW, PPC_INS_EVLDWX, PPC_INS_EVLHHESPLAT, PPC_INS_EVLHHESPLATX, PPC_INS_EVLHHOSSPLAT, PPC_INS_EVLHHOSSPLATX, PPC_INS_EVLHHOUSPLAT, PPC_INS_EVLHHOUSPLATX, PPC_INS_EVLWHE, PPC_INS_EVLWHEX, PPC_INS_EVLWHOS, PPC_INS_EVLWHOSX, PPC_INS_EVLWHOU, PPC_INS_EVLWHOUX, PPC_INS_EVLWHSPLAT, PPC_INS_EVLWHSPLATX, PPC_INS_EVLWWSPLAT, PPC_INS_EVLWWSPLATX, PPC_INS_EVMERGEHI, PPC_INS_EVMERGEHILO, PPC_INS_EVMERGELO, PPC_INS_EVMERGELOHI, PPC_INS_EVMHEGSMFAA, PPC_INS_EVMHEGSMFAN, PPC_INS_EVMHEGSMIAA, PPC_INS_EVMHEGSMIAN, PPC_INS_EVMHEGUMIAA, PPC_INS_EVMHEGUMIAN, PPC_INS_EVMHESMF, PPC_INS_EVMHESMFA, PPC_INS_EVMHESMFAAW, PPC_INS_EVMHESMFANW, PPC_INS_EVMHESMI, PPC_INS_EVMHESMIA, PPC_INS_EVMHESMIAAW, PPC_INS_EVMHESMIANW, PPC_INS_EVMHESSF, PPC_INS_EVMHESSFA, PPC_INS_EVMHESSFAAW, PPC_INS_EVMHESSFANW, PPC_INS_EVMHESSIAAW, PPC_INS_EVMHESSIANW, PPC_INS_EVMHEUMI, PPC_INS_EVMHEUMIA, PPC_INS_EVMHEUMIAAW, PPC_INS_EVMHEUMIANW, PPC_INS_EVMHEUSIAAW, PPC_INS_EVMHEUSIANW, PPC_INS_EVMHOGSMFAA, PPC_INS_EVMHOGSMFAN, PPC_INS_EVMHOGSMIAA, PPC_INS_EVMHOGSMIAN, PPC_INS_EVMHOGUMIAA, PPC_INS_EVMHOGUMIAN, PPC_INS_EVMHOSMF, PPC_INS_EVMHOSMFA, PPC_INS_EVMHOSMFAAW, PPC_INS_EVMHOSMFANW, PPC_INS_EVMHOSMI, PPC_INS_EVMHOSMIA, PPC_INS_EVMHOSMIAAW, PPC_INS_EVMHOSMIANW, PPC_INS_EVMHOSSF, PPC_INS_EVMHOSSFA, PPC_INS_EVMHOSSFAAW, PPC_INS_EVMHOSSFANW, PPC_INS_EVMHOSSIAAW, PPC_INS_EVMHOSSIANW, PPC_INS_EVMHOUMI, PPC_INS_EVMHOUMIA, PPC_INS_EVMHOUMIAAW, PPC_INS_EVMHOUMIANW, PPC_INS_EVMHOUSIAAW, PPC_INS_EVMHOUSIANW, PPC_INS_EVMRA, PPC_INS_EVMWHSMF, PPC_INS_EVMWHSMFA, PPC_INS_EVMWHSMI, PPC_INS_EVMWHSMIA, PPC_INS_EVMWHSSF, PPC_INS_EVMWHSSFA, PPC_INS_EVMWHUMI, PPC_INS_EVMWHUMIA, PPC_INS_EVMWLSMIAAW, PPC_INS_EVMWLSMIANW, PPC_INS_EVMWLSSIAAW, PPC_INS_EVMWLSSIANW, PPC_INS_EVMWLUMI, PPC_INS_EVMWLUMIA, PPC_INS_EVMWLUMIAAW, PPC_INS_EVMWLUMIANW, PPC_INS_EVMWLUSIAAW, PPC_INS_EVMWLUSIANW, PPC_INS_EVMWSMF, PPC_INS_EVMWSMFA, PPC_INS_EVMWSMFAA, PPC_INS_EVMWSMFAN, PPC_INS_EVMWSMI, PPC_INS_EVMWSMIA, PPC_INS_EVMWSMIAA, PPC_INS_EVMWSMIAN, PPC_INS_EVMWSSF, PPC_INS_EVMWSSFA, PPC_INS_EVMWSSFAA, PPC_INS_EVMWSSFAN, PPC_INS_EVMWUMI, PPC_INS_EVMWUMIA, PPC_INS_EVMWUMIAA, PPC_INS_EVMWUMIAN, PPC_INS_EVNAND, PPC_INS_EVNEG, PPC_INS_EVNOR, PPC_INS_EVOR, PPC_INS_EVORC, PPC_INS_EVRLW, PPC_INS_EVRLWI, PPC_INS_EVRNDW, PPC_INS_EVSEL, PPC_INS_EVSLW, PPC_INS_EVSLWI, PPC_INS_EVSPLATFI, PPC_INS_EVSPLATI, PPC_INS_EVSRWIS, PPC_INS_EVSRWIU, PPC_INS_EVSRWS, PPC_INS_EVSRWU, PPC_INS_EVSTDD, PPC_INS_EVSTDDX, PPC_INS_EVSTDH, PPC_INS_EVSTDHX, PPC_INS_EVSTDW, PPC_INS_EVSTDWX, PPC_INS_EVSTWHE, PPC_INS_EVSTWHEX, PPC_INS_EVSTWHO, PPC_INS_EVSTWHOX, PPC_INS_EVSTWWE, PPC_INS_EVSTWWEX, PPC_INS_EVSTWWO, PPC_INS_EVSTWWOX, PPC_INS_EVSUBFSMIAAW, PPC_INS_EVSUBFSSIAAW, PPC_INS_EVSUBFUMIAAW, PPC_INS_EVSUBFUSIAAW, PPC_INS_EVSUBFW, PPC_INS_EVSUBIFW, PPC_INS_EVXOR, PPC_INS_EXTLDI, PPC_INS_EXTLWI, PPC_INS_EXTRDI, PPC_INS_EXTRWI, PPC_INS_EXTSB, PPC_INS_EXTSH, PPC_INS_EXTSW, PPC_INS_EXTSWSLI, PPC_INS_FABS, PPC_INS_FADD, PPC_INS_FADDS, PPC_INS_FCFID, PPC_INS_FCFIDS, PPC_INS_FCFIDU, PPC_INS_FCFIDUS, PPC_INS_FCMPU, PPC_INS_FCPSGN, PPC_INS_FCTID, PPC_INS_FCTIDU, PPC_INS_FCTIDUZ, PPC_INS_FCTIDZ, PPC_INS_FCTIW, PPC_INS_FCTIWU, PPC_INS_FCTIWUZ, PPC_INS_FCTIWZ, PPC_INS_FDIV, PPC_INS_FDIVS, PPC_INS_FMADD, PPC_INS_FMADDS, PPC_INS_FMR, PPC_INS_FMSUB, PPC_INS_FMSUBS, PPC_INS_FMUL, PPC_INS_FMULS, PPC_INS_FNABS, PPC_INS_FNEG, PPC_INS_FNMADD, PPC_INS_FNMADDS, PPC_INS_FNMSUB, PPC_INS_FNMSUBS, PPC_INS_FRE, PPC_INS_FRES, PPC_INS_FRIM, PPC_INS_FRIN, PPC_INS_FRIP, PPC_INS_FRIZ, PPC_INS_FRSP, PPC_INS_FRSQRTE, PPC_INS_FRSQRTES, PPC_INS_FSEL, PPC_INS_FSQRT, PPC_INS_FSQRTS, PPC_INS_FSUB, PPC_INS_FSUBS, PPC_INS_FTDIV, PPC_INS_FTSQRT, PPC_INS_HRFID, PPC_INS_ICBI, PPC_INS_ICBIEP, PPC_INS_ICBLC, PPC_INS_ICBLQ, PPC_INS_ICBT, PPC_INS_ICBTLS, PPC_INS_ICCCI, PPC_INS_ICI, PPC_INS_INSLWI, PPC_INS_INSRDI, PPC_INS_INSRWI, PPC_INS_ISEL, PPC_INS_ISYNC, PPC_INS_LA, PPC_INS_LBARX, PPC_INS_LBEPX, PPC_INS_LBZ, PPC_INS_LBZCIX, PPC_INS_LBZU, PPC_INS_LBZUX, PPC_INS_LBZX, PPC_INS_LD, PPC_INS_LDARX, PPC_INS_LDAT, PPC_INS_LDBRX, PPC_INS_LDCIX, PPC_INS_LDMX, PPC_INS_LDU, PPC_INS_LDUX, PPC_INS_LDX, PPC_INS_LFD, PPC_INS_LFDEPX, PPC_INS_LFDU, PPC_INS_LFDUX, PPC_INS_LFDX, PPC_INS_LFIWAX, PPC_INS_LFIWZX, PPC_INS_LFS, PPC_INS_LFSU, PPC_INS_LFSUX, PPC_INS_LFSX, PPC_INS_LHA, PPC_INS_LHARX, PPC_INS_LHAU, PPC_INS_LHAUX, PPC_INS_LHAX, PPC_INS_LHBRX, PPC_INS_LHEPX, PPC_INS_LHZ, PPC_INS_LHZCIX, PPC_INS_LHZU, PPC_INS_LHZUX, PPC_INS_LHZX, PPC_INS_LI, PPC_INS_LIS, PPC_INS_LMW, PPC_INS_LNIA, PPC_INS_LSWI, PPC_INS_LVEBX, PPC_INS_LVEHX, PPC_INS_LVEWX, PPC_INS_LVSL, PPC_INS_LVSR, PPC_INS_LVX, PPC_INS_LVXL, PPC_INS_LWA, PPC_INS_LWARX, PPC_INS_LWAT, PPC_INS_LWAUX, PPC_INS_LWAX, PPC_INS_LWBRX, PPC_INS_LWEPX, PPC_INS_LWSYNC, PPC_INS_LWZ, PPC_INS_LWZCIX, PPC_INS_LWZU, PPC_INS_LWZUX, PPC_INS_LWZX, PPC_INS_LXSD, PPC_INS_LXSDX, PPC_INS_LXSIBZX, PPC_INS_LXSIHZX, PPC_INS_LXSIWAX, PPC_INS_LXSIWZX, PPC_INS_LXSSP, PPC_INS_LXSSPX, PPC_INS_LXV, PPC_INS_LXVB16X, PPC_INS_LXVD2X, PPC_INS_LXVDSX, PPC_INS_LXVH8X, PPC_INS_LXVL, PPC_INS_LXVLL, PPC_INS_LXVW4X, PPC_INS_LXVWSX, PPC_INS_LXVX, PPC_INS_MADDHD, PPC_INS_MADDHDU, PPC_INS_MADDLD, PPC_INS_MBAR, PPC_INS_MCRF, PPC_INS_MCRFS, PPC_INS_MCRXRX, PPC_INS_MFAMR, PPC_INS_MFASR, PPC_INS_MFBHRBE, PPC_INS_MFBR0, PPC_INS_MFBR1, PPC_INS_MFBR2, PPC_INS_MFBR3, PPC_INS_MFBR4, PPC_INS_MFBR5, PPC_INS_MFBR6, PPC_INS_MFBR7, PPC_INS_MFCFAR, PPC_INS_MFCR, PPC_INS_MFCTR, PPC_INS_MFDAR, PPC_INS_MFDBATL, PPC_INS_MFDBATU, PPC_INS_MFDCCR, PPC_INS_MFDCR, PPC_INS_MFDEAR, PPC_INS_MFDEC, PPC_INS_MFDSCR, PPC_INS_MFDSISR, PPC_INS_MFESR, PPC_INS_MFFPRD, PPC_INS_MFFS, PPC_INS_MFFSCDRN, PPC_INS_MFFSCDRNI, PPC_INS_MFFSCE, PPC_INS_MFFSCRN, PPC_INS_MFFSCRNI, PPC_INS_MFFSL, PPC_INS_MFIBATL, PPC_INS_MFIBATU, PPC_INS_MFICCR, PPC_INS_MFLR, PPC_INS_MFMSR, PPC_INS_MFOCRF, PPC_INS_MFPID, PPC_INS_MFPMR, PPC_INS_MFPVR, PPC_INS_MFRTCL, PPC_INS_MFRTCU, PPC_INS_MFSDR1, PPC_INS_MFSPEFSCR, PPC_INS_MFSPR, PPC_INS_MFSPRG, PPC_INS_MFSPRG0, PPC_INS_MFSPRG1, PPC_INS_MFSPRG2, PPC_INS_MFSPRG3, PPC_INS_MFSPRG4, PPC_INS_MFSPRG5, PPC_INS_MFSPRG6, PPC_INS_MFSPRG7, PPC_INS_MFSR, PPC_INS_MFSRIN, PPC_INS_MFSRR0, PPC_INS_MFSRR1, PPC_INS_MFSRR2, PPC_INS_MFSRR3, PPC_INS_MFTB, PPC_INS_MFTBHI, PPC_INS_MFTBL, PPC_INS_MFTBLO, PPC_INS_MFTBU, PPC_INS_MFTCR, PPC_INS_MFVRD, PPC_INS_MFVRSAVE, PPC_INS_MFVSCR, PPC_INS_MFVSRD, PPC_INS_MFVSRLD, PPC_INS_MFVSRWZ, PPC_INS_MFXER, PPC_INS_MODSD, PPC_INS_MODSW, PPC_INS_MODUD, PPC_INS_MODUW, PPC_INS_MR, PPC_INS_MSGSYNC, PPC_INS_MSYNC, PPC_INS_MTAMR, PPC_INS_MTASR, PPC_INS_MTBR0, PPC_INS_MTBR1, PPC_INS_MTBR2, PPC_INS_MTBR3, PPC_INS_MTBR4, PPC_INS_MTBR5, PPC_INS_MTBR6, PPC_INS_MTBR7, PPC_INS_MTCFAR, PPC_INS_MTCR, PPC_INS_MTCRF, PPC_INS_MTCTR, PPC_INS_MTDAR, PPC_INS_MTDBATL, PPC_INS_MTDBATU, PPC_INS_MTDCCR, PPC_INS_MTDCR, PPC_INS_MTDEAR, PPC_INS_MTDEC, PPC_INS_MTDSCR, PPC_INS_MTDSISR, PPC_INS_MTESR, PPC_INS_MTFSB0, PPC_INS_MTFSB1, PPC_INS_MTFSF, PPC_INS_MTFSFI, PPC_INS_MTIBATL, PPC_INS_MTIBATU, PPC_INS_MTICCR, PPC_INS_MTLR, PPC_INS_MTMSR, PPC_INS_MTMSRD, PPC_INS_MTOCRF, PPC_INS_MTPID, PPC_INS_MTPMR, PPC_INS_MTSDR1, PPC_INS_MTSPEFSCR, PPC_INS_MTSPR, PPC_INS_MTSPRG, PPC_INS_MTSPRG0, PPC_INS_MTSPRG1, PPC_INS_MTSPRG2, PPC_INS_MTSPRG3, PPC_INS_MTSPRG4, PPC_INS_MTSPRG5, PPC_INS_MTSPRG6, PPC_INS_MTSPRG7, PPC_INS_MTSR, PPC_INS_MTSRIN, PPC_INS_MTSRR0, PPC_INS_MTSRR1, PPC_INS_MTSRR2, PPC_INS_MTSRR3, PPC_INS_MTTBHI, PPC_INS_MTTBL, PPC_INS_MTTBLO, PPC_INS_MTTBU, PPC_INS_MTTCR, PPC_INS_MTVRSAVE, PPC_INS_MTVSCR, PPC_INS_MTVSRD, PPC_INS_MTVSRDD, PPC_INS_MTVSRWA, PPC_INS_MTVSRWS, PPC_INS_MTVSRWZ, PPC_INS_MTXER, PPC_INS_MULHD, PPC_INS_MULHDU, PPC_INS_MULHW, PPC_INS_MULHWU, PPC_INS_MULLD, PPC_INS_MULLI, PPC_INS_MULLW, PPC_INS_NAND, PPC_INS_NAP, PPC_INS_NEG, PPC_INS_NOP, PPC_INS_NOR, PPC_INS_NOT, PPC_INS_OR, PPC_INS_ORC, PPC_INS_ORI, PPC_INS_ORIS, PPC_INS_PASTE, PPC_INS_PASTE_LAST, PPC_INS_POPCNTB, PPC_INS_POPCNTD, PPC_INS_POPCNTW, PPC_INS_PTESYNC, PPC_INS_QVALIGNI, PPC_INS_QVESPLATI, PPC_INS_QVFABS, PPC_INS_QVFADD, PPC_INS_QVFADDS, PPC_INS_QVFAND, PPC_INS_QVFANDC, PPC_INS_QVFCFID, PPC_INS_QVFCFIDS, PPC_INS_QVFCFIDU, PPC_INS_QVFCFIDUS, PPC_INS_QVFCLR, PPC_INS_QVFCMPEQ, PPC_INS_QVFCMPGT, PPC_INS_QVFCMPLT, PPC_INS_QVFCPSGN, PPC_INS_QVFCTFB, PPC_INS_QVFCTID, PPC_INS_QVFCTIDU, PPC_INS_QVFCTIDUZ, PPC_INS_QVFCTIDZ, PPC_INS_QVFCTIW, PPC_INS_QVFCTIWU, PPC_INS_QVFCTIWUZ, PPC_INS_QVFCTIWZ, PPC_INS_QVFEQU, PPC_INS_QVFLOGICAL, PPC_INS_QVFMADD, PPC_INS_QVFMADDS, PPC_INS_QVFMR, PPC_INS_QVFMSUB, PPC_INS_QVFMSUBS, PPC_INS_QVFMUL, PPC_INS_QVFMULS, PPC_INS_QVFNABS, PPC_INS_QVFNAND, PPC_INS_QVFNEG, PPC_INS_QVFNMADD, PPC_INS_QVFNMADDS, PPC_INS_QVFNMSUB, PPC_INS_QVFNMSUBS, PPC_INS_QVFNOR, PPC_INS_QVFNOT, PPC_INS_QVFOR, PPC_INS_QVFORC, PPC_INS_QVFPERM, PPC_INS_QVFRE, PPC_INS_QVFRES, PPC_INS_QVFRIM, PPC_INS_QVFRIN, PPC_INS_QVFRIP, PPC_INS_QVFRIZ, PPC_INS_QVFRSP, PPC_INS_QVFRSQRTE, PPC_INS_QVFRSQRTES, PPC_INS_QVFSEL, PPC_INS_QVFSET, PPC_INS_QVFSUB, PPC_INS_QVFSUBS, PPC_INS_QVFTSTNAN, PPC_INS_QVFXMADD, PPC_INS_QVFXMADDS, PPC_INS_QVFXMUL, PPC_INS_QVFXMULS, PPC_INS_QVFXOR, PPC_INS_QVFXXCPNMADD, PPC_INS_QVFXXCPNMADDS, PPC_INS_QVFXXMADD, PPC_INS_QVFXXMADDS, PPC_INS_QVFXXNPMADD, PPC_INS_QVFXXNPMADDS, PPC_INS_QVGPCI, PPC_INS_QVLFCDUX, PPC_INS_QVLFCDUXA, PPC_INS_QVLFCDX, PPC_INS_QVLFCDXA, PPC_INS_QVLFCSUX, PPC_INS_QVLFCSUXA, PPC_INS_QVLFCSX, PPC_INS_QVLFCSXA, PPC_INS_QVLFDUX, PPC_INS_QVLFDUXA, PPC_INS_QVLFDX, PPC_INS_QVLFDXA, PPC_INS_QVLFIWAX, PPC_INS_QVLFIWAXA, PPC_INS_QVLFIWZX, PPC_INS_QVLFIWZXA, PPC_INS_QVLFSUX, PPC_INS_QVLFSUXA, PPC_INS_QVLFSX, PPC_INS_QVLFSXA, PPC_INS_QVLPCLDX, PPC_INS_QVLPCLSX, PPC_INS_QVLPCRDX, PPC_INS_QVLPCRSX, PPC_INS_QVSTFCDUX, PPC_INS_QVSTFCDUXA, PPC_INS_QVSTFCDUXI, PPC_INS_QVSTFCDUXIA, PPC_INS_QVSTFCDX, PPC_INS_QVSTFCDXA, PPC_INS_QVSTFCDXI, PPC_INS_QVSTFCDXIA, PPC_INS_QVSTFCSUX, PPC_INS_QVSTFCSUXA, PPC_INS_QVSTFCSUXI, PPC_INS_QVSTFCSUXIA, PPC_INS_QVSTFCSX, PPC_INS_QVSTFCSXA, PPC_INS_QVSTFCSXI, PPC_INS_QVSTFCSXIA, PPC_INS_QVSTFDUX, PPC_INS_QVSTFDUXA, PPC_INS_QVSTFDUXI, PPC_INS_QVSTFDUXIA, PPC_INS_QVSTFDX, PPC_INS_QVSTFDXA, PPC_INS_QVSTFDXI, PPC_INS_QVSTFDXIA, PPC_INS_QVSTFIWX, PPC_INS_QVSTFIWXA, PPC_INS_QVSTFSUX, PPC_INS_QVSTFSUXA, PPC_INS_QVSTFSUXI, PPC_INS_QVSTFSUXIA, PPC_INS_QVSTFSX, PPC_INS_QVSTFSXA, PPC_INS_QVSTFSXI, PPC_INS_QVSTFSXIA, PPC_INS_RFCI, PPC_INS_RFDI, PPC_INS_RFEBB, PPC_INS_RFI, PPC_INS_RFID, PPC_INS_RFMCI, PPC_INS_RLDCL, PPC_INS_RLDCR, PPC_INS_RLDIC, PPC_INS_RLDICL, PPC_INS_RLDICR, PPC_INS_RLDIMI, PPC_INS_RLWIMI, PPC_INS_RLWINM, PPC_INS_RLWNM, PPC_INS_ROTLD, PPC_INS_ROTLDI, PPC_INS_ROTLW, PPC_INS_ROTLWI, PPC_INS_ROTRDI, PPC_INS_ROTRWI, PPC_INS_SC, PPC_INS_SETB, PPC_INS_SLBIA, PPC_INS_SLBIE, PPC_INS_SLBIEG, PPC_INS_SLBMFEE, PPC_INS_SLBMFEV, PPC_INS_SLBMTE, PPC_INS_SLBSYNC, PPC_INS_SLD, PPC_INS_SLDI, PPC_INS_SLW, PPC_INS_SLWI, PPC_INS_SRAD, PPC_INS_SRADI, PPC_INS_SRAW, PPC_INS_SRAWI, PPC_INS_SRD, PPC_INS_SRDI, PPC_INS_SRW, PPC_INS_SRWI, PPC_INS_STB, PPC_INS_STBCIX, PPC_INS_STBCX, PPC_INS_STBEPX, PPC_INS_STBU, PPC_INS_STBUX, PPC_INS_STBX, PPC_INS_STD, PPC_INS_STDAT, PPC_INS_STDBRX, PPC_INS_STDCIX, PPC_INS_STDCX, PPC_INS_STDU, PPC_INS_STDUX, PPC_INS_STDX, PPC_INS_STFD, PPC_INS_STFDEPX, PPC_INS_STFDU, PPC_INS_STFDUX, PPC_INS_STFDX, PPC_INS_STFIWX, PPC_INS_STFS, PPC_INS_STFSU, PPC_INS_STFSUX, PPC_INS_STFSX, PPC_INS_STH, PPC_INS_STHBRX, PPC_INS_STHCIX, PPC_INS_STHCX, PPC_INS_STHEPX, PPC_INS_STHU, PPC_INS_STHUX, PPC_INS_STHX, PPC_INS_STMW, PPC_INS_STOP, PPC_INS_STSWI, PPC_INS_STVEBX, PPC_INS_STVEHX, PPC_INS_STVEWX, PPC_INS_STVX, PPC_INS_STVXL, PPC_INS_STW, PPC_INS_STWAT, PPC_INS_STWBRX, PPC_INS_STWCIX, PPC_INS_STWCX, PPC_INS_STWEPX, PPC_INS_STWU, PPC_INS_STWUX, PPC_INS_STWX, PPC_INS_STXSD, PPC_INS_STXSDX, PPC_INS_STXSIBX, PPC_INS_STXSIHX, PPC_INS_STXSIWX, PPC_INS_STXSSP, PPC_INS_STXSSPX, PPC_INS_STXV, PPC_INS_STXVB16X, PPC_INS_STXVD2X, PPC_INS_STXVH8X, PPC_INS_STXVL, PPC_INS_STXVLL, PPC_INS_STXVW4X, PPC_INS_STXVX, PPC_INS_SUB, PPC_INS_SUBC, PPC_INS_SUBF, PPC_INS_SUBFC, PPC_INS_SUBFE, PPC_INS_SUBFIC, PPC_INS_SUBFME, PPC_INS_SUBFZE, PPC_INS_SUBI, PPC_INS_SUBIC, PPC_INS_SUBIS, PPC_INS_SUBPCIS, PPC_INS_SYNC, PPC_INS_TABORT, PPC_INS_TABORTDC, PPC_INS_TABORTDCI, PPC_INS_TABORTWC, PPC_INS_TABORTWCI, PPC_INS_TBEGIN, PPC_INS_TCHECK, PPC_INS_TD, PPC_INS_TDEQ, PPC_INS_TDEQI, PPC_INS_TDGE, PPC_INS_TDGEI, PPC_INS_TDGT, PPC_INS_TDGTI, PPC_INS_TDI, PPC_INS_TDLE, PPC_INS_TDLEI, PPC_INS_TDLGE, PPC_INS_TDLGEI, PPC_INS_TDLGT, PPC_INS_TDLGTI, PPC_INS_TDLLE, PPC_INS_TDLLEI, PPC_INS_TDLLT, PPC_INS_TDLLTI, PPC_INS_TDLNG, PPC_INS_TDLNGI, PPC_INS_TDLNL, PPC_INS_TDLNLI, PPC_INS_TDLT, PPC_INS_TDLTI, PPC_INS_TDNE, PPC_INS_TDNEI, PPC_INS_TDNG, PPC_INS_TDNGI, PPC_INS_TDNL, PPC_INS_TDNLI, PPC_INS_TDU, PPC_INS_TDUI, PPC_INS_TEND, PPC_INS_TLBIA, PPC_INS_TLBIE, PPC_INS_TLBIEL, PPC_INS_TLBIVAX, PPC_INS_TLBLD, PPC_INS_TLBLI, PPC_INS_TLBRE, PPC_INS_TLBREHI, PPC_INS_TLBRELO, PPC_INS_TLBSX, PPC_INS_TLBSYNC, PPC_INS_TLBWE, PPC_INS_TLBWEHI, PPC_INS_TLBWELO, PPC_INS_TRAP, PPC_INS_TRECHKPT, PPC_INS_TRECLAIM, PPC_INS_TSR, PPC_INS_TW, PPC_INS_TWEQ, PPC_INS_TWEQI, PPC_INS_TWGE, PPC_INS_TWGEI, PPC_INS_TWGT, PPC_INS_TWGTI, PPC_INS_TWI, PPC_INS_TWLE, PPC_INS_TWLEI, PPC_INS_TWLGE, PPC_INS_TWLGEI, PPC_INS_TWLGT, PPC_INS_TWLGTI, PPC_INS_TWLLE, PPC_INS_TWLLEI, PPC_INS_TWLLT, PPC_INS_TWLLTI, PPC_INS_TWLNG, PPC_INS_TWLNGI, PPC_INS_TWLNL, PPC_INS_TWLNLI, PPC_INS_TWLT, PPC_INS_TWLTI, PPC_INS_TWNE, PPC_INS_TWNEI, PPC_INS_TWNG, PPC_INS_TWNGI, PPC_INS_TWNL, PPC_INS_TWNLI, PPC_INS_TWU, PPC_INS_TWUI, PPC_INS_VABSDUB, PPC_INS_VABSDUH, PPC_INS_VABSDUW, PPC_INS_VADDCUQ, PPC_INS_VADDCUW, PPC_INS_VADDECUQ, PPC_INS_VADDEUQM, PPC_INS_VADDFP, PPC_INS_VADDSBS, PPC_INS_VADDSHS, PPC_INS_VADDSWS, PPC_INS_VADDUBM, PPC_INS_VADDUBS, PPC_INS_VADDUDM, PPC_INS_VADDUHM, PPC_INS_VADDUHS, PPC_INS_VADDUQM, PPC_INS_VADDUWM, PPC_INS_VADDUWS, PPC_INS_VAND, PPC_INS_VANDC, PPC_INS_VAVGSB, PPC_INS_VAVGSH, PPC_INS_VAVGSW, PPC_INS_VAVGUB, PPC_INS_VAVGUH, PPC_INS_VAVGUW, PPC_INS_VBPERMD, PPC_INS_VBPERMQ, PPC_INS_VCFSX, PPC_INS_VCFUX, PPC_INS_VCIPHER, PPC_INS_VCIPHERLAST, PPC_INS_VCLZB, PPC_INS_VCLZD, PPC_INS_VCLZH, PPC_INS_VCLZLSBB, PPC_INS_VCLZW, PPC_INS_VCMPBFP, PPC_INS_VCMPEQFP, PPC_INS_VCMPEQUB, PPC_INS_VCMPEQUD, PPC_INS_VCMPEQUH, PPC_INS_VCMPEQUW, PPC_INS_VCMPGEFP, PPC_INS_VCMPGTFP, PPC_INS_VCMPGTSB, PPC_INS_VCMPGTSD, PPC_INS_VCMPGTSH, PPC_INS_VCMPGTSW, PPC_INS_VCMPGTUB, PPC_INS_VCMPGTUD, PPC_INS_VCMPGTUH, PPC_INS_VCMPGTUW, PPC_INS_VCMPNEB, PPC_INS_VCMPNEH, PPC_INS_VCMPNEW, PPC_INS_VCMPNEZB, PPC_INS_VCMPNEZH, PPC_INS_VCMPNEZW, PPC_INS_VCTSXS, PPC_INS_VCTUXS, PPC_INS_VCTZB, PPC_INS_VCTZD, PPC_INS_VCTZH, PPC_INS_VCTZLSBB, PPC_INS_VCTZW, PPC_INS_VEQV, PPC_INS_VEXPTEFP, PPC_INS_VEXTRACTD, PPC_INS_VEXTRACTUB, PPC_INS_VEXTRACTUH, PPC_INS_VEXTRACTUW, PPC_INS_VEXTSB2D, PPC_INS_VEXTSB2W, PPC_INS_VEXTSH2D, PPC_INS_VEXTSH2W, PPC_INS_VEXTSW2D, PPC_INS_VEXTUBLX, PPC_INS_VEXTUBRX, PPC_INS_VEXTUHLX, PPC_INS_VEXTUHRX, PPC_INS_VEXTUWLX, PPC_INS_VEXTUWRX, PPC_INS_VGBBD, PPC_INS_VINSERTB, PPC_INS_VINSERTD, PPC_INS_VINSERTH, PPC_INS_VINSERTW, PPC_INS_VLOGEFP, PPC_INS_VMADDFP, PPC_INS_VMAXFP, PPC_INS_VMAXSB, PPC_INS_VMAXSD, PPC_INS_VMAXSH, PPC_INS_VMAXSW, PPC_INS_VMAXUB, PPC_INS_VMAXUD, PPC_INS_VMAXUH, PPC_INS_VMAXUW, PPC_INS_VMHADDSHS, PPC_INS_VMHRADDSHS, PPC_INS_VMINFP, PPC_INS_VMINSB, PPC_INS_VMINSD, PPC_INS_VMINSH, PPC_INS_VMINSW, PPC_INS_VMINUB, PPC_INS_VMINUD, PPC_INS_VMINUH, PPC_INS_VMINUW, PPC_INS_VMLADDUHM, PPC_INS_VMR, PPC_INS_VMRGEW, PPC_INS_VMRGHB, PPC_INS_VMRGHH, PPC_INS_VMRGHW, PPC_INS_VMRGLB, PPC_INS_VMRGLH, PPC_INS_VMRGLW, PPC_INS_VMRGOW, PPC_INS_VMSUMMBM, PPC_INS_VMSUMSHM, PPC_INS_VMSUMSHS, PPC_INS_VMSUMUBM, PPC_INS_VMSUMUHM, PPC_INS_VMSUMUHS, PPC_INS_VMUL10CUQ, PPC_INS_VMUL10ECUQ, PPC_INS_VMUL10EUQ, PPC_INS_VMUL10UQ, PPC_INS_VMULESB, PPC_INS_VMULESH, PPC_INS_VMULESW, PPC_INS_VMULEUB, PPC_INS_VMULEUH, PPC_INS_VMULEUW, PPC_INS_VMULOSB, PPC_INS_VMULOSH, PPC_INS_VMULOSW, PPC_INS_VMULOUB, PPC_INS_VMULOUH, PPC_INS_VMULOUW, PPC_INS_VMULUWM, PPC_INS_VNAND, PPC_INS_VNCIPHER, PPC_INS_VNCIPHERLAST, PPC_INS_VNEGD, PPC_INS_VNEGW, PPC_INS_VNMSUBFP, PPC_INS_VNOR, PPC_INS_VNOT, PPC_INS_VOR, PPC_INS_VORC, PPC_INS_VPERM, PPC_INS_VPERMR, PPC_INS_VPERMXOR, PPC_INS_VPKPX, PPC_INS_VPKSDSS, PPC_INS_VPKSDUS, PPC_INS_VPKSHSS, PPC_INS_VPKSHUS, PPC_INS_VPKSWSS, PPC_INS_VPKSWUS, PPC_INS_VPKUDUM, PPC_INS_VPKUDUS, PPC_INS_VPKUHUM, PPC_INS_VPKUHUS, PPC_INS_VPKUWUM, PPC_INS_VPKUWUS, PPC_INS_VPMSUMB, PPC_INS_VPMSUMD, PPC_INS_VPMSUMH, PPC_INS_VPMSUMW, PPC_INS_VPOPCNTB, PPC_INS_VPOPCNTD, PPC_INS_VPOPCNTH, PPC_INS_VPOPCNTW, PPC_INS_VPRTYBD, PPC_INS_VPRTYBQ, PPC_INS_VPRTYBW, PPC_INS_VREFP, PPC_INS_VRFIM, PPC_INS_VRFIN, PPC_INS_VRFIP, PPC_INS_VRFIZ, PPC_INS_VRLB, PPC_INS_VRLD, PPC_INS_VRLDMI, PPC_INS_VRLDNM, PPC_INS_VRLH, PPC_INS_VRLW, PPC_INS_VRLWMI, PPC_INS_VRLWNM, PPC_INS_VRSQRTEFP, PPC_INS_VSBOX, PPC_INS_VSEL, PPC_INS_VSHASIGMAD, PPC_INS_VSHASIGMAW, PPC_INS_VSL, PPC_INS_VSLB, PPC_INS_VSLD, PPC_INS_VSLDOI, PPC_INS_VSLH, PPC_INS_VSLO, PPC_INS_VSLV, PPC_INS_VSLW, PPC_INS_VSPLTB, PPC_INS_VSPLTH, PPC_INS_VSPLTISB, PPC_INS_VSPLTISH, PPC_INS_VSPLTISW, PPC_INS_VSPLTW, PPC_INS_VSR, PPC_INS_VSRAB, PPC_INS_VSRAD, PPC_INS_VSRAH, PPC_INS_VSRAW, PPC_INS_VSRB, PPC_INS_VSRD, PPC_INS_VSRH, PPC_INS_VSRO, PPC_INS_VSRV, PPC_INS_VSRW, PPC_INS_VSUBCUQ, PPC_INS_VSUBCUW, PPC_INS_VSUBECUQ, PPC_INS_VSUBEUQM, PPC_INS_VSUBFP, PPC_INS_VSUBSBS, PPC_INS_VSUBSHS, PPC_INS_VSUBSWS, PPC_INS_VSUBUBM, PPC_INS_VSUBUBS, PPC_INS_VSUBUDM, PPC_INS_VSUBUHM, PPC_INS_VSUBUHS, PPC_INS_VSUBUQM, PPC_INS_VSUBUWM, PPC_INS_VSUBUWS, PPC_INS_VSUM2SWS, PPC_INS_VSUM4SBS, PPC_INS_VSUM4SHS, PPC_INS_VSUM4UBS, PPC_INS_VSUMSWS, PPC_INS_VUPKHPX, PPC_INS_VUPKHSB, PPC_INS_VUPKHSH, PPC_INS_VUPKHSW, PPC_INS_VUPKLPX, PPC_INS_VUPKLSB, PPC_INS_VUPKLSH, PPC_INS_VUPKLSW, PPC_INS_VXOR, PPC_INS_WAIT, PPC_INS_WAITIMPL, PPC_INS_WAITRSV, PPC_INS_WRTEE, PPC_INS_WRTEEI, PPC_INS_XNOP, PPC_INS_XOR, PPC_INS_XORI, PPC_INS_XORIS, PPC_INS_XSABSDP, PPC_INS_XSABSQP, PPC_INS_XSADDDP, PPC_INS_XSADDQP, PPC_INS_XSADDQPO, PPC_INS_XSADDSP, PPC_INS_XSCMPEQDP, PPC_INS_XSCMPEXPDP, PPC_INS_XSCMPEXPQP, PPC_INS_XSCMPGEDP, PPC_INS_XSCMPGTDP, PPC_INS_XSCMPODP, PPC_INS_XSCMPOQP, PPC_INS_XSCMPUDP, PPC_INS_XSCMPUQP, PPC_INS_XSCPSGNDP, PPC_INS_XSCPSGNQP, PPC_INS_XSCVDPHP, PPC_INS_XSCVDPQP, PPC_INS_XSCVDPSP, PPC_INS_XSCVDPSPN, PPC_INS_XSCVDPSXDS, PPC_INS_XSCVDPSXWS, PPC_INS_XSCVDPUXDS, PPC_INS_XSCVDPUXWS, PPC_INS_XSCVHPDP, PPC_INS_XSCVQPDP, PPC_INS_XSCVQPDPO, PPC_INS_XSCVQPSDZ, PPC_INS_XSCVQPSWZ, PPC_INS_XSCVQPUDZ, PPC_INS_XSCVQPUWZ, PPC_INS_XSCVSDQP, PPC_INS_XSCVSPDP, PPC_INS_XSCVSPDPN, PPC_INS_XSCVSXDDP, PPC_INS_XSCVSXDSP, PPC_INS_XSCVUDQP, PPC_INS_XSCVUXDDP, PPC_INS_XSCVUXDSP, PPC_INS_XSDIVDP, PPC_INS_XSDIVQP, PPC_INS_XSDIVQPO, PPC_INS_XSDIVSP, PPC_INS_XSIEXPDP, PPC_INS_XSIEXPQP, PPC_INS_XSMADDADP, PPC_INS_XSMADDASP, PPC_INS_XSMADDMDP, PPC_INS_XSMADDMSP, PPC_INS_XSMADDQP, PPC_INS_XSMADDQPO, PPC_INS_XSMAXCDP, PPC_INS_XSMAXDP, PPC_INS_XSMAXJDP, PPC_INS_XSMINCDP, PPC_INS_XSMINDP, PPC_INS_XSMINJDP, PPC_INS_XSMSUBADP, PPC_INS_XSMSUBASP, PPC_INS_XSMSUBMDP, PPC_INS_XSMSUBMSP, PPC_INS_XSMSUBQP, PPC_INS_XSMSUBQPO, PPC_INS_XSMULDP, PPC_INS_XSMULQP, PPC_INS_XSMULQPO, PPC_INS_XSMULSP, PPC_INS_XSNABSDP, PPC_INS_XSNABSQP, PPC_INS_XSNEGDP, PPC_INS_XSNEGQP, PPC_INS_XSNMADDADP, PPC_INS_XSNMADDASP, PPC_INS_XSNMADDMDP, PPC_INS_XSNMADDMSP, PPC_INS_XSNMADDQP, PPC_INS_XSNMADDQPO, PPC_INS_XSNMSUBADP, PPC_INS_XSNMSUBASP, PPC_INS_XSNMSUBMDP, PPC_INS_XSNMSUBMSP, PPC_INS_XSNMSUBQP, PPC_INS_XSNMSUBQPO, PPC_INS_XSRDPI, PPC_INS_XSRDPIC, PPC_INS_XSRDPIM, PPC_INS_XSRDPIP, PPC_INS_XSRDPIZ, PPC_INS_XSREDP, PPC_INS_XSRESP, PPC_INS_XSRQPI, PPC_INS_XSRQPIX, PPC_INS_XSRQPXP, PPC_INS_XSRSP, PPC_INS_XSRSQRTEDP, PPC_INS_XSRSQRTESP, PPC_INS_XSSQRTDP, PPC_INS_XSSQRTQP, PPC_INS_XSSQRTQPO, PPC_INS_XSSQRTSP, PPC_INS_XSSUBDP, PPC_INS_XSSUBQP, PPC_INS_XSSUBQPO, PPC_INS_XSSUBSP, PPC_INS_XSTDIVDP, PPC_INS_XSTSQRTDP, PPC_INS_XSTSTDCDP, PPC_INS_XSTSTDCQP, PPC_INS_XSTSTDCSP, PPC_INS_XSXEXPDP, PPC_INS_XSXEXPQP, PPC_INS_XSXSIGDP, PPC_INS_XSXSIGQP, PPC_INS_XVABSDP, PPC_INS_XVABSSP, PPC_INS_XVADDDP, PPC_INS_XVADDSP, PPC_INS_XVCMPEQDP, PPC_INS_XVCMPEQSP, PPC_INS_XVCMPGEDP, PPC_INS_XVCMPGESP, PPC_INS_XVCMPGTDP, PPC_INS_XVCMPGTSP, PPC_INS_XVCPSGNDP, PPC_INS_XVCPSGNSP, PPC_INS_XVCVDPSP, PPC_INS_XVCVDPSXDS, PPC_INS_XVCVDPSXWS, PPC_INS_XVCVDPUXDS, PPC_INS_XVCVDPUXWS, PPC_INS_XVCVHPSP, PPC_INS_XVCVSPDP, PPC_INS_XVCVSPHP, PPC_INS_XVCVSPSXDS, PPC_INS_XVCVSPSXWS, PPC_INS_XVCVSPUXDS, PPC_INS_XVCVSPUXWS, PPC_INS_XVCVSXDDP, PPC_INS_XVCVSXDSP, PPC_INS_XVCVSXWDP, PPC_INS_XVCVSXWSP, PPC_INS_XVCVUXDDP, PPC_INS_XVCVUXDSP, PPC_INS_XVCVUXWDP, PPC_INS_XVCVUXWSP, PPC_INS_XVDIVDP, PPC_INS_XVDIVSP, PPC_INS_XVIEXPDP, PPC_INS_XVIEXPSP, PPC_INS_XVMADDADP, PPC_INS_XVMADDASP, PPC_INS_XVMADDMDP, PPC_INS_XVMADDMSP, PPC_INS_XVMAXDP, PPC_INS_XVMAXSP, PPC_INS_XVMINDP, PPC_INS_XVMINSP, PPC_INS_XVMOVDP, PPC_INS_XVMOVSP, PPC_INS_XVMSUBADP, PPC_INS_XVMSUBASP, PPC_INS_XVMSUBMDP, PPC_INS_XVMSUBMSP, PPC_INS_XVMULDP, PPC_INS_XVMULSP, PPC_INS_XVNABSDP, PPC_INS_XVNABSSP, PPC_INS_XVNEGDP, PPC_INS_XVNEGSP, PPC_INS_XVNMADDADP, PPC_INS_XVNMADDASP, PPC_INS_XVNMADDMDP, PPC_INS_XVNMADDMSP, PPC_INS_XVNMSUBADP, PPC_INS_XVNMSUBASP, PPC_INS_XVNMSUBMDP, PPC_INS_XVNMSUBMSP, PPC_INS_XVRDPI, PPC_INS_XVRDPIC, PPC_INS_XVRDPIM, PPC_INS_XVRDPIP, PPC_INS_XVRDPIZ, PPC_INS_XVREDP, PPC_INS_XVRESP, PPC_INS_XVRSPI, PPC_INS_XVRSPIC, PPC_INS_XVRSPIM, PPC_INS_XVRSPIP, PPC_INS_XVRSPIZ, PPC_INS_XVRSQRTEDP, PPC_INS_XVRSQRTESP, PPC_INS_XVSQRTDP, PPC_INS_XVSQRTSP, PPC_INS_XVSUBDP, PPC_INS_XVSUBSP, PPC_INS_XVTDIVDP, PPC_INS_XVTDIVSP, PPC_INS_XVTSQRTDP, PPC_INS_XVTSQRTSP, PPC_INS_XVTSTDCDP, PPC_INS_XVTSTDCSP, PPC_INS_XVXEXPDP, PPC_INS_XVXEXPSP, PPC_INS_XVXSIGDP, PPC_INS_XVXSIGSP, PPC_INS_XXBRD, PPC_INS_XXBRH, PPC_INS_XXBRQ, PPC_INS_XXBRW, PPC_INS_XXEXTRACTUW, PPC_INS_XXINSERTW, PPC_INS_XXLAND, PPC_INS_XXLANDC, PPC_INS_XXLEQV, PPC_INS_XXLNAND, PPC_INS_XXLNOR, PPC_INS_XXLOR, PPC_INS_XXLORC, PPC_INS_XXLXOR, PPC_INS_XXMRGHD, PPC_INS_XXMRGHW, PPC_INS_XXMRGLD, PPC_INS_XXMRGLW, PPC_INS_XXPERM, PPC_INS_XXPERMDI, PPC_INS_XXPERMR, PPC_INS_XXSEL, PPC_INS_XXSLDWI, PPC_INS_XXSPLTD, PPC_INS_XXSPLTIB, PPC_INS_XXSPLTW, PPC_INS_XXSWAPD, PPC_INS_ENDING, // <-- mark the end of the list of instructions } ppc_insn; /// Group of PPC instructions typedef enum ppc_insn_group { PPC_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) PPC_GRP_JUMP, ///< = CS_GRP_JUMP // Architecture-specific groups PPC_GRP_ALTIVEC = 128, PPC_GRP_MODE32, PPC_GRP_MODE64, PPC_GRP_BOOKE, PPC_GRP_NOTBOOKE, PPC_GRP_SPE, PPC_GRP_VSX, PPC_GRP_E500, PPC_GRP_PPC4XX, PPC_GRP_PPC6XX, PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR, PPC_GRP_QPX, PPC_GRP_ENDING, // <-- mark the end of the list of groups } ppc_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/riscv.h000064400000000000000000000305510072674642500207450ustar 00000000000000#ifndef CAPSTONE_RISCV_H #define CAPSTONE_RISCV_H /* Capstone Disassembly Engine */ /* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ #ifdef __cplusplus extern "C" { #endif #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) #include #endif #include "platform.h" // GCC MIPS toolchain has a default macro called "mips" which breaks // compilation //#undef riscv #ifdef _MSC_VER #pragma warning(disable:4201) #endif //> Operand type for instruction's operands typedef enum riscv_op_type { RISCV_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). RISCV_OP_REG, // = CS_OP_REG (Register operand). RISCV_OP_IMM, // = CS_OP_IMM (Immediate operand). RISCV_OP_MEM, // = CS_OP_MEM (Memory operand). } riscv_op_type; // Instruction's operand referring to memory // This is associated with RISCV_OP_MEM operand type above typedef struct riscv_op_mem { unsigned int base; // base register int64_t disp; // displacement/offset value } riscv_op_mem; // Instruction operand typedef struct cs_riscv_op { riscv_op_type type; // operand type union { unsigned int reg; // register value for REG operand int64_t imm; // immediate value for IMM operand riscv_op_mem mem; // base/disp value for MEM operand }; } cs_riscv_op; // Instruction structure typedef struct cs_riscv { // Does this instruction need effective address or not. bool need_effective_addr; // Number of operands of this instruction, // or 0 when instruction has no operand. uint8_t op_count; cs_riscv_op operands[8]; // operands for this instruction. } cs_riscv; //> RISCV registers typedef enum riscv_reg { RISCV_REG_INVALID = 0, //> General purpose registers RISCV_REG_X0, // "zero" RISCV_REG_ZERO = RISCV_REG_X0, // "zero" RISCV_REG_X1, // "ra" RISCV_REG_RA = RISCV_REG_X1, // "ra" RISCV_REG_X2, // "sp" RISCV_REG_SP = RISCV_REG_X2, // "sp" RISCV_REG_X3, // "gp" RISCV_REG_GP = RISCV_REG_X3, // "gp" RISCV_REG_X4, // "tp" RISCV_REG_TP = RISCV_REG_X4, // "tp" RISCV_REG_X5, // "t0" RISCV_REG_T0 = RISCV_REG_X5, // "t0" RISCV_REG_X6, // "t1" RISCV_REG_T1 = RISCV_REG_X6, // "t1" RISCV_REG_X7, // "t2" RISCV_REG_T2 = RISCV_REG_X7, // "t2" RISCV_REG_X8, // "s0/fp" RISCV_REG_S0 = RISCV_REG_X8, // "s0" RISCV_REG_FP = RISCV_REG_X8, // "fp" RISCV_REG_X9, // "s1" RISCV_REG_S1 = RISCV_REG_X9, // "s1" RISCV_REG_X10, // "a0" RISCV_REG_A0 = RISCV_REG_X10, // "a0" RISCV_REG_X11, // "a1" RISCV_REG_A1 = RISCV_REG_X11, // "a1" RISCV_REG_X12, // "a2" RISCV_REG_A2 = RISCV_REG_X12, // "a2" RISCV_REG_X13, // "a3" RISCV_REG_A3 = RISCV_REG_X13, // "a3" RISCV_REG_X14, // "a4" RISCV_REG_A4 = RISCV_REG_X14, // "a4" RISCV_REG_X15, // "a5" RISCV_REG_A5 = RISCV_REG_X15, // "a5" RISCV_REG_X16, // "a6" RISCV_REG_A6 = RISCV_REG_X16, // "a6" RISCV_REG_X17, // "a7" RISCV_REG_A7 = RISCV_REG_X17, // "a7" RISCV_REG_X18, // "s2" RISCV_REG_S2 = RISCV_REG_X18, // "s2" RISCV_REG_X19, // "s3" RISCV_REG_S3 = RISCV_REG_X19, // "s3" RISCV_REG_X20, // "s4" RISCV_REG_S4 = RISCV_REG_X20, // "s4" RISCV_REG_X21, // "s5" RISCV_REG_S5 = RISCV_REG_X21, // "s5" RISCV_REG_X22, // "s6" RISCV_REG_S6 = RISCV_REG_X22, // "s6" RISCV_REG_X23, // "s7" RISCV_REG_S7 = RISCV_REG_X23, // "s7" RISCV_REG_X24, // "s8" RISCV_REG_S8 = RISCV_REG_X24, // "s8" RISCV_REG_X25, // "s9" RISCV_REG_S9 = RISCV_REG_X25, // "s9" RISCV_REG_X26, // "s10" RISCV_REG_S10 = RISCV_REG_X26, // "s10" RISCV_REG_X27, // "s11" RISCV_REG_S11 = RISCV_REG_X27, // "s11" RISCV_REG_X28, // "t3" RISCV_REG_T3 = RISCV_REG_X28, // "t3" RISCV_REG_X29, // "t4" RISCV_REG_T4 = RISCV_REG_X29, // "t4" RISCV_REG_X30, // "t5" RISCV_REG_T5 = RISCV_REG_X30, // "t5" RISCV_REG_X31, // "t6" RISCV_REG_T6 = RISCV_REG_X31, // "t6" //> Floating-point registers RISCV_REG_F0_32, // "ft0" RISCV_REG_F0_64, // "ft0" RISCV_REG_F1_32, // "ft1" RISCV_REG_F1_64, // "ft1" RISCV_REG_F2_32, // "ft2" RISCV_REG_F2_64, // "ft2" RISCV_REG_F3_32, // "ft3" RISCV_REG_F3_64, // "ft3" RISCV_REG_F4_32, // "ft4" RISCV_REG_F4_64, // "ft4" RISCV_REG_F5_32, // "ft5" RISCV_REG_F5_64, // "ft5" RISCV_REG_F6_32, // "ft6" RISCV_REG_F6_64, // "ft6" RISCV_REG_F7_32, // "ft7" RISCV_REG_F7_64, // "ft7" RISCV_REG_F8_32, // "fs0" RISCV_REG_F8_64, // "fs0" RISCV_REG_F9_32, // "fs1" RISCV_REG_F9_64, // "fs1" RISCV_REG_F10_32, // "fa0" RISCV_REG_F10_64, // "fa0" RISCV_REG_F11_32, // "fa1" RISCV_REG_F11_64, // "fa1" RISCV_REG_F12_32, // "fa2" RISCV_REG_F12_64, // "fa2" RISCV_REG_F13_32, // "fa3" RISCV_REG_F13_64, // "fa3" RISCV_REG_F14_32, // "fa4" RISCV_REG_F14_64, // "fa4" RISCV_REG_F15_32, // "fa5" RISCV_REG_F15_64, // "fa5" RISCV_REG_F16_32, // "fa6" RISCV_REG_F16_64, // "fa6" RISCV_REG_F17_32, // "fa7" RISCV_REG_F17_64, // "fa7" RISCV_REG_F18_32, // "fs2" RISCV_REG_F18_64, // "fs2" RISCV_REG_F19_32, // "fs3" RISCV_REG_F19_64, // "fs3" RISCV_REG_F20_32, // "fs4" RISCV_REG_F20_64, // "fs4" RISCV_REG_F21_32, // "fs5" RISCV_REG_F21_64, // "fs5" RISCV_REG_F22_32, // "fs6" RISCV_REG_F22_64, // "fs6" RISCV_REG_F23_32, // "fs7" RISCV_REG_F23_64, // "fs7" RISCV_REG_F24_32, // "fs8" RISCV_REG_F24_64, // "fs8" RISCV_REG_F25_32, // "fs9" RISCV_REG_F25_64, // "fs9" RISCV_REG_F26_32, // "fs10" RISCV_REG_F26_64, // "fs10" RISCV_REG_F27_32, // "fs11" RISCV_REG_F27_64, // "fs11" RISCV_REG_F28_32, // "ft8" RISCV_REG_F28_64, // "ft8" RISCV_REG_F29_32, // "ft9" RISCV_REG_F29_64, // "ft9" RISCV_REG_F30_32, // "ft10" RISCV_REG_F30_64, // "ft10" RISCV_REG_F31_32, // "ft11" RISCV_REG_F31_64, // "ft11" RISCV_REG_ENDING, // <-- mark the end of the list or registers } riscv_reg; //> RISCV instruction typedef enum riscv_insn { RISCV_INS_INVALID = 0, RISCV_INS_ADD, RISCV_INS_ADDI, RISCV_INS_ADDIW, RISCV_INS_ADDW, RISCV_INS_AMOADD_D, RISCV_INS_AMOADD_D_AQ, RISCV_INS_AMOADD_D_AQ_RL, RISCV_INS_AMOADD_D_RL, RISCV_INS_AMOADD_W, RISCV_INS_AMOADD_W_AQ, RISCV_INS_AMOADD_W_AQ_RL, RISCV_INS_AMOADD_W_RL, RISCV_INS_AMOAND_D, RISCV_INS_AMOAND_D_AQ, RISCV_INS_AMOAND_D_AQ_RL, RISCV_INS_AMOAND_D_RL, RISCV_INS_AMOAND_W, RISCV_INS_AMOAND_W_AQ, RISCV_INS_AMOAND_W_AQ_RL, RISCV_INS_AMOAND_W_RL, RISCV_INS_AMOMAXU_D, RISCV_INS_AMOMAXU_D_AQ, RISCV_INS_AMOMAXU_D_AQ_RL, RISCV_INS_AMOMAXU_D_RL, RISCV_INS_AMOMAXU_W, RISCV_INS_AMOMAXU_W_AQ, RISCV_INS_AMOMAXU_W_AQ_RL, RISCV_INS_AMOMAXU_W_RL, RISCV_INS_AMOMAX_D, RISCV_INS_AMOMAX_D_AQ, RISCV_INS_AMOMAX_D_AQ_RL, RISCV_INS_AMOMAX_D_RL, RISCV_INS_AMOMAX_W, RISCV_INS_AMOMAX_W_AQ, RISCV_INS_AMOMAX_W_AQ_RL, RISCV_INS_AMOMAX_W_RL, RISCV_INS_AMOMINU_D, RISCV_INS_AMOMINU_D_AQ, RISCV_INS_AMOMINU_D_AQ_RL, RISCV_INS_AMOMINU_D_RL, RISCV_INS_AMOMINU_W, RISCV_INS_AMOMINU_W_AQ, RISCV_INS_AMOMINU_W_AQ_RL, RISCV_INS_AMOMINU_W_RL, RISCV_INS_AMOMIN_D, RISCV_INS_AMOMIN_D_AQ, RISCV_INS_AMOMIN_D_AQ_RL, RISCV_INS_AMOMIN_D_RL, RISCV_INS_AMOMIN_W, RISCV_INS_AMOMIN_W_AQ, RISCV_INS_AMOMIN_W_AQ_RL, RISCV_INS_AMOMIN_W_RL, RISCV_INS_AMOOR_D, RISCV_INS_AMOOR_D_AQ, RISCV_INS_AMOOR_D_AQ_RL, RISCV_INS_AMOOR_D_RL, RISCV_INS_AMOOR_W, RISCV_INS_AMOOR_W_AQ, RISCV_INS_AMOOR_W_AQ_RL, RISCV_INS_AMOOR_W_RL, RISCV_INS_AMOSWAP_D, RISCV_INS_AMOSWAP_D_AQ, RISCV_INS_AMOSWAP_D_AQ_RL, RISCV_INS_AMOSWAP_D_RL, RISCV_INS_AMOSWAP_W, RISCV_INS_AMOSWAP_W_AQ, RISCV_INS_AMOSWAP_W_AQ_RL, RISCV_INS_AMOSWAP_W_RL, RISCV_INS_AMOXOR_D, RISCV_INS_AMOXOR_D_AQ, RISCV_INS_AMOXOR_D_AQ_RL, RISCV_INS_AMOXOR_D_RL, RISCV_INS_AMOXOR_W, RISCV_INS_AMOXOR_W_AQ, RISCV_INS_AMOXOR_W_AQ_RL, RISCV_INS_AMOXOR_W_RL, RISCV_INS_AND, RISCV_INS_ANDI, RISCV_INS_AUIPC, RISCV_INS_BEQ, RISCV_INS_BGE, RISCV_INS_BGEU, RISCV_INS_BLT, RISCV_INS_BLTU, RISCV_INS_BNE, RISCV_INS_CSRRC, RISCV_INS_CSRRCI, RISCV_INS_CSRRS, RISCV_INS_CSRRSI, RISCV_INS_CSRRW, RISCV_INS_CSRRWI, RISCV_INS_C_ADD, RISCV_INS_C_ADDI, RISCV_INS_C_ADDI16SP, RISCV_INS_C_ADDI4SPN, RISCV_INS_C_ADDIW, RISCV_INS_C_ADDW, RISCV_INS_C_AND, RISCV_INS_C_ANDI, RISCV_INS_C_BEQZ, RISCV_INS_C_BNEZ, RISCV_INS_C_EBREAK, RISCV_INS_C_FLD, RISCV_INS_C_FLDSP, RISCV_INS_C_FLW, RISCV_INS_C_FLWSP, RISCV_INS_C_FSD, RISCV_INS_C_FSDSP, RISCV_INS_C_FSW, RISCV_INS_C_FSWSP, RISCV_INS_C_J, RISCV_INS_C_JAL, RISCV_INS_C_JALR, RISCV_INS_C_JR, RISCV_INS_C_LD, RISCV_INS_C_LDSP, RISCV_INS_C_LI, RISCV_INS_C_LUI, RISCV_INS_C_LW, RISCV_INS_C_LWSP, RISCV_INS_C_MV, RISCV_INS_C_NOP, RISCV_INS_C_OR, RISCV_INS_C_SD, RISCV_INS_C_SDSP, RISCV_INS_C_SLLI, RISCV_INS_C_SRAI, RISCV_INS_C_SRLI, RISCV_INS_C_SUB, RISCV_INS_C_SUBW, RISCV_INS_C_SW, RISCV_INS_C_SWSP, RISCV_INS_C_UNIMP, RISCV_INS_C_XOR, RISCV_INS_DIV, RISCV_INS_DIVU, RISCV_INS_DIVUW, RISCV_INS_DIVW, RISCV_INS_EBREAK, RISCV_INS_ECALL, RISCV_INS_FADD_D, RISCV_INS_FADD_S, RISCV_INS_FCLASS_D, RISCV_INS_FCLASS_S, RISCV_INS_FCVT_D_L, RISCV_INS_FCVT_D_LU, RISCV_INS_FCVT_D_S, RISCV_INS_FCVT_D_W, RISCV_INS_FCVT_D_WU, RISCV_INS_FCVT_LU_D, RISCV_INS_FCVT_LU_S, RISCV_INS_FCVT_L_D, RISCV_INS_FCVT_L_S, RISCV_INS_FCVT_S_D, RISCV_INS_FCVT_S_L, RISCV_INS_FCVT_S_LU, RISCV_INS_FCVT_S_W, RISCV_INS_FCVT_S_WU, RISCV_INS_FCVT_WU_D, RISCV_INS_FCVT_WU_S, RISCV_INS_FCVT_W_D, RISCV_INS_FCVT_W_S, RISCV_INS_FDIV_D, RISCV_INS_FDIV_S, RISCV_INS_FENCE, RISCV_INS_FENCE_I, RISCV_INS_FENCE_TSO, RISCV_INS_FEQ_D, RISCV_INS_FEQ_S, RISCV_INS_FLD, RISCV_INS_FLE_D, RISCV_INS_FLE_S, RISCV_INS_FLT_D, RISCV_INS_FLT_S, RISCV_INS_FLW, RISCV_INS_FMADD_D, RISCV_INS_FMADD_S, RISCV_INS_FMAX_D, RISCV_INS_FMAX_S, RISCV_INS_FMIN_D, RISCV_INS_FMIN_S, RISCV_INS_FMSUB_D, RISCV_INS_FMSUB_S, RISCV_INS_FMUL_D, RISCV_INS_FMUL_S, RISCV_INS_FMV_D_X, RISCV_INS_FMV_W_X, RISCV_INS_FMV_X_D, RISCV_INS_FMV_X_W, RISCV_INS_FNMADD_D, RISCV_INS_FNMADD_S, RISCV_INS_FNMSUB_D, RISCV_INS_FNMSUB_S, RISCV_INS_FSD, RISCV_INS_FSGNJN_D, RISCV_INS_FSGNJN_S, RISCV_INS_FSGNJX_D, RISCV_INS_FSGNJX_S, RISCV_INS_FSGNJ_D, RISCV_INS_FSGNJ_S, RISCV_INS_FSQRT_D, RISCV_INS_FSQRT_S, RISCV_INS_FSUB_D, RISCV_INS_FSUB_S, RISCV_INS_FSW, RISCV_INS_JAL, RISCV_INS_JALR, RISCV_INS_LB, RISCV_INS_LBU, RISCV_INS_LD, RISCV_INS_LH, RISCV_INS_LHU, RISCV_INS_LR_D, RISCV_INS_LR_D_AQ, RISCV_INS_LR_D_AQ_RL, RISCV_INS_LR_D_RL, RISCV_INS_LR_W, RISCV_INS_LR_W_AQ, RISCV_INS_LR_W_AQ_RL, RISCV_INS_LR_W_RL, RISCV_INS_LUI, RISCV_INS_LW, RISCV_INS_LWU, RISCV_INS_MRET, RISCV_INS_MUL, RISCV_INS_MULH, RISCV_INS_MULHSU, RISCV_INS_MULHU, RISCV_INS_MULW, RISCV_INS_OR, RISCV_INS_ORI, RISCV_INS_REM, RISCV_INS_REMU, RISCV_INS_REMUW, RISCV_INS_REMW, RISCV_INS_SB, RISCV_INS_SC_D, RISCV_INS_SC_D_AQ, RISCV_INS_SC_D_AQ_RL, RISCV_INS_SC_D_RL, RISCV_INS_SC_W, RISCV_INS_SC_W_AQ, RISCV_INS_SC_W_AQ_RL, RISCV_INS_SC_W_RL, RISCV_INS_SD, RISCV_INS_SFENCE_VMA, RISCV_INS_SH, RISCV_INS_SLL, RISCV_INS_SLLI, RISCV_INS_SLLIW, RISCV_INS_SLLW, RISCV_INS_SLT, RISCV_INS_SLTI, RISCV_INS_SLTIU, RISCV_INS_SLTU, RISCV_INS_SRA, RISCV_INS_SRAI, RISCV_INS_SRAIW, RISCV_INS_SRAW, RISCV_INS_SRET, RISCV_INS_SRL, RISCV_INS_SRLI, RISCV_INS_SRLIW, RISCV_INS_SRLW, RISCV_INS_SUB, RISCV_INS_SUBW, RISCV_INS_SW, RISCV_INS_UNIMP, RISCV_INS_URET, RISCV_INS_WFI, RISCV_INS_XOR, RISCV_INS_XORI, RISCV_INS_ENDING, } riscv_insn; //> Group of RISCV instructions typedef enum riscv_insn_group { RISCV_GRP_INVALID = 0, // = CS_GRP_INVALID RISCV_GRP_JUMP, RISCV_GRP_ISRV32 = 128, RISCV_GRP_ISRV64, RISCV_GRP_HASSTDEXTA, RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, RISCV_GRP_HASSTDEXTF, RISCV_GRP_HASSTDEXTM, /* RISCV_GRP_ISRVA, RISCV_GRP_ISRVC, RISCV_GRP_ISRVD, RISCV_GRP_ISRVCD, RISCV_GRP_ISRVF, RISCV_GRP_ISRV32C, RISCV_GRP_ISRV32CF, RISCV_GRP_ISRVM, RISCV_GRP_ISRV64A, RISCV_GRP_ISRV64C, RISCV_GRP_ISRV64D, RISCV_GRP_ISRV64F, RISCV_GRP_ISRV64M, */ RISCV_GRP_ENDING, } riscv_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/sparc.h000064400000000000000000000260410072674642500207260ustar 00000000000000#ifndef CAPSTONE_SPARC_H #define CAPSTONE_SPARC_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2014-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" // GCC SPARC toolchain has a default macro called "sparc" which breaks // compilation #undef sparc #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// Enums corresponding to Sparc condition codes, both icc's and fcc's. typedef enum sparc_cc { SPARC_CC_INVALID = 0, ///< invalid CC (default) // Integer condition codes SPARC_CC_ICC_A = 8+256, ///< Always SPARC_CC_ICC_N = 0+256, ///< Never SPARC_CC_ICC_NE = 9+256, ///< Not Equal SPARC_CC_ICC_E = 1+256, ///< Equal SPARC_CC_ICC_G = 10+256, ///< Greater SPARC_CC_ICC_LE = 2+256, ///< Less or Equal SPARC_CC_ICC_GE = 11+256, ///< Greater or Equal SPARC_CC_ICC_L = 3+256, ///< Less SPARC_CC_ICC_GU = 12+256, ///< Greater Unsigned SPARC_CC_ICC_LEU = 4+256, ///< Less or Equal Unsigned SPARC_CC_ICC_CC = 13+256, ///< Carry Clear/Great or Equal Unsigned SPARC_CC_ICC_CS = 5+256, ///< Carry Set/Less Unsigned SPARC_CC_ICC_POS = 14+256, ///< Positive SPARC_CC_ICC_NEG = 6+256, ///< Negative SPARC_CC_ICC_VC = 15+256, ///< Overflow Clear SPARC_CC_ICC_VS = 7+256, ///< Overflow Set // Floating condition codes SPARC_CC_FCC_A = 8+16+256, ///< Always SPARC_CC_FCC_N = 0+16+256, ///< Never SPARC_CC_FCC_U = 7+16+256, ///< Unordered SPARC_CC_FCC_G = 6+16+256, ///< Greater SPARC_CC_FCC_UG = 5+16+256, ///< Unordered or Greater SPARC_CC_FCC_L = 4+16+256, ///< Less SPARC_CC_FCC_UL = 3+16+256, ///< Unordered or Less SPARC_CC_FCC_LG = 2+16+256, ///< Less or Greater SPARC_CC_FCC_NE = 1+16+256, ///< Not Equal SPARC_CC_FCC_E = 9+16+256, ///< Equal SPARC_CC_FCC_UE = 10+16+256, ///< Unordered or Equal SPARC_CC_FCC_GE = 11+16+256, ///< Greater or Equal SPARC_CC_FCC_UGE = 12+16+256, ///< Unordered or Greater or Equal SPARC_CC_FCC_LE = 13+16+256, ///< Less or Equal SPARC_CC_FCC_ULE = 14+16+256, ///< Unordered or Less or Equal SPARC_CC_FCC_O = 15+16+256, ///< Ordered } sparc_cc; /// Branch hint typedef enum sparc_hint { SPARC_HINT_INVALID = 0, ///< no hint SPARC_HINT_A = 1 << 0, ///< annul delay slot instruction SPARC_HINT_PT = 1 << 1, ///< branch taken SPARC_HINT_PN = 1 << 2, ///< branch NOT taken } sparc_hint; /// Operand type for instruction's operands typedef enum sparc_op_type { SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). SPARC_OP_REG, ///< = CS_OP_REG (Register operand). SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand). SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand). } sparc_op_type; /// SPARC registers typedef enum sparc_reg { SPARC_REG_INVALID = 0, SPARC_REG_F0, SPARC_REG_F1, SPARC_REG_F2, SPARC_REG_F3, SPARC_REG_F4, SPARC_REG_F5, SPARC_REG_F6, SPARC_REG_F7, SPARC_REG_F8, SPARC_REG_F9, SPARC_REG_F10, SPARC_REG_F11, SPARC_REG_F12, SPARC_REG_F13, SPARC_REG_F14, SPARC_REG_F15, SPARC_REG_F16, SPARC_REG_F17, SPARC_REG_F18, SPARC_REG_F19, SPARC_REG_F20, SPARC_REG_F21, SPARC_REG_F22, SPARC_REG_F23, SPARC_REG_F24, SPARC_REG_F25, SPARC_REG_F26, SPARC_REG_F27, SPARC_REG_F28, SPARC_REG_F29, SPARC_REG_F30, SPARC_REG_F31, SPARC_REG_F32, SPARC_REG_F34, SPARC_REG_F36, SPARC_REG_F38, SPARC_REG_F40, SPARC_REG_F42, SPARC_REG_F44, SPARC_REG_F46, SPARC_REG_F48, SPARC_REG_F50, SPARC_REG_F52, SPARC_REG_F54, SPARC_REG_F56, SPARC_REG_F58, SPARC_REG_F60, SPARC_REG_F62, SPARC_REG_FCC0, // Floating condition codes SPARC_REG_FCC1, SPARC_REG_FCC2, SPARC_REG_FCC3, SPARC_REG_FP, SPARC_REG_G0, SPARC_REG_G1, SPARC_REG_G2, SPARC_REG_G3, SPARC_REG_G4, SPARC_REG_G5, SPARC_REG_G6, SPARC_REG_G7, SPARC_REG_I0, SPARC_REG_I1, SPARC_REG_I2, SPARC_REG_I3, SPARC_REG_I4, SPARC_REG_I5, SPARC_REG_I7, SPARC_REG_ICC, // Integer condition codes SPARC_REG_L0, SPARC_REG_L1, SPARC_REG_L2, SPARC_REG_L3, SPARC_REG_L4, SPARC_REG_L5, SPARC_REG_L6, SPARC_REG_L7, SPARC_REG_O0, SPARC_REG_O1, SPARC_REG_O2, SPARC_REG_O3, SPARC_REG_O4, SPARC_REG_O5, SPARC_REG_O7, SPARC_REG_SP, SPARC_REG_Y, // special register SPARC_REG_XCC, SPARC_REG_ENDING, // <-- mark the end of the list of registers // extras SPARC_REG_O6 = SPARC_REG_SP, SPARC_REG_I6 = SPARC_REG_FP, } sparc_reg; /// Instruction's operand referring to memory /// This is associated with SPARC_OP_MEM operand type above typedef struct sparc_op_mem { uint8_t base; ///< base register, can be safely interpreted as ///< a value of type `sparc_reg`, but it is only ///< one byte wide uint8_t index; ///< index register, same conditions apply here int32_t disp; ///< displacement/offset value } sparc_op_mem; /// Instruction operand typedef struct cs_sparc_op { sparc_op_type type; ///< operand type union { sparc_reg reg; ///< register value for REG operand int64_t imm; ///< immediate value for IMM operand sparc_op_mem mem; ///< base/disp value for MEM operand }; } cs_sparc_op; /// Instruction structure typedef struct cs_sparc { sparc_cc cc; ///< code condition for this insn sparc_hint hint; ///< branch hint: encoding as bitwise OR of sparc_hint. /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_sparc_op operands[4]; ///< operands for this instruction. } cs_sparc; /// SPARC instruction typedef enum sparc_insn { SPARC_INS_INVALID = 0, SPARC_INS_ADDCC, SPARC_INS_ADDX, SPARC_INS_ADDXCC, SPARC_INS_ADDXC, SPARC_INS_ADDXCCC, SPARC_INS_ADD, SPARC_INS_ALIGNADDR, SPARC_INS_ALIGNADDRL, SPARC_INS_ANDCC, SPARC_INS_ANDNCC, SPARC_INS_ANDN, SPARC_INS_AND, SPARC_INS_ARRAY16, SPARC_INS_ARRAY32, SPARC_INS_ARRAY8, SPARC_INS_B, SPARC_INS_JMP, SPARC_INS_BMASK, SPARC_INS_FB, SPARC_INS_BRGEZ, SPARC_INS_BRGZ, SPARC_INS_BRLEZ, SPARC_INS_BRLZ, SPARC_INS_BRNZ, SPARC_INS_BRZ, SPARC_INS_BSHUFFLE, SPARC_INS_CALL, SPARC_INS_CASX, SPARC_INS_CAS, SPARC_INS_CMASK16, SPARC_INS_CMASK32, SPARC_INS_CMASK8, SPARC_INS_CMP, SPARC_INS_EDGE16, SPARC_INS_EDGE16L, SPARC_INS_EDGE16LN, SPARC_INS_EDGE16N, SPARC_INS_EDGE32, SPARC_INS_EDGE32L, SPARC_INS_EDGE32LN, SPARC_INS_EDGE32N, SPARC_INS_EDGE8, SPARC_INS_EDGE8L, SPARC_INS_EDGE8LN, SPARC_INS_EDGE8N, SPARC_INS_FABSD, SPARC_INS_FABSQ, SPARC_INS_FABSS, SPARC_INS_FADDD, SPARC_INS_FADDQ, SPARC_INS_FADDS, SPARC_INS_FALIGNDATA, SPARC_INS_FAND, SPARC_INS_FANDNOT1, SPARC_INS_FANDNOT1S, SPARC_INS_FANDNOT2, SPARC_INS_FANDNOT2S, SPARC_INS_FANDS, SPARC_INS_FCHKSM16, SPARC_INS_FCMPD, SPARC_INS_FCMPEQ16, SPARC_INS_FCMPEQ32, SPARC_INS_FCMPGT16, SPARC_INS_FCMPGT32, SPARC_INS_FCMPLE16, SPARC_INS_FCMPLE32, SPARC_INS_FCMPNE16, SPARC_INS_FCMPNE32, SPARC_INS_FCMPQ, SPARC_INS_FCMPS, SPARC_INS_FDIVD, SPARC_INS_FDIVQ, SPARC_INS_FDIVS, SPARC_INS_FDMULQ, SPARC_INS_FDTOI, SPARC_INS_FDTOQ, SPARC_INS_FDTOS, SPARC_INS_FDTOX, SPARC_INS_FEXPAND, SPARC_INS_FHADDD, SPARC_INS_FHADDS, SPARC_INS_FHSUBD, SPARC_INS_FHSUBS, SPARC_INS_FITOD, SPARC_INS_FITOQ, SPARC_INS_FITOS, SPARC_INS_FLCMPD, SPARC_INS_FLCMPS, SPARC_INS_FLUSHW, SPARC_INS_FMEAN16, SPARC_INS_FMOVD, SPARC_INS_FMOVQ, SPARC_INS_FMOVRDGEZ, SPARC_INS_FMOVRQGEZ, SPARC_INS_FMOVRSGEZ, SPARC_INS_FMOVRDGZ, SPARC_INS_FMOVRQGZ, SPARC_INS_FMOVRSGZ, SPARC_INS_FMOVRDLEZ, SPARC_INS_FMOVRQLEZ, SPARC_INS_FMOVRSLEZ, SPARC_INS_FMOVRDLZ, SPARC_INS_FMOVRQLZ, SPARC_INS_FMOVRSLZ, SPARC_INS_FMOVRDNZ, SPARC_INS_FMOVRQNZ, SPARC_INS_FMOVRSNZ, SPARC_INS_FMOVRDZ, SPARC_INS_FMOVRQZ, SPARC_INS_FMOVRSZ, SPARC_INS_FMOVS, SPARC_INS_FMUL8SUX16, SPARC_INS_FMUL8ULX16, SPARC_INS_FMUL8X16, SPARC_INS_FMUL8X16AL, SPARC_INS_FMUL8X16AU, SPARC_INS_FMULD, SPARC_INS_FMULD8SUX16, SPARC_INS_FMULD8ULX16, SPARC_INS_FMULQ, SPARC_INS_FMULS, SPARC_INS_FNADDD, SPARC_INS_FNADDS, SPARC_INS_FNAND, SPARC_INS_FNANDS, SPARC_INS_FNEGD, SPARC_INS_FNEGQ, SPARC_INS_FNEGS, SPARC_INS_FNHADDD, SPARC_INS_FNHADDS, SPARC_INS_FNOR, SPARC_INS_FNORS, SPARC_INS_FNOT1, SPARC_INS_FNOT1S, SPARC_INS_FNOT2, SPARC_INS_FNOT2S, SPARC_INS_FONE, SPARC_INS_FONES, SPARC_INS_FOR, SPARC_INS_FORNOT1, SPARC_INS_FORNOT1S, SPARC_INS_FORNOT2, SPARC_INS_FORNOT2S, SPARC_INS_FORS, SPARC_INS_FPACK16, SPARC_INS_FPACK32, SPARC_INS_FPACKFIX, SPARC_INS_FPADD16, SPARC_INS_FPADD16S, SPARC_INS_FPADD32, SPARC_INS_FPADD32S, SPARC_INS_FPADD64, SPARC_INS_FPMERGE, SPARC_INS_FPSUB16, SPARC_INS_FPSUB16S, SPARC_INS_FPSUB32, SPARC_INS_FPSUB32S, SPARC_INS_FQTOD, SPARC_INS_FQTOI, SPARC_INS_FQTOS, SPARC_INS_FQTOX, SPARC_INS_FSLAS16, SPARC_INS_FSLAS32, SPARC_INS_FSLL16, SPARC_INS_FSLL32, SPARC_INS_FSMULD, SPARC_INS_FSQRTD, SPARC_INS_FSQRTQ, SPARC_INS_FSQRTS, SPARC_INS_FSRA16, SPARC_INS_FSRA32, SPARC_INS_FSRC1, SPARC_INS_FSRC1S, SPARC_INS_FSRC2, SPARC_INS_FSRC2S, SPARC_INS_FSRL16, SPARC_INS_FSRL32, SPARC_INS_FSTOD, SPARC_INS_FSTOI, SPARC_INS_FSTOQ, SPARC_INS_FSTOX, SPARC_INS_FSUBD, SPARC_INS_FSUBQ, SPARC_INS_FSUBS, SPARC_INS_FXNOR, SPARC_INS_FXNORS, SPARC_INS_FXOR, SPARC_INS_FXORS, SPARC_INS_FXTOD, SPARC_INS_FXTOQ, SPARC_INS_FXTOS, SPARC_INS_FZERO, SPARC_INS_FZEROS, SPARC_INS_JMPL, SPARC_INS_LDD, SPARC_INS_LD, SPARC_INS_LDQ, SPARC_INS_LDSB, SPARC_INS_LDSH, SPARC_INS_LDSW, SPARC_INS_LDUB, SPARC_INS_LDUH, SPARC_INS_LDX, SPARC_INS_LZCNT, SPARC_INS_MEMBAR, SPARC_INS_MOVDTOX, SPARC_INS_MOV, SPARC_INS_MOVRGEZ, SPARC_INS_MOVRGZ, SPARC_INS_MOVRLEZ, SPARC_INS_MOVRLZ, SPARC_INS_MOVRNZ, SPARC_INS_MOVRZ, SPARC_INS_MOVSTOSW, SPARC_INS_MOVSTOUW, SPARC_INS_MULX, SPARC_INS_NOP, SPARC_INS_ORCC, SPARC_INS_ORNCC, SPARC_INS_ORN, SPARC_INS_OR, SPARC_INS_PDIST, SPARC_INS_PDISTN, SPARC_INS_POPC, SPARC_INS_RD, SPARC_INS_RESTORE, SPARC_INS_RETT, SPARC_INS_SAVE, SPARC_INS_SDIVCC, SPARC_INS_SDIVX, SPARC_INS_SDIV, SPARC_INS_SETHI, SPARC_INS_SHUTDOWN, SPARC_INS_SIAM, SPARC_INS_SLLX, SPARC_INS_SLL, SPARC_INS_SMULCC, SPARC_INS_SMUL, SPARC_INS_SRAX, SPARC_INS_SRA, SPARC_INS_SRLX, SPARC_INS_SRL, SPARC_INS_STBAR, SPARC_INS_STB, SPARC_INS_STD, SPARC_INS_ST, SPARC_INS_STH, SPARC_INS_STQ, SPARC_INS_STX, SPARC_INS_SUBCC, SPARC_INS_SUBX, SPARC_INS_SUBXCC, SPARC_INS_SUB, SPARC_INS_SWAP, SPARC_INS_TADDCCTV, SPARC_INS_TADDCC, SPARC_INS_T, SPARC_INS_TSUBCCTV, SPARC_INS_TSUBCC, SPARC_INS_UDIVCC, SPARC_INS_UDIVX, SPARC_INS_UDIV, SPARC_INS_UMULCC, SPARC_INS_UMULXHI, SPARC_INS_UMUL, SPARC_INS_UNIMP, SPARC_INS_FCMPED, SPARC_INS_FCMPEQ, SPARC_INS_FCMPES, SPARC_INS_WR, SPARC_INS_XMULX, SPARC_INS_XMULXHI, SPARC_INS_XNORCC, SPARC_INS_XNOR, SPARC_INS_XORCC, SPARC_INS_XOR, // alias instructions SPARC_INS_RET, SPARC_INS_RETL, SPARC_INS_ENDING, // <-- mark the end of the list of instructions } sparc_insn; /// Group of SPARC instructions typedef enum sparc_insn_group { SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) SPARC_GRP_JUMP, ///< = CS_GRP_JUMP // Architecture-specific groups SPARC_GRP_HARDQUAD = 128, SPARC_GRP_V9, SPARC_GRP_VIS, SPARC_GRP_VIS2, SPARC_GRP_VIS3, SPARC_GRP_32BIT, SPARC_GRP_64BIT, SPARC_GRP_ENDING, // <-- mark the end of the list of groups } sparc_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/systemz.h000064400000000000000000001271270072674642500213430ustar 00000000000000#ifndef CAPSTONE_SYSTEMZ_H #define CAPSTONE_SYSTEMZ_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2014-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// Enums corresponding to SystemZ condition codes typedef enum sysz_cc { SYSZ_CC_INVALID = 0, ///< invalid CC (default) SYSZ_CC_O, SYSZ_CC_H, SYSZ_CC_NLE, SYSZ_CC_L, SYSZ_CC_NHE, SYSZ_CC_LH, SYSZ_CC_NE, SYSZ_CC_E, SYSZ_CC_NLH, SYSZ_CC_HE, SYSZ_CC_NL, SYSZ_CC_LE, SYSZ_CC_NH, SYSZ_CC_NO, } sysz_cc; /// Operand type for instruction's operands typedef enum sysz_op_type { SYSZ_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). SYSZ_OP_REG, ///< = CS_OP_REG (Register operand). SYSZ_OP_IMM, ///< = CS_OP_IMM (Immediate operand). SYSZ_OP_MEM, ///< = CS_OP_MEM (Memory operand). SYSZ_OP_ACREG = 64, ///< Access register operand. } sysz_op_type; /// SystemZ registers typedef enum sysz_reg { SYSZ_REG_INVALID = 0, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, SYSZ_REG_6, SYSZ_REG_7, SYSZ_REG_8, SYSZ_REG_9, SYSZ_REG_10, SYSZ_REG_11, SYSZ_REG_12, SYSZ_REG_13, SYSZ_REG_14, SYSZ_REG_15, SYSZ_REG_CC, SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F2, SYSZ_REG_F3, SYSZ_REG_F4, SYSZ_REG_F5, SYSZ_REG_F6, SYSZ_REG_F7, SYSZ_REG_F8, SYSZ_REG_F9, SYSZ_REG_F10, SYSZ_REG_F11, SYSZ_REG_F12, SYSZ_REG_F13, SYSZ_REG_F14, SYSZ_REG_F15, SYSZ_REG_R0L, SYSZ_REG_A0, SYSZ_REG_A1, SYSZ_REG_A2, SYSZ_REG_A3, SYSZ_REG_A4, SYSZ_REG_A5, SYSZ_REG_A6, SYSZ_REG_A7, SYSZ_REG_A8, SYSZ_REG_A9, SYSZ_REG_A10, SYSZ_REG_A11, SYSZ_REG_A12, SYSZ_REG_A13, SYSZ_REG_A14, SYSZ_REG_A15, SYSZ_REG_C0, SYSZ_REG_C1, SYSZ_REG_C2, SYSZ_REG_C3, SYSZ_REG_C4, SYSZ_REG_C5, SYSZ_REG_C6, SYSZ_REG_C7, SYSZ_REG_C8, SYSZ_REG_C9, SYSZ_REG_C10, SYSZ_REG_C11, SYSZ_REG_C12, SYSZ_REG_C13, SYSZ_REG_C14, SYSZ_REG_C15, SYSZ_REG_V0, SYSZ_REG_V1, SYSZ_REG_V2, SYSZ_REG_V3, SYSZ_REG_V4, SYSZ_REG_V5, SYSZ_REG_V6, SYSZ_REG_V7, SYSZ_REG_V8, SYSZ_REG_V9, SYSZ_REG_V10, SYSZ_REG_V11, SYSZ_REG_V12, SYSZ_REG_V13, SYSZ_REG_V14, SYSZ_REG_V15, SYSZ_REG_V16, SYSZ_REG_V17, SYSZ_REG_V18, SYSZ_REG_V19, SYSZ_REG_V20, SYSZ_REG_V21, SYSZ_REG_V22, SYSZ_REG_V23, SYSZ_REG_V24, SYSZ_REG_V25, SYSZ_REG_V26, SYSZ_REG_V27, SYSZ_REG_V28, SYSZ_REG_V29, SYSZ_REG_V30, SYSZ_REG_V31, SYSZ_REG_F16, SYSZ_REG_F17, SYSZ_REG_F18, SYSZ_REG_F19, SYSZ_REG_F20, SYSZ_REG_F21, SYSZ_REG_F22, SYSZ_REG_F23, SYSZ_REG_F24, SYSZ_REG_F25, SYSZ_REG_F26, SYSZ_REG_F27, SYSZ_REG_F28, SYSZ_REG_F29, SYSZ_REG_F30, SYSZ_REG_F31, SYSZ_REG_F0Q, SYSZ_REG_F4Q, SYSZ_REG_ENDING, } sysz_reg; /// Instruction's operand referring to memory /// This is associated with SYSZ_OP_MEM operand type above typedef struct sysz_op_mem { uint8_t base; ///< base register, can be safely interpreted as ///< a value of type `sysz_reg`, but it is only ///< one byte wide uint8_t index; ///< index register, same conditions apply here uint64_t length; ///< BDLAddr operand int64_t disp; ///< displacement/offset value } sysz_op_mem; /// Instruction operand typedef struct cs_sysz_op { sysz_op_type type; ///< operand type union { sysz_reg reg; ///< register value for REG operand int64_t imm; ///< immediate value for IMM operand sysz_op_mem mem; ///< base/disp value for MEM operand }; } cs_sysz_op; // Instruction structure typedef struct cs_sysz { sysz_cc cc; ///< Code condition /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_sysz_op operands[6]; ///< operands for this instruction. } cs_sysz; /// SystemZ instruction typedef enum sysz_insn { SYSZ_INS_INVALID = 0, SYSZ_INS_A, SYSZ_INS_ADB, SYSZ_INS_ADBR, SYSZ_INS_AEB, SYSZ_INS_AEBR, SYSZ_INS_AFI, SYSZ_INS_AG, SYSZ_INS_AGF, SYSZ_INS_AGFI, SYSZ_INS_AGFR, SYSZ_INS_AGHI, SYSZ_INS_AGHIK, SYSZ_INS_AGR, SYSZ_INS_AGRK, SYSZ_INS_AGSI, SYSZ_INS_AH, SYSZ_INS_AHI, SYSZ_INS_AHIK, SYSZ_INS_AHY, SYSZ_INS_AIH, SYSZ_INS_AL, SYSZ_INS_ALC, SYSZ_INS_ALCG, SYSZ_INS_ALCGR, SYSZ_INS_ALCR, SYSZ_INS_ALFI, SYSZ_INS_ALG, SYSZ_INS_ALGF, SYSZ_INS_ALGFI, SYSZ_INS_ALGFR, SYSZ_INS_ALGHSIK, SYSZ_INS_ALGR, SYSZ_INS_ALGRK, SYSZ_INS_ALHSIK, SYSZ_INS_ALR, SYSZ_INS_ALRK, SYSZ_INS_ALY, SYSZ_INS_AR, SYSZ_INS_ARK, SYSZ_INS_ASI, SYSZ_INS_AXBR, SYSZ_INS_AY, SYSZ_INS_BCR, SYSZ_INS_BRC, SYSZ_INS_BRCL, SYSZ_INS_CGIJ, SYSZ_INS_CGRJ, SYSZ_INS_CIJ, SYSZ_INS_CLGIJ, SYSZ_INS_CLGRJ, SYSZ_INS_CLIJ, SYSZ_INS_CLRJ, SYSZ_INS_CRJ, SYSZ_INS_BER, SYSZ_INS_JE, SYSZ_INS_JGE, SYSZ_INS_LOCE, SYSZ_INS_LOCGE, SYSZ_INS_LOCGRE, SYSZ_INS_LOCRE, SYSZ_INS_STOCE, SYSZ_INS_STOCGE, SYSZ_INS_BHR, SYSZ_INS_BHER, SYSZ_INS_JHE, SYSZ_INS_JGHE, SYSZ_INS_LOCHE, SYSZ_INS_LOCGHE, SYSZ_INS_LOCGRHE, SYSZ_INS_LOCRHE, SYSZ_INS_STOCHE, SYSZ_INS_STOCGHE, SYSZ_INS_JH, SYSZ_INS_JGH, SYSZ_INS_LOCH, SYSZ_INS_LOCGH, SYSZ_INS_LOCGRH, SYSZ_INS_LOCRH, SYSZ_INS_STOCH, SYSZ_INS_STOCGH, SYSZ_INS_CGIJNLH, SYSZ_INS_CGRJNLH, SYSZ_INS_CIJNLH, SYSZ_INS_CLGIJNLH, SYSZ_INS_CLGRJNLH, SYSZ_INS_CLIJNLH, SYSZ_INS_CLRJNLH, SYSZ_INS_CRJNLH, SYSZ_INS_CGIJE, SYSZ_INS_CGRJE, SYSZ_INS_CIJE, SYSZ_INS_CLGIJE, SYSZ_INS_CLGRJE, SYSZ_INS_CLIJE, SYSZ_INS_CLRJE, SYSZ_INS_CRJE, SYSZ_INS_CGIJNLE, SYSZ_INS_CGRJNLE, SYSZ_INS_CIJNLE, SYSZ_INS_CLGIJNLE, SYSZ_INS_CLGRJNLE, SYSZ_INS_CLIJNLE, SYSZ_INS_CLRJNLE, SYSZ_INS_CRJNLE, SYSZ_INS_CGIJH, SYSZ_INS_CGRJH, SYSZ_INS_CIJH, SYSZ_INS_CLGIJH, SYSZ_INS_CLGRJH, SYSZ_INS_CLIJH, SYSZ_INS_CLRJH, SYSZ_INS_CRJH, SYSZ_INS_CGIJNL, SYSZ_INS_CGRJNL, SYSZ_INS_CIJNL, SYSZ_INS_CLGIJNL, SYSZ_INS_CLGRJNL, SYSZ_INS_CLIJNL, SYSZ_INS_CLRJNL, SYSZ_INS_CRJNL, SYSZ_INS_CGIJHE, SYSZ_INS_CGRJHE, SYSZ_INS_CIJHE, SYSZ_INS_CLGIJHE, SYSZ_INS_CLGRJHE, SYSZ_INS_CLIJHE, SYSZ_INS_CLRJHE, SYSZ_INS_CRJHE, SYSZ_INS_CGIJNHE, SYSZ_INS_CGRJNHE, SYSZ_INS_CIJNHE, SYSZ_INS_CLGIJNHE, SYSZ_INS_CLGRJNHE, SYSZ_INS_CLIJNHE, SYSZ_INS_CLRJNHE, SYSZ_INS_CRJNHE, SYSZ_INS_CGIJL, SYSZ_INS_CGRJL, SYSZ_INS_CIJL, SYSZ_INS_CLGIJL, SYSZ_INS_CLGRJL, SYSZ_INS_CLIJL, SYSZ_INS_CLRJL, SYSZ_INS_CRJL, SYSZ_INS_CGIJNH, SYSZ_INS_CGRJNH, SYSZ_INS_CIJNH, SYSZ_INS_CLGIJNH, SYSZ_INS_CLGRJNH, SYSZ_INS_CLIJNH, SYSZ_INS_CLRJNH, SYSZ_INS_CRJNH, SYSZ_INS_CGIJLE, SYSZ_INS_CGRJLE, SYSZ_INS_CIJLE, SYSZ_INS_CLGIJLE, SYSZ_INS_CLGRJLE, SYSZ_INS_CLIJLE, SYSZ_INS_CLRJLE, SYSZ_INS_CRJLE, SYSZ_INS_CGIJNE, SYSZ_INS_CGRJNE, SYSZ_INS_CIJNE, SYSZ_INS_CLGIJNE, SYSZ_INS_CLGRJNE, SYSZ_INS_CLIJNE, SYSZ_INS_CLRJNE, SYSZ_INS_CRJNE, SYSZ_INS_CGIJLH, SYSZ_INS_CGRJLH, SYSZ_INS_CIJLH, SYSZ_INS_CLGIJLH, SYSZ_INS_CLGRJLH, SYSZ_INS_CLIJLH, SYSZ_INS_CLRJLH, SYSZ_INS_CRJLH, SYSZ_INS_BLR, SYSZ_INS_BLER, SYSZ_INS_JLE, SYSZ_INS_JGLE, SYSZ_INS_LOCLE, SYSZ_INS_LOCGLE, SYSZ_INS_LOCGRLE, SYSZ_INS_LOCRLE, SYSZ_INS_STOCLE, SYSZ_INS_STOCGLE, SYSZ_INS_BLHR, SYSZ_INS_JLH, SYSZ_INS_JGLH, SYSZ_INS_LOCLH, SYSZ_INS_LOCGLH, SYSZ_INS_LOCGRLH, SYSZ_INS_LOCRLH, SYSZ_INS_STOCLH, SYSZ_INS_STOCGLH, SYSZ_INS_JL, SYSZ_INS_JGL, SYSZ_INS_LOCL, SYSZ_INS_LOCGL, SYSZ_INS_LOCGRL, SYSZ_INS_LOCRL, SYSZ_INS_LOC, SYSZ_INS_LOCG, SYSZ_INS_LOCGR, SYSZ_INS_LOCR, SYSZ_INS_STOCL, SYSZ_INS_STOCGL, SYSZ_INS_BNER, SYSZ_INS_JNE, SYSZ_INS_JGNE, SYSZ_INS_LOCNE, SYSZ_INS_LOCGNE, SYSZ_INS_LOCGRNE, SYSZ_INS_LOCRNE, SYSZ_INS_STOCNE, SYSZ_INS_STOCGNE, SYSZ_INS_BNHR, SYSZ_INS_BNHER, SYSZ_INS_JNHE, SYSZ_INS_JGNHE, SYSZ_INS_LOCNHE, SYSZ_INS_LOCGNHE, SYSZ_INS_LOCGRNHE, SYSZ_INS_LOCRNHE, SYSZ_INS_STOCNHE, SYSZ_INS_STOCGNHE, SYSZ_INS_JNH, SYSZ_INS_JGNH, SYSZ_INS_LOCNH, SYSZ_INS_LOCGNH, SYSZ_INS_LOCGRNH, SYSZ_INS_LOCRNH, SYSZ_INS_STOCNH, SYSZ_INS_STOCGNH, SYSZ_INS_BNLR, SYSZ_INS_BNLER, SYSZ_INS_JNLE, SYSZ_INS_JGNLE, SYSZ_INS_LOCNLE, SYSZ_INS_LOCGNLE, SYSZ_INS_LOCGRNLE, SYSZ_INS_LOCRNLE, SYSZ_INS_STOCNLE, SYSZ_INS_STOCGNLE, SYSZ_INS_BNLHR, SYSZ_INS_JNLH, SYSZ_INS_JGNLH, SYSZ_INS_LOCNLH, SYSZ_INS_LOCGNLH, SYSZ_INS_LOCGRNLH, SYSZ_INS_LOCRNLH, SYSZ_INS_STOCNLH, SYSZ_INS_STOCGNLH, SYSZ_INS_JNL, SYSZ_INS_JGNL, SYSZ_INS_LOCNL, SYSZ_INS_LOCGNL, SYSZ_INS_LOCGRNL, SYSZ_INS_LOCRNL, SYSZ_INS_STOCNL, SYSZ_INS_STOCGNL, SYSZ_INS_BNOR, SYSZ_INS_JNO, SYSZ_INS_JGNO, SYSZ_INS_LOCNO, SYSZ_INS_LOCGNO, SYSZ_INS_LOCGRNO, SYSZ_INS_LOCRNO, SYSZ_INS_STOCNO, SYSZ_INS_STOCGNO, SYSZ_INS_BOR, SYSZ_INS_JO, SYSZ_INS_JGO, SYSZ_INS_LOCO, SYSZ_INS_LOCGO, SYSZ_INS_LOCGRO, SYSZ_INS_LOCRO, SYSZ_INS_STOCO, SYSZ_INS_STOCGO, SYSZ_INS_STOC, SYSZ_INS_STOCG, SYSZ_INS_BASR, SYSZ_INS_BR, SYSZ_INS_BRAS, SYSZ_INS_BRASL, SYSZ_INS_J, SYSZ_INS_JG, SYSZ_INS_BRCT, SYSZ_INS_BRCTG, SYSZ_INS_C, SYSZ_INS_CDB, SYSZ_INS_CDBR, SYSZ_INS_CDFBR, SYSZ_INS_CDGBR, SYSZ_INS_CDLFBR, SYSZ_INS_CDLGBR, SYSZ_INS_CEB, SYSZ_INS_CEBR, SYSZ_INS_CEFBR, SYSZ_INS_CEGBR, SYSZ_INS_CELFBR, SYSZ_INS_CELGBR, SYSZ_INS_CFDBR, SYSZ_INS_CFEBR, SYSZ_INS_CFI, SYSZ_INS_CFXBR, SYSZ_INS_CG, SYSZ_INS_CGDBR, SYSZ_INS_CGEBR, SYSZ_INS_CGF, SYSZ_INS_CGFI, SYSZ_INS_CGFR, SYSZ_INS_CGFRL, SYSZ_INS_CGH, SYSZ_INS_CGHI, SYSZ_INS_CGHRL, SYSZ_INS_CGHSI, SYSZ_INS_CGR, SYSZ_INS_CGRL, SYSZ_INS_CGXBR, SYSZ_INS_CH, SYSZ_INS_CHF, SYSZ_INS_CHHSI, SYSZ_INS_CHI, SYSZ_INS_CHRL, SYSZ_INS_CHSI, SYSZ_INS_CHY, SYSZ_INS_CIH, SYSZ_INS_CL, SYSZ_INS_CLC, SYSZ_INS_CLFDBR, SYSZ_INS_CLFEBR, SYSZ_INS_CLFHSI, SYSZ_INS_CLFI, SYSZ_INS_CLFXBR, SYSZ_INS_CLG, SYSZ_INS_CLGDBR, SYSZ_INS_CLGEBR, SYSZ_INS_CLGF, SYSZ_INS_CLGFI, SYSZ_INS_CLGFR, SYSZ_INS_CLGFRL, SYSZ_INS_CLGHRL, SYSZ_INS_CLGHSI, SYSZ_INS_CLGR, SYSZ_INS_CLGRL, SYSZ_INS_CLGXBR, SYSZ_INS_CLHF, SYSZ_INS_CLHHSI, SYSZ_INS_CLHRL, SYSZ_INS_CLI, SYSZ_INS_CLIH, SYSZ_INS_CLIY, SYSZ_INS_CLR, SYSZ_INS_CLRL, SYSZ_INS_CLST, SYSZ_INS_CLY, SYSZ_INS_CPSDR, SYSZ_INS_CR, SYSZ_INS_CRL, SYSZ_INS_CS, SYSZ_INS_CSG, SYSZ_INS_CSY, SYSZ_INS_CXBR, SYSZ_INS_CXFBR, SYSZ_INS_CXGBR, SYSZ_INS_CXLFBR, SYSZ_INS_CXLGBR, SYSZ_INS_CY, SYSZ_INS_DDB, SYSZ_INS_DDBR, SYSZ_INS_DEB, SYSZ_INS_DEBR, SYSZ_INS_DL, SYSZ_INS_DLG, SYSZ_INS_DLGR, SYSZ_INS_DLR, SYSZ_INS_DSG, SYSZ_INS_DSGF, SYSZ_INS_DSGFR, SYSZ_INS_DSGR, SYSZ_INS_DXBR, SYSZ_INS_EAR, SYSZ_INS_FIDBR, SYSZ_INS_FIDBRA, SYSZ_INS_FIEBR, SYSZ_INS_FIEBRA, SYSZ_INS_FIXBR, SYSZ_INS_FIXBRA, SYSZ_INS_FLOGR, SYSZ_INS_IC, SYSZ_INS_ICY, SYSZ_INS_IIHF, SYSZ_INS_IIHH, SYSZ_INS_IIHL, SYSZ_INS_IILF, SYSZ_INS_IILH, SYSZ_INS_IILL, SYSZ_INS_IPM, SYSZ_INS_L, SYSZ_INS_LA, SYSZ_INS_LAA, SYSZ_INS_LAAG, SYSZ_INS_LAAL, SYSZ_INS_LAALG, SYSZ_INS_LAN, SYSZ_INS_LANG, SYSZ_INS_LAO, SYSZ_INS_LAOG, SYSZ_INS_LARL, SYSZ_INS_LAX, SYSZ_INS_LAXG, SYSZ_INS_LAY, SYSZ_INS_LB, SYSZ_INS_LBH, SYSZ_INS_LBR, SYSZ_INS_LCDBR, SYSZ_INS_LCEBR, SYSZ_INS_LCGFR, SYSZ_INS_LCGR, SYSZ_INS_LCR, SYSZ_INS_LCXBR, SYSZ_INS_LD, SYSZ_INS_LDEB, SYSZ_INS_LDEBR, SYSZ_INS_LDGR, SYSZ_INS_LDR, SYSZ_INS_LDXBR, SYSZ_INS_LDXBRA, SYSZ_INS_LDY, SYSZ_INS_LE, SYSZ_INS_LEDBR, SYSZ_INS_LEDBRA, SYSZ_INS_LER, SYSZ_INS_LEXBR, SYSZ_INS_LEXBRA, SYSZ_INS_LEY, SYSZ_INS_LFH, SYSZ_INS_LG, SYSZ_INS_LGB, SYSZ_INS_LGBR, SYSZ_INS_LGDR, SYSZ_INS_LGF, SYSZ_INS_LGFI, SYSZ_INS_LGFR, SYSZ_INS_LGFRL, SYSZ_INS_LGH, SYSZ_INS_LGHI, SYSZ_INS_LGHR, SYSZ_INS_LGHRL, SYSZ_INS_LGR, SYSZ_INS_LGRL, SYSZ_INS_LH, SYSZ_INS_LHH, SYSZ_INS_LHI, SYSZ_INS_LHR, SYSZ_INS_LHRL, SYSZ_INS_LHY, SYSZ_INS_LLC, SYSZ_INS_LLCH, SYSZ_INS_LLCR, SYSZ_INS_LLGC, SYSZ_INS_LLGCR, SYSZ_INS_LLGF, SYSZ_INS_LLGFR, SYSZ_INS_LLGFRL, SYSZ_INS_LLGH, SYSZ_INS_LLGHR, SYSZ_INS_LLGHRL, SYSZ_INS_LLH, SYSZ_INS_LLHH, SYSZ_INS_LLHR, SYSZ_INS_LLHRL, SYSZ_INS_LLIHF, SYSZ_INS_LLIHH, SYSZ_INS_LLIHL, SYSZ_INS_LLILF, SYSZ_INS_LLILH, SYSZ_INS_LLILL, SYSZ_INS_LMG, SYSZ_INS_LNDBR, SYSZ_INS_LNEBR, SYSZ_INS_LNGFR, SYSZ_INS_LNGR, SYSZ_INS_LNR, SYSZ_INS_LNXBR, SYSZ_INS_LPDBR, SYSZ_INS_LPEBR, SYSZ_INS_LPGFR, SYSZ_INS_LPGR, SYSZ_INS_LPR, SYSZ_INS_LPXBR, SYSZ_INS_LR, SYSZ_INS_LRL, SYSZ_INS_LRV, SYSZ_INS_LRVG, SYSZ_INS_LRVGR, SYSZ_INS_LRVR, SYSZ_INS_LT, SYSZ_INS_LTDBR, SYSZ_INS_LTEBR, SYSZ_INS_LTG, SYSZ_INS_LTGF, SYSZ_INS_LTGFR, SYSZ_INS_LTGR, SYSZ_INS_LTR, SYSZ_INS_LTXBR, SYSZ_INS_LXDB, SYSZ_INS_LXDBR, SYSZ_INS_LXEB, SYSZ_INS_LXEBR, SYSZ_INS_LXR, SYSZ_INS_LY, SYSZ_INS_LZDR, SYSZ_INS_LZER, SYSZ_INS_LZXR, SYSZ_INS_MADB, SYSZ_INS_MADBR, SYSZ_INS_MAEB, SYSZ_INS_MAEBR, SYSZ_INS_MDB, SYSZ_INS_MDBR, SYSZ_INS_MDEB, SYSZ_INS_MDEBR, SYSZ_INS_MEEB, SYSZ_INS_MEEBR, SYSZ_INS_MGHI, SYSZ_INS_MH, SYSZ_INS_MHI, SYSZ_INS_MHY, SYSZ_INS_MLG, SYSZ_INS_MLGR, SYSZ_INS_MS, SYSZ_INS_MSDB, SYSZ_INS_MSDBR, SYSZ_INS_MSEB, SYSZ_INS_MSEBR, SYSZ_INS_MSFI, SYSZ_INS_MSG, SYSZ_INS_MSGF, SYSZ_INS_MSGFI, SYSZ_INS_MSGFR, SYSZ_INS_MSGR, SYSZ_INS_MSR, SYSZ_INS_MSY, SYSZ_INS_MVC, SYSZ_INS_MVGHI, SYSZ_INS_MVHHI, SYSZ_INS_MVHI, SYSZ_INS_MVI, SYSZ_INS_MVIY, SYSZ_INS_MVST, SYSZ_INS_MXBR, SYSZ_INS_MXDB, SYSZ_INS_MXDBR, SYSZ_INS_N, SYSZ_INS_NC, SYSZ_INS_NG, SYSZ_INS_NGR, SYSZ_INS_NGRK, SYSZ_INS_NI, SYSZ_INS_NIHF, SYSZ_INS_NIHH, SYSZ_INS_NIHL, SYSZ_INS_NILF, SYSZ_INS_NILH, SYSZ_INS_NILL, SYSZ_INS_NIY, SYSZ_INS_NR, SYSZ_INS_NRK, SYSZ_INS_NY, SYSZ_INS_O, SYSZ_INS_OC, SYSZ_INS_OG, SYSZ_INS_OGR, SYSZ_INS_OGRK, SYSZ_INS_OI, SYSZ_INS_OIHF, SYSZ_INS_OIHH, SYSZ_INS_OIHL, SYSZ_INS_OILF, SYSZ_INS_OILH, SYSZ_INS_OILL, SYSZ_INS_OIY, SYSZ_INS_OR, SYSZ_INS_ORK, SYSZ_INS_OY, SYSZ_INS_PFD, SYSZ_INS_PFDRL, SYSZ_INS_RISBG, SYSZ_INS_RISBHG, SYSZ_INS_RISBLG, SYSZ_INS_RLL, SYSZ_INS_RLLG, SYSZ_INS_RNSBG, SYSZ_INS_ROSBG, SYSZ_INS_RXSBG, SYSZ_INS_S, SYSZ_INS_SDB, SYSZ_INS_SDBR, SYSZ_INS_SEB, SYSZ_INS_SEBR, SYSZ_INS_SG, SYSZ_INS_SGF, SYSZ_INS_SGFR, SYSZ_INS_SGR, SYSZ_INS_SGRK, SYSZ_INS_SH, SYSZ_INS_SHY, SYSZ_INS_SL, SYSZ_INS_SLB, SYSZ_INS_SLBG, SYSZ_INS_SLBR, SYSZ_INS_SLFI, SYSZ_INS_SLG, SYSZ_INS_SLBGR, SYSZ_INS_SLGF, SYSZ_INS_SLGFI, SYSZ_INS_SLGFR, SYSZ_INS_SLGR, SYSZ_INS_SLGRK, SYSZ_INS_SLL, SYSZ_INS_SLLG, SYSZ_INS_SLLK, SYSZ_INS_SLR, SYSZ_INS_SLRK, SYSZ_INS_SLY, SYSZ_INS_SQDB, SYSZ_INS_SQDBR, SYSZ_INS_SQEB, SYSZ_INS_SQEBR, SYSZ_INS_SQXBR, SYSZ_INS_SR, SYSZ_INS_SRA, SYSZ_INS_SRAG, SYSZ_INS_SRAK, SYSZ_INS_SRK, SYSZ_INS_SRL, SYSZ_INS_SRLG, SYSZ_INS_SRLK, SYSZ_INS_SRST, SYSZ_INS_ST, SYSZ_INS_STC, SYSZ_INS_STCH, SYSZ_INS_STCY, SYSZ_INS_STD, SYSZ_INS_STDY, SYSZ_INS_STE, SYSZ_INS_STEY, SYSZ_INS_STFH, SYSZ_INS_STG, SYSZ_INS_STGRL, SYSZ_INS_STH, SYSZ_INS_STHH, SYSZ_INS_STHRL, SYSZ_INS_STHY, SYSZ_INS_STMG, SYSZ_INS_STRL, SYSZ_INS_STRV, SYSZ_INS_STRVG, SYSZ_INS_STY, SYSZ_INS_SXBR, SYSZ_INS_SY, SYSZ_INS_TM, SYSZ_INS_TMHH, SYSZ_INS_TMHL, SYSZ_INS_TMLH, SYSZ_INS_TMLL, SYSZ_INS_TMY, SYSZ_INS_X, SYSZ_INS_XC, SYSZ_INS_XG, SYSZ_INS_XGR, SYSZ_INS_XGRK, SYSZ_INS_XI, SYSZ_INS_XIHF, SYSZ_INS_XILF, SYSZ_INS_XIY, SYSZ_INS_XR, SYSZ_INS_XRK, SYSZ_INS_XY, SYSZ_INS_AD, SYSZ_INS_ADR, SYSZ_INS_ADTR, SYSZ_INS_ADTRA, SYSZ_INS_AE, SYSZ_INS_AER, SYSZ_INS_AGH, SYSZ_INS_AHHHR, SYSZ_INS_AHHLR, SYSZ_INS_ALGSI, SYSZ_INS_ALHHHR, SYSZ_INS_ALHHLR, SYSZ_INS_ALSI, SYSZ_INS_ALSIH, SYSZ_INS_ALSIHN, SYSZ_INS_AP, SYSZ_INS_AU, SYSZ_INS_AUR, SYSZ_INS_AW, SYSZ_INS_AWR, SYSZ_INS_AXR, SYSZ_INS_AXTR, SYSZ_INS_AXTRA, SYSZ_INS_B, SYSZ_INS_BAKR, SYSZ_INS_BAL, SYSZ_INS_BALR, SYSZ_INS_BAS, SYSZ_INS_BASSM, SYSZ_INS_BC, SYSZ_INS_BCT, SYSZ_INS_BCTG, SYSZ_INS_BCTGR, SYSZ_INS_BCTR, SYSZ_INS_BE, SYSZ_INS_BH, SYSZ_INS_BHE, SYSZ_INS_BI, SYSZ_INS_BIC, SYSZ_INS_BIE, SYSZ_INS_BIH, SYSZ_INS_BIHE, SYSZ_INS_BIL, SYSZ_INS_BILE, SYSZ_INS_BILH, SYSZ_INS_BIM, SYSZ_INS_BINE, SYSZ_INS_BINH, SYSZ_INS_BINHE, SYSZ_INS_BINL, SYSZ_INS_BINLE, SYSZ_INS_BINLH, SYSZ_INS_BINM, SYSZ_INS_BINO, SYSZ_INS_BINP, SYSZ_INS_BINZ, SYSZ_INS_BIO, SYSZ_INS_BIP, SYSZ_INS_BIZ, SYSZ_INS_BL, SYSZ_INS_BLE, SYSZ_INS_BLH, SYSZ_INS_BM, SYSZ_INS_BMR, SYSZ_INS_BNE, SYSZ_INS_BNH, SYSZ_INS_BNHE, SYSZ_INS_BNL, SYSZ_INS_BNLE, SYSZ_INS_BNLH, SYSZ_INS_BNM, SYSZ_INS_BNMR, SYSZ_INS_BNO, SYSZ_INS_BNP, SYSZ_INS_BNPR, SYSZ_INS_BNZ, SYSZ_INS_BNZR, SYSZ_INS_BO, SYSZ_INS_BP, SYSZ_INS_BPP, SYSZ_INS_BPR, SYSZ_INS_BPRP, SYSZ_INS_BRCTH, SYSZ_INS_BRXH, SYSZ_INS_BRXHG, SYSZ_INS_BRXLE, SYSZ_INS_BRXLG, SYSZ_INS_BSA, SYSZ_INS_BSG, SYSZ_INS_BSM, SYSZ_INS_BXH, SYSZ_INS_BXHG, SYSZ_INS_BXLE, SYSZ_INS_BXLEG, SYSZ_INS_BZ, SYSZ_INS_BZR, SYSZ_INS_CD, SYSZ_INS_CDFBRA, SYSZ_INS_CDFR, SYSZ_INS_CDFTR, SYSZ_INS_CDGBRA, SYSZ_INS_CDGR, SYSZ_INS_CDGTR, SYSZ_INS_CDGTRA, SYSZ_INS_CDLFTR, SYSZ_INS_CDLGTR, SYSZ_INS_CDPT, SYSZ_INS_CDR, SYSZ_INS_CDS, SYSZ_INS_CDSG, SYSZ_INS_CDSTR, SYSZ_INS_CDSY, SYSZ_INS_CDTR, SYSZ_INS_CDUTR, SYSZ_INS_CDZT, SYSZ_INS_CE, SYSZ_INS_CEDTR, SYSZ_INS_CEFBRA, SYSZ_INS_CEFR, SYSZ_INS_CEGBRA, SYSZ_INS_CEGR, SYSZ_INS_CER, SYSZ_INS_CEXTR, SYSZ_INS_CFC, SYSZ_INS_CFDBRA, SYSZ_INS_CFDR, SYSZ_INS_CFDTR, SYSZ_INS_CFEBRA, SYSZ_INS_CFER, SYSZ_INS_CFXBRA, SYSZ_INS_CFXR, SYSZ_INS_CFXTR, SYSZ_INS_CGDBRA, SYSZ_INS_CGDR, SYSZ_INS_CGDTR, SYSZ_INS_CGDTRA, SYSZ_INS_CGEBRA, SYSZ_INS_CGER, SYSZ_INS_CGIB, SYSZ_INS_CGIBE, SYSZ_INS_CGIBH, SYSZ_INS_CGIBHE, SYSZ_INS_CGIBL, SYSZ_INS_CGIBLE, SYSZ_INS_CGIBLH, SYSZ_INS_CGIBNE, SYSZ_INS_CGIBNH, SYSZ_INS_CGIBNHE, SYSZ_INS_CGIBNL, SYSZ_INS_CGIBNLE, SYSZ_INS_CGIBNLH, SYSZ_INS_CGIT, SYSZ_INS_CGITE, SYSZ_INS_CGITH, SYSZ_INS_CGITHE, SYSZ_INS_CGITL, SYSZ_INS_CGITLE, SYSZ_INS_CGITLH, SYSZ_INS_CGITNE, SYSZ_INS_CGITNH, SYSZ_INS_CGITNHE, SYSZ_INS_CGITNL, SYSZ_INS_CGITNLE, SYSZ_INS_CGITNLH, SYSZ_INS_CGRB, SYSZ_INS_CGRBE, SYSZ_INS_CGRBH, SYSZ_INS_CGRBHE, SYSZ_INS_CGRBL, SYSZ_INS_CGRBLE, SYSZ_INS_CGRBLH, SYSZ_INS_CGRBNE, SYSZ_INS_CGRBNH, SYSZ_INS_CGRBNHE, SYSZ_INS_CGRBNL, SYSZ_INS_CGRBNLE, SYSZ_INS_CGRBNLH, SYSZ_INS_CGRT, SYSZ_INS_CGRTE, SYSZ_INS_CGRTH, SYSZ_INS_CGRTHE, SYSZ_INS_CGRTL, SYSZ_INS_CGRTLE, SYSZ_INS_CGRTLH, SYSZ_INS_CGRTNE, SYSZ_INS_CGRTNH, SYSZ_INS_CGRTNHE, SYSZ_INS_CGRTNL, SYSZ_INS_CGRTNLE, SYSZ_INS_CGRTNLH, SYSZ_INS_CGXBRA, SYSZ_INS_CGXR, SYSZ_INS_CGXTR, SYSZ_INS_CGXTRA, SYSZ_INS_CHHR, SYSZ_INS_CHLR, SYSZ_INS_CIB, SYSZ_INS_CIBE, SYSZ_INS_CIBH, SYSZ_INS_CIBHE, SYSZ_INS_CIBL, SYSZ_INS_CIBLE, SYSZ_INS_CIBLH, SYSZ_INS_CIBNE, SYSZ_INS_CIBNH, SYSZ_INS_CIBNHE, SYSZ_INS_CIBNL, SYSZ_INS_CIBNLE, SYSZ_INS_CIBNLH, SYSZ_INS_CIT, SYSZ_INS_CITE, SYSZ_INS_CITH, SYSZ_INS_CITHE, SYSZ_INS_CITL, SYSZ_INS_CITLE, SYSZ_INS_CITLH, SYSZ_INS_CITNE, SYSZ_INS_CITNH, SYSZ_INS_CITNHE, SYSZ_INS_CITNL, SYSZ_INS_CITNLE, SYSZ_INS_CITNLH, SYSZ_INS_CKSM, SYSZ_INS_CLCL, SYSZ_INS_CLCLE, SYSZ_INS_CLCLU, SYSZ_INS_CLFDTR, SYSZ_INS_CLFIT, SYSZ_INS_CLFITE, SYSZ_INS_CLFITH, SYSZ_INS_CLFITHE, SYSZ_INS_CLFITL, SYSZ_INS_CLFITLE, SYSZ_INS_CLFITLH, SYSZ_INS_CLFITNE, SYSZ_INS_CLFITNH, SYSZ_INS_CLFITNHE, SYSZ_INS_CLFITNL, SYSZ_INS_CLFITNLE, SYSZ_INS_CLFITNLH, SYSZ_INS_CLFXTR, SYSZ_INS_CLGDTR, SYSZ_INS_CLGIB, SYSZ_INS_CLGIBE, SYSZ_INS_CLGIBH, SYSZ_INS_CLGIBHE, SYSZ_INS_CLGIBL, SYSZ_INS_CLGIBLE, SYSZ_INS_CLGIBLH, SYSZ_INS_CLGIBNE, SYSZ_INS_CLGIBNH, SYSZ_INS_CLGIBNHE, SYSZ_INS_CLGIBNL, SYSZ_INS_CLGIBNLE, SYSZ_INS_CLGIBNLH, SYSZ_INS_CLGIT, SYSZ_INS_CLGITE, SYSZ_INS_CLGITH, SYSZ_INS_CLGITHE, SYSZ_INS_CLGITL, SYSZ_INS_CLGITLE, SYSZ_INS_CLGITLH, SYSZ_INS_CLGITNE, SYSZ_INS_CLGITNH, SYSZ_INS_CLGITNHE, SYSZ_INS_CLGITNL, SYSZ_INS_CLGITNLE, SYSZ_INS_CLGITNLH, SYSZ_INS_CLGRB, SYSZ_INS_CLGRBE, SYSZ_INS_CLGRBH, SYSZ_INS_CLGRBHE, SYSZ_INS_CLGRBL, SYSZ_INS_CLGRBLE, SYSZ_INS_CLGRBLH, SYSZ_INS_CLGRBNE, SYSZ_INS_CLGRBNH, SYSZ_INS_CLGRBNHE, SYSZ_INS_CLGRBNL, SYSZ_INS_CLGRBNLE, SYSZ_INS_CLGRBNLH, SYSZ_INS_CLGRT, SYSZ_INS_CLGRTE, SYSZ_INS_CLGRTH, SYSZ_INS_CLGRTHE, SYSZ_INS_CLGRTL, SYSZ_INS_CLGRTLE, SYSZ_INS_CLGRTLH, SYSZ_INS_CLGRTNE, SYSZ_INS_CLGRTNH, SYSZ_INS_CLGRTNHE, SYSZ_INS_CLGRTNL, SYSZ_INS_CLGRTNLE, SYSZ_INS_CLGRTNLH, SYSZ_INS_CLGT, SYSZ_INS_CLGTE, SYSZ_INS_CLGTH, SYSZ_INS_CLGTHE, SYSZ_INS_CLGTL, SYSZ_INS_CLGTLE, SYSZ_INS_CLGTLH, SYSZ_INS_CLGTNE, SYSZ_INS_CLGTNH, SYSZ_INS_CLGTNHE, SYSZ_INS_CLGTNL, SYSZ_INS_CLGTNLE, SYSZ_INS_CLGTNLH, SYSZ_INS_CLGXTR, SYSZ_INS_CLHHR, SYSZ_INS_CLHLR, SYSZ_INS_CLIB, SYSZ_INS_CLIBE, SYSZ_INS_CLIBH, SYSZ_INS_CLIBHE, SYSZ_INS_CLIBL, SYSZ_INS_CLIBLE, SYSZ_INS_CLIBLH, SYSZ_INS_CLIBNE, SYSZ_INS_CLIBNH, SYSZ_INS_CLIBNHE, SYSZ_INS_CLIBNL, SYSZ_INS_CLIBNLE, SYSZ_INS_CLIBNLH, SYSZ_INS_CLM, SYSZ_INS_CLMH, SYSZ_INS_CLMY, SYSZ_INS_CLRB, SYSZ_INS_CLRBE, SYSZ_INS_CLRBH, SYSZ_INS_CLRBHE, SYSZ_INS_CLRBL, SYSZ_INS_CLRBLE, SYSZ_INS_CLRBLH, SYSZ_INS_CLRBNE, SYSZ_INS_CLRBNH, SYSZ_INS_CLRBNHE, SYSZ_INS_CLRBNL, SYSZ_INS_CLRBNLE, SYSZ_INS_CLRBNLH, SYSZ_INS_CLRT, SYSZ_INS_CLRTE, SYSZ_INS_CLRTH, SYSZ_INS_CLRTHE, SYSZ_INS_CLRTL, SYSZ_INS_CLRTLE, SYSZ_INS_CLRTLH, SYSZ_INS_CLRTNE, SYSZ_INS_CLRTNH, SYSZ_INS_CLRTNHE, SYSZ_INS_CLRTNL, SYSZ_INS_CLRTNLE, SYSZ_INS_CLRTNLH, SYSZ_INS_CLT, SYSZ_INS_CLTE, SYSZ_INS_CLTH, SYSZ_INS_CLTHE, SYSZ_INS_CLTL, SYSZ_INS_CLTLE, SYSZ_INS_CLTLH, SYSZ_INS_CLTNE, SYSZ_INS_CLTNH, SYSZ_INS_CLTNHE, SYSZ_INS_CLTNL, SYSZ_INS_CLTNLE, SYSZ_INS_CLTNLH, SYSZ_INS_CMPSC, SYSZ_INS_CP, SYSZ_INS_CPDT, SYSZ_INS_CPXT, SYSZ_INS_CPYA, SYSZ_INS_CRB, SYSZ_INS_CRBE, SYSZ_INS_CRBH, SYSZ_INS_CRBHE, SYSZ_INS_CRBL, SYSZ_INS_CRBLE, SYSZ_INS_CRBLH, SYSZ_INS_CRBNE, SYSZ_INS_CRBNH, SYSZ_INS_CRBNHE, SYSZ_INS_CRBNL, SYSZ_INS_CRBNLE, SYSZ_INS_CRBNLH, SYSZ_INS_CRDTE, SYSZ_INS_CRT, SYSZ_INS_CRTE, SYSZ_INS_CRTH, SYSZ_INS_CRTHE, SYSZ_INS_CRTL, SYSZ_INS_CRTLE, SYSZ_INS_CRTLH, SYSZ_INS_CRTNE, SYSZ_INS_CRTNH, SYSZ_INS_CRTNHE, SYSZ_INS_CRTNL, SYSZ_INS_CRTNLE, SYSZ_INS_CRTNLH, SYSZ_INS_CSCH, SYSZ_INS_CSDTR, SYSZ_INS_CSP, SYSZ_INS_CSPG, SYSZ_INS_CSST, SYSZ_INS_CSXTR, SYSZ_INS_CU12, SYSZ_INS_CU14, SYSZ_INS_CU21, SYSZ_INS_CU24, SYSZ_INS_CU41, SYSZ_INS_CU42, SYSZ_INS_CUDTR, SYSZ_INS_CUSE, SYSZ_INS_CUTFU, SYSZ_INS_CUUTF, SYSZ_INS_CUXTR, SYSZ_INS_CVB, SYSZ_INS_CVBG, SYSZ_INS_CVBY, SYSZ_INS_CVD, SYSZ_INS_CVDG, SYSZ_INS_CVDY, SYSZ_INS_CXFBRA, SYSZ_INS_CXFR, SYSZ_INS_CXFTR, SYSZ_INS_CXGBRA, SYSZ_INS_CXGR, SYSZ_INS_CXGTR, SYSZ_INS_CXGTRA, SYSZ_INS_CXLFTR, SYSZ_INS_CXLGTR, SYSZ_INS_CXPT, SYSZ_INS_CXR, SYSZ_INS_CXSTR, SYSZ_INS_CXTR, SYSZ_INS_CXUTR, SYSZ_INS_CXZT, SYSZ_INS_CZDT, SYSZ_INS_CZXT, SYSZ_INS_D, SYSZ_INS_DD, SYSZ_INS_DDR, SYSZ_INS_DDTR, SYSZ_INS_DDTRA, SYSZ_INS_DE, SYSZ_INS_DER, SYSZ_INS_DIAG, SYSZ_INS_DIDBR, SYSZ_INS_DIEBR, SYSZ_INS_DP, SYSZ_INS_DR, SYSZ_INS_DXR, SYSZ_INS_DXTR, SYSZ_INS_DXTRA, SYSZ_INS_ECAG, SYSZ_INS_ECCTR, SYSZ_INS_ECPGA, SYSZ_INS_ECTG, SYSZ_INS_ED, SYSZ_INS_EDMK, SYSZ_INS_EEDTR, SYSZ_INS_EEXTR, SYSZ_INS_EFPC, SYSZ_INS_EPAIR, SYSZ_INS_EPAR, SYSZ_INS_EPCTR, SYSZ_INS_EPSW, SYSZ_INS_EREG, SYSZ_INS_EREGG, SYSZ_INS_ESAIR, SYSZ_INS_ESAR, SYSZ_INS_ESDTR, SYSZ_INS_ESEA, SYSZ_INS_ESTA, SYSZ_INS_ESXTR, SYSZ_INS_ETND, SYSZ_INS_EX, SYSZ_INS_EXRL, SYSZ_INS_FIDR, SYSZ_INS_FIDTR, SYSZ_INS_FIER, SYSZ_INS_FIXR, SYSZ_INS_FIXTR, SYSZ_INS_HDR, SYSZ_INS_HER, SYSZ_INS_HSCH, SYSZ_INS_IAC, SYSZ_INS_ICM, SYSZ_INS_ICMH, SYSZ_INS_ICMY, SYSZ_INS_IDTE, SYSZ_INS_IEDTR, SYSZ_INS_IEXTR, SYSZ_INS_IPK, SYSZ_INS_IPTE, SYSZ_INS_IRBM, SYSZ_INS_ISKE, SYSZ_INS_IVSK, SYSZ_INS_JGM, SYSZ_INS_JGNM, SYSZ_INS_JGNP, SYSZ_INS_JGNZ, SYSZ_INS_JGP, SYSZ_INS_JGZ, SYSZ_INS_JM, SYSZ_INS_JNM, SYSZ_INS_JNP, SYSZ_INS_JNZ, SYSZ_INS_JP, SYSZ_INS_JZ, SYSZ_INS_KDB, SYSZ_INS_KDBR, SYSZ_INS_KDTR, SYSZ_INS_KEB, SYSZ_INS_KEBR, SYSZ_INS_KIMD, SYSZ_INS_KLMD, SYSZ_INS_KM, SYSZ_INS_KMA, SYSZ_INS_KMAC, SYSZ_INS_KMC, SYSZ_INS_KMCTR, SYSZ_INS_KMF, SYSZ_INS_KMO, SYSZ_INS_KXBR, SYSZ_INS_KXTR, SYSZ_INS_LAE, SYSZ_INS_LAEY, SYSZ_INS_LAM, SYSZ_INS_LAMY, SYSZ_INS_LASP, SYSZ_INS_LAT, SYSZ_INS_LCBB, SYSZ_INS_LCCTL, SYSZ_INS_LCDFR, SYSZ_INS_LCDR, SYSZ_INS_LCER, SYSZ_INS_LCTL, SYSZ_INS_LCTLG, SYSZ_INS_LCXR, SYSZ_INS_LDE, SYSZ_INS_LDER, SYSZ_INS_LDETR, SYSZ_INS_LDXR, SYSZ_INS_LDXTR, SYSZ_INS_LEDR, SYSZ_INS_LEDTR, SYSZ_INS_LEXR, SYSZ_INS_LFAS, SYSZ_INS_LFHAT, SYSZ_INS_LFPC, SYSZ_INS_LGAT, SYSZ_INS_LGG, SYSZ_INS_LGSC, SYSZ_INS_LLGFAT, SYSZ_INS_LLGFSG, SYSZ_INS_LLGT, SYSZ_INS_LLGTAT, SYSZ_INS_LLGTR, SYSZ_INS_LLZRGF, SYSZ_INS_LM, SYSZ_INS_LMD, SYSZ_INS_LMH, SYSZ_INS_LMY, SYSZ_INS_LNDFR, SYSZ_INS_LNDR, SYSZ_INS_LNER, SYSZ_INS_LNXR, SYSZ_INS_LOCFH, SYSZ_INS_LOCFHE, SYSZ_INS_LOCFHH, SYSZ_INS_LOCFHHE, SYSZ_INS_LOCFHL, SYSZ_INS_LOCFHLE, SYSZ_INS_LOCFHLH, SYSZ_INS_LOCFHM, SYSZ_INS_LOCFHNE, SYSZ_INS_LOCFHNH, SYSZ_INS_LOCFHNHE, SYSZ_INS_LOCFHNL, SYSZ_INS_LOCFHNLE, SYSZ_INS_LOCFHNLH, SYSZ_INS_LOCFHNM, SYSZ_INS_LOCFHNO, SYSZ_INS_LOCFHNP, SYSZ_INS_LOCFHNZ, SYSZ_INS_LOCFHO, SYSZ_INS_LOCFHP, SYSZ_INS_LOCFHR, SYSZ_INS_LOCFHRE, SYSZ_INS_LOCFHRH, SYSZ_INS_LOCFHRHE, SYSZ_INS_LOCFHRL, SYSZ_INS_LOCFHRLE, SYSZ_INS_LOCFHRLH, SYSZ_INS_LOCFHRM, SYSZ_INS_LOCFHRNE, SYSZ_INS_LOCFHRNH, SYSZ_INS_LOCFHRNHE, SYSZ_INS_LOCFHRNL, SYSZ_INS_LOCFHRNLE, SYSZ_INS_LOCFHRNLH, SYSZ_INS_LOCFHRNM, SYSZ_INS_LOCFHRNO, SYSZ_INS_LOCFHRNP, SYSZ_INS_LOCFHRNZ, SYSZ_INS_LOCFHRO, SYSZ_INS_LOCFHRP, SYSZ_INS_LOCFHRZ, SYSZ_INS_LOCFHZ, SYSZ_INS_LOCGHI, SYSZ_INS_LOCGHIE, SYSZ_INS_LOCGHIH, SYSZ_INS_LOCGHIHE, SYSZ_INS_LOCGHIL, SYSZ_INS_LOCGHILE, SYSZ_INS_LOCGHILH, SYSZ_INS_LOCGHIM, SYSZ_INS_LOCGHINE, SYSZ_INS_LOCGHINH, SYSZ_INS_LOCGHINHE, SYSZ_INS_LOCGHINL, SYSZ_INS_LOCGHINLE, SYSZ_INS_LOCGHINLH, SYSZ_INS_LOCGHINM, SYSZ_INS_LOCGHINO, SYSZ_INS_LOCGHINP, SYSZ_INS_LOCGHINZ, SYSZ_INS_LOCGHIO, SYSZ_INS_LOCGHIP, SYSZ_INS_LOCGHIZ, SYSZ_INS_LOCGM, SYSZ_INS_LOCGNM, SYSZ_INS_LOCGNP, SYSZ_INS_LOCGNZ, SYSZ_INS_LOCGP, SYSZ_INS_LOCGRM, SYSZ_INS_LOCGRNM, SYSZ_INS_LOCGRNP, SYSZ_INS_LOCGRNZ, SYSZ_INS_LOCGRP, SYSZ_INS_LOCGRZ, SYSZ_INS_LOCGZ, SYSZ_INS_LOCHHI, SYSZ_INS_LOCHHIE, SYSZ_INS_LOCHHIH, SYSZ_INS_LOCHHIHE, SYSZ_INS_LOCHHIL, SYSZ_INS_LOCHHILE, SYSZ_INS_LOCHHILH, SYSZ_INS_LOCHHIM, SYSZ_INS_LOCHHINE, SYSZ_INS_LOCHHINH, SYSZ_INS_LOCHHINHE, SYSZ_INS_LOCHHINL, SYSZ_INS_LOCHHINLE, SYSZ_INS_LOCHHINLH, SYSZ_INS_LOCHHINM, SYSZ_INS_LOCHHINO, SYSZ_INS_LOCHHINP, SYSZ_INS_LOCHHINZ, SYSZ_INS_LOCHHIO, SYSZ_INS_LOCHHIP, SYSZ_INS_LOCHHIZ, SYSZ_INS_LOCHI, SYSZ_INS_LOCHIE, SYSZ_INS_LOCHIH, SYSZ_INS_LOCHIHE, SYSZ_INS_LOCHIL, SYSZ_INS_LOCHILE, SYSZ_INS_LOCHILH, SYSZ_INS_LOCHIM, SYSZ_INS_LOCHINE, SYSZ_INS_LOCHINH, SYSZ_INS_LOCHINHE, SYSZ_INS_LOCHINL, SYSZ_INS_LOCHINLE, SYSZ_INS_LOCHINLH, SYSZ_INS_LOCHINM, SYSZ_INS_LOCHINO, SYSZ_INS_LOCHINP, SYSZ_INS_LOCHINZ, SYSZ_INS_LOCHIO, SYSZ_INS_LOCHIP, SYSZ_INS_LOCHIZ, SYSZ_INS_LOCM, SYSZ_INS_LOCNM, SYSZ_INS_LOCNP, SYSZ_INS_LOCNZ, SYSZ_INS_LOCP, SYSZ_INS_LOCRM, SYSZ_INS_LOCRNM, SYSZ_INS_LOCRNP, SYSZ_INS_LOCRNZ, SYSZ_INS_LOCRP, SYSZ_INS_LOCRZ, SYSZ_INS_LOCZ, SYSZ_INS_LPCTL, SYSZ_INS_LPD, SYSZ_INS_LPDFR, SYSZ_INS_LPDG, SYSZ_INS_LPDR, SYSZ_INS_LPER, SYSZ_INS_LPP, SYSZ_INS_LPQ, SYSZ_INS_LPSW, SYSZ_INS_LPSWE, SYSZ_INS_LPTEA, SYSZ_INS_LPXR, SYSZ_INS_LRA, SYSZ_INS_LRAG, SYSZ_INS_LRAY, SYSZ_INS_LRDR, SYSZ_INS_LRER, SYSZ_INS_LRVH, SYSZ_INS_LSCTL, SYSZ_INS_LTDR, SYSZ_INS_LTDTR, SYSZ_INS_LTER, SYSZ_INS_LTXR, SYSZ_INS_LTXTR, SYSZ_INS_LURA, SYSZ_INS_LURAG, SYSZ_INS_LXD, SYSZ_INS_LXDR, SYSZ_INS_LXDTR, SYSZ_INS_LXE, SYSZ_INS_LXER, SYSZ_INS_LZRF, SYSZ_INS_LZRG, SYSZ_INS_M, SYSZ_INS_MAD, SYSZ_INS_MADR, SYSZ_INS_MAE, SYSZ_INS_MAER, SYSZ_INS_MAY, SYSZ_INS_MAYH, SYSZ_INS_MAYHR, SYSZ_INS_MAYL, SYSZ_INS_MAYLR, SYSZ_INS_MAYR, SYSZ_INS_MC, SYSZ_INS_MD, SYSZ_INS_MDE, SYSZ_INS_MDER, SYSZ_INS_MDR, SYSZ_INS_MDTR, SYSZ_INS_MDTRA, SYSZ_INS_ME, SYSZ_INS_MEE, SYSZ_INS_MEER, SYSZ_INS_MER, SYSZ_INS_MFY, SYSZ_INS_MG, SYSZ_INS_MGH, SYSZ_INS_MGRK, SYSZ_INS_ML, SYSZ_INS_MLR, SYSZ_INS_MP, SYSZ_INS_MR, SYSZ_INS_MSC, SYSZ_INS_MSCH, SYSZ_INS_MSD, SYSZ_INS_MSDR, SYSZ_INS_MSE, SYSZ_INS_MSER, SYSZ_INS_MSGC, SYSZ_INS_MSGRKC, SYSZ_INS_MSRKC, SYSZ_INS_MSTA, SYSZ_INS_MVCDK, SYSZ_INS_MVCIN, SYSZ_INS_MVCK, SYSZ_INS_MVCL, SYSZ_INS_MVCLE, SYSZ_INS_MVCLU, SYSZ_INS_MVCOS, SYSZ_INS_MVCP, SYSZ_INS_MVCS, SYSZ_INS_MVCSK, SYSZ_INS_MVN, SYSZ_INS_MVO, SYSZ_INS_MVPG, SYSZ_INS_MVZ, SYSZ_INS_MXD, SYSZ_INS_MXDR, SYSZ_INS_MXR, SYSZ_INS_MXTR, SYSZ_INS_MXTRA, SYSZ_INS_MY, SYSZ_INS_MYH, SYSZ_INS_MYHR, SYSZ_INS_MYL, SYSZ_INS_MYLR, SYSZ_INS_MYR, SYSZ_INS_NIAI, SYSZ_INS_NTSTG, SYSZ_INS_PACK, SYSZ_INS_PALB, SYSZ_INS_PC, SYSZ_INS_PCC, SYSZ_INS_PCKMO, SYSZ_INS_PFMF, SYSZ_INS_PFPO, SYSZ_INS_PGIN, SYSZ_INS_PGOUT, SYSZ_INS_PKA, SYSZ_INS_PKU, SYSZ_INS_PLO, SYSZ_INS_POPCNT, SYSZ_INS_PPA, SYSZ_INS_PPNO, SYSZ_INS_PR, SYSZ_INS_PRNO, SYSZ_INS_PT, SYSZ_INS_PTF, SYSZ_INS_PTFF, SYSZ_INS_PTI, SYSZ_INS_PTLB, SYSZ_INS_QADTR, SYSZ_INS_QAXTR, SYSZ_INS_QCTRI, SYSZ_INS_QSI, SYSZ_INS_RCHP, SYSZ_INS_RISBGN, SYSZ_INS_RP, SYSZ_INS_RRBE, SYSZ_INS_RRBM, SYSZ_INS_RRDTR, SYSZ_INS_RRXTR, SYSZ_INS_RSCH, SYSZ_INS_SAC, SYSZ_INS_SACF, SYSZ_INS_SAL, SYSZ_INS_SAM24, SYSZ_INS_SAM31, SYSZ_INS_SAM64, SYSZ_INS_SAR, SYSZ_INS_SCCTR, SYSZ_INS_SCHM, SYSZ_INS_SCK, SYSZ_INS_SCKC, SYSZ_INS_SCKPF, SYSZ_INS_SD, SYSZ_INS_SDR, SYSZ_INS_SDTR, SYSZ_INS_SDTRA, SYSZ_INS_SE, SYSZ_INS_SER, SYSZ_INS_SFASR, SYSZ_INS_SFPC, SYSZ_INS_SGH, SYSZ_INS_SHHHR, SYSZ_INS_SHHLR, SYSZ_INS_SIE, SYSZ_INS_SIGA, SYSZ_INS_SIGP, SYSZ_INS_SLA, SYSZ_INS_SLAG, SYSZ_INS_SLAK, SYSZ_INS_SLDA, SYSZ_INS_SLDL, SYSZ_INS_SLDT, SYSZ_INS_SLHHHR, SYSZ_INS_SLHHLR, SYSZ_INS_SLXT, SYSZ_INS_SP, SYSZ_INS_SPCTR, SYSZ_INS_SPKA, SYSZ_INS_SPM, SYSZ_INS_SPT, SYSZ_INS_SPX, SYSZ_INS_SQD, SYSZ_INS_SQDR, SYSZ_INS_SQE, SYSZ_INS_SQER, SYSZ_INS_SQXR, SYSZ_INS_SRDA, SYSZ_INS_SRDL, SYSZ_INS_SRDT, SYSZ_INS_SRNM, SYSZ_INS_SRNMB, SYSZ_INS_SRNMT, SYSZ_INS_SRP, SYSZ_INS_SRSTU, SYSZ_INS_SRXT, SYSZ_INS_SSAIR, SYSZ_INS_SSAR, SYSZ_INS_SSCH, SYSZ_INS_SSKE, SYSZ_INS_SSM, SYSZ_INS_STAM, SYSZ_INS_STAMY, SYSZ_INS_STAP, SYSZ_INS_STCK, SYSZ_INS_STCKC, SYSZ_INS_STCKE, SYSZ_INS_STCKF, SYSZ_INS_STCM, SYSZ_INS_STCMH, SYSZ_INS_STCMY, SYSZ_INS_STCPS, SYSZ_INS_STCRW, SYSZ_INS_STCTG, SYSZ_INS_STCTL, SYSZ_INS_STFL, SYSZ_INS_STFLE, SYSZ_INS_STFPC, SYSZ_INS_STGSC, SYSZ_INS_STIDP, SYSZ_INS_STM, SYSZ_INS_STMH, SYSZ_INS_STMY, SYSZ_INS_STNSM, SYSZ_INS_STOCFH, SYSZ_INS_STOCFHE, SYSZ_INS_STOCFHH, SYSZ_INS_STOCFHHE, SYSZ_INS_STOCFHL, SYSZ_INS_STOCFHLE, SYSZ_INS_STOCFHLH, SYSZ_INS_STOCFHM, SYSZ_INS_STOCFHNE, SYSZ_INS_STOCFHNH, SYSZ_INS_STOCFHNHE, SYSZ_INS_STOCFHNL, SYSZ_INS_STOCFHNLE, SYSZ_INS_STOCFHNLH, SYSZ_INS_STOCFHNM, SYSZ_INS_STOCFHNO, SYSZ_INS_STOCFHNP, SYSZ_INS_STOCFHNZ, SYSZ_INS_STOCFHO, SYSZ_INS_STOCFHP, SYSZ_INS_STOCFHZ, SYSZ_INS_STOCGM, SYSZ_INS_STOCGNM, SYSZ_INS_STOCGNP, SYSZ_INS_STOCGNZ, SYSZ_INS_STOCGP, SYSZ_INS_STOCGZ, SYSZ_INS_STOCM, SYSZ_INS_STOCNM, SYSZ_INS_STOCNP, SYSZ_INS_STOCNZ, SYSZ_INS_STOCP, SYSZ_INS_STOCZ, SYSZ_INS_STOSM, SYSZ_INS_STPQ, SYSZ_INS_STPT, SYSZ_INS_STPX, SYSZ_INS_STRAG, SYSZ_INS_STRVH, SYSZ_INS_STSCH, SYSZ_INS_STSI, SYSZ_INS_STURA, SYSZ_INS_STURG, SYSZ_INS_SU, SYSZ_INS_SUR, SYSZ_INS_SVC, SYSZ_INS_SW, SYSZ_INS_SWR, SYSZ_INS_SXR, SYSZ_INS_SXTR, SYSZ_INS_SXTRA, SYSZ_INS_TABORT, SYSZ_INS_TAM, SYSZ_INS_TAR, SYSZ_INS_TB, SYSZ_INS_TBDR, SYSZ_INS_TBEDR, SYSZ_INS_TBEGIN, SYSZ_INS_TBEGINC, SYSZ_INS_TCDB, SYSZ_INS_TCEB, SYSZ_INS_TCXB, SYSZ_INS_TDCDT, SYSZ_INS_TDCET, SYSZ_INS_TDCXT, SYSZ_INS_TDGDT, SYSZ_INS_TDGET, SYSZ_INS_TDGXT, SYSZ_INS_TEND, SYSZ_INS_THDER, SYSZ_INS_THDR, SYSZ_INS_TP, SYSZ_INS_TPI, SYSZ_INS_TPROT, SYSZ_INS_TR, SYSZ_INS_TRACE, SYSZ_INS_TRACG, SYSZ_INS_TRAP2, SYSZ_INS_TRAP4, SYSZ_INS_TRE, SYSZ_INS_TROO, SYSZ_INS_TROT, SYSZ_INS_TRT, SYSZ_INS_TRTE, SYSZ_INS_TRTO, SYSZ_INS_TRTR, SYSZ_INS_TRTRE, SYSZ_INS_TRTT, SYSZ_INS_TS, SYSZ_INS_TSCH, SYSZ_INS_UNPK, SYSZ_INS_UNPKA, SYSZ_INS_UNPKU, SYSZ_INS_UPT, SYSZ_INS_VA, SYSZ_INS_VAB, SYSZ_INS_VAC, SYSZ_INS_VACC, SYSZ_INS_VACCB, SYSZ_INS_VACCC, SYSZ_INS_VACCCQ, SYSZ_INS_VACCF, SYSZ_INS_VACCG, SYSZ_INS_VACCH, SYSZ_INS_VACCQ, SYSZ_INS_VACQ, SYSZ_INS_VAF, SYSZ_INS_VAG, SYSZ_INS_VAH, SYSZ_INS_VAP, SYSZ_INS_VAQ, SYSZ_INS_VAVG, SYSZ_INS_VAVGB, SYSZ_INS_VAVGF, SYSZ_INS_VAVGG, SYSZ_INS_VAVGH, SYSZ_INS_VAVGL, SYSZ_INS_VAVGLB, SYSZ_INS_VAVGLF, SYSZ_INS_VAVGLG, SYSZ_INS_VAVGLH, SYSZ_INS_VBPERM, SYSZ_INS_VCDG, SYSZ_INS_VCDGB, SYSZ_INS_VCDLG, SYSZ_INS_VCDLGB, SYSZ_INS_VCEQ, SYSZ_INS_VCEQB, SYSZ_INS_VCEQBS, SYSZ_INS_VCEQF, SYSZ_INS_VCEQFS, SYSZ_INS_VCEQG, SYSZ_INS_VCEQGS, SYSZ_INS_VCEQH, SYSZ_INS_VCEQHS, SYSZ_INS_VCGD, SYSZ_INS_VCGDB, SYSZ_INS_VCH, SYSZ_INS_VCHB, SYSZ_INS_VCHBS, SYSZ_INS_VCHF, SYSZ_INS_VCHFS, SYSZ_INS_VCHG, SYSZ_INS_VCHGS, SYSZ_INS_VCHH, SYSZ_INS_VCHHS, SYSZ_INS_VCHL, SYSZ_INS_VCHLB, SYSZ_INS_VCHLBS, SYSZ_INS_VCHLF, SYSZ_INS_VCHLFS, SYSZ_INS_VCHLG, SYSZ_INS_VCHLGS, SYSZ_INS_VCHLH, SYSZ_INS_VCHLHS, SYSZ_INS_VCKSM, SYSZ_INS_VCLGD, SYSZ_INS_VCLGDB, SYSZ_INS_VCLZ, SYSZ_INS_VCLZB, SYSZ_INS_VCLZF, SYSZ_INS_VCLZG, SYSZ_INS_VCLZH, SYSZ_INS_VCP, SYSZ_INS_VCTZ, SYSZ_INS_VCTZB, SYSZ_INS_VCTZF, SYSZ_INS_VCTZG, SYSZ_INS_VCTZH, SYSZ_INS_VCVB, SYSZ_INS_VCVBG, SYSZ_INS_VCVD, SYSZ_INS_VCVDG, SYSZ_INS_VDP, SYSZ_INS_VEC, SYSZ_INS_VECB, SYSZ_INS_VECF, SYSZ_INS_VECG, SYSZ_INS_VECH, SYSZ_INS_VECL, SYSZ_INS_VECLB, SYSZ_INS_VECLF, SYSZ_INS_VECLG, SYSZ_INS_VECLH, SYSZ_INS_VERIM, SYSZ_INS_VERIMB, SYSZ_INS_VERIMF, SYSZ_INS_VERIMG, SYSZ_INS_VERIMH, SYSZ_INS_VERLL, SYSZ_INS_VERLLB, SYSZ_INS_VERLLF, SYSZ_INS_VERLLG, SYSZ_INS_VERLLH, SYSZ_INS_VERLLV, SYSZ_INS_VERLLVB, SYSZ_INS_VERLLVF, SYSZ_INS_VERLLVG, SYSZ_INS_VERLLVH, SYSZ_INS_VESL, SYSZ_INS_VESLB, SYSZ_INS_VESLF, SYSZ_INS_VESLG, SYSZ_INS_VESLH, SYSZ_INS_VESLV, SYSZ_INS_VESLVB, SYSZ_INS_VESLVF, SYSZ_INS_VESLVG, SYSZ_INS_VESLVH, SYSZ_INS_VESRA, SYSZ_INS_VESRAB, SYSZ_INS_VESRAF, SYSZ_INS_VESRAG, SYSZ_INS_VESRAH, SYSZ_INS_VESRAV, SYSZ_INS_VESRAVB, SYSZ_INS_VESRAVF, SYSZ_INS_VESRAVG, SYSZ_INS_VESRAVH, SYSZ_INS_VESRL, SYSZ_INS_VESRLB, SYSZ_INS_VESRLF, SYSZ_INS_VESRLG, SYSZ_INS_VESRLH, SYSZ_INS_VESRLV, SYSZ_INS_VESRLVB, SYSZ_INS_VESRLVF, SYSZ_INS_VESRLVG, SYSZ_INS_VESRLVH, SYSZ_INS_VFA, SYSZ_INS_VFADB, SYSZ_INS_VFAE, SYSZ_INS_VFAEB, SYSZ_INS_VFAEBS, SYSZ_INS_VFAEF, SYSZ_INS_VFAEFS, SYSZ_INS_VFAEH, SYSZ_INS_VFAEHS, SYSZ_INS_VFAEZB, SYSZ_INS_VFAEZBS, SYSZ_INS_VFAEZF, SYSZ_INS_VFAEZFS, SYSZ_INS_VFAEZH, SYSZ_INS_VFAEZHS, SYSZ_INS_VFASB, SYSZ_INS_VFCE, SYSZ_INS_VFCEDB, SYSZ_INS_VFCEDBS, SYSZ_INS_VFCESB, SYSZ_INS_VFCESBS, SYSZ_INS_VFCH, SYSZ_INS_VFCHDB, SYSZ_INS_VFCHDBS, SYSZ_INS_VFCHE, SYSZ_INS_VFCHEDB, SYSZ_INS_VFCHEDBS, SYSZ_INS_VFCHESB, SYSZ_INS_VFCHESBS, SYSZ_INS_VFCHSB, SYSZ_INS_VFCHSBS, SYSZ_INS_VFD, SYSZ_INS_VFDDB, SYSZ_INS_VFDSB, SYSZ_INS_VFEE, SYSZ_INS_VFEEB, SYSZ_INS_VFEEBS, SYSZ_INS_VFEEF, SYSZ_INS_VFEEFS, SYSZ_INS_VFEEH, SYSZ_INS_VFEEHS, SYSZ_INS_VFEEZB, SYSZ_INS_VFEEZBS, SYSZ_INS_VFEEZF, SYSZ_INS_VFEEZFS, SYSZ_INS_VFEEZH, SYSZ_INS_VFEEZHS, SYSZ_INS_VFENE, SYSZ_INS_VFENEB, SYSZ_INS_VFENEBS, SYSZ_INS_VFENEF, SYSZ_INS_VFENEFS, SYSZ_INS_VFENEH, SYSZ_INS_VFENEHS, SYSZ_INS_VFENEZB, SYSZ_INS_VFENEZBS, SYSZ_INS_VFENEZF, SYSZ_INS_VFENEZFS, SYSZ_INS_VFENEZH, SYSZ_INS_VFENEZHS, SYSZ_INS_VFI, SYSZ_INS_VFIDB, SYSZ_INS_VFISB, SYSZ_INS_VFKEDB, SYSZ_INS_VFKEDBS, SYSZ_INS_VFKESB, SYSZ_INS_VFKESBS, SYSZ_INS_VFKHDB, SYSZ_INS_VFKHDBS, SYSZ_INS_VFKHEDB, SYSZ_INS_VFKHEDBS, SYSZ_INS_VFKHESB, SYSZ_INS_VFKHESBS, SYSZ_INS_VFKHSB, SYSZ_INS_VFKHSBS, SYSZ_INS_VFLCDB, SYSZ_INS_VFLCSB, SYSZ_INS_VFLL, SYSZ_INS_VFLLS, SYSZ_INS_VFLNDB, SYSZ_INS_VFLNSB, SYSZ_INS_VFLPDB, SYSZ_INS_VFLPSB, SYSZ_INS_VFLR, SYSZ_INS_VFLRD, SYSZ_INS_VFM, SYSZ_INS_VFMA, SYSZ_INS_VFMADB, SYSZ_INS_VFMASB, SYSZ_INS_VFMAX, SYSZ_INS_VFMAXDB, SYSZ_INS_VFMAXSB, SYSZ_INS_VFMDB, SYSZ_INS_VFMIN, SYSZ_INS_VFMINDB, SYSZ_INS_VFMINSB, SYSZ_INS_VFMS, SYSZ_INS_VFMSB, SYSZ_INS_VFMSDB, SYSZ_INS_VFMSSB, SYSZ_INS_VFNMA, SYSZ_INS_VFNMADB, SYSZ_INS_VFNMASB, SYSZ_INS_VFNMS, SYSZ_INS_VFNMSDB, SYSZ_INS_VFNMSSB, SYSZ_INS_VFPSO, SYSZ_INS_VFPSODB, SYSZ_INS_VFPSOSB, SYSZ_INS_VFS, SYSZ_INS_VFSDB, SYSZ_INS_VFSQ, SYSZ_INS_VFSQDB, SYSZ_INS_VFSQSB, SYSZ_INS_VFSSB, SYSZ_INS_VFTCI, SYSZ_INS_VFTCIDB, SYSZ_INS_VFTCISB, SYSZ_INS_VGBM, SYSZ_INS_VGEF, SYSZ_INS_VGEG, SYSZ_INS_VGFM, SYSZ_INS_VGFMA, SYSZ_INS_VGFMAB, SYSZ_INS_VGFMAF, SYSZ_INS_VGFMAG, SYSZ_INS_VGFMAH, SYSZ_INS_VGFMB, SYSZ_INS_VGFMF, SYSZ_INS_VGFMG, SYSZ_INS_VGFMH, SYSZ_INS_VGM, SYSZ_INS_VGMB, SYSZ_INS_VGMF, SYSZ_INS_VGMG, SYSZ_INS_VGMH, SYSZ_INS_VISTR, SYSZ_INS_VISTRB, SYSZ_INS_VISTRBS, SYSZ_INS_VISTRF, SYSZ_INS_VISTRFS, SYSZ_INS_VISTRH, SYSZ_INS_VISTRHS, SYSZ_INS_VL, SYSZ_INS_VLBB, SYSZ_INS_VLC, SYSZ_INS_VLCB, SYSZ_INS_VLCF, SYSZ_INS_VLCG, SYSZ_INS_VLCH, SYSZ_INS_VLDE, SYSZ_INS_VLDEB, SYSZ_INS_VLEB, SYSZ_INS_VLED, SYSZ_INS_VLEDB, SYSZ_INS_VLEF, SYSZ_INS_VLEG, SYSZ_INS_VLEH, SYSZ_INS_VLEIB, SYSZ_INS_VLEIF, SYSZ_INS_VLEIG, SYSZ_INS_VLEIH, SYSZ_INS_VLGV, SYSZ_INS_VLGVB, SYSZ_INS_VLGVF, SYSZ_INS_VLGVG, SYSZ_INS_VLGVH, SYSZ_INS_VLIP, SYSZ_INS_VLL, SYSZ_INS_VLLEZ, SYSZ_INS_VLLEZB, SYSZ_INS_VLLEZF, SYSZ_INS_VLLEZG, SYSZ_INS_VLLEZH, SYSZ_INS_VLLEZLF, SYSZ_INS_VLM, SYSZ_INS_VLP, SYSZ_INS_VLPB, SYSZ_INS_VLPF, SYSZ_INS_VLPG, SYSZ_INS_VLPH, SYSZ_INS_VLR, SYSZ_INS_VLREP, SYSZ_INS_VLREPB, SYSZ_INS_VLREPF, SYSZ_INS_VLREPG, SYSZ_INS_VLREPH, SYSZ_INS_VLRL, SYSZ_INS_VLRLR, SYSZ_INS_VLVG, SYSZ_INS_VLVGB, SYSZ_INS_VLVGF, SYSZ_INS_VLVGG, SYSZ_INS_VLVGH, SYSZ_INS_VLVGP, SYSZ_INS_VMAE, SYSZ_INS_VMAEB, SYSZ_INS_VMAEF, SYSZ_INS_VMAEH, SYSZ_INS_VMAH, SYSZ_INS_VMAHB, SYSZ_INS_VMAHF, SYSZ_INS_VMAHH, SYSZ_INS_VMAL, SYSZ_INS_VMALB, SYSZ_INS_VMALE, SYSZ_INS_VMALEB, SYSZ_INS_VMALEF, SYSZ_INS_VMALEH, SYSZ_INS_VMALF, SYSZ_INS_VMALH, SYSZ_INS_VMALHB, SYSZ_INS_VMALHF, SYSZ_INS_VMALHH, SYSZ_INS_VMALHW, SYSZ_INS_VMALO, SYSZ_INS_VMALOB, SYSZ_INS_VMALOF, SYSZ_INS_VMALOH, SYSZ_INS_VMAO, SYSZ_INS_VMAOB, SYSZ_INS_VMAOF, SYSZ_INS_VMAOH, SYSZ_INS_VME, SYSZ_INS_VMEB, SYSZ_INS_VMEF, SYSZ_INS_VMEH, SYSZ_INS_VMH, SYSZ_INS_VMHB, SYSZ_INS_VMHF, SYSZ_INS_VMHH, SYSZ_INS_VML, SYSZ_INS_VMLB, SYSZ_INS_VMLE, SYSZ_INS_VMLEB, SYSZ_INS_VMLEF, SYSZ_INS_VMLEH, SYSZ_INS_VMLF, SYSZ_INS_VMLH, SYSZ_INS_VMLHB, SYSZ_INS_VMLHF, SYSZ_INS_VMLHH, SYSZ_INS_VMLHW, SYSZ_INS_VMLO, SYSZ_INS_VMLOB, SYSZ_INS_VMLOF, SYSZ_INS_VMLOH, SYSZ_INS_VMN, SYSZ_INS_VMNB, SYSZ_INS_VMNF, SYSZ_INS_VMNG, SYSZ_INS_VMNH, SYSZ_INS_VMNL, SYSZ_INS_VMNLB, SYSZ_INS_VMNLF, SYSZ_INS_VMNLG, SYSZ_INS_VMNLH, SYSZ_INS_VMO, SYSZ_INS_VMOB, SYSZ_INS_VMOF, SYSZ_INS_VMOH, SYSZ_INS_VMP, SYSZ_INS_VMRH, SYSZ_INS_VMRHB, SYSZ_INS_VMRHF, SYSZ_INS_VMRHG, SYSZ_INS_VMRHH, SYSZ_INS_VMRL, SYSZ_INS_VMRLB, SYSZ_INS_VMRLF, SYSZ_INS_VMRLG, SYSZ_INS_VMRLH, SYSZ_INS_VMSL, SYSZ_INS_VMSLG, SYSZ_INS_VMSP, SYSZ_INS_VMX, SYSZ_INS_VMXB, SYSZ_INS_VMXF, SYSZ_INS_VMXG, SYSZ_INS_VMXH, SYSZ_INS_VMXL, SYSZ_INS_VMXLB, SYSZ_INS_VMXLF, SYSZ_INS_VMXLG, SYSZ_INS_VMXLH, SYSZ_INS_VN, SYSZ_INS_VNC, SYSZ_INS_VNN, SYSZ_INS_VNO, SYSZ_INS_VNX, SYSZ_INS_VO, SYSZ_INS_VOC, SYSZ_INS_VONE, SYSZ_INS_VPDI, SYSZ_INS_VPERM, SYSZ_INS_VPK, SYSZ_INS_VPKF, SYSZ_INS_VPKG, SYSZ_INS_VPKH, SYSZ_INS_VPKLS, SYSZ_INS_VPKLSF, SYSZ_INS_VPKLSFS, SYSZ_INS_VPKLSG, SYSZ_INS_VPKLSGS, SYSZ_INS_VPKLSH, SYSZ_INS_VPKLSHS, SYSZ_INS_VPKS, SYSZ_INS_VPKSF, SYSZ_INS_VPKSFS, SYSZ_INS_VPKSG, SYSZ_INS_VPKSGS, SYSZ_INS_VPKSH, SYSZ_INS_VPKSHS, SYSZ_INS_VPKZ, SYSZ_INS_VPOPCT, SYSZ_INS_VPOPCTB, SYSZ_INS_VPOPCTF, SYSZ_INS_VPOPCTG, SYSZ_INS_VPOPCTH, SYSZ_INS_VPSOP, SYSZ_INS_VREP, SYSZ_INS_VREPB, SYSZ_INS_VREPF, SYSZ_INS_VREPG, SYSZ_INS_VREPH, SYSZ_INS_VREPI, SYSZ_INS_VREPIB, SYSZ_INS_VREPIF, SYSZ_INS_VREPIG, SYSZ_INS_VREPIH, SYSZ_INS_VRP, SYSZ_INS_VS, SYSZ_INS_VSB, SYSZ_INS_VSBCBI, SYSZ_INS_VSBCBIQ, SYSZ_INS_VSBI, SYSZ_INS_VSBIQ, SYSZ_INS_VSCBI, SYSZ_INS_VSCBIB, SYSZ_INS_VSCBIF, SYSZ_INS_VSCBIG, SYSZ_INS_VSCBIH, SYSZ_INS_VSCBIQ, SYSZ_INS_VSCEF, SYSZ_INS_VSCEG, SYSZ_INS_VSDP, SYSZ_INS_VSEG, SYSZ_INS_VSEGB, SYSZ_INS_VSEGF, SYSZ_INS_VSEGH, SYSZ_INS_VSEL, SYSZ_INS_VSF, SYSZ_INS_VSG, SYSZ_INS_VSH, SYSZ_INS_VSL, SYSZ_INS_VSLB, SYSZ_INS_VSLDB, SYSZ_INS_VSP, SYSZ_INS_VSQ, SYSZ_INS_VSRA, SYSZ_INS_VSRAB, SYSZ_INS_VSRL, SYSZ_INS_VSRLB, SYSZ_INS_VSRP, SYSZ_INS_VST, SYSZ_INS_VSTEB, SYSZ_INS_VSTEF, SYSZ_INS_VSTEG, SYSZ_INS_VSTEH, SYSZ_INS_VSTL, SYSZ_INS_VSTM, SYSZ_INS_VSTRC, SYSZ_INS_VSTRCB, SYSZ_INS_VSTRCBS, SYSZ_INS_VSTRCF, SYSZ_INS_VSTRCFS, SYSZ_INS_VSTRCH, SYSZ_INS_VSTRCHS, SYSZ_INS_VSTRCZB, SYSZ_INS_VSTRCZBS, SYSZ_INS_VSTRCZF, SYSZ_INS_VSTRCZFS, SYSZ_INS_VSTRCZH, SYSZ_INS_VSTRCZHS, SYSZ_INS_VSTRL, SYSZ_INS_VSTRLR, SYSZ_INS_VSUM, SYSZ_INS_VSUMB, SYSZ_INS_VSUMG, SYSZ_INS_VSUMGF, SYSZ_INS_VSUMGH, SYSZ_INS_VSUMH, SYSZ_INS_VSUMQ, SYSZ_INS_VSUMQF, SYSZ_INS_VSUMQG, SYSZ_INS_VTM, SYSZ_INS_VTP, SYSZ_INS_VUPH, SYSZ_INS_VUPHB, SYSZ_INS_VUPHF, SYSZ_INS_VUPHH, SYSZ_INS_VUPKZ, SYSZ_INS_VUPL, SYSZ_INS_VUPLB, SYSZ_INS_VUPLF, SYSZ_INS_VUPLH, SYSZ_INS_VUPLHB, SYSZ_INS_VUPLHF, SYSZ_INS_VUPLHH, SYSZ_INS_VUPLHW, SYSZ_INS_VUPLL, SYSZ_INS_VUPLLB, SYSZ_INS_VUPLLF, SYSZ_INS_VUPLLH, SYSZ_INS_VX, SYSZ_INS_VZERO, SYSZ_INS_WCDGB, SYSZ_INS_WCDLGB, SYSZ_INS_WCGDB, SYSZ_INS_WCLGDB, SYSZ_INS_WFADB, SYSZ_INS_WFASB, SYSZ_INS_WFAXB, SYSZ_INS_WFC, SYSZ_INS_WFCDB, SYSZ_INS_WFCEDB, SYSZ_INS_WFCEDBS, SYSZ_INS_WFCESB, SYSZ_INS_WFCESBS, SYSZ_INS_WFCEXB, SYSZ_INS_WFCEXBS, SYSZ_INS_WFCHDB, SYSZ_INS_WFCHDBS, SYSZ_INS_WFCHEDB, SYSZ_INS_WFCHEDBS, SYSZ_INS_WFCHESB, SYSZ_INS_WFCHESBS, SYSZ_INS_WFCHEXB, SYSZ_INS_WFCHEXBS, SYSZ_INS_WFCHSB, SYSZ_INS_WFCHSBS, SYSZ_INS_WFCHXB, SYSZ_INS_WFCHXBS, SYSZ_INS_WFCSB, SYSZ_INS_WFCXB, SYSZ_INS_WFDDB, SYSZ_INS_WFDSB, SYSZ_INS_WFDXB, SYSZ_INS_WFIDB, SYSZ_INS_WFISB, SYSZ_INS_WFIXB, SYSZ_INS_WFK, SYSZ_INS_WFKDB, SYSZ_INS_WFKEDB, SYSZ_INS_WFKEDBS, SYSZ_INS_WFKESB, SYSZ_INS_WFKESBS, SYSZ_INS_WFKEXB, SYSZ_INS_WFKEXBS, SYSZ_INS_WFKHDB, SYSZ_INS_WFKHDBS, SYSZ_INS_WFKHEDB, SYSZ_INS_WFKHEDBS, SYSZ_INS_WFKHESB, SYSZ_INS_WFKHESBS, SYSZ_INS_WFKHEXB, SYSZ_INS_WFKHEXBS, SYSZ_INS_WFKHSB, SYSZ_INS_WFKHSBS, SYSZ_INS_WFKHXB, SYSZ_INS_WFKHXBS, SYSZ_INS_WFKSB, SYSZ_INS_WFKXB, SYSZ_INS_WFLCDB, SYSZ_INS_WFLCSB, SYSZ_INS_WFLCXB, SYSZ_INS_WFLLD, SYSZ_INS_WFLLS, SYSZ_INS_WFLNDB, SYSZ_INS_WFLNSB, SYSZ_INS_WFLNXB, SYSZ_INS_WFLPDB, SYSZ_INS_WFLPSB, SYSZ_INS_WFLPXB, SYSZ_INS_WFLRD, SYSZ_INS_WFLRX, SYSZ_INS_WFMADB, SYSZ_INS_WFMASB, SYSZ_INS_WFMAXB, SYSZ_INS_WFMAXDB, SYSZ_INS_WFMAXSB, SYSZ_INS_WFMAXXB, SYSZ_INS_WFMDB, SYSZ_INS_WFMINDB, SYSZ_INS_WFMINSB, SYSZ_INS_WFMINXB, SYSZ_INS_WFMSB, SYSZ_INS_WFMSDB, SYSZ_INS_WFMSSB, SYSZ_INS_WFMSXB, SYSZ_INS_WFMXB, SYSZ_INS_WFNMADB, SYSZ_INS_WFNMASB, SYSZ_INS_WFNMAXB, SYSZ_INS_WFNMSDB, SYSZ_INS_WFNMSSB, SYSZ_INS_WFNMSXB, SYSZ_INS_WFPSODB, SYSZ_INS_WFPSOSB, SYSZ_INS_WFPSOXB, SYSZ_INS_WFSDB, SYSZ_INS_WFSQDB, SYSZ_INS_WFSQSB, SYSZ_INS_WFSQXB, SYSZ_INS_WFSSB, SYSZ_INS_WFSXB, SYSZ_INS_WFTCIDB, SYSZ_INS_WFTCISB, SYSZ_INS_WFTCIXB, SYSZ_INS_WLDEB, SYSZ_INS_WLEDB, SYSZ_INS_XSCH, SYSZ_INS_ZAP, SYSZ_INS_ENDING, // <-- mark the end of the list of instructions } sysz_insn; /// Group of SystemZ instructions typedef enum sysz_insn_group { SYSZ_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) SYSZ_GRP_JUMP, ///< = CS_GRP_JUMP // Architecture-specific groups SYSZ_GRP_DISTINCTOPS = 128, SYSZ_GRP_FPEXTENSION, SYSZ_GRP_HIGHWORD, SYSZ_GRP_INTERLOCKEDACCESS1, SYSZ_GRP_LOADSTOREONCOND, SYSZ_GRP_DFPPACKEDCONVERSION, SYSZ_GRP_DFPZONEDCONVERSION, SYSZ_GRP_ENHANCEDDAT2, SYSZ_GRP_EXECUTIONHINT, SYSZ_GRP_GUARDEDSTORAGE, SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE, SYSZ_GRP_LOADANDTRAP, SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE, SYSZ_GRP_LOADSTOREONCOND2, SYSZ_GRP_MESSAGESECURITYASSIST3, SYSZ_GRP_MESSAGESECURITYASSIST4, SYSZ_GRP_MESSAGESECURITYASSIST5, SYSZ_GRP_MESSAGESECURITYASSIST7, SYSZ_GRP_MESSAGESECURITYASSIST8, SYSZ_GRP_MISCELLANEOUSEXTENSIONS, SYSZ_GRP_MISCELLANEOUSEXTENSIONS2, SYSZ_GRP_NOVECTOR, SYSZ_GRP_POPULATIONCOUNT, SYSZ_GRP_PROCESSORASSIST, SYSZ_GRP_RESETREFERENCEBITSMULTIPLE, SYSZ_GRP_TRANSACTIONALEXECUTION, SYSZ_GRP_VECTOR, SYSZ_GRP_VECTORENHANCEMENTS1, SYSZ_GRP_VECTORPACKEDDECIMAL, SYSZ_GRP_ENDING, // <-- mark the end of the list of groups } sysz_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/tms320c64x.h000064400000000000000000000201060072674642500213470ustar 00000000000000/* Capstone Disassembly Engine */ /* TMS320C64x Backend by Fotis Loukos 2016 */ #ifndef CAPSTONE_TMS320C64X_H #define CAPSTONE_TMS320C64X_H #ifdef __cplusplus extern "C" { #endif #include #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif typedef enum tms320c64x_op_type { TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand). TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand). TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand). TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops } tms320c64x_op_type; typedef enum tms320c64x_mem_disp { TMS320C64X_MEM_DISP_INVALID = 0, TMS320C64X_MEM_DISP_CONSTANT, TMS320C64X_MEM_DISP_REGISTER, } tms320c64x_mem_disp; typedef enum tms320c64x_mem_dir { TMS320C64X_MEM_DIR_INVALID = 0, TMS320C64X_MEM_DIR_FW, TMS320C64X_MEM_DIR_BW, } tms320c64x_mem_dir; typedef enum tms320c64x_mem_mod { TMS320C64X_MEM_MOD_INVALID = 0, TMS320C64X_MEM_MOD_NO, TMS320C64X_MEM_MOD_PRE, TMS320C64X_MEM_MOD_POST, } tms320c64x_mem_mod; typedef struct tms320c64x_op_mem { unsigned int base; ///< base register unsigned int disp; ///< displacement/offset value unsigned int unit; ///< unit of base and offset register unsigned int scaled; ///< offset scaled unsigned int disptype; ///< displacement type unsigned int direction; ///< direction unsigned int modify; ///< modification } tms320c64x_op_mem; typedef struct cs_tms320c64x_op { tms320c64x_op_type type; ///< operand type union { unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand int32_t imm; ///< immediate value for IMM operand tms320c64x_op_mem mem; ///< base/disp value for MEM operand }; } cs_tms320c64x_op; typedef struct cs_tms320c64x { uint8_t op_count; cs_tms320c64x_op operands[8]; ///< operands for this instruction. struct { unsigned int reg; unsigned int zero; } condition; struct { unsigned int unit; unsigned int side; unsigned int crosspath; } funit; unsigned int parallel; } cs_tms320c64x; typedef enum tms320c64x_reg { TMS320C64X_REG_INVALID = 0, TMS320C64X_REG_AMR, TMS320C64X_REG_CSR, TMS320C64X_REG_DIER, TMS320C64X_REG_DNUM, TMS320C64X_REG_ECR, TMS320C64X_REG_GFPGFR, TMS320C64X_REG_GPLYA, TMS320C64X_REG_GPLYB, TMS320C64X_REG_ICR, TMS320C64X_REG_IER, TMS320C64X_REG_IERR, TMS320C64X_REG_ILC, TMS320C64X_REG_IRP, TMS320C64X_REG_ISR, TMS320C64X_REG_ISTP, TMS320C64X_REG_ITSR, TMS320C64X_REG_NRP, TMS320C64X_REG_NTSR, TMS320C64X_REG_REP, TMS320C64X_REG_RILC, TMS320C64X_REG_SSR, TMS320C64X_REG_TSCH, TMS320C64X_REG_TSCL, TMS320C64X_REG_TSR, TMS320C64X_REG_A0, TMS320C64X_REG_A1, TMS320C64X_REG_A2, TMS320C64X_REG_A3, TMS320C64X_REG_A4, TMS320C64X_REG_A5, TMS320C64X_REG_A6, TMS320C64X_REG_A7, TMS320C64X_REG_A8, TMS320C64X_REG_A9, TMS320C64X_REG_A10, TMS320C64X_REG_A11, TMS320C64X_REG_A12, TMS320C64X_REG_A13, TMS320C64X_REG_A14, TMS320C64X_REG_A15, TMS320C64X_REG_A16, TMS320C64X_REG_A17, TMS320C64X_REG_A18, TMS320C64X_REG_A19, TMS320C64X_REG_A20, TMS320C64X_REG_A21, TMS320C64X_REG_A22, TMS320C64X_REG_A23, TMS320C64X_REG_A24, TMS320C64X_REG_A25, TMS320C64X_REG_A26, TMS320C64X_REG_A27, TMS320C64X_REG_A28, TMS320C64X_REG_A29, TMS320C64X_REG_A30, TMS320C64X_REG_A31, TMS320C64X_REG_B0, TMS320C64X_REG_B1, TMS320C64X_REG_B2, TMS320C64X_REG_B3, TMS320C64X_REG_B4, TMS320C64X_REG_B5, TMS320C64X_REG_B6, TMS320C64X_REG_B7, TMS320C64X_REG_B8, TMS320C64X_REG_B9, TMS320C64X_REG_B10, TMS320C64X_REG_B11, TMS320C64X_REG_B12, TMS320C64X_REG_B13, TMS320C64X_REG_B14, TMS320C64X_REG_B15, TMS320C64X_REG_B16, TMS320C64X_REG_B17, TMS320C64X_REG_B18, TMS320C64X_REG_B19, TMS320C64X_REG_B20, TMS320C64X_REG_B21, TMS320C64X_REG_B22, TMS320C64X_REG_B23, TMS320C64X_REG_B24, TMS320C64X_REG_B25, TMS320C64X_REG_B26, TMS320C64X_REG_B27, TMS320C64X_REG_B28, TMS320C64X_REG_B29, TMS320C64X_REG_B30, TMS320C64X_REG_B31, TMS320C64X_REG_PCE1, TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers // Alias registers TMS320C64X_REG_EFR = TMS320C64X_REG_ECR, TMS320C64X_REG_IFR = TMS320C64X_REG_ISR, } tms320c64x_reg; typedef enum tms320c64x_insn { TMS320C64X_INS_INVALID = 0, TMS320C64X_INS_ABS, TMS320C64X_INS_ABS2, TMS320C64X_INS_ADD, TMS320C64X_INS_ADD2, TMS320C64X_INS_ADD4, TMS320C64X_INS_ADDAB, TMS320C64X_INS_ADDAD, TMS320C64X_INS_ADDAH, TMS320C64X_INS_ADDAW, TMS320C64X_INS_ADDK, TMS320C64X_INS_ADDKPC, TMS320C64X_INS_ADDU, TMS320C64X_INS_AND, TMS320C64X_INS_ANDN, TMS320C64X_INS_AVG2, TMS320C64X_INS_AVGU4, TMS320C64X_INS_B, TMS320C64X_INS_BDEC, TMS320C64X_INS_BITC4, TMS320C64X_INS_BNOP, TMS320C64X_INS_BPOS, TMS320C64X_INS_CLR, TMS320C64X_INS_CMPEQ, TMS320C64X_INS_CMPEQ2, TMS320C64X_INS_CMPEQ4, TMS320C64X_INS_CMPGT, TMS320C64X_INS_CMPGT2, TMS320C64X_INS_CMPGTU4, TMS320C64X_INS_CMPLT, TMS320C64X_INS_CMPLTU, TMS320C64X_INS_DEAL, TMS320C64X_INS_DOTP2, TMS320C64X_INS_DOTPN2, TMS320C64X_INS_DOTPNRSU2, TMS320C64X_INS_DOTPRSU2, TMS320C64X_INS_DOTPSU4, TMS320C64X_INS_DOTPU4, TMS320C64X_INS_EXT, TMS320C64X_INS_EXTU, TMS320C64X_INS_GMPGTU, TMS320C64X_INS_GMPY4, TMS320C64X_INS_LDB, TMS320C64X_INS_LDBU, TMS320C64X_INS_LDDW, TMS320C64X_INS_LDH, TMS320C64X_INS_LDHU, TMS320C64X_INS_LDNDW, TMS320C64X_INS_LDNW, TMS320C64X_INS_LDW, TMS320C64X_INS_LMBD, TMS320C64X_INS_MAX2, TMS320C64X_INS_MAXU4, TMS320C64X_INS_MIN2, TMS320C64X_INS_MINU4, TMS320C64X_INS_MPY, TMS320C64X_INS_MPY2, TMS320C64X_INS_MPYH, TMS320C64X_INS_MPYHI, TMS320C64X_INS_MPYHIR, TMS320C64X_INS_MPYHL, TMS320C64X_INS_MPYHLU, TMS320C64X_INS_MPYHSLU, TMS320C64X_INS_MPYHSU, TMS320C64X_INS_MPYHU, TMS320C64X_INS_MPYHULS, TMS320C64X_INS_MPYHUS, TMS320C64X_INS_MPYLH, TMS320C64X_INS_MPYLHU, TMS320C64X_INS_MPYLI, TMS320C64X_INS_MPYLIR, TMS320C64X_INS_MPYLSHU, TMS320C64X_INS_MPYLUHS, TMS320C64X_INS_MPYSU, TMS320C64X_INS_MPYSU4, TMS320C64X_INS_MPYU, TMS320C64X_INS_MPYU4, TMS320C64X_INS_MPYUS, TMS320C64X_INS_MVC, TMS320C64X_INS_MVD, TMS320C64X_INS_MVK, TMS320C64X_INS_MVKL, TMS320C64X_INS_MVKLH, TMS320C64X_INS_NOP, TMS320C64X_INS_NORM, TMS320C64X_INS_OR, TMS320C64X_INS_PACK2, TMS320C64X_INS_PACKH2, TMS320C64X_INS_PACKH4, TMS320C64X_INS_PACKHL2, TMS320C64X_INS_PACKL4, TMS320C64X_INS_PACKLH2, TMS320C64X_INS_ROTL, TMS320C64X_INS_SADD, TMS320C64X_INS_SADD2, TMS320C64X_INS_SADDU4, TMS320C64X_INS_SADDUS2, TMS320C64X_INS_SAT, TMS320C64X_INS_SET, TMS320C64X_INS_SHFL, TMS320C64X_INS_SHL, TMS320C64X_INS_SHLMB, TMS320C64X_INS_SHR, TMS320C64X_INS_SHR2, TMS320C64X_INS_SHRMB, TMS320C64X_INS_SHRU, TMS320C64X_INS_SHRU2, TMS320C64X_INS_SMPY, TMS320C64X_INS_SMPY2, TMS320C64X_INS_SMPYH, TMS320C64X_INS_SMPYHL, TMS320C64X_INS_SMPYLH, TMS320C64X_INS_SPACK2, TMS320C64X_INS_SPACKU4, TMS320C64X_INS_SSHL, TMS320C64X_INS_SSHVL, TMS320C64X_INS_SSHVR, TMS320C64X_INS_SSUB, TMS320C64X_INS_STB, TMS320C64X_INS_STDW, TMS320C64X_INS_STH, TMS320C64X_INS_STNDW, TMS320C64X_INS_STNW, TMS320C64X_INS_STW, TMS320C64X_INS_SUB, TMS320C64X_INS_SUB2, TMS320C64X_INS_SUB4, TMS320C64X_INS_SUBAB, TMS320C64X_INS_SUBABS4, TMS320C64X_INS_SUBAH, TMS320C64X_INS_SUBAW, TMS320C64X_INS_SUBC, TMS320C64X_INS_SUBU, TMS320C64X_INS_SWAP4, TMS320C64X_INS_UNPKHU4, TMS320C64X_INS_UNPKLU4, TMS320C64X_INS_XOR, TMS320C64X_INS_XPND2, TMS320C64X_INS_XPND4, // Aliases TMS320C64X_INS_IDLE, TMS320C64X_INS_MV, TMS320C64X_INS_NEG, TMS320C64X_INS_NOT, TMS320C64X_INS_SWAP2, TMS320C64X_INS_ZERO, TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions } tms320c64x_insn; typedef enum tms320c64x_insn_group { TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP TMS320C64X_GRP_FUNIT_D = 128, TMS320C64X_GRP_FUNIT_L, TMS320C64X_GRP_FUNIT_M, TMS320C64X_GRP_FUNIT_S, TMS320C64X_GRP_FUNIT_NO, TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups } tms320c64x_insn_group; typedef enum tms320c64x_funit { TMS320C64X_FUNIT_INVALID = 0, TMS320C64X_FUNIT_D, TMS320C64X_FUNIT_L, TMS320C64X_FUNIT_M, TMS320C64X_FUNIT_S, TMS320C64X_FUNIT_NO } tms320c64x_funit; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/wasm.h000064400000000000000000000140570072674642500205710ustar 00000000000000/* Capstone Disassembly Engine */ /* By Spike , xwings 2019 */ #ifndef CAPSTONE_WASM_H #define CAPSTONE_WASM_H #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif typedef enum wasm_op_type { WASM_OP_INVALID = 0, WASM_OP_NONE, WASM_OP_INT7, WASM_OP_VARUINT32, WASM_OP_VARUINT64, WASM_OP_UINT32, WASM_OP_UINT64, WASM_OP_IMM, WASM_OP_BRTABLE, } wasm_op_type; typedef struct cs_wasm_brtable { uint32_t length; uint64_t address; uint32_t default_target; } cs_wasm_brtable; typedef struct cs_wasm_op { wasm_op_type type; uint32_t size; union { int8_t int7; uint32_t varuint32; uint64_t varuint64; uint32_t uint32; uint64_t uint64; uint32_t immediate[2]; cs_wasm_brtable brtable; }; } cs_wasm_op; /// Instruction structure typedef struct cs_wasm { uint8_t op_count; cs_wasm_op operands[2]; } cs_wasm; /// WASM instruction typedef enum wasm_insn { WASM_INS_UNREACHABLE = 0x0, WASM_INS_NOP = 0x1, WASM_INS_BLOCK = 0x2, WASM_INS_LOOP = 0x3, WASM_INS_IF = 0x4, WASM_INS_ELSE = 0x5, WASM_INS_END = 0xb, WASM_INS_BR = 0xc, WASM_INS_BR_IF = 0xd, WASM_INS_BR_TABLE = 0xe, WASM_INS_RETURN = 0xf, WASM_INS_CALL = 0x10, WASM_INS_CALL_INDIRECT = 0x11, WASM_INS_DROP = 0x1a, WASM_INS_SELECT = 0x1b, WASM_INS_GET_LOCAL = 0x20, WASM_INS_SET_LOCAL = 0x21, WASM_INS_TEE_LOCAL = 0x22, WASM_INS_GET_GLOBAL = 0x23, WASM_INS_SET_GLOBAL = 0x24, WASM_INS_I32_LOAD = 0x28, WASM_INS_I64_LOAD = 0x29, WASM_INS_F32_LOAD = 0x2a, WASM_INS_F64_LOAD = 0x2b, WASM_INS_I32_LOAD8_S = 0x2c, WASM_INS_I32_LOAD8_U = 0x2d, WASM_INS_I32_LOAD16_S = 0x2e, WASM_INS_I32_LOAD16_U = 0x2f, WASM_INS_I64_LOAD8_S = 0x30, WASM_INS_I64_LOAD8_U = 0x31, WASM_INS_I64_LOAD16_S = 0x32, WASM_INS_I64_LOAD16_U = 0x33, WASM_INS_I64_LOAD32_S = 0x34, WASM_INS_I64_LOAD32_U = 0x35, WASM_INS_I32_STORE = 0x36, WASM_INS_I64_STORE = 0x37, WASM_INS_F32_STORE = 0x38, WASM_INS_F64_STORE = 0x39, WASM_INS_I32_STORE8 = 0x3a, WASM_INS_I32_STORE16 = 0x3b, WASM_INS_I64_STORE8 = 0x3c, WASM_INS_I64_STORE16 = 0x3d, WASM_INS_I64_STORE32 = 0x3e, WASM_INS_CURRENT_MEMORY = 0x3f, WASM_INS_GROW_MEMORY = 0x40, WASM_INS_I32_CONST = 0x41, WASM_INS_I64_CONST = 0x42, WASM_INS_F32_CONST = 0x43, WASM_INS_F64_CONST = 0x44, WASM_INS_I32_EQZ = 0x45, WASM_INS_I32_EQ = 0x46, WASM_INS_I32_NE = 0x47, WASM_INS_I32_LT_S = 0x48, WASM_INS_I32_LT_U = 0x49, WASM_INS_I32_GT_S = 0x4a, WASM_INS_I32_GT_U = 0x4b, WASM_INS_I32_LE_S = 0x4c, WASM_INS_I32_LE_U = 0x4d, WASM_INS_I32_GE_S = 0x4e, WASM_INS_I32_GE_U = 0x4f, WASM_INS_I64_EQZ = 0x50, WASM_INS_I64_EQ = 0x51, WASM_INS_I64_NE = 0x52, WASM_INS_I64_LT_S = 0x53, WASM_INS_I64_LT_U = 0x54, WASN_INS_I64_GT_S = 0x55, WASM_INS_I64_GT_U = 0x56, WASM_INS_I64_LE_S = 0x57, WASM_INS_I64_LE_U = 0x58, WASM_INS_I64_GE_S = 0x59, WASM_INS_I64_GE_U = 0x5a, WASM_INS_F32_EQ = 0x5b, WASM_INS_F32_NE = 0x5c, WASM_INS_F32_LT = 0x5d, WASM_INS_F32_GT = 0x5e, WASM_INS_F32_LE = 0x5f, WASM_INS_F32_GE = 0x60, WASM_INS_F64_EQ = 0x61, WASM_INS_F64_NE = 0x62, WASM_INS_F64_LT = 0x63, WASM_INS_F64_GT = 0x64, WASM_INS_F64_LE = 0x65, WASM_INS_F64_GE = 0x66, WASM_INS_I32_CLZ = 0x67, WASM_INS_I32_CTZ = 0x68, WASM_INS_I32_POPCNT = 0x69, WASM_INS_I32_ADD = 0x6a, WASM_INS_I32_SUB = 0x6b, WASM_INS_I32_MUL = 0x6c, WASM_INS_I32_DIV_S = 0x6d, WASM_INS_I32_DIV_U = 0x6e, WASM_INS_I32_REM_S = 0x6f, WASM_INS_I32_REM_U = 0x70, WASM_INS_I32_AND = 0x71, WASM_INS_I32_OR = 0x72, WASM_INS_I32_XOR = 0x73, WASM_INS_I32_SHL = 0x74, WASM_INS_I32_SHR_S = 0x75, WASM_INS_I32_SHR_U = 0x76, WASM_INS_I32_ROTL = 0x77, WASM_INS_I32_ROTR = 0x78, WASM_INS_I64_CLZ = 0x79, WASM_INS_I64_CTZ = 0x7a, WASM_INS_I64_POPCNT = 0x7b, WASM_INS_I64_ADD = 0x7c, WASM_INS_I64_SUB = 0x7d, WASM_INS_I64_MUL = 0x7e, WASM_INS_I64_DIV_S = 0x7f, WASM_INS_I64_DIV_U = 0x80, WASM_INS_I64_REM_S = 0x81, WASM_INS_I64_REM_U = 0x82, WASM_INS_I64_AND = 0x83, WASM_INS_I64_OR = 0x84, WASM_INS_I64_XOR = 0x85, WASM_INS_I64_SHL = 0x86, WASM_INS_I64_SHR_S = 0x87, WASM_INS_I64_SHR_U = 0x88, WASM_INS_I64_ROTL = 0x89, WASM_INS_I64_ROTR = 0x8a, WASM_INS_F32_ABS = 0x8b, WASM_INS_F32_NEG = 0x8c, WASM_INS_F32_CEIL = 0x8d, WASM_INS_F32_FLOOR = 0x8e, WASM_INS_F32_TRUNC = 0x8f, WASM_INS_F32_NEAREST = 0x90, WASM_INS_F32_SQRT = 0x91, WASM_INS_F32_ADD = 0x92, WASM_INS_F32_SUB = 0x93, WASM_INS_F32_MUL = 0x94, WASM_INS_F32_DIV = 0x95, WASM_INS_F32_MIN = 0x96, WASM_INS_F32_MAX = 0x97, WASM_INS_F32_COPYSIGN = 0x98, WASM_INS_F64_ABS = 0x99, WASM_INS_F64_NEG = 0x9a, WASM_INS_F64_CEIL = 0x9b, WASM_INS_F64_FLOOR = 0x9c, WASM_INS_F64_TRUNC = 0x9d, WASM_INS_F64_NEAREST = 0x9e, WASM_INS_F64_SQRT = 0x9f, WASM_INS_F64_ADD = 0xa0, WASM_INS_F64_SUB = 0xa1, WASM_INS_F64_MUL = 0xa2, WASM_INS_F64_DIV = 0xa3, WASM_INS_F64_MIN = 0xa4, WASM_INS_F64_MAX = 0xa5, WASM_INS_F64_COPYSIGN = 0xa6, WASM_INS_I32_WARP_I64 = 0xa7, WASP_INS_I32_TRUNC_S_F32 = 0xa8, WASM_INS_I32_TRUNC_U_F32 = 0xa9, WASM_INS_I32_TRUNC_S_F64 = 0xaa, WASM_INS_I32_TRUNC_U_F64 = 0xab, WASM_INS_I64_EXTEND_S_I32 = 0xac, WASM_INS_I64_EXTEND_U_I32 = 0xad, WASM_INS_I64_TRUNC_S_F32 = 0xae, WASM_INS_I64_TRUNC_U_F32 = 0xaf, WASM_INS_I64_TRUNC_S_F64 = 0xb0, WASM_INS_I64_TRUNC_U_F64 = 0xb1, WASM_INS_F32_CONVERT_S_I32 = 0xb2, WASM_INS_F32_CONVERT_U_I32 = 0xb3, WASM_INS_F32_CONVERT_S_I64 = 0xb4, WASM_INS_F32_CONVERT_U_I64 = 0xb5, WASM_INS_F32_DEMOTE_F64 = 0xb6, WASM_INS_F64_CONVERT_S_I32 = 0xb7, WASM_INS_F64_CONVERT_U_I32 = 0xb8, WASM_INS_F64_CONVERT_S_I64 = 0xb9, WASM_INS_F64_CONVERT_U_I64 = 0xba, WASM_INS_F64_PROMOTE_F32 = 0xbb, WASM_INS_I32_REINTERPRET_F32 = 0xbc, WASM_INS_I64_REINTERPRET_F64 = 0xbd, WASM_INS_F32_REINTERPRET_I32 = 0xbe, WASM_INS_F64_REINTERPRET_I64 = 0xbf, WASM_INS_INVALID = 512, WASM_INS_ENDING, } wasm_insn; /// Group of WASM instructions typedef enum wasm_insn_group { WASM_GRP_INVALID = 0, ///< = CS_GRP_INVALID WASM_GRP_NUMBERIC = 8, WASM_GRP_PARAMETRIC, WASM_GRP_VARIABLE, WASM_GRP_MEMORY, WASM_GRP_CONTROL, WASM_GRP_ENDING, ///< <-- mark the end of the list of groups } wasm_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/x86.h000064400000000000000000001240570072674642500202510ustar 00000000000000#ifndef CAPSTONE_X86_H #define CAPSTONE_X86_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" /// Calculate relative address for X86-64, given cs_insn structure #define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \ ? (uint64_t)((insn).detail->x86.operands[0].imm) \ : (((insn).address + (insn).size) + (uint64_t)(insn).detail->x86.disp)) /// X86 registers typedef enum x86_reg { X86_REG_INVALID = 0, X86_REG_AH, X86_REG_AL, X86_REG_AX, X86_REG_BH, X86_REG_BL, X86_REG_BP, X86_REG_BPL, X86_REG_BX, X86_REG_CH, X86_REG_CL, X86_REG_CS, X86_REG_CX, X86_REG_DH, X86_REG_DI, X86_REG_DIL, X86_REG_DL, X86_REG_DS, X86_REG_DX, X86_REG_EAX, X86_REG_EBP, X86_REG_EBX, X86_REG_ECX, X86_REG_EDI, X86_REG_EDX, X86_REG_EFLAGS, X86_REG_EIP, X86_REG_EIZ, X86_REG_ES, X86_REG_ESI, X86_REG_ESP, X86_REG_FPSW, X86_REG_FS, X86_REG_GS, X86_REG_IP, X86_REG_RAX, X86_REG_RBP, X86_REG_RBX, X86_REG_RCX, X86_REG_RDI, X86_REG_RDX, X86_REG_RIP, X86_REG_RIZ, X86_REG_RSI, X86_REG_RSP, X86_REG_SI, X86_REG_SIL, X86_REG_SP, X86_REG_SPL, X86_REG_SS, X86_REG_CR0, X86_REG_CR1, X86_REG_CR2, X86_REG_CR3, X86_REG_CR4, X86_REG_CR5, X86_REG_CR6, X86_REG_CR7, X86_REG_CR8, X86_REG_CR9, X86_REG_CR10, X86_REG_CR11, X86_REG_CR12, X86_REG_CR13, X86_REG_CR14, X86_REG_CR15, X86_REG_DR0, X86_REG_DR1, X86_REG_DR2, X86_REG_DR3, X86_REG_DR4, X86_REG_DR5, X86_REG_DR6, X86_REG_DR7, X86_REG_DR8, X86_REG_DR9, X86_REG_DR10, X86_REG_DR11, X86_REG_DR12, X86_REG_DR13, X86_REG_DR14, X86_REG_DR15, X86_REG_FP0, X86_REG_FP1, X86_REG_FP2, X86_REG_FP3, X86_REG_FP4, X86_REG_FP5, X86_REG_FP6, X86_REG_FP7, X86_REG_K0, X86_REG_K1, X86_REG_K2, X86_REG_K3, X86_REG_K4, X86_REG_K5, X86_REG_K6, X86_REG_K7, X86_REG_MM0, X86_REG_MM1, X86_REG_MM2, X86_REG_MM3, X86_REG_MM4, X86_REG_MM5, X86_REG_MM6, X86_REG_MM7, X86_REG_R8, X86_REG_R9, X86_REG_R10, X86_REG_R11, X86_REG_R12, X86_REG_R13, X86_REG_R14, X86_REG_R15, X86_REG_ST0, X86_REG_ST1, X86_REG_ST2, X86_REG_ST3, X86_REG_ST4, X86_REG_ST5, X86_REG_ST6, X86_REG_ST7, X86_REG_XMM0, X86_REG_XMM1, X86_REG_XMM2, X86_REG_XMM3, X86_REG_XMM4, X86_REG_XMM5, X86_REG_XMM6, X86_REG_XMM7, X86_REG_XMM8, X86_REG_XMM9, X86_REG_XMM10, X86_REG_XMM11, X86_REG_XMM12, X86_REG_XMM13, X86_REG_XMM14, X86_REG_XMM15, X86_REG_XMM16, X86_REG_XMM17, X86_REG_XMM18, X86_REG_XMM19, X86_REG_XMM20, X86_REG_XMM21, X86_REG_XMM22, X86_REG_XMM23, X86_REG_XMM24, X86_REG_XMM25, X86_REG_XMM26, X86_REG_XMM27, X86_REG_XMM28, X86_REG_XMM29, X86_REG_XMM30, X86_REG_XMM31, X86_REG_YMM0, X86_REG_YMM1, X86_REG_YMM2, X86_REG_YMM3, X86_REG_YMM4, X86_REG_YMM5, X86_REG_YMM6, X86_REG_YMM7, X86_REG_YMM8, X86_REG_YMM9, X86_REG_YMM10, X86_REG_YMM11, X86_REG_YMM12, X86_REG_YMM13, X86_REG_YMM14, X86_REG_YMM15, X86_REG_YMM16, X86_REG_YMM17, X86_REG_YMM18, X86_REG_YMM19, X86_REG_YMM20, X86_REG_YMM21, X86_REG_YMM22, X86_REG_YMM23, X86_REG_YMM24, X86_REG_YMM25, X86_REG_YMM26, X86_REG_YMM27, X86_REG_YMM28, X86_REG_YMM29, X86_REG_YMM30, X86_REG_YMM31, X86_REG_ZMM0, X86_REG_ZMM1, X86_REG_ZMM2, X86_REG_ZMM3, X86_REG_ZMM4, X86_REG_ZMM5, X86_REG_ZMM6, X86_REG_ZMM7, X86_REG_ZMM8, X86_REG_ZMM9, X86_REG_ZMM10, X86_REG_ZMM11, X86_REG_ZMM12, X86_REG_ZMM13, X86_REG_ZMM14, X86_REG_ZMM15, X86_REG_ZMM16, X86_REG_ZMM17, X86_REG_ZMM18, X86_REG_ZMM19, X86_REG_ZMM20, X86_REG_ZMM21, X86_REG_ZMM22, X86_REG_ZMM23, X86_REG_ZMM24, X86_REG_ZMM25, X86_REG_ZMM26, X86_REG_ZMM27, X86_REG_ZMM28, X86_REG_ZMM29, X86_REG_ZMM30, X86_REG_ZMM31, X86_REG_R8B, X86_REG_R9B, X86_REG_R10B, X86_REG_R11B, X86_REG_R12B, X86_REG_R13B, X86_REG_R14B, X86_REG_R15B, X86_REG_R8D, X86_REG_R9D, X86_REG_R10D, X86_REG_R11D, X86_REG_R12D, X86_REG_R13D, X86_REG_R14D, X86_REG_R15D, X86_REG_R8W, X86_REG_R9W, X86_REG_R10W, X86_REG_R11W, X86_REG_R12W, X86_REG_R13W, X86_REG_R14W, X86_REG_R15W, X86_REG_BND0, X86_REG_BND1, X86_REG_BND2, X86_REG_BND3, X86_REG_ENDING // <-- mark the end of the list of registers } x86_reg; // Sub-flags of EFLAGS #define X86_EFLAGS_MODIFY_AF (1ULL << 0) #define X86_EFLAGS_MODIFY_CF (1ULL << 1) #define X86_EFLAGS_MODIFY_SF (1ULL << 2) #define X86_EFLAGS_MODIFY_ZF (1ULL << 3) #define X86_EFLAGS_MODIFY_PF (1ULL << 4) #define X86_EFLAGS_MODIFY_OF (1ULL << 5) #define X86_EFLAGS_MODIFY_TF (1ULL << 6) #define X86_EFLAGS_MODIFY_IF (1ULL << 7) #define X86_EFLAGS_MODIFY_DF (1ULL << 8) #define X86_EFLAGS_MODIFY_NT (1ULL << 9) #define X86_EFLAGS_MODIFY_RF (1ULL << 10) #define X86_EFLAGS_PRIOR_OF (1ULL << 11) #define X86_EFLAGS_PRIOR_SF (1ULL << 12) #define X86_EFLAGS_PRIOR_ZF (1ULL << 13) #define X86_EFLAGS_PRIOR_AF (1ULL << 14) #define X86_EFLAGS_PRIOR_PF (1ULL << 15) #define X86_EFLAGS_PRIOR_CF (1ULL << 16) #define X86_EFLAGS_PRIOR_TF (1ULL << 17) #define X86_EFLAGS_PRIOR_IF (1ULL << 18) #define X86_EFLAGS_PRIOR_DF (1ULL << 19) #define X86_EFLAGS_PRIOR_NT (1ULL << 20) #define X86_EFLAGS_RESET_OF (1ULL << 21) #define X86_EFLAGS_RESET_CF (1ULL << 22) #define X86_EFLAGS_RESET_DF (1ULL << 23) #define X86_EFLAGS_RESET_IF (1ULL << 24) #define X86_EFLAGS_RESET_SF (1ULL << 25) #define X86_EFLAGS_RESET_AF (1ULL << 26) #define X86_EFLAGS_RESET_TF (1ULL << 27) #define X86_EFLAGS_RESET_NT (1ULL << 28) #define X86_EFLAGS_RESET_PF (1ULL << 29) #define X86_EFLAGS_SET_CF (1ULL << 30) #define X86_EFLAGS_SET_DF (1ULL << 31) #define X86_EFLAGS_SET_IF (1ULL << 32) #define X86_EFLAGS_TEST_OF (1ULL << 33) #define X86_EFLAGS_TEST_SF (1ULL << 34) #define X86_EFLAGS_TEST_ZF (1ULL << 35) #define X86_EFLAGS_TEST_PF (1ULL << 36) #define X86_EFLAGS_TEST_CF (1ULL << 37) #define X86_EFLAGS_TEST_NT (1ULL << 38) #define X86_EFLAGS_TEST_DF (1ULL << 39) #define X86_EFLAGS_UNDEFINED_OF (1ULL << 40) #define X86_EFLAGS_UNDEFINED_SF (1ULL << 41) #define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42) #define X86_EFLAGS_UNDEFINED_PF (1ULL << 43) #define X86_EFLAGS_UNDEFINED_AF (1ULL << 44) #define X86_EFLAGS_UNDEFINED_CF (1ULL << 45) #define X86_EFLAGS_RESET_RF (1ULL << 46) #define X86_EFLAGS_TEST_RF (1ULL << 47) #define X86_EFLAGS_TEST_IF (1ULL << 48) #define X86_EFLAGS_TEST_TF (1ULL << 49) #define X86_EFLAGS_TEST_AF (1ULL << 50) #define X86_EFLAGS_RESET_ZF (1ULL << 51) #define X86_EFLAGS_SET_OF (1ULL << 52) #define X86_EFLAGS_SET_SF (1ULL << 53) #define X86_EFLAGS_SET_ZF (1ULL << 54) #define X86_EFLAGS_SET_AF (1ULL << 55) #define X86_EFLAGS_SET_PF (1ULL << 56) #define X86_EFLAGS_RESET_0F (1ULL << 57) #define X86_EFLAGS_RESET_AC (1ULL << 58) #define X86_FPU_FLAGS_MODIFY_C0 (1ULL << 0) #define X86_FPU_FLAGS_MODIFY_C1 (1ULL << 1) #define X86_FPU_FLAGS_MODIFY_C2 (1ULL << 2) #define X86_FPU_FLAGS_MODIFY_C3 (1ULL << 3) #define X86_FPU_FLAGS_RESET_C0 (1ULL << 4) #define X86_FPU_FLAGS_RESET_C1 (1ULL << 5) #define X86_FPU_FLAGS_RESET_C2 (1ULL << 6) #define X86_FPU_FLAGS_RESET_C3 (1ULL << 7) #define X86_FPU_FLAGS_SET_C0 (1ULL << 8) #define X86_FPU_FLAGS_SET_C1 (1ULL << 9) #define X86_FPU_FLAGS_SET_C2 (1ULL << 10) #define X86_FPU_FLAGS_SET_C3 (1ULL << 11) #define X86_FPU_FLAGS_UNDEFINED_C0 (1ULL << 12) #define X86_FPU_FLAGS_UNDEFINED_C1 (1ULL << 13) #define X86_FPU_FLAGS_UNDEFINED_C2 (1ULL << 14) #define X86_FPU_FLAGS_UNDEFINED_C3 (1ULL << 15) #define X86_FPU_FLAGS_TEST_C0 (1ULL << 16) #define X86_FPU_FLAGS_TEST_C1 (1ULL << 17) #define X86_FPU_FLAGS_TEST_C2 (1ULL << 18) #define X86_FPU_FLAGS_TEST_C3 (1ULL << 19) /// Operand type for instruction's operands typedef enum x86_op_type { X86_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). X86_OP_REG, ///< = CS_OP_REG (Register operand). X86_OP_IMM, ///< = CS_OP_IMM (Immediate operand). X86_OP_MEM, ///< = CS_OP_MEM (Memory operand). } x86_op_type; /// XOP Code Condition type typedef enum x86_xop_cc { X86_XOP_CC_INVALID = 0, ///< Uninitialized. X86_XOP_CC_LT, X86_XOP_CC_LE, X86_XOP_CC_GT, X86_XOP_CC_GE, X86_XOP_CC_EQ, X86_XOP_CC_NEQ, X86_XOP_CC_FALSE, X86_XOP_CC_TRUE, } x86_xop_cc; /// AVX broadcast type typedef enum x86_avx_bcast { X86_AVX_BCAST_INVALID = 0, ///< Uninitialized. X86_AVX_BCAST_2, ///< AVX512 broadcast type {1to2} X86_AVX_BCAST_4, ///< AVX512 broadcast type {1to4} X86_AVX_BCAST_8, ///< AVX512 broadcast type {1to8} X86_AVX_BCAST_16, ///< AVX512 broadcast type {1to16} } x86_avx_bcast; /// SSE Code Condition type typedef enum x86_sse_cc { X86_SSE_CC_INVALID = 0, ///< Uninitialized. X86_SSE_CC_EQ, X86_SSE_CC_LT, X86_SSE_CC_LE, X86_SSE_CC_UNORD, X86_SSE_CC_NEQ, X86_SSE_CC_NLT, X86_SSE_CC_NLE, X86_SSE_CC_ORD, } x86_sse_cc; /// AVX Code Condition type typedef enum x86_avx_cc { X86_AVX_CC_INVALID = 0, ///< Uninitialized. X86_AVX_CC_EQ, X86_AVX_CC_LT, X86_AVX_CC_LE, X86_AVX_CC_UNORD, X86_AVX_CC_NEQ, X86_AVX_CC_NLT, X86_AVX_CC_NLE, X86_AVX_CC_ORD, X86_AVX_CC_EQ_UQ, X86_AVX_CC_NGE, X86_AVX_CC_NGT, X86_AVX_CC_FALSE, X86_AVX_CC_NEQ_OQ, X86_AVX_CC_GE, X86_AVX_CC_GT, X86_AVX_CC_TRUE, X86_AVX_CC_EQ_OS, X86_AVX_CC_LT_OQ, X86_AVX_CC_LE_OQ, X86_AVX_CC_UNORD_S, X86_AVX_CC_NEQ_US, X86_AVX_CC_NLT_UQ, X86_AVX_CC_NLE_UQ, X86_AVX_CC_ORD_S, X86_AVX_CC_EQ_US, X86_AVX_CC_NGE_UQ, X86_AVX_CC_NGT_UQ, X86_AVX_CC_FALSE_OS, X86_AVX_CC_NEQ_OS, X86_AVX_CC_GE_OQ, X86_AVX_CC_GT_OQ, X86_AVX_CC_TRUE_US, } x86_avx_cc; /// AVX static rounding mode type typedef enum x86_avx_rm { X86_AVX_RM_INVALID = 0, ///< Uninitialized. X86_AVX_RM_RN, ///< Round to nearest X86_AVX_RM_RD, ///< Round down X86_AVX_RM_RU, ///< Round up X86_AVX_RM_RZ, ///< Round toward zero } x86_avx_rm; /// Instruction prefixes - to be used in cs_x86.prefix[] typedef enum x86_prefix { X86_PREFIX_LOCK = 0xf0, ///< lock (cs_x86.prefix[0] X86_PREFIX_REP = 0xf3, ///< rep (cs_x86.prefix[0] X86_PREFIX_REPE = 0xf3, ///< repe/repz (cs_x86.prefix[0] X86_PREFIX_REPNE = 0xf2, ///< repne/repnz (cs_x86.prefix[0] X86_PREFIX_CS = 0x2e, ///< segment override CS (cs_x86.prefix[1] X86_PREFIX_SS = 0x36, ///< segment override SS (cs_x86.prefix[1] X86_PREFIX_DS = 0x3e, ///< segment override DS (cs_x86.prefix[1] X86_PREFIX_ES = 0x26, ///< segment override ES (cs_x86.prefix[1] X86_PREFIX_FS = 0x64, ///< segment override FS (cs_x86.prefix[1] X86_PREFIX_GS = 0x65, ///< segment override GS (cs_x86.prefix[1] X86_PREFIX_OPSIZE = 0x66, ///< operand-size override (cs_x86.prefix[2] X86_PREFIX_ADDRSIZE = 0x67, ///< address-size override (cs_x86.prefix[3] } x86_prefix; /// Instruction's operand referring to memory /// This is associated with X86_OP_MEM operand type above typedef struct x86_op_mem { x86_reg segment; ///< segment register (or X86_REG_INVALID if irrelevant) x86_reg base; ///< base register (or X86_REG_INVALID if irrelevant) x86_reg index; ///< index register (or X86_REG_INVALID if irrelevant) int scale; ///< scale for index register int64_t disp; ///< displacement value } x86_op_mem; /// Instruction operand typedef struct cs_x86_op { x86_op_type type; ///< operand type union { x86_reg reg; ///< register value for REG operand int64_t imm; ///< immediate value for IMM operand x86_op_mem mem; ///< base/index/scale/disp value for MEM operand }; /// size of this operand (in bytes). uint8_t size; /// How is this operand accessed? (READ, WRITE or READ|WRITE) /// This field is combined of cs_ac_type. /// NOTE: this field is irrelevant if engine is compiled in DIET mode. uint8_t access; /// AVX broadcast type, or 0 if irrelevant x86_avx_bcast avx_bcast; /// AVX zero opmask {z} bool avx_zero_opmask; } cs_x86_op; typedef struct cs_x86_encoding { /// ModR/M offset, or 0 when irrelevant uint8_t modrm_offset; /// Displacement offset, or 0 when irrelevant. uint8_t disp_offset; uint8_t disp_size; /// Immediate offset, or 0 when irrelevant. uint8_t imm_offset; uint8_t imm_size; } cs_x86_encoding; /// Instruction structure typedef struct cs_x86 { /// Instruction prefix, which can be up to 4 bytes. /// A prefix byte gets value 0 when irrelevant. /// prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above) /// prefix[1] indicates segment override (irrelevant for x86_64): /// See X86_PREFIX_CS/SS/DS/ES/FS/GS above. /// prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE) /// prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) uint8_t prefix[4]; /// Instruction opcode, which can be from 1 to 4 bytes in size. /// This contains VEX opcode as well. /// An trailing opcode byte gets value 0 when irrelevant. uint8_t opcode[4]; /// REX prefix: only a non-zero value is relevant for x86_64 uint8_t rex; /// Address size, which can be overridden with above prefix[5]. uint8_t addr_size; /// ModR/M byte uint8_t modrm; /// SIB value, or 0 when irrelevant. uint8_t sib; /// Displacement value, valid if encoding.disp_offset != 0 int64_t disp; /// SIB index register, or X86_REG_INVALID when irrelevant. x86_reg sib_index; /// SIB scale, only applicable if sib_index is valid. int8_t sib_scale; /// SIB base register, or X86_REG_INVALID when irrelevant. x86_reg sib_base; /// XOP Code Condition x86_xop_cc xop_cc; /// SSE Code Condition x86_sse_cc sse_cc; /// AVX Code Condition x86_avx_cc avx_cc; /// AVX Suppress all Exception bool avx_sae; /// AVX static rounding mode x86_avx_rm avx_rm; union { /// EFLAGS updated by this instruction. /// This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h uint64_t eflags; /// FPU_FLAGS updated by this instruction. /// This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h uint64_t fpu_flags; }; /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_x86_op operands[8]; ///< operands for this instruction. cs_x86_encoding encoding; ///< encoding information } cs_x86; /// X86 instructions typedef enum x86_insn { X86_INS_INVALID = 0, X86_INS_AAA, X86_INS_AAD, X86_INS_AAM, X86_INS_AAS, X86_INS_FABS, X86_INS_ADC, X86_INS_ADCX, X86_INS_ADD, X86_INS_ADDPD, X86_INS_ADDPS, X86_INS_ADDSD, X86_INS_ADDSS, X86_INS_ADDSUBPD, X86_INS_ADDSUBPS, X86_INS_FADD, X86_INS_FIADD, X86_INS_ADOX, X86_INS_AESDECLAST, X86_INS_AESDEC, X86_INS_AESENCLAST, X86_INS_AESENC, X86_INS_AESIMC, X86_INS_AESKEYGENASSIST, X86_INS_AND, X86_INS_ANDN, X86_INS_ANDNPD, X86_INS_ANDNPS, X86_INS_ANDPD, X86_INS_ANDPS, X86_INS_ARPL, X86_INS_BEXTR, X86_INS_BLCFILL, X86_INS_BLCI, X86_INS_BLCIC, X86_INS_BLCMSK, X86_INS_BLCS, X86_INS_BLENDPD, X86_INS_BLENDPS, X86_INS_BLENDVPD, X86_INS_BLENDVPS, X86_INS_BLSFILL, X86_INS_BLSI, X86_INS_BLSIC, X86_INS_BLSMSK, X86_INS_BLSR, X86_INS_BNDCL, X86_INS_BNDCN, X86_INS_BNDCU, X86_INS_BNDLDX, X86_INS_BNDMK, X86_INS_BNDMOV, X86_INS_BNDSTX, X86_INS_BOUND, X86_INS_BSF, X86_INS_BSR, X86_INS_BSWAP, X86_INS_BT, X86_INS_BTC, X86_INS_BTR, X86_INS_BTS, X86_INS_BZHI, X86_INS_CALL, X86_INS_CBW, X86_INS_CDQ, X86_INS_CDQE, X86_INS_FCHS, X86_INS_CLAC, X86_INS_CLC, X86_INS_CLD, X86_INS_CLDEMOTE, X86_INS_CLFLUSH, X86_INS_CLFLUSHOPT, X86_INS_CLGI, X86_INS_CLI, X86_INS_CLRSSBSY, X86_INS_CLTS, X86_INS_CLWB, X86_INS_CLZERO, X86_INS_CMC, X86_INS_CMOVA, X86_INS_CMOVAE, X86_INS_CMOVB, X86_INS_CMOVBE, X86_INS_FCMOVBE, X86_INS_FCMOVB, X86_INS_CMOVE, X86_INS_FCMOVE, X86_INS_CMOVG, X86_INS_CMOVGE, X86_INS_CMOVL, X86_INS_CMOVLE, X86_INS_FCMOVNBE, X86_INS_FCMOVNB, X86_INS_CMOVNE, X86_INS_FCMOVNE, X86_INS_CMOVNO, X86_INS_CMOVNP, X86_INS_FCMOVNU, X86_INS_FCMOVNP, X86_INS_CMOVNS, X86_INS_CMOVO, X86_INS_CMOVP, X86_INS_FCMOVU, X86_INS_CMOVS, X86_INS_CMP, X86_INS_CMPPD, X86_INS_CMPPS, X86_INS_CMPSB, X86_INS_CMPSD, X86_INS_CMPSQ, X86_INS_CMPSS, X86_INS_CMPSW, X86_INS_CMPXCHG16B, X86_INS_CMPXCHG, X86_INS_CMPXCHG8B, X86_INS_COMISD, X86_INS_COMISS, X86_INS_FCOMP, X86_INS_FCOMPI, X86_INS_FCOMI, X86_INS_FCOM, X86_INS_FCOS, X86_INS_CPUID, X86_INS_CQO, X86_INS_CRC32, X86_INS_CVTDQ2PD, X86_INS_CVTDQ2PS, X86_INS_CVTPD2DQ, X86_INS_CVTPD2PS, X86_INS_CVTPS2DQ, X86_INS_CVTPS2PD, X86_INS_CVTSD2SI, X86_INS_CVTSD2SS, X86_INS_CVTSI2SD, X86_INS_CVTSI2SS, X86_INS_CVTSS2SD, X86_INS_CVTSS2SI, X86_INS_CVTTPD2DQ, X86_INS_CVTTPS2DQ, X86_INS_CVTTSD2SI, X86_INS_CVTTSS2SI, X86_INS_CWD, X86_INS_CWDE, X86_INS_DAA, X86_INS_DAS, X86_INS_DATA16, X86_INS_DEC, X86_INS_DIV, X86_INS_DIVPD, X86_INS_DIVPS, X86_INS_FDIVR, X86_INS_FIDIVR, X86_INS_FDIVRP, X86_INS_DIVSD, X86_INS_DIVSS, X86_INS_FDIV, X86_INS_FIDIV, X86_INS_FDIVP, X86_INS_DPPD, X86_INS_DPPS, X86_INS_ENCLS, X86_INS_ENCLU, X86_INS_ENCLV, X86_INS_ENDBR32, X86_INS_ENDBR64, X86_INS_ENTER, X86_INS_EXTRACTPS, X86_INS_EXTRQ, X86_INS_F2XM1, X86_INS_LCALL, X86_INS_LJMP, X86_INS_JMP, X86_INS_FBLD, X86_INS_FBSTP, X86_INS_FCOMPP, X86_INS_FDECSTP, X86_INS_FDISI8087_NOP, X86_INS_FEMMS, X86_INS_FENI8087_NOP, X86_INS_FFREE, X86_INS_FFREEP, X86_INS_FICOM, X86_INS_FICOMP, X86_INS_FINCSTP, X86_INS_FLDCW, X86_INS_FLDENV, X86_INS_FLDL2E, X86_INS_FLDL2T, X86_INS_FLDLG2, X86_INS_FLDLN2, X86_INS_FLDPI, X86_INS_FNCLEX, X86_INS_FNINIT, X86_INS_FNOP, X86_INS_FNSTCW, X86_INS_FNSTSW, X86_INS_FPATAN, X86_INS_FSTPNCE, X86_INS_FPREM, X86_INS_FPREM1, X86_INS_FPTAN, X86_INS_FRNDINT, X86_INS_FRSTOR, X86_INS_FNSAVE, X86_INS_FSCALE, X86_INS_FSETPM, X86_INS_FSINCOS, X86_INS_FNSTENV, X86_INS_FXAM, X86_INS_FXRSTOR, X86_INS_FXRSTOR64, X86_INS_FXSAVE, X86_INS_FXSAVE64, X86_INS_FXTRACT, X86_INS_FYL2X, X86_INS_FYL2XP1, X86_INS_GETSEC, X86_INS_GF2P8AFFINEINVQB, X86_INS_GF2P8AFFINEQB, X86_INS_GF2P8MULB, X86_INS_HADDPD, X86_INS_HADDPS, X86_INS_HLT, X86_INS_HSUBPD, X86_INS_HSUBPS, X86_INS_IDIV, X86_INS_FILD, X86_INS_IMUL, X86_INS_IN, X86_INS_INC, X86_INS_INCSSPD, X86_INS_INCSSPQ, X86_INS_INSB, X86_INS_INSERTPS, X86_INS_INSERTQ, X86_INS_INSD, X86_INS_INSW, X86_INS_INT, X86_INS_INT1, X86_INS_INT3, X86_INS_INTO, X86_INS_INVD, X86_INS_INVEPT, X86_INS_INVLPG, X86_INS_INVLPGA, X86_INS_INVPCID, X86_INS_INVVPID, X86_INS_IRET, X86_INS_IRETD, X86_INS_IRETQ, X86_INS_FISTTP, X86_INS_FIST, X86_INS_FISTP, X86_INS_JAE, X86_INS_JA, X86_INS_JBE, X86_INS_JB, X86_INS_JCXZ, X86_INS_JECXZ, X86_INS_JE, X86_INS_JGE, X86_INS_JG, X86_INS_JLE, X86_INS_JL, X86_INS_JNE, X86_INS_JNO, X86_INS_JNP, X86_INS_JNS, X86_INS_JO, X86_INS_JP, X86_INS_JRCXZ, X86_INS_JS, X86_INS_KADDB, X86_INS_KADDD, X86_INS_KADDQ, X86_INS_KADDW, X86_INS_KANDB, X86_INS_KANDD, X86_INS_KANDNB, X86_INS_KANDND, X86_INS_KANDNQ, X86_INS_KANDNW, X86_INS_KANDQ, X86_INS_KANDW, X86_INS_KMOVB, X86_INS_KMOVD, X86_INS_KMOVQ, X86_INS_KMOVW, X86_INS_KNOTB, X86_INS_KNOTD, X86_INS_KNOTQ, X86_INS_KNOTW, X86_INS_KORB, X86_INS_KORD, X86_INS_KORQ, X86_INS_KORTESTB, X86_INS_KORTESTD, X86_INS_KORTESTQ, X86_INS_KORTESTW, X86_INS_KORW, X86_INS_KSHIFTLB, X86_INS_KSHIFTLD, X86_INS_KSHIFTLQ, X86_INS_KSHIFTLW, X86_INS_KSHIFTRB, X86_INS_KSHIFTRD, X86_INS_KSHIFTRQ, X86_INS_KSHIFTRW, X86_INS_KTESTB, X86_INS_KTESTD, X86_INS_KTESTQ, X86_INS_KTESTW, X86_INS_KUNPCKBW, X86_INS_KUNPCKDQ, X86_INS_KUNPCKWD, X86_INS_KXNORB, X86_INS_KXNORD, X86_INS_KXNORQ, X86_INS_KXNORW, X86_INS_KXORB, X86_INS_KXORD, X86_INS_KXORQ, X86_INS_KXORW, X86_INS_LAHF, X86_INS_LAR, X86_INS_LDDQU, X86_INS_LDMXCSR, X86_INS_LDS, X86_INS_FLDZ, X86_INS_FLD1, X86_INS_FLD, X86_INS_LEA, X86_INS_LEAVE, X86_INS_LES, X86_INS_LFENCE, X86_INS_LFS, X86_INS_LGDT, X86_INS_LGS, X86_INS_LIDT, X86_INS_LLDT, X86_INS_LLWPCB, X86_INS_LMSW, X86_INS_LOCK, X86_INS_LODSB, X86_INS_LODSD, X86_INS_LODSQ, X86_INS_LODSW, X86_INS_LOOP, X86_INS_LOOPE, X86_INS_LOOPNE, X86_INS_RETF, X86_INS_RETFQ, X86_INS_LSL, X86_INS_LSS, X86_INS_LTR, X86_INS_LWPINS, X86_INS_LWPVAL, X86_INS_LZCNT, X86_INS_MASKMOVDQU, X86_INS_MAXPD, X86_INS_MAXPS, X86_INS_MAXSD, X86_INS_MAXSS, X86_INS_MFENCE, X86_INS_MINPD, X86_INS_MINPS, X86_INS_MINSD, X86_INS_MINSS, X86_INS_CVTPD2PI, X86_INS_CVTPI2PD, X86_INS_CVTPI2PS, X86_INS_CVTPS2PI, X86_INS_CVTTPD2PI, X86_INS_CVTTPS2PI, X86_INS_EMMS, X86_INS_MASKMOVQ, X86_INS_MOVD, X86_INS_MOVQ, X86_INS_MOVDQ2Q, X86_INS_MOVNTQ, X86_INS_MOVQ2DQ, X86_INS_PABSB, X86_INS_PABSD, X86_INS_PABSW, X86_INS_PACKSSDW, X86_INS_PACKSSWB, X86_INS_PACKUSWB, X86_INS_PADDB, X86_INS_PADDD, X86_INS_PADDQ, X86_INS_PADDSB, X86_INS_PADDSW, X86_INS_PADDUSB, X86_INS_PADDUSW, X86_INS_PADDW, X86_INS_PALIGNR, X86_INS_PANDN, X86_INS_PAND, X86_INS_PAVGB, X86_INS_PAVGW, X86_INS_PCMPEQB, X86_INS_PCMPEQD, X86_INS_PCMPEQW, X86_INS_PCMPGTB, X86_INS_PCMPGTD, X86_INS_PCMPGTW, X86_INS_PEXTRW, X86_INS_PHADDD, X86_INS_PHADDSW, X86_INS_PHADDW, X86_INS_PHSUBD, X86_INS_PHSUBSW, X86_INS_PHSUBW, X86_INS_PINSRW, X86_INS_PMADDUBSW, X86_INS_PMADDWD, X86_INS_PMAXSW, X86_INS_PMAXUB, X86_INS_PMINSW, X86_INS_PMINUB, X86_INS_PMOVMSKB, X86_INS_PMULHRSW, X86_INS_PMULHUW, X86_INS_PMULHW, X86_INS_PMULLW, X86_INS_PMULUDQ, X86_INS_POR, X86_INS_PSADBW, X86_INS_PSHUFB, X86_INS_PSHUFW, X86_INS_PSIGNB, X86_INS_PSIGND, X86_INS_PSIGNW, X86_INS_PSLLD, X86_INS_PSLLQ, X86_INS_PSLLW, X86_INS_PSRAD, X86_INS_PSRAW, X86_INS_PSRLD, X86_INS_PSRLQ, X86_INS_PSRLW, X86_INS_PSUBB, X86_INS_PSUBD, X86_INS_PSUBQ, X86_INS_PSUBSB, X86_INS_PSUBSW, X86_INS_PSUBUSB, X86_INS_PSUBUSW, X86_INS_PSUBW, X86_INS_PUNPCKHBW, X86_INS_PUNPCKHDQ, X86_INS_PUNPCKHWD, X86_INS_PUNPCKLBW, X86_INS_PUNPCKLDQ, X86_INS_PUNPCKLWD, X86_INS_PXOR, X86_INS_MONITORX, X86_INS_MONITOR, X86_INS_MONTMUL, X86_INS_MOV, X86_INS_MOVABS, X86_INS_MOVAPD, X86_INS_MOVAPS, X86_INS_MOVBE, X86_INS_MOVDDUP, X86_INS_MOVDIR64B, X86_INS_MOVDIRI, X86_INS_MOVDQA, X86_INS_MOVDQU, X86_INS_MOVHLPS, X86_INS_MOVHPD, X86_INS_MOVHPS, X86_INS_MOVLHPS, X86_INS_MOVLPD, X86_INS_MOVLPS, X86_INS_MOVMSKPD, X86_INS_MOVMSKPS, X86_INS_MOVNTDQA, X86_INS_MOVNTDQ, X86_INS_MOVNTI, X86_INS_MOVNTPD, X86_INS_MOVNTPS, X86_INS_MOVNTSD, X86_INS_MOVNTSS, X86_INS_MOVSB, X86_INS_MOVSD, X86_INS_MOVSHDUP, X86_INS_MOVSLDUP, X86_INS_MOVSQ, X86_INS_MOVSS, X86_INS_MOVSW, X86_INS_MOVSX, X86_INS_MOVSXD, X86_INS_MOVUPD, X86_INS_MOVUPS, X86_INS_MOVZX, X86_INS_MPSADBW, X86_INS_MUL, X86_INS_MULPD, X86_INS_MULPS, X86_INS_MULSD, X86_INS_MULSS, X86_INS_MULX, X86_INS_FMUL, X86_INS_FIMUL, X86_INS_FMULP, X86_INS_MWAITX, X86_INS_MWAIT, X86_INS_NEG, X86_INS_NOP, X86_INS_NOT, X86_INS_OR, X86_INS_ORPD, X86_INS_ORPS, X86_INS_OUT, X86_INS_OUTSB, X86_INS_OUTSD, X86_INS_OUTSW, X86_INS_PACKUSDW, X86_INS_PAUSE, X86_INS_PAVGUSB, X86_INS_PBLENDVB, X86_INS_PBLENDW, X86_INS_PCLMULQDQ, X86_INS_PCMPEQQ, X86_INS_PCMPESTRI, X86_INS_PCMPESTRM, X86_INS_PCMPGTQ, X86_INS_PCMPISTRI, X86_INS_PCMPISTRM, X86_INS_PCONFIG, X86_INS_PDEP, X86_INS_PEXT, X86_INS_PEXTRB, X86_INS_PEXTRD, X86_INS_PEXTRQ, X86_INS_PF2ID, X86_INS_PF2IW, X86_INS_PFACC, X86_INS_PFADD, X86_INS_PFCMPEQ, X86_INS_PFCMPGE, X86_INS_PFCMPGT, X86_INS_PFMAX, X86_INS_PFMIN, X86_INS_PFMUL, X86_INS_PFNACC, X86_INS_PFPNACC, X86_INS_PFRCPIT1, X86_INS_PFRCPIT2, X86_INS_PFRCP, X86_INS_PFRSQIT1, X86_INS_PFRSQRT, X86_INS_PFSUBR, X86_INS_PFSUB, X86_INS_PHMINPOSUW, X86_INS_PI2FD, X86_INS_PI2FW, X86_INS_PINSRB, X86_INS_PINSRD, X86_INS_PINSRQ, X86_INS_PMAXSB, X86_INS_PMAXSD, X86_INS_PMAXUD, X86_INS_PMAXUW, X86_INS_PMINSB, X86_INS_PMINSD, X86_INS_PMINUD, X86_INS_PMINUW, X86_INS_PMOVSXBD, X86_INS_PMOVSXBQ, X86_INS_PMOVSXBW, X86_INS_PMOVSXDQ, X86_INS_PMOVSXWD, X86_INS_PMOVSXWQ, X86_INS_PMOVZXBD, X86_INS_PMOVZXBQ, X86_INS_PMOVZXBW, X86_INS_PMOVZXDQ, X86_INS_PMOVZXWD, X86_INS_PMOVZXWQ, X86_INS_PMULDQ, X86_INS_PMULHRW, X86_INS_PMULLD, X86_INS_POP, X86_INS_POPAW, X86_INS_POPAL, X86_INS_POPCNT, X86_INS_POPF, X86_INS_POPFD, X86_INS_POPFQ, X86_INS_PREFETCH, X86_INS_PREFETCHNTA, X86_INS_PREFETCHT0, X86_INS_PREFETCHT1, X86_INS_PREFETCHT2, X86_INS_PREFETCHW, X86_INS_PREFETCHWT1, X86_INS_PSHUFD, X86_INS_PSHUFHW, X86_INS_PSHUFLW, X86_INS_PSLLDQ, X86_INS_PSRLDQ, X86_INS_PSWAPD, X86_INS_PTEST, X86_INS_PTWRITE, X86_INS_PUNPCKHQDQ, X86_INS_PUNPCKLQDQ, X86_INS_PUSH, X86_INS_PUSHAW, X86_INS_PUSHAL, X86_INS_PUSHF, X86_INS_PUSHFD, X86_INS_PUSHFQ, X86_INS_RCL, X86_INS_RCPPS, X86_INS_RCPSS, X86_INS_RCR, X86_INS_RDFSBASE, X86_INS_RDGSBASE, X86_INS_RDMSR, X86_INS_RDPID, X86_INS_RDPKRU, X86_INS_RDPMC, X86_INS_RDRAND, X86_INS_RDSEED, X86_INS_RDSSPD, X86_INS_RDSSPQ, X86_INS_RDTSC, X86_INS_RDTSCP, X86_INS_REPNE, X86_INS_REP, X86_INS_RET, X86_INS_REX64, X86_INS_ROL, X86_INS_ROR, X86_INS_RORX, X86_INS_ROUNDPD, X86_INS_ROUNDPS, X86_INS_ROUNDSD, X86_INS_ROUNDSS, X86_INS_RSM, X86_INS_RSQRTPS, X86_INS_RSQRTSS, X86_INS_RSTORSSP, X86_INS_SAHF, X86_INS_SAL, X86_INS_SALC, X86_INS_SAR, X86_INS_SARX, X86_INS_SAVEPREVSSP, X86_INS_SBB, X86_INS_SCASB, X86_INS_SCASD, X86_INS_SCASQ, X86_INS_SCASW, X86_INS_SETAE, X86_INS_SETA, X86_INS_SETBE, X86_INS_SETB, X86_INS_SETE, X86_INS_SETGE, X86_INS_SETG, X86_INS_SETLE, X86_INS_SETL, X86_INS_SETNE, X86_INS_SETNO, X86_INS_SETNP, X86_INS_SETNS, X86_INS_SETO, X86_INS_SETP, X86_INS_SETSSBSY, X86_INS_SETS, X86_INS_SFENCE, X86_INS_SGDT, X86_INS_SHA1MSG1, X86_INS_SHA1MSG2, X86_INS_SHA1NEXTE, X86_INS_SHA1RNDS4, X86_INS_SHA256MSG1, X86_INS_SHA256MSG2, X86_INS_SHA256RNDS2, X86_INS_SHL, X86_INS_SHLD, X86_INS_SHLX, X86_INS_SHR, X86_INS_SHRD, X86_INS_SHRX, X86_INS_SHUFPD, X86_INS_SHUFPS, X86_INS_SIDT, X86_INS_FSIN, X86_INS_SKINIT, X86_INS_SLDT, X86_INS_SLWPCB, X86_INS_SMSW, X86_INS_SQRTPD, X86_INS_SQRTPS, X86_INS_SQRTSD, X86_INS_SQRTSS, X86_INS_FSQRT, X86_INS_STAC, X86_INS_STC, X86_INS_STD, X86_INS_STGI, X86_INS_STI, X86_INS_STMXCSR, X86_INS_STOSB, X86_INS_STOSD, X86_INS_STOSQ, X86_INS_STOSW, X86_INS_STR, X86_INS_FST, X86_INS_FSTP, X86_INS_SUB, X86_INS_SUBPD, X86_INS_SUBPS, X86_INS_FSUBR, X86_INS_FISUBR, X86_INS_FSUBRP, X86_INS_SUBSD, X86_INS_SUBSS, X86_INS_FSUB, X86_INS_FISUB, X86_INS_FSUBP, X86_INS_SWAPGS, X86_INS_SYSCALL, X86_INS_SYSENTER, X86_INS_SYSEXIT, X86_INS_SYSEXITQ, X86_INS_SYSRET, X86_INS_SYSRETQ, X86_INS_T1MSKC, X86_INS_TEST, X86_INS_TPAUSE, X86_INS_FTST, X86_INS_TZCNT, X86_INS_TZMSK, X86_INS_UCOMISD, X86_INS_UCOMISS, X86_INS_FUCOMPI, X86_INS_FUCOMI, X86_INS_FUCOMPP, X86_INS_FUCOMP, X86_INS_FUCOM, X86_INS_UD0, X86_INS_UD1, X86_INS_UD2, X86_INS_UMONITOR, X86_INS_UMWAIT, X86_INS_UNPCKHPD, X86_INS_UNPCKHPS, X86_INS_UNPCKLPD, X86_INS_UNPCKLPS, X86_INS_V4FMADDPS, X86_INS_V4FMADDSS, X86_INS_V4FNMADDPS, X86_INS_V4FNMADDSS, X86_INS_VADDPD, X86_INS_VADDPS, X86_INS_VADDSD, X86_INS_VADDSS, X86_INS_VADDSUBPD, X86_INS_VADDSUBPS, X86_INS_VAESDECLAST, X86_INS_VAESDEC, X86_INS_VAESENCLAST, X86_INS_VAESENC, X86_INS_VAESIMC, X86_INS_VAESKEYGENASSIST, X86_INS_VALIGND, X86_INS_VALIGNQ, X86_INS_VANDNPD, X86_INS_VANDNPS, X86_INS_VANDPD, X86_INS_VANDPS, X86_INS_VBLENDMPD, X86_INS_VBLENDMPS, X86_INS_VBLENDPD, X86_INS_VBLENDPS, X86_INS_VBLENDVPD, X86_INS_VBLENDVPS, X86_INS_VBROADCASTF128, X86_INS_VBROADCASTF32X2, X86_INS_VBROADCASTF32X4, X86_INS_VBROADCASTF32X8, X86_INS_VBROADCASTF64X2, X86_INS_VBROADCASTF64X4, X86_INS_VBROADCASTI128, X86_INS_VBROADCASTI32X2, X86_INS_VBROADCASTI32X4, X86_INS_VBROADCASTI32X8, X86_INS_VBROADCASTI64X2, X86_INS_VBROADCASTI64X4, X86_INS_VBROADCASTSD, X86_INS_VBROADCASTSS, X86_INS_VCMP, X86_INS_VCMPPD, X86_INS_VCMPPS, X86_INS_VCMPSD, X86_INS_VCMPSS, X86_INS_VCOMISD, X86_INS_VCOMISS, X86_INS_VCOMPRESSPD, X86_INS_VCOMPRESSPS, X86_INS_VCVTDQ2PD, X86_INS_VCVTDQ2PS, X86_INS_VCVTPD2DQ, X86_INS_VCVTPD2PS, X86_INS_VCVTPD2QQ, X86_INS_VCVTPD2UDQ, X86_INS_VCVTPD2UQQ, X86_INS_VCVTPH2PS, X86_INS_VCVTPS2DQ, X86_INS_VCVTPS2PD, X86_INS_VCVTPS2PH, X86_INS_VCVTPS2QQ, X86_INS_VCVTPS2UDQ, X86_INS_VCVTPS2UQQ, X86_INS_VCVTQQ2PD, X86_INS_VCVTQQ2PS, X86_INS_VCVTSD2SI, X86_INS_VCVTSD2SS, X86_INS_VCVTSD2USI, X86_INS_VCVTSI2SD, X86_INS_VCVTSI2SS, X86_INS_VCVTSS2SD, X86_INS_VCVTSS2SI, X86_INS_VCVTSS2USI, X86_INS_VCVTTPD2DQ, X86_INS_VCVTTPD2QQ, X86_INS_VCVTTPD2UDQ, X86_INS_VCVTTPD2UQQ, X86_INS_VCVTTPS2DQ, X86_INS_VCVTTPS2QQ, X86_INS_VCVTTPS2UDQ, X86_INS_VCVTTPS2UQQ, X86_INS_VCVTTSD2SI, X86_INS_VCVTTSD2USI, X86_INS_VCVTTSS2SI, X86_INS_VCVTTSS2USI, X86_INS_VCVTUDQ2PD, X86_INS_VCVTUDQ2PS, X86_INS_VCVTUQQ2PD, X86_INS_VCVTUQQ2PS, X86_INS_VCVTUSI2SD, X86_INS_VCVTUSI2SS, X86_INS_VDBPSADBW, X86_INS_VDIVPD, X86_INS_VDIVPS, X86_INS_VDIVSD, X86_INS_VDIVSS, X86_INS_VDPPD, X86_INS_VDPPS, X86_INS_VERR, X86_INS_VERW, X86_INS_VEXP2PD, X86_INS_VEXP2PS, X86_INS_VEXPANDPD, X86_INS_VEXPANDPS, X86_INS_VEXTRACTF128, X86_INS_VEXTRACTF32X4, X86_INS_VEXTRACTF32X8, X86_INS_VEXTRACTF64X2, X86_INS_VEXTRACTF64X4, X86_INS_VEXTRACTI128, X86_INS_VEXTRACTI32X4, X86_INS_VEXTRACTI32X8, X86_INS_VEXTRACTI64X2, X86_INS_VEXTRACTI64X4, X86_INS_VEXTRACTPS, X86_INS_VFIXUPIMMPD, X86_INS_VFIXUPIMMPS, X86_INS_VFIXUPIMMSD, X86_INS_VFIXUPIMMSS, X86_INS_VFMADD132PD, X86_INS_VFMADD132PS, X86_INS_VFMADD132SD, X86_INS_VFMADD132SS, X86_INS_VFMADD213PD, X86_INS_VFMADD213PS, X86_INS_VFMADD213SD, X86_INS_VFMADD213SS, X86_INS_VFMADD231PD, X86_INS_VFMADD231PS, X86_INS_VFMADD231SD, X86_INS_VFMADD231SS, X86_INS_VFMADDPD, X86_INS_VFMADDPS, X86_INS_VFMADDSD, X86_INS_VFMADDSS, X86_INS_VFMADDSUB132PD, X86_INS_VFMADDSUB132PS, X86_INS_VFMADDSUB213PD, X86_INS_VFMADDSUB213PS, X86_INS_VFMADDSUB231PD, X86_INS_VFMADDSUB231PS, X86_INS_VFMADDSUBPD, X86_INS_VFMADDSUBPS, X86_INS_VFMSUB132PD, X86_INS_VFMSUB132PS, X86_INS_VFMSUB132SD, X86_INS_VFMSUB132SS, X86_INS_VFMSUB213PD, X86_INS_VFMSUB213PS, X86_INS_VFMSUB213SD, X86_INS_VFMSUB213SS, X86_INS_VFMSUB231PD, X86_INS_VFMSUB231PS, X86_INS_VFMSUB231SD, X86_INS_VFMSUB231SS, X86_INS_VFMSUBADD132PD, X86_INS_VFMSUBADD132PS, X86_INS_VFMSUBADD213PD, X86_INS_VFMSUBADD213PS, X86_INS_VFMSUBADD231PD, X86_INS_VFMSUBADD231PS, X86_INS_VFMSUBADDPD, X86_INS_VFMSUBADDPS, X86_INS_VFMSUBPD, X86_INS_VFMSUBPS, X86_INS_VFMSUBSD, X86_INS_VFMSUBSS, X86_INS_VFNMADD132PD, X86_INS_VFNMADD132PS, X86_INS_VFNMADD132SD, X86_INS_VFNMADD132SS, X86_INS_VFNMADD213PD, X86_INS_VFNMADD213PS, X86_INS_VFNMADD213SD, X86_INS_VFNMADD213SS, X86_INS_VFNMADD231PD, X86_INS_VFNMADD231PS, X86_INS_VFNMADD231SD, X86_INS_VFNMADD231SS, X86_INS_VFNMADDPD, X86_INS_VFNMADDPS, X86_INS_VFNMADDSD, X86_INS_VFNMADDSS, X86_INS_VFNMSUB132PD, X86_INS_VFNMSUB132PS, X86_INS_VFNMSUB132SD, X86_INS_VFNMSUB132SS, X86_INS_VFNMSUB213PD, X86_INS_VFNMSUB213PS, X86_INS_VFNMSUB213SD, X86_INS_VFNMSUB213SS, X86_INS_VFNMSUB231PD, X86_INS_VFNMSUB231PS, X86_INS_VFNMSUB231SD, X86_INS_VFNMSUB231SS, X86_INS_VFNMSUBPD, X86_INS_VFNMSUBPS, X86_INS_VFNMSUBSD, X86_INS_VFNMSUBSS, X86_INS_VFPCLASSPD, X86_INS_VFPCLASSPS, X86_INS_VFPCLASSSD, X86_INS_VFPCLASSSS, X86_INS_VFRCZPD, X86_INS_VFRCZPS, X86_INS_VFRCZSD, X86_INS_VFRCZSS, X86_INS_VGATHERDPD, X86_INS_VGATHERDPS, X86_INS_VGATHERPF0DPD, X86_INS_VGATHERPF0DPS, X86_INS_VGATHERPF0QPD, X86_INS_VGATHERPF0QPS, X86_INS_VGATHERPF1DPD, X86_INS_VGATHERPF1DPS, X86_INS_VGATHERPF1QPD, X86_INS_VGATHERPF1QPS, X86_INS_VGATHERQPD, X86_INS_VGATHERQPS, X86_INS_VGETEXPPD, X86_INS_VGETEXPPS, X86_INS_VGETEXPSD, X86_INS_VGETEXPSS, X86_INS_VGETMANTPD, X86_INS_VGETMANTPS, X86_INS_VGETMANTSD, X86_INS_VGETMANTSS, X86_INS_VGF2P8AFFINEINVQB, X86_INS_VGF2P8AFFINEQB, X86_INS_VGF2P8MULB, X86_INS_VHADDPD, X86_INS_VHADDPS, X86_INS_VHSUBPD, X86_INS_VHSUBPS, X86_INS_VINSERTF128, X86_INS_VINSERTF32X4, X86_INS_VINSERTF32X8, X86_INS_VINSERTF64X2, X86_INS_VINSERTF64X4, X86_INS_VINSERTI128, X86_INS_VINSERTI32X4, X86_INS_VINSERTI32X8, X86_INS_VINSERTI64X2, X86_INS_VINSERTI64X4, X86_INS_VINSERTPS, X86_INS_VLDDQU, X86_INS_VLDMXCSR, X86_INS_VMASKMOVDQU, X86_INS_VMASKMOVPD, X86_INS_VMASKMOVPS, X86_INS_VMAXPD, X86_INS_VMAXPS, X86_INS_VMAXSD, X86_INS_VMAXSS, X86_INS_VMCALL, X86_INS_VMCLEAR, X86_INS_VMFUNC, X86_INS_VMINPD, X86_INS_VMINPS, X86_INS_VMINSD, X86_INS_VMINSS, X86_INS_VMLAUNCH, X86_INS_VMLOAD, X86_INS_VMMCALL, X86_INS_VMOVQ, X86_INS_VMOVAPD, X86_INS_VMOVAPS, X86_INS_VMOVDDUP, X86_INS_VMOVD, X86_INS_VMOVDQA32, X86_INS_VMOVDQA64, X86_INS_VMOVDQA, X86_INS_VMOVDQU16, X86_INS_VMOVDQU32, X86_INS_VMOVDQU64, X86_INS_VMOVDQU8, X86_INS_VMOVDQU, X86_INS_VMOVHLPS, X86_INS_VMOVHPD, X86_INS_VMOVHPS, X86_INS_VMOVLHPS, X86_INS_VMOVLPD, X86_INS_VMOVLPS, X86_INS_VMOVMSKPD, X86_INS_VMOVMSKPS, X86_INS_VMOVNTDQA, X86_INS_VMOVNTDQ, X86_INS_VMOVNTPD, X86_INS_VMOVNTPS, X86_INS_VMOVSD, X86_INS_VMOVSHDUP, X86_INS_VMOVSLDUP, X86_INS_VMOVSS, X86_INS_VMOVUPD, X86_INS_VMOVUPS, X86_INS_VMPSADBW, X86_INS_VMPTRLD, X86_INS_VMPTRST, X86_INS_VMREAD, X86_INS_VMRESUME, X86_INS_VMRUN, X86_INS_VMSAVE, X86_INS_VMULPD, X86_INS_VMULPS, X86_INS_VMULSD, X86_INS_VMULSS, X86_INS_VMWRITE, X86_INS_VMXOFF, X86_INS_VMXON, X86_INS_VORPD, X86_INS_VORPS, X86_INS_VP4DPWSSDS, X86_INS_VP4DPWSSD, X86_INS_VPABSB, X86_INS_VPABSD, X86_INS_VPABSQ, X86_INS_VPABSW, X86_INS_VPACKSSDW, X86_INS_VPACKSSWB, X86_INS_VPACKUSDW, X86_INS_VPACKUSWB, X86_INS_VPADDB, X86_INS_VPADDD, X86_INS_VPADDQ, X86_INS_VPADDSB, X86_INS_VPADDSW, X86_INS_VPADDUSB, X86_INS_VPADDUSW, X86_INS_VPADDW, X86_INS_VPALIGNR, X86_INS_VPANDD, X86_INS_VPANDND, X86_INS_VPANDNQ, X86_INS_VPANDN, X86_INS_VPANDQ, X86_INS_VPAND, X86_INS_VPAVGB, X86_INS_VPAVGW, X86_INS_VPBLENDD, X86_INS_VPBLENDMB, X86_INS_VPBLENDMD, X86_INS_VPBLENDMQ, X86_INS_VPBLENDMW, X86_INS_VPBLENDVB, X86_INS_VPBLENDW, X86_INS_VPBROADCASTB, X86_INS_VPBROADCASTD, X86_INS_VPBROADCASTMB2Q, X86_INS_VPBROADCASTMW2D, X86_INS_VPBROADCASTQ, X86_INS_VPBROADCASTW, X86_INS_VPCLMULQDQ, X86_INS_VPCMOV, X86_INS_VPCMP, X86_INS_VPCMPB, X86_INS_VPCMPD, X86_INS_VPCMPEQB, X86_INS_VPCMPEQD, X86_INS_VPCMPEQQ, X86_INS_VPCMPEQW, X86_INS_VPCMPESTRI, X86_INS_VPCMPESTRM, X86_INS_VPCMPGTB, X86_INS_VPCMPGTD, X86_INS_VPCMPGTQ, X86_INS_VPCMPGTW, X86_INS_VPCMPISTRI, X86_INS_VPCMPISTRM, X86_INS_VPCMPQ, X86_INS_VPCMPUB, X86_INS_VPCMPUD, X86_INS_VPCMPUQ, X86_INS_VPCMPUW, X86_INS_VPCMPW, X86_INS_VPCOM, X86_INS_VPCOMB, X86_INS_VPCOMD, X86_INS_VPCOMPRESSB, X86_INS_VPCOMPRESSD, X86_INS_VPCOMPRESSQ, X86_INS_VPCOMPRESSW, X86_INS_VPCOMQ, X86_INS_VPCOMUB, X86_INS_VPCOMUD, X86_INS_VPCOMUQ, X86_INS_VPCOMUW, X86_INS_VPCOMW, X86_INS_VPCONFLICTD, X86_INS_VPCONFLICTQ, X86_INS_VPDPBUSDS, X86_INS_VPDPBUSD, X86_INS_VPDPWSSDS, X86_INS_VPDPWSSD, X86_INS_VPERM2F128, X86_INS_VPERM2I128, X86_INS_VPERMB, X86_INS_VPERMD, X86_INS_VPERMI2B, X86_INS_VPERMI2D, X86_INS_VPERMI2PD, X86_INS_VPERMI2PS, X86_INS_VPERMI2Q, X86_INS_VPERMI2W, X86_INS_VPERMIL2PD, X86_INS_VPERMILPD, X86_INS_VPERMIL2PS, X86_INS_VPERMILPS, X86_INS_VPERMPD, X86_INS_VPERMPS, X86_INS_VPERMQ, X86_INS_VPERMT2B, X86_INS_VPERMT2D, X86_INS_VPERMT2PD, X86_INS_VPERMT2PS, X86_INS_VPERMT2Q, X86_INS_VPERMT2W, X86_INS_VPERMW, X86_INS_VPEXPANDB, X86_INS_VPEXPANDD, X86_INS_VPEXPANDQ, X86_INS_VPEXPANDW, X86_INS_VPEXTRB, X86_INS_VPEXTRD, X86_INS_VPEXTRQ, X86_INS_VPEXTRW, X86_INS_VPGATHERDD, X86_INS_VPGATHERDQ, X86_INS_VPGATHERQD, X86_INS_VPGATHERQQ, X86_INS_VPHADDBD, X86_INS_VPHADDBQ, X86_INS_VPHADDBW, X86_INS_VPHADDDQ, X86_INS_VPHADDD, X86_INS_VPHADDSW, X86_INS_VPHADDUBD, X86_INS_VPHADDUBQ, X86_INS_VPHADDUBW, X86_INS_VPHADDUDQ, X86_INS_VPHADDUWD, X86_INS_VPHADDUWQ, X86_INS_VPHADDWD, X86_INS_VPHADDWQ, X86_INS_VPHADDW, X86_INS_VPHMINPOSUW, X86_INS_VPHSUBBW, X86_INS_VPHSUBDQ, X86_INS_VPHSUBD, X86_INS_VPHSUBSW, X86_INS_VPHSUBWD, X86_INS_VPHSUBW, X86_INS_VPINSRB, X86_INS_VPINSRD, X86_INS_VPINSRQ, X86_INS_VPINSRW, X86_INS_VPLZCNTD, X86_INS_VPLZCNTQ, X86_INS_VPMACSDD, X86_INS_VPMACSDQH, X86_INS_VPMACSDQL, X86_INS_VPMACSSDD, X86_INS_VPMACSSDQH, X86_INS_VPMACSSDQL, X86_INS_VPMACSSWD, X86_INS_VPMACSSWW, X86_INS_VPMACSWD, X86_INS_VPMACSWW, X86_INS_VPMADCSSWD, X86_INS_VPMADCSWD, X86_INS_VPMADD52HUQ, X86_INS_VPMADD52LUQ, X86_INS_VPMADDUBSW, X86_INS_VPMADDWD, X86_INS_VPMASKMOVD, X86_INS_VPMASKMOVQ, X86_INS_VPMAXSB, X86_INS_VPMAXSD, X86_INS_VPMAXSQ, X86_INS_VPMAXSW, X86_INS_VPMAXUB, X86_INS_VPMAXUD, X86_INS_VPMAXUQ, X86_INS_VPMAXUW, X86_INS_VPMINSB, X86_INS_VPMINSD, X86_INS_VPMINSQ, X86_INS_VPMINSW, X86_INS_VPMINUB, X86_INS_VPMINUD, X86_INS_VPMINUQ, X86_INS_VPMINUW, X86_INS_VPMOVB2M, X86_INS_VPMOVD2M, X86_INS_VPMOVDB, X86_INS_VPMOVDW, X86_INS_VPMOVM2B, X86_INS_VPMOVM2D, X86_INS_VPMOVM2Q, X86_INS_VPMOVM2W, X86_INS_VPMOVMSKB, X86_INS_VPMOVQ2M, X86_INS_VPMOVQB, X86_INS_VPMOVQD, X86_INS_VPMOVQW, X86_INS_VPMOVSDB, X86_INS_VPMOVSDW, X86_INS_VPMOVSQB, X86_INS_VPMOVSQD, X86_INS_VPMOVSQW, X86_INS_VPMOVSWB, X86_INS_VPMOVSXBD, X86_INS_VPMOVSXBQ, X86_INS_VPMOVSXBW, X86_INS_VPMOVSXDQ, X86_INS_VPMOVSXWD, X86_INS_VPMOVSXWQ, X86_INS_VPMOVUSDB, X86_INS_VPMOVUSDW, X86_INS_VPMOVUSQB, X86_INS_VPMOVUSQD, X86_INS_VPMOVUSQW, X86_INS_VPMOVUSWB, X86_INS_VPMOVW2M, X86_INS_VPMOVWB, X86_INS_VPMOVZXBD, X86_INS_VPMOVZXBQ, X86_INS_VPMOVZXBW, X86_INS_VPMOVZXDQ, X86_INS_VPMOVZXWD, X86_INS_VPMOVZXWQ, X86_INS_VPMULDQ, X86_INS_VPMULHRSW, X86_INS_VPMULHUW, X86_INS_VPMULHW, X86_INS_VPMULLD, X86_INS_VPMULLQ, X86_INS_VPMULLW, X86_INS_VPMULTISHIFTQB, X86_INS_VPMULUDQ, X86_INS_VPOPCNTB, X86_INS_VPOPCNTD, X86_INS_VPOPCNTQ, X86_INS_VPOPCNTW, X86_INS_VPORD, X86_INS_VPORQ, X86_INS_VPOR, X86_INS_VPPERM, X86_INS_VPROLD, X86_INS_VPROLQ, X86_INS_VPROLVD, X86_INS_VPROLVQ, X86_INS_VPRORD, X86_INS_VPRORQ, X86_INS_VPRORVD, X86_INS_VPRORVQ, X86_INS_VPROTB, X86_INS_VPROTD, X86_INS_VPROTQ, X86_INS_VPROTW, X86_INS_VPSADBW, X86_INS_VPSCATTERDD, X86_INS_VPSCATTERDQ, X86_INS_VPSCATTERQD, X86_INS_VPSCATTERQQ, X86_INS_VPSHAB, X86_INS_VPSHAD, X86_INS_VPSHAQ, X86_INS_VPSHAW, X86_INS_VPSHLB, X86_INS_VPSHLDD, X86_INS_VPSHLDQ, X86_INS_VPSHLDVD, X86_INS_VPSHLDVQ, X86_INS_VPSHLDVW, X86_INS_VPSHLDW, X86_INS_VPSHLD, X86_INS_VPSHLQ, X86_INS_VPSHLW, X86_INS_VPSHRDD, X86_INS_VPSHRDQ, X86_INS_VPSHRDVD, X86_INS_VPSHRDVQ, X86_INS_VPSHRDVW, X86_INS_VPSHRDW, X86_INS_VPSHUFBITQMB, X86_INS_VPSHUFB, X86_INS_VPSHUFD, X86_INS_VPSHUFHW, X86_INS_VPSHUFLW, X86_INS_VPSIGNB, X86_INS_VPSIGND, X86_INS_VPSIGNW, X86_INS_VPSLLDQ, X86_INS_VPSLLD, X86_INS_VPSLLQ, X86_INS_VPSLLVD, X86_INS_VPSLLVQ, X86_INS_VPSLLVW, X86_INS_VPSLLW, X86_INS_VPSRAD, X86_INS_VPSRAQ, X86_INS_VPSRAVD, X86_INS_VPSRAVQ, X86_INS_VPSRAVW, X86_INS_VPSRAW, X86_INS_VPSRLDQ, X86_INS_VPSRLD, X86_INS_VPSRLQ, X86_INS_VPSRLVD, X86_INS_VPSRLVQ, X86_INS_VPSRLVW, X86_INS_VPSRLW, X86_INS_VPSUBB, X86_INS_VPSUBD, X86_INS_VPSUBQ, X86_INS_VPSUBSB, X86_INS_VPSUBSW, X86_INS_VPSUBUSB, X86_INS_VPSUBUSW, X86_INS_VPSUBW, X86_INS_VPTERNLOGD, X86_INS_VPTERNLOGQ, X86_INS_VPTESTMB, X86_INS_VPTESTMD, X86_INS_VPTESTMQ, X86_INS_VPTESTMW, X86_INS_VPTESTNMB, X86_INS_VPTESTNMD, X86_INS_VPTESTNMQ, X86_INS_VPTESTNMW, X86_INS_VPTEST, X86_INS_VPUNPCKHBW, X86_INS_VPUNPCKHDQ, X86_INS_VPUNPCKHQDQ, X86_INS_VPUNPCKHWD, X86_INS_VPUNPCKLBW, X86_INS_VPUNPCKLDQ, X86_INS_VPUNPCKLQDQ, X86_INS_VPUNPCKLWD, X86_INS_VPXORD, X86_INS_VPXORQ, X86_INS_VPXOR, X86_INS_VRANGEPD, X86_INS_VRANGEPS, X86_INS_VRANGESD, X86_INS_VRANGESS, X86_INS_VRCP14PD, X86_INS_VRCP14PS, X86_INS_VRCP14SD, X86_INS_VRCP14SS, X86_INS_VRCP28PD, X86_INS_VRCP28PS, X86_INS_VRCP28SD, X86_INS_VRCP28SS, X86_INS_VRCPPS, X86_INS_VRCPSS, X86_INS_VREDUCEPD, X86_INS_VREDUCEPS, X86_INS_VREDUCESD, X86_INS_VREDUCESS, X86_INS_VRNDSCALEPD, X86_INS_VRNDSCALEPS, X86_INS_VRNDSCALESD, X86_INS_VRNDSCALESS, X86_INS_VROUNDPD, X86_INS_VROUNDPS, X86_INS_VROUNDSD, X86_INS_VROUNDSS, X86_INS_VRSQRT14PD, X86_INS_VRSQRT14PS, X86_INS_VRSQRT14SD, X86_INS_VRSQRT14SS, X86_INS_VRSQRT28PD, X86_INS_VRSQRT28PS, X86_INS_VRSQRT28SD, X86_INS_VRSQRT28SS, X86_INS_VRSQRTPS, X86_INS_VRSQRTSS, X86_INS_VSCALEFPD, X86_INS_VSCALEFPS, X86_INS_VSCALEFSD, X86_INS_VSCALEFSS, X86_INS_VSCATTERDPD, X86_INS_VSCATTERDPS, X86_INS_VSCATTERPF0DPD, X86_INS_VSCATTERPF0DPS, X86_INS_VSCATTERPF0QPD, X86_INS_VSCATTERPF0QPS, X86_INS_VSCATTERPF1DPD, X86_INS_VSCATTERPF1DPS, X86_INS_VSCATTERPF1QPD, X86_INS_VSCATTERPF1QPS, X86_INS_VSCATTERQPD, X86_INS_VSCATTERQPS, X86_INS_VSHUFF32X4, X86_INS_VSHUFF64X2, X86_INS_VSHUFI32X4, X86_INS_VSHUFI64X2, X86_INS_VSHUFPD, X86_INS_VSHUFPS, X86_INS_VSQRTPD, X86_INS_VSQRTPS, X86_INS_VSQRTSD, X86_INS_VSQRTSS, X86_INS_VSTMXCSR, X86_INS_VSUBPD, X86_INS_VSUBPS, X86_INS_VSUBSD, X86_INS_VSUBSS, X86_INS_VTESTPD, X86_INS_VTESTPS, X86_INS_VUCOMISD, X86_INS_VUCOMISS, X86_INS_VUNPCKHPD, X86_INS_VUNPCKHPS, X86_INS_VUNPCKLPD, X86_INS_VUNPCKLPS, X86_INS_VXORPD, X86_INS_VXORPS, X86_INS_VZEROALL, X86_INS_VZEROUPPER, X86_INS_WAIT, X86_INS_WBINVD, X86_INS_WBNOINVD, X86_INS_WRFSBASE, X86_INS_WRGSBASE, X86_INS_WRMSR, X86_INS_WRPKRU, X86_INS_WRSSD, X86_INS_WRSSQ, X86_INS_WRUSSD, X86_INS_WRUSSQ, X86_INS_XABORT, X86_INS_XACQUIRE, X86_INS_XADD, X86_INS_XBEGIN, X86_INS_XCHG, X86_INS_FXCH, X86_INS_XCRYPTCBC, X86_INS_XCRYPTCFB, X86_INS_XCRYPTCTR, X86_INS_XCRYPTECB, X86_INS_XCRYPTOFB, X86_INS_XEND, X86_INS_XGETBV, X86_INS_XLATB, X86_INS_XOR, X86_INS_XORPD, X86_INS_XORPS, X86_INS_XRELEASE, X86_INS_XRSTOR, X86_INS_XRSTOR64, X86_INS_XRSTORS, X86_INS_XRSTORS64, X86_INS_XSAVE, X86_INS_XSAVE64, X86_INS_XSAVEC, X86_INS_XSAVEC64, X86_INS_XSAVEOPT, X86_INS_XSAVEOPT64, X86_INS_XSAVES, X86_INS_XSAVES64, X86_INS_XSETBV, X86_INS_XSHA1, X86_INS_XSHA256, X86_INS_XSTORE, X86_INS_XTEST, X86_INS_ENDING, // mark the end of the list of insn } x86_insn; /// Group of X86 instructions typedef enum x86_insn_group { X86_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) X86_GRP_JUMP, ///< = CS_GRP_JUMP // all call instructions X86_GRP_CALL, ///< = CS_GRP_CALL // all return instructions X86_GRP_RET, ///< = CS_GRP_RET // all interrupt instructions (int+syscall) X86_GRP_INT, ///< = CS_GRP_INT // all interrupt return instructions X86_GRP_IRET, ///< = CS_GRP_IRET // all privileged instructions X86_GRP_PRIVILEGE, ///< = CS_GRP_PRIVILEGE // all relative branching instructions X86_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE // Architecture-specific groups X86_GRP_VM = 128, ///< all virtualization instructions (VT-x + AMD-V) X86_GRP_3DNOW, X86_GRP_AES, X86_GRP_ADX, X86_GRP_AVX, X86_GRP_AVX2, X86_GRP_AVX512, X86_GRP_BMI, X86_GRP_BMI2, X86_GRP_CMOV, X86_GRP_F16C, X86_GRP_FMA, X86_GRP_FMA4, X86_GRP_FSGSBASE, X86_GRP_HLE, X86_GRP_MMX, X86_GRP_MODE32, X86_GRP_MODE64, X86_GRP_RTM, X86_GRP_SHA, X86_GRP_SSE1, X86_GRP_SSE2, X86_GRP_SSE3, X86_GRP_SSE41, X86_GRP_SSE42, X86_GRP_SSE4A, X86_GRP_SSSE3, X86_GRP_PCLMUL, X86_GRP_XOP, X86_GRP_CDI, X86_GRP_ERI, X86_GRP_TBM, X86_GRP_16BITMODE, X86_GRP_NOT64BITMODE, X86_GRP_SGX, X86_GRP_DQI, X86_GRP_BWI, X86_GRP_PFI, X86_GRP_VLX, X86_GRP_SMAP, X86_GRP_NOVLX, X86_GRP_FPU, X86_GRP_ENDING } x86_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/capstone/xcore.h000064400000000000000000000114670072674642500207440ustar 00000000000000#ifndef CAPSTONE_XCORE_H #define CAPSTONE_XCORE_H /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2014-2015 */ #ifdef __cplusplus extern "C" { #endif #include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) #endif /// Operand type for instruction's operands typedef enum xcore_op_type { XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). XCORE_OP_REG, ///< = CS_OP_REG (Register operand). XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand). XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand). } xcore_op_type; /// XCore registers typedef enum xcore_reg { XCORE_REG_INVALID = 0, XCORE_REG_CP, XCORE_REG_DP, XCORE_REG_LR, XCORE_REG_SP, XCORE_REG_R0, XCORE_REG_R1, XCORE_REG_R2, XCORE_REG_R3, XCORE_REG_R4, XCORE_REG_R5, XCORE_REG_R6, XCORE_REG_R7, XCORE_REG_R8, XCORE_REG_R9, XCORE_REG_R10, XCORE_REG_R11, // pseudo registers XCORE_REG_PC, ///< pc // internal thread registers // see The-XMOS-XS1-Architecture(X7879A).pdf XCORE_REG_SCP, ///< save pc XCORE_REG_SSR, //< save status XCORE_REG_ET, //< exception type XCORE_REG_ED, //< exception data XCORE_REG_SED, //< save exception data XCORE_REG_KEP, //< kernel entry pointer XCORE_REG_KSP, //< kernel stack pointer XCORE_REG_ID, //< thread ID XCORE_REG_ENDING, // <-- mark the end of the list of registers } xcore_reg; /// Instruction's operand referring to memory /// This is associated with XCORE_OP_MEM operand type above typedef struct xcore_op_mem { uint8_t base; ///< base register, can be safely interpreted as ///< a value of type `xcore_reg`, but it is only ///< one byte wide uint8_t index; ///< index register, same conditions apply here int32_t disp; ///< displacement/offset value int direct; ///< +1: forward, -1: backward } xcore_op_mem; /// Instruction operand typedef struct cs_xcore_op { xcore_op_type type; ///< operand type union { xcore_reg reg; ///< register value for REG operand int32_t imm; ///< immediate value for IMM operand xcore_op_mem mem; ///< base/disp value for MEM operand }; } cs_xcore_op; /// Instruction structure typedef struct cs_xcore { /// Number of operands of this instruction, /// or 0 when instruction has no operand. uint8_t op_count; cs_xcore_op operands[8]; ///< operands for this instruction. } cs_xcore; /// XCore instruction typedef enum xcore_insn { XCORE_INS_INVALID = 0, XCORE_INS_ADD, XCORE_INS_ANDNOT, XCORE_INS_AND, XCORE_INS_ASHR, XCORE_INS_BAU, XCORE_INS_BITREV, XCORE_INS_BLA, XCORE_INS_BLAT, XCORE_INS_BL, XCORE_INS_BF, XCORE_INS_BT, XCORE_INS_BU, XCORE_INS_BRU, XCORE_INS_BYTEREV, XCORE_INS_CHKCT, XCORE_INS_CLRE, XCORE_INS_CLRPT, XCORE_INS_CLRSR, XCORE_INS_CLZ, XCORE_INS_CRC8, XCORE_INS_CRC32, XCORE_INS_DCALL, XCORE_INS_DENTSP, XCORE_INS_DGETREG, XCORE_INS_DIVS, XCORE_INS_DIVU, XCORE_INS_DRESTSP, XCORE_INS_DRET, XCORE_INS_ECALLF, XCORE_INS_ECALLT, XCORE_INS_EDU, XCORE_INS_EEF, XCORE_INS_EET, XCORE_INS_EEU, XCORE_INS_ENDIN, XCORE_INS_ENTSP, XCORE_INS_EQ, XCORE_INS_EXTDP, XCORE_INS_EXTSP, XCORE_INS_FREER, XCORE_INS_FREET, XCORE_INS_GETD, XCORE_INS_GET, XCORE_INS_GETN, XCORE_INS_GETR, XCORE_INS_GETSR, XCORE_INS_GETST, XCORE_INS_GETTS, XCORE_INS_INCT, XCORE_INS_INIT, XCORE_INS_INPW, XCORE_INS_INSHR, XCORE_INS_INT, XCORE_INS_IN, XCORE_INS_KCALL, XCORE_INS_KENTSP, XCORE_INS_KRESTSP, XCORE_INS_KRET, XCORE_INS_LADD, XCORE_INS_LD16S, XCORE_INS_LD8U, XCORE_INS_LDA16, XCORE_INS_LDAP, XCORE_INS_LDAW, XCORE_INS_LDC, XCORE_INS_LDW, XCORE_INS_LDIVU, XCORE_INS_LMUL, XCORE_INS_LSS, XCORE_INS_LSUB, XCORE_INS_LSU, XCORE_INS_MACCS, XCORE_INS_MACCU, XCORE_INS_MJOIN, XCORE_INS_MKMSK, XCORE_INS_MSYNC, XCORE_INS_MUL, XCORE_INS_NEG, XCORE_INS_NOT, XCORE_INS_OR, XCORE_INS_OUTCT, XCORE_INS_OUTPW, XCORE_INS_OUTSHR, XCORE_INS_OUTT, XCORE_INS_OUT, XCORE_INS_PEEK, XCORE_INS_REMS, XCORE_INS_REMU, XCORE_INS_RETSP, XCORE_INS_SETCLK, XCORE_INS_SET, XCORE_INS_SETC, XCORE_INS_SETD, XCORE_INS_SETEV, XCORE_INS_SETN, XCORE_INS_SETPSC, XCORE_INS_SETPT, XCORE_INS_SETRDY, XCORE_INS_SETSR, XCORE_INS_SETTW, XCORE_INS_SETV, XCORE_INS_SEXT, XCORE_INS_SHL, XCORE_INS_SHR, XCORE_INS_SSYNC, XCORE_INS_ST16, XCORE_INS_ST8, XCORE_INS_STW, XCORE_INS_SUB, XCORE_INS_SYNCR, XCORE_INS_TESTCT, XCORE_INS_TESTLCL, XCORE_INS_TESTWCT, XCORE_INS_TSETMR, XCORE_INS_START, XCORE_INS_WAITEF, XCORE_INS_WAITET, XCORE_INS_WAITEU, XCORE_INS_XOR, XCORE_INS_ZEXT, XCORE_INS_ENDING, // <-- mark the end of the list of instructions } xcore_insn; /// Group of XCore instructions typedef enum xcore_insn_group { XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID // Generic groups // all jump instructions (conditional+direct+indirect jumps) XCORE_GRP_JUMP, ///< = CS_GRP_JUMP XCORE_GRP_ENDING, // <-- mark the end of the list of groups } xcore_insn_group; #ifdef __cplusplus } #endif #endif capstone-sys-0.15.0/capstone/include/platform.h000064400000000000000000000062140072674642500176260ustar 00000000000000/* Capstone Disassembly Engine */ /* By Axel Souchet & Nguyen Anh Quynh, 2014 */ #ifndef CAPSTONE_PLATFORM_H #define CAPSTONE_PLATFORM_H // handle C99 issue (for pre-2013 VisualStudio) #if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)) // MSVC // stdbool.h #if (_MSC_VER < 1800) || defined(_KERNEL_MODE) // this system does not have stdbool.h #ifndef __cplusplus typedef unsigned char bool; #define false 0 #define true 1 #endif #else // VisualStudio 2013+ -> C99 is supported #include #endif #else // not MSVC -> C99 is supported #include #endif // handle C99 issue (for pre-2013 VisualStudio) #if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE))) // this system does not have inttypes.h #if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE)) // this system does not have stdint.h typedef signed char int8_t; typedef signed short int16_t; typedef signed int int32_t; typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; #define INT8_MIN (-127i8 - 1) #define INT16_MIN (-32767i16 - 1) #define INT32_MIN (-2147483647i32 - 1) #define INT64_MIN (-9223372036854775807i64 - 1) #define INT8_MAX 127i8 #define INT16_MAX 32767i16 #define INT32_MAX 2147483647i32 #define INT64_MAX 9223372036854775807i64 #define UINT8_MAX 0xffui8 #define UINT16_MAX 0xffffui16 #define UINT32_MAX 0xffffffffui32 #define UINT64_MAX 0xffffffffffffffffui64 #endif #define __PRI_8_LENGTH_MODIFIER__ "hh" #define __PRI_64_LENGTH_MODIFIER__ "ll" #define PRId8 __PRI_8_LENGTH_MODIFIER__ "d" #define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i" #define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o" #define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u" #define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x" #define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X" #define PRId16 "hd" #define PRIi16 "hi" #define PRIo16 "ho" #define PRIu16 "hu" #define PRIx16 "hx" #define PRIX16 "hX" #if defined(_MSC_VER) && _MSC_VER <= 1700 #define PRId32 "ld" #define PRIi32 "li" #define PRIo32 "lo" #define PRIu32 "lu" #define PRIx32 "lx" #define PRIX32 "lX" #else // OSX #define PRId32 "d" #define PRIi32 "i" #define PRIo32 "o" #define PRIu32 "u" #define PRIx32 "x" #define PRIX32 "X" #endif #if defined(_MSC_VER) && _MSC_VER <= 1700 // redefine functions from inttypes.h used in cstool #define strtoull _strtoui64 #endif #define PRId64 __PRI_64_LENGTH_MODIFIER__ "d" #define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i" #define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o" #define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u" #define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x" #define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X" #else // this system has inttypes.h by default #include #endif #endif capstone-sys-0.15.0/capstone/include/windowsce/intrin.h000064400000000000000000000004730072674642500213100ustar 00000000000000 #if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(__INTRIN_H_) && !defined(_INTRIN) #define _STDINT #ifdef _M_ARM #include #if (_WIN32_WCE >= 0x700) && defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) #include #endif #endif // _M_ARM #endif capstone-sys-0.15.0/capstone/include/windowsce/stdint.h000064400000000000000000000057140072674642500213150ustar 00000000000000 #if defined(_MSC_VER) && defined(_WIN32_WCE) && (_WIN32_WCE < 0x800) && !defined(_STDINT_H_) && !defined(_STDINT) #define _STDINT typedef __int8 int8_t, int_least8_t; typedef __int16 int16_t, int_least16_t; typedef __int32 int32_t, int_least32_t, int_fast8_t, int_fast16_t, int_fast32_t; typedef __int64 int64_t, intmax_t, int_least64_t, int_fast64_t; typedef unsigned __int8 uint8_t, uint_least8_t; typedef unsigned __int16 uint16_t, uint_least16_t; typedef unsigned __int32 uint32_t, uint_least32_t, uint_fast8_t, uint_fast16_t, uint_fast32_t; typedef unsigned __int64 uint64_t, uintmax_t, uint_least64_t, uint_fast64_t; #ifndef _INTPTR_T_DEFINED #define _INTPTR_T_DEFINED typedef __int32 intptr_t; #endif #ifndef _UINTPTR_T_DEFINED #define _UINTPTR_T_DEFINED typedef unsigned __int32 uintptr_t; #endif #define INT8_MIN (-127i8 - 1) #define INT16_MIN (-32767i16 - 1) #define INT32_MIN (-2147483647i32 - 1) #define INT64_MIN (-9223372036854775807i64 - 1) #define INT8_MAX 127i8 #define INT16_MAX 32767i16 #define INT32_MAX 2147483647i32 #define INT64_MAX 9223372036854775807i64 #define UINT8_MAX 0xffui8 #define UINT16_MAX 0xffffui16 #define UINT32_MAX 0xffffffffui32 #define UINT64_MAX 0xffffffffffffffffui64 #define INT_LEAST8_MIN INT8_MIN #define INT_LEAST16_MIN INT16_MIN #define INT_LEAST32_MIN INT32_MIN #define INT_LEAST64_MIN INT64_MIN #define INT_LEAST8_MAX INT8_MAX #define INT_LEAST16_MAX INT16_MAX #define INT_LEAST32_MAX INT32_MAX #define INT_LEAST64_MAX INT64_MAX #define UINT_LEAST8_MAX UINT8_MAX #define UINT_LEAST16_MAX UINT16_MAX #define UINT_LEAST32_MAX UINT32_MAX #define UINT_LEAST64_MAX UINT64_MAX #define INT_FAST8_MIN INT8_MIN #define INT_FAST16_MIN INT32_MIN #define INT_FAST32_MIN INT32_MIN #define INT_FAST64_MIN INT64_MIN #define INT_FAST8_MAX INT8_MAX #define INT_FAST16_MAX INT32_MAX #define INT_FAST32_MAX INT32_MAX #define INT_FAST64_MAX INT64_MAX #define UINT_FAST8_MAX UINT8_MAX #define UINT_FAST16_MAX UINT32_MAX #define UINT_FAST32_MAX UINT32_MAX #define UINT_FAST64_MAX UINT64_MAX #define INTPTR_MIN INT32_MIN #define INTPTR_MAX INT32_MAX #define UINTPTR_MAX UINT32_MAX #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX #define PTRDIFF_MIN INTPTR_MIN #define PTRDIFF_MAX INTPTR_MAX #ifndef SIZE_MAX #define SIZE_MAX UINTPTR_MAX #endif #define SIG_ATOMIC_MIN INT32_MIN #define SIG_ATOMIC_MAX INT32_MAX #define WCHAR_MIN 0x0000 #define WCHAR_MAX 0xffff #define WINT_MIN 0x0000 #define WINT_MAX 0xffff #define INT8_C(x) (x) #define INT16_C(x) (x) #define INT32_C(x) (x) #define INT64_C(x) (x ## LL) #define UINT8_C(x) (x) #define UINT16_C(x) (x) #define UINT32_C(x) (x ## U) #define UINT64_C(x) (x ## ULL) #define INTMAX_C(x) INT64_C(x) #define UINTMAX_C(x) UINT64_C(x) #endif capstone-sys-0.15.0/capstone/make.sh000075500000000000000000000106250072674642500154630ustar 00000000000000#!/bin/sh # Capstone Disassembly Engine # By Nguyen Anh Quynh , 2013-2019 # Note: to cross-compile "nix32" on Linux, package gcc-multilib is required. MAKE_JOBS=${MAKE_JOBS:-4} # build Android lib for only one supported architecture build_android() { if [ -z "$NDK" ]; then echo "ERROR! Please set \$NDK to point at your Android NDK directory." exit 1 fi HOSTOS=$(uname -s | tr 'LD' 'ld') HOSTARCH=$(uname -m) TARGARCH="$1" shift case "$TARGARCH" in arm) [ -n "$APILEVEL" ] || APILEVEL="android-14" # default to ICS CROSS=arm-linux-androideabi ;; arm64) [ -n "$APILEVEL" ] || APILEVEL="android-21" # first with arm64 CROSS=aarch64-linux-android ;; *) echo "ERROR! Building for Android on $1 is not currently supported." exit 1 ;; esac STANDALONE=`realpath android-ndk-${TARGARCH}-${APILEVEL}` [ -d $STANDALONE ] || { python ${NDK}/build/tools/make_standalone_toolchain.py \ --arch ${TARGARCH} \ --api ${APILEVEL##*-} \ --install-dir ${STANDALONE} } ANDROID=1 CROSS="${STANDALONE}/${CROSS}/bin" CFLAGS="--sysroot=${STANDALONE}/sysroot" ${MAKE} $* } # build iOS lib for all iDevices, or only specific device build_iOS() { IOS_SDK=`xcrun --sdk iphoneos --show-sdk-path` IOS_CC=`xcrun --sdk iphoneos -f clang` IOS_CFLAGS="-Os -Wimplicit -isysroot $IOS_SDK" IOS_LDFLAGS="-isysroot $IOS_SDK" if [ -z "$1" ]; then # build for all iDevices IOS_ARCHS="armv7 armv7s arm64" else IOS_ARCHS="$1" fi export CC="$IOS_CC" export LIBARCHS="$IOS_ARCHS" CFLAGS="$IOS_CFLAGS" LDFLAGS="$IOS_LDFLAGS" MACOS_UNIVERSAL=yes ${MAKE} } install() { # Mac OSX needs to find the right directory for pkgconfig if [ "$UNAME" = Darwin ]; then # we are going to install into /usr/local, so remove old installs under /usr rm -rf /usr/lib/libcapstone.* rm -rf /usr/include/capstone if [ "${HOMEBREW_CAPSTONE}" != 1 ]; then # find the directory automatically, so we can support both Macport & Brew export PKGCFGDIR="$(pkg-config --variable pc_path pkg-config | cut -d ':' -f 1)" fi ${MAKE} install else # not OSX test -d /usr/lib64 && ${MAKE} LIBDIRARCH=lib64 ${MAKE} install fi } uninstall() { # Mac OSX needs to find the right directory for pkgconfig if [ "$UNAME" = "Darwin" ]; then # find the directory automatically, so we can support both Macport & Brew export PKGCFGDIR="$(pkg-config --variable pc_path pkg-config | cut -d ':' -f 1)" ${MAKE} uninstall else # not OSX test -d /usr/lib64 && LIBDIRARCH=lib64 ${MAKE} uninstall fi } UNAME="${UNAME:-$(uname)}" if [ "$UNAME" = SunOS ]; then MAKE="${MAKE:-gmake}" export INSTALL_BIN=ginstall export CC=gcc fi MAKE="${MAKE:-make}" if echo "$UNAME" | grep -q BSD; then MAKE=gmake export PREFIX=/usr/local fi MAKE="$MAKE -j${MAKE_JOBS}" TARGET="$1" [ $# -gt 0 ] && shift case "$TARGET" in "" | "default" ) ${MAKE} "$@";; "debug" ) \ CAPSTONE_USE_SYS_DYN_MEM=yes \ CAPSTONE_STATIC=yes \ CFLAGS='-DCAPSTONE_DEBUG -O0 -g -fsanitize=address' \ LDFLAGS='-fsanitize=address' \ ${MAKE} "$@";; "install" ) install;; "uninstall" ) uninstall;; "nix32" ) CFLAGS=-m32 LDFLAGS=-m32 ${MAKE} "$@";; "cross-win32" ) CROSS=i686-w64-mingw32- ${MAKE} "$@";; "cross-win64" ) CROSS=x86_64-w64-mingw32- ${MAKE} "$@";; "cygwin-mingw32" ) CROSS=i686-pc-mingw32- ${MAKE} "$@";; "cygwin-mingw64" ) CROSS=x86_64-w64-mingw32- ${MAKE} "$@";; "cross-android" ) build_android "$@";; "cross-android64" ) CROSS=aarch64-linux-gnu- ${MAKE} "$@";; # Linux cross build "clang" ) CC=clang ${MAKE} "$@";; "gcc" ) CC=gcc ${MAKE} "$@";; "ios" ) build_iOS "$@";; "ios_armv7" ) build_iOS armv7 "$@";; "ios_armv7s" ) build_iOS armv7s "$@";; "ios_arm64" ) build_iOS arm64 "$@";; "osx-kernel" ) CAPSTONE_USE_SYS_DYN_MEM=yes \ CAPSTONE_HAS_OSXKERNEL=yes \ CAPSTONE_ARCHS=x86 \ CAPSTONE_SHARED=no \ CAPSTONE_BUILD_CORE_ONLY=yes \ ${MAKE} "$@";; "mac-universal" ) MACOS_UNIVERSAL=yes ${MAKE} "$@";; "mac-universal-no" ) MACOS_UNIVERSAL=no ${MAKE} "$@";; "xlc31" ) CC=xlc CFLAGS=-q31 LDFLAGS=-q31 ${MAKE} "$@";; "xlc32" ) CC=xlc CFLAGS=-q32 LDFLAGS=-q32 ${MAKE} "$@";; "xlc64" ) CC=xlc CFLAGS=-q64 LDFLAGS=-q64 ${MAKE} "$@";; * ) echo "Usage: $0 ["$(grep '^ "' $0 | cut -d '"' -f 2 | tr "\\n" "|")"]" exit 1;; esac capstone-sys-0.15.0/capstone/nmake.bat000064400000000000000000000017120072674642500157670ustar 00000000000000:: Capstone disassembler engine (www.capstone-engine.org) :: Build Capstone libs (capstone.dll & capstone.lib) on Windows with CMake & Nmake :: By Nguyen Anh Quynh, Jorn Vernee, 2017, 2019 @echo off set flags="-DCMAKE_BUILD_TYPE=Release -DCAPSTONE_BUILD_STATIC_RUNTIME=ON" if "%1"=="ARM" set %arch%=ARM if "%1"=="ARM64" set %arch%=ARM64 if "%1"=="M68K" set %arch%=M68K if "%1"=="MIPS" set %arch%=MIPS if "%1"=="PowerPC" set %arch%=PPC if "%1"=="Sparc" set %arch%=SPARC if "%1"=="SystemZ" set %arch%=SYSZ if "%1"=="XCore" set %arch%=XCORE if "%1"=="x86" set %arch%=X86 if "%1"=="TMS320C64x" set %arch%=TMS320C64X if "%1"=="M680x" set %arch%=M680X if "%1"=="EVM" set %arch%=EVM if "%1"=="MOS65XX" set %arch%=MOS65XX if "%1"=="WASM" set %arch%=WASM if "%1"=="BPF" set %arch%=BPF if "%1"=="RISCV" set %arch%=RISCV if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON" cmake %flags% -G "NMake Makefiles" .. nmake capstone-sys-0.15.0/capstone/packages/freebsd/ports/devel/capstone/Makefile000064400000000000000000000010670072674642500251210ustar 00000000000000# $FreeBSD$ PORTNAME= capstone PORTVERSION= 4.0.0 CATEGORIES= devel MASTER_SITES= http://capstone-engine.org/download/${PORTVERSION}/ MAINTAINER= oliver.pntr@gmail.com COMMENT= Multi-platform, multi-architecture disassembly framework LICENSE= BSD3CLAUSE USES= gmake USE_LDCONFIG= yes MAKE_ENV+= INSTALL_LIB="${INSTALL_LIB}" \ INSTALL_DATA="${INSTALL_DATA}" post-build: # The pkgconfig file is generated and points to stagedir ${REINPLACE_CMD} -e '/libdir/s|\(libdir=\)\(.*\)\(devel/capstone/work/stage\)|\1|g' ${WRKSRC}/capstone.pc .include capstone-sys-0.15.0/capstone/packages/freebsd/ports/devel/capstone/pkg-descr000064400000000000000000000013620072674642500252610ustar 00000000000000Capstone is a lightweight multi-platform, multi-architecture disassembly framework. Features: * Supported architectures: ARM, ARM64 (aka ARMv8), Mips, PowerPC, Sparc, SystemZ, X86, X86_64 & XCore. * Clean/simple/lightweight/intuitive architecture-neutral API * Provide details on disassembled instruction (called "decomposer") * Provide some semantics of the disassembled instruction, such as list of implicit registers read & written. * Implemented in pure C language, with bindings for Python, Ruby, C#, Java, Javascript, GO, OCaml & Vala available. * Native support for Windows & *nix (including MacOSX, Linux, *BSD & Solaris) * Thread-safe by design * Distributed under the open source BSD license WWW: http://capstone-engine.org/ capstone-sys-0.15.0/capstone/packages/freebsd/ports/devel/capstone/pkg-plist000064400000000000000000000005310072674642500253110ustar 00000000000000include/capstone/arm.h include/capstone/arm64.h include/capstone/capstone.h include/capstone/mips.h include/capstone/ppc.h include/capstone/sparc.h include/capstone/systemz.h include/capstone/x86.h include/capstone/xcore.h include/capstone/platform.h lib/libcapstone.a lib/libcapstone.so libdata/pkgconfig/capstone.pc @dirrmtry include/capstone capstone-sys-0.15.0/capstone/packages/macports/devel/capstone/Portfile000064400000000000000000000024730072674642500242410ustar 00000000000000# -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4 # $Id: Portfile 118429 2014-04-02 07:44:35Z and.damore@macports.org $ PortSystem 1.0 name capstone version 3.0.1 categories devel platforms darwin maintainers gmail.com:aquynh license BSD description Capstone disassembly engine long_description Capstone is a multi-arch, multi-platform disassembly framework with advanced features homepage http://www.capstone-engine.org/ master_sites ${homepage}download/${version}/ extract.suffix .tgz checksums sha256 38fc736830de83ae345d917a6c122e2a09119ec5724b553174ddf84062cf2551 \ rmd160 3da96a34fbdde07c2cbb57ed7a76a07c035bb920 patchfiles patch-Makefile.diff variant universal {} use_configure no build.env CC=${configure.cc} \ CFLAGS="${configure.cflags} [get_canonical_archflags cc]" \ LDFLAGS="${configure.ldflags} [get_canonical_archflags ld]" \ PREFIX=${prefix} eval destroot.env ${build.env} livecheck.type regex livecheck.url ${homepage}download.html livecheck.regex ${name}-(\[0-9.\]+)${extract.suffix} capstone-sys-0.15.0/capstone/packages/macports/devel/capstone/files/patch-Makefile.diff000064400000000000000000000012670072674642500273000ustar 00000000000000--- Makefile +++ Makefile @@ -246,14 +246,6 @@ EXT = dylib VERSION_EXT = $(API_MAJOR).$(EXT) $(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) AR_EXT = a -# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE -# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default -ifneq ($(HOMEBREW_CAPSTONE),1) -ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) -# remove string check because OSX kernel complains about missing symbols -CFLAGS += -D_FORTIFY_SOURCE=0 -endif -endif else $(LIBNAME)_LDFLAGS += -shared # Cygwin? capstone-sys-0.15.0/capstone/packages/rpm/capstone.spec000064400000000000000000000106620072674642500212540ustar 00000000000000Name: capstone Version: 3.0.4 Release: 2 Summary: A lightweight multi-platform, multi-architecture disassembly framework License: BSD URL: http://www.capstone-engine.org/ Source0: http://www.capstone-engine.org/download/%{version}/%{name}-%{version}.tar.gz %if 0%{?fedora} > 12 %global with_python3 1 %else %{!?__python2: %global __python2 /usr/bin/python2} %{!?python2_sitelib: %global python2_sitelib %(%{__python2} -c "from distutils.sysconfig import get_python_lib; print (get_python_lib())")} %endif %global srcname distribute BuildRequires: python2-devel BuildRequires: jna BuildRequires: java-devel %if 0%{?with_python3} BuildRequires: python3-devel %endif # if with_python3 %global _hardened_build 1 %description Capstone is a disassembly framework with the target of becoming the ultimate disasm engine for binary analysis and reversing in the security community. %package devel Summary: Development files for %{name} Requires: %{name}%{?_isa} = %{version}-%{release} %description devel The %{name}-devel package contains libraries and header files for developing applications that use %{name}. %package python Summary: Python bindings for %{name} Requires: %{name}%{?_isa} = %{version}-%{release} %description python The %{name}-python package contains python bindings for %{name}. %if 0%{?with_python3} %package python3 Summary: Python3 bindings for %{name} Requires: %{name}%{?_isa} = %{version}-%{release} %description python3 The %{name}-python3 package contains python3 bindings for %{name}. %endif # with_python3 %package java Summary: Java bindings for %{name} Requires: %{name} = %{version}-%{release} BuildArch: noarch %description java The %{name}-java package contains java bindings for %{name}. %prep %setup -q %build DESTDIR="%{buildroot}" V=1 CFLAGS="%{optflags}" \ LIBDIRARCH="%{_lib}" INCDIR="%{_includedir}" make %{?_smp_mflags} # Fix pkgconfig file sed -i 's;%{buildroot};;' capstone.pc grep -v archive capstone.pc > capstone.pc.tmp mv capstone.pc.tmp capstone.pc # build python bindings pushd bindings/python CFLAGS="%{optflags}" %{__python2} setup.py build %if 0%{?with_python3} CFLAGS="%{optflags}" %{__python3} setup.py build %endif # with_python3 popd # build java bindings pushd bindings/java make CFLAGS="%{optflags}" # %{?_smp_mflags} parallel seems broken popd %install DESTDIR=%{buildroot} LIBDIRARCH=%{_lib} \ INCDIR="%{_includedir}" make install find %{buildroot} -name '*.la' -exec rm -f {} ';' find %{buildroot} -name '*.a' -exec rm -f {} ';' # install python bindings pushd bindings/python %{__python2} setup.py install --skip-build --root %{buildroot} %if 0%{?with_python3} %{__python3} setup.py install --skip-build --root %{buildroot} %endif # with_python3 popd # install java bindings install -D -p -m 0644 bindings/java/%{name}.jar %{buildroot}/%{_javadir}/%{name}.jar %check ln -s libcapstone.so libcapstone.so.3 make check LD_LIBRARY_PATH="`pwd`" %post -p /sbin/ldconfig %postun -p /sbin/ldconfig %files # %license does not work for RHEL<7 %if 0%{?rhel} || 0%{?fedora} < 21 %doc LICENSE.TXT LICENSE_LLVM.TXT %else %license LICENSE.TXT LICENSE_LLVM.TXT %endif # %license workarond for RHEL<7 %doc README ChangeLog %{_libdir}/*.so.* %files devel %{_includedir}/* %{_libdir}/*.so %{_libdir}/pkgconfig/* %files python %{python2_sitelib}/*egg-info %{python2_sitelib}/%{name} %if 0%{?with_python3} %files python3 %{python3_sitelib}/*egg-info %{python3_sitelib}/%{name} %endif # _with_python3 %files java %{_javadir}/ %changelog * Thu Jul 16 2015 Stefan Cornelius - 3.0.4-2 - Fix EPEL6 build problems * Wed Jul 15 2015 Stefan Cornelius - 3.0.4-1 - new version 3.0.4. Includes security fixes. * Tue May 12 2015 Stefan Cornelius - 3.0.3-2 - Addressed issues found during package review. * Fri May 08 2015 Stefan Cornelius - 3.0.3-1 - Update to version 3.0.3 * Fri May 08 2015 Stefan Cornelius - 3.0.2-3 - Added python3 and hardened build support. Update java building. - Various cleanups. * Wed May 06 2015 Stefan Cornelius - 3.0.2-2 - Update to 3.0.2. Fix 64bit issues. add %check. * Sat Sep 27 2014 Adel Gadllah - 2.1.2-2 - Addressed issues found during package review. * Mon May 19 2014 Adel Gadllah - 2.1.2-1 - Initial package capstone-sys-0.15.0/capstone/pkgconfig.mk000064400000000000000000000004070072674642500165040ustar 00000000000000# Package version of Capstone for Makefile. # To be used to generate capstone.pc for pkg-config # version major & minor PKG_MAJOR = 5 PKG_MINOR = 0 # version bugfix level. Example: PKG_EXTRA = 1 PKG_EXTRA = 0 # version tag. Examples: rc1, b2, post1 PKG_TAG = capstone-sys-0.15.0/capstone/suite/MC/AArch64/basic-a64-instructions.s.cs000064400000000000000000002531270072674642500240000ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x82,0x00,0x25,0x8b = add x2, x4, w5, uxtb 0xf4,0x23,0x33,0x8b = add x20, sp, w19, uxth 0x2c,0x40,0x34,0x8b = add x12, x1, w20, uxtw 0x74,0x60,0x2d,0x8b = add x20, x3, x13, uxtx 0x31,0x83,0x34,0x8b = add x17, x25, w20, sxtb 0xb2,0xa1,0x33,0x8b = add x18, x13, w19, sxth 0x5f,0xc0,0x23,0x8b = add sp, x2, w3, sxtw 0xa3,0xe0,0x29,0x8b = add x3, x5, x9, sxtx 0xa2,0x00,0x27,0x0b = add w2, w5, w7, uxtb 0xf5,0x21,0x31,0x0b = add w21, w15, w17, uxth 0xbe,0x43,0x3f,0x0b = add w30, w29, wzr, uxtw 0x33,0x62,0x21,0x0b = add w19, w17, w1, uxtx 0xa2,0x80,0x21,0x0b = add w2, w5, w1, sxtb 0x3a,0xa2,0x33,0x0b = add w26, w17, w19, sxth 0x40,0xc0,0x23,0x0b = add w0, w2, w3, sxtw 0x62,0xe0,0x25,0x0b = add w2, w3, w5, sxtx 0x62,0x80,0x25,0x8b = add x2, x3, w5, sxtb 0x67,0x31,0x2d,0x8b = add x7, x11, w13, uxth #4 0x71,0x4a,0x37,0x0b = add w17, w19, w23, uxtw #2 0xfd,0x66,0x31,0x0b = add w29, w23, w17, uxtx #1 0x82,0x08,0x25,0xcb = sub x2, x4, w5, uxtb #2 0xf4,0x33,0x33,0xcb = sub x20, sp, w19, uxth #4 0x2c,0x40,0x34,0xcb = sub x12, x1, w20, uxtw 0x74,0x60,0x2d,0xcb = sub x20, x3, x13, uxtx 0x31,0x83,0x34,0xcb = sub x17, x25, w20, sxtb 0xb2,0xa1,0x33,0xcb = sub x18, x13, w19, sxth 0x5f,0xc0,0x23,0xcb = sub sp, x2, w3, sxtw 0xa3,0xe0,0x29,0xcb = sub x3, x5, x9, sxtx 0xa2,0x00,0x27,0x4b = sub w2, w5, w7, uxtb 0xf5,0x21,0x31,0x4b = sub w21, w15, w17, uxth 0xbe,0x43,0x3f,0x4b = sub w30, w29, wzr, uxtw 0x33,0x62,0x21,0x4b = sub w19, w17, w1, uxtx 0xa2,0x80,0x21,0x4b = sub w2, w5, w1, sxtb 0xfa,0xa3,0x33,0x4b = sub w26, wsp, w19, sxth 0x5f,0xc0,0x23,0x4b = sub wsp, w2, w3, sxtw 0x62,0xe0,0x25,0x4b = sub w2, w3, w5, sxtx 0x82,0x08,0x25,0xab = adds x2, x4, w5, uxtb #2 0xf4,0x33,0x33,0xab = adds x20, sp, w19, uxth #4 0x2c,0x40,0x34,0xab = adds x12, x1, w20, uxtw 0x74,0x60,0x2d,0xab = adds x20, x3, x13, uxtx // 0x3f,0x8f,0x34,0xab = adds xzr, x25, w20, sxtb #3 0xf2,0xa3,0x33,0xab = adds x18, sp, w19, sxth // 0x5f,0xc0,0x23,0xab = adds xzr, x2, w3, sxtw 0xa3,0xe8,0x29,0xab = adds x3, x5, x9, sxtx #2 0xa2,0x00,0x27,0x2b = adds w2, w5, w7, uxtb 0xf5,0x21,0x31,0x2b = adds w21, w15, w17, uxth 0xbe,0x43,0x3f,0x2b = adds w30, w29, wzr, uxtw 0x33,0x62,0x21,0x2b = adds w19, w17, w1, uxtx 0xa2,0x84,0x21,0x2b = adds w2, w5, w1, sxtb #1 0xfa,0xa3,0x33,0x2b = adds w26, wsp, w19, sxth // 0x5f,0xc0,0x23,0x2b = adds wzr, w2, w3, sxtw 0x62,0xe0,0x25,0x2b = adds w2, w3, w5, sxtx 0x82,0x08,0x25,0xeb = subs x2, x4, w5, uxtb #2 0xf4,0x33,0x33,0xeb = subs x20, sp, w19, uxth #4 0x2c,0x40,0x34,0xeb = subs x12, x1, w20, uxtw 0x74,0x60,0x2d,0xeb = subs x20, x3, x13, uxtx // 0x3f,0x8f,0x34,0xeb = subs xzr, x25, w20, sxtb #3 0xf2,0xa3,0x33,0xeb = subs x18, sp, w19, sxth // 0x5f,0xc0,0x23,0xeb = subs xzr, x2, w3, sxtw 0xa3,0xe8,0x29,0xeb = subs x3, x5, x9, sxtx #2 0xa2,0x00,0x27,0x6b = subs w2, w5, w7, uxtb 0xf5,0x21,0x31,0x6b = subs w21, w15, w17, uxth 0xbe,0x43,0x3f,0x6b = subs w30, w29, wzr, uxtw 0x33,0x62,0x21,0x6b = subs w19, w17, w1, uxtx 0xa2,0x84,0x21,0x6b = subs w2, w5, w1, sxtb #1 0xfa,0xa3,0x33,0x6b = subs w26, wsp, w19, sxth // 0x5f,0xc0,0x23,0x6b = subs wzr, w2, w3, sxtw 0x62,0xe0,0x25,0x6b = subs w2, w3, w5, sxtx 0x9f,0x08,0x25,0xeb = cmp x4, w5, uxtb #2 0xff,0x33,0x33,0xeb = cmp sp, w19, uxth #4 0x3f,0x40,0x34,0xeb = cmp x1, w20, uxtw 0x7f,0x60,0x2d,0xeb = cmp x3, x13, uxtx // 0x3f,0x8f,0x34,0xeb = cmp x25, w20, sxtb #3 0xff,0xa3,0x33,0xeb = cmp sp, w19, sxth // 0x5f,0xc0,0x23,0xeb = cmp x2, w3, sxtw 0xbf,0xe8,0x29,0xeb = cmp x5, x9, sxtx #2 0xbf,0x00,0x27,0x6b = cmp w5, w7, uxtb 0xff,0x21,0x31,0x6b = cmp w15, w17, uxth 0xbf,0x43,0x3f,0x6b = cmp w29, wzr, uxtw 0x3f,0x62,0x21,0x6b = cmp w17, w1, uxtx 0xbf,0x84,0x21,0x6b = cmp w5, w1, sxtb #1 0xff,0xa3,0x33,0x6b = cmp wsp, w19, sxth // 0x5f,0xc0,0x23,0x6b = cmp w2, w3, sxtw 0x7f,0xe0,0x25,0x6b = cmp w3, w5, sxtx 0x9f,0x08,0x25,0xab = cmn x4, w5, uxtb #2 0xff,0x33,0x33,0xab = cmn sp, w19, uxth #4 0x3f,0x40,0x34,0xab = cmn x1, w20, uxtw 0x7f,0x60,0x2d,0xab = cmn x3, x13, uxtx // 0x3f,0x8f,0x34,0xab = cmn x25, w20, sxtb #3 0xff,0xa3,0x33,0xab = cmn sp, w19, sxth // 0x5f,0xc0,0x23,0xab = cmn x2, w3, sxtw 0xbf,0xe8,0x29,0xab = cmn x5, x9, sxtx #2 0xbf,0x00,0x27,0x2b = cmn w5, w7, uxtb 0xff,0x21,0x31,0x2b = cmn w15, w17, uxth 0xbf,0x43,0x3f,0x2b = cmn w29, wzr, uxtw 0x3f,0x62,0x21,0x2b = cmn w17, w1, uxtx 0xbf,0x84,0x21,0x2b = cmn w5, w1, sxtb #1 0xff,0xa3,0x33,0x2b = cmn wsp, w19, sxth // 0x5f,0xc0,0x23,0x2b = cmn w2, w3, sxtw 0x7f,0xe0,0x25,0x2b = cmn w3, w5, sxtx 0x9f,0x0e,0x3d,0xeb = cmp x20, w29, uxtb #3 0x9f,0x71,0x2d,0xeb = cmp x12, x13, uxtx #4 0xff,0x03,0x21,0x6b = cmp wsp, w1, uxtb 0xff,0xc3,0x3f,0x2b = cmn wsp, wzr, sxtw 0x7f,0x70,0x27,0xcb = sub sp, x3, x7, lsl #4 0xe2,0x47,0x23,0x0b = add w2, wsp, w3, lsl #1 0xff,0x43,0x29,0x6b = cmp wsp, w9 // 0xff,0x53,0x23,0x2b = adds wzr, wsp, w3, lsl #4 0xe3,0x6b,0x29,0xeb = subs x3, sp, x9, lsl #2 0xa4,0x00,0x00,0x11 = add w4, w5, #0 0x62,0xfc,0x3f,0x11 = add w2, w3, #0xfff 0xbe,0x07,0x40,0x11 = add w30, w29, #1, lsl #12 0xad,0xfc,0x7f,0x11 = add w13, w5, #0xfff, lsl #12 0xe5,0x98,0x19,0x91 = add x5, x7, #0x666 0xf4,0x87,0x0c,0x11 = add w20, wsp, #0x321 0xff,0x43,0x11,0x11 = add wsp, wsp, #0x450 0xdf,0xd3,0x3f,0x11 = add wsp, w30, #0xff4 0x00,0x8f,0x04,0x91 = add x0, x24, #0x123 0x03,0xff,0x7f,0x91 = add x3, x24, #0xfff, lsl #12 0xe8,0xcb,0x10,0x91 = add x8, sp, #0x432 0xbf,0xa3,0x3b,0x91 = add sp, x29, #0xee8 0xe0,0xb7,0x3f,0x51 = sub w0, wsp, #0xfed 0x84,0x8a,0x48,0x51 = sub w4, w20, #0x222, lsl #12 0xff,0x83,0x04,0xd1 = sub sp, sp, #0x120 0x7f,0x42,0x00,0x51 = sub wsp, w19, #0x10 0xed,0x8e,0x44,0x31 = adds w13, w23, #0x123, lsl #12 // 0x5f,0xfc,0x3f,0x31 = adds wzr, w2, #0xfff 0xf4,0x03,0x00,0x31 = adds w20, wsp, #0 // 0x7f,0x04,0x40,0xb1 = adds xzr, x3, #1, lsl #12 // 0xff,0x53,0x40,0xf1 = subs xzr, sp, #0x14, lsl #12 // 0xdf,0xff,0x3f,0xf1 = subs xzr, x30, #0xfff 0xe4,0xbb,0x3b,0xf1 = subs x4, sp, #0xeee 0x7f,0x8c,0x44,0x31 = cmn w3, #0x123, lsl #12 0xff,0x57,0x15,0x31 = cmn wsp, #0x555 0xff,0x13,0x51,0xb1 = cmn sp, #0x444, lsl #12 0x9f,0xb0,0x44,0xf1 = cmp x4, #0x12c, lsl #12 0xff,0xd3,0x07,0x71 = cmp wsp, #0x1f4 0xff,0x23,0x03,0xf1 = cmp sp, #0xc8 0xdf,0x03,0x00,0x91 = mov sp, x30 0x9f,0x02,0x00,0x11 = mov wsp, w20 0xeb,0x03,0x00,0x91 = mov x11, sp 0xf8,0x03,0x00,0x11 = mov w24, wsp 0xa3,0x00,0x07,0x0b = add w3, w5, w7 0x7f,0x00,0x05,0x0b = add wzr, w3, w5 0xf4,0x03,0x04,0x0b = add w20, wzr, w4 0xc4,0x00,0x1f,0x0b = add w4, w6, wzr 0xab,0x01,0x0f,0x0b = add w11, w13, w15 0x69,0x28,0x1f,0x0b = add w9, w3, wzr, lsl #10 0xb1,0x7f,0x14,0x0b = add w17, w29, w20, lsl #31 0xd5,0x02,0x57,0x0b = add w21, w22, w23, lsr #0 0x38,0x4b,0x5a,0x0b = add w24, w25, w26, lsr #18 0x9b,0x7f,0x5d,0x0b = add w27, w28, w29, lsr #31 0x62,0x00,0x84,0x0b = add w2, w3, w4, asr #0 0xc5,0x54,0x87,0x0b = add w5, w6, w7, asr #21 0x28,0x7d,0x8a,0x0b = add w8, w9, w10, asr #31 0xa3,0x00,0x07,0x8b = add x3, x5, x7 0x7f,0x00,0x05,0x8b = add xzr, x3, x5 0xf4,0x03,0x04,0x8b = add x20, xzr, x4 0xc4,0x00,0x1f,0x8b = add x4, x6, xzr 0xab,0x01,0x0f,0x8b = add x11, x13, x15 0x69,0x28,0x1f,0x8b = add x9, x3, xzr, lsl #10 0xb1,0xff,0x14,0x8b = add x17, x29, x20, lsl #63 0xd5,0x02,0x57,0x8b = add x21, x22, x23, lsr #0 0x38,0x4b,0x5a,0x8b = add x24, x25, x26, lsr #18 0x9b,0xff,0x5d,0x8b = add x27, x28, x29, lsr #63 0x62,0x00,0x84,0x8b = add x2, x3, x4, asr #0 0xc5,0x54,0x87,0x8b = add x5, x6, x7, asr #21 0x28,0xfd,0x8a,0x8b = add x8, x9, x10, asr #63 0xa3,0x00,0x07,0x2b = adds w3, w5, w7 // 0x7f,0x00,0x05,0x2b = adds wzr, w3, w5 0xf4,0x03,0x04,0x2b = adds w20, wzr, w4 0xc4,0x00,0x1f,0x2b = adds w4, w6, wzr 0xab,0x01,0x0f,0x2b = adds w11, w13, w15 0x69,0x28,0x1f,0x2b = adds w9, w3, wzr, lsl #10 0xb1,0x7f,0x14,0x2b = adds w17, w29, w20, lsl #31 0xd5,0x02,0x57,0x2b = adds w21, w22, w23, lsr #0 0x38,0x4b,0x5a,0x2b = adds w24, w25, w26, lsr #18 0x9b,0x7f,0x5d,0x2b = adds w27, w28, w29, lsr #31 0x62,0x00,0x84,0x2b = adds w2, w3, w4, asr #0 0xc5,0x54,0x87,0x2b = adds w5, w6, w7, asr #21 0x28,0x7d,0x8a,0x2b = adds w8, w9, w10, asr #31 0xa3,0x00,0x07,0xab = adds x3, x5, x7 // 0x7f,0x00,0x05,0xab = adds xzr, x3, x5 0xf4,0x03,0x04,0xab = adds x20, xzr, x4 0xc4,0x00,0x1f,0xab = adds x4, x6, xzr 0xab,0x01,0x0f,0xab = adds x11, x13, x15 0x69,0x28,0x1f,0xab = adds x9, x3, xzr, lsl #10 0xb1,0xff,0x14,0xab = adds x17, x29, x20, lsl #63 0xd5,0x02,0x57,0xab = adds x21, x22, x23, lsr #0 0x38,0x4b,0x5a,0xab = adds x24, x25, x26, lsr #18 0x9b,0xff,0x5d,0xab = adds x27, x28, x29, lsr #63 0x62,0x00,0x84,0xab = adds x2, x3, x4, asr #0 0xc5,0x54,0x87,0xab = adds x5, x6, x7, asr #21 0x28,0xfd,0x8a,0xab = adds x8, x9, x10, asr #63 0xa3,0x00,0x07,0x4b = sub w3, w5, w7 0x7f,0x00,0x05,0x4b = sub wzr, w3, w5 // 0xf4,0x03,0x04,0x4b = sub w20, wzr, w4 0xc4,0x00,0x1f,0x4b = sub w4, w6, wzr 0xab,0x01,0x0f,0x4b = sub w11, w13, w15 0x69,0x28,0x1f,0x4b = sub w9, w3, wzr, lsl #10 0xb1,0x7f,0x14,0x4b = sub w17, w29, w20, lsl #31 0xd5,0x02,0x57,0x4b = sub w21, w22, w23, lsr #0 0x38,0x4b,0x5a,0x4b = sub w24, w25, w26, lsr #18 0x9b,0x7f,0x5d,0x4b = sub w27, w28, w29, lsr #31 0x62,0x00,0x84,0x4b = sub w2, w3, w4, asr #0 0xc5,0x54,0x87,0x4b = sub w5, w6, w7, asr #21 0x28,0x7d,0x8a,0x4b = sub w8, w9, w10, asr #31 0xa3,0x00,0x07,0xcb = sub x3, x5, x7 0x7f,0x00,0x05,0xcb = sub xzr, x3, x5 // 0xf4,0x03,0x04,0xcb = sub x20, xzr, x4 0xc4,0x00,0x1f,0xcb = sub x4, x6, xzr 0xab,0x01,0x0f,0xcb = sub x11, x13, x15 0x69,0x28,0x1f,0xcb = sub x9, x3, xzr, lsl #10 0xb1,0xff,0x14,0xcb = sub x17, x29, x20, lsl #63 0xd5,0x02,0x57,0xcb = sub x21, x22, x23, lsr #0 0x38,0x4b,0x5a,0xcb = sub x24, x25, x26, lsr #18 0x9b,0xff,0x5d,0xcb = sub x27, x28, x29, lsr #63 0x62,0x00,0x84,0xcb = sub x2, x3, x4, asr #0 0xc5,0x54,0x87,0xcb = sub x5, x6, x7, asr #21 0x28,0xfd,0x8a,0xcb = sub x8, x9, x10, asr #63 0xa3,0x00,0x07,0x6b = subs w3, w5, w7 // 0x7f,0x00,0x05,0x6b = subs wzr, w3, w5 // 0xf4,0x03,0x04,0x6b = subs w20, wzr, w4 0xc4,0x00,0x1f,0x6b = subs w4, w6, wzr 0xab,0x01,0x0f,0x6b = subs w11, w13, w15 0x69,0x28,0x1f,0x6b = subs w9, w3, wzr, lsl #10 0xb1,0x7f,0x14,0x6b = subs w17, w29, w20, lsl #31 0xd5,0x02,0x57,0x6b = subs w21, w22, w23, lsr #0 0x38,0x4b,0x5a,0x6b = subs w24, w25, w26, lsr #18 0x9b,0x7f,0x5d,0x6b = subs w27, w28, w29, lsr #31 0x62,0x00,0x84,0x6b = subs w2, w3, w4, asr #0 0xc5,0x54,0x87,0x6b = subs w5, w6, w7, asr #21 0x28,0x7d,0x8a,0x6b = subs w8, w9, w10, asr #31 0xa3,0x00,0x07,0xeb = subs x3, x5, x7 // 0x7f,0x00,0x05,0xeb = subs xzr, x3, x5 // 0xf4,0x03,0x04,0xeb = subs x20, xzr, x4 0xc4,0x00,0x1f,0xeb = subs x4, x6, xzr 0xab,0x01,0x0f,0xeb = subs x11, x13, x15 0x69,0x28,0x1f,0xeb = subs x9, x3, xzr, lsl #10 0xb1,0xff,0x14,0xeb = subs x17, x29, x20, lsl #63 0xd5,0x02,0x57,0xeb = subs x21, x22, x23, lsr #0 0x38,0x4b,0x5a,0xeb = subs x24, x25, x26, lsr #18 0x9b,0xff,0x5d,0xeb = subs x27, x28, x29, lsr #63 0x62,0x00,0x84,0xeb = subs x2, x3, x4, asr #0 0xc5,0x54,0x87,0xeb = subs x5, x6, x7, asr #21 0x28,0xfd,0x8a,0xeb = subs x8, x9, x10, asr #63 0x1f,0x00,0x03,0x2b = cmn w0, w3 0xff,0x03,0x04,0x2b = cmn wzr, w4 0xbf,0x00,0x1f,0x2b = cmn w5, wzr 0xdf,0x00,0x07,0x2b = cmn w6, w7 0x1f,0x3d,0x09,0x2b = cmn w8, w9, lsl #15 0x5f,0x7d,0x0b,0x2b = cmn w10, w11, lsl #31 0x9f,0x01,0x4d,0x2b = cmn w12, w13, lsr #0 0xdf,0x55,0x4f,0x2b = cmn w14, w15, lsr #21 0x1f,0x7e,0x51,0x2b = cmn w16, w17, lsr #31 0x5f,0x02,0x93,0x2b = cmn w18, w19, asr #0 0x9f,0x5a,0x95,0x2b = cmn w20, w21, asr #22 0xdf,0x7e,0x97,0x2b = cmn w22, w23, asr #31 0x1f,0x00,0x03,0xab = cmn x0, x3 0xff,0x03,0x04,0xab = cmn xzr, x4 0xbf,0x00,0x1f,0xab = cmn x5, xzr 0xdf,0x00,0x07,0xab = cmn x6, x7 0x1f,0x3d,0x09,0xab = cmn x8, x9, lsl #15 0x5f,0xfd,0x0b,0xab = cmn x10, x11, lsl #63 0x9f,0x01,0x4d,0xab = cmn x12, x13, lsr #0 0xdf,0xa5,0x4f,0xab = cmn x14, x15, lsr #41 0x1f,0xfe,0x51,0xab = cmn x16, x17, lsr #63 0x5f,0x02,0x93,0xab = cmn x18, x19, asr #0 0x9f,0xde,0x95,0xab = cmn x20, x21, asr #55 0xdf,0xfe,0x97,0xab = cmn x22, x23, asr #63 0x1f,0x00,0x03,0x6b = cmp w0, w3 0xff,0x03,0x04,0x6b = cmp wzr, w4 0xbf,0x00,0x1f,0x6b = cmp w5, wzr 0xdf,0x00,0x07,0x6b = cmp w6, w7 0x1f,0x3d,0x09,0x6b = cmp w8, w9, lsl #15 0x5f,0x7d,0x0b,0x6b = cmp w10, w11, lsl #31 0x9f,0x01,0x4d,0x6b = cmp w12, w13, lsr #0 0xdf,0x55,0x4f,0x6b = cmp w14, w15, lsr #21 0x1f,0x7e,0x51,0x6b = cmp w16, w17, lsr #31 0x5f,0x02,0x93,0x6b = cmp w18, w19, asr #0 0x9f,0x5a,0x95,0x6b = cmp w20, w21, asr #22 0xdf,0x7e,0x97,0x6b = cmp w22, w23, asr #31 0x1f,0x00,0x03,0xeb = cmp x0, x3 0xff,0x03,0x04,0xeb = cmp xzr, x4 0xbf,0x00,0x1f,0xeb = cmp x5, xzr 0xdf,0x00,0x07,0xeb = cmp x6, x7 0x1f,0x3d,0x09,0xeb = cmp x8, x9, lsl #15 0x5f,0xfd,0x0b,0xeb = cmp x10, x11, lsl #63 0x9f,0x01,0x4d,0xeb = cmp x12, x13, lsr #0 0xdf,0xa5,0x4f,0xeb = cmp x14, x15, lsr #41 0x1f,0xfe,0x51,0xeb = cmp x16, x17, lsr #63 0x5f,0x02,0x93,0xeb = cmp x18, x19, asr #0 0x9f,0xde,0x95,0xeb = cmp x20, x21, asr #55 0xdf,0xfe,0x97,0xeb = cmp x22, x23, asr #63 // 0xfd,0x03,0x1e,0x4b = sub w29, wzr, w30 // 0xfe,0x03,0x1f,0x4b = sub w30, wzr, wzr // 0xff,0x03,0x00,0x4b = sub wzr, wzr, w0 // 0xfc,0x03,0x1b,0x4b = sub w28, wzr, w27 // 0xfa,0x77,0x19,0x4b = sub w26, wzr, w25, lsl #29 // 0xf8,0x7f,0x17,0x4b = sub w24, wzr, w23, lsl #31 // 0xf6,0x03,0x55,0x4b = sub w22, wzr, w21, lsr #0 // 0xf4,0x07,0x53,0x4b = sub w20, wzr, w19, lsr #1 // 0xf2,0x7f,0x51,0x4b = sub w18, wzr, w17, lsr #31 // 0xf0,0x03,0x8f,0x4b = sub w16, wzr, w15, asr #0 // 0xee,0x33,0x8d,0x4b = sub w14, wzr, w13, asr #12 // 0xec,0x7f,0x8b,0x4b = sub w12, wzr, w11, asr #31 // 0xfd,0x03,0x1e,0xcb = sub x29, xzr, x30 // 0xfe,0x03,0x1f,0xcb = sub x30, xzr, xzr // 0xff,0x03,0x00,0xcb = sub xzr, xzr, x0 // 0xfc,0x03,0x1b,0xcb = sub x28, xzr, x27 // 0xfa,0x77,0x19,0xcb = sub x26, xzr, x25, lsl #29 // 0xf8,0x7f,0x17,0xcb = sub x24, xzr, x23, lsl #31 // 0xf6,0x03,0x55,0xcb = sub x22, xzr, x21, lsr #0 // 0xf4,0x07,0x53,0xcb = sub x20, xzr, x19, lsr #1 // 0xf2,0x7f,0x51,0xcb = sub x18, xzr, x17, lsr #31 // 0xf0,0x03,0x8f,0xcb = sub x16, xzr, x15, asr #0 // 0xee,0x33,0x8d,0xcb = sub x14, xzr, x13, asr #12 // 0xec,0x7f,0x8b,0xcb = sub x12, xzr, x11, asr #31 // 0xfd,0x03,0x1e,0x6b = subs w29, wzr, w30 // 0xfe,0x03,0x1f,0x6b = subs w30, wzr, wzr // 0xff,0x03,0x00,0x6b = subs wzr, wzr, w0 // 0xfc,0x03,0x1b,0x6b = subs w28, wzr, w27 // 0xfa,0x77,0x19,0x6b = subs w26, wzr, w25, lsl #29 // 0xf8,0x7f,0x17,0x6b = subs w24, wzr, w23, lsl #31 // 0xf6,0x03,0x55,0x6b = subs w22, wzr, w21, lsr #0 // 0xf4,0x07,0x53,0x6b = subs w20, wzr, w19, lsr #1 // 0xf2,0x7f,0x51,0x6b = subs w18, wzr, w17, lsr #31 // 0xf0,0x03,0x8f,0x6b = subs w16, wzr, w15, asr #0 // 0xee,0x33,0x8d,0x6b = subs w14, wzr, w13, asr #12 // 0xec,0x7f,0x8b,0x6b = subs w12, wzr, w11, asr #31 // 0xfd,0x03,0x1e,0xeb = subs x29, xzr, x30 // 0xfe,0x03,0x1f,0xeb = subs x30, xzr, xzr // 0xff,0x03,0x00,0xeb = subs xzr, xzr, x0 // 0xfc,0x03,0x1b,0xeb = subs x28, xzr, x27 // 0xfa,0x77,0x19,0xeb = subs x26, xzr, x25, lsl #29 // 0xf8,0x7f,0x17,0xeb = subs x24, xzr, x23, lsl #31 // 0xf6,0x03,0x55,0xeb = subs x22, xzr, x21, lsr #0 // 0xf4,0x07,0x53,0xeb = subs x20, xzr, x19, lsr #1 // 0xf2,0x7f,0x51,0xeb = subs x18, xzr, x17, lsr #31 // 0xf0,0x03,0x8f,0xeb = subs x16, xzr, x15, asr #0 // 0xee,0x33,0x8d,0xeb = subs x14, xzr, x13, asr #12 // 0xec,0x7f,0x8b,0xeb = subs x12, xzr, x11, asr #31 0x7d,0x03,0x19,0x1a = adc w29, w27, w25 0x7f,0x00,0x04,0x1a = adc wzr, w3, w4 0xe9,0x03,0x0a,0x1a = adc w9, wzr, w10 0x14,0x00,0x1f,0x1a = adc w20, w0, wzr 0x7d,0x03,0x19,0x9a = adc x29, x27, x25 0x7f,0x00,0x04,0x9a = adc xzr, x3, x4 0xe9,0x03,0x0a,0x9a = adc x9, xzr, x10 0x14,0x00,0x1f,0x9a = adc x20, x0, xzr 0x7d,0x03,0x19,0x3a = adcs w29, w27, w25 0x7f,0x00,0x04,0x3a = adcs wzr, w3, w4 0xe9,0x03,0x0a,0x3a = adcs w9, wzr, w10 0x14,0x00,0x1f,0x3a = adcs w20, w0, wzr 0x7d,0x03,0x19,0xba = adcs x29, x27, x25 0x7f,0x00,0x04,0xba = adcs xzr, x3, x4 0xe9,0x03,0x0a,0xba = adcs x9, xzr, x10 0x14,0x00,0x1f,0xba = adcs x20, x0, xzr 0x7d,0x03,0x19,0x5a = sbc w29, w27, w25 0x7f,0x00,0x04,0x5a = sbc wzr, w3, w4 0xe9,0x03,0x0a,0x5a = ngc w9, w10 0x14,0x00,0x1f,0x5a = sbc w20, w0, wzr 0x7d,0x03,0x19,0xda = sbc x29, x27, x25 0x7f,0x00,0x04,0xda = sbc xzr, x3, x4 0xe9,0x03,0x0a,0xda = ngc x9, x10 0x14,0x00,0x1f,0xda = sbc x20, x0, xzr 0x7d,0x03,0x19,0x7a = sbcs w29, w27, w25 0x7f,0x00,0x04,0x7a = sbcs wzr, w3, w4 0xe9,0x03,0x0a,0x7a = ngcs w9, w10 0x14,0x00,0x1f,0x7a = sbcs w20, w0, wzr 0x7d,0x03,0x19,0xfa = sbcs x29, x27, x25 0x7f,0x00,0x04,0xfa = sbcs xzr, x3, x4 0xe9,0x03,0x0a,0xfa = ngcs x9, x10 0x14,0x00,0x1f,0xfa = sbcs x20, x0, xzr 0xe3,0x03,0x0c,0x5a = ngc w3, w12 0xff,0x03,0x09,0x5a = ngc wzr, w9 0xf7,0x03,0x1f,0x5a = ngc w23, wzr 0xfd,0x03,0x1e,0xda = ngc x29, x30 0xff,0x03,0x00,0xda = ngc xzr, x0 0xe0,0x03,0x1f,0xda = ngc x0, xzr 0xe3,0x03,0x0c,0x7a = ngcs w3, w12 0xff,0x03,0x09,0x7a = ngcs wzr, w9 0xf7,0x03,0x1f,0x7a = ngcs w23, wzr 0xfd,0x03,0x1e,0xfa = ngcs x29, x30 0xff,0x03,0x00,0xfa = ngcs xzr, x0 0xe0,0x03,0x1f,0xfa = ngcs x0, xzr // 0x41,0x10,0x43,0x93 = sbfm x1, x2, #3, #4 // 0x83,0xfc,0x7f,0x93 = sbfm x3, x4, #63, #63 // 0xff,0x7f,0x1f,0x13 = sbfm wzr, wzr, #31, #31 // 0x2c,0x01,0x00,0x13 = sbfm w12, w9, #0, #0 // 0xa4,0x28,0x4c,0xd3 = ubfm x4, x5, #12, #10 // 0x9f,0x00,0x40,0xd3 = ubfm xzr, x4, #0, #0 // 0xe4,0x17,0x7f,0xd3 = ubfm x4, xzr, #63, #5 // 0xc5,0xfc,0x4c,0xd3 = ubfm x5, x6, #12, #63 // 0xa4,0x28,0x4c,0xb3 = bfm x4, x5, #12, #10 // 0x9f,0x00,0x40,0xb3 = bfm xzr, x4, #0, #0 // 0xe4,0x17,0x7f,0xb3 = bfm x4, xzr, #63, #5 // 0xc5,0xfc,0x4c,0xb3 = bfm x5, x6, #12, #63 0x41,0x1c,0x00,0x13 = sxtb w1, w2 0x7f,0x1c,0x40,0x93 = sxtb xzr, w3 0x49,0x3d,0x00,0x13 = sxth w9, w10 0x20,0x3c,0x40,0x93 = sxth x0, w1 0xc3,0x7f,0x40,0x93 = sxtw x3, w30 0x41,0x1c,0x00,0x53 = uxtb w1, w2 // 0x7f,0x1c,0x00,0x53 = uxtb xzr, w3 0x49,0x3d,0x00,0x53 = uxth w9, w10 // 0x20,0x3c,0x00,0x53 = uxth x0, w1 0x43,0x7c,0x00,0x13 = asr w3, w2, #0 0x49,0x7d,0x1f,0x13 = asr w9, w10, #0x1f 0xb4,0xfe,0x7f,0x93 = asr x20, x21, #0x3f 0xe1,0x7f,0x03,0x13 = asr w1, wzr, #3 // 0x43,0x7c,0x00,0x53 = lsr w3, w2, #0 0x49,0x7d,0x1f,0x53 = lsr w9, w10, #0x1f 0xb4,0xfe,0x7f,0xd3 = lsr x20, x21, #0x3f 0xff,0x7f,0x03,0x53 = lsr wzr, wzr, #3 // 0x43,0x7c,0x00,0x53 = lsl w3, w2, #0 0x49,0x01,0x01,0x53 = lsl w9, w10, #0x1f 0xb4,0x02,0x41,0xd3 = lsl x20, x21, #0x3f 0xe1,0x73,0x1d,0x53 = lsl w1, wzr, #3 // 0x49,0x01,0x00,0x13 = sbfiz w9, w10, #0, #1 0x62,0x00,0x41,0x93 = sbfiz x2, x3, #0x3f, #1 // 0x93,0xfe,0x40,0x93 = sbfiz x19, x20, #0, #64 0x49,0xe9,0x7b,0x93 = sbfiz x9, x10, #5, #59 // 0x49,0x7d,0x00,0x13 = sbfiz w9, w10, #0, #32 0x8b,0x01,0x01,0x13 = sbfiz w11, w12, #0x1f, #1 0xcd,0x09,0x03,0x13 = sbfiz w13, w14, #0x1d, #3 0xff,0x2b,0x76,0x93 = sbfiz xzr, xzr, #0xa, #11 // 0x49,0x01,0x00,0x13 = sbfx w9, w10, #0, #1 // 0x62,0xfc,0x7f,0x93 = sbfx x2, x3, #0x3f, #1 // 0x93,0xfe,0x40,0x93 = sbfx x19, x20, #0, #64 // 0x49,0xfd,0x45,0x93 = sbfx x9, x10, #5, #59 // 0x49,0x7d,0x00,0x13 = sbfx w9, w10, #0, #32 // 0x8b,0x7d,0x1f,0x13 = sbfx w11, w12, #31, #1 // 0xcd,0x7d,0x1d,0x13 = sbfx w13, w14, #29, #3 0xff,0x53,0x4a,0x93 = sbfx xzr, xzr, #10, #11 // 0x49,0x01,0x00,0x33 = bfi w9, w10, #0, #1 0x62,0x00,0x41,0xb3 = bfi x2, x3, #63, #1 // 0x93,0xfe,0x40,0xb3 = bfi x19, x20, #0, #64 0x49,0xe9,0x7b,0xb3 = bfi x9, x10, #5, #59 // 0x49,0x7d,0x00,0x33 = bfi w9, w10, #0, #32 0x8b,0x01,0x01,0x33 = bfi w11, w12, #31, #1 0xcd,0x09,0x03,0x33 = bfi w13, w14, #29, #3 0xff,0x2b,0x76,0xb3 = bfc xzr, #0xa, #0xb // 0x49,0x01,0x00,0x33 = bfxil w9, w10, #0, #1 0x62,0xfc,0x7f,0xb3 = bfxil x2, x3, #63, #1 // 0x93,0xfe,0x40,0xb3 = bfxil x19, x20, #0, #64 0x49,0xfd,0x45,0xb3 = bfxil x9, x10, #5, #59 // 0x49,0x7d,0x00,0x33 = bfxil w9, w10, #0, #32 0x8b,0x7d,0x1f,0x33 = bfxil w11, w12, #31, #1 0xcd,0x7d,0x1d,0x33 = bfxil w13, w14, #29, #3 0xff,0x53,0x4a,0xb3 = bfxil xzr, xzr, #10, #11 // 0x49,0x01,0x00,0x53 = ubfiz w9, w10, #0, #1 // 0x62,0x00,0x41,0xd3 = ubfiz x2, x3, #63, #1 // 0x93,0xfe,0x40,0xd3 = ubfiz x19, x20, #0, #64 // 0x49,0xe9,0x7b,0xd3 = ubfiz x9, x10, #5, #59 // 0x49,0x7d,0x00,0x53 = ubfiz w9, w10, #0, #32 // 0x8b,0x01,0x01,0x53 = ubfiz w11, w12, #31, #1 // 0xcd,0x09,0x03,0x53 = ubfiz w13, w14, #29, #3 0xff,0x2b,0x76,0xd3 = ubfiz xzr, xzr, #10, #11 // 0x49,0x01,0x00,0x53 = ubfx w9, w10, #0, #1 // 0x62,0xfc,0x7f,0xd3 = ubfx x2, x3, #63, #1 // 0x93,0xfe,0x40,0xd3 = ubfx x19, x20, #0, #64 // 0x49,0xfd,0x45,0xd3 = ubfx x9, x10, #5, #59 // 0x49,0x7d,0x00,0x53 = ubfx w9, w10, #0, #32 // 0x8b,0x7d,0x1f,0x53 = ubfx w11, w12, #31, #1 // 0xcd,0x7d,0x1d,0x53 = ubfx w13, w14, #29, #3 0xff,0x53,0x4a,0xd3 = ubfx xzr, xzr, #10, #11 0x05,0x00,0x00,0x34 = cbz w5, #0 0xe3,0xff,0xff,0xb5 = cbnz x3, #-4 0xf4,0xff,0x7f,0x34 = cbz w20, #1048572 0x1f,0x00,0x80,0xb5 = cbnz xzr, #-1048576 0x00,0x00,0x00,0x54 = b.eq #0 0xeb,0xff,0xff,0x54 = b.lt #-4 0xe3,0xff,0x7f,0x54 = b.lo #1048572 0x20,0x08,0x5f,0x7a = ccmp w1, #31, #0, eq 0x6f,0x28,0x40,0x7a = ccmp w3, #0, #15, hs 0xed,0x2b,0x4f,0x7a = ccmp wzr, #15, #13, hs 0x20,0xd9,0x5f,0xfa = ccmp x9, #31, #0, le 0x6f,0xc8,0x40,0xfa = ccmp x3, #0, #15, gt 0xe7,0x1b,0x45,0xfa = ccmp xzr, #5, #7, ne 0x20,0x08,0x5f,0x3a = ccmn w1, #31, #0, eq 0x6f,0x28,0x40,0x3a = ccmn w3, #0, #15, hs 0xed,0x2b,0x4f,0x3a = ccmn wzr, #15, #13, hs 0x20,0xd9,0x5f,0xba = ccmn x9, #31, #0, le 0x6f,0xc8,0x40,0xba = ccmn x3, #0, #15, gt 0xe7,0x1b,0x45,0xba = ccmn xzr, #5, #7, ne 0x20,0x00,0x5f,0x7a = ccmp w1, wzr, #0, eq 0x6f,0x20,0x40,0x7a = ccmp w3, w0, #15, hs 0xed,0x23,0x4f,0x7a = ccmp wzr, w15, #13, hs 0x20,0xd1,0x5f,0xfa = ccmp x9, xzr, #0, le 0x6f,0xc0,0x40,0xfa = ccmp x3, x0, #15, gt 0xe7,0x13,0x45,0xfa = ccmp xzr, x5, #7, ne 0x20,0x00,0x5f,0x3a = ccmn w1, wzr, #0, eq 0x6f,0x20,0x40,0x3a = ccmn w3, w0, #15, hs 0xed,0x23,0x4f,0x3a = ccmn wzr, w15, #13, hs 0x20,0xd1,0x5f,0xba = ccmn x9, xzr, #0, le 0x6f,0xc0,0x40,0xba = ccmn x3, x0, #15, gt 0xe7,0x13,0x45,0xba = ccmn xzr, x5, #7, ne 0x01,0x10,0x93,0x1a = csel w1, w0, w19, ne 0xbf,0x00,0x89,0x1a = csel wzr, w5, w9, eq 0xe9,0xc3,0x9e,0x1a = csel w9, wzr, w30, gt 0x81,0x43,0x9f,0x1a = csel w1, w28, wzr, mi 0xf3,0xb2,0x9d,0x9a = csel x19, x23, x29, lt 0x7f,0xa0,0x84,0x9a = csel xzr, x3, x4, ge 0xe5,0x23,0x86,0x9a = csel x5, xzr, x6, hs 0x07,0x31,0x9f,0x9a = csel x7, x8, xzr, lo 0x01,0x14,0x93,0x1a = csinc w1, w0, w19, ne 0xbf,0x04,0x89,0x1a = csinc wzr, w5, w9, eq 0xe9,0xc7,0x9e,0x1a = csinc w9, wzr, w30, gt 0x81,0x47,0x9f,0x1a = csinc w1, w28, wzr, mi 0xf3,0xb6,0x9d,0x9a = csinc x19, x23, x29, lt 0x7f,0xa4,0x84,0x9a = csinc xzr, x3, x4, ge 0xe5,0x27,0x86,0x9a = csinc x5, xzr, x6, hs 0x07,0x35,0x9f,0x9a = csinc x7, x8, xzr, lo 0x01,0x10,0x93,0x5a = csinv w1, w0, w19, ne 0xbf,0x00,0x89,0x5a = csinv wzr, w5, w9, eq 0xe9,0xc3,0x9e,0x5a = csinv w9, wzr, w30, gt 0x81,0x43,0x9f,0x5a = csinv w1, w28, wzr, mi 0xf3,0xb2,0x9d,0xda = csinv x19, x23, x29, lt 0x7f,0xa0,0x84,0xda = csinv xzr, x3, x4, ge 0xe5,0x23,0x86,0xda = csinv x5, xzr, x6, hs 0x07,0x31,0x9f,0xda = csinv x7, x8, xzr, lo 0x01,0x14,0x93,0x5a = csneg w1, w0, w19, ne 0xbf,0x04,0x89,0x5a = csneg wzr, w5, w9, eq 0xe9,0xc7,0x9e,0x5a = csneg w9, wzr, w30, gt 0x81,0x47,0x9f,0x5a = csneg w1, w28, wzr, mi 0xf3,0xb6,0x9d,0xda = csneg x19, x23, x29, lt 0x7f,0xa4,0x84,0xda = csneg xzr, x3, x4, ge 0xe5,0x27,0x86,0xda = csneg x5, xzr, x6, hs 0x07,0x35,0x9f,0xda = csneg x7, x8, xzr, lo // 0xe3,0x17,0x9f,0x1a = csinc w3, wzr, wzr, ne // 0xe9,0x47,0x9f,0x9a = csinc x9, xzr, xzr, mi // 0xf4,0x03,0x9f,0x5a = csinv w20, wzr, wzr, eq // 0xfe,0xb3,0x9f,0xda = csinv x30, xzr, xzr, lt // 0xa3,0xd4,0x85,0x1a = csinc w3, w5, w5, le // 0x9f,0xc4,0x84,0x1a = csinc wzr, w4, w4, gt // 0xe9,0xa7,0x9f,0x1a = csinc w9, wzr, wzr, ge // 0xa3,0xd4,0x85,0x9a = csinc x3, x5, x5, le // 0x9f,0xc4,0x84,0x9a = csinc xzr, x4, x4, gt // 0xe9,0xa7,0x9f,0x9a = csinc x9, xzr, xzr, ge // 0xa3,0xd0,0x85,0x5a = csinv w3, w5, w5, le // 0x9f,0xc0,0x84,0x5a = csinv wzr, w4, w4, gt // 0xe9,0xa3,0x9f,0x5a = csinv w9, wzr, wzr, ge // 0xa3,0xd0,0x85,0xda = csinv x3, x5, x5, le // 0x9f,0xc0,0x84,0xda = csinv xzr, x4, x4, gt // 0xe9,0xa3,0x9f,0xda = csinv x9, xzr, xzr, ge // 0xa3,0xd4,0x85,0x5a = csneg w3, w5, w5, le // 0x9f,0xc4,0x84,0x5a = csneg wzr, w4, w4, gt // 0xe9,0xa7,0x9f,0x5a = csneg w9, wzr, wzr, ge // 0xa3,0xd4,0x85,0xda = csneg x3, x5, x5, le // 0x9f,0xc4,0x84,0xda = csneg xzr, x4, x4, gt // 0xe9,0xa7,0x9f,0xda = csneg x9, xzr, xzr, ge 0xe0,0x00,0xc0,0x5a = rbit w0, w7 0x72,0x00,0xc0,0xda = rbit x18, x3 0x31,0x04,0xc0,0x5a = rev16 w17, w1 0x45,0x04,0xc0,0xda = rev16 x5, x2 0x12,0x08,0xc0,0x5a = rev w18, w0 0x34,0x08,0xc0,0xda = rev32 x20, x1 0xf4,0x0b,0xc0,0xda = rev32 x20, xzr 0x56,0x0c,0xc0,0xda = rev x22, x2 0xf2,0x0f,0xc0,0xda = rev x18, xzr 0xe7,0x0b,0xc0,0x5a = rev w7, wzr 0x78,0x10,0xc0,0x5a = clz w24, w3 0x9a,0x10,0xc0,0xda = clz x26, x4 0xa3,0x14,0xc0,0x5a = cls w3, w5 0xb4,0x14,0xc0,0xda = cls x20, x5 0xf8,0x13,0xc0,0x5a = clz w24, wzr 0xf6,0x0f,0xc0,0xda = rev x22, xzr 0xe5,0x40,0xd4,0x1a = crc32b w5, w7, w20 0xfc,0x47,0xde,0x1a = crc32h w28, wzr, w30 0x20,0x48,0xc2,0x1a = crc32w w0, w1, w2 0x27,0x4d,0xd4,0x9a = crc32x w7, w9, x20 0xa9,0x50,0xc4,0x1a = crc32cb w9, w5, w4 0x2d,0x56,0xd9,0x1a = crc32ch w13, w17, w25 0x7f,0x58,0xc5,0x1a = crc32cw wzr, w3, w5 0x12,0x5e,0xdf,0x9a = crc32cx w18, w16, xzr 0xe0,0x08,0xca,0x1a = udiv w0, w7, w10 0xc9,0x0a,0xc4,0x9a = udiv x9, x22, x4 0xac,0x0e,0xc0,0x1a = sdiv w12, w21, w0 0x4d,0x0c,0xc1,0x9a = sdiv x13, x2, x1 0x8b,0x21,0xcd,0x1a = lsl w11, w12, w13 0xee,0x21,0xd0,0x9a = lsl x14, x15, x16 0x51,0x26,0xd3,0x1a = lsr w17, w18, w19 0xb4,0x26,0xd6,0x9a = lsr x20, x21, x22 0x17,0x2b,0xd9,0x1a = asr w23, w24, w25 0x7a,0x2b,0xdc,0x9a = asr x26, x27, x28 0x20,0x2c,0xc2,0x1a = ror w0, w1, w2 0x83,0x2c,0xc5,0x9a = ror x3, x4, x5 0xe6,0x20,0xc8,0x1a = lsl w6, w7, w8 0x49,0x21,0xcb,0x9a = lsl x9, x10, x11 0xac,0x25,0xce,0x1a = lsr w12, w13, w14 0x0f,0x26,0xd1,0x9a = lsr x15, x16, x17 0x72,0x2a,0xd4,0x1a = asr w18, w19, w20 0xd5,0x2a,0xd7,0x9a = asr x21, x22, x23 0x38,0x2f,0xda,0x1a = ror w24, w25, w26 0x9b,0x2f,0xdd,0x9a = ror x27, x28, x29 0x61,0x10,0x07,0x1b = madd w1, w3, w7, w4 0x1f,0x2c,0x09,0x1b = madd wzr, w0, w9, w11 0xed,0x13,0x04,0x1b = madd w13, wzr, w4, w4 0xd3,0x77,0x1f,0x1b = madd w19, w30, wzr, w29 0xa4,0x7c,0x06,0x1b = mul w4, w5, w6 0x61,0x10,0x07,0x9b = madd x1, x3, x7, x4 0x1f,0x2c,0x09,0x9b = madd xzr, x0, x9, x11 0xed,0x13,0x04,0x9b = madd x13, xzr, x4, x4 0xd3,0x77,0x1f,0x9b = madd x19, x30, xzr, x29 0xa4,0x7c,0x06,0x9b = mul x4, x5, x6 0x61,0x90,0x07,0x1b = msub w1, w3, w7, w4 0x1f,0xac,0x09,0x1b = msub wzr, w0, w9, w11 0xed,0x93,0x04,0x1b = msub w13, wzr, w4, w4 0xd3,0xf7,0x1f,0x1b = msub w19, w30, wzr, w29 0xa4,0xfc,0x06,0x1b = mneg w4, w5, w6 0x61,0x90,0x07,0x9b = msub x1, x3, x7, x4 0x1f,0xac,0x09,0x9b = msub xzr, x0, x9, x11 0xed,0x93,0x04,0x9b = msub x13, xzr, x4, x4 0xd3,0xf7,0x1f,0x9b = msub x19, x30, xzr, x29 0xa4,0xfc,0x06,0x9b = mneg x4, x5, x6 0xa3,0x24,0x22,0x9b = smaddl x3, w5, w2, x9 0x5f,0x31,0x2b,0x9b = smaddl xzr, w10, w11, x12 0xed,0x3f,0x2e,0x9b = smaddl x13, wzr, w14, x15 0x30,0x4a,0x3f,0x9b = smaddl x16, w17, wzr, x18 0x93,0x7e,0x35,0x9b = smull x19, w20, w21 0xa3,0xa4,0x22,0x9b = smsubl x3, w5, w2, x9 0x5f,0xb1,0x2b,0x9b = smsubl xzr, w10, w11, x12 0xed,0xbf,0x2e,0x9b = smsubl x13, wzr, w14, x15 0x30,0xca,0x3f,0x9b = smsubl x16, w17, wzr, x18 0x93,0xfe,0x35,0x9b = smnegl x19, w20, w21 0xa3,0x24,0xa2,0x9b = umaddl x3, w5, w2, x9 0x5f,0x31,0xab,0x9b = umaddl xzr, w10, w11, x12 0xed,0x3f,0xae,0x9b = umaddl x13, wzr, w14, x15 0x30,0x4a,0xbf,0x9b = umaddl x16, w17, wzr, x18 0x93,0x7e,0xb5,0x9b = umull x19, w20, w21 0xa3,0xa4,0xa2,0x9b = umsubl x3, w5, w2, x9 0x5f,0xb1,0xab,0x9b = umsubl xzr, w10, w11, x12 0xed,0xbf,0xae,0x9b = umsubl x13, wzr, w14, x15 0x30,0xca,0xbf,0x9b = umsubl x16, w17, wzr, x18 0x93,0xfe,0xb5,0x9b = umnegl x19, w20, w21 0xbe,0x7f,0x5c,0x9b = smulh x30, x29, x28 0x7f,0x7f,0x5a,0x9b = smulh xzr, x27, x26 0xf9,0x7f,0x58,0x9b = smulh x25, xzr, x24 0xd7,0x7e,0x5f,0x9b = smulh x23, x22, xzr 0xbe,0x7f,0xdc,0x9b = umulh x30, x29, x28 0x7f,0x7f,0xda,0x9b = umulh xzr, x27, x26 0xf9,0x7f,0xd8,0x9b = umulh x25, xzr, x24 0xd7,0x7e,0xdf,0x9b = umulh x23, x22, xzr 0x83,0x7c,0x05,0x1b = mul w3, w4, w5 0xdf,0x7c,0x07,0x1b = mul wzr, w6, w7 0xe8,0x7f,0x09,0x1b = mul w8, wzr, w9 0x6a,0x7d,0x1f,0x1b = mul w10, w11, wzr 0xac,0x7d,0x0e,0x9b = mul x12, x13, x14 0xff,0x7d,0x10,0x9b = mul xzr, x15, x16 0xf1,0x7f,0x12,0x9b = mul x17, xzr, x18 0x93,0x7e,0x1f,0x9b = mul x19, x20, xzr 0xd5,0xfe,0x17,0x1b = mneg w21, w22, w23 0x1f,0xff,0x19,0x1b = mneg wzr, w24, w25 0xfa,0xff,0x1b,0x1b = mneg w26, wzr, w27 0xbc,0xff,0x1f,0x1b = mneg w28, w29, wzr 0xab,0x7d,0x31,0x9b = smull x11, w13, w17 0xab,0x7d,0xb1,0x9b = umull x11, w13, w17 0xab,0xfd,0x31,0x9b = smnegl x11, w13, w17 0xab,0xfd,0xb1,0x9b = umnegl x11, w13, w17 0x01,0x00,0x00,0xd4 = svc #0 0xe1,0xff,0x1f,0xd4 = svc #65535 0x22,0x00,0x00,0xd4 = hvc #1 0x03,0xdc,0x05,0xd4 = smc #12000 0x80,0x01,0x20,0xd4 = brk #12 0x60,0x0f,0x40,0xd4 = hlt #123 0x41,0x05,0xa0,0xd4 = dcps1 #42 0x22,0x01,0xa0,0xd4 = dcps2 #9 0x03,0x7d,0xa0,0xd4 = dcps3 #1000 0x01,0x00,0xa0,0xd4 = dcps1 0x02,0x00,0xa0,0xd4 = dcps2 0x03,0x00,0xa0,0xd4 = dcps3 0xa3,0x00,0x87,0x13 = extr w3, w5, w7, #0 0xab,0x7d,0x91,0x13 = extr w11, w13, w17, #31 0xa3,0x3c,0xc7,0x93 = extr x3, x5, x7, #15 0xab,0xfd,0xd1,0x93 = extr x11, x13, x17, #63 // 0xf3,0x62,0xd7,0x93 = extr x19, x23, x23, #24 // 0xfd,0xff,0xdf,0x93 = extr x29, xzr, xzr, #63 // 0xa9,0x7d,0x8d,0x13 = extr w9, w13, w13, #31 0x60,0x20,0x25,0x1e = fcmp s3, s5 0xe8,0x23,0x20,0x1e = fcmp s31, #0.0 0xb0,0x23,0x3e,0x1e = fcmpe s29, s30 0xf8,0x21,0x20,0x1e = fcmpe s15, #0.0 0x80,0x20,0x6c,0x1e = fcmp d4, d12 0xe8,0x22,0x60,0x1e = fcmp d23, #0.0 0x50,0x23,0x76,0x1e = fcmpe d26, d22 0xb8,0x23,0x60,0x1e = fcmpe d29, #0.0 0x20,0x04,0x3f,0x1e = fccmp s1, s31, #0, eq 0x6f,0x24,0x20,0x1e = fccmp s3, s0, #15, hs 0xed,0x27,0x2f,0x1e = fccmp s31, s15, #13, hs 0x20,0xd5,0x7f,0x1e = fccmp d9, d31, #0, le 0x6f,0xc4,0x60,0x1e = fccmp d3, d0, #15, gt 0xe7,0x17,0x65,0x1e = fccmp d31, d5, #7, ne 0x30,0x04,0x3f,0x1e = fccmpe s1, s31, #0, eq 0x7f,0x24,0x20,0x1e = fccmpe s3, s0, #15, hs 0xfd,0x27,0x2f,0x1e = fccmpe s31, s15, #13, hs 0x30,0xd5,0x7f,0x1e = fccmpe d9, d31, #0, le 0x7f,0xc4,0x60,0x1e = fccmpe d3, d0, #15, gt 0xf7,0x17,0x65,0x1e = fccmpe d31, d5, #7, ne 0x83,0x5e,0x29,0x1e = fcsel s3, s20, s9, pl 0x49,0x4d,0x6b,0x1e = fcsel d9, d10, d11, mi 0x20,0x40,0x20,0x1e = fmov s0, s1 0x62,0xc0,0x20,0x1e = fabs s2, s3 0xa4,0x40,0x21,0x1e = fneg s4, s5 0xe6,0xc0,0x21,0x1e = fsqrt s6, s7 0x28,0xc1,0x22,0x1e = fcvt d8, s9 0x6a,0xc1,0x23,0x1e = fcvt h10, s11 0xac,0x41,0x24,0x1e = frintn s12, s13 0xee,0xc1,0x24,0x1e = frintp s14, s15 0x30,0x42,0x25,0x1e = frintm s16, s17 0x72,0xc2,0x25,0x1e = frintz s18, s19 0xb4,0x42,0x26,0x1e = frinta s20, s21 0xf6,0x42,0x27,0x1e = frintx s22, s23 0x38,0xc3,0x27,0x1e = frinti s24, s25 0x20,0x40,0x60,0x1e = fmov d0, d1 0x62,0xc0,0x60,0x1e = fabs d2, d3 0xa4,0x40,0x61,0x1e = fneg d4, d5 0xe6,0xc0,0x61,0x1e = fsqrt d6, d7 0x28,0x41,0x62,0x1e = fcvt s8, d9 0x6a,0xc1,0x63,0x1e = fcvt h10, d11 0xac,0x41,0x64,0x1e = frintn d12, d13 0xee,0xc1,0x64,0x1e = frintp d14, d15 0x30,0x42,0x65,0x1e = frintm d16, d17 0x72,0xc2,0x65,0x1e = frintz d18, d19 0xb4,0x42,0x66,0x1e = frinta d20, d21 0xf6,0x42,0x67,0x1e = frintx d22, d23 0x38,0xc3,0x67,0x1e = frinti d24, d25 0x7a,0x43,0xe2,0x1e = fcvt s26, h27 0xbc,0xc3,0xe2,0x1e = fcvt d28, h29 0x74,0x0a,0x31,0x1e = fmul s20, s19, s17 0x41,0x18,0x23,0x1e = fdiv s1, s2, s3 0xa4,0x28,0x26,0x1e = fadd s4, s5, s6 0x07,0x39,0x29,0x1e = fsub s7, s8, s9 0x6a,0x49,0x2c,0x1e = fmax s10, s11, s12 0xcd,0x59,0x2f,0x1e = fmin s13, s14, s15 0x30,0x6a,0x32,0x1e = fmaxnm s16, s17, s18 0x93,0x7a,0x35,0x1e = fminnm s19, s20, s21 0xf6,0x8a,0x38,0x1e = fnmul s22, s23, s24 0x74,0x0a,0x71,0x1e = fmul d20, d19, d17 0x41,0x18,0x63,0x1e = fdiv d1, d2, d3 0xa4,0x28,0x66,0x1e = fadd d4, d5, d6 0x07,0x39,0x69,0x1e = fsub d7, d8, d9 0x6a,0x49,0x6c,0x1e = fmax d10, d11, d12 0xcd,0x59,0x6f,0x1e = fmin d13, d14, d15 0x30,0x6a,0x72,0x1e = fmaxnm d16, d17, d18 0x93,0x7a,0x75,0x1e = fminnm d19, d20, d21 0xf6,0x8a,0x78,0x1e = fnmul d22, d23, d24 0xa3,0x7c,0x06,0x1f = fmadd s3, s5, s6, s31 0xa3,0x5d,0x40,0x1f = fmadd d3, d13, d0, d23 0xa3,0xfc,0x06,0x1f = fmsub s3, s5, s6, s31 0xa3,0xdd,0x40,0x1f = fmsub d3, d13, d0, d23 0xa3,0x7c,0x26,0x1f = fnmadd s3, s5, s6, s31 0xa3,0x5d,0x60,0x1f = fnmadd d3, d13, d0, d23 0xa3,0xfc,0x26,0x1f = fnmsub s3, s5, s6, s31 0xa3,0xdd,0x60,0x1f = fnmsub d3, d13, d0, d23 0xa3,0xfc,0x18,0x1e = fcvtzs w3, s5, #1 0x9f,0xce,0x18,0x1e = fcvtzs wzr, s20, #13 0x13,0x80,0x18,0x1e = fcvtzs w19, s0, #32 0xa3,0xfc,0x18,0x9e = fcvtzs x3, s5, #1 0xcc,0x4f,0x18,0x9e = fcvtzs x12, s30, #45 0x13,0x00,0x18,0x9e = fcvtzs x19, s0, #64 0xa3,0xfc,0x58,0x1e = fcvtzs w3, d5, #1 0x9f,0xce,0x58,0x1e = fcvtzs wzr, d20, #13 0x13,0x80,0x58,0x1e = fcvtzs w19, d0, #32 0xa3,0xfc,0x58,0x9e = fcvtzs x3, d5, #1 0xcc,0x4f,0x58,0x9e = fcvtzs x12, d30, #45 0x13,0x00,0x58,0x9e = fcvtzs x19, d0, #64 0xa3,0xfc,0x19,0x1e = fcvtzu w3, s5, #1 0x9f,0xce,0x19,0x1e = fcvtzu wzr, s20, #13 0x13,0x80,0x19,0x1e = fcvtzu w19, s0, #32 0xa3,0xfc,0x19,0x9e = fcvtzu x3, s5, #1 0xcc,0x4f,0x19,0x9e = fcvtzu x12, s30, #45 0x13,0x00,0x19,0x9e = fcvtzu x19, s0, #64 0xa3,0xfc,0x59,0x1e = fcvtzu w3, d5, #1 0x9f,0xce,0x59,0x1e = fcvtzu wzr, d20, #13 0x13,0x80,0x59,0x1e = fcvtzu w19, d0, #32 0xa3,0xfc,0x59,0x9e = fcvtzu x3, d5, #1 0xcc,0x4f,0x59,0x9e = fcvtzu x12, d30, #45 0x13,0x00,0x59,0x9e = fcvtzu x19, d0, #64 0x77,0xfe,0x02,0x1e = scvtf s23, w19, #1 0xff,0xb3,0x02,0x1e = scvtf s31, wzr, #20 0x0e,0x80,0x02,0x1e = scvtf s14, w0, #32 0x77,0xfe,0x02,0x9e = scvtf s23, x19, #1 0xff,0xb3,0x02,0x9e = scvtf s31, xzr, #20 0x0e,0x00,0x02,0x9e = scvtf s14, x0, #64 0x77,0xfe,0x42,0x1e = scvtf d23, w19, #1 0xff,0xb3,0x42,0x1e = scvtf d31, wzr, #20 0x0e,0x80,0x42,0x1e = scvtf d14, w0, #32 0x77,0xfe,0x42,0x9e = scvtf d23, x19, #1 0xff,0xb3,0x42,0x9e = scvtf d31, xzr, #20 0x0e,0x00,0x42,0x9e = scvtf d14, x0, #64 0x77,0xfe,0x03,0x1e = ucvtf s23, w19, #1 0xff,0xb3,0x03,0x1e = ucvtf s31, wzr, #20 0x0e,0x80,0x03,0x1e = ucvtf s14, w0, #32 0x77,0xfe,0x03,0x9e = ucvtf s23, x19, #1 0xff,0xb3,0x03,0x9e = ucvtf s31, xzr, #20 0x0e,0x00,0x03,0x9e = ucvtf s14, x0, #64 0x77,0xfe,0x43,0x1e = ucvtf d23, w19, #1 0xff,0xb3,0x43,0x1e = ucvtf d31, wzr, #20 0x0e,0x80,0x43,0x1e = ucvtf d14, w0, #32 0x77,0xfe,0x43,0x9e = ucvtf d23, x19, #1 0xff,0xb3,0x43,0x9e = ucvtf d31, xzr, #20 0x0e,0x00,0x43,0x9e = ucvtf d14, x0, #64 0xe3,0x03,0x20,0x1e = fcvtns w3, s31 0x9f,0x01,0x20,0x9e = fcvtns xzr, s12 0x9f,0x01,0x21,0x1e = fcvtnu wzr, s12 0x00,0x00,0x21,0x9e = fcvtnu x0, s0 0x3f,0x01,0x28,0x1e = fcvtps wzr, s9 0x8c,0x02,0x28,0x9e = fcvtps x12, s20 0xfe,0x02,0x29,0x1e = fcvtpu w30, s23 0x7d,0x00,0x29,0x9e = fcvtpu x29, s3 0x62,0x00,0x30,0x1e = fcvtms w2, s3 0xa4,0x00,0x30,0x9e = fcvtms x4, s5 0xe6,0x00,0x31,0x1e = fcvtmu w6, s7 0x28,0x01,0x31,0x9e = fcvtmu x8, s9 0x6a,0x01,0x38,0x1e = fcvtzs w10, s11 0xac,0x01,0x38,0x9e = fcvtzs x12, s13 0xee,0x01,0x39,0x1e = fcvtzu w14, s15 0x0f,0x02,0x39,0x9e = fcvtzu x15, s16 0x51,0x02,0x22,0x1e = scvtf s17, w18 0x93,0x02,0x22,0x9e = scvtf s19, x20 0xd5,0x02,0x23,0x1e = ucvtf s21, w22 0x17,0x03,0x22,0x9e = scvtf s23, x24 0x59,0x03,0x24,0x1e = fcvtas w25, s26 0x9b,0x03,0x24,0x9e = fcvtas x27, s28 0xdd,0x03,0x25,0x1e = fcvtau w29, s30 0x1f,0x00,0x25,0x9e = fcvtau xzr, s0 0xe3,0x03,0x60,0x1e = fcvtns w3, d31 0x9f,0x01,0x60,0x9e = fcvtns xzr, d12 0x9f,0x01,0x61,0x1e = fcvtnu wzr, d12 0x00,0x00,0x61,0x9e = fcvtnu x0, d0 0x3f,0x01,0x68,0x1e = fcvtps wzr, d9 0x8c,0x02,0x68,0x9e = fcvtps x12, d20 0xfe,0x02,0x69,0x1e = fcvtpu w30, d23 0x7d,0x00,0x69,0x9e = fcvtpu x29, d3 0x62,0x00,0x70,0x1e = fcvtms w2, d3 0xa4,0x00,0x70,0x9e = fcvtms x4, d5 0xe6,0x00,0x71,0x1e = fcvtmu w6, d7 0x28,0x01,0x71,0x9e = fcvtmu x8, d9 0x6a,0x01,0x78,0x1e = fcvtzs w10, d11 0xac,0x01,0x78,0x9e = fcvtzs x12, d13 0xee,0x01,0x79,0x1e = fcvtzu w14, d15 0x0f,0x02,0x79,0x9e = fcvtzu x15, d16 0x51,0x02,0x62,0x1e = scvtf d17, w18 0x93,0x02,0x62,0x9e = scvtf d19, x20 0xd5,0x02,0x63,0x1e = ucvtf d21, w22 0x17,0x03,0x63,0x9e = ucvtf d23, x24 0x59,0x03,0x64,0x1e = fcvtas w25, d26 0x9b,0x03,0x64,0x9e = fcvtas x27, d28 0xdd,0x03,0x65,0x1e = fcvtau w29, d30 0x1f,0x00,0x65,0x9e = fcvtau xzr, d0 0x23,0x01,0x26,0x1e = fmov w3, s9 0x69,0x00,0x27,0x1e = fmov s9, w3 0xf4,0x03,0x66,0x9e = fmov x20, d31 0xe1,0x01,0x67,0x9e = fmov d1, x15 0x83,0x01,0xae,0x9e = fmov x3, v12.d[1] 0x61,0x02,0xaf,0x9e = fmov v1.d[1], x19 0xe3,0x03,0xaf,0x9e = fmov v3.d[1], xzr 0x02,0x10,0x28,0x1e = fmov s2, #0.12500000 0x03,0x10,0x2e,0x1e = fmov s3, #1.00000000 0x1e,0x10,0x66,0x1e = fmov d30, #16.00000000 0x04,0x30,0x2e,0x1e = fmov s4, #1.06250000 0x0a,0xf0,0x6f,0x1e = fmov d10, #1.93750000 0x0c,0x10,0x3e,0x1e = fmov s12, #-1.00000000 0x10,0x30,0x64,0x1e = fmov d16, #8.50000000 0xe0,0xff,0x7f,0x18 = ldr w0, #1048572 0x0a,0x00,0x80,0x58 = ldr x10, #-1048576 0x02,0x10,0x28,0x1e = fmov s2, #0.12500000 0x03,0x10,0x2e,0x1e = fmov s3, #1.00000000 0x1e,0x10,0x66,0x1e = fmov d30, #16.00000000 0x04,0x30,0x2e,0x1e = fmov s4, #1.06250000 0x0a,0xf0,0x6f,0x1e = fmov d10, #1.93750000 0x0c,0x10,0x3e,0x1e = fmov s12, #-1.00000000 0x10,0x30,0x64,0x1e = fmov d16, #8.50000000 0x62,0x7c,0x01,0x08 = stxrb w1, w2, [x3] 0x83,0x7c,0x02,0x48 = stxrh w2, w3, [x4] 0xe4,0x7f,0x1f,0x88 = stxr wzr, w4, [sp] 0xe6,0x7c,0x05,0xc8 = stxr w5, x6, [x7] 0x27,0x7d,0x5f,0x08 = ldxrb w7, [x9] 0x5f,0x7d,0x5f,0x48 = ldxrh wzr, [x10] 0xe9,0x7f,0x5f,0x88 = ldxr w9, [sp] 0x6a,0x7d,0x5f,0xc8 = ldxr x10, [x11] 0xcc,0x35,0x2b,0x88 = stxp w11, w12, w13, [x14] 0xf7,0x39,0x3f,0xc8 = stxp wzr, x23, x14, [x15] 0xec,0x7f,0x7f,0x88 = ldxp w12, wzr, [sp] 0xed,0x39,0x7f,0xc8 = ldxp x13, x14, [x15] 0x0f,0xfe,0x0e,0x08 = stlxrb w14, w15, [x16] 0x30,0xfe,0x0f,0x48 = stlxrh w15, w16, [x17] 0xf1,0xff,0x1f,0x88 = stlxr wzr, w17, [sp] 0x93,0xfe,0x12,0xc8 = stlxr w18, x19, [x20] 0xb3,0xfe,0x5f,0x08 = ldaxrb w19, [x21] 0xf4,0xff,0x5f,0x48 = ldaxrh w20, [sp] 0xdf,0xfe,0x5f,0x88 = ldaxr wzr, [x22] 0xf5,0xfe,0x5f,0xc8 = ldaxr x21, [x23] 0x16,0xdf,0x3f,0x88 = stlxp wzr, w22, w23, [x24] 0xfa,0xef,0x39,0xc8 = stlxp w25, x26, x27, [sp] 0xfa,0xff,0x7f,0x88 = ldaxp w26, wzr, [sp] 0xdb,0xf3,0x7f,0xc8 = ldaxp x27, x28, [x30] 0xfb,0xff,0x9f,0x08 = stlrb w27, [sp] 0x1c,0xfc,0x9f,0x48 = stlrh w28, [x0] 0x3f,0xfc,0x9f,0x88 = stlr wzr, [x1] 0x5e,0xfc,0x9f,0xc8 = stlr x30, [x2] 0xfd,0xff,0xdf,0x08 = ldarb w29, [sp] 0x1e,0xfc,0xdf,0x48 = ldarh w30, [x0] 0x3f,0xfc,0xdf,0x88 = ldar wzr, [x1] 0x41,0xfc,0xdf,0xc8 = ldar x1, [x2] 0x16,0xdf,0x3f,0x88 = stlxp wzr, w22, w23, [x24] 0xe9,0x03,0x00,0x38 = sturb w9, [sp] 0x9f,0xf1,0x0f,0x78 = sturh wzr, [x12, #255] 0x10,0x00,0x10,0xb8 = stur w16, [x0, #-256] 0xdc,0x11,0x00,0xf8 = stur x28, [x14, #1] 0x81,0xf2,0x4f,0x38 = ldurb w1, [x20, #255] 0x34,0xf0,0x4f,0x78 = ldurh w20, [x1, #255] 0xec,0xf3,0x4f,0xb8 = ldur w12, [sp, #255] 0x9f,0xf1,0x4f,0xf8 = ldur xzr, [x12, #255] 0xe9,0x00,0x90,0x38 = ldursb x9, [x7, #-256] 0x71,0x02,0x90,0x78 = ldursh x17, [x19, #-256] 0xf4,0x01,0x90,0xb8 = ldursw x20, [x15, #-256] 0x4d,0x00,0x80,0xb8 = ldursw x13, [x2] 0xe2,0x03,0x90,0xf8 = prfum pldl2keep, [sp, #-256] 0x33,0x00,0xd0,0x38 = ldursb w19, [x1, #-256] 0xaf,0x02,0xd0,0x78 = ldursh w15, [x21, #-256] 0xe0,0x13,0x00,0x3c = stur b0, [sp, #1] 0x8c,0xf1,0x1f,0x7c = stur h12, [x12, #-1] 0x0f,0xf0,0x0f,0xbc = stur s15, [x0, #255] 0xbf,0x90,0x01,0xfc = stur d31, [x5, #25] 0xa9,0x00,0x80,0x3c = stur q9, [x5] 0xe3,0x03,0x40,0x3c = ldur b3, [sp] 0x85,0x00,0x50,0x7c = ldur h5, [x4, #-256] 0x87,0xf1,0x5f,0xbc = ldur s7, [x12, #-1] 0x6b,0x42,0x40,0xfc = ldur d11, [x19, #4] 0x2d,0x20,0xc0,0x3c = ldur q13, [x1, #2] 0x00,0x00,0x40,0xf9 = ldr x0, [x0] 0xa4,0x03,0x40,0xf9 = ldr x4, [x29] 0x9e,0xfd,0x7f,0xf9 = ldr x30, [x12, #32760] 0xf4,0x07,0x40,0xf9 = ldr x20, [sp, #8] 0xff,0x03,0x40,0xf9 = ldr xzr, [sp] 0xe2,0x03,0x40,0xb9 = ldr w2, [sp] // 0xf1,0xff,0x7f,0xb9 = ldr w17, [sp, #0x6660] 0x4d,0x04,0x40,0xb9 = ldr w13, [x2, #4] 0xa2,0x04,0x80,0xb9 = ldrsw x2, [x5, #4] // 0xf7,0xff,0xbf,0xb9 = ldrsw x23, [sp, #0x6660] 0x82,0x00,0x40,0x79 = ldrh w2, [x4] 0xd7,0xfc,0xff,0x79 = ldrsh w23, [x6, #8190] 0xff,0x07,0xc0,0x79 = ldrsh wzr, [sp, #2] 0x5d,0x04,0x80,0x79 = ldrsh x29, [x2, #2] 0x7a,0xe4,0x41,0x39 = ldrb w26, [x3, #121] 0x4c,0x00,0x40,0x39 = ldrb w12, [x2] 0xfb,0xff,0xff,0x39 = ldrsb w27, [sp, #0xfff] 0xff,0x01,0x80,0x39 = ldrsb xzr, [x15] 0xfe,0x03,0x00,0xf9 = str x30, [sp] // 0x94,0xfc,0x3f,0xb9 = str w20, [x4, #0x6660] 0x54,0x1d,0x00,0x79 = strh w20, [x10, #14] 0xf1,0xff,0x3f,0x79 = strh w17, [sp, #8190] 0x77,0xfc,0x3f,0x39 = strb w23, [x3, #0xfff] 0x5f,0x00,0x00,0x39 = strb wzr, [x2] 0xe0,0x07,0x80,0xf9 = prfm pldl1keep, [sp, #8] // 0x61,0x00,0x80,0xf9 = prfm pldl1strm, [x3, #0] 0xa2,0x08,0x80,0xf9 = prfm pldl2keep, [x5, #16] // 0x43,0x00,0x80,0xf9 = prfm pldl2strm, [x2, #0] // 0xa4,0x00,0x80,0xf9 = prfm pldl3keep, [x5, #0] // 0xc5,0x00,0x80,0xf9 = prfm pldl3strm, [x6, #0] 0xe8,0x07,0x80,0xf9 = prfm plil1keep, [sp, #8] // 0x69,0x00,0x80,0xf9 = prfm plil1strm, [x3, #0] 0xaa,0x08,0x80,0xf9 = prfm plil2keep, [x5, #16] // 0x4b,0x00,0x80,0xf9 = prfm plil2strm, [x2, #0] // 0xac,0x00,0x80,0xf9 = prfm plil3keep, [x5, #0] // 0xcd,0x00,0x80,0xf9 = prfm plil3strm, [x6, #0] 0xf0,0x07,0x80,0xf9 = prfm pstl1keep, [sp, #8] // 0x71,0x00,0x80,0xf9 = prfm pstl1strm, [x3, #0] 0xb2,0x08,0x80,0xf9 = prfm pstl2keep, [x5, #16] // 0x53,0x00,0x80,0xf9 = prfm pstl2strm, [x2, #0] // 0xb4,0x00,0x80,0xf9 = prfm pstl3keep, [x5, #0] // 0xd5,0x00,0x80,0xf9 = prfm pstl3strm, [x6, #0] // 0xef,0x03,0x80,0xf9 = prfm #15, [sp, #0] 0xff,0xff,0x7f,0x3d = ldr b31, [sp, #0xfff] 0x54,0xfc,0x7f,0x7d = ldr h20, [x2, #8190] // 0x6a,0xfe,0x7f,0xbd = ldr s10, [x19, #0x6660] 0x43,0xfd,0x7f,0xfd = ldr d3, [x10, #32760] 0xec,0xff,0xbf,0x3d = str q12, [sp, #65520] 0xe3,0x6b,0x65,0x38 = ldrb w3, [sp, x5] 0x69,0x7b,0x66,0x38 = ldrb w9, [x27, x6, lsl #0] 0xca,0x6b,0xe7,0x38 = ldrsb w10, [x30, x7] 0xab,0xeb,0x63,0x38 = ldrb w11, [x29, x3, sxtx] 0x8c,0xfb,0x3f,0x38 = strb w12, [x28, xzr, sxtx #0] 0x4e,0x4b,0x66,0x38 = ldrb w14, [x26, w6, uxtw] 0x2f,0x5b,0xe7,0x38 = ldrsb w15, [x25, w7, uxtw #0] 0xf1,0xca,0x69,0x38 = ldrb w17, [x23, w9, sxtw] 0xd2,0xda,0xaa,0x38 = ldrsb x18, [x22, w10, sxtw #0] 0xe3,0x6b,0xe5,0x78 = ldrsh w3, [sp, x5] 0x69,0x6b,0xe6,0x78 = ldrsh w9, [x27, x6] 0xca,0x7b,0x67,0x78 = ldrh w10, [x30, x7, lsl #1] 0xab,0xeb,0x23,0x78 = strh w11, [x29, x3, sxtx] 0x8c,0xeb,0x7f,0x78 = ldrh w12, [x28, xzr, sxtx] 0x6d,0xfb,0xa5,0x78 = ldrsh x13, [x27, x5, sxtx #1] 0x4e,0x4b,0x66,0x78 = ldrh w14, [x26, w6, uxtw] 0x2f,0x4b,0x67,0x78 = ldrh w15, [x25, w7, uxtw] 0x10,0x5b,0xe8,0x78 = ldrsh w16, [x24, w8, uxtw #1] 0xf1,0xca,0x69,0x78 = ldrh w17, [x23, w9, sxtw] 0xd2,0xca,0x6a,0x78 = ldrh w18, [x22, w10, sxtw] 0xb3,0xda,0x3f,0x78 = strh w19, [x21, wzr, sxtw #1] 0xe3,0x6b,0x65,0xb8 = ldr w3, [sp, x5] 0x69,0x6b,0x66,0xbc = ldr s9, [x27, x6] 0xca,0x7b,0x67,0xb8 = ldr w10, [x30, x7, lsl #2] 0xab,0xeb,0x63,0xb8 = ldr w11, [x29, x3, sxtx] 0x8c,0xeb,0x3f,0xbc = str s12, [x28, xzr, sxtx] 0x6d,0xfb,0x25,0xb8 = str w13, [x27, x5, sxtx #2] 0x4e,0x4b,0x26,0xb8 = str w14, [x26, w6, uxtw] 0x2f,0x4b,0x67,0xb8 = ldr w15, [x25, w7, uxtw] 0x10,0x5b,0x68,0xb8 = ldr w16, [x24, w8, uxtw #2] 0xf1,0xca,0xa9,0xb8 = ldrsw x17, [x23, w9, sxtw] 0xd2,0xca,0x6a,0xb8 = ldr w18, [x22, w10, sxtw] 0xb3,0xda,0xbf,0xb8 = ldrsw x19, [x21, wzr, sxtw #2] 0xe3,0x6b,0x65,0xf8 = ldr x3, [sp, x5] 0x69,0x6b,0x26,0xf8 = str x9, [x27, x6] 0xca,0x7b,0x67,0xfc = ldr d10, [x30, x7, lsl #3] 0xab,0xeb,0x23,0xf8 = str x11, [x29, x3, sxtx] 0x8c,0xeb,0x7f,0xf8 = ldr x12, [x28, xzr, sxtx] 0x6d,0xfb,0x65,0xf8 = ldr x13, [x27, x5, sxtx #3] 0x40,0x4b,0xa6,0xf8 = prfm pldl1keep, [x26, w6, uxtw] 0x2f,0x4b,0x67,0xf8 = ldr x15, [x25, w7, uxtw] 0x10,0x5b,0x68,0xf8 = ldr x16, [x24, w8, uxtw #3] 0xf1,0xca,0x69,0xf8 = ldr x17, [x23, w9, sxtw] 0xd2,0xca,0x6a,0xf8 = ldr x18, [x22, w10, sxtw] 0xb3,0xda,0x3f,0xfc = str d19, [x21, wzr, sxtw #3] // 0x06,0x68,0xa5,0xf8 = prfm #6, [x0, x5, lsl #0] 0xe3,0x6b,0xe5,0x3c = ldr q3, [sp, x5] 0x69,0x6b,0xe6,0x3c = ldr q9, [x27, x6] 0xca,0x7b,0xe7,0x3c = ldr q10, [x30, x7, lsl #4] 0xab,0xeb,0xa3,0x3c = str q11, [x29, x3, sxtx] 0x8c,0xeb,0xbf,0x3c = str q12, [x28, xzr, sxtx] 0x6d,0xfb,0xa5,0x3c = str q13, [x27, x5, sxtx #4] 0x4e,0x4b,0xe6,0x3c = ldr q14, [x26, w6, uxtw] 0x2f,0x4b,0xe7,0x3c = ldr q15, [x25, w7, uxtw] 0x10,0x5b,0xe8,0x3c = ldr q16, [x24, w8, uxtw #4] 0xf1,0xca,0xe9,0x3c = ldr q17, [x23, w9, sxtw] 0xd2,0xca,0xaa,0x3c = str q18, [x22, w10, sxtw] 0xb3,0xda,0xff,0x3c = ldr q19, [x21, wzr, sxtw #4] 0x49,0xf4,0x0f,0x38 = strb w9, [x2], #255 0x6a,0x14,0x00,0x38 = strb w10, [x3], #1 0x6a,0x04,0x10,0x38 = strb w10, [x3], #-256 0x49,0xf4,0x0f,0x78 = strh w9, [x2], #255 0x49,0x14,0x00,0x78 = strh w9, [x2], #1 0x6a,0x04,0x10,0x78 = strh w10, [x3], #-256 0xf3,0xf7,0x0f,0xb8 = str w19, [sp], #255 0xd4,0x17,0x00,0xb8 = str w20, [x30], #1 0x95,0x05,0x10,0xb8 = str w21, [x12], #-256 0x3f,0xf5,0x0f,0xf8 = str xzr, [x9], #255 0x62,0x14,0x00,0xf8 = str x2, [x3], #1 0x93,0x05,0x10,0xf8 = str x19, [x12], #-256 0x49,0xf4,0x4f,0x38 = ldrb w9, [x2], #255 0x6a,0x14,0x40,0x38 = ldrb w10, [x3], #1 0x6a,0x04,0x50,0x38 = ldrb w10, [x3], #-256 0x49,0xf4,0x4f,0x78 = ldrh w9, [x2], #255 0x49,0x14,0x40,0x78 = ldrh w9, [x2], #1 0x6a,0x04,0x50,0x78 = ldrh w10, [x3], #-256 0xf3,0xf7,0x4f,0xb8 = ldr w19, [sp], #255 0xd4,0x17,0x40,0xb8 = ldr w20, [x30], #1 0x95,0x05,0x50,0xb8 = ldr w21, [x12], #-256 0x3f,0xf5,0x4f,0xf8 = ldr xzr, [x9], #255 0x62,0x14,0x40,0xf8 = ldr x2, [x3], #1 0x93,0x05,0x50,0xf8 = ldr x19, [x12], #-256 0x3f,0xf5,0x8f,0x38 = ldrsb xzr, [x9], #255 0x62,0x14,0x80,0x38 = ldrsb x2, [x3], #1 0x93,0x05,0x90,0x38 = ldrsb x19, [x12], #-256 0x3f,0xf5,0x8f,0x78 = ldrsh xzr, [x9], #255 0x62,0x14,0x80,0x78 = ldrsh x2, [x3], #1 0x93,0x05,0x90,0x78 = ldrsh x19, [x12], #-256 0x3f,0xf5,0x8f,0xb8 = ldrsw xzr, [x9], #255 0x62,0x14,0x80,0xb8 = ldrsw x2, [x3], #1 0x93,0x05,0x90,0xb8 = ldrsw x19, [x12], #-256 0x3f,0xf5,0xcf,0x38 = ldrsb wzr, [x9], #255 0x62,0x14,0xc0,0x38 = ldrsb w2, [x3], #1 0x93,0x05,0xd0,0x38 = ldrsb w19, [x12], #-256 0x3f,0xf5,0xcf,0x78 = ldrsh wzr, [x9], #255 0x62,0x14,0xc0,0x78 = ldrsh w2, [x3], #1 0x93,0x05,0xd0,0x78 = ldrsh w19, [x12], #-256 0x00,0xf4,0x0f,0x3c = str b0, [x0], #255 0x63,0x14,0x00,0x3c = str b3, [x3], #1 0xe5,0x07,0x10,0x3c = str b5, [sp], #-256 0x4a,0xf5,0x0f,0x7c = str h10, [x10], #255 0xed,0x16,0x00,0x7c = str h13, [x23], #1 0xef,0x07,0x10,0x7c = str h15, [sp], #-256 0x94,0xf6,0x0f,0xbc = str s20, [x20], #255 0xf7,0x16,0x00,0xbc = str s23, [x23], #1 0x19,0x04,0x10,0xbc = str s25, [x0], #-256 0x94,0xf6,0x0f,0xfc = str d20, [x20], #255 0xf7,0x16,0x00,0xfc = str d23, [x23], #1 0x19,0x04,0x10,0xfc = str d25, [x0], #-256 0x00,0xf4,0x4f,0x3c = ldr b0, [x0], #255 0x63,0x14,0x40,0x3c = ldr b3, [x3], #1 0xe5,0x07,0x50,0x3c = ldr b5, [sp], #-256 0x4a,0xf5,0x4f,0x7c = ldr h10, [x10], #255 0xed,0x16,0x40,0x7c = ldr h13, [x23], #1 0xef,0x07,0x50,0x7c = ldr h15, [sp], #-256 0x94,0xf6,0x4f,0xbc = ldr s20, [x20], #255 0xf7,0x16,0x40,0xbc = ldr s23, [x23], #1 0x19,0x04,0x50,0xbc = ldr s25, [x0], #-256 0x94,0xf6,0x4f,0xfc = ldr d20, [x20], #255 0xf7,0x16,0x40,0xfc = ldr d23, [x23], #1 0x19,0x04,0x50,0xfc = ldr d25, [x0], #-256 0x34,0xf4,0xcf,0x3c = ldr q20, [x1], #255 0x37,0x15,0xc0,0x3c = ldr q23, [x9], #1 0x99,0x06,0xd0,0x3c = ldr q25, [x20], #-256 0x2a,0xf4,0x8f,0x3c = str q10, [x1], #255 0xf6,0x17,0x80,0x3c = str q22, [sp], #1 0x95,0x06,0x90,0x3c = str q21, [x20], #-256 0x83,0x0c,0x40,0xf8 = ldr x3, [x4, #0]! 0xff,0x0f,0x40,0xf8 = ldr xzr, [sp, #0]! 0x49,0xfc,0x0f,0x38 = strb w9, [x2, #255]! 0x6a,0x1c,0x00,0x38 = strb w10, [x3, #1]! 0x6a,0x0c,0x10,0x38 = strb w10, [x3, #-256]! 0x49,0xfc,0x0f,0x78 = strh w9, [x2, #255]! 0x49,0x1c,0x00,0x78 = strh w9, [x2, #1]! 0x6a,0x0c,0x10,0x78 = strh w10, [x3, #-256]! 0xf3,0xff,0x0f,0xb8 = str w19, [sp, #255]! 0xd4,0x1f,0x00,0xb8 = str w20, [x30, #1]! 0x95,0x0d,0x10,0xb8 = str w21, [x12, #-256]! 0x3f,0xfd,0x0f,0xf8 = str xzr, [x9, #255]! 0x62,0x1c,0x00,0xf8 = str x2, [x3, #1]! 0x93,0x0d,0x10,0xf8 = str x19, [x12, #-256]! 0x49,0xfc,0x4f,0x38 = ldrb w9, [x2, #255]! 0x6a,0x1c,0x40,0x38 = ldrb w10, [x3, #1]! 0x6a,0x0c,0x50,0x38 = ldrb w10, [x3, #-256]! 0x49,0xfc,0x4f,0x78 = ldrh w9, [x2, #255]! 0x49,0x1c,0x40,0x78 = ldrh w9, [x2, #1]! 0x6a,0x0c,0x50,0x78 = ldrh w10, [x3, #-256]! 0xf3,0xff,0x4f,0xb8 = ldr w19, [sp, #255]! 0xd4,0x1f,0x40,0xb8 = ldr w20, [x30, #1]! 0x95,0x0d,0x50,0xb8 = ldr w21, [x12, #-256]! 0x3f,0xfd,0x4f,0xf8 = ldr xzr, [x9, #255]! 0x62,0x1c,0x40,0xf8 = ldr x2, [x3, #1]! 0x93,0x0d,0x50,0xf8 = ldr x19, [x12, #-256]! 0x3f,0xfd,0x8f,0x38 = ldrsb xzr, [x9, #255]! 0x62,0x1c,0x80,0x38 = ldrsb x2, [x3, #1]! 0x93,0x0d,0x90,0x38 = ldrsb x19, [x12, #-256]! 0x3f,0xfd,0x8f,0x78 = ldrsh xzr, [x9, #255]! 0x62,0x1c,0x80,0x78 = ldrsh x2, [x3, #1]! 0x93,0x0d,0x90,0x78 = ldrsh x19, [x12, #-256]! 0x3f,0xfd,0x8f,0xb8 = ldrsw xzr, [x9, #255]! 0x62,0x1c,0x80,0xb8 = ldrsw x2, [x3, #1]! 0x93,0x0d,0x90,0xb8 = ldrsw x19, [x12, #-256]! 0x3f,0xfd,0xcf,0x38 = ldrsb wzr, [x9, #255]! 0x62,0x1c,0xc0,0x38 = ldrsb w2, [x3, #1]! 0x93,0x0d,0xd0,0x38 = ldrsb w19, [x12, #-256]! 0x3f,0xfd,0xcf,0x78 = ldrsh wzr, [x9, #255]! 0x62,0x1c,0xc0,0x78 = ldrsh w2, [x3, #1]! 0x93,0x0d,0xd0,0x78 = ldrsh w19, [x12, #-256]! 0x00,0xfc,0x0f,0x3c = str b0, [x0, #255]! 0x63,0x1c,0x00,0x3c = str b3, [x3, #1]! 0xe5,0x0f,0x10,0x3c = str b5, [sp, #-256]! 0x4a,0xfd,0x0f,0x7c = str h10, [x10, #255]! 0xed,0x1e,0x00,0x7c = str h13, [x23, #1]! 0xef,0x0f,0x10,0x7c = str h15, [sp, #-256]! 0x94,0xfe,0x0f,0xbc = str s20, [x20, #255]! 0xf7,0x1e,0x00,0xbc = str s23, [x23, #1]! 0x19,0x0c,0x10,0xbc = str s25, [x0, #-256]! 0x94,0xfe,0x0f,0xfc = str d20, [x20, #255]! 0xf7,0x1e,0x00,0xfc = str d23, [x23, #1]! 0x19,0x0c,0x10,0xfc = str d25, [x0, #-256]! 0x00,0xfc,0x4f,0x3c = ldr b0, [x0, #255]! 0x63,0x1c,0x40,0x3c = ldr b3, [x3, #1]! 0xe5,0x0f,0x50,0x3c = ldr b5, [sp, #-256]! 0x4a,0xfd,0x4f,0x7c = ldr h10, [x10, #255]! 0xed,0x1e,0x40,0x7c = ldr h13, [x23, #1]! 0xef,0x0f,0x50,0x7c = ldr h15, [sp, #-256]! 0x94,0xfe,0x4f,0xbc = ldr s20, [x20, #255]! 0xf7,0x1e,0x40,0xbc = ldr s23, [x23, #1]! 0x19,0x0c,0x50,0xbc = ldr s25, [x0, #-256]! 0x94,0xfe,0x4f,0xfc = ldr d20, [x20, #255]! 0xf7,0x1e,0x40,0xfc = ldr d23, [x23, #1]! 0x19,0x0c,0x50,0xfc = ldr d25, [x0, #-256]! 0x34,0xfc,0xcf,0x3c = ldr q20, [x1, #255]! 0x37,0x1d,0xc0,0x3c = ldr q23, [x9, #1]! 0x99,0x0e,0xd0,0x3c = ldr q25, [x20, #-256]! 0x2a,0xfc,0x8f,0x3c = str q10, [x1, #255]! 0xf6,0x1f,0x80,0x3c = str q22, [sp, #1]! 0x95,0x0e,0x90,0x3c = str q21, [x20, #-256]! 0xe9,0x0b,0x00,0x38 = sttrb w9, [sp] 0x9f,0xf9,0x0f,0x78 = sttrh wzr, [x12, #255] 0x10,0x08,0x10,0xb8 = sttr w16, [x0, #-256] 0xdc,0x19,0x00,0xf8 = sttr x28, [x14, #1] 0x81,0xfa,0x4f,0x38 = ldtrb w1, [x20, #255] 0x34,0xf8,0x4f,0x78 = ldtrh w20, [x1, #255] 0xec,0xfb,0x4f,0xb8 = ldtr w12, [sp, #255] 0x9f,0xf9,0x4f,0xf8 = ldtr xzr, [x12, #255] 0xe9,0x08,0x90,0x38 = ldtrsb x9, [x7, #-256] 0x71,0x0a,0x90,0x78 = ldtrsh x17, [x19, #-256] 0xf4,0x09,0x90,0xb8 = ldtrsw x20, [x15, #-256] 0x33,0x08,0xd0,0x38 = ldtrsb w19, [x1, #-256] 0xaf,0x0a,0xd0,0x78 = ldtrsh w15, [x21, #-256] 0xe3,0x17,0x40,0x29 = ldp w3, w5, [sp] 0xff,0xa7,0x1f,0x29 = stp wzr, w9, [sp, #252] 0xe2,0x7f,0x60,0x29 = ldp w2, wzr, [sp, #-256] 0xe9,0xab,0x40,0x29 = ldp w9, w10, [sp, #4] 0xe9,0xab,0x40,0x69 = ldpsw x9, x10, [sp, #4] 0x49,0x28,0x60,0x69 = ldpsw x9, x10, [x2, #-256] 0xf4,0xfb,0x5f,0x69 = ldpsw x20, x30, [sp, #252] 0x55,0xf4,0x5f,0xa9 = ldp x21, x29, [x2, #504] 0x76,0x5c,0x60,0xa9 = ldp x22, x23, [x3, #-512] 0x98,0xe4,0x40,0xa9 = ldp x24, x25, [x4, #8] 0xfd,0xf3,0x5f,0x2d = ldp s29, s28, [sp, #252] 0xfb,0x6b,0x20,0x2d = stp s27, s26, [sp, #-256] 0x61,0x88,0x45,0x2d = ldp s1, s2, [x3, #44] 0x23,0x95,0x1f,0x6d = stp d3, d5, [x9, #504] 0x47,0x2d,0x20,0x6d = stp d7, d11, [x10, #-512] 0xc2,0x8f,0x7f,0x6d = ldp d2, d3, [x30, #-8] 0xe3,0x17,0x00,0xad = stp q3, q5, [sp] 0xf1,0xcf,0x1f,0xad = stp q17, q19, [sp, #1008] 0x37,0x74,0x60,0xad = ldp q23, q29, [x1, #-1024] 0xe3,0x17,0xc0,0x28 = ldp w3, w5, [sp], #0 0xff,0xa7,0x9f,0x28 = stp wzr, w9, [sp], #252 0xe2,0x7f,0xe0,0x28 = ldp w2, wzr, [sp], #-256 0xe9,0xab,0xc0,0x28 = ldp w9, w10, [sp], #4 0xe9,0xab,0xc0,0x68 = ldpsw x9, x10, [sp], #4 0x49,0x28,0xe0,0x68 = ldpsw x9, x10, [x2], #-256 0xf4,0xfb,0xdf,0x68 = ldpsw x20, x30, [sp], #252 0x55,0xf4,0xdf,0xa8 = ldp x21, x29, [x2], #504 0x76,0x5c,0xe0,0xa8 = ldp x22, x23, [x3], #-512 0x98,0xe4,0xc0,0xa8 = ldp x24, x25, [x4], #8 0xfd,0xf3,0xdf,0x2c = ldp s29, s28, [sp], #252 0xfb,0x6b,0xa0,0x2c = stp s27, s26, [sp], #-256 0x61,0x88,0xc5,0x2c = ldp s1, s2, [x3], #44 0x23,0x95,0x9f,0x6c = stp d3, d5, [x9], #504 0x47,0x2d,0xa0,0x6c = stp d7, d11, [x10], #-512 0xc2,0x8f,0xff,0x6c = ldp d2, d3, [x30], #-8 0xe3,0x17,0x80,0xac = stp q3, q5, [sp], #0 0xf1,0xcf,0x9f,0xac = stp q17, q19, [sp], #1008 0x37,0x74,0xe0,0xac = ldp q23, q29, [x1], #-1024 0xe3,0x17,0xc0,0x29 = ldp w3, w5, [sp, #0]! 0xff,0xa7,0x9f,0x29 = stp wzr, w9, [sp, #252]! 0xe2,0x7f,0xe0,0x29 = ldp w2, wzr, [sp, #-256]! 0xe9,0xab,0xc0,0x29 = ldp w9, w10, [sp, #4]! 0xe9,0xab,0xc0,0x69 = ldpsw x9, x10, [sp, #4]! 0x49,0x28,0xe0,0x69 = ldpsw x9, x10, [x2, #-256]! 0xf4,0xfb,0xdf,0x69 = ldpsw x20, x30, [sp, #252]! 0x55,0xf4,0xdf,0xa9 = ldp x21, x29, [x2, #504]! 0x76,0x5c,0xe0,0xa9 = ldp x22, x23, [x3, #-512]! 0x98,0xe4,0xc0,0xa9 = ldp x24, x25, [x4, #8]! 0xfd,0xf3,0xdf,0x2d = ldp s29, s28, [sp, #252]! 0xfb,0x6b,0xa0,0x2d = stp s27, s26, [sp, #-256]! 0x61,0x88,0xc5,0x2d = ldp s1, s2, [x3, #44]! 0x23,0x95,0x9f,0x6d = stp d3, d5, [x9, #504]! 0x47,0x2d,0xa0,0x6d = stp d7, d11, [x10, #-512]! 0xc2,0x8f,0xff,0x6d = ldp d2, d3, [x30, #-8]! 0xe3,0x17,0x80,0xad = stp q3, q5, [sp, #0]! 0xf1,0xcf,0x9f,0xad = stp q17, q19, [sp, #1008]! 0x37,0x74,0xe0,0xad = ldp q23, q29, [x1, #-1024]! 0xe3,0x17,0x40,0x28 = ldnp w3, w5, [sp] 0xff,0xa7,0x1f,0x28 = stnp wzr, w9, [sp, #252] 0xe2,0x7f,0x60,0x28 = ldnp w2, wzr, [sp, #-256] 0xe9,0xab,0x40,0x28 = ldnp w9, w10, [sp, #4] 0x55,0xf4,0x5f,0xa8 = ldnp x21, x29, [x2, #504] 0x76,0x5c,0x60,0xa8 = ldnp x22, x23, [x3, #-512] 0x98,0xe4,0x40,0xa8 = ldnp x24, x25, [x4, #8] 0xfd,0xf3,0x5f,0x2c = ldnp s29, s28, [sp, #252] 0xfb,0x6b,0x20,0x2c = stnp s27, s26, [sp, #-256] 0x61,0x88,0x45,0x2c = ldnp s1, s2, [x3, #44] 0x23,0x95,0x1f,0x6c = stnp d3, d5, [x9, #504] 0x47,0x2d,0x20,0x6c = stnp d7, d11, [x10, #-512] 0xc2,0x8f,0x7f,0x6c = ldnp d2, d3, [x30, #-8] 0xe3,0x17,0x00,0xac = stnp q3, q5, [sp] 0xf1,0xcf,0x1f,0xac = stnp q17, q19, [sp, #1008] 0x37,0x74,0x60,0xac = ldnp q23, q29, [x1, #-1024] 0x23,0x3d,0x10,0x32 = orr w3, w9, #0xffff0000 0x5f,0x29,0x03,0x32 = orr wsp, w10, #0xe00000ff 0x49,0x25,0x00,0x32 = orr w9, w10, #0x3ff 0xee,0x81,0x01,0x12 = and w14, w15, #0x80008000 0xac,0xad,0x0a,0x12 = and w12, w13, #0xffc3ffc3 0xeb,0x87,0x00,0x12 = and w11, wzr, #0x30003 0xc3,0xc8,0x03,0x52 = eor w3, w6, #0xe0e0e0e0 0xff,0xc7,0x00,0x52 = eor wsp, wzr, #0x3030303 0x30,0xc6,0x01,0x52 = eor w16, w17, #0x81818181 // 0x5f,0xe6,0x02,0x72 = ands wzr, w18, #0xcccccccc 0x93,0xe6,0x00,0x72 = ands w19, w20, #0x33333333 0xd5,0xe6,0x01,0x72 = ands w21, w22, #0x99999999 // 0x7f,0xf0,0x01,0x72 = ands wzr, w3, #0xaaaaaaaa // 0xff,0xf3,0x00,0x72 = ands wzr, wzr, #0x55555555 0xa3,0x84,0x66,0xd2 = eor x3, x5, #0xffffffffc000000 0x49,0xb9,0x40,0x92 = and x9, x10, #0x7fffffffffff 0x8b,0x31,0x41,0xb2 = orr x11, x12, #0x8000000000000fff 0x23,0x3d,0x10,0xb2 = orr x3, x9, #0xffff0000ffff0000 0x5f,0x29,0x03,0xb2 = orr sp, x10, #0xe00000ffe00000ff 0x49,0x25,0x00,0xb2 = orr x9, x10, #0x3ff000003ff 0xee,0x81,0x01,0x92 = and x14, x15, #0x8000800080008000 0xac,0xad,0x0a,0x92 = and x12, x13, #0xffc3ffc3ffc3ffc3 0xeb,0x87,0x00,0x92 = and x11, xzr, #0x3000300030003 0xc3,0xc8,0x03,0xd2 = eor x3, x6, #0xe0e0e0e0e0e0e0e0 0xff,0xc7,0x00,0xd2 = eor sp, xzr, #0x303030303030303 0x30,0xc6,0x01,0xd2 = eor x16, x17, #0x8181818181818181 // 0x5f,0xe6,0x02,0xf2 = ands xzr, x18, #0xcccccccccccccccc 0x93,0xe6,0x00,0xf2 = ands x19, x20, #0x3333333333333333 0xd5,0xe6,0x01,0xf2 = ands x21, x22, #0x9999999999999999 // 0x7f,0xf0,0x01,0xf2 = ands xzr, x3, #0xaaaaaaaaaaaaaaaa // 0xff,0xf3,0x00,0xf2 = ands xzr, xzr, #0x5555555555555555 0xe3,0x8f,0x00,0x32 = mov w3, #0xf000f 0xea,0xf3,0x01,0xb2 = orr x10, xzr, #0xaaaaaaaaaaaaaaaa 0xec,0x02,0x15,0x0a = and w12, w23, w21 0xf0,0x05,0x01,0x0a = and w16, w15, w1, lsl #1 0x89,0x7c,0x0a,0x0a = and w9, w4, w10, lsl #31 0xc3,0x03,0x0b,0x0a = and w3, w30, w11 0xa3,0xfc,0x07,0x8a = and x3, x5, x7, lsl #63 0xc5,0x11,0x93,0x8a = and x5, x14, x19, asr #4 0x23,0x7e,0xd3,0x0a = and w3, w17, w19, ror #31 0x40,0x44,0x5f,0x0a = and w0, w2, wzr, lsr #17 0xc3,0x03,0x8b,0x0a = and w3, w30, w11, asr #0 0x9f,0x00,0x1a,0x8a = and xzr, x4, x26 0xe3,0x03,0xd4,0x0a = and w3, wzr, w20, ror #0 0x87,0xfe,0x9f,0x8a = and x7, x20, xzr, asr #63 0x8d,0xbe,0x2e,0x8a = bic x13, x20, x14, lsl #47 0xe2,0x00,0x29,0x0a = bic w2, w7, w9 0xe2,0x7c,0x80,0x2a = orr w2, w7, w0, asr #31 0x28,0x31,0x0a,0xaa = orr x8, x9, x10, lsl #12 0xa3,0x00,0xa7,0xaa = orn x3, x5, x7, asr #0 0xa2,0x00,0x3d,0x2a = orn w2, w5, w29 0xe7,0x07,0x09,0x6a = ands w7, wzr, w9, lsl #1 0xa3,0xfc,0xd4,0xea = ands x3, x5, x20, ror #63 0xa3,0x00,0x27,0x6a = bics w3, w5, w7 0xe3,0x07,0x23,0xea = bics x3, xzr, x3, lsl #1 0x7f,0x7c,0x07,0x6a = tst w3, w7, lsl #31 0x5f,0x00,0x94,0xea = tst x2, x20, asr #0 0xe3,0x03,0x06,0xaa = mov x3, x6 0xe3,0x03,0x1f,0xaa = mov x3, xzr 0xff,0x03,0x02,0x2a = mov wzr, w2 0xe3,0x03,0x05,0x2a = mov w3, w5 0xe1,0xff,0x9f,0x52 = mov w1, #0xffff 0x02,0x00,0xa0,0x52 = movz w2, #0, lsl #16 0x42,0x9a,0x80,0x12 = mov w2, #-0x4d3 // 0x42,0x9a,0xc0,0xd2 = movz x2, #1234, lsl #32 0x3f,0x1c,0xe2,0xf2 = movk xzr, #4321, lsl #48 0x1e,0x00,0x00,0xb0 = adrp x30, #4096 0x14,0x00,0x00,0x10 = adr x20, #0 0xe9,0xff,0xff,0x70 = adr x9, #-1 0xe5,0xff,0x7f,0x70 = adr x5, #1048575 0xe9,0xff,0x7f,0x70 = adr x9, #1048575 0x02,0x00,0x80,0x10 = adr x2, #-1048576 0xe9,0xff,0x7f,0xf0 = adrp x9, #4294963200 0x14,0x00,0x80,0x90 = adrp x20, #-4294967296 0x1f,0x20,0x03,0xd5 = nop 0xff,0x2f,0x03,0xd5 = hint #127 0x1f,0x20,0x03,0xd5 = nop 0x3f,0x20,0x03,0xd5 = yield 0x5f,0x20,0x03,0xd5 = wfe 0x7f,0x20,0x03,0xd5 = wfi 0x9f,0x20,0x03,0xd5 = sev 0xbf,0x20,0x03,0xd5 = sevl 0x5f,0x3f,0x03,0xd5 = clrex 0x5f,0x30,0x03,0xd5 = clrex #0 0x5f,0x37,0x03,0xd5 = clrex #7 0x5f,0x3f,0x03,0xd5 = clrex 0x9f,0x30,0x03,0xd5 = dsb #0 0x9f,0x3c,0x03,0xd5 = dsb #12 0x9f,0x3f,0x03,0xd5 = dsb sy 0x9f,0x31,0x03,0xd5 = dsb oshld 0x9f,0x32,0x03,0xd5 = dsb oshst 0x9f,0x33,0x03,0xd5 = dsb osh 0x9f,0x35,0x03,0xd5 = dsb nshld 0x9f,0x36,0x03,0xd5 = dsb nshst 0x9f,0x37,0x03,0xd5 = dsb nsh 0x9f,0x39,0x03,0xd5 = dsb ishld 0x9f,0x3a,0x03,0xd5 = dsb ishst 0x9f,0x3b,0x03,0xd5 = dsb ish 0x9f,0x3d,0x03,0xd5 = dsb ld 0x9f,0x3e,0x03,0xd5 = dsb st 0x9f,0x3f,0x03,0xd5 = dsb sy 0xbf,0x30,0x03,0xd5 = dmb #0 0xbf,0x3c,0x03,0xd5 = dmb #12 0xbf,0x3f,0x03,0xd5 = dmb sy 0xbf,0x31,0x03,0xd5 = dmb oshld 0xbf,0x32,0x03,0xd5 = dmb oshst 0xbf,0x33,0x03,0xd5 = dmb osh 0xbf,0x35,0x03,0xd5 = dmb nshld 0xbf,0x36,0x03,0xd5 = dmb nshst 0xbf,0x37,0x03,0xd5 = dmb nsh 0xbf,0x39,0x03,0xd5 = dmb ishld 0xbf,0x3a,0x03,0xd5 = dmb ishst 0xbf,0x3b,0x03,0xd5 = dmb ish 0xbf,0x3d,0x03,0xd5 = dmb ld 0xbf,0x3e,0x03,0xd5 = dmb st 0xbf,0x3f,0x03,0xd5 = dmb sy 0xdf,0x3f,0x03,0xd5 = isb 0xdf,0x3f,0x03,0xd5 = isb 0xdf,0x3c,0x03,0xd5 = isb #12 0xbf,0x40,0x00,0xd5 = msr spsel, #0 0xdf,0x4f,0x03,0xd5 = msr daifset, #15 0xff,0x4c,0x03,0xd5 = msr daifclr, #12 0x9f,0x40,0x00,0xd5 = msr pan, #0 0x7f,0x40,0x00,0xd5 = msr uao, #0 0xe5,0x59,0x0f,0xd5 = sys #7, c5, c9, #7, x5 // 0x5f,0xff,0x08,0xd5 = sys #0, c15, c15, #2, xzr 0xe9,0x59,0x2f,0xd5 = sysl x9, #7, c5, c9, #7 0x41,0xff,0x28,0xd5 = sysl x1, #0, c15, c15, #2 0x1f,0x71,0x08,0xd5 = ic ialluis 0x1f,0x75,0x08,0xd5 = ic iallu 0x29,0x75,0x0b,0xd5 = ic ivau, x9 0x2c,0x74,0x0b,0xd5 = dc zva, x12 0x3f,0x76,0x08,0xd5 = dc ivac, xzr 0x42,0x76,0x08,0xd5 = dc isw, x2 0x29,0x7a,0x0b,0xd5 = dc cvac, x9 0x4a,0x7a,0x08,0xd5 = dc csw, x10 0x20,0x7b,0x0b,0xd5 = dc cvau, x0 0x23,0x7e,0x0b,0xd5 = dc civac, x3 0x5e,0x7e,0x08,0xd5 = dc cisw, x30 0x13,0x78,0x08,0xd5 = at s1e1r, x19 0x13,0x78,0x0c,0xd5 = at s1e2r, x19 0x13,0x78,0x0e,0xd5 = at s1e3r, x19 0x33,0x78,0x08,0xd5 = at s1e1w, x19 0x33,0x78,0x0c,0xd5 = at s1e2w, x19 0x33,0x78,0x0e,0xd5 = at s1e3w, x19 0x53,0x78,0x08,0xd5 = at s1e0r, x19 0x73,0x78,0x08,0xd5 = at s1e0w, x19 0x94,0x78,0x0c,0xd5 = at s12e1r, x20 0xb4,0x78,0x0c,0xd5 = at s12e1w, x20 0xd4,0x78,0x0c,0xd5 = at s12e0r, x20 0xf4,0x78,0x0c,0xd5 = at s12e0w, x20 0x24,0x80,0x0c,0xd5 = tlbi ipas2e1is, x4 0xa9,0x80,0x0c,0xd5 = tlbi ipas2le1is, x9 0x1f,0x83,0x08,0xd5 = tlbi vmalle1is 0x1f,0x83,0x0c,0xd5 = tlbi alle2is 0x1f,0x83,0x0e,0xd5 = tlbi alle3is 0x21,0x83,0x08,0xd5 = tlbi vae1is, x1 0x22,0x83,0x0c,0xd5 = tlbi vae2is, x2 0x23,0x83,0x0e,0xd5 = tlbi vae3is, x3 0x45,0x83,0x08,0xd5 = tlbi aside1is, x5 0x69,0x83,0x08,0xd5 = tlbi vaae1is, x9 0x9f,0x83,0x0c,0xd5 = tlbi alle1is 0xaa,0x83,0x08,0xd5 = tlbi vale1is, x10 0xab,0x83,0x0c,0xd5 = tlbi vale2is, x11 0xad,0x83,0x0e,0xd5 = tlbi vale3is, x13 0xdf,0x83,0x0c,0xd5 = tlbi vmalls12e1is 0xee,0x83,0x08,0xd5 = tlbi vaale1is, x14 0x2f,0x84,0x0c,0xd5 = tlbi ipas2e1, x15 0xb0,0x84,0x0c,0xd5 = tlbi ipas2le1, x16 0x1f,0x87,0x08,0xd5 = tlbi vmalle1 0x1f,0x87,0x0c,0xd5 = tlbi alle2 0x1f,0x87,0x0e,0xd5 = tlbi alle3 0x31,0x87,0x08,0xd5 = tlbi vae1, x17 0x32,0x87,0x0c,0xd5 = tlbi vae2, x18 0x33,0x87,0x0e,0xd5 = tlbi vae3, x19 0x54,0x87,0x08,0xd5 = tlbi aside1, x20 0x75,0x87,0x08,0xd5 = tlbi vaae1, x21 0x9f,0x87,0x0c,0xd5 = tlbi alle1 0xb6,0x87,0x08,0xd5 = tlbi vale1, x22 0xb7,0x87,0x0c,0xd5 = tlbi vale2, x23 0xb8,0x87,0x0e,0xd5 = tlbi vale3, x24 0xdf,0x87,0x0c,0xd5 = tlbi vmalls12e1 0xf9,0x87,0x08,0xd5 = tlbi vaale1, x25 0x0c,0x00,0x12,0xd5 = msr teecr32_el1, x12 0x4c,0x00,0x10,0xd5 = msr osdtrrx_el1, x12 0x0c,0x02,0x10,0xd5 = msr mdccint_el1, x12 0x4c,0x02,0x10,0xd5 = msr mdscr_el1, x12 0x4c,0x03,0x10,0xd5 = msr osdtrtx_el1, x12 0x0c,0x04,0x13,0xd5 = msr dbgdtr_el0, x12 0x0c,0x05,0x13,0xd5 = msr dbgdtrtx_el0, x12 0x4c,0x06,0x10,0xd5 = msr oseccr_el1, x12 0x0c,0x07,0x14,0xd5 = msr dbgvcr32_el2, x12 0x8c,0x00,0x10,0xd5 = msr dbgbvr0_el1, x12 0x8c,0x01,0x10,0xd5 = msr dbgbvr1_el1, x12 0x8c,0x02,0x10,0xd5 = msr dbgbvr2_el1, x12 0x8c,0x03,0x10,0xd5 = msr dbgbvr3_el1, x12 0x8c,0x04,0x10,0xd5 = msr dbgbvr4_el1, x12 0x8c,0x05,0x10,0xd5 = msr dbgbvr5_el1, x12 0x8c,0x06,0x10,0xd5 = msr dbgbvr6_el1, x12 0x8c,0x07,0x10,0xd5 = msr dbgbvr7_el1, x12 0x8c,0x08,0x10,0xd5 = msr dbgbvr8_el1, x12 0x8c,0x09,0x10,0xd5 = msr dbgbvr9_el1, x12 0x8c,0x0a,0x10,0xd5 = msr dbgbvr10_el1, x12 0x8c,0x0b,0x10,0xd5 = msr dbgbvr11_el1, x12 0x8c,0x0c,0x10,0xd5 = msr dbgbvr12_el1, x12 0x8c,0x0d,0x10,0xd5 = msr dbgbvr13_el1, x12 0x8c,0x0e,0x10,0xd5 = msr dbgbvr14_el1, x12 0x8c,0x0f,0x10,0xd5 = msr dbgbvr15_el1, x12 0xac,0x00,0x10,0xd5 = msr dbgbcr0_el1, x12 0xac,0x01,0x10,0xd5 = msr dbgbcr1_el1, x12 0xac,0x02,0x10,0xd5 = msr dbgbcr2_el1, x12 0xac,0x03,0x10,0xd5 = msr dbgbcr3_el1, x12 0xac,0x04,0x10,0xd5 = msr dbgbcr4_el1, x12 0xac,0x05,0x10,0xd5 = msr dbgbcr5_el1, x12 0xac,0x06,0x10,0xd5 = msr dbgbcr6_el1, x12 0xac,0x07,0x10,0xd5 = msr dbgbcr7_el1, x12 0xac,0x08,0x10,0xd5 = msr dbgbcr8_el1, x12 0xac,0x09,0x10,0xd5 = msr dbgbcr9_el1, x12 0xac,0x0a,0x10,0xd5 = msr dbgbcr10_el1, x12 0xac,0x0b,0x10,0xd5 = msr dbgbcr11_el1, x12 0xac,0x0c,0x10,0xd5 = msr dbgbcr12_el1, x12 0xac,0x0d,0x10,0xd5 = msr dbgbcr13_el1, x12 0xac,0x0e,0x10,0xd5 = msr dbgbcr14_el1, x12 0xac,0x0f,0x10,0xd5 = msr dbgbcr15_el1, x12 0xcc,0x00,0x10,0xd5 = msr dbgwvr0_el1, x12 0xcc,0x01,0x10,0xd5 = msr dbgwvr1_el1, x12 0xcc,0x02,0x10,0xd5 = msr dbgwvr2_el1, x12 0xcc,0x03,0x10,0xd5 = msr dbgwvr3_el1, x12 0xcc,0x04,0x10,0xd5 = msr dbgwvr4_el1, x12 0xcc,0x05,0x10,0xd5 = msr dbgwvr5_el1, x12 0xcc,0x06,0x10,0xd5 = msr dbgwvr6_el1, x12 0xcc,0x07,0x10,0xd5 = msr dbgwvr7_el1, x12 0xcc,0x08,0x10,0xd5 = msr dbgwvr8_el1, x12 0xcc,0x09,0x10,0xd5 = msr dbgwvr9_el1, x12 0xcc,0x0a,0x10,0xd5 = msr dbgwvr10_el1, x12 0xcc,0x0b,0x10,0xd5 = msr dbgwvr11_el1, x12 0xcc,0x0c,0x10,0xd5 = msr dbgwvr12_el1, x12 0xcc,0x0d,0x10,0xd5 = msr dbgwvr13_el1, x12 0xcc,0x0e,0x10,0xd5 = msr dbgwvr14_el1, x12 0xcc,0x0f,0x10,0xd5 = msr dbgwvr15_el1, x12 0xec,0x00,0x10,0xd5 = msr dbgwcr0_el1, x12 0xec,0x01,0x10,0xd5 = msr dbgwcr1_el1, x12 0xec,0x02,0x10,0xd5 = msr dbgwcr2_el1, x12 0xec,0x03,0x10,0xd5 = msr dbgwcr3_el1, x12 0xec,0x04,0x10,0xd5 = msr dbgwcr4_el1, x12 0xec,0x05,0x10,0xd5 = msr dbgwcr5_el1, x12 0xec,0x06,0x10,0xd5 = msr dbgwcr6_el1, x12 0xec,0x07,0x10,0xd5 = msr dbgwcr7_el1, x12 0xec,0x08,0x10,0xd5 = msr dbgwcr8_el1, x12 0xec,0x09,0x10,0xd5 = msr dbgwcr9_el1, x12 0xec,0x0a,0x10,0xd5 = msr dbgwcr10_el1, x12 0xec,0x0b,0x10,0xd5 = msr dbgwcr11_el1, x12 0xec,0x0c,0x10,0xd5 = msr dbgwcr12_el1, x12 0xec,0x0d,0x10,0xd5 = msr dbgwcr13_el1, x12 0xec,0x0e,0x10,0xd5 = msr dbgwcr14_el1, x12 0xec,0x0f,0x10,0xd5 = msr dbgwcr15_el1, x12 0x0c,0x10,0x12,0xd5 = msr teehbr32_el1, x12 0x8c,0x10,0x10,0xd5 = msr oslar_el1, x12 0x8c,0x13,0x10,0xd5 = msr osdlr_el1, x12 0x8c,0x14,0x10,0xd5 = msr dbgprcr_el1, x12 0xcc,0x78,0x10,0xd5 = msr dbgclaimset_el1, x12 0xcc,0x79,0x10,0xd5 = msr dbgclaimclr_el1, x12 0x0c,0x00,0x1a,0xd5 = msr csselr_el1, x12 0x0c,0x00,0x1c,0xd5 = msr vpidr_el2, x12 0xac,0x00,0x1c,0xd5 = msr vmpidr_el2, x12 0x0c,0x10,0x18,0xd5 = msr sctlr_el1, x12 0x0c,0x10,0x1c,0xd5 = msr sctlr_el2, x12 0x0c,0x10,0x1e,0xd5 = msr sctlr_el3, x12 0x2c,0x10,0x18,0xd5 = msr actlr_el1, x12 0x2c,0x10,0x1c,0xd5 = msr actlr_el2, x12 0x2c,0x10,0x1e,0xd5 = msr actlr_el3, x12 0x4c,0x10,0x18,0xd5 = msr cpacr_el1, x12 0x0c,0x11,0x1c,0xd5 = msr hcr_el2, x12 0x0c,0x11,0x1e,0xd5 = msr scr_el3, x12 0x2c,0x11,0x1c,0xd5 = msr mdcr_el2, x12 0x2c,0x11,0x1e,0xd5 = msr sder32_el3, x12 0x4c,0x11,0x1c,0xd5 = msr cptr_el2, x12 0x4c,0x11,0x1e,0xd5 = msr cptr_el3, x12 0x6c,0x11,0x1c,0xd5 = msr hstr_el2, x12 0xec,0x11,0x1c,0xd5 = msr hacr_el2, x12 0x2c,0x13,0x1e,0xd5 = msr mdcr_el3, x12 0x0c,0x20,0x18,0xd5 = msr ttbr0_el1, x12 0x0c,0x20,0x1c,0xd5 = msr ttbr0_el2, x12 0x0c,0x20,0x1e,0xd5 = msr ttbr0_el3, x12 0x2c,0x20,0x18,0xd5 = msr ttbr1_el1, x12 0x4c,0x20,0x18,0xd5 = msr tcr_el1, x12 0x4c,0x20,0x1c,0xd5 = msr tcr_el2, x12 0x4c,0x20,0x1e,0xd5 = msr tcr_el3, x12 0x0c,0x21,0x1c,0xd5 = msr vttbr_el2, x12 0x4c,0x21,0x1c,0xd5 = msr vtcr_el2, x12 0x0c,0x30,0x1c,0xd5 = msr dacr32_el2, x12 0x0c,0x40,0x18,0xd5 = msr spsr_el1, x12 0x0c,0x40,0x1c,0xd5 = msr spsr_el2, x12 0x0c,0x40,0x1e,0xd5 = msr spsr_el3, x12 0x2c,0x40,0x18,0xd5 = msr elr_el1, x12 0x2c,0x40,0x1c,0xd5 = msr elr_el2, x12 0x2c,0x40,0x1e,0xd5 = msr elr_el3, x12 0x0c,0x41,0x18,0xd5 = msr sp_el0, x12 0x0c,0x41,0x1c,0xd5 = msr sp_el1, x12 0x0c,0x41,0x1e,0xd5 = msr sp_el2, x12 0x0c,0x42,0x18,0xd5 = msr spsel, x12 0x0c,0x42,0x1b,0xd5 = msr nzcv, x12 0x2c,0x42,0x1b,0xd5 = msr daif, x12 0x4c,0x42,0x18,0xd5 = msr currentel, x12 0x0c,0x43,0x1c,0xd5 = msr spsr_irq, x12 0x2c,0x43,0x1c,0xd5 = msr spsr_abt, x12 0x4c,0x43,0x1c,0xd5 = msr spsr_und, x12 0x6c,0x43,0x1c,0xd5 = msr spsr_fiq, x12 0x0c,0x44,0x1b,0xd5 = msr fpcr, x12 0x2c,0x44,0x1b,0xd5 = msr fpsr, x12 0x0c,0x45,0x1b,0xd5 = msr dspsr_el0, x12 0x2c,0x45,0x1b,0xd5 = msr dlr_el0, x12 0x2c,0x50,0x1c,0xd5 = msr ifsr32_el2, x12 0x0c,0x51,0x18,0xd5 = msr afsr0_el1, x12 0x0c,0x51,0x1c,0xd5 = msr afsr0_el2, x12 0x0c,0x51,0x1e,0xd5 = msr afsr0_el3, x12 0x2c,0x51,0x18,0xd5 = msr afsr1_el1, x12 0x2c,0x51,0x1d,0xd5 = msr afsr1_el12, x12 0x2c,0x51,0x1c,0xd5 = msr afsr1_el2, x12 0x2c,0x51,0x1e,0xd5 = msr afsr1_el3, x12 0x0c,0x52,0x18,0xd5 = msr esr_el1, x12 0x0c,0x52,0x1c,0xd5 = msr esr_el2, x12 0x0c,0x52,0x1e,0xd5 = msr esr_el3, x12 0x0c,0x53,0x1c,0xd5 = msr fpexc32_el2, x12 0x0c,0x60,0x18,0xd5 = msr far_el1, x12 0x0c,0x60,0x1c,0xd5 = msr far_el2, x12 0x0c,0x60,0x1e,0xd5 = msr far_el3, x12 0x8c,0x60,0x1c,0xd5 = msr hpfar_el2, x12 0x0c,0x74,0x18,0xd5 = msr par_el1, x12 0x0c,0x9c,0x1b,0xd5 = msr pmcr_el0, x12 0x2c,0x9c,0x1b,0xd5 = msr pmcntenset_el0, x12 0x4c,0x9c,0x1b,0xd5 = msr pmcntenclr_el0, x12 0x6c,0x9c,0x1b,0xd5 = msr pmovsclr_el0, x12 0xac,0x9c,0x1b,0xd5 = msr pmselr_el0, x12 0x0c,0x9d,0x1b,0xd5 = msr pmccntr_el0, x12 0x2c,0x9d,0x1b,0xd5 = msr pmxevtyper_el0, x12 0x4c,0x9d,0x1b,0xd5 = msr pmxevcntr_el0, x12 0x0c,0x9e,0x1b,0xd5 = msr pmuserenr_el0, x12 0x2c,0x9e,0x18,0xd5 = msr pmintenset_el1, x12 0x4c,0x9e,0x18,0xd5 = msr pmintenclr_el1, x12 0x6c,0x9e,0x1b,0xd5 = msr pmovsset_el0, x12 0x0c,0xa2,0x18,0xd5 = msr mair_el1, x12 0x0c,0xa2,0x1c,0xd5 = msr mair_el2, x12 0x0c,0xa2,0x1e,0xd5 = msr mair_el3, x12 0x0c,0xa3,0x18,0xd5 = msr amair_el1, x12 0x0c,0xa3,0x1c,0xd5 = msr amair_el2, x12 0x0c,0xa3,0x1e,0xd5 = msr amair_el3, x12 0x0c,0xc0,0x18,0xd5 = msr vbar_el1, x12 0x0c,0xc0,0x1c,0xd5 = msr vbar_el2, x12 0x0c,0xc0,0x1e,0xd5 = msr vbar_el3, x12 0x4c,0xc0,0x18,0xd5 = msr rmr_el1, x12 0x4c,0xc0,0x1c,0xd5 = msr rmr_el2, x12 0x4c,0xc0,0x1e,0xd5 = msr rmr_el3, x12 0x2c,0xd0,0x18,0xd5 = msr contextidr_el1, x12 0x4c,0xd0,0x1b,0xd5 = msr tpidr_el0, x12 0x4c,0xd0,0x1c,0xd5 = msr tpidr_el2, x12 0x4c,0xd0,0x1e,0xd5 = msr tpidr_el3, x12 0x6c,0xd0,0x1b,0xd5 = msr tpidrro_el0, x12 0x8c,0xd0,0x18,0xd5 = msr tpidr_el1, x12 0x0c,0xe0,0x1b,0xd5 = msr cntfrq_el0, x12 0x6c,0xe0,0x1c,0xd5 = msr cntvoff_el2, x12 0x0c,0xe1,0x18,0xd5 = msr cntkctl_el1, x12 0x0c,0xe1,0x1c,0xd5 = msr cnthctl_el2, x12 0x0c,0xe2,0x1b,0xd5 = msr cntp_tval_el0, x12 0x0c,0xe2,0x1c,0xd5 = msr cnthp_tval_el2, x12 0x0c,0xe2,0x1f,0xd5 = msr cntps_tval_el1, x12 0x2c,0xe2,0x1b,0xd5 = msr cntp_ctl_el0, x12 0x2c,0xe2,0x1c,0xd5 = msr cnthp_ctl_el2, x12 0x2c,0xe2,0x1f,0xd5 = msr cntps_ctl_el1, x12 0x4c,0xe2,0x1b,0xd5 = msr cntp_cval_el0, x12 0x4c,0xe2,0x1c,0xd5 = msr cnthp_cval_el2, x12 0x4c,0xe2,0x1f,0xd5 = msr cntps_cval_el1, x12 0x0c,0xe3,0x1b,0xd5 = msr cntv_tval_el0, x12 0x0c,0xe3,0x1d,0xd5 = msr cntv_tval_el02, x12 0x2c,0xe3,0x1b,0xd5 = msr cntv_ctl_el0, x12 0x4c,0xe3,0x1b,0xd5 = msr cntv_cval_el0, x12 0x0c,0xe8,0x1b,0xd5 = msr pmevcntr0_el0, x12 0x2c,0xe8,0x1b,0xd5 = msr pmevcntr1_el0, x12 0x4c,0xe8,0x1b,0xd5 = msr pmevcntr2_el0, x12 0x6c,0xe8,0x1b,0xd5 = msr pmevcntr3_el0, x12 0x8c,0xe8,0x1b,0xd5 = msr pmevcntr4_el0, x12 0xac,0xe8,0x1b,0xd5 = msr pmevcntr5_el0, x12 0xcc,0xe8,0x1b,0xd5 = msr pmevcntr6_el0, x12 0xec,0xe8,0x1b,0xd5 = msr pmevcntr7_el0, x12 0x0c,0xe9,0x1b,0xd5 = msr pmevcntr8_el0, x12 0x2c,0xe9,0x1b,0xd5 = msr pmevcntr9_el0, x12 0x4c,0xe9,0x1b,0xd5 = msr pmevcntr10_el0, x12 0x6c,0xe9,0x1b,0xd5 = msr pmevcntr11_el0, x12 0x8c,0xe9,0x1b,0xd5 = msr pmevcntr12_el0, x12 0xac,0xe9,0x1b,0xd5 = msr pmevcntr13_el0, x12 0xcc,0xe9,0x1b,0xd5 = msr pmevcntr14_el0, x12 0xec,0xe9,0x1b,0xd5 = msr pmevcntr15_el0, x12 0x0c,0xea,0x1b,0xd5 = msr pmevcntr16_el0, x12 0x2c,0xea,0x1b,0xd5 = msr pmevcntr17_el0, x12 0x4c,0xea,0x1b,0xd5 = msr pmevcntr18_el0, x12 0x6c,0xea,0x1b,0xd5 = msr pmevcntr19_el0, x12 0x8c,0xea,0x1b,0xd5 = msr pmevcntr20_el0, x12 0xac,0xea,0x1b,0xd5 = msr pmevcntr21_el0, x12 0xcc,0xea,0x1b,0xd5 = msr pmevcntr22_el0, x12 0xec,0xea,0x1b,0xd5 = msr pmevcntr23_el0, x12 0x0c,0xeb,0x1b,0xd5 = msr pmevcntr24_el0, x12 0x2c,0xeb,0x1b,0xd5 = msr pmevcntr25_el0, x12 0x4c,0xeb,0x1b,0xd5 = msr pmevcntr26_el0, x12 0x6c,0xeb,0x1b,0xd5 = msr pmevcntr27_el0, x12 0x8c,0xeb,0x1b,0xd5 = msr pmevcntr28_el0, x12 0xac,0xeb,0x1b,0xd5 = msr pmevcntr29_el0, x12 0xcc,0xeb,0x1b,0xd5 = msr pmevcntr30_el0, x12 0xec,0xef,0x1b,0xd5 = msr pmccfiltr_el0, x12 0x0c,0xec,0x1b,0xd5 = msr pmevtyper0_el0, x12 0x2c,0xec,0x1b,0xd5 = msr pmevtyper1_el0, x12 0x4c,0xec,0x1b,0xd5 = msr pmevtyper2_el0, x12 0x6c,0xec,0x1b,0xd5 = msr pmevtyper3_el0, x12 0x8c,0xec,0x1b,0xd5 = msr pmevtyper4_el0, x12 0xac,0xec,0x1b,0xd5 = msr pmevtyper5_el0, x12 0xcc,0xec,0x1b,0xd5 = msr pmevtyper6_el0, x12 0xec,0xec,0x1b,0xd5 = msr pmevtyper7_el0, x12 0x0c,0xed,0x1b,0xd5 = msr pmevtyper8_el0, x12 0x2c,0xed,0x1b,0xd5 = msr pmevtyper9_el0, x12 0x4c,0xed,0x1b,0xd5 = msr pmevtyper10_el0, x12 0x6c,0xed,0x1b,0xd5 = msr pmevtyper11_el0, x12 0x8c,0xed,0x1b,0xd5 = msr pmevtyper12_el0, x12 0xac,0xed,0x1b,0xd5 = msr pmevtyper13_el0, x12 0xcc,0xed,0x1b,0xd5 = msr pmevtyper14_el0, x12 0xec,0xed,0x1b,0xd5 = msr pmevtyper15_el0, x12 0x0c,0xee,0x1b,0xd5 = msr pmevtyper16_el0, x12 0x2c,0xee,0x1b,0xd5 = msr pmevtyper17_el0, x12 0x4c,0xee,0x1b,0xd5 = msr pmevtyper18_el0, x12 0x6c,0xee,0x1b,0xd5 = msr pmevtyper19_el0, x12 0x8c,0xee,0x1b,0xd5 = msr pmevtyper20_el0, x12 0xac,0xee,0x1b,0xd5 = msr pmevtyper21_el0, x12 0xcc,0xee,0x1b,0xd5 = msr pmevtyper22_el0, x12 0xec,0xee,0x1b,0xd5 = msr pmevtyper23_el0, x12 0x0c,0xef,0x1b,0xd5 = msr pmevtyper24_el0, x12 0x2c,0xef,0x1b,0xd5 = msr pmevtyper25_el0, x12 0x4c,0xef,0x1b,0xd5 = msr pmevtyper26_el0, x12 0x6c,0xef,0x1b,0xd5 = msr pmevtyper27_el0, x12 0x8c,0xef,0x1b,0xd5 = msr pmevtyper28_el0, x12 0xac,0xef,0x1b,0xd5 = msr pmevtyper29_el0, x12 0xcc,0xef,0x1b,0xd5 = msr pmevtyper30_el0, x12 0x69,0x42,0x38,0xd5 = mrs x9, pan 0x89,0x42,0x38,0xd5 = mrs x9, uao 0x09,0x00,0x32,0xd5 = mrs x9, teecr32_el1 0x49,0x00,0x30,0xd5 = mrs x9, osdtrrx_el1 0x09,0x01,0x33,0xd5 = mrs x9, mdccsr_el0 0x09,0x02,0x30,0xd5 = mrs x9, mdccint_el1 0x49,0x02,0x30,0xd5 = mrs x9, mdscr_el1 0x49,0x03,0x30,0xd5 = mrs x9, osdtrtx_el1 0x09,0x04,0x33,0xd5 = mrs x9, dbgdtr_el0 0x09,0x05,0x33,0xd5 = mrs x9, dbgdtrrx_el0 0x49,0x06,0x30,0xd5 = mrs x9, oseccr_el1 0x09,0x07,0x34,0xd5 = mrs x9, dbgvcr32_el2 0x89,0x00,0x30,0xd5 = mrs x9, dbgbvr0_el1 0x89,0x01,0x30,0xd5 = mrs x9, dbgbvr1_el1 0x89,0x02,0x30,0xd5 = mrs x9, dbgbvr2_el1 0x89,0x03,0x30,0xd5 = mrs x9, dbgbvr3_el1 0x89,0x04,0x30,0xd5 = mrs x9, dbgbvr4_el1 0x89,0x05,0x30,0xd5 = mrs x9, dbgbvr5_el1 0x89,0x06,0x30,0xd5 = mrs x9, dbgbvr6_el1 0x89,0x07,0x30,0xd5 = mrs x9, dbgbvr7_el1 0x89,0x08,0x30,0xd5 = mrs x9, dbgbvr8_el1 0x89,0x09,0x30,0xd5 = mrs x9, dbgbvr9_el1 0x89,0x0a,0x30,0xd5 = mrs x9, dbgbvr10_el1 0x89,0x0b,0x30,0xd5 = mrs x9, dbgbvr11_el1 0x89,0x0c,0x30,0xd5 = mrs x9, dbgbvr12_el1 0x89,0x0d,0x30,0xd5 = mrs x9, dbgbvr13_el1 0x89,0x0e,0x30,0xd5 = mrs x9, dbgbvr14_el1 0x89,0x0f,0x30,0xd5 = mrs x9, dbgbvr15_el1 0xa9,0x00,0x30,0xd5 = mrs x9, dbgbcr0_el1 0xa9,0x01,0x30,0xd5 = mrs x9, dbgbcr1_el1 0xa9,0x02,0x30,0xd5 = mrs x9, dbgbcr2_el1 0xa9,0x03,0x30,0xd5 = mrs x9, dbgbcr3_el1 0xa9,0x04,0x30,0xd5 = mrs x9, dbgbcr4_el1 0xa9,0x05,0x30,0xd5 = mrs x9, dbgbcr5_el1 0xa9,0x06,0x30,0xd5 = mrs x9, dbgbcr6_el1 0xa9,0x07,0x30,0xd5 = mrs x9, dbgbcr7_el1 0xa9,0x08,0x30,0xd5 = mrs x9, dbgbcr8_el1 0xa9,0x09,0x30,0xd5 = mrs x9, dbgbcr9_el1 0xa9,0x0a,0x30,0xd5 = mrs x9, dbgbcr10_el1 0xa9,0x0b,0x30,0xd5 = mrs x9, dbgbcr11_el1 0xa9,0x0c,0x30,0xd5 = mrs x9, dbgbcr12_el1 0xa9,0x0d,0x30,0xd5 = mrs x9, dbgbcr13_el1 0xa9,0x0e,0x30,0xd5 = mrs x9, dbgbcr14_el1 0xa9,0x0f,0x30,0xd5 = mrs x9, dbgbcr15_el1 0xc9,0x00,0x30,0xd5 = mrs x9, dbgwvr0_el1 0xc9,0x01,0x30,0xd5 = mrs x9, dbgwvr1_el1 0xc9,0x02,0x30,0xd5 = mrs x9, dbgwvr2_el1 0xc9,0x03,0x30,0xd5 = mrs x9, dbgwvr3_el1 0xc9,0x04,0x30,0xd5 = mrs x9, dbgwvr4_el1 0xc9,0x05,0x30,0xd5 = mrs x9, dbgwvr5_el1 0xc9,0x06,0x30,0xd5 = mrs x9, dbgwvr6_el1 0xc9,0x07,0x30,0xd5 = mrs x9, dbgwvr7_el1 0xc9,0x08,0x30,0xd5 = mrs x9, dbgwvr8_el1 0xc9,0x09,0x30,0xd5 = mrs x9, dbgwvr9_el1 0xc9,0x0a,0x30,0xd5 = mrs x9, dbgwvr10_el1 0xc9,0x0b,0x30,0xd5 = mrs x9, dbgwvr11_el1 0xc9,0x0c,0x30,0xd5 = mrs x9, dbgwvr12_el1 0xc9,0x0d,0x30,0xd5 = mrs x9, dbgwvr13_el1 0xc9,0x0e,0x30,0xd5 = mrs x9, dbgwvr14_el1 0xc9,0x0f,0x30,0xd5 = mrs x9, dbgwvr15_el1 0xe9,0x00,0x30,0xd5 = mrs x9, dbgwcr0_el1 0xe9,0x01,0x30,0xd5 = mrs x9, dbgwcr1_el1 0xe9,0x02,0x30,0xd5 = mrs x9, dbgwcr2_el1 0xe9,0x03,0x30,0xd5 = mrs x9, dbgwcr3_el1 0xe9,0x04,0x30,0xd5 = mrs x9, dbgwcr4_el1 0xe9,0x05,0x30,0xd5 = mrs x9, dbgwcr5_el1 0xe9,0x06,0x30,0xd5 = mrs x9, dbgwcr6_el1 0xe9,0x07,0x30,0xd5 = mrs x9, dbgwcr7_el1 0xe9,0x08,0x30,0xd5 = mrs x9, dbgwcr8_el1 0xe9,0x09,0x30,0xd5 = mrs x9, dbgwcr9_el1 0xe9,0x0a,0x30,0xd5 = mrs x9, dbgwcr10_el1 0xe9,0x0b,0x30,0xd5 = mrs x9, dbgwcr11_el1 0xe9,0x0c,0x30,0xd5 = mrs x9, dbgwcr12_el1 0xe9,0x0d,0x30,0xd5 = mrs x9, dbgwcr13_el1 0xe9,0x0e,0x30,0xd5 = mrs x9, dbgwcr14_el1 0xe9,0x0f,0x30,0xd5 = mrs x9, dbgwcr15_el1 0x09,0x10,0x30,0xd5 = mrs x9, mdrar_el1 0x09,0x10,0x32,0xd5 = mrs x9, teehbr32_el1 0x89,0x11,0x30,0xd5 = mrs x9, oslsr_el1 0x89,0x13,0x30,0xd5 = mrs x9, osdlr_el1 0x89,0x14,0x30,0xd5 = mrs x9, dbgprcr_el1 0xc9,0x78,0x30,0xd5 = mrs x9, dbgclaimset_el1 0xc9,0x79,0x30,0xd5 = mrs x9, dbgclaimclr_el1 0xc9,0x7e,0x30,0xd5 = mrs x9, dbgauthstatus_el1 0x09,0x00,0x38,0xd5 = mrs x9, midr_el1 0x09,0x00,0x39,0xd5 = mrs x9, ccsidr_el1 0x09,0x00,0x3a,0xd5 = mrs x9, csselr_el1 0x09,0x00,0x3c,0xd5 = mrs x9, vpidr_el2 0x29,0x00,0x39,0xd5 = mrs x9, clidr_el1 0x29,0x00,0x3b,0xd5 = mrs x9, ctr_el0 0xa9,0x00,0x38,0xd5 = mrs x9, mpidr_el1 0xa9,0x00,0x3c,0xd5 = mrs x9, vmpidr_el2 0xc9,0x00,0x38,0xd5 = mrs x9, revidr_el1 0xe9,0x00,0x39,0xd5 = mrs x9, aidr_el1 0xe9,0x00,0x3b,0xd5 = mrs x9, dczid_el0 0x09,0x01,0x38,0xd5 = mrs x9, id_pfr0_el1 0x29,0x01,0x38,0xd5 = mrs x9, id_pfr1_el1 0x49,0x01,0x38,0xd5 = mrs x9, id_dfr0_el1 0x69,0x01,0x38,0xd5 = mrs x9, id_afr0_el1 0x89,0x01,0x38,0xd5 = mrs x9, id_mmfr0_el1 0xa9,0x01,0x38,0xd5 = mrs x9, id_mmfr1_el1 0xc9,0x01,0x38,0xd5 = mrs x9, id_mmfr2_el1 0xe9,0x01,0x38,0xd5 = mrs x9, id_mmfr3_el1 0xc9,0x02,0x38,0xd5 = mrs x9, id_mmfr4_el1 0x09,0x02,0x38,0xd5 = mrs x9, id_isar0_el1 0x29,0x02,0x38,0xd5 = mrs x9, id_isar1_el1 0x49,0x02,0x38,0xd5 = mrs x9, id_isar2_el1 0x69,0x02,0x38,0xd5 = mrs x9, id_isar3_el1 0x89,0x02,0x38,0xd5 = mrs x9, id_isar4_el1 0xa9,0x02,0x38,0xd5 = mrs x9, id_isar5_el1 0x09,0x03,0x38,0xd5 = mrs x9, mvfr0_el1 0x29,0x03,0x38,0xd5 = mrs x9, mvfr1_el1 0x49,0x03,0x38,0xd5 = mrs x9, mvfr2_el1 0x09,0x04,0x38,0xd5 = mrs x9, id_aa64pfr0_el1 0x29,0x04,0x38,0xd5 = mrs x9, id_aa64pfr1_el1 0x09,0x05,0x38,0xd5 = mrs x9, id_aa64dfr0_el1 0x29,0x05,0x38,0xd5 = mrs x9, id_aa64dfr1_el1 0x89,0x05,0x38,0xd5 = mrs x9, id_aa64afr0_el1 0xa9,0x05,0x38,0xd5 = mrs x9, id_aa64afr1_el1 0x09,0x06,0x38,0xd5 = mrs x9, id_aa64isar0_el1 0x29,0x06,0x38,0xd5 = mrs x9, id_aa64isar1_el1 0x09,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr0_el1 0x29,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr1_el1 0x49,0x07,0x38,0xd5 = mrs x9, id_aa64mmfr2_el1 0x69,0xa4,0x38,0xd5 = mrs x9, lorc_el1 0x29,0xa4,0x38,0xd5 = mrs x9, lorea_el1 0xe9,0xa4,0x38,0xd5 = mrs x9, lorid_el1 0x49,0xa4,0x38,0xd5 = mrs x9, lorn_el1 0x09,0xa4,0x38,0xd5 = mrs x9, lorsa_el1 0x09,0x10,0x38,0xd5 = mrs x9, sctlr_el1 0x09,0x10,0x3d,0xd5 = mrs x9, sctlr_el12 0x09,0x10,0x3c,0xd5 = mrs x9, sctlr_el2 0x09,0x10,0x3e,0xd5 = mrs x9, sctlr_el3 0x29,0x10,0x38,0xd5 = mrs x9, actlr_el1 0x29,0x10,0x3c,0xd5 = mrs x9, actlr_el2 0x29,0x10,0x3e,0xd5 = mrs x9, actlr_el3 0x49,0x10,0x38,0xd5 = mrs x9, cpacr_el1 0x49,0x10,0x3d,0xd5 = mrs x9, cpacr_el12 0x09,0x11,0x3c,0xd5 = mrs x9, hcr_el2 0x09,0x11,0x3e,0xd5 = mrs x9, scr_el3 0x29,0x11,0x3c,0xd5 = mrs x9, mdcr_el2 0x29,0x11,0x3e,0xd5 = mrs x9, sder32_el3 0x49,0x11,0x3c,0xd5 = mrs x9, cptr_el2 0x49,0x11,0x3e,0xd5 = mrs x9, cptr_el3 0x69,0x11,0x3c,0xd5 = mrs x9, hstr_el2 0xe9,0x11,0x3c,0xd5 = mrs x9, hacr_el2 0x29,0x13,0x3e,0xd5 = mrs x9, mdcr_el3 0x09,0x20,0x38,0xd5 = mrs x9, ttbr0_el1 0x09,0x20,0x3d,0xd5 = mrs x9, ttbr0_el12 0x09,0x20,0x3c,0xd5 = mrs x9, ttbr0_el2 0x09,0x20,0x3e,0xd5 = mrs x9, ttbr0_el3 0x29,0x20,0x38,0xd5 = mrs x9, ttbr1_el1 0x29,0x20,0x3d,0xd5 = mrs x9, ttbr1_el12 0x29,0x20,0x3c,0xd5 = mrs x9, ttbr1_el2 0x49,0x20,0x38,0xd5 = mrs x9, tcr_el1 0x49,0x20,0x3d,0xd5 = mrs x9, tcr_el12 0x49,0x20,0x3c,0xd5 = mrs x9, tcr_el2 0x49,0x20,0x3e,0xd5 = mrs x9, tcr_el3 0x09,0x21,0x3c,0xd5 = mrs x9, vttbr_el2 0x49,0x21,0x3c,0xd5 = mrs x9, vtcr_el2 0x09,0x30,0x3c,0xd5 = mrs x9, dacr32_el2 0x09,0x40,0x38,0xd5 = mrs x9, spsr_el1 0x09,0x40,0x3d,0xd5 = mrs x9, spsr_el12 0x09,0x40,0x3c,0xd5 = mrs x9, spsr_el2 0x09,0x40,0x3e,0xd5 = mrs x9, spsr_el3 0x29,0x40,0x38,0xd5 = mrs x9, elr_el1 0x29,0x40,0x3d,0xd5 = mrs x9, elr_el12 0x29,0x40,0x3c,0xd5 = mrs x9, elr_el2 0x29,0x40,0x3e,0xd5 = mrs x9, elr_el3 0x09,0x41,0x38,0xd5 = mrs x9, sp_el0 0x09,0x41,0x3c,0xd5 = mrs x9, sp_el1 0x09,0x41,0x3e,0xd5 = mrs x9, sp_el2 0x09,0x42,0x38,0xd5 = mrs x9, spsel 0x09,0x42,0x3b,0xd5 = mrs x9, nzcv 0x29,0x42,0x3b,0xd5 = mrs x9, daif 0x49,0x42,0x38,0xd5 = mrs x9, currentel 0x09,0x43,0x3c,0xd5 = mrs x9, spsr_irq 0x29,0x43,0x3c,0xd5 = mrs x9, spsr_abt 0x49,0x43,0x3c,0xd5 = mrs x9, spsr_und 0x69,0x43,0x3c,0xd5 = mrs x9, spsr_fiq 0x09,0x44,0x3b,0xd5 = mrs x9, fpcr 0x29,0x44,0x3b,0xd5 = mrs x9, fpsr 0x09,0x45,0x3b,0xd5 = mrs x9, dspsr_el0 0x29,0x45,0x3b,0xd5 = mrs x9, dlr_el0 0x29,0x50,0x3c,0xd5 = mrs x9, ifsr32_el2 0x09,0x51,0x38,0xd5 = mrs x9, afsr0_el1 0x09,0x51,0x3d,0xd5 = mrs x9, afsr0_el12 0x09,0x51,0x3c,0xd5 = mrs x9, afsr0_el2 0x09,0x51,0x3e,0xd5 = mrs x9, afsr0_el3 0x29,0x51,0x38,0xd5 = mrs x9, afsr1_el1 0x29,0x51,0x3c,0xd5 = mrs x9, afsr1_el2 0x29,0x51,0x3e,0xd5 = mrs x9, afsr1_el3 0x09,0x52,0x38,0xd5 = mrs x9, esr_el1 0x09,0x52,0x3d,0xd5 = mrs x9, esr_el12 0x09,0x52,0x3c,0xd5 = mrs x9, esr_el2 0x09,0x52,0x3e,0xd5 = mrs x9, esr_el3 0x09,0x53,0x3c,0xd5 = mrs x9, fpexc32_el2 0x09,0x60,0x38,0xd5 = mrs x9, far_el1 0x09,0x60,0x3d,0xd5 = mrs x9, far_el12 0x09,0x60,0x3c,0xd5 = mrs x9, far_el2 0x09,0x60,0x3e,0xd5 = mrs x9, far_el3 0x89,0x60,0x3c,0xd5 = mrs x9, hpfar_el2 0x09,0x74,0x38,0xd5 = mrs x9, par_el1 0x09,0x9c,0x3b,0xd5 = mrs x9, pmcr_el0 0x29,0x9c,0x3b,0xd5 = mrs x9, pmcntenset_el0 0x49,0x9c,0x3b,0xd5 = mrs x9, pmcntenclr_el0 0x69,0x9c,0x3b,0xd5 = mrs x9, pmovsclr_el0 0xa9,0x9c,0x3b,0xd5 = mrs x9, pmselr_el0 0xc9,0x9c,0x3b,0xd5 = mrs x9, pmceid0_el0 0xe9,0x9c,0x3b,0xd5 = mrs x9, pmceid1_el0 0x09,0x9d,0x3b,0xd5 = mrs x9, pmccntr_el0 0x29,0x9d,0x3b,0xd5 = mrs x9, pmxevtyper_el0 0x49,0x9d,0x3b,0xd5 = mrs x9, pmxevcntr_el0 0x09,0x9e,0x3b,0xd5 = mrs x9, pmuserenr_el0 0x29,0x9e,0x38,0xd5 = mrs x9, pmintenset_el1 0x49,0x9e,0x38,0xd5 = mrs x9, pmintenclr_el1 0x69,0x9e,0x3b,0xd5 = mrs x9, pmovsset_el0 0x09,0xa2,0x38,0xd5 = mrs x9, mair_el1 0x09,0xa2,0x3d,0xd5 = mrs x9, mair_el12 0x09,0xa2,0x3c,0xd5 = mrs x9, mair_el2 0x09,0xa2,0x3e,0xd5 = mrs x9, mair_el3 0x09,0xa3,0x38,0xd5 = mrs x9, amair_el1 0x09,0xa3,0x3d,0xd5 = mrs x9, amair_el12 0x09,0xa3,0x3c,0xd5 = mrs x9, amair_el2 0x09,0xa3,0x3e,0xd5 = mrs x9, amair_el3 0x09,0xc0,0x38,0xd5 = mrs x9, vbar_el1 0x09,0xc0,0x3d,0xd5 = mrs x9, vbar_el12 0x09,0xc0,0x3c,0xd5 = mrs x9, vbar_el2 0x09,0xc0,0x3e,0xd5 = mrs x9, vbar_el3 0x29,0xc0,0x38,0xd5 = mrs x9, rvbar_el1 0x29,0xc0,0x3c,0xd5 = mrs x9, rvbar_el2 0x29,0xc0,0x3e,0xd5 = mrs x9, rvbar_el3 0x49,0xc0,0x38,0xd5 = mrs x9, rmr_el1 0x49,0xc0,0x3c,0xd5 = mrs x9, rmr_el2 0x49,0xc0,0x3e,0xd5 = mrs x9, rmr_el3 0x09,0xc1,0x38,0xd5 = mrs x9, isr_el1 0x29,0xd0,0x38,0xd5 = mrs x9, contextidr_el1 0x29,0xd0,0x3d,0xd5 = mrs x9, contextidr_el12 // 0x29,0xd0,0x3c,0xd5 = mrs x9, contextdir_el2 0x49,0xd0,0x3b,0xd5 = mrs x9, tpidr_el0 0x49,0xd0,0x3c,0xd5 = mrs x9, tpidr_el2 0x49,0xd0,0x3e,0xd5 = mrs x9, tpidr_el3 0x69,0xd0,0x3b,0xd5 = mrs x9, tpidrro_el0 0x89,0xd0,0x38,0xd5 = mrs x9, tpidr_el1 0x09,0xe0,0x3b,0xd5 = mrs x9, cntfrq_el0 0x29,0xe0,0x3b,0xd5 = mrs x9, cntpct_el0 0x49,0xe0,0x3b,0xd5 = mrs x9, cntvct_el0 0x69,0xe0,0x3c,0xd5 = mrs x9, cntvoff_el2 0x09,0xe1,0x38,0xd5 = mrs x9, cntkctl_el1 0x09,0xe1,0x3d,0xd5 = mrs x9, cntkctl_el12 0x09,0xe1,0x3c,0xd5 = mrs x9, cnthctl_el2 0x09,0xe2,0x3b,0xd5 = mrs x9, cntp_tval_el0 0x09,0xe2,0x3d,0xd5 = mrs x9, cntp_tval_el02 0x09,0xe2,0x3c,0xd5 = mrs x9, cnthp_tval_el2 0x09,0xe2,0x3f,0xd5 = mrs x9, cntps_tval_el1 0x29,0xe2,0x3b,0xd5 = mrs x9, cntp_ctl_el0 0x29,0xe2,0x3c,0xd5 = mrs x9, cnthp_ctl_el2 0x29,0xe2,0x3f,0xd5 = mrs x9, cntps_ctl_el1 0x49,0xe2,0x3b,0xd5 = mrs x9, cntp_cval_el0 0x49,0xe2,0x3d,0xd5 = mrs x9, cntp_cval_el02 0x49,0xe2,0x3c,0xd5 = mrs x9, cnthp_cval_el2 // 0x20,0xe3,0x3c,0xd5 = mrs x9, cnthv_ctl_el2 0x49,0xe3,0x3c,0xd5 = mrs x9, cnthv_cval_el2 0x09,0xe3,0x3c,0xd5 = mrs x9, cnthv_tval_el2 0x49,0xe2,0x3f,0xd5 = mrs x9, cntps_cval_el1 0x09,0xe3,0x3b,0xd5 = mrs x9, cntv_tval_el0 0x29,0xe3,0x3b,0xd5 = mrs x9, cntv_ctl_el0 0x29,0xe3,0x3d,0xd5 = mrs x9, cntv_ctl_el02 0x49,0xe3,0x3b,0xd5 = mrs x9, cntv_cval_el0 0x49,0xe3,0x3d,0xd5 = mrs x9, cntv_cval_el02 0x09,0xe8,0x3b,0xd5 = mrs x9, pmevcntr0_el0 0x29,0xe8,0x3b,0xd5 = mrs x9, pmevcntr1_el0 0x49,0xe8,0x3b,0xd5 = mrs x9, pmevcntr2_el0 0x69,0xe8,0x3b,0xd5 = mrs x9, pmevcntr3_el0 0x89,0xe8,0x3b,0xd5 = mrs x9, pmevcntr4_el0 0xa9,0xe8,0x3b,0xd5 = mrs x9, pmevcntr5_el0 0xc9,0xe8,0x3b,0xd5 = mrs x9, pmevcntr6_el0 0xe9,0xe8,0x3b,0xd5 = mrs x9, pmevcntr7_el0 0x09,0xe9,0x3b,0xd5 = mrs x9, pmevcntr8_el0 0x29,0xe9,0x3b,0xd5 = mrs x9, pmevcntr9_el0 0x49,0xe9,0x3b,0xd5 = mrs x9, pmevcntr10_el0 0x69,0xe9,0x3b,0xd5 = mrs x9, pmevcntr11_el0 0x89,0xe9,0x3b,0xd5 = mrs x9, pmevcntr12_el0 0xa9,0xe9,0x3b,0xd5 = mrs x9, pmevcntr13_el0 0xc9,0xe9,0x3b,0xd5 = mrs x9, pmevcntr14_el0 0xe9,0xe9,0x3b,0xd5 = mrs x9, pmevcntr15_el0 0x09,0xea,0x3b,0xd5 = mrs x9, pmevcntr16_el0 0x29,0xea,0x3b,0xd5 = mrs x9, pmevcntr17_el0 0x49,0xea,0x3b,0xd5 = mrs x9, pmevcntr18_el0 0x69,0xea,0x3b,0xd5 = mrs x9, pmevcntr19_el0 0x89,0xea,0x3b,0xd5 = mrs x9, pmevcntr20_el0 0xa9,0xea,0x3b,0xd5 = mrs x9, pmevcntr21_el0 0xc9,0xea,0x3b,0xd5 = mrs x9, pmevcntr22_el0 0xe9,0xea,0x3b,0xd5 = mrs x9, pmevcntr23_el0 0x09,0xeb,0x3b,0xd5 = mrs x9, pmevcntr24_el0 0x29,0xeb,0x3b,0xd5 = mrs x9, pmevcntr25_el0 0x49,0xeb,0x3b,0xd5 = mrs x9, pmevcntr26_el0 0x69,0xeb,0x3b,0xd5 = mrs x9, pmevcntr27_el0 0x89,0xeb,0x3b,0xd5 = mrs x9, pmevcntr28_el0 0xa9,0xeb,0x3b,0xd5 = mrs x9, pmevcntr29_el0 0xc9,0xeb,0x3b,0xd5 = mrs x9, pmevcntr30_el0 0xe9,0xef,0x3b,0xd5 = mrs x9, pmccfiltr_el0 0x09,0xec,0x3b,0xd5 = mrs x9, pmevtyper0_el0 0x29,0xec,0x3b,0xd5 = mrs x9, pmevtyper1_el0 0x49,0xec,0x3b,0xd5 = mrs x9, pmevtyper2_el0 0x69,0xec,0x3b,0xd5 = mrs x9, pmevtyper3_el0 0x89,0xec,0x3b,0xd5 = mrs x9, pmevtyper4_el0 0xa9,0xec,0x3b,0xd5 = mrs x9, pmevtyper5_el0 0xc9,0xec,0x3b,0xd5 = mrs x9, pmevtyper6_el0 0xe9,0xec,0x3b,0xd5 = mrs x9, pmevtyper7_el0 0x09,0xed,0x3b,0xd5 = mrs x9, pmevtyper8_el0 0x29,0xed,0x3b,0xd5 = mrs x9, pmevtyper9_el0 0x49,0xed,0x3b,0xd5 = mrs x9, pmevtyper10_el0 0x69,0xed,0x3b,0xd5 = mrs x9, pmevtyper11_el0 0x89,0xed,0x3b,0xd5 = mrs x9, pmevtyper12_el0 0xa9,0xed,0x3b,0xd5 = mrs x9, pmevtyper13_el0 0xc9,0xed,0x3b,0xd5 = mrs x9, pmevtyper14_el0 0xe9,0xed,0x3b,0xd5 = mrs x9, pmevtyper15_el0 0x09,0xee,0x3b,0xd5 = mrs x9, pmevtyper16_el0 0x29,0xee,0x3b,0xd5 = mrs x9, pmevtyper17_el0 0x49,0xee,0x3b,0xd5 = mrs x9, pmevtyper18_el0 0x69,0xee,0x3b,0xd5 = mrs x9, pmevtyper19_el0 0x89,0xee,0x3b,0xd5 = mrs x9, pmevtyper20_el0 0xa9,0xee,0x3b,0xd5 = mrs x9, pmevtyper21_el0 0xc9,0xee,0x3b,0xd5 = mrs x9, pmevtyper22_el0 0xe9,0xee,0x3b,0xd5 = mrs x9, pmevtyper23_el0 0x09,0xef,0x3b,0xd5 = mrs x9, pmevtyper24_el0 0x29,0xef,0x3b,0xd5 = mrs x9, pmevtyper25_el0 0x49,0xef,0x3b,0xd5 = mrs x9, pmevtyper26_el0 0x69,0xef,0x3b,0xd5 = mrs x9, pmevtyper27_el0 0x89,0xef,0x3b,0xd5 = mrs x9, pmevtyper28_el0 0xa9,0xef,0x3b,0xd5 = mrs x9, pmevtyper29_el0 0xc9,0xef,0x3b,0xd5 = mrs x9, pmevtyper30_el0 0xe9,0x99,0x38,0xd5 = mrs x9, pmsidr_el1 0xe9,0x9a,0x38,0xd5 = mrs x9, pmbidr_el1 0x09,0x9a,0x38,0xd5 = mrs x9, pmblimitr_el1 0x29,0x9a,0x38,0xd5 = mrs x9, pmbptr_el1 0x69,0x9a,0x38,0xd5 = mrs x9, pmbsr_el1 0x09,0x99,0x38,0xd5 = mrs x9, pmscr_el1 0x09,0x99,0x3d,0xd5 = mrs x9, pmscr_el12 0x09,0x99,0x3c,0xd5 = mrs x9, pmscr_el2 0x49,0x99,0x38,0xd5 = mrs x9, pmsicr_el1 0x69,0x99,0x38,0xd5 = mrs x9, pmsirr_el1 0x89,0x99,0x38,0xd5 = mrs x9, pmsfcr_el1 0xa9,0x99,0x38,0xd5 = mrs x9, pmsevfr_el1 0xc9,0x99,0x38,0xd5 = mrs x9, pmslatfr_el1 0xac,0xf1,0x3f,0xd5 = mrs x12, s3_7_c15_c1_5 0xed,0xbf,0x3a,0xd5 = mrs x13, s3_2_c11_c15_7 0x0c,0xf0,0x18,0xd5 = msr s3_0_c15_c0_0, x12 0xe5,0xbd,0x1f,0xd5 = msr s3_7_c11_c13_7, x5 0x01,0x00,0x00,0x14 = b #4 0x00,0x00,0x00,0x94 = bl #0 0xff,0xff,0xff,0x15 = b #134217724 0x00,0x00,0x00,0x96 = bl #-134217728 0x80,0x02,0x1f,0xd6 = br x20 0xe0,0x03,0x3f,0xd6 = blr xzr 0x40,0x01,0x5f,0xd6 = ret x10 0xc0,0x03,0x5f,0xd6 = ret 0xe0,0x03,0x9f,0xd6 = eret 0xe0,0x03,0xbf,0xd6 = drps capstone-sys-0.15.0/capstone/suite/MC/AArch64/gicv3-regs.s.cs000064400000000000000000000113710072674642500215270ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x08,0xcc,0x38,0xd5 = mrs x8, icc_iar1_el1 0x1a,0xc8,0x38,0xd5 = mrs x26, icc_iar0_el1 0x42,0xcc,0x38,0xd5 = mrs x2, icc_hppir1_el1 0x51,0xc8,0x38,0xd5 = mrs x17, icc_hppir0_el1 0x7d,0xcb,0x38,0xd5 = mrs x29, icc_rpr_el1 0x24,0xcb,0x3c,0xd5 = mrs x4, ich_vtr_el2 0x78,0xcb,0x3c,0xd5 = mrs x24, ich_eisr_el2 0xa9,0xcb,0x3c,0xd5 = mrs x9, ich_elrsr_el2 0x78,0xcc,0x38,0xd5 = mrs x24, icc_bpr1_el1 0x6e,0xc8,0x38,0xd5 = mrs x14, icc_bpr0_el1 0x13,0x46,0x38,0xd5 = mrs x19, icc_pmr_el1 0x97,0xcc,0x38,0xd5 = mrs x23, icc_ctlr_el1 0x94,0xcc,0x3e,0xd5 = mrs x20, icc_ctlr_el3 0xbc,0xcc,0x38,0xd5 = mrs x28, icc_sre_el1 0xb9,0xc9,0x3c,0xd5 = mrs x25, icc_sre_el2 0xa8,0xcc,0x3e,0xd5 = mrs x8, icc_sre_el3 0xd6,0xcc,0x38,0xd5 = mrs x22, icc_igrpen0_el1 0xe5,0xcc,0x38,0xd5 = mrs x5, icc_igrpen1_el1 0xe7,0xcc,0x3e,0xd5 = mrs x7, icc_igrpen1_el3 0x16,0xcd,0x38,0xd5 = mrs x22, icc_seien_el1 0x84,0xc8,0x38,0xd5 = mrs x4, icc_ap0r0_el1 0xab,0xc8,0x38,0xd5 = mrs x11, icc_ap0r1_el1 0xdb,0xc8,0x38,0xd5 = mrs x27, icc_ap0r2_el1 0xf5,0xc8,0x38,0xd5 = mrs x21, icc_ap0r3_el1 0x02,0xc9,0x38,0xd5 = mrs x2, icc_ap1r0_el1 0x35,0xc9,0x38,0xd5 = mrs x21, icc_ap1r1_el1 0x4a,0xc9,0x38,0xd5 = mrs x10, icc_ap1r2_el1 0x7b,0xc9,0x38,0xd5 = mrs x27, icc_ap1r3_el1 0x14,0xc8,0x3c,0xd5 = mrs x20, ich_ap0r0_el2 0x35,0xc8,0x3c,0xd5 = mrs x21, ich_ap0r1_el2 0x45,0xc8,0x3c,0xd5 = mrs x5, ich_ap0r2_el2 0x64,0xc8,0x3c,0xd5 = mrs x4, ich_ap0r3_el2 0x0f,0xc9,0x3c,0xd5 = mrs x15, ich_ap1r0_el2 0x2c,0xc9,0x3c,0xd5 = mrs x12, ich_ap1r1_el2 0x5b,0xc9,0x3c,0xd5 = mrs x27, ich_ap1r2_el2 0x74,0xc9,0x3c,0xd5 = mrs x20, ich_ap1r3_el2 0x0a,0xcb,0x3c,0xd5 = mrs x10, ich_hcr_el2 0x5b,0xcb,0x3c,0xd5 = mrs x27, ich_misr_el2 0xe6,0xcb,0x3c,0xd5 = mrs x6, ich_vmcr_el2 0x93,0xc9,0x3c,0xd5 = mrs x19, ich_vseir_el2 0x03,0xcc,0x3c,0xd5 = mrs x3, ich_lr0_el2 0x21,0xcc,0x3c,0xd5 = mrs x1, ich_lr1_el2 0x56,0xcc,0x3c,0xd5 = mrs x22, ich_lr2_el2 0x75,0xcc,0x3c,0xd5 = mrs x21, ich_lr3_el2 0x86,0xcc,0x3c,0xd5 = mrs x6, ich_lr4_el2 0xaa,0xcc,0x3c,0xd5 = mrs x10, ich_lr5_el2 0xcb,0xcc,0x3c,0xd5 = mrs x11, ich_lr6_el2 0xec,0xcc,0x3c,0xd5 = mrs x12, ich_lr7_el2 0x00,0xcd,0x3c,0xd5 = mrs x0, ich_lr8_el2 0x35,0xcd,0x3c,0xd5 = mrs x21, ich_lr9_el2 0x4d,0xcd,0x3c,0xd5 = mrs x13, ich_lr10_el2 0x7a,0xcd,0x3c,0xd5 = mrs x26, ich_lr11_el2 0x81,0xcd,0x3c,0xd5 = mrs x1, ich_lr12_el2 0xa8,0xcd,0x3c,0xd5 = mrs x8, ich_lr13_el2 0xc2,0xcd,0x3c,0xd5 = mrs x2, ich_lr14_el2 0xe8,0xcd,0x3c,0xd5 = mrs x8, ich_lr15_el2 0x3b,0xcc,0x18,0xd5 = msr icc_eoir1_el1, x27 0x25,0xc8,0x18,0xd5 = msr icc_eoir0_el1, x5 0x2d,0xcb,0x18,0xd5 = msr icc_dir_el1, x13 0xb5,0xcb,0x18,0xd5 = msr icc_sgi1r_el1, x21 0xd9,0xcb,0x18,0xd5 = msr icc_asgi1r_el1, x25 0xfc,0xcb,0x18,0xd5 = msr icc_sgi0r_el1, x28 0x67,0xcc,0x18,0xd5 = msr icc_bpr1_el1, x7 0x69,0xc8,0x18,0xd5 = msr icc_bpr0_el1, x9 0x1d,0x46,0x18,0xd5 = msr icc_pmr_el1, x29 0x98,0xcc,0x18,0xd5 = msr icc_ctlr_el1, x24 0x80,0xcc,0x1e,0xd5 = msr icc_ctlr_el3, x0 0xa2,0xcc,0x18,0xd5 = msr icc_sre_el1, x2 0xa5,0xc9,0x1c,0xd5 = msr icc_sre_el2, x5 0xaa,0xcc,0x1e,0xd5 = msr icc_sre_el3, x10 0xd6,0xcc,0x18,0xd5 = msr icc_igrpen0_el1, x22 0xeb,0xcc,0x18,0xd5 = msr icc_igrpen1_el1, x11 0xe8,0xcc,0x1e,0xd5 = msr icc_igrpen1_el3, x8 0x04,0xcd,0x18,0xd5 = msr icc_seien_el1, x4 0x9b,0xc8,0x18,0xd5 = msr icc_ap0r0_el1, x27 0xa5,0xc8,0x18,0xd5 = msr icc_ap0r1_el1, x5 0xd4,0xc8,0x18,0xd5 = msr icc_ap0r2_el1, x20 0xe0,0xc8,0x18,0xd5 = msr icc_ap0r3_el1, x0 0x02,0xc9,0x18,0xd5 = msr icc_ap1r0_el1, x2 0x3d,0xc9,0x18,0xd5 = msr icc_ap1r1_el1, x29 0x57,0xc9,0x18,0xd5 = msr icc_ap1r2_el1, x23 0x6b,0xc9,0x18,0xd5 = msr icc_ap1r3_el1, x11 0x02,0xc8,0x1c,0xd5 = msr ich_ap0r0_el2, x2 0x3b,0xc8,0x1c,0xd5 = msr ich_ap0r1_el2, x27 0x47,0xc8,0x1c,0xd5 = msr ich_ap0r2_el2, x7 0x61,0xc8,0x1c,0xd5 = msr ich_ap0r3_el2, x1 0x07,0xc9,0x1c,0xd5 = msr ich_ap1r0_el2, x7 0x2c,0xc9,0x1c,0xd5 = msr ich_ap1r1_el2, x12 0x4e,0xc9,0x1c,0xd5 = msr ich_ap1r2_el2, x14 0x6d,0xc9,0x1c,0xd5 = msr ich_ap1r3_el2, x13 0x01,0xcb,0x1c,0xd5 = msr ich_hcr_el2, x1 0x4a,0xcb,0x1c,0xd5 = msr ich_misr_el2, x10 0xf8,0xcb,0x1c,0xd5 = msr ich_vmcr_el2, x24 0x9d,0xc9,0x1c,0xd5 = msr ich_vseir_el2, x29 0x1a,0xcc,0x1c,0xd5 = msr ich_lr0_el2, x26 0x29,0xcc,0x1c,0xd5 = msr ich_lr1_el2, x9 0x52,0xcc,0x1c,0xd5 = msr ich_lr2_el2, x18 0x7a,0xcc,0x1c,0xd5 = msr ich_lr3_el2, x26 0x96,0xcc,0x1c,0xd5 = msr ich_lr4_el2, x22 0xba,0xcc,0x1c,0xd5 = msr ich_lr5_el2, x26 0xdb,0xcc,0x1c,0xd5 = msr ich_lr6_el2, x27 0xe8,0xcc,0x1c,0xd5 = msr ich_lr7_el2, x8 0x11,0xcd,0x1c,0xd5 = msr ich_lr8_el2, x17 0x33,0xcd,0x1c,0xd5 = msr ich_lr9_el2, x19 0x51,0xcd,0x1c,0xd5 = msr ich_lr10_el2, x17 0x65,0xcd,0x1c,0xd5 = msr ich_lr11_el2, x5 0x9d,0xcd,0x1c,0xd5 = msr ich_lr12_el2, x29 0xa2,0xcd,0x1c,0xd5 = msr ich_lr13_el2, x2 0xcd,0xcd,0x1c,0xd5 = msr ich_lr14_el2, x13 0xfb,0xcd,0x1c,0xd5 = msr ich_lr15_el2, x27 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-2velem.s.cs000064400000000000000000000131040072674642500217010ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x08,0x82,0x2f = mla v0.2s, v1.2s, v2.s[2] 0x20,0x08,0x96,0x2f = mla v0.2s, v1.2s, v22.s[2] 0x03,0x01,0xa2,0x6f = mla v3.4s, v8.4s, v2.s[1] 0x03,0x09,0xb6,0x6f = mla v3.4s, v8.4s, v22.s[3] 0x20,0x00,0x62,0x2f = mla v0.4h, v1.4h, v2.h[2] 0x20,0x00,0x6f,0x2f = mla v0.4h, v1.4h, v15.h[2] 0x20,0x08,0x72,0x6f = mla v0.8h, v1.8h, v2.h[7] 0x20,0x08,0x6e,0x6f = mla v0.8h, v1.8h, v14.h[6] 0x20,0x48,0x82,0x2f = mls v0.2s, v1.2s, v2.s[2] 0x20,0x48,0x96,0x2f = mls v0.2s, v1.2s, v22.s[2] 0x03,0x41,0xa2,0x6f = mls v3.4s, v8.4s, v2.s[1] 0x03,0x49,0xb6,0x6f = mls v3.4s, v8.4s, v22.s[3] 0x20,0x40,0x62,0x2f = mls v0.4h, v1.4h, v2.h[2] 0x20,0x40,0x6f,0x2f = mls v0.4h, v1.4h, v15.h[2] 0x20,0x48,0x72,0x6f = mls v0.8h, v1.8h, v2.h[7] 0x20,0x48,0x6e,0x6f = mls v0.8h, v1.8h, v14.h[6] 0x20,0x18,0x82,0x0f = fmla v0.2s, v1.2s, v2.s[2] 0x20,0x18,0x96,0x0f = fmla v0.2s, v1.2s, v22.s[2] 0x03,0x11,0xa2,0x4f = fmla v3.4s, v8.4s, v2.s[1] 0x03,0x19,0xb6,0x4f = fmla v3.4s, v8.4s, v22.s[3] 0x20,0x18,0xc2,0x4f = fmla v0.2d, v1.2d, v2.d[1] 0x20,0x18,0xd6,0x4f = fmla v0.2d, v1.2d, v22.d[1] 0x20,0x58,0x82,0x0f = fmls v0.2s, v1.2s, v2.s[2] 0x20,0x58,0x96,0x0f = fmls v0.2s, v1.2s, v22.s[2] 0x03,0x51,0xa2,0x4f = fmls v3.4s, v8.4s, v2.s[1] 0x03,0x59,0xb6,0x4f = fmls v3.4s, v8.4s, v22.s[3] 0x20,0x58,0xc2,0x4f = fmls v0.2d, v1.2d, v2.d[1] 0x20,0x58,0xd6,0x4f = fmls v0.2d, v1.2d, v22.d[1] 0x20,0x20,0x62,0x0f = smlal v0.4s, v1.4h, v2.h[2] 0x20,0x28,0x82,0x0f = smlal v0.2d, v1.2s, v2.s[2] 0x20,0x28,0x96,0x0f = smlal v0.2d, v1.2s, v22.s[2] 0x20,0x20,0x61,0x4f = smlal2 v0.4s, v1.8h, v1.h[2] 0x20,0x28,0x81,0x4f = smlal2 v0.2d, v1.4s, v1.s[2] 0x20,0x28,0x96,0x4f = smlal2 v0.2d, v1.4s, v22.s[2] 0x20,0x60,0x62,0x0f = smlsl v0.4s, v1.4h, v2.h[2] 0x20,0x68,0x82,0x0f = smlsl v0.2d, v1.2s, v2.s[2] 0x20,0x68,0x96,0x0f = smlsl v0.2d, v1.2s, v22.s[2] 0x20,0x60,0x61,0x4f = smlsl2 v0.4s, v1.8h, v1.h[2] 0x20,0x68,0x81,0x4f = smlsl2 v0.2d, v1.4s, v1.s[2] 0x20,0x68,0x96,0x4f = smlsl2 v0.2d, v1.4s, v22.s[2] 0x20,0x30,0x62,0x0f = sqdmlal v0.4s, v1.4h, v2.h[2] 0x20,0x38,0x82,0x0f = sqdmlal v0.2d, v1.2s, v2.s[2] 0x20,0x38,0x96,0x0f = sqdmlal v0.2d, v1.2s, v22.s[2] 0x20,0x30,0x61,0x4f = sqdmlal2 v0.4s, v1.8h, v1.h[2] 0x20,0x38,0x81,0x4f = sqdmlal2 v0.2d, v1.4s, v1.s[2] 0x20,0x38,0x96,0x4f = sqdmlal2 v0.2d, v1.4s, v22.s[2] 0x20,0x20,0x62,0x2f = umlal v0.4s, v1.4h, v2.h[2] 0x20,0x28,0x82,0x2f = umlal v0.2d, v1.2s, v2.s[2] 0x20,0x28,0x96,0x2f = umlal v0.2d, v1.2s, v22.s[2] 0x20,0x20,0x61,0x6f = umlal2 v0.4s, v1.8h, v1.h[2] 0x20,0x28,0x81,0x6f = umlal2 v0.2d, v1.4s, v1.s[2] 0x20,0x28,0x96,0x6f = umlal2 v0.2d, v1.4s, v22.s[2] 0x20,0x60,0x62,0x2f = umlsl v0.4s, v1.4h, v2.h[2] 0x20,0x68,0x82,0x2f = umlsl v0.2d, v1.2s, v2.s[2] 0x20,0x68,0x96,0x2f = umlsl v0.2d, v1.2s, v22.s[2] 0x20,0x60,0x61,0x6f = umlsl2 v0.4s, v1.8h, v1.h[2] 0x20,0x68,0x81,0x6f = umlsl2 v0.2d, v1.4s, v1.s[2] 0x20,0x68,0x96,0x6f = umlsl2 v0.2d, v1.4s, v22.s[2] 0x20,0x70,0x62,0x0f = sqdmlsl v0.4s, v1.4h, v2.h[2] 0x20,0x78,0x82,0x0f = sqdmlsl v0.2d, v1.2s, v2.s[2] 0x20,0x78,0x96,0x0f = sqdmlsl v0.2d, v1.2s, v22.s[2] 0x20,0x70,0x61,0x4f = sqdmlsl2 v0.4s, v1.8h, v1.h[2] 0x20,0x78,0x81,0x4f = sqdmlsl2 v0.2d, v1.4s, v1.s[2] 0x20,0x78,0x96,0x4f = sqdmlsl2 v0.2d, v1.4s, v22.s[2] 0x20,0x80,0x62,0x0f = mul v0.4h, v1.4h, v2.h[2] 0x20,0x80,0x62,0x4f = mul v0.8h, v1.8h, v2.h[2] 0x20,0x88,0x82,0x0f = mul v0.2s, v1.2s, v2.s[2] 0x20,0x88,0x96,0x0f = mul v0.2s, v1.2s, v22.s[2] 0x20,0x88,0x82,0x4f = mul v0.4s, v1.4s, v2.s[2] 0x20,0x88,0x96,0x4f = mul v0.4s, v1.4s, v22.s[2] 0x20,0x98,0x82,0x0f = fmul v0.2s, v1.2s, v2.s[2] 0x20,0x98,0x96,0x0f = fmul v0.2s, v1.2s, v22.s[2] 0x20,0x98,0x82,0x4f = fmul v0.4s, v1.4s, v2.s[2] 0x20,0x98,0x96,0x4f = fmul v0.4s, v1.4s, v22.s[2] 0x20,0x98,0xc2,0x4f = fmul v0.2d, v1.2d, v2.d[1] 0x20,0x98,0xd6,0x4f = fmul v0.2d, v1.2d, v22.d[1] 0x20,0x98,0x82,0x2f = fmulx v0.2s, v1.2s, v2.s[2] 0x20,0x98,0x96,0x2f = fmulx v0.2s, v1.2s, v22.s[2] 0x20,0x98,0x82,0x6f = fmulx v0.4s, v1.4s, v2.s[2] 0x20,0x98,0x96,0x6f = fmulx v0.4s, v1.4s, v22.s[2] 0x20,0x98,0xc2,0x6f = fmulx v0.2d, v1.2d, v2.d[1] 0x20,0x98,0xd6,0x6f = fmulx v0.2d, v1.2d, v22.d[1] 0x20,0xa0,0x62,0x0f = smull v0.4s, v1.4h, v2.h[2] 0x20,0xa8,0x82,0x0f = smull v0.2d, v1.2s, v2.s[2] 0x20,0xa8,0x96,0x0f = smull v0.2d, v1.2s, v22.s[2] 0x20,0xa0,0x62,0x4f = smull2 v0.4s, v1.8h, v2.h[2] 0x20,0xa8,0x82,0x4f = smull2 v0.2d, v1.4s, v2.s[2] 0x20,0xa8,0x96,0x4f = smull2 v0.2d, v1.4s, v22.s[2] 0x20,0xa0,0x62,0x2f = umull v0.4s, v1.4h, v2.h[2] 0x20,0xa8,0x82,0x2f = umull v0.2d, v1.2s, v2.s[2] 0x20,0xa8,0x96,0x2f = umull v0.2d, v1.2s, v22.s[2] 0x20,0xa0,0x62,0x6f = umull2 v0.4s, v1.8h, v2.h[2] 0x20,0xa8,0x82,0x6f = umull2 v0.2d, v1.4s, v2.s[2] 0x20,0xa8,0x96,0x6f = umull2 v0.2d, v1.4s, v22.s[2] 0x20,0xb0,0x62,0x0f = sqdmull v0.4s, v1.4h, v2.h[2] 0x20,0xb8,0x82,0x0f = sqdmull v0.2d, v1.2s, v2.s[2] 0x20,0xb8,0x96,0x0f = sqdmull v0.2d, v1.2s, v22.s[2] 0x20,0xb0,0x62,0x4f = sqdmull2 v0.4s, v1.8h, v2.h[2] 0x20,0xb8,0x82,0x4f = sqdmull2 v0.2d, v1.4s, v2.s[2] 0x20,0xb8,0x96,0x4f = sqdmull2 v0.2d, v1.4s, v22.s[2] 0x20,0xc0,0x62,0x0f = sqdmulh v0.4h, v1.4h, v2.h[2] 0x20,0xc0,0x62,0x4f = sqdmulh v0.8h, v1.8h, v2.h[2] 0x20,0xc8,0x82,0x0f = sqdmulh v0.2s, v1.2s, v2.s[2] 0x20,0xc8,0x96,0x0f = sqdmulh v0.2s, v1.2s, v22.s[2] 0x20,0xc8,0x82,0x4f = sqdmulh v0.4s, v1.4s, v2.s[2] 0x20,0xc8,0x96,0x4f = sqdmulh v0.4s, v1.4s, v22.s[2] 0x20,0xd0,0x62,0x0f = sqrdmulh v0.4h, v1.4h, v2.h[2] 0x20,0xd0,0x62,0x4f = sqrdmulh v0.8h, v1.8h, v2.h[2] 0x20,0xd8,0x82,0x0f = sqrdmulh v0.2s, v1.2s, v2.s[2] 0x20,0xd8,0x96,0x0f = sqrdmulh v0.2s, v1.2s, v22.s[2] 0x20,0xd8,0x82,0x4f = sqrdmulh v0.4s, v1.4s, v2.s[2] 0x20,0xd8,0x96,0x4f = sqrdmulh v0.4s, v1.4s, v22.s[2] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-3vdiff.s.cs000064400000000000000000000155110072674642500216740ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x00,0x22,0x0e = saddl v0.8h, v1.8b, v2.8b 0x20,0x00,0x62,0x0e = saddl v0.4s, v1.4h, v2.4h 0x20,0x00,0xa2,0x0e = saddl v0.2d, v1.2s, v2.2s 0x20,0x00,0x62,0x4e = saddl2 v0.4s, v1.8h, v2.8h 0x20,0x00,0x22,0x4e = saddl2 v0.8h, v1.16b, v2.16b 0x20,0x00,0xa2,0x4e = saddl2 v0.2d, v1.4s, v2.4s 0x20,0x00,0x22,0x2e = uaddl v0.8h, v1.8b, v2.8b 0x20,0x00,0x62,0x2e = uaddl v0.4s, v1.4h, v2.4h 0x20,0x00,0xa2,0x2e = uaddl v0.2d, v1.2s, v2.2s 0x20,0x00,0x22,0x6e = uaddl2 v0.8h, v1.16b, v2.16b 0x20,0x00,0x62,0x6e = uaddl2 v0.4s, v1.8h, v2.8h 0x20,0x00,0xa2,0x6e = uaddl2 v0.2d, v1.4s, v2.4s 0x20,0x20,0x22,0x0e = ssubl v0.8h, v1.8b, v2.8b 0x20,0x20,0x62,0x0e = ssubl v0.4s, v1.4h, v2.4h 0x20,0x20,0xa2,0x0e = ssubl v0.2d, v1.2s, v2.2s 0x20,0x20,0x22,0x4e = ssubl2 v0.8h, v1.16b, v2.16b 0x20,0x20,0x62,0x4e = ssubl2 v0.4s, v1.8h, v2.8h 0x20,0x20,0xa2,0x4e = ssubl2 v0.2d, v1.4s, v2.4s 0x20,0x20,0x22,0x2e = usubl v0.8h, v1.8b, v2.8b 0x20,0x20,0x62,0x2e = usubl v0.4s, v1.4h, v2.4h 0x20,0x20,0xa2,0x2e = usubl v0.2d, v1.2s, v2.2s 0x20,0x20,0x22,0x6e = usubl2 v0.8h, v1.16b, v2.16b 0x20,0x20,0x62,0x6e = usubl2 v0.4s, v1.8h, v2.8h 0x20,0x20,0xa2,0x6e = usubl2 v0.2d, v1.4s, v2.4s 0x20,0x50,0x22,0x0e = sabal v0.8h, v1.8b, v2.8b 0x20,0x50,0x62,0x0e = sabal v0.4s, v1.4h, v2.4h 0x20,0x50,0xa2,0x0e = sabal v0.2d, v1.2s, v2.2s 0x20,0x50,0x22,0x4e = sabal2 v0.8h, v1.16b, v2.16b 0x20,0x50,0x62,0x4e = sabal2 v0.4s, v1.8h, v2.8h 0x20,0x50,0xa2,0x4e = sabal2 v0.2d, v1.4s, v2.4s 0x20,0x50,0x22,0x2e = uabal v0.8h, v1.8b, v2.8b 0x20,0x50,0x62,0x2e = uabal v0.4s, v1.4h, v2.4h 0x20,0x50,0xa2,0x2e = uabal v0.2d, v1.2s, v2.2s 0x20,0x50,0x22,0x6e = uabal2 v0.8h, v1.16b, v2.16b 0x20,0x50,0x62,0x6e = uabal2 v0.4s, v1.8h, v2.8h 0x20,0x50,0xa2,0x6e = uabal2 v0.2d, v1.4s, v2.4s 0x20,0x70,0x22,0x0e = sabdl v0.8h, v1.8b, v2.8b 0x20,0x70,0x62,0x0e = sabdl v0.4s, v1.4h, v2.4h 0x20,0x70,0xa2,0x0e = sabdl v0.2d, v1.2s, v2.2s 0x20,0x70,0x22,0x4e = sabdl2 v0.8h, v1.16b, v2.16b 0x20,0x70,0x62,0x4e = sabdl2 v0.4s, v1.8h, v2.8h 0x20,0x70,0xa2,0x4e = sabdl2 v0.2d, v1.4s, v2.4s 0x20,0x70,0x22,0x2e = uabdl v0.8h, v1.8b, v2.8b 0x20,0x70,0x62,0x2e = uabdl v0.4s, v1.4h, v2.4h 0x20,0x70,0xa2,0x2e = uabdl v0.2d, v1.2s, v2.2s 0x20,0x70,0x22,0x6e = uabdl2 v0.8h, v1.16b, v2.16b 0x20,0x70,0x62,0x6e = uabdl2 v0.4s, v1.8h, v2.8h 0x20,0x70,0xa2,0x6e = uabdl2 v0.2d, v1.4s, v2.4s 0x20,0x80,0x22,0x0e = smlal v0.8h, v1.8b, v2.8b 0x20,0x80,0x62,0x0e = smlal v0.4s, v1.4h, v2.4h 0x20,0x80,0xa2,0x0e = smlal v0.2d, v1.2s, v2.2s 0x20,0x80,0x22,0x4e = smlal2 v0.8h, v1.16b, v2.16b 0x20,0x80,0x62,0x4e = smlal2 v0.4s, v1.8h, v2.8h 0x20,0x80,0xa2,0x4e = smlal2 v0.2d, v1.4s, v2.4s 0x20,0x80,0x22,0x2e = umlal v0.8h, v1.8b, v2.8b 0x20,0x80,0x62,0x2e = umlal v0.4s, v1.4h, v2.4h 0x20,0x80,0xa2,0x2e = umlal v0.2d, v1.2s, v2.2s 0x20,0x80,0x22,0x6e = umlal2 v0.8h, v1.16b, v2.16b 0x20,0x80,0x62,0x6e = umlal2 v0.4s, v1.8h, v2.8h 0x20,0x80,0xa2,0x6e = umlal2 v0.2d, v1.4s, v2.4s 0x20,0xa0,0x22,0x0e = smlsl v0.8h, v1.8b, v2.8b 0x20,0xa0,0x62,0x0e = smlsl v0.4s, v1.4h, v2.4h 0x20,0xa0,0xa2,0x0e = smlsl v0.2d, v1.2s, v2.2s 0x20,0xa0,0x22,0x4e = smlsl2 v0.8h, v1.16b, v2.16b 0x20,0xa0,0x62,0x4e = smlsl2 v0.4s, v1.8h, v2.8h 0x20,0xa0,0xa2,0x4e = smlsl2 v0.2d, v1.4s, v2.4s 0x20,0xa0,0x22,0x2e = umlsl v0.8h, v1.8b, v2.8b 0x20,0xa0,0x62,0x2e = umlsl v0.4s, v1.4h, v2.4h 0x20,0xa0,0xa2,0x2e = umlsl v0.2d, v1.2s, v2.2s 0x20,0xa0,0x22,0x6e = umlsl2 v0.8h, v1.16b, v2.16b 0x20,0xa0,0x62,0x6e = umlsl2 v0.4s, v1.8h, v2.8h 0x20,0xa0,0xa2,0x6e = umlsl2 v0.2d, v1.4s, v2.4s 0x20,0xc0,0x22,0x0e = smull v0.8h, v1.8b, v2.8b 0x20,0xc0,0x62,0x0e = smull v0.4s, v1.4h, v2.4h 0x20,0xc0,0xa2,0x0e = smull v0.2d, v1.2s, v2.2s 0x20,0xc0,0x22,0x4e = smull2 v0.8h, v1.16b, v2.16b 0x20,0xc0,0x62,0x4e = smull2 v0.4s, v1.8h, v2.8h 0x20,0xc0,0xa2,0x4e = smull2 v0.2d, v1.4s, v2.4s 0x20,0xc0,0x22,0x2e = umull v0.8h, v1.8b, v2.8b 0x20,0xc0,0x62,0x2e = umull v0.4s, v1.4h, v2.4h 0x20,0xc0,0xa2,0x2e = umull v0.2d, v1.2s, v2.2s 0x20,0xc0,0x22,0x6e = umull2 v0.8h, v1.16b, v2.16b 0x20,0xc0,0x62,0x6e = umull2 v0.4s, v1.8h, v2.8h 0x20,0xc0,0xa2,0x6e = umull2 v0.2d, v1.4s, v2.4s 0x20,0x90,0x62,0x0e = sqdmlal v0.4s, v1.4h, v2.4h 0x20,0x90,0xa2,0x0e = sqdmlal v0.2d, v1.2s, v2.2s 0x20,0x90,0x62,0x4e = sqdmlal2 v0.4s, v1.8h, v2.8h 0x20,0x90,0xa2,0x4e = sqdmlal2 v0.2d, v1.4s, v2.4s 0x20,0xb0,0x62,0x0e = sqdmlsl v0.4s, v1.4h, v2.4h 0x20,0xb0,0xa2,0x0e = sqdmlsl v0.2d, v1.2s, v2.2s 0x20,0xb0,0x62,0x4e = sqdmlsl2 v0.4s, v1.8h, v2.8h 0x20,0xb0,0xa2,0x4e = sqdmlsl2 v0.2d, v1.4s, v2.4s 0x20,0xd0,0x62,0x0e = sqdmull v0.4s, v1.4h, v2.4h 0x20,0xd0,0xa2,0x0e = sqdmull v0.2d, v1.2s, v2.2s 0x20,0xd0,0x62,0x4e = sqdmull2 v0.4s, v1.8h, v2.8h 0x20,0xd0,0xa2,0x4e = sqdmull2 v0.2d, v1.4s, v2.4s 0x20,0xe0,0x22,0x0e = pmull v0.8h, v1.8b, v2.8b 0x20,0xe0,0xe2,0x0e = pmull v0.1q, v1.1d, v2.1d 0x20,0xe0,0x22,0x4e = pmull2 v0.8h, v1.16b, v2.16b 0x20,0xe0,0xe2,0x4e = pmull2 v0.1q, v1.2d, v2.2d 0x20,0x10,0x22,0x0e = saddw v0.8h, v1.8h, v2.8b 0x20,0x10,0x62,0x0e = saddw v0.4s, v1.4s, v2.4h 0x20,0x10,0xa2,0x0e = saddw v0.2d, v1.2d, v2.2s 0x20,0x10,0x22,0x4e = saddw2 v0.8h, v1.8h, v2.16b 0x20,0x10,0x62,0x4e = saddw2 v0.4s, v1.4s, v2.8h 0x20,0x10,0xa2,0x4e = saddw2 v0.2d, v1.2d, v2.4s 0x20,0x10,0x22,0x2e = uaddw v0.8h, v1.8h, v2.8b 0x20,0x10,0x62,0x2e = uaddw v0.4s, v1.4s, v2.4h 0x20,0x10,0xa2,0x2e = uaddw v0.2d, v1.2d, v2.2s 0x20,0x10,0x22,0x6e = uaddw2 v0.8h, v1.8h, v2.16b 0x20,0x10,0x62,0x6e = uaddw2 v0.4s, v1.4s, v2.8h 0x20,0x10,0xa2,0x6e = uaddw2 v0.2d, v1.2d, v2.4s 0x20,0x30,0x22,0x0e = ssubw v0.8h, v1.8h, v2.8b 0x20,0x30,0x62,0x0e = ssubw v0.4s, v1.4s, v2.4h 0x20,0x30,0xa2,0x0e = ssubw v0.2d, v1.2d, v2.2s 0x20,0x30,0x22,0x4e = ssubw2 v0.8h, v1.8h, v2.16b 0x20,0x30,0x62,0x4e = ssubw2 v0.4s, v1.4s, v2.8h 0x20,0x30,0xa2,0x4e = ssubw2 v0.2d, v1.2d, v2.4s 0x20,0x30,0x22,0x2e = usubw v0.8h, v1.8h, v2.8b 0x20,0x30,0x62,0x2e = usubw v0.4s, v1.4s, v2.4h 0x20,0x30,0xa2,0x2e = usubw v0.2d, v1.2d, v2.2s 0x20,0x30,0x22,0x6e = usubw2 v0.8h, v1.8h, v2.16b 0x20,0x30,0x62,0x6e = usubw2 v0.4s, v1.4s, v2.8h 0x20,0x30,0xa2,0x6e = usubw2 v0.2d, v1.2d, v2.4s 0x20,0x40,0x22,0x0e = addhn v0.8b, v1.8h, v2.8h 0x20,0x40,0x62,0x0e = addhn v0.4h, v1.4s, v2.4s 0x20,0x40,0xa2,0x0e = addhn v0.2s, v1.2d, v2.2d 0x20,0x40,0x22,0x4e = addhn2 v0.16b, v1.8h, v2.8h 0x20,0x40,0x62,0x4e = addhn2 v0.8h, v1.4s, v2.4s 0x20,0x40,0xa2,0x4e = addhn2 v0.4s, v1.2d, v2.2d 0x20,0x40,0x22,0x2e = raddhn v0.8b, v1.8h, v2.8h 0x20,0x40,0x62,0x2e = raddhn v0.4h, v1.4s, v2.4s 0x20,0x40,0xa2,0x2e = raddhn v0.2s, v1.2d, v2.2d 0x20,0x40,0x22,0x6e = raddhn2 v0.16b, v1.8h, v2.8h 0x20,0x40,0x62,0x6e = raddhn2 v0.8h, v1.4s, v2.4s 0x20,0x40,0xa2,0x6e = raddhn2 v0.4s, v1.2d, v2.2d 0x20,0x60,0x22,0x2e = rsubhn v0.8b, v1.8h, v2.8h 0x20,0x60,0x62,0x2e = rsubhn v0.4h, v1.4s, v2.4s 0x20,0x60,0xa2,0x2e = rsubhn v0.2s, v1.2d, v2.2d 0x20,0x60,0x22,0x6e = rsubhn2 v0.16b, v1.8h, v2.8h 0x20,0x60,0x62,0x6e = rsubhn2 v0.8h, v1.4s, v2.4s 0x20,0x60,0xa2,0x6e = rsubhn2 v0.4s, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-aba-abd.s.cs000064400000000000000000000024360072674642500217640ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x7c,0x22,0x2e = uaba v0.8b, v1.8b, v2.8b 0x20,0x7c,0x22,0x6e = uaba v0.16b, v1.16b, v2.16b 0x20,0x7c,0x62,0x2e = uaba v0.4h, v1.4h, v2.4h 0x20,0x7c,0x62,0x6e = uaba v0.8h, v1.8h, v2.8h 0x20,0x7c,0xa2,0x2e = uaba v0.2s, v1.2s, v2.2s 0x20,0x7c,0xa2,0x6e = uaba v0.4s, v1.4s, v2.4s 0x20,0x7c,0x22,0x0e = saba v0.8b, v1.8b, v2.8b 0x20,0x7c,0x22,0x4e = saba v0.16b, v1.16b, v2.16b 0x20,0x7c,0x62,0x0e = saba v0.4h, v1.4h, v2.4h 0x20,0x7c,0x62,0x4e = saba v0.8h, v1.8h, v2.8h 0x20,0x7c,0xa2,0x0e = saba v0.2s, v1.2s, v2.2s 0x20,0x7c,0xa2,0x4e = saba v0.4s, v1.4s, v2.4s 0x20,0x74,0x22,0x2e = uabd v0.8b, v1.8b, v2.8b 0x20,0x74,0x22,0x6e = uabd v0.16b, v1.16b, v2.16b 0x20,0x74,0x62,0x2e = uabd v0.4h, v1.4h, v2.4h 0x20,0x74,0x62,0x6e = uabd v0.8h, v1.8h, v2.8h 0x20,0x74,0xa2,0x2e = uabd v0.2s, v1.2s, v2.2s 0x20,0x74,0xa2,0x6e = uabd v0.4s, v1.4s, v2.4s 0x20,0x74,0x22,0x0e = sabd v0.8b, v1.8b, v2.8b 0x20,0x74,0x22,0x4e = sabd v0.16b, v1.16b, v2.16b 0x20,0x74,0x62,0x0e = sabd v0.4h, v1.4h, v2.4h 0x20,0x74,0x62,0x4e = sabd v0.8h, v1.8h, v2.8h 0x20,0x74,0xa2,0x0e = sabd v0.2s, v1.2s, v2.2s 0x20,0x74,0xa2,0x4e = sabd v0.4s, v1.4s, v2.4s 0x20,0xd4,0xa2,0x2e = fabd v0.2s, v1.2s, v2.2s 0xff,0xd5,0xb0,0x6e = fabd v31.4s, v15.4s, v16.4s 0x07,0xd5,0xf9,0x6e = fabd v7.2d, v8.2d, v25.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-across.s.cs000064400000000000000000000027630072674642500220120ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x38,0x30,0x0e = saddlv h0, v1.8b 0x20,0x38,0x30,0x4e = saddlv h0, v1.16b 0x20,0x38,0x70,0x0e = saddlv s0, v1.4h 0x20,0x38,0x70,0x4e = saddlv s0, v1.8h 0x20,0x38,0xb0,0x4e = saddlv d0, v1.4s 0x20,0x38,0x30,0x2e = uaddlv h0, v1.8b 0x20,0x38,0x30,0x6e = uaddlv h0, v1.16b 0x20,0x38,0x70,0x2e = uaddlv s0, v1.4h 0x20,0x38,0x70,0x6e = uaddlv s0, v1.8h 0x20,0x38,0xb0,0x6e = uaddlv d0, v1.4s 0x20,0xa8,0x30,0x0e = smaxv b0, v1.8b 0x20,0xa8,0x30,0x4e = smaxv b0, v1.16b 0x20,0xa8,0x70,0x0e = smaxv h0, v1.4h 0x20,0xa8,0x70,0x4e = smaxv h0, v1.8h 0x20,0xa8,0xb0,0x4e = smaxv s0, v1.4s 0x20,0xa8,0x31,0x0e = sminv b0, v1.8b 0x20,0xa8,0x31,0x4e = sminv b0, v1.16b 0x20,0xa8,0x71,0x0e = sminv h0, v1.4h 0x20,0xa8,0x71,0x4e = sminv h0, v1.8h 0x20,0xa8,0xb1,0x4e = sminv s0, v1.4s 0x20,0xa8,0x30,0x2e = umaxv b0, v1.8b 0x20,0xa8,0x30,0x6e = umaxv b0, v1.16b 0x20,0xa8,0x70,0x2e = umaxv h0, v1.4h 0x20,0xa8,0x70,0x6e = umaxv h0, v1.8h 0x20,0xa8,0xb0,0x6e = umaxv s0, v1.4s 0x20,0xa8,0x31,0x2e = uminv b0, v1.8b 0x20,0xa8,0x31,0x6e = uminv b0, v1.16b 0x20,0xa8,0x71,0x2e = uminv h0, v1.4h 0x20,0xa8,0x71,0x6e = uminv h0, v1.8h 0x20,0xa8,0xb1,0x6e = uminv s0, v1.4s 0x20,0xb8,0x31,0x0e = addv b0, v1.8b 0x20,0xb8,0x31,0x4e = addv b0, v1.16b 0x20,0xb8,0x71,0x0e = addv h0, v1.4h 0x20,0xb8,0x71,0x4e = addv h0, v1.8h 0x20,0xb8,0xb1,0x4e = addv s0, v1.4s 0x20,0xc8,0x30,0x6e = fmaxnmv s0, v1.4s 0x20,0xc8,0xb0,0x6e = fminnmv s0, v1.4s 0x20,0xf8,0x30,0x6e = fmaxv s0, v1.4s 0x20,0xf8,0xb0,0x6e = fminv s0, v1.4s capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-add-pairwise.s.cs000064400000000000000000000007650072674642500230710ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0xbc,0x22,0x0e = addp v0.8b, v1.8b, v2.8b 0x20,0xbc,0x22,0x4e = addp v0.16b, v1.16b, v2.16b 0x20,0xbc,0x62,0x0e = addp v0.4h, v1.4h, v2.4h 0x20,0xbc,0x62,0x4e = addp v0.8h, v1.8h, v2.8h 0x20,0xbc,0xa2,0x0e = addp v0.2s, v1.2s, v2.2s 0x20,0xbc,0xa2,0x4e = addp v0.4s, v1.4s, v2.4s 0x20,0xbc,0xe2,0x4e = addp v0.2d, v1.2d, v2.2d 0x20,0xd4,0x22,0x2e = faddp v0.2s, v1.2s, v2.2s 0x20,0xd4,0x22,0x6e = faddp v0.4s, v1.4s, v2.4s 0x20,0xd4,0x62,0x6e = faddp v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-add-sub-instructions.s.cs000064400000000000000000000016750072674642500246020ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x84,0x22,0x0e = add v0.8b, v1.8b, v2.8b 0x20,0x84,0x22,0x4e = add v0.16b, v1.16b, v2.16b 0x20,0x84,0x62,0x0e = add v0.4h, v1.4h, v2.4h 0x20,0x84,0x62,0x4e = add v0.8h, v1.8h, v2.8h 0x20,0x84,0xa2,0x0e = add v0.2s, v1.2s, v2.2s 0x20,0x84,0xa2,0x4e = add v0.4s, v1.4s, v2.4s 0x20,0x84,0xe2,0x4e = add v0.2d, v1.2d, v2.2d 0x20,0x84,0x22,0x2e = sub v0.8b, v1.8b, v2.8b 0x20,0x84,0x22,0x6e = sub v0.16b, v1.16b, v2.16b 0x20,0x84,0x62,0x2e = sub v0.4h, v1.4h, v2.4h 0x20,0x84,0x62,0x6e = sub v0.8h, v1.8h, v2.8h 0x20,0x84,0xa2,0x2e = sub v0.2s, v1.2s, v2.2s 0x20,0x84,0xa2,0x6e = sub v0.4s, v1.4s, v2.4s 0x20,0x84,0xe2,0x6e = sub v0.2d, v1.2d, v2.2d 0x20,0xd4,0x22,0x0e = fadd v0.2s, v1.2s, v2.2s 0x20,0xd4,0x22,0x4e = fadd v0.4s, v1.4s, v2.4s 0x20,0xd4,0x62,0x4e = fadd v0.2d, v1.2d, v2.2d 0x20,0xd4,0xa2,0x0e = fsub v0.2s, v1.2s, v2.2s 0x20,0xd4,0xa2,0x4e = fsub v0.4s, v1.4s, v2.4s 0x20,0xd4,0xe2,0x4e = fsub v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-bitwise-instructions.s.cs000064400000000000000000000014210072674642500247160ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x1c,0x22,0x0e = and v0.8b, v1.8b, v2.8b 0x20,0x1c,0x22,0x4e = and v0.16b, v1.16b, v2.16b 0x20,0x1c,0xa2,0x0e = orr v0.8b, v1.8b, v2.8b 0x20,0x1c,0xa2,0x4e = orr v0.16b, v1.16b, v2.16b 0x20,0x1c,0x22,0x2e = eor v0.8b, v1.8b, v2.8b 0x20,0x1c,0x22,0x6e = eor v0.16b, v1.16b, v2.16b 0x20,0x1c,0xa2,0x2e = bit v0.8b, v1.8b, v2.8b 0x20,0x1c,0xa2,0x6e = bit v0.16b, v1.16b, v2.16b 0x20,0x1c,0xe2,0x2e = bif v0.8b, v1.8b, v2.8b 0x20,0x1c,0xe2,0x6e = bif v0.16b, v1.16b, v2.16b 0x20,0x1c,0x62,0x2e = bsl v0.8b, v1.8b, v2.8b 0x20,0x1c,0x62,0x6e = bsl v0.16b, v1.16b, v2.16b 0x20,0x1c,0xe2,0x0e = orn v0.8b, v1.8b, v2.8b 0x20,0x1c,0xe2,0x4e = orn v0.16b, v1.16b, v2.16b 0x20,0x1c,0x62,0x0e = bic v0.8b, v1.8b, v2.8b 0x20,0x1c,0x62,0x4e = bic v0.16b, v1.16b, v2.16b capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-compare-instructions.s.cs000064400000000000000000000146670072674642500247160ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xe0,0x8d,0x31,0x2e = cmeq v0.8b, v15.8b, v17.8b 0xe1,0x8f,0x28,0x6e = cmeq v1.16b, v31.16b, v8.16b 0x0f,0x8e,0x71,0x2e = cmeq v15.4h, v16.4h, v17.4h 0xc5,0x8c,0x67,0x6e = cmeq v5.8h, v6.8h, v7.8h 0x7d,0x8f,0xbc,0x2e = cmeq v29.2s, v27.2s, v28.2s 0xe9,0x8c,0xa8,0x6e = cmeq v9.4s, v7.4s, v8.4s 0xe3,0x8f,0xf5,0x6e = cmeq v3.2d, v31.2d, v21.2d 0xe0,0x3d,0x31,0x2e = cmhs v0.8b, v15.8b, v17.8b 0xe1,0x3f,0x28,0x6e = cmhs v1.16b, v31.16b, v8.16b 0x0f,0x3e,0x71,0x2e = cmhs v15.4h, v16.4h, v17.4h 0xc5,0x3c,0x67,0x6e = cmhs v5.8h, v6.8h, v7.8h 0x7d,0x3f,0xbc,0x2e = cmhs v29.2s, v27.2s, v28.2s 0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s 0xe3,0x3f,0xf5,0x6e = cmhs v3.2d, v31.2d, v21.2d 0xe0,0x3d,0x31,0x2e = cmhs v0.8b, v15.8b, v17.8b 0xe1,0x3f,0x28,0x6e = cmhs v1.16b, v31.16b, v8.16b 0x0f,0x3e,0x71,0x2e = cmhs v15.4h, v16.4h, v17.4h 0xc5,0x3c,0x67,0x6e = cmhs v5.8h, v6.8h, v7.8h 0x7d,0x3f,0xbc,0x2e = cmhs v29.2s, v27.2s, v28.2s 0xe9,0x3c,0xa8,0x6e = cmhs v9.4s, v7.4s, v8.4s 0xe3,0x3f,0xf5,0x6e = cmhs v3.2d, v31.2d, v21.2d 0xe0,0x3d,0x31,0x0e = cmge v0.8b, v15.8b, v17.8b 0xe1,0x3f,0x28,0x4e = cmge v1.16b, v31.16b, v8.16b 0x0f,0x3e,0x71,0x0e = cmge v15.4h, v16.4h, v17.4h 0xc5,0x3c,0x67,0x4e = cmge v5.8h, v6.8h, v7.8h 0x7d,0x3f,0xbc,0x0e = cmge v29.2s, v27.2s, v28.2s 0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s 0xe3,0x3f,0xf5,0x4e = cmge v3.2d, v31.2d, v21.2d 0xe0,0x3d,0x31,0x0e = cmge v0.8b, v15.8b, v17.8b 0xe1,0x3f,0x28,0x4e = cmge v1.16b, v31.16b, v8.16b 0x0f,0x3e,0x71,0x0e = cmge v15.4h, v16.4h, v17.4h 0xc5,0x3c,0x67,0x4e = cmge v5.8h, v6.8h, v7.8h 0x7d,0x3f,0xbc,0x0e = cmge v29.2s, v27.2s, v28.2s 0xe9,0x3c,0xa8,0x4e = cmge v9.4s, v7.4s, v8.4s 0xe3,0x3f,0xf5,0x4e = cmge v3.2d, v31.2d, v21.2d 0xe0,0x35,0x31,0x2e = cmhi v0.8b, v15.8b, v17.8b 0xe1,0x37,0x28,0x6e = cmhi v1.16b, v31.16b, v8.16b 0x0f,0x36,0x71,0x2e = cmhi v15.4h, v16.4h, v17.4h 0xc5,0x34,0x67,0x6e = cmhi v5.8h, v6.8h, v7.8h 0x7d,0x37,0xbc,0x2e = cmhi v29.2s, v27.2s, v28.2s 0xe9,0x34,0xa8,0x6e = cmhi v9.4s, v7.4s, v8.4s 0xe3,0x37,0xf5,0x6e = cmhi v3.2d, v31.2d, v21.2d 0xe0,0x35,0x31,0x2e = cmhi v0.8b, v15.8b, v17.8b 0xe1,0x37,0x28,0x6e = cmhi v1.16b, v31.16b, v8.16b 0x0f,0x36,0x71,0x2e = cmhi v15.4h, v16.4h, v17.4h 0xc5,0x34,0x67,0x6e = cmhi v5.8h, v6.8h, v7.8h 0x7d,0x37,0xbc,0x2e = cmhi v29.2s, v27.2s, v28.2s 0xe9,0x34,0xa8,0x6e = cmhi v9.4s, v7.4s, v8.4s 0xe3,0x37,0xf5,0x6e = cmhi v3.2d, v31.2d, v21.2d 0xe0,0x35,0x31,0x0e = cmgt v0.8b, v15.8b, v17.8b 0xe1,0x37,0x28,0x4e = cmgt v1.16b, v31.16b, v8.16b 0x0f,0x36,0x71,0x0e = cmgt v15.4h, v16.4h, v17.4h 0xc5,0x34,0x67,0x4e = cmgt v5.8h, v6.8h, v7.8h 0x7d,0x37,0xbc,0x0e = cmgt v29.2s, v27.2s, v28.2s 0xe9,0x34,0xa8,0x4e = cmgt v9.4s, v7.4s, v8.4s 0xe3,0x37,0xf5,0x4e = cmgt v3.2d, v31.2d, v21.2d 0xe0,0x35,0x31,0x0e = cmgt v0.8b, v15.8b, v17.8b 0xe1,0x37,0x28,0x4e = cmgt v1.16b, v31.16b, v8.16b 0x0f,0x36,0x71,0x0e = cmgt v15.4h, v16.4h, v17.4h 0xc5,0x34,0x67,0x4e = cmgt v5.8h, v6.8h, v7.8h 0x7d,0x37,0xbc,0x0e = cmgt v29.2s, v27.2s, v28.2s 0xe9,0x34,0xa8,0x4e = cmgt v9.4s, v7.4s, v8.4s 0xe3,0x37,0xf5,0x4e = cmgt v3.2d, v31.2d, v21.2d 0xe0,0x8d,0x31,0x0e = cmtst v0.8b, v15.8b, v17.8b 0xe1,0x8f,0x28,0x4e = cmtst v1.16b, v31.16b, v8.16b 0x0f,0x8e,0x71,0x0e = cmtst v15.4h, v16.4h, v17.4h 0xc5,0x8c,0x67,0x4e = cmtst v5.8h, v6.8h, v7.8h 0x7d,0x8f,0xbc,0x0e = cmtst v29.2s, v27.2s, v28.2s 0xe9,0x8c,0xa8,0x4e = cmtst v9.4s, v7.4s, v8.4s 0xe3,0x8f,0xf5,0x4e = cmtst v3.2d, v31.2d, v21.2d 0xe0,0xe7,0x30,0x0e = fcmeq v0.2s, v31.2s, v16.2s 0xe4,0xe4,0x2f,0x4e = fcmeq v4.4s, v7.4s, v15.4s 0x5d,0xe4,0x65,0x4e = fcmeq v29.2d, v2.2d, v5.2d 0xbf,0xe7,0x3c,0x6e = fcmge v31.4s, v29.4s, v28.4s 0x03,0xe5,0x2c,0x2e = fcmge v3.2s, v8.2s, v12.2s 0xf1,0xe5,0x6d,0x6e = fcmge v17.2d, v15.2d, v13.2d 0xbf,0xe7,0x3c,0x6e = fcmge v31.4s, v29.4s, v28.4s 0x03,0xe5,0x2c,0x2e = fcmge v3.2s, v8.2s, v12.2s 0xf1,0xe5,0x6d,0x6e = fcmge v17.2d, v15.2d, v13.2d 0xe0,0xe7,0xb0,0x2e = fcmgt v0.2s, v31.2s, v16.2s 0xe4,0xe4,0xaf,0x6e = fcmgt v4.4s, v7.4s, v15.4s 0x5d,0xe4,0xe5,0x6e = fcmgt v29.2d, v2.2d, v5.2d 0xe0,0xe7,0xb0,0x2e = fcmgt v0.2s, v31.2s, v16.2s 0xe4,0xe4,0xaf,0x6e = fcmgt v4.4s, v7.4s, v15.4s 0x5d,0xe4,0xe5,0x6e = fcmgt v29.2d, v2.2d, v5.2d 0xe0,0x99,0x20,0x0e = cmeq v0.8b, v15.8b, #0x0 0xe1,0x9b,0x20,0x4e = cmeq v1.16b, v31.16b, #0x0 0x0f,0x9a,0x60,0x0e = cmeq v15.4h, v16.4h, #0x0 0xc5,0x98,0x60,0x4e = cmeq v5.8h, v6.8h, #0x0 0x7d,0x9b,0xa0,0x0e = cmeq v29.2s, v27.2s, #0x0 0xe9,0x98,0xa0,0x4e = cmeq v9.4s, v7.4s, #0x0 0xe3,0x9b,0xe0,0x4e = cmeq v3.2d, v31.2d, #0x0 0xe0,0x89,0x20,0x2e = cmge v0.8b, v15.8b, #0x0 0xe1,0x8b,0x20,0x6e = cmge v1.16b, v31.16b, #0x0 0x0f,0x8a,0x60,0x2e = cmge v15.4h, v16.4h, #0x0 0xc5,0x88,0x60,0x6e = cmge v5.8h, v6.8h, #0x0 0x7d,0x8b,0xa0,0x2e = cmge v29.2s, v27.2s, #0x0 0x91,0x8a,0xa0,0x6e = cmge v17.4s, v20.4s, #0x0 0xe3,0x8b,0xe0,0x6e = cmge v3.2d, v31.2d, #0x0 0xe0,0x89,0x20,0x0e = cmgt v0.8b, v15.8b, #0x0 0xe1,0x8b,0x20,0x4e = cmgt v1.16b, v31.16b, #0x0 0x0f,0x8a,0x60,0x0e = cmgt v15.4h, v16.4h, #0x0 0xc5,0x88,0x60,0x4e = cmgt v5.8h, v6.8h, #0x0 0x7d,0x8b,0xa0,0x0e = cmgt v29.2s, v27.2s, #0x0 0xe9,0x88,0xa0,0x4e = cmgt v9.4s, v7.4s, #0x0 0xe3,0x8b,0xe0,0x4e = cmgt v3.2d, v31.2d, #0x0 0xe0,0x99,0x20,0x2e = cmle v0.8b, v15.8b, #0x0 0xe1,0x9b,0x20,0x6e = cmle v1.16b, v31.16b, #0x0 0x0f,0x9a,0x60,0x2e = cmle v15.4h, v16.4h, #0x0 0xc5,0x98,0x60,0x6e = cmle v5.8h, v6.8h, #0x0 0x7d,0x9b,0xa0,0x2e = cmle v29.2s, v27.2s, #0x0 0xe9,0x98,0xa0,0x6e = cmle v9.4s, v7.4s, #0x0 0xe3,0x9b,0xe0,0x6e = cmle v3.2d, v31.2d, #0x0 0xe0,0xa9,0x20,0x0e = cmlt v0.8b, v15.8b, #0x0 0xe1,0xab,0x20,0x4e = cmlt v1.16b, v31.16b, #0x0 0x0f,0xaa,0x60,0x0e = cmlt v15.4h, v16.4h, #0x0 0xc5,0xa8,0x60,0x4e = cmlt v5.8h, v6.8h, #0x0 0x7d,0xab,0xa0,0x0e = cmlt v29.2s, v27.2s, #0x0 0xe9,0xa8,0xa0,0x4e = cmlt v9.4s, v7.4s, #0x0 0xe3,0xab,0xe0,0x4e = cmlt v3.2d, v31.2d, #0x0 0xe0,0xdb,0xa0,0x0e = fcmeq v0.2s, v31.2s, #0.0 0xe4,0xd8,0xa0,0x4e = fcmeq v4.4s, v7.4s, #0.0 0x5d,0xd8,0xe0,0x4e = fcmeq v29.2d, v2.2d, #0.0 0xbf,0xcb,0xa0,0x6e = fcmge v31.4s, v29.4s, #0.0 0x03,0xc9,0xa0,0x2e = fcmge v3.2s, v8.2s, #0.0 0xf1,0xc9,0xe0,0x6e = fcmge v17.2d, v15.2d, #0.0 0xe0,0xcb,0xa0,0x0e = fcmgt v0.2s, v31.2s, #0.0 0xe4,0xc8,0xa0,0x4e = fcmgt v4.4s, v7.4s, #0.0 0x5d,0xc8,0xe0,0x4e = fcmgt v29.2d, v2.2d, #0.0 0x01,0xd9,0xa0,0x6e = fcmle v1.4s, v8.4s, #0.0 0x83,0xda,0xa0,0x2e = fcmle v3.2s, v20.2s, #0.0 0xa7,0xd9,0xe0,0x6e = fcmle v7.2d, v13.2d, #0.0 0x50,0xe8,0xa0,0x0e = fcmlt v16.2s, v2.2s, #0.0 0x8f,0xe8,0xa0,0x4e = fcmlt v15.4s, v4.4s, #0.0 0xa5,0xeb,0xe0,0x4e = fcmlt v5.2d, v29.2d, #0.0 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-crypto.s.cs000064400000000000000000000011740072674642500220330ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x48,0x28,0x4e = aese v0.16b, v1.16b 0x20,0x58,0x28,0x4e = aesd v0.16b, v1.16b 0x20,0x68,0x28,0x4e = aesmc v0.16b, v1.16b 0x20,0x78,0x28,0x4e = aesimc v0.16b, v1.16b 0x20,0x08,0x28,0x5e = sha1h s0, s1 0x20,0x18,0x28,0x5e = sha1su1 v0.4s, v1.4s 0x20,0x28,0x28,0x5e = sha256su0 v0.4s, v1.4s 0x20,0x00,0x02,0x5e = sha1c q0, s1, v2.4s 0x20,0x10,0x02,0x5e = sha1p q0, s1, v2.4s 0x20,0x20,0x02,0x5e = sha1m q0, s1, v2.4s 0x20,0x30,0x02,0x5e = sha1su0 v0.4s, v1.4s, v2.4s 0x20,0x40,0x02,0x5e = sha256h q0, q1, v2.4s 0x20,0x50,0x02,0x5e = sha256h2 q0, q1, v2.4s 0x20,0x60,0x02,0x5e = sha256su1 v0.4s, v1.4s, v2.4s capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-extract.s.cs000064400000000000000000000002040072674642500221560ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x18,0x02,0x2e = ext v0.8b, v1.8b, v2.8b, #0x3 0x20,0x18,0x02,0x6e = ext v0.16b, v1.16b, v2.16b, #0x3 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-facge-facgt.s.cs000064400000000000000000000011570072674642500226430ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s 0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s 0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d 0xe0,0xef,0x30,0x2e = facge v0.2s, v31.2s, v16.2s 0xe4,0xec,0x2f,0x6e = facge v4.4s, v7.4s, v15.4s 0x5d,0xec,0x65,0x6e = facge v29.2d, v2.2d, v5.2d 0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s 0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s 0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d 0xbf,0xef,0xbc,0x6e = facgt v31.4s, v29.4s, v28.4s 0x03,0xed,0xac,0x2e = facgt v3.2s, v8.2s, v12.2s 0xf1,0xed,0xed,0x6e = facgt v17.2d, v15.2d, v13.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-frsqrt-frecp.s.cs000064400000000000000000000005150072674642500231270ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xe0,0xff,0xb0,0x0e = frsqrts v0.2s, v31.2s, v16.2s 0xe4,0xfc,0xaf,0x4e = frsqrts v4.4s, v7.4s, v15.4s 0x5d,0xfc,0xe5,0x4e = frsqrts v29.2d, v2.2d, v5.2d 0xbf,0xff,0x3c,0x4e = frecps v31.4s, v29.4s, v28.4s 0x03,0xfd,0x2c,0x0e = frecps v3.2s, v8.2s, v12.2s 0xf1,0xfd,0x6d,0x4e = frecps v17.2d, v15.2d, v13.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-halving-add-sub.s.cs000064400000000000000000000022450072674642500234600ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x04,0x22,0x0e = shadd v0.8b, v1.8b, v2.8b 0x20,0x04,0x22,0x4e = shadd v0.16b, v1.16b, v2.16b 0x20,0x04,0x62,0x0e = shadd v0.4h, v1.4h, v2.4h 0x20,0x04,0x62,0x4e = shadd v0.8h, v1.8h, v2.8h 0x20,0x04,0xa2,0x0e = shadd v0.2s, v1.2s, v2.2s 0x20,0x04,0xa2,0x4e = shadd v0.4s, v1.4s, v2.4s 0x20,0x04,0x22,0x2e = uhadd v0.8b, v1.8b, v2.8b 0x20,0x04,0x22,0x6e = uhadd v0.16b, v1.16b, v2.16b 0x20,0x04,0x62,0x2e = uhadd v0.4h, v1.4h, v2.4h 0x20,0x04,0x62,0x6e = uhadd v0.8h, v1.8h, v2.8h 0x20,0x04,0xa2,0x2e = uhadd v0.2s, v1.2s, v2.2s 0x20,0x04,0xa2,0x6e = uhadd v0.4s, v1.4s, v2.4s 0x20,0x24,0x22,0x0e = shsub v0.8b, v1.8b, v2.8b 0x20,0x24,0x22,0x4e = shsub v0.16b, v1.16b, v2.16b 0x20,0x24,0x62,0x0e = shsub v0.4h, v1.4h, v2.4h 0x20,0x24,0x62,0x4e = shsub v0.8h, v1.8h, v2.8h 0x20,0x24,0xa2,0x0e = shsub v0.2s, v1.2s, v2.2s 0x20,0x24,0xa2,0x4e = shsub v0.4s, v1.4s, v2.4s 0x20,0x24,0x22,0x2e = uhsub v0.8b, v1.8b, v2.8b 0x20,0x24,0x22,0x6e = uhsub v0.16b, v1.16b, v2.16b 0x20,0x24,0x62,0x2e = uhsub v0.4h, v1.4h, v2.4h 0x20,0x24,0x62,0x6e = uhsub v0.8h, v1.8h, v2.8h 0x20,0x24,0xa2,0x2e = uhsub v0.2s, v1.2s, v2.2s 0x20,0x24,0xa2,0x6e = uhsub v0.4s, v1.4s, v2.4s capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-max-min-pairwise.s.cs000064400000000000000000000034030072674642500236770ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0xa4,0x22,0x0e = smaxp v0.8b, v1.8b, v2.8b 0x20,0xa4,0x22,0x4e = smaxp v0.16b, v1.16b, v2.16b 0x20,0xa4,0x62,0x0e = smaxp v0.4h, v1.4h, v2.4h 0x20,0xa4,0x62,0x4e = smaxp v0.8h, v1.8h, v2.8h 0x20,0xa4,0xa2,0x0e = smaxp v0.2s, v1.2s, v2.2s 0x20,0xa4,0xa2,0x4e = smaxp v0.4s, v1.4s, v2.4s 0x20,0xa4,0x22,0x2e = umaxp v0.8b, v1.8b, v2.8b 0x20,0xa4,0x22,0x6e = umaxp v0.16b, v1.16b, v2.16b 0x20,0xa4,0x62,0x2e = umaxp v0.4h, v1.4h, v2.4h 0x20,0xa4,0x62,0x6e = umaxp v0.8h, v1.8h, v2.8h 0x20,0xa4,0xa2,0x2e = umaxp v0.2s, v1.2s, v2.2s 0x20,0xa4,0xa2,0x6e = umaxp v0.4s, v1.4s, v2.4s 0x20,0xac,0x22,0x0e = sminp v0.8b, v1.8b, v2.8b 0x20,0xac,0x22,0x4e = sminp v0.16b, v1.16b, v2.16b 0x20,0xac,0x62,0x0e = sminp v0.4h, v1.4h, v2.4h 0x20,0xac,0x62,0x4e = sminp v0.8h, v1.8h, v2.8h 0x20,0xac,0xa2,0x0e = sminp v0.2s, v1.2s, v2.2s 0x20,0xac,0xa2,0x4e = sminp v0.4s, v1.4s, v2.4s 0x20,0xac,0x22,0x2e = uminp v0.8b, v1.8b, v2.8b 0x20,0xac,0x22,0x6e = uminp v0.16b, v1.16b, v2.16b 0x20,0xac,0x62,0x2e = uminp v0.4h, v1.4h, v2.4h 0x20,0xac,0x62,0x6e = uminp v0.8h, v1.8h, v2.8h 0x20,0xac,0xa2,0x2e = uminp v0.2s, v1.2s, v2.2s 0x20,0xac,0xa2,0x6e = uminp v0.4s, v1.4s, v2.4s 0x20,0xf4,0x22,0x2e = fmaxp v0.2s, v1.2s, v2.2s 0xff,0xf5,0x30,0x6e = fmaxp v31.4s, v15.4s, v16.4s 0x07,0xf5,0x79,0x6e = fmaxp v7.2d, v8.2d, v25.2d 0xea,0xf5,0xb6,0x2e = fminp v10.2s, v15.2s, v22.2s 0xa3,0xf4,0xa6,0x6e = fminp v3.4s, v5.4s, v6.4s 0xb1,0xf5,0xe2,0x6e = fminp v17.2d, v13.2d, v2.2d 0x20,0xc4,0x22,0x2e = fmaxnmp v0.2s, v1.2s, v2.2s 0xff,0xc5,0x30,0x6e = fmaxnmp v31.4s, v15.4s, v16.4s 0x07,0xc5,0x79,0x6e = fmaxnmp v7.2d, v8.2d, v25.2d 0xea,0xc5,0xb6,0x2e = fminnmp v10.2s, v15.2s, v22.2s 0xa3,0xc4,0xa6,0x6e = fminnmp v3.4s, v5.4s, v6.4s 0xb1,0xc5,0xe2,0x6e = fminnmp v17.2d, v13.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-max-min.s.cs000064400000000000000000000033370072674642500220640ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x64,0x22,0x0e = smax v0.8b, v1.8b, v2.8b 0x20,0x64,0x22,0x4e = smax v0.16b, v1.16b, v2.16b 0x20,0x64,0x62,0x0e = smax v0.4h, v1.4h, v2.4h 0x20,0x64,0x62,0x4e = smax v0.8h, v1.8h, v2.8h 0x20,0x64,0xa2,0x0e = smax v0.2s, v1.2s, v2.2s 0x20,0x64,0xa2,0x4e = smax v0.4s, v1.4s, v2.4s 0x20,0x64,0x22,0x2e = umax v0.8b, v1.8b, v2.8b 0x20,0x64,0x22,0x6e = umax v0.16b, v1.16b, v2.16b 0x20,0x64,0x62,0x2e = umax v0.4h, v1.4h, v2.4h 0x20,0x64,0x62,0x6e = umax v0.8h, v1.8h, v2.8h 0x20,0x64,0xa2,0x2e = umax v0.2s, v1.2s, v2.2s 0x20,0x64,0xa2,0x6e = umax v0.4s, v1.4s, v2.4s 0x20,0x6c,0x22,0x0e = smin v0.8b, v1.8b, v2.8b 0x20,0x6c,0x22,0x4e = smin v0.16b, v1.16b, v2.16b 0x20,0x6c,0x62,0x0e = smin v0.4h, v1.4h, v2.4h 0x20,0x6c,0x62,0x4e = smin v0.8h, v1.8h, v2.8h 0x20,0x6c,0xa2,0x0e = smin v0.2s, v1.2s, v2.2s 0x20,0x6c,0xa2,0x4e = smin v0.4s, v1.4s, v2.4s 0x20,0x6c,0x22,0x2e = umin v0.8b, v1.8b, v2.8b 0x20,0x6c,0x22,0x6e = umin v0.16b, v1.16b, v2.16b 0x20,0x6c,0x62,0x2e = umin v0.4h, v1.4h, v2.4h 0x20,0x6c,0x62,0x6e = umin v0.8h, v1.8h, v2.8h 0x20,0x6c,0xa2,0x2e = umin v0.2s, v1.2s, v2.2s 0x20,0x6c,0xa2,0x6e = umin v0.4s, v1.4s, v2.4s 0x20,0xf4,0x22,0x0e = fmax v0.2s, v1.2s, v2.2s 0xff,0xf5,0x30,0x4e = fmax v31.4s, v15.4s, v16.4s 0x07,0xf5,0x79,0x4e = fmax v7.2d, v8.2d, v25.2d 0xea,0xf5,0xb6,0x0e = fmin v10.2s, v15.2s, v22.2s 0xa3,0xf4,0xa6,0x4e = fmin v3.4s, v5.4s, v6.4s 0xb1,0xf5,0xe2,0x4e = fmin v17.2d, v13.2d, v2.2d 0x20,0xc4,0x22,0x0e = fmaxnm v0.2s, v1.2s, v2.2s 0xff,0xc5,0x30,0x4e = fmaxnm v31.4s, v15.4s, v16.4s 0x07,0xc5,0x79,0x4e = fmaxnm v7.2d, v8.2d, v25.2d 0xea,0xc5,0xb6,0x0e = fminnm v10.2s, v15.2s, v22.2s 0xa3,0xc4,0xa6,0x4e = fminnm v3.4s, v5.4s, v6.4s 0xb1,0xc5,0xe2,0x4e = fminnm v17.2d, v13.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-mla-mls-instructions.s.cs000064400000000000000000000015410072674642500246150ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x94,0x22,0x0e = mla v0.8b, v1.8b, v2.8b 0x20,0x94,0x22,0x4e = mla v0.16b, v1.16b, v2.16b 0x20,0x94,0x62,0x0e = mla v0.4h, v1.4h, v2.4h 0x20,0x94,0x62,0x4e = mla v0.8h, v1.8h, v2.8h 0x20,0x94,0xa2,0x0e = mla v0.2s, v1.2s, v2.2s 0x20,0x94,0xa2,0x4e = mla v0.4s, v1.4s, v2.4s 0x20,0x94,0x22,0x2e = mls v0.8b, v1.8b, v2.8b 0x20,0x94,0x22,0x6e = mls v0.16b, v1.16b, v2.16b 0x20,0x94,0x62,0x2e = mls v0.4h, v1.4h, v2.4h 0x20,0x94,0x62,0x6e = mls v0.8h, v1.8h, v2.8h 0x20,0x94,0xa2,0x2e = mls v0.2s, v1.2s, v2.2s 0x20,0x94,0xa2,0x6e = mls v0.4s, v1.4s, v2.4s 0x20,0xcc,0x22,0x0e = fmla v0.2s, v1.2s, v2.2s 0x20,0xcc,0x22,0x4e = fmla v0.4s, v1.4s, v2.4s 0x20,0xcc,0x62,0x4e = fmla v0.2d, v1.2d, v2.2d 0x20,0xcc,0xa2,0x0e = fmls v0.2s, v1.2s, v2.2s 0x20,0xcc,0xa2,0x4e = fmls v0.4s, v1.4s, v2.4s 0x20,0xcc,0xe2,0x4e = fmls v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-mov.s.cs000064400000000000000000000060350072674642500213150ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x04,0x00,0x0f = movi v0.2s, #0x1 0x01,0x04,0x00,0x0f = movi v1.2s, #0x0 0x2f,0x24,0x00,0x0f = movi v15.2s, #0x1, lsl #8 0x30,0x44,0x00,0x0f = movi v16.2s, #0x1, lsl #16 0x3f,0x64,0x00,0x0f = movi v31.2s, #0x1, lsl #24 0x20,0x04,0x00,0x4f = movi v0.4s, #0x1 0x20,0x24,0x00,0x4f = movi v0.4s, #0x1, lsl #8 0x20,0x44,0x00,0x4f = movi v0.4s, #0x1, lsl #16 0x20,0x64,0x00,0x4f = movi v0.4s, #0x1, lsl #24 0x20,0x84,0x00,0x0f = movi v0.4h, #0x1 0x20,0xa4,0x00,0x0f = movi v0.4h, #0x1, lsl #8 0x20,0x84,0x00,0x4f = movi v0.8h, #0x1 0x20,0xa4,0x00,0x4f = movi v0.8h, #0x1, lsl #8 0x20,0x04,0x00,0x2f = mvni v0.2s, #0x1 0x01,0x04,0x00,0x2f = mvni v1.2s, #0x0 0x20,0x24,0x00,0x2f = mvni v0.2s, #0x1, lsl #8 0x20,0x44,0x00,0x2f = mvni v0.2s, #0x1, lsl #16 0x20,0x64,0x00,0x2f = mvni v0.2s, #0x1, lsl #24 0x20,0x04,0x00,0x6f = mvni v0.4s, #0x1 0x2f,0x24,0x00,0x6f = mvni v15.4s, #0x1, lsl #8 0x30,0x44,0x00,0x6f = mvni v16.4s, #0x1, lsl #16 0x3f,0x64,0x00,0x6f = mvni v31.4s, #0x1, lsl #24 0x20,0x84,0x00,0x2f = mvni v0.4h, #0x1 0x20,0xa4,0x00,0x2f = mvni v0.4h, #0x1, lsl #8 0x20,0x84,0x00,0x6f = mvni v0.8h, #0x1 0x20,0xa4,0x00,0x6f = mvni v0.8h, #0x1, lsl #8 0x20,0x14,0x00,0x2f = bic v0.2s, #0x1 0x01,0x14,0x00,0x2f = bic v1.2s, #0x0 0x20,0x34,0x00,0x2f = bic v0.2s, #0x1, lsl #8 0x20,0x54,0x00,0x2f = bic v0.2s, #0x1, lsl #16 0x20,0x74,0x00,0x2f = bic v0.2s, #0x1, lsl #24 0x20,0x14,0x00,0x6f = bic v0.4s, #0x1 0x20,0x34,0x00,0x6f = bic v0.4s, #0x1, lsl #8 0x20,0x54,0x00,0x6f = bic v0.4s, #0x1, lsl #16 0x20,0x74,0x00,0x6f = bic v0.4s, #0x1, lsl #24 0x2f,0x94,0x00,0x2f = bic v15.4h, #0x1 0x30,0xb4,0x00,0x2f = bic v16.4h, #0x1, lsl #8 0x20,0x94,0x00,0x6f = bic v0.8h, #0x1 0x3f,0xb4,0x00,0x6f = bic v31.8h, #0x1, lsl #8 0x20,0x14,0x00,0x0f = orr v0.2s, #0x1 0x01,0x14,0x00,0x0f = orr v1.2s, #0x0 0x20,0x34,0x00,0x0f = orr v0.2s, #0x1, lsl #8 0x20,0x54,0x00,0x0f = orr v0.2s, #0x1, lsl #16 0x20,0x74,0x00,0x0f = orr v0.2s, #0x1, lsl #24 0x20,0x14,0x00,0x4f = orr v0.4s, #0x1 0x20,0x34,0x00,0x4f = orr v0.4s, #0x1, lsl #8 0x20,0x54,0x00,0x4f = orr v0.4s, #0x1, lsl #16 0x20,0x74,0x00,0x4f = orr v0.4s, #0x1, lsl #24 0x3f,0x94,0x00,0x0f = orr v31.4h, #0x1 0x2f,0xb4,0x00,0x0f = orr v15.4h, #0x1, lsl #8 0x20,0x94,0x00,0x4f = orr v0.8h, #0x1 0x30,0xb4,0x00,0x4f = orr v16.8h, #0x1, lsl #8 0x20,0xc4,0x00,0x0f = movi v0.2s, #0x1, msl #8 0x21,0xd4,0x00,0x0f = movi v1.2s, #0x1, msl #16 0x20,0xc4,0x00,0x4f = movi v0.4s, #0x1, msl #8 0x3f,0xd4,0x00,0x4f = movi v31.4s, #0x1, msl #16 0x21,0xc4,0x00,0x2f = mvni v1.2s, #0x1, msl #8 0x20,0xd4,0x00,0x2f = mvni v0.2s, #0x1, msl #16 0x3f,0xc4,0x00,0x6f = mvni v31.4s, #0x1, msl #8 0x20,0xd4,0x00,0x6f = mvni v0.4s, #0x1, msl #16 0x00,0xe4,0x00,0x0f = movi v0.8b, #0x0 0xff,0xe7,0x07,0x0f = movi v31.8b, #0xff 0xef,0xe5,0x00,0x4f = movi v15.16b, #0xf 0xff,0xe7,0x00,0x4f = movi v31.16b, #0x1f 0x40,0xe5,0x05,0x6f = movi v0.2d, #0xff00ff00ff00ff00 0x40,0xe5,0x05,0x2f = movi d0, #0xff00ff00ff00ff00 0x01,0xf6,0x03,0x0f = fmov v1.2s, #1.00000000 0x0f,0xf6,0x03,0x4f = fmov v15.4s, #1.00000000 0x1f,0xf6,0x03,0x6f = fmov v31.2d, #1.00000000 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-mul-div-instructions.s.cs000064400000000000000000000021720072674642500246310ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x9c,0x22,0x0e = mul v0.8b, v1.8b, v2.8b 0x20,0x9c,0x22,0x4e = mul v0.16b, v1.16b, v2.16b 0x20,0x9c,0x62,0x0e = mul v0.4h, v1.4h, v2.4h 0x20,0x9c,0x62,0x4e = mul v0.8h, v1.8h, v2.8h 0x20,0x9c,0xa2,0x0e = mul v0.2s, v1.2s, v2.2s 0x20,0x9c,0xa2,0x4e = mul v0.4s, v1.4s, v2.4s 0x20,0xdc,0x22,0x2e = fmul v0.2s, v1.2s, v2.2s 0x20,0xdc,0x22,0x6e = fmul v0.4s, v1.4s, v2.4s 0x20,0xdc,0x62,0x6e = fmul v0.2d, v1.2d, v2.2d 0x20,0xfc,0x22,0x2e = fdiv v0.2s, v1.2s, v2.2s 0x20,0xfc,0x22,0x6e = fdiv v0.4s, v1.4s, v2.4s 0x20,0xfc,0x62,0x6e = fdiv v0.2d, v1.2d, v2.2d 0xf1,0x9f,0x30,0x2e = pmul v17.8b, v31.8b, v16.8b 0x20,0x9c,0x22,0x6e = pmul v0.16b, v1.16b, v2.16b 0x22,0xb7,0x63,0x0e = sqdmulh v2.4h, v25.4h, v3.4h 0xac,0xb4,0x6d,0x4e = sqdmulh v12.8h, v5.8h, v13.8h 0x23,0xb4,0xbe,0x0e = sqdmulh v3.2s, v1.2s, v30.2s 0x22,0xb7,0x63,0x2e = sqrdmulh v2.4h, v25.4h, v3.4h 0xac,0xb4,0x6d,0x6e = sqrdmulh v12.8h, v5.8h, v13.8h 0x23,0xb4,0xbe,0x2e = sqrdmulh v3.2s, v1.2s, v30.2s 0xb5,0xdc,0x2d,0x0e = fmulx v21.2s, v5.2s, v13.2s 0x21,0xdf,0x23,0x4e = fmulx v1.4s, v25.4s, v3.4s 0xdf,0xde,0x62,0x4e = fmulx v31.2d, v22.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-perm.s.cs000064400000000000000000000037410072674642500214600ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x18,0x02,0x0e = uzp1 v0.8b, v1.8b, v2.8b 0x20,0x18,0x02,0x4e = uzp1 v0.16b, v1.16b, v2.16b 0x20,0x18,0x42,0x0e = uzp1 v0.4h, v1.4h, v2.4h 0x20,0x18,0x42,0x4e = uzp1 v0.8h, v1.8h, v2.8h 0x20,0x18,0x82,0x0e = uzp1 v0.2s, v1.2s, v2.2s 0x20,0x18,0x82,0x4e = uzp1 v0.4s, v1.4s, v2.4s 0x20,0x18,0xc2,0x4e = uzp1 v0.2d, v1.2d, v2.2d 0x20,0x28,0x02,0x0e = trn1 v0.8b, v1.8b, v2.8b 0x20,0x28,0x02,0x4e = trn1 v0.16b, v1.16b, v2.16b 0x20,0x28,0x42,0x0e = trn1 v0.4h, v1.4h, v2.4h 0x20,0x28,0x42,0x4e = trn1 v0.8h, v1.8h, v2.8h 0x20,0x28,0x82,0x0e = trn1 v0.2s, v1.2s, v2.2s 0x20,0x28,0x82,0x4e = trn1 v0.4s, v1.4s, v2.4s 0x20,0x28,0xc2,0x4e = trn1 v0.2d, v1.2d, v2.2d 0x20,0x38,0x02,0x0e = zip1 v0.8b, v1.8b, v2.8b 0x20,0x38,0x02,0x4e = zip1 v0.16b, v1.16b, v2.16b 0x20,0x38,0x42,0x0e = zip1 v0.4h, v1.4h, v2.4h 0x20,0x38,0x42,0x4e = zip1 v0.8h, v1.8h, v2.8h 0x20,0x38,0x82,0x0e = zip1 v0.2s, v1.2s, v2.2s 0x20,0x38,0x82,0x4e = zip1 v0.4s, v1.4s, v2.4s 0x20,0x38,0xc2,0x4e = zip1 v0.2d, v1.2d, v2.2d 0x20,0x58,0x02,0x0e = uzp2 v0.8b, v1.8b, v2.8b 0x20,0x58,0x02,0x4e = uzp2 v0.16b, v1.16b, v2.16b 0x20,0x58,0x42,0x0e = uzp2 v0.4h, v1.4h, v2.4h 0x20,0x58,0x42,0x4e = uzp2 v0.8h, v1.8h, v2.8h 0x20,0x58,0x82,0x0e = uzp2 v0.2s, v1.2s, v2.2s 0x20,0x58,0x82,0x4e = uzp2 v0.4s, v1.4s, v2.4s 0x20,0x58,0xc2,0x4e = uzp2 v0.2d, v1.2d, v2.2d 0x20,0x68,0x02,0x0e = trn2 v0.8b, v1.8b, v2.8b 0x20,0x68,0x02,0x4e = trn2 v0.16b, v1.16b, v2.16b 0x20,0x68,0x42,0x0e = trn2 v0.4h, v1.4h, v2.4h 0x20,0x68,0x42,0x4e = trn2 v0.8h, v1.8h, v2.8h 0x20,0x68,0x82,0x0e = trn2 v0.2s, v1.2s, v2.2s 0x20,0x68,0x82,0x4e = trn2 v0.4s, v1.4s, v2.4s 0x20,0x68,0xc2,0x4e = trn2 v0.2d, v1.2d, v2.2d 0x20,0x78,0x02,0x0e = zip2 v0.8b, v1.8b, v2.8b 0x20,0x78,0x02,0x4e = zip2 v0.16b, v1.16b, v2.16b 0x20,0x78,0x42,0x0e = zip2 v0.4h, v1.4h, v2.4h 0x20,0x78,0x42,0x4e = zip2 v0.8h, v1.8h, v2.8h 0x20,0x78,0x82,0x0e = zip2 v0.2s, v1.2s, v2.2s 0x20,0x78,0x82,0x4e = zip2 v0.4s, v1.4s, v2.4s 0x20,0x78,0xc2,0x4e = zip2 v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-rounding-halving-add.s.cs000064400000000000000000000011530072674642500245110ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x14,0x22,0x0e = srhadd v0.8b, v1.8b, v2.8b 0x20,0x14,0x22,0x4e = srhadd v0.16b, v1.16b, v2.16b 0x20,0x14,0x62,0x0e = srhadd v0.4h, v1.4h, v2.4h 0x20,0x14,0x62,0x4e = srhadd v0.8h, v1.8h, v2.8h 0x20,0x14,0xa2,0x0e = srhadd v0.2s, v1.2s, v2.2s 0x20,0x14,0xa2,0x4e = srhadd v0.4s, v1.4s, v2.4s 0x20,0x14,0x22,0x2e = urhadd v0.8b, v1.8b, v2.8b 0x20,0x14,0x22,0x6e = urhadd v0.16b, v1.16b, v2.16b 0x20,0x14,0x62,0x2e = urhadd v0.4h, v1.4h, v2.4h 0x20,0x14,0x62,0x6e = urhadd v0.8h, v1.8h, v2.8h 0x20,0x14,0xa2,0x2e = urhadd v0.2s, v1.2s, v2.2s 0x20,0x14,0xa2,0x6e = urhadd v0.4s, v1.4s, v2.4s capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-rounding-shift.s.cs000064400000000000000000000012770072674642500234570ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x54,0x22,0x0e = srshl v0.8b, v1.8b, v2.8b 0x20,0x54,0x22,0x4e = srshl v0.16b, v1.16b, v2.16b 0x20,0x54,0x62,0x0e = srshl v0.4h, v1.4h, v2.4h 0x20,0x54,0x62,0x4e = srshl v0.8h, v1.8h, v2.8h 0x20,0x54,0xa2,0x0e = srshl v0.2s, v1.2s, v2.2s 0x20,0x54,0xa2,0x4e = srshl v0.4s, v1.4s, v2.4s 0x20,0x54,0xe2,0x4e = srshl v0.2d, v1.2d, v2.2d 0x20,0x54,0x22,0x2e = urshl v0.8b, v1.8b, v2.8b 0x20,0x54,0x22,0x6e = urshl v0.16b, v1.16b, v2.16b 0x20,0x54,0x62,0x2e = urshl v0.4h, v1.4h, v2.4h 0x20,0x54,0x62,0x6e = urshl v0.8h, v1.8h, v2.8h 0x20,0x54,0xa2,0x2e = urshl v0.2s, v1.2s, v2.2s 0x20,0x54,0xa2,0x6e = urshl v0.4s, v1.4s, v2.4s 0x20,0x54,0xe2,0x6e = urshl v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-saturating-add-sub.s.cs000064400000000000000000000025450072674642500242140ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x0c,0x22,0x0e = sqadd v0.8b, v1.8b, v2.8b 0x20,0x0c,0x22,0x4e = sqadd v0.16b, v1.16b, v2.16b 0x20,0x0c,0x62,0x0e = sqadd v0.4h, v1.4h, v2.4h 0x20,0x0c,0x62,0x4e = sqadd v0.8h, v1.8h, v2.8h 0x20,0x0c,0xa2,0x0e = sqadd v0.2s, v1.2s, v2.2s 0x20,0x0c,0xa2,0x4e = sqadd v0.4s, v1.4s, v2.4s 0x20,0x0c,0xe2,0x4e = sqadd v0.2d, v1.2d, v2.2d 0x20,0x0c,0x22,0x2e = uqadd v0.8b, v1.8b, v2.8b 0x20,0x0c,0x22,0x6e = uqadd v0.16b, v1.16b, v2.16b 0x20,0x0c,0x62,0x2e = uqadd v0.4h, v1.4h, v2.4h 0x20,0x0c,0x62,0x6e = uqadd v0.8h, v1.8h, v2.8h 0x20,0x0c,0xa2,0x2e = uqadd v0.2s, v1.2s, v2.2s 0x20,0x0c,0xa2,0x6e = uqadd v0.4s, v1.4s, v2.4s 0x20,0x0c,0xe2,0x6e = uqadd v0.2d, v1.2d, v2.2d 0x20,0x2c,0x22,0x0e = sqsub v0.8b, v1.8b, v2.8b 0x20,0x2c,0x22,0x4e = sqsub v0.16b, v1.16b, v2.16b 0x20,0x2c,0x62,0x0e = sqsub v0.4h, v1.4h, v2.4h 0x20,0x2c,0x62,0x4e = sqsub v0.8h, v1.8h, v2.8h 0x20,0x2c,0xa2,0x0e = sqsub v0.2s, v1.2s, v2.2s 0x20,0x2c,0xa2,0x4e = sqsub v0.4s, v1.4s, v2.4s 0x20,0x2c,0xe2,0x4e = sqsub v0.2d, v1.2d, v2.2d 0x20,0x2c,0x22,0x2e = uqsub v0.8b, v1.8b, v2.8b 0x20,0x2c,0x22,0x6e = uqsub v0.16b, v1.16b, v2.16b 0x20,0x2c,0x62,0x2e = uqsub v0.4h, v1.4h, v2.4h 0x20,0x2c,0x62,0x6e = uqsub v0.8h, v1.8h, v2.8h 0x20,0x2c,0xa2,0x2e = uqsub v0.2s, v1.2s, v2.2s 0x20,0x2c,0xa2,0x6e = uqsub v0.4s, v1.4s, v2.4s 0x20,0x2c,0xe2,0x6e = uqsub v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-saturating-rounding-shift.s.cs000064400000000000000000000013150072674642500256270ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x5c,0x22,0x0e = sqrshl v0.8b, v1.8b, v2.8b 0x20,0x5c,0x22,0x4e = sqrshl v0.16b, v1.16b, v2.16b 0x20,0x5c,0x62,0x0e = sqrshl v0.4h, v1.4h, v2.4h 0x20,0x5c,0x62,0x4e = sqrshl v0.8h, v1.8h, v2.8h 0x20,0x5c,0xa2,0x0e = sqrshl v0.2s, v1.2s, v2.2s 0x20,0x5c,0xa2,0x4e = sqrshl v0.4s, v1.4s, v2.4s 0x20,0x5c,0xe2,0x4e = sqrshl v0.2d, v1.2d, v2.2d 0x20,0x5c,0x22,0x2e = uqrshl v0.8b, v1.8b, v2.8b 0x20,0x5c,0x22,0x6e = uqrshl v0.16b, v1.16b, v2.16b 0x20,0x5c,0x62,0x2e = uqrshl v0.4h, v1.4h, v2.4h 0x20,0x5c,0x62,0x6e = uqrshl v0.8h, v1.8h, v2.8h 0x20,0x5c,0xa2,0x2e = uqrshl v0.2s, v1.2s, v2.2s 0x20,0x5c,0xa2,0x6e = uqrshl v0.4s, v1.4s, v2.4s 0x20,0x5c,0xe2,0x6e = uqrshl v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-saturating-shift.s.cs000064400000000000000000000012770072674642500240130ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x4c,0x22,0x0e = sqshl v0.8b, v1.8b, v2.8b 0x20,0x4c,0x22,0x4e = sqshl v0.16b, v1.16b, v2.16b 0x20,0x4c,0x62,0x0e = sqshl v0.4h, v1.4h, v2.4h 0x20,0x4c,0x62,0x4e = sqshl v0.8h, v1.8h, v2.8h 0x20,0x4c,0xa2,0x0e = sqshl v0.2s, v1.2s, v2.2s 0x20,0x4c,0xa2,0x4e = sqshl v0.4s, v1.4s, v2.4s 0x20,0x4c,0xe2,0x4e = sqshl v0.2d, v1.2d, v2.2d 0x20,0x4c,0x22,0x2e = uqshl v0.8b, v1.8b, v2.8b 0x20,0x4c,0x22,0x6e = uqshl v0.16b, v1.16b, v2.16b 0x20,0x4c,0x62,0x2e = uqshl v0.4h, v1.4h, v2.4h 0x20,0x4c,0x62,0x6e = uqshl v0.8h, v1.8h, v2.8h 0x20,0x4c,0xa2,0x2e = uqshl v0.2s, v1.2s, v2.2s 0x20,0x4c,0xa2,0x6e = uqshl v0.4s, v1.4s, v2.4s 0x20,0x4c,0xe2,0x6e = uqshl v0.2d, v1.2d, v2.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-abs.s.cs000064400000000000000000000004420072674642500225200ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x1d,0xbb,0xe0,0x5e = abs d29, d24 0x1d,0xd7,0xb4,0x7e = fabd s29, s24, s20 0x1d,0xd7,0xf4,0x7e = fabd d29, d24, d20 0xd3,0x79,0x20,0x5e = sqabs b19, b14 0xf5,0x79,0x60,0x5e = sqabs h21, h15 0x94,0x79,0xa0,0x5e = sqabs s20, s12 0x92,0x79,0xe0,0x5e = sqabs d18, d12 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-add-sub.s.cs000064400000000000000000000001450072674642500232720ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x1f,0x84,0xf0,0x5e = add d31, d0, d16 0xe1,0x84,0xe8,0x7e = sub d1, d7, d8 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-by-elem-mla.s.cs000064400000000000000000000010550072674642500240550ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x10,0x81,0x5f = fmla s0, s1, v1.s[0] 0x7e,0x11,0xa1,0x5f = fmla s30, s11, v1.s[1] 0xa4,0x18,0x87,0x5f = fmla s4, s5, v7.s[2] 0xd0,0x1a,0xb0,0x5f = fmla s16, s22, v16.s[3] 0x20,0x10,0xc1,0x5f = fmla d0, d1, v1.d[0] 0x7e,0x19,0xc1,0x5f = fmla d30, d11, v1.d[1] 0x62,0x50,0x84,0x5f = fmls s2, s3, v4.s[0] 0x5d,0x51,0xbc,0x5f = fmls s29, s10, v28.s[1] 0x85,0x59,0x97,0x5f = fmls s5, s12, v23.s[2] 0x27,0x5a,0xba,0x5f = fmls s7, s17, v26.s[3] 0x20,0x50,0xc1,0x5f = fmls d0, d1, v1.d[0] 0x7e,0x59,0xc1,0x5f = fmls d30, d11, v1.d[1] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-by-elem-mul.s.cs000064400000000000000000000010620072674642500240770ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x90,0x81,0x5f = fmul s0, s1, v1.s[0] 0x7e,0x91,0xa1,0x5f = fmul s30, s11, v1.s[1] 0xa4,0x98,0x87,0x5f = fmul s4, s5, v7.s[2] 0xd0,0x9a,0xb0,0x5f = fmul s16, s22, v16.s[3] 0x20,0x90,0xc1,0x5f = fmul d0, d1, v1.d[0] 0x7e,0x99,0xc1,0x5f = fmul d30, d11, v1.d[1] 0x46,0x90,0x88,0x7f = fmulx s6, s2, v8.s[0] 0x67,0x90,0xad,0x7f = fmulx s7, s3, v13.s[1] 0xe9,0x98,0x89,0x7f = fmulx s9, s7, v9.s[2] 0xad,0x9a,0xaa,0x7f = fmulx s13, s21, v10.s[3] 0x2f,0x91,0xc7,0x7f = fmulx d15, d9, v7.d[0] 0x8d,0x99,0xcb,0x7f = fmulx d13, d12, v11.d[1] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs000064400000000000000000000012630072674642500262350ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x00,0x30,0x40,0x5f = sqdmlal s0, h0, v0.h[0] 0x27,0x30,0x74,0x5f = sqdmlal s7, h1, v4.h[3] 0x0b,0x3a,0x48,0x5f = sqdmlal s11, h16, v8.h[4] 0xde,0x3b,0x7f,0x5f = sqdmlal s30, h30, v15.h[7] 0x00,0x30,0x83,0x5f = sqdmlal d0, s0, v3.s[0] 0xde,0x3b,0xbe,0x5f = sqdmlal d30, s30, v30.s[3] 0x28,0x31,0xae,0x5f = sqdmlal d8, s9, v14.s[1] 0x21,0x70,0x41,0x5f = sqdmlsl s1, h1, v1.h[0] 0x48,0x70,0x55,0x5f = sqdmlsl s8, h2, v5.h[1] 0xac,0x71,0x6e,0x5f = sqdmlsl s12, h13, v14.h[2] 0x9d,0x7b,0x7b,0x5f = sqdmlsl s29, h28, v11.h[7] 0x21,0x70,0x8d,0x5f = sqdmlsl d1, s1, v13.s[0] 0xff,0x7b,0x9f,0x5f = sqdmlsl d31, s31, v31.s[2] 0x50,0x7a,0xbc,0x5f = sqdmlsl d16, s18, v28.s[3] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs000064400000000000000000000015100072674642500262540ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x21,0xb0,0x51,0x5f = sqdmull s1, h1, v1.h[1] 0x48,0xb0,0x65,0x5f = sqdmull s8, h2, v5.h[2] 0x2c,0xb2,0x79,0x5f = sqdmull s12, h17, v9.h[3] 0xff,0xbb,0x7f,0x5f = sqdmull s31, h31, v15.h[7] 0x21,0xb0,0x84,0x5f = sqdmull d1, s1, v4.s[0] 0xff,0xbb,0xbf,0x5f = sqdmull d31, s31, v31.s[3] 0x49,0xb1,0x8f,0x5f = sqdmull d9, s10, v15.s[0] 0x20,0xc0,0x40,0x5f = sqdmulh h0, h1, v0.h[0] 0x6a,0xc9,0x4a,0x5f = sqdmulh h10, h11, v10.h[4] 0xb4,0xca,0x7f,0x5f = sqdmulh h20, h21, v15.h[7] 0x59,0xcb,0xbb,0x5f = sqdmulh s25, s26, v27.s[3] 0xc2,0xc0,0x87,0x5f = sqdmulh s2, s6, v7.s[0] 0xdf,0xd3,0x6e,0x5f = sqrdmulh h31, h30, v14.h[2] 0x21,0xd8,0x41,0x5f = sqrdmulh h1, h1, v1.h[4] 0xd5,0xda,0x7f,0x5f = sqrdmulh h21, h22, v15.h[7] 0xc5,0xd8,0x87,0x5f = sqrdmulh s5, s6, v7.s[2] 0x54,0xd3,0xbb,0x5f = sqrdmulh s20, s26, v27.s[1] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-compare.s.cs000064400000000000000000000007420072674642500234040ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xb4,0x8e,0xf6,0x7e = cmeq d20, d21, d22 0xb4,0x9a,0xe0,0x5e = cmeq d20, d21, #0x0 0xb4,0x3e,0xf6,0x7e = cmhs d20, d21, d22 0xb4,0x3e,0xf6,0x5e = cmge d20, d21, d22 0xb4,0x8a,0xe0,0x7e = cmge d20, d21, #0x0 0xb4,0x36,0xf6,0x7e = cmhi d20, d21, d22 0xb4,0x36,0xf6,0x5e = cmgt d20, d21, d22 0xb4,0x8a,0xe0,0x5e = cmgt d20, d21, #0x0 0xb4,0x9a,0xe0,0x7e = cmle d20, d21, #0x0 0xb4,0xaa,0xe0,0x5e = cmlt d20, d21, #0x0 0xb4,0x8e,0xf6,0x5e = cmtst d20, d21, d22 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-cvt.s.cs000064400000000000000000000024330072674642500225510ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xb6,0xd9,0x21,0x5e = scvtf s22, s13 0x95,0xd9,0x61,0x5e = scvtf d21, d12 0xb6,0xd9,0x21,0x7e = ucvtf s22, s13 0xd5,0xd9,0x61,0x7e = ucvtf d21, d14 0xb6,0xe5,0x20,0x5f = scvtf s22, s13, #32 0x95,0xe5,0x40,0x5f = scvtf d21, d12, #64 0xb6,0xe5,0x20,0x7f = ucvtf s22, s13, #32 0xd5,0xe5,0x40,0x7f = ucvtf d21, d14, #64 0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1 0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1 0x95,0xfd,0x3f,0x7f = fcvtzu s21, s12, #1 0x95,0xfd,0x7f,0x7f = fcvtzu d21, d12, #1 0xb6,0x69,0x61,0x7e = fcvtxn s22, d13 0xac,0xc9,0x21,0x5e = fcvtas s12, s13 0xd5,0xc9,0x61,0x5e = fcvtas d21, d14 0xac,0xc9,0x21,0x7e = fcvtau s12, s13 0xd5,0xc9,0x61,0x7e = fcvtau d21, d14 0xb6,0xb9,0x21,0x5e = fcvtms s22, s13 0xd5,0xb9,0x61,0x5e = fcvtms d21, d14 0xac,0xb9,0x21,0x7e = fcvtmu s12, s13 0xd5,0xb9,0x61,0x7e = fcvtmu d21, d14 0xb6,0xa9,0x21,0x5e = fcvtns s22, s13 0xd5,0xa9,0x61,0x5e = fcvtns d21, d14 0xac,0xa9,0x21,0x7e = fcvtnu s12, s13 0xd5,0xa9,0x61,0x7e = fcvtnu d21, d14 0xb6,0xa9,0xa1,0x5e = fcvtps s22, s13 0xd5,0xa9,0xe1,0x5e = fcvtps d21, d14 0xac,0xa9,0xa1,0x7e = fcvtpu s12, s13 0xd5,0xa9,0xe1,0x7e = fcvtpu d21, d14 0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13 0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14 0xac,0xb9,0xa1,0x7e = fcvtzu s12, s13 0xd5,0xb9,0xe1,0x7e = fcvtzu d21, d14 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-dup.s.cs000064400000000000000000000015550072674642500225510ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x00,0x04,0x1f,0x5e = mov b0, v0.b[15] 0x01,0x04,0x0f,0x5e = mov b1, v0.b[7] 0x11,0x04,0x01,0x5e = mov b17, v0.b[0] 0xe5,0x07,0x1e,0x5e = mov h5, v31.h[7] 0x29,0x04,0x12,0x5e = mov h9, v1.h[4] 0x2b,0x06,0x02,0x5e = mov h11, v17.h[0] 0x42,0x04,0x1c,0x5e = mov s2, v2.s[3] 0xa4,0x06,0x04,0x5e = mov s4, v21.s[0] 0xbf,0x06,0x14,0x5e = mov s31, v21.s[2] 0xa3,0x04,0x08,0x5e = mov d3, v5.d[0] 0xa6,0x04,0x18,0x5e = mov d6, v5.d[1] 0x00,0x04,0x1f,0x5e = mov b0, v0.b[15] 0x01,0x04,0x0f,0x5e = mov b1, v0.b[7] 0x11,0x04,0x01,0x5e = mov b17, v0.b[0] 0xe5,0x07,0x1e,0x5e = mov h5, v31.h[7] 0x29,0x04,0x12,0x5e = mov h9, v1.h[4] 0x2b,0x06,0x02,0x5e = mov h11, v17.h[0] 0x42,0x04,0x1c,0x5e = mov s2, v2.s[3] 0xa4,0x06,0x04,0x5e = mov s4, v21.s[0] 0xbf,0x06,0x14,0x5e = mov s31, v21.s[2] 0xa3,0x04,0x08,0x5e = mov d3, v5.d[0] 0xa6,0x04,0x18,0x5e = mov d6, v5.d[1] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-extract-narrow.s.cs000064400000000000000000000005510072674642500247340ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xd3,0x29,0x21,0x7e = sqxtun b19, h14 0xf5,0x29,0x61,0x7e = sqxtun h21, s15 0x94,0x29,0xa1,0x7e = sqxtun s20, d12 0x52,0x4a,0x21,0x5e = sqxtn b18, h18 0x34,0x4a,0x61,0x5e = sqxtn h20, s17 0xd3,0x49,0xa1,0x5e = sqxtn s19, d14 0x52,0x4a,0x21,0x7e = uqxtn b18, h18 0x34,0x4a,0x61,0x7e = uqxtn h20, s17 0xd3,0x49,0xa1,0x7e = uqxtn s19, d14 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-fp-compare.s.cs000064400000000000000000000015530072674642500240100ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x6a,0xe5,0x2c,0x5e = fcmeq s10, s11, s12 0xb4,0xe6,0x76,0x5e = fcmeq d20, d21, d22 0x6a,0xd9,0xa0,0x5e = fcmeq s10, s11, #0.0 0xb4,0xda,0xe0,0x5e = fcmeq d20, d21, #0.0 0x6a,0xe5,0x2c,0x7e = fcmge s10, s11, s12 0xb4,0xe6,0x76,0x7e = fcmge d20, d21, d22 0x6a,0xc9,0xa0,0x7e = fcmge s10, s11, #0.0 0xb4,0xca,0xe0,0x7e = fcmge d20, d21, #0.0 0x6a,0xe5,0xac,0x7e = fcmgt s10, s11, s12 0xb4,0xe6,0xf6,0x7e = fcmgt d20, d21, d22 0x6a,0xc9,0xa0,0x5e = fcmgt s10, s11, #0.0 0xb4,0xca,0xe0,0x5e = fcmgt d20, d21, #0.0 0x6a,0xd9,0xa0,0x7e = fcmle s10, s11, #0.0 0xb4,0xda,0xe0,0x7e = fcmle d20, d21, #0.0 0x6a,0xe9,0xa0,0x5e = fcmlt s10, s11, #0.0 0xb4,0xea,0xe0,0x5e = fcmlt d20, d21, #0.0 0x6a,0xed,0x2c,0x7e = facge s10, s11, s12 0xb4,0xee,0x76,0x7e = facge d20, d21, d22 0x6a,0xed,0xac,0x7e = facgt s10, s11, s12 0xb4,0xee,0xf6,0x7e = facgt d20, d21, d22 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-mul.s.cs000064400000000000000000000010440072674642500225470ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x6a,0xb5,0x6c,0x5e = sqdmulh h10, h11, h12 0xb4,0xb6,0xa2,0x5e = sqdmulh s20, s21, s2 0x6a,0xb5,0x6c,0x7e = sqrdmulh h10, h11, h12 0xb4,0xb6,0xa2,0x7e = sqrdmulh s20, s21, s2 0xd4,0xde,0x2f,0x5e = fmulx s20, s22, s15 0x77,0xdd,0x61,0x5e = fmulx d23, d11, d1 0x71,0x93,0x6c,0x5e = sqdmlal s17, h27, h12 0x13,0x93,0xac,0x5e = sqdmlal d19, s24, s12 0x8e,0xb1,0x79,0x5e = sqdmlsl s14, h12, h25 0xec,0xb2,0xad,0x5e = sqdmlsl d12, s23, s13 0xcc,0xd2,0x6c,0x5e = sqdmull s12, h22, h12 0xcf,0xd2,0xac,0x5e = sqdmull d15, s22, s12 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-neg.s.cs000064400000000000000000000003200072674642500225170ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x1d,0xbb,0xe0,0x7e = neg d29, d24 0xd3,0x79,0x20,0x7e = sqneg b19, b14 0xf5,0x79,0x60,0x7e = sqneg h21, h15 0x94,0x79,0xa0,0x7e = sqneg s20, s12 0x92,0x79,0xe0,0x7e = sqneg d18, d12 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-recip.s.cs000064400000000000000000000006530072674642500230610ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x15,0xfe,0x2d,0x5e = frecps s21, s16, s13 0xd6,0xff,0x75,0x5e = frecps d22, d30, d21 0xb5,0xfc,0xac,0x5e = frsqrts s21, s5, s12 0xc8,0xfe,0xf2,0x5e = frsqrts d8, d22, d18 0xd3,0xd9,0xa1,0x5e = frecpe s19, s14 0xad,0xd9,0xe1,0x5e = frecpe d13, d13 0x52,0xf9,0xa1,0x5e = frecpx s18, s10 0x70,0xfa,0xe1,0x5e = frecpx d16, d19 0xb6,0xd9,0xa1,0x7e = frsqrte s22, s13 0x95,0xd9,0xe1,0x7e = frsqrte d21, d12 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-reduce-pairwise.s.cs000064400000000000000000000001450072674642500250430ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0xb8,0xf1,0x5e = addp d0, v1.2d 0x34,0xd8,0x70,0x7e = faddp d20, v1.2d capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-rounding-shift.s.cs000064400000000000000000000001530072674642500247120ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xf1,0x57,0xe8,0x5e = srshl d17, d31, d8 0xf1,0x57,0xe8,0x7e = urshl d17, d31, d8 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-saturating-add-sub.s.cs000064400000000000000000000017250072674642500254560ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x0c,0x22,0x5e = sqadd b0, b1, b2 0x6a,0x0d,0x6c,0x5e = sqadd h10, h11, h12 0xb4,0x0e,0xa2,0x5e = sqadd s20, s21, s2 0xf1,0x0f,0xe8,0x5e = sqadd d17, d31, d8 0x20,0x0c,0x22,0x7e = uqadd b0, b1, b2 0x6a,0x0d,0x6c,0x7e = uqadd h10, h11, h12 0xb4,0x0e,0xa2,0x7e = uqadd s20, s21, s2 0xf1,0x0f,0xe8,0x7e = uqadd d17, d31, d8 0x20,0x2c,0x22,0x5e = sqsub b0, b1, b2 0x6a,0x2d,0x6c,0x5e = sqsub h10, h11, h12 0xb4,0x2e,0xa2,0x5e = sqsub s20, s21, s2 0xf1,0x2f,0xe8,0x5e = sqsub d17, d31, d8 0x20,0x2c,0x22,0x7e = uqsub b0, b1, b2 0x6a,0x2d,0x6c,0x7e = uqsub h10, h11, h12 0xb4,0x2e,0xa2,0x7e = uqsub s20, s21, s2 0xf1,0x2f,0xe8,0x7e = uqsub d17, d31, d8 0xd3,0x39,0x20,0x5e = suqadd b19, b14 0xf4,0x39,0x60,0x5e = suqadd h20, h15 0x95,0x39,0xa0,0x5e = suqadd s21, s12 0xd2,0x3a,0xe0,0x5e = suqadd d18, d22 0xd3,0x39,0x20,0x7e = usqadd b19, b14 0xf4,0x39,0x60,0x7e = usqadd h20, h15 0x95,0x39,0xa0,0x7e = usqadd s21, s12 0xd2,0x3a,0xe0,0x7e = usqadd d18, d22 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs000064400000000000000000000005470072674642500271000ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x5c,0x22,0x5e = sqrshl b0, b1, b2 0x6a,0x5d,0x6c,0x5e = sqrshl h10, h11, h12 0xb4,0x5e,0xa2,0x5e = sqrshl s20, s21, s2 0xf1,0x5f,0xe8,0x5e = sqrshl d17, d31, d8 0x20,0x5c,0x22,0x7e = uqrshl b0, b1, b2 0x6a,0x5d,0x6c,0x7e = uqrshl h10, h11, h12 0xb4,0x5e,0xa2,0x7e = uqrshl s20, s21, s2 0xf1,0x5f,0xe8,0x7e = uqrshl d17, d31, d8 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-saturating-shift.s.cs000064400000000000000000000005370072674642500252540ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x4c,0x22,0x5e = sqshl b0, b1, b2 0x6a,0x4d,0x6c,0x5e = sqshl h10, h11, h12 0xb4,0x4e,0xa2,0x5e = sqshl s20, s21, s2 0xf1,0x4f,0xe8,0x5e = sqshl d17, d31, d8 0x20,0x4c,0x22,0x7e = uqshl b0, b1, b2 0x6a,0x4d,0x6c,0x7e = uqshl h10, h11, h12 0xb4,0x4e,0xa2,0x7e = uqshl s20, s21, s2 0xf1,0x4f,0xe8,0x7e = uqshl d17, d31, d8 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-shift-imm.s.cs000064400000000000000000000033340072674642500236530ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x0f,0x06,0x74,0x5f = sshr d15, d16, #12 0x2a,0x06,0x6e,0x7f = ushr d10, d17, #18 0x53,0x26,0x79,0x5f = srshr d19, d18, #7 0xf4,0x26,0x61,0x7f = urshr d20, d23, #31 0x92,0x15,0x6b,0x5f = ssra d18, d12, #21 0xb4,0x15,0x43,0x7f = usra d20, d13, #61 0x6f,0x35,0x6d,0x5f = srsra d15, d11, #19 0x52,0x35,0x73,0x7f = ursra d18, d10, #13 0x47,0x55,0x4c,0x5f = shl d7, d10, #12 0x6b,0x76,0x0f,0x5f = sqshl b11, b19, #7 0x4d,0x76,0x1b,0x5f = sqshl h13, h18, #11 0x2e,0x76,0x36,0x5f = sqshl s14, s17, #22 0x0f,0x76,0x73,0x5f = sqshl d15, d16, #51 0xf2,0x75,0x0e,0x7f = uqshl b18, b15, #6 0x4b,0x76,0x17,0x7f = uqshl h11, h18, #7 0x6e,0x76,0x32,0x7f = uqshl s14, s19, #18 0x8f,0x75,0x53,0x7f = uqshl d15, d12, #19 0x4f,0x66,0x0e,0x7f = sqshlu b15, b18, #6 0x33,0x66,0x16,0x7f = sqshlu h19, h17, #6 0xd0,0x65,0x39,0x7f = sqshlu s16, s14, #25 0xab,0x65,0x60,0x7f = sqshlu d11, d13, #32 0x8a,0x45,0x72,0x7f = sri d10, d12, #14 0xca,0x55,0x4c,0x7f = sli d10, d14, #12 0xea,0x95,0x0b,0x5f = sqshrn b10, h15, #5 0x51,0x95,0x1c,0x5f = sqshrn h17, s10, #4 0x52,0x95,0x21,0x5f = sqshrn s18, d10, #31 0x4c,0x95,0x09,0x7f = uqshrn b12, h10, #7 0xca,0x95,0x1b,0x7f = uqshrn h10, s14, #5 0x8a,0x95,0x33,0x7f = uqshrn s10, d12, #13 0xaa,0x9d,0x0e,0x5f = sqrshrn b10, h13, #2 0x4f,0x9d,0x1a,0x5f = sqrshrn h15, s10, #6 0x8f,0x9d,0x37,0x5f = sqrshrn s15, d12, #9 0x8a,0x9d,0x0b,0x7f = uqrshrn b10, h12, #5 0x4c,0x9d,0x12,0x7f = uqrshrn h12, s10, #14 0x4a,0x9d,0x27,0x7f = uqrshrn s10, d10, #25 0x4f,0x85,0x09,0x7f = sqshrun b15, h10, #7 0xd4,0x85,0x1d,0x7f = sqshrun h20, s14, #3 0xea,0x85,0x31,0x7f = sqshrun s10, d15, #15 0x51,0x8d,0x0a,0x7f = sqrshrun b17, h10, #6 0xaa,0x8d,0x11,0x7f = sqrshrun h10, s13, #15 0x16,0x8e,0x21,0x7f = sqrshrun s22, d16, #31 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-scalar-shift.s.cs000064400000000000000000000001510072674642500230650ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xf1,0x47,0xe8,0x5e = sshl d17, d31, d8 0xf1,0x47,0xe8,0x7e = ushl d17, d31, d8 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-shift-left-long.s.cs000064400000000000000000000010750072674642500235150ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0xa4,0x0b,0x0f = sshll v0.8h, v1.8b, #3 0x20,0xa4,0x13,0x0f = sshll v0.4s, v1.4h, #3 0x20,0xa4,0x23,0x0f = sshll v0.2d, v1.2s, #3 0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3 0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3 0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3 0x20,0xa4,0x0b,0x2f = ushll v0.8h, v1.8b, #3 0x20,0xa4,0x13,0x2f = ushll v0.4s, v1.4h, #3 0x20,0xa4,0x23,0x2f = ushll v0.2d, v1.2s, #3 0x20,0xa4,0x0b,0x6f = ushll2 v0.8h, v1.16b, #3 0x20,0xa4,0x13,0x6f = ushll2 v0.4s, v1.8h, #3 0x20,0xa4,0x23,0x6f = ushll2 v0.2d, v1.4s, #3 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-shift.s.cs000064400000000000000000000017400072674642500216270ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x44,0x22,0x0e = sshl v0.8b, v1.8b, v2.8b 0x20,0x44,0x22,0x4e = sshl v0.16b, v1.16b, v2.16b 0x20,0x44,0x62,0x0e = sshl v0.4h, v1.4h, v2.4h 0x20,0x44,0x62,0x4e = sshl v0.8h, v1.8h, v2.8h 0x20,0x44,0xa2,0x0e = sshl v0.2s, v1.2s, v2.2s 0x20,0x44,0xa2,0x4e = sshl v0.4s, v1.4s, v2.4s 0x20,0x44,0xe2,0x4e = sshl v0.2d, v1.2d, v2.2d 0x20,0x44,0x22,0x2e = ushl v0.8b, v1.8b, v2.8b 0x20,0x44,0x22,0x6e = ushl v0.16b, v1.16b, v2.16b 0x20,0x44,0x62,0x2e = ushl v0.4h, v1.4h, v2.4h 0x20,0x44,0x62,0x6e = ushl v0.8h, v1.8h, v2.8h 0x20,0x44,0xa2,0x2e = ushl v0.2s, v1.2s, v2.2s 0x20,0x44,0xa2,0x6e = ushl v0.4s, v1.4s, v2.4s 0x20,0x44,0xe2,0x6e = ushl v0.2d, v1.2d, v2.2d 0x20,0x54,0x0b,0x0f = shl v0.8b, v1.8b, #3 0x20,0x54,0x13,0x0f = shl v0.4h, v1.4h, #3 0x20,0x54,0x23,0x0f = shl v0.2s, v1.2s, #3 0x20,0x54,0x0b,0x4f = shl v0.16b, v1.16b, #3 0x20,0x54,0x13,0x4f = shl v0.8h, v1.8h, #3 0x20,0x54,0x23,0x4f = shl v0.4s, v1.4s, #3 0x20,0x54,0x43,0x4f = shl v0.2d, v1.2d, #3 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-simd-copy.s.cs000064400000000000000000000032140072674642500224140ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x22,0x1c,0x05,0x4e = mov v2.b[2], w1 0xc7,0x1d,0x1e,0x4e = mov v7.h[7], w14 0xd4,0x1f,0x04,0x4e = mov v20.s[0], w30 0xe1,0x1c,0x18,0x4e = mov v1.d[1], x7 0x22,0x1c,0x05,0x4e = mov v2.b[2], w1 0xc7,0x1d,0x1e,0x4e = mov v7.h[7], w14 0xd4,0x1f,0x04,0x4e = mov v20.s[0], w30 0xe1,0x1c,0x18,0x4e = mov v1.d[1], x7 0x01,0x2c,0x1f,0x0e = smov w1, v0.b[15] 0xce,0x2c,0x12,0x0e = smov w14, v6.h[4] 0x01,0x2c,0x1f,0x4e = smov x1, v0.b[15] 0xce,0x2c,0x12,0x4e = smov x14, v6.h[4] 0x34,0x2d,0x14,0x4e = smov x20, v9.s[2] 0x01,0x3c,0x1f,0x0e = umov w1, v0.b[15] 0xce,0x3c,0x12,0x0e = umov w14, v6.h[4] 0x34,0x3d,0x14,0x0e = mov w20, v9.s[2] 0x47,0x3e,0x18,0x4e = mov x7, v18.d[1] 0x34,0x3d,0x14,0x0e = mov w20, v9.s[2] 0x47,0x3e,0x18,0x4e = mov x7, v18.d[1] 0x61,0x34,0x1d,0x6e = mov v1.b[14], v3.b[6] 0xe6,0x54,0x1e,0x6e = mov v6.h[7], v7.h[5] 0xcf,0x46,0x1c,0x6e = mov v15.s[3], v22.s[2] 0x80,0x44,0x08,0x6e = mov v0.d[0], v4.d[1] 0x61,0x34,0x1d,0x6e = mov v1.b[14], v3.b[6] 0xe6,0x54,0x1e,0x6e = mov v6.h[7], v7.h[5] 0xcf,0x46,0x1c,0x6e = mov v15.s[3], v22.s[2] 0x80,0x44,0x08,0x6e = mov v0.d[0], v4.d[1] 0x41,0x04,0x05,0x0e = dup v1.8b, v2.b[2] 0xeb,0x04,0x1e,0x0e = dup v11.4h, v7.h[7] 0x91,0x06,0x04,0x0e = dup v17.2s, v20.s[0] 0x41,0x04,0x05,0x4e = dup v1.16b, v2.b[2] 0xeb,0x04,0x1e,0x4e = dup v11.8h, v7.h[7] 0x91,0x06,0x04,0x4e = dup v17.4s, v20.s[0] 0x25,0x04,0x18,0x4e = dup v5.2d, v1.d[1] 0x21,0x0c,0x01,0x0e = dup v1.8b, w1 0xcb,0x0d,0x02,0x0e = dup v11.4h, w14 0xd1,0x0f,0x04,0x0e = dup v17.2s, w30 0x41,0x0c,0x01,0x4e = dup v1.16b, w2 0x0b,0x0e,0x02,0x4e = dup v11.8h, w16 0x91,0x0f,0x04,0x4e = dup v17.4s, w28 0x05,0x0c,0x08,0x4e = dup v5.2d, x0 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-simd-ldst-multi-elem.s.cs000064400000000000000000000247270072674642500244740ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x00,0x70,0x00,0x4c = st1 {v0.16b}, [x0] 0xef,0x75,0x00,0x4c = st1 {v15.8h}, [x15] 0xff,0x7b,0x00,0x4c = st1 {v31.4s}, [sp] 0x00,0x7c,0x00,0x4c = st1 {v0.2d}, [x0] 0x00,0x70,0x00,0x0c = st1 {v0.8b}, [x0] 0xef,0x75,0x00,0x0c = st1 {v15.4h}, [x15] 0xff,0x7b,0x00,0x0c = st1 {v31.2s}, [sp] 0x00,0x7c,0x00,0x0c = st1 {v0.1d}, [x0] 0x00,0xa0,0x00,0x4c = st1 {v0.16b, v1.16b}, [x0] 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15] 0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp] 0x00,0xac,0x00,0x4c = st1 {v0.2d, v1.2d}, [x0] 0x00,0xa0,0x00,0x0c = st1 {v0.8b, v1.8b}, [x0] 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15] 0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp] 0x00,0xac,0x00,0x0c = st1 {v0.1d, v1.1d}, [x0] 0x00,0xa0,0x00,0x4c = st1 {v0.16b, v1.16b}, [x0] 0xef,0xa5,0x00,0x4c = st1 {v15.8h, v16.8h}, [x15] 0xff,0xab,0x00,0x4c = st1 {v31.4s, v0.4s}, [sp] 0x00,0xac,0x00,0x4c = st1 {v0.2d, v1.2d}, [x0] 0x00,0xa0,0x00,0x0c = st1 {v0.8b, v1.8b}, [x0] 0xef,0xa5,0x00,0x0c = st1 {v15.4h, v16.4h}, [x15] 0xff,0xab,0x00,0x0c = st1 {v31.2s, v0.2s}, [sp] 0x00,0xac,0x00,0x0c = st1 {v0.1d, v1.1d}, [x0] 0x00,0x60,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x6c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x60,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x6c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0] 0x00,0x60,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x65,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x6b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x6c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x60,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x65,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x6b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x6c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0] 0x00,0x20,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x2b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x2c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x20,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x2b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x2c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] 0x00,0x20,0x00,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x25,0x00,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x2b,0x00,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x2c,0x00,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x20,0x00,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x25,0x00,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x2b,0x00,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x2c,0x00,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] 0x00,0x80,0x00,0x4c = st2 {v0.16b, v1.16b}, [x0] 0xef,0x85,0x00,0x4c = st2 {v15.8h, v16.8h}, [x15] 0xff,0x8b,0x00,0x4c = st2 {v31.4s, v0.4s}, [sp] 0x00,0x8c,0x00,0x4c = st2 {v0.2d, v1.2d}, [x0] 0x00,0x80,0x00,0x0c = st2 {v0.8b, v1.8b}, [x0] 0xef,0x85,0x00,0x0c = st2 {v15.4h, v16.4h}, [x15] 0xff,0x8b,0x00,0x0c = st2 {v31.2s, v0.2s}, [sp] 0x00,0x80,0x00,0x4c = st2 {v0.16b, v1.16b}, [x0] 0xef,0x85,0x00,0x4c = st2 {v15.8h, v16.8h}, [x15] 0xff,0x8b,0x00,0x4c = st2 {v31.4s, v0.4s}, [sp] 0x00,0x8c,0x00,0x4c = st2 {v0.2d, v1.2d}, [x0] 0x00,0x80,0x00,0x0c = st2 {v0.8b, v1.8b}, [x0] 0xef,0x85,0x00,0x0c = st2 {v15.4h, v16.4h}, [x15] 0xff,0x8b,0x00,0x0c = st2 {v31.2s, v0.2s}, [sp] 0x00,0x40,0x00,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x45,0x00,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x4b,0x00,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x4c,0x00,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x40,0x00,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x45,0x00,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x4b,0x00,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x40,0x00,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x45,0x00,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x4b,0x00,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x4c,0x00,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x40,0x00,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x45,0x00,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x4b,0x00,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x00,0x00,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x05,0x00,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x0b,0x00,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x0c,0x00,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x00,0x00,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x05,0x00,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x0b,0x00,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x00,0x00,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x05,0x00,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x0b,0x00,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x0c,0x00,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x00,0x00,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x05,0x00,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x0b,0x00,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x70,0x40,0x4c = ld1 {v0.16b}, [x0] 0xef,0x75,0x40,0x4c = ld1 {v15.8h}, [x15] 0xff,0x7b,0x40,0x4c = ld1 {v31.4s}, [sp] 0x00,0x7c,0x40,0x4c = ld1 {v0.2d}, [x0] 0x00,0x70,0x40,0x0c = ld1 {v0.8b}, [x0] 0xef,0x75,0x40,0x0c = ld1 {v15.4h}, [x15] 0xff,0x7b,0x40,0x0c = ld1 {v31.2s}, [sp] 0x00,0x7c,0x40,0x0c = ld1 {v0.1d}, [x0] 0x00,0xa0,0x40,0x4c = ld1 {v0.16b, v1.16b}, [x0] 0xef,0xa5,0x40,0x4c = ld1 {v15.8h, v16.8h}, [x15] 0xff,0xab,0x40,0x4c = ld1 {v31.4s, v0.4s}, [sp] 0x00,0xac,0x40,0x4c = ld1 {v0.2d, v1.2d}, [x0] 0x00,0xa0,0x40,0x0c = ld1 {v0.8b, v1.8b}, [x0] 0xef,0xa5,0x40,0x0c = ld1 {v15.4h, v16.4h}, [x15] 0xff,0xab,0x40,0x0c = ld1 {v31.2s, v0.2s}, [sp] 0x00,0xac,0x40,0x0c = ld1 {v0.1d, v1.1d}, [x0] 0x00,0xa0,0x40,0x4c = ld1 {v0.16b, v1.16b}, [x0] 0xef,0xa5,0x40,0x4c = ld1 {v15.8h, v16.8h}, [x15] 0xff,0xab,0x40,0x4c = ld1 {v31.4s, v0.4s}, [sp] 0x00,0xac,0x40,0x4c = ld1 {v0.2d, v1.2d}, [x0] 0x00,0xa0,0x40,0x0c = ld1 {v0.8b, v1.8b}, [x0] 0xef,0xa5,0x40,0x0c = ld1 {v15.4h, v16.4h}, [x15] 0xff,0xab,0x40,0x0c = ld1 {v31.2s, v0.2s}, [sp] 0x00,0xac,0x40,0x0c = ld1 {v0.1d, v1.1d}, [x0] 0x00,0x60,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x65,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x6b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x6c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x60,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x65,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x6b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x6c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0] 0x00,0x60,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x65,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x6b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x6c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x60,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x65,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x6b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x6c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0] 0x00,0x20,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x25,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x2b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x2c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x20,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x25,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x2b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x2c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] 0x00,0x20,0x40,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x25,0x40,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x2b,0x40,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x2c,0x40,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x20,0x40,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x25,0x40,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x2b,0x40,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x2c,0x40,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] 0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0] 0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15] 0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp] 0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0] 0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0] 0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15] 0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp] 0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0] 0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15] 0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp] 0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0] 0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0] 0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15] 0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp] 0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp] 0x00,0x00,0x40,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x05,0x40,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x0b,0x40,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x0c,0x40,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x00,0x40,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x05,0x40,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x0b,0x40,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0x00,0x00,0x40,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0x05,0x40,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0x0b,0x40,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0x0c,0x40,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0x00,0x40,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0x05,0x40,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0x0b,0x40,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-simd-ldst-one-elem.s.cs000064400000000000000000000155550072674642500241220ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x00,0xc0,0x40,0x4d = ld1r {v0.16b}, [x0] 0xef,0xc5,0x40,0x4d = ld1r {v15.8h}, [x15] 0xff,0xcb,0x40,0x4d = ld1r {v31.4s}, [sp] 0x00,0xcc,0x40,0x4d = ld1r {v0.2d}, [x0] 0x00,0xc0,0x40,0x0d = ld1r {v0.8b}, [x0] 0xef,0xc5,0x40,0x0d = ld1r {v15.4h}, [x15] 0xff,0xcb,0x40,0x0d = ld1r {v31.2s}, [sp] 0x00,0xcc,0x40,0x0d = ld1r {v0.1d}, [x0] 0x00,0xc0,0x60,0x4d = ld2r {v0.16b, v1.16b}, [x0] 0xef,0xc5,0x60,0x4d = ld2r {v15.8h, v16.8h}, [x15] 0xff,0xcb,0x60,0x4d = ld2r {v31.4s, v0.4s}, [sp] 0x00,0xcc,0x60,0x4d = ld2r {v0.2d, v1.2d}, [x0] 0x00,0xc0,0x60,0x0d = ld2r {v0.8b, v1.8b}, [x0] 0xef,0xc5,0x60,0x0d = ld2r {v15.4h, v16.4h}, [x15] 0xff,0xcb,0x60,0x0d = ld2r {v31.2s, v0.2s}, [sp] 0xff,0xcf,0x60,0x0d = ld2r {v31.1d, v0.1d}, [sp] 0x00,0xe0,0x40,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0] 0xef,0xe5,0x40,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15] 0xff,0xeb,0x40,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp] 0x00,0xec,0x40,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0] 0x00,0xe0,0x40,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0] 0xef,0xe5,0x40,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15] 0xff,0xeb,0x40,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp] 0xff,0xef,0x40,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp] 0x00,0xe0,0x60,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] 0xef,0xe5,0x60,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] 0xff,0xeb,0x60,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] 0x00,0xec,0x60,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] 0x00,0xe0,0x60,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] 0xef,0xe5,0x60,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] 0xff,0xeb,0x60,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] 0xff,0xef,0x60,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] 0x00,0x04,0x40,0x4d = ld1 {v0.b}[9], [x0] 0xef,0x59,0x40,0x4d = ld1 {v15.h}[7], [x15] 0xff,0x93,0x40,0x4d = ld1 {v31.s}[3], [sp] 0x00,0x84,0x40,0x4d = ld1 {v0.d}[1], [x0] 0x00,0x04,0x60,0x4d = ld2 {v0.b, v1.b}[9], [x0] 0xef,0x59,0x60,0x4d = ld2 {v15.h, v16.h}[7], [x15] 0xff,0x93,0x60,0x4d = ld2 {v31.s, v0.s}[3], [sp] 0x00,0x84,0x60,0x4d = ld2 {v0.d, v1.d}[1], [x0] 0x00,0x24,0x40,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0] 0xef,0x79,0x40,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15] 0xff,0xb3,0x40,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp] 0x00,0xa4,0x40,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0] 0x00,0x24,0x60,0x4d = ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] 0xef,0x79,0x60,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] 0xff,0xb3,0x60,0x4d = ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] 0x00,0xa4,0x60,0x4d = ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] 0x00,0x04,0x00,0x4d = st1 {v0.b}[9], [x0] 0xef,0x59,0x00,0x4d = st1 {v15.h}[7], [x15] 0xff,0x93,0x00,0x4d = st1 {v31.s}[3], [sp] 0x00,0x84,0x00,0x4d = st1 {v0.d}[1], [x0] 0x00,0x04,0x20,0x4d = st2 {v0.b, v1.b}[9], [x0] 0xef,0x59,0x20,0x4d = st2 {v15.h, v16.h}[7], [x15] 0xff,0x93,0x20,0x4d = st2 {v31.s, v0.s}[3], [sp] 0x00,0x84,0x20,0x4d = st2 {v0.d, v1.d}[1], [x0] 0x00,0x24,0x00,0x4d = st3 {v0.b, v1.b, v2.b}[9], [x0] 0xef,0x79,0x00,0x4d = st3 {v15.h, v16.h, v17.h}[7], [x15] 0xff,0xb3,0x00,0x4d = st3 {v31.s, v0.s, v1.s}[3], [sp] 0x00,0xa4,0x00,0x4d = st3 {v0.d, v1.d, v2.d}[1], [x0] 0x00,0x24,0x20,0x4d = st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] 0xef,0x79,0x20,0x4d = st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] 0xff,0xb3,0x20,0x4d = st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] 0x00,0xa4,0x20,0x4d = st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] 0x00,0xc0,0xdf,0x4d = ld1r {v0.16b}, [x0], #1 0xef,0xc5,0xdf,0x4d = ld1r {v15.8h}, [x15], #2 0xff,0xcb,0xdf,0x4d = ld1r {v31.4s}, [sp], #4 0x00,0xcc,0xdf,0x4d = ld1r {v0.2d}, [x0], #8 0x00,0xc0,0xc0,0x0d = ld1r {v0.8b}, [x0], x0 0xef,0xc5,0xc1,0x0d = ld1r {v15.4h}, [x15], x1 0xff,0xcb,0xc2,0x0d = ld1r {v31.2s}, [sp], x2 0x00,0xcc,0xc3,0x0d = ld1r {v0.1d}, [x0], x3 0x00,0xc0,0xff,0x4d = ld2r {v0.16b, v1.16b}, [x0], #2 0xef,0xc5,0xff,0x4d = ld2r {v15.8h, v16.8h}, [x15], #4 0xff,0xcb,0xff,0x4d = ld2r {v31.4s, v0.4s}, [sp], #8 0x00,0xcc,0xff,0x4d = ld2r {v0.2d, v1.2d}, [x0], #16 0x00,0xc0,0xe6,0x0d = ld2r {v0.8b, v1.8b}, [x0], x6 0xef,0xc5,0xe7,0x0d = ld2r {v15.4h, v16.4h}, [x15], x7 0xff,0xcb,0xe9,0x0d = ld2r {v31.2s, v0.2s}, [sp], x9 0x1f,0xcc,0xe5,0x0d = ld2r {v31.1d, v0.1d}, [x0], x5 0x00,0xe0,0xc9,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 0xef,0xe5,0xc6,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 0xff,0xeb,0xc7,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 0x00,0xec,0xc5,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 0x00,0xe0,0xdf,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 0xef,0xe5,0xdf,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 0xff,0xeb,0xdf,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 0xff,0xef,0xdf,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 0x00,0xe0,0xff,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 0xef,0xe5,0xff,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 0xff,0xeb,0xff,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 0x00,0xec,0xff,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 0x00,0xe0,0xe5,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 0xef,0xe5,0xe9,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 0xff,0xeb,0xfe,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 0xff,0xef,0xe7,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 0x00,0x04,0xdf,0x4d = ld1 {v0.b}[9], [x0], #1 0xef,0x59,0xc9,0x4d = ld1 {v15.h}[7], [x15], x9 0xff,0x93,0xc6,0x4d = ld1 {v31.s}[3], [sp], x6 0x00,0x84,0xdf,0x4d = ld1 {v0.d}[1], [x0], #8 0x00,0x04,0xe3,0x4d = ld2 {v0.b, v1.b}[9], [x0], x3 0xef,0x59,0xff,0x4d = ld2 {v15.h, v16.h}[7], [x15], #4 0xff,0x93,0xff,0x4d = ld2 {v31.s, v0.s}[3], [sp], #8 0x00,0x84,0xe0,0x4d = ld2 {v0.d, v1.d}[1], [x0], x0 0x00,0x24,0xdf,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 0xef,0x79,0xdf,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 0xff,0xb3,0xc3,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 0x00,0xa4,0xc6,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 0x00,0x24,0xe5,0x4d = ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 0xef,0x79,0xe7,0x4d = ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 0xff,0xb3,0xff,0x4d = ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 0x00,0xa4,0xff,0x4d = ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 0x00,0x04,0x9f,0x4d = st1 {v0.b}[9], [x0], #1 0xef,0x59,0x89,0x4d = st1 {v15.h}[7], [x15], x9 0xff,0x93,0x86,0x4d = st1 {v31.s}[3], [sp], x6 0x00,0x84,0x9f,0x4d = st1 {v0.d}[1], [x0], #8 0x00,0x04,0xa3,0x4d = st2 {v0.b, v1.b}[9], [x0], x3 0xef,0x59,0xbf,0x4d = st2 {v15.h, v16.h}[7], [x15], #4 0xff,0x93,0xbf,0x4d = st2 {v31.s, v0.s}[3], [sp], #8 0x00,0x84,0xa0,0x4d = st2 {v0.d, v1.d}[1], [x0], x0 0x00,0x24,0x9f,0x4d = st3 {v0.b, v1.b, v2.b}[9], [x0], #3 0xef,0x79,0x9f,0x4d = st3 {v15.h, v16.h, v17.h}[7], [x15], #6 0xff,0xb3,0x83,0x4d = st3 {v31.s, v0.s, v1.s}[3], [sp], x3 0x00,0xa4,0x86,0x4d = st3 {v0.d, v1.d, v2.d}[1], [x0], x6 0x00,0x24,0xa5,0x4d = st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 0xef,0x79,0xa7,0x4d = st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 0xff,0xb3,0xbf,0x4d = st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 0x00,0xa4,0xbf,0x4d = st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-simd-misc.s.cs000064400000000000000000000213070072674642500224000ustar 00000000000000# CS_ARCH_ARM64, 0, None 0xe0,0x0b,0x20,0x4e = rev64 v0.16b, v31.16b 0x82,0x08,0x60,0x4e = rev64 v2.8h, v4.8h 0x06,0x09,0xa0,0x4e = rev64 v6.4s, v8.4s 0x21,0x09,0x20,0x0e = rev64 v1.8b, v9.8b 0xad,0x0a,0x60,0x0e = rev64 v13.4h, v21.4h 0x04,0x08,0xa0,0x0e = rev64 v4.2s, v0.2s 0xfe,0x0b,0x20,0x6e = rev32 v30.16b, v31.16b 0xe4,0x08,0x60,0x6e = rev32 v4.8h, v7.8h 0x35,0x08,0x20,0x2e = rev32 v21.8b, v1.8b 0x20,0x09,0x60,0x2e = rev32 v0.4h, v9.4h 0xfe,0x1b,0x20,0x4e = rev16 v30.16b, v31.16b 0x35,0x18,0x20,0x0e = rev16 v21.8b, v1.8b 0xa3,0x2a,0x20,0x4e = saddlp v3.8h, v21.16b 0xa8,0x28,0x20,0x0e = saddlp v8.4h, v5.8b 0x29,0x28,0x60,0x4e = saddlp v9.4s, v1.8h 0x20,0x28,0x60,0x0e = saddlp v0.2s, v1.4h 0x8c,0x28,0xa0,0x4e = saddlp v12.2d, v4.4s 0x91,0x2b,0xa0,0x0e = saddlp v17.1d, v28.2s 0xa3,0x2a,0x20,0x6e = uaddlp v3.8h, v21.16b 0xa8,0x28,0x20,0x2e = uaddlp v8.4h, v5.8b 0x29,0x28,0x60,0x6e = uaddlp v9.4s, v1.8h 0x20,0x28,0x60,0x2e = uaddlp v0.2s, v1.4h 0x8c,0x28,0xa0,0x6e = uaddlp v12.2d, v4.4s 0x91,0x2b,0xa0,0x2e = uaddlp v17.1d, v28.2s 0xa3,0x6a,0x20,0x4e = sadalp v3.8h, v21.16b 0xa8,0x68,0x20,0x0e = sadalp v8.4h, v5.8b 0x29,0x68,0x60,0x4e = sadalp v9.4s, v1.8h 0x20,0x68,0x60,0x0e = sadalp v0.2s, v1.4h 0x8c,0x68,0xa0,0x4e = sadalp v12.2d, v4.4s 0x91,0x6b,0xa0,0x0e = sadalp v17.1d, v28.2s 0xa3,0x6a,0x20,0x6e = uadalp v3.8h, v21.16b 0xa8,0x68,0x20,0x2e = uadalp v8.4h, v5.8b 0x29,0x68,0x60,0x6e = uadalp v9.4s, v1.8h 0x20,0x68,0x60,0x2e = uadalp v0.2s, v1.4h 0x8c,0x68,0xa0,0x6e = uadalp v12.2d, v4.4s 0x91,0x6b,0xa0,0x2e = uadalp v17.1d, v28.2s 0xe0,0x3b,0x20,0x4e = suqadd v0.16b, v31.16b 0x82,0x38,0x60,0x4e = suqadd v2.8h, v4.8h 0x06,0x39,0xa0,0x4e = suqadd v6.4s, v8.4s 0x06,0x39,0xe0,0x4e = suqadd v6.2d, v8.2d 0x21,0x39,0x20,0x0e = suqadd v1.8b, v9.8b 0xad,0x3a,0x60,0x0e = suqadd v13.4h, v21.4h 0x04,0x38,0xa0,0x0e = suqadd v4.2s, v0.2s 0xe0,0x3b,0x20,0x6e = usqadd v0.16b, v31.16b 0x82,0x38,0x60,0x6e = usqadd v2.8h, v4.8h 0x06,0x39,0xa0,0x6e = usqadd v6.4s, v8.4s 0x06,0x39,0xe0,0x6e = usqadd v6.2d, v8.2d 0x21,0x39,0x20,0x2e = usqadd v1.8b, v9.8b 0xad,0x3a,0x60,0x2e = usqadd v13.4h, v21.4h 0x04,0x38,0xa0,0x2e = usqadd v4.2s, v0.2s 0xe0,0x7b,0x20,0x4e = sqabs v0.16b, v31.16b 0x82,0x78,0x60,0x4e = sqabs v2.8h, v4.8h 0x06,0x79,0xa0,0x4e = sqabs v6.4s, v8.4s 0x06,0x79,0xe0,0x4e = sqabs v6.2d, v8.2d 0x21,0x79,0x20,0x0e = sqabs v1.8b, v9.8b 0xad,0x7a,0x60,0x0e = sqabs v13.4h, v21.4h 0x04,0x78,0xa0,0x0e = sqabs v4.2s, v0.2s 0xe0,0x7b,0x20,0x6e = sqneg v0.16b, v31.16b 0x82,0x78,0x60,0x6e = sqneg v2.8h, v4.8h 0x06,0x79,0xa0,0x6e = sqneg v6.4s, v8.4s 0x06,0x79,0xe0,0x6e = sqneg v6.2d, v8.2d 0x21,0x79,0x20,0x2e = sqneg v1.8b, v9.8b 0xad,0x7a,0x60,0x2e = sqneg v13.4h, v21.4h 0x04,0x78,0xa0,0x2e = sqneg v4.2s, v0.2s 0xe0,0xbb,0x20,0x4e = abs v0.16b, v31.16b 0x82,0xb8,0x60,0x4e = abs v2.8h, v4.8h 0x06,0xb9,0xa0,0x4e = abs v6.4s, v8.4s 0x06,0xb9,0xe0,0x4e = abs v6.2d, v8.2d 0x21,0xb9,0x20,0x0e = abs v1.8b, v9.8b 0xad,0xba,0x60,0x0e = abs v13.4h, v21.4h 0x04,0xb8,0xa0,0x0e = abs v4.2s, v0.2s 0xe0,0xbb,0x20,0x6e = neg v0.16b, v31.16b 0x82,0xb8,0x60,0x6e = neg v2.8h, v4.8h 0x06,0xb9,0xa0,0x6e = neg v6.4s, v8.4s 0x06,0xb9,0xe0,0x6e = neg v6.2d, v8.2d 0x21,0xb9,0x20,0x2e = neg v1.8b, v9.8b 0xad,0xba,0x60,0x2e = neg v13.4h, v21.4h 0x04,0xb8,0xa0,0x2e = neg v4.2s, v0.2s 0xe0,0x4b,0x20,0x4e = cls v0.16b, v31.16b 0x82,0x48,0x60,0x4e = cls v2.8h, v4.8h 0x06,0x49,0xa0,0x4e = cls v6.4s, v8.4s 0x21,0x49,0x20,0x0e = cls v1.8b, v9.8b 0xad,0x4a,0x60,0x0e = cls v13.4h, v21.4h 0x04,0x48,0xa0,0x0e = cls v4.2s, v0.2s 0xe0,0x4b,0x20,0x6e = clz v0.16b, v31.16b 0x82,0x48,0x60,0x6e = clz v2.8h, v4.8h 0x06,0x49,0xa0,0x6e = clz v6.4s, v8.4s 0x21,0x49,0x20,0x2e = clz v1.8b, v9.8b 0xad,0x4a,0x60,0x2e = clz v13.4h, v21.4h 0x04,0x48,0xa0,0x2e = clz v4.2s, v0.2s 0xe0,0x5b,0x20,0x4e = cnt v0.16b, v31.16b 0x21,0x59,0x20,0x0e = cnt v1.8b, v9.8b // 0xe0,0x5b,0x20,0x6e = not v0.16b, v31.16b // 0x21,0x59,0x20,0x2e = not v1.8b, v9.8b 0xe0,0x5b,0x60,0x6e = rbit v0.16b, v31.16b 0x21,0x59,0x60,0x2e = rbit v1.8b, v9.8b 0x06,0xf9,0xa0,0x4e = fabs v6.4s, v8.4s 0x06,0xf9,0xe0,0x4e = fabs v6.2d, v8.2d 0x04,0xf8,0xa0,0x0e = fabs v4.2s, v0.2s 0x06,0xf9,0xa0,0x6e = fneg v6.4s, v8.4s 0x06,0xf9,0xe0,0x6e = fneg v6.2d, v8.2d 0x04,0xf8,0xa0,0x2e = fneg v4.2s, v0.2s 0xe0,0x2b,0x21,0x4e = xtn2 v0.16b, v31.8h 0x82,0x28,0x61,0x4e = xtn2 v2.8h, v4.4s 0x06,0x29,0xa1,0x4e = xtn2 v6.4s, v8.2d 0x21,0x29,0x21,0x0e = xtn v1.8b, v9.8h 0xad,0x2a,0x61,0x0e = xtn v13.4h, v21.4s 0x04,0x28,0xa1,0x0e = xtn v4.2s, v0.2d 0xe0,0x2b,0x21,0x6e = sqxtun2 v0.16b, v31.8h 0x82,0x28,0x61,0x6e = sqxtun2 v2.8h, v4.4s 0x06,0x29,0xa1,0x6e = sqxtun2 v6.4s, v8.2d 0x21,0x29,0x21,0x2e = sqxtun v1.8b, v9.8h 0xad,0x2a,0x61,0x2e = sqxtun v13.4h, v21.4s 0x04,0x28,0xa1,0x2e = sqxtun v4.2s, v0.2d 0xe0,0x4b,0x21,0x4e = sqxtn2 v0.16b, v31.8h 0x82,0x48,0x61,0x4e = sqxtn2 v2.8h, v4.4s 0x06,0x49,0xa1,0x4e = sqxtn2 v6.4s, v8.2d 0x21,0x49,0x21,0x0e = sqxtn v1.8b, v9.8h 0xad,0x4a,0x61,0x0e = sqxtn v13.4h, v21.4s 0x04,0x48,0xa1,0x0e = sqxtn v4.2s, v0.2d 0xe0,0x4b,0x21,0x6e = uqxtn2 v0.16b, v31.8h 0x82,0x48,0x61,0x6e = uqxtn2 v2.8h, v4.4s 0x06,0x49,0xa1,0x6e = uqxtn2 v6.4s, v8.2d 0x21,0x49,0x21,0x2e = uqxtn v1.8b, v9.8h 0xad,0x4a,0x61,0x2e = uqxtn v13.4h, v21.4s 0x04,0x48,0xa1,0x2e = uqxtn v4.2s, v0.2d 0x82,0x38,0x21,0x6e = shll2 v2.8h, v4.16b, #8 0x06,0x39,0x61,0x6e = shll2 v6.4s, v8.8h, #16 0x06,0x39,0xa1,0x6e = shll2 v6.2d, v8.4s, #32 0x82,0x38,0x21,0x2e = shll v2.8h, v4.8b, #8 0x06,0x39,0x61,0x2e = shll v6.4s, v8.4h, #16 0x06,0x39,0xa1,0x2e = shll v6.2d, v8.2s, #32 0x82,0x68,0x21,0x4e = fcvtn2 v2.8h, v4.4s 0x06,0x69,0x61,0x4e = fcvtn2 v6.4s, v8.2d 0xad,0x6a,0x21,0x0e = fcvtn v13.4h, v21.4s 0x04,0x68,0x61,0x0e = fcvtn v4.2s, v0.2d 0x06,0x69,0x61,0x6e = fcvtxn2 v6.4s, v8.2d 0x04,0x68,0x61,0x2e = fcvtxn v4.2s, v0.2d 0x29,0x78,0x21,0x0e = fcvtl v9.4s, v1.4h 0x20,0x78,0x61,0x0e = fcvtl v0.2d, v1.2s 0x8c,0x78,0x21,0x4e = fcvtl2 v12.4s, v4.8h 0x91,0x7b,0x61,0x4e = fcvtl2 v17.2d, v28.4s 0x06,0x89,0x21,0x4e = frintn v6.4s, v8.4s 0x06,0x89,0x61,0x4e = frintn v6.2d, v8.2d 0x04,0x88,0x21,0x0e = frintn v4.2s, v0.2s 0x06,0x89,0x21,0x6e = frinta v6.4s, v8.4s 0x06,0x89,0x61,0x6e = frinta v6.2d, v8.2d 0x04,0x88,0x21,0x2e = frinta v4.2s, v0.2s 0x06,0x89,0xa1,0x4e = frintp v6.4s, v8.4s 0x06,0x89,0xe1,0x4e = frintp v6.2d, v8.2d 0x04,0x88,0xa1,0x0e = frintp v4.2s, v0.2s 0x06,0x99,0x21,0x4e = frintm v6.4s, v8.4s 0x06,0x99,0x61,0x4e = frintm v6.2d, v8.2d 0x04,0x98,0x21,0x0e = frintm v4.2s, v0.2s 0x06,0x99,0x21,0x6e = frintx v6.4s, v8.4s 0x06,0x99,0x61,0x6e = frintx v6.2d, v8.2d 0x04,0x98,0x21,0x2e = frintx v4.2s, v0.2s 0x06,0x99,0xa1,0x4e = frintz v6.4s, v8.4s 0x06,0x99,0xe1,0x4e = frintz v6.2d, v8.2d 0x04,0x98,0xa1,0x0e = frintz v4.2s, v0.2s 0x06,0x99,0xa1,0x6e = frinti v6.4s, v8.4s 0x06,0x99,0xe1,0x6e = frinti v6.2d, v8.2d 0x04,0x98,0xa1,0x2e = frinti v4.2s, v0.2s 0x06,0xa9,0x21,0x4e = fcvtns v6.4s, v8.4s 0x06,0xa9,0x61,0x4e = fcvtns v6.2d, v8.2d 0x04,0xa8,0x21,0x0e = fcvtns v4.2s, v0.2s 0x06,0xa9,0x21,0x6e = fcvtnu v6.4s, v8.4s 0x06,0xa9,0x61,0x6e = fcvtnu v6.2d, v8.2d 0x04,0xa8,0x21,0x2e = fcvtnu v4.2s, v0.2s 0x06,0xa9,0xa1,0x4e = fcvtps v6.4s, v8.4s 0x06,0xa9,0xe1,0x4e = fcvtps v6.2d, v8.2d 0x04,0xa8,0xa1,0x0e = fcvtps v4.2s, v0.2s 0x06,0xa9,0xa1,0x6e = fcvtpu v6.4s, v8.4s 0x06,0xa9,0xe1,0x6e = fcvtpu v6.2d, v8.2d 0x04,0xa8,0xa1,0x2e = fcvtpu v4.2s, v0.2s 0x06,0xb9,0x21,0x4e = fcvtms v6.4s, v8.4s 0x06,0xb9,0x61,0x4e = fcvtms v6.2d, v8.2d 0x04,0xb8,0x21,0x0e = fcvtms v4.2s, v0.2s 0x06,0xb9,0x21,0x6e = fcvtmu v6.4s, v8.4s 0x06,0xb9,0x61,0x6e = fcvtmu v6.2d, v8.2d 0x04,0xb8,0x21,0x2e = fcvtmu v4.2s, v0.2s 0x06,0xb9,0xa1,0x4e = fcvtzs v6.4s, v8.4s 0x06,0xb9,0xe1,0x4e = fcvtzs v6.2d, v8.2d 0x04,0xb8,0xa1,0x0e = fcvtzs v4.2s, v0.2s 0x06,0xb9,0xa1,0x6e = fcvtzu v6.4s, v8.4s 0x06,0xb9,0xe1,0x6e = fcvtzu v6.2d, v8.2d 0x04,0xb8,0xa1,0x2e = fcvtzu v4.2s, v0.2s 0x06,0xc9,0x21,0x4e = fcvtas v6.4s, v8.4s 0x06,0xc9,0x61,0x4e = fcvtas v6.2d, v8.2d 0x04,0xc8,0x21,0x0e = fcvtas v4.2s, v0.2s 0x06,0xc9,0x21,0x6e = fcvtau v6.4s, v8.4s 0x06,0xc9,0x61,0x6e = fcvtau v6.2d, v8.2d 0x04,0xc8,0x21,0x2e = fcvtau v4.2s, v0.2s 0x06,0xc9,0xa1,0x4e = urecpe v6.4s, v8.4s 0x04,0xc8,0xa1,0x0e = urecpe v4.2s, v0.2s 0x06,0xc9,0xa1,0x6e = ursqrte v6.4s, v8.4s 0x04,0xc8,0xa1,0x2e = ursqrte v4.2s, v0.2s 0x06,0xd9,0x21,0x4e = scvtf v6.4s, v8.4s 0x06,0xd9,0x61,0x4e = scvtf v6.2d, v8.2d 0x04,0xd8,0x21,0x0e = scvtf v4.2s, v0.2s 0x06,0xd9,0x21,0x6e = ucvtf v6.4s, v8.4s 0x06,0xd9,0x61,0x6e = ucvtf v6.2d, v8.2d 0x04,0xd8,0x21,0x2e = ucvtf v4.2s, v0.2s 0x06,0xd9,0xa1,0x4e = frecpe v6.4s, v8.4s 0x06,0xd9,0xe1,0x4e = frecpe v6.2d, v8.2d 0x04,0xd8,0xa1,0x0e = frecpe v4.2s, v0.2s 0x06,0xd9,0xa1,0x6e = frsqrte v6.4s, v8.4s 0x06,0xd9,0xe1,0x6e = frsqrte v6.2d, v8.2d 0x04,0xd8,0xa1,0x2e = frsqrte v4.2s, v0.2s 0x06,0xf9,0xa1,0x6e = fsqrt v6.4s, v8.4s 0x06,0xf9,0xe1,0x6e = fsqrt v6.2d, v8.2d 0x04,0xf8,0xa1,0x2e = fsqrt v4.2s, v0.2s capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs000064400000000000000000000140250072674642500254450ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x00,0x70,0xc1,0x4c = ld1 {v0.16b}, [x0], x1 0xef,0x75,0xc2,0x4c = ld1 {v15.8h}, [x15], x2 0xff,0x7b,0xdf,0x4c = ld1 {v31.4s}, [sp], #16 0x00,0x7c,0xdf,0x4c = ld1 {v0.2d}, [x0], #16 0x00,0x70,0xc2,0x0c = ld1 {v0.8b}, [x0], x2 0xef,0x75,0xc3,0x0c = ld1 {v15.4h}, [x15], x3 0xff,0x7b,0xdf,0x0c = ld1 {v31.2s}, [sp], #8 0x00,0x7c,0xdf,0x0c = ld1 {v0.1d}, [x0], #8 0x00,0xa0,0xc1,0x4c = ld1 {v0.16b, v1.16b}, [x0], x1 0xef,0xa5,0xc2,0x4c = ld1 {v15.8h, v16.8h}, [x15], x2 0xff,0xab,0xdf,0x4c = ld1 {v31.4s, v0.4s}, [sp], #32 0x00,0xac,0xdf,0x4c = ld1 {v0.2d, v1.2d}, [x0], #32 0x00,0xa0,0xc2,0x0c = ld1 {v0.8b, v1.8b}, [x0], x2 0xef,0xa5,0xc3,0x0c = ld1 {v15.4h, v16.4h}, [x15], x3 0xff,0xab,0xdf,0x0c = ld1 {v31.2s, v0.2s}, [sp], #16 0x00,0xac,0xdf,0x0c = ld1 {v0.1d, v1.1d}, [x0], #16 0x00,0x60,0xc1,0x4c = ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 0xef,0x65,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 0xff,0x6b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 0x00,0x6c,0xdf,0x4c = ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 0x00,0x60,0xc2,0x0c = ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 0xef,0x65,0xc3,0x0c = ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 0xff,0x6b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 0x00,0x6c,0xdf,0x0c = ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 0x00,0x20,0xc1,0x4c = ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 0xef,0x25,0xc2,0x4c = ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 0xff,0x2b,0xdf,0x4c = ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 0x00,0x2c,0xdf,0x4c = ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 0x00,0x20,0xc3,0x0c = ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 0xef,0x25,0xc4,0x0c = ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 0xff,0x2b,0xdf,0x0c = ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 0x00,0x2c,0xdf,0x0c = ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 0x00,0x80,0xc1,0x4c = ld2 {v0.16b, v1.16b}, [x0], x1 0xef,0x85,0xc2,0x4c = ld2 {v15.8h, v16.8h}, [x15], x2 0xff,0x8b,0xdf,0x4c = ld2 {v31.4s, v0.4s}, [sp], #32 0x00,0x8c,0xdf,0x4c = ld2 {v0.2d, v1.2d}, [x0], #32 0x00,0x80,0xc2,0x0c = ld2 {v0.8b, v1.8b}, [x0], x2 0xef,0x85,0xc3,0x0c = ld2 {v15.4h, v16.4h}, [x15], x3 0xff,0x8b,0xdf,0x0c = ld2 {v31.2s, v0.2s}, [sp], #16 0x00,0x40,0xc1,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 0xef,0x45,0xc2,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 0xff,0x4b,0xdf,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 0x00,0x4c,0xdf,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 0x00,0x40,0xc2,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 0xef,0x45,0xc3,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 0xff,0x4b,0xdf,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 0x00,0x00,0xc1,0x4c = ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 0xef,0x05,0xc2,0x4c = ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 0xff,0x0b,0xdf,0x4c = ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 0x00,0x0c,0xdf,0x4c = ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 0x00,0x00,0xc3,0x0c = ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 0xef,0x05,0xc4,0x0c = ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 0xff,0x0b,0xdf,0x0c = ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 0x00,0x70,0x81,0x4c = st1 {v0.16b}, [x0], x1 0xef,0x75,0x82,0x4c = st1 {v15.8h}, [x15], x2 0xff,0x7b,0x9f,0x4c = st1 {v31.4s}, [sp], #16 0x00,0x7c,0x9f,0x4c = st1 {v0.2d}, [x0], #16 0x00,0x70,0x82,0x0c = st1 {v0.8b}, [x0], x2 0xef,0x75,0x83,0x0c = st1 {v15.4h}, [x15], x3 0xff,0x7b,0x9f,0x0c = st1 {v31.2s}, [sp], #8 0x00,0x7c,0x9f,0x0c = st1 {v0.1d}, [x0], #8 0x00,0xa0,0x81,0x4c = st1 {v0.16b, v1.16b}, [x0], x1 0xef,0xa5,0x82,0x4c = st1 {v15.8h, v16.8h}, [x15], x2 0xff,0xab,0x9f,0x4c = st1 {v31.4s, v0.4s}, [sp], #32 0x00,0xac,0x9f,0x4c = st1 {v0.2d, v1.2d}, [x0], #32 0x00,0xa0,0x82,0x0c = st1 {v0.8b, v1.8b}, [x0], x2 0xef,0xa5,0x83,0x0c = st1 {v15.4h, v16.4h}, [x15], x3 0xff,0xab,0x9f,0x0c = st1 {v31.2s, v0.2s}, [sp], #16 0x00,0xac,0x9f,0x0c = st1 {v0.1d, v1.1d}, [x0], #16 0x00,0x60,0x81,0x4c = st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 0xef,0x65,0x82,0x4c = st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 0xff,0x6b,0x9f,0x4c = st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 0x00,0x6c,0x9f,0x4c = st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 0x00,0x60,0x82,0x0c = st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 0xef,0x65,0x83,0x0c = st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 0xff,0x6b,0x9f,0x0c = st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 0x00,0x6c,0x9f,0x0c = st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 0x00,0x20,0x81,0x4c = st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 0xef,0x25,0x82,0x4c = st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 0xff,0x2b,0x9f,0x4c = st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 0x00,0x2c,0x9f,0x4c = st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 0x00,0x20,0x83,0x0c = st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 0xef,0x25,0x84,0x0c = st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 0xff,0x2b,0x9f,0x0c = st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 0x00,0x2c,0x9f,0x0c = st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 0x00,0x80,0x81,0x4c = st2 {v0.16b, v1.16b}, [x0], x1 0xef,0x85,0x82,0x4c = st2 {v15.8h, v16.8h}, [x15], x2 0xff,0x8b,0x9f,0x4c = st2 {v31.4s, v0.4s}, [sp], #32 0x00,0x8c,0x9f,0x4c = st2 {v0.2d, v1.2d}, [x0], #32 0x00,0x80,0x82,0x0c = st2 {v0.8b, v1.8b}, [x0], x2 0xef,0x85,0x83,0x0c = st2 {v15.4h, v16.4h}, [x15], x3 0xff,0x8b,0x9f,0x0c = st2 {v31.2s, v0.2s}, [sp], #16 0x00,0x40,0x81,0x4c = st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 0xef,0x45,0x82,0x4c = st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 0xff,0x4b,0x9f,0x4c = st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 0x00,0x4c,0x9f,0x4c = st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 0x00,0x40,0x82,0x0c = st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 0xef,0x45,0x83,0x0c = st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 0xff,0x4b,0x9f,0x0c = st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 0x00,0x00,0x81,0x4c = st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 0xef,0x05,0x82,0x4c = st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 0xff,0x0b,0x9f,0x4c = st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 0x00,0x0c,0x9f,0x4c = st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 0x00,0x00,0x83,0x0c = st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 0xef,0x05,0x84,0x0c = st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 0xff,0x0b,0x9f,0x0c = st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-simd-shift.s.cs000064400000000000000000000153040072674642500225620ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x04,0x0d,0x0f = sshr v0.8b, v1.8b, #3 0x20,0x04,0x1d,0x0f = sshr v0.4h, v1.4h, #3 0x20,0x04,0x3d,0x0f = sshr v0.2s, v1.2s, #3 0x20,0x04,0x0d,0x4f = sshr v0.16b, v1.16b, #3 0x20,0x04,0x1d,0x4f = sshr v0.8h, v1.8h, #3 0x20,0x04,0x3d,0x4f = sshr v0.4s, v1.4s, #3 0x20,0x04,0x7d,0x4f = sshr v0.2d, v1.2d, #3 0x20,0x04,0x0d,0x2f = ushr v0.8b, v1.8b, #3 0x20,0x04,0x1d,0x2f = ushr v0.4h, v1.4h, #3 0x20,0x04,0x3d,0x2f = ushr v0.2s, v1.2s, #3 0x20,0x04,0x0d,0x6f = ushr v0.16b, v1.16b, #3 0x20,0x04,0x1d,0x6f = ushr v0.8h, v1.8h, #3 0x20,0x04,0x3d,0x6f = ushr v0.4s, v1.4s, #3 0x20,0x04,0x7d,0x6f = ushr v0.2d, v1.2d, #3 0x20,0x14,0x0d,0x0f = ssra v0.8b, v1.8b, #3 0x20,0x14,0x1d,0x0f = ssra v0.4h, v1.4h, #3 0x20,0x14,0x3d,0x0f = ssra v0.2s, v1.2s, #3 0x20,0x14,0x0d,0x4f = ssra v0.16b, v1.16b, #3 0x20,0x14,0x1d,0x4f = ssra v0.8h, v1.8h, #3 0x20,0x14,0x3d,0x4f = ssra v0.4s, v1.4s, #3 0x20,0x14,0x7d,0x4f = ssra v0.2d, v1.2d, #3 0x20,0x14,0x0d,0x2f = usra v0.8b, v1.8b, #3 0x20,0x14,0x1d,0x2f = usra v0.4h, v1.4h, #3 0x20,0x14,0x3d,0x2f = usra v0.2s, v1.2s, #3 0x20,0x14,0x0d,0x6f = usra v0.16b, v1.16b, #3 0x20,0x14,0x1d,0x6f = usra v0.8h, v1.8h, #3 0x20,0x14,0x3d,0x6f = usra v0.4s, v1.4s, #3 0x20,0x14,0x7d,0x6f = usra v0.2d, v1.2d, #3 0x20,0x24,0x0d,0x0f = srshr v0.8b, v1.8b, #3 0x20,0x24,0x1d,0x0f = srshr v0.4h, v1.4h, #3 0x20,0x24,0x3d,0x0f = srshr v0.2s, v1.2s, #3 0x20,0x24,0x0d,0x4f = srshr v0.16b, v1.16b, #3 0x20,0x24,0x1d,0x4f = srshr v0.8h, v1.8h, #3 0x20,0x24,0x3d,0x4f = srshr v0.4s, v1.4s, #3 0x20,0x24,0x7d,0x4f = srshr v0.2d, v1.2d, #3 0x20,0x24,0x0d,0x2f = urshr v0.8b, v1.8b, #3 0x20,0x24,0x1d,0x2f = urshr v0.4h, v1.4h, #3 0x20,0x24,0x3d,0x2f = urshr v0.2s, v1.2s, #3 0x20,0x24,0x0d,0x6f = urshr v0.16b, v1.16b, #3 0x20,0x24,0x1d,0x6f = urshr v0.8h, v1.8h, #3 0x20,0x24,0x3d,0x6f = urshr v0.4s, v1.4s, #3 0x20,0x24,0x7d,0x6f = urshr v0.2d, v1.2d, #3 0x20,0x34,0x0d,0x0f = srsra v0.8b, v1.8b, #3 0x20,0x34,0x1d,0x0f = srsra v0.4h, v1.4h, #3 0x20,0x34,0x3d,0x0f = srsra v0.2s, v1.2s, #3 0x20,0x34,0x0d,0x4f = srsra v0.16b, v1.16b, #3 0x20,0x34,0x1d,0x4f = srsra v0.8h, v1.8h, #3 0x20,0x34,0x3d,0x4f = srsra v0.4s, v1.4s, #3 0x20,0x34,0x7d,0x4f = srsra v0.2d, v1.2d, #3 0x20,0x34,0x0d,0x2f = ursra v0.8b, v1.8b, #3 0x20,0x34,0x1d,0x2f = ursra v0.4h, v1.4h, #3 0x20,0x34,0x3d,0x2f = ursra v0.2s, v1.2s, #3 0x20,0x34,0x0d,0x6f = ursra v0.16b, v1.16b, #3 0x20,0x34,0x1d,0x6f = ursra v0.8h, v1.8h, #3 0x20,0x34,0x3d,0x6f = ursra v0.4s, v1.4s, #3 0x20,0x34,0x7d,0x6f = ursra v0.2d, v1.2d, #3 0x20,0x44,0x0d,0x2f = sri v0.8b, v1.8b, #3 0x20,0x44,0x1d,0x2f = sri v0.4h, v1.4h, #3 0x20,0x44,0x3d,0x2f = sri v0.2s, v1.2s, #3 0x20,0x44,0x0d,0x6f = sri v0.16b, v1.16b, #3 0x20,0x44,0x1d,0x6f = sri v0.8h, v1.8h, #3 0x20,0x44,0x3d,0x6f = sri v0.4s, v1.4s, #3 0x20,0x54,0x0b,0x2f = sli v0.8b, v1.8b, #3 0x20,0x54,0x13,0x2f = sli v0.4h, v1.4h, #3 0x20,0x54,0x23,0x2f = sli v0.2s, v1.2s, #3 0x20,0x54,0x0b,0x6f = sli v0.16b, v1.16b, #3 0x20,0x54,0x13,0x6f = sli v0.8h, v1.8h, #3 0x20,0x54,0x23,0x6f = sli v0.4s, v1.4s, #3 0x20,0x54,0x43,0x6f = sli v0.2d, v1.2d, #3 0x20,0x64,0x0b,0x2f = sqshlu v0.8b, v1.8b, #3 0x20,0x64,0x13,0x2f = sqshlu v0.4h, v1.4h, #3 0x20,0x64,0x23,0x2f = sqshlu v0.2s, v1.2s, #3 0x20,0x64,0x0b,0x6f = sqshlu v0.16b, v1.16b, #3 0x20,0x64,0x13,0x6f = sqshlu v0.8h, v1.8h, #3 0x20,0x64,0x23,0x6f = sqshlu v0.4s, v1.4s, #3 0x20,0x64,0x43,0x6f = sqshlu v0.2d, v1.2d, #3 0x20,0x74,0x0b,0x0f = sqshl v0.8b, v1.8b, #3 0x20,0x74,0x13,0x0f = sqshl v0.4h, v1.4h, #3 0x20,0x74,0x23,0x0f = sqshl v0.2s, v1.2s, #3 0x20,0x74,0x0b,0x4f = sqshl v0.16b, v1.16b, #3 0x20,0x74,0x13,0x4f = sqshl v0.8h, v1.8h, #3 0x20,0x74,0x23,0x4f = sqshl v0.4s, v1.4s, #3 0x20,0x74,0x43,0x4f = sqshl v0.2d, v1.2d, #3 0x20,0x74,0x0b,0x2f = uqshl v0.8b, v1.8b, #3 0x20,0x74,0x13,0x2f = uqshl v0.4h, v1.4h, #3 0x20,0x74,0x23,0x2f = uqshl v0.2s, v1.2s, #3 0x20,0x74,0x0b,0x6f = uqshl v0.16b, v1.16b, #3 0x20,0x74,0x13,0x6f = uqshl v0.8h, v1.8h, #3 0x20,0x74,0x23,0x6f = uqshl v0.4s, v1.4s, #3 0x20,0x74,0x43,0x6f = uqshl v0.2d, v1.2d, #3 0x20,0x84,0x0d,0x0f = shrn v0.8b, v1.8h, #3 0x20,0x84,0x1d,0x0f = shrn v0.4h, v1.4s, #3 0x20,0x84,0x3d,0x0f = shrn v0.2s, v1.2d, #3 0x20,0x84,0x0d,0x4f = shrn2 v0.16b, v1.8h, #3 0x20,0x84,0x1d,0x4f = shrn2 v0.8h, v1.4s, #3 0x20,0x84,0x3d,0x4f = shrn2 v0.4s, v1.2d, #3 0x20,0x84,0x0d,0x2f = sqshrun v0.8b, v1.8h, #3 0x20,0x84,0x1d,0x2f = sqshrun v0.4h, v1.4s, #3 0x20,0x84,0x3d,0x2f = sqshrun v0.2s, v1.2d, #3 0x20,0x84,0x0d,0x6f = sqshrun2 v0.16b, v1.8h, #3 0x20,0x84,0x1d,0x6f = sqshrun2 v0.8h, v1.4s, #3 0x20,0x84,0x3d,0x6f = sqshrun2 v0.4s, v1.2d, #3 0x20,0x8c,0x0d,0x0f = rshrn v0.8b, v1.8h, #3 0x20,0x8c,0x1d,0x0f = rshrn v0.4h, v1.4s, #3 0x20,0x8c,0x3d,0x0f = rshrn v0.2s, v1.2d, #3 0x20,0x8c,0x0d,0x4f = rshrn2 v0.16b, v1.8h, #3 0x20,0x8c,0x1d,0x4f = rshrn2 v0.8h, v1.4s, #3 0x20,0x8c,0x3d,0x4f = rshrn2 v0.4s, v1.2d, #3 0x20,0x8c,0x0d,0x2f = sqrshrun v0.8b, v1.8h, #3 0x20,0x8c,0x1d,0x2f = sqrshrun v0.4h, v1.4s, #3 0x20,0x8c,0x3d,0x2f = sqrshrun v0.2s, v1.2d, #3 0x20,0x8c,0x0d,0x6f = sqrshrun2 v0.16b, v1.8h, #3 0x20,0x8c,0x1d,0x6f = sqrshrun2 v0.8h, v1.4s, #3 0x20,0x8c,0x3d,0x6f = sqrshrun2 v0.4s, v1.2d, #3 0x20,0x94,0x0d,0x0f = sqshrn v0.8b, v1.8h, #3 0x20,0x94,0x1d,0x0f = sqshrn v0.4h, v1.4s, #3 0x20,0x94,0x3d,0x0f = sqshrn v0.2s, v1.2d, #3 0x20,0x94,0x0d,0x4f = sqshrn2 v0.16b, v1.8h, #3 0x20,0x94,0x1d,0x4f = sqshrn2 v0.8h, v1.4s, #3 0x20,0x94,0x3d,0x4f = sqshrn2 v0.4s, v1.2d, #3 0x20,0x94,0x0d,0x2f = uqshrn v0.8b, v1.8h, #3 0x20,0x94,0x1d,0x2f = uqshrn v0.4h, v1.4s, #3 0x20,0x94,0x3d,0x2f = uqshrn v0.2s, v1.2d, #3 0x20,0x94,0x0d,0x6f = uqshrn2 v0.16b, v1.8h, #3 0x20,0x94,0x1d,0x6f = uqshrn2 v0.8h, v1.4s, #3 0x20,0x94,0x3d,0x6f = uqshrn2 v0.4s, v1.2d, #3 0x20,0x9c,0x0d,0x0f = sqrshrn v0.8b, v1.8h, #3 0x20,0x9c,0x1d,0x0f = sqrshrn v0.4h, v1.4s, #3 0x20,0x9c,0x3d,0x0f = sqrshrn v0.2s, v1.2d, #3 0x20,0x9c,0x0d,0x4f = sqrshrn2 v0.16b, v1.8h, #3 0x20,0x9c,0x1d,0x4f = sqrshrn2 v0.8h, v1.4s, #3 0x20,0x9c,0x3d,0x4f = sqrshrn2 v0.4s, v1.2d, #3 0x20,0x9c,0x0d,0x2f = uqrshrn v0.8b, v1.8h, #3 0x20,0x9c,0x1d,0x2f = uqrshrn v0.4h, v1.4s, #3 0x20,0x9c,0x3d,0x2f = uqrshrn v0.2s, v1.2d, #3 0x20,0x9c,0x0d,0x6f = uqrshrn2 v0.16b, v1.8h, #3 0x20,0x9c,0x1d,0x6f = uqrshrn2 v0.8h, v1.4s, #3 0x20,0x9c,0x3d,0x6f = uqrshrn2 v0.4s, v1.2d, #3 0x20,0xe4,0x3d,0x0f = scvtf v0.2s, v1.2s, #3 0x20,0xe4,0x3d,0x4f = scvtf v0.4s, v1.4s, #3 0x20,0xe4,0x7d,0x4f = scvtf v0.2d, v1.2d, #3 0x20,0xe4,0x3d,0x2f = ucvtf v0.2s, v1.2s, #3 0x20,0xe4,0x3d,0x6f = ucvtf v0.4s, v1.4s, #3 0x20,0xe4,0x7d,0x6f = ucvtf v0.2d, v1.2d, #3 0x20,0xfc,0x3d,0x0f = fcvtzs v0.2s, v1.2s, #3 0x20,0xfc,0x3d,0x4f = fcvtzs v0.4s, v1.4s, #3 0x20,0xfc,0x7d,0x4f = fcvtzs v0.2d, v1.2d, #3 0x20,0xfc,0x3d,0x2f = fcvtzu v0.2s, v1.2s, #3 0x20,0xfc,0x3d,0x6f = fcvtzu v0.4s, v1.4s, #3 0x20,0xfc,0x7d,0x6f = fcvtzu v0.2d, v1.2d, #3 capstone-sys-0.15.0/capstone/suite/MC/AArch64/neon-tbl.s.cs000064400000000000000000000024470072674642500213000ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x20,0x00,0x02,0x0e = tbl v0.8b, {v1.16b}, v2.8b 0x20,0x20,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b}, v2.8b 0x20,0x40,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b 0x20,0x60,0x02,0x0e = tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b 0xe0,0x63,0x02,0x0e = tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b 0x20,0x00,0x02,0x4e = tbl v0.16b, {v1.16b}, v2.16b 0x20,0x20,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b}, v2.16b 0x20,0x40,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b 0x20,0x60,0x02,0x4e = tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b 0xc0,0x63,0x02,0x4e = tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b 0x20,0x10,0x02,0x0e = tbx v0.8b, {v1.16b}, v2.8b 0x20,0x30,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b}, v2.8b 0x20,0x50,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b 0x20,0x70,0x02,0x0e = tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b 0xe0,0x73,0x02,0x0e = tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b 0x20,0x10,0x02,0x4e = tbx v0.16b, {v1.16b}, v2.16b 0x20,0x30,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b}, v2.16b 0x20,0x50,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b 0x20,0x70,0x02,0x4e = tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b 0xc0,0x73,0x02,0x4e = tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b capstone-sys-0.15.0/capstone/suite/MC/AArch64/trace-regs.s.cs000064400000000000000000000367460072674642500216270ustar 00000000000000# CS_ARCH_ARM64, 0, None 0x08,0x03,0x31,0xd5 = mrs x8, trcstatr 0xc9,0x00,0x31,0xd5 = mrs x9, trcidr8 0xcb,0x01,0x31,0xd5 = mrs x11, trcidr9 0xd9,0x02,0x31,0xd5 = mrs x25, trcidr10 0xc7,0x03,0x31,0xd5 = mrs x7, trcidr11 0xc7,0x04,0x31,0xd5 = mrs x7, trcidr12 0xc6,0x05,0x31,0xd5 = mrs x6, trcidr13 0xfb,0x08,0x31,0xd5 = mrs x27, trcidr0 0xfd,0x09,0x31,0xd5 = mrs x29, trcidr1 0xe4,0x0a,0x31,0xd5 = mrs x4, trcidr2 0xe8,0x0b,0x31,0xd5 = mrs x8, trcidr3 0xef,0x0c,0x31,0xd5 = mrs x15, trcidr4 0xf4,0x0d,0x31,0xd5 = mrs x20, trcidr5 0xe6,0x0e,0x31,0xd5 = mrs x6, trcidr6 0xe6,0x0f,0x31,0xd5 = mrs x6, trcidr7 0x98,0x11,0x31,0xd5 = mrs x24, trcoslsr 0x92,0x15,0x31,0xd5 = mrs x18, trcpdsr 0xdc,0x7a,0x31,0xd5 = mrs x28, trcdevaff0 0xc5,0x7b,0x31,0xd5 = mrs x5, trcdevaff1 0xc5,0x7d,0x31,0xd5 = mrs x5, trclsr 0xcb,0x7e,0x31,0xd5 = mrs x11, trcauthstatus 0xcd,0x7f,0x31,0xd5 = mrs x13, trcdevarch 0xf2,0x72,0x31,0xd5 = mrs x18, trcdevid 0xf6,0x73,0x31,0xd5 = mrs x22, trcdevtype 0xee,0x74,0x31,0xd5 = mrs x14, trcpidr4 0xe5,0x75,0x31,0xd5 = mrs x5, trcpidr5 0xe5,0x76,0x31,0xd5 = mrs x5, trcpidr6 0xe9,0x77,0x31,0xd5 = mrs x9, trcpidr7 0xef,0x78,0x31,0xd5 = mrs x15, trcpidr0 0xe6,0x79,0x31,0xd5 = mrs x6, trcpidr1 0xeb,0x7a,0x31,0xd5 = mrs x11, trcpidr2 0xf4,0x7b,0x31,0xd5 = mrs x20, trcpidr3 0xf1,0x7c,0x31,0xd5 = mrs x17, trccidr0 0xe2,0x7d,0x31,0xd5 = mrs x2, trccidr1 0xf4,0x7e,0x31,0xd5 = mrs x20, trccidr2 0xe4,0x7f,0x31,0xd5 = mrs x4, trccidr3 0x0b,0x01,0x31,0xd5 = mrs x11, trcprgctlr 0x17,0x02,0x31,0xd5 = mrs x23, trcprocselr 0x0d,0x04,0x31,0xd5 = mrs x13, trcconfigr 0x17,0x06,0x31,0xd5 = mrs x23, trcauxctlr 0x09,0x08,0x31,0xd5 = mrs x9, trceventctl0r 0x10,0x09,0x31,0xd5 = mrs x16, trceventctl1r 0x04,0x0b,0x31,0xd5 = mrs x4, trcstallctlr 0x0e,0x0c,0x31,0xd5 = mrs x14, trctsctlr 0x18,0x0d,0x31,0xd5 = mrs x24, trcsyncpr 0x1c,0x0e,0x31,0xd5 = mrs x28, trcccctlr 0x0f,0x0f,0x31,0xd5 = mrs x15, trcbbctlr 0x21,0x00,0x31,0xd5 = mrs x1, trctraceidr 0x34,0x01,0x31,0xd5 = mrs x20, trcqctlr 0x42,0x00,0x31,0xd5 = mrs x2, trcvictlr 0x4c,0x01,0x31,0xd5 = mrs x12, trcviiectlr 0x50,0x02,0x31,0xd5 = mrs x16, trcvissctlr 0x48,0x03,0x31,0xd5 = mrs x8, trcvipcssctlr 0x5b,0x08,0x31,0xd5 = mrs x27, trcvdctlr 0x49,0x09,0x31,0xd5 = mrs x9, trcvdsacctlr 0x40,0x0a,0x31,0xd5 = mrs x0, trcvdarcctlr 0x8d,0x00,0x31,0xd5 = mrs x13, trcseqevr0 0x8b,0x01,0x31,0xd5 = mrs x11, trcseqevr1 0x9a,0x02,0x31,0xd5 = mrs x26, trcseqevr2 0x8e,0x06,0x31,0xd5 = mrs x14, trcseqrstevr 0x84,0x07,0x31,0xd5 = mrs x4, trcseqstr 0x91,0x08,0x31,0xd5 = mrs x17, trcextinselr 0xb5,0x00,0x31,0xd5 = mrs x21, trccntrldvr0 0xaa,0x01,0x31,0xd5 = mrs x10, trccntrldvr1 0xb4,0x02,0x31,0xd5 = mrs x20, trccntrldvr2 0xa5,0x03,0x31,0xd5 = mrs x5, trccntrldvr3 0xb1,0x04,0x31,0xd5 = mrs x17, trccntctlr0 0xa1,0x05,0x31,0xd5 = mrs x1, trccntctlr1 0xb1,0x06,0x31,0xd5 = mrs x17, trccntctlr2 0xa6,0x07,0x31,0xd5 = mrs x6, trccntctlr3 0xbc,0x08,0x31,0xd5 = mrs x28, trccntvr0 0xb7,0x09,0x31,0xd5 = mrs x23, trccntvr1 0xa9,0x0a,0x31,0xd5 = mrs x9, trccntvr2 0xa6,0x0b,0x31,0xd5 = mrs x6, trccntvr3 0xf8,0x00,0x31,0xd5 = mrs x24, trcimspec0 0xf8,0x01,0x31,0xd5 = mrs x24, trcimspec1 0xef,0x02,0x31,0xd5 = mrs x15, trcimspec2 0xea,0x03,0x31,0xd5 = mrs x10, trcimspec3 0xfd,0x04,0x31,0xd5 = mrs x29, trcimspec4 0xf2,0x05,0x31,0xd5 = mrs x18, trcimspec5 0xfd,0x06,0x31,0xd5 = mrs x29, trcimspec6 0xe2,0x07,0x31,0xd5 = mrs x2, trcimspec7 0x08,0x12,0x31,0xd5 = mrs x8, trcrsctlr2 0x00,0x13,0x31,0xd5 = mrs x0, trcrsctlr3 0x0c,0x14,0x31,0xd5 = mrs x12, trcrsctlr4 0x1a,0x15,0x31,0xd5 = mrs x26, trcrsctlr5 0x1d,0x16,0x31,0xd5 = mrs x29, trcrsctlr6 0x11,0x17,0x31,0xd5 = mrs x17, trcrsctlr7 0x00,0x18,0x31,0xd5 = mrs x0, trcrsctlr8 0x01,0x19,0x31,0xd5 = mrs x1, trcrsctlr9 0x11,0x1a,0x31,0xd5 = mrs x17, trcrsctlr10 0x15,0x1b,0x31,0xd5 = mrs x21, trcrsctlr11 0x01,0x1c,0x31,0xd5 = mrs x1, trcrsctlr12 0x08,0x1d,0x31,0xd5 = mrs x8, trcrsctlr13 0x18,0x1e,0x31,0xd5 = mrs x24, trcrsctlr14 0x00,0x1f,0x31,0xd5 = mrs x0, trcrsctlr15 0x22,0x10,0x31,0xd5 = mrs x2, trcrsctlr16 0x3d,0x11,0x31,0xd5 = mrs x29, trcrsctlr17 0x36,0x12,0x31,0xd5 = mrs x22, trcrsctlr18 0x26,0x13,0x31,0xd5 = mrs x6, trcrsctlr19 0x3a,0x14,0x31,0xd5 = mrs x26, trcrsctlr20 0x3a,0x15,0x31,0xd5 = mrs x26, trcrsctlr21 0x24,0x16,0x31,0xd5 = mrs x4, trcrsctlr22 0x2c,0x17,0x31,0xd5 = mrs x12, trcrsctlr23 0x21,0x18,0x31,0xd5 = mrs x1, trcrsctlr24 0x20,0x19,0x31,0xd5 = mrs x0, trcrsctlr25 0x31,0x1a,0x31,0xd5 = mrs x17, trcrsctlr26 0x28,0x1b,0x31,0xd5 = mrs x8, trcrsctlr27 0x2a,0x1c,0x31,0xd5 = mrs x10, trcrsctlr28 0x39,0x1d,0x31,0xd5 = mrs x25, trcrsctlr29 0x2c,0x1e,0x31,0xd5 = mrs x12, trcrsctlr30 0x2b,0x1f,0x31,0xd5 = mrs x11, trcrsctlr31 0x52,0x10,0x31,0xd5 = mrs x18, trcssccr0 0x4c,0x11,0x31,0xd5 = mrs x12, trcssccr1 0x43,0x12,0x31,0xd5 = mrs x3, trcssccr2 0x42,0x13,0x31,0xd5 = mrs x2, trcssccr3 0x55,0x14,0x31,0xd5 = mrs x21, trcssccr4 0x4a,0x15,0x31,0xd5 = mrs x10, trcssccr5 0x56,0x16,0x31,0xd5 = mrs x22, trcssccr6 0x57,0x17,0x31,0xd5 = mrs x23, trcssccr7 0x57,0x18,0x31,0xd5 = mrs x23, trcsscsr0 0x53,0x19,0x31,0xd5 = mrs x19, trcsscsr1 0x59,0x1a,0x31,0xd5 = mrs x25, trcsscsr2 0x51,0x1b,0x31,0xd5 = mrs x17, trcsscsr3 0x53,0x1c,0x31,0xd5 = mrs x19, trcsscsr4 0x4b,0x1d,0x31,0xd5 = mrs x11, trcsscsr5 0x45,0x1e,0x31,0xd5 = mrs x5, trcsscsr6 0x49,0x1f,0x31,0xd5 = mrs x9, trcsscsr7 0x61,0x10,0x31,0xd5 = mrs x1, trcsspcicr0 0x6c,0x11,0x31,0xd5 = mrs x12, trcsspcicr1 0x75,0x12,0x31,0xd5 = mrs x21, trcsspcicr2 0x6b,0x13,0x31,0xd5 = mrs x11, trcsspcicr3 0x63,0x14,0x31,0xd5 = mrs x3, trcsspcicr4 0x69,0x15,0x31,0xd5 = mrs x9, trcsspcicr5 0x65,0x16,0x31,0xd5 = mrs x5, trcsspcicr6 0x62,0x17,0x31,0xd5 = mrs x2, trcsspcicr7 0x9a,0x14,0x31,0xd5 = mrs x26, trcpdcr 0x08,0x20,0x31,0xd5 = mrs x8, trcacvr0 0x0f,0x22,0x31,0xd5 = mrs x15, trcacvr1 0x13,0x24,0x31,0xd5 = mrs x19, trcacvr2 0x08,0x26,0x31,0xd5 = mrs x8, trcacvr3 0x1c,0x28,0x31,0xd5 = mrs x28, trcacvr4 0x03,0x2a,0x31,0xd5 = mrs x3, trcacvr5 0x19,0x2c,0x31,0xd5 = mrs x25, trcacvr6 0x18,0x2e,0x31,0xd5 = mrs x24, trcacvr7 0x26,0x20,0x31,0xd5 = mrs x6, trcacvr8 0x23,0x22,0x31,0xd5 = mrs x3, trcacvr9 0x38,0x24,0x31,0xd5 = mrs x24, trcacvr10 0x23,0x26,0x31,0xd5 = mrs x3, trcacvr11 0x2c,0x28,0x31,0xd5 = mrs x12, trcacvr12 0x29,0x2a,0x31,0xd5 = mrs x9, trcacvr13 0x2e,0x2c,0x31,0xd5 = mrs x14, trcacvr14 0x23,0x2e,0x31,0xd5 = mrs x3, trcacvr15 0x55,0x20,0x31,0xd5 = mrs x21, trcacatr0 0x5a,0x22,0x31,0xd5 = mrs x26, trcacatr1 0x48,0x24,0x31,0xd5 = mrs x8, trcacatr2 0x56,0x26,0x31,0xd5 = mrs x22, trcacatr3 0x46,0x28,0x31,0xd5 = mrs x6, trcacatr4 0x5d,0x2a,0x31,0xd5 = mrs x29, trcacatr5 0x45,0x2c,0x31,0xd5 = mrs x5, trcacatr6 0x52,0x2e,0x31,0xd5 = mrs x18, trcacatr7 0x62,0x20,0x31,0xd5 = mrs x2, trcacatr8 0x73,0x22,0x31,0xd5 = mrs x19, trcacatr9 0x6d,0x24,0x31,0xd5 = mrs x13, trcacatr10 0x79,0x26,0x31,0xd5 = mrs x25, trcacatr11 0x72,0x28,0x31,0xd5 = mrs x18, trcacatr12 0x7d,0x2a,0x31,0xd5 = mrs x29, trcacatr13 0x69,0x2c,0x31,0xd5 = mrs x9, trcacatr14 0x72,0x2e,0x31,0xd5 = mrs x18, trcacatr15 0x9d,0x20,0x31,0xd5 = mrs x29, trcdvcvr0 0x8f,0x24,0x31,0xd5 = mrs x15, trcdvcvr1 0x8f,0x28,0x31,0xd5 = mrs x15, trcdvcvr2 0x8f,0x2c,0x31,0xd5 = mrs x15, trcdvcvr3 0xb3,0x20,0x31,0xd5 = mrs x19, trcdvcvr4 0xb6,0x24,0x31,0xd5 = mrs x22, trcdvcvr5 0xbb,0x28,0x31,0xd5 = mrs x27, trcdvcvr6 0xa1,0x2c,0x31,0xd5 = mrs x1, trcdvcvr7 0xdd,0x20,0x31,0xd5 = mrs x29, trcdvcmr0 0xc9,0x24,0x31,0xd5 = mrs x9, trcdvcmr1 0xc1,0x28,0x31,0xd5 = mrs x1, trcdvcmr2 0xc2,0x2c,0x31,0xd5 = mrs x2, trcdvcmr3 0xe5,0x20,0x31,0xd5 = mrs x5, trcdvcmr4 0xf5,0x24,0x31,0xd5 = mrs x21, trcdvcmr5 0xe5,0x28,0x31,0xd5 = mrs x5, trcdvcmr6 0xe1,0x2c,0x31,0xd5 = mrs x1, trcdvcmr7 0x15,0x30,0x31,0xd5 = mrs x21, trccidcvr0 0x18,0x32,0x31,0xd5 = mrs x24, trccidcvr1 0x18,0x34,0x31,0xd5 = mrs x24, trccidcvr2 0x0c,0x36,0x31,0xd5 = mrs x12, trccidcvr3 0x0a,0x38,0x31,0xd5 = mrs x10, trccidcvr4 0x09,0x3a,0x31,0xd5 = mrs x9, trccidcvr5 0x06,0x3c,0x31,0xd5 = mrs x6, trccidcvr6 0x14,0x3e,0x31,0xd5 = mrs x20, trccidcvr7 0x34,0x30,0x31,0xd5 = mrs x20, trcvmidcvr0 0x34,0x32,0x31,0xd5 = mrs x20, trcvmidcvr1 0x3a,0x34,0x31,0xd5 = mrs x26, trcvmidcvr2 0x21,0x36,0x31,0xd5 = mrs x1, trcvmidcvr3 0x2e,0x38,0x31,0xd5 = mrs x14, trcvmidcvr4 0x3b,0x3a,0x31,0xd5 = mrs x27, trcvmidcvr5 0x3d,0x3c,0x31,0xd5 = mrs x29, trcvmidcvr6 0x31,0x3e,0x31,0xd5 = mrs x17, trcvmidcvr7 0x4a,0x30,0x31,0xd5 = mrs x10, trccidcctlr0 0x44,0x31,0x31,0xd5 = mrs x4, trccidcctlr1 0x49,0x32,0x31,0xd5 = mrs x9, trcvmidcctlr0 0x4b,0x33,0x31,0xd5 = mrs x11, trcvmidcctlr1 0x96,0x70,0x31,0xd5 = mrs x22, trcitctrl 0xd7,0x78,0x31,0xd5 = mrs x23, trcclaimset 0xce,0x79,0x31,0xd5 = mrs x14, trcclaimclr 0x9c,0x10,0x11,0xd5 = msr trcoslar, x28 0xce,0x7c,0x11,0xd5 = msr trclar, x14 0x0a,0x01,0x11,0xd5 = msr trcprgctlr, x10 0x1b,0x02,0x11,0xd5 = msr trcprocselr, x27 0x18,0x04,0x11,0xd5 = msr trcconfigr, x24 0x08,0x06,0x11,0xd5 = msr trcauxctlr, x8 0x10,0x08,0x11,0xd5 = msr trceventctl0r, x16 0x1b,0x09,0x11,0xd5 = msr trceventctl1r, x27 0x1a,0x0b,0x11,0xd5 = msr trcstallctlr, x26 0x00,0x0c,0x11,0xd5 = msr trctsctlr, x0 0x0e,0x0d,0x11,0xd5 = msr trcsyncpr, x14 0x08,0x0e,0x11,0xd5 = msr trcccctlr, x8 0x06,0x0f,0x11,0xd5 = msr trcbbctlr, x6 0x37,0x00,0x11,0xd5 = msr trctraceidr, x23 0x25,0x01,0x11,0xd5 = msr trcqctlr, x5 0x40,0x00,0x11,0xd5 = msr trcvictlr, x0 0x40,0x01,0x11,0xd5 = msr trcviiectlr, x0 0x41,0x02,0x11,0xd5 = msr trcvissctlr, x1 0x40,0x03,0x11,0xd5 = msr trcvipcssctlr, x0 0x47,0x08,0x11,0xd5 = msr trcvdctlr, x7 0x52,0x09,0x11,0xd5 = msr trcvdsacctlr, x18 0x58,0x0a,0x11,0xd5 = msr trcvdarcctlr, x24 0x9c,0x00,0x11,0xd5 = msr trcseqevr0, x28 0x95,0x01,0x11,0xd5 = msr trcseqevr1, x21 0x90,0x02,0x11,0xd5 = msr trcseqevr2, x16 0x90,0x06,0x11,0xd5 = msr trcseqrstevr, x16 0x99,0x07,0x11,0xd5 = msr trcseqstr, x25 0x9d,0x08,0x11,0xd5 = msr trcextinselr, x29 0xb4,0x00,0x11,0xd5 = msr trccntrldvr0, x20 0xb4,0x01,0x11,0xd5 = msr trccntrldvr1, x20 0xb6,0x02,0x11,0xd5 = msr trccntrldvr2, x22 0xac,0x03,0x11,0xd5 = msr trccntrldvr3, x12 0xb4,0x04,0x11,0xd5 = msr trccntctlr0, x20 0xa4,0x05,0x11,0xd5 = msr trccntctlr1, x4 0xa8,0x06,0x11,0xd5 = msr trccntctlr2, x8 0xb0,0x07,0x11,0xd5 = msr trccntctlr3, x16 0xa5,0x08,0x11,0xd5 = msr trccntvr0, x5 0xbb,0x09,0x11,0xd5 = msr trccntvr1, x27 0xb5,0x0a,0x11,0xd5 = msr trccntvr2, x21 0xa8,0x0b,0x11,0xd5 = msr trccntvr3, x8 0xe6,0x00,0x11,0xd5 = msr trcimspec0, x6 0xfb,0x01,0x11,0xd5 = msr trcimspec1, x27 0xf7,0x02,0x11,0xd5 = msr trcimspec2, x23 0xef,0x03,0x11,0xd5 = msr trcimspec3, x15 0xed,0x04,0x11,0xd5 = msr trcimspec4, x13 0xf9,0x05,0x11,0xd5 = msr trcimspec5, x25 0xf3,0x06,0x11,0xd5 = msr trcimspec6, x19 0xfb,0x07,0x11,0xd5 = msr trcimspec7, x27 0x04,0x12,0x11,0xd5 = msr trcrsctlr2, x4 0x00,0x13,0x11,0xd5 = msr trcrsctlr3, x0 0x15,0x14,0x11,0xd5 = msr trcrsctlr4, x21 0x08,0x15,0x11,0xd5 = msr trcrsctlr5, x8 0x14,0x16,0x11,0xd5 = msr trcrsctlr6, x20 0x0b,0x17,0x11,0xd5 = msr trcrsctlr7, x11 0x12,0x18,0x11,0xd5 = msr trcrsctlr8, x18 0x18,0x19,0x11,0xd5 = msr trcrsctlr9, x24 0x0f,0x1a,0x11,0xd5 = msr trcrsctlr10, x15 0x15,0x1b,0x11,0xd5 = msr trcrsctlr11, x21 0x04,0x1c,0x11,0xd5 = msr trcrsctlr12, x4 0x1c,0x1d,0x11,0xd5 = msr trcrsctlr13, x28 0x03,0x1e,0x11,0xd5 = msr trcrsctlr14, x3 0x14,0x1f,0x11,0xd5 = msr trcrsctlr15, x20 0x2c,0x10,0x11,0xd5 = msr trcrsctlr16, x12 0x31,0x11,0x11,0xd5 = msr trcrsctlr17, x17 0x2a,0x12,0x11,0xd5 = msr trcrsctlr18, x10 0x2b,0x13,0x11,0xd5 = msr trcrsctlr19, x11 0x23,0x14,0x11,0xd5 = msr trcrsctlr20, x3 0x32,0x15,0x11,0xd5 = msr trcrsctlr21, x18 0x3a,0x16,0x11,0xd5 = msr trcrsctlr22, x26 0x25,0x17,0x11,0xd5 = msr trcrsctlr23, x5 0x39,0x18,0x11,0xd5 = msr trcrsctlr24, x25 0x25,0x19,0x11,0xd5 = msr trcrsctlr25, x5 0x24,0x1a,0x11,0xd5 = msr trcrsctlr26, x4 0x34,0x1b,0x11,0xd5 = msr trcrsctlr27, x20 0x25,0x1c,0x11,0xd5 = msr trcrsctlr28, x5 0x2a,0x1d,0x11,0xd5 = msr trcrsctlr29, x10 0x38,0x1e,0x11,0xd5 = msr trcrsctlr30, x24 0x34,0x1f,0x11,0xd5 = msr trcrsctlr31, x20 0x57,0x10,0x11,0xd5 = msr trcssccr0, x23 0x5b,0x11,0x11,0xd5 = msr trcssccr1, x27 0x5b,0x12,0x11,0xd5 = msr trcssccr2, x27 0x46,0x13,0x11,0xd5 = msr trcssccr3, x6 0x43,0x14,0x11,0xd5 = msr trcssccr4, x3 0x4c,0x15,0x11,0xd5 = msr trcssccr5, x12 0x47,0x16,0x11,0xd5 = msr trcssccr6, x7 0x46,0x17,0x11,0xd5 = msr trcssccr7, x6 0x54,0x18,0x11,0xd5 = msr trcsscsr0, x20 0x51,0x19,0x11,0xd5 = msr trcsscsr1, x17 0x4b,0x1a,0x11,0xd5 = msr trcsscsr2, x11 0x44,0x1b,0x11,0xd5 = msr trcsscsr3, x4 0x4e,0x1c,0x11,0xd5 = msr trcsscsr4, x14 0x56,0x1d,0x11,0xd5 = msr trcsscsr5, x22 0x43,0x1e,0x11,0xd5 = msr trcsscsr6, x3 0x4b,0x1f,0x11,0xd5 = msr trcsscsr7, x11 0x62,0x10,0x11,0xd5 = msr trcsspcicr0, x2 0x63,0x11,0x11,0xd5 = msr trcsspcicr1, x3 0x65,0x12,0x11,0xd5 = msr trcsspcicr2, x5 0x67,0x13,0x11,0xd5 = msr trcsspcicr3, x7 0x6b,0x14,0x11,0xd5 = msr trcsspcicr4, x11 0x6d,0x15,0x11,0xd5 = msr trcsspcicr5, x13 0x71,0x16,0x11,0xd5 = msr trcsspcicr6, x17 0x77,0x17,0x11,0xd5 = msr trcsspcicr7, x23 0x83,0x14,0x11,0xd5 = msr trcpdcr, x3 0x06,0x20,0x11,0xd5 = msr trcacvr0, x6 0x14,0x22,0x11,0xd5 = msr trcacvr1, x20 0x19,0x24,0x11,0xd5 = msr trcacvr2, x25 0x01,0x26,0x11,0xd5 = msr trcacvr3, x1 0x1c,0x28,0x11,0xd5 = msr trcacvr4, x28 0x0f,0x2a,0x11,0xd5 = msr trcacvr5, x15 0x19,0x2c,0x11,0xd5 = msr trcacvr6, x25 0x0c,0x2e,0x11,0xd5 = msr trcacvr7, x12 0x25,0x20,0x11,0xd5 = msr trcacvr8, x5 0x39,0x22,0x11,0xd5 = msr trcacvr9, x25 0x2d,0x24,0x11,0xd5 = msr trcacvr10, x13 0x2a,0x26,0x11,0xd5 = msr trcacvr11, x10 0x33,0x28,0x11,0xd5 = msr trcacvr12, x19 0x2a,0x2a,0x11,0xd5 = msr trcacvr13, x10 0x33,0x2c,0x11,0xd5 = msr trcacvr14, x19 0x22,0x2e,0x11,0xd5 = msr trcacvr15, x2 0x4f,0x20,0x11,0xd5 = msr trcacatr0, x15 0x4d,0x22,0x11,0xd5 = msr trcacatr1, x13 0x48,0x24,0x11,0xd5 = msr trcacatr2, x8 0x41,0x26,0x11,0xd5 = msr trcacatr3, x1 0x4b,0x28,0x11,0xd5 = msr trcacatr4, x11 0x48,0x2a,0x11,0xd5 = msr trcacatr5, x8 0x58,0x2c,0x11,0xd5 = msr trcacatr6, x24 0x46,0x2e,0x11,0xd5 = msr trcacatr7, x6 0x77,0x20,0x11,0xd5 = msr trcacatr8, x23 0x65,0x22,0x11,0xd5 = msr trcacatr9, x5 0x6b,0x24,0x11,0xd5 = msr trcacatr10, x11 0x6b,0x26,0x11,0xd5 = msr trcacatr11, x11 0x63,0x28,0x11,0xd5 = msr trcacatr12, x3 0x7c,0x2a,0x11,0xd5 = msr trcacatr13, x28 0x79,0x2c,0x11,0xd5 = msr trcacatr14, x25 0x64,0x2e,0x11,0xd5 = msr trcacatr15, x4 0x86,0x20,0x11,0xd5 = msr trcdvcvr0, x6 0x83,0x24,0x11,0xd5 = msr trcdvcvr1, x3 0x85,0x28,0x11,0xd5 = msr trcdvcvr2, x5 0x8b,0x2c,0x11,0xd5 = msr trcdvcvr3, x11 0xa9,0x20,0x11,0xd5 = msr trcdvcvr4, x9 0xae,0x24,0x11,0xd5 = msr trcdvcvr5, x14 0xaa,0x28,0x11,0xd5 = msr trcdvcvr6, x10 0xac,0x2c,0x11,0xd5 = msr trcdvcvr7, x12 0xc8,0x20,0x11,0xd5 = msr trcdvcmr0, x8 0xc8,0x24,0x11,0xd5 = msr trcdvcmr1, x8 0xd6,0x28,0x11,0xd5 = msr trcdvcmr2, x22 0xd6,0x2c,0x11,0xd5 = msr trcdvcmr3, x22 0xe5,0x20,0x11,0xd5 = msr trcdvcmr4, x5 0xf0,0x24,0x11,0xd5 = msr trcdvcmr5, x16 0xfb,0x28,0x11,0xd5 = msr trcdvcmr6, x27 0xf5,0x2c,0x11,0xd5 = msr trcdvcmr7, x21 0x08,0x30,0x11,0xd5 = msr trccidcvr0, x8 0x06,0x32,0x11,0xd5 = msr trccidcvr1, x6 0x09,0x34,0x11,0xd5 = msr trccidcvr2, x9 0x08,0x36,0x11,0xd5 = msr trccidcvr3, x8 0x03,0x38,0x11,0xd5 = msr trccidcvr4, x3 0x15,0x3a,0x11,0xd5 = msr trccidcvr5, x21 0x0c,0x3c,0x11,0xd5 = msr trccidcvr6, x12 0x07,0x3e,0x11,0xd5 = msr trccidcvr7, x7 0x24,0x30,0x11,0xd5 = msr trcvmidcvr0, x4 0x23,0x32,0x11,0xd5 = msr trcvmidcvr1, x3 0x29,0x34,0x11,0xd5 = msr trcvmidcvr2, x9 0x31,0x36,0x11,0xd5 = msr trcvmidcvr3, x17 0x2e,0x38,0x11,0xd5 = msr trcvmidcvr4, x14 0x2c,0x3a,0x11,0xd5 = msr trcvmidcvr5, x12 0x2a,0x3c,0x11,0xd5 = msr trcvmidcvr6, x10 0x23,0x3e,0x11,0xd5 = msr trcvmidcvr7, x3 0x4e,0x30,0x11,0xd5 = msr trccidcctlr0, x14 0x56,0x31,0x11,0xd5 = msr trccidcctlr1, x22 0x48,0x32,0x11,0xd5 = msr trcvmidcctlr0, x8 0x4f,0x33,0x11,0xd5 = msr trcvmidcctlr1, x15 0x81,0x70,0x11,0xd5 = msr trcitctrl, x1 0xc7,0x78,0x11,0xd5 = msr trcclaimset, x7 0xdd,0x79,0x11,0xd5 = msr trcclaimclr, x29 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-aliases.s.cs000064400000000000000000000003770072674642500212470ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x03,0x10,0x82,0xe0 = add r1, r2, r3 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 0x03,0x10,0x82,0xe1 = orr r1, r2, r3 0x03,0x10,0x02,0xe0 = and r1, r2, r3 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-arithmetic-aliases.s.cs000064400000000000000000000036000072674642500233660ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x06,0x20,0x42,0xe2 = sub r2, r2, #6 0x06,0x20,0x42,0xe2 = sub r2, r2, #6 0x03,0x20,0x42,0xe0 = sub r2, r2, r3 0x03,0x20,0x42,0xe0 = sub r2, r2, r3 0x06,0x20,0x82,0xe2 = add r2, r2, #6 0x06,0x20,0x82,0xe2 = add r2, r2, #6 0x03,0x20,0x82,0xe0 = add r2, r2, r3 0x03,0x20,0x82,0xe0 = add r2, r2, r3 0x06,0x20,0x02,0xe2 = and r2, r2, #6 0x06,0x20,0x02,0xe2 = and r2, r2, #6 0x03,0x20,0x02,0xe0 = and r2, r2, r3 0x03,0x20,0x02,0xe0 = and r2, r2, r3 0x06,0x20,0x82,0xe3 = orr r2, r2, #6 0x06,0x20,0x82,0xe3 = orr r2, r2, #6 0x03,0x20,0x82,0xe1 = orr r2, r2, r3 0x03,0x20,0x82,0xe1 = orr r2, r2, r3 0x06,0x20,0x22,0xe2 = eor r2, r2, #6 0x06,0x20,0x22,0xe2 = eor r2, r2, #6 0x03,0x20,0x22,0xe0 = eor r2, r2, r3 0x03,0x20,0x22,0xe0 = eor r2, r2, r3 0x06,0x20,0xc2,0xe3 = bic r2, r2, #6 0x06,0x20,0xc2,0xe3 = bic r2, r2, #6 0x03,0x20,0xc2,0xe1 = bic r2, r2, r3 0x03,0x20,0xc2,0xe1 = bic r2, r2, r3 0x06,0x20,0x52,0x02 = subseq r2, r2, #6 0x06,0x20,0x52,0x02 = subseq r2, r2, #6 0x03,0x20,0x52,0x00 = subseq r2, r2, r3 0x03,0x20,0x52,0x00 = subseq r2, r2, r3 0x06,0x20,0x92,0x02 = addseq r2, r2, #6 0x06,0x20,0x92,0x02 = addseq r2, r2, #6 0x03,0x20,0x92,0x00 = addseq r2, r2, r3 0x03,0x20,0x92,0x00 = addseq r2, r2, r3 0x06,0x20,0x12,0x02 = andseq r2, r2, #6 0x06,0x20,0x12,0x02 = andseq r2, r2, #6 0x03,0x20,0x12,0x00 = andseq r2, r2, r3 0x03,0x20,0x12,0x00 = andseq r2, r2, r3 0x06,0x20,0x92,0x03 = orrseq r2, r2, #6 0x06,0x20,0x92,0x03 = orrseq r2, r2, #6 0x03,0x20,0x92,0x01 = orrseq r2, r2, r3 0x03,0x20,0x92,0x01 = orrseq r2, r2, r3 0x06,0x20,0x32,0x02 = eorseq r2, r2, #6 0x06,0x20,0x32,0x02 = eorseq r2, r2, #6 0x03,0x20,0x32,0x00 = eorseq r2, r2, r3 0x03,0x20,0x32,0x00 = eorseq r2, r2, r3 0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6 0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3 0x7b,0x00,0x8f,0xe2 = add r0, pc, #123 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-it-block.s.cs000064400000000000000000000001040072674642500213160ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x03,0x20,0xa0,0x01 = moveq r2, r3 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-memory-instructions.s.cs000064400000000000000000000132530072674642500236750ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x00,0x50,0x97,0xe5 = ldr r5, [r7] 0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #63] 0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #4095]! 0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #30 0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-30 0x00,0x90,0x12,0xe4 = ldr r9, [r2], #-0 0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1] 0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3] 0x09,0x10,0xb5,0xe7 = ldr r1, [r5, r9]! 0x08,0x60,0x37,0xe7 = ldr r6, [r7, -r8]! 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]! 0x02,0x50,0x99,0xe6 = ldr r5, [r9], r2 0x06,0x40,0x13,0xe6 = ldr r4, [r3], -r6 0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #15] 0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #15 0x00,0x30,0xd8,0xe5 = ldrb r3, [r8] 0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #63] 0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #4095]! 0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #22 0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-19 0x05,0x90,0xd8,0xe7 = ldrb r9, [r8, r5] 0x01,0x10,0x55,0xe7 = ldrb r1, [r5, -r1] 0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]! 0x03,0x60,0x79,0xe7 = ldrb r6, [r9, -r3]! 0x04,0x20,0xd1,0xe6 = ldrb r2, [r1], r4 0x05,0x80,0x54,0xe6 = ldrb r8, [r4], -r5 0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #15] 0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #15 0x04,0x30,0xf1,0xe4 = ldrbt r3, [r1], #4 0x08,0x20,0x78,0xe4 = ldrbt r2, [r8], #-8 0x06,0x80,0xf7,0xe6 = ldrbt r8, [r7], r6 0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #12 0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5] 0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #15] 0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #32]! 0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0 0xd0,0x00,0x48,0xe0 = ldrd r0, r1, [r8], #-0 0xd3,0x40,0x81,0xe1 = ldrd r4, r5, [r1, r3] 0xd2,0x40,0xa7,0xe1 = ldrd r4, r5, [r7, r2]! 0xdc,0x00,0x88,0xe0 = ldrd r0, r1, [r8], r12 0xdc,0x00,0x08,0xe0 = ldrd r0, r1, [r8], -r12 0xb0,0x30,0xd4,0xe1 = ldrh r3, [r4] 0xb4,0x20,0xd7,0xe1 = ldrh r2, [r7, #4] 0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #64]! 0xb4,0xc0,0xdd,0xe0 = ldrh ip, [sp], #4 0xb4,0x60,0x95,0xe1 = ldrh r6, [r5, r4] 0xbb,0x30,0xb8,0xe1 = ldrh r3, [r8, r11]! 0xb1,0x10,0x32,0xe1 = ldrh r1, [r2, -r1]! 0xb2,0x90,0x97,0xe0 = ldrh r9, [r7], r2 0xb2,0x40,0x13,0xe0 = ldrh r4, [r3], -r2 0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #128 0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-75 0xb2,0x90,0xb7,0xe0 = ldrht r9, [r7], r2 0xb2,0x40,0x33,0xe0 = ldrht r4, [r3], -r2 0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4] 0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #17] 0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #255]! 0xd9,0xc0,0xdd,0xe0 = ldrsb ip, [sp], #9 0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4] 0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]! 0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]! 0xd2,0x90,0x97,0xe0 = ldrsb r9, [r7], r2 0xd2,0x40,0x13,0xe0 = ldrsb r4, [r3], -r2 0xd1,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #1 0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-12 0xd5,0x80,0xb9,0xe0 = ldrsbt r8, [r9], r5 0xd4,0x20,0x31,0xe0 = ldrsbt r2, [r1], -r4 0xf0,0x50,0xd9,0xe1 = ldrsh r5, [r9] 0xf7,0x40,0xd5,0xe1 = ldrsh r4, [r5, #7] 0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #55]! 0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-9 0xf5,0x30,0x91,0xe1 = ldrsh r3, [r1, r5] 0xf1,0x40,0xb6,0xe1 = ldrsh r4, [r6, r1]! 0xf6,0x50,0x33,0xe1 = ldrsh r5, [r3, -r6]! 0xf8,0x60,0x99,0xe0 = ldrsh r6, [r9], r8 0xf3,0x70,0x18,0xe0 = ldrsh r7, [r8], -r3 0xf1,0x50,0xf6,0xe0 = ldrsht r5, [r6], #1 0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-12 0xf5,0x80,0xb9,0xe0 = ldrsht r8, [r9], r5 0xf4,0x20,0x31,0xe0 = ldrsht r2, [r1], -r4 0x00,0x80,0x8c,0xe5 = str r8, [r12] 0x0c,0x70,0x81,0xe5 = str r7, [r1, #12] 0x28,0x30,0xa5,0xe5 = str r3, [r5, #40]! 0xff,0x9f,0x8d,0xe4 = str sb, [sp], #4095 0x80,0x10,0x07,0xe4 = str r1, [r7], #-128 0x00,0x10,0x00,0xe4 = str r1, [r0], #-0 0x03,0x90,0x86,0xe7 = str r9, [r6, r3] 0x02,0x80,0x00,0xe7 = str r8, [r0, -r2] 0x06,0x70,0xa1,0xe7 = str r7, [r1, r6]! 0x01,0x60,0x2d,0xe7 = str r6, [sp, -r1]! 0x09,0x50,0x83,0xe6 = str r5, [r3], r9 0x05,0x40,0x02,0xe6 = str r4, [r2], -r5 0x02,0x31,0x04,0xe7 = str r3, [r4, -r2, lsl #2] 0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #24 0x00,0x90,0xc2,0xe5 = strb r9, [r2] 0x03,0x70,0xc1,0xe5 = strb r7, [r1, #3] 0x95,0x61,0xe4,0xe5 = strb r6, [r4, #405]! 0x48,0x50,0xc7,0xe4 = strb r5, [r7], #72 0x01,0x10,0x4d,0xe4 = strb r1, [sp], #-1 0x09,0x10,0xc2,0xe7 = strb r1, [r2, r9] 0x08,0x20,0x43,0xe7 = strb r2, [r3, -r8] 0x07,0x30,0xe4,0xe7 = strb r3, [r4, r7]! 0x06,0x40,0x65,0xe7 = strb r4, [r5, -r6]! 0x05,0x50,0xc6,0xe6 = strb r5, [r6], r5 0x04,0x60,0x42,0xe6 = strb r6, [r2], -r4 0x83,0x72,0x4c,0xe7 = strb r7, [r12, -r3, lsl #5] 0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #12 0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #12 0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-13 0x05,0x40,0xe9,0xe6 = strbt r4, [r9], r5 0x82,0x31,0x68,0xe6 = strbt r3, [r8], -r2, lsl #3 0xf0,0x10,0xc4,0xe1 = strd r1, r2, [r4] 0xf1,0x20,0xc6,0xe1 = strd r2, r3, [r6, #1] 0xf6,0x31,0xe7,0xe1 = strd r3, r4, [r7, #22]! 0xf7,0x40,0xc8,0xe0 = strd r4, r5, [r8], #7 0xf0,0x50,0xcd,0xe0 = strd r5, r6, [sp], #0 0xf0,0x60,0xce,0xe0 = strd r6, r7, [lr], #0 0xf0,0x70,0x49,0xe0 = strd r7, r8, [r9], #-0 0xf1,0x80,0x84,0xe1 = strd r8, r9, [r4, r1] 0xf9,0x70,0xa3,0xe1 = strd r7, r8, [r3, r9]! 0xf8,0x60,0x85,0xe0 = strd r6, r7, [r5], r8 0xfa,0x50,0x0c,0xe0 = strd r5, r6, [r12], -r10 0xb0,0x30,0xc4,0xe1 = strh r3, [r4] 0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4] 0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #64]! 0xb4,0xc0,0xcd,0xe0 = strh ip, [sp], #4 0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4] 0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]! 0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]! 0xb2,0x90,0x87,0xe0 = strh r9, [r7], r2 0xb2,0x40,0x03,0xe0 = strh r4, [r3], -r2 0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #76 0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-25 0xb4,0x50,0xa3,0xe0 = strht r5, [r3], r4 0xb0,0x60,0x28,0xe0 = strht r6, [r8], -r0 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-shift-encoding.s.cs000064400000000000000000000041350072674642500225230ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0] 0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32] 0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16] 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0] 0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16] 0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32] 0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16] 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx] 0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16] 0x00,0xf0,0xd0,0xf7 = pld [r0, r0] 0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #32] 0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #16] 0x00,0xf0,0xd0,0xf7 = pld [r0, r0] 0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #16] 0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #32] 0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #16] 0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx] 0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #16] 0x00,0x00,0x80,0xe7 = str r0, [r0, r0] 0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #32] 0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #16] 0x00,0x00,0x80,0xe7 = str r0, [r0, r0] 0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #16] 0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #32] 0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #16] 0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx] 0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #16] 0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx 0x05,0x30,0x94,0xe6 = ldr r3, [r4], r5 0x08,0x60,0x87,0xe6 = str r6, [r7], r8 0x0b,0x90,0x8a,0xe6 = str r9, [r10], r11 0x0f,0xd0,0xae,0xe0 = adc sp, lr, pc 0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #32 0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #16 0x0a,0x30,0xa6,0xe0 = adc r3, r6, r10 0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #16 0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #32 0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #16 0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx 0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #16 0x0e,0x00,0x5d,0xe1 = cmp sp, lr 0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #32 0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #16 0x06,0x00,0x53,0xe1 = cmp r3, r6 0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #16 0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #32 0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #16 0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx 0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #16 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-thumb-trustzone.s.cs000064400000000000000000000001240072674642500230060ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xff,0xf7,0x00,0x80 = smc #15 0x0c,0xbf = ite eq capstone-sys-0.15.0/capstone/suite/MC/ARM/arm-trustzone.s.cs000064400000000000000000000001360072674642500216740ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x7f,0x00,0x60,0xe1 = smc #15 0x70,0x00,0x60,0x01 = smceq #0 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm_addrmode2.s.cs000064400000000000000000000012100072674642500215340ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4 0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3 0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4 0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3 0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4 0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3 0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]! 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]! capstone-sys-0.15.0/capstone/suite/MC/ARM/arm_addrmode3.s.cs000064400000000000000000000005550072674642500215500ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xd2,0x10,0xb0,0xe0 = ldrsbt r1, [r0], r2 0xd4,0x10,0xf0,0xe0 = ldrsbt r1, [r0], #4 0xf2,0x10,0xb0,0xe0 = ldrsht r1, [r0], r2 0xf4,0x10,0xf0,0xe0 = ldrsht r1, [r0], #4 0xb2,0x10,0xb0,0xe0 = ldrht r1, [r0], r2 0xb4,0x10,0xf0,0xe0 = ldrht r1, [r0], #4 0xb2,0x10,0xa0,0xe0 = strht r1, [r0], r2 0xb4,0x10,0xe0,0xe0 = strht r1, [r0], #4 capstone-sys-0.15.0/capstone/suite/MC/ARM/arm_instructions.s.cs000064400000000000000000000016720072674642500224530ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x1e,0xff,0x2f,0xe1 = bx lr 0xa0,0x0d,0xe1,0xf2 = vqdmull.s32 q8, d17, d16 0x03,0x10,0x02,0xe0 = and r1, r2, r3 0x03,0x10,0x12,0xe0 = ands r1, r2, r3 0x03,0x10,0x22,0xe0 = eor r1, r2, r3 0x03,0x10,0x32,0xe0 = eors r1, r2, r3 0x03,0x10,0x42,0xe0 = sub r1, r2, r3 0x03,0x10,0x52,0xe0 = subs r1, r2, r3 0x03,0x10,0x82,0xe0 = add r1, r2, r3 0x03,0x10,0x92,0xe0 = adds r1, r2, r3 0x03,0x10,0xa2,0xe0 = adc r1, r2, r3 0x03,0x10,0xc2,0xe1 = bic r1, r2, r3 0x03,0x10,0xd2,0xe1 = bics r1, r2, r3 0x02,0x10,0xa0,0xe1 = mov r1, r2 0x02,0x10,0xe0,0xe1 = mvn r1, r2 0x02,0x10,0xf0,0xe1 = mvns r1, r2 0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7 0x7a,0x00,0x20,0xe1 = bkpt #10 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4 0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4 0x30,0x0f,0xa6,0xe6 = ssat16 r0, #7, r0 0x00,0x00,0x0a,0xf1 = cpsie none, #0 0xb0,0x30,0x42,0xe1 = strh r3, [r2, #-0] capstone-sys-0.15.0/capstone/suite/MC/ARM/basic-arm-instructions-v8.s.cs000064400000000000000000000005020072674642500237720ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0x59,0xf0,0x7f,0xf5 = dmb ishld 0x51,0xf0,0x7f,0xf5 = dmb oshld 0x55,0xf0,0x7f,0xf5 = dmb nshld 0x5d,0xf0,0x7f,0xf5 = dmb ld 0x49,0xf0,0x7f,0xf5 = dsb ishld 0x41,0xf0,0x7f,0xf5 = dsb oshld 0x45,0xf0,0x7f,0xf5 = dsb nshld 0x4d,0xf0,0x7f,0xf5 = dsb ld 0x05,0xf0,0x20,0xe3 = sevl capstone-sys-0.15.0/capstone/suite/MC/ARM/basic-arm-instructions.s.cs000064400000000000000000001200560072674642500234460ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x0f,0x10,0xa2,0xe2 = adc r1, r2, #15 0xf0,0x10,0xa2,0xe2 = adc r1, r2, #240 0x0f,0x1c,0xa2,0xe2 = adc r1, r2, #3840 0x0f,0x1a,0xa2,0xe2 = adc r1, r2, #61440 0x0f,0x18,0xa2,0xe2 = adc r1, r2, #983040 0x0f,0x16,0xa2,0xe2 = adc r1, r2, #15728640 0x0f,0x14,0xa2,0xe2 = adc r1, r2, #251658240 0x0f,0x12,0xa2,0xe2 = adc r1, r2, #4026531840 0xff,0x12,0xa2,0xe2 = adc r1, r2, #4026531855 0x0f,0x1c,0xb2,0xe2 = adcs r1, r2, #3840 0x0f,0x1c,0xb2,0x02 = adcseq r1, r2, #3840 0x0f,0x1c,0xa2,0x02 = adceq r1, r2, #3840 0x06,0x40,0xa5,0xe0 = adc r4, r5, r6 0x86,0x40,0xa5,0xe0 = adc r4, r5, r6, lsl #1 0x86,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsl #31 0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1 0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #31 0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #32 0xc6,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #1 0xc6,0x4f,0xa5,0xe0 = adc r4, r5, r6, asr #31 0x46,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #32 0xe6,0x40,0xa5,0xe0 = adc r4, r5, r6, ror #1 0xe6,0x4f,0xa5,0xe0 = adc r4, r5, r6, ror #31 0x18,0x69,0xa7,0xe0 = adc r6, r7, r8, lsl r9 0x38,0x69,0xa7,0xe0 = adc r6, r7, r8, lsr r9 0x58,0x69,0xa7,0xe0 = adc r6, r7, r8, asr r9 0x78,0x69,0xa7,0xe0 = adc r6, r7, r8, ror r9 0x66,0x40,0xa5,0xe0 = adc r4, r5, r6, rrx 0x06,0x50,0xa5,0xe0 = adc r5, r5, r6 0x85,0x40,0xa4,0xe0 = adc r4, r4, r5, lsl #1 0x85,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsl #31 0xa5,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #1 0xa5,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsr #31 0x25,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #32 0xc5,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #1 0xc5,0x4f,0xa4,0xe0 = adc r4, r4, r5, asr #31 0x45,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #32 0xe5,0x40,0xa4,0xe0 = adc r4, r4, r5, ror #1 0xe5,0x4f,0xa4,0xe0 = adc r4, r4, r5, ror #31 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx 0x17,0x69,0xa6,0xe0 = adc r6, r6, r7, lsl r9 0x37,0x69,0xa6,0xe0 = adc r6, r6, r7, lsr r9 0x57,0x69,0xa6,0xe0 = adc r6, r6, r7, asr r9 0x77,0x69,0xa6,0xe0 = adc r6, r6, r7, ror r9 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx 0x0f,0x4a,0x85,0xe2 = add r4, r5, #61440 0x06,0x40,0x85,0xe0 = add r4, r5, r6 0x86,0x42,0x85,0xe0 = add r4, r5, r6, lsl #5 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5 0xc6,0x42,0x85,0xe0 = add r4, r5, r6, asr #5 0xe6,0x42,0x85,0xe0 = add r4, r5, r6, ror #5 0x18,0x69,0x87,0xe0 = add r6, r7, r8, lsl r9 0x13,0x49,0x84,0xe0 = add r4, r4, r3, lsl r9 0x38,0x69,0x87,0xe0 = add r6, r7, r8, lsr r9 0x58,0x69,0x87,0xe0 = add r6, r7, r8, asr r9 0x78,0x69,0x87,0xe0 = add r6, r7, r8, ror r9 0x66,0x40,0x85,0xe0 = add r4, r5, r6, rrx 0x0f,0x5a,0x85,0xe2 = add r5, r5, #61440 0x05,0x40,0x84,0xe0 = add r4, r4, r5 0x85,0x42,0x84,0xe0 = add r4, r4, r5, lsl #5 0xa5,0x42,0x84,0xe0 = add r4, r4, r5, lsr #5 0xa5,0x42,0x84,0xe0 = add r4, r4, r5, lsr #5 0xc5,0x42,0x84,0xe0 = add r4, r4, r5, asr #5 0xe5,0x42,0x84,0xe0 = add r4, r4, r5, ror #5 0x17,0x69,0x86,0xe0 = add r6, r6, r7, lsl r9 0x37,0x69,0x86,0xe0 = add r6, r6, r7, lsr r9 0x57,0x69,0x86,0xe0 = add r6, r6, r7, asr r9 0x77,0x69,0x86,0xe0 = add r6, r6, r7, ror r9 0x65,0x40,0x84,0xe0 = add r4, r4, r5, rrx 0x04,0x00,0x40,0xe2 = sub r0, r0, #4 0x15,0x40,0x45,0xe2 = sub r4, r5, #21 0x22,0x30,0x81,0xe0 = add r3, r1, r2, lsr #32 0x42,0x30,0x81,0xe0 = add r3, r1, r2, asr #32 0x0f,0xa0,0x01,0xe2 = and r10, r1, #15 0x06,0xa0,0x01,0xe0 = and r10, r1, r6 0x06,0xa5,0x01,0xe0 = and r10, r1, r6, lsl #10 0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #10 0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #10 0x46,0xa5,0x01,0xe0 = and r10, r1, r6, asr #10 0x66,0xa5,0x01,0xe0 = and r10, r1, r6, ror #10 0x18,0x62,0x07,0xe0 = and r6, r7, r8, lsl r2 0x38,0x62,0x07,0xe0 = and r6, r7, r8, lsr r2 0x58,0x62,0x07,0xe0 = and r6, r7, r8, asr r2 0x78,0x62,0x07,0xe0 = and r6, r7, r8, ror r2 0x66,0xa0,0x01,0xe0 = and r10, r1, r6, rrx 0x02,0x21,0xc3,0xe3 = bic r2, r3, #-2147483648 0x0f,0x10,0x01,0xe2 = and r1, r1, #15 0x01,0xa0,0x0a,0xe0 = and r10, r10, r1 0x01,0xa5,0x0a,0xe0 = and r10, r10, r1, lsl #10 0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #10 0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #10 0x41,0xa5,0x0a,0xe0 = and r10, r10, r1, asr #10 0x61,0xa5,0x0a,0xe0 = and r10, r10, r1, ror #10 0x17,0x62,0x06,0xe0 = and r6, r6, r7, lsl r2 0x37,0x62,0x06,0xe0 = and r6, r6, r7, lsr r2 0x57,0x62,0x06,0xe0 = and r6, r6, r7, asr r2 0x77,0x62,0x06,0xe0 = and r6, r6, r7, ror r2 0x61,0xa0,0x0a,0xe0 = and r10, r10, r1, rrx 0x22,0x30,0x01,0xe0 = and r3, r1, r2, lsr #32 0x42,0x30,0x01,0xe0 = and r3, r1, r2, asr #32 0x44,0x20,0xa0,0xe1 = asr r2, r4, #32 0x44,0x21,0xa0,0xe1 = asr r2, r4, #2 0x04,0x20,0xa0,0xe1 = mov r2, r4 0x44,0x41,0xa0,0xe1 = asr r4, r4, #2 0x9f,0x51,0xd3,0xe7 = bfc r5, #3, #17 0x9f,0x51,0xd3,0x37 = bfclo r5, #3, #17 0x92,0x51,0xd3,0xe7 = bfi r5, r2, #3, #17 0x92,0x51,0xd3,0x17 = bfine r5, r2, #3, #17 0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #15 0x06,0xa0,0xc1,0xe1 = bic r10, r1, r6 0x06,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsl #10 0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #10 0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #10 0x46,0xa5,0xc1,0xe1 = bic r10, r1, r6, asr #10 0x66,0xa5,0xc1,0xe1 = bic r10, r1, r6, ror #10 0x18,0x62,0xc7,0xe1 = bic r6, r7, r8, lsl r2 0x38,0x62,0xc7,0xe1 = bic r6, r7, r8, lsr r2 0x58,0x62,0xc7,0xe1 = bic r6, r7, r8, asr r2 0x78,0x62,0xc7,0xe1 = bic r6, r7, r8, ror r2 0x66,0xa0,0xc1,0xe1 = bic r10, r1, r6, rrx 0x0f,0x10,0xc1,0xe3 = bic r1, r1, #15 0x01,0xa0,0xca,0xe1 = bic r10, r10, r1 0x01,0xa5,0xca,0xe1 = bic r10, r10, r1, lsl #10 0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #10 0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #10 0x41,0xa5,0xca,0xe1 = bic r10, r10, r1, asr #10 0x61,0xa5,0xca,0xe1 = bic r10, r10, r1, ror #10 0x17,0x62,0xc6,0xe1 = bic r6, r6, r7, lsl r2 0x37,0x62,0xc6,0xe1 = bic r6, r6, r7, lsr r2 0x57,0x62,0xc6,0xe1 = bic r6, r6, r7, asr r2 0x77,0x62,0xc6,0xe1 = bic r6, r6, r7, ror r2 0x61,0xa0,0xca,0xe1 = bic r10, r10, r1, rrx 0x22,0x30,0xc1,0xe1 = bic r3, r1, r2, lsr #32 0x42,0x30,0xc1,0xe1 = bic r3, r1, r2, asr #32 0x7a,0x00,0x20,0xe1 = bkpt #10 0x7f,0xff,0x2f,0xe1 = bkpt #65535 0x27,0x3b,0x6d,0x9b = blls #28634276 0xa0,0xb0,0x7b,0xfa = blx #32424584 0x50,0xd8,0x3d,0xfa = blx #16212296 0x32,0xff,0x2f,0xe1 = blx r2 0x32,0xff,0x2f,0x11 = blxne r2 0x12,0xff,0x2f,0xe1 = bx r2 0x12,0xff,0x2f,0x11 = bxne r2 0x22,0xff,0x2f,0xe1 = bxj r2 0x22,0xff,0x2f,0x11 = bxjne r2 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4 0xe0,0x6c,0x0c,0xfe = cdp2 p12, #0, c6, c12, c0, #7 0x81,0x17,0x11,0x1e = cdpne p7, #1, c1, c1, c1, #4 0x1f,0xf0,0x7f,0xf5 = clrex 0x12,0x1f,0x6f,0xe1 = clz r1, r2 0x12,0x1f,0x6f,0x01 = clzeq r1, r2 0x0f,0x00,0x71,0xe3 = cmn r1, #15 0x06,0x00,0x71,0xe1 = cmn r1, r6 0x06,0x05,0x71,0xe1 = cmn r1, r6, lsl #10 0x26,0x05,0x71,0xe1 = cmn r1, r6, lsr #10 0x26,0x05,0x7d,0xe1 = cmn sp, r6, lsr #10 0x46,0x05,0x71,0xe1 = cmn r1, r6, asr #10 0x66,0x05,0x71,0xe1 = cmn r1, r6, ror #10 0x18,0x02,0x77,0xe1 = cmn r7, r8, lsl r2 0x38,0x02,0x7d,0xe1 = cmn sp, r8, lsr r2 0x58,0x02,0x77,0xe1 = cmn r7, r8, asr r2 0x78,0x02,0x77,0xe1 = cmn r7, r8, ror r2 0x66,0x00,0x71,0xe1 = cmn r1, r6, rrx 0x0f,0x00,0x51,0xe3 = cmp r1, #15 0x06,0x00,0x51,0xe1 = cmp r1, r6 0x06,0x05,0x51,0xe1 = cmp r1, r6, lsl #10 0x26,0x05,0x51,0xe1 = cmp r1, r6, lsr #10 0x26,0x05,0x5d,0xe1 = cmp sp, r6, lsr #10 0x46,0x05,0x51,0xe1 = cmp r1, r6, asr #10 0x66,0x05,0x51,0xe1 = cmp r1, r6, ror #10 0x18,0x02,0x57,0xe1 = cmp r7, r8, lsl r2 0x38,0x02,0x5d,0xe1 = cmp sp, r8, lsr r2 0x58,0x02,0x57,0xe1 = cmp r7, r8, asr r2 0x78,0x02,0x57,0xe1 = cmp r7, r8, ror r2 0x66,0x00,0x51,0xe1 = cmp r1, r6, rrx 0x02,0x00,0x70,0xe3 = cmn r0, #2 0x00,0x00,0x5e,0xe3 = cmp lr, #0 0xc0,0x01,0x08,0xf1 = cpsie aif 0x0f,0x00,0x02,0xf1 = cps #15 0xca,0x00,0x0e,0xf1 = cpsid if, #10 0xf0,0xf0,0x20,0xe3 = dbg #0 0xf5,0xf0,0x20,0xe3 = dbg #5 0xff,0xf0,0x20,0xe3 = dbg #15 0x5f,0xf0,0x7f,0xf5 = dmb sy 0x5e,0xf0,0x7f,0xf5 = dmb st 0x5d,0xf0,0x7f,0xf5 = dmb #0xd 0x5c,0xf0,0x7f,0xf5 = dmb #0xc 0x5b,0xf0,0x7f,0xf5 = dmb ish 0x5a,0xf0,0x7f,0xf5 = dmb ishst 0x59,0xf0,0x7f,0xf5 = dmb #0x9 0x58,0xf0,0x7f,0xf5 = dmb #0x8 0x57,0xf0,0x7f,0xf5 = dmb nsh 0x56,0xf0,0x7f,0xf5 = dmb nshst 0x55,0xf0,0x7f,0xf5 = dmb #0x5 0x54,0xf0,0x7f,0xf5 = dmb #0x4 0x53,0xf0,0x7f,0xf5 = dmb osh 0x52,0xf0,0x7f,0xf5 = dmb oshst 0x51,0xf0,0x7f,0xf5 = dmb #0x1 0x50,0xf0,0x7f,0xf5 = dmb #0x0 0x5f,0xf0,0x7f,0xf5 = dmb sy 0x5e,0xf0,0x7f,0xf5 = dmb st 0x5b,0xf0,0x7f,0xf5 = dmb ish 0x5b,0xf0,0x7f,0xf5 = dmb ish 0x5a,0xf0,0x7f,0xf5 = dmb ishst 0x5a,0xf0,0x7f,0xf5 = dmb ishst 0x57,0xf0,0x7f,0xf5 = dmb nsh 0x57,0xf0,0x7f,0xf5 = dmb nsh 0x56,0xf0,0x7f,0xf5 = dmb nshst 0x56,0xf0,0x7f,0xf5 = dmb nshst 0x53,0xf0,0x7f,0xf5 = dmb osh 0x52,0xf0,0x7f,0xf5 = dmb oshst 0x5f,0xf0,0x7f,0xf5 = dmb sy 0x4f,0xf0,0x7f,0xf5 = dsb sy 0x4e,0xf0,0x7f,0xf5 = dsb st 0x4d,0xf0,0x7f,0xf5 = dsb #0xd 0x4b,0xf0,0x7f,0xf5 = dsb ish 0x4a,0xf0,0x7f,0xf5 = dsb ishst 0x49,0xf0,0x7f,0xf5 = dsb #0x9 0x48,0xf0,0x7f,0xf5 = dsb #0x8 0x47,0xf0,0x7f,0xf5 = dsb nsh 0x46,0xf0,0x7f,0xf5 = dsb nshst 0x45,0xf0,0x7f,0xf5 = dsb #0x5 0x44,0xf0,0x7f,0xf5 = dsb #0x4 0x43,0xf0,0x7f,0xf5 = dsb osh 0x42,0xf0,0x7f,0xf5 = dsb oshst 0x41,0xf0,0x7f,0xf5 = dsb #0x1 0x40,0xf0,0x7f,0xf5 = dsb #0x0 0x48,0xf0,0x7f,0xf5 = dsb #0x8 0x47,0xf0,0x7f,0xf5 = dsb nsh 0x4f,0xf0,0x7f,0xf5 = dsb sy 0x4e,0xf0,0x7f,0xf5 = dsb st 0x4b,0xf0,0x7f,0xf5 = dsb ish 0x4b,0xf0,0x7f,0xf5 = dsb ish 0x4a,0xf0,0x7f,0xf5 = dsb ishst 0x4a,0xf0,0x7f,0xf5 = dsb ishst 0x47,0xf0,0x7f,0xf5 = dsb nsh 0x47,0xf0,0x7f,0xf5 = dsb nsh 0x46,0xf0,0x7f,0xf5 = dsb nshst 0x46,0xf0,0x7f,0xf5 = dsb nshst 0x43,0xf0,0x7f,0xf5 = dsb osh 0x42,0xf0,0x7f,0xf5 = dsb oshst 0x4f,0xf0,0x7f,0xf5 = dsb sy 0x4f,0xf0,0x7f,0xf5 = dsb sy 0x42,0xf0,0x7f,0xf5 = dsb oshst 0x0f,0x4a,0x25,0xe2 = eor r4, r5, #61440 0x06,0x40,0x25,0xe0 = eor r4, r5, r6 0x86,0x42,0x25,0xe0 = eor r4, r5, r6, lsl #5 0xa6,0x42,0x25,0xe0 = eor r4, r5, r6, lsr #5 0xa6,0x42,0x25,0xe0 = eor r4, r5, r6, lsr #5 0xc6,0x42,0x25,0xe0 = eor r4, r5, r6, asr #5 0xe6,0x42,0x25,0xe0 = eor r4, r5, r6, ror #5 0x18,0x69,0x27,0xe0 = eor r6, r7, r8, lsl r9 0x38,0x69,0x27,0xe0 = eor r6, r7, r8, lsr r9 0x58,0x69,0x27,0xe0 = eor r6, r7, r8, asr r9 0x78,0x69,0x27,0xe0 = eor r6, r7, r8, ror r9 0x66,0x40,0x25,0xe0 = eor r4, r5, r6, rrx 0x0f,0x5a,0x25,0xe2 = eor r5, r5, #61440 0x05,0x40,0x24,0xe0 = eor r4, r4, r5 0x85,0x42,0x24,0xe0 = eor r4, r4, r5, lsl #5 0xa5,0x42,0x24,0xe0 = eor r4, r4, r5, lsr #5 0xa5,0x42,0x24,0xe0 = eor r4, r4, r5, lsr #5 0xc5,0x42,0x24,0xe0 = eor r4, r4, r5, asr #5 0xe5,0x42,0x24,0xe0 = eor r4, r4, r5, ror #5 0x17,0x69,0x26,0xe0 = eor r6, r6, r7, lsl r9 0x37,0x69,0x26,0xe0 = eor r6, r6, r7, lsr r9 0x57,0x69,0x26,0xe0 = eor r6, r6, r7, asr r9 0x77,0x69,0x26,0xe0 = eor r6, r6, r7, ror r9 0x65,0x40,0x24,0xe0 = eor r4, r4, r5, rrx 0x22,0x30,0x21,0xe0 = eor r3, r1, r2, lsr #32 0x42,0x30,0x21,0xe0 = eor r3, r1, r2, asr #32 0x6f,0xf0,0x7f,0xf5 = isb sy 0x6f,0xf0,0x7f,0xf5 = isb sy 0x6f,0xf0,0x7f,0xf5 = isb sy 0x61,0xf0,0x7f,0xf5 = isb #0x1 0x01,0x80,0x91,0xfd = ldc2 p0, c8, [r1, #4] 0x00,0x71,0x92,0xfd = ldc2 p1, c7, [r2] 0x38,0x62,0x13,0xfd = ldc2 p2, c6, [r3, #-224] 0x1e,0x53,0x34,0xfd = ldc2 p3, c5, [r4, #-120]! 0x04,0x44,0xb5,0xfc = ldc2 p4, c4, [r5], #16 0x12,0x35,0x36,0xfc = ldc2 p5, c3, [r6], #-72 0x01,0x26,0xd7,0xfd = ldc2l p6, c2, [r7, #4] 0x00,0x17,0xd8,0xfd = ldc2l p7, c1, [r8] 0x38,0x08,0x59,0xfd = ldc2l p8, c0, [r9, #-224] 0x1e,0x19,0x7a,0xfd = ldc2l p9, c1, [r10, #-120]! 0x04,0x20,0xfb,0xfc = ldc2l p0, c2, [r11], #16 0x12,0x31,0x7c,0xfc = ldc2l p1, c3, [r12], #-72 0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4] 0x00,0x5d,0x91,0xed = ldc p13, c5, [r1] 0x38,0x6e,0x12,0xed = ldc p14, c6, [r2, #-224] 0x1e,0x7f,0x33,0xed = ldc p15, c7, [r3, #-120]! 0x04,0x85,0xb4,0xec = ldc p5, c8, [r4], #16 0x12,0x94,0x35,0xec = ldc p4, c9, [r5], #-72 0x01,0xa3,0xd6,0xed = ldcl p3, c10, [r6, #4] 0x00,0xb2,0xd7,0xed = ldcl p2, c11, [r7] 0x38,0xc1,0x58,0xed = ldcl p1, c12, [r8, #-224] 0x1e,0xd0,0x79,0xed = ldcl p0, c13, [r9, #-120]! 0x04,0xe6,0xfa,0xec = ldcl p6, c14, [r10], #16 0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-72 0x01,0x4c,0x90,0x3d = ldclo p12, c4, [r0, #4] 0x00,0x5d,0x91,0x8d = ldchi p13, c5, [r1] 0x38,0x6e,0x12,0x2d = ldchs p14, c6, [r2, #-224] 0x1e,0x7f,0x33,0x3d = ldclo p15, c7, [r3, #-120]! 0x04,0x85,0xb4,0x0c = ldceq p5, c8, [r4], #16 0x12,0x94,0x35,0xcc = ldcgt p4, c9, [r5], #-72 0x01,0xa3,0xd6,0xbd = ldcllt p3, c10, [r6, #4] 0x00,0xb2,0xd7,0xad = ldclge p2, c11, [r7] 0x38,0xc1,0x58,0xdd = ldclle p1, c12, [r8, #-224] 0x1e,0xd0,0x79,0x1d = ldclne p0, c13, [r9, #-120]! 0x04,0xe6,0xfa,0x0c = ldcleq p6, c14, [r10], #16 0x12,0xf7,0x7b,0x8c = ldclhi p7, c15, [r11], #-72 0x19,0x82,0x91,0xfc = ldc2 p2, c8, [r1], {25} 0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x92,0xe9 = ldmib r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x12,0xe8 = ldmda r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x12,0xe9 = ldmdb r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0xb2,0xe8 = ldm r2!, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0xb2,0xe9 = ldmib r2!, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x32,0xe8 = ldmda r2!, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x32,0xe9 = ldmdb r2!, {r1, r3, r4, r5, r6, sp} 0x05,0x40,0xd0,0xe8 = ldm r0, {r0, r2, lr} ^ 0x0f,0x80,0xfd,0xe8 = ldm sp!, {r0, r1, r2, r3, pc} ^ 0x9f,0x3f,0xd4,0xe1 = ldrexb r3, [r4] 0x9f,0x2f,0xf5,0xe1 = ldrexh r2, [r5] 0x9f,0x1f,0x97,0xe1 = ldrex r1, [r7] 0x9f,0x6f,0xb8,0xe1 = ldrexd r6, r7, [r8] 0xb0,0x80,0x7b,0x80 = ldrhthi r8, [r11], #-0 0xb0,0x80,0xfb,0x80 = ldrhthi r8, [r11], #0 0x84,0x2f,0xa0,0xe1 = lsl r2, r4, #31 0x84,0x20,0xa0,0xe1 = lsl r2, r4, #1 0x04,0x20,0xa0,0xe1 = mov r2, r4 0x84,0x40,0xa0,0xe1 = lsl r4, r4, #1 0x24,0x20,0xa0,0xe1 = lsr r2, r4, #32 0x24,0x21,0xa0,0xe1 = lsr r2, r4, #2 0x04,0x20,0xa0,0xe1 = mov r2, r4 0x24,0x41,0xa0,0xe1 = lsr r4, r4, #2 0x91,0x57,0x21,0xee = mcr p7, #1, r5, c1, c1, #4 0x91,0x57,0x21,0xfe = mcr2 p7, #1, r5, c1, c1, #4 0x91,0x57,0x21,0x9e = mcrls p7, #1, r5, c1, c1, #4 0xf1,0x57,0x44,0xec = mcrr p7, #15, r5, r4, c1 0xf1,0x57,0x44,0xfc = mcrr2 p7, #15, r5, r4, c1 0xf1,0x57,0x44,0xcc = mcrrgt p7, #15, r5, r4, c1 0x92,0x43,0x21,0xe0 = mla r1, r2, r3, r4 0x92,0x43,0x31,0xe0 = mlas r1, r2, r3, r4 0x92,0x43,0x21,0x10 = mlane r1, r2, r3, r4 0x92,0x43,0x31,0x10 = mlasne r1, r2, r3, r4 0x95,0x36,0x62,0xe0 = mls r2, r5, r6, r3 0x95,0x36,0x62,0x10 = mlsne r2, r5, r6, r3 0x07,0x30,0xa0,0xe3 = mov r3, #7 0xff,0x4e,0xa0,0xe3 = mov r4, #4080 0xff,0x58,0xa0,0xe3 = mov r5, #16711680 0xff,0x6f,0x0f,0xe3 = movw r6, #65535 0xff,0x9f,0x0f,0xe3 = movw r9, #65535 0x07,0x30,0xb0,0xe3 = movs r3, #7 0xff,0x4e,0xa0,0x03 = moveq r4, #4080 0xff,0x58,0xb0,0x03 = movseq r5, #16711680 0x03,0x20,0xa0,0xe1 = mov r2, r3 0x03,0x20,0xb0,0xe1 = movs r2, r3 0x03,0x20,0xa0,0x01 = moveq r2, r3 0x03,0x20,0xb0,0x01 = movseq r2, r3 0x08,0xc0,0xa0,0xe1 = mov r12, r8 0x03,0x20,0xa0,0xe1 = mov r2, r3 0x08,0xc0,0xa0,0xe1 = mov r12, r8 0x03,0x20,0xa0,0xe1 = mov r2, r3 0x08,0xc0,0xa0,0xe1 = mov r12, r8 0x03,0x20,0xa0,0xe1 = mov r2, r3 0x08,0xc0,0xa0,0xe1 = mov r12, r8 0x03,0x20,0xa0,0xe1 = mov r2, r3 0x07,0x30,0x40,0xe3 = movt r3, #7 0xff,0x6f,0x4f,0xe3 = movt r6, #65535 0xf0,0x4f,0x40,0x03 = movteq r4, #4080 0x92,0x1e,0x11,0xee = mrc p14, #0, r1, c1, c2, #4 0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6 0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4 0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1 0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6 0x11,0x57,0x54,0xec = mrrc p7, #1, r5, r4, c1 0x11,0x57,0x54,0xfc = mrrc2 p7, #1, r5, r4, c1 0x11,0x57,0x54,0x3c = mrrclo p7, #1, r5, r4, c1 0x00,0x80,0x0f,0xe1 = mrs r8, apsr 0x00,0x80,0x0f,0xe1 = mrs r8, apsr 0x00,0x80,0x4f,0xe1 = mrs r8, spsr 0x05,0xf0,0x28,0xe3 = msr apsr_nzcvq, #5 0x05,0xf0,0x24,0xe3 = msr apsr_g, #5 0x05,0xf0,0x28,0xe3 = msr apsr_nzcvq, #5 0x05,0xf0,0x28,0xe3 = msr apsr_nzcvq, #5 0x05,0xf0,0x2c,0xe3 = msr apsr_nzcvqg, #5 0x05,0xf0,0x29,0xe3 = msr cpsr_fc, #5 0x05,0xf0,0x21,0xe3 = msr cpsr_c, #5 0x05,0xf0,0x22,0xe3 = msr cpsr_x, #5 0x05,0xf0,0x29,0xe3 = msr cpsr_fc, #5 0x05,0xf0,0x29,0xe3 = msr cpsr_fc, #5 0x05,0xf0,0x2e,0xe3 = msr cpsr_fsx, #5 0x05,0xf0,0x69,0xe3 = msr spsr_fc, #5 0x05,0xf0,0x6f,0xe3 = msr spsr_fsxc, #5 0x05,0xf0,0x2f,0xe3 = msr cpsr_fsxc, #5 0x00,0xf0,0x28,0xe1 = msr apsr_nzcvq, r0 0x00,0xf0,0x24,0xe1 = msr apsr_g, r0 0x00,0xf0,0x28,0xe1 = msr apsr_nzcvq, r0 0x00,0xf0,0x28,0xe1 = msr apsr_nzcvq, r0 0x00,0xf0,0x2c,0xe1 = msr apsr_nzcvqg, r0 0x00,0xf0,0x29,0xe1 = msr cpsr_fc, r0 0x00,0xf0,0x21,0xe1 = msr cpsr_c, r0 0x00,0xf0,0x22,0xe1 = msr cpsr_x, r0 0x00,0xf0,0x29,0xe1 = msr cpsr_fc, r0 0x00,0xf0,0x29,0xe1 = msr cpsr_fc, r0 0x00,0xf0,0x2e,0xe1 = msr cpsr_fsx, r0 0x00,0xf0,0x69,0xe1 = msr spsr_fc, r0 0x00,0xf0,0x6f,0xe1 = msr spsr_fsxc, r0 0x00,0xf0,0x2f,0xe1 = msr cpsr_fsxc, r0 0x96,0x07,0x05,0xe0 = mul r5, r6, r7 0x96,0x07,0x15,0xe0 = muls r5, r6, r7 0x96,0x07,0x05,0xc0 = mulgt r5, r6, r7 0x96,0x07,0x15,0xd0 = mulsle r5, r6, r7 0x07,0x30,0xe0,0xe3 = mvn r3, #7 0xff,0x4e,0xe0,0xe3 = mvn r4, #4080 0xff,0x58,0xe0,0xe3 = mvn r5, #16711680 0x07,0x30,0xf0,0xe3 = mvns r3, #7 0xff,0x4e,0xe0,0x03 = mvneq r4, #4080 0xff,0x58,0xf0,0x03 = mvnseq r5, #16711680 0x03,0x20,0xe0,0xe1 = mvn r2, r3 0x03,0x20,0xf0,0xe1 = mvns r2, r3 0x86,0x59,0xe0,0xe1 = mvn r5, r6, lsl #19 0xa6,0x54,0xe0,0xe1 = mvn r5, r6, lsr #9 0x46,0x52,0xe0,0xe1 = mvn r5, r6, asr #4 0x66,0x53,0xe0,0xe1 = mvn r5, r6, ror #6 0x66,0x50,0xe0,0xe1 = mvn r5, r6, rrx 0x03,0x20,0xe0,0x01 = mvneq r2, r3 0x03,0x25,0xf0,0x01 = mvnseq r2, r3, lsl #10 0x16,0x57,0xe0,0xe1 = mvn r5, r6, lsl r7 0x36,0x57,0xf0,0xe1 = mvns r5, r6, lsr r7 0x56,0x57,0xe0,0xc1 = mvngt r5, r6, asr r7 0x76,0x57,0xf0,0xb1 = mvnslt r5, r6, ror r7 0x00,0x50,0x68,0xe2 = rsb r5, r8, #0 0x00,0xf0,0x20,0xe3 = nop 0x00,0xf0,0x20,0xe3 = nop 0x00,0xf0,0x20,0xc3 = nopgt 0x0f,0x4a,0x85,0xe3 = orr r4, r5, #61440 0x06,0x40,0x85,0xe1 = orr r4, r5, r6 0x86,0x42,0x85,0xe1 = orr r4, r5, r6, lsl #5 0xa6,0x42,0x85,0xe1 = orr r4, r5, r6, lsr #5 0xa6,0x42,0x85,0xe1 = orr r4, r5, r6, lsr #5 0xc6,0x42,0x85,0xe1 = orr r4, r5, r6, asr #5 0xe6,0x42,0x85,0xe1 = orr r4, r5, r6, ror #5 0x18,0x69,0x87,0xe1 = orr r6, r7, r8, lsl r9 0x38,0x69,0x87,0xe1 = orr r6, r7, r8, lsr r9 0x58,0x69,0x87,0xe1 = orr r6, r7, r8, asr r9 0x78,0x69,0x87,0xe1 = orr r6, r7, r8, ror r9 0x66,0x40,0x85,0xe1 = orr r4, r5, r6, rrx 0x0f,0x5a,0x85,0xe3 = orr r5, r5, #61440 0x05,0x40,0x84,0xe1 = orr r4, r4, r5 0x85,0x42,0x84,0xe1 = orr r4, r4, r5, lsl #5 0xa5,0x42,0x84,0xe1 = orr r4, r4, r5, lsr #5 0xa5,0x42,0x84,0xe1 = orr r4, r4, r5, lsr #5 0xc5,0x42,0x84,0xe1 = orr r4, r4, r5, asr #5 0xe5,0x42,0x84,0xe1 = orr r4, r4, r5, ror #5 0x17,0x69,0x86,0xe1 = orr r6, r6, r7, lsl r9 0x37,0x69,0x86,0xe1 = orr r6, r6, r7, lsr r9 0x57,0x69,0x86,0xe1 = orr r6, r6, r7, asr r9 0x77,0x69,0x86,0xe1 = orr r6, r6, r7, ror r9 0x65,0x40,0x84,0xe1 = orr r4, r4, r5, rrx 0x0f,0x4a,0x95,0x03 = orrseq r4, r5, #61440 0x06,0x40,0x85,0x11 = orrne r4, r5, r6 0x86,0x42,0x95,0x01 = orrseq r4, r5, r6, lsl #5 0x78,0x69,0x87,0x31 = orrlo r6, r7, r8, ror r9 0x66,0x40,0x95,0x81 = orrshi r4, r5, r6, rrx 0x0f,0x5a,0x85,0x23 = orrhs r5, r5, #61440 0x05,0x40,0x94,0x01 = orrseq r4, r4, r5 0x57,0x69,0x86,0x11 = orrne r6, r6, r7, asr r9 0x77,0x69,0x96,0xb1 = orrslt r6, r6, r7, ror r9 0x65,0x40,0x94,0xc1 = orrsgt r4, r4, r5, rrx 0x22,0x30,0x81,0xe1 = orr r3, r1, r2, lsr #32 0x42,0x30,0x81,0xe1 = orr r3, r1, r2, asr #32 0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3 0x93,0x2f,0x82,0xe6 = pkhbt r2, r2, r3, lsl #31 0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3 0x93,0x27,0x82,0xe6 = pkhbt r2, r2, r3, lsl #15 0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3 0xd3,0x2f,0x82,0xe6 = pkhtb r2, r2, r3, asr #31 0xd3,0x27,0x82,0xe6 = pkhtb r2, r2, r3, asr #15 // 0x04,0x70,0x9d,0xe4 = pop {r7} 0x80,0x07,0xbd,0xe8 = pop {r7, r8, r9, r10} #0x04,0x70,0x2d,0xe5 = push {r7} 0x80,0x07,0x2d,0xe9 = push {r7, r8, r9, r10} 0x52,0x10,0x03,0xe1 = qadd r1, r2, r3 0x52,0x10,0x03,0x11 = qaddne r1, r2, r3 0x13,0x1f,0x22,0xe6 = qadd16 r1, r2, r3 0x13,0x1f,0x22,0xc6 = qadd16gt r1, r2, r3 0x93,0x1f,0x22,0xe6 = qadd8 r1, r2, r3 0x93,0x1f,0x22,0xd6 = qadd8le r1, r2, r3 0x57,0x60,0x48,0xe1 = qdadd r6, r7, r8 0x57,0x60,0x48,0x81 = qdaddhi r6, r7, r8 0x57,0x60,0x68,0xe1 = qdsub r6, r7, r8 0x57,0x60,0x68,0x81 = qdsubhi r6, r7, r8 0x50,0x9f,0x2c,0xe6 = qsax r9, r12, r0 0x50,0x9f,0x2c,0x06 = qsaxeq r9, r12, r0 0x52,0x10,0x23,0xe1 = qsub r1, r2, r3 0x52,0x10,0x23,0x11 = qsubne r1, r2, r3 0x73,0x1f,0x22,0xe6 = qsub16 r1, r2, r3 0x73,0x1f,0x22,0xc6 = qsub16gt r1, r2, r3 0xf3,0x1f,0x22,0xe6 = qsub8 r1, r2, r3 0xf3,0x1f,0x22,0xd6 = qsub8le r1, r2, r3 0x32,0x1f,0xff,0xe6 = rbit r1, r2 0x32,0x1f,0xff,0x16 = rbitne r1, r2 0x39,0x1f,0xbf,0xe6 = rev r1, r9 0x35,0x1f,0xbf,0x16 = revne r1, r5 0xb3,0x8f,0xbf,0xe6 = rev16 r8, r3 0xb4,0xcf,0xbf,0x16 = rev16ne r12, r4 0xb9,0x4f,0xff,0xe6 = revsh r4, r9 0xb1,0x9f,0xff,0x16 = revshne r9, r1 0x00,0x0a,0x12,0xf8 = rfeda r2 0x00,0x0a,0x13,0xf9 = rfedb r3 0x00,0x0a,0x95,0xf8 = rfeia r5 0x00,0x0a,0x96,0xf9 = rfeib r6 0x00,0x0a,0x34,0xf8 = rfeda r4! 0x00,0x0a,0x37,0xf9 = rfedb r7! 0x00,0x0a,0xb9,0xf8 = rfeia r9! 0x00,0x0a,0xb8,0xf9 = rfeib r8! 0x00,0x0a,0x12,0xf8 = rfeda r2 0x00,0x0a,0x13,0xf9 = rfedb r3 0x00,0x0a,0x95,0xf8 = rfeia r5 0x00,0x0a,0x96,0xf9 = rfeib r6 0x00,0x0a,0x34,0xf8 = rfeda r4! 0x00,0x0a,0x37,0xf9 = rfedb r7! 0x00,0x0a,0xb9,0xf8 = rfeia r9! 0x00,0x0a,0xb8,0xf9 = rfeib r8! 0x00,0x0a,0x91,0xf8 = rfeia r1 0x00,0x0a,0xb1,0xf8 = rfeia r1! 0xe4,0x2f,0xa0,0xe1 = ror r2, r4, #31 0xe4,0x20,0xa0,0xe1 = ror r2, r4, #1 0x04,0x20,0xa0,0xe1 = mov r2, r4 0xe4,0x40,0xa0,0xe1 = ror r4, r4, #1 0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #61440 0x06,0x40,0x65,0xe0 = rsb r4, r5, r6 0x86,0x42,0x65,0xe0 = rsb r4, r5, r6, lsl #5 0xa6,0x42,0x65,0x30 = rsblo r4, r5, r6, lsr #5 0xa6,0x42,0x65,0xe0 = rsb r4, r5, r6, lsr #5 0xc6,0x42,0x65,0xe0 = rsb r4, r5, r6, asr #5 0xe6,0x42,0x65,0xe0 = rsb r4, r5, r6, ror #5 0x18,0x69,0x67,0xe0 = rsb r6, r7, r8, lsl r9 0x38,0x69,0x67,0xe0 = rsb r6, r7, r8, lsr r9 0x58,0x69,0x67,0xe0 = rsb r6, r7, r8, asr r9 0x78,0x69,0x67,0xd0 = rsble r6, r7, r8, ror r9 0x66,0x40,0x65,0xe0 = rsb r4, r5, r6, rrx 0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #61440 0x05,0x40,0x64,0xe0 = rsb r4, r4, r5 0x85,0x42,0x64,0xe0 = rsb r4, r4, r5, lsl #5 0xa5,0x42,0x64,0xe0 = rsb r4, r4, r5, lsr #5 0xa5,0x42,0x64,0x10 = rsbne r4, r4, r5, lsr #5 0xc5,0x42,0x64,0xe0 = rsb r4, r4, r5, asr #5 0xe5,0x42,0x64,0xe0 = rsb r4, r4, r5, ror #5 0x17,0x69,0x66,0xc0 = rsbgt r6, r6, r7, lsl r9 0x37,0x69,0x66,0xe0 = rsb r6, r6, r7, lsr r9 0x57,0x69,0x66,0xe0 = rsb r6, r6, r7, asr r9 0x77,0x69,0x66,0xe0 = rsb r6, r6, r7, ror r9 0x65,0x40,0x64,0xe0 = rsb r4, r4, r5, rrx 0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #61440 0x06,0x40,0xe5,0xe0 = rsc r4, r5, r6 0x86,0x42,0xe5,0xe0 = rsc r4, r5, r6, lsl #5 0xa6,0x42,0xe5,0x30 = rsclo r4, r5, r6, lsr #5 0xa6,0x42,0xe5,0xe0 = rsc r4, r5, r6, lsr #5 0xc6,0x42,0xe5,0xe0 = rsc r4, r5, r6, asr #5 0xe6,0x42,0xe5,0xe0 = rsc r4, r5, r6, ror #5 0x18,0x69,0xe7,0xe0 = rsc r6, r7, r8, lsl r9 0x38,0x69,0xe7,0xe0 = rsc r6, r7, r8, lsr r9 0x58,0x69,0xe7,0xe0 = rsc r6, r7, r8, asr r9 0x78,0x69,0xe7,0xd0 = rscle r6, r7, r8, ror r9 0xfe,0x1e,0xf8,0xe2 = rscs r1, r8, #4064 0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #61440 0x05,0x40,0xe4,0xe0 = rsc r4, r4, r5 0x85,0x42,0xe4,0xe0 = rsc r4, r4, r5, lsl #5 0xa5,0x42,0xe4,0xe0 = rsc r4, r4, r5, lsr #5 0xa5,0x42,0xe4,0x10 = rscne r4, r4, r5, lsr #5 0xc5,0x42,0xe4,0xe0 = rsc r4, r4, r5, asr #5 0xe5,0x42,0xe4,0xe0 = rsc r4, r4, r5, ror #5 0x17,0x69,0xe6,0xc0 = rscgt r6, r6, r7, lsl r9 0x37,0x69,0xe6,0xe0 = rsc r6, r6, r7, lsr r9 0x57,0x69,0xe6,0xe0 = rsc r6, r6, r7, asr r9 0x77,0x69,0xe6,0xe0 = rsc r6, r6, r7, ror r9 0x61,0x00,0xa0,0xe1 = rrx r0, r1 0x6f,0xd0,0xa0,0xe1 = rrx sp, pc 0x6e,0xf0,0xa0,0xe1 = rrx pc, lr 0x6d,0xe0,0xa0,0xe1 = rrx lr, sp 0x61,0x00,0xb0,0xe1 = rrxs r0, r1 0x6f,0xd0,0xb0,0xe1 = rrxs sp, pc 0x6e,0xf0,0xb0,0xe1 = rrxs pc, lr 0x6d,0xe0,0xb0,0xe1 = rrxs lr, sp 0x13,0x1f,0x12,0xe6 = sadd16 r1, r2, r3 0x13,0x1f,0x12,0xc6 = sadd16gt r1, r2, r3 0x93,0x1f,0x12,0xe6 = sadd8 r1, r2, r3 0x93,0x1f,0x12,0xd6 = sadd8le r1, r2, r3 0x30,0x9f,0x1c,0xe6 = sasx r9, r12, r0 0x30,0x9f,0x1c,0x06 = sasxeq r9, r12, r0 0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #61440 0x06,0x40,0xc5,0xe0 = sbc r4, r5, r6 0x86,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsl #5 0xa6,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsr #5 0xa6,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsr #5 0xc6,0x42,0xc5,0xe0 = sbc r4, r5, r6, asr #5 0xe6,0x42,0xc5,0xe0 = sbc r4, r5, r6, ror #5 0x18,0x69,0xc7,0xe0 = sbc r6, r7, r8, lsl r9 0x38,0x69,0xc7,0xe0 = sbc r6, r7, r8, lsr r9 0x58,0x69,0xc7,0xe0 = sbc r6, r7, r8, asr r9 0x78,0x69,0xc7,0xe0 = sbc r6, r7, r8, ror r9 0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #61440 0x05,0x40,0xc4,0xe0 = sbc r4, r4, r5 0x85,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsl #5 0xa5,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsr #5 0xa5,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsr #5 0xc5,0x42,0xc4,0xe0 = sbc r4, r4, r5, asr #5 0xe5,0x42,0xc4,0xe0 = sbc r4, r4, r5, ror #5 0x17,0x69,0xc6,0xe0 = sbc r6, r6, r7, lsl r9 0x37,0x69,0xc6,0xe0 = sbc r6, r6, r7, lsr r9 0x57,0x69,0xc6,0xe0 = sbc r6, r6, r7, asr r9 0x77,0x69,0xc6,0xe0 = sbc r6, r6, r7, ror r9 0x55,0x48,0xa0,0xe7 = sbfx r4, r5, #16, #1 0x55,0x48,0xaf,0xc7 = sbfxgt r4, r5, #16, #16 0xb1,0x9f,0x82,0xe6 = sel r9, r2, r1 0xb1,0x9f,0x82,0x16 = selne r9, r2, r1 0x00,0x02,0x01,0xf1 = setend be 0x00,0x02,0x01,0xf1 = setend be 0x00,0x00,0x01,0xf1 = setend le 0x00,0x00,0x01,0xf1 = setend le 0x04,0xf0,0x20,0xe3 = sev 0x04,0xf0,0x20,0x03 = seveq 0x12,0x4f,0x38,0xe6 = shadd16 r4, r8, r2 0x12,0x4f,0x38,0xc6 = shadd16gt r4, r8, r2 0x92,0x4f,0x38,0xe6 = shadd8 r4, r8, r2 0x92,0x4f,0x38,0xc6 = shadd8gt r4, r8, r2 0x32,0x4f,0x38,0xe6 = shasx r4, r8, r2 0x32,0x4f,0x38,0xc6 = shasxgt r4, r8, r2 0x72,0x4f,0x38,0xe6 = shsub16 r4, r8, r2 0x72,0x4f,0x38,0xc6 = shsub16gt r4, r8, r2 0xf2,0x4f,0x38,0xe6 = shsub8 r4, r8, r2 0xf2,0x4f,0x38,0xc6 = shsub8gt r4, r8, r2 0x81,0x09,0x03,0xe1 = smlabb r3, r1, r9, r0 0xc6,0x14,0x05,0xe1 = smlabt r5, r6, r4, r1 0xa2,0x23,0x04,0xe1 = smlatb r4, r2, r3, r2 0xe3,0x48,0x08,0xe1 = smlatt r8, r3, r8, r4 0x81,0x09,0x03,0xa1 = smlabbge r3, r1, r9, r0 0xc6,0x14,0x05,0xd1 = smlabtle r5, r6, r4, r1 0xa2,0x23,0x04,0x11 = smlatbne r4, r2, r3, r2 0xe3,0x48,0x08,0x01 = smlatteq r8, r3, r8, r4 0x13,0x85,0x02,0xe7 = smlad r2, r3, r5, r8 0x33,0x85,0x02,0xe7 = smladx r2, r3, r5, r8 0x13,0x85,0x02,0x07 = smladeq r2, r3, r5, r8 0x33,0x85,0x02,0x87 = smladxhi r2, r3, r5, r8 0x95,0x28,0xe3,0xe0 = smlal r2, r3, r5, r8 0x95,0x28,0xf3,0xe0 = smlals r2, r3, r5, r8 0x95,0x28,0xe3,0x00 = smlaleq r2, r3, r5, r8 0x95,0x28,0xf3,0x80 = smlalshi r2, r3, r5, r8 0x89,0x30,0x41,0xe1 = smlalbb r3, r1, r9, r0 0xc4,0x51,0x46,0xe1 = smlalbt r5, r6, r4, r1 0xa3,0x42,0x42,0xe1 = smlaltb r4, r2, r3, r2 0xe8,0x84,0x43,0xe1 = smlaltt r8, r3, r8, r4 0x89,0x30,0x41,0xa1 = smlalbbge r3, r1, r9, r0 0xc4,0x51,0x46,0xd1 = smlalbtle r5, r6, r4, r1 0xa3,0x42,0x42,0x11 = smlaltbne r4, r2, r3, r2 0xe8,0x84,0x43,0x01 = smlaltteq r8, r3, r8, r4 0x15,0x28,0x43,0xe7 = smlald r2, r3, r5, r8 0x35,0x28,0x43,0xe7 = smlaldx r2, r3, r5, r8 0x15,0x28,0x43,0x07 = smlaldeq r2, r3, r5, r8 0x35,0x28,0x43,0x87 = smlaldxhi r2, r3, r5, r8 0x83,0x8a,0x22,0xe1 = smlawb r2, r3, r10, r8 0xc3,0x95,0x28,0xe1 = smlawt r8, r3, r5, r9 0x87,0x85,0x22,0x01 = smlawbeq r2, r7, r5, r8 0xc3,0x80,0x21,0x81 = smlawthi r1, r3, r0, r8 0x53,0x85,0x02,0xe7 = smlsd r2, r3, r5, r8 0x73,0x85,0x02,0xe7 = smlsdx r2, r3, r5, r8 0x53,0x85,0x02,0x07 = smlsdeq r2, r3, r5, r8 0x73,0x85,0x02,0x87 = smlsdxhi r2, r3, r5, r8 0x55,0x21,0x49,0xe7 = smlsld r2, r9, r5, r1 0x72,0x48,0x4b,0xe7 = smlsldx r4, r11, r2, r8 0x55,0x86,0x42,0x07 = smlsldeq r8, r2, r5, r6 0x73,0x18,0x40,0x87 = smlsldxhi r1, r0, r3, r8 0x12,0x43,0x51,0xe7 = smmla r1, r2, r3, r4 0x33,0x12,0x54,0xe7 = smmlar r4, r3, r2, r1 0x12,0x43,0x51,0x37 = smmlalo r1, r2, r3, r4 0x33,0x12,0x54,0x27 = smmlarhs r4, r3, r2, r1 0xd2,0x43,0x51,0xe7 = smmls r1, r2, r3, r4 0xf3,0x12,0x54,0xe7 = smmlsr r4, r3, r2, r1 0xd2,0x43,0x51,0x37 = smmlslo r1, r2, r3, r4 0xf3,0x12,0x54,0x27 = smmlsrhs r4, r3, r2, r1 0x13,0xf4,0x52,0xe7 = smmul r2, r3, r4 0x32,0xf1,0x53,0xe7 = smmulr r3, r2, r1 0x13,0xf4,0x52,0x37 = smmullo r2, r3, r4 0x32,0xf1,0x53,0x27 = smmulrhs r3, r2, r1 0x13,0xf4,0x02,0xe7 = smuad r2, r3, r4 0x32,0xf1,0x03,0xe7 = smuadx r3, r2, r1 0x13,0xf4,0x02,0xb7 = smuadlt r2, r3, r4 0x32,0xf1,0x03,0xa7 = smuadxge r3, r2, r1 0x89,0x00,0x63,0xe1 = smulbb r3, r9, r0 0xc4,0x01,0x65,0xe1 = smulbt r5, r4, r1 0xa2,0x02,0x64,0xe1 = smultb r4, r2, r2 0xe3,0x04,0x68,0xe1 = smultt r8, r3, r4 0x89,0x00,0x61,0xa1 = smulbbge r1, r9, r0 0xc6,0x04,0x65,0xd1 = smulbtle r5, r6, r4 0xa3,0x02,0x62,0x11 = smultbne r2, r3, r2 0xe3,0x04,0x68,0x01 = smultteq r8, r3, r4 0x90,0x31,0xc9,0xe0 = smull r3, r9, r0, r1 0x90,0x32,0xd9,0xe0 = smulls r3, r9, r0, r2 0x94,0x85,0xc3,0x00 = smulleq r8, r3, r4, r5 0x94,0x83,0xd3,0x00 = smullseq r8, r3, r4, r3 0xa9,0x00,0x23,0xe1 = smulwb r3, r9, r0 0xe9,0x02,0x23,0xe1 = smulwt r3, r9, r2 0x50,0xf1,0x03,0xe7 = smusd r3, r0, r1 0x79,0xf2,0x03,0xe7 = smusdx r3, r9, r2 0x53,0xf2,0x08,0x07 = smusdeq r8, r3, r2 0x74,0xf3,0x07,0x17 = smusdxne r7, r4, r3 0x05,0x05,0x4d,0xf8 = srsda sp, #5 0x01,0x05,0x4d,0xf9 = srsdb sp, #1 0x00,0x05,0xcd,0xf8 = srsia sp, #0 0x0f,0x05,0xcd,0xf9 = srsib sp, #15 0x1f,0x05,0x6d,0xf8 = srsda sp!, #31 0x13,0x05,0x6d,0xf9 = srsdb sp!, #19 0x02,0x05,0xed,0xf8 = srsia sp!, #2 0x0e,0x05,0xed,0xf9 = srsib sp!, #14 0x0b,0x05,0xcd,0xf9 = srsib sp, #11 0x0a,0x05,0xcd,0xf8 = srsia sp, #10 0x09,0x05,0x4d,0xf9 = srsdb sp, #9 0x05,0x05,0x4d,0xf8 = srsda sp, #5 0x05,0x05,0xed,0xf9 = srsib sp!, #5 0x05,0x05,0xed,0xf8 = srsia sp!, #5 0x05,0x05,0x6d,0xf9 = srsdb sp!, #5 0x05,0x05,0x6d,0xf8 = srsda sp!, #5 0x05,0x05,0xcd,0xf8 = srsia sp, #5 0x05,0x05,0xed,0xf8 = srsia sp!, #5 0x05,0x05,0x4d,0xf8 = srsda sp, #5 0x01,0x05,0x4d,0xf9 = srsdb sp, #1 0x00,0x05,0xcd,0xf8 = srsia sp, #0 0x0f,0x05,0xcd,0xf9 = srsib sp, #15 0x1f,0x05,0x6d,0xf8 = srsda sp!, #31 0x13,0x05,0x6d,0xf9 = srsdb sp!, #19 0x02,0x05,0xed,0xf8 = srsia sp!, #2 0x0e,0x05,0xed,0xf9 = srsib sp!, #14 0x0b,0x05,0xcd,0xf9 = srsib sp, #11 0x0a,0x05,0xcd,0xf8 = srsia sp, #10 0x09,0x05,0x4d,0xf9 = srsdb sp, #9 0x05,0x05,0x4d,0xf8 = srsda sp, #5 0x05,0x05,0xed,0xf9 = srsib sp!, #5 0x05,0x05,0xed,0xf8 = srsia sp!, #5 0x05,0x05,0x6d,0xf9 = srsdb sp!, #5 0x05,0x05,0x6d,0xf8 = srsda sp!, #5 0x05,0x05,0xcd,0xf8 = srsia sp, #5 0x05,0x05,0xed,0xf8 = srsia sp!, #5 0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10 0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10 0x9a,0x8f,0xa0,0xe6 = ssat r8, #1, r10, lsl #31 0x5a,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #32 0xda,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #1 0x37,0x2f,0xa0,0xe6 = ssat16 r2, #1, r7 0x35,0x3f,0xaf,0xe6 = ssat16 r3, #16, r5 0x54,0x2f,0x13,0xe6 = ssax r2, r3, r4 0x54,0x2f,0x13,0xb6 = ssaxlt r2, r3, r4 0x76,0x1f,0x10,0xe6 = ssub16 r1, r0, r6 0x72,0x5f,0x13,0x16 = ssub16ne r5, r3, r2 0xf4,0x9f,0x12,0xe6 = ssub8 r9, r2, r4 0xf2,0x5f,0x11,0x06 = ssub8eq r5, r1, r2 0x01,0x80,0x81,0xfd = stc2 p0, c8, [r1, #4] 0x00,0x71,0x82,0xfd = stc2 p1, c7, [r2] 0x38,0x62,0x03,0xfd = stc2 p2, c6, [r3, #-224] 0x1e,0x53,0x24,0xfd = stc2 p3, c5, [r4, #-120]! 0x04,0x44,0xa5,0xfc = stc2 p4, c4, [r5], #16 0x12,0x35,0x26,0xfc = stc2 p5, c3, [r6], #-72 0x01,0x26,0xc7,0xfd = stc2l p6, c2, [r7, #4] 0x00,0x17,0xc8,0xfd = stc2l p7, c1, [r8] 0x38,0x08,0x49,0xfd = stc2l p8, c0, [r9, #-224] 0x1e,0x19,0x6a,0xfd = stc2l p9, c1, [r10, #-120]! 0x04,0x20,0xeb,0xfc = stc2l p0, c2, [r11], #16 0x12,0x31,0x6c,0xfc = stc2l p1, c3, [r12], #-72 0x01,0x4c,0x80,0xed = stc p12, c4, [r0, #4] 0x00,0x5d,0x81,0xed = stc p13, c5, [r1] 0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-224] 0x1e,0x7f,0x23,0xed = stc p15, c7, [r3, #-120]! 0x04,0x85,0xa4,0xec = stc p5, c8, [r4], #16 0x12,0x94,0x25,0xec = stc p4, c9, [r5], #-72 0x01,0xa3,0xc6,0xed = stcl p3, c10, [r6, #4] 0x00,0xb2,0xc7,0xed = stcl p2, c11, [r7] 0x38,0xc1,0x48,0xed = stcl p1, c12, [r8, #-224] 0x1e,0xd0,0x69,0xed = stcl p0, c13, [r9, #-120]! 0x04,0xe6,0xea,0xec = stcl p6, c14, [r10], #16 0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-72 0x01,0x4c,0x80,0x3d = stclo p12, c4, [r0, #4] 0x00,0x5d,0x81,0x8d = stchi p13, c5, [r1] 0x38,0x6e,0x02,0x2d = stchs p14, c6, [r2, #-224] 0x1e,0x7f,0x23,0x3d = stclo p15, c7, [r3, #-120]! 0x04,0x85,0xa4,0x0c = stceq p5, c8, [r4], #16 0x12,0x94,0x25,0xcc = stcgt p4, c9, [r5], #-72 0x01,0xa3,0xc6,0xbd = stcllt p3, c10, [r6, #4] 0x00,0xb2,0xc7,0xad = stclge p2, c11, [r7] 0x38,0xc1,0x48,0xdd = stclle p1, c12, [r8, #-224] 0x1e,0xd0,0x69,0x1d = stclne p0, c13, [r9, #-120]! 0x04,0xe6,0xea,0x0c = stcleq p6, c14, [r10], #16 0x12,0xf7,0x6b,0x8c = stclhi p7, c15, [r11], #-72 0x19,0x82,0x81,0xfc = stc2 p2, c8, [r1], {25} 0x7a,0x20,0x82,0xe8 = stm r2, {r1, r3, r4, r5, r6, sp} 0x7a,0x40,0x83,0xe8 = stm r3, {r1, r3, r4, r5, r6, lr} 0x7a,0x20,0x84,0xe9 = stmib r4, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0x05,0xe8 = stmda r5, {r1, r3, r4, r5, r6, sp} 0x7a,0x01,0x06,0xe9 = stmdb r6, {r1, r3, r4, r5, r6, r8} 0x7a,0x20,0x0d,0xe9 = stmdb sp, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0xa8,0xe8 = stm r8!, {r1, r3, r4, r5, r6, sp} 0x7a,0x20,0xa9,0xe9 = stmib sb!, {r1, r3, r4, r5, r6, sp} 0x7a,0x00,0x2d,0xe8 = stmda sp!, {r1, r3, r4, r5, r6} 0xa2,0x20,0x20,0xe9 = stmdb r0!, {r1, r5, r7, sp} 0x93,0x1f,0xc4,0xe1 = strexb r1, r3, [r4] 0x92,0x4f,0xe5,0xe1 = strexh r4, r2, [r5] 0x91,0x2f,0x87,0xe1 = strex r2, r1, [r7] 0x92,0x6f,0xa8,0xe1 = strexd r6, r2, r3, [r8] 0x00,0x30,0x2a,0x55 = strpl r3, [r10, #-0]! 0x00,0x30,0xaa,0x55 = strpl r3, [r10, #0]! 0x0f,0x4a,0x45,0xe2 = sub r4, r5, #61440 0x06,0x40,0x45,0xe0 = sub r4, r5, r6 0x86,0x42,0x45,0xe0 = sub r4, r5, r6, lsl #5 0xa6,0x42,0x45,0xe0 = sub r4, r5, r6, lsr #5 0xa6,0x42,0x45,0xe0 = sub r4, r5, r6, lsr #5 0xc6,0x42,0x45,0xe0 = sub r4, r5, r6, asr #5 0xe6,0x42,0x45,0xe0 = sub r4, r5, r6, ror #5 0x18,0x69,0x47,0xe0 = sub r6, r7, r8, lsl r9 0x38,0x69,0x47,0xe0 = sub r6, r7, r8, lsr r9 0x58,0x69,0x47,0xe0 = sub r6, r7, r8, asr r9 0x78,0x69,0x47,0xe0 = sub r6, r7, r8, ror r9 0x0f,0x5a,0x45,0xe2 = sub r5, r5, #61440 0x05,0x40,0x44,0xe0 = sub r4, r4, r5 0x85,0x42,0x44,0xe0 = sub r4, r4, r5, lsl #5 0xa5,0x42,0x44,0xe0 = sub r4, r4, r5, lsr #5 0xa5,0x42,0x44,0xe0 = sub r4, r4, r5, lsr #5 0xc5,0x42,0x44,0xe0 = sub r4, r4, r5, asr #5 0xe5,0x42,0x44,0xe0 = sub r4, r4, r5, ror #5 0x17,0x69,0x46,0xe0 = sub r6, r6, r7, lsl r9 0x37,0x69,0x46,0xe0 = sub r6, r6, r7, lsr r9 0x57,0x69,0x46,0xe0 = sub r6, r6, r7, asr r9 0x77,0x69,0x46,0xe0 = sub r6, r6, r7, ror r9 0x22,0x30,0x41,0xe0 = sub r3, r1, r2, lsr #32 0x42,0x30,0x41,0xe0 = sub r3, r1, r2, asr #32 0x10,0x00,0x00,0xef = svc #16 0x00,0x00,0x00,0xef = svc #0 0xff,0xff,0xff,0xef = svc #16777215 0x92,0x10,0x03,0xe1 = swp r1, r2, [r3] 0x94,0x40,0x06,0xe1 = swp r4, r4, [r6] 0x91,0x50,0x49,0xe1 = swpb r5, r1, [r9] 0x74,0x20,0xa3,0xe6 = sxtab r2, r3, r4 0x76,0x40,0xa5,0xe6 = sxtab r4, r5, r6 0x79,0x64,0xa2,0xb6 = sxtablt r6, r2, r9, ror #8 0x74,0x58,0xa1,0xe6 = sxtab r5, r1, r4, ror #16 0x73,0x7c,0xa8,0xe6 = sxtab r7, r8, r3, ror #24 0x74,0x00,0x81,0xa6 = sxtab16ge r0, r1, r4 0x77,0x60,0x82,0xe6 = sxtab16 r6, r2, r7 0x78,0x34,0x85,0xe6 = sxtab16 r3, r5, r8, ror #8 0x71,0x38,0x82,0xe6 = sxtab16 r3, r2, r1, ror #16 0x73,0x1c,0x82,0x06 = sxtab16eq r1, r2, r3, ror #24 0x79,0x10,0xb3,0xe6 = sxtah r1, r3, r9 0x76,0x60,0xb1,0x86 = sxtahhi r6, r1, r6 0x73,0x34,0xb8,0xe6 = sxtah r3, r8, r3, ror #8 0x74,0x28,0xb2,0x36 = sxtahlo r2, r2, r4, ror #16 0x73,0x9c,0xb3,0xe6 = sxtah r9, r3, r3, ror #24 0x74,0x20,0xaf,0xa6 = sxtbge r2, r4 0x76,0x50,0xaf,0xe6 = sxtb r5, r6 0x79,0x64,0xaf,0xe6 = sxtb r6, r9, ror #8 0x71,0x58,0xaf,0x36 = sxtblo r5, r1, ror #16 0x73,0x8c,0xaf,0xe6 = sxtb r8, r3, ror #24 0x74,0x10,0x8f,0xe6 = sxtb16 r1, r4 0x77,0x60,0x8f,0xe6 = sxtb16 r6, r7 0x75,0x34,0x8f,0x26 = sxtb16hs r3, r5, ror #8 0x71,0x38,0x8f,0xe6 = sxtb16 r3, r1, ror #16 0x73,0x2c,0x8f,0xa6 = sxtb16ge r2, r3, ror #24 0x79,0x30,0xbf,0x16 = sxthne r3, r9 0x76,0x10,0xbf,0xe6 = sxth r1, r6 0x78,0x34,0xbf,0xe6 = sxth r3, r8, ror #8 0x72,0x28,0xbf,0xd6 = sxthle r2, r2, ror #16 0x73,0x9c,0xbf,0xe6 = sxth r9, r3, ror #24 0x0f,0x0a,0x35,0xe3 = teq r5, #61440 0x05,0x00,0x34,0xe1 = teq r4, r5 0x85,0x02,0x34,0xe1 = teq r4, r5, lsl #5 0xa5,0x02,0x34,0xe1 = teq r4, r5, lsr #5 0xa5,0x02,0x34,0xe1 = teq r4, r5, lsr #5 0xc5,0x02,0x34,0xe1 = teq r4, r5, asr #5 0xe5,0x02,0x34,0xe1 = teq r4, r5, ror #5 0x17,0x09,0x36,0xe1 = teq r6, r7, lsl r9 0x37,0x09,0x36,0xe1 = teq r6, r7, lsr r9 0x57,0x09,0x36,0xe1 = teq r6, r7, asr r9 0x77,0x09,0x36,0xe1 = teq r6, r7, ror r9 0x0f,0x0a,0x15,0xe3 = tst r5, #61440 0x05,0x00,0x14,0xe1 = tst r4, r5 0x85,0x02,0x14,0xe1 = tst r4, r5, lsl #5 0xa5,0x02,0x14,0xe1 = tst r4, r5, lsr #5 0xa5,0x02,0x14,0xe1 = tst r4, r5, lsr #5 0xc5,0x02,0x14,0xe1 = tst r4, r5, asr #5 0xe5,0x02,0x14,0xe1 = tst r4, r5, ror #5 0x17,0x09,0x16,0xe1 = tst r6, r7, lsl r9 0x37,0x09,0x16,0xe1 = tst r6, r7, lsr r9 0x57,0x09,0x16,0xe1 = tst r6, r7, asr r9 0x77,0x09,0x16,0xe1 = tst r6, r7, ror r9 0x13,0x1f,0x52,0xe6 = uadd16 r1, r2, r3 0x13,0x1f,0x52,0xc6 = uadd16gt r1, r2, r3 0x93,0x1f,0x52,0xe6 = uadd8 r1, r2, r3 0x93,0x1f,0x52,0xd6 = uadd8le r1, r2, r3 0x30,0x9f,0x5c,0xe6 = uasx r9, r12, r0 0x30,0x9f,0x5c,0x06 = uasxeq r9, r12, r0 0x55,0x48,0xe0,0xe7 = ubfx r4, r5, #16, #1 0x55,0x48,0xef,0xc7 = ubfxgt r4, r5, #16, #16 0x12,0x4f,0x78,0xe6 = uhadd16 r4, r8, r2 0x12,0x4f,0x78,0xc6 = uhadd16gt r4, r8, r2 0x92,0x4f,0x78,0xe6 = uhadd8 r4, r8, r2 0x92,0x4f,0x78,0xc6 = uhadd8gt r4, r8, r2 0x32,0x4f,0x78,0xe6 = uhasx r4, r8, r2 0x32,0x4f,0x78,0xc6 = uhasxgt r4, r8, r2 0x72,0x4f,0x78,0xe6 = uhsub16 r4, r8, r2 0x72,0x4f,0x78,0xc6 = uhsub16gt r4, r8, r2 0xf2,0x4f,0x78,0xe6 = uhsub8 r4, r8, r2 0xf2,0x4f,0x78,0xc6 = uhsub8gt r4, r8, r2 0x95,0x36,0x44,0xe0 = umaal r3, r4, r5, r6 0x95,0x36,0x44,0xb0 = umaallt r3, r4, r5, r6 0x96,0x28,0xa4,0xe0 = umlal r2, r4, r6, r8 0x92,0x66,0xa1,0xc0 = umlalgt r6, r1, r2, r6 0x92,0x23,0xb9,0xe0 = umlals r2, r9, r2, r3 0x91,0x32,0xb5,0x00 = umlalseq r3, r5, r1, r2 0x96,0x28,0x84,0xe0 = umull r2, r4, r6, r8 0x92,0x66,0x81,0xc0 = umullgt r6, r1, r2, r6 0x92,0x23,0x99,0xe0 = umulls r2, r9, r2, r3 0x91,0x32,0x95,0x00 = umullseq r3, r5, r1, r2 0x13,0x1f,0x62,0xe6 = uqadd16 r1, r2, r3 0x19,0x4f,0x67,0xc6 = uqadd16gt r4, r7, r9 0x98,0x3f,0x64,0xe6 = uqadd8 r3, r4, r8 0x92,0x8f,0x61,0xd6 = uqadd8le r8, r1, r2 0x31,0x2f,0x64,0xe6 = uqasx r2, r4, r1 0x39,0x5f,0x62,0x86 = uqasxhi r5, r2, r9 0x57,0x1f,0x63,0xe6 = uqsax r1, r3, r7 0x52,0x3f,0x66,0xe6 = uqsax r3, r6, r2 0x73,0x1f,0x65,0xe6 = uqsub16 r1, r5, r3 0x75,0x3f,0x62,0xc6 = uqsub16gt r3, r2, r5 0xf4,0x2f,0x61,0xe6 = uqsub8 r2, r1, r4 0xf9,0x4f,0x66,0xd6 = uqsub8le r4, r6, r9 0x11,0xf4,0x82,0xe7 = usad8 r2, r1, r4 0x16,0xf9,0x84,0xd7 = usad8le r4, r6, r9 0x15,0x73,0x81,0xe7 = usada8 r1, r5, r3, r7 0x12,0x15,0x83,0xc7 = usada8gt r3, r2, r5, r1 0x1a,0x80,0xe1,0xe6 = usat r8, #1, r10 0x1a,0x80,0xe4,0xe6 = usat r8, #4, r10 0x9a,0x8f,0xe5,0xe6 = usat r8, #5, r10, lsl #31 0x5a,0x80,0xff,0xe6 = usat r8, #31, r10, asr #32 0xda,0x80,0xf0,0xe6 = usat r8, #16, r10, asr #1 0x37,0x2f,0xe2,0xe6 = usat16 r2, #2, r7 0x35,0x3f,0xef,0xe6 = usat16 r3, #15, r5 0x54,0x2f,0x53,0xe6 = usax r2, r3, r4 0x54,0x2f,0x53,0x16 = usaxne r2, r3, r4 0x77,0x4f,0x52,0xe6 = usub16 r4, r2, r7 0x73,0x1f,0x51,0x86 = usub16hi r1, r1, r3 0xf5,0x1f,0x58,0xe6 = usub8 r1, r8, r5 0xf3,0x9f,0x52,0xd6 = usub8le r9, r2, r3 0x74,0x20,0xe3,0xe6 = uxtab r2, r3, r4 0x76,0x40,0xe5,0xe6 = uxtab r4, r5, r6 0x79,0x64,0xe2,0xb6 = uxtablt r6, r2, r9, ror #8 0x74,0x58,0xe1,0xe6 = uxtab r5, r1, r4, ror #16 0x73,0x7c,0xe8,0xe6 = uxtab r7, r8, r3, ror #24 0x74,0x00,0xc1,0xa6 = uxtab16ge r0, r1, r4 0x77,0x60,0xc2,0xe6 = uxtab16 r6, r2, r7 0x78,0x34,0xc5,0xe6 = uxtab16 r3, r5, r8, ror #8 0x71,0x38,0xc2,0xe6 = uxtab16 r3, r2, r1, ror #16 0x73,0x1c,0xc2,0x06 = uxtab16eq r1, r2, r3, ror #24 0x79,0x10,0xf3,0xe6 = uxtah r1, r3, r9 0x76,0x60,0xf1,0x86 = uxtahhi r6, r1, r6 0x73,0x34,0xf8,0xe6 = uxtah r3, r8, r3, ror #8 0x74,0x28,0xf2,0x36 = uxtahlo r2, r2, r4, ror #16 0x73,0x9c,0xf3,0xe6 = uxtah r9, r3, r3, ror #24 0x74,0x20,0xef,0xa6 = uxtbge r2, r4 0x76,0x50,0xef,0xe6 = uxtb r5, r6 0x79,0x64,0xef,0xe6 = uxtb r6, r9, ror #8 0x71,0x58,0xef,0x36 = uxtblo r5, r1, ror #16 0x73,0x8c,0xef,0xe6 = uxtb r8, r3, ror #24 0x74,0x10,0xcf,0xe6 = uxtb16 r1, r4 0x77,0x60,0xcf,0xe6 = uxtb16 r6, r7 0x75,0x34,0xcf,0x26 = uxtb16hs r3, r5, ror #8 0x71,0x38,0xcf,0xe6 = uxtb16 r3, r1, ror #16 0x73,0x2c,0xcf,0xa6 = uxtb16ge r2, r3, ror #24 0x79,0x30,0xff,0x16 = uxthne r3, r9 0x76,0x10,0xff,0xe6 = uxth r1, r6 0x78,0x34,0xff,0xe6 = uxth r3, r8, ror #8 0x72,0x28,0xff,0xd6 = uxthle r2, r2, ror #16 0x73,0x9c,0xff,0xe6 = uxth r9, r3, ror #24 0x02,0xf0,0x20,0xe3 = wfe 0x02,0xf0,0x20,0x83 = wfehi 0x03,0xf0,0x20,0xe3 = wfi 0x03,0xf0,0x20,0xb3 = wfilt 0x01,0xf0,0x20,0xe3 = yield 0x01,0xf0,0x20,0x13 = yieldne 0x04,0xf0,0x20,0xe3 = sev 0x03,0xf0,0x20,0xe3 = wfi 0x02,0xf0,0x20,0xe3 = wfe 0x01,0xf0,0x20,0xe3 = yield 0x00,0xf0,0x20,0xe3 = nop 0xef,0xf0,0x20,0xc3 = hintgt #239 capstone-sys-0.15.0/capstone/suite/MC/ARM/basic-thumb-instructions.s.cs000064400000000000000000000066230072674642500240110ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x74,0x41 = adcs r4, r6 0xd1,0x1c = adds r1, r2, #3 0x03,0x32 = adds r2, #3 0x08,0x32 = adds r2, #8 0xd1,0x18 = adds r1, r2, r3 0x42,0x44 = add r2, r8 0x01,0xb0 = add sp, #4 0x7f,0xb0 = add sp, #508 0x01,0xb0 = add sp, #4 0x02,0xaa = add r2, sp, #8 0xff,0xaa = add r2, sp, #1020 0x82,0xb0 = sub sp, #8 0x82,0xb0 = sub sp, #8 0x9d,0x44 = add sp, r3 0x6a,0x44 = add r2, sp, r2 0x00,0xa5 = adr r5, #0 0x01,0xa2 = adr r2, #4 0xff,0xa3 = adr r3, #1020 0x1a,0x10 = asrs r2, r3, #32 0x5a,0x11 = asrs r2, r3, #5 0x5a,0x10 = asrs r2, r3, #1 0x6d,0x15 = asrs r5, r5, #21 0x6d,0x15 = asrs r5, r5, #21 0x6b,0x15 = asrs r3, r5, #21 0x15,0x41 = asrs r5, r2 0x97,0xe3 = b #1842 0x2e,0xe7 = b #-416 0x80,0xd0 = beq #-252 0x50,0xd0 = beq #164 0xd8,0xf0,0x20,0xe8 = blx #884804 0xb0,0xf1,0x40,0xe8 = blx #1769604 0xb1,0x43 = bics r1, r6 0x00,0xbe = bkpt #0 0xff,0xbe = bkpt #255 0xa0,0x47 = blx r4 0x10,0x47 = bx r2 0xcd,0x42 = cmn r5, r1 0x20,0x2e = cmp r6, #32 0xa3,0x42 = cmp r3, r4 0x88,0x45 = cmp r8, r1 0x61,0xb6 = cpsie f 0x74,0xb6 = cpsid a 0x6c,0x40 = eors r4, r5 0xff,0xcb = ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} 0xba,0xca = ldm r2!, {r1, r3, r4, r5, r7} 0x02,0xc9 = ldm r1, {r1} 0x29,0x68 = ldr r1, [r5] 0x32,0x6a = ldr r2, [r6, #32] 0xfb,0x6f = ldr r3, [r7, #124] 0x00,0x99 = ldr r1, [sp] 0x06,0x9a = ldr r2, [sp, #24] 0xff,0x9b = ldr r3, [sp, #1020] 0x97,0x4b = ldr r3, [pc, #604] 0x5c,0x4b = ldr r3, [pc, #368] 0xd1,0x58 = ldr r1, [r2, r3] 0x1c,0x78 = ldrb r4, [r3] 0x35,0x78 = ldrb r5, [r6] 0xfe,0x7f = ldrb r6, [r7, #31] 0x66,0x5d = ldrb r6, [r4, r5] 0x1b,0x88 = ldrh r3, [r3] 0x74,0x88 = ldrh r4, [r6, #2] 0xfd,0x8f = ldrh r5, [r7, #62] 0x96,0x5b = ldrh r6, [r2, r6] 0x96,0x57 = ldrsb r6, [r2, r6] 0x7b,0x5e = ldrsh r3, [r7, r1] // 0x2c,0x00 = lsls r4, r5, #0 0x2c,0x01 = lsls r4, r5, #4 0x1b,0x03 = lsls r3, r3, #12 0x1b,0x03 = lsls r3, r3, #12 0x19,0x03 = lsls r1, r3, #12 0xb2,0x40 = lsls r2, r6 0x59,0x08 = lsrs r1, r3, #1 0x19,0x08 = lsrs r1, r3, #32 0x24,0x0d = lsrs r4, r4, #20 0x24,0x0d = lsrs r4, r4, #20 0x22,0x0d = lsrs r2, r4, #20 0xf2,0x40 = lsrs r2, r6 0x00,0x22 = movs r2, #0 0xff,0x22 = movs r2, #255 0x17,0x22 = movs r2, #23 0x23,0x46 = mov r3, r4 0x19,0x00 = movs r1, r3 0x51,0x43 = muls r1, r2, r1 0x5a,0x43 = muls r2, r3, r2 0x63,0x43 = muls r3, r4, r3 0xde,0x43 = mvns r6, r3 0x63,0x42 = rsbs r3, r4, #0 0x4c,0xbc = pop {r2, r3, r6} 0x86,0xb4 = push {r1, r2, r7} 0x1e,0xba = rev r6, r3 0x57,0xba = rev16 r7, r2 0xcd,0xba = revsh r5, r1 0xfa,0x41 = rors r2, r7 0x59,0x42 = rsbs r1, r3, #0 0x9c,0x41 = sbcs r4, r3 0x58,0xb6 = setend be 0x50,0xb6 = setend le 0x44,0xc1 = stm r1!, {r2, r6} 0x8e,0xc1 = stm r1!, {r1, r2, r3, r7} 0x3a,0x60 = str r2, [r7] 0x3a,0x60 = str r2, [r7] 0x4d,0x60 = str r5, [r1, #4] 0xfb,0x67 = str r3, [r7, #124] 0x00,0x92 = str r2, [sp] 0x00,0x93 = str r3, [sp] 0x05,0x94 = str r4, [sp, #20] 0xff,0x95 = str r5, [sp, #1020] 0xfa,0x50 = str r2, [r7, r3] 0x1c,0x70 = strb r4, [r3] 0x35,0x70 = strb r5, [r6] 0xfe,0x77 = strb r6, [r7, #31] 0x66,0x55 = strb r6, [r4, r5] 0x1b,0x80 = strh r3, [r3] 0x74,0x80 = strh r4, [r6, #2] 0xfd,0x87 = strh r5, [r7, #62] 0x96,0x53 = strh r6, [r2, r6] 0xd1,0x1e = subs r1, r2, #3 0x03,0x3a = subs r2, #3 0x08,0x3a = subs r2, #8 0x83,0xb0 = sub sp, #12 0xff,0xb0 = sub sp, #508 0xd1,0x1a = subs r1, r2, r3 0x00,0xdf = svc #0 0xff,0xdf = svc #255 0x6b,0xb2 = sxtb r3, r5 0x2b,0xb2 = sxth r3, r5 0x0e,0x42 = tst r6, r1 0xd7,0xb2 = uxtb r7, r2 0xa1,0xb2 = uxth r1, r4 capstone-sys-0.15.0/capstone/suite/MC/ARM/basic-thumb2-instructions-v8.s.cs000064400000000000000000000000560072674642500244200ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None capstone-sys-0.15.0/capstone/suite/MC/ARM/basic-thumb2-instructions.s.cs000064400000000000000000001362100072674642500240670ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x41,0xf1,0x04,0x00 = adc r0, r1, #4 0x51,0xf1,0x00,0x00 = adcs r0, r1, #0 0x42,0xf1,0xff,0x01 = adc r1, r2, #255 0x47,0xf1,0x55,0x13 = adc r3, r7, #5570645 0x4c,0xf1,0xaa,0x28 = adc r8, r12, #2852170240 0x47,0xf1,0xa5,0x39 = adc r9, r7, #2779096485 0x43,0xf1,0x07,0x45 = adc r5, r3, #2264924160 0x42,0xf1,0xff,0x44 = adc r4, r2, #2139095040 0x42,0xf5,0xd0,0x64 = adc r4, r2, #1664 0x45,0xeb,0x06,0x04 = adc.w r4, r5, r6 0x55,0xeb,0x06,0x04 = adcs.w r4, r5, r6 0x41,0xeb,0x03,0x09 = adc.w r9, r1, r3 0x51,0xeb,0x03,0x09 = adcs.w r9, r1, r3 0x41,0xeb,0x33,0x10 = adc.w r0, r1, r3, ror #4 0x51,0xeb,0xc3,0x10 = adcs.w r0, r1, r3, lsl #7 0x41,0xeb,0xd3,0x70 = adc.w r0, r1, r3, lsr #31 0x51,0xeb,0x23,0x00 = adcs.w r0, r1, r3, asr #32 0x0d,0xeb,0x0c,0x02 = add.w r2, sp, ip 0x0a,0xbf = itet eq // 0x03,0xf2,0xff,0x35 = addwne r5, r3, #1023 // 0x05,0xf2,0x25,0x14 = addweq r4, r5, #293 0x0d,0xf5,0x80,0x62 = add.w r2, sp, #1024 0x08,0xf5,0x7f,0x42 = add.w r2, r8, #65280 0x03,0xf2,0x01,0x12 = addw r2, r3, #257 0x03,0xf2,0x01,0x12 = addw r2, r3, #257 0x06,0xf5,0x80,0x7c = add.w r12, r6, #256 0x06,0xf2,0x00,0x1c = addw r12, r6, #256 0x12,0xf5,0xf8,0x71 = adds.w r1, r2, #496 0x02,0xf1,0x01,0x02 = add.w r2, r2, #1 0x00,0xf1,0x20,0x00 = add.w r0, r0, #32 0x38,0x32 = adds r2, #56 0x38,0x32 = adds r2, #56 0x07,0xf1,0xcb,0x31 = add.w r1, r7, #3419130827 0x0d,0xf1,0xff,0x7d = add.w sp, sp, #33423360 0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #16 0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #16 0xa2,0xf2,0x10,0x02 = subw r2, r2, #16 0xa2,0xf2,0x10,0x02 = subw r2, r2, #16 0xa2,0xf2,0x10,0x02 = subw r2, r2, #16 0x02,0xeb,0x08,0x01 = add.w r1, r2, r8 0x09,0xeb,0x22,0x05 = add.w r5, r9, r2, asr #32 0x13,0xeb,0xc1,0x77 = adds.w r7, r3, r1, lsl #31 0x13,0xeb,0x56,0x60 = adds.w r0, r3, r6, lsr #25 0x08,0xeb,0x31,0x34 = add.w r4, r8, r1, ror #12 0xc2,0x44 = add r10, r8 0xc2,0x44 = add r10, r8 0xaf,0xf6,0xc6,0x4b = subw r11, pc, #3270 // 0x0f,0xf2,0x03,0x02 = adr.w r2, #3 // 0xaf,0xf2,0x3a,0x3b = adr.w r11, #-826 // 0xaf,0xf2,0x00,0x01 = adr.w r1, #-0 0x05,0xf4,0x7f,0x22 = and r2, r5, #1044480 0x1c,0xf0,0x0f,0x03 = ands r3, r12, #15 0x01,0xf0,0xff,0x01 = and r1, r1, #255 0x01,0xf0,0xff,0x01 = and r1, r1, #255 0x04,0xf0,0xff,0x35 = and r5, r4, #4294967295 0x19,0xf0,0xff,0x31 = ands r1, r9, #4294967295 0x09,0xea,0x08,0x04 = and.w r4, r9, r8 0x04,0xea,0xe8,0x01 = and.w r1, r4, r8, asr #3 0x11,0xea,0x47,0x02 = ands.w r2, r1, r7, lsl #1 0x15,0xea,0x12,0x54 = ands.w r4, r5, r2, lsr #20 0x0c,0xea,0x71,0x49 = and.w r9, r12, r1, ror #17 0x4f,0xea,0x23,0x32 = asr.w r2, r3, #12 0x5f,0xea,0x23,0x08 = asrs.w r8, r3, #32 0x5f,0xea,0x63,0x02 = asrs.w r2, r3, #1 0x4f,0xea,0x23,0x12 = asr.w r2, r3, #4 0x5f,0xea,0xec,0x32 = asrs.w r2, r12, #15 0x4f,0xea,0xe3,0x43 = asr.w r3, r3, #19 0x5f,0xea,0xa8,0x08 = asrs.w r8, r8, #2 0x5f,0xea,0x67,0x17 = asrs.w r7, r7, #5 0x4f,0xea,0x6c,0x5c = asr.w r12, r12, #21 0x44,0xfa,0x02,0xf3 = asr.w r3, r4, r2 0x41,0xfa,0x02,0xf1 = asr.w r1, r1, r2 0x54,0xfa,0x08,0xf3 = asrs.w r3, r4, r8 0x08,0xbf = it eq 0x13,0xf5,0xce,0xa9 = bmi.w #-183392 // 0x6f,0xf3,0xd3,0x05 = bfc r5, #3, #17 0x38,0xbf = it lo // 0x6f,0xf3,0xd3,0x05 = bfclo r5, #3, #17 // 0x62,0xf3,0xd3,0x05 = bfi r5, r2, #3, #17 0x18,0xbf = it ne // 0x62,0xf3,0xd3,0x05 = bfine r5, r2, #3, #17 0x21,0xf0,0x0f,0x0a = bic r10, r1, #15 0x22,0xf0,0xff,0x35 = bic r5, r2, #4294967295 0x3a,0xf0,0xff,0x3b = bics r11, r10, #4294967295 0x23,0xea,0x06,0x0c = bic.w r12, r3, r6 0x22,0xea,0x06,0x3b = bic.w r11, r2, r6, lsl #12 0x24,0xea,0xd1,0x28 = bic.w r8, r4, r1, lsr #11 0x25,0xea,0xd7,0x37 = bic.w r7, r5, r7, lsr #15 0x27,0xea,0x29,0x06 = bic.w r6, r7, r9, asr #32 0x26,0xea,0x78,0x05 = bic.w r5, r6, r8, ror #1 0x21,0xf0,0x0f,0x01 = bic r1, r1, #15 0x21,0xea,0x01,0x01 = bic.w r1, r1, r1 0x24,0xea,0xc2,0x74 = bic.w r4, r4, r2, lsl #31 0x26,0xea,0x13,0x36 = bic.w r6, r6, r3, lsr #12 0x27,0xea,0xd4,0x17 = bic.w r7, r7, r4, lsr #7 0x28,0xea,0xe5,0x38 = bic.w r8, r8, r5, asr #15 0x2c,0xea,0x76,0x7c = bic.w r12, r12, r6, ror #29 0x58,0xbf = it pl 0xea,0xbe = bkpt #234 0xc5,0xf3,0x00,0x8f = bxj r5 0x18,0xbf = it ne // 0xc7,0xf3,0x00,0x8f = bxjne r7 // 0x1f,0xb9 = cbnz r7, #6 // 0x37,0xb9 = cbnz r7, #12 0x11,0xee,0x81,0x17 = cdp p7, #1, c1, c1, c1, #4 0x11,0xfe,0x81,0x17 = cdp2 p7, #1, c1, c1, c1, #4 0xbf,0xf3,0x2f,0x8f = clrex 0x18,0xbf = it ne // 0xb2,0xfa,0x82,0xf1 = clz r1, r2 0x08,0xbf = it eq // 0xb2,0xfa,0x82,0xf1 = clzeq r1, r2 0x11,0xf1,0x0f,0x0f = cmn.w r1, #15 0x18,0xeb,0x06,0x0f = cmn.w r8, r6 0x11,0xeb,0x86,0x2f = cmn.w r1, r6, lsl #10 0x11,0xeb,0x96,0x2f = cmn.w r1, r6, lsr #10 0x1d,0xeb,0x96,0x2f = cmn.w sp, r6, lsr #10 0x11,0xeb,0xa6,0x2f = cmn.w r1, r6, asr #10 0x11,0xeb,0xb6,0x2f = cmn.w r1, r6, ror #10 0xb5,0xf5,0x7f,0x4f = cmp.w r5, #65280 0xb4,0xeb,0x0c,0x0f = cmp.w r4, r12 0xb9,0xeb,0x06,0x3f = cmp.w r9, r6, lsl #12 0xb3,0xeb,0xd7,0x7f = cmp.w r3, r7, lsr #31 0xbd,0xeb,0x56,0x0f = cmp.w sp, r6, lsr #1 0xb2,0xeb,0x25,0x6f = cmp.w r2, r5, asr #24 0xb1,0xeb,0xf4,0x3f = cmp.w r1, r4, ror #15 0x12,0xf1,0x02,0x0f = cmn.w r2, #2 0xb9,0xf1,0x01,0x0f = cmp.w r9, #1 0x61,0xb6 = cpsie f 0x74,0xb6 = cpsid a 0xaf,0xf3,0x20,0x84 = cpsie.w f 0xaf,0xf3,0x80,0x86 = cpsid.w a 0xaf,0xf3,0x43,0x85 = cpsie i, #3 0xaf,0xf3,0x43,0x85 = cpsie i, #3 0xaf,0xf3,0x29,0x87 = cpsid f, #9 0xaf,0xf3,0x29,0x87 = cpsid f, #9 0xaf,0xf3,0x00,0x81 = cps #0 0xaf,0xf3,0x00,0x81 = cps #0 0xaf,0xf3,0xf5,0x80 = dbg #5 0xaf,0xf3,0xf0,0x80 = dbg #0 0xaf,0xf3,0xff,0x80 = dbg #15 0xbf,0xf3,0x5f,0x8f = dmb sy 0xbf,0xf3,0x5e,0x8f = dmb st 0xbf,0xf3,0x5d,0x8f = dmb #0xd 0xbf,0xf3,0x5c,0x8f = dmb #0xc 0xbf,0xf3,0x5b,0x8f = dmb ish 0xbf,0xf3,0x5a,0x8f = dmb ishst 0xbf,0xf3,0x59,0x8f = dmb #0x9 0xbf,0xf3,0x58,0x8f = dmb #0x8 0xbf,0xf3,0x57,0x8f = dmb nsh 0xbf,0xf3,0x56,0x8f = dmb nshst 0xbf,0xf3,0x55,0x8f = dmb #0x5 0xbf,0xf3,0x54,0x8f = dmb #0x4 0xbf,0xf3,0x53,0x8f = dmb osh 0xbf,0xf3,0x52,0x8f = dmb oshst 0xbf,0xf3,0x51,0x8f = dmb #0x1 0xbf,0xf3,0x50,0x8f = dmb #0x0 0xbf,0xf3,0x5f,0x8f = dmb sy 0xbf,0xf3,0x5e,0x8f = dmb st 0xbf,0xf3,0x5b,0x8f = dmb ish 0xbf,0xf3,0x5b,0x8f = dmb ish 0xbf,0xf3,0x5a,0x8f = dmb ishst 0xbf,0xf3,0x5a,0x8f = dmb ishst 0xbf,0xf3,0x57,0x8f = dmb nsh 0xbf,0xf3,0x57,0x8f = dmb nsh 0xbf,0xf3,0x56,0x8f = dmb nshst 0xbf,0xf3,0x56,0x8f = dmb nshst 0xbf,0xf3,0x53,0x8f = dmb osh 0xbf,0xf3,0x52,0x8f = dmb oshst 0xbf,0xf3,0x5f,0x8f = dmb sy 0xbf,0xf3,0x4f,0x8f = dsb sy 0xbf,0xf3,0x4e,0x8f = dsb st 0xbf,0xf3,0x4d,0x8f = dsb #0xd 0xbf,0xf3,0x4b,0x8f = dsb ish 0xbf,0xf3,0x4a,0x8f = dsb ishst 0xbf,0xf3,0x49,0x8f = dsb #0x9 0xbf,0xf3,0x48,0x8f = dsb #0x8 0xbf,0xf3,0x47,0x8f = dsb nsh 0xbf,0xf3,0x46,0x8f = dsb nshst 0xbf,0xf3,0x45,0x8f = dsb #0x5 0xbf,0xf3,0x44,0x8f = dsb #0x4 0xbf,0xf3,0x43,0x8f = dsb osh 0xbf,0xf3,0x42,0x8f = dsb oshst 0xbf,0xf3,0x41,0x8f = dsb #0x1 0xbf,0xf3,0x40,0x8f = dsb #0x0 0xbf,0xf3,0x4f,0x8f = dsb sy 0xbf,0xf3,0x4e,0x8f = dsb st 0xbf,0xf3,0x4b,0x8f = dsb ish 0xbf,0xf3,0x4b,0x8f = dsb ish 0xbf,0xf3,0x4a,0x8f = dsb ishst 0xbf,0xf3,0x4a,0x8f = dsb ishst 0xbf,0xf3,0x47,0x8f = dsb nsh 0xbf,0xf3,0x47,0x8f = dsb nsh 0xbf,0xf3,0x46,0x8f = dsb nshst 0xbf,0xf3,0x46,0x8f = dsb nshst 0xbf,0xf3,0x43,0x8f = dsb osh 0xbf,0xf3,0x42,0x8f = dsb oshst 0xbf,0xf3,0x4f,0x8f = dsb sy 0x85,0xf4,0x70,0x44 = eor r4, r5, #61440 0x85,0xea,0x06,0x04 = eor.w r4, r5, r6 0x85,0xea,0x46,0x14 = eor.w r4, r5, r6, lsl #5 0x85,0xea,0x56,0x14 = eor.w r4, r5, r6, lsr #5 0x85,0xea,0x56,0x14 = eor.w r4, r5, r6, lsr #5 0x85,0xea,0x66,0x14 = eor.w r4, r5, r6, asr #5 0x85,0xea,0x76,0x14 = eor.w r4, r5, r6, ror #5 0xbf,0xf3,0x6f,0x8f = isb sy 0xbf,0xf3,0x6f,0x8f = isb sy 0xbf,0xf3,0x6f,0x8f = isb sy 0xbf,0xf3,0x61,0x8f = isb #0x1 0x0d,0xbf = iteet eq // 0x88,0x18 = addeq r0, r1, r2 // 0x00,0xbf = nopne // 0xf5,0x1b = subne r5, r6, r7 0x0d,0xbf = iteet eq // 0x88,0x18 = addeq r0, r1, r2 // 0x00,0xbf = nopne // 0xf5,0x1b = subne r5, r6, r7 0x91,0xfd,0x01,0x80 = ldc2 p0, c8, [r1, #4] 0x92,0xfd,0x00,0x71 = ldc2 p1, c7, [r2] 0x13,0xfd,0x38,0x62 = ldc2 p2, c6, [r3, #-224] 0x34,0xfd,0x1e,0x53 = ldc2 p3, c5, [r4, #-120]! 0xb5,0xfc,0x04,0x44 = ldc2 p4, c4, [r5], #16 0x36,0xfc,0x12,0x35 = ldc2 p5, c3, [r6], #-72 0xd7,0xfd,0x01,0x26 = ldc2l p6, c2, [r7, #4] 0xd8,0xfd,0x00,0x17 = ldc2l p7, c1, [r8] 0x59,0xfd,0x38,0x08 = ldc2l p8, c0, [r9, #-224] 0x7a,0xfd,0x1e,0x19 = ldc2l p9, c1, [r10, #-120]! 0xfb,0xfc,0x04,0x20 = ldc2l p0, c2, [r11], #16 0x7c,0xfc,0x12,0x31 = ldc2l p1, c3, [r12], #-72 0x90,0xed,0x01,0x4c = ldc p12, c4, [r0, #4] 0x91,0xed,0x00,0x5d = ldc p13, c5, [r1] 0x12,0xed,0x38,0x6e = ldc p14, c6, [r2, #-224] 0x33,0xed,0x1e,0x7f = ldc p15, c7, [r3, #-120]! 0xb4,0xec,0x04,0x85 = ldc p5, c8, [r4], #16 0x35,0xec,0x12,0x94 = ldc p4, c9, [r5], #-72 0xd6,0xed,0x01,0xa3 = ldcl p3, c10, [r6, #4] 0xd7,0xed,0x00,0xb2 = ldcl p2, c11, [r7] 0x58,0xed,0x38,0xc1 = ldcl p1, c12, [r8, #-224] 0x79,0xed,0x1e,0xd0 = ldcl p0, c13, [r9, #-120]! 0xfa,0xec,0x04,0xe6 = ldcl p6, c14, [r10], #16 0x7b,0xec,0x12,0xf7 = ldcl p7, c15, [r11], #-72 0x91,0xfc,0x19,0x82 = ldc2 p2, c8, [r1], {25} 0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} 0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} 0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} 0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} 0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} 0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} 0xb5,0xe8,0x06,0x00 = ldm.w r5!, {r1, r2} 0x92,0xe8,0x06,0x00 = ldm.w r2, {r1, r2} 0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} 0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} 0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} 0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9} 0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6} 0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} 0xb5,0xe8,0x08,0x01 = ldm.w r5!, {r3, r8} 0xbd,0xe8,0xf0,0x8f = pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} 0x14,0xe9,0x30,0x03 = ldmdb r4, {r4, r5, r8, r9} 0x14,0xe9,0x60,0x00 = ldmdb r4, {r5, r6} 0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8} 0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8} 0x14,0xe9,0x60,0x00 = ldmdb r4, {r5, r6} 0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8} 0x55,0xf8,0x04,0x5c = ldr r5, [r5, #-4] 0x35,0x6a = ldr r5, [r6, #32] 0xd6,0xf8,0x21,0x50 = ldr.w r5, [r6, #33] 0xd6,0xf8,0x01,0x51 = ldr.w r5, [r6, #257] 0xd7,0xf8,0x01,0xf1 = ldr.w pc, [r7, #257] 0x54,0xf8,0xff,0x2f = ldr r2, [r4, #255]! 0x5d,0xf8,0x04,0x8f = ldr r8, [sp, #4]! 0x5d,0xf8,0x04,0xed = ldr lr, [sp, #-4]! 0x54,0xf8,0xff,0x2b = ldr r2, [r4], #255 0x5d,0xf8,0x04,0x8b = ldr r8, [sp], #4 0x5d,0xf8,0x04,0xe9 = ldr lr, [sp], #-4 0x02,0x4f = ldr r7, [pc, #8] 0x02,0x4f = ldr r7, [pc, #8] 0xdf,0xf8,0x08,0x70 = ldr.w r7, [pc, #8] 0xff,0x4c = ldr r4, [pc, #1020] 0x5f,0xf8,0xfc,0x33 = ldr.w r3, [pc, #-1020] 0xdf,0xf8,0x00,0x64 = ldr.w r6, [pc, #1024] 0x5f,0xf8,0x00,0x04 = ldr.w r0, [pc, #-1024] 0xdf,0xf8,0xff,0x2f = ldr.w r2, [pc, #4095] 0x5f,0xf8,0xff,0x1f = ldr.w r1, [pc, #-4095] 0xdf,0xf8,0x84,0x80 = ldr.w r8, [pc, #132] 0xdf,0xf8,0x00,0xf1 = ldr.w pc, [pc, #256] 0x5f,0xf8,0x90,0xf1 = ldr.w pc, [pc, #-400] 0x1f,0xf8,0x00,0x90 = ldrb.w r9, [pc, #-0] 0x1f,0xf9,0x00,0xb0 = ldrsb.w r11, [pc, #-0] 0x3f,0xf8,0x00,0xa0 = ldrh.w r10, [pc, #-0] 0x3f,0xf9,0x00,0x10 = ldrsh.w r1, [pc, #-0] 0x5f,0xf8,0x00,0x50 = ldr.w r5, [pc, #-0] 0x58,0xf8,0x01,0x10 = ldr.w r1, [r8, r1] 0x55,0xf8,0x02,0x40 = ldr.w r4, [r5, r2] 0x50,0xf8,0x32,0x60 = ldr.w r6, [r0, r2, lsl #3] 0x58,0xf8,0x22,0x80 = ldr.w r8, [r8, r2, lsl #2] 0x5d,0xf8,0x12,0x70 = ldr.w r7, [sp, r2, lsl #1] 0x5d,0xf8,0x02,0x70 = ldr.w r7, [sp, r2] 0x15,0xf8,0x04,0x5c = ldrb r5, [r5, #-4] 0x96,0xf8,0x20,0x50 = ldrb.w r5, [r6, #32] 0x96,0xf8,0x21,0x50 = ldrb.w r5, [r6, #33] 0x96,0xf8,0x01,0x51 = ldrb.w r5, [r6, #257] 0x97,0xf8,0x01,0xe1 = ldrb.w lr, [r7, #257] 0x18,0xf8,0xff,0x5f = ldrb r5, [r8, #255]! 0x15,0xf8,0x04,0x2f = ldrb r2, [r5, #4]! 0x14,0xf8,0x04,0x1d = ldrb r1, [r4, #-4]! 0x13,0xf8,0xff,0xeb = ldrb lr, [r3], #255 0x12,0xf8,0x04,0x9b = ldrb r9, [r2], #4 0x1d,0xf8,0x04,0x39 = ldrb r3, [sp], #-4 0x18,0xf8,0x01,0x10 = ldrb.w r1, [r8, r1] 0x15,0xf8,0x02,0x40 = ldrb.w r4, [r5, r2] 0x10,0xf8,0x32,0x60 = ldrb.w r6, [r0, r2, lsl #3] 0x18,0xf8,0x22,0x80 = ldrb.w r8, [r8, r2, lsl #2] 0x1d,0xf8,0x12,0x70 = ldrb.w r7, [sp, r2, lsl #1] 0x1d,0xf8,0x02,0x70 = ldrb.w r7, [sp, r2] 0x12,0xf8,0x00,0x1e = ldrbt r1, [r2] 0x18,0xf8,0x00,0x1e = ldrbt r1, [r8] 0x18,0xf8,0x03,0x1e = ldrbt r1, [r8, #3] 0x18,0xf8,0xff,0x1e = ldrbt r1, [r8, #255] 0xd6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #24] 0xf6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #24]! 0xf6,0xe8,0x01,0x35 = ldrd r3, r5, [r6], #4 0x76,0xe8,0x02,0x35 = ldrd r3, r5, [r6], #-8 0xd6,0xe9,0x00,0x35 = ldrd r3, r5, [r6] 0xd3,0xe9,0x00,0x81 = ldrd r8, r1, [r3] 0x52,0xe9,0x00,0x01 = ldrd r0, r1, [r2, #-0] 0x72,0xe9,0x00,0x01 = ldrd r0, r1, [r2, #-0]! 0x72,0xe8,0x00,0x01 = ldrd r0, r1, [r2], #-0 0x54,0xe8,0x00,0x1f = ldrex r1, [r4] 0x54,0xe8,0x00,0x8f = ldrex r8, [r4] 0x5d,0xe8,0x20,0x2f = ldrex r2, [sp, #128] 0xd7,0xe8,0x4f,0x5f = ldrexb r5, [r7] 0xdc,0xe8,0x5f,0x9f = ldrexh r9, [r12] 0xd4,0xe8,0x7f,0x93 = ldrexd r9, r3, [r4] 0x35,0xf8,0x04,0x5c = ldrh r5, [r5, #-4] 0x35,0x8c = ldrh r5, [r6, #32] 0xb6,0xf8,0x21,0x50 = ldrh.w r5, [r6, #33] 0xb6,0xf8,0x01,0x51 = ldrh.w r5, [r6, #257] 0xb7,0xf8,0x01,0xe1 = ldrh.w lr, [r7, #257] 0x38,0xf8,0xff,0x5f = ldrh r5, [r8, #255]! 0x35,0xf8,0x04,0x2f = ldrh r2, [r5, #4]! 0x34,0xf8,0x04,0x1d = ldrh r1, [r4, #-4]! 0x33,0xf8,0xff,0xeb = ldrh lr, [r3], #255 0x32,0xf8,0x04,0x9b = ldrh r9, [r2], #4 0x3d,0xf8,0x04,0x39 = ldrh r3, [sp], #-4 0x38,0xf8,0x01,0x10 = ldrh.w r1, [r8, r1] 0x35,0xf8,0x02,0x40 = ldrh.w r4, [r5, r2] 0x30,0xf8,0x32,0x60 = ldrh.w r6, [r0, r2, lsl #3] 0x38,0xf8,0x22,0x80 = ldrh.w r8, [r8, r2, lsl #2] 0x3d,0xf8,0x12,0x70 = ldrh.w r7, [sp, r2, lsl #1] 0x3d,0xf8,0x02,0x70 = ldrh.w r7, [sp, r2] 0x32,0xf8,0x00,0x1e = ldrht r1, [r2] 0x38,0xf8,0x00,0x1e = ldrht r1, [r8] 0x38,0xf8,0x03,0x1e = ldrht r1, [r8, #3] 0x38,0xf8,0xff,0x1e = ldrht r1, [r8, #255] 0x15,0xf9,0x04,0x5c = ldrsb r5, [r5, #-4] 0x96,0xf9,0x20,0x50 = ldrsb.w r5, [r6, #32] 0x96,0xf9,0x21,0x50 = ldrsb.w r5, [r6, #33] 0x96,0xf9,0x01,0x51 = ldrsb.w r5, [r6, #257] 0x97,0xf9,0x01,0xe1 = ldrsb.w lr, [r7, #257] 0x18,0xf9,0x01,0x10 = ldrsb.w r1, [r8, r1] 0x15,0xf9,0x02,0x40 = ldrsb.w r4, [r5, r2] 0x10,0xf9,0x32,0x60 = ldrsb.w r6, [r0, r2, lsl #3] 0x18,0xf9,0x22,0x80 = ldrsb.w r8, [r8, r2, lsl #2] 0x1d,0xf9,0x12,0x70 = ldrsb.w r7, [sp, r2, lsl #1] 0x1d,0xf9,0x02,0x70 = ldrsb.w r7, [sp, r2] 0x18,0xf9,0xff,0x5f = ldrsb r5, [r8, #255]! 0x15,0xf9,0x04,0x2f = ldrsb r2, [r5, #4]! 0x14,0xf9,0x04,0x1d = ldrsb r1, [r4, #-4]! 0x13,0xf9,0xff,0xeb = ldrsb lr, [r3], #255 0x12,0xf9,0x04,0x9b = ldrsb r9, [r2], #4 0x1d,0xf9,0x04,0x39 = ldrsb r3, [sp], #-4 0x12,0xf9,0x00,0x1e = ldrsbt r1, [r2] 0x18,0xf9,0x00,0x1e = ldrsbt r1, [r8] 0x18,0xf9,0x03,0x1e = ldrsbt r1, [r8, #3] 0x18,0xf9,0xff,0x1e = ldrsbt r1, [r8, #255] 0x35,0xf9,0x04,0x5c = ldrsh r5, [r5, #-4] 0xb6,0xf9,0x20,0x50 = ldrsh.w r5, [r6, #32] 0xb6,0xf9,0x21,0x50 = ldrsh.w r5, [r6, #33] 0xb6,0xf9,0x01,0x51 = ldrsh.w r5, [r6, #257] 0xb7,0xf9,0x01,0xe1 = ldrsh.w lr, [r7, #257] 0x38,0xf9,0x01,0x10 = ldrsh.w r1, [r8, r1] 0x35,0xf9,0x02,0x40 = ldrsh.w r4, [r5, r2] 0x30,0xf9,0x32,0x60 = ldrsh.w r6, [r0, r2, lsl #3] 0x38,0xf9,0x22,0x80 = ldrsh.w r8, [r8, r2, lsl #2] 0x3d,0xf9,0x12,0x70 = ldrsh.w r7, [sp, r2, lsl #1] 0x3d,0xf9,0x02,0x70 = ldrsh.w r7, [sp, r2] 0x38,0xf9,0xff,0x5f = ldrsh r5, [r8, #255]! 0x35,0xf9,0x04,0x2f = ldrsh r2, [r5, #4]! 0x34,0xf9,0x04,0x1d = ldrsh r1, [r4, #-4]! 0x33,0xf9,0xff,0xeb = ldrsh lr, [r3], #255 0x32,0xf9,0x04,0x9b = ldrsh r9, [r2], #4 0x3d,0xf9,0x04,0x39 = ldrsh r3, [sp], #-4 0x32,0xf9,0x00,0x1e = ldrsht r1, [r2] 0x38,0xf9,0x00,0x1e = ldrsht r1, [r8] 0x38,0xf9,0x03,0x1e = ldrsht r1, [r8, #3] 0x38,0xf9,0xff,0x1e = ldrsht r1, [r8, #255] 0x52,0xf8,0x00,0x1e = ldrt r1, [r2] 0x56,0xf8,0x00,0x2e = ldrt r2, [r6] 0x57,0xf8,0x03,0x3e = ldrt r3, [r7, #3] 0x59,0xf8,0xff,0x4e = ldrt r4, [r9, #255] 0x4f,0xea,0x03,0x32 = lsl.w r2, r3, #12 0x5f,0xea,0xc3,0x78 = lsls.w r8, r3, #31 0x5f,0xea,0x43,0x02 = lsls.w r2, r3, #1 0x4f,0xea,0x03,0x12 = lsl.w r2, r3, #4 0x5f,0xea,0xcc,0x32 = lsls.w r2, r12, #15 0x4f,0xea,0xc3,0x43 = lsl.w r3, r3, #19 0x5f,0xea,0x88,0x08 = lsls.w r8, r8, #2 0x5f,0xea,0x47,0x17 = lsls.w r7, r7, #5 0x4f,0xea,0x4c,0x5c = lsl.w r12, r12, #21 0x04,0xfa,0x02,0xf3 = lsl.w r3, r4, r2 0x01,0xfa,0x02,0xf1 = lsl.w r1, r1, r2 0x14,0xfa,0x08,0xf3 = lsls.w r3, r4, r8 0x4f,0xea,0x13,0x32 = lsr.w r2, r3, #12 0x5f,0xea,0x13,0x08 = lsrs.w r8, r3, #32 0x5f,0xea,0x53,0x02 = lsrs.w r2, r3, #1 0x4f,0xea,0x13,0x12 = lsr.w r2, r3, #4 0x5f,0xea,0xdc,0x32 = lsrs.w r2, r12, #15 0x4f,0xea,0xd3,0x43 = lsr.w r3, r3, #19 0x5f,0xea,0x98,0x08 = lsrs.w r8, r8, #2 0x5f,0xea,0x57,0x17 = lsrs.w r7, r7, #5 0x4f,0xea,0x5c,0x5c = lsr.w r12, r12, #21 0x24,0xfa,0x02,0xf3 = lsr.w r3, r4, r2 0x21,0xfa,0x02,0xf1 = lsr.w r1, r1, r2 0x34,0xfa,0x08,0xf3 = lsrs.w r3, r4, r8 0x21,0xee,0x91,0x57 = mcr p7, #1, r5, c1, c1, #4 0x21,0xfe,0x91,0x57 = mcr2 p7, #1, r5, c1, c1, #4 0x00,0xee,0x15,0x4e = mcr p14, #0, r4, c0, c5, #0 0x41,0xfe,0x13,0x24 = mcr2 p4, #2, r2, c1, c3, #0 0x44,0xec,0xf1,0x57 = mcrr p7, #15, r5, r4, c1 0x44,0xfc,0xf1,0x57 = mcrr2 p7, #15, r5, r4, c1 0x02,0xfb,0x03,0x41 = mla r1, r2, r3, r4 0x02,0xfb,0x13,0x41 = mls r1, r2, r3, r4 0x15,0x21 = movs r1, #21 0x5f,0xf0,0x15,0x01 = movs.w r1, #21 0x5f,0xf0,0x15,0x08 = movs.w r8, #21 0x4f,0xf6,0xff,0x70 = movw r0, #65535 0x4a,0xf6,0x01,0x31 = movw r1, #43777 0x4a,0xf6,0x10,0x31 = movw r1, #43792 0x4f,0xf0,0x7f,0x70 = mov.w r0, #66846720 0x4f,0xf0,0x7f,0x70 = mov.w r0, #66846720 0x5f,0xf0,0x7f,0x70 = movs.w r0, #66846720 0x06,0xbf = itte eq // 0x5f,0xf0,0x0c,0x01 = movseq.w r1, #12 // 0x0c,0x21 = moveq r1, #12 // 0x4f,0xf0,0x0c,0x01 = movne.w r1, #12 0x4f,0xf4,0xe1,0x76 = mov.w r6, #450 0x38,0xbf = it lo // 0x4f,0xf0,0xff,0x31 = movlo.w r1, #-1 0x6f,0xf0,0x02,0x03 = mvn r3, #2 0x4a,0xf6,0xcd,0x3b = movw r11, #43981 0x01,0x20 = movs r0, #1 0x18,0xbf = it ne // 0x0f,0x23 = movne r3, #15 0x04,0xbf = itt eq // 0xff,0x20 = moveq r0, #255 // 0x40,0xf2,0x00,0x11 = movweq r1, #256 0x4f,0xea,0x02,0x46 = lsl.w r6, r2, #16 0x4f,0xea,0x12,0x46 = lsr.w r6, r2, #16 0x16,0x10 = asrs r6, r2, #32 0x5f,0xea,0x72,0x16 = rors.w r6, r2, #5 // 0xac,0x40 = lsls r4, r5 // 0xec,0x40 = lsrs r4, r5 // 0x2c,0x41 = asrs r4, r5 // 0xec,0x41 = rors r4, r5 0x04,0xfa,0x05,0xf4 = lsl.w r4, r4, r5 0x74,0xfa,0x08,0xf4 = rors.w r4, r4, r8 0x35,0xfa,0x06,0xf4 = lsrs.w r4, r5, r6 0x01,0xbf = itttt eq // 0xac,0x40 = lsleq r4, r5 // 0xec,0x40 = lsreq r4, r5 // 0x2c,0x41 = asreq r4, r5 // 0xec,0x41 = roreq r4, r5 0x4f,0xea,0x34,0x04 = rrx r4, r4 0xc0,0xf2,0x07,0x03 = movt r3, #7 0xcf,0xf6,0xff,0x76 = movt r6, #65535 0x08,0xbf = it eq // 0xc0,0xf6,0xf0,0x74 = movteq r4, #4080 0x11,0xee,0x92,0x1e = mrc p14, #0, r1, c1, c2, #4 0xff,0xee,0xd6,0xff = mrc p15, #7, apsr_nzcv, c15, c6, #6 0x32,0xee,0x12,0x19 = mrc p9, #1, r1, c2, c2, #0 0x73,0xfe,0x14,0x3c = mrc2 p12, #3, r3, c3, c4, #0 0x11,0xfe,0x92,0x1e = mrc2 p14, #0, r1, c1, c2, #4 0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1 0x54,0xec,0x11,0x57 = mrrc p7, #1, r5, r4, c1 0x54,0xfc,0x11,0x57 = mrrc2 p7, #1, r5, r4, c1 0xef,0xf3,0x00,0x88 = mrs r8, apsr 0xef,0xf3,0x00,0x88 = mrs r8, apsr 0xff,0xf3,0x00,0x88 = mrs r8, spsr 0x81,0xf3,0x00,0x88 = msr apsr_nzcvq, r1 0x82,0xf3,0x00,0x84 = msr apsr_g, r2 0x83,0xf3,0x00,0x88 = msr apsr_nzcvq, r3 0x84,0xf3,0x00,0x88 = msr apsr_nzcvq, r4 0x85,0xf3,0x00,0x8c = msr apsr_nzcvqg, r5 0x86,0xf3,0x00,0x89 = msr cpsr_fc, r6 0x87,0xf3,0x00,0x81 = msr cpsr_c, r7 0x88,0xf3,0x00,0x82 = msr cpsr_x, r8 0x89,0xf3,0x00,0x89 = msr cpsr_fc, r9 0x8b,0xf3,0x00,0x89 = msr cpsr_fc, r11 0x8c,0xf3,0x00,0x8e = msr cpsr_fsx, r12 0x90,0xf3,0x00,0x89 = msr spsr_fc, r0 0x95,0xf3,0x00,0x8f = msr spsr_fsxc, r5 0x88,0xf3,0x00,0x8f = msr cpsr_fsxc, r8 0x83,0xf3,0x00,0x89 = msr cpsr_fc, r3 0x63,0x43 = muls r3, r4, r3 0x04,0xfb,0x03,0xf3 = mul r3, r4, r3 0x04,0xfb,0x06,0xf3 = mul r3, r4, r6 0x08,0xbf = it eq // 0x04,0xfb,0x05,0xf3 = muleq r3, r4, r5 0xd8,0xbf = it le // 0x04,0xfb,0x08,0xf4 = mulle r4, r4, r8 0x06,0xfb,0x05,0xf5 = mul r5, r6, r5 0x7f,0xf0,0x15,0x08 = mvns r8, #21 0x6f,0xf0,0x7f,0x70 = mvn r0, #66846720 0x7f,0xf0,0x7f,0x70 = mvns r0, #66846720 0x06,0xbf = itte eq // 0x7f,0xf0,0x0c,0x01 = mvnseq r1, #12 // 0x6f,0xf0,0x0c,0x01 = mvneq r1, #12 // 0x6f,0xf0,0x0c,0x01 = mvnne r1, #12 0x6f,0xea,0x03,0x02 = mvn.w r2, r3 // 0xda,0x43 = mvns r2, r3 0x6f,0xea,0xc6,0x45 = mvn.w r5, r6, lsl #19 0x6f,0xea,0x56,0x25 = mvn.w r5, r6, lsr #9 0x6f,0xea,0x26,0x15 = mvn.w r5, r6, asr #4 0x6f,0xea,0xb6,0x15 = mvn.w r5, r6, ror #6 0x6f,0xea,0x36,0x05 = mvn.w r5, r6, rrx 0x08,0xbf = it eq // 0xda,0x43 = mvneq r2, r3 0xc2,0xf1,0x00,0x05 = rsb.w r5, r2, #0 0xc8,0xf1,0x00,0x05 = rsb.w r5, r8, #0 0xaf,0xf3,0x00,0x80 = nop.w 0x65,0xf4,0x70,0x44 = orn r4, r5, #61440 0x65,0xea,0x06,0x04 = orn r4, r5, r6 0x75,0xea,0x06,0x04 = orns r4, r5, r6 0x65,0xea,0x46,0x14 = orn r4, r5, r6, lsl #5 0x75,0xea,0x56,0x14 = orns r4, r5, r6, lsr #5 0x65,0xea,0x56,0x14 = orn r4, r5, r6, lsr #5 0x75,0xea,0x66,0x14 = orns r4, r5, r6, asr #5 0x65,0xea,0x76,0x14 = orn r4, r5, r6, ror #5 0x45,0xf4,0x70,0x44 = orr r4, r5, #61440 0x45,0xea,0x06,0x04 = orr.w r4, r5, r6 0x45,0xea,0x46,0x14 = orr.w r4, r5, r6, lsl #5 0x55,0xea,0x56,0x14 = orrs.w r4, r5, r6, lsr #5 0x45,0xea,0x56,0x14 = orr.w r4, r5, r6, lsr #5 0x55,0xea,0x66,0x14 = orrs.w r4, r5, r6, asr #5 0x45,0xea,0x76,0x14 = orr.w r4, r5, r6, ror #5 0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3 0xc2,0xea,0xc3,0x72 = pkhbt r2, r2, r3, lsl #31 0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3 0xc2,0xea,0xc3,0x32 = pkhbt r2, r2, r3, lsl #15 0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3 0xc2,0xea,0xe3,0x72 = pkhtb r2, r2, r3, asr #31 0xc2,0xea,0xe3,0x32 = pkhtb r2, r2, r3, asr #15 0x15,0xf8,0x04,0xfc = pld [r5, #-4] 0x96,0xf8,0x20,0xf0 = pld [r6, #32] 0x96,0xf8,0x21,0xf0 = pld [r6, #33] 0x96,0xf8,0x01,0xf1 = pld [r6, #257] 0x97,0xf8,0x01,0xf1 = pld [r7, #257] 0x91,0xf8,0x00,0xf0 = pld [r1] 0x11,0xf8,0x00,0xfc = pld [r1, #-0] 0x1f,0xf8,0xff,0xff = pld [pc, #-4095] 0x18,0xf8,0x01,0xf0 = pld [r8, r1] 0x15,0xf8,0x02,0xf0 = pld [r5, r2] 0x10,0xf8,0x32,0xf0 = pld [r0, r2, lsl #3] 0x18,0xf8,0x22,0xf0 = pld [r8, r2, lsl #2] 0x1d,0xf8,0x12,0xf0 = pld [sp, r2, lsl #1] 0x1d,0xf8,0x02,0xf0 = pld [sp, r2] 0x15,0xf9,0x04,0xfc = pli [r5, #-4] 0x96,0xf9,0x20,0xf0 = pli [r6, #32] 0x96,0xf9,0x21,0xf0 = pli [r6, #33] 0x96,0xf9,0x01,0xf1 = pli [r6, #257] 0x97,0xf9,0x01,0xf1 = pli [r7, #257] 0x9f,0xf9,0xff,0xff = pli [pc, #4095] 0x1f,0xf9,0xff,0xff = pli [pc, #-4095] 0x18,0xf9,0x01,0xf0 = pli [r8, r1] 0x15,0xf9,0x02,0xf0 = pli [r5, r2] 0x10,0xf9,0x32,0xf0 = pli [r0, r2, lsl #3] 0x18,0xf9,0x22,0xf0 = pli [r8, r2, lsl #2] 0x1d,0xf9,0x12,0xf0 = pli [sp, r2, lsl #1] 0x1d,0xf9,0x02,0xf0 = pli [sp, r2] 0xbd,0xe8,0x04,0x02 = pop.w {r2, r9} 0x2d,0xe9,0x04,0x02 = push.w {r2, r9} // 0x83,0xfa,0x82,0xf1 = qadd r1, r2, r3 // 0x92,0xfa,0x13,0xf1 = qadd16 r1, r2, r3 // 0x82,0xfa,0x13,0xf1 = qadd8 r1, r2, r3 0xc6,0xbf = itte gt // 0x83,0xfa,0x82,0xf1 = qaddgt r1, r2, r3 // 0x92,0xfa,0x13,0xf1 = qadd16gt r1, r2, r3 // 0x82,0xfa,0x13,0xf1 = qadd8le r1, r2, r3 // 0x88,0xfa,0x97,0xf6 = qdadd r6, r7, r8 // 0x88,0xfa,0xb7,0xf6 = qdsub r6, r7, r8 0x84,0xbf = itt hi // 0x88,0xfa,0x97,0xf6 = qdaddhi r6, r7, r8 // 0x88,0xfa,0xb7,0xf6 = qdsubhi r6, r7, r8 // 0xec,0xfa,0x10,0xf9 = qsax r9, r12, r0 0x08,0xbf = it eq // 0xec,0xfa,0x10,0xf9 = qsaxeq r9, r12, r0 // 0x83,0xfa,0xa2,0xf1 = qsub r1, r2, r3 // 0xd2,0xfa,0x13,0xf1 = qsub16 r1, r2, r3 // 0xc2,0xfa,0x13,0xf1 = qsub8 r1, r2, r3 0xd6,0xbf = itet le // 0x83,0xfa,0xa2,0xf1 = qsuble r1, r2, r3 // 0xd2,0xfa,0x13,0xf1 = qsub16gt r1, r2, r3 // 0xc2,0xfa,0x13,0xf1 = qsub8le r1, r2, r3 // 0x92,0xfa,0xa2,0xf1 = rbit r1, r2 0x18,0xbf = it ne // 0x92,0xfa,0xa2,0xf1 = rbitne r1, r2 0x92,0xfa,0x82,0xf1 = rev.w r1, r2 0x98,0xfa,0x88,0xf2 = rev.w r2, r8 0x1c,0xbf = itt ne // 0x11,0xba = revne r1, r2 // 0x98,0xfa,0x88,0xf1 = revne.w r1, r8 0x92,0xfa,0x92,0xf1 = rev16.w r1, r2 0x98,0xfa,0x98,0xf2 = rev16.w r2, r8 0x1c,0xbf = itt ne // 0x51,0xba = rev16ne r1, r2 // 0x98,0xfa,0x98,0xf1 = rev16ne.w r1, r8 0x92,0xfa,0xb2,0xf1 = revsh.w r1, r2 0x98,0xfa,0xb8,0xf2 = revsh.w r2, r8 0x1c,0xbf = itt ne // 0xd1,0xba = revshne r1, r2 // 0x98,0xfa,0xb8,0xf1 = revshne.w r1, r8 0x4f,0xea,0x33,0x32 = ror.w r2, r3, #12 0x5f,0xea,0xf3,0x78 = rors.w r8, r3, #31 0x5f,0xea,0x73,0x02 = rors.w r2, r3, #1 0x4f,0xea,0x33,0x12 = ror.w r2, r3, #4 0x5f,0xea,0xfc,0x32 = rors.w r2, r12, #15 0x4f,0xea,0xf3,0x43 = ror.w r3, r3, #19 0x5f,0xea,0xb8,0x08 = rors.w r8, r8, #2 0x5f,0xea,0x77,0x17 = rors.w r7, r7, #5 0x4f,0xea,0x7c,0x5c = ror.w r12, r12, #21 0x64,0xfa,0x02,0xf3 = ror.w r3, r4, r2 0x61,0xfa,0x02,0xf1 = ror.w r1, r1, r2 0x74,0xfa,0x08,0xf3 = rors.w r3, r4, r8 0x4f,0xea,0x32,0x01 = rrx r1, r2 0x5f,0xea,0x32,0x01 = rrxs r1, r2 0xb4,0xbf = ite lt // 0x4f,0xea,0x3c,0x09 = rrxlt r9, r12 // 0x5f,0xea,0x33,0x08 = rrxsge r8, r3 0xc5,0xf5,0x7f,0x22 = rsb.w r2, r5, #1044480 0xdc,0xf1,0x0f,0x03 = rsbs.w r3, r12, #15 0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #255 0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #255 0xcb,0xf1,0x00,0x0b = rsb.w r11, r11, #0 0xc9,0xf1,0x00,0x09 = rsb.w r9, r9, #0 0x4b,0x42 = rsbs r3, r1, #0 0xc1,0xf1,0x00,0x03 = rsb.w r3, r1, #0 0xc4,0xeb,0x08,0x04 = rsb r4, r4, r8 0xc9,0xeb,0x08,0x04 = rsb r4, r9, r8 0xc4,0xeb,0xe8,0x01 = rsb r1, r4, r8, asr #3 0xd1,0xeb,0x47,0x02 = rsbs r2, r1, r7, lsl #1 // 0x94,0xfa,0x08,0xf3 = sadd16 r3, r4, r8 0x18,0xbf = it ne // 0x94,0xfa,0x08,0xf3 = sadd16ne r3, r4, r8 // 0x84,0xfa,0x08,0xf3 = sadd8 r3, r4, r8 0x18,0xbf = it ne // 0x84,0xfa,0x08,0xf3 = sadd8ne r3, r4, r8 0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7 0x18,0xbf = it ne // 0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6 0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7 0x18,0xbf = it ne // 0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6 0x61,0xf1,0x04,0x00 = sbc r0, r1, #4 0x71,0xf1,0x00,0x00 = sbcs r0, r1, #0 0x62,0xf1,0xff,0x01 = sbc r1, r2, #255 0x67,0xf1,0x55,0x13 = sbc r3, r7, #5570645 0x6c,0xf1,0xaa,0x28 = sbc r8, r12, #2852170240 0x67,0xf1,0xa5,0x39 = sbc r9, r7, #2779096485 0x63,0xf1,0x07,0x45 = sbc r5, r3, #2264924160 0x62,0xf1,0xff,0x44 = sbc r4, r2, #2139095040 0x62,0xf5,0xd0,0x64 = sbc r4, r2, #1664 0x65,0xeb,0x06,0x04 = sbc.w r4, r5, r6 0x75,0xeb,0x06,0x04 = sbcs.w r4, r5, r6 0x61,0xeb,0x03,0x09 = sbc.w r9, r1, r3 0x71,0xeb,0x03,0x09 = sbcs.w r9, r1, r3 0x61,0xeb,0x33,0x10 = sbc.w r0, r1, r3, ror #4 0x71,0xeb,0xc3,0x10 = sbcs.w r0, r1, r3, lsl #7 0x61,0xeb,0xd3,0x70 = sbc.w r0, r1, r3, lsr #31 0x71,0xeb,0x23,0x00 = sbcs.w r0, r1, r3, asr #32 0x45,0xf3,0x00,0x44 = sbfx r4, r5, #16, #1 0xc8,0xbf = it gt // 0x45,0xf3,0x0f,0x44 = sbfxgt r4, r5, #16, #16 // 0xa9,0xfa,0x82,0xf5 = sel r5, r9, r2 0xd8,0xbf = it le // 0xa9,0xfa,0x82,0xf5 = selle r5, r9, r2 // 0xaf,0xf3,0x04,0x80 = sev.w 0x08,0xbf = it eq // 0xaf,0xf3,0x04,0x80 = seveq.w // 0x92,0xfa,0x03,0xf1 = sadd16 r1, r2, r3 // 0x82,0xfa,0x03,0xf1 = sadd8 r1, r2, r3 0xcc,0xbf = ite gt // 0x92,0xfa,0x03,0xf1 = sadd16gt r1, r2, r3 // 0x82,0xfa,0x03,0xf1 = sadd8le r1, r2, r3 // 0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2 0xc8,0xbf = it gt // 0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2 // 0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2 0xc8,0xbf = it gt // 0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2 // 0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2 0xc8,0xbf = it gt // 0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2 // 0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2 0xc8,0xbf = it gt // 0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2 // 0xd8,0xfa,0x22,0xf4 = shsub16 r4, r8, r2 // 0xc8,0xfa,0x22,0xf4 = shsub8 r4, r8, r2 0xc4,0xbf = itt gt // 0xd8,0xfa,0x22,0xf4 = shsub16gt r4, r8, r2 // 0xc8,0xfa,0x22,0xf4 = shsub8gt r4, r8, r2 // 0x11,0xfb,0x09,0x03 = smlabb r3, r1, r9, r0 // 0x16,0xfb,0x14,0x15 = smlabt r5, r6, r4, r1 // 0x12,0xfb,0x23,0x24 = smlatb r4, r2, r3, r2 // 0x13,0xfb,0x38,0x48 = smlatt r8, r3, r8, r4 0xcb,0xbf = itete gt // 0x11,0xfb,0x09,0x03 = smlabbgt r3, r1, r9, r0 // 0x16,0xfb,0x14,0x15 = smlabtle r5, r6, r4, r1 // 0x12,0xfb,0x23,0x24 = smlatbgt r4, r2, r3, r2 // 0x13,0xfb,0x38,0x48 = smlattle r8, r3, r8, r4 // 0x23,0xfb,0x05,0x82 = smlad r2, r3, r5, r8 // 0x23,0xfb,0x15,0x82 = smladx r2, r3, r5, r8 0x84,0xbf = itt hi // 0x23,0xfb,0x05,0x82 = smladhi r2, r3, r5, r8 // 0x23,0xfb,0x15,0x82 = smladxhi r2, r3, r5, r8 // 0xc5,0xfb,0x08,0x23 = smlal r2, r3, r5, r8 0x08,0xbf = it eq // 0xc5,0xfb,0x08,0x23 = smlaleq r2, r3, r5, r8 // 0xc9,0xfb,0x80,0x31 = smlalbb r3, r1, r9, r0 // 0xc4,0xfb,0x91,0x56 = smlalbt r5, r6, r4, r1 // 0xc3,0xfb,0xa2,0x42 = smlaltb r4, r2, r3, r2 // 0xc8,0xfb,0xb4,0x83 = smlaltt r8, r3, r8, r4 0xad,0xbf = iteet ge // 0xc9,0xfb,0x80,0x31 = smlalbbge r3, r1, r9, r0 // 0xc4,0xfb,0x91,0x56 = smlalbtlt r5, r6, r4, r1 // 0xc3,0xfb,0xa2,0x42 = smlaltblt r4, r2, r3, r2 // 0xc8,0xfb,0xb4,0x83 = smlalttge r8, r3, r8, r4 // 0xc5,0xfb,0xc8,0x23 = smlald r2, r3, r5, r8 // 0xc5,0xfb,0xd8,0x23 = smlaldx r2, r3, r5, r8 0x0c,0xbf = ite eq // 0xc5,0xfb,0xc8,0x23 = smlaldeq r2, r3, r5, r8 // 0xc5,0xfb,0xd8,0x23 = smlaldxne r2, r3, r5, r8 0x33,0xfb,0x0a,0x82 = smlawb r2, r3, r10, r8 0x33,0xfb,0x15,0x98 = smlawt r8, r3, r5, r9 0x0c,0xbf = ite eq // 0x37,0xfb,0x05,0x82 = smlawbeq r2, r7, r5, r8 // 0x33,0xfb,0x10,0x81 = smlawtne r1, r3, r0, r8 // 0x43,0xfb,0x05,0x82 = smlsd r2, r3, r5, r8 // 0x43,0xfb,0x15,0x82 = smlsdx r2, r3, r5, r8 0xd4,0xbf = ite le // 0x43,0xfb,0x05,0x82 = smlsdle r2, r3, r5, r8 // 0x43,0xfb,0x15,0x82 = smlsdxgt r2, r3, r5, r8 0xd5,0xfb,0xc1,0x29 = smlsld r2, r9, r5, r1 0xd2,0xfb,0xd8,0x4b = smlsldx r4, r11, r2, r8 0xac,0xbf = ite ge // 0xd5,0xfb,0xc6,0x82 = smlsldge r8, r2, r5, r6 // 0xd3,0xfb,0xd8,0x10 = smlsldxlt r1, r0, r3, r8 // 0x52,0xfb,0x03,0x41 = smmla r1, r2, r3, r4 // 0x53,0xfb,0x12,0x14 = smmlar r4, r3, r2, r1 0x34,0xbf = ite lo // 0x52,0xfb,0x03,0x41 = smmlalo r1, r2, r3, r4 // 0x53,0xfb,0x12,0x14 = smmlarhs r4, r3, r2, r1 // 0x62,0xfb,0x03,0x41 = smmls r1, r2, r3, r4 // 0x63,0xfb,0x12,0x14 = smmlsr r4, r3, r2, r1 0x34,0xbf = ite lo // 0x62,0xfb,0x03,0x41 = smmlslo r1, r2, r3, r4 // 0x63,0xfb,0x12,0x14 = smmlsrhs r4, r3, r2, r1 // 0x53,0xfb,0x04,0xf2 = smmul r2, r3, r4 // 0x52,0xfb,0x11,0xf3 = smmulr r3, r2, r1 0x34,0xbf = ite lo // 0x53,0xfb,0x04,0xf2 = smmullo r2, r3, r4 // 0x52,0xfb,0x11,0xf3 = smmulrhs r3, r2, r1 // 0x23,0xfb,0x04,0xf2 = smuad r2, r3, r4 // 0x22,0xfb,0x11,0xf3 = smuadx r3, r2, r1 0xb4,0xbf = ite lt // 0x23,0xfb,0x04,0xf2 = smuadlt r2, r3, r4 // 0x22,0xfb,0x11,0xf3 = smuadxge r3, r2, r1 0x19,0xfb,0x00,0xf3 = smulbb r3, r9, r0 0x14,0xfb,0x11,0xf5 = smulbt r5, r4, r1 0x12,0xfb,0x22,0xf4 = smultb r4, r2, r2 // 0x13,0xfb,0x34,0xf8 = smultt r8, r3, r4 0xab,0xbf = itete ge // 0x19,0xfb,0x00,0xf1 = smulbbge r1, r9, r0 // 0x16,0xfb,0x14,0xf5 = smulbtlt r5, r6, r4 // 0x13,0xfb,0x22,0xf2 = smultbge r2, r3, r2 // 0x13,0xfb,0x34,0xf8 = smulttlt r8, r3, r4 0x80,0xfb,0x01,0x39 = smull r3, r9, r0, r1 0x08,0xbf = it eq // 0x84,0xfb,0x05,0x83 = smulleq r8, r3, r4, r5 // 0x39,0xfb,0x00,0xf3 = smulwb r3, r9, r0 // 0x39,0xfb,0x12,0xf3 = smulwt r3, r9, r2 0xcc,0xbf = ite gt // 0x39,0xfb,0x00,0xf3 = smulwbgt r3, r9, r0 // 0x39,0xfb,0x12,0xf3 = smulwtle r3, r9, r2 0x40,0xfb,0x01,0xf3 = smusd r3, r0, r1 0x49,0xfb,0x12,0xf3 = smusdx r3, r9, r2 0x0c,0xbf = ite eq // 0x43,0xfb,0x02,0xf8 = smusdeq r8, r3, r2 // 0x44,0xfb,0x13,0xf7 = smusdxne r7, r4, r3 0x0d,0xe8,0x01,0xc0 = srsdb sp, #1 0x8d,0xe9,0x00,0xc0 = srsia sp, #0 0x2d,0xe8,0x13,0xc0 = srsdb sp!, #19 0xad,0xe9,0x02,0xc0 = srsia sp!, #2 0x8d,0xe9,0x0a,0xc0 = srsia sp, #10 0x0d,0xe8,0x09,0xc0 = srsdb sp, #9 0xad,0xe9,0x05,0xc0 = srsia sp!, #5 0x2d,0xe8,0x05,0xc0 = srsdb sp!, #5 0x8d,0xe9,0x05,0xc0 = srsia sp, #5 0xad,0xe9,0x05,0xc0 = srsia sp!, #5 0x0d,0xe8,0x01,0xc0 = srsdb sp, #1 0x8d,0xe9,0x00,0xc0 = srsia sp, #0 0x2d,0xe8,0x13,0xc0 = srsdb sp!, #19 0xad,0xe9,0x02,0xc0 = srsia sp!, #2 0x8d,0xe9,0x0a,0xc0 = srsia sp, #10 0x0d,0xe8,0x09,0xc0 = srsdb sp, #9 0xad,0xe9,0x05,0xc0 = srsia sp!, #5 0x2d,0xe8,0x05,0xc0 = srsdb sp!, #5 0x8d,0xe9,0x05,0xc0 = srsia sp, #5 0xad,0xe9,0x05,0xc0 = srsia sp!, #5 0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10 0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10 0x0a,0xf3,0xc0,0x78 = ssat r8, #1, r10, lsl #31 0x2a,0xf3,0x40,0x08 = ssat r8, #1, r10, asr #1 0x27,0xf3,0x00,0x02 = ssat16 r2, #1, r7 0x25,0xf3,0x0f,0x03 = ssat16 r3, #16, r5 // 0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4 0xb8,0xbf = it lt // 0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4 // 0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4 0xb8,0xbf = it lt // 0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4 0xd0,0xfa,0x06,0xf1 = ssub16 r1, r0, r6 0xc2,0xfa,0x04,0xf9 = ssub8 r9, r2, r4 0x14,0xbf = ite ne // 0xd3,0xfa,0x02,0xf5 = ssub16ne r5, r3, r2 // 0xc1,0xfa,0x02,0xf5 = ssub8eq r5, r1, r2 0x81,0xfd,0x01,0x80 = stc2 p0, c8, [r1, #4] 0x82,0xfd,0x00,0x71 = stc2 p1, c7, [r2] 0x03,0xfd,0x38,0x62 = stc2 p2, c6, [r3, #-224] 0x24,0xfd,0x1e,0x53 = stc2 p3, c5, [r4, #-120]! 0xa5,0xfc,0x04,0x44 = stc2 p4, c4, [r5], #16 0x26,0xfc,0x12,0x35 = stc2 p5, c3, [r6], #-72 0xc7,0xfd,0x01,0x26 = stc2l p6, c2, [r7, #4] 0xc8,0xfd,0x00,0x17 = stc2l p7, c1, [r8] 0x49,0xfd,0x38,0x08 = stc2l p8, c0, [r9, #-224] 0x6a,0xfd,0x1e,0x19 = stc2l p9, c1, [r10, #-120]! 0xeb,0xfc,0x04,0x20 = stc2l p0, c2, [r11], #16 0x6c,0xfc,0x12,0x31 = stc2l p1, c3, [r12], #-72 0x80,0xed,0x01,0x4c = stc p12, c4, [r0, #4] 0x81,0xed,0x00,0x5d = stc p13, c5, [r1] 0x02,0xed,0x38,0x6e = stc p14, c6, [r2, #-224] 0x23,0xed,0x1e,0x7f = stc p15, c7, [r3, #-120]! 0xa4,0xec,0x04,0x85 = stc p5, c8, [r4], #16 0x25,0xec,0x12,0x94 = stc p4, c9, [r5], #-72 0xc6,0xed,0x01,0xa3 = stcl p3, c10, [r6, #4] 0xc7,0xed,0x00,0xb2 = stcl p2, c11, [r7] 0x48,0xed,0x38,0xc1 = stcl p1, c12, [r8, #-224] 0x69,0xed,0x1e,0xd0 = stcl p0, c13, [r9, #-120]! 0xea,0xec,0x04,0xe6 = stcl p6, c14, [r10], #16 0x6b,0xec,0x12,0xf7 = stcl p7, c15, [r11], #-72 0x81,0xfc,0x19,0x82 = stc2 p2, c8, [r1], {25} 0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} 0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} 0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} 0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} 0xa5,0xe8,0x06,0x00 = stm.w r5!, {r1, r2} 0x82,0xe8,0x06,0x00 = stm.w r2, {r1, r2} 0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} 0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} 0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9} 0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6} 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} 0x04,0xe9,0x30,0x03 = stmdb r4, {r4, r5, r8, r9} 0x04,0xe9,0x60,0x00 = stmdb r4, {r5, r6} 0x25,0xe9,0x08,0x01 = stmdb r5!, {r3, r8} 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8} 0x05,0xe9,0x03,0x00 = stmdb r5, {r0, r1} 0x45,0xf8,0x04,0x5c = str r5, [r5, #-4] 0x35,0x62 = str r5, [r6, #32] 0xc6,0xf8,0x21,0x50 = str.w r5, [r6, #33] 0xc6,0xf8,0x01,0x51 = str.w r5, [r6, #257] 0xc7,0xf8,0x01,0xf1 = str.w pc, [r7, #257] 0x44,0xf8,0xff,0x2f = str r2, [r4, #255]! 0x4d,0xf8,0x04,0x8f = str r8, [sp, #4]! 0x4d,0xf8,0x04,0xed = str lr, [sp, #-4]! 0x44,0xf8,0xff,0x2b = str r2, [r4], #255 0x4d,0xf8,0x04,0x8b = str r8, [sp], #4 0x4d,0xf8,0x04,0xe9 = str lr, [sp], #-4 0x48,0xf8,0x01,0x10 = str.w r1, [r8, r1] 0x45,0xf8,0x02,0x40 = str.w r4, [r5, r2] 0x40,0xf8,0x32,0x60 = str.w r6, [r0, r2, lsl #3] 0x48,0xf8,0x22,0x80 = str.w r8, [r8, r2, lsl #2] 0x4d,0xf8,0x12,0x70 = str.w r7, [sp, r2, lsl #1] 0x4d,0xf8,0x02,0x70 = str.w r7, [sp, r2] 0x05,0xf8,0x04,0x5c = strb r5, [r5, #-4] 0x86,0xf8,0x20,0x50 = strb.w r5, [r6, #32] 0x86,0xf8,0x21,0x50 = strb.w r5, [r6, #33] 0x86,0xf8,0x01,0x51 = strb.w r5, [r6, #257] 0x87,0xf8,0x01,0xe1 = strb.w lr, [r7, #257] 0x08,0xf8,0xff,0x5f = strb r5, [r8, #255]! 0x05,0xf8,0x04,0x2f = strb r2, [r5, #4]! 0x04,0xf8,0x04,0x1d = strb r1, [r4, #-4]! 0x03,0xf8,0xff,0xeb = strb lr, [r3], #255 0x02,0xf8,0x04,0x9b = strb r9, [r2], #4 0x0d,0xf8,0x04,0x39 = strb r3, [sp], #-4 0x08,0xf8,0x00,0x4d = strb r4, [r8, #-0]! 0x00,0xf8,0x00,0x19 = strb r1, [r0], #-0 0x08,0xf8,0x01,0x10 = strb.w r1, [r8, r1] 0x05,0xf8,0x02,0x40 = strb.w r4, [r5, r2] 0x00,0xf8,0x32,0x60 = strb.w r6, [r0, r2, lsl #3] 0x08,0xf8,0x22,0x80 = strb.w r8, [r8, r2, lsl #2] 0x0d,0xf8,0x12,0x70 = strb.w r7, [sp, r2, lsl #1] 0x0d,0xf8,0x02,0x70 = strb.w r7, [sp, r2] 0x02,0xf8,0x00,0x1e = strbt r1, [r2] 0x08,0xf8,0x00,0x1e = strbt r1, [r8] 0x08,0xf8,0x03,0x1e = strbt r1, [r8, #3] 0x08,0xf8,0xff,0x1e = strbt r1, [r8, #255] 0xc6,0xe9,0x06,0x35 = strd r3, r5, [r6, #24] 0xe6,0xe9,0x06,0x35 = strd r3, r5, [r6, #24]! 0xe6,0xe8,0x01,0x35 = strd r3, r5, [r6], #4 0x66,0xe8,0x02,0x35 = strd r3, r5, [r6], #-8 0xc6,0xe9,0x00,0x35 = strd r3, r5, [r6] 0xc3,0xe9,0x00,0x81 = strd r8, r1, [r3] 0x42,0xe9,0x00,0x01 = strd r0, r1, [r2, #-0] 0x62,0xe9,0x00,0x01 = strd r0, r1, [r2, #-0]! 0x62,0xe8,0x00,0x01 = strd r0, r1, [r2], #-0 0x44,0xe8,0x00,0x81 = strex r1, r8, [r4] 0x44,0xe8,0x00,0x28 = strex r8, r2, [r4] 0x4d,0xe8,0x20,0xc2 = strex r2, ip, [sp, #128] 0xc7,0xe8,0x45,0x1f = strexb r5, r1, [r7] 0xcc,0xe8,0x59,0x7f = strexh r9, r7, [r12] 0xc4,0xe8,0x79,0x36 = strexd r9, r3, r6, [r4] 0x25,0xf8,0x04,0x5c = strh r5, [r5, #-4] 0x35,0x84 = strh r5, [r6, #32] 0xa6,0xf8,0x21,0x50 = strh.w r5, [r6, #33] 0xa6,0xf8,0x01,0x51 = strh.w r5, [r6, #257] 0xa7,0xf8,0x01,0xe1 = strh.w lr, [r7, #257] 0x28,0xf8,0xff,0x5f = strh r5, [r8, #255]! 0x25,0xf8,0x04,0x2f = strh r2, [r5, #4]! 0x24,0xf8,0x04,0x1d = strh r1, [r4, #-4]! 0x23,0xf8,0xff,0xeb = strh lr, [r3], #255 0x22,0xf8,0x04,0x9b = strh r9, [r2], #4 0x2d,0xf8,0x04,0x39 = strh r3, [sp], #-4 0x28,0xf8,0x01,0x10 = strh.w r1, [r8, r1] 0x25,0xf8,0x02,0x40 = strh.w r4, [r5, r2] 0x20,0xf8,0x32,0x60 = strh.w r6, [r0, r2, lsl #3] 0x28,0xf8,0x22,0x80 = strh.w r8, [r8, r2, lsl #2] 0x2d,0xf8,0x12,0x70 = strh.w r7, [sp, r2, lsl #1] 0x2d,0xf8,0x02,0x70 = strh.w r7, [sp, r2] 0x22,0xf8,0x00,0x1e = strht r1, [r2] 0x28,0xf8,0x00,0x1e = strht r1, [r8] 0x28,0xf8,0x03,0x1e = strht r1, [r8, #3] 0x28,0xf8,0xff,0x1e = strht r1, [r8, #255] 0x42,0xf8,0x00,0x1e = strt r1, [r2] 0x48,0xf8,0x00,0x1e = strt r1, [r8] 0x48,0xf8,0x03,0x1e = strt r1, [r8, #3] 0x48,0xf8,0xff,0x1e = strt r1, [r8, #255] 0x0a,0xbf = itet eq // 0x11,0x1f = subeq r1, r2, #4 // 0xa3,0xf2,0xff,0x35 = subwne r5, r3, #1023 // 0xa5,0xf2,0x25,0x14 = subweq r4, r5, #293 0xad,0xf5,0x80,0x62 = sub.w r2, sp, #1024 0xa8,0xf5,0x7f,0x42 = sub.w r2, r8, #65280 0xa3,0xf2,0x01,0x12 = subw r2, r3, #257 0xa3,0xf2,0x01,0x12 = subw r2, r3, #257 0xa6,0xf5,0x80,0x7c = sub.w r12, r6, #256 0xa6,0xf2,0x00,0x1c = subw r12, r6, #256 0xb2,0xf5,0xf8,0x71 = subs.w r1, r2, #496 0xa2,0xf1,0x01,0x02 = sub.w r2, r2, #1 0xa0,0xf1,0x20,0x00 = sub.w r0, r0, #32 0x38,0x3a = subs r2, #56 0x38,0x3a = subs r2, #56 0xa5,0xeb,0x06,0x04 = sub.w r4, r5, r6 0xa5,0xeb,0x46,0x14 = sub.w r4, r5, r6, lsl #5 0xa5,0xeb,0x56,0x14 = sub.w r4, r5, r6, lsr #5 0xa5,0xeb,0x56,0x14 = sub.w r4, r5, r6, lsr #5 0xa5,0xeb,0x66,0x14 = sub.w r4, r5, r6, asr #5 0xa5,0xeb,0x76,0x14 = sub.w r4, r5, r6, ror #5 0xa2,0xeb,0x3c,0x05 = sub.w r5, r2, r12, rrx 0xad,0xeb,0x0c,0x02 = sub.w r2, sp, ip 0xad,0xeb,0x0c,0x0d = sub.w sp, sp, ip 0xad,0xeb,0x0c,0x02 = sub.w r2, sp, ip 0xad,0xeb,0x0c,0x0d = sub.w sp, sp, ip 0x00,0xdf = svc #0 0x0c,0xbf = ite eq // 0xff,0xdf = svceq #255 // 0x21,0xdf = svcne #33 0x43,0xfa,0x84,0xf2 = sxtab r2, r3, r4 0x45,0xfa,0x86,0xf4 = sxtab r4, r5, r6 0xb8,0xbf = it lt // 0x42,0xfa,0x99,0xf6 = sxtablt r6, r2, r9, ror #8 0x41,0xfa,0xa4,0xf5 = sxtab r5, r1, r4, ror #16 0x48,0xfa,0xb3,0xf7 = sxtab r7, r8, r3, ror #24 0x22,0xfa,0x87,0xf6 = sxtab16 r6, r2, r7 0x25,0xfa,0x98,0xf3 = sxtab16 r3, r5, r8, ror #8 0x22,0xfa,0xa1,0xf3 = sxtab16 r3, r2, r1, ror #16 0x14,0xbf = ite ne // 0x21,0xfa,0x84,0xf0 = sxtab16ne r0, r1, r4 // 0x22,0xfa,0xb3,0xf1 = sxtab16eq r1, r2, r3, ror #24 0x03,0xfa,0x89,0xf1 = sxtah r1, r3, r9 0x08,0xfa,0x93,0xf3 = sxtah r3, r8, r3, ror #8 0x03,0xfa,0xb3,0xf9 = sxtah r9, r3, r3, ror #24 0x8c,0xbf = ite hi // 0x01,0xfa,0x86,0xf6 = sxtahhi r6, r1, r6 // 0x02,0xfa,0xa4,0xf2 = sxtahls r2, r2, r4, ror #16 0x75,0xb2 = sxtb r5, r6 0x4f,0xfa,0x99,0xf6 = sxtb.w r6, r9, ror #8 0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #24 0xac,0xbf = ite ge // 0x62,0xb2 = sxtbge r2, r4 // 0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #16 0x4f,0xfa,0x88,0xf7 = sxtb.w r7, r8 0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4 0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7 0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #16 0x2c,0xbf = ite hs // 0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8 // 0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #24 0x31,0xb2 = sxth r1, r6 0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8 0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #24 0x1c,0xbf = itt ne // 0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9 // 0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #16 0x0f,0xfa,0x88,0xf7 = sxth.w r7, r8 0x75,0xb2 = sxtb r5, r6 0x4f,0xfa,0x99,0xf6 = sxtb.w r6, r9, ror #8 0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #24 0xac,0xbf = ite ge // 0x62,0xb2 = sxtbge r2, r4 // 0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #16 0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4 0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7 0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #16 0x2c,0xbf = ite hs // 0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8 // 0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #24 0x31,0xb2 = sxth r1, r6 0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8 0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #24 0x1c,0xbf = itt ne // 0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9 // 0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #16 // 0xd3,0xe8,0x08,0xf0 = tbb [r3, r8] // 0xd3,0xe8,0x18,0xf0 = tbh [r3, r8, lsl #1] 0x08,0xbf = it eq // 0xd3,0xe8,0x08,0xf0 = tbbeq [r3, r8] 0x28,0xbf = it hs // 0xd3,0xe8,0x18,0xf0 = tbhhs [r3, r8, lsl #1] 0x95,0xf4,0x70,0x4f = teq.w r5, #61440 0x94,0xea,0x05,0x0f = teq.w r4, r5 0x94,0xea,0x45,0x1f = teq.w r4, r5, lsl #5 0x94,0xea,0x55,0x1f = teq.w r4, r5, lsr #5 0x94,0xea,0x55,0x1f = teq.w r4, r5, lsr #5 0x94,0xea,0x65,0x1f = teq.w r4, r5, asr #5 0x94,0xea,0x75,0x1f = teq.w r4, r5, ror #5 0x15,0xf4,0x70,0x4f = tst.w r5, #61440 0x2a,0x42 = tst r2, r5 0x13,0xea,0x4c,0x1f = tst.w r3, r12, lsl #5 0x14,0xea,0x1b,0x1f = tst.w r4, r11, lsr #4 0x15,0xea,0x1a,0x3f = tst.w r5, r10, lsr #12 0x16,0xea,0xa9,0x7f = tst.w r6, r9, asr #30 0x17,0xea,0xb8,0x0f = tst.w r7, r8, ror #2 // 0x92,0xfa,0x43,0xf1 = uadd16 r1, r2, r3 // 0x82,0xfa,0x43,0xf1 = uadd8 r1, r2, r3 0xcc,0xbf = ite gt // 0x92,0xfa,0x43,0xf1 = uadd16gt r1, r2, r3 // 0x82,0xfa,0x43,0xf1 = uadd8le r1, r2, r3 // 0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0 0x08,0xbf = it eq // 0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0 // 0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0 0x08,0xbf = it eq // 0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0 0xc5,0xf3,0x00,0x44 = ubfx r4, r5, #16, #1 0xc8,0xbf = it gt // 0xc5,0xf3,0x0f,0x44 = ubfxgt r4, r5, #16, #16 // 0x98,0xfa,0x62,0xf4 = uhadd16 r4, r8, r2 // 0x88,0xfa,0x62,0xf4 = uhadd8 r4, r8, r2 0xc4,0xbf = itt gt // 0x98,0xfa,0x62,0xf4 = uhadd16gt r4, r8, r2 // 0x88,0xfa,0x62,0xf4 = uhadd8gt r4, r8, r2 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5 0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6 0xc4,0xbf = itt gt // 0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8 // 0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5 0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6 0xc4,0xbf = itt gt // 0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8 // 0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12 0xd8,0xfa,0x63,0xf5 = uhsub16 r5, r8, r3 0xc7,0xfa,0x66,0xf1 = uhsub8 r1, r7, r6 0xbc,0xbf = itt lt // 0xd9,0xfa,0x6c,0xf4 = uhsub16lt r4, r9, r12 // 0xc1,0xfa,0x65,0xf3 = uhsub8lt r3, r1, r5 // 0xe5,0xfb,0x66,0x34 = umaal r3, r4, r5, r6 0xb8,0xbf = it lt // 0xe5,0xfb,0x66,0x34 = umaallt r3, r4, r5, r6 0xe6,0xfb,0x08,0x24 = umlal r2, r4, r6, r8 0xc8,0xbf = it gt // 0xe2,0xfb,0x06,0x61 = umlalgt r6, r1, r2, r6 0xa6,0xfb,0x08,0x24 = umull r2, r4, r6, r8 0xc8,0xbf = it gt // 0xa2,0xfb,0x06,0x61 = umullgt r6, r1, r2, r6 0x92,0xfa,0x53,0xf1 = uqadd16 r1, r2, r3 0x84,0xfa,0x58,0xf3 = uqadd8 r3, r4, r8 0xcc,0xbf = ite gt // 0x97,0xfa,0x59,0xf4 = uqadd16gt r4, r7, r9 // 0x81,0xfa,0x52,0xf8 = uqadd8le r8, r1, r2 0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3 0xe4,0xfa,0x58,0xf3 = uqsax r3, r4, r8 0xcc,0xbf = ite gt // 0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9 // 0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2 0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3 0xe4,0xfa,0x58,0xf3 = uqsax r3, r4, r8 0xcc,0xbf = ite gt // 0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9 // 0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2 0xc2,0xfa,0x59,0xf8 = uqsub8 r8, r2, r9 0xd9,0xfa,0x57,0xf1 = uqsub16 r1, r9, r7 0xcc,0xbf = ite gt // 0xc1,0xfa,0x56,0xf3 = uqsub8gt r3, r1, r6 // 0xd6,0xfa,0x54,0xf4 = uqsub16le r4, r6, r4 0x79,0xfb,0x07,0xf1 = usad8 r1, r9, r7 0x72,0xfb,0x09,0xc8 = usada8 r8, r2, r9, r12 0xcc,0xbf = ite gt // 0x71,0xfb,0x06,0x93 = usada8gt r3, r1, r6, r9 // 0x76,0xfb,0x04,0xf4 = usad8le r4, r6, r4 0x8a,0xf3,0x01,0x08 = usat r8, #1, r10 0x8a,0xf3,0x04,0x08 = usat r8, #4, r10 0x8a,0xf3,0xc5,0x78 = usat r8, #5, r10, lsl #31 0xaa,0xf3,0x50,0x08 = usat r8, #16, r10, asr #1 0xa7,0xf3,0x02,0x02 = usat16 r2, #2, r7 0xa5,0xf3,0x0f,0x03 = usat16 r3, #15, r5 0xe3,0xfa,0x44,0xf2 = usax r2, r3, r4 0x18,0xbf = it ne // 0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9 0xe3,0xfa,0x44,0xf2 = usax r2, r3, r4 0x18,0xbf = it ne // 0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9 0xd2,0xfa,0x47,0xf4 = usub16 r4, r2, r7 0xc8,0xfa,0x45,0xf1 = usub8 r1, r8, r5 0x8c,0xbf = ite hi // 0xd1,0xfa,0x43,0xf1 = usub16hi r1, r1, r3 // 0xc2,0xfa,0x43,0xf9 = usub8ls r9, r2, r3 0x53,0xfa,0x84,0xf2 = uxtab r2, r3, r4 0x55,0xfa,0x86,0xf4 = uxtab r4, r5, r6 0xb8,0xbf = it lt // 0x52,0xfa,0x99,0xf6 = uxtablt r6, r2, r9, ror #8 0x51,0xfa,0xa4,0xf5 = uxtab r5, r1, r4, ror #16 0x58,0xfa,0xb3,0xf7 = uxtab r7, r8, r3, ror #24 0xa8,0xbf = it ge // 0x31,0xfa,0x84,0xf0 = uxtab16ge r0, r1, r4 0x32,0xfa,0x87,0xf6 = uxtab16 r6, r2, r7 0x35,0xfa,0x98,0xf3 = uxtab16 r3, r5, r8, ror #8 0x32,0xfa,0xa1,0xf3 = uxtab16 r3, r2, r1, ror #16 0x08,0xbf = it eq // 0x32,0xfa,0xb3,0xf1 = uxtab16eq r1, r2, r3, ror #24 0x13,0xfa,0x89,0xf1 = uxtah r1, r3, r9 0x88,0xbf = it hi // 0x11,0xfa,0x86,0xf6 = uxtahhi r6, r1, r6 0x18,0xfa,0x93,0xf3 = uxtah r3, r8, r3, ror #8 0x38,0xbf = it lo // 0x12,0xfa,0xa4,0xf2 = uxtahlo r2, r2, r4, ror #16 0x13,0xfa,0xb3,0xf9 = uxtah r9, r3, r3, ror #24 0xa8,0xbf = it ge // 0xe2,0xb2 = uxtbge r2, r4 0xf5,0xb2 = uxtb r5, r6 0x5f,0xfa,0x99,0xf6 = uxtb.w r6, r9, ror #8 0x38,0xbf = it lo // 0x5f,0xfa,0xa1,0xf5 = uxtblo.w r5, r1, ror #16 0x5f,0xfa,0xb3,0xf8 = uxtb.w r8, r3, ror #24 0x5f,0xfa,0x88,0xf7 = uxtb.w r7, r8 0x3f,0xfa,0x84,0xf1 = uxtb16 r1, r4 0x3f,0xfa,0x87,0xf6 = uxtb16 r6, r7 0x28,0xbf = it hs // 0x3f,0xfa,0x95,0xf3 = uxtb16hs r3, r5, ror #8 0x3f,0xfa,0xa1,0xf3 = uxtb16 r3, r1, ror #16 0xa8,0xbf = it ge // 0x3f,0xfa,0xb3,0xf2 = uxtb16ge r2, r3, ror #24 0x18,0xbf = it ne // 0x1f,0xfa,0x89,0xf3 = uxthne.w r3, r9 0xb1,0xb2 = uxth r1, r6 0x1f,0xfa,0x98,0xf3 = uxth.w r3, r8, ror #8 0xd8,0xbf = it le // 0x1f,0xfa,0xa2,0xf2 = uxthle.w r2, r2, ror #16 0x1f,0xfa,0xb3,0xf9 = uxth.w r9, r3, ror #24 0x1f,0xfa,0x88,0xf7 = uxth.w r7, r8 // 0x20,0xbf = wfe // 0x30,0xbf = wfi // 0x10,0xbf = yield 0xb6,0xbf = itet lt // 0x20,0xbf = wfelt // 0x30,0xbf = wfige // 0x10,0xbf = yieldlt // 0xaf,0xf3,0x04,0x80 = sev.w 0xaf,0xf3,0x03,0x80 = wfi.w 0xaf,0xf3,0x02,0x80 = wfe.w 0xaf,0xf3,0x01,0x80 = yield.w 0xaf,0xf3,0x00,0x80 = nop.w 0x40,0xbf = sev // 0x30,0xbf = wfi // 0x20,0xbf = wfe // 0x10,0xbf = yield // 0x00,0xbf = nop 0xb6,0xbf = itet lt // 0xf0,0xbf = hintlt #15 // 0xaf,0xf3,0x10,0x80 = hintge.w #16 // 0xaf,0xf3,0xef,0x80 = hintlt.w #239 0x70,0xbf = hint #7 0xaf,0xf3,0x07,0x80 = hint.w #7 0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #22] 0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #22] 0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #22] 0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #22] 0xdf,0xf8,0x16,0xb0 = ldr.w r11, [pc, #22] 0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #22] 0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #22] 0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #22] 0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #22] 0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-22] 0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-22] 0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-22] 0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-22] 0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-22] 0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-22] 0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-22] 0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-22] 0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-22] 0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-22] 0x03,0x49 = ldr r1, [pc, #12] 0xde,0xf3,0x04,0x8f = subs pc, lr, #4 capstone-sys-0.15.0/capstone/suite/MC/ARM/crc32-thumb.s.cs000064400000000000000000000004410072674642500210720ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 0xc1,0xfa,0x82,0xf0 = crc32b r0, r1, r2 0xc1,0xfa,0x92,0xf0 = crc32h r0, r1, r2 0xc1,0xfa,0xa2,0xf0 = crc32w r0, r1, r2 0xd1,0xfa,0x82,0xf0 = crc32cb r0, r1, r2 0xd1,0xfa,0x92,0xf0 = crc32ch r0, r1, r2 0xd1,0xfa,0xa2,0xf0 = crc32cw r0, r1, r2 capstone-sys-0.15.0/capstone/suite/MC/ARM/crc32.s.cs000064400000000000000000000004370072674642500177620ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0x42,0x00,0x01,0xe1 = crc32b r0, r1, r2 0x42,0x00,0x21,0xe1 = crc32h r0, r1, r2 0x42,0x00,0x41,0xe1 = crc32w r0, r1, r2 0x42,0x02,0x01,0xe1 = crc32cb r0, r1, r2 0x42,0x02,0x21,0xe1 = crc32ch r0, r1, r2 0x42,0x02,0x41,0xe1 = crc32cw r0, r1, r2 capstone-sys-0.15.0/capstone/suite/MC/ARM/dot-req.s.cs000064400000000000000000000001440072674642500204140ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x05,0xb0,0xa0,0xe1 = mov r11, r5 0x06,0x10,0xa0,0xe1 = mov r1, r6 capstone-sys-0.15.0/capstone/suite/MC/ARM/fp-armv8.s.cs000064400000000000000000000043160072674642500205060ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0xe0,0x3b,0xb2,0xee = vcvtt.f64.f16 d3, s1 0xcc,0x2b,0xf3,0xee = vcvtt.f16.f64 s5, d12 0x60,0x3b,0xb2,0xee = vcvtb.f64.f16 d3, s1 0x41,0x2b,0xb3,0xee = vcvtb.f16.f64 s4, d1 0xe0,0x3b,0xb2,0xae = vcvttge.f64.f16 d3, s1 0xcc,0x2b,0xf3,0xce = vcvttgt.f16.f64 s5, d12 0x60,0x3b,0xb2,0x0e = vcvtbeq.f64.f16 d3, s1 0x41,0x2b,0xb3,0xbe = vcvtblt.f16.f64 s4, d1 0xe1,0x1a,0xbc,0xfe = vcvta.s32.f32 s2, s3 0xc3,0x1b,0xbc,0xfe = vcvta.s32.f64 s2, d3 0xeb,0x3a,0xbd,0xfe = vcvtn.s32.f32 s6, s23 0xe7,0x3b,0xbd,0xfe = vcvtn.s32.f64 s6, d23 0xc2,0x0a,0xbe,0xfe = vcvtp.s32.f32 s0, s4 0xc4,0x0b,0xbe,0xfe = vcvtp.s32.f64 s0, d4 0xc4,0x8a,0xff,0xfe = vcvtm.s32.f32 s17, s8 0xc8,0x8b,0xff,0xfe = vcvtm.s32.f64 s17, d8 0x61,0x1a,0xbc,0xfe = vcvta.u32.f32 s2, s3 0x43,0x1b,0xbc,0xfe = vcvta.u32.f64 s2, d3 0x6b,0x3a,0xbd,0xfe = vcvtn.u32.f32 s6, s23 0x67,0x3b,0xbd,0xfe = vcvtn.u32.f64 s6, d23 0x42,0x0a,0xbe,0xfe = vcvtp.u32.f32 s0, s4 0x44,0x0b,0xbe,0xfe = vcvtp.u32.f64 s0, d4 0x44,0x8a,0xff,0xfe = vcvtm.u32.f32 s17, s8 0x48,0x8b,0xff,0xfe = vcvtm.u32.f64 s17, d8 0xab,0x2a,0x20,0xfe = vselge.f32 s4, s1, s23 0xa7,0xeb,0x6f,0xfe = vselge.f64 d30, d31, d23 0x80,0x0a,0x30,0xfe = vselgt.f32 s0, s1, s0 0x24,0x5b,0x3a,0xfe = vselgt.f64 d5, d10, d20 0x2b,0xfa,0x0e,0xfe = vseleq.f32 s30, s28, s23 0x08,0x2b,0x04,0xfe = vseleq.f64 d2, d4, d8 0x07,0xaa,0x58,0xfe = vselvs.f32 s21, s16, s14 0x2f,0x0b,0x11,0xfe = vselvs.f64 d0, d1, d31 0x00,0x2a,0xc6,0xfe = vmaxnm.f32 s5, s12, s0 0xae,0x5b,0x86,0xfe = vmaxnm.f64 d5, d22, d30 0x46,0x0a,0x80,0xfe = vminnm.f32 s0, s0, s12 0x49,0x4b,0x86,0xfe = vminnm.f64 d4, d6, d9 0xcc,0x3b,0xb6,0xae = vrintzge.f64 d3, d12 0xcc,0x1a,0xf6,0xee = vrintz.f32 s3, s24 0x40,0x5b,0xb6,0xbe = vrintrlt.f64 d5, d0 0x64,0x0a,0xb6,0xee = vrintr.f32 s0, s9 0x6e,0xcb,0xf7,0x0e = vrintxeq.f64 d28, d30 0x47,0x5a,0xb7,0x6e = vrintxvs.f32 s10, s14 0x44,0x3b,0xb8,0xfe = vrinta.f64 d3, d4 0x60,0x6a,0xb8,0xfe = vrinta.f32 s12, s1 0x44,0x3b,0xb9,0xfe = vrintn.f64 d3, d4 0x60,0x6a,0xb9,0xfe = vrintn.f32 s12, s1 0x44,0x3b,0xba,0xfe = vrintp.f64 d3, d4 0x60,0x6a,0xba,0xfe = vrintp.f32 s12, s1 0x44,0x3b,0xbb,0xfe = vrintm.f64 d3, d4 0x60,0x6a,0xbb,0xfe = vrintm.f32 s12, s1 0x10,0xda,0xf5,0xee = vmrs sp, mvfr2 capstone-sys-0.15.0/capstone/suite/MC/ARM/fpv8.s.cs000064400000000000000000000031160072674642500177260ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16 0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16 0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16 0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7 0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16 0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17 0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16 0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16 0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0 0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16 0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16 0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0 0x60,0x0b,0xf1,0xee = vneg.f64 d16, d16 0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16 0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0 0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0 0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16 0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16 0xa1,0x0b,0x42,0xee = vmla.f64 d16, d18, d17 0xe1,0x0b,0x42,0xee = vmls.f64 d16, d18, d17 0xe1,0x0b,0x52,0xee = vnmla.f64 d16, d18, d17 0xa1,0x0b,0x52,0xee = vnmls.f64 d16, d18, d17 0x60,0x0b,0xf1,0x1e = vnegne.f64 d16, d16 0x08,0x0b,0xf0,0xee = vmov.f64 d16, #3.000000e+00 0x08,0x0b,0xf8,0xee = vmov.f64 d16, #-3.000000e+00 0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0 0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0 0xc0,0x0b,0xba,0xee = vcvt.f64.s32 d0, d0, #32 0x40,0x0b,0xba,0xee = vcvt.f64.s16 d0, d0, #16 0xc0,0x4b,0xfb,0xee = vcvt.f64.u32 d20, d20, #32 0x40,0x7b,0xfb,0xee = vcvt.f64.u16 d23, d23, #16 0xc0,0x2b,0xbe,0xee = vcvt.s32.f64 d2, d2, #32 0x40,0xfb,0xbe,0xee = vcvt.s16.f64 d15, d15, #16 0xc0,0x4b,0xff,0xee = vcvt.u32.f64 d20, d20, #32 0x40,0x7b,0xff,0xee = vcvt.u16.f64 d23, d23, #16 capstone-sys-0.15.0/capstone/suite/MC/ARM/idiv-thumb.s.cs000064400000000000000000000001570072674642500211150ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3 0xb4,0xfb,0xf5,0xf3 = udiv r3, r4, r5 capstone-sys-0.15.0/capstone/suite/MC/ARM/idiv.s.cs000064400000000000000000000001550072674642500177760ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x12,0xf3,0x11,0xe7 = sdiv r1, r2, r3 0x14,0xf5,0x33,0xe7 = udiv r3, r4, r5 capstone-sys-0.15.0/capstone/suite/MC/ARM/load-store-acquire-release-v8-thumb.s.cs000064400000000000000000000011130072674642500256240ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 0xd4,0xe8,0xcf,0x3f = ldaexb r3, [r4] 0xd5,0xe8,0xdf,0x2f = ldaexh r2, [r5] 0xd7,0xe8,0xef,0x1f = ldaex r1, [r7] 0xd8,0xe8,0xff,0x67 = ldaexd r6, r7, [r8] 0xc4,0xe8,0xc1,0x3f = stlexb r1, r3, [r4] 0xc5,0xe8,0xd4,0x2f = stlexh r4, r2, [r5] 0xc7,0xe8,0xe2,0x1f = stlex r2, r1, [r7] 0xc8,0xe8,0xf6,0x23 = stlexd r6, r2, r3, [r8] 0xd6,0xe8,0xaf,0x5f = lda r5, [r6] 0xd6,0xe8,0x8f,0x5f = ldab r5, [r6] 0xd9,0xe8,0x9f,0xcf = ldah r12, [r9] 0xc0,0xe8,0xaf,0x3f = stl r3, [r0] 0xc1,0xe8,0x8f,0x2f = stlb r2, [r1] 0xc3,0xe8,0x9f,0x2f = stlh r2, [r3] capstone-sys-0.15.0/capstone/suite/MC/ARM/load-store-acquire-release-v8.s.cs000064400000000000000000000011110072674642500245050ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0x9f,0x3e,0xd4,0xe1 = ldaexb r3, [r4] 0x9f,0x2e,0xf5,0xe1 = ldaexh r2, [r5] 0x9f,0x1e,0x97,0xe1 = ldaex r1, [r7] 0x9f,0x6e,0xb8,0xe1 = ldaexd r6, r7, [r8] 0x93,0x1e,0xc4,0xe1 = stlexb r1, r3, [r4] 0x92,0x4e,0xe5,0xe1 = stlexh r4, r2, [r5] 0x91,0x2e,0x87,0xe1 = stlex r2, r1, [r7] 0x92,0x6e,0xa8,0xe1 = stlexd r6, r2, r3, [r8] 0x9f,0x5c,0x96,0xe1 = lda r5, [r6] 0x9f,0x5c,0xd6,0xe1 = ldab r5, [r6] 0x9f,0xcc,0xf9,0xe1 = ldah r12, [r9] 0x93,0xfc,0x80,0xe1 = stl r3, [r0] 0x92,0xfc,0xc1,0xe1 = stlb r2, [r1] 0x92,0xfc,0xe3,0xe1 = stlh r2, [r3] capstone-sys-0.15.0/capstone/suite/MC/ARM/mode-switch.s.cs000064400000000000000000000002510072674642500212630ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1 0x40,0x18 = adds r0, r0, r1 0x00,0xeb,0x01,0x00 = add.w r0, r0, r1 0x40,0x18 = adds r0, r0, r1 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-abs-encoding.s.cs000064400000000000000000000011050072674642500223250ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x20,0x03,0xf1,0xf3 = vabs.s8 d16, d16 0x20,0x03,0xf5,0xf3 = vabs.s16 d16, d16 0x20,0x03,0xf9,0xf3 = vabs.s32 d16, d16 0x20,0x07,0xf9,0xf3 = vabs.f32 d16, d16 0x60,0x03,0xf1,0xf3 = vabs.s8 q8, q8 0x60,0x03,0xf5,0xf3 = vabs.s16 q8, q8 0x60,0x03,0xf9,0xf3 = vabs.s32 q8, q8 0x60,0x07,0xf9,0xf3 = vabs.f32 q8, q8 0x20,0x07,0xf0,0xf3 = vqabs.s8 d16, d16 0x20,0x07,0xf4,0xf3 = vqabs.s16 d16, d16 0x20,0x07,0xf8,0xf3 = vqabs.s32 d16, d16 0x60,0x07,0xf0,0xf3 = vqabs.s8 q8, q8 0x60,0x07,0xf4,0xf3 = vqabs.s16 q8, q8 0x60,0x07,0xf8,0xf3 = vqabs.s32 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-absdiff-encoding.s.cs000064400000000000000000000032420072674642500231620ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa1,0x07,0x40,0xf2 = vabd.s8 d16, d16, d17 0xa1,0x07,0x50,0xf2 = vabd.s16 d16, d16, d17 0xa1,0x07,0x60,0xf2 = vabd.s32 d16, d16, d17 0xa1,0x07,0x40,0xf3 = vabd.u8 d16, d16, d17 0xa1,0x07,0x50,0xf3 = vabd.u16 d16, d16, d17 0xa1,0x07,0x60,0xf3 = vabd.u32 d16, d16, d17 0xa1,0x0d,0x60,0xf3 = vabd.f32 d16, d16, d17 0xe2,0x07,0x40,0xf2 = vabd.s8 q8, q8, q9 0xe2,0x07,0x50,0xf2 = vabd.s16 q8, q8, q9 0xe2,0x07,0x60,0xf2 = vabd.s32 q8, q8, q9 0xe2,0x07,0x40,0xf3 = vabd.u8 q8, q8, q9 0xe2,0x07,0x50,0xf3 = vabd.u16 q8, q8, q9 0xe2,0x07,0x60,0xf3 = vabd.u32 q8, q8, q9 0xe2,0x0d,0x60,0xf3 = vabd.f32 q8, q8, q9 0xa1,0x07,0xc0,0xf2 = vabdl.s8 q8, d16, d17 0xa1,0x07,0xd0,0xf2 = vabdl.s16 q8, d16, d17 0xa1,0x07,0xe0,0xf2 = vabdl.s32 q8, d16, d17 0xa1,0x07,0xc0,0xf3 = vabdl.u8 q8, d16, d17 0xa1,0x07,0xd0,0xf3 = vabdl.u16 q8, d16, d17 0xa1,0x07,0xe0,0xf3 = vabdl.u32 q8, d16, d17 0xb1,0x07,0x42,0xf2 = vaba.s8 d16, d18, d17 0xb1,0x07,0x52,0xf2 = vaba.s16 d16, d18, d17 0xb1,0x07,0x62,0xf2 = vaba.s32 d16, d18, d17 0xb1,0x07,0x42,0xf3 = vaba.u8 d16, d18, d17 0xb1,0x07,0x52,0xf3 = vaba.u16 d16, d18, d17 0xb1,0x07,0x62,0xf3 = vaba.u32 d16, d18, d17 0xf4,0x27,0x40,0xf2 = vaba.s8 q9, q8, q10 0xf4,0x27,0x50,0xf2 = vaba.s16 q9, q8, q10 0xf4,0x27,0x60,0xf2 = vaba.s32 q9, q8, q10 0xf4,0x27,0x40,0xf3 = vaba.u8 q9, q8, q10 0xf4,0x27,0x50,0xf3 = vaba.u16 q9, q8, q10 0xf4,0x27,0x60,0xf3 = vaba.u32 q9, q8, q10 0xa2,0x05,0xc3,0xf2 = vabal.s8 q8, d19, d18 0xa2,0x05,0xd3,0xf2 = vabal.s16 q8, d19, d18 0xa2,0x05,0xe3,0xf2 = vabal.s32 q8, d19, d18 0xa2,0x05,0xc3,0xf3 = vabal.u8 q8, d19, d18 0xa2,0x05,0xd3,0xf3 = vabal.u16 q8, d19, d18 0xa2,0x05,0xe3,0xf3 = vabal.u32 q8, d19, d18 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-add-encoding.s.cs000064400000000000000000000122070072674642500223150ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa0,0x08,0x41,0xf2 = vadd.i8 d16, d17, d16 0xa0,0x08,0x51,0xf2 = vadd.i16 d16, d17, d16 0xa0,0x08,0x71,0xf2 = vadd.i64 d16, d17, d16 0xa0,0x08,0x61,0xf2 = vadd.i32 d16, d17, d16 0xa1,0x0d,0x40,0xf2 = vadd.f32 d16, d16, d17 0xe2,0x0d,0x40,0xf2 = vadd.f32 q8, q8, q9 0xa0,0x00,0xc1,0xf2 = vaddl.s8 q8, d17, d16 0xa0,0x00,0xd1,0xf2 = vaddl.s16 q8, d17, d16 0xa0,0x00,0xe1,0xf2 = vaddl.s32 q8, d17, d16 0xa0,0x00,0xc1,0xf3 = vaddl.u8 q8, d17, d16 0xa0,0x00,0xd1,0xf3 = vaddl.u16 q8, d17, d16 0xa0,0x00,0xe1,0xf3 = vaddl.u32 q8, d17, d16 0xa2,0x01,0xc0,0xf2 = vaddw.s8 q8, q8, d18 0xa2,0x01,0xd0,0xf2 = vaddw.s16 q8, q8, d18 0xa2,0x01,0xe0,0xf2 = vaddw.s32 q8, q8, d18 0xa2,0x01,0xc0,0xf3 = vaddw.u8 q8, q8, d18 0xa2,0x01,0xd0,0xf3 = vaddw.u16 q8, q8, d18 0xa2,0x01,0xe0,0xf3 = vaddw.u32 q8, q8, d18 0xa1,0x00,0x40,0xf2 = vhadd.s8 d16, d16, d17 0xa1,0x00,0x50,0xf2 = vhadd.s16 d16, d16, d17 0xa1,0x00,0x60,0xf2 = vhadd.s32 d16, d16, d17 0xa1,0x00,0x40,0xf3 = vhadd.u8 d16, d16, d17 0xa1,0x00,0x50,0xf3 = vhadd.u16 d16, d16, d17 0xa1,0x00,0x60,0xf3 = vhadd.u32 d16, d16, d17 0xe2,0x00,0x40,0xf2 = vhadd.s8 q8, q8, q9 0xe2,0x00,0x50,0xf2 = vhadd.s16 q8, q8, q9 0xe2,0x00,0x60,0xf2 = vhadd.s32 q8, q8, q9 0xe2,0x00,0x40,0xf3 = vhadd.u8 q8, q8, q9 0xe2,0x00,0x50,0xf3 = vhadd.u16 q8, q8, q9 0xe2,0x00,0x60,0xf3 = vhadd.u32 q8, q8, q9 0x28,0xb0,0x0b,0xf2 = vhadd.s8 d11, d11, d24 0x27,0xc0,0x1c,0xf2 = vhadd.s16 d12, d12, d23 0x26,0xd0,0x2d,0xf2 = vhadd.s32 d13, d13, d22 0x25,0xe0,0x0e,0xf3 = vhadd.u8 d14, d14, d21 0x24,0xf0,0x1f,0xf3 = vhadd.u16 d15, d15, d20 0xa3,0x00,0x60,0xf3 = vhadd.u32 d16, d16, d19 0x68,0x20,0x02,0xf2 = vhadd.s8 q1, q1, q12 0x66,0x40,0x14,0xf2 = vhadd.s16 q2, q2, q11 0x64,0x60,0x26,0xf2 = vhadd.s32 q3, q3, q10 0x62,0x80,0x08,0xf3 = vhadd.u8 q4, q4, q9 0x60,0xa0,0x1a,0xf3 = vhadd.u16 q5, q5, q8 0x4e,0xc0,0x2c,0xf3 = vhadd.u32 q6, q6, q7 0xa1,0x01,0x40,0xf2 = vrhadd.s8 d16, d16, d17 0xa1,0x01,0x50,0xf2 = vrhadd.s16 d16, d16, d17 0xa1,0x01,0x60,0xf2 = vrhadd.s32 d16, d16, d17 0xa1,0x01,0x40,0xf3 = vrhadd.u8 d16, d16, d17 0xa1,0x01,0x50,0xf3 = vrhadd.u16 d16, d16, d17 0xa1,0x01,0x60,0xf3 = vrhadd.u32 d16, d16, d17 0xe2,0x01,0x40,0xf2 = vrhadd.s8 q8, q8, q9 0xe2,0x01,0x50,0xf2 = vrhadd.s16 q8, q8, q9 0xe2,0x01,0x60,0xf2 = vrhadd.s32 q8, q8, q9 0xe2,0x01,0x40,0xf3 = vrhadd.u8 q8, q8, q9 0xe2,0x01,0x50,0xf3 = vrhadd.u16 q8, q8, q9 0xe2,0x01,0x60,0xf3 = vrhadd.u32 q8, q8, q9 0xa1,0x01,0x40,0xf2 = vrhadd.s8 d16, d16, d17 0xa1,0x01,0x50,0xf2 = vrhadd.s16 d16, d16, d17 0xa1,0x01,0x60,0xf2 = vrhadd.s32 d16, d16, d17 0xa1,0x01,0x40,0xf3 = vrhadd.u8 d16, d16, d17 0xa1,0x01,0x50,0xf3 = vrhadd.u16 d16, d16, d17 0xa1,0x01,0x60,0xf3 = vrhadd.u32 d16, d16, d17 0xe2,0x01,0x40,0xf2 = vrhadd.s8 q8, q8, q9 0xe2,0x01,0x50,0xf2 = vrhadd.s16 q8, q8, q9 0xe2,0x01,0x60,0xf2 = vrhadd.s32 q8, q8, q9 0xe2,0x01,0x40,0xf3 = vrhadd.u8 q8, q8, q9 0xe2,0x01,0x50,0xf3 = vrhadd.u16 q8, q8, q9 0xe2,0x01,0x60,0xf3 = vrhadd.u32 q8, q8, q9 0xb1,0x00,0x40,0xf2 = vqadd.s8 d16, d16, d17 0xb1,0x00,0x50,0xf2 = vqadd.s16 d16, d16, d17 0xb1,0x00,0x60,0xf2 = vqadd.s32 d16, d16, d17 0xb1,0x00,0x70,0xf2 = vqadd.s64 d16, d16, d17 0xb1,0x00,0x40,0xf3 = vqadd.u8 d16, d16, d17 0xb1,0x00,0x50,0xf3 = vqadd.u16 d16, d16, d17 0xb1,0x00,0x60,0xf3 = vqadd.u32 d16, d16, d17 0xb1,0x00,0x70,0xf3 = vqadd.u64 d16, d16, d17 0xf2,0x00,0x40,0xf2 = vqadd.s8 q8, q8, q9 0xf2,0x00,0x50,0xf2 = vqadd.s16 q8, q8, q9 0xf2,0x00,0x60,0xf2 = vqadd.s32 q8, q8, q9 0xf2,0x00,0x70,0xf2 = vqadd.s64 q8, q8, q9 0xf2,0x00,0x40,0xf3 = vqadd.u8 q8, q8, q9 0xf2,0x00,0x50,0xf3 = vqadd.u16 q8, q8, q9 0xf2,0x00,0x60,0xf3 = vqadd.u32 q8, q8, q9 0xf2,0x00,0x70,0xf3 = vqadd.u64 q8, q8, q9 0xb1,0x00,0x40,0xf2 = vqadd.s8 d16, d16, d17 0xb1,0x00,0x50,0xf2 = vqadd.s16 d16, d16, d17 0xb1,0x00,0x60,0xf2 = vqadd.s32 d16, d16, d17 0xb1,0x00,0x70,0xf2 = vqadd.s64 d16, d16, d17 0xb1,0x00,0x40,0xf3 = vqadd.u8 d16, d16, d17 0xb1,0x00,0x50,0xf3 = vqadd.u16 d16, d16, d17 0xb1,0x00,0x60,0xf3 = vqadd.u32 d16, d16, d17 0xb1,0x00,0x70,0xf3 = vqadd.u64 d16, d16, d17 0xf2,0x00,0x40,0xf2 = vqadd.s8 q8, q8, q9 0xf2,0x00,0x50,0xf2 = vqadd.s16 q8, q8, q9 0xf2,0x00,0x60,0xf2 = vqadd.s32 q8, q8, q9 0xf2,0x00,0x70,0xf2 = vqadd.s64 q8, q8, q9 0xf2,0x00,0x40,0xf3 = vqadd.u8 q8, q8, q9 0xf2,0x00,0x50,0xf3 = vqadd.u16 q8, q8, q9 0xf2,0x00,0x60,0xf3 = vqadd.u32 q8, q8, q9 0xf2,0x00,0x70,0xf3 = vqadd.u64 q8, q8, q9 0xa2,0x04,0xc0,0xf2 = vaddhn.i16 d16, q8, q9 0xa2,0x04,0xd0,0xf2 = vaddhn.i32 d16, q8, q9 0xa2,0x04,0xe0,0xf2 = vaddhn.i64 d16, q8, q9 0xa2,0x04,0xc0,0xf3 = vraddhn.i16 d16, q8, q9 0xa2,0x04,0xd0,0xf3 = vraddhn.i32 d16, q8, q9 0xa2,0x04,0xe0,0xf3 = vraddhn.i64 d16, q8, q9 0x05,0x68,0x06,0xf2 = vadd.i8 d6, d6, d5 0x01,0x78,0x17,0xf2 = vadd.i16 d7, d7, d1 0x02,0x88,0x28,0xf2 = vadd.i32 d8, d8, d2 0x03,0x98,0x39,0xf2 = vadd.i64 d9, d9, d3 0x4a,0xc8,0x0c,0xf2 = vadd.i8 q6, q6, q5 0x42,0xe8,0x1e,0xf2 = vadd.i16 q7, q7, q1 0xc4,0x08,0x60,0xf2 = vadd.i32 q8, q8, q2 0xc6,0x28,0x72,0xf2 = vadd.i64 q9, q9, q3 0x05,0xc1,0x8c,0xf2 = vaddw.s8 q6, q6, d5 0x01,0xe1,0x9e,0xf2 = vaddw.s16 q7, q7, d1 0x82,0x01,0xe0,0xf2 = vaddw.s32 q8, q8, d2 0x05,0xc1,0x8c,0xf3 = vaddw.u8 q6, q6, d5 0x01,0xe1,0x9e,0xf3 = vaddw.u16 q7, q7, d1 0x82,0x01,0xe0,0xf3 = vaddw.u32 q8, q8, d2 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-bitcount-encoding.s.cs000064400000000000000000000010730072674642500234130ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x20,0x05,0xf0,0xf3 = vcnt.8 d16, d16 0x60,0x05,0xf0,0xf3 = vcnt.8 q8, q8 0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16 0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16 0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8 0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8 0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16 0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16 0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16 0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8 0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8 0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-bitwise-encoding.s.cs000064400000000000000000000114710072674642500232350ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xb0,0x01,0x41,0xf2 = vand d16, d17, d16 0xf2,0x01,0x40,0xf2 = vand q8, q8, q9 0xb0,0x01,0x41,0xf3 = veor d16, d17, d16 0xf2,0x01,0x40,0xf3 = veor q8, q8, q9 0xb0,0x01,0x61,0xf2 = vorr d16, d17, d16 0xf2,0x01,0x60,0xf2 = vorr q8, q8, q9 0x11,0x07,0xc0,0xf2 = vorr.i32 d16, #0x1000000 0x51,0x07,0xc0,0xf2 = vorr.i32 q8, #0x1000000 0x50,0x01,0xc0,0xf2 = vorr.i32 q8, #0 0xb0,0x01,0x51,0xf2 = vbic d16, d17, d16 0xf2,0x01,0x50,0xf2 = vbic q8, q8, q9 0x3f,0x07,0xc7,0xf3 = vbic.i32 d16, #0xff000000 0x7f,0x07,0xc7,0xf3 = vbic.i32 q8, #0xff000000 0xf6,0x41,0x54,0xf2 = vbic q10, q10, q11 0x11,0x91,0x19,0xf2 = vbic d9, d9, d1 0xb0,0x01,0x71,0xf2 = vorn d16, d17, d16 0xf2,0x01,0x70,0xf2 = vorn q8, q8, q9 0xa0,0x05,0xf0,0xf3 = vmvn d16, d16 0xe0,0x05,0xf0,0xf3 = vmvn q8, q8 0xb0,0x21,0x51,0xf3 = vbsl d18, d17, d16 0xf2,0x01,0x54,0xf3 = vbsl q8, q10, q9 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x07,0xf2 = vand d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x13,0x41,0x27,0xf2 = vorr d4, d7, d3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x56,0x81,0x2e,0xf2 = vorr q4, q7, q3 0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5 0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5 0x52,0xe1,0x0e,0xf2 = vand q7, q7, q1 0xd4,0x01,0x40,0xf2 = vand q8, q8, q2 0xd4,0x01,0x40,0xf2 = vand q8, q8, q2 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 0x52,0xe1,0x0e,0xf3 = veor q7, q7, q1 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 0x52,0xe1,0x0e,0xf3 = veor q7, q7, q1 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 0xd4,0x01,0x40,0xf3 = veor q8, q8, q2 0x4a,0xa2,0xb5,0xf3 = vclt.s16 q5, q5, #0 0x05,0x52,0xb5,0xf3 = vclt.s16 d5, d5, #0 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3 0x46,0xa3,0x1a,0xf2 = vcgt.s16 q5, q5, q3 0x03,0x53,0x15,0xf2 = vcgt.s16 d5, d5, d3 0x56,0xa3,0x1a,0xf2 = vcge.s16 q5, q5, q3 0x13,0x53,0x15,0xf2 = vcge.s16 d5, d5, d3 0x4a,0xa0,0xb5,0xf3 = vcgt.s16 q5, q5, #0 0x05,0x50,0xb5,0xf3 = vcgt.s16 d5, d5, #0 0xca,0xa0,0xb5,0xf3 = vcge.s16 q5, q5, #0 0x85,0x50,0xb5,0xf3 = vcge.s16 d5, d5, #0 0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0 0xca,0xa1,0xb5,0xf3 = vcle.s16 q5, q5, #0 0x85,0x51,0xb5,0xf3 = vcle.s16 d5, d5, #0 0x3e,0x5e,0x05,0xf3 = vacge.f32 d5, d5, d30 0x56,0xae,0x0a,0xf3 = vacge.f32 q5, q5, q3 0x3e,0x5e,0x25,0xf3 = vacgt.f32 d5, d5, d30 0x56,0xae,0x2a,0xf3 = vacgt.f32 q5, q5, q3 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-cmp-encoding.s.cs000064400000000000000000000073500072674642500223470ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9 0xb1,0x03,0x40,0xf2 = vcge.s8 d16, d16, d17 0xb1,0x03,0x50,0xf2 = vcge.s16 d16, d16, d17 0xb1,0x03,0x60,0xf2 = vcge.s32 d16, d16, d17 0xb1,0x03,0x40,0xf3 = vcge.u8 d16, d16, d17 0xb1,0x03,0x50,0xf3 = vcge.u16 d16, d16, d17 0xb1,0x03,0x60,0xf3 = vcge.u32 d16, d16, d17 0xa1,0x0e,0x40,0xf3 = vcge.f32 d16, d16, d17 0xf2,0x03,0x40,0xf2 = vcge.s8 q8, q8, q9 0xf2,0x03,0x50,0xf2 = vcge.s16 q8, q8, q9 0xf2,0x03,0x60,0xf2 = vcge.s32 q8, q8, q9 0xf2,0x03,0x40,0xf3 = vcge.u8 q8, q8, q9 0xf2,0x03,0x50,0xf3 = vcge.u16 q8, q8, q9 0xf2,0x03,0x60,0xf3 = vcge.u32 q8, q8, q9 0xe2,0x0e,0x40,0xf3 = vcge.f32 q8, q8, q9 0xb1,0x0e,0x40,0xf3 = vacge.f32 d16, d16, d17 0xf2,0x0e,0x40,0xf3 = vacge.f32 q8, q8, q9 0xa1,0x03,0x40,0xf2 = vcgt.s8 d16, d16, d17 0xa1,0x03,0x50,0xf2 = vcgt.s16 d16, d16, d17 0xa1,0x03,0x60,0xf2 = vcgt.s32 d16, d16, d17 0xa1,0x03,0x40,0xf3 = vcgt.u8 d16, d16, d17 0xa1,0x03,0x50,0xf3 = vcgt.u16 d16, d16, d17 0xa1,0x03,0x60,0xf3 = vcgt.u32 d16, d16, d17 0xa1,0x0e,0x60,0xf3 = vcgt.f32 d16, d16, d17 0xe2,0x03,0x40,0xf2 = vcgt.s8 q8, q8, q9 0xe2,0x03,0x50,0xf2 = vcgt.s16 q8, q8, q9 0xe2,0x03,0x60,0xf2 = vcgt.s32 q8, q8, q9 0xe2,0x03,0x40,0xf3 = vcgt.u8 q8, q8, q9 0xe2,0x03,0x50,0xf3 = vcgt.u16 q8, q8, q9 0xe2,0x03,0x60,0xf3 = vcgt.u32 q8, q8, q9 0xe2,0x0e,0x60,0xf3 = vcgt.f32 q8, q8, q9 0xb1,0x0e,0x60,0xf3 = vacgt.f32 d16, d16, d17 0xf2,0x0e,0x60,0xf3 = vacgt.f32 q8, q8, q9 0xb1,0x08,0x40,0xf2 = vtst.8 d16, d16, d17 0xb1,0x08,0x50,0xf2 = vtst.16 d16, d16, d17 0xb1,0x08,0x60,0xf2 = vtst.32 d16, d16, d17 0xf2,0x08,0x40,0xf2 = vtst.8 q8, q8, q9 0xf2,0x08,0x50,0xf2 = vtst.16 q8, q8, q9 0xf2,0x08,0x60,0xf2 = vtst.32 q8, q8, q9 0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0 0xa0,0x00,0xf1,0xf3 = vcge.s8 d16, d16, #0 0xa0,0x01,0xf1,0xf3 = vcle.s8 d16, d16, #0 0x20,0x00,0xf1,0xf3 = vcgt.s8 d16, d16, #0 0x20,0x02,0xf1,0xf3 = vclt.s8 d16, d16, #0 0x6a,0x83,0x46,0xf2 = vcgt.s8 q12, q3, q13 0x6a,0x83,0x56,0xf2 = vcgt.s16 q12, q3, q13 0x6a,0x83,0x66,0xf2 = vcgt.s32 q12, q3, q13 0x6a,0x83,0x46,0xf3 = vcgt.u8 q12, q3, q13 0x6a,0x83,0x56,0xf3 = vcgt.u16 q12, q3, q13 0x6a,0x83,0x66,0xf3 = vcgt.u32 q12, q3, q13 0x6a,0x8e,0x66,0xf3 = vcgt.f32 q12, q3, q13 0x0d,0xc3,0x03,0xf2 = vcgt.s8 d12, d3, d13 0x0d,0xc3,0x13,0xf2 = vcgt.s16 d12, d3, d13 0x0d,0xc3,0x23,0xf2 = vcgt.s32 d12, d3, d13 0x0d,0xc3,0x03,0xf3 = vcgt.u8 d12, d3, d13 0x0d,0xc3,0x13,0xf3 = vcgt.u16 d12, d3, d13 0x0d,0xc3,0x23,0xf3 = vcgt.u32 d12, d3, d13 0x0d,0xce,0x23,0xf3 = vcgt.f32 d12, d3, d13 0xb0,0x03,0x41,0xf2 = vcge.s8 d16, d17, d16 0xb0,0x03,0x51,0xf2 = vcge.s16 d16, d17, d16 0xb0,0x03,0x61,0xf2 = vcge.s32 d16, d17, d16 0xb0,0x03,0x41,0xf3 = vcge.u8 d16, d17, d16 0xb0,0x03,0x51,0xf3 = vcge.u16 d16, d17, d16 0xb0,0x03,0x61,0xf3 = vcge.u32 d16, d17, d16 0xa0,0x0e,0x41,0xf3 = vcge.f32 d16, d17, d16 0xf0,0x03,0x42,0xf2 = vcge.s8 q8, q9, q8 0xf0,0x03,0x52,0xf2 = vcge.s16 q8, q9, q8 0xf0,0x03,0x62,0xf2 = vcge.s32 q8, q9, q8 0xf0,0x03,0x42,0xf3 = vcge.u8 q8, q9, q8 0xf0,0x03,0x52,0xf3 = vcge.u16 q8, q9, q8 0xf0,0x03,0x62,0xf3 = vcge.u32 q8, q9, q8 0xe0,0x0e,0x42,0xf3 = vcge.f32 q8, q9, q8 0xf6,0x2e,0x68,0xf3 = vacgt.f32 q9, q12, q11 0x1b,0x9e,0x2c,0xf3 = vacgt.f32 d9, d12, d11 0xf6,0x6e,0x68,0xf3 = vacgt.f32 q11, q12, q11 0x1b,0xbe,0x2c,0xf3 = vacgt.f32 d11, d12, d11 0xf6,0x2e,0x48,0xf3 = vacge.f32 q9, q12, q11 0x1b,0x9e,0x0c,0xf3 = vacge.f32 d9, d12, d11 0xf6,0x6e,0x48,0xf3 = vacge.f32 q11, q12, q11 0x1b,0xbe,0x0c,0xf3 = vacge.f32 d11, d12, d11 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-convert-encoding.s.cs000064400000000000000000000022370072674642500232470ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 0x30,0x0f,0xff,0xf2 = vcvt.s32.f32 d16, d16, #1 0x20,0x07,0xfb,0xf3 = vcvt.s32.f32 d16, d16 0x30,0x0f,0xff,0xf3 = vcvt.u32.f32 d16, d16, #1 0xa0,0x07,0xfb,0xf3 = vcvt.u32.f32 d16, d16 0x30,0x0e,0xff,0xf2 = vcvt.f32.s32 d16, d16, #1 0x20,0x06,0xfb,0xf3 = vcvt.f32.s32 d16, d16 0x30,0x0e,0xff,0xf3 = vcvt.f32.u32 d16, d16, #1 0xa0,0x06,0xfb,0xf3 = vcvt.f32.u32 d16, d16 0x70,0x0f,0xff,0xf2 = vcvt.s32.f32 q8, q8, #1 0x60,0x07,0xfb,0xf3 = vcvt.s32.f32 q8, q8 0x70,0x0f,0xff,0xf3 = vcvt.u32.f32 q8, q8, #1 0xe0,0x07,0xfb,0xf3 = vcvt.u32.f32 q8, q8 0x70,0x0e,0xff,0xf2 = vcvt.f32.s32 q8, q8, #1 0x60,0x06,0xfb,0xf3 = vcvt.f32.s32 q8, q8 0x70,0x0e,0xff,0xf3 = vcvt.f32.u32 q8, q8, #1 0xe0,0x06,0xfb,0xf3 = vcvt.f32.u32 q8, q8 0x20,0x07,0xf6,0xf3 = vcvt.f32.f16 q8, d16 0x20,0x06,0xf6,0xf3 = vcvt.f16.f32 d16, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-crypto.s.cs000064400000000000000000000012250072674642500213170ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0x42,0x03,0xb0,0xf3 = aesd.8 q0, q1 0x02,0x03,0xb0,0xf3 = aese.8 q0, q1 0xc2,0x03,0xb0,0xf3 = aesimc.8 q0, q1 0x82,0x03,0xb0,0xf3 = aesmc.8 q0, q1 0xc2,0x02,0xb9,0xf3 = sha1h.32 q0, q1 0x82,0x03,0xba,0xf3 = sha1su1.32 q0, q1 0xc2,0x03,0xba,0xf3 = sha256su0.32 q0, q1 0x44,0x0c,0x02,0xf2 = sha1c.32 q0, q1, q2 0x44,0x0c,0x22,0xf2 = sha1m.32 q0, q1, q2 0x44,0x0c,0x12,0xf2 = sha1p.32 q0, q1, q2 0x44,0x0c,0x32,0xf2 = sha1su0.32 q0, q1, q2 0x44,0x0c,0x02,0xf3 = sha256h.32 q0, q1, q2 0x44,0x0c,0x12,0xf3 = sha256h2.32 q0, q1, q2 0x44,0x0c,0x22,0xf3 = sha256su1.32 q0, q1, q2 0xa1,0x0e,0xe0,0xf2 = vmull.p64 q8, d16, d17 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-dup-encoding.s.cs000064400000000000000000000007670072674642500223650ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x90,0x0b,0xc0,0xee = vdup.8 d16, r0 0xb0,0x0b,0x80,0xee = vdup.16 d16, r0 0x90,0x0b,0x80,0xee = vdup.32 d16, r0 0x90,0x0b,0xe0,0xee = vdup.8 q8, r0 0xb0,0x0b,0xa0,0xee = vdup.16 q8, r0 0x90,0x0b,0xa0,0xee = vdup.32 q8, r0 0x20,0x0c,0xf3,0xf3 = vdup.8 d16, d16[1] 0x20,0x0c,0xf6,0xf3 = vdup.16 d16, d16[1] 0x20,0x0c,0xfc,0xf3 = vdup.32 d16, d16[1] 0x60,0x0c,0xf3,0xf3 = vdup.8 q8, d16[1] 0x60,0x0c,0xf6,0xf3 = vdup.16 q8, d16[1] 0x60,0x0c,0xfc,0xf3 = vdup.32 q8, d16[1] capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-minmax-encoding.s.cs000064400000000000000000000046010072674642500230550ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x03,0x16,0x02,0xf2 = vmax.s8 d1, d2, d3 0x06,0x46,0x15,0xf2 = vmax.s16 d4, d5, d6 0x09,0x76,0x28,0xf2 = vmax.s32 d7, d8, d9 0x0c,0xa6,0x0b,0xf3 = vmax.u8 d10, d11, d12 0x0f,0xd6,0x1e,0xf3 = vmax.u16 d13, d14, d15 0xa2,0x06,0x61,0xf3 = vmax.u32 d16, d17, d18 0xa5,0x3f,0x44,0xf2 = vmax.f32 d19, d20, d21 0x03,0x26,0x02,0xf2 = vmax.s8 d2, d2, d3 0x06,0x56,0x15,0xf2 = vmax.s16 d5, d5, d6 0x09,0x86,0x28,0xf2 = vmax.s32 d8, d8, d9 0x0c,0xb6,0x0b,0xf3 = vmax.u8 d11, d11, d12 0x0f,0xe6,0x1e,0xf3 = vmax.u16 d14, d14, d15 0xa2,0x16,0x61,0xf3 = vmax.u32 d17, d17, d18 0xa5,0x4f,0x44,0xf2 = vmax.f32 d20, d20, d21 0x46,0x26,0x04,0xf2 = vmax.s8 q1, q2, q3 0x4c,0x86,0x1a,0xf2 = vmax.s16 q4, q5, q6 0xe2,0xe6,0x20,0xf2 = vmax.s32 q7, q8, q9 0xe8,0x46,0x46,0xf3 = vmax.u8 q10, q11, q12 0xee,0xa6,0x5c,0xf3 = vmax.u16 q13, q14, q15 0x60,0xc6,0x2e,0xf3 = vmax.u32 q6, q7, q8 0x42,0x2f,0x4a,0xf2 = vmax.f32 q9, q5, q1 0x46,0x46,0x04,0xf2 = vmax.s8 q2, q2, q3 0x4c,0xa6,0x1a,0xf2 = vmax.s16 q5, q5, q6 0xe2,0x06,0x60,0xf2 = vmax.s32 q8, q8, q9 0xc4,0x66,0x46,0xf3 = vmax.u8 q11, q11, q2 0x4a,0x86,0x18,0xf3 = vmax.u16 q4, q4, q5 0x60,0xe6,0x2e,0xf3 = vmax.u32 q7, q7, q8 0x42,0x4f,0x04,0xf2 = vmax.f32 q2, q2, q1 0x13,0x16,0x02,0xf2 = vmin.s8 d1, d2, d3 0x16,0x46,0x15,0xf2 = vmin.s16 d4, d5, d6 0x19,0x76,0x28,0xf2 = vmin.s32 d7, d8, d9 0x1c,0xa6,0x0b,0xf3 = vmin.u8 d10, d11, d12 0x1f,0xd6,0x1e,0xf3 = vmin.u16 d13, d14, d15 0xb2,0x06,0x61,0xf3 = vmin.u32 d16, d17, d18 0xa5,0x3f,0x64,0xf2 = vmin.f32 d19, d20, d21 0x13,0x26,0x02,0xf2 = vmin.s8 d2, d2, d3 0x16,0x56,0x15,0xf2 = vmin.s16 d5, d5, d6 0x19,0x86,0x28,0xf2 = vmin.s32 d8, d8, d9 0x1c,0xb6,0x0b,0xf3 = vmin.u8 d11, d11, d12 0x1f,0xe6,0x1e,0xf3 = vmin.u16 d14, d14, d15 0xb2,0x16,0x61,0xf3 = vmin.u32 d17, d17, d18 0xa5,0x4f,0x64,0xf2 = vmin.f32 d20, d20, d21 0x56,0x26,0x04,0xf2 = vmin.s8 q1, q2, q3 0x5c,0x86,0x1a,0xf2 = vmin.s16 q4, q5, q6 0xf2,0xe6,0x20,0xf2 = vmin.s32 q7, q8, q9 0xf8,0x46,0x46,0xf3 = vmin.u8 q10, q11, q12 0xfe,0xa6,0x5c,0xf3 = vmin.u16 q13, q14, q15 0x70,0xc6,0x2e,0xf3 = vmin.u32 q6, q7, q8 0x42,0x2f,0x6a,0xf2 = vmin.f32 q9, q5, q1 0x56,0x46,0x04,0xf2 = vmin.s8 q2, q2, q3 0x5c,0xa6,0x1a,0xf2 = vmin.s16 q5, q5, q6 0xf2,0x06,0x60,0xf2 = vmin.s32 q8, q8, q9 0xd4,0x66,0x46,0xf3 = vmin.u8 q11, q11, q2 0x5a,0x86,0x18,0xf3 = vmin.u16 q4, q4, q5 0x70,0xe6,0x2e,0xf3 = vmin.u32 q7, q7, q8 0x42,0x4f,0x24,0xf2 = vmin.f32 q2, q2, q1 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-mov-encoding.s.cs000064400000000000000000000060040072674642500223640ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x18,0x0e,0xc0,0xf2 = vmov.i8 d16, #0x8 0x10,0x08,0xc1,0xf2 = vmov.i16 d16, #0x10 0x10,0x0a,0xc1,0xf2 = vmov.i16 d16, #0x1000 0x10,0x00,0xc2,0xf2 = vmov.i32 d16, #0x20 0x10,0x02,0xc2,0xf2 = vmov.i32 d16, #0x2000 0x10,0x04,0xc2,0xf2 = vmov.i32 d16, #0x200000 0x10,0x06,0xc2,0xf2 = vmov.i32 d16, #0x20000000 0x10,0x0c,0xc2,0xf2 = vmov.i32 d16, #0x20ff 0x10,0x0d,0xc2,0xf2 = vmov.i32 d16, #0x20ffff 0x33,0x0e,0xc1,0xf3 = vmov.i64 d16, #0xff0000ff0000ffff 0x58,0x0e,0xc0,0xf2 = vmov.i8 q8, #0x8 0x50,0x08,0xc1,0xf2 = vmov.i16 q8, #0x10 0x50,0x0a,0xc1,0xf2 = vmov.i16 q8, #0x1000 0x50,0x00,0xc2,0xf2 = vmov.i32 q8, #0x20 0x50,0x02,0xc2,0xf2 = vmov.i32 q8, #0x2000 0x50,0x04,0xc2,0xf2 = vmov.i32 q8, #0x200000 0x50,0x06,0xc2,0xf2 = vmov.i32 q8, #0x20000000 0x50,0x0c,0xc2,0xf2 = vmov.i32 q8, #0x20ff 0x50,0x0d,0xc2,0xf2 = vmov.i32 q8, #0x20ffff 0x73,0x0e,0xc1,0xf3 = vmov.i64 q8, #0xff0000ff0000ffff 0x30,0x08,0xc1,0xf2 = vmvn.i16 d16, #0x10 0x30,0x0a,0xc1,0xf2 = vmvn.i16 d16, #0x1000 0x30,0x00,0xc2,0xf2 = vmvn.i32 d16, #0x20 0x30,0x02,0xc2,0xf2 = vmvn.i32 d16, #0x2000 0x30,0x04,0xc2,0xf2 = vmvn.i32 d16, #0x200000 0x30,0x06,0xc2,0xf2 = vmvn.i32 d16, #0x20000000 0x30,0x0c,0xc2,0xf2 = vmvn.i32 d16, #0x20ff 0x30,0x0d,0xc2,0xf2 = vmvn.i32 d16, #0x20ffff 0x30,0x0a,0xc8,0xf2 = vmovl.s8 q8, d16 0x30,0x0a,0xd0,0xf2 = vmovl.s16 q8, d16 0x30,0x0a,0xe0,0xf2 = vmovl.s32 q8, d16 0x30,0x0a,0xc8,0xf3 = vmovl.u8 q8, d16 0x30,0x0a,0xd0,0xf3 = vmovl.u16 q8, d16 0x30,0x0a,0xe0,0xf3 = vmovl.u32 q8, d16 0x20,0x02,0xf2,0xf3 = vmovn.i16 d16, q8 0x20,0x02,0xf6,0xf3 = vmovn.i32 d16, q8 0x20,0x02,0xfa,0xf3 = vmovn.i64 d16, q8 0xa0,0x02,0xf2,0xf3 = vqmovn.s16 d16, q8 0xa0,0x02,0xf6,0xf3 = vqmovn.s32 d16, q8 0xa0,0x02,0xfa,0xf3 = vqmovn.s64 d16, q8 0xe0,0x02,0xf2,0xf3 = vqmovn.u16 d16, q8 0xe0,0x02,0xf6,0xf3 = vqmovn.u32 d16, q8 0xe0,0x02,0xfa,0xf3 = vqmovn.u64 d16, q8 0x60,0x02,0xf2,0xf3 = vqmovun.s16 d16, q8 0x60,0x02,0xf6,0xf3 = vqmovun.s32 d16, q8 0x60,0x02,0xfa,0xf3 = vqmovun.s64 d16, q8 0xb0,0x0b,0x50,0xee = vmov.s8 r0, d16[1] 0xf0,0x0b,0x10,0xee = vmov.s16 r0, d16[1] 0xb0,0x0b,0xd0,0xee = vmov.u8 r0, d16[1] 0xf0,0x0b,0x90,0xee = vmov.u16 r0, d16[1] 0x90,0x0b,0x30,0xee = vmov.32 r0, d16[1] 0xb0,0x1b,0x40,0xee = vmov.8 d16[1], r1 0xf0,0x1b,0x00,0xee = vmov.16 d16[1], r1 0x90,0x1b,0x20,0xee = vmov.32 d16[1], r1 0xb0,0x1b,0x42,0xee = vmov.8 d18[1], r1 0xf0,0x1b,0x02,0xee = vmov.16 d18[1], r1 0x90,0x1b,0x22,0xee = vmov.32 d18[1], r1 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 0x82,0x15,0xb0,0xf3 = vmvn d1, d2 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-mul-accum-encoding.s.cs000064400000000000000000000033250072674642500234510ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa1,0x09,0x42,0xf2 = vmla.i8 d16, d18, d17 0xa1,0x09,0x52,0xf2 = vmla.i16 d16, d18, d17 0xa1,0x09,0x62,0xf2 = vmla.i32 d16, d18, d17 0xb1,0x0d,0x42,0xf2 = vmla.f32 d16, d18, d17 0xe4,0x29,0x40,0xf2 = vmla.i8 q9, q8, q10 0xe4,0x29,0x50,0xf2 = vmla.i16 q9, q8, q10 0xe4,0x29,0x60,0xf2 = vmla.i32 q9, q8, q10 0xf4,0x2d,0x40,0xf2 = vmla.f32 q9, q8, q10 0xc3,0x80,0xe0,0xf3 = vmla.i32 q12, q8, d3[0] 0xa2,0x08,0xc3,0xf2 = vmlal.s8 q8, d19, d18 0xa2,0x08,0xd3,0xf2 = vmlal.s16 q8, d19, d18 0xa2,0x08,0xe3,0xf2 = vmlal.s32 q8, d19, d18 0xa2,0x08,0xc3,0xf3 = vmlal.u8 q8, d19, d18 0xa2,0x08,0xd3,0xf3 = vmlal.u16 q8, d19, d18 0xa2,0x08,0xe3,0xf3 = vmlal.u32 q8, d19, d18 0xa2,0x09,0xd3,0xf2 = vqdmlal.s16 q8, d19, d18 0xa2,0x09,0xe3,0xf2 = vqdmlal.s32 q8, d19, d18 0x47,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[0] 0x4f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[1] 0x67,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[2] 0x6f,0x63,0xdb,0xf2 = vqdmlal.s16 q11, d11, d7[3] 0xa1,0x09,0x42,0xf3 = vmls.i8 d16, d18, d17 0xa1,0x09,0x52,0xf3 = vmls.i16 d16, d18, d17 0xa1,0x09,0x62,0xf3 = vmls.i32 d16, d18, d17 0xb1,0x0d,0x62,0xf2 = vmls.f32 d16, d18, d17 0xe4,0x29,0x40,0xf3 = vmls.i8 q9, q8, q10 0xe4,0x29,0x50,0xf3 = vmls.i16 q9, q8, q10 0xe4,0x29,0x60,0xf3 = vmls.i32 q9, q8, q10 0xf4,0x2d,0x60,0xf2 = vmls.f32 q9, q8, q10 0xe6,0x84,0x98,0xf3 = vmls.i16 q4, q12, d6[2] 0xa2,0x0a,0xc3,0xf2 = vmlsl.s8 q8, d19, d18 0xa2,0x0a,0xd3,0xf2 = vmlsl.s16 q8, d19, d18 0xa2,0x0a,0xe3,0xf2 = vmlsl.s32 q8, d19, d18 0xa2,0x0a,0xc3,0xf3 = vmlsl.u8 q8, d19, d18 0xa2,0x0a,0xd3,0xf3 = vmlsl.u16 q8, d19, d18 0xa2,0x0a,0xe3,0xf3 = vmlsl.u32 q8, d19, d18 0xa2,0x0b,0xd3,0xf2 = vqdmlsl.s16 q8, d19, d18 0xa2,0x0b,0xe3,0xf2 = vqdmlsl.s32 q8, d19, d18 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-mul-encoding.s.cs000064400000000000000000000062220072674642500223620ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17 0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17 0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17 0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17 0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9 0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9 0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9 0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9 0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17 0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9 0x68,0x28,0xd8,0xf2 = vmul.i16 d18, d8, d0[3] 0xb1,0x09,0x40,0xf2 = vmul.i8 d16, d16, d17 0xb1,0x09,0x50,0xf2 = vmul.i16 d16, d16, d17 0xb1,0x09,0x60,0xf2 = vmul.i32 d16, d16, d17 0xb1,0x0d,0x40,0xf3 = vmul.f32 d16, d16, d17 0xf2,0x09,0x40,0xf2 = vmul.i8 q8, q8, q9 0xf2,0x09,0x50,0xf2 = vmul.i16 q8, q8, q9 0xf2,0x09,0x60,0xf2 = vmul.i32 q8, q8, q9 0xf2,0x0d,0x40,0xf3 = vmul.f32 q8, q8, q9 0xb1,0x09,0x40,0xf3 = vmul.p8 d16, d16, d17 0xf2,0x09,0x40,0xf3 = vmul.p8 q8, q8, q9 0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17 0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17 0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9 0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9 0xa1,0x0b,0x50,0xf2 = vqdmulh.s16 d16, d16, d17 0xa1,0x0b,0x60,0xf2 = vqdmulh.s32 d16, d16, d17 0xe2,0x0b,0x50,0xf2 = vqdmulh.s16 q8, q8, q9 0xe2,0x0b,0x60,0xf2 = vqdmulh.s32 q8, q8, q9 0x43,0xbc,0x92,0xf2 = vqdmulh.s16 d11, d2, d3[0] 0xa1,0x0b,0x50,0xf3 = vqrdmulh.s16 d16, d16, d17 0xa1,0x0b,0x60,0xf3 = vqrdmulh.s32 d16, d16, d17 0xe2,0x0b,0x50,0xf3 = vqrdmulh.s16 q8, q8, q9 0xe2,0x0b,0x60,0xf3 = vqrdmulh.s32 q8, q8, q9 0xa1,0x0c,0xc0,0xf2 = vmull.s8 q8, d16, d17 0xa1,0x0c,0xd0,0xf2 = vmull.s16 q8, d16, d17 0xa1,0x0c,0xe0,0xf2 = vmull.s32 q8, d16, d17 0xa1,0x0c,0xc0,0xf3 = vmull.u8 q8, d16, d17 0xa1,0x0c,0xd0,0xf3 = vmull.u16 q8, d16, d17 0xa1,0x0c,0xe0,0xf3 = vmull.u32 q8, d16, d17 0xa1,0x0e,0xc0,0xf2 = vmull.p8 q8, d16, d17 0xa1,0x0d,0xd0,0xf2 = vqdmull.s16 q8, d16, d17 0xa1,0x0d,0xe0,0xf2 = vqdmull.s32 q8, d16, d17 0x64,0x08,0x90,0xf2 = vmul.i16 d0, d0, d4[2] 0x6f,0x18,0x91,0xf2 = vmul.i16 d1, d1, d7[3] 0x49,0x28,0x92,0xf2 = vmul.i16 d2, d2, d1[1] 0x42,0x38,0xa3,0xf2 = vmul.i32 d3, d3, d2[0] 0x63,0x48,0xa4,0xf2 = vmul.i32 d4, d4, d3[1] 0x44,0x58,0xa5,0xf2 = vmul.i32 d5, d5, d4[0] 0x65,0x69,0xa6,0xf2 = vmul.f32 d6, d6, d5[1] 0x64,0x08,0x90,0xf3 = vmul.i16 q0, q0, d4[2] 0x6f,0x28,0x92,0xf3 = vmul.i16 q1, q1, d7[3] 0x49,0x48,0x94,0xf3 = vmul.i16 q2, q2, d1[1] 0x42,0x68,0xa6,0xf3 = vmul.i32 q3, q3, d2[0] 0x63,0x88,0xa8,0xf3 = vmul.i32 q4, q4, d3[1] 0x44,0xa8,0xaa,0xf3 = vmul.i32 q5, q5, d4[0] 0x65,0xc9,0xac,0xf3 = vmul.f32 q6, q6, d5[1] 0x64,0x98,0x90,0xf2 = vmul.i16 d9, d0, d4[2] 0x6f,0x88,0x91,0xf2 = vmul.i16 d8, d1, d7[3] 0x49,0x78,0x92,0xf2 = vmul.i16 d7, d2, d1[1] 0x42,0x68,0xa3,0xf2 = vmul.i32 d6, d3, d2[0] 0x63,0x58,0xa4,0xf2 = vmul.i32 d5, d4, d3[1] 0x44,0x48,0xa5,0xf2 = vmul.i32 d4, d5, d4[0] 0x65,0x39,0xa6,0xf2 = vmul.f32 d3, d6, d5[1] 0x64,0x28,0xd0,0xf3 = vmul.i16 q9, q0, d4[2] 0x6f,0x08,0xd2,0xf3 = vmul.i16 q8, q1, d7[3] 0x49,0xe8,0x94,0xf3 = vmul.i16 q7, q2, d1[1] 0x42,0xc8,0xa6,0xf3 = vmul.i32 q6, q3, d2[0] 0x63,0xa8,0xa8,0xf3 = vmul.i32 q5, q4, d3[1] 0x44,0x88,0xaa,0xf3 = vmul.i32 q4, q5, d4[0] 0x65,0x69,0xac,0xf3 = vmul.f32 q3, q6, d5[1] capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-neg-encoding.s.cs000064400000000000000000000011050072674642500223310ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa0,0x03,0xf1,0xf3 = vneg.s8 d16, d16 0xa0,0x03,0xf5,0xf3 = vneg.s16 d16, d16 0xa0,0x03,0xf9,0xf3 = vneg.s32 d16, d16 0xa0,0x07,0xf9,0xf3 = vneg.f32 d16, d16 0xe0,0x03,0xf1,0xf3 = vneg.s8 q8, q8 0xe0,0x03,0xf5,0xf3 = vneg.s16 q8, q8 0xe0,0x03,0xf9,0xf3 = vneg.s32 q8, q8 0xe0,0x07,0xf9,0xf3 = vneg.f32 q8, q8 0xa0,0x07,0xf0,0xf3 = vqneg.s8 d16, d16 0xa0,0x07,0xf4,0xf3 = vqneg.s16 d16, d16 0xa0,0x07,0xf8,0xf3 = vqneg.s32 d16, d16 0xe0,0x07,0xf0,0xf3 = vqneg.s8 q8, q8 0xe0,0x07,0xf4,0xf3 = vqneg.s16 q8, q8 0xe0,0x07,0xf8,0xf3 = vqneg.s32 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-pairwise-encoding.s.cs000064400000000000000000000037370072674642500234200ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xb0,0x0b,0x41,0xf2 = vpadd.i8 d16, d17, d16 0xb0,0x0b,0x51,0xf2 = vpadd.i16 d16, d17, d16 0xb0,0x0b,0x61,0xf2 = vpadd.i32 d16, d17, d16 0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17 0xb0,0x1b,0x41,0xf2 = vpadd.i8 d17, d17, d16 0xb0,0x1b,0x51,0xf2 = vpadd.i16 d17, d17, d16 0xb0,0x1b,0x61,0xf2 = vpadd.i32 d17, d17, d16 0xa1,0x0d,0x40,0xf3 = vpadd.f32 d16, d16, d17 0x20,0x02,0xf0,0xf3 = vpaddl.s8 d16, d16 0x20,0x02,0xf4,0xf3 = vpaddl.s16 d16, d16 0x20,0x02,0xf8,0xf3 = vpaddl.s32 d16, d16 0xa0,0x02,0xf0,0xf3 = vpaddl.u8 d16, d16 0xa0,0x02,0xf4,0xf3 = vpaddl.u16 d16, d16 0xa0,0x02,0xf8,0xf3 = vpaddl.u32 d16, d16 0x60,0x02,0xf0,0xf3 = vpaddl.s8 q8, q8 0x60,0x02,0xf4,0xf3 = vpaddl.s16 q8, q8 0x60,0x02,0xf8,0xf3 = vpaddl.s32 q8, q8 0xe0,0x02,0xf0,0xf3 = vpaddl.u8 q8, q8 0xe0,0x02,0xf4,0xf3 = vpaddl.u16 q8, q8 0xe0,0x02,0xf8,0xf3 = vpaddl.u32 q8, q8 0x21,0x06,0xf0,0xf3 = vpadal.s8 d16, d17 0x21,0x06,0xf4,0xf3 = vpadal.s16 d16, d17 0x21,0x06,0xf8,0xf3 = vpadal.s32 d16, d17 0xa1,0x06,0xf0,0xf3 = vpadal.u8 d16, d17 0xa1,0x06,0xf4,0xf3 = vpadal.u16 d16, d17 0xa1,0x06,0xf8,0xf3 = vpadal.u32 d16, d17 0x60,0x26,0xf0,0xf3 = vpadal.s8 q9, q8 0x60,0x26,0xf4,0xf3 = vpadal.s16 q9, q8 0x60,0x26,0xf8,0xf3 = vpadal.s32 q9, q8 0xe0,0x26,0xf0,0xf3 = vpadal.u8 q9, q8 0xe0,0x26,0xf4,0xf3 = vpadal.u16 q9, q8 0xe0,0x26,0xf8,0xf3 = vpadal.u32 q9, q8 0xb1,0x0a,0x40,0xf2 = vpmin.s8 d16, d16, d17 0xb1,0x0a,0x50,0xf2 = vpmin.s16 d16, d16, d17 0xb1,0x0a,0x60,0xf2 = vpmin.s32 d16, d16, d17 0xb1,0x0a,0x40,0xf3 = vpmin.u8 d16, d16, d17 0xb1,0x0a,0x50,0xf3 = vpmin.u16 d16, d16, d17 0xb1,0x0a,0x60,0xf3 = vpmin.u32 d16, d16, d17 0xa1,0x0f,0x60,0xf3 = vpmin.f32 d16, d16, d17 0xa1,0x0a,0x40,0xf2 = vpmax.s8 d16, d16, d17 0xa1,0x0a,0x50,0xf2 = vpmax.s16 d16, d16, d17 0xa1,0x0a,0x60,0xf2 = vpmax.s32 d16, d16, d17 0xa1,0x0a,0x40,0xf3 = vpmax.u8 d16, d16, d17 0xa1,0x0a,0x50,0xf3 = vpmax.u16 d16, d16, d17 0xa1,0x0a,0x60,0xf3 = vpmax.u32 d16, d16, d17 0xa1,0x0f,0x40,0xf3 = vpmax.f32 d16, d16, d17 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-reciprocal-encoding.s.cs000064400000000000000000000010450072674642500237060ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x20,0x04,0xfb,0xf3 = vrecpe.u32 d16, d16 0x60,0x04,0xfb,0xf3 = vrecpe.u32 q8, q8 0x20,0x05,0xfb,0xf3 = vrecpe.f32 d16, d16 0x60,0x05,0xfb,0xf3 = vrecpe.f32 q8, q8 0xb1,0x0f,0x40,0xf2 = vrecps.f32 d16, d16, d17 0xf2,0x0f,0x40,0xf2 = vrecps.f32 q8, q8, q9 0xa0,0x04,0xfb,0xf3 = vrsqrte.u32 d16, d16 0xe0,0x04,0xfb,0xf3 = vrsqrte.u32 q8, q8 0xa0,0x05,0xfb,0xf3 = vrsqrte.f32 d16, d16 0xe0,0x05,0xfb,0xf3 = vrsqrte.f32 q8, q8 0xb1,0x0f,0x60,0xf2 = vrsqrts.f32 d16, d16, d17 0xf2,0x0f,0x60,0xf2 = vrsqrts.f32 q8, q8, q9 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-reverse-encoding.s.cs000064400000000000000000000007730072674642500232450ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x20,0x00,0xf0,0xf3 = vrev64.8 d16, d16 0x20,0x00,0xf4,0xf3 = vrev64.16 d16, d16 0x20,0x00,0xf8,0xf3 = vrev64.32 d16, d16 0x60,0x00,0xf0,0xf3 = vrev64.8 q8, q8 0x60,0x00,0xf4,0xf3 = vrev64.16 q8, q8 0x60,0x00,0xf8,0xf3 = vrev64.32 q8, q8 0xa0,0x00,0xf0,0xf3 = vrev32.8 d16, d16 0xa0,0x00,0xf4,0xf3 = vrev32.16 d16, d16 0xe0,0x00,0xf0,0xf3 = vrev32.8 q8, q8 0xe0,0x00,0xf4,0xf3 = vrev32.16 q8, q8 0x20,0x01,0xf0,0xf3 = vrev16.8 d16, d16 0x60,0x01,0xf0,0xf3 = vrev16.8 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-satshift-encoding.s.cs000064400000000000000000000064620072674642500234200ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xb0,0x04,0x41,0xf2 = vqshl.s8 d16, d16, d17 0xb0,0x04,0x51,0xf2 = vqshl.s16 d16, d16, d17 0xb0,0x04,0x61,0xf2 = vqshl.s32 d16, d16, d17 0xb0,0x04,0x71,0xf2 = vqshl.s64 d16, d16, d17 0xb0,0x04,0x41,0xf3 = vqshl.u8 d16, d16, d17 0xb0,0x04,0x51,0xf3 = vqshl.u16 d16, d16, d17 0xb0,0x04,0x61,0xf3 = vqshl.u32 d16, d16, d17 0xb0,0x04,0x71,0xf3 = vqshl.u64 d16, d16, d17 0xf0,0x04,0x42,0xf2 = vqshl.s8 q8, q8, q9 0xf0,0x04,0x52,0xf2 = vqshl.s16 q8, q8, q9 0xf0,0x04,0x62,0xf2 = vqshl.s32 q8, q8, q9 0xf0,0x04,0x72,0xf2 = vqshl.s64 q8, q8, q9 0xf0,0x04,0x42,0xf3 = vqshl.u8 q8, q8, q9 0xf0,0x04,0x52,0xf3 = vqshl.u16 q8, q8, q9 0xf0,0x04,0x62,0xf3 = vqshl.u32 q8, q8, q9 0xf0,0x04,0x72,0xf3 = vqshl.u64 q8, q8, q9 0x30,0x07,0xcf,0xf2 = vqshl.s8 d16, d16, #7 0x30,0x07,0xdf,0xf2 = vqshl.s16 d16, d16, #15 0x30,0x07,0xff,0xf2 = vqshl.s32 d16, d16, #31 0xb0,0x07,0xff,0xf2 = vqshl.s64 d16, d16, #63 0x30,0x07,0xcf,0xf3 = vqshl.u8 d16, d16, #7 0x30,0x07,0xdf,0xf3 = vqshl.u16 d16, d16, #15 0x30,0x07,0xff,0xf3 = vqshl.u32 d16, d16, #31 0xb0,0x07,0xff,0xf3 = vqshl.u64 d16, d16, #63 0x30,0x06,0xcf,0xf3 = vqshlu.s8 d16, d16, #7 0x30,0x06,0xdf,0xf3 = vqshlu.s16 d16, d16, #15 0x30,0x06,0xff,0xf3 = vqshlu.s32 d16, d16, #31 0xb0,0x06,0xff,0xf3 = vqshlu.s64 d16, d16, #63 0x70,0x07,0xcf,0xf2 = vqshl.s8 q8, q8, #7 0x70,0x07,0xdf,0xf2 = vqshl.s16 q8, q8, #15 0x70,0x07,0xff,0xf2 = vqshl.s32 q8, q8, #31 0xf0,0x07,0xff,0xf2 = vqshl.s64 q8, q8, #63 0x70,0x07,0xcf,0xf3 = vqshl.u8 q8, q8, #7 0x70,0x07,0xdf,0xf3 = vqshl.u16 q8, q8, #15 0x70,0x07,0xff,0xf3 = vqshl.u32 q8, q8, #31 0xf0,0x07,0xff,0xf3 = vqshl.u64 q8, q8, #63 0x70,0x06,0xcf,0xf3 = vqshlu.s8 q8, q8, #7 0x70,0x06,0xdf,0xf3 = vqshlu.s16 q8, q8, #15 0x70,0x06,0xff,0xf3 = vqshlu.s32 q8, q8, #31 0xf0,0x06,0xff,0xf3 = vqshlu.s64 q8, q8, #63 0xb0,0x05,0x41,0xf2 = vqrshl.s8 d16, d16, d17 0xb0,0x05,0x51,0xf2 = vqrshl.s16 d16, d16, d17 0xb0,0x05,0x61,0xf2 = vqrshl.s32 d16, d16, d17 0xb0,0x05,0x71,0xf2 = vqrshl.s64 d16, d16, d17 0xb0,0x05,0x41,0xf3 = vqrshl.u8 d16, d16, d17 0xb0,0x05,0x51,0xf3 = vqrshl.u16 d16, d16, d17 0xb0,0x05,0x61,0xf3 = vqrshl.u32 d16, d16, d17 0xb0,0x05,0x71,0xf3 = vqrshl.u64 d16, d16, d17 0xf0,0x05,0x42,0xf2 = vqrshl.s8 q8, q8, q9 0xf0,0x05,0x52,0xf2 = vqrshl.s16 q8, q8, q9 0xf0,0x05,0x62,0xf2 = vqrshl.s32 q8, q8, q9 0xf0,0x05,0x72,0xf2 = vqrshl.s64 q8, q8, q9 0xf0,0x05,0x42,0xf3 = vqrshl.u8 q8, q8, q9 0xf0,0x05,0x52,0xf3 = vqrshl.u16 q8, q8, q9 0xf0,0x05,0x62,0xf3 = vqrshl.u32 q8, q8, q9 0xf0,0x05,0x72,0xf3 = vqrshl.u64 q8, q8, q9 0x30,0x09,0xc8,0xf2 = vqshrn.s16 d16, q8, #8 0x30,0x09,0xd0,0xf2 = vqshrn.s32 d16, q8, #16 0x30,0x09,0xe0,0xf2 = vqshrn.s64 d16, q8, #32 0x30,0x09,0xc8,0xf3 = vqshrn.u16 d16, q8, #8 0x30,0x09,0xd0,0xf3 = vqshrn.u32 d16, q8, #16 0x30,0x09,0xe0,0xf3 = vqshrn.u64 d16, q8, #32 0x30,0x08,0xc8,0xf3 = vqshrun.s16 d16, q8, #8 0x30,0x08,0xd0,0xf3 = vqshrun.s32 d16, q8, #16 0x30,0x08,0xe0,0xf3 = vqshrun.s64 d16, q8, #32 0x70,0x09,0xc8,0xf2 = vqrshrn.s16 d16, q8, #8 0x70,0x09,0xd0,0xf2 = vqrshrn.s32 d16, q8, #16 0x70,0x09,0xe0,0xf2 = vqrshrn.s64 d16, q8, #32 0x70,0x09,0xc8,0xf3 = vqrshrn.u16 d16, q8, #8 0x70,0x09,0xd0,0xf3 = vqrshrn.u32 d16, q8, #16 0x70,0x09,0xe0,0xf3 = vqrshrn.u64 d16, q8, #32 0x70,0x08,0xc8,0xf3 = vqrshrun.s16 d16, q8, #8 0x70,0x08,0xd0,0xf3 = vqrshrun.s32 d16, q8, #16 0x70,0x08,0xe0,0xf3 = vqrshrun.s64 d16, q8, #32 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-shift-encoding.s.cs000064400000000000000000000241650072674642500227100ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa1,0x04,0x40,0xf3 = vshl.u8 d16, d17, d16 0xa1,0x04,0x50,0xf3 = vshl.u16 d16, d17, d16 0xa1,0x04,0x60,0xf3 = vshl.u32 d16, d17, d16 0xa1,0x04,0x70,0xf3 = vshl.u64 d16, d17, d16 0x30,0x05,0xcf,0xf2 = vshl.i8 d16, d16, #7 0x30,0x05,0xdf,0xf2 = vshl.i16 d16, d16, #15 0x30,0x05,0xff,0xf2 = vshl.i32 d16, d16, #31 0xb0,0x05,0xff,0xf2 = vshl.i64 d16, d16, #63 0xe2,0x04,0x40,0xf3 = vshl.u8 q8, q9, q8 0xe2,0x04,0x50,0xf3 = vshl.u16 q8, q9, q8 0xe2,0x04,0x60,0xf3 = vshl.u32 q8, q9, q8 0xe2,0x04,0x70,0xf3 = vshl.u64 q8, q9, q8 0x70,0x05,0xcf,0xf2 = vshl.i8 q8, q8, #7 0x70,0x05,0xdf,0xf2 = vshl.i16 q8, q8, #15 0x70,0x05,0xff,0xf2 = vshl.i32 q8, q8, #31 0xf0,0x05,0xff,0xf2 = vshl.i64 q8, q8, #63 0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7 0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #15 0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #31 0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #63 0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7 0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #15 0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #31 0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #63 0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7 0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #15 0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #31 0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #63 0x70,0x00,0xc9,0xf2 = vshr.s8 q8, q8, #7 0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #15 0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #31 0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #63 0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7 0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #15 0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #31 0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #63 0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7 0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #15 0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #31 0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #63 0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7 0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #15 0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #31 0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #63 0x70,0x00,0xc9,0xf2 = vshr.s8 q8, q8, #7 0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #15 0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #31 0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #63 0x16,0x01,0xc9,0xf2 = vsra.s8 d16, d6, #7 0x32,0xa1,0xd1,0xf2 = vsra.s16 d26, d18, #15 0x1a,0xb1,0xa1,0xf2 = vsra.s32 d11, d10, #31 0xb3,0xc1,0x81,0xf2 = vsra.s64 d12, d19, #63 0x70,0x21,0x89,0xf2 = vsra.s8 q1, q8, #7 0x5e,0x41,0x91,0xf2 = vsra.s16 q2, q7, #15 0x5c,0x61,0xa1,0xf2 = vsra.s32 q3, q6, #31 0xda,0x81,0x81,0xf2 = vsra.s64 q4, q5, #63 0x30,0x01,0xc9,0xf2 = vsra.s8 d16, d16, #7 0x1f,0xf1,0x91,0xf2 = vsra.s16 d15, d15, #15 0x1e,0xe1,0xa1,0xf2 = vsra.s32 d14, d14, #31 0x9d,0xd1,0x81,0xf2 = vsra.s64 d13, d13, #63 0x58,0x81,0x89,0xf2 = vsra.s8 q4, q4, #7 0x5a,0xa1,0x91,0xf2 = vsra.s16 q5, q5, #15 0x5c,0xc1,0xa1,0xf2 = vsra.s32 q6, q6, #31 0xde,0xe1,0x81,0xf2 = vsra.s64 q7, q7, #63 0x16,0x01,0xc9,0xf3 = vsra.u8 d16, d6, #7 0x32,0xa1,0xd1,0xf3 = vsra.u16 d26, d18, #15 0x1a,0xb1,0xa1,0xf3 = vsra.u32 d11, d10, #31 0xb3,0xc1,0x81,0xf3 = vsra.u64 d12, d19, #63 0x70,0x21,0x89,0xf3 = vsra.u8 q1, q8, #7 0x5e,0x41,0x91,0xf3 = vsra.u16 q2, q7, #15 0x5c,0x61,0xa1,0xf3 = vsra.u32 q3, q6, #31 0xda,0x81,0x81,0xf3 = vsra.u64 q4, q5, #63 0x30,0x01,0xc9,0xf3 = vsra.u8 d16, d16, #7 0x1f,0xf1,0x91,0xf3 = vsra.u16 d15, d15, #15 0x1e,0xe1,0xa1,0xf3 = vsra.u32 d14, d14, #31 0x9d,0xd1,0x81,0xf3 = vsra.u64 d13, d13, #63 0x58,0x81,0x89,0xf3 = vsra.u8 q4, q4, #7 0x5a,0xa1,0x91,0xf3 = vsra.u16 q5, q5, #15 0x5c,0xc1,0xa1,0xf3 = vsra.u32 q6, q6, #31 0xde,0xe1,0x81,0xf3 = vsra.u64 q7, q7, #63 0x16,0x04,0xc9,0xf3 = vsri.8 d16, d6, #7 0x32,0xa4,0xd1,0xf3 = vsri.16 d26, d18, #15 0x1a,0xb4,0xa1,0xf3 = vsri.32 d11, d10, #31 0xb3,0xc4,0x81,0xf3 = vsri.64 d12, d19, #63 0x70,0x24,0x89,0xf3 = vsri.8 q1, q8, #7 0x5e,0x44,0x91,0xf3 = vsri.16 q2, q7, #15 0x5c,0x64,0xa1,0xf3 = vsri.32 q3, q6, #31 0xda,0x84,0x81,0xf3 = vsri.64 q4, q5, #63 0x30,0x04,0xc9,0xf3 = vsri.8 d16, d16, #7 0x1f,0xf4,0x91,0xf3 = vsri.16 d15, d15, #15 0x1e,0xe4,0xa1,0xf3 = vsri.32 d14, d14, #31 0x9d,0xd4,0x81,0xf3 = vsri.64 d13, d13, #63 0x58,0x84,0x89,0xf3 = vsri.8 q4, q4, #7 0x5a,0xa4,0x91,0xf3 = vsri.16 q5, q5, #15 0x5c,0xc4,0xa1,0xf3 = vsri.32 q6, q6, #31 0xde,0xe4,0x81,0xf3 = vsri.64 q7, q7, #63 0x16,0x05,0xcf,0xf3 = vsli.8 d16, d6, #7 0x32,0xa5,0xdf,0xf3 = vsli.16 d26, d18, #15 0x1a,0xb5,0xbf,0xf3 = vsli.32 d11, d10, #31 0xb3,0xc5,0xbf,0xf3 = vsli.64 d12, d19, #63 0x70,0x25,0x8f,0xf3 = vsli.8 q1, q8, #7 0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #15 0x5c,0x65,0xbf,0xf3 = vsli.32 q3, q6, #31 0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #63 0x30,0x05,0xcf,0xf3 = vsli.8 d16, d16, #7 0x1f,0xf5,0x9f,0xf3 = vsli.16 d15, d15, #15 0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #31 0x9d,0xd5,0xbf,0xf3 = vsli.64 d13, d13, #63 0x58,0x85,0x8f,0xf3 = vsli.8 q4, q4, #7 0x5a,0xa5,0x9f,0xf3 = vsli.16 q5, q5, #15 0x5c,0xc5,0xbf,0xf3 = vsli.32 q6, q6, #31 0xde,0xe5,0xbf,0xf3 = vsli.64 q7, q7, #63 0x30,0x0a,0xcf,0xf2 = vshll.s8 q8, d16, #7 0x30,0x0a,0xdf,0xf2 = vshll.s16 q8, d16, #15 0x30,0x0a,0xff,0xf2 = vshll.s32 q8, d16, #31 0x30,0x0a,0xcf,0xf3 = vshll.u8 q8, d16, #7 0x30,0x0a,0xdf,0xf3 = vshll.u16 q8, d16, #15 0x30,0x0a,0xff,0xf3 = vshll.u32 q8, d16, #31 0x20,0x03,0xf2,0xf3 = vshll.i8 q8, d16, #8 0x20,0x03,0xf6,0xf3 = vshll.i16 q8, d16, #16 0x20,0x03,0xfa,0xf3 = vshll.i32 q8, d16, #32 0x30,0x08,0xc8,0xf2 = vshrn.i16 d16, q8, #8 0x30,0x08,0xd0,0xf2 = vshrn.i32 d16, q8, #16 0x30,0x08,0xe0,0xf2 = vshrn.i64 d16, q8, #32 0xa1,0x05,0x40,0xf2 = vrshl.s8 d16, d17, d16 0xa1,0x05,0x50,0xf2 = vrshl.s16 d16, d17, d16 0xa1,0x05,0x60,0xf2 = vrshl.s32 d16, d17, d16 0xa1,0x05,0x70,0xf2 = vrshl.s64 d16, d17, d16 0xa1,0x05,0x40,0xf3 = vrshl.u8 d16, d17, d16 0xa1,0x05,0x50,0xf3 = vrshl.u16 d16, d17, d16 0xa1,0x05,0x60,0xf3 = vrshl.u32 d16, d17, d16 0xa1,0x05,0x70,0xf3 = vrshl.u64 d16, d17, d16 0xe2,0x05,0x40,0xf2 = vrshl.s8 q8, q9, q8 0xe2,0x05,0x50,0xf2 = vrshl.s16 q8, q9, q8 0xe2,0x05,0x60,0xf2 = vrshl.s32 q8, q9, q8 0xe2,0x05,0x70,0xf2 = vrshl.s64 q8, q9, q8 0xe2,0x05,0x40,0xf3 = vrshl.u8 q8, q9, q8 0xe2,0x05,0x50,0xf3 = vrshl.u16 q8, q9, q8 0xe2,0x05,0x60,0xf3 = vrshl.u32 q8, q9, q8 0xe2,0x05,0x70,0xf3 = vrshl.u64 q8, q9, q8 0x30,0x02,0xc8,0xf2 = vrshr.s8 d16, d16, #8 0x30,0x02,0xd0,0xf2 = vrshr.s16 d16, d16, #16 0x30,0x02,0xe0,0xf2 = vrshr.s32 d16, d16, #32 0xb0,0x02,0xc0,0xf2 = vrshr.s64 d16, d16, #64 0x30,0x02,0xc8,0xf3 = vrshr.u8 d16, d16, #8 0x30,0x02,0xd0,0xf3 = vrshr.u16 d16, d16, #16 0x30,0x02,0xe0,0xf3 = vrshr.u32 d16, d16, #32 0xb0,0x02,0xc0,0xf3 = vrshr.u64 d16, d16, #64 0x70,0x02,0xc8,0xf2 = vrshr.s8 q8, q8, #8 0x70,0x02,0xd0,0xf2 = vrshr.s16 q8, q8, #16 0x70,0x02,0xe0,0xf2 = vrshr.s32 q8, q8, #32 0xf0,0x02,0xc0,0xf2 = vrshr.s64 q8, q8, #64 0x70,0x02,0xc8,0xf3 = vrshr.u8 q8, q8, #8 0x70,0x02,0xd0,0xf3 = vrshr.u16 q8, q8, #16 0x70,0x02,0xe0,0xf3 = vrshr.u32 q8, q8, #32 0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #64 0x70,0x08,0xc8,0xf2 = vrshrn.i16 d16, q8, #8 0x70,0x08,0xd0,0xf2 = vrshrn.i32 d16, q8, #16 0x70,0x08,0xe0,0xf2 = vrshrn.i64 d16, q8, #32 0x70,0x09,0xcc,0xf2 = vqrshrn.s16 d16, q8, #4 0x70,0x09,0xd3,0xf2 = vqrshrn.s32 d16, q8, #13 0x70,0x09,0xf3,0xf2 = vqrshrn.s64 d16, q8, #13 0x70,0x09,0xcc,0xf3 = vqrshrn.u16 d16, q8, #4 0x70,0x09,0xd3,0xf3 = vqrshrn.u32 d16, q8, #13 0x70,0x09,0xf3,0xf3 = vqrshrn.u64 d16, q8, #13 0x48,0x84,0x0a,0xf2 = vshl.s8 q4, q4, q5 0x48,0x84,0x1a,0xf2 = vshl.s16 q4, q4, q5 0x48,0x84,0x2a,0xf2 = vshl.s32 q4, q4, q5 0x48,0x84,0x3a,0xf2 = vshl.s64 q4, q4, q5 0x48,0x84,0x0a,0xf3 = vshl.u8 q4, q4, q5 0x48,0x84,0x1a,0xf3 = vshl.u16 q4, q4, q5 0x48,0x84,0x2a,0xf3 = vshl.u32 q4, q4, q5 0x48,0x84,0x3a,0xf3 = vshl.u64 q4, q4, q5 0x04,0x44,0x05,0xf2 = vshl.s8 d4, d4, d5 0x04,0x44,0x15,0xf2 = vshl.s16 d4, d4, d5 0x04,0x44,0x25,0xf2 = vshl.s32 d4, d4, d5 0x04,0x44,0x35,0xf2 = vshl.s64 d4, d4, d5 0x04,0x44,0x05,0xf3 = vshl.u8 d4, d4, d5 0x04,0x44,0x15,0xf3 = vshl.u16 d4, d4, d5 0x04,0x44,0x25,0xf3 = vshl.u32 d4, d4, d5 0x04,0x44,0x35,0xf3 = vshl.u64 d4, d4, d5 0x58,0x85,0x8a,0xf2 = vshl.i8 q4, q4, #2 0x58,0x85,0x9e,0xf2 = vshl.i16 q4, q4, #14 0x58,0x85,0xbb,0xf2 = vshl.i32 q4, q4, #27 0xd8,0x85,0xa3,0xf2 = vshl.i64 q4, q4, #35 0x14,0x45,0x8e,0xf2 = vshl.i8 d4, d4, #6 0x14,0x45,0x9a,0xf2 = vshl.i16 d4, d4, #10 0x14,0x45,0xb1,0xf2 = vshl.i32 d4, d4, #17 0x94,0x45,0xab,0xf2 = vshl.i64 d4, d4, #43 0x0b,0xb5,0x04,0xf2 = vrshl.s8 d11, d11, d4 0x0c,0xc5,0x15,0xf2 = vrshl.s16 d12, d12, d5 0x0d,0xd5,0x26,0xf2 = vrshl.s32 d13, d13, d6 0x0e,0xe5,0x37,0xf2 = vrshl.s64 d14, d14, d7 0x0f,0xf5,0x08,0xf3 = vrshl.u8 d15, d15, d8 0x20,0x05,0x59,0xf3 = vrshl.u16 d16, d16, d9 0x21,0x15,0x6a,0xf3 = vrshl.u32 d17, d17, d10 0x22,0x25,0x7b,0xf3 = vrshl.u64 d18, d18, d11 0xc2,0x25,0x00,0xf2 = vrshl.s8 q1, q1, q8 0xc4,0x45,0x1e,0xf2 = vrshl.s16 q2, q2, q15 0xc6,0x65,0x2c,0xf2 = vrshl.s32 q3, q3, q14 0xc8,0x85,0x3a,0xf2 = vrshl.s64 q4, q4, q13 0xca,0xa5,0x08,0xf3 = vrshl.u8 q5, q5, q12 0xcc,0xc5,0x16,0xf3 = vrshl.u16 q6, q6, q11 0xce,0xe5,0x24,0xf3 = vrshl.u32 q7, q7, q10 0xe0,0x05,0x72,0xf3 = vrshl.u64 q8, q8, q9 0x1f,0xf0,0x88,0xf2 = vshr.s8 d15, d15, #8 0x1c,0xc0,0x90,0xf2 = vshr.s16 d12, d12, #16 0x1d,0xd0,0xa0,0xf2 = vshr.s32 d13, d13, #32 0x9e,0xe0,0x80,0xf2 = vshr.s64 d14, d14, #64 0x30,0x00,0xc8,0xf3 = vshr.u8 d16, d16, #8 0x31,0x10,0xd0,0xf3 = vshr.u16 d17, d17, #16 0x16,0x60,0xa0,0xf3 = vshr.u32 d6, d6, #32 0x9a,0xa0,0x80,0xf3 = vshr.u64 d10, d10, #64 0x52,0x20,0x88,0xf2 = vshr.s8 q1, q1, #8 0x54,0x40,0x90,0xf2 = vshr.s16 q2, q2, #16 0x56,0x60,0xa0,0xf2 = vshr.s32 q3, q3, #32 0xd8,0x80,0x80,0xf2 = vshr.s64 q4, q4, #64 0x5a,0xa0,0x88,0xf3 = vshr.u8 q5, q5, #8 0x5c,0xc0,0x90,0xf3 = vshr.u16 q6, q6, #16 0x5e,0xe0,0xa0,0xf3 = vshr.u32 q7, q7, #32 0xf0,0x00,0xc0,0xf3 = vshr.u64 q8, q8, #64 0x1f,0xf2,0x88,0xf2 = vrshr.s8 d15, d15, #8 0x1c,0xc2,0x90,0xf2 = vrshr.s16 d12, d12, #16 0x1d,0xd2,0xa0,0xf2 = vrshr.s32 d13, d13, #32 0x9e,0xe2,0x80,0xf2 = vrshr.s64 d14, d14, #64 0x30,0x02,0xc8,0xf3 = vrshr.u8 d16, d16, #8 0x31,0x12,0xd0,0xf3 = vrshr.u16 d17, d17, #16 0x16,0x62,0xa0,0xf3 = vrshr.u32 d6, d6, #32 0x9a,0xa2,0x80,0xf3 = vrshr.u64 d10, d10, #64 0x52,0x22,0x88,0xf2 = vrshr.s8 q1, q1, #8 0x54,0x42,0x90,0xf2 = vrshr.s16 q2, q2, #16 0x56,0x62,0xa0,0xf2 = vrshr.s32 q3, q3, #32 0xd8,0x82,0x80,0xf2 = vrshr.s64 q4, q4, #64 0x5a,0xa2,0x88,0xf3 = vrshr.u8 q5, q5, #8 0x5c,0xc2,0x90,0xf3 = vrshr.u16 q6, q6, #16 0x5e,0xe2,0xa0,0xf3 = vrshr.u32 q7, q7, #32 0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #64 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-shiftaccum-encoding.s.cs000064400000000000000000000101540072674642500237120ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x30,0x11,0xc8,0xf2 = vsra.s8 d17, d16, #8 0x1e,0xf1,0x90,0xf2 = vsra.s16 d15, d14, #16 0x1c,0xd1,0xa0,0xf2 = vsra.s32 d13, d12, #32 0x9a,0xb1,0x80,0xf2 = vsra.s64 d11, d10, #64 0x54,0xe1,0x88,0xf2 = vsra.s8 q7, q2, #8 0x5c,0x61,0x90,0xf2 = vsra.s16 q3, q6, #16 0x5a,0x21,0xe0,0xf2 = vsra.s32 q9, q5, #32 0xd8,0x01,0xc0,0xf2 = vsra.s64 q8, q4, #64 0x30,0x11,0xc8,0xf3 = vsra.u8 d17, d16, #8 0x1e,0xb1,0x95,0xf3 = vsra.u16 d11, d14, #11 0x1f,0xc1,0xaa,0xf3 = vsra.u32 d12, d15, #22 0xb0,0xd1,0x8a,0xf3 = vsra.u64 d13, d16, #54 0x5e,0x21,0x88,0xf3 = vsra.u8 q1, q7, #8 0x5e,0x41,0x9a,0xf3 = vsra.u16 q2, q7, #6 0x5c,0x61,0xab,0xf3 = vsra.u32 q3, q6, #21 0xda,0x81,0xa7,0xf3 = vsra.u64 q4, q5, #25 0x30,0x01,0xc8,0xf2 = vsra.s8 d16, d16, #8 0x1e,0xe1,0x90,0xf2 = vsra.s16 d14, d14, #16 0x1c,0xc1,0xa0,0xf2 = vsra.s32 d12, d12, #32 0x9a,0xa1,0x80,0xf2 = vsra.s64 d10, d10, #64 0x54,0x41,0x88,0xf2 = vsra.s8 q2, q2, #8 0x5c,0xc1,0x90,0xf2 = vsra.s16 q6, q6, #16 0x5a,0xa1,0xa0,0xf2 = vsra.s32 q5, q5, #32 0xd8,0x81,0x80,0xf2 = vsra.s64 q4, q4, #64 0x30,0x01,0xc8,0xf3 = vsra.u8 d16, d16, #8 0x1e,0xe1,0x95,0xf3 = vsra.u16 d14, d14, #11 0x1f,0xf1,0xaa,0xf3 = vsra.u32 d15, d15, #22 0xb0,0x01,0xca,0xf3 = vsra.u64 d16, d16, #54 0x5e,0xe1,0x88,0xf3 = vsra.u8 q7, q7, #8 0x5e,0xe1,0x9a,0xf3 = vsra.u16 q7, q7, #6 0x5c,0xc1,0xab,0xf3 = vsra.u32 q6, q6, #21 0xda,0xa1,0xa7,0xf3 = vsra.u64 q5, q5, #25 0x3a,0x53,0x88,0xf2 = vrsra.s8 d5, d26, #8 0x39,0x63,0x90,0xf2 = vrsra.s16 d6, d25, #16 0x38,0x73,0xa0,0xf2 = vrsra.s32 d7, d24, #32 0xb7,0xe3,0x80,0xf2 = vrsra.s64 d14, d23, #64 0x36,0xf3,0x88,0xf3 = vrsra.u8 d15, d22, #8 0x35,0x03,0xd0,0xf3 = vrsra.u16 d16, d21, #16 0x34,0x13,0xe0,0xf3 = vrsra.u32 d17, d20, #32 0xb3,0x23,0xc0,0xf3 = vrsra.u64 d18, d19, #64 0x54,0x23,0x88,0xf2 = vrsra.s8 q1, q2, #8 0x56,0x43,0x90,0xf2 = vrsra.s16 q2, q3, #16 0x58,0x63,0xa0,0xf2 = vrsra.s32 q3, q4, #32 0xda,0x83,0x80,0xf2 = vrsra.s64 q4, q5, #64 0x5c,0xa3,0x88,0xf3 = vrsra.u8 q5, q6, #8 0x5e,0xc3,0x90,0xf3 = vrsra.u16 q6, q7, #16 0x70,0xe3,0xa0,0xf3 = vrsra.u32 q7, q8, #32 0xf2,0x03,0xc0,0xf3 = vrsra.u64 q8, q9, #64 0x3a,0xa3,0xc8,0xf2 = vrsra.s8 d26, d26, #8 0x39,0x93,0xd0,0xf2 = vrsra.s16 d25, d25, #16 0x38,0x83,0xe0,0xf2 = vrsra.s32 d24, d24, #32 0xb7,0x73,0xc0,0xf2 = vrsra.s64 d23, d23, #64 0x36,0x63,0xc8,0xf3 = vrsra.u8 d22, d22, #8 0x35,0x53,0xd0,0xf3 = vrsra.u16 d21, d21, #16 0x34,0x43,0xe0,0xf3 = vrsra.u32 d20, d20, #32 0xb3,0x33,0xc0,0xf3 = vrsra.u64 d19, d19, #64 0x54,0x43,0x88,0xf2 = vrsra.s8 q2, q2, #8 0x56,0x63,0x90,0xf2 = vrsra.s16 q3, q3, #16 0x58,0x83,0xa0,0xf2 = vrsra.s32 q4, q4, #32 0xda,0xa3,0x80,0xf2 = vrsra.s64 q5, q5, #64 0x5c,0xc3,0x88,0xf3 = vrsra.u8 q6, q6, #8 0x5e,0xe3,0x90,0xf3 = vrsra.u16 q7, q7, #16 0x70,0x03,0xe0,0xf3 = vrsra.u32 q8, q8, #32 0xf2,0x23,0xc0,0xf3 = vrsra.u64 q9, q9, #64 0x1c,0xb5,0x8f,0xf3 = vsli.8 d11, d12, #7 0x1d,0xc5,0x9f,0xf3 = vsli.16 d12, d13, #15 0x1e,0xd5,0xbf,0xf3 = vsli.32 d13, d14, #31 0x9f,0xe5,0xbf,0xf3 = vsli.64 d14, d15, #63 0x70,0x25,0x8f,0xf3 = vsli.8 q1, q8, #7 0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #15 0x58,0x65,0xbf,0xf3 = vsli.32 q3, q4, #31 0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #63 0x1b,0xc4,0xc8,0xf3 = vsri.8 d28, d11, #8 0x1c,0xa4,0xd0,0xf3 = vsri.16 d26, d12, #16 0x1d,0x84,0xe0,0xf3 = vsri.32 d24, d13, #32 0x9e,0x54,0xc0,0xf3 = vsri.64 d21, d14, #64 0x70,0x24,0x88,0xf3 = vsri.8 q1, q8, #8 0x54,0xa4,0x90,0xf3 = vsri.16 q5, q2, #16 0x58,0xe4,0xa0,0xf3 = vsri.32 q7, q4, #32 0xdc,0x24,0xc0,0xf3 = vsri.64 q9, q6, #64 0x1c,0xc5,0x8f,0xf3 = vsli.8 d12, d12, #7 0x1d,0xd5,0x9f,0xf3 = vsli.16 d13, d13, #15 0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #31 0x9f,0xf5,0xbf,0xf3 = vsli.64 d15, d15, #63 0x70,0x05,0xcf,0xf3 = vsli.8 q8, q8, #7 0x5e,0xe5,0x9f,0xf3 = vsli.16 q7, q7, #15 0x58,0x85,0xbf,0xf3 = vsli.32 q4, q4, #31 0xda,0xa5,0xbf,0xf3 = vsli.64 q5, q5, #63 0x1b,0xb4,0x88,0xf3 = vsri.8 d11, d11, #8 0x1c,0xc4,0x90,0xf3 = vsri.16 d12, d12, #16 0x1d,0xd4,0xa0,0xf3 = vsri.32 d13, d13, #32 0x9e,0xe4,0x80,0xf3 = vsri.64 d14, d14, #64 0x70,0x04,0xc8,0xf3 = vsri.8 q8, q8, #8 0x54,0x44,0x90,0xf3 = vsri.16 q2, q2, #16 0x58,0x84,0xa0,0xf3 = vsri.32 q4, q4, #32 0xdc,0xc4,0x80,0xf3 = vsri.64 q6, q6, #64 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-shuffle-encoding.s.cs000064400000000000000000000044060072674642500232230ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa0,0x03,0xf1,0xf2 = vext.8 d16, d17, d16, #3 0xa0,0x05,0xf1,0xf2 = vext.8 d16, d17, d16, #5 0xe0,0x03,0xf2,0xf2 = vext.8 q8, q9, q8, #3 0xe0,0x07,0xf2,0xf2 = vext.8 q8, q9, q8, #7 0xa0,0x06,0xf1,0xf2 = vext.16 d16, d17, d16, #3 0xe0,0x0c,0xf2,0xf2 = vext.32 q8, q9, q8, #3 0xe0,0x08,0xf2,0xf2 = vext.64 q8, q9, q8, #1 0xa0,0x13,0xf1,0xf2 = vext.8 d17, d17, d16, #3 0x0b,0x75,0xb7,0xf2 = vext.8 d7, d7, d11, #5 0x60,0x63,0xb6,0xf2 = vext.8 q3, q3, q8, #3 0xc8,0x27,0xf2,0xf2 = vext.8 q9, q9, q4, #7 0x2a,0x16,0xb1,0xf2 = vext.16 d1, d1, d26, #3 0x60,0xac,0xba,0xf2 = vext.32 q5, q5, q8, #3 0x60,0xa8,0xba,0xf2 = vext.64 q5, q5, q8, #1 0xa0,0x10,0xf2,0xf3 = vtrn.8 d17, d16 0xa0,0x10,0xf6,0xf3 = vtrn.16 d17, d16 0xa0,0x10,0xfa,0xf3 = vtrn.32 d17, d16 0xe0,0x20,0xf2,0xf3 = vtrn.8 q9, q8 0xe0,0x20,0xf6,0xf3 = vtrn.16 q9, q8 0xe0,0x20,0xfa,0xf3 = vtrn.32 q9, q8 0x20,0x11,0xf2,0xf3 = vuzp.8 d17, d16 0x20,0x11,0xf6,0xf3 = vuzp.16 d17, d16 0x60,0x21,0xf2,0xf3 = vuzp.8 q9, q8 0x60,0x21,0xf6,0xf3 = vuzp.16 q9, q8 0x60,0x21,0xfa,0xf3 = vuzp.32 q9, q8 0xa0,0x11,0xf2,0xf3 = vzip.8 d17, d16 0xa0,0x11,0xf6,0xf3 = vzip.16 d17, d16 0xe0,0x21,0xf2,0xf3 = vzip.8 q9, q8 0xe0,0x21,0xf6,0xf3 = vzip.16 q9, q8 0xe0,0x21,0xfa,0xf3 = vzip.32 q9, q8 0x83,0x20,0xba,0xf3 = vtrn.32 d2, d3 0x83,0x20,0xba,0xf3 = vtrn.32 d2, d3 0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 0x89,0x30,0xb2,0xf3 = vtrn.8 d3, d9 0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 0x89,0x30,0xb6,0xf3 = vtrn.16 d3, d9 0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 0x89,0x30,0xba,0xf3 = vtrn.32 d3, d9 0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 0xcc,0xc0,0xf2,0xf3 = vtrn.8 q14, q6 0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 0xcc,0xc0,0xf6,0xf3 = vtrn.16 q14, q6 0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 0xcc,0xc0,0xfa,0xf3 = vtrn.32 q14, q6 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-sub-encoding.s.cs000064400000000000000000000070220072674642500223550ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa0,0x08,0x41,0xf3 = vsub.i8 d16, d17, d16 0xa0,0x08,0x51,0xf3 = vsub.i16 d16, d17, d16 0xa0,0x08,0x61,0xf3 = vsub.i32 d16, d17, d16 0xa0,0x08,0x71,0xf3 = vsub.i64 d16, d17, d16 0xa1,0x0d,0x60,0xf2 = vsub.f32 d16, d16, d17 0xe2,0x08,0x40,0xf3 = vsub.i8 q8, q8, q9 0xe2,0x08,0x50,0xf3 = vsub.i16 q8, q8, q9 0xe2,0x08,0x60,0xf3 = vsub.i32 q8, q8, q9 0xe2,0x08,0x70,0xf3 = vsub.i64 q8, q8, q9 0xe2,0x0d,0x60,0xf2 = vsub.f32 q8, q8, q9 0x25,0xd8,0x0d,0xf3 = vsub.i8 d13, d13, d21 0x26,0xe8,0x1e,0xf3 = vsub.i16 d14, d14, d22 0x27,0xf8,0x2f,0xf3 = vsub.i32 d15, d15, d23 0xa8,0x08,0x70,0xf3 = vsub.i64 d16, d16, d24 0xa9,0x1d,0x61,0xf2 = vsub.f32 d17, d17, d25 0x64,0x28,0x02,0xf3 = vsub.i8 q1, q1, q10 0x62,0x48,0x14,0xf3 = vsub.i16 q2, q2, q9 0x60,0x68,0x26,0xf3 = vsub.i32 q3, q3, q8 0x4e,0x88,0x38,0xf3 = vsub.i64 q4, q4, q7 0x4c,0xad,0x2a,0xf2 = vsub.f32 q5, q5, q6 0xa0,0x02,0xc1,0xf2 = vsubl.s8 q8, d17, d16 0xa0,0x02,0xd1,0xf2 = vsubl.s16 q8, d17, d16 0xa0,0x02,0xe1,0xf2 = vsubl.s32 q8, d17, d16 0xa0,0x02,0xc1,0xf3 = vsubl.u8 q8, d17, d16 0xa0,0x02,0xd1,0xf3 = vsubl.u16 q8, d17, d16 0xa0,0x02,0xe1,0xf3 = vsubl.u32 q8, d17, d16 0xa2,0x03,0xc0,0xf2 = vsubw.s8 q8, q8, d18 0xa2,0x03,0xd0,0xf2 = vsubw.s16 q8, q8, d18 0xa2,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d18 0xa2,0x03,0xc0,0xf3 = vsubw.u8 q8, q8, d18 0xa2,0x03,0xd0,0xf3 = vsubw.u16 q8, q8, d18 0xa2,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d18 0xa1,0x02,0x40,0xf2 = vhsub.s8 d16, d16, d17 0xa1,0x02,0x50,0xf2 = vhsub.s16 d16, d16, d17 0xa1,0x02,0x60,0xf2 = vhsub.s32 d16, d16, d17 0xa1,0x02,0x40,0xf3 = vhsub.u8 d16, d16, d17 0xa1,0x02,0x50,0xf3 = vhsub.u16 d16, d16, d17 0xa1,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d17 0xe2,0x02,0x40,0xf2 = vhsub.s8 q8, q8, q9 0xe2,0x02,0x50,0xf2 = vhsub.s16 q8, q8, q9 0xe2,0x02,0x60,0xf2 = vhsub.s32 q8, q8, q9 0xb1,0x02,0x40,0xf2 = vqsub.s8 d16, d16, d17 0xb1,0x02,0x50,0xf2 = vqsub.s16 d16, d16, d17 0xb1,0x02,0x60,0xf2 = vqsub.s32 d16, d16, d17 0xb1,0x02,0x70,0xf2 = vqsub.s64 d16, d16, d17 0xb1,0x02,0x40,0xf3 = vqsub.u8 d16, d16, d17 0xb1,0x02,0x50,0xf3 = vqsub.u16 d16, d16, d17 0xb1,0x02,0x60,0xf3 = vqsub.u32 d16, d16, d17 0xb1,0x02,0x70,0xf3 = vqsub.u64 d16, d16, d17 0xf2,0x02,0x40,0xf2 = vqsub.s8 q8, q8, q9 0xf2,0x02,0x50,0xf2 = vqsub.s16 q8, q8, q9 0xf2,0x02,0x60,0xf2 = vqsub.s32 q8, q8, q9 0xf2,0x02,0x70,0xf2 = vqsub.s64 q8, q8, q9 0xf2,0x02,0x40,0xf3 = vqsub.u8 q8, q8, q9 0xf2,0x02,0x50,0xf3 = vqsub.u16 q8, q8, q9 0xf2,0x02,0x60,0xf3 = vqsub.u32 q8, q8, q9 0xf2,0x02,0x70,0xf3 = vqsub.u64 q8, q8, q9 0xa2,0x06,0xc0,0xf2 = vsubhn.i16 d16, q8, q9 0xa2,0x06,0xd0,0xf2 = vsubhn.i32 d16, q8, q9 0xa2,0x06,0xe0,0xf2 = vsubhn.i64 d16, q8, q9 0xa2,0x06,0xc0,0xf3 = vrsubhn.i16 d16, q8, q9 0xa2,0x06,0xd0,0xf3 = vrsubhn.i32 d16, q8, q9 0xa2,0x06,0xe0,0xf3 = vrsubhn.i64 d16, q8, q9 0x28,0xb2,0x0b,0xf2 = vhsub.s8 d11, d11, d24 0x27,0xc2,0x1c,0xf2 = vhsub.s16 d12, d12, d23 0x26,0xd2,0x2d,0xf2 = vhsub.s32 d13, d13, d22 0x25,0xe2,0x0e,0xf3 = vhsub.u8 d14, d14, d21 0x24,0xf2,0x1f,0xf3 = vhsub.u16 d15, d15, d20 0xa3,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d19 0x68,0x22,0x02,0xf2 = vhsub.s8 q1, q1, q12 0x66,0x42,0x14,0xf2 = vhsub.s16 q2, q2, q11 0x64,0x62,0x26,0xf2 = vhsub.s32 q3, q3, q10 0x62,0x82,0x08,0xf3 = vhsub.u8 q4, q4, q9 0x60,0xa2,0x1a,0xf3 = vhsub.u16 q5, q5, q8 0x4e,0xc2,0x2c,0xf3 = vhsub.u32 q6, q6, q7 0x05,0xc3,0x8c,0xf2 = vsubw.s8 q6, q6, d5 0x01,0xe3,0x9e,0xf2 = vsubw.s16 q7, q7, d1 0x82,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d2 0x05,0xc3,0x8c,0xf3 = vsubw.u8 q6, q6, d5 0x01,0xe3,0x9e,0xf3 = vsubw.u16 q7, q7, d1 0x82,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d2 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-table-encoding.s.cs000064400000000000000000000007050072674642500226540ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16 0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18 0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20 0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20 0xe1,0x28,0xf0,0xf3 = vtbx.8 d18, {d16}, d17 0xe2,0x39,0xf0,0xf3 = vtbx.8 d19, {d16, d17}, d18 0xe5,0x4a,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18}, d21 0xe5,0x4b,0xf0,0xf3 = vtbx.8 d20, {d16, d17, d18, d19}, d21 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-v8.s.cs000064400000000000000000000031100072674642500203270ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None 0x11,0x4f,0x05,0xf3 = vmaxnm.f32 d4, d5, d1 0x5c,0x4f,0x08,0xf3 = vmaxnm.f32 q2, q4, q6 0x3e,0x5f,0x24,0xf3 = vminnm.f32 d5, d4, d30 0xd4,0x0f,0x2a,0xf3 = vminnm.f32 q0, q13, q2 0x06,0x40,0xbb,0xf3 = vcvta.s32.f32 d4, d6 0x8a,0xc0,0xbb,0xf3 = vcvta.u32.f32 d12, d10 0x4c,0x80,0xbb,0xf3 = vcvta.s32.f32 q4, q6 0xe4,0x80,0xbb,0xf3 = vcvta.u32.f32 q4, q10 0x2e,0x13,0xbb,0xf3 = vcvtm.s32.f32 d1, d30 0x8a,0xc3,0xbb,0xf3 = vcvtm.u32.f32 d12, d10 0x64,0x23,0xbb,0xf3 = vcvtm.s32.f32 q1, q10 0xc2,0xa3,0xfb,0xf3 = vcvtm.u32.f32 q13, q1 0x21,0xf1,0xbb,0xf3 = vcvtn.s32.f32 d15, d17 0x83,0x51,0xbb,0xf3 = vcvtn.u32.f32 d5, d3 0x60,0x61,0xbb,0xf3 = vcvtn.s32.f32 q3, q8 0xc6,0xa1,0xbb,0xf3 = vcvtn.u32.f32 q5, q3 0x25,0xb2,0xbb,0xf3 = vcvtp.s32.f32 d11, d21 0xa7,0xe2,0xbb,0xf3 = vcvtp.u32.f32 d14, d23 0x6e,0x82,0xbb,0xf3 = vcvtp.s32.f32 q4, q15 0xe0,0x22,0xfb,0xf3 = vcvtp.u32.f32 q9, q8 0x00,0x34,0xba,0xf3 = vrintn.f32 d3, d0 0x48,0x24,0xba,0xf3 = vrintn.f32 q1, q4 0x8c,0x54,0xba,0xf3 = vrintx.f32 d5, d12 0xc6,0x04,0xba,0xf3 = vrintx.f32 q0, q3 0x00,0x35,0xba,0xf3 = vrinta.f32 d3, d0 0x44,0x05,0xfa,0xf3 = vrinta.f32 q8, q2 0xa2,0xc5,0xba,0xf3 = vrintz.f32 d12, d18 0xc8,0x25,0xfa,0xf3 = vrintz.f32 q9, q4 0x80,0x36,0xba,0xf3 = vrintm.f32 d3, d0 0xc8,0x26,0xba,0xf3 = vrintm.f32 q1, q4 0x80,0x37,0xba,0xf3 = vrintp.f32 d3, d0 0xc8,0x27,0xba,0xf3 = vrintp.f32 q1, q4 0x00,0x34,0xba,0xf3 = vrintn.f32 d3, d0 0xc6,0x04,0xba,0xf3 = vrintx.f32 q0, q3 0x00,0x35,0xba,0xf3 = vrinta.f32 d3, d0 0xc8,0x25,0xfa,0xf3 = vrintz.f32 q9, q4 0xc8,0x27,0xba,0xf3 = vrintp.f32 q1, q4 capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-vld-encoding.s.cs000064400000000000000000000272240072674642500223570ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x1f,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64] 0x4f,0x07,0x60,0xf4 = vld1.16 {d16}, [r0] 0x8f,0x07,0x60,0xf4 = vld1.32 {d16}, [r0] 0xcf,0x07,0x60,0xf4 = vld1.64 {d16}, [r0] 0x1f,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64] 0x6f,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128] 0x8f,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0] 0xcf,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0] 0x0f,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3] 0x5f,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64] 0x8f,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3] 0xdf,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64] 0x0f,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3] 0x5f,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64] 0x8f,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3] 0xdf,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64] 0x1d,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64]! 0x4d,0x07,0x60,0xf4 = vld1.16 {d16}, [r0]! 0x8d,0x07,0x60,0xf4 = vld1.32 {d16}, [r0]! 0xcd,0x07,0x60,0xf4 = vld1.64 {d16}, [r0]! 0x1d,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64]! 0x6d,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128]! 0x8d,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0]! 0xcd,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0]! 0x15,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64], r5 0x45,0x07,0x60,0xf4 = vld1.16 {d16}, [r0], r5 0x85,0x07,0x60,0xf4 = vld1.32 {d16}, [r0], r5 0xc5,0x07,0x60,0xf4 = vld1.64 {d16}, [r0], r5 0x15,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64], r5 0x65,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128], r5 0x85,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0], r5 0xc5,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0], r5 0x0d,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3]! 0x5d,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]! 0x8d,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]! 0xdd,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64]! 0x06,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3], r6 0x56,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64], r6 0x86,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3], r6 0xd6,0x66,0x23,0xf4 = vld1.64 {d6, d7, d8}, [r3:64], r6 0x0d,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3]! 0x5d,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]! 0x8d,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]! 0xdd,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64]! 0x08,0x12,0x23,0xf4 = vld1.8 {d1, d2, d3, d4}, [r3], r8 0x58,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64], r8 0x88,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3], r8 0xd8,0x62,0x23,0xf4 = vld1.64 {d6, d7, d8, d9}, [r3:64], r8 0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64] 0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128] 0x8f,0x08,0x60,0xf4 = vld2.32 {d16, d17}, [r0] 0x1f,0x03,0x60,0xf4 = vld2.8 {d16, d17, d18, d19}, [r0:64] 0x6f,0x03,0x60,0xf4 = vld2.16 {d16, d17, d18, d19}, [r0:128] 0xbf,0x03,0x60,0xf4 = vld2.32 {d16, d17, d18, d19}, [r0:256] 0x1d,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64]! 0x6d,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]! 0x8d,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0]! 0x1d,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64]! 0x6d,0x13,0x20,0xf4 = vld2.16 {d1, d2, d3, d4}, [r0:128]! 0xbd,0xe3,0x20,0xf4 = vld2.32 {d14, d15, d16, d17}, [r0:256]! 0x16,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64], r6 0x66,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128], r6 0x86,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0], r6 0x16,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64], r6 0x66,0x13,0x20,0xf4 = vld2.16 {d1, d2, d3, d4}, [r0:128], r6 0xb6,0xe3,0x20,0xf4 = vld2.32 {d14, d15, d16, d17}, [r0:256], r6 0x0f,0x04,0x61,0xf4 = vld3.8 {d16, d17, d18}, [r1] 0x4f,0x64,0x22,0xf4 = vld3.16 {d6, d7, d8}, [r2] 0x8f,0x14,0x23,0xf4 = vld3.32 {d1, d2, d3}, [r3] 0x1f,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64] 0x4f,0xb5,0x64,0xf4 = vld3.16 {d27, d29, d31}, [r4] 0x8f,0x65,0x25,0xf4 = vld3.32 {d6, d8, d10}, [r5] 0x01,0xc4,0x26,0xf4 = vld3.8 {d12, d13, d14}, [r6], r1 0x42,0xb4,0x27,0xf4 = vld3.16 {d11, d12, d13}, [r7], r2 0x83,0x24,0x28,0xf4 = vld3.32 {d2, d3, d4}, [r8], r3 0x04,0x45,0x29,0xf4 = vld3.8 {d4, d6, d8}, [r9], r4 0x44,0xe5,0x29,0xf4 = vld3.16 {d14, d16, d18}, [r9], r4 0x85,0x05,0x6a,0xf4 = vld3.32 {d16, d18, d20}, [r10], r5 0x0d,0x64,0x28,0xf4 = vld3.8 {d6, d7, d8}, [r8]! 0x4d,0x94,0x27,0xf4 = vld3.16 {d9, d10, d11}, [r7]! 0x8d,0x14,0x26,0xf4 = vld3.32 {d1, d2, d3}, [r6]! 0x1d,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64]! 0x4d,0x45,0x65,0xf4 = vld3.16 {d20, d22, d24}, [r5]! 0x8d,0x55,0x24,0xf4 = vld3.32 {d5, d7, d9}, [r4]! 0x1f,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64] 0x6f,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2:128] 0xbf,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:256] 0x3f,0x11,0x65,0xf4 = vld4.8 {d17, d19, d21, d23}, [r5:256] 0x4f,0x11,0x67,0xf4 = vld4.16 {d17, d19, d21, d23}, [r7] 0x8f,0x01,0x68,0xf4 = vld4.32 {d16, d18, d20, d22}, [r8] 0x1d,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64]! 0x6d,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2:128]! 0xbd,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:256]! 0x3d,0x11,0x65,0xf4 = vld4.8 {d17, d19, d21, d23}, [r5:256]! 0x4d,0x11,0x67,0xf4 = vld4.16 {d17, d19, d21, d23}, [r7]! 0x8d,0x01,0x68,0xf4 = vld4.32 {d16, d18, d20, d22}, [r8]! 0x18,0x00,0x61,0xf4 = vld4.8 {d16, d17, d18, d19}, [r1:64], r8 0x47,0x00,0x62,0xf4 = vld4.16 {d16, d17, d18, d19}, [r2], r7 0x95,0x00,0x63,0xf4 = vld4.32 {d16, d17, d18, d19}, [r3:64], r5 0x32,0x01,0x64,0xf4 = vld4.8 {d16, d18, d20, d22}, [r4:256], r2 0x43,0x01,0x66,0xf4 = vld4.16 {d16, d18, d20, d22}, [r6], r3 0x84,0x11,0x69,0xf4 = vld4.32 {d17, d19, d21, d23}, [r9], r4 0x0f,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1] 0x0d,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1]! 0x03,0x4c,0xa1,0xf4 = vld1.8 {d4[]}, [r1], r3 0x2f,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1] 0x2d,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1]! 0x23,0x4c,0xa1,0xf4 = vld1.8 {d4[], d5[]}, [r1], r3 0x6f,0x00,0xe0,0xf4 = vld1.8 {d16[3]}, [r0] 0x9f,0x04,0xe0,0xf4 = vld1.16 {d16[2]}, [r0:16] 0xbf,0x08,0xe0,0xf4 = vld1.32 {d16[1]}, [r0:32] 0xcd,0xc0,0xa2,0xf4 = vld1.8 {d12[6]}, [r2]! 0xc2,0xc0,0xa2,0xf4 = vld1.8 {d12[6]}, [r2], r2 0xcd,0xc4,0xa2,0xf4 = vld1.16 {d12[3]}, [r2]! 0x82,0xc4,0xa2,0xf4 = vld1.16 {d12[2]}, [r2], r2 0x3f,0x01,0xe0,0xf4 = vld2.8 {d16[1], d17[1]}, [r0:16] 0x5f,0x05,0xe0,0xf4 = vld2.16 {d16[1], d17[1]}, [r0:32] 0x8f,0x09,0xe0,0xf4 = vld2.32 {d16[1], d17[1]}, [r0] 0x6f,0x15,0xe0,0xf4 = vld2.16 {d17[1], d19[1]}, [r0] 0x5f,0x19,0xe0,0xf4 = vld2.32 {d17[0], d19[0]}, [r0:64] 0x5d,0x19,0xe0,0xf4 = vld2.32 {d17[0], d19[0]}, [r0:64]! 0x83,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2], r3 0x8d,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2]! 0x8f,0x21,0xa2,0xf4 = vld2.8 {d2[4], d3[4]}, [r2] 0x8f,0x6d,0xe1,0xf4 = vld2.32 {d22[], d23[]}, [r1] 0xaf,0x6d,0xe1,0xf4 = vld2.32 {d22[], d24[]}, [r1] 0x8d,0xad,0xa3,0xf4 = vld2.32 {d10[], d11[]}, [r3]! 0xad,0xed,0xa4,0xf4 = vld2.32 {d14[], d16[]}, [r4]! 0x84,0x6d,0xe5,0xf4 = vld2.32 {d22[], d23[]}, [r5], r4 0xa4,0x6d,0xe6,0xf4 = vld2.32 {d22[], d24[]}, [r6], r4 0x2f,0x02,0xe1,0xf4 = vld3.8 {d16[1], d17[1], d18[1]}, [r1] 0x4f,0x66,0xa2,0xf4 = vld3.16 {d6[1], d7[1], d8[1]}, [r2] 0x8f,0x1a,0xa3,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r3] 0xaf,0xb6,0xe4,0xf4 = vld3.16 {d27[2], d29[2], d31[2]}, [r4] 0x4f,0x6a,0xa5,0xf4 = vld3.32 {d6[0], d8[0], d10[0]}, [r5] 0x61,0xc2,0xa6,0xf4 = vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1 0x82,0xb6,0xa7,0xf4 = vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2 0x83,0x2a,0xa8,0xf4 = vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3 0xa4,0xe6,0xa9,0xf4 = vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4 0x45,0x0a,0xea,0xf4 = vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5 0xcd,0x62,0xa8,0xf4 = vld3.8 {d6[6], d7[6], d8[6]}, [r8]! 0x8d,0x96,0xa7,0xf4 = vld3.16 {d9[2], d10[2], d11[2]}, [r7]! 0x8d,0x1a,0xa6,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r6]! // 0xad,0x46,0xe5,0xf4 = vld3.16 {d20[2], d21[2], d22[2]}, [r5]! 0x4d,0x5a,0xa4,0xf4 = vld3.32 {d5[0], d7[0], d9[0]}, [r4]! 0x0f,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1] 0x4f,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2] 0x8f,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3] 0x2f,0x1e,0xe7,0xf4 = vld3.8 {d17[], d19[], d21[]}, [r7] 0x6f,0x1e,0xe7,0xf4 = vld3.16 {d17[], d19[], d21[]}, [r7] 0xaf,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8] 0x0d,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1]! 0x4d,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2]! 0x8d,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3]! // 0x2d,0x1e,0xe7,0xf4 = vld3.8 {d17[], d18[], d19[]}, [r7]! // 0x6d,0x1e,0xe7,0xf4 = vld3.16 {d17[], d18[], d19[]}, [r7]! 0xad,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8]! 0x08,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1], r8 0x47,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2], r7 0x85,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3], r5 0x23,0x0e,0xe6,0xf4 = vld3.8 {d16[], d18[], d20[]}, [r6], r3 0x63,0x0e,0xe6,0xf4 = vld3.16 {d16[], d18[], d20[]}, [r6], r3 0xa4,0x1e,0xe9,0xf4 = vld3.32 {d17[], d19[], d21[]}, [r9], r4 0x2f,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] 0x4f,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] 0x8f,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] 0x6f,0x17,0xe7,0xf4 = vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] 0xcf,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] 0x3d,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! 0x5d,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! 0xad,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! // 0x6d,0x17,0xe7,0xf4 = vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! 0xcd,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! 0x38,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 0x47,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 0x95,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 0x63,0x07,0xe6,0xf4 = vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 0xc4,0x1b,0xe9,0xf4 = vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 0x0f,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1] 0x4f,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2] 0x8f,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3] 0x2f,0x1f,0xe7,0xf4 = vld4.8 {d17[], d19[], d21[], d23[]}, [r7] 0x6f,0x1f,0xe7,0xf4 = vld4.16 {d17[], d19[], d21[], d23[]}, [r7] 0xaf,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8] 0x0d,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1]! 0x4d,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2]! 0x8d,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3]! // 0x2d,0x1f,0xe7,0xf4 = vld4.8 {d17[], d18[], d19[], d20[]}, [r7]! // 0x6d,0x1f,0xe7,0xf4 = vld4.16 {d17[], d18[], d19[], d20[]}, [r7]! 0xad,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8]! 0x08,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8 0x47,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7 0x85,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5 0x23,0x0f,0xe6,0xf4 = vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3 0x63,0x0f,0xe6,0xf4 = vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3 0xa4,0x1f,0xe9,0xf4 = vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4 0x0f,0x6a,0x29,0xf4 = vld1.8 {d6, d7}, [r9] 0x0f,0x62,0x29,0xf4 = vld1.8 {d6, d7, d8, d9}, [r9] 0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2] 0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2] 0x0f,0x27,0x22,0xf4 = vld1.8 {d2}, [r2] 0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2] 0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2] 0x0f,0x4a,0x22,0xf4 = vld1.8 {d4, d5}, [r2] 0x8f,0x4a,0x22,0xf4 = vld1.32 {d4, d5}, [r2] 0x0f,0x26,0x22,0xf4 = vld1.8 {d2, d3, d4}, [r2] 0x8f,0x26,0x22,0xf4 = vld1.32 {d2, d3, d4}, [r2] 0xcf,0x26,0x22,0xf4 = vld1.64 {d2, d3, d4}, [r2] 0xed,0x22,0x22,0xf4 = vld1.64 {d2, d3, d4, d5}, [r2:128]! 0xed,0x22,0x22,0xf4 = vld1.64 {d2, d3, d4, d5}, [r2:128]! 0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64] 0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128] capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-vst-encoding.s.cs000064400000000000000000000151720072674642500224050ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x1f,0x07,0x40,0xf4 = vst1.8 {d16}, [r0:64] 0x4f,0x07,0x40,0xf4 = vst1.16 {d16}, [r0] 0x8f,0x07,0x40,0xf4 = vst1.32 {d16}, [r0] 0xcf,0x07,0x40,0xf4 = vst1.64 {d16}, [r0] 0x1f,0x0a,0x40,0xf4 = vst1.8 {d16, d17}, [r0:64] 0x6f,0x0a,0x40,0xf4 = vst1.16 {d16, d17}, [r0:128] 0x8f,0x0a,0x40,0xf4 = vst1.32 {d16, d17}, [r0] 0xcf,0x0a,0x40,0xf4 = vst1.64 {d16, d17}, [r0] 0x1f,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0:64] 0x1d,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0:64]! 0x03,0x06,0x40,0xf4 = vst1.8 {d16, d17, d18}, [r0], r3 0x1f,0x02,0x40,0xf4 = vst1.8 {d16, d17, d18, d19}, [r0:64] 0x5d,0x02,0x41,0xf4 = vst1.16 {d16, d17, d18, d19}, [r1:64]! 0xc2,0x02,0x43,0xf4 = vst1.64 {d16, d17, d18, d19}, [r3], r2 0x1f,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64] 0x6f,0x08,0x40,0xf4 = vst2.16 {d16, d17}, [r0:128] 0x8f,0x08,0x40,0xf4 = vst2.32 {d16, d17}, [r0] 0x1f,0x03,0x40,0xf4 = vst2.8 {d16, d17, d18, d19}, [r0:64] 0x6f,0x03,0x40,0xf4 = vst2.16 {d16, d17, d18, d19}, [r0:128] 0xbf,0x03,0x40,0xf4 = vst2.32 {d16, d17, d18, d19}, [r0:256] 0x1d,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64]! 0x6d,0xe8,0x40,0xf4 = vst2.16 {d30, d31}, [r0:128]! 0x8d,0xe8,0x00,0xf4 = vst2.32 {d14, d15}, [r0]! 0x1d,0x03,0x40,0xf4 = vst2.8 {d16, d17, d18, d19}, [r0:64]! 0x6d,0x23,0x40,0xf4 = vst2.16 {d18, d19, d20, d21}, [r0:128]! 0xbd,0x83,0x00,0xf4 = vst2.32 {d8, d9, d10, d11}, [r0:256]! 0x0f,0x04,0x41,0xf4 = vst3.8 {d16, d17, d18}, [r1] 0x4f,0x64,0x02,0xf4 = vst3.16 {d6, d7, d8}, [r2] 0x8f,0x14,0x03,0xf4 = vst3.32 {d1, d2, d3}, [r3] 0x1f,0x05,0x40,0xf4 = vst3.8 {d16, d18, d20}, [r0:64] 0x4f,0xb5,0x44,0xf4 = vst3.16 {d27, d29, d31}, [r4] 0x8f,0x65,0x05,0xf4 = vst3.32 {d6, d8, d10}, [r5] 0x01,0xc4,0x06,0xf4 = vst3.8 {d12, d13, d14}, [r6], r1 0x42,0xb4,0x07,0xf4 = vst3.16 {d11, d12, d13}, [r7], r2 0x83,0x24,0x08,0xf4 = vst3.32 {d2, d3, d4}, [r8], r3 0x04,0x45,0x09,0xf4 = vst3.8 {d4, d6, d8}, [r9], r4 0x44,0xe5,0x09,0xf4 = vst3.16 {d14, d16, d18}, [r9], r4 0x85,0x05,0x4a,0xf4 = vst3.32 {d16, d18, d20}, [r10], r5 0x0d,0x64,0x08,0xf4 = vst3.8 {d6, d7, d8}, [r8]! 0x4d,0x94,0x07,0xf4 = vst3.16 {d9, d10, d11}, [r7]! 0x8d,0x14,0x06,0xf4 = vst3.32 {d1, d2, d3}, [r6]! 0x1d,0x05,0x40,0xf4 = vst3.8 {d16, d18, d20}, [r0:64]! 0x4d,0x45,0x45,0xf4 = vst3.16 {d20, d22, d24}, [r5]! 0x8d,0x55,0x04,0xf4 = vst3.32 {d5, d7, d9}, [r4]! 0x1f,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64] 0x6f,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2:128] 0xbf,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:256] 0x3f,0x11,0x45,0xf4 = vst4.8 {d17, d19, d21, d23}, [r5:256] 0x4f,0x11,0x47,0xf4 = vst4.16 {d17, d19, d21, d23}, [r7] 0x8f,0x01,0x48,0xf4 = vst4.32 {d16, d18, d20, d22}, [r8] 0x1d,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64]! 0x6d,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2:128]! 0xbd,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:256]! 0x3d,0x11,0x45,0xf4 = vst4.8 {d17, d19, d21, d23}, [r5:256]! 0x4d,0x11,0x47,0xf4 = vst4.16 {d17, d19, d21, d23}, [r7]! 0x8d,0x01,0x48,0xf4 = vst4.32 {d16, d18, d20, d22}, [r8]! 0x18,0x00,0x41,0xf4 = vst4.8 {d16, d17, d18, d19}, [r1:64], r8 0x47,0x00,0x42,0xf4 = vst4.16 {d16, d17, d18, d19}, [r2], r7 0x95,0x00,0x43,0xf4 = vst4.32 {d16, d17, d18, d19}, [r3:64], r5 0x32,0x01,0x44,0xf4 = vst4.8 {d16, d18, d20, d22}, [r4:256], r2 0x43,0x01,0x46,0xf4 = vst4.16 {d16, d18, d20, d22}, [r6], r3 0x84,0x11,0x49,0xf4 = vst4.32 {d17, d19, d21, d23}, [r9], r4 0x3f,0x01,0xc0,0xf4 = vst2.8 {d16[1], d17[1]}, [r0:16] 0x5f,0x05,0xc0,0xf4 = vst2.16 {d16[1], d17[1]}, [r0:32] 0x8f,0x09,0xc0,0xf4 = vst2.32 {d16[1], d17[1]}, [r0] 0x6f,0x15,0xc0,0xf4 = vst2.16 {d17[1], d19[1]}, [r0] 0x5f,0x19,0xc0,0xf4 = vst2.32 {d17[0], d19[0]}, [r0:64] 0x83,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2], r3 0x8d,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2]! 0x8f,0x21,0x82,0xf4 = vst2.8 {d2[4], d3[4]}, [r2] 0x6f,0x15,0xc0,0xf4 = vst2.16 {d17[1], d19[1]}, [r0] 0x5f,0x19,0xc0,0xf4 = vst2.32 {d17[0], d19[0]}, [r0:64] 0x6d,0x75,0x81,0xf4 = vst2.16 {d7[1], d9[1]}, [r1]! 0x5d,0x69,0x82,0xf4 = vst2.32 {d6[0], d8[0]}, [r2:64]! 0x65,0x25,0x83,0xf4 = vst2.16 {d2[1], d4[1]}, [r3], r5 0x57,0x59,0x84,0xf4 = vst2.32 {d5[0], d7[0]}, [r4:64], r7 0x2f,0x02,0xc1,0xf4 = vst3.8 {d16[1], d17[1], d18[1]}, [r1] 0x4f,0x66,0x82,0xf4 = vst3.16 {d6[1], d7[1], d8[1]}, [r2] 0x8f,0x1a,0x83,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r3] 0x6f,0xb6,0xc4,0xf4 = vst3.16 {d27[1], d29[1], d31[1]}, [r4] 0xcf,0x6a,0x85,0xf4 = vst3.32 {d6[1], d8[1], d10[1]}, [r5] 0x21,0xc2,0x86,0xf4 = vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1 0x42,0xb6,0x87,0xf4 = vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2 0x83,0x2a,0x88,0xf4 = vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3 0x64,0xe6,0x89,0xf4 = vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4 0xc5,0x0a,0xca,0xf4 = vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5 0x2d,0x62,0x88,0xf4 = vst3.8 {d6[1], d7[1], d8[1]}, [r8]! 0x4d,0x96,0x87,0xf4 = vst3.16 {d9[1], d10[1], d11[1]}, [r7]! 0x8d,0x1a,0x86,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r6]! // 0x6d,0x46,0xc5,0xf4 = vst3.16 {d20[1], d21[1], d22[1]}, [r5]! 0xcd,0x5a,0x84,0xf4 = vst3.32 {d5[1], d7[1], d9[1]}, [r4]! 0x2f,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1] 0x4f,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2] 0x8f,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] 0x6f,0x17,0xc7,0xf4 = vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] 0xcf,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] 0x3d,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! 0x5d,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! 0xad,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! // 0x6d,0x17,0xc7,0xf4 = vst4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! 0xcd,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! 0x38,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 0x47,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 0x95,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 0x63,0x07,0xc6,0xf4 = vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 0xc4,0x1b,0xc9,0xf4 = vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2] 0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2] 0x0f,0x27,0x02,0xf4 = vst1.8 {d2}, [r2] 0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2] 0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2] 0x0f,0x4a,0x02,0xf4 = vst1.8 {d4, d5}, [r2] 0x8f,0x4a,0x02,0xf4 = vst1.32 {d4, d5}, [r2] 0x0f,0x89,0x04,0xf4 = vst2.8 {d8, d10}, [r4] 0xbf,0x98,0x83,0xf4 = vst1.32 {d9[1]}, [r3:32] 0xbd,0xb8,0xc9,0xf4 = vst1.32 {d27[1]}, [r9:32]! 0xb5,0xb8,0xc3,0xf4 = vst1.32 {d27[1]}, [r3:32], r5 0x1f,0x08,0x40,0xf4 = vst2.8 {d16, d17}, [r0:64] 0x6f,0x08,0x40,0xf4 = vst2.16 {d16, d17}, [r0:128] capstone-sys-0.15.0/capstone/suite/MC/ARM/neon-vswp.s.cs000064400000000000000000000001450072674642500207760ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x02,0x10,0xb2,0xf3 = vswp d1, d2 0x44,0x20,0xb2,0xf3 = vswp q1, q2 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-abs-encoding.s.cs000064400000000000000000000011070072674642500225750ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf1,0xff,0x20,0x03 = vabs.s8 d16, d16 0xf5,0xff,0x20,0x03 = vabs.s16 d16, d16 0xf9,0xff,0x20,0x03 = vabs.s32 d16, d16 0xf9,0xff,0x20,0x07 = vabs.f32 d16, d16 0xf1,0xff,0x60,0x03 = vabs.s8 q8, q8 0xf5,0xff,0x60,0x03 = vabs.s16 q8, q8 0xf9,0xff,0x60,0x03 = vabs.s32 q8, q8 0xf9,0xff,0x60,0x07 = vabs.f32 q8, q8 0xf0,0xff,0x20,0x07 = vqabs.s8 d16, d16 0xf4,0xff,0x20,0x07 = vqabs.s16 d16, d16 0xf8,0xff,0x20,0x07 = vqabs.s32 d16, d16 0xf0,0xff,0x60,0x07 = vqabs.s8 q8, q8 0xf4,0xff,0x60,0x07 = vqabs.s16 q8, q8 0xf8,0xff,0x60,0x07 = vqabs.s32 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-absdiff-encoding.s.cs000064400000000000000000000032440072674642500234320ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x40,0xef,0xa1,0x07 = vabd.s8 d16, d16, d17 0x50,0xef,0xa1,0x07 = vabd.s16 d16, d16, d17 0x60,0xef,0xa1,0x07 = vabd.s32 d16, d16, d17 0x40,0xff,0xa1,0x07 = vabd.u8 d16, d16, d17 0x50,0xff,0xa1,0x07 = vabd.u16 d16, d16, d17 0x60,0xff,0xa1,0x07 = vabd.u32 d16, d16, d17 0x60,0xff,0xa1,0x0d = vabd.f32 d16, d16, d17 0x40,0xef,0xe2,0x07 = vabd.s8 q8, q8, q9 0x50,0xef,0xe2,0x07 = vabd.s16 q8, q8, q9 0x60,0xef,0xe2,0x07 = vabd.s32 q8, q8, q9 0x40,0xff,0xe2,0x07 = vabd.u8 q8, q8, q9 0x50,0xff,0xe2,0x07 = vabd.u16 q8, q8, q9 0x60,0xff,0xe2,0x07 = vabd.u32 q8, q8, q9 0x60,0xff,0xe2,0x0d = vabd.f32 q8, q8, q9 0xc0,0xef,0xa1,0x07 = vabdl.s8 q8, d16, d17 0xd0,0xef,0xa1,0x07 = vabdl.s16 q8, d16, d17 0xe0,0xef,0xa1,0x07 = vabdl.s32 q8, d16, d17 0xc0,0xff,0xa1,0x07 = vabdl.u8 q8, d16, d17 0xd0,0xff,0xa1,0x07 = vabdl.u16 q8, d16, d17 0xe0,0xff,0xa1,0x07 = vabdl.u32 q8, d16, d17 0x42,0xef,0xb1,0x07 = vaba.s8 d16, d18, d17 0x52,0xef,0xb1,0x07 = vaba.s16 d16, d18, d17 0x62,0xef,0xb1,0x07 = vaba.s32 d16, d18, d17 0x42,0xff,0xb1,0x07 = vaba.u8 d16, d18, d17 0x52,0xff,0xb1,0x07 = vaba.u16 d16, d18, d17 0x62,0xff,0xb1,0x07 = vaba.u32 d16, d18, d17 0x40,0xef,0xf4,0x27 = vaba.s8 q9, q8, q10 0x50,0xef,0xf4,0x27 = vaba.s16 q9, q8, q10 0x60,0xef,0xf4,0x27 = vaba.s32 q9, q8, q10 0x40,0xff,0xf4,0x27 = vaba.u8 q9, q8, q10 0x50,0xff,0xf4,0x27 = vaba.u16 q9, q8, q10 0x60,0xff,0xf4,0x27 = vaba.u32 q9, q8, q10 0xc3,0xef,0xa2,0x05 = vabal.s8 q8, d19, d18 0xd3,0xef,0xa2,0x05 = vabal.s16 q8, d19, d18 0xe3,0xef,0xa2,0x05 = vabal.s32 q8, d19, d18 0xc3,0xff,0xa2,0x05 = vabal.u8 q8, d19, d18 0xd3,0xff,0xa2,0x05 = vabal.u16 q8, d19, d18 0xe3,0xff,0xa2,0x05 = vabal.u32 q8, d19, d18 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-add-encoding.s.cs000064400000000000000000000055040072674642500225650ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x41,0xef,0xa0,0x08 = vadd.i8 d16, d17, d16 0x51,0xef,0xa0,0x08 = vadd.i16 d16, d17, d16 0x71,0xef,0xa0,0x08 = vadd.i64 d16, d17, d16 0x61,0xef,0xa0,0x08 = vadd.i32 d16, d17, d16 0x40,0xef,0xa1,0x0d = vadd.f32 d16, d16, d17 0x40,0xef,0xe2,0x0d = vadd.f32 q8, q8, q9 0xc1,0xef,0xa0,0x00 = vaddl.s8 q8, d17, d16 0xd1,0xef,0xa0,0x00 = vaddl.s16 q8, d17, d16 0xe1,0xef,0xa0,0x00 = vaddl.s32 q8, d17, d16 0xc1,0xff,0xa0,0x00 = vaddl.u8 q8, d17, d16 0xd1,0xff,0xa0,0x00 = vaddl.u16 q8, d17, d16 0xe1,0xff,0xa0,0x00 = vaddl.u32 q8, d17, d16 0xc0,0xef,0xa2,0x01 = vaddw.s8 q8, q8, d18 0xd0,0xef,0xa2,0x01 = vaddw.s16 q8, q8, d18 0xe0,0xef,0xa2,0x01 = vaddw.s32 q8, q8, d18 0xc0,0xff,0xa2,0x01 = vaddw.u8 q8, q8, d18 0xd0,0xff,0xa2,0x01 = vaddw.u16 q8, q8, d18 0xe0,0xff,0xa2,0x01 = vaddw.u32 q8, q8, d18 0x40,0xef,0xa1,0x00 = vhadd.s8 d16, d16, d17 0x50,0xef,0xa1,0x00 = vhadd.s16 d16, d16, d17 0x60,0xef,0xa1,0x00 = vhadd.s32 d16, d16, d17 0x40,0xff,0xa1,0x00 = vhadd.u8 d16, d16, d17 0x50,0xff,0xa1,0x00 = vhadd.u16 d16, d16, d17 0x60,0xff,0xa1,0x00 = vhadd.u32 d16, d16, d17 0x40,0xef,0xe2,0x00 = vhadd.s8 q8, q8, q9 0x50,0xef,0xe2,0x00 = vhadd.s16 q8, q8, q9 0x60,0xef,0xe2,0x00 = vhadd.s32 q8, q8, q9 0x40,0xff,0xe2,0x00 = vhadd.u8 q8, q8, q9 0x50,0xff,0xe2,0x00 = vhadd.u16 q8, q8, q9 0x60,0xff,0xe2,0x00 = vhadd.u32 q8, q8, q9 0x40,0xef,0xa1,0x01 = vrhadd.s8 d16, d16, d17 0x50,0xef,0xa1,0x01 = vrhadd.s16 d16, d16, d17 0x60,0xef,0xa1,0x01 = vrhadd.s32 d16, d16, d17 0x40,0xff,0xa1,0x01 = vrhadd.u8 d16, d16, d17 0x50,0xff,0xa1,0x01 = vrhadd.u16 d16, d16, d17 0x60,0xff,0xa1,0x01 = vrhadd.u32 d16, d16, d17 0x40,0xef,0xe2,0x01 = vrhadd.s8 q8, q8, q9 0x50,0xef,0xe2,0x01 = vrhadd.s16 q8, q8, q9 0x60,0xef,0xe2,0x01 = vrhadd.s32 q8, q8, q9 0x40,0xff,0xe2,0x01 = vrhadd.u8 q8, q8, q9 0x50,0xff,0xe2,0x01 = vrhadd.u16 q8, q8, q9 0x60,0xff,0xe2,0x01 = vrhadd.u32 q8, q8, q9 0x40,0xef,0xb1,0x00 = vqadd.s8 d16, d16, d17 0x50,0xef,0xb1,0x00 = vqadd.s16 d16, d16, d17 0x60,0xef,0xb1,0x00 = vqadd.s32 d16, d16, d17 0x70,0xef,0xb1,0x00 = vqadd.s64 d16, d16, d17 0x40,0xff,0xb1,0x00 = vqadd.u8 d16, d16, d17 0x50,0xff,0xb1,0x00 = vqadd.u16 d16, d16, d17 0x60,0xff,0xb1,0x00 = vqadd.u32 d16, d16, d17 0x70,0xff,0xb1,0x00 = vqadd.u64 d16, d16, d17 0x40,0xef,0xf2,0x00 = vqadd.s8 q8, q8, q9 0x50,0xef,0xf2,0x00 = vqadd.s16 q8, q8, q9 0x60,0xef,0xf2,0x00 = vqadd.s32 q8, q8, q9 0x70,0xef,0xf2,0x00 = vqadd.s64 q8, q8, q9 0x40,0xff,0xf2,0x00 = vqadd.u8 q8, q8, q9 0x50,0xff,0xf2,0x00 = vqadd.u16 q8, q8, q9 0x60,0xff,0xf2,0x00 = vqadd.u32 q8, q8, q9 0x70,0xff,0xf2,0x00 = vqadd.u64 q8, q8, q9 0xc0,0xef,0xa2,0x04 = vaddhn.i16 d16, q8, q9 0xd0,0xef,0xa2,0x04 = vaddhn.i32 d16, q8, q9 0xe0,0xef,0xa2,0x04 = vaddhn.i64 d16, q8, q9 0xc0,0xff,0xa2,0x04 = vraddhn.i16 d16, q8, q9 0xd0,0xff,0xa2,0x04 = vraddhn.i32 d16, q8, q9 0xe0,0xff,0xa2,0x04 = vraddhn.i64 d16, q8, q9 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-bitcount-encoding.s.cs000064400000000000000000000010750072674642500236630ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf0,0xff,0x20,0x05 = vcnt.8 d16, d16 0xf0,0xff,0x60,0x05 = vcnt.8 q8, q8 0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16 0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16 0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8 0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8 0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16 0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16 0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16 0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8 0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8 0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-bitwise-encoding.s.cs000064400000000000000000000011040072674642500234730ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x41,0xef,0xb0,0x01 = vand d16, d17, d16 0x40,0xef,0xf2,0x01 = vand q8, q8, q9 0x41,0xff,0xb0,0x01 = veor d16, d17, d16 0x40,0xff,0xf2,0x01 = veor q8, q8, q9 0x61,0xef,0xb0,0x01 = vorr d16, d17, d16 0x60,0xef,0xf2,0x01 = vorr q8, q8, q9 0x51,0xef,0xb0,0x01 = vbic d16, d17, d16 0x50,0xef,0xf2,0x01 = vbic q8, q8, q9 0x71,0xef,0xb0,0x01 = vorn d16, d17, d16 0x70,0xef,0xf2,0x01 = vorn q8, q8, q9 0xf0,0xff,0xa0,0x05 = vmvn d16, d16 0xf0,0xff,0xe0,0x05 = vmvn q8, q8 0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16 0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-cmp-encoding.s.cs000064400000000000000000000013630072674642500226130ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-convert-encoding.s.cs000064400000000000000000000015110072674642500235070ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1 0xf6,0xff,0x20,0x07 = vcvt.f32.f16 q8, d16 0xf6,0xff,0x20,0x06 = vcvt.f16.f32 d16, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-dup-encoding.s.cs000064400000000000000000000013540072674642500226240ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xc0,0xee,0x90,0x1b = vdup.8 d16, r1 0x8f,0xee,0x30,0x2b = vdup.16 d15, r2 0x8e,0xee,0x10,0x3b = vdup.32 d14, r3 0xe2,0xee,0x90,0x4b = vdup.8 q9, r4 0xa0,0xee,0xb0,0x5b = vdup.16 q8, r5 0xae,0xee,0x10,0x6b = vdup.32 q7, r6 0xf1,0xff,0x0b,0x0c = vdup.8 d16, d11[0] 0xf2,0xff,0x0c,0x1c = vdup.16 d17, d12[0] 0xf4,0xff,0x0d,0x2c = vdup.32 d18, d13[0] 0xb1,0xff,0x4a,0x6c = vdup.8 q3, d10[0] 0xf2,0xff,0x49,0x2c = vdup.16 q9, d9[0] 0xf4,0xff,0x48,0x0c = vdup.32 q8, d8[0] 0xf3,0xff,0x0b,0x0c = vdup.8 d16, d11[1] 0xf6,0xff,0x0c,0x1c = vdup.16 d17, d12[1] 0xfc,0xff,0x0d,0x2c = vdup.32 d18, d13[1] 0xb3,0xff,0x4a,0x6c = vdup.8 q3, d10[1] 0xf6,0xff,0x49,0x2c = vdup.16 q9, d9[1] 0xfc,0xff,0x48,0x0c = vdup.32 q8, d8[1] capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-minmax-encoding.s.cs000064400000000000000000000046030072674642500233250ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x02,0xef,0x03,0x16 = vmax.s8 d1, d2, d3 0x15,0xef,0x06,0x46 = vmax.s16 d4, d5, d6 0x28,0xef,0x09,0x76 = vmax.s32 d7, d8, d9 0x0b,0xff,0x0c,0xa6 = vmax.u8 d10, d11, d12 0x1e,0xff,0x0f,0xd6 = vmax.u16 d13, d14, d15 0x61,0xff,0xa2,0x06 = vmax.u32 d16, d17, d18 0x44,0xef,0xa5,0x3f = vmax.f32 d19, d20, d21 0x02,0xef,0x03,0x26 = vmax.s8 d2, d2, d3 0x15,0xef,0x06,0x56 = vmax.s16 d5, d5, d6 0x28,0xef,0x09,0x86 = vmax.s32 d8, d8, d9 0x0b,0xff,0x0c,0xb6 = vmax.u8 d11, d11, d12 0x1e,0xff,0x0f,0xe6 = vmax.u16 d14, d14, d15 0x61,0xff,0xa2,0x16 = vmax.u32 d17, d17, d18 0x44,0xef,0xa5,0x4f = vmax.f32 d20, d20, d21 0x04,0xef,0x46,0x26 = vmax.s8 q1, q2, q3 0x1a,0xef,0x4c,0x86 = vmax.s16 q4, q5, q6 0x20,0xef,0xe2,0xe6 = vmax.s32 q7, q8, q9 0x46,0xff,0xe8,0x46 = vmax.u8 q10, q11, q12 0x5c,0xff,0xee,0xa6 = vmax.u16 q13, q14, q15 0x2e,0xff,0x60,0xc6 = vmax.u32 q6, q7, q8 0x4a,0xef,0x42,0x2f = vmax.f32 q9, q5, q1 0x04,0xef,0x46,0x46 = vmax.s8 q2, q2, q3 0x1a,0xef,0x4c,0xa6 = vmax.s16 q5, q5, q6 0x60,0xef,0xe2,0x06 = vmax.s32 q8, q8, q9 0x46,0xff,0xc4,0x66 = vmax.u8 q11, q11, q2 0x18,0xff,0x4a,0x86 = vmax.u16 q4, q4, q5 0x2e,0xff,0x60,0xe6 = vmax.u32 q7, q7, q8 0x04,0xef,0x42,0x4f = vmax.f32 q2, q2, q1 0x02,0xef,0x13,0x16 = vmin.s8 d1, d2, d3 0x15,0xef,0x16,0x46 = vmin.s16 d4, d5, d6 0x28,0xef,0x19,0x76 = vmin.s32 d7, d8, d9 0x0b,0xff,0x1c,0xa6 = vmin.u8 d10, d11, d12 0x1e,0xff,0x1f,0xd6 = vmin.u16 d13, d14, d15 0x61,0xff,0xb2,0x06 = vmin.u32 d16, d17, d18 0x64,0xef,0xa5,0x3f = vmin.f32 d19, d20, d21 0x02,0xef,0x13,0x26 = vmin.s8 d2, d2, d3 0x15,0xef,0x16,0x56 = vmin.s16 d5, d5, d6 0x28,0xef,0x19,0x86 = vmin.s32 d8, d8, d9 0x0b,0xff,0x1c,0xb6 = vmin.u8 d11, d11, d12 0x1e,0xff,0x1f,0xe6 = vmin.u16 d14, d14, d15 0x61,0xff,0xb2,0x16 = vmin.u32 d17, d17, d18 0x64,0xef,0xa5,0x4f = vmin.f32 d20, d20, d21 0x04,0xef,0x56,0x26 = vmin.s8 q1, q2, q3 0x1a,0xef,0x5c,0x86 = vmin.s16 q4, q5, q6 0x20,0xef,0xf2,0xe6 = vmin.s32 q7, q8, q9 0x46,0xff,0xf8,0x46 = vmin.u8 q10, q11, q12 0x5c,0xff,0xfe,0xa6 = vmin.u16 q13, q14, q15 0x2e,0xff,0x70,0xc6 = vmin.u32 q6, q7, q8 0x6a,0xef,0x42,0x2f = vmin.f32 q9, q5, q1 0x04,0xef,0x56,0x46 = vmin.s8 q2, q2, q3 0x1a,0xef,0x5c,0xa6 = vmin.s16 q5, q5, q6 0x60,0xef,0xf2,0x06 = vmin.s32 q8, q8, q9 0x46,0xff,0xd4,0x66 = vmin.u8 q11, q11, q2 0x18,0xff,0x5a,0x86 = vmin.u16 q4, q4, q5 0x2e,0xff,0x70,0xe6 = vmin.u32 q7, q7, q8 0x24,0xef,0x42,0x4f = vmin.f32 q2, q2, q1 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-mov-encoding.s.cs000064400000000000000000000046420072674642500226400ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xc0,0xef,0x18,0x0e = vmov.i8 d16, #0x8 0xc1,0xef,0x10,0x08 = vmov.i16 d16, #0x10 0xc1,0xef,0x10,0x0a = vmov.i16 d16, #0x1000 0xc2,0xef,0x10,0x00 = vmov.i32 d16, #0x20 0xc2,0xef,0x10,0x02 = vmov.i32 d16, #0x2000 0xc2,0xef,0x10,0x04 = vmov.i32 d16, #0x200000 0xc2,0xef,0x10,0x06 = vmov.i32 d16, #0x20000000 0xc2,0xef,0x10,0x0c = vmov.i32 d16, #0x20ff 0xc2,0xef,0x10,0x0d = vmov.i32 d16, #0x20ffff 0xc1,0xff,0x33,0x0e = vmov.i64 d16, #0xff0000ff0000ffff 0xc0,0xef,0x58,0x0e = vmov.i8 q8, #0x8 0xc1,0xef,0x50,0x08 = vmov.i16 q8, #0x10 0xc1,0xef,0x50,0x0a = vmov.i16 q8, #0x1000 0xc2,0xef,0x50,0x00 = vmov.i32 q8, #0x20 0xc2,0xef,0x50,0x02 = vmov.i32 q8, #0x2000 0xc2,0xef,0x50,0x04 = vmov.i32 q8, #0x200000 0xc2,0xef,0x50,0x06 = vmov.i32 q8, #0x20000000 0xc2,0xef,0x50,0x0c = vmov.i32 q8, #0x20ff 0xc2,0xef,0x50,0x0d = vmov.i32 q8, #0x20ffff 0xc1,0xff,0x73,0x0e = vmov.i64 q8, #0xff0000ff0000ffff 0xc1,0xef,0x30,0x08 = vmvn.i16 d16, #0x10 0xc1,0xef,0x30,0x0a = vmvn.i16 d16, #0x1000 0xc2,0xef,0x30,0x00 = vmvn.i32 d16, #0x20 0xc2,0xef,0x30,0x02 = vmvn.i32 d16, #0x2000 0xc2,0xef,0x30,0x04 = vmvn.i32 d16, #0x200000 0xc2,0xef,0x30,0x06 = vmvn.i32 d16, #0x20000000 0xc2,0xef,0x30,0x0c = vmvn.i32 d16, #0x20ff 0xc2,0xef,0x30,0x0d = vmvn.i32 d16, #0x20ffff 0xc8,0xef,0x30,0x0a = vmovl.s8 q8, d16 0xd0,0xef,0x30,0x0a = vmovl.s16 q8, d16 0xe0,0xef,0x30,0x0a = vmovl.s32 q8, d16 0xc8,0xff,0x30,0x0a = vmovl.u8 q8, d16 0xd0,0xff,0x30,0x0a = vmovl.u16 q8, d16 0xe0,0xff,0x30,0x0a = vmovl.u32 q8, d16 0xf2,0xff,0x20,0x02 = vmovn.i16 d16, q8 0xf6,0xff,0x20,0x02 = vmovn.i32 d16, q8 0xfa,0xff,0x20,0x02 = vmovn.i64 d16, q8 0xf2,0xff,0xa0,0x02 = vqmovn.s16 d16, q8 0xf6,0xff,0xa0,0x02 = vqmovn.s32 d16, q8 0xfa,0xff,0xa0,0x02 = vqmovn.s64 d16, q8 0xf2,0xff,0xe0,0x02 = vqmovn.u16 d16, q8 0xf6,0xff,0xe0,0x02 = vqmovn.u32 d16, q8 0xfa,0xff,0xe0,0x02 = vqmovn.u64 d16, q8 0xf2,0xff,0x60,0x02 = vqmovun.s16 d16, q8 0xf6,0xff,0x60,0x02 = vqmovun.s32 d16, q8 0xfa,0xff,0x60,0x02 = vqmovun.s64 d16, q8 0x50,0xee,0xb0,0x0b = vmov.s8 r0, d16[1] 0x10,0xee,0xf0,0x0b = vmov.s16 r0, d16[1] 0xd0,0xee,0xb0,0x0b = vmov.u8 r0, d16[1] 0x90,0xee,0xf0,0x0b = vmov.u16 r0, d16[1] 0x30,0xee,0x90,0x0b = vmov.32 r0, d16[1] 0x40,0xee,0xb0,0x1b = vmov.8 d16[1], r1 0x00,0xee,0xf0,0x1b = vmov.16 d16[1], r1 0x20,0xee,0x90,0x1b = vmov.32 d16[1], r1 0x42,0xee,0xb0,0x1b = vmov.8 d18[1], r1 0x02,0xee,0xf0,0x1b = vmov.16 d18[1], r1 0x22,0xee,0x90,0x1b = vmov.32 d18[1], r1 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-mul-accum-encoding.s.cs000064400000000000000000000034660072674642500237250ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x42,0xef,0xa1,0x09 = vmla.i8 d16, d18, d17 0x52,0xef,0xa1,0x09 = vmla.i16 d16, d18, d17 0x62,0xef,0xa1,0x09 = vmla.i32 d16, d18, d17 0x42,0xef,0xb1,0x0d = vmla.f32 d16, d18, d17 0x40,0xef,0xe4,0x29 = vmla.i8 q9, q8, q10 0x50,0xef,0xe4,0x29 = vmla.i16 q9, q8, q10 0x60,0xef,0xe4,0x29 = vmla.i32 q9, q8, q10 0x40,0xef,0xf4,0x2d = vmla.f32 q9, q8, q10 0xe0,0xff,0xc3,0x80 = vmla.i32 q12, q8, d3[0] 0xc3,0xef,0xa2,0x08 = vmlal.s8 q8, d19, d18 0xd3,0xef,0xa2,0x08 = vmlal.s16 q8, d19, d18 0xe3,0xef,0xa2,0x08 = vmlal.s32 q8, d19, d18 0xc3,0xff,0xa2,0x08 = vmlal.u8 q8, d19, d18 0xd3,0xff,0xa2,0x08 = vmlal.u16 q8, d19, d18 0xe3,0xff,0xa2,0x08 = vmlal.u32 q8, d19, d18 0xa5,0xef,0x4a,0x02 = vmlal.s32 q0, d5, d10[0] 0xd3,0xef,0xa2,0x09 = vqdmlal.s16 q8, d19, d18 0xe3,0xef,0xa2,0x09 = vqdmlal.s32 q8, d19, d18 0xdb,0xef,0x47,0x63 = vqdmlal.s16 q11, d11, d7[0] 0xdb,0xef,0x4f,0x63 = vqdmlal.s16 q11, d11, d7[1] 0xdb,0xef,0x67,0x63 = vqdmlal.s16 q11, d11, d7[2] 0xdb,0xef,0x6f,0x63 = vqdmlal.s16 q11, d11, d7[3] 0x42,0xff,0xa1,0x09 = vmls.i8 d16, d18, d17 0x52,0xff,0xa1,0x09 = vmls.i16 d16, d18, d17 0x62,0xff,0xa1,0x09 = vmls.i32 d16, d18, d17 0x62,0xef,0xb1,0x0d = vmls.f32 d16, d18, d17 0x40,0xff,0xe4,0x29 = vmls.i8 q9, q8, q10 0x50,0xff,0xe4,0x29 = vmls.i16 q9, q8, q10 0x60,0xff,0xe4,0x29 = vmls.i32 q9, q8, q10 0x60,0xef,0xf4,0x2d = vmls.f32 q9, q8, q10 0x98,0xff,0xe6,0x84 = vmls.i16 q4, q12, d6[2] 0xc3,0xef,0xa2,0x0a = vmlsl.s8 q8, d19, d18 0xd3,0xef,0xa2,0x0a = vmlsl.s16 q8, d19, d18 0xe3,0xef,0xa2,0x0a = vmlsl.s32 q8, d19, d18 0xc3,0xff,0xa2,0x0a = vmlsl.u8 q8, d19, d18 0xd3,0xff,0xa2,0x0a = vmlsl.u16 q8, d19, d18 0xe3,0xff,0xa2,0x0a = vmlsl.u32 q8, d19, d18 0xd9,0xff,0xe9,0x66 = vmlsl.u16 q11, d25, d1[3] 0xd3,0xef,0xa2,0x0b = vqdmlsl.s16 q8, d19, d18 0xe3,0xef,0xa2,0x0b = vqdmlsl.s32 q8, d19, d18 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-mul-encoding.s.cs000064400000000000000000000025570072674642500226370ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x40,0xef,0xb1,0x09 = vmul.i8 d16, d16, d17 0x50,0xef,0xb1,0x09 = vmul.i16 d16, d16, d17 0x60,0xef,0xb1,0x09 = vmul.i32 d16, d16, d17 0x40,0xff,0xb1,0x0d = vmul.f32 d16, d16, d17 0x40,0xef,0xf2,0x09 = vmul.i8 q8, q8, q9 0x50,0xef,0xf2,0x09 = vmul.i16 q8, q8, q9 0x60,0xef,0xf2,0x09 = vmul.i32 q8, q8, q9 0x40,0xff,0xf2,0x0d = vmul.f32 q8, q8, q9 0x40,0xff,0xb1,0x09 = vmul.p8 d16, d16, d17 0x40,0xff,0xf2,0x09 = vmul.p8 q8, q8, q9 0xd8,0xef,0x68,0x28 = vmul.i16 d18, d8, d0[3] 0x50,0xef,0xa1,0x0b = vqdmulh.s16 d16, d16, d17 0x60,0xef,0xa1,0x0b = vqdmulh.s32 d16, d16, d17 0x50,0xef,0xe2,0x0b = vqdmulh.s16 q8, q8, q9 0x60,0xef,0xe2,0x0b = vqdmulh.s32 q8, q8, q9 0x92,0xef,0x43,0xbc = vqdmulh.s16 d11, d2, d3[0] 0x50,0xff,0xa1,0x0b = vqrdmulh.s16 d16, d16, d17 0x60,0xff,0xa1,0x0b = vqrdmulh.s32 d16, d16, d17 0x50,0xff,0xe2,0x0b = vqrdmulh.s16 q8, q8, q9 0x60,0xff,0xe2,0x0b = vqrdmulh.s32 q8, q8, q9 0xc0,0xef,0xa1,0x0c = vmull.s8 q8, d16, d17 0xd0,0xef,0xa1,0x0c = vmull.s16 q8, d16, d17 0xe0,0xef,0xa1,0x0c = vmull.s32 q8, d16, d17 0xc0,0xff,0xa1,0x0c = vmull.u8 q8, d16, d17 0xd0,0xff,0xa1,0x0c = vmull.u16 q8, d16, d17 0xe0,0xff,0xa1,0x0c = vmull.u32 q8, d16, d17 0xc0,0xef,0xa1,0x0e = vmull.p8 q8, d16, d17 0xd0,0xef,0xa1,0x0d = vqdmull.s16 q8, d16, d17 0xe0,0xef,0xa1,0x0d = vqdmull.s32 q8, d16, d17 0x97,0xef,0x49,0x2b = vqdmull.s16 q1, d7, d1[1] capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-neg-encoding.s.cs000064400000000000000000000011070072674642500226010ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf1,0xff,0xa0,0x03 = vneg.s8 d16, d16 0xf5,0xff,0xa0,0x03 = vneg.s16 d16, d16 0xf9,0xff,0xa0,0x03 = vneg.s32 d16, d16 0xf9,0xff,0xa0,0x07 = vneg.f32 d16, d16 0xf1,0xff,0xe0,0x03 = vneg.s8 q8, q8 0xf5,0xff,0xe0,0x03 = vneg.s16 q8, q8 0xf9,0xff,0xe0,0x03 = vneg.s32 q8, q8 0xf9,0xff,0xe0,0x07 = vneg.f32 q8, q8 0xf0,0xff,0xa0,0x07 = vqneg.s8 d16, d16 0xf4,0xff,0xa0,0x07 = vqneg.s16 d16, d16 0xf8,0xff,0xa0,0x07 = vqneg.s32 d16, d16 0xf0,0xff,0xe0,0x07 = vqneg.s8 q8, q8 0xf4,0xff,0xe0,0x07 = vqneg.s16 q8, q8 0xf8,0xff,0xe0,0x07 = vqneg.s32 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-pairwise-encoding.s.cs000064400000000000000000000034320072674642500236560ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x05,0xef,0x1b,0x1b = vpadd.i8 d1, d5, d11 0x12,0xef,0x1c,0xdb = vpadd.i16 d13, d2, d12 0x21,0xef,0x1d,0xeb = vpadd.i32 d14, d1, d13 0x40,0xff,0x8e,0x3d = vpadd.f32 d19, d16, d14 0xb0,0xff,0x0a,0x72 = vpaddl.s8 d7, d10 0xb4,0xff,0x0b,0x82 = vpaddl.s16 d8, d11 0xb8,0xff,0x0c,0x92 = vpaddl.s32 d9, d12 0xb0,0xff,0x8d,0x02 = vpaddl.u8 d0, d13 0xb4,0xff,0x8e,0x52 = vpaddl.u16 d5, d14 0xb8,0xff,0x8f,0x62 = vpaddl.u32 d6, d15 0xb0,0xff,0x4e,0x82 = vpaddl.s8 q4, q7 0xb4,0xff,0x4c,0xa2 = vpaddl.s16 q5, q6 0xb8,0xff,0x4a,0xc2 = vpaddl.s32 q6, q5 0xb0,0xff,0xc8,0xe2 = vpaddl.u8 q7, q4 0xf4,0xff,0xc6,0x02 = vpaddl.u16 q8, q3 0xf8,0xff,0xc4,0x22 = vpaddl.u32 q9, q2 0xf0,0xff,0x04,0x06 = vpadal.s8 d16, d4 0xf4,0xff,0x09,0x46 = vpadal.s16 d20, d9 0xf8,0xff,0x01,0x26 = vpadal.s32 d18, d1 0xb0,0xff,0xa9,0xe6 = vpadal.u8 d14, d25 0xb4,0xff,0x86,0xc6 = vpadal.u16 d12, d6 0xb8,0xff,0x87,0xb6 = vpadal.u32 d11, d7 0xb0,0xff,0x64,0x86 = vpadal.s8 q4, q10 0xb4,0xff,0x66,0xa6 = vpadal.s16 q5, q11 0xb8,0xff,0x68,0xc6 = vpadal.s32 q6, q12 0xb0,0xff,0xea,0xe6 = vpadal.u8 q7, q13 0xf4,0xff,0xec,0x06 = vpadal.u16 q8, q14 0xf8,0xff,0xee,0x26 = vpadal.u32 q9, q15 0x4d,0xef,0x9a,0x0a = vpmin.s8 d16, d29, d10 0x5c,0xef,0x9b,0x1a = vpmin.s16 d17, d28, d11 0x6b,0xef,0x9c,0x2a = vpmin.s32 d18, d27, d12 0x4a,0xff,0x9d,0x3a = vpmin.u8 d19, d26, d13 0x59,0xff,0x9e,0x4a = vpmin.u16 d20, d25, d14 0x68,0xff,0x9f,0x5a = vpmin.u32 d21, d24, d15 0x67,0xff,0xa0,0x6f = vpmin.f32 d22, d23, d16 0x04,0xef,0xa1,0x3a = vpmax.s8 d3, d20, d17 0x15,0xef,0xa0,0x4a = vpmax.s16 d4, d21, d16 0x26,0xef,0x8f,0x5a = vpmax.s32 d5, d22, d15 0x07,0xff,0x8e,0x6a = vpmax.u8 d6, d23, d14 0x18,0xff,0x8d,0x7a = vpmax.u16 d7, d24, d13 0x29,0xff,0x8c,0x8a = vpmax.u32 d8, d25, d12 0x0a,0xff,0x8b,0x9f = vpmax.f32 d9, d26, d11 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-reciprocal-encoding.s.cs000064400000000000000000000010470072674642500241560ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xfb,0xff,0x20,0x04 = vrecpe.u32 d16, d16 0xfb,0xff,0x60,0x04 = vrecpe.u32 q8, q8 0xfb,0xff,0x20,0x05 = vrecpe.f32 d16, d16 0xfb,0xff,0x60,0x05 = vrecpe.f32 q8, q8 0x40,0xef,0xb1,0x0f = vrecps.f32 d16, d16, d17 0x40,0xef,0xf2,0x0f = vrecps.f32 q8, q8, q9 0xfb,0xff,0xa0,0x04 = vrsqrte.u32 d16, d16 0xfb,0xff,0xe0,0x04 = vrsqrte.u32 q8, q8 0xfb,0xff,0xa0,0x05 = vrsqrte.f32 d16, d16 0xfb,0xff,0xe0,0x05 = vrsqrte.f32 q8, q8 0x60,0xef,0xb1,0x0f = vrsqrts.f32 d16, d16, d17 0x60,0xef,0xf2,0x0f = vrsqrts.f32 q8, q8, q9 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-reverse-encoding.s.cs000064400000000000000000000007750072674642500235150ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf0,0xff,0x20,0x00 = vrev64.8 d16, d16 0xf4,0xff,0x20,0x00 = vrev64.16 d16, d16 0xf8,0xff,0x20,0x00 = vrev64.32 d16, d16 0xf0,0xff,0x60,0x00 = vrev64.8 q8, q8 0xf4,0xff,0x60,0x00 = vrev64.16 q8, q8 0xf8,0xff,0x60,0x00 = vrev64.32 q8, q8 0xf0,0xff,0xa0,0x00 = vrev32.8 d16, d16 0xf4,0xff,0xa0,0x00 = vrev32.16 d16, d16 0xf0,0xff,0xe0,0x00 = vrev32.8 q8, q8 0xf4,0xff,0xe0,0x00 = vrev32.16 q8, q8 0xf0,0xff,0x20,0x01 = vrev16.8 d16, d16 0xf0,0xff,0x60,0x01 = vrev16.8 q8, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-satshift-encoding.s.cs000064400000000000000000000064640072674642500236700ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x41,0xef,0xb0,0x04 = vqshl.s8 d16, d16, d17 0x51,0xef,0xb0,0x04 = vqshl.s16 d16, d16, d17 0x61,0xef,0xb0,0x04 = vqshl.s32 d16, d16, d17 0x71,0xef,0xb0,0x04 = vqshl.s64 d16, d16, d17 0x41,0xff,0xb0,0x04 = vqshl.u8 d16, d16, d17 0x51,0xff,0xb0,0x04 = vqshl.u16 d16, d16, d17 0x61,0xff,0xb0,0x04 = vqshl.u32 d16, d16, d17 0x71,0xff,0xb0,0x04 = vqshl.u64 d16, d16, d17 0x42,0xef,0xf0,0x04 = vqshl.s8 q8, q8, q9 0x52,0xef,0xf0,0x04 = vqshl.s16 q8, q8, q9 0x62,0xef,0xf0,0x04 = vqshl.s32 q8, q8, q9 0x72,0xef,0xf0,0x04 = vqshl.s64 q8, q8, q9 0x42,0xff,0xf0,0x04 = vqshl.u8 q8, q8, q9 0x52,0xff,0xf0,0x04 = vqshl.u16 q8, q8, q9 0x62,0xff,0xf0,0x04 = vqshl.u32 q8, q8, q9 0x72,0xff,0xf0,0x04 = vqshl.u64 q8, q8, q9 0xcf,0xef,0x30,0x07 = vqshl.s8 d16, d16, #7 0xdf,0xef,0x30,0x07 = vqshl.s16 d16, d16, #15 0xff,0xef,0x30,0x07 = vqshl.s32 d16, d16, #31 0xff,0xef,0xb0,0x07 = vqshl.s64 d16, d16, #63 0xcf,0xff,0x30,0x07 = vqshl.u8 d16, d16, #7 0xdf,0xff,0x30,0x07 = vqshl.u16 d16, d16, #15 0xff,0xff,0x30,0x07 = vqshl.u32 d16, d16, #31 0xff,0xff,0xb0,0x07 = vqshl.u64 d16, d16, #63 0xcf,0xff,0x30,0x06 = vqshlu.s8 d16, d16, #7 0xdf,0xff,0x30,0x06 = vqshlu.s16 d16, d16, #15 0xff,0xff,0x30,0x06 = vqshlu.s32 d16, d16, #31 0xff,0xff,0xb0,0x06 = vqshlu.s64 d16, d16, #63 0xcf,0xef,0x70,0x07 = vqshl.s8 q8, q8, #7 0xdf,0xef,0x70,0x07 = vqshl.s16 q8, q8, #15 0xff,0xef,0x70,0x07 = vqshl.s32 q8, q8, #31 0xff,0xef,0xf0,0x07 = vqshl.s64 q8, q8, #63 0xcf,0xff,0x70,0x07 = vqshl.u8 q8, q8, #7 0xdf,0xff,0x70,0x07 = vqshl.u16 q8, q8, #15 0xff,0xff,0x70,0x07 = vqshl.u32 q8, q8, #31 0xff,0xff,0xf0,0x07 = vqshl.u64 q8, q8, #63 0xcf,0xff,0x70,0x06 = vqshlu.s8 q8, q8, #7 0xdf,0xff,0x70,0x06 = vqshlu.s16 q8, q8, #15 0xff,0xff,0x70,0x06 = vqshlu.s32 q8, q8, #31 0xff,0xff,0xf0,0x06 = vqshlu.s64 q8, q8, #63 0x41,0xef,0xb0,0x05 = vqrshl.s8 d16, d16, d17 0x51,0xef,0xb0,0x05 = vqrshl.s16 d16, d16, d17 0x61,0xef,0xb0,0x05 = vqrshl.s32 d16, d16, d17 0x71,0xef,0xb0,0x05 = vqrshl.s64 d16, d16, d17 0x41,0xff,0xb0,0x05 = vqrshl.u8 d16, d16, d17 0x51,0xff,0xb0,0x05 = vqrshl.u16 d16, d16, d17 0x61,0xff,0xb0,0x05 = vqrshl.u32 d16, d16, d17 0x71,0xff,0xb0,0x05 = vqrshl.u64 d16, d16, d17 0x42,0xef,0xf0,0x05 = vqrshl.s8 q8, q8, q9 0x52,0xef,0xf0,0x05 = vqrshl.s16 q8, q8, q9 0x62,0xef,0xf0,0x05 = vqrshl.s32 q8, q8, q9 0x72,0xef,0xf0,0x05 = vqrshl.s64 q8, q8, q9 0x42,0xff,0xf0,0x05 = vqrshl.u8 q8, q8, q9 0x52,0xff,0xf0,0x05 = vqrshl.u16 q8, q8, q9 0x62,0xff,0xf0,0x05 = vqrshl.u32 q8, q8, q9 0x72,0xff,0xf0,0x05 = vqrshl.u64 q8, q8, q9 0xc8,0xef,0x30,0x09 = vqshrn.s16 d16, q8, #8 0xd0,0xef,0x30,0x09 = vqshrn.s32 d16, q8, #16 0xe0,0xef,0x30,0x09 = vqshrn.s64 d16, q8, #32 0xc8,0xff,0x30,0x09 = vqshrn.u16 d16, q8, #8 0xd0,0xff,0x30,0x09 = vqshrn.u32 d16, q8, #16 0xe0,0xff,0x30,0x09 = vqshrn.u64 d16, q8, #32 0xc8,0xff,0x30,0x08 = vqshrun.s16 d16, q8, #8 0xd0,0xff,0x30,0x08 = vqshrun.s32 d16, q8, #16 0xe0,0xff,0x30,0x08 = vqshrun.s64 d16, q8, #32 0xc8,0xef,0x70,0x09 = vqrshrn.s16 d16, q8, #8 0xd0,0xef,0x70,0x09 = vqrshrn.s32 d16, q8, #16 0xe0,0xef,0x70,0x09 = vqrshrn.s64 d16, q8, #32 0xc8,0xff,0x70,0x09 = vqrshrn.u16 d16, q8, #8 0xd0,0xff,0x70,0x09 = vqrshrn.u32 d16, q8, #16 0xe0,0xff,0x70,0x09 = vqrshrn.u64 d16, q8, #32 0xc8,0xff,0x70,0x08 = vqrshrun.s16 d16, q8, #8 0xd0,0xff,0x70,0x08 = vqrshrun.s32 d16, q8, #16 0xe0,0xff,0x70,0x08 = vqrshrun.s64 d16, q8, #32 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-shift-encoding.s.cs000064400000000000000000000066730072674642500231620ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x40,0xff,0xa1,0x04 = vshl.u8 d16, d17, d16 0x50,0xff,0xa1,0x04 = vshl.u16 d16, d17, d16 0x60,0xff,0xa1,0x04 = vshl.u32 d16, d17, d16 0x70,0xff,0xa1,0x04 = vshl.u64 d16, d17, d16 0xcf,0xef,0x30,0x05 = vshl.i8 d16, d16, #7 0xdf,0xef,0x30,0x05 = vshl.i16 d16, d16, #15 0xff,0xef,0x30,0x05 = vshl.i32 d16, d16, #31 0xff,0xef,0xb0,0x05 = vshl.i64 d16, d16, #63 0x40,0xff,0xe2,0x04 = vshl.u8 q8, q9, q8 0x50,0xff,0xe2,0x04 = vshl.u16 q8, q9, q8 0x60,0xff,0xe2,0x04 = vshl.u32 q8, q9, q8 0x70,0xff,0xe2,0x04 = vshl.u64 q8, q9, q8 0xcf,0xef,0x70,0x05 = vshl.i8 q8, q8, #7 0xdf,0xef,0x70,0x05 = vshl.i16 q8, q8, #15 0xff,0xef,0x70,0x05 = vshl.i32 q8, q8, #31 0xff,0xef,0xf0,0x05 = vshl.i64 q8, q8, #63 0xc8,0xff,0x30,0x00 = vshr.u8 d16, d16, #8 0xd0,0xff,0x30,0x00 = vshr.u16 d16, d16, #16 0xe0,0xff,0x30,0x00 = vshr.u32 d16, d16, #32 0xc0,0xff,0xb0,0x00 = vshr.u64 d16, d16, #64 0xc8,0xff,0x70,0x00 = vshr.u8 q8, q8, #8 0xd0,0xff,0x70,0x00 = vshr.u16 q8, q8, #16 0xe0,0xff,0x70,0x00 = vshr.u32 q8, q8, #32 0xc0,0xff,0xf0,0x00 = vshr.u64 q8, q8, #64 0xc8,0xef,0x30,0x00 = vshr.s8 d16, d16, #8 0xd0,0xef,0x30,0x00 = vshr.s16 d16, d16, #16 0xe0,0xef,0x30,0x00 = vshr.s32 d16, d16, #32 0xc0,0xef,0xb0,0x00 = vshr.s64 d16, d16, #64 0xc8,0xef,0x70,0x00 = vshr.s8 q8, q8, #8 0xd0,0xef,0x70,0x00 = vshr.s16 q8, q8, #16 0xe0,0xef,0x70,0x00 = vshr.s32 q8, q8, #32 0xc0,0xef,0xf0,0x00 = vshr.s64 q8, q8, #64 0xcf,0xef,0x30,0x0a = vshll.s8 q8, d16, #7 0xdf,0xef,0x30,0x0a = vshll.s16 q8, d16, #15 0xff,0xef,0x30,0x0a = vshll.s32 q8, d16, #31 0xcf,0xff,0x30,0x0a = vshll.u8 q8, d16, #7 0xdf,0xff,0x30,0x0a = vshll.u16 q8, d16, #15 0xff,0xff,0x30,0x0a = vshll.u32 q8, d16, #31 0xf2,0xff,0x20,0x03 = vshll.i8 q8, d16, #8 0xf6,0xff,0x20,0x03 = vshll.i16 q8, d16, #16 0xfa,0xff,0x20,0x03 = vshll.i32 q8, d16, #32 0xc8,0xef,0x30,0x08 = vshrn.i16 d16, q8, #8 0xd0,0xef,0x30,0x08 = vshrn.i32 d16, q8, #16 0xe0,0xef,0x30,0x08 = vshrn.i64 d16, q8, #32 0x40,0xef,0xa1,0x05 = vrshl.s8 d16, d17, d16 0x50,0xef,0xa1,0x05 = vrshl.s16 d16, d17, d16 0x60,0xef,0xa1,0x05 = vrshl.s32 d16, d17, d16 0x70,0xef,0xa1,0x05 = vrshl.s64 d16, d17, d16 0x40,0xff,0xa1,0x05 = vrshl.u8 d16, d17, d16 0x50,0xff,0xa1,0x05 = vrshl.u16 d16, d17, d16 0x60,0xff,0xa1,0x05 = vrshl.u32 d16, d17, d16 0x70,0xff,0xa1,0x05 = vrshl.u64 d16, d17, d16 0x40,0xef,0xe2,0x05 = vrshl.s8 q8, q9, q8 0x50,0xef,0xe2,0x05 = vrshl.s16 q8, q9, q8 0x60,0xef,0xe2,0x05 = vrshl.s32 q8, q9, q8 0x70,0xef,0xe2,0x05 = vrshl.s64 q8, q9, q8 0x40,0xff,0xe2,0x05 = vrshl.u8 q8, q9, q8 0x50,0xff,0xe2,0x05 = vrshl.u16 q8, q9, q8 0x60,0xff,0xe2,0x05 = vrshl.u32 q8, q9, q8 0x70,0xff,0xe2,0x05 = vrshl.u64 q8, q9, q8 0xc8,0xef,0x30,0x02 = vrshr.s8 d16, d16, #8 0xd0,0xef,0x30,0x02 = vrshr.s16 d16, d16, #16 0xe0,0xef,0x30,0x02 = vrshr.s32 d16, d16, #32 0xc0,0xef,0xb0,0x02 = vrshr.s64 d16, d16, #64 0xc8,0xff,0x30,0x02 = vrshr.u8 d16, d16, #8 0xd0,0xff,0x30,0x02 = vrshr.u16 d16, d16, #16 0xe0,0xff,0x30,0x02 = vrshr.u32 d16, d16, #32 0xc0,0xff,0xb0,0x02 = vrshr.u64 d16, d16, #64 0xc8,0xef,0x70,0x02 = vrshr.s8 q8, q8, #8 0xd0,0xef,0x70,0x02 = vrshr.s16 q8, q8, #16 0xe0,0xef,0x70,0x02 = vrshr.s32 q8, q8, #32 0xc0,0xef,0xf0,0x02 = vrshr.s64 q8, q8, #64 0xc8,0xff,0x70,0x02 = vrshr.u8 q8, q8, #8 0xd0,0xff,0x70,0x02 = vrshr.u16 q8, q8, #16 0xe0,0xff,0x70,0x02 = vrshr.u32 q8, q8, #32 0xc0,0xff,0xf0,0x02 = vrshr.u64 q8, q8, #64 0xc8,0xef,0x70,0x08 = vrshrn.i16 d16, q8, #8 0xd0,0xef,0x70,0x08 = vrshrn.i32 d16, q8, #16 0xe0,0xef,0x70,0x08 = vrshrn.i64 d16, q8, #32 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs000064400000000000000000000101560072674642500241620ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xc8,0xef,0x30,0x11 = vsra.s8 d17, d16, #8 0x90,0xef,0x1e,0xf1 = vsra.s16 d15, d14, #16 0xa0,0xef,0x1c,0xd1 = vsra.s32 d13, d12, #32 0x80,0xef,0x9a,0xb1 = vsra.s64 d11, d10, #64 0x88,0xef,0x54,0xe1 = vsra.s8 q7, q2, #8 0x90,0xef,0x5c,0x61 = vsra.s16 q3, q6, #16 0xe0,0xef,0x5a,0x21 = vsra.s32 q9, q5, #32 0xc0,0xef,0xd8,0x01 = vsra.s64 q8, q4, #64 0xc8,0xff,0x30,0x11 = vsra.u8 d17, d16, #8 0x95,0xff,0x1e,0xb1 = vsra.u16 d11, d14, #11 0xaa,0xff,0x1f,0xc1 = vsra.u32 d12, d15, #22 0x8a,0xff,0xb0,0xd1 = vsra.u64 d13, d16, #54 0x88,0xff,0x5e,0x21 = vsra.u8 q1, q7, #8 0x9a,0xff,0x5e,0x41 = vsra.u16 q2, q7, #6 0xab,0xff,0x5c,0x61 = vsra.u32 q3, q6, #21 0xa7,0xff,0xda,0x81 = vsra.u64 q4, q5, #25 0xc8,0xef,0x30,0x01 = vsra.s8 d16, d16, #8 0x90,0xef,0x1e,0xe1 = vsra.s16 d14, d14, #16 0xa0,0xef,0x1c,0xc1 = vsra.s32 d12, d12, #32 0x80,0xef,0x9a,0xa1 = vsra.s64 d10, d10, #64 0x88,0xef,0x54,0x41 = vsra.s8 q2, q2, #8 0x90,0xef,0x5c,0xc1 = vsra.s16 q6, q6, #16 0xa0,0xef,0x5a,0xa1 = vsra.s32 q5, q5, #32 0x80,0xef,0xd8,0x81 = vsra.s64 q4, q4, #64 0xc8,0xff,0x30,0x01 = vsra.u8 d16, d16, #8 0x95,0xff,0x1e,0xe1 = vsra.u16 d14, d14, #11 0xaa,0xff,0x1f,0xf1 = vsra.u32 d15, d15, #22 0xca,0xff,0xb0,0x01 = vsra.u64 d16, d16, #54 0x88,0xff,0x5e,0xe1 = vsra.u8 q7, q7, #8 0x9a,0xff,0x5e,0xe1 = vsra.u16 q7, q7, #6 0xab,0xff,0x5c,0xc1 = vsra.u32 q6, q6, #21 0xa7,0xff,0xda,0xa1 = vsra.u64 q5, q5, #25 0x88,0xef,0x3a,0x53 = vrsra.s8 d5, d26, #8 0x90,0xef,0x39,0x63 = vrsra.s16 d6, d25, #16 0xa0,0xef,0x38,0x73 = vrsra.s32 d7, d24, #32 0x80,0xef,0xb7,0xe3 = vrsra.s64 d14, d23, #64 0x88,0xff,0x36,0xf3 = vrsra.u8 d15, d22, #8 0xd0,0xff,0x35,0x03 = vrsra.u16 d16, d21, #16 0xe0,0xff,0x34,0x13 = vrsra.u32 d17, d20, #32 0xc0,0xff,0xb3,0x23 = vrsra.u64 d18, d19, #64 0x88,0xef,0x54,0x23 = vrsra.s8 q1, q2, #8 0x90,0xef,0x56,0x43 = vrsra.s16 q2, q3, #16 0xa0,0xef,0x58,0x63 = vrsra.s32 q3, q4, #32 0x80,0xef,0xda,0x83 = vrsra.s64 q4, q5, #64 0x88,0xff,0x5c,0xa3 = vrsra.u8 q5, q6, #8 0x90,0xff,0x5e,0xc3 = vrsra.u16 q6, q7, #16 0xa0,0xff,0x70,0xe3 = vrsra.u32 q7, q8, #32 0xc0,0xff,0xf2,0x03 = vrsra.u64 q8, q9, #64 0xc8,0xef,0x3a,0xa3 = vrsra.s8 d26, d26, #8 0xd0,0xef,0x39,0x93 = vrsra.s16 d25, d25, #16 0xe0,0xef,0x38,0x83 = vrsra.s32 d24, d24, #32 0xc0,0xef,0xb7,0x73 = vrsra.s64 d23, d23, #64 0xc8,0xff,0x36,0x63 = vrsra.u8 d22, d22, #8 0xd0,0xff,0x35,0x53 = vrsra.u16 d21, d21, #16 0xe0,0xff,0x34,0x43 = vrsra.u32 d20, d20, #32 0xc0,0xff,0xb3,0x33 = vrsra.u64 d19, d19, #64 0x88,0xef,0x54,0x43 = vrsra.s8 q2, q2, #8 0x90,0xef,0x56,0x63 = vrsra.s16 q3, q3, #16 0xa0,0xef,0x58,0x83 = vrsra.s32 q4, q4, #32 0x80,0xef,0xda,0xa3 = vrsra.s64 q5, q5, #64 0x88,0xff,0x5c,0xc3 = vrsra.u8 q6, q6, #8 0x90,0xff,0x5e,0xe3 = vrsra.u16 q7, q7, #16 0xe0,0xff,0x70,0x03 = vrsra.u32 q8, q8, #32 0xc0,0xff,0xf2,0x23 = vrsra.u64 q9, q9, #64 0x8f,0xff,0x1c,0xb5 = vsli.8 d11, d12, #7 0x9f,0xff,0x1d,0xc5 = vsli.16 d12, d13, #15 0xbf,0xff,0x1e,0xd5 = vsli.32 d13, d14, #31 0xbf,0xff,0x9f,0xe5 = vsli.64 d14, d15, #63 0x8f,0xff,0x70,0x25 = vsli.8 q1, q8, #7 0x9f,0xff,0x5e,0x45 = vsli.16 q2, q7, #15 0xbf,0xff,0x58,0x65 = vsli.32 q3, q4, #31 0xbf,0xff,0xda,0x85 = vsli.64 q4, q5, #63 0xc8,0xff,0x1b,0xc4 = vsri.8 d28, d11, #8 0xd0,0xff,0x1c,0xa4 = vsri.16 d26, d12, #16 0xe0,0xff,0x1d,0x84 = vsri.32 d24, d13, #32 0xc0,0xff,0x9e,0x54 = vsri.64 d21, d14, #64 0x88,0xff,0x70,0x24 = vsri.8 q1, q8, #8 0x90,0xff,0x54,0xa4 = vsri.16 q5, q2, #16 0xa0,0xff,0x58,0xe4 = vsri.32 q7, q4, #32 0xc0,0xff,0xdc,0x24 = vsri.64 q9, q6, #64 0x8f,0xff,0x1c,0xc5 = vsli.8 d12, d12, #7 0x9f,0xff,0x1d,0xd5 = vsli.16 d13, d13, #15 0xbf,0xff,0x1e,0xe5 = vsli.32 d14, d14, #31 0xbf,0xff,0x9f,0xf5 = vsli.64 d15, d15, #63 0xcf,0xff,0x70,0x05 = vsli.8 q8, q8, #7 0x9f,0xff,0x5e,0xe5 = vsli.16 q7, q7, #15 0xbf,0xff,0x58,0x85 = vsli.32 q4, q4, #31 0xbf,0xff,0xda,0xa5 = vsli.64 q5, q5, #63 0x88,0xff,0x1b,0xb4 = vsri.8 d11, d11, #8 0x90,0xff,0x1c,0xc4 = vsri.16 d12, d12, #16 0xa0,0xff,0x1d,0xd4 = vsri.32 d13, d13, #32 0x80,0xff,0x9e,0xe4 = vsri.64 d14, d14, #64 0xc8,0xff,0x70,0x04 = vsri.8 q8, q8, #8 0x90,0xff,0x54,0x44 = vsri.16 q2, q2, #16 0xa0,0xff,0x58,0x84 = vsri.32 q4, q4, #32 0x80,0xff,0xdc,0xc4 = vsri.64 q6, q6, #64 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-shuffle-encoding.s.cs000064400000000000000000000016160072674642500234710ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-sub-encoding.s.cs000064400000000000000000000016160072674642500226260ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf1,0xef,0xa0,0x03 = vext.8 d16, d17, d16, #3 0xf1,0xef,0xa0,0x05 = vext.8 d16, d17, d16, #5 0xf2,0xef,0xe0,0x03 = vext.8 q8, q9, q8, #3 0xf2,0xef,0xe0,0x07 = vext.8 q8, q9, q8, #7 0xf1,0xef,0xa0,0x06 = vext.16 d16, d17, d16, #3 0xf2,0xef,0xe0,0x0c = vext.32 q8, q9, q8, #3 0xf2,0xff,0xa0,0x10 = vtrn.8 d17, d16 0xf6,0xff,0xa0,0x10 = vtrn.16 d17, d16 0xfa,0xff,0xa0,0x10 = vtrn.32 d17, d16 0xf2,0xff,0xe0,0x20 = vtrn.8 q9, q8 0xf6,0xff,0xe0,0x20 = vtrn.16 q9, q8 0xfa,0xff,0xe0,0x20 = vtrn.32 q9, q8 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8 0xf2,0xff,0xa0,0x11 = vzip.8 d17, d16 0xf6,0xff,0xa0,0x11 = vzip.16 d17, d16 0xf2,0xff,0xe0,0x21 = vzip.8 q9, q8 0xf6,0xff,0xe0,0x21 = vzip.16 q9, q8 0xfa,0xff,0xe0,0x21 = vzip.32 q9, q8 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-table-encoding.s.cs000064400000000000000000000007070072674642500231240ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xf1,0xff,0xa0,0x08 = vtbl.8 d16, {d17}, d16 0xf0,0xff,0xa2,0x09 = vtbl.8 d16, {d16, d17}, d18 0xf0,0xff,0xa4,0x0a = vtbl.8 d16, {d16, d17, d18}, d20 0xf0,0xff,0xa4,0x0b = vtbl.8 d16, {d16, d17, d18, d19}, d20 0xf0,0xff,0xe1,0x28 = vtbx.8 d18, {d16}, d17 0xf0,0xff,0xe2,0x39 = vtbx.8 d19, {d16, d17}, d18 0xf0,0xff,0xe5,0x4a = vtbx.8 d20, {d16, d17, d18}, d21 0xf0,0xff,0xe5,0x4b = vtbx.8 d20, {d16, d17, d18, d19}, d21 capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-vld-encoding.s.cs000064400000000000000000000053750072674642500226300ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x60,0xf9,0x1f,0x07 = vld1.8 {d16}, [r0:64] 0x60,0xf9,0x4f,0x07 = vld1.16 {d16}, [r0] 0x60,0xf9,0x8f,0x07 = vld1.32 {d16}, [r0] 0x60,0xf9,0xcf,0x07 = vld1.64 {d16}, [r0] 0x60,0xf9,0x1f,0x0a = vld1.8 {d16, d17}, [r0:64] 0x60,0xf9,0x6f,0x0a = vld1.16 {d16, d17}, [r0:128] 0x60,0xf9,0x8f,0x0a = vld1.32 {d16, d17}, [r0] 0x60,0xf9,0xcf,0x0a = vld1.64 {d16, d17}, [r0] 0x60,0xf9,0x1f,0x08 = vld2.8 {d16, d17}, [r0:64] 0x60,0xf9,0x6f,0x08 = vld2.16 {d16, d17}, [r0:128] 0x60,0xf9,0x8f,0x08 = vld2.32 {d16, d17}, [r0] 0x60,0xf9,0x1f,0x03 = vld2.8 {d16, d17, d18, d19}, [r0:64] 0x60,0xf9,0x6f,0x03 = vld2.16 {d16, d17, d18, d19}, [r0:128] 0x60,0xf9,0xbf,0x03 = vld2.32 {d16, d17, d18, d19}, [r0:256] 0x60,0xf9,0x1f,0x04 = vld3.8 {d16, d17, d18}, [r0:64] 0x60,0xf9,0x4f,0x04 = vld3.16 {d16, d17, d18}, [r0] 0x60,0xf9,0x8f,0x04 = vld3.32 {d16, d17, d18}, [r0] 0x60,0xf9,0x1d,0x05 = vld3.8 {d16, d18, d20}, [r0:64]! 0x60,0xf9,0x1d,0x15 = vld3.8 {d17, d19, d21}, [r0:64]! 0x60,0xf9,0x4d,0x05 = vld3.16 {d16, d18, d20}, [r0]! 0x60,0xf9,0x4d,0x15 = vld3.16 {d17, d19, d21}, [r0]! 0x60,0xf9,0x8d,0x05 = vld3.32 {d16, d18, d20}, [r0]! 0x60,0xf9,0x8d,0x15 = vld3.32 {d17, d19, d21}, [r0]! 0x60,0xf9,0x1f,0x00 = vld4.8 {d16, d17, d18, d19}, [r0:64] 0x60,0xf9,0x6f,0x00 = vld4.16 {d16, d17, d18, d19}, [r0:128] 0x60,0xf9,0xbf,0x00 = vld4.32 {d16, d17, d18, d19}, [r0:256] 0x60,0xf9,0x3d,0x01 = vld4.8 {d16, d18, d20, d22}, [r0:256]! 0x60,0xf9,0x3d,0x11 = vld4.8 {d17, d19, d21, d23}, [r0:256]! 0x60,0xf9,0x4d,0x01 = vld4.16 {d16, d18, d20, d22}, [r0]! 0x60,0xf9,0x4d,0x11 = vld4.16 {d17, d19, d21, d23}, [r0]! 0x60,0xf9,0x8d,0x01 = vld4.32 {d16, d18, d20, d22}, [r0]! 0x60,0xf9,0x8d,0x11 = vld4.32 {d17, d19, d21, d23}, [r0]! 0xe0,0xf9,0x6f,0x00 = vld1.8 {d16[3]}, [r0] 0xe0,0xf9,0x9f,0x04 = vld1.16 {d16[2]}, [r0:16] 0xe0,0xf9,0xbf,0x08 = vld1.32 {d16[1]}, [r0:32] 0xe0,0xf9,0x3f,0x01 = vld2.8 {d16[1], d17[1]}, [r0:16] 0xe0,0xf9,0x5f,0x05 = vld2.16 {d16[1], d17[1]}, [r0:32] 0xe0,0xf9,0x8f,0x09 = vld2.32 {d16[1], d17[1]}, [r0] 0xe0,0xf9,0x6f,0x15 = vld2.16 {d17[1], d19[1]}, [r0] 0xe0,0xf9,0x5f,0x19 = vld2.32 {d17[0], d19[0]}, [r0:64] 0xe0,0xf9,0x2f,0x02 = vld3.8 {d16[1], d17[1], d18[1]}, [r0] 0xe0,0xf9,0x4f,0x06 = vld3.16 {d16[1], d17[1], d18[1]}, [r0] 0xe0,0xf9,0x8f,0x0a = vld3.32 {d16[1], d17[1], d18[1]}, [r0] 0xe0,0xf9,0x6f,0x06 = vld3.16 {d16[1], d18[1], d20[1]}, [r0] 0xe0,0xf9,0xcf,0x1a = vld3.32 {d17[1], d19[1], d21[1]}, [r0] 0xe0,0xf9,0x3f,0x03 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0xe0,0xf9,0x4f,0x07 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xe0,0xf9,0xaf,0x0b = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xe0,0xf9,0x7f,0x07 = vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] 0xe0,0xf9,0x4f,0x1b = vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] capstone-sys-0.15.0/capstone/suite/MC/ARM/neont2-vst-encoding.s.cs000064400000000000000000000051410072674642500226460ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x40,0xf9,0x1f,0x07 = vst1.8 {d16}, [r0:64] 0x40,0xf9,0x4f,0x07 = vst1.16 {d16}, [r0] 0x40,0xf9,0x8f,0x07 = vst1.32 {d16}, [r0] 0x40,0xf9,0xcf,0x07 = vst1.64 {d16}, [r0] 0x40,0xf9,0x1f,0x0a = vst1.8 {d16, d17}, [r0:64] 0x40,0xf9,0x6f,0x0a = vst1.16 {d16, d17}, [r0:128] 0x40,0xf9,0x8f,0x0a = vst1.32 {d16, d17}, [r0] 0x40,0xf9,0xcf,0x0a = vst1.64 {d16, d17}, [r0] 0x40,0xf9,0x1f,0x08 = vst2.8 {d16, d17}, [r0:64] 0x40,0xf9,0x6f,0x08 = vst2.16 {d16, d17}, [r0:128] 0x40,0xf9,0x8f,0x08 = vst2.32 {d16, d17}, [r0] 0x40,0xf9,0x1f,0x03 = vst2.8 {d16, d17, d18, d19}, [r0:64] 0x40,0xf9,0x6f,0x03 = vst2.16 {d16, d17, d18, d19}, [r0:128] 0x40,0xf9,0xbf,0x03 = vst2.32 {d16, d17, d18, d19}, [r0:256] 0x40,0xf9,0x1f,0x04 = vst3.8 {d16, d17, d18}, [r0:64] 0x40,0xf9,0x4f,0x04 = vst3.16 {d16, d17, d18}, [r0] 0x40,0xf9,0x8f,0x04 = vst3.32 {d16, d17, d18}, [r0] 0x40,0xf9,0x1d,0x05 = vst3.8 {d16, d18, d20}, [r0:64]! 0x40,0xf9,0x1d,0x15 = vst3.8 {d17, d19, d21}, [r0:64]! 0x40,0xf9,0x4d,0x05 = vst3.16 {d16, d18, d20}, [r0]! 0x40,0xf9,0x4d,0x15 = vst3.16 {d17, d19, d21}, [r0]! 0x40,0xf9,0x8d,0x05 = vst3.32 {d16, d18, d20}, [r0]! 0x40,0xf9,0x8d,0x15 = vst3.32 {d17, d19, d21}, [r0]! 0x40,0xf9,0x1f,0x00 = vst4.8 {d16, d17, d18, d19}, [r0:64] 0x40,0xf9,0x6f,0x00 = vst4.16 {d16, d17, d18, d19}, [r0:128] 0x40,0xf9,0x3d,0x01 = vst4.8 {d16, d18, d20, d22}, [r0:256]! 0x40,0xf9,0x3d,0x11 = vst4.8 {d17, d19, d21, d23}, [r0:256]! 0x40,0xf9,0x4d,0x01 = vst4.16 {d16, d18, d20, d22}, [r0]! 0x40,0xf9,0x4d,0x11 = vst4.16 {d17, d19, d21, d23}, [r0]! 0x40,0xf9,0x8d,0x01 = vst4.32 {d16, d18, d20, d22}, [r0]! 0x40,0xf9,0x8d,0x11 = vst4.32 {d17, d19, d21, d23}, [r0]! 0xc0,0xf9,0x3f,0x01 = vst2.8 {d16[1], d17[1]}, [r0:16] 0xc0,0xf9,0x5f,0x05 = vst2.16 {d16[1], d17[1]}, [r0:32] 0xc0,0xf9,0x8f,0x09 = vst2.32 {d16[1], d17[1]}, [r0] 0xc0,0xf9,0x6f,0x15 = vst2.16 {d17[1], d19[1]}, [r0] 0xc0,0xf9,0x5f,0x19 = vst2.32 {d17[0], d19[0]}, [r0:64] 0xc0,0xf9,0x2f,0x02 = vst3.8 {d16[1], d17[1], d18[1]}, [r0] 0xc0,0xf9,0x4f,0x06 = vst3.16 {d16[1], d17[1], d18[1]}, [r0] 0xc0,0xf9,0x8f,0x0a = vst3.32 {d16[1], d17[1], d18[1]}, [r0] 0xc0,0xf9,0xaf,0x16 = vst3.16 {d17[2], d19[2], d21[2]}, [r0] 0xc0,0xf9,0x4f,0x0a = vst3.32 {d16[0], d18[0], d20[0]}, [r0] 0xc0,0xf9,0x3f,0x03 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] 0xc0,0xf9,0x4f,0x07 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] 0xc0,0xf9,0xaf,0x0b = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] 0xc0,0xf9,0xff,0x17 = vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] 0xc0,0xf9,0x4f,0x1b = vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] 0x04,0xf9,0x0f,0x89 = vst2.8 {d8, d10}, [r4] capstone-sys-0.15.0/capstone/suite/MC/ARM/simple-fp-encoding.s.cs000064400000000000000000000115320072674642500225240ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x80,0x0a,0x30,0xee = vadd.f32 s0, s1, s0 0xc0,0x0a,0x30,0xee = vsub.f32 s0, s1, s0 0x80,0x0a,0x80,0xee = vdiv.f32 s0, s1, s0 0xa3,0x2a,0xc2,0xee = vdiv.f32 s5, s5, s7 0x80,0x0a,0x20,0xee = vmul.f32 s0, s1, s0 0xaa,0x5a,0x65,0xee = vmul.f32 s11, s11, s21 0xc0,0x0a,0x20,0xee = vnmul.f32 s0, s1, s0 0xc0,0x0a,0xf4,0xee = vcmpe.f32 s1, s0 0xc0,0x0a,0xb5,0xee = vcmpe.f32 s0, #0 0xc0,0x0a,0xb0,0xee = vabs.f32 s0, s0 0x40,0x0a,0xb1,0xee = vneg.f32 s0, s0 0xc0,0x0a,0xb1,0xee = vsqrt.f32 s0, s0 0xc0,0x0a,0xb8,0xee = vcvt.f32.s32 s0, s0 0x40,0x0a,0xb8,0xee = vcvt.f32.u32 s0, s0 0xc0,0x0a,0xbd,0xee = vcvt.s32.f32 s0, s0 0xc0,0x0a,0xbc,0xee = vcvt.u32.f32 s0, s0 0x00,0x0a,0x41,0xee = vmla.f32 s1, s2, s0 0x40,0x0a,0x41,0xee = vmls.f32 s1, s2, s0 0x40,0x0a,0x51,0xee = vnmla.f32 s1, s2, s0 0x00,0x0a,0x51,0xee = vnmls.f32 s1, s2, s0 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr 0x10,0x2a,0xf0,0xee = vmrs r2, fpsid 0x10,0x3a,0xf0,0xee = vmrs r3, fpsid 0x10,0x4a,0xf7,0xee = vmrs r4, mvfr0 0x10,0x5a,0xf6,0xee = vmrs r5, mvfr1 0x10,0x0a,0x00,0x1e = vmovne s0, r0 0x10,0x1a,0x00,0x0e = vmoveq s0, r1 0x10,0x1a,0x11,0xee = vmov r1, s2 0x10,0x3a,0x02,0xee = vmov s4, r3 0x12,0x1b,0x55,0xec = vmov r1, r5, d2 0x14,0x3b,0x49,0xec = vmov d4, r3, r9 0x10,0x0a,0xf1,0xee = vmrs r0, fpscr 0x10,0x0a,0xf8,0xee = vmrs r0, fpexc 0x10,0x0a,0xf0,0xee = vmrs r0, fpsid 0x10,0x1a,0xf9,0xee = vmrs r1, fpinst 0x10,0x8a,0xfa,0xee = vmrs r8, fpinst2 0x10,0x0a,0xe1,0xee = vmsr fpscr, r0 0x10,0x0a,0xe8,0xee = vmsr fpexc, r0 0x10,0x0a,0xe0,0xee = vmsr fpsid, r0 0x10,0x3a,0xe9,0xee = vmsr fpinst, r3 0x10,0x4a,0xea,0xee = vmsr fpinst2, r4 0x08,0x0a,0xb0,0xee = vmov.f32 s0, #3.000000e+00 0x08,0x0a,0xb8,0xee = vmov.f32 s0, #-3.000000e+00 0x10,0x0a,0x00,0xee = vmov s0, r0 0x90,0x1a,0x00,0xee = vmov s1, r1 0x10,0x2a,0x01,0xee = vmov s2, r2 0x90,0x3a,0x01,0xee = vmov s3, r3 0x10,0x0a,0x10,0xee = vmov r0, s0 0x90,0x1a,0x10,0xee = vmov r1, s1 0x10,0x2a,0x11,0xee = vmov r2, s2 0x90,0x3a,0x11,0xee = vmov r3, s3 0x30,0x0b,0x51,0xec = vmov r0, r1, d16 0x31,0x1a,0x42,0xec = vmov s3, s4, r1, r2 0x11,0x1a,0x42,0xec = vmov s2, s3, r1, r2 0x31,0x1a,0x52,0xec = vmov r1, r2, s3, s4 0x11,0x1a,0x52,0xec = vmov r1, r2, s2, s3 0x1f,0x1b,0x42,0xec = vmov d15, r1, r2 0x30,0x1b,0x42,0xec = vmov d16, r1, r2 0x1f,0x1b,0x52,0xec = vmov r1, r2, d15 0x30,0x1b,0x52,0xec = vmov r1, r2, d16 0x00,0x1b,0xd0,0xed = vldr d17, [r0] 0x00,0x0a,0x9e,0xed = vldr s0, [lr] 0x00,0x0b,0x9e,0xed = vldr d0, [lr] 0x08,0x1b,0x92,0xed = vldr d1, [r2, #32] 0x08,0x1b,0x12,0xed = vldr d1, [r2, #-32] 0x00,0x2b,0x93,0xed = vldr d2, [r3] 0x00,0x3b,0x9f,0xed = vldr d3, [pc] 0x00,0x3b,0x9f,0xed = vldr d3, [pc] 0x00,0x3b,0x1f,0xed = vldr d3, [pc, #-0] 0x00,0x6a,0xd0,0xed = vldr s13, [r0] 0x08,0x0a,0xd2,0xed = vldr s1, [r2, #32] 0x08,0x0a,0x52,0xed = vldr s1, [r2, #-32] 0x00,0x1a,0x93,0xed = vldr s2, [r3] 0x00,0x2a,0xdf,0xed = vldr s5, [pc] 0x00,0x2a,0xdf,0xed = vldr s5, [pc] 0x00,0x2a,0x5f,0xed = vldr s5, [pc, #-0] 0x00,0x4b,0x81,0xed = vstr d4, [r1] 0x06,0x4b,0x81,0xed = vstr d4, [r1, #24] 0x06,0x4b,0x01,0xed = vstr d4, [r1, #-24] 0x00,0x0a,0x8e,0xed = vstr s0, [lr] 0x00,0x0b,0x8e,0xed = vstr d0, [lr] 0x00,0x2a,0x81,0xed = vstr s4, [r1] 0x06,0x2a,0x81,0xed = vstr s4, [r1, #24] 0x06,0x2a,0x01,0xed = vstr s4, [r1, #-24] 0x0c,0x2b,0x91,0xec = vldmia r1, {d2, d3, d4, d5, d6, d7} 0x06,0x1a,0x91,0xec = vldmia r1, {s2, s3, s4, s5, s6, s7} 0x0c,0x2b,0x81,0xec = vstmia r1, {d2, d3, d4, d5, d6, d7} 0x06,0x1a,0x81,0xec = vstmia r1, {s2, s3, s4, s5, s6, s7} 0x10,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12, d13, d14, d15} 0x07,0x0b,0xb5,0xec = fldmiax r5!, {d0, d1, d2} 0x05,0x4b,0x90,0x0c = fldmiaxeq r0, {d4, d5} 0x07,0x4b,0x35,0x1d = fldmdbxne r5!, {d4, d5, d6} 0x11,0x0b,0xa5,0xec = fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7} 0x05,0x8b,0x84,0x0c = fstmiaxeq r4, {d8, d9} 0x07,0x2b,0x27,0x1d = fstmdbxne r7!, {d2, d3, d4} 0x60,0x0a,0xbd,0xee = vcvtr.s32.f32 s0, s1 0x60,0x0a,0xbc,0xee = vcvtr.u32.f32 s0, s1 0x90,0x8a,0x00,0xee = vmov s1, r8 0x10,0x4a,0x01,0xee = vmov s2, r4 0x90,0x6a,0x01,0xee = vmov s3, r6 0x10,0x1a,0x02,0xee = vmov s4, r1 0x90,0x2a,0x02,0xee = vmov s5, r2 0x10,0x3a,0x03,0xee = vmov s6, r3 0x10,0x1a,0x14,0xee = vmov r1, s8 0x10,0x2a,0x12,0xee = vmov r2, s4 0x10,0x3a,0x13,0xee = vmov r3, s6 0x90,0x4a,0x10,0xee = vmov r4, s1 0x10,0x5a,0x11,0xee = vmov r5, s2 0x90,0x6a,0x11,0xee = vmov r6, s3 0xc6,0x0a,0xbb,0xee = vcvt.f32.u32 s0, s0, #20 0x67,0x0a,0xbb,0xee = vcvt.f32.u16 s0, s0, #1 0xc6,0x0a,0xfa,0xee = vcvt.f32.s32 s1, s1, #20 0x67,0x8a,0xfa,0xee = vcvt.f32.s16 s17, s17, #1 0xc6,0x6a,0xbf,0xee = vcvt.u32.f32 s12, s12, #20 0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1 0xc6,0x0a,0xfe,0xee = vcvt.s32.f32 s1, s1, #20 0x67,0x8a,0xfe,0xee = vcvt.s16.f32 s17, s17, #1 0x10,0x40,0x80,0xf2 = vmov.i32 d4, #0x0 0x12,0x46,0x84,0xf2 = vmov.i32 d4, #0x42000000 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb-fp-armv8.s.cs000064400000000000000000000043170072674642500216240ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None // 0xb2,0xee,0xe0,0x3b = vcvtt.f64.f16 d3, s1 // 0xf3,0xee,0xcc,0x2b = vcvtt.f16.f64 s5, d12 // 0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1 // 0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1 // 0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1 // 0xf3,0xee,0xcc,0x2b = vcvttgt.f16.f64 s5, d12 // 0xb2,0xee,0x60,0x3b = vcvtbeq.f64.f16 d3, s1 // 0xb3,0xee,0x41,0x2b = vcvtblt.f16.f64 s4, d1 0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3 0xbc,0xfe,0xc3,0x1b = vcvta.s32.f64 s2, d3 0xbd,0xfe,0xeb,0x3a = vcvtn.s32.f32 s6, s23 0xbd,0xfe,0xe7,0x3b = vcvtn.s32.f64 s6, d23 0xbe,0xfe,0xc2,0x0a = vcvtp.s32.f32 s0, s4 0xbe,0xfe,0xc4,0x0b = vcvtp.s32.f64 s0, d4 0xff,0xfe,0xc4,0x8a = vcvtm.s32.f32 s17, s8 0xff,0xfe,0xc8,0x8b = vcvtm.s32.f64 s17, d8 0xbc,0xfe,0x61,0x1a = vcvta.u32.f32 s2, s3 0xbc,0xfe,0x43,0x1b = vcvta.u32.f64 s2, d3 0xbd,0xfe,0x6b,0x3a = vcvtn.u32.f32 s6, s23 0xbd,0xfe,0x67,0x3b = vcvtn.u32.f64 s6, d23 0xbe,0xfe,0x42,0x0a = vcvtp.u32.f32 s0, s4 0xbe,0xfe,0x44,0x0b = vcvtp.u32.f64 s0, d4 0xff,0xfe,0x44,0x8a = vcvtm.u32.f32 s17, s8 0xff,0xfe,0x48,0x8b = vcvtm.u32.f64 s17, d8 0x20,0xfe,0xab,0x2a = vselge.f32 s4, s1, s23 0x6f,0xfe,0xa7,0xeb = vselge.f64 d30, d31, d23 0x30,0xfe,0x80,0x0a = vselgt.f32 s0, s1, s0 0x3a,0xfe,0x24,0x5b = vselgt.f64 d5, d10, d20 0x0e,0xfe,0x2b,0xfa = vseleq.f32 s30, s28, s23 0x04,0xfe,0x08,0x2b = vseleq.f64 d2, d4, d8 0x58,0xfe,0x07,0xaa = vselvs.f32 s21, s16, s14 0x11,0xfe,0x2f,0x0b = vselvs.f64 d0, d1, d31 0xc6,0xfe,0x00,0x2a = vmaxnm.f32 s5, s12, s0 0x86,0xfe,0xae,0x5b = vmaxnm.f64 d5, d22, d30 0x80,0xfe,0x46,0x0a = vminnm.f32 s0, s0, s12 0x86,0xfe,0x49,0x4b = vminnm.f64 d4, d6, d9 // 0xb6,0xee,0xcc,0x3b = vrintzge.f64 d3, d12 0xf6,0xee,0xcc,0x1a = vrintz.f32 s3, s24 // 0xb6,0xee,0x40,0x5b = vrintrlt.f64 d5, d0 0xb6,0xee,0x64,0x0a = vrintr.f32 s0, s9 // 0xf7,0xee,0x6e,0xcb = vrintxeq.f64 d28, d30 // 0xb7,0xee,0x47,0x5a = vrintxvs.f32 s10, s14 0xb8,0xfe,0x44,0x3b = vrinta.f64 d3, d4 0xb8,0xfe,0x60,0x6a = vrinta.f32 s12, s1 0xb9,0xfe,0x44,0x3b = vrintn.f64 d3, d4 0xb9,0xfe,0x60,0x6a = vrintn.f32 s12, s1 0xba,0xfe,0x44,0x3b = vrintp.f64 d3, d4 0xba,0xfe,0x60,0x6a = vrintp.f32 s12, s1 0xbb,0xfe,0x44,0x3b = vrintm.f64 d3, d4 0xbb,0xfe,0x60,0x6a = vrintm.f32 s12, s1 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb-hints.s.cs000064400000000000000000000004500072674642500213030ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x00,0xbf = nop 0x10,0xbf = yield 0x20,0xbf = wfe 0x30,0xbf = wfi 0x40,0xbf = sev 0xbf,0xf3,0x5f,0x8f = dmb sy 0xbf,0xf3,0x5f,0x8f = dmb sy 0xbf,0xf3,0x4f,0x8f = dsb sy 0xbf,0xf3,0x4f,0x8f = dsb sy 0xbf,0xf3,0x6f,0x8f = isb sy 0xbf,0xf3,0x6f,0x8f = isb sy capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb-neon-crypto.s.cs000064400000000000000000000012270072674642500224360ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 0xb0,0xff,0x42,0x03 = aesd.8 q0, q1 0xb0,0xff,0x02,0x03 = aese.8 q0, q1 0xb0,0xff,0xc2,0x03 = aesimc.8 q0, q1 0xb0,0xff,0x82,0x03 = aesmc.8 q0, q1 0xb9,0xff,0xc2,0x02 = sha1h.32 q0, q1 0xba,0xff,0x82,0x03 = sha1su1.32 q0, q1 0xba,0xff,0xc2,0x03 = sha256su0.32 q0, q1 0x02,0xef,0x44,0x0c = sha1c.32 q0, q1, q2 0x22,0xef,0x44,0x0c = sha1m.32 q0, q1, q2 0x12,0xef,0x44,0x0c = sha1p.32 q0, q1, q2 0x32,0xef,0x44,0x0c = sha1su0.32 q0, q1, q2 0x02,0xff,0x44,0x0c = sha256h.32 q0, q1, q2 0x12,0xff,0x44,0x0c = sha256h2.32 q0, q1, q2 0x22,0xff,0x44,0x0c = sha256su1.32 q0, q1, q2 0xe0,0xef,0xa1,0x0e = vmull.p64 q8, d16, d17 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb-neon-v8.s.cs000064400000000000000000000031120072674642500214460ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None 0x05,0xff,0x11,0x4f = vmaxnm.f32 d4, d5, d1 0x08,0xff,0x5c,0x4f = vmaxnm.f32 q2, q4, q6 0x24,0xff,0x3e,0x5f = vminnm.f32 d5, d4, d30 0x2a,0xff,0xd4,0x0f = vminnm.f32 q0, q13, q2 0xbb,0xff,0x06,0x40 = vcvta.s32.f32 d4, d6 0xbb,0xff,0x8a,0xc0 = vcvta.u32.f32 d12, d10 0xbb,0xff,0x4c,0x80 = vcvta.s32.f32 q4, q6 0xbb,0xff,0xe4,0x80 = vcvta.u32.f32 q4, q10 0xbb,0xff,0x2e,0x13 = vcvtm.s32.f32 d1, d30 0xbb,0xff,0x8a,0xc3 = vcvtm.u32.f32 d12, d10 0xbb,0xff,0x64,0x23 = vcvtm.s32.f32 q1, q10 0xfb,0xff,0xc2,0xa3 = vcvtm.u32.f32 q13, q1 0xbb,0xff,0x21,0xf1 = vcvtn.s32.f32 d15, d17 0xbb,0xff,0x83,0x51 = vcvtn.u32.f32 d5, d3 0xbb,0xff,0x60,0x61 = vcvtn.s32.f32 q3, q8 0xbb,0xff,0xc6,0xa1 = vcvtn.u32.f32 q5, q3 0xbb,0xff,0x25,0xb2 = vcvtp.s32.f32 d11, d21 0xbb,0xff,0xa7,0xe2 = vcvtp.u32.f32 d14, d23 0xbb,0xff,0x6e,0x82 = vcvtp.s32.f32 q4, q15 0xfb,0xff,0xe0,0x22 = vcvtp.u32.f32 q9, q8 0xba,0xff,0x00,0x34 = vrintn.f32 d3, d0 0xba,0xff,0x48,0x24 = vrintn.f32 q1, q4 0xba,0xff,0x8c,0x54 = vrintx.f32 d5, d12 0xba,0xff,0xc6,0x04 = vrintx.f32 q0, q3 0xba,0xff,0x00,0x35 = vrinta.f32 d3, d0 0xfa,0xff,0x44,0x05 = vrinta.f32 q8, q2 0xba,0xff,0xa2,0xc5 = vrintz.f32 d12, d18 0xfa,0xff,0xc8,0x25 = vrintz.f32 q9, q4 0xba,0xff,0x80,0x36 = vrintm.f32 d3, d0 0xba,0xff,0xc8,0x26 = vrintm.f32 q1, q4 0xba,0xff,0x80,0x37 = vrintp.f32 d3, d0 0xba,0xff,0xc8,0x27 = vrintp.f32 q1, q4 0xba,0xff,0x00,0x34 = vrintn.f32 d3, d0 0xba,0xff,0xc6,0x04 = vrintx.f32 q0, q3 0xba,0xff,0x00,0x35 = vrinta.f32 d3, d0 0xfa,0xff,0xc8,0x25 = vrintz.f32 q9, q4 0xba,0xff,0xc8,0x27 = vrintp.f32 q1, q4 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb-shift-encoding.s.cs000064400000000000000000000015350072674642500230640ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x6e,0xeb,0x00,0x0c = sbc.w ip, lr, r0 0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #32 0x67,0xeb,0x1f,0x42 = sbc.w r2, r7, pc, lsr #16 0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10 0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #16 0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #32 0x63,0xeb,0x2d,0x46 = sbc.w r6, r3, sp, asr #16 0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx 0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #16 0x0e,0xea,0x00,0x0c = and.w ip, lr, r0 0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #32 0x07,0xea,0x1f,0x42 = and.w r2, r7, pc, lsr #16 0x06,0xea,0x0a,0x03 = and.w r3, r6, r10 0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #16 0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #32 0x03,0xea,0x2d,0x46 = and.w r6, r3, sp, asr #16 0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx 0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #16 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb.s.cs000064400000000000000000000007050072674642500201630ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x91,0x42 = cmp r1, r2 0x16,0xbc = pop {r1, r2, r4} 0xfe,0xde = trap 0xc8,0x47 = blx r9 0xd0,0x47 = blx r10 0x1a,0xba = rev r2, r3 0x63,0xba = rev16 r3, r4 0xf5,0xba = revsh r5, r6 0x5a,0xb2 = sxtb r2, r3 0x1a,0xb2 = sxth r2, r3 0x2c,0x42 = tst r4, r5 0xf3,0xb2 = uxtb r3, r6 0xb3,0xb2 = uxth r3, r6 0x8b,0x58 = ldr r3, [r1, r2] 0x02,0xbe = bkpt #2 0xc0,0x46 = mov r8, r8 0x67,0xb6 = cpsie aif 0x78,0x46 = mov r0, pc capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs000064400000000000000000000001050072674642500227170ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x36,0xf0,0x06,0xbc = b.w #223248 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb2-branches.s.cs000064400000000000000000000045050072674642500220320ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None // 0xff,0xf7,0x00,0xbc = b.w #-2044 // 0x00,0xf0,0xff,0xbb = b.w #2050 // 0x66,0xf6,0x30,0xbc = b.w #-1677212 // 0x99,0xf1,0xcf,0xbb = b.w #1677218 // 0x00,0xe4 = b #-2044 0xff,0xe3 = b #2050 0xff,0xf7,0xff,0xbb = b.w #-2046 0x00,0xf0,0x00,0xbc = b.w #2052 // 0x66,0xf6,0x30,0xbc = b.w #-1677212 // 0x99,0xf1,0xcf,0xbb = b.w #1677218 0x08,0xbf = it eq // 0x00,0xe4 = beq #-2044 0x18,0xbf = it ne // 0x01,0xe4 = bne #-2042 0xc8,0xbf = it gt // 0xff,0xf7,0x00,0xbc = bgt.w #-2044 0xd8,0xbf = it le // 0x00,0xf0,0xff,0xbb = ble.w #2050 0xa8,0xbf = it ge // 0x66,0xf6,0x30,0xbc = bge.w #-1677212 0xb8,0xbf = it lt // 0x99,0xf1,0xcf,0xbb = blt.w #1677218 0x80,0xd0 = beq #-252 0x7f,0xd1 = bne #258 0x3f,0xf5,0x80,0xaf = bmi.w #-252 0x40,0xf0,0x7f,0x80 = bne.w #258 0xc0,0xf6,0x00,0x80 = blt.w #-1048572 0xbf,0xf2,0xff,0xaf = bge.w #1048578 0x80,0xd1 = bne #-252 0x7f,0xdc = bgt #258 0x7f,0xf4,0x7f,0xaf = bne.w #-254 0x00,0xf3,0x80,0x80 = bgt.w #260 0x40,0xf4,0x00,0x80 = bne.w #-1048572 0x3f,0xf3,0xff,0xaf = bgt.w #1048578 0x08,0xbf = it eq // 0x08,0x44 = addeq r0, r1 0x40,0xd1 = bne #132 0x0c,0xbf = ite eq // 0x08,0x44 = addeq r0, r1 // 0x40,0xe0 = bne #132 // 0x00,0xe4 = b #-2044 // 0xff,0xf7,0x00,0xbc = b.w #-2044 // 0x00,0xf0,0xff,0xbb = b.w #2050 // 0x66,0xf6,0x30,0xbc = b.w #-1677212 // 0x99,0xf1,0xcf,0xbb = b.w #1677218 // 0x00,0xe4 = b #-2044 0xff,0xe3 = b #2050 0xff,0xf7,0xff,0xbb = b.w #-2046 0x00,0xf0,0x00,0xbc = b.w #2052 // 0x66,0xf6,0x30,0xbc = b.w #-1677212 // 0x99,0xf1,0xcf,0xbb = b.w #1677218 0x08,0xbf = it eq // 0x00,0xe4 = beq #-2044 0x18,0xbf = it ne // 0x01,0xe4 = bne #-2042 0xc8,0xbf = it gt // 0xff,0xf7,0x00,0xbc = bgt.w #-2044 0xd8,0xbf = it le // 0x00,0xf0,0xff,0xbb = ble.w #2050 0xa8,0xbf = it ge // 0x66,0xf6,0x30,0xbc = bge.w #-1677212 0xb8,0xbf = it lt // 0x99,0xf1,0xcf,0xbb = blt.w #1677218 0x80,0xd0 = beq #-252 0x7f,0xd1 = bne #258 0x3f,0xf5,0x80,0xaf = bmi.w #-252 0x40,0xf0,0x7f,0x80 = bne.w #258 0xc0,0xf6,0x00,0x80 = blt.w #-1048572 0xbf,0xf2,0xff,0xaf = bge.w #1048578 0x80,0xd1 = bne #-252 0x7f,0xdc = bgt #258 0x7f,0xf4,0x7f,0xaf = bne.w #-254 0x00,0xf3,0x80,0x80 = bgt.w #260 0x40,0xf4,0x00,0x80 = bne.w #-1048572 0x3f,0xf3,0xff,0xaf = bgt.w #1048578 0x08,0xbf = it eq // 0x08,0x44 = addeq r0, r1 0x40,0xd1 = bne #132 0x0c,0xbf = ite eq // 0x08,0x44 = addeq r0, r1 // 0x40,0xe0 = b #132 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb2-mclass.s.cs000064400000000000000000000030300072674642500215170ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None 0xef,0xf3,0x00,0x80 = mrs r0, apsr 0xef,0xf3,0x01,0x80 = mrs r0, iapsr 0xef,0xf3,0x02,0x80 = mrs r0, eapsr 0xef,0xf3,0x03,0x80 = mrs r0, xpsr 0xef,0xf3,0x05,0x80 = mrs r0, ipsr 0xef,0xf3,0x06,0x80 = mrs r0, epsr 0xef,0xf3,0x07,0x80 = mrs r0, iepsr 0xef,0xf3,0x08,0x80 = mrs r0, msp 0xef,0xf3,0x09,0x80 = mrs r0, psp 0xef,0xf3,0x10,0x80 = mrs r0, primask 0xef,0xf3,0x11,0x80 = mrs r0, basepri 0xef,0xf3,0x12,0x80 = mrs r0, basepri_max 0xef,0xf3,0x13,0x80 = mrs r0, faultmask 0xef,0xf3,0x14,0x80 = mrs r0, control // 0x80,0xf3,0x00,0x88 = msr apsr, r0 // 0x80,0xf3,0x00,0x88 = msr apsr, r0 0x80,0xf3,0x00,0x84 = msr apsr_g, r0 0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0 // 0x80,0xf3,0x01,0x88 = msr iapsr, r0 // 0x80,0xf3,0x01,0x88 = msr iapsr, r0 0x80,0xf3,0x01,0x84 = msr iapsr_g, r0 0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0 // 0x80,0xf3,0x02,0x88 = msr eapsr, r0 // 0x80,0xf3,0x02,0x88 = msr eapsr, r0 0x80,0xf3,0x02,0x84 = msr eapsr_g, r0 0x80,0xf3,0x02,0x8c = msr eapsr_nzcvqg, r0 // 0x80,0xf3,0x03,0x88 = msr xpsr, r0 // 0x80,0xf3,0x03,0x88 = msr xpsr, r0 0x80,0xf3,0x03,0x84 = msr xpsr_g, r0 0x80,0xf3,0x03,0x8c = msr xpsr_nzcvqg, r0 0x80,0xf3,0x05,0x88 = msr ipsr, r0 0x80,0xf3,0x06,0x88 = msr epsr, r0 0x80,0xf3,0x07,0x88 = msr iepsr, r0 0x80,0xf3,0x08,0x88 = msr msp, r0 0x80,0xf3,0x09,0x88 = msr psp, r0 0x80,0xf3,0x10,0x88 = msr primask, r0 0x80,0xf3,0x11,0x88 = msr basepri, r0 0x80,0xf3,0x12,0x88 = msr basepri_max, r0 0x80,0xf3,0x13,0x88 = msr faultmask, r0 0x80,0xf3,0x14,0x88 = msr control, r0 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb2-narrow-dp.ll.cs000064400000000000000000000277260072674642500223350ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x12,0xea,0x01,0x00 = ands.w r0, r2, r1 0x0a,0x40 = ands r2, r1 0x0a,0x40 = ands r2, r1 0x10,0xea,0x01,0x00 = ands.w r0, r0, r1 0x11,0xea,0x03,0x03 = ands.w r3, r1, r3 0x01,0xea,0x00,0x00 = and.w r0, r1, r0 // 0x0f,0x40 = ands r7, r1 // 0x0f,0x40 = ands r7, r1 0x11,0xea,0x08,0x08 = ands.w r8, r1, r8 0x18,0xea,0x01,0x08 = ands.w r8, r8, r1 0x18,0xea,0x00,0x00 = ands.w r0, r8, r0 0x11,0xea,0x08,0x01 = ands.w r1, r1, r8 0x12,0xea,0x41,0x02 = ands.w r2, r2, r1, lsl #1 0x11,0xea,0x50,0x00 = ands.w r0, r1, r0, lsr #1 0x08,0xbf = it eq // 0x02,0xea,0x01,0x00 = andeq.w r0, r2, r1 0x08,0xbf = it eq // 0x0b,0x40 = andeq r3, r1 0x08,0xbf = it eq // 0x0b,0x40 = andeq r3, r1 0x08,0xbf = it eq // 0x00,0xea,0x01,0x00 = andeq.w r0, r0, r1 0x08,0xbf = it eq // 0x01,0xea,0x02,0x02 = andeq.w r2, r1, r2 0x08,0xbf = it eq // 0x11,0xea,0x00,0x00 = andseq.w r0, r1, r0 0x08,0xbf = it eq // 0x0f,0x40 = andeq r7, r1 0x08,0xbf = it eq // 0x0f,0x40 = andeq r7, r1 0x08,0xbf = it eq // 0x01,0xea,0x08,0x08 = andeq.w r8, r1, r8 0x08,0xbf = it eq // 0x08,0xea,0x01,0x08 = andeq.w r8, r8, r1 0x08,0xbf = it eq // 0x08,0xea,0x04,0x04 = andeq.w r4, r8, r4 0x08,0xbf = it eq // 0x04,0xea,0x08,0x04 = andeq.w r4, r4, r8 0x08,0xbf = it eq // 0x00,0xea,0x41,0x00 = andeq.w r0, r0, r1, lsl #1 0x08,0xbf = it eq // 0x01,0xea,0x55,0x05 = andeq.w r5, r1, r5, lsr #1 0x92,0xea,0x01,0x00 = eors.w r0, r2, r1 0x4d,0x40 = eors r5, r1 0x4d,0x40 = eors r5, r1 0x90,0xea,0x01,0x00 = eors.w r0, r0, r1 0x91,0xea,0x02,0x02 = eors.w r2, r1, r2 0x81,0xea,0x01,0x01 = eor.w r1, r1, r1 // 0x4f,0x40 = eors r7, r1 // 0x4f,0x40 = eors r7, r1 0x91,0xea,0x08,0x08 = eors.w r8, r1, r8 0x98,0xea,0x01,0x08 = eors.w r8, r8, r1 0x98,0xea,0x06,0x06 = eors.w r6, r8, r6 0x90,0xea,0x08,0x00 = eors.w r0, r0, r8 0x92,0xea,0x41,0x02 = eors.w r2, r2, r1, lsl #1 0x91,0xea,0x50,0x00 = eors.w r0, r1, r0, lsr #1 0x08,0xbf = it eq // 0x82,0xea,0x01,0x03 = eoreq.w r3, r2, r1 0x08,0xbf = it eq // 0x48,0x40 = eoreq r0, r1 0x08,0xbf = it eq // 0x4a,0x40 = eoreq r2, r1 0x08,0xbf = it eq // 0x83,0xea,0x01,0x03 = eoreq.w r3, r3, r1 0x08,0xbf = it eq // 0x81,0xea,0x00,0x00 = eoreq.w r0, r1, r0 0x08,0xbf = it eq // 0x91,0xea,0x01,0x01 = eorseq.w r1, r1, r1 0x08,0xbf = it eq // 0x4f,0x40 = eoreq r7, r1 0x08,0xbf = it eq // 0x4f,0x40 = eoreq r7, r1 0x08,0xbf = it eq // 0x81,0xea,0x08,0x08 = eoreq.w r8, r1, r8 0x08,0xbf = it eq // 0x88,0xea,0x01,0x08 = eoreq.w r8, r8, r1 0x08,0xbf = it eq // 0x88,0xea,0x00,0x00 = eoreq.w r0, r8, r0 0x08,0xbf = it eq // 0x83,0xea,0x08,0x03 = eoreq.w r3, r3, r8 0x08,0xbf = it eq // 0x84,0xea,0x41,0x04 = eoreq.w r4, r4, r1, lsl #1 0x08,0xbf = it eq // 0x81,0xea,0x50,0x00 = eoreq.w r0, r1, r0, lsr #1 0x12,0xfa,0x01,0xf0 = lsls.w r0, r2, r1 // 0x8a,0x40 = lsls r2, r1 0x11,0xfa,0x02,0xf2 = lsls.w r2, r1, r2 0x10,0xfa,0x01,0xf0 = lsls.w r0, r0, r1 // 0x11,0xfa,0x04,0xf4 = lsls.w r4, r1, r4 0x01,0xfa,0x04,0xf4 = lsl.w r4, r1, r4 // 0x8f,0x40 = lsls r7, r1 0x11,0xfa,0x08,0xf8 = lsls.w r8, r1, r8 0x18,0xfa,0x01,0xf8 = lsls.w r8, r8, r1 0x18,0xfa,0x03,0xf3 = lsls.w r3, r8, r3 0x15,0xfa,0x08,0xf5 = lsls.w r5, r5, r8 0x08,0xbf = it eq // 0x02,0xfa,0x01,0xf0 = lsleq.w r0, r2, r1 0x08,0xbf = it eq // 0x8a,0x40 = lsleq r2, r1 0x08,0xbf = it eq // 0x01,0xfa,0x02,0xf2 = lsleq.w r2, r1, r2 0x08,0xbf = it eq // 0x00,0xfa,0x01,0xf0 = lsleq.w r0, r0, r1 0x08,0xbf = it eq // 0x01,0xfa,0x03,0xf3 = lsleq.w r3, r1, r3 0x08,0xbf = it eq // 0x11,0xfa,0x04,0xf4 = lslseq.w r4, r1, r4 0x08,0xbf = it eq // 0x8f,0x40 = lsleq r7, r1 0x08,0xbf = it eq // 0x01,0xfa,0x08,0xf8 = lsleq.w r8, r1, r8 0x08,0xbf = it eq // 0x08,0xfa,0x01,0xf8 = lsleq.w r8, r8, r1 0x08,0xbf = it eq // 0x08,0xfa,0x00,0xf0 = lsleq.w r0, r8, r0 0x08,0xbf = it eq // 0x03,0xfa,0x08,0xf3 = lsleq.w r3, r3, r8 0x32,0xfa,0x01,0xf6 = lsrs.w r6, r2, r1 0xca,0x40 = lsrs r2, r1 0x31,0xfa,0x02,0xf2 = lsrs.w r2, r1, r2 0x32,0xfa,0x01,0xf2 = lsrs.w r2, r2, r1 0x31,0xfa,0x03,0xf3 = lsrs.w r3, r1, r3 0x21,0xfa,0x04,0xf4 = lsr.w r4, r1, r4 // 0xcf,0x40 = lsrs r7, r1 0x31,0xfa,0x08,0xf8 = lsrs.w r8, r1, r8 0x38,0xfa,0x01,0xf8 = lsrs.w r8, r8, r1 0x38,0xfa,0x02,0xf2 = lsrs.w r2, r8, r2 0x35,0xfa,0x08,0xf5 = lsrs.w r5, r5, r8 0x08,0xbf = it eq // 0x22,0xfa,0x01,0xf6 = lsreq.w r6, r2, r1 0x08,0xbf = it eq // 0xcf,0x40 = lsreq r7, r1 0x08,0xbf = it eq // 0x21,0xfa,0x07,0xf7 = lsreq.w r7, r1, r7 0x08,0xbf = it eq // 0x27,0xfa,0x01,0xf7 = lsreq.w r7, r7, r1 0x08,0xbf = it eq // 0x21,0xfa,0x02,0xf2 = lsreq.w r2, r1, r2 0x08,0xbf = it eq // 0x31,0xfa,0x00,0xf0 = lsrseq.w r0, r1, r0 0x08,0xbf = it eq // 0xcf,0x40 = lsreq r7, r1 0x08,0xbf = it eq // 0x21,0xfa,0x08,0xf8 = lsreq.w r8, r1, r8 0x08,0xbf = it eq // 0x28,0xfa,0x01,0xf8 = lsreq.w r8, r8, r1 0x08,0xbf = it eq // 0x28,0xfa,0x01,0xf1 = lsreq.w r1, r8, r1 0x08,0xbf = it eq // 0x24,0xfa,0x08,0xf4 = lsreq.w r4, r4, r8 0x56,0xfa,0x05,0xf7 = asrs.w r7, r6, r5 0x08,0x41 = asrs r0, r1 0x51,0xfa,0x00,0xf0 = asrs.w r0, r1, r0 0x53,0xfa,0x01,0xf3 = asrs.w r3, r3, r1 0x51,0xfa,0x01,0xf1 = asrs.w r1, r1, r1 0x41,0xfa,0x00,0xf0 = asr.w r0, r1, r0 // 0x0f,0x41 = asrs r7, r1 0x51,0xfa,0x08,0xf8 = asrs.w r8, r1, r8 0x58,0xfa,0x01,0xf8 = asrs.w r8, r8, r1 0x58,0xfa,0x05,0xf5 = asrs.w r5, r8, r5 0x55,0xfa,0x08,0xf5 = asrs.w r5, r5, r8 0x08,0xbf = it eq // 0x42,0xfa,0x01,0xf0 = asreq.w r0, r2, r1 0x08,0xbf = it eq // 0x0a,0x41 = asreq r2, r1 0x08,0xbf = it eq // 0x42,0xfa,0x01,0xf1 = asreq.w r1, r2, r1 0x08,0xbf = it eq // 0x44,0xfa,0x01,0xf4 = asreq.w r4, r4, r1 0x08,0xbf = it eq // 0x41,0xfa,0x06,0xf6 = asreq.w r6, r1, r6 0x08,0xbf = it eq // 0x51,0xfa,0x03,0xf3 = asrseq.w r3, r1, r3 0x08,0xbf = it eq // 0x0f,0x41 = asreq r7, r1 0x08,0xbf = it eq // 0x41,0xfa,0x08,0xf8 = asreq.w r8, r1, r8 0x08,0xbf = it eq // 0x48,0xfa,0x01,0xf8 = asreq.w r8, r8, r1 0x08,0xbf = it eq // 0x48,0xfa,0x01,0xf1 = asreq.w r1, r8, r1 0x08,0xbf = it eq // 0x43,0xfa,0x08,0xf3 = asreq.w r3, r3, r8 0x52,0xeb,0x01,0x05 = adcs.w r5, r2, r1 0x4d,0x41 = adcs r5, r1 // 0x4b,0x41 = adcs r3, r1 0x52,0xeb,0x01,0x02 = adcs.w r2, r2, r1 // 0x51,0xeb,0x03,0x03 = adcs.w r3, r1, r3 // 0x41,0xeb,0x00,0x00 = adc.w r0, r1, r0 // 0x4f,0x41 = adcs r7, r1 // 0x4f,0x41 = adcs r7, r1 0x51,0xeb,0x08,0x08 = adcs.w r8, r1, r8 0x58,0xeb,0x01,0x08 = adcs.w r8, r8, r1 0x58,0xeb,0x05,0x05 = adcs.w r5, r8, r5 0x52,0xeb,0x08,0x02 = adcs.w r2, r2, r8 0x53,0xeb,0x41,0x03 = adcs.w r3, r3, r1, lsl #1 0x51,0xeb,0x54,0x04 = adcs.w r4, r1, r4, lsr #1 0x08,0xbf = it eq // 0x42,0xeb,0x03,0x01 = adceq.w r1, r2, r3 0x08,0xbf = it eq // 0x49,0x41 = adceq r1, r1 0x08,0xbf = it eq // 0x4b,0x41 = adceq r3, r1 0x08,0xbf = it eq // 0x43,0xeb,0x01,0x03 = adceq.w r3, r3, r1 0x08,0xbf = it eq // 0x41,0xeb,0x00,0x00 = adceq.w r0, r1, r0 0x08,0xbf = it eq // 0x51,0xeb,0x03,0x03 = adcseq.w r3, r1, r3 0x08,0xbf = it eq // 0x4f,0x41 = adceq r7, r1 0x08,0xbf = it eq // 0x4f,0x41 = adceq r7, r1 0x08,0xbf = it eq // 0x41,0xeb,0x08,0x08 = adceq.w r8, r1, r8 0x08,0xbf = it eq // 0x48,0xeb,0x01,0x08 = adceq.w r8, r8, r1 0x08,0xbf = it eq // 0x48,0xeb,0x03,0x03 = adceq.w r3, r8, r3 0x08,0xbf = it eq // 0x41,0xeb,0x08,0x01 = adceq.w r1, r1, r8 0x08,0xbf = it eq // 0x42,0xeb,0x41,0x02 = adceq.w r2, r2, r1, lsl #1 0x08,0xbf = it eq // 0x41,0xeb,0x51,0x01 = adceq.w r1, r1, r1, lsr #1 0x72,0xeb,0x01,0x03 = sbcs.w r3, r2, r1 0x8c,0x41 = sbcs r4, r1 0x74,0xeb,0x01,0x01 = sbcs.w r1, r4, r1 0x74,0xeb,0x01,0x04 = sbcs.w r4, r4, r1 // 0x71,0xeb,0x02,0x02 = sbcs.w r2, r1, r2 // 0x61,0xeb,0x00,0x00 = sbc.w r0, r1, r0 // 0x8f,0x41 = sbcs r7, r1 0x71,0xeb,0x08,0x08 = sbcs.w r8, r1, r8 0x78,0xeb,0x01,0x08 = sbcs.w r8, r8, r1 0x78,0xeb,0x04,0x04 = sbcs.w r4, r8, r4 0x73,0xeb,0x08,0x03 = sbcs.w r3, r3, r8 0x72,0xeb,0x41,0x02 = sbcs.w r2, r2, r1, lsl #1 0x71,0xeb,0x55,0x05 = sbcs.w r5, r1, r5, lsr #1 0x08,0xbf = it eq // 0x62,0xeb,0x01,0x05 = sbceq.w r5, r2, r1 0x08,0xbf = it eq // 0x8d,0x41 = sbceq r5, r1 0x08,0xbf = it eq // 0x65,0xeb,0x01,0x01 = sbceq.w r1, r5, r1 0x08,0xbf = it eq // 0x65,0xeb,0x01,0x05 = sbceq.w r5, r5, r1 0x08,0xbf = it eq // 0x61,0xeb,0x00,0x00 = sbceq.w r0, r1, r0 0x08,0xbf = it eq // 0x71,0xeb,0x02,0x02 = sbcseq.w r2, r1, r2 0x08,0xbf = it eq // 0x8f,0x41 = sbceq r7, r1 0x08,0xbf = it eq // 0x61,0xeb,0x08,0x08 = sbceq.w r8, r1, r8 0x08,0xbf = it eq // 0x68,0xeb,0x01,0x08 = sbceq.w r8, r8, r1 0x08,0xbf = it eq // 0x68,0xeb,0x07,0x07 = sbceq.w r7, r8, r7 0x08,0xbf = it eq // 0x67,0xeb,0x08,0x07 = sbceq.w r7, r7, r8 0x08,0xbf = it eq // 0x62,0xeb,0x41,0x02 = sbceq.w r2, r2, r1, lsl #1 0x08,0xbf = it eq // 0x61,0xeb,0x55,0x05 = sbceq.w r5, r1, r5, lsr #1 0x72,0xfa,0x01,0xf3 = rors.w r3, r2, r1 0xc8,0x41 = rors r0, r1 0x70,0xfa,0x01,0xf1 = rors.w r1, r0, r1 0x72,0xfa,0x01,0xf2 = rors.w r2, r2, r1 0x71,0xfa,0x02,0xf2 = rors.w r2, r1, r2 0x61,0xfa,0x05,0xf5 = ror.w r5, r1, r5 // 0xcf,0x41 = rors r7, r1 0x71,0xfa,0x08,0xf8 = rors.w r8, r1, r8 0x78,0xfa,0x01,0xf8 = rors.w r8, r8, r1 0x78,0xfa,0x06,0xf6 = rors.w r6, r8, r6 0x76,0xfa,0x08,0xf6 = rors.w r6, r6, r8 0x08,0xbf = it eq // 0x62,0xfa,0x01,0xf4 = roreq.w r4, r2, r1 0x08,0xbf = it eq // 0xcc,0x41 = roreq r4, r1 0x08,0xbf = it eq // 0x64,0xfa,0x01,0xf1 = roreq.w r1, r4, r1 0x08,0xbf = it eq // 0x64,0xfa,0x01,0xf4 = roreq.w r4, r4, r1 0x08,0xbf = it eq // 0x61,0xfa,0x00,0xf0 = roreq.w r0, r1, r0 0x08,0xbf = it eq // 0x71,0xfa,0x00,0xf0 = rorseq.w r0, r1, r0 0x08,0xbf = it eq // 0xcf,0x41 = roreq r7, r1 0x08,0xbf = it eq // 0x61,0xfa,0x08,0xf8 = roreq.w r8, r1, r8 0x08,0xbf = it eq // 0x68,0xfa,0x01,0xf8 = roreq.w r8, r8, r1 0x08,0xbf = it eq // 0x68,0xfa,0x03,0xf3 = roreq.w r3, r8, r3 0x08,0xbf = it eq // 0x61,0xfa,0x08,0xf1 = roreq.w r1, r1, r8 0x52,0xea,0x01,0x07 = orrs.w r7, r2, r1 0x0a,0x43 = orrs r2, r1 0x0b,0x43 = orrs r3, r1 0x54,0xea,0x01,0x04 = orrs.w r4, r4, r1 0x51,0xea,0x05,0x05 = orrs.w r5, r1, r5 0x41,0xea,0x02,0x02 = orr.w r2, r1, r2 // 0x0f,0x43 = orrs r7, r1 // 0x0f,0x43 = orrs r7, r1 0x51,0xea,0x08,0x08 = orrs.w r8, r1, r8 0x58,0xea,0x01,0x08 = orrs.w r8, r8, r1 0x58,0xea,0x01,0x01 = orrs.w r1, r8, r1 0x50,0xea,0x08,0x00 = orrs.w r0, r0, r8 0x51,0xea,0x41,0x01 = orrs.w r1, r1, r1, lsl #1 0x51,0xea,0x50,0x00 = orrs.w r0, r1, r0, lsr #1 0x08,0xbf = it eq // 0x42,0xea,0x01,0x00 = orreq.w r0, r2, r1 0x08,0xbf = it eq // 0x0d,0x43 = orreq r5, r1 0x08,0xbf = it eq // 0x0d,0x43 = orreq r5, r1 0x08,0xbf = it eq // 0x42,0xea,0x01,0x02 = orreq.w r2, r2, r1 0x08,0xbf = it eq // 0x41,0xea,0x03,0x03 = orreq.w r3, r1, r3 0x08,0xbf = it eq // 0x51,0xea,0x04,0x04 = orrseq.w r4, r1, r4 0x08,0xbf = it eq // 0x0f,0x43 = orreq r7, r1 0x08,0xbf = it eq // 0x0f,0x43 = orreq r7, r1 0x08,0xbf = it eq // 0x41,0xea,0x08,0x08 = orreq.w r8, r1, r8 0x08,0xbf = it eq // 0x48,0xea,0x01,0x08 = orreq.w r8, r8, r1 0x08,0xbf = it eq // 0x48,0xea,0x00,0x00 = orreq.w r0, r8, r0 0x08,0xbf = it eq // 0x40,0xea,0x08,0x00 = orreq.w r0, r0, r8 0x08,0xbf = it eq // 0x42,0xea,0x41,0x02 = orreq.w r2, r2, r1, lsl #1 0x08,0xbf = it eq // 0x41,0xea,0x52,0x02 = orreq.w r2, r1, r2, lsr #1 0x32,0xea,0x01,0x03 = bics.w r3, r2, r1 0x8a,0x43 = bics r2, r1 0x32,0xea,0x01,0x01 = bics.w r1, r2, r1 0x32,0xea,0x01,0x02 = bics.w r2, r2, r1 0x31,0xea,0x00,0x00 = bics.w r0, r1, r0 0x21,0xea,0x00,0x00 = bic.w r0, r1, r0 // 0x8f,0x43 = bics r7, r1 0x31,0xea,0x08,0x08 = bics.w r8, r1, r8 0x38,0xea,0x01,0x08 = bics.w r8, r8, r1 0x38,0xea,0x07,0x07 = bics.w r7, r8, r7 0x35,0xea,0x08,0x05 = bics.w r5, r5, r8 0x33,0xea,0x41,0x03 = bics.w r3, r3, r1, lsl #1 0x31,0xea,0x54,0x04 = bics.w r4, r1, r4, lsr #1 0x08,0xbf = it eq // 0x22,0xea,0x01,0x00 = biceq.w r0, r2, r1 0x08,0xbf = it eq // 0x8d,0x43 = biceq r5, r1 0x08,0xbf = it eq // 0x25,0xea,0x01,0x01 = biceq.w r1, r5, r1 0x08,0xbf = it eq // 0x24,0xea,0x01,0x04 = biceq.w r4, r4, r1 0x08,0xbf = it eq // 0x21,0xea,0x02,0x02 = biceq.w r2, r1, r2 0x08,0xbf = it eq // 0x31,0xea,0x05,0x05 = bicseq.w r5, r1, r5 0x08,0xbf = it eq // 0x8f,0x43 = biceq r7, r1 0x08,0xbf = it eq // 0x21,0xea,0x08,0x08 = biceq.w r8, r1, r8 0x08,0xbf = it eq // 0x28,0xea,0x01,0x08 = biceq.w r8, r8, r1 0x08,0xbf = it eq // 0x28,0xea,0x00,0x00 = biceq.w r0, r8, r0 0x08,0xbf = it eq // 0x22,0xea,0x08,0x02 = biceq.w r2, r2, r8 0x08,0xbf = it eq // 0x24,0xea,0x41,0x04 = biceq.w r4, r4, r1, lsl #1 0x08,0xbf = it eq // 0x21,0xea,0x55,0x05 = biceq.w r5, r1, r5, lsr #1 capstone-sys-0.15.0/capstone/suite/MC/ARM/thumb2-pldw.s.cs000064400000000000000000000001110072674642500212000ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0xb0,0xf8,0x01,0xf1 = pldw [r0, #257] capstone-sys-0.15.0/capstone/suite/MC/ARM/vfp4-thumb.s.cs000064400000000000000000000010750072674642500210410ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None // 0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17 0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0 0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17 0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0 // 0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17 0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0 // 0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17 0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0 0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17 0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0 // 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17 0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0 capstone-sys-0.15.0/capstone/suite/MC/ARM/vfp4.s.cs000064400000000000000000000010730072674642500177220ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None // 0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17 0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0 0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17 0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0 // 0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17 0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0 // 0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17 0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0 0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17 0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0 // 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17 0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0 capstone-sys-0.15.0/capstone/suite/MC/ARM/vpush-vpop-thumb.s.cs000064400000000000000000000006770072674642500223200ustar 00000000000000# CS_ARCH_ARM, CS_MODE_THUMB, None 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} 0x2d,0xed,0x0a,0x8b = vpush {d8, d9, d10, d11, d12} 0x2d,0xed,0x05,0x4a = vpush {s8, s9, s10, s11, s12} 0xbd,0xec,0x0a,0x8b = vpop {d8, d9, d10, d11, d12} 0xbd,0xec,0x05,0x4a = vpop {s8, s9, s10, s11, s12} capstone-sys-0.15.0/capstone/suite/MC/ARM/vpush-vpop.s.cs000064400000000000000000000006750072674642500212010ustar 00000000000000# CS_ARCH_ARM, CS_MODE_ARM, None 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} 0x0a,0x8b,0x2d,0xed = vpush {d8, d9, d10, d11, d12} 0x05,0x4a,0x2d,0xed = vpush {s8, s9, s10, s11, s12} 0x0a,0x8b,0xbd,0xec = vpop {d8, d9, d10, d11, d12} 0x05,0x4a,0xbd,0xec = vpop {s8, s9, s10, s11, s12} capstone-sys-0.15.0/capstone/suite/MC/BPF/classic-all.cs000064400000000000000000000054650072674642500207720ustar 00000000000000# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC, None 0x00,0x00,0x98,0xab,0x08,0x02,0x0e,0x45 = ld 0x450e0208 0x01,0x00,0x44,0x49,0x1f,0xfe,0xd3,0x93 = ldx 0x93d3fe1f 0x04,0x00,0xda,0x23,0x71,0xc5,0x51,0x42 = add 0x4251c571 0x05,0x00,0xd4,0xbd,0x37,0xc8,0x2c,0xd5 = jmp +0xd52cc837 0x06,0x00,0xa7,0x84,0x25,0x40,0x28,0x1c = ret 0x1c284025 0x07,0x00,0xe8,0xe8,0x48,0xe2,0x84,0x2a = tax 0x0c,0x00,0x55,0x8c,0x32,0xd8,0x21,0xe8 = add x 0x0e,0x00,0xd4,0x24,0x96,0xf7,0xa1,0x49 = ret x 0x14,0x00,0x6a,0xc8,0x14,0x50,0x2d,0x69 = sub 0x692d5014 0x15,0x00,0xc3,0x39,0x6e,0x4f,0x37,0x18 = jeq 0x18374f6e, +0xc3, +0x39 0x16,0x00,0x57,0xd2,0xc4,0xd4,0x8a,0x51 = ret a 0x1c,0x00,0xd1,0x51,0x90,0x8a,0x8d,0xea = sub x 0x1d,0x00,0x2e,0xa8,0xbc,0xa7,0xd5,0x3a = jeq x, +0x2e, +0xa8 0x20,0x00,0x9a,0x43,0x93,0x27,0xec,0xf7 = ld [0xf7ec2793] 0x24,0x00,0x0f,0x46,0xbe,0xe5,0xd2,0x4a = mul 0x4ad2e5be 0x25,0x00,0x8c,0x80,0xc1,0x03,0x38,0x61 = jgt 0x613803c1, +0x8c, +0x80 0x28,0x00,0xc3,0x05,0x73,0x01,0x39,0xbd = ldh [0xbd390173] 0x2c,0x00,0x7a,0x3d,0xad,0x19,0xe7,0xcc = mul x 0x2d,0x00,0xd9,0xc6,0xf7,0x72,0x9a,0x9d = jgt x, +0xd9, +0xc6 0x30,0x00,0x22,0x29,0x29,0x5b,0xb5,0x87 = ldb [0x87b55b29] 0x34,0x00,0xa8,0xfa,0x6a,0x92,0xa2,0xa8 = div 0xa8a2926a 0x35,0x00,0x24,0xdb,0x58,0x41,0xa8,0x58 = jge 0x58a84158, +0x24, +0xdb 0x3c,0x00,0x41,0xa6,0xd5,0x66,0x8a,0xdd = div x 0x3d,0x00,0xe4,0xbc,0x40,0xb3,0x4d,0x84 = jge x, +0xe4, +0xbc 0x40,0x00,0xf1,0xa0,0xd9,0x89,0x72,0x25 = ld [x+0x257289d9] 0x44,0x00,0x8d,0xf8,0x49,0xdb,0x10,0x82 = or 0x8210db49 0x45,0x00,0x43,0xfc,0x7d,0xa1,0x34,0xed = jset 0xed34a17d, +0x43, +0xfc 0x48,0x00,0x6b,0x89,0x0b,0xca,0xfb,0x1b = ldh [x+0x1bfbca0b] 0x4c,0x00,0xc9,0xff,0x36,0xe9,0x2a,0xe7 = or x 0x4d,0x00,0x0d,0xaa,0xc3,0x50,0xea,0x40 = jset x, +0xd, +0xaa 0x50,0x00,0xd9,0xf3,0xda,0xa7,0xd9,0xb1 = ldb [x+0xb1d9a7da] 0x54,0x00,0x14,0x82,0x29,0x82,0x6c,0x06 = and 0x66c8229 0x5c,0x00,0x80,0x37,0x5f,0x52,0xc0,0x84 = and x 0x60,0x00,0xba,0x4e,0xb5,0x3f,0xdc,0xd8 = ld m[0xd8dc3fb5] 0x61,0x00,0x06,0xd9,0xcd,0x84,0x58,0x94 = ldx m[0x945884cd] 0x62,0x00,0x2c,0x44,0xdf,0x71,0x48,0x1b = st m[0x1b4871df] 0x63,0x00,0xc9,0x53,0x7f,0x80,0x89,0x2d = stx m[0x2d89807f] 0x64,0x00,0x8a,0xe5,0xf0,0x0c,0xca,0xfd = lsh 0xfdca0cf0 0x6c,0x00,0xd3,0x85,0xc1,0x96,0xb1,0x48 = lsh x 0x74,0x00,0xfa,0x6f,0xe9,0xbe,0xde,0x7e = rsh 0x7edebee9 0x7c,0x00,0x0d,0x89,0xed,0x17,0x7d,0xcd = rsh x 0x80,0x00,0x70,0x62,0x0e,0x61,0x1b,0x94 = ld #len 0x81,0x00,0xa0,0x03,0xa2,0x5c,0x1f,0x2a = ldx #len 0x84,0x00,0x4f,0x0f,0xc9,0x4a,0x72,0xff = neg 0x87,0x00,0x17,0x2a,0x9a,0xd6,0xb6,0x8f = txa 0x94,0x00,0x85,0x0c,0x29,0xb2,0xbe,0x83 = mod 0x83beb229 0x9c,0x00,0x30,0x3f,0x9d,0x33,0x89,0x50 = mod x 0xa1,0x00,0x53,0x03,0xdd,0xdf,0xd4,0xe3 = ldx 4*([0xe3d4dfdd]&0xf) 0xa4,0x00,0x66,0x8f,0x3c,0xde,0xe2,0x4d = xor 0x4de2de3c 0xac,0x00,0x02,0x2f,0x1e,0xe3,0x2e,0x84 = xor x capstone-sys-0.15.0/capstone/suite/MC/BPF/classic-be.cs000064400000000000000000000007100072674642500205740ustar 00000000000000# CS_ARCH_BPF, CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC, None 0x00,0x01,0x00,0x00,0x33,0x00,0x0c,0x11 = ldx 0x33000c11 0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00 = ld #len 0x00,0xa1,0x00,0x00,0x10,0x00,0x00,0x00 = ldx 4*([0x10000000]&0xf) 0x00,0x60,0x00,0x00,0x09,0x00,0x00,0x00 = ld m[0x9000000] 0x00,0x30,0x00,0x00,0x37,0x13,0x03,0x00 = ldb [0x37130300] 0x00,0x63,0x00,0x00,0x0f,0x00,0x30,0x00 = stx m[0xf003000] 0x00,0x84,0x00,0x00,0x00,0x00,0x00,0x00 = neg capstone-sys-0.15.0/capstone/suite/MC/BPF/extended-all.cs000064400000000000000000000134510072674642500211430ustar 00000000000000# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, None 0x04,0xb4,0x97,0xa8,0xe8,0x60,0x56,0xe1 = add r4, 0xe15660e8 0x05,0xc7,0x71,0xb0,0x43,0x1f,0xb9,0xf5 = jmp +0xb071 0x07,0x76,0x01,0x28,0xc4,0x09,0xfe,0x8b = add64 r6, 0x8bfe09c4 0x0c,0x42,0x0a,0x48,0x58,0xc4,0xef,0x37 = add r2, r4 0x0f,0x09,0x40,0x54,0x67,0x24,0x2f,0x88 = add64 r9, r0 0x14,0xd9,0xba,0xb8,0x6f,0x07,0x93,0x2a = sub r9, 0x2a93076f 0x15,0x6a,0x9f,0x38,0x1a,0x9d,0xb7,0x4d = jeq r10, 0x4db79d1a, +0x389f 0x17,0xc5,0x60,0xed,0x0b,0xdc,0xe6,0x22 = sub64 r5, 0x22e6dc0b 0x18,0xa3,0x5c,0x14,0xde,0xf0,0xa5,0xff,0x9a,0x7e,0x10,0xee,0xd8,0xa4,0x2b,0x2f = lddw 0x2f2ba4d8ffa5f0de 0x1c,0x73,0x68,0xa4,0x8b,0x5b,0x93,0x1f = sub r3, r7 0x1d,0x21,0x20,0x4d,0xe3,0x47,0xaf,0x1b = jeq r1, r2, +0x4d20 0x1f,0x06,0x51,0x5a,0x39,0xb2,0x10,0x10 = sub64 r6, r0 0x20,0xc7,0x0c,0x70,0xda,0x41,0x1a,0xca = ldw [0xca1a41da] 0x24,0xb6,0x69,0x66,0xe3,0xef,0xec,0x25 = mul r6, 0x25ecefe3 0x25,0x89,0xda,0x53,0x19,0x73,0x8a,0xc0 = jgt r9, 0xc08a7319, +0x53da 0x27,0xb1,0x96,0x1d,0xd4,0xab,0x2c,0x8c = mul64 r1, 0x8c2cabd4 0x28,0x4e,0xb0,0x62,0xe8,0x48,0x0b,0x0d = ldh [0xd0b48e8] 0x2c,0x78,0x03,0xf6,0x29,0x29,0x15,0xfc = mul r8, r7 0x2d,0x18,0x5b,0xfd,0x8f,0x53,0x3b,0xf0 = jgt r8, r1, +0xfd5b 0x2f,0x77,0xc7,0xa4,0x4c,0x32,0x73,0x2a = mul64 r7, r7 0x30,0x5f,0xfe,0xfc,0x85,0x66,0x7c,0x4b = ldb [0x4b7c6685] 0x34,0x46,0x49,0x33,0xe1,0x72,0xd4,0xcb = div r6, 0xcbd472e1 0x35,0xa5,0x42,0xb9,0x5b,0x37,0xa1,0x3d = jge r5, 0x3da1375b, +0xb942 0x37,0x84,0xd8,0xba,0x3b,0x84,0x55,0x1f = div64 r4, 0x1f55843b 0x38,0x8e,0x3f,0xd7,0x1c,0x3e,0x3a,0x7b = lddw [0x7b3a3e1c] 0x3d,0x1a,0xc3,0x9b,0x88,0xa2,0x3f,0x65 = jge r10, r1, +0x9bc3 0x3f,0x36,0x99,0x32,0x7e,0x07,0x59,0x7a = div64 r6, r3 0x40,0x95,0xc2,0x39,0x6b,0xe7,0xd7,0xc4 = ldw [r9+0xc4d7e76b] 0x44,0x16,0xf7,0x98,0xf7,0x02,0x92,0x94 = or r6, 0x949202f7 0x45,0x12,0xa2,0xf2,0x14,0xe7,0x2d,0x1e = jset r2, 0x1e2de714, +0xf2a2 0x47,0x36,0xf4,0xd5,0xbe,0x04,0x58,0x4d = or64 r6, 0x4d5804be 0x48,0x7e,0xfb,0x77,0xeb,0x0e,0x5a,0x0d = ldh [r7+0xd5a0eeb] 0x4c,0x81,0x0a,0x66,0xfc,0x32,0x61,0xc4 = or r1, r8 0x4d,0x10,0x67,0x44,0x4d,0x3f,0x4d,0x8b = jset r0, r1, +0x4467 0x4f,0x81,0xeb,0x6b,0xde,0x98,0x87,0x64 = or64 r1, r8 0x50,0x38,0x80,0xf8,0x04,0x70,0xd1,0x6c = ldb [r3+0x6cd17004] 0x54,0x40,0x0a,0x6a,0x4a,0xe8,0xab,0xfb = and r0, 0xfbabe84a 0x55,0xb9,0xa3,0x80,0x90,0xbc,0xc8,0x96 = jne r9, 0x96c8bc90, +0x80a3 0x57,0x30,0x12,0xe9,0x7c,0x06,0x82,0x27 = and64 r0, 0x2782067c 0x58,0x6d,0xf1,0x05,0xd3,0x50,0x4b,0xc0 = lddw [r6+0xc04b50d3] 0x5c,0x02,0x95,0xb2,0xbd,0x3f,0x38,0x37 = and r2, r0 0x5d,0x56,0xa3,0x4c,0x2a,0xc8,0x4a,0xc5 = jne r6, r5, +0x4ca3 0x5f,0x59,0xf6,0xaa,0x5d,0xeb,0x27,0xdd = and64 r9, r5 0x61,0x28,0xb2,0xed,0xb8,0xcf,0xb5,0xe4 = ldxw r8, [r2+0xedb2] 0x62,0xa5,0xdf,0xe0,0x14,0x7d,0x95,0x78 = stw [r5+0xe0df], 0x78957d14 0x63,0x77,0x2f,0xcf,0x76,0xb7,0xd3,0xfa = stxw [r7+0xcf2f], r7 0x64,0x68,0xc1,0xf4,0x88,0x92,0xd2,0xeb = lsh r8, 0xebd29288 0x65,0xe8,0x97,0xe1,0x87,0xbe,0x8f,0xf8 = jsgt r8, 0xf88fbe87, +0xe197 0x67,0x00,0xd7,0xc0,0x05,0xb0,0xf6,0x74 = lsh64 r0, 0x74f6b005 0x69,0x14,0xc7,0x8e,0x0b,0xc1,0xad,0x69 = ldxh r4, [r1+0x8ec7] 0x6a,0xb5,0xbc,0x8c,0x4f,0x5c,0x94,0x01 = sth [r5+0x8cbc], 0x1945c4f 0x6b,0x34,0x58,0xf5,0xc8,0x27,0x9e,0x14 = stxh [r4+0xf558], r3 0x6c,0x21,0x10,0x48,0x01,0x3e,0x6e,0xf8 = lsh r1, r2 0x6d,0x38,0x69,0xe3,0xc9,0xac,0x3c,0xdb = jsgt r8, r3, +0xe369 0x6f,0x64,0x49,0xd6,0x07,0xa9,0x93,0x13 = lsh64 r4, r6 0x71,0xa0,0xeb,0xfb,0x3d,0x6b,0x58,0x45 = ldxb r0, [r10+0xfbeb] 0x72,0xe2,0xc1,0x1b,0x25,0x2f,0x4a,0xdc = stb [r2+0x1bc1], 0xdc4a2f25 0x73,0x44,0x09,0x0f,0xc1,0x07,0xa8,0xf4 = stxb [r4+0xf09], r4 0x74,0xe0,0x23,0x23,0x2f,0x04,0x15,0x35 = rsh r0, 0x3515042f 0x75,0x04,0x8e,0x18,0x6a,0xcc,0x3c,0x09 = jsge r4, 0x93ccc6a, +0x188e 0x77,0x09,0x3a,0xa7,0x3c,0x6e,0xfa,0x23 = rsh64 r9, 0x23fa6e3c 0x79,0xa9,0x5c,0x7b,0x16,0x1f,0xfb,0x01 = ldxdw r9, [r10+0x7b5c] 0x7a,0xd8,0x6b,0x04,0x76,0xf0,0x51,0x75 = stdw [r8+0x46b], 0x7551f076 0x7b,0x72,0x0f,0x30,0x51,0x78,0xd2,0x9a = stxdw [r2+0x300f], r7 0x7c,0x13,0x12,0x73,0x5a,0x20,0x65,0xdb = rsh r3, r1 0x7d,0x58,0x52,0x01,0x90,0xf9,0x30,0x9a = jsge r8, r5, +0x152 0x7f,0x98,0xea,0xff,0xcf,0x5d,0x5f,0xa3 = rsh64 r8, r9 0x84,0x14,0xd4,0xaf,0x60,0xe1,0x41,0x18 = neg r4 0x85,0xd3,0xa5,0xe2,0x83,0x3d,0xbd,0x5d = call 0x5dbd3d83 0x87,0xf5,0x2b,0xbe,0xa9,0xc7,0x31,0xa3 = neg64 r5 0x94,0x39,0x0d,0xdc,0x0b,0xd2,0xd1,0xc9 = mod r9, 0xc9d1d20b 0x95,0xf2,0xd1,0x83,0x53,0xa9,0x09,0x9f = exit 0x97,0xc8,0xa6,0x75,0xd2,0x09,0x98,0x09 = mod64 r8, 0x99809d2 0x9c,0x96,0xe7,0x16,0x0f,0x69,0x13,0x90 = mod r6, r9 0x9f,0x35,0x5a,0x59,0xd6,0x70,0xd9,0x5e = mod64 r5, r3 0xa4,0x89,0x6b,0x5f,0x0d,0xbf,0x90,0xf7 = xor r9, 0xf790bf0d 0xa5,0xd4,0xef,0x79,0xd3,0xbb,0xde,0xfd = jlt r4, 0xfddebbd3, +0x79ef 0xa7,0x80,0x8b,0x18,0xa9,0x34,0x74,0x45 = xor64 r0, 0x457434a9 0xac,0x36,0x16,0xe0,0x0f,0x52,0x30,0x65 = xor r6, r3 0xaf,0x41,0x04,0xc2,0x2e,0xc9,0xf7,0x84 = xor64 r1, r4 0xb4,0xa1,0x9c,0x78,0xf9,0x3f,0x77,0x1f = mov r1, 0x1f773ff9 0xb5,0x92,0x5d,0x5a,0x49,0x33,0xfc,0x33 = jle r2, 0x33fc3349, +0x5a5d 0xb7,0x70,0x59,0x4d,0x5b,0x52,0x2a,0x99 = mov64 r0, 0x992a525b 0xbc,0x72,0x3e,0x6c,0xc9,0x8a,0x56,0xd6 = mov r2, r7 0xbd,0x19,0x80,0xe8,0x29,0x85,0xcf,0x51 = jle r9, r1, +0xe880 0xbf,0x86,0x55,0x58,0xb2,0x6d,0x14,0x03 = mov64 r6, r8 0xc4,0xb6,0xe2,0xe0,0x7c,0x68,0xc5,0x2b = arsh r6, 0x2bc5687c 0xc5,0xf2,0xeb,0xe4,0xba,0xc0,0xce,0x4f = jslt r2, 0x4fcec0ba, +0xe4eb 0xc7,0xe8,0xba,0xff,0x1f,0xef,0xc0,0x88 = arsh64 r8, 0x88c0ef1f 0xcc,0x38,0xc5,0x37,0x13,0xc0,0xe7,0x27 = arsh r8, r3 0xcd,0x90,0x67,0x88,0x6b,0xd0,0x27,0xf4 = jslt r0, r9, +0x8867 0xcf,0x82,0xe1,0xcd,0xbe,0xc3,0x2d,0x7c = arsh64 r2, r8 0xd4,0x53,0x3f,0x0c,0x40,0x00,0x00,0x00 = le64 r3 0xd5,0xe9,0xf6,0xb2,0x50,0xfd,0xb0,0xe5 = jsle r9, 0xe5b0fd50, +0xb2f6 0xdc,0xb2,0xa3,0x50,0x20,0x00,0x00,0x00 = be32 r2 0xdd,0x95,0xbf,0xb1,0xf2,0x5f,0x7b,0xc4 = jsle r5, r9, +0xb1bf capstone-sys-0.15.0/capstone/suite/MC/BPF/extended-be.cs000064400000000000000000000016350072674642500207620ustar 00000000000000# CS_ARCH_BPF, CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED, None 0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00 = ldb [0x0] 0x28,0x00,0x00,0x00,0xfa,0x00,0x00,0xff = ldh [0xfa0000ff] 0x40,0x10,0x00,0x00,0xcc,0x00,0x00,0x00 = ldw [r1+0xcc000000] 0x18,0x00,0x00,0x00,0x0c,0xb0,0xce,0xfa,0x00,0x00,0x00,0x00,0xef,0xbe,0xad,0xde = lddw 0xefbeadde0cb0cefa 0x71,0x13,0x11,0x00,0x00,0x00,0x00,0x00 = ldxb r3, [r1+0x1100] 0x94,0x09,0x00,0x00,0x37,0x13,0x03,0x00 = mod r9, 0x37130300 0x84,0x03,0x00,0x00,0x00,0x00,0x00,0x00 = neg r3 0x87,0x00,0x00,0x00,0x00,0x00,0x00,0x00 = neg64 r0 0xdc,0x02,0x00,0x00,0x00,0x00,0x00,0x20 = be32 r2 0x05,0x00,0x08,0x00,0x00,0x00,0x00,0x00 = jmp +0x800 0xdd,0x35,0x30,0x00,0x00,0x00,0x00,0x00 = jsle r5, r3, +0x3000 0xa5,0x35,0x30,0x00,0x10,0x00,0x00,0x00 = jlt r5, 0x10000000, +0x3000 0xc3,0x12,0x00,0x10,0x00,0x00,0x00,0x00 = xaddw [r2+0x10], r1 0xdb,0xa9,0x00,0x01,0x00,0x00,0x00,0x00 = xadddw [r9+0x1], r10 capstone-sys-0.15.0/capstone/suite/MC/Mips/hilo-addressing.s.cs000064400000000000000000000002610072674642500224060ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None // 0x3c,0x04,0xde,0xae = lui $a0, %hi(addr) 0x03,0xe0,0x00,0x08 = jr $ra // 0x80,0x82,0xbe,0xef = lb $v0, %lo(addr)($a0) capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-alu-instructions-EB.s.cs000064400000000000000000000025500072674642500251440ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None 0x00,0xe6,0x49,0x10 = add $t1, $a2, $a3 0x11,0x26,0x45,0x67 = addi $t1, $a2, 17767 0x31,0x26,0xc5,0x67 = addiu $t1, $a2, -15001 0x11,0x26,0x45,0x67 = addi $t1, $a2, 17767 0x31,0x26,0xc5,0x67 = addiu $t1, $a2, -15001 0x00,0xe6,0x49,0x50 = addu $t1, $a2, $a3 0x00,0xe6,0x49,0x90 = sub $t1, $a2, $a3 0x00,0xa3,0x21,0xd0 = subu $a0, $v1, $a1 0x00,0xe0,0x31,0x90 = sub $a2, $zero, $a3 0x00,0xe0,0x31,0xd0 = subu $a2, $zero, $a3 0x00,0x08,0x39,0x50 = addu $a3, $t0, $zero 0x00,0xa3,0x1b,0x50 = slt $v1, $v1, $a1 0x90,0x63,0x00,0x67 = slti $v1, $v1, 103 0x90,0x63,0x00,0x67 = slti $v1, $v1, 103 0xb0,0x63,0x00,0x67 = sltiu $v1, $v1, 103 0x00,0xa3,0x1b,0x90 = sltu $v1, $v1, $a1 0x41,0xa9,0x45,0x67 = lui $t1, 17767 0x00,0xe6,0x4a,0x50 = and $t1, $a2, $a3 0xd1,0x26,0x45,0x67 = andi $t1, $a2, 17767 0xd1,0x26,0x45,0x67 = andi $t1, $a2, 17767 0x00,0xa4,0x1a,0x90 = or $v1, $a0, $a1 0x51,0x26,0x45,0x67 = ori $t1, $a2, 17767 0x00,0xa3,0x1b,0x10 = xor $v1, $v1, $a1 0x71,0x26,0x45,0x67 = xori $t1, $a2, 17767 0x71,0x26,0x45,0x67 = xori $t1, $a2, 17767 0x00,0xe6,0x4a,0xd0 = nor $t1, $a2, $a3 0x00,0x08,0x3a,0xd0 = not $a3, $t0 0x00,0xe6,0x4a,0x10 = mul $t1, $a2, $a3 0x00,0xe9,0x8b,0x3c = mult $t1, $a3 0x00,0xe9,0x9b,0x3c = multu $t1, $a3 0x00,0xe9,0xab,0x3c = div $zero, $t1, $a3 0x00,0xe9,0xbb,0x3c = divu $zero, $t1, $a3 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-alu-instructions.s.cs000064400000000000000000000025250072674642500246620ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0xe6,0x00,0x10,0x49 = add $t1, $a2, $a3 0x26,0x11,0x67,0x45 = addi $t1, $a2, 17767 0x26,0x31,0x67,0xc5 = addiu $t1, $a2, -15001 0x26,0x11,0x67,0x45 = addi $t1, $a2, 17767 0x26,0x31,0x67,0xc5 = addiu $t1, $a2, -15001 0xe6,0x00,0x50,0x49 = addu $t1, $a2, $a3 0xe6,0x00,0x90,0x49 = sub $t1, $a2, $a3 0xa3,0x00,0xd0,0x21 = subu $a0, $v1, $a1 0xe0,0x00,0x90,0x31 = sub $a2, $zero, $a3 0xe0,0x00,0xd0,0x31 = subu $a2, $zero, $a3 0x08,0x00,0x50,0x39 = addu $a3, $t0, $zero 0xa3,0x00,0x50,0x1b = slt $v1, $v1, $a1 0x63,0x90,0x67,0x00 = slti $v1, $v1, 103 0x63,0x90,0x67,0x00 = slti $v1, $v1, 103 0x63,0xb0,0x67,0x00 = sltiu $v1, $v1, 103 0xa3,0x00,0x90,0x1b = sltu $v1, $v1, $a1 0xa9,0x41,0x67,0x45 = lui $t1, 17767 0xe6,0x00,0x50,0x4a = and $t1, $a2, $a3 0x26,0xd1,0x67,0x45 = andi $t1, $a2, 17767 0x26,0xd1,0x67,0x45 = andi $t1, $a2, 17767 0xa4,0x00,0x90,0x1a = or $v1, $a0, $a1 0x26,0x51,0x67,0x45 = ori $t1, $a2, 17767 0xa3,0x00,0x10,0x1b = xor $v1, $v1, $a1 0x26,0x71,0x67,0x45 = xori $t1, $a2, 17767 0x26,0x71,0x67,0x45 = xori $t1, $a2, 17767 0xe6,0x00,0xd0,0x4a = nor $t1, $a2, $a3 0x08,0x00,0xd0,0x3a = not $a3, $t0 0xe6,0x00,0x10,0x4a = mul $t1, $a2, $a3 0xe9,0x00,0x3c,0x8b = mult $t1, $a3 0xe9,0x00,0x3c,0x9b = multu $t1, $a3 0xe9,0x00,0x3c,0xab = div $zero, $t1, $a3 0xe9,0x00,0x3c,0xbb = divu $zero, $t1, $a3 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-branch-instructions-EB.s.cs000064400000000000000000000006710072674642500256220ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0x94,0x00,0x02,0x9a = b 1332 0x94,0xc9,0x02,0x9a = beq $t1, $a2, 1332 0x40,0x46,0x02,0x9a = bgez $a2, 1332 0x40,0x66,0x02,0x9a = bgezal $a2, 1332 0x40,0x26,0x02,0x9a = bltzal $a2, 1332 0x40,0xc6,0x02,0x9a = bgtz $a2, 1332 0x40,0x86,0x02,0x9a = blez $a2, 1332 0xb4,0xc9,0x02,0x9a = bne $t1, $a2, 1332 // 0x40,0x60,0x02,0x9a = bal 1332 0x40,0x06,0x02,0x9a = bltz $a2, 1332 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-branch-instructions.s.cs000064400000000000000000000006460072674642500253400ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0x00,0x94,0x9a,0x02 = b 1332 0xc9,0x94,0x9a,0x02 = beq $t1, $a2, 1332 0x46,0x40,0x9a,0x02 = bgez $a2, 1332 0x66,0x40,0x9a,0x02 = bgezal $a2, 1332 0x26,0x40,0x9a,0x02 = bltzal $a2, 1332 0xc6,0x40,0x9a,0x02 = bgtz $a2, 1332 0x86,0x40,0x9a,0x02 = blez $a2, 1332 0xc9,0xb4,0x9a,0x02 = bne $t1, $a2, 1332 // 0x60,0x40,0x9a,0x02 = bal 1332 0x06,0x40,0x9a,0x02 = bltz $a2, 1332 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-expansions.s.cs000064400000000000000000000014270072674642500235260ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0xa0,0x50,0x7b,0x00 = ori $a1, $zero, 123 0xc0,0x30,0xd7,0xf6 = addiu $a2, $zero, -2345 0xa7,0x41,0x01,0x00 = lui $a3, 1 0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 0x80,0x30,0x14,0x00 = addiu $a0, $zero, 20 0xa7,0x41,0x01,0x00 = lui $a3, 1 0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 0x85,0x30,0x14,0x00 = addiu $a0, $a1, 20 0xa7,0x41,0x01,0x00 = lui $a3, 1 0xe7,0x50,0x02,0x00 = ori $a3, $a3, 2 0x07,0x01,0x50,0x39 = addu $a3, $a3, $t0 0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 0x21,0x01,0x50,0x09 = addu $at, $at, $t1 0xaa,0x41,0x0a,0x00 = lui $t2, 10 0x8a,0x00,0x50,0x51 = addu $t2, $t2, $a0 0x4a,0xfd,0x7b,0x00 = lw $t2, 123($t2) 0xa1,0x41,0x02,0x00 = lui $at, 2 0x21,0x01,0x50,0x09 = addu $at, $at, $t1 // 0x41,0xf9,0x40,0xe2 = sw $t2, 57920($at) capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-jump-instructions-EB.s.cs000064400000000000000000000003010072674642500253260ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0xd4,0x00,0x02,0x98 = j 1328 0xf4,0x00,0x02,0x98 = jal 1328 // 0x03,0xe6,0x0f,0x3c = jalr $a2 0x00,0x07,0x0f,0x3c = jr $a3 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-jump-instructions.s.cs000064400000000000000000000003130072674642500250450ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0x00,0xd4,0x98,0x02 = j 1328 0x00,0xf4,0x98,0x02 = jal 1328 // 0xe6,0x03,0x3c,0x0f = jalr $a2 0x07,0x00,0x3c,0x0f = jr $a3 0x07,0x00,0x3c,0x0f = jr $a3 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs000064400000000000000000000005600072674642500263560ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0x1c,0xa4,0x00,0x08 = lb $a1, 8($a0) 0x14,0xc4,0x00,0x08 = lbu $a2, 8($a0) 0x3c,0x44,0x00,0x08 = lh $v0, 8($a0) 0x34,0x82,0x00,0x08 = lhu $a0, 8($v0) 0xfc,0xc5,0x00,0x04 = lw $a2, 4($a1) 0x18,0xa4,0x00,0x08 = sb $a1, 8($a0) 0x38,0x44,0x00,0x08 = sh $v0, 8($a0) 0xf8,0xa6,0x00,0x04 = sw $a1, 4($a2) capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-loadstore-instructions.s.cs000064400000000000000000000005350072674642500260740ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0xa4,0x1c,0x08,0x00 = lb $a1, 8($a0) 0xc4,0x14,0x08,0x00 = lbu $a2, 8($a0) 0x44,0x3c,0x08,0x00 = lh $v0, 8($a0) 0x82,0x34,0x08,0x00 = lhu $a0, 8($v0) 0xc5,0xfc,0x04,0x00 = lw $a2, 4($a1) 0xa4,0x18,0x08,0x00 = sb $a1, 8($a0) 0x44,0x38,0x08,0x00 = sh $v0, 8($a0) 0xa6,0xf8,0x04,0x00 = sw $a1, 4($a2) capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs000064400000000000000000000003420072674642500255560ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0x60,0x85,0x00,0x10 = lwl $a0, 16($a1) 0x60,0x85,0x10,0x10 = lwr $a0, 16($a1) 0x60,0x85,0x80,0x10 = swl $a0, 16($a1) 0x60,0x85,0x90,0x10 = swr $a0, 16($a1) capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-loadstore-unaligned.s.cs000064400000000000000000000003170072674642500252740ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0x85,0x60,0x10,0x00 = lwl $a0, 16($a1) 0x85,0x60,0x10,0x10 = lwr $a0, 16($a1) 0x85,0x60,0x10,0x80 = swl $a0, 16($a1) 0x85,0x60,0x10,0x90 = swr $a0, 16($a1) capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-movcond-instructions-EB.s.cs000064400000000000000000000003560072674642500260320ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0x00,0xe6,0x48,0x58 = movz $t1, $a2, $a3 0x00,0xe6,0x48,0x18 = movn $t1, $a2, $a3 0x55,0x26,0x09,0x7b = movt $t1, $a2, $fcc0 0x55,0x26,0x01,0x7b = movf $t1, $a2, $fcc0 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-movcond-instructions.s.cs000064400000000000000000000003330072674642500255410ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0xe6,0x00,0x58,0x48 = movz $t1, $a2, $a3 0xe6,0x00,0x18,0x48 = movn $t1, $a2, $a3 0x26,0x55,0x7b,0x09 = movt $t1, $a2, $fcc0 0x26,0x55,0x7b,0x01 = movf $t1, $a2, $fcc0 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-multiply-instructions-EB.s.cs000064400000000000000000000003300072674642500262340ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0x00,0xa4,0xcb,0x3c = madd $a0, $a1 0x00,0xa4,0xdb,0x3c = maddu $a0, $a1 0x00,0xa4,0xeb,0x3c = msub $a0, $a1 0x00,0xa4,0xfb,0x3c = msubu $a0, $a1 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-multiply-instructions.s.cs000064400000000000000000000003050072674642500257520ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0xa4,0x00,0x3c,0xcb = madd $a0, $a1 0xa4,0x00,0x3c,0xdb = maddu $a0, $a1 0xa4,0x00,0x3c,0xeb = msub $a0, $a1 0xa4,0x00,0x3c,0xfb = msubu $a0, $a1 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-shift-instructions-EB.s.cs000064400000000000000000000006040072674642500254760ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None 0x00,0x83,0x38,0x00 = sll $a0, $v1, 7 0x00,0x65,0x10,0x10 = sllv $v0, $v1, $a1 0x00,0x83,0x38,0x80 = sra $a0, $v1, 7 0x00,0x65,0x10,0x90 = srav $v0, $v1, $a1 0x00,0x83,0x38,0x40 = srl $a0, $v1, 7 0x00,0x65,0x10,0x50 = srlv $v0, $v1, $a1 0x01,0x26,0x38,0xc0 = rotr $t1, $a2, 7 0x00,0xc7,0x48,0xd0 = rotrv $t1, $a2, $a3 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-shift-instructions.s.cs000064400000000000000000000005610072674642500252140ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None 0x83,0x00,0x00,0x38 = sll $a0, $v1, 7 0x65,0x00,0x10,0x10 = sllv $v0, $v1, $a1 0x83,0x00,0x80,0x38 = sra $a0, $v1, 7 0x65,0x00,0x90,0x10 = srav $v0, $v1, $a1 0x83,0x00,0x40,0x38 = srl $a0, $v1, 7 0x65,0x00,0x50,0x10 = srlv $v0, $v1, $a1 0x26,0x01,0xc0,0x38 = rotr $t1, $a2, 7 0xc7,0x00,0xd0,0x48 = rotrv $t1, $a2, $a3 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-trap-instructions-EB.s.cs000064400000000000000000000010220072674642500253220ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None // 0x01,0x28,0x00,0x3c = teq $t0, $t1 // 0x01,0x28,0x02,0x3c = tge $t0, $t1 // 0x01,0x28,0x04,0x3c = tgeu $t0, $t1 // 0x01,0x28,0x08,0x3c = tlt $t0, $t1 // 0x01,0x28,0x0a,0x3c = tltu $t0, $t1 // 0x01,0x28,0x0c,0x3c = tne $t0, $t1 0x41,0xc9,0x45,0x67 = teqi $t1, 17767 0x41,0x29,0x45,0x67 = tgei $t1, 17767 0x41,0x69,0x45,0x67 = tgeiu $t1, 17767 0x41,0x09,0x45,0x67 = tlti $t1, 17767 0x41,0x49,0x45,0x67 = tltiu $t1, 17767 0x41,0x89,0x45,0x67 = tnei $t1, 17767 capstone-sys-0.15.0/capstone/suite/MC/Mips/micromips-trap-instructions.s.cs000064400000000000000000000007770072674642500250560ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None // 0x28,0x01,0x3c,0x00 = teq $t0, $t1 // 0x28,0x01,0x3c,0x02 = tge $t0, $t1 // 0x28,0x01,0x3c,0x04 = tgeu $t0, $t1 // 0x28,0x01,0x3c,0x08 = tlt $t0, $t1 // 0x28,0x01,0x3c,0x0a = tltu $t0, $t1 // 0x28,0x01,0x3c,0x0c = tne $t0, $t1 0xc9,0x41,0x67,0x45 = teqi $t1, 17767 0x29,0x41,0x67,0x45 = tgei $t1, 17767 0x69,0x41,0x67,0x45 = tgeiu $t1, 17767 0x09,0x41,0x67,0x45 = tlti $t1, 17767 0x49,0x41,0x67,0x45 = tltiu $t1, 17767 0x89,0x41,0x67,0x45 = tnei $t1, 17767 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-alu-instructions.s.cs000064400000000000000000000040770072674642500236340ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32, None 0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 0x67,0x45,0x29,0x31 = andi $t1, $t1, 17767 0x21,0x30,0xe6,0x70 = clo $a2, $a3 0x20,0x30,0xe6,0x70 = clz $a2, $a3 0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 0x80,0x00,0x6b,0x35 = ori $t3, $t3, 128 0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 0x0c,0x00,0x6b,0x39 = xori $t3, $t3, 12 0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 0x27,0x38,0x00,0x01 = not $a3, $t0 0x20,0x48,0xc7,0x00 = add $t1, $a2, $a3 0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 0x67,0x45,0xc9,0x20 = addi $t1, $a2, 17767 0x67,0x45,0x29,0x21 = addi $t1, $t1, 17767 0x67,0xc5,0xc9,0x24 = addiu $t1, $a2, -15001 0x28,0x00,0x6b,0x25 = addiu $t3, $t3, 40 0x21,0x48,0xc7,0x00 = addu $t1, $a2, $a3 0x00,0x00,0xc7,0x70 = madd $a2, $a3 0x01,0x00,0xc7,0x70 = maddu $a2, $a3 0x04,0x00,0xc7,0x70 = msub $a2, $a3 0x05,0x00,0xc7,0x70 = msubu $a2, $a3 0x18,0x00,0x65,0x00 = mult $v1, $a1 0x19,0x00,0x65,0x00 = multu $v1, $a1 0x22,0x48,0xc7,0x00 = sub $t1, $a2, $a3 0xc8,0xff,0xbd,0x23 = addi $sp, $sp, -56 0x23,0x20,0x65,0x00 = subu $a0, $v1, $a1 0xd8,0xff,0xbd,0x27 = addiu $sp, $sp, -40 0x22,0x30,0x07,0x00 = neg $a2, $a3 0x23,0x30,0x07,0x00 = negu $a2, $a3 0x21,0x38,0x00,0x01 = move $a3, $t0 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-control-instructions-64.s.cs000064400000000000000000000022000072674642500247440ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 0x00,0x00,0x00,0x0d = break // 0x00,0x07,0x00,0x0d = break 7, 0 0x00,0x07,0x01,0x4d = break 7, 5 0x00,0x00,0x00,0x0c = syscall 0x00,0x0d,0x15,0x0c = syscall 13396 0x42,0x00,0x00,0x18 = eret 0x42,0x00,0x00,0x1f = deret 0x41,0x60,0x60,0x00 = di 0x41,0x60,0x60,0x00 = di 0x41,0x6a,0x60,0x00 = di $t2 0x41,0x60,0x60,0x20 = ei 0x41,0x60,0x60,0x20 = ei 0x41,0x6a,0x60,0x20 = ei $t2 0x42,0x00,0x00,0x20 = wait 0x00,0x03,0x00,0x34 = teq $zero, $v1 0x00,0x03,0x00,0x74 = teq $zero, $v1, 1 0x04,0x6c,0x00,0x01 = teqi $v1, 1 0x00,0x03,0x00,0x30 = tge $zero, $v1 0x00,0x03,0x00,0xf0 = tge $zero, $v1, 3 0x04,0x68,0x00,0x03 = tgei $v1, 3 0x00,0x03,0x00,0x31 = tgeu $zero, $v1 0x00,0x03,0x01,0xf1 = tgeu $zero, $v1, 7 0x04,0x69,0x00,0x07 = tgeiu $v1, 7 0x00,0x03,0x00,0x32 = tlt $zero, $v1 0x00,0x03,0x07,0xf2 = tlt $zero, $v1, 31 0x04,0x6a,0x00,0x1f = tlti $v1, 31 0x00,0x03,0x00,0x33 = tltu $zero, $v1 0x00,0x03,0x3f,0xf3 = tltu $zero, $v1, 255 0x04,0x6b,0x00,0xff = tltiu $v1, 255 0x00,0x03,0x00,0x36 = tne $zero, $v1 0x00,0x03,0xff,0xf6 = tne $zero, $v1, 1023 0x04,0x6e,0x03,0xff = tnei $v1, 1023 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-control-instructions.s.cs000064400000000000000000000022000072674642500245150ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x00,0x00,0x00,0x0d = break // 0x00,0x07,0x00,0x0d = break 7, 0 0x00,0x07,0x01,0x4d = break 7, 5 0x00,0x00,0x00,0x0c = syscall 0x00,0x0d,0x15,0x0c = syscall 13396 0x42,0x00,0x00,0x18 = eret 0x42,0x00,0x00,0x1f = deret 0x41,0x60,0x60,0x00 = di 0x41,0x60,0x60,0x00 = di 0x41,0x6a,0x60,0x00 = di $t2 0x41,0x60,0x60,0x20 = ei 0x41,0x60,0x60,0x20 = ei 0x41,0x6a,0x60,0x20 = ei $t2 0x42,0x00,0x00,0x20 = wait 0x00,0x03,0x00,0x34 = teq $zero, $v1 0x00,0x03,0x00,0x74 = teq $zero, $v1, 1 0x04,0x6c,0x00,0x01 = teqi $v1, 1 0x00,0x03,0x00,0x30 = tge $zero, $v1 0x00,0x03,0x00,0xf0 = tge $zero, $v1, 3 0x04,0x68,0x00,0x03 = tgei $v1, 3 0x00,0x03,0x00,0x31 = tgeu $zero, $v1 0x00,0x03,0x01,0xf1 = tgeu $zero, $v1, 7 0x04,0x69,0x00,0x07 = tgeiu $v1, 7 0x00,0x03,0x00,0x32 = tlt $zero, $v1 0x00,0x03,0x07,0xf2 = tlt $zero, $v1, 31 0x04,0x6a,0x00,0x1f = tlti $v1, 31 0x00,0x03,0x00,0x33 = tltu $zero, $v1 0x00,0x03,0x3f,0xf3 = tltu $zero, $v1, 255 0x04,0x6b,0x00,0xff = tltiu $v1, 255 0x00,0x03,0x00,0x36 = tne $zero, $v1 0x00,0x03,0xff,0xf6 = tne $zero, $v1, 1023 0x04,0x6e,0x03,0xff = tnei $v1, 1023 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-coprocessor-encodings.s.cs000064400000000000000000000012600072674642500246100ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 0x40,0xac,0x80,0x02 = dmtc0 $t4, $s0, 2 0x40,0xac,0x80,0x00 = dmtc0 $t4, $s0, 0 0x40,0x8c,0x80,0x02 = mtc0 $t4, $s0, 2 0x40,0x8c,0x80,0x00 = mtc0 $t4, $s0, 0 0x40,0x2c,0x80,0x02 = dmfc0 $t4, $s0, 2 0x40,0x2c,0x80,0x00 = dmfc0 $t4, $s0, 0 0x40,0x0c,0x80,0x02 = mfc0 $t4, $s0, 2 0x40,0x0c,0x80,0x00 = mfc0 $t4, $s0, 0 0x48,0xac,0x80,0x02 = dmtc2 $t4, $s0, 2 0x48,0xac,0x80,0x00 = dmtc2 $t4, $s0, 0 0x48,0x8c,0x80,0x02 = mtc2 $t4, $s0, 2 0x48,0x8c,0x80,0x00 = mtc2 $t4, $s0, 0 0x48,0x2c,0x80,0x02 = dmfc2 $t4, $s0, 2 0x48,0x2c,0x80,0x00 = dmfc2 $t4, $s0, 0 0x48,0x0c,0x80,0x02 = mfc2 $t4, $s0, 2 0x48,0x0c,0x80,0x00 = mfc2 $t4, $s0, 0 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-dsp-instructions.s.cs000064400000000000000000000034610072674642500236350ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x7e,0x32,0x83,0x11 = precrq.qb.ph $s0, $s1, $s2 0x7e,0x53,0x8d,0x11 = precrq.ph.w $s1, $s2, $s3 0x7e,0x74,0x95,0x51 = precrq_rs.ph.w $s2, $s3, $s4 0x7e,0x95,0x9b,0xd1 = precrqu_s.qb.ph $s3, $s4, $s5 0x7c,0x15,0xa3,0x12 = preceq.w.phl $s4, $s5 0x7c,0x16,0xab,0x52 = preceq.w.phr $s5, $s6 0x7c,0x17,0xb1,0x12 = precequ.ph.qbl $s6, $s7 0x7c,0x18,0xb9,0x52 = precequ.ph.qbr $s7, $t8 0x7c,0x19,0xc1,0x92 = precequ.ph.qbla $t8, $t9 0x7c,0x1a,0xc9,0xd2 = precequ.ph.qbra $t9, $k0 0x7c,0x1b,0xd7,0x12 = preceu.ph.qbl $k0, $k1 0x7c,0x1c,0xdf,0x52 = preceu.ph.qbr $k1, $gp 0x7c,0x1d,0xe7,0x92 = preceu.ph.qbla $gp, $sp 0x7c,0x1e,0xef,0xd2 = preceu.ph.qbra $sp, $fp 0x7f,0x19,0xbb,0x51 = precr.qb.ph $s7, $t8, $t9 0x7f,0x38,0x07,0x91 = precr_sra.ph.w $t8, $t9, 0 0x7f,0x38,0xff,0x91 = precr_sra.ph.w $t8, $t9, 31 0x7f,0x59,0x07,0xd1 = precr_sra_r.ph.w $t9, $k0, 0 0x7f,0x59,0xff,0xd1 = precr_sra_r.ph.w $t9, $k0, 31 0x7f,0x54,0x51,0x8a = lbux $t2, $s4($k0) 0x7f,0x75,0x59,0x0a = lhx $t3, $s5($k1) 0x7f,0x96,0x60,0x0a = lwx $t4, $s6($gp) 0x00,0x43,0x18,0x18 = mult $ac3, $v0, $v1 0x00,0x85,0x10,0x19 = multu $ac2, $a0, $a1 0x70,0xc7,0x08,0x00 = madd $ac1, $a2, $a3 // 0x71,0x09,0x00,0x01 = maddu $ac0, $t0, $t1 0x71,0x4b,0x18,0x04 = msub $ac3, $t2, $t3 0x71,0x8d,0x10,0x05 = msubu $ac2, $t4, $t5 0x00,0x20,0x70,0x10 = mfhi $t6, $ac1 // 0x00,0x00,0x78,0x12 = mflo $t7, $ac0 0x02,0x00,0x18,0x11 = mthi $s0, $ac3 0x02,0x20,0x10,0x13 = mtlo $s1, $ac2 0x00,0x43,0x00,0x18 = mult $v0, $v1 0x00,0x85,0x00,0x19 = multu $a0, $a1 0x70,0xc7,0x00,0x00 = madd $a2, $a3 // 0x71,0x09,0x00,0x01 = maddu $t0, $t1 0x71,0x4b,0x00,0x04 = msub $t2, $t3 0x71,0x8d,0x00,0x05 = msubu $t4, $t5 0x00,0x00,0x70,0x10 = mfhi $t6 // 0x00,0x00,0x78,0x12 = mflo $t7 0x02,0x00,0x00,0x11 = mthi $s0 0x02,0x20,0x00,0x13 = mtlo $s1 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-expansions.s.cs000064400000000000000000000013400072674642500224660ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32, None 0x7b,0x00,0x05,0x34 = ori $a1, $zero, 123 0xd7,0xf6,0x06,0x24 = addiu $a2, $zero, -2345 0x01,0x00,0x07,0x3c = lui $a3, 1 0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 0x14,0x00,0x04,0x24 = addiu $a0, $zero, 20 0x01,0x00,0x07,0x3c = lui $a3, 1 0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 0x14,0x00,0xa4,0x24 = addiu $a0, $a1, 20 0x01,0x00,0x07,0x3c = lui $a3, 1 0x02,0x00,0xe7,0x34 = ori $a3, $a3, 2 0x21,0x38,0xe8,0x00 = addu $a3, $a3, $t0 0x21,0x50,0x44,0x01 = addu $t2, $t2, $a0 0x21,0x08,0x29,0x00 = addu $at, $at, $t1 0x0a,0x00,0x0a,0x3c = lui $t2, 10 0x7b,0x00,0x4a,0x8d = lw $t2, 123($t2) 0x02,0x00,0x01,0x3c = lui $at, 2 0x21,0x08,0x29,0x00 = addu $at, $at, $t1 // 0x40,0xe2,0x2a,0xac = sw $t2, 57920($at) capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-fpu-instructions.s.cs000064400000000000000000000071450072674642500236440ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32, None 0x05,0x73,0x20,0x46 = abs.d $f12, $f14 0x85,0x39,0x00,0x46 = abs.s $f6, $f7 0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14 0x40,0x32,0x07,0x46 = add.s $f9, $f6, $f7 0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14 0x8f,0x39,0x00,0x46 = floor.w.s $f6, $f7 0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14 0x8e,0x39,0x00,0x46 = ceil.w.s $f6, $f7 0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14 0x42,0x32,0x07,0x46 = mul.s $f9, $f6, $f7 0x07,0x73,0x20,0x46 = neg.d $f12, $f14 0x87,0x39,0x00,0x46 = neg.s $f6, $f7 0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14 0x8c,0x39,0x00,0x46 = round.w.s $f6, $f7 0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14 0x84,0x39,0x00,0x46 = sqrt.s $f6, $f7 0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14 0x41,0x32,0x07,0x46 = sub.s $f9, $f6, $f7 0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14 0x8d,0x39,0x00,0x46 = trunc.w.s $f6, $f7 0x32,0x60,0x2e,0x46 = c.eq.d $f12, $f14 0x32,0x30,0x07,0x46 = c.eq.s $f6, $f7 0x30,0x60,0x2e,0x46 = c.f.d $f12, $f14 0x30,0x30,0x07,0x46 = c.f.s $f6, $f7 0x3e,0x60,0x2e,0x46 = c.le.d $f12, $f14 0x3e,0x30,0x07,0x46 = c.le.s $f6, $f7 0x3c,0x60,0x2e,0x46 = c.lt.d $f12, $f14 0x3c,0x30,0x07,0x46 = c.lt.s $f6, $f7 0x3d,0x60,0x2e,0x46 = c.nge.d $f12, $f14 0x3d,0x30,0x07,0x46 = c.nge.s $f6, $f7 0x3b,0x60,0x2e,0x46 = c.ngl.d $f12, $f14 0x3b,0x30,0x07,0x46 = c.ngl.s $f6, $f7 0x39,0x60,0x2e,0x46 = c.ngle.d $f12, $f14 0x39,0x30,0x07,0x46 = c.ngle.s $f6, $f7 0x3f,0x60,0x2e,0x46 = c.ngt.d $f12, $f14 0x3f,0x30,0x07,0x46 = c.ngt.s $f6, $f7 0x36,0x60,0x2e,0x46 = c.ole.d $f12, $f14 0x36,0x30,0x07,0x46 = c.ole.s $f6, $f7 0x34,0x60,0x2e,0x46 = c.olt.d $f12, $f14 0x34,0x30,0x07,0x46 = c.olt.s $f6, $f7 0x3a,0x60,0x2e,0x46 = c.seq.d $f12, $f14 0x3a,0x30,0x07,0x46 = c.seq.s $f6, $f7 0x38,0x60,0x2e,0x46 = c.sf.d $f12, $f14 0x38,0x30,0x07,0x46 = c.sf.s $f6, $f7 0x33,0x60,0x2e,0x46 = c.ueq.d $f12, $f14 0x33,0xe0,0x12,0x46 = c.ueq.s $f28, $f18 0x37,0x60,0x2e,0x46 = c.ule.d $f12, $f14 0x37,0x30,0x07,0x46 = c.ule.s $f6, $f7 0x35,0x60,0x2e,0x46 = c.ult.d $f12, $f14 0x35,0x30,0x07,0x46 = c.ult.s $f6, $f7 0x31,0x60,0x2e,0x46 = c.un.d $f12, $f14 0x31,0x30,0x07,0x46 = c.un.s $f6, $f7 0xa1,0x39,0x00,0x46 = cvt.d.s $f6, $f7 0x21,0x73,0x80,0x46 = cvt.d.w $f12, $f14 0x20,0x73,0x20,0x46 = cvt.s.d $f12, $f14 0xa0,0x39,0x80,0x46 = cvt.s.w $f6, $f7 0x24,0x73,0x20,0x46 = cvt.w.d $f12, $f14 0xa4,0x39,0x00,0x46 = cvt.w.s $f6, $f7 0x00,0x00,0x46,0x44 = cfc1 $a2, $0 0x00,0xf8,0xca,0x44 = ctc1 $t2, $31 0x00,0x38,0x06,0x44 = mfc1 $a2, $f7 0x10,0x28,0x00,0x00 = mfhi $a1 0x12,0x28,0x00,0x00 = mflo $a1 0x86,0x41,0x20,0x46 = mov.d $f6, $f8 0x86,0x39,0x00,0x46 = mov.s $f6, $f7 0x00,0x38,0x86,0x44 = mtc1 $a2, $f7 0x11,0x00,0xe0,0x00 = mthi $a3 0x13,0x00,0xe0,0x00 = mtlo $a3 0xc6,0x23,0xe9,0xe4 = swc1 $f9, 9158($a3) 0x00,0x38,0x06,0x40 = mfc0 $a2, $a3, 0 0x00,0x40,0x89,0x40 = mtc0 $t1, $t0, 0 0x00,0x38,0x05,0x48 = mfc2 $a1, $a3, 0 0x00,0x20,0x89,0x48 = mtc2 $t1, $a0, 0 0x02,0x38,0x06,0x40 = mfc0 $a2, $a3, 2 0x03,0x40,0x89,0x40 = mtc0 $t1, $t0, 3 0x04,0x38,0x05,0x48 = mfc2 $a1, $a3, 4 0x05,0x20,0x89,0x48 = mtc2 $t1, $a0, 5 0x01,0x10,0x20,0x00 = movf $v0, $at, $fcc0 0x01,0x10,0x21,0x00 = movt $v0, $at, $fcc0 0x01,0x20,0xb1,0x00 = movt $a0, $a1, $fcc4 0x11,0x31,0x28,0x46 = movf.d $f4, $f6, $fcc2 0x11,0x31,0x14,0x46 = movf.s $f4, $f6, $fcc5 0x05,0x00,0xa6,0x4c = luxc1 $f0, $a2($a1) 0x0d,0x20,0xb8,0x4c = suxc1 $f4, $t8($a1) 0x00,0x05,0xcc,0x4d = lwxc1 $f20, $t4($t6) 0x08,0xd0,0xd2,0x4e = swxc1 $f26, $s2($s6) 0x00,0x20,0x71,0x44 = mfhc1 $s1, $f4 0x00,0x30,0xf1,0x44 = mthc1 $s1, $f6 0x10,0x00,0xa4,0xeb = swc2 $4, 16($sp) 0x10,0x00,0xa4,0xfb = sdc2 $4, 16($sp) 0x0c,0x00,0xeb,0xcb = lwc2 $11, 12($ra) 0x0c,0x00,0xeb,0xdb = ldc2 $11, 12($ra) capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-jump-instructions.s.cs000064400000000000000000000000450072674642500240150ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32, None capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-memory-instructions.s.cs000064400000000000000000000011770072674642500243610ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32, None 0x10,0x00,0xa4,0xa0 = sb $a0, 16($a1) 0x10,0x00,0xa4,0xe0 = sc $a0, 16($a1) 0x10,0x00,0xa4,0xa4 = sh $a0, 16($a1) 0x10,0x00,0xa4,0xac = sw $a0, 16($a1) 0x00,0x00,0xa7,0xac = sw $a3, ($a1) 0x10,0x00,0xa2,0xe4 = swc1 $f2, 16($a1) 0x10,0x00,0xa4,0xa8 = swl $a0, 16($a1) 0x04,0x00,0xa4,0x80 = lb $a0, 4($a1) 0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) 0x04,0x00,0xa4,0x90 = lbu $a0, 4($a1) 0x04,0x00,0xa4,0x84 = lh $a0, 4($a1) 0x04,0x00,0xa4,0x94 = lhu $a0, 4($a1) 0x04,0x00,0xa4,0xc0 = ll $a0, 4($a1) 0x04,0x00,0xa4,0x8c = lw $a0, 4($a1) 0x00,0x00,0xe7,0x8c = lw $a3, ($a3) 0x10,0x00,0xa2,0x8f = lw $v0, 16($sp) capstone-sys-0.15.0/capstone/suite/MC/Mips/mips-register-names.s.cs000064400000000000000000000025750072674642500232370ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x24,0x00,0x00,0x00 = addiu $zero, $zero, 0 0x24,0x01,0x00,0x00 = addiu $at, $zero, 0 0x24,0x02,0x00,0x00 = addiu $v0, $zero, 0 0x24,0x03,0x00,0x00 = addiu $v1, $zero, 0 0x24,0x04,0x00,0x00 = addiu $a0, $zero, 0 0x24,0x05,0x00,0x00 = addiu $a1, $zero, 0 0x24,0x06,0x00,0x00 = addiu $a2, $zero, 0 0x24,0x07,0x00,0x00 = addiu $a3, $zero, 0 0x24,0x08,0x00,0x00 = addiu $t0, $zero, 0 0x24,0x09,0x00,0x00 = addiu $t1, $zero, 0 0x24,0x0a,0x00,0x00 = addiu $t2, $zero, 0 0x24,0x0b,0x00,0x00 = addiu $t3, $zero, 0 0x24,0x0c,0x00,0x00 = addiu $t4, $zero, 0 0x24,0x0d,0x00,0x00 = addiu $t5, $zero, 0 0x24,0x0e,0x00,0x00 = addiu $t6, $zero, 0 0x24,0x0f,0x00,0x00 = addiu $t7, $zero, 0 0x24,0x10,0x00,0x00 = addiu $s0, $zero, 0 0x24,0x11,0x00,0x00 = addiu $s1, $zero, 0 0x24,0x12,0x00,0x00 = addiu $s2, $zero, 0 0x24,0x13,0x00,0x00 = addiu $s3, $zero, 0 0x24,0x14,0x00,0x00 = addiu $s4, $zero, 0 0x24,0x15,0x00,0x00 = addiu $s5, $zero, 0 0x24,0x16,0x00,0x00 = addiu $s6, $zero, 0 0x24,0x17,0x00,0x00 = addiu $s7, $zero, 0 0x24,0x18,0x00,0x00 = addiu $t8, $zero, 0 0x24,0x19,0x00,0x00 = addiu $t9, $zero, 0 0x24,0x1a,0x00,0x00 = addiu $k0, $zero, 0 0x24,0x1b,0x00,0x00 = addiu $k1, $zero, 0 0x24,0x1c,0x00,0x00 = addiu $gp, $zero, 0 0x24,0x1d,0x00,0x00 = addiu $sp, $zero, 0 0x24,0x1e,0x00,0x00 = addiu $fp, $zero, 0 // 0x24,0x1f,0x00,0x00 = addiu $sp, $zero, 0 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips64-alu-instructions.s.cs000064400000000000000000000035460072674642500240060ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS64, None 0x24,0x48,0xc7,0x00 = and $t1, $a2, $a3 0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 0x67,0x45,0xc9,0x30 = andi $t1, $a2, 17767 0x21,0x30,0xe6,0x70 = clo $a2, $a3 0x20,0x30,0xe6,0x70 = clz $a2, $a3 0x84,0x61,0x33,0x7d = ins $s3, $t1, 6, 7 0x27,0x48,0xc7,0x00 = nor $t1, $a2, $a3 0x25,0x18,0x65,0x00 = or $v1, $v1, $a1 0x67,0x45,0xa4,0x34 = ori $a0, $a1, 17767 0x67,0x45,0xc9,0x34 = ori $t1, $a2, 17767 0xc2,0x49,0x26,0x00 = rotr $t1, $a2, 7 0x46,0x48,0xe6,0x00 = rotrv $t1, $a2, $a3 0xc0,0x21,0x03,0x00 = sll $a0, $v1, 7 0x04,0x10,0xa3,0x00 = sllv $v0, $v1, $a1 0x2a,0x18,0x65,0x00 = slt $v1, $v1, $a1 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 0x67,0x00,0x63,0x28 = slti $v1, $v1, 103 0x67,0x00,0x63,0x2c = sltiu $v1, $v1, 103 0x2b,0x18,0x65,0x00 = sltu $v1, $v1, $a1 0xc3,0x21,0x03,0x00 = sra $a0, $v1, 7 0x07,0x10,0xa3,0x00 = srav $v0, $v1, $a1 0xc2,0x21,0x03,0x00 = srl $a0, $v1, 7 0x06,0x10,0xa3,0x00 = srlv $v0, $v1, $a1 0x26,0x18,0x65,0x00 = xor $v1, $v1, $a1 0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 0x67,0x45,0xc9,0x38 = xori $t1, $a2, 17767 0xa0,0x30,0x07,0x7c = wsbh $a2, $a3 0x27,0x38,0x00,0x01 = not $a3, $t0 0x2c,0x48,0xc7,0x00 = dadd $t1, $a2, $a3 0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 0x67,0x45,0xc9,0x60 = daddi $t1, $a2, 17767 0x67,0x45,0x29,0x61 = daddi $t1, $t1, 17767 0x67,0xc5,0xc9,0x64 = daddiu $t1, $a2, -15001 0x67,0xc5,0x29,0x65 = daddiu $t1, $t1, -15001 0x2d,0x48,0xc7,0x00 = daddu $t1, $a2, $a3 0x3a,0x4d,0x26,0x00 = drotr $t1, $a2, 20 // 0x3e,0x4d,0x26,0x00 = drotr32 $t1, $a2, 52 0x00,0x00,0xc7,0x70 = madd $a2, $a3 0x01,0x00,0xc7,0x70 = maddu $a2, $a3 0x04,0x00,0xc7,0x70 = msub $a2, $a3 0x05,0x00,0xc7,0x70 = msubu $a2, $a3 0x18,0x00,0x65,0x00 = mult $v1, $a1 0x19,0x00,0x65,0x00 = multu $v1, $a1 0x2f,0x20,0x65,0x00 = dsubu $a0, $v1, $a1 0x2d,0x38,0x00,0x01 = move $a3, $t0 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips64-instructions.s.cs000064400000000000000000000001710072674642500232160ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS64, None 0x81,0x00,0x42,0x4d = ldxc1 $f2, $v0($t2) 0x09,0x40,0x24,0x4f = sdxc1 $f8, $a0($t9) capstone-sys-0.15.0/capstone/suite/MC/Mips/mips64-register-names.s.cs000064400000000000000000000026640072674642500234100ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 0x64,0x00,0x00,0x00 = daddiu $zero, $zero, 0 0x64,0x01,0x00,0x00 = daddiu $at, $zero, 0 0x64,0x02,0x00,0x00 = daddiu $v0, $zero, 0 0x64,0x03,0x00,0x00 = daddiu $v1, $zero, 0 0x64,0x04,0x00,0x00 = daddiu $a0, $zero, 0 0x64,0x05,0x00,0x00 = daddiu $a1, $zero, 0 0x64,0x06,0x00,0x00 = daddiu $a2, $zero, 0 // 0x64,0x07,0x00,0x00 = daddiu $a2, $zero, 0 // 0x64,0x08,0x00,0x00 = daddiu $a4, $zero, 0 // 0x64,0x09,0x00,0x00 = daddiu $a5, $zero, 0 // 0x64,0x0a,0x00,0x00 = daddiu $a6, $zero, 0 // 0x64,0x0b,0x00,0x00 = daddiu $a7, $zero, 0 0x64,0x0c,0x00,0x00 = daddiu $t4, $zero, 0 0x64,0x0d,0x00,0x00 = daddiu $t5, $zero, 0 0x64,0x0e,0x00,0x00 = daddiu $t6, $zero, 0 0x64,0x0f,0x00,0x00 = daddiu $t7, $zero, 0 0x64,0x10,0x00,0x00 = daddiu $s0, $zero, 0 0x64,0x11,0x00,0x00 = daddiu $s1, $zero, 0 0x64,0x12,0x00,0x00 = daddiu $s2, $zero, 0 0x64,0x13,0x00,0x00 = daddiu $s3, $zero, 0 0x64,0x14,0x00,0x00 = daddiu $s4, $zero, 0 0x64,0x15,0x00,0x00 = daddiu $s5, $zero, 0 0x64,0x16,0x00,0x00 = daddiu $s6, $zero, 0 0x64,0x17,0x00,0x00 = daddiu $s7, $zero, 0 0x64,0x18,0x00,0x00 = daddiu $t8, $zero, 0 0x64,0x19,0x00,0x00 = daddiu $t9, $zero, 0 // 0x64,0x1a,0x00,0x00 = daddiu $kt0, $zero, 0 // 0x64,0x1b,0x00,0x00 = daddiu $kt1, $zero, 0 0x64,0x1c,0x00,0x00 = daddiu $gp, $zero, 0 0x64,0x1d,0x00,0x00 = daddiu $sp, $zero, 0 // 0x64,0x1e,0x00,0x00 = daddiu $s8, $zero, 0 0x64,0x1f,0x00,0x00 = daddiu $ra, $zero, 0 capstone-sys-0.15.0/capstone/suite/MC/Mips/mips_directives.s.cs000064400000000000000000000006100072674642500225210ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x10,0x00,0x01,0x4d = b 1336 0x08,0x00,0x01,0x4c = j 1328 0x0c,0x00,0x01,0x4c = jal 1328 0x10,0x00,0x01,0x4d = b 1336 0x00,0x00,0x00,0x00 = nop 0x08,0x00,0x01,0x4c = j 1328 0x00,0x00,0x00,0x00 = nop 0x0c,0x00,0x01,0x4c = jal 1328 0x00,0x00,0x00,0x00 = nop 0x46,0x00,0x39,0x85 = abs.s $f6, $f7 0x01,0xef,0x18,0x24 = and $v1, $t7, $t7 capstone-sys-0.15.0/capstone/suite/MC/Mips/nabi-regs.s.cs000064400000000000000000000007600072674642500212050ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None 0x02,0x04,0x80,0x20 = add $s0, $s0, $a0 0x02,0x06,0x80,0x20 = add $s0, $s0, $a2 0x02,0x07,0x80,0x20 = add $s0, $s0, $a3 0x02,0x08,0x80,0x20 = add $s0, $s0, $t0 0x02,0x09,0x80,0x20 = add $s0, $s0, $t1 0x02,0x0a,0x80,0x20 = add $s0, $s0, $t2 0x02,0x0b,0x80,0x20 = add $s0, $s0, $t3 0x02,0x0c,0x80,0x20 = add $s0, $s0, $t4 0x02,0x0d,0x80,0x20 = add $s0, $s0, $t5 0x02,0x0e,0x80,0x20 = add $s0, $s0, $t6 0x02,0x0f,0x80,0x20 = add $s0, $s0, $t7 capstone-sys-0.15.0/capstone/suite/MC/Mips/set-at-directive.s.cs000064400000000000000000000002660072674642500225100ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32, None 0x08,0x00,0x60,0x00 = jr $v1 0x08,0x00,0x80,0x03 = jr $gp 0x08,0x00,0xc0,0x03 = jr $fp 0x08,0x00,0xa0,0x03 = jr $sp 0x08,0x00,0xe0,0x03 = jr $ra capstone-sys-0.15.0/capstone/suite/MC/Mips/test_2r.s.cs000064400000000000000000000012050072674642500207130ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x7b,0x00,0x4f,0x9e = fill.b $w30, $t1 0x7b,0x01,0xbf,0xde = fill.h $w31, $s7 0x7b,0x02,0xc4,0x1e = fill.w $w16, $t8 0x7b,0x08,0x05,0x5e = nloc.b $w21, $w0 0x7b,0x09,0xfc,0x9e = nloc.h $w18, $w31 0x7b,0x0a,0xb8,0x9e = nloc.w $w2, $w23 0x7b,0x0b,0x51,0x1e = nloc.d $w4, $w10 0x7b,0x0c,0x17,0xde = nlzc.b $w31, $w2 0x7b,0x0d,0xb6,0xde = nlzc.h $w27, $w22 0x7b,0x0e,0xea,0x9e = nlzc.w $w10, $w29 0x7b,0x0f,0x4e,0x5e = nlzc.d $w25, $w9 0x7b,0x04,0x95,0x1e = pcnt.b $w20, $w18 0x7b,0x05,0x40,0x1e = pcnt.h $w0, $w8 0x7b,0x06,0x4d,0xde = pcnt.w $w23, $w9 0x7b,0x07,0xc5,0x5e = pcnt.d $w21, $w24 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_2rf.s.cs000064400000000000000000000025510072674642500210660ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12 0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17 0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0 0x7b,0x31,0xec,0x5e = fexupl.d $w17, $w29 0x7b,0x32,0x23,0x5e = fexupr.w $w13, $w4 0x7b,0x33,0x11,0x5e = fexupr.d $w5, $w2 0x7b,0x3c,0xed,0x1e = ffint_s.w $w20, $w29 0x7b,0x3d,0x7b,0x1e = ffint_s.d $w12, $w15 0x7b,0x3e,0xd9,0xde = ffint_u.w $w7, $w27 0x7b,0x3f,0x84,0xde = ffint_u.d $w19, $w16 0x7b,0x34,0x6f,0xde = ffql.w $w31, $w13 0x7b,0x35,0x6b,0x1e = ffql.d $w12, $w13 0x7b,0x36,0xf6,0xde = ffqr.w $w27, $w30 0x7b,0x37,0x7f,0x9e = ffqr.d $w30, $w15 0x7b,0x2e,0xfe,0x5e = flog2.w $w25, $w31 0x7b,0x2f,0x54,0x9e = flog2.d $w18, $w10 0x7b,0x2c,0x79,0xde = frint.w $w7, $w15 0x7b,0x2d,0xb5,0x5e = frint.d $w21, $w22 0x7b,0x2a,0x04,0xde = frcp.w $w19, $w0 0x7b,0x2b,0x71,0x1e = frcp.d $w4, $w14 0x7b,0x28,0x8b,0x1e = frsqrt.w $w12, $w17 0x7b,0x29,0x5d,0xde = frsqrt.d $w23, $w11 0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11 0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12 0x7b,0x38,0x2f,0x9e = ftint_s.w $w30, $w5 0x7b,0x39,0xb9,0x5e = ftint_s.d $w5, $w23 0x7b,0x3a,0x75,0x1e = ftint_u.w $w20, $w14 0x7b,0x3b,0xad,0xde = ftint_u.d $w23, $w21 0x7b,0x22,0x8f,0x5e = ftrunc_s.w $w29, $w17 0x7b,0x23,0xdb,0x1e = ftrunc_s.d $w12, $w27 0x7b,0x24,0x7c,0x5e = ftrunc_u.w $w17, $w15 0x7b,0x25,0xd9,0x5e = ftrunc_u.d $w5, $w27 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_3r.s.cs000064400000000000000000000257210072674642500207250ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4 0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31 0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22 0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0 0x78,0x93,0xc4,0xd0 = adds_a.b $w19, $w24, $w19 0x78,0xa4,0x36,0x50 = adds_a.h $w25, $w6, $w4 0x78,0xdb,0x8e,0x50 = adds_a.w $w25, $w17, $w27 0x78,0xfa,0x93,0xd0 = adds_a.d $w15, $w18, $w26 0x79,0x13,0x5f,0x50 = adds_s.b $w29, $w11, $w19 0x79,0x3a,0xb9,0x50 = adds_s.h $w5, $w23, $w26 0x79,0x4d,0x74,0x10 = adds_s.w $w16, $w14, $w13 0x79,0x7c,0x70,0x90 = adds_s.d $w2, $w14, $w28 0x79,0x8e,0x88,0xd0 = adds_u.b $w3, $w17, $w14 0x79,0xa4,0xf2,0x90 = adds_u.h $w10, $w30, $w4 0x79,0xd4,0x93,0xd0 = adds_u.w $w15, $w18, $w20 0x79,0xe9,0x57,0x90 = adds_u.d $w30, $w10, $w9 0x78,0x15,0xa6,0x0e = addv.b $w24, $w20, $w21 0x78,0x3b,0x69,0x0e = addv.h $w4, $w13, $w27 0x78,0x4e,0x5c,0xce = addv.w $w19, $w11, $w14 0x78,0x7f,0xa8,0x8e = addv.d $w2, $w21, $w31 0x7a,0x03,0x85,0xd1 = asub_s.b $w23, $w16, $w3 0x7a,0x39,0x8d,0x91 = asub_s.h $w22, $w17, $w25 0x7a,0x49,0x0e,0x11 = asub_s.w $w24, $w1, $w9 0x7a,0x6c,0x63,0x51 = asub_s.d $w13, $w12, $w12 0x7a,0x8b,0xea,0x91 = asub_u.b $w10, $w29, $w11 0x7a,0xaf,0x4c,0x91 = asub_u.h $w18, $w9, $w15 0x7a,0xdf,0x9a,0x91 = asub_u.w $w10, $w19, $w31 0x7a,0xe0,0x54,0x51 = asub_u.d $w17, $w10, $w0 0x7a,0x01,0x28,0x90 = ave_s.b $w2, $w5, $w1 0x7a,0x29,0x9c,0x10 = ave_s.h $w16, $w19, $w9 0x7a,0x45,0xfc,0x50 = ave_s.w $w17, $w31, $w5 0x7a,0x6a,0xce,0xd0 = ave_s.d $w27, $w25, $w10 0x7a,0x89,0x9c,0x10 = ave_u.b $w16, $w19, $w9 0x7a,0xab,0xe7,0x10 = ave_u.h $w28, $w28, $w11 0x7a,0xcb,0x62,0xd0 = ave_u.w $w11, $w12, $w11 0x7a,0xfc,0x9f,0x90 = ave_u.d $w30, $w19, $w28 0x7b,0x02,0x86,0x90 = aver_s.b $w26, $w16, $w2 0x7b,0x3b,0xdf,0xd0 = aver_s.h $w31, $w27, $w27 0x7b,0x59,0x97,0x10 = aver_s.w $w28, $w18, $w25 0x7b,0x7b,0xaf,0x50 = aver_s.d $w29, $w21, $w27 0x7b,0x83,0xd7,0x50 = aver_u.b $w29, $w26, $w3 0x7b,0xa9,0x94,0x90 = aver_u.h $w18, $w18, $w9 0x7b,0xdd,0xcc,0x50 = aver_u.w $w17, $w25, $w29 0x7b,0xf3,0xb5,0x90 = aver_u.d $w22, $w22, $w19 0x79,0x9d,0x78,0x8d = bclr.b $w2, $w15, $w29 0x79,0xbc,0xac,0x0d = bclr.h $w16, $w21, $w28 0x79,0xc9,0x14,0xcd = bclr.w $w19, $w2, $w9 0x79,0xe4,0xfe,0xcd = bclr.d $w27, $w31, $w4 0x7b,0x18,0x81,0x4d = binsl.b $w5, $w16, $w24 0x7b,0x2a,0x2f,0x8d = binsl.h $w30, $w5, $w10 0x7b,0x4d,0x7b,0x8d = binsl.w $w14, $w15, $w13 0x7b,0x6c,0xa5,0xcd = binsl.d $w23, $w20, $w12 0x7b,0x82,0x5d,0x8d = binsr.b $w22, $w11, $w2 0x7b,0xa6,0xd0,0x0d = binsr.h $w0, $w26, $w6 0x7b,0xdc,0x1e,0x8d = binsr.w $w26, $w3, $w28 0x7b,0xf5,0x00,0x0d = binsr.d $w0, $w0, $w21 0x7a,0x98,0x58,0x0d = bneg.b $w0, $w11, $w24 0x7a,0xa4,0x87,0x0d = bneg.h $w28, $w16, $w4 0x7a,0xd3,0xd0,0xcd = bneg.w $w3, $w26, $w19 0x7a,0xef,0xeb,0x4d = bneg.d $w13, $w29, $w15 0x7a,0x1f,0x2f,0xcd = bset.b $w31, $w5, $w31 0x7a,0x26,0x63,0x8d = bset.h $w14, $w12, $w6 0x7a,0x4c,0x4f,0xcd = bset.w $w31, $w9, $w12 0x7a,0x65,0xb1,0x4d = bset.d $w5, $w22, $w5 0x78,0x12,0xff,0xcf = ceq.b $w31, $w31, $w18 0x78,0x29,0xda,0x8f = ceq.h $w10, $w27, $w9 0x78,0x4e,0x2a,0x4f = ceq.w $w9, $w5, $w14 0x78,0x60,0x89,0x4f = ceq.d $w5, $w17, $w0 0x7a,0x09,0x25,0xcf = cle_s.b $w23, $w4, $w9 0x7a,0x33,0xdd,0x8f = cle_s.h $w22, $w27, $w19 0x7a,0x4a,0xd7,0x8f = cle_s.w $w30, $w26, $w10 0x7a,0x6a,0x2c,0x8f = cle_s.d $w18, $w5, $w10 0x7a,0x80,0xc8,0x4f = cle_u.b $w1, $w25, $w0 0x7a,0xbd,0x01,0xcf = cle_u.h $w7, $w0, $w29 0x7a,0xc1,0x96,0x4f = cle_u.w $w25, $w18, $w1 0x7a,0xfe,0x01,0x8f = cle_u.d $w6, $w0, $w30 0x79,0x15,0x16,0x4f = clt_s.b $w25, $w2, $w21 0x79,0x29,0x98,0x8f = clt_s.h $w2, $w19, $w9 0x79,0x50,0x45,0xcf = clt_s.w $w23, $w8, $w16 0x79,0x6c,0xf1,0xcf = clt_s.d $w7, $w30, $w12 0x79,0x8d,0xf8,0x8f = clt_u.b $w2, $w31, $w13 0x79,0xb7,0xfc,0x0f = clt_u.h $w16, $w31, $w23 0x79,0xc9,0xc0,0xcf = clt_u.w $w3, $w24, $w9 0x79,0xe1,0x01,0xcf = clt_u.d $w7, $w0, $w1 0x7a,0x12,0x1f,0x52 = div_s.b $w29, $w3, $w18 0x7a,0x2d,0x84,0x52 = div_s.h $w17, $w16, $w13 0x7a,0x5e,0xc9,0x12 = div_s.w $w4, $w25, $w30 0x7a,0x74,0x4f,0xd2 = div_s.d $w31, $w9, $w20 0x7a,0x8a,0xe9,0x92 = div_u.b $w6, $w29, $w10 0x7a,0xae,0xae,0x12 = div_u.h $w24, $w21, $w14 0x7a,0xd9,0x77,0x52 = div_u.w $w29, $w14, $w25 0x7a,0xf5,0x0f,0xd2 = div_u.d $w31, $w1, $w21 0x78,0x39,0xb5,0xd3 = dotp_s.h $w23, $w22, $w25 0x78,0x45,0x75,0x13 = dotp_s.w $w20, $w14, $w5 0x78,0x76,0x14,0x53 = dotp_s.d $w17, $w2, $w22 0x78,0xa6,0x13,0x53 = dotp_u.h $w13, $w2, $w6 0x78,0xd5,0xb3,0xd3 = dotp_u.w $w15, $w22, $w21 0x78,0xfa,0x81,0x13 = dotp_u.d $w4, $w16, $w26 0x79,0x36,0xe0,0x53 = dpadd_s.h $w1, $w28, $w22 0x79,0x4c,0x0a,0x93 = dpadd_s.w $w10, $w1, $w12 0x79,0x7b,0xa8,0xd3 = dpadd_s.d $w3, $w21, $w27 0x79,0xb4,0x2c,0x53 = dpadd_u.h $w17, $w5, $w20 0x79,0xd0,0x46,0x13 = dpadd_u.w $w24, $w8, $w16 0x79,0xf0,0xeb,0xd3 = dpadd_u.d $w15, $w29, $w16 0x7a,0x2c,0x59,0x13 = dpsub_s.h $w4, $w11, $w12 0x7a,0x46,0x39,0x13 = dpsub_s.w $w4, $w7, $w6 0x7a,0x7c,0x67,0xd3 = dpsub_s.d $w31, $w12, $w28 0x7a,0xb1,0xc9,0x13 = dpsub_u.h $w4, $w25, $w17 0x7a,0xd0,0xcc,0xd3 = dpsub_u.w $w19, $w25, $w16 0x7a,0xfa,0x51,0xd3 = dpsub_u.d $w7, $w10, $w26 0x7a,0x22,0xc7,0x15 = hadd_s.h $w28, $w24, $w2 0x7a,0x4b,0x8e,0x15 = hadd_s.w $w24, $w17, $w11 0x7a,0x74,0x7c,0x55 = hadd_s.d $w17, $w15, $w20 0x7a,0xb1,0xeb,0x15 = hadd_u.h $w12, $w29, $w17 0x7a,0xc6,0x2a,0x55 = hadd_u.w $w9, $w5, $w6 0x7a,0xe6,0xa0,0x55 = hadd_u.d $w1, $w20, $w6 0x7b,0x3d,0x74,0x15 = hsub_s.h $w16, $w14, $w29 0x7b,0x4b,0x6a,0x55 = hsub_s.w $w9, $w13, $w11 0x7b,0x6e,0x97,0x95 = hsub_s.d $w30, $w18, $w14 0x7b,0xae,0x61,0xd5 = hsub_u.h $w7, $w12, $w14 0x7b,0xc5,0x2d,0x55 = hsub_u.w $w21, $w5, $w5 0x7b,0xff,0x62,0xd5 = hsub_u.d $w11, $w12, $w31 0x7b,0x1e,0x84,0x94 = ilvev.b $w18, $w16, $w30 0x7b,0x2d,0x03,0x94 = ilvev.h $w14, $w0, $w13 0x7b,0x56,0xcb,0x14 = ilvev.w $w12, $w25, $w22 0x7b,0x63,0xdf,0x94 = ilvev.d $w30, $w27, $w3 0x7a,0x15,0x1f,0x54 = ilvl.b $w29, $w3, $w21 0x7a,0x31,0x56,0xd4 = ilvl.h $w27, $w10, $w17 0x7a,0x40,0x09,0x94 = ilvl.w $w6, $w1, $w0 0x7a,0x78,0x80,0xd4 = ilvl.d $w3, $w16, $w24 0x7b,0x94,0x2a,0xd4 = ilvod.b $w11, $w5, $w20 0x7b,0xbf,0x6c,0x94 = ilvod.h $w18, $w13, $w31 0x7b,0xd8,0x87,0x54 = ilvod.w $w29, $w16, $w24 0x7b,0xfd,0x65,0x94 = ilvod.d $w22, $w12, $w29 0x7a,0x86,0xf1,0x14 = ilvr.b $w4, $w30, $w6 0x7a,0xbd,0x9f,0x14 = ilvr.h $w28, $w19, $w29 0x7a,0xd5,0xa4,0x94 = ilvr.w $w18, $w20, $w21 0x7a,0xec,0xf5,0xd4 = ilvr.d $w23, $w30, $w12 0x78,0x9d,0xfc,0x52 = maddv.b $w17, $w31, $w29 0x78,0xa9,0xc1,0xd2 = maddv.h $w7, $w24, $w9 0x78,0xd4,0xb5,0x92 = maddv.w $w22, $w22, $w20 0x78,0xf4,0xd7,0x92 = maddv.d $w30, $w26, $w20 0x7b,0x17,0x5d,0xce = max_a.b $w23, $w11, $w23 0x7b,0x3e,0x2d,0x0e = max_a.h $w20, $w5, $w30 0x7b,0x5e,0x91,0xce = max_a.w $w7, $w18, $w30 0x7b,0x7f,0x42,0x0e = max_a.d $w8, $w8, $w31 0x79,0x13,0x0a,0x8e = max_s.b $w10, $w1, $w19 0x79,0x31,0xeb,0xce = max_s.h $w15, $w29, $w17 0x79,0x4e,0xeb,0xce = max_s.w $w15, $w29, $w14 0x79,0x63,0xc6,0x4e = max_s.d $w25, $w24, $w3 0x79,0x85,0xc3,0x0e = max_u.b $w12, $w24, $w5 0x79,0xa7,0x31,0x4e = max_u.h $w5, $w6, $w7 0x79,0xc7,0x24,0x0e = max_u.w $w16, $w4, $w7 0x79,0xf8,0x66,0x8e = max_u.d $w26, $w12, $w24 0x7b,0x81,0xd1,0x0e = min_a.b $w4, $w26, $w1 0x7b,0xbf,0x6b,0x0e = min_a.h $w12, $w13, $w31 0x7b,0xc0,0xa7,0x0e = min_a.w $w28, $w20, $w0 0x7b,0xf3,0xa3,0x0e = min_a.d $w12, $w20, $w19 0x7a,0x0e,0x1c,0xce = min_s.b $w19, $w3, $w14 0x7a,0x28,0xae,0xce = min_s.h $w27, $w21, $w8 0x7a,0x5e,0x70,0x0e = min_s.w $w0, $w14, $w30 0x7a,0x75,0x41,0x8e = min_s.d $w6, $w8, $w21 0x7a,0x88,0xd5,0x8e = min_u.b $w22, $w26, $w8 0x7a,0xac,0xd9,0xce = min_u.h $w7, $w27, $w12 0x7a,0xce,0xa2,0x0e = min_u.w $w8, $w20, $w14 0x7a,0xef,0x76,0x8e = min_u.d $w26, $w14, $w15 0x7b,0x1a,0x0c,0x92 = mod_s.b $w18, $w1, $w26 0x7b,0x3c,0xf7,0xd2 = mod_s.h $w31, $w30, $w28 0x7b,0x4d,0x30,0x92 = mod_s.w $w2, $w6, $w13 0x7b,0x76,0xdd,0x52 = mod_s.d $w21, $w27, $w22 0x7b,0x8d,0x3c,0x12 = mod_u.b $w16, $w7, $w13 0x7b,0xa7,0x46,0x12 = mod_u.h $w24, $w8, $w7 0x7b,0xd1,0x17,0x92 = mod_u.w $w30, $w2, $w17 0x7b,0xf9,0x17,0xd2 = mod_u.d $w31, $w2, $w25 0x79,0x0c,0x2b,0x92 = msubv.b $w14, $w5, $w12 0x79,0x3e,0x39,0x92 = msubv.h $w6, $w7, $w30 0x79,0x55,0x13,0x52 = msubv.w $w13, $w2, $w21 0x79,0x7b,0x74,0x12 = msubv.d $w16, $w14, $w27 0x78,0x0d,0x1d,0x12 = mulv.b $w20, $w3, $w13 0x78,0x2e,0xd6,0xd2 = mulv.h $w27, $w26, $w14 0x78,0x43,0xea,0x92 = mulv.w $w10, $w29, $w3 0x78,0x7d,0x99,0xd2 = mulv.d $w7, $w19, $w29 0x79,0x07,0xd9,0x54 = pckev.b $w5, $w27, $w7 0x79,0x3b,0x20,0x54 = pckev.h $w1, $w4, $w27 0x79,0x40,0xa7,0x94 = pckev.w $w30, $w20, $w0 0x79,0x6f,0x09,0x94 = pckev.d $w6, $w1, $w15 0x79,0x9e,0xe4,0x94 = pckod.b $w18, $w28, $w30 0x79,0xa8,0x2e,0x94 = pckod.h $w26, $w5, $w8 0x79,0xc2,0x22,0x54 = pckod.w $w9, $w4, $w2 0x79,0xf4,0xb7,0x94 = pckod.d $w30, $w22, $w20 0x78,0x0c,0xb9,0x54 = sld.b $w5, $w23[$t4] 0x78,0x23,0xb8,0x54 = sld.h $w1, $w23[$v1] 0x78,0x49,0x45,0x14 = sld.w $w20, $w8[$t1] 0x78,0x7e,0xb9,0xd4 = sld.d $w7, $w23[$fp] 0x78,0x11,0x00,0xcd = sll.b $w3, $w0, $w17 0x78,0x23,0xdc,0x4d = sll.h $w17, $w27, $w3 0x78,0x46,0x3c,0x0d = sll.w $w16, $w7, $w6 0x78,0x7a,0x02,0x4d = sll.d $w9, $w0, $w26 0x78,0x81,0x0f,0x14 = splat.b $w28, $w1[$at] 0x78,0xab,0x58,0x94 = splat.h $w2, $w11[$t3] 0x78,0xcb,0x05,0x94 = splat.w $w22, $w0[$t3] 0x78,0xe2,0x00,0x14 = splat.d $w0, $w0[$v0] 0x78,0x91,0x27,0x0d = sra.b $w28, $w4, $w17 0x78,0xa3,0x4b,0x4d = sra.h $w13, $w9, $w3 0x78,0xd3,0xae,0xcd = sra.w $w27, $w21, $w19 0x78,0xf7,0x47,0x8d = sra.d $w30, $w8, $w23 0x78,0x92,0x94,0xd5 = srar.b $w19, $w18, $w18 0x78,0xa8,0xb9,0xd5 = srar.h $w7, $w23, $w8 0x78,0xc2,0x60,0x55 = srar.w $w1, $w12, $w2 0x78,0xee,0x3d,0x55 = srar.d $w21, $w7, $w14 0x79,0x13,0x1b,0x0d = srl.b $w12, $w3, $w19 0x79,0x34,0xfd,0xcd = srl.h $w23, $w31, $w20 0x79,0x4b,0xdc,0x8d = srl.w $w18, $w27, $w11 0x79,0x7a,0x60,0xcd = srl.d $w3, $w12, $w26 0x79,0x0b,0xab,0xd5 = srlr.b $w15, $w21, $w11 0x79,0x33,0x6d,0x55 = srlr.h $w21, $w13, $w19 0x79,0x43,0xf1,0x95 = srlr.w $w6, $w30, $w3 0x79,0x6e,0x10,0x55 = srlr.d $w1, $w2, $w14 0x78,0x01,0x7e,0x51 = subs_s.b $w25, $w15, $w1 0x78,0x36,0xcf,0x11 = subs_s.h $w28, $w25, $w22 0x78,0x55,0x62,0x91 = subs_s.w $w10, $w12, $w21 0x78,0x72,0xa1,0x11 = subs_s.d $w4, $w20, $w18 0x78,0x99,0x35,0x51 = subs_u.b $w21, $w6, $w25 0x78,0xa7,0x50,0xd1 = subs_u.h $w3, $w10, $w7 0x78,0xca,0x7a,0x51 = subs_u.w $w9, $w15, $w10 0x78,0xea,0x99,0xd1 = subs_u.d $w7, $w19, $w10 0x79,0x0c,0x39,0x91 = subsus_u.b $w6, $w7, $w12 0x79,0x33,0xe9,0x91 = subsus_u.h $w6, $w29, $w19 0x79,0x47,0x79,0xd1 = subsus_u.w $w7, $w15, $w7 0x79,0x6f,0x1a,0x51 = subsus_u.d $w9, $w3, $w15 0x79,0x9f,0x1d,0x91 = subsuu_s.b $w22, $w3, $w31 0x79,0xb6,0xbc,0xd1 = subsuu_s.h $w19, $w23, $w22 0x79,0xcd,0x52,0x51 = subsuu_s.w $w9, $w10, $w13 0x79,0xe0,0x31,0x51 = subsuu_s.d $w5, $w6, $w0 0x78,0x93,0x69,0x8e = subv.b $w6, $w13, $w19 0x78,0xac,0xc9,0x0e = subv.h $w4, $w25, $w12 0x78,0xcb,0xde,0xce = subv.w $w27, $w27, $w11 0x78,0xea,0xc2,0x4e = subv.d $w9, $w24, $w10 0x78,0x05,0x80,0xd5 = vshf.b $w3, $w16, $w5 0x78,0x28,0x9d,0x15 = vshf.h $w20, $w19, $w8 0x78,0x59,0xf4,0x15 = vshf.w $w16, $w30, $w25 0x78,0x6f,0x5c,0xd5 = vshf.d $w19, $w11, $w15 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_3rf.s.cs000064400000000000000000000073530072674642500210740ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28 0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29 0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25 0x78,0x33,0x08,0x5a = fcaf.d $w1, $w1, $w19 0x78,0x90,0xb8,0x5a = fceq.w $w1, $w23, $w16 0x78,0xb0,0x40,0x1a = fceq.d $w0, $w8, $w16 0x79,0x98,0x4c,0x1a = fcle.w $w16, $w9, $w24 0x79,0xa1,0x76,0xda = fcle.d $w27, $w14, $w1 0x79,0x08,0x47,0x1a = fclt.w $w28, $w8, $w8 0x79,0x2b,0xcf,0x9a = fclt.d $w30, $w25, $w11 0x78,0xd7,0x90,0x9c = fcne.w $w2, $w18, $w23 0x78,0xef,0xa3,0x9c = fcne.d $w14, $w20, $w15 0x78,0x59,0x92,0x9c = fcor.w $w10, $w18, $w25 0x78,0x6b,0xcc,0x5c = fcor.d $w17, $w25, $w11 0x78,0xd5,0x13,0x9a = fcueq.w $w14, $w2, $w21 0x78,0xe7,0x1f,0x5a = fcueq.d $w29, $w3, $w7 0x79,0xc3,0x2c,0x5a = fcule.w $w17, $w5, $w3 0x79,0xfe,0x0f,0xda = fcule.d $w31, $w1, $w30 0x79,0x49,0xc9,0x9a = fcult.w $w6, $w25, $w9 0x79,0x71,0x46,0xda = fcult.d $w27, $w8, $w17 0x78,0x48,0xa1,0x1a = fcun.w $w4, $w20, $w8 0x78,0x63,0x5f,0x5a = fcun.d $w29, $w11, $w3 0x78,0x93,0x93,0x5c = fcune.w $w13, $w18, $w19 0x78,0xb5,0xd4,0x1c = fcune.d $w16, $w26, $w21 0x78,0xc2,0xc3,0x5b = fdiv.w $w13, $w24, $w2 0x78,0xf9,0x24,0xdb = fdiv.d $w19, $w4, $w25 0x7a,0x10,0x02,0x1b = fexdo.h $w8, $w0, $w16 0x7a,0x3b,0x68,0x1b = fexdo.w $w0, $w13, $w27 0x79,0xc3,0x04,0x5b = fexp2.w $w17, $w0, $w3 0x79,0xea,0x05,0x9b = fexp2.d $w22, $w0, $w10 0x79,0x17,0x37,0x5b = fmadd.w $w29, $w6, $w23 0x79,0x35,0xe2,0xdb = fmadd.d $w11, $w28, $w21 0x7b,0x8d,0xb8,0x1b = fmax.w $w0, $w23, $w13 0x7b,0xa8,0x96,0x9b = fmax.d $w26, $w18, $w8 0x7b,0xca,0x82,0x9b = fmax_a.w $w10, $w16, $w10 0x7b,0xf6,0x4f,0x9b = fmax_a.d $w30, $w9, $w22 0x7b,0x1e,0x0e,0x1b = fmin.w $w24, $w1, $w30 0x7b,0x2a,0xde,0xdb = fmin.d $w27, $w27, $w10 0x7b,0x54,0xea,0x9b = fmin_a.w $w10, $w29, $w20 0x7b,0x78,0xf3,0x5b = fmin_a.d $w13, $w30, $w24 0x79,0x40,0xcc,0x5b = fmsub.w $w17, $w25, $w0 0x79,0x70,0x92,0x1b = fmsub.d $w8, $w18, $w16 0x78,0x8f,0x78,0xdb = fmul.w $w3, $w15, $w15 0x78,0xaa,0xf2,0x5b = fmul.d $w9, $w30, $w10 0x7a,0x0a,0x2e,0x5a = fsaf.w $w25, $w5, $w10 0x7a,0x3d,0x1e,0x5a = fsaf.d $w25, $w3, $w29 0x7a,0x8d,0x8a,0xda = fseq.w $w11, $w17, $w13 0x7a,0xbf,0x07,0x5a = fseq.d $w29, $w0, $w31 0x7b,0x9f,0xff,0x9a = fsle.w $w30, $w31, $w31 0x7b,0xb8,0xbc,0x9a = fsle.d $w18, $w23, $w24 0x7b,0x06,0x2b,0x1a = fslt.w $w12, $w5, $w6 0x7b,0x35,0xd4,0x1a = fslt.d $w16, $w26, $w21 0x7a,0xcc,0x0f,0x9c = fsne.w $w30, $w1, $w12 0x7a,0xf7,0x6b,0x9c = fsne.d $w14, $w13, $w23 0x7a,0x5b,0x6e,0xdc = fsor.w $w27, $w13, $w27 0x7a,0x6b,0xc3,0x1c = fsor.d $w12, $w24, $w11 0x78,0x41,0xd7,0xdb = fsub.w $w31, $w26, $w1 0x78,0x7b,0x8c,0xdb = fsub.d $w19, $w17, $w27 0x7a,0xd9,0xc4,0x1a = fsueq.w $w16, $w24, $w25 0x7a,0xee,0x74,0x9a = fsueq.d $w18, $w14, $w14 0x7b,0xcd,0xf5,0xda = fsule.w $w23, $w30, $w13 0x7b,0xfa,0x58,0x9a = fsule.d $w2, $w11, $w26 0x7b,0x56,0xd2,0xda = fsult.w $w11, $w26, $w22 0x7b,0x7e,0xb9,0x9a = fsult.d $w6, $w23, $w30 0x7a,0x5c,0x90,0xda = fsun.w $w3, $w18, $w28 0x7a,0x73,0x5c,0x9a = fsun.d $w18, $w11, $w19 0x7a,0x82,0xfc,0x1c = fsune.w $w16, $w31, $w2 0x7a,0xb1,0xd0,0xdc = fsune.d $w3, $w26, $w17 0x7a,0x98,0x24,0x1b = ftq.h $w16, $w4, $w24 0x7a,0xb9,0x29,0x5b = ftq.w $w5, $w5, $w25 0x79,0x4a,0xa4,0x1c = madd_q.h $w16, $w20, $w10 0x79,0x69,0x17,0x1c = madd_q.w $w28, $w2, $w9 0x7b,0x49,0x92,0x1c = maddr_q.h $w8, $w18, $w9 0x7b,0x70,0x67,0x5c = maddr_q.w $w29, $w12, $w16 0x79,0x8a,0xd6,0x1c = msub_q.h $w24, $w26, $w10 0x79,0xbc,0xf3,0x5c = msub_q.w $w13, $w30, $w28 0x7b,0x8b,0xab,0x1c = msubr_q.h $w12, $w21, $w11 0x7b,0xb4,0x70,0x5c = msubr_q.w $w1, $w14, $w20 0x79,0x1e,0x81,0x9c = mul_q.h $w6, $w16, $w30 0x79,0x24,0x0c,0x1c = mul_q.w $w16, $w1, $w4 0x7b,0x13,0xa1,0x9c = mulr_q.h $w6, $w20, $w19 0x7b,0x34,0x0e,0xdc = mulr_q.w $w27, $w1, $w20 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_bit.s.cs000064400000000000000000000041320072674642500211500ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2 0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0 0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3 0x79,0x80,0x5a,0x49 = bclri.d $w9, $w11, 0 0x7b,0x71,0x66,0x49 = binsli.b $w25, $w12, 1 0x7b,0x60,0xb5,0x49 = binsli.h $w21, $w22, 0 0x7b,0x40,0x25,0x89 = binsli.w $w22, $w4, 0 0x7b,0x06,0x11,0x89 = binsli.d $w6, $w2, 6 0x7b,0xf0,0x9b,0xc9 = binsri.b $w15, $w19, 0 0x7b,0xe1,0xf2,0x09 = binsri.h $w8, $w30, 1 0x7b,0xc5,0x98,0x89 = binsri.w $w2, $w19, 5 0x7b,0x81,0xa4,0x89 = binsri.d $w18, $w20, 1 0x7a,0xf0,0x9e,0x09 = bnegi.b $w24, $w19, 0 0x7a,0xe3,0x5f,0x09 = bnegi.h $w28, $w11, 3 0x7a,0xc5,0xd8,0x49 = bnegi.w $w1, $w27, 5 0x7a,0x81,0xa9,0x09 = bnegi.d $w4, $w21, 1 0x7a,0x70,0x44,0x89 = bseti.b $w18, $w8, 0 0x7a,0x62,0x76,0x09 = bseti.h $w24, $w14, 2 0x7a,0x44,0x92,0x49 = bseti.w $w9, $w18, 4 0x7a,0x01,0x79,0xc9 = bseti.d $w7, $w15, 1 0x78,0x72,0xff,0xca = sat_s.b $w31, $w31, 2 0x78,0x60,0x9c,0xca = sat_s.h $w19, $w19, 0 0x78,0x40,0xec,0xca = sat_s.w $w19, $w29, 0 0x78,0x00,0xb2,0xca = sat_s.d $w11, $w22, 0 0x78,0xf3,0x68,0x4a = sat_u.b $w1, $w13, 3 0x78,0xe4,0xc7,0x8a = sat_u.h $w30, $w24, 4 0x78,0xc0,0x6f,0xca = sat_u.w $w31, $w13, 0 0x78,0x85,0x87,0x4a = sat_u.d $w29, $w16, 5 0x78,0x71,0x55,0xc9 = slli.b $w23, $w10, 1 0x78,0x61,0x92,0x49 = slli.h $w9, $w18, 1 0x78,0x44,0xea,0xc9 = slli.w $w11, $w29, 4 0x78,0x01,0xa6,0x49 = slli.d $w25, $w20, 1 0x78,0xf1,0xee,0x09 = srai.b $w24, $w29, 1 0x78,0xe0,0x30,0x49 = srai.h $w1, $w6, 0 0x78,0xc1,0xd1,0xc9 = srai.w $w7, $w26, 1 0x78,0x83,0xcd,0x09 = srai.d $w20, $w25, 3 0x79,0x70,0xc9,0x4a = srari.b $w5, $w25, 0 0x79,0x64,0x31,0xca = srari.h $w7, $w6, 4 0x79,0x45,0x5c,0x4a = srari.w $w17, $w11, 5 0x79,0x05,0xcd,0x4a = srari.d $w21, $w25, 5 0x79,0x72,0x00,0x89 = srli.b $w2, $w0, 2 0x79,0x62,0xff,0xc9 = srli.h $w31, $w31, 2 0x79,0x44,0x49,0x49 = srli.w $w5, $w9, 4 0x79,0x05,0xd6,0xc9 = srli.d $w27, $w26, 5 0x79,0xf0,0x1c,0x8a = srlri.b $w18, $w3, 0 0x79,0xe3,0x10,0x4a = srlri.h $w1, $w2, 3 0x79,0xc2,0xb2,0xca = srlri.w $w11, $w22, 2 0x79,0x86,0x56,0x0a = srlri.d $w24, $w10, 6 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_cbranch.s.cs000064400000000000000000000006770072674642500220040ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None // 0x47,0x80,0x00,0x01 = bnz.b $w0, 4 // 0x47,0xa1,0x00,0x04 = bnz.h $w1, 16 // 0x47,0xc2,0x00,0x20 = bnz.w $w2, 128 // 0x47,0xe3,0xff,0xe0 = bnz.d $w3, -128 // 0x45,0xe0,0x00,0x01 = bnz.v $w0, 4 // 0x47,0x00,0x00,0x20 = bz.b $w0, 128 // 0x47,0x21,0x00,0x40 = bz.h $w1, 256 // 0x47,0x42,0x00,0x80 = bz.w $w2, 512 // 0x47,0x63,0xff,0x00 = bz.d $w3, -1024 // 0x45,0x60,0x00,0x01 = bz.v $w0, 4 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_ctrlregs.s.cs000064400000000000000000000023300072674642500222150ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 0x78,0x7e,0x00,0x59 = cfcmsa $at, $0 0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 0x78,0x7e,0x08,0x99 = cfcmsa $v0, $1 0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 0x78,0x7e,0x10,0xd9 = cfcmsa $v1, $2 0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 0x78,0x7e,0x19,0x19 = cfcmsa $a0, $3 0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 0x78,0x7e,0x21,0x59 = cfcmsa $a1, $4 0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 0x78,0x7e,0x29,0x99 = cfcmsa $a2, $5 0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 0x78,0x7e,0x31,0xd9 = cfcmsa $a3, $6 0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 0x78,0x7e,0x3a,0x19 = cfcmsa $t0, $7 0x78,0x3e,0x08,0x19 = ctcmsa $0, $at 0x78,0x3e,0x08,0x19 = ctcmsa $0, $at 0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 0x78,0x3e,0x10,0x59 = ctcmsa $1, $v0 0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 0x78,0x3e,0x18,0x99 = ctcmsa $2, $v1 0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 0x78,0x3e,0x20,0xd9 = ctcmsa $3, $a0 0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 0x78,0x3e,0x29,0x19 = ctcmsa $4, $a1 0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 0x78,0x3e,0x31,0x59 = ctcmsa $5, $a2 0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 0x78,0x3e,0x39,0x99 = ctcmsa $6, $a3 0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 0x78,0x3e,0x41,0xd9 = ctcmsa $7, $t0 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_elm.s.cs000064400000000000000000000013000072674642500211410ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x82,0x43,0x59 = copy_s.b $t5, $w8[2] 0x78,0xa0,0xc8,0x59 = copy_s.h $at, $w25[0] 0x78,0xb1,0x2d,0x99 = copy_s.w $s6, $w5[1] 0x78,0xc4,0xa5,0x99 = copy_u.b $s6, $w20[4] 0x78,0xe0,0x25,0x19 = copy_u.h $s4, $w4[0] 0x78,0xf2,0x6f,0x99 = copy_u.w $fp, $w13[2] 0x78,0x04,0xe8,0x19 = sldi.b $w0, $w29[4] 0x78,0x20,0x8a,0x19 = sldi.h $w8, $w17[0] 0x78,0x32,0xdd,0x19 = sldi.w $w20, $w27[2] 0x78,0x38,0x61,0x19 = sldi.d $w4, $w12[0] 0x78,0x42,0x1e,0x59 = splati.b $w25, $w3[2] 0x78,0x61,0xe6,0x19 = splati.h $w24, $w28[1] 0x78,0x70,0x93,0x59 = splati.w $w13, $w18[0] 0x78,0x78,0x0f,0x19 = splati.d $w28, $w1[0] 0x78,0xbe,0xc5,0xd9 = move.v $w23, $w24 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_elm_insert.s.cs000064400000000000000000000002730072674642500225350ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp 0x79,0x22,0x2d,0x19 = insert.h $w20[2], $a1 0x79,0x32,0x7a,0x19 = insert.w $w8[2], $t7 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_elm_insve.s.cs000064400000000000000000000003600072674642500223520ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0] 0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0] 0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0] 0x79,0x78,0x90,0xd9 = insve.d $w3[0], $w18[0] capstone-sys-0.15.0/capstone/suite/MC/Mips/test_i10.s.cs000064400000000000000000000003230072674642500207610ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x7b,0x06,0x32,0x07 = ldi.b $w8, 198 0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313 0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492 // 0x7b,0x7a,0x66,0xc7 = ldi.d $w27, -180 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_i5.s.cs000064400000000000000000000040300072674642500207040ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30 0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26 0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26 0x78,0x75,0x0c,0x06 = addvi.d $w16, $w1, 21 // 0x78,0x18,0xae,0x07 = ceqi.b $w24, $w21, -8 0x78,0x22,0x7f,0xc7 = ceqi.h $w31, $w15, 2 // 0x78,0x5f,0x0b,0x07 = ceqi.w $w12, $w1, -1 0x78,0x67,0xb6,0x07 = ceqi.d $w24, $w22, 7 0x7a,0x01,0x83,0x07 = clei_s.b $w12, $w16, 1 // 0x7a,0x37,0x50,0x87 = clei_s.h $w2, $w10, -9 // 0x7a,0x56,0x59,0x07 = clei_s.w $w4, $w11, -10 // 0x7a,0x76,0xe8,0x07 = clei_s.d $w0, $w29, -10 0x7a,0x83,0x8d,0x47 = clei_u.b $w21, $w17, 3 0x7a,0xb1,0x3f,0x47 = clei_u.h $w29, $w7, 17 0x7a,0xc2,0x08,0x47 = clei_u.w $w1, $w1, 2 0x7a,0xfd,0xde,0xc7 = clei_u.d $w27, $w27, 29 // 0x79,0x19,0x6c,0xc7 = clti_s.b $w19, $w13, -7 // 0x79,0x34,0x53,0xc7 = clti_s.h $w15, $w10, -12 0x79,0x4b,0x63,0x07 = clti_s.w $w12, $w12, 11 // 0x79,0x71,0xa7,0x47 = clti_s.d $w29, $w20, -15 0x79,0x9d,0x4b,0x87 = clti_u.b $w14, $w9, 29 0x79,0xb9,0xce,0x07 = clti_u.h $w24, $w25, 25 0x79,0xd6,0x08,0x47 = clti_u.w $w1, $w1, 22 0x79,0xe1,0xcd,0x47 = clti_u.d $w21, $w25, 1 0x79,0x01,0xad,0x86 = maxi_s.b $w22, $w21, 1 // 0x79,0x38,0x2f,0x46 = maxi_s.h $w29, $w5, -8 // 0x79,0x54,0x50,0x46 = maxi_s.w $w1, $w10, -12 // 0x79,0x70,0xeb,0x46 = maxi_s.d $w13, $w29, -16 0x79,0x8c,0x05,0x06 = maxi_u.b $w20, $w0, 12 0x79,0xa3,0x70,0x46 = maxi_u.h $w1, $w14, 3 0x79,0xcb,0xb6,0xc6 = maxi_u.w $w27, $w22, 11 0x79,0xe4,0x36,0x86 = maxi_u.d $w26, $w6, 4 0x7a,0x01,0x09,0x06 = mini_s.b $w4, $w1, 1 // 0x7a,0x37,0xde,0xc6 = mini_s.h $w27, $w27, -9 0x7a,0x49,0x5f,0x06 = mini_s.w $w28, $w11, 9 0x7a,0x6a,0x52,0xc6 = mini_s.d $w11, $w10, 10 0x7a,0x9b,0xbc,0x86 = mini_u.b $w18, $w23, 27 0x7a,0xb2,0xd1,0xc6 = mini_u.h $w7, $w26, 18 0x7a,0xda,0x62,0xc6 = mini_u.w $w11, $w12, 26 0x7a,0xe2,0x7a,0xc6 = mini_u.d $w11, $w15, 2 0x78,0x93,0xa6,0x06 = subvi.b $w24, $w20, 19 0x78,0xa4,0x9a,0xc6 = subvi.h $w11, $w19, 4 0x78,0xcb,0x53,0x06 = subvi.w $w12, $w10, 11 0x78,0xe7,0x84,0xc6 = subvi.d $w19, $w16, 7 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_i8.s.cs000064400000000000000000000007530072674642500207170ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48 0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126 0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88 0x7a,0xbd,0x1f,0x41 = bseli.b $w29, $w3, 189 0x7a,0x38,0x88,0x40 = nori.b $w1, $w17, 56 0x79,0x87,0xa6,0x80 = ori.b $w26, $w20, 135 0x78,0x69,0xf4,0xc2 = shf.b $w19, $w30, 105 0x79,0x4c,0x44,0x42 = shf.h $w17, $w8, 76 0x7a,0x5d,0x1b,0x82 = shf.w $w14, $w3, 93 0x7b,0x14,0x54,0x00 = xori.b $w16, $w10, 20 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_lsa.s.cs000064400000000000000000000003440072674642500211520ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x01,0x2a,0x40,0x05 = lsa $t0, $t1, $t2, 1 0x01,0x2a,0x40,0x45 = lsa $t0, $t1, $t2, 2 0x01,0x2a,0x40,0x85 = lsa $t0, $t1, $t2, 3 0x01,0x2a,0x40,0xc5 = lsa $t0, $t1, $t2, 4 capstone-sys-0.15.0/capstone/suite/MC/Mips/test_mi10.s.cs000064400000000000000000000020010072674642500211310ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x7a,0x00,0x08,0x20 = ld.b $w0, -512($at) 0x78,0x00,0x10,0x60 = ld.b $w1, ($v0) 0x79,0xff,0x18,0xa0 = ld.b $w2, 511($v1) 0x7a,0x00,0x20,0xe1 = ld.h $w3, -1024($a0) 0x7b,0x00,0x29,0x21 = ld.h $w4, -512($a1) 0x78,0x00,0x31,0x61 = ld.h $w5, ($a2) 0x79,0x00,0x39,0xa1 = ld.h $w6, 512($a3) 0x79,0xff,0x41,0xe1 = ld.h $w7, 1022($t0) 0x7a,0x00,0x4a,0x22 = ld.w $w8, -2048($t1) 0x7b,0x00,0x52,0x62 = ld.w $w9, -1024($t2) 0x7b,0x80,0x5a,0xa2 = ld.w $w10, -512($t3) 0x78,0x80,0x62,0xe2 = ld.w $w11, 512($t4) 0x79,0x00,0x6b,0x22 = ld.w $w12, 1024($t5) 0x79,0xff,0x73,0x62 = ld.w $w13, 2044($t6) 0x7a,0x00,0x7b,0xa3 = ld.d $w14, -4096($t7) 0x7b,0x00,0x83,0xe3 = ld.d $w15, -2048($s0) 0x7b,0x80,0x8c,0x23 = ld.d $w16, -1024($s1) 0x7b,0xc0,0x94,0x63 = ld.d $w17, -512($s2) 0x78,0x00,0x9c,0xa3 = ld.d $w18, ($s3) 0x78,0x40,0xa4,0xe3 = ld.d $w19, 512($s4) 0x78,0x80,0xad,0x23 = ld.d $w20, 1024($s5) 0x79,0x00,0xb5,0x63 = ld.d $w21, 2048($s6) 0x79,0xff,0xbd,0xa3 = ld.d $w22, 4088($s7) capstone-sys-0.15.0/capstone/suite/MC/Mips/test_vec.s.cs000064400000000000000000000005530072674642500211520ustar 00000000000000# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None 0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27 0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7 0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9 0x78,0xce,0x02,0x1e = bsel.v $w8, $w0, $w14 0x78,0x40,0xf9,0xde = nor.v $w7, $w31, $w0 0x78,0x3e,0xd6,0x1e = or.v $w24, $w26, $w30 0x78,0x6f,0xd9,0xde = xor.v $w7, $w27, $w15 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-encoding-bookII.s.cs000064400000000000000000000014560072674642500236420ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 0x7c,0x02,0x1f,0xac = icbi 2, 3 0x7c,0x02,0x1a,0x2c = dcbt 2, 3 0x7c,0x02,0x19,0xec = dcbtst 2, 3 0x7c,0x02,0x1f,0xec = dcbz 2, 3 0x7c,0x02,0x18,0x6c = dcbst 2, 3 0x4c,0x00,0x01,0x2c = isync 0x7c,0x43,0x21,0x2d = stwcx. 2, 3, 4 0x7c,0x43,0x21,0xad = stdcx. 2, 3, 4 // 0x7c,0x40,0x04,0xac = sync 2 0x7c,0x00,0x06,0xac = eieio // 0x7c,0x40,0x00,0x7c = wait 2 0x7c,0x02,0x18,0xac = dcbf 2, 3 0x7c,0x43,0x20,0x28 = lwarx 2, 3, 4 0x7c,0x43,0x20,0xa8 = ldarx 2, 3, 4 0x7c,0x00,0x04,0xac = sync // 0x7c,0x20,0x04,0xac = sync 1 // 0x7c,0x40,0x04,0xac = sync 2 // 0x7c,0x00,0x00,0x7c = wait 0 // 0x7c,0x20,0x00,0x7c = wait 1 // 0x7c,0x40,0x00,0x7c = wait 2 0x7c,0x5b,0x1a,0xe6 = mftb 2, 123 0x7c,0x4c,0x42,0xe6 = mftb 2, 268 // 0x7c,0x4d,0x42,0xe6 = mftb 2, 269 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-encoding-bookIII.s.cs000064400000000000000000000023030072674642500237430ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME // 0x7c,0x80,0x01,0x24 = mtmsr 4, 0 0x7c,0x81,0x01,0x24 = mtmsr 4, 1 0x7c,0x80,0x00,0xa6 = mfmsr 4 // 0x7c,0x80,0x01,0x64 = mtmsrd 4, 0 0x7c,0x81,0x01,0x64 = mtmsrd 4, 1 0x7c,0x90,0x42,0xa6 = mfspr 4, 272 0x7c,0x91,0x42,0xa6 = mfspr 4, 273 0x7c,0x92,0x42,0xa6 = mfspr 4, 274 0x7c,0x93,0x42,0xa6 = mfspr 4, 275 0x7c,0x90,0x43,0xa6 = mtspr 272, 4 0x7c,0x91,0x43,0xa6 = mtspr 273, 4 0x7c,0x92,0x43,0xa6 = mtspr 274, 4 0x7c,0x93,0x43,0xa6 = mtspr 275, 4 0x7c,0x90,0x43,0xa6 = mtspr 272, 4 0x7c,0x91,0x43,0xa6 = mtspr 273, 4 0x7c,0x92,0x43,0xa6 = mtspr 274, 4 0x7c,0x93,0x43,0xa6 = mtspr 275, 4 0x7c,0x98,0x43,0xa6 = mtspr 280, 4 0x7c,0x96,0x02,0xa6 = mfspr 4, 22 0x7c,0x96,0x03,0xa6 = mtspr 22, 4 // 0x7c,0x9f,0x42,0xa6 = mfspr 4, 287 0x7c,0x99,0x02,0xa6 = mfspr 4, 25 0x7c,0x99,0x03,0xa6 = mtspr 25, 4 0x7c,0x9a,0x02,0xa6 = mfspr 4, 26 0x7c,0x9a,0x03,0xa6 = mtspr 26, 4 0x7c,0x9b,0x02,0xa6 = mfspr 4, 27 0x7c,0x9b,0x03,0xa6 = mtspr 27, 4 0x7c,0x00,0x23,0x64 = slbie 4 0x7c,0x80,0x2b,0x24 = slbmte 4, 5 0x7c,0x80,0x2f,0x26 = slbmfee 4, 5 0x7c,0x00,0x03,0xe4 = slbia 0x7c,0x00,0x04,0x6c = tlbsync 0x7c,0x00,0x22,0x24 = tlbiel 4 // 0x7c,0x00,0x22,0x64 = tlbie 4,0 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-encoding-ext.s.cs000064400000000000000000000456220072674642500232710ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME // 0x4d,0x82,0x00,0x20 = beqlr 0 // 0x4d,0x86,0x00,0x20 = beqlr 1 // 0x4d,0x8a,0x00,0x20 = beqlr 2 // 0x4d,0x8e,0x00,0x20 = beqlr 3 // 0x4d,0x92,0x00,0x20 = beqlr 4 // 0x4d,0x96,0x00,0x20 = beqlr 5 // 0x4d,0x9a,0x00,0x20 = beqlr 6 // 0x4d,0x9e,0x00,0x20 = beqlr 7 // 0x4d,0x80,0x00,0x20 = bclr 12, 0, 0 // 0x4d,0x81,0x00,0x20 = bclr 12, 1, 0 // 0x4d,0x82,0x00,0x20 = bclr 12, 2, 0 // 0x4d,0x83,0x00,0x20 = bclr 12, 3, 0 // 0x4d,0x83,0x00,0x20 = bclr 12, 3, 0 // 0x4d,0x84,0x00,0x20 = bclr 12, 4, 0 // 0x4d,0x85,0x00,0x20 = bclr 12, 5, 0 // 0x4d,0x86,0x00,0x20 = bclr 12, 6, 0 // 0x4d,0x87,0x00,0x20 = bclr 12, 7, 0 // 0x4d,0x87,0x00,0x20 = bclr 12, 7, 0 // 0x4d,0x88,0x00,0x20 = bclr 12, 8, 0 // 0x4d,0x89,0x00,0x20 = bclr 12, 9, 0 // 0x4d,0x8a,0x00,0x20 = bclr 12, 10, 0 // 0x4d,0x8b,0x00,0x20 = bclr 12, 11, 0 // 0x4d,0x8b,0x00,0x20 = bclr 12, 11, 0 // 0x4d,0x8c,0x00,0x20 = bclr 12, 12, 0 // 0x4d,0x8d,0x00,0x20 = bclr 12, 13, 0 // 0x4d,0x8e,0x00,0x20 = bclr 12, 14, 0 // 0x4d,0x8f,0x00,0x20 = bclr 12, 15, 0 // 0x4d,0x8f,0x00,0x20 = bclr 12, 15, 0 // 0x4d,0x90,0x00,0x20 = bclr 12, 16, 0 // 0x4d,0x91,0x00,0x20 = bclr 12, 17, 0 // 0x4d,0x92,0x00,0x20 = bclr 12, 18, 0 // 0x4d,0x93,0x00,0x20 = bclr 12, 19, 0 // 0x4d,0x93,0x00,0x20 = bclr 12, 19, 0 // 0x4d,0x94,0x00,0x20 = bclr 12, 20, 0 // 0x4d,0x95,0x00,0x20 = bclr 12, 21, 0 // 0x4d,0x96,0x00,0x20 = bclr 12, 22, 0 // 0x4d,0x97,0x00,0x20 = bclr 12, 23, 0 // 0x4d,0x97,0x00,0x20 = bclr 12, 23, 0 // 0x4d,0x98,0x00,0x20 = bclr 12, 24, 0 // 0x4d,0x99,0x00,0x20 = bclr 12, 25, 0 // 0x4d,0x9a,0x00,0x20 = bclr 12, 26, 0 // 0x4d,0x9b,0x00,0x20 = bclr 12, 27, 0 // 0x4d,0x9b,0x00,0x20 = bclr 12, 27, 0 // 0x4d,0x9c,0x00,0x20 = bclr 12, 28, 0 // 0x4d,0x9d,0x00,0x20 = bclr 12, 29, 0 // 0x4d,0x9e,0x00,0x20 = bclr 12, 30, 0 // 0x4d,0x9f,0x00,0x20 = bclr 12, 31, 0 // 0x4d,0x9f,0x00,0x20 = bclr 12, 31, 0 0x4e,0x80,0x00,0x20 = blr 0x4e,0x80,0x04,0x20 = bctr 0x4e,0x80,0x00,0x21 = blrl 0x4e,0x80,0x04,0x21 = bctrl // 0x4d,0x82,0x00,0x20 = bclr 12, 2, 0 // 0x4d,0x82,0x04,0x20 = bcctr 12, 2, 0 // 0x4d,0x82,0x00,0x21 = bclrl 12, 2, 0 // 0x4d,0x82,0x04,0x21 = bcctrl 12, 2, 0 // 0x4d,0xe2,0x00,0x20 = bclr 15, 2, 0 // 0x4d,0xe2,0x04,0x20 = bcctr 15, 2, 0 // 0x4d,0xe2,0x00,0x21 = bclrl 15, 2, 0 // 0x4d,0xe2,0x04,0x21 = bcctrl 15, 2, 0 // 0x4d,0xc2,0x00,0x20 = bclr 14, 2, 0 // 0x4d,0xc2,0x04,0x20 = bcctr 14, 2, 0 // 0x4d,0xc2,0x00,0x21 = bclrl 14, 2, 0 // 0x4d,0xc2,0x04,0x21 = bcctrl 14, 2, 0 // 0x4c,0x82,0x00,0x20 = bclr 4, 2, 0 // 0x4c,0x82,0x04,0x20 = bcctr 4, 2, 0 // 0x4c,0x82,0x00,0x21 = bclrl 4, 2, 0 // 0x4c,0x82,0x04,0x21 = bcctrl 4, 2, 0 // 0x4c,0xe2,0x00,0x20 = bclr 7, 2, 0 // 0x4c,0xe2,0x04,0x20 = bcctr 7, 2, 0 // 0x4c,0xe2,0x00,0x21 = bclrl 7, 2, 0 // 0x4c,0xe2,0x04,0x21 = bcctrl 7, 2, 0 // 0x4c,0xc2,0x00,0x20 = bclr 6, 2, 0 // 0x4c,0xc2,0x04,0x20 = bcctr 6, 2, 0 // 0x4c,0xc2,0x00,0x21 = bclrl 6, 2, 0 // 0x4c,0xc2,0x04,0x21 = bcctrl 6, 2, 0 0x4e,0x00,0x00,0x20 = bdnzlr 0x4e,0x00,0x00,0x21 = bdnzlrl 0x4f,0x20,0x00,0x20 = bdnzlr+ 0x4f,0x20,0x00,0x21 = bdnzlrl+ 0x4f,0x00,0x00,0x20 = bdnzlr- 0x4f,0x00,0x00,0x21 = bdnzlrl- // 0x4d,0x02,0x00,0x20 = bclr 8, 2, 0 // 0x4d,0x02,0x00,0x21 = bclrl 8, 2, 0 // 0x4c,0x02,0x00,0x20 = bclr 0, 2, 0 // 0x4c,0x02,0x00,0x21 = bclrl 0, 2, 0 0x4e,0x40,0x00,0x20 = bdzlr 0x4e,0x40,0x00,0x21 = bdzlrl 0x4f,0x60,0x00,0x20 = bdzlr+ 0x4f,0x60,0x00,0x21 = bdzlrl+ 0x4f,0x40,0x00,0x20 = bdzlr- 0x4f,0x40,0x00,0x21 = bdzlrl- // 0x4d,0x42,0x00,0x20 = bclr 10, 2, 0 // 0x4d,0x42,0x00,0x21 = bclrl 10, 2, 0 // 0x4c,0x42,0x00,0x20 = bclr 2, 2, 0 // 0x4c,0x42,0x00,0x21 = bclrl 2, 2, 0 // 0x4d,0x88,0x00,0x20 = bltlr 2 // 0x4d,0x80,0x00,0x20 = bltlr 0 // 0x4d,0x88,0x04,0x20 = bltctr 2 // 0x4d,0x80,0x04,0x20 = bltctr 0 // 0x4d,0x88,0x00,0x21 = bltlrl 2 // 0x4d,0x80,0x00,0x21 = bltlrl 0 // 0x4d,0x88,0x04,0x21 = bltctrl 2 // 0x4d,0x80,0x04,0x21 = bltctrl 0 // 0x4d,0xe8,0x00,0x20 = bltlr+ 2 // 0x4d,0xe0,0x00,0x20 = bltlr+ 0 // 0x4d,0xe8,0x04,0x20 = bltctr+ 2 // 0x4d,0xe0,0x04,0x20 = bltctr+ 0 // 0x4d,0xe8,0x00,0x21 = bltlrl+ 2 // 0x4d,0xe0,0x00,0x21 = bltlrl+ 0 // 0x4d,0xe8,0x04,0x21 = bltctrl+ 2 // 0x4d,0xe0,0x04,0x21 = bltctrl+ 0 // 0x4d,0xc8,0x00,0x20 = bltlr- 2 // 0x4d,0xc0,0x00,0x20 = bltlr- 0 // 0x4d,0xc8,0x04,0x20 = bltctr- 2 // 0x4d,0xc0,0x04,0x20 = bltctr- 0 // 0x4d,0xc8,0x00,0x21 = bltlrl- 2 // 0x4d,0xc0,0x00,0x21 = bltlrl- 0 // 0x4d,0xc8,0x04,0x21 = bltctrl- 2 // 0x4d,0xc0,0x04,0x21 = bltctrl- 0 // 0x4c,0x89,0x00,0x20 = blelr 2 // 0x4c,0x81,0x00,0x20 = blelr 0 // 0x4c,0x89,0x04,0x20 = blectr 2 // 0x4c,0x81,0x04,0x20 = blectr 0 // 0x4c,0x89,0x00,0x21 = blelrl 2 // 0x4c,0x81,0x00,0x21 = blelrl 0 // 0x4c,0x89,0x04,0x21 = blectrl 2 // 0x4c,0x81,0x04,0x21 = blectrl 0 // 0x4c,0xe9,0x00,0x20 = blelr+ 2 // 0x4c,0xe1,0x00,0x20 = blelr+ 0 // 0x4c,0xe9,0x04,0x20 = blectr+ 2 // 0x4c,0xe1,0x04,0x20 = blectr+ 0 // 0x4c,0xe9,0x00,0x21 = blelrl+ 2 // 0x4c,0xe1,0x00,0x21 = blelrl+ 0 // 0x4c,0xe9,0x04,0x21 = blectrl+ 2 // 0x4c,0xe1,0x04,0x21 = blectrl+ 0 // 0x4c,0xc9,0x00,0x20 = blelr- 2 // 0x4c,0xc1,0x00,0x20 = blelr- 0 // 0x4c,0xc9,0x04,0x20 = blectr- 2 // 0x4c,0xc1,0x04,0x20 = blectr- 0 // 0x4c,0xc9,0x00,0x21 = blelrl- 2 // 0x4c,0xc1,0x00,0x21 = blelrl- 0 // 0x4c,0xc9,0x04,0x21 = blectrl- 2 // 0x4c,0xc1,0x04,0x21 = blectrl- 0 // 0x4d,0x8a,0x00,0x20 = beqlr 2 // 0x4d,0x82,0x00,0x20 = beqlr 0 // 0x4d,0x8a,0x04,0x20 = beqctr 2 // 0x4d,0x82,0x04,0x20 = beqctr 0 // 0x4d,0x8a,0x00,0x21 = beqlrl 2 // 0x4d,0x82,0x00,0x21 = beqlrl 0 // 0x4d,0x8a,0x04,0x21 = beqctrl 2 // 0x4d,0x82,0x04,0x21 = beqctrl 0 // 0x4d,0xea,0x00,0x20 = beqlr+ 2 // 0x4d,0xe2,0x00,0x20 = beqlr+ 0 // 0x4d,0xea,0x04,0x20 = beqctr+ 2 // 0x4d,0xe2,0x04,0x20 = beqctr+ 0 // 0x4d,0xea,0x00,0x21 = beqlrl+ 2 // 0x4d,0xe2,0x00,0x21 = beqlrl+ 0 // 0x4d,0xea,0x04,0x21 = beqctrl+ 2 // 0x4d,0xe2,0x04,0x21 = beqctrl+ 0 // 0x4d,0xca,0x00,0x20 = beqlr- 2 // 0x4d,0xc2,0x00,0x20 = beqlr- 0 // 0x4d,0xca,0x04,0x20 = beqctr- 2 // 0x4d,0xc2,0x04,0x20 = beqctr- 0 // 0x4d,0xca,0x00,0x21 = beqlrl- 2 // 0x4d,0xc2,0x00,0x21 = beqlrl- 0 // 0x4d,0xca,0x04,0x21 = beqctrl- 2 // 0x4d,0xc2,0x04,0x21 = beqctrl- 0 // 0x4c,0x88,0x00,0x20 = bgelr 2 // 0x4c,0x80,0x00,0x20 = bgelr 0 // 0x4c,0x88,0x04,0x20 = bgectr 2 // 0x4c,0x80,0x04,0x20 = bgectr 0 // 0x4c,0x88,0x00,0x21 = bgelrl 2 // 0x4c,0x80,0x00,0x21 = bgelrl 0 // 0x4c,0x88,0x04,0x21 = bgectrl 2 // 0x4c,0x80,0x04,0x21 = bgectrl 0 // 0x4c,0xe8,0x00,0x20 = bgelr+ 2 // 0x4c,0xe0,0x00,0x20 = bgelr+ 0 // 0x4c,0xe8,0x04,0x20 = bgectr+ 2 // 0x4c,0xe0,0x04,0x20 = bgectr+ 0 // 0x4c,0xe8,0x00,0x21 = bgelrl+ 2 // 0x4c,0xe0,0x00,0x21 = bgelrl+ 0 // 0x4c,0xe8,0x04,0x21 = bgectrl+ 2 // 0x4c,0xe0,0x04,0x21 = bgectrl+ 0 // 0x4c,0xc8,0x00,0x20 = bgelr- 2 // 0x4c,0xc0,0x00,0x20 = bgelr- 0 // 0x4c,0xc8,0x04,0x20 = bgectr- 2 // 0x4c,0xc0,0x04,0x20 = bgectr- 0 // 0x4c,0xc8,0x00,0x21 = bgelrl- 2 // 0x4c,0xc0,0x00,0x21 = bgelrl- 0 // 0x4c,0xc8,0x04,0x21 = bgectrl- 2 // 0x4c,0xc0,0x04,0x21 = bgectrl- 0 // 0x4d,0x89,0x00,0x20 = bgtlr 2 // 0x4d,0x81,0x00,0x20 = bgtlr 0 // 0x4d,0x89,0x04,0x20 = bgtctr 2 // 0x4d,0x81,0x04,0x20 = bgtctr 0 // 0x4d,0x89,0x00,0x21 = bgtlrl 2 // 0x4d,0x81,0x00,0x21 = bgtlrl 0 // 0x4d,0x89,0x04,0x21 = bgtctrl 2 // 0x4d,0x81,0x04,0x21 = bgtctrl 0 // 0x4d,0xe9,0x00,0x20 = bgtlr+ 2 // 0x4d,0xe1,0x00,0x20 = bgtlr+ 0 // 0x4d,0xe9,0x04,0x20 = bgtctr+ 2 // 0x4d,0xe1,0x04,0x20 = bgtctr+ 0 // 0x4d,0xe9,0x00,0x21 = bgtlrl+ 2 // 0x4d,0xe1,0x00,0x21 = bgtlrl+ 0 // 0x4d,0xe9,0x04,0x21 = bgtctrl+ 2 // 0x4d,0xe1,0x04,0x21 = bgtctrl+ 0 // 0x4d,0xc9,0x00,0x20 = bgtlr- 2 // 0x4d,0xc1,0x00,0x20 = bgtlr- 0 // 0x4d,0xc9,0x04,0x20 = bgtctr- 2 // 0x4d,0xc1,0x04,0x20 = bgtctr- 0 // 0x4d,0xc9,0x00,0x21 = bgtlrl- 2 // 0x4d,0xc1,0x00,0x21 = bgtlrl- 0 // 0x4d,0xc9,0x04,0x21 = bgtctrl- 2 // 0x4d,0xc1,0x04,0x21 = bgtctrl- 0 // 0x4c,0x88,0x00,0x20 = bgelr 2 // 0x4c,0x80,0x00,0x20 = bgelr 0 // 0x4c,0x88,0x04,0x20 = bgectr 2 // 0x4c,0x80,0x04,0x20 = bgectr 0 // 0x4c,0x88,0x00,0x21 = bgelrl 2 // 0x4c,0x80,0x00,0x21 = bgelrl 0 // 0x4c,0x88,0x04,0x21 = bgectrl 2 // 0x4c,0x80,0x04,0x21 = bgectrl 0 // 0x4c,0xe8,0x00,0x20 = bgelr+ 2 // 0x4c,0xe0,0x00,0x20 = bgelr+ 0 // 0x4c,0xe8,0x04,0x20 = bgectr+ 2 // 0x4c,0xe0,0x04,0x20 = bgectr+ 0 // 0x4c,0xe8,0x00,0x21 = bgelrl+ 2 // 0x4c,0xe0,0x00,0x21 = bgelrl+ 0 // 0x4c,0xe8,0x04,0x21 = bgectrl+ 2 // 0x4c,0xe0,0x04,0x21 = bgectrl+ 0 // 0x4c,0xc8,0x00,0x20 = bgelr- 2 // 0x4c,0xc0,0x00,0x20 = bgelr- 0 // 0x4c,0xc8,0x04,0x20 = bgectr- 2 // 0x4c,0xc0,0x04,0x20 = bgectr- 0 // 0x4c,0xc8,0x00,0x21 = bgelrl- 2 // 0x4c,0xc0,0x00,0x21 = bgelrl- 0 // 0x4c,0xc8,0x04,0x21 = bgectrl- 2 // 0x4c,0xc0,0x04,0x21 = bgectrl- 0 // 0x4c,0x8a,0x00,0x20 = bnelr 2 // 0x4c,0x82,0x00,0x20 = bnelr 0 // 0x4c,0x8a,0x04,0x20 = bnectr 2 // 0x4c,0x82,0x04,0x20 = bnectr 0 // 0x4c,0x8a,0x00,0x21 = bnelrl 2 // 0x4c,0x82,0x00,0x21 = bnelrl 0 // 0x4c,0x8a,0x04,0x21 = bnectrl 2 // 0x4c,0x82,0x04,0x21 = bnectrl 0 // 0x4c,0xea,0x00,0x20 = bnelr+ 2 // 0x4c,0xe2,0x00,0x20 = bnelr+ 0 // 0x4c,0xea,0x04,0x20 = bnectr+ 2 // 0x4c,0xe2,0x04,0x20 = bnectr+ 0 // 0x4c,0xea,0x00,0x21 = bnelrl+ 2 // 0x4c,0xe2,0x00,0x21 = bnelrl+ 0 // 0x4c,0xea,0x04,0x21 = bnectrl+ 2 // 0x4c,0xe2,0x04,0x21 = bnectrl+ 0 // 0x4c,0xca,0x00,0x20 = bnelr- 2 // 0x4c,0xc2,0x00,0x20 = bnelr- 0 // 0x4c,0xca,0x04,0x20 = bnectr- 2 // 0x4c,0xc2,0x04,0x20 = bnectr- 0 // 0x4c,0xca,0x00,0x21 = bnelrl- 2 // 0x4c,0xc2,0x00,0x21 = bnelrl- 0 // 0x4c,0xca,0x04,0x21 = bnectrl- 2 // 0x4c,0xc2,0x04,0x21 = bnectrl- 0 // 0x4c,0x89,0x00,0x20 = blelr 2 // 0x4c,0x81,0x00,0x20 = blelr 0 // 0x4c,0x89,0x04,0x20 = blectr 2 // 0x4c,0x81,0x04,0x20 = blectr 0 // 0x4c,0x89,0x00,0x21 = blelrl 2 // 0x4c,0x81,0x00,0x21 = blelrl 0 // 0x4c,0x89,0x04,0x21 = blectrl 2 // 0x4c,0x81,0x04,0x21 = blectrl 0 // 0x4c,0xe9,0x00,0x20 = blelr+ 2 // 0x4c,0xe1,0x00,0x20 = blelr+ 0 // 0x4c,0xe9,0x04,0x20 = blectr+ 2 // 0x4c,0xe1,0x04,0x20 = blectr+ 0 // 0x4c,0xe9,0x00,0x21 = blelrl+ 2 // 0x4c,0xe1,0x00,0x21 = blelrl+ 0 // 0x4c,0xe9,0x04,0x21 = blectrl+ 2 // 0x4c,0xe1,0x04,0x21 = blectrl+ 0 // 0x4c,0xc9,0x00,0x20 = blelr- 2 // 0x4c,0xc1,0x00,0x20 = blelr- 0 // 0x4c,0xc9,0x04,0x20 = blectr- 2 // 0x4c,0xc1,0x04,0x20 = blectr- 0 // 0x4c,0xc9,0x00,0x21 = blelrl- 2 // 0x4c,0xc1,0x00,0x21 = blelrl- 0 // 0x4c,0xc9,0x04,0x21 = blectrl- 2 // 0x4c,0xc1,0x04,0x21 = blectrl- 0 // 0x4d,0x8b,0x00,0x20 = bunlr 2 // 0x4d,0x83,0x00,0x20 = bunlr 0 // 0x4d,0x8b,0x04,0x20 = bunctr 2 // 0x4d,0x83,0x04,0x20 = bunctr 0 // 0x4d,0x8b,0x00,0x21 = bunlrl 2 // 0x4d,0x83,0x00,0x21 = bunlrl 0 // 0x4d,0x8b,0x04,0x21 = bunctrl 2 // 0x4d,0x83,0x04,0x21 = bunctrl 0 // 0x4d,0xeb,0x00,0x20 = bunlr+ 2 // 0x4d,0xe3,0x00,0x20 = bunlr+ 0 // 0x4d,0xeb,0x04,0x20 = bunctr+ 2 // 0x4d,0xe3,0x04,0x20 = bunctr+ 0 // 0x4d,0xeb,0x00,0x21 = bunlrl+ 2 // 0x4d,0xe3,0x00,0x21 = bunlrl+ 0 // 0x4d,0xeb,0x04,0x21 = bunctrl+ 2 // 0x4d,0xe3,0x04,0x21 = bunctrl+ 0 // 0x4d,0xcb,0x00,0x20 = bunlr- 2 // 0x4d,0xc3,0x00,0x20 = bunlr- 0 // 0x4d,0xcb,0x04,0x20 = bunctr- 2 // 0x4d,0xc3,0x04,0x20 = bunctr- 0 // 0x4d,0xcb,0x00,0x21 = bunlrl- 2 // 0x4d,0xc3,0x00,0x21 = bunlrl- 0 // 0x4d,0xcb,0x04,0x21 = bunctrl- 2 // 0x4d,0xc3,0x04,0x21 = bunctrl- 0 // 0x4c,0x8b,0x00,0x20 = bnulr 2 // 0x4c,0x83,0x00,0x20 = bnulr 0 // 0x4c,0x8b,0x04,0x20 = bnuctr 2 // 0x4c,0x83,0x04,0x20 = bnuctr 0 // 0x4c,0x8b,0x00,0x21 = bnulrl 2 // 0x4c,0x83,0x00,0x21 = bnulrl 0 // 0x4c,0x8b,0x04,0x21 = bnuctrl 2 // 0x4c,0x83,0x04,0x21 = bnuctrl 0 // 0x4c,0xeb,0x00,0x20 = bnulr+ 2 // 0x4c,0xe3,0x00,0x20 = bnulr+ 0 // 0x4c,0xeb,0x04,0x20 = bnuctr+ 2 // 0x4c,0xe3,0x04,0x20 = bnuctr+ 0 // 0x4c,0xeb,0x00,0x21 = bnulrl+ 2 // 0x4c,0xe3,0x00,0x21 = bnulrl+ 0 // 0x4c,0xeb,0x04,0x21 = bnuctrl+ 2 // 0x4c,0xe3,0x04,0x21 = bnuctrl+ 0 // 0x4c,0xcb,0x00,0x20 = bnulr- 2 // 0x4c,0xc3,0x00,0x20 = bnulr- 0 // 0x4c,0xcb,0x04,0x20 = bnuctr- 2 // 0x4c,0xc3,0x04,0x20 = bnuctr- 0 // 0x4c,0xcb,0x00,0x21 = bnulrl- 2 // 0x4c,0xc3,0x00,0x21 = bnulrl- 0 // 0x4c,0xcb,0x04,0x21 = bnuctrl- 2 // 0x4c,0xc3,0x04,0x21 = bnuctrl- 0 // 0x4d,0x8b,0x00,0x20 = bunlr 2 // 0x4d,0x83,0x00,0x20 = bunlr 0 // 0x4d,0x8b,0x04,0x20 = bunctr 2 // 0x4d,0x83,0x04,0x20 = bunctr 0 // 0x4d,0x8b,0x00,0x21 = bunlrl 2 // 0x4d,0x83,0x00,0x21 = bunlrl 0 // 0x4d,0x8b,0x04,0x21 = bunctrl 2 // 0x4d,0x83,0x04,0x21 = bunctrl 0 // 0x4d,0xeb,0x00,0x20 = bunlr+ 2 // 0x4d,0xe3,0x00,0x20 = bunlr+ 0 // 0x4d,0xeb,0x04,0x20 = bunctr+ 2 // 0x4d,0xe3,0x04,0x20 = bunctr+ 0 // 0x4d,0xeb,0x00,0x21 = bunlrl+ 2 // 0x4d,0xe3,0x00,0x21 = bunlrl+ 0 // 0x4d,0xeb,0x04,0x21 = bunctrl+ 2 // 0x4d,0xe3,0x04,0x21 = bunctrl+ 0 // 0x4d,0xcb,0x00,0x20 = bunlr- 2 // 0x4d,0xc3,0x00,0x20 = bunlr- 0 // 0x4d,0xcb,0x04,0x20 = bunctr- 2 // 0x4d,0xc3,0x04,0x20 = bunctr- 0 // 0x4d,0xcb,0x00,0x21 = bunlrl- 2 // 0x4d,0xc3,0x00,0x21 = bunlrl- 0 // 0x4d,0xcb,0x04,0x21 = bunctrl- 2 // 0x4d,0xc3,0x04,0x21 = bunctrl- 0 // 0x4c,0x8b,0x00,0x20 = bnulr 2 // 0x4c,0x83,0x00,0x20 = bnulr 0 // 0x4c,0x8b,0x04,0x20 = bnuctr 2 // 0x4c,0x83,0x04,0x20 = bnuctr 0 // 0x4c,0x8b,0x00,0x21 = bnulrl 2 // 0x4c,0x83,0x00,0x21 = bnulrl 0 // 0x4c,0x8b,0x04,0x21 = bnuctrl 2 // 0x4c,0x83,0x04,0x21 = bnuctrl 0 // 0x4c,0xeb,0x00,0x20 = bnulr+ 2 // 0x4c,0xe3,0x00,0x20 = bnulr+ 0 // 0x4c,0xeb,0x04,0x20 = bnuctr+ 2 // 0x4c,0xe3,0x04,0x20 = bnuctr+ 0 // 0x4c,0xeb,0x00,0x21 = bnulrl+ 2 // 0x4c,0xe3,0x00,0x21 = bnulrl+ 0 // 0x4c,0xeb,0x04,0x21 = bnuctrl+ 2 // 0x4c,0xe3,0x04,0x21 = bnuctrl+ 0 // 0x4c,0xcb,0x00,0x20 = bnulr- 2 // 0x4c,0xc3,0x00,0x20 = bnulr- 0 // 0x4c,0xcb,0x04,0x20 = bnuctr- 2 // 0x4c,0xc3,0x04,0x20 = bnuctr- 0 // 0x4c,0xcb,0x00,0x21 = bnulrl- 2 // 0x4c,0xc3,0x00,0x21 = bnulrl- 0 // 0x4c,0xcb,0x04,0x21 = bnuctrl- 2 // 0x4c,0xc3,0x04,0x21 = bnuctrl- 0 // 0x4c,0x42,0x12,0x42 = creqv 2, 2, 2 // 0x4c,0x42,0x11,0x82 = crxor 2, 2, 2 // 0x4c,0x43,0x1b,0x82 = cror 2, 3, 3 // 0x4c,0x43,0x18,0x42 = crnor 2, 3, 3 // 0x38,0x43,0xff,0x80 = addi 2, 3, -128 // 0x3c,0x43,0xff,0x80 = addis 2, 3, -128 // 0x30,0x43,0xff,0x80 = addic 2, 3, -128 // 0x34,0x43,0xff,0x80 = addic. 2, 3, -128 0x7c,0x44,0x18,0x50 = subf 2, 4, 3 0x7c,0x44,0x18,0x51 = subf. 2, 4, 3 0x7c,0x44,0x18,0x10 = subfc 2, 4, 3 0x7c,0x44,0x18,0x11 = subfc. 2, 4, 3 0x2d,0x23,0x00,0x80 = cmpdi 2, 3, 128 // 0x2c,0x23,0x00,0x80 = cmpdi 0, 3, 128 0x7d,0x23,0x20,0x00 = cmpd 2, 3, 4 // 0x7c,0x23,0x20,0x00 = cmpd 0, 3, 4 0x29,0x23,0x00,0x80 = cmpldi 2, 3, 128 // 0x28,0x23,0x00,0x80 = cmpldi 0, 3, 128 0x7d,0x23,0x20,0x40 = cmpld 2, 3, 4 // 0x7c,0x23,0x20,0x40 = cmpld 0, 3, 4 0x2d,0x03,0x00,0x80 = cmpwi 2, 3, 128 // 0x2c,0x03,0x00,0x80 = cmpwi 0, 3, 128 0x7d,0x03,0x20,0x00 = cmpw 2, 3, 4 // 0x7c,0x03,0x20,0x00 = cmpw 0, 3, 4 0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128 // 0x28,0x03,0x00,0x80 = cmplwi 0, 3, 128 0x7d,0x03,0x20,0x40 = cmplw 2, 3, 4 // 0x7c,0x03,0x20,0x40 = cmplw 0, 3, 4 // 0x0e,0x03,0x00,0x04 = twi 16, 3, 4 // 0x7e,0x03,0x20,0x08 = tw 16, 3, 4 // 0x0a,0x03,0x00,0x04 = tdi 16, 3, 4 // 0x7e,0x03,0x20,0x88 = td 16, 3, 4 0x0e,0x83,0x00,0x04 = twi 20, 3, 4 0x7e,0x83,0x20,0x08 = tw 20, 3, 4 0x0a,0x83,0x00,0x04 = tdi 20, 3, 4 0x7e,0x83,0x20,0x88 = td 20, 3, 4 // 0x0c,0x83,0x00,0x04 = twi 4, 3, 4 // 0x7c,0x83,0x20,0x08 = tw 4, 3, 4 // 0x08,0x83,0x00,0x04 = tdi 4, 3, 4 // 0x7c,0x83,0x20,0x88 = td 4, 3, 4 0x0d,0x83,0x00,0x04 = twi 12, 3, 4 0x7d,0x83,0x20,0x08 = tw 12, 3, 4 0x09,0x83,0x00,0x04 = tdi 12, 3, 4 0x7d,0x83,0x20,0x88 = td 12, 3, 4 // 0x0d,0x03,0x00,0x04 = twi 8, 3, 4 // 0x7d,0x03,0x20,0x08 = tw 8, 3, 4 // 0x09,0x03,0x00,0x04 = tdi 8, 3, 4 // 0x7d,0x03,0x20,0x88 = td 8, 3, 4 0x0d,0x83,0x00,0x04 = twi 12, 3, 4 0x7d,0x83,0x20,0x08 = tw 12, 3, 4 0x09,0x83,0x00,0x04 = tdi 12, 3, 4 0x7d,0x83,0x20,0x88 = td 12, 3, 4 // 0x0f,0x03,0x00,0x04 = twi 24, 3, 4 // 0x7f,0x03,0x20,0x08 = tw 24, 3, 4 // 0x0b,0x03,0x00,0x04 = tdi 24, 3, 4 // 0x7f,0x03,0x20,0x88 = td 24, 3, 4 0x0e,0x83,0x00,0x04 = twi 20, 3, 4 0x7e,0x83,0x20,0x08 = tw 20, 3, 4 0x0a,0x83,0x00,0x04 = tdi 20, 3, 4 0x7e,0x83,0x20,0x88 = td 20, 3, 4 // 0x0c,0x43,0x00,0x04 = twi 2, 3, 4 // 0x7c,0x43,0x20,0x08 = tw 2, 3, 4 // 0x08,0x43,0x00,0x04 = tdi 2, 3, 4 // 0x7c,0x43,0x20,0x88 = td 2, 3, 4 0x0c,0xc3,0x00,0x04 = twi 6, 3, 4 0x7c,0xc3,0x20,0x08 = tw 6, 3, 4 0x08,0xc3,0x00,0x04 = tdi 6, 3, 4 0x7c,0xc3,0x20,0x88 = td 6, 3, 4 0x0c,0xa3,0x00,0x04 = twi 5, 3, 4 0x7c,0xa3,0x20,0x08 = tw 5, 3, 4 0x08,0xa3,0x00,0x04 = tdi 5, 3, 4 0x7c,0xa3,0x20,0x88 = td 5, 3, 4 // 0x0c,0x23,0x00,0x04 = twi 1, 3, 4 // 0x7c,0x23,0x20,0x08 = tw 1, 3, 4 // 0x08,0x23,0x00,0x04 = tdi 1, 3, 4 // 0x7c,0x23,0x20,0x88 = td 1, 3, 4 0x0c,0xa3,0x00,0x04 = twi 5, 3, 4 0x7c,0xa3,0x20,0x08 = tw 5, 3, 4 0x08,0xa3,0x00,0x04 = tdi 5, 3, 4 0x7c,0xa3,0x20,0x88 = td 5, 3, 4 0x0c,0xc3,0x00,0x04 = twi 6, 3, 4 0x7c,0xc3,0x20,0x08 = tw 6, 3, 4 0x08,0xc3,0x00,0x04 = tdi 6, 3, 4 0x7c,0xc3,0x20,0x88 = td 6, 3, 4 // 0x0f,0xe3,0x00,0x04 = twi 31, 3, 4 // 0x7f,0xe3,0x20,0x08 = tw 31, 3, 4 // 0x0b,0xe3,0x00,0x04 = tdi 31, 3, 4 // 0x7f,0xe3,0x20,0x88 = td 31, 3, 4 0x7f,0xe0,0x00,0x08 = trap 0x78,0x62,0x28,0xc4 = rldicr 2, 3, 5, 3 0x78,0x62,0x28,0xc5 = rldicr. 2, 3, 5, 3 0x78,0x62,0x4f,0x20 = rldicl 2, 3, 9, 60 0x78,0x62,0x4f,0x21 = rldicl. 2, 3, 9, 60 0x78,0x62,0xb9,0x4e = rldimi 2, 3, 55, 5 0x78,0x62,0xb9,0x4f = rldimi. 2, 3, 55, 5 // 0x78,0x62,0x20,0x00 = rldicl 2, 3, 4, 0 // 0x78,0x62,0x20,0x01 = rldicl. 2, 3, 4, 0 // 0x78,0x62,0xe0,0x02 = rldicl 2, 3, 60, 0 // 0x78,0x62,0xe0,0x03 = rldicl. 2, 3, 60, 0 // 0x78,0x62,0x20,0x10 = rldcl 2, 3, 4, 0 // 0x78,0x62,0x20,0x11 = rldcl. 2, 3, 4, 0 0x78,0x62,0x26,0xe4 = sldi 2, 3, 4 0x78,0x62,0x26,0xe5 = rldicr. 2, 3, 4, 59 0x78,0x62,0xe1,0x02 = rldicl 2, 3, 60, 4 0x78,0x62,0xe1,0x03 = rldicl. 2, 3, 60, 4 // 0x78,0x62,0x01,0x00 = rldicl 2, 3, 0, 4 // 0x78,0x62,0x01,0x01 = rldicl. 2, 3, 0, 4 0x78,0x62,0x06,0xe4 = rldicr 2, 3, 0, 59 0x78,0x62,0x06,0xe5 = rldicr. 2, 3, 0, 59 0x78,0x62,0x20,0x48 = rldic 2, 3, 4, 1 0x78,0x62,0x20,0x49 = rldic. 2, 3, 4, 1 0x54,0x62,0x28,0x06 = rlwinm 2, 3, 5, 0, 3 0x54,0x62,0x28,0x07 = rlwinm. 2, 3, 5, 0, 3 0x54,0x62,0x4f,0x3e = rlwinm 2, 3, 9, 28, 31 0x54,0x62,0x4f,0x3f = rlwinm. 2, 3, 9, 28, 31 0x50,0x62,0xd9,0x50 = rlwimi 2, 3, 27, 5, 8 0x50,0x62,0xd9,0x51 = rlwimi. 2, 3, 27, 5, 8 0x50,0x62,0xb9,0x50 = rlwimi 2, 3, 23, 5, 8 0x50,0x62,0xb9,0x51 = rlwimi. 2, 3, 23, 5, 8 // 0x54,0x62,0x20,0x3e = rlwinm 2, 3, 4, 0, 31 // 0x54,0x62,0x20,0x3f = rlwinm. 2, 3, 4, 0, 31 // 0x54,0x62,0xe0,0x3e = rlwinm 2, 3, 28, 0, 31 // 0x54,0x62,0xe0,0x3f = rlwinm. 2, 3, 28, 0, 31 // 0x5c,0x62,0x20,0x3e = rlwnm 2, 3, 4, 0, 31 // 0x5c,0x62,0x20,0x3f = rlwnm. 2, 3, 4, 0, 31 0x54,0x62,0x20,0x36 = slwi 2, 3, 4 0x54,0x62,0x20,0x37 = rlwinm. 2, 3, 4, 0, 27 0x54,0x62,0xe1,0x3e = srwi 2, 3, 4 0x54,0x62,0xe1,0x3f = rlwinm. 2, 3, 28, 4, 31 // 0x54,0x62,0x01,0x3e = rlwinm 2, 3, 0, 4, 31 // 0x54,0x62,0x01,0x3f = rlwinm. 2, 3, 0, 4, 31 0x54,0x62,0x00,0x36 = rlwinm 2, 3, 0, 0, 27 0x54,0x62,0x00,0x37 = rlwinm. 2, 3, 0, 0, 27 0x54,0x62,0x20,0x76 = rlwinm 2, 3, 4, 1, 27 0x54,0x62,0x20,0x77 = rlwinm. 2, 3, 4, 1, 27 // 0x7c,0x41,0x03,0xa6 = mtspr 1, 2 // 0x7c,0x41,0x02,0xa6 = mfspr 2, 1 0x7c,0x48,0x03,0xa6 = mtlr 2 0x7c,0x48,0x02,0xa6 = mflr 2 0x7c,0x49,0x03,0xa6 = mtctr 2 0x7c,0x49,0x02,0xa6 = mfctr 2 0x60,0x00,0x00,0x00 = nop // 0x68,0x00,0x00,0x00 = xori 0, 0, 0 0x38,0x40,0x00,0x80 = li 2, 128 0x3c,0x40,0x00,0x80 = lis 2, 128 0x7c,0x62,0x1b,0x78 = mr 2, 3 0x7c,0x62,0x1b,0x79 = or. 2, 3, 3 0x7c,0x62,0x18,0xf8 = nor 2, 3, 3 0x7c,0x62,0x18,0xf9 = nor. 2, 3, 3 0x7c,0x4f,0xf1,0x20 = mtcrf 255, 2 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-encoding-fp.s.cs000064400000000000000000000075460072674642500231010ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 0xc0,0x44,0x00,0x80 = lfs 2, 128(4) 0x7c,0x43,0x24,0x2e = lfsx 2, 3, 4 0xc4,0x44,0x00,0x80 = lfsu 2, 128(4) 0x7c,0x43,0x24,0x6e = lfsux 2, 3, 4 0xc8,0x44,0x00,0x80 = lfd 2, 128(4) 0x7c,0x43,0x24,0xae = lfdx 2, 3, 4 0xcc,0x44,0x00,0x80 = lfdu 2, 128(4) 0x7c,0x43,0x24,0xee = lfdux 2, 3, 4 0x7c,0x43,0x26,0xae = lfiwax 2, 3, 4 0x7c,0x43,0x26,0xee = lfiwzx 2, 3, 4 0xd0,0x44,0x00,0x80 = stfs 2, 128(4) 0x7c,0x43,0x25,0x2e = stfsx 2, 3, 4 0xd4,0x44,0x00,0x80 = stfsu 2, 128(4) 0x7c,0x43,0x25,0x6e = stfsux 2, 3, 4 0xd8,0x44,0x00,0x80 = stfd 2, 128(4) 0x7c,0x43,0x25,0xae = stfdx 2, 3, 4 0xdc,0x44,0x00,0x80 = stfdu 2, 128(4) 0x7c,0x43,0x25,0xee = stfdux 2, 3, 4 0x7c,0x43,0x27,0xae = stfiwx 2, 3, 4 0xfc,0x40,0x18,0x90 = fmr 2, 3 0xfc,0x40,0x18,0x91 = fmr. 2, 3 0xfc,0x40,0x18,0x50 = fneg 2, 3 0xfc,0x40,0x18,0x51 = fneg. 2, 3 0xfc,0x40,0x1a,0x10 = fabs 2, 3 0xfc,0x40,0x1a,0x11 = fabs. 2, 3 0xfc,0x40,0x19,0x10 = fnabs 2, 3 0xfc,0x40,0x19,0x11 = fnabs. 2, 3 0xfc,0x43,0x20,0x10 = fcpsgn 2, 3, 4 0xfc,0x43,0x20,0x11 = fcpsgn. 2, 3, 4 0xfc,0x43,0x20,0x2a = fadd 2, 3, 4 0xfc,0x43,0x20,0x2b = fadd. 2, 3, 4 0xec,0x43,0x20,0x2a = fadds 2, 3, 4 0xec,0x43,0x20,0x2b = fadds. 2, 3, 4 0xfc,0x43,0x20,0x28 = fsub 2, 3, 4 0xfc,0x43,0x20,0x29 = fsub. 2, 3, 4 0xec,0x43,0x20,0x28 = fsubs 2, 3, 4 0xec,0x43,0x20,0x29 = fsubs. 2, 3, 4 0xfc,0x43,0x01,0x32 = fmul 2, 3, 4 0xfc,0x43,0x01,0x33 = fmul. 2, 3, 4 0xec,0x43,0x01,0x32 = fmuls 2, 3, 4 0xec,0x43,0x01,0x33 = fmuls. 2, 3, 4 0xfc,0x43,0x20,0x24 = fdiv 2, 3, 4 0xfc,0x43,0x20,0x25 = fdiv. 2, 3, 4 0xec,0x43,0x20,0x24 = fdivs 2, 3, 4 0xec,0x43,0x20,0x25 = fdivs. 2, 3, 4 0xfc,0x40,0x18,0x2c = fsqrt 2, 3 0xfc,0x40,0x18,0x2d = fsqrt. 2, 3 0xec,0x40,0x18,0x2c = fsqrts 2, 3 0xec,0x40,0x18,0x2d = fsqrts. 2, 3 0xfc,0x40,0x18,0x30 = fre 2, 3 0xfc,0x40,0x18,0x31 = fre. 2, 3 0xec,0x40,0x18,0x30 = fres 2, 3 0xec,0x40,0x18,0x31 = fres. 2, 3 0xfc,0x40,0x18,0x34 = frsqrte 2, 3 0xfc,0x40,0x18,0x35 = frsqrte. 2, 3 0xec,0x40,0x18,0x34 = frsqrtes 2, 3 0xec,0x40,0x18,0x35 = frsqrtes. 2, 3 0xfc,0x43,0x29,0x3a = fmadd 2, 3, 4, 5 0xfc,0x43,0x29,0x3b = fmadd. 2, 3, 4, 5 0xec,0x43,0x29,0x3a = fmadds 2, 3, 4, 5 0xec,0x43,0x29,0x3b = fmadds. 2, 3, 4, 5 0xfc,0x43,0x29,0x38 = fmsub 2, 3, 4, 5 0xfc,0x43,0x29,0x39 = fmsub. 2, 3, 4, 5 0xec,0x43,0x29,0x38 = fmsubs 2, 3, 4, 5 0xec,0x43,0x29,0x39 = fmsubs. 2, 3, 4, 5 0xfc,0x43,0x29,0x3e = fnmadd 2, 3, 4, 5 0xfc,0x43,0x29,0x3f = fnmadd. 2, 3, 4, 5 0xec,0x43,0x29,0x3e = fnmadds 2, 3, 4, 5 0xec,0x43,0x29,0x3f = fnmadds. 2, 3, 4, 5 0xfc,0x43,0x29,0x3c = fnmsub 2, 3, 4, 5 0xfc,0x43,0x29,0x3d = fnmsub. 2, 3, 4, 5 0xec,0x43,0x29,0x3c = fnmsubs 2, 3, 4, 5 0xec,0x43,0x29,0x3d = fnmsubs. 2, 3, 4, 5 0xfc,0x40,0x18,0x18 = frsp 2, 3 0xfc,0x40,0x18,0x19 = frsp. 2, 3 0xfc,0x40,0x1e,0x5c = fctid 2, 3 0xfc,0x40,0x1e,0x5d = fctid. 2, 3 0xfc,0x40,0x1e,0x5e = fctidz 2, 3 0xfc,0x40,0x1e,0x5f = fctidz. 2, 3 0xfc,0x40,0x1f,0x5e = fctiduz 2, 3 0xfc,0x40,0x1f,0x5f = fctiduz. 2, 3 0xfc,0x40,0x18,0x1c = fctiw 2, 3 0xfc,0x40,0x18,0x1d = fctiw. 2, 3 0xfc,0x40,0x18,0x1e = fctiwz 2, 3 0xfc,0x40,0x18,0x1f = fctiwz. 2, 3 0xfc,0x40,0x19,0x1e = fctiwuz 2, 3 0xfc,0x40,0x19,0x1f = fctiwuz. 2, 3 0xfc,0x40,0x1e,0x9c = fcfid 2, 3 0xfc,0x40,0x1e,0x9d = fcfid. 2, 3 0xfc,0x40,0x1f,0x9c = fcfidu 2, 3 0xfc,0x40,0x1f,0x9d = fcfidu. 2, 3 0xec,0x40,0x1e,0x9c = fcfids 2, 3 0xec,0x40,0x1e,0x9d = fcfids. 2, 3 0xec,0x40,0x1f,0x9c = fcfidus 2, 3 0xec,0x40,0x1f,0x9d = fcfidus. 2, 3 0xfc,0x40,0x1b,0x10 = frin 2, 3 0xfc,0x40,0x1b,0x11 = frin. 2, 3 0xfc,0x40,0x1b,0x90 = frip 2, 3 0xfc,0x40,0x1b,0x91 = frip. 2, 3 0xfc,0x40,0x1b,0x50 = friz 2, 3 0xfc,0x40,0x1b,0x51 = friz. 2, 3 0xfc,0x40,0x1b,0xd0 = frim 2, 3 0xfc,0x40,0x1b,0xd1 = frim. 2, 3 0xfd,0x03,0x20,0x00 = fcmpu 2, 3, 4 0xfc,0x43,0x29,0x2e = fsel 2, 3, 4, 5 0xfc,0x43,0x29,0x2f = fsel. 2, 3, 4, 5 0xfc,0x40,0x04,0x8e = mffs 2 0xff,0xe0,0x00,0x8c = mtfsb0 31 0xff,0xe0,0x00,0x4c = mtfsb1 31 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-encoding-vmx.s.cs000064400000000000000000000143470072674642500233030ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 0x7c,0x43,0x20,0x0e = lvebx 2, 3, 4 0x7c,0x43,0x20,0x4e = lvehx 2, 3, 4 0x7c,0x43,0x20,0x8e = lvewx 2, 3, 4 0x7c,0x43,0x20,0xce = lvx 2, 3, 4 0x7c,0x43,0x22,0xce = lvxl 2, 3, 4 0x7c,0x43,0x21,0x0e = stvebx 2, 3, 4 0x7c,0x43,0x21,0x4e = stvehx 2, 3, 4 0x7c,0x43,0x21,0x8e = stvewx 2, 3, 4 0x7c,0x43,0x21,0xce = stvx 2, 3, 4 0x7c,0x43,0x23,0xce = stvxl 2, 3, 4 0x7c,0x43,0x20,0x0c = lvsl 2, 3, 4 0x7c,0x43,0x20,0x4c = lvsr 2, 3, 4 0x10,0x43,0x23,0x0e = vpkpx 2, 3, 4 0x10,0x43,0x21,0x8e = vpkshss 2, 3, 4 0x10,0x43,0x21,0x0e = vpkshus 2, 3, 4 0x10,0x43,0x21,0xce = vpkswss 2, 3, 4 0x10,0x43,0x21,0x4e = vpkswus 2, 3, 4 0x10,0x43,0x20,0x0e = vpkuhum 2, 3, 4 0x10,0x43,0x20,0x8e = vpkuhus 2, 3, 4 0x10,0x43,0x20,0x4e = vpkuwum 2, 3, 4 0x10,0x43,0x20,0xce = vpkuwus 2, 3, 4 0x10,0x40,0x1b,0x4e = vupkhpx 2, 3 0x10,0x40,0x1a,0x0e = vupkhsb 2, 3 0x10,0x40,0x1a,0x4e = vupkhsh 2, 3 0x10,0x40,0x1b,0xce = vupklpx 2, 3 0x10,0x40,0x1a,0x8e = vupklsb 2, 3 0x10,0x40,0x1a,0xce = vupklsh 2, 3 0x10,0x43,0x20,0x0c = vmrghb 2, 3, 4 0x10,0x43,0x20,0x4c = vmrghh 2, 3, 4 0x10,0x43,0x20,0x8c = vmrghw 2, 3, 4 0x10,0x43,0x21,0x0c = vmrglb 2, 3, 4 0x10,0x43,0x21,0x4c = vmrglh 2, 3, 4 0x10,0x43,0x21,0x8c = vmrglw 2, 3, 4 0x10,0x41,0x1a,0x0c = vspltb 2, 3, 1 0x10,0x41,0x1a,0x4c = vsplth 2, 3, 1 0x10,0x41,0x1a,0x8c = vspltw 2, 3, 1 0x10,0x43,0x03,0x0c = vspltisb 2, 3 0x10,0x43,0x03,0x4c = vspltish 2, 3 0x10,0x43,0x03,0x8c = vspltisw 2, 3 0x10,0x43,0x21,0x6b = vperm 2, 3, 4, 5 0x10,0x43,0x21,0x6a = vsel 2, 3, 4, 5 0x10,0x43,0x21,0xc4 = vsl 2, 3, 4 0x10,0x43,0x21,0x6c = vsldoi 2, 3, 4, 5 0x10,0x43,0x24,0x0c = vslo 2, 3, 4 0x10,0x43,0x22,0xc4 = vsr 2, 3, 4 0x10,0x43,0x24,0x4c = vsro 2, 3, 4 0x10,0x43,0x21,0x80 = vaddcuw 2, 3, 4 0x10,0x43,0x23,0x00 = vaddsbs 2, 3, 4 0x10,0x43,0x23,0x40 = vaddshs 2, 3, 4 0x10,0x43,0x23,0x80 = vaddsws 2, 3, 4 0x10,0x43,0x20,0x00 = vaddubm 2, 3, 4 0x10,0x43,0x20,0x40 = vadduhm 2, 3, 4 0x10,0x43,0x20,0x80 = vadduwm 2, 3, 4 0x10,0x43,0x22,0x00 = vaddubs 2, 3, 4 0x10,0x43,0x22,0x40 = vadduhs 2, 3, 4 0x10,0x43,0x22,0x80 = vadduws 2, 3, 4 0x10,0x43,0x25,0x80 = vsubcuw 2, 3, 4 0x10,0x43,0x27,0x00 = vsubsbs 2, 3, 4 0x10,0x43,0x27,0x40 = vsubshs 2, 3, 4 0x10,0x43,0x27,0x80 = vsubsws 2, 3, 4 0x10,0x43,0x24,0x00 = vsububm 2, 3, 4 0x10,0x43,0x24,0x40 = vsubuhm 2, 3, 4 0x10,0x43,0x24,0x80 = vsubuwm 2, 3, 4 0x10,0x43,0x26,0x00 = vsububs 2, 3, 4 0x10,0x43,0x26,0x40 = vsubuhs 2, 3, 4 0x10,0x43,0x26,0x80 = vsubuws 2, 3, 4 0x10,0x43,0x23,0x08 = vmulesb 2, 3, 4 0x10,0x43,0x23,0x48 = vmulesh 2, 3, 4 0x10,0x43,0x22,0x08 = vmuleub 2, 3, 4 0x10,0x43,0x22,0x48 = vmuleuh 2, 3, 4 0x10,0x43,0x21,0x08 = vmulosb 2, 3, 4 0x10,0x43,0x21,0x48 = vmulosh 2, 3, 4 0x10,0x43,0x20,0x08 = vmuloub 2, 3, 4 0x10,0x43,0x20,0x48 = vmulouh 2, 3, 4 0x10,0x43,0x21,0x60 = vmhaddshs 2, 3, 4, 5 0x10,0x43,0x21,0x61 = vmhraddshs 2, 3, 4, 5 0x10,0x43,0x21,0x62 = vmladduhm 2, 3, 4, 5 0x10,0x43,0x21,0x64 = vmsumubm 2, 3, 4, 5 0x10,0x43,0x21,0x65 = vmsummbm 2, 3, 4, 5 0x10,0x43,0x21,0x68 = vmsumshm 2, 3, 4, 5 0x10,0x43,0x21,0x69 = vmsumshs 2, 3, 4, 5 0x10,0x43,0x21,0x66 = vmsumuhm 2, 3, 4, 5 0x10,0x43,0x21,0x67 = vmsumuhs 2, 3, 4, 5 0x10,0x43,0x27,0x88 = vsumsws 2, 3, 4 0x10,0x43,0x26,0x88 = vsum2sws 2, 3, 4 0x10,0x43,0x27,0x08 = vsum4sbs 2, 3, 4 0x10,0x43,0x26,0x48 = vsum4shs 2, 3, 4 0x10,0x43,0x26,0x08 = vsum4ubs 2, 3, 4 0x10,0x43,0x25,0x02 = vavgsb 2, 3, 4 0x10,0x43,0x25,0x42 = vavgsh 2, 3, 4 0x10,0x43,0x25,0x82 = vavgsw 2, 3, 4 0x10,0x43,0x24,0x02 = vavgub 2, 3, 4 0x10,0x43,0x24,0x42 = vavguh 2, 3, 4 0x10,0x43,0x24,0x82 = vavguw 2, 3, 4 0x10,0x43,0x21,0x02 = vmaxsb 2, 3, 4 0x10,0x43,0x21,0x42 = vmaxsh 2, 3, 4 0x10,0x43,0x21,0x82 = vmaxsw 2, 3, 4 0x10,0x43,0x20,0x02 = vmaxub 2, 3, 4 0x10,0x43,0x20,0x42 = vmaxuh 2, 3, 4 0x10,0x43,0x20,0x82 = vmaxuw 2, 3, 4 0x10,0x43,0x23,0x02 = vminsb 2, 3, 4 0x10,0x43,0x23,0x42 = vminsh 2, 3, 4 0x10,0x43,0x23,0x82 = vminsw 2, 3, 4 0x10,0x43,0x22,0x02 = vminub 2, 3, 4 0x10,0x43,0x22,0x42 = vminuh 2, 3, 4 0x10,0x43,0x22,0x82 = vminuw 2, 3, 4 0x10,0x43,0x20,0x06 = vcmpequb 2, 3, 4 0x10,0x43,0x24,0x06 = vcmpequb. 2, 3, 4 0x10,0x43,0x20,0x46 = vcmpequh 2, 3, 4 0x10,0x43,0x24,0x46 = vcmpequh. 2, 3, 4 0x10,0x43,0x20,0x86 = vcmpequw 2, 3, 4 0x10,0x43,0x24,0x86 = vcmpequw. 2, 3, 4 0x10,0x43,0x23,0x06 = vcmpgtsb 2, 3, 4 0x10,0x43,0x27,0x06 = vcmpgtsb. 2, 3, 4 0x10,0x43,0x23,0x46 = vcmpgtsh 2, 3, 4 0x10,0x43,0x27,0x46 = vcmpgtsh. 2, 3, 4 0x10,0x43,0x23,0x86 = vcmpgtsw 2, 3, 4 0x10,0x43,0x27,0x86 = vcmpgtsw. 2, 3, 4 0x10,0x43,0x22,0x06 = vcmpgtub 2, 3, 4 0x10,0x43,0x26,0x06 = vcmpgtub. 2, 3, 4 0x10,0x43,0x22,0x46 = vcmpgtuh 2, 3, 4 0x10,0x43,0x26,0x46 = vcmpgtuh. 2, 3, 4 0x10,0x43,0x22,0x86 = vcmpgtuw 2, 3, 4 0x10,0x43,0x26,0x86 = vcmpgtuw. 2, 3, 4 0x10,0x43,0x24,0x04 = vand 2, 3, 4 0x10,0x43,0x24,0x44 = vandc 2, 3, 4 0x10,0x43,0x25,0x04 = vnor 2, 3, 4 0x10,0x43,0x24,0x84 = vor 2, 3, 4 0x10,0x43,0x24,0xc4 = vxor 2, 3, 4 0x10,0x43,0x20,0x04 = vrlb 2, 3, 4 0x10,0x43,0x20,0x44 = vrlh 2, 3, 4 0x10,0x43,0x20,0x84 = vrlw 2, 3, 4 0x10,0x43,0x21,0x04 = vslb 2, 3, 4 0x10,0x43,0x21,0x44 = vslh 2, 3, 4 0x10,0x43,0x21,0x84 = vslw 2, 3, 4 0x10,0x43,0x22,0x04 = vsrb 2, 3, 4 0x10,0x43,0x22,0x44 = vsrh 2, 3, 4 0x10,0x43,0x22,0x84 = vsrw 2, 3, 4 0x10,0x43,0x23,0x04 = vsrab 2, 3, 4 0x10,0x43,0x23,0x44 = vsrah 2, 3, 4 0x10,0x43,0x23,0x84 = vsraw 2, 3, 4 0x10,0x43,0x20,0x0a = vaddfp 2, 3, 4 0x10,0x43,0x20,0x4a = vsubfp 2, 3, 4 0x10,0x43,0x29,0x2e = vmaddfp 2, 3, 4, 5 0x10,0x43,0x29,0x2f = vnmsubfp 2, 3, 4, 5 0x10,0x43,0x24,0x0a = vmaxfp 2, 3, 4 0x10,0x43,0x24,0x4a = vminfp 2, 3, 4 0x10,0x44,0x1b,0xca = vctsxs 2, 3, 4 0x10,0x44,0x1b,0x8a = vctuxs 2, 3, 4 0x10,0x44,0x1b,0x4a = vcfsx 2, 3, 4 0x10,0x44,0x1b,0x0a = vcfux 2, 3, 4 0x10,0x40,0x1a,0xca = vrfim 2, 3 0x10,0x40,0x1a,0x0a = vrfin 2, 3 0x10,0x40,0x1a,0x8a = vrfip 2, 3 0x10,0x40,0x1a,0x4a = vrfiz 2, 3 0x10,0x43,0x23,0xc6 = vcmpbfp 2, 3, 4 0x10,0x43,0x27,0xc6 = vcmpbfp. 2, 3, 4 0x10,0x43,0x20,0xc6 = vcmpeqfp 2, 3, 4 0x10,0x43,0x24,0xc6 = vcmpeqfp. 2, 3, 4 0x10,0x43,0x21,0xc6 = vcmpgefp 2, 3, 4 0x10,0x43,0x25,0xc6 = vcmpgefp. 2, 3, 4 0x10,0x43,0x22,0xc6 = vcmpgtfp 2, 3, 4 0x10,0x43,0x26,0xc6 = vcmpgtfp. 2, 3, 4 0x10,0x40,0x19,0x8a = vexptefp 2, 3 0x10,0x40,0x19,0xca = vlogefp 2, 3 0x10,0x40,0x19,0x0a = vrefp 2, 3 0x10,0x40,0x19,0x4a = vrsqrtefp 2, 3 0x10,0x00,0x16,0x44 = mtvscr 2 0x10,0x40,0x06,0x04 = mfvscr 2 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-encoding.s.cs000064400000000000000000000164100072674642500224640ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, None // 0x4c,0x8a,0x18,0x20 = bclr 4, 10, 3 // 0x4c,0x8a,0x00,0x20 = bclr 4, 10, 0 // 0x4c,0x8a,0x18,0x21 = bclrl 4, 10, 3 // 0x4c,0x8a,0x00,0x21 = bclrl 4, 10, 0 // 0x4c,0x8a,0x1c,0x20 = bcctr 4, 10, 3 // 0x4c,0x8a,0x04,0x20 = bcctr 4, 10, 0 // 0x4c,0x8a,0x1c,0x21 = bcctrl 4, 10, 3 // 0x4c,0x8a,0x04,0x21 = bcctrl 4, 10, 0 0x4c,0x43,0x22,0x02 = crand cr0eq, cr0un, cr1lt 0x4c,0x43,0x21,0xc2 = crnand cr0eq, cr0un, cr1lt 0x4c,0x43,0x23,0x82 = cror cr0eq, cr0un, cr1lt 0x4c,0x43,0x21,0x82 = crxor cr0eq, cr0un, cr1lt 0x4c,0x43,0x20,0x42 = crnor cr0eq, cr0un, cr1lt 0x4c,0x43,0x22,0x42 = creqv cr0eq, cr0un, cr1lt 0x4c,0x43,0x21,0x02 = crandc cr0eq, cr0un, cr1lt 0x4c,0x43,0x23,0x42 = crorc cr0eq, cr0un, cr1lt 0x4d,0x0c,0x00,0x00 = mcrf 2, 3 0x44,0x00,0x00,0x22 = sc 1 // 0x44,0x00,0x00,0x02 = sc 0 0x88,0x44,0x00,0x80 = lbz 2, 128(4) 0x7c,0x43,0x20,0xae = lbzx 2, 3, 4 0x8c,0x44,0x00,0x80 = lbzu 2, 128(4) 0x7c,0x43,0x20,0xee = lbzux 2, 3, 4 0xa0,0x44,0x00,0x80 = lhz 2, 128(4) 0x7c,0x43,0x22,0x2e = lhzx 2, 3, 4 0xa4,0x44,0x00,0x80 = lhzu 2, 128(4) 0x7c,0x43,0x22,0x6e = lhzux 2, 3, 4 0xa8,0x44,0x00,0x80 = lha 2, 128(4) 0x7c,0x43,0x22,0xae = lhax 2, 3, 4 0xac,0x44,0x00,0x80 = lhau 2, 128(4) 0x7c,0x43,0x22,0xee = lhaux 2, 3, 4 0x80,0x44,0x00,0x80 = lwz 2, 128(4) 0x7c,0x43,0x20,0x2e = lwzx 2, 3, 4 0x84,0x44,0x00,0x80 = lwzu 2, 128(4) 0x7c,0x43,0x20,0x6e = lwzux 2, 3, 4 0xe8,0x44,0x00,0x82 = lwa 2, 128(4) 0x7c,0x43,0x22,0xaa = lwax 2, 3, 4 0x7c,0x43,0x22,0xea = lwaux 2, 3, 4 0xe8,0x44,0x00,0x80 = ld 2, 128(4) 0x7c,0x43,0x20,0x2a = ldx 2, 3, 4 0xe8,0x44,0x00,0x81 = ldu 2, 128(4) 0x7c,0x43,0x20,0x6a = ldux 2, 3, 4 0x98,0x44,0x00,0x80 = stb 2, 128(4) 0x7c,0x43,0x21,0xae = stbx 2, 3, 4 0x9c,0x44,0x00,0x80 = stbu 2, 128(4) 0x7c,0x43,0x21,0xee = stbux 2, 3, 4 0xb0,0x44,0x00,0x80 = sth 2, 128(4) 0x7c,0x43,0x23,0x2e = sthx 2, 3, 4 0xb4,0x44,0x00,0x80 = sthu 2, 128(4) 0x7c,0x43,0x23,0x6e = sthux 2, 3, 4 0x90,0x44,0x00,0x80 = stw 2, 128(4) 0x7c,0x43,0x21,0x2e = stwx 2, 3, 4 0x94,0x44,0x00,0x80 = stwu 2, 128(4) 0x7c,0x43,0x21,0x6e = stwux 2, 3, 4 0xf8,0x44,0x00,0x80 = std 2, 128(4) 0x7c,0x43,0x21,0x2a = stdx 2, 3, 4 0xf8,0x44,0x00,0x81 = stdu 2, 128(4) 0x7c,0x43,0x21,0x6a = stdux 2, 3, 4 0x7c,0x43,0x26,0x2c = lhbrx 2, 3, 4 0x7c,0x43,0x27,0x2c = sthbrx 2, 3, 4 0x7c,0x43,0x24,0x2c = lwbrx 2, 3, 4 0x7c,0x43,0x25,0x2c = stwbrx 2, 3, 4 0x7c,0x43,0x24,0x28 = ldbrx 2, 3, 4 0x7c,0x43,0x25,0x28 = stdbrx 2, 3, 4 0xb8,0x41,0x00,0x80 = lmw 2, 128(1) 0xbc,0x41,0x00,0x80 = stmw 2, 128(1) 0x38,0x43,0x00,0x80 = addi 2, 3, 128 0x3c,0x43,0x00,0x80 = addis 2, 3, 128 0x7c,0x43,0x22,0x14 = add 2, 3, 4 0x7c,0x43,0x22,0x15 = add. 2, 3, 4 0x7c,0x43,0x20,0x50 = subf 2, 3, 4 0x7c,0x43,0x20,0x51 = subf. 2, 3, 4 0x30,0x43,0x00,0x80 = addic 2, 3, 128 0x34,0x43,0x00,0x80 = addic. 2, 3, 128 0x20,0x43,0x00,0x04 = subfic 2, 3, 4 0x7c,0x43,0x20,0x14 = addc 2, 3, 4 0x7c,0x43,0x20,0x15 = addc. 2, 3, 4 0x7c,0x43,0x20,0x10 = subfc 2, 3, 4 0x7c,0x43,0x20,0x10 = subfc 2, 3, 4 0x7c,0x43,0x21,0x14 = adde 2, 3, 4 0x7c,0x43,0x21,0x15 = adde. 2, 3, 4 0x7c,0x43,0x21,0x10 = subfe 2, 3, 4 0x7c,0x43,0x21,0x11 = subfe. 2, 3, 4 0x7c,0x43,0x01,0xd4 = addme 2, 3 0x7c,0x43,0x01,0xd5 = addme. 2, 3 0x7c,0x43,0x01,0xd0 = subfme 2, 3 0x7c,0x43,0x01,0xd1 = subfme. 2, 3 0x7c,0x43,0x01,0x94 = addze 2, 3 0x7c,0x43,0x01,0x95 = addze. 2, 3 0x7c,0x43,0x01,0x90 = subfze 2, 3 0x7c,0x43,0x01,0x91 = subfze. 2, 3 0x7c,0x43,0x00,0xd0 = neg 2, 3 0x7c,0x43,0x00,0xd1 = neg. 2, 3 0x1c,0x43,0x00,0x80 = mulli 2, 3, 128 0x7c,0x43,0x20,0x96 = mulhw 2, 3, 4 0x7c,0x43,0x20,0x97 = mulhw. 2, 3, 4 0x7c,0x43,0x21,0xd6 = mullw 2, 3, 4 0x7c,0x43,0x21,0xd7 = mullw. 2, 3, 4 0x7c,0x43,0x20,0x16 = mulhwu 2, 3, 4 0x7c,0x43,0x20,0x17 = mulhwu. 2, 3, 4 0x7c,0x43,0x23,0xd6 = divw 2, 3, 4 0x7c,0x43,0x23,0xd7 = divw. 2, 3, 4 0x7c,0x43,0x23,0x96 = divwu 2, 3, 4 0x7c,0x43,0x23,0x97 = divwu. 2, 3, 4 0x7c,0x43,0x21,0xd2 = mulld 2, 3, 4 0x7c,0x43,0x21,0xd3 = mulld. 2, 3, 4 0x7c,0x43,0x20,0x92 = mulhd 2, 3, 4 0x7c,0x43,0x20,0x93 = mulhd. 2, 3, 4 0x7c,0x43,0x20,0x12 = mulhdu 2, 3, 4 0x7c,0x43,0x20,0x13 = mulhdu. 2, 3, 4 0x7c,0x43,0x23,0xd2 = divd 2, 3, 4 0x7c,0x43,0x23,0xd3 = divd. 2, 3, 4 0x7c,0x43,0x23,0x92 = divdu 2, 3, 4 0x7c,0x43,0x23,0x93 = divdu. 2, 3, 4 0x2d,0x23,0x00,0x80 = cmpdi 2, 3, 128 0x7d,0x23,0x20,0x00 = cmpd 2, 3, 4 0x29,0x23,0x00,0x80 = cmpldi 2, 3, 128 0x7d,0x23,0x20,0x40 = cmpld 2, 3, 4 0x2d,0x03,0x00,0x80 = cmpwi 2, 3, 128 0x7d,0x03,0x20,0x00 = cmpw 2, 3, 4 0x29,0x03,0x00,0x80 = cmplwi 2, 3, 128 0x7d,0x03,0x20,0x40 = cmplw 2, 3, 4 // 0x0c,0x43,0x00,0x04 = twi 2, 3, 4 // 0x7c,0x43,0x20,0x08 = tw 2, 3, 4 // 0x08,0x43,0x00,0x04 = tdi 2, 3, 4 // 0x7c,0x43,0x20,0x88 = td 2, 3, 4 0x7c,0x43,0x21,0x5e = isel r2, r3, r4, cr1gt 0x70,0x62,0x00,0x80 = andi. 2, 3, 128 0x74,0x62,0x00,0x80 = andis. 2, 3, 128 0x60,0x62,0x00,0x80 = ori 2, 3, 128 0x64,0x62,0x00,0x80 = oris 2, 3, 128 0x68,0x62,0x00,0x80 = xori 2, 3, 128 0x6c,0x62,0x00,0x80 = xoris 2, 3, 128 0x7c,0x62,0x20,0x38 = and 2, 3, 4 0x7c,0x62,0x20,0x39 = and. 2, 3, 4 0x7c,0x62,0x22,0x78 = xor 2, 3, 4 0x7c,0x62,0x22,0x79 = xor. 2, 3, 4 0x7c,0x62,0x23,0xb8 = nand 2, 3, 4 0x7c,0x62,0x23,0xb9 = nand. 2, 3, 4 0x7c,0x62,0x23,0x78 = or 2, 3, 4 0x7c,0x62,0x23,0x79 = or. 2, 3, 4 0x7c,0x62,0x20,0xf8 = nor 2, 3, 4 0x7c,0x62,0x20,0xf9 = nor. 2, 3, 4 0x7c,0x62,0x22,0x38 = eqv 2, 3, 4 0x7c,0x62,0x22,0x39 = eqv. 2, 3, 4 0x7c,0x62,0x20,0x78 = andc 2, 3, 4 0x7c,0x62,0x20,0x79 = andc. 2, 3, 4 0x7c,0x62,0x23,0x38 = orc 2, 3, 4 0x7c,0x62,0x23,0x39 = orc. 2, 3, 4 0x7c,0x62,0x07,0x74 = extsb 2, 3 0x7c,0x62,0x07,0x75 = extsb. 2, 3 0x7c,0x62,0x07,0x34 = extsh 2, 3 0x7c,0x62,0x07,0x35 = extsh. 2, 3 // 0x7c,0x62,0x00,0x34 = cntlzw 2, 3 // 0x7c,0x62,0x00,0x35 = cntlzw. 2, 3 0x7c,0x62,0x02,0xf4 = popcntw 2, 3 0x7c,0x62,0x07,0xb4 = extsw 2, 3 0x7c,0x62,0x07,0xb5 = extsw. 2, 3 0x7c,0x62,0x00,0x74 = cntlzd 2, 3 0x7c,0x62,0x00,0x75 = cntlzd. 2, 3 0x7c,0x62,0x03,0xf4 = popcntd 2, 3 0x54,0x62,0x21,0x4c = rlwinm 2, 3, 4, 5, 6 0x54,0x62,0x21,0x4d = rlwinm. 2, 3, 4, 5, 6 0x5c,0x62,0x21,0x4c = rlwnm 2, 3, 4, 5, 6 0x5c,0x62,0x21,0x4d = rlwnm. 2, 3, 4, 5, 6 0x50,0x62,0x21,0x4c = rlwimi 2, 3, 4, 5, 6 0x50,0x62,0x21,0x4d = rlwimi. 2, 3, 4, 5, 6 0x78,0x62,0x21,0x40 = rldicl 2, 3, 4, 5 0x78,0x62,0x21,0x41 = rldicl. 2, 3, 4, 5 0x78,0x62,0x21,0x44 = rldicr 2, 3, 4, 5 0x78,0x62,0x21,0x45 = rldicr. 2, 3, 4, 5 0x78,0x62,0x21,0x48 = rldic 2, 3, 4, 5 0x78,0x62,0x21,0x49 = rldic. 2, 3, 4, 5 0x78,0x62,0x21,0x50 = rldcl 2, 3, 4, 5 0x78,0x62,0x21,0x51 = rldcl. 2, 3, 4, 5 0x78,0x62,0x21,0x52 = rldcr 2, 3, 4, 5 0x78,0x62,0x21,0x53 = rldcr. 2, 3, 4, 5 0x78,0x62,0x21,0x4c = rldimi 2, 3, 4, 5 0x78,0x62,0x21,0x4d = rldimi. 2, 3, 4, 5 0x7c,0x62,0x20,0x30 = slw 2, 3, 4 0x7c,0x62,0x20,0x31 = slw. 2, 3, 4 0x7c,0x62,0x24,0x30 = srw 2, 3, 4 0x7c,0x62,0x24,0x31 = srw. 2, 3, 4 0x7c,0x62,0x26,0x70 = srawi 2, 3, 4 0x7c,0x62,0x26,0x71 = srawi. 2, 3, 4 0x7c,0x62,0x26,0x30 = sraw 2, 3, 4 0x7c,0x62,0x26,0x31 = sraw. 2, 3, 4 0x7c,0x62,0x20,0x36 = sld 2, 3, 4 0x7c,0x62,0x20,0x37 = sld. 2, 3, 4 0x7c,0x62,0x24,0x36 = srd 2, 3, 4 0x7c,0x62,0x24,0x37 = srd. 2, 3, 4 0x7c,0x62,0x26,0x74 = sradi 2, 3, 4 0x7c,0x62,0x26,0x75 = sradi. 2, 3, 4 0x7c,0x62,0x26,0x34 = srad 2, 3, 4 0x7c,0x62,0x26,0x35 = srad. 2, 3, 4 0x7c,0x58,0x93,0xa6 = mtspr 600, 2 0x7c,0x58,0x92,0xa6 = mfspr 2, 600 0x7c,0x47,0xb1,0x20 = mtcrf 123, 2 0x7c,0x40,0x00,0x26 = mfcr 2 0x7c,0x51,0x01,0x20 = mtocrf 16, 2 0x7e,0x10,0x80,0x26 = mfocrf 16, 8 capstone-sys-0.15.0/capstone/suite/MC/PowerPC/ppc64-operands.s.cs000064400000000000000000000021150072674642500225060ustar 00000000000000# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME 0x7c,0x22,0x1a,0x14 = add 1, 2, 3 0x7c,0x22,0x1a,0x14 = add 1, 2, 3 0x7c,0x00,0x02,0x14 = add 0, 0, 0 0x7f,0xff,0xfa,0x14 = add 31, 31, 31 0x38,0x20,0x00,0x00 = li 1, 0 0x38,0x22,0x00,0x00 = addi 1, 2, 0 0x38,0x20,0x80,0x00 = li 1, -0x8000 0x38,0x20,0x7f,0xff = li 1, 0x7fff 0x60,0x41,0x00,0x00 = ori 1, 2, 0 0x60,0x41,0xff,0xff = ori 1, 2, 65535 0x3c,0x20,0x00,0x00 = lis 1, 0 0x3c,0x20,0xff,0xff = lis 1, -1 0x80,0x20,0x00,0x00 = lwz 1, 0(0) 0x80,0x20,0x00,0x00 = lwz 1, 0(0) 0x80,0x3f,0x00,0x00 = lwz 1, 0(31) 0x80,0x3f,0x00,0x00 = lwz 1, 0(31) 0x80,0x22,0x80,0x00 = lwz 1, -32768(2) 0x80,0x22,0x7f,0xff = lwz 1, 32767(2) 0xe8,0x20,0x00,0x00 = ld 1, 0(0) 0xe8,0x20,0x00,0x00 = ld 1, 0(0) 0xe8,0x3f,0x00,0x00 = ld 1, 0(31) 0xe8,0x3f,0x00,0x00 = ld 1, 0(31) 0xe8,0x22,0x80,0x00 = ld 1, -32768(2) 0xe8,0x22,0x7f,0xfc = ld 1, 32764(2) 0xe8,0x22,0x00,0x04 = ld 1, 4(2) 0xe8,0x22,0xff,0xfc = ld 1, -4(2) // 0x48,0x00,0x04,0x00 = b .+1024 0x48,0x00,0x04,0x02 = ba 1024 // 0x41,0x82,0x04,0x00 = beq 0, .+1024 // 0x41,0x82,0x04,0x02 = beqa 0, 1024 capstone-sys-0.15.0/capstone/suite/MC/README000064400000000000000000000003760072674642500165210ustar 00000000000000Input files for testing Capstone engine. Format of input files: # ARCH, MODE, OPTION hexcode = assembly Format of issue file: # ARCH, MODE, OPTION hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_countcapstone-sys-0.15.0/capstone/suite/MC/RISCV/insn-riscv32.s.cs000064400000000000000000000006570072674642500215610ustar 00000000000000# CS_ARCH_RISCV, CS_MODE_RISCV32, None 0x37,0x34,0x00,0x00 = lui s0, 3 0x97,0x82,0x00,0x00 = auipc t0, 8 0x2f,0xae,0xaa,0x0a = amoswap.w.rl t3, a0, (s5) 0xe3,0x1f,0x31,0x5e = bne sp, gp, 0xdfe 0x73,0x00,0x00,0x00 = ecall 0x33,0x00,0x31,0x02 = mul zero, sp, gp 0x53,0x00,0x31,0x28 = fmin.s ft0, ft2, ft3 0x53,0x10,0x31,0x2a = fmax.d ft0, ft2, ft3 0x27,0xaa,0x6a,0x00 = fsw ft6, 0x14(s5) // issues 0xef,0xf0,0x1f,0xff = jal -0x10 capstone-sys-0.15.0/capstone/suite/MC/RISCV/insn-riscv64.s.cs000064400000000000000000000004470072674642500215630ustar 00000000000000# CS_ARCH_RISCV, CS_MODE_RISCV64, None 0x13,0x04,0xa8,0x7a = addi s0, a6, 0x7aa 0x1b,0x8e,0xaa,0x2a = addiw t3, s5, 0x2aa 0x2f,0xbe,0xaa,0x0a = amoswap.d.rl t3, a0, (s5) 0x3b,0x00,0x31,0x02 = mulw zero, sp, gp 0x53,0xa0,0x31,0xd0 = fcvt.s.lu ft0, gp, rdn 0x53,0x81,0x01,0xf2 = fmv.d.x ft2, gp capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc-alu-instructions.s.cs000064400000000000000000000035550072674642500241340ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x80,0x00,0x00,0x00 = add %g0, %g0, %g0 0x86,0x00,0x40,0x02 = add %g1, %g2, %g3 0xa0,0x02,0x00,0x09 = add %o0, %o1, %l0 0xa0,0x02,0x20,0x0a = add %o0, 10, %l0 0x86,0x80,0x40,0x02 = addcc %g1, %g2, %g3 0x86,0xc0,0x40,0x02 = addxcc %g1, %g2, %g3 0x86,0x70,0x40,0x02 = udiv %g1, %g2, %g3 0x86,0x78,0x40,0x02 = sdiv %g1, %g2, %g3 0x86,0x08,0x40,0x02 = and %g1, %g2, %g3 0x86,0x28,0x40,0x02 = andn %g1, %g2, %g3 0x86,0x10,0x40,0x02 = or %g1, %g2, %g3 0x86,0x30,0x40,0x02 = orn %g1, %g2, %g3 0x86,0x18,0x40,0x02 = xor %g1, %g2, %g3 0x86,0x38,0x40,0x02 = xnor %g1, %g2, %g3 0x86,0x50,0x40,0x02 = umul %g1, %g2, %g3 0x86,0x58,0x40,0x02 = smul %g1, %g2, %g3 0x01,0x00,0x00,0x00 = nop 0x21,0x00,0x00,0x0a = sethi 10, %l0 0x87,0x28,0x40,0x02 = sll %g1, %g2, %g3 0x87,0x28,0x60,0x1f = sll %g1, 31, %g3 0x87,0x30,0x40,0x02 = srl %g1, %g2, %g3 0x87,0x30,0x60,0x1f = srl %g1, 31, %g3 0x87,0x38,0x40,0x02 = sra %g1, %g2, %g3 0x87,0x38,0x60,0x1f = sra %g1, 31, %g3 0x86,0x20,0x40,0x02 = sub %g1, %g2, %g3 0x86,0xa0,0x40,0x02 = subcc %g1, %g2, %g3 0x86,0xe0,0x40,0x02 = subxcc %g1, %g2, %g3 0x86,0x10,0x00,0x01 = mov %g1, %g3 0x86,0x10,0x20,0xff = mov 0xff, %g3 0x81,0xe8,0x00,0x00 = restore 0x86,0x40,0x80,0x01 = addx %g2, %g1, %g3 0x86,0x60,0x80,0x01 = subx %g2, %g1, %g3 0x86,0xd0,0x80,0x01 = umulcc %g2, %g1, %g3 0x86,0xd8,0x80,0x01 = smulcc %g2, %g1, %g3 0x86,0xf0,0x80,0x01 = udivcc %g2, %g1, %g3 0x86,0xf8,0x80,0x01 = sdivcc %g2, %g1, %g3 0x86,0x88,0x80,0x01 = andcc %g2, %g1, %g3 0x86,0xa8,0x80,0x01 = andncc %g2, %g1, %g3 0x86,0x90,0x80,0x01 = orcc %g2, %g1, %g3 0x86,0xb0,0x80,0x01 = orncc %g2, %g1, %g3 0x86,0x98,0x80,0x01 = xorcc %g2, %g1, %g3 0x86,0xb8,0x80,0x01 = xnorcc %g2, %g1, %g3 0x87,0x00,0x80,0x01 = taddcc %g2, %g1, %g3 0x87,0x08,0x80,0x01 = tsubcc %g2, %g1, %g3 0x87,0x10,0x80,0x01 = taddcctv %g2, %g1, %g3 0x87,0x18,0x80,0x01 = tsubcctv %g2, %g1, %g3 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc-atomic-instructions.s.cs000064400000000000000000000004170072674642500246210ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x81,0x43,0xe0,0x0f = membar 15 0x81,0x43,0xc0,0x00 = stbar 0xd4,0x7e,0x00,0x16 = swap [%i0+%l6], %o2 0xd4,0x7e,0x20,0x20 = swap [%i0+32], %o2 0xd5,0xe6,0x10,0x16 = cas [%i0], %l6, %o2 0xd5,0xf6,0x10,0x16 = casx [%i0], %l6, %o2 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc-ctrl-instructions.s.cs000064400000000000000000000006000072674642500243030ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x9f,0xc0,0x40,0x1a = call %g1+%i2 0x9f,0xc2,0x60,0x08 = call %o1+8 0x9f,0xc0,0x60,0x00 = call %g1 0x81,0xc0,0x40,0x1a = jmp %g1+%i2 0x81,0xc2,0x60,0x08 = jmp %o1+8 0x81,0xc0,0x60,0x00 = jmp %g1 0x85,0xc0,0x40,0x1a = jmpl %g1+%i2, %g2 0x85,0xc2,0x60,0x08 = jmpl %o1+8, %g2 0x85,0xc0,0x60,0x00 = jmpl %g1, %g2 0x81,0xcf,0xe0,0x08 = rett %i7+8 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc-fp-instructions.s.cs000064400000000000000000000045400072674642500237530ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, None 0x89,0xa0,0x18,0x80 = fitos %f0, %f4 0x89,0xa0,0x19,0x00 = fitod %f0, %f4 0x89,0xa0,0x19,0x80 = fitoq %f0, %f4 0x89,0xa0,0x1a,0x20 = fstoi %f0, %f4 0x89,0xa0,0x1a,0x40 = fdtoi %f0, %f4 0x89,0xa0,0x1a,0x60 = fqtoi %f0, %f4 0x89,0xa0,0x19,0x20 = fstod %f0, %f4 0x89,0xa0,0x19,0xa0 = fstoq %f0, %f4 0x89,0xa0,0x18,0xc0 = fdtos %f0, %f4 0x89,0xa0,0x19,0xc0 = fdtoq %f0, %f4 0x89,0xa0,0x18,0xe0 = fqtos %f0, %f4 0x89,0xa0,0x19,0x60 = fqtod %f0, %f4 0x89,0xa0,0x00,0x20 = fmovs %f0, %f4 0x89,0xa0,0x00,0x40 = fmovd %f0, %f4 0x89,0xa0,0x00,0x60 = fmovq %f0, %f4 0x89,0xa0,0x00,0xa0 = fnegs %f0, %f4 0x89,0xa0,0x00,0xc0 = fnegd %f0, %f4 0x89,0xa0,0x00,0xe0 = fnegq %f0, %f4 0x89,0xa0,0x01,0x20 = fabss %f0, %f4 0x89,0xa0,0x01,0x40 = fabsd %f0, %f4 0x89,0xa0,0x01,0x60 = fabsq %f0, %f4 0x89,0xa0,0x05,0x20 = fsqrts %f0, %f4 0x89,0xa0,0x05,0x40 = fsqrtd %f0, %f4 0x89,0xa0,0x05,0x60 = fsqrtq %f0, %f4 0x91,0xa0,0x08,0x24 = fadds %f0, %f4, %f8 0x91,0xa0,0x08,0x44 = faddd %f0, %f4, %f8 0x91,0xa0,0x08,0x64 = faddq %f0, %f4, %f8 0xbf,0xa0,0x48,0x43 = faddd %f32, %f34, %f62 0xbb,0xa0,0x48,0x65 = faddq %f32, %f36, %f60 0x91,0xa0,0x08,0xa4 = fsubs %f0, %f4, %f8 0x91,0xa0,0x08,0xc4 = fsubd %f0, %f4, %f8 0x91,0xa0,0x08,0xe4 = fsubq %f0, %f4, %f8 0x91,0xa0,0x09,0x24 = fmuls %f0, %f4, %f8 0x91,0xa0,0x09,0x44 = fmuld %f0, %f4, %f8 0x91,0xa0,0x09,0x64 = fmulq %f0, %f4, %f8 0x91,0xa0,0x0d,0x24 = fsmuld %f0, %f4, %f8 0x91,0xa0,0x0d,0xc4 = fdmulq %f0, %f4, %f8 0x91,0xa0,0x09,0xa4 = fdivs %f0, %f4, %f8 0x91,0xa0,0x09,0xc4 = fdivd %f0, %f4, %f8 0x91,0xa0,0x09,0xe4 = fdivq %f0, %f4, %f8 // 0x81,0xa8,0x0a,0x24 = fcmps %fcc0, %f0, %f4 // 0x81,0xa8,0x0a,0x44 = fcmpd %fcc0, %f0, %f4 // 0x81,0xa8,0x0a,0x64 = fcmpq %fcc0, %f0, %f4 // 0x81,0xa8,0x0a,0xa4 = fcmpes %fcc0, %f0, %f4 // 0x81,0xa8,0x0a,0xc4 = fcmped %fcc0, %f0, %f4 // 0x81,0xa8,0x0a,0xe4 = fcmpeq %fcc0, %f0, %f4 0x85,0xa8,0x0a,0x24 = fcmps %fcc2, %f0, %f4 0x85,0xa8,0x0a,0x44 = fcmpd %fcc2, %f0, %f4 0x85,0xa8,0x0a,0x64 = fcmpq %fcc2, %f0, %f4 0x85,0xa8,0x0a,0xa4 = fcmpes %fcc2, %f0, %f4 0x85,0xa8,0x0a,0xc4 = fcmped %fcc2, %f0, %f4 0x85,0xa8,0x0a,0xe4 = fcmpeq %fcc2, %f0, %f4 0x89,0xa0,0x10,0x80 = fxtos %f0, %f4 0x89,0xa0,0x11,0x00 = fxtod %f0, %f4 0x89,0xa0,0x11,0x80 = fxtoq %f0, %f4 0x89,0xa0,0x10,0x20 = fstox %f0, %f4 0x89,0xa0,0x10,0x40 = fdtox %f0, %f4 0x89,0xa0,0x10,0x60 = fqtox %f0, %f4 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc-mem-instructions.s.cs000064400000000000000000000017400072674642500241230ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0xd4,0x4e,0x00,0x16 = ldsb [%i0+%l6], %o2 0xd4,0x4e,0x20,0x20 = ldsb [%i0+32], %o2 0xd8,0x48,0x60,0x00 = ldsb [%g1], %o4 0xd4,0x56,0x00,0x16 = ldsh [%i0+%l6], %o2 0xd4,0x56,0x20,0x20 = ldsh [%i0+32], %o2 0xd8,0x50,0x60,0x00 = ldsh [%g1], %o4 0xd4,0x0e,0x00,0x16 = ldub [%i0+%l6], %o2 0xd4,0x0e,0x20,0x20 = ldub [%i0+32], %o2 0xd4,0x08,0x60,0x00 = ldub [%g1], %o2 0xd4,0x16,0x00,0x16 = lduh [%i0+%l6], %o2 0xd4,0x16,0x20,0x20 = lduh [%i0+32], %o2 0xd4,0x10,0x60,0x00 = lduh [%g1], %o2 0xd4,0x06,0x00,0x16 = ld [%i0+%l6], %o2 0xd4,0x06,0x20,0x20 = ld [%i0+32], %o2 0xd4,0x00,0x60,0x00 = ld [%g1], %o2 0xd4,0x2e,0x00,0x16 = stb %o2, [%i0+%l6] 0xd4,0x2e,0x20,0x20 = stb %o2, [%i0+32] 0xd4,0x28,0x60,0x00 = stb %o2, [%g1] 0xd4,0x36,0x00,0x16 = sth %o2, [%i0+%l6] 0xd4,0x36,0x20,0x20 = sth %o2, [%i0+32] 0xd4,0x30,0x60,0x00 = sth %o2, [%g1] 0xd4,0x26,0x00,0x16 = st %o2, [%i0+%l6] 0xd4,0x26,0x20,0x20 = st %o2, [%i0+32] 0xd4,0x20,0x60,0x00 = st %o2, [%g1] capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc-vis.s.cs000064400000000000000000000001140072674642500213760ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0xbf,0xb0,0x0c,0x20 = fzeros %f31 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc64-alu-instructions.s.cs000064400000000000000000000010240072674642500242730ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0xb1,0x28,0x50,0x1a = sllx %g1, %i2, %i0 0xb1,0x28,0x70,0x3f = sllx %g1, 63, %i0 0xb1,0x30,0x50,0x1a = srlx %g1, %i2, %i0 0xb1,0x30,0x70,0x3f = srlx %g1, 63, %i0 0xb1,0x38,0x50,0x1a = srax %g1, %i2, %i0 0xb1,0x38,0x70,0x3f = srax %g1, 63, %i0 0xb0,0x48,0x40,0x1a = mulx %g1, %i2, %i0 0xb0,0x48,0x60,0x3f = mulx %g1, 63, %i0 0xb1,0x68,0x40,0x1a = sdivx %g1, %i2, %i0 0xb1,0x68,0x60,0x3f = sdivx %g1, 63, %i0 0xb0,0x68,0x40,0x1a = udivx %g1, %i2, %i0 0xb0,0x68,0x60,0x3f = udivx %g1, 63, %i0 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparc64-ctrl-instructions.s.cs000064400000000000000000000106140072674642500244630ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x85,0x66,0x40,0x01 = movne %icc, %g1, %g2 0x85,0x64,0x40,0x01 = move %icc, %g1, %g2 0x85,0x66,0x80,0x01 = movg %icc, %g1, %g2 0x85,0x64,0x80,0x01 = movle %icc, %g1, %g2 0x85,0x66,0xc0,0x01 = movge %icc, %g1, %g2 0x85,0x64,0xc0,0x01 = movl %icc, %g1, %g2 0x85,0x67,0x00,0x01 = movgu %icc, %g1, %g2 0x85,0x65,0x00,0x01 = movleu %icc, %g1, %g2 0x85,0x67,0x40,0x01 = movcc %icc, %g1, %g2 0x85,0x65,0x40,0x01 = movcs %icc, %g1, %g2 0x85,0x67,0x80,0x01 = movpos %icc, %g1, %g2 0x85,0x65,0x80,0x01 = movneg %icc, %g1, %g2 0x85,0x67,0xc0,0x01 = movvc %icc, %g1, %g2 0x85,0x65,0xc0,0x01 = movvs %icc, %g1, %g2 0x85,0x66,0x50,0x01 = movne %xcc, %g1, %g2 0x85,0x64,0x50,0x01 = move %xcc, %g1, %g2 0x85,0x66,0x90,0x01 = movg %xcc, %g1, %g2 0x85,0x64,0x90,0x01 = movle %xcc, %g1, %g2 0x85,0x66,0xd0,0x01 = movge %xcc, %g1, %g2 0x85,0x64,0xd0,0x01 = movl %xcc, %g1, %g2 0x85,0x67,0x10,0x01 = movgu %xcc, %g1, %g2 0x85,0x65,0x10,0x01 = movleu %xcc, %g1, %g2 0x85,0x67,0x50,0x01 = movcc %xcc, %g1, %g2 0x85,0x65,0x50,0x01 = movcs %xcc, %g1, %g2 0x85,0x67,0x90,0x01 = movpos %xcc, %g1, %g2 0x85,0x65,0x90,0x01 = movneg %xcc, %g1, %g2 0x85,0x67,0xd0,0x01 = movvc %xcc, %g1, %g2 0x85,0x65,0xd0,0x01 = movvs %xcc, %g1, %g2 0x85,0x61,0xc0,0x01 = movu %fcc0, %g1, %g2 0x85,0x61,0x80,0x01 = movg %fcc0, %g1, %g2 0x85,0x61,0x40,0x01 = movug %fcc0, %g1, %g2 0x85,0x61,0x00,0x01 = movl %fcc0, %g1, %g2 0x85,0x60,0xc0,0x01 = movul %fcc0, %g1, %g2 0x85,0x60,0x80,0x01 = movlg %fcc0, %g1, %g2 0x85,0x60,0x40,0x01 = movne %fcc0, %g1, %g2 0x85,0x62,0x40,0x01 = move %fcc0, %g1, %g2 0x85,0x62,0x80,0x01 = movue %fcc0, %g1, %g2 0x85,0x62,0xc0,0x01 = movge %fcc0, %g1, %g2 0x85,0x63,0x00,0x01 = movuge %fcc0, %g1, %g2 0x85,0x63,0x40,0x01 = movle %fcc0, %g1, %g2 0x85,0x63,0x80,0x01 = movule %fcc0, %g1, %g2 0x85,0x63,0xc0,0x01 = movo %fcc0, %g1, %g2 0x85,0xaa,0x60,0x21 = fmovsne %icc, %f1, %f2 0x85,0xa8,0x60,0x21 = fmovse %icc, %f1, %f2 0x85,0xaa,0xa0,0x21 = fmovsg %icc, %f1, %f2 0x85,0xa8,0xa0,0x21 = fmovsle %icc, %f1, %f2 0x85,0xaa,0xe0,0x21 = fmovsge %icc, %f1, %f2 0x85,0xa8,0xe0,0x21 = fmovsl %icc, %f1, %f2 0x85,0xab,0x20,0x21 = fmovsgu %icc, %f1, %f2 0x85,0xa9,0x20,0x21 = fmovsleu %icc, %f1, %f2 0x85,0xab,0x60,0x21 = fmovscc %icc, %f1, %f2 0x85,0xa9,0x60,0x21 = fmovscs %icc, %f1, %f2 0x85,0xab,0xa0,0x21 = fmovspos %icc, %f1, %f2 0x85,0xa9,0xa0,0x21 = fmovsneg %icc, %f1, %f2 0x85,0xab,0xe0,0x21 = fmovsvc %icc, %f1, %f2 0x85,0xa9,0xe0,0x21 = fmovsvs %icc, %f1, %f2 0x85,0xaa,0x70,0x21 = fmovsne %xcc, %f1, %f2 0x85,0xa8,0x70,0x21 = fmovse %xcc, %f1, %f2 0x85,0xaa,0xb0,0x21 = fmovsg %xcc, %f1, %f2 0x85,0xa8,0xb0,0x21 = fmovsle %xcc, %f1, %f2 0x85,0xaa,0xf0,0x21 = fmovsge %xcc, %f1, %f2 0x85,0xa8,0xf0,0x21 = fmovsl %xcc, %f1, %f2 0x85,0xab,0x30,0x21 = fmovsgu %xcc, %f1, %f2 0x85,0xa9,0x30,0x21 = fmovsleu %xcc, %f1, %f2 0x85,0xab,0x70,0x21 = fmovscc %xcc, %f1, %f2 0x85,0xa9,0x70,0x21 = fmovscs %xcc, %f1, %f2 0x85,0xab,0xb0,0x21 = fmovspos %xcc, %f1, %f2 0x85,0xa9,0xb0,0x21 = fmovsneg %xcc, %f1, %f2 0x85,0xab,0xf0,0x21 = fmovsvc %xcc, %f1, %f2 0x85,0xa9,0xf0,0x21 = fmovsvs %xcc, %f1, %f2 0x85,0xa9,0xc0,0x21 = fmovsu %fcc0, %f1, %f2 0x85,0xa9,0x80,0x21 = fmovsg %fcc0, %f1, %f2 0x85,0xa9,0x40,0x21 = fmovsug %fcc0, %f1, %f2 0x85,0xa9,0x00,0x21 = fmovsl %fcc0, %f1, %f2 0x85,0xa8,0xc0,0x21 = fmovsul %fcc0, %f1, %f2 0x85,0xa8,0x80,0x21 = fmovslg %fcc0, %f1, %f2 0x85,0xa8,0x40,0x21 = fmovsne %fcc0, %f1, %f2 0x85,0xaa,0x40,0x21 = fmovse %fcc0, %f1, %f2 0x85,0xaa,0x80,0x21 = fmovsue %fcc0, %f1, %f2 0x85,0xaa,0xc0,0x21 = fmovsge %fcc0, %f1, %f2 0x85,0xab,0x00,0x21 = fmovsuge %fcc0, %f1, %f2 0x85,0xab,0x40,0x21 = fmovsle %fcc0, %f1, %f2 0x85,0xab,0x80,0x21 = fmovsule %fcc0, %f1, %f2 0x85,0xab,0xc0,0x21 = fmovso %fcc0, %f1, %f2 0x85,0x61,0xc8,0x01 = movu %fcc1, %g1, %g2 0x85,0xa9,0x90,0x21 = fmovsg %fcc2, %f1, %f2 0x87,0x78,0x44,0x02 = movrz %g1, %g2, %g3 0x87,0x78,0x48,0x02 = movrlez %g1, %g2, %g3 0x87,0x78,0x4c,0x02 = movrlz %g1, %g2, %g3 0x87,0x78,0x54,0x02 = movrnz %g1, %g2, %g3 0x87,0x78,0x58,0x02 = movrgz %g1, %g2, %g3 0x87,0x78,0x5c,0x02 = movrgez %g1, %g2, %g3 0x87,0xa8,0x44,0xa2 = fmovrsz %g1, %f2, %f3 0x87,0xa8,0x48,0xa2 = fmovrslez %g1, %f2, %f3 0x87,0xa8,0x4c,0xa2 = fmovrslz %g1, %f2, %f3 0x87,0xa8,0x54,0xa2 = fmovrsnz %g1, %f2, %f3 0x87,0xa8,0x58,0xa2 = fmovrsgz %g1, %f2, %f3 0x87,0xa8,0x5c,0xa2 = fmovrsgez %g1, %f2, %f3 0x81,0xcf,0xe0,0x08 = rett %i7+8 // 0x91,0xd0,0x20,0x05 = ta %icc, %g0 + 5 0x83,0xd0,0x30,0x03 = te %xcc, %g0 + 3 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparcv8-instructions.s.cs000064400000000000000000000004130072674642500236210ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x81,0xa8,0x0a,0x24 = fcmps %f0, %f4 0x81,0xa8,0x0a,0x44 = fcmpd %f0, %f4 0x81,0xa8,0x0a,0x64 = fcmpq %f0, %f4 0x81,0xa8,0x0a,0xa4 = fcmpes %f0, %f4 0x81,0xa8,0x0a,0xc4 = fcmped %f0, %f4 0x81,0xa8,0x0a,0xe4 = fcmpeq %f0, %f4 capstone-sys-0.15.0/capstone/suite/MC/Sparc/sparcv9-instructions.s.cs000064400000000000000000000000520072674642500236210ustar 00000000000000# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None capstone-sys-0.15.0/capstone/suite/MC/SystemZ/insn-good-z196.s.cs000064400000000000000000000676500072674642500224630ustar 00000000000000# CS_ARCH_SYSZ, 0, None 0xec,0x00,0x80,0x00,0x00,0xd9 = aghik %r0, %r0, -32768 0xec,0x00,0xff,0xff,0x00,0xd9 = aghik %r0, %r0, -1 0xec,0x00,0x00,0x00,0x00,0xd9 = aghik %r0, %r0, 0 0xec,0x00,0x00,0x01,0x00,0xd9 = aghik %r0, %r0, 1 0xec,0x00,0x7f,0xff,0x00,0xd9 = aghik %r0, %r0, 32767 0xec,0x0f,0x00,0x00,0x00,0xd9 = aghik %r0, %r15, 0 0xec,0xf0,0x00,0x00,0x00,0xd9 = aghik %r15, %r0, 0 0xec,0x78,0xff,0xf0,0x00,0xd9 = aghik %r7, %r8, -16 0xb9,0xe8,0x00,0x00 = agrk %r0, %r0, %r0 0xb9,0xe8,0xf0,0x00 = agrk %r0, %r0, %r15 0xb9,0xe8,0x00,0x0f = agrk %r0, %r15, %r0 0xb9,0xe8,0x00,0xf0 = agrk %r15, %r0, %r0 0xb9,0xe8,0x90,0x78 = agrk %r7, %r8, %r9 0xec,0x00,0x80,0x00,0x00,0xd8 = ahik %r0, %r0, -32768 0xec,0x00,0xff,0xff,0x00,0xd8 = ahik %r0, %r0, -1 0xec,0x00,0x00,0x00,0x00,0xd8 = ahik %r0, %r0, 0 0xec,0x00,0x00,0x01,0x00,0xd8 = ahik %r0, %r0, 1 0xec,0x00,0x7f,0xff,0x00,0xd8 = ahik %r0, %r0, 32767 0xec,0x0f,0x00,0x00,0x00,0xd8 = ahik %r0, %r15, 0 0xec,0xf0,0x00,0x00,0x00,0xd8 = ahik %r15, %r0, 0 0xec,0x78,0xff,0xf0,0x00,0xd8 = ahik %r7, %r8, -16 0xcc,0x08,0x80,0x00,0x00,0x00 = aih %r0, -2147483648 0xcc,0x08,0xff,0xff,0xff,0xff = aih %r0, -1 0xcc,0x08,0x00,0x00,0x00,0x00 = aih %r0, 0 0xcc,0x08,0x00,0x00,0x00,0x01 = aih %r0, 1 0xcc,0x08,0x7f,0xff,0xff,0xff = aih %r0, 2147483647 0xcc,0xf8,0x00,0x00,0x00,0x00 = aih %r15, 0 0xec,0x00,0x80,0x00,0x00,0xdb = alghsik %r0, %r0, -32768 0xec,0x00,0xff,0xff,0x00,0xdb = alghsik %r0, %r0, -1 0xec,0x00,0x00,0x00,0x00,0xdb = alghsik %r0, %r0, 0 0xec,0x00,0x00,0x01,0x00,0xdb = alghsik %r0, %r0, 1 0xec,0x00,0x7f,0xff,0x00,0xdb = alghsik %r0, %r0, 32767 0xec,0x0f,0x00,0x00,0x00,0xdb = alghsik %r0, %r15, 0 0xec,0xf0,0x00,0x00,0x00,0xdb = alghsik %r15, %r0, 0 0xec,0x78,0xff,0xf0,0x00,0xdb = alghsik %r7, %r8, -16 0xb9,0xea,0x00,0x00 = algrk %r0, %r0, %r0 0xb9,0xea,0xf0,0x00 = algrk %r0, %r0, %r15 0xb9,0xea,0x00,0x0f = algrk %r0, %r15, %r0 0xb9,0xea,0x00,0xf0 = algrk %r15, %r0, %r0 0xb9,0xea,0x90,0x78 = algrk %r7, %r8, %r9 0xec,0x00,0x80,0x00,0x00,0xda = alhsik %r0, %r0, -32768 0xec,0x00,0xff,0xff,0x00,0xda = alhsik %r0, %r0, -1 0xec,0x00,0x00,0x00,0x00,0xda = alhsik %r0, %r0, 0 0xec,0x00,0x00,0x01,0x00,0xda = alhsik %r0, %r0, 1 0xec,0x00,0x7f,0xff,0x00,0xda = alhsik %r0, %r0, 32767 0xec,0x0f,0x00,0x00,0x00,0xda = alhsik %r0, %r15, 0 0xec,0xf0,0x00,0x00,0x00,0xda = alhsik %r15, %r0, 0 0xec,0x78,0xff,0xf0,0x00,0xda = alhsik %r7, %r8, -16 0xb9,0xfa,0x00,0x00 = alrk %r0, %r0, %r0 0xb9,0xfa,0xf0,0x00 = alrk %r0, %r0, %r15 0xb9,0xfa,0x00,0x0f = alrk %r0, %r15, %r0 0xb9,0xfa,0x00,0xf0 = alrk %r15, %r0, %r0 0xb9,0xfa,0x90,0x78 = alrk %r7, %r8, %r9 0xb9,0xf8,0x00,0x00 = ark %r0, %r0, %r0 0xb9,0xf8,0xf0,0x00 = ark %r0, %r0, %r15 0xb9,0xf8,0x00,0x0f = ark %r0, %r15, %r0 0xb9,0xf8,0x00,0xf0 = ark %r15, %r0, %r0 0xb9,0xf8,0x90,0x78 = ark %r7, %r8, %r9 0xb3,0x91,0x00,0x00 = cdlfbr %f0, 0, %r0, 0 0xb3,0x91,0x0f,0x00 = cdlfbr %f0, 0, %r0, 15 0xb3,0x91,0x00,0x0f = cdlfbr %f0, 0, %r15, 0 0xb3,0x91,0xf0,0x00 = cdlfbr %f0, 15, %r0, 0 0xb3,0x91,0x57,0x46 = cdlfbr %f4, 5, %r6, 7 0xb3,0x91,0x00,0xf0 = cdlfbr %f15, 0, %r0, 0 0xb3,0xa1,0x00,0x00 = cdlgbr %f0, 0, %r0, 0 0xb3,0xa1,0x0f,0x00 = cdlgbr %f0, 0, %r0, 15 0xb3,0xa1,0x00,0x0f = cdlgbr %f0, 0, %r15, 0 0xb3,0xa1,0xf0,0x00 = cdlgbr %f0, 15, %r0, 0 0xb3,0xa1,0x57,0x46 = cdlgbr %f4, 5, %r6, 7 0xb3,0xa1,0x00,0xf0 = cdlgbr %f15, 0, %r0, 0 0xb3,0x90,0x00,0x00 = celfbr %f0, 0, %r0, 0 0xb3,0x90,0x0f,0x00 = celfbr %f0, 0, %r0, 15 0xb3,0x90,0x00,0x0f = celfbr %f0, 0, %r15, 0 0xb3,0x90,0xf0,0x00 = celfbr %f0, 15, %r0, 0 0xb3,0x90,0x57,0x46 = celfbr %f4, 5, %r6, 7 0xb3,0x90,0x00,0xf0 = celfbr %f15, 0, %r0, 0 0xb3,0xa0,0x00,0x00 = celgbr %f0, 0, %r0, 0 0xb3,0xa0,0x0f,0x00 = celgbr %f0, 0, %r0, 15 0xb3,0xa0,0x00,0x0f = celgbr %f0, 0, %r15, 0 0xb3,0xa0,0xf0,0x00 = celgbr %f0, 15, %r0, 0 0xb3,0xa0,0x57,0x46 = celgbr %f4, 5, %r6, 7 0xb3,0xa0,0x00,0xf0 = celgbr %f15, 0, %r0, 0 0xe3,0x00,0x00,0x00,0x80,0xcd = chf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xcd = chf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xcd = chf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xcd = chf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xcd = chf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xcd = chf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xcd = chf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xcd = chf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xcd = chf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xcd = chf %r15, 0 0xcc,0x0d,0x80,0x00,0x00,0x00 = cih %r0, -2147483648 0xcc,0x0d,0xff,0xff,0xff,0xff = cih %r0, -1 0xcc,0x0d,0x00,0x00,0x00,0x00 = cih %r0, 0 0xcc,0x0d,0x00,0x00,0x00,0x01 = cih %r0, 1 0xcc,0x0d,0x7f,0xff,0xff,0xff = cih %r0, 2147483647 0xcc,0xfd,0x00,0x00,0x00,0x00 = cih %r15, 0 0xb3,0x9d,0x00,0x00 = clfdbr %r0, 0, %f0, 0 0xb3,0x9d,0x0f,0x00 = clfdbr %r0, 0, %f0, 15 0xb3,0x9d,0x00,0x0f = clfdbr %r0, 0, %f15, 0 0xb3,0x9d,0xf0,0x00 = clfdbr %r0, 15, %f0, 0 0xb3,0x9d,0x57,0x46 = clfdbr %r4, 5, %f6, 7 0xb3,0x9d,0x00,0xf0 = clfdbr %r15, 0, %f0, 0 0xb3,0x9c,0x00,0x00 = clfebr %r0, 0, %f0, 0 0xb3,0x9c,0x0f,0x00 = clfebr %r0, 0, %f0, 15 0xb3,0x9c,0x00,0x0f = clfebr %r0, 0, %f15, 0 0xb3,0x9c,0xf0,0x00 = clfebr %r0, 15, %f0, 0 0xb3,0x9c,0x57,0x46 = clfebr %r4, 5, %f6, 7 0xb3,0x9c,0x00,0xf0 = clfebr %r15, 0, %f0, 0 0xb3,0x9e,0x00,0x00 = clfxbr %r0, 0, %f0, 0 0xb3,0x9e,0x0f,0x00 = clfxbr %r0, 0, %f0, 15 0xb3,0x9e,0x00,0x0d = clfxbr %r0, 0, %f13, 0 0xb3,0x9e,0xf0,0x00 = clfxbr %r0, 15, %f0, 0 0xb3,0x9e,0x59,0x78 = clfxbr %r7, 5, %f8, 9 0xb3,0x9e,0x00,0xf0 = clfxbr %r15, 0, %f0, 0 0xb3,0xad,0x00,0x00 = clgdbr %r0, 0, %f0, 0 0xb3,0xad,0x0f,0x00 = clgdbr %r0, 0, %f0, 15 0xb3,0xad,0x00,0x0f = clgdbr %r0, 0, %f15, 0 0xb3,0xad,0xf0,0x00 = clgdbr %r0, 15, %f0, 0 0xb3,0xad,0x57,0x46 = clgdbr %r4, 5, %f6, 7 0xb3,0xad,0x00,0xf0 = clgdbr %r15, 0, %f0, 0 0xb3,0xac,0x00,0x00 = clgebr %r0, 0, %f0, 0 0xb3,0xac,0x0f,0x00 = clgebr %r0, 0, %f0, 15 0xb3,0xac,0x00,0x0f = clgebr %r0, 0, %f15, 0 0xb3,0xac,0xf0,0x00 = clgebr %r0, 15, %f0, 0 0xb3,0xac,0x57,0x46 = clgebr %r4, 5, %f6, 7 0xb3,0xac,0x00,0xf0 = clgebr %r15, 0, %f0, 0 0xb3,0xae,0x00,0x00 = clgxbr %r0, 0, %f0, 0 0xb3,0xae,0x0f,0x00 = clgxbr %r0, 0, %f0, 15 0xb3,0xae,0x00,0x0d = clgxbr %r0, 0, %f13, 0 0xb3,0xae,0xf0,0x00 = clgxbr %r0, 15, %f0, 0 0xb3,0xae,0x59,0x78 = clgxbr %r7, 5, %f8, 9 0xb3,0xae,0x00,0xf0 = clgxbr %r15, 0, %f0, 0 0xe3,0x00,0x00,0x00,0x80,0xcf = clhf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xcf = clhf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xcf = clhf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xcf = clhf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xcf = clhf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xcf = clhf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xcf = clhf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xcf = clhf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xcf = clhf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xcf = clhf %r15, 0 0xcc,0x0f,0x00,0x00,0x00,0x00 = clih %r0, 0 0xcc,0x0f,0x00,0x00,0x00,0x01 = clih %r0, 1 0xcc,0x0f,0xff,0xff,0xff,0xff = clih %r0, 4294967295 0xcc,0xff,0x00,0x00,0x00,0x00 = clih %r15, 0 0xb3,0x92,0x00,0x00 = cxlfbr %f0, 0, %r0, 0 0xb3,0x92,0x0f,0x00 = cxlfbr %f0, 0, %r0, 15 0xb3,0x92,0x00,0x0f = cxlfbr %f0, 0, %r15, 0 0xb3,0x92,0xf0,0x00 = cxlfbr %f0, 15, %r0, 0 0xb3,0x92,0x5a,0x49 = cxlfbr %f4, 5, %r9, 10 0xb3,0x92,0x00,0xd0 = cxlfbr %f13, 0, %r0, 0 0xb3,0xa2,0x00,0x00 = cxlgbr %f0, 0, %r0, 0 0xb3,0xa2,0x0f,0x00 = cxlgbr %f0, 0, %r0, 15 0xb3,0xa2,0x00,0x0f = cxlgbr %f0, 0, %r15, 0 0xb3,0xa2,0xf0,0x00 = cxlgbr %f0, 15, %r0, 0 0xb3,0xa2,0x5a,0x49 = cxlgbr %f4, 5, %r9, 10 0xb3,0xa2,0x00,0xd0 = cxlgbr %f13, 0, %r0, 0 // 0xb3,0x5f,0x00,0x00 = fidbra %f0, 0, %f0, 0 0xb3,0x5f,0x0f,0x00 = fidbra %f0, 0, %f0, 15 // 0xb3,0x5f,0x00,0x0f = fidbra %f0, 0, %f15, 0 // 0xb3,0x5f,0xf0,0x00 = fidbra %f0, 15, %f0, 0 0xb3,0x5f,0x57,0x46 = fidbra %f4, 5, %f6, 7 // 0xb3,0x5f,0x00,0xf0 = fidbra %f15, 0, %f0, 0 // 0xb3,0x57,0x00,0x00 = fiebra %f0, 0, %f0, 0 0xb3,0x57,0x0f,0x00 = fiebra %f0, 0, %f0, 15 // 0xb3,0x57,0x00,0x0f = fiebra %f0, 0, %f15, 0 // 0xb3,0x57,0xf0,0x00 = fiebra %f0, 15, %f0, 0 0xb3,0x57,0x57,0x46 = fiebra %f4, 5, %f6, 7 // 0xb3,0x57,0x00,0xf0 = fiebra %f15, 0, %f0, 0 // 0xb3,0x47,0x00,0x00 = fixbra %f0, 0, %f0, 0 0xb3,0x47,0x0f,0x00 = fixbra %f0, 0, %f0, 15 // 0xb3,0x47,0x00,0x0d = fixbra %f0, 0, %f13, 0 // 0xb3,0x47,0xf0,0x00 = fixbra %f0, 15, %f0, 0 0xb3,0x47,0x59,0x48 = fixbra %f4, 5, %f8, 9 // 0xb3,0x47,0x00,0xd0 = fixbra %f13, 0, %f0, 0 0xeb,0x00,0x00,0x00,0x80,0xf8 = laa %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xf8 = laa %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xf8 = laa %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xf8 = laa %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xf8 = laa %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xf8 = laa %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xf8 = laa %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xf8 = laa %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xf8 = laa %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xf8 = laa %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xf8 = laa %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xe8 = laag %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xe8 = laag %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xe8 = laag %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xe8 = laag %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xe8 = laag %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xe8 = laag %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xe8 = laag %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xe8 = laag %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xe8 = laag %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xe8 = laag %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xe8 = laag %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xfa = laal %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xfa = laal %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xfa = laal %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xfa = laal %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xfa = laal %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xfa = laal %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xfa = laal %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xfa = laal %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xfa = laal %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xfa = laal %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xfa = laal %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xea = laalg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xea = laalg %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xea = laalg %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xea = laalg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xea = laalg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xea = laalg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xea = laalg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xea = laalg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xea = laalg %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xea = laalg %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xea = laalg %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xf4 = lan %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xf4 = lan %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xf4 = lan %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xf4 = lan %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xf4 = lan %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xf4 = lan %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xf4 = lan %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xf4 = lan %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xf4 = lan %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xf4 = lan %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xf4 = lan %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xe4 = lang %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xe4 = lang %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xe4 = lang %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xe4 = lang %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xe4 = lang %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xe4 = lang %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xe4 = lang %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xe4 = lang %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xe4 = lang %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xe4 = lang %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xe4 = lang %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xf6 = lao %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xf6 = lao %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xf6 = lao %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xf6 = lao %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xf6 = lao %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xf6 = lao %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xf6 = lao %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xf6 = lao %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xf6 = lao %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xf6 = lao %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xf6 = lao %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xe6 = laog %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xe6 = laog %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xe6 = laog %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xe6 = laog %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xe6 = laog %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xe6 = laog %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xe6 = laog %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xe6 = laog %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xe6 = laog %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xe6 = laog %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xe6 = laog %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xf7 = lax %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xf7 = lax %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xf7 = lax %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xf7 = lax %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xf7 = lax %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xf7 = lax %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xf7 = lax %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xf7 = lax %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xf7 = lax %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xf7 = lax %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xf7 = lax %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0xe7 = laxg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xe7 = laxg %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0xe7 = laxg %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0xe7 = laxg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xe7 = laxg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xe7 = laxg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xe7 = laxg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xe7 = laxg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xe7 = laxg %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0xe7 = laxg %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0xe7 = laxg %r15, %r0, 0 0xe3,0x00,0x00,0x00,0x80,0xc0 = lbh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xc0 = lbh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xc0 = lbh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xc0 = lbh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xc0 = lbh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xc0 = lbh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xc0 = lbh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xc0 = lbh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xc0 = lbh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xc0 = lbh %r15, 0 0xe3,0x00,0x00,0x00,0x80,0xca = lfh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xca = lfh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xca = lfh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xca = lfh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xca = lfh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xca = lfh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xca = lfh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xca = lfh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xca = lfh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xca = lfh %r15, 0 0xe3,0x00,0x00,0x00,0x80,0xc4 = lhh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xc4 = lhh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xc4 = lhh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xc4 = lhh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xc4 = lhh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xc4 = lhh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xc4 = lhh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xc4 = lhh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xc4 = lhh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xc4 = lhh %r15, 0 0xe3,0x00,0x00,0x00,0x80,0xc2 = llch %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xc2 = llch %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xc2 = llch %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xc2 = llch %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xc2 = llch %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xc2 = llch %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xc2 = llch %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xc2 = llch %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xc2 = llch %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xc2 = llch %r15, 0 0xe3,0x00,0x00,0x00,0x80,0xc6 = llhh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xc6 = llhh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xc6 = llhh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xc6 = llhh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xc6 = llhh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xc6 = llhh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xc6 = llhh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xc6 = llhh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xc6 = llhh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xc6 = llhh %r15, 0 0xeb,0x00,0x00,0x00,0x00,0xf2 = loc %r0, 0, 0 0xeb,0x0f,0x00,0x00,0x00,0xf2 = loc %r0, 0, 15 0xeb,0x00,0x00,0x00,0x80,0xf2 = loc %r0, -524288, 0 0xeb,0x00,0x0f,0xff,0x7f,0xf2 = loc %r0, 524287, 0 0xeb,0x00,0x10,0x00,0x00,0xf2 = loc %r0, 0(%r1), 0 0xeb,0x00,0xf0,0x00,0x00,0xf2 = loc %r0, 0(%r15), 0 0xeb,0xf0,0x00,0x00,0x00,0xf2 = loc %r15, 0, 0 // 0xeb,0x13,0x2f,0xff,0x00,0xf2 = loc %r1, 4095(%r2), 3 0xeb,0x11,0x30,0x02,0x00,0xf2 = loco %r1, 2(%r3) 0xeb,0x12,0x30,0x02,0x00,0xf2 = loch %r1, 2(%r3) 0xeb,0x13,0x30,0x02,0x00,0xf2 = locnle %r1, 2(%r3) 0xeb,0x14,0x30,0x02,0x00,0xf2 = locl %r1, 2(%r3) 0xeb,0x15,0x30,0x02,0x00,0xf2 = locnhe %r1, 2(%r3) 0xeb,0x16,0x30,0x02,0x00,0xf2 = loclh %r1, 2(%r3) 0xeb,0x17,0x30,0x02,0x00,0xf2 = locne %r1, 2(%r3) 0xeb,0x18,0x30,0x02,0x00,0xf2 = loce %r1, 2(%r3) 0xeb,0x19,0x30,0x02,0x00,0xf2 = locnlh %r1, 2(%r3) 0xeb,0x1a,0x30,0x02,0x00,0xf2 = loche %r1, 2(%r3) 0xeb,0x1b,0x30,0x02,0x00,0xf2 = locnl %r1, 2(%r3) 0xeb,0x1c,0x30,0x02,0x00,0xf2 = locle %r1, 2(%r3) 0xeb,0x1d,0x30,0x02,0x00,0xf2 = locnh %r1, 2(%r3) 0xeb,0x1e,0x30,0x02,0x00,0xf2 = locno %r1, 2(%r3) 0xeb,0x00,0x00,0x00,0x00,0xe2 = locg %r0, 0, 0 0xeb,0x0f,0x00,0x00,0x00,0xe2 = locg %r0, 0, 15 0xeb,0x00,0x00,0x00,0x80,0xe2 = locg %r0, -524288, 0 0xeb,0x00,0x0f,0xff,0x7f,0xe2 = locg %r0, 524287, 0 0xeb,0x00,0x10,0x00,0x00,0xe2 = locg %r0, 0(%r1), 0 0xeb,0x00,0xf0,0x00,0x00,0xe2 = locg %r0, 0(%r15), 0 0xeb,0xf0,0x00,0x00,0x00,0xe2 = locg %r15, 0, 0 // 0xeb,0x13,0x2f,0xff,0x00,0xe2 = locg %r1, 4095(%r2), 3 0xeb,0x11,0x30,0x02,0x00,0xe2 = locgo %r1, 2(%r3) 0xeb,0x12,0x30,0x02,0x00,0xe2 = locgh %r1, 2(%r3) 0xeb,0x13,0x30,0x02,0x00,0xe2 = locgnle %r1, 2(%r3) 0xeb,0x14,0x30,0x02,0x00,0xe2 = locgl %r1, 2(%r3) 0xeb,0x15,0x30,0x02,0x00,0xe2 = locgnhe %r1, 2(%r3) 0xeb,0x16,0x30,0x02,0x00,0xe2 = locglh %r1, 2(%r3) 0xeb,0x17,0x30,0x02,0x00,0xe2 = locgne %r1, 2(%r3) 0xeb,0x18,0x30,0x02,0x00,0xe2 = locge %r1, 2(%r3) 0xeb,0x19,0x30,0x02,0x00,0xe2 = locgnlh %r1, 2(%r3) 0xeb,0x1a,0x30,0x02,0x00,0xe2 = locghe %r1, 2(%r3) 0xeb,0x1b,0x30,0x02,0x00,0xe2 = locgnl %r1, 2(%r3) 0xeb,0x1c,0x30,0x02,0x00,0xe2 = locgle %r1, 2(%r3) 0xeb,0x1d,0x30,0x02,0x00,0xe2 = locgnh %r1, 2(%r3) 0xeb,0x1e,0x30,0x02,0x00,0xe2 = locgno %r1, 2(%r3) 0xb9,0xe2,0x00,0x12 = locgr %r1, %r2, 0 0xb9,0xe2,0xf0,0x12 = locgr %r1, %r2, 15 0xb9,0xe2,0x10,0x13 = locgro %r1, %r3 0xb9,0xe2,0x20,0x13 = locgrh %r1, %r3 0xb9,0xe2,0x30,0x13 = locgrnle %r1, %r3 0xb9,0xe2,0x40,0x13 = locgrl %r1, %r3 0xb9,0xe2,0x50,0x13 = locgrnhe %r1, %r3 0xb9,0xe2,0x60,0x13 = locgrlh %r1, %r3 0xb9,0xe2,0x70,0x13 = locgrne %r1, %r3 0xb9,0xe2,0x80,0x13 = locgre %r1, %r3 0xb9,0xe2,0x90,0x13 = locgrnlh %r1, %r3 0xb9,0xe2,0xa0,0x13 = locgrhe %r1, %r3 0xb9,0xe2,0xb0,0x13 = locgrnl %r1, %r3 0xb9,0xe2,0xc0,0x13 = locgrle %r1, %r3 0xb9,0xe2,0xd0,0x13 = locgrnh %r1, %r3 0xb9,0xe2,0xe0,0x13 = locgrno %r1, %r3 0xb9,0xf2,0x00,0x12 = locr %r1, %r2, 0 0xb9,0xf2,0xf0,0x12 = locr %r1, %r2, 15 0xb9,0xf2,0x10,0x13 = locro %r1, %r3 0xb9,0xf2,0x20,0x13 = locrh %r1, %r3 0xb9,0xf2,0x30,0x13 = locrnle %r1, %r3 0xb9,0xf2,0x40,0x13 = locrl %r1, %r3 0xb9,0xf2,0x50,0x13 = locrnhe %r1, %r3 0xb9,0xf2,0x60,0x13 = locrlh %r1, %r3 0xb9,0xf2,0x70,0x13 = locrne %r1, %r3 0xb9,0xf2,0x80,0x13 = locre %r1, %r3 0xb9,0xf2,0x90,0x13 = locrnlh %r1, %r3 0xb9,0xf2,0xa0,0x13 = locrhe %r1, %r3 0xb9,0xf2,0xb0,0x13 = locrnl %r1, %r3 0xb9,0xf2,0xc0,0x13 = locrle %r1, %r3 0xb9,0xf2,0xd0,0x13 = locrnh %r1, %r3 0xb9,0xf2,0xe0,0x13 = locrno %r1, %r3 0xb9,0xe4,0x00,0x00 = ngrk %r0, %r0, %r0 0xb9,0xe4,0xf0,0x00 = ngrk %r0, %r0, %r15 0xb9,0xe4,0x00,0x0f = ngrk %r0, %r15, %r0 0xb9,0xe4,0x00,0xf0 = ngrk %r15, %r0, %r0 0xb9,0xe4,0x90,0x78 = ngrk %r7, %r8, %r9 0xb9,0xf4,0x00,0x00 = nrk %r0, %r0, %r0 0xb9,0xf4,0xf0,0x00 = nrk %r0, %r0, %r15 0xb9,0xf4,0x00,0x0f = nrk %r0, %r15, %r0 0xb9,0xf4,0x00,0xf0 = nrk %r15, %r0, %r0 0xb9,0xf4,0x90,0x78 = nrk %r7, %r8, %r9 0xb9,0xe6,0x00,0x00 = ogrk %r0, %r0, %r0 0xb9,0xe6,0xf0,0x00 = ogrk %r0, %r0, %r15 0xb9,0xe6,0x00,0x0f = ogrk %r0, %r15, %r0 0xb9,0xe6,0x00,0xf0 = ogrk %r15, %r0, %r0 0xb9,0xe6,0x90,0x78 = ogrk %r7, %r8, %r9 0xb9,0xf6,0x00,0x00 = ork %r0, %r0, %r0 0xb9,0xf6,0xf0,0x00 = ork %r0, %r0, %r15 0xb9,0xf6,0x00,0x0f = ork %r0, %r15, %r0 0xb9,0xf6,0x00,0xf0 = ork %r15, %r0, %r0 0xb9,0xf6,0x90,0x78 = ork %r7, %r8, %r9 0xec,0x00,0x00,0x00,0x00,0x5d = risbhg %r0, %r0, 0, 0, 0 0xec,0x00,0x00,0x00,0x3f,0x5d = risbhg %r0, %r0, 0, 0, 63 0xec,0x00,0x00,0xff,0x00,0x5d = risbhg %r0, %r0, 0, 255, 0 0xec,0x00,0xff,0x00,0x00,0x5d = risbhg %r0, %r0, 255, 0, 0 0xec,0x0f,0x00,0x00,0x00,0x5d = risbhg %r0, %r15, 0, 0, 0 0xec,0xf0,0x00,0x00,0x00,0x5d = risbhg %r15, %r0, 0, 0, 0 0xec,0x45,0x06,0x07,0x08,0x5d = risbhg %r4, %r5, 6, 7, 8 0xec,0x00,0x00,0x00,0x00,0x51 = risblg %r0, %r0, 0, 0, 0 0xec,0x00,0x00,0x00,0x3f,0x51 = risblg %r0, %r0, 0, 0, 63 0xec,0x00,0x00,0xff,0x00,0x51 = risblg %r0, %r0, 0, 255, 0 0xec,0x00,0xff,0x00,0x00,0x51 = risblg %r0, %r0, 255, 0, 0 0xec,0x0f,0x00,0x00,0x00,0x51 = risblg %r0, %r15, 0, 0, 0 0xec,0xf0,0x00,0x00,0x00,0x51 = risblg %r15, %r0, 0, 0, 0 0xec,0x45,0x06,0x07,0x08,0x51 = risblg %r4, %r5, 6, 7, 8 0xb9,0xe9,0x00,0x00 = sgrk %r0, %r0, %r0 0xb9,0xe9,0xf0,0x00 = sgrk %r0, %r0, %r15 0xb9,0xe9,0x00,0x0f = sgrk %r0, %r15, %r0 0xb9,0xe9,0x00,0xf0 = sgrk %r15, %r0, %r0 0xb9,0xe9,0x90,0x78 = sgrk %r7, %r8, %r9 0xb9,0xeb,0x00,0x00 = slgrk %r0, %r0, %r0 0xb9,0xeb,0xf0,0x00 = slgrk %r0, %r0, %r15 0xb9,0xeb,0x00,0x0f = slgrk %r0, %r15, %r0 0xb9,0xeb,0x00,0xf0 = slgrk %r15, %r0, %r0 0xb9,0xeb,0x90,0x78 = slgrk %r7, %r8, %r9 0xb9,0xfb,0x00,0x00 = slrk %r0, %r0, %r0 0xb9,0xfb,0xf0,0x00 = slrk %r0, %r0, %r15 0xb9,0xfb,0x00,0x0f = slrk %r0, %r15, %r0 0xb9,0xfb,0x00,0xf0 = slrk %r15, %r0, %r0 0xb9,0xfb,0x90,0x78 = slrk %r7, %r8, %r9 0xeb,0x00,0x00,0x00,0x00,0xdf = sllk %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0xdf = sllk %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0xdf = sllk %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0xdf = sllk %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0xdf = sllk %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xdf = sllk %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0xdf = sllk %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xdf = sllk %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xdf = sllk %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xdf = sllk %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xdf = sllk %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xdf = sllk %r0, %r0, 524287(%r15) 0xeb,0x00,0x00,0x00,0x00,0xdc = srak %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0xdc = srak %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0xdc = srak %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0xdc = srak %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0xdc = srak %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xdc = srak %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0xdc = srak %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xdc = srak %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xdc = srak %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xdc = srak %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xdc = srak %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xdc = srak %r0, %r0, 524287(%r15) 0xb9,0xf9,0x00,0x00 = srk %r0, %r0, %r0 0xb9,0xf9,0xf0,0x00 = srk %r0, %r0, %r15 0xb9,0xf9,0x00,0x0f = srk %r0, %r15, %r0 0xb9,0xf9,0x00,0xf0 = srk %r15, %r0, %r0 0xb9,0xf9,0x90,0x78 = srk %r7, %r8, %r9 0xeb,0x00,0x00,0x00,0x00,0xde = srlk %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0xde = srlk %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0xde = srlk %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0xde = srlk %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0xde = srlk %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0xde = srlk %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0xde = srlk %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0xde = srlk %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0xde = srlk %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0xde = srlk %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0xde = srlk %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0xde = srlk %r0, %r0, 524287(%r15) 0xe3,0x00,0x00,0x00,0x80,0xc3 = stch %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xc3 = stch %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xc3 = stch %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xc3 = stch %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xc3 = stch %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xc3 = stch %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xc3 = stch %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xc3 = stch %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xc3 = stch %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xc3 = stch %r15, 0 0xe3,0x00,0x00,0x00,0x80,0xc7 = sthh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xc7 = sthh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xc7 = sthh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xc7 = sthh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xc7 = sthh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xc7 = sthh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xc7 = sthh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xc7 = sthh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xc7 = sthh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xc7 = sthh %r15, 0 0xe3,0x00,0x00,0x00,0x80,0xcb = stfh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0xcb = stfh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0xcb = stfh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0xcb = stfh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0xcb = stfh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0xcb = stfh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0xcb = stfh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0xcb = stfh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0xcb = stfh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0xcb = stfh %r15, 0 0xeb,0x00,0x00,0x00,0x00,0xf3 = stoc %r0, 0, 0 0xeb,0x0f,0x00,0x00,0x00,0xf3 = stoc %r0, 0, 15 0xeb,0x00,0x00,0x00,0x80,0xf3 = stoc %r0, -524288, 0 0xeb,0x00,0x0f,0xff,0x7f,0xf3 = stoc %r0, 524287, 0 0xeb,0x00,0x10,0x00,0x00,0xf3 = stoc %r0, 0(%r1), 0 0xeb,0x00,0xf0,0x00,0x00,0xf3 = stoc %r0, 0(%r15), 0 0xeb,0xf0,0x00,0x00,0x00,0xf3 = stoc %r15, 0, 0 // 0xeb,0x13,0x2f,0xff,0x00,0xf3 = stoc %r1, 4095(%r2), 3 0xeb,0x11,0x30,0x02,0x00,0xf3 = stoco %r1, 2(%r3) 0xeb,0x12,0x30,0x02,0x00,0xf3 = stoch %r1, 2(%r3) 0xeb,0x13,0x30,0x02,0x00,0xf3 = stocnle %r1, 2(%r3) 0xeb,0x14,0x30,0x02,0x00,0xf3 = stocl %r1, 2(%r3) 0xeb,0x15,0x30,0x02,0x00,0xf3 = stocnhe %r1, 2(%r3) 0xeb,0x16,0x30,0x02,0x00,0xf3 = stoclh %r1, 2(%r3) 0xeb,0x17,0x30,0x02,0x00,0xf3 = stocne %r1, 2(%r3) 0xeb,0x18,0x30,0x02,0x00,0xf3 = stoce %r1, 2(%r3) 0xeb,0x19,0x30,0x02,0x00,0xf3 = stocnlh %r1, 2(%r3) 0xeb,0x1a,0x30,0x02,0x00,0xf3 = stoche %r1, 2(%r3) 0xeb,0x1b,0x30,0x02,0x00,0xf3 = stocnl %r1, 2(%r3) 0xeb,0x1c,0x30,0x02,0x00,0xf3 = stocle %r1, 2(%r3) 0xeb,0x1d,0x30,0x02,0x00,0xf3 = stocnh %r1, 2(%r3) 0xeb,0x1e,0x30,0x02,0x00,0xf3 = stocno %r1, 2(%r3) 0xeb,0x00,0x00,0x00,0x00,0xe3 = stocg %r0, 0, 0 0xeb,0x0f,0x00,0x00,0x00,0xe3 = stocg %r0, 0, 15 0xeb,0x00,0x00,0x00,0x80,0xe3 = stocg %r0, -524288, 0 0xeb,0x00,0x0f,0xff,0x7f,0xe3 = stocg %r0, 524287, 0 0xeb,0x00,0x10,0x00,0x00,0xe3 = stocg %r0, 0(%r1), 0 0xeb,0x00,0xf0,0x00,0x00,0xe3 = stocg %r0, 0(%r15), 0 0xeb,0xf0,0x00,0x00,0x00,0xe3 = stocg %r15, 0, 0 // 0xeb,0x13,0x2f,0xff,0x00,0xe3 = stocg %r1, 4095(%r2), 3 0xeb,0x11,0x30,0x02,0x00,0xe3 = stocgo %r1, 2(%r3) 0xeb,0x12,0x30,0x02,0x00,0xe3 = stocgh %r1, 2(%r3) 0xeb,0x13,0x30,0x02,0x00,0xe3 = stocgnle %r1, 2(%r3) 0xeb,0x14,0x30,0x02,0x00,0xe3 = stocgl %r1, 2(%r3) 0xeb,0x15,0x30,0x02,0x00,0xe3 = stocgnhe %r1, 2(%r3) 0xeb,0x16,0x30,0x02,0x00,0xe3 = stocglh %r1, 2(%r3) 0xeb,0x17,0x30,0x02,0x00,0xe3 = stocgne %r1, 2(%r3) 0xeb,0x18,0x30,0x02,0x00,0xe3 = stocge %r1, 2(%r3) 0xeb,0x19,0x30,0x02,0x00,0xe3 = stocgnlh %r1, 2(%r3) 0xeb,0x1a,0x30,0x02,0x00,0xe3 = stocghe %r1, 2(%r3) 0xeb,0x1b,0x30,0x02,0x00,0xe3 = stocgnl %r1, 2(%r3) 0xeb,0x1c,0x30,0x02,0x00,0xe3 = stocgle %r1, 2(%r3) 0xeb,0x1d,0x30,0x02,0x00,0xe3 = stocgnh %r1, 2(%r3) 0xeb,0x1e,0x30,0x02,0x00,0xe3 = stocgno %r1, 2(%r3) 0xb9,0xe7,0x00,0x00 = xgrk %r0, %r0, %r0 0xb9,0xe7,0xf0,0x00 = xgrk %r0, %r0, %r15 0xb9,0xe7,0x00,0x0f = xgrk %r0, %r15, %r0 0xb9,0xe7,0x00,0xf0 = xgrk %r15, %r0, %r0 0xb9,0xe7,0x90,0x78 = xgrk %r7, %r8, %r9 0xb9,0xf7,0x00,0x00 = xrk %r0, %r0, %r0 0xb9,0xf7,0xf0,0x00 = xrk %r0, %r0, %r15 0xb9,0xf7,0x00,0x0f = xrk %r0, %r15, %r0 0xb9,0xf7,0x00,0xf0 = xrk %r15, %r0, %r0 0xb9,0xf7,0x90,0x78 = xrk %r7, %r8, %r9 capstone-sys-0.15.0/capstone/suite/MC/SystemZ/insn-good.s.cs000064400000000000000000003003500072674642500217370ustar 00000000000000# CS_ARCH_SYSZ, 0, None 0x5a,0x00,0x00,0x00 = a %r0, 0 0x5a,0x00,0x0f,0xff = a %r0, 4095 0x5a,0x00,0x10,0x00 = a %r0, 0(%r1) 0x5a,0x00,0xf0,0x00 = a %r0, 0(%r15) 0x5a,0x01,0xff,0xff = a %r0, 4095(%r1, %r15) 0x5a,0x0f,0x1f,0xff = a %r0, 4095(%r15, %r1) 0x5a,0xf0,0x00,0x00 = a %r15, 0 0xed,0x00,0x00,0x00,0x00,0x1a = adb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x1a = adb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x1a = adb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x1a = adb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x1a = adb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x1a = adb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x1a = adb %f15, 0 0xb3,0x1a,0x00,0x00 = adbr %f0, %f0 0xb3,0x1a,0x00,0x0f = adbr %f0, %f15 0xb3,0x1a,0x00,0x78 = adbr %f7, %f8 0xb3,0x1a,0x00,0xf0 = adbr %f15, %f0 0xed,0x00,0x00,0x00,0x00,0x0a = aeb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x0a = aeb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x0a = aeb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x0a = aeb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x0a = aeb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x0a = aeb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x0a = aeb %f15, 0 0xb3,0x0a,0x00,0x00 = aebr %f0, %f0 0xb3,0x0a,0x00,0x0f = aebr %f0, %f15 0xb3,0x0a,0x00,0x78 = aebr %f7, %f8 0xb3,0x0a,0x00,0xf0 = aebr %f15, %f0 0xc2,0x09,0x80,0x00,0x00,0x00 = afi %r0, -2147483648 0xc2,0x09,0xff,0xff,0xff,0xff = afi %r0, -1 0xc2,0x09,0x00,0x00,0x00,0x00 = afi %r0, 0 0xc2,0x09,0x00,0x00,0x00,0x01 = afi %r0, 1 0xc2,0x09,0x7f,0xff,0xff,0xff = afi %r0, 2147483647 0xc2,0xf9,0x00,0x00,0x00,0x00 = afi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x08 = ag %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x08 = ag %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x08 = ag %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x08 = ag %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x08 = ag %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x08 = ag %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x08 = ag %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x08 = ag %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x08 = ag %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x08 = ag %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x18 = agf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x18 = agf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x18 = agf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x18 = agf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x18 = agf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x18 = agf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x18 = agf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x18 = agf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x18 = agf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x18 = agf %r15, 0 0xc2,0x08,0x80,0x00,0x00,0x00 = agfi %r0, -2147483648 0xc2,0x08,0xff,0xff,0xff,0xff = agfi %r0, -1 0xc2,0x08,0x00,0x00,0x00,0x00 = agfi %r0, 0 0xc2,0x08,0x00,0x00,0x00,0x01 = agfi %r0, 1 0xc2,0x08,0x7f,0xff,0xff,0xff = agfi %r0, 2147483647 0xc2,0xf8,0x00,0x00,0x00,0x00 = agfi %r15, 0 0xb9,0x18,0x00,0x00 = agfr %r0, %r0 0xb9,0x18,0x00,0x0f = agfr %r0, %r15 0xb9,0x18,0x00,0xf0 = agfr %r15, %r0 0xb9,0x18,0x00,0x78 = agfr %r7, %r8 0xa7,0x0b,0x80,0x00 = aghi %r0, -32768 0xa7,0x0b,0xff,0xff = aghi %r0, -1 0xa7,0x0b,0x00,0x00 = aghi %r0, 0 0xa7,0x0b,0x00,0x01 = aghi %r0, 1 0xa7,0x0b,0x7f,0xff = aghi %r0, 32767 0xa7,0xfb,0x00,0x00 = aghi %r15, 0 0xb9,0x08,0x00,0x00 = agr %r0, %r0 0xb9,0x08,0x00,0x0f = agr %r0, %r15 0xb9,0x08,0x00,0xf0 = agr %r15, %r0 0xb9,0x08,0x00,0x78 = agr %r7, %r8 0xeb,0x00,0x00,0x00,0x80,0x7a = agsi -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x7a = agsi -1, 0 0xeb,0x00,0x00,0x00,0x00,0x7a = agsi 0, 0 0xeb,0x00,0x00,0x01,0x00,0x7a = agsi 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x7a = agsi 524287, 0 0xeb,0x80,0x00,0x00,0x00,0x7a = agsi 0, -128 0xeb,0xff,0x00,0x00,0x00,0x7a = agsi 0, -1 0xeb,0x01,0x00,0x00,0x00,0x7a = agsi 0, 1 0xeb,0x7f,0x00,0x00,0x00,0x7a = agsi 0, 127 0xeb,0x2a,0x10,0x00,0x00,0x7a = agsi 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x7a = agsi 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x7a = agsi 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x7a = agsi 524287(%r15), 42 0x4a,0x00,0x00,0x00 = ah %r0, 0 0x4a,0x00,0x0f,0xff = ah %r0, 4095 0x4a,0x00,0x10,0x00 = ah %r0, 0(%r1) 0x4a,0x00,0xf0,0x00 = ah %r0, 0(%r15) 0x4a,0x01,0xff,0xff = ah %r0, 4095(%r1, %r15) 0x4a,0x0f,0x1f,0xff = ah %r0, 4095(%r15, %r1) 0x4a,0xf0,0x00,0x00 = ah %r15, 0 0xa7,0x0a,0x80,0x00 = ahi %r0, -32768 0xa7,0x0a,0xff,0xff = ahi %r0, -1 0xa7,0x0a,0x00,0x00 = ahi %r0, 0 0xa7,0x0a,0x00,0x01 = ahi %r0, 1 0xa7,0x0a,0x7f,0xff = ahi %r0, 32767 0xa7,0xfa,0x00,0x00 = ahi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x7a = ahy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x7a = ahy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x7a = ahy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x7a = ahy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x7a = ahy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x7a = ahy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x7a = ahy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x7a = ahy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x7a = ahy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x7a = ahy %r15, 0 0x5e,0x00,0x00,0x00 = al %r0, 0 0x5e,0x00,0x0f,0xff = al %r0, 4095 0x5e,0x00,0x10,0x00 = al %r0, 0(%r1) 0x5e,0x00,0xf0,0x00 = al %r0, 0(%r15) 0x5e,0x01,0xff,0xff = al %r0, 4095(%r1, %r15) 0x5e,0x0f,0x1f,0xff = al %r0, 4095(%r15, %r1) 0x5e,0xf0,0x00,0x00 = al %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x98 = alc %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x98 = alc %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x98 = alc %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x98 = alc %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x98 = alc %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x98 = alc %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x98 = alc %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x98 = alc %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x98 = alc %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x98 = alc %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x88 = alcg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x88 = alcg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x88 = alcg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x88 = alcg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x88 = alcg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x88 = alcg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x88 = alcg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x88 = alcg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x88 = alcg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x88 = alcg %r15, 0 0xb9,0x88,0x00,0x00 = alcgr %r0, %r0 0xb9,0x88,0x00,0x0f = alcgr %r0, %r15 0xb9,0x88,0x00,0xf0 = alcgr %r15, %r0 0xb9,0x88,0x00,0x78 = alcgr %r7, %r8 0xb9,0x98,0x00,0x00 = alcr %r0, %r0 0xb9,0x98,0x00,0x0f = alcr %r0, %r15 0xb9,0x98,0x00,0xf0 = alcr %r15, %r0 0xb9,0x98,0x00,0x78 = alcr %r7, %r8 0xc2,0x0b,0x00,0x00,0x00,0x00 = alfi %r0, 0 0xc2,0x0b,0xff,0xff,0xff,0xff = alfi %r0, 4294967295 0xc2,0xfb,0x00,0x00,0x00,0x00 = alfi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x0a = alg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x0a = alg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x0a = alg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x0a = alg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x0a = alg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x0a = alg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x0a = alg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x0a = alg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x0a = alg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x0a = alg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x1a = algf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x1a = algf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x1a = algf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x1a = algf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x1a = algf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x1a = algf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x1a = algf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x1a = algf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x1a = algf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x1a = algf %r15, 0 0xc2,0x0a,0x00,0x00,0x00,0x00 = algfi %r0, 0 0xc2,0x0a,0xff,0xff,0xff,0xff = algfi %r0, 4294967295 0xc2,0xfa,0x00,0x00,0x00,0x00 = algfi %r15, 0 0xb9,0x1a,0x00,0x00 = algfr %r0, %r0 0xb9,0x1a,0x00,0x0f = algfr %r0, %r15 0xb9,0x1a,0x00,0xf0 = algfr %r15, %r0 0xb9,0x1a,0x00,0x78 = algfr %r7, %r8 0xb9,0x0a,0x00,0x00 = algr %r0, %r0 0xb9,0x0a,0x00,0x0f = algr %r0, %r15 0xb9,0x0a,0x00,0xf0 = algr %r15, %r0 0xb9,0x0a,0x00,0x78 = algr %r7, %r8 0x1e,0x00 = alr %r0, %r0 0x1e,0x0f = alr %r0, %r15 0x1e,0xf0 = alr %r15, %r0 0x1e,0x78 = alr %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x5e = aly %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x5e = aly %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x5e = aly %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x5e = aly %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x5e = aly %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x5e = aly %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x5e = aly %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x5e = aly %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x5e = aly %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x5e = aly %r15, 0 0x1a,0x00 = ar %r0, %r0 0x1a,0x0f = ar %r0, %r15 0x1a,0xf0 = ar %r15, %r0 0x1a,0x78 = ar %r7, %r8 0xeb,0x00,0x00,0x00,0x80,0x6a = asi -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x6a = asi -1, 0 0xeb,0x00,0x00,0x00,0x00,0x6a = asi 0, 0 0xeb,0x00,0x00,0x01,0x00,0x6a = asi 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x6a = asi 524287, 0 0xeb,0x80,0x00,0x00,0x00,0x6a = asi 0, -128 0xeb,0xff,0x00,0x00,0x00,0x6a = asi 0, -1 0xeb,0x01,0x00,0x00,0x00,0x6a = asi 0, 1 0xeb,0x7f,0x00,0x00,0x00,0x6a = asi 0, 127 0xeb,0x2a,0x10,0x00,0x00,0x6a = asi 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x6a = asi 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x6a = asi 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x6a = asi 524287(%r15), 42 0xb3,0x4a,0x00,0x00 = axbr %f0, %f0 0xb3,0x4a,0x00,0x0d = axbr %f0, %f13 0xb3,0x4a,0x00,0x88 = axbr %f8, %f8 0xb3,0x4a,0x00,0xd0 = axbr %f13, %f0 0xe3,0x00,0x00,0x00,0x80,0x5a = ay %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x5a = ay %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x5a = ay %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x5a = ay %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x5a = ay %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x5a = ay %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x5a = ay %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x5a = ay %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x5a = ay %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x5a = ay %r15, 0 0x0d,0x01 = basr %r0, %r1 0x0d,0x0f = basr %r0, %r15 0x0d,0xe9 = basr %r14, %r9 0x0d,0xf1 = basr %r15, %r1 0x07,0x00 = bcr 0, %r0 0x07,0x0f = bcr 0, %r15 // 0x07,0x17 = bcr 1, %r7 0x07,0x1f = bor %r15 // 0x07,0x27 = bcr 2, %r7 0x07,0x2f = bhr %r15 // 0x07,0x37 = bcr 3, %r7 0x07,0x3f = bnler %r15 // 0x07,0x47 = bcr 4, %r7 0x07,0x4f = blr %r15 // 0x07,0x57 = bcr 5, %r7 0x07,0x5f = bnher %r15 // 0x07,0x67 = bcr 6, %r7 0x07,0x6f = blhr %r15 // 0x07,0x77 = bcr 7, %r7 0x07,0x7f = bner %r15 // 0x07,0x87 = bcr 8, %r7 0x07,0x8f = ber %r15 // 0x07,0x97 = bcr 9, %r7 0x07,0x9f = bnlhr %r15 // 0x07,0xa7 = bcr 10, %r7 0x07,0xaf = bher %r15 // 0x07,0xb7 = bcr 11, %r7 0x07,0xbf = bnlr %r15 // 0x07,0xc7 = bcr 12, %r7 0x07,0xcf = bler %r15 // 0x07,0xd7 = bcr 13, %r7 0x07,0xdf = bnhr %r15 // 0x07,0xe7 = bcr 14, %r7 0x07,0xef = bnor %r15 // 0x07,0xf7 = bcr 15, %r7 0x07,0xf1 = br %r1 0x07,0xfe = br %r14 0x07,0xff = br %r15 0x59,0x00,0x00,0x00 = c %r0, 0 0x59,0x00,0x0f,0xff = c %r0, 4095 0x59,0x00,0x10,0x00 = c %r0, 0(%r1) 0x59,0x00,0xf0,0x00 = c %r0, 0(%r15) 0x59,0x01,0xff,0xff = c %r0, 4095(%r1, %r15) 0x59,0x0f,0x1f,0xff = c %r0, 4095(%r15, %r1) 0x59,0xf0,0x00,0x00 = c %r15, 0 0xed,0x00,0x00,0x00,0x00,0x19 = cdb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x19 = cdb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x19 = cdb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x19 = cdb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x19 = cdb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x19 = cdb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x19 = cdb %f15, 0 0xb3,0x19,0x00,0x00 = cdbr %f0, %f0 0xb3,0x19,0x00,0x0f = cdbr %f0, %f15 0xb3,0x19,0x00,0x78 = cdbr %f7, %f8 0xb3,0x19,0x00,0xf0 = cdbr %f15, %f0 0xb3,0x95,0x00,0x00 = cdfbr %f0, %r0 0xb3,0x95,0x00,0x0f = cdfbr %f0, %r15 0xb3,0x95,0x00,0xf0 = cdfbr %f15, %r0 0xb3,0x95,0x00,0x78 = cdfbr %f7, %r8 0xb3,0x95,0x00,0xff = cdfbr %f15, %r15 0xb3,0xa5,0x00,0x00 = cdgbr %f0, %r0 0xb3,0xa5,0x00,0x0f = cdgbr %f0, %r15 0xb3,0xa5,0x00,0xf0 = cdgbr %f15, %r0 0xb3,0xa5,0x00,0x78 = cdgbr %f7, %r8 0xb3,0xa5,0x00,0xff = cdgbr %f15, %r15 0xed,0x00,0x00,0x00,0x00,0x09 = ceb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x09 = ceb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x09 = ceb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x09 = ceb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x09 = ceb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x09 = ceb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x09 = ceb %f15, 0 0xb3,0x09,0x00,0x00 = cebr %f0, %f0 0xb3,0x09,0x00,0x0f = cebr %f0, %f15 0xb3,0x09,0x00,0x78 = cebr %f7, %f8 0xb3,0x09,0x00,0xf0 = cebr %f15, %f0 0xb3,0x94,0x00,0x00 = cefbr %f0, %r0 0xb3,0x94,0x00,0x0f = cefbr %f0, %r15 0xb3,0x94,0x00,0xf0 = cefbr %f15, %r0 0xb3,0x94,0x00,0x78 = cefbr %f7, %r8 0xb3,0x94,0x00,0xff = cefbr %f15, %r15 0xb3,0xa4,0x00,0x00 = cegbr %f0, %r0 0xb3,0xa4,0x00,0x0f = cegbr %f0, %r15 0xb3,0xa4,0x00,0xf0 = cegbr %f15, %r0 0xb3,0xa4,0x00,0x78 = cegbr %f7, %r8 0xb3,0xa4,0x00,0xff = cegbr %f15, %r15 0xb3,0x99,0x00,0x00 = cfdbr %r0, 0, %f0 0xb3,0x99,0x00,0x0f = cfdbr %r0, 0, %f15 0xb3,0x99,0xf0,0x00 = cfdbr %r0, 15, %f0 0xb3,0x99,0x50,0x46 = cfdbr %r4, 5, %f6 0xb3,0x99,0x00,0xf0 = cfdbr %r15, 0, %f0 0xb3,0x98,0x00,0x00 = cfebr %r0, 0, %f0 0xb3,0x98,0x00,0x0f = cfebr %r0, 0, %f15 0xb3,0x98,0xf0,0x00 = cfebr %r0, 15, %f0 0xb3,0x98,0x50,0x46 = cfebr %r4, 5, %f6 0xb3,0x98,0x00,0xf0 = cfebr %r15, 0, %f0 0xc2,0x0d,0x80,0x00,0x00,0x00 = cfi %r0, -2147483648 0xc2,0x0d,0xff,0xff,0xff,0xff = cfi %r0, -1 0xc2,0x0d,0x00,0x00,0x00,0x00 = cfi %r0, 0 0xc2,0x0d,0x00,0x00,0x00,0x01 = cfi %r0, 1 0xc2,0x0d,0x7f,0xff,0xff,0xff = cfi %r0, 2147483647 0xc2,0xfd,0x00,0x00,0x00,0x00 = cfi %r15, 0 0xb3,0x9a,0x00,0x00 = cfxbr %r0, 0, %f0 0xb3,0x9a,0x00,0x0d = cfxbr %r0, 0, %f13 0xb3,0x9a,0xf0,0x00 = cfxbr %r0, 15, %f0 0xb3,0x9a,0x50,0x48 = cfxbr %r4, 5, %f8 0xb3,0x9a,0x00,0xf0 = cfxbr %r15, 0, %f0 0xe3,0x00,0x00,0x00,0x80,0x20 = cg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x20 = cg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x20 = cg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x20 = cg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x20 = cg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x20 = cg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x20 = cg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x20 = cg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x20 = cg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x20 = cg %r15, 0 0xb3,0xa9,0x00,0x00 = cgdbr %r0, 0, %f0 0xb3,0xa9,0x00,0x0f = cgdbr %r0, 0, %f15 0xb3,0xa9,0xf0,0x00 = cgdbr %r0, 15, %f0 0xb3,0xa9,0x50,0x46 = cgdbr %r4, 5, %f6 0xb3,0xa9,0x00,0xf0 = cgdbr %r15, 0, %f0 0xb3,0xa8,0x00,0x00 = cgebr %r0, 0, %f0 0xb3,0xa8,0x00,0x0f = cgebr %r0, 0, %f15 0xb3,0xa8,0xf0,0x00 = cgebr %r0, 15, %f0 0xb3,0xa8,0x50,0x46 = cgebr %r4, 5, %f6 0xb3,0xa8,0x00,0xf0 = cgebr %r15, 0, %f0 0xe3,0x00,0x00,0x00,0x80,0x30 = cgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x30 = cgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x30 = cgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x30 = cgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x30 = cgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x30 = cgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x30 = cgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x30 = cgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x30 = cgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x30 = cgf %r15, 0 0xc2,0x0c,0x80,0x00,0x00,0x00 = cgfi %r0, -2147483648 0xc2,0x0c,0xff,0xff,0xff,0xff = cgfi %r0, -1 0xc2,0x0c,0x00,0x00,0x00,0x00 = cgfi %r0, 0 0xc2,0x0c,0x00,0x00,0x00,0x01 = cgfi %r0, 1 0xc2,0x0c,0x7f,0xff,0xff,0xff = cgfi %r0, 2147483647 0xc2,0xfc,0x00,0x00,0x00,0x00 = cgfi %r15, 0 0xb9,0x30,0x00,0x00 = cgfr %r0, %r0 0xb9,0x30,0x00,0x0f = cgfr %r0, %r15 0xb9,0x30,0x00,0xf0 = cgfr %r15, %r0 0xb9,0x30,0x00,0x78 = cgfr %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x34 = cgh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x34 = cgh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x34 = cgh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x34 = cgh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x34 = cgh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x34 = cgh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x34 = cgh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x34 = cgh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x34 = cgh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x34 = cgh %r15, 0 0xa7,0x0f,0x80,0x00 = cghi %r0, -32768 0xa7,0x0f,0xff,0xff = cghi %r0, -1 0xa7,0x0f,0x00,0x00 = cghi %r0, 0 0xa7,0x0f,0x00,0x01 = cghi %r0, 1 0xa7,0x0f,0x7f,0xff = cghi %r0, 32767 0xa7,0xff,0x00,0x00 = cghi %r15, 0 0xe5,0x58,0x00,0x00,0x00,0x00 = cghsi 0, 0 0xe5,0x58,0x0f,0xff,0x00,0x00 = cghsi 4095, 0 0xe5,0x58,0x00,0x00,0x80,0x00 = cghsi 0, -32768 0xe5,0x58,0x00,0x00,0xff,0xff = cghsi 0, -1 0xe5,0x58,0x00,0x00,0x00,0x00 = cghsi 0, 0 0xe5,0x58,0x00,0x00,0x00,0x01 = cghsi 0, 1 0xe5,0x58,0x00,0x00,0x7f,0xff = cghsi 0, 32767 0xe5,0x58,0x10,0x00,0x00,0x2a = cghsi 0(%r1), 42 0xe5,0x58,0xf0,0x00,0x00,0x2a = cghsi 0(%r15), 42 0xe5,0x58,0x1f,0xff,0x00,0x2a = cghsi 4095(%r1), 42 0xe5,0x58,0xff,0xff,0x00,0x2a = cghsi 4095(%r15), 42 0xb9,0x20,0x00,0x00 = cgr %r0, %r0 0xb9,0x20,0x00,0x0f = cgr %r0, %r15 0xb9,0x20,0x00,0xf0 = cgr %r15, %r0 0xb9,0x20,0x00,0x78 = cgr %r7, %r8 0xb3,0xaa,0x00,0x00 = cgxbr %r0, 0, %f0 0xb3,0xaa,0x00,0x0d = cgxbr %r0, 0, %f13 0xb3,0xaa,0xf0,0x00 = cgxbr %r0, 15, %f0 0xb3,0xaa,0x50,0x48 = cgxbr %r4, 5, %f8 0xb3,0xaa,0x00,0xf0 = cgxbr %r15, 0, %f0 0x49,0x00,0x00,0x00 = ch %r0, 0 0x49,0x00,0x0f,0xff = ch %r0, 4095 0x49,0x00,0x10,0x00 = ch %r0, 0(%r1) 0x49,0x00,0xf0,0x00 = ch %r0, 0(%r15) 0x49,0x01,0xff,0xff = ch %r0, 4095(%r1, %r15) 0x49,0x0f,0x1f,0xff = ch %r0, 4095(%r15, %r1) 0x49,0xf0,0x00,0x00 = ch %r15, 0 0xe5,0x54,0x00,0x00,0x00,0x00 = chhsi 0, 0 0xe5,0x54,0x0f,0xff,0x00,0x00 = chhsi 4095, 0 0xe5,0x54,0x00,0x00,0x80,0x00 = chhsi 0, -32768 0xe5,0x54,0x00,0x00,0xff,0xff = chhsi 0, -1 0xe5,0x54,0x00,0x00,0x00,0x00 = chhsi 0, 0 0xe5,0x54,0x00,0x00,0x00,0x01 = chhsi 0, 1 0xe5,0x54,0x00,0x00,0x7f,0xff = chhsi 0, 32767 0xe5,0x54,0x10,0x00,0x00,0x2a = chhsi 0(%r1), 42 0xe5,0x54,0xf0,0x00,0x00,0x2a = chhsi 0(%r15), 42 0xe5,0x54,0x1f,0xff,0x00,0x2a = chhsi 4095(%r1), 42 0xe5,0x54,0xff,0xff,0x00,0x2a = chhsi 4095(%r15), 42 0xa7,0x0e,0x80,0x00 = chi %r0, -32768 0xa7,0x0e,0xff,0xff = chi %r0, -1 0xa7,0x0e,0x00,0x00 = chi %r0, 0 0xa7,0x0e,0x00,0x01 = chi %r0, 1 0xa7,0x0e,0x7f,0xff = chi %r0, 32767 0xa7,0xfe,0x00,0x00 = chi %r15, 0 0xe5,0x5c,0x00,0x00,0x00,0x00 = chsi 0, 0 0xe5,0x5c,0x0f,0xff,0x00,0x00 = chsi 4095, 0 0xe5,0x5c,0x00,0x00,0x80,0x00 = chsi 0, -32768 0xe5,0x5c,0x00,0x00,0xff,0xff = chsi 0, -1 0xe5,0x5c,0x00,0x00,0x00,0x00 = chsi 0, 0 0xe5,0x5c,0x00,0x00,0x00,0x01 = chsi 0, 1 0xe5,0x5c,0x00,0x00,0x7f,0xff = chsi 0, 32767 0xe5,0x5c,0x10,0x00,0x00,0x2a = chsi 0(%r1), 42 0xe5,0x5c,0xf0,0x00,0x00,0x2a = chsi 0(%r15), 42 0xe5,0x5c,0x1f,0xff,0x00,0x2a = chsi 4095(%r1), 42 0xe5,0x5c,0xff,0xff,0x00,0x2a = chsi 4095(%r15), 42 0xe3,0x00,0x00,0x00,0x80,0x79 = chy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x79 = chy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x79 = chy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x79 = chy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x79 = chy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x79 = chy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x79 = chy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x79 = chy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x79 = chy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x79 = chy %r15, 0 0x55,0x00,0x00,0x00 = cl %r0, 0 0x55,0x00,0x0f,0xff = cl %r0, 4095 0x55,0x00,0x10,0x00 = cl %r0, 0(%r1) 0x55,0x00,0xf0,0x00 = cl %r0, 0(%r15) 0x55,0x01,0xff,0xff = cl %r0, 4095(%r1, %r15) 0x55,0x0f,0x1f,0xff = cl %r0, 4095(%r15, %r1) 0x55,0xf0,0x00,0x00 = cl %r15, 0 0xd5,0x00,0x00,0x00,0x00,0x00 = clc 0(1), 0 0xd5,0x00,0x00,0x00,0x10,0x00 = clc 0(1), 0(%r1) 0xd5,0x00,0x00,0x00,0xf0,0x00 = clc 0(1), 0(%r15) 0xd5,0x00,0x00,0x00,0x0f,0xff = clc 0(1), 4095 0xd5,0x00,0x00,0x00,0x1f,0xff = clc 0(1), 4095(%r1) 0xd5,0x00,0x00,0x00,0xff,0xff = clc 0(1), 4095(%r15) 0xd5,0x00,0x10,0x00,0x00,0x00 = clc 0(1, %r1), 0 0xd5,0x00,0xf0,0x00,0x00,0x00 = clc 0(1, %r15), 0 0xd5,0x00,0x1f,0xff,0x00,0x00 = clc 4095(1, %r1), 0 0xd5,0x00,0xff,0xff,0x00,0x00 = clc 4095(1, %r15), 0 0xd5,0xff,0x10,0x00,0x00,0x00 = clc 0(256, %r1), 0 0xd5,0xff,0xf0,0x00,0x00,0x00 = clc 0(256, %r15), 0 0xe5,0x5d,0x00,0x00,0x00,0x00 = clfhsi 0, 0 0xe5,0x5d,0x0f,0xff,0x00,0x00 = clfhsi 4095, 0 0xe5,0x5d,0x00,0x00,0xff,0xff = clfhsi 0, 65535 0xe5,0x5d,0x10,0x00,0x00,0x2a = clfhsi 0(%r1), 42 0xe5,0x5d,0xf0,0x00,0x00,0x2a = clfhsi 0(%r15), 42 0xe5,0x5d,0x1f,0xff,0x00,0x2a = clfhsi 4095(%r1), 42 0xe5,0x5d,0xff,0xff,0x00,0x2a = clfhsi 4095(%r15), 42 0xc2,0x0f,0x00,0x00,0x00,0x00 = clfi %r0, 0 0xc2,0x0f,0xff,0xff,0xff,0xff = clfi %r0, 4294967295 0xc2,0xff,0x00,0x00,0x00,0x00 = clfi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x21 = clg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x21 = clg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x21 = clg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x21 = clg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x21 = clg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x21 = clg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x21 = clg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x21 = clg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x21 = clg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x21 = clg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x31 = clgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x31 = clgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x31 = clgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x31 = clgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x31 = clgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x31 = clgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x31 = clgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x31 = clgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x31 = clgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x31 = clgf %r15, 0 0xc2,0x0e,0x00,0x00,0x00,0x00 = clgfi %r0, 0 0xc2,0x0e,0xff,0xff,0xff,0xff = clgfi %r0, 4294967295 0xc2,0xfe,0x00,0x00,0x00,0x00 = clgfi %r15, 0 0xb9,0x31,0x00,0x00 = clgfr %r0, %r0 0xb9,0x31,0x00,0x0f = clgfr %r0, %r15 0xb9,0x31,0x00,0xf0 = clgfr %r15, %r0 0xb9,0x31,0x00,0x78 = clgfr %r7, %r8 0xb9,0x21,0x00,0x00 = clgr %r0, %r0 0xb9,0x21,0x00,0x0f = clgr %r0, %r15 0xb9,0x21,0x00,0xf0 = clgr %r15, %r0 0xb9,0x21,0x00,0x78 = clgr %r7, %r8 0xe5,0x55,0x00,0x00,0x00,0x00 = clhhsi 0, 0 0xe5,0x55,0x0f,0xff,0x00,0x00 = clhhsi 4095, 0 0xe5,0x55,0x00,0x00,0xff,0xff = clhhsi 0, 65535 0xe5,0x55,0x10,0x00,0x00,0x2a = clhhsi 0(%r1), 42 0xe5,0x55,0xf0,0x00,0x00,0x2a = clhhsi 0(%r15), 42 0xe5,0x55,0x1f,0xff,0x00,0x2a = clhhsi 4095(%r1), 42 0xe5,0x55,0xff,0xff,0x00,0x2a = clhhsi 4095(%r15), 42 0x95,0x00,0x00,0x00 = cli 0, 0 0x95,0x00,0x0f,0xff = cli 4095, 0 0x95,0xff,0x00,0x00 = cli 0, 255 0x95,0x2a,0x10,0x00 = cli 0(%r1), 42 0x95,0x2a,0xf0,0x00 = cli 0(%r15), 42 0x95,0x2a,0x1f,0xff = cli 4095(%r1), 42 0x95,0x2a,0xff,0xff = cli 4095(%r15), 42 0xeb,0x00,0x00,0x00,0x80,0x55 = cliy -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x55 = cliy -1, 0 0xeb,0x00,0x00,0x00,0x00,0x55 = cliy 0, 0 0xeb,0x00,0x00,0x01,0x00,0x55 = cliy 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x55 = cliy 524287, 0 0xeb,0xff,0x00,0x00,0x00,0x55 = cliy 0, 255 0xeb,0x2a,0x10,0x00,0x00,0x55 = cliy 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x55 = cliy 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x55 = cliy 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x55 = cliy 524287(%r15), 42 0x15,0x00 = clr %r0, %r0 0x15,0x0f = clr %r0, %r15 0x15,0xf0 = clr %r15, %r0 0x15,0x78 = clr %r7, %r8 0xb2,0x5d,0x00,0x00 = clst %r0, %r0 0xb2,0x5d,0x00,0x0f = clst %r0, %r15 0xb2,0x5d,0x00,0xf0 = clst %r15, %r0 0xb2,0x5d,0x00,0x78 = clst %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x55 = cly %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x55 = cly %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x55 = cly %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x55 = cly %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x55 = cly %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x55 = cly %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x55 = cly %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x55 = cly %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x55 = cly %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x55 = cly %r15, 0 0xb3,0x72,0x00,0x00 = cpsdr %f0, %f0, %f0 0xb3,0x72,0x00,0x0f = cpsdr %f0, %f0, %f15 0xb3,0x72,0xf0,0x00 = cpsdr %f0, %f15, %f0 0xb3,0x72,0x00,0xf0 = cpsdr %f15, %f0, %f0 0xb3,0x72,0x20,0x13 = cpsdr %f1, %f2, %f3 0xb3,0x72,0xf0,0xff = cpsdr %f15, %f15, %f15 0x19,0x00 = cr %r0, %r0 0x19,0x0f = cr %r0, %r15 0x19,0xf0 = cr %r15, %r0 0x19,0x78 = cr %r7, %r8 0xba,0x00,0x00,0x00 = cs %r0, %r0, 0 0xba,0x00,0x0f,0xff = cs %r0, %r0, 4095 0xba,0x00,0x10,0x00 = cs %r0, %r0, 0(%r1) 0xba,0x00,0xf0,0x00 = cs %r0, %r0, 0(%r15) 0xba,0x00,0x1f,0xff = cs %r0, %r0, 4095(%r1) 0xba,0x00,0xff,0xff = cs %r0, %r0, 4095(%r15) 0xba,0x0f,0x00,0x00 = cs %r0, %r15, 0 0xba,0xf0,0x00,0x00 = cs %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0x30 = csg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x30 = csg %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0x30 = csg %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0x30 = csg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x30 = csg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x30 = csg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x30 = csg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x30 = csg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x30 = csg %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0x30 = csg %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0x30 = csg %r15, %r0, 0 0xeb,0x00,0x00,0x00,0x80,0x14 = csy %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x14 = csy %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0x14 = csy %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0x14 = csy %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x14 = csy %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x14 = csy %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x14 = csy %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x14 = csy %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x14 = csy %r0, %r0, 524287(%r15) 0xeb,0x0f,0x00,0x00,0x00,0x14 = csy %r0, %r15, 0 0xeb,0xf0,0x00,0x00,0x00,0x14 = csy %r15, %r0, 0 0xb3,0x49,0x00,0x00 = cxbr %f0, %f0 0xb3,0x49,0x00,0x0d = cxbr %f0, %f13 0xb3,0x49,0x00,0x88 = cxbr %f8, %f8 0xb3,0x49,0x00,0xd0 = cxbr %f13, %f0 0xb3,0x96,0x00,0x00 = cxfbr %f0, %r0 0xb3,0x96,0x00,0x0f = cxfbr %f0, %r15 0xb3,0x96,0x00,0xd0 = cxfbr %f13, %r0 0xb3,0x96,0x00,0x87 = cxfbr %f8, %r7 0xb3,0x96,0x00,0xdf = cxfbr %f13, %r15 0xb3,0xa6,0x00,0x00 = cxgbr %f0, %r0 0xb3,0xa6,0x00,0x0f = cxgbr %f0, %r15 0xb3,0xa6,0x00,0xd0 = cxgbr %f13, %r0 0xb3,0xa6,0x00,0x87 = cxgbr %f8, %r7 0xb3,0xa6,0x00,0xdf = cxgbr %f13, %r15 0xe3,0x00,0x00,0x00,0x80,0x59 = cy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x59 = cy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x59 = cy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x59 = cy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x59 = cy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x59 = cy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x59 = cy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x59 = cy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x59 = cy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x59 = cy %r15, 0 0xed,0x00,0x00,0x00,0x00,0x1d = ddb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x1d = ddb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x1d = ddb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x1d = ddb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x1d = ddb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x1d = ddb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x1d = ddb %f15, 0 0xb3,0x1d,0x00,0x00 = ddbr %f0, %f0 0xb3,0x1d,0x00,0x0f = ddbr %f0, %f15 0xb3,0x1d,0x00,0x78 = ddbr %f7, %f8 0xb3,0x1d,0x00,0xf0 = ddbr %f15, %f0 0xed,0x00,0x00,0x00,0x00,0x0d = deb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x0d = deb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x0d = deb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x0d = deb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x0d = deb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x0d = deb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x0d = deb %f15, 0 0xb3,0x0d,0x00,0x00 = debr %f0, %f0 0xb3,0x0d,0x00,0x0f = debr %f0, %f15 0xb3,0x0d,0x00,0x78 = debr %f7, %f8 0xb3,0x0d,0x00,0xf0 = debr %f15, %f0 0xe3,0x00,0x00,0x00,0x80,0x97 = dl %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x97 = dl %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x97 = dl %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x97 = dl %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x97 = dl %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x97 = dl %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x97 = dl %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x97 = dl %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x97 = dl %r0, 524287(%r15, %r1) 0xe3,0xe0,0x00,0x00,0x00,0x97 = dl %r14, 0 0xe3,0x00,0x00,0x00,0x80,0x87 = dlg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x87 = dlg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x87 = dlg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x87 = dlg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x87 = dlg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x87 = dlg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x87 = dlg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x87 = dlg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x87 = dlg %r0, 524287(%r15, %r1) 0xe3,0xe0,0x00,0x00,0x00,0x87 = dlg %r14, 0 0xb9,0x87,0x00,0x00 = dlgr %r0, %r0 0xb9,0x87,0x00,0x0f = dlgr %r0, %r15 0xb9,0x87,0x00,0xe0 = dlgr %r14, %r0 0xb9,0x87,0x00,0x69 = dlgr %r6, %r9 0xb9,0x97,0x00,0x00 = dlr %r0, %r0 0xb9,0x97,0x00,0x0f = dlr %r0, %r15 0xb9,0x97,0x00,0xe0 = dlr %r14, %r0 0xb9,0x97,0x00,0x69 = dlr %r6, %r9 0xe3,0x00,0x00,0x00,0x80,0x0d = dsg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x0d = dsg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x0d = dsg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x0d = dsg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x0d = dsg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x0d = dsg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x0d = dsg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x0d = dsg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x0d = dsg %r0, 524287(%r15, %r1) 0xe3,0xe0,0x00,0x00,0x00,0x0d = dsg %r14, 0 0xe3,0x00,0x00,0x00,0x80,0x1d = dsgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x1d = dsgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x1d = dsgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x1d = dsgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x1d = dsgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x1d = dsgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x1d = dsgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x1d = dsgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x1d = dsgf %r0, 524287(%r15, %r1) 0xe3,0xe0,0x00,0x00,0x00,0x1d = dsgf %r14, 0 0xb9,0x1d,0x00,0x00 = dsgfr %r0, %r0 0xb9,0x1d,0x00,0x0f = dsgfr %r0, %r15 0xb9,0x1d,0x00,0xe0 = dsgfr %r14, %r0 0xb9,0x1d,0x00,0x69 = dsgfr %r6, %r9 0xb9,0x0d,0x00,0x00 = dsgr %r0, %r0 0xb9,0x0d,0x00,0x0f = dsgr %r0, %r15 0xb9,0x0d,0x00,0xe0 = dsgr %r14, %r0 0xb9,0x0d,0x00,0x69 = dsgr %r6, %r9 0xb3,0x4d,0x00,0x00 = dxbr %f0, %f0 0xb3,0x4d,0x00,0x0d = dxbr %f0, %f13 0xb3,0x4d,0x00,0x88 = dxbr %f8, %f8 0xb3,0x4d,0x00,0xd0 = dxbr %f13, %f0 0xb2,0x4f,0x00,0x00 = ear %r0, %a0 0xb2,0x4f,0x00,0x0f = ear %r0, %a15 0xb2,0x4f,0x00,0xf0 = ear %r15, %a0 0xb2,0x4f,0x00,0x78 = ear %r7, %a8 0xb2,0x4f,0x00,0xff = ear %r15, %a15 0xb3,0x5f,0x00,0x00 = fidbr %f0, 0, %f0 0xb3,0x5f,0x00,0x0f = fidbr %f0, 0, %f15 0xb3,0x5f,0xf0,0x00 = fidbr %f0, 15, %f0 0xb3,0x5f,0x50,0x46 = fidbr %f4, 5, %f6 0xb3,0x5f,0x00,0xf0 = fidbr %f15, 0, %f0 0xb3,0x57,0x00,0x00 = fiebr %f0, 0, %f0 0xb3,0x57,0x00,0x0f = fiebr %f0, 0, %f15 0xb3,0x57,0xf0,0x00 = fiebr %f0, 15, %f0 0xb3,0x57,0x50,0x46 = fiebr %f4, 5, %f6 0xb3,0x57,0x00,0xf0 = fiebr %f15, 0, %f0 0xb3,0x47,0x00,0x00 = fixbr %f0, 0, %f0 0xb3,0x47,0x00,0x0d = fixbr %f0, 0, %f13 0xb3,0x47,0xf0,0x00 = fixbr %f0, 15, %f0 0xb3,0x47,0x50,0x48 = fixbr %f4, 5, %f8 0xb3,0x47,0x00,0xd0 = fixbr %f13, 0, %f0 0xb9,0x83,0x00,0x00 = flogr %r0, %r0 0xb9,0x83,0x00,0x0f = flogr %r0, %r15 0xb9,0x83,0x00,0xa9 = flogr %r10, %r9 0xb9,0x83,0x00,0xe0 = flogr %r14, %r0 0x43,0x00,0x00,0x00 = ic %r0, 0 0x43,0x00,0x0f,0xff = ic %r0, 4095 0x43,0x00,0x10,0x00 = ic %r0, 0(%r1) 0x43,0x00,0xf0,0x00 = ic %r0, 0(%r15) 0x43,0x01,0xff,0xff = ic %r0, 4095(%r1, %r15) 0x43,0x0f,0x1f,0xff = ic %r0, 4095(%r15, %r1) 0x43,0xf0,0x00,0x00 = ic %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x73 = icy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x73 = icy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x73 = icy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x73 = icy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x73 = icy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x73 = icy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x73 = icy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x73 = icy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x73 = icy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x73 = icy %r15, 0 0xc0,0x08,0x00,0x00,0x00,0x00 = iihf %r0, 0 0xc0,0x08,0xff,0xff,0xff,0xff = iihf %r0, 4294967295 0xc0,0xf8,0x00,0x00,0x00,0x00 = iihf %r15, 0 0xa5,0x00,0x00,0x00 = iihh %r0, 0 0xa5,0x00,0x80,0x00 = iihh %r0, 32768 0xa5,0x00,0xff,0xff = iihh %r0, 65535 0xa5,0xf0,0x00,0x00 = iihh %r15, 0 0xa5,0x01,0x00,0x00 = iihl %r0, 0 0xa5,0x01,0x80,0x00 = iihl %r0, 32768 0xa5,0x01,0xff,0xff = iihl %r0, 65535 0xa5,0xf1,0x00,0x00 = iihl %r15, 0 0xc0,0x09,0x00,0x00,0x00,0x00 = iilf %r0, 0 0xc0,0x09,0xff,0xff,0xff,0xff = iilf %r0, 4294967295 0xc0,0xf9,0x00,0x00,0x00,0x00 = iilf %r15, 0 0xa5,0x02,0x00,0x00 = iilh %r0, 0 0xa5,0x02,0x80,0x00 = iilh %r0, 32768 0xa5,0x02,0xff,0xff = iilh %r0, 65535 0xa5,0xf2,0x00,0x00 = iilh %r15, 0 0xa5,0x03,0x00,0x00 = iill %r0, 0 0xa5,0x03,0x80,0x00 = iill %r0, 32768 0xa5,0x03,0xff,0xff = iill %r0, 65535 0xa5,0xf3,0x00,0x00 = iill %r15, 0 0xb2,0x22,0x00,0x00 = ipm %r0 0xb2,0x22,0x00,0x10 = ipm %r1 0xb2,0x22,0x00,0xf0 = ipm %r15 0x58,0x00,0x00,0x00 = l %r0, 0 0x58,0x00,0x0f,0xff = l %r0, 4095 0x58,0x00,0x10,0x00 = l %r0, 0(%r1) 0x58,0x00,0xf0,0x00 = l %r0, 0(%r15) 0x58,0x01,0xff,0xff = l %r0, 4095(%r1, %r15) 0x58,0x0f,0x1f,0xff = l %r0, 4095(%r15, %r1) 0x58,0xf0,0x00,0x00 = l %r15, 0 0x41,0x00,0x00,0x00 = la %r0, 0 0x41,0x00,0x0f,0xff = la %r0, 4095 0x41,0x00,0x10,0x00 = la %r0, 0(%r1) 0x41,0x00,0xf0,0x00 = la %r0, 0(%r15) 0x41,0x01,0xff,0xff = la %r0, 4095(%r1, %r15) 0x41,0x0f,0x1f,0xff = la %r0, 4095(%r15, %r1) 0x41,0xf0,0x00,0x00 = la %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x71 = lay %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x71 = lay %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x71 = lay %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x71 = lay %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x71 = lay %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x71 = lay %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x71 = lay %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x71 = lay %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x71 = lay %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x71 = lay %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x76 = lb %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x76 = lb %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x76 = lb %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x76 = lb %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x76 = lb %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x76 = lb %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x76 = lb %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x76 = lb %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x76 = lb %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x76 = lb %r15, 0 0xb9,0x26,0x00,0x0f = lbr %r0, %r15 0xb9,0x26,0x00,0x78 = lbr %r7, %r8 0xb9,0x26,0x00,0xf0 = lbr %r15, %r0 0xb3,0x13,0x00,0x09 = lcdbr %f0, %f9 0xb3,0x13,0x00,0x0f = lcdbr %f0, %f15 0xb3,0x13,0x00,0xf0 = lcdbr %f15, %f0 0xb3,0x13,0x00,0xf9 = lcdbr %f15, %f9 0xb3,0x03,0x00,0x09 = lcebr %f0, %f9 0xb3,0x03,0x00,0x0f = lcebr %f0, %f15 0xb3,0x03,0x00,0xf0 = lcebr %f15, %f0 0xb3,0x03,0x00,0xf9 = lcebr %f15, %f9 0xb9,0x13,0x00,0x00 = lcgfr %r0, %r0 0xb9,0x13,0x00,0x0f = lcgfr %r0, %r15 0xb9,0x13,0x00,0xf0 = lcgfr %r15, %r0 0xb9,0x13,0x00,0x78 = lcgfr %r7, %r8 0xb9,0x03,0x00,0x00 = lcgr %r0, %r0 0xb9,0x03,0x00,0x0f = lcgr %r0, %r15 0xb9,0x03,0x00,0xf0 = lcgr %r15, %r0 0xb9,0x03,0x00,0x78 = lcgr %r7, %r8 0x13,0x00 = lcr %r0, %r0 0x13,0x0f = lcr %r0, %r15 0x13,0xf0 = lcr %r15, %r0 0x13,0x78 = lcr %r7, %r8 0xb3,0x43,0x00,0x08 = lcxbr %f0, %f8 0xb3,0x43,0x00,0x0d = lcxbr %f0, %f13 0xb3,0x43,0x00,0xd0 = lcxbr %f13, %f0 0xb3,0x43,0x00,0xd9 = lcxbr %f13, %f9 0x68,0x00,0x00,0x00 = ld %f0, 0 0x68,0x00,0x0f,0xff = ld %f0, 4095 0x68,0x00,0x10,0x00 = ld %f0, 0(%r1) 0x68,0x00,0xf0,0x00 = ld %f0, 0(%r15) 0x68,0x01,0xff,0xff = ld %f0, 4095(%r1, %r15) 0x68,0x0f,0x1f,0xff = ld %f0, 4095(%r15, %r1) 0x68,0xf0,0x00,0x00 = ld %f15, 0 0xed,0x00,0x00,0x00,0x00,0x04 = ldeb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x04 = ldeb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x04 = ldeb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x04 = ldeb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x04 = ldeb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x04 = ldeb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x04 = ldeb %f15, 0 0xb3,0x04,0x00,0x0f = ldebr %f0, %f15 0xb3,0x04,0x00,0x78 = ldebr %f7, %f8 0xb3,0x04,0x00,0xf0 = ldebr %f15, %f0 0xb3,0xc1,0x00,0x00 = ldgr %f0, %r0 0xb3,0xc1,0x00,0x0f = ldgr %f0, %r15 0xb3,0xc1,0x00,0xf0 = ldgr %f15, %r0 0xb3,0xc1,0x00,0x79 = ldgr %f7, %r9 0xb3,0xc1,0x00,0xff = ldgr %f15, %r15 0x28,0x09 = ldr %f0, %f9 0x28,0x0f = ldr %f0, %f15 0x28,0xf0 = ldr %f15, %f0 0x28,0xf9 = ldr %f15, %f9 0xb3,0x45,0x00,0x00 = ldxbr %f0, %f0 0xb3,0x45,0x00,0x0d = ldxbr %f0, %f13 0xb3,0x45,0x00,0x8c = ldxbr %f8, %f12 0xb3,0x45,0x00,0xd0 = ldxbr %f13, %f0 0xb3,0x45,0x00,0xdd = ldxbr %f13, %f13 0xed,0x00,0x00,0x00,0x80,0x65 = ldy %f0, -524288 0xed,0x00,0x0f,0xff,0xff,0x65 = ldy %f0, -1 0xed,0x00,0x00,0x00,0x00,0x65 = ldy %f0, 0 0xed,0x00,0x00,0x01,0x00,0x65 = ldy %f0, 1 0xed,0x00,0x0f,0xff,0x7f,0x65 = ldy %f0, 524287 0xed,0x00,0x10,0x00,0x00,0x65 = ldy %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x65 = ldy %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x7f,0x65 = ldy %f0, 524287(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x7f,0x65 = ldy %f0, 524287(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x65 = ldy %f15, 0 0x78,0x00,0x00,0x00 = le %f0, 0 0x78,0x00,0x0f,0xff = le %f0, 4095 0x78,0x00,0x10,0x00 = le %f0, 0(%r1) 0x78,0x00,0xf0,0x00 = le %f0, 0(%r15) 0x78,0x01,0xff,0xff = le %f0, 4095(%r1, %r15) 0x78,0x0f,0x1f,0xff = le %f0, 4095(%r15, %r1) 0x78,0xf0,0x00,0x00 = le %f15, 0 0xb3,0x44,0x00,0x00 = ledbr %f0, %f0 0xb3,0x44,0x00,0x0f = ledbr %f0, %f15 0xb3,0x44,0x00,0x78 = ledbr %f7, %f8 0xb3,0x44,0x00,0xf0 = ledbr %f15, %f0 0xb3,0x44,0x00,0xff = ledbr %f15, %f15 0x38,0x09 = ler %f0, %f9 0x38,0x0f = ler %f0, %f15 0x38,0xf0 = ler %f15, %f0 0x38,0xf9 = ler %f15, %f9 0xb3,0x46,0x00,0x00 = lexbr %f0, %f0 0xb3,0x46,0x00,0x0d = lexbr %f0, %f13 0xb3,0x46,0x00,0x8c = lexbr %f8, %f12 0xb3,0x46,0x00,0xd0 = lexbr %f13, %f0 0xb3,0x46,0x00,0xdd = lexbr %f13, %f13 0xed,0x00,0x00,0x00,0x80,0x64 = ley %f0, -524288 0xed,0x00,0x0f,0xff,0xff,0x64 = ley %f0, -1 0xed,0x00,0x00,0x00,0x00,0x64 = ley %f0, 0 0xed,0x00,0x00,0x01,0x00,0x64 = ley %f0, 1 0xed,0x00,0x0f,0xff,0x7f,0x64 = ley %f0, 524287 0xed,0x00,0x10,0x00,0x00,0x64 = ley %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x64 = ley %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x7f,0x64 = ley %f0, 524287(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x7f,0x64 = ley %f0, 524287(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x64 = ley %f15, 0 0xe3,0x00,0x00,0x00,0x80,0x04 = lg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x04 = lg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x04 = lg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x04 = lg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x04 = lg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x04 = lg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x04 = lg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x04 = lg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x04 = lg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x04 = lg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x77 = lgb %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x77 = lgb %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x77 = lgb %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x77 = lgb %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x77 = lgb %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x77 = lgb %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x77 = lgb %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x77 = lgb %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x77 = lgb %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x77 = lgb %r15, 0 0xb9,0x06,0x00,0x0f = lgbr %r0, %r15 0xb9,0x06,0x00,0x78 = lgbr %r7, %r8 0xb9,0x06,0x00,0xf0 = lgbr %r15, %r0 0xb3,0xcd,0x00,0x00 = lgdr %r0, %f0 0xb3,0xcd,0x00,0x0f = lgdr %r0, %f15 0xb3,0xcd,0x00,0xf0 = lgdr %r15, %f0 0xb3,0xcd,0x00,0x88 = lgdr %r8, %f8 0xb3,0xcd,0x00,0xff = lgdr %r15, %f15 0xe3,0x00,0x00,0x00,0x80,0x14 = lgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x14 = lgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x14 = lgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x14 = lgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x14 = lgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x14 = lgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x14 = lgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x14 = lgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x14 = lgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x14 = lgf %r15, 0 0xc0,0x01,0x80,0x00,0x00,0x00 = lgfi %r0, -2147483648 0xc0,0x01,0xff,0xff,0xff,0xff = lgfi %r0, -1 0xc0,0x01,0x00,0x00,0x00,0x00 = lgfi %r0, 0 0xc0,0x01,0x00,0x00,0x00,0x01 = lgfi %r0, 1 0xc0,0x01,0x7f,0xff,0xff,0xff = lgfi %r0, 2147483647 0xc0,0xf1,0x00,0x00,0x00,0x00 = lgfi %r15, 0 0xb9,0x14,0x00,0x0f = lgfr %r0, %r15 0xb9,0x14,0x00,0x78 = lgfr %r7, %r8 0xb9,0x14,0x00,0xf0 = lgfr %r15, %r0 0xe3,0x00,0x00,0x00,0x80,0x15 = lgh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x15 = lgh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x15 = lgh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x15 = lgh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x15 = lgh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x15 = lgh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x15 = lgh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x15 = lgh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x15 = lgh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x15 = lgh %r15, 0 0xa7,0x09,0x80,0x00 = lghi %r0, -32768 0xa7,0x09,0xff,0xff = lghi %r0, -1 0xa7,0x09,0x00,0x00 = lghi %r0, 0 0xa7,0x09,0x00,0x01 = lghi %r0, 1 0xa7,0x09,0x7f,0xff = lghi %r0, 32767 0xa7,0xf9,0x00,0x00 = lghi %r15, 0 0xb9,0x07,0x00,0x0f = lghr %r0, %r15 0xb9,0x07,0x00,0x78 = lghr %r7, %r8 0xb9,0x07,0x00,0xf0 = lghr %r15, %r0 0xb9,0x04,0x00,0x09 = lgr %r0, %r9 0xb9,0x04,0x00,0x0f = lgr %r0, %r15 0xb9,0x04,0x00,0xf0 = lgr %r15, %r0 0xb9,0x04,0x00,0xf9 = lgr %r15, %r9 0x48,0x00,0x00,0x00 = lh %r0, 0 0x48,0x00,0x0f,0xff = lh %r0, 4095 0x48,0x00,0x10,0x00 = lh %r0, 0(%r1) 0x48,0x00,0xf0,0x00 = lh %r0, 0(%r15) 0x48,0x01,0xff,0xff = lh %r0, 4095(%r1, %r15) 0x48,0x0f,0x1f,0xff = lh %r0, 4095(%r15, %r1) 0x48,0xf0,0x00,0x00 = lh %r15, 0 0xa7,0x08,0x80,0x00 = lhi %r0, -32768 0xa7,0x08,0xff,0xff = lhi %r0, -1 0xa7,0x08,0x00,0x00 = lhi %r0, 0 0xa7,0x08,0x00,0x01 = lhi %r0, 1 0xa7,0x08,0x7f,0xff = lhi %r0, 32767 0xa7,0xf8,0x00,0x00 = lhi %r15, 0 0xb9,0x27,0x00,0x0f = lhr %r0, %r15 0xb9,0x27,0x00,0x78 = lhr %r7, %r8 0xb9,0x27,0x00,0xf0 = lhr %r15, %r0 0xe3,0x00,0x00,0x00,0x80,0x78 = lhy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x78 = lhy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x78 = lhy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x78 = lhy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x78 = lhy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x78 = lhy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x78 = lhy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x78 = lhy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x78 = lhy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x78 = lhy %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x94 = llc %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x94 = llc %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x94 = llc %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x94 = llc %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x94 = llc %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x94 = llc %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x94 = llc %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x94 = llc %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x94 = llc %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x94 = llc %r15, 0 0xb9,0x94,0x00,0x0f = llcr %r0, %r15 0xb9,0x94,0x00,0x78 = llcr %r7, %r8 0xb9,0x94,0x00,0xf0 = llcr %r15, %r0 0xe3,0x00,0x00,0x00,0x80,0x90 = llgc %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x90 = llgc %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x90 = llgc %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x90 = llgc %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x90 = llgc %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x90 = llgc %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x90 = llgc %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x90 = llgc %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x90 = llgc %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x90 = llgc %r15, 0 0xb9,0x84,0x00,0x0f = llgcr %r0, %r15 0xb9,0x84,0x00,0x78 = llgcr %r7, %r8 0xb9,0x84,0x00,0xf0 = llgcr %r15, %r0 0xe3,0x00,0x00,0x00,0x80,0x16 = llgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x16 = llgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x16 = llgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x16 = llgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x16 = llgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x16 = llgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x16 = llgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x16 = llgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x16 = llgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x16 = llgf %r15, 0 0xb9,0x16,0x00,0x0f = llgfr %r0, %r15 0xb9,0x16,0x00,0x78 = llgfr %r7, %r8 0xb9,0x16,0x00,0xf0 = llgfr %r15, %r0 0xe3,0x00,0x00,0x00,0x80,0x91 = llgh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x91 = llgh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x91 = llgh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x91 = llgh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x91 = llgh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x91 = llgh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x91 = llgh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x91 = llgh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x91 = llgh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x91 = llgh %r15, 0 0xb9,0x85,0x00,0x0f = llghr %r0, %r15 0xb9,0x85,0x00,0x78 = llghr %r7, %r8 0xb9,0x85,0x00,0xf0 = llghr %r15, %r0 0xe3,0x00,0x00,0x00,0x80,0x95 = llh %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x95 = llh %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x95 = llh %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x95 = llh %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x95 = llh %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x95 = llh %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x95 = llh %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x95 = llh %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x95 = llh %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x95 = llh %r15, 0 0xb9,0x95,0x00,0x0f = llhr %r0, %r15 0xb9,0x95,0x00,0x78 = llhr %r7, %r8 0xb9,0x95,0x00,0xf0 = llhr %r15, %r0 0xc0,0x0e,0x00,0x00,0x00,0x00 = llihf %r0, 0 0xc0,0x0e,0xff,0xff,0xff,0xff = llihf %r0, 4294967295 0xc0,0xfe,0x00,0x00,0x00,0x00 = llihf %r15, 0 0xa5,0x0c,0x00,0x00 = llihh %r0, 0 0xa5,0x0c,0x80,0x00 = llihh %r0, 32768 0xa5,0x0c,0xff,0xff = llihh %r0, 65535 0xa5,0xfc,0x00,0x00 = llihh %r15, 0 0xa5,0x0d,0x00,0x00 = llihl %r0, 0 0xa5,0x0d,0x80,0x00 = llihl %r0, 32768 0xa5,0x0d,0xff,0xff = llihl %r0, 65535 0xa5,0xfd,0x00,0x00 = llihl %r15, 0 0xc0,0x0f,0x00,0x00,0x00,0x00 = llilf %r0, 0 0xc0,0x0f,0xff,0xff,0xff,0xff = llilf %r0, 4294967295 0xc0,0xff,0x00,0x00,0x00,0x00 = llilf %r15, 0 0xa5,0x0e,0x00,0x00 = llilh %r0, 0 0xa5,0x0e,0x80,0x00 = llilh %r0, 32768 0xa5,0x0e,0xff,0xff = llilh %r0, 65535 0xa5,0xfe,0x00,0x00 = llilh %r15, 0 0xa5,0x0f,0x00,0x00 = llill %r0, 0 0xa5,0x0f,0x80,0x00 = llill %r0, 32768 0xa5,0x0f,0xff,0xff = llill %r0, 65535 0xa5,0xff,0x00,0x00 = llill %r15, 0 0xeb,0x00,0x00,0x00,0x00,0x04 = lmg %r0, %r0, 0 0xeb,0x0f,0x00,0x00,0x00,0x04 = lmg %r0, %r15, 0 0xeb,0xef,0x00,0x00,0x00,0x04 = lmg %r14, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x04 = lmg %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x04 = lmg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x04 = lmg %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0x04 = lmg %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0x04 = lmg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x04 = lmg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x04 = lmg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x04 = lmg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x04 = lmg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x04 = lmg %r0, %r0, 524287(%r15) 0xb3,0x11,0x00,0x09 = lndbr %f0, %f9 0xb3,0x11,0x00,0x0f = lndbr %f0, %f15 0xb3,0x11,0x00,0xf0 = lndbr %f15, %f0 0xb3,0x11,0x00,0xf9 = lndbr %f15, %f9 0xb3,0x01,0x00,0x09 = lnebr %f0, %f9 0xb3,0x01,0x00,0x0f = lnebr %f0, %f15 0xb3,0x01,0x00,0xf0 = lnebr %f15, %f0 0xb3,0x01,0x00,0xf9 = lnebr %f15, %f9 0xb9,0x11,0x00,0x00 = lngfr %r0, %r0 0xb9,0x11,0x00,0x0f = lngfr %r0, %r15 0xb9,0x11,0x00,0xf0 = lngfr %r15, %r0 0xb9,0x11,0x00,0x78 = lngfr %r7, %r8 0xb9,0x01,0x00,0x00 = lngr %r0, %r0 0xb9,0x01,0x00,0x0f = lngr %r0, %r15 0xb9,0x01,0x00,0xf0 = lngr %r15, %r0 0xb9,0x01,0x00,0x78 = lngr %r7, %r8 0x11,0x00 = lnr %r0, %r0 0x11,0x0f = lnr %r0, %r15 0x11,0xf0 = lnr %r15, %r0 0x11,0x78 = lnr %r7, %r8 0xb3,0x41,0x00,0x08 = lnxbr %f0, %f8 0xb3,0x41,0x00,0x0d = lnxbr %f0, %f13 0xb3,0x41,0x00,0xd0 = lnxbr %f13, %f0 0xb3,0x41,0x00,0xd9 = lnxbr %f13, %f9 0xb3,0x10,0x00,0x09 = lpdbr %f0, %f9 0xb3,0x10,0x00,0x0f = lpdbr %f0, %f15 0xb3,0x10,0x00,0xf0 = lpdbr %f15, %f0 0xb3,0x10,0x00,0xf9 = lpdbr %f15, %f9 0xb3,0x00,0x00,0x09 = lpebr %f0, %f9 0xb3,0x00,0x00,0x0f = lpebr %f0, %f15 0xb3,0x00,0x00,0xf0 = lpebr %f15, %f0 0xb3,0x00,0x00,0xf9 = lpebr %f15, %f9 0xb9,0x10,0x00,0x00 = lpgfr %r0, %r0 0xb9,0x10,0x00,0x0f = lpgfr %r0, %r15 0xb9,0x10,0x00,0xf0 = lpgfr %r15, %r0 0xb9,0x10,0x00,0x78 = lpgfr %r7, %r8 0xb9,0x00,0x00,0x00 = lpgr %r0, %r0 0xb9,0x00,0x00,0x0f = lpgr %r0, %r15 0xb9,0x00,0x00,0xf0 = lpgr %r15, %r0 0xb9,0x00,0x00,0x78 = lpgr %r7, %r8 0x10,0x00 = lpr %r0, %r0 0x10,0x0f = lpr %r0, %r15 0x10,0xf0 = lpr %r15, %r0 0x10,0x78 = lpr %r7, %r8 0xb3,0x40,0x00,0x08 = lpxbr %f0, %f8 0xb3,0x40,0x00,0x0d = lpxbr %f0, %f13 0xb3,0x40,0x00,0xd0 = lpxbr %f13, %f0 0xb3,0x40,0x00,0xd9 = lpxbr %f13, %f9 0x18,0x09 = lr %r0, %r9 0x18,0x0f = lr %r0, %r15 0x18,0xf0 = lr %r15, %r0 0x18,0xf9 = lr %r15, %r9 0xe3,0x00,0x00,0x00,0x80,0x1e = lrv %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x1e = lrv %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x1e = lrv %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x1e = lrv %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x1e = lrv %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x1e = lrv %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x1e = lrv %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x1e = lrv %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x1e = lrv %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x1e = lrv %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x0f = lrvg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x0f = lrvg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x0f = lrvg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x0f = lrvg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x0f = lrvg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x0f = lrvg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x0f = lrvg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x0f = lrvg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x0f = lrvg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x0f = lrvg %r15, 0 0xb9,0x0f,0x00,0x00 = lrvgr %r0, %r0 0xb9,0x0f,0x00,0x0f = lrvgr %r0, %r15 0xb9,0x0f,0x00,0xf0 = lrvgr %r15, %r0 0xb9,0x0f,0x00,0x78 = lrvgr %r7, %r8 0xb9,0x0f,0x00,0xff = lrvgr %r15, %r15 0xb9,0x1f,0x00,0x00 = lrvr %r0, %r0 0xb9,0x1f,0x00,0x0f = lrvr %r0, %r15 0xb9,0x1f,0x00,0xf0 = lrvr %r15, %r0 0xb9,0x1f,0x00,0x78 = lrvr %r7, %r8 0xb9,0x1f,0x00,0xff = lrvr %r15, %r15 0xe3,0x00,0x00,0x00,0x80,0x12 = lt %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x12 = lt %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x12 = lt %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x12 = lt %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x12 = lt %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x12 = lt %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x12 = lt %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x12 = lt %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x12 = lt %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x12 = lt %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x02 = ltg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x02 = ltg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x02 = ltg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x02 = ltg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x02 = ltg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x02 = ltg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x02 = ltg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x02 = ltg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x02 = ltg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x02 = ltg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x32 = ltgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x32 = ltgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x32 = ltgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x32 = ltgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x32 = ltgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x32 = ltgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x32 = ltgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x32 = ltgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x32 = ltgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x32 = ltgf %r15, 0 0xb3,0x12,0x00,0x09 = ltdbr %f0, %f9 0xb3,0x12,0x00,0x0f = ltdbr %f0, %f15 0xb3,0x12,0x00,0xf0 = ltdbr %f15, %f0 0xb3,0x12,0x00,0xf9 = ltdbr %f15, %f9 0xb3,0x02,0x00,0x09 = ltebr %f0, %f9 0xb3,0x02,0x00,0x0f = ltebr %f0, %f15 0xb3,0x02,0x00,0xf0 = ltebr %f15, %f0 0xb3,0x02,0x00,0xf9 = ltebr %f15, %f9 0xb9,0x12,0x00,0x09 = ltgfr %r0, %r9 0xb9,0x12,0x00,0x0f = ltgfr %r0, %r15 0xb9,0x12,0x00,0xf0 = ltgfr %r15, %r0 0xb9,0x12,0x00,0xf9 = ltgfr %r15, %r9 0xb9,0x02,0x00,0x09 = ltgr %r0, %r9 0xb9,0x02,0x00,0x0f = ltgr %r0, %r15 0xb9,0x02,0x00,0xf0 = ltgr %r15, %r0 0xb9,0x02,0x00,0xf9 = ltgr %r15, %r9 0x12,0x09 = ltr %r0, %r9 0x12,0x0f = ltr %r0, %r15 0x12,0xf0 = ltr %r15, %r0 0x12,0xf9 = ltr %r15, %r9 0xb3,0x42,0x00,0x09 = ltxbr %f0, %f9 0xb3,0x42,0x00,0x0d = ltxbr %f0, %f13 0xb3,0x42,0x00,0xd0 = ltxbr %f13, %f0 0xb3,0x42,0x00,0xd9 = ltxbr %f13, %f9 0xb3,0x65,0x00,0x08 = lxr %f0, %f8 0xb3,0x65,0x00,0x0d = lxr %f0, %f13 0xb3,0x65,0x00,0xd0 = lxr %f13, %f0 0xb3,0x65,0x00,0xd9 = lxr %f13, %f9 0xe3,0x00,0x00,0x00,0x80,0x58 = ly %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x58 = ly %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x58 = ly %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x58 = ly %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x58 = ly %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x58 = ly %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x58 = ly %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x58 = ly %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x58 = ly %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x58 = ly %r15, 0 0xb3,0x75,0x00,0x00 = lzdr %f0 0xb3,0x75,0x00,0x70 = lzdr %f7 0xb3,0x75,0x00,0xf0 = lzdr %f15 0xb3,0x74,0x00,0x00 = lzer %f0 0xb3,0x74,0x00,0x70 = lzer %f7 0xb3,0x74,0x00,0xf0 = lzer %f15 0xb3,0x76,0x00,0x00 = lzxr %f0 0xb3,0x76,0x00,0x80 = lzxr %f8 0xb3,0x76,0x00,0xd0 = lzxr %f13 0xed,0x00,0x00,0x00,0x00,0x1e = madb %f0, %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x1e = madb %f0, %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x1e = madb %f0, %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x1e = madb %f0, %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x1e = madb %f0, %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x1e = madb %f0, %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x1e = madb %f0, %f15, 0 0xed,0x00,0x00,0x00,0xf0,0x1e = madb %f15, %f0, 0 0xed,0xf0,0x00,0x00,0xf0,0x1e = madb %f15, %f15, 0 0xb3,0x1e,0x00,0x00 = madbr %f0, %f0, %f0 0xb3,0x1e,0x00,0x0f = madbr %f0, %f0, %f15 0xb3,0x1e,0x00,0xf0 = madbr %f0, %f15, %f0 0xb3,0x1e,0xf0,0x00 = madbr %f15, %f0, %f0 0xb3,0x1e,0x70,0x89 = madbr %f7, %f8, %f9 0xb3,0x1e,0xf0,0xff = madbr %f15, %f15, %f15 0xed,0x00,0x00,0x00,0x00,0x0e = maeb %f0, %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x0e = maeb %f0, %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x0e = maeb %f0, %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x0e = maeb %f0, %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x0e = maeb %f0, %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x0e = maeb %f0, %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x0e = maeb %f0, %f15, 0 0xed,0x00,0x00,0x00,0xf0,0x0e = maeb %f15, %f0, 0 0xed,0xf0,0x00,0x00,0xf0,0x0e = maeb %f15, %f15, 0 0xb3,0x0e,0x00,0x00 = maebr %f0, %f0, %f0 0xb3,0x0e,0x00,0x0f = maebr %f0, %f0, %f15 0xb3,0x0e,0x00,0xf0 = maebr %f0, %f15, %f0 0xb3,0x0e,0xf0,0x00 = maebr %f15, %f0, %f0 0xb3,0x0e,0x70,0x89 = maebr %f7, %f8, %f9 0xb3,0x0e,0xf0,0xff = maebr %f15, %f15, %f15 0xed,0x00,0x00,0x00,0x00,0x1c = mdb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x1c = mdb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x1c = mdb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x1c = mdb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x1c = mdb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x1c = mdb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x1c = mdb %f15, 0 0xb3,0x1c,0x00,0x00 = mdbr %f0, %f0 0xb3,0x1c,0x00,0x0f = mdbr %f0, %f15 0xb3,0x1c,0x00,0x78 = mdbr %f7, %f8 0xb3,0x1c,0x00,0xf0 = mdbr %f15, %f0 0xed,0x00,0x00,0x00,0x00,0x0c = mdeb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x0c = mdeb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x0c = mdeb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x0c = mdeb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x0c = mdeb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x0c = mdeb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x0c = mdeb %f15, 0 0xb3,0x0c,0x00,0x00 = mdebr %f0, %f0 0xb3,0x0c,0x00,0x0f = mdebr %f0, %f15 0xb3,0x0c,0x00,0x78 = mdebr %f7, %f8 0xb3,0x0c,0x00,0xf0 = mdebr %f15, %f0 0xed,0x00,0x00,0x00,0x00,0x17 = meeb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x17 = meeb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x17 = meeb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x17 = meeb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x17 = meeb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x17 = meeb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x17 = meeb %f15, 0 0xb3,0x17,0x00,0x00 = meebr %f0, %f0 0xb3,0x17,0x00,0x0f = meebr %f0, %f15 0xb3,0x17,0x00,0x78 = meebr %f7, %f8 0xb3,0x17,0x00,0xf0 = meebr %f15, %f0 0xa7,0x0d,0x80,0x00 = mghi %r0, -32768 0xa7,0x0d,0xff,0xff = mghi %r0, -1 0xa7,0x0d,0x00,0x00 = mghi %r0, 0 0xa7,0x0d,0x00,0x01 = mghi %r0, 1 0xa7,0x0d,0x7f,0xff = mghi %r0, 32767 0xa7,0xfd,0x00,0x00 = mghi %r15, 0 0x4c,0x00,0x00,0x00 = mh %r0, 0 0x4c,0x00,0x0f,0xff = mh %r0, 4095 0x4c,0x00,0x10,0x00 = mh %r0, 0(%r1) 0x4c,0x00,0xf0,0x00 = mh %r0, 0(%r15) 0x4c,0x01,0xff,0xff = mh %r0, 4095(%r1, %r15) 0x4c,0x0f,0x1f,0xff = mh %r0, 4095(%r15, %r1) 0x4c,0xf0,0x00,0x00 = mh %r15, 0 0xa7,0x0c,0x80,0x00 = mhi %r0, -32768 0xa7,0x0c,0xff,0xff = mhi %r0, -1 0xa7,0x0c,0x00,0x00 = mhi %r0, 0 0xa7,0x0c,0x00,0x01 = mhi %r0, 1 0xa7,0x0c,0x7f,0xff = mhi %r0, 32767 0xa7,0xfc,0x00,0x00 = mhi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x7c = mhy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x7c = mhy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x7c = mhy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x7c = mhy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x7c = mhy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x7c = mhy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x7c = mhy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x7c = mhy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x7c = mhy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x7c = mhy %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x86 = mlg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x86 = mlg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x86 = mlg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x86 = mlg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x86 = mlg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x86 = mlg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x86 = mlg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x86 = mlg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x86 = mlg %r0, 524287(%r15, %r1) 0xe3,0xe0,0x00,0x00,0x00,0x86 = mlg %r14, 0 0xb9,0x86,0x00,0x00 = mlgr %r0, %r0 0xb9,0x86,0x00,0x0f = mlgr %r0, %r15 0xb9,0x86,0x00,0xe0 = mlgr %r14, %r0 0xb9,0x86,0x00,0x69 = mlgr %r6, %r9 0x71,0x00,0x00,0x00 = ms %r0, 0 0x71,0x00,0x0f,0xff = ms %r0, 4095 0x71,0x00,0x10,0x00 = ms %r0, 0(%r1) 0x71,0x00,0xf0,0x00 = ms %r0, 0(%r15) 0x71,0x01,0xff,0xff = ms %r0, 4095(%r1, %r15) 0x71,0x0f,0x1f,0xff = ms %r0, 4095(%r15, %r1) 0x71,0xf0,0x00,0x00 = ms %r15, 0 0xed,0x00,0x00,0x00,0x00,0x1f = msdb %f0, %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x1f = msdb %f0, %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x1f = msdb %f0, %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x1f = msdb %f0, %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x1f = msdb %f0, %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x1f = msdb %f0, %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x1f = msdb %f0, %f15, 0 0xed,0x00,0x00,0x00,0xf0,0x1f = msdb %f15, %f0, 0 0xed,0xf0,0x00,0x00,0xf0,0x1f = msdb %f15, %f15, 0 0xb3,0x1f,0x00,0x00 = msdbr %f0, %f0, %f0 0xb3,0x1f,0x00,0x0f = msdbr %f0, %f0, %f15 0xb3,0x1f,0x00,0xf0 = msdbr %f0, %f15, %f0 0xb3,0x1f,0xf0,0x00 = msdbr %f15, %f0, %f0 0xb3,0x1f,0x70,0x89 = msdbr %f7, %f8, %f9 0xb3,0x1f,0xf0,0xff = msdbr %f15, %f15, %f15 0xed,0x00,0x00,0x00,0x00,0x0f = mseb %f0, %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x0f = mseb %f0, %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x0f = mseb %f0, %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x0f = mseb %f0, %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x0f = mseb %f0, %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x0f = mseb %f0, %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x0f = mseb %f0, %f15, 0 0xed,0x00,0x00,0x00,0xf0,0x0f = mseb %f15, %f0, 0 0xed,0xf0,0x00,0x00,0xf0,0x0f = mseb %f15, %f15, 0 0xb3,0x0f,0x00,0x00 = msebr %f0, %f0, %f0 0xb3,0x0f,0x00,0x0f = msebr %f0, %f0, %f15 0xb3,0x0f,0x00,0xf0 = msebr %f0, %f15, %f0 0xb3,0x0f,0xf0,0x00 = msebr %f15, %f0, %f0 0xb3,0x0f,0x70,0x89 = msebr %f7, %f8, %f9 0xb3,0x0f,0xf0,0xff = msebr %f15, %f15, %f15 0xc2,0x01,0x80,0x00,0x00,0x00 = msfi %r0, -2147483648 0xc2,0x01,0xff,0xff,0xff,0xff = msfi %r0, -1 0xc2,0x01,0x00,0x00,0x00,0x00 = msfi %r0, 0 0xc2,0x01,0x00,0x00,0x00,0x01 = msfi %r0, 1 0xc2,0x01,0x7f,0xff,0xff,0xff = msfi %r0, 2147483647 0xc2,0xf1,0x00,0x00,0x00,0x00 = msfi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x0c = msg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x0c = msg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x0c = msg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x0c = msg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x0c = msg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x0c = msg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x0c = msg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x0c = msg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x0c = msg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x0c = msg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x1c = msgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x1c = msgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x1c = msgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x1c = msgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x1c = msgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x1c = msgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x1c = msgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x1c = msgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x1c = msgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x1c = msgf %r15, 0 0xc2,0x00,0x80,0x00,0x00,0x00 = msgfi %r0, -2147483648 0xc2,0x00,0xff,0xff,0xff,0xff = msgfi %r0, -1 0xc2,0x00,0x00,0x00,0x00,0x00 = msgfi %r0, 0 0xc2,0x00,0x00,0x00,0x00,0x01 = msgfi %r0, 1 0xc2,0x00,0x7f,0xff,0xff,0xff = msgfi %r0, 2147483647 0xc2,0xf0,0x00,0x00,0x00,0x00 = msgfi %r15, 0 0xb9,0x1c,0x00,0x00 = msgfr %r0, %r0 0xb9,0x1c,0x00,0x0f = msgfr %r0, %r15 0xb9,0x1c,0x00,0xf0 = msgfr %r15, %r0 0xb9,0x1c,0x00,0x78 = msgfr %r7, %r8 0xb9,0x0c,0x00,0x00 = msgr %r0, %r0 0xb9,0x0c,0x00,0x0f = msgr %r0, %r15 0xb9,0x0c,0x00,0xf0 = msgr %r15, %r0 0xb9,0x0c,0x00,0x78 = msgr %r7, %r8 0xb2,0x52,0x00,0x00 = msr %r0, %r0 0xb2,0x52,0x00,0x0f = msr %r0, %r15 0xb2,0x52,0x00,0xf0 = msr %r15, %r0 0xb2,0x52,0x00,0x78 = msr %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x51 = msy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x51 = msy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x51 = msy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x51 = msy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x51 = msy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x51 = msy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x51 = msy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x51 = msy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x51 = msy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x51 = msy %r15, 0 0xd2,0x00,0x00,0x00,0x00,0x00 = mvc 0(1), 0 0xd2,0x00,0x00,0x00,0x10,0x00 = mvc 0(1), 0(%r1) 0xd2,0x00,0x00,0x00,0xf0,0x00 = mvc 0(1), 0(%r15) 0xd2,0x00,0x00,0x00,0x0f,0xff = mvc 0(1), 4095 0xd2,0x00,0x00,0x00,0x1f,0xff = mvc 0(1), 4095(%r1) 0xd2,0x00,0x00,0x00,0xff,0xff = mvc 0(1), 4095(%r15) 0xd2,0x00,0x10,0x00,0x00,0x00 = mvc 0(1, %r1), 0 0xd2,0x00,0xf0,0x00,0x00,0x00 = mvc 0(1, %r15), 0 0xd2,0x00,0x1f,0xff,0x00,0x00 = mvc 4095(1, %r1), 0 0xd2,0x00,0xff,0xff,0x00,0x00 = mvc 4095(1, %r15), 0 0xd2,0xff,0x10,0x00,0x00,0x00 = mvc 0(256, %r1), 0 0xd2,0xff,0xf0,0x00,0x00,0x00 = mvc 0(256, %r15), 0 0xe5,0x48,0x00,0x00,0x00,0x00 = mvghi 0, 0 0xe5,0x48,0x0f,0xff,0x00,0x00 = mvghi 4095, 0 0xe5,0x48,0x00,0x00,0x80,0x00 = mvghi 0, -32768 0xe5,0x48,0x00,0x00,0xff,0xff = mvghi 0, -1 0xe5,0x48,0x00,0x00,0x00,0x00 = mvghi 0, 0 0xe5,0x48,0x00,0x00,0x00,0x01 = mvghi 0, 1 0xe5,0x48,0x00,0x00,0x7f,0xff = mvghi 0, 32767 0xe5,0x48,0x10,0x00,0x00,0x2a = mvghi 0(%r1), 42 0xe5,0x48,0xf0,0x00,0x00,0x2a = mvghi 0(%r15), 42 0xe5,0x48,0x1f,0xff,0x00,0x2a = mvghi 4095(%r1), 42 0xe5,0x48,0xff,0xff,0x00,0x2a = mvghi 4095(%r15), 42 0xe5,0x44,0x00,0x00,0x00,0x00 = mvhhi 0, 0 0xe5,0x44,0x0f,0xff,0x00,0x00 = mvhhi 4095, 0 0xe5,0x44,0x00,0x00,0x80,0x00 = mvhhi 0, -32768 0xe5,0x44,0x00,0x00,0xff,0xff = mvhhi 0, -1 0xe5,0x44,0x00,0x00,0x00,0x00 = mvhhi 0, 0 0xe5,0x44,0x00,0x00,0x00,0x01 = mvhhi 0, 1 0xe5,0x44,0x00,0x00,0x7f,0xff = mvhhi 0, 32767 0xe5,0x44,0x10,0x00,0x00,0x2a = mvhhi 0(%r1), 42 0xe5,0x44,0xf0,0x00,0x00,0x2a = mvhhi 0(%r15), 42 0xe5,0x44,0x1f,0xff,0x00,0x2a = mvhhi 4095(%r1), 42 0xe5,0x44,0xff,0xff,0x00,0x2a = mvhhi 4095(%r15), 42 0xe5,0x4c,0x00,0x00,0x00,0x00 = mvhi 0, 0 0xe5,0x4c,0x0f,0xff,0x00,0x00 = mvhi 4095, 0 0xe5,0x4c,0x00,0x00,0x80,0x00 = mvhi 0, -32768 0xe5,0x4c,0x00,0x00,0xff,0xff = mvhi 0, -1 0xe5,0x4c,0x00,0x00,0x00,0x00 = mvhi 0, 0 0xe5,0x4c,0x00,0x00,0x00,0x01 = mvhi 0, 1 0xe5,0x4c,0x00,0x00,0x7f,0xff = mvhi 0, 32767 0xe5,0x4c,0x10,0x00,0x00,0x2a = mvhi 0(%r1), 42 0xe5,0x4c,0xf0,0x00,0x00,0x2a = mvhi 0(%r15), 42 0xe5,0x4c,0x1f,0xff,0x00,0x2a = mvhi 4095(%r1), 42 0xe5,0x4c,0xff,0xff,0x00,0x2a = mvhi 4095(%r15), 42 0x92,0x00,0x00,0x00 = mvi 0, 0 0x92,0x00,0x0f,0xff = mvi 4095, 0 0x92,0xff,0x00,0x00 = mvi 0, 255 0x92,0x2a,0x10,0x00 = mvi 0(%r1), 42 0x92,0x2a,0xf0,0x00 = mvi 0(%r15), 42 0x92,0x2a,0x1f,0xff = mvi 4095(%r1), 42 0x92,0x2a,0xff,0xff = mvi 4095(%r15), 42 0xeb,0x00,0x00,0x00,0x80,0x52 = mviy -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x52 = mviy -1, 0 0xeb,0x00,0x00,0x00,0x00,0x52 = mviy 0, 0 0xeb,0x00,0x00,0x01,0x00,0x52 = mviy 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x52 = mviy 524287, 0 0xeb,0xff,0x00,0x00,0x00,0x52 = mviy 0, 255 0xeb,0x2a,0x10,0x00,0x00,0x52 = mviy 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x52 = mviy 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x52 = mviy 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x52 = mviy 524287(%r15), 42 0xb2,0x55,0x00,0x00 = mvst %r0, %r0 0xb2,0x55,0x00,0x0f = mvst %r0, %r15 0xb2,0x55,0x00,0xf0 = mvst %r15, %r0 0xb2,0x55,0x00,0x78 = mvst %r7, %r8 0xb3,0x4c,0x00,0x00 = mxbr %f0, %f0 0xb3,0x4c,0x00,0x0d = mxbr %f0, %f13 0xb3,0x4c,0x00,0x85 = mxbr %f8, %f5 0xb3,0x4c,0x00,0xdd = mxbr %f13, %f13 0xed,0x00,0x00,0x00,0x00,0x07 = mxdb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x07 = mxdb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x07 = mxdb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x07 = mxdb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x07 = mxdb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x07 = mxdb %f0, 4095(%r15, %r1) 0xed,0xd0,0x00,0x00,0x00,0x07 = mxdb %f13, 0 0xb3,0x07,0x00,0x00 = mxdbr %f0, %f0 0xb3,0x07,0x00,0x0f = mxdbr %f0, %f15 0xb3,0x07,0x00,0x88 = mxdbr %f8, %f8 0xb3,0x07,0x00,0xd0 = mxdbr %f13, %f0 0x54,0x00,0x00,0x00 = n %r0, 0 0x54,0x00,0x0f,0xff = n %r0, 4095 0x54,0x00,0x10,0x00 = n %r0, 0(%r1) 0x54,0x00,0xf0,0x00 = n %r0, 0(%r15) 0x54,0x01,0xff,0xff = n %r0, 4095(%r1, %r15) 0x54,0x0f,0x1f,0xff = n %r0, 4095(%r15, %r1) 0x54,0xf0,0x00,0x00 = n %r15, 0 0xd4,0x00,0x00,0x00,0x00,0x00 = nc 0(1), 0 0xd4,0x00,0x00,0x00,0x10,0x00 = nc 0(1), 0(%r1) 0xd4,0x00,0x00,0x00,0xf0,0x00 = nc 0(1), 0(%r15) 0xd4,0x00,0x00,0x00,0x0f,0xff = nc 0(1), 4095 0xd4,0x00,0x00,0x00,0x1f,0xff = nc 0(1), 4095(%r1) 0xd4,0x00,0x00,0x00,0xff,0xff = nc 0(1), 4095(%r15) 0xd4,0x00,0x10,0x00,0x00,0x00 = nc 0(1, %r1), 0 0xd4,0x00,0xf0,0x00,0x00,0x00 = nc 0(1, %r15), 0 0xd4,0x00,0x1f,0xff,0x00,0x00 = nc 4095(1, %r1), 0 0xd4,0x00,0xff,0xff,0x00,0x00 = nc 4095(1, %r15), 0 0xd4,0xff,0x10,0x00,0x00,0x00 = nc 0(256, %r1), 0 0xd4,0xff,0xf0,0x00,0x00,0x00 = nc 0(256, %r15), 0 0xe3,0x00,0x00,0x00,0x80,0x80 = ng %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x80 = ng %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x80 = ng %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x80 = ng %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x80 = ng %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x80 = ng %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x80 = ng %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x80 = ng %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x80 = ng %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x80 = ng %r15, 0 0xb9,0x80,0x00,0x00 = ngr %r0, %r0 0xb9,0x80,0x00,0x0f = ngr %r0, %r15 0xb9,0x80,0x00,0xf0 = ngr %r15, %r0 0xb9,0x80,0x00,0x78 = ngr %r7, %r8 0x94,0x00,0x00,0x00 = ni 0, 0 0x94,0x00,0x0f,0xff = ni 4095, 0 0x94,0xff,0x00,0x00 = ni 0, 255 0x94,0x2a,0x10,0x00 = ni 0(%r1), 42 0x94,0x2a,0xf0,0x00 = ni 0(%r15), 42 0x94,0x2a,0x1f,0xff = ni 4095(%r1), 42 0x94,0x2a,0xff,0xff = ni 4095(%r15), 42 0xc0,0x0a,0x00,0x00,0x00,0x00 = nihf %r0, 0 0xc0,0x0a,0xff,0xff,0xff,0xff = nihf %r0, 4294967295 0xc0,0xfa,0x00,0x00,0x00,0x00 = nihf %r15, 0 0xa5,0x04,0x00,0x00 = nihh %r0, 0 0xa5,0x04,0x80,0x00 = nihh %r0, 32768 0xa5,0x04,0xff,0xff = nihh %r0, 65535 0xa5,0xf4,0x00,0x00 = nihh %r15, 0 0xa5,0x05,0x00,0x00 = nihl %r0, 0 0xa5,0x05,0x80,0x00 = nihl %r0, 32768 0xa5,0x05,0xff,0xff = nihl %r0, 65535 0xa5,0xf5,0x00,0x00 = nihl %r15, 0 0xc0,0x0b,0x00,0x00,0x00,0x00 = nilf %r0, 0 0xc0,0x0b,0xff,0xff,0xff,0xff = nilf %r0, 4294967295 0xc0,0xfb,0x00,0x00,0x00,0x00 = nilf %r15, 0 0xa5,0x06,0x00,0x00 = nilh %r0, 0 0xa5,0x06,0x80,0x00 = nilh %r0, 32768 0xa5,0x06,0xff,0xff = nilh %r0, 65535 0xa5,0xf6,0x00,0x00 = nilh %r15, 0 0xa5,0x07,0x00,0x00 = nill %r0, 0 0xa5,0x07,0x80,0x00 = nill %r0, 32768 0xa5,0x07,0xff,0xff = nill %r0, 65535 0xa5,0xf7,0x00,0x00 = nill %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x54 = niy -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x54 = niy -1, 0 0xeb,0x00,0x00,0x00,0x00,0x54 = niy 0, 0 0xeb,0x00,0x00,0x01,0x00,0x54 = niy 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x54 = niy 524287, 0 0xeb,0xff,0x00,0x00,0x00,0x54 = niy 0, 255 0xeb,0x2a,0x10,0x00,0x00,0x54 = niy 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x54 = niy 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x54 = niy 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x54 = niy 524287(%r15), 42 0x14,0x00 = nr %r0, %r0 0x14,0x0f = nr %r0, %r15 0x14,0xf0 = nr %r15, %r0 0x14,0x78 = nr %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x54 = ny %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x54 = ny %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x54 = ny %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x54 = ny %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x54 = ny %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x54 = ny %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x54 = ny %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x54 = ny %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x54 = ny %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x54 = ny %r15, 0 0x56,0x00,0x00,0x00 = o %r0, 0 0x56,0x00,0x0f,0xff = o %r0, 4095 0x56,0x00,0x10,0x00 = o %r0, 0(%r1) 0x56,0x00,0xf0,0x00 = o %r0, 0(%r15) 0x56,0x01,0xff,0xff = o %r0, 4095(%r1, %r15) 0x56,0x0f,0x1f,0xff = o %r0, 4095(%r15, %r1) 0x56,0xf0,0x00,0x00 = o %r15, 0 0xd6,0x00,0x00,0x00,0x00,0x00 = oc 0(1), 0 0xd6,0x00,0x00,0x00,0x10,0x00 = oc 0(1), 0(%r1) 0xd6,0x00,0x00,0x00,0xf0,0x00 = oc 0(1), 0(%r15) 0xd6,0x00,0x00,0x00,0x0f,0xff = oc 0(1), 4095 0xd6,0x00,0x00,0x00,0x1f,0xff = oc 0(1), 4095(%r1) 0xd6,0x00,0x00,0x00,0xff,0xff = oc 0(1), 4095(%r15) 0xd6,0x00,0x10,0x00,0x00,0x00 = oc 0(1, %r1), 0 0xd6,0x00,0xf0,0x00,0x00,0x00 = oc 0(1, %r15), 0 0xd6,0x00,0x1f,0xff,0x00,0x00 = oc 4095(1, %r1), 0 0xd6,0x00,0xff,0xff,0x00,0x00 = oc 4095(1, %r15), 0 0xd6,0xff,0x10,0x00,0x00,0x00 = oc 0(256, %r1), 0 0xd6,0xff,0xf0,0x00,0x00,0x00 = oc 0(256, %r15), 0 0xe3,0x00,0x00,0x00,0x80,0x81 = og %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x81 = og %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x81 = og %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x81 = og %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x81 = og %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x81 = og %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x81 = og %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x81 = og %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x81 = og %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x81 = og %r15, 0 0xb9,0x81,0x00,0x00 = ogr %r0, %r0 0xb9,0x81,0x00,0x0f = ogr %r0, %r15 0xb9,0x81,0x00,0xf0 = ogr %r15, %r0 0xb9,0x81,0x00,0x78 = ogr %r7, %r8 0x96,0x00,0x00,0x00 = oi 0, 0 0x96,0x00,0x0f,0xff = oi 4095, 0 0x96,0xff,0x00,0x00 = oi 0, 255 0x96,0x2a,0x10,0x00 = oi 0(%r1), 42 0x96,0x2a,0xf0,0x00 = oi 0(%r15), 42 0x96,0x2a,0x1f,0xff = oi 4095(%r1), 42 0x96,0x2a,0xff,0xff = oi 4095(%r15), 42 0xc0,0x0c,0x00,0x00,0x00,0x00 = oihf %r0, 0 0xc0,0x0c,0xff,0xff,0xff,0xff = oihf %r0, 4294967295 0xc0,0xfc,0x00,0x00,0x00,0x00 = oihf %r15, 0 0xa5,0x08,0x00,0x00 = oihh %r0, 0 0xa5,0x08,0x80,0x00 = oihh %r0, 32768 0xa5,0x08,0xff,0xff = oihh %r0, 65535 0xa5,0xf8,0x00,0x00 = oihh %r15, 0 0xa5,0x09,0x00,0x00 = oihl %r0, 0 0xa5,0x09,0x80,0x00 = oihl %r0, 32768 0xa5,0x09,0xff,0xff = oihl %r0, 65535 0xa5,0xf9,0x00,0x00 = oihl %r15, 0 0xc0,0x0d,0x00,0x00,0x00,0x00 = oilf %r0, 0 0xc0,0x0d,0xff,0xff,0xff,0xff = oilf %r0, 4294967295 0xc0,0xfd,0x00,0x00,0x00,0x00 = oilf %r15, 0 0xa5,0x0a,0x00,0x00 = oilh %r0, 0 0xa5,0x0a,0x80,0x00 = oilh %r0, 32768 0xa5,0x0a,0xff,0xff = oilh %r0, 65535 0xa5,0xfa,0x00,0x00 = oilh %r15, 0 0xa5,0x0b,0x00,0x00 = oill %r0, 0 0xa5,0x0b,0x80,0x00 = oill %r0, 32768 0xa5,0x0b,0xff,0xff = oill %r0, 65535 0xa5,0xfb,0x00,0x00 = oill %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x56 = oiy -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x56 = oiy -1, 0 0xeb,0x00,0x00,0x00,0x00,0x56 = oiy 0, 0 0xeb,0x00,0x00,0x01,0x00,0x56 = oiy 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x56 = oiy 524287, 0 0xeb,0xff,0x00,0x00,0x00,0x56 = oiy 0, 255 0xeb,0x2a,0x10,0x00,0x00,0x56 = oiy 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x56 = oiy 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x56 = oiy 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x56 = oiy 524287(%r15), 42 0x16,0x00 = or %r0, %r0 0x16,0x0f = or %r0, %r15 0x16,0xf0 = or %r15, %r0 0x16,0x78 = or %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x56 = oy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x56 = oy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x56 = oy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x56 = oy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x56 = oy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x56 = oy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x56 = oy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x56 = oy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x56 = oy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x56 = oy %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x36 = pfd 0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x36 = pfd 0, -1 0xe3,0x00,0x00,0x00,0x00,0x36 = pfd 0, 0 0xe3,0x00,0x00,0x01,0x00,0x36 = pfd 0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x36 = pfd 0, 524287 0xe3,0x00,0x10,0x00,0x00,0x36 = pfd 0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x36 = pfd 0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x36 = pfd 0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x36 = pfd 0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x36 = pfd 15, 0 0xec,0x00,0x00,0x00,0x00,0x55 = risbg %r0, %r0, 0, 0, 0 0xec,0x00,0x00,0x00,0x3f,0x55 = risbg %r0, %r0, 0, 0, 63 0xec,0x00,0x00,0xff,0x00,0x55 = risbg %r0, %r0, 0, 255, 0 0xec,0x00,0xff,0x00,0x00,0x55 = risbg %r0, %r0, 255, 0, 0 0xec,0x0f,0x00,0x00,0x00,0x55 = risbg %r0, %r15, 0, 0, 0 0xec,0xf0,0x00,0x00,0x00,0x55 = risbg %r15, %r0, 0, 0, 0 0xec,0x45,0x06,0x07,0x08,0x55 = risbg %r4, %r5, 6, 7, 8 0xec,0x00,0x00,0x00,0x00,0x54 = rnsbg %r0, %r0, 0, 0, 0 0xec,0x00,0x00,0x00,0x3f,0x54 = rnsbg %r0, %r0, 0, 0, 63 0xec,0x00,0x00,0xff,0x00,0x54 = rnsbg %r0, %r0, 0, 255, 0 0xec,0x00,0xff,0x00,0x00,0x54 = rnsbg %r0, %r0, 255, 0, 0 0xec,0x0f,0x00,0x00,0x00,0x54 = rnsbg %r0, %r15, 0, 0, 0 0xec,0xf0,0x00,0x00,0x00,0x54 = rnsbg %r15, %r0, 0, 0, 0 0xec,0x45,0x06,0x07,0x08,0x54 = rnsbg %r4, %r5, 6, 7, 8 0xec,0x00,0x00,0x00,0x00,0x56 = rosbg %r0, %r0, 0, 0, 0 0xec,0x00,0x00,0x00,0x3f,0x56 = rosbg %r0, %r0, 0, 0, 63 0xec,0x00,0x00,0xff,0x00,0x56 = rosbg %r0, %r0, 0, 255, 0 0xec,0x00,0xff,0x00,0x00,0x56 = rosbg %r0, %r0, 255, 0, 0 0xec,0x0f,0x00,0x00,0x00,0x56 = rosbg %r0, %r15, 0, 0, 0 0xec,0xf0,0x00,0x00,0x00,0x56 = rosbg %r15, %r0, 0, 0, 0 0xec,0x45,0x06,0x07,0x08,0x56 = rosbg %r4, %r5, 6, 7, 8 0xec,0x00,0x00,0x00,0x00,0x57 = rxsbg %r0, %r0, 0, 0, 0 0xec,0x00,0x00,0x00,0x3f,0x57 = rxsbg %r0, %r0, 0, 0, 63 0xec,0x00,0x00,0xff,0x00,0x57 = rxsbg %r0, %r0, 0, 255, 0 0xec,0x00,0xff,0x00,0x00,0x57 = rxsbg %r0, %r0, 255, 0, 0 0xec,0x0f,0x00,0x00,0x00,0x57 = rxsbg %r0, %r15, 0, 0, 0 0xec,0xf0,0x00,0x00,0x00,0x57 = rxsbg %r15, %r0, 0, 0, 0 0xec,0x45,0x06,0x07,0x08,0x57 = rxsbg %r4, %r5, 6, 7, 8 0xeb,0x00,0x00,0x00,0x00,0x1d = rll %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0x1d = rll %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0x1d = rll %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x1d = rll %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x1d = rll %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x1d = rll %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0x1d = rll %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x1d = rll %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x1d = rll %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x1d = rll %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x1d = rll %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x1d = rll %r0, %r0, 524287(%r15) 0xeb,0x00,0x00,0x00,0x00,0x1c = rllg %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0x1c = rllg %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0x1c = rllg %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x1c = rllg %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x1c = rllg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x1c = rllg %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0x1c = rllg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x1c = rllg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x1c = rllg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x1c = rllg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x1c = rllg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x1c = rllg %r0, %r0, 524287(%r15) 0x5b,0x00,0x00,0x00 = s %r0, 0 0x5b,0x00,0x0f,0xff = s %r0, 4095 0x5b,0x00,0x10,0x00 = s %r0, 0(%r1) 0x5b,0x00,0xf0,0x00 = s %r0, 0(%r15) 0x5b,0x01,0xff,0xff = s %r0, 4095(%r1, %r15) 0x5b,0x0f,0x1f,0xff = s %r0, 4095(%r15, %r1) 0x5b,0xf0,0x00,0x00 = s %r15, 0 0xed,0x00,0x00,0x00,0x00,0x1b = sdb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x1b = sdb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x1b = sdb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x1b = sdb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x1b = sdb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x1b = sdb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x1b = sdb %f15, 0 0xb3,0x1b,0x00,0x00 = sdbr %f0, %f0 0xb3,0x1b,0x00,0x0f = sdbr %f0, %f15 0xb3,0x1b,0x00,0x78 = sdbr %f7, %f8 0xb3,0x1b,0x00,0xf0 = sdbr %f15, %f0 0xed,0x00,0x00,0x00,0x00,0x0b = seb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x0b = seb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x0b = seb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x0b = seb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x0b = seb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x0b = seb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x0b = seb %f15, 0 0xb3,0x0b,0x00,0x00 = sebr %f0, %f0 0xb3,0x0b,0x00,0x0f = sebr %f0, %f15 0xb3,0x0b,0x00,0x78 = sebr %f7, %f8 0xb3,0x0b,0x00,0xf0 = sebr %f15, %f0 0xe3,0x00,0x00,0x00,0x80,0x09 = sg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x09 = sg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x09 = sg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x09 = sg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x09 = sg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x09 = sg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x09 = sg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x09 = sg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x09 = sg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x09 = sg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x19 = sgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x19 = sgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x19 = sgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x19 = sgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x19 = sgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x19 = sgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x19 = sgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x19 = sgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x19 = sgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x19 = sgf %r15, 0 0xb9,0x19,0x00,0x00 = sgfr %r0, %r0 0xb9,0x19,0x00,0x0f = sgfr %r0, %r15 0xb9,0x19,0x00,0xf0 = sgfr %r15, %r0 0xb9,0x19,0x00,0x78 = sgfr %r7, %r8 0xb9,0x09,0x00,0x00 = sgr %r0, %r0 0xb9,0x09,0x00,0x0f = sgr %r0, %r15 0xb9,0x09,0x00,0xf0 = sgr %r15, %r0 0xb9,0x09,0x00,0x78 = sgr %r7, %r8 0x4b,0x00,0x00,0x00 = sh %r0, 0 0x4b,0x00,0x0f,0xff = sh %r0, 4095 0x4b,0x00,0x10,0x00 = sh %r0, 0(%r1) 0x4b,0x00,0xf0,0x00 = sh %r0, 0(%r15) 0x4b,0x01,0xff,0xff = sh %r0, 4095(%r1, %r15) 0x4b,0x0f,0x1f,0xff = sh %r0, 4095(%r15, %r1) 0x4b,0xf0,0x00,0x00 = sh %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x7b = shy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x7b = shy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x7b = shy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x7b = shy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x7b = shy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x7b = shy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x7b = shy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x7b = shy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x7b = shy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x7b = shy %r15, 0 0x5f,0x00,0x00,0x00 = sl %r0, 0 0x5f,0x00,0x0f,0xff = sl %r0, 4095 0x5f,0x00,0x10,0x00 = sl %r0, 0(%r1) 0x5f,0x00,0xf0,0x00 = sl %r0, 0(%r15) 0x5f,0x01,0xff,0xff = sl %r0, 4095(%r1, %r15) 0x5f,0x0f,0x1f,0xff = sl %r0, 4095(%r15, %r1) 0x5f,0xf0,0x00,0x00 = sl %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x99 = slb %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x99 = slb %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x99 = slb %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x99 = slb %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x99 = slb %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x99 = slb %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x99 = slb %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x99 = slb %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x99 = slb %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x99 = slb %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x89 = slbg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x89 = slbg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x89 = slbg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x89 = slbg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x89 = slbg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x89 = slbg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x89 = slbg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x89 = slbg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x89 = slbg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x89 = slbg %r15, 0 0xb9,0x89,0x00,0x00 = slbgr %r0, %r0 0xb9,0x89,0x00,0x0f = slbgr %r0, %r15 0xb9,0x89,0x00,0xf0 = slbgr %r15, %r0 0xb9,0x89,0x00,0x78 = slbgr %r7, %r8 0xb9,0x99,0x00,0x00 = slbr %r0, %r0 0xb9,0x99,0x00,0x0f = slbr %r0, %r15 0xb9,0x99,0x00,0xf0 = slbr %r15, %r0 0xb9,0x99,0x00,0x78 = slbr %r7, %r8 0xc2,0x05,0x00,0x00,0x00,0x00 = slfi %r0, 0 0xc2,0x05,0xff,0xff,0xff,0xff = slfi %r0, 4294967295 0xc2,0xf5,0x00,0x00,0x00,0x00 = slfi %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x0b = slg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x0b = slg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x0b = slg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x0b = slg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x0b = slg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x0b = slg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x0b = slg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x0b = slg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x0b = slg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x0b = slg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x1b = slgf %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x1b = slgf %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x1b = slgf %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x1b = slgf %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x1b = slgf %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x1b = slgf %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x1b = slgf %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x1b = slgf %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x1b = slgf %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x1b = slgf %r15, 0 0xc2,0x04,0x00,0x00,0x00,0x00 = slgfi %r0, 0 0xc2,0x04,0xff,0xff,0xff,0xff = slgfi %r0, 4294967295 0xc2,0xf4,0x00,0x00,0x00,0x00 = slgfi %r15, 0 0xb9,0x1b,0x00,0x00 = slgfr %r0, %r0 0xb9,0x1b,0x00,0x0f = slgfr %r0, %r15 0xb9,0x1b,0x00,0xf0 = slgfr %r15, %r0 0xb9,0x1b,0x00,0x78 = slgfr %r7, %r8 0xb9,0x0b,0x00,0x00 = slgr %r0, %r0 0xb9,0x0b,0x00,0x0f = slgr %r0, %r15 0xb9,0x0b,0x00,0xf0 = slgr %r15, %r0 0xb9,0x0b,0x00,0x78 = slgr %r7, %r8 0x89,0x00,0x00,0x00 = sll %r0, 0 0x89,0x70,0x00,0x00 = sll %r7, 0 0x89,0xf0,0x00,0x00 = sll %r15, 0 0x89,0x00,0x0f,0xff = sll %r0, 4095 0x89,0x00,0x10,0x00 = sll %r0, 0(%r1) 0x89,0x00,0xf0,0x00 = sll %r0, 0(%r15) 0x89,0x00,0x1f,0xff = sll %r0, 4095(%r1) 0x89,0x00,0xff,0xff = sll %r0, 4095(%r15) 0xeb,0x00,0x00,0x00,0x00,0x0d = sllg %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0x0d = sllg %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0x0d = sllg %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x0d = sllg %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x0d = sllg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x0d = sllg %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0x0d = sllg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x0d = sllg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x0d = sllg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x0d = sllg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x0d = sllg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x0d = sllg %r0, %r0, 524287(%r15) 0x1f,0x00 = slr %r0, %r0 0x1f,0x0f = slr %r0, %r15 0x1f,0xf0 = slr %r15, %r0 0x1f,0x78 = slr %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x5f = sly %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x5f = sly %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x5f = sly %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x5f = sly %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x5f = sly %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x5f = sly %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x5f = sly %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x5f = sly %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x5f = sly %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x5f = sly %r15, 0 0xed,0x00,0x00,0x00,0x00,0x15 = sqdb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x15 = sqdb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x15 = sqdb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x15 = sqdb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x15 = sqdb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x15 = sqdb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x15 = sqdb %f15, 0 0xb3,0x15,0x00,0x00 = sqdbr %f0, %f0 0xb3,0x15,0x00,0x0f = sqdbr %f0, %f15 0xb3,0x15,0x00,0x78 = sqdbr %f7, %f8 0xb3,0x15,0x00,0xf0 = sqdbr %f15, %f0 0xed,0x00,0x00,0x00,0x00,0x14 = sqeb %f0, 0 0xed,0x00,0x0f,0xff,0x00,0x14 = sqeb %f0, 4095 0xed,0x00,0x10,0x00,0x00,0x14 = sqeb %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x14 = sqeb %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x00,0x14 = sqeb %f0, 4095(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x00,0x14 = sqeb %f0, 4095(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x14 = sqeb %f15, 0 0xb3,0x14,0x00,0x00 = sqebr %f0, %f0 0xb3,0x14,0x00,0x0f = sqebr %f0, %f15 0xb3,0x14,0x00,0x78 = sqebr %f7, %f8 0xb3,0x14,0x00,0xf0 = sqebr %f15, %f0 0xb3,0x16,0x00,0x00 = sqxbr %f0, %f0 0xb3,0x16,0x00,0x0d = sqxbr %f0, %f13 0xb3,0x16,0x00,0x88 = sqxbr %f8, %f8 0xb3,0x16,0x00,0xd0 = sqxbr %f13, %f0 0x1b,0x00 = sr %r0, %r0 0x1b,0x0f = sr %r0, %r15 0x1b,0xf0 = sr %r15, %r0 0x1b,0x78 = sr %r7, %r8 0x8a,0x00,0x00,0x00 = sra %r0, 0 0x8a,0x70,0x00,0x00 = sra %r7, 0 0x8a,0xf0,0x00,0x00 = sra %r15, 0 0x8a,0x00,0x0f,0xff = sra %r0, 4095 0x8a,0x00,0x10,0x00 = sra %r0, 0(%r1) 0x8a,0x00,0xf0,0x00 = sra %r0, 0(%r15) 0x8a,0x00,0x1f,0xff = sra %r0, 4095(%r1) 0x8a,0x00,0xff,0xff = sra %r0, 4095(%r15) 0xeb,0x00,0x00,0x00,0x00,0x0a = srag %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0x0a = srag %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0x0a = srag %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x0a = srag %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x0a = srag %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x0a = srag %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0x0a = srag %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x0a = srag %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x0a = srag %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x0a = srag %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x0a = srag %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x0a = srag %r0, %r0, 524287(%r15) 0x88,0x00,0x00,0x00 = srl %r0, 0 0x88,0x70,0x00,0x00 = srl %r7, 0 0x88,0xf0,0x00,0x00 = srl %r15, 0 0x88,0x00,0x0f,0xff = srl %r0, 4095 0x88,0x00,0x10,0x00 = srl %r0, 0(%r1) 0x88,0x00,0xf0,0x00 = srl %r0, 0(%r15) 0x88,0x00,0x1f,0xff = srl %r0, 4095(%r1) 0x88,0x00,0xff,0xff = srl %r0, 4095(%r15) 0xeb,0x00,0x00,0x00,0x00,0x0c = srlg %r0, %r0, 0 0xeb,0xf1,0x00,0x00,0x00,0x0c = srlg %r15, %r1, 0 0xeb,0x1f,0x00,0x00,0x00,0x0c = srlg %r1, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x0c = srlg %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x0c = srlg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x0c = srlg %r0, %r0, -1 0xeb,0x00,0x00,0x01,0x00,0x0c = srlg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x0c = srlg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x0c = srlg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x0c = srlg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x0c = srlg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x0c = srlg %r0, %r0, 524287(%r15) 0xb2,0x5e,0x00,0x00 = srst %r0, %r0 0xb2,0x5e,0x00,0x0f = srst %r0, %r15 0xb2,0x5e,0x00,0xf0 = srst %r15, %r0 0xb2,0x5e,0x00,0x78 = srst %r7, %r8 0x50,0x00,0x00,0x00 = st %r0, 0 0x50,0x00,0x0f,0xff = st %r0, 4095 0x50,0x00,0x10,0x00 = st %r0, 0(%r1) 0x50,0x00,0xf0,0x00 = st %r0, 0(%r15) 0x50,0x01,0xff,0xff = st %r0, 4095(%r1, %r15) 0x50,0x0f,0x1f,0xff = st %r0, 4095(%r15, %r1) 0x50,0xf0,0x00,0x00 = st %r15, 0 0x42,0x00,0x00,0x00 = stc %r0, 0 0x42,0x00,0x0f,0xff = stc %r0, 4095 0x42,0x00,0x10,0x00 = stc %r0, 0(%r1) 0x42,0x00,0xf0,0x00 = stc %r0, 0(%r15) 0x42,0x01,0xff,0xff = stc %r0, 4095(%r1, %r15) 0x42,0x0f,0x1f,0xff = stc %r0, 4095(%r15, %r1) 0x42,0xf0,0x00,0x00 = stc %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x72 = stcy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x72 = stcy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x72 = stcy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x72 = stcy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x72 = stcy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x72 = stcy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x72 = stcy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x72 = stcy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x72 = stcy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x72 = stcy %r15, 0 0x60,0x00,0x00,0x00 = std %f0, 0 0x60,0x00,0x0f,0xff = std %f0, 4095 0x60,0x00,0x10,0x00 = std %f0, 0(%r1) 0x60,0x00,0xf0,0x00 = std %f0, 0(%r15) 0x60,0x01,0xff,0xff = std %f0, 4095(%r1, %r15) 0x60,0x0f,0x1f,0xff = std %f0, 4095(%r15, %r1) 0x60,0xf0,0x00,0x00 = std %f15, 0 0xed,0x00,0x00,0x00,0x80,0x67 = stdy %f0, -524288 0xed,0x00,0x0f,0xff,0xff,0x67 = stdy %f0, -1 0xed,0x00,0x00,0x00,0x00,0x67 = stdy %f0, 0 0xed,0x00,0x00,0x01,0x00,0x67 = stdy %f0, 1 0xed,0x00,0x0f,0xff,0x7f,0x67 = stdy %f0, 524287 0xed,0x00,0x10,0x00,0x00,0x67 = stdy %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x67 = stdy %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x7f,0x67 = stdy %f0, 524287(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x7f,0x67 = stdy %f0, 524287(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x67 = stdy %f15, 0 0x70,0x00,0x00,0x00 = ste %f0, 0 0x70,0x00,0x0f,0xff = ste %f0, 4095 0x70,0x00,0x10,0x00 = ste %f0, 0(%r1) 0x70,0x00,0xf0,0x00 = ste %f0, 0(%r15) 0x70,0x01,0xff,0xff = ste %f0, 4095(%r1, %r15) 0x70,0x0f,0x1f,0xff = ste %f0, 4095(%r15, %r1) 0x70,0xf0,0x00,0x00 = ste %f15, 0 0xed,0x00,0x00,0x00,0x80,0x66 = stey %f0, -524288 0xed,0x00,0x0f,0xff,0xff,0x66 = stey %f0, -1 0xed,0x00,0x00,0x00,0x00,0x66 = stey %f0, 0 0xed,0x00,0x00,0x01,0x00,0x66 = stey %f0, 1 0xed,0x00,0x0f,0xff,0x7f,0x66 = stey %f0, 524287 0xed,0x00,0x10,0x00,0x00,0x66 = stey %f0, 0(%r1) 0xed,0x00,0xf0,0x00,0x00,0x66 = stey %f0, 0(%r15) 0xed,0x01,0xff,0xff,0x7f,0x66 = stey %f0, 524287(%r1, %r15) 0xed,0x0f,0x1f,0xff,0x7f,0x66 = stey %f0, 524287(%r15, %r1) 0xed,0xf0,0x00,0x00,0x00,0x66 = stey %f15, 0 0xe3,0x00,0x00,0x00,0x80,0x24 = stg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x24 = stg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x24 = stg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x24 = stg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x24 = stg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x24 = stg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x24 = stg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x24 = stg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x24 = stg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x24 = stg %r15, 0 0x40,0x00,0x00,0x00 = sth %r0, 0 0x40,0x00,0x0f,0xff = sth %r0, 4095 0x40,0x00,0x10,0x00 = sth %r0, 0(%r1) 0x40,0x00,0xf0,0x00 = sth %r0, 0(%r15) 0x40,0x01,0xff,0xff = sth %r0, 4095(%r1, %r15) 0x40,0x0f,0x1f,0xff = sth %r0, 4095(%r15, %r1) 0x40,0xf0,0x00,0x00 = sth %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x70 = sthy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x70 = sthy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x70 = sthy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x70 = sthy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x70 = sthy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x70 = sthy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x70 = sthy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x70 = sthy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x70 = sthy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x70 = sthy %r15, 0 0xeb,0x00,0x00,0x00,0x00,0x24 = stmg %r0, %r0, 0 0xeb,0x0f,0x00,0x00,0x00,0x24 = stmg %r0, %r15, 0 0xeb,0xef,0x00,0x00,0x00,0x24 = stmg %r14, %r15, 0 0xeb,0xff,0x00,0x00,0x00,0x24 = stmg %r15, %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x24 = stmg %r0, %r0, -524288 0xeb,0x00,0x0f,0xff,0xff,0x24 = stmg %r0, %r0, -1 0xeb,0x00,0x00,0x00,0x00,0x24 = stmg %r0, %r0, 0 0xeb,0x00,0x00,0x01,0x00,0x24 = stmg %r0, %r0, 1 0xeb,0x00,0x0f,0xff,0x7f,0x24 = stmg %r0, %r0, 524287 0xeb,0x00,0x10,0x00,0x00,0x24 = stmg %r0, %r0, 0(%r1) 0xeb,0x00,0xf0,0x00,0x00,0x24 = stmg %r0, %r0, 0(%r15) 0xeb,0x00,0x1f,0xff,0x7f,0x24 = stmg %r0, %r0, 524287(%r1) 0xeb,0x00,0xff,0xff,0x7f,0x24 = stmg %r0, %r0, 524287(%r15) 0xe3,0x00,0x00,0x00,0x80,0x3e = strv %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x3e = strv %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x3e = strv %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x3e = strv %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x3e = strv %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x3e = strv %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x3e = strv %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x3e = strv %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x3e = strv %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x3e = strv %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x2f = strvg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x2f = strvg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x2f = strvg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x2f = strvg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x2f = strvg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x2f = strvg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x2f = strvg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x2f = strvg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x2f = strvg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x2f = strvg %r15, 0 0xe3,0x00,0x00,0x00,0x80,0x50 = sty %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x50 = sty %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x50 = sty %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x50 = sty %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x50 = sty %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x50 = sty %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x50 = sty %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x50 = sty %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x50 = sty %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x50 = sty %r15, 0 0xb3,0x4b,0x00,0x00 = sxbr %f0, %f0 0xb3,0x4b,0x00,0x0d = sxbr %f0, %f13 0xb3,0x4b,0x00,0x88 = sxbr %f8, %f8 0xb3,0x4b,0x00,0xd0 = sxbr %f13, %f0 0xe3,0x00,0x00,0x00,0x80,0x5b = sy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x5b = sy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x5b = sy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x5b = sy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x5b = sy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x5b = sy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x5b = sy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x5b = sy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x5b = sy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x5b = sy %r15, 0 0x91,0x00,0x00,0x00 = tm 0, 0 0x91,0x00,0x0f,0xff = tm 4095, 0 0x91,0xff,0x00,0x00 = tm 0, 255 0x91,0x2a,0x10,0x00 = tm 0(%r1), 42 0x91,0x2a,0xf0,0x00 = tm 0(%r15), 42 0x91,0x2a,0x1f,0xff = tm 4095(%r1), 42 0x91,0x2a,0xff,0xff = tm 4095(%r15), 42 0xa7,0x02,0x00,0x00 = tmhh %r0, 0 0xa7,0x02,0x80,0x00 = tmhh %r0, 32768 0xa7,0x02,0xff,0xff = tmhh %r0, 65535 0xa7,0xf2,0x00,0x00 = tmhh %r15, 0 0xa7,0x03,0x00,0x00 = tmhl %r0, 0 0xa7,0x03,0x80,0x00 = tmhl %r0, 32768 0xa7,0x03,0xff,0xff = tmhl %r0, 65535 0xa7,0xf3,0x00,0x00 = tmhl %r15, 0 0xa7,0x00,0x00,0x00 = tmlh %r0, 0 0xa7,0x00,0x80,0x00 = tmlh %r0, 32768 0xa7,0x00,0xff,0xff = tmlh %r0, 65535 0xa7,0xf0,0x00,0x00 = tmlh %r15, 0 0xa7,0x01,0x00,0x00 = tmll %r0, 0 0xa7,0x01,0x80,0x00 = tmll %r0, 32768 0xa7,0x01,0xff,0xff = tmll %r0, 65535 0xa7,0xf1,0x00,0x00 = tmll %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x51 = tmy -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x51 = tmy -1, 0 0xeb,0x00,0x00,0x00,0x00,0x51 = tmy 0, 0 0xeb,0x00,0x00,0x01,0x00,0x51 = tmy 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x51 = tmy 524287, 0 0xeb,0xff,0x00,0x00,0x00,0x51 = tmy 0, 255 0xeb,0x2a,0x10,0x00,0x00,0x51 = tmy 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x51 = tmy 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x51 = tmy 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x51 = tmy 524287(%r15), 42 0x57,0x00,0x00,0x00 = x %r0, 0 0x57,0x00,0x0f,0xff = x %r0, 4095 0x57,0x00,0x10,0x00 = x %r0, 0(%r1) 0x57,0x00,0xf0,0x00 = x %r0, 0(%r15) 0x57,0x01,0xff,0xff = x %r0, 4095(%r1, %r15) 0x57,0x0f,0x1f,0xff = x %r0, 4095(%r15, %r1) 0x57,0xf0,0x00,0x00 = x %r15, 0 0xd7,0x00,0x00,0x00,0x00,0x00 = xc 0(1), 0 0xd7,0x00,0x00,0x00,0x10,0x00 = xc 0(1), 0(%r1) 0xd7,0x00,0x00,0x00,0xf0,0x00 = xc 0(1), 0(%r15) 0xd7,0x00,0x00,0x00,0x0f,0xff = xc 0(1), 4095 0xd7,0x00,0x00,0x00,0x1f,0xff = xc 0(1), 4095(%r1) 0xd7,0x00,0x00,0x00,0xff,0xff = xc 0(1), 4095(%r15) 0xd7,0x00,0x10,0x00,0x00,0x00 = xc 0(1, %r1), 0 0xd7,0x00,0xf0,0x00,0x00,0x00 = xc 0(1, %r15), 0 0xd7,0x00,0x1f,0xff,0x00,0x00 = xc 4095(1, %r1), 0 0xd7,0x00,0xff,0xff,0x00,0x00 = xc 4095(1, %r15), 0 0xd7,0xff,0x10,0x00,0x00,0x00 = xc 0(256, %r1), 0 0xd7,0xff,0xf0,0x00,0x00,0x00 = xc 0(256, %r15), 0 0xe3,0x00,0x00,0x00,0x80,0x82 = xg %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x82 = xg %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x82 = xg %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x82 = xg %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x82 = xg %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x82 = xg %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x82 = xg %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x82 = xg %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x82 = xg %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x82 = xg %r15, 0 0xb9,0x82,0x00,0x00 = xgr %r0, %r0 0xb9,0x82,0x00,0x0f = xgr %r0, %r15 0xb9,0x82,0x00,0xf0 = xgr %r15, %r0 0xb9,0x82,0x00,0x78 = xgr %r7, %r8 0x97,0x00,0x00,0x00 = xi 0, 0 0x97,0x00,0x0f,0xff = xi 4095, 0 0x97,0xff,0x00,0x00 = xi 0, 255 0x97,0x2a,0x10,0x00 = xi 0(%r1), 42 0x97,0x2a,0xf0,0x00 = xi 0(%r15), 42 0x97,0x2a,0x1f,0xff = xi 4095(%r1), 42 0x97,0x2a,0xff,0xff = xi 4095(%r15), 42 0xc0,0x06,0x00,0x00,0x00,0x00 = xihf %r0, 0 0xc0,0x06,0xff,0xff,0xff,0xff = xihf %r0, 4294967295 0xc0,0xf6,0x00,0x00,0x00,0x00 = xihf %r15, 0 0xc0,0x07,0x00,0x00,0x00,0x00 = xilf %r0, 0 0xc0,0x07,0xff,0xff,0xff,0xff = xilf %r0, 4294967295 0xc0,0xf7,0x00,0x00,0x00,0x00 = xilf %r15, 0 0xeb,0x00,0x00,0x00,0x80,0x57 = xiy -524288, 0 0xeb,0x00,0x0f,0xff,0xff,0x57 = xiy -1, 0 0xeb,0x00,0x00,0x00,0x00,0x57 = xiy 0, 0 0xeb,0x00,0x00,0x01,0x00,0x57 = xiy 1, 0 0xeb,0x00,0x0f,0xff,0x7f,0x57 = xiy 524287, 0 0xeb,0xff,0x00,0x00,0x00,0x57 = xiy 0, 255 0xeb,0x2a,0x10,0x00,0x00,0x57 = xiy 0(%r1), 42 0xeb,0x2a,0xf0,0x00,0x00,0x57 = xiy 0(%r15), 42 0xeb,0x2a,0x1f,0xff,0x7f,0x57 = xiy 524287(%r1), 42 0xeb,0x2a,0xff,0xff,0x7f,0x57 = xiy 524287(%r15), 42 0x17,0x00 = xr %r0, %r0 0x17,0x0f = xr %r0, %r15 0x17,0xf0 = xr %r15, %r0 0x17,0x78 = xr %r7, %r8 0xe3,0x00,0x00,0x00,0x80,0x57 = xy %r0, -524288 0xe3,0x00,0x0f,0xff,0xff,0x57 = xy %r0, -1 0xe3,0x00,0x00,0x00,0x00,0x57 = xy %r0, 0 0xe3,0x00,0x00,0x01,0x00,0x57 = xy %r0, 1 0xe3,0x00,0x0f,0xff,0x7f,0x57 = xy %r0, 524287 0xe3,0x00,0x10,0x00,0x00,0x57 = xy %r0, 0(%r1) 0xe3,0x00,0xf0,0x00,0x00,0x57 = xy %r0, 0(%r15) 0xe3,0x01,0xff,0xff,0x7f,0x57 = xy %r0, 524287(%r1, %r15) 0xe3,0x0f,0x1f,0xff,0x7f,0x57 = xy %r0, 524287(%r15, %r1) 0xe3,0xf0,0x00,0x00,0x00,0x57 = xy %r15, 0 capstone-sys-0.15.0/capstone/suite/MC/SystemZ/regs-good.s.cs000064400000000000000000000025010072674642500217250ustar 00000000000000# CS_ARCH_SYSZ, 0, None 0x18,0x01 = lr %r0, %r1 0x18,0x23 = lr %r2, %r3 0x18,0x45 = lr %r4, %r5 0x18,0x67 = lr %r6, %r7 0x18,0x89 = lr %r8, %r9 0x18,0xab = lr %r10, %r11 0x18,0xcd = lr %r12, %r13 0x18,0xef = lr %r14, %r15 0xb9,0x04,0x00,0x01 = lgr %r0, %r1 0xb9,0x04,0x00,0x23 = lgr %r2, %r3 0xb9,0x04,0x00,0x45 = lgr %r4, %r5 0xb9,0x04,0x00,0x67 = lgr %r6, %r7 0xb9,0x04,0x00,0x89 = lgr %r8, %r9 0xb9,0x04,0x00,0xab = lgr %r10, %r11 0xb9,0x04,0x00,0xcd = lgr %r12, %r13 0xb9,0x04,0x00,0xef = lgr %r14, %r15 0xb9,0x97,0x00,0x00 = dlr %r0, %r0 0xb9,0x97,0x00,0x20 = dlr %r2, %r0 0xb9,0x97,0x00,0x40 = dlr %r4, %r0 0xb9,0x97,0x00,0x60 = dlr %r6, %r0 0xb9,0x97,0x00,0x80 = dlr %r8, %r0 0xb9,0x97,0x00,0xa0 = dlr %r10, %r0 0xb9,0x97,0x00,0xc0 = dlr %r12, %r0 0xb9,0x97,0x00,0xe0 = dlr %r14, %r0 0x38,0x01 = ler %f0, %f1 0x38,0x23 = ler %f2, %f3 0x38,0x45 = ler %f4, %f5 0x38,0x67 = ler %f6, %f7 0x38,0x89 = ler %f8, %f9 0x38,0xab = ler %f10, %f11 0x38,0xcd = ler %f12, %f13 0x38,0xef = ler %f14, %f15 0x28,0x01 = ldr %f0, %f1 0x28,0x23 = ldr %f2, %f3 0x28,0x45 = ldr %f4, %f5 0x28,0x67 = ldr %f6, %f7 0x28,0x89 = ldr %f8, %f9 0x28,0xab = ldr %f10, %f11 0x28,0xcd = ldr %f12, %f13 0x28,0xef = ldr %f14, %f15 0xb3,0x65,0x00,0x01 = lxr %f0, %f1 0xb3,0x65,0x00,0x45 = lxr %f4, %f5 0xb3,0x65,0x00,0x89 = lxr %f8, %f9 0xb3,0x65,0x00,0xcd = lxr %f12, %f13 capstone-sys-0.15.0/capstone/suite/MC/X86/3DNow.s.cs000064400000000000000000000022310072674642500177400ustar 00000000000000# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0x0f,0x0f,0xca,0xbf = pavgusb %mm2, %mm1 0x0f,0x0f,0x5c,0x16,0x09,0xbf = pavgusb 9(%esi, %edx), %mm3 0x0f,0x0f,0xca,0x1d = pf2id %mm2, %mm1 0x0f,0x0f,0x5c,0x16,0x09,0x1d = pf2id 9(%esi, %edx), %mm3 0x0f,0x0f,0xca,0xae = pfacc %mm2, %mm1 0x0f,0x0f,0xca,0x9e = pfadd %mm2, %mm1 0x0f,0x0f,0xca,0xb0 = pfcmpeq %mm2, %mm1 0x0f,0x0f,0xca,0x90 = pfcmpge %mm2, %mm1 0x0f,0x0f,0xca,0xa0 = pfcmpgt %mm2, %mm1 0x0f,0x0f,0xca,0xa4 = pfmax %mm2, %mm1 0x0f,0x0f,0xca,0x94 = pfmin %mm2, %mm1 0x0f,0x0f,0xca,0xb4 = pfmul %mm2, %mm1 0x0f,0x0f,0xca,0x96 = pfrcp %mm2, %mm1 0x0f,0x0f,0xca,0xa6 = pfrcpit1 %mm2, %mm1 0x0f,0x0f,0xca,0xb6 = pfrcpit2 %mm2, %mm1 0x0f,0x0f,0xca,0xa7 = pfrsqit1 %mm2, %mm1 0x0f,0x0f,0xca,0x97 = pfrsqrt %mm2, %mm1 0x0f,0x0f,0xca,0x9a = pfsub %mm2, %mm1 0x0f,0x0f,0xca,0xaa = pfsubr %mm2, %mm1 0x0f,0x0f,0xca,0x0d = pi2fd %mm2, %mm1 0x0f,0x0f,0xca,0xb7 = pmulhrw %mm2, %mm1 0x0f,0x0e = femms 0x0f,0x0d,0x00 = prefetch (%eax) 0x0f,0x0f,0xca,0x1c = pf2iw %mm2, %mm1 0x0f,0x0f,0xca,0x0c = pi2fw %mm2, %mm1 0x0f,0x0f,0xca,0x8a = pfnacc %mm2, %mm1 0x0f,0x0f,0xca,0x8e = pfpnacc %mm2, %mm1 0x0f,0x0f,0xca,0xbb = pswapd %mm2, %mm1 capstone-sys-0.15.0/capstone/suite/MC/X86/address-size.s.cs000064400000000000000000000003030072674642500214010ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) 0xc6,0x06,0x00 = movb $0x0, (%rsi) 0x67,0xc6,0x06,0x00 = movb $0x0, (%esi) 0xc6,0x06,0x00 = movb $0x0, (%rsi) capstone-sys-0.15.0/capstone/suite/MC/X86/avx512-encodings.s.cs000064400000000000000000000015140072674642500220060ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x62,0xa3,0x55,0x48,0x38,0xcd,0x01 = vinserti32x4 $1, %xmm21, %zmm5, %zmm17 0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01 = vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17 0x62,0x33,0x7d,0x48,0x39,0xc9,0x01 = vextracti32x4 $1, %zmm9, %xmm17 0x62,0x33,0xfd,0x48,0x3b,0xc9,0x01 = vextracti64x4 $1, %zmm9, %ymm17 0x62,0x73,0xfd,0x48,0x3b,0x4f,0x10,0x01 = vextracti64x4 $1, %zmm9, 512(%rdi) 0x62,0xb1,0x35,0x40,0x72,0xe1,0x02 = vpsrad $2, %zmm17, %zmm25 0x62,0xf1,0x35,0x40,0x72,0x64,0xb7,0x08,0x02 = vpsrad $2, 512(%rdi, %rsi, 4), %zmm25 0x62,0x21,0x1d,0x48,0xe2,0xc9 = vpsrad %xmm17, %zmm12, %zmm25 0x62,0x61,0x1d,0x48,0xe2,0x4c,0xb7,0x20 = vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25 0x62,0xf2,0x7d,0xc9,0x58,0xc8 = vpbroadcastd %xmm0, %zmm1 {%k1} {z} 0x62,0xf1,0xfe,0x4b,0x6f,0xc8 = vmovdqu64 %zmm0, %zmm1 {%k3} capstone-sys-0.15.0/capstone/suite/MC/X86/intel-syntax-encoding.s.cs000064400000000000000000000017440072674642500232410ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, None 0x66,0x83,0xf0,0x0c = xor ax, 12 0x83,0xf0,0x0c = xor eax, 12 0x48,0x83,0xf0,0x0c = xor rax, 12 0x66,0x83,0xc8,0x0c = or ax, 12 0x83,0xc8,0x0c = or eax, 12 0x48,0x83,0xc8,0x0c = or rax, 12 0x66,0x83,0xf8,0x0c = cmp ax, 12 0x83,0xf8,0x0c = cmp eax, 12 0x48,0x83,0xf8,0x0c = cmp rax, 12 0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX 0x66,0x83,0xc0,0xf4 = add ax, -12 0x83,0xc0,0xf4 = add eax, -12 0x48,0x83,0xc0,0xf4 = add rax, -12 0x66,0x83,0xd0,0xf4 = adc ax, -12 0x83,0xd0,0xf4 = adc eax, -12 0x48,0x83,0xd0,0xf4 = adc rax, -12 0x66,0x83,0xd8,0xf4 = sbb ax, -12 0x83,0xd8,0xf4 = sbb eax, -12 0x48,0x83,0xd8,0xf4 = sbb rax, -12 0x66,0x83,0xf8,0xf4 = cmp ax, -12 0x83,0xf8,0xf4 = cmp eax, -12 0x48,0x83,0xf8,0xf4 = cmp rax, -12 0xf2,0x0f,0x10,0x2c,0x25,0xf8,0xff,0xff,0xff = movsd xmm5, qword ptr [0xfffffffffffffff8] 0xd1,0xe7 = shl EDI, 1 0x0f,0xc2,0xd1,0x01 = cmpltps XMM2, XMM1 0xc3 = ret 0xcb = retf 0xc2,0x08,0x00 = ret 8 0xca,0x08,0x00 = retf 8 capstone-sys-0.15.0/capstone/suite/MC/X86/x86-32-avx.s.cs000064400000000000000000001320610072674642500204560ustar 00000000000000# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0xc5,0xca,0x58,0xd4 = vaddss %xmm4, %xmm6, %xmm2 0xc5,0xca,0x59,0xd4 = vmulss %xmm4, %xmm6, %xmm2 0xc5,0xca,0x5c,0xd4 = vsubss %xmm4, %xmm6, %xmm2 0xc5,0xca,0x5e,0xd4 = vdivss %xmm4, %xmm6, %xmm2 0xc5,0xcb,0x58,0xd4 = vaddsd %xmm4, %xmm6, %xmm2 0xc5,0xcb,0x59,0xd4 = vmulsd %xmm4, %xmm6, %xmm2 0xc5,0xcb,0x5c,0xd4 = vsubsd %xmm4, %xmm6, %xmm2 0xc5,0xcb,0x5e,0xd4 = vdivsd %xmm4, %xmm6, %xmm2 0xc5,0xea,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xea,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xea,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xea,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xeb,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xeb,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xeb,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xeb,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xc8,0x58,0xd4 = vaddps %xmm4, %xmm6, %xmm2 0xc5,0xc8,0x5c,0xd4 = vsubps %xmm4, %xmm6, %xmm2 0xc5,0xc8,0x59,0xd4 = vmulps %xmm4, %xmm6, %xmm2 0xc5,0xc8,0x5e,0xd4 = vdivps %xmm4, %xmm6, %xmm2 0xc5,0xc9,0x58,0xd4 = vaddpd %xmm4, %xmm6, %xmm2 0xc5,0xc9,0x5c,0xd4 = vsubpd %xmm4, %xmm6, %xmm2 0xc5,0xc9,0x59,0xd4 = vmulpd %xmm4, %xmm6, %xmm2 0xc5,0xc9,0x5e,0xd4 = vdivpd %xmm4, %xmm6, %xmm2 0xc5,0xe8,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe8,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe8,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe8,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde = vaddpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde = vsubpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde = vmulpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde = vdivpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xda,0x5f,0xf2 = vmaxss %xmm2, %xmm4, %xmm6 0xc5,0xdb,0x5f,0xf2 = vmaxsd %xmm2, %xmm4, %xmm6 0xc5,0xda,0x5d,0xf2 = vminss %xmm2, %xmm4, %xmm6 0xc5,0xdb,0x5d,0xf2 = vminsd %xmm2, %xmm4, %xmm6 0xc5,0xea,0x5f,0x6c,0xcb,0xfc = vmaxss -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xeb,0x5f,0x6c,0xcb,0xfc = vmaxsd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xea,0x5d,0x6c,0xcb,0xfc = vminss -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xeb,0x5d,0x6c,0xcb,0xfc = vminsd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xd8,0x5f,0xf2 = vmaxps %xmm2, %xmm4, %xmm6 0xc5,0xd9,0x5f,0xf2 = vmaxpd %xmm2, %xmm4, %xmm6 0xc5,0xd8,0x5d,0xf2 = vminps %xmm2, %xmm4, %xmm6 0xc5,0xd9,0x5d,0xf2 = vminpd %xmm2, %xmm4, %xmm6 0xc5,0xe8,0x5f,0x6c,0xcb,0xfc = vmaxps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x5f,0x6c,0xcb,0xfc = vmaxpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe8,0x5d,0x6c,0xcb,0xfc = vminps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x5d,0x6c,0xcb,0xfc = vminpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xd8,0x54,0xf2 = vandps %xmm2, %xmm4, %xmm6 0xc5,0xd9,0x54,0xf2 = vandpd %xmm2, %xmm4, %xmm6 0xc5,0xe8,0x54,0x6c,0xcb,0xfc = vandps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x54,0x6c,0xcb,0xfc = vandpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xd8,0x56,0xf2 = vorps %xmm2, %xmm4, %xmm6 0xc5,0xd9,0x56,0xf2 = vorpd %xmm2, %xmm4, %xmm6 0xc5,0xe8,0x56,0x6c,0xcb,0xfc = vorps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x56,0x6c,0xcb,0xfc = vorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xd8,0x57,0xf2 = vxorps %xmm2, %xmm4, %xmm6 0xc5,0xd9,0x57,0xf2 = vxorpd %xmm2, %xmm4, %xmm6 0xc5,0xe8,0x57,0x6c,0xcb,0xfc = vxorps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x57,0x6c,0xcb,0xfc = vxorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xd8,0x55,0xf2 = vandnps %xmm2, %xmm4, %xmm6 0xc5,0xd9,0x55,0xf2 = vandnpd %xmm2, %xmm4, %xmm6 0xc5,0xe8,0x55,0x6c,0xcb,0xfc = vandnps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x55,0x6c,0xcb,0xfc = vandnpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xfa,0x10,0x6c,0xcb,0xfc = vmovss -4(%ebx, %ecx, 8), %xmm5 0xc5,0xea,0x10,0xec = vmovss %xmm4, %xmm2, %xmm5 0xc5,0xfb,0x10,0x6c,0xcb,0xfc = vmovsd -4(%ebx, %ecx, 8), %xmm5 0xc5,0xeb,0x10,0xec = vmovsd %xmm4, %xmm2, %xmm5 0xc5,0xe8,0x15,0xe1 = vunpckhps %xmm1, %xmm2, %xmm4 0xc5,0xe9,0x15,0xe1 = vunpckhpd %xmm1, %xmm2, %xmm4 0xc5,0xe8,0x14,0xe1 = vunpcklps %xmm1, %xmm2, %xmm4 0xc5,0xe9,0x14,0xe1 = vunpcklpd %xmm1, %xmm2, %xmm4 0xc5,0xe8,0x15,0x6c,0xcb,0xfc = vunpckhps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x15,0x6c,0xcb,0xfc = vunpckhpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe8,0x14,0x6c,0xcb,0xfc = vunpcklps -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xe9,0x14,0x6c,0xcb,0xfc = vunpcklpd -4(%ebx, %ecx, 8), %xmm2, %xmm5 0xc5,0xc8,0xc2,0xc8,0x00 = vcmpeqps %xmm0, %xmm6, %xmm1 0xc5,0xc8,0xc2,0x08,0x00 = vcmpeqps (%eax), %xmm6, %xmm1 0xc5,0xc8,0xc2,0xc8,0x07 = vcmpordps %xmm0, %xmm6, %xmm1 0xc5,0xc9,0xc2,0xc8,0x00 = vcmpeqpd %xmm0, %xmm6, %xmm1 0xc5,0xc9,0xc2,0x08,0x00 = vcmpeqpd (%eax), %xmm6, %xmm1 0xc5,0xc9,0xc2,0xc8,0x07 = vcmpordpd %xmm0, %xmm6, %xmm1 0xc5,0xe8,0xc6,0xd9,0x08 = vshufps $8, %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc6,0x5c,0xcb,0xfc,0x08 = vshufps $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc6,0xd9,0x08 = vshufpd $8, %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc6,0x5c,0xcb,0xfc,0x08 = vshufpd $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x00 = vcmpeqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x02 = vcmpleps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x01 = vcmpltps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x04 = vcmpneqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x06 = vcmpnleps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x05 = vcmpnltps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x07 = vcmpordps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x03 = vcmpunordps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x02 = vcmpleps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnleps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordps -4(%ebx, %ecx, 8), %xmm6, %xmm2 0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordps -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x00 = vcmpeqpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x02 = vcmplepd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x01 = vcmpltpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x04 = vcmpneqpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x06 = vcmpnlepd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x05 = vcmpnltpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x07 = vcmpordpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0xd9,0x03 = vcmpunordpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x02 = vcmplepd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnlepd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordpd -4(%ebx, %ecx, 8), %xmm6, %xmm2 0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordpd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xf8,0x50,0xc2 = vmovmskps %xmm2, %eax 0xc5,0xf9,0x50,0xc2 = vmovmskpd %xmm2, %eax 0xc5,0xfc,0x50,0xc2 = vmovmskps %ymm2, %eax 0xc5,0xfd,0x50,0xc2 = vmovmskpd %ymm2, %eax 0xc5,0xea,0xc2,0xd9,0x00 = vcmpeqss %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x02 = vcmpless %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x01 = vcmpltss %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x04 = vcmpneqss %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x06 = vcmpnless %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x05 = vcmpnltss %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x07 = vcmpordss %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0xd9,0x03 = vcmpunordss %xmm1, %xmm2, %xmm3 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqss -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x02 = vcmpless -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltss -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqss -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnless -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltss -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordss -4(%ebx, %ecx, 8), %xmm6, %xmm2 0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordss -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x00 = vcmpeqsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x02 = vcmplesd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x01 = vcmpltsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x04 = vcmpneqsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x06 = vcmpnlesd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x05 = vcmpnltsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x07 = vcmpordsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0xd9,0x03 = vcmpunordsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x02 = vcmplesd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnlesd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordsd -4(%ebx, %ecx, 8), %xmm6, %xmm2 0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordsd -4(%ebx, %ecx, 8), %xmm2, %xmm3 0xc5,0xf8,0x2e,0xd1 = vucomiss %xmm1, %xmm2 0xc5,0xf8,0x2e,0x10 = vucomiss (%eax), %xmm2 0xc5,0xf8,0x2f,0xd1 = vcomiss %xmm1, %xmm2 0xc5,0xf8,0x2f,0x10 = vcomiss (%eax), %xmm2 0xc5,0xf9,0x2e,0xd1 = vucomisd %xmm1, %xmm2 0xc5,0xf9,0x2e,0x10 = vucomisd (%eax), %xmm2 0xc5,0xf9,0x2f,0xd1 = vcomisd %xmm1, %xmm2 0xc5,0xf9,0x2f,0x10 = vcomisd (%eax), %xmm2 0xc5,0xfa,0x2c,0xc1 = vcvttss2si %xmm1, %eax 0xc5,0xf2,0x2a,0x10 = vcvtsi2ssl (%eax), %xmm1, %xmm2 0xc5,0xfb,0x2c,0xc1 = vcvttsd2si %xmm1, %eax 0xc5,0xfb,0x2c,0x01 = vcvttsd2si (%ecx), %eax 0xc5,0xf3,0x2a,0x10 = vcvtsi2sdl (%eax), %xmm1, %xmm2 0xc5,0xf8,0x28,0x10 = vmovaps (%eax), %xmm2 0xc5,0xf8,0x28,0xd1 = vmovaps %xmm1, %xmm2 0xc5,0xf8,0x29,0x08 = vmovaps %xmm1, (%eax) 0xc5,0xf9,0x28,0x10 = vmovapd (%eax), %xmm2 0xc5,0xf9,0x28,0xd1 = vmovapd %xmm1, %xmm2 0xc5,0xf9,0x29,0x08 = vmovapd %xmm1, (%eax) 0xc5,0xf8,0x10,0x10 = vmovups (%eax), %xmm2 0xc5,0xf8,0x10,0xd1 = vmovups %xmm1, %xmm2 0xc5,0xf8,0x11,0x08 = vmovups %xmm1, (%eax) 0xc5,0xf9,0x10,0x10 = vmovupd (%eax), %xmm2 0xc5,0xf9,0x10,0xd1 = vmovupd %xmm1, %xmm2 0xc5,0xf9,0x11,0x08 = vmovupd %xmm1, (%eax) 0xc5,0xf8,0x13,0x08 = vmovlps %xmm1, (%eax) 0xc5,0xe8,0x12,0x18 = vmovlps (%eax), %xmm2, %xmm3 0xc5,0xf9,0x13,0x08 = vmovlpd %xmm1, (%eax) 0xc5,0xe9,0x12,0x18 = vmovlpd (%eax), %xmm2, %xmm3 0xc5,0xf8,0x17,0x08 = vmovhps %xmm1, (%eax) 0xc5,0xe8,0x16,0x18 = vmovhps (%eax), %xmm2, %xmm3 0xc5,0xf9,0x17,0x08 = vmovhpd %xmm1, (%eax) 0xc5,0xe9,0x16,0x18 = vmovhpd (%eax), %xmm2, %xmm3 0xc5,0xe8,0x16,0xd9 = vmovlhps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0x12,0xd9 = vmovhlps %xmm1, %xmm2, %xmm3 0xc5,0xfa,0x2d,0xc1 = vcvtss2si %xmm1, %eax 0xc5,0xfa,0x2d,0x18 = vcvtss2si (%eax), %ebx 0xc5,0xfa,0x2d,0xc1 = vcvtss2si %xmm1, %eax 0xc5,0xfa,0x2d,0x18 = vcvtss2si (%eax), %ebx 0xc5,0xf8,0x5b,0xf5 = vcvtdq2ps %xmm5, %xmm6 0xc5,0xf8,0x5b,0x30 = vcvtdq2ps (%eax), %xmm6 0xc5,0xdb,0x5a,0xf2 = vcvtsd2ss %xmm2, %xmm4, %xmm6 0xc5,0xdb,0x5a,0x30 = vcvtsd2ss (%eax), %xmm4, %xmm6 0xc5,0xf9,0x5b,0xda = vcvtps2dq %xmm2, %xmm3 0xc5,0xf9,0x5b,0x18 = vcvtps2dq (%eax), %xmm3 0xc5,0xda,0x5a,0xf2 = vcvtss2sd %xmm2, %xmm4, %xmm6 0xc5,0xda,0x5a,0x30 = vcvtss2sd (%eax), %xmm4, %xmm6 0xc5,0xf8,0x5b,0xf4 = vcvtdq2ps %xmm4, %xmm6 0xc5,0xf8,0x5b,0x21 = vcvtdq2ps (%ecx), %xmm4 0xc5,0xfa,0x5b,0xda = vcvttps2dq %xmm2, %xmm3 0xc5,0xfa,0x5b,0x18 = vcvttps2dq (%eax), %xmm3 0xc5,0xf8,0x5a,0xda = vcvtps2pd %xmm2, %xmm3 0xc5,0xf8,0x5a,0x18 = vcvtps2pd (%eax), %xmm3 0xc5,0xf9,0x5a,0xda = vcvtpd2ps %xmm2, %xmm3 0xc5,0xf9,0x51,0xd1 = vsqrtpd %xmm1, %xmm2 0xc5,0xf9,0x51,0x10 = vsqrtpd (%eax), %xmm2 0xc5,0xf8,0x51,0xd1 = vsqrtps %xmm1, %xmm2 0xc5,0xf8,0x51,0x10 = vsqrtps (%eax), %xmm2 0xc5,0xeb,0x51,0xd9 = vsqrtsd %xmm1, %xmm2, %xmm3 0xc5,0xeb,0x51,0x18 = vsqrtsd (%eax), %xmm2, %xmm3 0xc5,0xea,0x51,0xd9 = vsqrtss %xmm1, %xmm2, %xmm3 0xc5,0xea,0x51,0x18 = vsqrtss (%eax), %xmm2, %xmm3 0xc5,0xf8,0x52,0xd1 = vrsqrtps %xmm1, %xmm2 0xc5,0xf8,0x52,0x10 = vrsqrtps (%eax), %xmm2 0xc5,0xea,0x52,0xd9 = vrsqrtss %xmm1, %xmm2, %xmm3 0xc5,0xea,0x52,0x18 = vrsqrtss (%eax), %xmm2, %xmm3 0xc5,0xf8,0x53,0xd1 = vrcpps %xmm1, %xmm2 0xc5,0xf8,0x53,0x10 = vrcpps (%eax), %xmm2 0xc5,0xea,0x53,0xd9 = vrcpss %xmm1, %xmm2, %xmm3 0xc5,0xea,0x53,0x18 = vrcpss (%eax), %xmm2, %xmm3 0xc5,0xf9,0xe7,0x08 = vmovntdq %xmm1, (%eax) 0xc5,0xf9,0x2b,0x08 = vmovntpd %xmm1, (%eax) 0xc5,0xf8,0x2b,0x08 = vmovntps %xmm1, (%eax) 0xc5,0xf8,0xae,0x10 = vldmxcsr (%eax) 0xc5,0xf8,0xae,0x18 = vstmxcsr (%eax) 0xc5,0xf8,0xae,0x15,0xef,0xbe,0xad,0xde = vldmxcsr 0xdeadbeef 0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde = vstmxcsr 0xdeadbeef 0xc5,0xe9,0xf8,0xd9 = vpsubb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf8,0x18 = vpsubb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xf9,0xd9 = vpsubw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf9,0x18 = vpsubw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xfa,0xd9 = vpsubd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xfa,0x18 = vpsubd (%eax), %xmm2, %xmm3 0xc5,0xe9,0xfb,0xd9 = vpsubq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xfb,0x18 = vpsubq (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe8,0xd9 = vpsubsb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe8,0x18 = vpsubsb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe9,0xd9 = vpsubsw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe9,0x18 = vpsubsw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd8,0xd9 = vpsubusb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd8,0x18 = vpsubusb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd9,0xd9 = vpsubusw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd9,0x18 = vpsubusw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xfc,0xd9 = vpaddb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xfc,0x18 = vpaddb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xfd,0xd9 = vpaddw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xfd,0x18 = vpaddw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xfe,0xd9 = vpaddd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xfe,0x18 = vpaddd (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd4,0xd9 = vpaddq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd4,0x18 = vpaddq (%eax), %xmm2, %xmm3 0xc5,0xe9,0xec,0xd9 = vpaddsb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xec,0x18 = vpaddsb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xed,0xd9 = vpaddsw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xed,0x18 = vpaddsw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xdc,0xd9 = vpaddusb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xdc,0x18 = vpaddusb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xdd,0xd9 = vpaddusw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xdd,0x18 = vpaddusw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe4,0xd9 = vpmulhuw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe4,0x18 = vpmulhuw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe5,0xd9 = vpmulhw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe5,0x18 = vpmulhw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd5,0xd9 = vpmullw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd5,0x18 = vpmullw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xf4,0xd9 = vpmuludq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf4,0x18 = vpmuludq (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe0,0xd9 = vpavgb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe0,0x18 = vpavgb (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe3,0xd9 = vpavgw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe3,0x18 = vpavgw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xea,0xd9 = vpminsw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xea,0x18 = vpminsw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xda,0xd9 = vpminub %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xda,0x18 = vpminub (%eax), %xmm2, %xmm3 0xc5,0xe9,0xee,0xd9 = vpmaxsw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xee,0x18 = vpmaxsw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xde,0xd9 = vpmaxub %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xde,0x18 = vpmaxub (%eax), %xmm2, %xmm3 0xc5,0xe9,0xf6,0xd9 = vpsadbw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf6,0x18 = vpsadbw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xf1,0xd9 = vpsllw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf1,0x18 = vpsllw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xf2,0xd9 = vpslld %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf2,0x18 = vpslld (%eax), %xmm2, %xmm3 0xc5,0xe9,0xf3,0xd9 = vpsllq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xf3,0x18 = vpsllq (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe1,0xd9 = vpsraw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe1,0x18 = vpsraw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xe2,0xd9 = vpsrad %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xe2,0x18 = vpsrad (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd1,0xd9 = vpsrlw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd1,0x18 = vpsrlw (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd2,0xd9 = vpsrld %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd2,0x18 = vpsrld (%eax), %xmm2, %xmm3 0xc5,0xe9,0xd3,0xd9 = vpsrlq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xd3,0x18 = vpsrlq (%eax), %xmm2, %xmm3 0xc5,0xe1,0x72,0xf2,0x0a = vpslld $10, %xmm2, %xmm3 0xc5,0xe1,0x73,0xfa,0x0a = vpslldq $10, %xmm2, %xmm3 0xc5,0xe1,0x73,0xf2,0x0a = vpsllq $10, %xmm2, %xmm3 0xc5,0xe1,0x71,0xf2,0x0a = vpsllw $10, %xmm2, %xmm3 0xc5,0xe1,0x72,0xe2,0x0a = vpsrad $10, %xmm2, %xmm3 0xc5,0xe1,0x71,0xe2,0x0a = vpsraw $10, %xmm2, %xmm3 0xc5,0xe1,0x72,0xd2,0x0a = vpsrld $10, %xmm2, %xmm3 0xc5,0xe1,0x73,0xda,0x0a = vpsrldq $10, %xmm2, %xmm3 0xc5,0xe1,0x73,0xd2,0x0a = vpsrlq $10, %xmm2, %xmm3 0xc5,0xe1,0x71,0xd2,0x0a = vpsrlw $10, %xmm2, %xmm3 0xc5,0xe1,0x72,0xf2,0x0a = vpslld $10, %xmm2, %xmm3 0xc5,0xe9,0xdb,0xd9 = vpand %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xdb,0x18 = vpand (%eax), %xmm2, %xmm3 0xc5,0xe9,0xeb,0xd9 = vpor %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xeb,0x18 = vpor (%eax), %xmm2, %xmm3 0xc5,0xe9,0xef,0xd9 = vpxor %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xef,0x18 = vpxor (%eax), %xmm2, %xmm3 0xc5,0xe9,0xdf,0xd9 = vpandn %xmm1, %xmm2, %xmm3 0xc5,0xe9,0xdf,0x18 = vpandn (%eax), %xmm2, %xmm3 0xc5,0xe9,0x74,0xd9 = vpcmpeqb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x74,0x18 = vpcmpeqb (%eax), %xmm2, %xmm3 0xc5,0xe9,0x75,0xd9 = vpcmpeqw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x75,0x18 = vpcmpeqw (%eax), %xmm2, %xmm3 0xc5,0xe9,0x76,0xd9 = vpcmpeqd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x76,0x18 = vpcmpeqd (%eax), %xmm2, %xmm3 0xc5,0xe9,0x64,0xd9 = vpcmpgtb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x64,0x18 = vpcmpgtb (%eax), %xmm2, %xmm3 0xc5,0xe9,0x65,0xd9 = vpcmpgtw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x65,0x18 = vpcmpgtw (%eax), %xmm2, %xmm3 0xc5,0xe9,0x66,0xd9 = vpcmpgtd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x66,0x18 = vpcmpgtd (%eax), %xmm2, %xmm3 0xc5,0xe9,0x63,0xd9 = vpacksswb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x63,0x18 = vpacksswb (%eax), %xmm2, %xmm3 0xc5,0xe9,0x6b,0xd9 = vpackssdw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x6b,0x18 = vpackssdw (%eax), %xmm2, %xmm3 0xc5,0xe9,0x67,0xd9 = vpackuswb %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x67,0x18 = vpackuswb (%eax), %xmm2, %xmm3 0xc5,0xf9,0x70,0xda,0x04 = vpshufd $4, %xmm2, %xmm3 0xc5,0xf9,0x70,0x18,0x04 = vpshufd $4, (%eax), %xmm3 0xc5,0xfa,0x70,0xda,0x04 = vpshufhw $4, %xmm2, %xmm3 0xc5,0xfa,0x70,0x18,0x04 = vpshufhw $4, (%eax), %xmm3 0xc5,0xfb,0x70,0xda,0x04 = vpshuflw $4, %xmm2, %xmm3 0xc5,0xfb,0x70,0x18,0x04 = vpshuflw $4, (%eax), %xmm3 0xc5,0xe9,0x60,0xd9 = vpunpcklbw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x60,0x18 = vpunpcklbw (%eax), %xmm2, %xmm3 0xc5,0xe9,0x61,0xd9 = vpunpcklwd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x61,0x18 = vpunpcklwd (%eax), %xmm2, %xmm3 0xc5,0xe9,0x62,0xd9 = vpunpckldq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x62,0x18 = vpunpckldq (%eax), %xmm2, %xmm3 0xc5,0xe9,0x6c,0xd9 = vpunpcklqdq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x6c,0x18 = vpunpcklqdq (%eax), %xmm2, %xmm3 0xc5,0xe9,0x68,0xd9 = vpunpckhbw %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x68,0x18 = vpunpckhbw (%eax), %xmm2, %xmm3 0xc5,0xe9,0x69,0xd9 = vpunpckhwd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x69,0x18 = vpunpckhwd (%eax), %xmm2, %xmm3 0xc5,0xe9,0x6a,0xd9 = vpunpckhdq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x6a,0x18 = vpunpckhdq (%eax), %xmm2, %xmm3 0xc5,0xe9,0x6d,0xd9 = vpunpckhqdq %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x6d,0x18 = vpunpckhqdq (%eax), %xmm2, %xmm3 0xc5,0xe9,0xc4,0xd8,0x07 = vpinsrw $7, %eax, %xmm2, %xmm3 0xc5,0xe9,0xc4,0x18,0x07 = vpinsrw $7, (%eax), %xmm2, %xmm3 0xc5,0xf9,0xc5,0xc2,0x07 = vpextrw $7, %xmm2, %eax 0xc5,0xf9,0xd7,0xc1 = vpmovmskb %xmm1, %eax 0xc5,0xf9,0xf7,0xd1 = vmaskmovdqu %xmm1, %xmm2 0xc5,0xf9,0x7e,0xc8 = vmovd %xmm1, %eax 0xc5,0xf9,0x7e,0x08 = vmovd %xmm1, (%eax) 0xc5,0xf9,0x6e,0xc8 = vmovd %eax, %xmm1 0xc5,0xf9,0x6e,0x08 = vmovd (%eax), %xmm1 0xc5,0xf9,0xd6,0x08 = vmovq %xmm1, (%eax) 0xc5,0xfa,0x7e,0xd1 = vmovq %xmm1, %xmm2 0xc5,0xfa,0x7e,0x08 = vmovq (%eax), %xmm1 0xc5,0xfb,0xe6,0xd1 = vcvtpd2dq %xmm1, %xmm2 0xc5,0xfa,0xe6,0xd1 = vcvtdq2pd %xmm1, %xmm2 0xc5,0xfa,0xe6,0x10 = vcvtdq2pd (%eax), %xmm2 0xc5,0xfa,0x16,0xd1 = vmovshdup %xmm1, %xmm2 0xc5,0xfa,0x16,0x10 = vmovshdup (%eax), %xmm2 0xc5,0xfa,0x12,0xd1 = vmovsldup %xmm1, %xmm2 0xc5,0xfa,0x12,0x10 = vmovsldup (%eax), %xmm2 0xc5,0xfb,0x12,0xd1 = vmovddup %xmm1, %xmm2 0xc5,0xfb,0x12,0x10 = vmovddup (%eax), %xmm2 0xc5,0xeb,0xd0,0xd9 = vaddsubps %xmm1, %xmm2, %xmm3 0xc5,0xf3,0xd0,0x10 = vaddsubps (%eax), %xmm1, %xmm2 0xc5,0xe9,0xd0,0xd9 = vaddsubpd %xmm1, %xmm2, %xmm3 0xc5,0xf1,0xd0,0x10 = vaddsubpd (%eax), %xmm1, %xmm2 0xc5,0xeb,0x7c,0xd9 = vhaddps %xmm1, %xmm2, %xmm3 0xc5,0xeb,0x7c,0x18 = vhaddps (%eax), %xmm2, %xmm3 0xc5,0xe9,0x7c,0xd9 = vhaddpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x7c,0x18 = vhaddpd (%eax), %xmm2, %xmm3 0xc5,0xeb,0x7d,0xd9 = vhsubps %xmm1, %xmm2, %xmm3 0xc5,0xeb,0x7d,0x18 = vhsubps (%eax), %xmm2, %xmm3 0xc5,0xe9,0x7d,0xd9 = vhsubpd %xmm1, %xmm2, %xmm3 0xc5,0xe9,0x7d,0x18 = vhsubpd (%eax), %xmm2, %xmm3 0xc4,0xe2,0x79,0x1c,0xd1 = vpabsb %xmm1, %xmm2 0xc4,0xe2,0x79,0x1c,0x10 = vpabsb (%eax), %xmm2 0xc4,0xe2,0x79,0x1d,0xd1 = vpabsw %xmm1, %xmm2 0xc4,0xe2,0x79,0x1d,0x10 = vpabsw (%eax), %xmm2 0xc4,0xe2,0x79,0x1e,0xd1 = vpabsd %xmm1, %xmm2 0xc4,0xe2,0x79,0x1e,0x10 = vpabsd (%eax), %xmm2 0xc4,0xe2,0x69,0x01,0xd9 = vphaddw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x01,0x18 = vphaddw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x02,0xd9 = vphaddd %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x02,0x18 = vphaddd (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x03,0xd9 = vphaddsw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x03,0x18 = vphaddsw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x05,0xd9 = vphsubw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x05,0x18 = vphsubw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x06,0xd9 = vphsubd %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x06,0x18 = vphsubd (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x07,0xd9 = vphsubsw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x07,0x18 = vphsubsw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x04,0xd9 = vpmaddubsw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x04,0x18 = vpmaddubsw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x00,0xd9 = vpshufb %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x00,0x18 = vpshufb (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x08,0xd9 = vpsignb %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x08,0x18 = vpsignb (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x09,0xd9 = vpsignw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x09,0x18 = vpsignw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x0a,0xd9 = vpsignd %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x0a,0x18 = vpsignd (%eax), %xmm2, %xmm3 0xc4,0xe2,0x69,0x0b,0xd9 = vpmulhrsw %xmm1, %xmm2, %xmm3 0xc4,0xe2,0x69,0x0b,0x18 = vpmulhrsw (%eax), %xmm2, %xmm3 0xc4,0xe3,0x69,0x0f,0xd9,0x07 = vpalignr $7, %xmm1, %xmm2, %xmm3 0xc4,0xe3,0x69,0x0f,0x18,0x07 = vpalignr $7, (%eax), %xmm2, %xmm3 0xc4,0xe3,0x69,0x0b,0xd9,0x07 = vroundsd $7, %xmm1, %xmm2, %xmm3 0xc4,0xe3,0x69,0x0b,0x18,0x07 = vroundsd $7, (%eax), %xmm2, %xmm3 0xc4,0xe3,0x69,0x0a,0xd9,0x07 = vroundss $7, %xmm1, %xmm2, %xmm3 0xc4,0xe3,0x69,0x0a,0x18,0x07 = vroundss $7, (%eax), %xmm2, %xmm3 0xc4,0xe3,0x79,0x09,0xda,0x07 = vroundpd $7, %xmm2, %xmm3 0xc4,0xe3,0x79,0x09,0x18,0x07 = vroundpd $7, (%eax), %xmm3 0xc4,0xe3,0x79,0x08,0xda,0x07 = vroundps $7, %xmm2, %xmm3 0xc4,0xe3,0x79,0x08,0x18,0x07 = vroundps $7, (%eax), %xmm3 0xc4,0xe2,0x79,0x41,0xda = vphminposuw %xmm2, %xmm3 0xc4,0xe2,0x79,0x41,0x10 = vphminposuw (%eax), %xmm2 0xc4,0xe2,0x61,0x2b,0xca = vpackusdw %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x2b,0x18 = vpackusdw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x29,0xca = vpcmpeqq %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x29,0x18 = vpcmpeqq (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x38,0xca = vpminsb %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x38,0x18 = vpminsb (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x39,0xca = vpminsd %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x39,0x18 = vpminsd (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x3b,0xca = vpminud %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x3b,0x18 = vpminud (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x3a,0xca = vpminuw %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x3a,0x18 = vpminuw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x3c,0xca = vpmaxsb %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x3c,0x18 = vpmaxsb (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x3d,0xca = vpmaxsd %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x3d,0x18 = vpmaxsd (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x3f,0xca = vpmaxud %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x3f,0x18 = vpmaxud (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x3e,0xca = vpmaxuw %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x3e,0x18 = vpmaxuw (%eax), %xmm2, %xmm3 0xc4,0xe2,0x61,0x28,0xca = vpmuldq %xmm2, %xmm3, %xmm1 0xc4,0xe2,0x69,0x28,0x18 = vpmuldq (%eax), %xmm2, %xmm3 0xc4,0xe2,0x51,0x40,0xca = vpmulld %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x40,0x18 = vpmulld (%eax), %xmm5, %xmm3 0xc4,0xe3,0x51,0x0c,0xca,0x03 = vblendps $3, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x0c,0x08,0x03 = vblendps $3, (%eax), %xmm5, %xmm1 0xc4,0xe3,0x51,0x0d,0xca,0x03 = vblendpd $3, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x0d,0x08,0x03 = vblendpd $3, (%eax), %xmm5, %xmm1 0xc4,0xe3,0x51,0x0e,0xca,0x03 = vpblendw $3, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x0e,0x08,0x03 = vpblendw $3, (%eax), %xmm5, %xmm1 0xc4,0xe3,0x51,0x42,0xca,0x03 = vmpsadbw $3, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x42,0x08,0x03 = vmpsadbw $3, (%eax), %xmm5, %xmm1 0xc4,0xe3,0x51,0x40,0xca,0x03 = vdpps $3, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x40,0x08,0x03 = vdpps $3, (%eax), %xmm5, %xmm1 0xc4,0xe3,0x51,0x41,0xca,0x03 = vdppd $3, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x41,0x08,0x03 = vdppd $3, (%eax), %xmm5, %xmm1 0xc4,0xe3,0x71,0x4b,0xdd,0x20 = vblendvpd %xmm2, %xmm5, %xmm1, %xmm3 0xc4,0xe3,0x71,0x4b,0x18,0x20 = vblendvpd %xmm2, (%eax), %xmm1, %xmm3 0xc4,0xe3,0x71,0x4a,0xdd,0x20 = vblendvps %xmm2, %xmm5, %xmm1, %xmm3 0xc4,0xe3,0x71,0x4a,0x18,0x20 = vblendvps %xmm2, (%eax), %xmm1, %xmm3 0xc4,0xe3,0x71,0x4c,0xdd,0x20 = vpblendvb %xmm2, %xmm5, %xmm1, %xmm3 0xc4,0xe3,0x71,0x4c,0x18,0x20 = vpblendvb %xmm2, (%eax), %xmm1, %xmm3 0xc4,0xe2,0x79,0x20,0xea = vpmovsxbw %xmm2, %xmm5 0xc4,0xe2,0x79,0x20,0x10 = vpmovsxbw (%eax), %xmm2 0xc4,0xe2,0x79,0x23,0xea = vpmovsxwd %xmm2, %xmm5 0xc4,0xe2,0x79,0x23,0x10 = vpmovsxwd (%eax), %xmm2 0xc4,0xe2,0x79,0x25,0xea = vpmovsxdq %xmm2, %xmm5 0xc4,0xe2,0x79,0x25,0x10 = vpmovsxdq (%eax), %xmm2 0xc4,0xe2,0x79,0x30,0xea = vpmovzxbw %xmm2, %xmm5 0xc4,0xe2,0x79,0x30,0x10 = vpmovzxbw (%eax), %xmm2 0xc4,0xe2,0x79,0x33,0xea = vpmovzxwd %xmm2, %xmm5 0xc4,0xe2,0x79,0x33,0x10 = vpmovzxwd (%eax), %xmm2 0xc4,0xe2,0x79,0x35,0xea = vpmovzxdq %xmm2, %xmm5 0xc4,0xe2,0x79,0x35,0x10 = vpmovzxdq (%eax), %xmm2 0xc4,0xe2,0x79,0x22,0xea = vpmovsxbq %xmm2, %xmm5 0xc4,0xe2,0x79,0x22,0x10 = vpmovsxbq (%eax), %xmm2 0xc4,0xe2,0x79,0x32,0xea = vpmovzxbq %xmm2, %xmm5 0xc4,0xe2,0x79,0x32,0x10 = vpmovzxbq (%eax), %xmm2 0xc4,0xe2,0x79,0x21,0xea = vpmovsxbd %xmm2, %xmm5 0xc4,0xe2,0x79,0x21,0x10 = vpmovsxbd (%eax), %xmm2 0xc4,0xe2,0x79,0x24,0xea = vpmovsxwq %xmm2, %xmm5 0xc4,0xe2,0x79,0x24,0x10 = vpmovsxwq (%eax), %xmm2 0xc4,0xe2,0x79,0x31,0xea = vpmovzxbd %xmm2, %xmm5 0xc4,0xe2,0x79,0x31,0x10 = vpmovzxbd (%eax), %xmm2 0xc4,0xe2,0x79,0x34,0xea = vpmovzxwq %xmm2, %xmm5 0xc4,0xe2,0x79,0x34,0x10 = vpmovzxwq (%eax), %xmm2 0xc5,0xf9,0xc5,0xc2,0x07 = vpextrw $7, %xmm2, %eax 0xc4,0xe3,0x79,0x15,0x10,0x07 = vpextrw $7, %xmm2, (%eax) 0xc4,0xe3,0x79,0x16,0xd0,0x07 = vpextrd $7, %xmm2, %eax 0xc4,0xe3,0x79,0x16,0x10,0x07 = vpextrd $7, %xmm2, (%eax) 0xc4,0xe3,0x79,0x14,0xd0,0x07 = vpextrb $7, %xmm2, %eax 0xc4,0xe3,0x79,0x14,0x10,0x07 = vpextrb $7, %xmm2, (%eax) 0xc4,0xe3,0x79,0x17,0x10,0x07 = vextractps $7, %xmm2, (%eax) 0xc4,0xe3,0x79,0x17,0xd0,0x07 = vextractps $7, %xmm2, %eax 0xc5,0xe9,0xc4,0xe8,0x07 = vpinsrw $7, %eax, %xmm2, %xmm5 0xc5,0xe9,0xc4,0x28,0x07 = vpinsrw $7, (%eax), %xmm2, %xmm5 0xc4,0xe3,0x69,0x20,0xe8,0x07 = vpinsrb $7, %eax, %xmm2, %xmm5 0xc4,0xe3,0x69,0x20,0x28,0x07 = vpinsrb $7, (%eax), %xmm2, %xmm5 0xc4,0xe3,0x69,0x22,0xe8,0x07 = vpinsrd $7, %eax, %xmm2, %xmm5 0xc4,0xe3,0x69,0x22,0x28,0x07 = vpinsrd $7, (%eax), %xmm2, %xmm5 0xc4,0xe3,0x51,0x21,0xca,0x07 = vinsertps $7, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x21,0x08,0x07 = vinsertps $7, (%eax), %xmm5, %xmm1 0xc4,0xe2,0x79,0x17,0xea = vptest %xmm2, %xmm5 0xc4,0xe2,0x79,0x17,0x10 = vptest (%eax), %xmm2 0xc4,0xe2,0x79,0x2a,0x10 = vmovntdqa (%eax), %xmm2 0xc4,0xe2,0x51,0x37,0xca = vpcmpgtq %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x37,0x18 = vpcmpgtq (%eax), %xmm5, %xmm3 0xc4,0xe3,0x79,0x62,0xea,0x07 = vpcmpistrm $7, %xmm2, %xmm5 0xc4,0xe3,0x79,0x62,0x28,0x07 = vpcmpistrm $7, (%eax), %xmm5 0xc4,0xe3,0x79,0x60,0xea,0x07 = vpcmpestrm $7, %xmm2, %xmm5 0xc4,0xe3,0x79,0x60,0x28,0x07 = vpcmpestrm $7, (%eax), %xmm5 0xc4,0xe3,0x79,0x63,0xea,0x07 = vpcmpistri $7, %xmm2, %xmm5 0xc4,0xe3,0x79,0x63,0x28,0x07 = vpcmpistri $7, (%eax), %xmm5 0xc4,0xe3,0x79,0x61,0xea,0x07 = vpcmpestri $7, %xmm2, %xmm5 0xc4,0xe3,0x79,0x61,0x28,0x07 = vpcmpestri $7, (%eax), %xmm5 0xc4,0xe2,0x79,0xdb,0xea = vaesimc %xmm2, %xmm5 0xc4,0xe2,0x79,0xdb,0x10 = vaesimc (%eax), %xmm2 0xc4,0xe2,0x51,0xdc,0xca = vaesenc %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xdc,0x18 = vaesenc (%eax), %xmm5, %xmm3 0xc4,0xe2,0x51,0xdd,0xca = vaesenclast %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xdd,0x18 = vaesenclast (%eax), %xmm5, %xmm3 0xc4,0xe2,0x51,0xde,0xca = vaesdec %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xde,0x18 = vaesdec (%eax), %xmm5, %xmm3 0xc4,0xe2,0x51,0xdf,0xca = vaesdeclast %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xdf,0x18 = vaesdeclast (%eax), %xmm5, %xmm3 0xc4,0xe3,0x79,0xdf,0xea,0x07 = vaeskeygenassist $7, %xmm2, %xmm5 0xc4,0xe3,0x79,0xdf,0x28,0x07 = vaeskeygenassist $7, (%eax), %xmm5 0xc5,0xe8,0xc2,0xd9,0x08 = vcmpeq_uqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x09 = vcmpngeps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x0a = vcmpngtps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x0b = vcmpfalseps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x0c = vcmpneq_oqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x0d = vcmpgeps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x0e = vcmpgtps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x0f = vcmptrueps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x10 = vcmpeq_osps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x11 = vcmplt_oqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x12 = vcmple_oqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x13 = vcmpunord_sps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x14 = vcmpneq_usps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x15 = vcmpnlt_uqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x16 = vcmpnle_uqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x17 = vcmpord_sps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x18 = vcmpeq_usps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x19 = vcmpnge_uqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x1a = vcmpngt_uqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x1b = vcmpfalse_osps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x1c = vcmpneq_osps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x1d = vcmpge_oqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x1e = vcmpgt_oqps %xmm1, %xmm2, %xmm3 0xc5,0xe8,0xc2,0xd9,0x1f = vcmptrue_usps %xmm1, %xmm2, %xmm3 0xc5,0xfc,0x28,0x10 = vmovaps (%eax), %ymm2 0xc5,0xfc,0x28,0xd1 = vmovaps %ymm1, %ymm2 0xc5,0xfc,0x29,0x08 = vmovaps %ymm1, (%eax) 0xc5,0xfd,0x28,0x10 = vmovapd (%eax), %ymm2 0xc5,0xfd,0x28,0xd1 = vmovapd %ymm1, %ymm2 0xc5,0xfd,0x29,0x08 = vmovapd %ymm1, (%eax) 0xc5,0xfc,0x10,0x10 = vmovups (%eax), %ymm2 0xc5,0xfc,0x10,0xd1 = vmovups %ymm1, %ymm2 0xc5,0xfc,0x11,0x08 = vmovups %ymm1, (%eax) 0xc5,0xfd,0x10,0x10 = vmovupd (%eax), %ymm2 0xc5,0xfd,0x10,0xd1 = vmovupd %ymm1, %ymm2 0xc5,0xfd,0x11,0x08 = vmovupd %ymm1, (%eax) 0xc5,0xec,0x15,0xe1 = vunpckhps %ymm1, %ymm2, %ymm4 0xc5,0xed,0x15,0xe1 = vunpckhpd %ymm1, %ymm2, %ymm4 0xc5,0xec,0x14,0xe1 = vunpcklps %ymm1, %ymm2, %ymm4 0xc5,0xed,0x14,0xe1 = vunpcklpd %ymm1, %ymm2, %ymm4 0xc5,0xec,0x15,0x6c,0xcb,0xfc = vunpckhps -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xed,0x15,0x6c,0xcb,0xfc = vunpckhpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xec,0x14,0x6c,0xcb,0xfc = vunpcklps -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xed,0x14,0x6c,0xcb,0xfc = vunpcklpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xfd,0xe7,0x08 = vmovntdq %ymm1, (%eax) 0xc5,0xfd,0x2b,0x08 = vmovntpd %ymm1, (%eax) 0xc5,0xfc,0x2b,0x08 = vmovntps %ymm1, (%eax) 0xc5,0xf8,0x50,0xc2 = vmovmskps %xmm2, %eax 0xc5,0xf9,0x50,0xc2 = vmovmskpd %xmm2, %eax 0xc5,0xdc,0x5f,0xf2 = vmaxps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x5f,0xf2 = vmaxpd %ymm2, %ymm4, %ymm6 0xc5,0xdc,0x5d,0xf2 = vminps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x5d,0xf2 = vminpd %ymm2, %ymm4, %ymm6 0xc5,0xdc,0x5c,0xf2 = vsubps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x5c,0xf2 = vsubpd %ymm2, %ymm4, %ymm6 0xc5,0xdc,0x5e,0xf2 = vdivps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x5e,0xf2 = vdivpd %ymm2, %ymm4, %ymm6 0xc5,0xdc,0x58,0xf2 = vaddps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x58,0xf2 = vaddpd %ymm2, %ymm4, %ymm6 0xc5,0xdc,0x59,0xf2 = vmulps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x59,0xf2 = vmulpd %ymm2, %ymm4, %ymm6 0xc5,0xdc,0x5f,0x30 = vmaxps (%eax), %ymm4, %ymm6 0xc5,0xdd,0x5f,0x30 = vmaxpd (%eax), %ymm4, %ymm6 0xc5,0xdc,0x5d,0x30 = vminps (%eax), %ymm4, %ymm6 0xc5,0xdd,0x5d,0x30 = vminpd (%eax), %ymm4, %ymm6 0xc5,0xdc,0x5c,0x30 = vsubps (%eax), %ymm4, %ymm6 0xc5,0xdd,0x5c,0x30 = vsubpd (%eax), %ymm4, %ymm6 0xc5,0xdc,0x5e,0x30 = vdivps (%eax), %ymm4, %ymm6 0xc5,0xdd,0x5e,0x30 = vdivpd (%eax), %ymm4, %ymm6 0xc5,0xdc,0x58,0x30 = vaddps (%eax), %ymm4, %ymm6 0xc5,0xdd,0x58,0x30 = vaddpd (%eax), %ymm4, %ymm6 0xc5,0xdc,0x59,0x30 = vmulps (%eax), %ymm4, %ymm6 0xc5,0xdd,0x59,0x30 = vmulpd (%eax), %ymm4, %ymm6 0xc5,0xfd,0x51,0xd1 = vsqrtpd %ymm1, %ymm2 0xc5,0xfd,0x51,0x10 = vsqrtpd (%eax), %ymm2 0xc5,0xfc,0x51,0xd1 = vsqrtps %ymm1, %ymm2 0xc5,0xfc,0x51,0x10 = vsqrtps (%eax), %ymm2 0xc5,0xfc,0x52,0xd1 = vrsqrtps %ymm1, %ymm2 0xc5,0xfc,0x52,0x10 = vrsqrtps (%eax), %ymm2 0xc5,0xfc,0x53,0xd1 = vrcpps %ymm1, %ymm2 0xc5,0xfc,0x53,0x10 = vrcpps (%eax), %ymm2 0xc5,0xdc,0x54,0xf2 = vandps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x54,0xf2 = vandpd %ymm2, %ymm4, %ymm6 0xc5,0xec,0x54,0x6c,0xcb,0xfc = vandps -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xed,0x54,0x6c,0xcb,0xfc = vandpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xdc,0x56,0xf2 = vorps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x56,0xf2 = vorpd %ymm2, %ymm4, %ymm6 0xc5,0xec,0x56,0x6c,0xcb,0xfc = vorps -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xed,0x56,0x6c,0xcb,0xfc = vorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xdc,0x57,0xf2 = vxorps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x57,0xf2 = vxorpd %ymm2, %ymm4, %ymm6 0xc5,0xec,0x57,0x6c,0xcb,0xfc = vxorps -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xed,0x57,0x6c,0xcb,0xfc = vxorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xdc,0x55,0xf2 = vandnps %ymm2, %ymm4, %ymm6 0xc5,0xdd,0x55,0xf2 = vandnpd %ymm2, %ymm4, %ymm6 0xc5,0xec,0x55,0x6c,0xcb,0xfc = vandnps -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xed,0x55,0x6c,0xcb,0xfc = vandnpd -4(%ebx, %ecx, 8), %ymm2, %ymm5 0xc5,0xfc,0x5a,0xd3 = vcvtps2pd %xmm3, %ymm2 0xc5,0xfc,0x5a,0x10 = vcvtps2pd (%eax), %ymm2 0xc5,0xfe,0xe6,0xd3 = vcvtdq2pd %xmm3, %ymm2 0xc5,0xfe,0xe6,0x10 = vcvtdq2pd (%eax), %ymm2 0xc5,0xfc,0x5b,0xea = vcvtdq2ps %ymm2, %ymm5 0xc5,0xfc,0x5b,0x10 = vcvtdq2ps (%eax), %ymm2 0xc5,0xfd,0x5b,0xea = vcvtps2dq %ymm2, %ymm5 0xc5,0xfd,0x5b,0x28 = vcvtps2dq (%eax), %ymm5 0xc5,0xfe,0x5b,0xea = vcvttps2dq %ymm2, %ymm5 0xc5,0xfe,0x5b,0x28 = vcvttps2dq (%eax), %ymm5 0xc5,0xf9,0xe6,0xe9 = vcvttpd2dq %xmm1, %xmm5 0xc5,0xfd,0xe6,0xea = vcvttpd2dq %ymm2, %xmm5 0xc5,0xf9,0xe6,0xe9 = vcvttpd2dq %xmm1, %xmm5 0xc5,0xf9,0xe6,0x08 = vcvttpd2dqx (%eax), %xmm1 0xc5,0xfd,0xe6,0xca = vcvttpd2dq %ymm2, %xmm1 0xc5,0xfd,0xe6,0x08 = vcvttpd2dqy (%eax), %xmm1 0xc5,0xfd,0x5a,0xea = vcvtpd2ps %ymm2, %xmm5 0xc5,0xf9,0x5a,0xe9 = vcvtpd2ps %xmm1, %xmm5 0xc5,0xf9,0x5a,0x08 = vcvtpd2psx (%eax), %xmm1 0xc5,0xfd,0x5a,0xca = vcvtpd2ps %ymm2, %xmm1 0xc5,0xfd,0x5a,0x08 = vcvtpd2psy (%eax), %xmm1 0xc5,0xff,0xe6,0xea = vcvtpd2dq %ymm2, %xmm5 0xc5,0xff,0xe6,0xca = vcvtpd2dq %ymm2, %xmm1 0xc5,0xff,0xe6,0x08 = vcvtpd2dqy (%eax), %xmm1 0xc5,0xfb,0xe6,0xe9 = vcvtpd2dq %xmm1, %xmm5 0xc5,0xfb,0xe6,0x08 = vcvtpd2dqx (%eax), %xmm1 0xc5,0xec,0xc2,0xd9,0x00 = vcmpeqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x02 = vcmpleps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x01 = vcmpltps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x04 = vcmpneqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x06 = vcmpnleps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x05 = vcmpnltps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x07 = vcmpordps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x03 = vcmpunordps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x02 = vcmpleps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnleps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xcc,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordps -4(%ebx, %ecx, 8), %ymm6, %ymm2 0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordps -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x00 = vcmpeqpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x02 = vcmplepd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x01 = vcmpltpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x04 = vcmpneqpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x06 = vcmpnlepd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x05 = vcmpnltpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x07 = vcmpordpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0xd9,0x03 = vcmpunordpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x00 = vcmpeqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x02 = vcmplepd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x01 = vcmpltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x04 = vcmpneqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x06 = vcmpnlepd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x05 = vcmpnltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xcd,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordpd -4(%ebx, %ecx, 8), %ymm6, %ymm2 0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x03 = vcmpunordpd -4(%ebx, %ecx, 8), %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x08 = vcmpeq_uqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x09 = vcmpngeps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x0a = vcmpngtps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x0b = vcmpfalseps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x0c = vcmpneq_oqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x0d = vcmpgeps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x0e = vcmpgtps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x0f = vcmptrueps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x10 = vcmpeq_osps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x11 = vcmplt_oqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x12 = vcmple_oqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x13 = vcmpunord_sps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x14 = vcmpneq_usps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x15 = vcmpnlt_uqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x16 = vcmpnle_uqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x17 = vcmpord_sps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x18 = vcmpeq_usps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x19 = vcmpnge_uqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x1a = vcmpngt_uqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x1b = vcmpfalse_osps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x1c = vcmpneq_osps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x1d = vcmpge_oqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x1e = vcmpgt_oqps %ymm1, %ymm2, %ymm3 0xc5,0xec,0xc2,0xd9,0x1f = vcmptrue_usps %ymm1, %ymm2, %ymm3 0xc5,0xef,0xd0,0xd9 = vaddsubps %ymm1, %ymm2, %ymm3 0xc5,0xf7,0xd0,0x10 = vaddsubps (%eax), %ymm1, %ymm2 0xc5,0xed,0xd0,0xd9 = vaddsubpd %ymm1, %ymm2, %ymm3 0xc5,0xf5,0xd0,0x10 = vaddsubpd (%eax), %ymm1, %ymm2 0xc5,0xef,0x7c,0xd9 = vhaddps %ymm1, %ymm2, %ymm3 0xc5,0xef,0x7c,0x18 = vhaddps (%eax), %ymm2, %ymm3 0xc5,0xed,0x7c,0xd9 = vhaddpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0x7c,0x18 = vhaddpd (%eax), %ymm2, %ymm3 0xc5,0xef,0x7d,0xd9 = vhsubps %ymm1, %ymm2, %ymm3 0xc5,0xef,0x7d,0x18 = vhsubps (%eax), %ymm2, %ymm3 0xc5,0xed,0x7d,0xd9 = vhsubpd %ymm1, %ymm2, %ymm3 0xc5,0xed,0x7d,0x18 = vhsubpd (%eax), %ymm2, %ymm3 0xc4,0xe3,0x55,0x0c,0xca,0x03 = vblendps $3, %ymm2, %ymm5, %ymm1 0xc4,0xe3,0x55,0x0c,0x08,0x03 = vblendps $3, (%eax), %ymm5, %ymm1 0xc4,0xe3,0x55,0x0d,0xca,0x03 = vblendpd $3, %ymm2, %ymm5, %ymm1 0xc4,0xe3,0x55,0x0d,0x08,0x03 = vblendpd $3, (%eax), %ymm5, %ymm1 0xc4,0xe3,0x55,0x40,0xca,0x03 = vdpps $3, %ymm2, %ymm5, %ymm1 0xc4,0xe3,0x55,0x40,0x08,0x03 = vdpps $3, (%eax), %ymm5, %ymm1 0xc4,0xe2,0x7d,0x1a,0x10 = vbroadcastf128 (%eax), %ymm2 0xc4,0xe2,0x7d,0x19,0x10 = vbroadcastsd (%eax), %ymm2 0xc4,0xe2,0x79,0x18,0x10 = vbroadcastss (%eax), %xmm2 0xc4,0xe2,0x7d,0x18,0x10 = vbroadcastss (%eax), %ymm2 0xc4,0xe3,0x6d,0x18,0xea,0x07 = vinsertf128 $7, %xmm2, %ymm2, %ymm5 0xc4,0xe3,0x6d,0x18,0x28,0x07 = vinsertf128 $7, (%eax), %ymm2, %ymm5 0xc4,0xe3,0x7d,0x19,0xd2,0x07 = vextractf128 $7, %ymm2, %xmm2 0xc4,0xe3,0x7d,0x19,0x10,0x07 = vextractf128 $7, %ymm2, (%eax) 0xc4,0xe2,0x51,0x2f,0x10 = vmaskmovpd %xmm2, %xmm5, (%eax) 0xc4,0xe2,0x55,0x2f,0x10 = vmaskmovpd %ymm2, %ymm5, (%eax) 0xc4,0xe2,0x69,0x2d,0x28 = vmaskmovpd (%eax), %xmm2, %xmm5 0xc4,0xe2,0x6d,0x2d,0x28 = vmaskmovpd (%eax), %ymm2, %ymm5 0xc4,0xe2,0x51,0x2e,0x10 = vmaskmovps %xmm2, %xmm5, (%eax) 0xc4,0xe2,0x55,0x2e,0x10 = vmaskmovps %ymm2, %ymm5, (%eax) 0xc4,0xe2,0x69,0x2c,0x28 = vmaskmovps (%eax), %xmm2, %xmm5 0xc4,0xe2,0x6d,0x2c,0x28 = vmaskmovps (%eax), %ymm2, %ymm5 0xc4,0xe3,0x79,0x04,0xe9,0x07 = vpermilps $7, %xmm1, %xmm5 0xc4,0xe3,0x7d,0x04,0xcd,0x07 = vpermilps $7, %ymm5, %ymm1 0xc4,0xe3,0x79,0x04,0x28,0x07 = vpermilps $7, (%eax), %xmm5 0xc4,0xe3,0x7d,0x04,0x28,0x07 = vpermilps $7, (%eax), %ymm5 0xc4,0xe2,0x51,0x0c,0xc9 = vpermilps %xmm1, %xmm5, %xmm1 0xc4,0xe2,0x55,0x0c,0xc9 = vpermilps %ymm1, %ymm5, %ymm1 0xc4,0xe2,0x51,0x0c,0x18 = vpermilps (%eax), %xmm5, %xmm3 0xc4,0xe2,0x55,0x0c,0x08 = vpermilps (%eax), %ymm5, %ymm1 0xc4,0xe3,0x79,0x05,0xe9,0x07 = vpermilpd $7, %xmm1, %xmm5 0xc4,0xe3,0x7d,0x05,0xcd,0x07 = vpermilpd $7, %ymm5, %ymm1 0xc4,0xe3,0x79,0x05,0x28,0x07 = vpermilpd $7, (%eax), %xmm5 0xc4,0xe3,0x7d,0x05,0x28,0x07 = vpermilpd $7, (%eax), %ymm5 0xc4,0xe2,0x51,0x0d,0xc9 = vpermilpd %xmm1, %xmm5, %xmm1 0xc4,0xe2,0x55,0x0d,0xc9 = vpermilpd %ymm1, %ymm5, %ymm1 0xc4,0xe2,0x51,0x0d,0x18 = vpermilpd (%eax), %xmm5, %xmm3 0xc4,0xe2,0x55,0x0d,0x08 = vpermilpd (%eax), %ymm5, %ymm1 0xc4,0xe3,0x55,0x06,0xca,0x07 = vperm2f128 $7, %ymm2, %ymm5, %ymm1 0xc4,0xe3,0x55,0x06,0x08,0x07 = vperm2f128 $7, (%eax), %ymm5, %ymm1 0xc5,0xfc,0x77 = vzeroall 0xc5,0xf8,0x77 = vzeroupper 0xc5,0xfb,0x2d,0xcc = vcvtsd2si %xmm4, %ecx 0xc5,0xfb,0x2d,0x09 = vcvtsd2si (%ecx), %ecx 0xc5,0xfb,0x2d,0xcc = vcvtsd2si %xmm4, %ecx 0xc5,0xfb,0x2d,0x09 = vcvtsd2si (%ecx), %ecx 0xc5,0xfb,0x2a,0x7d,0x00 = vcvtsi2sdl (%ebp), %xmm0, %xmm7 0xc5,0xfb,0x2a,0x3c,0x24 = vcvtsi2sdl (%esp), %xmm0, %xmm7 0xc5,0xfb,0x2a,0x7d,0x00 = vcvtsi2sdl (%ebp), %xmm0, %xmm7 0xc5,0xfb,0x2a,0x3c,0x24 = vcvtsi2sdl (%esp), %xmm0, %xmm7 0xc5,0xff,0xf0,0x10 = vlddqu (%eax), %ymm2 0xc5,0xff,0x12,0xea = vmovddup %ymm2, %ymm5 0xc5,0xff,0x12,0x10 = vmovddup (%eax), %ymm2 0xc5,0xfd,0x6f,0xea = vmovdqa %ymm2, %ymm5 0xc5,0xfd,0x7f,0x10 = vmovdqa %ymm2, (%eax) 0xc5,0xfd,0x6f,0x10 = vmovdqa (%eax), %ymm2 0xc5,0xfe,0x6f,0xea = vmovdqu %ymm2, %ymm5 0xc5,0xfe,0x7f,0x10 = vmovdqu %ymm2, (%eax) 0xc5,0xfe,0x6f,0x10 = vmovdqu (%eax), %ymm2 0xc5,0xfe,0x16,0xea = vmovshdup %ymm2, %ymm5 0xc5,0xfe,0x16,0x10 = vmovshdup (%eax), %ymm2 0xc5,0xfe,0x12,0xea = vmovsldup %ymm2, %ymm5 0xc5,0xfe,0x12,0x10 = vmovsldup (%eax), %ymm2 0xc4,0xe2,0x7d,0x17,0xea = vptest %ymm2, %ymm5 0xc4,0xe2,0x7d,0x17,0x10 = vptest (%eax), %ymm2 0xc4,0xe3,0x7d,0x09,0xcd,0x07 = vroundpd $7, %ymm5, %ymm1 0xc4,0xe3,0x7d,0x09,0x28,0x07 = vroundpd $7, (%eax), %ymm5 0xc4,0xe3,0x7d,0x08,0xcd,0x07 = vroundps $7, %ymm5, %ymm1 0xc4,0xe3,0x7d,0x08,0x28,0x07 = vroundps $7, (%eax), %ymm5 0xc5,0xd5,0xc6,0xca,0x07 = vshufpd $7, %ymm2, %ymm5, %ymm1 0xc5,0xd5,0xc6,0x08,0x07 = vshufpd $7, (%eax), %ymm5, %ymm1 0xc5,0xd4,0xc6,0xca,0x07 = vshufps $7, %ymm2, %ymm5, %ymm1 0xc5,0xd4,0xc6,0x08,0x07 = vshufps $7, (%eax), %ymm5, %ymm1 0xc4,0xe2,0x79,0x0f,0xea = vtestpd %xmm2, %xmm5 0xc4,0xe2,0x7d,0x0f,0xea = vtestpd %ymm2, %ymm5 0xc4,0xe2,0x79,0x0f,0x10 = vtestpd (%eax), %xmm2 0xc4,0xe2,0x7d,0x0f,0x10 = vtestpd (%eax), %ymm2 0xc4,0xe2,0x79,0x0e,0xea = vtestps %xmm2, %xmm5 0xc4,0xe2,0x7d,0x0e,0xea = vtestps %ymm2, %ymm5 0xc4,0xe2,0x79,0x0e,0x10 = vtestps (%eax), %xmm2 0xc4,0xe2,0x7d,0x0e,0x10 = vtestps (%eax), %ymm2 0xc4,0xe3,0x75,0x4b,0x94,0x20,0xad,0xde,0x00,0x00,0x00 = vblendvpd %ymm0, 0xdead(%eax), %ymm1, %ymm2 // 0xc4,0xe3,0x51,0x44,0xca,0x11 = vpclmulhqhqdq %xmm2, %xmm5, %xmm1 // 0xc4,0xe3,0x51,0x44,0x18,0x11 = vpclmulhqhqdq (%eax), %xmm5, %xmm3 // 0xc4,0xe3,0x51,0x44,0xca,0x01 = vpclmulhqlqdq %xmm2, %xmm5, %xmm1 // 0xc4,0xe3,0x51,0x44,0x18,0x01 = vpclmulhqlqdq (%eax), %xmm5, %xmm3 // 0xc4,0xe3,0x51,0x44,0xca,0x10 = vpclmullqhqdq %xmm2, %xmm5, %xmm1 // 0xc4,0xe3,0x51,0x44,0x18,0x10 = vpclmullqhqdq (%eax), %xmm5, %xmm3 // 0xc4,0xe3,0x51,0x44,0xca,0x00 = vpclmullqlqdq %xmm2, %xmm5, %xmm1 // 0xc4,0xe3,0x51,0x44,0x18,0x00 = vpclmullqlqdq (%eax), %xmm5, %xmm3 0xc4,0xe3,0x51,0x44,0xca,0x11 = vpclmulqdq $17, %xmm2, %xmm5, %xmm1 0xc4,0xe3,0x51,0x44,0x18,0x11 = vpclmulqdq $17, (%eax), %xmm5, %xmm3 capstone-sys-0.15.0/capstone/suite/MC/X86/x86-32-fma3.s.cs000064400000000000000000000237740072674642500205200ustar 00000000000000# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0xc4,0xe2,0xd1,0x98,0xca = vfmadd132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x98,0x08 = vfmadd132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x98,0xca = vfmadd132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x98,0x08 = vfmadd132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa8,0xca = vfmadd213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa8,0x08 = vfmadd213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xa8,0xca = vfmadd213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xa8,0x08 = vfmadd213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb8,0xca = vfmadd231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb8,0x08 = vfmadd231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xb8,0xca = vfmadd231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xb8,0x08 = vfmadd231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd5,0x98,0xca = vfmadd132pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0x98,0x08 = vfmadd132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x98,0xca = vfmadd132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x98,0x08 = vfmadd132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa8,0xca = vfmadd213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa8,0x08 = vfmadd213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xa8,0xca = vfmadd213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xa8,0x08 = vfmadd213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb8,0xca = vfmadd231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb8,0x08 = vfmadd231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xb8,0xca = vfmadd231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xb8,0x08 = vfmadd231ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd1,0x98,0xca = vfmadd132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x98,0x08 = vfmadd132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x98,0xca = vfmadd132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x98,0x08 = vfmadd132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa8,0xca = vfmadd213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa8,0x08 = vfmadd213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xa8,0xca = vfmadd213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xa8,0x08 = vfmadd213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb8,0xca = vfmadd231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb8,0x08 = vfmadd231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xb8,0xca = vfmadd231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xb8,0x08 = vfmadd231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0x96,0xca = vfmaddsub132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x96,0x08 = vfmaddsub132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x96,0xca = vfmaddsub132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x96,0x08 = vfmaddsub132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa6,0xca = vfmaddsub213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa6,0x08 = vfmaddsub213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xa6,0xca = vfmaddsub213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xa6,0x08 = vfmaddsub213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb6,0xca = vfmaddsub231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb6,0x08 = vfmaddsub231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xb6,0xca = vfmaddsub231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xb6,0x08 = vfmaddsub231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0x97,0xca = vfmsubadd132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x97,0x08 = vfmsubadd132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x97,0xca = vfmsubadd132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x97,0x08 = vfmsubadd132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa7,0xca = vfmsubadd213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xa7,0x08 = vfmsubadd213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xa7,0xca = vfmsubadd213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xa7,0x08 = vfmsubadd213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb7,0xca = vfmsubadd231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xb7,0x08 = vfmsubadd231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xb7,0xca = vfmsubadd231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xb7,0x08 = vfmsubadd231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0x9a,0xca = vfmsub132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x9a,0x08 = vfmsub132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x9a,0xca = vfmsub132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x9a,0x08 = vfmsub132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xaa,0xca = vfmsub213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xaa,0x08 = vfmsub213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xaa,0xca = vfmsub213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xaa,0x08 = vfmsub213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xba,0xca = vfmsub231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xba,0x08 = vfmsub231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xba,0xca = vfmsub231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xba,0x08 = vfmsub231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0x9c,0xca = vfnmadd132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x9c,0x08 = vfnmadd132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x9c,0xca = vfnmadd132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x9c,0x08 = vfnmadd132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xac,0xca = vfnmadd213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xac,0x08 = vfnmadd213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xac,0xca = vfnmadd213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xac,0x08 = vfnmadd213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xbc,0xca = vfnmadd231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xbc,0x08 = vfnmadd231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xbc,0xca = vfnmadd231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xbc,0x08 = vfnmadd231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0x9e,0xca = vfnmsub132pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0x9e,0x08 = vfnmsub132pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0x9e,0xca = vfnmsub132ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0x9e,0x08 = vfnmsub132ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xae,0xca = vfnmsub213pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xae,0x08 = vfnmsub213pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xae,0xca = vfnmsub213ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xae,0x08 = vfnmsub213ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd1,0xbe,0xca = vfnmsub231pd %xmm2, %xmm5, %xmm1 0xc4,0xe2,0xd1,0xbe,0x08 = vfnmsub231pd (%eax), %xmm5, %xmm1 0xc4,0xe2,0x51,0xbe,0xca = vfnmsub231ps %xmm2, %xmm5, %xmm1 0xc4,0xe2,0x51,0xbe,0x08 = vfnmsub231ps (%eax), %xmm5, %xmm1 0xc4,0xe2,0xd5,0x98,0xca = vfmadd132pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0x98,0x08 = vfmadd132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x98,0xca = vfmadd132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x98,0x08 = vfmadd132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa8,0xca = vfmadd213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa8,0x08 = vfmadd213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xa8,0xca = vfmadd213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xa8,0x08 = vfmadd213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb8,0xca = vfmadd231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb8,0x08 = vfmadd231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xb8,0xca = vfmadd231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xb8,0x08 = vfmadd231ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0x96,0xca = vfmaddsub132pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0x96,0x08 = vfmaddsub132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x96,0xca = vfmaddsub132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x96,0x08 = vfmaddsub132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa6,0xca = vfmaddsub213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa6,0x08 = vfmaddsub213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xa6,0xca = vfmaddsub213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xa6,0x08 = vfmaddsub213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb6,0xca = vfmaddsub231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb6,0x08 = vfmaddsub231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xb6,0xca = vfmaddsub231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xb6,0x08 = vfmaddsub231ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0x97,0xca = vfmsubadd132pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0x97,0x08 = vfmsubadd132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x97,0xca = vfmsubadd132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x97,0x08 = vfmsubadd132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa7,0xca = vfmsubadd213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xa7,0x08 = vfmsubadd213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xa7,0xca = vfmsubadd213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xa7,0x08 = vfmsubadd213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb7,0xca = vfmsubadd231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xb7,0x08 = vfmsubadd231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xb7,0xca = vfmsubadd231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xb7,0x08 = vfmsubadd231ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0x9a,0xca = vfmsub132pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0x9a,0x08 = vfmsub132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x9a,0xca = vfmsub132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x9a,0x08 = vfmsub132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xaa,0xca = vfmsub213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xaa,0x08 = vfmsub213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xaa,0xca = vfmsub213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xaa,0x08 = vfmsub213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xba,0xca = vfmsub231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xba,0x08 = vfmsub231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xba,0xca = vfmsub231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xba,0x08 = vfmsub231ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0x9c,0xca = vfnmadd132pd %ymm2, %ymm5, %ymm1 // 0xc4,0xe2,0xd5,0x9c,0x08 = vfnmadd132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x9c,0xca = vfnmadd132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x9c,0x08 = vfnmadd132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xac,0xca = vfnmadd213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xac,0x08 = vfnmadd213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xac,0xca = vfnmadd213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xac,0x08 = vfnmadd213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xbc,0xca = vfnmadd231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xbc,0x08 = vfnmadd231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xbc,0xca = vfnmadd231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xbc,0x08 = vfnmadd231ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0x9e,0xca = vfnmsub132pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0x9e,0x08 = vfnmsub132pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0x9e,0xca = vfnmsub132ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0x9e,0x08 = vfnmsub132ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xae,0xca = vfnmsub213pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xae,0x08 = vfnmsub213pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xae,0xca = vfnmsub213ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xae,0x08 = vfnmsub213ps (%eax), %ymm5, %ymm1 0xc4,0xe2,0xd5,0xbe,0xca = vfnmsub231pd %ymm2, %ymm5, %ymm1 0xc4,0xe2,0xd5,0xbe,0x08 = vfnmsub231pd (%eax), %ymm5, %ymm1 0xc4,0xe2,0x55,0xbe,0xca = vfnmsub231ps %ymm2, %ymm5, %ymm1 0xc4,0xe2,0x55,0xbe,0x08 = vfnmsub231ps (%eax), %ymm5, %ymm1 capstone-sys-0.15.0/capstone/suite/MC/X86/x86-32-ms-inline-asm.s.cs000064400000000000000000000021670072674642500223340ustar 00000000000000# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0x8b,0x03 = movl (%ebx), %eax 0x89,0x4b,0x04 = movl %ecx, 4(%ebx) 0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax 0x8b,0x04,0x85,0x04,0x00,0x00,0x00 = movl 4(, %eax, 4), %eax 0x8b,0x04,0x06 = movl (%esi, %eax), %eax 0x8b,0x04,0x06 = movl (%esi, %eax), %eax 0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax 0x8b,0x04,0x86 = movl (%esi, %eax, 4), %eax 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 0x8b,0x44,0x06,0x04 = movl 4(%esi, %eax), %eax 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x04 = movl 4(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x08 = movl 8(%esi, %eax, 2), %eax 0x8b,0x44,0x46,0x10 = movl 16(%esi, %eax, 2), %eax 0x0f,0x18,0x40,0x40 = prefetchnta 64(%eax) 0x60 = pushal 0x61 = popal 0x60 = pushal 0x61 = popal capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-avx-clmul-encoding.s.cs000064400000000000000000000013730072674642500234440ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT // 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulhqhqdq %xmm12, %xmm10, %xmm11 // 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulhqhqdq (%rax), %xmm10, %xmm13 // 0xc4,0x43,0x29,0x44,0xdc,0x01 = vpclmulhqlqdq %xmm12, %xmm10, %xmm11 // 0xc4,0x63,0x29,0x44,0x28,0x01 = vpclmulhqlqdq (%rax), %xmm10, %xmm13 // 0xc4,0x43,0x29,0x44,0xdc,0x10 = vpclmullqhqdq %xmm12, %xmm10, %xmm11 // 0xc4,0x63,0x29,0x44,0x28,0x10 = vpclmullqhqdq (%rax), %xmm10, %xmm13 // 0xc4,0x43,0x29,0x44,0xdc,0x00 = vpclmullqlqdq %xmm12, %xmm10, %xmm11 // 0xc4,0x63,0x29,0x44,0x28,0x00 = vpclmullqlqdq (%rax), %xmm10, %xmm13 0xc4,0x43,0x29,0x44,0xdc,0x11 = vpclmulqdq $17, %xmm12, %xmm10, %xmm11 0xc4,0x63,0x29,0x44,0x28,0x11 = vpclmulqdq $17, (%rax), %xmm10, %xmm13 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-avx-encoding.s.cs000064400000000000000000002003550072674642500223330ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0xc4,0x41,0x32,0x58,0xd0 = vaddss %xmm8, %xmm9, %xmm10 0xc4,0x41,0x32,0x59,0xd0 = vmulss %xmm8, %xmm9, %xmm10 0xc4,0x41,0x32,0x5c,0xd0 = vsubss %xmm8, %xmm9, %xmm10 0xc4,0x41,0x32,0x5e,0xd0 = vdivss %xmm8, %xmm9, %xmm10 0xc4,0x41,0x33,0x58,0xd0 = vaddsd %xmm8, %xmm9, %xmm10 0xc4,0x41,0x33,0x59,0xd0 = vmulsd %xmm8, %xmm9, %xmm10 0xc4,0x41,0x33,0x5c,0xd0 = vsubsd %xmm8, %xmm9, %xmm10 0xc4,0x41,0x33,0x5e,0xd0 = vdivsd %xmm8, %xmm9, %xmm10 0xc5,0x2a,0x58,0x5c,0xd9,0xfc = vaddss -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2a,0x5c,0x5c,0xd9,0xfc = vsubss -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2a,0x59,0x5c,0xd9,0xfc = vmulss -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2a,0x5e,0x5c,0xd9,0xfc = vdivss -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2b,0x58,0x5c,0xd9,0xfc = vaddsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2b,0x5c,0x5c,0xd9,0xfc = vsubsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2b,0x59,0x5c,0xd9,0xfc = vmulsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x2b,0x5e,0x5c,0xd9,0xfc = vdivsd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc4,0x41,0x20,0x58,0xfa = vaddps %xmm10, %xmm11, %xmm15 0xc4,0x41,0x20,0x5c,0xfa = vsubps %xmm10, %xmm11, %xmm15 0xc4,0x41,0x20,0x59,0xfa = vmulps %xmm10, %xmm11, %xmm15 0xc4,0x41,0x20,0x5e,0xfa = vdivps %xmm10, %xmm11, %xmm15 0xc4,0x41,0x21,0x58,0xfa = vaddpd %xmm10, %xmm11, %xmm15 0xc4,0x41,0x21,0x5c,0xfa = vsubpd %xmm10, %xmm11, %xmm15 0xc4,0x41,0x21,0x59,0xfa = vmulpd %xmm10, %xmm11, %xmm15 0xc4,0x41,0x21,0x5e,0xfa = vdivpd %xmm10, %xmm11, %xmm15 0xc5,0x28,0x58,0x5c,0xd9,0xfc = vaddps -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x28,0x5c,0x5c,0xd9,0xfc = vsubps -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x28,0x59,0x5c,0xd9,0xfc = vmulps -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x28,0x5e,0x5c,0xd9,0xfc = vdivps -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x29,0x58,0x5c,0xd9,0xfc = vaddpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x29,0x5c,0x5c,0xd9,0xfc = vsubpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x29,0x59,0x5c,0xd9,0xfc = vmulpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc5,0x29,0x5e,0x5c,0xd9,0xfc = vdivpd -4(%rcx, %rbx, 8), %xmm10, %xmm11 0xc4,0x41,0x0a,0x5f,0xe2 = vmaxss %xmm10, %xmm14, %xmm12 0xc4,0x41,0x0b,0x5f,0xe2 = vmaxsd %xmm10, %xmm14, %xmm12 0xc4,0x41,0x0a,0x5d,0xe2 = vminss %xmm10, %xmm14, %xmm12 0xc4,0x41,0x0b,0x5d,0xe2 = vminsd %xmm10, %xmm14, %xmm12 0xc5,0x1a,0x5f,0x54,0xcb,0xfc = vmaxss -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x1b,0x5f,0x54,0xcb,0xfc = vmaxsd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x1a,0x5d,0x54,0xcb,0xfc = vminss -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x1b,0x5d,0x54,0xcb,0xfc = vminsd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc4,0x41,0x08,0x5f,0xe2 = vmaxps %xmm10, %xmm14, %xmm12 0xc4,0x41,0x09,0x5f,0xe2 = vmaxpd %xmm10, %xmm14, %xmm12 0xc4,0x41,0x08,0x5d,0xe2 = vminps %xmm10, %xmm14, %xmm12 0xc4,0x41,0x09,0x5d,0xe2 = vminpd %xmm10, %xmm14, %xmm12 0xc5,0x18,0x5f,0x54,0xcb,0xfc = vmaxps -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x19,0x5f,0x54,0xcb,0xfc = vmaxpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x18,0x5d,0x54,0xcb,0xfc = vminps -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x19,0x5d,0x54,0xcb,0xfc = vminpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc4,0x41,0x08,0x54,0xe2 = vandps %xmm10, %xmm14, %xmm12 0xc4,0x41,0x09,0x54,0xe2 = vandpd %xmm10, %xmm14, %xmm12 0xc5,0x18,0x54,0x54,0xcb,0xfc = vandps -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x19,0x54,0x54,0xcb,0xfc = vandpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc4,0x41,0x08,0x56,0xe2 = vorps %xmm10, %xmm14, %xmm12 0xc4,0x41,0x09,0x56,0xe2 = vorpd %xmm10, %xmm14, %xmm12 0xc5,0x18,0x56,0x54,0xcb,0xfc = vorps -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x19,0x56,0x54,0xcb,0xfc = vorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc4,0x41,0x08,0x57,0xe2 = vxorps %xmm10, %xmm14, %xmm12 0xc4,0x41,0x09,0x57,0xe2 = vxorpd %xmm10, %xmm14, %xmm12 0xc5,0x18,0x57,0x54,0xcb,0xfc = vxorps -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x19,0x57,0x54,0xcb,0xfc = vxorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc4,0x41,0x08,0x55,0xe2 = vandnps %xmm10, %xmm14, %xmm12 0xc4,0x41,0x09,0x55,0xe2 = vandnpd %xmm10, %xmm14, %xmm12 0xc5,0x18,0x55,0x54,0xcb,0xfc = vandnps -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x19,0x55,0x54,0xcb,0xfc = vandnpd -4(%rbx, %rcx, 8), %xmm12, %xmm10 0xc5,0x7a,0x10,0x54,0xcb,0xfc = vmovss -4(%rbx, %rcx, 8), %xmm10 0xc4,0x41,0x2a,0x10,0xfe = vmovss %xmm14, %xmm10, %xmm15 0xc5,0x7b,0x10,0x54,0xcb,0xfc = vmovsd -4(%rbx, %rcx, 8), %xmm10 0xc4,0x41,0x2b,0x10,0xfe = vmovsd %xmm14, %xmm10, %xmm15 0xc4,0x41,0x18,0x15,0xef = vunpckhps %xmm15, %xmm12, %xmm13 0xc4,0x41,0x19,0x15,0xef = vunpckhpd %xmm15, %xmm12, %xmm13 0xc4,0x41,0x18,0x14,0xef = vunpcklps %xmm15, %xmm12, %xmm13 0xc4,0x41,0x19,0x14,0xef = vunpcklpd %xmm15, %xmm12, %xmm13 0xc5,0x18,0x15,0x7c,0xcb,0xfc = vunpckhps -4(%rbx, %rcx, 8), %xmm12, %xmm15 0xc5,0x19,0x15,0x7c,0xcb,0xfc = vunpckhpd -4(%rbx, %rcx, 8), %xmm12, %xmm15 0xc5,0x18,0x14,0x7c,0xcb,0xfc = vunpcklps -4(%rbx, %rcx, 8), %xmm12, %xmm15 0xc5,0x19,0x14,0x7c,0xcb,0xfc = vunpcklpd -4(%rbx, %rcx, 8), %xmm12, %xmm15 0xc4,0x41,0x18,0xc2,0xfa,0x00 = vcmpeqps %xmm10, %xmm12, %xmm15 0xc5,0x18,0xc2,0x38,0x00 = vcmpeqps (%rax), %xmm12, %xmm15 0xc4,0x41,0x18,0xc2,0xfa,0x07 = vcmpordps %xmm10, %xmm12, %xmm15 0xc4,0x41,0x19,0xc2,0xfa,0x00 = vcmpeqpd %xmm10, %xmm12, %xmm15 0xc5,0x19,0xc2,0x38,0x00 = vcmpeqpd (%rax), %xmm12, %xmm15 0xc4,0x41,0x19,0xc2,0xfa,0x07 = vcmpordpd %xmm10, %xmm12, %xmm15 0xc4,0x41,0x18,0xc6,0xeb,0x08 = vshufps $8, %xmm11, %xmm12, %xmm13 0xc5,0x18,0xc6,0x6c,0xcb,0xfc,0x08 = vshufps $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x19,0xc6,0xeb,0x08 = vshufpd $8, %xmm11, %xmm12, %xmm13 0xc5,0x19,0xc6,0x6c,0xcb,0xfc,0x08 = vshufpd $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x00 = vcmpeqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x02 = vcmpleps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x01 = vcmpltps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x04 = vcmpneqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x06 = vcmpnleps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x05 = vcmpnltps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x07 = vcmpordps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x03 = vcmpunordps %xmm11, %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x02 = vcmpleps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnleps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordps -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x00 = vcmpeqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x02 = vcmplepd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x01 = vcmpltpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x04 = vcmpneqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x06 = vcmpnlepd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x05 = vcmpnltpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x07 = vcmpordpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x03 = vcmpunordpd %xmm11, %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x02 = vcmplepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnlepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x00 = vcmpeqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x02 = vcmpless %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x01 = vcmpltss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x04 = vcmpneqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x06 = vcmpnless %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x05 = vcmpnltss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x07 = vcmpordss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x03 = vcmpunordss %xmm11, %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x02 = vcmpless -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnless -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordss -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x00 = vcmpeqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x02 = vcmplesd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x01 = vcmpltsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x04 = vcmpneqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x06 = vcmpnlesd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x05 = vcmpnltsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x07 = vcmpordsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x03 = vcmpunordsd %xmm11, %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x02 = vcmplesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnlesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07 = vcmpordsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x08 = vcmpeq_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x09 = vcmpngeps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0a = vcmpngtps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0b = vcmpfalseps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0c = vcmpneq_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0d = vcmpgeps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0e = vcmpgtps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0f = vcmptrueps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x10 = vcmpeq_osps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x11 = vcmplt_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x12 = vcmple_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x13 = vcmpunord_sps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x14 = vcmpneq_usps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x15 = vcmpnlt_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x16 = vcmpnle_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x17 = vcmpord_sps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x18 = vcmpeq_usps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x19 = vcmpnge_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1a = vcmpngt_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1b = vcmpfalse_osps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1c = vcmpneq_osps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1d = vcmpge_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1e = vcmpgt_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1f = vcmptrue_usps %xmm11, %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngeps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalseps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgeps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtps -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptrueps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqps -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqps -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x08 = vcmpeq_uqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x09 = vcmpngepd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x0a = vcmpngtpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x0b = vcmpfalsepd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x0c = vcmpneq_oqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x0d = vcmpgepd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x0e = vcmpgtpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x0f = vcmptruepd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x10 = vcmpeq_ospd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x11 = vcmplt_oqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x12 = vcmple_oqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x13 = vcmpunord_spd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x14 = vcmpneq_uspd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x15 = vcmpnlt_uqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x16 = vcmpnle_uqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x17 = vcmpord_spd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x18 = vcmpeq_uspd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x19 = vcmpnge_uqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x1a = vcmpngt_uqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x1b = vcmpfalse_ospd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x1c = vcmpneq_ospd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x1d = vcmpge_oqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x1e = vcmpgt_oqpd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x19,0xc2,0xeb,0x1f = vcmptrue_uspd %xmm11, %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalsepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptruepd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x08 = vcmpeq_uqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x09 = vcmpngess %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x0a = vcmpngtss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x0b = vcmpfalsess %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x0c = vcmpneq_oqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x0d = vcmpgess %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x0e = vcmpgtss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x0f = vcmptruess %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x10 = vcmpeq_osss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x11 = vcmplt_oqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x12 = vcmple_oqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x13 = vcmpunord_sss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x14 = vcmpneq_usss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x15 = vcmpnlt_uqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x16 = vcmpnle_uqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x17 = vcmpord_sss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x18 = vcmpeq_usss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x19 = vcmpnge_uqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x1a = vcmpngt_uqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x1b = vcmpfalse_osss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x1c = vcmpneq_osss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x1d = vcmpge_oqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x1e = vcmpgt_oqss %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1a,0xc2,0xeb,0x1f = vcmptrue_usss %xmm11, %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngess -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalsess -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgess -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtss -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptruess -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqss -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqss -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x08 = vcmpeq_uqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x09 = vcmpngesd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x0a = vcmpngtsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x0b = vcmpfalsesd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x0c = vcmpneq_oqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x0d = vcmpgesd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x0e = vcmpgtsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x0f = vcmptruesd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x10 = vcmpeq_ossd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x11 = vcmplt_oqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x12 = vcmple_oqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x13 = vcmpunord_ssd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x14 = vcmpneq_ussd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x15 = vcmpnlt_uqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x16 = vcmpnle_uqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x17 = vcmpord_ssd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x18 = vcmpeq_ussd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x19 = vcmpnge_uqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x1a = vcmpngt_uqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x1b = vcmpfalse_ossd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x1c = vcmpneq_ossd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x1d = vcmpge_oqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x1e = vcmpgt_oqsd %xmm11, %xmm12, %xmm13 0xc4,0x41,0x1b,0xc2,0xeb,0x1f = vcmptrue_ussd %xmm11, %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x08 = vcmpeq_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x09 = vcmpngesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0a = vcmpngtsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0b = vcmpfalsesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0c = vcmpneq_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0d = vcmpgesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x0e = vcmpgtsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x0f = vcmptruesd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x10 = vcmpeq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x11 = vcmplt_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x12 = vcmple_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x13 = vcmpunord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x14 = vcmpneq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x15 = vcmpnlt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x16 = vcmpnle_uqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x17 = vcmpord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x18 = vcmpeq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x19 = vcmpnge_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1a = vcmpngt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1b = vcmpfalse_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1c = vcmpneq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1d = vcmpge_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x1e = vcmpgt_oqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2 0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x1f = vcmptrue_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13 0xc4,0x41,0x78,0x2e,0xe3 = vucomiss %xmm11, %xmm12 0xc5,0x78,0x2e,0x20 = vucomiss (%rax), %xmm12 0xc4,0x41,0x78,0x2f,0xe3 = vcomiss %xmm11, %xmm12 0xc5,0x78,0x2f,0x20 = vcomiss (%rax), %xmm12 0xc4,0x41,0x79,0x2e,0xe3 = vucomisd %xmm11, %xmm12 0xc5,0x79,0x2e,0x20 = vucomisd (%rax), %xmm12 0xc4,0x41,0x79,0x2f,0xe3 = vcomisd %xmm11, %xmm12 0xc5,0x79,0x2f,0x20 = vcomisd (%rax), %xmm12 0xc5,0xfa,0x2c,0x01 = vcvttss2si (%rcx), %eax 0xc5,0x22,0x2a,0x20 = vcvtsi2ssl (%rax), %xmm11, %xmm12 0xc5,0x22,0x2a,0x20 = vcvtsi2ssl (%rax), %xmm11, %xmm12 0xc5,0xfb,0x2c,0x01 = vcvttsd2si (%rcx), %eax 0xc5,0x23,0x2a,0x20 = vcvtsi2sdl (%rax), %xmm11, %xmm12 0xc5,0x23,0x2a,0x20 = vcvtsi2sdl (%rax), %xmm11, %xmm12 0xc5,0x78,0x28,0x20 = vmovaps (%rax), %xmm12 0xc4,0x41,0x78,0x28,0xe3 = vmovaps %xmm11, %xmm12 0xc5,0x78,0x29,0x18 = vmovaps %xmm11, (%rax) 0xc5,0x79,0x28,0x20 = vmovapd (%rax), %xmm12 0xc4,0x41,0x79,0x28,0xe3 = vmovapd %xmm11, %xmm12 0xc5,0x79,0x29,0x18 = vmovapd %xmm11, (%rax) 0xc5,0x78,0x10,0x20 = vmovups (%rax), %xmm12 0xc4,0x41,0x78,0x10,0xe3 = vmovups %xmm11, %xmm12 0xc5,0x78,0x11,0x18 = vmovups %xmm11, (%rax) 0xc5,0x79,0x10,0x20 = vmovupd (%rax), %xmm12 0xc4,0x41,0x79,0x10,0xe3 = vmovupd %xmm11, %xmm12 0xc5,0x79,0x11,0x18 = vmovupd %xmm11, (%rax) 0xc5,0x78,0x13,0x18 = vmovlps %xmm11, (%rax) 0xc5,0x18,0x12,0x28 = vmovlps (%rax), %xmm12, %xmm13 0xc5,0x79,0x13,0x18 = vmovlpd %xmm11, (%rax) 0xc5,0x19,0x12,0x28 = vmovlpd (%rax), %xmm12, %xmm13 0xc5,0x78,0x17,0x18 = vmovhps %xmm11, (%rax) 0xc5,0x18,0x16,0x28 = vmovhps (%rax), %xmm12, %xmm13 0xc5,0x79,0x17,0x18 = vmovhpd %xmm11, (%rax) 0xc5,0x19,0x16,0x28 = vmovhpd (%rax), %xmm12, %xmm13 0xc4,0x41,0x18,0x16,0xeb = vmovlhps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0x12,0xeb = vmovhlps %xmm11, %xmm12, %xmm13 0xc4,0xc1,0x7a,0x2d,0xc3 = vcvtss2si %xmm11, %eax 0xc5,0xfa,0x2d,0x18 = vcvtss2si (%rax), %ebx 0xc4,0x41,0x78,0x5b,0xe2 = vcvtdq2ps %xmm10, %xmm12 0xc5,0x78,0x5b,0x20 = vcvtdq2ps (%rax), %xmm12 0xc4,0x41,0x13,0x5a,0xd4 = vcvtsd2ss %xmm12, %xmm13, %xmm10 0xc5,0x13,0x5a,0x10 = vcvtsd2ss (%rax), %xmm13, %xmm10 0xc4,0x41,0x79,0x5b,0xdc = vcvtps2dq %xmm12, %xmm11 0xc5,0x79,0x5b,0x18 = vcvtps2dq (%rax), %xmm11 0xc4,0x41,0x12,0x5a,0xd4 = vcvtss2sd %xmm12, %xmm13, %xmm10 0xc5,0x12,0x5a,0x10 = vcvtss2sd (%rax), %xmm13, %xmm10 0xc4,0x41,0x78,0x5b,0xd5 = vcvtdq2ps %xmm13, %xmm10 0xc5,0x78,0x5b,0x29 = vcvtdq2ps (%rcx), %xmm13 0xc4,0x41,0x7a,0x5b,0xdc = vcvttps2dq %xmm12, %xmm11 0xc5,0x7a,0x5b,0x18 = vcvttps2dq (%rax), %xmm11 0xc4,0x41,0x78,0x5a,0xdc = vcvtps2pd %xmm12, %xmm11 0xc5,0x78,0x5a,0x18 = vcvtps2pd (%rax), %xmm11 0xc4,0x41,0x79,0x5a,0xdc = vcvtpd2ps %xmm12, %xmm11 0xc4,0x41,0x79,0x51,0xe3 = vsqrtpd %xmm11, %xmm12 0xc5,0x79,0x51,0x20 = vsqrtpd (%rax), %xmm12 0xc4,0x41,0x78,0x51,0xe3 = vsqrtps %xmm11, %xmm12 0xc5,0x78,0x51,0x20 = vsqrtps (%rax), %xmm12 0xc4,0x41,0x1b,0x51,0xd3 = vsqrtsd %xmm11, %xmm12, %xmm10 0xc5,0x1b,0x51,0x10 = vsqrtsd (%rax), %xmm12, %xmm10 0xc4,0x41,0x1a,0x51,0xd3 = vsqrtss %xmm11, %xmm12, %xmm10 0xc5,0x1a,0x51,0x10 = vsqrtss (%rax), %xmm12, %xmm10 0xc4,0x41,0x78,0x52,0xe3 = vrsqrtps %xmm11, %xmm12 0xc5,0x78,0x52,0x20 = vrsqrtps (%rax), %xmm12 0xc4,0x41,0x1a,0x52,0xd3 = vrsqrtss %xmm11, %xmm12, %xmm10 0xc5,0x1a,0x52,0x10 = vrsqrtss (%rax), %xmm12, %xmm10 0xc4,0x41,0x78,0x53,0xe3 = vrcpps %xmm11, %xmm12 0xc5,0x78,0x53,0x20 = vrcpps (%rax), %xmm12 0xc4,0x41,0x1a,0x53,0xd3 = vrcpss %xmm11, %xmm12, %xmm10 0xc5,0x1a,0x53,0x10 = vrcpss (%rax), %xmm12, %xmm10 0xc5,0x79,0xe7,0x18 = vmovntdq %xmm11, (%rax) 0xc5,0x79,0x2b,0x18 = vmovntpd %xmm11, (%rax) 0xc5,0x78,0x2b,0x18 = vmovntps %xmm11, (%rax) 0xc5,0xf8,0xae,0x15,0xfc,0xff,0xff,0xff = vldmxcsr -4(%rip) 0xc5,0xf8,0xae,0x5c,0x24,0xfc = vstmxcsr -4(%rsp) 0xc4,0x41,0x19,0xf8,0xeb = vpsubb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf8,0x28 = vpsubb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xf9,0xeb = vpsubw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf9,0x28 = vpsubw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xfa,0xeb = vpsubd %xmm11, %xmm12, %xmm13 0xc5,0x19,0xfa,0x28 = vpsubd (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xfb,0xeb = vpsubq %xmm11, %xmm12, %xmm13 0xc5,0x19,0xfb,0x28 = vpsubq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe8,0xeb = vpsubsb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe8,0x28 = vpsubsb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe9,0xeb = vpsubsw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe9,0x28 = vpsubsw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd8,0xeb = vpsubusb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd8,0x28 = vpsubusb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd9,0xeb = vpsubusw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd9,0x28 = vpsubusw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xfc,0xeb = vpaddb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xfc,0x28 = vpaddb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xfd,0xeb = vpaddw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xfd,0x28 = vpaddw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xfe,0xeb = vpaddd %xmm11, %xmm12, %xmm13 0xc5,0x19,0xfe,0x28 = vpaddd (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd4,0xeb = vpaddq %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd4,0x28 = vpaddq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xec,0xeb = vpaddsb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xec,0x28 = vpaddsb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xed,0xeb = vpaddsw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xed,0x28 = vpaddsw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xdc,0xeb = vpaddusb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xdc,0x28 = vpaddusb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xdd,0xeb = vpaddusw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xdd,0x28 = vpaddusw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe4,0xeb = vpmulhuw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe4,0x28 = vpmulhuw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe5,0xeb = vpmulhw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe5,0x28 = vpmulhw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd5,0xeb = vpmullw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd5,0x28 = vpmullw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xf4,0xeb = vpmuludq %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf4,0x28 = vpmuludq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe0,0xeb = vpavgb %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe0,0x28 = vpavgb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe3,0xeb = vpavgw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe3,0x28 = vpavgw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xea,0xeb = vpminsw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xea,0x28 = vpminsw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xda,0xeb = vpminub %xmm11, %xmm12, %xmm13 0xc5,0x19,0xda,0x28 = vpminub (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xee,0xeb = vpmaxsw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xee,0x28 = vpmaxsw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xde,0xeb = vpmaxub %xmm11, %xmm12, %xmm13 0xc5,0x19,0xde,0x28 = vpmaxub (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xf6,0xeb = vpsadbw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf6,0x28 = vpsadbw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xf1,0xeb = vpsllw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf1,0x28 = vpsllw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xf2,0xeb = vpslld %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf2,0x28 = vpslld (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xf3,0xeb = vpsllq %xmm11, %xmm12, %xmm13 0xc5,0x19,0xf3,0x28 = vpsllq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe1,0xeb = vpsraw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe1,0x28 = vpsraw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xe2,0xeb = vpsrad %xmm11, %xmm12, %xmm13 0xc5,0x19,0xe2,0x28 = vpsrad (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd1,0xeb = vpsrlw %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd1,0x28 = vpsrlw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd2,0xeb = vpsrld %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd2,0x28 = vpsrld (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xd3,0xeb = vpsrlq %xmm11, %xmm12, %xmm13 0xc5,0x19,0xd3,0x28 = vpsrlq (%rax), %xmm12, %xmm13 0xc4,0xc1,0x11,0x72,0xf4,0x0a = vpslld $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x73,0xfc,0x0a = vpslldq $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x73,0xf4,0x0a = vpsllq $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x71,0xf4,0x0a = vpsllw $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x72,0xe4,0x0a = vpsrad $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x71,0xe4,0x0a = vpsraw $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x72,0xd4,0x0a = vpsrld $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x73,0xdc,0x0a = vpsrldq $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x73,0xd4,0x0a = vpsrlq $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x71,0xd4,0x0a = vpsrlw $10, %xmm12, %xmm13 0xc4,0xc1,0x11,0x72,0xf4,0x0a = vpslld $10, %xmm12, %xmm13 0xc4,0x41,0x19,0xdb,0xeb = vpand %xmm11, %xmm12, %xmm13 0xc5,0x19,0xdb,0x28 = vpand (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xeb,0xeb = vpor %xmm11, %xmm12, %xmm13 0xc5,0x19,0xeb,0x28 = vpor (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xef,0xeb = vpxor %xmm11, %xmm12, %xmm13 0xc5,0x19,0xef,0x28 = vpxor (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0xdf,0xeb = vpandn %xmm11, %xmm12, %xmm13 0xc5,0x19,0xdf,0x28 = vpandn (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x74,0xeb = vpcmpeqb %xmm11, %xmm12, %xmm13 0xc5,0x19,0x74,0x28 = vpcmpeqb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x75,0xeb = vpcmpeqw %xmm11, %xmm12, %xmm13 0xc5,0x19,0x75,0x28 = vpcmpeqw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x76,0xeb = vpcmpeqd %xmm11, %xmm12, %xmm13 0xc5,0x19,0x76,0x28 = vpcmpeqd (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x64,0xeb = vpcmpgtb %xmm11, %xmm12, %xmm13 0xc5,0x19,0x64,0x28 = vpcmpgtb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x65,0xeb = vpcmpgtw %xmm11, %xmm12, %xmm13 0xc5,0x19,0x65,0x28 = vpcmpgtw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x66,0xeb = vpcmpgtd %xmm11, %xmm12, %xmm13 0xc5,0x19,0x66,0x28 = vpcmpgtd (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x63,0xeb = vpacksswb %xmm11, %xmm12, %xmm13 0xc5,0x19,0x63,0x28 = vpacksswb (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x6b,0xeb = vpackssdw %xmm11, %xmm12, %xmm13 0xc5,0x19,0x6b,0x28 = vpackssdw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x67,0xeb = vpackuswb %xmm11, %xmm12, %xmm13 0xc5,0x19,0x67,0x28 = vpackuswb (%rax), %xmm12, %xmm13 0xc4,0x41,0x79,0x70,0xec,0x04 = vpshufd $4, %xmm12, %xmm13 0xc5,0x79,0x70,0x28,0x04 = vpshufd $4, (%rax), %xmm13 0xc4,0x41,0x7a,0x70,0xec,0x04 = vpshufhw $4, %xmm12, %xmm13 0xc5,0x7a,0x70,0x28,0x04 = vpshufhw $4, (%rax), %xmm13 0xc4,0x41,0x7b,0x70,0xec,0x04 = vpshuflw $4, %xmm12, %xmm13 0xc5,0x7b,0x70,0x28,0x04 = vpshuflw $4, (%rax), %xmm13 0xc4,0x41,0x19,0x60,0xeb = vpunpcklbw %xmm11, %xmm12, %xmm13 0xc5,0x19,0x60,0x28 = vpunpcklbw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x61,0xeb = vpunpcklwd %xmm11, %xmm12, %xmm13 0xc5,0x19,0x61,0x28 = vpunpcklwd (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x62,0xeb = vpunpckldq %xmm11, %xmm12, %xmm13 0xc5,0x19,0x62,0x28 = vpunpckldq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x6c,0xeb = vpunpcklqdq %xmm11, %xmm12, %xmm13 0xc5,0x19,0x6c,0x28 = vpunpcklqdq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x68,0xeb = vpunpckhbw %xmm11, %xmm12, %xmm13 0xc5,0x19,0x68,0x28 = vpunpckhbw (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x69,0xeb = vpunpckhwd %xmm11, %xmm12, %xmm13 0xc5,0x19,0x69,0x28 = vpunpckhwd (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x6a,0xeb = vpunpckhdq %xmm11, %xmm12, %xmm13 0xc5,0x19,0x6a,0x28 = vpunpckhdq (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x6d,0xeb = vpunpckhqdq %xmm11, %xmm12, %xmm13 0xc5,0x19,0x6d,0x28 = vpunpckhqdq (%rax), %xmm12, %xmm13 0xc5,0x19,0xc4,0xe8,0x07 = vpinsrw $7, %eax, %xmm12, %xmm13 0xc5,0x19,0xc4,0x28,0x07 = vpinsrw $7, (%rax), %xmm12, %xmm13 0xc4,0xc1,0x79,0xc5,0xc4,0x07 = vpextrw $7, %xmm12, %eax 0xc4,0xc1,0x79,0xd7,0xc4 = vpmovmskb %xmm12, %eax 0xc4,0x41,0x79,0xf7,0xfe = vmaskmovdqu %xmm14, %xmm15 0xc5,0x79,0x6e,0xf0 = vmovd %eax, %xmm14 0xc5,0x79,0x6e,0x30 = vmovd (%rax), %xmm14 0xc5,0x79,0x7e,0x30 = vmovd %xmm14, (%rax) 0xc4,0x61,0xf9,0x6e,0xf0 = vmovq %rax, %xmm14 0xc4,0xe1,0xf9,0x7e,0xc0 = vmovq %xmm0, %rax 0xc5,0x79,0xd6,0x30 = vmovq %xmm14, (%rax) 0xc4,0x41,0x7a,0x7e,0xe6 = vmovq %xmm14, %xmm12 0xc5,0x7a,0x7e,0x30 = vmovq (%rax), %xmm14 0xc4,0x61,0xf9,0x6e,0xf0 = vmovq %rax, %xmm14 0xc4,0x61,0xf9,0x7e,0xf0 = vmovq %xmm14, %rax 0xc4,0x41,0x7b,0xe6,0xe3 = vcvtpd2dq %xmm11, %xmm12 0xc4,0x41,0x7a,0xe6,0xe3 = vcvtdq2pd %xmm11, %xmm12 0xc5,0x7a,0xe6,0x20 = vcvtdq2pd (%rax), %xmm12 0xc4,0x41,0x7a,0x16,0xe3 = vmovshdup %xmm11, %xmm12 0xc5,0x7a,0x16,0x20 = vmovshdup (%rax), %xmm12 0xc4,0x41,0x7a,0x12,0xe3 = vmovsldup %xmm11, %xmm12 0xc5,0x7a,0x12,0x20 = vmovsldup (%rax), %xmm12 0xc4,0x41,0x7b,0x12,0xe3 = vmovddup %xmm11, %xmm12 0xc5,0x7b,0x12,0x20 = vmovddup (%rax), %xmm12 0xc4,0x41,0x1b,0xd0,0xeb = vaddsubps %xmm11, %xmm12, %xmm13 0xc5,0x23,0xd0,0x20 = vaddsubps (%rax), %xmm11, %xmm12 0xc4,0x41,0x19,0xd0,0xeb = vaddsubpd %xmm11, %xmm12, %xmm13 0xc5,0x21,0xd0,0x20 = vaddsubpd (%rax), %xmm11, %xmm12 0xc4,0x41,0x1b,0x7c,0xeb = vhaddps %xmm11, %xmm12, %xmm13 0xc5,0x1b,0x7c,0x28 = vhaddps (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x7c,0xeb = vhaddpd %xmm11, %xmm12, %xmm13 0xc5,0x19,0x7c,0x28 = vhaddpd (%rax), %xmm12, %xmm13 0xc4,0x41,0x1b,0x7d,0xeb = vhsubps %xmm11, %xmm12, %xmm13 0xc5,0x1b,0x7d,0x28 = vhsubps (%rax), %xmm12, %xmm13 0xc4,0x41,0x19,0x7d,0xeb = vhsubpd %xmm11, %xmm12, %xmm13 0xc5,0x19,0x7d,0x28 = vhsubpd (%rax), %xmm12, %xmm13 0xc4,0x42,0x79,0x1c,0xe3 = vpabsb %xmm11, %xmm12 0xc4,0x62,0x79,0x1c,0x20 = vpabsb (%rax), %xmm12 0xc4,0x42,0x79,0x1d,0xe3 = vpabsw %xmm11, %xmm12 0xc4,0x62,0x79,0x1d,0x20 = vpabsw (%rax), %xmm12 0xc4,0x42,0x79,0x1e,0xe3 = vpabsd %xmm11, %xmm12 0xc4,0x62,0x79,0x1e,0x20 = vpabsd (%rax), %xmm12 0xc4,0x42,0x19,0x01,0xeb = vphaddw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x01,0x28 = vphaddw (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x02,0xeb = vphaddd %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x02,0x28 = vphaddd (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x03,0xeb = vphaddsw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x03,0x28 = vphaddsw (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x05,0xeb = vphsubw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x05,0x28 = vphsubw (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x06,0xeb = vphsubd %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x06,0x28 = vphsubd (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x07,0xeb = vphsubsw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x07,0x28 = vphsubsw (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x04,0xeb = vpmaddubsw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x04,0x28 = vpmaddubsw (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x00,0xeb = vpshufb %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x00,0x28 = vpshufb (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x08,0xeb = vpsignb %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x08,0x28 = vpsignb (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x09,0xeb = vpsignw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x09,0x28 = vpsignw (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x0a,0xeb = vpsignd %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x0a,0x28 = vpsignd (%rax), %xmm12, %xmm13 0xc4,0x42,0x19,0x0b,0xeb = vpmulhrsw %xmm11, %xmm12, %xmm13 0xc4,0x62,0x19,0x0b,0x28 = vpmulhrsw (%rax), %xmm12, %xmm13 0xc4,0x43,0x19,0x0f,0xeb,0x07 = vpalignr $7, %xmm11, %xmm12, %xmm13 0xc4,0x63,0x19,0x0f,0x28,0x07 = vpalignr $7, (%rax), %xmm12, %xmm13 0xc4,0x43,0x19,0x0b,0xeb,0x07 = vroundsd $7, %xmm11, %xmm12, %xmm13 0xc4,0x63,0x19,0x0b,0x28,0x07 = vroundsd $7, (%rax), %xmm12, %xmm13 0xc4,0x43,0x19,0x0a,0xeb,0x07 = vroundss $7, %xmm11, %xmm12, %xmm13 0xc4,0x63,0x19,0x0a,0x28,0x07 = vroundss $7, (%rax), %xmm12, %xmm13 0xc4,0x43,0x79,0x09,0xec,0x07 = vroundpd $7, %xmm12, %xmm13 0xc4,0x63,0x79,0x09,0x28,0x07 = vroundpd $7, (%rax), %xmm13 0xc4,0x43,0x79,0x08,0xec,0x07 = vroundps $7, %xmm12, %xmm13 0xc4,0x63,0x79,0x08,0x28,0x07 = vroundps $7, (%rax), %xmm13 0xc4,0x42,0x79,0x41,0xec = vphminposuw %xmm12, %xmm13 0xc4,0x62,0x79,0x41,0x20 = vphminposuw (%rax), %xmm12 0xc4,0x42,0x11,0x2b,0xdc = vpackusdw %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x2b,0x28 = vpackusdw (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x29,0xdc = vpcmpeqq %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x29,0x28 = vpcmpeqq (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x38,0xdc = vpminsb %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x38,0x28 = vpminsb (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x39,0xdc = vpminsd %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x39,0x28 = vpminsd (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x3b,0xdc = vpminud %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x3b,0x28 = vpminud (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x3a,0xdc = vpminuw %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x3a,0x28 = vpminuw (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x3c,0xdc = vpmaxsb %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x3c,0x28 = vpmaxsb (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x3d,0xdc = vpmaxsd %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x3d,0x28 = vpmaxsd (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x3f,0xdc = vpmaxud %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x3f,0x28 = vpmaxud (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x3e,0xdc = vpmaxuw %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x3e,0x28 = vpmaxuw (%rax), %xmm12, %xmm13 0xc4,0x42,0x11,0x28,0xdc = vpmuldq %xmm12, %xmm13, %xmm11 0xc4,0x62,0x19,0x28,0x28 = vpmuldq (%rax), %xmm12, %xmm13 0xc4,0x42,0x51,0x40,0xdc = vpmulld %xmm12, %xmm5, %xmm11 0xc4,0x62,0x51,0x40,0x28 = vpmulld (%rax), %xmm5, %xmm13 0xc4,0x43,0x51,0x0c,0xdc,0x03 = vblendps $3, %xmm12, %xmm5, %xmm11 0xc4,0x63,0x51,0x0c,0x18,0x03 = vblendps $3, (%rax), %xmm5, %xmm11 0xc4,0x43,0x51,0x0d,0xdc,0x03 = vblendpd $3, %xmm12, %xmm5, %xmm11 0xc4,0x63,0x51,0x0d,0x18,0x03 = vblendpd $3, (%rax), %xmm5, %xmm11 0xc4,0x43,0x51,0x0e,0xdc,0x03 = vpblendw $3, %xmm12, %xmm5, %xmm11 0xc4,0x63,0x51,0x0e,0x18,0x03 = vpblendw $3, (%rax), %xmm5, %xmm11 0xc4,0x43,0x51,0x42,0xdc,0x03 = vmpsadbw $3, %xmm12, %xmm5, %xmm11 0xc4,0x63,0x51,0x42,0x18,0x03 = vmpsadbw $3, (%rax), %xmm5, %xmm11 0xc4,0x43,0x51,0x40,0xdc,0x03 = vdpps $3, %xmm12, %xmm5, %xmm11 0xc4,0x63,0x51,0x40,0x18,0x03 = vdpps $3, (%rax), %xmm5, %xmm11 0xc4,0x43,0x51,0x41,0xdc,0x03 = vdppd $3, %xmm12, %xmm5, %xmm11 0xc4,0x63,0x51,0x41,0x18,0x03 = vdppd $3, (%rax), %xmm5, %xmm11 0xc4,0x63,0x21,0x4b,0xed,0xc0 = vblendvpd %xmm12, %xmm5, %xmm11, %xmm13 0xc4,0x63,0x21,0x4b,0x28,0xc0 = vblendvpd %xmm12, (%rax), %xmm11, %xmm13 0xc4,0x63,0x21,0x4a,0xed,0xc0 = vblendvps %xmm12, %xmm5, %xmm11, %xmm13 0xc4,0x63,0x21,0x4a,0x28,0xc0 = vblendvps %xmm12, (%rax), %xmm11, %xmm13 0xc4,0x63,0x21,0x4c,0xed,0xc0 = vpblendvb %xmm12, %xmm5, %xmm11, %xmm13 0xc4,0x63,0x21,0x4c,0x28,0xc0 = vpblendvb %xmm12, (%rax), %xmm11, %xmm13 0xc4,0x42,0x79,0x20,0xd4 = vpmovsxbw %xmm12, %xmm10 0xc4,0x62,0x79,0x20,0x20 = vpmovsxbw (%rax), %xmm12 0xc4,0x42,0x79,0x23,0xd4 = vpmovsxwd %xmm12, %xmm10 0xc4,0x62,0x79,0x23,0x20 = vpmovsxwd (%rax), %xmm12 0xc4,0x42,0x79,0x25,0xd4 = vpmovsxdq %xmm12, %xmm10 0xc4,0x62,0x79,0x25,0x20 = vpmovsxdq (%rax), %xmm12 0xc4,0x42,0x79,0x30,0xd4 = vpmovzxbw %xmm12, %xmm10 0xc4,0x62,0x79,0x30,0x20 = vpmovzxbw (%rax), %xmm12 0xc4,0x42,0x79,0x33,0xd4 = vpmovzxwd %xmm12, %xmm10 0xc4,0x62,0x79,0x33,0x20 = vpmovzxwd (%rax), %xmm12 0xc4,0x42,0x79,0x35,0xd4 = vpmovzxdq %xmm12, %xmm10 0xc4,0x62,0x79,0x35,0x20 = vpmovzxdq (%rax), %xmm12 0xc4,0x42,0x79,0x22,0xd4 = vpmovsxbq %xmm12, %xmm10 0xc4,0x62,0x79,0x22,0x20 = vpmovsxbq (%rax), %xmm12 0xc4,0x42,0x79,0x32,0xd4 = vpmovzxbq %xmm12, %xmm10 0xc4,0x62,0x79,0x32,0x20 = vpmovzxbq (%rax), %xmm12 0xc4,0x42,0x79,0x21,0xd4 = vpmovsxbd %xmm12, %xmm10 0xc4,0x62,0x79,0x21,0x20 = vpmovsxbd (%rax), %xmm12 0xc4,0x42,0x79,0x24,0xd4 = vpmovsxwq %xmm12, %xmm10 0xc4,0x62,0x79,0x24,0x20 = vpmovsxwq (%rax), %xmm12 0xc4,0x42,0x79,0x31,0xd4 = vpmovzxbd %xmm12, %xmm10 0xc4,0x62,0x79,0x31,0x20 = vpmovzxbd (%rax), %xmm12 0xc4,0x42,0x79,0x34,0xd4 = vpmovzxwq %xmm12, %xmm10 0xc4,0x62,0x79,0x34,0x20 = vpmovzxwq (%rax), %xmm12 0xc4,0xc1,0x79,0xc5,0xc4,0x07 = vpextrw $7, %xmm12, %eax 0xc4,0x63,0x79,0x15,0x20,0x07 = vpextrw $7, %xmm12, (%rax) 0xc4,0x63,0x79,0x16,0xe0,0x07 = vpextrd $7, %xmm12, %eax 0xc4,0x63,0x79,0x16,0x20,0x07 = vpextrd $7, %xmm12, (%rax) 0xc4,0x63,0x79,0x14,0xe0,0x07 = vpextrb $7, %xmm12, %eax 0xc4,0x63,0x79,0x14,0x20,0x07 = vpextrb $7, %xmm12, (%rax) 0xc4,0x63,0xf9,0x16,0xe1,0x07 = vpextrq $7, %xmm12, %rcx 0xc4,0x63,0xf9,0x16,0x21,0x07 = vpextrq $7, %xmm12, (%rcx) 0xc4,0x63,0x79,0x17,0x20,0x07 = vextractps $7, %xmm12, (%rax) 0xc4,0x63,0x79,0x17,0xe0,0x07 = vextractps $7, %xmm12, %eax 0xc5,0x19,0xc4,0xd0,0x07 = vpinsrw $7, %eax, %xmm12, %xmm10 0xc5,0x19,0xc4,0x10,0x07 = vpinsrw $7, (%rax), %xmm12, %xmm10 0xc4,0x63,0x19,0x20,0xd0,0x07 = vpinsrb $7, %eax, %xmm12, %xmm10 0xc4,0x63,0x19,0x20,0x10,0x07 = vpinsrb $7, (%rax), %xmm12, %xmm10 0xc4,0x63,0x19,0x22,0xd0,0x07 = vpinsrd $7, %eax, %xmm12, %xmm10 0xc4,0x63,0x19,0x22,0x10,0x07 = vpinsrd $7, (%rax), %xmm12, %xmm10 0xc4,0x63,0x99,0x22,0xd0,0x07 = vpinsrq $7, %rax, %xmm12, %xmm10 0xc4,0x63,0x99,0x22,0x10,0x07 = vpinsrq $7, (%rax), %xmm12, %xmm10 0xc4,0x43,0x29,0x21,0xdc,0x07 = vinsertps $7, %xmm12, %xmm10, %xmm11 0xc4,0x63,0x29,0x21,0x18,0x07 = vinsertps $7, (%rax), %xmm10, %xmm11 0xc4,0x42,0x79,0x17,0xd4 = vptest %xmm12, %xmm10 0xc4,0x62,0x79,0x17,0x20 = vptest (%rax), %xmm12 0xc4,0x62,0x79,0x2a,0x20 = vmovntdqa (%rax), %xmm12 0xc4,0x42,0x29,0x37,0xdc = vpcmpgtq %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x37,0x28 = vpcmpgtq (%rax), %xmm10, %xmm13 0xc4,0x43,0x79,0x62,0xd4,0x07 = vpcmpistrm $7, %xmm12, %xmm10 0xc4,0x63,0x79,0x62,0x10,0x07 = vpcmpistrm $7, (%rax), %xmm10 0xc4,0x43,0x79,0x60,0xd4,0x07 = vpcmpestrm $7, %xmm12, %xmm10 0xc4,0x63,0x79,0x60,0x10,0x07 = vpcmpestrm $7, (%rax), %xmm10 0xc4,0x43,0x79,0x63,0xd4,0x07 = vpcmpistri $7, %xmm12, %xmm10 0xc4,0x63,0x79,0x63,0x10,0x07 = vpcmpistri $7, (%rax), %xmm10 0xc4,0x43,0x79,0x61,0xd4,0x07 = vpcmpestri $7, %xmm12, %xmm10 0xc4,0x63,0x79,0x61,0x10,0x07 = vpcmpestri $7, (%rax), %xmm10 0xc4,0x42,0x79,0xdb,0xd4 = vaesimc %xmm12, %xmm10 0xc4,0x62,0x79,0xdb,0x20 = vaesimc (%rax), %xmm12 0xc4,0x42,0x29,0xdc,0xdc = vaesenc %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xdc,0x28 = vaesenc (%rax), %xmm10, %xmm13 0xc4,0x42,0x29,0xdd,0xdc = vaesenclast %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xdd,0x28 = vaesenclast (%rax), %xmm10, %xmm13 0xc4,0x42,0x29,0xde,0xdc = vaesdec %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xde,0x28 = vaesdec (%rax), %xmm10, %xmm13 0xc4,0x42,0x29,0xdf,0xdc = vaesdeclast %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xdf,0x28 = vaesdeclast (%rax), %xmm10, %xmm13 0xc4,0x43,0x79,0xdf,0xd4,0x07 = vaeskeygenassist $7, %xmm12, %xmm10 0xc4,0x63,0x79,0xdf,0x10,0x07 = vaeskeygenassist $7, (%rax), %xmm10 0xc4,0x41,0x18,0xc2,0xeb,0x08 = vcmpeq_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x09 = vcmpngeps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0a = vcmpngtps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0b = vcmpfalseps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0c = vcmpneq_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0d = vcmpgeps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0e = vcmpgtps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x0f = vcmptrueps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x10 = vcmpeq_osps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x11 = vcmplt_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x12 = vcmple_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x13 = vcmpunord_sps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x14 = vcmpneq_usps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x15 = vcmpnlt_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x16 = vcmpnle_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x17 = vcmpord_sps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x18 = vcmpeq_usps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x19 = vcmpnge_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1a = vcmpngt_uqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1b = vcmpfalse_osps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1c = vcmpneq_osps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1d = vcmpge_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1e = vcmpgt_oqps %xmm11, %xmm12, %xmm13 0xc4,0x41,0x18,0xc2,0xeb,0x1f = vcmptrue_usps %xmm11, %xmm12, %xmm13 0xc5,0x7c,0x28,0x20 = vmovaps (%rax), %ymm12 0xc4,0x41,0x7c,0x28,0xe3 = vmovaps %ymm11, %ymm12 0xc5,0x7c,0x29,0x18 = vmovaps %ymm11, (%rax) 0xc5,0x7d,0x28,0x20 = vmovapd (%rax), %ymm12 0xc4,0x41,0x7d,0x28,0xe3 = vmovapd %ymm11, %ymm12 0xc5,0x7d,0x29,0x18 = vmovapd %ymm11, (%rax) 0xc5,0x7c,0x10,0x20 = vmovups (%rax), %ymm12 0xc4,0x41,0x7c,0x10,0xe3 = vmovups %ymm11, %ymm12 0xc5,0x7c,0x11,0x18 = vmovups %ymm11, (%rax) 0xc5,0x7d,0x10,0x20 = vmovupd (%rax), %ymm12 0xc4,0x41,0x7d,0x10,0xe3 = vmovupd %ymm11, %ymm12 0xc5,0x7d,0x11,0x18 = vmovupd %ymm11, (%rax) 0xc4,0xc1,0x1c,0x15,0xe3 = vunpckhps %ymm11, %ymm12, %ymm4 0xc4,0xc1,0x1d,0x15,0xe3 = vunpckhpd %ymm11, %ymm12, %ymm4 0xc4,0xc1,0x1c,0x14,0xe3 = vunpcklps %ymm11, %ymm12, %ymm4 0xc4,0xc1,0x1d,0x14,0xe3 = vunpcklpd %ymm11, %ymm12, %ymm4 0xc5,0x1c,0x15,0x54,0xcb,0xfc = vunpckhps -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1d,0x15,0x54,0xcb,0xfc = vunpckhpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1c,0x14,0x54,0xcb,0xfc = vunpcklps -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1d,0x14,0x54,0xcb,0xfc = vunpcklpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x7d,0xe7,0x18 = vmovntdq %ymm11, (%rax) 0xc5,0x7d,0x2b,0x18 = vmovntpd %ymm11, (%rax) 0xc5,0x7c,0x2b,0x18 = vmovntps %ymm11, (%rax) 0xc4,0xc1,0x78,0x50,0xc4 = vmovmskps %xmm12, %eax 0xc4,0xc1,0x79,0x50,0xc4 = vmovmskpd %xmm12, %eax 0xc4,0xc1,0x5c,0x5f,0xf4 = vmaxps %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5d,0x5f,0xf4 = vmaxpd %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5c,0x5d,0xf4 = vminps %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5d,0x5d,0xf4 = vminpd %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5c,0x5c,0xf4 = vsubps %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5d,0x5c,0xf4 = vsubpd %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5c,0x5e,0xf4 = vdivps %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5d,0x5e,0xf4 = vdivpd %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5c,0x58,0xf4 = vaddps %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5d,0x58,0xf4 = vaddpd %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5c,0x59,0xf4 = vmulps %ymm12, %ymm4, %ymm6 0xc4,0xc1,0x5d,0x59,0xf4 = vmulpd %ymm12, %ymm4, %ymm6 0xc5,0xdc,0x5f,0x30 = vmaxps (%rax), %ymm4, %ymm6 0xc5,0xdd,0x5f,0x30 = vmaxpd (%rax), %ymm4, %ymm6 0xc5,0xdc,0x5d,0x30 = vminps (%rax), %ymm4, %ymm6 0xc5,0xdd,0x5d,0x30 = vminpd (%rax), %ymm4, %ymm6 0xc5,0xdc,0x5c,0x30 = vsubps (%rax), %ymm4, %ymm6 0xc5,0xdd,0x5c,0x30 = vsubpd (%rax), %ymm4, %ymm6 0xc5,0xdc,0x5e,0x30 = vdivps (%rax), %ymm4, %ymm6 0xc5,0xdd,0x5e,0x30 = vdivpd (%rax), %ymm4, %ymm6 0xc5,0xdc,0x58,0x30 = vaddps (%rax), %ymm4, %ymm6 0xc5,0xdd,0x58,0x30 = vaddpd (%rax), %ymm4, %ymm6 0xc5,0xdc,0x59,0x30 = vmulps (%rax), %ymm4, %ymm6 0xc5,0xdd,0x59,0x30 = vmulpd (%rax), %ymm4, %ymm6 0xc4,0x41,0x7d,0x51,0xe3 = vsqrtpd %ymm11, %ymm12 0xc5,0x7d,0x51,0x20 = vsqrtpd (%rax), %ymm12 0xc4,0x41,0x7c,0x51,0xe3 = vsqrtps %ymm11, %ymm12 0xc5,0x7c,0x51,0x20 = vsqrtps (%rax), %ymm12 0xc4,0x41,0x7c,0x52,0xe3 = vrsqrtps %ymm11, %ymm12 0xc5,0x7c,0x52,0x20 = vrsqrtps (%rax), %ymm12 0xc4,0x41,0x7c,0x53,0xe3 = vrcpps %ymm11, %ymm12 0xc5,0x7c,0x53,0x20 = vrcpps (%rax), %ymm12 0xc4,0x41,0x0c,0x54,0xdc = vandps %ymm12, %ymm14, %ymm11 0xc4,0x41,0x0d,0x54,0xdc = vandpd %ymm12, %ymm14, %ymm11 0xc5,0x1c,0x54,0x54,0xcb,0xfc = vandps -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1d,0x54,0x54,0xcb,0xfc = vandpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc4,0x41,0x0c,0x56,0xdc = vorps %ymm12, %ymm14, %ymm11 0xc4,0x41,0x0d,0x56,0xdc = vorpd %ymm12, %ymm14, %ymm11 0xc5,0x1c,0x56,0x54,0xcb,0xfc = vorps -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1d,0x56,0x54,0xcb,0xfc = vorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc4,0x41,0x0c,0x57,0xdc = vxorps %ymm12, %ymm14, %ymm11 0xc4,0x41,0x0d,0x57,0xdc = vxorpd %ymm12, %ymm14, %ymm11 0xc5,0x1c,0x57,0x54,0xcb,0xfc = vxorps -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1d,0x57,0x54,0xcb,0xfc = vxorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc4,0x41,0x0c,0x55,0xdc = vandnps %ymm12, %ymm14, %ymm11 0xc4,0x41,0x0d,0x55,0xdc = vandnpd %ymm12, %ymm14, %ymm11 0xc5,0x1c,0x55,0x54,0xcb,0xfc = vandnps -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc5,0x1d,0x55,0x54,0xcb,0xfc = vandnpd -4(%rbx, %rcx, 8), %ymm12, %ymm10 0xc4,0x41,0x7c,0x5a,0xe5 = vcvtps2pd %xmm13, %ymm12 0xc5,0x7c,0x5a,0x20 = vcvtps2pd (%rax), %ymm12 0xc4,0x41,0x7e,0xe6,0xe5 = vcvtdq2pd %xmm13, %ymm12 0xc5,0x7e,0xe6,0x20 = vcvtdq2pd (%rax), %ymm12 0xc4,0x41,0x7c,0x5b,0xd4 = vcvtdq2ps %ymm12, %ymm10 0xc5,0x7c,0x5b,0x20 = vcvtdq2ps (%rax), %ymm12 0xc4,0x41,0x7d,0x5b,0xd4 = vcvtps2dq %ymm12, %ymm10 0xc5,0x7d,0x5b,0x10 = vcvtps2dq (%rax), %ymm10 0xc4,0x41,0x7e,0x5b,0xd4 = vcvttps2dq %ymm12, %ymm10 0xc5,0x7e,0x5b,0x10 = vcvttps2dq (%rax), %ymm10 0xc4,0x41,0x79,0xe6,0xd3 = vcvttpd2dq %xmm11, %xmm10 0xc4,0x41,0x7d,0xe6,0xd4 = vcvttpd2dq %ymm12, %xmm10 0xc4,0x41,0x79,0xe6,0xd3 = vcvttpd2dq %xmm11, %xmm10 0xc5,0x79,0xe6,0x18 = vcvttpd2dqx (%rax), %xmm11 0xc4,0x41,0x7d,0xe6,0xdc = vcvttpd2dq %ymm12, %xmm11 0xc5,0x7d,0xe6,0x18 = vcvttpd2dqy (%rax), %xmm11 0xc4,0x41,0x7d,0x5a,0xd4 = vcvtpd2ps %ymm12, %xmm10 0xc4,0x41,0x79,0x5a,0xd3 = vcvtpd2ps %xmm11, %xmm10 0xc5,0x79,0x5a,0x18 = vcvtpd2psx (%rax), %xmm11 0xc4,0x41,0x7d,0x5a,0xdc = vcvtpd2ps %ymm12, %xmm11 0xc5,0x7d,0x5a,0x18 = vcvtpd2psy (%rax), %xmm11 0xc4,0x41,0x7f,0xe6,0xd4 = vcvtpd2dq %ymm12, %xmm10 0xc4,0x41,0x7f,0xe6,0xdc = vcvtpd2dq %ymm12, %xmm11 0xc5,0x7f,0xe6,0x18 = vcvtpd2dqy (%rax), %xmm11 0xc4,0x41,0x7b,0xe6,0xd3 = vcvtpd2dq %xmm11, %xmm10 0xc5,0x7b,0xe6,0x18 = vcvtpd2dqx (%rax), %xmm11 0xc4,0x41,0x1c,0xc2,0xeb,0x00 = vcmpeqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x02 = vcmpleps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x01 = vcmpltps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x04 = vcmpneqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x06 = vcmpnleps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x05 = vcmpnltps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x07 = vcmpordps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x03 = vcmpunordps %ymm11, %ymm12, %ymm13 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x02 = vcmpleps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnleps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x4c,0xc2,0x64,0xcb,0xfc,0x07 = vcmpordps -4(%rbx, %rcx, 8), %ymm6, %ymm12 0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordps -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x00 = vcmpeqpd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x02 = vcmplepd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x01 = vcmpltpd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x04 = vcmpneqpd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x06 = vcmpnlepd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x05 = vcmpnltpd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x07 = vcmpordpd %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1d,0xc2,0xeb,0x03 = vcmpunordpd %ymm11, %ymm12, %ymm13 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x00 = vcmpeqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x02 = vcmplepd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x01 = vcmpltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x04 = vcmpneqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x06 = vcmpnlepd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x05 = vcmpnltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc5,0x4d,0xc2,0x64,0xcb,0xfc,0x07 = vcmpordpd -4(%rbx, %rcx, 8), %ymm6, %ymm12 0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x03 = vcmpunordpd -4(%rbx, %rcx, 8), %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x08 = vcmpeq_uqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x09 = vcmpngeps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x0a = vcmpngtps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x0b = vcmpfalseps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x0c = vcmpneq_oqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x0d = vcmpgeps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x0e = vcmpgtps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x0f = vcmptrueps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x10 = vcmpeq_osps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x11 = vcmplt_oqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x12 = vcmple_oqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x13 = vcmpunord_sps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x14 = vcmpneq_usps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x15 = vcmpnlt_uqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x16 = vcmpnle_uqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x17 = vcmpord_sps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x18 = vcmpeq_usps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x19 = vcmpnge_uqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x1a = vcmpngt_uqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x1b = vcmpfalse_osps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x1c = vcmpneq_osps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x1d = vcmpge_oqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x1e = vcmpgt_oqps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1c,0xc2,0xeb,0x1f = vcmptrue_usps %ymm11, %ymm12, %ymm13 0xc4,0x41,0x1f,0xd0,0xeb = vaddsubps %ymm11, %ymm12, %ymm13 0xc5,0x27,0xd0,0x20 = vaddsubps (%rax), %ymm11, %ymm12 0xc4,0x41,0x1d,0xd0,0xeb = vaddsubpd %ymm11, %ymm12, %ymm13 0xc5,0x25,0xd0,0x20 = vaddsubpd (%rax), %ymm11, %ymm12 0xc4,0x41,0x1f,0x7c,0xeb = vhaddps %ymm11, %ymm12, %ymm13 0xc5,0x1f,0x7c,0x28 = vhaddps (%rax), %ymm12, %ymm13 0xc4,0x41,0x1d,0x7c,0xeb = vhaddpd %ymm11, %ymm12, %ymm13 0xc5,0x1d,0x7c,0x28 = vhaddpd (%rax), %ymm12, %ymm13 0xc4,0x41,0x1f,0x7d,0xeb = vhsubps %ymm11, %ymm12, %ymm13 0xc5,0x1f,0x7d,0x28 = vhsubps (%rax), %ymm12, %ymm13 0xc4,0x41,0x1d,0x7d,0xeb = vhsubpd %ymm11, %ymm12, %ymm13 0xc5,0x1d,0x7d,0x28 = vhsubpd (%rax), %ymm12, %ymm13 0xc4,0x43,0x2d,0x0c,0xdc,0x03 = vblendps $3, %ymm12, %ymm10, %ymm11 0xc4,0x63,0x2d,0x0c,0x18,0x03 = vblendps $3, (%rax), %ymm10, %ymm11 0xc4,0x43,0x2d,0x0d,0xdc,0x03 = vblendpd $3, %ymm12, %ymm10, %ymm11 0xc4,0x63,0x2d,0x0d,0x18,0x03 = vblendpd $3, (%rax), %ymm10, %ymm11 0xc4,0x43,0x2d,0x40,0xdc,0x03 = vdpps $3, %ymm12, %ymm10, %ymm11 0xc4,0x63,0x2d,0x40,0x18,0x03 = vdpps $3, (%rax), %ymm10, %ymm11 0xc4,0x62,0x7d,0x1a,0x20 = vbroadcastf128 (%rax), %ymm12 0xc4,0x62,0x7d,0x19,0x20 = vbroadcastsd (%rax), %ymm12 0xc4,0x62,0x79,0x18,0x20 = vbroadcastss (%rax), %xmm12 0xc4,0x62,0x7d,0x18,0x20 = vbroadcastss (%rax), %ymm12 0xc4,0x43,0x1d,0x18,0xd4,0x07 = vinsertf128 $7, %xmm12, %ymm12, %ymm10 0xc4,0x63,0x1d,0x18,0x10,0x07 = vinsertf128 $7, (%rax), %ymm12, %ymm10 0xc4,0x43,0x7d,0x19,0xe4,0x07 = vextractf128 $7, %ymm12, %xmm12 0xc4,0x63,0x7d,0x19,0x20,0x07 = vextractf128 $7, %ymm12, (%rax) 0xc4,0x62,0x29,0x2f,0x20 = vmaskmovpd %xmm12, %xmm10, (%rax) 0xc4,0x62,0x2d,0x2f,0x20 = vmaskmovpd %ymm12, %ymm10, (%rax) 0xc4,0x62,0x19,0x2d,0x10 = vmaskmovpd (%rax), %xmm12, %xmm10 0xc4,0x62,0x1d,0x2d,0x10 = vmaskmovpd (%rax), %ymm12, %ymm10 0xc4,0x62,0x29,0x2e,0x20 = vmaskmovps %xmm12, %xmm10, (%rax) 0xc4,0x62,0x2d,0x2e,0x20 = vmaskmovps %ymm12, %ymm10, (%rax) 0xc4,0x62,0x19,0x2c,0x10 = vmaskmovps (%rax), %xmm12, %xmm10 0xc4,0x62,0x1d,0x2c,0x10 = vmaskmovps (%rax), %ymm12, %ymm10 0xc4,0x43,0x79,0x04,0xd3,0x07 = vpermilps $7, %xmm11, %xmm10 0xc4,0x43,0x7d,0x04,0xda,0x07 = vpermilps $7, %ymm10, %ymm11 0xc4,0x63,0x79,0x04,0x10,0x07 = vpermilps $7, (%rax), %xmm10 0xc4,0x63,0x7d,0x04,0x10,0x07 = vpermilps $7, (%rax), %ymm10 0xc4,0x42,0x29,0x0c,0xdb = vpermilps %xmm11, %xmm10, %xmm11 0xc4,0x42,0x2d,0x0c,0xdb = vpermilps %ymm11, %ymm10, %ymm11 0xc4,0x62,0x29,0x0c,0x28 = vpermilps (%rax), %xmm10, %xmm13 0xc4,0x62,0x2d,0x0c,0x18 = vpermilps (%rax), %ymm10, %ymm11 0xc4,0x43,0x79,0x05,0xd3,0x07 = vpermilpd $7, %xmm11, %xmm10 0xc4,0x43,0x7d,0x05,0xda,0x07 = vpermilpd $7, %ymm10, %ymm11 0xc4,0x63,0x79,0x05,0x10,0x07 = vpermilpd $7, (%rax), %xmm10 0xc4,0x63,0x7d,0x05,0x10,0x07 = vpermilpd $7, (%rax), %ymm10 0xc4,0x42,0x29,0x0d,0xdb = vpermilpd %xmm11, %xmm10, %xmm11 0xc4,0x42,0x2d,0x0d,0xdb = vpermilpd %ymm11, %ymm10, %ymm11 0xc4,0x62,0x29,0x0d,0x28 = vpermilpd (%rax), %xmm10, %xmm13 0xc4,0x62,0x2d,0x0d,0x18 = vpermilpd (%rax), %ymm10, %ymm11 0xc4,0x43,0x2d,0x06,0xdc,0x07 = vperm2f128 $7, %ymm12, %ymm10, %ymm11 0xc4,0x63,0x2d,0x06,0x18,0x07 = vperm2f128 $7, (%rax), %ymm10, %ymm11 0xc4,0x41,0x7b,0x2d,0xc0 = vcvtsd2si %xmm8, %r8d 0xc5,0xfb,0x2d,0x09 = vcvtsd2si (%rcx), %ecx 0xc4,0xe1,0xfa,0x2d,0xcc = vcvtss2si %xmm4, %rcx 0xc4,0x61,0xfa,0x2d,0x01 = vcvtss2si (%rcx), %r8 0xc4,0x41,0x3b,0x2a,0xf8 = vcvtsi2sdl %r8d, %xmm8, %xmm15 0xc5,0x3b,0x2a,0x7d,0x00 = vcvtsi2sdl (%rbp), %xmm8, %xmm15 0xc4,0xe1,0xdb,0x2a,0xf1 = vcvtsi2sdq %rcx, %xmm4, %xmm6 0xc4,0xe1,0xdb,0x2a,0x31 = vcvtsi2sdq (%rcx), %xmm4, %xmm6 0xc4,0xe1,0xda,0x2a,0xf1 = vcvtsi2ssq %rcx, %xmm4, %xmm6 0xc4,0xe1,0xda,0x2a,0x31 = vcvtsi2ssq (%rcx), %xmm4, %xmm6 0xc4,0xe1,0xfb,0x2c,0xcc = vcvttsd2si %xmm4, %rcx 0xc4,0xe1,0xfb,0x2c,0x09 = vcvttsd2si (%rcx), %rcx 0xc4,0xe1,0xfa,0x2c,0xcc = vcvttss2si %xmm4, %rcx 0xc4,0xe1,0xfa,0x2c,0x09 = vcvttss2si (%rcx), %rcx 0xc5,0x7f,0xf0,0x20 = vlddqu (%rax), %ymm12 0xc4,0x41,0x7f,0x12,0xd4 = vmovddup %ymm12, %ymm10 0xc5,0x7f,0x12,0x20 = vmovddup (%rax), %ymm12 0xc4,0x41,0x7d,0x6f,0xd4 = vmovdqa %ymm12, %ymm10 0xc5,0x7d,0x7f,0x20 = vmovdqa %ymm12, (%rax) 0xc5,0x7d,0x6f,0x20 = vmovdqa (%rax), %ymm12 0xc4,0x41,0x7e,0x6f,0xd4 = vmovdqu %ymm12, %ymm10 0xc5,0x7e,0x7f,0x20 = vmovdqu %ymm12, (%rax) 0xc5,0x7e,0x6f,0x20 = vmovdqu (%rax), %ymm12 0xc4,0x41,0x7e,0x16,0xd4 = vmovshdup %ymm12, %ymm10 0xc5,0x7e,0x16,0x20 = vmovshdup (%rax), %ymm12 0xc4,0x41,0x7e,0x12,0xd4 = vmovsldup %ymm12, %ymm10 0xc5,0x7e,0x12,0x20 = vmovsldup (%rax), %ymm12 0xc4,0x42,0x7d,0x17,0xd4 = vptest %ymm12, %ymm10 0xc4,0x62,0x7d,0x17,0x20 = vptest (%rax), %ymm12 0xc4,0x43,0x7d,0x09,0xda,0x07 = vroundpd $7, %ymm10, %ymm11 0xc4,0x63,0x7d,0x09,0x10,0x07 = vroundpd $7, (%rax), %ymm10 0xc4,0x43,0x7d,0x08,0xda,0x07 = vroundps $7, %ymm10, %ymm11 0xc4,0x63,0x7d,0x08,0x10,0x07 = vroundps $7, (%rax), %ymm10 0xc4,0x41,0x2d,0xc6,0xdc,0x07 = vshufpd $7, %ymm12, %ymm10, %ymm11 0xc5,0x2d,0xc6,0x18,0x07 = vshufpd $7, (%rax), %ymm10, %ymm11 0xc4,0x41,0x2c,0xc6,0xdc,0x07 = vshufps $7, %ymm12, %ymm10, %ymm11 0xc5,0x2c,0xc6,0x18,0x07 = vshufps $7, (%rax), %ymm10, %ymm11 0xc4,0x42,0x79,0x0f,0xd4 = vtestpd %xmm12, %xmm10 0xc4,0x42,0x7d,0x0f,0xd4 = vtestpd %ymm12, %ymm10 0xc4,0x62,0x79,0x0f,0x20 = vtestpd (%rax), %xmm12 0xc4,0x62,0x7d,0x0f,0x20 = vtestpd (%rax), %ymm12 0xc4,0x42,0x79,0x0e,0xd4 = vtestps %xmm12, %xmm10 0xc4,0x42,0x7d,0x0e,0xd4 = vtestps %ymm12, %ymm10 0xc4,0x62,0x79,0x0e,0x20 = vtestps (%rax), %xmm12 0xc4,0x62,0x7d,0x0e,0x20 = vtestps (%rax), %ymm12 0xc4,0x43,0x79,0x17,0xc0,0x0a = vextractps $10, %xmm8, %r8d 0xc4,0xe3,0x79,0x17,0xe1,0x07 = vextractps $7, %xmm4, %ecx 0xc4,0xe1,0xf9,0x7e,0xe1 = vmovq %xmm4, %rcx 0xc5,0xf9,0x50,0xcc = vmovmskpd %xmm4, %ecx 0xc5,0xfd,0x50,0xcc = vmovmskpd %ymm4, %ecx 0xc5,0xf8,0x50,0xcc = vmovmskps %xmm4, %ecx 0xc5,0xfc,0x50,0xcc = vmovmskps %ymm4, %ecx 0xc4,0xe3,0x79,0x14,0xe1,0x07 = vpextrb $7, %xmm4, %ecx 0xc4,0x41,0x01,0xc4,0xc0,0x07 = vpinsrw $7, %r8d, %xmm15, %xmm8 0xc5,0xd9,0xc4,0xf1,0x07 = vpinsrw $7, %ecx, %xmm4, %xmm6 0xc5,0xf9,0xd7,0xcc = vpmovmskb %xmm4, %ecx 0xc4,0x63,0x1d,0x4b,0xac,0x20,0xad,0xde,0x00,0x00,0xb0 = vblendvpd %ymm11, 0xdead(%rax, %riz), %ymm12, %ymm13 0xc4,0x81,0x78,0x29,0x1c,0x1e = vmovaps %xmm3, (%r14, %r11) 0xc4,0x81,0x78,0x28,0x1c,0x1e = vmovaps (%r14, %r11), %xmm3 0xc4,0xc1,0x78,0x29,0x1c,0x1e = vmovaps %xmm3, (%r14, %rbx) 0xc4,0xc1,0x78,0x28,0x1c,0x1e = vmovaps (%r14, %rbx), %xmm3 0xc4,0xa1,0x78,0x29,0x1c,0x18 = vmovaps %xmm3, (%rax, %r11) 0xc4,0xe2,0xf9,0x92,0x14,0x4f = vgatherdpd %xmm0, (%rdi, %xmm1, 2), %xmm2 0xc4,0xe2,0xf9,0x93,0x14,0x4f = vgatherqpd %xmm0, (%rdi, %xmm1, 2), %xmm2 0xc4,0xe2,0xfd,0x92,0x14,0x4f = vgatherdpd %ymm0, (%rdi, %xmm1, 2), %ymm2 0xc4,0xe2,0xfd,0x93,0x14,0x4f = vgatherqpd %ymm0, (%rdi, %ymm1, 2), %ymm2 0xc4,0x02,0x39,0x92,0x14,0x4f = vgatherdps %xmm8, (%r15, %xmm9, 2), %xmm10 0xc4,0x02,0x39,0x93,0x14,0x4f = vgatherqps %xmm8, (%r15, %xmm9, 2), %xmm10 0xc4,0x02,0x3d,0x92,0x14,0x4f = vgatherdps %ymm8, (%r15, %ymm9, 2), %ymm10 0xc4,0x02,0x3d,0x93,0x14,0x4f = vgatherqps %xmm8, (%r15, %ymm9, 2), %xmm10 0xc4,0xe2,0xf9,0x90,0x14,0x4f = vpgatherdq %xmm0, (%rdi, %xmm1, 2), %xmm2 0xc4,0xe2,0xf9,0x91,0x14,0x4f = vpgatherqq %xmm0, (%rdi, %xmm1, 2), %xmm2 0xc4,0xe2,0xfd,0x90,0x14,0x4f = vpgatherdq %ymm0, (%rdi, %xmm1, 2), %ymm2 0xc4,0xe2,0xfd,0x91,0x14,0x4f = vpgatherqq %ymm0, (%rdi, %ymm1, 2), %ymm2 0xc4,0x02,0x39,0x90,0x14,0x4f = vpgatherdd %xmm8, (%r15, %xmm9, 2), %xmm10 0xc4,0x02,0x39,0x91,0x14,0x4f = vpgatherqd %xmm8, (%r15, %xmm9, 2), %xmm10 0xc4,0x02,0x3d,0x90,0x14,0x4f = vpgatherdd %ymm8, (%r15, %ymm9, 2), %ymm10 0xc4,0x02,0x3d,0x91,0x14,0x4f = vpgatherqd %xmm8, (%r15, %ymm9, 2), %xmm10 0xc5,0x78,0x28,0xc0 = vmovaps %xmm0, %xmm8 0xc5,0x78,0x29,0xc0 = vmovaps %xmm8, %xmm0 0xc5,0x7c,0x28,0xc0 = vmovaps %ymm0, %ymm8 0xc5,0x7c,0x29,0xc0 = vmovaps %ymm8, %ymm0 0xc5,0x78,0x10,0xc0 = vmovups %xmm0, %xmm8 0xc5,0x78,0x11,0xc0 = vmovups %xmm8, %xmm0 0xc5,0x7c,0x10,0xc0 = vmovups %ymm0, %ymm8 0xc5,0x7c,0x11,0xc0 = vmovups %ymm8, %ymm0 0xc5,0x7a,0x10,0xc0 = vmovss %xmm0, %xmm0, %xmm8 0xc5,0xba,0x10,0xc0 = vmovss %xmm0, %xmm8, %xmm0 0xc5,0x7a,0x11,0xc0 = vmovss %xmm8, %xmm0, %xmm0 0xc5,0x7b,0x10,0xc0 = vmovsd %xmm0, %xmm0, %xmm8 0xc5,0xbb,0x10,0xc0 = vmovsd %xmm0, %xmm8, %xmm0 0xc5,0x7b,0x11,0xc0 = vmovsd %xmm8, %xmm0, %xmm0 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-bmi-encoding.s.cs000064400000000000000000000050560072674642500223050ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0xc4,0xc2,0x28,0xf3,0xd3 = blsmskl %r11d, %r10d 0xc4,0xc2,0xa8,0xf3,0xd3 = blsmskq %r11, %r10 0xc4,0xe2,0x28,0xf3,0x10 = blsmskl (%rax), %r10d 0xc4,0xe2,0xa8,0xf3,0x10 = blsmskq (%rax), %r10 0xc4,0xc2,0x28,0xf3,0xdb = blsil %r11d, %r10d 0xc4,0xc2,0xa8,0xf3,0xdb = blsiq %r11, %r10 0xc4,0xe2,0x28,0xf3,0x18 = blsil (%rax), %r10d 0xc4,0xe2,0xa8,0xf3,0x18 = blsiq (%rax), %r10 0xc4,0xc2,0x28,0xf3,0xcb = blsrl %r11d, %r10d 0xc4,0xc2,0xa8,0xf3,0xcb = blsrq %r11, %r10 0xc4,0xe2,0x28,0xf3,0x08 = blsrl (%rax), %r10d 0xc4,0xe2,0xa8,0xf3,0x08 = blsrq (%rax), %r10 0xc4,0x62,0x20,0xf2,0x10 = andnl (%rax), %r11d, %r10d 0xc4,0x62,0xa0,0xf2,0x10 = andnq (%rax), %r11, %r10 0xc4,0x62,0x18,0xf7,0x10 = bextrl %r12d, (%rax), %r10d 0xc4,0x42,0x18,0xf7,0xd3 = bextrl %r12d, %r11d, %r10d 0xc4,0x62,0x98,0xf7,0x10 = bextrq %r12, (%rax), %r10 0xc4,0x42,0x98,0xf7,0xd3 = bextrq %r12, %r11, %r10 0xc4,0x62,0x18,0xf5,0x10 = bzhil %r12d, (%rax), %r10d 0xc4,0x42,0x18,0xf5,0xd3 = bzhil %r12d, %r11d, %r10d 0xc4,0x62,0x98,0xf5,0x10 = bzhiq %r12, (%rax), %r10 0xc4,0x42,0x98,0xf5,0xd3 = bzhiq %r12, %r11, %r10 0xc4,0x42,0x22,0xf5,0xd4 = pextl %r12d, %r11d, %r10d 0xc4,0x62,0x22,0xf5,0x10 = pextl (%rax), %r11d, %r10d 0xc4,0x42,0xa2,0xf5,0xd4 = pextq %r12, %r11, %r10 0xc4,0x62,0xa2,0xf5,0x10 = pextq (%rax), %r11, %r10 0xc4,0x42,0x23,0xf5,0xd4 = pdepl %r12d, %r11d, %r10d 0xc4,0x62,0x23,0xf5,0x10 = pdepl (%rax), %r11d, %r10d 0xc4,0x42,0xa3,0xf5,0xd4 = pdepq %r12, %r11, %r10 0xc4,0x62,0xa3,0xf5,0x10 = pdepq (%rax), %r11, %r10 0xc4,0x42,0x23,0xf6,0xd4 = mulxl %r12d, %r11d, %r10d 0xc4,0x62,0x23,0xf6,0x10 = mulxl (%rax), %r11d, %r10d 0xc4,0x42,0xa3,0xf6,0xd4 = mulxq %r12, %r11, %r10 0xc4,0x62,0xa3,0xf6,0x10 = mulxq (%rax), %r11, %r10 0xc4,0x43,0x7b,0xf0,0xd4,0x0a = rorxl $10, %r12d, %r10d 0xc4,0x63,0x7b,0xf0,0x10,0x1f = rorxl $31, (%rax), %r10d 0xc4,0x43,0xfb,0xf0,0xd4,0x01 = rorxq $1, %r12, %r10 0xc4,0x63,0xfb,0xf0,0x10,0x3f = rorxq $63, (%rax), %r10 0xc4,0x62,0x19,0xf7,0x10 = shlxl %r12d, (%rax), %r10d 0xc4,0x42,0x19,0xf7,0xd3 = shlxl %r12d, %r11d, %r10d 0xc4,0x62,0x99,0xf7,0x10 = shlxq %r12, (%rax), %r10 0xc4,0x42,0x99,0xf7,0xd3 = shlxq %r12, %r11, %r10 0xc4,0x62,0x1a,0xf7,0x10 = sarxl %r12d, (%rax), %r10d 0xc4,0x42,0x1a,0xf7,0xd3 = sarxl %r12d, %r11d, %r10d 0xc4,0x62,0x9a,0xf7,0x10 = sarxq %r12, (%rax), %r10 0xc4,0x42,0x9a,0xf7,0xd3 = sarxq %r12, %r11, %r10 0xc4,0x62,0x1b,0xf7,0x10 = shrxl %r12d, (%rax), %r10d 0xc4,0x42,0x1b,0xf7,0xd3 = shrxl %r12d, %r11d, %r10d 0xc4,0x62,0x9b,0xf7,0x10 = shrxq %r12, (%rax), %r10 0xc4,0x42,0x9b,0xf7,0xd3 = shrxq %r12, %r11, %r10 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-encoding.s.cs000064400000000000000000000053470072674642500215430ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x65,0x48,0x8b,0x07 = movq %gs:(%rdi), %rax 0xf2,0x0f,0x38,0xf0,0xc3 = crc32b %bl, %eax 0xf2,0x0f,0x38,0xf0,0x43,0x04 = crc32b 4(%rbx), %eax 0x66,0xf2,0x0f,0x38,0xf1,0xc3 = crc32w %bx, %eax 0x66,0xf2,0x0f,0x38,0xf1,0x43,0x04 = crc32w 4(%rbx), %eax 0xf2,0x0f,0x38,0xf1,0xc3 = crc32l %ebx, %eax 0xf2,0x0f,0x38,0xf1,0x43,0x04 = crc32l 4(%rbx), %eax 0xf2,0x0f,0x38,0xf1,0x8c,0xcb,0xef,0xbe,0xad,0xde = crc32l -0x21524111(%rbx, %rcx, 8), %ecx 0xf2,0x0f,0x38,0xf1,0x0c,0x25,0x45,0x00,0x00,0x00 = crc32l 0x45, %ecx 0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xed,0x7e,0x00,0x00 = crc32l 0x7eed, %ecx 0xf2,0x0f,0x38,0xf1,0x0c,0x25,0xfe,0xca,0xbe,0xba = crc32l 0xffffffffbabecafe, %ecx 0xf2,0x0f,0x38,0xf1,0xc9 = crc32l %ecx, %ecx 0xf2,0x41,0x0f,0x38,0xf0,0xc3 = crc32b %r11b, %eax 0xf2,0x0f,0x38,0xf0,0x43,0x04 = crc32b 4(%rbx), %eax 0xf2,0x48,0x0f,0x38,0xf0,0xc7 = crc32b %dil, %rax 0xf2,0x49,0x0f,0x38,0xf0,0xc3 = crc32b %r11b, %rax 0xf2,0x48,0x0f,0x38,0xf0,0x43,0x04 = crc32b 4(%rbx), %rax 0xf2,0x48,0x0f,0x38,0xf1,0xc3 = crc32q %rbx, %rax 0xf2,0x48,0x0f,0x38,0xf1,0x43,0x04 = crc32q 4(%rbx), %rax 0x49,0x0f,0x6e,0xc8 = movq %r8, %mm1 0x41,0x0f,0x6e,0xc8 = movd %r8d, %mm1 0x48,0x0f,0x6e,0xca = movq %rdx, %mm1 0x0f,0x6e,0xca = movd %edx, %mm1 0x49,0x0f,0x7e,0xc8 = movq %mm1, %r8 0x41,0x0f,0x7e,0xc8 = movd %mm1, %r8d 0x48,0x0f,0x7e,0xca = movq %mm1, %rdx 0x0f,0x7e,0xca = movd %mm1, %edx 0x0f,0x3a,0xcc,0xd1,0x01 = sha1rnds4 $1, %xmm1, %xmm2 0x0f,0x3a,0xcc,0x10,0x01 = sha1rnds4 $1, (%rax), %xmm2 0x0f,0x38,0xc8,0xd1 = sha1nexte %xmm1, %xmm2 0x0f,0x38,0xc9,0xd1 = sha1msg1 %xmm1, %xmm2 0x0f,0x38,0xc9,0x10 = sha1msg1 (%rax), %xmm2 0x0f,0x38,0xca,0xd1 = sha1msg2 %xmm1, %xmm2 0x0f,0x38,0xca,0x10 = sha1msg2 (%rax), %xmm2 0x0f,0x38,0xcb,0x10 = sha256rnds2 %xmm0, (%rax), %xmm2 0x0f,0x38,0xcb,0xd1 = sha256rnds2 %xmm0, %xmm1, %xmm2 0x0f,0x38,0xcb,0x10 = sha256rnds2 %xmm0, (%rax), %xmm2 0x0f,0x38,0xcb,0xd1 = sha256rnds2 %xmm0, %xmm1, %xmm2 0x0f,0x38,0xcc,0xd1 = sha256msg1 %xmm1, %xmm2 0x0f,0x38,0xcc,0x10 = sha256msg1 (%rax), %xmm2 0x0f,0x38,0xcd,0xd1 = sha256msg2 %xmm1, %xmm2 0x0f,0x38,0xcd,0x10 = sha256msg2 (%rax), %xmm2 0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00 = movq 0xdead, %rbx 0x48,0x8b,0x04,0x25,0xef,0xbe,0x00,0x00 = movq 0xbeef, %rax 0x48,0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff = movq -4(, %riz, 8), %rax 0x48,0x8b,0x04,0x21 = movq (%rcx, %riz), %rax 0x48,0x8b,0x04,0xe1 = movq (%rcx, %riz, 8), %rax 0x48,0x0f,0xae,0x00 = fxsave64 (%rax) 0x48,0x0f,0xae,0x08 = fxrstor64 (%rax) 0xc9 = leave 0xc9 = leave 0x67,0xd9,0x07 = flds (%edi) 0x67,0xdf,0x07 = filds (%edi) 0xd9,0x07 = flds (%rdi) 0xdf,0x07 = filds (%rdi) 0x66,0x0f,0xd7,0xcd = pmovmskb %xmm5, %ecx 0x66,0x0f,0xc4,0xe9,0x03 = pinsrw $3, %ecx, %xmm5 0x66,0x0f,0xc4,0xe9,0x03 = pinsrw $3, %ecx, %xmm5 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-fma3-encoding.s.cs000064400000000000000000000246350072674642500223700ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0xc4,0x42,0xa9,0x98,0xdc = vfmadd132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x98,0x18 = vfmadd132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x98,0xdc = vfmadd132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x98,0x18 = vfmadd132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xa8,0xdc = vfmadd213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xa8,0x18 = vfmadd213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xa8,0xdc = vfmadd213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xa8,0x18 = vfmadd213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xb8,0xdc = vfmadd231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xb8,0x18 = vfmadd231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xb8,0xdc = vfmadd231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xb8,0x18 = vfmadd231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xad,0x98,0xdc = vfmadd132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x98,0x18 = vfmadd132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x98,0xdc = vfmadd132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x98,0x18 = vfmadd132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xa8,0xdc = vfmadd213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xa8,0x18 = vfmadd213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xa8,0xdc = vfmadd213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xa8,0x18 = vfmadd213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xb8,0xdc = vfmadd231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xb8,0x18 = vfmadd231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xb8,0xdc = vfmadd231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xb8,0x18 = vfmadd231ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xa9,0x98,0xdc = vfmadd132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x98,0x18 = vfmadd132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x98,0xdc = vfmadd132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x98,0x18 = vfmadd132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xa8,0xdc = vfmadd213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xa8,0x18 = vfmadd213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xa8,0xdc = vfmadd213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xa8,0x18 = vfmadd213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xb8,0xdc = vfmadd231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xb8,0x18 = vfmadd231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xb8,0xdc = vfmadd231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xb8,0x18 = vfmadd231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0x96,0xdc = vfmaddsub132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x96,0x18 = vfmaddsub132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x96,0xdc = vfmaddsub132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x96,0x18 = vfmaddsub132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xa6,0xdc = vfmaddsub213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xa6,0x18 = vfmaddsub213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xa6,0xdc = vfmaddsub213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xa6,0x18 = vfmaddsub213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xb6,0xdc = vfmaddsub231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xb6,0x18 = vfmaddsub231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xb6,0xdc = vfmaddsub231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xb6,0x18 = vfmaddsub231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0x97,0xdc = vfmsubadd132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x97,0x18 = vfmsubadd132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x97,0xdc = vfmsubadd132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x97,0x18 = vfmsubadd132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xa7,0xdc = vfmsubadd213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xa7,0x18 = vfmsubadd213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xa7,0xdc = vfmsubadd213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xa7,0x18 = vfmsubadd213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xb7,0xdc = vfmsubadd231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xb7,0x18 = vfmsubadd231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xb7,0xdc = vfmsubadd231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xb7,0x18 = vfmsubadd231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0x9a,0xdc = vfmsub132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x9a,0x18 = vfmsub132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x9a,0xdc = vfmsub132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x9a,0x18 = vfmsub132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xaa,0xdc = vfmsub213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xaa,0x18 = vfmsub213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xaa,0xdc = vfmsub213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xaa,0x18 = vfmsub213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xba,0xdc = vfmsub231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xba,0x18 = vfmsub231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xba,0xdc = vfmsub231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xba,0x18 = vfmsub231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0x9c,0xdc = vfnmadd132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x9c,0x18 = vfnmadd132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x9c,0xdc = vfnmadd132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x9c,0x18 = vfnmadd132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xac,0xdc = vfnmadd213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xac,0x18 = vfnmadd213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xac,0xdc = vfnmadd213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xac,0x18 = vfnmadd213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xbc,0xdc = vfnmadd231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xbc,0x18 = vfnmadd231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xbc,0xdc = vfnmadd231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xbc,0x18 = vfnmadd231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0x9e,0xdc = vfnmsub132pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0x9e,0x18 = vfnmsub132pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0x9e,0xdc = vfnmsub132ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0x9e,0x18 = vfnmsub132ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xae,0xdc = vfnmsub213pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xae,0x18 = vfnmsub213pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xae,0xdc = vfnmsub213ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xae,0x18 = vfnmsub213ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xa9,0xbe,0xdc = vfnmsub231pd %xmm12, %xmm10, %xmm11 0xc4,0x62,0xa9,0xbe,0x18 = vfnmsub231pd (%rax), %xmm10, %xmm11 0xc4,0x42,0x29,0xbe,0xdc = vfnmsub231ps %xmm12, %xmm10, %xmm11 0xc4,0x62,0x29,0xbe,0x18 = vfnmsub231ps (%rax), %xmm10, %xmm11 0xc4,0x42,0xad,0x98,0xdc = vfmadd132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x98,0x18 = vfmadd132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x98,0xdc = vfmadd132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x98,0x18 = vfmadd132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xa8,0xdc = vfmadd213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xa8,0x18 = vfmadd213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xa8,0xdc = vfmadd213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xa8,0x18 = vfmadd213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xb8,0xdc = vfmadd231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xb8,0x18 = vfmadd231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xb8,0xdc = vfmadd231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xb8,0x18 = vfmadd231ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0x96,0xdc = vfmaddsub132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x96,0x18 = vfmaddsub132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x96,0xdc = vfmaddsub132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x96,0x18 = vfmaddsub132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xa6,0xdc = vfmaddsub213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xa6,0x18 = vfmaddsub213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xa6,0xdc = vfmaddsub213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xa6,0x18 = vfmaddsub213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xb6,0xdc = vfmaddsub231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xb6,0x18 = vfmaddsub231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xb6,0xdc = vfmaddsub231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xb6,0x18 = vfmaddsub231ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0x97,0xdc = vfmsubadd132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x97,0x18 = vfmsubadd132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x97,0xdc = vfmsubadd132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x97,0x18 = vfmsubadd132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xa7,0xdc = vfmsubadd213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xa7,0x18 = vfmsubadd213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xa7,0xdc = vfmsubadd213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xa7,0x18 = vfmsubadd213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xb7,0xdc = vfmsubadd231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xb7,0x18 = vfmsubadd231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xb7,0xdc = vfmsubadd231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xb7,0x18 = vfmsubadd231ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0x9a,0xdc = vfmsub132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x9a,0x18 = vfmsub132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x9a,0xdc = vfmsub132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x9a,0x18 = vfmsub132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xaa,0xdc = vfmsub213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xaa,0x18 = vfmsub213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xaa,0xdc = vfmsub213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xaa,0x18 = vfmsub213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xba,0xdc = vfmsub231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xba,0x18 = vfmsub231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xba,0xdc = vfmsub231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xba,0x18 = vfmsub231ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0x9c,0xdc = vfnmadd132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x9c,0x18 = vfnmadd132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x9c,0xdc = vfnmadd132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x9c,0x18 = vfnmadd132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xac,0xdc = vfnmadd213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xac,0x18 = vfnmadd213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xac,0xdc = vfnmadd213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xac,0x18 = vfnmadd213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xbc,0xdc = vfnmadd231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xbc,0x18 = vfnmadd231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xbc,0xdc = vfnmadd231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xbc,0x18 = vfnmadd231ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0x9e,0xdc = vfnmsub132pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0x9e,0x18 = vfnmsub132pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0x9e,0xdc = vfnmsub132ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0x9e,0x18 = vfnmsub132ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xae,0xdc = vfnmsub213pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xae,0x18 = vfnmsub213pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xae,0xdc = vfnmsub213ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xae,0x18 = vfnmsub213ps (%rax), %ymm10, %ymm11 0xc4,0x42,0xad,0xbe,0xdc = vfnmsub231pd %ymm12, %ymm10, %ymm11 0xc4,0x62,0xad,0xbe,0x18 = vfnmsub231pd (%rax), %ymm10, %ymm11 0xc4,0x42,0x2d,0xbe,0xdc = vfnmsub231ps %ymm12, %ymm10, %ymm11 0xc4,0x62,0x2d,0xbe,0x18 = vfnmsub231ps (%rax), %ymm10, %ymm11 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-fma4-encoding.s.cs000064400000000000000000000152360072674642500223660ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0xc4,0xe3,0xf9,0x6a,0x01,0x10 = vfmaddss (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x6a,0x01,0x10 = vfmaddss %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6a,0xc2,0x10 = vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6b,0x01,0x10 = vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x6b,0x01,0x10 = vfmaddsd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6b,0xc2,0x10 = vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xc3,0xf9,0x6b,0xc2,0x10 = vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x68,0x01,0x10 = vfmaddps (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x68,0x01,0x10 = vfmaddps %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x68,0xc2,0x10 = vfmaddps %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x69,0x01,0x10 = vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x69,0x01,0x10 = vfmaddpd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x69,0xc2,0x10 = vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xfd,0x68,0x01,0x10 = vfmaddps (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x68,0x01,0x10 = vfmaddps %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x68,0xc2,0x10 = vfmaddps %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xfd,0x69,0x01,0x10 = vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x69,0x01,0x10 = vfmaddpd %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x69,0xc2,0x10 = vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xf9,0x6e,0x01,0x10 = vfmsubss (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x6e,0x01,0x10 = vfmsubss %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6e,0xc2,0x10 = vfmsubss %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6f,0x01,0x10 = vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x6f,0x01,0x10 = vfmsubsd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6f,0xc2,0x10 = vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6c,0x01,0x10 = vfmsubps (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x6c,0x01,0x10 = vfmsubps %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6c,0xc2,0x10 = vfmsubps %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6d,0x01,0x10 = vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x6d,0x01,0x10 = vfmsubpd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x6d,0xc2,0x10 = vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xfd,0x6c,0x01,0x10 = vfmsubps (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x6c,0x01,0x10 = vfmsubps %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x6c,0xc2,0x10 = vfmsubps %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xfd,0x6d,0x01,0x10 = vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x6d,0x01,0x10 = vfmsubpd %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x6d,0xc2,0x10 = vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xf9,0x7a,0x01,0x10 = vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x7a,0x01,0x10 = vfnmaddss %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7a,0xc2,0x10 = vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7b,0x01,0x10 = vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x7b,0x01,0x10 = vfnmaddsd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7b,0xc2,0x10 = vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x78,0x01,0x10 = vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x78,0x01,0x10 = vfnmaddps %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x78,0xc2,0x10 = vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x79,0x01,0x10 = vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x79,0x01,0x10 = vfnmaddpd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x79,0xc2,0x10 = vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xfd,0x78,0x01,0x10 = vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x78,0x01,0x10 = vfnmaddps %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x78,0xc2,0x10 = vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xfd,0x79,0x01,0x10 = vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x79,0x01,0x10 = vfnmaddpd %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x79,0xc2,0x10 = vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xf9,0x7e,0x01,0x10 = vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x7e,0x01,0x10 = vfnmsubss %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7e,0xc2,0x10 = vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7f,0x01,0x10 = vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x7f,0x01,0x10 = vfnmsubsd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7f,0xc2,0x10 = vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7c,0x01,0x10 = vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x7c,0x01,0x10 = vfnmsubps %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7c,0xc2,0x10 = vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7d,0x01,0x10 = vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x7d,0x01,0x10 = vfnmsubpd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x7d,0xc2,0x10 = vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xfd,0x7c,0x01,0x10 = vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x7c,0x01,0x10 = vfnmsubps %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x7c,0xc2,0x10 = vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xfd,0x7d,0x01,0x10 = vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x7d,0x01,0x10 = vfnmsubpd %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x7d,0xc2,0x10 = vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xf9,0x5c,0x01,0x10 = vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x5c,0x01,0x10 = vfmaddsubps %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x5c,0xc2,0x10 = vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x5d,0x01,0x10 = vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x5d,0x01,0x10 = vfmaddsubpd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x5d,0xc2,0x10 = vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xfd,0x5c,0x01,0x10 = vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x5c,0x01,0x10 = vfmaddsubps %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x5c,0xc2,0x10 = vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xfd,0x5d,0x01,0x10 = vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x5d,0x01,0x10 = vfmaddsubpd %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x5d,0xc2,0x10 = vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xf9,0x5e,0x01,0x10 = vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x5e,0x01,0x10 = vfmsubaddps %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x5e,0xc2,0x10 = vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xf9,0x5f,0x01,0x10 = vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0 0xc4,0xe3,0x79,0x5f,0x01,0x10 = vfmsubaddpd %xmm1, (%rcx), %xmm0, %xmm0 0xc4,0xe3,0xf9,0x5f,0xc2,0x10 = vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0 0xc4,0xe3,0xfd,0x5e,0x01,0x10 = vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x5e,0x01,0x10 = vfmsubaddps %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x5e,0xc2,0x10 = vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0 0xc4,0xe3,0xfd,0x5f,0x01,0x10 = vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0 0xc4,0xe3,0x7d,0x5f,0x01,0x10 = vfmsubaddpd %ymm1, (%rcx), %ymm0, %ymm0 0xc4,0xe3,0xfd,0x5f,0xc2,0x10 = vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-imm-widths.s.cs000064400000000000000000000023570072674642500220350ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x04,0x00 = addb $0x00, %al 0x04,0x7f = addb $0x7F, %al 0x04,0x80 = addb $0x80, %al 0x04,0xff = addb $0xFF, %al 0x66,0x83,0xc0,0x00 = addw $0x0000, %ax 0x66,0x83,0xc0,0x7f = addw $0x007F, %ax 0x66,0x83,0xc0,0x80 = addw $-0x80, %ax 0x66,0x83,0xc0,0xff = addw $-1, %ax 0x83,0xc0,0x00 = addl $0x00000000, %eax 0x83,0xc0,0x7f = addl $0x0000007F, %eax 0x05,0x80,0xff,0x00,0x00 = addl $0xFF80, %eax 0x05,0xff,0xff,0x00,0x00 = addl $0xFFFF, %eax 0x83,0xc0,0x80 = addl $-0x80, %eax 0x83,0xc0,0xff = addl $-1, %eax 0x48,0x83,0xc0,0x00 = addq $0x0000000000000000, %rax 0x48,0x83,0xc0,0x7f = addq $0x000000000000007F, %rax 0x48,0x83,0xc0,0x80 = addq $0xFFFFFFFFFFFFFF80, %rax 0x48,0x83,0xc0,0xff = addq $0xFFFFFFFFFFFFFFFF, %rax 0x48,0x83,0xc0,0x00 = addq $0x0000000000000000, %rax 0x48,0x05,0x80,0xff,0x00,0x00 = addq $0xFF80, %rax 0x48,0x05,0xff,0xff,0x00,0x00 = addq $0xFFFF, %rax 0x48,0xb8,0x80,0xff,0xff,0xff,0x00,0x00,0x00,0x00 = movabsq $0xFFFFFF80, %rax 0x48,0xb8,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00 = movabsq $0xFFFFFFFF, %rax 0x48,0x05,0xff,0xff,0xff,0x7f = addq $0x000000007FFFFFFF, %rax 0x48,0x05,0x00,0x00,0x00,0x80 = addq $0xFFFFFFFF80000000, %rax 0x48,0x05,0x00,0xff,0xff,0xff = addq $0xFFFFFFFFFFFFFF00, %rax capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-rand-encoding.s.cs000064400000000000000000000007230072674642500224560ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x66,0x0f,0xc7,0xf0 = rdrandw %ax 0x0f,0xc7,0xf0 = rdrandl %eax 0x48,0x0f,0xc7,0xf0 = rdrandq %rax 0x66,0x41,0x0f,0xc7,0xf3 = rdrandw %r11w 0x41,0x0f,0xc7,0xf3 = rdrandl %r11d 0x49,0x0f,0xc7,0xf3 = rdrandq %r11 0x66,0x0f,0xc7,0xf8 = rdseedw %ax 0x0f,0xc7,0xf8 = rdseedl %eax 0x48,0x0f,0xc7,0xf8 = rdseedq %rax 0x66,0x41,0x0f,0xc7,0xfb = rdseedw %r11w 0x41,0x0f,0xc7,0xfb = rdseedl %r11d 0x49,0x0f,0xc7,0xfb = rdseedq %r11 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-rtm-encoding.s.cs000064400000000000000000000001700072674642500223300ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0f,0x01,0xd5 = xend 0x0f,0x01,0xd6 = xtest 0xc6,0xf8,0x0d = xabort $13 capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-sse4a.s.cs000064400000000000000000000000550072674642500207630ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-tbm-encoding.s.cs000064400000000000000000000036520072674642500223200ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x8f,0xea,0x78,0x10,0xc7,0xfe,0x0a,0x00,0x00 = bextrl $2814, %edi, %eax 0x8f,0xea,0x78,0x10,0x07,0xfe,0x0a,0x00,0x00 = bextrl $2814, (%rdi), %eax 0x8f,0xea,0xf8,0x10,0xc7,0xfe,0x0a,0x00,0x00 = bextrq $2814, %rdi, %rax 0x8f,0xea,0xf8,0x10,0x07,0xfe,0x0a,0x00,0x00 = bextrq $2814, (%rdi), %rax 0x8f,0xe9,0x78,0x01,0xcf = blcfilll %edi, %eax 0x8f,0xe9,0x78,0x01,0x0f = blcfilll (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xcf = blcfillq %rdi, %rax 0x8f,0xe9,0xf8,0x01,0x0f = blcfillq (%rdi), %rax 0x8f,0xe9,0x78,0x02,0xf7 = blcil %edi, %eax 0x8f,0xe9,0x78,0x02,0x37 = blcil (%rdi), %eax 0x8f,0xe9,0xf8,0x02,0xf7 = blciq %rdi, %rax 0x8f,0xe9,0xf8,0x02,0x37 = blciq (%rdi), %rax 0x8f,0xe9,0x78,0x01,0xef = blcicl %edi, %eax 0x8f,0xe9,0x78,0x01,0x2f = blcicl (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xef = blcicq %rdi, %rax 0x8f,0xe9,0xf8,0x01,0x2f = blcicq (%rdi), %rax 0x8f,0xe9,0x78,0x02,0xcf = blcmskl %edi, %eax 0x8f,0xe9,0x78,0x02,0x0f = blcmskl (%rdi), %eax 0x8f,0xe9,0xf8,0x02,0xcf = blcmskq %rdi, %rax 0x8f,0xe9,0xf8,0x02,0x0f = blcmskq (%rdi), %rax 0x8f,0xe9,0x78,0x01,0xdf = blcsl %edi, %eax 0x8f,0xe9,0x78,0x01,0x1f = blcsl (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xdf = blcsq %rdi, %rax 0x8f,0xe9,0xf8,0x01,0x1f = blcsq (%rdi), %rax 0x8f,0xe9,0x78,0x01,0xd7 = blsfilll %edi, %eax 0x8f,0xe9,0x78,0x01,0x17 = blsfilll (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xd7 = blsfillq %rdi, %rax 0x8f,0xe9,0xf8,0x01,0x17 = blsfillq (%rdi), %rax 0x8f,0xe9,0x78,0x01,0xf7 = blsicl %edi, %eax 0x8f,0xe9,0x78,0x01,0x37 = blsicl (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xf7 = blsicq %rdi, %rax 0x8f,0xe9,0x78,0x01,0xff = t1mskcl %edi, %eax 0x8f,0xe9,0x78,0x01,0x3f = t1mskcl (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xff = t1mskcq %rdi, %rax 0x8f,0xe9,0xf8,0x01,0x3f = t1mskcq (%rdi), %rax 0x8f,0xe9,0x78,0x01,0xe7 = tzmskl %edi, %eax 0x8f,0xe9,0x78,0x01,0x27 = tzmskl (%rdi), %eax 0x8f,0xe9,0xf8,0x01,0xe7 = tzmskq %rdi, %rax 0x8f,0xe9,0xf8,0x01,0x27 = tzmskq (%rdi), %rax capstone-sys-0.15.0/capstone/suite/MC/X86/x86_64-xop-encoding.s.cs000064400000000000000000000222710072674642500223420ustar 00000000000000# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x8f,0xe9,0x78,0xe2,0x0c,0x01 = vphsubwd (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0xe2,0xc8 = vphsubwd %xmm0, %xmm1 0x8f,0xe9,0x78,0xe3,0x0c,0x01 = vphsubdq (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0xe3,0xc8 = vphsubdq %xmm0, %xmm1 0x8f,0xe9,0x78,0xe1,0x08 = vphsubbw (%rax), %xmm1 0x8f,0xe9,0x78,0xe1,0xca = vphsubbw %xmm2, %xmm1 0x8f,0xe9,0x78,0xc7,0x21 = vphaddwq (%rcx), %xmm4 0x8f,0xe9,0x78,0xc7,0xd6 = vphaddwq %xmm6, %xmm2 0x8f,0xe9,0x78,0xc6,0x3c,0x02 = vphaddwd (%rdx, %rax), %xmm7 0x8f,0xe9,0x78,0xc6,0xe3 = vphaddwd %xmm3, %xmm4 0x8f,0xe9,0x78,0xd7,0x34,0x01 = vphadduwq (%rcx, %rax), %xmm6 0x8f,0xe9,0x78,0xd7,0xc7 = vphadduwq %xmm7, %xmm0 0x8f,0xe9,0x78,0xd6,0x28 = vphadduwd (%rax), %xmm5 0x8f,0xe9,0x78,0xd6,0xca = vphadduwd %xmm2, %xmm1 0x8f,0xe9,0x78,0xdb,0x64,0x01,0x08 = vphaddudq 8(%rcx, %rax), %xmm4 0x8f,0xe9,0x78,0xdb,0xd6 = vphaddudq %xmm6, %xmm2 0x8f,0xe9,0x78,0xd1,0x19 = vphaddubw (%rcx), %xmm3 0x8f,0xe9,0x78,0xd1,0xc5 = vphaddubw %xmm5, %xmm0 0x8f,0xe9,0x78,0xd3,0x21 = vphaddubq (%rcx), %xmm4 0x8f,0xe9,0x78,0xd3,0xd2 = vphaddubq %xmm2, %xmm2 0x8f,0xe9,0x78,0xd2,0x28 = vphaddubd (%rax), %xmm5 0x8f,0xe9,0x78,0xd2,0xfd = vphaddubd %xmm5, %xmm7 0x8f,0xe9,0x78,0xcb,0x22 = vphadddq (%rdx), %xmm4 0x8f,0xe9,0x78,0xcb,0xec = vphadddq %xmm4, %xmm5 0x8f,0xe9,0x78,0xc1,0x0c,0x01 = vphaddbw (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0xc1,0xf5 = vphaddbw %xmm5, %xmm6 0x8f,0xe9,0x78,0xc3,0x0c,0x01 = vphaddbq (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0xc3,0xc2 = vphaddbq %xmm2, %xmm0 0x8f,0xe9,0x78,0xc2,0x0c,0x01 = vphaddbd (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0xc2,0xd9 = vphaddbd %xmm1, %xmm3 0x8f,0xe9,0x78,0x82,0x0c,0x01 = vfrczss (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0x82,0xfd = vfrczss %xmm5, %xmm7 0x8f,0xe9,0x78,0x83,0x0c,0x01 = vfrczsd (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0x83,0xc7 = vfrczsd %xmm7, %xmm0 0x8f,0xe9,0x78,0x80,0x58,0x04 = vfrczps 4(%rax), %xmm3 0x8f,0xe9,0x78,0x80,0xee = vfrczps %xmm6, %xmm5 0x8f,0xe9,0x78,0x80,0x09 = vfrczps (%rcx), %xmm1 0x8f,0xe9,0x7c,0x80,0xe2 = vfrczps %ymm2, %ymm4 0x8f,0xe9,0x78,0x81,0x0c,0x01 = vfrczpd (%rcx, %rax), %xmm1 0x8f,0xe9,0x78,0x81,0xc7 = vfrczpd %xmm7, %xmm0 0x8f,0xe9,0x7c,0x81,0x14,0x01 = vfrczpd (%rcx, %rax), %ymm2 0x8f,0xe9,0x7c,0x81,0xdd = vfrczpd %ymm5, %ymm3 0x8f,0xe9,0x78,0x95,0xd1 = vpshlw %xmm0, %xmm1, %xmm2 0x8f,0xe9,0xf0,0x95,0x10 = vpshlw (%rax), %xmm1, %xmm2 0x8f,0xe9,0x78,0x95,0x14,0x08 = vpshlw %xmm0, (%rax, %rcx), %xmm2 0x8f,0xe9,0x68,0x97,0xf4 = vpshlq %xmm2, %xmm4, %xmm6 0x8f,0xe9,0xe8,0x97,0x09 = vpshlq (%rcx), %xmm2, %xmm1 0x8f,0xe9,0x50,0x97,0x34,0x0a = vpshlq %xmm5, (%rdx, %rcx), %xmm6 0x8f,0xe9,0x40,0x96,0xdd = vpshld %xmm7, %xmm5, %xmm3 0x8f,0xe9,0xe0,0x96,0x58,0x04 = vpshld 4(%rax), %xmm3, %xmm3 0x8f,0xe9,0x70,0x96,0x2c,0x08 = vpshld %xmm1, (%rax, %rcx), %xmm5 0x8f,0xe9,0x70,0x94,0xda = vpshlb %xmm1, %xmm2, %xmm3 0x8f,0xe9,0xf8,0x94,0x39 = vpshlb (%rcx), %xmm0, %xmm7 0x8f,0xe9,0x68,0x94,0x1c,0x10 = vpshlb %xmm2, (%rax, %rdx), %xmm3 0x8f,0xe9,0x40,0x99,0xdd = vpshaw %xmm7, %xmm5, %xmm3 0x8f,0xe9,0xe8,0x99,0x08 = vpshaw (%rax), %xmm2, %xmm1 0x8f,0xe9,0x78,0x99,0x5c,0x08,0x08 = vpshaw %xmm0, 8(%rax, %rcx), %xmm3 0x8f,0xe9,0x58,0x9b,0xe4 = vpshaq %xmm4, %xmm4, %xmm4 0x8f,0xe9,0xe8,0x9b,0x01 = vpshaq (%rcx), %xmm2, %xmm0 0x8f,0xe9,0x48,0x9b,0x2c,0x08 = vpshaq %xmm6, (%rax, %rcx), %xmm5 0x8f,0xe9,0x50,0x9a,0xc4 = vpshad %xmm5, %xmm4, %xmm0 0x8f,0xe9,0xe8,0x9a,0x28 = vpshad (%rax), %xmm2, %xmm5 0x8f,0xe9,0x68,0x9a,0x28 = vpshad %xmm2, (%rax), %xmm5 0x8f,0xe9,0x70,0x98,0xc1 = vpshab %xmm1, %xmm1, %xmm0 0x8f,0xe9,0xd8,0x98,0x01 = vpshab (%rcx), %xmm4, %xmm0 0x8f,0xe9,0x50,0x98,0x19 = vpshab %xmm5, (%rcx), %xmm3 0x8f,0xe9,0xe0,0x91,0x30 = vprotw (%rax), %xmm3, %xmm6 0x8f,0xe9,0x50,0x91,0x0c,0x08 = vprotw %xmm5, (%rax, %rcx), %xmm1 0x8f,0xe9,0x78,0x91,0xd1 = vprotw %xmm0, %xmm1, %xmm2 0x8f,0xe8,0x78,0xc1,0x09,0x2a = vprotw $42, (%rcx), %xmm1 0x8f,0xe8,0x78,0xc1,0x20,0x29 = vprotw $41, (%rax), %xmm4 0x8f,0xe8,0x78,0xc1,0xd9,0x28 = vprotw $40, %xmm1, %xmm3 0x8f,0xe9,0xf0,0x93,0x10 = vprotq (%rax), %xmm1, %xmm2 0x8f,0xe9,0xf0,0x93,0x14,0x08 = vprotq (%rax, %rcx), %xmm1, %xmm2 0x8f,0xe9,0x78,0x93,0xd1 = vprotq %xmm0, %xmm1, %xmm2 0x8f,0xe8,0x78,0xc3,0x10,0x2a = vprotq $42, (%rax), %xmm2 0x8f,0xe8,0x78,0xc3,0x14,0x08,0x2a = vprotq $42, (%rax, %rcx), %xmm2 0x8f,0xe8,0x78,0xc3,0xd1,0x2a = vprotq $42, %xmm1, %xmm2 0x8f,0xe9,0xf8,0x92,0x18 = vprotd (%rax), %xmm0, %xmm3 0x8f,0xe9,0x68,0x92,0x24,0x08 = vprotd %xmm2, (%rax, %rcx), %xmm4 0x8f,0xe9,0x50,0x92,0xd3 = vprotd %xmm5, %xmm3, %xmm2 0x8f,0xe8,0x78,0xc2,0x31,0x2b = vprotd $43, (%rcx), %xmm6 0x8f,0xe8,0x78,0xc2,0x3c,0x08,0x2c = vprotd $44, (%rax, %rcx), %xmm7 0x8f,0xe8,0x78,0xc2,0xe4,0x2d = vprotd $45, %xmm4, %xmm4 0x8f,0xe9,0xe8,0x90,0x29 = vprotb (%rcx), %xmm2, %xmm5 0x8f,0xe9,0x50,0x90,0x24,0x08 = vprotb %xmm5, (%rax, %rcx), %xmm4 0x8f,0xe9,0x58,0x90,0xd3 = vprotb %xmm4, %xmm3, %xmm2 0x8f,0xe8,0x78,0xc0,0x18,0x2e = vprotb $46, (%rax), %xmm3 0x8f,0xe8,0x78,0xc0,0x3c,0x08,0x2f = vprotb $47, (%rax, %rcx), %xmm7 0x8f,0xe8,0x78,0xc0,0xed,0x30 = vprotb $48, %xmm5, %xmm5 0x8f,0xe8,0x60,0xb6,0xe2,0x10 = vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4 0x8f,0xe8,0x60,0xb6,0x20,0x10 = vpmadcswd %xmm1, (%rax), %xmm3, %xmm4 0x8f,0xe8,0x48,0xa6,0xe4,0x10 = vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4 0x8f,0xe8,0x60,0xa6,0x24,0x08,0x10 = vpmadcsswd %xmm1, (%rax, %rcx), %xmm3, %xmm4 0x8f,0xe8,0x50,0x95,0xe2,0x00 = vpmacsww %xmm0, %xmm2, %xmm5, %xmm4 0x8f,0xe8,0x48,0x95,0x20,0x10 = vpmacsww %xmm1, (%rax), %xmm6, %xmm4 0x8f,0xe8,0x48,0x96,0xfd,0x40 = vpmacswd %xmm4, %xmm5, %xmm6, %xmm7 0x8f,0xe8,0x70,0x96,0x10,0x00 = vpmacswd %xmm0, (%rax), %xmm1, %xmm2 0x8f,0xe8,0x68,0x85,0xcb,0x40 = vpmacssww %xmm4, %xmm3, %xmm2, %xmm1 0x8f,0xe8,0x40,0x85,0x39,0x60 = vpmacssww %xmm6, (%rcx), %xmm7, %xmm7 0x8f,0xe8,0x58,0x86,0xd2,0x40 = vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2 0x8f,0xe8,0x70,0x86,0x44,0x08,0x08,0x00 = vpmacsswd %xmm0, 8(%rax, %rcx), %xmm1, %xmm0 0x8f,0xe8,0x68,0x87,0xe1,0x10 = vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4 0x8f,0xe8,0x48,0x87,0x29,0x70 = vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5 0x8f,0xe8,0x78,0x8f,0xca,0x30 = vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1 0x8f,0xe8,0x68,0x8f,0x1c,0x08,0x70 = vpmacssdqh %xmm7, (%rax, %rcx), %xmm2, %xmm3 0x8f,0xe8,0x60,0x8e,0xea,0x20 = vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5 0x8f,0xe8,0x70,0x8e,0x10,0x40 = vpmacssdd %xmm4, (%rax), %xmm1, %xmm2 0x8f,0xe8,0x48,0x97,0xf8,0x30 = vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7 0x8f,0xe8,0x60,0x97,0x69,0x08,0x50 = vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5 0x8f,0xe8,0x60,0x9f,0xd5,0x70 = vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2 0x8f,0xe8,0x68,0x9f,0x40,0x04,0x50 = vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0 0x8f,0xe8,0x58,0x9e,0xd6,0x40 = vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2 0x8f,0xe8,0x58,0x9e,0x1c,0x08,0x40 = vpmacsdd %xmm4, (%rax, %rcx), %xmm4, %xmm3 0x8f,0xe8,0x60,0xcd,0xe2,0x2a = vpcomw $42, %xmm2, %xmm3, %xmm4 0x8f,0xe8,0x60,0xcd,0x20,0x2a = vpcomw $42, (%rax), %xmm3, %xmm4 0x8f,0xe8,0x60,0xed,0xe9,0x2b = vpcomuw $43, %xmm1, %xmm3, %xmm5 0x8f,0xe8,0x78,0xed,0x34,0x08,0x2c = vpcomuw $44, (%rax, %rcx), %xmm0, %xmm6 0x8f,0xe8,0x60,0xef,0xfb,0x2d = vpcomuq $45, %xmm3, %xmm3, %xmm7 0x8f,0xe8,0x60,0xef,0x08,0x2e = vpcomuq $46, (%rax), %xmm3, %xmm1 0x8f,0xe8,0x70,0xee,0xd0,0x2f = vpcomud $47, %xmm0, %xmm1, %xmm2 0x8f,0xe8,0x48,0xee,0x58,0x04,0x30 = vpcomud $48, 4(%rax), %xmm6, %xmm3 0x8f,0xe8,0x58,0xec,0xeb,0x31 = vpcomub $49, %xmm3, %xmm4, %xmm5 0x8f,0xe8,0x48,0xec,0x11,0x32 = vpcomub $50, (%rcx), %xmm6, %xmm2 0x8f,0xe8,0x78,0xcf,0xeb,0x33 = vpcomq $51, %xmm3, %xmm0, %xmm5 0x8f,0xe8,0x70,0xcf,0x38,0x34 = vpcomq $52, (%rax), %xmm1, %xmm7 0x8f,0xe8,0x60,0xce,0xc3,0x35 = vpcomd $53, %xmm3, %xmm3, %xmm0 0x8f,0xe8,0x68,0xce,0x11,0x36 = vpcomd $54, (%rcx), %xmm2, %xmm2 0x8f,0xe8,0x58,0xcc,0xd6,0x37 = vpcomb $55, %xmm6, %xmm4, %xmm2 0x8f,0xe8,0x60,0xcc,0x50,0x08,0x38 = vpcomb $56, 8(%rax), %xmm3, %xmm2 0x8f,0xe8,0x60,0xa3,0xe2,0x10 = vpperm %xmm1, %xmm2, %xmm3, %xmm4 0x8f,0xe8,0xe0,0xa3,0x20,0x20 = vpperm (%rax), %xmm2, %xmm3, %xmm4 0x8f,0xe8,0x60,0xa3,0x20,0x10 = vpperm %xmm1, (%rax), %xmm3, %xmm4 0x8f,0xe8,0x60,0xa2,0xe2,0x10 = vpcmov %xmm1, %xmm2, %xmm3, %xmm4 0x8f,0xe8,0xe0,0xa2,0x20,0x20 = vpcmov (%rax), %xmm2, %xmm3, %xmm4 0x8f,0xe8,0x60,0xa2,0x20,0x10 = vpcmov %xmm1, (%rax), %xmm3, %xmm4 0x8f,0xe8,0x64,0xa2,0xe2,0x10 = vpcmov %ymm1, %ymm2, %ymm3, %ymm4 0x8f,0xe8,0xe4,0xa2,0x20,0x20 = vpcmov (%rax), %ymm2, %ymm3, %ymm4 0x8f,0xe8,0x64,0xa2,0x20,0x10 = vpcmov %ymm1, (%rax), %ymm3, %ymm4 0xc4,0xe3,0x71,0x49,0xfa,0x51 = vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7 0xc4,0xe3,0xe1,0x49,0x20,0x32 = vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4 0xc4,0xe3,0xdd,0x49,0x70,0x08,0x03 = vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6 0xc4,0xe3,0x71,0x49,0x04,0x08,0x30 = vpermil2pd $0, %xmm3, (%rax, %rcx), %xmm1, %xmm0 0xc4,0xe3,0x65,0x49,0xe2,0x11 = vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4 0xc4,0xe3,0x65,0x49,0x20,0x12 = vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4 0xc4,0xe3,0x69,0x48,0xcb,0x40 = vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1 0xc4,0xe3,0xe1,0x48,0x40,0x04,0x21 = vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 0xc4,0xe3,0xd5,0x48,0x30,0x12 = vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6 0xc4,0xe3,0x61,0x48,0x20,0x13 = vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4 0xc4,0xe3,0x6d,0x48,0xd4,0x40 = vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2 0xc4,0xe3,0x75,0x49,0x40,0x04,0x11 = vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0 capstone-sys-0.15.0/capstone/suite/README000064400000000000000000000020000072674642500162040ustar 00000000000000This directory contains some tools used by developers of Capstone project. Average users should ignore all the contents here. - arm/ Test some ARM's special input. - MC/ Input used to test various architectures & modes. - benchmark.py This script benchmarks Python binding by disassembling some random code. - test_*.sh Run all the tests and send the output to external file to be compared later. This is useful when we want to verify if a commit (wrongly) changes the disassemble result. - compile_all.sh Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) & report the result as pass or fail. - fuzz.py This simple script disassembles random code for all archs (or selected arch) in order to find segfaults. - test_mc.sh This script compares the output of Capstone with LLVM's llvm-mc with the input coming from MC/. This relies on test_mc.py to do all the hard works. - x86odd.py Test some tricky X86 instructions. - ppcbranch.py Test some tricky branch PPC instructions. capstone-sys-0.15.0/capstone/suite/arm/Makefile000064400000000000000000000003560072674642500175570ustar 00000000000000# Sample Makefile for Capstone Disassembly Engine LIBNAME = capstone test_arm_regression: test_arm_regression.o ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ %.o: %.c ${CC} -c -I../../include $< -o $@ clean: rm -rf *.o test_arm_regression capstone-sys-0.15.0/capstone/suite/arm/test_arm_regression.c000064400000000000000000000214320072674642500223370ustar 00000000000000/* Capstone Disassembler Engine */ /* By David Hogarty, 2014 */ // the following must precede stdio (woo, thanks msft) #if defined(_MSC_VER) && _MSC_VER < 1900 #define _CRT_SECURE_NO_WARNINGS #define snprintf _snprintf #endif #include #include #include #include #include static csh handle; struct platform { cs_arch arch; cs_mode mode; unsigned char *code; size_t size; char *comment; int syntax; }; static char *hex_string(unsigned char *str, size_t len) { // returns a malloced string that has the hex version of the string in it // null if failed to malloc char *hex_out; size_t i; hex_out = (char *) malloc(len*2 + 1); // two ascii characters per input character, plus trailing null if (!hex_out) { goto Exit; } for (i = 0; i < len; ++i) { snprintf(hex_out + (i*2), 2, "%02x", str[i]); } hex_out[len*2] = 0; // trailing null Exit: return hex_out; } static void snprint_insn_detail(char * buf, size_t * cur, size_t * left, cs_insn *ins) { size_t used = 0; #define _this_printf(...) \ { \ size_t used = 0; \ used = snprintf(buf + *cur, *left, __VA_ARGS__); \ *left -= used; \ *cur += used; \ } cs_arm *arm; int i; // detail can be NULL on "data" instruction if SKIPDATA option is turned ON if (ins->detail == NULL) return; arm = &(ins->detail->arm); if (arm->op_count) _this_printf("\top_count: %u\n", arm->op_count); for (i = 0; i < arm->op_count; i++) { cs_arm_op *op = &(arm->operands[i]); switch((int)op->type) { default: break; case ARM_OP_REG: _this_printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); break; case ARM_OP_IMM: _this_printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); break; case ARM_OP_FP: _this_printf("\t\toperands[%u].type: FP = %f\n", i, op->fp); break; case ARM_OP_MEM: _this_printf("\t\toperands[%u].type: MEM\n", i); if (op->mem.base != X86_REG_INVALID) _this_printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base)); if (op->mem.index != X86_REG_INVALID) _this_printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index)); if (op->mem.scale != 1) _this_printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale); if (op->mem.disp != 0) _this_printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); break; case ARM_OP_PIMM: _this_printf("\t\toperands[%u].type: P-IMM = %u\n", i, op->imm); break; case ARM_OP_CIMM: _this_printf("\t\toperands[%u].type: C-IMM = %u\n", i, op->imm); break; } if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { if (op->shift.type < ARM_SFT_ASR_REG) { // shift with constant value _this_printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value); } else { // shift with register _this_printf("\t\t\tShift: %u = %s\n", op->shift.type, cs_reg_name(handle, op->shift.value)); } } } if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) { _this_printf("\tCode condition: %u\n", arm->cc); } if (arm->update_flags) { _this_printf("\tUpdate-flags: True\n"); } if (arm->writeback) { _this_printf("\tWrite-back: True\n"); } #undef _this_printf } static void print_insn_detail(cs_insn *ins) { char a_buf[2048]; size_t cur=0, left=2048; snprint_insn_detail(a_buf, &cur, &left, ins); printf("%s\n", a_buf); } struct invalid_code { unsigned char *code; size_t size; char *comment; }; #define MAX_INVALID_CODES 16 struct invalid_instructions { cs_arch arch; cs_mode mode; char *platform_comment; int num_invalid_codes; struct invalid_code invalid_codes[MAX_INVALID_CODES]; }; static void test_invalids() { struct invalid_instructions invalids[] = {{ CS_ARCH_ARM, CS_MODE_THUMB, "Thumb", 1, {{ (unsigned char *)"\xbd\xe8\x1e\xff", 4, "invalid thumb2 pop because sp used and because both pc and lr are " "present at the same time" }}, }}; struct invalid_instructions * invalid = NULL; uint64_t address = 0x1000; cs_insn *insn; int i; int j; size_t count; printf("\nShould be invalid\n" "-----------------\n"); for (i = 0; i < sizeof(invalids)/sizeof(invalids[0]); i++) { cs_err err; invalid = invalids + i; err = cs_open(invalid->arch, invalid->mode, &handle); if (err) { printf("Failed on cs_open() with error returned: %u\n", err); continue; } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME); for (j = 0; j < invalid->num_invalid_codes; ++j) { struct invalid_code *invalid_code = NULL; char *hex_str = NULL; invalid_code = invalid->invalid_codes + j; hex_str = hex_string(invalid_code->code, invalid_code->size); printf("%s %s: %s\n", invalid->platform_comment, hex_str, invalid_code->comment); free(hex_str); count = cs_disasm(handle, invalid_code->code, invalid_code->size, address, 0, &insn ); if (count) { size_t k; printf(" ERROR:\n"); for (k = 0; k < count; k++) { printf(" 0x%"PRIx64":\t%s\t%s\n", insn[k].address, insn[k].mnemonic, insn[k].op_str); print_insn_detail(&insn[k]); } cs_free(insn, count); } else { printf(" SUCCESS: invalid\n"); } } cs_close(&handle); } } struct valid_code { unsigned char *code; size_t size; uint32_t start_addr; char *expected_out; char *comment; }; #define MAX_VALID_CODES 16 struct valid_instructions { cs_arch arch; cs_mode mode; char *platform_comment; int num_valid_codes; struct valid_code valid_codes[MAX_VALID_CODES]; }; static void test_valids() { struct valid_instructions valids[] = {{ CS_ARCH_ARM, CS_MODE_THUMB, "Thumb", 3, {{ (unsigned char *)"\x00\xf0\x26\xe8", 4, 0x352, "0x352:\tblx\t#0x3a0\n" "\top_count: 1\n" "\t\toperands[0].type: IMM = 0x3a0\n", "thumb2 blx with misaligned immediate" }, { (unsigned char *)"\x05\xdd", 2, 0x1f0, "0x1f0:\tble\t#0x1fe\n" "\top_count: 1\n" "\t\toperands[0].type: IMM = 0x1fe\n" "\tCode condition: 14\n", "thumb b cc with thumb-aligned target" }, { (unsigned char *)"\xbd\xe8\xf0\x8f", 4, 0, "0x0:\tpop.w\t{r4, r5, r6, r7, r8, r9, r10, r11, pc}\n" "\top_count: 9\n" "\t\toperands[0].type: REG = r4\n" "\t\toperands[1].type: REG = r5\n" "\t\toperands[2].type: REG = r6\n" "\t\toperands[3].type: REG = r7\n" "\t\toperands[4].type: REG = r8\n" "\t\toperands[5].type: REG = r9\n" "\t\toperands[6].type: REG = r10\n" "\t\toperands[7].type: REG = r11\n" "\t\toperands[8].type: REG = pc\n", "thumb2 pop that should be valid" }, } }}; struct valid_instructions * valid = NULL; uint64_t address = 0x1000; cs_insn *insn; int i; int j; size_t count; for (i = 0; i < sizeof(valids)/sizeof(valids[0]); i++) { cs_err err; valid = valids + i; err = cs_open(valid->arch, valid->mode, &handle); if (err) { printf("Failed on cs_open() with error returned: %u\n", err); continue; } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME); #define _this_printf(...) \ { \ size_t used = 0; \ used = snprintf(tmp_buf + cur, left, __VA_ARGS__); \ left -= used; \ cur += used; \ } printf("\nShould be valid\n" "---------------\n"); for (j = 0; j < valid->num_valid_codes; ++j) { char tmp_buf[2048]; size_t left = 2048; size_t cur = 0; size_t used = 0; int success = 0; char * hex_str = NULL; struct valid_code * valid_code = NULL; valid_code = valid->valid_codes + j; hex_str = hex_string(valid_code->code, valid_code->size); printf("%s %s @ 0x%04x: %s\n %s", valid->platform_comment, hex_str, valid_code->start_addr, valid_code->comment, valid_code->expected_out); count = cs_disasm(handle, valid_code->code, valid_code->size, valid_code->start_addr, 0, &insn ); if (count) { size_t k; size_t max_len = 0; size_t tmp_len = 0; for (k = 0; k < count; k++) { _this_printf( "0x%"PRIx64":\t%s\t%s\n", insn[k].address, insn[k].mnemonic, insn[k].op_str ); snprint_insn_detail(tmp_buf, &cur, &left, &insn[k]); } max_len = strlen(tmp_buf); tmp_len = strlen(valid_code->expected_out); if (tmp_len > max_len) { max_len = tmp_len; } if (memcmp(tmp_buf, valid_code->expected_out, max_len)) { printf( " ERROR: '''\n%s''' does not match" " expected '''\n%s'''\n", tmp_buf, valid_code->expected_out ); } else { printf(" SUCCESS: valid\n"); } cs_free(insn, count); } else { printf("ERROR: invalid\n"); } } cs_close(&handle); } #undef _this_prinf } int main() { test_invalids(); test_valids(); return 0; } capstone-sys-0.15.0/capstone/suite/autogen_x86imm.py000075500000000000000000000066640072674642500205770ustar 00000000000000#!/usr/bin/python # By Nguyen Anh Quynh, 2015 # This tool extract sizes of immediadte operands from X86 instruction names. # Syntax: ./autogen_x86imm.py # Gather immediate sizes to put into X86ImmSize.inc OUTPUT = "../arch/X86/X86ImmSize.inc" f = open("../arch/X86/X86GenInstrInfo.inc") f2 = open(OUTPUT, "w") for line in f.readlines(): tmp = line.strip().split("=") if len(tmp) == 2: # X86_xxx = nnn, name = tmp[0].strip() if name == "X86_INSTRUCTION_LIST_END": # no more instructions break if name.endswith("_DB"): # pseudo instruction continue if "_LOCK_" in name or "BEXTR" in name: # exception continue if name.startswith("X86_"): # instruction if name.endswith("16mi8"): f2.write("{2, %s},\n" %name) elif name.endswith("16ri8"): f2.write("{2, %s},\n" %name) elif name.endswith("32ri8"): f2.write("{4, %s},\n" %name) elif name.endswith("32mi8"): f2.write("{4, %s},\n" %name) elif name.endswith("64i32"): f2.write("{8, %s},\n" %name) elif name.endswith("64mi32"): f2.write("{8, %s},\n" %name) elif name.endswith("64ri32"): f2.write("{8, %s},\n" %name) elif name.endswith("64ri8"): f2.write("{8, %s},\n" %name) elif name.endswith("64mi8"): f2.write("{8, %s},\n" %name) elif name.endswith("16rmi8"): f2.write("{2, %s},\n" %name) elif name.endswith("32rmi8"): f2.write("{4, %s},\n" %name) elif name.endswith("16rri8"): f2.write("{2, %s},\n" %name) elif name.endswith("32rri8"): f2.write("{4, %s},\n" %name) elif name.endswith("64rmi8"): f2.write("{8, %s},\n" %name) elif name.endswith("64rmi32"): f2.write("{8, %s},\n" %name) elif name.endswith("64rri32"): f2.write("{8, %s},\n" %name) elif name.endswith("64rri8"): f2.write("{8, %s},\n" %name) elif name.endswith("32ri64"): # special case f2.write("{8, %s},\n" %name) elif name.endswith("16i8"): # special case f2.write("{2, %s},\n" %name) elif name.endswith("32i8"): # special case f2.write("{4, %s},\n" %name) elif name.endswith("64i16"): # special case f2.write("{8, %s},\n" %name) elif name.endswith("64i8"): # special case f2.write("{8, %s},\n" %name) elif name.endswith("i8") or "i8_" in name: f2.write("{1, %s},\n" %name) elif "8ri" in name or "8mi" in name: f2.write("{1, %s},\n" %name) elif name.endswith("i16") or "i16_" in name: f2.write("{2, %s},\n" %name) elif "16ri" in name or "16mi" in name: f2.write("{2, %s},\n" %name) elif name.endswith("i32") or "i32_" in name: f2.write("{4, %s},\n" %name) elif "32ri" in name or "32mi" in name: f2.write("{4, %s},\n" %name) elif name.endswith("i64") or "i64_" in name: f2.write("{8, %s},\n" %name) elif "64ri" in name or "64mi" in name: f2.write("{8, %s},\n" %name) f.close() f2.close() print("Generated %s" %OUTPUT) capstone-sys-0.15.0/capstone/suite/benchmark/Makefile000064400000000000000000000003560072674642500207320ustar 00000000000000# Sample Makefile for Capstone Disassembly Engine LIBNAME = capstone test_iter_benchmark: test_iter_benchmark.o ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ %.o: %.c ${CC} -c -I../../include $< -o $@ clean: rm -rf *.o test_iter_benchmark capstone-sys-0.15.0/capstone/suite/benchmark/test_iter_benchmark.c000064400000000000000000000102270072674642500234500ustar 00000000000000/* Capstone Disassembler Engine */ /* By bughoho , 2015> */ #include #include #include #include #include static void test() { #define X86_CODE32 "\x53\x8B\xDC\x83\xEC\x08\x83\xE4\xF0\x83\xC4\x04\x55\x8B\x6B\x04\x89\x6C\x24\x04\x8B\xEC\x83\xEC\x78\xA1\x90\xA3\x4B\x01\x33\xC5 \ \x89\x45\xFC\x8B\x41\x04\x0F\x28\x05\x80\x30\x20\x01\x0F\x29\x45\xD0\x0F\x28\x05\x50\xAB\x1E\x01\x89\x4D\x90\x89\x45\xB8\x0F\x29 \ \x45\xE0\x56\x8B\x73\x08\x57\xC7\x06\x00\x00\x00\x00\xC7\x46\x04\x00\x00\x00\x00\xC7\x46\x08\x00\x00\x00\x00\xC7\x46\x0C\x00\x00 \ \x00\x00\x85\xC0\x0F\x84\xCB\x01\x00\x00\x33\xFF\x8D\x64\x24\x00\x8B\x01\x8B\x0C\x07\x89\x4D\xBC\x85\xC9\x0F\x84\xA6\x01\x00\x00 \ \x8B\x43\x0C\x0F\x10\x00\x0F\x29\x45\xD0\x0F\x10\x40\x10\x0F\x29\x45\xE0\x8B\x01\x8B\x40\x08\xFF\xD0\xF3\x0F\x10\x65\xD0\x8D\x55 \ \xD0\xF3\x0F\x10\x55\xD4\xF3\x0F\x10\x6D\xE0\xF3\x0F\x10\x48\x10\xF3\x0F\x10\x00\xF3\x0F\x10\x5D\xE4\xF3\x0F\x59\xCA\x8B\x4D\xBC \ \xF3\x0F\x59\xC4\x52\x8D\x55\xC0\x52\xF3\x0F\x58\xC8\xF3\x0F\x11\x4D\xD0\xF3\x0F\x10\x48\x10\xF3\x0F\x10\x00\xF3\x0F\x59\xCB\xF3 \ \x0F\x59\xC5\xF3\x0F\x58\xC8\xF3\x0F\x11\x4D\xE0\x0F\x28\xCC\xF3\x0F\x59\x48\x04\xF3\x0F\x10\x40\x14\xF3\x0F\x59\xC2\xF3\x0F\x58 \ \xC8\xF3\x0F\x11\x4D\xD4\x0F\x28\xCD\xF3\x0F\x10\x40\x14\xF3\x0F\x59\x48\x04\xC7\x45\xE8\x00\x00\x00\x00\xF3\x0F\x59\xC3\xC7\x45 \ \xD8\x00\x00\x00\x00\xF3\x0F\x58\xC8\xF3\x0F\x11\x4D\xE4\xF3\x0F\x59\x60\x0C\xF3\x0F\x59\x50\x1C\xF3\x0F\x58\xE2\xF3\x0F\x58\x65 \ \xDC\xF3\x0F\x11\x65\xDC\xF3\x0F\x59\x68\x0C\xF3\x0F\x59\x58\x1C\xF3\x0F\x58\xEB\xF3\x0F\x58\x6D\xEC\xF3\x0F\x11\x6D\xEC\x8B\x01 \ \x8B\x80\xF8\x00\x00\x00\xFF\xD0\xF3\x0F\x10\x10\xF3\x0F\x10\x58\x08\x0F\x2F\xD3\xF3\x0F\x10\x40\x04\xF3\x0F\x10\x48\x0C\xF3\x0F \ \x11\x55\xA0\xF3\x0F\x11\x45\x94\xF3\x0F\x11\x5D\x98\xF3\x0F\x11\x4D\xBC\x0F\x83\x8E\x00\x00\x00\x0F\x2F\xC1\x0F\x83\x85\x00\x00 \ \x00\x8B\xCE\xE8\xE8\xAC\x86\xFF\xF3\x0F\x10\x65\xA0\x84\xC0\x75\x53\xF3\x0F\x10\x06\x0F\x2F\xC4\x77\x03\x0F\x28\xE0\xF3\x0F\x10 \ \x5E\x08\xF3\x0F\x10\x45\x98\x0F\x2F\xD8\x77\x03\x0F\x28\xD8\xF3\x0F\x10\x4E\x04\xF3\x0F\x10\x45\x94\x0F\x2F\xC8\x77\x03\x0F\x28 \ \xC1\xF3\x0F\x10\x4E\x0C\xF3\x0F\x10\x55\xBC\x0F\x2F\xCA\x77\x03\x0F\x28\xCA\xF3\x0F\x11\x46\x04\xF3\x0F\x11\x5E\x08\xF3\x0F\x11" /* i'm test on the ubuntu 15.04 vmware, * Sorry I haven't linux under the physical environment, * so the results may not be accurate. * * original version output: * bug@ubuntu:~/capstone/suite/benchmark$ make * cc -c -I../../include test_iter_benchmark.c -o test_iter_benchmark.o * cc test_iter_benchmark.o -O3 -Wall -lcapstone -o test_iter_benchmark * bug@ubuntu:~/capstone/suite/benchmark$ ./test_iter_benchmark * time used:6.017613 * * rebuild: * * bug@ubuntu:~/capstone$ make clean * bug@ubuntu:~/capstone$ sudo make install * bug@ubuntu:~/capstone$ cd suite/benchmark/ * bug@ubuntu:~/capstone/suite/benchmark$ make clean * bug@ubuntu:~/capstone/suite/benchmark$ make * * modified version output: * bug@ubuntu:~/capstone/suite/benchmark$ ./test_iter_benchmark * time used:5.003864 * * if we don't output format text string,like this: * //handle->printer(&mci, &ss, handle->printer_info); <-----cs.c line 700 * bug@ubuntu:~/capstone/suite/benchmark$ ./test_iter_benchmark * time used:2.059570 */ csh handle; uint64_t address; cs_insn *insn; int i; cs_err err; const uint8_t *code; size_t size; err = cs_open(CS_ARCH_X86, CS_MODE_32, &handle); if (err) { printf("Failed on cs_open() with error returned: %u\n", err); return; } cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL); cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); clock_t start, end; double timeUsed; start = clock(); int maxcount = 10000000; insn = cs_malloc(handle); for (i = 0; i < maxcount;) { code = (const uint8_t *)X86_CODE32; address = 0x1000; size = sizeof(X86_CODE32) - 1; while(cs_disasm_iter(handle, &code, &size, &address, insn)) { i++; } } cs_free(insn, 1); cs_close(&handle); end = clock(); timeUsed = (double)(end - start) / CLOCKS_PER_SEC; printf("time used:%f\n", timeUsed); } int main() { test(); return 0; } capstone-sys-0.15.0/capstone/suite/benchmark.py000075500000000000000000000071040072674642500176450ustar 00000000000000#!/usr/bin/python # Simple benchmark for Capstone by disassembling random code. By Nguyen Anh Quynh, 2014 # Syntax: # ./suite/benchmark.py --> Benchmark all archs # ./suite/benchmark.py x86 --> Benchmark all X86 (all 16bit, 32bit, 64bit) # ./suite/benchmark.py x86-32 --> Benchmark X86-32 arch only # ./suite/benchmark.py arm --> Benchmark all ARM (arm, thumb) # ./suite/benchmark.py aarch64 --> Benchmark ARM-64 # ./suite/benchmark.py mips --> Benchmark all Mips (32bit, 64bit) # ./suite/benchmark.py ppc --> Benchmark PPC from capstone import * from time import time from random import randint import sys # file providing code to disassemble FILE = '/usr/bin/python' all_tests = ( (CS_ARCH_X86, CS_MODE_16, "X86-16 (Intel syntax)", 0), (CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT), (CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0), (CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0), (CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0), (CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0), (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0), (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0), (CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0), (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0), (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0), (CS_ARCH_SYSZ, 0, "SystemZ", 0), (CS_ARCH_XCORE, 0, "XCore", 0), (CS_ARCH_M68K, 0, "M68K", 0), (CS_ARCH_RISCV, 0, "RISCV", 0), ) # for debugging def to_hex(s): return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK def get_code(f, size): code = f.read(size) if len(code) != size: # reached end-of-file? # then reset file position to begin-of-file f.seek(0) code = f.read(size) return code def cs(md, code): insns = md.disasm(code, 0) # uncomment below line to speed up this function 200 times! # return for i in insns: if i.address == 0x100000: print i def cs_lite(md, code): insns = md.disasm_lite(code, 0) for (addr, size, mnem, ops) in insns: if addr == 0x100000: print i cfile = open(FILE) for (arch, mode, comment, syntax) in all_tests: try: request = sys.argv[1] if not request in comment.lower(): continue except: pass print("Platform: %s" %comment) try: md = Cs(arch, mode) #md.detail = True if syntax != 0: md.syntax = syntax # warm up few times cfile.seek(0) for i in xrange(3): code = get_code(cfile, 128) #print to_hex(code) #print cs(md, code) # start real benchmark c_t = 0 for i in xrange(50000): code = get_code(cfile, 128) #print to_hex(code) #print t1 = time() cs(md, code) c_t += time() - t1 print "Benchmark - full obj:", c_t, "seconds" print cfile.seek(0) c_t = 0 for i in xrange(50000): code = get_code(cfile, 128) #print to_hex(code) #print t1 = time() cs_lite(md, code) c_t += time() - t1 print "Benchmark - lite:", c_t, "seconds" print except CsError as e: print("ERROR: %s" %e) capstone-sys-0.15.0/capstone/suite/capstone_get_setup.c000064400000000000000000000027670072674642500214070ustar 00000000000000/* Retrieve architectures compiled in Capstone. By Nguyen Anh Quynh, 2019. Compile this code with: $ cc -o capstone_get_setup capstone_get_setup.c -lcapstone On default Capstone build, this code prints out the below output: $ capstone_get_setup x86=1 arm=1 arm64=1 mips=1 ppc=1 sparc=1 sysz=1 xcore=1 m68k=1 tms320c64x=1 m680x=1 evm=1 wasm=1 mos65xx=1 bpf=1 */ #include #include int main() { if (cs_support(CS_ARCH_X86)) { printf("x86=1 "); } if (cs_support(CS_ARCH_ARM)) { printf("arm=1 "); } if (cs_support(CS_ARCH_ARM64)) { printf("arm64=1 "); } if (cs_support(CS_ARCH_MIPS)) { printf("mips=1 "); } if (cs_support(CS_ARCH_PPC)) { printf("ppc=1 "); } if (cs_support(CS_ARCH_SPARC)) { printf("sparc=1 "); } if (cs_support(CS_ARCH_SYSZ)) { printf("sysz=1 "); } if (cs_support(CS_ARCH_XCORE)) { printf("xcore=1 "); } if (cs_support(CS_ARCH_M68K)) { printf("m68k=1 "); } if (cs_support(CS_ARCH_TMS320C64X)) { printf("tms320c64x=1 "); } if (cs_support(CS_ARCH_M680X)) { printf("m680x=1 "); } if (cs_support(CS_ARCH_EVM)) { printf("evm=1 "); } if (cs_support(CS_ARCH_WASM)) { printf("wasm=1 "); } if (cs_support(CS_ARCH_MOS65XX)) { printf("mos65xx=1 "); } if (cs_support(CS_ARCH_BPF)) { printf("bpf=1 "); } if (cs_support(CS_ARCH_RISCV)) { printf("riscv=1 "); } if (cs_support(CS_SUPPORT_DIET)) { printf("diet=1 "); } if (cs_support(CS_SUPPORT_X86_REDUCE)) { printf("x86_reduce=1 "); } printf("\n"); return 0; } capstone-sys-0.15.0/capstone/suite/compile_all.sh000075500000000000000000000010410072674642500201470ustar 00000000000000#! /bin/bash # By Daniel Godas-Lopez. export LD_LIBRARY_PATH=. for x in default nix32 cross-win32 cross-win64 cygwin-mingw32 cygwin-mingw64 bsd clang gcc; do echo -n "Compiling: $x ... " ./compile.sh $x &> /dev/null if [ $? == 0 ]; then echo "-> PASS" else echo -e "-> FAILED\n" continue fi for t in test test_arm test_arm64 test_detail test_mips test_x86 test_ppc; do ./tests/$t &> /dev/null if [ $? -eq 0 ]; then echo " Run $t -> PASS" else echo " Run $t -> FAIL" fi done echo done make clean &> /dev/null capstone-sys-0.15.0/capstone/suite/cstest/Makefile000064400000000000000000000003650072674642500203050ustar 00000000000000SOURCE = src INCLUDE = include BUILD = build LIBRARY = -lcmocka -lcapstone -L../.. all: rm -rf $(BUILD) mkdir $(BUILD) $(CC) $(SOURCE)/*.c -I$(INCLUDE) -o $(BUILD)/cstest $(LIBRARY) cstest: $(BUILD)/cstest -d ../MC clean: rm -rf $(BUILD) capstone-sys-0.15.0/capstone/suite/cstest/README.md000064400000000000000000000022030072674642500201150ustar 00000000000000# Regression testing This directory contains a tool for regression testing core of Capstone ## Dependency - MacOS users can install cmocka with: ``` brew install cmocka ``` - Or download & build from source code [Cmocka](https://git.cryptomilk.org/projects/cmocka.git) - Build Cmocka ``` cd cmocka_dir mkdir build cd build cmake .. make sudo make isntall ``` ## Build - Build `cstest` ``` cd suite/cstest make ``` ## Usage - Usage: `cstest [-e] [-f ] [-d ]` - `-e` : test all commented test - Test for all closed issues ``` cd suite/cstest ./build/cstest -f ./issues.cs ``` - Test for some input from LLVM ``` cd suite/cstest ./build/cstest -f ../MC/AArch64/basic-a64-instructions.s.cs ``` - Test for all cs file in a folder ``` cd suite/cstest ./build/cstest -d ../MC ``` - Test all ``` cd suite/cstest make cstest ``` ## Report tool - Usage `cstest_report.py [-Dc] -t [-f ] [-d ]` - `-D` : print details - `-c` : auto comment out failed test - Example: ``` ./cstest_report.py -t build/cstest -d ../MC/PowerPC/ ./cstest_report.py -t build/cstest -f issues.cs ``` capstone-sys-0.15.0/capstone/suite/cstest/build_cstest.sh000064400000000000000000000004050072674642500216600ustar 00000000000000#!/bin/sh cd cmocka && mkdir build && cd build if [ "$(uname)" = Darwin ]; then cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install else # Linux cmake -DCMAKE_INSTALL_PREFIX=/usr .. && make -j2 && sudo make install fi cd ../.. && make capstone-sys-0.15.0/capstone/suite/cstest/cstest_report.py000075500000000000000000000052360072674642500221240ustar 00000000000000#!/usr/bin/python import re import sys import getopt from subprocess import Popen, PIPE from pprint import pprint as ppr import os def Usage(s): print 'Usage: {} -t [-f ] [-d ]'.format(s) sys.exit(-1) def get_report_file(toolpath, filepath, getDetails, cmt_out): cmd = [toolpath, '-f', filepath] process = Popen(cmd, stdout=PIPE, stderr=PIPE) stdout, stderr = process.communicate() # stdout failed_tests = [] # print '---> stdout\n', stdout # print '---> stderr\n', stderr matches = re.finditer(r'\[\s+RUN\s+\]\s+(.*)\n\[\s+FAILED\s+\]', stdout) for match in matches: failed_tests.append(match.group(1)) # stderr counter = 0 details = [] for line in stderr.split('\n'): if '[ PASSED ] 0 test(s).' in line: break elif 'LINE' in line: continue elif 'ERROR' in line and ' --- ' in line: parts = line.split(' --- ') try: details.append((parts[1], failed_tests[counter], parts[2])) except IndexError: details.append(('', 'Unknown test', line.split(' --- ')[1])) counter += 1 else: continue print '\n[-] There are/is {} failed test(s)'.format(len(details)) if len(details) > 0 and getDetails: print '[-] Detailed report for {}:\n'.format(filepath) for c, f, d in details: print '\t[+] {}: {}\n\t\t{}\n'.format(f, c, d) print '\n' return 0 elif len(details) > 0: for c, f, d in details: if len(f) > 0 and cmt_out is True: tmp_cmd = ['sed', '-E', '-i.bak', 's/({})(.*)/\/\/ \\1\\2/g'.format(c), filepath] sed_proc = Popen(tmp_cmd, stdout=PIPE, stderr=PIPE) sed_proc.communicate() tmp_cmd2 = ['rm', '-f', filepath + '.bak'] rm_proc = Popen(tmp_cmd2, stdout=PIPE, stderr=PIPE) rm_proc.communicate() return 0; return 1 def get_report_folder(toolpath, folderpath, details, cmt_out): result = 1 for root, dirs, files in os.walk(folderpath): path = root.split(os.sep) for f in files: if f.split('.')[-1] == 'cs': print '[-] Target:', f, result *= get_report_file(toolpath, os.sep.join(x for x in path) + os.sep + f, details, cmt_out) sys.exit(result ^ 1) if __name__ == '__main__': Done = False details = False toolpath = '' cmt_out = False try: opts, args = getopt.getopt(sys.argv[1:], "ct:f:d:D") for opt, arg in opts: if opt == '-f': result = get_report_file(toolpath, arg, details, cmt_out) if result == 0: sys.exit(1) Done = True elif opt == '-d': get_report_folder(toolpath, arg, details, cmt_out) Done = True elif opt == '-t': toolpath = arg elif opt == '-D': details = True elif opt == '-c': cmt_out = True except getopt.GetoptError: Usage(sys.argv[0]) if Done is False: Usage(sys.argv[0]) capstone-sys-0.15.0/capstone/suite/cstest/include/capstone_test.h000064400000000000000000000027140072674642500233140ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #ifndef CAPSTONE_TEST_H #define CAPSTONE_TEST_H #include #include #include #include #include #include #include #include #include "helper.h" #include "factory.h" #define cs_assert_err(expect, err) \ do { \ cs_err __err = err; \ if (__err != expect) { \ fail_msg("%s",cs_strerror(__err)); \ } \ } while (0) #define cs_assert_success(err) cs_assert_err(CS_ERR_OK, err) #define cs_assert_fail(err) \ do { \ cs_err __err = err; \ if (__err == CS_ERR_OK) { \ fail_msg("%s",cs_strerror(__err)); \ } \ } while (0) #define NUMARCH 10 #define NUMMODE 35 #define NUMOPTION 41 #define MAXMEM 1024 typedef struct { const char *str; unsigned int value; } single_dict; typedef struct { const char *str; unsigned int first_value; unsigned int second_value; } double_dict; extern char *(*function)(csh *, cs_mode, cs_insn*); int get_index(double_dict d[], unsigned size, const char *str); int get_value(single_dict d[], unsigned size, const char *str); void test_single_MC(csh *handle, int mc_mode, char *line); void test_single_issue(csh *handle, cs_mode mode, char *line, int detail); int set_function(int arch); #endif /* CAPSTONE_TEST_H */ capstone-sys-0.15.0/capstone/suite/cstest/include/factory.h000064400000000000000000000022220072674642500221020ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #ifndef FACTORY_H #define FACTORY_H #include #include "helper.h" char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_x86(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins); #endif /* FACTORY_H */ capstone-sys-0.15.0/capstone/suite/cstest/include/helper.h000064400000000000000000000014200072674642500217110ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #ifndef HELPER_H #define HELPER_H #include #include #include #include #include #include #include "capstone_test.h" #define X86_16 0 #define X86_32 1 #define X86_64 2 char **split(char *str, char *delim, int *size); void print_strs(char **list_str, int size); void free_strs(char **list_str, int size); void add_str(char **src, const char *format, ...); void trim_str(char *src); void replace_hex(char *src); void replace_negative(char *src, int mode); const char *get_filename_ext(const char *filename); char *readfile(const char *filename); void listdir(const char *name, char ***files, int *num_files); #endif /* HELPER_H */ capstone-sys-0.15.0/capstone/suite/cstest/issues.cs000064400000000000000000001013110072674642500205000ustar 00000000000000!# issue 1504 movhps qword ptr !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0f,0x16,0x08 == movhps xmm1, qword ptr [rax] ; Opcode:0x0f 0x16 0x00 0x00 !# issue 1505 opcode 0f !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0f,0xa5,0xc2 == shld edx, eax, cl ; Opcode:0x0f 0xa5 0x00 0x00 !# issue 1478 tbegin. !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x7c,0x20,0x05,0x1d == tbegin. 1 ; Update-CR0: True !# issue 970 PPC bdnzt lt !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x41,0x00,0xff,0xac == bdnzt lt, 0xffffffffffffffac ; operands[0].type: REG = cr0lt !# issue 970 PPC bdnzt eq !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x41,0x02,0xff,0xac == bdnzt eq, 0xffffffffffffffac ; operands[0].type: REG = cr0eq !# issue 969 PPC bdnzflr operand 2 !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x4c,0x10,0x00,0x20 == bdnzflr 4*cr4+lt ; operands[0].type: REG = cr4lt 0x41,0x82,0x00,0x10 == beq 0x10 ; Groups: jump !# issue 1481 ARM64 LDR operand2 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0xe9,0x03,0x40,0xf9 == ldr x9, [sp] ; operands[1].mem.base: REG = sp !# issue 968 PPC absolute branch: bdnzla !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None 0x1000: 0x42,0x00,0x12,0x37 == bdnzla 0x1234 !# issue 968 PPC absolute branch: bdzla !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None 0x1000: 0x42,0x40,0x12,0x37 == bdzla 0x1234 !# issue X86 xrelease xchg !# CS_ARCH_X86, CS_MODE_32, None 0xf3,0x87,0x03 == xrelease xchg dword ptr [ebx], eax !# issue X86 xacquire xchg !# CS_ARCH_X86, CS_MODE_32, None 0xf2,0x87,0x03 == xacquire xchg dword ptr [ebx], eax !# issue X86 xrelease !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0xf0,0x31,0x1f == xrelease lock xor dword ptr [rdi], ebx !# issue 1477 X86 xacquire !# CS_ARCH_X86, CS_MODE_64, None 0xf2,0xf0,0x31,0x1f == xacquire lock xor dword ptr [rdi], ebx !# issue PPC JUMP group !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x41,0x82,0x00,0x10 == beq 0x10 ; Groups: jump !# issue 1468 PPC bdnz !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None 0x101086c: 0x42,0x00,0xff,0xf8 == bdnz 0x1010864 !# issue PPC bdnzt !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None 0x1000: 0x41,0x00,0xff,0xac == bdnzt lt, 0xfac !# issue 1469 PPC CRx !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x4c,0x02,0x39,0x82 == crxor cr0lt, cr0eq, cr1un ; operands[0].type: REG = cr0lt !# issue 1468 B target !# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None 0x1000: 0x4b,0xff,0xf8,0x00 == b 0x800 !# issue 1456 test alt 1 !# CS_ARCH_X86, CS_MODE_32, None 0xf6,0x08,0x00 == test byte ptr [eax], 0 !# issue 1456 test alt 2 !# CS_ARCH_X86, CS_MODE_32, None 0xf7,0x08,0x00,0x00,0x00,0x00 == test dword ptr [eax], 0 !# issue 1472 lock sub !# CS_ARCH_X86, CS_MODE_32, None 0xF0,0x2B,0x45,0x08 == lock sub eax, dword ptr [ebp + 8] !# issue 1472 lock or !# CS_ARCH_X86, CS_MODE_32, None 0xF0,0x0B,0x45,0x08 == lock or eax, dword ptr [ebp + 8] !# issue 1472 lock and !# CS_ARCH_X86, CS_MODE_32, None 0xF0,0x23,0x45,0x08 == lock and eax, dword ptr [ebp + 8] !# issue 1472 lock add !# CS_ARCH_X86, CS_MODE_32, None 0xF0,0x03,0x45,0x08 == lock add eax, dword ptr [ebp + 8] !# issue 1456 MOV dr !# CS_ARCH_X86, CS_MODE_32, None 0x0f,0x23,0x00 == mov dr0, eax !# issue 1456 MOV dr !# CS_ARCH_X86, CS_MODE_32, None 0x0f,0x21,0x00 == mov eax, dr0 !# issue 1456 MOV cr !# CS_ARCH_X86, CS_MODE_32, None 0x0f,0x22,0x00 == mov cr0, eax !# issue 1472 lock adc !# CS_ARCH_X86, CS_MODE_32, None 0xf0,0x12,0x45,0x08 == lock adc al, byte ptr [ebp + 8] !# issue 1456 xmmword !# CS_ARCH_X86, CS_MODE_32, None 0x66,0x0f,0x2f,0x00 == comisd xmm0, xmmword ptr [eax] !# issue 1456 ARM printPKHASRShiftImm !# CS_ARCH_ARM, CS_MODE_THUMB, None 0xca,0xea,0x21,0x06 == pkhtb r6, sl, r1, asr #0x20 !# issue 1456 EIZ !# CS_ARCH_X86, CS_MODE_32, None 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00 == lea esi, [esi] !# issue 1456 ARM POP !# CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, None 0x04,0x10,0x9d,0xe4 == pop {r1} !# issue 1456 !# CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0x31,0x02,0xa0,0xe1 == lsr r0, r1, r2 ; operands[2].type: REG = r2 !# issue 1456 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0x0c,0x00,0x80,0x12 == mov w12, #-1 ; operands[1].type: IMM = 0xffffffffffffffff 0xb8,0x00,0x00,0x00,0x00 == movl $0, %eax !# issue 1456 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0xb8,0x00,0x00,0x00,0x00 == movl $0, %eax 0xd1,0x5e,0x48 == rcrl $1, 0x48(%esi) !# issue 1456 !# CS_ARCH_X86, CS_MODE_32, None 0xd1,0x5e,0x48 == rcr dword ptr [esi + 0x48], 1 !# issue 1456 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0xd1,0x5e,0x48 == rcrl $1, 0x48(%esi) !# issue 1456 !# CS_ARCH_X86, CS_MODE_32, None 0x62,0x00 == bound eax, qword ptr [eax] !# issue 1454 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0xf0,0x0f,0xb1,0x1e == lock cmpxchg dword ptr [esi], ebx ; Registers read: eax esi ebx !# issue 1452 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; Vector Arrangement Specifier: 0xb !# issue 1452 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; Vector Arrangement Specifier: 0xd !# issue 1452 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0x20,0x3c,0x03,0x0e == umov w0, v1.b[1] ; Vector Arrangement Specifier: 0x4 !# issue 1452 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL 0x20,0x3c,0x06,0x0e == umov w0, v1.h[1] ; Vector Arrangement Specifier: 0x8 !# issue 1211 !# CS_ARCH_X86, CS_MODE_64, None 0xc4,0xe1,0xf8,0x90,0xc0 == kmovq k0, k0 !# issue 1211 !# CS_ARCH_X86, CS_MODE_64, None 0xc4,0xe1,0xfb,0x92,0xc3 == kmovq k0, rbx !# issue 1211 !# CS_ARCH_X86, CS_MODE_64, None 0x62,0xf1,0x7d,0x48,0x74,0x83,0x12,0x00,0x00,0x00 == vpcmpeqb k0, zmm0, zmmword ptr [rbx + 0x12] !# issue 1211 !# CS_ARCH_X86, CS_MODE_64, None 0x62,0xf2,0x7d,0x48,0x30,0x43,0x08 == vpmovzxbw zmm0, ymmword ptr [rbx + 0x100] !# issue x86 BND register (OSS-fuzz #13467) !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0f,0x1a,0x1a == bndldx bnd3, [edx] ; operands[0].type: REG = bnd3 !# issue 1335 !# CS_ARCH_X86, CS_MODE_32, None 0x0f,0x1f,0xc0 == nop eax !# issue 1335 !# CS_ARCH_X86, CS_MODE_64, None 0x48,0x0f,0x1f,0x00 == nop qword ptr [rax] !# issue 1259 !# CS_ARCH_X86, CS_MODE_64, None 0x0f,0x0d,0x44,0x11,0x40 == prefetch byte ptr [rcx + rdx + 0x40] !# issue 1259 !# CS_ARCH_X86, CS_MODE_64, None 0x41,0x0f,0x0d,0x44,0x12,0x40 == prefetch byte ptr [r10 + rdx + 0x40] !# issue 1304 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x66,0x0f,0x7f,0x4c,0x24,0x40 == movdqa xmmword ptr [rsp + 0x40], xmm1 ; operands[0].access: WRITE !# issue 1304 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x66,0x0f,0x7e,0x04,0x24 == movd dword ptr [rsp], xmm0 ; operands[0].access: WRITE !# issue 1304 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0xf3,0x41,0x0f,0x7f,0x4d,0x00 == movdqu xmmword ptr [r13], xmm1 ; operands[0].access: WRITE !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x48,0x0f,0x1e,0xc8 == rdsspq rax !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0x1e,0xc8 == rdsspd eax !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x48,0x0f,0xae,0xe8 == incsspq rax !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0xae,0xe8 == incsspd eax !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0x01,0xea == saveprevssp !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0x01,0x28 == rstorssp dword ptr [rax] !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0x67,0xf3,0x0f,0x01,0x28 == rstorssp dword ptr [eax] !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0x48,0x0f,0x38,0xf6,0x00 == wrssq qword ptr [rax], rax !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0x67,0x0f,0x38,0xf6,0x00 == wrssd dword ptr [eax], eax !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0x01,0xe8 == setssbsy !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0xae,0x30 == clrssbsy dword ptr [rax] !# issue 1346 !# CS_ARCH_X86, CS_MODE_64, None 0x67,0xf3,0x0f,0xae,0x30 == clrssbsy dword ptr [eax] !# issue 1206 !# CS_ARCH_X86, CS_MODE_64, None 0xc4,0xe2,0x7d,0x5a,0x0c,0x0e == vbroadcasti128 ymm1, xmmword ptr [rsi + rcx] !# issue xchg 16bit !# CS_ARCH_X86, CS_MODE_16, None 0x91 == xchg cx, ax !# issue ROL 1, ATT syntax !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x66,0x48,0xf3,0xd1,0xc0 == rolw $1, %ax !# issue 1129 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0x1e,0xfa == endbr64 !# issue 1129 !# CS_ARCH_X86, CS_MODE_32, None 0xf3,0x0f,0x1e,0xfa == endbr64 !# issue 1129 !# CS_ARCH_X86, CS_MODE_64, None 0xf3,0x0f,0x1e,0xfb == endbr32 !# issue 1129 !# CS_ARCH_X86, CS_MODE_32, None 0xf3,0x0f,0x1e,0xfb == endbr32 !# issue x64 jmp !# CS_ARCH_X86, CS_MODE_64, None 0x1000: 0xeb,0xfe == jmp 0x1000 !# issue x64att jmp !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x1000: 0xeb,0xfe == jmp 0x1000 !# issue x32 jmp !# CS_ARCH_X86, CS_MODE_32, None 0x1000: 0xeb,0xfe == jmp 0x1000 !# issue x32att jmp !# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT 0x1000: 0xeb,0xfe == jmp 0x1000 !# issue 1389 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x66,0x0f,0x73,0xf9,0x01 == pslldq xmm1, 1 ; operands[1].size: 1 !# issue 1389 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_DETAIL 0x66,0x0f,0x73,0xf9,0x01 == pslldq $1, %xmm1 ; operands[0].size: 1 !# issue x64 unsigned !# CS_ARCH_X86, CS_MODE_64, CS_OPT_UNSIGNED 0x66,0x83,0xc0,0x80 == add ax, 0xff80 !# issue x64att unsigned !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_UNSIGNED 0x66,0x83,0xc0,0x80 == addw $0xff80, %ax !# issue 1323 !# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL 0x0: 0x70,0x47,0x00 == bx lr ; op_count: 1 ; operands[0].type: REG = lr ; operands[0].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: thumb jump !# issue 1317 !# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL 0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.index: REG = r1 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r0 r1 ; Groups: thumb2 jump !# issue 1308 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 == cmp dword ptr [rip + 0x2175a1], 4 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x83 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x3d ; disp: 0x2175a1 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x4 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rip ; operands[0].mem.disp: 0x2175a1 ; operands[0].size: 4 ; operands[0].access: READ ; operands[1].type: IMM = 0x4 ; operands[1].size: 4 ; Registers read: rip ; Registers modified: rflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF !# issue 1262 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0x0f,0x95,0x44,0x24,0x5e == setne byte ptr [rsp + 0x5e] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x95 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x5e ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x5e ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF !# issue 1262 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0x0f,0x94,0x44,0x24,0x1f == sete byte ptr [rsp + 0x1f] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x94 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x1f ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x1f ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF !# issue 1263 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x67,0x48,0x89,0x18 == mov qword ptr [eax], rbx !# issue 1263 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x67,0x48,0x8b,0x03 == mov rax, qword ptr [ebx] !# issue 1255 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0xdb,0x7c,0x24,0x40 == fstp xword ptr [rsp + 0x40] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdb 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x40 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x40 ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu !# issue 1255 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0xdd,0xd9 == fstp st(1) ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdd 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0xd9 ; disp: 0x0 ; sib: 0x0 ; op_count: 1 ; operands[0].type: REG = st(1) ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers modified: fpsw st(1) ; EFLAGS: MOD_CF PRIOR_SF PRIOR_AF PRIOR_PF !# issue 1255 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0xdf,0x7c,0x24,0x68 == fistp qword ptr [rsp + 0x68] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xdf 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x68 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x68 ; operands[0].size: 8 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: RESET_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu !# issue 1221 !# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x0: 0x55,0x48,0x89,0xe5 == call 0x55222794 !# issue 1144 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None 0x0: 0x00,0x00,0x02,0xb6 == tbz x0, #0x20, #0x4000 !# issue 1144 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None 0x0: 0x00,0x00,0x04,0xb6 == tbz x0, #0x20, #0xffffffffffff8000 !# issue 1144 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None 0x0: 0x00,0x00,0x02,0xb7 == tbnz x0, #0x20, #0x4000 !# issue 1144 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None 0x0: 0x00,0x00,0x04,0xb7 == tbnz x0, #0x20, #0xffffffffffff8000 !# issue 826 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x0b,0x00,0x00,0x0a == beq #0x34 ; op_count: 1 ; operands[0].type: IMM = 0x34 ; Code condition: 1 ; Registers read: pc ; Registers modified: pc ; Groups: branch_relative arm jump !# issue 1047 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0: 0x48,0x83,0xe4,0xf0 == andq $0xfffffffffffffff0, %rsp !# issue 959 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xa0,0x28,0x57,0x88,0x7c == mov al, byte ptr [0x7c885728] !# issue 950 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0x66,0xa3,0x94,0x90,0x04,0x08 == mov word ptr [0x8049094], ax ; Prefix:0x00 0x00 0x66 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x8049094 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x8049094 ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: ax !# issue 938 !# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, None 0x0: 0x70,0x00,0xb2,0xff == sd $s2, 0x70($sp) !# issue 915 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0xf0,0x0f,0x1f,0x00 == lock nop dword ptr [rax] // !# issue 913 // !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x04,0x10,0x9d,0xe4 == pop {r1} ; op_count: 1 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; Write-back: True ; Registers read: sp ; Registers modified: sp r1 ; Groups: arm !# issue 884 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0: 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 == addq %fs:0, %rax !# issue 872 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0xeb,0x3e == bnd jmp 0x41 !# issue 861 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x01,0x81,0xa0,0xfc == stc2 p1, c8, [r0], #4 ; op_count: 4 ; operands[0].type: P-IMM = 1 ; operands[1].type: C-IMM = 8 ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].access: READ ; operands[3].type: IMM = 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 ; Groups: prev8 !# issue 852 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0x64,0xa3,0x00,0x00,0x00,0x00 == mov dword ptr fs:[0], eax ; Prefix:0x00 0x64 0x00 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.segment: REG = fs ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: fs eax !# issue 825 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x0e,0xf0,0xa0,0xe1 == mov pc, lr ; op_count: 2 ; operands[0].type: REG = pc ; operands[0].access: WRITE ; operands[1].type: REG = lr ; operands[1].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: arm !# issue 813 !# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, None 0x0: 0xF6,0xC0,0x04,0x01 == movt r4, #0x801 !# issue 809 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff == movaps xmmword ptr [rbp - 0x210], xmm1 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x0f 0x29 0x00 0x00 ; rex: 0x0 ; addr_size: 8 ; modrm: 0x8d ; disp: 0xfffffffffffffdf0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rbp ; operands[0].mem.disp: 0xfffffffffffffdf0 ; operands[0].size: 16 ; operands[0].access: WRITE ; operands[1].type: REG = xmm1 ; operands[1].size: 16 ; operands[1].access: READ ; Registers read: rbp xmm1 ; Groups: sse1 !# issue 807 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe == sldt word ptr [rax - 0x17589ea] !# issue 806 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x0f,0x35 == sysexit !# issue 805 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0: 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe == lgs -0x17589ea(%rax), %r8 !# issue 804 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0: 0x66,0x48,0xf3,0xd1,0xc0 == rolw $1, %ax !# issue 789 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0: 0x8e,0x1e == movw (%rsi), %ds !# issue 767 !# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL 0x0: 0xb1,0xe8,0xfc,0x07 == ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, sb, sl} ; op_count: 10 ; operands[0].type: REG = r1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r2 ; operands[1].access: WRITE ; operands[2].type: REG = r3 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: REG = r5 ; operands[4].access: WRITE ; operands[5].type: REG = r6 ; operands[5].access: WRITE ; operands[6].type: REG = r7 ; operands[6].access: WRITE ; operands[7].type: REG = r8 ; operands[7].access: WRITE ; operands[8].type: REG = sb ; operands[8].access: WRITE ; operands[9].type: REG = sl ; operands[9].access: WRITE ; Write-back: True ; Registers read: r1 ; Registers modified: r1 r2 r3 r4 r5 r6 r7 r8 sb sl ; Groups: thumb2 !# issue 760 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = pc ; operands[1].access: WRITE ; Registers read: sp ; Registers modified: sp r1 pc ; Groups: arm !# issue 750 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x0e,0x00,0x20,0xe9 == stmdb r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r1 ; operands[2].type: REG = r2 ; operands[3].type: REG = r3 ; Write-back: True ; Registers read: r0 ; Groups: arm !# issue 747 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x0e,0x00,0xb0,0xe8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: arm !# issue 747 !# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL 0x0: 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: thumb thumb1only !# issue 746 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x89,0x00,0x2d,0xe9 == push {r0, r3, r7} ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r3 ; operands[1].access: READ ; operands[2].type: REG = r7 ; operands[2].access: READ ; Registers read: sp r0 r3 r7 ; Registers modified: sp ; Groups: arm !# issue 744 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = pc ; operands[1].access: WRITE ; Registers read: sp ; Registers modified: sp r1 pc ; Groups: arm !# issue 741 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x83,0xff,0xf7 == cmp edi, -9 !# issue 717 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT 0x0: 0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00 == movq 0, %rax !# issue 711 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xa3,0x44,0xb0,0x00,0x10 == mov dword ptr [0x1000b044], eax ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xa3 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x1000b044 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1000b044 ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: eax !# issue 613 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0xd9,0x74,0x24,0xd8 == fnstenv [rsp - 0x28] !# issue 554 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xe7,0x84 == out 0x84, eax !# issue 554 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xe5,0x8c == in eax, 0x8c !# issue 545 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0x95 == xchg ebp, eax ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x95 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ebp ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ | WRITE ; Registers read: ebp eax ; Registers modified: ebp eax ; Groups: not64bitmode !# issue 544 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xdf,0x30 == fbstp tbyte ptr [eax] !# issue 544 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xdf,0x20 == fbld tbyte ptr [eax] !# issue 541 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x80,0xf8,0xff,0xff == movabs rax, 0xfffff88000000000 !# issue 499 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80 == movabs rax, 0x8000000000000000 !# issue 492 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xff,0x18 == call ptr [eax] !# issue 492 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xff,0x28 == jmp ptr [eax] !# issue 492 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x0f,0xae,0x04,0x24 == fxsave [esp] !# issue 492 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x0f,0xae,0x0c,0x24 == fxrstor [esp] !# issue 470 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x0f,0x01,0x05,0xa0,0x90,0x04,0x08 == sgdt [0x80490a0] !# issue 470 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x0f,0x01,0x0d,0xa7,0x90,0x04,0x08 == sidt [0x80490a7] !# issue 470 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x0f,0x01,0x15,0xa0,0x90,0x04,0x08 == lgdt [0x80490a0] !# issue 470 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x0f,0x01,0x1d,0xa7,0x90,0x04,0x08 == lidt [0x80490a7] !# issue 459 !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL 0x0: 0xd3,0x20,0x11,0xe1 == ldrsb r2, [r1, -r3] ; op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.index: REG = r3 ; operands[1].mem.scale: -1 ; Subtracted: True ; Registers read: r1 r3 ; Registers modified: r2 ; Groups: arm !# issue 456 !# CS_ARCH_X86, CS_MODE_16, None 0x0: 0xe8,0x35,0x64 == call 0x6438 !# issue 456 !# CS_ARCH_X86, CS_MODE_16, None 0x0: 0xe9,0x35,0x64 == jmp 0x6438 !# issue 456 !# CS_ARCH_X86, CS_MODE_16, None 0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b !# issue 456 !# CS_ARCH_X86, CS_MODE_16, None 0x0: 0x66,0xe8,0x35,0x64,0x93,0x53 == call 0x5393643b !# issue 456 !# CS_ARCH_X86, CS_MODE_16, None 0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b !# issue 456 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x66,0xe8,0x35,0x64 == call 0x6439 !# issue 456 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643a !# issue 456 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x66,0xe9,0x35,0x64 == jmp 0x6439 !# issue 458 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xA1,0x12,0x34,0x90,0x90 == mov eax, dword ptr [0x90903412] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xa1 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x90903412 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = eax ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.disp: 0x90903412 ; operands[1].size: 4 ; operands[1].access: READ ; Registers modified: eax !# issue 454 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0x6c == repne insb byte ptr es:[edi], dx !# issue 454 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0x6d == repne insd dword ptr es:[edi], dx !# issue 454 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0x6e == repne outsb dx, byte ptr [esi] !# issue 454 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0x6f == repne outsd dx, dword ptr [esi] !# issue 454 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0xac == repne lodsb al, byte ptr [esi] !# issue 454 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf2,0xad == repne lodsd eax, dword ptr [esi] !# issue 450 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xff,0x2d,0x34,0x35,0x23,0x01 == jmp ptr [0x1233534] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xff 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x2d ; disp: 0x1233534 ; sib: 0x0 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1233534 ; operands[0].size: 6 ; Groups: jump !# issue 448 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xea,0x12,0x34,0x56,0x78,0x9a,0xbc == ljmp 0xbc9a:0x78563412 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xea 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 2 ; imms[1]: 0xbc9a ; imms[2]: 0x78563412 ; op_count: 2 ; operands[0].type: IMM = 0xbc9a ; operands[0].size: 2 ; operands[1].type: IMM = 0x78563412 ; operands[1].size: 4 ; Groups: not64bitmode jump !# issue 426 !# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None 0x0: 0xbb,0x70,0x00,0x00 == popc %g0, %i5 !# issue 358 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xe8,0xe3,0xf6,0xff,0xff == call 0xfffff6e8 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xe8 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xfffff6e8 ; op_count: 1 ; operands[0].type: IMM = 0xfffff6e8 ; operands[0].size: 4 ; Registers read: esp eip ; Registers modified: esp ; Groups: call branch_relative not64bitmode !# issue 353 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xe6,0xa2 == out 0xa2, al ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xe6 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xa2 ; op_count: 2 ; operands[0].type: IMM = 0xa2 ; operands[0].size: 1 ; operands[1].type: REG = al ; operands[1].size: 1 ; operands[1].access: READ ; Registers read: al !# issue 305 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x34,0x8b == xor al, 0x8b !# issue 298 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xf3,0x90 == pause !# issue 298 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0x66,0xf3,0xf2,0x0f,0x59,0xff == mulsd xmm7, xmm7 // !# issue 298 // !# CS_ARCH_X86, CS_MODE_32, None // 0x0: 0xf2,0x66,0x0f,0x59,0xff == mulpd xmm7, xmm7 !# issue 294 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xc1,0xe6,0x08 == shl esi, 8 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xc1 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0xe6 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x8 ; op_count: 2 ; operands[0].type: REG = esi ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x8 ; operands[1].size: 1 ; Registers read: esi ; Registers modified: eflags esi ; EFLAGS: MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF UNDEF_AF !# issue 285 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0x3c,0x12,0x80 == cmp al, 0x12 ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x3c 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x12 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: READ ; operands[1].type: IMM = 0x12 ; operands[1].size: 1 ; Registers read: al ; Registers modified: eflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF !# issue 265 !# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL 0x0: 0x52,0xf8,0x23,0x30 == ldr.w r3, [r2, r3, lsl #2] ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r3 ; operands[1].access: READ ; Shift: 2 = 2 ; Registers read: r2 r3 ; Registers modified: r3 ; Groups: thumb2 !# issue 264 !# CS_ARCH_ARM, CS_MODE_THUMB, None 0x0: 0x0c,0xbf == ite eq !# issue 264 !# CS_ARCH_ARM, CS_MODE_THUMB, None 0x0: 0x17,0x20 == movs r0, #0x17 !# issue 264 !# CS_ARCH_ARM, CS_MODE_THUMB, None 0x0: 0x4f,0xf0,0xff,0x30 == mov.w r0, #-1 !# issue 246 !# CS_ARCH_ARM, CS_MODE_THUMB, None 0x0: 0x52,0xf8,0x23,0xf0 == ldr.w pc, [r2, r3, lsl #2] !# issue 232 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0x8e,0x10 == mov ss, word ptr [eax] ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0x8e 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x10 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ss ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = eax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: eax ; Registers modified: ss ; Groups: privilege !# issue 231 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0x66,0x6b,0xc0,0x02 == imul ax, ax, 2 ; Prefix:0x00 0x00 0x66 0x00 ; Opcode:0x6b 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0xc0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x2 ; op_count: 3 ; operands[0].type: REG = ax ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; operands[2].type: IMM = 0x2 ; operands[2].size: 2 ; Registers read: ax ; Registers modified: eflags ax ; EFLAGS: MOD_CF MOD_SF MOD_OF UNDEF_ZF UNDEF_PF UNDEF_AF !# issue 230 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xec == in al, dx ; Prefix:0x00 0x00 0x00 0x00 ; Opcode:0xec 0x00 0x00 0x00 ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: WRITE ; operands[1].type: REG = dx ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: dx ; Registers modified: al !# issue 213 !# CS_ARCH_X86, CS_MODE_16, None 0x0: 0xea,0xaa,0xff,0x00,0xf0 == ljmp 0xf000:0xffaa !# issue 191 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0xc5,0xe8,0xc2,0x33,0x9b == vcmpps xmm6, xmm2, xmmword ptr [rbx], 0x9b !# issue 176 !# CS_ARCH_ARM, CS_MODE_ARM, None 0x0: 0xfd,0xff,0xff,0x1a == bne #0xfffffffc !# issue 151 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0x4d,0x8d,0x3d,0x02,0x00,0x00,0x00 == lea r15, [rip + 2] !# issue 151 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0xeb,0xb0 == jmp 0xffffffffffffffb2 !# issue 134 !# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x0: 0xe7,0x92,0x11,0x80 == ldr r1, [r2, r0, lsl #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r0 ; operands[1].access: READ ; Shift: 2 = 3 ; Registers read: r2 r0 ; Registers modified: r1 ; Groups: arm !# issue 133 !# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x0: 0xed,0xdf,0x2b,0x1b == vldr d18, [pc, #0x6c] ; op_count: 2 ; operands[0].type: REG = d18 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = pc ; operands[1].mem.disp: 0x6c ; operands[1].access: READ ; Registers read: pc ; Registers modified: d18 ; Groups: vfp2 !# issue 132 !# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x0: 0x49,0x19 == ldr r1, [pc, #0x64] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = pc ; operands[1].mem.disp: 0x64 ; operands[1].access: READ ; Registers read: pc ; Registers modified: r1 ; Groups: thumb thumb1only !# issue 130 !# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL 0x0: 0xe1,0xa0,0xf0,0x0e == mov pc, lr ; op_count: 2 ; operands[0].type: REG = pc ; operands[0].access: WRITE ; operands[1].type: REG = lr ; operands[1].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: arm !# issue 85 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None 0x0: 0xee,0x3f,0xbf,0x29 == stp w14, w15, [sp, #-8]! !# issue 82 !# CS_ARCH_X86, CS_MODE_64, None 0x0: 0xf2,0x66,0xaf == repne scasw ax, word ptr [rdi] !# issue 35 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xe8,0xc6,0x02,0x00,0x00 == call 0x2cb !# issue 8 !# CS_ARCH_X86, CS_MODE_32, None 0x0: 0xff,0x8c,0xf9,0xff,0xff,0x9b,0xf9 == dec dword ptr [ecx + edi*8 - 0x6640001] !# issue 29 !# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None 0x0: 0x00,0x00,0x00,0x4c == st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] capstone-sys-0.15.0/capstone/suite/cstest/src/arm64_detail.c000064400000000000000000000100210072674642500220410ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) { cs_arm64 *arm64; int i; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; uint8_t access; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; // detail can be NULL if SKIPDATA option is turned ON if (ins->detail == NULL) return result; arm64 = &(ins->detail->arm64); if (arm64->op_count) add_str(&result, " ; op_count: %u", arm64->op_count); for (i = 0; i < arm64->op_count; i++) { cs_arm64_op *op = &(arm64->operands[i]); switch(op->type) { default: break; case ARM64_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case ARM64_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64, i, op->imm); break; case ARM64_OP_FP: #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point add_str(&result, " ; operands[%u].type: FP = ", i); #else add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp); #endif break; case ARM64_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != ARM64_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.index != ARM64_REG_INVALID) add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); break; case ARM64_OP_CIMM: add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm); break; case ARM64_OP_REG_MRS: add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg); break; case ARM64_OP_REG_MSR: add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg); break; case ARM64_OP_PSTATE: add_str(&result, " ; operands[%u].type: PSTATE = 0x%x", i, op->pstate); break; case ARM64_OP_SYS: add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys); break; case ARM64_OP_PREFETCH: add_str(&result, " ; operands[%u].type: PREFETCH = 0x%x", i, op->prefetch); break; case ARM64_OP_BARRIER: add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier); break; } access = op->access; switch(access) { default: break; case CS_AC_READ: add_str(&result, " ; operands[%u].access: READ", i); break; case CS_AC_WRITE: add_str(&result, " ; operands[%u].access: WRITE", i); break; case CS_AC_READ | CS_AC_WRITE: add_str(&result, " ; operands[%u].access: READ | WRITE", i); break; } if (op->shift.type != ARM64_SFT_INVALID && op->shift.value) add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value); if (op->ext != ARM64_EXT_INVALID) add_str(&result, " ; Ext: %u", op->ext); if (op->vas != ARM64_VAS_INVALID) add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas); if (op->vector_index != -1) add_str(&result, " ; Vector Index: %u", op->vector_index); } if (arm64->update_flags) add_str(&result, " ; Update-flags: True"); if (arm64->writeback) add_str(&result, " ; Write-back: True"); if (arm64->cc) add_str(&result, " ; Code-condition: %u", arm64->cc); // Print out all registers accessed by this instruction (either implicit or explicit) if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { add_str(&result, " ; Registers read:"); for(i = 0; i < regs_read_count; i++) { add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); } } if (regs_write_count) { add_str(&result, " ; Registers modified:"); for(i = 0; i < regs_write_count; i++) { add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); } } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/arm_detail.c000064400000000000000000000104630072674642500217010ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins) { cs_arm *arm; int i; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; arm = &(ins->detail->arm); if (arm->op_count) add_str(&result, " ; op_count: %u", arm->op_count); for (i = 0; i < arm->op_count; i++) { cs_arm_op *op = &(arm->operands[i]); switch((int)op->type) { default: break; case ARM_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case ARM_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); break; case ARM_OP_FP: #if defined(_KERNEL_MODE) // Issue #681: Windows kernel does not support formatting float point add_str(&result, " ; operands[%u].type: FP = ", i); #else add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp); #endif break; case ARM_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != ARM_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.index != ARM_REG_INVALID) add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); if (op->mem.scale != 1) add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); if (op->mem.lshift != 0) add_str(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift); break; case ARM_OP_PIMM: add_str(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm); break; case ARM_OP_CIMM: add_str(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm); break; case ARM_OP_SETEND: add_str(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le"); break; case ARM_OP_SYSREG: add_str(&result, " ; operands[%u].type: SYSREG = %u", i, op->reg); break; } if (op->neon_lane != -1) { add_str(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane); } switch(op->access) { default: break; case CS_AC_READ: add_str(&result, " ; operands[%u].access: READ", i); break; case CS_AC_WRITE: add_str(&result, " ; operands[%u].access: WRITE", i); break; case CS_AC_READ | CS_AC_WRITE: add_str(&result, " ; operands[%u].access: READ | WRITE", i); break; } if (op->shift.type != ARM_SFT_INVALID && op->shift.value) { if (op->shift.type < ARM_SFT_ASR_REG) add_str(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value); else add_str(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value)); } if (op->vector_index != -1) { add_str(&result, " ; operands[%u].vector_index = %u", i, op->vector_index); } if (op->subtracted) add_str(&result, " ; Subtracted: True"); } if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) add_str(&result, " ; Code condition: %u", arm->cc); if (arm->update_flags) add_str(&result, " ; Update-flags: True"); if (arm->writeback) add_str(&result, " ; Write-back: True"); if (arm->cps_mode) add_str(&result, " ; CPSI-mode: %u", arm->cps_mode); if (arm->cps_flag) add_str(&result, " ; CPSI-flag: %u", arm->cps_flag); if (arm->vector_data) add_str(&result, " ; Vector-data: %u", arm->vector_data); if (arm->vector_size) add_str(&result, " ; Vector-size: %u", arm->vector_size); if (arm->usermode) add_str(&result, " ; User-mode: True"); if (arm->mem_barrier) add_str(&result, " ; Memory-barrier: %u", arm->mem_barrier); if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { add_str(&result, " ; Registers read:"); for(i = 0; i < regs_read_count; i++) { add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); } } if (regs_write_count) { add_str(&result, " ; Registers modified:"); for(i = 0; i < regs_write_count; i++) { add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); } } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/bpf_detail.c000064400000000000000000000035760072674642500217000ustar 00000000000000/* Capstone testing regression */ /* By david942j , 2019 */ #include #include "factory.h" static char * ext_name[] = { [BPF_EXT_LEN] = "#len", }; char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins) { cs_bpf *bpf; unsigned int i; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; bpf = &(ins->detail->bpf); if (bpf->op_count) add_str(&result, " ; op_count: %u", bpf->op_count); for (i = 0; i < bpf->op_count; i++) { cs_bpf_op *op = &(bpf->operands[i]); add_str(&result, " ; operands[%u].type: ", i); switch (op->type) { case BPF_OP_INVALID: add_str(&result, "INVALID"); break; case BPF_OP_REG: add_str(&result, "REG = %s", cs_reg_name(*handle, op->reg)); break; case BPF_OP_IMM: add_str(&result, "IMM = 0x%" PRIx64, op->imm); break; case BPF_OP_OFF: add_str(&result, "OFF = +0x%x", op->off); break; case BPF_OP_MEM: add_str(&result, "MEM [base=%s, disp=0x%x]", cs_reg_name(*handle, op->mem.base), op->mem.disp); break; case BPF_OP_MMEM: add_str(&result, "MMEM = M[0x%x]", op->mmem); break; case BPF_OP_MSH: add_str(&result, "MSH = 4*([0x%x]&0xf)", op->msh); break; case BPF_OP_EXT: add_str(&result, "EXT = %s", ext_name[op->ext]); break; } } if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { add_str(&result, " ; Registers read:"); for(i = 0; i < regs_read_count; i++) add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); } if (regs_write_count) { add_str(&result, " ; Registers modified:"); for(i = 0; i < regs_write_count; i++) add_str(&result, " %s", cs_reg_name(*handle, regs_write[i])); } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/capstone_test.c000064400000000000000000000173030072674642500224530ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "capstone_test.h" char *(*function)(csh *, cs_mode, cs_insn*) = NULL; void test_single_MC(csh *handle, int mc_mode, char *line) { char **list_part, **list_byte; int size_part, size_byte, size_data, size_insn; int i, count, count_noreg; unsigned char *code; cs_insn *insn; char tmp[MAXMEM], tmp_mc[MAXMEM], origin[MAXMEM], tmp_noreg[MAXMEM]; char **offset_opcode; int size_offset_opcode; unsigned long offset; char *p; list_part = split(line, " = ", &size_part); offset_opcode = split(list_part[0], ": ", &size_offset_opcode); if (size_offset_opcode > 1) { offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); list_byte = split(offset_opcode[1], ",", &size_byte); } else { offset = 0; list_byte = split(offset_opcode[0], ",", &size_byte); } code = (unsigned char *)malloc(size_byte * sizeof(char)); for (i = 0; i < size_byte; ++i) { code[i] = (unsigned char)strtol(list_byte[i], NULL, 16); } count = cs_disasm(*handle, code, size_byte, offset, 0, &insn); if (count == 0) { fprintf(stderr, "[ ERROR ] --- %s --- Failed to disassemble given code!\n", list_part[0]); free_strs(list_part, size_part); free_strs(offset_opcode, size_offset_opcode); free_strs(list_byte, size_byte); free(code); _fail(__FILE__, __LINE__); } if (count > 1) { fprintf(stderr, "[ ERROR ] --- %s --- Multiple instructions(%d) disassembling doesn't support!\n", list_part[0], count); free_strs(list_part, size_part); free_strs(offset_opcode, size_offset_opcode); free_strs(list_byte, size_byte); free(code); _fail(__FILE__, __LINE__); } for (p = list_part[1]; *p; ++p) *p = tolower(*p); for (p = list_part[1]; *p; ++p) if (*p == '\t') *p = ' '; trim_str(list_part[1]); strcpy(tmp_mc, list_part[1]); replace_hex(tmp_mc); replace_negative(tmp_mc, mc_mode); strcpy(tmp, insn[0].mnemonic); if (strlen(insn[0].op_str) > 0) { tmp[strlen(insn[0].mnemonic)] = ' '; strcpy(tmp + strlen(insn[0].mnemonic) + 1, insn[0].op_str); } trim_str(tmp); strcpy(origin, tmp); replace_hex(tmp); replace_negative(tmp, mc_mode); if (cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME) == CS_ERR_OK) { count_noreg = cs_disasm(*handle, code, size_byte, offset, 0, &insn); strcpy(tmp_noreg, insn[0].mnemonic); if (strlen(insn[0].op_str) > 0) { tmp_noreg[strlen(insn[0].mnemonic)] = ' '; strcpy(tmp_noreg + strlen(insn[0].mnemonic) + 1, insn[0].op_str); } trim_str(tmp_noreg); replace_hex(tmp_noreg); replace_negative(tmp_noreg, mc_mode); if (strcmp(tmp, tmp_mc) && strcmp(tmp_noreg, tmp_mc)) { fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" and \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc, tmp_noreg, tmp_mc); free_strs(list_part, size_part); free_strs(offset_opcode, size_offset_opcode); free_strs(list_byte, size_byte); free(code); cs_free(insn, count); _fail(__FILE__, __LINE__); } cs_option(*handle, CS_OPT_SYNTAX, 0); } else if (strcmp(tmp, tmp_mc)) { fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc); free_strs(list_part, size_part); free_strs(offset_opcode, size_offset_opcode); free_strs(list_byte, size_byte); free(code); cs_free(insn, count); _fail(__FILE__, __LINE__); } free_strs(list_part, size_part); free_strs(offset_opcode, size_offset_opcode); free_strs(list_byte, size_byte); free(code); cs_free(insn, count); } int get_value(single_dict d[], unsigned int size, const char *str) { int i; for (i = 0; i < size; ++i) if (!strcmp(d[i].str, str)) return d[i].value; return -1; } int get_index(double_dict d[], unsigned int size, const char *s) { int i; for (i = 0; i < size; ++i) { if (!strcmp(s, d[i].str)) return i; } return -1; } int set_function(int arch) { switch(arch) { case CS_ARCH_ARM: function = get_detail_arm; break; case CS_ARCH_ARM64: function = get_detail_arm64; break; case CS_ARCH_MIPS: function = get_detail_mips; break; case CS_ARCH_PPC: function = get_detail_ppc; break; case CS_ARCH_SPARC: function = get_detail_sparc; break; case CS_ARCH_SYSZ: function = get_detail_sysz; break; case CS_ARCH_X86: function = get_detail_x86; break; case CS_ARCH_XCORE: function = get_detail_xcore; break; case CS_ARCH_M68K: function = get_detail_m68k; break; case CS_ARCH_M680X: function = get_detail_m680x; break; case CS_ARCH_EVM: function = get_detail_evm; break; case CS_ARCH_MOS65XX: function = get_detail_mos65xx; break; case CS_ARCH_TMS320C64X: function = get_detail_tms320c64x; break; case CS_ARCH_BPF: function = get_detail_bpf; break; case CS_ARCH_RISCV: function = get_detail_riscv; break; default: return -1; } return 0; } void test_single_issue(csh *handle, cs_mode mode, char *line, int detail) { char **list_part, **list_byte, **list_part_cs_result, **list_part_issue_result; int size_part, size_byte, size_part_cs_result, size_part_issue_result; char *tmptmp; int i, count, j; unsigned char *code; cs_insn *insn; char *cs_result, *tmp, *p; char **offset_opcode; int size_offset_opcode; unsigned long offset; cs_result = (char *)malloc(sizeof(char)); cs_result[0] = '\0'; list_part = split(line, " == ", &size_part); offset_opcode = split(list_part[0], ": ", &size_offset_opcode); if (size_offset_opcode > 1) { offset = (unsigned int)strtol(offset_opcode[0], NULL, 16); list_byte = split(offset_opcode[1], ",", &size_byte); } else { offset = 0; list_byte = split(offset_opcode[0], ",", &size_byte); } code = (unsigned char *)malloc(sizeof(char) * size_byte); for (i = 0; i < size_byte; ++i) { code[i] = (unsigned char)strtol(list_byte[i], NULL, 16); } count = cs_disasm(*handle, code, size_byte, offset, 0, &insn); for (i = 0; i < count; ++i) { tmp = (char *)malloc(strlen(insn[i].mnemonic) + strlen(insn[i].op_str) + 100); strcpy(tmp, insn[i].mnemonic); if (strlen(insn[i].op_str) > 0) { tmp[strlen(insn[i].mnemonic)] = ' '; strcpy(tmp + strlen(insn[i].mnemonic) + 1, insn[i].op_str); } add_str(&cs_result, "%s", tmp); free(tmp); } if (detail == 1) { tmp = (*function)(handle, mode, insn); add_str(&cs_result, "%s", tmp); free(tmp); if (insn->detail->groups_count) { add_str(&cs_result, " ; Groups: "); for (j = 0; j < insn->detail->groups_count; j++) { add_str(&cs_result, "%s ", cs_group_name(*handle, insn->detail->groups[j])); } } } trim_str(cs_result); add_str(&cs_result, " ;"); // list_part_cs_result = split(cs_result, " ; ", &size_part_cs_result); for (p = list_part[1]; *p; ++p) if (*p == '\t') *p = ' '; list_part_issue_result = split(list_part[1], " ; ", &size_part_issue_result); for (i = 0; i < size_part_issue_result; ++i) { trim_str(list_part_issue_result[i]); memset(tmptmp, MAXMEM, 0); tmptmp = (char *)malloc(sizeof(char)); tmptmp[0] = '\0'; add_str(&tmptmp, "%s", list_part_issue_result[i]); add_str(&tmptmp, " ;"); if ((strstr(cs_result, tmptmp)) == NULL) { fprintf(stderr, "[ ERROR ] --- %s --- \"%s\" not in \"%s\"\n", list_part[0], list_part_issue_result[i], cs_result); cs_free(insn, count); free_strs(list_part, size_part); free_strs(list_byte, size_byte); free(cs_result); // free_strs(list_part_cs_result, size_part_cs_result); free_strs(list_part_issue_result, size_part_issue_result); free(tmptmp); _fail(__FILE__, __LINE__); } } cs_free(insn, count); free_strs(list_part, size_part); free_strs(list_byte, size_byte); free(cs_result); // free_strs(list_part_cs_result, size_part_cs_result); free_strs(list_part_issue_result, size_part_issue_result); } capstone-sys-0.15.0/capstone/suite/cstest/src/evm_detail.c000064400000000000000000000010360072674642500217050ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins) { cs_evm *evm; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; evm = &(ins->detail->evm); if (evm->pop) add_str(&result, " ; Pop: %u", evm->pop); if (evm->push) add_str(&result, " ; Push: %u", evm->push); if (evm->fee) add_str(&result, " ; Gas fee: %u", evm->fee); return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/helper.c000064400000000000000000000124610072674642500210570ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "helper.h" char **split(char *str, char *delim, int *size) { char **result; char *token, *src; int cnt; cnt = 0; src = str; result = NULL; while ((token = strstr(src, delim)) != NULL) { result = (char **)realloc(result, sizeof(char *) * (cnt + 1)); result[cnt] = (char *)calloc(1, sizeof(char) * (int)(token - src + 10)); memcpy(result[cnt], src, token - src); result[cnt][token - src] = '\0'; src = token + strlen(delim); cnt ++; } if (strlen(src) > 0) { result = (char **)realloc(result, sizeof(char *) * (cnt + 1)); result[cnt] = strdup(src); cnt ++; } *size = cnt; return result; } void print_strs(char **list_str, int size) { int i; printf("[+] Debug %d strings:\n", size); for (i = 0; i < size; ++i) printf("String %d'th: %s\n", i+1, list_str[i]); } void free_strs(char **list_str, int size) { int i; for (i = 0; i < size; ++i) free(list_str[i]); free(list_str); } const char *get_filename_ext(const char *filename) { const char *dot; dot = strrchr(filename, '.'); if (!dot || dot == filename) return ""; return dot + 1; } char *readfile(const char *filename) { char *result; FILE *fp; int size; fp = fopen(filename, "r"); if (fp == NULL) { puts("No such file"); exit(-1); } fseek(fp, 0, SEEK_END); size = ftell(fp); rewind(fp); result = (char *)calloc(1, sizeof(char) * size + 1); fread(result, size, 1, fp); result[size] = '\0'; fclose(fp); return result; } void add_str(char **src, const char *format, ...) { char *tmp; size_t len1, len2; va_list args; tmp = (char *)malloc(sizeof(char) * 1000); va_start(args, format); vsprintf(tmp, format, args); va_end(args); len1 = strlen(*src); len2 = strlen(tmp); *src = (char *)realloc(*src, sizeof(char) * (len1 + len2 + 10)); memcpy(*src + len1, tmp, len2 + 1); free(tmp); } void replace_hex(char *src) { char *tmp, *result, *found, *origin, *orig_found; int i, valid; unsigned long long int value; char *tmp_tmp; result = (char *)malloc(sizeof(char)); result[0] = '\0'; tmp = strdup(src); origin = tmp; while ((found = strstr(tmp, "0x")) != NULL) { orig_found = found; found += 2; value = 0; valid = 0; tmp_tmp = strndup(tmp, orig_found - tmp); while (*found != '\0' && isxdigit(*found)) { valid = 1; if (*found >= 'a' && *found <='f') value = value*0x10 + (*found - 'a' + 10); else value = value*0x10 + (*found - '0'); found++; } if (valid == 1) add_str(&result, "%s%llu", tmp_tmp, value); else add_str(&result, "%s0x", tmp_tmp); tmp = found; free(tmp_tmp); } add_str(&result, "%s", tmp); if (strlen(result) >= MAXMEM) { fprintf(stderr, "[ Error ] --- Buffer Overflow in replace_hex()\n"); free(result); free(origin); _fail(__FILE__, __LINE__); } strcpy(src, result); free(result); free(origin); } void replace_negative(char *src, int mode) { char *tmp, *result, *found, *origin, *orig_found; int i, cnt, valid; char *value, *tmp_tmp; unsigned short int tmp_short; unsigned int tmp_int; unsigned long int tmp_long; result = (char *)malloc(sizeof(char)); result[0] = '\0'; tmp = strdup(src); origin = tmp; while ((found = strstr(tmp, "-")) != NULL) { orig_found = found; found ++; valid = 0; value = strdup("-"); cnt = 2; while (*found != '\0' && isdigit(*found)) { valid = 1; value = (char *)realloc(value, cnt + 1); value[cnt - 1] = *found; value[cnt] = '\0'; cnt ++; found++; } tmp_tmp = strndup(tmp, orig_found - tmp); if (valid == 1) { *orig_found = '\0'; if (mode == X86_16) { sscanf(value, "%hu", &tmp_short); add_str(&result, "%s%hu", tmp_tmp, tmp_short); } else if (mode == X86_32) { sscanf(value, "%u", &tmp_int); add_str(&result, "%s%u", tmp_tmp, tmp_int); } else if (mode == X86_64) { sscanf(value, "%lu", &tmp_long); add_str(&result, "%s%lu", tmp_tmp, tmp_long); } } else add_str(&result, "%s-", tmp_tmp); tmp = found; free(value); free(tmp_tmp); } add_str(&result, "%s", tmp); if (strlen(result) >= MAXMEM) { fprintf(stderr, "[ Error ] --- Buffer Overflow in replace_negative()\n"); free(result); free(origin); _fail(__FILE__, __LINE__); } strcpy(src, result); free(result); free(origin); } void listdir(const char *name, char ***files, int *num_files) { DIR *dir; struct dirent *entry; int cnt; if (!(dir = opendir(name))) return; while ((entry = readdir(dir)) != NULL) { if (entry->d_type == DT_DIR) { char path[1024]; if (strcmp(entry->d_name, ".") == 0 || strcmp(entry->d_name, "..") == 0) continue; snprintf(path, sizeof(path), "%s/%s", name, entry->d_name); listdir(path, files, num_files); } else { cnt = *num_files; *files = (char **)realloc(*files, sizeof(char *) * (cnt + 1)); (*files)[cnt] = (char *)malloc(sizeof(char) * ( strlen(name) + 1 + strlen(entry->d_name) + 10)); sprintf((*files)[cnt], "%s/%s", name, entry->d_name); cnt ++; *num_files = cnt; } } closedir(dir); } void trim_str(char *str) { char tmp[MAXMEM]; int start, end, j, i; start = 0; end = strlen(str) - 1; j = 0; while (start < strlen(str) && isspace(str[start])) start++; while (end >= 0 && isspace(str[end])) end--; for (i = start; i <= end; ++i) tmp[j++] = str[i]; tmp[j] = '\0'; strcpy(str, tmp); return; } capstone-sys-0.15.0/capstone/suite/cstest/src/m680x_detail.c000064400000000000000000000070140072674642500220020ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" static const char *s_access[] = { "UNCHANGED", "READ", "WRITE", "READ ; WRITE", }; static void print_read_write_regs(char *result, csh *handle, cs_detail *detail) { int i; if (detail->regs_read_count > 0) { add_str(&result, "\treading from regs: "); for (i = 0; i < detail->regs_read_count; ++i) { if (i > 0) add_str(&result, ", "); add_str(&result, "%s", cs_reg_name(*handle, detail->regs_read[i])); } } if (detail->regs_write_count > 0) { add_str(&result, "\twriting to regs: "); for (i = 0; i < detail->regs_write_count; ++i) { if (i > 0) add_str(&result, ", "); add_str(&result, "%s", cs_reg_name(*handle, detail->regs_write[i])); } } } char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn) { cs_detail *detail = insn->detail; cs_m680x *m680x = NULL; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (detail == NULL) return result; m680x = &detail->m680x; if (m680x->op_count) add_str(&result, " ; op_count: %u", m680x->op_count); for (i = 0; i < m680x->op_count; i++) { cs_m680x_op *op = &(m680x->operands[i]); const char *comment; switch ((int)op->type) { default: break; case M680X_OP_REGISTER: comment = ""; if ((i == 0 && m680x->flags & M680X_FIRST_OP_IN_MNEM) || (i == 1 && m680x->flags & M680X_SECOND_OP_IN_MNEM)) comment = " (in mnemonic)"; add_str(&result, " ; operands[%u].type: REGISTER = %s%s", i, cs_reg_name(*handle, op->reg), comment); break; case M680X_OP_CONSTANT: add_str(&result, " ; operands[%u].type: CONSTANT = %u", i, op->const_val); break; case M680X_OP_IMMEDIATE: add_str(&result, " ; operands[%u].type: IMMEDIATE = #%d", i, op->imm); break; case M680X_OP_DIRECT: add_str(&result, " ; operands[%u].type: DIRECT = 0x%02x", i, op->direct_addr); break; case M680X_OP_EXTENDED: add_str(&result, " ; operands[%u].type: EXTENDED %s = 0x%04x", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address); break; case M680X_OP_RELATIVE: add_str(&result, " ; operands[%u].type: RELATIVE = 0x%04x", i, op->rel.address); break; case M680X_OP_INDEXED: add_str(&result, " ; operands[%u].type: INDEXED%s", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : ""); if (op->idx.base_reg != M680X_REG_INVALID) add_str(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg)); if (op->idx.offset_reg != M680X_REG_INVALID) add_str(&result, " ; offset register: %s", cs_reg_name(*handle, op->idx.offset_reg)); if ((op->idx.offset_bits != 0) && (op->idx.offset_reg == M680X_REG_INVALID) && !op->idx.inc_dec) { add_str(&result, " ; offset: %d", op->idx.offset); if (op->idx.base_reg == M680X_REG_PC) add_str(&result, " ; offset address: 0x%x", op->idx.offset_addr); add_str(&result, " ; offset bits: %u", op->idx.offset_bits); } if (op->idx.inc_dec) { const char *post_pre = op->idx.flags & M680X_IDX_POST_INC_DEC ? "post" : "pre"; const char *inc_dec = (op->idx.inc_dec > 0) ? "increment" : "decrement"; add_str(&result, " ; %s %s: %d", post_pre, inc_dec, abs(op->idx.inc_dec)); } break; } if (op->size != 0) add_str(&result, " ; size: %u", op->size); if (op->access != CS_AC_INVALID) add_str(&result, " ; access: %s", s_access[op->access]); } print_read_write_regs(result, handle, detail); return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/m68k_detail.c000064400000000000000000000065740072674642500217170ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" static const char* s_addressing_modes[] = { "", "Register Direct - Data", "Register Direct - Address", "Register Indirect - Address", "Register Indirect - Address with Postincrement", "Register Indirect - Address with Predecrement", "Register Indirect - Address with Displacement", "Address Register Indirect With Index - 8-bit displacement", "Address Register Indirect With Index - Base displacement", "Memory indirect - Postindex", "Memory indirect - Preindex", "Program Counter Indirect - with Displacement", "Program Counter Indirect with Index - with 8-Bit Displacement", "Program Counter Indirect with Index - with Base Displacement", "Program Counter Memory Indirect - Postindexed", "Program Counter Memory Indirect - Preindexed", "Absolute Data Addressing - Short", "Absolute Data Addressing - Long", "Immediate value", }; static void print_read_write_regs(char *result, cs_detail* detail, csh *handle) { int i; for (i = 0; i < detail->regs_read_count; ++i) { uint16_t reg_id = detail->regs_read[i]; const char* reg_name = cs_reg_name(*handle, reg_id); add_str(&result, " ; reading from reg: %s", reg_name); } for (i = 0; i < detail->regs_write_count; ++i) { uint16_t reg_id = detail->regs_write[i]; const char* reg_name = cs_reg_name(*handle, reg_id); add_str(&result, " ; writing to reg: %s", reg_name); } } char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins) { cs_m68k* m68k; cs_detail* detail; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; detail = ins->detail; m68k = &detail->m68k; if (m68k->op_count) add_str(&result, " ; op_count: %u", m68k->op_count); print_read_write_regs(result, detail, handle); add_str(&result, " ; groups_count: %u", detail->groups_count); for (i = 0; i < m68k->op_count; i++) { cs_m68k_op* op = &(m68k->operands[i]); switch((int)op->type) { default: break; case M68K_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case M68K_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, (int)op->imm); break; case M68K_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base_reg != M68K_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg)); if (op->mem.index_reg != M68K_REG_INVALID) { add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index_reg)); add_str(&result, " ; operands[%u].mem.index: size = %c", i, op->mem.index_size ? 'l' : 'w'); } if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); if (op->mem.scale != 0) add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale); add_str(&result, " ; address mode: %s", s_addressing_modes[op->address_mode]); break; case M68K_OP_FP_SINGLE: add_str(&result, " ; operands[%u].type: FP_SINGLE", i); add_str(&result, " ; operands[%u].simm: %f", i, op->simm); break; case M68K_OP_FP_DOUBLE: add_str(&result, " ; operands[%u].type: FP_DOUBLE", i); add_str(&result, " ; operands[%u].dimm: %lf", i, op->dimm); break; } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/main.c000064400000000000000000000304130072674642500205210ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "helper.h" #include "capstone_test.h" #include #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) static single_dict arches[] = { {"CS_ARCH_ARM", CS_ARCH_ARM}, {"CS_ARCH_ARM64", CS_ARCH_ARM64}, {"CS_ARCH_MIPS", CS_ARCH_MIPS}, {"CS_ARCH_PPC", CS_ARCH_PPC}, {"CS_ARCH_SPARC", CS_ARCH_SPARC}, {"CS_ARCH_SYSZ", CS_ARCH_SYSZ}, {"CS_ARCH_X86", CS_ARCH_X86}, {"CS_ARCH_XCORE", CS_ARCH_XCORE}, {"CS_ARCH_M68K", CS_ARCH_M68K}, {"CS_ARCH_BPF", CS_ARCH_BPF}, {"CS_ARCH_RISCV", CS_ARCH_RISCV}, }; static single_dict modes[] = { {"CS_MODE_LITTLE_ENDIAN", CS_MODE_LITTLE_ENDIAN}, {"CS_MODE_ARM", CS_MODE_ARM}, {"CS_MODE_16", CS_MODE_16}, {"CS_MODE_32", CS_MODE_32}, {"CS_MODE_64", CS_MODE_64}, {"CS_MODE_THUMB", CS_MODE_THUMB}, {"CS_MODE_MCLASS", CS_MODE_MCLASS}, {"CS_MODE_V8", CS_MODE_V8}, {"CS_MODE_MICRO", CS_MODE_MICRO}, {"CS_MODE_MIPS3", CS_MODE_MIPS3}, {"CS_MODE_MIPS32R6", CS_MODE_MIPS32R6}, {"CS_MODE_MIPS2", CS_MODE_MIPS2}, {"CS_MODE_V9", CS_MODE_V9}, {"CS_MODE_QPX", CS_MODE_QPX}, {"CS_MODE_M68K_000", CS_MODE_M68K_000}, {"CS_MODE_M68K_010", CS_MODE_M68K_010}, {"CS_MODE_M68K_020", CS_MODE_M68K_020}, {"CS_MODE_M68K_030", CS_MODE_M68K_030}, {"CS_MODE_M68K_040", CS_MODE_M68K_040}, {"CS_MODE_M68K_060", CS_MODE_M68K_060}, {"CS_MODE_BIG_ENDIAN", CS_MODE_BIG_ENDIAN}, {"CS_MODE_MIPS32", CS_MODE_MIPS32}, {"CS_MODE_MIPS64", CS_MODE_MIPS64}, {"CS_MODE_M680X_6301", CS_MODE_M680X_6301}, {"CS_MODE_M680X_6309", CS_MODE_M680X_6309}, {"CS_MODE_M680X_6800", CS_MODE_M680X_6800}, {"CS_MODE_M680X_6801", CS_MODE_M680X_6801}, {"CS_MODE_M680X_6805", CS_MODE_M680X_6805}, {"CS_MODE_M680X_6808", CS_MODE_M680X_6808}, {"CS_MODE_M680X_6809", CS_MODE_M680X_6809}, {"CS_MODE_M680X_6811", CS_MODE_M680X_6811}, {"CS_MODE_M680X_CPU12", CS_MODE_M680X_CPU12}, {"CS_MODE_M680X_HCS08", CS_MODE_M680X_HCS08}, {"CS_MODE_BPF_CLASSIC", CS_MODE_BPF_CLASSIC}, {"CS_MODE_BPF_EXTENDED", CS_MODE_BPF_EXTENDED}, {"CS_MODE_RISCV32", CS_MODE_RISCV32}, {"CS_MODE_RISCV64", CS_MODE_RISCV64}, }; static double_dict options[] = { {"CS_OPT_DETAIL", CS_OPT_DETAIL, CS_OPT_ON}, {"CS_OPT_SKIPDATA", CS_OPT_SKIPDATA, CS_OPT_ON}, {"CS_OPT_SYNTAX_DEFAULT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT}, {"CS_OPT_SYNTAX_INTEL", CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL}, {"CS_OPT_SYNTAX_ATT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT}, {"CS_OPT_SYNTAX_NOREGNAME", CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME}, {"CS_OPT_SYNTAX_MASM", CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM}, {"CS_MODE_LITTLE_ENDIAN", CS_OPT_MODE, CS_MODE_LITTLE_ENDIAN}, {"CS_MODE_ARM", CS_OPT_MODE, CS_MODE_ARM}, {"CS_MODE_16", CS_OPT_MODE, CS_MODE_16}, {"CS_MODE_32", CS_OPT_MODE, CS_MODE_32}, {"CS_MODE_64", CS_OPT_MODE, CS_MODE_64}, {"CS_MODE_THUMB", CS_OPT_MODE, CS_MODE_THUMB}, {"CS_MODE_MCLASS", CS_OPT_MODE, CS_MODE_MCLASS}, {"CS_MODE_V8", CS_OPT_MODE, CS_MODE_V8}, {"CS_MODE_MICRO", CS_OPT_MODE, CS_MODE_MICRO}, {"CS_MODE_MIPS3", CS_OPT_MODE, CS_MODE_MIPS3}, {"CS_MODE_MIPS32R6", CS_OPT_MODE, CS_MODE_MIPS32R6}, {"CS_MODE_MIPS2", CS_OPT_MODE, CS_MODE_MIPS2}, {"CS_MODE_V9", CS_OPT_MODE, CS_MODE_V9}, {"CS_MODE_QPX", CS_OPT_MODE, CS_MODE_QPX}, {"CS_MODE_M68K_000", CS_OPT_MODE, CS_MODE_M68K_000}, {"CS_MODE_M68K_010", CS_OPT_MODE, CS_MODE_M68K_010}, {"CS_MODE_M68K_020", CS_OPT_MODE, CS_MODE_M68K_020}, {"CS_MODE_M68K_030", CS_OPT_MODE, CS_MODE_M68K_030}, {"CS_MODE_M68K_040", CS_OPT_MODE, CS_MODE_M68K_040}, {"CS_MODE_M68K_060", CS_OPT_MODE, CS_MODE_M68K_060}, {"CS_MODE_BIG_ENDIAN", CS_OPT_MODE, CS_MODE_BIG_ENDIAN}, {"CS_MODE_MIPS32", CS_OPT_MODE, CS_MODE_MIPS32}, {"CS_MODE_MIPS64", CS_OPT_MODE, CS_MODE_MIPS64}, {"CS_MODE_M680X_6301", CS_OPT_MODE, CS_MODE_M680X_6301}, {"CS_MODE_M680X_6309", CS_OPT_MODE, CS_MODE_M680X_6309}, {"CS_MODE_M680X_6800", CS_OPT_MODE, CS_MODE_M680X_6800}, {"CS_MODE_M680X_6801", CS_OPT_MODE, CS_MODE_M680X_6801}, {"CS_MODE_M680X_6805", CS_OPT_MODE, CS_MODE_M680X_6805}, {"CS_MODE_M680X_6808", CS_OPT_MODE, CS_MODE_M680X_6808}, {"CS_MODE_M680X_6809", CS_OPT_MODE, CS_MODE_M680X_6809}, {"CS_MODE_M680X_6811", CS_OPT_MODE, CS_MODE_M680X_6811}, {"CS_MODE_M680X_CPU12", CS_OPT_MODE, CS_MODE_M680X_CPU12}, {"CS_MODE_M680X_HCS08", CS_OPT_MODE, CS_MODE_M680X_HCS08}, {"CS_MODE_RISCV32", CS_OPT_MODE, CS_MODE_RISCV32}, {"CS_MODE_RISCV64", CS_OPT_MODE, CS_MODE_RISCV64}, {"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON}, }; static int counter; static char **list_lines; static int failed_setup; static int size_lines; static cs_mode issue_mode; static int getDetail; static int mc_mode; static int e_flag; static int setup_MC(void **state) { csh *handle; char **list_params; int size_params; int arch, mode; int i, index, tmp_counter; if (failed_setup) { fprintf(stderr, "[ ERROR ] --- Invalid file to setup\n"); return -1; } tmp_counter = 0; while (tmp_counter < size_lines && list_lines[tmp_counter][0] != '#') tmp_counter++; list_params = split(list_lines[tmp_counter] + 2, ", ", &size_params); if (size_params != 3) { fprintf(stderr, "[ ERROR ] --- Invalid options ( arch, mode, option )\n"); failed_setup = 1; return -1; } arch = get_value(arches, ARR_SIZE(arches), list_params[0]); if (!strcmp(list_params[0], "CS_ARCH_ARM64")) mc_mode = 2; else mc_mode = 1; mode = 0; for (i = 0; i < ARR_SIZE(modes); ++i) { if (strstr(list_params[1], modes[i].str)) { mode += modes[i].value; switch (modes[i].value) { case CS_MODE_16: mc_mode = 0; break; case CS_MODE_64: mc_mode = 2; break; case CS_MODE_THUMB: mc_mode = 1; break; default: break; } } } if (arch == -1) { fprintf(stderr, "[ ERROR ] --- Arch is not supported!\n"); failed_setup = 1; return -1; } handle = (csh *)malloc(sizeof(csh)); if(cs_open(arch, mode, handle) != CS_ERR_OK) { fprintf(stderr, "[ ERROR ] --- Cannot initialize capstone\n"); failed_setup = 1; return -1; } for (i = 0; i < ARR_SIZE(options); ++i) { if (strstr(list_params[2], options[i].str)) { if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) { fprintf(stderr, "[ ERROR ] --- Option is not supported for this arch/mode\n"); failed_setup = 1; return -1; } } } *state = (void *)handle; counter++; if (e_flag == 0) while (counter < size_lines && strncmp(list_lines[counter], "0x", 2)) counter++; else while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5)) counter++; free_strs(list_params, size_params); return 0; } static void test_MC(void **state) { if (e_flag == 1) test_single_MC((csh *)*state, mc_mode, list_lines[counter] + 3); else test_single_MC((csh *)*state, mc_mode, list_lines[counter]); } static int teardown_MC(void **state) { cs_close(*state); free(*state); return 0; } static int setup_issue(void **state) { csh *handle; char **list_params; int size_params; int arch, mode; int i, index, result; char *(*function)(csh *, cs_mode, cs_insn*); getDetail = 0; failed_setup = 0; if (e_flag == 0) while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3)) counter++; // get issue line else while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) counter++; counter++; if (e_flag == 0) while (counter < size_lines && strncmp(list_lines[counter], "!#", 2)) counter++; // get arch line else while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) counter++; if (e_flag == 0) list_params = split(list_lines[counter] + 3, ", ", &size_params); else list_params = split(list_lines[counter] + 6, ", ", &size_params); arch = get_value(arches, ARR_SIZE(arches), list_params[0]); if (!strcmp(list_params[0], "CS_ARCH_ARM64")) mc_mode = 2; else mc_mode = 1; mode = 0; for (i = 0; i < ARR_SIZE(modes); ++i) { if (strstr(list_params[1], modes[i].str)) { mode += modes[i].value; switch (modes[i].value) { case CS_MODE_16: mc_mode = 0; break; case CS_MODE_64: mc_mode = 2; break; case CS_MODE_THUMB: mc_mode = 1; break; default: break; } } } if (arch == -1) { fprintf(stderr, "[ ERROR ] --- Arch is not supported!\n"); failed_setup = 1; return -1; } handle = (csh *)calloc(1, sizeof(csh)); if(cs_open(arch, mode, handle) != CS_ERR_OK) { fprintf(stderr, "[ ERROR ] --- Cannot initialize capstone\n"); failed_setup = 1; return -1; } for (i = 0; i < ARR_SIZE(options); ++i) { if (strstr(list_params[2], options[i].str)) { if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) { fprintf(stderr, "[ ERROR ] --- Option is not supported for this arch/mode\n"); failed_setup = 1; return -1; } if (i == 0) { result = set_function(arch); if (result == -1) { fprintf(stderr, "[ ERROR ] --- Cannot get details\n"); failed_setup = 1; return -1; } getDetail = 1; } } } *state = (void *)handle; issue_mode = mode; if (e_flag == 0) while (counter < size_lines && strncmp(list_lines[counter], "0x", 2)) counter++; else while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5)) counter++; free_strs(list_params, size_params); return 0; } static void test_issue(void **state) { if (e_flag == 0) test_single_issue((csh *)*state, issue_mode, list_lines[counter], getDetail); else test_single_issue((csh *)*state, issue_mode, list_lines[counter] + 3, getDetail); return; } static int teardown_issue(void **state) { if (e_flag == 0) while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3)) counter++; else while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6)) counter++; cs_close(*state); free(*state); function = NULL; return 0; } static void test_file(const char *filename) { int size, i; char **list_str; char *content, *tmp; struct CMUnitTest *tests; int issue_num, number_of_tests; printf("[+] TARGET: %s\n", filename); content = readfile(filename); counter = 0; failed_setup = 0; function = NULL; if (strstr(filename, "issue")) { number_of_tests = 0; list_lines = split(content, "\n", &size_lines); tests = NULL; for (i = 0; i < size_lines; ++i) { if ((!strncmp(list_lines[i], "// !# issue", 11) && e_flag == 1) || (!strncmp(list_lines[i], "!# issue", 8) && e_flag == 0)) { tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1)); tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_issue, setup_issue, teardown_issue); tests[number_of_tests].name = strdup(list_lines[i]); number_of_tests ++; } } _cmocka_run_group_tests("Testing issues", tests, number_of_tests, NULL, NULL); } else { list_lines = split(content, "\n", &size_lines); number_of_tests = 0; tests = NULL; for (i = 1; i < size_lines; ++i) { if ((!strncmp(list_lines[i], "// 0x", 5) && e_flag == 1) || (!strncmp(list_lines[i], "0x", 2) && e_flag == 0)) { tmp = (char *)malloc(sizeof(char) * 100); sprintf(tmp, "Line %d", i+1); tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1)); tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_MC, setup_MC, teardown_MC); tests[number_of_tests].name = tmp; number_of_tests ++; } } _cmocka_run_group_tests("Testing MC", tests, number_of_tests, NULL, NULL); } printf("[+] DONE: %s\n", filename); printf("[!] Noted:\n[ ERROR ] --- \"\" != \"\"\n"); printf("\n\n"); free_strs(list_lines, size_lines); } static void test_folder(const char *folder) { char **files; int num_files, i; files = NULL; num_files = 0; listdir(folder, &files, &num_files); for (i = 0; i < num_files; ++i) { if (strcmp("cs", get_filename_ext(files[i]))) continue; test_file(files[i]); } } int main(int argc, char *argv[]) { int opt, flag; flag = 0; e_flag = 0; while ((opt = getopt(argc, argv, "ef:d:")) > 0) { switch (opt) { case 'f': test_file(optarg); flag = 1; break; case 'd': test_folder(optarg); flag = 1; break; case 'e': e_flag = 1; break; default: printf("Usage: %s [-e] [-f ] [-d ]\n", argv[0]); exit(-1); } } if (flag == 0) { printf("Usage: %s [-e] [-f ] [-d ]\n", argv[0]); exit(-1); } return 0; } capstone-sys-0.15.0/capstone/suite/cstest/src/mips_detail.c000064400000000000000000000022040072674642500220640ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins) { int i; cs_mips *mips; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; mips = &(ins->detail->mips); if (mips->op_count) add_str(&result, " ; op_count: %u", mips->op_count); for (i = 0; i < mips->op_count; i++) { cs_mips_op *op = &(mips->operands[i]); switch((int)op->type) { default: break; case MIPS_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case MIPS_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); break; case MIPS_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != MIPS_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); break; } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/mos65xx_detail.c000064400000000000000000000053070072674642500224540ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" static const char *get_am_name(mos65xx_address_mode mode) { switch(mode) { default: case MOS65XX_AM_NONE: return "No address mode"; case MOS65XX_AM_IMP: return "implied"; case MOS65XX_AM_ACC: return "accumulator"; case MOS65XX_AM_IMM: return "immediate value"; case MOS65XX_AM_REL: return "relative"; case MOS65XX_AM_INT: return "interrupt signature"; case MOS65XX_AM_BLOCK: return "block move"; case MOS65XX_AM_ZP: return "zero page"; case MOS65XX_AM_ZP_X: return "zero page indexed with x"; case MOS65XX_AM_ZP_Y: return "zero page indexed with y"; case MOS65XX_AM_ZP_REL: return "relative bit branch"; case MOS65XX_AM_ZP_IND: return "zero page indirect"; case MOS65XX_AM_ZP_X_IND: return "zero page indexed with x indirect"; case MOS65XX_AM_ZP_IND_Y: return "zero page indirect indexed with y"; case MOS65XX_AM_ZP_IND_LONG: return "zero page indirect long"; case MOS65XX_AM_ZP_IND_LONG_Y: return "zero page indirect long indexed with y"; case MOS65XX_AM_ABS: return "absolute"; case MOS65XX_AM_ABS_X: return "absolute indexed with x"; case MOS65XX_AM_ABS_Y: return "absolute indexed with y"; case MOS65XX_AM_ABS_IND: return "absolute indirect"; case MOS65XX_AM_ABS_X_IND: return "absolute indexed with x indirect"; case MOS65XX_AM_ABS_IND_LONG: return "absolute indirect long"; case MOS65XX_AM_ABS_LONG: return "absolute long"; case MOS65XX_AM_ABS_LONG_X: return "absolute long indexed with x"; case MOS65XX_AM_SR: return "stack relative"; case MOS65XX_AM_SR_IND_Y: return "stack relative indirect indexed with y"; } } char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins) { int i; cs_mos65xx *mos65xx; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; mos65xx = &(ins->detail->mos65xx); add_str(&result, " ; address mode: %s", get_am_name(mos65xx->am)); add_str(&result, " ; modifies flags: %s", mos65xx->modifies_flags ? "true": "false"); if (mos65xx->op_count) add_str(&result, " ; op_count: %u", mos65xx->op_count); for (i = 0; i < mos65xx->op_count; i++) { cs_mos65xx_op *op = &(mos65xx->operands[i]); switch((int)op->type) { default: break; case MOS65XX_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case MOS65XX_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); break; case MOS65XX_OP_MEM: add_str(&result, " ; operands[%u].type: MEM = 0x%x", i, op->mem); break; } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/ppc_detail.c000064400000000000000000000041450072674642500217040ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" static const char* get_bc_name(int bc) { switch(bc) { default: case PPC_BC_INVALID: return ("invalid"); case PPC_BC_LT: return ("lt"); case PPC_BC_LE: return ("le"); case PPC_BC_EQ: return ("eq"); case PPC_BC_GE: return ("ge"); case PPC_BC_GT: return ("gt"); case PPC_BC_NE: return ("ne"); case PPC_BC_UN: return ("un"); case PPC_BC_NU: return ("nu"); case PPC_BC_SO: return ("so"); case PPC_BC_NS: return ("ns"); } } char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins) { cs_ppc *ppc; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; ppc = &(ins->detail->ppc); if (ppc->op_count) add_str(&result, " ; op_count: %u", ppc->op_count); for (i = 0; i < ppc->op_count; i++) { cs_ppc_op *op = &(ppc->operands[i]); switch((int)op->type) { default: break; case PPC_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case PPC_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%"PRIx64"", i, op->imm); break; case PPC_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != PPC_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); break; case PPC_OP_CRX: add_str(&result, " ; operands[%u].type: CRX", i); add_str(&result, " ; operands[%u].crx.scale: %d", i, op->crx.scale); add_str(&result, " ; operands[%u].crx.reg: %s", i, cs_reg_name(*handle, op->crx.reg)); add_str(&result, " ; operands[%u].crx.cond: %s", i, get_bc_name(op->crx.cond)); break; } } if (ppc->bc != 0) add_str(&result, " ; Branch code: %u", ppc->bc); if (ppc->bh != 0) add_str(&result, " ; Branch hint: %u", ppc->bh); if (ppc->update_cr0) add_str(&result, " ; Update-CR0: True"); return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/riscv_detail.c000064400000000000000000000022050072674642500222430ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins) { cs_riscv *riscv; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; riscv = &(ins->detail->riscv); if (riscv->op_count) add_str(&result, " ; op_count: %u", riscv->op_count); for (i = 0; i < riscv->op_count; i++) { cs_riscv_op *op = &(riscv->operands[i]); switch((int)op->type) { default: break; case RISCV_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case RISCV_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); break; case RISCV_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != RISCV_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); break; } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/sparc_detail.c000064400000000000000000000026610072674642500222330ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins) { cs_sparc *sparc; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; sparc = &(ins->detail->sparc); if (sparc->op_count) add_str(&result, " ; op_count: %u", sparc->op_count); for (i = 0; i < sparc->op_count; i++) { cs_sparc_op *op = &(sparc->operands[i]); switch((int)op->type) { default: break; case SPARC_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case SPARC_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); break; case SPARC_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != X86_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.index != X86_REG_INVALID) add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); break; } } if (sparc->cc != 0) add_str(&result, " ; Code condition: %u", sparc->cc); if (sparc->hint != 0) add_str(&result, " ; Hint code: %u", sparc->hint); return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/systemz_detail.c000064400000000000000000000030740072674642500226400ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins) { cs_sysz *sysz; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; sysz = &(ins->detail->sysz); if (sysz->op_count) add_str(&result, " ; op_count: %u", sysz->op_count); for (i = 0; i < sysz->op_count; i++) { cs_sysz_op *op = &(sysz->operands[i]); switch((int)op->type) { default: break; case SYSZ_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case SYSZ_OP_ACREG: add_str(&result, " ; operands[%u].type: ACREG = %u", i, op->reg); break; case SYSZ_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); break; case SYSZ_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != SYSZ_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.index != SYSZ_REG_INVALID) add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); if (op->mem.length != 0) add_str(&result, " ; operands[%u].mem.length: 0x%" PRIx64 "", i, op->mem.length); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); break; } } if (sysz->cc != 0) add_str(&result, " ; Code condition: %u", sysz->cc); return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/tms320c64x_detail.c000064400000000000000000000072440072674642500226620ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins) { cs_tms320c64x *tms320c64x; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; tms320c64x = &(ins->detail->tms320c64x); if (tms320c64x->op_count) add_str(&result, " ; op_count: %u", tms320c64x->op_count); for (i = 0; i < tms320c64x->op_count; i++) { cs_tms320c64x_op *op = &(tms320c64x->operands[i]); switch((int)op->type) { default: break; case TMS320C64X_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case TMS320C64X_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); break; case TMS320C64X_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != TMS320C64X_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); add_str(&result, " ; operands[%u].mem.disptype: ", i); if (op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) { add_str(&result, "Invalid"); add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp); } if (op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) { add_str(&result, "Constant"); add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp); } if (op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) { add_str(&result, "Register"); add_str(&result, " ; operands[%u].mem.disp: %s", i, cs_reg_name(*handle, op->mem.disp)); } add_str(&result, " ; operands[%u].mem.unit: %u", i, op->mem.unit); add_str(&result, " ; operands[%u].mem.direction: ", i); if (op->mem.direction == TMS320C64X_MEM_DIR_INVALID) add_str(&result, "Invalid"); if (op->mem.direction == TMS320C64X_MEM_DIR_FW) add_str(&result, "Forward"); if (op->mem.direction == TMS320C64X_MEM_DIR_BW) add_str(&result, "Backward"); add_str(&result, " ; operands[%u].mem.modify: ", i); if (op->mem.modify == TMS320C64X_MEM_MOD_INVALID) add_str(&result, "Invalid"); if (op->mem.modify == TMS320C64X_MEM_MOD_NO) add_str(&result, "No"); if (op->mem.modify == TMS320C64X_MEM_MOD_PRE) add_str(&result, "Pre"); if (op->mem.modify == TMS320C64X_MEM_MOD_POST) add_str(&result, "Post"); add_str(&result, " ; operands[%u].mem.scaled: %u", i, op->mem.scaled); break; case TMS320C64X_OP_REGPAIR: add_str(&result, " ; operands[%u].type: REGPAIR = %s:%s", i, cs_reg_name(*handle, op->reg + 1), cs_reg_name(*handle, op->reg)); break; } } add_str(&result, " ; Functional unit: "); switch(tms320c64x->funit.unit) { case TMS320C64X_FUNIT_D: add_str(&result, "D%u", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_L: add_str(&result, "L%u", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_M: add_str(&result, "M%u", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_S: add_str(&result, "S%u", tms320c64x->funit.side); break; case TMS320C64X_FUNIT_NO: add_str(&result, "No Functional Unit"); break; default: add_str(&result, "Unknown (Unit %u, Side %u)", tms320c64x->funit.unit, tms320c64x->funit.side); break; } if (tms320c64x->funit.crosspath == 1) add_str(&result, " ; Crosspath: 1"); if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID) add_str(&result, " ; Condition: [%c%s]", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(*handle, tms320c64x->condition.reg)); add_str(&result, " ; Parallel: %s", (tms320c64x->parallel == 1) ? "true" : "false"); return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/x86_detail.c000064400000000000000000000215650072674642500215540ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" static void print_string_hex(char **result, const char *comment, unsigned char *str, size_t len) { unsigned char *c; add_str(result, "%s", comment); for (c = str; c < str + len; c++) { add_str(result, "0x%02x", *c & 0xff); if (c < str + len - 1) add_str(result, " "); } } static const char *get_eflag_name(uint64_t flag) { switch(flag) { default: return NULL; case X86_EFLAGS_UNDEFINED_OF: return "UNDEF_OF"; case X86_EFLAGS_UNDEFINED_SF: return "UNDEF_SF"; case X86_EFLAGS_UNDEFINED_ZF: return "UNDEF_ZF"; case X86_EFLAGS_MODIFY_AF: return "MOD_AF"; case X86_EFLAGS_UNDEFINED_PF: return "UNDEF_PF"; case X86_EFLAGS_MODIFY_CF: return "MOD_CF"; case X86_EFLAGS_MODIFY_SF: return "MOD_SF"; case X86_EFLAGS_MODIFY_ZF: return "MOD_ZF"; case X86_EFLAGS_UNDEFINED_AF: return "UNDEF_AF"; case X86_EFLAGS_MODIFY_PF: return "MOD_PF"; case X86_EFLAGS_UNDEFINED_CF: return "UNDEF_CF"; case X86_EFLAGS_MODIFY_OF: return "MOD_OF"; case X86_EFLAGS_RESET_OF: return "RESET_OF"; case X86_EFLAGS_RESET_CF: return "RESET_CF"; case X86_EFLAGS_RESET_DF: return "RESET_DF"; case X86_EFLAGS_RESET_IF: return "RESET_IF"; case X86_EFLAGS_RESET_ZF: return "RESET_ZF"; case X86_EFLAGS_TEST_OF: return "TEST_OF"; case X86_EFLAGS_TEST_SF: return "TEST_SF"; case X86_EFLAGS_TEST_ZF: return "TEST_ZF"; case X86_EFLAGS_TEST_PF: return "TEST_PF"; case X86_EFLAGS_TEST_CF: return "TEST_CF"; case X86_EFLAGS_RESET_SF: return "RESET_SF"; case X86_EFLAGS_RESET_AF: return "RESET_AF"; case X86_EFLAGS_RESET_TF: return "RESET_TF"; case X86_EFLAGS_RESET_NT: return "RESET_NT"; case X86_EFLAGS_PRIOR_OF: return "PRIOR_OF"; case X86_EFLAGS_PRIOR_SF: return "PRIOR_SF"; case X86_EFLAGS_PRIOR_ZF: return "PRIOR_ZF"; case X86_EFLAGS_PRIOR_AF: return "PRIOR_AF"; case X86_EFLAGS_PRIOR_PF: return "PRIOR_PF"; case X86_EFLAGS_PRIOR_CF: return "PRIOR_CF"; case X86_EFLAGS_PRIOR_TF: return "PRIOR_TF"; case X86_EFLAGS_PRIOR_IF: return "PRIOR_IF"; case X86_EFLAGS_PRIOR_DF: return "PRIOR_DF"; case X86_EFLAGS_TEST_NT: return "TEST_NT"; case X86_EFLAGS_TEST_DF: return "TEST_DF"; case X86_EFLAGS_RESET_PF: return "RESET_PF"; case X86_EFLAGS_PRIOR_NT: return "PRIOR_NT"; case X86_EFLAGS_MODIFY_TF: return "MOD_TF"; case X86_EFLAGS_MODIFY_IF: return "MOD_IF"; case X86_EFLAGS_MODIFY_DF: return "MOD_DF"; case X86_EFLAGS_MODIFY_NT: return "MOD_NT"; case X86_EFLAGS_MODIFY_RF: return "MOD_RF"; case X86_EFLAGS_SET_CF: return "SET_CF"; case X86_EFLAGS_SET_DF: return "SET_DF"; case X86_EFLAGS_SET_IF: return "SET_IF"; case X86_EFLAGS_SET_OF: return "SET_OF"; case X86_EFLAGS_SET_SF: return "SET_SF"; case X86_EFLAGS_SET_ZF: return "SET_ZF"; case X86_EFLAGS_SET_AF: return "SET_AF"; case X86_EFLAGS_SET_PF: return "SET_PF"; case X86_EFLAGS_TEST_AF: return "TEST_AF"; case X86_EFLAGS_TEST_TF: return "TEST_TF"; case X86_EFLAGS_TEST_RF: return "TEST_RF"; case X86_EFLAGS_RESET_0F: return "RESET_0F"; case X86_EFLAGS_RESET_AC: return "RESET_AC"; } } static const char *get_fpu_flag_name(uint64_t flag) { switch (flag) { default: return NULL; case X86_FPU_FLAGS_MODIFY_C0: return "MOD_C0"; case X86_FPU_FLAGS_MODIFY_C1: return "MOD_C1"; case X86_FPU_FLAGS_MODIFY_C2: return "MOD_C2"; case X86_FPU_FLAGS_MODIFY_C3: return "MOD_C3"; case X86_FPU_FLAGS_RESET_C0: return "RESET_C0"; case X86_FPU_FLAGS_RESET_C1: return "RESET_C1"; case X86_FPU_FLAGS_RESET_C2: return "RESET_C2"; case X86_FPU_FLAGS_RESET_C3: return "RESET_C3"; case X86_FPU_FLAGS_SET_C0: return "SET_C0"; case X86_FPU_FLAGS_SET_C1: return "SET_C1"; case X86_FPU_FLAGS_SET_C2: return "SET_C2"; case X86_FPU_FLAGS_SET_C3: return "SET_C3"; case X86_FPU_FLAGS_UNDEFINED_C0: return "UNDEF_C0"; case X86_FPU_FLAGS_UNDEFINED_C1: return "UNDEF_C1"; case X86_FPU_FLAGS_UNDEFINED_C2: return "UNDEF_C2"; case X86_FPU_FLAGS_UNDEFINED_C3: return "UNDEF_C3"; case X86_FPU_FLAGS_TEST_C0: return "TEST_C0"; case X86_FPU_FLAGS_TEST_C1: return "TEST_C1"; case X86_FPU_FLAGS_TEST_C2: return "TEST_C2"; case X86_FPU_FLAGS_TEST_C3: return "TEST_C3"; } } char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins) { int count, i; cs_x86 *x86; cs_regs regs_read, regs_write; uint8_t regs_read_count, regs_write_count; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; x86 = &(ins->detail->x86); print_string_hex(&result, " ; Prefix:", x86->prefix, 4); print_string_hex(&result, " ; Opcode:", x86->opcode, 4); add_str(&result, " ; rex: 0x%x", x86->rex); add_str(&result, " ; addr_size: %u", x86->addr_size); add_str(&result, " ; modrm: 0x%x", x86->modrm); add_str(&result, " ; disp: 0x%" PRIx64 "", x86->disp); if ((mode & CS_MODE_16) == 0) { add_str(&result, " ; sib: 0x%x", x86->sib); if (x86->sib_base != X86_REG_INVALID) add_str(&result, " ; sib_base: %s", cs_reg_name(*ud, x86->sib_base)); if (x86->sib_index != X86_REG_INVALID) add_str(&result, " ; sib_index: %s", cs_reg_name(*ud, x86->sib_index)); if (x86->sib_scale != 0) add_str(&result, " ; sib_scale: %d", x86->sib_scale); } if (x86->xop_cc != X86_XOP_CC_INVALID) { add_str(&result, " ; xop_cc: %u", x86->xop_cc); } if (x86->sse_cc != X86_SSE_CC_INVALID) { add_str(&result, " ; sse_cc: %u", x86->sse_cc); } if (x86->avx_cc != X86_AVX_CC_INVALID) { add_str(&result, " ; avx_cc: %u", x86->avx_cc); } if (x86->avx_sae) { add_str(&result, " ; avx_sae: %u", x86->avx_sae); } if (x86->avx_rm != X86_AVX_RM_INVALID) { add_str(&result, " ; avx_rm: %u", x86->avx_rm); } count = cs_op_count(*ud, ins, X86_OP_IMM); if (count > 0) { add_str(&result, " ; imm_count: %u", count); for (i = 1; i < count + 1; i++) { int index = cs_op_index(*ud, ins, X86_OP_IMM, i); add_str(&result, " ; imms[%u]: 0x%" PRIx64 "", i, x86->operands[index].imm); } } if (x86->op_count) add_str(&result, " ; op_count: %u", x86->op_count); for (i = 0; i < x86->op_count; i++) { cs_x86_op *op = &(x86->operands[i]); switch((int)op->type) { case X86_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*ud, op->reg)); break; case X86_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); break; case X86_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.segment != X86_REG_INVALID) add_str(&result, " ; operands[%u].mem.segment: REG = %s", i, cs_reg_name(*ud, op->mem.segment)); if (op->mem.base != X86_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*ud, op->mem.base)); if (op->mem.index != X86_REG_INVALID) add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*ud, op->mem.index)); if (op->mem.scale != 1) add_str(&result, " ; operands[%u].mem.scale: %u", i, op->mem.scale); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp); break; default: break; } if (op->avx_bcast != X86_AVX_BCAST_INVALID) add_str(&result, " ; operands[%u].avx_bcast: %u", i, op->avx_bcast); if (op->avx_zero_opmask != false) add_str(&result, " ; operands[%u].avx_zero_opmask: TRUE", i); add_str(&result, " ; operands[%u].size: %u", i, op->size); switch(op->access) { default: break; case CS_AC_READ: add_str(&result, " ; operands[%u].access: READ", i); break; case CS_AC_WRITE: add_str(&result, " ; operands[%u].access: WRITE", i); break; case CS_AC_READ | CS_AC_WRITE: add_str(&result, " ; operands[%u].access: READ | WRITE", i); break; } } if (!cs_regs_access(*ud, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { if (regs_read_count) { add_str(&result, " ; Registers read:"); for(i = 0; i < regs_read_count; i++) { add_str(&result, " %s", cs_reg_name(*ud, regs_read[i])); } } if (regs_write_count) { add_str(&result, " ; Registers modified:"); for(i = 0; i < regs_write_count; i++) { add_str(&result, " %s", cs_reg_name(*ud, regs_write[i])); } } } if (x86->eflags || x86->fpu_flags) { for(i = 0; i < ins->detail->groups_count; i++) { if (ins->detail->groups[i] == X86_GRP_FPU) { add_str(&result, " ; FPU_FLAGS:"); for(i = 0; i <= 63; i++) if (x86->fpu_flags & ((uint64_t)1 << i)) { add_str(&result, " %s", get_fpu_flag_name((uint64_t)1 << i)); } break; } } if (i == ins->detail->groups_count) { add_str(&result, " ; EFLAGS:"); for(i = 0; i <= 63; i++) if (x86->eflags & ((uint64_t)1 << i)) { add_str(&result, " %s", get_eflag_name((uint64_t)1 << i)); } } } return result; } capstone-sys-0.15.0/capstone/suite/cstest/src/xcore_detail.c000064400000000000000000000025530072674642500222430ustar 00000000000000/* Capstone testing regression */ /* By Do Minh Tuan , 02-2019 */ #include "factory.h" char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins) { cs_xcore *xcore; int i; char *result; result = (char *)malloc(sizeof(char)); result[0] = '\0'; if (ins->detail == NULL) return result; xcore = &(ins->detail->xcore); if (xcore->op_count) add_str(&result, " ; op_count: %u", xcore->op_count); for (i = 0; i < xcore->op_count; i++) { cs_xcore_op *op = &(xcore->operands[i]); switch((int)op->type) { default: break; case XCORE_OP_REG: add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case XCORE_OP_IMM: add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm); break; case XCORE_OP_MEM: add_str(&result, " ; operands[%u].type: MEM", i); if (op->mem.base != XCORE_REG_INVALID) add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base)); if (op->mem.index != XCORE_REG_INVALID) add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index)); if (op->mem.disp != 0) add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp); if (op->mem.direct != 1) add_str(&result, " ; operands[%u].mem.direct: -1", i); break; } } return result; } capstone-sys-0.15.0/capstone/suite/disasm_mc.py000075500000000000000000000172170072674642500176600ustar 00000000000000#!/usr/bin/python # Test tool to disassemble MC files. By Nguyen Anh Quynh, 2017 import array, os.path, sys from capstone import * # convert all hex numbers to decimal numbers in a text def normalize_hex(a): while(True): i = a.find('0x') if i == -1: # no more hex number break hexnum = '0x' for c in a[i + 2:]: if c in '0123456789abcdefABCDEF': hexnum += c else: break num = int(hexnum, 16) a = a.replace(hexnum, str(num)) return a def test_file(fname): print("Test %s" %fname); f = open(fname) lines = f.readlines() f.close() if not lines[0].startswith('# '): print("ERROR: decoding information is missing") return # skip '# ' at the front, then split line to get out hexcode # Note: option can be '', or 'None' #print lines[0] #print lines[0][2:].split(', ') (arch, mode, option) = lines[0][2:].split(', ') mode = mode.replace(' ', '') option = option.strip() archs = { "CS_ARCH_ARM": CS_ARCH_ARM, "CS_ARCH_ARM64": CS_ARCH_ARM64, "CS_ARCH_MIPS": CS_ARCH_MIPS, "CS_ARCH_PPC": CS_ARCH_PPC, "CS_ARCH_SPARC": CS_ARCH_SPARC, "CS_ARCH_SYSZ": CS_ARCH_SYSZ, "CS_ARCH_X86": CS_ARCH_X86, "CS_ARCH_XCORE": CS_ARCH_XCORE, "CS_ARCH_M68K": CS_ARCH_M68K, "CS_ARCH_RISCV": CS_ARCH_RISCV, } modes = { "CS_MODE_16": CS_MODE_16, "CS_MODE_32": CS_MODE_32, "CS_MODE_64": CS_MODE_64, "CS_MODE_MIPS32": CS_MODE_MIPS32, "CS_MODE_MIPS64": CS_MODE_MIPS64, "0": CS_MODE_ARM, "CS_MODE_ARM": CS_MODE_ARM, "CS_MODE_THUMB": CS_MODE_THUMB, "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8, "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8, "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS, "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN, "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN, "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN, "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN, "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO, "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9, "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN, "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, "CS_MODE_RISCV32": CS_MODE_RISCV32, "CS_MODE_RISCV64": CS_MODE_RISCV64, } options = { "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT, "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME, } mc_modes = { ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'], ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'], ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'], ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'], ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'], ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'], ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'], ("CS_ARCH_ARM64", "0"): ['-triple=aarch64'], ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'], ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'], ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'], ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'], ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'], ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'], ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'], ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'], ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'], ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'], ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'], ('CS_ARCH_RISCV', 'CS_MODE_RISCV32'): ['-triple=riscv32'], ('CS_ARCH_RISCV', 'CS_MODE_RISCV64'): ['-triple=riscv64'], } #if not option in ('', 'None'): # print archs[arch], modes[mode], options[option] #print(arch, mode, option) md = Cs(archs[arch], modes[mode]) if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' : md.syntax = CS_OPT_SYNTAX_NOREGNAME if fname.endswith('3DNow.s.cs'): md.syntax = CS_OPT_SYNTAX_ATT for line in lines[1:]: # ignore all the input lines having # in front. if line.startswith('#'): continue #print("Check %s" %line) code = line.split(' = ')[0] asm = ''.join(line.split(' = ')[1:]) hex_code = code.replace('0x', '') hex_code = hex_code.replace(',', '') hex_data = hex_code.decode('hex') #hex_bytes = array.array('B', hex_data) x = list(md.disasm(hex_data, 0)) if len(x) > 0: if x[0].op_str != '': cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str) else: cs_output = x[0].mnemonic else: cs_output = 'FAILED to disassemble' cs_output2 = normalize_hex(cs_output) cs_output2 = cs_output2.replace(' ', '') if arch == 'CS_ARCH_MIPS': # normalize register alias names cs_output2 = cs_output2.replace('$at', '$1') cs_output2 = cs_output2.replace('$v0', '$2') cs_output2 = cs_output2.replace('$v1', '$3') cs_output2 = cs_output2.replace('$a0', '$4') cs_output2 = cs_output2.replace('$a1', '$5') cs_output2 = cs_output2.replace('$a2', '$6') cs_output2 = cs_output2.replace('$a3', '$7') cs_output2 = cs_output2.replace('$t0', '$8') cs_output2 = cs_output2.replace('$t1', '$9') cs_output2 = cs_output2.replace('$t2', '$10') cs_output2 = cs_output2.replace('$t3', '$11') cs_output2 = cs_output2.replace('$t4', '$12') cs_output2 = cs_output2.replace('$t5', '$13') cs_output2 = cs_output2.replace('$t6', '$14') cs_output2 = cs_output2.replace('$t7', '$15') cs_output2 = cs_output2.replace('$t8', '$24') cs_output2 = cs_output2.replace('$t9', '$25') cs_output2 = cs_output2.replace('$s0', '$16') cs_output2 = cs_output2.replace('$s1', '$17') cs_output2 = cs_output2.replace('$s2', '$18') cs_output2 = cs_output2.replace('$s3', '$19') cs_output2 = cs_output2.replace('$s4', '$20') cs_output2 = cs_output2.replace('$s5', '$21') cs_output2 = cs_output2.replace('$s6', '$22') cs_output2 = cs_output2.replace('$s7', '$23') cs_output2 = cs_output2.replace('$k0', '$26') cs_output2 = cs_output2.replace('$k1', '$27') print("\t%s = %s" %(hex_code, cs_output)) if __name__ == '__main__': if len(sys.argv) == 1: fnames = sys.stdin.readlines() for fname in fnames: test_file(fname.strip()) else: #print("Usage: ./test_mc.py ") test_file(sys.argv[1]) capstone-sys-0.15.0/capstone/suite/disasm_mc.sh000075500000000000000000000004730072674642500176360ustar 00000000000000#!/bin/sh # This script test all architectures by default. find MC/ -name *.cs | ./disasm_mc.py # To test just one architecture, specify the corresponsing dir: # $ find MC/X86 -name *.cs | ./disasm_mc.py # To test just one input file, run disasm_mc.py with that file: # $ ./disasm_mc.py MC/X86/x86-32-fma3.s.cs capstone-sys-0.15.0/capstone/suite/fuzz/Makefile000064400000000000000000000045570072674642500200050ustar 00000000000000# Capstone Disassembler Engine # By Philippe Antoine , 2018 include ../../config.mk include ../../functions.mk ifneq ($(CAPSTONE_STATIC),yes) $(error Needs static capstone.) endif # Verbose output? V ?= 0 INCDIR = ../../include ifndef BUILDDIR TESTDIR = . OBJDIR = . LIBDIR = ../.. else TESTDIR = $(BUILDDIR)/tests OBJDIR = $(BUILDDIR)/obj/tests LIBDIR = $(BUILDDIR) endif CFLAGS += -Wall -I$(INCDIR) LDFLAGS += -L$(LIBDIR) CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) FUZZLDFLAGS = LIBNAME = capstone BIN_EXT = AR_EXT = a ARCHIVE = $(LIBDIR)/lib$(LIBNAME).$(AR_EXT) .PHONY: all clean SOURCES = fuzz_disasm.c drivermc.c fuzz_harness.c driverbin.c platform.c OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) # reproducer using MC file as input REPRODUCERMC = $(addprefix $(TESTDIR)/,fuzz_disasm$(BIN_EXT)) # reproducer using raw binary file as input (as produced by fuzzer) REPRODUCERBIN = $(addprefix $(TESTDIR)/,fuzz_bindisasm$(BIN_EXT)) # fuzzer FUZZERBIN = $(addprefix $(TESTDIR)/,fuzz_bindisasm2$(BIN_EXT)) PLATFORMDECODE = $(addprefix $(TESTDIR)/,fuzz_decode_platform$(BIN_EXT)) all: $(REPRODUCERMC) $(REPRODUCERBIN) $(FUZZERBIN) $(PLATFORMDECODE) clean: rm -rf fuzz_harness $(OBJS) $(PLATFORMDECODE) $(REPRODUCERMC) $(REPRODUCERBIN) $(FUZZERBIN) $(OBJDIR)/lib$(LIBNAME).* $(OBJDIR)/$(LIBNAME).* rm -f *.d $(OBJDIR)/*.d $(REPRODUCERMC): fuzz_disasm.o drivermc.o platform.o @mkdir -p $(@D) ifeq ($(V),0) $(call log,LINK,$(notdir $@)) @$(link-static) else $(link-static) endif $(REPRODUCERBIN): fuzz_disasm.o driverbin.o platform.o @mkdir -p $(@D) ifeq ($(V),0) $(call log,LINK,$(notdir $@)) @$(link-static) else $(link-static) endif $(FUZZERBIN): FUZZLDFLAGS="-fsanitize=fuzzer" $(FUZZERBIN): fuzz_disasm.o platform.o @mkdir -p $(@D) ifeq ($(V),0) $(call log,LINK,$(notdir $@)) @$(link-static) || touch $(FUZZERBIN) else $(link-static) || touch $(FUZZERBIN) endif $(PLATFORMDECODE): fuzz_decode_platform.o platform.o @mkdir -p $(@D) ifeq ($(V),0) $(call log,LINK,$(notdir $@)) @$(link-static) else $(link-static) endif $(OBJDIR)/%.o: %.c @mkdir -p $(@D) ifeq ($(V),0) $(call log,CC,$(@:$(OBJDIR)/%=%)) @$(compile) else $(compile) endif define link-static $(CC) $(LDFLAGS) $(FUZZLDFLAGS) $^ $(ARCHIVE) -o $@ endef fuzz_harness: fuzz_harness.o ${CC} $< -O3 -Wall -l$(LIBNAME) -o $@ capstone-sys-0.15.0/capstone/suite/fuzz/README000064400000000000000000000001360072674642500172120ustar 00000000000000This directory contains a fuzz testing harness for Capstone. Run "make" to compile this code. capstone-sys-0.15.0/capstone/suite/fuzz/README.md000064400000000000000000000025040072674642500176120ustar 00000000000000Fuzzing =============== Build the fuzz target ------- To build the fuzz target, you can simply run `make` with appropriate flags set : ``` ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address -fsanitize=fuzzer-no-link" LDFLAGS="-fsanitize=address" make ``` You can replace `address` with another sanitizer : `memory` or `undefined` The fuzz target is then `suite/fuzz/fuzz_bindisasm2` You can find this in travis configuration `.travis.yml` Another way is to use oss-fuzz, see https://github.com/google/oss-fuzz/blob/master/projects/capstone/build.sh Fuzz drivers ------ There are custom drivers : - driverbin.c : prints cstool command before running one input - drivermc.c : converts MC test data to raw binary data before running as many inputs as there are lines in a file - onefile.c : simple one file driver For libfuzzer, the preferred main function is now to use linker option `-fsanitize=fuzzer` Fuzzit integration ------ Travis will build the fuzz target with the different sanitizers. Then, Travis will launch sanity fuzzit jobs as part of continuous integration (for each of the sanitizers) The fuzzit target ids are stored in a configuration file fuzzitid.txt and used by fuzzit.sh capstone-sys-0.15.0/capstone/suite/fuzz/driverbin.c000064400000000000000000000036070072674642500204700ustar 00000000000000#include #include #include #include #include #include "platform.h" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); int main(int argc, char** argv) { FILE * fp; uint8_t Data[0x1000]; size_t Size; DIR *d; struct dirent *dir; int r = 0; int i; if (argc != 2) { return 1; } d = opendir(argv[1]); if (d == NULL) { printf("Invalid directory\n"); return 2; } if (chdir(argv[1]) != 0) { closedir(d); printf("Invalid directory\n"); return 2; } while((dir = readdir(d)) != NULL) { //opens the file, get its size, and reads it into a buffer if (dir->d_type != DT_REG) { continue; } printf("Running file %s ", dir->d_name); fflush(stdout); fp = fopen(dir->d_name, "rb"); if (fp == NULL) { r = 3; break; } if (fseek(fp, 0L, SEEK_END) != 0) { fclose(fp); r = 4; break; } Size = ftell(fp); if (Size == (size_t) -1) { fclose(fp); r = 5; break; } else if (Size > 0x1000) { fclose(fp); continue; } if (fseek(fp, 0L, SEEK_SET) != 0) { fclose(fp); r = 7; break; } if (fread(Data, Size, 1, fp) != 1) { fclose(fp); r = 8; break; } if (Size > 0) { printf("command cstool %s\n", get_platform_cstoolname(Data[0])); } for (i=0; i #include #include #include int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); #define MAX_INSTR_SIZE 64 #define MAX_LINE_SIZE 128 int main(int argc, char** argv) { FILE * fp; uint8_t Data[MAX_INSTR_SIZE]; char line[MAX_LINE_SIZE]; size_t Size; char arch[MAX_LINE_SIZE]; char mode[MAX_LINE_SIZE]; unsigned int value; int i; if (argc < 2) { return 1; } for (i = 1; i < argc; i++) { //opens the file, get its size, and reads it into a buffer fp = fopen(argv[i], "rb"); if (fp == NULL) { return 2; } printf("Trying %s\n", argv[i]); if (fgets(line, MAX_LINE_SIZE, fp) == NULL) { break; } if (line[0] == '#') { if (sscanf(line, "# %[^,], %[^,]", arch, mode) != 2) { printf("Wrong mode %s\n", line); return 1; } if (strcmp(arch, "CS_ARCH_X86") == 0 && strcmp(mode, "CS_MODE_32") == 0) { Data[0] = 0; } else if (strcmp(arch, "CS_ARCH_X86") == 0 && strcmp(mode, "CS_MODE_64") == 0) { Data[0] = 1; } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_ARM") == 0) { Data[0] = 2; } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_THUMB") == 0) { Data[0] = 3; } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_ARM+CS_MODE_V8") == 0) { Data[0] = 4; } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_THUMB+CS_MODE_V8") == 0) { Data[0] = 5; } else if (strcmp(arch, "CS_ARCH_ARM") == 0 && strcmp(mode, "CS_MODE_THUMB+CS_MODE_MCLASS") == 0) { Data[0] = 6; } else if (strcmp(arch, "CS_ARCH_ARM64") == 0 && strcmp(mode, "0") == 0) { Data[0] = 7; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 8; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_MICRO") == 0) { Data[0] = 9; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS64") == 0) { Data[0] = 10; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32") == 0) { Data[0] = 11; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 12; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 13; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO") == 0) { Data[0] = 13; } else if (strcmp(arch, "CS_ARCH_PPC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 14; } else if (strcmp(arch, "CS_ARCH_SPARC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 15; } else if (strcmp(arch, "CS_ARCH_SPARC") == 0 && strcmp(mode, "CS_MODE_BIG_ENDIAN + CS_MODE_V9") == 0) { Data[0] = 16; } else if (strcmp(arch, "CS_ARCH_SYSZ") == 0 && strcmp(mode, "0") == 0) { Data[0] = 17; } else if (strcmp(arch, "CS_ARCH_XCORE") == 0 && strcmp(mode, "0") == 0) { Data[0] = 18; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 19; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN") == 0) { Data[0] = 20; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6") == 0) { Data[0] = 21; } else if (strcmp(arch, "CS_ARCH_MIPS") == 0 && strcmp(mode, "CS_MODE_MIPS32R6+CS_MODE_MICRO") == 0) { Data[0] = 22; } else if (strcmp(arch, "CS_ARCH_M68K") == 0 && strcmp(mode, "0") == 0) { Data[0] = 23; } else if (strcmp(arch, "CS_ARCH_M680X") == 0 && strcmp(mode, "CS_MODE_M680X_6809") == 0) { Data[0] = 24; } else if (strcmp(arch, "CS_ARCH_EVM") == 0 && strcmp(mode, "0") == 0) { Data[0] = 25; } else if (strcmp(arch, "CS_ARCH_BPF") == 0 && strstr(mode, "CS_MODE_BPF_CLASSIC") != NULL) { Data[0] = 29; } else if (strcmp(arch, "CS_ARCH_BPF") == 0 && strstr(mode, "CS_MODE_BPF_EXTENDED") != NULL) { Data[0] = 30; } else if (strcmp(arch, "CS_ARCH_RISCV") == 0 && strcmp(mode, "CS_MODE_RISCV32") == 0) { Data[0] = 44; } else if (strcmp(arch, "CS_ARCH_RISCV") == 0 && strcmp(mode, "CS_MODE_RISCV64") == 0) { Data[0] = 45; } else { printf("Unknown mode\n"); //fail instead of continue return 1; } } else { printf("No mode\n"); //fail instead of continue return 1; } while(1) { if (fgets(line, MAX_LINE_SIZE, fp) == NULL) { break; } Size = 1; // we start line at offset 0 and Data buffer at offset 1 // since Data[0] is option : arch + mode while (sscanf(line+(Size-1)*5, "0x%02x", &value) == 1) { Data[Size] = value; Size++; if (line[(Size-1)*5-1] != ',') { //end of pattern break; } else if (MAX_LINE_SIZE < (Size-1)*5) { printf("Line overflow\n"); return 1; } } //lauch fuzzer LLVMFuzzerTestOneInput(Data, Size); } fclose(fp); } return 0; } capstone-sys-0.15.0/capstone/suite/fuzz/fuzz_decode_platform.c000064400000000000000000000010510072674642500227000ustar 00000000000000// this tool decodes first input byte feed to OSS fuzz, that encodes arch+mode // by Nguyen Anh Quynh, 2019 #include #include #include #include "platform.h" int main(int argc, char **argv) { unsigned char data; if (argc != 2) { printf("Decoding OSS fuzz platform\n"); printf("Syntax: %s \n", argv[0]); return -1; } data = (unsigned int)strtol(argv[1], NULL, 16); printf("cstool arch+mode = %s\n", get_platform_cstoolname(data)); return 0; } capstone-sys-0.15.0/capstone/suite/fuzz/fuzz_diff.c000064400000000000000000000114470072674642500204730ustar 00000000000000 #include #include #include #include #include struct platform { cs_arch arch; cs_mode mode; char *comment; }; FILE * outfile = NULL; struct platform platforms[] = { { // item 0 CS_ARCH_X86, CS_MODE_32, "X86 32 (Intel syntax)" }, { // item 1 CS_ARCH_X86, CS_MODE_64, "X86 64 (Intel syntax)" }, { // item 2 CS_ARCH_ARM, CS_MODE_ARM, "ARM" }, { // item 3 CS_ARCH_ARM, CS_MODE_THUMB, "THUMB" }, { // item 4 CS_ARCH_ARM, (cs_mode)(CS_MODE_ARM + CS_MODE_V8), "Arm-V8" }, { // item 5 CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB+CS_MODE_V8), "THUMB+V8" }, { // item 6 CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), "Thumb-MClass" }, { // item 7 CS_ARCH_ARM64, (cs_mode)0, "ARM-64" }, { // item 8 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), "MIPS-32 (Big-endian)" }, { // item 9 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO), "MIPS-32 (micro)" }, { //item 10 CS_ARCH_MIPS, CS_MODE_MIPS64, "MIPS-64-EL (Little-endian)" }, { //item 11 CS_ARCH_MIPS, CS_MODE_MIPS32, "MIPS-32-EL (Little-endian)" }, { //item 12 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN), "MIPS-64 (Big-endian)" }, { //item 13 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), "MIPS-32 | Micro (Big-endian)" }, { //item 14 CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC-64" }, { //item 15 CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc" }, { //item 16 CS_ARCH_SPARC, (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), "SparcV9" }, { //item 17 CS_ARCH_SYSZ, (cs_mode)0, "SystemZ" }, { //item 18 CS_ARCH_XCORE, (cs_mode)0, "XCore" }, { //item 19 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), "MIPS-32R6 (Big-endian)" }, { //item 20 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), "MIPS-32R6 (Micro+Big-endian)" }, { //item 21 CS_ARCH_MIPS, CS_MODE_MIPS32R6, "MIPS-32R6 (Little-endian)" }, { //item 22 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO), "MIPS-32R6 (Micro+Little-endian)" }, { //item 23 CS_ARCH_M68K, (cs_mode)0, "M68K" }, { //item 24 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6809, "M680X_M6809" }, { //item 25 CS_ARCH_EVM, (cs_mode)0, "EVM" }, }; void LLVMFuzzerInit(); int LLVMFuzzerReturnOneInput(const uint8_t *Data, size_t Size, char * AssemblyText); int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { csh handle; cs_insn *insn; cs_err err; const uint8_t **Datap = &Data; size_t * Sizep = &Size; uint64_t address = 0x1000; char LLVMAssemblyText[80]; char CapstoneAssemblyText[80]; if (Size < 1) { // 1 byte for arch choice return 0; } else if (Size > 0x1000) { //limit input to 4kb Size = 0x1000; } if (outfile == NULL) { // we compute the output outfile = fopen("/dev/null", "w"); if (outfile == NULL) { return 0; } LLVMFuzzerInit(); } if (Data[0] >= sizeof(platforms)/sizeof(platforms[0])) { return 0; } if (LLVMFuzzerReturnOneInput(Data, Size, LLVMAssemblyText) == 1) { return 0; } err = cs_open(platforms[Data[0]].arch, platforms[Data[0]].mode, &handle); if (err) { return 0; } insn = cs_malloc(handle); Data++; Size--; assert(insn); if (cs_disasm_iter(handle, Datap, Sizep, &address, insn)) { snprintf(CapstoneAssemblyText, 80, "\t%s\t%s", insn->mnemonic, insn->op_str); if (strcmp(CapstoneAssemblyText, LLVMAssemblyText) != 0) { printf("capstone %s != llvm %s", CapstoneAssemblyText, LLVMAssemblyText); abort(); } } else { printf("capstone failed with llvm %s", LLVMAssemblyText); abort(); } cs_free(insn, 1); cs_close(&handle); return 0; } capstone-sys-0.15.0/capstone/suite/fuzz/fuzz_disasm.c000064400000000000000000000052330072674642500210370ustar 00000000000000// the following must precede stdio (woo, thanks msft) #if defined(_MSC_VER) && _MSC_VER < 1900 #define _CRT_SECURE_NO_WARNINGS #endif #include #include #include #include #include "platform.h" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); static FILE *outfile = NULL; int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { csh handle; cs_insn *all_insn; cs_detail *detail; cs_err err; unsigned int i; if (Size < 1) { // 1 byte for arch choice return 0; } else if (Size > 0x1000) { //limit input to 4kb Size = 0x1000; } if (outfile == NULL) { // we compute the output outfile = fopen("/dev/null", "w"); if (outfile == NULL) { return 0; } } i = get_platform_entry((uint8_t)Data[0]); err = cs_open(platforms[i].arch, platforms[i].mode, &handle); if (err) { return 0; } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); if (Data[0]&0x80) { //hack cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); } uint64_t address = 0x1000; size_t count = cs_disasm(handle, Data+1, Size-1, address, 0, &all_insn); if (count) { size_t j; unsigned int n; for (j = 0; j < count; j++) { cs_insn *i = &(all_insn[j]); fprintf(outfile, "0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", i->address, i->mnemonic, i->op_str, i->id, cs_insn_name(handle, i->id)); detail = i->detail; if (detail->regs_read_count > 0) { fprintf(outfile, "\tImplicit registers read: "); for (n = 0; n < detail->regs_read_count; n++) { fprintf(outfile, "%s ", cs_reg_name(handle, detail->regs_read[n])); } } if (detail->regs_write_count > 0) { fprintf(outfile, "\tImplicit registers modified: "); for (n = 0; n < detail->regs_write_count; n++) { fprintf(outfile, "%s ", cs_reg_name(handle, detail->regs_write[n])); } } if (detail->groups_count > 0) { fprintf(outfile, "\tThis instruction belongs to groups: "); for (n = 0; n < detail->groups_count; n++) { fprintf(outfile, "%s ", cs_group_name(handle, detail->groups[n])); } } } fprintf(outfile, "0x%"PRIx64":\n", all_insn[j-1].address + all_insn[j-1].size); cs_free(all_insn, count); } cs_close(&handle); return 0; } capstone-sys-0.15.0/capstone/suite/fuzz/fuzz_disasm.options000064400000000000000000000000330072674642500223010ustar 00000000000000[libfuzzer] max_len = 4096 capstone-sys-0.15.0/capstone/suite/fuzz/fuzz_harness.c000064400000000000000000000106740072674642500212270ustar 00000000000000#include #include #include #include struct platform { cs_arch arch; cs_mode mode; char *comment; }; int main(int argc, char **argv) { if (argc != 2) { printf("Usage: %s \n", argv[0]); return 1; } struct platform platforms[] = { { CS_ARCH_X86, CS_MODE_32, "X86 32 (Intel syntax)" }, { CS_ARCH_X86, CS_MODE_64, "X86 64 (Intel syntax)" }, { CS_ARCH_ARM, CS_MODE_ARM, "ARM" }, { CS_ARCH_ARM, CS_MODE_THUMB, "THUMB-2" }, { CS_ARCH_ARM, CS_MODE_ARM, "ARM: Cortex-A15 + NEON" }, { CS_ARCH_ARM, CS_MODE_THUMB, "THUMB" }, { CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), "Thumb-MClass" }, { CS_ARCH_ARM, (cs_mode)(CS_MODE_ARM + CS_MODE_V8), "Arm-V8" }, { CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), "MIPS-32 (Big-endian)" }, { CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN), "MIPS-64-EL (Little-endian)" }, { CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), "MIPS-32R6 | Micro (Big-endian)" }, { CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), "MIPS-32R6 (Big-endian)" }, { CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64" }, { CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC-64" }, { CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc" }, { CS_ARCH_SPARC, (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), "SparcV9" }, { CS_ARCH_SYSZ, (cs_mode)0, "SystemZ" }, { CS_ARCH_XCORE, (cs_mode)0, "XCore" }, { CS_ARCH_M68K, (cs_mode)0, "M68K" }, { CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6809, "M680X_M6809" }, }; // Read input long bufsize = 0; unsigned char *buf = NULL; FILE *fp = fopen(argv[1], "r"); if (fp == NULL) return 1; if (fseek(fp, 0L, SEEK_END) == 0) { bufsize = ftell(fp); if (bufsize == -1) return 1; buf = malloc(bufsize + 1); if (buf == NULL) return 1; if (fseek(fp, 0L, SEEK_SET) != 0) return 1; size_t len = fread(buf, sizeof(char), bufsize, fp); if (len == 0) return 2; } fclose(fp); // Disassemble csh handle; cs_insn *all_insn; cs_detail *detail; cs_err err; if (bufsize < 3) return 0; int platforms_len = sizeof(platforms)/sizeof(platforms[0]); int i = (int)buf[0] % platforms_len; unsigned char *buf_ptr = buf + 1; long buf_ptr_size = bufsize - 1; printf("Platform: %s (0x%.2x of 0x%.2x)\n", platforms[i].comment, i, platforms_len); err = cs_open(platforms[i].arch, platforms[i].mode, &handle); if (err) { printf("Failed on cs_open() with error returned: %u\n", err); return 1; } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); uint64_t address = 0x1000; size_t count = cs_disasm(handle, buf_ptr, buf_ptr_size, address, 0, &all_insn); if (count) { size_t j; int n; printf("Disasm:\n"); for (j = 0; j < count; j++) { cs_insn *i = &(all_insn[j]); printf("0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", i->address, i->mnemonic, i->op_str, i->id, cs_insn_name(handle, i->id)); detail = i->detail; if (detail->regs_read_count > 0) { printf("\tImplicit registers read: "); for (n = 0; n < detail->regs_read_count; n++) { printf("%s ", cs_reg_name(handle, detail->regs_read[n])); } printf("\n"); } if (detail->regs_write_count > 0) { printf("\tImplicit registers modified: "); for (n = 0; n < detail->regs_write_count; n++) { printf("%s ", cs_reg_name(handle, detail->regs_write[n])); } printf("\n"); } if (detail->groups_count > 0) { printf("\tThis instruction belongs to groups: "); for (n = 0; n < detail->groups_count; n++) { printf("%s ", cs_group_name(handle, detail->groups[n])); } printf("\n"); } } printf("0x%"PRIx64":\n", all_insn[j-1].address + all_insn[j-1].size); cs_free(all_insn, count); } else { printf("ERROR: Failed to disasm given code!\n"); } printf("\n"); free(buf); cs_close(&handle); return 0; } capstone-sys-0.15.0/capstone/suite/fuzz/fuzz_llvm.cpp000064400000000000000000000021060072674642500210650ustar 00000000000000#include "llvm-c/Disassembler.h" #include "llvm-c/Target.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; extern "C" void LLVMFuzzerInit() { LLVMInitializeAllTargetInfos(); LLVMInitializeAllTargetMCs(); LLVMInitializeAllDisassemblers(); } extern "C" int LLVMFuzzerReturnOneInput(const uint8_t *Data, size_t Size, char * AssemblyText) { LLVMDisasmContextRef Ctx; std::vector DataCopy(Data, Data + Size); uint8_t *p = DataCopy.data(); int r = 1; switch(Data[0]) { case 0: Ctx = LLVMCreateDisasmCPUFeatures("i386", "", "", nullptr, 0, nullptr, nullptr); if (LLVMSetDisasmOptions(Ctx, LLVMDisassembler_Option_AsmPrinterVariant) == 0) { abort(); } break; //TODO other cases default: return 1; } assert(Ctx); if (LLVMDisasmInstruction(Ctx, p+1, Size-1, 0, AssemblyText, 80) > 0) { r = 0; } LLVMDisasmDispose(Ctx); return r; } capstone-sys-0.15.0/capstone/suite/fuzz/fuzzit.sh000075500000000000000000000015760072674642500202350ustar 00000000000000FUZZIT_API_KEY=f10b19a56d96b29dfdfe459d41b3d82e475e49c737095c74c99d65a032d5c2ab84d44dad510886bc824f101a860b1754 [ -s ./suite/fuzz/fuzz_bindisasm2 ] || exit 0 if [ ${TRAVIS_EVENT_TYPE} -eq 'cron' ]; then FUZZING_TYPE=fuzzing else FUZZING_TYPE=sanity fi if [ "$TRAVIS_PULL_REQUEST" = "false" ]; then FUZZIT_BRANCH="${TRAVIS_BRANCH}" else FUZZIT_BRANCH="PR-${TRAVIS_PULL_REQUEST}" fi FUZZIT_ARGS="--type ${FUZZING_TYPE} --branch ${FUZZIT_BRANCH} --revision ${TRAVIS_COMMIT}" if [ -n "$UBSAN_OPTIONS" ]; then FUZZIT_ARGS+=" --ubsan_options ${UBSAN_OPTIONS}" fi wget -O fuzzit https://github.com/fuzzitdev/fuzzit/releases/download/v1.2.5/fuzzit_1.2.5_Linux_x86_64 chmod +x fuzzit ./fuzzit auth ${FUZZIT_API_KEY} set -x grep "$QA_FUZZIT" suite/fuzz/fuzzitid.txt | cut -d" " -f2 | while read i; do ./fuzzit c job ${FUZZIT_ARGS} ${i} ./suite/fuzz/fuzz_bindisasm2 done set +x capstone-sys-0.15.0/capstone/suite/fuzz/fuzzitid.txt000064400000000000000000000001160072674642500207410ustar 00000000000000asan A1NqPndmOVrguCNj95LZ msan JchjH3j58fOnB8ZXGyWl ubsan JqHqVabfDEqitOusrPFxcapstone-sys-0.15.0/capstone/suite/fuzz/onefile.c000064400000000000000000000017060072674642500201230ustar 00000000000000#include #include #include int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size); int main(int argc, char** argv) { FILE * fp; uint8_t *Data; size_t Size; if (argc != 2) { return 1; } //opens the file, get its size, and reads it into a buffer fp = fopen(argv[1], "rb"); if (fp == NULL) { return 2; } if (fseek(fp, 0L, SEEK_END) != 0) { fclose(fp); return 2; } Size = ftell(fp); if (Size == (size_t) -1) { fclose(fp); return 2; } if (fseek(fp, 0L, SEEK_SET) != 0) { fclose(fp); return 2; } Data = malloc(Size); if (Data == NULL) { fclose(fp); return 2; } if (fread(Data, Size, 1, fp) != 1) { fclose(fp); free(Data); return 2; } //lauch fuzzer LLVMFuzzerTestOneInput(Data, Size); free(Data); fclose(fp); return 0; } capstone-sys-0.15.0/capstone/suite/fuzz/platform.c000064400000000000000000000153010072674642500203220ustar 00000000000000#include "platform.h" struct platform platforms[] = { { // item 0 CS_ARCH_X86, CS_MODE_32, "X86 32 (Intel syntax)", "x32" }, { // item 1 CS_ARCH_X86, CS_MODE_64, "X86 64 (Intel syntax)", "x64" }, { // item 2 CS_ARCH_ARM, CS_MODE_ARM, "ARM", "arm" }, { // item 3 CS_ARCH_ARM, CS_MODE_THUMB, "THUMB", "thumb" }, { // item 4 CS_ARCH_ARM, (cs_mode)(CS_MODE_ARM + CS_MODE_V8), "Arm-V8", "armv8" }, { // item 5 CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB+CS_MODE_V8), "THUMB+V8", "thumbv8" }, { // item 6 CS_ARCH_ARM, (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS), "Thumb-MClass", "cortexm" }, { // item 7 CS_ARCH_ARM64, (cs_mode)0, "ARM-64", "arm64" }, { // item 8 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN), "MIPS-32 (Big-endian)", "mipsbe" }, { // item 9 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO), "MIPS-32 (micro)", "mipsmicro" }, { //item 10 CS_ARCH_MIPS, CS_MODE_MIPS64, "MIPS-64-EL (Little-endian)", "mips64" }, { //item 11 CS_ARCH_MIPS, CS_MODE_MIPS32, "MIPS-32-EL (Little-endian)", "mips" }, { //item 12 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN), "MIPS-64 (Big-endian)", "mips64be" }, { //item 13 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), "MIPS-32 | Micro (Big-endian)", "mipsbemicro" }, { //item 14 CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, "PPC-64", "ppc64be" }, { //item 15 CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", "sparc" }, { //item 16 CS_ARCH_SPARC, (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9), "SparcV9", "sparcv9" }, { //item 17 CS_ARCH_SYSZ, (cs_mode)0, "SystemZ", "systemz" }, { //item 18 CS_ARCH_XCORE, (cs_mode)0, "XCore", "xcore" }, { //item 19 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN), "MIPS-32R6 (Big-endian)", "mipsbe32r6" }, { //item 20 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN), "MIPS-32R6 (Micro+Big-endian)", "mipsbe32r6micro" }, { //item 21 CS_ARCH_MIPS, CS_MODE_MIPS32R6, "MIPS-32R6 (Little-endian)", "mips32r6" }, { //item 22 CS_ARCH_MIPS, (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO), "MIPS-32R6 (Micro+Little-endian)", "mips32r6micro" }, { //item 23 CS_ARCH_M68K, (cs_mode)0, "M68K", "m68k" }, { //item 24 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6809, "M680X_M6809", "m6809" }, { //item 25 CS_ARCH_EVM, (cs_mode)0, "EVM", "evm" }, { //item 26 CS_ARCH_MOS65XX, (cs_mode)0, "MOS65XX", "mos65xx" }, { //item 27 CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN, "tms320c64x", "tms320c64x" }, { //item 28 CS_ARCH_WASM, (cs_mode)0, "WASM", "wasm" }, { //item 29 CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC, "cBPF", "bpf" }, { //item 30 CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, "eBPF", "ebpf" }, { //item 31 CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC, "cBPF", "bpfbe" }, { //item 32 CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED, "eBPF", "ebpfbe" }, { // item 33 CS_ARCH_X86, CS_MODE_16, "X86 16 (Intel syntax)", "x16" }, { // item 34 CS_ARCH_M68K, CS_MODE_M68K_040, "M68K mode 40", "m68k40" }, { //item 35 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6800, "M680X_M6800", "m6800" }, { //item 36 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6801, "M680X_M6801", "m6801" }, { //item 37 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6805, "M680X_M6805", "m6805" }, { //item 38 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6808, "M680X_M6808", "m6808" }, { //item 39 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6811, "M680X_M6811", "m6811" }, { //item 40 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_CPU12, "M680X_cpu12", "cpu12" }, { //item 41 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6301, "M680X_M6808", "hd6301" }, { //item 42 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_6309, "M680X_M6808", "hd6309" }, { //item 43 CS_ARCH_M680X, (cs_mode)CS_MODE_M680X_HCS08, "M680X_M6808", "hcs08" }, { //item 44 CS_ARCH_RISCV, CS_MODE_RISCV32, "RISCV", "riscv32" }, { //item 45 CS_ARCH_RISCV, CS_MODE_RISCV64, "RISCV", "riscv64" }, { //item 46 CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX, "ppc+qpx", "ppc64beqpx" }, // dummy entry to mark the end of this array. // DO NOT DELETE THIS { 0, 0, NULL, NULL, }, }; // get length of platforms[] unsigned int platform_len(void) { unsigned int c; for(c = 0; platforms[c].cstoolname; c++); return c; } // get platform entry encoded n (first byte for input data of OSS fuzz) unsigned int get_platform_entry(uint8_t n) { return n % platform_len(); } // get cstoolname from encoded n (first byte for input data of OSS fuzz) const char *get_platform_cstoolname(uint8_t n) { return platforms[get_platform_entry(n)].cstoolname; } capstone-sys-0.15.0/capstone/suite/fuzz/platform.h000064400000000000000000000010400072674642500203220ustar 00000000000000#ifndef CS_FUZZ_PLATFORM_H #define CS_FUZZ_PLATFORM_H #include struct platform { cs_arch arch; cs_mode mode; const char *comment; const char *cstoolname; }; extern struct platform platforms[]; // get length of platforms[] unsigned int platform_len(void); // get platform entry encoded n (first byte for input data of OSS fuzz) unsigned int get_platform_entry(uint8_t n); // get cstoolname from encoded n (first byte for input data of OSS fuzz) const char *get_platform_cstoolname(uint8_t n); #endif capstone-sys-0.15.0/capstone/suite/fuzz.py000075500000000000000000000076400072674642500167160ustar 00000000000000#!/usr/bin/python # Simple fuzzing tool by disassembling random code. By Nguyen Anh Quynh, 2014 # Syntax: # ./suite/fuzz.py --> Fuzz all archs # ./suite/fuzz.py x86 --> Fuzz all X86 (all 16bit, 32bit, 64bit) # ./suite/fuzz.py x86-16 --> Fuzz X86-32 arch only # ./suite/fuzz.py x86-32 --> Fuzz X86-32 arch only # ./suite/fuzz.py x86-64 --> Fuzz X86-64 arch only # ./suite/fuzz.py arm --> Fuzz all ARM (arm, thumb) # ./suite/fuzz.py aarch64 --> Fuzz ARM-64 # ./suite/fuzz.py mips --> Fuzz all Mips (32bit, 64bit) # ./suite/fuzz.py ppc --> Fuzz PPC from capstone import * from time import time from random import randint import sys # file providing code to disassemble FILE = '/usr/bin/python' TIMES = 64 INTERVALS = (4, 5, 7, 9, 11, 13) all_tests = ( (CS_ARCH_X86, CS_MODE_16, "X86-16bit (Intel syntax)", 0), (CS_ARCH_X86, CS_MODE_16, "X86-16bit (ATT syntax)", CS_OPT_SYNTAX_ATT), (CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0), (CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT), (CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0), (CS_ARCH_X86, CS_MODE_64, "X86-64 (ATT syntax)", CS_OPT_SYNTAX_ATT), (CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0), (CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0), (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0), (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0), (CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0), (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0), (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME), (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0), (CS_ARCH_SYSZ, 0, "SystemZ", 0), (CS_ARCH_XCORE, 0, "XCore", 0), (CS_ARCH_M68K, 0, "M68K", 0), (CS_ARCH_RISCV, CS_MODE_RISCV32, "riscv32", 0), (CS_ARCH_RISCV, CS_MODE_RISCV64, "riscv64", 0), ) # for debugging def to_hex(s): return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK # read @size bytes from @f & return data. # return None when there is not enough data def get_code(f, size): code = f.read(size) if len(code) != size: # reached end-of-file? # then reset file position to begin-of-file f.seek(0) return None return code def cs(md, code): insns = md.disasm(code, 0) for i in insns: if i.address == 0x100000: print i def cs_lite(md, code): insns = md.disasm_lite(code, 0) for (addr, size, mnem, ops) in insns: if addr == 0x100000: print i cfile = open(FILE) for (arch, mode, comment, syntax) in all_tests: try: request = sys.argv[1] if not request in comment.lower(): continue except: pass try: md = Cs(arch, mode) md.detail = True if syntax != 0: md.syntax = syntax # test disasm() print("\nFuzzing disasm() @platform: %s" %comment) for ii in INTERVALS: print("Interval: %u" %ii) for j in xrange(1, TIMES): while (True): code = get_code(cfile, j * ii) if code is None: # EOF? break break #print to_hex(code) cs(md, code) # test disasm_lite() print("Fuzzing disasm_lite() @platform: %s" %comment) for ii in INTERVALS: print("Interval: %u" %ii) for j in xrange(1, TIMES): while (True): code = get_code(cfile, j * ii) if code is None: # EOF? break break #print to_hex(code) cs_lite(md, code) except CsError as e: print("ERROR: %s" %e) capstone-sys-0.15.0/capstone/suite/patch_major_os_version.py000075500000000000000000000014260072674642500224510ustar 00000000000000#!/usr/bin/env python # By Daniel Pistelli & Nguyen Tan Cong # This script is to patch DLL/EXE MajorVersion to 5, # so they can be loaded by Windows XP. # This is the problem introduced by compiling on Windows 7, using VS2013. import sys, struct if len(sys.argv) < 2: print("Usage: %s " % sys.argv[0]) sys.exit(0) pe_file_path = sys.argv[1] with open(pe_file_path, "rb") as f: b = f.read() if not b.startswith("MZ"): print("Not a PE file") sys.exit(0) e_lfanew = struct.unpack_from(" # PPC Branch testing suite by kratolp from __future__ import print_function import sys from capstone import * CODE32 = b"\x48\x01\x05\x15" # bl .+0x10514 CODE32 += b"\x4B\xff\xff\xfd" # bl .-0x4 CODE32 += b"\x48\x00\x00\x0c" # b .+0xc CODE32 += b"\x41\x80\xff\xd8" # blt .-0x28 CODE32 += b"\x40\x80\xff\xec" # bge .-0x14 CODE32 += b"\x41\x84\x01\x6c" # blt cr1, .+0x16c CODE32 += b"\x41\x82\x00\x10" # beq .+0x10 CODE32 += b"\x40\x82\x00\x08" # bne .+0x8 CODE32 += b"\x40\x95\x00\x94" # ble cr5,.+0x94 CODE32 += b"\x40\x9f\x10\x30" # bns cr5,.+0x94 CODE32 += b"\x42\x00\xff\xd8" # bdnz .-0x28 CODE32 += b"\x4d\x82\x00\x20" # beqlr CODE32 += b"\x4e\x80\x00\x20" # blr CODE32 += b"\x4a\x00\x00\x02" # ba .0xfe000000 CODE32 += b"\x41\x80\xff\xda" # blta .0xffffffd8 CODE32 += b"\x41\x4f\xff\x17" # bdztla 4*cr3+so, .0xffffff14 CODE32 += b"\x43\x20\x0c\x07" # bdnzla+ .0xc04 CODE32 += b"\x4c\x00\x04\x20" # bdnzfctr lt _python3 = sys.version_info.major == 3 all_tests = ( (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CODE32, "PPC branch instruction decoding", 0), ) def to_hex(s): if _python3: return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK else: return " ".join("0x{0:02x}".format(ord(c)) for c in s) # ## Test cs_disasm_quick() def test_cs_disasm_quick(): for (arch, mode, code, comment, syntax) in all_tests: print("Platform: %s" % comment) print("Code: %s" %(to_hex(code))), print("Disasm:") for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000): print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str)) print() if __name__ == '__main__': test_cs_disasm_quick() capstone-sys-0.15.0/capstone/suite/python_capstone_setup.py000075500000000000000000000001770072674642500223530ustar 00000000000000#!/bin/sh # this prints out Capstone setup & core+Python-binding versions python -c "import capstone; print capstone.debug()" capstone-sys-0.15.0/capstone/suite/regress.py000075500000000000000000002410670072674642500173750ustar 00000000000000#!/usr/bin/env python # Capstone Python bindings, by Nguyen Anh Quynnh from __future__ import print_function import sys from capstone import * all_tests = ( # arch, mode, syntax, address, hexcode, expected output # issue 456 https://github.com/aquynh/capstone/issues/456 (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xfc16, b"\xE8\x35\x64", "call 0x604e"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123fc1b, b"\x66\xE8\x35\x64", "call 0x6054"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x9123fc1b, b"\x66\xE8\x35\x64", "call 0x6054"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xfc26, b"\xE9\x35\x64", "jmp 0x605e"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xfff6, b"\x66\xE9\x35\x64\x93\x53", "jmp 0x53946431"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0xe4b7642b"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0x64e4b7642b"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xe8\x35\x64\x93\x53", "call 0x5394641c"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xe8\x35\x64", "call 0x641a"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xe9\x35\x64", "jmp 0x641a"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xe9\x35\x64\x93\x53", "jmp 0x5394641c"), # AT&T syntax (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xfc16, b"\xE8\x35\x64", "callw 0x604e"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT, 0x9123fc1b, b"\x66\xE8\x35\x64", "callw 0x6054"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x9123fc1b, b"\x66\xE8\x35\x64", "callw 0x6054"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xfc26, b"\xE9\x35\x64", "jmp 0x605e"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xfff6, b"\x66\xE9\x35\x64\x93\x53", "jmp 0x53946431"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT, 0x9123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0xe4b7642b"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x649123fff1, b"\xE9\x35\x64\x93\x53", "jmp 0x64e4b7642b"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xffe1, b"\x66\xe8\x35\x64\x93\x53", "calll 0x5394641c"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x649123ffe1, b"\x66\xe8\x35\x64", "callw 0x641a"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT, 0x649123ffe1, b"\x66\xe9\x35\x64", "jmp 0x641a"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_ATT, 0xffe1, b"\x66\xe9\x35\x64\x93\x53", "jmp 0x5394641c"), # issue 452 https://github.com/aquynh/capstone/issues/452 (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6C", "insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6D", "insw word ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6E", "outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x6F", "outsw dx, word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA4", "movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA5", "movsw word ptr es:[di], word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xA7", "cmpsw word ptr [si], word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAA", "stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAB", "stosw word ptr es:[di], ax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAC", "lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAD", "lodsw ax, word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAE", "scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xAF", "scasw ax, word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6C", "insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6D", "insd dword ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6E", "outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x6F", "outsd dx, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA4", "movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA5", "movsd dword ptr es:[di], dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xA7", "cmpsd dword ptr [si], dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAA", "stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAB", "stosd dword ptr es:[di], eax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAC", "lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAD", "lodsd eax, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAE", "scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xAF", "scasd eax, dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6C", "insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6D", "insw word ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6E", "outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\x6F", "outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA5", "movsw word ptr es:[edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xA7", "cmpsw word ptr [esi], word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAA", "stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAB", "stosw word ptr es:[edi], ax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAD", "lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAE", "scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xAF", "scasw ax, word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6C", "repne insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6D", "repne insw word ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6E", "repne outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\x6F", "repne outsw dx, word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA5", "repne movsw word ptr es:[di], word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xA7", "repne cmpsw word ptr [si], word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAA", "repne stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAB", "repne stosw word ptr es:[di], ax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAC", "repne lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAD", "repne lodsw ax, word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAE", "repne scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF2\xAF", "repne scasw ax, word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6C", "rep insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6D", "rep insw word ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6E", "rep outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\x6F", "rep outsw dx, word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA5", "rep movsw word ptr es:[di], word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xA7", "repe cmpsw word ptr [si], word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAA", "rep stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAB", "rep stosw word ptr es:[di], ax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAC", "rep lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAD", "rep lodsw ax, word ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAE", "repe scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\xF3\xAF", "repe scasw ax, word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6C", "insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6D", "insd dword ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6E", "outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\x6F", "outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA5", "movsd dword ptr es:[edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xA7", "cmpsd dword ptr [esi], dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAA", "stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAB", "stosd dword ptr es:[edi], eax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAD", "lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAE", "scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xAF", "scasd eax, dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6C", "repne insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6D", "repne insd dword ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6E", "repne outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\x6F", "repne outsd dx, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA5", "repne movsd dword ptr es:[di], dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xA7", "repne cmpsd dword ptr [si], dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAA", "repne stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAB", "repne stosd dword ptr es:[di], eax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAC", "repne lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAD", "repne lodsd eax, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAE", "repne scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF2\xAF", "repne scasd eax, dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6C", "rep insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6D", "rep insd dword ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6E", "rep outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\x6F", "rep outsd dx, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA5", "rep movsd dword ptr es:[di], dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xA7", "repe cmpsd dword ptr [si], dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAA", "rep stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAB", "rep stosd dword ptr es:[di], eax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAC", "rep lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAD", "rep lodsd eax, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAE", "repe scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\xF3\xAF", "repe scasd eax, dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6C", "repne insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6D", "repne insw word ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\x6F", "repne outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA5", "repne movsw word ptr es:[edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xA7", "repne cmpsw word ptr [esi], word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAA", "repne stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAB", "repne stosw word ptr es:[edi], ax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAD", "repne lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF2\xAF", "repne scasw ax, word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6C", "rep insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6D", "rep insw word ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\x6F", "rep outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA5", "rep movsw word ptr es:[edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xA7", "repe cmpsw word ptr [esi], word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAA", "rep stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAB", "rep stosw word ptr es:[edi], ax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAD", "rep lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x67\xF3\xAF", "repe scasw ax, word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6C", "repne insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6D", "repne insd dword ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\x6F", "repne outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA5", "repne movsd dword ptr es:[edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xA7", "repne cmpsd dword ptr [esi], dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAA", "repne stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAB", "repne stosd dword ptr es:[edi], eax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAD", "repne lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF2\xAF", "repne scasd eax, dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6C", "rep insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6D", "rep insd dword ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\x6F", "rep outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA5", "rep movsd dword ptr es:[edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xA7", "repe cmpsd dword ptr [esi], dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAA", "rep stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAB", "rep stosd dword ptr es:[edi], eax"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAD", "rep lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x67\xF3\xAF", "repe scasd eax, dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6C", "insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6D", "insd dword ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6E", "outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x6F", "outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA5", "movsd dword ptr es:[edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xA7", "cmpsd dword ptr [esi], dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAA", "stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAB", "stosd dword ptr es:[edi], eax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAD", "lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAE", "scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xAF", "scasd eax, dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6C", "insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6D", "insw word ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6E", "outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x6F", "outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA4", "movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA5", "movsw word ptr es:[edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA6", "cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xA7", "cmpsw word ptr [esi], word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAA", "stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAB", "stosw word ptr es:[edi], ax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAD", "lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAE", "scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xAF", "scasw ax, word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6C", "insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6D", "insd dword ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6E", "outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\x6F", "outsd dx, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA4", "movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA5", "movsd dword ptr es:[di], dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xA7", "cmpsd dword ptr [si], dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAA", "stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAB", "stosd dword ptr es:[di], eax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAC", "lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAD", "lodsd eax, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAE", "scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xAF", "scasd eax, dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6C", "repne insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6D", "repne insd dword ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6E", "repne outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\x6F", "repne outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA5", "repne movsd dword ptr es:[edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xA7", "repne cmpsd dword ptr [esi], dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAA", "repne stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAB", "repne stosd dword ptr es:[edi], eax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAD", "repne lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF2\xAF", "repne scasd eax, dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6C", "rep insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6D", "rep insd dword ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6E", "rep outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\x6F", "rep outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA5", "rep movsd dword ptr es:[edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xA7", "repe cmpsd dword ptr [esi], dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAA", "rep stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAB", "rep stosd dword ptr es:[edi], eax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAD", "rep lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\xF3\xAF", "repe scasd eax, dword ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6C", "insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6D", "insw word ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6E", "outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\x6F", "outsw dx, word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA4", "movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA5", "movsw word ptr es:[di], word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA6", "cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xA7", "cmpsw word ptr [si], word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAA", "stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAB", "stosw word ptr es:[di], ax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAC", "lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAD", "lodsw ax, word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAE", "scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xAF", "scasw ax, word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6C", "repne insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6D", "repne insw word ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6E", "repne outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\x6F", "repne outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA4", "repne movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA5", "repne movsw word ptr es:[edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xA7", "repne cmpsw word ptr [esi], word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAA", "repne stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAB", "repne stosw word ptr es:[edi], ax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAD", "repne lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAE", "repne scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF2\xAF", "repne scasw ax, word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6C", "rep insb byte ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6D", "rep insw word ptr es:[edi], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6E", "rep outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\x6F", "rep outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA4", "rep movsb byte ptr es:[edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA5", "rep movsw word ptr es:[edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xA7", "repe cmpsw word ptr [esi], word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAA", "rep stosb byte ptr es:[edi], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAB", "rep stosw word ptr es:[edi], ax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAD", "rep lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAE", "repe scasb al, byte ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\xF3\xAF", "repe scasw ax, word ptr es:[edi]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6C", "repne insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6D", "repne insd dword ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6E", "repne outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\x6F", "repne outsd dx, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA5", "repne movsd dword ptr es:[di], dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xA7", "repne cmpsd dword ptr [si], dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAA", "repne stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAB", "repne stosd dword ptr es:[di], eax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAC", "repne lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAD", "repne lodsd eax, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAE", "repne scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF2\xAF", "repne scasd eax, dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6C", "rep insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6D", "rep insd dword ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6E", "rep outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\x6F", "rep outsd dx, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA5", "rep movsd dword ptr es:[di], dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xA7", "repe cmpsd dword ptr [si], dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAA", "rep stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAB", "rep stosd dword ptr es:[di], eax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAC", "rep lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAD", "rep lodsd eax, dword ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAE", "repe scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x67\xF3\xAF", "repe scasd eax, dword ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6C", "repne insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6D", "repne insw word ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6E", "repne outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\x6F", "repne outsw dx, word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA4", "repne movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA5", "repne movsw word ptr es:[di], word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA6", "repne cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xA7", "repne cmpsw word ptr [si], word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAA", "repne stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAB", "repne stosw word ptr es:[di], ax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAC", "repne lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAD", "repne lodsw ax, word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAE", "repne scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF2\xAF", "repne scasw ax, word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6C", "rep insb byte ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6D", "rep insw word ptr es:[di], dx"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6E", "rep outsb dx, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\x6F", "rep outsw dx, word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA4", "rep movsb byte ptr es:[di], byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA5", "rep movsw word ptr es:[di], word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA6", "repe cmpsb byte ptr [si], byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xA7", "repe cmpsw word ptr [si], word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAA", "rep stosb byte ptr es:[di], al"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAB", "rep stosw word ptr es:[di], ax"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAC", "rep lodsb al, byte ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAD", "rep lodsw ax, word ptr [si]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAE", "repe scasb al, byte ptr es:[di]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x67\xF3\xAF", "repe scasw ax, word ptr es:[di]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6C", "insb byte ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6D", "insd dword ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6E", "outsb dx, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x6F", "outsd dx, dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA5", "movsd dword ptr [rdi], dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xA7", "cmpsd dword ptr [rsi], dword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAA", "stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAB", "stosd dword ptr [rdi], eax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAC", "lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAD", "lodsd eax, dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAE", "scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xAF", "scasd eax, dword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6C", "insb byte ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6D", "insw word ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6E", "outsb dx, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x6F", "outsw dx, word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA5", "movsw word ptr [rdi], word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xA7", "cmpsw word ptr [rsi], word ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAA", "stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAB", "stosw word ptr [rdi], ax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAC", "lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAD", "lodsw ax, word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAE", "scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xAF", "scasw ax, word ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6C", "insb byte ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6D", "insd dword ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6E", "outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x6F", "outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA4", "movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA5", "movsd dword ptr [edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xA7", "cmpsd dword ptr [esi], dword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAA", "stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAB", "stosd dword ptr [edi], eax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAD", "lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAE", "scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xAF", "scasd eax, dword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6C", "repne insb byte ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6D", "repne insd dword ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6E", "repne outsb dx, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x6F", "repne outsd dx, dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA5", "repne movsd dword ptr [rdi], dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xA7", "repne cmpsd dword ptr [rsi], dword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAA", "repne stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAB", "repne stosd dword ptr [rdi], eax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAC", "repne lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAD", "repne lodsd eax, dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAE", "repne scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\xAF", "repne scasd eax, dword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6C", "rep insb byte ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6D", "rep insd dword ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6E", "rep outsb dx, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x6F", "rep outsd dx, dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA5", "rep movsd dword ptr [rdi], dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xA7", "repe cmpsd dword ptr [rsi], dword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAA", "rep stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAB", "rep stosd dword ptr [rdi], eax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAC", "rep lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAD", "rep lodsd eax, dword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAE", "repe scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\xAF", "repe scasd eax, dword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6C", "insb byte ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6D", "insw word ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6E", "outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x6F", "outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA4", "movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA5", "movsw word ptr [edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xA7", "cmpsw word ptr [esi], word ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAA", "stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAB", "stosw word ptr [edi], ax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAD", "lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAE", "scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xAF", "scasw ax, word ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6C", "repne insb byte ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6D", "repne insw word ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6E", "repne outsb dx, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x6F", "repne outsw dx, word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA5", "repne movsw word ptr [rdi], word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xA7", "repne cmpsw word ptr [rsi], word ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAA", "repne stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAB", "repne stosw word ptr [rdi], ax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAC", "repne lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAD", "repne lodsw ax, word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAE", "repne scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\xAF", "repne scasw ax, word ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6C", "rep insb byte ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6D", "rep insw word ptr [rdi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6E", "rep outsb dx, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x6F", "rep outsw dx, word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA5", "rep movsw word ptr [rdi], word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xA7", "repe cmpsw word ptr [rsi], word ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAA", "rep stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAB", "rep stosw word ptr [rdi], ax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAC", "rep lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAD", "rep lodsw ax, word ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAE", "repe scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\xAF", "repe scasw ax, word ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6C", "repne insb byte ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6D", "repne insd dword ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x6F", "repne outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA5", "repne movsd dword ptr [edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xA7", "repne cmpsd dword ptr [esi], dword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAA", "repne stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAB", "repne stosd dword ptr [edi], eax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAD", "repne lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAE", "repne scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\xAF", "repne scasd eax, dword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6C", "rep insb byte ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6D", "rep insd dword ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x6F", "rep outsd dx, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA5", "rep movsd dword ptr [edi], dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xA7", "repe cmpsd dword ptr [esi], dword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAA", "rep stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAB", "rep stosd dword ptr [edi], eax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAD", "rep lodsd eax, dword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAE", "repe scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\xAF", "repe scasd eax, dword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6C", "repne insb byte ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6D", "repne insw word ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6E", "repne outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x6F", "repne outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA5", "repne movsw word ptr [edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xA7", "repne cmpsw word ptr [esi], word ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAA", "repne stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAB", "repne stosw word ptr [edi], ax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAD", "repne lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAE", "repne scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\xAF", "repne scasw ax, word ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6C", "rep insb byte ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6D", "rep insw word ptr [edi], dx"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6E", "rep outsb dx, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x6F", "rep outsw dx, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA5", "rep movsw word ptr [edi], word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xA7", "repe cmpsw word ptr [esi], word ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAA", "rep stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAB", "rep stosw word ptr [edi], ax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAD", "rep lodsw ax, word ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAE", "repe scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\xAF", "repe scasw ax, word ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA5", "movsq qword ptr [rdi], qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xA7", "cmpsq qword ptr [rsi], qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAA", "stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAB", "stosq qword ptr [rdi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAC", "lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAD", "lodsq rax, qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAE", "scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x48\xAF", "scasq rax, qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA4", "movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA5", "movsq qword ptr [rdi], qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA6", "cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xA7", "cmpsq qword ptr [rsi], qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAA", "stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAB", "stosq qword ptr [rdi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAC", "lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAD", "lodsq rax, qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAE", "scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x48\xAF", "scasq rax, qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA4", "movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA5", "movsq qword ptr [edi], qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xA7", "cmpsq qword ptr [esi], qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAA", "stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAB", "stosq qword ptr [edi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAD", "lodsq rax, qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAE", "scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\x48\xAF", "scasq rax, qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA5", "repne movsq qword ptr [rdi], qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xA7", "repne cmpsq qword ptr [rsi], qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAA", "repne stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAB", "repne stosq qword ptr [rdi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAC", "repne lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAD", "repne lodsq rax, qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAE", "repne scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF2\x48\xAF", "repne scasq rax, qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA5", "rep movsq qword ptr [rdi], qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xA7", "repe cmpsq qword ptr [rsi], qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAA", "rep stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAB", "rep stosq qword ptr [rdi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAC", "rep lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAD", "rep lodsq rax, qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAE", "repe scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\xF3\x48\xAF", "repe scasq rax, qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA4", "movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA5", "movsq qword ptr [edi], qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA6", "cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xA7", "cmpsq qword ptr [esi], qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAA", "stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAB", "stosq qword ptr [edi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAC", "lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAD", "lodsq rax, qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAE", "scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\x48\xAF", "scasq rax, qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA4", "repne movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA5", "repne movsq qword ptr [rdi], qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA6", "repne cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xA7", "repne cmpsq qword ptr [rsi], qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAA", "repne stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAB", "repne stosq qword ptr [rdi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAC", "repne lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAD", "repne lodsq rax, qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAE", "repne scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF2\x48\xAF", "repne scasq rax, qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA4", "rep movsb byte ptr [rdi], byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA5", "rep movsq qword ptr [rdi], qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA6", "repe cmpsb byte ptr [rsi], byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xA7", "repe cmpsq qword ptr [rsi], qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAA", "rep stosb byte ptr [rdi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAB", "rep stosq qword ptr [rdi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAC", "rep lodsb al, byte ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAD", "rep lodsq rax, qword ptr [rsi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAE", "repe scasb al, byte ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\xF3\x48\xAF", "repe scasq rax, qword ptr [rdi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA5", "repne movsq qword ptr [edi], qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xA7", "repne cmpsq qword ptr [esi], qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAA", "repne stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAB", "repne stosq qword ptr [edi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAD", "repne lodsq rax, qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAE", "repne scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF2\x48\xAF", "repne scasq rax, qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA5", "rep movsq qword ptr [edi], qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xA7", "repe cmpsq qword ptr [esi], qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAA", "rep stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAB", "rep stosq qword ptr [edi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAD", "rep lodsq rax, qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAE", "repe scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x67\xF3\x48\xAF", "repe scasq rax, qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA4", "repne movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA5", "repne movsq qword ptr [edi], qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA6", "repne cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xA7", "repne cmpsq qword ptr [esi], qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAA", "repne stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAB", "repne stosq qword ptr [edi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAC", "repne lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAD", "repne lodsq rax, qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAE", "repne scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF2\x48\xAF", "repne scasq rax, qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA4", "rep movsb byte ptr [edi], byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA5", "rep movsq qword ptr [edi], qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA6", "repe cmpsb byte ptr [esi], byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xA7", "repe cmpsq qword ptr [esi], qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAA", "rep stosb byte ptr [edi], al"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAB", "rep stosq qword ptr [edi], rax"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAC", "rep lodsb al, byte ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAD", "rep lodsq rax, qword ptr [esi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAE", "repe scasb al, byte ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x67\xF3\x48\xAF", "repe scasq rax, qword ptr [edi]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x05\xa0\x90\x04\x08", "sgdt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x05", "sgdt [di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x05", "sgdt [di]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x0d\xa0\x90\x04\x08", "sidt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x0d", "sidt [di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x0d", "sidt [di]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x15\xa0\x90\x04\x08", "lgdt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x15", "lgdt [di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x15", "lgdt [di]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_INTEL, 0x649123ffe1, b"\x66\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [rip + 0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0x9123ffe1, b"\x66\x0f\x01\x1d\xa0\x90\x04\x08", "lidt [0x80490a0]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x0f\x01\x1d", "lidt [di]"), (CS_ARCH_X86, CS_MODE_16, CS_OPT_SYNTAX_INTEL, 0xffe1, b"\x66\x0f\x01\x1d", "lidt [di]"), # issues 702 https://github.com/aquynh/capstone/issues/702 (CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_INTEL, 0, b"\x85\xC8", "test eax, ecx") ) _python3 = sys.version_info.major == 3 def to_hex(s): if _python3: return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK else: return " ".join("0x{0:02x}".format(ord(c)) for c in s) def str_syntax(syntax): slist = { 0: "", CS_OPT_SYNTAX_INTEL: "intel", CS_OPT_SYNTAX_ATT: "att", } return slist[syntax] def str_arch_mode(a, m): amlist = { (CS_ARCH_X86, CS_MODE_16): "X86-16bit", (CS_ARCH_X86, CS_MODE_32): "X86-32bit", (CS_ARCH_X86, CS_MODE_64): "X86-64bit", } return amlist[(a, m)] # ## Test cs_disasm_quick() def test_regression(verbose): for (arch, mode, syntax, address, code, expected_output) in all_tests: #print("%s %s: %s = " %(str_arch_mode(arch, mode), str_syntax(syntax), to_hex(code)), end=""), output = "%s %s: %s = " %(str_arch_mode(arch, mode), str_syntax(syntax), to_hex(code)) md = Cs(arch, mode) if syntax != 0: md.syntax = syntax insn = list(md.disasm(code, address))[0] output2 = "%s %s" % (insn.mnemonic, insn.op_str) if output2 != expected_output: print(output, output2) print("\t --> ERROR: expected output = %s" %(expected_output)) elif verbose: print(output, output2) if __name__ == '__main__': import sys if len(sys.argv) == 2 and sys.argv[1] == "-v": test_regression(True) # quiet else: test_regression(False) # verbose capstone-sys-0.15.0/capstone/suite/synctools/.gitignore000064400000000000000000000002210072674642500213540ustar 00000000000000*.inc disassemblertables_reduce2 disassemblertables2 ppc_gen_reg arm64_gen_vreg strinforeduce/strinforeduce strinforeduce/strinforeduce_reduce capstone-sys-0.15.0/capstone/suite/synctools/Makefile000064400000000000000000000006170072674642500210350ustar 00000000000000all: x86: # compile disassembler2 with X86GenDisassemblerTables2.inc $(CC) disassemblertables2.c -o disassemblertables2 # compile disassembler2 with X86GenDisassemblerTables_reduce2.inc $(CC) -DCAPSTONE_X86_REDUCE disassemblertables2.c -o disassemblertables_reduce2 arm64: $(CC) arm64_gen_vreg.c -o arm64_gen_vreg clean: $(RM) disassemblertables2 disassemblertables_reduce2 arm64_gen_vreg capstone-sys-0.15.0/capstone/suite/synctools/README000064400000000000000000000046250072674642500202600ustar 00000000000000Sync tools to port LLVM inc files to Capstone. For X86 ======= 0. cd tablegen/, then follow its README. 1. Run genall-{full|reduce}.sh, then copy generated .inc files to arch// directory $ ./genall-full.sh tablegen ~/projects/tmp/capstone777.git/arch/X86 $ ./genall-reduce.sh tablegen ~/projects/tmp/capstone777.git/arch/X86 2. Run disassemblertables_reduce2 & disassemblertables_reduce2 to generate optimized (index table) X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc # use 2x name to avoid overwritting X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc $ make $ ./disassemblertables2 > X86GenDisassemblerTables2x.inc $ ./disassemblertables_reduce2 > X86GenDisassemblerTables_reduce2x.inc 3. cd strinforeduce/, and follow its README. 4. Copy all generated .inc files to arch/X86/ $ cp X86GenAsmWriter_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86GenAsmWriter1_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86MappingInsnName_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86MappingInsn_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86MappingInsnOp_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86GenInstrInfo_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86GenDisassemblerTables_reduce.inc ~/projects/capstone.git/arch/X86 $ cp X86GenDisassemblerTables_reduce2x.inc ~/projects/capstone.git/arch/X86/X86GenDisassemblerTables_reduce2.inc $ cp X86GenAsmWriter.inc ~/projects/capstone.git/arch/X86 $ cp X86GenAsmWriter1.inc ~/projects/capstone.git/arch/X86 $ cp X86MappingInsnName.inc ~/projects/capstone.git/arch/X86 $ cp X86MappingInsn.inc ~/projects/capstone.git/arch/X86 $ cp X86MappingInsnOp.inc ~/projects/capstone.git/arch/X86 $ cp X86GenInstrInfo.inc ~/projects/capstone.git/arch/X86 $ cp X86GenDisassemblerTables.inc ~/projects/capstone.git/arch/X86 $ cp X86GenDisassemblerTables2x.inc ~/projects/capstone.git/arch/X86/X86GenDisassemblerTables2.inc 5. copy insn_list.txt to include/capstone/ For non-X86 =========== 0. cd tablegen/, then follow its README. 1. Run gen-tablegen-arch.sh 2. Run genall-arch.sh ./genall-arch.sh tablegen ~/projects/capstone.git/arch/ARM ARM ./genall-arch.sh tablegen ~/projects/capstone.git/arch/ARM AArch64 ./genall-arch.sh tablegen ~/projects/capstone.git/arch/ARM PowerPC 3. Copy generated *.inc files to arch// capstone-sys-0.15.0/capstone/suite/synctools/X86DisassemblerDecoderCommon.h000064400000000000000000000717020072674642500251330ustar 00000000000000/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===* * * The LLVM Compiler Infrastructure * * This file is distributed under the University of Illinois Open Source * License. See LICENSE.TXT for details. * *===----------------------------------------------------------------------===* * * This file is part of the X86 Disassembler. * It contains common definitions used by both the disassembler and the table * generator. * Documentation for the disassembler can be found in X86Disassembler.h. * *===----------------------------------------------------------------------===*/ /* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ /* * This header file provides those definitions that need to be shared between * the decoder and the table generator in a C-friendly manner. */ #ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H #define CS_X86_DISASSEMBLERDECODERCOMMON_H #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers #define CONTEXTS_SYM x86DisassemblerContexts #define ONEBYTE_SYM x86DisassemblerOneByteOpcodes #define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes #define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes #define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes #define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes /* * Attributes of an instruction that must be known before the opcode can be * processed correctly. Most of these indicate the presence of particular * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. */ #define ATTRIBUTE_BITS \ ENUM_ENTRY(ATTR_NONE, 0x00) \ ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \ ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \ ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \ ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \ ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \ ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \ ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \ ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \ ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \ ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \ ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \ ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \ ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \ ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13)) #define ENUM_ENTRY(n, v) n = v, enum attributeBits { ATTRIBUTE_BITS ATTR_max }; #undef ENUM_ENTRY /* * Combinations of the above attributes that are relevant to instruction * decode. Although other combinations are possible, they can be reduced to * these without affecting the ultimately decoded instruction. */ // Class name Rank Rationale for rank assignment #define INSTRUCTION_CONTEXTS \ ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ "64-bit mode but no more") \ ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ "but not the operands") \ ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ "but not the operands") \ ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \ "operands change width") \ ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\ "change width; overrides IC_OPSIZE") \ ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \ "prefix") \ ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \ "IC_ADSIZE") \ ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \ "secondary") \ ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \ ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \ ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \ "opcode") \ ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \ "IC_64BIT_REXW_XS") \ ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \ "else because this changes most " \ "operands' meaning") \ ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") #define ENUM_ENTRY(n, r, d) n, typedef enum { INSTRUCTION_CONTEXTS IC_max } InstructionContext; #undef ENUM_ENTRY /* * Opcode types, which determine which decode table to use, both in the Intel * manual and also for the decoder. */ typedef enum { ONEBYTE = 0, TWOBYTE = 1, THREEBYTE_38 = 2, THREEBYTE_3A = 3, XOP8_MAP = 4, XOP9_MAP = 5, XOPA_MAP = 6, THREEDNOW_MAP = 7 } OpcodeType; /* * The following structs are used for the hierarchical decode table. After * determining the instruction's class (i.e., which IC_* constant applies to * it), the decoder reads the opcode. Some instructions require specific * values of the ModR/M byte, so the ModR/M byte indexes into the final table. * * If a ModR/M byte is not required, "required" is left unset, and the values * for each instructionID are identical. */ typedef uint16_t InstrUID; /* * ModRMDecisionType - describes the type of ModR/M decision, allowing the * consumer to determine the number of entries in it. * * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded * instruction is the same. * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode * corresponds to one instruction; otherwise, it corresponds to * a different instruction. * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte * divided by 8 is used to select instruction; otherwise, each * value of the ModR/M byte could correspond to a different * instruction. * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This corresponds to instructions that use reg field as opcode * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond * to a different instruction. */ #define MODRMTYPES \ ENUM_ENTRY(MODRM_ONEENTRY) \ ENUM_ENTRY(MODRM_SPLITRM) \ ENUM_ENTRY(MODRM_SPLITMISC) \ ENUM_ENTRY(MODRM_SPLITREG) \ ENUM_ENTRY(MODRM_FULL) #define ENUM_ENTRY(n) n, typedef enum { MODRMTYPES MODRM_max } ModRMDecisionType; #undef ENUM_ENTRY #define CASE_ENCODING_RM \ case ENCODING_RM: \ case ENCODING_RM_CD2: \ case ENCODING_RM_CD4: \ case ENCODING_RM_CD8: \ case ENCODING_RM_CD16: \ case ENCODING_RM_CD32: \ case ENCODING_RM_CD64 #define CASE_ENCODING_VSIB \ case ENCODING_VSIB: \ case ENCODING_VSIB_CD2: \ case ENCODING_VSIB_CD4: \ case ENCODING_VSIB_CD8: \ case ENCODING_VSIB_CD16: \ case ENCODING_VSIB_CD32: \ case ENCODING_VSIB_CD64 // Physical encodings of instruction operands. #define ENCODINGS \ ENUM_ENTRY(ENCODING_NONE, "") \ ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \ ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \ ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ ENUM_ENTRY(ENCODING_IW, "2-byte") \ ENUM_ENTRY(ENCODING_ID, "4-byte") \ ENUM_ENTRY(ENCODING_IO, "8-byte") \ ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ "the opcode byte") \ ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ "byte.") \ ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \ ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ "opcode byte") \ ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ "in type") \ ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") #define ENUM_ENTRY(n, d) n, typedef enum { ENCODINGS ENCODING_max } OperandEncoding; #undef ENUM_ENTRY /* * Semantic interpretations of instruction operands. */ #define TYPES \ ENUM_ENTRY(TYPE_NONE, "") \ ENUM_ENTRY(TYPE_REL, "immediate address") \ ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ ENUM_ENTRY(TYPE_R16, "2-byte") \ ENUM_ENTRY(TYPE_R32, "4-byte") \ ENUM_ENTRY(TYPE_R64, "8-byte") \ ENUM_ENTRY(TYPE_IMM, "immediate operand") \ ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ ENUM_ENTRY(TYPE_M, "Memory operand") \ ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ ENUM_ENTRY(TYPE_XMM, "16-byte") \ ENUM_ENTRY(TYPE_YMM, "32-byte") \ ENUM_ENTRY(TYPE_ZMM, "64-byte") \ ENUM_ENTRY(TYPE_VK, "mask register") \ ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ \ ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ ENUM_ENTRY(TYPE_DUP1, "operand 1") \ ENUM_ENTRY(TYPE_DUP2, "operand 2") \ ENUM_ENTRY(TYPE_DUP3, "operand 3") \ ENUM_ENTRY(TYPE_DUP4, "operand 4") \ #define ENUM_ENTRY(n, d) n, typedef enum { TYPES TYPE_max } OperandType; #undef ENUM_ENTRY /* * The specification for how to extract and interpret one operand. */ typedef struct OperandSpecifier { uint8_t encoding; uint8_t type; } OperandSpecifier; #define X86_MAX_OPERANDS 6 /* * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, * respectively. */ typedef enum { MODE_16BIT, MODE_32BIT, MODE_64BIT } DisassemblerMode; #endif capstone-sys-0.15.0/capstone/suite/synctools/arm64_gen_vreg.c000064400000000000000000000013760072674642500223510ustar 00000000000000// $ make arm64_gen_vreg // $ ./arm64_gen_vreg > AArch64GenRegisterV.inc #include #include #include #include #undef CAPSTONE_DIET #define GET_REGINFO_ENUM #include "AArch64GenRegisterInfo.inc" #include "AArch64GenRegisterName.inc" int main() { unsigned int i; size_t size = (size_t)getRegisterName(i, 100); printf("// size = %zu\n", size); for(i = 1; i < size; i++) { unsigned int j; const char *name = getRegisterName(i, AArch64_vreg); //printf("%u: ARM64_REG_%s, ", i, getRegisterName(i, AArch64_vreg)); if (strlen(name) == 0) { printf("0,\n"); } else { printf("ARM64_REG_"); for(j = 0; j < strlen(name); j++) { printf("%c", toupper(name[j])); } printf(",\n"); } } return 0; } capstone-sys-0.15.0/capstone/suite/synctools/asmwriter.py000075500000000000000000001007640072674642500217730ustar 00000000000000#!/usr/bin/python # convert LLVM GenAsmWriter.inc for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) arch = sys.argv[4] f = open(sys.argv[1]) lines = f.readlines() f.close() f1 = open(sys.argv[2], 'w+') f2 = open(sys.argv[3], 'w+') f1.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f1.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f1.write("\n") f2.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f2.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f2.write("\n") need_endif = False in_getRegisterName = False in_printAliasInstr = False fragment_no = None skip_printing = False skip_line = 0 skip_count = 0 def replace_getOp(line): line2 = line if 'MI->getOperand(0)' in line: line2 = line.replace('MI->getOperand(0)', 'MCInst_getOperand(MI, 0)') elif 'MI->getOperand(1)' in line: line2 = line.replace('MI->getOperand(1)', 'MCInst_getOperand(MI, 1)') elif 'MI->getOperand(2)' in line: line2 = line.replace('MI->getOperand(2)', 'MCInst_getOperand(MI, 2)') elif 'MI->getOperand(3)' in line: line2 = line.replace('MI->getOperand(3)', 'MCInst_getOperand(MI, 3)') elif 'MI->getOperand(4)' in line: line2 = line.replace('MI->getOperand(4)', 'MCInst_getOperand(MI, 4)') elif 'MI->getOperand(5)' in line: line2 = line.replace('MI->getOperand(5)', 'MCInst_getOperand(MI, 5)') elif 'MI->getOperand(6)' in line: line2 = line.replace('MI->getOperand(6)', 'MCInst_getOperand(MI, 6)') elif 'MI->getOperand(7)' in line: line2 = line.replace('MI->getOperand(7)', 'MCInst_getOperand(MI, 7)') elif 'MI->getOperand(8)' in line: line2 = line.replace('MI->getOperand(8)', 'MCInst_getOperand(MI, 8)') return line2 def replace_getReg(line): line2 = line if 'MI->getOperand(0).getReg()' in line: line2 = line.replace('MI->getOperand(0).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 0))') elif 'MI->getOperand(1).getReg()' in line: line2 = line.replace('MI->getOperand(1).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 1))') elif 'MI->getOperand(2).getReg()' in line: line2 = line.replace('MI->getOperand(2).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 2))') elif 'MI->getOperand(3).getReg()' in line: line2 = line.replace('MI->getOperand(3).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 3))') elif 'MI->getOperand(4).getReg()' in line: line2 = line.replace('MI->getOperand(4).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 4))') elif 'MI->getOperand(5).getReg()' in line: line2 = line.replace('MI->getOperand(5).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 5))') elif 'MI->getOperand(6).getReg()' in line: line2 = line.replace('MI->getOperand(6).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 6))') elif 'MI->getOperand(7).getReg()' in line: line2 = line.replace('MI->getOperand(7).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 7))') elif 'MI->getOperand(8).getReg()' in line: line2 = line.replace('MI->getOperand(8).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 8))') return line2 # extract param between text() # MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) def extract_paren(line, text): i = line.index(text) return line[line.index('(', i)+1 : line.index(')', i)] # extract text between <> # printSVERegOp<'q'> def extract_brackets(line): if '<' in line: return line[line.index('<')+1 : line.index('>')] else: return '' # delete text between <>, including <> # printSVERegOp<'q'> def del_brackets(line): if '<' in line: return line[:line.index('<')] + line[line.index('>') + 1:] else: return line def print_line(line): line = line.replace('::', '_') line = line.replace('nullptr', 'NULL') if not skip_printing: if in_getRegisterName: f2.write(line + "\n") else: f1.write(line + "\n") for line in lines: line = line.rstrip() #print("@", line) # skip Alias if arch.upper() == 'X86': if 'PRINT_ALIAS_INSTR' in line: # done break if skip_line: skip_count += 1 if skip_count <= skip_line: # skip this line continue else: # skip enough number of lines, reset counters skip_line = 0 skip_count = 0 if "::printInstruction" in line: if arch.upper() in ('AARCH64', 'ARM64'): #print_line("static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)\n{") print_line("static void printInstruction(MCInst *MI, SStream *O)\n{") else: print_line("static void printInstruction(MCInst *MI, SStream *O)\n{") elif 'const char *AArch64InstPrinter::' in line: continue elif 'getRegisterName(' in line: if 'unsigned AltIdx' in line: print_line("static const char *getRegisterName(unsigned RegNo, unsigned AltIdx)\n{") else: print_line("static const char *getRegisterName(unsigned RegNo)\n{") elif 'getRegisterName' in line: in_getRegisterName = True print_line(line) elif '::printAliasInstr' in line: if arch.upper() in ('AARCH64', 'PPC'): print_line("static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)\n{") print_line(' #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))') else: print_line("static bool printAliasInstr(MCInst *MI, SStream *OS)\n{") print_line(" unsigned int I = 0, OpIdx, PrintMethodIdx;") print_line(" char *tmpString;") in_printAliasInstr = True elif 'STI.getFeatureBits()[' in line: if arch.upper() == 'ARM': line2 = line.replace('STI.getFeatureBits()[', 'ARM_getFeatureBits(MI->csh->mode, ') elif arch.upper() == 'AARCH64': line2 = line.replace('STI.getFeatureBits()[', 'AArch64_getFeatureBits(') line2 = line2.replace(']', ')') print_line(line2) elif ', STI, ' in line: line2 = line.replace(', STI, ', ', ') if 'printSVELogicalImm<' in line: if 'int16' in line: line2 = line2.replace('printSVELogicalImm', 'printSVELogicalImm16') line2 = line2.replace('', '') elif 'int32' in line: line2 = line2.replace('printSVELogicalImm', 'printSVELogicalImm32') line2 = line2.replace('', '') else: line2 = line2.replace('printSVELogicalImm', 'printSVELogicalImm64') line2 = line2.replace('', '') if 'MI->getOperand(' in line: line2 = replace_getOp(line2) # C++ template if 'printPrefetchOp' in line2: param = extract_brackets(line2) if param == '': param = 'false' line2 = del_brackets(line2) line2 = line2.replace(', O);', ', O, %s);' %param) line2 = line2.replace(', OS);', ', OS, %s);' %param) elif '' in line2: line2 = line2.replace('', '') line2 = line2.replace(', O);', ', O, false);') line2 = line2.replace('STI, ', '') elif '' in line: line2 = line2.replace('', '') line2 = line2.replace(', O);', ', O, true);') line2 = line2.replace('STI, ', '') elif 'printAdrLabelOperand' in line: # C++ template if '<0>' in line: line2 = line2.replace('<0>', '') line2 = line2.replace(', O);', ', O, 0);') elif '<1>' in line: line2 = line2.replace('<1>', '') line2 = line2.replace(', O);', ', O, 1);') elif '<2>' in line: line2 = line2.replace('<2>', '') line2 = line2.replace(', O);', ', O, 2);') elif 'printImm8OptLsl' in line2: param = extract_brackets(line2) line2 = del_brackets(line2) if '8' in param or '16' in param or '32' in param: line2 = line2.replace('printImm8OptLsl', 'printImm8OptLsl32') elif '64' in param: line2 = line2.replace('printImm8OptLsl', 'printImm8OptLsl64') elif 'printLogicalImm' in line2: param = extract_brackets(line2) line2 = del_brackets(line2) if '8' in param or '16' in param or '32' in param: line2 = line2.replace('printLogicalImm', 'printLogicalImm32') elif '64' in param: line2 = line2.replace('printLogicalImm', 'printLogicalImm64') elif 'printSVERegOp' in line2 or 'printGPRSeqPairsClassOperand' in line2 or 'printTypedVectorList' in line2 or 'printPostIncOperand' in line2 or 'printImmScale' in line2 or 'printRegWithShiftExtend' in line2 or 'printUImm12Offset' in line2 or 'printExactFPImm' in line2 or 'printMemExtend' in line2 or 'printZPRasFPR' in line2: param = extract_brackets(line2) if param == '': param = '0' line2 = del_brackets(line2) line2 = line2.replace(', O);', ', O, %s);' %param) line2 = line2.replace(', OS);', ', OS, %s);' %param) elif 'printComplexRotationOp' in line: # printComplexRotationOp<90, 0>(MI, 5, STI, O); bracket_content = line2[line2.index('<') + 1 : line2.index('>')] line2 = line2.replace('<' + bracket_content + '>', '') line2 = line2.replace(' O);', ' O, %s);' %bracket_content) print_line(line2) elif "static const char AsmStrs[]" in line: print_line("#ifndef CAPSTONE_DIET") print_line(" static const char AsmStrs[] = {") need_endif = True elif "static const char AsmStrsNoRegAltName[]" in line: print_line("#ifndef CAPSTONE_DIET") print_line(" static const char AsmStrsNoRegAltName[] = {") need_endif = True elif line == ' O << "\\t";': print_line(" unsigned int opcode = MCInst_getOpcode(MI);") print_line(' // printf("opcode = %u\\n", opcode);'); elif 'MI->getOpcode()' in line: if 'switch' in line: line2 = line.replace('MI->getOpcode()', 'MCInst_getOpcode(MI)') else: line2 = line.replace('MI->getOpcode()', 'opcode') print_line(line2) elif 'O << ' in line: if '"' in line: line2 = line.lower() line2 = line2.replace('o << ', 'SStream_concat0(O, '); else: line2 = line.replace('O << ', 'SStream_concat0(O, '); line2 = line2.replace("'", '"') line2 = line2.replace(';', ');') if '" : "' in line2: # "segment : offset" in X86 line2 = line2.replace('" : "', '":"') # ARM print_line(line2) if '", #0"' in line2: print_line(' op_addImm(MI, 0);') if '", #1"' in line2: print_line(' op_addImm(MI, 1);') # PowerPC if '", 268"' in line2: print_line(' op_addImm(MI, 268);') elif '", 256"' in line2: print_line(' op_addImm(MI, 256);') elif '", 0, "' in line2 or '", 0"' in line2: print_line(' op_addImm(MI, 0);') elif '", -1"' in line2: print_line(' op_addImm(MI, -1);') if '[' in line2: if not '[]' in line2: print_line(' set_mem_access(MI, true);') if ']' in line2: if not '[]' in line2: print_line(' set_mem_access(MI, false);') if '".f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64);') elif '".f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32);') elif '".f16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16);') elif '".s64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S64);') elif '".s32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S32);') elif '".s16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S16);') elif '".s8\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S8);') elif '".u64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U64);') elif '".u32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32);') elif '".u16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16);') elif '".u8\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U8);') elif '".i64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I64);') elif '".i32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I32);') elif '".i16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I16);') elif '".i8\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I8);') elif '".f16.f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64);') elif '".f64.f16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16);') elif '".f16.f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32);') elif '".f32.f16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16);') elif '".f64.f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32);') elif '".f32.f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64);') elif '".s32.f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32);') elif '".f32.s32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32);') elif '".u32.f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32);') elif '".f32.u32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32);') elif '".p8\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_P8);') elif '".f64.s16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16);') elif '".s16.f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64);') elif '".f32.s16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16);') elif '".s16.f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32);') elif '".f64.s32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32);') elif '".s32.f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64);') elif '".f64.u16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16);') elif '".u16.f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64);') elif '".f32.u16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16);') elif '".u16.f32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32);') elif '".f64.u32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32);') elif '".u32.f64\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64);') elif '".f16.u32\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U32);') elif '".u32.f16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F16);') elif '".f16.u16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U16);') elif '".u16.f16\\t"' in line2: print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F16);') elif '"\\tlr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_LR);') elif '"\\tapsr_nzcv, fpscr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_APSR_NZCV);') print_line(' ARM_addReg(MI, ARM_REG_FPSCR);') elif '"\\tpc, lr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_PC);') print_line(' ARM_addReg(MI, ARM_REG_LR);') elif '"\\tfpscr, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPSCR);') elif '"\\tfpexc, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPEXC);') elif '"\\tfpinst, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPINST);') elif '"\\tfpinst2, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPINST2);') elif '"\\tfpsid, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPSID);') elif '"\\tsp, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_SP);') elif '"\\tsp!, "' in line2: print_line(' ARM_addReg(MI, ARM_REG_SP);') elif '", apsr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_APSR);') elif '", spsr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_SPSR);') elif '", fpscr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPSCR);') elif '", fpscr"' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPSCR);') elif '", fpexc"' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPEXC);') elif '", fpinst"' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPINST);') elif '", fpinst2"' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPINST2);') elif '", fpsid"' in line2: print_line(' ARM_addReg(MI, ARM_REG_FPSID);') elif '", mvfr0"' in line2: print_line(' ARM_addReg(MI, ARM_REG_MVFR0);') elif '", mvfr1"' in line2: print_line(' ARM_addReg(MI, ARM_REG_MVFR1);') elif '", mvfr2"' in line2: print_line(' ARM_addReg(MI, ARM_REG_MVFR2);') elif '.8\\t' in line2: print_line(' ARM_addVectorDataSize(MI, 8);') elif '.16\\t' in line2: print_line(' ARM_addVectorDataSize(MI, 16);') elif '.32\\t' in line2: print_line(' ARM_addVectorDataSize(MI, 32);') elif '.64\\t' in line2: print_line(' ARM_addVectorDataSize(MI, 64);') elif '" ^"' in line2: print_line(' ARM_addUserMode(MI);') if '.16b' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);') elif '.8b' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);') elif '.4b' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4B);') elif '.b' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B);') elif '.8h' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);') elif '.4h' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);') elif '.2h' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H);') elif '.h' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H);') elif '.4s' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);') elif '.2s' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);') elif '.s' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);') elif '.2d' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);') elif '.1d' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);') elif '.1q' in line2: print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q);') if '#0.0' in line2: print_line(' arm64_op_addFP(MI, 0);') elif '#0' in line2: print_line(' arm64_op_addImm(MI, 0);') elif '#8' in line2: print_line(' arm64_op_addImm(MI, 8);') elif '#16' in line2: print_line(' arm64_op_addImm(MI, 16);') elif '#32' in line2: print_line(' arm64_op_addImm(MI, 32);') # X86 if '", %rax"' in line2 or '", rax"' in line2: print_line(' op_addReg(MI, X86_REG_RAX);') elif '", %eax"' in line2 or '", eax"' in line2: print_line(' op_addReg(MI, X86_REG_EAX);') elif '", %ax"' in line2 or '", ax"' in line2: print_line(' op_addReg(MI, X86_REG_AX);') elif '", %al"' in line2 or '", al"' in line2: print_line(' op_addReg(MI, X86_REG_AL);') elif '", %dx"' in line2 or '", dx"' in line2: print_line(' op_addReg(MI, X86_REG_DX);') elif '", %st(0)"' in line2 or '", st(0)"' in line2: print_line(' op_addReg(MI, X86_REG_ST0);') elif '", 1"' in line2: print_line(' op_addImm(MI, 1);') elif '", cl"' in line2: print_line(' op_addReg(MI, X86_REG_CL);') elif '"{1to2}, "' in line2: print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_2);') elif '"{1to4}, "' in line2: print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_4);') elif '"{1to8}, "' in line2: print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_8);') elif '"{1to16}, "' in line2: print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_16);') elif '{z}{sae}' in line2: print_line(' op_addAvxSae(MI);') print_line(' op_addAvxZeroOpmask(MI);') elif ('{z}' in line2): print_line(' op_addAvxZeroOpmask(MI);') elif '{sae}' in line2: print_line(' op_addAvxSae(MI);') elif 'llvm_unreachable("Invalid command number.");' in line: line2 = line.replace('llvm_unreachable("Invalid command number.");', '// unreachable') print_line(line2) elif ('assert(' in line) or ('assert (' in line): pass elif 'Invalid alt name index' in line: pass elif '::' in line and 'case ' in line: #print_line(line2) print_line(line) elif 'MI->getNumOperands()' in line: line2 = line.replace('MI->getNumOperands()', 'MCInst_getNumOperands(MI)') print_line(line2) elif 'const MCOperand &MCOp' in line: line2 = line.replace('const MCOperand &MCOp', 'MCOperand *MCOp') print_line(line2) elif 'MI->getOperand(0).isImm()' in line: line2 = line.replace('MI->getOperand(0).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 0))') print_line(line2) elif 'MI->getOperand(1).isImm()' in line: line2 = line.replace('MI->getOperand(1).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 1))') print_line(line2) elif 'MI->getOperand(2).isImm()' in line: line2 = line.replace('MI->getOperand(2).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 2))') print_line(line2) elif 'MI->getOperand(3).isImm()' in line: line2 = line.replace('MI->getOperand(3).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 3))') print_line(line2) elif 'MI->getOperand(4).isImm()' in line: line2 = line.replace('MI->getOperand(4).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 4))') print_line(line2) elif 'MI->getOperand(5).isImm()' in line: line2 = line.replace('MI->getOperand(5).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 5))') print_line(line2) elif 'MI->getOperand(6).isImm()' in line: line2 = line.replace('MI->getOperand(6).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 6))') print_line(line2) elif 'MI->getOperand(7).isImm()' in line: line2 = line.replace('MI->getOperand(7).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 7))') print_line(line2) elif 'MI->getOperand(8).isImm()' in line: line2 = line.replace('MI->getOperand(8).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 8))') print_line(line2) elif 'MI->getOperand(0).getImm()' in line: line2 = line.replace('MI->getOperand(0).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 0))') print_line(line2) elif 'MI->getOperand(1).getImm()' in line: line2 = line.replace('MI->getOperand(1).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 1))') print_line(line2) elif 'MI->getOperand(2).getImm()' in line: line2 = line.replace('MI->getOperand(2).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 2))') print_line(line2) elif 'MI->getOperand(3).getImm()' in line: line2 = line.replace('MI->getOperand(3).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 3))') print_line(line2) elif 'MI->getOperand(4).getImm()' in line: line2 = line.replace('MI->getOperand(4).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 4))') print_line(line2) elif 'MI->getOperand(5).getImm()' in line: line2 = line.replace('MI->getOperand(5).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 5))') print_line(line2) elif 'MI->getOperand(6).getImm()' in line: line2 = line.replace('MI->getOperand(6).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 6))') print_line(line2) elif 'MI->getOperand(7).getImm()' in line: line2 = line.replace('MI->getOperand(7).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 7))') print_line(line2) elif 'MI->getOperand(8).getImm()' in line: line2 = line.replace('MI->getOperand(8).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 8))') print_line(line2) elif 'MRI.getRegClass(' in line: classid = extract_paren(line, 'getRegClass(') operand = extract_paren(line, 'getOperand') line2 = line.replace('MI->getNumOperands()', 'MCInst_getNumOperands(MI)') line2 = ' GETREGCLASS_CONTAIN(%s, %s)' %(classid, operand) if line.endswith('())) {'): line2 += ') {' elif line.endswith(' {'): line2 += ' {' elif line.endswith(' &&'): line2 += ' &&' print_line(line2) elif 'MI->getOperand(' in line and 'isReg' in line: operand = extract_paren(line, 'getOperand') line2 = ' MCOperand_isReg(MCInst_getOperand(MI, %s))' %(operand) # MI->getOperand(1).isReg() && if line.endswith(' {'): line2 += ' {' elif line.endswith(' &&'): line2 += ' &&' print_line(line2) elif 'MI->getOperand(' in line and 'getReg' in line: line2 = replace_getReg(line) # one more time line2 = replace_getReg(line2) print_line(line2) elif ' return false;' in line and in_printAliasInstr: print_line(' return NULL;') elif 'MCOp.isImm()' in line: line2 = line.replace('MCOp.isImm()', 'MCOperand_isImm(MCOp)') print_line(line2) elif 'MCOp.getImm()' in line: line2 = line.replace('MCOp.getImm()', 'MCOperand_getImm(MCOp)') if 'int64_t Val =' in line: line2 = line2.replace('int64_t Val =', 'Val =') print_line(line2) elif 'isSVEMaskOfIdenticalElements<' in line: if 'int8' in line: line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements8') line2 = line2.replace('', '') elif 'int16' in line: line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements16') line2 = line2.replace('', '') elif 'int32' in line: line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements32') line2 = line2.replace('', '') else: line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements64') line2 = line2.replace('', '') print_line(line2) elif 'switch (PredicateIndex) {' in line: print_line(' int64_t Val;') print_line(line) elif 'unsigned I = 0;' in line and in_printAliasInstr: print_line(""" tmpString = cs_strdup(AsmString); while (AsmString[I] != ' ' && AsmString[I] != '\\t' && AsmString[I] != '$' && AsmString[I] != '\\0') ++I; tmpString[I] = 0; SStream_concat0(OS, tmpString); if (AsmString[I] != '\\0') { if (AsmString[I] == ' ' || AsmString[I] == '\\t') { SStream_concat0(OS, " "); ++I; } do { if (AsmString[I] == '$') { ++I; if (AsmString[I] == (char)0xff) { ++I; OpIdx = AsmString[I++] - 1; PrintMethodIdx = AsmString[I++] - 1; printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); } else printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); } else { SStream_concat1(OS, AsmString[I++]); } } while (AsmString[I] != '\\0'); } return tmpString; } """) in_printAliasInstr = False # skip next few lines skip_printing = True elif '::printCustomAliasOperand' in line: # print again skip_printing = False print_line('static void printCustomAliasOperand(') elif 'const MCSubtargetInfo &STI' in line: pass elif 'const MCInst *MI' in line: line2 = line.replace('const MCInst *MI', 'MCInst *MI') print_line(line2) elif 'llvm_unreachable("' in line: if 'default: ' in line: print_line(' default:') elif 'llvm_unreachable("Unknown MCOperandPredicate kind")' in line: print_line(' return false; // never reach') else: pass elif 'raw_ostream &' in line: line2 = line.replace('raw_ostream &', 'SStream *') if line2.endswith(' {'): line2 = line2.replace(' {', '\n{') print_line(line2) elif 'printPredicateOperand(' in line and 'STI, ' in line: line2 = line.replace('STI, ', '') print_line(line2) elif '// Fragment ' in line: # // Fragment 0 encoded into 6 bits for 51 unique commands. tmp = line.strip().split(' ') fragment_no = tmp[2] print_line(line) elif ('switch ((' in line or 'if ((' in line) and 'Bits' in line: # switch ((Bits >> 14) & 63) { bits = line.strip() bits = bits.replace('switch ', '') bits = bits.replace('if ', '') bits = bits.replace('{', '') bits = bits.strip() print_line(' // printf("Fragment %s: %%"PRIu64"\\n", %s);' %(fragment_no, bits)) print_line(line) elif not skip_printing: print_line(line) if line == ' };': if need_endif and not in_getRegisterName: # endif only for AsmStrs when we are not inside getRegisterName() print_line("#endif") need_endif = False elif 'return AsmStrs+RegAsmOffset[RegNo-1];' in line: if in_getRegisterName: # return NULL for register name on Diet mode print_line("#else") print_line(" return NULL;") print_line("#endif") print_line("}") need_endif = False in_getRegisterName = False # skip 1 line skip_line = 1 elif line == ' }': # ARM64 if in_getRegisterName: # return NULL for register name on Diet mode print_line("#else") print_line(" return NULL;") print_line("#endif") print_line("}") need_endif = False in_getRegisterName = False # skip 1 line skip_line = 1 elif 'default:' in line: # ARM64 if in_getRegisterName: # get the size of RegAsmOffsetvreg[] print_line(" return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0]));") f1.close() f2.close() capstone-sys-0.15.0/capstone/suite/synctools/compare_mapping_insn.py000075500000000000000000000015030072674642500241350ustar 00000000000000#!/usr/bin/python # compare instructions in 2 files of MappingInsn.inc # find instructions in MappingInsn1, that does not exist in MappingInsn2 # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) mapping1 = f.readlines() f.close() f = open(sys.argv[2]) mapping2 = f.readlines() f.close() insn1 = [] for line in mapping1: if 'X86_INS_' in line: tmp = line.split(',') insn_id = tmp[0].strip() insn1.append(insn_id) insn2 = [] for line in mapping2: if 'X86_INS_' in line: tmp = line.split(',') insn_id = tmp[0].strip() insn2.append(insn_id) for insn_id in insn1: if not insn_id in insn2: print("instruction %s is not in list 2" %insn_id) capstone-sys-0.15.0/capstone/suite/synctools/disassemblertables-arch.py000075500000000000000000000212720072674642500245350ustar 00000000000000#!/usr/bin/python # convert LLVM GenDisassemblerTables.inc for Capstone disassembler. # this just adds a header # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() print("/* Capstone Disassembly Engine, http://www.capstone-engine.org */") print("/* By Nguyen Anh Quynh , 2013-2019 */") print("/* Automatically generated file, do not edit! */\n") print('#include "../../MCInst.h"') print('#include "../../LEB128.h"') print("") print(""" // Helper function for extracting fields from encoded instructions. //#if defined(_MSC_VER) && !defined(__clang__) //__declspec(noinline) //#endif #define FieldFromInstruction(fname, InsnType) \\ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \\ { \\ InsnType fieldMask; \\ if (numBits == sizeof(InsnType) * 8) \\ fieldMask = (InsnType)(-1LL); \\ else \\ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \\ return (insn & fieldMask) >> startBit; \\ } """) # extract text between <> # printSVERegOp<'q'> def extract_brackets(line): return line[line.index('<')+1 : line.index('>')] # delete text between <>, including <> # printSVERegOp<'q'> def del_brackets(line): return line[:line.index('<')] + line[line.index('>') + 1:] # skip printing some lines? skip_print = True # adding slash at the end of the line for C macro? adding_slash = False # skip LLVM_DEBUG llvm_debug = False def print_line(line): if skip_print is True: return if adding_slash: # skip blank line if (len(line.strip()) == 0): return # // must be handled if '//' in line: line = line.replace('//', '/*') line += ' */' print(line + ' \\') else: print(line) for line in lines: line2 = line.rstrip() if '#include ' in line2: continue # skip until the first decoder table elif skip_print and 'static const uint8_t DecoderTable' in line2: skip_print = False elif 'End llvm namespace' in line2: # done break elif 'llvm_unreachable' in line2: line2 = line2.replace('llvm_unreachable', '/* llvm_unreachable') line2 += '*/ ' if '"Invalid index!"' in line2: pass #line2 += '\n return true;' elif 'Bits[' in line2: if sys.argv[2] == 'ARM': line2 = line2.replace('Bits[', 'ARM_getFeatureBits(MI->csh->mode, ') line2 = line2.replace(']', ')') elif sys.argv[2] == 'AArch64': line2 = line2.replace('Bits[', 'AArch64_getFeatureBits(') line2 = line2.replace(']', ')') elif 'static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset& Bits) {' in line2: line2 = 'static bool checkDecoderPredicate(unsigned Idx, MCInst *MI)\n{' elif 'checkDecoderPredicate(PIdx, ' in line2: line2 = line2.replace(', Bits)', ', MI)') elif 'template' in line2: continue elif 'static DecodeStatus decodeToMCInst' in line2: line2 = '#define DecodeToMCInst(fname, fieldname, InsnType) \\\n' + \ 'static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \\\n' + \ '\t\tuint64_t Address, bool *Decoder) \\\n{' adding_slash = True elif 'fieldFromInstruction' in line2: line2 = line2.replace('fieldFromInstruction', 'fieldname') if 'InsnType FieldValue' in line2: line2 = line2.replace('InsnType ', '') elif 'DecodeComplete = true;' in line2: # dead code continue elif 'bool &DecodeComplete) {' in line2: continue elif line2 == '}': if adding_slash: adding_slash = False elif 'static DecodeStatus decodeInstruction' in line2: line2 = '#define DecodeInstruction(fname, fieldname, decoder, InsnType) \\\n' + \ 'static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \\\n' + \ '\t\tInsnType insn, uint64_t Address) \\\n{ \\\n' + \ ' unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \\\n' + \ ' InsnType Val, FieldValue, PositiveMask, NegativeMask; \\\n' + \ ' bool Pred, Fail, DecodeComplete = true; \\\n' + \ ' uint32_t ExpectedValue;' adding_slash = True print_line(line2) # skip printing few lines skip_print = True elif 'const MCSubtargetInfo &STI' in line2: skip_print = False # skip this line continue elif 'Bits = STI.getFeatureBits()' in line2: # skip this line continue elif 'errs() << ' in line2: continue elif 'unsigned Start =' in line2: line2 = line2.replace('unsigned ', '') elif 'unsigned Len =' in line2: line2 = line2.replace('unsigned ', '') elif 'unsigned Len;' in line2: continue elif 'MCInst TmpMI;' in line2: continue elif 'bool Pred;' in line2: continue elif 'bool DecodeComplete;' in line2: continue elif 'unsigned NumToSkip =' in line2: line2 = line2.replace('unsigned ', '') elif 'unsigned PIdx =' in line2: line2 = line2.replace('unsigned ', '') elif 'unsigned Opc =' in line2: line2 = line2.replace('unsigned ', '') elif 'unsigned DecodeIdx =' in line2: line2 = line2.replace('unsigned ', '') elif 'InsnType Val =' in line2: line2 = line2.replace('InsnType ', '') elif 'bool Fail' in line2: line2 = line2.replace('bool ', '') elif 'InsnType PositiveMask =' in line2: line2 = line2.replace('InsnType ', '') elif 'InsnType NegativeMask =' in line2: line2 = line2.replace('InsnType ', '') elif 'uint32_t ExpectedValue' in line2: line2 = line2.replace('uint32_t ', '') elif 'ptrdiff_t Loc = ' in line2: continue elif 'LLVM_DEBUG(' in line2: # just this line? if ');' in line2: continue skip_print = True llvm_debug = True continue elif skip_print and llvm_debug and ');' in line2: llvm_debug = False skip_print = False continue elif 'decodeToMCInst(' in line2: line2 = line2.replace('decodeToMCInst', 'decoder') line2 = line2.replace('DecodeComplete);', '&DecodeComplete);') line2 = line2.replace(', DisAsm', '') line2 = line2.replace(', TmpMI', ', MI') elif 'TmpMI.setOpcode(Opc);' in line2: line2 = ' MCInst_setOpcode(MI, Opc);' elif 'MI.setOpcode(Opc);' in line2: line2 = ' MCInst_setOpcode(MI, Opc);' elif 'MI.clear();' in line2: line2 = ' MCInst_clear(MI);' elif 'assert(' in line2: line2 = line2.replace('assert(', '/* assert(') line2 += ' */' elif 'Check(S, ' in line2: line2 = line2.replace('Check(S, ', 'Check(&S, ') if 'DecodeImm8OptLsl<' in line2: param = extract_brackets(line2) line2 = del_brackets(line2) line2 = line2.replace(', Decoder)', ', Decoder, %s)' %param) elif 'DecodeSImm<' in line2: param = extract_brackets(line2) line2 = del_brackets(line2) line2 = line2.replace(', Decoder)', ', Decoder, %s)' %param) if 'DecodeComplete = false; ' in line2: line2 = line2.replace('DecodeComplete = false; ', '') elif 'decodeUImmOperand<' in line2 or 'decodeSImmOperand<' in line2 : # decodeUImmOperand<5>(MI, tmp, Address, Decoder) param = extract_brackets(line2) line2 = del_brackets(line2) line2 = line2.replace(', Decoder)', ', Decoder, %s)' %param) elif 'MI.addOperand(MCOperand::createImm(tmp));' in line2: line2 = ' MCOperand_CreateImm0(MI, tmp);' elif 'MI = TmpMI;' in line2: line2 = '' #line2 = line2.replace('TmpMI', '&TmpMI') line2 = line2.replace('::', '_') print_line(line2) if sys.argv[2] == 'ARM': print(""" FieldFromInstruction(fieldFromInstruction_2, uint16_t) DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) """) if sys.argv[2] in ('AArch64', 'PPC'): print(""" FieldFromInstruction(fieldFromInstruction_4, uint32_t) DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) """) capstone-sys-0.15.0/capstone/suite/synctools/disassemblertables.py000075500000000000000000000023160072674642500236200ustar 00000000000000#!/usr/bin/python # convert LLVM GenDisassemblerTables.inc for Capstone disassembler. # for X86, this separate ContextDecision tables into another file # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() f1 = open(sys.argv[2], 'w+') f2 = open(sys.argv[3], 'w+') f1.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f1.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f1.write("\n") f2.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f2.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f2.write("\n") # static const struct ContextDecision x86DisassemblerOneByteOpcodes = { # static const struct ContextDecision x86DisassemblerXOP8Opcodes = { write_to_f2 = False for line in lines: if 'ContextDecision x86DisassemblerOneByteOpcodes = {' in line: # done with f1, start writing to f2 write_to_f2 = True if write_to_f2: f2.write(line) else: f1.write(line) f1.close() f2.close() capstone-sys-0.15.0/capstone/suite/synctools/disassemblertables2.c000064400000000000000000000125400072674642500234710ustar 00000000000000/* Capstone Disassembly Engine */ /* By Nguyen Anh Quynh , 2013-2019 */ // this tool is to generate arch/X86/X86GenDisassemblerTables2.inc // NOTE: this requires updated X86GenDisassemblerTables2 & X86GenDisassemblerTables2 // generatedy by ./disassemblertables.py & disassemblertables_reduce.py #include #include #include // X86DisassemblerDecoderCommon.h is copied from Capstone src #include "../../arch/X86/X86DisassemblerDecoderCommon.h" #define ARR_SIZE(a) (sizeof(a) / sizeof(a[0])) /// Specifies whether a ModR/M byte is needed and (if so) which /// instruction each possible value of the ModR/M byte corresponds to. Once /// this information is known, we have narrowed down to a single instruction. struct ModRMDecision { uint8_t modrm_type; uint16_t instructionIDs; }; /// Specifies which set of ModR/M->instruction tables to look at /// given a particular opcode. struct OpcodeDecision { struct ModRMDecision modRMDecisions[256]; }; /// Specifies which opcode->instruction tables to look at given /// a particular context (set of attributes). Since there are many possible /// contexts, the decoder first uses CONTEXTS_SYM to determine which context /// applies given a specific set of attributes. Hence there are only IC_max /// entries in this table, rather than 2^(ATTR_max). struct ContextDecision { struct OpcodeDecision opcodeDecisions[IC_max]; }; #ifdef CAPSTONE_X86_REDUCE #include "X86GenDisassemblerTables_reduce2.inc" #else #include "X86GenDisassemblerTables2.inc" #endif static void index_OpcodeDecision(const struct OpcodeDecision *decisions, size_t size, const struct OpcodeDecision *emptyDecision, unsigned int *index_table, const char *opcodeTable, const char *index_opcodeTable) { unsigned int i, count = 0; for (i = 0; i < size; i++) { if (memcmp((const void *)&decisions[i], emptyDecision, sizeof(*emptyDecision)) != 0) { // this is a non-zero entry // index_table entry must be != 0 index_table[i] = count + 1; count++; } else // empty entry index_table[i] = 0; } printf("static const unsigned char %s[] = {\n", index_opcodeTable); for (i = 0; i < size; i++) { printf(" %u,\n", index_table[i]); } printf("};\n\n"); printf("static const struct OpcodeDecision %s[] = {\n", opcodeTable); for (i = 0; i < size; i++) { if (index_table[i]) { unsigned int j; const struct OpcodeDecision *decision; // print out this non-zero entry printf(" { {\n"); decision = &decisions[i]; for(j = 0; j < ARR_SIZE(emptyDecision->modRMDecisions); j++) { const char *modrm; switch(decision->modRMDecisions[j].modrm_type) { default: modrm = "MODRM_ONEENTRY"; break; case 1: modrm = "MODRM_SPLITRM"; break; case 2: modrm = "MODRM_SPLITMISC"; break; case 3: modrm = "MODRM_SPLITREG"; break; case 4: modrm = "MODRM_FULL"; break; } printf(" { %s, %u },\n", modrm, decision->modRMDecisions[j].instructionIDs); } printf(" } },\n"); } } printf("};\n\n"); } int main(int argc, char **argv) { unsigned int index_table[ARR_SIZE(x86DisassemblerOneByteOpcodes.opcodeDecisions)]; const struct OpcodeDecision emptyDecision; memset((void *)&emptyDecision, 0, sizeof(emptyDecision)); printf("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n"); printf("/* By Nguyen Anh Quynh , 2013-2019 */\n"); printf("\n"); index_OpcodeDecision(x86DisassemblerOneByteOpcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerOneByteOpcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerOneByteOpcodes", "index_x86DisassemblerOneByteOpcodes"); index_OpcodeDecision(x86DisassemblerTwoByteOpcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerTwoByteOpcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerTwoByteOpcodes", "index_x86DisassemblerTwoByteOpcodes"); index_OpcodeDecision(x86DisassemblerThreeByte38Opcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerThreeByte38Opcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerThreeByte38Opcodes", "index_x86DisassemblerThreeByte38Opcodes"); index_OpcodeDecision(x86DisassemblerThreeByte3AOpcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerThreeByte3AOpcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerThreeByte3AOpcodes", "index_x86DisassemblerThreeByte3AOpcodes"); #ifndef CAPSTONE_X86_REDUCE index_OpcodeDecision(x86DisassemblerXOP8Opcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerXOP8Opcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerXOP8Opcodes", "index_x86DisassemblerXOP8Opcodes"); index_OpcodeDecision(x86DisassemblerXOP9Opcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerXOP9Opcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerXOP9Opcodes", "index_x86DisassemblerXOP9Opcodes"); index_OpcodeDecision(x86DisassemblerXOPAOpcodes.opcodeDecisions, ARR_SIZE(x86DisassemblerXOPAOpcodes.opcodeDecisions), &emptyDecision, index_table, "x86DisassemblerXOPAOpcodes", "index_x86DisassemblerXOPAOpcodes"); index_OpcodeDecision(x86Disassembler3DNowOpcodes.opcodeDecisions, ARR_SIZE(x86Disassembler3DNowOpcodes.opcodeDecisions), &emptyDecision, index_table, "x86Disassembler3DNowOpcodes", "index_x86Disassembler3DNowOpcodes"); #endif return 0; } capstone-sys-0.15.0/capstone/suite/synctools/disassemblertables_reduce.py000075500000000000000000000024560072674642500251540ustar 00000000000000#!/usr/bin/python # convert LLVM GenDisassemblerTables.inc for Capstone disassembler. # this just adds a header # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() f1 = open(sys.argv[2], 'w+') f2 = open(sys.argv[3], 'w+') f1.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f1.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f1.write("\n") f2.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f2.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f2.write("\n") # static const struct ContextDecision x86DisassemblerOneByteOpcodes = { # static const struct ContextDecision x86DisassemblerXOP8Opcodes = { write_to_f2 = False for line in lines: # ignore all tables from XOP onwards if 'ContextDecision x86DisassemblerXOP8Opcodes = {' in line: # done break if 'ContextDecision x86DisassemblerOneByteOpcodes = {' in line: # done with f1, start writing to f2 write_to_f2 = True if write_to_f2: f2.write(line) else: f1.write(line) f1.close() f2.close() capstone-sys-0.15.0/capstone/suite/synctools/genall-arch.sh000075500000000000000000000065040072674642500221120ustar 00000000000000#!/bin/sh # generate all ARCH*.inc files for Capstone, by Nguyen Anh Quynh # Syntax: genall-arch.sh # ./genall-arch.sh tablegen ~/projects/capstone.git/arch/ARM ARM # ./genall-arch.sh tablegen ~/projects/capstone.git/arch/ARM AArch64 # ./genall-arch.sh tablegen ~/projects/capstone.git/arch/ARM PowerPC ARCH=$3 echo "Generating ${ARCH}GenAsmWriter.inc" ./asmwriter.py $1/${ARCH}GenAsmWriter.inc ${ARCH}GenAsmWriter.inc ${ARCH}GenRegisterName.inc ${ARCH} echo "Generating ${ARCH}MappingInsnName.inc" ./mapping_insn_name-arch.py $1/${ARCH}GenAsmMatcher.inc > ${ARCH}MappingInsnName.inc #./mapping_insn_name-arch.py tablegen/ARMGenAsmMatcher.inc echo "Generating ${ARCH}MappingInsn.inc" ./mapping_insn-arch.py $1/${ARCH}GenAsmMatcher.inc $1/${ARCH}GenInstrInfo.inc $2/${ARCH}MappingInsn.inc > ${ARCH}MappingInsn.inc echo "Generating ${ARCH}GenInstrInfo.inc" ./instrinfo-arch.py $1/${ARCH}GenInstrInfo.inc ${ARCH} > ${ARCH}GenInstrInfo.inc echo "Generating ${ARCH}GenDisassemblerTables.inc" ./disassemblertables-arch.py $1/${ARCH}GenDisassemblerTables.inc ${ARCH} > ${ARCH}GenDisassemblerTables.inc echo "Generating ${ARCH}GenRegisterInfo.inc" ./registerinfo.py $1/${ARCH}GenRegisterInfo.inc ${ARCH} > ${ARCH}GenRegisterInfo.inc echo "Generating ${ARCH}GenSubtargetInfo.inc" ./subtargetinfo.py $1/${ARCH}GenSubtargetInfo.inc ${ARCH} > ${ARCH}GenSubtargetInfo.inc case $3 in ARM) # for ARM only echo "Generating ${ARCH}GenAsmWriter-digit.inc" ./asmwriter.py $1/${ARCH}GenAsmWriter-digit.inc ${ARCH}GenAsmWriter.inc ${ARCH}GenRegisterName_digit.inc ${ARCH} echo "Generating ${ARCH}GenSystemRegister.inc" ./systemregister.py $1/${ARCH}GenSystemRegister.inc > ${ARCH}GenSystemRegister.inc echo "Generating instruction enum in insn_list.txt (for include/capstone/.h)" ./insn.py $1/${ARCH}GenAsmMatcher.inc $1/${ARCH}GenInstrInfo.inc $2/${ARCH}MappingInsn.inc > insn_list.txt # then copy these instructions to include/capstone/.h echo "Generating ${ARCH}MappingInsnOp.inc" ./mapping_insn_op-arch.py $1/${ARCH}GenAsmMatcher.inc $1/${ARCH}GenInstrInfo.inc $2/${ARCH}MappingInsnOp.inc > ${ARCH}MappingInsnOp.inc echo "Generating ${ARCH}GenSystemRegister.inc" ./systemregister.py $1/${ARCH}GenSystemRegister.inc > ${ARCH}GenSystemRegister.inc ;; AArch64) echo "Generating ${ARCH}GenSystemOperands.inc" ./systemoperand.py tablegen/AArch64GenSystemOperands.inc AArch64GenSystemOperands.inc AArch64GenSystemOperands_enum.inc echo "Generating instruction enum in insn_list.txt (for include/capstone/.h)" ./insn.py $1/${ARCH}GenAsmMatcher.inc $1/${ARCH}GenInstrInfo.inc $2/${ARCH}MappingInsn.inc > insn_list.txt # then copy these instructions to include/capstone/.h ./arm64_gen_vreg > AArch64GenRegisterV.inc echo "Generating ${ARCH}MappingInsnOp.inc" ./mapping_insn_op-arch.py $1/${ARCH}GenAsmMatcher.inc $1/${ARCH}GenInstrInfo.inc $2/${ARCH}MappingInsnOp.inc > ${ARCH}MappingInsnOp.inc make arm64 ;; PowerPC) # PowerPC ./insn3.py $1/${ARCH}GenAsmMatcher.inc > insn_list.txt # then copy these instructions to include/capstone/arch.h ;; *) echo "Generating instruction enum in insn_list.txt (for include/capstone/.h)" ./insn.py $1/${ARCH}GenAsmMatcher.inc $1/${ARCH}GenInstrInfo.inc $2/${ARCH}MappingInsn.inc > insn_list.txt ;; esac capstone-sys-0.15.0/capstone/suite/synctools/genall-full.sh000075500000000000000000000027070072674642500221400ustar 00000000000000#!/bin/sh # generate all X86*.inc files for Capstone, by Nguyen Anh Quynh # Syntax: genall.sh # ./genall-full.sh tablegen ~/projects/capstone.git/arch/X86 echo "Generating GenAsmWriter.inc" ./asmwriter.py $1/X86GenAsmWriter.inc X86GenAsmWriter.inc X86GenRegisterName.inc X86 echo "Generating GenAsmWriter1.inc" ./asmwriter.py $1/X86GenAsmWriter1.inc X86GenAsmWriter1.inc X86GenRegisterName1.inc X86 echo "Generating instruction enum in insn_list.txt (for include/capstone/.h)" ./insn.py $1/X86GenAsmMatcher.inc $1/X86GenInstrInfo.inc $2/X86MappingInsn.inc > insn_list.txt # then copy these instructions to include/capstone/x86.h echo "Generating MappingInsnName.inc" ./mapping_insn_name.py $1/X86GenAsmMatcher.inc $1/X86GenInstrInfo.inc $2/X86MappingInsn.inc > X86MappingInsnName.inc echo "Generating MappingInsn.inc" ./mapping_insn.py $1/X86GenAsmMatcher.inc $1/X86GenInstrInfo.inc $2/X86MappingInsn.inc > X86MappingInsn.inc echo "Generating MappingInsnOp.inc" ./mapping_insn_op.py $1/X86GenAsmMatcher.inc $1/X86GenInstrInfo.inc $2/X86MappingInsnOp.inc > X86MappingInsnOp.inc echo "Generating GenInstrInfo.inc" ./instrinfo.py $1/X86GenInstrInfo.inc $1/X86GenAsmMatcher.inc > X86GenInstrInfo.inc echo "Generating GenDisassemblerTables.inc & X86GenDisassemblerTables2.inc" ./disassemblertables.py $1/X86GenDisassemblerTables.inc X86GenDisassemblerTables.inc X86GenDisassemblerTables2.inc make x86 capstone-sys-0.15.0/capstone/suite/synctools/genall-reduce.sh000075500000000000000000000026500072674642500224420ustar 00000000000000#!/bin/sh # generate all X86*reduce.inc files for Capstone, by Nguyen Anh Quynh # Syntax: genall.sh # ./genall-reduce.sh tablegen ~/projects/capstone.git/arch/X86 echo "Generating GenAsmWriter_reduce.inc" ./asmwriter.py $1/X86GenAsmWriter_reduce.inc X86GenAsmWriter_reduce.inc X86GenRegisterName.inc X86 echo "Generating GenAsmWriter1_reduce.inc" ./asmwriter.py $1/X86GenAsmWriter1_reduce.inc X86GenAsmWriter1_reduce.inc X86GenRegisterName1.inc X86 echo "Generating MappingInsnName_reduce.inc" ./mapping_insn_name.py $1/X86GenAsmMatcher_reduce.inc $1/X86GenInstrInfo_reduce.inc $2/X86MappingInsn_reduce.inc > X86MappingInsnName_reduce.inc echo "Generating MappingInsn_reduce.inc" ./mapping_insn.py $1/X86GenAsmMatcher_reduce.inc $1/X86GenInstrInfo_reduce.inc $2/X86MappingInsn_reduce.inc > X86MappingInsn_reduce.inc echo "Generating MappingInsnOp_reduce.inc" ./mapping_insn_op.py $1/X86GenAsmMatcher.inc $1/X86GenInstrInfo_reduce.inc $2/X86MappingInsnOp_reduce.inc > X86MappingInsnOp_reduce.inc echo "Generating GenInstrInfo_reduce.inc" ./instrinfo.py $1/X86GenInstrInfo_reduce.inc $1/X86GenAsmMatcher_reduce.inc > X86GenInstrInfo_reduce.inc echo "Generating GenDisassemblerTables_reduce.inc & GenDisassemblerTables_reduce2.inc" ./disassemblertables_reduce.py $1/X86GenDisassemblerTables_reduce.inc X86GenDisassemblerTables_reduce.inc X86GenDisassemblerTables_reduce2.inc capstone-sys-0.15.0/capstone/suite/synctools/insn.py000075500000000000000000000305330072674642500207210ustar 00000000000000#!/usr/bin/python # print list of instructions LLVM inc files, for Capstone disassembler. # this will be put into capstone/.h # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s MappingInsn.inc" %sys.argv[0]) sys.exit(1) # MappingInsn.inc f = open(sys.argv[3]) mapping = f.readlines() f.close() print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AArch64': arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, insn_id_list, insn_lines def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 #insn_lines = [] insn_id_list = {} arch = None first_insn = None pattern = None # first we try to find Table1, or Table0 for line in lines: if 'MatchEntry MatchTable0[] = {' in line.strip(): pattern = 'MatchEntry MatchTable0[] = {' elif 'MatchEntry MatchTable1[] = {' in line.strip(): pattern = 'MatchEntry MatchTable1[] = {' # last pattern, done break # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if pattern in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) if not mnem.startswith('__'): if not first_insn: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # print("***", arch, mnem, insn_id) insn_id_list[insn_id] = mnem #insn_lines.append(line) #return arch, first_insn, insn_id_list, insn_lines return arch, first_insn, insn_id_list # GenAsmMatcher.inc #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) arch = arch.upper() #for line in insn_id_list: # print(line) insn_list = [] #{ # X86_AAA, X86_INS_AAA, ##ifndef CAPSTONE_DIET # { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 ##endif #}, def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong): print(arch, insn_id, mnem, mnem_can_be_wrong) if not mnem_can_be_wrong: insn = "%s_INS_%s" %(arch.upper(), mnem.upper()) if insn in insn_list: return print("%s," %insn) insn_list.append(insn) return insn = "%s_%s" %(arch.upper(), insn_id) # so mnem can be wrong, we need to verify with MappingInsn.inc # first, try to find this entry in old MappingInsn.inc file for i in range(len(mapping)): tmp = mapping[i].split(',') if tmp[0].strip() == insn: insn = tmp[1].strip() if insn in insn_list: return #print("==== get below from MappingInsn.inc file: %s" %insn) print("%s," %insn) insn_list.append(insn) return # extract from GenInstrInfo.inc, because the insn id is in order enum_count = 0 meet_insn = False # GenInstrInfo.inc f = open(sys.argv[2]) lines = f.readlines() f.close() count = 0 last_mnem = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 #print(line.strip()) continue line = line.strip() if enum_count == 1: if 'INSTRUCTION_LIST_END' in line: break else: insn = None if meet_insn: # enum items insn = line.split('=')[0].strip() if 'CALLSTACK' in insn or 'TAILJUMP' in insn: # pseudo instruction insn = None elif line.startswith(first_insn): insn = line.split('=')[0].strip() meet_insn = True if insn: count += 1 if insn == 'BSWAP16r_BAD': last_mnem = 'BSWAP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp32': last_mnem = 'FCMOVNP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVP_Fp3': last_mnem = 'FCMOVP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrm_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVSX16rm16': last_mnem = 'MOVSX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVZX16rm16': last_mnem = 'MOVZX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'ST_Fp32m': last_mnem = 'FST' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp64': last_mnem = 'FCMOVNU' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrr_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSSrm_Int': last_mnem = 'CMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSDrm_Int': last_mnem = 'VCMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSSrm_Int': last_mnem = 'VCMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPCMOVYrrr_REV': last_mnem = 'VPCMOV' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESDZm': last_mnem = 'VRNDSCALESD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESSZm': last_mnem = 'VRNDSCALESS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPDZ128rm': last_mnem = 'VMAXPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPSZ128rm': last_mnem = 'VMAXPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSDZrm': last_mnem = 'VMAXSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSSZrm': last_mnem = 'VMAXSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPDZ128rm': last_mnem = 'VMINPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPSZ128rm': last_mnem = 'VMINPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSDZrm': last_mnem = 'VMINSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSSZrm': last_mnem = 'VMINSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMOV64toPQIZrm': last_mnem = 'VMOVQ' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PDYrr_REV': last_mnem = 'VPERMILPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PSYrr_REV': last_mnem = 'VPERMILPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SI64Zrm_Int': last_mnem = 'VCVTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SSrm_Int': last_mnem = 'VCVTSD2SS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSS2SI64Zrm_Int': last_mnem = 'VCVTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSD2SI64Zrm_Int': last_mnem = 'VCVTTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSS2SI64Zrm_Int': last_mnem = 'VCVTTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUBADD'): if insn[len('VFMSUBADD')].isdigit(): last_mnem = insn[:len('VFMSUBADD123xy')] else: last_mnem = insn[:len('VFMSUBADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADDSUB'): if insn[len('VFMADDSUB')].isdigit(): last_mnem = insn[:len('VFMADDSUB123xy')] else: last_mnem = insn[:len('VFMADDSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADD'): if insn[len('VFMADD')].isdigit(): last_mnem = insn[:len('VFMADD123PD')] else: last_mnem = insn[:len('VFMADDPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUB'): if insn[len('VFMSUB')].isdigit(): last_mnem = insn[:len('VFMSUB123PD')] else: last_mnem = insn[:len('VFMSUBPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMADD'): if insn[len('VFNMADD')].isdigit(): last_mnem = insn[:len('VFNMADD123xy')] else: last_mnem = insn[:len('VFNMADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMSUB'): if insn[len('VFNMSUB')].isdigit(): last_mnem = insn[:len('VFNMSUB123xy')] else: last_mnem = insn[:len('VFNMSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn in insn_id_list: # trust old mapping table last_mnem = insn_id_list[insn].upper() print_entry(arch.upper(), insn, last_mnem, mapping, False) else: # the last option when we cannot find mnem: use the last good mnem print_entry(arch.upper(), insn, last_mnem, mapping, True) capstone-sys-0.15.0/capstone/suite/synctools/insn3.py000075500000000000000000000060620072674642500210040ustar 00000000000000#!/usr/bin/python # print list of instructions LLVM inc files, for Capstone disassembler. # this will be put into capstone/.h # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AARCH64': arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, first_insn, insn_id_list def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 mnem_list = [] insn_id_list = {} arch = None first_insn = None pattern = None # first we try to find Table1, or Table0 for line in lines: if 'MatchEntry MatchTable0[] = {' in line.strip(): pattern = 'MatchEntry MatchTable0[] = {' elif 'MatchEntry MatchTable1[] = {' in line.strip(): pattern = 'MatchEntry MatchTable1[] = {' # last pattern, done break # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if pattern in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) # skip pseudo instructions if not mnem.startswith('__'): # PPC if mnem.endswith('-') or mnem.endswith('+'): mnem = mnem[:-1] if not first_insn: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # save this insn_id_list[insn_id] = mnem if not mnem in mnem_list: print("%s_INS_%s," %(arch, mnem.upper())) mnem_list.append(mnem) #return arch, first_insn, insn_id_list return arch, first_insn, insn_id_list # GenAsmMatcher.inc #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) capstone-sys-0.15.0/capstone/suite/synctools/insn_check.py000075500000000000000000000013200072674642500220460ustar 00000000000000#!/usr/bin/python # check MappingInsn.inc to find potential incorrect mapping - for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) # ARM_CMPri, ARM_INS_CMN, f = open(sys.argv[1]) lines = f.readlines() f.close() for line in lines: if '_INS_' in line: tmp = line.strip().split(',') if len(tmp) == 3 and tmp[2] == '': id_private = tmp[0].strip() id_public = tmp[1].strip() pos = id_public.find('_INS_') mnem = id_public[pos + len('_INS_'):] if not mnem in id_private: print("%s -> %s" %(id_private, id_public)) capstone-sys-0.15.0/capstone/suite/synctools/instrinfo-arch.py000075500000000000000000000101220072674642500226700ustar 00000000000000#!/usr/bin/python # convert LLVM GenInstrInfo.inc for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # return (arch, mnem) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AArch64': arch = 'ARM64' return (arch, insn_mnem) # get (arch, first insn) from MatchTable def get_first_insn(filename): f = open(filename) lines = f.readlines() f.close() count = 0 for line in lines: line = line.strip() if len(line) == 0: continue # Intel syntax in Table1 if 'MatchEntry MatchTable1[] = {' in line: count += 1 #print(line.strip()) continue if count == 1: arch, mnem = extract_insn(line) return (arch, mnem) return (None, None) #arch, first_insn = get_first_insn(sys.argv[2]) #first_insn = first_insn.upper() #print(arch, first_insn) arch = sys.argv[2].upper() if arch.upper() == 'AARCH64': arch = 'AArch64' elif arch.upper() == 'ARM64': arch = 'AArch64' print(""" /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM """) enum_count = 0 f = open(sys.argv[1]) lines = f.readlines() f.close() # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 print(line.strip()) continue line = line.strip() if enum_count == 1: if line == '};': # done with first enum break else: # skip pseudo instructions if '__' in line or 'setjmp' in line or 'longjmp' in line or 'Pseudo' in line: pass else: print("\t%s_%s" %(arch, line)) print('};\n') print("#endif // GET_INSTRINFO_ENUM") if arch == 'ARM64': sys.exit(0) print("") print("#ifdef GET_INSTRINFO_MC_DESC") print("#undef GET_INSTRINFO_MC_DESC") print("") print("#define nullptr 0") print("") in_insts = False for line in lines: if line.strip() == '': continue line = line.rstrip() if 'static const MCOperandInfo ' in line: line2 = line.replace('::', '_') print(line2) elif 'Insts[] = {' in line: # extern const MCInstrDesc ARMInsts[] = { line2 = line.replace('extern const ', 'static const ') print("") print(line2) in_insts = True elif in_insts: if line == '};': print(line) break # { 0, 1, 1, 0, 0, 0|(1ULL< " %sys.argv[0]) sys.exit(1) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # return (arch, mnem) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AArch64': arch = 'ARM64' return (arch, insn_mnem) # get (arch, first insn) from MatchTable def get_first_insn(filename): f = open(filename) lines = f.readlines() f.close() count = 0 for line in lines: line = line.strip() if len(line) == 0: continue # Intel syntax in Table1 if 'MatchEntry MatchTable1[] = {' in line: count += 1 #print(line.strip()) continue if count == 1: arch, mnem = extract_insn(line) return (arch, mnem) return (None, None) arch, first_insn = get_first_insn(sys.argv[2]) first_insn = first_insn.upper() arch = arch.upper() #print(arch, first_insn) print(""" /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM """) enum_count = 0 meet_insn = False f = open(sys.argv[1]) lines = f.readlines() f.close() # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 print(line.strip()) continue line = line.strip() if enum_count == 1: if line == '};': # done with first enum break else: insn = None if meet_insn: # enum items insn = line elif line.startswith(first_insn): insn = line meet_insn = True if insn: print("\t%s_%s" %(arch, line)) print('};\n') print("#endif // GET_INSTRINFO_ENUM") capstone-sys-0.15.0/capstone/suite/synctools/mapping_insn-arch.py000075500000000000000000000322640072674642500233520ustar 00000000000000#!/usr/bin/python # print MappingInsn.inc file from LLVM GenAsmMatcher.inc, for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s MappingInsn.inc" %sys.argv[0]) sys.exit(1) f = open(sys.argv[3]) mapping = f.readlines() f.close() print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 #if arch.upper() == 'AARCH64': # arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, first_insn, insn_id_list def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 insn_id_list = {} arch = None first_insn = None pattern = None # first we try to find Table1, or Table0 for line in lines: if 'MatchEntry MatchTable0[] = {' in line.strip(): pattern = 'MatchEntry MatchTable0[] = {' elif 'AArch64::' in line and pattern: # We do not care about Apple Assembly break elif 'MatchEntry MatchTable1[] = {' in line.strip(): pattern = 'MatchEntry MatchTable1[] = {' # last pattern, done break for line in lines: line = line.rstrip() # skip empty line if len(line.strip()) == 0: continue if pattern in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) # skip pseudo instructions if not mnem.startswith('__'): # PPC if mnem.endswith('-') or mnem.endswith('+'): mnem = mnem[:-1] if not first_insn: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # save this insn_id_list[insn_id] = mnem #return arch, first_insn, insn_id_list return arch, first_insn, insn_id_list #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) #arch = arch.upper() #print("first insn = %s" %first_insn) #for line in insn_id_list: # print(line) #{ # X86_AAA, X86_INS_AAA, ##ifndef CAPSTONE_DIET # { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 ##endif #}, def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong): #insn = "%s_%s" %(arch.upper(), insn_id) insn = "%s_%s" %(arch, insn_id) arch1 = arch if arch.upper() == 'AARCH64': arch1 = 'ARM64' #if '64' in insn_id: # is64bit = '1' #else: # is64bit = '0' # first, try to find this entry in old MappingInsn.inc file for i in range(len(mapping)): tmp = mapping[i].split(',') if tmp[0].strip() == insn: if not mnem_can_be_wrong: print(''' { \t%s, %s_INS_%s, #ifndef CAPSTONE_DIET \t%s #endif },'''% (insn, arch1, mnem, mapping[i + 2].strip())) else: # ATTENTION: mnem can be wrong if not tmp[1].endswith(mnem): #print("======== cannot find %s, mapping to %s (instead of %s)" %(insn, tmp[1].strip(), mnem)) pass print(''' { \t%s, %s, #ifndef CAPSTONE_DIET \t%s #endif },'''% (insn, tmp[1].strip(), mapping[i + 2].strip())) return if mnem_can_be_wrong: #print("======== CANNOT FIND %s, mapping to %s" %(insn, mnem)) return pass # this insn does not exist in mapping table print(''' { \t%s, %s_INS_%s, #ifndef CAPSTONE_DIET \t{ 0 }, { 0 }, { 0 }, 0, 0 #endif },'''% (insn, arch1, mnem)) # extract from GenInstrInfo.inc, because the insn id is in order enum_count = 0 meet_insn = False f = open(sys.argv[2]) lines = f.readlines() f.close() count = 0 last_mnem = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue # skip pseudo instructions if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 #print(line.strip()) continue line = line.strip() if enum_count == 1: # skip pseudo instructions if '__' in line or 'setjmp' in line or 'longjmp' in line or 'Pseudo' in line: continue elif 'INSTRUCTION_LIST_END' in line: break else: insn = line.split('=')[0].strip() ''' insn = None if meet_insn: # enum items insn = line.split('=')[0].strip() if 'CALLSTACK' in insn or 'TAILJUMP' in insn: # pseudo instruction insn = None elif line.startswith(first_insn): insn = line.split('=')[0].strip() meet_insn = True if insn: count += 1 if insn == 'BSWAP16r_BAD': last_mnem = 'BSWAP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp32': last_mnem = 'FCMOVNP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVP_Fp3': last_mnem = 'FCMOVP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrm_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVSX16rm16': last_mnem = 'MOVSX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVZX16rm16': last_mnem = 'MOVZX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'ST_Fp32m': last_mnem = 'FST' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp64': last_mnem = 'FCMOVNU' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrr_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSSrm_Int': last_mnem = 'CMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSDrm_Int': last_mnem = 'VCMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSSrm_Int': last_mnem = 'VCMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPCMOVYrrr_REV': last_mnem = 'VPCMOV' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESDZm': last_mnem = 'VRNDSCALESD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESSZm': last_mnem = 'VRNDSCALESS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPDZ128rm': last_mnem = 'VMAXPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPSZ128rm': last_mnem = 'VMAXPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSDZrm': last_mnem = 'VMAXSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSSZrm': last_mnem = 'VMAXSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPDZ128rm': last_mnem = 'VMINPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPSZ128rm': last_mnem = 'VMINPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSDZrm': last_mnem = 'VMINSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSSZrm': last_mnem = 'VMINSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMOV64toPQIZrm': last_mnem = 'VMOVQ' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PDYrr_REV': last_mnem = 'VPERMILPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PSYrr_REV': last_mnem = 'VPERMILPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SI64Zrm_Int': last_mnem = 'VCVTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SSrm_Int': last_mnem = 'VCVTSD2SS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSS2SI64Zrm_Int': last_mnem = 'VCVTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSD2SI64Zrm_Int': last_mnem = 'VCVTTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSS2SI64Zrm_Int': last_mnem = 'VCVTTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUBADD'): if insn[len('VFMSUBADD')].isdigit(): last_mnem = insn[:len('VFMSUBADD123xy')] else: last_mnem = insn[:len('VFMSUBADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADDSUB'): if insn[len('VFMADDSUB')].isdigit(): last_mnem = insn[:len('VFMADDSUB123xy')] else: last_mnem = insn[:len('VFMADDSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADD'): if insn[len('VFMADD')].isdigit(): last_mnem = insn[:len('VFMADD123PD')] else: last_mnem = insn[:len('VFMADDPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUB'): if insn[len('VFMSUB')].isdigit(): last_mnem = insn[:len('VFMSUB123PD')] else: last_mnem = insn[:len('VFMSUBPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMADD'): if insn[len('VFNMADD')].isdigit(): last_mnem = insn[:len('VFNMADD123xy')] else: last_mnem = insn[:len('VFNMADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMSUB'): if insn[len('VFNMSUB')].isdigit(): last_mnem = insn[:len('VFNMSUB123xy')] else: last_mnem = insn[:len('VFNMSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) ''' if insn in insn_id_list: # trust old mapping table last_mnem = insn_id_list[insn].upper() print_entry(arch, insn, insn_id_list[insn].upper(), mapping, False) else: # the last option when we cannot find mnem: use the last good mnem print_entry(arch, insn, last_mnem, mapping, True) capstone-sys-0.15.0/capstone/suite/synctools/mapping_insn.py000075500000000000000000000303230072674642500224310ustar 00000000000000#!/usr/bin/python # print MappingInsn.inc file from LLVM GenAsmMatcher.inc, for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s MappingInsn.inc" %sys.argv[0]) sys.exit(1) f = open(sys.argv[3]) mapping = f.readlines() f.close() print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AARCH64': arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, insn_id_list, insn_lines def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 count = 0 #insn_lines = [] insn_id_list = {} arch = None first_insn = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'MatchEntry MatchTable1[] = {' in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: count += 1 if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) if count == 1: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # print("***", arch, mnem, insn_id) insn_id_list[insn_id] = mnem #insn_lines.append(line) #return arch, first_insn, insn_id_list, insn_lines return arch, first_insn, insn_id_list #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) arch = arch.upper() #for line in insn_id_list: # print(line) #{ # X86_AAA, X86_INS_AAA, ##ifndef CAPSTONE_DIET # { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 ##endif #}, def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong): insn = "%s_%s" %(arch.upper(), insn_id) if '64' in insn_id: is64bit = '1' else: is64bit = '0' # first, try to find this entry in old MappingInsn.inc file for i in range(len(mapping)): tmp = mapping[i].split(',') if tmp[0].strip() == insn: if not mnem_can_be_wrong: print(''' { \t%s_%s, %s_INS_%s, %s, #ifndef CAPSTONE_DIET \t%s #endif },'''% (arch, insn_id, arch, mnem, is64bit, mapping[i + 2].strip())) else: if not tmp[1].endswith(mnem): #print("======== cannot find %s, mapping to %s (instead of %s)" %(insn, tmp[1].strip(), mnem)) pass print(''' { \t%s_%s, %s, %s, #ifndef CAPSTONE_DIET \t%s #endif },'''% (arch, insn_id, tmp[1].strip(), is64bit, mapping[i + 2].strip())) return if mnem_can_be_wrong: #print("======== CANNOT FIND %s, mapping to %s" %(insn, mnem)) pass print(''' { \t%s_%s, %s_INS_%s, %s, #ifndef CAPSTONE_DIET \t{ 0 }, { 0 }, { 0 }, 0, 0 #endif },'''% (arch, insn_id, arch, mnem, is64bit)) # extract from GenInstrInfo.inc, because the insn id is in order enum_count = 0 meet_insn = False f = open(sys.argv[2]) lines = f.readlines() f.close() count = 0 last_mnem = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 #print(line.strip()) continue line = line.strip() if enum_count == 1: if 'INSTRUCTION_LIST_END' in line: break else: insn = None if meet_insn: # enum items insn = line.split('=')[0].strip() if 'CALLSTACK' in insn or 'TAILJUMP' in insn: # pseudo instruction insn = None elif line.startswith(first_insn): insn = line.split('=')[0].strip() meet_insn = True if insn: count += 1 if insn == 'BSWAP16r_BAD': last_mnem = 'BSWAP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp32': last_mnem = 'FCMOVNP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVP_Fp3': last_mnem = 'FCMOVP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrm_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVSX16rm16': last_mnem = 'MOVSX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVZX16rm16': last_mnem = 'MOVZX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'ST_Fp32m': last_mnem = 'FST' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp64': last_mnem = 'FCMOVNU' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrr_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSSrm_Int': last_mnem = 'CMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSDrm_Int': last_mnem = 'VCMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSSrm_Int': last_mnem = 'VCMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPCMOVYrrr_REV': last_mnem = 'VPCMOV' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESDZm': last_mnem = 'VRNDSCALESD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESSZm': last_mnem = 'VRNDSCALESS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPDZ128rm': last_mnem = 'VMAXPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPSZ128rm': last_mnem = 'VMAXPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSDZrm': last_mnem = 'VMAXSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSSZrm': last_mnem = 'VMAXSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPDZ128rm': last_mnem = 'VMINPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPSZ128rm': last_mnem = 'VMINPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSDZrm': last_mnem = 'VMINSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSSZrm': last_mnem = 'VMINSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMOV64toPQIZrm': last_mnem = 'VMOVQ' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PDYrr_REV': last_mnem = 'VPERMILPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PSYrr_REV': last_mnem = 'VPERMILPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SI64Zrm_Int': last_mnem = 'VCVTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SSrm_Int': last_mnem = 'VCVTSD2SS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSS2SI64Zrm_Int': last_mnem = 'VCVTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSD2SI64Zrm_Int': last_mnem = 'VCVTTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSS2SI64Zrm_Int': last_mnem = 'VCVTTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUBADD'): if insn[len('VFMSUBADD')].isdigit(): last_mnem = insn[:len('VFMSUBADD123xy')] else: last_mnem = insn[:len('VFMSUBADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADDSUB'): if insn[len('VFMADDSUB')].isdigit(): last_mnem = insn[:len('VFMADDSUB123xy')] else: last_mnem = insn[:len('VFMADDSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADD'): if insn[len('VFMADD')].isdigit(): last_mnem = insn[:len('VFMADD123PD')] else: last_mnem = insn[:len('VFMADDPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUB'): if insn[len('VFMSUB')].isdigit(): last_mnem = insn[:len('VFMSUB123PD')] else: last_mnem = insn[:len('VFMSUBPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMADD'): if insn[len('VFNMADD')].isdigit(): last_mnem = insn[:len('VFNMADD123xy')] else: last_mnem = insn[:len('VFNMADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMSUB'): if insn[len('VFNMSUB')].isdigit(): last_mnem = insn[:len('VFNMSUB123xy')] else: last_mnem = insn[:len('VFNMSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn in insn_id_list: # trust old mapping table last_mnem = insn_id_list[insn].upper() print_entry(arch.upper(), insn, insn_id_list[insn].upper(), mapping, False) else: # the last option when we cannot find mnem: use the last good mnem print_entry(arch.upper(), insn, last_mnem, mapping, True) capstone-sys-0.15.0/capstone/suite/synctools/mapping_insn_name-arch.py000075500000000000000000000061130072674642500243440ustar 00000000000000#!/usr/bin/python # print list of instructions LLVM inc files, for Capstone disassembler. # this will be put into capstone/.h # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AARCH64': arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, first_insn, insn_id_list def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 mnem_list = [] insn_id_list = {} arch = None first_insn = None pattern = None # first we try to find Table1, or Table0 for line in lines: if 'MatchEntry MatchTable0[] = {' in line.strip(): pattern = 'MatchEntry MatchTable0[] = {' elif 'MatchEntry MatchTable1[] = {' in line.strip(): pattern = 'MatchEntry MatchTable1[] = {' # last pattern, done break # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if pattern in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) # skip pseudo instructions if not mnem.startswith('__'): # PPC if mnem.endswith('-') or mnem.endswith('+'): mnem = mnem[:-1] if not first_insn: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # save this insn_id_list[insn_id] = mnem if not mnem in mnem_list: print('\t"%s", // %s_INS_%s,' %(mnem.lower(), arch, mnem.upper())) mnem_list.append(mnem) #return arch, first_insn, insn_id_list return arch, first_insn, insn_id_list # GenAsmMatcher.inc #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) capstone-sys-0.15.0/capstone/suite/synctools/mapping_insn_name.py000075500000000000000000000277340072674642500234450ustar 00000000000000#!/usr/bin/python # print list of instructions LLVM inc files, for Capstone disassembler. # this will be put into capstone/.h # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s MappingInsn.inc" %sys.argv[0]) sys.exit(1) f = open(sys.argv[3]) mapping = f.readlines() f.close() print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AARCH64': arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, insn_id_list, insn_lines def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 count = 0 #insn_lines = [] insn_id_list = {} arch = None first_insn = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'MatchEntry MatchTable1[] = {' in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: count += 1 if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) if count == 1: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # print("***", arch, mnem, insn_id) insn_id_list[insn_id] = mnem #insn_lines.append(line) #return arch, first_insn, insn_id_list, insn_lines return arch, first_insn, insn_id_list #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) arch = arch.upper() #for line in insn_id_list: # print(line) insn_list = [] #{ # X86_AAA, X86_INS_AAA, ##ifndef CAPSTONE_DIET # { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0 ##endif #}, def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong): if not mnem_can_be_wrong: insn = "%s_INS_%s" %(arch.upper(), mnem.upper()) if insn in insn_list: return print('\t"%s", // %s' %(mnem.lower(), insn)) insn_list.append(insn) return insn = "%s_%s" %(arch.upper(), insn_id) # so mnem can be wrong, we need to verify with MappingInsn.inc # first, try to find this entry in old MappingInsn.inc file for i in range(len(mapping)): tmp = mapping[i].split(',') if tmp[0].strip() == insn: insn = tmp[1].strip() if insn in insn_list: return mnem = insn[len("%s_INS_" %(arch)):] #print("==== get below from MappingInsn.inc file: %s" %insn) print('\t"%s", // %s' %(mnem.lower(), insn)) insn_list.append(insn) return # extract from GenInstrInfo.inc, because the insn id is in order enum_count = 0 meet_insn = False f = open(sys.argv[2]) lines = f.readlines() f.close() count = 0 last_mnem = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 #print(line.strip()) continue line = line.strip() if enum_count == 1: if 'INSTRUCTION_LIST_END' in line: break else: insn = None if meet_insn: # enum items insn = line.split('=')[0].strip() if 'CALLSTACK' in insn or 'TAILJUMP' in insn: # pseudo instruction insn = None elif line.startswith(first_insn): insn = line.split('=')[0].strip() meet_insn = True if insn: count += 1 if insn == 'BSWAP16r_BAD': last_mnem = 'BSWAP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp32': last_mnem = 'FCMOVNP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVP_Fp3': last_mnem = 'FCMOVP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrm_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVSX16rm16': last_mnem = 'MOVSX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVZX16rm16': last_mnem = 'MOVZX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'ST_Fp32m': last_mnem = 'FST' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp64': last_mnem = 'FCMOVNU' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrr_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSSrm_Int': last_mnem = 'CMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSDrm_Int': last_mnem = 'VCMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSSrm_Int': last_mnem = 'VCMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPCMOVYrrr_REV': last_mnem = 'VPCMOV' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESDZm': last_mnem = 'VRNDSCALESD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESSZm': last_mnem = 'VRNDSCALESS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPDZ128rm': last_mnem = 'VMAXPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPSZ128rm': last_mnem = 'VMAXPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSDZrm': last_mnem = 'VMAXSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSSZrm': last_mnem = 'VMAXSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPDZ128rm': last_mnem = 'VMINPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPSZ128rm': last_mnem = 'VMINPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSDZrm': last_mnem = 'VMINSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSSZrm': last_mnem = 'VMINSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMOV64toPQIZrm': last_mnem = 'VMOVQ' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PDYrr_REV': last_mnem = 'VPERMILPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PSYrr_REV': last_mnem = 'VPERMILPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SI64Zrm_Int': last_mnem = 'VCVTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SSrm_Int': last_mnem = 'VCVTSD2SS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSS2SI64Zrm_Int': last_mnem = 'VCVTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSD2SI64Zrm_Int': last_mnem = 'VCVTTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSS2SI64Zrm_Int': last_mnem = 'VCVTTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUBADD'): if insn[len('VFMSUBADD')].isdigit(): last_mnem = insn[:len('VFMSUBADD123xy')] else: last_mnem = insn[:len('VFMSUBADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADDSUB'): if insn[len('VFMADDSUB')].isdigit(): last_mnem = insn[:len('VFMADDSUB123xy')] else: last_mnem = insn[:len('VFMADDSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADD'): if insn[len('VFMADD')].isdigit(): last_mnem = insn[:len('VFMADD123PD')] else: last_mnem = insn[:len('VFMADDPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUB'): if insn[len('VFMSUB')].isdigit(): last_mnem = insn[:len('VFMSUB123PD')] else: last_mnem = insn[:len('VFMSUBPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMADD'): if insn[len('VFNMADD')].isdigit(): last_mnem = insn[:len('VFNMADD123xy')] else: last_mnem = insn[:len('VFNMADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMSUB'): if insn[len('VFNMSUB')].isdigit(): last_mnem = insn[:len('VFNMSUB123xy')] else: last_mnem = insn[:len('VFNMSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn in insn_id_list: # trust old mapping table last_mnem = insn_id_list[insn].upper() print_entry(arch.upper(), insn, last_mnem, mapping, False) else: # the last option when we cannot find mnem: use the last good mnem print_entry(arch.upper(), insn, last_mnem, mapping, True) capstone-sys-0.15.0/capstone/suite/synctools/mapping_insn_op-arch.py000075500000000000000000000335760072674642500240570ustar 00000000000000#!/usr/bin/python # print MappingInsn.inc file from LLVM GenAsmMatcher.inc, for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[3]) mapping = f.readlines() f.close() print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 #if arch.upper() == 'AARCH64': # arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, first_insn, insn_id_list def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 insn_id_list = {} arch = None first_insn = None pattern = None # first we try to find Table1, or Table0 for line in lines: if 'MatchEntry MatchTable0[] = {' in line.strip(): pattern = 'MatchEntry MatchTable0[] = {' elif 'AArch64::' in line and pattern: # We do not care about Apple Assembly break elif 'MatchEntry MatchTable1[] = {' in line.strip(): pattern = 'MatchEntry MatchTable1[] = {' # last pattern, done break for line in lines: line = line.rstrip() # skip empty line if len(line.strip()) == 0: continue if pattern in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) # skip pseudo instructions if not mnem.startswith('__'): if not first_insn: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # save this insn_id_list[insn_id] = mnem #return arch, first_insn, insn_id_list return arch, first_insn, insn_id_list #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) #arch = arch.upper() #for line in insn_id_list: # print(line) #{ /* X86_AAA, X86_INS_AAA: aaa */ # X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, # { 0 } #}, #{ /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ # { CS_AC_WRITE, CS_AC_READ, 0 } #}, def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong): insn = "%s_%s" %(arch, insn_id) arch1 = arch if arch.upper() == 'AARCH64': arch1 = 'ARM64' # first, try to find this entry in old MappingInsn.inc file for i in range(len(mapping)): if mapping[i].startswith('{') and '/*' in mapping[i]: #print(mapping[i]) tmp = mapping[i].split('/*') tmp = tmp[1].strip() tmp = tmp.split(',') #print("insn2 = |%s|" %tmp.strip()) if tmp[0].strip() == insn: if not mnem_can_be_wrong: if arch.upper() == 'ARM': print(''' {\t/* %s, %s_INS_%s: %s */ \t%s },'''% (insn, arch1, mnem, mnem.lower(), mapping[i + 1].strip())) else: # ARM64 print(''' {\t/* %s, %s_INS_%s: %s */ \t%s \t%s },'''% (insn, arch, mnem, mnem.lower(), mapping[i + 1].strip(), mapping[i + 2].strip())) else: if arch.upper() == 'ARM': print(''' {\t/* %s, %s \t%s },'''% (insn, ''.join(tmp[1:]), mapping[i + 1].strip())) else: # ARM64 print(''' {\t/* %s, %s \t%s \t%s },'''% (insn, ''.join(tmp[1:]), mapping[i + 1].strip(), mapping[i + 2].strip())) return if mnem_can_be_wrong: #print("======== CANNOT FIND %s, mapping to %s" %(insn, mnem)) return pass # this insn does not exist in mapping table if arch.upper() == 'ARM': print(''' {\t/* %s, %s_INS_%s: %s */ \t{ 0 } },'''% (insn, arch1, mnem, mnem.lower())) else: print(''' {\t/* %s, %s_INS_%s: %s */ \t0, \t{ 0 } },'''% (insn, arch, mnem, mnem.lower())) # extract from GenInstrInfo.inc, because the insn id is in order enum_count = 0 meet_insn = False f = open(sys.argv[2]) lines = f.readlines() f.close() count = 0 last_mnem = None def is_pseudo_insn(insn, lines): return False for line in lines: tmp = '= %s' %insn if tmp in line and 'MCID::Pseudo' in line: return True return False # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 #print(line.strip()) continue line = line.strip() if enum_count == 1: # skip pseudo instructions if '__' in line or 'setjmp' in line or 'longjmp' in line or 'Pseudo' in line: continue elif 'INSTRUCTION_LIST_END' in line: break else: insn = line.split('=')[0].strip() # skip more pseudo instruction if is_pseudo_insn(insn, lines): continue ''' insn = None if meet_insn: # enum items insn = line.split('=')[0].strip() if 'CALLSTACK' in insn or 'TAILJUMP' in insn: # pseudo instruction insn = None elif line.startswith(first_insn): insn = line.split('=')[0].strip() meet_insn = True if insn: count += 1 if insn == 'BSWAP16r_BAD': last_mnem = 'BSWAP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp32': last_mnem = 'FCMOVNP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVP_Fp3': last_mnem = 'FCMOVP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrm_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVSX16rm16': last_mnem = 'MOVSX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVZX16rm16': last_mnem = 'MOVZX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'ST_Fp32m': last_mnem = 'FST' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp64': last_mnem = 'FCMOVNU' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrr_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSSrm_Int': last_mnem = 'CMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSDrm_Int': last_mnem = 'VCMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSSrm_Int': last_mnem = 'VCMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPCMOVYrrr_REV': last_mnem = 'VPCMOV' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESDZm': last_mnem = 'VRNDSCALESD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESSZm': last_mnem = 'VRNDSCALESS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPDZ128rm': last_mnem = 'VMAXPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPSZ128rm': last_mnem = 'VMAXPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSDZrm': last_mnem = 'VMAXSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSSZrm': last_mnem = 'VMAXSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPDZ128rm': last_mnem = 'VMINPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPSZ128rm': last_mnem = 'VMINPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSDZrm': last_mnem = 'VMINSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSSZrm': last_mnem = 'VMINSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMOV64toPQIZrm': last_mnem = 'VMOVQ' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PDYrr_REV': last_mnem = 'VPERMILPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PSYrr_REV': last_mnem = 'VPERMILPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SI64Zrm_Int': last_mnem = 'VCVTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SSrm_Int': last_mnem = 'VCVTSD2SS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSS2SI64Zrm_Int': last_mnem = 'VCVTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSD2SI64Zrm_Int': last_mnem = 'VCVTTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSS2SI64Zrm_Int': last_mnem = 'VCVTTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUBADD'): if insn[len('VFMSUBADD')].isdigit(): last_mnem = insn[:len('VFMSUBADD123xy')] else: last_mnem = insn[:len('VFMSUBADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADDSUB'): if insn[len('VFMADDSUB')].isdigit(): last_mnem = insn[:len('VFMADDSUB123xy')] else: last_mnem = insn[:len('VFMADDSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADD'): if insn[len('VFMADD')].isdigit(): last_mnem = insn[:len('VFMADD123PD')] else: last_mnem = insn[:len('VFMADDPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUB'): if insn[len('VFMSUB')].isdigit(): last_mnem = insn[:len('VFMSUB123PD')] else: last_mnem = insn[:len('VFMSUBPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMADD'): if insn[len('VFNMADD')].isdigit(): last_mnem = insn[:len('VFNMADD123xy')] else: last_mnem = insn[:len('VFNMADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMSUB'): if insn[len('VFNMSUB')].isdigit(): last_mnem = insn[:len('VFNMSUB123xy')] else: last_mnem = insn[:len('VFNMSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) ''' if insn in insn_id_list: # trust old mapping table last_mnem = insn_id_list[insn].upper() print_entry(arch, insn, insn_id_list[insn].upper(), mapping, False) else: #pass # the last option when we cannot find mnem: use the last good mnem print_entry(arch, insn, last_mnem, mapping, True) capstone-sys-0.15.0/capstone/suite/synctools/mapping_insn_op.py000075500000000000000000000301160072674642500231270ustar 00000000000000#!/usr/bin/python # print MappingInsn.inc file from LLVM GenAsmMatcher.inc, for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[3]) mapping = f.readlines() f.close() print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # lib/Target/X86/X86GenAsmMatcher.inc # static const MatchEntry MatchTable1[] = { # { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, }, # extract insn from GenAsmMatcher Table # return (arch, mnem, insn_id) def extract_insn(line): tmp = line.split(',') insn_raw = tmp[1].strip() insn_mnem = tmp[0].split(' ')[3] # X86 mov.s if '.' in insn_mnem: tmp = insn_mnem.split('.') insn_mnem = tmp[0] tmp = insn_raw.split('::') arch = tmp[0] # AArch64 -> ARM64 if arch.upper() == 'AARCH64': arch = 'ARM64' return (arch, insn_mnem, tmp[1]) # extract all insn lines from GenAsmMatcher # return arch, insn_id_list, insn_lines def extract_matcher(filename): f = open(filename) lines = f.readlines() f.close() match_count = 0 count = 0 #insn_lines = [] insn_id_list = {} arch = None first_insn = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'MatchEntry MatchTable1[] = {' in line.strip(): match_count += 1 #print(line.strip()) continue line = line.strip() if match_count == 1: count += 1 if line == '};': # done with first enum break else: _arch, mnem, insn_id = extract_insn(line) if count == 1: arch, first_insn = _arch, insn_id if not insn_id in insn_id_list: # print("***", arch, mnem, insn_id) insn_id_list[insn_id] = mnem #insn_lines.append(line) #return arch, first_insn, insn_id_list, insn_lines return arch, first_insn, insn_id_list #arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1]) arch, first_insn, insn_id_list = extract_matcher(sys.argv[1]) arch = arch.upper() #for line in insn_id_list: # print(line) #{ /* X86_AAA, X86_INS_AAA: aaa */ # X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF, # { 0 } #}, def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong): insn = "%s_%s" %(arch, insn_id) # first, try to find this entry in old MappingInsn.inc file for i in range(len(mapping)): if mapping[i].startswith('{') and '/*' in mapping[i]: #print(mapping[i]) tmp = mapping[i].split('/*') tmp = tmp[1].strip() tmp = tmp.split(',') #print("insn2 = |%s|" %tmp.strip()) if tmp[0].strip() == insn: if not mnem_can_be_wrong: print(''' {\t/* %s, %s_INS_%s: %s */ \t%s \t%s },'''% (insn, arch, mnem, mnem.lower(), mapping[i + 1].strip(), mapping[i + 2].strip())) else: print(''' {\t/* %s, %s \t%s \t%s },'''% (insn, ''.join(tmp[1:]).strip(), mapping[i + 1].strip(), mapping[i + 2].strip())) return print(''' {\t/* %s, %s_INS_%s: %s */ \t0, \t{ 0 } },'''% (insn, arch, mnem, mnem.lower())) # extract from GenInstrInfo.inc, because the insn id is in order enum_count = 0 meet_insn = False f = open(sys.argv[2]) lines = f.readlines() f.close() count = 0 last_mnem = None # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 #print(line.strip()) continue line = line.strip() if enum_count == 1: if 'INSTRUCTION_LIST_END' in line: break else: insn = None if meet_insn: # enum items insn = line.split('=')[0].strip() if 'CALLSTACK' in insn or 'TAILJUMP' in insn: # pseudo instruction insn = None elif line.startswith(first_insn): insn = line.split('=')[0].strip() meet_insn = True if insn: count += 1 if insn == 'BSWAP16r_BAD': last_mnem = 'BSWAP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp32': last_mnem = 'FCMOVNP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVP_Fp3': last_mnem = 'FCMOVP' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrm_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVSX16rm16': last_mnem = 'MOVSX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'MOVZX16rm16': last_mnem = 'MOVZX' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'ST_Fp32m': last_mnem = 'FST' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMOVNP_Fp64': last_mnem = 'FCMOVNU' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSDrr_Int': last_mnem = 'CMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'CMPSSrm_Int': last_mnem = 'CMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSDrm_Int': last_mnem = 'VCMPSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCMPSSrm_Int': last_mnem = 'VCMPSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPCMOVYrrr_REV': last_mnem = 'VPCMOV' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESDZm': last_mnem = 'VRNDSCALESD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VRNDSCALESSZm': last_mnem = 'VRNDSCALESS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPDZ128rm': last_mnem = 'VMAXPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCPSZ128rm': last_mnem = 'VMAXPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSDZrm': last_mnem = 'VMAXSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMAXCSSZrm': last_mnem = 'VMAXSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPDZ128rm': last_mnem = 'VMINPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCPSZ128rm': last_mnem = 'VMINPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSDZrm': last_mnem = 'VMINSD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMINCSSZrm': last_mnem = 'VMINSS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VMOV64toPQIZrm': last_mnem = 'VMOVQ' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PDYrr_REV': last_mnem = 'VPERMILPD' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VPERMIL2PSYrr_REV': last_mnem = 'VPERMILPS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SI64Zrm_Int': last_mnem = 'VCVTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSD2SSrm_Int': last_mnem = 'VCVTSD2SS' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTSS2SI64Zrm_Int': last_mnem = 'VCVTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSD2SI64Zrm_Int': last_mnem = 'VCVTTSD2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn == 'VCVTTSS2SI64Zrm_Int': last_mnem = 'VCVTTSS2SI' print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUBADD'): if insn[len('VFMSUBADD')].isdigit(): last_mnem = insn[:len('VFMSUBADD123xy')] else: last_mnem = insn[:len('VFMSUBADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADDSUB'): if insn[len('VFMADDSUB')].isdigit(): last_mnem = insn[:len('VFMADDSUB123xy')] else: last_mnem = insn[:len('VFMADDSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMADD'): if insn[len('VFMADD')].isdigit(): last_mnem = insn[:len('VFMADD123PD')] else: last_mnem = insn[:len('VFMADDPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFMSUB'): if insn[len('VFMSUB')].isdigit(): last_mnem = insn[:len('VFMSUB123PD')] else: last_mnem = insn[:len('VFMSUBPD')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMADD'): if insn[len('VFNMADD')].isdigit(): last_mnem = insn[:len('VFNMADD123xy')] else: last_mnem = insn[:len('VFNMADDSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn.startswith('VFNMSUB'): if insn[len('VFNMSUB')].isdigit(): last_mnem = insn[:len('VFNMSUB123xy')] else: last_mnem = insn[:len('VFNMSUBSS')] print_entry(arch.upper(), insn, last_mnem, mapping, False) elif insn in insn_id_list: # trust old mapping table last_mnem = insn_id_list[insn].upper() print_entry(arch.upper(), insn, insn_id_list[insn].upper(), mapping, False) else: # the last option when we cannot find mnem: use the last good mnem print_entry(arch.upper(), insn, last_mnem, mapping, True) capstone-sys-0.15.0/capstone/suite/synctools/mapping_reg.py000075500000000000000000000031100072674642500222310ustar 00000000000000#!/usr/bin/python # print out all registers from LLVM GenRegisterInfo.inc for Capstone disassembler. # NOTE: the list then must be filtered, manually. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() arch = sys.argv[2].upper() enum_count = 0 print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ /* By Nguyen Anh Quynh , 2013-2019 */ """) # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 continue if enum_count == 1: if line == '};': # done with first enum break else: # enum items if 'NoRegister' in line or 'TARGET_REGS' in line: continue reg = line.strip().split('=')[0].strip() if reg.startswith('H') or reg.endswith('PH') or reg.endswith('IH') or reg.endswith('WH'): print("{ %s_%s, 0 }," %(arch, reg)) elif 'K' in reg or 'BND' in reg: print("{ %s_%s, 0 }," %(arch, reg)) elif reg in ('DF', 'SSP', 'R8BH', 'R9BH', 'R10BH', 'R11BH', 'R12BH', 'R13BH', 'R14BH', 'R15BH'): print("{ %s_%s, 0 }," %(arch, reg)) else: print("{ %s_%s, %s_REG_%s }," %(arch, reg, arch, reg)) capstone-sys-0.15.0/capstone/suite/synctools/register.py000075500000000000000000000025630072674642500216000ustar 00000000000000#!/usr/bin/python # print out all registers from LLVM GenRegisterInfo.inc for Capstone disassembler. # NOTE: the list then must be filtered, manually. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() arch = sys.argv[2].upper() enum_count = 0 # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 continue if enum_count == 1: if line == '};': # done with first enum break else: # enum items if 'NoRegister' in line or 'TARGET_REGS' in line: continue reg = line.strip().split('=')[0].strip() if reg.startswith('H') or reg.endswith('PH') or or reg.endswith('IH') or or reg.endswith('WH'): print(" %s_REG_%s = REMOVE," %(arch, reg)) elif 'K' in reg or 'BND' in reg: print(" %s_REG_%s = REMOVE," %(arch, reg)) elif reg in ('DF', 'SSP', 'R8BH', 'R9BH', 'R10BH', 'R11BH', 'R12BH', 'R13BH', 'R14BH', 'R15BH'): print(" %s_REG_%s = REMOVE," %(arch, reg)) else: print(" %s_REG_%s," %(arch, reg)) capstone-sys-0.15.0/capstone/suite/synctools/registerinfo.py000075500000000000000000000155510072674642500224550ustar 00000000000000#!/usr/bin/python # convert LLVM GenRegisterInfo.inc for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() arch = sys.argv[2] print(""" /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM """) enum_count = 0 # 1st enum is register enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 print(line) continue if enum_count == 1: if line.strip() == '};': print(line) # done with first enum break else: # enum items print(" %s_%s" %(arch, line.strip())) # 2nd enum is register class enum_count = 0 print("\n// Register classes") for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 if enum_count == 2: print(line) continue if enum_count == 2: if line.strip() == '};': # done with 2nd enum print(line.strip()) break else: # enum items print(" %s_%s" %(arch, line.strip())) if arch.upper() == 'ARM': # 3rd enum is Subregister indices enum_count = 0 print("\n// Subregister indices") for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 if enum_count == 3: print(line) continue if enum_count == 3: if line.strip() == '};': # done with 2nd enum print(line.strip()) break else: # enum items print(" %s_%s" %(arch, line.strip())) if arch.upper() == 'AARCH64': # 3rd enum is Register alternate name indices enum_count = 0 print("\n// Register alternate name indices") for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 if enum_count == 3: print(line) continue if enum_count == 3: if line.strip() == '};': # done with 2nd enum print(line.strip()) break else: # enum items print(" %s_%s" %(arch, line.strip())) # 4th enum is Subregister indices enum_count = 0 print("\n// Subregister indices") for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': enum_count += 1 if enum_count == 4: print(line) continue if enum_count == 4: if line.strip() == '};': # done with 2nd enum print(line.strip()) break else: # enum items print(" %s_%s" %(arch, line.strip())) # end of enum print("") print("#endif // GET_REGINFO_ENUM") print(""" #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC """) # extract RegDiffLists finding_struct = True for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if arch + 'RegDiffLists' in line: finding_struct = False print("static const MCPhysReg " + arch + "RegDiffLists[] = {") continue if finding_struct: continue else: print(line) if line == '};': # done with this struct print("") break # extract SubRegIdxLists finding_struct = True for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if arch + 'SubRegIdxLists' in line: finding_struct = False print("static const uint16_t " + arch + "SubRegIdxLists[] = {") continue if finding_struct: continue else: print(line) if line == '};': # done with this struct print("") break # extract RegDesc finding_struct = True for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if arch + 'RegDesc' in line: finding_struct = False print("static const MCRegisterDesc " + arch + "RegDesc[] = {") continue if finding_struct: continue else: print(line) if line == '};': # done with this struct print("") break # extract register classes finding_struct = True for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'Register classes' in line and 'namespace' in line: finding_struct = False continue if finding_struct: continue else: if 'const' in line: line2 = line.replace('const', 'static const') print(line2) elif '::' in line: line2 = line.replace('::', '_') print(line2) elif 'end anonymous namespace' in line: # done with this struct break else: print(line) print("\n") # extract MCRegisterClasses finding_struct = True for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'MCRegisterClass ' + arch + 'MCRegisterClasses[] = {' in line: finding_struct = False print("static const MCRegisterClass " + arch + "MCRegisterClasses[] = {") continue if finding_struct: continue else: if line == '};': # done with this struct print('};\n') break elif '::' in line: line = line.replace('::', '_') # { GR8, GR8Bits, 130, 20, sizeof(GR8Bits), X86_GR8RegClassID, 1, 1, 1, 1 }, tmp = line.split(',') print(" %s, %s, %s }," %(tmp[0].strip(), tmp[1].strip(), tmp[4].strip())) print("#endif // GET_REGINFO_MC_DESC") capstone-sys-0.15.0/capstone/suite/synctools/strinforeduce/Makefile000064400000000000000000000003010072674642500236770ustar 00000000000000all: full reduce full: g++ strinforeduce.cpp -o strinforeduce reduce: g++ -DCAPSTONE_X86_REDUCE strinforeduce.cpp -o strinforeduce_reduce clean: rm -rf strinforeduce strinforeduce_reduce capstone-sys-0.15.0/capstone/suite/synctools/strinforeduce/README000064400000000000000000000006450072674642500231320ustar 00000000000000- Run instroinfo2.py on X86GenInstrInfo.inc & X86GenInstrInfo_reduce.inc $ ./instrinfo2.py ../tablegen/X86GenInstrInfo.inc > X86GenInstrInfo.inc $ ./instrinfo2.py ../tablegen/X86GenInstrInfo_reduce.inc > X86GenInstrInfo_reduce.inc - Compile $ make - Run $ ./strinforeduce > X86Lookup16.inc $ ./strinforeduce_reduce > X86Lookup16_reduce.inc - Then copy X86Lookup16*.inc to Capstone dir arch/X86/ capstone-sys-0.15.0/capstone/suite/synctools/strinforeduce/instrinfo2.py000075500000000000000000000021210072674642500247130ustar 00000000000000#!/usr/bin/python # convert LLVM GenInstrInfo.inc for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) count = 0 last_line = None f = open(sys.argv[1]) lines = f.readlines() f.close() # 1st enum is register enum for line in lines: line = line.rstrip() # skip all MCPhysReg line if 'static const MCPhysReg ' in line: continue # skip all MCOperandInfo line if 'static const MCOperandInfo ' in line: continue # skip InitX86MCInstrInfo() if 'static inline void InitX86MCInstrInfo' in line: continue if 'II->InitMCInstrInfo' in line: last_line = line continue # skip the next line after II->InitMCInstrInfo if last_line: last_line = None continue if 'extern const MCInstrDesc ' in line: count += 1 continue if count == 1: if line == '};': # done with first enum count += 1 continue else: print(line) capstone-sys-0.15.0/capstone/suite/synctools/strinforeduce/strinforeduce.cpp000064400000000000000000000107550072674642500256350ustar 00000000000000// By Martin Tofall, Obsidium Software #define GET_INSTRINFO_ENUM #define GET_INSTRINFO_MC_DESC #ifdef CAPSTONE_X86_REDUCE #include "X86GenInstrInfo_reduce.inc" #else #include "X86GenInstrInfo.inc" #endif #include #include #include #include static const char *x86DisassemblerGetInstrName(unsigned Opcode) { return &llvm::X86InstrNameData[llvm::X86InstrNameIndices[Opcode]]; } static bool is16BitEquivalent(const char* orig, const char* equiv) { size_t i; for (i = 0;; i++) { if (orig[i] == '\0' && equiv[i] == '\0') return true; if (orig[i] == '\0' || equiv[i] == '\0') return false; if (orig[i] != equiv[i]) { if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W') continue; if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1') continue; if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6') continue; return false; } } } // static const char *header = "#ifdef GET_INSTRINFO_MC_DESC\n#undef GET_INSTRINFO_MC_DESC\n\n" static const char *header = "typedef struct x86_op_id_pair {\n"\ "\tuint16_t first;\n" \ "\tuint16_t second;\n" \ "} x86_op_id_pair;\n\n" \ "static const x86_op_id_pair x86_16_bit_eq_tbl[] = {\n"; static const char *footer = "};\n\n"; static const char *header_lookup = "static const uint16_t x86_16_bit_eq_lookup[] = {\n"; //static const char *footer_lookup = "};\n\n#endif\n"; static const char *footer_lookup = "};\n"; static bool is16BitEquivalent_old(unsigned id1, unsigned id2) { return (is16BitEquivalent(x86DisassemblerGetInstrName(id1), x86DisassemblerGetInstrName(id2))) != false; } //#include "reduced.h" #if 0 static bool is16BitEquivalent_new(unsigned orig, unsigned equiv) { size_t i; uint16_t idx; if (orig == equiv) return true; // emulate old behaviour if ((idx = x86_16_bit_eq_lookup[orig]) != 0) { for (i = idx - 1; x86_16_bit_eq_tbl[i].first == orig; ++i) { if (x86_16_bit_eq_tbl[i].second == equiv) return true; } } return false; } #endif int main() { size_t size_names = sizeof(llvm::X86InstrNameData); size_t size_indices = sizeof(llvm::X86InstrNameIndices); size_t size_total = size_names + size_indices; #if 1 printf("%s", header); size_t eq_count = 0; std::string str_lookup; bool got_i = false; for (size_t i = 0; i < llvm::X86::INSTRUCTION_LIST_END; ++i) { const char *name1 = x86DisassemblerGetInstrName(i); for (size_t j = 0; j < llvm::X86::INSTRUCTION_LIST_END; ++j) { const char *name2 = x86DisassemblerGetInstrName(j); if (i != j && is16BitEquivalent(name1, name2) != false) { //printf("Found equivalent %d and %d\n", i, j); printf("\t{ %zu, %zu },\n", i, j); if (!got_i) { char buf[16]; sprintf(buf, "\t%zu,\n", eq_count + 1); str_lookup += buf; got_i = true; } ++eq_count; } } if (!got_i) { //char buf[32]; //sprintf(buf, "\t0, //%d\n", i); //str_lookup += buf; str_lookup += "\t0,\n"; } // reset got_i got_i = false; } printf("%s", footer); printf("%s", header_lookup); printf("%s", str_lookup.c_str()); printf("%s", footer_lookup); // printf("%zu equivalents total\n", eq_count); // size_t size_new = eq_count * 4 + llvm::X86::INSTRUCTION_LIST_END * 2; // printf("before: %zu, after: %zu, %zu bytes saved\n", size_total, size_new, size_total - size_new); #endif #if 0 for (size_t i = 0; i < llvm::X86::INSTRUCTION_LIST_END; ++i) { for (size_t j = 0; j < llvm::X86::INSTRUCTION_LIST_END; ++j) { if (is16BitEquivalent_new(i, j) != is16BitEquivalent_old(i, j)) { bool old_result = is16BitEquivalent_old(i, j); bool new_result = is16BitEquivalent_new(i, j); printf("ERROR!\n"); } } } #endif #if 0 static const size_t BENCH_LOOPS = 50; size_t eq_count = 0; DWORD time = GetTickCount(); for (size_t l = 0; l < BENCH_LOOPS; ++l) { for (size_t i = 0; i < llvm::X86::INSTRUCTION_LIST_END; ++i) { for (size_t j = 0; j < llvm::X86::INSTRUCTION_LIST_END; ++j) if (is16BitEquivalent_new(i, j)) ++eq_count; } } time = GetTickCount() - time; printf("new: %f msecs\n", static_cast(time) / static_cast(BENCH_LOOPS)); eq_count = 0; time = GetTickCount(); for (size_t l = 0; l < BENCH_LOOPS; ++l) { for (size_t i = 0; i < llvm::X86::INSTRUCTION_LIST_END; ++i) { for (size_t j = 0; j < llvm::X86::INSTRUCTION_LIST_END; ++j) if (is16BitEquivalent_old(i, j)) ++eq_count; } } time = GetTickCount() - time; printf("old: %f msecs\n", static_cast(time) / static_cast(BENCH_LOOPS)); #endif return 0; } capstone-sys-0.15.0/capstone/suite/synctools/subtargetinfo.py000075500000000000000000000026550072674642500226320ustar 00000000000000#!/usr/bin/python # convert LLVM GenSubtargetInfo.inc for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() arch = sys.argv[2] print(""" /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ """) count = 0 # 1st enum is subtarget enum for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum {': count += 1 print(line) continue if count == 1: if line.strip() == '};': # done with first enum break else: # enum items print(" %s_%s" %(arch, line.strip())) print('};\n') capstone-sys-0.15.0/capstone/suite/synctools/systemoperand.py000075500000000000000000000564170072674642500226600ustar 00000000000000#!/usr/bin/python # convert LLVM GenSystemOperands.inc of AArch64 for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() f1 = open(sys.argv[2], 'w+') f2 = open(sys.argv[3], 'w+') f1.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f1.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f1.write("\n") f2.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n") f2.write("/* By Nguyen Anh Quynh , 2013-2019 */\n") f2.write("\n") # extract PStateValues enum count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum PStateValues {': count += 1 f2.write(line.strip() + "\n") continue line = line.strip() if count == 1: if line == '};': # done with first enum f2.write(line + "\n") f2.write("\n") break else: # skip pseudo instructions f2.write(" AArch64PState_%s\n" %(line)) def print_line(line): f1.write(line + "\n") # extract ExactFPImmValues enum count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum ExactFPImmValues {': count += 1 f2.write(line.strip() + "\n") continue line = line.strip() if count == 1: if line == '};': # done with first enum f2.write(line + "\n") f2.write("\n") break else: # skip pseudo instructions f2.write(" AArch64ExactFPImm_%s\n" %(line)) # extract ATsList[] count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const AT ATsList[] = {': count += 1 print_line('static const AT ATsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) c += 1 # lookupATByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupATByEncoding' in line and '{' in line: count += 1 print_line('const AT *lookupATByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &ATsList[Index[i].index]; } """) # extract DBsList[] count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const DB DBsList[] = {': count += 1 print_line('static const DB DBsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') print_line(" %s" %(line)) # lookupDBByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupDBByEncoding' in line and '{' in line: count += 1 print_line('const DB *lookupDBByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &DBsList[Index[i].index]; } """) # extract DCsList[] count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const DC DCsList[] = {': count += 1 print_line('static const DC DCsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) c += 1 # lookupDCByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupDCByEncoding' in line and '{' in line: count += 1 print_line('const DC *lookupDCByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &DCsList[Index[i].index]; } """) # extract ICsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const IC ICsList[] = {': count += 1 print_line('static const IC ICsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') #tmp = line.split(',') #print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) print_line(" %s" %line.lower()) c += 1 # lookupICByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupICByEncoding' in line and '{' in line: count += 1 print_line('const IC *lookupICByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &ICsList[Index[i].index]; } """) # extract TLBIsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const TLBI TLBIsList[] = {': count += 1 print_line('static const TLBI TLBIsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s, %s }, // %u" %(tmp[0].lower(), tmp[1], tmp[2], c)) #print_line(" %s" %line.lower()) c += 1 # lookupTLBIByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupTLBIByEncoding' in line and '{' in line: count += 1 print_line('const TLBI *lookupTLBIByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &TLBIsList[Index[i].index]; } """) # extract SVEPRFMsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const SVEPRFM SVEPRFMsList[] = {': count += 1 print_line('static const SVEPRFM SVEPRFMsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) #print_line(" %s" %line.lower()) c += 1 # lookupSVEPRFMByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupSVEPRFMByEncoding' in line and '{' in line: count += 1 print_line('const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &SVEPRFMsList[Index[i].index]; } """) # extract PRFMsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const PRFM PRFMsList[] = {': count += 1 print_line('static const PRFM PRFMsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') #tmp = line.split(',') #print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) print_line(" %s" %line.lower()) c += 1 # lookupPRFMByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupPRFMByEncoding' in line and '{' in line: count += 1 print_line('const PRFM *lookupPRFMByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &PRFMsList[Index[i].index]; } """) # extract PSBsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const PSB PSBsList[] = {': count += 1 print_line('static const PSB PSBsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') #tmp = line.split(',') #print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) print_line(" %s" %line.lower()) c += 1 # lookupPSBByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupPSBByEncoding' in line and '{' in line: count += 1 print_line('const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &PSBsList[Index[i].index]; } """) # extract ISBsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const ISB ISBsList[] = {': count += 1 print_line('static const ISB ISBsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') #tmp = line.split(',') #print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) print_line(" %s" %line.lower()) c += 1 # lookupISBByName count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupISBByEncoding' in line and '{' in line: count += 1 print_line('const ISB *lookupISBByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &ISBsList[Index[i].index]; } """) # extract TSBsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const TSB TSBsList[] = {': count += 1 print_line('static const TSB TSBsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) #print_line(" %s" %line.lower()) c += 1 # lookupTSBByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupTSBByEncoding' in line and '{' in line: count += 1 print_line('const TSB *lookupTSBByEncoding(uint16_t Encoding)\n{') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" if (Encoding >= ARR_SIZE(TSBsList)) return NULL; else return &TSBsList[Index[Encoding].index]; } """) # extract SysRegsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const SysReg SysRegsList[] = {': count += 1 print_line('static const SysReg SysRegsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s, %s, %s }, // %u" %(tmp[0].lower(), tmp[1], tmp[2], tmp[3], c)) #print_line(" %s" %line.lower()) c += 1 # lookupSysRegByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupSysRegByEncoding' in line and '{' in line: count += 1 print_line('const SysReg *lookupSysRegByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &SysRegsList[Index[i].index]; } """) # extract PStatesList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const PState PStatesList[] = {': count += 1 print_line('static const PState PStatesList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) #print_line(" %s" %line.lower()) c += 1 # lookupPStateByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupPStateByEncoding' in line and '{' in line: count += 1 print_line('const PState *lookupPStateByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &PStatesList[Index[i].index]; } """) # extract SVEPREDPATsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const SVEPREDPAT SVEPREDPATsList[] = {': count += 1 print_line('static const SVEPREDPAT SVEPREDPATsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') #print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) print_line(" %s" %line.lower()) c += 1 # lookupSVEPREDPATByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupSVEPREDPATByEncoding' in line and '{' in line: count += 1 print_line('const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding)\n{') print_line(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); if (i == -1) return NULL; else return &SVEPREDPATsList[Index[i].index]; } """) # extract ExactFPImmsList count = 0 c = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'const ExactFPImm ExactFPImmsList[] = {': count += 1 print_line('static const ExactFPImm ExactFPImmsList[] = {') continue line = line.strip() if count == 1: if line == '};': # done with first enum print_line('};\n') break else: # skip pseudo instructions line = line.replace('::', '_') #line = line.replace('{}', '{ 0 }') line = line.replace('{}', '') tmp = line.split(',') #print_line(" %s, %s }, // %u" %(tmp[0].lower(), tmp[1], c)) print_line(" %s" %line.lower()) c += 1 # lookupExactFPImmByEnum count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupExactFPImmByEnum' in line and '{' in line: count += 1 print_line('const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding)\n{') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print_line(line) break else: # enum items print_line(line) print_line(""" if (Encoding >= ARR_SIZE(ExactFPImmsList)) return NULL; else return &ExactFPImmsList[Index[Encoding].index]; } """) capstone-sys-0.15.0/capstone/suite/synctools/systemregister.py000075500000000000000000000124400072674642500230400ustar 00000000000000#!/usr/bin/python # convert LLVM GenSystemRegister.inc for Capstone disassembler. # by Nguyen Anh Quynh, 2019 import sys if len(sys.argv) == 1: print("Syntax: %s " %sys.argv[0]) sys.exit(1) f = open(sys.argv[1]) lines = f.readlines() f.close() #arch = sys.argv[2].upper() print(""" /* Capstone Disassembly Engine, http://www.capstone-engine.org */ /* By Nguyen Anh Quynh , 2013-2019 */ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* GenSystemRegister Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ """) # extract BankedRegValues enum count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if line.strip() == 'enum BankedRegValues {': count += 1 print(line.strip()) continue line = line.strip() if count == 1: if line == '};': # done with first enum break else: # skip pseudo instructions print("\t%s" %(line)) print('};\n') # extract MClassSysRegsList count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'MClassSysRegsList[]' in line: count += 1 print('static const MClassSysReg MClassSysRegsList[] = {') continue if count == 1: if line.strip() == '};': # done with first enum break else: # enum items # { "apsr_g", 0x400, 0x0, 0x400, {ARM::FeatureDSP} }, // 0 line2 = line.replace('::', '_') sysreg = line2[line2.index('"') + 1 : line2.index('",')] tmp = line2.split(',') print("%s, ARM_SYSREG_%s%s" %(line2[:line2.index('",') + 1], sysreg.upper(), line2[line2.index('",') + 1 :])) print('};\n') # extract BankedRegsList count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'BankedRegsList[]' in line: count += 1 print('static const BankedReg BankedRegsList[] = {') continue if count == 1: if line.strip() == '};': # done with first enum break else: # enum items line2 = line.replace('::', '_') sysreg = line2[line2.index('"') + 1 : line2.index('",')] tmp = line2.split(',') print("%s, ARM_SYSREG_%s%s" %(line2[:line2.index('",') + 1], sysreg.upper(), line2[line2.index('",') + 1 :])) print('};\n') # lookupMClassSysRegByM2M3Encoding8 count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupMClassSysRegByM2M3Encoding8' in line and '{' in line: count += 1 print('const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)\n{') print(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print(line) break else: # enum items print(line) print(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else return &MClassSysRegsList[Index[i].index]; } """) # lookupMClassSysRegByM1Encoding12 count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupMClassSysRegByM1Encoding12' in line and '{' in line: count += 1 print('const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)\n{') print(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print(line) break else: # enum items print(line) print(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else return &MClassSysRegsList[Index[i].index]; } """) # lookupBankedRegByEncoding count = 0 for line in lines: line = line.rstrip() if len(line.strip()) == 0: continue if 'lookupBankedRegByEncoding' in line and '{' in line: count += 1 print('const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)\n{') print(' unsigned int i;') continue if count == 1 and 'IndexType Index[] = {' in line: count += 1 if count == 2: if line.strip() == '};': # done with array, or this function? print(line) break else: # enum items print(line) print(""" i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else return &BankedRegsList[Index[i].index]; } """) capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64.td000064400000000000000000000644730072674642500240010ustar 00000000000000//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Target-independent interfaces which we are implementing. //===----------------------------------------------------------------------===// include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // AArch64 Subtarget features. // def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", "Enable ARMv8 FP">; def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; def FeatureSM4 : SubtargetFeature< "sm4", "HasSM4", "true", "Enable SM3 and SM4 support", [FeatureNEON]>; def FeatureSHA2 : SubtargetFeature< "sha2", "HasSHA2", "true", "Enable SHA1 and SHA256 support", [FeatureNEON]>; def FeatureSHA3 : SubtargetFeature< "sha3", "HasSHA3", "true", "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; def FeatureAES : SubtargetFeature< "aes", "HasAES", "true", "Enable AES support", [FeatureNEON]>; // Crypto has been split up and any combination is now valid (see the // crypto defintions above). Also, crypto is now context sensitive: // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. // Therefore, we rely on Clang, the user interacing tool, to pass on the // appropriate crypto options. But here in the backend, crypto has very little // meaning anymore. We kept the Crypto defintion here for backward // compatibility, and now imply features SHA2 and AES, which was the // "traditional" meaning of Crypto. def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable ARMv8 CRC-32 checksum instructions">; def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", "Enable ARMv8 PMUv3 Performance Monitors extension">; def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", "Full FP16", [FeatureFPARMv8]>; def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", "Enable Statistical Profiling extension">; def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", "Enable Scalable Vector Extension (SVE) instructions">; /// Cyclone has register move instructions which are "free". def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", "Has zero-cycle register moves">; /// Cyclone has instructions which zero registers for "free". def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", "Has zero-cycle zeroing instructions">; /// ... but the floating-point version doesn't quite work in rare cases on older /// CPUs. def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", "HasZeroCycleZeroingFPWorkaround", "true", "The zero-cycle floating-point zeroing instruction has a bug">; def FeatureStrictAlign : SubtargetFeature<"strict-align", "StrictAlign", "true", "Disallow all unaligned memory " "access">; def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true", "Reserve X18, making it unavailable " "as a GPR">; def FeatureReserveX20 : SubtargetFeature<"reserve-x20", "ReserveX20", "true", "Reserve X20, making it unavailable " "as a GPR">; def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", "Use alias analysis during codegen">; def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", "true", "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; def FeaturePredictableSelectIsExpensive : SubtargetFeature< "predictable-select-expensive", "PredictableSelectIsExpensive", "true", "Prefer likely predicted branches over selects">; def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", "CustomAsCheapAsMove", "true", "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">; def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", "ExynosAsCheapAsMove", "true", "Use Exynos specific code in TargetInstrInfo::isAsCheapAsAMove()", [FeatureCustomCheapAsMoveHandling]>; def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", "true", "STR of Q register with register offset is slow">; def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", "true", "Use alternative pattern for sextload convert to f32">; def FeatureArithmeticBccFusion : SubtargetFeature< "arith-bcc-fusion", "HasArithmeticBccFusion", "true", "CPU fuses arithmetic+bcc operations">; def FeatureArithmeticCbzFusion : SubtargetFeature< "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", "CPU fuses arithmetic + cbz/cbnz operations">; def FeatureFuseAddress : SubtargetFeature< "fuse-address", "HasFuseAddress", "true", "CPU fuses address generation and memory operations">; def FeatureFuseAES : SubtargetFeature< "fuse-aes", "HasFuseAES", "true", "CPU fuses AES crypto operations">; def FeatureFuseCCSelect : SubtargetFeature< "fuse-csel", "HasFuseCCSelect", "true", "CPU fuses conditional select operations">; def FeatureFuseLiterals : SubtargetFeature< "fuse-literals", "HasFuseLiterals", "true", "CPU fuses literal generation operations">; def FeatureDisableLatencySchedHeuristic : SubtargetFeature< "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", "Disable latency scheduling heuristic">; def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", "Enable support for RCPC extension">; def FeatureUseRSqrt : SubtargetFeature< "use-reciprocal-square-root", "UseRSqrt", "true", "Use the reciprocal square root approximation">; def FeatureDotProd : SubtargetFeature< "dotprod", "HasDotProd", "true", "Enable dot product support">; def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", "NegativeImmediates", "false", "Convert immediates and instructions " "to their negated or complemented " "equivalent when the immediate does " "not fit in the encoding.">; def FeatureLSLFast : SubtargetFeature< "lsl-fast", "HasLSLFast", "true", "CPU has a fastpath logical shift of up to 3 places">; def FeatureAggressiveFMA : SubtargetFeature<"aggressive-fma", "HasAggressiveFMA", "true", "Enable Aggressive FMA for floating-point.">; //===----------------------------------------------------------------------===// // Architectures. // def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>; def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>; def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// include "AArch64RegisterInfo.td" include "AArch64RegisterBanks.td" include "AArch64CallingConvention.td" //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// include "AArch64Schedule.td" include "AArch64InstrInfo.td" def AArch64InstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Named operands for MRS/MSR/TLBI/... //===----------------------------------------------------------------------===// include "AArch64SystemOperands.td" //===----------------------------------------------------------------------===// // AArch64 Processors supported. // include "AArch64SchedA53.td" include "AArch64SchedA57.td" include "AArch64SchedCyclone.td" include "AArch64SchedFalkor.td" include "AArch64SchedKryo.td" include "AArch64SchedExynosM1.td" include "AArch64SchedExynosM3.td" include "AArch64SchedThunderX.td" include "AArch64SchedThunderX2T99.td" def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeaturePerfMon ]>; def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [ FeatureBalanceFPOps, FeatureCRC, FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeatureUseAA ]>; def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", "Cortex-A55 ARM processors", [ HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon ]>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", [ FeatureBalanceFPOps, FeatureCRC, FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureFuseLiterals, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive ]>; def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon ]>; def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon ]>; def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", "Cortex-A75 ARM processors", [ HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon ]>; // Note that cyclone does not fuse AES instructions, but newer apple chips do // perform the fusion and cyclone is used by default when targetting apple OSes. def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", "Cyclone", [ FeatureAlternateSExtLoadCVTF32Pattern, FeatureArithmeticBccFusion, FeatureArithmeticCbzFusion, FeatureCrypto, FeatureDisableLatencySchedHeuristic, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon, FeatureZCRegMove, FeatureZCZeroing, FeatureZCZeroingFPWorkaround ]>; def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", "Samsung Exynos-M1 processors", [FeatureSlowPaired128, FeatureCRC, FeatureCrypto, FeatureExynosCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeatureSlowMisaligned128Store, FeatureUseRSqrt, FeatureZCZeroing]>; def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1", "Samsung Exynos-M2 processors", [FeatureSlowPaired128, FeatureCRC, FeatureCrypto, FeatureExynosCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeatureSlowMisaligned128Store, FeatureZCZeroing]>; def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", "Samsung Exynos-M3 processors", [FeatureCRC, FeatureCrypto, FeatureExynosCheapAsMoveHandling, FeatureFPARMv8, FeatureFuseAddress, FeatureFuseAES, FeatureFuseCCSelect, FeatureFuseLiterals, FeatureLSLFast, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureZCZeroing]>; def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", "Qualcomm Kryo processors", [ FeatureCRC, FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureZCZeroing, FeatureLSLFast ]>; def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", "Qualcomm Falkor processors", [ FeatureCRC, FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureRDM, FeatureZCZeroing, FeatureLSLFast, FeatureSlowSTRQro ]>; def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", "Qualcomm Saphira processors", [ FeatureCrypto, FeatureCustomCheapAsMoveHandling, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureZCZeroing, FeatureLSLFast, HasV8_3aOps]>; def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", "ThunderX2T99", "Cavium ThunderX2 processors", [ FeatureAggressiveFMA, FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeatureArithmeticBccFusion, FeatureNEON, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureLSE, HasV8_1aOps]>; def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", "Cavium ThunderX processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureNEON]>; def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", "ThunderXT88", "Cavium ThunderX processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureNEON]>; def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", "ThunderXT81", "Cavium ThunderX processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureNEON]>; def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", "ThunderXT83", "Cavium ThunderX processors", [ FeatureCRC, FeatureCrypto, FeatureFPARMv8, FeaturePerfMon, FeaturePostRAScheduler, FeaturePredictableSelectIsExpensive, FeatureNEON]>; def : ProcessorModel<"generic", NoSchedModel, [ FeatureFPARMv8, FeatureFuseAES, FeatureNEON, FeaturePerfMon, FeaturePostRAScheduler ]>; // FIXME: Cortex-A35 and Cortex-A55 are currently modeled as a Cortex-A53. def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; // FIXME: Cortex-A72, Cortex-A73 and Cortex-A75 are currently modeled as a Cortex-A57. def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; def : ProcessorModel<"exynos-m4", ExynosM3Model, [ProcExynosM3]>; def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; // Cavium ThunderX/ThunderX T8X Processors def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; // Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; //===----------------------------------------------------------------------===// // Assembly parser //===----------------------------------------------------------------------===// def GenericAsmParserVariant : AsmParserVariant { int Variant = 0; string Name = "generic"; string BreakCharacters = "."; string TokenizingCharacters = "[]*!/"; } def AppleAsmParserVariant : AsmParserVariant { int Variant = 1; string Name = "apple-neon"; string BreakCharacters = "."; string TokenizingCharacters = "[]*!/"; } //===----------------------------------------------------------------------===// // Assembly printer //===----------------------------------------------------------------------===// // AArch64 Uses the MC printer for asm output, so make sure the TableGen // AsmWriter bits get associated with the correct class. def GenericAsmWriter : AsmWriter { string AsmWriterClassName = "InstPrinter"; int PassSubtarget = 1; int Variant = 0; bit isMCAsmWriter = 1; } def AppleAsmWriter : AsmWriter { let AsmWriterClassName = "AppleInstPrinter"; int PassSubtarget = 1; int Variant = 1; int isMCAsmWriter = 1; } //===----------------------------------------------------------------------===// // Target Declaration //===----------------------------------------------------------------------===// def AArch64 : Target { let InstructionSet = AArch64InstrInfo; let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; let AllowRegisterRenaming = 1; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64CallingConvention.td000064400000000000000000000422150072674642500273240ustar 00000000000000//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This describes the calling conventions for AArch64 architecture. // //===----------------------------------------------------------------------===// /// CCIfAlign - Match of the original alignment of the arg class CCIfAlign : CCIf; /// CCIfBigEndian - Match only if we're in big endian mode. class CCIfBigEndian : CCIf<"State.getMachineFunction().getDataLayout().isBigEndian()", A>; //===----------------------------------------------------------------------===// // ARM AAPCS64 Calling Convention //===----------------------------------------------------------------------===// def CC_AArch64_AAPCS : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, CCIfType<[v2f64, v4f32], CCBitConvertToType>, // Big endian vectors must be passed as if they were 1-element vectors so that // their lanes are in a consistent order. CCIfBigEndian>>, CCIfBigEndian>>, // An SRet is passed in X8, not X0 like a normal pointer parameter. CCIfSRet>>, // Put ByVal arguments directly on the stack. Minimum size and alignment of a // slot is 64-bit. CCIfByVal>, // The 'nest' parameter, if any, is passed in X18. // Darwin uses X18 as the platform register and hence 'nest' isn't currently // supported there. CCIfNest>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is passed in X21. CCIfSwiftError>>, CCIfConsecutiveRegs>, // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, // up to eight each of GPR and FPR. CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], [X0, X1, X2, X3, X4, X5, X6, X7]>>, // i128 is split to two i64s, we can't fit half to register X7. CCIfType<[i64], CCIfSplit>>, // i128 is split to two i64s, and its stack alignment is 16 bytes. CCIfType<[i64], CCIfSplit>>, CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], [W0, W1, W2, W3, W4, W5, W6, W7]>>, CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, // If more than will fit in registers, pass them on the stack instead. CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>, CCIfType<[i32, f32], CCAssignToStack<8, 8>>, CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], CCAssignToStack<8, 8>>, CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], CCAssignToStack<16, 16>> ]>; def RetCC_AArch64_AAPCS : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, CCIfType<[v2f64, v4f32], CCBitConvertToType>, CCIfSwiftError>>, // Big endian vectors must be passed as if they were 1-element vectors so that // their lanes are in a consistent order. CCIfBigEndian>>, CCIfBigEndian>>, CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], [X0, X1, X2, X3, X4, X5, X6, X7]>>, CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], [W0, W1, W2, W3, W4, W5, W6, W7]>>, CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> ]>; // Vararg functions on windows pass floats in integer registers def CC_AArch64_Win64_VarArg : CallingConv<[ CCIfType<[f16, f32], CCPromoteToType>, CCIfType<[f64], CCBitConvertToType>, CCDelegateTo ]>; // Darwin uses a calling convention which differs in only two ways // from the standard one at this level: // + i128s (i.e. split i64s) don't need even registers. // + Stack slots are sized as needed rather than being at least 64-bit. def CC_AArch64_DarwinPCS : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, CCIfType<[v2f64, v4f32, f128], CCBitConvertToType>, // An SRet is passed in X8, not X0 like a normal pointer parameter. CCIfSRet>>, // Put ByVal arguments directly on the stack. Minimum size and alignment of a // slot is 64-bit. CCIfByVal>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is passed in X21. CCIfSwiftError>>, CCIfConsecutiveRegs>, // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers, // up to eight each of GPR and FPR. CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], [X0, X1, X2, X3, X4, X5, X6, X7]>>, // i128 is split to two i64s, we can't fit half to register X7. CCIfType<[i64], CCIfSplit>>, // i128 is split to two i64s, and its stack alignment is 16 bytes. CCIfType<[i64], CCIfSplit>>, CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], [W0, W1, W2, W3, W4, W5, W6, W7]>>, CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, // If more than will fit in registers, pass them on the stack instead. CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>, CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16", CCAssignToStack<2, 2>>, CCIfType<[i32, f32], CCAssignToStack<4, 4>>, CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], CCAssignToStack<8, 8>>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], CCAssignToStack<16, 16>> ]>; def CC_AArch64_DarwinPCS_VarArg : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, CCIfType<[v2f64, v4f32, f128], CCBitConvertToType>, CCIfConsecutiveRegs>, // Handle all scalar types as either i64 or f64. CCIfType<[i8, i16, i32], CCPromoteToType>, CCIfType<[f16, f32], CCPromoteToType>, // Everything is on the stack. // i128 is split to two i64s, and its stack alignment is 16 bytes. CCIfType<[i64], CCIfSplit>>, CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], CCAssignToStack<8, 8>>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], CCAssignToStack<16, 16>> ]>; // The WebKit_JS calling convention only passes the first argument (the callee) // in register and the remaining arguments on stack. We allow 32bit stack slots, // so that WebKit can write partial values in the stack and define the other // 32bit quantity as undef. def CC_AArch64_WebKit_JS : CallingConv<[ // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0). CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>, CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>, // Pass the remaining arguments on the stack instead. CCIfType<[i32, f32], CCAssignToStack<4, 4>>, CCIfType<[i64, f64], CCAssignToStack<8, 8>> ]>; def RetCC_AArch64_WebKit_JS : CallingConv<[ CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], [X0, X1, X2, X3, X4, X5, X6, X7]>>, CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7], [W0, W1, W2, W3, W4, W5, W6, W7]>>, CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> ]>; //===----------------------------------------------------------------------===// // ARM64 Calling Convention for GHC //===----------------------------------------------------------------------===// // This calling convention is specific to the Glasgow Haskell Compiler. // The only documentation is the GHC source code, specifically the C header // file: // // https://github.com/ghc/ghc/blob/master/includes/stg/MachRegs.h // // which defines the registers for the Spineless Tagless G-Machine (STG) that // GHC uses to implement lazy evaluation. The generic STG machine has a set of // registers which are mapped to appropriate set of architecture specific // registers for each CPU architecture. // // The STG Machine is documented here: // // https://ghc.haskell.org/trac/ghc/wiki/Commentary/Compiler/GeneratedCode // // The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI // register mapping". def CC_AArch64_GHC : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, f128], CCBitConvertToType>, CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, CCIfType<[f32], CCAssignToReg<[S8, S9, S10, S11]>>, CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>, // Promote i8/i16/i32 arguments to i64. CCIfType<[i8, i16, i32], CCPromoteToType>, // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim CCIfType<[i64], CCAssignToReg<[X19, X20, X21, X22, X23, X24, X25, X26, X27, X28]>> ]>; // FIXME: LR is only callee-saved in the sense that *we* preserve it and are // presumably a callee to someone. External functions may not do so, but this // is currently safe since BL has LR as an implicit-def and what happens after a // tail call doesn't matter. // // It would be better to model its preservation semantics properly (create a // vreg on entry, use it in RET & tail call generation; make that vreg def if we // end up saving LR as part of a call frame). Watch this space... def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, D8, D9, D10, D11, D12, D13, D14, D15)>; // Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since // 'this' and the pointer return value are both passed in X0 in these cases, // this can be partially modelled by treating X0 as a callee-saved register; // only the resulting RegMask is used; the SaveList is ignored // // (For generic ARM 64-bit ABI code, clang will not generate constructors or // destructors with 'this' returns, so this RegMask will not be used in that // case) def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>; def CSR_AArch64_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>; // The function used by Darwin to obtain the address of a thread-local variable // guarantees more than a normal AAPCS function. x16 and x17 are used on the // fast path for calculation, but other registers except X0 (argument/return) // and LR (it is a call, after all) are preserved. def CSR_AArch64_TLS_Darwin : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17), FP, (sequence "Q%u", 0, 31))>; // We can only handle a register pair with adjacent registers, the register pair // should belong to the same class as well. Since the access function on the // fast path calls a function that follows CSR_AArch64_TLS_Darwin, // CSR_AArch64_CXX_TLS_Darwin should be a subset of CSR_AArch64_TLS_Darwin. def CSR_AArch64_CXX_TLS_Darwin : CalleeSavedRegs<(add CSR_AArch64_AAPCS, (sub (sequence "X%u", 1, 28), X15, X16, X17, X18), (sequence "D%u", 0, 31))>; // CSRs that are handled by prologue, epilogue. def CSR_AArch64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add LR, FP)>; // CSRs that are handled explicitly via copies. def CSR_AArch64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_AArch64_CXX_TLS_Darwin, LR, FP)>; // The ELF stub used for TLS-descriptor access saves every feasible // register. Only X0 and LR are clobbered. def CSR_AArch64_TLS_ELF : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP, (sequence "Q%u", 0, 31))>; def CSR_AArch64_AllRegs : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP, (sequence "X%u", 0, 28), FP, LR, SP, (sequence "B%u", 0, 31), (sequence "H%u", 0, 31), (sequence "S%u", 0, 31), (sequence "D%u", 0, 31), (sequence "Q%u", 0, 31))>; def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>; def CSR_AArch64_RT_MostRegs : CalleeSavedRegs<(add CSR_AArch64_AAPCS, (sequence "X%u", 9, 15))>; def CSR_AArch64_StackProbe_Windows : CalleeSavedRegs<(add (sequence "X%u", 0, 15), (sequence "X%u", 18, 28), FP, SP, (sequence "Q%u", 0, 31))>; // Variants of the standard calling conventions for shadow call stack. // These all preserve x18 in addition to any other registers. def CSR_AArch64_NoRegs_SCS : CalleeSavedRegs<(add CSR_AArch64_NoRegs, X18)>; def CSR_AArch64_AllRegs_SCS : CalleeSavedRegs<(add CSR_AArch64_AllRegs, X18)>; def CSR_AArch64_CXX_TLS_Darwin_SCS : CalleeSavedRegs<(add CSR_AArch64_CXX_TLS_Darwin, X18)>; def CSR_AArch64_AAPCS_SwiftError_SCS : CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>; def CSR_AArch64_RT_MostRegs_SCS : CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>; def CSR_AArch64_AAPCS_SCS : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64InstrAtomics.td000064400000000000000000000462250072674642500263340ustar 00000000000000//=- AArch64InstrAtomics.td - AArch64 Atomic codegen support -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // AArch64 Atomic operand code-gen constructs. // //===----------------------------------------------------------------------===// //===---------------------------------- // Atomic fences //===---------------------------------- let AddedComplexity = 15, Size = 0 in def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering), [(atomic_fence imm:$ordering, 0)]>, Sched<[]>; def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>; def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>; //===---------------------------------- // Atomic loads //===---------------------------------- // When they're actually atomic, only one addressing mode (GPR64sp) is // supported, but when they're relaxed and anything can be used, all the // standard modes would be valid and may give efficiency gains. // A atomic load operation that actually needs acquire semantics. class acquiring_load : PatFrag<(ops node:$ptr), (base node:$ptr)> { let IsAtomic = 1; let IsAtomicOrderingAcquireOrStronger = 1; } // An atomic load operation that does not need either acquire or release // semantics. class relaxed_load : PatFrag<(ops node:$ptr), (base node:$ptr)> { let IsAtomic = 1; let IsAtomicOrderingAcquireOrStronger = 0; } // 8-bit loads def : Pat<(acquiring_load GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>; def : Pat<(relaxed_load (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)), (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>; def : Pat<(relaxed_load (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)), (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>; def : Pat<(relaxed_load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(relaxed_load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; // 16-bit loads def : Pat<(acquiring_load GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>; def : Pat<(relaxed_load (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)), (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>; def : Pat<(relaxed_load (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)), (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>; def : Pat<(relaxed_load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>; def : Pat<(relaxed_load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)), (LDURHHi GPR64sp:$Rn, simm9:$offset)>; // 32-bit loads def : Pat<(acquiring_load GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>; def : Pat<(relaxed_load (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)), (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>; def : Pat<(relaxed_load (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)), (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>; def : Pat<(relaxed_load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)), (LDRWui GPR64sp:$Rn, uimm12s4:$offset)>; def : Pat<(relaxed_load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)), (LDURWi GPR64sp:$Rn, simm9:$offset)>; // 64-bit loads def : Pat<(acquiring_load GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>; def : Pat<(relaxed_load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)), (LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>; def : Pat<(relaxed_load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)), (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; def : Pat<(relaxed_load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (LDRXui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(relaxed_load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (LDURXi GPR64sp:$Rn, simm9:$offset)>; //===---------------------------------- // Atomic stores //===---------------------------------- // When they're actually atomic, only one addressing mode (GPR64sp) is // supported, but when they're relaxed and anything can be used, all the // standard modes would be valid and may give efficiency gains. // A store operation that actually needs release semantics. class releasing_store : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingReleaseOrStronger = 1; } // An atomic store operation that doesn't actually need to be atomic on AArch64. class relaxed_store : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val)> { let IsAtomic = 1; let IsAtomicOrderingReleaseOrStronger = 0; } // 8-bit stores def : Pat<(releasing_store GPR64sp:$ptr, GPR32:$val), (STLRB GPR32:$val, GPR64sp:$ptr)>; def : Pat<(relaxed_store (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend), GPR32:$val), (STRBBroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend)>; def : Pat<(relaxed_store (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend), GPR32:$val), (STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>; def : Pat<(relaxed_store (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset), GPR32:$val), (STRBBui GPR32:$val, GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(relaxed_store (am_unscaled8 GPR64sp:$Rn, simm9:$offset), GPR32:$val), (STURBBi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>; // 16-bit stores def : Pat<(releasing_store GPR64sp:$ptr, GPR32:$val), (STLRH GPR32:$val, GPR64sp:$ptr)>; def : Pat<(relaxed_store (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend), GPR32:$val), (STRHHroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>; def : Pat<(relaxed_store (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend), GPR32:$val), (STRHHroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>; def : Pat<(relaxed_store (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), GPR32:$val), (STRHHui GPR32:$val, GPR64sp:$Rn, uimm12s2:$offset)>; def : Pat<(relaxed_store (am_unscaled16 GPR64sp:$Rn, simm9:$offset), GPR32:$val), (STURHHi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>; // 32-bit stores def : Pat<(releasing_store GPR64sp:$ptr, GPR32:$val), (STLRW GPR32:$val, GPR64sp:$ptr)>; def : Pat<(relaxed_store (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend), GPR32:$val), (STRWroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>; def : Pat<(relaxed_store (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend), GPR32:$val), (STRWroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>; def : Pat<(relaxed_store (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset), GPR32:$val), (STRWui GPR32:$val, GPR64sp:$Rn, uimm12s4:$offset)>; def : Pat<(relaxed_store (am_unscaled32 GPR64sp:$Rn, simm9:$offset), GPR32:$val), (STURWi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>; // 64-bit stores def : Pat<(releasing_store GPR64sp:$ptr, GPR64:$val), (STLRX GPR64:$val, GPR64sp:$ptr)>; def : Pat<(relaxed_store (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend), GPR64:$val), (STRXroW GPR64:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>; def : Pat<(relaxed_store (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend), GPR64:$val), (STRXroX GPR64:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; def : Pat<(relaxed_store (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset), GPR64:$val), (STRXui GPR64:$val, GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(relaxed_store (am_unscaled64 GPR64sp:$Rn, simm9:$offset), GPR64:$val), (STURXi GPR64:$val, GPR64sp:$Rn, simm9:$offset)>; //===---------------------------------- // Low-level exclusive operations //===---------------------------------- // Load-exclusives. def ldxr_1 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def ldxr_2 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def ldxr_4 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i64; }]>; def : Pat<(ldxr_1 GPR64sp:$addr), (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_2 GPR64sp:$addr), (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_4 GPR64sp:$addr), (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_8 GPR64sp:$addr), (LDXRX GPR64sp:$addr)>; def : Pat<(and (ldxr_1 GPR64sp:$addr), 0xff), (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>; def : Pat<(and (ldxr_2 GPR64sp:$addr), 0xffff), (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>; def : Pat<(and (ldxr_4 GPR64sp:$addr), 0xffffffff), (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>; // Load-exclusives. def ldaxr_1 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def ldaxr_2 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def ldaxr_4 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def ldaxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i64; }]>; def : Pat<(ldaxr_1 GPR64sp:$addr), (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_2 GPR64sp:$addr), (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_4 GPR64sp:$addr), (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_8 GPR64sp:$addr), (LDAXRX GPR64sp:$addr)>; def : Pat<(and (ldaxr_1 GPR64sp:$addr), 0xff), (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>; def : Pat<(and (ldaxr_2 GPR64sp:$addr), 0xffff), (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>; def : Pat<(and (ldaxr_4 GPR64sp:$addr), 0xffffffff), (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>; // Store-exclusives. def stxr_1 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def stxr_2 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def stxr_4 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def stxr_8 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i64; }]>; def : Pat<(stxr_1 GPR64:$val, GPR64sp:$addr), (STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stxr_2 GPR64:$val, GPR64sp:$addr), (STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stxr_4 GPR64:$val, GPR64sp:$addr), (STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stxr_8 GPR64:$val, GPR64sp:$addr), (STXRX GPR64:$val, GPR64sp:$addr)>; def : Pat<(stxr_1 (zext (and GPR32:$val, 0xff)), GPR64sp:$addr), (STXRB GPR32:$val, GPR64sp:$addr)>; def : Pat<(stxr_2 (zext (and GPR32:$val, 0xffff)), GPR64sp:$addr), (STXRH GPR32:$val, GPR64sp:$addr)>; def : Pat<(stxr_4 (zext GPR32:$val), GPR64sp:$addr), (STXRW GPR32:$val, GPR64sp:$addr)>; def : Pat<(stxr_1 (and GPR64:$val, 0xff), GPR64sp:$addr), (STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stxr_2 (and GPR64:$val, 0xffff), GPR64sp:$addr), (STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stxr_4 (and GPR64:$val, 0xffffffff), GPR64sp:$addr), (STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; // Store-release-exclusives. def stlxr_1 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stlxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def stlxr_2 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stlxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def stlxr_4 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stlxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def stlxr_8 : PatFrag<(ops node:$val, node:$ptr), (int_aarch64_stlxr node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i64; }]>; def : Pat<(stlxr_1 GPR64:$val, GPR64sp:$addr), (STLXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stlxr_2 GPR64:$val, GPR64sp:$addr), (STLXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stlxr_4 GPR64:$val, GPR64sp:$addr), (STLXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stlxr_8 GPR64:$val, GPR64sp:$addr), (STLXRX GPR64:$val, GPR64sp:$addr)>; def : Pat<(stlxr_1 (zext (and GPR32:$val, 0xff)), GPR64sp:$addr), (STLXRB GPR32:$val, GPR64sp:$addr)>; def : Pat<(stlxr_2 (zext (and GPR32:$val, 0xffff)), GPR64sp:$addr), (STLXRH GPR32:$val, GPR64sp:$addr)>; def : Pat<(stlxr_4 (zext GPR32:$val), GPR64sp:$addr), (STLXRW GPR32:$val, GPR64sp:$addr)>; def : Pat<(stlxr_1 (and GPR64:$val, 0xff), GPR64sp:$addr), (STLXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stlxr_2 (and GPR64:$val, 0xffff), GPR64sp:$addr), (STLXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; def : Pat<(stlxr_4 (and GPR64:$val, 0xffffffff), GPR64sp:$addr), (STLXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>; // And clear exclusive. def : Pat<(int_aarch64_clrex), (CLREX 0xf)>; //===---------------------------------- // Atomic cmpxchg for -O0 //===---------------------------------- // The fast register allocator used during -O0 inserts spills to cover any VRegs // live across basic block boundaries. When this happens between an LDXR and an // STXR it can clear the exclusive monitor, causing all cmpxchg attempts to // fail. // Unfortunately, this means we have to have an alternative (expanded // post-regalloc) path for -O0 compilations. Fortunately this path can be // significantly more naive than the standard expansion: we conservatively // assume seq_cst, strong cmpxchg and omit clrex on failure. let Constraints = "@earlyclobber $Rd,@earlyclobber $scratch", mayLoad = 1, mayStore = 1 in { def CMP_SWAP_8 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch), (ins GPR64:$addr, GPR32:$desired, GPR32:$new), []>, Sched<[WriteAtomic]>; def CMP_SWAP_16 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch), (ins GPR64:$addr, GPR32:$desired, GPR32:$new), []>, Sched<[WriteAtomic]>; def CMP_SWAP_32 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch), (ins GPR64:$addr, GPR32:$desired, GPR32:$new), []>, Sched<[WriteAtomic]>; def CMP_SWAP_64 : Pseudo<(outs GPR64:$Rd, GPR32:$scratch), (ins GPR64:$addr, GPR64:$desired, GPR64:$new), []>, Sched<[WriteAtomic]>; } let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,@earlyclobber $scratch", mayLoad = 1, mayStore = 1 in def CMP_SWAP_128 : Pseudo<(outs GPR64:$RdLo, GPR64:$RdHi, GPR32:$scratch), (ins GPR64:$addr, GPR64:$desiredLo, GPR64:$desiredHi, GPR64:$newLo, GPR64:$newHi), []>, Sched<[WriteAtomic]>; // v8.1 Atomic instructions: let Predicates = [HasLSE] in { defm : LDOPregister_patterns<"LDADD", "atomic_load_add">; defm : LDOPregister_patterns<"LDSET", "atomic_load_or">; defm : LDOPregister_patterns<"LDEOR", "atomic_load_xor">; defm : LDOPregister_patterns<"LDCLR", "atomic_load_clr">; defm : LDOPregister_patterns<"LDSMAX", "atomic_load_max">; defm : LDOPregister_patterns<"LDSMIN", "atomic_load_min">; defm : LDOPregister_patterns<"LDUMAX", "atomic_load_umax">; defm : LDOPregister_patterns<"LDUMIN", "atomic_load_umin">; defm : LDOPregister_patterns<"SWP", "atomic_swap">; defm : CASregister_patterns<"CAS", "atomic_cmp_swap">; // These two patterns are only needed for global isel, selection dag isel // converts atomic load-sub into a sub and atomic load-add, and likewise for // and -> clr. defm : LDOPregister_patterns_mod<"LDADD", "atomic_load_sub", "SUB">; defm : LDOPregister_patterns_mod<"LDCLR", "atomic_load_and", "ORN">; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64InstrFormats.td000064400000000000000000014323200072674642500263440ustar 00000000000000//===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Describe AArch64 instructions format here // // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine // code emitter. class Format val> { bits<2> Value = val; } def PseudoFrm : Format<0>; def NormalFrm : Format<1>; // Do we need any others? // AArch64 Instruction Format class AArch64Inst : Instruction { field bits<32> Inst; // Instruction encoding. // Mask of bits that cause an encoding to be UNPREDICTABLE. // If a bit is set, then if the corresponding bit in the // target encoding differs from its value in the "Inst" field, // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). field bits<32> Unpredictable = 0; // SoftFail is the generic name for this field, but we alias it so // as to make it more obvious what it means in ARM-land. field bits<32> SoftFail = Unpredictable; let Namespace = "AArch64"; Format F = f; bits<2> Form = F.Value; let Pattern = []; let Constraints = cstr; } class InstSubst : InstAlias, Requires<[UseNegativeImmediates]>; // Pseudo instructions (don't have encoding information) class Pseudo pattern, string cstr = ""> : AArch64Inst { dag OutOperandList = oops; dag InOperandList = iops; let Pattern = pattern; let isCodeGenOnly = 1; } // Real instructions (have encoding information) class EncodedI pattern> : AArch64Inst { let Pattern = pattern; let Size = 4; } // Enum describing whether an instruction is // destructive in its first source operand. class DestructiveInstTypeEnum val> { bits<1> Value = val; } def NotDestructive : DestructiveInstTypeEnum<0>; def Destructive : DestructiveInstTypeEnum<1>; // Normal instructions class I pattern> : EncodedI { dag OutOperandList = oops; dag InOperandList = iops; let AsmString = !strconcat(asm, operands); // Destructive operations (SVE) DestructiveInstTypeEnum DestructiveInstType = NotDestructive; ElementSizeEnum ElementSize = ElementSizeB; let TSFlags{3} = DestructiveInstType.Value; let TSFlags{2-0} = ElementSize.Value; } class TriOpFrag : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>; class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; class UnOpFrag : PatFrag<(ops node:$LHS), res>; // Helper fragment for an extract of the high portion of a 128-bit vector. def extract_high_v16i8 : UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>; def extract_high_v8i16 : UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>; def extract_high_v4i32 : UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>; def extract_high_v2i64 : UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>; //===----------------------------------------------------------------------===// // Asm Operand Classes. // // Shifter operand for arithmetic shifted encodings. def ShifterOperand : AsmOperandClass { let Name = "Shifter"; } // Shifter operand for mov immediate encodings. def MovImm32ShifterOperand : AsmOperandClass { let SuperClasses = [ShifterOperand]; let Name = "MovImm32Shifter"; let RenderMethod = "addShifterOperands"; let DiagnosticType = "InvalidMovImm32Shift"; } def MovImm64ShifterOperand : AsmOperandClass { let SuperClasses = [ShifterOperand]; let Name = "MovImm64Shifter"; let RenderMethod = "addShifterOperands"; let DiagnosticType = "InvalidMovImm64Shift"; } // Shifter operand for arithmetic register shifted encodings. class ArithmeticShifterOperand : AsmOperandClass { let SuperClasses = [ShifterOperand]; let Name = "ArithmeticShifter" # width; let PredicateMethod = "isArithmeticShifter<" # width # ">"; let RenderMethod = "addShifterOperands"; let DiagnosticType = "AddSubRegShift" # width; } def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>; def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>; // Shifter operand for logical register shifted encodings. class LogicalShifterOperand : AsmOperandClass { let SuperClasses = [ShifterOperand]; let Name = "LogicalShifter" # width; let PredicateMethod = "isLogicalShifter<" # width # ">"; let RenderMethod = "addShifterOperands"; let DiagnosticType = "AddSubRegShift" # width; } def LogicalShifterOperand32 : LogicalShifterOperand<32>; def LogicalShifterOperand64 : LogicalShifterOperand<64>; // Shifter operand for logical vector 128/64-bit shifted encodings. def LogicalVecShifterOperand : AsmOperandClass { let SuperClasses = [ShifterOperand]; let Name = "LogicalVecShifter"; let RenderMethod = "addShifterOperands"; } def LogicalVecHalfWordShifterOperand : AsmOperandClass { let SuperClasses = [LogicalVecShifterOperand]; let Name = "LogicalVecHalfWordShifter"; let RenderMethod = "addShifterOperands"; } // The "MSL" shifter on the vector MOVI instruction. def MoveVecShifterOperand : AsmOperandClass { let SuperClasses = [ShifterOperand]; let Name = "MoveVecShifter"; let RenderMethod = "addShifterOperands"; } // Extend operand for arithmetic encodings. def ExtendOperand : AsmOperandClass { let Name = "Extend"; let DiagnosticType = "AddSubRegExtendLarge"; } def ExtendOperand64 : AsmOperandClass { let SuperClasses = [ExtendOperand]; let Name = "Extend64"; let DiagnosticType = "AddSubRegExtendSmall"; } // 'extend' that's a lsl of a 64-bit register. def ExtendOperandLSL64 : AsmOperandClass { let SuperClasses = [ExtendOperand]; let Name = "ExtendLSL64"; let RenderMethod = "addExtend64Operands"; let DiagnosticType = "AddSubRegExtendLarge"; } // 8-bit floating-point immediate encodings. def FPImmOperand : AsmOperandClass { let Name = "FPImm"; let ParserMethod = "tryParseFPImm"; let DiagnosticType = "InvalidFPImm"; } def CondCode : AsmOperandClass { let Name = "CondCode"; let DiagnosticType = "InvalidCondCode"; } // A 32-bit register pasrsed as 64-bit def GPR32as64Operand : AsmOperandClass { let Name = "GPR32as64"; let ParserMethod = "tryParseGPROperand"; } def GPR32as64 : RegisterOperand { let ParserMatchClass = GPR32as64Operand; } // A 64-bit register pasrsed as 32-bit def GPR64as32Operand : AsmOperandClass { let Name = "GPR64as32"; let ParserMethod = "tryParseGPROperand"; } def GPR64as32 : RegisterOperand { let ParserMatchClass = GPR64as32Operand; } // 8-bit immediate for AdvSIMD where 64-bit values of the form: // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh // are encoded as the eight bit value 'abcdefgh'. def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; } class UImmScaledMemoryIndexed : AsmOperandClass { let Name = "UImm" # Width # "s" # Scale; let DiagnosticType = "InvalidMemoryIndexed" # Scale # "UImm" # Width; let RenderMethod = "addImmScaledOperands<" # Scale # ">"; let PredicateMethod = "isUImmScaled<" # Width # ", " # Scale # ">"; } class SImmScaledMemoryIndexed : AsmOperandClass { let Name = "SImm" # Width # "s" # Scale; let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm" # Width; let RenderMethod = "addImmScaledOperands<" # Scale # ">"; let PredicateMethod = "isSImmScaled<" # Width # ", " # Scale # ">"; } //===----------------------------------------------------------------------===// // Operand Definitions. // // ADR[P] instruction labels. def AdrpOperand : AsmOperandClass { let Name = "AdrpLabel"; let ParserMethod = "tryParseAdrpLabel"; let DiagnosticType = "InvalidLabel"; } def adrplabel : Operand { let EncoderMethod = "getAdrLabelOpValue"; let PrintMethod = "printAdrpLabel"; let ParserMatchClass = AdrpOperand; } def AdrOperand : AsmOperandClass { let Name = "AdrLabel"; let ParserMethod = "tryParseAdrLabel"; let DiagnosticType = "InvalidLabel"; } def adrlabel : Operand { let EncoderMethod = "getAdrLabelOpValue"; let ParserMatchClass = AdrOperand; } class SImmOperand : AsmOperandClass { let Name = "SImm" # width; let DiagnosticType = "InvalidMemoryIndexedSImm" # width; let RenderMethod = "addImmOperands"; let PredicateMethod = "isSImm<" # width # ">"; } // Authenticated loads for v8.3 can have scaled 10-bit immediate offsets. def SImm10s8Operand : SImmScaledMemoryIndexed<10, 8>; def simm10Scaled : Operand { let ParserMatchClass = SImm10s8Operand; let DecoderMethod = "DecodeSImm<10>"; let PrintMethod = "printImmScale<8>"; } // uimm6 predicate - True if the immediate is in the range [0, 63]. def UImm6Operand : AsmOperandClass { let Name = "UImm6"; let DiagnosticType = "InvalidImm0_63"; } def uimm6 : Operand, ImmLeaf= 0 && Imm < 64; }]> { let ParserMatchClass = UImm6Operand; } def SImm9Operand : SImmOperand<9>; def simm9 : Operand, ImmLeaf= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; let DecoderMethod = "DecodeSImm<9>"; } def SImm8Operand : SImmOperand<8>; def simm8 : Operand, ImmLeaf= -128 && Imm < 127; }]> { let ParserMatchClass = SImm8Operand; let DecoderMethod = "DecodeSImm<8>"; } def SImm6Operand : SImmOperand<6>; def simm6_32b : Operand, ImmLeaf= -32 && Imm < 32; }]> { let ParserMatchClass = SImm6Operand; let DecoderMethod = "DecodeSImm<6>"; } def SImm5Operand : SImmOperand<5>; def simm5_64b : Operand, ImmLeaf= -16 && Imm < 16; }]> { let ParserMatchClass = SImm5Operand; let DecoderMethod = "DecodeSImm<5>"; } def simm5_32b : Operand, ImmLeaf= -16 && Imm < 16; }]> { let ParserMatchClass = SImm5Operand; let DecoderMethod = "DecodeSImm<5>"; } // simm7sN predicate - True if the immediate is a multiple of N in the range // [-64 * N, 63 * N]. def SImm7s4Operand : SImmScaledMemoryIndexed<7, 4>; def SImm7s8Operand : SImmScaledMemoryIndexed<7, 8>; def SImm7s16Operand : SImmScaledMemoryIndexed<7, 16>; def simm7s4 : Operand { let ParserMatchClass = SImm7s4Operand; let PrintMethod = "printImmScale<4>"; } def simm7s8 : Operand { let ParserMatchClass = SImm7s8Operand; let PrintMethod = "printImmScale<8>"; } def simm7s16 : Operand { let ParserMatchClass = SImm7s16Operand; let PrintMethod = "printImmScale<16>"; } def am_indexed7s8 : ComplexPattern; def am_indexed7s16 : ComplexPattern; def am_indexed7s32 : ComplexPattern; def am_indexed7s64 : ComplexPattern; def am_indexed7s128 : ComplexPattern; // uimm5sN predicate - True if the immediate is a multiple of N in the range // [0 * N, 32 * N]. def UImm5s2Operand : UImmScaledMemoryIndexed<5, 2>; def UImm5s4Operand : UImmScaledMemoryIndexed<5, 4>; def UImm5s8Operand : UImmScaledMemoryIndexed<5, 8>; def uimm5s2 : Operand, ImmLeaf= 0 && Imm < (32*2) && ((Imm % 2) == 0); }]> { let ParserMatchClass = UImm5s2Operand; let PrintMethod = "printImmScale<2>"; } def uimm5s4 : Operand, ImmLeaf= 0 && Imm < (32*4) && ((Imm % 4) == 0); }]> { let ParserMatchClass = UImm5s4Operand; let PrintMethod = "printImmScale<4>"; } def uimm5s8 : Operand, ImmLeaf= 0 && Imm < (32*8) && ((Imm % 8) == 0); }]> { let ParserMatchClass = UImm5s8Operand; let PrintMethod = "printImmScale<8>"; } // uimm6sN predicate - True if the immediate is a multiple of N in the range // [0 * N, 64 * N]. def UImm6s1Operand : UImmScaledMemoryIndexed<6, 1>; def UImm6s2Operand : UImmScaledMemoryIndexed<6, 2>; def UImm6s4Operand : UImmScaledMemoryIndexed<6, 4>; def UImm6s8Operand : UImmScaledMemoryIndexed<6, 8>; def uimm6s1 : Operand, ImmLeaf= 0 && Imm < 64; }]> { let ParserMatchClass = UImm6s1Operand; } def uimm6s2 : Operand, ImmLeaf= 0 && Imm < (64*2) && ((Imm % 2) == 0); }]> { let PrintMethod = "printImmScale<2>"; let ParserMatchClass = UImm6s2Operand; } def uimm6s4 : Operand, ImmLeaf= 0 && Imm < (64*4) && ((Imm % 4) == 0); }]> { let PrintMethod = "printImmScale<4>"; let ParserMatchClass = UImm6s4Operand; } def uimm6s8 : Operand, ImmLeaf= 0 && Imm < (64*8) && ((Imm % 8) == 0); }]> { let PrintMethod = "printImmScale<8>"; let ParserMatchClass = UImm6s8Operand; } // simm6sN predicate - True if the immediate is a multiple of N in the range // [-32 * N, 31 * N]. def SImm6s1Operand : SImmScaledMemoryIndexed<6, 1>; def simm6s1 : Operand, ImmLeaf= -32 && Imm < 32; }]> { let ParserMatchClass = SImm6s1Operand; let DecoderMethod = "DecodeSImm<6>"; } // simm4sN predicate - True if the immediate is a multiple of N in the range // [ -8* N, 7 * N]. def SImm4s1Operand : SImmScaledMemoryIndexed<4, 1>; def SImm4s2Operand : SImmScaledMemoryIndexed<4, 2>; def SImm4s3Operand : SImmScaledMemoryIndexed<4, 3>; def SImm4s4Operand : SImmScaledMemoryIndexed<4, 4>; def SImm4s16Operand : SImmScaledMemoryIndexed<4, 16>; def simm4s1 : Operand, ImmLeaf=-8 && Imm <= 7; }]> { let ParserMatchClass = SImm4s1Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s2 : Operand, ImmLeaf=-16 && Imm <= 14 && (Imm % 2) == 0x0; }]> { let PrintMethod = "printImmScale<2>"; let ParserMatchClass = SImm4s2Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s3 : Operand, ImmLeaf=-24 && Imm <= 21 && (Imm % 3) == 0x0; }]> { let PrintMethod = "printImmScale<3>"; let ParserMatchClass = SImm4s3Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s4 : Operand, ImmLeaf=-32 && Imm <= 28 && (Imm % 4) == 0x0; }]> { let PrintMethod = "printImmScale<4>"; let ParserMatchClass = SImm4s4Operand; let DecoderMethod = "DecodeSImm<4>"; } def simm4s16 : Operand, ImmLeaf=-128 && Imm <= 112 && (Imm % 16) == 0x0; }]> { let PrintMethod = "printImmScale<16>"; let ParserMatchClass = SImm4s16Operand; let DecoderMethod = "DecodeSImm<4>"; } class AsmImmRange : AsmOperandClass { let Name = "Imm" # Low # "_" # High; let DiagnosticType = "InvalidImm" # Low # "_" # High; let RenderMethod = "addImmOperands"; let PredicateMethod = "isImmInRange<" # Low # "," # High # ">"; } def Imm1_8Operand : AsmImmRange<1, 8>; def Imm1_16Operand : AsmImmRange<1, 16>; def Imm1_32Operand : AsmImmRange<1, 32>; def Imm1_64Operand : AsmImmRange<1, 64>; class BranchTarget : AsmOperandClass { let Name = "BranchTarget" # N; let DiagnosticType = "InvalidLabel"; let PredicateMethod = "isBranchTarget<" # N # ">"; } class PCRelLabel : BranchTarget { let Name = "PCRelLabel" # N; } def BranchTarget14Operand : BranchTarget<14>; def BranchTarget26Operand : BranchTarget<26>; def PCRelLabel19Operand : PCRelLabel<19>; def MovZSymbolG3AsmOperand : AsmOperandClass { let Name = "MovZSymbolG3"; let RenderMethod = "addImmOperands"; } def movz_symbol_g3 : Operand { let ParserMatchClass = MovZSymbolG3AsmOperand; } def MovZSymbolG2AsmOperand : AsmOperandClass { let Name = "MovZSymbolG2"; let RenderMethod = "addImmOperands"; } def movz_symbol_g2 : Operand { let ParserMatchClass = MovZSymbolG2AsmOperand; } def MovZSymbolG1AsmOperand : AsmOperandClass { let Name = "MovZSymbolG1"; let RenderMethod = "addImmOperands"; } def movz_symbol_g1 : Operand { let ParserMatchClass = MovZSymbolG1AsmOperand; } def MovZSymbolG0AsmOperand : AsmOperandClass { let Name = "MovZSymbolG0"; let RenderMethod = "addImmOperands"; } def movz_symbol_g0 : Operand { let ParserMatchClass = MovZSymbolG0AsmOperand; } def MovKSymbolG3AsmOperand : AsmOperandClass { let Name = "MovKSymbolG3"; let RenderMethod = "addImmOperands"; } def movk_symbol_g3 : Operand { let ParserMatchClass = MovKSymbolG3AsmOperand; } def MovKSymbolG2AsmOperand : AsmOperandClass { let Name = "MovKSymbolG2"; let RenderMethod = "addImmOperands"; } def movk_symbol_g2 : Operand { let ParserMatchClass = MovKSymbolG2AsmOperand; } def MovKSymbolG1AsmOperand : AsmOperandClass { let Name = "MovKSymbolG1"; let RenderMethod = "addImmOperands"; } def movk_symbol_g1 : Operand { let ParserMatchClass = MovKSymbolG1AsmOperand; } def MovKSymbolG0AsmOperand : AsmOperandClass { let Name = "MovKSymbolG0"; let RenderMethod = "addImmOperands"; } def movk_symbol_g0 : Operand { let ParserMatchClass = MovKSymbolG0AsmOperand; } class fixedpoint_i32 : Operand, ComplexPattern", [fpimm, ld]> { let EncoderMethod = "getFixedPointScaleOpValue"; let DecoderMethod = "DecodeFixedPointScaleImm32"; let ParserMatchClass = Imm1_32Operand; } class fixedpoint_i64 : Operand, ComplexPattern", [fpimm, ld]> { let EncoderMethod = "getFixedPointScaleOpValue"; let DecoderMethod = "DecodeFixedPointScaleImm64"; let ParserMatchClass = Imm1_64Operand; } def fixedpoint_f16_i32 : fixedpoint_i32; def fixedpoint_f32_i32 : fixedpoint_i32; def fixedpoint_f64_i32 : fixedpoint_i32; def fixedpoint_f16_i64 : fixedpoint_i64; def fixedpoint_f32_i64 : fixedpoint_i64; def fixedpoint_f64_i64 : fixedpoint_i64; def vecshiftR8 : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 9); }]> { let EncoderMethod = "getVecShiftR8OpValue"; let DecoderMethod = "DecodeVecShiftR8Imm"; let ParserMatchClass = Imm1_8Operand; } def vecshiftR16 : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 17); }]> { let EncoderMethod = "getVecShiftR16OpValue"; let DecoderMethod = "DecodeVecShiftR16Imm"; let ParserMatchClass = Imm1_16Operand; } def vecshiftR16Narrow : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 9); }]> { let EncoderMethod = "getVecShiftR16OpValue"; let DecoderMethod = "DecodeVecShiftR16ImmNarrow"; let ParserMatchClass = Imm1_8Operand; } def vecshiftR32 : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 33); }]> { let EncoderMethod = "getVecShiftR32OpValue"; let DecoderMethod = "DecodeVecShiftR32Imm"; let ParserMatchClass = Imm1_32Operand; } def vecshiftR32Narrow : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 17); }]> { let EncoderMethod = "getVecShiftR32OpValue"; let DecoderMethod = "DecodeVecShiftR32ImmNarrow"; let ParserMatchClass = Imm1_16Operand; } def vecshiftR64 : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 65); }]> { let EncoderMethod = "getVecShiftR64OpValue"; let DecoderMethod = "DecodeVecShiftR64Imm"; let ParserMatchClass = Imm1_64Operand; } def vecshiftR64Narrow : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 33); }]> { let EncoderMethod = "getVecShiftR64OpValue"; let DecoderMethod = "DecodeVecShiftR64ImmNarrow"; let ParserMatchClass = Imm1_32Operand; } def Imm0_1Operand : AsmImmRange<0, 1>; def Imm0_7Operand : AsmImmRange<0, 7>; def Imm0_15Operand : AsmImmRange<0, 15>; def Imm0_31Operand : AsmImmRange<0, 31>; def Imm0_63Operand : AsmImmRange<0, 63>; def vecshiftL8 : Operand, ImmLeaf { let EncoderMethod = "getVecShiftL8OpValue"; let DecoderMethod = "DecodeVecShiftL8Imm"; let ParserMatchClass = Imm0_7Operand; } def vecshiftL16 : Operand, ImmLeaf { let EncoderMethod = "getVecShiftL16OpValue"; let DecoderMethod = "DecodeVecShiftL16Imm"; let ParserMatchClass = Imm0_15Operand; } def vecshiftL32 : Operand, ImmLeaf { let EncoderMethod = "getVecShiftL32OpValue"; let DecoderMethod = "DecodeVecShiftL32Imm"; let ParserMatchClass = Imm0_31Operand; } def vecshiftL64 : Operand, ImmLeaf { let EncoderMethod = "getVecShiftL64OpValue"; let DecoderMethod = "DecodeVecShiftL64Imm"; let ParserMatchClass = Imm0_63Operand; } // Crazy immediate formats used by 32-bit and 64-bit logical immediate // instructions for splatting repeating bit patterns across the immediate. def logical_imm32_XFORM : SDNodeXFormgetZExtValue(), 32); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); }]>; def logical_imm64_XFORM : SDNodeXFormgetZExtValue(), 64); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); }]>; let DiagnosticType = "LogicalSecondSource" in { def LogicalImm32Operand : AsmOperandClass { let Name = "LogicalImm32"; let PredicateMethod = "isLogicalImm"; let RenderMethod = "addLogicalImmOperands"; } def LogicalImm64Operand : AsmOperandClass { let Name = "LogicalImm64"; let PredicateMethod = "isLogicalImm"; let RenderMethod = "addLogicalImmOperands"; } def LogicalImm32NotOperand : AsmOperandClass { let Name = "LogicalImm32Not"; let PredicateMethod = "isLogicalImm"; let RenderMethod = "addLogicalImmNotOperands"; } def LogicalImm64NotOperand : AsmOperandClass { let Name = "LogicalImm64Not"; let PredicateMethod = "isLogicalImm"; let RenderMethod = "addLogicalImmNotOperands"; } } def logical_imm32 : Operand, IntImmLeaf { let PrintMethod = "printLogicalImm"; let ParserMatchClass = LogicalImm32Operand; } def logical_imm64 : Operand, IntImmLeaf { let PrintMethod = "printLogicalImm"; let ParserMatchClass = LogicalImm64Operand; } def logical_imm32_not : Operand { let ParserMatchClass = LogicalImm32NotOperand; } def logical_imm64_not : Operand { let ParserMatchClass = LogicalImm64NotOperand; } // imm0_65535 predicate - True if the immediate is in the range [0,65535]. def Imm0_65535Operand : AsmImmRange<0, 65535>; def imm0_65535 : Operand, ImmLeaf { let ParserMatchClass = Imm0_65535Operand; let PrintMethod = "printImmHex"; } // imm0_255 predicate - True if the immediate is in the range [0,255]. def Imm0_255Operand : AsmImmRange<0,255>; def imm0_255 : Operand, ImmLeaf { let ParserMatchClass = Imm0_255Operand; let PrintMethod = "printImm"; } // imm0_127 predicate - True if the immediate is in the range [0,127] def Imm0_127Operand : AsmImmRange<0, 127>; def imm0_127 : Operand, ImmLeaf { let ParserMatchClass = Imm0_127Operand; let PrintMethod = "printImm"; } // NOTE: These imm0_N operands have to be of type i64 because i64 is the size // for all shift-amounts. // imm0_63 predicate - True if the immediate is in the range [0,63] def imm0_63 : Operand, ImmLeaf { let ParserMatchClass = Imm0_63Operand; } // imm0_31 predicate - True if the immediate is in the range [0,31] def imm0_31 : Operand, ImmLeaf { let ParserMatchClass = Imm0_31Operand; } // True if the 32-bit immediate is in the range [0,31] def imm32_0_31 : Operand, ImmLeaf { let ParserMatchClass = Imm0_31Operand; } // imm0_1 predicate - True if the immediate is in the range [0,1] def imm0_1 : Operand, ImmLeaf { let ParserMatchClass = Imm0_1Operand; } // imm0_15 predicate - True if the immediate is in the range [0,15] def imm0_15 : Operand, ImmLeaf { let ParserMatchClass = Imm0_15Operand; } // imm0_7 predicate - True if the immediate is in the range [0,7] def imm0_7 : Operand, ImmLeaf { let ParserMatchClass = Imm0_7Operand; } // imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15] def imm32_0_15 : Operand, ImmLeaf { let ParserMatchClass = Imm0_15Operand; } // An arithmetic shifter operand: // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr // {5-0} - imm6 class arith_shift : Operand { let PrintMethod = "printShifter"; let ParserMatchClass = !cast( "ArithmeticShifterOperand" # width); } def arith_shift32 : arith_shift; def arith_shift64 : arith_shift; class arith_shifted_reg : Operand, ComplexPattern { let PrintMethod = "printShiftedRegister"; let MIOperandInfo = (ops regclass, !cast("arith_shift" # width)); } def arith_shifted_reg32 : arith_shifted_reg; def arith_shifted_reg64 : arith_shifted_reg; // An arithmetic shifter operand: // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror // {5-0} - imm6 class logical_shift : Operand { let PrintMethod = "printShifter"; let ParserMatchClass = !cast( "LogicalShifterOperand" # width); } def logical_shift32 : logical_shift<32>; def logical_shift64 : logical_shift<64>; class logical_shifted_reg : Operand, ComplexPattern { let PrintMethod = "printShiftedRegister"; let MIOperandInfo = (ops regclass, shiftop); } def logical_shifted_reg32 : logical_shifted_reg; def logical_shifted_reg64 : logical_shifted_reg; // A logical vector shifter operand: // {7-6} - shift type: 00 = lsl // {5-0} - imm6: #0, #8, #16, or #24 def logical_vec_shift : Operand { let PrintMethod = "printShifter"; let EncoderMethod = "getVecShifterOpValue"; let ParserMatchClass = LogicalVecShifterOperand; } // A logical vector half-word shifter operand: // {7-6} - shift type: 00 = lsl // {5-0} - imm6: #0 or #8 def logical_vec_hw_shift : Operand { let PrintMethod = "printShifter"; let EncoderMethod = "getVecShifterOpValue"; let ParserMatchClass = LogicalVecHalfWordShifterOperand; } // A vector move shifter operand: // {0} - imm1: #8 or #16 def move_vec_shift : Operand { let PrintMethod = "printShifter"; let EncoderMethod = "getMoveVecShifterOpValue"; let ParserMatchClass = MoveVecShifterOperand; } let DiagnosticType = "AddSubSecondSource" in { def AddSubImmOperand : AsmOperandClass { let Name = "AddSubImm"; let ParserMethod = "tryParseImmWithOptionalShift"; let RenderMethod = "addImmWithOptionalShiftOperands<12>"; } def AddSubImmNegOperand : AsmOperandClass { let Name = "AddSubImmNeg"; let ParserMethod = "tryParseImmWithOptionalShift"; let RenderMethod = "addImmNegWithOptionalShiftOperands<12>"; } } // An ADD/SUB immediate shifter operand: // second operand: // {7-6} - shift type: 00 = lsl // {5-0} - imm6: #0 or #12 class addsub_shifted_imm : Operand, ComplexPattern { let PrintMethod = "printAddSubImm"; let EncoderMethod = "getAddSubImmOpValue"; let ParserMatchClass = AddSubImmOperand; let MIOperandInfo = (ops i32imm, i32imm); } class addsub_shifted_imm_neg : Operand { let EncoderMethod = "getAddSubImmOpValue"; let ParserMatchClass = AddSubImmNegOperand; let MIOperandInfo = (ops i32imm, i32imm); } def addsub_shifted_imm32 : addsub_shifted_imm; def addsub_shifted_imm64 : addsub_shifted_imm; def addsub_shifted_imm32_neg : addsub_shifted_imm_neg; def addsub_shifted_imm64_neg : addsub_shifted_imm_neg; def gi_addsub_shifted_imm32 : GIComplexOperandMatcher, GIComplexPatternEquiv; def gi_addsub_shifted_imm64 : GIComplexOperandMatcher, GIComplexPatternEquiv; class neg_addsub_shifted_imm : Operand, ComplexPattern { let PrintMethod = "printAddSubImm"; let EncoderMethod = "getAddSubImmOpValue"; let ParserMatchClass = AddSubImmOperand; let MIOperandInfo = (ops i32imm, i32imm); } def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm; def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm; // An extend operand: // {5-3} - extend type // {2-0} - imm3 def arith_extend : Operand { let PrintMethod = "printArithExtend"; let ParserMatchClass = ExtendOperand; } def arith_extend64 : Operand { let PrintMethod = "printArithExtend"; let ParserMatchClass = ExtendOperand64; } // 'extend' that's a lsl of a 64-bit register. def arith_extendlsl64 : Operand { let PrintMethod = "printArithExtend"; let ParserMatchClass = ExtendOperandLSL64; } class arith_extended_reg32 : Operand, ComplexPattern { let PrintMethod = "printExtendedRegister"; let MIOperandInfo = (ops GPR32, arith_extend); } class arith_extended_reg32to64 : Operand, ComplexPattern { let PrintMethod = "printExtendedRegister"; let MIOperandInfo = (ops GPR32, arith_extend64); } // Floating-point immediate. def fpimm16 : Operand, FPImmLeafgetValueAPF(); uint32_t enc = AArch64_AM::getFP16Imm(InVal); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); }]>> { let ParserMatchClass = FPImmOperand; let PrintMethod = "printFPImmOperand"; } def fpimm32 : Operand, FPImmLeafgetValueAPF(); uint32_t enc = AArch64_AM::getFP32Imm(InVal); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); }]>> { let ParserMatchClass = FPImmOperand; let PrintMethod = "printFPImmOperand"; } def fpimm64 : Operand, FPImmLeafgetValueAPF(); uint32_t enc = AArch64_AM::getFP64Imm(InVal); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); }]>> { let ParserMatchClass = FPImmOperand; let PrintMethod = "printFPImmOperand"; } def fpimm8 : Operand { let ParserMatchClass = FPImmOperand; let PrintMethod = "printFPImmOperand"; } def fpimm0 : FPImmLeaf; // Vector lane operands class AsmVectorIndex : AsmOperandClass { let Name = NamePrefix # "IndexRange" # Min # "_" # Max; let DiagnosticType = "Invalid" # Name; let PredicateMethod = "isVectorIndex<" # Min # ", " # Max # ">"; let RenderMethod = "addVectorIndexOperands"; } class AsmVectorIndexOpnd : Operand, ImmLeaf { let ParserMatchClass = mc; let PrintMethod = "printVectorIndex"; } def VectorIndex1Operand : AsmVectorIndex<1, 1>; def VectorIndexBOperand : AsmVectorIndex<0, 15>; def VectorIndexHOperand : AsmVectorIndex<0, 7>; def VectorIndexSOperand : AsmVectorIndex<0, 3>; def VectorIndexDOperand : AsmVectorIndex<0, 1>; def VectorIndex1 : AsmVectorIndexOpnd; def VectorIndexB : AsmVectorIndexOpnd; def VectorIndexH : AsmVectorIndexOpnd; def VectorIndexS : AsmVectorIndexOpnd; def VectorIndexD : AsmVectorIndexOpnd; def SVEVectorIndexExtDupBOperand : AsmVectorIndex<0, 63, "SVE">; def SVEVectorIndexExtDupHOperand : AsmVectorIndex<0, 31, "SVE">; def SVEVectorIndexExtDupSOperand : AsmVectorIndex<0, 15, "SVE">; def SVEVectorIndexExtDupDOperand : AsmVectorIndex<0, 7, "SVE">; def SVEVectorIndexExtDupQOperand : AsmVectorIndex<0, 3, "SVE">; def sve_elm_idx_extdup_b : AsmVectorIndexOpnd; def sve_elm_idx_extdup_h : AsmVectorIndexOpnd; def sve_elm_idx_extdup_s : AsmVectorIndexOpnd; def sve_elm_idx_extdup_d : AsmVectorIndexOpnd; def sve_elm_idx_extdup_q : AsmVectorIndexOpnd; // 8-bit immediate for AdvSIMD where 64-bit values of the form: // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh // are encoded as the eight bit value 'abcdefgh'. def simdimmtype10 : Operand, FPImmLeafgetValueAPF(); uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF() .bitcastToAPInt() .getZExtValue()); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); }]>> { let ParserMatchClass = SIMDImmType10Operand; let PrintMethod = "printSIMDType10Operand"; } //--- // System management //--- // Base encoding for system instruction operands. let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class BaseSystemI pattern = []> : I { let Inst{31-22} = 0b1101010100; let Inst{21} = L; } // System instructions which do not have an Rt register. class SimpleSystemI pattern = []> : BaseSystemI { let Inst{4-0} = 0b11111; } // System instructions which have an Rt register. class RtSystemI : BaseSystemI, Sched<[WriteSys]> { bits<5> Rt; let Inst{4-0} = Rt; } // Hint instructions that take both a CRm and a 3-bit immediate. // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot // model patterns with sufficiently fine granularity let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in class HintI : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#"\t$imm", "", [(int_aarch64_hint imm0_127:$imm)]>, Sched<[WriteHint]> { bits <7> imm; let Inst{20-12} = 0b000110010; let Inst{11-5} = imm; } // System instructions taking a single literal operand which encodes into // CRm. op2 differentiates the opcodes. def BarrierAsmOperand : AsmOperandClass { let Name = "Barrier"; let ParserMethod = "tryParseBarrierOperand"; } def barrier_op : Operand { let PrintMethod = "printBarrierOption"; let ParserMatchClass = BarrierAsmOperand; } class CRmSystemI opc, string asm, list pattern = []> : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>, Sched<[WriteBarrier]> { bits<4> CRm; let Inst{20-12} = 0b000110011; let Inst{11-8} = CRm; let Inst{7-5} = opc; } class SystemNoOperands op2, string asm, list pattern = []> : SimpleSystemI<0, (ins), asm, "", pattern>, Sched<[]> { bits<4> CRm; let CRm = 0b0011; let Inst{31-12} = 0b11010101000000110010; let Inst{11-8} = CRm; let Inst{7-5} = op2; let Inst{4-0} = 0b11111; } // MRS/MSR system instructions. These have different operand classes because // a different subset of registers can be accessed through each instruction. def MRSSystemRegisterOperand : AsmOperandClass { let Name = "MRSSystemRegister"; let ParserMethod = "tryParseSysReg"; let DiagnosticType = "MRS"; } // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate. def mrs_sysreg_op : Operand { let ParserMatchClass = MRSSystemRegisterOperand; let DecoderMethod = "DecodeMRSSystemRegister"; let PrintMethod = "printMRSSystemRegister"; } def MSRSystemRegisterOperand : AsmOperandClass { let Name = "MSRSystemRegister"; let ParserMethod = "tryParseSysReg"; let DiagnosticType = "MSR"; } def msr_sysreg_op : Operand { let ParserMatchClass = MSRSystemRegisterOperand; let DecoderMethod = "DecodeMSRSystemRegister"; let PrintMethod = "printMSRSystemRegister"; } def PSBHintOperand : AsmOperandClass { let Name = "PSBHint"; let ParserMethod = "tryParsePSBHint"; } def psbhint_op : Operand { let ParserMatchClass = PSBHintOperand; let PrintMethod = "printPSBHintOp"; let MCOperandPredicate = [{ // Check, if operand is valid, to fix exhaustive aliasing in disassembly. // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. if (!MCOp.isImm()) return false; return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr; }]; } class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg), "mrs", "\t$Rt, $systemreg"> { bits<16> systemreg; let Inst{20-5} = systemreg; } // FIXME: Some of these def NZCV, others don't. Best way to model that? // Explicitly modeling each of the system register as a register class // would do it, but feels like overkill at this point. class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt), "msr", "\t$systemreg, $Rt"> { bits<16> systemreg; let Inst{20-5} = systemreg; } def SystemPStateFieldWithImm0_15Operand : AsmOperandClass { let Name = "SystemPStateFieldWithImm0_15"; let ParserMethod = "tryParseSysReg"; } def pstatefield4_op : Operand { let ParserMatchClass = SystemPStateFieldWithImm0_15Operand; let PrintMethod = "printSystemPStateField"; } let Defs = [NZCV] in class MSRpstateImm0_15 : SimpleSystemI<0, (ins pstatefield4_op:$pstatefield, imm0_15:$imm), "msr", "\t$pstatefield, $imm">, Sched<[WriteSys]> { bits<6> pstatefield; bits<4> imm; let Inst{20-19} = 0b00; let Inst{18-16} = pstatefield{5-3}; let Inst{15-12} = 0b0100; let Inst{11-8} = imm; let Inst{7-5} = pstatefield{2-0}; let DecoderMethod = "DecodeSystemPStateInstruction"; // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns // Fail the decoder should attempt to decode the instruction as MSRI. let hasCompleteDecoder = 0; } def SystemPStateFieldWithImm0_1Operand : AsmOperandClass { let Name = "SystemPStateFieldWithImm0_1"; let ParserMethod = "tryParseSysReg"; } def pstatefield1_op : Operand { let ParserMatchClass = SystemPStateFieldWithImm0_1Operand; let PrintMethod = "printSystemPStateField"; } let Defs = [NZCV] in class MSRpstateImm0_1 : SimpleSystemI<0, (ins pstatefield1_op:$pstatefield, imm0_1:$imm), "msr", "\t$pstatefield, $imm">, Sched<[WriteSys]> { bits<6> pstatefield; bit imm; let Inst{20-19} = 0b00; let Inst{18-16} = pstatefield{5-3}; let Inst{15-9} = 0b0100000; let Inst{8} = imm; let Inst{7-5} = pstatefield{2-0}; let DecoderMethod = "DecodeSystemPStateInstruction"; // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns // Fail the decoder should attempt to decode the instruction as MSRI. let hasCompleteDecoder = 0; } // SYS and SYSL generic system instructions. def SysCRAsmOperand : AsmOperandClass { let Name = "SysCR"; let ParserMethod = "tryParseSysCROperand"; } def sys_cr_op : Operand { let PrintMethod = "printSysCROperand"; let ParserMatchClass = SysCRAsmOperand; } class SystemXtI : RtSystemI { bits<3> op1; bits<4> Cn; bits<4> Cm; bits<3> op2; let Inst{20-19} = 0b01; let Inst{18-16} = op1; let Inst{15-12} = Cn; let Inst{11-8} = Cm; let Inst{7-5} = op2; } class SystemLXtI : RtSystemI { bits<3> op1; bits<4> Cn; bits<4> Cm; bits<3> op2; let Inst{20-19} = 0b01; let Inst{18-16} = op1; let Inst{15-12} = Cn; let Inst{11-8} = Cm; let Inst{7-5} = op2; } // Branch (register) instructions: // // case opc of // 0001 blr // 0000 br // 0101 dret // 0100 eret // 0010 ret // otherwise UNDEFINED class BaseBranchReg opc, dag oops, dag iops, string asm, string operands, list pattern> : I, Sched<[WriteBrReg]> { let Inst{31-25} = 0b1101011; let Inst{24-21} = opc; let Inst{20-16} = 0b11111; let Inst{15-10} = 0b000000; let Inst{4-0} = 0b00000; } class BranchReg opc, string asm, list pattern> : BaseBranchReg { bits<5> Rn; let Inst{9-5} = Rn; } let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in class SpecialReturn opc, string asm> : BaseBranchReg { let Inst{9-5} = 0b11111; } let mayLoad = 1 in class RCPCLoad sz, string asm, RegisterClass RC> : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>, Sched<[]> { bits<5> Rn; bits<5> Rt; let Inst{31-30} = sz; let Inst{29-10} = 0b11100010111111110000; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } class AuthBase M, dag oops, dag iops, string asm, string operands, list pattern> : I, Sched<[]> { let Inst{31-25} = 0b1101011; let Inst{20-11} = 0b1111100001; let Inst{10} = M; let Inst{4-0} = 0b11111; } class AuthBranchTwoOperands op, bits<1> M, string asm> : AuthBase { bits<5> Rn; bits<5> Rm; let Inst{24-22} = 0b100; let Inst{21} = op; let Inst{9-5} = Rn; let Inst{4-0} = Rm; } class AuthOneOperand opc, bits<1> M, string asm> : AuthBase { bits<5> Rn; let Inst{24} = 0; let Inst{23-21} = opc; let Inst{9-5} = Rn; } class AuthReturn op, bits<1> M, string asm> : AuthBase { let Inst{24} = 0; let Inst{23-21} = op; let Inst{9-0} = 0b1111111111; } let mayLoad = 1 in class BaseAuthLoad : I, Sched<[]> { bits<10> offset; bits<5> Rn; bits<5> Rt; let Inst{31-24} = 0b11111000; let Inst{23} = M; let Inst{22} = offset{9}; let Inst{21} = 1; let Inst{20-12} = offset{8-0}; let Inst{11} = W; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } multiclass AuthLoad { def indexed : BaseAuthLoad; def writeback : BaseAuthLoad; def : InstAlias(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>; } //--- // Conditional branch instruction. //--- // Condition code. // 4-bit immediate. Pretty-printed as def ccode : Operand { let PrintMethod = "printCondCode"; let ParserMatchClass = CondCode; } def inv_ccode : Operand { // AL and NV are invalid in the aliases which use inv_ccode let PrintMethod = "printInverseCondCode"; let ParserMatchClass = CondCode; let MCOperandPredicate = [{ return MCOp.isImm() && MCOp.getImm() != AArch64CC::AL && MCOp.getImm() != AArch64CC::NV; }]; } // Conditional branch target. 19-bit immediate. The low two bits of the target // offset are implied zero and so are not part of the immediate. def am_brcond : Operand { let EncoderMethod = "getCondBranchTargetOpValue"; let DecoderMethod = "DecodePCRelLabel19"; let PrintMethod = "printAlignedLabel"; let ParserMatchClass = PCRelLabel19Operand; let OperandType = "OPERAND_PCREL"; } class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target), "b", ".$cond\t$target", "", [(AArch64brcond bb:$target, imm:$cond, NZCV)]>, Sched<[WriteBr]> { let isBranch = 1; let isTerminator = 1; let Uses = [NZCV]; bits<4> cond; bits<19> target; let Inst{31-24} = 0b01010100; let Inst{23-5} = target; let Inst{4} = 0; let Inst{3-0} = cond; } //--- // Compare-and-branch instructions. //--- class BaseCmpBranch : I<(outs), (ins regtype:$Rt, am_brcond:$target), asm, "\t$Rt, $target", "", [(node regtype:$Rt, bb:$target)]>, Sched<[WriteBr]> { let isBranch = 1; let isTerminator = 1; bits<5> Rt; bits<19> target; let Inst{30-25} = 0b011010; let Inst{24} = op; let Inst{23-5} = target; let Inst{4-0} = Rt; } multiclass CmpBranch { def W : BaseCmpBranch { let Inst{31} = 0; } def X : BaseCmpBranch { let Inst{31} = 1; } } //--- // Test-bit-and-branch instructions. //--- // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of // the target offset are implied zero and so are not part of the immediate. def am_tbrcond : Operand { let EncoderMethod = "getTestBranchTargetOpValue"; let PrintMethod = "printAlignedLabel"; let ParserMatchClass = BranchTarget14Operand; let OperandType = "OPERAND_PCREL"; } // AsmOperand classes to emit (or not) special diagnostics def TBZImm0_31Operand : AsmOperandClass { let Name = "TBZImm0_31"; let PredicateMethod = "isImmInRange<0,31>"; let RenderMethod = "addImmOperands"; } def TBZImm32_63Operand : AsmOperandClass { let Name = "Imm32_63"; let PredicateMethod = "isImmInRange<32,63>"; let DiagnosticType = "InvalidImm0_63"; let RenderMethod = "addImmOperands"; } class tbz_imm0_31 : Operand, ImmLeaf { let ParserMatchClass = matcher; } def tbz_imm0_31_diag : tbz_imm0_31; def tbz_imm0_31_nodiag : tbz_imm0_31; def tbz_imm32_63 : Operand, ImmLeaf 31) && (((uint32_t)Imm) < 64); }]> { let ParserMatchClass = TBZImm32_63Operand; } class BaseTestBranch : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target), asm, "\t$Rt, $bit_off, $target", "", [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>, Sched<[WriteBr]> { let isBranch = 1; let isTerminator = 1; bits<5> Rt; bits<6> bit_off; bits<14> target; let Inst{30-25} = 0b011011; let Inst{24} = op; let Inst{23-19} = bit_off{4-0}; let Inst{18-5} = target; let Inst{4-0} = Rt; let DecoderMethod = "DecodeTestAndBranch"; } multiclass TestBranch { def W : BaseTestBranch { let Inst{31} = 0; } def X : BaseTestBranch { let Inst{31} = 1; } // Alias X-reg with 0-31 imm to W-Reg. def : InstAlias(NAME#"W") GPR32as64:$Rd, tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>; def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target), (!cast(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32), tbz_imm0_31_diag:$imm, bb:$target)>; } //--- // Unconditional branch (immediate) instructions. //--- def am_b_target : Operand { let EncoderMethod = "getBranchTargetOpValue"; let PrintMethod = "printAlignedLabel"; let ParserMatchClass = BranchTarget26Operand; let OperandType = "OPERAND_PCREL"; } def am_bl_target : Operand { let EncoderMethod = "getBranchTargetOpValue"; let PrintMethod = "printAlignedLabel"; let ParserMatchClass = BranchTarget26Operand; let OperandType = "OPERAND_PCREL"; } class BImm pattern> : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> { bits<26> addr; let Inst{31} = op; let Inst{30-26} = 0b00101; let Inst{25-0} = addr; let DecoderMethod = "DecodeUnconditionalBranch"; } class BranchImm pattern> : BImm; class CallImm pattern> : BImm; //--- // Basic one-operand data processing instructions. //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseOneOperandData opc, RegisterClass regtype, string asm, SDPatternOperator node> : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "", [(set regtype:$Rd, (node regtype:$Rn))]>, Sched<[WriteI, ReadI]> { bits<5> Rd; bits<5> Rn; let Inst{30-13} = 0b101101011000000000; let Inst{12-10} = opc; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in multiclass OneOperandData opc, string asm, SDPatternOperator node = null_frag> { def Wr : BaseOneOperandData { let Inst{31} = 0; } def Xr : BaseOneOperandData { let Inst{31} = 1; } } class OneWRegData opc, string asm, SDPatternOperator node> : BaseOneOperandData { let Inst{31} = 0; } class OneXRegData opc, string asm, SDPatternOperator node> : BaseOneOperandData { let Inst{31} = 1; } class SignAuthOneData opcode_prefix, bits<2> opcode, string asm> : I<(outs GPR64:$Rd), (ins GPR64sp:$Rn), asm, "\t$Rd, $Rn", "", []>, Sched<[WriteI, ReadI]> { bits<5> Rd; bits<5> Rn; let Inst{31-15} = 0b11011010110000010; let Inst{14-12} = opcode_prefix; let Inst{11-10} = opcode; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class SignAuthZero opcode_prefix, bits<2> opcode, string asm> : I<(outs GPR64:$Rd), (ins), asm, "\t$Rd", "", []>, Sched<[]> { bits<5> Rd; let Inst{31-15} = 0b11011010110000010; let Inst{14-12} = opcode_prefix; let Inst{11-10} = opcode; let Inst{9-5} = 0b11111; let Inst{4-0} = Rd; } class SignAuthTwoOperand opc, string asm, SDPatternOperator OpNode> : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rd, $Rn, $Rm", "", [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>, Sched<[WriteI, ReadI, ReadI]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-21} = 0b10011010110; let Inst{20-16} = Rm; let Inst{15-14} = 0b00; let Inst{13-10} = opc; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } // Base class for the Armv8.4-A 8 and 16-bit flag manipulation instructions class BaseFlagManipulation : I<(outs), iops, asm, ops, "", []>, Sched<[WriteI, ReadI, ReadI]> { let Uses = [NZCV]; bits<5> Rn; let Inst{31} = sf; let Inst{30-15} = 0b0111010000000000; let Inst{14} = sz; let Inst{13-10} = 0b0010; let Inst{9-5} = Rn; let Inst{4-0} = 0b01101; } class FlagRotate : BaseFlagManipulation<0b1, 0b0, iops, asm, ops> { bits<6> imm; bits<4> mask; let Inst{20-15} = imm; let Inst{13-10} = 0b0001; let Inst{4} = 0b0; let Inst{3-0} = mask; } //--- // Basic two-operand data processing instructions. //--- class BaseBaseAddSubCarry pattern> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rd, $Rn, $Rm", "", pattern>, Sched<[WriteI, ReadI, ReadI]> { let Uses = [NZCV]; bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{30} = isSub; let Inst{28-21} = 0b11010000; let Inst{20-16} = Rm; let Inst{15-10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class BaseAddSubCarry : BaseBaseAddSubCarry; class BaseAddSubCarrySetFlags : BaseBaseAddSubCarry { let Defs = [NZCV]; } multiclass AddSubCarry { def Wr : BaseAddSubCarry { let Inst{31} = 0; let Inst{29} = 0; } def Xr : BaseAddSubCarry { let Inst{31} = 1; let Inst{29} = 0; } // Sets flags. def SWr : BaseAddSubCarrySetFlags { let Inst{31} = 0; let Inst{29} = 1; } def SXr : BaseAddSubCarrySetFlags { let Inst{31} = 1; let Inst{29} = 1; } } class BaseTwoOperand opc, RegisterClass regtype, string asm, SDPatternOperator OpNode> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rd, $Rn, $Rm", "", [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{30-21} = 0b0011010110; let Inst{20-16} = Rm; let Inst{15-14} = 0b00; let Inst{13-10} = opc; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class BaseDiv : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> { let Inst{10} = isSigned; } multiclass Div { def Wr : BaseDiv, Sched<[WriteID32, ReadID, ReadID]> { let Inst{31} = 0; } def Xr : BaseDiv, Sched<[WriteID64, ReadID, ReadID]> { let Inst{31} = 1; } } class BaseShift shift_type, RegisterClass regtype, string asm, SDPatternOperator OpNode = null_frag> : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>, Sched<[WriteIS, ReadI]> { let Inst{11-10} = shift_type; } multiclass Shift shift_type, string asm, SDNode OpNode> { def Wr : BaseShift { let Inst{31} = 0; } def Xr : BaseShift { let Inst{31} = 1; } def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)), (!cast(NAME # "Wr") GPR32:$Rn, (EXTRACT_SUBREG i64:$Rm, sub_32))>; def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))), (!cast(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>; def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))), (!cast(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>; def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))), (!cast(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>; } class ShiftAlias : InstAlias; class BaseMulAccum opc, RegisterClass multype, RegisterClass addtype, string asm, list pattern> : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra), asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<5> Ra; let Inst{30-24} = 0b0011011; let Inst{23-21} = opc; let Inst{20-16} = Rm; let Inst{15} = isSub; let Inst{14-10} = Ra; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass MulAccum { // MADD/MSUB generation is decided by MachineCombiner.cpp def Wrrr : BaseMulAccum, Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> { let Inst{31} = 0; } def Xrrr : BaseMulAccum, Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> { let Inst{31} = 1; } } class WideMulAccum opc, string asm, SDNode AccNode, SDNode ExtNode> : BaseMulAccum, Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> { let Inst{31} = 1; } class MulHi opc, string asm, SDNode OpNode> : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm), asm, "\t$Rd, $Rn, $Rm", "", [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>, Sched<[WriteIM64, ReadIM, ReadIM]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-24} = 0b10011011; let Inst{23-21} = opc; let Inst{20-16} = Rm; let Inst{15} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; // The Ra field of SMULH and UMULH is unused: it should be assembled as 31 // (i.e. all bits 1) but is ignored by the processor. let PostEncoderMethod = "fixMulHigh"; } class MulAccumWAlias : InstAlias; class MulAccumXAlias : InstAlias; class WideMulAccumAlias : InstAlias; class BaseCRC32 sz, bit C, RegisterClass StreamReg, SDPatternOperator OpNode, string asm> : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm), asm, "\t$Rd, $Rn, $Rm", "", [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>, Sched<[WriteISReg, ReadI, ReadISReg]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = sf; let Inst{30-21} = 0b0011010110; let Inst{20-16} = Rm; let Inst{15-13} = 0b010; let Inst{12} = C; let Inst{11-10} = sz; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let Predicates = [HasCRC]; } //--- // Address generation. //--- class ADRI pattern> : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "", pattern>, Sched<[WriteI]> { bits<5> Xd; bits<21> label; let Inst{31} = page; let Inst{30-29} = label{1-0}; let Inst{28-24} = 0b10000; let Inst{23-5} = label{20-2}; let Inst{4-0} = Xd; let DecoderMethod = "DecodeAdrInstruction"; } //--- // Move immediate. //--- def movimm32_imm : Operand { let ParserMatchClass = Imm0_65535Operand; let EncoderMethod = "getMoveWideImmOpValue"; let PrintMethod = "printImm"; } def movimm32_shift : Operand { let PrintMethod = "printShifter"; let ParserMatchClass = MovImm32ShifterOperand; } def movimm64_shift : Operand { let PrintMethod = "printShifter"; let ParserMatchClass = MovImm64ShifterOperand; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseMoveImmediate opc, RegisterClass regtype, Operand shifter, string asm> : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift), asm, "\t$Rd, $imm$shift", "", []>, Sched<[WriteImm]> { bits<5> Rd; bits<16> imm; bits<6> shift; let Inst{30-29} = opc; let Inst{28-23} = 0b100101; let Inst{22-21} = shift{5-4}; let Inst{20-5} = imm; let Inst{4-0} = Rd; let DecoderMethod = "DecodeMoveImmInstruction"; } multiclass MoveImmediate opc, string asm> { def Wi : BaseMoveImmediate { let Inst{31} = 0; } def Xi : BaseMoveImmediate { let Inst{31} = 1; } } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseInsertImmediate opc, RegisterClass regtype, Operand shifter, string asm> : I<(outs regtype:$Rd), (ins regtype:$src, movimm32_imm:$imm, shifter:$shift), asm, "\t$Rd, $imm$shift", "$src = $Rd", []>, Sched<[WriteI, ReadI]> { bits<5> Rd; bits<16> imm; bits<6> shift; let Inst{30-29} = opc; let Inst{28-23} = 0b100101; let Inst{22-21} = shift{5-4}; let Inst{20-5} = imm; let Inst{4-0} = Rd; let DecoderMethod = "DecodeMoveImmInstruction"; } multiclass InsertImmediate opc, string asm> { def Wi : BaseInsertImmediate { let Inst{31} = 0; } def Xi : BaseInsertImmediate { let Inst{31} = 1; } } //--- // Add/Subtract //--- class BaseAddSubImm : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm), asm, "\t$Rd, $Rn, $imm", "", [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>, Sched<[WriteI, ReadI]> { bits<5> Rd; bits<5> Rn; bits<14> imm; let Inst{30} = isSub; let Inst{29} = setFlags; let Inst{28-24} = 0b10001; let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12 let Inst{21-10} = imm{11-0}; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let DecoderMethod = "DecodeBaseAddSubImm"; } class BaseAddSubRegPseudo : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>, Sched<[WriteI, ReadI, ReadI]>; class BaseAddSubSReg : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm), asm, "\t$Rd, $Rn, $Rm", "", [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>, Sched<[WriteISReg, ReadI, ReadISReg]> { // The operands are in order to match the 'addr' MI operands, so we // don't need an encoder method and by-name matching. Just use the default // in-order handling. Since we're using by-order, make sure the names // do not match. bits<5> dst; bits<5> src1; bits<5> src2; bits<8> shift; let Inst{30} = isSub; let Inst{29} = setFlags; let Inst{28-24} = 0b01011; let Inst{23-22} = shift{7-6}; let Inst{21} = 0; let Inst{20-16} = src2; let Inst{15-10} = shift{5-0}; let Inst{9-5} = src1; let Inst{4-0} = dst; let DecoderMethod = "DecodeThreeAddrSRegInstruction"; } class BaseAddSubEReg : I<(outs dstRegtype:$R1), (ins src1Regtype:$R2, src2Regtype:$R3), asm, "\t$R1, $R2, $R3", "", [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>, Sched<[WriteIEReg, ReadI, ReadIEReg]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<6> ext; let Inst{30} = isSub; let Inst{29} = setFlags; let Inst{28-24} = 0b01011; let Inst{23-21} = 0b001; let Inst{20-16} = Rm; let Inst{15-13} = ext{5-3}; let Inst{12-10} = ext{2-0}; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let DecoderMethod = "DecodeAddSubERegInstruction"; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseAddSubEReg64 : I<(outs dstRegtype:$Rd), (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext), asm, "\t$Rd, $Rn, $Rm$ext", "", []>, Sched<[WriteIEReg, ReadI, ReadIEReg]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<6> ext; let Inst{30} = isSub; let Inst{29} = setFlags; let Inst{28-24} = 0b01011; let Inst{23-21} = 0b001; let Inst{20-16} = Rm; let Inst{15} = ext{5}; let Inst{12-10} = ext{2-0}; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let DecoderMethod = "DecodeAddSubERegInstruction"; } // Aliases for register+register add/subtract. class AddSubRegAlias : InstAlias; multiclass AddSub { let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in { // Add/Subtract immediate // Increase the weight of the immediate variant to try to match it before // the extended register variant. // We used to match the register variant before the immediate when the // register argument could be implicitly zero-extended. let AddedComplexity = 6 in def Wri : BaseAddSubImm { let Inst{31} = 0; } let AddedComplexity = 6 in def Xri : BaseAddSubImm { let Inst{31} = 1; } // Add/Subtract register - Only used for CodeGen def Wrr : BaseAddSubRegPseudo; def Xrr : BaseAddSubRegPseudo; // Add/Subtract shifted register def Wrs : BaseAddSubSReg { let Inst{31} = 0; } def Xrs : BaseAddSubSReg { let Inst{31} = 1; } } // Add/Subtract extended register let AddedComplexity = 1, hasSideEffects = 0 in { def Wrx : BaseAddSubEReg, mnemonic, OpNode> { let Inst{31} = 0; } def Xrx : BaseAddSubEReg, mnemonic, OpNode> { let Inst{31} = 1; } } def Xrx64 : BaseAddSubEReg64 { // UXTX and SXTX only. let Inst{14-13} = 0b11; let Inst{31} = 1; } // add Rd, Rb, -imm -> sub Rd, Rn, imm def : InstSubst(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn, addsub_shifted_imm32_neg:$imm), 0>; def : InstSubst(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn, addsub_shifted_imm64_neg:$imm), 0>; // Register/register aliases with no shift when SP is not used. def : AddSubRegAlias(NAME#"Wrs"), GPR32, GPR32, GPR32, 0>; def : AddSubRegAlias(NAME#"Xrs"), GPR64, GPR64, GPR64, 0>; // Register/register aliases with no shift when either the destination or // first source register is SP. def : AddSubRegAlias(NAME#"Wrx"), GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0 def : AddSubRegAlias(NAME#"Wrx"), GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0 def : AddSubRegAlias(NAME#"Xrx64"), GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0 def : AddSubRegAlias(NAME#"Xrx64"), GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0 } multiclass AddSubS { let isCompare = 1, Defs = [NZCV] in { // Add/Subtract immediate def Wri : BaseAddSubImm { let Inst{31} = 0; } def Xri : BaseAddSubImm { let Inst{31} = 1; } // Add/Subtract register def Wrr : BaseAddSubRegPseudo; def Xrr : BaseAddSubRegPseudo; // Add/Subtract shifted register def Wrs : BaseAddSubSReg { let Inst{31} = 0; } def Xrs : BaseAddSubSReg { let Inst{31} = 1; } // Add/Subtract extended register let AddedComplexity = 1 in { def Wrx : BaseAddSubEReg, mnemonic, OpNode> { let Inst{31} = 0; } def Xrx : BaseAddSubEReg, mnemonic, OpNode> { let Inst{31} = 1; } } def Xrx64 : BaseAddSubEReg64 { // UXTX and SXTX only. let Inst{14-13} = 0b11; let Inst{31} = 1; } } // Defs = [NZCV] // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm def : InstSubst(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn, addsub_shifted_imm32_neg:$imm), 0>; def : InstSubst(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn, addsub_shifted_imm64_neg:$imm), 0>; // Compare aliases def : InstAlias(NAME#"Wri") WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>; def : InstAlias(NAME#"Xri") XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>; def : InstAlias(NAME#"Wrx") WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>; def : InstAlias(NAME#"Xrx") XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>; def : InstAlias(NAME#"Xrx64") XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>; def : InstAlias(NAME#"Wrs") WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>; def : InstAlias(NAME#"Xrs") XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>; // Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm def : InstSubst(NAME#"Wri") WZR, GPR32sp:$src, addsub_shifted_imm32_neg:$imm), 0>; def : InstSubst(NAME#"Xri") XZR, GPR64sp:$src, addsub_shifted_imm64_neg:$imm), 0>; // Compare shorthands def : InstAlias(NAME#"Wrs") WZR, GPR32:$src1, GPR32:$src2, 0), 5>; def : InstAlias(NAME#"Xrs") XZR, GPR64:$src1, GPR64:$src2, 0), 5>; def : InstAlias(NAME#"Wrx") WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>; def : InstAlias(NAME#"Xrx64") XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>; // Register/register aliases with no shift when SP is not used. def : AddSubRegAlias(NAME#"Wrs"), GPR32, GPR32, GPR32, 0>; def : AddSubRegAlias(NAME#"Xrs"), GPR64, GPR64, GPR64, 0>; // Register/register aliases with no shift when the first source register // is SP. def : AddSubRegAlias(NAME#"Wrx"), GPR32, GPR32sponly, GPR32, 16>; // UXTW #0 def : AddSubRegAlias(NAME#"Xrx64"), GPR64, GPR64sponly, GPR64, 24>; // UXTX #0 } //--- // Extract //--- def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>; def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>; class BaseExtractImm patterns> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm), asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>, Sched<[WriteExtr, ReadExtrHi]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<6> imm; let Inst{30-23} = 0b00100111; let Inst{21} = 0; let Inst{20-16} = Rm; let Inst{15-10} = imm; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass ExtractImm { def Wrri : BaseExtractImm { let Inst{31} = 0; let Inst{22} = 0; // imm<5> must be zero. let imm{5} = 0; } def Xrri : BaseExtractImm { let Inst{31} = 1; let Inst{22} = 1; } } //--- // Bitfield //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseBitfieldImm opc, RegisterClass regtype, Operand imm_type, string asm> : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms), asm, "\t$Rd, $Rn, $immr, $imms", "", []>, Sched<[WriteIS, ReadI]> { bits<5> Rd; bits<5> Rn; bits<6> immr; bits<6> imms; let Inst{30-29} = opc; let Inst{28-23} = 0b100110; let Inst{21-16} = immr; let Inst{15-10} = imms; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass BitfieldImm opc, string asm> { def Wri : BaseBitfieldImm { let Inst{31} = 0; let Inst{22} = 0; // imms<5> and immr<5> must be zero, else ReservedValue(). let Inst{21} = 0; let Inst{15} = 0; } def Xri : BaseBitfieldImm { let Inst{31} = 1; let Inst{22} = 1; } } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseBitfieldImmWith2RegArgs opc, RegisterClass regtype, Operand imm_type, string asm> : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr, imm_type:$imms), asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>, Sched<[WriteIS, ReadI]> { bits<5> Rd; bits<5> Rn; bits<6> immr; bits<6> imms; let Inst{30-29} = opc; let Inst{28-23} = 0b100110; let Inst{21-16} = immr; let Inst{15-10} = imms; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass BitfieldImmWith2RegArgs opc, string asm> { def Wri : BaseBitfieldImmWith2RegArgs { let Inst{31} = 0; let Inst{22} = 0; // imms<5> and immr<5> must be zero, else ReservedValue(). let Inst{21} = 0; let Inst{15} = 0; } def Xri : BaseBitfieldImmWith2RegArgs { let Inst{31} = 1; let Inst{22} = 1; } } //--- // Logical //--- // Logical (immediate) class BaseLogicalImm opc, RegisterClass dregtype, RegisterClass sregtype, Operand imm_type, string asm, list pattern> : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm), asm, "\t$Rd, $Rn, $imm", "", pattern>, Sched<[WriteI, ReadI]> { bits<5> Rd; bits<5> Rn; bits<13> imm; let Inst{30-29} = opc; let Inst{28-23} = 0b100100; let Inst{22} = imm{12}; let Inst{21-16} = imm{11-6}; let Inst{15-10} = imm{5-0}; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let DecoderMethod = "DecodeLogicalImmInstruction"; } // Logical (shifted register) class BaseLogicalSReg opc, bit N, RegisterClass regtype, logical_shifted_reg shifted_regtype, string asm, list pattern> : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm), asm, "\t$Rd, $Rn, $Rm", "", pattern>, Sched<[WriteISReg, ReadI, ReadISReg]> { // The operands are in order to match the 'addr' MI operands, so we // don't need an encoder method and by-name matching. Just use the default // in-order handling. Since we're using by-order, make sure the names // do not match. bits<5> dst; bits<5> src1; bits<5> src2; bits<8> shift; let Inst{30-29} = opc; let Inst{28-24} = 0b01010; let Inst{23-22} = shift{7-6}; let Inst{21} = N; let Inst{20-16} = src2; let Inst{15-10} = shift{5-0}; let Inst{9-5} = src1; let Inst{4-0} = dst; let DecoderMethod = "DecodeThreeAddrSRegInstruction"; } // Aliases for register+register logical instructions. class LogicalRegAlias : InstAlias; multiclass LogicalImm opc, string mnemonic, SDNode OpNode, string Alias> { let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in def Wri : BaseLogicalImm { let Inst{31} = 0; let Inst{22} = 0; // 64-bit version has an additional bit of immediate. } let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in def Xri : BaseLogicalImm { let Inst{31} = 1; } def : InstSubst(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn, logical_imm32_not:$imm), 0>; def : InstSubst(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn, logical_imm64_not:$imm), 0>; } multiclass LogicalImmS opc, string mnemonic, SDNode OpNode, string Alias> { let isCompare = 1, Defs = [NZCV] in { def Wri : BaseLogicalImm { let Inst{31} = 0; let Inst{22} = 0; // 64-bit version has an additional bit of immediate. } def Xri : BaseLogicalImm { let Inst{31} = 1; } } // end Defs = [NZCV] def : InstSubst(NAME # "Wri") GPR32:$Rd, GPR32:$Rn, logical_imm32_not:$imm), 0>; def : InstSubst(NAME # "Xri") GPR64:$Rd, GPR64:$Rn, logical_imm64_not:$imm), 0>; } class BaseLogicalRegPseudo : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>, Sched<[WriteI, ReadI, ReadI]>; // Split from LogicalImm as not all instructions have both. multiclass LogicalReg opc, bit N, string mnemonic, SDPatternOperator OpNode> { let isReMaterializable = 1, isAsCheapAsAMove = 1 in { def Wrr : BaseLogicalRegPseudo; def Xrr : BaseLogicalRegPseudo; } def Wrs : BaseLogicalSReg { let Inst{31} = 0; } def Xrs : BaseLogicalSReg { let Inst{31} = 1; } def : LogicalRegAlias(NAME#"Wrs"), GPR32>; def : LogicalRegAlias(NAME#"Xrs"), GPR64>; } // Split from LogicalReg to allow setting NZCV Defs multiclass LogicalRegS opc, bit N, string mnemonic, SDPatternOperator OpNode = null_frag> { let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def Wrr : BaseLogicalRegPseudo; def Xrr : BaseLogicalRegPseudo; def Wrs : BaseLogicalSReg { let Inst{31} = 0; } def Xrs : BaseLogicalSReg { let Inst{31} = 1; } } // Defs = [NZCV] def : LogicalRegAlias(NAME#"Wrs"), GPR32>; def : LogicalRegAlias(NAME#"Xrs"), GPR64>; } //--- // Conditionally set flags //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseCondComparisonImm : I<(outs), (ins regtype:$Rn, immtype:$imm, imm32_0_15:$nzcv, ccode:$cond), mnemonic, "\t$Rn, $imm, $nzcv, $cond", "", [(set NZCV, (OpNode regtype:$Rn, immtype:$imm, (i32 imm:$nzcv), (i32 imm:$cond), NZCV))]>, Sched<[WriteI, ReadI]> { let Uses = [NZCV]; let Defs = [NZCV]; bits<5> Rn; bits<5> imm; bits<4> nzcv; bits<4> cond; let Inst{30} = op; let Inst{29-21} = 0b111010010; let Inst{20-16} = imm; let Inst{15-12} = cond; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = nzcv; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseCondComparisonReg : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond), mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", [(set NZCV, (OpNode regtype:$Rn, regtype:$Rm, (i32 imm:$nzcv), (i32 imm:$cond), NZCV))]>, Sched<[WriteI, ReadI, ReadI]> { let Uses = [NZCV]; let Defs = [NZCV]; bits<5> Rn; bits<5> Rm; bits<4> nzcv; bits<4> cond; let Inst{30} = op; let Inst{29-21} = 0b111010010; let Inst{20-16} = Rm; let Inst{15-12} = cond; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = nzcv; } multiclass CondComparison { // immediate operand variants def Wi : BaseCondComparisonImm { let Inst{31} = 0; } def Xi : BaseCondComparisonImm { let Inst{31} = 1; } // register operand variants def Wr : BaseCondComparisonReg { let Inst{31} = 0; } def Xr : BaseCondComparisonReg { let Inst{31} = 1; } } //--- // Conditional select //--- class BaseCondSelect op2, RegisterClass regtype, string asm> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond), asm, "\t$Rd, $Rn, $Rm, $cond", "", [(set regtype:$Rd, (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>, Sched<[WriteI, ReadI, ReadI]> { let Uses = [NZCV]; bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<4> cond; let Inst{30} = op; let Inst{29-21} = 0b011010100; let Inst{20-16} = Rm; let Inst{15-12} = cond; let Inst{11-10} = op2; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass CondSelect op2, string asm> { def Wr : BaseCondSelect { let Inst{31} = 0; } def Xr : BaseCondSelect { let Inst{31} = 1; } } class BaseCondSelectOp op2, RegisterClass regtype, string asm, PatFrag frag> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond), asm, "\t$Rd, $Rn, $Rm, $cond", "", [(set regtype:$Rd, (AArch64csel regtype:$Rn, (frag regtype:$Rm), (i32 imm:$cond), NZCV))]>, Sched<[WriteI, ReadI, ReadI]> { let Uses = [NZCV]; bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<4> cond; let Inst{30} = op; let Inst{29-21} = 0b011010100; let Inst{20-16} = Rm; let Inst{15-12} = cond; let Inst{11-10} = op2; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } def inv_cond_XFORM : SDNodeXForm(N->getZExtValue()); return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), SDLoc(N), MVT::i32); }]>; multiclass CondSelectOp op2, string asm, PatFrag frag> { def Wr : BaseCondSelectOp { let Inst{31} = 0; } def Xr : BaseCondSelectOp { let Inst{31} = 1; } def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV), (!cast(NAME # Wr) GPR32:$Rn, GPR32:$Rm, (inv_cond_XFORM imm:$cond))>; def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV), (!cast(NAME # Xr) GPR64:$Rn, GPR64:$Rm, (inv_cond_XFORM imm:$cond))>; } //--- // Special Mask Value //--- def maski8_or_more : Operand, ImmLeaf { } def maski16_or_more : Operand, ImmLeaf { } //--- // Load/store //--- // (unsigned immediate) // Indexed for 8-bit registers. offset is in range [0,4095]. def am_indexed8 : ComplexPattern; def am_indexed16 : ComplexPattern; def am_indexed32 : ComplexPattern; def am_indexed64 : ComplexPattern; def am_indexed128 : ComplexPattern; def gi_am_indexed8 : GIComplexOperandMatcher">, GIComplexPatternEquiv; def gi_am_indexed16 : GIComplexOperandMatcher">, GIComplexPatternEquiv; def gi_am_indexed32 : GIComplexOperandMatcher">, GIComplexPatternEquiv; def gi_am_indexed64 : GIComplexOperandMatcher">, GIComplexPatternEquiv; def gi_am_indexed128 : GIComplexOperandMatcher">, GIComplexPatternEquiv; class UImm12OffsetOperand : AsmOperandClass { let Name = "UImm12Offset" # Scale; let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">"; let PredicateMethod = "isUImm12Offset<" # Scale # ">"; let DiagnosticType = "InvalidMemoryIndexed" # Scale; } def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>; def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>; def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>; def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>; def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>; class uimm12_scaled : Operand { let ParserMatchClass = !cast("UImm12OffsetScale" # Scale # "Operand"); let EncoderMethod = "getLdStUImm12OpValue"; let PrintMethod = "printUImm12Offset<" # Scale # ">"; } def uimm12s1 : uimm12_scaled<1>; def uimm12s2 : uimm12_scaled<2>; def uimm12s4 : uimm12_scaled<4>; def uimm12s8 : uimm12_scaled<8>; def uimm12s16 : uimm12_scaled<16>; class BaseLoadStoreUI sz, bit V, bits<2> opc, dag oops, dag iops, string asm, list pattern> : I { bits<5> Rt; bits<5> Rn; bits<12> offset; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b01; let Inst{23-22} = opc; let Inst{21-10} = offset; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodeUnsignedLdStInstruction"; } multiclass LoadUI sz, bit V, bits<2> opc, RegisterOperand regtype, Operand indextype, string asm, list pattern> { let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def ui : BaseLoadStoreUI, Sched<[WriteLD]>; def : InstAlias(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>; } multiclass StoreUI sz, bit V, bits<2> opc, RegisterOperand regtype, Operand indextype, string asm, list pattern> { let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def ui : BaseLoadStoreUI, Sched<[WriteST]>; def : InstAlias(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>; } // Same as StoreUI, but take a RegisterOperand. This is used by GlobalISel to // substitute zero-registers automatically. // // TODO: Roll out zero-register subtitution to GPR32/GPR64 and fold this back // into StoreUI. multiclass StoreUIz sz, bit V, bits<2> opc, RegisterOperand regtype, Operand indextype, string asm, list pattern> { let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def ui : BaseLoadStoreUI, Sched<[WriteST]>; def : InstAlias(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>; } def PrefetchOperand : AsmOperandClass { let Name = "Prefetch"; let ParserMethod = "tryParsePrefetch"; } def prfop : Operand { let PrintMethod = "printPrefetchOp"; let ParserMatchClass = PrefetchOperand; } let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class PrefetchUI sz, bit V, bits<2> opc, string asm, list pat> : BaseLoadStoreUI, Sched<[WriteLD]>; //--- // Load literal //--- // Load literal address: 19-bit immediate. The low two bits of the target // offset are implied zero and so are not part of the immediate. def am_ldrlit : Operand { let EncoderMethod = "getLoadLiteralOpValue"; let DecoderMethod = "DecodePCRelLabel19"; let PrintMethod = "printAlignedLabel"; let ParserMatchClass = PCRelLabel19Operand; let OperandType = "OPERAND_PCREL"; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in class LoadLiteral opc, bit V, RegisterOperand regtype, string asm> : I<(outs regtype:$Rt), (ins am_ldrlit:$label), asm, "\t$Rt, $label", "", []>, Sched<[WriteLD]> { bits<5> Rt; bits<19> label; let Inst{31-30} = opc; let Inst{29-27} = 0b011; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-5} = label; let Inst{4-0} = Rt; } let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class PrefetchLiteral opc, bit V, string asm, list pat> : I<(outs), (ins prfop:$Rt, am_ldrlit:$label), asm, "\t$Rt, $label", "", pat>, Sched<[WriteLD]> { bits<5> Rt; bits<19> label; let Inst{31-30} = opc; let Inst{29-27} = 0b011; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-5} = label; let Inst{4-0} = Rt; } //--- // Load/store register offset //--- def ro_Xindexed8 : ComplexPattern", []>; def ro_Xindexed16 : ComplexPattern", []>; def ro_Xindexed32 : ComplexPattern", []>; def ro_Xindexed64 : ComplexPattern", []>; def ro_Xindexed128 : ComplexPattern", []>; def ro_Windexed8 : ComplexPattern", []>; def ro_Windexed16 : ComplexPattern", []>; def ro_Windexed32 : ComplexPattern", []>; def ro_Windexed64 : ComplexPattern", []>; def ro_Windexed128 : ComplexPattern", []>; class MemExtendOperand : AsmOperandClass { let Name = "Mem" # Reg # "Extend" # Width; let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">"; let RenderMethod = "addMemExtendOperands"; let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width; } def MemWExtend8Operand : MemExtendOperand<"W", 8> { // The address "[x0, x1, lsl #0]" actually maps to the variant which performs // the trivial shift. let RenderMethod = "addMemExtend8Operands"; } def MemWExtend16Operand : MemExtendOperand<"W", 16>; def MemWExtend32Operand : MemExtendOperand<"W", 32>; def MemWExtend64Operand : MemExtendOperand<"W", 64>; def MemWExtend128Operand : MemExtendOperand<"W", 128>; def MemXExtend8Operand : MemExtendOperand<"X", 8> { // The address "[x0, x1, lsl #0]" actually maps to the variant which performs // the trivial shift. let RenderMethod = "addMemExtend8Operands"; } def MemXExtend16Operand : MemExtendOperand<"X", 16>; def MemXExtend32Operand : MemExtendOperand<"X", 32>; def MemXExtend64Operand : MemExtendOperand<"X", 64>; def MemXExtend128Operand : MemExtendOperand<"X", 128>; class ro_extend : Operand { let ParserMatchClass = ParserClass; let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">"; let DecoderMethod = "DecodeMemExtend"; let EncoderMethod = "getMemExtendOpValue"; let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift); } def ro_Wextend8 : ro_extend; def ro_Wextend16 : ro_extend; def ro_Wextend32 : ro_extend; def ro_Wextend64 : ro_extend; def ro_Wextend128 : ro_extend; def ro_Xextend8 : ro_extend; def ro_Xextend16 : ro_extend; def ro_Xextend32 : ro_extend; def ro_Xextend64 : ro_extend; def ro_Xextend128 : ro_extend; class ROAddrMode { // CodeGen-level pattern covering the entire addressing mode. ComplexPattern Wpat = windex; ComplexPattern Xpat = xindex; // Asm-level Operand covering the valid "uxtw #3" style syntax. Operand Wext = wextend; Operand Xext = xextend; } def ro8 : ROAddrMode; def ro16 : ROAddrMode; def ro32 : ROAddrMode; def ro64 : ROAddrMode; def ro128 : ROAddrMode; class LoadStore8RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list pat> : I { bits<5> Rt; bits<5> Rn; bits<5> Rm; bits<2> extend; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15} = extend{1}; // sign extend Rm? let Inst{14} = 1; let Inst{12} = extend{0}; // do shift? let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } class ROInstAlias : InstAlias; multiclass Load8RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10 in def roW : LoadStore8RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10 in def roX : LoadStore8RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } multiclass Store8RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10 in def roW : LoadStore8RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10 in def roX : LoadStore8RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } class LoadStore16RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list pat> : I { bits<5> Rt; bits<5> Rn; bits<5> Rm; bits<2> extend; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15} = extend{1}; // sign extend Rm? let Inst{14} = 1; let Inst{12} = extend{0}; // do shift? let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } multiclass Load16RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10 in def roW : LoadStore16RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10 in def roX : LoadStore16RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } multiclass Store16RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10 in def roW : LoadStore16RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10 in def roX : LoadStore16RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } class LoadStore32RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list pat> : I { bits<5> Rt; bits<5> Rn; bits<5> Rm; bits<2> extend; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15} = extend{1}; // sign extend Rm? let Inst{14} = 1; let Inst{12} = extend{0}; // do shift? let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } multiclass Load32RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10 in def roW : LoadStore32RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10 in def roX : LoadStore32RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } multiclass Store32RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10 in def roW : LoadStore32RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10 in def roX : LoadStore32RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } class LoadStore64RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list pat> : I { bits<5> Rt; bits<5> Rn; bits<5> Rm; bits<2> extend; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15} = extend{1}; // sign extend Rm? let Inst{14} = 1; let Inst{12} = extend{0}; // do shift? let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } multiclass Load64RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def roW : LoadStore64RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def roX : LoadStore64RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } multiclass Store64RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def roW : LoadStore64RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def roX : LoadStore64RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } class LoadStore128RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list pat> : I { bits<5> Rt; bits<5> Rn; bits<5> Rm; bits<2> extend; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15} = extend{1}; // sign extend Rm? let Inst{14} = 1; let Inst{12} = extend{0}; // do shift? let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } multiclass Load128RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def roW : LoadStore128RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def roX : LoadStore128RO, Sched<[WriteLDIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } multiclass Store128RO sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def roW : LoadStore128RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b0; } let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def roX : LoadStore128RO, Sched<[WriteSTIdx, ReadAdrBase]> { let Inst{13} = 0b1; } def : ROInstAlias(NAME # "roX")>; } let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class BasePrefetchRO sz, bit V, bits<2> opc, dag outs, dag ins, string asm, list pat> : I, Sched<[WriteLD]> { bits<5> Rt; bits<5> Rn; bits<5> Rm; bits<2> extend; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15} = extend{1}; // sign extend Rm? let Inst{14} = 1; let Inst{12} = extend{0}; // do shift? let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; } multiclass PrefetchRO sz, bit V, bits<2> opc, string asm> { def roW : BasePrefetchRO { let Inst{13} = 0b0; } def roX : BasePrefetchRO { let Inst{13} = 0b1; } def : InstAlias<"prfm $Rt, [$Rn, $Rm]", (!cast(NAME # "roX") prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>; } //--- // Load/store unscaled immediate //--- def am_unscaled8 : ComplexPattern; def am_unscaled16 : ComplexPattern; def am_unscaled32 : ComplexPattern; def am_unscaled64 : ComplexPattern; def am_unscaled128 :ComplexPattern; def gi_am_unscaled8 : GIComplexOperandMatcher, GIComplexPatternEquiv; def gi_am_unscaled16 : GIComplexOperandMatcher, GIComplexPatternEquiv; def gi_am_unscaled32 : GIComplexOperandMatcher, GIComplexPatternEquiv; def gi_am_unscaled64 : GIComplexOperandMatcher, GIComplexPatternEquiv; def gi_am_unscaled128 : GIComplexOperandMatcher, GIComplexPatternEquiv; class BaseLoadStoreUnscale sz, bit V, bits<2> opc, dag oops, dag iops, string asm, list pattern> : I { bits<5> Rt; bits<5> Rn; bits<9> offset; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 0; let Inst{20-12} = offset; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodeSignedLdStInstruction"; } // Armv8.4 LDAPR & STLR with Immediate Offset instruction multiclass BaseLoadUnscaleV84 sz, bits<2> opc, RegisterOperand regtype > { def i : BaseLoadStoreUnscale, Sched<[WriteST]> { let Inst{29} = 0; let Inst{24} = 1; } def : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } multiclass BaseStoreUnscaleV84 sz, bits<2> opc, RegisterOperand regtype > { def i : BaseLoadStoreUnscale, Sched<[WriteST]> { let Inst{29} = 0; let Inst{24} = 1; } def : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } multiclass LoadUnscaled sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, list pattern> { let AddedComplexity = 1 in // try this before LoadUI def i : BaseLoadStoreUnscale, Sched<[WriteLD]>; def : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } multiclass StoreUnscaled sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, list pattern> { let AddedComplexity = 1 in // try this before StoreUI def i : BaseLoadStoreUnscale, Sched<[WriteST]>; def : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } multiclass PrefetchUnscaled sz, bit V, bits<2> opc, string asm, list pat> { let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in def i : BaseLoadStoreUnscale, Sched<[WriteLD]>; def : InstAlias(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>; } //--- // Load/store unscaled immediate, unprivileged //--- class BaseLoadStoreUnprivileged sz, bit V, bits<2> opc, dag oops, dag iops, string asm> : I { bits<5> Rt; bits<5> Rn; bits<9> offset; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 0; let Inst{20-12} = offset; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodeSignedLdStInstruction"; } multiclass LoadUnprivileged sz, bit V, bits<2> opc, RegisterClass regtype, string asm> { let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in def i : BaseLoadStoreUnprivileged, Sched<[WriteLD]>; def : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } multiclass StoreUnprivileged sz, bit V, bits<2> opc, RegisterClass regtype, string asm> { let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in def i : BaseLoadStoreUnprivileged, Sched<[WriteST]>; def : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } //--- // Load/store pre-indexed //--- class BaseLoadStorePreIdx sz, bit V, bits<2> opc, dag oops, dag iops, string asm, string cstr, list pat> : I { bits<5> Rt; bits<5> Rn; bits<9> offset; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0; let Inst{23-22} = opc; let Inst{21} = 0; let Inst{20-12} = offset; let Inst{11-10} = 0b11; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodeSignedLdStInstruction"; } let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in class LoadPreIdx sz, bit V, bits<2> opc, RegisterOperand regtype, string asm> : BaseLoadStorePreIdx, Sched<[WriteLD, WriteAdr]>; let mayStore = 1, mayLoad = 0 in class StorePreIdx sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, SDPatternOperator storeop, ValueType Ty> : BaseLoadStorePreIdx, Sched<[WriteAdr, WriteST]>; } // hasSideEffects = 0 //--- // Load/store post-indexed //--- class BaseLoadStorePostIdx sz, bit V, bits<2> opc, dag oops, dag iops, string asm, string cstr, list pat> : I { bits<5> Rt; bits<5> Rn; bits<9> offset; let Inst{31-30} = sz; let Inst{29-27} = 0b111; let Inst{26} = V; let Inst{25-24} = 0b00; let Inst{23-22} = opc; let Inst{21} = 0b0; let Inst{20-12} = offset; let Inst{11-10} = 0b01; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodeSignedLdStInstruction"; } let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in class LoadPostIdx sz, bit V, bits<2> opc, RegisterOperand regtype, string asm> : BaseLoadStorePostIdx, Sched<[WriteLD, WriteAdr]>; let mayStore = 1, mayLoad = 0 in class StorePostIdx sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, SDPatternOperator storeop, ValueType Ty> : BaseLoadStorePostIdx, Sched<[WriteAdr, WriteST]>; } // hasSideEffects = 0 //--- // Load/store pair //--- // (indexed, offset) class BaseLoadStorePairOffset opc, bit V, bit L, dag oops, dag iops, string asm> : I { bits<5> Rt; bits<5> Rt2; bits<5> Rn; bits<7> offset; let Inst{31-30} = opc; let Inst{29-27} = 0b101; let Inst{26} = V; let Inst{25-23} = 0b010; let Inst{22} = L; let Inst{21-15} = offset; let Inst{14-10} = Rt2; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodePairLdStInstruction"; } multiclass LoadPairOffset opc, bit V, RegisterOperand regtype, Operand indextype, string asm> { let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in def i : BaseLoadStorePairOffset, Sched<[WriteLD, WriteLDHi]>; def : InstAlias(NAME # "i") regtype:$Rt, regtype:$Rt2, GPR64sp:$Rn, 0)>; } multiclass StorePairOffset opc, bit V, RegisterOperand regtype, Operand indextype, string asm> { let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in def i : BaseLoadStorePairOffset, Sched<[WriteSTP]>; def : InstAlias(NAME # "i") regtype:$Rt, regtype:$Rt2, GPR64sp:$Rn, 0)>; } // (pre-indexed) class BaseLoadStorePairPreIdx opc, bit V, bit L, dag oops, dag iops, string asm> : I { bits<5> Rt; bits<5> Rt2; bits<5> Rn; bits<7> offset; let Inst{31-30} = opc; let Inst{29-27} = 0b101; let Inst{26} = V; let Inst{25-23} = 0b011; let Inst{22} = L; let Inst{21-15} = offset; let Inst{14-10} = Rt2; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodePairLdStInstruction"; } let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in class LoadPairPreIdx opc, bit V, RegisterOperand regtype, Operand indextype, string asm> : BaseLoadStorePairPreIdx, Sched<[WriteLD, WriteLDHi, WriteAdr]>; let mayStore = 1, mayLoad = 0 in class StorePairPreIdx opc, bit V, RegisterOperand regtype, Operand indextype, string asm> : BaseLoadStorePairPreIdx, Sched<[WriteAdr, WriteSTP]>; } // hasSideEffects = 0 // (post-indexed) class BaseLoadStorePairPostIdx opc, bit V, bit L, dag oops, dag iops, string asm> : I { bits<5> Rt; bits<5> Rt2; bits<5> Rn; bits<7> offset; let Inst{31-30} = opc; let Inst{29-27} = 0b101; let Inst{26} = V; let Inst{25-23} = 0b001; let Inst{22} = L; let Inst{21-15} = offset; let Inst{14-10} = Rt2; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodePairLdStInstruction"; } let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in class LoadPairPostIdx opc, bit V, RegisterOperand regtype, Operand idxtype, string asm> : BaseLoadStorePairPostIdx, Sched<[WriteLD, WriteLDHi, WriteAdr]>; let mayStore = 1, mayLoad = 0 in class StorePairPostIdx opc, bit V, RegisterOperand regtype, Operand idxtype, string asm> : BaseLoadStorePairPostIdx, Sched<[WriteAdr, WriteSTP]>; } // hasSideEffects = 0 // (no-allocate) class BaseLoadStorePairNoAlloc opc, bit V, bit L, dag oops, dag iops, string asm> : I { bits<5> Rt; bits<5> Rt2; bits<5> Rn; bits<7> offset; let Inst{31-30} = opc; let Inst{29-27} = 0b101; let Inst{26} = V; let Inst{25-23} = 0b000; let Inst{22} = L; let Inst{21-15} = offset; let Inst{14-10} = Rt2; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let DecoderMethod = "DecodePairLdStInstruction"; } multiclass LoadPairNoAlloc opc, bit V, RegisterClass regtype, Operand indextype, string asm> { let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in def i : BaseLoadStorePairNoAlloc, Sched<[WriteLD, WriteLDHi]>; def : InstAlias(NAME # "i") regtype:$Rt, regtype:$Rt2, GPR64sp:$Rn, 0)>; } multiclass StorePairNoAlloc opc, bit V, RegisterClass regtype, Operand indextype, string asm> { let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in def i : BaseLoadStorePairNoAlloc, Sched<[WriteSTP]>; def : InstAlias(NAME # "i") regtype:$Rt, regtype:$Rt2, GPR64sp:$Rn, 0)>; } //--- // Load/store exclusive //--- // True exclusive operations write to and/or read from the system's exclusive // monitors, which as far as a compiler is concerned can be modelled as a // random shared memory address. Hence LoadExclusive mayStore. // // Since these instructions have the undefined register bits set to 1 in // their canonical form, we need a post encoder method to set those bits // to 1 when encoding these instructions. We do this using the // fixLoadStoreExclusive function. This function has template parameters: // // fixLoadStoreExclusive // // hasRs indicates that the instruction uses the Rs field, so we won't set // it to 1 (and the same for Rt2). We don't need template parameters for // the other register fields since Rt and Rn are always used. // let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in class BaseLoadStoreExclusive sz, bit o2, bit L, bit o1, bit o0, dag oops, dag iops, string asm, string operands> : I { let Inst{31-30} = sz; let Inst{29-24} = 0b001000; let Inst{23} = o2; let Inst{22} = L; let Inst{21} = o1; let Inst{15} = o0; let DecoderMethod = "DecodeExclusiveLdStInstruction"; } // Neither Rs nor Rt2 operands. class LoadStoreExclusiveSimple sz, bit o2, bit L, bit o1, bit o0, dag oops, dag iops, string asm, string operands> : BaseLoadStoreExclusive { bits<5> Rt; bits<5> Rn; let Inst{20-16} = 0b11111; let Unpredictable{20-16} = 0b11111; let Inst{14-10} = 0b11111; let Unpredictable{14-10} = 0b11111; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; } // Simple load acquires don't set the exclusive monitor let mayLoad = 1, mayStore = 0 in class LoadAcquire sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : LoadStoreExclusiveSimple, Sched<[WriteLD]>; class LoadExclusive sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : LoadStoreExclusiveSimple, Sched<[WriteLD]>; class LoadExclusivePair sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : BaseLoadStoreExclusive, Sched<[WriteLD, WriteLDHi]> { bits<5> Rt; bits<5> Rt2; bits<5> Rn; let Inst{14-10} = Rt2; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; } // Simple store release operations do not check the exclusive monitor. let mayLoad = 0, mayStore = 1 in class StoreRelease sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : LoadStoreExclusiveSimple, Sched<[WriteST]>; let mayLoad = 1, mayStore = 1 in class StoreExclusive sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : BaseLoadStoreExclusive, Sched<[WriteSTX]> { bits<5> Ws; bits<5> Rt; bits<5> Rn; let Inst{20-16} = Ws; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let Constraints = "@earlyclobber $Ws"; let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; } class StoreExclusivePair sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : BaseLoadStoreExclusive, Sched<[WriteSTX]> { bits<5> Ws; bits<5> Rt; bits<5> Rt2; bits<5> Rn; let Inst{20-16} = Ws; let Inst{14-10} = Rt2; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let Constraints = "@earlyclobber $Ws"; } //--- // Exception generation //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class ExceptionGeneration op1, bits<2> ll, string asm> : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>, Sched<[WriteSys]> { bits<16> imm; let Inst{31-24} = 0b11010100; let Inst{23-21} = op1; let Inst{20-5} = imm; let Inst{4-2} = 0b000; let Inst{1-0} = ll; } let Predicates = [HasFPARMv8] in { //--- // Floating point to integer conversion //--- class BaseFPToIntegerUnscaled type, bits<2> rmode, bits<3> opcode, RegisterClass srcType, RegisterClass dstType, string asm, list pattern> : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>, Sched<[WriteFCvt]> { bits<5> Rd; bits<5> Rn; let Inst{30-29} = 0b00; let Inst{28-24} = 0b11110; let Inst{23-22} = type; let Inst{21} = 1; let Inst{20-19} = rmode; let Inst{18-16} = opcode; let Inst{15-10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseFPToInteger type, bits<2> rmode, bits<3> opcode, RegisterClass srcType, RegisterClass dstType, Operand immType, string asm, list pattern> : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale), asm, "\t$Rd, $Rn, $scale", "", pattern>, Sched<[WriteFCvt]> { bits<5> Rd; bits<5> Rn; bits<6> scale; let Inst{30-29} = 0b00; let Inst{28-24} = 0b11110; let Inst{23-22} = type; let Inst{21} = 0; let Inst{20-19} = rmode; let Inst{18-16} = opcode; let Inst{15-10} = scale; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass FPToIntegerUnscaled rmode, bits<3> opcode, string asm, SDPatternOperator OpN> { // Unscaled half-precision to 32-bit def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm, [(set GPR32:$Rd, (OpN FPR16:$Rn))]> { let Inst{31} = 0; // 32-bit GPR flag let Predicates = [HasFullFP16]; } // Unscaled half-precision to 64-bit def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm, [(set GPR64:$Rd, (OpN FPR16:$Rn))]> { let Inst{31} = 1; // 64-bit GPR flag let Predicates = [HasFullFP16]; } // Unscaled single-precision to 32-bit def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm, [(set GPR32:$Rd, (OpN FPR32:$Rn))]> { let Inst{31} = 0; // 32-bit GPR flag } // Unscaled single-precision to 64-bit def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm, [(set GPR64:$Rd, (OpN FPR32:$Rn))]> { let Inst{31} = 1; // 64-bit GPR flag } // Unscaled double-precision to 32-bit def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm, [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> { let Inst{31} = 0; // 32-bit GPR flag } // Unscaled double-precision to 64-bit def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm, [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> { let Inst{31} = 1; // 64-bit GPR flag } } multiclass FPToIntegerScaled rmode, bits<3> opcode, string asm, SDPatternOperator OpN> { // Scaled half-precision to 32-bit def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32, fixedpoint_f16_i32, asm, [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn, fixedpoint_f16_i32:$scale)))]> { let Inst{31} = 0; // 32-bit GPR flag let scale{5} = 1; let Predicates = [HasFullFP16]; } // Scaled half-precision to 64-bit def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64, fixedpoint_f16_i64, asm, [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn, fixedpoint_f16_i64:$scale)))]> { let Inst{31} = 1; // 64-bit GPR flag let Predicates = [HasFullFP16]; } // Scaled single-precision to 32-bit def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32, fixedpoint_f32_i32, asm, [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn, fixedpoint_f32_i32:$scale)))]> { let Inst{31} = 0; // 32-bit GPR flag let scale{5} = 1; } // Scaled single-precision to 64-bit def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64, fixedpoint_f32_i64, asm, [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn, fixedpoint_f32_i64:$scale)))]> { let Inst{31} = 1; // 64-bit GPR flag } // Scaled double-precision to 32-bit def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32, fixedpoint_f64_i32, asm, [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn, fixedpoint_f64_i32:$scale)))]> { let Inst{31} = 0; // 32-bit GPR flag let scale{5} = 1; } // Scaled double-precision to 64-bit def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64, fixedpoint_f64_i64, asm, [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn, fixedpoint_f64_i64:$scale)))]> { let Inst{31} = 1; // 64-bit GPR flag } } //--- // Integer to floating point conversion //--- let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseIntegerToFP pattern> : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale), asm, "\t$Rd, $Rn, $scale", "", pattern>, Sched<[WriteFCvt]> { bits<5> Rd; bits<5> Rn; bits<6> scale; let Inst{30-24} = 0b0011110; let Inst{21-17} = 0b00001; let Inst{16} = isUnsigned; let Inst{15-10} = scale; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class BaseIntegerToFPUnscaled : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>, Sched<[WriteFCvt]> { bits<5> Rd; bits<5> Rn; bits<6> scale; let Inst{30-24} = 0b0011110; let Inst{21-17} = 0b10001; let Inst{16} = isUnsigned; let Inst{15-10} = 0b000000; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass IntegerToFP { // Unscaled def UWHri: BaseIntegerToFPUnscaled { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def UWSri: BaseIntegerToFPUnscaled { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b00; // 32-bit FPR flag } def UWDri: BaseIntegerToFPUnscaled { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b01; // 64-bit FPR flag } def UXHri: BaseIntegerToFPUnscaled { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def UXSri: BaseIntegerToFPUnscaled { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b00; // 32-bit FPR flag } def UXDri: BaseIntegerToFPUnscaled { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b01; // 64-bit FPR flag } // Scaled def SWHri: BaseIntegerToFP { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let scale{5} = 1; let Predicates = [HasFullFP16]; } def SWSri: BaseIntegerToFP { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b00; // 32-bit FPR flag let scale{5} = 1; } def SWDri: BaseIntegerToFP { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b01; // 64-bit FPR flag let scale{5} = 1; } def SXHri: BaseIntegerToFP { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def SXSri: BaseIntegerToFP { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b00; // 32-bit FPR flag } def SXDri: BaseIntegerToFP { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b01; // 64-bit FPR flag } } //--- // Unscaled integer <-> floating point conversion (i.e. FMOV) //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseUnscaledConversion rmode, bits<3> opcode, RegisterClass srcType, RegisterClass dstType, string asm> : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", // We use COPY_TO_REGCLASS for these bitconvert operations. // copyPhysReg() expands the resultant COPY instructions after // regalloc is done. This gives greater freedom for the allocator // and related passes (coalescing, copy propagation, et. al.) to // be more effective. [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>, Sched<[WriteFCopy]> { bits<5> Rd; bits<5> Rn; let Inst{30-24} = 0b0011110; let Inst{21} = 1; let Inst{20-19} = rmode; let Inst{18-16} = opcode; let Inst{15-10} = 0b000000; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseUnscaledConversionToHigh rmode, bits<3> opcode, RegisterClass srcType, RegisterOperand dstType, string asm, string kind> : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm, "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>, Sched<[WriteFCopy]> { bits<5> Rd; bits<5> Rn; let Inst{30-23} = 0b00111101; let Inst{21} = 1; let Inst{20-19} = rmode; let Inst{18-16} = opcode; let Inst{15-10} = 0b000000; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let DecoderMethod = "DecodeFMOVLaneInstruction"; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseUnscaledConversionFromHigh rmode, bits<3> opcode, RegisterOperand srcType, RegisterClass dstType, string asm, string kind> : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm, "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>, Sched<[WriteFCopy]> { bits<5> Rd; bits<5> Rn; let Inst{30-23} = 0b00111101; let Inst{21} = 1; let Inst{20-19} = rmode; let Inst{18-16} = opcode; let Inst{15-10} = 0b000000; let Inst{9-5} = Rn; let Inst{4-0} = Rd; let DecoderMethod = "DecodeFMOVLaneInstruction"; } multiclass UnscaledConversion { def WHr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR16, asm> { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def XHr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR16, asm> { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b00; // 32-bit FPR flag } def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b01; // 64-bit FPR flag } def HWr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR32, asm> { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def HXr : BaseUnscaledConversion<0b00, 0b110, FPR16, GPR64, asm> { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b11; // 16-bit FPR flag let Predicates = [HasFullFP16]; } def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> { let Inst{31} = 0; // 32-bit GPR flag let Inst{23-22} = 0b00; // 32-bit FPR flag } def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> { let Inst{31} = 1; // 64-bit GPR flag let Inst{23-22} = 0b01; // 64-bit FPR flag } def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128, asm, ".d"> { let Inst{31} = 1; let Inst{22} = 0; } def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64, asm, ".d"> { let Inst{31} = 1; let Inst{22} = 0; } } //--- // Floating point conversion //--- class BaseFPConversion type, bits<2> opcode, RegisterClass dstType, RegisterClass srcType, string asm, list pattern> : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>, Sched<[WriteFCvt]> { bits<5> Rd; bits<5> Rn; let Inst{31-24} = 0b00011110; let Inst{23-22} = type; let Inst{21-17} = 0b10001; let Inst{16-15} = opcode; let Inst{14-10} = 0b10000; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass FPConversion { // Double-precision to Half-precision def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm, [(set FPR16:$Rd, (fpround FPR64:$Rn))]>; // Double-precision to Single-precision def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm, [(set FPR32:$Rd, (fpround FPR64:$Rn))]>; // Half-precision to Double-precision def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm, [(set FPR64:$Rd, (fpextend FPR16:$Rn))]>; // Half-precision to Single-precision def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm, [(set FPR32:$Rd, (fpextend FPR16:$Rn))]>; // Single-precision to Double-precision def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm, [(set FPR64:$Rd, (fpextend FPR32:$Rn))]>; // Single-precision to Half-precision def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm, [(set FPR16:$Rd, (fpround FPR32:$Rn))]>; } //--- // Single operand floating point data processing //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSingleOperandFPData opcode, RegisterClass regtype, ValueType vt, string asm, SDPatternOperator node> : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "", [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>, Sched<[WriteF]> { bits<5> Rd; bits<5> Rn; let Inst{31-24} = 0b00011110; let Inst{21-19} = 0b100; let Inst{18-15} = opcode; let Inst{14-10} = 0b10000; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SingleOperandFPData opcode, string asm, SDPatternOperator node = null_frag> { def Hr : BaseSingleOperandFPData { let Inst{23-22} = 0b11; // 16-bit size flag let Predicates = [HasFullFP16]; } def Sr : BaseSingleOperandFPData { let Inst{23-22} = 0b00; // 32-bit size flag } def Dr : BaseSingleOperandFPData { let Inst{23-22} = 0b01; // 64-bit size flag } } //--- // Two operand floating point data processing //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseTwoOperandFPData opcode, RegisterClass regtype, string asm, list pat> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rd, $Rn, $Rm", "", pat>, Sched<[WriteF]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass TwoOperandFPData opcode, string asm, SDPatternOperator node = null_frag> { def Hrr : BaseTwoOperandFPData { let Inst{23-22} = 0b11; // 16-bit size flag let Predicates = [HasFullFP16]; } def Srr : BaseTwoOperandFPData { let Inst{23-22} = 0b00; // 32-bit size flag } def Drr : BaseTwoOperandFPData { let Inst{23-22} = 0b01; // 64-bit size flag } } multiclass TwoOperandFPDataNeg opcode, string asm, SDNode node> { def Hrr : BaseTwoOperandFPData { let Inst{23-22} = 0b11; // 16-bit size flag let Predicates = [HasFullFP16]; } def Srr : BaseTwoOperandFPData { let Inst{23-22} = 0b00; // 32-bit size flag } def Drr : BaseTwoOperandFPData { let Inst{23-22} = 0b01; // 64-bit size flag } } //--- // Three operand floating point data processing //--- class BaseThreeOperandFPData pat> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra), asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>, Sched<[WriteFMul]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<5> Ra; let Inst{31-24} = 0b00011111; let Inst{21} = isNegated; let Inst{20-16} = Rm; let Inst{15} = isSub; let Inst{14-10} = Ra; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass ThreeOperandFPData { def Hrrr : BaseThreeOperandFPData { let Inst{23-22} = 0b11; // 16-bit size flag let Predicates = [HasFullFP16]; } def Srrr : BaseThreeOperandFPData { let Inst{23-22} = 0b00; // 32-bit size flag } def Drrr : BaseThreeOperandFPData { let Inst{23-22} = 0b01; // 64-bit size flag } } //--- // Floating point data comparisons //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseOneOperandFPComparison pat> : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>, Sched<[WriteFCmp]> { bits<5> Rn; let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{15-10} = 0b001000; let Inst{9-5} = Rn; let Inst{4} = signalAllNans; let Inst{3-0} = 0b1000; // Rm should be 0b00000 canonically, but we need to accept any value. let PostEncoderMethod = "fixOneOperandFPComparison"; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseTwoOperandFPComparison pat> : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>, Sched<[WriteFCmp]> { bits<5> Rm; bits<5> Rn; let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-10} = 0b001000; let Inst{9-5} = Rn; let Inst{4} = signalAllNans; let Inst{3-0} = 0b0000; } multiclass FPComparison { let Defs = [NZCV] in { def Hrr : BaseTwoOperandFPComparison { let Inst{23-22} = 0b11; let Predicates = [HasFullFP16]; } def Hri : BaseOneOperandFPComparison { let Inst{23-22} = 0b11; let Predicates = [HasFullFP16]; } def Srr : BaseTwoOperandFPComparison { let Inst{23-22} = 0b00; } def Sri : BaseOneOperandFPComparison { let Inst{23-22} = 0b00; } def Drr : BaseTwoOperandFPComparison { let Inst{23-22} = 0b01; } def Dri : BaseOneOperandFPComparison { let Inst{23-22} = 0b01; } } // Defs = [NZCV] } //--- // Floating point conditional comparisons //--- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseFPCondComparison pat> : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond), mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>, Sched<[WriteFCmp]> { let Uses = [NZCV]; let Defs = [NZCV]; bits<5> Rn; bits<5> Rm; bits<4> nzcv; bits<4> cond; let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = cond; let Inst{11-10} = 0b01; let Inst{9-5} = Rn; let Inst{4} = signalAllNans; let Inst{3-0} = nzcv; } multiclass FPCondComparison { def Hrr : BaseFPCondComparison { let Inst{23-22} = 0b11; let Predicates = [HasFullFP16]; } def Srr : BaseFPCondComparison { let Inst{23-22} = 0b00; } def Drr : BaseFPCondComparison { let Inst{23-22} = 0b01; } } //--- // Floating point conditional select //--- class BaseFPCondSelect : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond), asm, "\t$Rd, $Rn, $Rm, $cond", "", [(set regtype:$Rd, (AArch64csel (vt regtype:$Rn), regtype:$Rm, (i32 imm:$cond), NZCV))]>, Sched<[WriteF]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<4> cond; let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = cond; let Inst{11-10} = 0b11; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass FPCondSelect { let Uses = [NZCV] in { def Hrrr : BaseFPCondSelect { let Inst{23-22} = 0b11; let Predicates = [HasFullFP16]; } def Srrr : BaseFPCondSelect { let Inst{23-22} = 0b00; } def Drrr : BaseFPCondSelect { let Inst{23-22} = 0b01; } } // Uses = [NZCV] } //--- // Floating move immediate //--- class BaseFPMoveImmediate : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "", [(set regtype:$Rd, fpimmtype:$imm)]>, Sched<[WriteFImm]> { bits<5> Rd; bits<8> imm; let Inst{31-24} = 0b00011110; let Inst{21} = 1; let Inst{20-13} = imm; let Inst{12-5} = 0b10000000; let Inst{4-0} = Rd; } multiclass FPMoveImmediate { def Hi : BaseFPMoveImmediate { let Inst{23-22} = 0b11; let Predicates = [HasFullFP16]; } def Si : BaseFPMoveImmediate { let Inst{23-22} = 0b00; } def Di : BaseFPMoveImmediate { let Inst{23-22} = 0b01; } } } // end of 'let Predicates = [HasFPARMv8]' //---------------------------------------------------------------------------- // AdvSIMD //---------------------------------------------------------------------------- let Predicates = [HasNEON] in { //---------------------------------------------------------------------------- // AdvSIMD three register vector instructions //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDThreeSameVector size, bits<5> opcode, RegisterOperand regtype, string asm, string kind, list pattern> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-21} = size; let Inst{20-16} = Rm; let Inst{15-11} = opcode; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDThreeSameVectorTied size, bits<5> opcode, RegisterOperand regtype, string asm, string kind, list pattern> : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-21} = size; let Inst{20-16} = Rm; let Inst{15-11} = opcode; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class BaseSIMDThreeSameVectorDot : BaseSIMDThreeSameVectorTied { let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}"); } multiclass SIMDThreeSameVectorDot { def v8i8 : BaseSIMDThreeSameVectorDot<0, U, asm, ".2s", ".8b", V64, v2i32, v8i8, OpNode>; def v16i8 : BaseSIMDThreeSameVectorDot<1, U, asm, ".4s", ".16b", V128, v4i32, v16i8, OpNode>; } // All operand sizes distinguished in the encoding. multiclass SIMDThreeSameVector opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, asm, ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>; def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128, asm, ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>; def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64, asm, ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>; def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128, asm, ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>; def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64, asm, ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>; def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128, asm, ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>; def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128, asm, ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>; } // As above, but D sized elements unsupported. multiclass SIMDThreeSameVectorBHS opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, asm, ".8b", [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>; def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128, asm, ".16b", [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>; def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64, asm, ".4h", [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>; def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128, asm, ".8h", [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>; def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64, asm, ".2s", [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>; def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128, asm, ".4s", [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>; } multiclass SIMDThreeSameVectorBHSTied opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b001, opc, V64, asm, ".8b", [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>; def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b001, opc, V128, asm, ".16b", [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>; def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b011, opc, V64, asm, ".4h", [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>; def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b011, opc, V128, asm, ".8h", [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>; def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b101, opc, V64, asm, ".2s", [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>; def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b101, opc, V128, asm, ".4s", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>; } // As above, but only B sized elements supported. multiclass SIMDThreeSameVectorB opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, asm, ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>; def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128, asm, ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>; } // As above, but only floating point elements supported. multiclass SIMDThreeSameVectorFP opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64, asm, ".4h", [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>; def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128, asm, ".8h", [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>; } // Predicates = [HasNEON, HasFullFP16] def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64, asm, ".2s", [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>; def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128, asm, ".4s", [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>; def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128, asm, ".2d", [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>; } multiclass SIMDThreeSameVectorFPCmp opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64, asm, ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>; def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128, asm, ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>; } // Predicates = [HasNEON, HasFullFP16] def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64, asm, ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>; def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128, asm, ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>; def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128, asm, ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>; } multiclass SIMDThreeSameVectorFPTied opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorTied<0, U, {S,0b10}, {0b00,opc}, V64, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>; def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128, asm, ".8h", [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>; } // Predicates = [HasNEON, HasFullFP16] def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>; def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128, asm, ".4s", [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>; def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128, asm, ".2d", [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>; } // As above, but D and B sized elements unsupported. multiclass SIMDThreeSameVectorHS opc, string asm, SDPatternOperator OpNode> { def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64, asm, ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>; def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128, asm, ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>; def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64, asm, ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>; def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128, asm, ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>; } // Logical three vector ops share opcode bits, and only use B sized elements. multiclass SIMDLogicalThreeVector size, string asm, SDPatternOperator OpNode = null_frag> { def v8i8 : BaseSIMDThreeSameVector<0, U, {size,1}, 0b00011, V64, asm, ".8b", [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>; def v16i8 : BaseSIMDThreeSameVector<1, U, {size,1}, 0b00011, V128, asm, ".16b", [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>; def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)), (!cast(NAME#"v8i8") V64:$LHS, V64:$RHS)>; def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)), (!cast(NAME#"v8i8") V64:$LHS, V64:$RHS)>; def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)), (!cast(NAME#"v8i8") V64:$LHS, V64:$RHS)>; def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)), (!cast(NAME#"v16i8") V128:$LHS, V128:$RHS)>; def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)), (!cast(NAME#"v16i8") V128:$LHS, V128:$RHS)>; def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)), (!cast(NAME#"v16i8") V128:$LHS, V128:$RHS)>; } multiclass SIMDLogicalThreeVectorTied size, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDThreeSameVectorTied<0, U, {size,1}, 0b00011, V64, asm, ".8b", [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>; def v16i8 : BaseSIMDThreeSameVectorTied<1, U, {size,1}, 0b00011, V128, asm, ".16b", [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>; def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS), (v4i16 V64:$RHS))), (!cast(NAME#"v8i8") V64:$LHS, V64:$MHS, V64:$RHS)>; def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS), (v2i32 V64:$RHS))), (!cast(NAME#"v8i8") V64:$LHS, V64:$MHS, V64:$RHS)>; def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS), (v1i64 V64:$RHS))), (!cast(NAME#"v8i8") V64:$LHS, V64:$MHS, V64:$RHS)>; def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS), (v8i16 V128:$RHS))), (!cast(NAME#"v16i8") V128:$LHS, V128:$MHS, V128:$RHS)>; def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS), (v4i32 V128:$RHS))), (!cast(NAME#"v16i8") V128:$LHS, V128:$MHS, V128:$RHS)>; def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS), (v2i64 V128:$RHS))), (!cast(NAME#"v16i8") V128:$LHS, V128:$MHS, V128:$RHS)>; } //---------------------------------------------------------------------------- // AdvSIMD two register vector instructions. //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDTwoSameVector size, bits<5> opcode, bits<2> size2, RegisterOperand regtype, string asm, string dstkind, string srckind, list pattern> : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "{\t$Rd" # dstkind # ", $Rn" # srckind # "|" # dstkind # "\t$Rd, $Rn}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21} = 0b1; let Inst{20-19} = size2; let Inst{18-17} = 0b00; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDTwoSameVectorTied size, bits<5> opcode, bits<2> size2, RegisterOperand regtype, string asm, string dstkind, string srckind, list pattern> : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm, "{\t$Rd" # dstkind # ", $Rn" # srckind # "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21} = 0b1; let Inst{20-19} = size2; let Inst{18-17} = 0b00; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } // Supports B, H, and S element sizes. multiclass SIMDTwoVectorBHS opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64, asm, ".8b", ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>; def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128, asm, ".16b", ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>; def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>; def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>; def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>; def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>; } class BaseSIMDVectorLShiftLongBySize size, RegisterOperand regtype, string asm, string dstkind, string srckind, string amount> : I<(outs V128:$Rd), (ins regtype:$Rn), asm, "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount # "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29-24} = 0b101110; let Inst{23-22} = size; let Inst{21-10} = 0b100001001110; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDVectorLShiftLongBySizeBHS { let hasSideEffects = 0 in { def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64, "shll", ".8h", ".8b", "8">; def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128, "shll2", ".8h", ".16b", "8">; def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64, "shll", ".4s", ".4h", "16">; def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128, "shll2", ".4s", ".8h", "16">; def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64, "shll", ".2d", ".2s", "32">; def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128, "shll2", ".2d", ".4s", "32">; } } // Supports all element sizes. multiclass SIMDLongTwoVector opc, string asm, SDPatternOperator OpNode> { def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64, asm, ".4h", ".8b", [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>; def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128, asm, ".8h", ".16b", [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>; def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64, asm, ".2s", ".4h", [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>; def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128, asm, ".4s", ".8h", [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>; def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64, asm, ".1d", ".2s", [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>; def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128, asm, ".2d", ".4s", [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>; } multiclass SIMDLongTwoVectorTied opc, string asm, SDPatternOperator OpNode> { def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, 0b00, V64, asm, ".4h", ".8b", [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v8i8 V64:$Rn)))]>; def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128, asm, ".8h", ".16b", [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v16i8 V128:$Rn)))]>; def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64, asm, ".2s", ".4h", [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v4i16 V64:$Rn)))]>; def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128, asm, ".4s", ".8h", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v8i16 V128:$Rn)))]>; def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64, asm, ".1d", ".2s", [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd), (v2i32 V64:$Rn)))]>; def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128, asm, ".2d", ".4s", [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v4i32 V128:$Rn)))]>; } // Supports all element sizes, except 1xD. multiclass SIMDTwoVectorBHSDTied opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, 0b00, V64, asm, ".8b", ".8b", [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>; def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128, asm, ".16b", ".16b", [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>; def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64, asm, ".4h", ".4h", [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>; def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128, asm, ".8h", ".8h", [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>; def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>; def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>; def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, 0b00, V128, asm, ".2d", ".2d", [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>; } multiclass SIMDTwoVectorBHSD opc, string asm, SDPatternOperator OpNode = null_frag> { def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64, asm, ".8b", ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>; def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128, asm, ".16b", ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>; def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>; def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>; def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>; def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>; def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, 0b00, V128, asm, ".2d", ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>; } // Supports only B element sizes. multiclass SIMDTwoVectorB size, bits<5> opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, 0b00, V64, asm, ".8b", ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>; def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, 0b00, V128, asm, ".16b", ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>; } // Supports only B and H element sizes. multiclass SIMDTwoVectorBH opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, 0b00, V64, asm, ".8b", ".8b", [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>; def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128, asm, ".16b", ".16b", [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>; def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>; def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>; } // Supports only S and D element sizes, uses high bit of the size field // as an extra opcode bit. multiclass SIMDTwoVectorFP opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64, asm, ".4h", ".4h", [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>; def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128, asm, ".8h", ".8h", [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>; } // Predicates = [HasNEON, HasFullFP16] def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>; def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>; def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128, asm, ".2d", ".2d", [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>; } // Supports only S element size. multiclass SIMDTwoVectorS opc, string asm, SDPatternOperator OpNode> { def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>; def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>; } multiclass SIMDTwoVectorFPToInt opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>; def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>; } // Predicates = [HasNEON, HasFullFP16] def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>; def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>; def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128, asm, ".2d", ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>; } multiclass SIMDTwoVectorIntToFP opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64, asm, ".4h", ".4h", [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>; def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128, asm, ".8h", ".8h", [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>; } // Predicates = [HasNEON, HasFullFP16] def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64, asm, ".2s", ".2s", [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>; def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128, asm, ".4s", ".4s", [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>; def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128, asm, ".2d", ".2d", [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>; } class BaseSIMDMixedTwoVector size, bits<5> opcode, RegisterOperand inreg, RegisterOperand outreg, string asm, string outkind, string inkind, list pattern> : I<(outs outreg:$Rd), (ins inreg:$Rn), asm, "{\t$Rd" # outkind # ", $Rn" # inkind # "|" # outkind # "\t$Rd, $Rn}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21-17} = 0b10000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class BaseSIMDMixedTwoVectorTied size, bits<5> opcode, RegisterOperand inreg, RegisterOperand outreg, string asm, string outkind, string inkind, list pattern> : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm, "{\t$Rd" # outkind # ", $Rn" # inkind # "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21-17} = 0b10000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDMixedTwoVector opc, string asm, SDPatternOperator OpNode> { def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64, asm, ".8b", ".8h", [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>; def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128, asm#"2", ".16b", ".8h", []>; def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64, asm, ".4h", ".4s", [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>; def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128, asm#"2", ".8h", ".4s", []>; def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64, asm, ".2s", ".2d", [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>; def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128, asm#"2", ".4s", ".2d", []>; def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))), (!cast(NAME # "v16i8") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))), (!cast(NAME # "v8i16") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))), (!cast(NAME # "v4i32") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; } class BaseSIMDCmpTwoVector size, bits<2> size2, bits<5> opcode, RegisterOperand regtype, string asm, string kind, string zero, ValueType dty, ValueType sty, SDNode OpNode> : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero # "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "", [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21} = 0b1; let Inst{20-19} = size2; let Inst{18-17} = 0b00; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } // Comparisons support all element sizes, except 1xD. multiclass SIMDCmpTwoVector opc, string asm, SDNode OpNode> { def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, 0b00, opc, V64, asm, ".8b", "0", v8i8, v8i8, OpNode>; def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, 0b00, opc, V128, asm, ".16b", "0", v16i8, v16i8, OpNode>; def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, 0b00, opc, V64, asm, ".4h", "0", v4i16, v4i16, OpNode>; def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128, asm, ".8h", "0", v8i16, v8i16, OpNode>; def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, 0b00, opc, V64, asm, ".2s", "0", v2i32, v2i32, OpNode>; def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, 0b00, opc, V128, asm, ".4s", "0", v4i32, v4i32, OpNode>; def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128, asm, ".2d", "0", v2i64, v2i64, OpNode>; } // FP Comparisons support only S and D element sizes (and H for v8.2a). multiclass SIMDFPCmpTwoVector opc, string asm, SDNode OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4i16rz : BaseSIMDCmpTwoVector<0, U, {S,1}, 0b11, opc, V64, asm, ".4h", "0.0", v4i16, v4f16, OpNode>; def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128, asm, ".8h", "0.0", v8i16, v8f16, OpNode>; } // Predicates = [HasNEON, HasFullFP16] def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, 0b00, opc, V64, asm, ".2s", "0.0", v2i32, v2f32, OpNode>; def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, 0b00, opc, V128, asm, ".4s", "0.0", v4i32, v4f32, OpNode>; def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128, asm, ".2d", "0.0", v2i64, v2f64, OpNode>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>; def : InstAlias(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>; } def : InstAlias(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>; def : InstAlias(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>; def : InstAlias(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>; def : InstAlias(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>; } def : InstAlias(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>; def : InstAlias(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>; def : InstAlias(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDFPCvtTwoVector size, bits<5> opcode, RegisterOperand outtype, RegisterOperand intype, string asm, string VdTy, string VnTy, list pattern> : I<(outs outtype:$Rd), (ins intype:$Rn), asm, !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21-17} = 0b10000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class BaseSIMDFPCvtTwoVectorTied size, bits<5> opcode, RegisterOperand outtype, RegisterOperand intype, string asm, string VdTy, string VnTy, list pattern> : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm, !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21-17} = 0b10000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDFPWidenTwoVector opc, string asm> { def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64, asm, ".4s", ".4h", []>; def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128, asm#"2", ".4s", ".8h", []>; def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64, asm, ".2d", ".2s", []>; def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128, asm#"2", ".2d", ".4s", []>; } multiclass SIMDFPNarrowTwoVector opc, string asm> { def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128, asm, ".4h", ".4s", []>; def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128, asm#"2", ".8h", ".4s", []>; def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128, asm, ".2s", ".2d", []>; def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128, asm#"2", ".4s", ".2d", []>; } multiclass SIMDFPInexactCvtTwoVector opc, string asm, Intrinsic OpNode> { def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128, asm, ".2s", ".2d", [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>; def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128, asm#"2", ".4s", ".2d", []>; def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))), (!cast(NAME # "v4f32") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; } //---------------------------------------------------------------------------- // AdvSIMD three register different-size vector instructions. //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDDifferentThreeVector size, bits<4> opcode, RegisterOperand outtype, RegisterOperand intype1, RegisterOperand intype2, string asm, string outkind, string inkind1, string inkind2, list pattern> : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm, "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 # "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = size{0}; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size{2-1}; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = opcode; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDDifferentThreeVectorTied size, bits<4> opcode, RegisterOperand outtype, RegisterOperand intype1, RegisterOperand intype2, string asm, string outkind, string inkind1, string inkind2, list pattern> : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm, "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 # "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = size{0}; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size{2-1}; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-12} = opcode; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } // FIXME: TableGen doesn't know how to deal with expanded types that also // change the element count (in this case, placing the results in // the high elements of the result register rather than the low // elements). Until that's fixed, we can't code-gen those. multiclass SIMDNarrowThreeVectorBHS opc, string asm, Intrinsic IntOp> { def v8i16_v8i8 : BaseSIMDDifferentThreeVector; def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied; def v4i32_v4i16 : BaseSIMDDifferentThreeVector; def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied; def v2i64_v2i32 : BaseSIMDDifferentThreeVector; def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied; // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in // a version attached to an instruction. def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm))), (!cast(NAME # "v8i16_v16i8") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm))), (!cast(NAME # "v4i32_v8i16") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm))), (!cast(NAME # "v2i64_v4i32") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; } multiclass SIMDDifferentThreeVectorBD opc, string asm, Intrinsic IntOp> { def v8i8 : BaseSIMDDifferentThreeVector; def v16i8 : BaseSIMDDifferentThreeVector; let Predicates = [HasAES] in { def v1i64 : BaseSIMDDifferentThreeVector; def v2i64 : BaseSIMDDifferentThreeVector; } def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)), (v8i8 (extract_high_v16i8 V128:$Rm)))), (!cast(NAME#"v16i8") V128:$Rn, V128:$Rm)>; } multiclass SIMDLongThreeVectorHS opc, string asm, SDPatternOperator OpNode> { def v4i16_v4i32 : BaseSIMDDifferentThreeVector; def v8i16_v4i32 : BaseSIMDDifferentThreeVector; def v2i32_v2i64 : BaseSIMDDifferentThreeVector; def v4i32_v2i64 : BaseSIMDDifferentThreeVector; } multiclass SIMDLongThreeVectorBHSabdl opc, string asm, SDPatternOperator OpNode = null_frag> { def v8i8_v8i16 : BaseSIMDDifferentThreeVector; def v16i8_v8i16 : BaseSIMDDifferentThreeVector; def v4i16_v4i32 : BaseSIMDDifferentThreeVector; def v8i16_v4i32 : BaseSIMDDifferentThreeVector; def v2i32_v2i64 : BaseSIMDDifferentThreeVector; def v4i32_v2i64 : BaseSIMDDifferentThreeVector; } multiclass SIMDLongThreeVectorTiedBHSabal opc, string asm, SDPatternOperator OpNode> { def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied; def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied; def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied; def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied; def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied; def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied; } multiclass SIMDLongThreeVectorBHS opc, string asm, SDPatternOperator OpNode = null_frag> { def v8i8_v8i16 : BaseSIMDDifferentThreeVector; def v16i8_v8i16 : BaseSIMDDifferentThreeVector; def v4i16_v4i32 : BaseSIMDDifferentThreeVector; def v8i16_v4i32 : BaseSIMDDifferentThreeVector; def v2i32_v2i64 : BaseSIMDDifferentThreeVector; def v4i32_v2i64 : BaseSIMDDifferentThreeVector; } multiclass SIMDLongThreeVectorTiedBHS opc, string asm, SDPatternOperator OpNode> { def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied; def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied; def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied; def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied; def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied; def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied; } multiclass SIMDLongThreeVectorSQDMLXTiedHS opc, string asm, SDPatternOperator Accum> { def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied; def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied; def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied; def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied; } multiclass SIMDWideThreeVectorBHS opc, string asm, SDPatternOperator OpNode> { def v8i8_v8i16 : BaseSIMDDifferentThreeVector; def v16i8_v8i16 : BaseSIMDDifferentThreeVector; def v4i16_v4i32 : BaseSIMDDifferentThreeVector; def v8i16_v4i32 : BaseSIMDDifferentThreeVector; def v2i32_v2i64 : BaseSIMDDifferentThreeVector; def v4i32_v2i64 : BaseSIMDDifferentThreeVector; } //---------------------------------------------------------------------------- // AdvSIMD bitwise extract from vector //---------------------------------------------------------------------------- class BaseSIMDBitwiseExtract : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" # "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "", [(set (vty regtype:$Rd), (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<4> imm; let Inst{31} = 0; let Inst{30} = size; let Inst{29-21} = 0b101110000; let Inst{20-16} = Rm; let Inst{15} = 0; let Inst{14-11} = imm; let Inst{10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDBitwiseExtract { def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> { let imm{3} = 0; } def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">; } //---------------------------------------------------------------------------- // AdvSIMD zip vector //---------------------------------------------------------------------------- class BaseSIMDZipVector size, bits<3> opc, RegisterOperand regtype, string asm, string kind, SDNode OpNode, ValueType valty> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # "|" # kind # "\t$Rd, $Rn, $Rm}", "", [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = size{0}; let Inst{29-24} = 0b001110; let Inst{23-22} = size{2-1}; let Inst{21} = 0; let Inst{20-16} = Rm; let Inst{15} = 0; let Inst{14-12} = opc; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDZipVectoropc, string asm, SDNode OpNode> { def v8i8 : BaseSIMDZipVector<0b000, opc, V64, asm, ".8b", OpNode, v8i8>; def v16i8 : BaseSIMDZipVector<0b001, opc, V128, asm, ".16b", OpNode, v16i8>; def v4i16 : BaseSIMDZipVector<0b010, opc, V64, asm, ".4h", OpNode, v4i16>; def v8i16 : BaseSIMDZipVector<0b011, opc, V128, asm, ".8h", OpNode, v8i16>; def v2i32 : BaseSIMDZipVector<0b100, opc, V64, asm, ".2s", OpNode, v2i32>; def v4i32 : BaseSIMDZipVector<0b101, opc, V128, asm, ".4s", OpNode, v4i32>; def v2i64 : BaseSIMDZipVector<0b111, opc, V128, asm, ".2d", OpNode, v2i64>; def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)), (!cast(NAME#"v4i16") V64:$Rn, V64:$Rm)>; def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)), (!cast(NAME#"v8i16") V128:$Rn, V128:$Rm)>; def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)), (!cast(NAME#"v2i32") V64:$Rn, V64:$Rm)>; def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)), (!cast(NAME#"v4i32") V128:$Rn, V128:$Rm)>; def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)), (!cast(NAME#"v2i64") V128:$Rn, V128:$Rm)>; } //---------------------------------------------------------------------------- // AdvSIMD three register scalar instructions //---------------------------------------------------------------------------- let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDThreeScalar size, bits<5> opcode, RegisterClass regtype, string asm, list pattern> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rd, $Rn, $Rm", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-21} = size; let Inst{20-16} = Rm; let Inst{15-11} = opcode; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDThreeScalarTied size, bit R, bits<5> opcode, dag oops, dag iops, string asm, list pattern> : I, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-22} = size; let Inst{21} = R; let Inst{20-16} = Rm; let Inst{15-11} = opcode; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDThreeScalarD opc, string asm, SDPatternOperator OpNode> { def v1i64 : BaseSIMDThreeScalar; } multiclass SIMDThreeScalarBHSD opc, string asm, SDPatternOperator OpNode> { def v1i64 : BaseSIMDThreeScalar; def v1i32 : BaseSIMDThreeScalar; def v1i16 : BaseSIMDThreeScalar; def v1i8 : BaseSIMDThreeScalar; def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))), (!cast(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>; def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))), (!cast(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>; } multiclass SIMDThreeScalarHS opc, string asm, SDPatternOperator OpNode> { def v1i32 : BaseSIMDThreeScalar; def v1i16 : BaseSIMDThreeScalar; } multiclass SIMDThreeScalarHSTied opc, string asm, SDPatternOperator OpNode = null_frag> { def v1i32: BaseSIMDThreeScalarTied; def v1i16: BaseSIMDThreeScalarTied; } multiclass SIMDFPThreeScalar opc, string asm, SDPatternOperator OpNode = null_frag> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def #NAME#64 : BaseSIMDThreeScalar; def #NAME#32 : BaseSIMDThreeScalar; let Predicates = [HasNEON, HasFullFP16] in { def #NAME#16 : BaseSIMDThreeScalar; } // Predicates = [HasNEON, HasFullFP16] } def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (!cast(NAME # "64") FPR64:$Rn, FPR64:$Rm)>; } multiclass SIMDThreeScalarFPCmp opc, string asm, SDPatternOperator OpNode = null_frag> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def #NAME#64 : BaseSIMDThreeScalar; def #NAME#32 : BaseSIMDThreeScalar; let Predicates = [HasNEON, HasFullFP16] in { def #NAME#16 : BaseSIMDThreeScalar; } // Predicates = [HasNEON, HasFullFP16] } def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (!cast(NAME # "64") FPR64:$Rn, FPR64:$Rm)>; } class BaseSIMDThreeScalarMixed size, bits<5> opcode, dag oops, dag iops, string asm, string cstr, list pat> : I, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-22} = size; let Inst{21} = 1; let Inst{20-16} = Rm; let Inst{15-11} = opcode; let Inst{10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in multiclass SIMDThreeScalarMixedHS opc, string asm, SDPatternOperator OpNode = null_frag> { def i16 : BaseSIMDThreeScalarMixed; def i32 : BaseSIMDThreeScalarMixed; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in multiclass SIMDThreeScalarMixedTiedHS opc, string asm, SDPatternOperator OpNode = null_frag> { def i16 : BaseSIMDThreeScalarMixed; def i32 : BaseSIMDThreeScalarMixed; } //---------------------------------------------------------------------------- // AdvSIMD two register scalar instructions //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDTwoScalar size, bits<2> size2, bits<5> opcode, RegisterClass regtype, RegisterClass regtype2, string asm, list pat> : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm, "\t$Rd, $Rn", "", pat>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-22} = size; let Inst{21} = 0b1; let Inst{20-19} = size2; let Inst{18-17} = 0b00; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDTwoScalarTied size, bits<5> opcode, RegisterClass regtype, RegisterClass regtype2, string asm, list pat> : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm, "\t$Rd, $Rn", "$Rd = $dst", pat>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-22} = size; let Inst{21-17} = 0b10000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDCmpTwoScalar size, bits<2> size2, bits<5> opcode, RegisterClass regtype, string asm, string zero> : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn, #" # zero, "", []>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-22} = size; let Inst{21} = 0b1; let Inst{20-19} = size2; let Inst{18-17} = 0b00; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class SIMDInexactCvtTwoScalar opcode, string asm> : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "", [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31-17} = 0b011111100110000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDCmpTwoScalarD opc, string asm, SDPatternOperator OpNode> { def v1i64rz : BaseSIMDCmpTwoScalar; def : Pat<(v1i64 (OpNode FPR64:$Rn)), (!cast(NAME # v1i64rz) FPR64:$Rn)>; } multiclass SIMDFPCmpTwoScalar opc, string asm, SDPatternOperator OpNode> { def v1i64rz : BaseSIMDCmpTwoScalar; def v1i32rz : BaseSIMDCmpTwoScalar; let Predicates = [HasNEON, HasFullFP16] in { def v1i16rz : BaseSIMDCmpTwoScalar; } def : InstAlias(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>; def : InstAlias(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias(NAME # v1i16rz) FPR16:$Rd, FPR16:$Rn), 0>; } def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))), (!cast(NAME # v1i64rz) FPR64:$Rn)>; } multiclass SIMDTwoScalarD opc, string asm, SDPatternOperator OpNode = null_frag> { def v1i64 : BaseSIMDTwoScalar; def : Pat<(i64 (OpNode (i64 FPR64:$Rn))), (!cast(NAME # "v1i64") FPR64:$Rn)>; } multiclass SIMDFPTwoScalar opc, string asm> { def v1i64 : BaseSIMDTwoScalar; def v1i32 : BaseSIMDTwoScalar; let Predicates = [HasNEON, HasFullFP16] in { def v1f16 : BaseSIMDTwoScalar; } } multiclass SIMDFPTwoScalarCVT opc, string asm, SDPatternOperator OpNode> { def v1i64 : BaseSIMDTwoScalar; def v1i32 : BaseSIMDTwoScalar; let Predicates = [HasNEON, HasFullFP16] in { def v1i16 : BaseSIMDTwoScalar; } } multiclass SIMDTwoScalarBHSD opc, string asm, SDPatternOperator OpNode = null_frag> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def v1i64 : BaseSIMDTwoScalar; def v1i32 : BaseSIMDTwoScalar; def v1i16 : BaseSIMDTwoScalar; def v1i8 : BaseSIMDTwoScalar; } def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))), (!cast(NAME # v1i64) FPR64:$Rn)>; } multiclass SIMDTwoScalarBHSDTied opc, string asm, Intrinsic OpNode> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def v1i64 : BaseSIMDTwoScalarTied; def v1i32 : BaseSIMDTwoScalarTied; def v1i16 : BaseSIMDTwoScalarTied; def v1i8 : BaseSIMDTwoScalarTied; } def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))), (!cast(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in multiclass SIMDTwoScalarMixedBHS opc, string asm, SDPatternOperator OpNode = null_frag> { def v1i32 : BaseSIMDTwoScalar; def v1i16 : BaseSIMDTwoScalar; def v1i8 : BaseSIMDTwoScalar; } //---------------------------------------------------------------------------- // AdvSIMD scalar pairwise instructions //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDPairwiseScalar size, bits<5> opcode, RegisterOperand regtype, RegisterOperand vectype, string asm, string kind> : I<(outs regtype:$Rd), (ins vectype:$Rn), asm, "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-24} = 0b11110; let Inst{23-22} = size; let Inst{21-17} = 0b11000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDPairwiseScalarD opc, string asm> { def v2i64p : BaseSIMDPairwiseScalar; } multiclass SIMDFPPairwiseScalar opc, string asm> { let Predicates = [HasNEON, HasFullFP16] in { def v2i16p : BaseSIMDPairwiseScalar<0, {S,0}, opc, FPR16Op, V64, asm, ".2h">; } def v2i32p : BaseSIMDPairwiseScalar<1, {S,0}, opc, FPR32Op, V64, asm, ".2s">; def v2i64p : BaseSIMDPairwiseScalar<1, {S,1}, opc, FPR64Op, V128, asm, ".2d">; } //---------------------------------------------------------------------------- // AdvSIMD across lanes instructions //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDAcrossLanes size, bits<5> opcode, RegisterClass regtype, RegisterOperand vectype, string asm, string kind, list pattern> : I<(outs regtype:$Rd), (ins vectype:$Rn), asm, "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21-17} = 0b11000; let Inst{16-12} = opcode; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDAcrossLanesBHS opcode, string asm> { def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64, asm, ".8b", []>; def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128, asm, ".16b", []>; def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64, asm, ".4h", []>; def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128, asm, ".8h", []>; def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128, asm, ".4s", []>; } multiclass SIMDAcrossLanesHSD opcode, string asm> { def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64, asm, ".8b", []>; def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128, asm, ".16b", []>; def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64, asm, ".4h", []>; def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128, asm, ".8h", []>; def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128, asm, ".4s", []>; } multiclass SIMDFPAcrossLanes opcode, bit sz1, string asm, Intrinsic intOp> { let Predicates = [HasNEON, HasFullFP16] in { def v4i16v : BaseSIMDAcrossLanes<0, 0, {sz1, 0}, opcode, FPR16, V64, asm, ".4h", [(set FPR16:$Rd, (intOp (v4f16 V64:$Rn)))]>; def v8i16v : BaseSIMDAcrossLanes<1, 0, {sz1, 0}, opcode, FPR16, V128, asm, ".8h", [(set FPR16:$Rd, (intOp (v8f16 V128:$Rn)))]>; } // Predicates = [HasNEON, HasFullFP16] def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128, asm, ".4s", [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>; } //---------------------------------------------------------------------------- // AdvSIMD INS/DUP instructions //---------------------------------------------------------------------------- // FIXME: There has got to be a better way to factor these. ugh. class BaseSIMDInsDup pattern> : I, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = op; let Inst{28-21} = 0b01110000; let Inst{15} = 0; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class SIMDDupFromMain imm5, string size, ValueType vectype, RegisterOperand vecreg, RegisterClass regtype> : BaseSIMDInsDup { let Inst{20-16} = imm5; let Inst{14-11} = 0b0001; } class SIMDDupFromElement : BaseSIMDInsDup { let Inst{14-11} = 0b0000; } class SIMDDup64FromElement : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128, VectorIndexD, i64, AArch64duplane64> { bits<1> idx; let Inst{20} = idx; let Inst{19-16} = 0b1000; } class SIMDDup32FromElement : SIMDDupFromElement { bits<2> idx; let Inst{20-19} = idx; let Inst{18-16} = 0b100; } class SIMDDup16FromElement : SIMDDupFromElement { bits<3> idx; let Inst{20-18} = idx; let Inst{17-16} = 0b10; } class SIMDDup8FromElement : SIMDDupFromElement { bits<4> idx; let Inst{20-17} = idx; let Inst{16} = 1; } class BaseSIMDMov imm4, RegisterClass regtype, Operand idxtype, string asm, list pattern> : BaseSIMDInsDup { let Inst{14-11} = imm4; } class SIMDSMov : BaseSIMDMov; class SIMDUMov : BaseSIMDMov; class SIMDMovAlias : InstAlias; multiclass SMov { def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> { bits<4> idx; let Inst{20-17} = idx; let Inst{16} = 1; } def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> { bits<4> idx; let Inst{20-17} = idx; let Inst{16} = 1; } def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> { bits<3> idx; let Inst{20-18} = idx; let Inst{17-16} = 0b10; } def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> { bits<3> idx; let Inst{20-18} = idx; let Inst{17-16} = 0b10; } def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> { bits<2> idx; let Inst{20-19} = idx; let Inst{18-16} = 0b100; } } multiclass UMov { def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> { bits<4> idx; let Inst{20-17} = idx; let Inst{16} = 1; } def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> { bits<3> idx; let Inst{20-18} = idx; let Inst{17-16} = 0b10; } def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> { bits<2> idx; let Inst{20-19} = idx; let Inst{18-16} = 0b100; } def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> { bits<1> idx; let Inst{20} = idx; let Inst{19-16} = 0b1000; } def : SIMDMovAlias<"mov", ".s", !cast(NAME#"vi32"), GPR32, VectorIndexS>; def : SIMDMovAlias<"mov", ".d", !cast(NAME#"vi64"), GPR64, VectorIndexD>; } class SIMDInsFromMain : BaseSIMDInsDup<1, 0, (outs V128:$dst), (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins", "{\t$Rd" # size # "$idx, $Rn" # "|" # size # "\t$Rd$idx, $Rn}", "$Rd = $dst", [(set V128:$dst, (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> { let Inst{14-11} = 0b0011; } class SIMDInsFromElement : BaseSIMDInsDup<1, 1, (outs V128:$dst), (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins", "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" # "|" # size # "\t$Rd$idx, $Rn$idx2}", "$Rd = $dst", [(set V128:$dst, (vector_insert (vectype V128:$Rd), (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)), idxtype:$idx))]>; class SIMDInsMainMovAlias : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # "|" # size #"\t$dst$idx, $src}", (inst V128:$dst, idxtype:$idx, regtype:$src)>; class SIMDInsElementMovAlias : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" # # "|" # size #"\t$dst$idx, $src$idx2}", (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>; multiclass SIMDIns { def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> { bits<4> idx; let Inst{20-17} = idx; let Inst{16} = 1; } def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> { bits<3> idx; let Inst{20-18} = idx; let Inst{17-16} = 0b10; } def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> { bits<2> idx; let Inst{20-19} = idx; let Inst{18-16} = 0b100; } def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> { bits<1> idx; let Inst{20} = idx; let Inst{19-16} = 0b1000; } def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> { bits<4> idx; bits<4> idx2; let Inst{20-17} = idx; let Inst{16} = 1; let Inst{14-11} = idx2; } def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> { bits<3> idx; bits<3> idx2; let Inst{20-18} = idx; let Inst{17-16} = 0b10; let Inst{14-12} = idx2; let Inst{11} = {?}; } def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> { bits<2> idx; bits<2> idx2; let Inst{20-19} = idx; let Inst{18-16} = 0b100; let Inst{14-13} = idx2; let Inst{12-11} = {?,?}; } def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> { bits<1> idx; bits<1> idx2; let Inst{20} = idx; let Inst{19-16} = 0b1000; let Inst{14} = idx2; let Inst{13-11} = {?,?,?}; } // For all forms of the INS instruction, the "mov" mnemonic is the // preferred alias. Why they didn't just call the instruction "mov" in // the first place is a very good question indeed... def : SIMDInsMainMovAlias<".b", !cast(NAME#"vi8gpr"), GPR32, VectorIndexB>; def : SIMDInsMainMovAlias<".h", !cast(NAME#"vi16gpr"), GPR32, VectorIndexH>; def : SIMDInsMainMovAlias<".s", !cast(NAME#"vi32gpr"), GPR32, VectorIndexS>; def : SIMDInsMainMovAlias<".d", !cast(NAME#"vi64gpr"), GPR64, VectorIndexD>; def : SIMDInsElementMovAlias<".b", !cast(NAME#"vi8lane"), VectorIndexB>; def : SIMDInsElementMovAlias<".h", !cast(NAME#"vi16lane"), VectorIndexH>; def : SIMDInsElementMovAlias<".s", !cast(NAME#"vi32lane"), VectorIndexS>; def : SIMDInsElementMovAlias<".d", !cast(NAME#"vi64lane"), VectorIndexD>; } //---------------------------------------------------------------------------- // AdvSIMD TBL/TBX //---------------------------------------------------------------------------- let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDTableLookup len, bit op, RegisterOperand vectype, RegisterOperand listtype, string asm, string kind> : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm, "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>, Sched<[WriteV]> { bits<5> Vd; bits<5> Vn; bits<5> Vm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29-21} = 0b001110000; let Inst{20-16} = Vm; let Inst{15} = 0; let Inst{14-13} = len; let Inst{12} = op; let Inst{11-10} = 0b00; let Inst{9-5} = Vn; let Inst{4-0} = Vd; } let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDTableLookupTied len, bit op, RegisterOperand vectype, RegisterOperand listtype, string asm, string kind> : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm, "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>, Sched<[WriteV]> { bits<5> Vd; bits<5> Vn; bits<5> Vm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29-21} = 0b001110000; let Inst{20-16} = Vm; let Inst{15} = 0; let Inst{14-13} = len; let Inst{12} = op; let Inst{11-10} = 0b00; let Inst{9-5} = Vn; let Inst{4-0} = Vd; } class SIMDTableLookupAlias : InstAlias; multiclass SIMDTableLookup { def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b, asm, ".8b">; def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b, asm, ".8b">; def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b, asm, ".8b">; def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b, asm, ".8b">; def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b, asm, ".16b">; def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b, asm, ".16b">; def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b, asm, ".16b">; def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b, asm, ".16b">; def : SIMDTableLookupAlias(NAME#"v8i8One"), V64, VecListOne128>; def : SIMDTableLookupAlias(NAME#"v8i8Two"), V64, VecListTwo128>; def : SIMDTableLookupAlias(NAME#"v8i8Three"), V64, VecListThree128>; def : SIMDTableLookupAlias(NAME#"v8i8Four"), V64, VecListFour128>; def : SIMDTableLookupAlias(NAME#"v16i8One"), V128, VecListOne128>; def : SIMDTableLookupAlias(NAME#"v16i8Two"), V128, VecListTwo128>; def : SIMDTableLookupAlias(NAME#"v16i8Three"), V128, VecListThree128>; def : SIMDTableLookupAlias(NAME#"v16i8Four"), V128, VecListFour128>; } multiclass SIMDTableLookupTied { def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b, asm, ".8b">; def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b, asm, ".8b">; def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b, asm, ".8b">; def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b, asm, ".8b">; def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b, asm, ".16b">; def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b, asm, ".16b">; def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b, asm, ".16b">; def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b, asm, ".16b">; def : SIMDTableLookupAlias(NAME#"v8i8One"), V64, VecListOne128>; def : SIMDTableLookupAlias(NAME#"v8i8Two"), V64, VecListTwo128>; def : SIMDTableLookupAlias(NAME#"v8i8Three"), V64, VecListThree128>; def : SIMDTableLookupAlias(NAME#"v8i8Four"), V64, VecListFour128>; def : SIMDTableLookupAlias(NAME#"v16i8One"), V128, VecListOne128>; def : SIMDTableLookupAlias(NAME#"v16i8Two"), V128, VecListTwo128>; def : SIMDTableLookupAlias(NAME#"v16i8Three"), V128, VecListThree128>; def : SIMDTableLookupAlias(NAME#"v16i8Four"), V128, VecListFour128>; } //---------------------------------------------------------------------------- // AdvSIMD scalar CPY //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDScalarCPY : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov", "{\t$dst, $src" # kind # "$idx" # "|\t$dst, $src$idx}", "", []>, Sched<[WriteV]> { bits<5> dst; bits<5> src; let Inst{31-21} = 0b01011110000; let Inst{15-10} = 0b000001; let Inst{9-5} = src; let Inst{4-0} = dst; } class SIMDScalarCPYAlias : InstAlias; multiclass SIMDScalarCPY { def i8 : BaseSIMDScalarCPY { bits<4> idx; let Inst{20-17} = idx; let Inst{16} = 1; } def i16 : BaseSIMDScalarCPY { bits<3> idx; let Inst{20-18} = idx; let Inst{17-16} = 0b10; } def i32 : BaseSIMDScalarCPY { bits<2> idx; let Inst{20-19} = idx; let Inst{18-16} = 0b100; } def i64 : BaseSIMDScalarCPY { bits<1> idx; let Inst{20} = idx; let Inst{19-16} = 0b1000; } def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src), VectorIndexD:$idx)))), (!cast(NAME # i64) V128:$src, VectorIndexD:$idx)>; // 'DUP' mnemonic aliases. def : SIMDScalarCPYAlias<"dup", ".b", !cast(NAME#"i8"), FPR8, V128, VectorIndexB>; def : SIMDScalarCPYAlias<"dup", ".h", !cast(NAME#"i16"), FPR16, V128, VectorIndexH>; def : SIMDScalarCPYAlias<"dup", ".s", !cast(NAME#"i32"), FPR32, V128, VectorIndexS>; def : SIMDScalarCPYAlias<"dup", ".d", !cast(NAME#"i64"), FPR64, V128, VectorIndexD>; } //---------------------------------------------------------------------------- // AdvSIMD modified immediate instructions //---------------------------------------------------------------------------- class BaseSIMDModifiedImm pattern> : I, Sched<[WriteV]> { bits<5> Rd; bits<8> imm8; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = op; let Inst{28-19} = 0b0111100000; let Inst{18-16} = imm8{7-5}; let Inst{11} = op2; let Inst{10} = 1; let Inst{9-5} = imm8{4-0}; let Inst{4-0} = Rd; } class BaseSIMDModifiedImmVector pattern> : BaseSIMDModifiedImm { let DecoderMethod = "DecodeModImmInstruction"; } class BaseSIMDModifiedImmVectorTied pattern> : BaseSIMDModifiedImm { let DecoderMethod = "DecodeModImmTiedInstruction"; } class BaseSIMDModifiedImmVectorShift b15_b12, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVector { bits<2> shift; let Inst{15} = b15_b12{1}; let Inst{14-13} = shift; let Inst{12} = b15_b12{0}; } class BaseSIMDModifiedImmVectorShiftTied b15_b12, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVectorTied { bits<2> shift; let Inst{15} = b15_b12{1}; let Inst{14-13} = shift; let Inst{12} = b15_b12{0}; } class BaseSIMDModifiedImmVectorShiftHalf b15_b12, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVector { bits<2> shift; let Inst{15} = b15_b12{1}; let Inst{14} = 0; let Inst{13} = shift{0}; let Inst{12} = b15_b12{0}; } class BaseSIMDModifiedImmVectorShiftHalfTied b15_b12, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVectorTied { bits<2> shift; let Inst{15} = b15_b12{1}; let Inst{14} = 0; let Inst{13} = shift{0}; let Inst{12} = b15_b12{0}; } multiclass SIMDModifiedImmVectorShift hw_cmode, bits<2> w_cmode, string asm> { def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64, asm, ".4h", []>; def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128, asm, ".8h", []>; def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64, asm, ".2s", []>; def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128, asm, ".4s", []>; } multiclass SIMDModifiedImmVectorShiftTied hw_cmode, bits<2> w_cmode, string asm, SDNode OpNode> { def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64, asm, ".4h", [(set (v4i16 V64:$dst), (OpNode V64:$Rd, imm0_255:$imm8, (i32 imm:$shift)))]>; def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128, asm, ".8h", [(set (v8i16 V128:$dst), (OpNode V128:$Rd, imm0_255:$imm8, (i32 imm:$shift)))]>; def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64, asm, ".2s", [(set (v2i32 V64:$dst), (OpNode V64:$Rd, imm0_255:$imm8, (i32 imm:$shift)))]>; def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128, asm, ".4s", [(set (v4i32 V128:$dst), (OpNode V128:$Rd, imm0_255:$imm8, (i32 imm:$shift)))]>; } class SIMDModifiedImmMoveMSL cmode, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVector { bits<1> shift; let Inst{15-13} = cmode{3-1}; let Inst{12} = shift; } class SIMDModifiedImmVectorNoShift cmode, RegisterOperand vectype, Operand imm_type, string asm, string kind, list pattern> : BaseSIMDModifiedImmVector { let Inst{15-12} = cmode; } class SIMDModifiedImmScalarNoShift cmode, string asm, list pattern> : BaseSIMDModifiedImm { let Inst{15-12} = cmode; let DecoderMethod = "DecodeModImmInstruction"; } //---------------------------------------------------------------------------- // AdvSIMD indexed element //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDIndexed size, bits<4> opc, RegisterOperand dst_reg, RegisterOperand lhs_reg, RegisterOperand rhs_reg, Operand vec_idx, string asm, string apple_kind, string dst_kind, string lhs_kind, string rhs_kind, list pattern> : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm, "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" # "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28} = Scalar; let Inst{27-24} = 0b1111; let Inst{23-22} = size; // Bit 21 must be set by the derived class. let Inst{20-16} = Rm; let Inst{15-12} = opc; // Bit 11 must be set by the derived class. let Inst{10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDIndexedTied size, bits<4> opc, RegisterOperand dst_reg, RegisterOperand lhs_reg, RegisterOperand rhs_reg, Operand vec_idx, string asm, string apple_kind, string dst_kind, string lhs_kind, string rhs_kind, list pattern> : I<(outs dst_reg:$dst), (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm, "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" # "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28} = Scalar; let Inst{27-24} = 0b1111; let Inst{23-22} = size; // Bit 21 must be set by the derived class. let Inst{20-16} = Rm; let Inst{15-12} = opc; // Bit 11 must be set by the derived class. let Inst{10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } // ARMv8.2 Index Dot product instructions class BaseSIMDThreeSameVectorDotIndex : BaseSIMDIndexedTied { bits<2> idx; let Inst{21} = idx{0}; // L let Inst{11} = idx{1}; // H } multiclass SIMDThreeSameVectorDotIndex { def v8i8 : BaseSIMDThreeSameVectorDotIndex<0, U, asm, ".2s", ".8b", ".4b", V64, v2i32, v8i8, OpNode>; def v16i8 : BaseSIMDThreeSameVectorDotIndex<1, U, asm, ".4s", ".16b", ".4b", V128, v4i32, v16i8, OpNode>; } multiclass SIMDFPIndexed opc, string asm, SDPatternOperator OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b00, opc, V64, V64, V128_lo, VectorIndexH, asm, ".4h", ".4h", ".4h", ".h", [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 (AArch64duplane16 (v8f16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b00, opc, V128, V128, V128_lo, VectorIndexH, asm, ".8h", ".8h", ".8h", ".h", [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 (AArch64duplane16 (v8f16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } } // Predicates = [HasNEON, HasFullFP16] def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc, V64, V64, V128, VectorIndexS, asm, ".2s", ".2s", ".2s", ".s", [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm, ".4s", ".4s", ".4s", ".s", [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc, V128, V128, V128, VectorIndexD, asm, ".2d", ".2d", ".2d", ".d", [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> { bits<1> idx; let Inst{11} = idx{0}; let Inst{21} = 0; } let Predicates = [HasNEON, HasFullFP16] in { def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc, FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", [(set (f16 FPR16Op:$Rd), (OpNode (f16 FPR16Op:$Rn), (f16 (vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } } // Predicates = [HasNEON, HasFullFP16] def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc, FPR32Op, FPR32Op, V128, VectorIndexS, asm, ".s", "", "", ".s", [(set (f32 FPR32Op:$Rd), (OpNode (f32 FPR32Op:$Rn), (f32 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc, FPR64Op, FPR64Op, V128, VectorIndexD, asm, ".d", "", "", ".d", [(set (f64 FPR64Op:$Rd), (OpNode (f64 FPR64Op:$Rn), (f64 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))))]> { bits<1> idx; let Inst{11} = idx{0}; let Inst{21} = 0; } } multiclass SIMDFPIndexedTiedPatterns { // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar. def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))), (!cast(INST # v2i32_indexed) V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64dup (f32 FPR32Op:$Rm)))), (!cast(INST # "v2i32_indexed") V64:$Rd, V64:$Rn, (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar. def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))), (!cast(INST # "v4i32_indexed") V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64dup (f32 FPR32Op:$Rm)))), (!cast(INST # "v4i32_indexed") V128:$Rd, V128:$Rn, (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar. def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))), (!cast(INST # "v2i64_indexed") V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64dup (f64 FPR64Op:$Rm)))), (!cast(INST # "v2i64_indexed") V128:$Rd, V128:$Rn, (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; // 2 variants for 32-bit scalar version: extract from .2s or from .4s def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))), (!cast(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))), (!cast(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn, (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; // 1 variant for 64-bit scalar version: extract from .1d or from .2d def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))), (!cast(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn, V128:$Rm, VectorIndexD:$idx)>; } multiclass SIMDFPIndexedTied opc, string asm> { let Predicates = [HasNEON, HasFullFP16] in { def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b00, opc, V64, V64, V128_lo, VectorIndexH, asm, ".4h", ".4h", ".4h", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b00, opc, V128, V128, V128_lo, VectorIndexH, asm, ".8h", ".8h", ".8h", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } } // Predicates = [HasNEON, HasFullFP16] def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64, V128, VectorIndexS, asm, ".2s", ".2s", ".2s", ".s", []> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm, ".4s", ".4s", ".4s", ".s", []> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc, V128, V128, V128, VectorIndexD, asm, ".2d", ".2d", ".2d", ".d", []> { bits<1> idx; let Inst{11} = idx{0}; let Inst{21} = 0; } let Predicates = [HasNEON, HasFullFP16] in { def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc, FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } } // Predicates = [HasNEON, HasFullFP16] def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc, FPR32Op, FPR32Op, V128, VectorIndexS, asm, ".s", "", "", ".s", []> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc, FPR64Op, FPR64Op, V128, VectorIndexD, asm, ".d", "", "", ".d", []> { bits<1> idx; let Inst{11} = idx{0}; let Inst{21} = 0; } } multiclass SIMDIndexedHS opc, string asm, SDPatternOperator OpNode> { def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64, V128_lo, VectorIndexH, asm, ".4h", ".4h", ".4h", ".h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm, ".8h", ".8h", ".8h", ".h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc, V64, V64, V128, VectorIndexS, asm, ".2s", ".2s", ".2s", ".s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm, ".4s", ".4s", ".4s", ".s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc, FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc, FPR32Op, FPR32Op, V128, VectorIndexS, asm, ".s", "", "", ".s", [(set (i32 FPR32Op:$Rd), (OpNode FPR32Op:$Rn, (i32 (vector_extract (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } multiclass SIMDVectorIndexedHS opc, string asm, SDPatternOperator OpNode> { def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64, V128_lo, VectorIndexH, asm, ".4h", ".4h", ".4h", ".h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm, ".8h", ".8h", ".8h", ".h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc, V64, V64, V128, VectorIndexS, asm, ".2s", ".2s", ".2s", ".s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm, ".4s", ".4s", ".4s", ".s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } multiclass SIMDVectorIndexedHSTied opc, string asm, SDPatternOperator OpNode> { def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64, V128_lo, VectorIndexH, asm, ".4h", ".4h", ".4h", ".h", [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm, ".8h", ".8h", ".8h", ".h", [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64, V128, VectorIndexS, asm, ".2s", ".2s", ".2s", ".s", [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm, ".4s", ".4s", ".4s", ".s", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } multiclass SIMDIndexedLongSD opc, string asm, SDPatternOperator OpNode> { def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V128, V64, V128_lo, VectorIndexH, asm, ".4s", ".4s", ".4h", ".h", [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm#"2", ".4s", ".4s", ".8h", ".h", [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn), (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc, V128, V64, V128, VectorIndexS, asm, ".2d", ".2d", ".2s", ".s", [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm#"2", ".2d", ".2d", ".4s", ".s", [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn), (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc, FPR32Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc, FPR64Op, FPR32Op, V128, VectorIndexS, asm, ".s", "", "", ".s", []> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } multiclass SIMDIndexedLongSQDMLXSDTied opc, string asm, SDPatternOperator Accum> { def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V128, V64, V128_lo, VectorIndexH, asm, ".4s", ".4s", ".4h", ".h", [(set (v4i32 V128:$dst), (Accum (v4i32 V128:$Rd), (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an // intermediate EXTRACT_SUBREG would be untyped. def : Pat<(i32 (Accum (i32 FPR32Op:$Rd), (i32 (vector_extract (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx)))), (i64 0))))), (EXTRACT_SUBREG (!cast(NAME # v4i16_indexed) (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn, V128_lo:$Rm, VectorIndexH:$idx), ssub)>; def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm#"2", ".4s", ".4s", ".8h", ".h", [(set (v4i32 V128:$dst), (Accum (v4i32 V128:$Rd), (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn), (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V128, V64, V128, VectorIndexS, asm, ".2d", ".2d", ".2s", ".s", [(set (v2i64 V128:$dst), (Accum (v2i64 V128:$Rd), (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm#"2", ".2d", ".2d", ".4s", ".s", [(set (v2i64 V128:$dst), (Accum (v2i64 V128:$Rd), (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn), (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc, FPR32Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc, FPR64Op, FPR32Op, V128, VectorIndexS, asm, ".s", "", "", ".s", [(set (i64 FPR64Op:$dst), (Accum (i64 FPR64Op:$Rd), (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32Op:$Rn), (i32 (vector_extract (v4i32 V128:$Rm), VectorIndexS:$idx))))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } multiclass SIMDVectorIndexedLongSD opc, string asm, SDPatternOperator OpNode> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V128, V64, V128_lo, VectorIndexH, asm, ".4s", ".4s", ".4h", ".h", [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm#"2", ".4s", ".4s", ".8h", ".h", [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn), (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc, V128, V64, V128, VectorIndexS, asm, ".2d", ".2d", ".2s", ".s", [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm#"2", ".2d", ".2d", ".4s", ".s", [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn), (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } } multiclass SIMDVectorIndexedLongSDTied opc, string asm, SDPatternOperator OpNode> { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V128, V64, V128_lo, VectorIndexH, asm, ".4s", ".4s", ".4h", ".h", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm#"2", ".4s", ".4s", ".8h", ".h", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (extract_high_v8i16 V128:$Rn), (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V128, V64, V128, VectorIndexS, asm, ".2d", ".2d", ".2s", ".s", [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm#"2", ".2d", ".2d", ".4s", ".s", [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (extract_high_v4i32 V128:$Rn), (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } } //---------------------------------------------------------------------------- // AdvSIMD scalar shift by immediate //---------------------------------------------------------------------------- let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDScalarShift opc, bits<7> fixed_imm, RegisterClass regtype1, RegisterClass regtype2, Operand immtype, string asm, list pattern> : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm), asm, "\t$Rd, $Rn, $imm", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<7> imm; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-23} = 0b111110; let Inst{22-16} = fixed_imm; let Inst{15-11} = opc; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDScalarShiftTied opc, bits<7> fixed_imm, RegisterClass regtype1, RegisterClass regtype2, Operand immtype, string asm, list pattern> : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm), asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<7> imm; let Inst{31-30} = 0b01; let Inst{29} = U; let Inst{28-23} = 0b111110; let Inst{22-16} = fixed_imm; let Inst{15-11} = opc; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDFPScalarRShift opc, string asm> { let Predicates = [HasNEON, HasFullFP16] in { def h : BaseSIMDScalarShift { let Inst{19-16} = imm{3-0}; } } // Predicates = [HasNEON, HasFullFP16] def s : BaseSIMDScalarShift { let Inst{20-16} = imm{4-0}; } def d : BaseSIMDScalarShift { let Inst{21-16} = imm{5-0}; } } multiclass SIMDScalarRShiftD opc, string asm, SDPatternOperator OpNode> { def d : BaseSIMDScalarShift { let Inst{21-16} = imm{5-0}; } def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))), (!cast(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>; } multiclass SIMDScalarRShiftDTied opc, string asm, SDPatternOperator OpNode = null_frag> { def d : BaseSIMDScalarShiftTied { let Inst{21-16} = imm{5-0}; } def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))), (!cast(NAME # "d") FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>; } multiclass SIMDScalarLShiftD opc, string asm, SDPatternOperator OpNode> { def d : BaseSIMDScalarShift { let Inst{21-16} = imm{5-0}; } } let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in multiclass SIMDScalarLShiftDTied opc, string asm> { def d : BaseSIMDScalarShiftTied { let Inst{21-16} = imm{5-0}; } } let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in multiclass SIMDScalarRShiftBHS opc, string asm, SDPatternOperator OpNode = null_frag> { def b : BaseSIMDScalarShift { let Inst{18-16} = imm{2-0}; } def h : BaseSIMDScalarShift { let Inst{19-16} = imm{3-0}; } def s : BaseSIMDScalarShift { let Inst{20-16} = imm{4-0}; } } multiclass SIMDScalarLShiftBHSD opc, string asm, SDPatternOperator OpNode> { def b : BaseSIMDScalarShift { let Inst{18-16} = imm{2-0}; } def h : BaseSIMDScalarShift { let Inst{19-16} = imm{3-0}; } def s : BaseSIMDScalarShift { let Inst{20-16} = imm{4-0}; } def d : BaseSIMDScalarShift { let Inst{21-16} = imm{5-0}; } def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))), (!cast(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>; } multiclass SIMDScalarRShiftBHSD opc, string asm> { def b : BaseSIMDScalarShift { let Inst{18-16} = imm{2-0}; } def h : BaseSIMDScalarShift { let Inst{19-16} = imm{3-0}; } def s : BaseSIMDScalarShift { let Inst{20-16} = imm{4-0}; } def d : BaseSIMDScalarShift { let Inst{21-16} = imm{5-0}; } } //---------------------------------------------------------------------------- // AdvSIMD vector x indexed element //---------------------------------------------------------------------------- let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDVectorShift opc, bits<7> fixed_imm, RegisterOperand dst_reg, RegisterOperand src_reg, Operand immtype, string asm, string dst_kind, string src_kind, list pattern> : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm), asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" # "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-23} = 0b011110; let Inst{22-16} = fixed_imm; let Inst{15-11} = opc; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in class BaseSIMDVectorShiftTied opc, bits<7> fixed_imm, RegisterOperand vectype1, RegisterOperand vectype2, Operand immtype, string asm, string dst_kind, string src_kind, list pattern> : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm), asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" # "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-23} = 0b011110; let Inst{22-16} = fixed_imm; let Inst{15-11} = opc; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDVectorRShiftSD opc, string asm, Intrinsic OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?}, V64, V64, vecshiftR16, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (i32 imm:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftR16, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } } // Predicates = [HasNEON, HasFullFP16] def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?}, V64, V64, vecshiftR32, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftR32, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?}, V128, V128, vecshiftR64, asm, ".2d", ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> { bits<6> imm; let Inst{21-16} = imm; } } multiclass SIMDVectorRShiftToFP opc, string asm, Intrinsic OpNode> { let Predicates = [HasNEON, HasFullFP16] in { def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?}, V64, V64, vecshiftR16, asm, ".4h", ".4h", [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 imm:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftR16, asm, ".8h", ".8h", [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } } // Predicates = [HasNEON, HasFullFP16] def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?}, V64, V64, vecshiftR32, asm, ".2s", ".2s", [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftR32, asm, ".4s", ".4s", [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?}, V128, V128, vecshiftR64, asm, ".2d", ".2d", [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> { bits<6> imm; let Inst{21-16} = imm; } } multiclass SIMDVectorRShiftNarrowBHS opc, string asm, SDPatternOperator OpNode> { def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?}, V64, V128, vecshiftR16Narrow, asm, ".8b", ".8h", [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> { bits<3> imm; let Inst{18-16} = imm; } def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?}, V128, V128, vecshiftR16Narrow, asm#"2", ".16b", ".8h", []> { bits<3> imm; let Inst{18-16} = imm; let hasSideEffects = 0; } def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?}, V64, V128, vecshiftR32Narrow, asm, ".4h", ".4s", [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftR32Narrow, asm#"2", ".8h", ".4s", []> { bits<4> imm; let Inst{19-16} = imm; let hasSideEffects = 0; } def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?}, V64, V128, vecshiftR64Narrow, asm, ".2s", ".2d", [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftR64Narrow, asm#"2", ".4s", ".2d", []> { bits<5> imm; let Inst{20-16} = imm; let hasSideEffects = 0; } // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions // themselves, so put them here instead. // Patterns involving what's effectively an insert high and a normal // intrinsic, represented by CONCAT_VECTORS. def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm)), (!cast(NAME # "v16i8_shift") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, vecshiftR16Narrow:$imm)>; def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm)), (!cast(NAME # "v8i16_shift") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, vecshiftR32Narrow:$imm)>; def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm)), (!cast(NAME # "v4i32_shift") (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, vecshiftR64Narrow:$imm)>; } multiclass SIMDVectorLShiftBHSD opc, string asm, SDPatternOperator OpNode> { def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?}, V64, V64, vecshiftL8, asm, ".8b", ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (i32 vecshiftL8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?}, V128, V128, vecshiftL8, asm, ".16b", ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (i32 vecshiftL8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?}, V64, V64, vecshiftL16, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 vecshiftL16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftL16, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 vecshiftL16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?}, V64, V64, vecshiftL32, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 vecshiftL32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftL32, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 vecshiftL32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?}, V128, V128, vecshiftL64, asm, ".2d", ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 vecshiftL64:$imm)))]> { bits<6> imm; let Inst{21-16} = imm; } } multiclass SIMDVectorRShiftBHSD opc, string asm, SDPatternOperator OpNode> { def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?}, V64, V64, vecshiftR8, asm, ".8b", ".8b", [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (i32 vecshiftR8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?}, V128, V128, vecshiftR8, asm, ".16b", ".16b", [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (i32 vecshiftR8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?}, V64, V64, vecshiftR16, asm, ".4h", ".4h", [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 vecshiftR16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftR16, asm, ".8h", ".8h", [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 vecshiftR16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?}, V64, V64, vecshiftR32, asm, ".2s", ".2s", [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 vecshiftR32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftR32, asm, ".4s", ".4s", [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 vecshiftR32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?}, V128, V128, vecshiftR64, asm, ".2d", ".2d", [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 vecshiftR64:$imm)))]> { bits<6> imm; let Inst{21-16} = imm; } } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in multiclass SIMDVectorRShiftBHSDTied opc, string asm, SDPatternOperator OpNode = null_frag> { def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?}, V64, V64, vecshiftR8, asm, ".8b", ".8b", [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (i32 vecshiftR8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?}, V128, V128, vecshiftR8, asm, ".16b", ".16b", [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (i32 vecshiftR8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?}, V64, V64, vecshiftR16, asm, ".4h", ".4h", [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (i32 vecshiftR16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftR16, asm, ".8h", ".8h", [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (i32 vecshiftR16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?}, V64, V64, vecshiftR32, asm, ".2s", ".2s", [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (i32 vecshiftR32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftR32, asm, ".4s", ".4s", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (i32 vecshiftR32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?}, V128, V128, vecshiftR64, asm, ".2d", ".2d", [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn), (i32 vecshiftR64:$imm)))]> { bits<6> imm; let Inst{21-16} = imm; } } multiclass SIMDVectorLShiftBHSDTied opc, string asm, SDPatternOperator OpNode = null_frag> { def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?}, V64, V64, vecshiftL8, asm, ".8b", ".8b", [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (i32 vecshiftL8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?}, V128, V128, vecshiftL8, asm, ".16b", ".16b", [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (i32 vecshiftL8:$imm)))]> { bits<3> imm; let Inst{18-16} = imm; } def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?}, V64, V64, vecshiftL16, asm, ".4h", ".4h", [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (i32 vecshiftL16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftL16, asm, ".8h", ".8h", [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (i32 vecshiftL16:$imm)))]> { bits<4> imm; let Inst{19-16} = imm; } def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?}, V64, V64, vecshiftL32, asm, ".2s", ".2s", [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (i32 vecshiftL32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftL32, asm, ".4s", ".4s", [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (i32 vecshiftL32:$imm)))]> { bits<5> imm; let Inst{20-16} = imm; } def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?}, V128, V128, vecshiftL64, asm, ".2d", ".2d", [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn), (i32 vecshiftL64:$imm)))]> { bits<6> imm; let Inst{21-16} = imm; } } multiclass SIMDVectorLShiftLongBHSD opc, string asm, SDPatternOperator OpNode> { def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?}, V128, V64, vecshiftL8, asm, ".8h", ".8b", [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> { bits<3> imm; let Inst{18-16} = imm; } def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?}, V128, V128, vecshiftL8, asm#"2", ".8h", ".16b", [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> { bits<3> imm; let Inst{18-16} = imm; } def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?}, V128, V64, vecshiftL16, asm, ".4s", ".4h", [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> { bits<4> imm; let Inst{19-16} = imm; } def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?}, V128, V128, vecshiftL16, asm#"2", ".4s", ".8h", [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> { bits<4> imm; let Inst{19-16} = imm; } def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?}, V128, V64, vecshiftL32, asm, ".2d", ".2s", [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> { bits<5> imm; let Inst{20-16} = imm; } def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?}, V128, V128, vecshiftL32, asm#"2", ".2d", ".4s", [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> { bits<5> imm; let Inst{20-16} = imm; } } //--- // Vector load/store //--- // SIMD ldX/stX no-index memory references don't allow the optional // ", #0" constant and handle post-indexing explicitly, so we use // a more specialized parse method for them. Otherwise, it's the same as // the general GPR64sp handling. class BaseSIMDLdSt opcode, bits<2> size, string asm, dag oops, dag iops, list pattern> : I { bits<5> Vt; bits<5> Rn; let Inst{31} = 0; let Inst{30} = Q; let Inst{29-23} = 0b0011000; let Inst{22} = L; let Inst{21-16} = 0b000000; let Inst{15-12} = opcode; let Inst{11-10} = size; let Inst{9-5} = Rn; let Inst{4-0} = Vt; } class BaseSIMDLdStPost opcode, bits<2> size, string asm, dag oops, dag iops> : I { bits<5> Vt; bits<5> Rn; bits<5> Xm; let Inst{31} = 0; let Inst{30} = Q; let Inst{29-23} = 0b0011001; let Inst{22} = L; let Inst{21} = 0; let Inst{20-16} = Xm; let Inst{15-12} = opcode; let Inst{11-10} = size; let Inst{9-5} = Rn; let Inst{4-0} = Vt; } // The immediate form of AdvSIMD post-indexed addressing is encoded with // register post-index addressing from the zero register. multiclass SIMDLdStAliases { // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16" // "ld1\t$Vt, [$Rn], #16" // may get mapped to // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR) def : InstAlias(BaseName # Count # "v" # layout # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # layout):$Vt, XZR), 1>; // E.g. "ld1.8b { v0, v1 }, [x1], #16" // "ld1.8b\t$Vt, [$Rn], #16" // may get mapped to // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR) def : InstAlias(BaseName # Count # "v" # layout # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # Size):$Vt, XZR), 0>; // E.g. "ld1.8b { v0, v1 }, [x1]" // "ld1\t$Vt, [$Rn]" // may get mapped to // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn) def : InstAlias(BaseName # Count # "v" # layout) !cast("VecList" # Count # Size):$Vt, GPR64sp:$Rn), 0>; // E.g. "ld1.8b { v0, v1 }, [x1], x2" // "ld1\t$Vt, [$Rn], $Xm" // may get mapped to // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm) def : InstAlias(BaseName # Count # "v" # layout # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # Size):$Vt, !cast("GPR64pi" # Offset):$Xm), 0>; } multiclass BaseSIMDLdN opcode> { let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm, (outs !cast(veclist # "16b"):$Vt), (ins GPR64sp:$Rn), []>; def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm, (outs !cast(veclist # "8h"):$Vt), (ins GPR64sp:$Rn), []>; def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm, (outs !cast(veclist # "4s"):$Vt), (ins GPR64sp:$Rn), []>; def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm, (outs !cast(veclist # "2d"):$Vt), (ins GPR64sp:$Rn), []>; def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm, (outs !cast(veclist # "8b"):$Vt), (ins GPR64sp:$Rn), []>; def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm, (outs !cast(veclist # "4h"):$Vt), (ins GPR64sp:$Rn), []>; def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm, (outs !cast(veclist # "2s"):$Vt), (ins GPR64sp:$Rn), []>; def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm, (outs GPR64sp:$wback, !cast(veclist # "16b"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm, (outs GPR64sp:$wback, !cast(veclist # "8h"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm, (outs GPR64sp:$wback, !cast(veclist # "4s"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm, (outs GPR64sp:$wback, !cast(veclist # "2d"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm, (outs GPR64sp:$wback, !cast(veclist # "8b"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm, (outs GPR64sp:$wback, !cast(veclist # "4h"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm, (outs GPR64sp:$wback, !cast(veclist # "2s"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; } defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; } // Only ld1/st1 has a v1d version. multiclass BaseSIMDStN opcode> { let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in { def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs), (ins !cast(veclist # "16b"):$Vt, GPR64sp:$Rn), []>; def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs), (ins !cast(veclist # "8h"):$Vt, GPR64sp:$Rn), []>; def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs), (ins !cast(veclist # "4s"):$Vt, GPR64sp:$Rn), []>; def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs), (ins !cast(veclist # "2d"):$Vt, GPR64sp:$Rn), []>; def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs), (ins !cast(veclist # "8b"):$Vt, GPR64sp:$Rn), []>; def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs), (ins !cast(veclist # "4h"):$Vt, GPR64sp:$Rn), []>; def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs), (ins !cast(veclist # "2s"):$Vt, GPR64sp:$Rn), []>; def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "16b"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "8h"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "4s"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "2d"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset128):$Xm)>; def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "8b"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "4h"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "2s"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; } defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; defm : SIMDLdStAliases; } multiclass BaseSIMDLd1 opcode> : BaseSIMDLdN { // LD1 instructions have extra "1d" variants. let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm, (outs !cast(veclist # "1d"):$Vt), (ins GPR64sp:$Rn), []>; def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm, (outs GPR64sp:$wback, !cast(veclist # "1d"):$Vt), (ins GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; } defm : SIMDLdStAliases; } multiclass BaseSIMDSt1 opcode> : BaseSIMDStN { // ST1 instructions have extra "1d" variants. let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs), (ins !cast(veclist # "1d"):$Vt, GPR64sp:$Rn), []>; def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm, (outs GPR64sp:$wback), (ins !cast(veclist # "1d"):$Vt, GPR64sp:$Rn, !cast("GPR64pi" # Offset64):$Xm)>; } defm : SIMDLdStAliases; } multiclass SIMDLd1Multiple { defm One : BaseSIMDLd1; defm Two : BaseSIMDLd1; defm Three : BaseSIMDLd1; defm Four : BaseSIMDLd1; } multiclass SIMDSt1Multiple { defm One : BaseSIMDSt1; defm Two : BaseSIMDSt1; defm Three : BaseSIMDSt1; defm Four : BaseSIMDSt1; } multiclass SIMDLd2Multiple { defm Two : BaseSIMDLdN; } multiclass SIMDSt2Multiple { defm Two : BaseSIMDStN; } multiclass SIMDLd3Multiple { defm Three : BaseSIMDLdN; } multiclass SIMDSt3Multiple { defm Three : BaseSIMDStN; } multiclass SIMDLd4Multiple { defm Four : BaseSIMDLdN; } multiclass SIMDSt4Multiple { defm Four : BaseSIMDStN; } //--- // AdvSIMD Load/store single-element //--- class BaseSIMDLdStSingle opcode, string asm, string operands, string cst, dag oops, dag iops, list pattern> : I { bits<5> Vt; bits<5> Rn; let Inst{31} = 0; let Inst{29-24} = 0b001101; let Inst{22} = L; let Inst{21} = R; let Inst{15-13} = opcode; let Inst{9-5} = Rn; let Inst{4-0} = Vt; } class BaseSIMDLdStSingleTied opcode, string asm, string operands, string cst, dag oops, dag iops, list pattern> : I { bits<5> Vt; bits<5> Rn; let Inst{31} = 0; let Inst{29-24} = 0b001101; let Inst{22} = L; let Inst{21} = R; let Inst{15-13} = opcode; let Inst{9-5} = Rn; let Inst{4-0} = Vt; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in class BaseSIMDLdR opcode, bit S, bits<2> size, string asm, DAGOperand listtype> : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "", (outs listtype:$Vt), (ins GPR64sp:$Rn), []> { let Inst{30} = Q; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = S; let Inst{11-10} = size; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in class BaseSIMDLdRPost opcode, bit S, bits<2> size, string asm, DAGOperand listtype, DAGOperand GPR64pi> : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", (outs GPR64sp:$wback, listtype:$Vt), (ins GPR64sp:$Rn, GPR64pi:$Xm), []> { bits<5> Xm; let Inst{30} = Q; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = S; let Inst{11-10} = size; } multiclass SIMDLdrAliases { // E.g. "ld1r { v0.8b }, [x1], #1" // "ld1r.8b\t$Vt, [$Rn], #1" // may get mapped to // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR) def : InstAlias(BaseName # "v" # layout # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # layout):$Vt, XZR), 1>; // E.g. "ld1r.8b { v0 }, [x1], #1" // "ld1r.8b\t$Vt, [$Rn], #1" // may get mapped to // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR) def : InstAlias(BaseName # "v" # layout # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # Size):$Vt, XZR), 0>; // E.g. "ld1r.8b { v0 }, [x1]" // "ld1r.8b\t$Vt, [$Rn]" // may get mapped to // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn) def : InstAlias(BaseName # "v" # layout) !cast("VecList" # Count # Size):$Vt, GPR64sp:$Rn), 0>; // E.g. "ld1r.8b { v0 }, [x1], x2" // "ld1r.8b\t$Vt, [$Rn], $Xm" // may get mapped to // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm) def : InstAlias(BaseName # "v" # layout # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # Size):$Vt, !cast("GPR64pi" # Offset):$Xm), 0>; } multiclass SIMDLdR opcode, bit S, string asm, string Count, int Offset1, int Offset2, int Offset4, int Offset8> { def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm, !cast("VecList" # Count # "8b")>; def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm, !cast("VecList" # Count #"16b")>; def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm, !cast("VecList" # Count #"4h")>; def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm, !cast("VecList" # Count #"8h")>; def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm, !cast("VecList" # Count #"2s")>; def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm, !cast("VecList" # Count #"4s")>; def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm, !cast("VecList" # Count #"1d")>; def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm, !cast("VecList" # Count #"2d")>; def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm, !cast("VecList" # Count # "8b"), !cast("GPR64pi" # Offset1)>; def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm, !cast("VecList" # Count # "16b"), !cast("GPR64pi" # Offset1)>; def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm, !cast("VecList" # Count # "4h"), !cast("GPR64pi" # Offset2)>; def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm, !cast("VecList" # Count # "8h"), !cast("GPR64pi" # Offset2)>; def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm, !cast("VecList" # Count # "2s"), !cast("GPR64pi" # Offset4)>; def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm, !cast("VecList" # Count # "4s"), !cast("GPR64pi" # Offset4)>; def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm, !cast("VecList" # Count # "1d"), !cast("GPR64pi" # Offset8)>; def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm, !cast("VecList" # Count # "2d"), !cast("GPR64pi" # Offset8)>; defm : SIMDLdrAliases; defm : SIMDLdrAliases; defm : SIMDLdrAliases; defm : SIMDLdrAliases; defm : SIMDLdrAliases; defm : SIMDLdrAliases; defm : SIMDLdrAliases; defm : SIMDLdrAliases; } class SIMDLdStSingleB opcode, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingle { // idx encoded in Q:S:size fields. bits<4> idx; let Inst{30} = idx{3}; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = idx{2}; let Inst{11-10} = idx{1-0}; } class SIMDLdStSingleBTied opcode, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingleTied { // idx encoded in Q:S:size fields. bits<4> idx; let Inst{30} = idx{3}; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = idx{2}; let Inst{11-10} = idx{1-0}; } class SIMDLdStSingleBPost opcode, string asm, dag oops, dag iops> : BaseSIMDLdStSingle { // idx encoded in Q:S:size fields. bits<4> idx; bits<5> Xm; let Inst{30} = idx{3}; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = idx{2}; let Inst{11-10} = idx{1-0}; } class SIMDLdStSingleBTiedPost opcode, string asm, dag oops, dag iops> : BaseSIMDLdStSingleTied { // idx encoded in Q:S:size fields. bits<4> idx; bits<5> Xm; let Inst{30} = idx{3}; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = idx{2}; let Inst{11-10} = idx{1-0}; } class SIMDLdStSingleH opcode, bit size, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingle { // idx encoded in Q:S:size<1> fields. bits<3> idx; let Inst{30} = idx{2}; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = idx{1}; let Inst{11} = idx{0}; let Inst{10} = size; } class SIMDLdStSingleHTied opcode, bit size, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingleTied { // idx encoded in Q:S:size<1> fields. bits<3> idx; let Inst{30} = idx{2}; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = idx{1}; let Inst{11} = idx{0}; let Inst{10} = size; } class SIMDLdStSingleHPost opcode, bit size, string asm, dag oops, dag iops> : BaseSIMDLdStSingle { // idx encoded in Q:S:size<1> fields. bits<3> idx; bits<5> Xm; let Inst{30} = idx{2}; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = idx{1}; let Inst{11} = idx{0}; let Inst{10} = size; } class SIMDLdStSingleHTiedPost opcode, bit size, string asm, dag oops, dag iops> : BaseSIMDLdStSingleTied { // idx encoded in Q:S:size<1> fields. bits<3> idx; bits<5> Xm; let Inst{30} = idx{2}; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = idx{1}; let Inst{11} = idx{0}; let Inst{10} = size; } class SIMDLdStSingleS opcode, bits<2> size, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingle { // idx encoded in Q:S fields. bits<2> idx; let Inst{30} = idx{1}; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = idx{0}; let Inst{11-10} = size; } class SIMDLdStSingleSTied opcode, bits<2> size, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingleTied { // idx encoded in Q:S fields. bits<2> idx; let Inst{30} = idx{1}; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = idx{0}; let Inst{11-10} = size; } class SIMDLdStSingleSPost opcode, bits<2> size, string asm, dag oops, dag iops> : BaseSIMDLdStSingle { // idx encoded in Q:S fields. bits<2> idx; bits<5> Xm; let Inst{30} = idx{1}; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = idx{0}; let Inst{11-10} = size; } class SIMDLdStSingleSTiedPost opcode, bits<2> size, string asm, dag oops, dag iops> : BaseSIMDLdStSingleTied { // idx encoded in Q:S fields. bits<2> idx; bits<5> Xm; let Inst{30} = idx{1}; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = idx{0}; let Inst{11-10} = size; } class SIMDLdStSingleD opcode, bits<2> size, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingle { // idx encoded in Q field. bits<1> idx; let Inst{30} = idx; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = 0; let Inst{11-10} = size; } class SIMDLdStSingleDTied opcode, bits<2> size, string asm, dag oops, dag iops, list pattern> : BaseSIMDLdStSingleTied { // idx encoded in Q field. bits<1> idx; let Inst{30} = idx; let Inst{23} = 0; let Inst{20-16} = 0b00000; let Inst{12} = 0; let Inst{11-10} = size; } class SIMDLdStSingleDPost opcode, bits<2> size, string asm, dag oops, dag iops> : BaseSIMDLdStSingle { // idx encoded in Q field. bits<1> idx; bits<5> Xm; let Inst{30} = idx; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = 0; let Inst{11-10} = size; } class SIMDLdStSingleDTiedPost opcode, bits<2> size, string asm, dag oops, dag iops> : BaseSIMDLdStSingleTied { // idx encoded in Q field. bits<1> idx; bits<5> Xm; let Inst{30} = idx; let Inst{23} = 1; let Inst{20-16} = Xm; let Inst{12} = 0; let Inst{11-10} = size; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in multiclass SIMDLdSingleBTied opcode, string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i8 : SIMDLdStSingleBTied<1, R, opcode, asm, (outs listtype:$dst), (ins listtype:$Vt, VectorIndexB:$idx, GPR64sp:$Rn), []>; def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm, (outs GPR64sp:$wback, listtype:$dst), (ins listtype:$Vt, VectorIndexB:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in multiclass SIMDLdSingleHTied opcode, bit size, string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm, (outs listtype:$dst), (ins listtype:$Vt, VectorIndexH:$idx, GPR64sp:$Rn), []>; def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm, (outs GPR64sp:$wback, listtype:$dst), (ins listtype:$Vt, VectorIndexH:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in multiclass SIMDLdSingleSTied opcode, bits<2> size,string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm, (outs listtype:$dst), (ins listtype:$Vt, VectorIndexS:$idx, GPR64sp:$Rn), []>; def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm, (outs GPR64sp:$wback, listtype:$dst), (ins listtype:$Vt, VectorIndexS:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in multiclass SIMDLdSingleDTied opcode, bits<2> size, string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm, (outs listtype:$dst), (ins listtype:$Vt, VectorIndexD:$idx, GPR64sp:$Rn), []>; def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm, (outs GPR64sp:$wback, listtype:$dst), (ins listtype:$Vt, VectorIndexD:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in multiclass SIMDStSingleB opcode, string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i8 : SIMDLdStSingleB<0, R, opcode, asm, (outs), (ins listtype:$Vt, VectorIndexB:$idx, GPR64sp:$Rn), []>; def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm, (outs GPR64sp:$wback), (ins listtype:$Vt, VectorIndexB:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in multiclass SIMDStSingleH opcode, bit size, string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i16 : SIMDLdStSingleH<0, R, opcode, size, asm, (outs), (ins listtype:$Vt, VectorIndexH:$idx, GPR64sp:$Rn), []>; def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm, (outs GPR64sp:$wback), (ins listtype:$Vt, VectorIndexH:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in multiclass SIMDStSingleS opcode, bits<2> size,string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i32 : SIMDLdStSingleS<0, R, opcode, size, asm, (outs), (ins listtype:$Vt, VectorIndexS:$idx, GPR64sp:$Rn), []>; def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm, (outs GPR64sp:$wback), (ins listtype:$Vt, VectorIndexS:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in multiclass SIMDStSingleD opcode, bits<2> size, string asm, RegisterOperand listtype, RegisterOperand GPR64pi> { def i64 : SIMDLdStSingleD<0, R, opcode, size, asm, (outs), (ins listtype:$Vt, VectorIndexD:$idx, GPR64sp:$Rn), []>; def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm, (outs GPR64sp:$wback), (ins listtype:$Vt, VectorIndexD:$idx, GPR64sp:$Rn, GPR64pi:$Xm)>; } multiclass SIMDLdStSingleAliases { // E.g. "ld1 { v0.8b }[0], [x1], #1" // "ld1\t$Vt, [$Rn], #1" // may get mapped to // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR) def : InstAlias(NAME # Type # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # layout):$Vt, idxtype:$idx, XZR), 1>; // E.g. "ld1.8b { v0 }[0], [x1], #1" // "ld1.8b\t$Vt, [$Rn], #1" // may get mapped to // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR) def : InstAlias(NAME # Type # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # "128"):$Vt, idxtype:$idx, XZR), 0>; // E.g. "ld1.8b { v0 }[0], [x1]" // "ld1.8b\t$Vt, [$Rn]" // may get mapped to // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn) def : InstAlias(NAME # Type) !cast("VecList" # Count # "128"):$Vt, idxtype:$idx, GPR64sp:$Rn), 0>; // E.g. "ld1.8b { v0 }[0], [x1], x2" // "ld1.8b\t$Vt, [$Rn], $Xm" // may get mapped to // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm) def : InstAlias(NAME # Type # "_POST") GPR64sp:$Rn, !cast("VecList" # Count # "128"):$Vt, idxtype:$idx, !cast("GPR64pi" # Offset):$Xm), 0>; } multiclass SIMDLdSt1SingleAliases { defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; } multiclass SIMDLdSt2SingleAliases { defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; } multiclass SIMDLdSt3SingleAliases { defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; } multiclass SIMDLdSt4SingleAliases { defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; defm "" : SIMDLdStSingleAliases; } } // end of 'let Predicates = [HasNEON]' //---------------------------------------------------------------------------- // AdvSIMD v8.1 Rounding Double Multiply Add/Subtract //---------------------------------------------------------------------------- let Predicates = [HasNEON, HasRDM] in { class BaseSIMDThreeSameVectorTiedR0 size, bits<5> opcode, RegisterOperand regtype, string asm, string kind, list pattern> : BaseSIMDThreeSameVectorTied { } multiclass SIMDThreeSameVectorSQRDMLxHTiedHS opc, string asm, SDPatternOperator Accum> { def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h", [(set (v4i16 V64:$dst), (Accum (v4i16 V64:$Rd), (v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>; def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h", [(set (v8i16 V128:$dst), (Accum (v8i16 V128:$Rd), (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn), (v8i16 V128:$Rm)))))]>; def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s", [(set (v2i32 V64:$dst), (Accum (v2i32 V64:$Rd), (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>; def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s", [(set (v4i32 V128:$dst), (Accum (v4i32 V128:$Rd), (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn), (v4i32 V128:$Rm)))))]>; } multiclass SIMDIndexedSQRDMLxHSDTied opc, string asm, SDPatternOperator Accum> { def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64, V128_lo, VectorIndexH, asm, ".4h", ".4h", ".4h", ".h", [(set (v4i16 V64:$dst), (Accum (v4i16 V64:$Rd), (v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn), (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc, V128, V128, V128_lo, VectorIndexH, asm, ".8h", ".8h", ".8h", ".h", [(set (v8i16 V128:$dst), (Accum (v8i16 V128:$Rd), (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn), (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))))]> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64, V128, VectorIndexS, asm, ".2s", ".2s", ".2s", ".s", [(set (v2i32 V64:$dst), (Accum (v2i32 V64:$Rd), (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } // FIXME: it would be nice to use the scalar (v1i32) instruction here, but // an intermediate EXTRACT_SUBREG would be untyped. // FIXME: direct EXTRACT_SUBREG from v2i32 to i32 is illegal, that's why we // got it lowered here as (i32 vector_extract (v4i32 insert_subvector(..))) def : Pat<(i32 (Accum (i32 FPR32Op:$Rd), (i32 (vector_extract (v4i32 (insert_subvector (undef), (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn), (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx)))), (i32 0))), (i64 0))))), (EXTRACT_SUBREG (v2i32 (!cast(NAME # v2i32_indexed) (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), FPR32Op:$Rd, ssub)), V64:$Rn, V128:$Rm, VectorIndexS:$idx)), ssub)>; def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc, V128, V128, V128, VectorIndexS, asm, ".4s", ".4s", ".4s", ".s", [(set (v4i32 V128:$dst), (Accum (v4i32 V128:$Rd), (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn), (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } // FIXME: it would be nice to use the scalar (v1i32) instruction here, but // an intermediate EXTRACT_SUBREG would be untyped. def : Pat<(i32 (Accum (i32 FPR32Op:$Rd), (i32 (vector_extract (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn), (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx)))), (i64 0))))), (EXTRACT_SUBREG (v4i32 (!cast(NAME # v4i32_indexed) (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32Op:$Rd, ssub)), V128:$Rn, V128:$Rm, VectorIndexS:$idx)), ssub)>; def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc, FPR16Op, FPR16Op, V128_lo, VectorIndexH, asm, ".h", "", "", ".h", []> { bits<3> idx; let Inst{11} = idx{2}; let Inst{21} = idx{1}; let Inst{20} = idx{0}; } def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc, FPR32Op, FPR32Op, V128, VectorIndexS, asm, ".s", "", "", ".s", [(set (i32 FPR32Op:$dst), (Accum (i32 FPR32Op:$Rd), (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32Op:$Rn), (i32 (vector_extract (v4i32 V128:$Rm), VectorIndexS:$idx))))))]> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } } // let Predicates = [HasNeon, HasRDM] //---------------------------------------------------------------------------- // ARMv8.3 Complex ADD/MLA instructions //---------------------------------------------------------------------------- class ComplexRotationOperand : AsmOperandClass { let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">"; let DiagnosticType = "InvalidComplexRotation" # Type; let Name = "ComplexRotation" # Type; } def complexrotateop : Operand { let ParserMatchClass = ComplexRotationOperand<90, 0, "Even">; let PrintMethod = "printComplexRotationOp<90, 0>"; } def complexrotateopodd : Operand { let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">; let PrintMethod = "printComplexRotationOp<180, 90>"; } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDThreeSameVectorComplex size, bits<3> opcode, RegisterOperand regtype, Operand rottype, string asm, string kind, list pattern> : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, rottype:$rot), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot" "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<1> rot; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21} = 0; let Inst{20-16} = Rm; let Inst{15-13} = opcode; // Non-tied version (FCADD) only has one rotation bit let Inst{12} = rot; let Inst{11} = 0; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDThreeSameVectorComplexHSD opcode, Operand rottype, string asm, SDPatternOperator OpNode>{ let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm), (rottype i32:$rot)))]>; def v8f16 : BaseSIMDThreeSameVectorComplex<1, U, 0b01, opcode, V128, rottype, asm, ".8h", [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm), (rottype i32:$rot)))]>; } let Predicates = [HasV8_3a, HasNEON] in { def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm), (rottype i32:$rot)))]>; def v4f32 : BaseSIMDThreeSameVectorComplex<1, U, 0b10, opcode, V128, rottype, asm, ".4s", [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm), (rottype i32:$rot)))]>; def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype, asm, ".2d", [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm), (rottype i32:$rot)))]>; } } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDThreeSameVectorTiedComplex size, bits<3> opcode, RegisterOperand regtype, Operand rottype, string asm, string kind, list pattern> : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm, rottype:$rot), asm, "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot" "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<2> rot; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28-24} = 0b01110; let Inst{23-22} = size; let Inst{21} = 0; let Inst{20-16} = Rm; let Inst{15-13} = opcode; let Inst{12-11} = rot; let Inst{10} = 1; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } multiclass SIMDThreeSameVectorTiedComplexHSD opcode, Operand rottype, string asm, SDPatternOperator OpNode> { let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64, rottype, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm), (rottype i32:$rot)))]>; def v8f16 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b01, opcode, V128, rottype, asm, ".8h", [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm), (rottype i32:$rot)))]>; } let Predicates = [HasV8_3a, HasNEON] in { def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64, rottype, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm), (rottype i32:$rot)))]>; def v4f32 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b10, opcode, V128, rottype, asm, ".4s", [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm), (rottype i32:$rot)))]>; def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128, rottype, asm, ".2d", [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm), (rottype i32:$rot)))]>; } } let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseSIMDIndexedTiedComplex size, bit opc1, bit opc2, RegisterOperand dst_reg, RegisterOperand lhs_reg, RegisterOperand rhs_reg, Operand vec_idx, Operand rottype, string asm, string apple_kind, string dst_kind, string lhs_kind, string rhs_kind, list pattern> : I<(outs dst_reg:$dst), (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx, rottype:$rot), asm, "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx, $rot" # "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx, $rot}", "$Rd = $dst", pattern>, Sched<[WriteV]> { bits<5> Rd; bits<5> Rn; bits<5> Rm; bits<2> rot; let Inst{31} = 0; let Inst{30} = Q; let Inst{29} = U; let Inst{28} = Scalar; let Inst{27-24} = 0b1111; let Inst{23-22} = size; // Bit 21 must be set by the derived class. let Inst{20-16} = Rm; let Inst{15} = opc1; let Inst{14-13} = rot; let Inst{12} = opc2; // Bit 11 must be set by the derived class. let Inst{10} = 0; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } // The complex instructions index by pairs of elements, so the VectorIndexes // don't match the lane types, and the index bits are different to the other // classes. multiclass SIMDIndexedTiedComplexHSD { let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in { def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64, V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h", ".4h", ".h", []> { bits<1> idx; let Inst{11} = 0; let Inst{21} = idx{0}; } def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2, V128, V128, V128, VectorIndexS, rottype, asm, ".8h", ".8h", ".8h", ".h", []> { bits<2> idx; let Inst{11} = idx{1}; let Inst{21} = idx{0}; } } // Predicates = [HasV8_3a,HasNEON,HasFullFP16] let Predicates = [HasV8_3a,HasNEON] in { def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2, V128, V128, V128, VectorIndexD, rottype, asm, ".4s", ".4s", ".4s", ".s", []> { bits<1> idx; let Inst{11} = idx{0}; let Inst{21} = 0; } } // Predicates = [HasV8_3a,HasNEON] } //---------------------------------------------------------------------------- // Crypto extensions //---------------------------------------------------------------------------- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class AESBase opc, string asm, dag outs, dag ins, string cstr, list pat> : I, Sched<[WriteV]>{ bits<5> Rd; bits<5> Rn; let Inst{31-16} = 0b0100111000101000; let Inst{15-12} = opc; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class AESInst opc, string asm, Intrinsic OpNode> : AESBase; class AESTiedInst opc, string asm, Intrinsic OpNode> : AESBase; let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class SHA3OpTiedInst opc, string asm, string dst_lhs_kind, dag oops, dag iops, list pat> : I, Sched<[WriteV]>{ bits<5> Rd; bits<5> Rn; bits<5> Rm; let Inst{31-21} = 0b01011110000; let Inst{20-16} = Rm; let Inst{15} = 0; let Inst{14-12} = opc; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class SHATiedInstQSV opc, string asm, Intrinsic OpNode> : SHA3OpTiedInst; class SHATiedInstVVV opc, string asm, Intrinsic OpNode> : SHA3OpTiedInst; class SHATiedInstQQV opc, string asm, Intrinsic OpNode> : SHA3OpTiedInst; let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class SHA2OpInst opc, string asm, string kind, string cstr, dag oops, dag iops, list pat> : I, Sched<[WriteV]>{ bits<5> Rd; bits<5> Rn; let Inst{31-16} = 0b0101111000101000; let Inst{15-12} = opc; let Inst{11-10} = 0b10; let Inst{9-5} = Rn; let Inst{4-0} = Rd; } class SHATiedInstVV opc, string asm, Intrinsic OpNode> : SHA2OpInst; class SHAInstSS opc, string asm, Intrinsic OpNode> : SHA2OpInst; // Armv8.2-A Crypto extensions class BaseCryptoV82 pattern> : I , Sched<[WriteV]> { bits<5> Vd; bits<5> Vn; let Inst{31-25} = 0b1100111; let Inst{9-5} = Vn; let Inst{4-0} = Vd; } class CryptoRRTiedop0, bits<2>op1, string asm, string asmops> : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm, asmops, "$Vm = $Vd", []> { let Inst{31-25} = 0b1100111; let Inst{24-21} = 0b0110; let Inst{20-15} = 0b000001; let Inst{14} = op0; let Inst{13-12} = 0b00; let Inst{11-10} = op1; } class CryptoRRTied_2Dop0, bits<2>op1, string asm> : CryptoRRTied; class CryptoRRTied_4Sop0, bits<2>op1, string asm> : CryptoRRTied; class CryptoRRR op0, bits<2>op1, dag oops, dag iops, string asm, string asmops, string cst> : BaseCryptoV82 { bits<5> Vm; let Inst{24-21} = 0b0011; let Inst{20-16} = Vm; let Inst{15} = 0b1; let Inst{14} = op0; let Inst{13-12} = 0b00; let Inst{11-10} = op1; } class CryptoRRR_2D op0, bits<2>op1, string asm> : CryptoRRR; class CryptoRRRTied_2D op0, bits<2>op1, string asm> : CryptoRRR; class CryptoRRR_4S op0, bits<2>op1, string asm> : CryptoRRR; class CryptoRRRTied_4S op0, bits<2>op1, string asm> : CryptoRRR; class CryptoRRRTied op0, bits<2>op1, string asm> : CryptoRRR; class CryptoRRRRop0, string asm, string asmops> : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, V128:$Va), asm, asmops, "", []> { bits<5> Vm; bits<5> Va; let Inst{24-23} = 0b00; let Inst{22-21} = op0; let Inst{20-16} = Vm; let Inst{15} = 0b0; let Inst{14-10} = Va; } class CryptoRRRR_16Bop0, string asm> : CryptoRRRR { } class CryptoRRRR_4Sop0, string asm> : CryptoRRRR { } class CryptoRRRi6 : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, uimm6:$imm), asm, "{\t$Vd.2d, $Vn.2d, $Vm.2d, $imm}", "", []> { bits<6> imm; bits<5> Vm; let Inst{24-21} = 0b0100; let Inst{20-16} = Vm; let Inst{15-10} = imm; let Inst{9-5} = Vn; let Inst{4-0} = Vd; } class CryptoRRRi2Tiedop0, bits<2>op1, string asm> : BaseCryptoV82<(outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm, VectorIndexS:$imm), asm, "{\t$Vd.4s, $Vn.4s, $Vm.s$imm}", "$Vd = $Vdst", []> { bits<2> imm; bits<5> Vm; let Inst{24-21} = 0b0010; let Inst{20-16} = Vm; let Inst{15} = 0b1; let Inst{14} = op0; let Inst{13-12} = imm; let Inst{11-10} = op1; } //---------------------------------------------------------------------------- // v8.1 atomic instructions extension: // * CAS // * CASP // * SWP // * LDOPregister, and aliases STOPregister // Instruction encodings: // // 31 30|29 24|23|22|21|20 16|15|14 10|9 5|4 0 // CAS SZ |001000|1 |A |1 |Rs |R |11111 |Rn |Rt // CASP 0|SZ|001000|0 |A |1 |Rs |R |11111 |Rn |Rt // SWP SZ |111000|A |R |1 |Rs |1 |OPC|00|Rn |Rt // LD SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |Rt // ST SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |11111 // Instruction syntax: // // CAS{}[] , , [] // CAS{} , , [] // CASP{} , , , , [] // CASP{} , , , , [] // SWP{}[] , , [] // SWP{} , , [] // LD{}[] , , [] // LD{} , , [] // ST{}[] , [] // ST{} , [] let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in class BaseCASEncoding pattern> : I { bits<2> Sz; bit NP; bit Acq; bit Rel; bits<5> Rs; bits<5> Rn; bits<5> Rt; let Inst{31-30} = Sz; let Inst{29-24} = 0b001000; let Inst{23} = NP; let Inst{22} = Acq; let Inst{21} = 0b1; let Inst{20-16} = Rs; let Inst{15} = Rel; let Inst{14-10} = 0b11111; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let Predicates = [HasLSE]; } class BaseCAS : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn), "cas" # order # size, "\t$Rs, $Rt, [$Rn]", "$out = $Rs",[]>, Sched<[WriteAtomic]> { let NP = 1; } multiclass CompareAndSwap Acq, bits<1> Rel, string order> { let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseCAS; let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseCAS; let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseCAS; let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseCAS; } class BaseCASP : BaseCASEncoding<(outs RC:$out),(ins RC:$Rs, RC:$Rt, GPR64sp:$Rn), "casp" # order # size, "\t$Rs, $Rt, [$Rn]", "$out = $Rs",[]>, Sched<[WriteAtomic]> { let NP = 0; } multiclass CompareAndSwapPair Acq, bits<1> Rel, string order> { let Sz = 0b00, Acq = Acq, Rel = Rel in def W : BaseCASP; let Sz = 0b01, Acq = Acq, Rel = Rel in def X : BaseCASP; } let Predicates = [HasLSE] in class BaseSWP : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swp" # order # size, "\t$Rs, $Rt, [$Rn]","",[]>, Sched<[WriteAtomic]> { bits<2> Sz; bit Acq; bit Rel; bits<5> Rs; bits<3> opc = 0b000; bits<5> Rn; bits<5> Rt; let Inst{31-30} = Sz; let Inst{29-24} = 0b111000; let Inst{23} = Acq; let Inst{22} = Rel; let Inst{21} = 0b1; let Inst{20-16} = Rs; let Inst{15} = 0b1; let Inst{14-12} = opc; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let Predicates = [HasLSE]; } multiclass Swap Acq, bits<1> Rel, string order> { let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseSWP; let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseSWP; let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseSWP; let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseSWP; } let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in class BaseLDOPregister : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size, "\t$Rs, $Rt, [$Rn]","",[]>, Sched<[WriteAtomic]> { bits<2> Sz; bit Acq; bit Rel; bits<5> Rs; bits<3> opc; bits<5> Rn; bits<5> Rt; let Inst{31-30} = Sz; let Inst{29-24} = 0b111000; let Inst{23} = Acq; let Inst{22} = Rel; let Inst{21} = 0b1; let Inst{20-16} = Rs; let Inst{15} = 0b0; let Inst{14-12} = opc; let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rt; let Predicates = [HasLSE]; } multiclass LDOPregister opc, string op, bits<1> Acq, bits<1> Rel, string order> { let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in def B : BaseLDOPregister; let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in def H : BaseLDOPregister; let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in def W : BaseLDOPregister; let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in def X : BaseLDOPregister; } // Differing SrcRHS and DstRHS allow you to cover CLR & SUB by giving a more // complex DAG for DstRHS. let Predicates = [HasLSE] in multiclass LDOPregister_patterns_ord_dag { def : Pat<(!cast(op#"_"#size#"_monotonic") GPR64sp:$Rn, SrcRHS), (!cast(inst # suffix) DstRHS, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_acquire") GPR64sp:$Rn, SrcRHS), (!cast(inst # "A" # suffix) DstRHS, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_release") GPR64sp:$Rn, SrcRHS), (!cast(inst # "L" # suffix) DstRHS, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_acq_rel") GPR64sp:$Rn, SrcRHS), (!cast(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_seq_cst") GPR64sp:$Rn, SrcRHS), (!cast(inst # "AL" # suffix) DstRHS, GPR64sp:$Rn)>; } multiclass LDOPregister_patterns_ord { defm : LDOPregister_patterns_ord_dag; } multiclass LDOPregister_patterns_ord_mod { defm : LDOPregister_patterns_ord_dag; } multiclass LDOPregister_patterns { defm : LDOPregister_patterns_ord; defm : LDOPregister_patterns_ord; defm : LDOPregister_patterns_ord; defm : LDOPregister_patterns_ord; } multiclass LDOPregister_patterns_mod { defm : LDOPregister_patterns_ord_mod(mod#Xrr) XZR, GPR64:$Rm))>; defm : LDOPregister_patterns_ord_mod(mod#Wrr) WZR, GPR32:$Rm))>; defm : LDOPregister_patterns_ord_mod(mod#Wrr) WZR, GPR32:$Rm))>; defm : LDOPregister_patterns_ord_mod(mod#Wrr) WZR, GPR32:$Rm))>; } let Predicates = [HasLSE] in multiclass CASregister_patterns_ord_dag { def : Pat<(!cast(op#"_"#size#"_monotonic") GPR64sp:$Rn, OLD, NEW), (!cast(inst # suffix) OLD, NEW, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_acquire") GPR64sp:$Rn, OLD, NEW), (!cast(inst # "A" # suffix) OLD, NEW, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_release") GPR64sp:$Rn, OLD, NEW), (!cast(inst # "L" # suffix) OLD, NEW, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_acq_rel") GPR64sp:$Rn, OLD, NEW), (!cast(inst # "AL" # suffix) OLD, NEW, GPR64sp:$Rn)>; def : Pat<(!cast(op#"_"#size#"_seq_cst") GPR64sp:$Rn, OLD, NEW), (!cast(inst # "AL" # suffix) OLD, NEW, GPR64sp:$Rn)>; } multiclass CASregister_patterns_ord { defm : CASregister_patterns_ord_dag; } multiclass CASregister_patterns { defm : CASregister_patterns_ord; defm : CASregister_patterns_ord; defm : CASregister_patterns_ord; defm : CASregister_patterns_ord; } let Predicates = [HasLSE] in class BaseSTOPregister : InstAlias; multiclass STOPregister { def : BaseSTOPregister(instr # "LB")>; def : BaseSTOPregister(instr # "LH")>; def : BaseSTOPregister(instr # "LW")>; def : BaseSTOPregister(instr # "LX")>; def : BaseSTOPregister(instr # "B")>; def : BaseSTOPregister(instr # "H")>; def : BaseSTOPregister(instr # "W")>; def : BaseSTOPregister(instr # "X")>; } //---------------------------------------------------------------------------- // Allow the size specifier tokens to be upper case, not just lower. def : TokenAlias<".4B", ".4b">; // Add dot product def : TokenAlias<".8B", ".8b">; def : TokenAlias<".4H", ".4h">; def : TokenAlias<".2S", ".2s">; def : TokenAlias<".1D", ".1d">; def : TokenAlias<".16B", ".16b">; def : TokenAlias<".8H", ".8h">; def : TokenAlias<".4S", ".4s">; def : TokenAlias<".2D", ".2d">; def : TokenAlias<".1Q", ".1q">; def : TokenAlias<".2H", ".2h">; def : TokenAlias<".B", ".b">; def : TokenAlias<".H", ".h">; def : TokenAlias<".S", ".s">; def : TokenAlias<".D", ".d">; def : TokenAlias<".Q", ".q">; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64InstrInfo.td000064400000000000000000011761560072674642500256400ustar 00000000000000//=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // AArch64 Instruction definitions. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "neon">; def HasCrypto : Predicate<"Subtarget->hasCrypto()">, AssemblerPredicate<"FeatureCrypto", "crypto">; def HasSM4 : Predicate<"Subtarget->hasSM4()">, AssemblerPredicate<"FeatureSM4", "sm4">; def HasSHA3 : Predicate<"Subtarget->hasSHA3()">, AssemblerPredicate<"FeatureSHA3", "sha3">; def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, AssemblerPredicate<"FeatureSHA2", "sha2">; def HasAES : Predicate<"Subtarget->hasAES()">, AssemblerPredicate<"FeatureAES", "aes">; def HasDotProd : Predicate<"Subtarget->hasDotProd()">, AssemblerPredicate<"FeatureDotProd", "dotprod">; def HasCRC : Predicate<"Subtarget->hasCRC()">, AssemblerPredicate<"FeatureCRC", "crc">; def HasLSE : Predicate<"Subtarget->hasLSE()">, AssemblerPredicate<"FeatureLSE", "lse">; def HasRAS : Predicate<"Subtarget->hasRAS()">, AssemblerPredicate<"FeatureRAS", "ras">; def HasRDM : Predicate<"Subtarget->hasRDM()">, AssemblerPredicate<"FeatureRDM", "rdm">; def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">; def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, AssemblerPredicate<"FeatureFullFP16", "fullfp16">; def HasSPE : Predicate<"Subtarget->hasSPE()">, AssemblerPredicate<"FeatureSPE", "spe">; def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, AssemblerPredicate<"FeatureFuseAES", "fuse-aes">; def HasSVE : Predicate<"Subtarget->hasSVE()">, AssemblerPredicate<"FeatureSVE", "sve">; def HasRCPC : Predicate<"Subtarget->hasRCPC()">, AssemblerPredicate<"FeatureRCPC", "rcpc">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def UseAlternateSExtLoadCVTF32 : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">; def UseNegativeImmediates : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates", "NegativeImmediates">; //===----------------------------------------------------------------------===// // AArch64-specific DAG Nodes. // // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i32>]>; // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<3, i32>]>; // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i32>, SDTCisVT<4, i32>]>; def SDT_AArch64Brcond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>; def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, OtherVT>]>; def SDT_AArch64CSel : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>, SDTCisVT<4, i32>]>; def SDT_AArch64CCMP : SDTypeProfile<1, 5, [SDTCisVT<0, i32>, SDTCisInt<1>, SDTCisSameAs<1, 2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisVT<5, i32>]>; def SDT_AArch64FCCMP : SDTypeProfile<1, 5, [SDTCisVT<0, i32>, SDTCisFP<1>, SDTCisSameAs<1, 2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisVT<5, i32>]>; def SDT_AArch64FCmp : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>; def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>; def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>; def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>; def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>; def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisInt<3>]>; def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>; def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>; def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>; def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>; def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>; def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>; def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; // Generates the general dynamic sequences, i.e. // adrp x0, :tlsdesc:var // ldr x1, [x0, #:tlsdesc_lo12:var] // add x0, x0, #:tlsdesc_lo12:var // .tlsdesccall var // blr x1 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here) // number of operands (the variable) def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1, [SDTCisPtrTy<0>]>; def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisSameAs<1, 4>]>; // Node definitions. def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>; def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>; def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>; def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>, [SDNPHasChain, SDNPOutGlue]>; def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; def AArch64call : SDNode<"AArch64ISD::CALL", SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond, [SDNPHasChain]>; def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz, [SDNPHasChain]>; def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz, [SDNPHasChain]>; def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz, [SDNPHasChain]>; def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz, [SDNPHasChain]>; def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>; def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>; def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>; def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>; def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >; def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>; def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut, [SDNPCommutative]>; def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>; def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut, [SDNPCommutative]>; def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>; def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>; def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>; def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>; def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>; def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>; def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>; def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>; def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>; def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>; def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>; def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>; def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>; def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>; def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>; def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>; def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>; def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>; def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>; def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>; def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>; def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>; def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>; def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>; def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>; def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>; def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>; def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>; def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>; def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>; def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>; def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>; def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>; def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>; def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>; def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>; def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>; def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>; def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>; def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>; def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>; def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>; def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>; def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>; def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>; def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>; def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>; def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>; def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>; def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>; def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>; def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>; def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS), (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>; def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>; def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>; def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>; def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>; def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>; def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>; def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>; def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>; def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH, [SDNPHasChain, SDNPSideEffect]>; def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>; def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>; def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ", SDT_AArch64TLSDescCallSeq, [SDNPInGlue, SDNPOutGlue, SDNPHasChain, SDNPVariadic]>; def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge", SDT_AArch64WrapperLarge>; def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>; def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>; def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>; def AArch64frecpe : SDNode<"AArch64ISD::FRECPE", SDTFPUnaryOp>; def AArch64frecps : SDNode<"AArch64ISD::FRECPS", SDTFPBinOp>; def AArch64frsqrte : SDNode<"AArch64ISD::FRSQRTE", SDTFPUnaryOp>; def AArch64frsqrts : SDNode<"AArch64ISD::FRSQRTS", SDTFPBinOp>; def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>; def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>; def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>; def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>; def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>; def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>; //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // AArch64 Instruction Predicate Definitions. // We could compute these on a per-module basis but doing so requires accessing // the Function object through the Subtarget and objections were raised // to that (see post-commit review comments for r301750). let RecomputePerFunction = 1 in { def ForCodeSize : Predicate<"MF->getFunction().optForSize()">; def NotForCodeSize : Predicate<"!MF->getFunction().optForSize()">; // Avoid generating STRQro if it is slow, unless we're optimizing for code size. def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize()">; } include "AArch64InstrFormats.td" include "SVEInstrFormats.td" //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Miscellaneous instructions. //===----------------------------------------------------------------------===// let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in { // We set Sched to empty list because we expect these instructions to simply get // removed in most cases. def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(AArch64callseq_start timm:$amt1, timm:$amt2)]>, Sched<[]>; def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), [(AArch64callseq_end timm:$amt1, timm:$amt2)]>, Sched<[]>; } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 let isReMaterializable = 1, isCodeGenOnly = 1 in { // FIXME: The following pseudo instructions are only needed because remat // cannot handle multiple instructions. When that changes, they can be // removed, along with the AArch64Wrapper node. let AddedComplexity = 10 in def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr), [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>, Sched<[WriteLDAdr]>; // The MOVaddr instruction should match only when the add is not folded // into a load or store address. def MOVaddr : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi), tglobaladdr:$low))]>, Sched<[WriteAdrAdr]>; def MOVaddrJT : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi), tjumptable:$low))]>, Sched<[WriteAdrAdr]>; def MOVaddrCP : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi), tconstpool:$low))]>, Sched<[WriteAdrAdr]>; def MOVaddrBA : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi), tblockaddress:$low))]>, Sched<[WriteAdrAdr]>; def MOVaddrTLS : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi), tglobaltlsaddr:$low))]>, Sched<[WriteAdrAdr]>; def MOVaddrEXT : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low), [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi), texternalsym:$low))]>, Sched<[WriteAdrAdr]>; // Normally AArch64addlow either gets folded into a following ldr/str, // or together with an adrp into MOVaddr above. For cases with TLS, it // might appear without either of them, so allow lowering it into a plain // add. def ADDlowTLS : Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low), [(set GPR64:$dst, (AArch64addlow GPR64:$src, tglobaltlsaddr:$low))]>, Sched<[WriteAdr]>; } // isReMaterializable, isCodeGenOnly def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr), (LOADgot tglobaltlsaddr:$addr)>; def : Pat<(AArch64LOADgot texternalsym:$addr), (LOADgot texternalsym:$addr)>; def : Pat<(AArch64LOADgot tconstpool:$addr), (LOADgot tconstpool:$addr)>; //===----------------------------------------------------------------------===// // System instructions. //===----------------------------------------------------------------------===// def HINT : HintI<"hint">; def : InstAlias<"nop", (HINT 0b000)>; def : InstAlias<"yield",(HINT 0b001)>; def : InstAlias<"wfe", (HINT 0b010)>; def : InstAlias<"wfi", (HINT 0b011)>; def : InstAlias<"sev", (HINT 0b100)>; def : InstAlias<"sevl", (HINT 0b101)>; def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; def : InstAlias<"csdb", (HINT 20)>; // v8.2a Statistical Profiling extension def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>; // As far as LLVM is concerned this writes to the system's exclusive monitors. let mayLoad = 1, mayStore = 1 in def CLREX : CRmSystemI; // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot // model patterns with sufficiently fine granularity. let mayLoad = ?, mayStore = ? in { def DMB : CRmSystemI; def DSB : CRmSystemI; def ISB : CRmSystemI; def TSB : CRmSystemI { let CRm = 0b0010; let Inst{12} = 0; let Predicates = [HasV8_4a]; } } // ARMv8.2 Dot Product let Predicates = [HasDotProd] in { defm SDOT : SIMDThreeSameVectorDot<0, "sdot", int_aarch64_neon_sdot>; defm UDOT : SIMDThreeSameVectorDot<1, "udot", int_aarch64_neon_udot>; defm SDOTlane : SIMDThreeSameVectorDotIndex<0, "sdot", int_aarch64_neon_sdot>; defm UDOTlane : SIMDThreeSameVectorDotIndex<1, "udot", int_aarch64_neon_udot>; } // Armv8.2-A Crypto extensions let Predicates = [HasSHA3] in { def SHA512H : CryptoRRRTied<0b0, 0b00, "sha512h">; def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">; def SHA512SU0 : CryptoRRTied_2D<0b0, 0b00, "sha512su0">; def SHA512SU1 : CryptoRRRTied_2D<0b0, 0b10, "sha512su1">; def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">; def EOR3 : CryptoRRRR_16B<0b00, "eor3">; def BCAX : CryptoRRRR_16B<0b01, "bcax">; def XAR : CryptoRRRi6<"xar">; } // HasSHA3 let Predicates = [HasSM4] in { def SM3TT1A : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">; def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">; def SM3TT2A : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">; def SM3TT2B : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">; def SM3SS1 : CryptoRRRR_4S<0b10, "sm3ss1">; def SM3PARTW1 : CryptoRRRTied_4S<0b1, 0b00, "sm3partw1">; def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">; def SM4ENCKEY : CryptoRRR_4S<0b1, 0b10, "sm4ekey">; def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">; } // HasSM4 let Predicates = [HasRCPC] in { // v8.3 Release Consistent Processor Consistent support, optional in v8.2. def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>; def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>; def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>; def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>; } // v8.3a complex add and multiply-accumulate. No predicate here, that is done // inside the multiclass as the FP16 versions need different predicates. defm FCMLA : SIMDThreeSameVectorTiedComplexHSD<1, 0b110, complexrotateop, "fcmla", null_frag>; defm FCADD : SIMDThreeSameVectorComplexHSD<1, 0b111, complexrotateopodd, "fcadd", null_frag>; defm FCMLA : SIMDIndexedTiedComplexHSD<1, 0, 1, complexrotateop, "fcmla", null_frag>; // v8.3a Pointer Authentication // These instructions inhabit part of the hint space and so can be used for // armv8 targets let Uses = [LR], Defs = [LR] in { def PACIAZ : SystemNoOperands<0b000, "paciaz">; def PACIBZ : SystemNoOperands<0b010, "pacibz">; def AUTIAZ : SystemNoOperands<0b100, "autiaz">; def AUTIBZ : SystemNoOperands<0b110, "autibz">; } let Uses = [LR, SP], Defs = [LR] in { def PACIASP : SystemNoOperands<0b001, "paciasp">; def PACIBSP : SystemNoOperands<0b011, "pacibsp">; def AUTIASP : SystemNoOperands<0b101, "autiasp">; def AUTIBSP : SystemNoOperands<0b111, "autibsp">; } let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in { def PACIA1716 : SystemNoOperands<0b000, "pacia1716">; def PACIB1716 : SystemNoOperands<0b010, "pacib1716">; def AUTIA1716 : SystemNoOperands<0b100, "autia1716">; def AUTIB1716 : SystemNoOperands<0b110, "autib1716">; } let Uses = [LR], Defs = [LR], CRm = 0b0000 in { def XPACLRI : SystemNoOperands<0b111, "xpaclri">; } // These pointer authentication isntructions require armv8.3a let Predicates = [HasV8_3a] in { multiclass SignAuth prefix, bits<3> prefix_z, string asm> { def IA : SignAuthOneData; def IB : SignAuthOneData; def DA : SignAuthOneData; def DB : SignAuthOneData; def IZA : SignAuthZero; def DZA : SignAuthZero; def IZB : SignAuthZero; def DZB : SignAuthZero; } defm PAC : SignAuth<0b000, 0b010, "pac">; defm AUT : SignAuth<0b001, 0b011, "aut">; def XPACI : SignAuthZero<0b100, 0b00, "xpaci">; def XPACD : SignAuthZero<0b100, 0b01, "xpacd">; def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>; // Combined Instructions def BRAA : AuthBranchTwoOperands<0, 0, "braa">; def BRAB : AuthBranchTwoOperands<0, 1, "brab">; def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">; def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">; def BRAAZ : AuthOneOperand<0b000, 0, "braaz">; def BRABZ : AuthOneOperand<0b000, 1, "brabz">; def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">; def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">; let isReturn = 1, isTerminator = 1, isBarrier = 1 in { def RETAA : AuthReturn<0b010, 0, "retaa">; def RETAB : AuthReturn<0b010, 1, "retab">; def ERETAA : AuthReturn<0b100, 0, "eretaa">; def ERETAB : AuthReturn<0b100, 1, "eretab">; } defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; // v8.3a floating point conversion for javascript let Predicates = [HasV8_3a, HasFPARMv8] in def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, "fjcvtzs", []> { let Inst{31} = 0; } } // HasV8_3a // v8.4 Flag manipulation instructions let Predicates = [HasV8_4a] in { def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> { let Inst{20-5} = 0b0000001000000000; } def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">; def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">; def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif", "{\t$Rn, $imm, $mask}">; } // HasV8_4a def : InstAlias<"clrex", (CLREX 0xf)>; def : InstAlias<"isb", (ISB 0xf)>; def MRS : MRSI; def MSR : MSRI; def MSRpstateImm1 : MSRpstateImm0_1; def MSRpstateImm4 : MSRpstateImm0_15; // The thread pointer (on Linux, at least, where this has been implemented) is // TPIDR_EL0. def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins), [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>; // The cycle counter PMC register is PMCCNTR_EL0. let Predicates = [HasPerfMon] in def : Pat<(readcyclecounter), (MRS 0xdce8)>; // FPCR register def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>; // Generic system instructions def SYSxt : SystemXtI<0, "sys">; def SYSLxt : SystemLXtI<1, "sysl">; def : InstAlias<"sys $op1, $Cn, $Cm, $op2", (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>; //===----------------------------------------------------------------------===// // Move immediate instructions. //===----------------------------------------------------------------------===// defm MOVK : InsertImmediate<0b11, "movk">; defm MOVN : MoveImmediate<0b00, "movn">; let PostEncoderMethod = "fixMOVZ" in defm MOVZ : MoveImmediate<0b10, "movz">; // First group of aliases covers an implicit "lsl #0". def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>; def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>; def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>; def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>; def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>; def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>; // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax. def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>; def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>; def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>; def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>; def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>; def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>; def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>; def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>; def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48), 0>; def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32), 0>; def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16), 0>; def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0), 0>; def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>; def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>; def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>; def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>; def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16), 0>; def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0), 0>; // Final group of aliases covers true "mov $Rd, $imm" cases. multiclass movw_mov_alias { def _asmoperand : AsmOperandClass { let Name = basename # width # "_lsl" # shift # "MovAlias"; let PredicateMethod = "is" # basename # "MovAlias<" # width # ", " # shift # ">"; let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">"; } def _movimm : Operand { let ParserMatchClass = !cast(NAME # "_asmoperand"); } def : InstAlias<"mov $Rd, $imm", (INST GPR:$Rd, !cast(NAME # "_movimm"):$imm, shift)>; } defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>; defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>; defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>; defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>; defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>; defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>; defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>; defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>; defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>; defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>; defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>; defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>; let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1 in { // FIXME: The following pseudo instructions are only needed because remat // cannot handle multiple instructions. When that changes, we can select // directly to the real instructions and get rid of these pseudos. def MOVi32imm : Pseudo<(outs GPR32:$dst), (ins i32imm:$src), [(set GPR32:$dst, imm:$src)]>, Sched<[WriteImm]>; def MOVi64imm : Pseudo<(outs GPR64:$dst), (ins i64imm:$src), [(set GPR64:$dst, imm:$src)]>, Sched<[WriteImm]>; } // isReMaterializable, isCodeGenOnly // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the // eventual expansion code fewer bits to worry about getting right. Marshalling // the types is a little tricky though: def i64imm_32bit : ImmLeaf(Imm); }]>; def s64imm_32bit : ImmLeaf(Imm); return Imm64 >= std::numeric_limits::min() && Imm64 <= std::numeric_limits::max(); }]>; def trunc_imm : SDNodeXFormgetTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32); }]>; def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">, GISDNodeXFormEquiv; def : Pat<(i64 i64imm_32bit:$src), (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>; // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). def bitcast_fpimm_to_i32 : SDNodeXFormgetTargetConstant( N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32); }]>; def bitcast_fpimm_to_i64 : SDNodeXFormgetTargetConstant( N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64); }]>; def : Pat<(f32 fpimm:$in), (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>; def : Pat<(f64 fpimm:$in), (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>; // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK // sequences. def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2, tglobaladdr:$g1, tglobaladdr:$g0), (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g0, 0), tglobaladdr:$g1, 16), tglobaladdr:$g2, 32), tglobaladdr:$g3, 48)>; def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2, tblockaddress:$g1, tblockaddress:$g0), (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g0, 0), tblockaddress:$g1, 16), tblockaddress:$g2, 32), tblockaddress:$g3, 48)>; def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2, tconstpool:$g1, tconstpool:$g0), (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g0, 0), tconstpool:$g1, 16), tconstpool:$g2, 32), tconstpool:$g3, 48)>; def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2, tjumptable:$g1, tjumptable:$g0), (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g0, 0), tjumptable:$g1, 16), tjumptable:$g2, 32), tjumptable:$g3, 48)>; //===----------------------------------------------------------------------===// // Arithmetic instructions. //===----------------------------------------------------------------------===// // Add/subtract with carry. defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>; defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>; def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>; def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>; def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>; def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>; // Add/subtract defm ADD : AddSub<0, "add", "sub", add>; defm SUB : AddSub<1, "sub", "add">; def : InstAlias<"mov $dst, $src", (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>; def : InstAlias<"mov $dst, $src", (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>; def : InstAlias<"mov $dst, $src", (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>; def : InstAlias<"mov $dst, $src", (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>; defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">; defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">; // Use SUBS instead of SUB to enable CSE between SUBS and SUB. def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm), (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>; def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm), (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>; def : Pat<(sub GPR32:$Rn, GPR32:$Rm), (SUBSWrr GPR32:$Rn, GPR32:$Rm)>; def : Pat<(sub GPR64:$Rn, GPR64:$Rm), (SUBSXrr GPR64:$Rn, GPR64:$Rm)>; def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm), (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>; def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm), (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>; let AddedComplexity = 1 in { def : Pat<(sub GPR32sp:$R2, arith_extended_reg32:$R3), (SUBSWrx GPR32sp:$R2, arith_extended_reg32:$R3)>; def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64:$R3), (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64:$R3)>; } // Because of the immediate format for add/sub-imm instructions, the // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). // These patterns capture that transformation. let AddedComplexity = 1 in { def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm), (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm), (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm), (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm), (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; } // Because of the immediate format for add/sub-imm instructions, the // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1). // These patterns capture that transformation. let AddedComplexity = 1 in { def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm), (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>; def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm), (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>; } def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; def : InstAlias<"neg $dst, $src$shift", (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; def : InstAlias<"neg $dst, $src$shift", (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>; def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>; def : InstAlias<"negs $dst, $src$shift", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>; def : InstAlias<"negs $dst, $src$shift", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>; // Unsigned/Signed divide defm UDIV : Div<0, "udiv", udiv>; defm SDIV : Div<1, "sdiv", sdiv>; def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>; def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>; def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>; def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>; // Variable shift defm ASRV : Shift<0b10, "asr", sra>; defm LSLV : Shift<0b00, "lsl", shl>; defm LSRV : Shift<0b01, "lsr", srl>; defm RORV : Shift<0b11, "ror", rotr>; def : ShiftAlias<"asrv", ASRVWr, GPR32>; def : ShiftAlias<"asrv", ASRVXr, GPR64>; def : ShiftAlias<"lslv", LSLVWr, GPR32>; def : ShiftAlias<"lslv", LSLVXr, GPR64>; def : ShiftAlias<"lsrv", LSRVWr, GPR32>; def : ShiftAlias<"lsrv", LSRVXr, GPR64>; def : ShiftAlias<"rorv", RORVWr, GPR32>; def : ShiftAlias<"rorv", RORVXr, GPR64>; // Multiply-add let AddedComplexity = 5 in { defm MADD : MulAccum<0, "madd", add>; defm MSUB : MulAccum<1, "msub", sub>; def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)), (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)), (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))), (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))), (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)), (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>; def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)), (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>; } // AddedComplexity = 5 let AddedComplexity = 5 in { def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>; def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>; def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>; def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>; def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))), (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))), (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))), (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))), (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>; def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))), (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; def : Pat<(i64 (mul (zext GPR32:$Rn), (i64imm_32bit:$C))), (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C))), (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), (MOVi32imm (trunc_imm imm:$C)), XZR)>; def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>; def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))), (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), (MOVi32imm (trunc_imm imm:$C)), XZR)>; def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)), (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)), (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; def : Pat<(i64 (add (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)), GPR64:$Ra)), (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))), (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))), (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; def : Pat<(i64 (sub GPR64:$Ra, (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))), (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)), (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>; } // AddedComplexity = 5 def : MulAccumWAlias<"mul", MADDWrrr>; def : MulAccumXAlias<"mul", MADDXrrr>; def : MulAccumWAlias<"mneg", MSUBWrrr>; def : MulAccumXAlias<"mneg", MSUBXrrr>; def : WideMulAccumAlias<"smull", SMADDLrrr>; def : WideMulAccumAlias<"smnegl", SMSUBLrrr>; def : WideMulAccumAlias<"umull", UMADDLrrr>; def : WideMulAccumAlias<"umnegl", UMSUBLrrr>; // Multiply-high def SMULHrr : MulHi<0b010, "smulh", mulhs>; def UMULHrr : MulHi<0b110, "umulh", mulhu>; // CRC32 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">; def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">; def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">; def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">; def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">; def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">; def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">; def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">; // v8.1 atomic CAS defm CAS : CompareAndSwap<0, 0, "">; defm CASA : CompareAndSwap<1, 0, "a">; defm CASL : CompareAndSwap<0, 1, "l">; defm CASAL : CompareAndSwap<1, 1, "al">; // v8.1 atomic CASP defm CASP : CompareAndSwapPair<0, 0, "">; defm CASPA : CompareAndSwapPair<1, 0, "a">; defm CASPL : CompareAndSwapPair<0, 1, "l">; defm CASPAL : CompareAndSwapPair<1, 1, "al">; // v8.1 atomic SWP defm SWP : Swap<0, 0, "">; defm SWPA : Swap<1, 0, "a">; defm SWPL : Swap<0, 1, "l">; defm SWPAL : Swap<1, 1, "al">; // v8.1 atomic LD(register). Performs load and then ST(register) defm LDADD : LDOPregister<0b000, "add", 0, 0, "">; defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">; defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">; defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">; defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">; defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">; defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">; defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">; defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">; defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">; defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">; defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">; defm LDSET : LDOPregister<0b011, "set", 0, 0, "">; defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">; defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">; defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">; defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">; defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">; defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">; defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">; defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">; defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">; defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">; defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">; defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">; defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">; defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">; defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">; defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">; defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">; defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">; defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">; // v8.1 atomic ST(register) as aliases to "LD(register) when Rt=xZR" defm : STOPregister<"stadd","LDADD">; // STADDx defm : STOPregister<"stclr","LDCLR">; // STCLRx defm : STOPregister<"steor","LDEOR">; // STEORx defm : STOPregister<"stset","LDSET">; // STSETx defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx defm : STOPregister<"stsmin","LDSMIN">;// STSMINx defm : STOPregister<"stumax","LDUMAX">;// STUMAXx defm : STOPregister<"stumin","LDUMIN">;// STUMINx //===----------------------------------------------------------------------===// // Logical instructions. //===----------------------------------------------------------------------===// // (immediate) defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">; defm AND : LogicalImm<0b00, "and", and, "bic">; defm EOR : LogicalImm<0b10, "eor", xor, "eon">; defm ORR : LogicalImm<0b01, "orr", or, "orn">; // FIXME: these aliases *are* canonical sometimes (when movz can't be // used). Actually, it seems to be working right now, but putting logical_immXX // here is a bit dodgy on the AsmParser side too. def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR, logical_imm32:$imm), 0>; def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR, logical_imm64:$imm), 0>; // (register) defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>; defm BICS : LogicalRegS<0b11, 1, "bics", BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>; defm AND : LogicalReg<0b00, 0, "and", and>; defm BIC : LogicalReg<0b00, 1, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; defm EON : LogicalReg<0b10, 1, "eon", BinOpFrag<(not (xor node:$LHS, node:$RHS))>>; defm EOR : LogicalReg<0b10, 0, "eor", xor>; defm ORN : LogicalReg<0b01, 1, "orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; defm ORR : LogicalReg<0b01, 0, "orr", or>; def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>; def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>; def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>; def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>; def : InstAlias<"mvn $Wd, $Wm$sh", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>; def : InstAlias<"mvn $Xd, $Xm$sh", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>; def : InstAlias<"tst $src1, $src2", (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>; def : InstAlias<"tst $src1, $src2", (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>; def : InstAlias<"tst $src1, $src2", (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>; def : InstAlias<"tst $src1, $src2", (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>; def : InstAlias<"tst $src1, $src2$sh", (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>; def : InstAlias<"tst $src1, $src2$sh", (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>; def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>; def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>; //===----------------------------------------------------------------------===// // One operand data processing instructions. //===----------------------------------------------------------------------===// defm CLS : OneOperandData<0b101, "cls">; defm CLZ : OneOperandData<0b100, "clz", ctlz>; defm RBIT : OneOperandData<0b000, "rbit", bitreverse>; def REV16Wr : OneWRegData<0b001, "rev16", UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>; def REV16Xr : OneXRegData<0b001, "rev16", null_frag>; def : Pat<(cttz GPR32:$Rn), (CLZWr (RBITWr GPR32:$Rn))>; def : Pat<(cttz GPR64:$Rn), (CLZXr (RBITXr GPR64:$Rn))>; def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)), (i32 1))), (CLSWr GPR32:$Rn)>; def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)), (i64 1))), (CLSXr GPR64:$Rn)>; // Unlike the other one operand instructions, the instructions with the "rev" // mnemonic do *not* just different in the size bit, but actually use different // opcode bits for the different sizes. def REVWr : OneWRegData<0b010, "rev", bswap>; def REVXr : OneXRegData<0b011, "rev", bswap>; def REV32Xr : OneXRegData<0b010, "rev32", UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>; def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>; // The bswap commutes with the rotr so we want a pattern for both possible // orders. def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>; def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>; //===----------------------------------------------------------------------===// // Bitfield immediate extraction instruction. //===----------------------------------------------------------------------===// let hasSideEffects = 0 in defm EXTR : ExtractImm<"extr">; def : InstAlias<"ror $dst, $src, $shift", (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>; def : InstAlias<"ror $dst, $src, $shift", (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>; def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)), (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>; def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)), (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>; //===----------------------------------------------------------------------===// // Other bitfield immediate instructions. //===----------------------------------------------------------------------===// let hasSideEffects = 0 in { defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">; defm SBFM : BitfieldImm<0b00, "sbfm">; defm UBFM : BitfieldImm<0b10, "ubfm">; } def i32shift_a : Operand, SDNodeXFormgetZExtValue()) & 0x1f; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; def i32shift_b : Operand, SDNodeXFormgetZExtValue(); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; // min(7, 31 - shift_amt) def i32shift_sext_i8 : Operand, SDNodeXFormgetZExtValue(); enc = enc > 7 ? 7 : enc; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; // min(15, 31 - shift_amt) def i32shift_sext_i16 : Operand, SDNodeXFormgetZExtValue(); enc = enc > 15 ? 15 : enc; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; def i64shift_a : Operand, SDNodeXFormgetZExtValue()) & 0x3f; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; def i64shift_b : Operand, SDNodeXFormgetZExtValue(); return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; // min(7, 63 - shift_amt) def i64shift_sext_i8 : Operand, SDNodeXFormgetZExtValue(); enc = enc > 7 ? 7 : enc; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; // min(15, 63 - shift_amt) def i64shift_sext_i16 : Operand, SDNodeXFormgetZExtValue(); enc = enc > 15 ? 15 : enc; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; // min(31, 63 - shift_amt) def i64shift_sext_i32 : Operand, SDNodeXFormgetZExtValue(); enc = enc > 31 ? 31 : enc; return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64); }]>; def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)), (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), (i64 (i32shift_b imm0_31:$imm)))>; def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)), (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), (i64 (i64shift_b imm0_63:$imm)))>; let AddedComplexity = 10 in { def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)), (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)), (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; } def : InstAlias<"asr $dst, $src, $shift", (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; def : InstAlias<"asr $dst, $src, $shift", (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)), (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>; def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)), (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>; def : InstAlias<"lsr $dst, $src, $shift", (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>; def : InstAlias<"lsr $dst, $src, $shift", (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>; def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>; def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>; def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>; def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>; def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>; //===----------------------------------------------------------------------===// // Conditional comparison instructions. //===----------------------------------------------------------------------===// defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>; defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>; //===----------------------------------------------------------------------===// // Conditional select instructions. //===----------------------------------------------------------------------===// defm CSEL : CondSelect<0, 0b00, "csel">; def inc : PatFrag<(ops node:$in), (add node:$in, 1)>; defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>; defm CSINV : CondSelectOp<1, 0b00, "csinv", not>; defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>; def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV), (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>; def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV), (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>; def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV), (CSINCWr WZR, WZR, (i32 imm:$cc))>; def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV), (CSINCXr XZR, XZR, (i32 imm:$cc))>; def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV), (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>; def : Pat<(AArch64csel GPR64:$tval, (i64 1), (i32 imm:$cc), NZCV), (CSINCXr GPR64:$tval, XZR, (i32 imm:$cc))>; def : Pat<(AArch64csel (i32 1), GPR32:$fval, (i32 imm:$cc), NZCV), (CSINCWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; def : Pat<(AArch64csel (i64 1), GPR64:$fval, (i32 imm:$cc), NZCV), (CSINCXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV), (CSINVWr WZR, WZR, (i32 imm:$cc))>; def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV), (CSINVXr XZR, XZR, (i32 imm:$cc))>; def : Pat<(AArch64csel GPR32:$tval, (i32 -1), (i32 imm:$cc), NZCV), (CSINVWr GPR32:$tval, WZR, (i32 imm:$cc))>; def : Pat<(AArch64csel GPR64:$tval, (i64 -1), (i32 imm:$cc), NZCV), (CSINVXr GPR64:$tval, XZR, (i32 imm:$cc))>; def : Pat<(AArch64csel (i32 -1), GPR32:$fval, (i32 imm:$cc), NZCV), (CSINVWr GPR32:$fval, WZR, (i32 (inv_cond_XFORM imm:$cc)))>; def : Pat<(AArch64csel (i64 -1), GPR64:$fval, (i32 imm:$cc), NZCV), (CSINVXr GPR64:$fval, XZR, (i32 (inv_cond_XFORM imm:$cc)))>; // The inverse of the condition code from the alias instruction is what is used // in the aliased instruction. The parser all ready inverts the condition code // for these aliases. def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>; def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>; def : InstAlias<"cinc $dst, $src, $cc", (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; def : InstAlias<"cinc $dst, $src, $cc", (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; def : InstAlias<"cinv $dst, $src, $cc", (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; def : InstAlias<"cinv $dst, $src, $cc", (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; def : InstAlias<"cneg $dst, $src, $cc", (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>; def : InstAlias<"cneg $dst, $src, $cc", (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>; //===----------------------------------------------------------------------===// // PC-relative instructions. //===----------------------------------------------------------------------===// let isReMaterializable = 1 in { let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { def ADR : ADRI<0, "adr", adrlabel, []>; } // hasSideEffects = 0 def ADRP : ADRI<1, "adrp", adrplabel, [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>; } // isReMaterializable = 1 // page address of a constant pool entry, block address def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>; def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>; def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>; //===----------------------------------------------------------------------===// // Unconditional branch (register) instructions. //===----------------------------------------------------------------------===// let isReturn = 1, isTerminator = 1, isBarrier = 1 in { def RET : BranchReg<0b0010, "ret", []>; def DRPS : SpecialReturn<0b0101, "drps">; def ERET : SpecialReturn<0b0100, "eret">; } // isReturn = 1, isTerminator = 1, isBarrier = 1 // Default to the LR register. def : InstAlias<"ret", (RET LR)>; let isCall = 1, Defs = [LR], Uses = [SP] in { def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>; } // isCall let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>; } // isBranch, isTerminator, isBarrier, isIndirectBranch // Create a separate pseudo-instruction for codegen to use so that we don't // flag lr as used in every function. It'll be restored before the RET by the // epilogue if it's legitimately used. def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]>, Sched<[WriteBrReg]> { let isTerminator = 1; let isBarrier = 1; let isReturn = 1; } // This is a directive-like pseudo-instruction. The purpose is to insert an // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction // (which in the usual case is a BLR). let hasSideEffects = 1 in def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []>, Sched<[]> { let AsmString = ".tlsdesccall $sym"; } // FIXME: maybe the scratch register used shouldn't be fixed to X1? // FIXME: can "hasSideEffects be dropped? let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1, isCodeGenOnly = 1 in def TLSDESC_CALLSEQ : Pseudo<(outs), (ins i64imm:$sym), [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>, Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>; def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym), (TLSDESC_CALLSEQ texternalsym:$sym)>; //===----------------------------------------------------------------------===// // Conditional branch (immediate) instruction. //===----------------------------------------------------------------------===// def Bcc : BranchCond; //===----------------------------------------------------------------------===// // Compare-and-branch instructions. //===----------------------------------------------------------------------===// defm CBZ : CmpBranch<0, "cbz", AArch64cbz>; defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>; //===----------------------------------------------------------------------===// // Test-bit-and-branch instructions. //===----------------------------------------------------------------------===// defm TBZ : TestBranch<0, "tbz", AArch64tbz>; defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>; //===----------------------------------------------------------------------===// // Unconditional branch (immediate) instructions. //===----------------------------------------------------------------------===// let isBranch = 1, isTerminator = 1, isBarrier = 1 in { def B : BranchImm<0, "b", [(br bb:$addr)]>; } // isBranch, isTerminator, isBarrier let isCall = 1, Defs = [LR], Uses = [SP] in { def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>; } // isCall def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>; //===----------------------------------------------------------------------===// // Exception generation instructions. //===----------------------------------------------------------------------===// let isTrap = 1 in { def BRK : ExceptionGeneration<0b001, 0b00, "brk">; } def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">; def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">; def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">; def HLT : ExceptionGeneration<0b010, 0b00, "hlt">; def HVC : ExceptionGeneration<0b000, 0b10, "hvc">; def SMC : ExceptionGeneration<0b000, 0b11, "smc">; def SVC : ExceptionGeneration<0b000, 0b01, "svc">; // DCPSn defaults to an immediate operand of zero if unspecified. def : InstAlias<"dcps1", (DCPS1 0)>; def : InstAlias<"dcps2", (DCPS2 0)>; def : InstAlias<"dcps3", (DCPS3 0)>; //===----------------------------------------------------------------------===// // Load instructions. //===----------------------------------------------------------------------===// // Pair (indexed, offset) defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">; defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">; defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (pre-indexed) def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">; def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">; def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (post-indexed) def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">; def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">; def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (no allocate) defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">; defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">; defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">; defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">; defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">; //--- // (register offset) //--- // Integer defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>; defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>; defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>; defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>; // Floating-point defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", untyped, load>; defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>; defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>; defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>; defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>; // Load sign-extended half-word defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>; defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>; // Load sign-extended byte defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>; defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>; // Load sign-extended word defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>; // Pre-fetch. defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">; // For regular load, we do not have any alignment requirement. // Thus, it is safe to directly map the vector loads with interesting // addressing modes. // FIXME: We could do the same for bitconvert to floating point vectors. multiclass ScalToVecROLoadPat { def : Pat<(VecTy (scalar_to_vector (ScalTy (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))), (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset), sub)>; def : Pat<(VecTy (scalar_to_vector (ScalTy (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))), (INSERT_SUBREG (VecTy (IMPLICIT_DEF)), (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset), sub)>; } let AddedComplexity = 10 in { defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; defm : ScalToVecROLoadPat; def : Pat <(v1i64 (scalar_to_vector (i64 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend))))), (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>; def : Pat <(v1i64 (scalar_to_vector (i64 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend))))), (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>; } // Match all load 64 bits width whose type is compatible with FPR64 multiclass VecROLoadPat { def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; } let AddedComplexity = 10 in { let Predicates = [IsLE] in { // We must do vector loads with LD1 in big-endian. defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; } defm : VecROLoadPat; defm : VecROLoadPat; // Match all load 128 bits width whose type is compatible with FPR128 let Predicates = [IsLE] in { // We must do vector loads with LD1 in big-endian. defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; defm : VecROLoadPat; } } // AddedComplexity = 10 // zextload -> i64 multiclass ExtLoadTo64ROPat { def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (SUBREG_TO_REG (i64 0), (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), sub_32)>; def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (SUBREG_TO_REG (i64 0), (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), sub_32)>; } let AddedComplexity = 10 in { defm : ExtLoadTo64ROPat; defm : ExtLoadTo64ROPat; defm : ExtLoadTo64ROPat; // zextloadi1 -> zextloadi8 defm : ExtLoadTo64ROPat; // extload -> zextload defm : ExtLoadTo64ROPat; defm : ExtLoadTo64ROPat; defm : ExtLoadTo64ROPat; // extloadi1 -> zextloadi8 defm : ExtLoadTo64ROPat; } // zextload -> i64 multiclass ExtLoadTo32ROPat { def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; } let AddedComplexity = 10 in { // extload -> zextload defm : ExtLoadTo32ROPat; defm : ExtLoadTo32ROPat; defm : ExtLoadTo32ROPat; // zextloadi1 -> zextloadi8 defm : ExtLoadTo32ROPat; } //--- // (unsigned immediate) //--- defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr", [(set GPR64z:$Rt, (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr", [(set GPR32z:$Rt, (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr", [(set FPR8Op:$Rt, (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr", [(set (f16 FPR16Op:$Rt), (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr", [(set (f32 FPR32Op:$Rt), (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr", [(set (f64 FPR64Op:$Rt), (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr", [(set (f128 FPR128Op:$Rt), (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>; // For regular load, we do not have any alignment requirement. // Thus, it is safe to directly map the vector loads with interesting // addressing modes. // FIXME: We could do the same for bitconvert to floating point vectors. def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; def : Pat <(v2i32 (scalar_to_vector (i32 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; def : Pat <(v4i32 (scalar_to_vector (i32 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; def : Pat <(v1i64 (scalar_to_vector (i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat <(v2i64 (scalar_to_vector (i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))), (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>; // Match all load 64 bits width whose type is compatible with FPR64 let Predicates = [IsLE] in { // We must use LD1 to perform vector loads in big-endian. def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; } def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))), (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>; // Match all load 128 bits width whose type is compatible with FPR128 let Predicates = [IsLE] in { // We must use LD1 to perform vector loads in big-endian. def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; } def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>; defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh", [(set GPR32:$Rt, (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb", [(set GPR32:$Rt, (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; // zextloadi1 -> zextloadi8 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; // extload -> zextload def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>; def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; // load sign-extended half-word defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh", [(set GPR32:$Rt, (sextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh", [(set GPR64:$Rt, (sextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; // load sign-extended byte defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb", [(set GPR32:$Rt, (sextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb", [(set GPR64:$Rt, (sextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; // load sign-extended word defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw", [(set GPR64:$Rt, (sextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; // load zero-extended word def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; // Pre-fetch. def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm", [(AArch64Prefetch imm:$Rt, (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>; //--- // (literal) def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr">; def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr">; def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr">; def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr">; def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr">; // load sign-extended word def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw">; // prefetch def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>; // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>; //--- // (unscaled immediate) defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur", [(set GPR64z:$Rt, (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur", [(set GPR32z:$Rt, (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur", [(set FPR8Op:$Rt, (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur", [(set FPR16Op:$Rt, (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur", [(set (f32 FPR32Op:$Rt), (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur", [(set (f64 FPR64Op:$Rt), (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur", [(set (f128 FPR128Op:$Rt), (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURHH : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh", [(set GPR32:$Rt, (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURBB : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb", [(set GPR32:$Rt, (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; // Match all load 64 bits width whose type is compatible with FPR64 let Predicates = [IsLE] in { def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; } def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))), (LDURDi GPR64sp:$Rn, simm9:$offset)>; // Match all load 128 bits width whose type is compatible with FPR128 let Predicates = [IsLE] in { def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), (LDURQi GPR64sp:$Rn, simm9:$offset)>; } // anyext -> zext def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (LDURHHi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; // unscaled zext def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (LDURHHi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; //--- // LDR mnemonics fall back to LDUR for negative or unaligned offsets. // Define new assembler match classes as we want to only match these when // the don't otherwise match the scaled addressing mode for LDR/STR. Don't // associate a DiagnosticType either, as we want the diagnostic for the // canonical form (the scaled operand) to take precedence. class SImm9OffsetOperand : AsmOperandClass { let Name = "SImm9OffsetFB" # Width; let PredicateMethod = "isSImm9OffsetFB<" # Width # ">"; let RenderMethod = "addImmOperands"; } def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>; def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>; def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>; def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>; def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>; def simm9_offset_fb8 : Operand { let ParserMatchClass = SImm9OffsetFB8Operand; } def simm9_offset_fb16 : Operand { let ParserMatchClass = SImm9OffsetFB16Operand; } def simm9_offset_fb32 : Operand { let ParserMatchClass = SImm9OffsetFB32Operand; } def simm9_offset_fb64 : Operand { let ParserMatchClass = SImm9OffsetFB64Operand; } def simm9_offset_fb128 : Operand { let ParserMatchClass = SImm9OffsetFB128Operand; } def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; // load sign-extended half-word defm LDURSHW : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh", [(set GPR32:$Rt, (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURSHX : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh", [(set GPR64:$Rt, (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; // load sign-extended byte defm LDURSBW : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb", [(set GPR32:$Rt, (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURSBX : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb", [(set GPR64:$Rt, (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; // load sign-extended word defm LDURSW : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw", [(set GPR64:$Rt, (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; // zero and sign extending aliases from generic LDR* mnemonics to LDUR*. def : InstAlias<"ldrb $Rt, [$Rn, $offset]", (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldrh $Rt, [$Rn, $offset]", (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldrsb $Rt, [$Rn, $offset]", (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"ldrsh $Rt, [$Rn, $offset]", (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"ldrsw $Rt, [$Rn, $offset]", (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; // Pre-fetch. defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum", [(AArch64Prefetch imm:$Rt, (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; //--- // (unscaled immediate, unprivileged) defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">; defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">; defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">; defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">; // load sign-extended half-word defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">; defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">; // load sign-extended byte defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">; defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">; // load sign-extended word defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">; //--- // (immediate pre-indexed) def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">; def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">; def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">; def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">; def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">; def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">; def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">; // load sign-extended half-word def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; // load sign-extended byte def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; // load zero-extended byte def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">; def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">; // load sign-extended word def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; //--- // (immediate post-indexed) def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">; def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">; def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">; def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">; def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">; def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">; def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">; // load sign-extended half-word def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; // load sign-extended byte def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; // load zero-extended byte def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">; def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">; // load sign-extended word def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; //===----------------------------------------------------------------------===// // Store instructions. //===----------------------------------------------------------------------===// // Pair (indexed, offset) // FIXME: Use dedicated range-checked addressing mode operand here. defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">; defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">; defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">; defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">; defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">; // Pair (pre-indexed) def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">; def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">; def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">; def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">; def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">; // Pair (pre-indexed) def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">; def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">; def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">; def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">; def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">; // Pair (no allocate) defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">; defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">; defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">; defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; //--- // (Register offset) // Integer defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>; defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>; defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>; defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>; // Floating-point defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", untyped, store>; defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>; defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>; defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>; defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>; let Predicates = [UseSTRQro], AddedComplexity = 10 in { def : Pat<(store (f128 FPR128:$Rt), (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)), (STRQroW FPR128:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend)>; def : Pat<(store (f128 FPR128:$Rt), (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend)), (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Wextend128:$extend)>; } multiclass TruncStoreFrom64ROPat { def : Pat<(storeop GPR64:$Rt, (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; def : Pat<(storeop GPR64:$Rt, (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; } let AddedComplexity = 10 in { // truncstore i64 defm : TruncStoreFrom64ROPat; defm : TruncStoreFrom64ROPat; defm : TruncStoreFrom64ROPat; } multiclass VecROStorePat { def : Pat<(store (VecTy FPR:$Rt), (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; def : Pat<(store (VecTy FPR:$Rt), (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; } let AddedComplexity = 10 in { // Match all store 64 bits width whose type is compatible with FPR64 let Predicates = [IsLE] in { // We must use ST1 to store vectors in big-endian. defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; } defm : VecROStorePat; defm : VecROStorePat; // Match all store 128 bits width whose type is compatible with FPR128 let Predicates = [IsLE, UseSTRQro] in { // We must use ST1 to store vectors in big-endian. defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; defm : VecROStorePat; } } // AddedComplexity = 10 // Match stores from lane 0 to the appropriate subreg's store. multiclass VecROStoreLane0Pat { def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)), (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>; def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)), (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)), (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>; } let AddedComplexity = 19 in { defm : VecROStoreLane0Pat; defm : VecROStoreLane0Pat; defm : VecROStoreLane0Pat; defm : VecROStoreLane0Pat; defm : VecROStoreLane0Pat; defm : VecROStoreLane0Pat; } //--- // (unsigned immediate) defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str", [(store GPR64z:$Rt, (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str", [(store GPR32z:$Rt, (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str", [(store FPR8Op:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str", [(store (f16 FPR16Op:$Rt), (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>; defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str", [(store (f32 FPR32Op:$Rt), (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str", [(store (f64 FPR64Op:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>; defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh", [(truncstorei16 GPR32z:$Rt, (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>; defm STRBB : StoreUIz<0b00, 0, 0b00, GPR32z, uimm12s1, "strb", [(truncstorei8 GPR32z:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; let AddedComplexity = 10 in { // Match all store 64 bits width whose type is compatible with FPR64 def : Pat<(store (v1i64 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(store (v1f64 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; let Predicates = [IsLE] in { // We must use ST1 to store vectors in big-endian. def : Pat<(store (v2f32 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(store (v8i8 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(store (v4i16 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(store (v2i32 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; def : Pat<(store (v4f16 FPR64:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)), (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>; } // Match all store 128 bits width whose type is compatible with FPR128 def : Pat<(store (f128 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; let Predicates = [IsLE] in { // We must use ST1 to store vectors in big-endian. def : Pat<(store (v4f32 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(store (v2f64 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(store (v16i8 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(store (v8i16 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(store (v4i32 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(store (v2i64 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; def : Pat<(store (v8f16 FPR128:$Rt), (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)), (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>; } // truncstore i64 def : Pat<(truncstorei32 GPR64:$Rt, (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)), (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>; def : Pat<(truncstorei16 GPR64:$Rt, (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)), (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>; def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)), (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>; } // AddedComplexity = 10 // Match stores from lane 0 to the appropriate subreg's store. multiclass VecStoreLane0Pat { def : Pat<(storeop (STy (vector_extract (VTy VecListOne128:$Vt), 0)), (UIAddrMode GPR64sp:$Rn, IndexType:$offset)), (STR (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx), GPR64sp:$Rn, IndexType:$offset)>; } let AddedComplexity = 19 in { defm : VecStoreLane0Pat; defm : VecStoreLane0Pat; defm : VecStoreLane0Pat; defm : VecStoreLane0Pat; defm : VecStoreLane0Pat; defm : VecStoreLane0Pat; } //--- // (unscaled immediate) defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur", [(store GPR64z:$Rt, (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur", [(store GPR32z:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur", [(store FPR8Op:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur", [(store (f16 FPR16Op:$Rt), (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur", [(store (f32 FPR32Op:$Rt), (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur", [(store (f64 FPR64Op:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur", [(store (f128 FPR128Op:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>; defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh", [(truncstorei16 GPR32z:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb", [(truncstorei8 GPR32z:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; // Armv8.4 LDAPR & STLR with Immediate Offset instruction let Predicates = [HasV8_4a] in { defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>; defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>; defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>; defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>; defm LDAPURB : BaseLoadUnscaleV84<"ldapurb", 0b00, 0b01, GPR32>; defm LDAPURSBW : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b11, GPR32>; defm LDAPURSBX : BaseLoadUnscaleV84<"ldapursb", 0b00, 0b10, GPR64>; defm LDAPURH : BaseLoadUnscaleV84<"ldapurh", 0b01, 0b01, GPR32>; defm LDAPURSHW : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b11, GPR32>; defm LDAPURSHX : BaseLoadUnscaleV84<"ldapursh", 0b01, 0b10, GPR64>; defm LDAPUR : BaseLoadUnscaleV84<"ldapur", 0b10, 0b01, GPR32>; defm LDAPURSW : BaseLoadUnscaleV84<"ldapursw", 0b10, 0b10, GPR64>; defm LDAPURX : BaseLoadUnscaleV84<"ldapur", 0b11, 0b01, GPR64>; } // Match all store 64 bits width whose type is compatible with FPR64 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; let AddedComplexity = 10 in { let Predicates = [IsLE] in { // We must use ST1 to store vectors in big-endian. def : Pat<(store (v2f32 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v8i8 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v4i16 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v2i32 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v4f16 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>; } // Match all store 128 bits width whose type is compatible with FPR128 def : Pat<(store (f128 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; let Predicates = [IsLE] in { // We must use ST1 to store vectors in big-endian. def : Pat<(store (v4f32 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v2f64 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v16i8 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v8i16 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v4i32 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v2i64 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v2f64 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; def : Pat<(store (v8f16 FPR128:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset)), (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>; } } // AddedComplexity = 10 // unscaled i64 truncating stores def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)), (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)), (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)), (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>; // Match stores from lane 0 to the appropriate subreg's store. multiclass VecStoreULane0Pat { defm : VecStoreLane0Pat; } let AddedComplexity = 19 in { defm : VecStoreULane0Pat; defm : VecStoreULane0Pat; defm : VecStoreULane0Pat; defm : VecStoreULane0Pat; defm : VecStoreULane0Pat; defm : VecStoreULane0Pat; } //--- // STR mnemonics fall back to STUR for negative or unaligned offsets. def : InstAlias<"str $Rt, [$Rn, $offset]", (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; def : InstAlias<"strb $Rt, [$Rn, $offset]", (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"strh $Rt, [$Rn, $offset]", (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; //--- // (unscaled immediate, unprivileged) defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">; defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">; defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">; defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">; //--- // (immediate pre-indexed) def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>; def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>; def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, untyped>; def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>; def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>; def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>; def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>; def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>; def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>; // truncstore i64 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; //--- // (immediate post-indexed) def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>; def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>; def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, untyped>; def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>; def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>; def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>; def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>; def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>; def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>; // truncstore i64 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, simm9:$off)>; def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off), (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, simm9:$off)>; def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off), (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off), (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>; //===----------------------------------------------------------------------===// // Load/store exclusive instructions. //===----------------------------------------------------------------------===// def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">; def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">; def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">; def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">; def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">; def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">; def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">; def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">; def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">; def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">; def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">; def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">; def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">; def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">; def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">; def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">; def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">; def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">; def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">; def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">; def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">; def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">; def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">; def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">; def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">; def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">; def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">; def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">; def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">; def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">; def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">; def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">; let Predicates = [HasV8_1a] in { // v8.1a "Limited Order Region" extension load-acquire instructions def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">; def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">; def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">; def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">; // v8.1a "Limited Order Region" extension store-release instructions def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">; def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">; def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">; def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">; } //===----------------------------------------------------------------------===// // Scaled floating point to integer conversion instructions. //===----------------------------------------------------------------------===// defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>; defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>; defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>; defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>; defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>; defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>; defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>; defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>; defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>; defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>; defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>; defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>; multiclass FPToIntegerIntPats { def : Pat<(i32 (round f16:$Rn)), (!cast(INST # UWHr) $Rn)>; def : Pat<(i64 (round f16:$Rn)), (!cast(INST # UXHr) $Rn)>; def : Pat<(i32 (round f32:$Rn)), (!cast(INST # UWSr) $Rn)>; def : Pat<(i64 (round f32:$Rn)), (!cast(INST # UXSr) $Rn)>; def : Pat<(i32 (round f64:$Rn)), (!cast(INST # UWDr) $Rn)>; def : Pat<(i64 (round f64:$Rn)), (!cast(INST # UXDr) $Rn)>; def : Pat<(i32 (round (fmul f16:$Rn, fixedpoint_f16_i32:$scale))), (!cast(INST # SWHri) $Rn, $scale)>; def : Pat<(i64 (round (fmul f16:$Rn, fixedpoint_f16_i64:$scale))), (!cast(INST # SXHri) $Rn, $scale)>; def : Pat<(i32 (round (fmul f32:$Rn, fixedpoint_f32_i32:$scale))), (!cast(INST # SWSri) $Rn, $scale)>; def : Pat<(i64 (round (fmul f32:$Rn, fixedpoint_f32_i64:$scale))), (!cast(INST # SXSri) $Rn, $scale)>; def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))), (!cast(INST # SWDri) $Rn, $scale)>; def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))), (!cast(INST # SXDri) $Rn, $scale)>; } defm : FPToIntegerIntPats; defm : FPToIntegerIntPats; multiclass FPToIntegerPats { def : Pat<(i32 (to_int (round f32:$Rn))), (!cast(INST # UWSr) f32:$Rn)>; def : Pat<(i64 (to_int (round f32:$Rn))), (!cast(INST # UXSr) f32:$Rn)>; def : Pat<(i32 (to_int (round f64:$Rn))), (!cast(INST # UWDr) f64:$Rn)>; def : Pat<(i64 (to_int (round f64:$Rn))), (!cast(INST # UXDr) f64:$Rn)>; } defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; defm : FPToIntegerPats; //===----------------------------------------------------------------------===// // Scaled integer to floating point conversion instructions. //===----------------------------------------------------------------------===// defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>; defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>; //===----------------------------------------------------------------------===// // Unscaled integer to floating point conversion instruction. //===----------------------------------------------------------------------===// defm FMOV : UnscaledConversion<"fmov">; // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, Sched<[WriteF]>, Requires<[HasFullFP16]>; def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, Sched<[WriteF]>; def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, Sched<[WriteF]>; } // Similarly add aliases def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>, Requires<[HasFullFP16]>; def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>; def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>; //===----------------------------------------------------------------------===// // Floating point conversion instruction. //===----------------------------------------------------------------------===// defm FCVT : FPConversion<"fcvt">; //===----------------------------------------------------------------------===// // Floating point single operand instructions. //===----------------------------------------------------------------------===// defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>; defm FMOV : SingleOperandFPData<0b0000, "fmov">; defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>; defm FRINTA : SingleOperandFPData<0b1100, "frinta", fround>; defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>; defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>; defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>; defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>; def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))), (FRINTNDr FPR64:$Rn)>; defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>; defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>; let SchedRW = [WriteFDiv] in { defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>; } //===----------------------------------------------------------------------===// // Floating point two operand instructions. //===----------------------------------------------------------------------===// defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>; let SchedRW = [WriteFDiv] in { defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>; } defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>; defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>; defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>; defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>; let SchedRW = [WriteFMul] in { defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>; defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>; } defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>; def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMAXDrr FPR64:$Rn, FPR64:$Rm)>; def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMINDrr FPR64:$Rn, FPR64:$Rm)>; def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>; def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>; //===----------------------------------------------------------------------===// // Floating point three operand instructions. //===----------------------------------------------------------------------===// defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>; defm FMSUB : ThreeOperandFPData<0, 1, "fmsub", TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >; defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd", TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >; defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub", TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >; // The following def pats catch the case where the LHS of an FMA is negated. // The TriOpFrag above catches the case where the middle operand is negated. // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike // the NEON variant. def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)), (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)), (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and // "(-a) + b*(-c)". def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))), (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))), (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))), (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))), (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; //===----------------------------------------------------------------------===// // Floating point comparison instructions. //===----------------------------------------------------------------------===// defm FCMPE : FPComparison<1, "fcmpe">; defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>; //===----------------------------------------------------------------------===// // Floating point conditional comparison instructions. //===----------------------------------------------------------------------===// defm FCCMPE : FPCondComparison<1, "fccmpe">; defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>; //===----------------------------------------------------------------------===// // Floating point conditional select instruction. //===----------------------------------------------------------------------===// defm FCSEL : FPCondSelect<"fcsel">; // CSEL instructions providing f128 types need to be handled by a // pseudo-instruction since the eventual code will need to introduce basic // blocks and control flow. def F128CSEL : Pseudo<(outs FPR128:$Rd), (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond), [(set (f128 FPR128:$Rd), (AArch64csel FPR128:$Rn, FPR128:$Rm, (i32 imm:$cond), NZCV))]> { let Uses = [NZCV]; let usesCustomInserter = 1; let hasNoSchedulingInfo = 1; } //===----------------------------------------------------------------------===// // Floating point immediate move. //===----------------------------------------------------------------------===// let isReMaterializable = 1 in { defm FMOV : FPMoveImmediate<"fmov">; } //===----------------------------------------------------------------------===// // Advanced SIMD two vector instructions. //===----------------------------------------------------------------------===// defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl", int_aarch64_neon_uabd>; // Match UABDL in log2-shuffle patterns. def : Pat<(abs (v8i16 (sub (zext (v8i8 V64:$opA)), (zext (v8i8 V64:$opB))))), (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), (v8i16 (add (sub (zext (v8i8 V64:$opA)), (zext (v8i8 V64:$opB))), (AArch64vashr v8i16:$src, (i32 15))))), (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>; def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 V128:$opA)), (zext (extract_high_v16i8 V128:$opB))))), (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))), (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)), (zext (extract_high_v16i8 V128:$opB))), (AArch64vashr v8i16:$src, (i32 15))))), (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>; def : Pat<(abs (v4i32 (sub (zext (v4i16 V64:$opA)), (zext (v4i16 V64:$opB))))), (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>; def : Pat<(abs (v4i32 (sub (zext (extract_high_v8i16 V128:$opA)), (zext (extract_high_v8i16 V128:$opB))))), (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>; def : Pat<(abs (v2i64 (sub (zext (v2i32 V64:$opA)), (zext (v2i32 V64:$opB))))), (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>; def : Pat<(abs (v2i64 (sub (zext (extract_high_v4i32 V128:$opA)), (zext (extract_high_v4i32 V128:$opB))))), (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>; defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", abs>; defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>; defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>; defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>; defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>; defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>; defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>; defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>; defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>; defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>; defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>; defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>; defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>; defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>; defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">; def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>; def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn), (i64 4)))), (FCVTLv8i16 V128:$Rn)>; def : Pat<(v2f64 (fpextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>; def : Pat<(v2f64 (fpextend (v2f32 (extract_subvector (v4f32 V128:$Rn), (i64 2))))), (FCVTLv4i32 V128:$Rn)>; def : Pat<(v4f32 (fpextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>; def : Pat<(v4f32 (fpextend (v4f16 (extract_subvector (v8f16 V128:$Rn), (i64 4))))), (FCVTLv8i16 V128:$Rn)>; defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>; defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>; defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>; defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>; defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">; def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>; def : Pat<(concat_vectors V64:$Rd, (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))), (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>; def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>; def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))), (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>; defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>; defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>; defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn", int_aarch64_neon_fcvtxn>; defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>; defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>; def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>; def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>; def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>; def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>; def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>; def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>; def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>; def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>; def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>; def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>; defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>; defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>; defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", fround>; defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>; defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>; defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>; defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>; defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>; defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>; defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>; defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>; defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", UnOpFrag<(sub immAllZerosV, node:$LHS)> >; defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; // Aliases for MVN -> NOT. def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", (NOTv8i8 V64:$Vd, V64:$Vn)>; def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", (NOTv16i8 V128:$Vd, V128:$Vn)>; def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>; def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>; def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>; def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>; def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>; def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>; def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>; def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>; def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>; def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>; defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>; defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>; defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>; defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>; defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp", BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >; defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>; defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>; defm SHLL : SIMDVectorLShiftLongBySizeBHS; defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>; defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>; defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>; defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp", BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >; defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp", int_aarch64_neon_uaddlp>; defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>; defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>; defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>; defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>; defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>; defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>; def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>; def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>; def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>; def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>; def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>; def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>; // Patterns for vector long shift (by element width). These need to match all // three of zext, sext and anyext so it's easier to pull the patterns out of the // definition. multiclass SIMDVectorLShiftLongBySizeBHSPats { def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)), (SHLLv8i8 V64:$Rn)>; def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)), (SHLLv16i8 V128:$Rn)>; def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)), (SHLLv4i16 V64:$Rn)>; def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)), (SHLLv8i16 V128:$Rn)>; def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)), (SHLLv2i32 V64:$Rn)>; def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)), (SHLLv4i32 V128:$Rn)>; } defm : SIMDVectorLShiftLongBySizeBHSPats; defm : SIMDVectorLShiftLongBySizeBHSPats; defm : SIMDVectorLShiftLongBySizeBHSPats; //===----------------------------------------------------------------------===// // Advanced SIMD three vector instructions. //===----------------------------------------------------------------------===// defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>; defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>; defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>; defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>; defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>; defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>; defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>; defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>; defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>; let Predicates = [HasNEON] in { foreach VT = [ v2f32, v4f32, v2f64 ] in def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast("FABD"#VT) VT:$Rn, VT:$Rm)>; } let Predicates = [HasNEON, HasFullFP16] in { foreach VT = [ v4f16, v8f16 ] in def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast("FABD"#VT) VT:$Rn, VT:$Rm)>; } defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>; defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>; defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_addp>; defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>; defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>; defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>; defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>; defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>; defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>; defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>; defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>; defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>; defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>; // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the // instruction expects the addend first, while the fma intrinsic puts it last. defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla", TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls", TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; // The following def pats catch the case where the LHS of an FMA is negated. // The TriOpFrag above catches the case where the middle operand is negated. def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)), (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>; def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>; defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>; defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>; defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>; defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>; defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>; defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >; defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls", TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >; defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>; defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>; defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba", TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >; defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>; defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>; defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>; defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>; defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>; defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>; defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>; defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>; defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>; defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>; defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>; defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>; defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>; defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>; defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>; defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>; defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>; defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba", TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >; defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>; defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>; defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>; defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>; defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>; defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>; defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>; defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>; defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>; defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>; defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>; defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>; defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>; defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>; defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah", int_aarch64_neon_sqadd>; defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh", int_aarch64_neon_sqsub>; defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>; defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic", BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >; defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">; defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>; defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl", TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>; defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>; defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn", BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >; defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>; def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm), (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm), (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm), (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm), (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm), (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm), (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm), (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm), (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}", (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>; def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}", (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}", (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}", (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>; def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}", (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>; def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}", (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}", (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}", (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>; def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" # "|cmls.8b\t$dst, $src1, $src2}", (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" # "|cmls.16b\t$dst, $src1, $src2}", (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" # "|cmls.4h\t$dst, $src1, $src2}", (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" # "|cmls.8h\t$dst, $src1, $src2}", (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" # "|cmls.2s\t$dst, $src1, $src2}", (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" # "|cmls.4s\t$dst, $src1, $src2}", (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" # "|cmls.2d\t$dst, $src1, $src2}", (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" # "|cmlo.8b\t$dst, $src1, $src2}", (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" # "|cmlo.16b\t$dst, $src1, $src2}", (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" # "|cmlo.4h\t$dst, $src1, $src2}", (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" # "|cmlo.8h\t$dst, $src1, $src2}", (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" # "|cmlo.2s\t$dst, $src1, $src2}", (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" # "|cmlo.4s\t$dst, $src1, $src2}", (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" # "|cmlo.2d\t$dst, $src1, $src2}", (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" # "|cmle.8b\t$dst, $src1, $src2}", (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" # "|cmle.16b\t$dst, $src1, $src2}", (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" # "|cmle.4h\t$dst, $src1, $src2}", (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" # "|cmle.8h\t$dst, $src1, $src2}", (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" # "|cmle.2s\t$dst, $src1, $src2}", (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" # "|cmle.4s\t$dst, $src1, $src2}", (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" # "|cmle.2d\t$dst, $src1, $src2}", (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" # "|cmlt.8b\t$dst, $src1, $src2}", (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" # "|cmlt.16b\t$dst, $src1, $src2}", (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" # "|cmlt.4h\t$dst, $src1, $src2}", (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" # "|cmlt.8h\t$dst, $src1, $src2}", (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" # "|cmlt.2s\t$dst, $src1, $src2}", (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" # "|cmlt.4s\t$dst, $src1, $src2}", (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" # "|cmlt.2d\t$dst, $src1, $src2}", (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" # "|fcmle.4h\t$dst, $src1, $src2}", (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" # "|fcmle.8h\t$dst, $src1, $src2}", (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; } def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" # "|fcmle.2s\t$dst, $src1, $src2}", (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" # "|fcmle.4s\t$dst, $src1, $src2}", (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" # "|fcmle.2d\t$dst, $src1, $src2}", (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" # "|fcmlt.4h\t$dst, $src1, $src2}", (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" # "|fcmlt.8h\t$dst, $src1, $src2}", (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; } def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" # "|fcmlt.2s\t$dst, $src1, $src2}", (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" # "|fcmlt.4s\t$dst, $src1, $src2}", (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" # "|fcmlt.2d\t$dst, $src1, $src2}", (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" # "|facle.4h\t$dst, $src1, $src2}", (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" # "|facle.8h\t$dst, $src1, $src2}", (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; } def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" # "|facle.2s\t$dst, $src1, $src2}", (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" # "|facle.4s\t$dst, $src1, $src2}", (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" # "|facle.2d\t$dst, $src1, $src2}", (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; let Predicates = [HasNEON, HasFullFP16] in { def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" # "|faclt.4h\t$dst, $src1, $src2}", (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" # "|faclt.8h\t$dst, $src1, $src2}", (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>; } def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" # "|faclt.2s\t$dst, $src1, $src2}", (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>; def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" # "|faclt.4s\t$dst, $src1, $src2}", (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>; def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" # "|faclt.2d\t$dst, $src1, $src2}", (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; //===----------------------------------------------------------------------===// // Advanced SIMD three scalar instructions. //===----------------------------------------------------------------------===// defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>; defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>; defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>; defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>; defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>; defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>; defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>; defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>; def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FABD64 FPR64:$Rn, FPR64:$Rm)>; let Predicates = [HasFullFP16] in { def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>; } def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>; def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>; defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge", int_aarch64_neon_facge>; defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt", int_aarch64_neon_facgt>; defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>; defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>; defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>; defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>; defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>; defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>; defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>; defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>; defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>; defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>; defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>; defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>; defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>; defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>; defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>; defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>; defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>; defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>; defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>; defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>; defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>; let Predicates = [HasRDM] in { defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">; defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">; def : Pat<(i32 (int_aarch64_neon_sqadd (i32 FPR32:$Rd), (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), (i32 FPR32:$Rm))))), (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; def : Pat<(i32 (int_aarch64_neon_sqsub (i32 FPR32:$Rd), (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn), (i32 FPR32:$Rm))))), (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>; } def : InstAlias<"cmls $dst, $src1, $src2", (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmle $dst, $src1, $src2", (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmlo $dst, $src1, $src2", (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmlt $dst, $src1, $src2", (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"fcmle $dst, $src1, $src2", (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"fcmle $dst, $src1, $src2", (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"fcmlt $dst, $src1, $src2", (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"fcmlt $dst, $src1, $src2", (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"facle $dst, $src1, $src2", (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"facle $dst, $src1, $src2", (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"faclt $dst, $src1, $src2", (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"faclt $dst, $src1, $src2", (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; //===----------------------------------------------------------------------===// // Advanced SIMD three scalar instructions (mixed operands). //===----------------------------------------------------------------------===// defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull", int_aarch64_neon_sqdmulls_scalar>; defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">; defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">; def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd), (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), (i32 FPR32:$Rm))))), (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd), (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), (i32 FPR32:$Rm))))), (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>; //===----------------------------------------------------------------------===// // Advanced SIMD two scalar instructions. //===----------------------------------------------------------------------===// defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs>; defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>; defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>; defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>; defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>; defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>; defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>; defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>; defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>; defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>; defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>; defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">; defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">; defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">; defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">; defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">; defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">; defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">; defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">; def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">; defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">; defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">; defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">; defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">; defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">; defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg", UnOpFrag<(sub immAllZerosV, node:$LHS)> >; defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>; defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>; defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>; defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>; defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>; defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd", int_aarch64_neon_suqadd>; defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>; defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>; defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd", int_aarch64_neon_usqadd>; def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))), (FCVTASv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))), (FCVTAUv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))), (FCVTMSv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))), (FCVTMUv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))), (FCVTNSv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))), (FCVTNUv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))), (FCVTPSv1i64 FPR64:$Rn)>; def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))), (FCVTPUv1i64 FPR64:$Rn)>; def : Pat<(f16 (int_aarch64_neon_frecpe (f16 FPR16:$Rn))), (FRECPEv1f16 FPR16:$Rn)>; def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))), (FRECPEv1i32 FPR32:$Rn)>; def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))), (FRECPEv1i64 FPR64:$Rn)>; def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))), (FRECPEv1i64 FPR64:$Rn)>; def : Pat<(f32 (AArch64frecpe (f32 FPR32:$Rn))), (FRECPEv1i32 FPR32:$Rn)>; def : Pat<(v2f32 (AArch64frecpe (v2f32 V64:$Rn))), (FRECPEv2f32 V64:$Rn)>; def : Pat<(v4f32 (AArch64frecpe (v4f32 FPR128:$Rn))), (FRECPEv4f32 FPR128:$Rn)>; def : Pat<(f64 (AArch64frecpe (f64 FPR64:$Rn))), (FRECPEv1i64 FPR64:$Rn)>; def : Pat<(v1f64 (AArch64frecpe (v1f64 FPR64:$Rn))), (FRECPEv1i64 FPR64:$Rn)>; def : Pat<(v2f64 (AArch64frecpe (v2f64 FPR128:$Rn))), (FRECPEv2f64 FPR128:$Rn)>; def : Pat<(f32 (AArch64frecps (f32 FPR32:$Rn), (f32 FPR32:$Rm))), (FRECPS32 FPR32:$Rn, FPR32:$Rm)>; def : Pat<(v2f32 (AArch64frecps (v2f32 V64:$Rn), (v2f32 V64:$Rm))), (FRECPSv2f32 V64:$Rn, V64:$Rm)>; def : Pat<(v4f32 (AArch64frecps (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>; def : Pat<(f64 (AArch64frecps (f64 FPR64:$Rn), (f64 FPR64:$Rm))), (FRECPS64 FPR64:$Rn, FPR64:$Rm)>; def : Pat<(v2f64 (AArch64frecps (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>; def : Pat<(f16 (int_aarch64_neon_frecpx (f16 FPR16:$Rn))), (FRECPXv1f16 FPR16:$Rn)>; def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))), (FRECPXv1i32 FPR32:$Rn)>; def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))), (FRECPXv1i64 FPR64:$Rn)>; def : Pat<(f16 (int_aarch64_neon_frsqrte (f16 FPR16:$Rn))), (FRSQRTEv1f16 FPR16:$Rn)>; def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))), (FRSQRTEv1i32 FPR32:$Rn)>; def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))), (FRSQRTEv1i64 FPR64:$Rn)>; def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))), (FRSQRTEv1i64 FPR64:$Rn)>; def : Pat<(f32 (AArch64frsqrte (f32 FPR32:$Rn))), (FRSQRTEv1i32 FPR32:$Rn)>; def : Pat<(v2f32 (AArch64frsqrte (v2f32 V64:$Rn))), (FRSQRTEv2f32 V64:$Rn)>; def : Pat<(v4f32 (AArch64frsqrte (v4f32 FPR128:$Rn))), (FRSQRTEv4f32 FPR128:$Rn)>; def : Pat<(f64 (AArch64frsqrte (f64 FPR64:$Rn))), (FRSQRTEv1i64 FPR64:$Rn)>; def : Pat<(v1f64 (AArch64frsqrte (v1f64 FPR64:$Rn))), (FRSQRTEv1i64 FPR64:$Rn)>; def : Pat<(v2f64 (AArch64frsqrte (v2f64 FPR128:$Rn))), (FRSQRTEv2f64 FPR128:$Rn)>; def : Pat<(f32 (AArch64frsqrts (f32 FPR32:$Rn), (f32 FPR32:$Rm))), (FRSQRTS32 FPR32:$Rn, FPR32:$Rm)>; def : Pat<(v2f32 (AArch64frsqrts (v2f32 V64:$Rn), (v2f32 V64:$Rm))), (FRSQRTSv2f32 V64:$Rn, V64:$Rm)>; def : Pat<(v4f32 (AArch64frsqrts (v4f32 FPR128:$Rn), (v4f32 FPR128:$Rm))), (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>; def : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))), (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>; def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>; // If an integer is about to be converted to a floating point value, // just load it on the floating point unit. // Here are the patterns for 8 and 16-bits to float. // 8-bits -> float. multiclass UIntToFPROLoadPat { def : Pat<(DstTy (uint_to_fp (SrcTy (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))))), (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), sub))>; def : Pat<(DstTy (uint_to_fp (SrcTy (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Wext:$extend))))), (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)), (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), sub))>; } defm : UIntToFPROLoadPat; def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; // 16-bits -> float. defm : UIntToFPROLoadPat; def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)), (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; // 32-bits are handled in target specific dag combine: // performIntToFpCombine. // 64-bits integer to 32-bits floating point, not possible with // UCVTF on floating point registers (both source and destination // must have the same size). // Here are the patterns for 8, 16, 32, and 64-bits to double. // 8-bits -> double. defm : UIntToFPROLoadPat; def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>; def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>; // 16-bits -> double. defm : UIntToFPROLoadPat; def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>; def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>; // 32-bits -> double. defm : UIntToFPROLoadPat; def : Pat <(f64 (uint_to_fp (i32 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))), (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>; def : Pat <(f64 (uint_to_fp (i32 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))), (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>; // 64-bits -> double are handled in target specific dag combine: // performIntToFpCombine. //===----------------------------------------------------------------------===// // Advanced SIMD three different-sized vector instructions. //===----------------------------------------------------------------------===// defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>; defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>; defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>; defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>; defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>; defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal", int_aarch64_neon_sabd>; defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl", int_aarch64_neon_sabd>; defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl", BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>; defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw", BinOpFrag<(add node:$LHS, (sext node:$RHS))>>; defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal", TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl", TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>; defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal", int_aarch64_neon_sqadd>; defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl", int_aarch64_neon_sqsub>; defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull", int_aarch64_neon_sqdmull>; defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl", BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>; defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw", BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>; defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal", int_aarch64_neon_uabd>; defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl", BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>; defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw", BinOpFrag<(add node:$LHS, (zext node:$RHS))>>; defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal", TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl", TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>; defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl", BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>; defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw", BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>; // Additional patterns for SMULL and UMULL multiclass Neon_mul_widen_patterns { def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))), (INST8B V64:$Rn, V64:$Rm)>; def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))), (INST4H V64:$Rn, V64:$Rm)>; def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))), (INST2S V64:$Rn, V64:$Rm)>; } defm : Neon_mul_widen_patterns; defm : Neon_mul_widen_patterns; // Patterns for smull2/umull2. multiclass Neon_mul_high_patterns { def : Pat<(v8i16 (opnode (extract_high_v16i8 V128:$Rn), (extract_high_v16i8 V128:$Rm))), (INST8B V128:$Rn, V128:$Rm)>; def : Pat<(v4i32 (opnode (extract_high_v8i16 V128:$Rn), (extract_high_v8i16 V128:$Rm))), (INST4H V128:$Rn, V128:$Rm)>; def : Pat<(v2i64 (opnode (extract_high_v4i32 V128:$Rn), (extract_high_v4i32 V128:$Rm))), (INST2S V128:$Rn, V128:$Rm)>; } defm : Neon_mul_high_patterns; defm : Neon_mul_high_patterns; // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL multiclass Neon_mulacc_widen_patterns { def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))), (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))), (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))), (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>; } defm : Neon_mulacc_widen_patterns< TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>; defm : Neon_mulacc_widen_patterns< TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>; defm : Neon_mulacc_widen_patterns< TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>, SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>; defm : Neon_mulacc_widen_patterns< TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>, UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>; // Patterns for 64-bit pmull def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm), (PMULLv1i64 V64:$Rn, V64:$Rm)>; def : Pat<(int_aarch64_neon_pmull64 (extractelt (v2i64 V128:$Rn), (i64 1)), (extractelt (v2i64 V128:$Rm), (i64 1))), (PMULLv2i64 V128:$Rn, V128:$Rm)>; // CodeGen patterns for addhn and subhn instructions, which can actually be // written in LLVM IR without too much difficulty. // ADDHN def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))), (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 16))))), (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 32))))), (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v8i8 V64:$Rd), (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))), (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v4i16 V64:$Rd), (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 16))))), (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v2i32 V64:$Rd), (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 32))))), (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; // SUBHN def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))), (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>; def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 16))))), (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>; def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 32))))), (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v8i8 V64:$Rd), (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))), (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v4i16 V64:$Rd), (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 16))))), (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(concat_vectors (v2i32 V64:$Rd), (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 32))))), (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; //---------------------------------------------------------------------------- // AdvSIMD bitwise extract from vector instruction. //---------------------------------------------------------------------------- defm EXT : SIMDBitwiseExtract<"ext">; def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))), (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>; def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))), (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>; // We use EXT to handle extract_subvector to copy the upper 64-bits of a // 128-bit vector. def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>; //---------------------------------------------------------------------------- // AdvSIMD zip vector //---------------------------------------------------------------------------- defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>; defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>; defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>; defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>; defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>; defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>; //---------------------------------------------------------------------------- // AdvSIMD TBL/TBX instructions //---------------------------------------------------------------------------- defm TBL : SIMDTableLookup< 0, "tbl">; defm TBX : SIMDTableLookupTied<1, "tbx">; def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>; def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), (TBLv16i8One V128:$Ri, V128:$Rn)>; def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd), (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>; def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd), (v16i8 V128:$Ri), (v16i8 V128:$Rn))), (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>; //---------------------------------------------------------------------------- // AdvSIMD scalar CPY instruction //---------------------------------------------------------------------------- defm CPY : SIMDScalarCPY<"cpy">; //---------------------------------------------------------------------------- // AdvSIMD scalar pairwise instructions //---------------------------------------------------------------------------- defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">; defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">; defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">; defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">; defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">; defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">; def : Pat<(v2i64 (AArch64saddv V128:$Rn)), (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; def : Pat<(v2i64 (AArch64uaddv V128:$Rn)), (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>; def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))), (FADDPv2i32p V64:$Rn)>; def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))), (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>; def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))), (FADDPv2i64p V128:$Rn)>; def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))), (FMAXNMPv2i32p V64:$Rn)>; def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))), (FMAXNMPv2i64p V128:$Rn)>; def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))), (FMAXPv2i32p V64:$Rn)>; def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))), (FMAXPv2i64p V128:$Rn)>; def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))), (FMINNMPv2i32p V64:$Rn)>; def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))), (FMINNMPv2i64p V128:$Rn)>; def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))), (FMINPv2i32p V64:$Rn)>; def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))), (FMINPv2i64p V128:$Rn)>; //---------------------------------------------------------------------------- // AdvSIMD INS/DUP instructions //---------------------------------------------------------------------------- def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>; def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>; def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>; def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>; def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>; def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>; def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>; def DUPv2i64lane : SIMDDup64FromElement; def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>; def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>; def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>; def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>; def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>; def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>; def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))), (v2f32 (DUPv2i32lane (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), (i64 0)))>; def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))), (v4f32 (DUPv4i32lane (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub), (i64 0)))>; def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))), (v2f64 (DUPv2i64lane (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub), (i64 0)))>; def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))), (v4f16 (DUPv4i16lane (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), (i64 0)))>; def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))), (v8f16 (DUPv8i16lane (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub), (i64 0)))>; def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>; def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)), (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>; def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>; def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)), (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>; def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)), (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>; // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane // instruction even if the types don't match: we just have to remap the lane // carefully. N.b. this trick only applies to truncations. def VecIndex_x2 : SDNodeXFormgetTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64); }]>; def VecIndex_x4 : SDNodeXFormgetTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64); }]>; def VecIndex_x8 : SDNodeXFormgetTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64); }]>; multiclass DUPWithTruncPats { def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn), imm:$idx)))), (DUP V128:$Rn, (IdxXFORM imm:$idx))>; def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn), imm:$idx)))), (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; } defm : DUPWithTruncPats; defm : DUPWithTruncPats; defm : DUPWithTruncPats; defm : DUPWithTruncPats; defm : DUPWithTruncPats; defm : DUPWithTruncPats; multiclass DUPWithTrunci64Pats { def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn), imm:$idx))))), (DUP V128:$Rn, (IdxXFORM imm:$idx))>; def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn), imm:$idx))))), (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>; } defm : DUPWithTrunci64Pats; defm : DUPWithTrunci64Pats; defm : DUPWithTrunci64Pats; defm : DUPWithTrunci64Pats; defm : DUPWithTrunci64Pats; defm : DUPWithTrunci64Pats; // SMOV and UMOV definitions, with some extra patterns for convenience defm SMOV : SMov; defm UMOV : UMov; def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>; def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16), (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>; def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))), (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>; def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx)))), i8), (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>; def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx)))), i16), (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>; // Extracting i8 or i16 elements will have the zero-extend transformed to // an 'and' mask by type legalization since neither i8 nor i16 are legal types // for AArch64. Match these patterns here since UMOV already zeroes out the high // bits of the destination register. def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), (i32 0xff)), (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>; def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), (i32 0xffff)), (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>; defm INS : SIMDIns; def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)), (SUBREG_TO_REG (i32 0), (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)), (SUBREG_TO_REG (i32 0), (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)), (SUBREG_TO_REG (i32 0), (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)), (SUBREG_TO_REG (i32 0), (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))), (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 FPR32:$Rn), ssub))>; def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))), (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (i32 FPR32:$Rn), ssub))>; def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))), (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (i64 FPR64:$Rn), dsub))>; def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))), (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))), (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>; def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))), (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>; def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))), (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>; def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn), (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))), (EXTRACT_SUBREG (INSvi16lane (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)), VectorIndexS:$imm, (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), (i64 0)), dsub)>; def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn), (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))), (INSvi16lane V128:$Rn, VectorIndexH:$imm, (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)), (i64 0))>; def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn), (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), (EXTRACT_SUBREG (INSvi32lane (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)), VectorIndexS:$imm, (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), (i64 0)), dsub)>; def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn), (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))), (INSvi32lane V128:$Rn, VectorIndexS:$imm, (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)), (i64 0))>; def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn), (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))), (INSvi64lane V128:$Rn, VectorIndexD:$imm, (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)), (i64 0))>; // Copy an element at a constant index in one vector into a constant indexed // element of another. // FIXME refactor to a shared class/dev parameterized on vector type, vector // index type and INS extension def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs), VectorIndexB:$idx2)), (v16i8 (INSvi8lane V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2) )>; def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs), VectorIndexH:$idx2)), (v8i16 (INSvi16lane V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2) )>; def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs), VectorIndexS:$idx2)), (v4i32 (INSvi32lane V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2) )>; def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs), VectorIndexD:$idx2)), (v2i64 (INSvi64lane V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2) )>; multiclass Neon_INS_elt_pattern { def : Pat<(VT128 (vector_insert V128:$src, (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), imm:$Immd)), (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>; def : Pat<(VT128 (vector_insert V128:$src, (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), imm:$Immd)), (INS V128:$src, imm:$Immd, (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>; def : Pat<(VT64 (vector_insert V64:$src, (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), imm:$Immd)), (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, V128:$Rn, imm:$Immn), dsub)>; def : Pat<(VT64 (vector_insert V64:$src, (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), imm:$Immd)), (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn), dsub)>; } defm : Neon_INS_elt_pattern; defm : Neon_INS_elt_pattern; defm : Neon_INS_elt_pattern; // Floating point vector extractions are codegen'd as either a sequence of // subregister extractions, or a MOV (aka CPY here, alias for DUP) if // the lane number is anything other than zero. def : Pat<(vector_extract (v2f64 V128:$Rn), 0), (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>; def : Pat<(vector_extract (v4f32 V128:$Rn), 0), (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>; def : Pat<(vector_extract (v8f16 V128:$Rn), 0), (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>; def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx), (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>; def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx), (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>; def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx), (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>; // All concat_vectors operations are canonicalised to act on i64 vectors for // AArch64. In the general case we need an instruction, which had just as well be // INS. class ConcatPat : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)), (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1, (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>; def : ConcatPat; def : ConcatPat; def : ConcatPat; def : ConcatPat; def : ConcatPat; def : ConcatPat; def : ConcatPat; // If the high lanes are undef, though, we can just ignore them: class ConcatUndefPat : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)), (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>; def : ConcatUndefPat; def : ConcatUndefPat; def : ConcatUndefPat; def : ConcatUndefPat; def : ConcatUndefPat; def : ConcatUndefPat; //---------------------------------------------------------------------------- // AdvSIMD across lanes instructions //---------------------------------------------------------------------------- defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">; defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">; defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">; defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">; defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">; defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">; defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">; defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>; defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>; defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>; defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>; // Patterns for across-vector intrinsics, that have a node equivalent, that // returns a vector (with only the low lane defined) instead of a scalar. // In effect, opNode is the same as (scalar_to_vector (IntNode)). multiclass SIMDAcrossLanesIntrinsic { // If a lane instruction caught the vector_extract around opNode, we can // directly match the latter to the instruction. def : Pat<(v8i8 (opNode V64:$Rn)), (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>; def : Pat<(v16i8 (opNode V128:$Rn)), (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>; def : Pat<(v4i16 (opNode V64:$Rn)), (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>; def : Pat<(v8i16 (opNode V128:$Rn)), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>; def : Pat<(v4i32 (opNode V128:$Rn)), (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>; // If none did, fallback to the explicit patterns, consuming the vector_extract. def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)), (i32 0)), (i64 0))), (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), ssub)>; def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))), (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), ssub)>; def : Pat<(i32 (vector_extract (insert_subvector undef, (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))), (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), ssub)>; def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))), (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), ssub)>; def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))), (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub), ssub)>; } multiclass SIMDAcrossLanesSignedIntrinsic : SIMDAcrossLanesIntrinsic { // If there is a sign extension after this intrinsic, consume it as smov already // performed it def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)), (i32 (SMOVvi8to32 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), (i64 0)))>; def : Pat<(i32 (sext_inreg (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))), i8)), (i32 (SMOVvi8to32 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), (i64 0)))>; def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef, (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)), (i32 (SMOVvi16to32 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), (i64 0)))>; def : Pat<(i32 (sext_inreg (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))), i16)), (i32 (SMOVvi16to32 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), (i64 0)))>; } multiclass SIMDAcrossLanesUnsignedIntrinsic : SIMDAcrossLanesIntrinsic { // If there is a masking operation keeping only what has been actually // generated, consume it. def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub), ssub))>; def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))), maski8_or_more)), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub), ssub))>; def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef, (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub), ssub))>; def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))), maski16_or_more)), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub), ssub))>; } defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>; // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))), (ADDPv2i32 V64:$Rn, V64:$Rn)>; defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>; // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))), (ADDPv2i32 V64:$Rn, V64:$Rn)>; defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>; def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))), (SMAXPv2i32 V64:$Rn, V64:$Rn)>; defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>; def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))), (SMINPv2i32 V64:$Rn, V64:$Rn)>; defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>; def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))), (UMAXPv2i32 V64:$Rn, V64:$Rn)>; defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>; def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))), (UMINPv2i32 V64:$Rn, V64:$Rn)>; multiclass SIMDAcrossLanesSignedLongIntrinsic { def : Pat<(i32 (intOp (v8i8 V64:$Rn))), (i32 (SMOVvi16to32 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), (i64 0)))>; def : Pat<(i32 (intOp (v16i8 V128:$Rn))), (i32 (SMOVvi16to32 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), (i64 0)))>; def : Pat<(i32 (intOp (v4i16 V64:$Rn))), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), ssub))>; def : Pat<(i32 (intOp (v8i16 V128:$Rn))), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), ssub))>; def : Pat<(i64 (intOp (v4i32 V128:$Rn))), (i64 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), dsub))>; } multiclass SIMDAcrossLanesUnsignedLongIntrinsic { def : Pat<(i32 (intOp (v8i8 V64:$Rn))), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub), ssub))>; def : Pat<(i32 (intOp (v16i8 V128:$Rn))), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub), ssub))>; def : Pat<(i32 (intOp (v4i16 V64:$Rn))), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub), ssub))>; def : Pat<(i32 (intOp (v8i16 V128:$Rn))), (i32 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub), ssub))>; def : Pat<(i64 (intOp (v4i32 V128:$Rn))), (i64 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (!cast(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub), dsub))>; } defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>; defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>; // The vaddlv_s32 intrinsic gets mapped to SADDLP. def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))), (i64 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (SADDLPv2i32_v1i64 V64:$Rn), dsub), dsub))>; // The vaddlv_u32 intrinsic gets mapped to UADDLP. def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))), (i64 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (UADDLPv2i32_v1i64 V64:$Rn), dsub), dsub))>; //------------------------------------------------------------------------------ // AdvSIMD modified immediate instructions //------------------------------------------------------------------------------ // AdvSIMD BIC defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>; // AdvSIMD ORR defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>; def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; // AdvSIMD FMOV def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, "fmov", ".2d", [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8, "fmov", ".2s", [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8, "fmov", ".4s", [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; let Predicates = [HasNEON, HasFullFP16] in { def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8, "fmov", ".4h", [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>; def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8, "fmov", ".8h", [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; } // Predicates = [HasNEON, HasFullFP16] // AdvSIMD MOVI // EDIT byte mask: scalar let isReMaterializable = 1, isAsCheapAsAMove = 1 in def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi", [(set FPR64:$Rd, simdimmtype10:$imm8)]>; // The movi_edit node has the immediate value already encoded, so we use // a plain imm0_255 here. def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)), (MOVID imm0_255:$shift)>; def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>; def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>; def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>; def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>; def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>; def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>; def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>; def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>; // EDIT byte mask: 2d // The movi_edit node has the immediate value already encoded, so we use // a plain imm0_255 in the pattern let isReMaterializable = 1, isAsCheapAsAMove = 1 in def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128, simdimmtype10, "movi", ".2d", [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>; def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>; def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>; def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>; def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>; def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>; def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>; def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>; def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>; // EDIT per word & halfword: 2s, 4h, 4s, & 8h let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">; def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), (MOVIv2i32 imm0_255:$imm8, imm:$shift)>; def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), (MOVIv4i32 imm0_255:$imm8, imm:$shift)>; def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), (MOVIv4i16 imm0_255:$imm8, imm:$shift)>; def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), (MOVIv8i16 imm0_255:$imm8, imm:$shift)>; let isReMaterializable = 1, isAsCheapAsAMove = 1 in { // EDIT per word: 2s & 4s with MSL shifter def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s", [(set (v2i32 V64:$Rd), (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s", [(set (v4i32 V128:$Rd), (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; // Per byte: 8b & 16b def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255, "movi", ".8b", [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>; def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255, "movi", ".16b", [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>; } // AdvSIMD MVNI // EDIT per word & halfword: 2s, 4h, 4s, & 8h let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), (MVNIv2i32 imm0_255:$imm8, imm:$shift)>; def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), (MVNIv4i32 imm0_255:$imm8, imm:$shift)>; def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), (MVNIv4i16 imm0_255:$imm8, imm:$shift)>; def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), (MVNIv8i16 imm0_255:$imm8, imm:$shift)>; // EDIT per word: 2s & 4s with MSL shifter let isReMaterializable = 1, isAsCheapAsAMove = 1 in { def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s", [(set (v2i32 V64:$Rd), (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s", [(set (v4i32 V128:$Rd), (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; } //---------------------------------------------------------------------------- // AdvSIMD indexed element //---------------------------------------------------------------------------- let hasSideEffects = 0 in { defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">; defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">; } // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the // instruction expects the addend first, while the intrinsic expects it last. // On the other hand, there are quite a few valid combinatorial options due to // the commutativity of multiplication and the fact that (-x) * y = x * (-y). defm : SIMDFPIndexedTiedPatterns<"FMLA", TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>; defm : SIMDFPIndexedTiedPatterns<"FMLA", TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>; defm : SIMDFPIndexedTiedPatterns<"FMLS", TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; defm : SIMDFPIndexedTiedPatterns<"FMLS", TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >; defm : SIMDFPIndexedTiedPatterns<"FMLS", TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >; defm : SIMDFPIndexedTiedPatterns<"FMLS", TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >; multiclass FMLSIndexedAfterNegPatterns { // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit // and DUP scalar. def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64duplane32 (v4f32 (fneg V128:$Rm)), VectorIndexS:$idx))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 (AArch64duplane32 (v4f32 (insert_subvector undef, (v2f32 (fneg V64:$Rm)), (i32 0))), VectorIndexS:$idx)))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64dup (f32 (fneg FPR32Op:$Rm))))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit // and DUP scalar. def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64duplane32 (v4f32 (fneg V128:$Rm)), VectorIndexS:$idx))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 (AArch64duplane32 (v4f32 (insert_subvector undef, (v2f32 (fneg V64:$Rm)), (i32 0))), VectorIndexS:$idx)))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64dup (f32 (fneg FPR32Op:$Rm))))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar // (DUPLANE from 64-bit would be trivial). def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64duplane64 (v2f64 (fneg V128:$Rm)), VectorIndexD:$idx))), (FMLSv2i64_indexed V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64dup (f64 (fneg FPR64Op:$Rm))))), (FMLSv2i64_indexed V128:$Rd, V128:$Rn, (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; // 2 variants for 32-bit scalar version: extract from .2s or from .4s def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), (vector_extract (v4f32 (fneg V128:$Rm)), VectorIndexS:$idx))), (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, V128:$Rm, VectorIndexS:$idx)>; def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), (vector_extract (v4f32 (insert_subvector undef, (v2f32 (fneg V64:$Rm)), (i32 0))), VectorIndexS:$idx))), (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; // 1 variant for 64-bit scalar version: extract from .1d or from .2d def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), (vector_extract (v2f64 (fneg V128:$Rm)), VectorIndexS:$idx))), (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn, V128:$Rm, VectorIndexS:$idx)>; } defm : FMLSIndexedAfterNegPatterns< TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; defm : FMLSIndexedAfterNegPatterns< TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >; defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>; defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>; def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))), (FMULv2i32_indexed V64:$Rn, (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), (i64 0))>; def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))), (FMULv4i32_indexed V128:$Rn, (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub), (i64 0))>; def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))), (FMULv2i64_indexed V128:$Rn, (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub), (i64 0))>; defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>; defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>; defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla", TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>; defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls", TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>; defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>; defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal", TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl", TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>; defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", int_aarch64_neon_smull>; defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal", int_aarch64_neon_sqadd>; defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl", int_aarch64_neon_sqsub>; defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah", int_aarch64_neon_sqadd>; defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh", int_aarch64_neon_sqsub>; defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>; defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal", TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl", TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>; defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull", int_aarch64_neon_umull>; // A scalar sqdmull with the second operand being a vector lane can be // handled directly with the indexed instruction encoding. def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn), (vector_extract (v4i32 V128:$Vm), VectorIndexS:$idx)), (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>; //---------------------------------------------------------------------------- // AdvSIMD scalar shift instructions //---------------------------------------------------------------------------- defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">; defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">; defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">; defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">; // Codegen patterns for the above. We don't put these directly on the // instructions because TableGen's type inference can't handle the truth. // Having the same base pattern for fp <--> int totally freaks it out. def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm), (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>; def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm), (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>; def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)), (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)), (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn), vecshiftR64:$imm)), (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn), vecshiftR64:$imm)), (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm), (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>; def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn), vecshiftR64:$imm)), (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)), (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn), vecshiftR64:$imm)), (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>; def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm), (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>; // Patterns for FP16 Instrinsics - requires reg copy to/from as i16s not supported. def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), vecshiftR16:$imm)), (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)), (SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (and FPR32:$Rn, (i32 65535)), vecshiftR16:$imm)), (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)), (UCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>; def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR16:$imm)), (UCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>; def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR32:$imm)), (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (FCVTZSh FPR16:$Rn, vecshiftR32:$imm), hsub))>; def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)), (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (FCVTZSh FPR16:$Rn, vecshiftR64:$imm), hsub))>; def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR32:$imm)), (i32 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (FCVTZUh FPR16:$Rn, vecshiftR32:$imm), hsub))>; def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f16 FPR16:$Rn), vecshiftR64:$imm)), (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (FCVTZUh FPR16:$Rn, vecshiftR64:$imm), hsub))>; defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>; defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">; defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn", int_aarch64_neon_sqrshrn>; defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun", int_aarch64_neon_sqrshrun>; defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn", int_aarch64_neon_sqshrn>; defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun", int_aarch64_neon_sqshrun>; defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">; defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>; defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra", TriOpFrag<(add node:$LHS, (AArch64srshri node:$MHS, node:$RHS))>>; defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>; defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra", TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>; defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn", int_aarch64_neon_uqrshrn>; defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn", int_aarch64_neon_uqshrn>; defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>; defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra", TriOpFrag<(add node:$LHS, (AArch64urshri node:$MHS, node:$RHS))>>; defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>; defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra", TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))>>; //---------------------------------------------------------------------------- // AdvSIMD vector shift instructions //---------------------------------------------------------------------------- defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>; defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>; defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", int_aarch64_neon_vcvtfxs2fp>; defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn", int_aarch64_neon_rshrn>; defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>; defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn", BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>; defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>; def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))), (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>; defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn", int_aarch64_neon_sqrshrn>; defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun", int_aarch64_neon_sqrshrun>; defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>; defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>; defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn", int_aarch64_neon_sqshrn>; defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun", int_aarch64_neon_sqshrun>; defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>; def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))), (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>; defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>; defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra", TriOpFrag<(add node:$LHS, (AArch64srshri node:$MHS, node:$RHS))> >; defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll", BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>; defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>; defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra", TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>; defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf", int_aarch64_neon_vcvtfxu2fp>; defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn", int_aarch64_neon_uqrshrn>; defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>; defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn", int_aarch64_neon_uqshrn>; defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>; defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra", TriOpFrag<(add node:$LHS, (AArch64urshri node:$MHS, node:$RHS))> >; defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll", BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>; defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>; defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra", TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >; // SHRN patterns for when a logical right shift was used instead of arithmetic // (the immediate guarantees no sign bits actually end up in the result so it // doesn't matter). def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))), (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>; def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))), (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>; def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))), (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>; def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd), (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm)))), (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, vecshiftR16Narrow:$imm)>; def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd), (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm)))), (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, vecshiftR32Narrow:$imm)>; def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd), (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm)))), (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn, vecshiftR32Narrow:$imm)>; // Vector sign and zero extensions are implemented with SSHLL and USSHLL. // Anyexts are implemented as zexts. def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>; def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>; def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>; def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>; def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>; def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>; // Also match an extend from the upper half of a 128 bit source register. def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), (USHLLv16i8_shift V128:$Rn, (i32 0))>; def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), (USHLLv16i8_shift V128:$Rn, (i32 0))>; def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))), (SSHLLv16i8_shift V128:$Rn, (i32 0))>; def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), (USHLLv8i16_shift V128:$Rn, (i32 0))>; def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), (USHLLv8i16_shift V128:$Rn, (i32 0))>; def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))), (SSHLLv8i16_shift V128:$Rn, (i32 0))>; def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), (USHLLv4i32_shift V128:$Rn, (i32 0))>; def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), (USHLLv4i32_shift V128:$Rn, (i32 0))>; def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))), (SSHLLv4i32_shift V128:$Rn, (i32 0))>; // Vector shift sxtl aliases def : InstAlias<"sxtl.8h $dst, $src1", (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"sxtl $dst.8h, $src1.8b", (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"sxtl.4s $dst, $src1", (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"sxtl $dst.4s, $src1.4h", (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"sxtl.2d $dst, $src1", (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"sxtl $dst.2d, $src1.2s", (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>; // Vector shift sxtl2 aliases def : InstAlias<"sxtl2.8h $dst, $src1", (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"sxtl2 $dst.8h, $src1.16b", (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"sxtl2.4s $dst, $src1", (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"sxtl2 $dst.4s, $src1.8h", (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"sxtl2.2d $dst, $src1", (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"sxtl2 $dst.2d, $src1.4s", (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>; // Vector shift uxtl aliases def : InstAlias<"uxtl.8h $dst, $src1", (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"uxtl $dst.8h, $src1.8b", (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"uxtl.4s $dst, $src1", (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"uxtl $dst.4s, $src1.4h", (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"uxtl.2d $dst, $src1", (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; def : InstAlias<"uxtl $dst.2d, $src1.2s", (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>; // Vector shift uxtl2 aliases def : InstAlias<"uxtl2.8h $dst, $src1", (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2 $dst.8h, $src1.16b", (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2.4s $dst, $src1", (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2 $dst.4s, $src1.8h", (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2.2d $dst, $src1", (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2 $dst.2d, $src1.4s", (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; // If an integer is about to be converted to a floating point value, // just load it on the floating point unit. // These patterns are more complex because floating point loads do not // support sign extension. // The sign extension has to be explicitly added and is only supported for // one step: byte-to-half, half-to-word, word-to-doubleword. // SCVTF GPR -> FPR is 9 cycles. // SCVTF FPR -> FPR is 4 cyclces. // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles. // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR // and still being faster. // However, this is not good for code size. // 8-bits -> float. 2 sizes step-up. class SExtLoadi8CVTf32Pat : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))), (SCVTFv1i32 (f32 (EXTRACT_SUBREG (SSHLLv4i16_shift (f64 (EXTRACT_SUBREG (SSHLLv8i8_shift (INSERT_SUBREG (f64 (IMPLICIT_DEF)), INST, bsub), 0), dsub)), 0), ssub)))>, Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext), (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>; def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext), (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>; def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset), (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>; def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset), (LDURBi GPR64sp:$Rn, simm9:$offset)>; // 16-bits -> float. 1 size step-up. class SExtLoadi16CVTf32Pat : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))), (SCVTFv1i32 (f32 (EXTRACT_SUBREG (SSHLLv4i16_shift (INSERT_SUBREG (f64 (IMPLICIT_DEF)), INST, hsub), 0), ssub)))>, Requires<[NotForCodeSize]>; def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), (LDURHi GPR64sp:$Rn, simm9:$offset)>; // 32-bits to 32-bits are handled in target specific dag combine: // performIntToFpCombine. // 64-bits integer to 32-bits floating point, not possible with // SCVTF on floating point registers (both source and destination // must have the same size). // Here are the patterns for 8, 16, 32, and 64-bits to double. // 8-bits -> double. 3 size step-up: give up. // 16-bits -> double. 2 size step. class SExtLoadi16CVTf64Pat : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))), (SCVTFv1i64 (f64 (EXTRACT_SUBREG (SSHLLv2i32_shift (f64 (EXTRACT_SUBREG (SSHLLv4i16_shift (INSERT_SUBREG (f64 (IMPLICIT_DEF)), INST, hsub), 0), dsub)), 0), dsub)))>, Requires<[NotForCodeSize, UseAlternateSExtLoadCVTF32]>; def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext), (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>; def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext), (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>; def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>; def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset), (LDURHi GPR64sp:$Rn, simm9:$offset)>; // 32-bits -> double. 1 size step-up. class SExtLoadi32CVTf64Pat : Pat <(f64 (sint_to_fp (i32 (load addrmode)))), (SCVTFv1i64 (f64 (EXTRACT_SUBREG (SSHLLv2i32_shift (INSERT_SUBREG (f64 (IMPLICIT_DEF)), INST, ssub), 0), dsub)))>, Requires<[NotForCodeSize]>; def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext), (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>; def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext), (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>; def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset), (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>; def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset), (LDURSi GPR64sp:$Rn, simm9:$offset)>; // 64-bits -> double are handled in target specific dag combine: // performIntToFpCombine. //---------------------------------------------------------------------------- // AdvSIMD Load-Store Structure //---------------------------------------------------------------------------- defm LD1 : SIMDLd1Multiple<"ld1">; defm LD2 : SIMDLd2Multiple<"ld2">; defm LD3 : SIMDLd3Multiple<"ld3">; defm LD4 : SIMDLd4Multiple<"ld4">; defm ST1 : SIMDSt1Multiple<"st1">; defm ST2 : SIMDSt2Multiple<"st2">; defm ST3 : SIMDSt3Multiple<"st3">; defm ST4 : SIMDSt4Multiple<"st4">; class Ld1Pat : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>; def : Ld1Pat; def : Ld1Pat; def : Ld1Pat; def : Ld1Pat; def : Ld1Pat; def : Ld1Pat; def : Ld1Pat; def : Ld1Pat; class St1Pat : Pat<(store ty:$Vt, GPR64sp:$Rn), (INST ty:$Vt, GPR64sp:$Rn)>; def : St1Pat; def : St1Pat; def : St1Pat; def : St1Pat; def : St1Pat; def : St1Pat; def : St1Pat; def : St1Pat; //--- // Single-element //--- defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>; defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>; defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>; defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>; let mayLoad = 1, hasSideEffects = 0 in { defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>; defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>; defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>; defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>; defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>; defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>; defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>; defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>; defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>; defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>; defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>; defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>; defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>; defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>; defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>; defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>; } def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), (LD1Rv8b GPR64sp:$Rn)>; def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))), (LD1Rv16b GPR64sp:$Rn)>; def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), (LD1Rv4h GPR64sp:$Rn)>; def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))), (LD1Rv8h GPR64sp:$Rn)>; def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), (LD1Rv2s GPR64sp:$Rn)>; def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))), (LD1Rv4s GPR64sp:$Rn)>; def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), (LD1Rv2d GPR64sp:$Rn)>; def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))), (LD1Rv1d GPR64sp:$Rn)>; // Grab the floating point version too def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), (LD1Rv2s GPR64sp:$Rn)>; def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))), (LD1Rv4s GPR64sp:$Rn)>; def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), (LD1Rv2d GPR64sp:$Rn)>; def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))), (LD1Rv1d GPR64sp:$Rn)>; def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), (LD1Rv4h GPR64sp:$Rn)>; def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))), (LD1Rv8h GPR64sp:$Rn)>; class Ld1Lane128Pat : Pat<(vector_insert (VTy VecListOne128:$Rd), (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>; def : Ld1Lane128Pat; def : Ld1Lane128Pat; def : Ld1Lane128Pat; def : Ld1Lane128Pat; def : Ld1Lane128Pat; def : Ld1Lane128Pat; def : Ld1Lane128Pat; class Ld1Lane64Pat : Pat<(vector_insert (VTy VecListOne64:$Rd), (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), (EXTRACT_SUBREG (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), VecIndex:$idx, GPR64sp:$Rn), dsub)>; def : Ld1Lane64Pat; def : Ld1Lane64Pat; def : Ld1Lane64Pat; def : Ld1Lane64Pat; def : Ld1Lane64Pat; defm LD1 : SIMDLdSt1SingleAliases<"ld1">; defm LD2 : SIMDLdSt2SingleAliases<"ld2">; defm LD3 : SIMDLdSt3SingleAliases<"ld3">; defm LD4 : SIMDLdSt4SingleAliases<"ld4">; // Stores defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>; defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>; defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>; defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>; let AddedComplexity = 19 in class St1Lane128Pat : Pat<(scalar_store (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), GPR64sp:$Rn), (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>; def : St1Lane128Pat; def : St1Lane128Pat; def : St1Lane128Pat; def : St1Lane128Pat; def : St1Lane128Pat; def : St1Lane128Pat; def : St1Lane128Pat; let AddedComplexity = 19 in class St1Lane64Pat : Pat<(scalar_store (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), GPR64sp:$Rn), (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), VecIndex:$idx, GPR64sp:$Rn)>; def : St1Lane64Pat; def : St1Lane64Pat; def : St1Lane64Pat; def : St1Lane64Pat; def : St1Lane64Pat; multiclass St1LanePost64Pat { def : Pat<(scalar_store (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), GPR64sp:$Rn, offset), (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), VecIndex:$idx, GPR64sp:$Rn, XZR)>; def : Pat<(scalar_store (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), GPR64sp:$Rn, GPR64:$Rm), (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), VecIndex:$idx, GPR64sp:$Rn, $Rm)>; } defm : St1LanePost64Pat; defm : St1LanePost64Pat; defm : St1LanePost64Pat; defm : St1LanePost64Pat; defm : St1LanePost64Pat; defm : St1LanePost64Pat; defm : St1LanePost64Pat; multiclass St1LanePost128Pat { def : Pat<(scalar_store (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), GPR64sp:$Rn, offset), (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>; def : Pat<(scalar_store (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)), GPR64sp:$Rn, GPR64:$Rm), (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>; } defm : St1LanePost128Pat; defm : St1LanePost128Pat; defm : St1LanePost128Pat; defm : St1LanePost128Pat; defm : St1LanePost128Pat; defm : St1LanePost128Pat; defm : St1LanePost128Pat; let mayStore = 1, hasSideEffects = 0 in { defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>; defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>; defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>; defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>; defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>; defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>; defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>; defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>; defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>; defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>; defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>; defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>; } defm ST1 : SIMDLdSt1SingleAliases<"st1">; defm ST2 : SIMDLdSt2SingleAliases<"st2">; defm ST3 : SIMDLdSt3SingleAliases<"st3">; defm ST4 : SIMDLdSt4SingleAliases<"st4">; //---------------------------------------------------------------------------- // Crypto extensions //---------------------------------------------------------------------------- let Predicates = [HasAES] in { def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>; def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>; def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>; def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; } // Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required // for AES fusion on some CPUs. let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, Sched<[WriteV]>; def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, Sched<[WriteV]>; } // Only use constrained versions of AES(I)MC instructions if they are paired with // AESE/AESD. def : Pat<(v16i8 (int_aarch64_crypto_aesmc (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1), (v16i8 V128:$src2))))), (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1), (v16i8 V128:$src2)))))>, Requires<[HasFuseAES]>; def : Pat<(v16i8 (int_aarch64_crypto_aesimc (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1), (v16i8 V128:$src2))))), (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1), (v16i8 V128:$src2)))))>, Requires<[HasFuseAES]>; let Predicates = [HasSHA2] in { def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>; def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>; def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>; def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>; def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>; def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>; def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>; def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>; def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>; def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>; } //---------------------------------------------------------------------------- // Compiler-pseudos //---------------------------------------------------------------------------- // FIXME: Like for X86, these should go in their own separate .td file. def def32 : PatLeaf<(i32 GPR32:$src), [{ return isDef32(*N); }]>; // In the case of a 32-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>; // For an anyext, we don't care what the high bits are, so we can perform an // INSERT_SUBREF into an IMPLICIT_DEF. def : Pat<(i64 (anyext GPR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and // then assert the extension has happened. def : Pat<(i64 (zext GPR32:$src)), (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; // To sign extend, we use a signed bitfield move instruction (SBFM) on the // containing super-reg. def : Pat<(i64 (sext GPR32:$src)), (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>; def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>; def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>; def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>; def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>; def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>; def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>; def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>; def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)), (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), (i64 (i32shift_sext_i8 imm0_31:$imm)))>; def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)), (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), (i64 (i64shift_sext_i8 imm0_63:$imm)))>; def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)), (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)), (i64 (i32shift_sext_i16 imm0_31:$imm)))>; def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)), (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)), (i64 (i64shift_sext_i16 imm0_63:$imm)))>; def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)), (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), (i64 (i64shift_a imm0_63:$imm)), (i64 (i64shift_sext_i32 imm0_63:$imm)))>; // sra patterns have an AddedComplexity of 10, so make sure we have a higher // AddedComplexity for the following patterns since we want to match sext + sra // patterns before we attempt to match a single sra node. let AddedComplexity = 20 in { // We support all sext + sra combinations which preserve at least one bit of the // original value which is to be sign extended. E.g. we support shifts up to // bitwidth-1 bits. def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)), (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>; def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)), (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>; def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)), (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>; def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)), (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>; def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)), (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32), (i64 imm0_31:$imm), 31)>; } // AddedComplexity = 20 // To truncate, we can simply extract from a subregister. def : Pat<(i32 (trunc GPR64sp:$src)), (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>; // __builtin_trap() uses the BRK instruction on AArch64. def : Pat<(trap), (BRK 1)>; // Conversions within AdvSIMD types in the same register size are free. // But because we need a consistent lane ordering, in big endian many // conversions require one or more REV instructions. // // Consider a simple memory load followed by a bitconvert then a store. // v0 = load v2i32 // v1 = BITCAST v2i32 v0 to v4i16 // store v4i16 v2 // // In big endian mode every memory access has an implicit byte swap. LDR and // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that // is, they treat the vector as a sequence of elements to be byte-swapped. // The two pairs of instructions are fundamentally incompatible. We've decided // to use LD1/ST1 only to simplify compiler implementation. // // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes // the original code sequence: // v0 = load v2i32 // v1 = REV v2i32 (implicit) // v2 = BITCAST v2i32 v1 to v4i16 // v3 = REV v4i16 v2 (implicit) // store v4i16 v3 // // But this is now broken - the value stored is different to the value loaded // due to lane reordering. To fix this, on every BITCAST we must perform two // other REVs: // v0 = load v2i32 // v1 = REV v2i32 (implicit) // v2 = REV v2i32 // v3 = BITCAST v2i32 v2 to v4i16 // v4 = REV v4i16 // v5 = REV v4i16 v4 (implicit) // store v4i16 v5 // // This means an extra two instructions, but actually in most cases the two REV // instructions can be combined into one. For example: // (REV64_2s (REV64_4h X)) === (REV32_4h X) // // There is also no 128-bit REV instruction. This must be synthesized with an // EXT instruction. // // Most bitconverts require some sort of conversion. The only exceptions are: // a) Identity conversions - vNfX <-> vNiX // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX // // Natural vector casts (64 bit) def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2f32 (AArch64NvCast (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; // Natural vector casts (128 bit) def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; } let Predicates = [IsBE] in { def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>; def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))), (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>; } def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>; def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))), (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>; def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))), (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>; def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>; def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))), (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>; def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), (COPY_TO_REGCLASS V64:$Vn, GPR64)>; let Predicates = [IsLE] in { def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 (REV64v2i32 FPR64:$src))>; def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 (REV64v4i16 FPR64:$src))>; def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 (REV64v8i8 FPR64:$src))>; def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 (REV64v4i16 FPR64:$src))>; def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 (REV64v2i32 FPR64:$src))>; } def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>; def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>; def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 (REV64v2i32 FPR64:$src))>; def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 (REV32v4i16 FPR64:$src))>; def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 (REV32v8i8 FPR64:$src))>; def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 (REV64v2i32 FPR64:$src))>; def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 (REV64v2i32 FPR64:$src))>; def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 (REV32v4i16 FPR64:$src))>; } def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>; def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 (REV64v4i16 FPR64:$src))>; def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 (REV32v4i16 FPR64:$src))>; def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 (REV16v8i8 FPR64:$src))>; def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 (REV64v4i16 FPR64:$src))>; def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 (REV32v4i16 FPR64:$src))>; def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 (REV64v4i16 FPR64:$src))>; } def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>; def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 (REV64v4i16 FPR64:$src))>; def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 (REV32v4i16 FPR64:$src))>; def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 (REV16v8i8 FPR64:$src))>; def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 (REV64v4i16 FPR64:$src))>; def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 (REV32v4i16 FPR64:$src))>; def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 (REV64v4i16 FPR64:$src))>; } def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>; def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 (REV64v8i8 FPR64:$src))>; def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 (REV32v8i8 FPR64:$src))>; def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 (REV16v8i8 FPR64:$src))>; def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 (REV64v8i8 FPR64:$src))>; def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 (REV32v8i8 FPR64:$src))>; def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 (REV64v8i8 FPR64:$src))>; def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 (REV16v8i8 FPR64:$src))>; } let Predicates = [IsLE] in { def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>; def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>; def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>; def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>; def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 (REV64v2i32 FPR64:$src))>; def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 (REV64v4i16 FPR64:$src))>; def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 (REV64v2i32 FPR64:$src))>; def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 (REV64v8i8 FPR64:$src))>; def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 (REV64v4i16 FPR64:$src))>; } def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>; def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 (REV64v2i32 FPR64:$src))>; def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 (REV64v4i16 FPR64:$src))>; def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 (REV64v8i8 FPR64:$src))>; def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 (REV64v2i32 FPR64:$src))>; def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 (REV64v4i16 FPR64:$src))>; } def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>; def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>; def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>; } let Predicates = [IsBE] in { def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 (REV64v2i32 FPR64:$src))>; def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 (REV32v4i16 FPR64:$src))>; def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 (REV32v8i8 FPR64:$src))>; def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 (REV64v2i32 FPR64:$src))>; def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 (REV64v2i32 FPR64:$src))>; def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 (REV32v4i16 FPR64:$src))>; } def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>; let Predicates = [IsLE] in { def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>; def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>; def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>; def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>; def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>; def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>; def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), (REV64v4i32 FPR128:$src), (i32 8)))>; def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), (REV64v8i16 FPR128:$src), (i32 8)))>; def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 (EXTv16i8 (REV64v8i16 FPR128:$src), (REV64v8i16 FPR128:$src), (i32 8)))>; def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 (EXTv16i8 (REV64v4i32 FPR128:$src), (REV64v4i32 FPR128:$src), (i32 8)))>; def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 (EXTv16i8 (REV64v16i8 FPR128:$src), (REV64v16i8 FPR128:$src), (i32 8)))>; } let Predicates = [IsLE] in { def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>; def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 (REV64v4i32 FPR128:$src))>; def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 (REV64v8i16 FPR128:$src))>; def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 (REV64v8i16 FPR128:$src))>; def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 (REV64v16i8 FPR128:$src))>; def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 (REV64v4i32 FPR128:$src))>; } def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>; def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src), (REV64v4i32 FPR128:$src), (i32 8)))>; def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 (REV32v8i16 FPR128:$src))>; def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 (REV32v8i16 FPR128:$src))>; def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 (REV32v16i8 FPR128:$src))>; def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 (REV64v4i32 FPR128:$src))>; def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 (REV64v4i32 FPR128:$src))>; } def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>; def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>; def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 (REV64v4i32 FPR128:$src))>; def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 (REV64v8i16 FPR128:$src))>; def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 (REV64v16i8 FPR128:$src))>; def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 (REV64v4i32 FPR128:$src))>; def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 (REV64v8i16 FPR128:$src))>; } def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>; def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src), (REV64v4i32 FPR128:$src), (i32 8)))>; def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 (REV64v4i32 FPR128:$src))>; def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 (REV32v8i16 FPR128:$src))>; def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 (REV32v16i8 FPR128:$src))>; def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 (REV64v4i32 FPR128:$src))>; def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 (REV32v8i16 FPR128:$src))>; } def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>; def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src), (REV64v8i16 FPR128:$src), (i32 8)))>; def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 (REV64v8i16 FPR128:$src))>; def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 (REV32v8i16 FPR128:$src))>; def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 (REV16v16i8 FPR128:$src))>; def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 (REV64v8i16 FPR128:$src))>; def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 (REV32v8i16 FPR128:$src))>; } def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>; def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src), (REV64v8i16 FPR128:$src), (i32 8)))>; def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 (REV64v8i16 FPR128:$src))>; def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 (REV32v8i16 FPR128:$src))>; def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 (REV16v16i8 FPR128:$src))>; def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 (REV64v8i16 FPR128:$src))>; def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 (REV32v8i16 FPR128:$src))>; } def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>; let Predicates = [IsLE] in { def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>; def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>; } let Predicates = [IsBE] in { def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src), (REV64v16i8 FPR128:$src), (i32 8)))>; def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 (REV64v16i8 FPR128:$src))>; def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 (REV32v16i8 FPR128:$src))>; def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 (REV16v16i8 FPR128:$src))>; def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 (REV64v16i8 FPR128:$src))>; def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 (REV32v16i8 FPR128:$src))>; def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 (REV16v16i8 FPR128:$src))>; } def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))), (EXTRACT_SUBREG V128:$Rn, dsub)>; def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))), (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))), (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))), (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))), (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>; // A 64-bit subvector insert to the first 128-bit vector position // is a subregister copy that needs no instruction. multiclass InsertSubvectorUndef { def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>; def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>; def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (Ty 0)), (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>; } defm : InsertSubvectorUndef; defm : InsertSubvectorUndef; // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64 // or v2f32. def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)), (vector_extract (v2i64 FPR128:$Rn), (i64 1)))), (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>; def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)), (vector_extract (v2f64 FPR128:$Rn), (i64 1)))), (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>; // vector_extract on 64-bit vectors gets promoted to a 128 bit vector, // so we match on v4f32 here, not v2f32. This will also catch adding // the low two lanes of a true v4f32 vector. def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)), (vector_extract (v4f32 FPR128:$Rn), (i64 1))), (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>; // Scalar 64-bit shifts in FPR64 registers. def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>; def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))), (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>; // Patterns for nontemporal/no-allocate stores. // We have to resort to tricks to turn a single-input store into a store pair, // because there is no single-input nontemporal store, only STNP. let Predicates = [IsLE] in { let AddedComplexity = 15 in { class NTStore128Pat : Pat<(nontemporalstore (VT FPR128:$Rt), (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)), (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub), (CPYi64 FPR128:$Rt, (i64 1)), GPR64sp:$Rn, simm7s8:$offset)>; def : NTStore128Pat; def : NTStore128Pat; def : NTStore128Pat; def : NTStore128Pat; class NTStore64Pat : Pat<(nontemporalstore (VT FPR64:$Rt), (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), GPR64sp:$Rn, simm7s4:$offset)>; // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? def : NTStore64Pat; def : NTStore64Pat; def : NTStore64Pat; def : NTStore64Pat; def : NTStore64Pat; def : Pat<(nontemporalstore GPR64:$Rt, (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 32, 63), sub_32), GPR64sp:$Rn, simm7s4:$offset)>; } // AddedComplexity=10 } // Predicates = [IsLE] // Tail call return handling. These are all compiler pseudo-instructions, // so no encoding information or anything like that. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff), []>, Sched<[WriteBrReg]>; def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>, Sched<[WriteBrReg]>; } def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)), (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>; def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)), (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>; include "AArch64InstrAtomics.td" include "AArch64SVEInstrInfo.td" capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64RegisterBanks.td000064400000000000000000000012630072674642500264510ustar 00000000000000//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// /// General Purpose Registers: W, X. def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; /// Floating Point/Vector Registers: B, H, S, D, Q. def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; /// Conditional register: NZCV. def CCRegBank : RegisterBank<"CC", [CCR]>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64RegisterInfo.td000064400000000000000000001435330072674642500263150ustar 00000000000000//=- AArch64RegisterInfo.td - Describe the AArch64 Registers -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// class AArch64Reg enc, string n, list subregs = [], list altNames = []> : Register { let HWEncoding = enc; let Namespace = "AArch64"; let SubRegs = subregs; } let Namespace = "AArch64" in { def sub_32 : SubRegIndex<32>; def bsub : SubRegIndex<8>; def hsub : SubRegIndex<16>; def ssub : SubRegIndex<32>; def dsub : SubRegIndex<32>; def sube32 : SubRegIndex<32>; def subo32 : SubRegIndex<32>; def qhisub : SubRegIndex<64>; def qsub : SubRegIndex<64>; def sube64 : SubRegIndex<64>; def subo64 : SubRegIndex<64>; // SVE def zsub : SubRegIndex<128>; // Note: zsub_hi should never be used directly because it represents // the scalable part of the SVE vector and cannot be manipulated as a // subvector in the same way the lower 128bits can. def zsub_hi : SubRegIndex<128>; // Note: Code depends on these having consecutive numbers def dsub0 : SubRegIndex<64>; def dsub1 : SubRegIndex<64>; def dsub2 : SubRegIndex<64>; def dsub3 : SubRegIndex<64>; // Note: Code depends on these having consecutive numbers def qsub0 : SubRegIndex<128>; def qsub1 : SubRegIndex<128>; def qsub2 : SubRegIndex<128>; def qsub3 : SubRegIndex<128>; } let Namespace = "AArch64" in { def vreg : RegAltNameIndex; def vlist1 : RegAltNameIndex; } //===----------------------------------------------------------------------===// // Registers //===----------------------------------------------------------------------===// def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>; def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>; def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>; def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>; def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>; def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>; def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>; def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>; def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>; def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>; def W10 : AArch64Reg<10, "w10">, DwarfRegNum<[10]>; def W11 : AArch64Reg<11, "w11">, DwarfRegNum<[11]>; def W12 : AArch64Reg<12, "w12">, DwarfRegNum<[12]>; def W13 : AArch64Reg<13, "w13">, DwarfRegNum<[13]>; def W14 : AArch64Reg<14, "w14">, DwarfRegNum<[14]>; def W15 : AArch64Reg<15, "w15">, DwarfRegNum<[15]>; def W16 : AArch64Reg<16, "w16">, DwarfRegNum<[16]>; def W17 : AArch64Reg<17, "w17">, DwarfRegNum<[17]>; def W18 : AArch64Reg<18, "w18">, DwarfRegNum<[18]>; def W19 : AArch64Reg<19, "w19">, DwarfRegNum<[19]>; def W20 : AArch64Reg<20, "w20">, DwarfRegNum<[20]>; def W21 : AArch64Reg<21, "w21">, DwarfRegNum<[21]>; def W22 : AArch64Reg<22, "w22">, DwarfRegNum<[22]>; def W23 : AArch64Reg<23, "w23">, DwarfRegNum<[23]>; def W24 : AArch64Reg<24, "w24">, DwarfRegNum<[24]>; def W25 : AArch64Reg<25, "w25">, DwarfRegNum<[25]>; def W26 : AArch64Reg<26, "w26">, DwarfRegNum<[26]>; def W27 : AArch64Reg<27, "w27">, DwarfRegNum<[27]>; def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>; def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>; def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>; def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>; def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias; let SubRegIndices = [sub_32] in { def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias; def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias; def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias; def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias; def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias; def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias; def X6 : AArch64Reg<6, "x6", [W6]>, DwarfRegAlias; def X7 : AArch64Reg<7, "x7", [W7]>, DwarfRegAlias; def X8 : AArch64Reg<8, "x8", [W8]>, DwarfRegAlias; def X9 : AArch64Reg<9, "x9", [W9]>, DwarfRegAlias; def X10 : AArch64Reg<10, "x10", [W10]>, DwarfRegAlias; def X11 : AArch64Reg<11, "x11", [W11]>, DwarfRegAlias; def X12 : AArch64Reg<12, "x12", [W12]>, DwarfRegAlias; def X13 : AArch64Reg<13, "x13", [W13]>, DwarfRegAlias; def X14 : AArch64Reg<14, "x14", [W14]>, DwarfRegAlias; def X15 : AArch64Reg<15, "x15", [W15]>, DwarfRegAlias; def X16 : AArch64Reg<16, "x16", [W16]>, DwarfRegAlias; def X17 : AArch64Reg<17, "x17", [W17]>, DwarfRegAlias; def X18 : AArch64Reg<18, "x18", [W18]>, DwarfRegAlias; def X19 : AArch64Reg<19, "x19", [W19]>, DwarfRegAlias; def X20 : AArch64Reg<20, "x20", [W20]>, DwarfRegAlias; def X21 : AArch64Reg<21, "x21", [W21]>, DwarfRegAlias; def X22 : AArch64Reg<22, "x22", [W22]>, DwarfRegAlias; def X23 : AArch64Reg<23, "x23", [W23]>, DwarfRegAlias; def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias; def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias; def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias; def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias; def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias; def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias; def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias; def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias; def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias; } // Condition code register. def NZCV : AArch64Reg<0, "nzcv">; // First fault status register def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>; // GPR register classes with the intersections of GPR32/GPR32sp and // GPR64/GPR64sp for use by the coalescer. def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> { let AltOrders = [(rotl GPR32common, 8)]; let AltOrderSelect = [{ return 1; }]; } def GPR64common : RegisterClass<"AArch64", [i64], 64, (add (sequence "X%u", 0, 28), FP, LR)> { let AltOrders = [(rotl GPR64common, 8)]; let AltOrderSelect = [{ return 1; }]; } // GPR register classes which exclude SP/WSP. def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> { let AltOrders = [(rotl GPR32, 8)]; let AltOrderSelect = [{ return 1; }]; } def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> { let AltOrders = [(rotl GPR64, 8)]; let AltOrderSelect = [{ return 1; }]; } // GPR register classes which include SP/WSP. def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> { let AltOrders = [(rotl GPR32sp, 8)]; let AltOrderSelect = [{ return 1; }]; } def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> { let AltOrders = [(rotl GPR64sp, 8)]; let AltOrderSelect = [{ return 1; }]; } def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>; def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>; def GPR64spPlus0Operand : AsmOperandClass { let Name = "GPR64sp0"; let RenderMethod = "addRegOperands"; let PredicateMethod = "isGPR64"; let ParserMethod = "tryParseGPR64sp0Operand"; } def GPR64sp0 : RegisterOperand { let ParserMatchClass = GPR64spPlus0Operand; } // GPR32/GPR64 but with zero-register substitution enabled. // TODO: Roll this out to GPR32/GPR64/GPR32all/GPR64all. def GPR32z : RegisterOperand { let GIZeroRegister = WZR; } def GPR64z : RegisterOperand { let GIZeroRegister = XZR; } // GPR register classes which include WZR/XZR AND SP/WSP. This is not a // constraint used by any instructions, it is used as a common super-class. def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>; def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>; // For tail calls, we can't use callee-saved registers, as they are restored // to the saved value before the tail call, which would clobber a call address. // This is for indirect tail calls to store the address of the destination. def tcGPR64 : RegisterClass<"AArch64", [i64], 64, (sub GPR64common, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, FP, LR)>; // GPR register classes for post increment amount of vector load/store that // has alternate printing when Rm=31 and prints a constant immediate value // equal to the total number of bytes transferred. // FIXME: TableGen *should* be able to do these itself now. There appears to be // a bug in counting how many operands a Post-indexed MCInst should have which // means the aliases don't trigger. def GPR64pi1 : RegisterOperand">; def GPR64pi2 : RegisterOperand">; def GPR64pi3 : RegisterOperand">; def GPR64pi4 : RegisterOperand">; def GPR64pi6 : RegisterOperand">; def GPR64pi8 : RegisterOperand">; def GPR64pi12 : RegisterOperand">; def GPR64pi16 : RegisterOperand">; def GPR64pi24 : RegisterOperand">; def GPR64pi32 : RegisterOperand">; def GPR64pi48 : RegisterOperand">; def GPR64pi64 : RegisterOperand">; // Condition code regclass. def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> { let CopyCost = -1; // Don't allow copying of status registers. // CCR is not allocatable. let isAllocatable = 0; } //===----------------------------------------------------------------------===// // Floating Point Scalar Registers //===----------------------------------------------------------------------===// def B0 : AArch64Reg<0, "b0">, DwarfRegNum<[64]>; def B1 : AArch64Reg<1, "b1">, DwarfRegNum<[65]>; def B2 : AArch64Reg<2, "b2">, DwarfRegNum<[66]>; def B3 : AArch64Reg<3, "b3">, DwarfRegNum<[67]>; def B4 : AArch64Reg<4, "b4">, DwarfRegNum<[68]>; def B5 : AArch64Reg<5, "b5">, DwarfRegNum<[69]>; def B6 : AArch64Reg<6, "b6">, DwarfRegNum<[70]>; def B7 : AArch64Reg<7, "b7">, DwarfRegNum<[71]>; def B8 : AArch64Reg<8, "b8">, DwarfRegNum<[72]>; def B9 : AArch64Reg<9, "b9">, DwarfRegNum<[73]>; def B10 : AArch64Reg<10, "b10">, DwarfRegNum<[74]>; def B11 : AArch64Reg<11, "b11">, DwarfRegNum<[75]>; def B12 : AArch64Reg<12, "b12">, DwarfRegNum<[76]>; def B13 : AArch64Reg<13, "b13">, DwarfRegNum<[77]>; def B14 : AArch64Reg<14, "b14">, DwarfRegNum<[78]>; def B15 : AArch64Reg<15, "b15">, DwarfRegNum<[79]>; def B16 : AArch64Reg<16, "b16">, DwarfRegNum<[80]>; def B17 : AArch64Reg<17, "b17">, DwarfRegNum<[81]>; def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>; def B19 : AArch64Reg<19, "b19">, DwarfRegNum<[83]>; def B20 : AArch64Reg<20, "b20">, DwarfRegNum<[84]>; def B21 : AArch64Reg<21, "b21">, DwarfRegNum<[85]>; def B22 : AArch64Reg<22, "b22">, DwarfRegNum<[86]>; def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>; def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>; def B25 : AArch64Reg<25, "b25">, DwarfRegNum<[89]>; def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>; def B27 : AArch64Reg<27, "b27">, DwarfRegNum<[91]>; def B28 : AArch64Reg<28, "b28">, DwarfRegNum<[92]>; def B29 : AArch64Reg<29, "b29">, DwarfRegNum<[93]>; def B30 : AArch64Reg<30, "b30">, DwarfRegNum<[94]>; def B31 : AArch64Reg<31, "b31">, DwarfRegNum<[95]>; let SubRegIndices = [bsub] in { def H0 : AArch64Reg<0, "h0", [B0]>, DwarfRegAlias; def H1 : AArch64Reg<1, "h1", [B1]>, DwarfRegAlias; def H2 : AArch64Reg<2, "h2", [B2]>, DwarfRegAlias; def H3 : AArch64Reg<3, "h3", [B3]>, DwarfRegAlias; def H4 : AArch64Reg<4, "h4", [B4]>, DwarfRegAlias; def H5 : AArch64Reg<5, "h5", [B5]>, DwarfRegAlias; def H6 : AArch64Reg<6, "h6", [B6]>, DwarfRegAlias; def H7 : AArch64Reg<7, "h7", [B7]>, DwarfRegAlias; def H8 : AArch64Reg<8, "h8", [B8]>, DwarfRegAlias; def H9 : AArch64Reg<9, "h9", [B9]>, DwarfRegAlias; def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias; def H11 : AArch64Reg<11, "h11", [B11]>, DwarfRegAlias; def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias; def H13 : AArch64Reg<13, "h13", [B13]>, DwarfRegAlias; def H14 : AArch64Reg<14, "h14", [B14]>, DwarfRegAlias; def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias; def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias; def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias; def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias; def H19 : AArch64Reg<19, "h19", [B19]>, DwarfRegAlias; def H20 : AArch64Reg<20, "h20", [B20]>, DwarfRegAlias; def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias; def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias; def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias; def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias; def H25 : AArch64Reg<25, "h25", [B25]>, DwarfRegAlias; def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias; def H27 : AArch64Reg<27, "h27", [B27]>, DwarfRegAlias; def H28 : AArch64Reg<28, "h28", [B28]>, DwarfRegAlias; def H29 : AArch64Reg<29, "h29", [B29]>, DwarfRegAlias; def H30 : AArch64Reg<30, "h30", [B30]>, DwarfRegAlias; def H31 : AArch64Reg<31, "h31", [B31]>, DwarfRegAlias; } let SubRegIndices = [hsub] in { def S0 : AArch64Reg<0, "s0", [H0]>, DwarfRegAlias; def S1 : AArch64Reg<1, "s1", [H1]>, DwarfRegAlias; def S2 : AArch64Reg<2, "s2", [H2]>, DwarfRegAlias; def S3 : AArch64Reg<3, "s3", [H3]>, DwarfRegAlias; def S4 : AArch64Reg<4, "s4", [H4]>, DwarfRegAlias; def S5 : AArch64Reg<5, "s5", [H5]>, DwarfRegAlias; def S6 : AArch64Reg<6, "s6", [H6]>, DwarfRegAlias; def S7 : AArch64Reg<7, "s7", [H7]>, DwarfRegAlias; def S8 : AArch64Reg<8, "s8", [H8]>, DwarfRegAlias; def S9 : AArch64Reg<9, "s9", [H9]>, DwarfRegAlias; def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias; def S11 : AArch64Reg<11, "s11", [H11]>, DwarfRegAlias; def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias; def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias; def S14 : AArch64Reg<14, "s14", [H14]>, DwarfRegAlias; def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias; def S16 : AArch64Reg<16, "s16", [H16]>, DwarfRegAlias; def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias; def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias; def S19 : AArch64Reg<19, "s19", [H19]>, DwarfRegAlias; def S20 : AArch64Reg<20, "s20", [H20]>, DwarfRegAlias; def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias; def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias; def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias; def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias; def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias; def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias; def S27 : AArch64Reg<27, "s27", [H27]>, DwarfRegAlias; def S28 : AArch64Reg<28, "s28", [H28]>, DwarfRegAlias; def S29 : AArch64Reg<29, "s29", [H29]>, DwarfRegAlias; def S30 : AArch64Reg<30, "s30", [H30]>, DwarfRegAlias; def S31 : AArch64Reg<31, "s31", [H31]>, DwarfRegAlias; } let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in { def D0 : AArch64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias; def D1 : AArch64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias; def D2 : AArch64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias; def D3 : AArch64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias; def D4 : AArch64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias; def D5 : AArch64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias; def D6 : AArch64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias; def D7 : AArch64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias; def D8 : AArch64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias; def D9 : AArch64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias; def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias; def D11 : AArch64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias; def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias; def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias; def D14 : AArch64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias; def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias; def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias; def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias; def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias; def D19 : AArch64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias; def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias; def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias; def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias; def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias; def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias; def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias; def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias; def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias; def D28 : AArch64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias; def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias; def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias; def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias; } let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in { def Q0 : AArch64Reg<0, "q0", [D0], ["v0", ""]>, DwarfRegAlias; def Q1 : AArch64Reg<1, "q1", [D1], ["v1", ""]>, DwarfRegAlias; def Q2 : AArch64Reg<2, "q2", [D2], ["v2", ""]>, DwarfRegAlias; def Q3 : AArch64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias; def Q4 : AArch64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias; def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias; def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias; def Q7 : AArch64Reg<7, "q7", [D7], ["v7", ""]>, DwarfRegAlias; def Q8 : AArch64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias; def Q9 : AArch64Reg<9, "q9", [D9], ["v9", ""]>, DwarfRegAlias; def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias; def Q11 : AArch64Reg<11, "q11", [D11], ["v11", ""]>, DwarfRegAlias; def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias; def Q13 : AArch64Reg<13, "q13", [D13], ["v13", ""]>, DwarfRegAlias; def Q14 : AArch64Reg<14, "q14", [D14], ["v14", ""]>, DwarfRegAlias; def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias; def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias; def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias; def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias; def Q19 : AArch64Reg<19, "q19", [D19], ["v19", ""]>, DwarfRegAlias; def Q20 : AArch64Reg<20, "q20", [D20], ["v20", ""]>, DwarfRegAlias; def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias; def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias; def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias; def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias; def Q25 : AArch64Reg<25, "q25", [D25], ["v25", ""]>, DwarfRegAlias; def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias; def Q27 : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias; def Q28 : AArch64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias; def Q29 : AArch64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias; def Q30 : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias; def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias; } def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> { let Size = 8; } def FPR16 : RegisterClass<"AArch64", [f16], 16, (sequence "H%u", 0, 31)> { let Size = 16; } def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>; def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32, v1i64, v4f16], 64, (sequence "D%u", 0, 31)>; // We don't (yet) have an f128 legal type, so don't use that here. We // normalize 128-bit vectors to v2f64 for arg passing and such, so use // that here. def FPR128 : RegisterClass<"AArch64", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128, v8f16], 128, (sequence "Q%u", 0, 31)>; // The lower 16 vector registers. Some instructions can only take registers // in this range. def FPR128_lo : RegisterClass<"AArch64", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128, (trunc FPR128, 16)>; // Pairs, triples, and quads of 64-bit vector registers. def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>; def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2], [(rotl FPR64, 0), (rotl FPR64, 1), (rotl FPR64, 2)]>; def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3], [(rotl FPR64, 0), (rotl FPR64, 1), (rotl FPR64, 2), (rotl FPR64, 3)]>; def DD : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> { let Size = 128; } def DDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> { let Size = 192; } def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> { let Size = 256; } // Pairs, triples, and quads of 128-bit vector registers. def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>; def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2], [(rotl FPR128, 0), (rotl FPR128, 1), (rotl FPR128, 2)]>; def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3], [(rotl FPR128, 0), (rotl FPR128, 1), (rotl FPR128, 2), (rotl FPR128, 3)]>; def QQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> { let Size = 256; } def QQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> { let Size = 384; } def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> { let Size = 512; } // Vector operand versions of the FP registers. Alternate name printing and // assmebler matching. def VectorReg64AsmOperand : AsmOperandClass { let Name = "VectorReg64"; let PredicateMethod = "isNeonVectorReg"; } def VectorReg128AsmOperand : AsmOperandClass { let Name = "VectorReg128"; let PredicateMethod = "isNeonVectorReg"; } def V64 : RegisterOperand { let ParserMatchClass = VectorReg64AsmOperand; } def V128 : RegisterOperand { let ParserMatchClass = VectorReg128AsmOperand; } def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; let PredicateMethod = "isNeonVectorRegLo"; } def V128_lo : RegisterOperand { let ParserMatchClass = VectorRegLoAsmOperand; } class TypedVecListAsmOperand : AsmOperandClass { let Name = "TypedVectorList" # count # "_" # lanes # eltsize; let PredicateMethod = "isTypedVectorList"; let RenderMethod = "addVectorListOperands<" # vecty # ", " # count # ">"; } class TypedVecListRegOperand : RegisterOperand">; multiclass VectorList { // With implicit types (probably on instruction instead). E.g. { v0, v1 } def _64AsmOperand : AsmOperandClass { let Name = NAME # "64"; let PredicateMethod = "isImplicitlyTypedVectorList"; let RenderMethod = "addVectorListOperands"; } def "64" : RegisterOperand { let ParserMatchClass = !cast(NAME # "_64AsmOperand"); } def _128AsmOperand : AsmOperandClass { let Name = NAME # "128"; let PredicateMethod = "isImplicitlyTypedVectorList"; let RenderMethod = "addVectorListOperands"; } def "128" : RegisterOperand { let ParserMatchClass = !cast(NAME # "_128AsmOperand"); } // 64-bit register lists with explicit type. // { v0.8b, v1.8b } def _8bAsmOperand : TypedVecListAsmOperand; def "8b" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_8bAsmOperand"); } // { v0.4h, v1.4h } def _4hAsmOperand : TypedVecListAsmOperand; def "4h" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_4hAsmOperand"); } // { v0.2s, v1.2s } def _2sAsmOperand : TypedVecListAsmOperand; def "2s" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_2sAsmOperand"); } // { v0.1d, v1.1d } def _1dAsmOperand : TypedVecListAsmOperand; def "1d" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_1dAsmOperand"); } // 128-bit register lists with explicit type // { v0.16b, v1.16b } def _16bAsmOperand : TypedVecListAsmOperand; def "16b" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_16bAsmOperand"); } // { v0.8h, v1.8h } def _8hAsmOperand : TypedVecListAsmOperand; def "8h" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_8hAsmOperand"); } // { v0.4s, v1.4s } def _4sAsmOperand : TypedVecListAsmOperand; def "4s" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_4sAsmOperand"); } // { v0.2d, v1.2d } def _2dAsmOperand : TypedVecListAsmOperand; def "2d" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_2dAsmOperand"); } // { v0.b, v1.b } def _bAsmOperand : TypedVecListAsmOperand; def "b" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_bAsmOperand"); } // { v0.h, v1.h } def _hAsmOperand : TypedVecListAsmOperand; def "h" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_hAsmOperand"); } // { v0.s, v1.s } def _sAsmOperand : TypedVecListAsmOperand; def "s" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_sAsmOperand"); } // { v0.d, v1.d } def _dAsmOperand : TypedVecListAsmOperand; def "d" : TypedVecListRegOperand { let ParserMatchClass = !cast(NAME # "_dAsmOperand"); } } defm VecListOne : VectorList<1, FPR64, FPR128>; defm VecListTwo : VectorList<2, DD, QQ>; defm VecListThree : VectorList<3, DDD, QQQ>; defm VecListFour : VectorList<4, DDDD, QQQQ>; class FPRAsmOperand : AsmOperandClass { let Name = "FPRAsmOperand" # RC; let PredicateMethod = "isGPR64"; let RenderMethod = "addRegOperands"; } // Register operand versions of the scalar FP registers. def FPR8Op : RegisterOperand { let ParserMatchClass = FPRAsmOperand<"FPR8">; } def FPR16Op : RegisterOperand { let ParserMatchClass = FPRAsmOperand<"FPR16">; } def FPR32Op : RegisterOperand { let ParserMatchClass = FPRAsmOperand<"FPR32">; } def FPR64Op : RegisterOperand { let ParserMatchClass = FPRAsmOperand<"FPR64">; } def FPR128Op : RegisterOperand { let ParserMatchClass = FPRAsmOperand<"FPR128">; } //===----------------------------------------------------------------------===// // ARMv8.1a atomic CASP register operands def WSeqPairs : RegisterTuples<[sube32, subo32], [(rotl GPR32, 0), (rotl GPR32, 1)]>; def XSeqPairs : RegisterTuples<[sube64, subo64], [(rotl GPR64, 0), (rotl GPR64, 1)]>; def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32, (add WSeqPairs)>{ let Size = 64; } def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64, (add XSeqPairs)>{ let Size = 128; } let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in { def WSeqPairsAsmOperandClass : AsmOperandClass { let Name = "WSeqPair"; } def XSeqPairsAsmOperandClass : AsmOperandClass { let Name = "XSeqPair"; } } def WSeqPairClassOperand : RegisterOperand"> { let ParserMatchClass = WSeqPairsAsmOperandClass; } def XSeqPairClassOperand : RegisterOperand"> { let ParserMatchClass = XSeqPairsAsmOperandClass; } //===----- END: v8.1a atomic CASP register operands -----------------------===// // SVE predicate registers def P0 : AArch64Reg<0, "p0">, DwarfRegNum<[48]>; def P1 : AArch64Reg<1, "p1">, DwarfRegNum<[49]>; def P2 : AArch64Reg<2, "p2">, DwarfRegNum<[50]>; def P3 : AArch64Reg<3, "p3">, DwarfRegNum<[51]>; def P4 : AArch64Reg<4, "p4">, DwarfRegNum<[52]>; def P5 : AArch64Reg<5, "p5">, DwarfRegNum<[53]>; def P6 : AArch64Reg<6, "p6">, DwarfRegNum<[54]>; def P7 : AArch64Reg<7, "p7">, DwarfRegNum<[55]>; def P8 : AArch64Reg<8, "p8">, DwarfRegNum<[56]>; def P9 : AArch64Reg<9, "p9">, DwarfRegNum<[57]>; def P10 : AArch64Reg<10, "p10">, DwarfRegNum<[58]>; def P11 : AArch64Reg<11, "p11">, DwarfRegNum<[59]>; def P12 : AArch64Reg<12, "p12">, DwarfRegNum<[60]>; def P13 : AArch64Reg<13, "p13">, DwarfRegNum<[61]>; def P14 : AArch64Reg<14, "p14">, DwarfRegNum<[62]>; def P15 : AArch64Reg<15, "p15">, DwarfRegNum<[63]>; // The part of SVE registers that don't overlap Neon registers. // These are only used as part of clobber lists. def Z0_HI : AArch64Reg<0, "z0_hi">; def Z1_HI : AArch64Reg<1, "z1_hi">; def Z2_HI : AArch64Reg<2, "z2_hi">; def Z3_HI : AArch64Reg<3, "z3_hi">; def Z4_HI : AArch64Reg<4, "z4_hi">; def Z5_HI : AArch64Reg<5, "z5_hi">; def Z6_HI : AArch64Reg<6, "z6_hi">; def Z7_HI : AArch64Reg<7, "z7_hi">; def Z8_HI : AArch64Reg<8, "z8_hi">; def Z9_HI : AArch64Reg<9, "z9_hi">; def Z10_HI : AArch64Reg<10, "z10_hi">; def Z11_HI : AArch64Reg<11, "z11_hi">; def Z12_HI : AArch64Reg<12, "z12_hi">; def Z13_HI : AArch64Reg<13, "z13_hi">; def Z14_HI : AArch64Reg<14, "z14_hi">; def Z15_HI : AArch64Reg<15, "z15_hi">; def Z16_HI : AArch64Reg<16, "z16_hi">; def Z17_HI : AArch64Reg<17, "z17_hi">; def Z18_HI : AArch64Reg<18, "z18_hi">; def Z19_HI : AArch64Reg<19, "z19_hi">; def Z20_HI : AArch64Reg<20, "z20_hi">; def Z21_HI : AArch64Reg<21, "z21_hi">; def Z22_HI : AArch64Reg<22, "z22_hi">; def Z23_HI : AArch64Reg<23, "z23_hi">; def Z24_HI : AArch64Reg<24, "z24_hi">; def Z25_HI : AArch64Reg<25, "z25_hi">; def Z26_HI : AArch64Reg<26, "z26_hi">; def Z27_HI : AArch64Reg<27, "z27_hi">; def Z28_HI : AArch64Reg<28, "z28_hi">; def Z29_HI : AArch64Reg<29, "z29_hi">; def Z30_HI : AArch64Reg<30, "z30_hi">; def Z31_HI : AArch64Reg<31, "z31_hi">; // SVE variable-size vector registers let SubRegIndices = [zsub,zsub_hi] in { def Z0 : AArch64Reg<0, "z0", [Q0, Z0_HI]>, DwarfRegNum<[96]>; def Z1 : AArch64Reg<1, "z1", [Q1, Z1_HI]>, DwarfRegNum<[97]>; def Z2 : AArch64Reg<2, "z2", [Q2, Z2_HI]>, DwarfRegNum<[98]>; def Z3 : AArch64Reg<3, "z3", [Q3, Z3_HI]>, DwarfRegNum<[99]>; def Z4 : AArch64Reg<4, "z4", [Q4, Z4_HI]>, DwarfRegNum<[100]>; def Z5 : AArch64Reg<5, "z5", [Q5, Z5_HI]>, DwarfRegNum<[101]>; def Z6 : AArch64Reg<6, "z6", [Q6, Z6_HI]>, DwarfRegNum<[102]>; def Z7 : AArch64Reg<7, "z7", [Q7, Z7_HI]>, DwarfRegNum<[103]>; def Z8 : AArch64Reg<8, "z8", [Q8, Z8_HI]>, DwarfRegNum<[104]>; def Z9 : AArch64Reg<9, "z9", [Q9, Z9_HI]>, DwarfRegNum<[105]>; def Z10 : AArch64Reg<10, "z10", [Q10, Z10_HI]>, DwarfRegNum<[106]>; def Z11 : AArch64Reg<11, "z11", [Q11, Z11_HI]>, DwarfRegNum<[107]>; def Z12 : AArch64Reg<12, "z12", [Q12, Z12_HI]>, DwarfRegNum<[108]>; def Z13 : AArch64Reg<13, "z13", [Q13, Z13_HI]>, DwarfRegNum<[109]>; def Z14 : AArch64Reg<14, "z14", [Q14, Z14_HI]>, DwarfRegNum<[110]>; def Z15 : AArch64Reg<15, "z15", [Q15, Z15_HI]>, DwarfRegNum<[111]>; def Z16 : AArch64Reg<16, "z16", [Q16, Z16_HI]>, DwarfRegNum<[112]>; def Z17 : AArch64Reg<17, "z17", [Q17, Z17_HI]>, DwarfRegNum<[113]>; def Z18 : AArch64Reg<18, "z18", [Q18, Z18_HI]>, DwarfRegNum<[114]>; def Z19 : AArch64Reg<19, "z19", [Q19, Z19_HI]>, DwarfRegNum<[115]>; def Z20 : AArch64Reg<20, "z20", [Q20, Z20_HI]>, DwarfRegNum<[116]>; def Z21 : AArch64Reg<21, "z21", [Q21, Z21_HI]>, DwarfRegNum<[117]>; def Z22 : AArch64Reg<22, "z22", [Q22, Z22_HI]>, DwarfRegNum<[118]>; def Z23 : AArch64Reg<23, "z23", [Q23, Z23_HI]>, DwarfRegNum<[119]>; def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>; def Z25 : AArch64Reg<25, "z25", [Q25, Z25_HI]>, DwarfRegNum<[121]>; def Z26 : AArch64Reg<26, "z26", [Q26, Z26_HI]>, DwarfRegNum<[122]>; def Z27 : AArch64Reg<27, "z27", [Q27, Z27_HI]>, DwarfRegNum<[123]>; def Z28 : AArch64Reg<28, "z28", [Q28, Z28_HI]>, DwarfRegNum<[124]>; def Z29 : AArch64Reg<29, "z29", [Q29, Z29_HI]>, DwarfRegNum<[125]>; def Z30 : AArch64Reg<30, "z30", [Q30, Z30_HI]>, DwarfRegNum<[126]>; def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>; } // Enum descibing the element size for destructive // operations. class ElementSizeEnum val> { bits<3> Value = val; } def ElementSizeNone : ElementSizeEnum<0>; def ElementSizeB : ElementSizeEnum<1>; def ElementSizeH : ElementSizeEnum<2>; def ElementSizeS : ElementSizeEnum<3>; def ElementSizeD : ElementSizeEnum<4>; def ElementSizeQ : ElementSizeEnum<5>; // Unused class SVERegOp : RegisterOperand { ElementSizeEnum ElementSize; let ElementSize = Size; let PrintMethod = !if(!eq(Suffix, ""), "printSVERegOp<>", "printSVERegOp<'" # Suffix # "'>"); let ParserMatchClass = C; } class PPRRegOp : SVERegOp {} class ZPRRegOp : SVERegOp {} //****************************************************************************** // SVE predicate register classes. class PPRClass : RegisterClass< "AArch64", [ nxv16i1, nxv8i1, nxv4i1, nxv2i1 ], 16, (sequence "P%u", 0, lastreg)> { let Size = 16; } def PPR : PPRClass<15>; def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class. class PPRAsmOperand : AsmOperandClass { let Name = "SVE" # name # "Reg"; let PredicateMethod = "isSVEPredicateVectorRegOfWidth<" # Width # ", " # "AArch64::" # RegClass # "RegClassID>"; let DiagnosticType = "InvalidSVE" # name # "Reg"; let RenderMethod = "addRegOperands"; let ParserMethod = "tryParseSVEPredicateVector"; } def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>; def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>; def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>; def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>; def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>; def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>; def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>; def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>; def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>; def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>; def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b", 0>; def PPRAsmOp3b8 : PPRAsmOperand<"Predicate3bB", "PPR_3b", 8>; def PPRAsmOp3b16 : PPRAsmOperand<"Predicate3bH", "PPR_3b", 16>; def PPRAsmOp3b32 : PPRAsmOperand<"Predicate3bS", "PPR_3b", 32>; def PPRAsmOp3b64 : PPRAsmOperand<"Predicate3bD", "PPR_3b", 64>; def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, ElementSizeNone, PPR_3b>; def PPR3b8 : PPRRegOp<"b", PPRAsmOp3b8, ElementSizeB, PPR_3b>; def PPR3b16 : PPRRegOp<"h", PPRAsmOp3b16, ElementSizeH, PPR_3b>; def PPR3b32 : PPRRegOp<"s", PPRAsmOp3b32, ElementSizeS, PPR_3b>; def PPR3b64 : PPRRegOp<"d", PPRAsmOp3b64, ElementSizeD, PPR_3b>; //****************************************************************************** // SVE vector register class def ZPR : RegisterClass<"AArch64", [nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, nxv1f32, nxv2f32, nxv4f32, nxv1f64, nxv2f64], 128, (sequence "Z%u", 0, 31)> { let Size = 128; } // SVE restricted 4 bit scalable vector register class def ZPR_4b : RegisterClass<"AArch64", [nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, nxv1f32, nxv2f32, nxv4f32, nxv1f64, nxv2f64], 128, (sequence "Z%u", 0, 15)> { let Size = 128; } // SVE restricted 3 bit scalable vector register class def ZPR_3b : RegisterClass<"AArch64", [nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16, nxv1f32, nxv2f32, nxv4f32, nxv1f64, nxv2f64], 128, (sequence "Z%u", 0, 7)> { let Size = 128; } class ZPRAsmOperand : AsmOperandClass { let Name = "SVE" # name # "Reg"; let PredicateMethod = "isSVEDataVectorRegOfWidth<" # Width # ", AArch64::ZPR" # RegClassSuffix # "RegClassID>"; let RenderMethod = "addRegOperands"; let DiagnosticType = "InvalidZPR" # RegClassSuffix # Width; let ParserMethod = "tryParseSVEDataVector"; } def ZPRAsmOpAny : ZPRAsmOperand<"VectorAny", 0>; def ZPRAsmOp8 : ZPRAsmOperand<"VectorB", 8>; def ZPRAsmOp16 : ZPRAsmOperand<"VectorH", 16>; def ZPRAsmOp32 : ZPRAsmOperand<"VectorS", 32>; def ZPRAsmOp64 : ZPRAsmOperand<"VectorD", 64>; def ZPRAsmOp128 : ZPRAsmOperand<"VectorQ", 128>; def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ElementSizeNone, ZPR>; def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ElementSizeB, ZPR>; def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ElementSizeH, ZPR>; def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ElementSizeS, ZPR>; def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ElementSizeD, ZPR>; def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>; def ZPRAsmOp3b8 : ZPRAsmOperand<"Vector3bB", 8, "_3b">; def ZPRAsmOp3b16 : ZPRAsmOperand<"Vector3bH", 16, "_3b">; def ZPRAsmOp3b32 : ZPRAsmOperand<"Vector3bS", 32, "_3b">; def ZPR3b8 : ZPRRegOp<"b", ZPRAsmOp3b8, ElementSizeB, ZPR_3b>; def ZPR3b16 : ZPRRegOp<"h", ZPRAsmOp3b16, ElementSizeH, ZPR_3b>; def ZPR3b32 : ZPRRegOp<"s", ZPRAsmOp3b32, ElementSizeS, ZPR_3b>; def ZPRAsmOp4b16 : ZPRAsmOperand<"Vector4bH", 16, "_4b">; def ZPRAsmOp4b32 : ZPRAsmOperand<"Vector4bS", 32, "_4b">; def ZPRAsmOp4b64 : ZPRAsmOperand<"Vector4bD", 64, "_4b">; def ZPR4b16 : ZPRRegOp<"h", ZPRAsmOp4b16, ElementSizeH, ZPR_4b>; def ZPR4b32 : ZPRRegOp<"s", ZPRAsmOp4b32, ElementSizeS, ZPR_4b>; def ZPR4b64 : ZPRRegOp<"d", ZPRAsmOp4b64, ElementSizeD, ZPR_4b>; class FPRasZPR : AsmOperandClass{ let Name = "FPR" # Width # "asZPR"; let PredicateMethod = "isFPRasZPR"; let RenderMethod = "addFPRasZPRRegOperands<" # Width # ">"; } class FPRasZPROperand : RegisterOperand { let ParserMatchClass = FPRasZPR; let PrintMethod = "printZPRasFPR<" # Width # ">"; } def FPR8asZPR : FPRasZPROperand<8>; def FPR16asZPR : FPRasZPROperand<16>; def FPR32asZPR : FPRasZPROperand<32>; def FPR64asZPR : FPRasZPROperand<64>; def FPR128asZPR : FPRasZPROperand<128>; let Namespace = "AArch64" in { def zsub0 : SubRegIndex<128, -1>; def zsub1 : SubRegIndex<128, -1>; def zsub2 : SubRegIndex<128, -1>; def zsub3 : SubRegIndex<128, -1>; } // Pairs, triples, and quads of SVE vector registers. def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>; def ZSeqTriples : RegisterTuples<[zsub0, zsub1, zsub2], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2)]>; def ZSeqQuads : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2), (rotl ZPR, 3)]>; def ZPR2 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqPairs)> { let Size = 256; } def ZPR3 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqTriples)> { let Size = 384; } def ZPR4 : RegisterClass<"AArch64", [untyped], 128, (add ZSeqQuads)> { let Size = 512; } class ZPRVectorList : AsmOperandClass { let Name = "SVEVectorList" # NumRegs # ElementWidth; let ParserMethod = "tryParseVectorList"; let PredicateMethod = "isTypedVectorList"; let RenderMethod = "addVectorListOperands"; } def Z_b : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<8, 1>; } def Z_h : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<16, 1>; } def Z_s : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<32, 1>; } def Z_d : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<64, 1>; } def ZZ_b : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<8, 2>; } def ZZ_h : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<16, 2>; } def ZZ_s : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<32, 2>; } def ZZ_d : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<64, 2>; } def ZZZ_b : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<8, 3>; } def ZZZ_h : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<16, 3>; } def ZZZ_s : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<32, 3>; } def ZZZ_d : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<64, 3>; } def ZZZZ_b : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<8, 4>; } def ZZZZ_h : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<16, 4>; } def ZZZZ_s : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<32, 4>; } def ZZZZ_d : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<64, 4>; } class ZPRExtendAsmOperand : AsmOperandClass { let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale # !if(ScaleAlwaysSame, "Only", ""); let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<" # RegWidth # ", AArch64::ZPRRegClassID, " # "AArch64_AM::" # ShiftExtend # ", " # Scale # ", " # !if(ScaleAlwaysSame, "true", "false") # ">"; let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale; let RenderMethod = "addRegOperands"; let ParserMethod = "tryParseSVEDataVector"; } class ZPRExtendRegisterOperand : RegisterOperand { let ParserMatchClass = !cast("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix); let PrintMethod = "printRegWithShiftExtend<" # !if(SignExtend, "true", "false") # ", " # Scale # ", " # !if(IsLSL, "'x'", "'w'") # ", " # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">"; } foreach RegWidth = [32, 64] in { // UXTW(8|16|32|64) def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>; def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>; def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>; def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>; def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>; def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "Only">; def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>; def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>; def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>; def ZPR#RegWidth#ExtUXTW64 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>; // SXTW(8|16|32|64) def ZPR#RegWidth#AsmOpndExtSXTW8Only : ZPRExtendAsmOperand<"SXTW", RegWidth, 8, 0b1>; def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>; def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>; def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>; def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>; def ZPR#RegWidth#ExtSXTW8Only : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8, "Only">; def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>; def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>; def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>; def ZPR#RegWidth#ExtSXTW64 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 64>; // LSL(8|16|32|64) def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>; def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>; def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>; def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>; def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>; def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>; def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>; def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>; } class GPR64ShiftExtendAsmOperand : AsmOperandClass { let Name = AsmOperandName # Scale; let PredicateMethod = "isGPR64WithShiftExtend"; let DiagnosticType = "Invalid" # AsmOperandName # Scale; let RenderMethod = "addRegOperands"; let ParserMethod = "tryParseGPROperand"; } class GPR64ExtendRegisterOperand : RegisterOperand{ let ParserMatchClass = !cast(Name); let PrintMethod = "printRegWithShiftExtend"; } foreach Scale = [8, 16, 32, 64] in { def GPR64shiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64shifted", Scale, "GPR64">; def GPR64shifted # Scale : GPR64ExtendRegisterOperand<"GPR64shiftedAsmOpnd" # Scale, Scale, GPR64>; def GPR64NoXZRshiftedAsmOpnd # Scale : GPR64ShiftExtendAsmOperand<"GPR64NoXZRshifted", Scale, "GPR64common">; def GPR64NoXZRshifted # Scale : GPR64ExtendRegisterOperand<"GPR64NoXZRshiftedAsmOpnd" # Scale, Scale, GPR64common>; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SVEInstrInfo.td000064400000000000000000001641400072674642500262030ustar 00000000000000//=- AArch64SVEInstrInfo.td - AArch64 SVE Instructions -*- tablegen -*-----=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // AArch64 Scalable Vector Extension (SVE) Instruction definitions. // //===----------------------------------------------------------------------===// let Predicates = [HasSVE] in { def RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr">; def RDFFRS_PPz : sve_int_rdffr_pred<0b1, "rdffrs">; def RDFFR_P : sve_int_rdffr_unpred<"rdffr">; def SETFFR : sve_int_setffr<"setffr">; def WRFFR : sve_int_wrffr<"wrffr">; defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">; defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">; defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">; defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">; def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">; def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">; def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">; def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">; defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">; defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">; defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">; defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">; defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">; defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; defm SUBR_ZI : sve_int_arith_imm0<0b011, "subr">; defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">; defm UQADD_ZI : sve_int_arith_imm0<0b101, "uqadd">; defm SQSUB_ZI : sve_int_arith_imm0<0b110, "sqsub">; defm UQSUB_ZI : sve_int_arith_imm0<0b111, "uqsub">; defm MAD_ZPmZZ : sve_int_mladdsub_vvv_pred<0b0, "mad">; defm MSB_ZPmZZ : sve_int_mladdsub_vvv_pred<0b1, "msb">; defm MLA_ZPmZZ : sve_int_mlas_vvv_pred<0b0, "mla">; defm MLS_ZPmZZ : sve_int_mlas_vvv_pred<0b1, "mls">; // SVE predicated integer reductions. defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv">; defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv">; defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv">; defm UMAXV_VPZ : sve_int_reduce_1<0b001, "umaxv">; defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv">; defm UMINV_VPZ : sve_int_reduce_1<0b011, "uminv">; defm ORV_VPZ : sve_int_reduce_2<0b000, "orv">; defm EORV_VPZ : sve_int_reduce_2<0b001, "eorv">; defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv">; defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">; defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">; defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; defm SMAX_ZI : sve_int_arith_imm1<0b00, "smax", simm8>; defm SMIN_ZI : sve_int_arith_imm1<0b10, "smin", simm8>; defm UMAX_ZI : sve_int_arith_imm1<0b01, "umax", imm0_255>; defm UMIN_ZI : sve_int_arith_imm1<0b11, "umin", imm0_255>; defm MUL_ZI : sve_int_arith_imm2<"mul">; defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul">; defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">; defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh">; defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">; defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv">; defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">; defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">; defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot">; defm UDOT_ZZZ : sve_intx_dot<0b1, "udot">; defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot">; defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot">; defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb">; defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb">; defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">; defm UXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b011, "uxth">; defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw">; defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw">; defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs">; defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg">; defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls">; defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz">; defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt">; defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot">; defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not">; defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">; defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">; defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">; defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">; defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">; defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin">; defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">; defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">; defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe">; defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">; defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>; defm FSUB_ZPmI : sve_fp_2op_i_p_zds<0b001, "fsub", sve_fpimm_half_one>; defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>; defm FSUBR_ZPmI : sve_fp_2op_i_p_zds<0b011, "fsubr", sve_fpimm_half_one>; defm FMAXNM_ZPmI : sve_fp_2op_i_p_zds<0b100, "fmaxnm", sve_fpimm_zero_one>; defm FMINNM_ZPmI : sve_fp_2op_i_p_zds<0b101, "fminnm", sve_fpimm_zero_one>; defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>; defm FMIN_ZPmI : sve_fp_2op_i_p_zds<0b111, "fmin", sve_fpimm_zero_one>; defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd">; defm FSUB_ZPmZ : sve_fp_2op_p_zds<0b0001, "fsub">; defm FMUL_ZPmZ : sve_fp_2op_p_zds<0b0010, "fmul">; defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr">; defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">; defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm">; defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax">; defm FMIN_ZPmZ : sve_fp_2op_p_zds<0b0111, "fmin">; defm FABD_ZPmZ : sve_fp_2op_p_zds<0b1000, "fabd">; defm FSCALE_ZPmZ : sve_fp_2op_p_zds<0b1001, "fscale">; defm FMULX_ZPmZ : sve_fp_2op_p_zds<0b1010, "fmulx">; defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">; defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">; defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd">; defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub">; defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul">; defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul">; defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">; defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">; defm FTSSEL_ZZZ : sve_int_bin_cons_misc_0_b<"ftssel">; defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; defm FMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, "fmla">; defm FMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b01, "fmls">; defm FNMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b10, "fnmla">; defm FNMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b11, "fnmls">; defm FMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b00, "fmad">; defm FMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b01, "fmsb">; defm FNMAD_ZPmZZ : sve_fp_3op_p_zds_b<0b10, "fnmad">; defm FNMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b11, "fnmsb">; defm FTMAD_ZZI : sve_fp_ftmad<"ftmad">; defm FMLA_ZZZI : sve_fp_fma_by_indexed_elem<0b0, "fmla">; defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b1, "fmls">; defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla">; defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul">; // SVE floating point reductions. defm FADDA_VPZ : sve_fp_2op_p_vd<0b000, "fadda">; defm FADDV_VPZ : sve_fp_fast_red<0b000, "faddv">; defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv">; defm FMINNMV_VPZ : sve_fp_fast_red<0b101, "fminnmv">; defm FMAXV_VPZ : sve_fp_fast_red<0b110, "fmaxv">; defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv">; // Splat immediate (unpredicated) defm DUP_ZI : sve_int_dup_imm<"dup">; defm FDUP_ZI : sve_int_dup_fpimm<"fdup">; defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">; // Splat immediate (predicated) defm CPY_ZPmI : sve_int_dup_imm_pred_merge<"cpy">; defm CPY_ZPzI : sve_int_dup_imm_pred_zero<"cpy">; defm FCPY_ZPmI : sve_int_dup_fpimm_pred<"fcpy">; // Splat scalar register (unpredicated, GPR or vector + element index) defm DUP_ZR : sve_int_perm_dup_r<"dup">; defm DUP_ZZI : sve_int_perm_dup_i<"dup">; // Splat scalar register (predicated) defm CPY_ZPmR : sve_int_perm_cpy_r<"cpy">; defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">; // Select elements from either vector (predicated) defm SEL_ZPZZ : sve_int_sel_vvv<"sel">; defm SPLICE_ZPZ : sve_int_perm_splice<"splice">; defm COMPACT_ZPZ : sve_int_perm_compact<"compact">; defm INSR_ZR : sve_int_perm_insrs<"insr">; defm INSR_ZV : sve_int_perm_insrv<"insr">; def EXT_ZZI : sve_int_perm_extract_i<"ext">; defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit">; defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb">; defm REVH_ZPmZ : sve_int_perm_rev_revh<"revh">; defm REVW_ZPmZ : sve_int_perm_rev_revw<"revw">; defm REV_PP : sve_int_perm_reverse_p<"rev">; defm REV_ZZ : sve_int_perm_reverse_z<"rev">; defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo">; defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi">; defm UUNPKLO_ZZ : sve_int_perm_unpk<0b10, "uunpklo">; defm UUNPKHI_ZZ : sve_int_perm_unpk<0b11, "uunpkhi">; def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">; def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">; defm MOVPRFX_ZPzZ : sve_int_movprfx_pred_zero<0b000, "movprfx">; defm MOVPRFX_ZPmZ : sve_int_movprfx_pred_merge<0b001, "movprfx">; def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>; def FEXPA_ZZ_H : sve_int_bin_cons_misc_0_c<0b01000000, "fexpa", ZPR16>; def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>; def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>; def BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa">; def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">; def BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb">; def BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs">; def BRKN_PPzP : sve_int_brkn<0b0, "brkn">; def BRKNS_PPzP : sve_int_brkn<0b1, "brkns">; defm BRKA_PPzP : sve_int_break_z<0b000, "brka">; defm BRKA_PPmP : sve_int_break_m<0b001, "brka">; defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">; defm BRKB_PPzP : sve_int_break_z<0b100, "brkb">; defm BRKB_PPmP : sve_int_break_m<0b101, "brkb">; defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">; def PTEST_PP : sve_int_ptest<0b010000, "ptest">; def PFALSE : sve_int_pfalse<0b000000, "pfalse">; defm PFIRST : sve_int_pfirst<0b00000, "pfirst">; defm PNEXT : sve_int_pnext<0b00110, "pnext">; def AND_PPzPP : sve_int_pred_log<0b0000, "and">; def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">; def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">; def SEL_PPPP : sve_int_pred_log<0b0011, "sel">; def ANDS_PPzPP : sve_int_pred_log<0b0100, "ands">; def BICS_PPzPP : sve_int_pred_log<0b0101, "bics">; def EORS_PPzPP : sve_int_pred_log<0b0110, "eors">; def ORR_PPzPP : sve_int_pred_log<0b1000, "orr">; def ORN_PPzPP : sve_int_pred_log<0b1001, "orn">; def NOR_PPzPP : sve_int_pred_log<0b1010, "nor">; def NAND_PPzPP : sve_int_pred_log<0b1011, "nand">; def ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs">; def ORNS_PPzPP : sve_int_pred_log<0b1101, "orns">; def NORS_PPzPP : sve_int_pred_log<0b1110, "nors">; def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">; defm CLASTA_RPZ : sve_int_perm_clast_rz<0, "clasta">; defm CLASTB_RPZ : sve_int_perm_clast_rz<1, "clastb">; defm CLASTA_VPZ : sve_int_perm_clast_vz<0, "clasta">; defm CLASTB_VPZ : sve_int_perm_clast_vz<1, "clastb">; defm CLASTA_ZPZ : sve_int_perm_clast_zz<0, "clasta">; defm CLASTB_ZPZ : sve_int_perm_clast_zz<1, "clastb">; defm LASTA_RPZ : sve_int_perm_last_r<0, "lasta">; defm LASTB_RPZ : sve_int_perm_last_r<1, "lastb">; defm LASTA_VPZ : sve_int_perm_last_v<0, "lasta">; defm LASTB_VPZ : sve_int_perm_last_v<1, "lastb">; // continuous load with reg+immediate defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>; defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>; defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>; defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>; defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>; defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>; defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>; defm LD1H_D_IMM : sve_mem_cld_si<0b0111, "ld1h", Z_d, ZPR64>; defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>; defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>; defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>; defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>; defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>; defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>; defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>; defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>; // LD1R loads (splat scalar to vector) defm LD1RB_IMM : sve_mem_ld_dup<0b00, 0b00, "ld1rb", Z_b, ZPR8, uimm6s1>; defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>; defm LD1RB_S_IMM : sve_mem_ld_dup<0b00, 0b10, "ld1rb", Z_s, ZPR32, uimm6s1>; defm LD1RB_D_IMM : sve_mem_ld_dup<0b00, 0b11, "ld1rb", Z_d, ZPR64, uimm6s1>; defm LD1RSW_IMM : sve_mem_ld_dup<0b01, 0b00, "ld1rsw", Z_d, ZPR64, uimm6s4>; defm LD1RH_IMM : sve_mem_ld_dup<0b01, 0b01, "ld1rh", Z_h, ZPR16, uimm6s2>; defm LD1RH_S_IMM : sve_mem_ld_dup<0b01, 0b10, "ld1rh", Z_s, ZPR32, uimm6s2>; defm LD1RH_D_IMM : sve_mem_ld_dup<0b01, 0b11, "ld1rh", Z_d, ZPR64, uimm6s2>; defm LD1RSH_D_IMM : sve_mem_ld_dup<0b10, 0b00, "ld1rsh", Z_d, ZPR64, uimm6s2>; defm LD1RSH_S_IMM : sve_mem_ld_dup<0b10, 0b01, "ld1rsh", Z_s, ZPR32, uimm6s2>; defm LD1RW_IMM : sve_mem_ld_dup<0b10, 0b10, "ld1rw", Z_s, ZPR32, uimm6s4>; defm LD1RW_D_IMM : sve_mem_ld_dup<0b10, 0b11, "ld1rw", Z_d, ZPR64, uimm6s4>; defm LD1RSB_D_IMM : sve_mem_ld_dup<0b11, 0b00, "ld1rsb", Z_d, ZPR64, uimm6s1>; defm LD1RSB_S_IMM : sve_mem_ld_dup<0b11, 0b01, "ld1rsb", Z_s, ZPR32, uimm6s1>; defm LD1RSB_H_IMM : sve_mem_ld_dup<0b11, 0b10, "ld1rsb", Z_h, ZPR16, uimm6s1>; defm LD1RD_IMM : sve_mem_ld_dup<0b11, 0b11, "ld1rd", Z_d, ZPR64, uimm6s8>; // LD1RQ loads (load quadword-vector and splat to scalable vector) defm LD1RQ_B_IMM : sve_mem_ldqr_si<0b00, "ld1rqb", Z_b, ZPR8>; defm LD1RQ_H_IMM : sve_mem_ldqr_si<0b01, "ld1rqh", Z_h, ZPR16>; defm LD1RQ_W_IMM : sve_mem_ldqr_si<0b10, "ld1rqw", Z_s, ZPR32>; defm LD1RQ_D_IMM : sve_mem_ldqr_si<0b11, "ld1rqd", Z_d, ZPR64>; defm LD1RQ_B : sve_mem_ldqr_ss<0b00, "ld1rqb", Z_b, ZPR8, GPR64NoXZRshifted8>; defm LD1RQ_H : sve_mem_ldqr_ss<0b01, "ld1rqh", Z_h, ZPR16, GPR64NoXZRshifted16>; defm LD1RQ_W : sve_mem_ldqr_ss<0b10, "ld1rqw", Z_s, ZPR32, GPR64NoXZRshifted32>; defm LD1RQ_D : sve_mem_ldqr_ss<0b11, "ld1rqd", Z_d, ZPR64, GPR64NoXZRshifted64>; // continuous load with reg+reg addressing. defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>; defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>; defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>; defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>; defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>; defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>; defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>; defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>; defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>; defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>; defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>; defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>; defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>; defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>; defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>; defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>; // non-faulting continuous load with reg+immediate defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>; defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>; defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>; defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>; defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>; defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>; defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>; defm LDNF1H_D_IMM : sve_mem_cldnf_si<0b0111, "ldnf1h", Z_d, ZPR64>; defm LDNF1SH_D_IMM : sve_mem_cldnf_si<0b1000, "ldnf1sh", Z_d, ZPR64>; defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>; defm LDNF1W_IMM : sve_mem_cldnf_si<0b1010, "ldnf1w", Z_s, ZPR32>; defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>; defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>; defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>; defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>; defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>; // First-faulting loads with reg+reg addressing. defm LDFF1B : sve_mem_cldff_ss<0b0000, "ldff1b", Z_b, ZPR8, GPR64shifted8>; defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>; defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>; defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>; defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>; defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>; defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>; defm LDFF1H_D : sve_mem_cldff_ss<0b0111, "ldff1h", Z_d, ZPR64, GPR64shifted16>; defm LDFF1SH_D : sve_mem_cldff_ss<0b1000, "ldff1sh", Z_d, ZPR64, GPR64shifted16>; defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>; defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>; defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>; defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>; defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>; defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>; defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>; // LD(2|3|4) structured loads with reg+immediate defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b, "ld2b", simm4s2>; defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b, "ld3b", simm4s3>; defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, ZZZZ_b, "ld4b", simm4s4>; defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h, "ld2h", simm4s2>; defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, ZZZ_h, "ld3h", simm4s3>; defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4s4>; defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s, "ld2w", simm4s2>; defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s, "ld3w", simm4s3>; defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4s4>; defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d, "ld2d", simm4s2>; defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4s3>; defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>; // LD(2|3|4) structured loads (register + register) def LD2B : sve_mem_eld_ss<0b00, 0b01, ZZ_b, "ld2b", GPR64NoXZRshifted8>; def LD3B : sve_mem_eld_ss<0b00, 0b10, ZZZ_b, "ld3b", GPR64NoXZRshifted8>; def LD4B : sve_mem_eld_ss<0b00, 0b11, ZZZZ_b, "ld4b", GPR64NoXZRshifted8>; def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>; def LD3H : sve_mem_eld_ss<0b01, 0b10, ZZZ_h, "ld3h", GPR64NoXZRshifted16>; def LD4H : sve_mem_eld_ss<0b01, 0b11, ZZZZ_h, "ld4h", GPR64NoXZRshifted16>; def LD2W : sve_mem_eld_ss<0b10, 0b01, ZZ_s, "ld2w", GPR64NoXZRshifted32>; def LD3W : sve_mem_eld_ss<0b10, 0b10, ZZZ_s, "ld3w", GPR64NoXZRshifted32>; def LD4W : sve_mem_eld_ss<0b10, 0b11, ZZZZ_s, "ld4w", GPR64NoXZRshifted32>; def LD2D : sve_mem_eld_ss<0b11, 0b01, ZZ_d, "ld2d", GPR64NoXZRshifted64>; def LD3D : sve_mem_eld_ss<0b11, 0b10, ZZZ_d, "ld3d", GPR64NoXZRshifted64>; def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>; // Gathers using unscaled 32-bit offsets, e.g. // ld1h z0.s, p0/z, [x0, z0.s, uxtw] defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>; // Gathers using scaled 32-bit offsets, e.g. // ld1h z0.s, p0/z, [x0, z0.s, uxtw #1] defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>; defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>; defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>; defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>; defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>; defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>; // Gathers using scaled 32-bit pointers with offset, e.g. // ld1h z0.s, p0/z, [z0.s, #16] defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31>; defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>; defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31>; defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31>; defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2>; defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>; defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2>; defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2>; defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4>; defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4>; // Gathers using scaled 64-bit pointers with offset, e.g. // ld1h z0.d, p0/z, [z0.d, #16] defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31>; defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>; defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31>; defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31>; defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2>; defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>; defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2>; defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2>; defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4>; defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>; defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4>; defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4>; defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8>; defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8>; // Gathers using unscaled 64-bit offsets, e.g. // ld1h z0.d, p0/z, [x0, z0.d] defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">; defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">; defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">; defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">; defm GLD1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh">; defm GLDFF1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0101, "ldff1sh">; defm GLD1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0110, "ld1h">; defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">; defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">; defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">; defm GLD1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">; defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">; defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">; defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">; // Gathers using scaled 64-bit offsets, e.g. // ld1h z0.d, p0/z, [x0, z0.d, lsl #1] defm GLD1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh", ZPR64ExtLSL16>; defm GLDFF1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0101, "ldff1sh", ZPR64ExtLSL16>; defm GLD1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0110, "ld1h", ZPR64ExtLSL16>; defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>; defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>; defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>; defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>; defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>; defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>; defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>; // Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g. // ld1h z0.d, p0/z, [x0, z0.d, uxtw] defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLDFF1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLD1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>; // Gathers using scaled 32-bit offsets unpacked in 64-bits elements, e.g. // ld1h z0.d, p0/z, [x0, z0.d, uxtw #1] defm GLD1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>; defm GLDFF1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0101, "ldff1sh",ZPR64ExtSXTW16, ZPR64ExtUXTW16>; defm GLD1H_D : sve_mem_64b_gld_sv_32_scaled<0b0110, "ld1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>; defm GLDFF1H_D : sve_mem_64b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>; defm GLD1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1000, "ld1sw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>; defm GLDFF1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1001, "ldff1sw",ZPR64ExtSXTW32, ZPR64ExtUXTW32>; defm GLD1W_D : sve_mem_64b_gld_sv_32_scaled<0b1010, "ld1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>; defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>; defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>; defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>; // Non-temporal contiguous loads (register + immediate) defm LDNT1B_ZRI : sve_mem_cldnt_si<0b00, "ldnt1b", Z_b, ZPR8>; defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>; defm LDNT1W_ZRI : sve_mem_cldnt_si<0b10, "ldnt1w", Z_s, ZPR32>; defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>; // Non-temporal contiguous loads (register + register) defm LDNT1B_ZRR : sve_mem_cldnt_ss<0b00, "ldnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>; defm LDNT1H_ZRR : sve_mem_cldnt_ss<0b01, "ldnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>; defm LDNT1W_ZRR : sve_mem_cldnt_ss<0b10, "ldnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>; defm LDNT1D_ZRR : sve_mem_cldnt_ss<0b11, "ldnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>; // contiguous store with immediates defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>; defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>; defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>; defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>; defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>; defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>; defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>; defm ST1W_IMM : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>; defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>; defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>; // contiguous store with reg+reg addressing. defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>; defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>; defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>; defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>; defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>; defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>; defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>; defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>; defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>; defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>; // Scatters using unscaled 32-bit offsets, e.g. // st1h z0.s, p0, [x0, z0.s, uxtw] // and unpacked: // st1h z0.d, p0, [x0, z0.d, uxtw] defm SST1B_D : sve_mem_sst_sv_32_unscaled<0b000, "st1b", Z_d, ZPR64, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm SST1B_S : sve_mem_sst_sv_32_unscaled<0b001, "st1b", Z_s, ZPR32, ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm SST1H_D : sve_mem_sst_sv_32_unscaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm SST1H_S : sve_mem_sst_sv_32_unscaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm SST1W_D : sve_mem_sst_sv_32_unscaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>; defm SST1W : sve_mem_sst_sv_32_unscaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>; defm SST1D : sve_mem_sst_sv_32_unscaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>; // Scatters using scaled 32-bit offsets, e.g. // st1h z0.s, p0, [x0, z0.s, uxtw #1] // and unpacked: // st1h z0.d, p0, [x0, z0.d, uxtw #1] defm SST1H_D : sve_mem_sst_sv_32_scaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW16, ZPR64ExtUXTW16>; defm SST1H_S : sve_mem_sst_sv_32_scaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW16, ZPR32ExtUXTW16>; defm SST1W_D : sve_mem_sst_sv_32_scaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW32, ZPR64ExtUXTW32>; defm SST1W : sve_mem_sst_sv_32_scaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW32, ZPR32ExtUXTW32>; defm SST1D : sve_mem_sst_sv_32_scaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW64, ZPR64ExtUXTW64>; // Scatters using 32/64-bit pointers with offset, e.g. // st1h z0.s, p0, [z0.s, #16] // st1h z0.d, p0, [z0.d, #16] defm SST1B_D : sve_mem_sst_vi_ptrs<0b000, "st1b", Z_d, ZPR64, imm0_31>; defm SST1B_S : sve_mem_sst_vi_ptrs<0b001, "st1b", Z_s, ZPR32, imm0_31>; defm SST1H_D : sve_mem_sst_vi_ptrs<0b010, "st1h", Z_d, ZPR64, uimm5s2>; defm SST1H_S : sve_mem_sst_vi_ptrs<0b011, "st1h", Z_s, ZPR32, uimm5s2>; defm SST1W_D : sve_mem_sst_vi_ptrs<0b100, "st1w", Z_d, ZPR64, uimm5s4>; defm SST1W : sve_mem_sst_vi_ptrs<0b101, "st1w", Z_s, ZPR32, uimm5s4>; defm SST1D : sve_mem_sst_vi_ptrs<0b110, "st1d", Z_d, ZPR64, uimm5s8>; // Scatters using unscaled 64-bit offsets, e.g. // st1h z0.d, p0, [x0, z0.d] defm SST1B_D : sve_mem_sst_sv_64_unscaled<0b00, "st1b">; defm SST1H_D : sve_mem_sst_sv_64_unscaled<0b01, "st1h">; defm SST1W_D : sve_mem_sst_sv_64_unscaled<0b10, "st1w">; defm SST1D : sve_mem_sst_sv_64_unscaled<0b11, "st1d">; // Scatters using scaled 64-bit offsets, e.g. // st1h z0.d, p0, [x0, z0.d, lsl #1] defm SST1H_D_SCALED : sve_mem_sst_sv_64_scaled<0b01, "st1h", ZPR64ExtLSL16>; defm SST1W_D_SCALED : sve_mem_sst_sv_64_scaled<0b10, "st1w", ZPR64ExtLSL32>; defm SST1D_SCALED : sve_mem_sst_sv_64_scaled<0b11, "st1d", ZPR64ExtLSL64>; // ST(2|3|4) structured stores (register + immediate) defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>; defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>; defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4s4>; defm ST2H_IMM : sve_mem_est_si<0b01, 0b01, ZZ_h, "st2h", simm4s2>; defm ST3H_IMM : sve_mem_est_si<0b01, 0b10, ZZZ_h, "st3h", simm4s3>; defm ST4H_IMM : sve_mem_est_si<0b01, 0b11, ZZZZ_h, "st4h", simm4s4>; defm ST2W_IMM : sve_mem_est_si<0b10, 0b01, ZZ_s, "st2w", simm4s2>; defm ST3W_IMM : sve_mem_est_si<0b10, 0b10, ZZZ_s, "st3w", simm4s3>; defm ST4W_IMM : sve_mem_est_si<0b10, 0b11, ZZZZ_s, "st4w", simm4s4>; defm ST2D_IMM : sve_mem_est_si<0b11, 0b01, ZZ_d, "st2d", simm4s2>; defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>; defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>; // ST(2|3|4) structured stores (register + register) def ST2B : sve_mem_est_ss<0b00, 0b01, ZZ_b, "st2b", GPR64NoXZRshifted8>; def ST3B : sve_mem_est_ss<0b00, 0b10, ZZZ_b, "st3b", GPR64NoXZRshifted8>; def ST4B : sve_mem_est_ss<0b00, 0b11, ZZZZ_b, "st4b", GPR64NoXZRshifted8>; def ST2H : sve_mem_est_ss<0b01, 0b01, ZZ_h, "st2h", GPR64NoXZRshifted16>; def ST3H : sve_mem_est_ss<0b01, 0b10, ZZZ_h, "st3h", GPR64NoXZRshifted16>; def ST4H : sve_mem_est_ss<0b01, 0b11, ZZZZ_h, "st4h", GPR64NoXZRshifted16>; def ST2W : sve_mem_est_ss<0b10, 0b01, ZZ_s, "st2w", GPR64NoXZRshifted32>; def ST3W : sve_mem_est_ss<0b10, 0b10, ZZZ_s, "st3w", GPR64NoXZRshifted32>; def ST4W : sve_mem_est_ss<0b10, 0b11, ZZZZ_s, "st4w", GPR64NoXZRshifted32>; def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>; def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>; def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>; // Non-temporal contiguous stores (register + immediate) defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>; defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>; defm STNT1W_ZRI : sve_mem_cstnt_si<0b10, "stnt1w", Z_s, ZPR32>; defm STNT1D_ZRI : sve_mem_cstnt_si<0b11, "stnt1d", Z_d, ZPR64>; // Non-temporal contiguous stores (register + register) defm STNT1B_ZRR : sve_mem_cstnt_ss<0b00, "stnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>; defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>; defm STNT1W_ZRR : sve_mem_cstnt_ss<0b10, "stnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>; defm STNT1D_ZRR : sve_mem_cstnt_ss<0b11, "stnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>; // Fill/Spill defm LDR_ZXI : sve_mem_z_fill<"ldr">; defm LDR_PXI : sve_mem_p_fill<"ldr">; defm STR_ZXI : sve_mem_z_spill<"str">; defm STR_PXI : sve_mem_p_spill<"str">; // Contiguous prefetch (register + immediate) defm PRFB_PRI : sve_mem_prfm_si<0b00, "prfb">; defm PRFH_PRI : sve_mem_prfm_si<0b01, "prfh">; defm PRFW_PRI : sve_mem_prfm_si<0b10, "prfw">; defm PRFD_PRI : sve_mem_prfm_si<0b11, "prfd">; // Contiguous prefetch (register + register) def PRFB_PRR : sve_mem_prfm_ss<0b001, "prfb", GPR64NoXZRshifted8>; def PRFH_PRR : sve_mem_prfm_ss<0b011, "prfh", GPR64NoXZRshifted16>; def PRFS_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>; def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>; // Gather prefetch using scaled 32-bit offsets, e.g. // prfh pldl1keep, p0, [x0, z0.s, uxtw #1] defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>; defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32, ZPR32ExtUXTW32>; defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64, ZPR32ExtUXTW64>; // Gather prefetch using unpacked, scaled 32-bit offsets, e.g. // prfh pldl1keep, p0, [x0, z0.d, uxtw #1] defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>; defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>; defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64, ZPR64ExtUXTW64>; // Gather prefetch using scaled 64-bit offsets, e.g. // prfh pldl1keep, p0, [x0, z0.d, lsl #1] defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8>; defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16>; defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32>; defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64>; // Gather prefetch using 32/64-bit pointers with offset, e.g. // prfh pldl1keep, p0, [z0.s, #16] // prfh pldl1keep, p0, [z0.d, #16] defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31>; defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2>; defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4>; defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8>; defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31>; defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2>; defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>; defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>; defm ADR_SXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_sxtw<0b00, "adr">; defm ADR_UXTW_ZZZ_D : sve_int_bin_cons_misc_0_a_uxtw<0b01, "adr">; defm ADR_LSL_ZZZ_S : sve_int_bin_cons_misc_0_a_32_lsl<0b10, "adr">; defm ADR_LSL_ZZZ_D : sve_int_bin_cons_misc_0_a_64_lsl<0b11, "adr">; defm TBL_ZZZ : sve_int_perm_tbl<"tbl">; defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">; defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">; defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">; defm UZP2_ZZZ : sve_int_perm_bin_perm_zz<0b011, "uzp2">; defm TRN1_ZZZ : sve_int_perm_bin_perm_zz<0b100, "trn1">; defm TRN2_ZZZ : sve_int_perm_bin_perm_zz<0b101, "trn2">; defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">; defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">; defm UZP1_PPP : sve_int_perm_bin_perm_pp<0b010, "uzp1">; defm UZP2_PPP : sve_int_perm_bin_perm_pp<0b011, "uzp2">; defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">; defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">; defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs">; defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi">; defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge">; defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt">; defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq">; defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne">; defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq">; defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne">; defm CMPGE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b000, "cmpge">; defm CMPGT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b001, "cmpgt">; defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt">; defm CMPLE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b011, "cmple">; defm CMPHS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b100, "cmphs">; defm CMPHI_WIDE_PPzZZ : sve_int_cmp_1_wide<0b101, "cmphi">; defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">; defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">; defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge">; defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt">; defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt">; defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple">; defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq">; defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne">; defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs">; defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi">; defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo">; defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls">; defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge">; defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt">; defm FCMEQ_PPzZZ : sve_fp_3op_p_pd<0b010, "fcmeq">; defm FCMNE_PPzZZ : sve_fp_3op_p_pd<0b011, "fcmne">; defm FCMUO_PPzZZ : sve_fp_3op_p_pd<0b100, "fcmuo">; defm FACGE_PPzZZ : sve_fp_3op_p_pd<0b101, "facge">; defm FACGT_PPzZZ : sve_fp_3op_p_pd<0b111, "facgt">; defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge">; defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt">; defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt">; defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle">; defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq">; defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne">; defm WHILELT_PWW : sve_int_while4_rr<0b010, "whilelt">; defm WHILELE_PWW : sve_int_while4_rr<0b011, "whilele">; defm WHILELO_PWW : sve_int_while4_rr<0b110, "whilelo">; defm WHILELS_PWW : sve_int_while4_rr<0b111, "whilels">; defm WHILELT_PXX : sve_int_while8_rr<0b010, "whilelt">; defm WHILELE_PXX : sve_int_while8_rr<0b011, "whilele">; defm WHILELO_PXX : sve_int_while8_rr<0b110, "whilelo">; defm WHILELS_PXX : sve_int_while8_rr<0b111, "whilels">; def CTERMEQ_WW : sve_int_cterm<0b0, 0b0, "ctermeq", GPR32>; def CTERMNE_WW : sve_int_cterm<0b0, 0b1, "ctermne", GPR32>; def CTERMEQ_XX : sve_int_cterm<0b1, 0b0, "ctermeq", GPR64>; def CTERMNE_XX : sve_int_cterm<0b1, 0b1, "ctermne", GPR64>; def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">; def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">; def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">; defm CNTB_XPiI : sve_int_count<0b000, "cntb">; defm CNTH_XPiI : sve_int_count<0b010, "cnth">; defm CNTW_XPiI : sve_int_count<0b100, "cntw">; defm CNTD_XPiI : sve_int_count<0b110, "cntd">; defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp">; defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">; defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">; defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">; defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">; defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">; defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">; defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">; defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">; defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">; defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">; defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">; defm UQDECB_WPiI : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">; defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">; defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">; defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">; defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">; defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">; defm UQINCH_WPiI : sve_int_pred_pattern_b_u32<0b01001, "uqinch">; defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">; defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech">; defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">; defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">; defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">; defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">; defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">; defm UQINCW_WPiI : sve_int_pred_pattern_b_u32<0b10001, "uqincw">; defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">; defm UQDECW_WPiI : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">; defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">; defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">; defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">; defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">; defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">; defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd">; defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">; defm UQDECD_WPiI : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">; defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">; defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">; defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">; defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">; defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>; defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>; defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>; defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>; defm INCH_ZPiI : sve_int_countvlv<0b01100, "inch", ZPR16>; defm DECH_ZPiI : sve_int_countvlv<0b01101, "dech", ZPR16>; defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>; defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>; defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>; defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>; defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>; defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>; defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>; defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>; defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>; defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>; defm INCD_ZPiI : sve_int_countvlv<0b11100, "incd", ZPR64>; defm DECD_ZPiI : sve_int_countvlv<0b11101, "decd", ZPR64>; defm SQINCP_XPWd : sve_int_count_r_s32<0b00000, "sqincp">; defm SQINCP_XP : sve_int_count_r_x64<0b00010, "sqincp">; defm UQINCP_WP : sve_int_count_r_u32<0b00100, "uqincp">; defm UQINCP_XP : sve_int_count_r_x64<0b00110, "uqincp">; defm SQDECP_XPWd : sve_int_count_r_s32<0b01000, "sqdecp">; defm SQDECP_XP : sve_int_count_r_x64<0b01010, "sqdecp">; defm UQDECP_WP : sve_int_count_r_u32<0b01100, "uqdecp">; defm UQDECP_XP : sve_int_count_r_x64<0b01110, "uqdecp">; defm INCP_XP : sve_int_count_r_x64<0b10000, "incp">; defm DECP_XP : sve_int_count_r_x64<0b10100, "decp">; defm SQINCP_ZP : sve_int_count_v<0b00000, "sqincp">; defm UQINCP_ZP : sve_int_count_v<0b00100, "uqincp">; defm SQDECP_ZP : sve_int_count_v<0b01000, "sqdecp">; defm UQDECP_ZP : sve_int_count_v<0b01100, "uqdecp">; defm INCP_ZP : sve_int_count_v<0b10000, "incp">; defm DECP_ZP : sve_int_count_v<0b10100, "decp">; defm INDEX_RR : sve_int_index_rr<"index">; defm INDEX_IR : sve_int_index_ir<"index">; defm INDEX_RI : sve_int_index_ri<"index">; defm INDEX_II : sve_int_index_ii<"index">; // Unpredicated shifts defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr">; defm LSR_ZZI : sve_int_bin_cons_shift_imm_right<0b01, "lsr">; defm LSL_ZZI : sve_int_bin_cons_shift_imm_left< 0b11, "lsl">; defm ASR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b00, "asr">; defm LSR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b01, "lsr">; defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; // Predicated shifts defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl">; defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr">; defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr">; defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr">; defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr">; defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr">; defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl">; def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16, ElementSizeS>; def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32, ElementSizeS>; def SCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110010, "scvtf", ZPR16, ZPR16, ElementSizeH>; def SCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010100, "scvtf", ZPR32, ZPR32, ElementSizeS>; def UCVTF_ZPmZ_StoS : sve_fp_2op_p_zd<0b1010101, "ucvtf", ZPR32, ZPR32, ElementSizeS>; def UCVTF_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0110011, "ucvtf", ZPR16, ZPR16, ElementSizeH>; def FCVTZS_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111010, "fcvtzs", ZPR16, ZPR16, ElementSizeH>; def FCVTZS_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011100, "fcvtzs", ZPR32, ZPR32, ElementSizeS>; def FCVTZU_ZPmZ_HtoH : sve_fp_2op_p_zd<0b0111011, "fcvtzu", ZPR16, ZPR16, ElementSizeH>; def FCVTZU_ZPmZ_StoS : sve_fp_2op_p_zd<0b1011101, "fcvtzu", ZPR32, ZPR32, ElementSizeS>; def FCVT_ZPmZ_DtoH : sve_fp_2op_p_zd<0b1101000, "fcvt", ZPR64, ZPR16, ElementSizeD>; def FCVT_ZPmZ_HtoD : sve_fp_2op_p_zd<0b1101001, "fcvt", ZPR16, ZPR64, ElementSizeD>; def FCVT_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1101010, "fcvt", ZPR64, ZPR32, ElementSizeD>; def FCVT_ZPmZ_StoD : sve_fp_2op_p_zd<0b1101011, "fcvt", ZPR32, ZPR64, ElementSizeD>; def SCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110000, "scvtf", ZPR32, ZPR64, ElementSizeD>; def UCVTF_ZPmZ_StoD : sve_fp_2op_p_zd<0b1110001, "ucvtf", ZPR32, ZPR64, ElementSizeD>; def UCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110101, "ucvtf", ZPR32, ZPR16, ElementSizeS>; def SCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110100, "scvtf", ZPR64, ZPR32, ElementSizeD>; def SCVTF_ZPmZ_StoH : sve_fp_2op_p_zd<0b0110100, "scvtf", ZPR32, ZPR16, ElementSizeS>; def SCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110110, "scvtf", ZPR64, ZPR16, ElementSizeD>; def UCVTF_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1110101, "ucvtf", ZPR64, ZPR32, ElementSizeD>; def UCVTF_ZPmZ_DtoH : sve_fp_2op_p_zd<0b0110111, "ucvtf", ZPR64, ZPR16, ElementSizeD>; def SCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110110, "scvtf", ZPR64, ZPR64, ElementSizeD>; def UCVTF_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1110111, "ucvtf", ZPR64, ZPR64, ElementSizeD>; def FCVTZS_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111000, "fcvtzs", ZPR64, ZPR32, ElementSizeD>; def FCVTZU_ZPmZ_DtoS : sve_fp_2op_p_zd<0b1111001, "fcvtzu", ZPR64, ZPR32, ElementSizeD>; def FCVTZS_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111100, "fcvtzs", ZPR32, ZPR64, ElementSizeD>; def FCVTZS_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111100, "fcvtzs", ZPR16, ZPR32, ElementSizeS>; def FCVTZS_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111110, "fcvtzs", ZPR16, ZPR64, ElementSizeD>; def FCVTZU_ZPmZ_HtoS : sve_fp_2op_p_zd<0b0111101, "fcvtzu", ZPR16, ZPR32, ElementSizeS>; def FCVTZU_ZPmZ_HtoD : sve_fp_2op_p_zd<0b0111111, "fcvtzu", ZPR16, ZPR64, ElementSizeD>; def FCVTZU_ZPmZ_StoD : sve_fp_2op_p_zd<0b1111101, "fcvtzu", ZPR32, ZPR64, ElementSizeD>; def FCVTZS_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111110, "fcvtzs", ZPR64, ZPR64, ElementSizeD>; def FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd<0b1111111, "fcvtzu", ZPR64, ZPR64, ElementSizeD>; defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn">; defm FRINTP_ZPmZ : sve_fp_2op_p_zd_HSD<0b00001, "frintp">; defm FRINTM_ZPmZ : sve_fp_2op_p_zd_HSD<0b00010, "frintm">; defm FRINTZ_ZPmZ : sve_fp_2op_p_zd_HSD<0b00011, "frintz">; defm FRINTA_ZPmZ : sve_fp_2op_p_zd_HSD<0b00100, "frinta">; defm FRINTX_ZPmZ : sve_fp_2op_p_zd_HSD<0b00110, "frintx">; defm FRINTI_ZPmZ : sve_fp_2op_p_zd_HSD<0b00111, "frinti">; defm FRECPX_ZPmZ : sve_fp_2op_p_zd_HSD<0b01100, "frecpx">; defm FSQRT_ZPmZ : sve_fp_2op_p_zd_HSD<0b01101, "fsqrt">; // InstAliases def : InstAlias<"mov $Zd, $Zn", (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>; def : InstAlias<"mov $Pd, $Pg/m, $Pn", (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>; def : InstAlias<"mov $Pd, $Pn", (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>; def : InstAlias<"mov $Pd, $Pg/z, $Pn", (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>; def : InstAlias<"movs $Pd, $Pn", (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>; def : InstAlias<"movs $Pd, $Pg/z, $Pn", (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>; def : InstAlias<"not $Pd, $Pg/z, $Pn", (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>; def : InstAlias<"nots $Pd, $Pg/z, $Pn", (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>; def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn", (CMPGE_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>; def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn", (CMPGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn", (CMPGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn", (CMPGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn", (CMPHI_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>; def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn", (CMPHI_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn", (CMPHI_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn", (CMPHI_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn", (CMPHS_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>; def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn", (CMPHS_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn", (CMPHS_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn", (CMPHS_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn", (CMPGT_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>; def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn", (CMPGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn", (CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn", (CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn", (FACGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn", (FACGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn", (FACGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn", (FACGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn", (FACGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn", (FACGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn", (FCMGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn", (FCMGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn", (FCMGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn", (FCMGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn", (FCMGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn", (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedA53.td000064400000000000000000000362460072674642500252160ustar 00000000000000//==- AArch64SchedA53.td - Cortex-A53 Scheduling Definitions -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the itinerary class data for the ARM Cortex A53 processors. // //===----------------------------------------------------------------------===// // ===---------------------------------------------------------------------===// // The following definitions describe the simpler per-operand machine model. // This works with MachineScheduler. See MCSchedule.h for details. // Cortex-A53 machine model for scheduling and other instruction cost heuristics. def CortexA53Model : SchedMachineModel { let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order. let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. let LoadLatency = 3; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation // Specification - Instruction Timings" // v 1.0 Spreadsheet let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available. // Modeling each pipeline as a ProcResource using the BufferSize = 0 since // Cortex-A53 is in-order. def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt //===----------------------------------------------------------------------===// // Subtarget-specific SchedWrite types which both map the ProcResources and // set the latency. let SchedModel = CortexA53Model in { // ALU - Despite having a full latency of 4, most of the ALU instructions can // forward a cycle earlier and then two cycles earlier in the case of a // shift-only instruction. These latencies will be incorrect when the // result cannot be forwarded, but modeling isn't rocket surgery. def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 3; } // MAC def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } // Div def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } // Load def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } // Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd // below, choosing the median of 3 which makes the latency 6. // May model this more carefully in the future. The remaining // A53WriteVLD# types represent the 1-5 cycle issues explicitly. def : WriteRes { let Latency = 6; let ResourceCycles = [3]; } def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; } def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5; let ResourceCycles = [2]; } def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6; let ResourceCycles = [3]; } def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7; let ResourceCycles = [4]; } def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8; let ResourceCycles = [5]; } // Pre/Post Indexing - Performed as part of address generation which is already // accounted for in the WriteST* latencies below def : WriteRes { let Latency = 0; } // Store def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } // Vector Store - Similar to vector loads, can take 1-3 cycles to issue. def : WriteRes { let Latency = 5; let ResourceCycles = [2];} def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; } def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5; let ResourceCycles = [2]; } def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6; let ResourceCycles = [3]; } def : WriteRes { let Unsupported = 1; } // Branch def : WriteRes; def : WriteRes; def : WriteRes; def : WriteRes; def : WriteRes; // FP ALU def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } // FP Mul, Div, Sqrt def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 33; let ResourceCycles = [29]; } def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; } def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18; let ResourceCycles = [14]; } def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33; let ResourceCycles = [29]; } def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17; let ResourceCycles = [13]; } def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32; let ResourceCycles = [28]; } //===----------------------------------------------------------------------===// // Subtarget-specific SchedRead types. // No forwarding for these reads. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // operands are needed one cycle later if and only if they are to be // shifted. Otherwise, they too are needed two cycles later. This same // ReadAdvance applies to Extended registers as well, even though there is // a separate SchedPredicate for them. def : ReadAdvance; def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI, WriteISReg, WriteIEReg,WriteIS, WriteID32,WriteID64, WriteIM32,WriteIM64]>; def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI, WriteISReg, WriteIEReg,WriteIS, WriteID32,WriteID64, WriteIM32,WriteIM64]>; def A53ReadISReg : SchedReadVariant<[ SchedVar, SchedVar]>; def : SchedAlias; def A53ReadIEReg : SchedReadVariant<[ SchedVar, SchedVar]>; def : SchedAlias; // MAC - Operands are generally needed one cycle later in the MAC pipe. // Accumulator operands are needed two cycles later. def : ReadAdvance; def : ReadAdvance; // Div def : ReadAdvance; //===----------------------------------------------------------------------===// // Subtarget-specific InstRWs. //--- // Miscellaneous //--- def : InstRW<[WriteI], (instrs COPY)>; //--- // Vector Loads //--- def : InstRW<[A53WriteVLD1], (instregex "LD1i(8|16|32|64)$")>; def : InstRW<[A53WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD1], (instregex "LD2i(8|16|32|64)$")>; def : InstRW<[A53WriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>; def : InstRW<[A53WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD2], (instregex "LD3i(8|16|32|64)$")>; def : InstRW<[A53WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[A53WriteVLD3], (instregex "LD3Threev2d$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[A53WriteVLD3, WriteAdr], (instregex "LD3Threev2d_POST$")>; def : InstRW<[A53WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; def : InstRW<[A53WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[A53WriteVLD4], (instregex "LD4Fourv(2d)$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[A53WriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; //--- // Vector Stores //--- def : InstRW<[A53WriteVST1], (instregex "ST1i(8|16|32|64)$")>; def : InstRW<[A53WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVST1], (instregex "ST2i(8|16|32|64)$")>; def : InstRW<[A53WriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>; def : InstRW<[A53WriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>; def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[A53WriteVST2], (instregex "ST3i(8|16|32|64)$")>; def : InstRW<[A53WriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[A53WriteVST2], (instregex "ST3Threev(2d)$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; def : InstRW<[A53WriteVST2], (instregex "ST4i(8|16|32|64)$")>; def : InstRW<[A53WriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[A53WriteVST2], (instregex "ST4Fourv(2d)$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; def : InstRW<[A53WriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[A53WriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; //--- // Floating Point MAC, DIV, SQRT //--- def : InstRW<[A53WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>; def : InstRW<[A53WriteFMAC], (instregex "^FML(A|S).*")>; def : InstRW<[A53WriteFDivSP], (instrs FDIVSrr)>; def : InstRW<[A53WriteFDivDP], (instrs FDIVDrr)>; def : InstRW<[A53WriteFDivSP], (instregex "^FDIVv.*32$")>; def : InstRW<[A53WriteFDivDP], (instregex "^FDIVv.*64$")>; def : InstRW<[A53WriteFSqrtSP], (instregex "^.*SQRT.*32$")>; def : InstRW<[A53WriteFSqrtDP], (instregex "^.*SQRT.*64$")>; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedA57.td000064400000000000000000001051050072674642500252110ustar 00000000000000//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for ARM Cortex-A57 to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // The Cortex-A57 is a traditional superscalar microprocessor with a // conservative 3-wide in-order stage for decode and dispatch. Combined with the // much wider out-of-order issue stage, this produced a need to carefully // schedule micro-ops so that all three decoded each cycle are successfully // issued as the reservation station(s) simply don't stay occupied for long. // Therefore, IssueWidth is set to the narrower of the two at three, while still // modeling the machine as out-of-order. def CortexA57Model : SchedMachineModel { let IssueWidth = 3; // 3-way decode and dispatch let MicroOpBufferSize = 128; // 128 micro-op re-order buffer let LoadLatency = 4; // Optimistic load latency let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch // Enable partial & runtime unrolling. The magic number is chosen based on // experiments and benchmarking data. let LoopMicroOpBufferSize = 16; let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available on Cortex-A57. // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where // micro-ops wait for their operands and then issue out-of-order. def A57UnitB : ProcResource<1>; // Type B micro-ops def A57UnitI : ProcResource<2>; // Type I micro-ops def A57UnitM : ProcResource<1>; // Type M micro-ops def A57UnitL : ProcResource<1>; // Type L micro-ops def A57UnitS : ProcResource<1>; // Type S micro-ops def A57UnitX : ProcResource<1>; // Type X micro-ops def A57UnitW : ProcResource<1>; // Type W micro-ops let SchedModel = CortexA57Model in { def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops } let SchedModel = CortexA57Model in { //===----------------------------------------------------------------------===// // Define customized scheduler read/write types specific to the Cortex-A57. include "AArch64SchedA57WriteRes.td" //===----------------------------------------------------------------------===// // Map the target-defined scheduler read/write resources and latency for // Cortex-A57. The Cortex-A57 types are directly associated with resources, so // defining the aliases precludes the need for mapping them using WriteRes. The // aliases are sufficient for creating a coarse, working model. As the model // evolves, InstRWs will be used to override some of these SchedAliases. // // WARNING: Using SchedAliases is convenient and works well for latency and // resource lookup for instructions. However, this creates an entry in // AArch64WriteLatencyTable with a WriteResourceID of 0, breaking // any SchedReadAdvance since the lookup will fail. def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 5; } def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; def : WriteRes { let Unsupported = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 4; } // Forwarding logic is only modeled for multiply and accumulate def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; //===----------------------------------------------------------------------===// // Specialize the coarse model by associating instruction groups with the // subtarget-defined types. As the modeled is refined, this will override most // of the above ShchedAlias mappings. // Miscellaneous // ----------------------------------------------------------------------------- def : InstRW<[WriteI], (instrs COPY)>; // Branch Instructions // ----------------------------------------------------------------------------- def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>; def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>; // Shifted Register with Shift == 0 // ---------------------------------------------------------------------------- def A57WriteISReg : SchedWriteVariant<[ SchedVar, SchedVar]>; def : InstRW<[A57WriteISReg], (instregex ".*rs$")>; // Divide and Multiply Instructions // ----------------------------------------------------------------------------- // Multiply high def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>; // Miscellaneous Data-Processing Instructions // ----------------------------------------------------------------------------- def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>; def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>; def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>; // Cryptography Extensions // ----------------------------------------------------------------------------- def A57ReadAES : SchedReadAdvance<3, [A57Write_3cyc_1W]>; def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>; def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>; def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>; def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>; def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>; def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>; def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>; def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>; // Vector Load // ----------------------------------------------------------------------------- def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>; def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>; def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>; def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>; def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>; def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>; def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>; def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>; def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>; def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>; def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>; def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>; def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>; def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>; def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>; def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>; def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>; def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>; def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>; def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>; def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>; def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>; def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>; def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>; def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>; def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>; def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>; def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>; def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>; def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>; def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; // Vector Store // ----------------------------------------------------------------------------- def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>; def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>; def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>; def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>; def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>; def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>; def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>; def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>; def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>; def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>; def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>; def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>; def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>; def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>; def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>; def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>; def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>; def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>; def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>; def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>; def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>; def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>; def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>; def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>; def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>; def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>; def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>; def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; // Vector - Integer // ----------------------------------------------------------------------------- // Reference for forms in this group // D form - v8i8, v4i16, v2i32 // Q form - v16i8, v8i16, v4i32 // D form - v1i8, v1i16, v1i32, v1i64 // Q form - v16i8, v8i16, v4i32, v2i64 // D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64 // Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64 // ASIMD absolute diff accum, D-form def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; // ASIMD absolute diff accum, Q-form def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; // ASIMD absolute diff accum long def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>; // ASIMD arith, reduce, 4H/4S def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; // ASIMD arith, reduce, 8B/8H def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; // ASIMD arith, reduce, 16B def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>; // ASIMD max/min, reduce, 4H/4S def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; // ASIMD max/min, reduce, 8B/8H def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; // ASIMD max/min, reduce, 16B def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; // ASIMD multiply, D-form def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>; // ASIMD multiply, Q-form def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; // ASIMD multiply accumulate, D-form def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; // ASIMD multiply accumulate, Q-form def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; // ASIMD multiply accumulate long // ASIMD multiply accumulate saturating long def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; } def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>; def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>; // ASIMD multiply long def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>; def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>; def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>; // ASIMD pairwise add and accumulate // ASIMD shift accumulate def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; } def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>; def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>; def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>; // ASIMD shift by immed, complex def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>; def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>; // ASIMD shift by register, basic, Q-form def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; // ASIMD shift by register, complex, D-form def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; // ASIMD shift by register, complex, Q-form def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; // Vector - Floating Point // ----------------------------------------------------------------------------- // Reference for forms in this group // D form - v2f32 // Q form - v4f32, v2f64 // D form - 32, 64 // D form - v1i32, v1i64 // D form - v2i32 // Q form - v4i32, v2i64 // ASIMD FP arith, normal, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>; // ASIMD FP arith, normal, Q-form def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>; // ASIMD FP arith, pairwise, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>; // ASIMD FP arith, pairwise, Q-form def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>; // ASIMD FP compare, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>; // ASIMD FP compare, Q-form def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP convert, long and narrow def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>; // ASIMD FP convert, other, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; // ASIMD FP convert, other, Q-form def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP divide, D-form, F32 def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>; // ASIMD FP divide, Q-form, F32 def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>; // ASIMD FP divide, Q-form, F64 def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>; // Note: These were simply duplicated from ASIMD FDIV because of missing documentation // ASIMD FP square root, D-form, F32 def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>; // ASIMD FP square root, Q-form, F32 def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>; // ASIMD FP square root, Q-form, F64 def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>; // ASIMD FP max/min, normal, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>; // ASIMD FP max/min, normal, Q-form def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>; // ASIMD FP max/min, pairwise, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>; // ASIMD FP max/min, pairwise, Q-form def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>; // ASIMD FP max/min, reduce def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>; // ASIMD FP multiply, D-form, FZ def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; // ASIMD FP multiply, Q-form, FZ def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP multiply accumulate, D-form, FZ // ASIMD FP multiply accumulate, Q-form, FZ def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP round, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>; // ASIMD FP round, Q-form def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; // Vector - Miscellaneous // ----------------------------------------------------------------------------- // Reference for forms in this group // D form - v8i8, v4i16, v2i32 // Q form - v16i8, v8i16, v4i32 // D form - v1i8, v1i16, v1i32, v1i64 // Q form - v16i8, v8i16, v4i32, v2i64 // ASIMD bitwise insert, Q-form def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>; // ASIMD duplicate, gen reg, D-form and Q-form def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>; def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>; // ASIMD move, saturating def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>; // ASIMD reciprocal estimate, D-form def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>; // ASIMD reciprocal estimate, Q-form def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>; // ASIMD reciprocal step, D-form, FZ def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>; // ASIMD reciprocal step, Q-form, FZ def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>; // ASIMD table lookup, D-form def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>; def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>; def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>; def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>; // ASIMD table lookup, Q-form def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>; def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>; def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>; def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>; // ASIMD transfer, element to gen reg def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>; // ASIMD transfer, gen reg to element def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>; // ASIMD unzip/zip, Q-form def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>; // Remainder // ----------------------------------------------------------------------------- def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>; def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; } def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>; def A57ReadFPM : SchedReadAdvance<0>; def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>; def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>; def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>; def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>; def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>; def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>; def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>; def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>; def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>; def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>; def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>; def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>; def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>; def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>; def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>; def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>; def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>; def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>; def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>; def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>; def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>; def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>; def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>; def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>; def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>; def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>; def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>; def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>; def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>; def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>; def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>; def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>; def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>; def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>; def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>; def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>; def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>; def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>; def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>; def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>; def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>; def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>; def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>; def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>; def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>; def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>; def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>; def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>; def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>; def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>; def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>; def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>; def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>; def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>; def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>; def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>; def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>; def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>; def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>; def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>; def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>; def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>; def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>; } // SchedModel = CortexA57Model capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedA57WriteRes.td000064400000000000000000000475360072674642500267130ustar 00000000000000//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach // below is to define a generic SchedWriteRes for every combination of // latency and microOps. The naming conventions is to use a prefix, one field // for latency, and one or more microOp count/type designators. // Prefix: A57Write // Latency: #cyc // MicroOp Count/Types: #(B|I|M|L|S|X|W|V) // // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Define Generic 1 micro-op types def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; } def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; } def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; } def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; } def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; } def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17; let ResourceCycles = [17]; } def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; let ResourceCycles = [19]; } def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; } def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; } def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; } def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; } def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32; let ResourceCycles = [32]; } def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; let ResourceCycles = [35]; } def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; } def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; } def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; } def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; } def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; } def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; } def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; } def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; } def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; } //===----------------------------------------------------------------------===// // Define Generic 2 micro-op types def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { let Latency = 64; let NumMicroOps = 2; let ResourceCycles = [32, 32]; } def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI, A57UnitL]> { let Latency = 6; let NumMicroOps = 2; } def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV, A57UnitX]> { let Latency = 7; let NumMicroOps = 2; } def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL, A57UnitV]> { let Latency = 8; let NumMicroOps = 2; } def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 2; } def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { let Latency = 8; let NumMicroOps = 2; } def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> { let Latency = 6; let NumMicroOps = 2; } def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 6; let NumMicroOps = 2; } def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { let Latency = 6; let NumMicroOps = 2; } def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI, A57UnitL]> { let Latency = 5; let NumMicroOps = 2; } def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 5; let NumMicroOps = 2; } def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { let Latency = 5; let NumMicroOps = 2; } def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL, A57UnitV]> { let Latency = 10; let NumMicroOps = 2; } def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; let NumMicroOps = 2; } def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB, A57UnitI]> { let Latency = 1; let NumMicroOps = 2; } def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI, A57UnitS]> { let Latency = 1; let NumMicroOps = 2; } def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB, A57UnitI]> { let Latency = 2; let NumMicroOps = 2; } def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> { let Latency = 2; let NumMicroOps = 2; } def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 2; let NumMicroOps = 2; } def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> { let Latency = 34; let NumMicroOps = 2; let ResourceCycles = [17, 17]; } def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI, A57UnitM]> { let Latency = 3; let NumMicroOps = 2; } def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI, A57UnitS]> { let Latency = 3; let NumMicroOps = 2; } def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS, A57UnitV]> { let Latency = 3; let NumMicroOps = 2; } def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 3; let NumMicroOps = 2; } def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI, A57UnitL]> { let Latency = 4; let NumMicroOps = 2; } def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> { let Latency = 4; let NumMicroOps = 2; } //===----------------------------------------------------------------------===// // Define Generic 3 micro-op types def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { let Latency = 10; let NumMicroOps = 3; } def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS]> { let Latency = 2; let NumMicroOps = 3; } def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitV]> { let Latency = 3; let NumMicroOps = 3; } def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM, A57UnitS, A57UnitS]> { let Latency = 3; let NumMicroOps = 3; } def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> { let Latency = 3; let NumMicroOps = 3; } def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitV]> { let Latency = 3; let NumMicroOps = 3; } def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL]> { let Latency = 5; let NumMicroOps = 3; } def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL]> { let Latency = 6; let NumMicroOps = 3; } def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { let Latency = 6; let NumMicroOps = 3; } def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> { let Latency = 7; let NumMicroOps = 3; } def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitV]> { let Latency = 8; let NumMicroOps = 3; } def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL, A57UnitV, A57UnitV]> { let Latency = 8; let NumMicroOps = 3; } def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { let Latency = 8; let NumMicroOps = 3; } def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 3; } //===----------------------------------------------------------------------===// // Define Generic 4 micro-op types def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, A57UnitS, A57UnitS]> { let Latency = 2; let NumMicroOps = 4; } def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI, A57UnitS, A57UnitS]> { let Latency = 3; let NumMicroOps = 4; } def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 3; let NumMicroOps = 4; } def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitV]> { let Latency = 3; let NumMicroOps = 4; } def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 4; let NumMicroOps = 4; } def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitL]> { let Latency = 7; let NumMicroOps = 4; } def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI, A57UnitL, A57UnitL]> { let Latency = 5; let NumMicroOps = 4; } def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitV, A57UnitV]> { let Latency = 8; let NumMicroOps = 4; } def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, A57UnitL]> { let Latency = 8; let NumMicroOps = 4; } def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 4; } def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 4; } def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 12; let NumMicroOps = 4; } //===----------------------------------------------------------------------===// // Define Generic 5 micro-op types def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV]> { let Latency = 3; let NumMicroOps = 5; } def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitL, A57UnitL]> { let Latency = 8; let NumMicroOps = 5; } def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 4; let NumMicroOps = 5; } def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 5; } def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 5; } def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 5; } def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 5; } //===----------------------------------------------------------------------===// // Define Generic 6 micro-op types def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV]> { let Latency = 3; let NumMicroOps = 6; } def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 4; let NumMicroOps = 6; } def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV]> { let Latency = 4; let NumMicroOps = 6; } def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 6; let NumMicroOps = 6; } def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 6; } def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 6; } def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 6; } //===----------------------------------------------------------------------===// // Define Generic 7 micro-op types def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 10; let NumMicroOps = 7; } def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV]> { let Latency = 4; let NumMicroOps = 7; } def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 6; let NumMicroOps = 7; } def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 9; let NumMicroOps = 7; } def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 12; let NumMicroOps = 7; } //===----------------------------------------------------------------------===// // Define Generic 8 micro-op types def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 10; let NumMicroOps = 8; } def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 11; let NumMicroOps = 8; } def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 8; let NumMicroOps = 8; } //===----------------------------------------------------------------------===// // Define Generic 9 micro-op types def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS]> { let Latency = 8; let NumMicroOps = 9; } def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitL, A57UnitL, A57UnitL, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 11; let NumMicroOps = 9; } def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 15; let NumMicroOps = 9; } //===----------------------------------------------------------------------===// // Define Generic 10 micro-op types def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 6; let NumMicroOps = 10; } //===----------------------------------------------------------------------===// // Define Generic 11 micro-op types def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 6; let NumMicroOps = 11; } //===----------------------------------------------------------------------===// // Define Generic 12 micro-op types def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 8; let NumMicroOps = 12; } //===----------------------------------------------------------------------===// // Define Generic 13 micro-op types def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitS, A57UnitV, A57UnitV, A57UnitV, A57UnitV]> { let Latency = 8; let NumMicroOps = 13; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedCyclone.td000064400000000000000000000733150072674642500262600ustar 00000000000000//=- AArch64SchedCyclone.td - Cyclone Scheduling Definitions -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for AArch64 Cyclone to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// def CycloneModel : SchedMachineModel { let IssueWidth = 6; // 6 micro-ops are dispatched per cycle. let MicroOpBufferSize = 192; // Based on the reorder buffer. let LoadLatency = 4; // Optimistic load latency. let MispredictPenalty = 16; // 14-19 cycles are typical. let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available on Cyclone. // 4 integer pipes def CyUnitI : ProcResource<4> { let BufferSize = 48; } // 2 branch units: I[0..1] def CyUnitB : ProcResource<2> { let Super = CyUnitI; let BufferSize = 24; } // 1 indirect-branch unit: I[0] def CyUnitBR : ProcResource<1> { let Super = CyUnitB; } // 2 shifter pipes: I[2..3] // When an instruction consumes a CyUnitIS, it also consumes a CyUnitI def CyUnitIS : ProcResource<2> { let Super = CyUnitI; let BufferSize = 24; } // 1 mul pipe: I[0] def CyUnitIM : ProcResource<1> { let Super = CyUnitBR; let BufferSize = 32; } // 1 div pipe: I[1] def CyUnitID : ProcResource<1> { let Super = CyUnitB; let BufferSize = 16; } // 1 integer division unit. This is driven by the ID pipe, but only // consumes the pipe for one cycle at issue and another cycle at writeback. def CyUnitIntDiv : ProcResource<1>; // 2 ld/st pipes. def CyUnitLS : ProcResource<2> { let BufferSize = 28; } // 3 fp/vector pipes. def CyUnitV : ProcResource<3> { let BufferSize = 48; } // 2 fp/vector arithmetic and multiply pipes: V[0-1] def CyUnitVM : ProcResource<2> { let Super = CyUnitV; let BufferSize = 32; } // 1 fp/vector division/sqrt pipe: V[2] def CyUnitVD : ProcResource<1> { let Super = CyUnitV; let BufferSize = 16; } // 1 fp compare pipe: V[0] def CyUnitVC : ProcResource<1> { let Super = CyUnitVM; let BufferSize = 16; } // 2 fp division/square-root units. These are driven by the VD pipe, // but only consume the pipe for one cycle at issue and a cycle at writeback. def CyUnitFloatDiv : ProcResource<2>; //===----------------------------------------------------------------------===// // Define scheduler read/write resources and latency on Cyclone. // This mirrors sections 7.7-7.9 of the Tuning Guide v1.0.1. let SchedModel = CycloneModel in { //--- // 7.8.1. Moves //--- // A single nop micro-op (uX). def WriteX : SchedWriteRes<[]> { let Latency = 0; } // Move zero is a register rename (to machine register zero). // The move is replaced by a single nop micro-op. // MOVZ Rd, #0 // AND Rd, Rzr, #imm def WriteZPred : SchedPredicate<[{TII->isGPRZero(*MI)}]>; def WriteImmZ : SchedWriteVariant<[ SchedVar, SchedVar]>; def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>; // Move GPR is a register rename and single nop micro-op. // ORR Xd, XZR, Xm // ADD Xd, Xn, #0 def WriteIMovPred : SchedPredicate<[{TII->isGPRCopy(*MI)}]>; def WriteVMovPred : SchedPredicate<[{TII->isFPRCopy(*MI)}]>; def WriteMov : SchedWriteVariant<[ SchedVar, SchedVar, SchedVar]>; def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>; // Move non-zero immediate is an integer ALU op. // MOVN,MOVZ,MOVK def : WriteRes; //--- // 7.8.2-7.8.5. Arithmetic and Logical, Comparison, Conditional, // Shifts and Bitfield Operations //--- // ADR,ADRP // ADD(S)ri,SUB(S)ri,AND(S)ri,EORri,ORRri // ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr // ADC(S),SBC(S) // Aliases: CMN, CMP, TST // // Conditional operations. // CCMNi,CCMPi,CCMNr,CCMPr, // CSEL,CSINC,CSINV,CSNEG // // Bit counting and reversal operations. // CLS,CLZ,RBIT,REV,REV16,REV32 def : WriteRes; // ADD with shifted register operand is a single micro-op that // consumes a shift pipeline for two cycles. // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs // EXAMPLE: ADDrs Xn, Xm LSL #imm def : WriteRes { let Latency = 2; let ResourceCycles = [2]; } // ADD with extended register operand is the same as shifted reg operand. // ADD(S)re,SUB(S)re // EXAMPLE: ADDXre Xn, Xm, UXTB #1 def : WriteRes { let Latency = 2; let ResourceCycles = [2]; } // Variable shift and bitfield operations. // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM def : WriteRes; // EXTR Shifts a pair of registers and requires two micro-ops. // The second micro-op is delayed, as modeled by ReadExtrHi. // EXTR Xn, Xm, #imm def : WriteRes { let Latency = 2; let NumMicroOps = 2; } // EXTR's first register read is delayed by one cycle, effectively // shortening its writer's latency. // EXTR Xn, Xm, #imm def : ReadAdvance; //--- // 7.8.6. Multiplies //--- // MUL/MNEG are aliases for MADD/MSUB. // MADDW,MSUBW,SMADDL,SMSUBL,UMADDL,UMSUBL def : WriteRes { let Latency = 4; } // MADDX,MSUBX,SMULH,UMULH def : WriteRes { let Latency = 5; } //--- // 7.8.7. Divide //--- // 32-bit divide takes 7-13 cycles. 10 cycles covers a 20-bit quotient. // The ID pipe is consumed for 2 cycles: issue and writeback. // SDIVW,UDIVW def : WriteRes { let Latency = 10; let ResourceCycles = [2, 10]; } // 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient. // The ID pipe is consumed for 2 cycles: issue and writeback. // SDIVX,UDIVX def : WriteRes { let Latency = 13; let ResourceCycles = [2, 13]; } //--- // 7.8.8,7.8.10. Load/Store, single element //--- // Integer loads take 4 cycles and use one LS unit for one cycle. def : WriteRes { let Latency = 4; } // Store-load forwarding is 4 cycles. // // Note: The store-exclusive sequence incorporates this // latency. However, general heuristics should not model the // dependence between a store and subsequent may-alias load because // hardware speculation works. def : WriteRes { let Latency = 4; } // Load from base address plus an optionally scaled register offset. // Rt latency is latency WriteIS + WriteLD. // EXAMPLE: LDR Xn, Xm [, lsl 3] def CyWriteLDIdx : SchedWriteVariant<[ SchedVar, // Load from scaled register. SchedVar]>; // Load from register offset. def : SchedAlias; // Map AArch64->Cyclone type. // EXAMPLE: STR Xn, Xm [, lsl 3] def CyWriteSTIdx : SchedWriteVariant<[ SchedVar, // Store to scaled register. SchedVar]>; // Store to register offset. def : SchedAlias; // Map AArch64->Cyclone type. // Read the (unshifted) base register Xn in the second micro-op one cycle later. // EXAMPLE: LDR Xn, Xm [, lsl 3] def ReadBaseRS : SchedReadAdvance<1>; def CyReadAdrBase : SchedReadVariant<[ SchedVar, // Read base reg after shifting offset. SchedVar]>; // Read base reg with no shift. def : SchedAlias; // Map AArch64->Cyclone type. //--- // 7.8.9,7.8.11. Load/Store, paired //--- // Address pre/post increment is a simple ALU op with one cycle latency. def : WriteRes; // LDP high register write is fused with the load, but a nop micro-op remains. def : WriteRes { let Latency = 4; } // STP is a vector op and store, except for QQ, which is just two stores. def : SchedAlias; def : InstRW<[WriteST, WriteST], (instrs STPQi)>; //--- // 7.8.13. Branches //--- // Branches take a single micro-op. // The misprediction penalty is defined as a SchedMachineModel property. def : WriteRes {let Latency = 0;} def : WriteRes {let Latency = 0;} //--- // 7.8.14. Never-issued Instructions, Barrier and Hint Operations //--- // NOP,SEV,SEVL,WFE,WFI,YIELD def : WriteRes {let Latency = 0;} // ISB def : InstRW<[WriteI], (instrs ISB)>; // SLREX,DMB,DSB def : WriteRes; // System instructions get an invalid latency because the latency of // other operations across them is meaningless. def : WriteRes {let Latency = -1;} //===----------------------------------------------------------------------===// // 7.9 Vector Unit Instructions // Simple vector operations take 2 cycles. def : WriteRes {let Latency = 2;} // Define some longer latency vector op types for Cyclone. def CyWriteV3 : SchedWriteRes<[CyUnitV]> {let Latency = 3;} def CyWriteV4 : SchedWriteRes<[CyUnitV]> {let Latency = 4;} def CyWriteV5 : SchedWriteRes<[CyUnitV]> {let Latency = 5;} def CyWriteV6 : SchedWriteRes<[CyUnitV]> {let Latency = 6;} // Simple floating-point operations take 2 cycles. def : WriteRes {let Latency = 2;} //--- // 7.9.1 Vector Moves //--- // TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently // generates expensive int-float conversion instead: // FMOVDi Dd, #0.0 // FMOVv2f64ns Vd.2d, #0.0 // FMOVSi,FMOVDi def : WriteRes {let Latency = 2;} // MOVI,MVNI are WriteV // FMOVv2f32ns,FMOVv2f64ns,FMOVv4f32ns are WriteV // Move FPR is a register rename and single nop micro-op. // ORR.16b Vd,Vn,Vn // COPY is handled above in the WriteMov Variant. def WriteVMov : SchedWriteVariant<[ SchedVar, SchedVar]>; def : InstRW<[WriteVMov], (instrs ORRv16i8)>; // FMOVSr,FMOVDr are WriteF. // MOV V,V is a WriteV. // CPY D,V[x] is a WriteV // INS V[x],V[y] is a WriteV. // FMOVWSr,FMOVXDr,FMOVXDHighr def : WriteRes { let Latency = 5; } // FMOVSWr,FMOVDXr def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>; // INS V[x],R def CyWriteCopyToFPR : WriteSequence<[WriteVLD, WriteV]>; def : InstRW<[CyWriteCopyToFPR], (instregex "INSv")>; // SMOV,UMOV R,V[x] def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>; def : InstRW<[CyWriteCopyToGPR], (instregex "SMOVv","UMOVv")>; // DUP V,R def : InstRW<[CyWriteCopyToFPR], (instregex "DUPv")>; // DUP V,V[x] is a WriteV. //--- // 7.9.2 Integer Arithmetic, Logical, and Comparisons //--- // BIC,ORR V,#imm are WriteV def : InstRW<[CyWriteV3], (instregex "ABSv")>; // MVN,NEG,NOT are WriteV def : InstRW<[CyWriteV3], (instregex "SQABSv","SQNEGv")>; // ADDP is a WriteV. def CyWriteVADDLP : SchedWriteRes<[CyUnitV]> {let Latency = 2;} def : InstRW<[CyWriteVADDLP], (instregex "SADDLPv","UADDLPv")>; def : InstRW<[CyWriteV3], (instregex "ADDVv","SMAXVv","UMAXVv","SMINVv","UMINVv")>; def : InstRW<[CyWriteV3], (instregex "SADDLV","UADDLV")>; // ADD,SUB are WriteV // Forward declare. def CyWriteVABD : SchedWriteRes<[CyUnitV]> {let Latency = 3;} // Add/Diff and accumulate uses the vector multiply unit. def CyWriteVAccum : SchedWriteRes<[CyUnitVM]> {let Latency = 3;} def CyReadVAccum : SchedReadAdvance<1, [CyWriteVAccum, CyWriteVADDLP, CyWriteVABD]>; def : InstRW<[CyWriteVAccum, CyReadVAccum], (instregex "SADALP","UADALP")>; def : InstRW<[CyWriteVAccum, CyReadVAccum], (instregex "SABAv","UABAv","SABALv","UABALv")>; def : InstRW<[CyWriteV3], (instregex "SQADDv","SQSUBv","UQADDv","UQSUBv")>; def : InstRW<[CyWriteV3], (instregex "SUQADDv","USQADDv")>; def : InstRW<[CyWriteV4], (instregex "ADDHNv","RADDHNv", "RSUBHNv", "SUBHNv")>; // WriteV includes: // AND,BIC,CMTST,EOR,ORN,ORR // ADDP // SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD // SADDL,SSUBL,UADDL,USUBL // SADDW,SSUBW,UADDW,USUBW def : InstRW<[CyWriteV3], (instregex "CMEQv","CMGEv","CMGTv", "CMLEv","CMLTv", "CMHIv","CMHSv")>; def : InstRW<[CyWriteV3], (instregex "SMAXv","SMINv","UMAXv","UMINv", "SMAXPv","SMINPv","UMAXPv","UMINPv")>; def : InstRW<[CyWriteVABD], (instregex "SABDv","UABDv", "SABDLv","UABDLv")>; //--- // 7.9.3 Floating Point Arithmetic and Comparisons //--- // FABS,FNEG are WriteF def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>; def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>; def : InstRW<[CyWriteV3], (instregex "FMAXPv2i","FMAXNMPv2i", "FMINPv2i","FMINNMPv2i")>; def : InstRW<[CyWriteV4], (instregex "FMAXVv","FMAXNMVv","FMINVv","FMINNMVv")>; def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32, FSUBSrr,FSUBv2f32,FSUBv4f32, FADDPv2f32,FADDPv4f32, FABD32,FABDv2f32,FABDv4f32)>; def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64, FSUBDrr,FSUBv2f64, FADDPv2f64, FABD64,FABDv2f64)>; def : InstRW<[CyWriteV3], (instregex "FCMEQ","FCMGT","FCMLE","FCMLT")>; def : InstRW<[CyWriteV3], (instregex "FACGE","FACGT", "FMAXS","FMAXD","FMAXv", "FMINS","FMIND","FMINv", "FMAXNMS","FMAXNMD","FMAXNMv", "FMINNMS","FMINNMD","FMINNMv", "FMAXPv2f","FMAXPv4f", "FMINPv2f","FMINPv4f", "FMAXNMPv2f","FMAXNMPv4f", "FMINNMPv2f","FMINNMPv4f")>; // FCMP,FCMPE,FCCMP,FCCMPE def : WriteRes {let Latency = 4;} // FCSEL is a WriteF. //--- // 7.9.4 Shifts and Bitfield Operations //--- // SHL is a WriteV def CyWriteVSHR : SchedWriteRes<[CyUnitV]> {let Latency = 2;} def : InstRW<[CyWriteVSHR], (instregex "SSHRv","USHRv")>; def CyWriteVSRSHR : SchedWriteRes<[CyUnitV]> {let Latency = 3;} def : InstRW<[CyWriteVSRSHR], (instregex "SRSHRv","URSHRv")>; // Shift and accumulate uses the vector multiply unit. def CyWriteVShiftAcc : SchedWriteRes<[CyUnitVM]> {let Latency = 3;} def CyReadVShiftAcc : SchedReadAdvance<1, [CyWriteVShiftAcc, CyWriteVSHR, CyWriteVSRSHR]>; def : InstRW<[CyWriteVShiftAcc, CyReadVShiftAcc], (instregex "SRSRAv","SSRAv","URSRAv","USRAv")>; // SSHL,USHL are WriteV. def : InstRW<[CyWriteV3], (instregex "SRSHLv","URSHLv")>; // SQSHL,SQSHLU,UQSHL are WriteV. def : InstRW<[CyWriteV3], (instregex "SQRSHLv","UQRSHLv")>; // WriteV includes: // SHLL,SSHLL,USHLL // SLI,SRI // BIF,BIT,BSL // EXT // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN // XTN2 def : InstRW<[CyWriteV4], (instregex "RSHRNv","SHRNv", "SQRSHRNv","SQRSHRUNv","SQSHRNv","SQSHRUNv", "UQRSHRNv","UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>; //--- // 7.9.5 Multiplication //--- def CyWriteVMul : SchedWriteRes<[CyUnitVM]> { let Latency = 4;} def : InstRW<[CyWriteVMul], (instregex "MULv","SMULLv","UMULLv", "SQDMULLv","SQDMULHv","SQRDMULHv")>; // FMUL,FMULX,FNMUL default to WriteFMul. def : WriteRes { let Latency = 4;} def CyWriteV64Mul : SchedWriteRes<[CyUnitVM]> { let Latency = 5;} def : InstRW<[CyWriteV64Mul], (instrs FMULDrr,FMULv2f64,FMULv2i64_indexed, FNMULDrr,FMULX64,FMULXv2f64,FMULXv2i64_indexed)>; def CyReadVMulAcc : SchedReadAdvance<1, [CyWriteVMul, CyWriteV64Mul]>; def : InstRW<[CyWriteVMul, CyReadVMulAcc], (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL", "SQDMLAL","SQDMLSL")>; def CyWriteSMul : SchedWriteRes<[CyUnitVM]> { let Latency = 8;} def CyWriteDMul : SchedWriteRes<[CyUnitVM]> { let Latency = 10;} def CyReadSMul : SchedReadAdvance<4, [CyWriteSMul]>; def CyReadDMul : SchedReadAdvance<5, [CyWriteDMul]>; def : InstRW<[CyWriteSMul, CyReadSMul], (instrs FMADDSrrr,FMSUBSrrr,FNMADDSrrr,FNMSUBSrrr, FMLAv2f32,FMLAv4f32, FMLAv1i32_indexed,FMLAv1i64_indexed,FMLAv2i32_indexed)>; def : InstRW<[CyWriteDMul, CyReadDMul], (instrs FMADDDrrr,FMSUBDrrr,FNMADDDrrr,FNMSUBDrrr, FMLAv2f64,FMLAv2i64_indexed, FMLSv2f64,FMLSv2i64_indexed)>; def CyWritePMUL : SchedWriteRes<[CyUnitVD]> { let Latency = 3; } def : InstRW<[CyWritePMUL], (instregex "PMULv", "PMULLv")>; //--- // 7.9.6 Divide and Square Root //--- // FDIV,FSQRT // TODO: Add 64-bit variant with 19 cycle latency. // TODO: Specialize FSQRT for longer latency. def : WriteRes { let Latency = 17; let ResourceCycles = [2, 17]; } def : InstRW<[CyWriteV4], (instregex "FRECPEv","FRECPXv","URECPEv","URSQRTEv")>; def WriteFRSQRTE : SchedWriteRes<[CyUnitVM]> { let Latency = 4; } def : InstRW<[WriteFRSQRTE], (instregex "FRSQRTEv")>; def WriteFRECPS : SchedWriteRes<[CyUnitVM]> { let Latency = 8; } def WriteFRSQRTS : SchedWriteRes<[CyUnitVM]> { let Latency = 10; } def : InstRW<[WriteFRECPS], (instregex "FRECPSv")>; def : InstRW<[WriteFRSQRTS], (instregex "FRSQRTSv")>; //--- // 7.9.7 Integer-FP Conversions //--- // FCVT lengthen f16/s32 def : InstRW<[WriteV], (instrs FCVTSHr,FCVTDHr,FCVTDSr)>; // FCVT,FCVTN,FCVTXN // SCVTF,UCVTF V,V // FRINT(AIMNPXZ) V,V def : WriteRes {let Latency = 4;} // SCVT/UCVT S/D, Rd = VLD5+V4: 9 cycles. def CyWriteCvtToFPR : WriteSequence<[WriteVLD, CyWriteV4]>; def : InstRW<[CyWriteCopyToFPR], (instregex "FCVT[AMNPZ][SU][SU][WX][SD]r")>; // FCVT Rd, S/D = V6+LD4: 10 cycles def CyWriteCvtToGPR : WriteSequence<[CyWriteV6, WriteLD]>; def : InstRW<[CyWriteCvtToGPR], (instregex "[SU]CVTF[SU][WX][SD]r")>; // FCVTL is a WriteV //--- // 7.9.8-7.9.10 Cryptography, Data Transposition, Table Lookup //--- def CyWriteCrypto2 : SchedWriteRes<[CyUnitVD]> {let Latency = 2;} def : InstRW<[CyWriteCrypto2], (instrs AESIMCrr, AESMCrr, SHA1Hrr, AESDrr, AESErr, SHA1SU1rr, SHA256SU0rr, SHA1SU0rrr)>; def CyWriteCrypto3 : SchedWriteRes<[CyUnitVD]> {let Latency = 3;} def : InstRW<[CyWriteCrypto3], (instrs SHA256SU1rrr)>; def CyWriteCrypto6 : SchedWriteRes<[CyUnitVD]> {let Latency = 6;} def : InstRW<[CyWriteCrypto6], (instrs SHA1Crrr, SHA1Mrrr, SHA1Prrr, SHA256Hrrr,SHA256H2rrr)>; // TRN,UZP,ZUP are WriteV. // TBL,TBX are WriteV. //--- // 7.9.11-7.9.14 Load/Store, single element and paired //--- // Loading into the vector unit takes 5 cycles vs 4 for integer loads. def : WriteRes { let Latency = 5; } // Store-load forwarding is 4 cycles. def : WriteRes { let Latency = 4; } // WriteVLDPair/VSTPair sequences are expanded by the target description. //--- // 7.9.15 Load, element operations //--- // Only the first WriteVLD and WriteAdr for writeback matches def operands. // Subsequent WriteVLDs consume resources. Since all loaded values have the // same latency, this is acceptable. // Vd is read 5 cycles after issuing the vector load. def : ReadAdvance; def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>; // Register writes from the load's high half are fused micro-ops. def : InstRW<[WriteVLD], (instregex "LD1Twov(8b|4h|2s|1d)$")>; def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVLD, WriteVLD], (instregex "LD1Twov(16b|8h|4s|2d)$")>; def : InstRW<[WriteVLD, WriteAdr, WriteVLD], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLD, WriteVLD], (instregex "LD1Threev(8b|4h|2s|1d)$")>; def : InstRW<[WriteVLD, WriteAdr, WriteVLD], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVLD, WriteVLD, WriteVLD], (instregex "LD1Threev(16b|8h|4s|2d)$")>; def : InstRW<[WriteVLD, WriteAdr, WriteVLD, WriteVLD], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLD, WriteVLD], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[WriteVLD, WriteAdr, WriteVLD], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVLD, WriteVLD, WriteVLD, WriteVLD], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[WriteVLD, WriteAdr, WriteVLD, WriteVLD, WriteVLD], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD], (instregex "LD1i(8|16|32)$")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr], (instregex "LD1i(8|16|32)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD], (instrs LD1i64)>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr],(instrs LD1i64_POST)>; def : InstRW<[WriteVLDShuffle], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[WriteVLDShuffle, WriteV], (instregex "LD2Twov(8b|4h|2s)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV], (instregex "LD2Twov(8b|4h|2s)_POST$")>; def : InstRW<[WriteVLDShuffle, WriteVLDShuffle], (instregex "LD2Twov(16b|8h|4s|2d)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV], (instregex "LD2i(8|16|32)$")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV], (instregex "LD2i(8|16|32)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV], (instregex "LD2i64$")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV], (instregex "LD2i64_POST")>; def : InstRW<[WriteVLDShuffle, WriteV], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV], (instregex "LD3Threev(8b|4h|2s)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV], (instregex "LD3Threev(8b|4h|2s)_POST")>; def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteVLDShuffle], (instregex "LD3Threev(16b|8h|4s|2d)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteVLDShuffle], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV, WriteV], (instregex "LD3i(8|16|32)$")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV, WriteV], (instregex "LD3i(8|16|32)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteV], (instregex "LD3i64$")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteV], (instregex "LD3i64_POST")>; def : InstRW<[WriteVLDShuffle, WriteV, WriteV], (instregex "LD3Rv(8b|4h|2s|16b|8h|4s)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV, WriteV], (instregex "LD3Rv(8b|4h|2s|16b|8h|4s)_POST")>; def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV], (instrs LD3Rv1d,LD3Rv2d)>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV], (instrs LD3Rv1d_POST,LD3Rv2d_POST)>; def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV, WriteV], (instregex "LD4Fourv(8b|4h|2s)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV, WriteV], (instregex "LD4Fourv(8b|4h|2s)_POST")>; def : InstRW<[WriteVLDPairShuffle, WriteVLDPairShuffle, WriteVLDPairShuffle, WriteVLDPairShuffle], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; def : InstRW<[WriteVLDPairShuffle, WriteAdr, WriteVLDPairShuffle, WriteVLDPairShuffle, WriteVLDPairShuffle], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteV, WriteV, WriteV], (instregex "LD4i(8|16|32)$")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteV, WriteV, WriteV], (instregex "LD4i(8|16|32)_POST")>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteVLDShuffle, WriteV, WriteV], (instrs LD4i64)>; def : InstRW<[WriteVLDShuffle, ReadVLD, WriteAdr, WriteVLDShuffle, WriteV], (instrs LD4i64_POST)>; def : InstRW<[WriteVLDShuffle, WriteV, WriteV, WriteV], (instregex "LD4Rv(8b|4h|2s|16b|8h|4s)$")>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteV, WriteV, WriteV], (instregex "LD4Rv(8b|4h|2s|16b|8h|4s)_POST")>; def : InstRW<[WriteVLDShuffle, WriteVLDShuffle, WriteV, WriteV], (instrs LD4Rv1d,LD4Rv2d)>; def : InstRW<[WriteVLDShuffle, WriteAdr, WriteVLDShuffle, WriteV, WriteV], (instrs LD4Rv1d_POST,LD4Rv2d_POST)>; //--- // 7.9.16 Store, element operations //--- // Only the WriteAdr for writeback matches a def operands. // Subsequent WriteVLDs only consume resources. def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVST], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTShuffle], (instregex "ST1Twov(8b|4h|2s|1d)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVST, WriteVST], (instregex "ST1Twov(16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVST, WriteVST], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTShuffle, WriteVST], (instregex "ST1Threev(8b|4h|2s|1d)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVST], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVST, WriteVST, WriteVST], (instregex "ST1Threev(16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVST, WriteVST, WriteVST], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVST, WriteVST, WriteVST, WriteVST], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVST, WriteVST, WriteVST, WriteVST], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTShuffle], (instregex "ST1i(8|16|32)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST1i(8|16|32)_POST")>; def : InstRW<[WriteVSTShuffle], (instrs ST1i64)>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instrs ST1i64_POST)>; def : InstRW<[WriteVSTShuffle], (instregex "ST2Twov(8b|4h|2s)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST2Twov(8b|4h|2s)_POST")>; def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instregex "ST2Twov(16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTShuffle], (instregex "ST2i(8|16|32)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST2i(8|16|32)_POST")>; def : InstRW<[WriteVSTShuffle], (instrs ST2i64)>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instrs ST2i64_POST)>; def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instregex "ST3Threev(8b|4h|2s)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], (instregex "ST3Threev(8b|4h|2s)_POST")>; def : InstRW<[WriteVSTShuffle, WriteVSTShuffle, WriteVSTShuffle], (instregex "ST3Threev(16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle, WriteVSTShuffle], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTShuffle], (instregex "ST3i(8|16|32)$")>; def : InstRW<[WriteAdr, WriteVSTShuffle], (instregex "ST3i(8|16|32)_POST")>; def :InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST3i64)>; def :InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle], (instrs ST3i64_POST)>; def : InstRW<[WriteVSTPairShuffle, WriteVSTPairShuffle], (instregex "ST4Fourv(8b|4h|2s|1d)$")>; def : InstRW<[WriteAdr, WriteVSTPairShuffle, WriteVSTPairShuffle], (instregex "ST4Fourv(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVSTPairShuffle, WriteVSTPairShuffle, WriteVSTPairShuffle, WriteVSTPairShuffle], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; def : InstRW<[WriteAdr, WriteVSTPairShuffle, WriteVSTPairShuffle, WriteVSTPairShuffle, WriteVSTPairShuffle], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[WriteVSTPairShuffle], (instregex "ST4i(8|16|32)$")>; def : InstRW<[WriteAdr, WriteVSTPairShuffle], (instregex "ST4i(8|16|32)_POST")>; def : InstRW<[WriteVSTShuffle, WriteVSTShuffle], (instrs ST4i64)>; def : InstRW<[WriteAdr, WriteVSTShuffle, WriteVSTShuffle],(instrs ST4i64_POST)>; // Atomic operations are not supported. def : WriteRes { let Unsupported = 1; } //--- // Unused SchedRead types //--- def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; } // SchedModel = CycloneModel capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedExynosM1.td000064400000000000000000001241320072674642500263410ustar 00000000000000//=- AArch64SchedExynosM1.td - Samsung Exynos M1 Sched Defs --*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for the Samsung Exynos M1 to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // The Exynos-M1 is a traditional superscalar microprocessor with a // 4-wide in-order stage for decode and dispatch and a wider issue stage. // The execution units and loads and stores are out-of-order. def ExynosM1Model : SchedMachineModel { let IssueWidth = 4; // Up to 4 uops per cycle. let MicroOpBufferSize = 96; // ROB size. let LoopMicroOpBufferSize = 24; // Based on the instruction queue size. let LoadLatency = 4; // Optimistic load cases. let MispredictPenalty = 14; // Minimum branch misprediction penalty. let CompleteModel = 1; // Use the default model otherwise. list UnsupportedFeatures = [HasSVE]; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available on the Exynos-M1, // which has 9 pipelines, each with its own queue with out-of-order dispatch. let SchedModel = ExynosM1Model in { def M1UnitA : ProcResource<2>; // Simple integer def M1UnitC : ProcResource<1>; // Simple and complex integer def M1UnitD : ProcResource<1>; // Integer division (inside C, serialized) def M1UnitB : ProcResource<2>; // Branch def M1UnitL : ProcResource<1>; // Load def M1UnitS : ProcResource<1>; // Store def M1PipeF0 : ProcResource<1>; // FP #0 let Super = M1PipeF0 in { def M1UnitFMAC : ProcResource<1>; // FP multiplication def M1UnitNAL0 : ProcResource<1>; // Simple vector def M1UnitNMISC : ProcResource<1>; // Miscellanea def M1UnitFCVT : ProcResource<1>; // FP conversion def M1UnitNCRYPT : ProcResource<1>; // Cryptographic } def M1PipeF1 : ProcResource<1>; // FP #1 let Super = M1PipeF1 in { def M1UnitFADD : ProcResource<1>; // Simple FP def M1UnitNAL1 : ProcResource<1>; // Simple vector def M1UnitFVAR : ProcResource<1>; // FP division & square root (serialized) def M1UnitFST : ProcResource<1>; // FP store } def M1UnitALU : ProcResGroup<[M1UnitA, M1UnitC]>; // All integer def M1UnitNALU : ProcResGroup<[M1UnitNAL0, M1UnitNAL1]>; // All simple vector //===----------------------------------------------------------------------===// // Predicates. def M1BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR && MI->getOperand(0).getReg() != AArch64::LR}]>; def M1ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>; //===----------------------------------------------------------------------===// // Coarse scheduling model. def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; } def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; } def M1WriteAA : SchedWriteRes<[M1UnitALU]> { let Latency = 2; let ResourceCycles = [2]; } def M1WriteAB : SchedWriteRes<[M1UnitALU, M1UnitC]> { let Latency = 1; let NumMicroOps = 2; } def M1WriteAC : SchedWriteRes<[M1UnitALU, M1UnitALU, M1UnitC]> { let Latency = 2; let NumMicroOps = 3; } def M1WriteAD : SchedWriteRes<[M1UnitALU, M1UnitC]> { let Latency = 2; let NumMicroOps = 2; } def M1WriteAX : SchedWriteVariant<[SchedVar, SchedVar]>; def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; } def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; } def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; } def M1WriteBX : SchedWriteVariant<[SchedVar, SchedVar]>; def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; } def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; } def M1WriteLA : SchedWriteRes<[M1UnitL]> { let Latency = 6; let ResourceCycles = [2]; } def M1WriteLB : SchedWriteRes<[M1UnitL, M1UnitA]> { let Latency = 4; let NumMicroOps = 2; } def M1WriteLC : SchedWriteRes<[M1UnitL, M1UnitA]> { let Latency = 5; let NumMicroOps = 2; } def M1WriteLD : SchedWriteRes<[M1UnitL, M1UnitA]> { let Latency = 6; let NumMicroOps = 2; let ResourceCycles = [2, 1]; } def M1WriteLH : SchedWriteRes<[]> { let Latency = 5; let NumMicroOps = 0; } def M1WriteLX : SchedWriteVariant<[SchedVar, SchedVar]>; def M1WriteLY : SchedWriteVariant<[SchedVar, SchedVar]>; def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; } def M1WriteS3 : SchedWriteRes<[M1UnitS]> { let Latency = 3; } def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; } def M1WriteSA : SchedWriteRes<[M1UnitS, M1UnitFST, M1UnitS, M1UnitFST]> { let Latency = 1; let NumMicroOps = 2; } def M1WriteSB : SchedWriteRes<[M1UnitS, M1UnitFST, M1UnitA]> { let Latency = 3; let NumMicroOps = 2; } def M1WriteSC : SchedWriteRes<[M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitA]> { let Latency = 3; let NumMicroOps = 3; } def M1WriteSD : SchedWriteRes<[M1UnitS, M1UnitFST, M1UnitA]> { let Latency = 1; let NumMicroOps = 2; } def M1WriteSE : SchedWriteRes<[M1UnitS, M1UnitA]> { let Latency = 2; let NumMicroOps = 2; } def M1WriteSX : SchedWriteVariant<[SchedVar, SchedVar]>; def M1WriteSY : SchedWriteVariant<[SchedVar, SchedVar]>; def M1ReadAdrBase : SchedReadVariant<[SchedVar, SchedVar]>; // Branch instructions. def : WriteRes { let Latency = 0; } def : WriteRes { let Latency = 1; } // Arithmetic and logical integer instructions. def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } // Move instructions. def : WriteRes { let Latency = 1; } // Divide and multiply instructions. def : WriteRes { let Latency = 13; let ResourceCycles = [1, 13]; } def : WriteRes { let Latency = 21; let ResourceCycles = [1, 21]; } // TODO: Long multiplication take 5 cycles and also the ALU. def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 4; let ResourceCycles = [2]; } // Miscellaneous instructions. def : WriteRes { let Latency = 2; let NumMicroOps = 2; } // Addressing modes. def : WriteRes { let Latency = 1; let NumMicroOps = 0; } def : SchedAlias; // Load instructions. def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; let NumMicroOps = 0; } def : SchedAlias; // Store instructions. def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : SchedAlias; // FP data instructions. def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 15; let ResourceCycles = [15]; } def : WriteRes { let Latency = 4; } // FP miscellaneous instructions. def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 4; } // FP load instructions. def : WriteRes { let Latency = 5; } // FP store instructions. def : WriteRes { let Latency = 1; let NumMicroOps = 1; } // ASIMD FP instructions. def : WriteRes { let Latency = 3; } // Other miscellaneous instructions. def : WriteRes { let Unsupported = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } //===----------------------------------------------------------------------===// // Fast forwarding. // TODO: Add FP register forwarding rules. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; // TODO: The forwarding for WriteIM32 saves actually 2 cycles. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; //===----------------------------------------------------------------------===// // Finer scheduling model. def M1WriteNEONA : SchedWriteRes<[M1UnitNALU, M1UnitNALU, M1UnitFADD]> { let Latency = 9; let NumMicroOps = 3; } def M1WriteNEONB : SchedWriteRes<[M1UnitNALU, M1UnitFST]> { let Latency = 5; let NumMicroOps = 2;} def M1WriteNEONC : SchedWriteRes<[M1UnitNALU, M1UnitFST]> { let Latency = 6; let NumMicroOps = 2; } def M1WriteNEOND : SchedWriteRes<[M1UnitNALU, M1UnitFST, M1UnitL]> { let Latency = 10; let NumMicroOps = 3; } def M1WriteNEONE : SchedWriteRes<[M1UnitFCVT, M1UnitFST]> { let Latency = 8; let NumMicroOps = 2; } def M1WriteNEONF : SchedWriteRes<[M1UnitFCVT, M1UnitFST, M1UnitL]> { let Latency = 13; let NumMicroOps = 3; } def M1WriteNEONG : SchedWriteRes<[M1UnitNMISC, M1UnitFST]> { let Latency = 6; let NumMicroOps = 2; } def M1WriteNEONH : SchedWriteRes<[M1UnitNALU, M1UnitFST]> { let Latency = 3; let NumMicroOps = 2; } def M1WriteNEONI : SchedWriteRes<[M1UnitFST, M1UnitL]> { let Latency = 9; let NumMicroOps = 2; } def M1WriteNEONJ : SchedWriteRes<[M1UnitNMISC, M1UnitFMAC]> { let Latency = 6; let NumMicroOps = 2; } def M1WriteNEONK : SchedWriteRes<[M1UnitNMISC, M1UnitFMAC]> { let Latency = 7; let NumMicroOps = 2; } def M1WriteNEONL : SchedWriteRes<[M1UnitNALU]> { let Latency = 2; let ResourceCycles = [2]; } def M1WriteFADD3 : SchedWriteRes<[M1UnitFADD]> { let Latency = 3; } def M1WriteFCVT3 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 3; } def M1WriteFCVT4 : SchedWriteRes<[M1UnitFCVT]> { let Latency = 4; } def M1WriteFMAC4 : SchedWriteRes<[M1UnitFMAC]> { let Latency = 4; } def M1WriteFMAC5 : SchedWriteRes<[M1UnitFMAC]> { let Latency = 5; } // TODO def M1WriteFVAR15 : SchedWriteRes<[M1UnitFVAR]> { let Latency = 15; let ResourceCycles = [15]; } def M1WriteFVAR23 : SchedWriteRes<[M1UnitFVAR]> { let Latency = 23; let ResourceCycles = [23]; } def M1WriteNALU1 : SchedWriteRes<[M1UnitNALU]> { let Latency = 1; } def M1WriteNALU2 : SchedWriteRes<[M1UnitNALU]> { let Latency = 2; } def M1WriteNAL11 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 1; } def M1WriteNAL12 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 2; } def M1WriteNAL13 : SchedWriteRes<[M1UnitNAL1]> { let Latency = 3; } def M1WriteNCRYPT1 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; } def M1WriteNCRYPT5 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 5; } def M1WriteNMISC1 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 1; } def M1WriteNMISC2 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 2; } def M1WriteNMISC3 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 3; } def M1WriteNMISC4 : SchedWriteRes<[M1UnitNMISC]> { let Latency = 4; } def M1WriteTB : SchedWriteRes<[M1UnitC, M1UnitALU]> { let Latency = 2; let NumMicroOps = 2; } def M1WriteVLDA : SchedWriteRes<[M1UnitL, M1UnitL]> { let Latency = 6; let NumMicroOps = 2; } def M1WriteVLDB : SchedWriteRes<[M1UnitL, M1UnitL, M1UnitL]> { let Latency = 7; let NumMicroOps = 3; } def M1WriteVLDC : SchedWriteRes<[M1UnitL, M1UnitL, M1UnitL, M1UnitL]> { let Latency = 8; let NumMicroOps = 4; } def M1WriteVLDD : SchedWriteRes<[M1UnitL, M1UnitNALU]> { let Latency = 7; let NumMicroOps = 2; let ResourceCycles = [2, 1]; } def M1WriteVLDE : SchedWriteRes<[M1UnitL, M1UnitNALU]> { let Latency = 6; let NumMicroOps = 2; } def M1WriteVLDF : SchedWriteRes<[M1UnitL, M1UnitL]> { let Latency = 10; let NumMicroOps = 2; let ResourceCycles = [1, 1]; } def M1WriteVLDG : SchedWriteRes<[M1UnitL, M1UnitNALU, M1UnitNALU]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [2, 1, 1]; } def M1WriteVLDH : SchedWriteRes<[M1UnitL, M1UnitNALU, M1UnitNALU]> { let Latency = 6; let NumMicroOps = 3; } def M1WriteVLDI : SchedWriteRes<[M1UnitL, M1UnitL, M1UnitL]> { let Latency = 12; let NumMicroOps = 3; let ResourceCycles = [2, 2, 2]; } def M1WriteVLDJ : SchedWriteRes<[M1UnitL, M1UnitNALU, M1UnitNALU, M1UnitNALU]> { let Latency = 9; let NumMicroOps = 4; let ResourceCycles = [2, 1, 1, 1]; } def M1WriteVLDK : SchedWriteRes<[M1UnitL, M1UnitNALU, M1UnitNALU, M1UnitNALU, M1UnitNALU]> { let Latency = 9; let NumMicroOps = 5; let ResourceCycles = [2, 1, 1, 1, 1]; } def M1WriteVLDL : SchedWriteRes<[M1UnitL, M1UnitNALU, M1UnitNALU, M1UnitL, M1UnitNALU]> { let Latency = 7; let NumMicroOps = 5; let ResourceCycles = [1, 1, 1, 1, 1]; } def M1WriteVLDM : SchedWriteRes<[M1UnitL, M1UnitNALU, M1UnitNALU, M1UnitL, M1UnitNALU, M1UnitNALU]> { let Latency = 7; let NumMicroOps = 6; let ResourceCycles = [1, 1, 1, 1, 1, 1]; } def M1WriteVLDN : SchedWriteRes<[M1UnitL, M1UnitL, M1UnitL, M1UnitL]> { let Latency = 14; let NumMicroOps = 4; let ResourceCycles = [2, 1, 2, 1]; } def M1WriteVSTA : WriteSequence<[WriteVST], 2>; def M1WriteVSTB : WriteSequence<[WriteVST], 3>; def M1WriteVSTC : WriteSequence<[WriteVST], 4>; def M1WriteVSTD : SchedWriteRes<[M1UnitS, M1UnitFST, M1UnitFST]> { let Latency = 7; let NumMicroOps = 2; let ResourceCycles = [7, 1, 1]; } def M1WriteVSTE : SchedWriteRes<[M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitFST]> { let Latency = 8; let NumMicroOps = 3; let ResourceCycles = [7, 1, 1, 1, 1]; } def M1WriteVSTF : SchedWriteRes<[M1UnitNALU, M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitFST, M1UnitFST]> { let Latency = 15; let NumMicroOps = 5; let ResourceCycles = [1, 7, 1, 7, 1, 1, 1]; } def M1WriteVSTG : SchedWriteRes<[M1UnitNALU, M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitFST, M1UnitFST]> { let Latency = 16; let NumMicroOps = 6; let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1]; } def M1WriteVSTH : SchedWriteRes<[M1UnitNALU, M1UnitS, M1UnitFST, M1UnitFST, M1UnitFST]> { let Latency = 14; let NumMicroOps = 4; let ResourceCycles = [1, 7, 1, 7, 1]; } def M1WriteVSTI : SchedWriteRes<[M1UnitNALU, M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitS, M1UnitFST, M1UnitFST, M1UnitFST]> { let Latency = 17; let NumMicroOps = 7; let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1, 1, 1]; } // Branch instructions def : InstRW<[M1WriteB1], (instrs Bcc)>; def : InstRW<[M1WriteA1], (instrs BL)>; def : InstRW<[M1WriteBX], (instrs BLR)>; def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>; def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>; // Arithmetic and logical integer instructions. def : InstRW<[M1WriteA1], (instrs COPY)>; def : InstRW<[M1WriteAX], (instregex ".+r[sx](64)?$")>; // Divide and multiply instructions. // Miscellaneous instructions. // Load instructions. def : InstRW<[M1WriteLB, WriteLDHi, WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; def : InstRW<[M1WriteLX, ReadAdrBase], (instregex "^PRFMro[WX]")>; // Store instructions. // FP data instructions. def : InstRW<[M1WriteNALU1], (instregex "^F(ABS|NEG)[DS]r")>; def : InstRW<[M1WriteFADD3], (instregex "^F(ADD|SUB)[DS]rr")>; def : InstRW<[M1WriteNEONG], (instregex "^FCCMPE?[DS]rr")>; def : InstRW<[M1WriteNMISC4], (instregex "^FCMPE?[DS]r")>; def : InstRW<[M1WriteFVAR15], (instrs FDIVSrr)>; def : InstRW<[M1WriteFVAR23], (instrs FDIVDrr)>; def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN).+rr")>; def : InstRW<[M1WriteFMAC4], (instregex "^FN?MUL[DS]rr")>; def : InstRW<[M1WriteFMAC5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>; def : InstRW<[M1WriteNEONH], (instregex "^FCSEL[DS]rrr")>; def : InstRW<[M1WriteFVAR15], (instrs FSQRTSr)>; def : InstRW<[M1WriteFVAR23], (instrs FSQRTDr)>; // FP miscellaneous instructions. def : InstRW<[M1WriteFCVT3], (instregex "^FCVT[DS][DS]r")>; def : InstRW<[M1WriteNEONF], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>; def : InstRW<[M1WriteNEONE], (instregex "^[SU]CVTF[SU]")>; def : InstRW<[M1WriteNALU1], (instregex "^FMOV[DS][ir]")>; def : InstRW<[M1WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv1")>; def : InstRW<[M1WriteFMAC5], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; def : InstRW<[M1WriteS4], (instregex "^FMOV[WX][DS](High)?r")>; def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>; // FP load instructions. def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; def : InstRW<[WriteVLD, WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; def : InstRW<[M1WriteLY, ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>; def : InstRW<[M1WriteLD, ReadAdrBase], (instregex "^LDRQro[WX]")>; def : InstRW<[WriteVLD, M1WriteLH], (instregex "^LDN?P[DS]i")>; def : InstRW<[M1WriteLA, M1WriteLH], (instregex "^LDN?PQi")>; def : InstRW<[M1WriteLC, M1WriteLH, WriteAdr], (instregex "^LDP[DS](post|pre)")>; def : InstRW<[M1WriteLD, M1WriteLH, WriteAdr], (instregex "^LDPQ(post|pre)")>; // FP store instructions. def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; def : InstRW<[WriteVST, WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; def : InstRW<[M1WriteSY, ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>; def : InstRW<[M1WriteSB, ReadAdrBase], (instregex "^STRQro[WX]")>; def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; def : InstRW<[WriteVST, WriteAdr], (instregex "^STP[DS](post|pre)")>; def : InstRW<[M1WriteSC, WriteAdr], (instregex "^STPQ(post|pre)")>; // ASIMD instructions. def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>; def : InstRW<[M1WriteNMISC1], (instregex "^[SU]ABDL?v")>; def : InstRW<[M1WriteNMISC1], (instregex "^(SQ)?ABSv")>; def : InstRW<[M1WriteNMISC1], (instregex "^SQNEGv")>; def : InstRW<[M1WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?H(ADD|SUB)v")>; def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?AD[AD](L|LP|P|W)V?2?v")>; def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?SUB[LW]2?v")>; def : InstRW<[M1WriteNMISC3], (instregex "^R?(ADD|SUB)HN?2?v")>; def : InstRW<[M1WriteNMISC3], (instregex "^[SU]+Q(ADD|SUB)v")>; def : InstRW<[M1WriteNMISC3], (instregex "^[SU]RHADDv")>; def : InstRW<[M1WriteNMISC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; def : InstRW<[M1WriteNALU1], (instregex "^CMTSTv")>; def : InstRW<[M1WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; def : InstRW<[M1WriteNMISC1], (instregex "^[SU](MIN|MAX)v")>; def : InstRW<[M1WriteNMISC2], (instregex "^[SU](MIN|MAX)Pv")>; def : InstRW<[M1WriteNMISC3], (instregex "^[SU](MIN|MAX)Vv")>; def : InstRW<[M1WriteNMISC4], (instregex "^(MUL|SQR?DMULH)v")>; def : InstRW<[M1WriteNMISC4], (instregex "^ML[AS]v")>; def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD|SQRD)ML[AS][HL]v")>; def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD)MULLv")>; def : InstRW<[M1WriteNAL13], (instregex "^(S|SR|U|UR)SRAv")>; def : InstRW<[M1WriteNALU1], (instregex "^SHL[dv]")>; def : InstRW<[M1WriteNALU1], (instregex "^[SU]SH[LR][dv]")>; def : InstRW<[M1WriteNALU1], (instregex "^S[RS]I[dv]")>; def : InstRW<[M1WriteNAL13], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; def : InstRW<[M1WriteNAL13], (instregex "^[SU]RSH[LR][dv]")>; def : InstRW<[M1WriteNAL13], (instregex "^[SU]QR?SHLU?[bdhsv]")>; // ASIMD FP instructions. def : InstRW<[M1WriteNALU1], (instregex "^F(ABS|NEG)v")>; def : InstRW<[M1WriteNMISC3], (instregex "^F(ABD|ADD|SUB)v")>; def : InstRW<[M1WriteNEONA], (instregex "^FADDP")>; def : InstRW<[M1WriteNMISC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; def : InstRW<[M1WriteFCVT3], (instregex "^[FVSU]CVTX?[AFLMNPZ][SU]?(_Int)?v")>; def : InstRW<[M1WriteFVAR15], (instregex "FDIVv.f32")>; def : InstRW<[M1WriteFVAR23], (instregex "FDIVv2f64")>; def : InstRW<[M1WriteFVAR15], (instregex "FSQRTv.f32")>; def : InstRW<[M1WriteFVAR23], (instregex "FSQRTv2f64")>; def : InstRW<[M1WriteNMISC1], (instregex "^F(MAX|MIN)(NM)?V?v")>; def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; def : InstRW<[M1WriteNEONJ], (instregex "^FMULX?v.i")>; def : InstRW<[M1WriteFMAC4], (instregex "^FMULX?v.f")>; def : InstRW<[M1WriteNEONK], (instregex "^FML[AS]v.i")>; def : InstRW<[M1WriteFMAC5], (instregex "^FML[AS]v.f")>; def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>; // ASIMD miscellaneous instructions. def : InstRW<[M1WriteNALU1], (instregex "^RBITv")>; def : InstRW<[M1WriteNAL11], (instregex "^(BIF|BIT|BSL)v")>; def : InstRW<[M1WriteNEONB], (instregex "^DUPv.+gpr")>; def : InstRW<[M1WriteNALU1], (instregex "^DUPv.+lane")>; def : InstRW<[M1WriteNALU1], (instregex "^EXTv8")>; def : InstRW<[M1WriteNEONL], (instregex "^EXTv16")>; def : InstRW<[M1WriteNAL13], (instregex "^[SU]?Q?XTU?Nv")>; def : InstRW<[M1WriteNALU1], (instregex "^CPY")>; def : InstRW<[M1WriteNALU1], (instregex "^INSv.+lane")>; def : InstRW<[M1WriteNALU1], (instregex "^MOVI[Dv]")>; def : InstRW<[M1WriteNALU1], (instregex "^FMOVv")>; def : InstRW<[M1WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; def : InstRW<[M1WriteFMAC5], (instregex "^F(RECP|RSQRT)Sv")>; def : InstRW<[M1WriteNALU1], (instregex "^REV(16|32|64)v")>; def : InstRW<[M1WriteNAL11], (instregex "^TB[LX]v8i8One")>; def : InstRW<[WriteSequence<[M1WriteNAL11], 2>], (instregex "^TB[LX]v8i8Two")>; def : InstRW<[WriteSequence<[M1WriteNAL11], 3>], (instregex "^TB[LX]v8i8Three")>; def : InstRW<[WriteSequence<[M1WriteNAL11], 4>], (instregex "^TB[LX]v8i8Four")>; def : InstRW<[M1WriteNAL12], (instregex "^TB[LX]v16i8One")>; def : InstRW<[WriteSequence<[M1WriteNAL12], 2>], (instregex "^TB[LX]v16i8Two")>; def : InstRW<[WriteSequence<[M1WriteNAL12], 3>], (instregex "^TB[LX]v16i8Three")>; def : InstRW<[WriteSequence<[M1WriteNAL12], 4>], (instregex "^TB[LX]v16i8Four")>; def : InstRW<[M1WriteNEOND], (instregex "^[SU]MOVv")>; def : InstRW<[M1WriteNEONC], (instregex "^INSv.+gpr")>; def : InstRW<[M1WriteNALU1], (instregex "^(TRN|UZP)[12](v8i8|v4i16|v2i32)")>; def : InstRW<[M1WriteNALU2], (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64)")>; def : InstRW<[M1WriteNALU1], (instregex "^ZIP[12]v")>; // ASIMD load instructions. def : InstRW<[M1WriteVLDD], (instregex "LD1i(8|16|32)$")>; def : InstRW<[M1WriteVLDD, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>; def : InstRW<[M1WriteVLDE], (instregex "LD1i(64)$")>; def : InstRW<[M1WriteVLDE, WriteAdr], (instregex "LD1i(64)_POST$")>; def : InstRW<[M1WriteL5], (instregex "LD1Rv(8b|4h|2s)$")>; def : InstRW<[M1WriteL5, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteL5], (instregex "LD1Rv(1d)$")>; def : InstRW<[M1WriteL5, WriteAdr], (instregex "LD1Rv(1d)_POST$")>; def : InstRW<[M1WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteL5, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteL5, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteL5, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteVLDA, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVLDA, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteVLDB, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVLDB, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteVLDC, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVLDC, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVLDG], (instregex "LD2i(8|16)$")>; def : InstRW<[M1WriteVLDG, WriteAdr], (instregex "LD2i(8|16)_POST$")>; def : InstRW<[M1WriteVLDG], (instregex "LD2i(32)$")>; def : InstRW<[M1WriteVLDG, WriteAdr], (instregex "LD2i(32)_POST$")>; def : InstRW<[M1WriteVLDH], (instregex "LD2i(64)$")>; def : InstRW<[M1WriteVLDH, WriteAdr], (instregex "LD2i(64)_POST$")>; def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(8b|4h|2s)$")>; def : InstRW<[M1WriteVLDA, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(1d)$")>; def : InstRW<[M1WriteVLDA, WriteAdr], (instregex "LD2Rv(1d)_POST$")>; def : InstRW<[M1WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVLDA, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; def : InstRW<[M1WriteVLDF, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(16b|8h|4s)$")>; def : InstRW<[M1WriteVLDF, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVLDF], (instregex "LD2Twov(2d)$")>; def : InstRW<[M1WriteVLDF, WriteAdr], (instregex "LD2Twov(2d)_POST$")>; def : InstRW<[M1WriteVLDJ], (instregex "LD3i(8|16)$")>; def : InstRW<[M1WriteVLDJ, WriteAdr], (instregex "LD3i(8|16)_POST$")>; def : InstRW<[M1WriteVLDJ], (instregex "LD3i(32)$")>; def : InstRW<[M1WriteVLDJ, WriteAdr], (instregex "LD3i(32)_POST$")>; def : InstRW<[M1WriteVLDL], (instregex "LD3i(64)$")>; def : InstRW<[M1WriteVLDL, WriteAdr], (instregex "LD3i(64)_POST$")>; def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(8b|4h|2s)$")>; def : InstRW<[M1WriteVLDB, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(1d)$")>; def : InstRW<[M1WriteVLDB, WriteAdr], (instregex "LD3Rv(1d)_POST$")>; def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(16b|8h|4s)$")>; def : InstRW<[M1WriteVLDB, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVLDB], (instregex "LD3Rv(2d)$")>; def : InstRW<[M1WriteVLDB, WriteAdr], (instregex "LD3Rv(2d)_POST$")>; def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; def : InstRW<[M1WriteVLDI, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(16b|8h|4s)$")>; def : InstRW<[M1WriteVLDI, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVLDI], (instregex "LD3Threev(2d)$")>; def : InstRW<[M1WriteVLDI, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; def : InstRW<[M1WriteVLDK], (instregex "LD4i(8|16)$")>; def : InstRW<[M1WriteVLDK, WriteAdr], (instregex "LD4i(8|16)_POST$")>; def : InstRW<[M1WriteVLDK], (instregex "LD4i(32)$")>; def : InstRW<[M1WriteVLDK, WriteAdr], (instregex "LD4i(32)_POST$")>; def : InstRW<[M1WriteVLDM], (instregex "LD4i(64)$")>; def : InstRW<[M1WriteVLDM, WriteAdr], (instregex "LD4i(64)_POST$")>; def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(8b|4h|2s)$")>; def : InstRW<[M1WriteVLDC, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(1d)$")>; def : InstRW<[M1WriteVLDC, WriteAdr], (instregex "LD4Rv(1d)_POST$")>; def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(16b|8h|4s)$")>; def : InstRW<[M1WriteVLDC, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVLDC], (instregex "LD4Rv(2d)$")>; def : InstRW<[M1WriteVLDC, WriteAdr], (instregex "LD4Rv(2d)_POST$")>; def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; def : InstRW<[M1WriteVLDN, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(16b|8h|4s)$")>; def : InstRW<[M1WriteVLDN, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVLDN], (instregex "LD4Fourv(2d)$")>; def : InstRW<[M1WriteVLDN, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; // ASIMD store instructions. def : InstRW<[M1WriteVSTD], (instregex "ST1i(8|16|32)$")>; def : InstRW<[M1WriteVSTD, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>; def : InstRW<[M1WriteVSTD], (instregex "ST1i(64)$")>; def : InstRW<[M1WriteVSTD, WriteAdr], (instregex "ST1i(64)_POST$")>; def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>; def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteVSTA, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVSTA, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteVSTB, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVSTB, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[M1WriteVSTC, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>; def : InstRW<[M1WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[M1WriteVSTC, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>; def : InstRW<[M1WriteVSTD], (instregex "ST2i(8|16|32)$")>; def : InstRW<[M1WriteVSTD, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>; def : InstRW<[M1WriteVSTD], (instregex "ST2i(64)$")>; def : InstRW<[M1WriteVSTD, WriteAdr], (instregex "ST2i(64)_POST$")>; def : InstRW<[M1WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; def : InstRW<[M1WriteVSTD, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVSTE], (instregex "ST2Twov(16b|8h|4s)$")>; def : InstRW<[M1WriteVSTE, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVSTE], (instregex "ST2Twov(2d)$")>; def : InstRW<[M1WriteVSTE, WriteAdr], (instregex "ST2Twov(2d)_POST$")>; def : InstRW<[M1WriteVSTH], (instregex "ST3i(8|16)$")>; def : InstRW<[M1WriteVSTH, WriteAdr], (instregex "ST3i(8|16)_POST$")>; def : InstRW<[M1WriteVSTH], (instregex "ST3i(32)$")>; def : InstRW<[M1WriteVSTH, WriteAdr], (instregex "ST3i(32)_POST$")>; def : InstRW<[M1WriteVSTF], (instregex "ST3i(64)$")>; def : InstRW<[M1WriteVSTF, WriteAdr], (instregex "ST3i(64)_POST$")>; def : InstRW<[M1WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; def : InstRW<[M1WriteVSTF, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVSTG], (instregex "ST3Threev(16b|8h|4s)$")>; def : InstRW<[M1WriteVSTG, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVSTG], (instregex "ST3Threev(2d)$")>; def : InstRW<[M1WriteVSTG, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; def : InstRW<[M1WriteVSTH], (instregex "ST4i(8|16)$")>; def : InstRW<[M1WriteVSTH, WriteAdr], (instregex "ST4i(8|16)_POST$")>; def : InstRW<[M1WriteVSTH], (instregex "ST4i(32)$")>; def : InstRW<[M1WriteVSTH, WriteAdr], (instregex "ST4i(32)_POST$")>; def : InstRW<[M1WriteVSTF], (instregex "ST4i(64)$")>; def : InstRW<[M1WriteVSTF, WriteAdr], (instregex "ST4i(64)_POST$")>; def : InstRW<[M1WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; def : InstRW<[M1WriteVSTF, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>; def : InstRW<[M1WriteVSTI], (instregex "ST4Fourv(16b|8h|4s)$")>; def : InstRW<[M1WriteVSTI, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>; def : InstRW<[M1WriteVSTI], (instregex "ST4Fourv(2d)$")>; def : InstRW<[M1WriteVSTI, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; // Cryptography instructions. def M1WriteAES : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; } def M1ReadAES : SchedReadAdvance<1, [M1WriteAES]>; def : InstRW<[M1WriteAES], (instregex "^AES[DE]")>; def : InstRW<[M1WriteAES, M1ReadAES], (instregex "^AESI?MC")>; def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>; def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>; def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>; def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA256SU0")>; def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA256(H|SU1)")>; // CRC instructions. def : InstRW<[M1WriteC2], (instregex "^CRC32")>; } // SchedModel = ExynosM1Model capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedExynosM3.td000064400000000000000000001235670072674642500263560ustar 00000000000000//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for the Samsung Exynos M3 to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide // in-order stage for decode and dispatch and a wider issue stage. // The execution units and loads and stores are out-of-order. def ExynosM3Model : SchedMachineModel { let IssueWidth = 6; // Up to 6 uops per cycle. let MicroOpBufferSize = 228; // ROB size. let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. let LoadLatency = 4; // Optimistic load cases. let MispredictPenalty = 16; // Minimum branch misprediction penalty. let CompleteModel = 1; // Use the default model otherwise. list UnsupportedFeatures = [HasSVE]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available on the Exynos-M3, // which has 12 pipelines, each with its own queue with out-of-order dispatch. let SchedModel = ExynosM3Model in { def M3UnitA : ProcResource<2>; // Simple integer def M3UnitC : ProcResource<2>; // Simple and complex integer def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) def M3UnitB : ProcResource<2>; // Branch def M3UnitL : ProcResource<2>; // Load def M3UnitS : ProcResource<1>; // Store def M3PipeF0 : ProcResource<1>; // FP #0 let Super = M3PipeF0 in { def M3UnitFMAC0 : ProcResource<1>; // FP multiplication def M3UnitFADD0 : ProcResource<1>; // Simple FP def M3UnitFCVT0 : ProcResource<1>; // FP conversion def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) def M3UnitNALU0 : ProcResource<1>; // Simple vector def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea def M3UnitNSHT0 : ProcResource<1>; // Vector shifting def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling } def M3PipeF1 : ProcResource<1>; // FP #1 let Super = M3PipeF1 in { def M3UnitFMAC1 : ProcResource<1>; // FP multiplication def M3UnitFADD1 : ProcResource<1>; // Simple FP def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) def M3UnitFCVT1 : ProcResource<1>; // FP conversion def M3UnitFST0 : ProcResource<1>; // FP store def M3UnitNALU1 : ProcResource<1>; // Simple vector def M3UnitNCRY0 : ProcResource<1>; // Cryptographic def M3UnitNMUL : ProcResource<1>; // Vector multiplication def M3UnitNSHT1 : ProcResource<1>; // Vector shifting def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling } def M3PipeF2 : ProcResource<1>; // FP #2 let Super = M3PipeF2 in { def M3UnitFMAC2 : ProcResource<1>; // FP multiplication def M3UnitFADD2 : ProcResource<1>; // Simple FP def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) def M3UnitFST1 : ProcResource<1>; // FP store def M3UnitNALU2 : ProcResource<1>; // Simple vector def M3UnitNCRY1 : ProcResource<1>; // Cryptographic def M3UnitNSHT2 : ProcResource<1>; // Vector shifting def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling } def M3UnitALU : ProcResGroup<[M3UnitA, M3UnitC]>; def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, M3UnitFMAC1, M3UnitFMAC2]>; def M3UnitFADD : ProcResGroup<[M3UnitFADD0, M3UnitFADD1, M3UnitFADD2]>; def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, M3UnitFDIV1]>; def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, M3UnitFCVT1]>; def M3UnitFST : ProcResGroup<[M3UnitFST0, M3UnitFST1]>; def M3UnitNALU : ProcResGroup<[M3UnitNALU0, M3UnitNALU1, M3UnitNALU2]>; def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, M3UnitNCRY1]>; def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, M3UnitNSHT1, M3UnitNSHT2]>; def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, M3UnitNSHF1, M3UnitNSHF2]>; //===----------------------------------------------------------------------===// // Predicates. def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() != AArch64::LR}]>; def M3ResetFastPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>; def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri || MI->getOpcode() == AArch64::EXTRXrri) && MI->getOperand(1).isReg() && MI->getOperand(2).isReg() && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>; def M3ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>; //===----------------------------------------------------------------------===// // Coarse scheduling model. def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; let NumMicroOps = 1; } def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; let ResourceCycles = [2]; } def M3WriteAB : SchedWriteRes<[M3UnitALU, M3UnitC]> { let Latency = 1; let NumMicroOps = 2; } def M3WriteAC : SchedWriteRes<[M3UnitALU, M3UnitALU, M3UnitC]> { let Latency = 2; let NumMicroOps = 3; } def M3WriteAD : SchedWriteRes<[M3UnitALU, M3UnitC]> { let Latency = 2; let NumMicroOps = 2; } def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } def M3WriteAX : SchedWriteVariant<[SchedVar, SchedVar, SchedVar]>; def M3WriteAY : SchedWriteVariant<[SchedVar, SchedVar]>; def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } def M3WriteBX : SchedWriteVariant<[SchedVar, SchedVar]>; def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } def M3WriteLA : SchedWriteRes<[M3UnitL, M3UnitL]> { let Latency = 5; let NumMicroOps = 1; } def M3WriteLB : SchedWriteRes<[M3UnitA, M3UnitL]> { let Latency = 5; let NumMicroOps = 2; } def M3WriteLC : SchedWriteRes<[M3UnitA, M3UnitL, M3UnitL]> { let Latency = 5; let NumMicroOps = 2; } def M3WriteLD : SchedWriteRes<[M3UnitA, M3UnitL]> { let Latency = 4; let NumMicroOps = 2; } def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; let NumMicroOps = 0; } def M3WriteLX : SchedWriteVariant<[SchedVar, SchedVar]>; def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } def M3WriteSA : SchedWriteRes<[M3UnitA, M3UnitS, M3UnitFST]> { let Latency = 2; let NumMicroOps = 2; } def M3WriteSB : SchedWriteRes<[M3UnitA, M3UnitS]> { let Latency = 1; let NumMicroOps = 2; } def M3WriteSC : SchedWriteRes<[M3UnitA, M3UnitS]> { let Latency = 2; let NumMicroOps = 2; } def M3WriteSX : SchedWriteVariant<[SchedVar, SchedVar]>; def M3WriteSY : SchedWriteVariant<[SchedVar, SchedVar]>; def M3ReadAdrBase : SchedReadVariant<[SchedVar, SchedVar]>; // Branch instructions. def : SchedAlias; def : WriteRes { let Latency = 1; } // Arithmetic and logical integer instructions. def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } // Move instructions. def : WriteRes { let Latency = 1; } // Divide and multiply instructions. def : WriteRes { let Latency = 12; let ResourceCycles = [1, 12]; } def : WriteRes { let Latency = 21; let ResourceCycles = [1, 21]; } def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 4; let ResourceCycles = [2]; } // Miscellaneous instructions. def : WriteRes { let Latency = 1; let NumMicroOps = 2; } // Addressing modes. def : WriteRes { let Latency = 1; let NumMicroOps = 0; } def : SchedAlias; // Load instructions. def : SchedAlias; def : WriteRes { let Latency = 4; let NumMicroOps = 0; } def : SchedAlias; // Store instructions. def : SchedAlias; def : SchedAlias; def : SchedAlias; def : SchedAlias; // FP data instructions. def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 12; let ResourceCycles = [12]; } def : WriteRes { let Latency = 4; } // FP miscellaneous instructions. // TODO: Conversion between register files is much different. def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } // FP load instructions. def : SchedAlias; // FP store instructions. def : WriteRes { let Latency = 1; let NumMicroOps = 1; } // ASIMD FP instructions. def : WriteRes { let Latency = 3; } // Other miscellaneous instructions. def : WriteRes { let Unsupported = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } //===----------------------------------------------------------------------===// // Generic fast forwarding. // TODO: Add FP register forwarding rules. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; // TODO: The forwarding for 32 bits actually saves 2 cycles. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; //===----------------------------------------------------------------------===// // Finer scheduling model. def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, M3UnitFADD]> { let Latency = 3; let NumMicroOps = 2; } def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, M3UnitFST]> { let Latency = 10; let NumMicroOps = 2; } def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, M3UnitFST]> { let Latency = 6; let NumMicroOps = 2; } def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, M3UnitS]> { let Latency = 5; let NumMicroOps = 2; } def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, M3UnitS]> { let Latency = 5; let NumMicroOps = 2; } def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, M3UnitFDIV1]> { let Latency = 7; let NumMicroOps = 2; let ResourceCycles = [8, 8]; } def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, M3UnitFDIV1]> { let Latency = 12; let NumMicroOps = 2; let ResourceCycles = [13, 13]; } def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, M3UnitFSQR]> { let Latency = 18; let NumMicroOps = 2; let ResourceCycles = [19, 19]; } def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, M3UnitFSQR]> { let Latency = 25; let NumMicroOps = 2; let ResourceCycles = [26, 26]; } def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, M3UnitNMSC]> { let Latency = 5; let NumMicroOps = 2; } def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; let ResourceCycles = [8]; } def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; let ResourceCycles = [13]; } def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; let ResourceCycles = [19]; } def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; let ResourceCycles = [26]; } def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } def M3WriteVLDA : SchedWriteRes<[M3UnitL, M3UnitL]> { let Latency = 5; let NumMicroOps = 2; } def M3WriteVLDB : SchedWriteRes<[M3UnitL, M3UnitL, M3UnitL]> { let Latency = 6; let NumMicroOps = 3; } def M3WriteVLDC : SchedWriteRes<[M3UnitL, M3UnitL, M3UnitL, M3UnitL]> { let Latency = 6; let NumMicroOps = 4; } def M3WriteVLDD : SchedWriteRes<[M3UnitL, M3UnitNALU]> { let Latency = 7; let NumMicroOps = 2; let ResourceCycles = [2, 1]; } def M3WriteVLDE : SchedWriteRes<[M3UnitL, M3UnitNALU]> { let Latency = 6; let NumMicroOps = 2; let ResourceCycles = [2, 1]; } def M3WriteVLDF : SchedWriteRes<[M3UnitL, M3UnitL]> { let Latency = 10; let NumMicroOps = 2; let ResourceCycles = [5, 5]; } def M3WriteVLDG : SchedWriteRes<[M3UnitL, M3UnitNALU, M3UnitNALU]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [2, 1, 1]; } def M3WriteVLDH : SchedWriteRes<[M3UnitL, M3UnitNALU, M3UnitNALU]> { let Latency = 6; let NumMicroOps = 3; let ResourceCycles = [2, 1, 1]; } def M3WriteVLDI : SchedWriteRes<[M3UnitL, M3UnitL, M3UnitL]> { let Latency = 12; let NumMicroOps = 3; let ResourceCycles = [6, 6, 6]; } def M3WriteVLDJ : SchedWriteRes<[M3UnitL, M3UnitNALU, M3UnitNALU, M3UnitNALU]> { let Latency = 7; let NumMicroOps = 4; let ResourceCycles = [2, 1, 1, 1]; } def M3WriteVLDK : SchedWriteRes<[M3UnitL, M3UnitNALU, M3UnitNALU, M3UnitNALU, M3UnitNALU]> { let Latency = 9; let NumMicroOps = 5; let ResourceCycles = [4, 1, 1, 1, 1]; } def M3WriteVLDL : SchedWriteRes<[M3UnitL, M3UnitNALU, M3UnitNALU, M3UnitL, M3UnitNALU]> { let Latency = 6; let NumMicroOps = 5; let ResourceCycles = [6, 1, 1, 6, 1]; } def M3WriteVLDM : SchedWriteRes<[M3UnitL, M3UnitNALU, M3UnitNALU, M3UnitL, M3UnitNALU, M3UnitNALU]> { let Latency = 7; let NumMicroOps = 6; let ResourceCycles = [6, 1, 1, 6, 1, 1]; } def M3WriteVLDN : SchedWriteRes<[M3UnitL, M3UnitL, M3UnitL, M3UnitL]> { let Latency = 14; let NumMicroOps = 4; let ResourceCycles = [6, 6, 6, 6]; } def M3WriteVSTA : WriteSequence<[WriteVST], 2>; def M3WriteVSTB : WriteSequence<[WriteVST], 3>; def M3WriteVSTC : WriteSequence<[WriteVST], 4>; def M3WriteVSTD : SchedWriteRes<[M3UnitS, M3UnitFST, M3UnitS, M3UnitFST]> { let Latency = 7; let NumMicroOps = 4; let ResourceCycles = [1, 3, 1, 3]; } def M3WriteVSTE : SchedWriteRes<[M3UnitS, M3UnitFST, M3UnitS, M3UnitFST, M3UnitS, M3UnitFST]> { let Latency = 8; let NumMicroOps = 6; let ResourceCycles = [1, 3, 1, 3, 1, 3]; } def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, M3UnitFST, M3UnitFST, M3UnitS, M3UnitFST, M3UnitS, M3UnitFST]> { let Latency = 15; let NumMicroOps = 7; let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, M3UnitFST, M3UnitFST, M3UnitS, M3UnitFST, M3UnitS, M3UnitFST, M3UnitS, M3UnitFST]> { let Latency = 16; let NumMicroOps = 9; let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, M3UnitFST, M3UnitFST, M3UnitS, M3UnitFST]> { let Latency = 14; let NumMicroOps = 5; let ResourceCycles = [1, 3, 3, 1, 3]; } def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, M3UnitFST, M3UnitFST, M3UnitS, M3UnitFST, M3UnitS, M3UnitFST, M3UnitS, M3UnitFST]> { let Latency = 17; let NumMicroOps = 9; let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } // Special cases. def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, M3WriteFMAC5]>; def M3WriteMOVI : SchedWriteVariant<[SchedVar, SchedVar]>; def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; // Branch instructions def : InstRW<[M3WriteB1], (instrs Bcc)>; def : InstRW<[M3WriteA1], (instrs BL)>; def : InstRW<[M3WriteBX], (instrs BLR)>; def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; // Arithmetic and logical integer instructions. def : InstRW<[M3WriteA1], (instrs COPY)>; def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?Xrx64")>; def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|ORR|SUB)[WX]r[sx]$")>; def : InstRW<[M3WriteAX], (instregex "^(ADD|BIC|SUB)S[WX]r[sx]$")>; def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|EOR|ORR|SUB)[WX]ri")>; // Move instructions. def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; // Divide and multiply instructions. // Miscellaneous instructions. def : InstRW<[M3WriteAY], (instrs EXTRWrri, EXTRXrri)>; // Load instructions. def : InstRW<[M3WriteLD, WriteLDHi, WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; def : InstRW<[M3WriteLX, ReadAdrBase], (instregex "^PRFMro[WX]")>; // Store instructions. // FP data instructions. def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; def : InstRW<[M3WriteFMAC4, M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; // FP miscellaneous instructions. def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; def : InstRW<[M3WriteFMAC4, M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; // FP load instructions. def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; def : InstRW<[WriteVLD, WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; def : InstRW<[M3WriteLX, ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>; def : InstRW<[M3WriteLB, ReadAdrBase], (instregex "^LDRQro[WX]")>; def : InstRW<[WriteVLD, M3WriteLH], (instregex "^LDN?P[DS]i")>; def : InstRW<[M3WriteLA, M3WriteLH], (instregex "^LDN?PQi")>; def : InstRW<[M3WriteLB, M3WriteLH, WriteAdr], (instregex "^LDP[DS](post|pre)")>; def : InstRW<[M3WriteLC, M3WriteLH, WriteAdr], (instregex "^LDPQ(post|pre)")>; // FP store instructions. def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; def : InstRW<[WriteVST, WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; def : InstRW<[M3WriteSY, ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>; def : InstRW<[M3WriteSA, ReadAdrBase], (instregex "^STRQro[WX]")>; def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; def : InstRW<[WriteVST, WriteAdr], (instregex "^STP[DS](post|pre)")>; def : InstRW<[M3WriteSA, WriteAdr], (instregex "^STPQ(post|pre)")>; // ASIMD instructions. def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; def : InstRW<[M3WriteNMSC1], (instregex "^(SQ)?(ABS|NEG)v")>; def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Vv")>; def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; def : InstRW<[M3WriteNMUL3, M3ReadNMUL], (instregex "^ML[AS]v")>; def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; // ASIMD FP instructions. def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; def : InstRW<[M3WriteFMAC4, M3ReadFMAC], (instregex "^FML[AS]v.f")>; def : InstRW<[M3WriteFMAC5, M3ReadFMAC], (instregex "^FML[AS]v.i")>; def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; // ASIMD miscellaneous instructions. def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; def : InstRW<[M3WriteFMAC4, M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; // ASIMD load instructions. def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteL5, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteL5, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVLDA, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDA, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVLDB, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDB, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVLDC, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDC, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; def : InstRW<[M3WriteVLDD, WriteAdr], (instregex "LD1i(8|16|32)_POST")>; def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; def : InstRW<[M3WriteVLDE, WriteAdr], (instregex "LD1i(64)_POST")>; def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteL5, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteL5, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; def : InstRW<[M3WriteVLDF, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST")>; def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDF, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; def : InstRW<[M3WriteVLDG, WriteAdr], (instregex "LD2i(8|16|32)_POST")>; def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; def : InstRW<[M3WriteVLDH, WriteAdr], (instregex "LD2i(64)_POST")>; def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVLDA, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDA, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; def : InstRW<[M3WriteVLDI, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST")>; def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDI, WriteAdr], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; def : InstRW<[M3WriteVLDJ, WriteAdr], (instregex "LD3i(8|16|32)_POST")>; def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; def : InstRW<[M3WriteVLDL, WriteAdr], (instregex "LD3i(64)_POST")>; def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVLDB, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDB, WriteAdr], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; def : InstRW<[M3WriteVLDN, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST")>; def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDN, WriteAdr], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; def : InstRW<[M3WriteVLDK, WriteAdr], (instregex "LD4i(8|16|32)_POST")>; def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; def : InstRW<[M3WriteVLDM, WriteAdr], (instregex "LD4i(64)_POST")>; def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVLDC, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVLDC, WriteAdr], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; // ASIMD store instructions. def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVSTA, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVSTA, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVSTB, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVSTB, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[M3WriteVSTC, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVSTC, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; def : InstRW<[M3WriteVSTD, WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; def : InstRW<[M3WriteVSTD, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVSTE, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; def : InstRW<[M3WriteVSTD, WriteAdr], (instregex "ST2i(8|16|32)_POST")>; def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; def : InstRW<[M3WriteVSTD, WriteAdr], (instregex "ST2i(64)_POST")>; def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; def : InstRW<[M3WriteVSTF, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVSTG, WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; def : InstRW<[M3WriteVSTH, WriteAdr], (instregex "ST3i(8|16|32)_POST")>; def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; def : InstRW<[M3WriteVSTF, WriteAdr], (instregex "ST3i(64)_POST")>; def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; def : InstRW<[M3WriteVSTF, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; def : InstRW<[M3WriteVSTI, WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; def : InstRW<[M3WriteVSTF, WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; // Cryptography instructions. def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; def : InstRW<[M3WriteAES, M3ReadAES], (instregex "^AESI?MC")>; def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; // CRC instructions. def : InstRW<[M3WriteC2], (instregex "^CRC32")>; } // SchedModel = ExynosM3Model capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedFalkor.td000064400000000000000000000122770072674642500261020ustar 00000000000000//==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for Qualcomm Falkor to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Define the SchedMachineModel and provide basic properties for coarse grained // instruction cost model. def FalkorModel : SchedMachineModel { let IssueWidth = 8; // 8 uops are dispatched per cycle. let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer. let LoopMicroOpBufferSize = 16; let LoadLatency = 3; // Optimistic load latency. let MispredictPenalty = 11; // Minimum branch misprediction penalty. let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available on Falkor. let SchedModel = FalkorModel in { def FalkorUnitB : ProcResource<1>; // Branch def FalkorUnitLD : ProcResource<1>; // Load pipe def FalkorUnitSD : ProcResource<1>; // Store data def FalkorUnitST : ProcResource<1>; // Store pipe def FalkorUnitX : ProcResource<1>; // Complex arithmetic def FalkorUnitY : ProcResource<1>; // Simple arithmetic def FalkorUnitZ : ProcResource<1>; // Simple arithmetic def FalkorUnitVSD : ProcResource<1>; // Vector store data def FalkorUnitVX : ProcResource<1>; // Vector X-pipe def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector def FalkorUnitVTOG : ProcResource<1>; // Vector to Scalar // Define the resource groups. def FalkorUnitXY : ProcResGroup<[FalkorUnitX, FalkorUnitY]>; def FalkorUnitXYZ : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ]>; def FalkorUnitXYZB : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ, FalkorUnitB]>; def FalkorUnitZB : ProcResGroup<[FalkorUnitZ, FalkorUnitB]>; def FalkorUnitVXVY : ProcResGroup<[FalkorUnitVX, FalkorUnitVY]>; } //===----------------------------------------------------------------------===// // Map the target-defined scheduler read/write resources and latency for // Falkor. let SchedModel = FalkorModel in { // These WriteRes entries are not used in the Falkor sched model. def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } def : WriteRes { let Unsupported = 1; } // These ReadAdvance entries are not used in the Falkor sched model. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; // Detailed Refinements // ----------------------------------------------------------------------------- include "AArch64SchedFalkorDetails.td" } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedFalkorDetails.td000064400000000000000000002071760072674642500274140ustar 00000000000000//==- AArch64SchedFalkorDetails.td - Falkor Scheduling Defs -*- tablegen -*-==// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the uop and latency details for the machine model for the // Qualcomm Falkor subtarget. // //===----------------------------------------------------------------------===// // Contains all of the Falkor specific SchedWriteRes types. The approach // below is to define a generic SchedWriteRes for every combination of // latency and microOps. The naming conventions is to use a prefix, one field // for latency, and one or more microOp count/type designators. // Prefix: FalkorWr // MicroOp Count/Types: #(B|X|Y|Z|LD|ST|SD|VX|VY|VSD) // Latency: #cyc // // e.g. FalkorWr_1Z_6SD_4VX_6cyc means there are 11 micro-ops to be issued // down one Z pipe, six SD pipes, four VX pipes and the total latency is // six cycles. // // Contains all of the Falkor specific ReadAdvance types for forwarding logic. // // Contains all of the Falkor specific WriteVariant types for immediate zero // and LSLFast. //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Define 0 micro-op types def FalkorWr_LdInc_none_2cyc : SchedWriteRes<[]> { let Latency = 2; let NumMicroOps = 0; } def FalkorWr_StInc_none_2cyc : SchedWriteRes<[]> { let Latency = 2; let NumMicroOps = 0; } def FalkorWr_none_3cyc : SchedWriteRes<[]> { let Latency = 3; let NumMicroOps = 0; } def FalkorWr_none_4cyc : SchedWriteRes<[]> { let Latency = 4; let NumMicroOps = 0; } //===----------------------------------------------------------------------===// // Define 1 micro-op types def FalkorWr_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 2; } def FalkorWr_IMUL32_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; } def FalkorWr_IMUL64_1X_4cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; } def FalkorWr_IMUL64_1X_5cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 5; } def FalkorWr_1Z_0cyc : SchedWriteRes<[FalkorUnitZ]> { let Latency = 0; } def FalkorWr_1ZB_0cyc : SchedWriteRes<[FalkorUnitZB]> { let Latency = 0; } def FalkorWr_1LD_3cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 3; } def FalkorWr_1LD_4cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 4; } def FalkorWr_1XYZ_0cyc : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 0; } def FalkorWr_1XYZ_1cyc : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 1; } def FalkorWr_1XYZ_2cyc : SchedWriteRes<[FalkorUnitXYZ]> { let Latency = 2; } def FalkorWr_1XYZB_0cyc : SchedWriteRes<[FalkorUnitXYZB]>{ let Latency = 0; } def FalkorWr_1XYZB_1cyc : SchedWriteRes<[FalkorUnitXYZB]>{ let Latency = 1; } def FalkorWr_1none_0cyc : SchedWriteRes<[]> { let Latency = 0; } def FalkorWr_1VXVY_0cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 0; } def FalkorWr_1VXVY_1cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 1; } def FalkorWr_1VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 2; } def FalkorWr_1VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 3; } def FalkorWr_1VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 4; } def FalkorWr_VMUL32_1VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 4; } def FalkorWr_1VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 5; } def FalkorWr_FMUL32_1VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 5; } def FalkorWr_1VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 6; } def FalkorWr_FMUL64_1VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY]>{ let Latency = 6; } def FalkorWr_1LD_0cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 0; } def FalkorWr_1ST_0cyc : SchedWriteRes<[FalkorUnitST]> { let Latency = 0; } def FalkorWr_1ST_3cyc : SchedWriteRes<[FalkorUnitST]> { let Latency = 3; } def FalkorWr_1GTOV_0cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 0; } def FalkorWr_1GTOV_1cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 1; } def FalkorWr_1GTOV_4cyc : SchedWriteRes<[FalkorUnitGTOV]>{ let Latency = 4; } def FalkorWr_1VTOG_1cyc : SchedWriteRes<[FalkorUnitVTOG]>{ let Latency = 1; } //===----------------------------------------------------------------------===// // Define 2 micro-op types def FalkorWr_2VXVY_0cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 0; let NumMicroOps = 2; } def FalkorWr_2VXVY_1cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 1; let NumMicroOps = 2; } def FalkorWr_2VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 2; let NumMicroOps = 2; } def FalkorWr_2VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 3; let NumMicroOps = 2; } def FalkorWr_2VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 2; } def FalkorWr_VMUL32_2VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 2; } def FalkorWr_2VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 5; let NumMicroOps = 2; } def FalkorWr_FMUL32_2VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 5; let NumMicroOps = 2; } def FalkorWr_2VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 6; let NumMicroOps = 2; } def FalkorWr_FMUL64_2VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 6; let NumMicroOps = 2; } def FalkorWr_1LD_1VXVY_4cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 2; } def FalkorWr_1XYZ_1LD_4cyc : SchedWriteRes<[FalkorUnitXYZ, FalkorUnitLD]> { let Latency = 4; let NumMicroOps = 2; } def FalkorWr_2LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_5cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 5; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_2cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 2; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_4cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 4; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_10cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 10; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_12cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 12; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_14cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 14; let NumMicroOps = 2; } def FalkorWr_1VX_1VY_21cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY]> { let Latency = 21; let NumMicroOps = 2; } def FalkorWr_1GTOV_1VXVY_2cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitVXVY]> { let Latency = 2; let NumMicroOps = 2; } def FalkorWr_2GTOV_1cyc : SchedWriteRes<[FalkorUnitGTOV, FalkorUnitGTOV]> { let Latency = 1; let NumMicroOps = 2; } def FalkorWr_1XYZ_1ST_4cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST]> { let Latency = 4; let NumMicroOps = 2; } def FalkorWr_1XYZ_1LD_5cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitLD]> { let Latency = 5; let NumMicroOps = 2; } def FalkorWr_2XYZ_2cyc : SchedWriteRes<[FalkorUnitXYZ, FalkorUnitXYZ]> { let Latency = 2; let NumMicroOps = 2; } def FalkorWr_1Z_1XY_0cyc : SchedWriteRes<[FalkorUnitZ, FalkorUnitXY]> { let Latency = 0; let NumMicroOps = 2; } def FalkorWr_1X_1Z_8cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> { let Latency = 8; let NumMicroOps = 2; let ResourceCycles = [2, 8]; } def FalkorWr_1X_1Z_11cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> { let Latency = 11; let NumMicroOps = 2; let ResourceCycles = [2, 11]; } def FalkorWr_1LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitZ]> { let Latency = 3; let NumMicroOps = 2; } def FalkorWr_1LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 2; } def FalkorWr_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitSD, FalkorUnitST]> { let Latency = 0; let NumMicroOps = 2; } def FalkorWr_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitVSD, FalkorUnitST]> { let Latency = 0; let NumMicroOps = 2; } //===----------------------------------------------------------------------===// // Define 3 micro-op types def FalkorWr_1ST_1SD_1LD_0cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD, FalkorUnitLD]> { let Latency = 0; let NumMicroOps = 3; } def FalkorWr_1ST_1SD_1LD_3cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 3; } def FalkorWr_3VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 3; let NumMicroOps = 3; } def FalkorWr_3VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 3; } def FalkorWr_3VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 5; let NumMicroOps = 3; } def FalkorWr_3VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 6; let NumMicroOps = 3; } def FalkorWr_1LD_2VXVY_4cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 3; } def FalkorWr_2LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 3; } def FalkorWr_3LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 3; } def FalkorWr_2LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitZ]> { let Latency = 3; let NumMicroOps = 3; } def FalkorWr_1XYZ_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitSD, FalkorUnitST]> { let Latency = 0; let NumMicroOps = 3; } def FalkorWr_1XYZ_1VSD_1ST_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitVSD, FalkorUnitST]> { let Latency = 0; let NumMicroOps = 3; } //===----------------------------------------------------------------------===// // Define 4 micro-op types def FalkorWr_2VX_2VY_14cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, FalkorUnitVX, FalkorUnitVY]> { let Latency = 14; let NumMicroOps = 4; } def FalkorWr_2VX_2VY_20cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, FalkorUnitVX, FalkorUnitVY]> { let Latency = 20; let NumMicroOps = 4; } def FalkorWr_2VX_2VY_21cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, FalkorUnitVX, FalkorUnitVY]> { let Latency = 21; let NumMicroOps = 4; } def FalkorWr_2VX_2VY_24cyc : SchedWriteRes<[FalkorUnitVX, FalkorUnitVY, FalkorUnitVX, FalkorUnitVY]> { let Latency = 24; let NumMicroOps = 4; } def FalkorWr_4VXVY_2cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 2; let NumMicroOps = 4; } def FalkorWr_4VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 3; let NumMicroOps = 4; } def FalkorWr_4VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 4; } def FalkorWr_4VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 6; let NumMicroOps = 4; } def FalkorWr_4LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitLD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 4; } def FalkorWr_1LD_3VXVY_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 4; } def FalkorWr_2LD_2none_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 4; } def FalkorWr_2LD_1ST_1SD_3cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitST, FalkorUnitSD, FalkorUnitLD]> { let Latency = 3; let NumMicroOps = 4; } def FalkorWr_2VSD_2ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 4; } //===----------------------------------------------------------------------===// // Define 5 micro-op types def FalkorWr_1LD_4VXVY_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 5; } def FalkorWr_2LD_2VXVY_1none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 5; } def FalkorWr_5VXVY_7cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 7; let NumMicroOps = 5; } def FalkorWr_1XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 5; } def FalkorWr_1VXVY_2ST_2VSD_0cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 5; } //===----------------------------------------------------------------------===// // Define 6 micro-op types def FalkorWr_2LD_2VXVY_2none_4cyc: SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 6; } def FalkorWr_2XYZ_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitXYZ, FalkorUnitST, FalkorUnitVSD, FalkorUnitXYZ, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 6; } def FalkorWr_2VXVY_2ST_2VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 6; } def FalkorWr_3VSD_3ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 6; } //===----------------------------------------------------------------------===// // Define 8 micro-op types def FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 8; } def FalkorWr_4VSD_4ST_0cyc: SchedWriteRes<[FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 8; } //===----------------------------------------------------------------------===// // Define 9 micro-op types def FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitLD, FalkorUnitLD, FalkorUnitXYZ, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 9; } def FalkorWr_2LD_2VXVY_1XYZ_2LD_2VXVY_4cyc:SchedWriteRes<[FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY, FalkorUnitXYZ, FalkorUnitLD, FalkorUnitLD, FalkorUnitVXVY, FalkorUnitVXVY]> { let Latency = 4; let NumMicroOps = 9; } //===----------------------------------------------------------------------===// // Define 10 micro-op types def FalkorWr_2VXVY_4ST_4VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 10; } //===----------------------------------------------------------------------===// // Define 12 micro-op types def FalkorWr_4VXVY_4ST_4VSD_0cyc: SchedWriteRes<[FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD, FalkorUnitVXVY, FalkorUnitST, FalkorUnitVSD]> { let Latency = 0; let NumMicroOps = 12; } // Forwarding logic is modeled for multiply add/accumulate and // load/store base register increment. // ----------------------------------------------------------------------------- def FalkorReadIMA32 : SchedReadAdvance<3, [FalkorWr_IMUL32_1X_2cyc]>; def FalkorReadIMA64 : SchedReadAdvance<4, [FalkorWr_IMUL64_1X_4cyc, FalkorWr_IMUL64_1X_5cyc]>; def FalkorReadVMA : SchedReadAdvance<3, [FalkorWr_VMUL32_1VXVY_4cyc, FalkorWr_VMUL32_2VXVY_4cyc]>; def FalkorReadFMA32 : SchedReadAdvance<1, [FalkorWr_FMUL32_1VXVY_5cyc, FalkorWr_FMUL32_2VXVY_5cyc]>; def FalkorReadFMA64 : SchedReadAdvance<2, [FalkorWr_FMUL64_1VXVY_6cyc, FalkorWr_FMUL64_2VXVY_6cyc]>; def FalkorReadIncLd : SchedReadAdvance<1, [FalkorWr_LdInc_none_2cyc]>; def FalkorReadIncSt : SchedReadAdvance<1, [FalkorWr_StInc_none_2cyc]>; // SchedPredicates and WriteVariants for Immediate Zero and LSLFast/ASRFast // ----------------------------------------------------------------------------- def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0}]>; def FalkorOp1ZrReg : SchedPredicate<[{MI->getOperand(1).getReg() == AArch64::WZR || MI->getOperand(1).getReg() == AArch64::XZR}]>; def FalkorShiftExtFastPred : SchedPredicate<[{TII->isFalkorShiftExtFast(*MI)}]>; def FalkorWr_FMOV : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_MOVZ : SchedWriteVariant<[ SchedVar, SchedVar]>; // imm fwd def FalkorWr_ADDSUBsx : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_LDRro : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_LDRSro : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_ORRi : SchedWriteVariant<[ SchedVar, // imm fwd SchedVar]>; def FalkorWr_PRFMro : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_STRVro : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_STRQro : SchedWriteVariant<[ SchedVar, SchedVar]>; def FalkorWr_STRro : SchedWriteVariant<[ SchedVar, SchedVar]>; //===----------------------------------------------------------------------===// // Specialize the coarse model by associating instruction groups with the // subtarget-defined types. As the modeled is refined, this will override most // of the earlier mappings. // Miscellaneous // ----------------------------------------------------------------------------- // FIXME: This could be better modeled by looking at the regclasses of the operands. def : InstRW<[FalkorWr_1XYZ_1cyc], (instrs COPY)>; // SIMD Floating-point Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FAC(GE|GT)(32|64)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^F(MAX|MIN)(NM)?Vv4i32v$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^FADDP(v2i32p|v2i64p|v2f32)$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instrs FCVTXNv1i64)>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVTZ(S|U)v2i32(_shift)?$")>; def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], (instregex "^(FMUL|FMULX)(v2f32|(v1i32_indexed|v2i32_indexed))$")>; def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], (instrs FMULX32)>; def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], (instregex "^(FMUL|FMULX)v1i64_indexed$")>; def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], (instrs FMULX64)>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f64|v4f32|v2i64p)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instrs FCVTLv4i16, FCVTLv2i32)>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>; def : InstRW<[FalkorWr_1VX_1VY_10cyc],(instrs FDIVv2f32)>; def : InstRW<[FalkorWr_1VX_1VY_12cyc],(instrs FSQRTv2f32)>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v2f64|v4f32)$")>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instrs FCVTLv8i16, FCVTLv4i32)>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVTZ(S|U)(v2i64|v4i32)(_shift)?$")>; def : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc], (instregex "^(FMUL|FMULX)(v2f64|v4f32|v4i32_indexed)$")>; def : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc], (instregex "^(FMUL|FMULX)v2i64_indexed$")>; def : InstRW<[FalkorWr_3VXVY_4cyc], (instrs FCVTNv4i16, FCVTNv2i32, FCVTXNv2f32)>; def : InstRW<[FalkorWr_3VXVY_5cyc], (instrs FCVTNv8i16, FCVTNv4i32, FCVTXNv4f32)>; def : InstRW<[FalkorWr_2VX_2VY_14cyc],(instrs FDIVv2f64)>; def : InstRW<[FalkorWr_2VX_2VY_20cyc],(instrs FDIVv4f32)>; def : InstRW<[FalkorWr_2VX_2VY_21cyc],(instrs FSQRTv2f64)>; def : InstRW<[FalkorWr_2VX_2VY_24cyc],(instrs FSQRTv4f32)>; def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA], (instregex "^ML(A|S)(v8i8|v4i16|v2i32)(_indexed)?$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>; def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc, FalkorReadFMA32], (instregex "^FML(A|S)(v2f32|(v1i32_indexed|v2i32_indexed))$")>; def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, FalkorReadFMA64], (instregex "^FML(A|S)v1i64_indexed$")>; def : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc, FalkorReadFMA32], (instregex "^FML(A|S)(v4f32|v4i32_indexed)$")>; def : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc, FalkorReadFMA64], (instregex "^FML(A|S)(v2f64|v2i64_indexed)$")>; // SIMD Integer Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs ADDPv2i64p)>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIC|ORR)(v2i32|v4i16)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.*)?$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHLv1i64$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHR(v2i32|v4i16|v8i8)_shift$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHRd$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instrs PMULv8i8)>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^SHL(v2i32|v4i16|v8i8)_shift$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^SHLd$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(ABD|ADALP)(v8i8|v4i16|v2i32)(_v.*)?$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)ADDLVv4i16v$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(s|h|b)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RHADD(v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RSHR(v2i32|v4i16|v8i8)_shift$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)RSHRd$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^R?SHRN(v2i32|v4i16|v8i8)_shift$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)?(MAX|MIN)V(v4i16v|v4i32v)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instrs ADDVv4i16v)>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^S(L|R)I(d|(v8i8|v4i16|v2i32)_shift)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)ADDLVv8i8v$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)?(MAX|MIN)V(v8i8v|v8i16v)$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instrs ADDVv8i8v)>; def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc], (instregex "^MUL(v2i32|v4i16|v8i8)(_indexed)?$")>; def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc], (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>; def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc], (instregex "^SQDMULL(i16|i32)$")>; def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA], (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>; def : InstRW<[FalkorWr_1VXVY_5cyc], (instregex "^(S|U)?(MAX|MIN)Vv16i8v$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instrs ADDVv4i32v)>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instrs ADDVv8i16v)>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(ADD|SUB)HNv.*$")>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(S|U)ABA(v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_2VXVY_5cyc], (instrs ADDVv16i8v)>; def : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32)_shift?$")>; def : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^R(ADD|SUB)HNv.*$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs ADDPv2i64)>; // sz==11 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)ADDLv.*$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i16)(_v.*)?$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i64)_shift$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SUBLv.*$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS)(v16i8|v2i64|v4i32|v8i16)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^ADDP(v4i32|v8i16|v16i8)$")>; // sz!=11 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v16i8|v2i64|v4i32|v8i16)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v16i8|v2i64|v4i32|v8i16)rz$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CMTST|PMUL)(v16i8|v2i64|v4i32|v8i16)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^PMULL(v8i8|v16i8)$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^SHL(v16i8|v8i16|v4i32|v2i64)_shift$")>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)ABD(v16i8|v8i16|v4i32|v2i64)$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)ABDLv.*$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)(ADALP|QADD)(v16i8|v8i16|v4i32|v2i64)(_v.*)?$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)QSHLU?(v2i64|v4i32|v8i16|v16i8)_shift$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(S|U)RSHR(v2i64|v4i32|v8i16|v16i8)_shift$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^R?SHRN(v2i64|v4i32|v8i16|v16i8)_shift$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^PMULL(v1i64|v2i64)$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^S(L|R)I(v16i8|v8i16|v4i32|v2i64)_shift$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc], (instregex "^(MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc], (instregex "^SQDMULLv.*$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], (instregex "^SQRDML(A|S)H(v16i8|v8i16|v4i32)(_indexed)?$")>; def : InstRW<[FalkorWr_3VXVY_3cyc], (instregex "^(S|U)ADDLVv4i32v$")>; def : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^(S|U)ADDLVv8i16v$")>; def : InstRW<[FalkorWr_3VXVY_6cyc], (instregex "^(S|U)ADDLVv16i8v$")>; def : InstRW<[FalkorWr_4VXVY_2cyc], (instregex "^(S|U)(ADD|SUB)Wv.*$")>; def : InstRW<[FalkorWr_4VXVY_3cyc], (instregex "^(S|U)ABALv.*$")>; def : InstRW<[FalkorWr_4VXVY_4cyc], (instregex "^(S|U)ABA(v16i8|v8i16|v4i32)$")>; def : InstRW<[FalkorWr_VMUL32_1VXVY_4cyc, FalkorReadVMA], (instregex "^SQD(MLAL|MLSL)(i16|i32|v1i32_indexed|v1i64_indexed)$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], (instregex "^SQD(MLAL|MLSL)v[248].*$")>; // SIMD Load Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instrs LD2i64)>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], (instrs LD2i64_POST)>; def : InstRW<[FalkorWr_1LD_1VXVY_4cyc, FalkorReadIncLd], (instregex "^LD1i(8|16|32)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1VXVY_4cyc, FalkorReadIncLd], (instregex "^LD1i(8|16|32)_POST$")>; def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD1Twov(8b|4h|2s|1d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>; def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD2Twov(8b|4h|2s)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD2Twov(8b|4h|2s)_POST$")>; def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD2Rv(8b|4h|2s|1d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD2Rv(8b|4h|2s|1d)_POST$")>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD1Twov(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD2Twov(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD2Rv(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], (instregex "^LD2Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instrs LD3i64)>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], (instrs LD3i64_POST)>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorReadIncLd], (instrs LD4i64)>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorReadIncLd], (instrs LD4i64_POST)>; def : InstRW<[FalkorWr_1LD_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD2i(8|16|32)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD2i(8|16|32)_POST$")>; def : InstRW<[FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD1Threev(8b|4h|2s|1d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>; def : InstRW<[FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD3Rv(8b|4h|2s|1d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_1none_3cyc, FalkorReadIncLd], (instregex "^LD3Rv(8b|4h|2s|1d)_POST$")>; def : InstRW<[FalkorWr_3LD_3cyc, FalkorReadIncLd], (instregex "^LD1Threev(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_3LD_3cyc, FalkorReadIncLd], (instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_3LD_3cyc, FalkorReadIncLd], (instrs LD3Threev2d)>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_3LD_3cyc, FalkorReadIncLd], (instrs LD3Threev2d_POST)>; def : InstRW<[FalkorWr_3LD_3cyc, FalkorReadIncLd], (instregex "^LD3Rv(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_3LD_3cyc, FalkorReadIncLd], (instregex "^LD3Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_1LD_3VXVY_4cyc, FalkorReadIncLd], (instregex "^LD3i(8|16|32)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3VXVY_4cyc, FalkorReadIncLd], (instregex "^LD3i(8|16|32)_POST$")>; def : InstRW<[FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], (instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>; def : InstRW<[FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], (instregex "^LD4Rv(8b|4h|2s|1d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2none_3cyc, FalkorReadIncLd], (instregex "^LD4Rv(8b|4h|2s|1d)_POST$")>; def : InstRW<[FalkorWr_4LD_3cyc, FalkorReadIncLd], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_4LD_3cyc, FalkorReadIncLd], (instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_4LD_3cyc, FalkorReadIncLd], (instrs LD4Fourv2d)>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_4LD_3cyc, FalkorReadIncLd], (instrs LD4Fourv2d_POST)>; def : InstRW<[FalkorWr_4LD_3cyc, FalkorReadIncLd], (instregex "^LD4Rv(16b|8h|4s|2d)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_4LD_3cyc, FalkorReadIncLd], (instregex "^LD4Rv(16b|8h|4s|2d)_POST$")>; def : InstRW<[FalkorWr_1LD_4VXVY_4cyc, FalkorReadIncLd], (instregex "^LD4i(8|16|32)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_4VXVY_4cyc, FalkorReadIncLd], (instregex "^LD4i(8|16|32)_POST$")>; def : InstRW<[FalkorWr_2LD_2VXVY_1none_4cyc, FalkorReadIncLd], (instregex "^LD3Threev(8b|4h|2s)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_1none_4cyc, FalkorReadIncLd], (instregex "^LD3Threev(8b|4h|2s)_POST$")>; def : InstRW<[FalkorWr_2LD_2VXVY_2none_4cyc, FalkorReadIncLd], (instregex "^LD4Fourv(8b|4h|2s)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_2none_4cyc, FalkorReadIncLd], (instregex "^LD4Fourv(8b|4h|2s)_POST$")>; def : InstRW<[FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD3Threev(16b|8h|4s)$")>; def : InstRW<[FalkorWr_2LD_2VXVY_2LD_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD4Fourv(16b|8h|4s)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_1XYZ_2LD_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD3Threev(16b|8h|4s)_POST$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_2VXVY_2LD_1XYZ_2VXVY_4cyc, FalkorReadIncLd], (instregex "^LD4Fourv(16b|8h|4s)_POST$")>; // Arithmetic and Logical Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CCMN|CCMP)(W|X)(r|i)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ADC(S)?(W|X)r$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ADD(S)?(W|X)r(r|i)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^AND(S)?(W|X)r(i|r|s)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^BIC(S)?(W|X)r(r|s)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EON(W|X)r(r|s)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EOR(W|X)r(i|r|s)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORN(W|X)r(r|s)$")>; def : InstRW<[FalkorWr_ORRi], (instregex "^ORR(W|X)ri$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^ORR(W|X)r(r|s)$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SBC(S)?(W|X)r$")>; def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^SUB(S)?(W|X)r(r|i)$")>; def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^ADD(S)?(W|X)r(s|x|x64)$")>; def : InstRW<[FalkorWr_ADDSUBsx], (instregex "^SUB(S)?(W|X)r(s|x|x64)$")>; // SIMD Miscellaneous Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^CPY(i8|i16|i32|i64)$")>; def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^INSv(i8|i16)(gpr|lane)$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^(S|U)MOVv.*$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL)v8i8$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs EXTv8i8)>; def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)$")>; // imm fwd def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs TBLv8i8One)>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs NOTv8i8)>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^REV(16|32|64)v.*$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|v4i16|v4i32|v8i8|v8i16|v16i8)$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "(S|U)QXTU?Nv.*$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instrs FRECPEv1i32, FRECPEv1i64, FRSQRTEv1i32, FRSQRTEv1i64, FRECPEv2f32, FRSQRTEv2f32)>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instrs FRECPXv1i32, FRECPXv1i64)>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instrs URECPEv2i32, URSQRTEv2i32)>; def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], (instrs FRECPS32, FRSQRTS32, FRECPSv2f32, FRSQRTSv2f32)>; def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], (instrs FRECPS64, FRSQRTS64)>; def : InstRW<[FalkorWr_1GTOV_1VXVY_2cyc], (instregex "^INSv(i32|i64)(gpr|lane)$")>; def : InstRW<[FalkorWr_2GTOV_1cyc], (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIF|BIT|BSL)v16i8$")>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs EXTv16i8)>; def : InstRW<[FalkorWr_2VXVY_0cyc], (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)$")>; // imm fwd def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs NOTv16i8)>; def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs TBLv16i8One)>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instrs FRECPEv2f64, FRECPEv4f32, FRSQRTEv2f64, FRSQRTEv4f32)>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instrs URECPEv4i32, URSQRTEv4i32)>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instrs TBLv8i8Two)>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^TBX(v8|v16)i8One$")>; def : InstRW<[FalkorWr_FMUL32_2VXVY_5cyc], (instrs FRECPSv4f32, FRSQRTSv4f32)>; def : InstRW<[FalkorWr_FMUL64_2VXVY_6cyc], (instrs FRECPSv2f64, FRSQRTSv2f64)>; def : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^TBL(v8i8Three|v16i8Two)$")>; def : InstRW<[FalkorWr_3VXVY_5cyc], (instregex "^TBX(v8i8Two|v16i8Two)$")>; def : InstRW<[FalkorWr_4VXVY_6cyc], (instregex "^TBL(v8i8Four|v16i8Three)$")>; def : InstRW<[FalkorWr_4VXVY_6cyc], (instregex "^TBX(v8i8Three|v16i8Three)$")>; def : InstRW<[FalkorWr_5VXVY_7cyc], (instrs TBLv16i8Four)>; def : InstRW<[FalkorWr_5VXVY_7cyc], (instregex "^TBX(v8i8Four|v16i8Four)$")>; // SIMD Store Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STR(Q|D|S|H|B)ui$")>; def : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STR(Q|D|S|H|B)(post|pre)$")>; def : InstRW<[FalkorWr_STRVro, ReadDefault, FalkorReadIncSt], (instregex "^STR(D|S|H|B)ro(W|X)$")>; def : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STPQi$")>; def : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STPQ(post|pre)$")>; def : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STP(D|S)(i)$")>; def : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STP(D|S)(post|pre)$")>; def : InstRW<[FalkorWr_STRQro, ReadDefault, FalkorReadIncSt], (instregex "^STRQro(W|X)$")>; def : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STUR(Q|D|S|B|H)i$")>; def : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instrs STNPDi, STNPSi)>; def : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instrs STNPQi)>; def : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))$")>; def : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>; def : InstRW<[FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST2(Two(v8b|v4h|v2s)|(i8|i16|i32|i64))$")>; def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>; def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VSD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST2(Two(v8b|v4h|v2s)|(i8|i16|i32|i64))_POST$")>; def : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>; def : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST2Two(v16b|v8h|v4s|v2d)$")>; def : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST3(i8|i16|i32|i64)$")>; def : InstRW<[FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST4(i8|i16|i32|i64)$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST2Two(v16b|v8h|v4s|v2d)_POST$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST3(i8|i16|i32|i64)_POST$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VSD_2ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST4(i8|i16|i32|i64)_POST$")>; def : InstRW<[FalkorWr_1VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST3Three(v8b|v4h|v2s)$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_1VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST3Three(v8b|v4h|v2s)_POST$")>; def : InstRW<[FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1Three(v16b|v8h|v4s|v2d)$")>; def : InstRW<[FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], (instrs ST3Threev2d)>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1Three(v16b|v8h|v4s|v2d)_POST$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_3VSD_3ST_0cyc, ReadDefault, FalkorReadIncSt], (instrs ST3Threev2d_POST)>; def : InstRW<[FalkorWr_2VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST4Four(v8b|v4h|v2s)$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VXVY_2ST_2VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST4Four(v8b|v4h|v2s)_POST$")>; def : InstRW<[FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1Four(v16b|v8h|v4s|v2d)$")>; def : InstRW<[FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], (instrs ST4Fourv2d)>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST1Four(v16b|v8h|v4s|v2d)_POST$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VSD_4ST_0cyc, ReadDefault, FalkorReadIncSt], (instrs ST4Fourv2d_POST)>; def : InstRW<[FalkorWr_2VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST3Three(v16b|v8h|v4s)$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_2VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST3Three(v16b|v8h|v4s)_POST$")>; def : InstRW<[FalkorWr_4VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST4Four(v16b|v8h|v4s)$")>; // FIXME: This is overly conservative in the imm POST case (no XYZ used in that case). def : InstRW<[FalkorWr_1XYZ_1cyc, FalkorWr_4VXVY_4ST_4VSD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^ST4Four(v16b|v8h|v4s)_POST$")>; // Branch Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1none_0cyc], (instrs B, TCRETURNdi)>; def : InstRW<[FalkorWr_1Z_0cyc], (instregex "^(BR|RET|(CBZ|CBNZ|TBZ|TBNZ)(W|X))$")>; def : InstRW<[FalkorWr_1Z_0cyc], (instrs RET_ReallyLR, TCRETURNri)>; def : InstRW<[FalkorWr_1ZB_0cyc], (instrs Bcc)>; def : InstRW<[FalkorWr_1XYZB_0cyc], (instrs BL)>; def : InstRW<[FalkorWr_1Z_1XY_0cyc], (instrs BLR)>; // Cryptography Extensions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1VXVY_1cyc], (instrs SHA1Hrr)>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instrs AESIMCrr, AESMCrr)>; def : InstRW<[FalkorWr_2VXVY_3cyc], (instrs AESDrr, AESErr)>; def : InstRW<[FalkorWr_2VXVY_2cyc], (instrs SHA1SU0rrr, SHA1SU1rr, SHA256SU0rr)>; def : InstRW<[FalkorWr_1VX_1VY_4cyc], (instregex "^SHA1(C|M|P)rrr$")>; def : InstRW<[FalkorWr_1VX_1VY_5cyc], (instrs SHA256H2rrr, SHA256Hrrr)>; def : InstRW<[FalkorWr_4VXVY_3cyc], (instrs SHA256SU1rrr)>; // FP Load Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDUR(Q|D|S|H|B)i$")>; def : InstRW<[FalkorWr_LDRro, FalkorReadIncLd], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instrs LDNPQi)>; def : InstRW<[FalkorWr_2LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instrs LDPQi)>; def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "LDNP(D|S)i$")>; def : InstRW<[FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "LDP(D|S)i$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_1none_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "LDP(D|S)(pre|post)$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_2LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "^LDPQ(pre|post)$")>; // FP Data Processing Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCCMP(E)?(S|D)rr$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCMP(E)?(S|D)r(r|i)$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>; def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCSEL(S|D)rrr$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^F(MAX|MIN)(NM)?(S|D)rr$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^F(MAX|MIN)(NM)?Pv2i(32|64)p$")>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instrs FCVTSHr, FCVTDHr)>; def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^FABD(32|64)$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>; def : InstRW<[FalkorWr_1VXVY_3cyc], (instrs FCVTHSr, FCVTHDr)>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instrs FCVTSDr, FCVTDSr)>; def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc], (instregex "^F(N)?MULSrr$")>; def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc], (instregex "^F(N)?MULDrr$")>; def : InstRW<[FalkorWr_1VX_1VY_10cyc],(instrs FDIVSrr)>; def : InstRW<[FalkorWr_1VX_1VY_14cyc],(instrs FDIVDrr)>; def : InstRW<[FalkorWr_1VX_1VY_12cyc],(instrs FSQRTSr)>; def : InstRW<[FalkorWr_1VX_1VY_21cyc],(instrs FSQRTDr)>; def : InstRW<[FalkorWr_FMUL32_1VXVY_5cyc, ReadDefault, ReadDefault, FalkorReadFMA32], (instregex "^F(N)?M(ADD|SUB)Srrr$")>; def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, ReadDefault, ReadDefault, FalkorReadFMA64], (instregex "^F(N)?M(ADD|SUB)Drrr$")>; // FP Miscellaneous Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>; def : InstRW<[FalkorWr_1GTOV_0cyc], (instregex "^FMOV(S|D)i$")>; // imm fwd def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVTZ(S|U)S(W|X)(D|S)ri$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVTZ(S|U)(d|s)$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(SW|DX|DXHigh)r$")>; def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "^FMOV(Sr|Dr|v.*_ns)$")>; // imm fwd // FIXME: We are currently generating movi v0.2d, #0 for these, which is worse than fmov wzr/xzr def : InstRW<[FalkorWr_2VXVY_0cyc], (instrs FMOVD0, FMOVS0)>; // imm fwd def : InstRW<[FalkorWr_1GTOV_4cyc], (instregex "^(S|U)CVTF(S|U)(W|X)(D|S)ri$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>; def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>; // Load Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1ST_0cyc], (instrs PRFMui, PRFMl)>; def : InstRW<[FalkorWr_1ST_0cyc], (instrs PRFUMi)>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "^LDNP(W|X)i$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "^LDP(W|X)i$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "^LDP(W|X)(post|pre)$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDR(BB|HH|W|X)ui$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>; def : InstRW<[FalkorWr_LDRro, FalkorReadIncLd], (instregex "^LDR(BB|HH|W|X)ro(W|X)$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDR(W|X)l$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDTR(B|H|W|X)i$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LDUR(BB|HH|W|X)i$")>; def : InstRW<[FalkorWr_PRFMro], (instregex "^PRFMro(W|X)$")>; def : InstRW<[FalkorWr_1LD_4cyc, FalkorWr_none_4cyc, FalkorReadIncLd], (instrs LDPSWi)>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_4cyc, FalkorWr_none_4cyc, FalkorReadIncLd], (instregex "^LDPSW(post|pre)$")>; def : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>; def : InstRW<[FalkorWr_LdInc_none_2cyc, FalkorWr_1LD_4cyc, FalkorReadIncLd], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>; def : InstRW<[FalkorWr_LDRSro, FalkorReadIncLd], (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>; def : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], (instrs LDRSWl)>; def : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>; def : InstRW<[FalkorWr_1LD_4cyc, FalkorReadIncLd], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>; // Miscellaneous Data-Processing Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(S|U)?BFM(W|X)ri$")>; def : InstRW<[FalkorWr_1X_2cyc], (instregex "^CRC32.*$")>; def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>; def : InstRW<[FalkorWr_2XYZ_2cyc], (instregex "^EXTR(W|X)rri$")>; // Divide and Multiply Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_IMUL64_1X_4cyc, ReadDefault, ReadDefault, FalkorReadIMA64], (instregex "^(S|U)M(ADD|SUB)Lrrr$")>; def : InstRW<[FalkorWr_IMUL32_1X_2cyc, ReadDefault, ReadDefault, FalkorReadIMA32], (instregex "^M(ADD|SUB)Wrrr$")>; def : InstRW<[FalkorWr_IMUL64_1X_5cyc], (instregex "^(S|U)MULHrr$")>; def : InstRW<[FalkorWr_IMUL64_1X_5cyc, ReadDefault, ReadDefault, FalkorReadIMA64], (instregex "^M(ADD|SUB)Xrrr$")>; def : InstRW<[FalkorWr_1X_1Z_8cyc], (instregex "^(S|U)DIVWr$")>; def : InstRW<[FalkorWr_1X_1Z_11cyc], (instregex "^(S|U)DIVXr$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc], (instregex "^(S|U)MULLv.*$")>; def : InstRW<[FalkorWr_VMUL32_2VXVY_4cyc, FalkorReadVMA], (instregex "^(S|U)(MLAL|MLSL)v.*$")>; // Move and Shift Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(LSLV|LSRV|ASRV|RORV)(W|X)r$")>; def : InstRW<[FalkorWr_1XYZ_0cyc], (instregex "^MOVK(W|X)i$")>; // imm fwd def : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^ADRP?$")>; // imm fwd def : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^MOVN(W|X)i$")>; // imm fwd def : InstRW<[FalkorWr_MOVZ], (instregex "^MOVZ(W|X)i$")>; def : InstRW<[FalkorWr_1XYZ_0cyc], (instrs MOVi32imm, MOVi64imm)>; // imm fwd (approximation) def : InstRW<[WriteSequence<[FalkorWr_1XYZ_1cyc, FalkorWr_1XYZ_1cyc]>], (instrs MOVaddr, MOVaddrBA, MOVaddrCP, MOVaddrEXT, MOVaddrJT, MOVaddrTLS)>; def : InstRW<[WriteSequence<[FalkorWr_1LD_3cyc, FalkorWr_1XYZ_1cyc]>], (instrs LOADgot)>; // Other Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>; def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, SVC)>; def : InstRW<[FalkorWr_1ST_0cyc], (instrs SYSxt, SYSLxt)>; def : InstRW<[FalkorWr_1Z_0cyc], (instrs MSRpstateImm1, MSRpstateImm4)>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^(LDAR(B|H|W|X)|LDAXR(B|H|W|X)|LDXR(B|H|W|X))$")>; def : InstRW<[FalkorWr_1LD_3cyc, FalkorWr_none_3cyc, FalkorReadIncLd], (instregex "^(LDAXP(W|X)|LDXP(W|X))$")>; def : InstRW<[FalkorWr_1LD_3cyc], (instrs MRS, MOVbaseTLS)>; def : InstRW<[FalkorWr_1LD_1Z_3cyc], (instrs DRPS)>; def : InstRW<[FalkorWr_1SD_1ST_0cyc], (instrs MSR)>; def : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instrs STNPWi, STNPXi)>; def : InstRW<[FalkorWr_2LD_1Z_3cyc], (instrs ERET)>; def : InstRW<[FalkorWr_1ST_1SD_1LD_3cyc], (instregex "^LDC.*$")>; def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STLR(B|H|W|X)$")>; def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STXP(W|X)$")>; def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STXR(B|H|W|X)$")>; def : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc, ReadDefault, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STLXP(W|X)$")>; def : InstRW<[FalkorWr_2LD_1ST_1SD_3cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STLXR(B|H|W|X)$")>; // Store Instructions // ----------------------------------------------------------------------------- def : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STP(W|X)i$")>; def : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1SD_1ST_0cyc, ReadDefault, ReadDefault, FalkorReadIncSt], (instregex "^STP(W|X)(post|pre)$")>; def : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STR(BB|HH|W|X)ui$")>; def : InstRW<[FalkorWr_StInc_none_2cyc, FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STR(BB|HH|W|X)(post|pre)$")>; def : InstRW<[FalkorWr_STRro, ReadDefault, FalkorReadIncSt], (instregex "^STR(BB|HH|W|X)ro(W|X)$")>; def : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STTR(B|H|W|X)i$")>; def : InstRW<[FalkorWr_1SD_1ST_0cyc, ReadDefault, FalkorReadIncSt], (instregex "^STUR(BB|HH|W|X)i$")>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedKryo.td000064400000000000000000000141410072674642500256000ustar 00000000000000//==- AArch64SchedKryo.td - Qualcomm Kryo Scheduling Defs ---*- tablegen -*-==// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the machine model for Qualcomm Kryo to support // instruction scheduling and other instruction cost heuristics. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // The issue width is set to five, matching the five issue queues for expanded // uops. Now, the latency spreadsheet has information based on fragmented uops, // but these do not actually take up an issue queue. def KryoModel : SchedMachineModel { let IssueWidth = 5; // 5-wide issue for expanded uops let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer let LoadLatency = 4; // Optimistic load latency let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch // Enable partial & runtime unrolling. The magic number is chosen based on // experiments and benchmarking data. let LoopMicroOpBufferSize = 16; let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } //===----------------------------------------------------------------------===// // Define each kind of processor resource and number available on Kryo. let SchedModel = KryoModel in { def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops def KryoUnitX : ProcResGroup<[KryoUnitXA, // Type X micro-ops KryoUnitXB]>; def KryoUnitY : ProcResGroup<[KryoUnitYA, // Type Y micro-ops KryoUnitYB]>; def KryoUnitXY : ProcResGroup<[KryoUnitXA, // Type XY micro-ops KryoUnitXB, KryoUnitYA, KryoUnitYB]>; def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops def KryoUnitLS : ProcResGroup<[KryoUnitLSA, // Type LS micro-ops KryoUnitLSB]>; } let SchedModel = KryoModel in { //===----------------------------------------------------------------------===// // Map the target-defined scheduler read/write resources and latency for // Kryo. def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 2; let NumMicroOps = 2; } def : WriteRes { let Latency = 2; let NumMicroOps = 2; } def : WriteRes { let Latency = 2; let NumMicroOps = 2; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 8; let NumMicroOps = 1; } // Fragent -1 def : WriteRes { let Latency = 8; let NumMicroOps = 1; } // Fragent -1 def : WriteRes { let Latency = 5; } def : WriteRes { let Latency = 5; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 3; let NumMicroOps = 2; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; let NumMicroOps = 2; } def : WriteRes { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1 def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 4; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 4; } def : WriteRes { let Unsupported = 1; } // No forwarding logic is modelled yet. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; //===----------------------------------------------------------------------===// // Specialize the coarse model by associating instruction groups with the // subtarget-defined types. As the modeled is refined, this will override most // of the above SchedWriteRes and SchedAlias mappings. // Miscellaneous // ----------------------------------------------------------------------------- def : InstRW<[WriteI], (instrs COPY)>; // Detailed Refinedments // ----------------------------------------------------------------------------- include "AArch64SchedKryoDetails.td" } // SchedModel = KryoModel capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedKryoDetails.td000064400000000000000000002451320072674642500271140ustar 00000000000000//=- AArch64SchedKryoDetails.td - QC Kryo Scheduling Defs ----*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the uop and latency details for the machine model for the // Qualcomm Kryo subtarget. // //===----------------------------------------------------------------------===// def KryoWrite_3cyc_X_noRSV_138ln : SchedWriteRes<[KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_X_noRSV_138ln], (instregex "(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)")>; def KryoWrite_3cyc_X_X_139ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_X_X_139ln], (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>; def KryoWrite_4cyc_XY_XY_noRSV_172ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_XY_XY_noRSV_172ln], (instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>; def KryoWrite_4cyc_XY_XY_XY_XY_178ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> { let Latency = 4; let NumMicroOps = 4; } def : InstRW<[KryoWrite_4cyc_XY_XY_XY_XY_178ln], (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>; def KryoWrite_3cyc_XY_XY_XY_XY_177ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_XY_XY_XY_XY_177ln], (instregex "(S|U)ABALv.*")>; def KryoWrite_3cyc_XY_XY_166ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_166ln], (instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_3cyc_XY_noRSV_159ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_159ln], (instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>; def KryoWrite_3cyc_XY_XY_165ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_165ln], (instregex "(S|U)ABDLv.*")>; def KryoWrite_3cyc_X_noRSV_154ln : SchedWriteRes<[KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_X_noRSV_154ln], (instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>; def KryoWrite_3cyc_X_X_155ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_X_X_155ln], (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>; def KryoWrite_2cyc_XY_XY_151ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_151ln], (instregex "(S|U)(ADD|SUB)Lv.*")>; def KryoWrite_2cyc_XY_noRSV_148ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_148ln], (instregex "((S|U)ADDLP|ABS)(v2i32|v4i16|v8i8)(_v.*)?")>; def KryoWrite_2cyc_XY_XY_150ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_150ln], (instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>; def KryoWrite_3cyc_XY_XY_XY_noRSV_179ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_XY_XY_XY_noRSV_179ln], (instrs SADDLVv4i32v, UADDLVv4i32v)>; def KryoWrite_5cyc_XY_XY_XY_noRSV_180ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY]> { let Latency = 5; let NumMicroOps = 4; } def : InstRW<[KryoWrite_5cyc_XY_XY_XY_noRSV_180ln], (instrs SADDLVv8i16v, UADDLVv8i16v)>; def KryoWrite_6cyc_XY_XY_X_noRSV_181ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX]> { let Latency = 6; let NumMicroOps = 4; } def : InstRW<[KryoWrite_6cyc_XY_XY_X_noRSV_181ln], (instrs SADDLVv16i8v, UADDLVv16i8v)>; def KryoWrite_3cyc_XY_noRSV_158ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_158ln], (instrs SADDLVv4i16v, UADDLVv4i16v, ADDVv4i16v)>; def KryoWrite_4cyc_X_noRSV_169ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_169ln], (instrs SADDLVv8i8v, UADDLVv8i8v, ADDVv8i8v)>; def KryoWrite_2cyc_XY_XY_XY_XY_176ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 4; } def : InstRW<[KryoWrite_2cyc_XY_XY_XY_XY_176ln], (instregex "(S|U)(ADDW|SUBW)v.*")>; def KryoWrite_4cyc_X_noRSV_40ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_40ln], (instregex "(S|U)CVTFS(W|X)(D|S)ri")>; def KryoWrite_4cyc_X_noRSV_97ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_97ln], (instregex "(S|U)CVTFU(W|X)(D|S)ri")>; def KryoWrite_4cyc_X_noRSV_110ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_110ln], (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>; def KryoWrite_4cyc_X_X_114ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_X_114ln], (instregex "(S|U)CVTF(v2i64|v4i32|v2f64|v4f32)(_shift)?")>; def KryoWrite_1cyc_XA_Y_98ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XA_Y_98ln], (instregex "(S|U)DIV(_Int)?(W|X)r")>; def KryoWrite_2cyc_XY_XY_152ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_152ln], (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>; def KryoWrite_2cyc_XY_noRSV_149ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_149ln], (instregex "((S|U)H(ADD|SUB)|ADDP)(v8i8|v4i16|v2i32)")>; def KryoWrite_4cyc_X_70ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_X_70ln], (instregex "(S|U)(MADDL|MSUBL)rrr")>; def KryoWrite_4cyc_X_X_191ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_X_191ln], (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>; def KryoWrite_1cyc_XY_195ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_195ln], (instregex "(S|U)MOVv.*")>; def KryoWrite_5cyc_X_71ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 1; } def : InstRW<[KryoWrite_5cyc_X_71ln], (instrs SMULHrr, UMULHrr)>; def KryoWrite_3cyc_XY_noRSV_186ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_186ln], (instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>; def KryoWrite_3cyc_XY_XY_187ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_187ln], (instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_3cyc_XY_noRSV_69ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_69ln], (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>; def KryoWrite_3cyc_XY_noRSV_248ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_248ln], (instregex "(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>; def KryoWrite_3cyc_XY_XY_250ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_250ln], (instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>; def KryoWrite_3cyc_XY_noRSV_246ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_246ln], (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>; def KryoWrite_3cyc_XY_XY_251ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_251ln], (instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>; def KryoWrite_6cyc_XY_X_238ln : SchedWriteRes<[KryoUnitXY, KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_XY_X_238ln], (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v16i8|v8i16|v4i32)_shift$")>; def KryoWrite_3cyc_XY_noRSV_249ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_249ln], (instregex "((S|U)QR?SHRN|SQR?SHRUN)(s|h|b)?")>; def KryoWrite_6cyc_XY_X_noRSV_252ln : SchedWriteRes<[KryoUnitXY, KryoUnitX]> { let Latency = 6; let NumMicroOps = 3; } def : InstRW<[KryoWrite_6cyc_XY_X_noRSV_252ln], (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v8i8|v4i16|v2i32)_shift?")>; def KryoWrite_3cyc_XY_noRSV_161ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_161ln], (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>; def KryoWrite_3cyc_XY_noRSV_163ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_163ln], (instregex "(S|U)QXTU?N(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)")>; def KryoWrite_3cyc_XY_noRSV_162ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_162ln], (instregex "(S|U)QXTU?N(v1i8|v1i16|v1i32)")>; def KryoWrite_3cyc_XY_noRSV_247ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_247ln], (instregex "(S|U)RSHR(d|(v8i8|v4i16|v2i32)_shift)$")>; def KryoWrite_2cyc_XY_noRSV_239ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_239ln], (instregex "(S|U)SHL(d|v8i8|v4i16|v2i32|v1i64)$")>; def KryoWrite_2cyc_XY_XY_243ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_243ln], (instregex "(S|U)SHL(v16i8|v8i16|v4i32|v2i64)$")>; def KryoWrite_2cyc_XY_XY_241ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_241ln], (instregex "(S|U)?SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>; def KryoWrite_2cyc_XY_noRSV_240ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_240ln], (instregex "((S|U)SHR|SHL)(d|(v8i8|v4i16|v2i32)_shift)$")>; def KryoWrite_2cyc_XY_XY_242ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_242ln], (instregex "((S|U)SHR|SHL)(v16i8|v8i16|v4i32|v2i64)_shift$")>; def KryoWrite_2cyc_XY_XY_183ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_183ln], (instregex "(S|U)(MAX|MIN)P?(v16i8|v8i16|v4i32)")>; def KryoWrite_2cyc_XY_noRSV_182ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_182ln], (instregex "(S|U)(MAX|MIN)P?(v8i8|v4i16|v2i32)")>; def KryoWrite_3cyc_XY_noRSV_184ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_184ln], (instregex "(S|U)(MAX|MIN)V(v4i16v|v8i8v|v4i32)")>; def KryoWrite_4cyc_X_noRSV_185ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_185ln], (instregex "(S|U)(MAX|MIN)V(v16i8v|v8i16v)")>; def KryoWrite_2cyc_XY_noRSV_67ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_67ln], (instrs ABSv1i64)>; def KryoWrite_1cyc_XY_63ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_63ln, ReadI, ReadI], (instregex "ADC.*")>; def KryoWrite_1cyc_XY_63_1ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_63_1ln], (instregex "ADR.*")>; def KryoWrite_1cyc_XY_62ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_62ln, ReadI], (instregex "ADDS?(W|X)ri")>; def KryoWrite_2cyc_XY_XY_64ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_64ln, ReadI, ReadI], (instregex "ADDS?(W|X)r(r|s|x)(64)?")>; def KryoWrite_1cyc_XY_noRSV_65ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_65ln], (instrs ADDv1i64)>; def KryoWrite_1cyc_XY_noRSV_144ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_144ln], (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>; def KryoWrite_1cyc_XY_XY_146ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_146ln], (instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_4cyc_XY_X_noRSV_171ln : SchedWriteRes<[KryoUnitXY, KryoUnitX]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_XY_X_noRSV_171ln], (instregex "(ADD|SUB)HNv.*")>; def KryoWrite_1cyc_XY_noRSV_66ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_66ln], (instrs ADDPv2i64p)>; def KryoWrite_2cyc_XY_XY_153ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_153ln], (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_3cyc_XY_XY_noRSV_170ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_XY_XY_noRSV_170ln], (instrs ADDVv4i32v)>; def KryoWrite_4cyc_XY_XY_noRSV_173ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_XY_XY_noRSV_173ln], (instrs ADDVv8i16v)>; def KryoWrite_5cyc_XY_X_noRSV_174ln : SchedWriteRes<[KryoUnitXY, KryoUnitX]> { let Latency = 5; let NumMicroOps = 3; } def : InstRW<[KryoWrite_5cyc_XY_X_noRSV_174ln], (instrs ADDVv16i8v)>; def KryoWrite_3cyc_XY_XY_X_X_27ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_XY_XY_X_X_27ln], (instrs AESDrr, AESErr)>; def KryoWrite_2cyc_X_X_22ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_X_X_22ln], (instrs AESIMCrr, AESMCrr)>; def KryoWrite_1cyc_XY_noRSV_76ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_76ln], (instregex "((AND|ORN|EOR|EON)S?(Wr[rsi]|v8i8|v4i16|v2i32)|(ORR|BIC)S?(Wr[rs]|v8i8|v4i16|v2i32))")>; def KryoWrite_1cyc_XY_XY_79ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_79ln], (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>; def KryoWrite_1cyc_X_72ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_X_72ln], (instregex "(S|U)?BFM.*")>; def KryoWrite_1cyc_XY_noRSV_77ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_77ln], (instregex "(BIC|ORR)S?Wri")>; def KryoWrite_1cyc_XY_XY_78ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_78ln], (instregex "(BIC|ORR)S?Xri")>; def KryoWrite_1cyc_X_noRSV_74ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_noRSV_74ln], (instrs BIFv8i8, BITv8i8, BSLv8i8)>; def KryoWrite_1cyc_X_X_75ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_75ln], (instrs BIFv16i8, BITv16i8, BSLv16i8)>; def KryoWrite_0cyc_noRSV_11ln : SchedWriteRes<[]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_noRSV_11ln], (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>; def KryoWrite_0cyc_XY_16ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_XY_16ln, ReadI], (instregex "(CCMN|CCMP)(W|X)i")>; def KryoWrite_0cyc_XY_16_1ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_XY_16_1ln, ReadI, ReadI], (instregex "(CCMN|CCMP)(W|X)r")>; def KryoWrite_2cyc_XY_3ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 1; } def : InstRW<[KryoWrite_2cyc_XY_3ln, ReadI], (instregex "(CLS|CLZ)(W|X)r")>; def KryoWrite_2cyc_XY_noRSV_7ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_7ln], (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>; def KryoWrite_2cyc_XY_XY_8ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_8ln], (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>; def KryoWrite_2cyc_XY_noRSV_80ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_80ln], (instregex "CM(EQ|GE|HS|GT|HI|TST)(v8i8|v4i16|v2i32|v1i64)$")>; def KryoWrite_2cyc_XY_XY_83ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_83ln], (instregex "CM(EQ|GE|HS|GT|HI|TST)(v16i8|v8i16|v4i32|v2i64)$")>; def KryoWrite_2cyc_XY_noRSV_81ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_81ln], (instregex "CM(EQ|LE|GE|GT|LT)(v8i8|v4i16|v2i32|v1i64)rz$")>; def KryoWrite_2cyc_XY_XY_82ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_82ln], (instregex "CM(EQ|LE|GE|GT|LT)(v16i8|v8i16|v4i32|v2i64)rz$")>; def KryoWrite_3cyc_XY_4ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_XY_4ln, ReadI, ReadISReg], (instregex "CRC32.*")>; def KryoWrite_1cyc_XY_20ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_20ln, ReadI, ReadI], (instregex "CSEL(W|X)r")>; def KryoWrite_1cyc_X_17ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_X_17ln, ReadI, ReadI], (instregex "(CSINC|CSNEG)(W|X)r")>; def KryoWrite_1cyc_XY_18ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_18ln, ReadI, ReadI], (instregex "(CSINV)(W|X)r")>; def KryoWrite_3cyc_LS_X_13ln : SchedWriteRes<[KryoUnitLS, KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_X_13ln], (instrs DRPS)>; def KryoWrite_0cyc_LS_10ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_LS_10ln], (instrs DSB, DMB, CLREX)>; def KryoWrite_1cyc_X_noRSV_196ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_noRSV_196ln], (instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>; def KryoWrite_1cyc_X_X_197ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_197ln], (instregex "DUP(v16i8|v8i16|v4i32|v2i64)(gpr|lane)")>; def KryoWrite_3cyc_LS_LS_X_15ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_LS_X_15ln], (instrs ERET)>; def KryoWrite_1cyc_X_noRSV_207ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_noRSV_207ln], (instrs EXTv8i8)>; def KryoWrite_1cyc_X_X_212ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_212ln], (instrs EXTv16i8)>; def KryoWrite_2cyc_XY_X_136ln : SchedWriteRes<[KryoUnitXY, KryoUnitX]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_X_136ln], (instrs EXTRWrri, EXTRXrri)>; def KryoWrite_2cyc_XY_noRSV_35ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_35ln], (instregex "F(MAX|MIN)(NM)?P?(D|S)rr")>; def KryoWrite_2cyc_XY_XY_106ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_106ln], (instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2i64p|v2f64|v4f32)")>; def KryoWrite_2cyc_XY_noRSV_104ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_104ln], (instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f32|v2i32p)")>; def KryoWrite_3cyc_XY_noRSV_107ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_107ln], (instregex "F(MAX|MIN)(NM)?Vv4i32v")>; def KryoWrite_3cyc_XY_noRSV_101ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_101ln], (instregex "FABD(32|64|v2f32)")>; def KryoWrite_3cyc_XY_XY_103ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_103ln], (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>; def KryoWrite_1cyc_XY_noRSV_48ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_48ln], (instregex "F(ABS|NEG)(D|S)r")>; def KryoWrite_1cyc_XY_noRSV_124ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_124ln], (instregex "F(ABS|NEG)v2f32")>; def KryoWrite_1cyc_XY_XY_125ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_125ln], (instregex "F(ABS|NEG)(v2f64|v4f32)")>; def KryoWrite_2cyc_XY_noRSV_33ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_33ln], (instregex "(FAC(GE|GT)|FCM(EQ|GE|GT))(32|64)")>; def KryoWrite_3cyc_XY_noRSV_30ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_30ln], (instregex "(FADD|FSUB)(D|S)rr")>; def KryoWrite_3cyc_XY_noRSV_100ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_100ln], (instregex "(FADD|FSUB|FADDP)v2f32")>; def KryoWrite_3cyc_XY_noRSV_29ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_29ln], (instregex "FADDP(v2i32p|v2i64p)")>; def KryoWrite_0cyc_XY_31ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_XY_31ln], (instregex "FCCMPE?(D|S)rr")>; def KryoWrite_2cyc_XY_noRSV_34ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_34ln], (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>; def KryoWrite_2cyc_XY_XY_36ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_36ln], (instregex "FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz")>; def KryoWrite_2cyc_XY_noRSV_105ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_105ln], (instregex "FCM(EQ|LE|GE|GT|LT)v2i32rz")>; def KryoWrite_0cyc_XY_32ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_XY_32ln], (instregex "FCMPE?(D|S)r(r|i)")>; def KryoWrite_1cyc_XY_noRSV_49ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_49ln], (instrs FCSELDrrr, FCSELSrrr)>; def KryoWrite_4cyc_X_noRSV_41ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_41ln], (instrs FCVTDHr, FCVTDSr, FCVTHDr, FCVTHSr, FCVTSDr, FCVTSHr)>; def KryoWrite_4cyc_X_38ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_X_38ln], (instregex "FCVT(((A|N|M|P)(S|U)(S|U)|Z(S|U)_Int(S|U))(W|X)(D|S)ri?|Z(S|U)(d|s))$")>; def KryoWrite_4cyc_X_noRSV_113ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_113ln], (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>; def KryoWrite_4cyc_X_X_117ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_X_117ln], (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v4f32|v2f64)$")>; def KryoWrite_5cyc_X_X_XY_noRSV_119ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitXY]> { let Latency = 5; let NumMicroOps = 4; } def : InstRW<[KryoWrite_5cyc_X_X_XY_noRSV_119ln], (instregex "FCVTX?N(v2f32|v4f32|v2i32|v4i16|v4i32|v8i16)$")>; def KryoWrite_4cyc_X_X_116ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_X_116ln], (instregex "FCVTL(v2i32|v4i16|v4i32|v8i16)$")>; def KryoWrite_4cyc_X_noRSV_112ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_112ln], (instrs FCVTXNv1i64)>; def KryoWrite_4cyc_X_37ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_X_37ln], (instregex "FCVTZ(S|U)(S|U)(W|X)(D|S)ri?$")>; def KryoWrite_4cyc_X_noRSV_111ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_111ln], (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>; def KryoWrite_4cyc_X_X_115ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_X_115ln], (instregex "FCVTZ(S|U)(v2f64|v4f32|(v2i64|v4i32)(_shift)?)$")>; def KryoWrite_10cyc_XA_Y_noRSV_43ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 10; let NumMicroOps = 3; } def : InstRW<[KryoWrite_10cyc_XA_Y_noRSV_43ln], (instrs FDIVSrr)>; def KryoWrite_14cyc_XA_Y_noRSV_43ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 14; let NumMicroOps = 3; } def : InstRW<[KryoWrite_14cyc_XA_Y_noRSV_43ln], (instrs FDIVDrr)>; def KryoWrite_10cyc_XA_Y_noRSV_121ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 10; let NumMicroOps = 3; } def : InstRW<[KryoWrite_10cyc_XA_Y_noRSV_121ln], (instrs FDIVv2f32)>; def KryoWrite_14cyc_XA_Y_XA_Y_123ln : SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> { let Latency = 14; let NumMicroOps = 4; } def : InstRW<[KryoWrite_14cyc_XA_Y_XA_Y_123ln], (instrs FDIVv2f64, FDIVv4f32)>; def KryoWrite_5cyc_X_noRSV_55ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_55ln], (instregex "FN?M(ADD|SUB)Srrr")>; def KryoWrite_6cyc_X_noRSV_57ln : SchedWriteRes<[KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_noRSV_57ln], (instregex "FN?M(ADD|SUB)Drrr")>; def KryoWrite_5cyc_X_noRSV_51ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_51ln], (instrs FMLAv2f32, FMLSv2f32, FMLAv1i32_indexed, FMLSv1i32_indexed)>; def KryoWrite_5cyc_X_X_56ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_X_56ln], (instrs FMLAv4f32, FMLSv4f32)>; def KryoWrite_6cyc_X_X_61ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_X_61ln], (instrs FMLAv2f64, FMLSv2f64)>; def KryoWrite_5cyc_X_noRSV_128ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_128ln], (instrs FMLAv2i32_indexed, FMLSv2i32_indexed)>; def KryoWrite_5cyc_X_X_131ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_X_131ln], (instrs FMLAv4i32_indexed, FMLSv4i32_indexed)>; def KryoWrite_6cyc_X_X_134ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_X_134ln], (instrs FMLAv2i64_indexed, FMLSv2i64_indexed)>; def KryoWrite_6cyc_X_noRSV_60ln : SchedWriteRes<[KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_noRSV_60ln], (instrs FMLAv1i64_indexed, FMLSv1i64_indexed, FMULv1i64_indexed, FMULXv1i64_indexed)>; def KryoWrite_1cyc_XY_45ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_45ln], (instregex "FMOV(XDHigh|DXHigh|DX)r")>; def KryoWrite_1cyc_XY_noRSV_47ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_47ln], (instregex "FMOV(Di|Dr|Si|Sr|SWr|WSr|XDr|v.*_ns)")>; def KryoWrite_5cyc_X_noRSV_53ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_53ln], (instrs FMULv1i32_indexed, FMULXv1i32_indexed)>; def KryoWrite_5cyc_X_noRSV_127ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_127ln], (instrs FMULv2f32, FMULXv2f32, FMULv2i32_indexed, FMULXv2i32_indexed)>; def KryoWrite_5cyc_X_X_130ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_X_130ln], (instrs FMULv4f32, FMULXv4f32, FMULv4i32_indexed, FMULXv4i32_indexed)>; def KryoWrite_6cyc_X_X_133ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_X_133ln], (instrs FMULv2f64, FMULXv2f64, FMULv2i64_indexed, FMULXv2i64_indexed)>; def KryoWrite_5cyc_X_noRSV_54ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_54ln], (instrs FMULSrr, FNMULSrr, FMULX32)>; def KryoWrite_6cyc_X_noRSV_59ln : SchedWriteRes<[KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_noRSV_59ln], (instrs FMULDrr, FNMULDrr, FMULX64)>; def KryoWrite_3cyc_XY_noRSV_28ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_28ln], (instrs FRECPEv1i32, FRECPEv1i64, FRSQRTEv1i32, FRSQRTEv1i64 )>; def KryoWrite_3cyc_XY_noRSV_99ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_99ln], (instrs FRECPEv2f32, FRSQRTEv2f32)>; def KryoWrite_3cyc_XY_XY_102ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_102ln], (instrs FRECPEv2f64, FRECPEv4f32, FRSQRTEv2f64, FRSQRTEv4f32)>; def KryoWrite_5cyc_X_noRSV_52ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_52ln], (instrs FRECPS32, FRSQRTS32)>; def KryoWrite_6cyc_X_noRSV_58ln : SchedWriteRes<[KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_noRSV_58ln], (instrs FRECPS64, FRSQRTS64)>; def KryoWrite_5cyc_X_noRSV_126ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_noRSV_126ln], (instrs FRECPSv2f32, FRSQRTSv2f32)>; def KryoWrite_5cyc_X_X_129ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_X_129ln], (instrs FRECPSv4f32, FRSQRTSv4f32)>; def KryoWrite_6cyc_X_X_132ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 6; let NumMicroOps = 2; } def : InstRW<[KryoWrite_6cyc_X_X_132ln], (instrs FRECPSv2f64, FRSQRTSv2f64)>; def KryoWrite_3cyc_XY_noRSV_50ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_50ln], (instrs FRECPXv1i32, FRECPXv1i64)>; def KryoWrite_2cyc_XY_noRSV_39ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_39ln], (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>; def KryoWrite_2cyc_XY_noRSV_108ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_108ln], (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>; def KryoWrite_2cyc_XY_XY_109ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_109ln], (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>; def KryoWrite_12cyc_XA_Y_noRSV_42ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 12; let NumMicroOps = 3; } def : InstRW<[KryoWrite_12cyc_XA_Y_noRSV_42ln], (instrs FSQRTSr)>; def KryoWrite_21cyc_XA_Y_noRSV_42ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 21; let NumMicroOps = 3; } def : InstRW<[KryoWrite_21cyc_XA_Y_noRSV_42ln], (instrs FSQRTDr)>; def KryoWrite_12cyc_XA_Y_noRSV_120ln : SchedWriteRes<[KryoUnitXA, KryoUnitY]> { let Latency = 12; let NumMicroOps = 3; } def : InstRW<[KryoWrite_12cyc_XA_Y_noRSV_120ln], (instrs FSQRTv2f32)>; def KryoWrite_21cyc_XA_Y_XA_Y_122ln : SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> { let Latency = 21; let NumMicroOps = 4; } def : InstRW<[KryoWrite_21cyc_XA_Y_XA_Y_122ln], (instrs FSQRTv4f32)>; def KryoWrite_36cyc_XA_Y_XA_Y_122ln : SchedWriteRes<[KryoUnitXA, KryoUnitY, KryoUnitXA, KryoUnitY]> { let Latency = 36; let NumMicroOps = 4; } def : InstRW<[KryoWrite_36cyc_XA_Y_XA_Y_122ln], (instrs FSQRTv2f64)>; def KryoWrite_1cyc_X_201ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_X_201ln], (instregex "INSv.*")>; def KryoWrite_3cyc_LS_255ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_255ln], (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>; def KryoWrite_4cyc_LS_X_270ln : SchedWriteRes<[KryoUnitLS, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_LS_X_270ln], (instregex "LD1(i8|i16|i32)$")>; def KryoWrite_3cyc_LS_noRSV_285ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_285ln], (instregex "LD1One(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_289ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_XY_289ln, WriteAdr], (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>; def KryoWrite_4cyc_LS_XY_X_298ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_LS_XY_X_298ln, WriteAdr], (instregex "LD1(i8|i16|i32)_POST$")>; def KryoWrite_3cyc_LS_LS_LS_308ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_LS_LS_308ln], (instregex "LD1Three(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_XY_noRSV_317ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_317ln, WriteAdr], (instregex "LD1One(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_LS_LS_LS_328ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_328ln, WriteAdr], (instregex "LD1Four(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_XY_LS_LS_332ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_332ln, WriteAdr], (instregex "LD1Three(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_348ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 5; } def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_348ln], (instregex "LD1Three(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_LS_LS_LS_351ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 5; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_351ln], (instregex "LD1Four(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_358ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 6; } def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_358ln], (instregex "LD1Four(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_360ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 6; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_360ln, WriteAdr], (instregex "LD1Three(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_368ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 7; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_368ln, WriteAdr], (instregex "LD1Four(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_LS_281ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_281ln], (instregex "LD(1|2)Two(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_noRSV_noRSV_311ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_311ln], (instregex "LD(1|2)Two(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_LS_313ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_313ln, WriteAdr], (instregex "LD(1|2)Two(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_XY_noRSV_noRSV_334ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_334ln, WriteAdr], (instregex "LD(1|2)Two(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_256ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_256ln], (instregex "LD1R(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_noRSV_286ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_286ln], (instregex "LD1R(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_290ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_XY_290ln, WriteAdr], (instregex "LD1R(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_XY_noRSV_318ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_318ln, WriteAdr], (instregex "LD1R(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_257ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_257ln], (instregex "LD2i64$")>; def KryoWrite_3cyc_LS_XY_291ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_XY_291ln, WriteAdr], (instregex "LD2i64_POST$")>; def KryoWrite_4cyc_LS_X_X_296ln : SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_LS_X_X_296ln], (instregex "LD2(i8|i16|i32)$")>; def KryoWrite_4cyc_LS_XY_X_X_321ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 4; } def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_321ln, WriteAdr], (instregex "LD2(i8|i16|i32)_POST$")>; def KryoWrite_3cyc_LS_LS_282ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_282ln], (instregex "LD2R(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_noRSV_noRSV_312ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_312ln], (instregex "LD2R(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_LS_314ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_314ln, WriteAdr], (instregex "LD2R(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_XY_noRSV_noRSV_335ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_335ln, WriteAdr], (instregex "LD2R(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_LS_283ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_283ln], (instregex "LD3i64$")>; def KryoWrite_3cyc_LS_LS_LS_309ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_LS_LS_309ln], (instregex "LD3Threev2d$")>; def KryoWrite_3cyc_LS_XY_LS_315ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_315ln, WriteAdr], (instregex "LD3i64_POST$")>; def KryoWrite_4cyc_LS_X_X_X_320ln : SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 4; } def : InstRW<[KryoWrite_4cyc_LS_X_X_X_320ln], (instregex "LD3(i8|i16|i32)$")>; def KryoWrite_3cyc_LS_XY_LS_LS_331ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_331ln, WriteAdr], (instregex "LD3Threev2d_POST$")>; def KryoWrite_4cyc_LS_XY_X_X_X_338ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 5; } def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_X_338ln, WriteAdr], (instregex "LD3(i8|i16|i32)_POST$")>; def KryoWrite_4cyc_LS_LS_X_X_X_noRSV_noRSV_noRSV_373ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 8; } def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_noRSV_noRSV_noRSV_373ln], (instregex "LD3Three(v8b|v4h|v2s)$")>; def KryoWrite_4cyc_LS_XY_LS_X_X_X_noRSV_noRSV_noRSV_380ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 9; } def : InstRW<[KryoWrite_4cyc_LS_XY_LS_X_X_X_noRSV_noRSV_noRSV_380ln, WriteAdr], (instregex "LD3Three(v8b|v4h|v2s)_POST$")>; def KryoWrite_4cyc_LS_LS_X_X_X_LS_LS_X_X_X_381ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 10; } def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_LS_LS_X_X_X_381ln], (instregex "LD3Three(v16b|v8h|v4s)$")>; def KryoWrite_4cyc_LS_LS_X_X_X_LS_XY_LS_X_X_X_383ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 11; } def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_LS_XY_LS_X_X_X_383ln, WriteAdr], (instregex "LD3Three(v16b|v8h|v4s)_POST$")>; def KryoWrite_3cyc_LS_LS_LS_310ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_LS_LS_310ln], (instregex "LD3R(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_XY_LS_LS_333ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_333ln, WriteAdr], (instregex "LD3R(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_349ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 5; } def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_349ln], (instregex "LD3R(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_361ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 6; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_361ln, WriteAdr], (instregex "LD3R(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_LS_284ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_284ln], (instregex "LD4i64$")>; def KryoWrite_3cyc_LS_XY_LS_316ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_316ln, WriteAdr], (instregex "LD4i64_POST$")>; def KryoWrite_3cyc_LS_LS_LS_LS_329ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_329ln], (instregex "LD4Four(v2d)$")>; def KryoWrite_4cyc_LS_X_X_X_X_337ln : SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 5; } def : InstRW<[KryoWrite_4cyc_LS_X_X_X_X_337ln], (instregex "LD4(i8|i16|i32)$")>; def KryoWrite_3cyc_LS_XY_LS_LS_LS_350ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 5; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_350ln, WriteAdr], (instregex "LD4Four(v2d)_POST$")>; def KryoWrite_4cyc_LS_XY_X_X_X_X_355ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 6; } def : InstRW<[KryoWrite_4cyc_LS_XY_X_X_X_X_355ln, WriteAdr], (instregex "LD4(i8|i16|i32)_POST$")>; def KryoWrite_4cyc_LS_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_382ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 10; } def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_382ln], (instregex "LD4Four(v8b|v4h|v2s)$")>; def KryoWrite_4cyc_LS_XY_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_384ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 11; } def : InstRW<[KryoWrite_4cyc_LS_XY_LS_X_X_X_X_noRSV_noRSV_noRSV_noRSV_384ln, WriteAdr], (instregex "LD4Four(v8b|v4h|v2s)_POST$")>; def KryoWrite_4cyc_LS_LS_X_X_X_X_LS_LS_X_X_X_X_386ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 12; } def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_LS_LS_X_X_X_X_386ln], (instregex "LD4Four(v16b|v8h|v4s)$")>; def KryoWrite_4cyc_LS_LS_X_X_X_X_LS_XY_LS_X_X_X_X_389ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 13; } def : InstRW<[KryoWrite_4cyc_LS_LS_X_X_X_X_LS_XY_LS_X_X_X_X_389ln, WriteAdr], (instregex "LD4Four(v16b|v8h|v4s)_POST$")>; def KryoWrite_3cyc_LS_LS_LS_LS_330ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_LS_LS_LS_330ln], (instregex "LD4R(v16b|v8h|v4s|v2d)$")>; def KryoWrite_3cyc_LS_XY_LS_LS_LS_352ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS, KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 5; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_LS_LS_352ln, WriteAdr], (instregex "LD4R(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_359ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 6; } def : InstRW<[KryoWrite_3cyc_LS_LS_noRSV_noRSV_noRSV_noRSV_359ln], (instregex "LD4R(v8b|v4h|v2s|v1d)$")>; def KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_369ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 7; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_noRSV_noRSV_noRSV_noRSV_369ln, WriteAdr], (instregex "LD4R(v8b|v4h|v2s|v1d)_POST$")>; def KryoWrite_3cyc_LS_LS_400ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_400ln], (instregex "LDAX?R(B|H|W|X)")>; def : InstRW<[KryoWrite_3cyc_LS_LS_400ln, WriteLDHi], (instregex "LDAXP(W|X)")>; def KryoWrite_3cyc_LS_LS_401ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_401ln, WriteLDHi], (instrs LDNPQi)>; def KryoWrite_3cyc_LS_noRSV_noRSV_408ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_408ln, WriteLDHi], (instrs LDNPDi, LDNPSi)>; def KryoWrite_3cyc_LS_394ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_394ln, WriteLDHi], (instrs LDNPWi, LDNPXi)>; def KryoWrite_3cyc_LS_LS_402ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_LS_402ln, WriteLDHi], (instrs LDPQi)>; def KryoWrite_3cyc_LS_noRSV_noRSV_409ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_noRSV_409ln, WriteLDHi], (instrs LDPDi, LDPSi)>; def KryoWrite_3cyc_LS_XY_LS_410ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY, KryoUnitLS]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_LS_410ln, WriteLDHi, WriteAdr], (instregex "LDPQ(post|pre)")>; def KryoWrite_3cyc_LS_XY_noRSV_noRSV_411ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_noRSV_411ln, WriteLDHi, WriteAdr], (instregex "LDP(D|S)(post|pre)")>; def KryoWrite_3cyc_LS_393ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_393ln, WriteLDHi], (instrs LDPWi, LDPXi)>; def KryoWrite_3cyc_LS_XY_403ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_XY_403ln, WriteLDHi, WriteAdr], (instregex "LDP(W|X)(post|pre)")>; def KryoWrite_4cyc_LS_395ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_LS_395ln, WriteLDHi], (instrs LDPSWi)>; def KryoWrite_4cyc_LS_XY_405ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_LS_XY_405ln, WriteLDHi, WriteAdr], (instrs LDPSWpost, LDPSWpre)>; def KryoWrite_3cyc_LS_264ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_264ln], (instrs LDRQui, LDRQl)>; def KryoWrite_4cyc_X_LS_271ln : SchedWriteRes<[KryoUnitX, KryoUnitLS]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_LS_271ln], (instrs LDRQroW, LDRQroX)>; def KryoWrite_3cyc_LS_noRSV_287ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_287ln], (instregex "LDR((D|S)l|(D|S|H|B)ui)")>; def KryoWrite_3cyc_LS_XY_293ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_XY_293ln, WriteAdr], (instrs LDRQpost, LDRQpre)>; def KryoWrite_4cyc_X_LS_noRSV_297ln : SchedWriteRes<[KryoUnitX, KryoUnitLS]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_X_LS_noRSV_297ln], (instregex "LDR(D|S|H|B)ro(W|X)")>; def KryoWrite_3cyc_LS_XY_noRSV_319ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_XY_noRSV_319ln, WriteAdr], (instregex "LDR(D|S|H|B)(post|pre)")>; def KryoWrite_3cyc_LS_261ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_261ln], (instregex "LDR(BB|HH|W|X)ui")>; def KryoWrite_3cyc_LS_XY_292ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_XY_292ln, WriteAdr], (instregex "LDR(BB|HH|W|X)(post|pre)")>; def KryoWrite_4cyc_X_LS_272ln : SchedWriteRes<[KryoUnitX, KryoUnitLS]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_LS_272ln], (instregex "(LDR(BB|HH|W|X)ro(W|X)|PRFMro(W|X))")>; def KryoWrite_3cyc_LS_262ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_262ln], (instrs LDRWl, LDRXl)>; def KryoWrite_4cyc_LS_268ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_LS_268ln], (instregex "LDRS(BW|BX|HW|HX|W)ui")>; def KryoWrite_5cyc_X_LS_273ln : SchedWriteRes<[KryoUnitX, KryoUnitLS]> { let Latency = 5; let NumMicroOps = 2; } def : InstRW<[KryoWrite_5cyc_X_LS_273ln], (instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>; def KryoWrite_4cyc_LS_XY_294ln : SchedWriteRes<[KryoUnitLS, KryoUnitXY]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_LS_XY_294ln, WriteAdr], (instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>; def KryoWrite_4cyc_LS_269ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_LS_269ln], (instrs LDRSWl)>; def KryoWrite_3cyc_LS_260ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_260ln], (instregex "LDTR(B|H|W|X)i")>; def KryoWrite_4cyc_LS_267ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_LS_267ln], (instregex "LDTRS(BW|BX|HW|HX|W)i")>; def KryoWrite_3cyc_LS_263ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_263ln], (instrs LDURQi)>; def KryoWrite_3cyc_LS_noRSV_288ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_noRSV_288ln], (instregex "LDUR(D|S|H|B)i")>; def KryoWrite_3cyc_LS_259ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_259ln], (instregex "LDUR(BB|HH|W|X)i")>; def KryoWrite_4cyc_LS_266ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_LS_266ln], (instregex "LDURS(B|H)?(W|X)i")>; def KryoWrite_3cyc_LS_258ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_258ln, WriteLDHi], (instregex "LDXP(W|X)")>; def KryoWrite_3cyc_LS_258_1ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 3; let NumMicroOps = 1; } def : InstRW<[KryoWrite_3cyc_LS_258_1ln], (instregex "LDXR(B|H|W|X)")>; def KryoWrite_2cyc_XY_XY_137ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_137ln], (instrs LSLVWr, LSLVXr)>; def KryoWrite_1cyc_XY_135ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_135ln], (instregex "(LS|AS|RO)RV(W|X)r")>; def KryoWrite_4cyc_X_84ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 1; } def : InstRW<[KryoWrite_4cyc_X_84ln], (instrs MADDWrrr, MSUBWrrr)>; def KryoWrite_5cyc_X_85ln : SchedWriteRes<[KryoUnitX]> { let Latency = 5; let NumMicroOps = 1; } def : InstRW<[KryoWrite_5cyc_X_85ln], (instrs MADDXrrr, MSUBXrrr)>; def KryoWrite_4cyc_X_noRSV_188ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_188ln], (instregex "(MLA|MLS|MUL)(v8i8|v4i16|v2i32)(_indexed)?")>; def KryoWrite_4cyc_X_X_192ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_X_192ln], (instregex "(MLA|MLS|MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?")>; def KryoWrite_1cyc_XY_noRSV_198ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_198ln], (instregex "(MOVI|MVNI)(D|v8b_ns|v2i32|v4i16|v2s_msl)")>; def KryoWrite_1cyc_XY_XY_199ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_199ln], (instregex "(MOVI|MVNI)(v2d_ns|v16b_ns|v4i32|v8i16|v4s_msl)")>; def KryoWrite_1cyc_X_89ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_X_89ln], (instrs MOVKWi, MOVKXi)>; def KryoWrite_1cyc_XY_91ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_91ln], (instrs MOVNWi, MOVNXi)>; def KryoWrite_1cyc_XY_90ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_90ln], (instrs MOVZWi, MOVZXi)>; def KryoWrite_2cyc_XY_93ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 1; } def : InstRW<[KryoWrite_2cyc_XY_93ln], (instrs MRS)>; def KryoWrite_0cyc_X_87ln : SchedWriteRes<[KryoUnitX]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_X_87ln], (instrs MSRpstateImm4)>; def : InstRW<[KryoWrite_0cyc_X_87ln], (instrs MSRpstateImm1)>; def KryoWrite_0cyc_XY_88ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_XY_88ln], (instrs MSR)>; def KryoWrite_1cyc_XY_noRSV_143ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_143ln], (instregex "NEG(v8i8|v4i16|v2i32|v1i64)")>; def KryoWrite_1cyc_XY_XY_145ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_145ln], (instregex "NEG(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_1cyc_XY_noRSV_193ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_193ln], (instrs NOTv8i8)>; def KryoWrite_1cyc_XY_XY_194ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_194ln], (instrs NOTv16i8)>; def KryoWrite_2cyc_XY_noRSV_234ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_234ln], (instrs PMULv8i8)>; def KryoWrite_2cyc_XY_XY_236ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_236ln], (instrs PMULv16i8)>; def KryoWrite_2cyc_XY_XY_235ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_235ln], (instrs PMULLv8i8, PMULLv16i8)>; def KryoWrite_3cyc_XY_XY_237ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_237ln], (instrs PMULLv1i64, PMULLv2i64)>; def KryoWrite_0cyc_LS_254ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_LS_254ln], (instrs PRFMl, PRFMui)>; def KryoWrite_0cyc_LS_253ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_LS_253ln], (instrs PRFUMi)>; def KryoWrite_6cyc_XY_X_noRSV_175ln : SchedWriteRes<[KryoUnitXY, KryoUnitX]> { let Latency = 6; let NumMicroOps = 3; } def : InstRW<[KryoWrite_6cyc_XY_X_noRSV_175ln], (instregex "R(ADD|SUB)HNv.*")>; def KryoWrite_2cyc_XY_204ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 1; } def : InstRW<[KryoWrite_2cyc_XY_204ln], (instrs RBITWr, RBITXr)>; def KryoWrite_2cyc_XY_noRSV_218ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_noRSV_218ln], (instrs RBITv8i8)>; def KryoWrite_2cyc_XY_XY_219ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_219ln], (instrs RBITv16i8)>; def KryoWrite_1cyc_X_202ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_X_202ln], (instregex "REV(16|32)?(W|X)r")>; def KryoWrite_1cyc_XY_noRSV_214ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_214ln], (instregex "REV(16|32|64)(v8i8|v4i16|v2i32)")>; def KryoWrite_1cyc_XY_XY_216ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_216ln], (instregex "REV(16|32|64)(v16i8|v8i16|v4i32)")>; def KryoWrite_3cyc_X_noRSV_244ln : SchedWriteRes<[KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_X_noRSV_244ln], (instregex "S(L|R)I(d|(v8i8|v4i16|v2i32)_shift)")>; def KryoWrite_3cyc_X_X_245ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_X_X_245ln], (instregex "S(L|R)I(v16i8|v8i16|v4i32|v2i64)_shift")>; def KryoWrite_1cyc_XY_2ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_2ln, ReadI, ReadI], (instregex "SBCS?(W|X)r")>; def KryoWrite_2cyc_XA_XA_XA_24ln : SchedWriteRes<[KryoUnitXA, KryoUnitXA, KryoUnitXA]> { let Latency = 2; let NumMicroOps = 3; } def : InstRW<[KryoWrite_2cyc_XA_XA_XA_24ln], (instrs SHA1Crrr, SHA1Mrrr, SHA1Prrr)>; def KryoWrite_1cyc_XY_noRSV_21ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_21ln], (instrs SHA1Hrr)>; def KryoWrite_2cyc_X_X_23ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_X_X_23ln], (instrs SHA1SU0rrr, SHA1SU1rr, SHA256SU0rr)>; def KryoWrite_4cyc_XA_XA_XA_25ln : SchedWriteRes<[KryoUnitXA, KryoUnitXA, KryoUnitXA]> { let Latency = 4; let NumMicroOps = 3; } def : InstRW<[KryoWrite_4cyc_XA_XA_XA_25ln], (instrs SHA256Hrrr, SHA256H2rrr)>; def KryoWrite_3cyc_XY_XY_X_X_26ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY, KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 4; } def : InstRW<[KryoWrite_3cyc_XY_XY_X_X_26ln], (instrs SHA256SU1rrr)>; def KryoWrite_4cyc_X_noRSV_189ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_189ln], (instregex "SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?")>; def KryoWrite_3cyc_XY_noRSV_68ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_68ln], (instregex "SQ(ABS|NEG)(v1i8|v1i16|v1i32|v1i64)")>; def KryoWrite_3cyc_XY_noRSV_157ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_157ln], (instregex "SQ(ABS|NEG)(v8i8|v4i16|v2i32)")>; def KryoWrite_3cyc_XY_XY_164ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_164ln], (instregex "SQ(ABS|NEG)(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_4cyc_X_noRSV_190ln : SchedWriteRes<[KryoUnitX]> { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[KryoWrite_4cyc_X_noRSV_190ln], (instregex "SQD(MLAL|MLSL|MULL)(i16|i32)")>; def KryoWrite_0cyc_LS_Y_274ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_274ln], (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>; def KryoWrite_1cyc_LS_Y_X_301ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_301ln], (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$")>; def KryoWrite_1cyc_LS_Y_XY_305ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_305ln], (instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>; def KryoWrite_0cyc_LS_Y_LS_Y_323ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 4; } def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_323ln], (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>; def KryoWrite_1cyc_LS_Y_XY_LS_Y_345ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 5; } def : InstRW<[KryoWrite_1cyc_LS_Y_XY_LS_Y_345ln], (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>; def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_356ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 6; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_356ln], (instregex "ST1Three(v16b|v8h|v4s|v2d)$")>; def KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_366ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 7; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_366ln], (instregex "ST1Three(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_371ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 8; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_371ln], (instregex "ST1Four(v16b|v8h|v4s|v2d)$")>; def KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_377ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 9; } def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_377ln], (instregex "ST1Four(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_0cyc_LS_Y_275ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_275ln], (instregex "ST2(Two(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64))$")>; def KryoWrite_1cyc_LS_Y_XY_306ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_306ln], (instregex "ST2(Two(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64))_POST$")>; def KryoWrite_0cyc_LS_Y_LS_Y_322ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 4; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_322ln], (instregex "ST2Two(v16b|v8h|v4s|v2d)$")>; def KryoWrite_1cyc_LS_Y_XY_LS_Y_344ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 5; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_344ln], (instregex "ST2Two(v16b|v8h|v4s|v2d)_POST$")>; def KryoWrite_0cyc_LS_Y_LS_Y_324ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 4; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_324ln], (instregex "ST3(Threev1d|(i8|i16|i32|i64))$")>; def KryoWrite_1cyc_LS_Y_XY_LS_Y_346ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 5; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_346ln], (instregex "ST3(Threev1d|(i8|i16|i32|i64))_POST$")>; def KryoWrite_1cyc_X_X_LS_Y_LS_Y_353ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 6; } def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_LS_Y_353ln], (instregex "ST3Three(v8b|v4h|v2s)$")>; def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_357ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 6; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_357ln], (instregex "ST3Threev2d$")>; def KryoWrite_1cyc_X_X_LS_Y_XY_LS_Y_363ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 7; } def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_XY_LS_Y_363ln], (instregex "ST3Three(v8b|v4h|v2s)_POST$")>; def KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_367ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 7; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_LS_Y_367ln], (instregex "ST3Threev2d_POST$")>; def KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_LS_Y_385ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 12; } def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_LS_Y_385ln], (instregex "ST3Three(v16b|v8h|v4s)$")>; def KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_XY_LS_Y_388ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 13; } def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_LS_Y_X_X_LS_Y_XY_LS_Y_388ln], (instregex "ST3Three(v16b|v8h|v4s)_POST$")>; def KryoWrite_0cyc_LS_Y_LS_Y_325ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 4; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_325ln], (instregex "ST4(Fourv1d|(i8|i16|i32|i64))$")>; def KryoWrite_1cyc_LS_Y_XY_LS_Y_347ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 5; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_XY_LS_Y_347ln], (instregex "ST4(Fourv1d|(i8|i16|i32|i64))_POST$")>; def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_370ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 8; } def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_370ln], (instregex "ST4Four(v8b|v4h|v2s)$")>; def KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_372ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 8; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_LS_Y_LS_Y_372ln], (instregex "ST4Fourv2d$")>; def KryoWrite_1cyc_X_X_LS_Y_XY_X_X_LS_Y_375ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 9; } def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_XY_X_X_LS_Y_375ln], (instregex "ST4Four(v8b|v4h|v2s)_POST$")>; def KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_379ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 9; } def : InstRW<[WriteAdr, KryoWrite_0cyc_LS_Y_LS_Y_XY_LS_Y_LS_Y_379ln], (instregex "ST4Fourv2d_POST$")>; def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_390ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 16; } def : InstRW<[KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_390ln], (instregex "ST4Four(v16b|v8h|v4s)$")>; def KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_XY_X_X_LS_Y_392ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 17; } def : InstRW<[WriteAdr, KryoWrite_1cyc_X_X_LS_Y_X_X_LS_Y_X_X_LS_Y_XY_X_X_LS_Y_392ln], (instregex "ST4Four(v16b|v8h|v4s)_POST$")>; def KryoWrite_0cyc_LS_LS_Y_299ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 3; } def : InstRW<[KryoWrite_0cyc_LS_LS_Y_299ln], (instregex "STLR(B|H|W|X)")>; def KryoWrite_3cyc_LS_LS_Y_307ln : SchedWriteRes<[KryoUnitLS, KryoUnitLS, KryoUnitY]> { let Latency = 3; let NumMicroOps = 3; } def : InstRW<[KryoWrite_3cyc_LS_LS_Y_307ln], (instregex "STLX(P(W|X)|R(B|H|W|X))")>; def KryoWrite_0cyc_LS_Y_276ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_276ln], (instrs STNPDi, STNPSi)>; def KryoWrite_0cyc_LS_Y_LS_Y_326ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 4; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_326ln], (instrs STNPQi)>; def KryoWrite_0cyc_LS_Y_280ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_280ln], (instrs STNPWi, STNPXi)>; def KryoWrite_0cyc_LS_Y_277ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_277ln], (instregex "STP(D|S)i")>; def KryoWrite_1cyc_LS_Y_X_303ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_303ln], (instregex "STP(D|S)(post|pre)")>; def KryoWrite_0cyc_LS_Y_LS_Y_327ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 4; } def : InstRW<[KryoWrite_0cyc_LS_Y_LS_Y_327ln], (instrs STPQi)>; def KryoWrite_1cyc_LS_Y_X_LS_Y_343ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 5; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_LS_Y_343ln], (instrs STPQpost, STPQpre)>; def KryoWrite_0cyc_LS_Y_279ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_279ln], (instregex "STP(W|X)i")>; def KryoWrite_1cyc_LS_X_Y_300ln : SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitY]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_X_Y_300ln], (instregex "STP(W|X)(post|pre)")>; def KryoWrite_0cyc_LS_Y_278ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_278ln], (instregex "STR(Q|D|S|H|B)ui")>; def KryoWrite_1cyc_X_LS_Y_295ln : SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[KryoWrite_1cyc_X_LS_Y_295ln], (instregex "STR(D|S|H|B)ro(W|X)")>; def KryoWrite_1cyc_LS_Y_X_304ln : SchedWriteRes<[KryoUnitLS, KryoUnitY, KryoUnitX]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_Y_X_304ln], (instregex "STR(Q|D|S|H|B)(post|pre)")>; def KryoWrite_2cyc_X_LS_Y_XY_LS_Y_354ln : SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY, KryoUnitXY, KryoUnitLS, KryoUnitY]> { let Latency = 2; let NumMicroOps = 6; } def : InstRW<[KryoWrite_2cyc_X_LS_Y_XY_LS_Y_354ln], (instregex "STRQro(W|X)")>; def KryoWrite_0cyc_LS_Y_399ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_399ln], (instregex "STR(BB|HH|W|X)ui")>; def KryoWrite_1cyc_X_LS_Y_406ln : SchedWriteRes<[KryoUnitX, KryoUnitLS, KryoUnitY]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[KryoWrite_1cyc_X_LS_Y_406ln], (instregex "STR(BB|HH|W|X)ro(W|X)")>; def KryoWrite_1cyc_LS_X_Y_407ln : SchedWriteRes<[KryoUnitLS, KryoUnitX, KryoUnitY]> { let Latency = 1; let NumMicroOps = 3; } def : InstRW<[WriteAdr, KryoWrite_1cyc_LS_X_Y_407ln], (instregex "STR(BB|HH|W|X)(post|pre)")>; def KryoWrite_0cyc_LS_Y_398ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_398ln], (instregex "STTR(B|H|W|X)i")>; def KryoWrite_0cyc_LS_Y_396ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_396ln], (instregex "STUR(Q|D|S|H|B)i")>; def KryoWrite_0cyc_LS_Y_397ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 0; let NumMicroOps = 2; } def : InstRW<[KryoWrite_0cyc_LS_Y_397ln], (instregex "STUR(BB|HH|W|X)i")>; def KryoWrite_3cyc_LS_Y_404ln : SchedWriteRes<[KryoUnitLS, KryoUnitY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_LS_Y_404ln], (instregex "STX(P(W|X)|R(B|H|W|X))")>; def KryoWrite_3cyc_XY_noRSV_160ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_160ln], (instregex "^(SU|US)QADD(v8i8|v4i16|v2i32)")>; def KryoWrite_3cyc_XY_XY_167ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_167ln], (instregex "^(SU|US)QADD(v16i8|v8i16|v4i32|v2i64)")>; def KryoWrite_1cyc_XY_1ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 1; } def : InstRW<[KryoWrite_1cyc_XY_1ln, ReadI], (instregex "SUBS?(W|X)ri")>; def KryoWrite_2cyc_XY_XY_5ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_5ln, ReadI, ReadIEReg], (instregex "SUBS?(W|X)rx")>; def KryoWrite_2cyc_XY_XY_5_1ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 2; let NumMicroOps = 2; } def : InstRW<[KryoWrite_2cyc_XY_XY_5_1ln, ReadI, ReadISReg], (instregex "SUBS?(W|X)rs")>; def KryoWrite_1cyc_XY_noRSV_6ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_6ln, ReadI, ReadI], (instregex "SUBS?(W|X)rr")>; def KryoWrite_0cyc_LS_9ln : SchedWriteRes<[KryoUnitLS]> { let Latency = 0; let NumMicroOps = 1; } def : InstRW<[KryoWrite_0cyc_LS_9ln], (instregex "SYSL?xt")>; def KryoWrite_1cyc_X_noRSV_205ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_noRSV_205ln], (instrs TBLv8i8One)>; def KryoWrite_1cyc_X_X_208ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_208ln], (instrs TBLv16i8One)>; def KryoWrite_2cyc_X_X_X_noRSV_222ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 2; let NumMicroOps = 4; } def : InstRW<[KryoWrite_2cyc_X_X_X_noRSV_222ln], (instrs TBLv8i8Two)>; def KryoWrite_2cyc_X_X_X_X_X_X_224ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 2; let NumMicroOps = 6; } def : InstRW<[KryoWrite_2cyc_X_X_X_X_X_X_224ln], (instrs TBLv16i8Two)>; def KryoWrite_3cyc_X_X_X_X_X_noRSV_225ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 6; } def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_noRSV_225ln], (instrs TBLv8i8Three)>; def KryoWrite_3cyc_X_X_X_X_X_X_X_noRSV_228ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 8; } def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_X_X_noRSV_228ln], (instrs TBLv8i8Four)>; def KryoWrite_4cyc_X_X_X_X_X_X_X_X_XY_X_X_230ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 11; } def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_XY_X_X_230ln], (instrs TBLv16i8Three)>; def KryoWrite_4cyc_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_232ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 15; } def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_232ln], (instrs TBLv16i8Four)>; def KryoWrite_2cyc_X_X_noRSV_220ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 2; let NumMicroOps = 3; } def : InstRW<[KryoWrite_2cyc_X_X_noRSV_220ln], (instrs TBXv8i8One)>; def KryoWrite_2cyc_X_X_X_X_221ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 2; let NumMicroOps = 4; } def : InstRW<[KryoWrite_2cyc_X_X_X_X_221ln], (instrs TBXv16i8One)>; def KryoWrite_3cyc_X_X_X_X_noRSV_223ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 5; } def : InstRW<[KryoWrite_3cyc_X_X_X_X_noRSV_223ln], (instrs TBXv8i8Two)>; def KryoWrite_4cyc_X_X_X_X_X_X_noRSV_226ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 7; } def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_noRSV_226ln], (instrs TBXv8i8Three)>; def KryoWrite_3cyc_X_X_X_X_X_X_X_X_227ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 3; let NumMicroOps = 8; } def : InstRW<[KryoWrite_3cyc_X_X_X_X_X_X_X_X_227ln], (instrs TBXv16i8Two)>; def KryoWrite_4cyc_X_X_X_X_X_X_X_X_noRSV_229ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 4; let NumMicroOps = 9; } def : InstRW<[KryoWrite_4cyc_X_X_X_X_X_X_X_X_noRSV_229ln], (instrs TBXv8i8Four)>; def KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_XY_X_X_X_231ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 5; let NumMicroOps = 13; } def : InstRW<[KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_XY_X_X_X_231ln], (instrs TBXv16i8Three)>; def KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_X_233ln : SchedWriteRes<[KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitXY, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX, KryoUnitX]> { let Latency = 5; let NumMicroOps = 17; } def : InstRW<[KryoWrite_5cyc_X_X_X_X_X_X_X_X_X_X_X_XY_X_X_X_X_X_233ln], (instrs TBXv16i8Four)>; def KryoWrite_1cyc_XY_XY_217ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_XY_217ln], (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>; def KryoWrite_1cyc_X_X_211ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_211ln], (instregex "(TRN1|TRN2)(v4i32|v8i16|v16i8)")>; def KryoWrite_1cyc_X_XY_213ln : SchedWriteRes<[KryoUnitX, KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_XY_213ln], (instregex "(TRN1|TRN2)(v2i32|v4i16|v8i8)")>; def KryoWrite_3cyc_XY_noRSV_156ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_noRSV_156ln], (instrs URECPEv2i32, URSQRTEv2i32)>; def KryoWrite_3cyc_XY_XY_168ln : SchedWriteRes<[KryoUnitXY, KryoUnitXY]> { let Latency = 3; let NumMicroOps = 2; } def : InstRW<[KryoWrite_3cyc_XY_XY_168ln], (instrs URECPEv4i32, URSQRTEv4i32)>; def KryoWrite_1cyc_X_X_210ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_210ln], (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>; def KryoWrite_1cyc_X_noRSV_206ln : SchedWriteRes<[KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_noRSV_206ln], (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>; def KryoWrite_1cyc_XY_noRSV_215ln : SchedWriteRes<[KryoUnitXY]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_XY_noRSV_215ln], (instregex "XTNv.*")>; def KryoWrite_1cyc_X_X_209ln : SchedWriteRes<[KryoUnitX, KryoUnitX]> { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[KryoWrite_1cyc_X_X_209ln], (instregex "ZIP1(v4i32|v8i16|v16i8)")>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedThunderX.td000064400000000000000000000356010072674642500264210ustar 00000000000000//==- AArch64SchedThunderX.td - Cavium ThunderX T8X Scheduling Definitions -*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the itinerary class data for the ARM ThunderX T8X // (T88, T81, T83) processors. // Loosely based on Cortex-A53 which is somewhat similar. // //===----------------------------------------------------------------------===// // ===---------------------------------------------------------------------===// // The following definitions describe the simpler per-operand machine model. // This works with MachineScheduler. See llvm/MC/MCSchedule.h for details. // Cavium ThunderX T8X scheduling machine model. def ThunderXT8XModel : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops dispatched per cycle. let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order. let LoadLatency = 3; // Optimistic load latency. let MispredictPenalty = 8; // Branch mispredict penalty. let PostRAScheduler = 1; // Use PostRA scheduler. let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } // Modeling each pipeline with BufferSize == 0 since T8X is in-order. def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt //===----------------------------------------------------------------------===// // Subtarget-specific SchedWrite types mapping the ProcResources and // latencies. let SchedModel = ThunderXT8XModel in { // ALU def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 2; } def : WriteRes { let Latency = 2; } // MAC def : WriteRes { let Latency = 4; let ResourceCycles = [1]; } def : WriteRes { let Latency = 4; let ResourceCycles = [1]; } // Div def : WriteRes { let Latency = 12; let ResourceCycles = [6]; } def : WriteRes { let Latency = 14; let ResourceCycles = [8]; } // Load def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 3; } def : WriteRes { let Latency = 3; } // Vector Load def : WriteRes { let Latency = 8; let ResourceCycles = [3]; } def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 6; let ResourceCycles = [1]; } def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 11; let ResourceCycles = [7]; } def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 12; let ResourceCycles = [8]; } def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 13; let ResourceCycles = [9]; } def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 13; let ResourceCycles = [9]; } // Pre/Post Indexing def : WriteRes { let Latency = 0; } // Store def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } // Vector Store def : WriteRes; def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>; def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 10; let ResourceCycles = [9]; } def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> { let Latency = 11; let ResourceCycles = [10]; } def : WriteRes { let Unsupported = 1; } // Branch def : WriteRes; def THXT8XWriteBR : SchedWriteRes<[THXT8XUnitBr]>; def : WriteRes; def THXT8XWriteBRR : SchedWriteRes<[THXT8XUnitBr]>; def THXT8XWriteRET : SchedWriteRes<[THXT8XUnitALU]>; def : WriteRes; def : WriteRes; def : WriteRes; // FP ALU def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 6; } // FP Mul, Div, Sqrt def : WriteRes { let Latency = 6; } def : WriteRes { let Latency = 22; let ResourceCycles = [19]; } def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; } def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 12; let ResourceCycles = [9]; } def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 22; let ResourceCycles = [19]; } def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 17; let ResourceCycles = [14]; } def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 31; let ResourceCycles = [28]; } //===----------------------------------------------------------------------===// // Subtarget-specific SchedRead types. // No forwarding for these reads. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; // FIXME: This needs more targeted benchmarking. // ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable // operands are needed one cycle later if and only if they are to be // shifted. Otherwise, they too are needed two cycles later. This same // ReadAdvance applies to Extended registers as well, even though there is // a separate SchedPredicate for them. def : ReadAdvance; def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI, WriteISReg, WriteIEReg, WriteIS, WriteID32, WriteID64, WriteIM32, WriteIM64]>; def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI, WriteISReg, WriteIEReg, WriteIS, WriteID32, WriteID64, WriteIM32, WriteIM64]>; def THXT8XReadISReg : SchedReadVariant<[ SchedVar, SchedVar]>; def : SchedAlias; def THXT8XReadIEReg : SchedReadVariant<[ SchedVar, SchedVar]>; def : SchedAlias; // MAC - Operands are generally needed one cycle later in the MAC pipe. // Accumulator operands are needed two cycles later. def : ReadAdvance; def : ReadAdvance; // Div def : ReadAdvance; //===----------------------------------------------------------------------===// // Subtarget-specific InstRW. //--- // Branch //--- def : InstRW<[THXT8XWriteBR], (instregex "^B$")>; def : InstRW<[THXT8XWriteBR], (instregex "^BL$")>; def : InstRW<[THXT8XWriteBR], (instregex "^B..$")>; def : InstRW<[THXT8XWriteBR], (instregex "^CBNZ")>; def : InstRW<[THXT8XWriteBR], (instregex "^CBZ")>; def : InstRW<[THXT8XWriteBR], (instregex "^TBNZ")>; def : InstRW<[THXT8XWriteBR], (instregex "^TBZ")>; def : InstRW<[THXT8XWriteBRR], (instregex "^BR$")>; def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>; //--- // Ret //--- def : InstRW<[THXT8XWriteRET], (instregex "^RET$")>; //--- // Miscellaneous //--- def : InstRW<[WriteI], (instrs COPY)>; //--- // Vector Loads //--- def : InstRW<[THXT8XWriteVLD1], (instregex "LD1i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD1], (instregex "LD2i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>; def : InstRW<[THXT8XWriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>; def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>; def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>; def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>; def : InstRW<[THXT8XWriteVLD2], (instregex "LD3i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[THXT8XWriteVLD3], (instregex "LD3Threev(2d)$")>; def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; def : InstRW<[THXT8XWriteVLD2], (instregex "LD4i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[THXT8XWriteVLD4], (instregex "LD4Fourv(2d)$")>; def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; //--- // Vector Stores //--- def : InstRW<[THXT8XWriteVST1], (instregex "ST1i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVST1], (instregex "ST2i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>; def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST3i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST3Threev(2d)$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST4i(8|16|32|64)$")>; def : InstRW<[THXT8XWriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; def : InstRW<[THXT8XWriteVST2], (instregex "ST4Fourv(2d)$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; //--- // Floating Point MAC, DIV, SQRT //--- def : InstRW<[THXT8XWriteFMAC], (instregex "^FN?M(ADD|SUB).*")>; def : InstRW<[THXT8XWriteFMAC], (instregex "^FML(A|S).*")>; def : InstRW<[THXT8XWriteFDivSP], (instrs FDIVSrr)>; def : InstRW<[THXT8XWriteFDivDP], (instrs FDIVDrr)>; def : InstRW<[THXT8XWriteFDivSP], (instregex "^FDIVv.*32$")>; def : InstRW<[THXT8XWriteFDivDP], (instregex "^FDIVv.*64$")>; def : InstRW<[THXT8XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>; def : InstRW<[THXT8XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SchedThunderX2T99.td000064400000000000000000002124260072674642500270130ustar 00000000000000//=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 ---*- tablegen -*-=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the scheduling model for Cavium ThunderX2T99 // processors. // Based on Broadcom Vulcan. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // 2. Pipeline Description. def ThunderX2T99Model : SchedMachineModel { let IssueWidth = 4; // 4 micro-ops dispatched at a time. let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer. let LoadLatency = 4; // Optimistic load latency. let MispredictPenalty = 12; // Extra cycles for mispredicted branch. // Determined via a mix of micro-arch details and experimentation. let LoopMicroOpBufferSize = 128; let PostRAScheduler = 1; // Using PostRA sched. let CompleteModel = 1; list UnsupportedFeatures = [HasSVE]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; } let SchedModel = ThunderX2T99Model in { // Define the issue ports. // Port 0: ALU, FP/SIMD. def THX2T99P0 : ProcResource<1>; // Port 1: ALU, FP/SIMD, integer mul/div. def THX2T99P1 : ProcResource<1>; // Port 2: ALU, Branch. def THX2T99P2 : ProcResource<1>; // Port 3: Store data. def THX2T99P3 : ProcResource<1>; // Port 4: Load/store. def THX2T99P4 : ProcResource<1>; // Port 5: Load/store. def THX2T99P5 : ProcResource<1>; // Define groups for the functional units on each issue port. Each group // created will be used by a WriteRes later on. // // NOTE: Some groups only contain one member. This is a way to create names for // the various functional units that share a single issue port. For example, // "THX2T99I1" for ALU ops on port 1 and "THX2T99F1" for FP ops on port 1. // Integer divide and multiply micro-ops only on port 1. def THX2T99I1 : ProcResGroup<[THX2T99P1]>; // Branch micro-ops only on port 2. def THX2T99I2 : ProcResGroup<[THX2T99P2]>; // ALU micro-ops on ports 0, 1, and 2. def THX2T99I012 : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2]>; // Crypto FP/SIMD micro-ops only on port 1. def THX2T99F1 : ProcResGroup<[THX2T99P1]>; // FP/SIMD micro-ops on ports 0 and 1. def THX2T99F01 : ProcResGroup<[THX2T99P0, THX2T99P1]>; // Store data micro-ops only on port 3. def THX2T99SD : ProcResGroup<[THX2T99P3]>; // Load/store micro-ops on ports 4 and 5. def THX2T99LS01 : ProcResGroup<[THX2T99P4, THX2T99P5]>; // 60 entry unified scheduler. def THX2T99Any : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2, THX2T99P3, THX2T99P4, THX2T99P5]> { let BufferSize = 60; } // Define commonly used write types for InstRW specializations. // All definitions follow the format: THX2T99Write_Cyc_. // 3 cycles on I1. def THX2T99Write_3Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 3; let NumMicroOps = 2; } // 1 cycles on I2. def THX2T99Write_1Cyc_I2 : SchedWriteRes<[THX2T99I2]> { let Latency = 1; let NumMicroOps = 2; } // 4 cycles on I1. def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 4; let NumMicroOps = 2; } // 23 cycles on I1. def THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 23; let ResourceCycles = [13, 23]; let NumMicroOps = 4; } // 39 cycles on I1. def THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 39; let ResourceCycles = [13, 39]; let NumMicroOps = 4; } // 1 cycle on I0, I1, or I2. def THX2T99Write_1Cyc_I012 : SchedWriteRes<[THX2T99I012]> { let Latency = 1; let NumMicroOps = 2; } // 2 cycles on I0, I1, or I2. def THX2T99Write_2Cyc_I012 : SchedWriteRes<[THX2T99I012]> { let Latency = 2; let NumMicroOps = 2; } // 4 cycles on I0, I1, or I2. def THX2T99Write_4Cyc_I012 : SchedWriteRes<[THX2T99I012]> { let Latency = 2; let NumMicroOps = 3; } // 5 cycles on I0, I1, or I2. def THX2T99Write_5Cyc_I012 : SchedWriteRes<[THX2T99I012]> { let Latency = 2; let NumMicroOps = 3; } // 5 cycles on F1. def THX2T99Write_5Cyc_F1 : SchedWriteRes<[THX2T99F1]> { let Latency = 5; let NumMicroOps = 2; } // 7 cycles on F1. def THX2T99Write_7Cyc_F1 : SchedWriteRes<[THX2T99F1]> { let Latency = 7; let NumMicroOps = 2; } // 4 cycles on F0 or F1. def THX2T99Write_4Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 4; let NumMicroOps = 2; } // 5 cycles on F0 or F1. def THX2T99Write_5Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 5; let NumMicroOps = 2; } // 6 cycles on F0 or F1. def THX2T99Write_6Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 6; let NumMicroOps = 3; } // 7 cycles on F0 or F1. def THX2T99Write_7Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 7; let NumMicroOps = 3; } // 8 cycles on F0 or F1. def THX2T99Write_8Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 8; let NumMicroOps = 3; } // 10 cycles on F0 or F1. def THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 10; let NumMicroOps = 3; } // 16 cycles on F0 or F1. def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 16; let NumMicroOps = 3; let ResourceCycles = [8]; } // 23 cycles on F0 or F1. def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 23; let NumMicroOps = 3; let ResourceCycles = [11]; } // 1 cycles on LS0 or LS1. def THX2T99Write_1Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 0; } // 1 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_1Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 0; let NumMicroOps = 2; } // 1 cycles on LS0 or LS1 and 2 of I0, I1, or I2. def THX2T99Write_1Cyc_LS01_I012_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { let Latency = 0; let NumMicroOps = 3; } // 2 cycles on LS0 or LS1. def THX2T99Write_2Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 1; let NumMicroOps = 2; } // 4 cycles on LS0 or LS1. def THX2T99Write_4Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 4; let NumMicroOps = 4; } // 5 cycles on LS0 or LS1. def THX2T99Write_5Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 5; let NumMicroOps = 3; } // 6 cycles on LS0 or LS1. def THX2T99Write_6Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 6; let NumMicroOps = 3; } // 4 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_4Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 4; let NumMicroOps = 3; } // 4 cycles on LS0 or LS1 and 2 of I0, I1, or I2. def THX2T99Write_4Cyc_LS01_I012_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { let Latency = 4; let NumMicroOps = 3; } // 5 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_5Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 5; let NumMicroOps = 3; } // 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2. def THX2T99Write_5Cyc_LS01_I012_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { let Latency = 5; let NumMicroOps = 3; } // 6 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_6Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 6; let NumMicroOps = 4; } // 6 cycles on LS0 or LS1 and 2 of I0, I1, or I2. def THX2T99Write_6Cyc_LS01_I012_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> { let Latency = 6; let NumMicroOps = 3; } // 1 cycles on LS0 or LS1 and F0 or F1. def THX2T99Write_1Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { let Latency = 1; let NumMicroOps = 2; } // 5 cycles on LS0 or LS1 and F0 or F1. def THX2T99Write_5Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { let Latency = 5; let NumMicroOps = 3; } // 6 cycles on LS0 or LS1 and F0 or F1. def THX2T99Write_6Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { let Latency = 6; let NumMicroOps = 3; } // 7 cycles on LS0 or LS1 and F0 or F1. def THX2T99Write_7Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { let Latency = 7; let NumMicroOps = 3; } // 8 cycles on LS0 or LS1 and F0 or F1. def THX2T99Write_8Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> { let Latency = 8; let NumMicroOps = 3; } // 8 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_8Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 8; let NumMicroOps = 4; } // 12 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_12Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 12; let NumMicroOps = 6; } // 16 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_16Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 16; let NumMicroOps = 8; } // 24 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_24Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 24; let NumMicroOps = 12; } // 32 cycles on LS0 or LS1 and I0, I1, or I2. def THX2T99Write_32Cyc_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> { let Latency = 32; let NumMicroOps = 16; } // Define commonly used read types. // No forwarding is provided for these types. def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; //===----------------------------------------------------------------------===// // 3. Instruction Tables. //--- // 3.1 Branch Instructions //--- // Branch, immed // Branch and link, immed // Compare and branch def : WriteRes { let Latency = 1; let NumMicroOps = 2; } // Branch, register // Branch and link, register != LR // Branch and link, register = LR def : WriteRes { let Latency = 1; let NumMicroOps = 2; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 1; } def : WriteRes { let Latency = 4; let NumMicroOps = 2; } //--- // Branch //--- def : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>; def : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>; def : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^B..$")>; def : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>; //--- // 3.2 Arithmetic and Logical Instructions // 3.3 Move and Shift Instructions //--- // ALU, basic // Conditional compare // Conditional select // Address generation def : WriteRes { let Latency = 1; let ResourceCycles = [1]; let NumMicroOps = 2; } def : InstRW<[WriteI], (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", "ADC(W|X)r", "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", "SBCS(W|X)r", "CCMN(W|X)(i|r)", "CCMP(W|X)(i|r)", "CSEL(W|X)r", "CSINC(W|X)r", "CSINV(W|X)r", "CSNEG(W|X)r")>; def : InstRW<[WriteI], (instrs COPY)>; // ALU, extend and/or shift def : WriteRes { let Latency = 2; let ResourceCycles = [2]; let NumMicroOps = 2; } def : InstRW<[WriteISReg], (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", "ADC(W|X)r", "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", "SBCS(W|X)r", "CCMN(W|X)(i|r)", "CCMP(W|X)(i|r)", "CSEL(W|X)r", "CSINC(W|X)r", "CSINV(W|X)r", "CSNEG(W|X)r")>; def : WriteRes { let Latency = 1; let ResourceCycles = [1]; let NumMicroOps = 2; } def : InstRW<[WriteIEReg], (instregex "ADD?(W|X)r(i|r|s|x)", "ADDS?(W|X)r(i|r|s|x)(64)?", "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)", "ADC(W|X)r", "BIC?(W|X)r(i|r|s|x)", "BICS?(W|X)r(i|r|s|x)", "EON?(W|X)r(i|r|s|x)", "ORN?(W|X)r(i|r|s|x)", "ORR?(W|X)r(i|r|s|x)", "SUB?(W|X)r(i|r|s|x)", "SUBS?(W|X)r(i|r|s|x)", "SBC(W|X)r", "SBCS(W|X)r", "CCMN(W|X)(i|r)", "CCMP(W|X)(i|r)", "CSEL(W|X)r", "CSINC(W|X)r", "CSINV(W|X)r", "CSNEG(W|X)r")>; // Move immed def : WriteRes { let Latency = 1; let NumMicroOps = 2; } def : InstRW<[THX2T99Write_1Cyc_I012], (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>; def : InstRW<[THX2T99Write_1Cyc_I012], (instrs ASRVWr, ASRVXr, LSLVWr, LSLVXr, RORVWr, RORVXr)>; // Variable shift def : WriteRes { let Latency = 1; let NumMicroOps = 2; } //--- // 3.4 Divide and Multiply Instructions //--- // Divide, W-form // Latency range of 13-23/13-39. def : WriteRes { let Latency = 39; let ResourceCycles = [39]; let NumMicroOps = 4; } // Divide, X-form def : WriteRes { let Latency = 23; let ResourceCycles = [23]; let NumMicroOps = 4; } // Multiply accumulate, W-form def : WriteRes { let Latency = 5; let NumMicroOps = 3; } // Multiply accumulate, X-form def : WriteRes { let Latency = 5; let NumMicroOps = 3; } //def : InstRW<[WriteIM32, ReadIM, ReadIM, ReadIMA, THX2T99Write_5Cyc_I012], // (instrs MADDWrrr, MSUBWrrr)>; def : InstRW<[WriteIM32], (instrs MADDWrrr, MSUBWrrr)>; def : InstRW<[WriteIM32], (instrs MADDXrrr, MSUBXrrr)>; def : InstRW<[THX2T99Write_5Cyc_I012], (instregex "(S|U)(MADDL|MSUBL)rrr")>; def : InstRW<[WriteID32], (instrs SDIVWr, UDIVWr)>; def : InstRW<[WriteID64], (instrs SDIVXr, UDIVXr)>; // Bitfield extract, two reg def : WriteRes { let Latency = 1; let NumMicroOps = 2; } // Multiply high def : InstRW<[THX2T99Write_4Cyc_I1], (instrs SMULHrr, UMULHrr)>; // Miscellaneous Data-Processing Instructions // Bitfield extract def : InstRW<[THX2T99Write_1Cyc_I012], (instrs EXTRWrri, EXTRXrri)>; // Bitifield move - basic def : InstRW<[THX2T99Write_1Cyc_I012], (instrs SBFMWri, SBFMXri, UBFMWri, UBFMXri)>; // Bitfield move, insert def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>; def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>; // Count leading def : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$", "^CLZ(W|X)r$")>; // Reverse bits def : InstRW<[THX2T99Write_1Cyc_I012], (instrs RBITWr, RBITXr)>; // Cryptography Extensions def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AES[DE]")>; def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AESI?MC")>; def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL")>; def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1SU0")>; def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1(H|SU1)")>; def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA1[CMP]")>; def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA256SU0")>; def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA256(H|H2|SU1)")>; // CRC Instructions // def : InstRW<[THX2T99Write_4Cyc_I1], (instregex "^CRC32", "^CRC32C")>; def : InstRW<[THX2T99Write_4Cyc_I1], (instrs CRC32Brr, CRC32Hrr, CRC32Wrr, CRC32Xrr)>; def : InstRW<[THX2T99Write_4Cyc_I1], (instrs CRC32CBrr, CRC32CHrr, CRC32CWrr, CRC32CXrr)>; // Reverse bits/bytes // NOTE: Handled by WriteI. //--- // 3.6 Load Instructions // 3.10 FP Load Instructions //--- // Load register, literal // Load register, unscaled immed // Load register, immed unprivileged // Load register, unsigned immed def : WriteRes { let Latency = 4; let NumMicroOps = 4; } // Load register, immed post-index // NOTE: Handled by WriteLD, WriteI. // Load register, immed pre-index // NOTE: Handled by WriteLD, WriteAdr. def : WriteRes { let Latency = 1; let NumMicroOps = 2; } // Load pair, immed offset, normal // Load pair, immed offset, signed words, base != SP // Load pair, immed offset signed words, base = SP // LDP only breaks into *one* LS micro-op. Thus // the resources are handled by WriteLD. def : WriteRes { let Latency = 5; let NumMicroOps = 5; } // Load register offset, basic // Load register, register offset, scale by 4/8 // Load register, register offset, scale by 2 // Load register offset, extend // Load register, register offset, extend, scale by 4/8 // Load register, register offset, extend, scale by 2 def THX2T99WriteLDIdx : SchedWriteVariant<[ SchedVar, SchedVar]>; def : SchedAlias; def THX2T99ReadAdrBase : SchedReadVariant<[ SchedVar, SchedVar]>; def : SchedAlias; // Load pair, immed pre-index, normal // Load pair, immed pre-index, signed words // Load pair, immed post-index, normal // Load pair, immed post-index, signed words // NOTE: Handled by WriteLD, WriteLDHi, WriteAdr. def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPDi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPQi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPSi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPWi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDNPXi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPDi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPQi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPSi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPSWi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPWi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi], (instrs LDPXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRBui)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRDui)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRHui)>; def : InstRW<[THX2T99Write_5Cyc_LS01], (instrs LDRQui)>; def : InstRW<[THX2T99Write_5Cyc_LS01], (instrs LDRSui)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRDl)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRQl)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRWl)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDRXl)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRBi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRHi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRWi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSBWi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSBXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSHWi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSHXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDTRSWi)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPDpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPQpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPSpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPWpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPWpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRBpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRDpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRHpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRQpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRSpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRWpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteAdr], (instrs LDRXpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBWpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBXpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBWpost)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSBXpost)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHWpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHXpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHWpost)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRSHXpost)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRBBpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRBBpost)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRHHpre)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, WriteAdr], (instrs LDRHHpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPDpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPQpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPSpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPWpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteLDHi, WriteAdr], (instrs LDPXpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRWpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRXpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPDpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPQpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPSpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPWpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPXpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRBpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRDpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRHpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRQpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRSpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRWpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteAdr], (instrs LDRXpre)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPDpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPQpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPSpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPWpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteLDHi, WriteAdr], (instrs LDPXpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRBpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRDpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRHpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRQpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRSpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRWpost)>; def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRXpost)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRBroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRDroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHHroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRQroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHWroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHXroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRWroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRXroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRBroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRDroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHHroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRHroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRQroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHWroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRSHXroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRWroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012, ReadAdrBase], (instrs LDRXroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRBroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRBroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRDroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRHroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRHHroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRQroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRSroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRSHWroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRSHXroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRWroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRXroW)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRBroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRDroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRHroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRHHroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRQroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRSroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRSHWroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRSHXroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRWroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01_I012_I012, ReadAdrBase], (instrs LDRXroX)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURBi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURBBi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURDi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURHi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURHHi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURQi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSBWi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSBXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSHWi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSHXi)>; def : InstRW<[THX2T99Write_4Cyc_LS01], (instrs LDURSWi)>; //--- // Prefetch //--- def : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMl)>; def : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFUMi)>; def : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMui)>; def : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMroW)>; def : InstRW<[THX2T99Write_6Cyc_LS01_I012], (instrs PRFMroX)>; //-- // 3.7 Store Instructions // 3.11 FP Store Instructions //-- // Store register, unscaled immed // Store register, immed unprivileged // Store register, unsigned immed def : WriteRes { let Latency = 1; let NumMicroOps = 2; } // Store register, immed post-index // NOTE: Handled by WriteAdr, WriteST, ReadAdrBase // Store register, immed pre-index // NOTE: Handled by WriteAdr, WriteST // Store register, register offset, basic // Store register, register offset, scaled by 4/8 // Store register, register offset, scaled by 2 // Store register, register offset, extend // Store register, register offset, extend, scale by 4/8 // Store register, register offset, extend, scale by 1 def : WriteRes { let Latency = 1; let NumMicroOps = 3; } // Store pair, immed offset, W-form // Store pair, immed offset, X-form def : WriteRes { let Latency = 1; let NumMicroOps = 2; } // Store pair, immed post-index, W-form // Store pair, immed post-index, X-form // Store pair, immed pre-index, W-form // Store pair, immed pre-index, X-form // NOTE: Handled by WriteAdr, WriteSTP. def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURBi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURBBi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURDi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURHi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURHHi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURQi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURSi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURWi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STURXi)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRBi)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRHi)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRWi)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01], (instrs STTRXi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPDi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPQi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPXi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STNPWi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPDi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPQi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPXi)>; def : InstRW<[THX2T99Write_1Cyc_LS01], (instrs STPWi)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRBui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRBui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRDui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRDui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRHui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRHui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRQui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRQui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRXui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRXui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRWui)>; def : InstRW<[THX2T99Write_1Cyc_LS01_I012], (instrs STRWui)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STPDpre, STPDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STPDpre, STPDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STPDpre, STPDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STPDpre, STPDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STPQpre, STPQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STPQpre, STPQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STPQpre, STPQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STPQpre, STPQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STPSpre, STPSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STPSpre, STPSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STPSpre, STPSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STPSpre, STPSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STPWpre, STPWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STPWpre, STPWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STPWpre, STPWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STPWpre, STPWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STPXpre, STPXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STPXpre, STPXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STPXpre, STPXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STPXpre, STPXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRBpre, STRBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRBpre, STRBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRBpre, STRBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRBpre, STRBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRBBpre, STRBBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRBBpre, STRBBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRBBpre, STRBBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRBBpre, STRBBpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRDpre, STRDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRDpre, STRDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRDpre, STRDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRDpre, STRDpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRHpre, STRHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRHpre, STRHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRHpre, STRHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRHpre, STRHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRHHpre, STRHHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRHHpre, STRHHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRHHpre, STRHHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRHHpre, STRHHpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRQpre, STRQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRQpre, STRQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRQpre, STRQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRQpre, STRQpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRSpre, STRSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRSpre, STRSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRSpre, STRSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRSpre, STRSpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRWpre, STRWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRWpre, STRWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRWpre, STRWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRWpre, STRWpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012], (instrs STRXpre, STRXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRXpre, STRXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012], (instrs STRXpre, STRXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRXpre, STRXpost)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRBroW, STRBroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRBroW, STRBroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRBBroW, STRBBroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRBBroW, STRBBroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRDroW, STRDroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRDroW, STRDroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRHroW, STRHroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRHroW, STRHroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRHHroW, STRHHroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRHHroW, STRHHroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRQroW, STRQroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRQroW, STRQroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRSroW, STRSroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRSroW, STRSroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRWroW, STRWroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRWroW, STRWroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012, ReadAdrBase], (instrs STRXroW, STRXroX)>; def : InstRW<[WriteAdr, THX2T99Write_1Cyc_LS01_I012_I012, ReadAdrBase], (instrs STRXroW, STRXroX)>; //--- // 3.8 FP Data Processing Instructions //--- // FP absolute value // FP min/max // FP negate def : WriteRes { let Latency = 5; let NumMicroOps = 2; } // FP arithmetic def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FADD", "^FSUB")>; // FP compare def : WriteRes { let Latency = 5; let NumMicroOps = 2; } // FP Mul, Div, Sqrt def : WriteRes { let Latency = 22; let ResourceCycles = [19]; } def THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> { let Latency = 16; let ResourceCycles = [8]; let NumMicroOps = 4; } def THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> { let Latency = 16; let ResourceCycles = [8]; let NumMicroOps = 4; } def THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> { let Latency = 23; let ResourceCycles = [12]; let NumMicroOps = 4; } def THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> { let Latency = 16; let ResourceCycles = [8]; let NumMicroOps = 4; } def THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> { let Latency = 23; let ResourceCycles = [12]; let NumMicroOps = 4; } // FP divide, S-form // FP square root, S-form def : InstRW<[THX2T99XWriteFDivSP], (instrs FDIVSrr)>; def : InstRW<[THX2T99XWriteFSqrtSP], (instrs FSQRTSr)>; def : InstRW<[THX2T99XWriteFDivSP], (instregex "^FDIVv.*32$")>; def : InstRW<[THX2T99XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>; def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "^FDIVSrr", "^FSQRTSr")>; // FP divide, D-form // FP square root, D-form def : InstRW<[THX2T99XWriteFDivDP], (instrs FDIVDrr)>; def : InstRW<[THX2T99XWriteFSqrtDP], (instrs FSQRTDr)>; def : InstRW<[THX2T99XWriteFDivDP], (instregex "^FDIVv.*64$")>; def : InstRW<[THX2T99XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>; def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>; // FP multiply // FP multiply accumulate def : WriteRes { let Latency = 6; let ResourceCycles = [2]; let NumMicroOps = 3; } def THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> { let Latency = 6; let ResourceCycles = [2]; let NumMicroOps = 3; } def THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> { let Latency = 6; let ResourceCycles = [2]; let NumMicroOps = 3; } def : InstRW<[THX2T99XWriteFMul], (instregex "^FMUL", "^FNMUL")>; def : InstRW<[THX2T99XWriteFMulAcc], (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>; // FP round to integral def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>; // FP select def : InstRW<[THX2T99Write_4Cyc_F01], (instregex "^FCSEL")>; //--- // 3.9 FP Miscellaneous Instructions //--- // FP convert, from vec to vec reg // FP convert, from gen to vec reg // FP convert, from vec to gen reg def : WriteRes { let Latency = 7; let NumMicroOps = 3; } // FP move, immed // FP move, register def : WriteRes { let Latency = 4; let NumMicroOps = 2; } // FP transfer, from gen to vec reg // FP transfer, from vec to gen reg def : WriteRes { let Latency = 4; let NumMicroOps = 2; } def : InstRW<[THX2T99Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>; //--- // 3.12 ASIMD Integer Instructions //--- // ASIMD absolute diff, D-form // ASIMD absolute diff, Q-form // ASIMD absolute diff accum, D-form // ASIMD absolute diff accum, Q-form // ASIMD absolute diff accum long // ASIMD absolute diff long // ASIMD arith, basic // ASIMD arith, complex // ASIMD compare // ASIMD logical (AND, BIC, EOR) // ASIMD max/min, basic // ASIMD max/min, reduce, 4H/4S // ASIMD max/min, reduce, 8B/8H // ASIMD max/min, reduce, 16B // ASIMD multiply, D-form // ASIMD multiply, Q-form // ASIMD multiply accumulate long // ASIMD multiply accumulate saturating long // ASIMD multiply long // ASIMD pairwise add and accumulate // ASIMD shift accumulate // ASIMD shift by immed, basic // ASIMD shift by immed and insert, basic, D-form // ASIMD shift by immed and insert, basic, Q-form // ASIMD shift by immed, complex // ASIMD shift by register, basic, D-form // ASIMD shift by register, basic, Q-form // ASIMD shift by register, complex, D-form // ASIMD shift by register, complex, Q-form def : WriteRes { let Latency = 7; let NumMicroOps = 4; let ResourceCycles = [4]; } // ASIMD arith, reduce, 4H/4S // ASIMD arith, reduce, 8B/8H // ASIMD arith, reduce, 16B // ASIMD logical (MVN (alias for NOT), ORN, ORR) def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^ANDv", "^BICv", "^EORv", "^ORRv", "^ORNv", "^NOTv")>; // ASIMD arith, reduce def : InstRW<[THX2T99Write_10Cyc_F01], (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>; // ASIMD polynomial (8x8) multiply long def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^(S|U|SQD)MULL")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(S|U|SQD)(MLAL|MLSL|MULL)v.*")>; def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL(v8i8|v16i8)")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64|v2i64)")>; // ASIMD absolute diff accum, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>; // ASIMD absolute diff accum, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>; // ASIMD absolute diff accum long def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]ABAL")>; // ASIMD arith, reduce, 4H/4S def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>; // ASIMD arith, reduce, 8B def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>; // ASIMD arith, reduce, 16B/16H def : InstRW<[THX2T99Write_10Cyc_F01], (instregex "^[SU]?ADDL?Vv16i8v$")>; // ASIMD max/min, reduce, 4H/4S def : InstRW<[THX2T99Write_10Cyc_F01], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>; // ASIMD max/min, reduce, 8B/8H def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>; // ASIMD max/min, reduce, 16B/16H def : InstRW<[THX2T99Write_10Cyc_F01], (instregex "^[SU](MIN|MAX)Vv16i8v$")>; // ASIMD multiply, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^(P?MUL|SQR?DMULH)" # "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" # "(_indexed)?$")>; // ASIMD multiply, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>; // ASIMD multiply accumulate, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>; // ASIMD multiply accumulate, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>; // ASIMD shift accumulate def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "SRSRAv","SSRAv","URSRAv","USRAv")>; // ASIMD shift by immed, basic def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "RSHRNv","SHRNv", "SQRSHRNv","SQRSHRUNv", "SQSHRNv","SQSHRUNv", "UQRSHRNv", "UQSHRNv","SQXTNv","SQXTUNv","UQXTNv")>; // ASIMD shift by immed, complex def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]?(Q|R){1,2}SHR")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SQSHLU")>; // ASIMD shift by register, basic, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>; // ASIMD shift by register, complex, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU][QR]{1,2}SHL" # "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>; // ASIMD shift by register, complex, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>; // ASIMD Arithmetic def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(ADD|SUB)(v16i8|v8i16|v4i32|v2i64)")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(ADD|SUB)HNv.*")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "(RADD|RSUB)HNv.*")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD", "^SUQADD", "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "ADDP(v16i8|v8i16|v4i32|v2i64)")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "((AND|ORN|EOR|EON)S?(Xr[rsi]|v16i8|v8i16|v4i32)|" # "(ORR|BIC)S?(Xr[rs]|v16i8|v8i16|v4i32))")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADALP","^UADALP")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLPv","^UADDLPv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLV","^UADDLV")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^ADDVv","^SMAXVv","^UMAXVv","^SMINVv","^UMINVv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SABAv","^UABAv","^SABALv","^UABALv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SQADDv","^SQSUBv","^UQADDv","^UQSUBv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SUQADDv","^USQADDv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^ADDHNv","^RADDHNv", "^RSUBHNv", "^SQABS", "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD", "^SUBHNv", "^SUQADD", "^UQADD", "^UQSUB", "^URHADD", "^USQADD")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^CMEQv","^CMGEv","^CMGTv", "^CMLEv","^CMLTv", "^CMHIv","^CMHSv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SMAXv","^SMINv","^UMAXv","^UMINv", "^SMAXPv","^SMINPv","^UMAXPv","^UMINPv")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SABDv","^UABDv", "^SABDLv","^UABDLv")>; //--- // 3.13 ASIMD Floating-point Instructions //--- // ASIMD FP absolute value def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FABSv")>; // ASIMD FP arith, normal, D-form // ASIMD FP arith, normal, Q-form def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FABDv", "^FADDv", "^FSUBv")>; // ASIMD FP arith,pairwise, D-form // ASIMD FP arith, pairwise, Q-form def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FADDPv")>; // ASIMD FP compare, D-form // ASIMD FP compare, Q-form def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FACGEv", "^FACGTv")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FCMEQv", "^FCMGEv", "^FCMGTv", "^FCMLEv", "^FCMLTv")>; // ASIMD FP round, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FRINT[AIMNPXZ](v2f32)")>; // ASIMD FP round, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>; // ASIMD FP convert, long // ASIMD FP convert, narrow // ASIMD FP convert, other, D-form // ASIMD FP convert, other, Q-form // NOTE: Handled by WriteV. // ASIMD FP convert, long and narrow def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FCVT(L|N|XN)v")>; // ASIMD FP convert, other, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>; // ASIMD FP convert, other, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP divide, D-form, F32 def : InstRW<[THX2T99Write_16Cyc_F01], (instrs FDIVv2f32)>; def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "FDIVv2f32")>; // ASIMD FP divide, Q-form, F32 def : InstRW<[THX2T99Write_16Cyc_F01], (instrs FDIVv4f32)>; def : InstRW<[THX2T99Write_16Cyc_F01], (instregex "FDIVv4f32")>; // ASIMD FP divide, Q-form, F64 def : InstRW<[THX2T99Write_23Cyc_F01], (instrs FDIVv2f64)>; def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "FDIVv2f64")>; // ASIMD FP max/min, normal, D-form // ASIMD FP max/min, normal, Q-form def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXv", "^FMAXNMv", "^FMINv", "^FMINNMv")>; // ASIMD FP max/min, pairwise, D-form // ASIMD FP max/min, pairwise, Q-form def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXPv", "^FMAXNMPv", "^FMINPv", "^FMINNMPv")>; // ASIMD FP max/min, reduce def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMAXVv", "^FMAXNMVv", "^FMINVv", "^FMINNMVv")>; // ASIMD FP multiply, D-form, FZ // ASIMD FP multiply, D-form, no FZ // ASIMD FP multiply, Q-form, FZ // ASIMD FP multiply, Q-form, no FZ def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMULv", "^FMULXv")>; def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>; def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP multiply accumulate, Dform, FZ // ASIMD FP multiply accumulate, Dform, no FZ // ASIMD FP multiply accumulate, Qform, FZ // ASIMD FP multiply accumulate, Qform, no FZ def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FMLAv", "^FMLSv")>; def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; // ASIMD FP negate def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FNEGv")>; //-- // 3.14 ASIMD Miscellaneous Instructions //-- // ASIMD bit reverse def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^RBITv")>; // ASIMD bitwise insert, D-form // ASIMD bitwise insert, Q-form def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^BIFv", "^BITv", "^BSLv")>; // ASIMD count, D-form // ASIMD count, Q-form def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^CLSv", "^CLZv", "^CNTv")>; // ASIMD duplicate, gen reg // ASIMD duplicate, element def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^CPY")>; def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^DUPv.+gpr")>; // ASIMD extract def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^EXTv")>; // ASIMD extract narrow def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^XTNv")>; // ASIMD extract narrow, saturating def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SQXTNv", "^SQXTUNv", "^UQXTNv")>; // ASIMD insert, element to element def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; // ASIMD transfer, element to gen reg def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; // ASIMD move, integer immed def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>; // ASIMD move, FP immed def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>; // ASIMD table lookup, D-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8One")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Two")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Three")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Four")>; // ASIMD table lookup, Q-form def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8One")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Two")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Three")>; def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Four")>; // ASIMD transpose def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1", "^TRN2")>; // ASIMD unzip/zip def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>; // ASIMD reciprocal estimate, D-form // ASIMD reciprocal estimate, Q-form def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FRECPEv", "^FRECPXv", "^URECPEv", "^FRSQRTEv", "^URSQRTEv")>; // ASIMD reciprocal step, D-form, FZ // ASIMD reciprocal step, D-form, no FZ // ASIMD reciprocal step, Q-form, FZ // ASIMD reciprocal step, Q-form, no FZ def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "^FRECPSv", "^FRSQRTSv")>; // ASIMD reverse def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^REV16v", "^REV32v", "^REV64v")>; // ASIMD table lookup, D-form // ASIMD table lookup, Q-form def : InstRW<[THX2T99Write_8Cyc_F01], (instregex "^TBLv", "^TBXv")>; // ASIMD transfer, element to word or word def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^[SU]MOVv")>; // ASIMD transfer, element to gen reg def : InstRW<[THX2T99Write_6Cyc_F01], (instregex "(S|U)MOVv.*")>; // ASIMD transfer gen reg to element def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^INSv")>; // ASIMD transpose def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1v", "^TRN2v", "^UZP1v", "^UZP2v")>; // ASIMD unzip/zip def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>; //-- // 3.15 ASIMD Load Instructions //-- // ASIMD load, 1 element, multiple, 1 reg, D-form // ASIMD load, 1 element, multiple, 1 reg, Q-form def : InstRW<[THX2T99Write_4Cyc_LS01], (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_4Cyc_LS01, WriteAdr], (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 1 element, multiple, 2 reg, D-form // ASIMD load, 1 element, multiple, 2 reg, Q-form def : InstRW<[THX2T99Write_4Cyc_LS01], (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_4Cyc_LS01, WriteAdr], (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 1 element, multiple, 3 reg, D-form // ASIMD load, 1 element, multiple, 3 reg, Q-form def : InstRW<[THX2T99Write_5Cyc_LS01], (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_5Cyc_LS01, WriteAdr], (instregex "^LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 1 element, multiple, 4 reg, D-form // ASIMD load, 1 element, multiple, 4 reg, Q-form def : InstRW<[THX2T99Write_6Cyc_LS01], (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_6Cyc_LS01, WriteAdr], (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 1 element, one lane, B/H/S // ASIMD load, 1 element, one lane, D def : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD1i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], (instregex "^LD1i(8|16|32|64)_POST$")>; // ASIMD load, 1 element, all lanes, D-form, B/H/S // ASIMD load, 1 element, all lanes, D-form, D // ASIMD load, 1 element, all lanes, Q-form def : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 2 element, multiple, D-form, B/H/S // ASIMD load, 2 element, multiple, Q-form, D def : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>; // ASIMD load, 2 element, one lane, B/H // ASIMD load, 2 element, one lane, S // ASIMD load, 2 element, one lane, D def : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD2i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], (instregex "^LD2i(8|16|32|64)_POST$")>; // ASIMD load, 2 element, all lanes, D-form, B/H/S // ASIMD load, 2 element, all lanes, D-form, D // ASIMD load, 2 element, all lanes, Q-form def : InstRW<[THX2T99Write_5Cyc_LS01_F01], (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_5Cyc_LS01_F01, WriteAdr], (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 3 element, multiple, D-form, B/H/S // ASIMD load, 3 element, multiple, Q-form, B/H/S // ASIMD load, 3 element, multiple, Q-form, D def : InstRW<[THX2T99Write_8Cyc_LS01_F01], (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_8Cyc_LS01_F01, WriteAdr], (instregex "^LD3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>; // ASIMD load, 3 element, one lone, B/H // ASIMD load, 3 element, one lane, S // ASIMD load, 3 element, one lane, D def : InstRW<[THX2T99Write_7Cyc_LS01_F01], (instregex "^LD3i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_7Cyc_LS01_F01, WriteAdr], (instregex "^LD3i(8|16|32|64)_POST$")>; // ASIMD load, 3 element, all lanes, D-form, B/H/S // ASIMD load, 3 element, all lanes, D-form, D // ASIMD load, 3 element, all lanes, Q-form, B/H/S // ASIMD load, 3 element, all lanes, Q-form, D def : InstRW<[THX2T99Write_7Cyc_LS01_F01], (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_7Cyc_LS01_F01, WriteAdr], (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD load, 4 element, multiple, D-form, B/H/S // ASIMD load, 4 element, multiple, Q-form, B/H/S // ASIMD load, 4 element, multiple, Q-form, D def : InstRW<[THX2T99Write_8Cyc_LS01_F01], (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_8Cyc_LS01_F01, WriteAdr], (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>; // ASIMD load, 4 element, one lane, B/H // ASIMD load, 4 element, one lane, S // ASIMD load, 4 element, one lane, D def : InstRW<[THX2T99Write_6Cyc_LS01_F01], (instregex "^LD4i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_6Cyc_LS01_F01, WriteAdr], (instregex "^LD4i(8|16|32|64)_POST$")>; // ASIMD load, 4 element, all lanes, D-form, B/H/S // ASIMD load, 4 element, all lanes, D-form, D // ASIMD load, 4 element, all lanes, Q-form, B/H/S // ASIMD load, 4 element, all lanes, Q-form, D def : InstRW<[THX2T99Write_6Cyc_LS01_F01], (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_6Cyc_LS01_F01, WriteAdr], (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; //-- // 3.16 ASIMD Store Instructions //-- // ASIMD store, 1 element, multiple, 1 reg, D-form // ASIMD store, 1 element, multiple, 1 reg, Q-form def : InstRW<[THX2T99Write_1Cyc_LS01], (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD store, 1 element, multiple, 2 reg, D-form // ASIMD store, 1 element, multiple, 2 reg, Q-form def : InstRW<[THX2T99Write_1Cyc_LS01], (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD store, 1 element, multiple, 3 reg, D-form // ASIMD store, 1 element, multiple, 3 reg, Q-form def : InstRW<[THX2T99Write_1Cyc_LS01], (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], (instregex "^ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD store, 1 element, multiple, 4 reg, D-form // ASIMD store, 1 element, multiple, 4 reg, Q-form def : InstRW<[THX2T99Write_1Cyc_LS01], (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01, WriteAdr], (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; // ASIMD store, 1 element, one lane, B/H/S // ASIMD store, 1 element, one lane, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST1i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST1i(8|16|32|64)_POST$")>; // ASIMD store, 2 element, multiple, D-form, B/H/S // ASIMD store, 2 element, multiple, Q-form, B/H/S // ASIMD store, 2 element, multiple, Q-form, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|2d)_POST$")>; // ASIMD store, 2 element, one lane, B/H/S // ASIMD store, 2 element, one lane, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST2i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST2i(8|16|32|64)_POST$")>; // ASIMD store, 3 element, multiple, D-form, B/H/S // ASIMD store, 3 element, multiple, Q-form, B/H/S // ASIMD store, 3 element, multiple, Q-form, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST3Threev(8b|4h|2s|16b|8h|4s|2d)_POST$")>; // ASIMD store, 3 element, one lane, B/H // ASIMD store, 3 element, one lane, S // ASIMD store, 3 element, one lane, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST3i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST3i(8|16|32|64)_POST$")>; // ASIMD store, 4 element, multiple, D-form, B/H/S // ASIMD store, 4 element, multiple, Q-form, B/H/S // ASIMD store, 4 element, multiple, Q-form, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|2d)_POST$")>; // ASIMD store, 4 element, one lane, B/H // ASIMD store, 4 element, one lane, S // ASIMD store, 4 element, one lane, D def : InstRW<[THX2T99Write_1Cyc_LS01_F01], (instregex "^ST4i(8|16|32|64)$")>; def : InstRW<[THX2T99Write_1Cyc_LS01_F01, WriteAdr], (instregex "^ST4i(8|16|32|64)_POST$")>; // V8.1a Atomics (LSE) def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs CASB, CASH, CASW, CASX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs CASAB, CASAH, CASAW, CASAX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs CASLB, CASLH, CASLW, CASLX)>; def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs CASALB, CASALH, CASALW, CASALX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDLARB, LDLARH, LDLARW, LDLARX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDADDB, LDADDH, LDADDW, LDADDX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDADDAB, LDADDAH, LDADDAW, LDADDAX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDADDLB, LDADDLH, LDADDLW, LDADDLX)>; def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs LDADDALB, LDADDALH, LDADDALW, LDADDALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDCLRB, LDCLRH, LDCLRW, LDCLRX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDCLRAB, LDCLRAH, LDCLRAW, LDCLRAX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDCLRLB, LDCLRLH, LDCLRLW, LDCLRLX)>; def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs LDCLRALB, LDCLRALH, LDCLRALW, LDCLRALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDEORB, LDEORH, LDEORW, LDEORX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDEORAB, LDEORAH, LDEORAW, LDEORAX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDEORLB, LDEORLH, LDEORLW, LDEORLX)>; def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs LDEORALB, LDEORALH, LDEORALW, LDEORALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDSETB, LDSETH, LDSETW, LDSETX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDSETAB, LDSETAH, LDSETAW, LDSETAX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs LDSETLB, LDSETLH, LDSETLW, LDSETLX)>; def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs LDSETALB, LDSETALH, LDSETALW, LDSETALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDSMAXB, LDSMAXH, LDSMAXW, LDSMAXX, LDSMAXAB, LDSMAXAH, LDSMAXAW, LDSMAXAX, LDSMAXLB, LDSMAXLH, LDSMAXLW, LDSMAXLX, LDSMAXALB, LDSMAXALH, LDSMAXALW, LDSMAXALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDSMINB, LDSMINH, LDSMINW, LDSMINX, LDSMINAB, LDSMINAH, LDSMINAW, LDSMINAX, LDSMINLB, LDSMINLH, LDSMINLW, LDSMINLX, LDSMINALB, LDSMINALH, LDSMINALW, LDSMINALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDUMAXB, LDUMAXH, LDUMAXW, LDUMAXX, LDUMAXAB, LDUMAXAH, LDUMAXAW, LDUMAXAX, LDUMAXLB, LDUMAXLH, LDUMAXLW, LDUMAXLX, LDUMAXALB, LDUMAXALH, LDUMAXALW, LDUMAXALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs LDUMINB, LDUMINH, LDUMINW, LDUMINX, LDUMINAB, LDUMINAH, LDUMINAW, LDUMINAX, LDUMINLB, LDUMINLH, LDUMINLW, LDUMINLX, LDUMINALB, LDUMINALH, LDUMINALW, LDUMINALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs SWPB, SWPH, SWPW, SWPX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs SWPAB, SWPAH, SWPAW, SWPAX)>; def : InstRW<[THX2T99Write_12Cyc_I012, WriteAtomic], (instrs SWPLB, SWPLH, SWPLW, SWPLX)>; def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs SWPALB, SWPALH, SWPALW, SWPALX)>; def : InstRW<[THX2T99Write_8Cyc_I012, WriteAtomic], (instrs STLLRB, STLLRH, STLLRW, STLLRX)>; } // SchedModel = ThunderX2T99Model capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64Schedule.td000064400000000000000000000105270072674642500254450ustar 00000000000000//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // Define TII for use in SchedVariant Predicates. // const MachineInstr *MI and const TargetSchedModel *SchedModel // are defined by default. def : PredicateProlog<[{ const AArch64InstrInfo *TII = static_cast(SchedModel->getInstrInfo()); (void)TII; }]>; // AArch64 Scheduler Definitions def WriteImm : SchedWrite; // MOVN, MOVZ // TODO: Provide variants for MOV32/64imm Pseudos that dynamically // select the correct sequence of WriteImms. def WriteI : SchedWrite; // ALU def WriteISReg : SchedWrite; // ALU of Shifted-Reg def WriteIEReg : SchedWrite; // ALU of Extended-Reg def ReadI : SchedRead; // ALU def ReadISReg : SchedRead; // ALU of Shifted-Reg def ReadIEReg : SchedRead; // ALU of Extended-Reg def WriteExtr : SchedWrite; // EXTR shifts a reg pair def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair def WriteIS : SchedWrite; // Shift/Scale def WriteID32 : SchedWrite; // 32-bit Divide def WriteID64 : SchedWrite; // 64-bit Divide def ReadID : SchedRead; // 32/64-bit Divide def WriteIM32 : SchedWrite; // 32-bit Multiply def WriteIM64 : SchedWrite; // 64-bit Multiply def ReadIM : SchedRead; // 32/64-bit Multiply def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate def WriteBr : SchedWrite; // Branch def WriteBrReg : SchedWrite; // Indirect Branch def WriteLD : SchedWrite; // Load from base addr plus immediate offset def WriteST : SchedWrite; // Store to base addr plus immediate offset def WriteSTP : SchedWrite; // Store a register pair. def WriteAdr : SchedWrite; // Address pre/post increment. def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled). def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. // Predicate for determining when a shiftable register is shifted. def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(*MI)}]>; // Predicate for determining when a extendedable register is extended. def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>; // ScaledIdxPred is true if a WriteLDIdx operand will be // scaled. Subtargets can use this to dynamically select resources and // latency for WriteLDIdx and ReadAdrBase. def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(*MI)}]>; // Serialized two-level address load. // EXAMPLE: LOADGot def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>; // Serialized two-level address lookup. // EXAMPLE: MOVaddr... def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>; // The second register of a load-pair. // LDP,LDPSW,LDNP,LDXP,LDAXP def WriteLDHi : SchedWrite; // Store-exclusive is a store followed by a dependent load. def WriteSTX : WriteSequence<[WriteST, WriteLD]>; def WriteSys : SchedWrite; // Long, variable latency system ops. def WriteBarrier : SchedWrite; // Memory barrier. def WriteHint : SchedWrite; // Hint instruction. def WriteF : SchedWrite; // General floating-point ops. def WriteFCmp : SchedWrite; // Floating-point compare. def WriteFCvt : SchedWrite; // Float conversion. def WriteFCopy : SchedWrite; // Float-int register copy. def WriteFImm : SchedWrite; // Floating-point immediate. def WriteFMul : SchedWrite; // Floating-point multiply. def WriteFDiv : SchedWrite; // Floating-point division. def WriteV : SchedWrite; // Vector ops. def WriteVLD : SchedWrite; // Vector loads. def WriteVST : SchedWrite; // Vector stores. def WriteAtomic : SchedWrite; // Atomic memory operations (CAS, Swap, LDOP) // Read the unwritten lanes of the VLD's destination registers. def ReadVLD : SchedRead; // Sequential vector load and shuffle. def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>; def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>; // Store a shuffled vector. def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>; def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/AArch64SystemOperands.td000064400000000000000000002231540072674642500266730ustar 00000000000000//===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file defines the symbolic operands permitted for various kinds of // AArch64 system instruction. // //===----------------------------------------------------------------------===// include "llvm/TableGen/SearchableTable.td" //===----------------------------------------------------------------------===// // AT (address translate) instruction options. //===----------------------------------------------------------------------===// class AT op1, bits<4> crn, bits<4> crm, bits<3> op2> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<14> Encoding; let Encoding{13-11} = op1; let Encoding{10-7} = crn; let Encoding{6-3} = crm; let Encoding{2-0} = op2; code Requires = [{ {} }]; } def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>; def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>; def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>; def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>; def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>; def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>; def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>; def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>; def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>; def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>; def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>; def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>; let Requires = [{ {AArch64::HasV8_2aOps} }] in { def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; } //===----------------------------------------------------------------------===// // DMB/DSB (data barrier) instruction options. //===----------------------------------------------------------------------===// class DB encoding> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<4> Encoding = encoding; } def : DB<"oshld", 0x1>; def : DB<"oshst", 0x2>; def : DB<"osh", 0x3>; def : DB<"nshld", 0x5>; def : DB<"nshst", 0x6>; def : DB<"nsh", 0x7>; def : DB<"ishld", 0x9>; def : DB<"ishst", 0xa>; def : DB<"ish", 0xb>; def : DB<"ld", 0xd>; def : DB<"st", 0xe>; def : DB<"sy", 0xf>; //===----------------------------------------------------------------------===// // DC (data cache maintenance) instruction options. //===----------------------------------------------------------------------===// class DC op1, bits<4> crn, bits<4> crm, bits<3> op2> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<14> Encoding; let Encoding{13-11} = op1; let Encoding{10-7} = crn; let Encoding{6-3} = crm; let Encoding{2-0} = op2; code Requires = [{ {} }]; } def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>; def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>; def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>; def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>; def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>; def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>; def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; let Requires = [{ {AArch64::HasV8_2aOps} }] in def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; //===----------------------------------------------------------------------===// // IC (instruction cache maintenance) instruction options. //===----------------------------------------------------------------------===// class IC op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<14> Encoding; let Encoding{13-11} = op1; let Encoding{10-7} = crn; let Encoding{6-3} = crm; let Encoding{2-0} = op2; bit NeedsReg = needsreg; } def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>; def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>; def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>; //===----------------------------------------------------------------------===// // ISB (instruction-fetch barrier) instruction options. //===----------------------------------------------------------------------===// class ISB encoding> : SearchableTable{ let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<4> Encoding; let Encoding = encoding; } def : ISB<"sy", 0xf>; //===----------------------------------------------------------------------===// // TSB (Trace synchronization barrier) instruction options. //===----------------------------------------------------------------------===// class TSB encoding> : SearchableTable{ let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<4> Encoding; let Encoding = encoding; code Requires = [{ {AArch64::HasV8_4aOps} }]; } def : TSB<"csync", 0>; //===----------------------------------------------------------------------===// // PRFM (prefetch) instruction options. //===----------------------------------------------------------------------===// class PRFM encoding> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<5> Encoding; let Encoding = encoding; } def : PRFM<"pldl1keep", 0x00>; def : PRFM<"pldl1strm", 0x01>; def : PRFM<"pldl2keep", 0x02>; def : PRFM<"pldl2strm", 0x03>; def : PRFM<"pldl3keep", 0x04>; def : PRFM<"pldl3strm", 0x05>; def : PRFM<"plil1keep", 0x08>; def : PRFM<"plil1strm", 0x09>; def : PRFM<"plil2keep", 0x0a>; def : PRFM<"plil2strm", 0x0b>; def : PRFM<"plil3keep", 0x0c>; def : PRFM<"plil3strm", 0x0d>; def : PRFM<"pstl1keep", 0x10>; def : PRFM<"pstl1strm", 0x11>; def : PRFM<"pstl2keep", 0x12>; def : PRFM<"pstl2strm", 0x13>; def : PRFM<"pstl3keep", 0x14>; def : PRFM<"pstl3strm", 0x15>; //===----------------------------------------------------------------------===// // SVE Prefetch instruction options. //===----------------------------------------------------------------------===// class SVEPRFM encoding> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<4> Encoding; let Encoding = encoding; code Requires = [{ {} }]; } let Requires = [{ {AArch64::FeatureSVE} }] in { def : SVEPRFM<"pldl1keep", 0x00>; def : SVEPRFM<"pldl1strm", 0x01>; def : SVEPRFM<"pldl2keep", 0x02>; def : SVEPRFM<"pldl2strm", 0x03>; def : SVEPRFM<"pldl3keep", 0x04>; def : SVEPRFM<"pldl3strm", 0x05>; def : SVEPRFM<"pstl1keep", 0x08>; def : SVEPRFM<"pstl1strm", 0x09>; def : SVEPRFM<"pstl2keep", 0x0a>; def : SVEPRFM<"pstl2strm", 0x0b>; def : SVEPRFM<"pstl3keep", 0x0c>; def : SVEPRFM<"pstl3strm", 0x0d>; } //===----------------------------------------------------------------------===// // SVE Predicate patterns //===----------------------------------------------------------------------===// class SVEPREDPAT encoding> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<5> Encoding; let Encoding = encoding; } def : SVEPREDPAT<"pow2", 0x00>; def : SVEPREDPAT<"vl1", 0x01>; def : SVEPREDPAT<"vl2", 0x02>; def : SVEPREDPAT<"vl3", 0x03>; def : SVEPREDPAT<"vl4", 0x04>; def : SVEPREDPAT<"vl5", 0x05>; def : SVEPREDPAT<"vl6", 0x06>; def : SVEPREDPAT<"vl7", 0x07>; def : SVEPREDPAT<"vl8", 0x08>; def : SVEPREDPAT<"vl16", 0x09>; def : SVEPREDPAT<"vl32", 0x0a>; def : SVEPREDPAT<"vl64", 0x0b>; def : SVEPREDPAT<"vl128", 0x0c>; def : SVEPREDPAT<"vl256", 0x0d>; def : SVEPREDPAT<"mul4", 0x1d>; def : SVEPREDPAT<"mul3", 0x1e>; def : SVEPREDPAT<"all", 0x1f>; //===----------------------------------------------------------------------===// // Exact FP Immediates. // // These definitions are used to create a lookup table with FP Immediates that // is used for a few instructions that only accept a limited set of exact FP // immediates values. //===----------------------------------------------------------------------===// class ExactFPImm enum > : SearchableTable { let SearchableFields = ["Enum", "Repr"]; let EnumValueField = "Enum"; string Name = name; bits<4> Enum = enum; string Repr = repr; } def : ExactFPImm<"zero", "0.0", 0x0>; def : ExactFPImm<"half", "0.5", 0x1>; def : ExactFPImm<"one", "1.0", 0x2>; def : ExactFPImm<"two", "2.0", 0x3>; //===----------------------------------------------------------------------===// // PState instruction options. //===----------------------------------------------------------------------===// class PState encoding> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<5> Encoding; let Encoding = encoding; code Requires = [{ {} }]; } def : PState<"SPSel", 0b00101>; def : PState<"DAIFSet", 0b11110>; def : PState<"DAIFClr", 0b11111>; // v8.1a "Privileged Access Never" extension-specific PStates let Requires = [{ {AArch64::HasV8_1aOps} }] in def : PState<"PAN", 0b00100>; // v8.2a "User Access Override" extension-specific PStates let Requires = [{ {AArch64::HasV8_2aOps} }] in def : PState<"UAO", 0b00011>; // v8.4a timining insensitivity of data processing instructions let Requires = [{ {AArch64::HasV8_4aOps} }] in def : PState<"DIT", 0b11010>; //===----------------------------------------------------------------------===// // PSB instruction options. //===----------------------------------------------------------------------===// class PSB encoding> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<5> Encoding; let Encoding = encoding; } def : PSB<"csync", 0x11>; //===----------------------------------------------------------------------===// // TLBI (translation lookaside buffer invalidate) instruction options. //===----------------------------------------------------------------------===// class TLBI op1, bits<4> crn, bits<4> crm, bits<3> op2, bit needsreg = 1> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<14> Encoding; let Encoding{13-11} = op1; let Encoding{10-7} = crn; let Encoding{6-3} = crm; let Encoding{2-0} = op2; bit NeedsReg = needsreg; code Requires = [{ {} }]; } def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>; def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>; def : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>; def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>; def : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>; def : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>; def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>; def : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>; def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>; def : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>; def : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>; def : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>; def : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>; def : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>; def : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>; def : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>; def : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>; def : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>; def : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>; def : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>; def : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>; def : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>; def : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>; def : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>; def : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>; def : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>; def : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>; def : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>; def : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>; def : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; // Armv8.4-A Outer Sharable TLB Maintenance instructions: let Requires = [{ {AArch64::HasV8_4aOps} }] in { // op1 CRn CRm op2 def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>; def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>; def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>; def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>; def : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>; def : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>; def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>; def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>; def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>; def : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>; def : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>; def : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>; def : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>; def : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>; // Armv8.4-A TLB Range Maintenance instructions: // op1 CRn CRm op2 def : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>; def : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>; def : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>; def : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>; def : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>; def : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>; def : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>; def : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>; def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>; def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>; def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>; def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>; def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>; def : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>; def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>; def : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>; def : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>; def : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>; def : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>; def : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>; def : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>; def : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>; def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>; def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>; def : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>; def : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>; def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; } //===----------------------------------------------------------------------===// // MRS/MSR (system register read/write) instruction options. //===----------------------------------------------------------------------===// class SysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> : SearchableTable { let SearchableFields = ["Name", "Encoding"]; let EnumValueField = "Encoding"; string Name = name; bits<16> Encoding; let Encoding{15-14} = op0; let Encoding{13-11} = op1; let Encoding{10-7} = crn; let Encoding{6-3} = crm; let Encoding{2-0} = op2; bit Readable = ?; bit Writeable = ?; code Requires = [{ {} }]; } class RWSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> : SysReg { let Readable = 1; let Writeable = 1; } class ROSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> : SysReg { let Readable = 1; let Writeable = 0; } class WOSysReg op0, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2> : SysReg { let Readable = 0; let Writeable = 1; } //===---------------------- // Read-only regs //===---------------------- // Op0 Op1 CRn CRm Op2 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>; def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>; def : ROSysReg<"OSLSR_EL1", 0b10, 0b000, 0b0001, 0b0001, 0b100>; def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { let Requires = [{ {AArch64::HasV8_3aOps} }]; } def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>; def : ROSysReg<"REVIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b110>; def : ROSysReg<"AIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b111>; def : ROSysReg<"DCZID_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b111>; def : ROSysReg<"ID_PFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b000>; def : ROSysReg<"ID_PFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b001>; def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; def : ROSysReg<"ID_MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b110>; def : ROSysReg<"ID_MMFR3_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b111>; def : ROSysReg<"ID_ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b000>; def : ROSysReg<"ID_ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b001>; def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>; def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>; def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>; def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>; def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> { let Requires = [{ {AArch64::HasV8_2aOps} }]; } def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>; def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>; def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>; def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>; def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>; def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>; def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> { let Requires = [{ {AArch64::HasV8_2aOps} }]; } def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>; def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>; def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>; def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>; def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; def : ROSysReg<"ID_MMFR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b110>; // Trace registers // Op0 Op1 CRn CRm Op2 def : ROSysReg<"TRCSTATR", 0b10, 0b001, 0b0000, 0b0011, 0b000>; def : ROSysReg<"TRCIDR8", 0b10, 0b001, 0b0000, 0b0000, 0b110>; def : ROSysReg<"TRCIDR9", 0b10, 0b001, 0b0000, 0b0001, 0b110>; def : ROSysReg<"TRCIDR10", 0b10, 0b001, 0b0000, 0b0010, 0b110>; def : ROSysReg<"TRCIDR11", 0b10, 0b001, 0b0000, 0b0011, 0b110>; def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>; def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>; def : ROSysReg<"TRCIDR0", 0b10, 0b001, 0b0000, 0b1000, 0b111>; def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>; def : ROSysReg<"TRCIDR2", 0b10, 0b001, 0b0000, 0b1010, 0b111>; def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>; def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>; def : ROSysReg<"TRCIDR5", 0b10, 0b001, 0b0000, 0b1101, 0b111>; def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>; def : ROSysReg<"TRCOSLSR", 0b10, 0b001, 0b0001, 0b0001, 0b100>; def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>; def : ROSysReg<"TRCDEVAFF0", 0b10, 0b001, 0b0111, 0b1010, 0b110>; def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>; def : ROSysReg<"TRCLSR", 0b10, 0b001, 0b0111, 0b1101, 0b110>; def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>; def : ROSysReg<"TRCDEVID", 0b10, 0b001, 0b0111, 0b0010, 0b111>; def : ROSysReg<"TRCDEVTYPE", 0b10, 0b001, 0b0111, 0b0011, 0b111>; def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>; def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>; def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>; def : ROSysReg<"TRCPIDR7", 0b10, 0b001, 0b0111, 0b0111, 0b111>; def : ROSysReg<"TRCPIDR0", 0b10, 0b001, 0b0111, 0b1000, 0b111>; def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>; def : ROSysReg<"TRCPIDR2", 0b10, 0b001, 0b0111, 0b1010, 0b111>; def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>; def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>; def : ROSysReg<"TRCCIDR1", 0b10, 0b001, 0b0111, 0b1101, 0b111>; def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>; // GICv3 registers // Op0 Op1 CRn CRm Op2 def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>; def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>; def : ROSysReg<"ICC_HPPIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b010>; def : ROSysReg<"ICC_HPPIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b010>; def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>; def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; // SVE control registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureSVE} }] in { def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; } // v8.1a "Limited Ordering Regions" extension-specific system register // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_1aOps} }] in def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; // v8.2a "RAS extension" registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureRAS} }] in { def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>; def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>; } //===---------------------- // Write-only regs //===---------------------- // Op0 Op1 CRn CRm Op2 def : WOSysReg<"DBGDTRTX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>; def : WOSysReg<"OSLAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b100>; def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>; // Trace Registers // Op0 Op1 CRn CRm Op2 def : WOSysReg<"TRCOSLAR", 0b10, 0b001, 0b0001, 0b0000, 0b100>; def : WOSysReg<"TRCLAR", 0b10, 0b001, 0b0111, 0b1100, 0b110>; // GICv3 registers // Op0 Op1 CRn CRm Op2 def : WOSysReg<"ICC_EOIR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b001>; def : WOSysReg<"ICC_EOIR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b001>; def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>; def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>; def : WOSysReg<"ICC_ASGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b110>; def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>; //===---------------------- // Read-write regs //===---------------------- // Op0 Op1 CRn CRm Op2 def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; def : RWSysReg<"MDCCINT_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b000>; def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>; def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; def : RWSysReg<"DBGBVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b100>; def : RWSysReg<"DBGBVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b100>; def : RWSysReg<"DBGBVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b100>; def : RWSysReg<"DBGBVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b100>; def : RWSysReg<"DBGBVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b100>; def : RWSysReg<"DBGBVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b100>; def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>; def : RWSysReg<"DBGBVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b100>; def : RWSysReg<"DBGBVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b100>; def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>; def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>; def : RWSysReg<"DBGBVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b100>; def : RWSysReg<"DBGBVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b100>; def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>; def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>; def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>; def : RWSysReg<"DBGBCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b101>; def : RWSysReg<"DBGBCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b101>; def : RWSysReg<"DBGBCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b101>; def : RWSysReg<"DBGBCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b101>; def : RWSysReg<"DBGBCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b101>; def : RWSysReg<"DBGBCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b101>; def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>; def : RWSysReg<"DBGBCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b101>; def : RWSysReg<"DBGBCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b101>; def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>; def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>; def : RWSysReg<"DBGBCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b101>; def : RWSysReg<"DBGBCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b101>; def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>; def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>; def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>; def : RWSysReg<"DBGWVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b110>; def : RWSysReg<"DBGWVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b110>; def : RWSysReg<"DBGWVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b110>; def : RWSysReg<"DBGWVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b110>; def : RWSysReg<"DBGWVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b110>; def : RWSysReg<"DBGWVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b110>; def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>; def : RWSysReg<"DBGWVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b110>; def : RWSysReg<"DBGWVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b110>; def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>; def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>; def : RWSysReg<"DBGWVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b110>; def : RWSysReg<"DBGWVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b110>; def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>; def : RWSysReg<"DBGWVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b110>; def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>; def : RWSysReg<"DBGWCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b111>; def : RWSysReg<"DBGWCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b111>; def : RWSysReg<"DBGWCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b111>; def : RWSysReg<"DBGWCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b111>; def : RWSysReg<"DBGWCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b111>; def : RWSysReg<"DBGWCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b111>; def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>; def : RWSysReg<"DBGWCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b111>; def : RWSysReg<"DBGWCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b111>; def : RWSysReg<"DBGWCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b111>; def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>; def : RWSysReg<"DBGWCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b111>; def : RWSysReg<"DBGWCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b111>; def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>; def : RWSysReg<"DBGWCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b111>; def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>; def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; def : RWSysReg<"DBGCLAIMSET_EL1", 0b10, 0b000, 0b0111, 0b1000, 0b110>; def : RWSysReg<"DBGCLAIMCLR_EL1", 0b10, 0b000, 0b0111, 0b1001, 0b110>; def : RWSysReg<"CSSELR_EL1", 0b11, 0b010, 0b0000, 0b0000, 0b000>; def : RWSysReg<"VPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b000>; def : RWSysReg<"VMPIDR_EL2", 0b11, 0b100, 0b0000, 0b0000, 0b101>; def : RWSysReg<"CPACR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b010>; def : RWSysReg<"SCTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b000>; def : RWSysReg<"SCTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b000>; def : RWSysReg<"SCTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b000>; def : RWSysReg<"ACTLR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b001>; def : RWSysReg<"ACTLR_EL2", 0b11, 0b100, 0b0001, 0b0000, 0b001>; def : RWSysReg<"ACTLR_EL3", 0b11, 0b110, 0b0001, 0b0000, 0b001>; def : RWSysReg<"HCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b000>; def : RWSysReg<"SCR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b000>; def : RWSysReg<"MDCR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b001>; def : RWSysReg<"SDER32_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b001>; def : RWSysReg<"CPTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b010>; def : RWSysReg<"CPTR_EL3", 0b11, 0b110, 0b0001, 0b0001, 0b010>; def : RWSysReg<"HSTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b011>; def : RWSysReg<"HACR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b111>; def : RWSysReg<"MDCR_EL3", 0b11, 0b110, 0b0001, 0b0011, 0b001>; def : RWSysReg<"TTBR0_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b000>; def : RWSysReg<"TTBR0_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b000>; def : RWSysReg<"TTBR0_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b000>; def : RWSysReg<"TTBR1_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b001>; def : RWSysReg<"TCR_EL1", 0b11, 0b000, 0b0010, 0b0000, 0b010>; def : RWSysReg<"TCR_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b010>; def : RWSysReg<"TCR_EL3", 0b11, 0b110, 0b0010, 0b0000, 0b010>; def : RWSysReg<"VTTBR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b000>; def : RWSysReg<"VTCR_EL2", 0b11, 0b100, 0b0010, 0b0001, 0b010>; def : RWSysReg<"DACR32_EL2", 0b11, 0b100, 0b0011, 0b0000, 0b000>; def : RWSysReg<"SPSR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b000>; def : RWSysReg<"SPSR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b000>; def : RWSysReg<"SPSR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b000>; def : RWSysReg<"ELR_EL1", 0b11, 0b000, 0b0100, 0b0000, 0b001>; def : RWSysReg<"ELR_EL2", 0b11, 0b100, 0b0100, 0b0000, 0b001>; def : RWSysReg<"ELR_EL3", 0b11, 0b110, 0b0100, 0b0000, 0b001>; def : RWSysReg<"SP_EL0", 0b11, 0b000, 0b0100, 0b0001, 0b000>; def : RWSysReg<"SP_EL1", 0b11, 0b100, 0b0100, 0b0001, 0b000>; def : RWSysReg<"SP_EL2", 0b11, 0b110, 0b0100, 0b0001, 0b000>; def : RWSysReg<"SPSel", 0b11, 0b000, 0b0100, 0b0010, 0b000>; def : RWSysReg<"NZCV", 0b11, 0b011, 0b0100, 0b0010, 0b000>; def : RWSysReg<"DAIF", 0b11, 0b011, 0b0100, 0b0010, 0b001>; def : RWSysReg<"CurrentEL", 0b11, 0b000, 0b0100, 0b0010, 0b010>; def : RWSysReg<"SPSR_irq", 0b11, 0b100, 0b0100, 0b0011, 0b000>; def : RWSysReg<"SPSR_abt", 0b11, 0b100, 0b0100, 0b0011, 0b001>; def : RWSysReg<"SPSR_und", 0b11, 0b100, 0b0100, 0b0011, 0b010>; def : RWSysReg<"SPSR_fiq", 0b11, 0b100, 0b0100, 0b0011, 0b011>; def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>; def : RWSysReg<"FPSR", 0b11, 0b011, 0b0100, 0b0100, 0b001>; def : RWSysReg<"DSPSR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b000>; def : RWSysReg<"DLR_EL0", 0b11, 0b011, 0b0100, 0b0101, 0b001>; def : RWSysReg<"IFSR32_EL2", 0b11, 0b100, 0b0101, 0b0000, 0b001>; def : RWSysReg<"AFSR0_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b000>; def : RWSysReg<"AFSR0_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b000>; def : RWSysReg<"AFSR0_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b000>; def : RWSysReg<"AFSR1_EL1", 0b11, 0b000, 0b0101, 0b0001, 0b001>; def : RWSysReg<"AFSR1_EL2", 0b11, 0b100, 0b0101, 0b0001, 0b001>; def : RWSysReg<"AFSR1_EL3", 0b11, 0b110, 0b0101, 0b0001, 0b001>; def : RWSysReg<"ESR_EL1", 0b11, 0b000, 0b0101, 0b0010, 0b000>; def : RWSysReg<"ESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b000>; def : RWSysReg<"ESR_EL3", 0b11, 0b110, 0b0101, 0b0010, 0b000>; def : RWSysReg<"FPEXC32_EL2", 0b11, 0b100, 0b0101, 0b0011, 0b000>; def : RWSysReg<"FAR_EL1", 0b11, 0b000, 0b0110, 0b0000, 0b000>; def : RWSysReg<"FAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b000>; def : RWSysReg<"FAR_EL3", 0b11, 0b110, 0b0110, 0b0000, 0b000>; def : RWSysReg<"HPFAR_EL2", 0b11, 0b100, 0b0110, 0b0000, 0b100>; def : RWSysReg<"PAR_EL1", 0b11, 0b000, 0b0111, 0b0100, 0b000>; def : RWSysReg<"PMCR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b000>; def : RWSysReg<"PMCNTENSET_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b001>; def : RWSysReg<"PMCNTENCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b010>; def : RWSysReg<"PMOVSCLR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b011>; def : RWSysReg<"PMSELR_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b101>; def : RWSysReg<"PMCCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b000>; def : RWSysReg<"PMXEVTYPER_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b001>; def : RWSysReg<"PMXEVCNTR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b010>; def : RWSysReg<"PMUSERENR_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b000>; def : RWSysReg<"PMINTENSET_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b001>; def : RWSysReg<"PMINTENCLR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b010>; def : RWSysReg<"PMOVSSET_EL0", 0b11, 0b011, 0b1001, 0b1110, 0b011>; def : RWSysReg<"MAIR_EL1", 0b11, 0b000, 0b1010, 0b0010, 0b000>; def : RWSysReg<"MAIR_EL2", 0b11, 0b100, 0b1010, 0b0010, 0b000>; def : RWSysReg<"MAIR_EL3", 0b11, 0b110, 0b1010, 0b0010, 0b000>; def : RWSysReg<"AMAIR_EL1", 0b11, 0b000, 0b1010, 0b0011, 0b000>; def : RWSysReg<"AMAIR_EL2", 0b11, 0b100, 0b1010, 0b0011, 0b000>; def : RWSysReg<"AMAIR_EL3", 0b11, 0b110, 0b1010, 0b0011, 0b000>; def : RWSysReg<"VBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b000>; def : RWSysReg<"VBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b000>; def : RWSysReg<"VBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b000>; def : RWSysReg<"RMR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b010>; def : RWSysReg<"RMR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b010>; def : RWSysReg<"RMR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b010>; def : RWSysReg<"CONTEXTIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b001>; def : RWSysReg<"TPIDR_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b010>; def : RWSysReg<"TPIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b010>; def : RWSysReg<"TPIDR_EL3", 0b11, 0b110, 0b1101, 0b0000, 0b010>; def : RWSysReg<"TPIDRRO_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b011>; def : RWSysReg<"TPIDR_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b100>; def : RWSysReg<"CNTFRQ_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b000>; def : RWSysReg<"CNTVOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b011>; def : RWSysReg<"CNTKCTL_EL1", 0b11, 0b000, 0b1110, 0b0001, 0b000>; def : RWSysReg<"CNTHCTL_EL2", 0b11, 0b100, 0b1110, 0b0001, 0b000>; def : RWSysReg<"CNTP_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b000>; def : RWSysReg<"CNTHP_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b000>; def : RWSysReg<"CNTPS_TVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b000>; def : RWSysReg<"CNTP_CTL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b001>; def : RWSysReg<"CNTHP_CTL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b001>; def : RWSysReg<"CNTPS_CTL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b001>; def : RWSysReg<"CNTP_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0010, 0b010>; def : RWSysReg<"CNTHP_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0010, 0b010>; def : RWSysReg<"CNTPS_CVAL_EL1", 0b11, 0b111, 0b1110, 0b0010, 0b010>; def : RWSysReg<"CNTV_TVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b000>; def : RWSysReg<"CNTV_CTL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b001>; def : RWSysReg<"CNTV_CVAL_EL0", 0b11, 0b011, 0b1110, 0b0011, 0b010>; def : RWSysReg<"PMEVCNTR0_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b000>; def : RWSysReg<"PMEVCNTR1_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b001>; def : RWSysReg<"PMEVCNTR2_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b010>; def : RWSysReg<"PMEVCNTR3_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b011>; def : RWSysReg<"PMEVCNTR4_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b100>; def : RWSysReg<"PMEVCNTR5_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b101>; def : RWSysReg<"PMEVCNTR6_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b110>; def : RWSysReg<"PMEVCNTR7_EL0", 0b11, 0b011, 0b1110, 0b1000, 0b111>; def : RWSysReg<"PMEVCNTR8_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b000>; def : RWSysReg<"PMEVCNTR9_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b001>; def : RWSysReg<"PMEVCNTR10_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b010>; def : RWSysReg<"PMEVCNTR11_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b011>; def : RWSysReg<"PMEVCNTR12_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b100>; def : RWSysReg<"PMEVCNTR13_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b101>; def : RWSysReg<"PMEVCNTR14_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b110>; def : RWSysReg<"PMEVCNTR15_EL0", 0b11, 0b011, 0b1110, 0b1001, 0b111>; def : RWSysReg<"PMEVCNTR16_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b000>; def : RWSysReg<"PMEVCNTR17_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b001>; def : RWSysReg<"PMEVCNTR18_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b010>; def : RWSysReg<"PMEVCNTR19_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b011>; def : RWSysReg<"PMEVCNTR20_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b100>; def : RWSysReg<"PMEVCNTR21_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b101>; def : RWSysReg<"PMEVCNTR22_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b110>; def : RWSysReg<"PMEVCNTR23_EL0", 0b11, 0b011, 0b1110, 0b1010, 0b111>; def : RWSysReg<"PMEVCNTR24_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b000>; def : RWSysReg<"PMEVCNTR25_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b001>; def : RWSysReg<"PMEVCNTR26_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b010>; def : RWSysReg<"PMEVCNTR27_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b011>; def : RWSysReg<"PMEVCNTR28_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b100>; def : RWSysReg<"PMEVCNTR29_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b101>; def : RWSysReg<"PMEVCNTR30_EL0", 0b11, 0b011, 0b1110, 0b1011, 0b110>; def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>; def : RWSysReg<"PMEVTYPER0_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b000>; def : RWSysReg<"PMEVTYPER1_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b001>; def : RWSysReg<"PMEVTYPER2_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b010>; def : RWSysReg<"PMEVTYPER3_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b011>; def : RWSysReg<"PMEVTYPER4_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b100>; def : RWSysReg<"PMEVTYPER5_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b101>; def : RWSysReg<"PMEVTYPER6_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b110>; def : RWSysReg<"PMEVTYPER7_EL0", 0b11, 0b011, 0b1110, 0b1100, 0b111>; def : RWSysReg<"PMEVTYPER8_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b000>; def : RWSysReg<"PMEVTYPER9_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b001>; def : RWSysReg<"PMEVTYPER10_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b010>; def : RWSysReg<"PMEVTYPER11_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b011>; def : RWSysReg<"PMEVTYPER12_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b100>; def : RWSysReg<"PMEVTYPER13_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b101>; def : RWSysReg<"PMEVTYPER14_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b110>; def : RWSysReg<"PMEVTYPER15_EL0", 0b11, 0b011, 0b1110, 0b1101, 0b111>; def : RWSysReg<"PMEVTYPER16_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b000>; def : RWSysReg<"PMEVTYPER17_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b001>; def : RWSysReg<"PMEVTYPER18_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b010>; def : RWSysReg<"PMEVTYPER19_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b011>; def : RWSysReg<"PMEVTYPER20_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b100>; def : RWSysReg<"PMEVTYPER21_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b101>; def : RWSysReg<"PMEVTYPER22_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b110>; def : RWSysReg<"PMEVTYPER23_EL0", 0b11, 0b011, 0b1110, 0b1110, 0b111>; def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>; def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>; def : RWSysReg<"PMEVTYPER26_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b010>; def : RWSysReg<"PMEVTYPER27_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b011>; def : RWSysReg<"PMEVTYPER28_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b100>; def : RWSysReg<"PMEVTYPER29_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b101>; def : RWSysReg<"PMEVTYPER30_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b110>; // Trace registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"TRCPRGCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b000>; def : RWSysReg<"TRCPROCSELR", 0b10, 0b001, 0b0000, 0b0010, 0b000>; def : RWSysReg<"TRCCONFIGR", 0b10, 0b001, 0b0000, 0b0100, 0b000>; def : RWSysReg<"TRCAUXCTLR", 0b10, 0b001, 0b0000, 0b0110, 0b000>; def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>; def : RWSysReg<"TRCEVENTCTL1R", 0b10, 0b001, 0b0000, 0b1001, 0b000>; def : RWSysReg<"TRCSTALLCTLR", 0b10, 0b001, 0b0000, 0b1011, 0b000>; def : RWSysReg<"TRCTSCTLR", 0b10, 0b001, 0b0000, 0b1100, 0b000>; def : RWSysReg<"TRCSYNCPR", 0b10, 0b001, 0b0000, 0b1101, 0b000>; def : RWSysReg<"TRCCCCTLR", 0b10, 0b001, 0b0000, 0b1110, 0b000>; def : RWSysReg<"TRCBBCTLR", 0b10, 0b001, 0b0000, 0b1111, 0b000>; def : RWSysReg<"TRCTRACEIDR", 0b10, 0b001, 0b0000, 0b0000, 0b001>; def : RWSysReg<"TRCQCTLR", 0b10, 0b001, 0b0000, 0b0001, 0b001>; def : RWSysReg<"TRCVICTLR", 0b10, 0b001, 0b0000, 0b0000, 0b010>; def : RWSysReg<"TRCVIIECTLR", 0b10, 0b001, 0b0000, 0b0001, 0b010>; def : RWSysReg<"TRCVISSCTLR", 0b10, 0b001, 0b0000, 0b0010, 0b010>; def : RWSysReg<"TRCVIPCSSCTLR", 0b10, 0b001, 0b0000, 0b0011, 0b010>; def : RWSysReg<"TRCVDCTLR", 0b10, 0b001, 0b0000, 0b1000, 0b010>; def : RWSysReg<"TRCVDSACCTLR", 0b10, 0b001, 0b0000, 0b1001, 0b010>; def : RWSysReg<"TRCVDARCCTLR", 0b10, 0b001, 0b0000, 0b1010, 0b010>; def : RWSysReg<"TRCSEQEVR0", 0b10, 0b001, 0b0000, 0b0000, 0b100>; def : RWSysReg<"TRCSEQEVR1", 0b10, 0b001, 0b0000, 0b0001, 0b100>; def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; def : RWSysReg<"TRCCNTRLDVR3", 0b10, 0b001, 0b0000, 0b0011, 0b101>; def : RWSysReg<"TRCCNTCTLR0", 0b10, 0b001, 0b0000, 0b0100, 0b101>; def : RWSysReg<"TRCCNTCTLR1", 0b10, 0b001, 0b0000, 0b0101, 0b101>; def : RWSysReg<"TRCCNTCTLR2", 0b10, 0b001, 0b0000, 0b0110, 0b101>; def : RWSysReg<"TRCCNTCTLR3", 0b10, 0b001, 0b0000, 0b0111, 0b101>; def : RWSysReg<"TRCCNTVR0", 0b10, 0b001, 0b0000, 0b1000, 0b101>; def : RWSysReg<"TRCCNTVR1", 0b10, 0b001, 0b0000, 0b1001, 0b101>; def : RWSysReg<"TRCCNTVR2", 0b10, 0b001, 0b0000, 0b1010, 0b101>; def : RWSysReg<"TRCCNTVR3", 0b10, 0b001, 0b0000, 0b1011, 0b101>; def : RWSysReg<"TRCIMSPEC0", 0b10, 0b001, 0b0000, 0b0000, 0b111>; def : RWSysReg<"TRCIMSPEC1", 0b10, 0b001, 0b0000, 0b0001, 0b111>; def : RWSysReg<"TRCIMSPEC2", 0b10, 0b001, 0b0000, 0b0010, 0b111>; def : RWSysReg<"TRCIMSPEC3", 0b10, 0b001, 0b0000, 0b0011, 0b111>; def : RWSysReg<"TRCIMSPEC4", 0b10, 0b001, 0b0000, 0b0100, 0b111>; def : RWSysReg<"TRCIMSPEC5", 0b10, 0b001, 0b0000, 0b0101, 0b111>; def : RWSysReg<"TRCIMSPEC6", 0b10, 0b001, 0b0000, 0b0110, 0b111>; def : RWSysReg<"TRCIMSPEC7", 0b10, 0b001, 0b0000, 0b0111, 0b111>; def : RWSysReg<"TRCRSCTLR2", 0b10, 0b001, 0b0001, 0b0010, 0b000>; def : RWSysReg<"TRCRSCTLR3", 0b10, 0b001, 0b0001, 0b0011, 0b000>; def : RWSysReg<"TRCRSCTLR4", 0b10, 0b001, 0b0001, 0b0100, 0b000>; def : RWSysReg<"TRCRSCTLR5", 0b10, 0b001, 0b0001, 0b0101, 0b000>; def : RWSysReg<"TRCRSCTLR6", 0b10, 0b001, 0b0001, 0b0110, 0b000>; def : RWSysReg<"TRCRSCTLR7", 0b10, 0b001, 0b0001, 0b0111, 0b000>; def : RWSysReg<"TRCRSCTLR8", 0b10, 0b001, 0b0001, 0b1000, 0b000>; def : RWSysReg<"TRCRSCTLR9", 0b10, 0b001, 0b0001, 0b1001, 0b000>; def : RWSysReg<"TRCRSCTLR10", 0b10, 0b001, 0b0001, 0b1010, 0b000>; def : RWSysReg<"TRCRSCTLR11", 0b10, 0b001, 0b0001, 0b1011, 0b000>; def : RWSysReg<"TRCRSCTLR12", 0b10, 0b001, 0b0001, 0b1100, 0b000>; def : RWSysReg<"TRCRSCTLR13", 0b10, 0b001, 0b0001, 0b1101, 0b000>; def : RWSysReg<"TRCRSCTLR14", 0b10, 0b001, 0b0001, 0b1110, 0b000>; def : RWSysReg<"TRCRSCTLR15", 0b10, 0b001, 0b0001, 0b1111, 0b000>; def : RWSysReg<"TRCRSCTLR16", 0b10, 0b001, 0b0001, 0b0000, 0b001>; def : RWSysReg<"TRCRSCTLR17", 0b10, 0b001, 0b0001, 0b0001, 0b001>; def : RWSysReg<"TRCRSCTLR18", 0b10, 0b001, 0b0001, 0b0010, 0b001>; def : RWSysReg<"TRCRSCTLR19", 0b10, 0b001, 0b0001, 0b0011, 0b001>; def : RWSysReg<"TRCRSCTLR20", 0b10, 0b001, 0b0001, 0b0100, 0b001>; def : RWSysReg<"TRCRSCTLR21", 0b10, 0b001, 0b0001, 0b0101, 0b001>; def : RWSysReg<"TRCRSCTLR22", 0b10, 0b001, 0b0001, 0b0110, 0b001>; def : RWSysReg<"TRCRSCTLR23", 0b10, 0b001, 0b0001, 0b0111, 0b001>; def : RWSysReg<"TRCRSCTLR24", 0b10, 0b001, 0b0001, 0b1000, 0b001>; def : RWSysReg<"TRCRSCTLR25", 0b10, 0b001, 0b0001, 0b1001, 0b001>; def : RWSysReg<"TRCRSCTLR26", 0b10, 0b001, 0b0001, 0b1010, 0b001>; def : RWSysReg<"TRCRSCTLR27", 0b10, 0b001, 0b0001, 0b1011, 0b001>; def : RWSysReg<"TRCRSCTLR28", 0b10, 0b001, 0b0001, 0b1100, 0b001>; def : RWSysReg<"TRCRSCTLR29", 0b10, 0b001, 0b0001, 0b1101, 0b001>; def : RWSysReg<"TRCRSCTLR30", 0b10, 0b001, 0b0001, 0b1110, 0b001>; def : RWSysReg<"TRCRSCTLR31", 0b10, 0b001, 0b0001, 0b1111, 0b001>; def : RWSysReg<"TRCSSCCR0", 0b10, 0b001, 0b0001, 0b0000, 0b010>; def : RWSysReg<"TRCSSCCR1", 0b10, 0b001, 0b0001, 0b0001, 0b010>; def : RWSysReg<"TRCSSCCR2", 0b10, 0b001, 0b0001, 0b0010, 0b010>; def : RWSysReg<"TRCSSCCR3", 0b10, 0b001, 0b0001, 0b0011, 0b010>; def : RWSysReg<"TRCSSCCR4", 0b10, 0b001, 0b0001, 0b0100, 0b010>; def : RWSysReg<"TRCSSCCR5", 0b10, 0b001, 0b0001, 0b0101, 0b010>; def : RWSysReg<"TRCSSCCR6", 0b10, 0b001, 0b0001, 0b0110, 0b010>; def : RWSysReg<"TRCSSCCR7", 0b10, 0b001, 0b0001, 0b0111, 0b010>; def : RWSysReg<"TRCSSCSR0", 0b10, 0b001, 0b0001, 0b1000, 0b010>; def : RWSysReg<"TRCSSCSR1", 0b10, 0b001, 0b0001, 0b1001, 0b010>; def : RWSysReg<"TRCSSCSR2", 0b10, 0b001, 0b0001, 0b1010, 0b010>; def : RWSysReg<"TRCSSCSR3", 0b10, 0b001, 0b0001, 0b1011, 0b010>; def : RWSysReg<"TRCSSCSR4", 0b10, 0b001, 0b0001, 0b1100, 0b010>; def : RWSysReg<"TRCSSCSR5", 0b10, 0b001, 0b0001, 0b1101, 0b010>; def : RWSysReg<"TRCSSCSR6", 0b10, 0b001, 0b0001, 0b1110, 0b010>; def : RWSysReg<"TRCSSCSR7", 0b10, 0b001, 0b0001, 0b1111, 0b010>; def : RWSysReg<"TRCSSPCICR0", 0b10, 0b001, 0b0001, 0b0000, 0b011>; def : RWSysReg<"TRCSSPCICR1", 0b10, 0b001, 0b0001, 0b0001, 0b011>; def : RWSysReg<"TRCSSPCICR2", 0b10, 0b001, 0b0001, 0b0010, 0b011>; def : RWSysReg<"TRCSSPCICR3", 0b10, 0b001, 0b0001, 0b0011, 0b011>; def : RWSysReg<"TRCSSPCICR4", 0b10, 0b001, 0b0001, 0b0100, 0b011>; def : RWSysReg<"TRCSSPCICR5", 0b10, 0b001, 0b0001, 0b0101, 0b011>; def : RWSysReg<"TRCSSPCICR6", 0b10, 0b001, 0b0001, 0b0110, 0b011>; def : RWSysReg<"TRCSSPCICR7", 0b10, 0b001, 0b0001, 0b0111, 0b011>; def : RWSysReg<"TRCPDCR", 0b10, 0b001, 0b0001, 0b0100, 0b100>; def : RWSysReg<"TRCACVR0", 0b10, 0b001, 0b0010, 0b0000, 0b000>; def : RWSysReg<"TRCACVR1", 0b10, 0b001, 0b0010, 0b0010, 0b000>; def : RWSysReg<"TRCACVR2", 0b10, 0b001, 0b0010, 0b0100, 0b000>; def : RWSysReg<"TRCACVR3", 0b10, 0b001, 0b0010, 0b0110, 0b000>; def : RWSysReg<"TRCACVR4", 0b10, 0b001, 0b0010, 0b1000, 0b000>; def : RWSysReg<"TRCACVR5", 0b10, 0b001, 0b0010, 0b1010, 0b000>; def : RWSysReg<"TRCACVR6", 0b10, 0b001, 0b0010, 0b1100, 0b000>; def : RWSysReg<"TRCACVR7", 0b10, 0b001, 0b0010, 0b1110, 0b000>; def : RWSysReg<"TRCACVR8", 0b10, 0b001, 0b0010, 0b0000, 0b001>; def : RWSysReg<"TRCACVR9", 0b10, 0b001, 0b0010, 0b0010, 0b001>; def : RWSysReg<"TRCACVR10", 0b10, 0b001, 0b0010, 0b0100, 0b001>; def : RWSysReg<"TRCACVR11", 0b10, 0b001, 0b0010, 0b0110, 0b001>; def : RWSysReg<"TRCACVR12", 0b10, 0b001, 0b0010, 0b1000, 0b001>; def : RWSysReg<"TRCACVR13", 0b10, 0b001, 0b0010, 0b1010, 0b001>; def : RWSysReg<"TRCACVR14", 0b10, 0b001, 0b0010, 0b1100, 0b001>; def : RWSysReg<"TRCACVR15", 0b10, 0b001, 0b0010, 0b1110, 0b001>; def : RWSysReg<"TRCACATR0", 0b10, 0b001, 0b0010, 0b0000, 0b010>; def : RWSysReg<"TRCACATR1", 0b10, 0b001, 0b0010, 0b0010, 0b010>; def : RWSysReg<"TRCACATR2", 0b10, 0b001, 0b0010, 0b0100, 0b010>; def : RWSysReg<"TRCACATR3", 0b10, 0b001, 0b0010, 0b0110, 0b010>; def : RWSysReg<"TRCACATR4", 0b10, 0b001, 0b0010, 0b1000, 0b010>; def : RWSysReg<"TRCACATR5", 0b10, 0b001, 0b0010, 0b1010, 0b010>; def : RWSysReg<"TRCACATR6", 0b10, 0b001, 0b0010, 0b1100, 0b010>; def : RWSysReg<"TRCACATR7", 0b10, 0b001, 0b0010, 0b1110, 0b010>; def : RWSysReg<"TRCACATR8", 0b10, 0b001, 0b0010, 0b0000, 0b011>; def : RWSysReg<"TRCACATR9", 0b10, 0b001, 0b0010, 0b0010, 0b011>; def : RWSysReg<"TRCACATR10", 0b10, 0b001, 0b0010, 0b0100, 0b011>; def : RWSysReg<"TRCACATR11", 0b10, 0b001, 0b0010, 0b0110, 0b011>; def : RWSysReg<"TRCACATR12", 0b10, 0b001, 0b0010, 0b1000, 0b011>; def : RWSysReg<"TRCACATR13", 0b10, 0b001, 0b0010, 0b1010, 0b011>; def : RWSysReg<"TRCACATR14", 0b10, 0b001, 0b0010, 0b1100, 0b011>; def : RWSysReg<"TRCACATR15", 0b10, 0b001, 0b0010, 0b1110, 0b011>; def : RWSysReg<"TRCDVCVR0", 0b10, 0b001, 0b0010, 0b0000, 0b100>; def : RWSysReg<"TRCDVCVR1", 0b10, 0b001, 0b0010, 0b0100, 0b100>; def : RWSysReg<"TRCDVCVR2", 0b10, 0b001, 0b0010, 0b1000, 0b100>; def : RWSysReg<"TRCDVCVR3", 0b10, 0b001, 0b0010, 0b1100, 0b100>; def : RWSysReg<"TRCDVCVR4", 0b10, 0b001, 0b0010, 0b0000, 0b101>; def : RWSysReg<"TRCDVCVR5", 0b10, 0b001, 0b0010, 0b0100, 0b101>; def : RWSysReg<"TRCDVCVR6", 0b10, 0b001, 0b0010, 0b1000, 0b101>; def : RWSysReg<"TRCDVCVR7", 0b10, 0b001, 0b0010, 0b1100, 0b101>; def : RWSysReg<"TRCDVCMR0", 0b10, 0b001, 0b0010, 0b0000, 0b110>; def : RWSysReg<"TRCDVCMR1", 0b10, 0b001, 0b0010, 0b0100, 0b110>; def : RWSysReg<"TRCDVCMR2", 0b10, 0b001, 0b0010, 0b1000, 0b110>; def : RWSysReg<"TRCDVCMR3", 0b10, 0b001, 0b0010, 0b1100, 0b110>; def : RWSysReg<"TRCDVCMR4", 0b10, 0b001, 0b0010, 0b0000, 0b111>; def : RWSysReg<"TRCDVCMR5", 0b10, 0b001, 0b0010, 0b0100, 0b111>; def : RWSysReg<"TRCDVCMR6", 0b10, 0b001, 0b0010, 0b1000, 0b111>; def : RWSysReg<"TRCDVCMR7", 0b10, 0b001, 0b0010, 0b1100, 0b111>; def : RWSysReg<"TRCCIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b000>; def : RWSysReg<"TRCCIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b000>; def : RWSysReg<"TRCCIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b000>; def : RWSysReg<"TRCCIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b000>; def : RWSysReg<"TRCCIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b000>; def : RWSysReg<"TRCCIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b000>; def : RWSysReg<"TRCCIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b000>; def : RWSysReg<"TRCCIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b000>; def : RWSysReg<"TRCVMIDCVR0", 0b10, 0b001, 0b0011, 0b0000, 0b001>; def : RWSysReg<"TRCVMIDCVR1", 0b10, 0b001, 0b0011, 0b0010, 0b001>; def : RWSysReg<"TRCVMIDCVR2", 0b10, 0b001, 0b0011, 0b0100, 0b001>; def : RWSysReg<"TRCVMIDCVR3", 0b10, 0b001, 0b0011, 0b0110, 0b001>; def : RWSysReg<"TRCVMIDCVR4", 0b10, 0b001, 0b0011, 0b1000, 0b001>; def : RWSysReg<"TRCVMIDCVR5", 0b10, 0b001, 0b0011, 0b1010, 0b001>; def : RWSysReg<"TRCVMIDCVR6", 0b10, 0b001, 0b0011, 0b1100, 0b001>; def : RWSysReg<"TRCVMIDCVR7", 0b10, 0b001, 0b0011, 0b1110, 0b001>; def : RWSysReg<"TRCCIDCCTLR0", 0b10, 0b001, 0b0011, 0b0000, 0b010>; def : RWSysReg<"TRCCIDCCTLR1", 0b10, 0b001, 0b0011, 0b0001, 0b010>; def : RWSysReg<"TRCVMIDCCTLR0", 0b10, 0b001, 0b0011, 0b0010, 0b010>; def : RWSysReg<"TRCVMIDCCTLR1", 0b10, 0b001, 0b0011, 0b0011, 0b010>; def : RWSysReg<"TRCITCTRL", 0b10, 0b001, 0b0111, 0b0000, 0b100>; def : RWSysReg<"TRCCLAIMSET", 0b10, 0b001, 0b0111, 0b1000, 0b110>; def : RWSysReg<"TRCCLAIMCLR", 0b10, 0b001, 0b0111, 0b1001, 0b110>; // GICv3 registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"ICC_BPR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b011>; def : RWSysReg<"ICC_BPR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b011>; def : RWSysReg<"ICC_PMR_EL1", 0b11, 0b000, 0b0100, 0b0110, 0b000>; def : RWSysReg<"ICC_CTLR_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b100>; def : RWSysReg<"ICC_CTLR_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b100>; def : RWSysReg<"ICC_SRE_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b101>; def : RWSysReg<"ICC_SRE_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b101>; def : RWSysReg<"ICC_SRE_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b101>; def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>; def : RWSysReg<"ICC_IGRPEN1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b111>; def : RWSysReg<"ICC_IGRPEN1_EL3", 0b11, 0b110, 0b1100, 0b1100, 0b111>; def : RWSysReg<"ICC_SEIEN_EL1", 0b11, 0b000, 0b1100, 0b1101, 0b000>; def : RWSysReg<"ICC_AP0R0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b100>; def : RWSysReg<"ICC_AP0R1_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b101>; def : RWSysReg<"ICC_AP0R2_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b110>; def : RWSysReg<"ICC_AP0R3_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b111>; def : RWSysReg<"ICC_AP1R0_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b000>; def : RWSysReg<"ICC_AP1R1_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b001>; def : RWSysReg<"ICC_AP1R2_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b010>; def : RWSysReg<"ICC_AP1R3_EL1", 0b11, 0b000, 0b1100, 0b1001, 0b011>; def : RWSysReg<"ICH_AP0R0_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b000>; def : RWSysReg<"ICH_AP0R1_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b001>; def : RWSysReg<"ICH_AP0R2_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b010>; def : RWSysReg<"ICH_AP0R3_EL2", 0b11, 0b100, 0b1100, 0b1000, 0b011>; def : RWSysReg<"ICH_AP1R0_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b000>; def : RWSysReg<"ICH_AP1R1_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b001>; def : RWSysReg<"ICH_AP1R2_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b010>; def : RWSysReg<"ICH_AP1R3_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b011>; def : RWSysReg<"ICH_HCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b000>; def : RWSysReg<"ICH_MISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b010>; def : RWSysReg<"ICH_VMCR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b111>; def : RWSysReg<"ICH_VSEIR_EL2", 0b11, 0b100, 0b1100, 0b1001, 0b100>; def : RWSysReg<"ICH_LR0_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b000>; def : RWSysReg<"ICH_LR1_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b001>; def : RWSysReg<"ICH_LR2_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b010>; def : RWSysReg<"ICH_LR3_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b011>; def : RWSysReg<"ICH_LR4_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b100>; def : RWSysReg<"ICH_LR5_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b101>; def : RWSysReg<"ICH_LR6_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b110>; def : RWSysReg<"ICH_LR7_EL2", 0b11, 0b100, 0b1100, 0b1100, 0b111>; def : RWSysReg<"ICH_LR8_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b000>; def : RWSysReg<"ICH_LR9_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b001>; def : RWSysReg<"ICH_LR10_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b010>; def : RWSysReg<"ICH_LR11_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b011>; def : RWSysReg<"ICH_LR12_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b100>; def : RWSysReg<"ICH_LR13_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b101>; def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; // v8.1a "Privileged Access Never" extension-specific system registers let Requires = [{ {AArch64::HasV8_1aOps} }] in def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; // v8.1a "Limited Ordering Regions" extension-specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_1aOps} }] in { def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; } // v8.1a "Virtualization hos extensions" system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_1aOps} }] in { def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>; def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>; def : RWSysReg<"SCTLR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b000>; def : RWSysReg<"CPACR_EL12", 0b11, 0b101, 0b0001, 0b0000, 0b010>; def : RWSysReg<"TTBR0_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b000>; def : RWSysReg<"TTBR1_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b001>; def : RWSysReg<"TCR_EL12", 0b11, 0b101, 0b0010, 0b0000, 0b010>; def : RWSysReg<"AFSR0_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b000>; def : RWSysReg<"AFSR1_EL12", 0b11, 0b101, 0b0101, 0b0001, 0b001>; def : RWSysReg<"ESR_EL12", 0b11, 0b101, 0b0101, 0b0010, 0b000>; def : RWSysReg<"FAR_EL12", 0b11, 0b101, 0b0110, 0b0000, 0b000>; def : RWSysReg<"MAIR_EL12", 0b11, 0b101, 0b1010, 0b0010, 0b000>; def : RWSysReg<"AMAIR_EL12", 0b11, 0b101, 0b1010, 0b0011, 0b000>; def : RWSysReg<"VBAR_EL12", 0b11, 0b101, 0b1100, 0b0000, 0b000>; def : RWSysReg<"CONTEXTIDR_EL12", 0b11, 0b101, 0b1101, 0b0000, 0b001>; def : RWSysReg<"CNTKCTL_EL12", 0b11, 0b101, 0b1110, 0b0001, 0b000>; def : RWSysReg<"CNTP_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b000>; def : RWSysReg<"CNTP_CTL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b001>; def : RWSysReg<"CNTP_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0010, 0b010>; def : RWSysReg<"CNTV_TVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b000>; def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>; def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>; def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>; def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; } // v8.2a registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_2aOps} }] in def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; // v8.2a "Statistical Profiling extension" registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureSPE} }] in { def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>; def : RWSysReg<"PMBPTR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b001>; def : RWSysReg<"PMBSR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b011>; def : RWSysReg<"PMBIDR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b111>; def : RWSysReg<"PMSCR_EL2", 0b11, 0b100, 0b1001, 0b1001, 0b000>; def : RWSysReg<"PMSCR_EL12", 0b11, 0b101, 0b1001, 0b1001, 0b000>; def : RWSysReg<"PMSCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b000>; def : RWSysReg<"PMSICR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b010>; def : RWSysReg<"PMSIRR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b011>; def : RWSysReg<"PMSFCR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b100>; def : RWSysReg<"PMSEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b101>; def : RWSysReg<"PMSLATFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b110>; def : RWSysReg<"PMSIDR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b111>; } // v8.2a "RAS extension" registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureRAS} }] in { def : RWSysReg<"ERRSELR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b001>; def : RWSysReg<"ERXCTLR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b001>; def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>; def : RWSysReg<"ERXADDR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b011>; def : RWSysReg<"ERXMISC0_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b000>; def : RWSysReg<"ERXMISC1_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b001>; def : RWSysReg<"DISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b001>; def : RWSysReg<"VDISR_EL2", 0b11, 0b100, 0b1100, 0b0001, 0b001>; def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; } // v8.3a "Pointer authentication extension" registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_3aOps} }] in { def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>; def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>; def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>; def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>; def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>; def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; } let Requires = [{ {AArch64::HasV8_4aOps} }] in { // v8.4a "Virtualization secure second stage translation" registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000>; // v8.4a "Virtualization timer" registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>; def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>; def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>; def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>; def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>; def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; // v8.4a "Virtualization debug state" registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; // v8.4a RAS registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>; def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; // v8.4a MPAM registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>; def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>; def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>; def : RWSysReg<"MPAM3_EL3", 0b11, 0b110, 0b1010, 0b0101, 0b000>; def : RWSysReg<"MPAM1_EL12", 0b11, 0b101, 0b1010, 0b0101, 0b000>; def : RWSysReg<"MPAMHCR_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b000>; def : RWSysReg<"MPAMVPMV_EL2", 0b11, 0b100, 0b1010, 0b0100, 0b001>; def : RWSysReg<"MPAMVPM0_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b000>; def : RWSysReg<"MPAMVPM1_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b001>; def : RWSysReg<"MPAMVPM2_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b010>; def : RWSysReg<"MPAMVPM3_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b011>; def : RWSysReg<"MPAMVPM4_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b100>; def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>; def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>; def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>; def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>; // v8.4a Activitiy monitor registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>; def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>; def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>; def : RWSysReg<"AMUSERENR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b011>; def : RWSysReg<"AMCNTENCLR0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b100>; def : RWSysReg<"AMCNTENSET0_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b101>; def : RWSysReg<"AMEVCNTR00_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b000>; def : RWSysReg<"AMEVCNTR01_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b001>; def : RWSysReg<"AMEVCNTR02_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b010>; def : RWSysReg<"AMEVCNTR03_EL0", 0b11, 0b011, 0b1101, 0b0100, 0b011>; def : ROSysReg<"AMEVTYPER00_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b000>; def : ROSysReg<"AMEVTYPER01_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b001>; def : ROSysReg<"AMEVTYPER02_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b010>; def : ROSysReg<"AMEVTYPER03_EL0", 0b11, 0b011, 0b1101, 0b0110, 0b011>; def : RWSysReg<"AMCNTENCLR1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b000>; def : RWSysReg<"AMCNTENSET1_EL0", 0b11, 0b011, 0b1101, 0b0011, 0b001>; def : RWSysReg<"AMEVCNTR10_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b000>; def : RWSysReg<"AMEVCNTR11_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b001>; def : RWSysReg<"AMEVCNTR12_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b010>; def : RWSysReg<"AMEVCNTR13_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b011>; def : RWSysReg<"AMEVCNTR14_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b100>; def : RWSysReg<"AMEVCNTR15_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b101>; def : RWSysReg<"AMEVCNTR16_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b110>; def : RWSysReg<"AMEVCNTR17_EL0", 0b11, 0b011, 0b1101, 0b1100, 0b111>; def : RWSysReg<"AMEVCNTR18_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b000>; def : RWSysReg<"AMEVCNTR19_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b001>; def : RWSysReg<"AMEVCNTR110_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b010>; def : RWSysReg<"AMEVCNTR111_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b011>; def : RWSysReg<"AMEVCNTR112_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b100>; def : RWSysReg<"AMEVCNTR113_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b101>; def : RWSysReg<"AMEVCNTR114_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b110>; def : RWSysReg<"AMEVCNTR115_EL0", 0b11, 0b011, 0b1101, 0b1101, 0b111>; def : RWSysReg<"AMEVTYPER10_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b000>; def : RWSysReg<"AMEVTYPER11_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b001>; def : RWSysReg<"AMEVTYPER12_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b010>; def : RWSysReg<"AMEVTYPER13_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b011>; def : RWSysReg<"AMEVTYPER14_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b100>; def : RWSysReg<"AMEVTYPER15_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b101>; def : RWSysReg<"AMEVTYPER16_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b110>; def : RWSysReg<"AMEVTYPER17_EL0", 0b11, 0b011, 0b1101, 0b1110, 0b111>; def : RWSysReg<"AMEVTYPER18_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b000>; def : RWSysReg<"AMEVTYPER19_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b001>; def : RWSysReg<"AMEVTYPER110_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b010>; def : RWSysReg<"AMEVTYPER111_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b011>; def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>; def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>; def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>; def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; // v8.4a Trace Extension registers // // Please note that the 8.4 spec also defines these registers: // TRCIDR1, ID_DFR0_EL1, ID_AA64DFR0_EL1, MDSCR_EL1, MDCR_EL2, and MDCR_EL3, // but they are already defined above. // // Op0 Op1 CRn CRm Op2 def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>; def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>; def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>; // v8.4a Timining insensitivity of data processing instructions // Op0 Op1 CRn CRm Op2 def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>; // v8.4a Enhanced Support for Nested Virtualization // Op0 Op1 CRn CRm Op2 def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; } // HasV8_4aOps // SVE control registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureSVE} }] in { def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; } // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcCyclone} }] in def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/AArch64/SVEInstrFormats.td000064400000000000000000004377330072674642500256650ustar 00000000000000//=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions. // //===----------------------------------------------------------------------===// def SVEPatternOperand : AsmOperandClass { let Name = "SVEPattern"; let ParserMethod = "tryParseSVEPattern"; let PredicateMethod = "isSVEPattern"; let RenderMethod = "addImmOperands"; let DiagnosticType = "InvalidSVEPattern"; } def sve_pred_enum : Operand, ImmLeaf { let PrintMethod = "printSVEPattern"; let ParserMatchClass = SVEPatternOperand; } def SVEPrefetchOperand : AsmOperandClass { let Name = "SVEPrefetch"; let ParserMethod = "tryParsePrefetch"; let PredicateMethod = "isPrefetch"; let RenderMethod = "addPrefetchOperands"; } def sve_prfop : Operand, ImmLeaf { let PrintMethod = "printPrefetchOp"; let ParserMatchClass = SVEPrefetchOperand; } class SVELogicalImmOperand : AsmOperandClass { let Name = "SVELogicalImm" # Width; let DiagnosticType = "LogicalSecondSource"; let PredicateMethod = "isLogicalImm"; let RenderMethod = "addLogicalImmOperands"; } def sve_logical_imm8 : Operand { let ParserMatchClass = SVELogicalImmOperand<8>; let PrintMethod = "printLogicalImm"; let MCOperandPredicate = [{ if (!MCOp.isImm()) return false; int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); return AArch64_AM::isSVEMaskOfIdenticalElements(Val); }]; } def sve_logical_imm16 : Operand { let ParserMatchClass = SVELogicalImmOperand<16>; let PrintMethod = "printLogicalImm"; let MCOperandPredicate = [{ if (!MCOp.isImm()) return false; int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); return AArch64_AM::isSVEMaskOfIdenticalElements(Val); }]; } def sve_logical_imm32 : Operand { let ParserMatchClass = SVELogicalImmOperand<32>; let PrintMethod = "printLogicalImm"; let MCOperandPredicate = [{ if (!MCOp.isImm()) return false; int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); return AArch64_AM::isSVEMaskOfIdenticalElements(Val); }]; } class SVEPreferredLogicalImmOperand : AsmOperandClass { let Name = "SVEPreferredLogicalImm" # Width; let PredicateMethod = "isSVEPreferredLogicalImm"; let RenderMethod = "addLogicalImmOperands"; } def sve_preferred_logical_imm16 : Operand { let ParserMatchClass = SVEPreferredLogicalImmOperand<16>; let PrintMethod = "printSVELogicalImm"; let MCOperandPredicate = [{ if (!MCOp.isImm()) return false; int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); return AArch64_AM::isSVEMaskOfIdenticalElements(Val) && AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); }]; } def sve_preferred_logical_imm32 : Operand { let ParserMatchClass = SVEPreferredLogicalImmOperand<32>; let PrintMethod = "printSVELogicalImm"; let MCOperandPredicate = [{ if (!MCOp.isImm()) return false; int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); return AArch64_AM::isSVEMaskOfIdenticalElements(Val) && AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); }]; } def sve_preferred_logical_imm64 : Operand { let ParserMatchClass = SVEPreferredLogicalImmOperand<64>; let PrintMethod = "printSVELogicalImm"; let MCOperandPredicate = [{ if (!MCOp.isImm()) return false; int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); return AArch64_AM::isSVEMaskOfIdenticalElements(Val) && AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); }]; } class SVELogicalImmNotOperand : AsmOperandClass { let Name = "SVELogicalImm" # Width # "Not"; let DiagnosticType = "LogicalSecondSource"; let PredicateMethod = "isLogicalImm"; let RenderMethod = "addLogicalImmNotOperands"; } def sve_logical_imm8_not : Operand { let ParserMatchClass = SVELogicalImmNotOperand<8>; } def sve_logical_imm16_not : Operand { let ParserMatchClass = SVELogicalImmNotOperand<16>; } def sve_logical_imm32_not : Operand { let ParserMatchClass = SVELogicalImmNotOperand<32>; } class SVEShiftedImmOperand : AsmOperandClass { let Name = "SVE" # Infix # "Imm" # ElementWidth; let DiagnosticType = "Invalid" # Name; let RenderMethod = "addImmWithOptionalShiftOperands<8>"; let ParserMethod = "tryParseImmWithOptionalShift"; let PredicateMethod = Predicate; } def SVECpyImmOperand8 : SVEShiftedImmOperand<8, "Cpy", "isSVECpyImm">; def SVECpyImmOperand16 : SVEShiftedImmOperand<16, "Cpy", "isSVECpyImm">; def SVECpyImmOperand32 : SVEShiftedImmOperand<32, "Cpy", "isSVECpyImm">; def SVECpyImmOperand64 : SVEShiftedImmOperand<64, "Cpy", "isSVECpyImm">; def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm">; def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm">; def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm">; def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm">; class imm8_opt_lsl : Operand, ImmLeaf { let EncoderMethod = "getImm8OptLsl"; let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">"; let PrintMethod = "printImm8OptLsl<" # printType # ">"; let ParserMatchClass = OpndClass; let MIOperandInfo = (ops i32imm, i32imm); } def cpy_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "int8_t", SVECpyImmOperand8, [{ return AArch64_AM::isSVECpyImm(Imm); }]>; def cpy_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "int16_t", SVECpyImmOperand16, [{ return AArch64_AM::isSVECpyImm(Imm); }]>; def cpy_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "int32_t", SVECpyImmOperand32, [{ return AArch64_AM::isSVECpyImm(Imm); }]>; def cpy_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "int64_t", SVECpyImmOperand64, [{ return AArch64_AM::isSVECpyImm(Imm); }]>; def addsub_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "uint8_t", SVEAddSubImmOperand8, [{ return AArch64_AM::isSVEAddSubImm(Imm); }]>; def addsub_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "uint16_t", SVEAddSubImmOperand16, [{ return AArch64_AM::isSVEAddSubImm(Imm); }]>; def addsub_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "uint32_t", SVEAddSubImmOperand32, [{ return AArch64_AM::isSVEAddSubImm(Imm); }]>; def addsub_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "uint64_t", SVEAddSubImmOperand64, [{ return AArch64_AM::isSVEAddSubImm(Imm); }]>; class SVEExactFPImm : AsmOperandClass { let Name = "SVEExactFPImmOperand" # Suffix; let DiagnosticType = "Invalid" # Name; let ParserMethod = "tryParseFPImm"; let PredicateMethod = "isExactFPImm<" # ValA # ", " # ValB # ">"; let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">"; } class SVEExactFPImmOperand : Operand { let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">"; let ParserMatchClass = SVEExactFPImm; } def sve_fpimm_half_one : SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half", "AArch64ExactFPImm::one">; def sve_fpimm_half_two : SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half", "AArch64ExactFPImm::two">; def sve_fpimm_zero_one : SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero", "AArch64ExactFPImm::one">; def sve_incdec_imm : Operand, ImmLeaf 0) && (((uint32_t)Imm) < 17); }]> { let ParserMatchClass = Imm1_16Operand; let EncoderMethod = "getSVEIncDecImm"; let DecoderMethod = "DecodeSVEIncDecImm"; } //===----------------------------------------------------------------------===// // SVE PTrue - These are used extensively throughout the pattern matching so // it's important we define them first. //===----------------------------------------------------------------------===// class sve_int_ptrue sz8_64, bits<3> opc, string asm, PPRRegOp pprty> : I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern), asm, "\t$Pd, $pattern", "", []>, Sched<[]> { bits<4> Pd; bits<5> pattern; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b011; let Inst{18-17} = opc{2-1}; let Inst{16} = opc{0}; let Inst{15-10} = 0b111000; let Inst{9-5} = pattern; let Inst{4} = 0b0; let Inst{3-0} = Pd; let Defs = !if(!eq (opc{0}, 1), [NZCV], []); } multiclass sve_int_ptrue opc, string asm> { def _B : sve_int_ptrue<0b00, opc, asm, PPR8>; def _H : sve_int_ptrue<0b01, opc, asm, PPR16>; def _S : sve_int_ptrue<0b10, opc, asm, PPR32>; def _D : sve_int_ptrue<0b11, opc, asm, PPR64>; def : InstAlias(NAME # _B) PPR8:$Pd, 0b11111), 1>; def : InstAlias(NAME # _H) PPR16:$Pd, 0b11111), 1>; def : InstAlias(NAME # _S) PPR32:$Pd, 0b11111), 1>; def : InstAlias(NAME # _D) PPR64:$Pd, 0b11111), 1>; } let Predicates = [HasSVE] in { defm PTRUE : sve_int_ptrue<0b000, "ptrue">; defm PTRUES : sve_int_ptrue<0b001, "ptrues">; } //===----------------------------------------------------------------------===// // SVE Predicate Misc Group //===----------------------------------------------------------------------===// class sve_int_pfalse opc, string asm> : I<(outs PPR8:$Pd), (ins), asm, "\t$Pd", "", []>, Sched<[]> { bits<4> Pd; let Inst{31-24} = 0b00100101; let Inst{23-22} = opc{5-4}; let Inst{21-19} = 0b011; let Inst{18-16} = opc{3-1}; let Inst{15-10} = 0b111001; let Inst{9} = opc{0}; let Inst{8-4} = 0b00000; let Inst{3-0} = Pd; } class sve_int_ptest opc, string asm> : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn), asm, "\t$Pg, $Pn", "", []>, Sched<[]> { bits<4> Pg; bits<4> Pn; let Inst{31-24} = 0b00100101; let Inst{23-22} = opc{5-4}; let Inst{21-19} = 0b010; let Inst{18-16} = opc{3-1}; let Inst{15-14} = 0b11; let Inst{13-10} = Pg; let Inst{9} = opc{0}; let Inst{8-5} = Pn; let Inst{4-0} = 0b00000; let Defs = [NZCV]; } class sve_int_pfirst_next sz8_64, bits<5> opc, string asm, PPRRegOp pprty> : I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn), asm, "\t$Pdn, $Pg, $_Pdn", "", []>, Sched<[]> { bits<4> Pdn; bits<4> Pg; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b011; let Inst{18-16} = opc{4-2}; let Inst{15-11} = 0b11000; let Inst{10-9} = opc{1-0}; let Inst{8-5} = Pg; let Inst{4} = 0; let Inst{3-0} = Pdn; let Constraints = "$Pdn = $_Pdn"; let Defs = [NZCV]; } multiclass sve_int_pfirst opc, string asm> { def : sve_int_pfirst_next<0b01, opc, asm, PPR8>; } multiclass sve_int_pnext opc, string asm> { def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>; def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>; def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>; def _D : sve_int_pfirst_next<0b11, opc, asm, PPR64>; } //===----------------------------------------------------------------------===// // SVE Predicate Count Group //===----------------------------------------------------------------------===// class sve_int_count_r sz8_64, bits<5> opc, string asm, RegisterOperand dty, PPRRegOp pprty, RegisterOperand sty> : I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn), asm, "\t$Rdn, $Pg", "", []>, Sched<[]> { bits<5> Rdn; bits<4> Pg; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b101; let Inst{18-16} = opc{4-2}; let Inst{15-11} = 0b10001; let Inst{10-9} = opc{1-0}; let Inst{8-5} = Pg; let Inst{4-0} = Rdn; // Signed 32bit forms require their GPR operand printed. let AsmString = !if(!eq(opc{4,2-0}, 0b0000), !strconcat(asm, "\t$Rdn, $Pg, $_Rdn"), !strconcat(asm, "\t$Rdn, $Pg")); let Constraints = "$Rdn = $_Rdn"; } multiclass sve_int_count_r_s32 opc, string asm> { def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>; def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>; def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>; def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64as32>; } multiclass sve_int_count_r_u32 opc, string asm> { def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>; def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>; def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>; def _D : sve_int_count_r<0b11, opc, asm, GPR32z, PPR64, GPR32z>; } multiclass sve_int_count_r_x64 opc, string asm> { def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>; def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>; def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>; def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>; } class sve_int_count_v sz8_64, bits<5> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg), asm, "\t$Zdn, $Pg", "", []>, Sched<[]> { bits<4> Pg; bits<5> Zdn; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b101; let Inst{18-16} = opc{4-2}; let Inst{15-11} = 0b10000; let Inst{10-9} = opc{1-0}; let Inst{8-5} = Pg; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_count_v opc, string asm> { def _H : sve_int_count_v<0b01, opc, asm, ZPR16>; def _S : sve_int_count_v<0b10, opc, asm, ZPR32>; def _D : sve_int_count_v<0b11, opc, asm, ZPR64>; } class sve_int_pcount_pred sz8_64, bits<4> opc, string asm, PPRRegOp pprty> : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), asm, "\t$Rd, $Pg, $Pn", "", []>, Sched<[]> { bits<4> Pg; bits<4> Pn; bits<5> Rd; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b100; let Inst{18-16} = opc{3-1}; let Inst{15-14} = 0b10; let Inst{13-10} = Pg; let Inst{9} = opc{0}; let Inst{8-5} = Pn; let Inst{4-0} = Rd; } multiclass sve_int_pcount_pred opc, string asm> { def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>; def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>; } //===----------------------------------------------------------------------===// // SVE Element Count Group //===----------------------------------------------------------------------===// class sve_int_count opc, string asm> : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4), asm, "\t$Rd, $pattern, mul $imm4", "", []>, Sched<[]> { bits<5> Rd; bits<4> imm4; bits<5> pattern; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc{2-1}; let Inst{21-20} = 0b10; let Inst{19-16} = imm4; let Inst{15-11} = 0b11100; let Inst{10} = opc{0}; let Inst{9-5} = pattern; let Inst{4-0} = Rd; } multiclass sve_int_count opc, string asm> { def NAME : sve_int_count; def : InstAlias(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>; def : InstAlias(NAME) GPR64:$Rd, 0b11111, 1), 2>; } class sve_int_countvlv opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), asm, "\t$Zdn, $pattern, mul $imm4", "", []>, Sched<[]> { bits<5> Zdn; bits<5> pattern; bits<4> imm4; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc{4-3}; let Inst{21} = 0b1; let Inst{20} = opc{2}; let Inst{19-16} = imm4; let Inst{15-12} = 0b1100; let Inst{11-10} = opc{1-0}; let Inst{9-5} = pattern; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_countvlv opc, string asm, ZPRRegOp zprty> { def NAME : sve_int_countvlv; def : InstAlias(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>; def : InstAlias(NAME) zprty:$Zdn, 0b11111, 1), 2>; } class sve_int_pred_pattern_a opc, string asm> : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), asm, "\t$Rdn, $pattern, mul $imm4", "", []>, Sched<[]> { bits<5> Rdn; bits<5> pattern; bits<4> imm4; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc{2-1}; let Inst{21-20} = 0b11; let Inst{19-16} = imm4; let Inst{15-11} = 0b11100; let Inst{10} = opc{0}; let Inst{9-5} = pattern; let Inst{4-0} = Rdn; let Constraints = "$Rdn = $_Rdn"; } multiclass sve_int_pred_pattern_a opc, string asm> { def NAME : sve_int_pred_pattern_a; def : InstAlias(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>; def : InstAlias(NAME) GPR64:$Rdn, 0b11111, 1), 2>; } class sve_int_pred_pattern_b opc, string asm, RegisterOperand dt, RegisterOperand st> : I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4), asm, "\t$Rdn, $pattern, mul $imm4", "", []>, Sched<[]> { bits<5> Rdn; bits<5> pattern; bits<4> imm4; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc{4-3}; let Inst{21} = 0b1; let Inst{20} = opc{2}; let Inst{19-16} = imm4; let Inst{15-12} = 0b1111; let Inst{11-10} = opc{1-0}; let Inst{9-5} = pattern; let Inst{4-0} = Rdn; // Signed 32bit forms require their GPR operand printed. let AsmString = !if(!eq(opc{2,0}, 0b00), !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"), !strconcat(asm, "\t$Rdn, $pattern, mul $imm4")); let Constraints = "$Rdn = $_Rdn"; } multiclass sve_int_pred_pattern_b_s32 opc, string asm> { def NAME : sve_int_pred_pattern_b; def : InstAlias(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>; def : InstAlias(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>; } multiclass sve_int_pred_pattern_b_u32 opc, string asm> { def NAME : sve_int_pred_pattern_b; def : InstAlias(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>; def : InstAlias(NAME) GPR32z:$Rdn, 0b11111, 1), 2>; } multiclass sve_int_pred_pattern_b_x64 opc, string asm> { def NAME : sve_int_pred_pattern_b; def : InstAlias(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>; def : InstAlias(NAME) GPR64z:$Rdn, 0b11111, 1), 2>; } //===----------------------------------------------------------------------===// // SVE Permute - Cross Lane Group //===----------------------------------------------------------------------===// class sve_int_perm_dup_r sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zd), (ins srcRegType:$Rn), asm, "\t$Zd, $Rn", "", []>, Sched<[]> { bits<5> Rn; bits<5> Zd; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-10} = 0b100000001110; let Inst{9-5} = Rn; let Inst{4-0} = Zd; } multiclass sve_int_perm_dup_r { def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>; def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>; def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, GPR32sp>; def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, GPR64sp>; def : InstAlias<"mov $Zd, $Rn", (!cast(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>; def : InstAlias<"mov $Zd, $Rn", (!cast(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>; def : InstAlias<"mov $Zd, $Rn", (!cast(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>; def : InstAlias<"mov $Zd, $Rn", (!cast(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>; } class sve_int_perm_dup_i tsz, Operand immtype, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$idx), asm, "\t$Zd, $Zn$idx", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; bits<7> idx; let Inst{31-24} = 0b00000101; let Inst{23-22} = {?,?}; // imm3h let Inst{21} = 0b1; let Inst{20-16} = tsz; let Inst{15-10} = 0b001000; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_dup_i { def _B : sve_int_perm_dup_i<{?,?,?,?,1}, sve_elm_idx_extdup_b, asm, ZPR8> { let Inst{23-22} = idx{5-4}; let Inst{20-17} = idx{3-0}; } def _H : sve_int_perm_dup_i<{?,?,?,1,0}, sve_elm_idx_extdup_h, asm, ZPR16> { let Inst{23-22} = idx{4-3}; let Inst{20-18} = idx{2-0}; } def _S : sve_int_perm_dup_i<{?,?,1,0,0}, sve_elm_idx_extdup_s, asm, ZPR32> { let Inst{23-22} = idx{3-2}; let Inst{20-19} = idx{1-0}; } def _D : sve_int_perm_dup_i<{?,1,0,0,0}, sve_elm_idx_extdup_d, asm, ZPR64> { let Inst{23-22} = idx{2-1}; let Inst{20} = idx{0}; } def _Q : sve_int_perm_dup_i<{1,0,0,0,0}, sve_elm_idx_extdup_q, asm, ZPR128> { let Inst{23-22} = idx{1-0}; } def : InstAlias<"mov $Zd, $Zn$idx", (!cast(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx), 1>; def : InstAlias<"mov $Zd, $Zn$idx", (!cast(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>; def : InstAlias<"mov $Zd, $Zn$idx", (!cast(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>; def : InstAlias<"mov $Zd, $Zn$idx", (!cast(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>; def : InstAlias<"mov $Zd, $Zn$idx", (!cast(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>; def : InstAlias<"mov $Zd, $Bn", (!cast(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>; def : InstAlias<"mov $Zd, $Hn", (!cast(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>; def : InstAlias<"mov $Zd, $Sn", (!cast(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>; def : InstAlias<"mov $Zd, $Dn", (!cast(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>; def : InstAlias<"mov $Zd, $Qn", (!cast(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; } class sve_int_perm_tbl sz8_64, string asm, ZPRRegOp zprty, RegisterOperand VecList> : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-10} = 0b001100; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_tbl { def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>; def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>; def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>; def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>; def : InstAlias(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>; def : InstAlias(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>; def : InstAlias(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>; def : InstAlias(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>; } class sve_int_perm_reverse_z sz8_64, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn), asm, "\t$Zd, $Zn", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-10} = 0b111000001110; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_reverse_z { def _B : sve_int_perm_reverse_z<0b00, asm, ZPR8>; def _H : sve_int_perm_reverse_z<0b01, asm, ZPR16>; def _S : sve_int_perm_reverse_z<0b10, asm, ZPR32>; def _D : sve_int_perm_reverse_z<0b11, asm, ZPR64>; } class sve_int_perm_reverse_p sz8_64, string asm, PPRRegOp pprty> : I<(outs pprty:$Pd), (ins pprty:$Pn), asm, "\t$Pd, $Pn", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-9} = 0b1101000100000; let Inst{8-5} = Pn; let Inst{4} = 0b0; let Inst{3-0} = Pd; } multiclass sve_int_perm_reverse_p { def _B : sve_int_perm_reverse_p<0b00, asm, PPR8>; def _H : sve_int_perm_reverse_p<0b01, asm, PPR16>; def _S : sve_int_perm_reverse_p<0b10, asm, PPR32>; def _D : sve_int_perm_reverse_p<0b11, asm, PPR64>; } class sve_int_perm_unpk sz16_64, bits<2> opc, string asm, ZPRRegOp zprty1, ZPRRegOp zprty2> : I<(outs zprty1:$Zd), (ins zprty2:$Zn), asm, "\t$Zd, $Zn", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz16_64; let Inst{21-18} = 0b1100; let Inst{17-16} = opc; let Inst{15-10} = 0b001110; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_unpk opc, string asm> { def _H : sve_int_perm_unpk<0b01, opc, asm, ZPR16, ZPR8>; def _S : sve_int_perm_unpk<0b10, opc, asm, ZPR32, ZPR16>; def _D : sve_int_perm_unpk<0b11, opc, asm, ZPR64, ZPR32>; } class sve_int_perm_insrs sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm), asm, "\t$Zdn, $Rm", "", []>, Sched<[]> { bits<5> Rm; bits<5> Zdn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-10} = 0b100100001110; let Inst{9-5} = Rm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_perm_insrs { def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>; def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>; def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>; def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>; } class sve_int_perm_insrv sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm), asm, "\t$Zdn, $Vm", "", []>, Sched<[]> { bits<5> Vm; bits<5> Zdn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-10} = 0b110100001110; let Inst{9-5} = Vm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_perm_insrv { def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>; def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>; def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>; def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>; } //===----------------------------------------------------------------------===// // SVE Permute - Extract Group //===----------------------------------------------------------------------===// class sve_int_perm_extract_i : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8), asm, "\t$Zdn, $_Zdn, $Zm, $imm8", "", []>, Sched<[]> { bits<5> Zdn; bits<5> Zm; bits<8> imm8; let Inst{31-21} = 0b00000101001; let Inst{20-16} = imm8{7-3}; let Inst{15-13} = 0b000; let Inst{12-10} = imm8{2-0}; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } //===----------------------------------------------------------------------===// // SVE Vector Select Group //===----------------------------------------------------------------------===// class sve_int_sel_vvv sz8_64, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm), asm, "\t$Zd, $Pg, $Zn, $Zm", "", []>, Sched<[]> { bits<4> Pg; bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-14} = 0b11; let Inst{13-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_sel_vvv { def _B : sve_int_sel_vvv<0b00, asm, ZPR8>; def _H : sve_int_sel_vvv<0b01, asm, ZPR16>; def _S : sve_int_sel_vvv<0b10, asm, ZPR32>; def _D : sve_int_sel_vvv<0b11, asm, ZPR64>; def : InstAlias<"mov $Zd, $Pg/m, $Zn", (!cast(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Zn", (!cast(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Zn", (!cast(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Zn", (!cast(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>; } //===----------------------------------------------------------------------===// // SVE Predicate Logical Operations Group //===----------------------------------------------------------------------===// class sve_int_pred_log opc, string asm> : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), asm, "\t$Pd, $Pg/z, $Pn, $Pm", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pg; bits<4> Pm; bits<4> Pn; let Inst{31-24} = 0b00100101; let Inst{23-22} = opc{3-2}; let Inst{21-20} = 0b00; let Inst{19-16} = Pm; let Inst{15-14} = 0b01; let Inst{13-10} = Pg; let Inst{9} = opc{1}; let Inst{8-5} = Pn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; // SEL has no predication qualifier. let AsmString = !if(!eq(opc, 0b0011), !strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"), !strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm")); let Defs = !if(!eq (opc{2}, 1), [NZCV], []); } //===----------------------------------------------------------------------===// // SVE Logical Mask Immediate Group //===----------------------------------------------------------------------===// class sve_int_log_imm opc, string asm> : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13), asm, "\t$Zdn, $_Zdn, $imms13", "", []>, Sched<[]> { bits<5> Zdn; bits<13> imms13; let Inst{31-24} = 0b00000101; let Inst{23-22} = opc; let Inst{21-18} = 0b0000; let Inst{17-5} = imms13; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DecoderMethod = "DecodeSVELogicalImmInstruction"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_log_imm opc, string asm, string alias> { def NAME : sve_int_log_imm; def : InstAlias(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>; def : InstAlias(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>; def : InstAlias(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>; def : InstAlias(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>; def : InstAlias(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>; def : InstAlias(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>; def : InstAlias(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>; } class sve_int_dup_mask_imm : I<(outs ZPR64:$Zd), (ins logical_imm64:$imms), asm, "\t$Zd, $imms", "", []>, Sched<[]> { bits<5> Zd; bits<13> imms; let Inst{31-18} = 0b00000101110000; let Inst{17-5} = imms; let Inst{4-0} = Zd; let isReMaterializable = 1; let DecoderMethod = "DecodeSVELogicalImmInstruction"; } multiclass sve_int_dup_mask_imm { def NAME : sve_int_dup_mask_imm; def : InstAlias<"dupm $Zd, $imm", (!cast(NAME) ZPR8:$Zd, sve_logical_imm8:$imm), 4>; def : InstAlias<"dupm $Zd, $imm", (!cast(NAME) ZPR16:$Zd, sve_logical_imm16:$imm), 3>; def : InstAlias<"dupm $Zd, $imm", (!cast(NAME) ZPR32:$Zd, sve_logical_imm32:$imm), 2>; // All Zd.b forms have a CPY/DUP equivalent, hence no byte alias here. def : InstAlias<"mov $Zd, $imm", (!cast(NAME) ZPR16:$Zd, sve_preferred_logical_imm16:$imm), 7>; def : InstAlias<"mov $Zd, $imm", (!cast(NAME) ZPR32:$Zd, sve_preferred_logical_imm32:$imm), 6>; def : InstAlias<"mov $Zd, $imm", (!cast(NAME) ZPR64:$Zd, sve_preferred_logical_imm64:$imm), 5>; } //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Unpredicated Group. //===----------------------------------------------------------------------===// class sve_int_bin_cons_arit_0 sz8_64, bits<3> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-13} = 0b000; let Inst{12-10} = opc; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_bin_cons_arit_0 opc, string asm> { def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>; def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>; def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Arithmetic - Predicated Group //===----------------------------------------------------------------------===// class sve_fp_2op_i_p_zds sz, bits<3> opc, string asm, ZPRRegOp zprty, Operand imm_ty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1), asm, "\t$Zdn, $Pg/m, $_Zdn, $i1", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bit i1; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-19} = 0b011; let Inst{18-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-6} = 0b0000; let Inst{5} = i1; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_fp_2op_i_p_zds opc, string asm, Operand imm_ty> { def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>; def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>; def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>; } class sve_fp_2op_p_zds sz, bits<4> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Zm; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-20} = 0b00; let Inst{19-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_fp_2op_p_zds opc, string asm> { def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>; def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>; def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; } class sve_fp_ftmad sz, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm0_7:$imm3), asm, "\t$Zdn, $_Zdn, $Zm, $imm3", "", []>, Sched<[]> { bits<5> Zdn; bits<5> Zm; bits<3> imm3; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-19} = 0b010; let Inst{18-16} = imm3; let Inst{15-10} = 0b100000; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_fp_ftmad { def _H : sve_fp_ftmad<0b01, asm, ZPR16>; def _S : sve_fp_ftmad<0b10, asm, ZPR32>; def _D : sve_fp_ftmad<0b11, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Arithmetic - Unpredicated Group //===----------------------------------------------------------------------===// class sve_fp_3op_u_zd sz, bits<3> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21} = 0b0; let Inst{20-16} = Zm; let Inst{15-13} = 0b000; let Inst{12-10} = opc; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_fp_3op_u_zd opc, string asm> { def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>; def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>; def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Fused Multiply-Add Group //===----------------------------------------------------------------------===// class sve_fp_3op_p_zds_a sz, bits<2> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), asm, "\t$Zda, $Pg/m, $Zn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zda; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15} = 0b0; let Inst{14-13} = opc; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_fp_3op_p_zds_a opc, string asm> { def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>; def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>; def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>; } class sve_fp_3op_p_zds_b sz, bits<2> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), asm, "\t$Zdn, $Pg/m, $Zm, $Za", "", []>, Sched<[]> { bits<3> Pg; bits<5> Za; bits<5> Zdn; bits<5> Zm; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21} = 0b1; let Inst{20-16} = Za; let Inst{15} = 0b1; let Inst{14-13} = opc; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_fp_3op_p_zds_b opc, string asm> { def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>; def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>; def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Multiply-Add - Indexed Group //===----------------------------------------------------------------------===// class sve_fp_fma_by_indexed_elem sz, bit opc, string asm, ZPRRegOp zprty1, ZPRRegOp zprty2, Operand itype> : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop), asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { bits<5> Zda; bits<5> Zn; let Inst{31-24} = 0b01100100; let Inst{23-22} = sz; let Inst{21} = 0b1; let Inst{15-11} = 0; let Inst{10} = opc; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_fp_fma_by_indexed_elem { def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> { bits<3> Zm; bits<3> iop; let Inst{22} = iop{2}; let Inst{20-19} = iop{1-0}; let Inst{18-16} = Zm; } def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS> { bits<3> Zm; bits<2> iop; let Inst{20-19} = iop; let Inst{18-16} = Zm; } def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD> { bits<4> Zm; bit iop; let Inst{20} = iop; let Inst{19-16} = Zm; } } //===----------------------------------------------------------------------===// // SVE Floating Point Multiply - Indexed Group //===----------------------------------------------------------------------===// class sve_fp_fmul_by_indexed_elem sz, string asm, ZPRRegOp zprty, ZPRRegOp zprty2, Operand itype> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop), asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b01100100; let Inst{23-22} = sz; let Inst{21} = 0b1; let Inst{15-10} = 0b001000; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_fp_fmul_by_indexed_elem { def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH> { bits<3> Zm; bits<3> iop; let Inst{22} = iop{2}; let Inst{20-19} = iop{1-0}; let Inst{18-16} = Zm; } def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS> { bits<3> Zm; bits<2> iop; let Inst{20-19} = iop; let Inst{18-16} = Zm; } def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD> { bits<4> Zm; bit iop; let Inst{20} = iop; let Inst{19-16} = Zm; } } //===----------------------------------------------------------------------===// // SVE Floating Point Complex Multiply-Add Group //===----------------------------------------------------------------------===// class sve_fp_fcmla sz, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm, complexrotateop:$imm), asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm", "", []>, Sched<[]> { bits<5> Zda; bits<3> Pg; bits<5> Zn; bits<5> Zm; bits<2> imm; let Inst{31-24} = 0b01100100; let Inst{23-22} = sz; let Inst{21} = 0; let Inst{20-16} = Zm; let Inst{15} = 0; let Inst{14-13} = imm; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_fp_fcmla { def _H : sve_fp_fcmla<0b01, asm, ZPR16>; def _S : sve_fp_fcmla<0b10, asm, ZPR32>; def _D : sve_fp_fcmla<0b11, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Complex Multiply-Add - Indexed Group //===----------------------------------------------------------------------===// class sve_fp_fcmla_by_indexed_elem sz, string asm, ZPRRegOp zprty, ZPRRegOp zprty2, Operand itype> : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop, complexrotateop:$imm), asm, "\t$Zda, $Zn, $Zm$iop, $imm", "", []>, Sched<[]> { bits<5> Zda; bits<5> Zn; bits<2> imm; let Inst{31-24} = 0b01100100; let Inst{23-22} = sz; let Inst{21} = 0b1; let Inst{15-12} = 0b0001; let Inst{11-10} = imm; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_fp_fcmla_by_indexed_elem { def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> { bits<3> Zm; bits<2> iop; let Inst{20-19} = iop; let Inst{18-16} = Zm; } def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> { bits<4> Zm; bits<1> iop; let Inst{20} = iop; let Inst{19-16} = Zm; } } //===----------------------------------------------------------------------===// // SVE Floating Point Complex Addition Group //===----------------------------------------------------------------------===// class sve_fp_fcadd sz, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$imm), asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm", "", []>, Sched<[]> { bits<5> Zdn; bits<5> Zm; bits<3> Pg; bit imm; let Inst{31-24} = 0b01100100; let Inst{23-22} = sz; let Inst{21-17} = 0; let Inst{16} = imm; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_fp_fcadd { def _H : sve_fp_fcadd<0b01, asm, ZPR16>; def _S : sve_fp_fcadd<0b10, asm, ZPR32>; def _D : sve_fp_fcadd<0b11, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Stack Allocation Group //===----------------------------------------------------------------------===// class sve_int_arith_vl : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6), asm, "\t$Rd, $Rn, $imm6", "", []>, Sched<[]> { bits<5> Rd; bits<5> Rn; bits<6> imm6; let Inst{31-23} = 0b000001000; let Inst{22} = opc; let Inst{21} = 0b1; let Inst{20-16} = Rn; let Inst{15-11} = 0b01010; let Inst{10-5} = imm6; let Inst{4-0} = Rd; } class sve_int_read_vl_a opc2, string asm> : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6), asm, "\t$Rd, $imm6", "", []>, Sched<[]> { bits<5> Rd; bits<6> imm6; let Inst{31-23} = 0b000001001; let Inst{22} = op; let Inst{21} = 0b1; let Inst{20-16} = opc2{4-0}; let Inst{15-11} = 0b01010; let Inst{10-5} = imm6; let Inst{4-0} = Rd; } //===----------------------------------------------------------------------===// // SVE Permute - In Lane Group //===----------------------------------------------------------------------===// class sve_int_perm_bin_perm_zz opc, bits<2> sz8_64, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-13} = 0b011; let Inst{12-10} = opc; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_bin_perm_zz opc, string asm> { def _B : sve_int_perm_bin_perm_zz; def _H : sve_int_perm_bin_perm_zz; def _S : sve_int_perm_bin_perm_zz; def _D : sve_int_perm_bin_perm_zz; } //===----------------------------------------------------------------------===// // SVE Floating Point Unary Operations Group //===----------------------------------------------------------------------===// class sve_fp_2op_p_zd opc, string asm, RegisterOperand i_zprtype, RegisterOperand o_zprtype, ElementSizeEnum size> : I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn), asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b01100101; let Inst{23-22} = opc{6-5}; let Inst{21} = 0b0; let Inst{20-16} = opc{4-0}; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; let Constraints = "$Zd = $_Zd"; let DestructiveInstType = Destructive; let ElementSize = size; } multiclass sve_fp_2op_p_zd_HSD opc, string asm> { def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>; def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>; def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>; } //===----------------------------------------------------------------------===// // SVE Floating Point Unary Operations - Unpredicated Group //===----------------------------------------------------------------------===// class sve_fp_2op_u_zd sz, bits<3> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn), asm, "\t$Zd, $Zn", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-19} = 0b001; let Inst{18-16} = opc; let Inst{15-10} = 0b001100; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_fp_2op_u_zd opc, string asm> { def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>; def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>; def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Binary Predicated Group //===----------------------------------------------------------------------===// class sve_int_bin_pred_arit_log sz8_64, bits<2> fmt, bits<3> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Zm; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b0; let Inst{20-19} = fmt; let Inst{18-16} = opc; let Inst{15-13} = 0b000; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_bin_pred_log opc, string asm> { def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; } multiclass sve_int_bin_pred_arit_0 opc, string asm> { def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>; } multiclass sve_int_bin_pred_arit_1 opc, string asm> { def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>; } multiclass sve_int_bin_pred_arit_2 opc, string asm> { def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>; def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; } // Special case for divides which are not defined for 8b/16b elements. multiclass sve_int_bin_pred_arit_2_div opc, string asm> { def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>; def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Integer Multiply-Add Group //===----------------------------------------------------------------------===// class sve_int_mladdsub_vvv_pred sz8_64, bits<1> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za), asm, "\t$Zdn, $Pg/m, $Zm, $Za", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Za; bits<5> Zm; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b0; let Inst{20-16} = Zm; let Inst{15-14} = 0b11; let Inst{13} = opc; let Inst{12-10} = Pg; let Inst{9-5} = Za; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_mladdsub_vvv_pred opc, string asm> { def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>; def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>; def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>; def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>; } class sve_int_mlas_vvv_pred sz8_64, bits<1> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm), asm, "\t$Zda, $Pg/m, $Zn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zda; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b0; let Inst{20-16} = Zm; let Inst{15-14} = 0b01; let Inst{13} = opc; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_mlas_vvv_pred opc, string asm> { def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>; def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>; def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>; def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Integer Dot Product Group //===----------------------------------------------------------------------===// class sve_intx_dot : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zda; bits<5> Zn; bits<5> Zm; let Inst{31-23} = 0b010001001; let Inst{22} = sz; let Inst{21} = 0; let Inst{20-16} = Zm; let Inst{15-11} = 0; let Inst{10} = U; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = zprty1.ElementSize; } multiclass sve_intx_dot { def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>; def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>; } //===----------------------------------------------------------------------===// // SVE Integer Dot Product Group - Indexed Group //===----------------------------------------------------------------------===// class sve_intx_dot_by_indexed_elem : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop), asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { bits<5> Zda; bits<5> Zn; let Inst{31-23} = 0b010001001; let Inst{22} = sz; let Inst{21} = 0b1; let Inst{15-11} = 0; let Inst{10} = U; let Inst{9-5} = Zn; let Inst{4-0} = Zda; let Constraints = "$Zda = $_Zda"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_intx_dot_by_indexed_elem { def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { bits<2> iop; bits<3> Zm; let Inst{20-19} = iop; let Inst{18-16} = Zm; } def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { bits<1> iop; bits<4> Zm; let Inst{20} = iop; let Inst{19-16} = Zm; } } //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Unary Predicated Group //===----------------------------------------------------------------------===// class sve_int_un_pred_arit sz8_64, bits<4> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21-20} = 0b01; let Inst{19} = opc{0}; let Inst{18-16} = opc{3-1}; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; let Constraints = "$Zd = $_Zd"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_un_pred_arit_0 opc, string asm> { def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>; def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; } multiclass sve_int_un_pred_arit_0_h opc, string asm> { def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>; def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; } multiclass sve_int_un_pred_arit_0_w opc, string asm> { def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; } multiclass sve_int_un_pred_arit_0_d opc, string asm> { def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>; } multiclass sve_int_un_pred_arit_1 opc, string asm> { def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>; def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>; def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; } multiclass sve_int_un_pred_arit_1_fp opc, string asm> { def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>; def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>; def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Integer Wide Immediate - Unpredicated Group //===----------------------------------------------------------------------===// class sve_int_dup_imm sz8_64, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zd), (ins immtype:$imm), asm, "\t$Zd, $imm", "", []>, Sched<[]> { bits<5> Zd; bits<9> imm; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-14} = 0b11100011; let Inst{13} = imm{8}; // sh let Inst{12-5} = imm{7-0}; // imm8 let Inst{4-0} = Zd; let isReMaterializable = 1; } multiclass sve_int_dup_imm { def _B : sve_int_dup_imm<0b00, asm, ZPR8, cpy_imm8_opt_lsl_i8>; def _H : sve_int_dup_imm<0b01, asm, ZPR16, cpy_imm8_opt_lsl_i16>; def _S : sve_int_dup_imm<0b10, asm, ZPR32, cpy_imm8_opt_lsl_i32>; def _D : sve_int_dup_imm<0b11, asm, ZPR64, cpy_imm8_opt_lsl_i64>; def : InstAlias<"mov $Zd, $imm", (!cast(NAME # _B) ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm), 1>; def : InstAlias<"mov $Zd, $imm", (!cast(NAME # _H) ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm), 1>; def : InstAlias<"mov $Zd, $imm", (!cast(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>; def : InstAlias<"mov $Zd, $imm", (!cast(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>; def : InstAlias<"fmov $Zd, #0.0", (!cast(NAME # _H) ZPR16:$Zd, 0, 0), 1>; def : InstAlias<"fmov $Zd, #0.0", (!cast(NAME # _S) ZPR32:$Zd, 0, 0), 1>; def : InstAlias<"fmov $Zd, #0.0", (!cast(NAME # _D) ZPR64:$Zd, 0, 0), 1>; } class sve_int_dup_fpimm sz8_64, Operand fpimmtype, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins fpimmtype:$imm8), asm, "\t$Zd, $imm8", "", []>, Sched<[]> { bits<5> Zd; bits<8> imm8; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-14} = 0b11100111; let Inst{13} = 0b0; let Inst{12-5} = imm8; let Inst{4-0} = Zd; let isReMaterializable = 1; } multiclass sve_int_dup_fpimm { def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>; def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>; def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>; def : InstAlias<"fmov $Zd, $imm8", (!cast(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>; def : InstAlias<"fmov $Zd, $imm8", (!cast(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>; def : InstAlias<"fmov $Zd, $imm8", (!cast(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>; } class sve_int_arith_imm0 sz8_64, bits<3> opc, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), asm, "\t$Zdn, $_Zdn, $imm", "", []>, Sched<[]> { bits<5> Zdn; bits<9> imm; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b100; let Inst{18-16} = opc; let Inst{15-14} = 0b11; let Inst{13} = imm{8}; // sh let Inst{12-5} = imm{7-0}; // imm8 let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_arith_imm0 opc, string asm> { def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>; def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>; def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>; def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; } class sve_int_arith_imm sz8_64, bits<6> opc, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm), asm, "\t$Zdn, $_Zdn, $imm", "", []>, Sched<[]> { bits<5> Zdn; bits<8> imm; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-16} = opc; let Inst{15-13} = 0b110; let Inst{12-5} = imm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_arith_imm1 opc, string asm, Operand immtype> { def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>; def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>; def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>; def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>; } multiclass sve_int_arith_imm2 { def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>; def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>; def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>; def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>; } //===----------------------------------------------------------------------===// // SVE Bitwise Logical - Unpredicated Group //===----------------------------------------------------------------------===// class sve_int_bin_cons_log opc, string asm> : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc{1-0}; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-10} = 0b001100; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } //===----------------------------------------------------------------------===// // SVE Integer Wide Immediate - Predicated Group //===----------------------------------------------------------------------===// class sve_int_dup_fpimm_pred sz, Operand fpimmtype, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8), asm, "\t$Zd, $Pg/m, $imm8", "", []>, Sched<[]> { bits<4> Pg; bits<5> Zd; bits<8> imm8; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz; let Inst{21-20} = 0b01; let Inst{19-16} = Pg; let Inst{15-13} = 0b110; let Inst{12-5} = imm8; let Inst{4-0} = Zd; let Constraints = "$Zd = $_Zd"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_dup_fpimm_pred { def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>; def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>; def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>; def : InstAlias<"fmov $Zd, $Pg/m, $imm8", (!cast(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8), 1>; def : InstAlias<"fmov $Zd, $Pg/m, $imm8", (!cast(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8), 1>; def : InstAlias<"fmov $Zd, $Pg/m, $imm8", (!cast(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8), 1>; } class sve_int_dup_imm_pred sz8_64, bit m, string asm, ZPRRegOp zprty, string pred_qual, dag iops> : I<(outs zprty:$Zd), iops, asm, "\t$Zd, $Pg"#pred_qual#", $imm", "", []>, Sched<[]> { bits<5> Zd; bits<4> Pg; bits<9> imm; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-20} = 0b01; let Inst{19-16} = Pg; let Inst{15} = 0b0; let Inst{14} = m; let Inst{13} = imm{8}; // sh let Inst{12-5} = imm{7-0}; // imm8 let Inst{4-0} = Zd; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_dup_imm_pred_merge { let Constraints = "$Zd = $_Zd" in { def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; } def : InstAlias<"mov $Zd, $Pg/m, $imm", (!cast(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>; def : InstAlias<"mov $Zd, $Pg/m, $imm", (!cast(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>; def : InstAlias<"mov $Zd, $Pg/m, $imm", (!cast(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>; def : InstAlias<"mov $Zd, $Pg/m, $imm", (!cast(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>; def : InstAlias<"fmov $Zd, $Pg/m, #0.0", (!cast(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, 0, 0), 0>; def : InstAlias<"fmov $Zd, $Pg/m, #0.0", (!cast(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, 0, 0), 0>; def : InstAlias<"fmov $Zd, $Pg/m, #0.0", (!cast(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, 0, 0), 0>; } multiclass sve_int_dup_imm_pred_zero { def _B : sve_int_dup_imm_pred<0b00, 0, asm, ZPR8, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>; def _H : sve_int_dup_imm_pred<0b01, 0, asm, ZPR16, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>; def _S : sve_int_dup_imm_pred<0b10, 0, asm, ZPR32, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>; def _D : sve_int_dup_imm_pred<0b11, 0, asm, ZPR64, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>; def : InstAlias<"mov $Zd, $Pg/z, $imm", (!cast(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>; def : InstAlias<"mov $Zd, $Pg/z, $imm", (!cast(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>; def : InstAlias<"mov $Zd, $Pg/z, $imm", (!cast(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>; def : InstAlias<"mov $Zd, $Pg/z, $imm", (!cast(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>; } //===----------------------------------------------------------------------===// // SVE Integer Compare - Vectors Group //===----------------------------------------------------------------------===// class sve_int_cmp sz8_64, bits<3> opc, string asm, PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2> : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm), asm, "\t$Pd, $Pg/z, $Zn, $Zm", "", []>, Sched<[]> { bits<4> Pd; bits<3> Pg; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00100100; let Inst{23-22} = sz8_64; let Inst{21} = 0b0; let Inst{20-16} = Zm; let Inst{15} = opc{2}; let Inst{14} = cmp_1; let Inst{13} = opc{1}; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; let Defs = [NZCV]; } multiclass sve_int_cmp_0 opc, string asm> { def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>; def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>; def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>; def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>; } multiclass sve_int_cmp_0_wide opc, string asm> { def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>; def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>; def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>; } multiclass sve_int_cmp_1_wide opc, string asm> { def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>; def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>; def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Integer Compare - Signed Immediate Group //===----------------------------------------------------------------------===// class sve_int_scmp_vi sz8_64, bits<3> opc, string asm, PPRRegOp pprty, ZPRRegOp zprty, Operand immtype> : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5), asm, "\t$Pd, $Pg/z, $Zn, $imm5", "", []>, Sched<[]> { bits<4> Pd; bits<3> Pg; bits<5> Zn; bits<5> imm5; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21} = 0b0; let Inst{20-16} = imm5; let Inst{15} = opc{2}; let Inst{14} = 0b0; let Inst{13} = opc{1}; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; let Defs = [NZCV]; } multiclass sve_int_scmp_vi opc, string asm> { def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>; def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>; def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>; def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>; } //===----------------------------------------------------------------------===// // SVE Integer Compare - Unsigned Immediate Group //===----------------------------------------------------------------------===// class sve_int_ucmp_vi sz8_64, bits<2> opc, string asm, PPRRegOp pprty, ZPRRegOp zprty, Operand immtype> : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7), asm, "\t$Pd, $Pg/z, $Zn, $imm7", "", []>, Sched<[]> { bits<4> Pd; bits<3> Pg; bits<5> Zn; bits<7> imm7; let Inst{31-24} = 0b00100100; let Inst{23-22} = sz8_64; let Inst{21} = 1; let Inst{20-14} = imm7; let Inst{13} = opc{1}; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; let Defs = [NZCV]; } multiclass sve_int_ucmp_vi opc, string asm> { def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>; def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>; def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>; def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127>; } //===----------------------------------------------------------------------===// // SVE Integer Compare - Scalars Group //===----------------------------------------------------------------------===// class sve_int_cterm : I<(outs), (ins rt:$Rn, rt:$Rm), asm, "\t$Rn, $Rm", "", []>, Sched<[]> { bits<5> Rm; bits<5> Rn; let Inst{31-23} = 0b001001011; let Inst{22} = sz; let Inst{21} = 0b1; let Inst{20-16} = Rm; let Inst{15-10} = 0b001000; let Inst{9-5} = Rn; let Inst{4} = opc; let Inst{3-0} = 0b0000; let Defs = [NZCV]; } class sve_int_while_rr sz8_64, bits<4> opc, string asm, RegisterClass gprty, PPRRegOp pprty> : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm), asm, "\t$Pd, $Rn, $Rm", "", []>, Sched<[]> { bits<4> Pd; bits<5> Rm; bits<5> Rn; let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Rm; let Inst{15-13} = 0b000; let Inst{12-10} = opc{3-1}; let Inst{9-5} = Rn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; let Defs = [NZCV]; } multiclass sve_int_while4_rr opc, string asm> { def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>; def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>; def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>; def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64>; } multiclass sve_int_while8_rr opc, string asm> { def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>; def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>; def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>; def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Fast Reduction Group //===----------------------------------------------------------------------===// class sve_fp_fast_red sz, bits<3> opc, string asm, ZPRRegOp zprty, RegisterClass dstRegClass> : I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Vd, $Pg, $Zn", "", []>, Sched<[]> { bits<5> Zn; bits<5> Vd; bits<3> Pg; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-19} = 0b000; let Inst{18-16} = opc; let Inst{15-13} = 0b001; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Vd; } multiclass sve_fp_fast_red opc, string asm> { def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>; def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>; def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Accumulating Reduction Group //===----------------------------------------------------------------------===// class sve_fp_2op_p_vd sz, bits<3> opc, string asm, ZPRRegOp zprty, RegisterClass dstRegClass> : I<(outs dstRegClass:$Vdn), (ins PPR3bAny:$Pg, dstRegClass:$_Vdn, zprty:$Zm), asm, "\t$Vdn, $Pg, $_Vdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Vdn; bits<5> Zm; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-19} = 0b011; let Inst{18-16} = opc; let Inst{15-13} = 0b001; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Vdn; let Constraints = "$Vdn = $_Vdn"; } multiclass sve_fp_2op_p_vd opc, string asm> { def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>; def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>; def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Compare - Vectors Group //===----------------------------------------------------------------------===// class sve_fp_3op_p_pd sz, bits<3> opc, string asm, PPRRegOp pprty, ZPRRegOp zprty> : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), asm, "\t$Pd, $Pg/z, $Zn, $Zm", "", []>, Sched<[]> { bits<4> Pd; bits<3> Pg; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21} = 0b0; let Inst{20-16} = Zm; let Inst{15} = opc{2}; let Inst{14} = 0b1; let Inst{13} = opc{1}; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; } multiclass sve_fp_3op_p_pd opc, string asm> { def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>; def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>; def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Floating Point Compare - with Zero Group //===----------------------------------------------------------------------===// class sve_fp_2op_p_pd sz, bits<3> opc, string asm, PPRRegOp pprty, ZPRRegOp zprty> : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Pd, $Pg/z, $Zn, #0.0", "", []>, Sched<[]> { bits<4> Pd; bits<3> Pg; bits<5> Zn; let Inst{31-24} = 0b01100101; let Inst{23-22} = sz; let Inst{21-18} = 0b0100; let Inst{17-16} = opc{2-1}; let Inst{15-13} = 0b001; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; } multiclass sve_fp_2op_p_pd opc, string asm> { def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>; def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>; def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>; } //===----------------------------------------------------------------------===// //SVE Index Generation Group //===----------------------------------------------------------------------===// class sve_int_index_ii sz8_64, string asm, ZPRRegOp zprty, Operand imm_ty> : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b), asm, "\t$Zd, $imm5, $imm5b", "", []>, Sched<[]> { bits<5> Zd; bits<5> imm5; bits<5> imm5b; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = imm5b; let Inst{15-10} = 0b010000; let Inst{9-5} = imm5; let Inst{4-0} = Zd; } multiclass sve_int_index_ii { def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>; def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>; def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>; def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>; } class sve_int_index_ir sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType, Operand imm_ty> : I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm), asm, "\t$Zd, $imm5, $Rm", "", []>, Sched<[]> { bits<5> Rm; bits<5> Zd; bits<5> imm5; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Rm; let Inst{15-10} = 0b010010; let Inst{9-5} = imm5; let Inst{4-0} = Zd; } multiclass sve_int_index_ir { def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>; def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>; def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>; def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>; } class sve_int_index_ri sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType, Operand imm_ty> : I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5), asm, "\t$Zd, $Rn, $imm5", "", []>, Sched<[]> { bits<5> Rn; bits<5> Zd; bits<5> imm5; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = imm5; let Inst{15-10} = 0b010001; let Inst{9-5} = Rn; let Inst{4-0} = Zd; } multiclass sve_int_index_ri { def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>; def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>; def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>; def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>; } class sve_int_index_rr sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm), asm, "\t$Zd, $Rn, $Rm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Rm; bits<5> Rn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Rm; let Inst{15-10} = 0b010011; let Inst{9-5} = Rn; let Inst{4-0} = Zd; } multiclass sve_int_index_rr { def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>; def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>; def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>; def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>; } // //===----------------------------------------------------------------------===// // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// class sve_int_bin_pred_shift_imm tsz8_64, bits<3> opc, string asm, ZPRRegOp zprty, Operand immtype, ElementSizeEnum size> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<6> imm; let Inst{31-24} = 0b00000100; let Inst{23-22} = tsz8_64{3-2}; let Inst{21-19} = 0b000; let Inst{18-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-8} = tsz8_64{1-0}; let Inst{7-5} = imm{2-0}; // imm3 let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = size; } multiclass sve_int_bin_pred_shift_imm_left opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, ElementSizeH> { let Inst{8} = imm{3}; } def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32, ElementSizeS> { let Inst{9-8} = imm{4-3}; } def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64, ElementSizeD> { let Inst{22} = imm{5}; let Inst{9-8} = imm{4-3}; } } multiclass sve_int_bin_pred_shift_imm_right opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, ElementSizeH> { let Inst{8} = imm{3}; } def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32, ElementSizeS> { let Inst{9-8} = imm{4-3}; } def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64, ElementSizeD> { let Inst{22} = imm{5}; let Inst{9-8} = imm{4-3}; } } class sve_int_bin_pred_shift sz8_64, bit wide, bits<3> opc, string asm, ZPRRegOp zprty, ZPRRegOp zprty2> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Zm; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21-20} = 0b01; let Inst{19} = wide; let Inst{18-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_bin_pred_shift opc, string asm> { def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>; def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>; def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>; def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>; } multiclass sve_int_bin_pred_shift_wide opc, string asm> { def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>; def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>; def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Shift - Unpredicated Group //===----------------------------------------------------------------------===// class sve_int_bin_cons_shift_wide sz8_64, bits<2> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-12} = 0b1000; let Inst{11-10} = opc; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_bin_cons_shift_wide opc, string asm> { def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>; def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>; def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>; } class sve_int_bin_cons_shift_imm tsz8_64, bits<2> opc, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm), asm, "\t$Zd, $Zn, $imm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; bits<6> imm; let Inst{31-24} = 0b00000100; let Inst{23-22} = tsz8_64{3-2}; let Inst{21} = 0b1; let Inst{20-19} = tsz8_64{1-0}; let Inst{18-16} = imm{2-0}; // imm3 let Inst{15-12} = 0b1001; let Inst{11-10} = opc; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_bin_cons_shift_imm_left opc, string asm> { def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { let Inst{19} = imm{3}; } def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { let Inst{20-19} = imm{4-3}; } def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } } multiclass sve_int_bin_cons_shift_imm_right opc, string asm> { def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { let Inst{19} = imm{3}; } def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { let Inst{20-19} = imm{4-3}; } def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } } //===----------------------------------------------------------------------===// // SVE Memory - Store Group //===----------------------------------------------------------------------===// class sve_mem_cst_si msz, bits<2> esz, string asm, RegisterOperand VecList> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zt; bits<4> imm4; let Inst{31-25} = 0b1110010; let Inst{24-23} = msz; let Inst{22-21} = esz; let Inst{20} = 0; let Inst{19-16} = imm4; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_cst_si msz, bits<2> esz, string asm, RegisterOperand listty, ZPRRegOp zprty> { def NAME : sve_mem_cst_si; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; def : InstAlias(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_est_si sz, bits<2> nregs, RegisterOperand VecList, string asm, Operand immtype> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zt; bits<4> imm4; let Inst{31-25} = 0b1110010; let Inst{24-23} = sz; let Inst{22-21} = nregs; let Inst{20} = 1; let Inst{19-16} = imm4; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_est_si sz, bits<2> nregs, RegisterOperand VecList, string asm, Operand immtype> { def NAME : sve_mem_est_si; def : InstAlias(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_est_ss sz, bits<2> nregs, RegisterOperand VecList, string asm, RegisterOperand gprty> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg, [$Rn, $Rm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rm; bits<5> Rn; bits<5> Zt; let Inst{31-25} = 0b1110010; let Inst{24-23} = sz; let Inst{22-21} = nregs; let Inst{20-16} = Rm; let Inst{15-13} = 0b011; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } class sve_mem_cst_ss_base dtype, string asm, RegisterOperand listty, RegisterOperand gprty> : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg, [$Rn, $Rm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rm; bits<5> Rn; bits<5> Zt; let Inst{31-25} = 0b1110010; let Inst{24-21} = dtype; let Inst{20-16} = Rm; let Inst{15-13} = 0b010; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_cst_ss dtype, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand gprty> { def NAME : sve_mem_cst_ss_base; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } class sve_mem_cstnt_si msz, string asm, RegisterOperand VecList> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zt; bits<4> imm4; let Inst{31-25} = 0b1110010; let Inst{24-23} = msz; let Inst{22-20} = 0b001; let Inst{19-16} = imm4; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_cstnt_si msz, string asm, RegisterOperand listty, ZPRRegOp zprty> { def NAME : sve_mem_cstnt_si; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; def : InstAlias(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_cstnt_ss_base msz, string asm, RegisterOperand listty, RegisterOperand gprty> : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg, [$Rn, $Rm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rm; bits<5> Rn; bits<5> Zt; let Inst{31-25} = 0b1110010; let Inst{24-23} = msz; let Inst{22-21} = 0b00; let Inst{20-16} = Rm; let Inst{15-13} = 0b011; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_cstnt_ss msz, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand gprty> { def NAME : sve_mem_cstnt_ss_base; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } class sve_mem_sst_sv opc, bit xs, bit scaled, string asm, RegisterOperand VecList, RegisterOperand zprext> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), asm, "\t$Zt, $Pg, [$Rn, $Zm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zm; bits<5> Zt; let Inst{31-25} = 0b1110010; let Inst{24-22} = opc; let Inst{21} = scaled; let Inst{20-16} = Zm; let Inst{15} = 0b1; let Inst{14} = xs; let Inst{13} = 0; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_sst_sv_32_scaled opc, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd > { def _UXTW_SCALED : sve_mem_sst_sv; def _SXTW_SCALED : sve_mem_sst_sv; def : InstAlias(NAME # _UXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; def : InstAlias(NAME # _SXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; } multiclass sve_mem_sst_sv_32_unscaled opc, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW : sve_mem_sst_sv; def _SXTW : sve_mem_sst_sv; def : InstAlias(NAME # _UXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; def : InstAlias(NAME # _SXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; } class sve_mem_sst_sv2 msz, bit scaled, string asm, RegisterOperand zprext> : I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), asm, "\t$Zt, $Pg, [$Rn, $Zm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zm; bits<5> Zt; let Inst{31-25} = 0b1110010; let Inst{24-23} = msz; let Inst{22} = 0b0; let Inst{21} = scaled; let Inst{20-16} = Zm; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_sst_sv_64_scaled msz, string asm, RegisterOperand zprext> { def "" : sve_mem_sst_sv2; def : InstAlias(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; } multiclass sve_mem_sst_sv_64_unscaled msz, string asm> { def "" : sve_mem_sst_sv2; def : InstAlias(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; } class sve_mem_sst_vi opc, string asm, ZPRRegOp zprty, RegisterOperand VecList, Operand imm_ty> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), asm, "\t$Zt, $Pg, [$Zn, $imm5]", "", []>, Sched<[]> { bits<3> Pg; bits<5> imm5; bits<5> Zn; bits<5> Zt; let Inst{31-25} = 0b1110010; let Inst{24-23} = opc{2-1}; let Inst{22} = 0b1; let Inst{21} = opc{0}; let Inst{20-16} = imm5; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_sst_vi_ptrs opc, string asm, RegisterOperand listty, ZPRRegOp zprty, Operand imm_ty> { def _IMM : sve_mem_sst_vi; def : InstAlias(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 0>; def : InstAlias(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 0>; def : InstAlias(NAME # _IMM) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 1>; } class sve_mem_z_spill : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9), asm, "\t$Zt, [$Rn, $imm9, mul vl]", "", []>, Sched<[]> { bits<5> Rn; bits<5> Zt; bits<9> imm9; let Inst{31-22} = 0b1110010110; let Inst{21-16} = imm9{8-3}; let Inst{15-13} = 0b010; let Inst{12-10} = imm9{2-0}; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayStore = 1; } multiclass sve_mem_z_spill { def NAME : sve_mem_z_spill; def : InstAlias(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>; } class sve_mem_p_spill : I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), asm, "\t$Pt, [$Rn, $imm9, mul vl]", "", []>, Sched<[]> { bits<4> Pt; bits<5> Rn; bits<9> imm9; let Inst{31-22} = 0b1110010110; let Inst{21-16} = imm9{8-3}; let Inst{15-13} = 0b000; let Inst{12-10} = imm9{2-0}; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = Pt; let mayStore = 1; } multiclass sve_mem_p_spill { def NAME : sve_mem_p_spill; def : InstAlias(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; } //===----------------------------------------------------------------------===// // SVE Permute - Predicates Group //===----------------------------------------------------------------------===// class sve_int_perm_bin_perm_pp opc, bits<2> sz8_64, string asm, PPRRegOp pprty> : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm), asm, "\t$Pd, $Pn, $Pm", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pm; bits<4> Pn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-20} = 0b10; let Inst{19-16} = Pm; let Inst{15-13} = 0b010; let Inst{12-10} = opc; let Inst{9} = 0b0; let Inst{8-5} = Pn; let Inst{4} = 0b0; let Inst{3-0} = Pd; } multiclass sve_int_perm_bin_perm_pp opc, string asm> { def _B : sve_int_perm_bin_perm_pp; def _H : sve_int_perm_bin_perm_pp; def _S : sve_int_perm_bin_perm_pp; def _D : sve_int_perm_bin_perm_pp; } class sve_int_perm_punpk : I<(outs PPR16:$Pd), (ins PPR8:$Pn), asm, "\t$Pd, $Pn", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pn; let Inst{31-17} = 0b000001010011000; let Inst{16} = opc; let Inst{15-9} = 0b0100000; let Inst{8-5} = Pn; let Inst{4} = 0b0; let Inst{3-0} = Pd; } class sve_int_rdffr_pred : I<(outs PPR8:$Pd), (ins PPRAny:$Pg), asm, "\t$Pd, $Pg/z", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pg; let Inst{31-23} = 0b001001010; let Inst{22} = s; let Inst{21-9} = 0b0110001111000; let Inst{8-5} = Pg; let Inst{4} = 0; let Inst{3-0} = Pd; let Defs = !if(!eq (s, 1), [NZCV], []); let Uses = [FFR]; } class sve_int_rdffr_unpred : I< (outs PPR8:$Pd), (ins), asm, "\t$Pd", "", []>, Sched<[]> { bits<4> Pd; let Inst{31-4} = 0b0010010100011001111100000000; let Inst{3-0} = Pd; let Uses = [FFR]; } class sve_int_wrffr : I<(outs), (ins PPR8:$Pn), asm, "\t$Pn", "", []>, Sched<[]> { bits<4> Pn; let Inst{31-9} = 0b00100101001010001001000; let Inst{8-5} = Pn; let Inst{4-0} = 0b00000; let hasSideEffects = 1; let Defs = [FFR]; } class sve_int_setffr : I<(outs), (ins), asm, "", "", []>, Sched<[]> { let Inst{31-0} = 0b00100101001011001001000000000000; let hasSideEffects = 1; let Defs = [FFR]; } //===----------------------------------------------------------------------===// // SVE Permute Vector - Predicated Group //===----------------------------------------------------------------------===// class sve_int_perm_clast_rz sz8_64, bit ab, string asm, ZPRRegOp zprty, RegisterClass rt> : I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm), asm, "\t$Rdn, $Pg, $_Rdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rdn; bits<5> Zm; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-17} = 0b11000; let Inst{16} = ab; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Rdn; let Constraints = "$Rdn = $_Rdn"; } multiclass sve_int_perm_clast_rz { def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>; def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>; def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>; def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>; } class sve_int_perm_clast_vz sz8_64, bit ab, string asm, ZPRRegOp zprty, RegisterClass rt> : I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm), asm, "\t$Vdn, $Pg, $_Vdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Vdn; bits<5> Zm; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-17} = 0b10101; let Inst{16} = ab; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Vdn; let Constraints = "$Vdn = $_Vdn"; } multiclass sve_int_perm_clast_vz { def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>; def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>; def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>; def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>; } class sve_int_perm_clast_zz sz8_64, bit ab, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), asm, "\t$Zdn, $Pg, $_Zdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Zm; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-17} = 0b10100; let Inst{16} = ab; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_perm_clast_zz { def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>; def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>; def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>; def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>; } class sve_int_perm_last_r sz8_64, bit ab, string asm, ZPRRegOp zprty, RegisterClass resultRegType> : I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Rd, $Pg, $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rd; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-17} = 0b10000; let Inst{16} = ab; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Rd; } multiclass sve_int_perm_last_r { def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>; def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>; def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>; def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>; } class sve_int_perm_last_v sz8_64, bit ab, string asm, ZPRRegOp zprty, RegisterClass dstRegtype> : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Vd, $Pg, $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Vd; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-17} = 0b10001; let Inst{16} = ab; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Vd; } multiclass sve_int_perm_last_v { def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>; def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>; def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>; def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>; } class sve_int_perm_splice sz8_64, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), asm, "\t$Zdn, $Pg, $_Zdn, $Zm", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zdn; bits<5> Zm; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-13} = 0b101100100; let Inst{12-10} = Pg; let Inst{9-5} = Zm; let Inst{4-0} = Zdn; let Constraints = "$Zdn = $_Zdn"; let DestructiveInstType = Destructive; let ElementSize = ElementSizeNone; } multiclass sve_int_perm_splice { def _B : sve_int_perm_splice<0b00, asm, ZPR8>; def _H : sve_int_perm_splice<0b01, asm, ZPR16>; def _S : sve_int_perm_splice<0b10, asm, ZPR32>; def _D : sve_int_perm_splice<0b11, asm, ZPR64>; } class sve_int_perm_rev sz8_64, bits<2> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> { bits<5> Zd; bits<3> Pg; bits<5> Zn; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-18} = 0b1001; let Inst{17-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; let Constraints = "$Zd = $_Zd"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_perm_rev_rbit { def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>; def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>; def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>; def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>; } multiclass sve_int_perm_rev_revb { def _H : sve_int_perm_rev<0b01, 0b00, asm, ZPR16>; def _S : sve_int_perm_rev<0b10, 0b00, asm, ZPR32>; def _D : sve_int_perm_rev<0b11, 0b00, asm, ZPR64>; } multiclass sve_int_perm_rev_revh { def _S : sve_int_perm_rev<0b10, 0b01, asm, ZPR32>; def _D : sve_int_perm_rev<0b11, 0b01, asm, ZPR64>; } multiclass sve_int_perm_rev_revw { def _D : sve_int_perm_rev<0b11, 0b10, asm, ZPR64>; } class sve_int_perm_cpy_r sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegType> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn), asm, "\t$Zd, $Pg/m, $Rn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zd; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-13} = 0b101000101; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zd; let Constraints = "$Zd = $_Zd"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_perm_cpy_r { def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>; def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>; def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>; def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>; def : InstAlias<"mov $Zd, $Pg/m, $Rn", (!cast(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Rn", (!cast(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Rn", (!cast(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Rn", (!cast(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>; } class sve_int_perm_cpy_v sz8_64, string asm, ZPRRegOp zprty, RegisterClass srcRegtype> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn), asm, "\t$Zd, $Pg/m, $Vn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Vn; bits<5> Zd; let Inst{31-24} = 0b00000101; let Inst{23-22} = sz8_64; let Inst{21-13} = 0b100000100; let Inst{12-10} = Pg; let Inst{9-5} = Vn; let Inst{4-0} = Zd; let Constraints = "$Zd = $_Zd"; let DestructiveInstType = Destructive; let ElementSize = zprty.ElementSize; } multiclass sve_int_perm_cpy_v { def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>; def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>; def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>; def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>; def : InstAlias<"mov $Zd, $Pg/m, $Vn", (!cast(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Vn", (!cast(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Vn", (!cast(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>; def : InstAlias<"mov $Zd, $Pg/m, $Vn", (!cast(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>; } class sve_int_perm_compact : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Zd, $Pg, $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zd; bits<5> Zn; let Inst{31-23} = 0b000001011; let Inst{22} = sz; let Inst{21-13} = 0b100001100; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_compact { def _S : sve_int_perm_compact<0b0, asm, ZPR32>; def _D : sve_int_perm_compact<0b1, asm, ZPR64>; } //===----------------------------------------------------------------------===// // SVE Memory - Contiguous Load Group //===----------------------------------------------------------------------===// class sve_mem_cld_si_base dtype, bit nf, string asm, RegisterOperand VecList> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zt; bits<4> imm4; let Inst{31-25} = 0b1010010; let Inst{24-21} = dtype; let Inst{20} = nf; let Inst{19-16} = imm4; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; let Uses = !if(!eq(nf, 1), [FFR], []); let Defs = !if(!eq(nf, 1), [FFR], []); } multiclass sve_mem_cld_si_base dtype, bit nf, string asm, RegisterOperand listty, ZPRRegOp zprty> { def _REAL : sve_mem_cld_si_base; def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } multiclass sve_mem_cld_si dtype, string asm, RegisterOperand listty, ZPRRegOp zprty> : sve_mem_cld_si_base; class sve_mem_cldnt_si_base msz, string asm, RegisterOperand VecList> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", "", []>, Sched<[]> { bits<5> Zt; bits<3> Pg; bits<5> Rn; bits<4> imm4; let Inst{31-25} = 0b1010010; let Inst{24-23} = msz; let Inst{22-20} = 0b000; let Inst{19-16} = imm4; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_cldnt_si msz, string asm, RegisterOperand listty, ZPRRegOp zprty> { def NAME : sve_mem_cldnt_si_base; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>; def : InstAlias(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_cldnt_ss_base msz, string asm, RegisterOperand VecList, RegisterOperand gprty> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rm; bits<5> Rn; bits<5> Zt; let Inst{31-25} = 0b1010010; let Inst{24-23} = msz; let Inst{22-21} = 0b00; let Inst{20-16} = Rm; let Inst{15-13} = 0b110; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_cldnt_ss msz, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand gprty> { def NAME : sve_mem_cldnt_ss_base; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } class sve_mem_ldqr_si sz, string asm, RegisterOperand VecList> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> { bits<5> Zt; bits<5> Rn; bits<3> Pg; bits<4> imm4; let Inst{31-25} = 0b1010010; let Inst{24-23} = sz; let Inst{22-20} = 0; let Inst{19-16} = imm4; let Inst{15-13} = 0b001; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_ldqr_si sz, string asm, RegisterOperand listty, ZPRRegOp zprty> { def NAME : sve_mem_ldqr_si; def : InstAlias(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>; } class sve_mem_ldqr_ss sz, string asm, RegisterOperand VecList, RegisterOperand gprty> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> { bits<5> Zt; bits<3> Pg; bits<5> Rn; bits<5> Rm; let Inst{31-25} = 0b1010010; let Inst{24-23} = sz; let Inst{22-21} = 0; let Inst{20-16} = Rm; let Inst{15-13} = 0; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_ldqr_ss sz, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand gprty> { def NAME : sve_mem_ldqr_ss; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } class sve_mem_ld_dup dtypeh, bits<2> dtypel, string asm, RegisterOperand VecList, Operand immtype> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), asm, "\t$Zt, $Pg/z, [$Rn, $imm6]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zt; bits<6> imm6; let Inst{31-25} = 0b1000010; let Inst{24-23} = dtypeh; let Inst{22} = 1; let Inst{21-16} = imm6; let Inst{15} = 0b1; let Inst{14-13} = dtypel; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_ld_dup dtypeh, bits<2> dtypel, string asm, RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> { def NAME : sve_mem_ld_dup; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>; def : InstAlias(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_cld_ss_base dtype, bit ff, dag iops, string asm, RegisterOperand VecList> : I<(outs VecList:$Zt), iops, asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> { bits<5> Zt; bits<3> Pg; bits<5> Rm; bits<5> Rn; let Inst{31-25} = 0b1010010; let Inst{24-21} = dtype; let Inst{20-16} = Rm; let Inst{15-14} = 0b01; let Inst{13} = ff; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; let Uses = !if(!eq(ff, 1), [FFR], []); let Defs = !if(!eq(ff, 1), [FFR], []); } multiclass sve_mem_cld_ss dtype, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand gprty> { def "" : sve_mem_cld_ss_base; def : InstAlias(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } multiclass sve_mem_cldff_ss dtype, string asm, RegisterOperand listty, ZPRRegOp zprty, RegisterOperand gprty> { def _REAL : sve_mem_cld_ss_base; def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>; def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>; } multiclass sve_mem_cldnf_si dtype, string asm, RegisterOperand listty, ZPRRegOp zprty> : sve_mem_cld_si_base; class sve_mem_eld_si sz, bits<2> nregs, RegisterOperand VecList, string asm, Operand immtype> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", "", []>, Sched<[]> { bits<5> Zt; bits<3> Pg; bits<5> Rn; bits<4> imm4; let Inst{31-25} = 0b1010010; let Inst{24-23} = sz; let Inst{22-21} = nregs; let Inst{20} = 0; let Inst{19-16} = imm4; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_eld_si sz, bits<2> nregs, RegisterOperand VecList, string asm, Operand immtype> { def NAME : sve_mem_eld_si; def : InstAlias(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_eld_ss sz, bits<2> nregs, RegisterOperand VecList, string asm, RegisterOperand gprty> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rm; bits<5> Rn; bits<5> Zt; let Inst{31-25} = 0b1010010; let Inst{24-23} = sz; let Inst{22-21} = nregs; let Inst{20-16} = Rm; let Inst{15-13} = 0b110; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } //===----------------------------------------------------------------------===// // SVE Memory - 32-bit Gather and Unsized Contiguous Group //===----------------------------------------------------------------------===// // bit xs is '1' if offsets are signed // bit scaled is '1' if the offsets are scaled class sve_mem_32b_gld_sv opc, bit xs, bit scaled, string asm, RegisterOperand zprext> : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zm; bits<5> Zt; let Inst{31-25} = 0b1000010; let Inst{24-23} = opc{3-2}; let Inst{22} = xs; let Inst{21} = scaled; let Inst{20-16} = Zm; let Inst{15} = 0b0; let Inst{14-13} = opc{1-0}; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; let Defs = !if(!eq(opc{0}, 1), [FFR], []); let Uses = !if(!eq(opc{0}, 1), [FFR], []); } multiclass sve_mem_32b_gld_sv_32_scaled opc, string asm, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv; def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv; def : InstAlias(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; def : InstAlias(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; } multiclass sve_mem_32b_gld_vs_32_unscaled opc, string asm, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW_REAL : sve_mem_32b_gld_sv; def _SXTW_REAL : sve_mem_32b_gld_sv; def : InstAlias(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; def : InstAlias(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; } class sve_mem_32b_gld_vi opc, string asm, Operand imm_ty> : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), asm, "\t$Zt, $Pg/z, [$Zn, $imm5]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zn; bits<5> Zt; bits<5> imm5; let Inst{31-25} = 0b1000010; let Inst{24-23} = opc{3-2}; let Inst{22-21} = 0b01; let Inst{20-16} = imm5; let Inst{15} = 0b1; let Inst{14-13} = opc{1-0}; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zt; let mayLoad = 1; let Defs = !if(!eq(opc{0}, 1), [FFR], []); let Uses = !if(!eq(opc{0}, 1), [FFR], []); } multiclass sve_mem_32b_gld_vi_32_ptrs opc, string asm, Operand imm_ty> { def _IMM_REAL : sve_mem_32b_gld_vi; def : InstAlias(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>; def : InstAlias(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>; def : InstAlias(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; } class sve_mem_prfm_si msz, string asm> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6), asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]", "", []>, Sched<[]> { bits<5> Rn; bits<3> Pg; bits<6> imm6; bits<4> prfop; let Inst{31-22} = 0b1000010111; let Inst{21-16} = imm6; let Inst{15} = 0b0; let Inst{14-13} = msz; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = prfop; let hasSideEffects = 1; } multiclass sve_mem_prfm_si msz, string asm> { def NAME : sve_mem_prfm_si; def : InstAlias(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } class sve_mem_prfm_ss opc, string asm, RegisterOperand gprty> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$prfop, $Pg, [$Rn, $Rm]", "", []>, Sched<[]> { bits<5> Rm; bits<5> Rn; bits<3> Pg; bits<4> prfop; let Inst{31-25} = 0b1000010; let Inst{24-23} = opc{2-1}; let Inst{22-21} = 0b00; let Inst{20-16} = Rm; let Inst{15} = 0b1; let Inst{14} = opc{0}; let Inst{13} = 0b0; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = prfop; let hasSideEffects = 1; } class sve_mem_32b_prfm_sv msz, bit xs, string asm, RegisterOperand zprext> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), asm, "\t$prfop, $Pg, [$Rn, $Zm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zm; bits<4> prfop; let Inst{31-23} = 0b100001000; let Inst{22} = xs; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15} = 0b0; let Inst{14-13} = msz; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = prfop; let hasSideEffects = 1; } multiclass sve_mem_32b_prfm_sv_scaled msz, string asm, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW_SCALED : sve_mem_32b_prfm_sv; def _SXTW_SCALED : sve_mem_32b_prfm_sv; } class sve_mem_32b_prfm_vi msz, string asm, Operand imm_ty> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), asm, "\t$prfop, $Pg, [$Zn, $imm5]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zn; bits<5> imm5; bits<4> prfop; let Inst{31-25} = 0b1000010; let Inst{24-23} = msz; let Inst{22-21} = 0b00; let Inst{20-16} = imm5; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = 0b0; let Inst{3-0} = prfop; } multiclass sve_mem_32b_prfm_vi msz, string asm, Operand imm_ty> { def NAME : sve_mem_32b_prfm_vi; def : InstAlias(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; } class sve_mem_z_fill : I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9), asm, "\t$Zt, [$Rn, $imm9, mul vl]", "", []>, Sched<[]> { bits<5> Rn; bits<5> Zt; bits<9> imm9; let Inst{31-22} = 0b1000010110; let Inst{21-16} = imm9{8-3}; let Inst{15-13} = 0b010; let Inst{12-10} = imm9{2-0}; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; } multiclass sve_mem_z_fill { def NAME : sve_mem_z_fill; def : InstAlias(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>; } class sve_mem_p_fill : I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), asm, "\t$Pt, [$Rn, $imm9, mul vl]", "", []>, Sched<[]> { bits<4> Pt; bits<5> Rn; bits<9> imm9; let Inst{31-22} = 0b1000010110; let Inst{21-16} = imm9{8-3}; let Inst{15-13} = 0b000; let Inst{12-10} = imm9{2-0}; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = Pt; let mayLoad = 1; } multiclass sve_mem_p_fill { def NAME : sve_mem_p_fill; def : InstAlias(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; } //===----------------------------------------------------------------------===// // SVE Memory - 64-bit Gather Group //===----------------------------------------------------------------------===// // bit xs is '1' if offsets are signed // bit scaled is '1' if the offsets are scaled // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) class sve_mem_64b_gld_sv opc, bit xs, bit scaled, bit lsl, string asm, RegisterOperand zprext> : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), asm, "\t$Zt, $Pg/z, [$Rn, $Zm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zm; bits<5> Zt; let Inst{31-25} = 0b1100010; let Inst{24-23} = opc{3-2}; let Inst{22} = xs; let Inst{21} = scaled; let Inst{20-16} = Zm; let Inst{15} = lsl; let Inst{14-13} = opc{1-0}; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; let mayLoad = 1; let Defs = !if(!eq(opc{0}, 1), [FFR], []); let Uses = !if(!eq(opc{0}, 1), [FFR], []); } multiclass sve_mem_64b_gld_sv_32_scaled opc, string asm, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv; def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv; def : InstAlias(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; def : InstAlias(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; } multiclass sve_mem_64b_gld_vs_32_unscaled opc, string asm, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW_REAL : sve_mem_64b_gld_sv; def _SXTW_REAL : sve_mem_64b_gld_sv; def : InstAlias(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; def : InstAlias(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; } multiclass sve_mem_64b_gld_sv2_64_scaled opc, string asm, RegisterOperand zprext> { def _SCALED_REAL : sve_mem_64b_gld_sv; def : InstAlias(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; } multiclass sve_mem_64b_gld_vs2_64_unscaled opc, string asm> { def _REAL : sve_mem_64b_gld_sv; def : InstAlias(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; } class sve_mem_64b_gld_vi opc, string asm, Operand imm_ty> : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), asm, "\t$Zt, $Pg/z, [$Zn, $imm5]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zn; bits<5> Zt; bits<5> imm5; let Inst{31-25} = 0b1100010; let Inst{24-23} = opc{3-2}; let Inst{22-21} = 0b01; let Inst{20-16} = imm5; let Inst{15} = 0b1; let Inst{14-13} = opc{1-0}; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zt; let mayLoad = 1; let Defs = !if(!eq(opc{0}, 1), [FFR], []); let Uses = !if(!eq(opc{0}, 1), [FFR], []); } multiclass sve_mem_64b_gld_vi_64_ptrs opc, string asm, Operand imm_ty> { def _IMM_REAL : sve_mem_64b_gld_vi; def : InstAlias(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>; def : InstAlias(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>; def : InstAlias(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; } // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) class sve_mem_64b_prfm_sv msz, bit xs, bit lsl, string asm, RegisterOperand zprext> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), asm, "\t$prfop, $Pg, [$Rn, $Zm]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Rn; bits<5> Zm; bits<4> prfop; let Inst{31-23} = 0b110001000; let Inst{22} = xs; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15} = lsl; let Inst{14-13} = msz; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4} = 0b0; let Inst{3-0} = prfop; let hasSideEffects = 1; } multiclass sve_mem_64b_prfm_sv_ext_scaled msz, string asm, RegisterOperand sxtw_opnd, RegisterOperand uxtw_opnd> { def _UXTW_SCALED : sve_mem_64b_prfm_sv; def _SXTW_SCALED : sve_mem_64b_prfm_sv; } multiclass sve_mem_64b_prfm_sv_lsl_scaled msz, string asm, RegisterOperand zprext> { def NAME : sve_mem_64b_prfm_sv; } class sve_mem_64b_prfm_vi msz, string asm, Operand imm_ty> : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), asm, "\t$prfop, $Pg, [$Zn, $imm5]", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zn; bits<5> imm5; bits<4> prfop; let Inst{31-25} = 0b1100010; let Inst{24-23} = msz; let Inst{22-21} = 0b00; let Inst{20-16} = imm5; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4} = 0b0; let Inst{3-0} = prfop; let hasSideEffects = 1; } multiclass sve_mem_64b_prfm_vi msz, string asm, Operand imm_ty> { def NAME : sve_mem_64b_prfm_vi; def : InstAlias(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; } //===----------------------------------------------------------------------===// // SVE Compute Vector Address Group //===----------------------------------------------------------------------===// class sve_int_bin_cons_misc_0_a opc, bits<2> msz, string asm, ZPRRegOp zprty, RegisterOperand zprext> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm), asm, "\t$Zd, [$Zn, $Zm]", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; bits<5> Zm; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-12} = 0b1010; let Inst{11-10} = msz; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_bin_cons_misc_0_a_uxtw opc, string asm> { def _0 : sve_int_bin_cons_misc_0_a; def _1 : sve_int_bin_cons_misc_0_a; def _2 : sve_int_bin_cons_misc_0_a; def _3 : sve_int_bin_cons_misc_0_a; } multiclass sve_int_bin_cons_misc_0_a_sxtw opc, string asm> { def _0 : sve_int_bin_cons_misc_0_a; def _1 : sve_int_bin_cons_misc_0_a; def _2 : sve_int_bin_cons_misc_0_a; def _3 : sve_int_bin_cons_misc_0_a; } multiclass sve_int_bin_cons_misc_0_a_32_lsl opc, string asm> { def _0 : sve_int_bin_cons_misc_0_a; def _1 : sve_int_bin_cons_misc_0_a; def _2 : sve_int_bin_cons_misc_0_a; def _3 : sve_int_bin_cons_misc_0_a; } multiclass sve_int_bin_cons_misc_0_a_64_lsl opc, string asm> { def _0 : sve_int_bin_cons_misc_0_a; def _1 : sve_int_bin_cons_misc_0_a; def _2 : sve_int_bin_cons_misc_0_a; def _3 : sve_int_bin_cons_misc_0_a; } //===----------------------------------------------------------------------===// // SVE Integer Misc - Unpredicated Group //===----------------------------------------------------------------------===// class sve_int_bin_cons_misc_0_b sz, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zm; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz; let Inst{21} = 0b1; let Inst{20-16} = Zm; let Inst{15-10} = 0b101100; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_bin_cons_misc_0_b { def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>; def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>; def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>; } class sve_int_bin_cons_misc_0_c opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn), asm, "\t$Zd, $Zn", "", []>, Sched<[]> { bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = opc{7-6}; let Inst{21} = 0b1; let Inst{20-16} = opc{5-1}; let Inst{15-11} = 0b10111; let Inst{10} = opc{0}; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } //===----------------------------------------------------------------------===// // SVE Integer Reduction Group //===----------------------------------------------------------------------===// class sve_int_reduce sz8_32, bits<2> fmt, bits<3> opc, string asm, ZPRRegOp zprty, RegisterClass regtype> : I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Vd, $Pg, $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Vd; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_32; let Inst{21} = 0b0; let Inst{20-19} = fmt; let Inst{18-16} = opc; let Inst{15-13} = 0b001; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Vd; } multiclass sve_int_reduce_0_saddv opc, string asm> { def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; } multiclass sve_int_reduce_0_uaddv opc, string asm> { def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>; } multiclass sve_int_reduce_1 opc, string asm> { def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>; def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>; def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>; def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>; } multiclass sve_int_reduce_2 opc, string asm> { def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>; def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>; def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>; def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>; } class sve_int_movprfx_pred sz8_32, bits<3> opc, string asm, ZPRRegOp zprty, string pg_suffix, dag iops> : I<(outs zprty:$Zd), iops, asm, "\t$Zd, $Pg"#pg_suffix#", $Zn", "", []>, Sched<[]> { bits<3> Pg; bits<5> Zd; bits<5> Zn; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_32; let Inst{21-19} = 0b010; let Inst{18-16} = opc; let Inst{15-13} = 0b001; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; let ElementSize = zprty.ElementSize; } multiclass sve_int_movprfx_pred_merge opc, string asm> { let Constraints = "$Zd = $_Zd" in { def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>; def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>; def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>; def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>; } } multiclass sve_int_movprfx_pred_zero opc, string asm> { def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z", (ins PPR3bAny:$Pg, ZPR8:$Zn)>; def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z", (ins PPR3bAny:$Pg, ZPR16:$Zn)>; def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z", (ins PPR3bAny:$Pg, ZPR32:$Zn)>; def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z", (ins PPR3bAny:$Pg, ZPR64:$Zn)>; } //===----------------------------------------------------------------------===// // SVE Propagate Break Group //===----------------------------------------------------------------------===// class sve_int_brkp opc, string asm> : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), asm, "\t$Pd, $Pg/z, $Pn, $Pm", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pg; bits<4> Pm; bits<4> Pn; let Inst{31-24} = 0b00100101; let Inst{23} = 0b0; let Inst{22} = opc{1}; let Inst{21-20} = 0b00; let Inst{19-16} = Pm; let Inst{15-14} = 0b11; let Inst{13-10} = Pg; let Inst{9} = 0b0; let Inst{8-5} = Pn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; let Defs = !if(!eq (opc{1}, 1), [NZCV], []); } //===----------------------------------------------------------------------===// // SVE Partition Break Group //===----------------------------------------------------------------------===// class sve_int_brkn : I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm), asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm", "", []>, Sched<[]> { bits<4> Pdm; bits<4> Pg; bits<4> Pn; let Inst{31-23} = 0b001001010; let Inst{22} = S; let Inst{21-14} = 0b01100001; let Inst{13-10} = Pg; let Inst{9} = 0b0; let Inst{8-5} = Pn; let Inst{4} = 0b0; let Inst{3-0} = Pdm; let Constraints = "$Pdm = $_Pdm"; let Defs = !if(!eq (S, 0b1), [NZCV], []); } class sve_int_break opc, string asm, string suffix, dag iops> : I<(outs PPR8:$Pd), iops, asm, "\t$Pd, $Pg"#suffix#", $Pn", "", []>, Sched<[]> { bits<4> Pd; bits<4> Pg; bits<4> Pn; let Inst{31-24} = 0b00100101; let Inst{23-22} = opc{2-1}; let Inst{21-14} = 0b01000001; let Inst{13-10} = Pg; let Inst{9} = 0b0; let Inst{8-5} = Pn; let Inst{4} = opc{0}; let Inst{3-0} = Pd; let Constraints = !if(!eq (opc{0}, 1), "$Pd = $_Pd", ""); let Defs = !if(!eq (opc{1}, 1), [NZCV], []); } multiclass sve_int_break_m opc, string asm> { def NAME : sve_int_break; } multiclass sve_int_break_z opc, string asm> { def NAME : sve_int_break; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARM-digit.td000064400000000000000000001673520072674642500236550ustar 00000000000000//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Target-independent interfaces which we are implementing //===----------------------------------------------------------------------===// include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // ARM Subtarget state. // def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", "Thumb mode">; def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", "true", "Use software floating " "point features.">; //===----------------------------------------------------------------------===// // ARM Subtarget features. // // Floating Point, HW Division and Neon Support def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", "Enable VFP2 instructions">; def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", "Enable VFP3 instructions", [FeatureVFP2]>; def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", "Enable NEON instructions", [FeatureVFP3]>; def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", "Enable half-precision " "floating point">; def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", "Enable VFP4 instructions", [FeatureVFP3, FeatureFP16]>; def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", "Enable ARMv8 FP", [FeatureVFP4]>; def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", "Enable full half-precision " "floating point", [FeatureFPARMv8]>; def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", "Floating point unit supports " "single precision only">; def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", "Restrict FP to 16 double registers">; def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb", "true", "Enable divide instructions in Thumb">; def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", "HasHardwareDivideInARM", "true", "Enable divide instructions in ARM mode">; // Atomic Support def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", "Has data barrier (dmb/dsb) instructions">; def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", "Has v7 clrex instruction">; def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", "Has full data barrier (dfb) instruction">; def FeatureAcquireRelease : SubtargetFeature<"acquire-release", "HasAcquireRelease", "true", "Has v8 acquire/release (lda/ldaex " " etc) instructions">; def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", "FP compare + branch is slow">; def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", "Enable support for Performance " "Monitor extensions">; // TrustZone Security Extensions def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", "Enable support for TrustZone " "security extensions">; def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", "Enable support for ARMv8-M " "Security Extensions">; def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", "Enable SHA1 and SHA256 support", [FeatureNEON]>; def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", "Enable AES support", [FeatureNEON]>; def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable support for " "Cryptography extensions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable support for CRC instructions">; def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", "Enable support for dot product instructions", [FeatureNEON]>; // Not to be confused with FeatureHasRetAddrStack (return address stack) def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", "Enable Reliability, Availability " "and Serviceability extensions">; // Fast computation of non-negative address offsets def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", "Enable fast computation of " "positive address offsets">; // Fast execution of AES crypto operations def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", "CPU fuses AES crypto operations">; // Fast execution of bottom and top halves of literal generation def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", "CPU fuses literal generation operations">; // The way of reading thread pointer def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", "Reading thread pointer from register">; // Cyclone can zero VFP registers in 0 cycles. def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", "Has zero-cycle zeroing instructions">; // Whether it is profitable to unpredicate certain instructions during if-conversion def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", "IsProfitableToUnpredicate", "true", "Is profitable to unpredicate">; // Some targets (e.g. Swift) have microcoded VGETLNi32. def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", "HasSlowVGETLNi32", "true", "Has slow VGETLNi32 - prefer VMOV">; // Some targets (e.g. Swift) have microcoded VDUP32. def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true", "Has slow VDUP32 - prefer VMOV">; // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON // for scalar FP, as this allows more effective execution domain optimization. def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", "true", "Prefer VMOVSR">; // Swift has ISHST barriers compatible with Atomic Release semantics but weaker // than ISH def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", "true", "Prefer ISHST barriers">; // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true", "Has muxed AGU and NEON/FPU">; // Whether VLDM/VSTM starting with odd register number need more microops // than single VLDRS def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", "true", "VLDM/VSTM starting " "with an odd register is slow">; // Some targets have a renaming dependency when loading into D subregisters. def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", "SlowLoadDSubregister", "true", "Loading into D subregs is slow">; // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", "DontWidenVMOVS", "true", "Don't widen VMOVS to VMOVD">; // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different // VFP register widths. def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", "SplatVFPToNeon", "true", "Splat register from VFP to NEON", [FeatureDontWidenVMOVS]>; // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true", "Expand VFP/NEON MLA/MLS instructions">; // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", "true", "Has VMLx hazards">; // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from // VFP to NEON, as an execution domain optimization. def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs", "true", "Convert VMOVSR, VMOVRS, " "VMOVS to NEON">; // Some processors benefit from using NEON instructions for scalar // single-precision FP operations. This affects instruction selection and should // only be enabled if the handling of denormals is not important. def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", "true", "Use NEON for single precision FP">; // On some processors, VLDn instructions that access unaligned data take one // extra cycle. Take that into account when computing operand latencies. def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", "true", "Check for VLDn unaligned access">; // Some processors have a nonpipelined VFP coprocessor. def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", "NonpipelinedVFP", "true", "VFP instructions are not pipelined">; // Some processors have FP multiply-accumulate instructions that don't // play nicely with other VFP / NEON instructions, and it's generally better // to just not use them. def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", "Disable VFP / NEON MAC instructions">; // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", "HasVMLxForwarding", "true", "Has multiplier accumulator forwarding">; // Disable 32-bit to 16-bit narrowing for experimentation. def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", "Prefer 32-bit Thumb instrs">; /// Some instructions update CPSR partially, which can add false dependency for /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is /// mapped to a separate physical register. Avoid partial CPSR update for these /// processors. def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", "AvoidCPSRPartialUpdate", "true", "Avoid CPSR partial update for OOO execution">; /// Disable +1 predication cost for instructions updating CPSR. /// Enabled for Cortex-A57. def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", "CheapPredicableCPSRDef", "true", "Disable +1 predication cost for instructions updating CPSR">; def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", "AvoidMOVsShifterOperand", "true", "Avoid movs instructions with " "shifter operand">; // Some processors perform return stack prediction. CodeGen should avoid issue // "normal" call instructions to callees which do not return. def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true", "Has return address stack">; // Some processors have no branch predictor, which changes the expected cost of // taking a branch which affects the choice of whether to use predicated // instructions. def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", "HasBranchPredictor", "false", "Has no branch predictor">; /// DSP extension. def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Supports DSP instructions in " "ARM and/or Thumb2">; // Multiprocessing extension. def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). def FeatureVirtualization : SubtargetFeature<"virtualization", "HasVirtualization", "true", "Supports Virtualization extension", [FeatureHWDivThumb, FeatureHWDivARM]>; // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. // See ARMInstrInfo.td for details. def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", "NaCl trap">; def FeatureStrictAlign : SubtargetFeature<"strict-align", "StrictAlign", "true", "Disallow all unaligned memory " "access">; def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", "Generate calls via indirect call " "instructions">; def FeatureExecuteOnly : SubtargetFeature<"execute-only", "GenExecuteOnly", "true", "Enable the generation of " "execute only code.">; def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", "Reserve R9, making it unavailable" " as GPR">; def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", "Don't use movt/movw pairs for " "32-bit imms">; def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", "NegativeImmediates", "false", "Convert immediates and instructions " "to their negated or complemented " "equivalent when the immediate does " "not fit in the encoding.">; // Use the MachineScheduler for instruction scheduling for the subtarget. def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", "Use the MachineScheduler">; def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", "DisablePostRAScheduler", "true", "Don't schedule again after register allocation">; // Enable use of alias analysis during code generation def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", "Use alias analysis during codegen">; //===----------------------------------------------------------------------===// // ARM architecture class // // A-series ISA def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", "Is application profile ('A' series)">; // R-series ISA def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", "Is realtime profile ('R' series)">; // M-series ISA def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", "Is microcontroller profile ('M' series)">; def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", "Does not support ARM mode execution">; //===----------------------------------------------------------------------===// // ARM ISAa. // def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "Support ARM v4T instructions">; def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", "Support ARM v5T instructions", [HasV4TOps]>; def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", "Support ARM v5TE, v5TEj, and " "v5TExp instructions", [HasV5TOps]>; def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", "Support ARM v6 instructions", [HasV5TEOps]>; def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", "Support ARM v6M instructions", [HasV6Ops]>; def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", "Support ARM v8M Baseline instructions", [HasV6MOps]>; def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", "Support ARM v6k instructions", [HasV6Ops]>; def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", "Support ARM v6t2 instructions", [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", "Support ARM v7 instructions", [HasV6T2Ops, FeaturePerfMon, FeatureV7Clrex]>; def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", "Support ARM v8M Mainline instructions", [HasV7Ops]>; def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", "Support ARM v8 instructions", [HasV7Ops, FeatureAcquireRelease]>; def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", "Support ARM v8.1a instructions", [HasV8Ops]>; def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", "Support ARM v8.2a instructions", [HasV8_1aOps]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", "Support ARM v8.3a instructions", [HasV8_2aOps]>; def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", "Cortex-A5 ARM processors", []>; def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", "Cortex-A7 ARM processors", []>; def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", "Cortex-A8 ARM processors", []>; def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", "Cortex-A9 ARM processors", []>; def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", "Cortex-A12 ARM processors", []>; def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", "Cortex-A15 ARM processors", []>; def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", "Cortex-A17 ARM processors", []>; def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", "Cortex-A32 ARM processors", []>; def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors", []>; def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", []>; def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", "Cortex-A55 ARM processors", []>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", []>; def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", []>; def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", []>; def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", "Cortex-A75 ARM processors", []>; def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", "Qualcomm Krait processors", []>; def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", "Qualcomm Kryo processors", []>; def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", "Swift ARM processors", []>; def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", "Samsung Exynos-Mx processors", []>; def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", "Cortex-R4 ARM processors", []>; def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", []>; def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", "Cortex-R7 ARM processors", []>; def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", "Cortex-R52 ARM processors", []>; def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", "Cortex-M3 ARM processors", []>; //===----------------------------------------------------------------------===// // ARM Helper classes. // class Architecture features> : SubtargetFeature; class ProcNoItin Features> : Processor; //===----------------------------------------------------------------------===// // ARM architectures // def ARMv2 : Architecture<"armv2", "ARMv2", []>; def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; def ARMv3 : Architecture<"armv3", "ARMv3", []>; def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; def ARMv4 : Architecture<"armv4", "ARMv4", []>; def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, FeatureDSP]>; def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, FeatureDSP]>; def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, FeatureTrustZone]>; def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass, FeatureStrictAlign]>; def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass, FeatureStrictAlign]>; def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureAClass]>; def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureAClass]>; def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, FeatureDB, FeatureDSP, FeatureHWDivThumb, FeatureRClass]>; def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass]>; def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass, FeatureDSP]>; def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC]>; def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC]>; def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS]>; def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS]>; def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS, FeatureDotProd]>; def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, FeatureDFB, FeatureDSP, FeatureCRC, FeatureMP, FeatureVirtualization, FeatureFPARMv8, FeatureNEON]>; def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", [HasV8MBaselineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureV7Clrex, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass, FeatureStrictAlign]>; def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", [HasV8MMainlineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass]>; // Aliases def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; //===----------------------------------------------------------------------===// // ARM schedules. //===----------------------------------------------------------------------===// // include "ARMSchedule.td" //===----------------------------------------------------------------------===// // ARM processors // // Dummy CPU, used to target architectures def : ProcessorModel<"generic", CortexA8Model, []>; // FIXME: Several processors below are not using their own scheduler // model, but one of similar/previous processor. These should be fixed. def : ProcNoItin<"arm8", [ARMv4]>; def : ProcNoItin<"arm810", [ARMv4]>; def : ProcNoItin<"strongarm", [ARMv4]>; def : ProcNoItin<"strongarm110", [ARMv4]>; def : ProcNoItin<"strongarm1100", [ARMv4]>; def : ProcNoItin<"strongarm1110", [ARMv4]>; def : ProcNoItin<"arm7tdmi", [ARMv4t]>; def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; def : ProcNoItin<"arm710t", [ARMv4t]>; def : ProcNoItin<"arm720t", [ARMv4t]>; def : ProcNoItin<"arm9", [ARMv4t]>; def : ProcNoItin<"arm9tdmi", [ARMv4t]>; def : ProcNoItin<"arm920", [ARMv4t]>; def : ProcNoItin<"arm920t", [ARMv4t]>; def : ProcNoItin<"arm922t", [ARMv4t]>; def : ProcNoItin<"arm940t", [ARMv4t]>; def : ProcNoItin<"ep9312", [ARMv4t]>; def : ProcNoItin<"arm10tdmi", [ARMv5t]>; def : ProcNoItin<"arm1020t", [ARMv5t]>; def : ProcNoItin<"arm9e", [ARMv5te]>; def : ProcNoItin<"arm926ej-s", [ARMv5te]>; def : ProcNoItin<"arm946e-s", [ARMv5te]>; def : ProcNoItin<"arm966e-s", [ARMv5te]>; def : ProcNoItin<"arm968e-s", [ARMv5te]>; def : ProcNoItin<"arm10e", [ARMv5te]>; def : ProcNoItin<"arm1020e", [ARMv5te]>; def : ProcNoItin<"arm1022e", [ARMv5te]>; def : ProcNoItin<"xscale", [ARMv5te]>; def : ProcNoItin<"iwmmxt", [ARMv5te]>; def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4]>; def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4, FeatureVirtualization]>; def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, FeatureHasRetAddrStack, FeatureNonpipelinedVFP, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding]>; def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, FeatureHasRetAddrStack, FeatureTrustZone, FeatureHasVMLxHazards, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureExpandMLx, FeaturePreferVMOVSR, FeatureMuxedUnits, FeatureNEONForFPMovs, FeatureCheckVLDnAlign, FeatureMP]>; def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, FeatureHasRetAddrStack, FeatureTrustZone, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization, FeatureMP]>; def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, FeatureDontWidenVMOVS, FeatureSplatVFPToNeon, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureTrustZone, FeatureVFP4, FeatureMP, FeatureCheckVLDnAlign, FeatureAvoidPartialCPSR, FeatureVirtualization]>; def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, FeatureHasRetAddrStack, FeatureTrustZone, FeatureMP, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization]>; // FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureCheckVLDnAlign, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureVFP4, FeatureHWDivThumb, FeatureHWDivARM]>; def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureHasVMLxHazards, FeatureProfUnpredicate, FeaturePrefISHSTBarrier, FeatureSlowOddRegister, FeatureSlowLoadDSubreg, FeatureSlowVGETLNi32, FeatureSlowVDUP32, FeatureUseMISched, FeatureNoPostRASched]>; def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVFP3, FeatureD16, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m, ProcM3, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m, ProcM3, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em, FeatureVFP4, FeatureVFPOnlySP, FeatureD16, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-m7", [ARMv7em, FeatureFPARMv8, FeatureD16]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, FeatureNoMovt]>; def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline, FeatureDSP, FeatureFPARMv8, FeatureD16, FeatureVFPOnlySP, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-a32", [ARMv8a, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO]>; def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO, FeatureAvoidPartialCPSR, FeatureCheapPredicableCPSR]>; def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd]>; def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureCrypto, FeatureUseMISched, FeatureZCZeroing, FeatureNoPostRASched]>; def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m4", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureUseMISched, FeatureFPAO, FeatureUseAA]>; //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// include "ARMRegisterInfo-digit.td" include "ARMRegisterBanks.td" include "ARMCallingConv.td" //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// include "ARMInstrInfo.td" def ARMInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===// def ARMAsmWriter : AsmWriter { string AsmWriterClassName = "InstPrinter"; int PassSubtarget = 1; int Variant = 0; bit isMCAsmWriter = 1; } def ARMAsmParser : AsmParser { bit ReportMultipleNearMisses = 1; } def ARMAsmParserVariant : AsmParserVariant { int Variant = 0; string Name = "ARM"; string BreakCharacters = "."; } def ARM : Target { // Pull in Instruction Info. let InstructionSet = ARMInstrInfo; let AssemblyWriters = [ARMAsmWriter]; let AssemblyParsers = [ARMAsmParser]; let AssemblyParserVariants = [ARMAsmParserVariant]; let AllowRegisterRenaming = 1; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARM.td000064400000000000000000001673440072674642500225600ustar 00000000000000//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Target-independent interfaces which we are implementing //===----------------------------------------------------------------------===// include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // ARM Subtarget state. // def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", "Thumb mode">; def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", "true", "Use software floating " "point features.">; //===----------------------------------------------------------------------===// // ARM Subtarget features. // // Floating Point, HW Division and Neon Support def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", "Enable VFP2 instructions">; def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", "Enable VFP3 instructions", [FeatureVFP2]>; def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", "Enable NEON instructions", [FeatureVFP3]>; def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", "Enable half-precision " "floating point">; def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", "Enable VFP4 instructions", [FeatureVFP3, FeatureFP16]>; def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", "Enable ARMv8 FP", [FeatureVFP4]>; def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", "Enable full half-precision " "floating point", [FeatureFPARMv8]>; def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", "Floating point unit supports " "single precision only">; def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", "Restrict FP to 16 double registers">; def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb", "true", "Enable divide instructions in Thumb">; def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", "HasHardwareDivideInARM", "true", "Enable divide instructions in ARM mode">; // Atomic Support def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", "Has data barrier (dmb/dsb) instructions">; def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", "Has v7 clrex instruction">; def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", "Has full data barrier (dfb) instruction">; def FeatureAcquireRelease : SubtargetFeature<"acquire-release", "HasAcquireRelease", "true", "Has v8 acquire/release (lda/ldaex " " etc) instructions">; def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", "FP compare + branch is slow">; def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", "Enable support for Performance " "Monitor extensions">; // TrustZone Security Extensions def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", "Enable support for TrustZone " "security extensions">; def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", "Enable support for ARMv8-M " "Security Extensions">; def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", "Enable SHA1 and SHA256 support", [FeatureNEON]>; def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", "Enable AES support", [FeatureNEON]>; def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable support for " "Cryptography extensions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable support for CRC instructions">; def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", "Enable support for dot product instructions", [FeatureNEON]>; // Not to be confused with FeatureHasRetAddrStack (return address stack) def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", "Enable Reliability, Availability " "and Serviceability extensions">; // Fast computation of non-negative address offsets def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", "Enable fast computation of " "positive address offsets">; // Fast execution of AES crypto operations def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", "CPU fuses AES crypto operations">; // Fast execution of bottom and top halves of literal generation def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", "CPU fuses literal generation operations">; // The way of reading thread pointer def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", "Reading thread pointer from register">; // Cyclone can zero VFP registers in 0 cycles. def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", "Has zero-cycle zeroing instructions">; // Whether it is profitable to unpredicate certain instructions during if-conversion def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", "IsProfitableToUnpredicate", "true", "Is profitable to unpredicate">; // Some targets (e.g. Swift) have microcoded VGETLNi32. def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", "HasSlowVGETLNi32", "true", "Has slow VGETLNi32 - prefer VMOV">; // Some targets (e.g. Swift) have microcoded VDUP32. def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true", "Has slow VDUP32 - prefer VMOV">; // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON // for scalar FP, as this allows more effective execution domain optimization. def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", "true", "Prefer VMOVSR">; // Swift has ISHST barriers compatible with Atomic Release semantics but weaker // than ISH def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", "true", "Prefer ISHST barriers">; // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true", "Has muxed AGU and NEON/FPU">; // Whether VLDM/VSTM starting with odd register number need more microops // than single VLDRS def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", "true", "VLDM/VSTM starting " "with an odd register is slow">; // Some targets have a renaming dependency when loading into D subregisters. def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", "SlowLoadDSubregister", "true", "Loading into D subregs is slow">; // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", "DontWidenVMOVS", "true", "Don't widen VMOVS to VMOVD">; // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different // VFP register widths. def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", "SplatVFPToNeon", "true", "Splat register from VFP to NEON", [FeatureDontWidenVMOVS]>; // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true", "Expand VFP/NEON MLA/MLS instructions">; // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", "true", "Has VMLx hazards">; // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from // VFP to NEON, as an execution domain optimization. def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs", "true", "Convert VMOVSR, VMOVRS, " "VMOVS to NEON">; // Some processors benefit from using NEON instructions for scalar // single-precision FP operations. This affects instruction selection and should // only be enabled if the handling of denormals is not important. def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", "true", "Use NEON for single precision FP">; // On some processors, VLDn instructions that access unaligned data take one // extra cycle. Take that into account when computing operand latencies. def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", "true", "Check for VLDn unaligned access">; // Some processors have a nonpipelined VFP coprocessor. def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", "NonpipelinedVFP", "true", "VFP instructions are not pipelined">; // Some processors have FP multiply-accumulate instructions that don't // play nicely with other VFP / NEON instructions, and it's generally better // to just not use them. def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", "Disable VFP / NEON MAC instructions">; // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", "HasVMLxForwarding", "true", "Has multiplier accumulator forwarding">; // Disable 32-bit to 16-bit narrowing for experimentation. def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", "Prefer 32-bit Thumb instrs">; /// Some instructions update CPSR partially, which can add false dependency for /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is /// mapped to a separate physical register. Avoid partial CPSR update for these /// processors. def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", "AvoidCPSRPartialUpdate", "true", "Avoid CPSR partial update for OOO execution">; /// Disable +1 predication cost for instructions updating CPSR. /// Enabled for Cortex-A57. def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", "CheapPredicableCPSRDef", "true", "Disable +1 predication cost for instructions updating CPSR">; def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", "AvoidMOVsShifterOperand", "true", "Avoid movs instructions with " "shifter operand">; // Some processors perform return stack prediction. CodeGen should avoid issue // "normal" call instructions to callees which do not return. def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true", "Has return address stack">; // Some processors have no branch predictor, which changes the expected cost of // taking a branch which affects the choice of whether to use predicated // instructions. def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", "HasBranchPredictor", "false", "Has no branch predictor">; /// DSP extension. def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Supports DSP instructions in " "ARM and/or Thumb2">; // Multiprocessing extension. def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). def FeatureVirtualization : SubtargetFeature<"virtualization", "HasVirtualization", "true", "Supports Virtualization extension", [FeatureHWDivThumb, FeatureHWDivARM]>; // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. // See ARMInstrInfo.td for details. def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", "NaCl trap">; def FeatureStrictAlign : SubtargetFeature<"strict-align", "StrictAlign", "true", "Disallow all unaligned memory " "access">; def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", "Generate calls via indirect call " "instructions">; def FeatureExecuteOnly : SubtargetFeature<"execute-only", "GenExecuteOnly", "true", "Enable the generation of " "execute only code.">; def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", "Reserve R9, making it unavailable" " as GPR">; def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", "Don't use movt/movw pairs for " "32-bit imms">; def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", "NegativeImmediates", "false", "Convert immediates and instructions " "to their negated or complemented " "equivalent when the immediate does " "not fit in the encoding.">; // Use the MachineScheduler for instruction scheduling for the subtarget. def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", "Use the MachineScheduler">; def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", "DisablePostRAScheduler", "true", "Don't schedule again after register allocation">; // Enable use of alias analysis during code generation def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", "Use alias analysis during codegen">; //===----------------------------------------------------------------------===// // ARM architecture class // // A-series ISA def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", "Is application profile ('A' series)">; // R-series ISA def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", "Is realtime profile ('R' series)">; // M-series ISA def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", "Is microcontroller profile ('M' series)">; def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", "Does not support ARM mode execution">; //===----------------------------------------------------------------------===// // ARM ISAa. // def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "Support ARM v4T instructions">; def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", "Support ARM v5T instructions", [HasV4TOps]>; def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", "Support ARM v5TE, v5TEj, and " "v5TExp instructions", [HasV5TOps]>; def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", "Support ARM v6 instructions", [HasV5TEOps]>; def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", "Support ARM v6M instructions", [HasV6Ops]>; def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", "Support ARM v8M Baseline instructions", [HasV6MOps]>; def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", "Support ARM v6k instructions", [HasV6Ops]>; def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", "Support ARM v6t2 instructions", [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", "Support ARM v7 instructions", [HasV6T2Ops, FeaturePerfMon, FeatureV7Clrex]>; def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", "Support ARM v8M Mainline instructions", [HasV7Ops]>; def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", "Support ARM v8 instructions", [HasV7Ops, FeatureAcquireRelease]>; def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", "Support ARM v8.1a instructions", [HasV8Ops]>; def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", "Support ARM v8.2a instructions", [HasV8_1aOps]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", "Support ARM v8.3a instructions", [HasV8_2aOps]>; def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", "Cortex-A5 ARM processors", []>; def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", "Cortex-A7 ARM processors", []>; def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", "Cortex-A8 ARM processors", []>; def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", "Cortex-A9 ARM processors", []>; def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", "Cortex-A12 ARM processors", []>; def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", "Cortex-A15 ARM processors", []>; def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", "Cortex-A17 ARM processors", []>; def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", "Cortex-A32 ARM processors", []>; def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors", []>; def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", []>; def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", "Cortex-A55 ARM processors", []>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", []>; def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", []>; def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", []>; def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", "Cortex-A75 ARM processors", []>; def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", "Qualcomm Krait processors", []>; def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", "Qualcomm Kryo processors", []>; def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", "Swift ARM processors", []>; def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", "Samsung Exynos-Mx processors", []>; def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", "Cortex-R4 ARM processors", []>; def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", []>; def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", "Cortex-R7 ARM processors", []>; def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", "Cortex-R52 ARM processors", []>; def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", "Cortex-M3 ARM processors", []>; //===----------------------------------------------------------------------===// // ARM Helper classes. // class Architecture features> : SubtargetFeature; class ProcNoItin Features> : Processor; //===----------------------------------------------------------------------===// // ARM architectures // def ARMv2 : Architecture<"armv2", "ARMv2", []>; def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; def ARMv3 : Architecture<"armv3", "ARMv3", []>; def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; def ARMv4 : Architecture<"armv4", "ARMv4", []>; def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, FeatureDSP]>; def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, FeatureDSP]>; def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, FeatureTrustZone]>; def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass, FeatureStrictAlign]>; def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass, FeatureStrictAlign]>; def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureAClass]>; def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureAClass]>; def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, FeatureDB, FeatureDSP, FeatureHWDivThumb, FeatureRClass]>; def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass]>; def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass, FeatureDSP]>; def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC]>; def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC]>; def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS]>; def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS]>; def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS, FeatureDotProd]>; def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, FeatureDFB, FeatureDSP, FeatureCRC, FeatureMP, FeatureVirtualization, FeatureFPARMv8, FeatureNEON]>; def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", [HasV8MBaselineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureV7Clrex, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass, FeatureStrictAlign]>; def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", [HasV8MMainlineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass]>; // Aliases def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; //===----------------------------------------------------------------------===// // ARM schedules. //===----------------------------------------------------------------------===// // include "ARMSchedule.td" //===----------------------------------------------------------------------===// // ARM processors // // Dummy CPU, used to target architectures def : ProcessorModel<"generic", CortexA8Model, []>; // FIXME: Several processors below are not using their own scheduler // model, but one of similar/previous processor. These should be fixed. def : ProcNoItin<"arm8", [ARMv4]>; def : ProcNoItin<"arm810", [ARMv4]>; def : ProcNoItin<"strongarm", [ARMv4]>; def : ProcNoItin<"strongarm110", [ARMv4]>; def : ProcNoItin<"strongarm1100", [ARMv4]>; def : ProcNoItin<"strongarm1110", [ARMv4]>; def : ProcNoItin<"arm7tdmi", [ARMv4t]>; def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; def : ProcNoItin<"arm710t", [ARMv4t]>; def : ProcNoItin<"arm720t", [ARMv4t]>; def : ProcNoItin<"arm9", [ARMv4t]>; def : ProcNoItin<"arm9tdmi", [ARMv4t]>; def : ProcNoItin<"arm920", [ARMv4t]>; def : ProcNoItin<"arm920t", [ARMv4t]>; def : ProcNoItin<"arm922t", [ARMv4t]>; def : ProcNoItin<"arm940t", [ARMv4t]>; def : ProcNoItin<"ep9312", [ARMv4t]>; def : ProcNoItin<"arm10tdmi", [ARMv5t]>; def : ProcNoItin<"arm1020t", [ARMv5t]>; def : ProcNoItin<"arm9e", [ARMv5te]>; def : ProcNoItin<"arm926ej-s", [ARMv5te]>; def : ProcNoItin<"arm946e-s", [ARMv5te]>; def : ProcNoItin<"arm966e-s", [ARMv5te]>; def : ProcNoItin<"arm968e-s", [ARMv5te]>; def : ProcNoItin<"arm10e", [ARMv5te]>; def : ProcNoItin<"arm1020e", [ARMv5te]>; def : ProcNoItin<"arm1022e", [ARMv5te]>; def : ProcNoItin<"xscale", [ARMv5te]>; def : ProcNoItin<"iwmmxt", [ARMv5te]>; def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4]>; def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4, FeatureVirtualization]>; def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, FeatureHasRetAddrStack, FeatureNonpipelinedVFP, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding]>; def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, FeatureHasRetAddrStack, FeatureTrustZone, FeatureHasVMLxHazards, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureExpandMLx, FeaturePreferVMOVSR, FeatureMuxedUnits, FeatureNEONForFPMovs, FeatureCheckVLDnAlign, FeatureMP]>; def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, FeatureHasRetAddrStack, FeatureTrustZone, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization, FeatureMP]>; def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, FeatureDontWidenVMOVS, FeatureSplatVFPToNeon, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureTrustZone, FeatureVFP4, FeatureMP, FeatureCheckVLDnAlign, FeatureAvoidPartialCPSR, FeatureVirtualization]>; def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, FeatureHasRetAddrStack, FeatureTrustZone, FeatureMP, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization]>; // FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureCheckVLDnAlign, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureVFP4, FeatureHWDivThumb, FeatureHWDivARM]>; def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureHasVMLxHazards, FeatureProfUnpredicate, FeaturePrefISHSTBarrier, FeatureSlowOddRegister, FeatureSlowLoadDSubreg, FeatureSlowVGETLNi32, FeatureSlowVDUP32, FeatureUseMISched, FeatureNoPostRASched]>; def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVFP3, FeatureD16, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, FeatureHasRetAddrStack, FeatureVFP3, FeatureD16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m, ProcM3, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m, ProcM3, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em, FeatureVFP4, FeatureVFPOnlySP, FeatureD16, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-m7", [ARMv7em, FeatureFPARMv8, FeatureD16]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, FeatureNoMovt]>; def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline, FeatureDSP, FeatureFPARMv8, FeatureD16, FeatureVFPOnlySP, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-a32", [ARMv8a, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO]>; def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO, FeatureAvoidPartialCPSR, FeatureCheapPredicableCPSR]>; def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd]>; def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureCrypto, FeatureUseMISched, FeatureZCZeroing, FeatureNoPostRASched]>; def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m4", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureUseMISched, FeatureFPAO, FeatureUseAA]>; //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// include "ARMRegisterInfo.td" include "ARMRegisterBanks.td" include "ARMCallingConv.td" //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// include "ARMInstrInfo.td" def ARMInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===// def ARMAsmWriter : AsmWriter { string AsmWriterClassName = "InstPrinter"; int PassSubtarget = 1; int Variant = 0; bit isMCAsmWriter = 1; } def ARMAsmParser : AsmParser { bit ReportMultipleNearMisses = 1; } def ARMAsmParserVariant : AsmParserVariant { int Variant = 0; string Name = "ARM"; string BreakCharacters = "."; } def ARM : Target { // Pull in Instruction Info. let InstructionSet = ARMInstrInfo; let AssemblyWriters = [ARMAsmWriter]; let AssemblyParsers = [ARMAsmParser]; let AssemblyParserVariants = [ARMAsmParserVariant]; let AllowRegisterRenaming = 1; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARMCallingConv.td000064400000000000000000000327250072674642500246720ustar 00000000000000//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // This describes the calling conventions for ARM architecture. //===----------------------------------------------------------------------===// /// CCIfAlign - Match of the original alignment of the arg class CCIfAlign: CCIf; //===----------------------------------------------------------------------===// // ARM APCS Calling Convention //===----------------------------------------------------------------------===// def CC_ARM_APCS : CallingConv<[ // Handles byval parameters. CCIfByVal>, CCIfType<[i1, i8, i16], CCPromoteToType>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is passed in R8. CCIfSwiftError>>, // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, CCIfType<[f32], CCBitConvertToType>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i32], CCAssignToStack<4, 4>>, CCIfType<[f64], CCAssignToStack<8, 4>>, CCIfType<[v2f64], CCAssignToStack<16, 4>> ]>; def RetCC_ARM_APCS : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[f32], CCBitConvertToType>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is returned in R8. CCIfSwiftError>>, // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> ]>; //===----------------------------------------------------------------------===// // ARM APCS Calling Convention for FastCC (when VFP2 or later is available) //===----------------------------------------------------------------------===// def FastCC_ARM_APCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15]>>, // CPRCs may be allocated to co-processor registers or the stack - they // may never be allocated to core registers. CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, CCDelegateTo ]>; def RetFastCC_ARM_APCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15]>>, CCDelegateTo ]>; //===----------------------------------------------------------------------===// // ARM APCS Calling Convention for GHC //===----------------------------------------------------------------------===// def CC_ARM_APCS_GHC : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType>, CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, // Promote i8/i16 arguments to i32. CCIfType<[i8, i16], CCPromoteToType>, // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> ]>; //===----------------------------------------------------------------------===// // ARM AAPCS (EABI) Calling Convention, common parts //===----------------------------------------------------------------------===// def CC_ARM_AAPCS_Common : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, // i64/f64 is passed in even pairs of GPRs // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register // (and the same is true for f64 if VFP is not enabled) CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8", CCAssignToReg<[R0, R1, R2, R3]>>>, CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>, CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>, CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, CCIfType<[v2f64], CCIfAlign<"16", CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>, CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> ]>; def RetCC_ARM_AAPCS_Common : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> ]>; //===----------------------------------------------------------------------===// // ARM AAPCS (EABI) Calling Convention //===----------------------------------------------------------------------===// def CC_ARM_AAPCS : CallingConv<[ // Handles byval parameters. CCIfByVal>, // The 'nest' parameter, if any, is passed in R12. CCIfNest>, // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is passed in R8. CCIfSwiftError>>, CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, CCIfType<[f32], CCBitConvertToType>, CCDelegateTo ]>; def RetCC_ARM_AAPCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v8f16,v16i8, v4f32], CCBitConvertToType>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is returned in R8. CCIfSwiftError>>, CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, CCIfType<[f32], CCBitConvertToType>, CCDelegateTo ]>; //===----------------------------------------------------------------------===// // ARM AAPCS-VFP (EABI) Calling Convention // Also used for FastCC (when VFP2 or later is available) //===----------------------------------------------------------------------===// def CC_ARM_AAPCS_VFP : CallingConv<[ // Handles byval parameters. CCIfByVal>, // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is passed in R8. CCIfSwiftError>>, // HFAs are passed in a contiguous block of registers, or on the stack CCIfConsecutiveRegs>, CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15]>>, CCDelegateTo ]>; def RetCC_ARM_AAPCS_VFP : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType>, CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType>, // Pass SwiftSelf in a callee saved register. CCIfSwiftSelf>>, // A SwiftError is returned in R8. CCIfSwiftError>>, CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15]>>, CCDelegateTo ]>; //===----------------------------------------------------------------------===// // Callee-saved register lists. //===----------------------------------------------------------------------===// def CSR_NoRegs : CalleeSavedRegs<(add)>; def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>; def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, (sequence "D%u", 15, 8))>; // R8 is used to pass swifterror, remove it from CSR. def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>; // The order of callee-saved registers needs to match the order we actually push // them in FrameLowering, because this order is what's used by // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame // pointer, we use this AAPCS alternative. def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4, R11, R10, R9, R8, (sequence "D%u", 15, 8))>; // R8 is used to pass swifterror, remove it from CSR. def CSR_AAPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS_SplitPush, R8)>; // Constructors and destructors return 'this' in the ARM C++ ABI; since 'this' // and the pointer return value are both passed in R0 in these cases, this can // be partially modelled by treating R0 as a callee-saved register // Only the resulting RegMask is used; the SaveList is ignored def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, (sequence "D%u", 15, 8), R0)>; // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. // Also save R7-R4 first to match the stack frame fixed spill areas. def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; // R8 is used to pass swifterror, remove it from CSR. def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>; def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS_ThisReturn, R9))>; def CSR_iOS_TLSCall : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12), (sequence "D%u", 31, 0))>; // C++ TLS access function saves all registers except SP. Try to match // the order of CSRs in CSR_iOS. def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1), (sequence "D%u", 31, 0))>; // CSRs that are handled by prologue, epilogue. def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>; // CSRs that are handled explicitly via copies. def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS, CSR_iOS_CXX_TLS_PE)>; // The "interrupt" attribute is used to generate code that is acceptable in // exception-handlers of various kinds. It makes us use a different return // instruction (handled elsewhere) and affects which registers we must return to // our "caller" in the same state as we receive them. // For most interrupts, all registers except SP and LR are shared with // user-space. We mark LR to be saved anyway, since this is what the ARM backend // generally does rather than tracking its liveness as a normal register. def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>; // The fast interrupt handlers have more private state and get their own copies // of R8-R12, in addition to SP and LR. As before, mark LR for saving too. // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and // current frame lowering expects to encounter it while processing callee-saved // registers. def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARMInstrFormats.td000064400000000000000000002570360072674642500251320ustar 00000000000000//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // // ARM Instruction Format Definitions. // // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine // code emitter. class Format val> { bits<6> Value = val; } def Pseudo : Format<0>; def MulFrm : Format<1>; def BrFrm : Format<2>; def BrMiscFrm : Format<3>; def DPFrm : Format<4>; def DPSoRegRegFrm : Format<5>; def LdFrm : Format<6>; def StFrm : Format<7>; def LdMiscFrm : Format<8>; def StMiscFrm : Format<9>; def LdStMulFrm : Format<10>; def LdStExFrm : Format<11>; def ArithMiscFrm : Format<12>; def SatFrm : Format<13>; def ExtFrm : Format<14>; def VFPUnaryFrm : Format<15>; def VFPBinaryFrm : Format<16>; def VFPConv1Frm : Format<17>; def VFPConv2Frm : Format<18>; def VFPConv3Frm : Format<19>; def VFPConv4Frm : Format<20>; def VFPConv5Frm : Format<21>; def VFPLdStFrm : Format<22>; def VFPLdStMulFrm : Format<23>; def VFPMiscFrm : Format<24>; def ThumbFrm : Format<25>; def MiscFrm : Format<26>; def NGetLnFrm : Format<27>; def NSetLnFrm : Format<28>; def NDupFrm : Format<29>; def NLdStFrm : Format<30>; def N1RegModImmFrm: Format<31>; def N2RegFrm : Format<32>; def NVCVTFrm : Format<33>; def NVDupLnFrm : Format<34>; def N2RegVShLFrm : Format<35>; def N2RegVShRFrm : Format<36>; def N3RegFrm : Format<37>; def N3RegVShFrm : Format<38>; def NVExtFrm : Format<39>; def NVMulSLFrm : Format<40>; def NVTBLFrm : Format<41>; def DPSoRegImmFrm : Format<42>; def N3RegCplxFrm : Format<43>; // Misc flags. // The instruction has an Rn register operand. // UnaryDP - Indicates this is a unary data processing instruction, i.e. // it doesn't have a Rn operand. class UnaryDP { bit isUnaryDataProc = 1; } // Xform16Bit - Indicates this Thumb2 instruction may be transformed into // a 16-bit Thumb instruction if certain conditions are met. class Xform16Bit { bit canXformTo16Bit = 1; } //===----------------------------------------------------------------------===// // ARM Instruction flags. These need to match ARMBaseInstrInfo.h. // // FIXME: Once the JIT is MC-ized, these can go away. // Addressing mode. class AddrMode val> { bits<5> Value = val; } def AddrModeNone : AddrMode<0>; def AddrMode1 : AddrMode<1>; def AddrMode2 : AddrMode<2>; def AddrMode3 : AddrMode<3>; def AddrMode4 : AddrMode<4>; def AddrMode5 : AddrMode<5>; def AddrMode6 : AddrMode<6>; def AddrModeT1_1 : AddrMode<7>; def AddrModeT1_2 : AddrMode<8>; def AddrModeT1_4 : AddrMode<9>; def AddrModeT1_s : AddrMode<10>; def AddrModeT2_i12 : AddrMode<11>; def AddrModeT2_i8 : AddrMode<12>; def AddrModeT2_so : AddrMode<13>; def AddrModeT2_pc : AddrMode<14>; def AddrModeT2_i8s4 : AddrMode<15>; def AddrMode_i12 : AddrMode<16>; def AddrMode5FP16 : AddrMode<17>; def AddrModeT2_ldrex : AddrMode<18>; // Load / store index mode. class IndexMode val> { bits<2> Value = val; } def IndexModeNone : IndexMode<0>; def IndexModePre : IndexMode<1>; def IndexModePost : IndexMode<2>; def IndexModeUpd : IndexMode<3>; // Instruction execution domain. class Domain val> { bits<3> Value = val; } def GenericDomain : Domain<0>; def VFPDomain : Domain<1>; // Instructions in VFP domain only def NeonDomain : Domain<2>; // Instructions in Neon domain only def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 //===----------------------------------------------------------------------===// // ARM special operands. // // ARM imod and iflag operands, used only by the CPS instruction. def imod_op : Operand { let PrintMethod = "printCPSIMod"; } def ProcIFlagsOperand : AsmOperandClass { let Name = "ProcIFlags"; let ParserMethod = "parseProcIFlagsOperand"; } def iflags_op : Operand { let PrintMethod = "printCPSIFlag"; let ParserMatchClass = ProcIFlagsOperand; } // ARM Predicate operand. Default to 14 = always (AL). Second part is CC // register whose default is 0 (no register). def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand { let PrintMethod = "printPredicateOperand"; let ParserMatchClass = CondCodeOperand; let DecoderMethod = "DecodePredicateOperand"; } // Selectable predicate operand for CMOV instructions. We can't use a normal // predicate because the default values interfere with instruction selection. In // all other respects it is identical though: pseudo-instruction expansion // relies on the MachineOperands being compatible. def cmovpred : Operand, PredicateOp, ComplexPattern { let MIOperandInfo = (ops i32imm, i32imm); let PrintMethod = "printPredicateOperand"; } // Conditional code result for instructions whose 's' bit is set, e.g. subs. def CCOutOperand : AsmOperandClass { let Name = "CCOut"; } def cc_out : OptionalDefOperand { let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; let ParserMatchClass = CCOutOperand; let DecoderMethod = "DecodeCCOutOperand"; } // Same as cc_out except it defaults to setting CPSR. def s_cc_out : OptionalDefOperand { let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; let ParserMatchClass = CCOutOperand; let DecoderMethod = "DecodeCCOutOperand"; } // ARM special operands for disassembly only. // def SetEndAsmOperand : ImmAsmOperand<0,1> { let Name = "SetEndImm"; let ParserMethod = "parseSetEndImm"; } def setend_op : Operand { let PrintMethod = "printSetendOperand"; let ParserMatchClass = SetEndAsmOperand; } def MSRMaskOperand : AsmOperandClass { let Name = "MSRMask"; let ParserMethod = "parseMSRMaskOperand"; } def msr_mask : Operand { let PrintMethod = "printMSRMaskOperand"; let DecoderMethod = "DecodeMSRMask"; let ParserMatchClass = MSRMaskOperand; } def BankedRegOperand : AsmOperandClass { let Name = "BankedReg"; let ParserMethod = "parseBankedRegOperand"; } def banked_reg : Operand { let PrintMethod = "printBankedRegOperand"; let DecoderMethod = "DecodeBankedReg"; let ParserMatchClass = BankedRegOperand; } // Shift Right Immediate - A shift right immediate is encoded differently from // other shift immediates. The imm6 field is encoded like so: // // Offset Encoding // 8 imm6<5:3> = '001', 8 - is encoded in imm6<2:0> // 16 imm6<5:4> = '01', 16 - is encoded in imm6<3:0> // 32 imm6<5> = '1', 32 - is encoded in imm6<4:0> // 64 64 - is encoded in imm6<5:0> def shr_imm8_asm_operand : ImmAsmOperand<1,8> { let Name = "ShrImm8"; } def shr_imm8 : Operand, ImmLeaf 0 && Imm <= 8; }]> { let EncoderMethod = "getShiftRight8Imm"; let DecoderMethod = "DecodeShiftRight8Imm"; let ParserMatchClass = shr_imm8_asm_operand; } def shr_imm16_asm_operand : ImmAsmOperand<1,16> { let Name = "ShrImm16"; } def shr_imm16 : Operand, ImmLeaf 0 && Imm <= 16; }]> { let EncoderMethod = "getShiftRight16Imm"; let DecoderMethod = "DecodeShiftRight16Imm"; let ParserMatchClass = shr_imm16_asm_operand; } def shr_imm32_asm_operand : ImmAsmOperand<1,32> { let Name = "ShrImm32"; } def shr_imm32 : Operand, ImmLeaf 0 && Imm <= 32; }]> { let EncoderMethod = "getShiftRight32Imm"; let DecoderMethod = "DecodeShiftRight32Imm"; let ParserMatchClass = shr_imm32_asm_operand; } def shr_imm64_asm_operand : ImmAsmOperand<1,64> { let Name = "ShrImm64"; } def shr_imm64 : Operand, ImmLeaf 0 && Imm <= 64; }]> { let EncoderMethod = "getShiftRight64Imm"; let DecoderMethod = "DecodeShiftRight64Imm"; let ParserMatchClass = shr_imm64_asm_operand; } // ARM Assembler operand for ldr Rd, =expression which generates an offset // to a constant pool entry or a MOV depending on the value of expression def const_pool_asm_operand : AsmOperandClass { let Name = "ConstPoolAsmImm"; } def const_pool_asm_imm : Operand { let ParserMatchClass = const_pool_asm_operand; } //===----------------------------------------------------------------------===// // ARM Assembler alias templates. // // Note: When EmitPriority == 1, the alias will be used for printing class ARMInstAlias : InstAlias, Requires<[IsARM]>; class ARMInstSubst : InstAlias, Requires<[IsARM,UseNegativeImmediates]>; class tInstAlias : InstAlias, Requires<[IsThumb]>; class tInstSubst : InstAlias, Requires<[IsThumb,UseNegativeImmediates]>; class t2InstAlias : InstAlias, Requires<[IsThumb2]>; class t2InstSubst : InstAlias, Requires<[IsThumb2,UseNegativeImmediates]>; class VFP2InstAlias : InstAlias, Requires<[HasVFP2]>; class VFP2DPInstAlias : InstAlias, Requires<[HasVFP2,HasDPVFP]>; class VFP3InstAlias : InstAlias, Requires<[HasVFP3]>; class NEONInstAlias : InstAlias, Requires<[HasNEON]>; class VFP2MnemonicAlias : MnemonicAlias, Requires<[HasVFP2]>; class NEONMnemonicAlias : MnemonicAlias, Requires<[HasNEON]>; //===----------------------------------------------------------------------===// // ARM Instruction templates. // class InstTemplate : Instruction { let Namespace = "ARM"; AddrMode AM = am; int Size = sz; IndexMode IM = im; bits<2> IndexModeBits = IM.Value; Format F = f; bits<6> Form = F.Value; Domain D = d; bit isUnaryDataProc = 0; bit canXformTo16Bit = 0; // The instruction is a 16-bit flag setting Thumb instruction. Used // by the parser to determine whether to require the 'S' suffix on the // mnemonic (when not in an IT block) or preclude it (when in an IT block). bit thumbArithFlagSetting = 0; // If this is a pseudo instruction, mark it isCodeGenOnly. let isCodeGenOnly = !eq(!cast(f), "Pseudo"); // The layout of TSFlags should be kept in sync with ARMBaseInfo.h. let TSFlags{4-0} = AM.Value; let TSFlags{6-5} = IndexModeBits; let TSFlags{12-7} = Form; let TSFlags{13} = isUnaryDataProc; let TSFlags{14} = canXformTo16Bit; let TSFlags{17-15} = D.Value; let TSFlags{18} = thumbArithFlagSetting; let Constraints = cstr; let Itinerary = itin; } class Encoding { field bits<32> Inst; // Mask of bits that cause an encoding to be UNPREDICTABLE. // If a bit is set, then if the corresponding bit in the // target encoding differs from its value in the "Inst" field, // the instruction is UNPREDICTABLE (SoftFail in abstract parlance). field bits<32> Unpredictable = 0; // SoftFail is the generic name for this field, but we alias it so // as to make it more obvious what it means in ARM-land. field bits<32> SoftFail = Unpredictable; } class InstARM : InstTemplate, Encoding { let DecoderNamespace = "ARM"; } // This Encoding-less class is used by Thumb1 to specify the encoding bits later // on by adding flavors to specific instructions. class InstThumb : InstTemplate { let DecoderNamespace = "Thumb"; } // Pseudo-instructions for alternate assembly syntax (never used by codegen). // These are aliases that require C++ handling to convert to the target // instruction, while InstAliases can be handled directly by tblgen. class AsmPseudoInst : InstTemplate { let OutOperandList = oops; let InOperandList = iops; let Pattern = []; let isCodeGenOnly = 0; // So we get asm matcher for it. let AsmString = asm; let isPseudo = 1; } class ARMAsmPseudo : AsmPseudoInst, Requires<[IsARM]>; class tAsmPseudo : AsmPseudoInst, Requires<[IsThumb]>; class t2AsmPseudo : AsmPseudoInst, Requires<[IsThumb2]>; class VFP2AsmPseudo : AsmPseudoInst, Requires<[HasVFP2]>; class NEONAsmPseudo : AsmPseudoInst, Requires<[HasNEON]>; // Pseudo instructions for the code generator. class PseudoInst pattern> : InstTemplate { let OutOperandList = oops; let InOperandList = iops; let Pattern = pattern; let isCodeGenOnly = 1; let isPseudo = 1; } // PseudoInst that's ARM-mode only. class ARMPseudoInst pattern> : PseudoInst { let Size = sz; list Predicates = [IsARM]; } // PseudoInst that's Thumb-mode only. class tPseudoInst pattern> : PseudoInst { let Size = sz; list Predicates = [IsThumb]; } // PseudoInst that's in ARMv8-M baseline (Somewhere between Thumb and Thumb2) class t2basePseudoInst pattern> : PseudoInst { let Size = sz; list Predicates = [IsThumb,HasV8MBaseline]; } // PseudoInst that's Thumb2-mode only. class t2PseudoInst pattern> : PseudoInst { let Size = sz; list Predicates = [IsThumb2]; } class ARMPseudoExpand pattern, dag Result> : ARMPseudoInst, PseudoInstExpansion; class tPseudoExpand pattern, dag Result> : tPseudoInst, PseudoInstExpansion; class t2PseudoExpand pattern, dag Result> : t2PseudoInst, PseudoInstExpansion; // Almost all ARM instructions are predicable. class I pattern> : InstARM { bits<4> p; let Inst{31-28} = p; let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); let Pattern = pattern; list Predicates = [IsARM]; } // A few are not predicable class InoP pattern> : InstARM { let OutOperandList = oops; let InOperandList = iops; let AsmString = !strconcat(opc, asm); let Pattern = pattern; let isPredicable = 0; list Predicates = [IsARM]; } // Same as I except it can optionally modify CPSR. Note it's modeled as an input // operand since by default it's a zero register. It will become an implicit def // once it's "flipped". class sI pattern> : InstARM { bits<4> p; // Predicate operand bits<1> s; // condition-code set flag ('1' if the insn should set the flags) let Inst{31-28} = p; let Inst{20} = s; let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); let AsmString = !strconcat(opc, "${s}${p}", asm); let Pattern = pattern; list Predicates = [IsARM]; } // Special cases class XI pattern> : InstARM { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list Predicates = [IsARM]; } class AI pattern> : I; class AsI pattern> : sI; class AXI pattern> : XI; class AXIM pattern> : XI; class AInoP pattern> : InoP; // Ctrl flow instructions class ABI opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { let Inst{27-24} = opcod; } class ABXI opcod, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : XI { let Inst{27-24} = opcod; } // BR_JT instructions class JTI pattern> : XI; class AIldr_ex_or_acq opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rt; bits<4> addr; let Inst{27-23} = 0b00011; let Inst{22-21} = opcod; let Inst{20} = 1; let Inst{19-16} = addr; let Inst{15-12} = Rt; let Inst{11-10} = 0b11; let Inst{9-8} = opcod2; let Inst{7-0} = 0b10011111; } class AIstr_ex_or_rel opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rt; bits<4> addr; let Inst{27-23} = 0b00011; let Inst{22-21} = opcod; let Inst{20} = 0; let Inst{19-16} = addr; let Inst{11-10} = 0b11; let Inst{9-8} = opcod2; let Inst{7-4} = 0b1001; let Inst{3-0} = Rt; } // Atomic load/store instructions class AIldrex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AIldr_ex_or_acq; class AIstrex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AIstr_ex_or_rel { bits<4> Rd; let Inst{15-12} = Rd; } // Exclusive load/store instructions class AIldaex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AIldr_ex_or_acq, Requires<[IsARM, HasAcquireRelease, HasV7Clrex]>; class AIstlex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AIstr_ex_or_rel, Requires<[IsARM, HasAcquireRelease, HasV7Clrex]> { bits<4> Rd; let Inst{15-12} = Rd; } class AIswp pattern> : AI { bits<4> Rt; bits<4> Rt2; bits<4> addr; let Inst{27-23} = 0b00010; let Inst{22} = b; let Inst{21-20} = 0b00; let Inst{19-16} = addr; let Inst{15-12} = Rt; let Inst{11-4} = 0b00001001; let Inst{3-0} = Rt2; let Unpredictable{11-8} = 0b1111; let DecoderMethod = "DecodeSwap"; } // Acquire/Release load/store instructions class AIldracq opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AIldr_ex_or_acq, Requires<[IsARM, HasAcquireRelease]>; class AIstrrel opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AIstr_ex_or_rel, Requires<[IsARM, HasAcquireRelease]> { let Inst{15-12} = 0b1111; } // addrmode1 instructions class AI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> : I { let Inst{24-21} = opcod; let Inst{27-26} = 0b00; } class AsI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> : sI { let Inst{24-21} = opcod; let Inst{27-26} = 0b00; } class AXI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string asm, list pattern> : XI { let Inst{24-21} = opcod; let Inst{27-26} = 0b00; } // loads // LDR/LDRB/STR/STRB/... class AI2ldst op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, Format f, InstrItinClass itin, string opc, string asm, list pattern> : I { let Inst{27-25} = op; let Inst{24} = 1; // 24 == P // 23 == U let Inst{22} = isByte; let Inst{21} = 0; // 21 == W let Inst{20} = isLd; } // Indexed load/stores class AI2ldstidx pattern> : I { bits<4> Rt; let Inst{27-26} = 0b01; let Inst{24} = isPre; // P bit let Inst{22} = isByte; // B bit let Inst{21} = isPre; // W bit let Inst{20} = isLd; // L bit let Inst{15-12} = Rt; } class AI2stridx_reg pattern> : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, pattern> { // AM2 store w/ two operands: (GPR, am2offset) // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> Rn; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{19-16} = Rn; let Inst{11-5} = offset{11-5}; let Inst{4} = 0; let Inst{3-0} = offset{3-0}; } class AI2stridx_imm pattern> : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, pattern> { // AM2 store w/ two operands: (GPR, am2offset) // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> Rn; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{19-16} = Rn; let Inst{11-0} = offset{11-0}; } // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB // but for now use this class for STRT and STRBT. class AI2stridxT pattern> : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, pattern> { // AM2 store w/ two operands: (GPR, am2offset) // {17-14} Rn // {13} 1 == Rm, 0 == imm12 // {12} isAdd // {11-0} imm12/Rm bits<18> addr; let Inst{25} = addr{13}; let Inst{23} = addr{12}; let Inst{19-16} = addr{17-14}; let Inst{11-0} = addr{11-0}; } // addrmode3 instructions class AI3ld op, bit op20, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<14> addr; bits<4> Rt; let Inst{27-25} = 0b000; let Inst{24} = 1; // P bit let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{21} = 0; // W bit let Inst{20} = op20; // L bit let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Rt; // Rt let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{7-4} = op; let Inst{3-0} = addr{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } class AI3ldstidx op, bit op20, bit isPre, dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : I { bits<4> Rt; let Inst{27-25} = 0b000; let Inst{24} = isPre; // P bit let Inst{21} = isPre; // W bit let Inst{20} = op20; // L bit let Inst{15-12} = Rt; // Rt let Inst{7-4} = op; } // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB // but for now use this class for LDRSBT, LDRHT, LDSHT. class AI3ldstidxT op, bit isLoad, dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : I { // {13} 1 == imm8, 0 == Rm // {12-9} Rn // {8} isAdd // {7-4} imm7_4/zero // {3-0} imm3_0/Rm bits<4> addr; bits<4> Rt; let Inst{27-25} = 0b000; let Inst{24} = 0; // P bit let Inst{21} = 1; let Inst{20} = isLoad; // L bit let Inst{19-16} = addr; // Rn let Inst{15-12} = Rt; // Rt let Inst{7-4} = op; } // stores class AI3str op, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<14> addr; bits<4> Rt; let Inst{27-25} = 0b000; let Inst{24} = 1; // P bit let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{21} = 0; // W bit let Inst{20} = 0; // L bit let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Rt; // Rt let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{7-4} = op; let Inst{3-0} = addr{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } // addrmode4 instructions class AXI4 pattern> : XI { bits<4> p; bits<16> regs; bits<4> Rn; let Inst{31-28} = p; let Inst{27-25} = 0b100; let Inst{22} = 0; // S bit let Inst{19-16} = Rn; let Inst{15-0} = regs; } // Unsigned multiply, multiply-accumulate instructions. class AMul1I opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { let Inst{7-4} = 0b1001; let Inst{20} = 0; // S bit let Inst{27-21} = opcod; } class AsMul1I opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : sI { let Inst{7-4} = 0b1001; let Inst{27-21} = opcod; } // Most significant word multiply class AMul2I opcod, bits<4> opc7_4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{7-4} = opc7_4; let Inst{20} = 1; let Inst{27-21} = opcod; let Inst{19-16} = Rd; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } // MSW multiple w/ Ra operand class AMul2Ia opcod, bits<4> opc7_4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AMul2I { bits<4> Ra; let Inst{15-12} = Ra; } // SMUL / SMULW / SMLA / SMLAW class AMulxyIbase opcod, bits<2> bit6_5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rn; bits<4> Rm; let Inst{4} = 0; let Inst{7} = 1; let Inst{20} = 0; let Inst{27-21} = opcod; let Inst{6-5} = bit6_5; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } class AMulxyI opcod, bits<2> bit6_5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AMulxyIbase { bits<4> Rd; let Inst{19-16} = Rd; } // AMulxyI with Ra operand class AMulxyIa opcod, bits<2> bit6_5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AMulxyI { bits<4> Ra; let Inst{15-12} = Ra; } // SMLAL* class AMulxyI64 opcod, bits<2> bit6_5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AMulxyIbase { bits<4> RdLo; bits<4> RdHi; let Inst{19-16} = RdHi; let Inst{15-12} = RdLo; } // Extend instructions. class AExtI opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { // All AExtI instructions have Rd and Rm register operands. bits<4> Rd; bits<4> Rm; let Inst{15-12} = Rd; let Inst{3-0} = Rm; let Inst{7-4} = 0b0111; let Inst{9-8} = 0b00; let Inst{27-20} = opcod; let Unpredictable{9-8} = 0b11; } // Misc Arithmetic instructions. class AMiscA1I opcod, bits<4> opc7_4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rd; bits<4> Rm; let Inst{27-20} = opcod; let Inst{19-16} = 0b1111; let Inst{15-12} = Rd; let Inst{11-8} = 0b1111; let Inst{7-4} = opc7_4; let Inst{3-0} = Rm; } // Division instructions. class ADivA1I opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{27-23} = 0b01110; let Inst{22-20} = opcod; let Inst{19-16} = Rd; let Inst{15-12} = 0b1111; let Inst{11-8} = Rm; let Inst{7-4} = 0b0001; let Inst{3-0} = Rn; } // PKH instructions def PKHLSLAsmOperand : ImmAsmOperand<0,31> { let Name = "PKHLSLImm"; let ParserMethod = "parsePKHLSLImm"; } def pkh_lsl_amt: Operand, ImmLeaf= 0 && Imm < 32; }]>{ let PrintMethod = "printPKHLSLShiftImm"; let ParserMatchClass = PKHLSLAsmOperand; } def PKHASRAsmOperand : AsmOperandClass { let Name = "PKHASRImm"; let ParserMethod = "parsePKHASRImm"; } def pkh_asr_amt: Operand, ImmLeaf 0 && Imm <= 32; }]>{ let PrintMethod = "printPKHASRShiftImm"; let ParserMatchClass = PKHASRAsmOperand; } class APKHI opcod, bit tb, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { bits<4> Rd; bits<4> Rn; bits<4> Rm; bits<5> sh; let Inst{27-20} = opcod; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-7} = sh; let Inst{6} = tb; let Inst{5-4} = 0b01; let Inst{3-0} = Rm; } //===----------------------------------------------------------------------===// // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. class ARMPat : Pat { list Predicates = [IsARM]; } class ARMV5TPat : Pat { list Predicates = [IsARM, HasV5T]; } class ARMV5TEPat : Pat { list Predicates = [IsARM, HasV5TE]; } // ARMV5MOPat - Same as ARMV5TEPat with UseMulOps. class ARMV5MOPat : Pat { list Predicates = [IsARM, HasV5TE, UseMulOps]; } class ARMV6Pat : Pat { list Predicates = [IsARM, HasV6]; } class VFPPat : Pat { list Predicates = [HasVFP2]; } class VFPNoNEONPat : Pat { list Predicates = [HasVFP2, DontUseNEONForFP]; } class Thumb2DSPPat : Pat { list Predicates = [IsThumb2, HasDSP]; } class Thumb2DSPMulPat : Pat { list Predicates = [IsThumb2, UseMulOps, HasDSP]; } class FP16Pat : Pat { list Predicates = [HasFP16]; } class FullFP16Pat : Pat { list Predicates = [HasFullFP16]; } //===----------------------------------------------------------------------===// // Thumb Instruction Format Definitions. // class ThumbI pattern> : InstThumb { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list Predicates = [IsThumb]; } // TI - Thumb instruction. class TI pattern> : ThumbI; // Two-address instructions class TIt pattern> : ThumbI; // tBL, tBX 32-bit instructions class TIx2 opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : ThumbI, Encoding { let Inst{31-27} = opcod1; let Inst{15-14} = opcod2; let Inst{12} = opcod3; } // BR_JT instructions class TJTI pattern> : ThumbI; // Thumb1 only class Thumb1I pattern> : InstThumb { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list Predicates = [IsThumb, IsThumb1Only]; } class T1I pattern> : Thumb1I; class T1Ix2 pattern> : Thumb1I; // Two-address instructions class T1It pattern> : Thumb1I; // Thumb1 instruction that can either be predicated or set CPSR. class Thumb1sI pattern> : InstThumb { let OutOperandList = !con(oops, (outs s_cc_out:$s)); let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${s}${p}", asm); let Pattern = pattern; let thumbArithFlagSetting = 1; list Predicates = [IsThumb, IsThumb1Only]; let DecoderNamespace = "ThumbSBit"; } class T1sI pattern> : Thumb1sI; // Two-address instructions class T1sIt pattern> : Thumb1sI; // Thumb1 instruction that can be predicated. class Thumb1pI pattern> : InstThumb { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); let Pattern = pattern; list Predicates = [IsThumb, IsThumb1Only]; } class T1pI pattern> : Thumb1pI; // Two-address instructions class T1pIt pattern> : Thumb1pI; class T1pIs pattern> : Thumb1pI; class Encoding16 : Encoding { let Inst{31-16} = 0x0000; } // A6.2 16-bit Thumb instruction encoding class T1Encoding opcode> : Encoding16 { let Inst{15-10} = opcode; } // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. class T1General opcode> : Encoding16 { let Inst{15-14} = 0b00; let Inst{13-9} = opcode; } // A6.2.2 Data-processing encoding. class T1DataProcessing opcode> : Encoding16 { let Inst{15-10} = 0b010000; let Inst{9-6} = opcode; } // A6.2.3 Special data instructions and branch and exchange encoding. class T1Special opcode> : Encoding16 { let Inst{15-10} = 0b010001; let Inst{9-6} = opcode; } // A6.2.4 Load/store single data item encoding. class T1LoadStore opA, bits<3> opB> : Encoding16 { let Inst{15-12} = opA; let Inst{11-9} = opB; } class T1LdStSP opB> : T1LoadStore<0b1001, opB>; // SP relative class T1BranchCond opcode> : Encoding16 { let Inst{15-12} = opcode; } // Helper classes to encode Thumb1 loads and stores. For immediates, the // following bits are used for "opA" (see A6.2.4): // // 0b0110 => Immediate, 4 bytes // 0b1000 => Immediate, 2 bytes // 0b0111 => Immediate, 1 byte class T1pILdStEncode opcode, dag oops, dag iops, AddrMode am, InstrItinClass itin, string opc, string asm, list pattern> : Thumb1pI, T1LoadStore<0b0101, opcode> { bits<3> Rt; bits<8> addr; let Inst{8-6} = addr{5-3}; // Rm let Inst{5-3} = addr{2-0}; // Rn let Inst{2-0} = Rt; } class T1pILdStEncodeImm opA, bit opB, dag oops, dag iops, AddrMode am, InstrItinClass itin, string opc, string asm, list pattern> : Thumb1pI, T1LoadStore { bits<3> Rt; bits<8> addr; let Inst{10-6} = addr{7-3}; // imm5 let Inst{5-3} = addr{2-0}; // Rn let Inst{2-0} = Rt; } // A6.2.5 Miscellaneous 16-bit instructions encoding. class T1Misc opcode> : Encoding16 { let Inst{15-12} = 0b1011; let Inst{11-5} = opcode; } // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. class Thumb2I pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); let Pattern = pattern; list Predicates = [IsThumb2]; let DecoderNamespace = "Thumb2"; } // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an // input operand since by default it's a zero register. It will become an // implicit def once it's "flipped". // // FIXME: This uses unified syntax so {s} comes before {p}. We should make it // more consistent. class Thumb2sI pattern> : InstARM { bits<1> s; // condition-code set flag ('1' if the insn should set the flags) let Inst{20} = s; let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); let AsmString = !strconcat(opc, "${s}${p}", asm); let Pattern = pattern; list Predicates = [IsThumb2]; let DecoderNamespace = "Thumb2"; } // Special cases class Thumb2XI pattern> : InstARM { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list Predicates = [IsThumb2]; let DecoderNamespace = "Thumb2"; } class ThumbXI pattern> : InstARM { let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; let Pattern = pattern; list Predicates = [IsThumb, IsThumb1Only]; let DecoderNamespace = "Thumb"; } class T2I pattern> : Thumb2I; class T2Ii12 pattern> : Thumb2I; class T2Ii8 pattern> : Thumb2I; class T2Iso pattern> : Thumb2I; class T2Ipc pattern> : Thumb2I; class T2Ii8s4 pattern> : Thumb2I { bits<4> Rt; bits<4> Rt2; bits<13> addr; let Inst{31-25} = 0b1110100; let Inst{24} = P; let Inst{23} = addr{8}; let Inst{22} = 1; let Inst{21} = W; let Inst{20} = isLoad; let Inst{19-16} = addr{12-9}; let Inst{15-12} = Rt{3-0}; let Inst{11-8} = Rt2{3-0}; let Inst{7-0} = addr{7-0}; } class T2Ii8s4post pattern> : Thumb2I { bits<4> Rt; bits<4> Rt2; bits<4> addr; bits<9> imm; let Inst{31-25} = 0b1110100; let Inst{24} = P; let Inst{23} = imm{8}; let Inst{22} = 1; let Inst{21} = W; let Inst{20} = isLoad; let Inst{19-16} = addr; let Inst{15-12} = Rt{3-0}; let Inst{11-8} = Rt2{3-0}; let Inst{7-0} = imm{7-0}; } class T2sI pattern> : Thumb2sI; class T2XI pattern> : Thumb2XI; class T2JTI pattern> : Thumb2XI; // Move to/from coprocessor instructions class T2Cop opc, dag oops, dag iops, string opcstr, string asm, list pattern> : T2I , Requires<[IsThumb2]> { let Inst{31-28} = opc; } // Two-address instructions class T2XIt pattern> : Thumb2XI; // T2Ipreldst - Thumb2 pre-indexed load / store instructions. class T2Ipreldst opcod, bit load, bit pre, dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); let Pattern = pattern; list Predicates = [IsThumb2]; let DecoderNamespace = "Thumb2"; bits<4> Rt; bits<13> addr; let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = signed; let Inst{23} = 0; let Inst{22-21} = opcod; let Inst{20} = load; let Inst{19-16} = addr{12-9}; let Inst{15-12} = Rt{3-0}; let Inst{11} = 1; // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed let Inst{10} = pre; // The P bit. let Inst{9} = addr{8}; // Sign bit let Inst{8} = 1; // The W bit. let Inst{7-0} = addr{7-0}; let DecoderMethod = "DecodeT2LdStPre"; } // T2Ipostldst - Thumb2 post-indexed load / store instructions. class T2Ipostldst opcod, bit load, bit pre, dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); let Pattern = pattern; list Predicates = [IsThumb2]; let DecoderNamespace = "Thumb2"; bits<4> Rt; bits<4> Rn; bits<9> offset; let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = signed; let Inst{23} = 0; let Inst{22-21} = opcod; let Inst{20} = load; let Inst{19-16} = Rn; let Inst{15-12} = Rt{3-0}; let Inst{11} = 1; // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed let Inst{10} = pre; // The P bit. let Inst{9} = offset{8}; // Sign bit let Inst{8} = 1; // The W bit. let Inst{7-0} = offset{7-0}; let DecoderMethod = "DecodeT2LdStPre"; } // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. class T1Pat : Pat { list Predicates = [IsThumb, IsThumb1Only]; } // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. class T2v6Pat : Pat { list Predicates = [IsThumb2, HasV6T2]; } // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. class T2Pat : Pat { list Predicates = [IsThumb2]; } //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // ARM VFP Instruction templates. // // Almost all VFP instructions are predicable. class VFPI pattern> : InstARM { bits<4> p; let Inst{31-28} = p; let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", asm); let Pattern = pattern; let PostEncoderMethod = "VFPThumb2PostEncoder"; let DecoderNamespace = "VFP"; list Predicates = [HasVFP2]; } // Special cases class VFPXI pattern> : InstARM { bits<4> p; let Inst{31-28} = p; let OutOperandList = oops; let InOperandList = iops; let AsmString = asm; let Pattern = pattern; let PostEncoderMethod = "VFPThumb2PostEncoder"; let DecoderNamespace = "VFP"; list Predicates = [HasVFP2]; } class VFPAI pattern> : VFPI { let PostEncoderMethod = "VFPThumb2PostEncoder"; } // ARM VFP addrmode5 loads and stores class ADI5 opcod1, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPI { // Instruction operands. bits<5> Dd; bits<13> addr; // Encode instruction operands. let Inst{23} = addr{8}; // U (add = (U == '1')) let Inst{22} = Dd{4}; let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Dd{3-0}; let Inst{7-0} = addr{7-0}; // imm8 let Inst{27-24} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; let Inst{8} = 1; // Double precision // Loads & stores operate on both NEON and VFP pipelines. let D = VFPNeonDomain; } class ASI5 opcod1, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPI { // Instruction operands. bits<5> Sd; bits<13> addr; // Encode instruction operands. let Inst{23} = addr{8}; // U (add = (U == '1')) let Inst{22} = Sd{0}; let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Sd{4-1}; let Inst{7-0} = addr{7-0}; // imm8 let Inst{27-24} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; let Inst{8} = 0; // Single precision // Loads & stores operate on both NEON and VFP pipelines. let D = VFPNeonDomain; } class AHI5 opcod1, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPI { list Predicates = [HasFullFP16]; // Instruction operands. bits<5> Sd; bits<13> addr; // Encode instruction operands. let Inst{23} = addr{8}; // U (add = (U == '1')) let Inst{22} = Sd{0}; let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Sd{4-1}; let Inst{7-0} = addr{7-0}; // imm8 let Inst{27-24} = opcod1; let Inst{21-20} = opcod2; let Inst{11-8} = 0b1001; // Half precision // Loads & stores operate on both NEON and VFP pipelines. let D = VFPNeonDomain; } // VFP Load / store multiple pseudo instructions. class PseudoVFPLdStM pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let Pattern = pattern; list Predicates = [HasVFP2]; } // Load / store multiple // Unknown precision class AXXI4 pattern> : VFPXI { // Instruction operands. bits<4> Rn; bits<13> regs; // Encode instruction operands. let Inst{19-16} = Rn; let Inst{22} = 0; let Inst{15-12} = regs{11-8}; let Inst{7-1} = regs{7-1}; let Inst{27-25} = 0b110; let Inst{11-8} = 0b1011; let Inst{0} = 1; } // Double precision class AXDI4 pattern> : VFPXI { // Instruction operands. bits<4> Rn; bits<13> regs; // Encode instruction operands. let Inst{19-16} = Rn; let Inst{22} = regs{12}; let Inst{15-12} = regs{11-8}; let Inst{7-1} = regs{7-1}; let Inst{27-25} = 0b110; let Inst{11-9} = 0b101; let Inst{8} = 1; // Double precision let Inst{0} = 0; } // Single Precision class AXSI4 pattern> : VFPXI { // Instruction operands. bits<4> Rn; bits<13> regs; // Encode instruction operands. let Inst{19-16} = Rn; let Inst{22} = regs{8}; let Inst{15-12} = regs{12-9}; let Inst{7-0} = regs{7-0}; let Inst{27-25} = 0b110; let Inst{11-9} = 0b101; let Inst{8} = 0; // Single precision } // Double precision, unary class ADuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { // Instruction operands. bits<5> Dd; bits<5> Dm; // Encode instruction operands. let Inst{3-0} = Dm{3-0}; let Inst{5} = Dm{4}; let Inst{15-12} = Dd{3-0}; let Inst{22} = Dd{4}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-9} = 0b101; let Inst{8} = 1; // Double precision let Inst{7-6} = opcod4; let Inst{4} = opcod5; let Predicates = [HasVFP2, HasDPVFP]; } // Double precision, unary, not-predicated class ADuInp opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : VFPXI { // Instruction operands. bits<5> Dd; bits<5> Dm; let Inst{31-28} = 0b1111; // Encode instruction operands. let Inst{3-0} = Dm{3-0}; let Inst{5} = Dm{4}; let Inst{15-12} = Dd{3-0}; let Inst{22} = Dd{4}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-9} = 0b101; let Inst{8} = 1; // Double precision let Inst{7-6} = opcod4; let Inst{4} = opcod5; } // Double precision, binary class ADbI opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { // Instruction operands. bits<5> Dd; bits<5> Dn; bits<5> Dm; // Encode instruction operands. let Inst{3-0} = Dm{3-0}; let Inst{5} = Dm{4}; let Inst{19-16} = Dn{3-0}; let Inst{7} = Dn{4}; let Inst{15-12} = Dd{3-0}; let Inst{22} = Dd{4}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; let Inst{8} = 1; // Double precision let Inst{6} = op6; let Inst{4} = op4; let Predicates = [HasVFP2, HasDPVFP]; } // FP, binary, not predicated class ADbInp opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : VFPXI { // Instruction operands. bits<5> Dd; bits<5> Dn; bits<5> Dm; let Inst{31-28} = 0b1111; // Encode instruction operands. let Inst{3-0} = Dm{3-0}; let Inst{5} = Dm{4}; let Inst{19-16} = Dn{3-0}; let Inst{7} = Dn{4}; let Inst{15-12} = Dd{3-0}; let Inst{22} = Dd{4}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; let Inst{8} = 1; // double precision let Inst{6} = opcod3; let Inst{4} = 0; let Predicates = [HasVFP2, HasDPVFP]; } // Single precision, unary, predicated class ASuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { // Instruction operands. bits<5> Sd; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-9} = 0b101; let Inst{8} = 0; // Single precision let Inst{7-6} = opcod4; let Inst{4} = opcod5; } // Single precision, unary, non-predicated class ASuInp opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : VFPXI { // Instruction operands. bits<5> Sd; bits<5> Sm; let Inst{31-28} = 0b1111; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-9} = 0b101; let Inst{8} = 0; // Single precision let Inst{7-6} = opcod4; let Inst{4} = opcod5; } // Single precision unary, if no NEON. Same as ASuI except not available if // NEON is enabled. class ASuIn opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : ASuI { list Predicates = [HasVFP2,DontUseNEONForFP]; } // Single precision, binary class ASbI opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { // Instruction operands. bits<5> Sd; bits<5> Sn; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{19-16} = Sn{4-1}; let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; let Inst{8} = 0; // Single precision let Inst{6} = op6; let Inst{4} = op4; } // Single precision, binary, not predicated class ASbInp opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : VFPXI { // Instruction operands. bits<5> Sd; bits<5> Sn; bits<5> Sm; let Inst{31-28} = 0b1111; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{19-16} = Sn{4-1}; let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-9} = 0b101; let Inst{8} = 0; // Single precision let Inst{6} = opcod3; let Inst{4} = 0; } // Single precision binary, if no NEON. Same as ASbI except not available if // NEON is enabled. class ASbIn opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : ASbI { list Predicates = [HasVFP2,DontUseNEONForFP]; // Instruction operands. bits<5> Sd; bits<5> Sn; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{19-16} = Sn{4-1}; let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; } // Half precision, unary, predicated class AHuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { list Predicates = [HasFullFP16]; // Instruction operands. bits<5> Sd; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-8} = 0b1001; // Half precision let Inst{7-6} = opcod4; let Inst{4} = opcod5; } // Half precision, unary, non-predicated class AHuInp opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : VFPXI { list Predicates = [HasFullFP16]; // Instruction operands. bits<5> Sd; bits<5> Sm; let Inst{31-28} = 0b1111; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-8} = 0b1001; // Half precision let Inst{7-6} = opcod4; let Inst{4} = opcod5; } // Half precision, binary class AHbI opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { list Predicates = [HasFullFP16]; // Instruction operands. bits<5> Sd; bits<5> Sn; bits<5> Sm; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{19-16} = Sn{4-1}; let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-8} = 0b1001; // Half precision let Inst{6} = op6; let Inst{4} = op4; } // Half precision, binary, not predicated class AHbInp opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops, InstrItinClass itin, string asm, list pattern> : VFPXI { list Predicates = [HasFullFP16]; // Instruction operands. bits<5> Sd; bits<5> Sn; bits<5> Sm; let Inst{31-28} = 0b1111; // Encode instruction operands. let Inst{3-0} = Sm{4-1}; let Inst{5} = Sm{0}; let Inst{19-16} = Sn{4-1}; let Inst{7} = Sn{0}; let Inst{15-12} = Sd{4-1}; let Inst{22} = Sd{0}; let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-8} = 0b1001; // Half precision let Inst{6} = opcod3; let Inst{4} = 0; } // VFP conversion instructions class AVConv1I opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{19-16} = opcod3; let Inst{11-8} = opcod4; let Inst{6} = 1; let Inst{4} = 0; } // VFP conversion between floating-point and fixed-point class AVConv1XI op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AVConv1I { bits<5> fbits; // size (fixed-point number): sx == 0 ? 16 : 32 let Inst{7} = op5; // sx let Inst{5} = fbits{0}; let Inst{3-0} = fbits{4-1}; } // VFP conversion instructions, if no NEON class AVConv1In opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AVConv1I { list Predicates = [HasVFP2,DontUseNEONForFP]; } class AVConvXI opcod1, bits<4> opcod2, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> : VFPAI { let Inst{27-20} = opcod1; let Inst{11-8} = opcod2; let Inst{4} = 1; } class AVConv2I opcod1, bits<4> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AVConvXI; class AVConv3I opcod1, bits<4> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AVConvXI; class AVConv4I opcod1, bits<4> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AVConvXI; class AVConv5I opcod1, bits<4> opcod2, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AVConvXI; //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // ARM NEON Instruction templates. // class NeonI pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); let Pattern = pattern; list Predicates = [HasNEON]; let DecoderNamespace = "NEON"; } // Same as NeonI except it does not have a "data type" specifier. class NeonXI pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", "\t", asm); let Pattern = pattern; list Predicates = [HasNEON]; let DecoderNamespace = "NEON"; } // Same as NeonI except it is not predicated class NeonInp pattern> : InstARM { let OutOperandList = oops; let InOperandList = iops; let AsmString = !strconcat(opc, ".", dt, "\t", asm); let Pattern = pattern; list Predicates = [HasNEON]; let DecoderNamespace = "NEON"; let Inst{31-28} = 0b1111; } class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NeonI { let Inst{31-24} = 0b11110100; let Inst{23} = op23; let Inst{21-20} = op21_20; let Inst{11-8} = op11_8; let Inst{7-4} = op7_4; let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; let DecoderNamespace = "NEONLoadStore"; bits<5> Vd; bits<6> Rn; bits<4> Rm; let Inst{22} = Vd{4}; let Inst{15-12} = Vd{3-0}; let Inst{19-16} = Rn{3-0}; let Inst{3-0} = Rm{3-0}; } class NLdStLn op21_20, bits<4> op11_8, bits<4> op7_4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NLdSt { bits<3> lane; } class PseudoNLdSt : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); list Predicates = [HasNEON]; } class PseudoNeonI pattern> : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let Pattern = pattern; list Predicates = [HasNEON]; } class NDataI pattern> : NeonI { let Inst{31-25} = 0b1111001; let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; let DecoderNamespace = "NEONData"; } class NDataXI pattern> : NeonXI { let Inst{31-25} = 0b1111001; let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; let DecoderNamespace = "NEONData"; } // NEON "one register and a modified immediate" format. class N1ModImm op21_19, bits<4> op11_8, bit op7, bit op6, bit op5, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NDataI { let Inst{23} = op23; let Inst{21-19} = op21_19; let Inst{11-8} = op11_8; let Inst{7} = op7; let Inst{6} = op6; let Inst{5} = op5; let Inst{4} = op4; // Instruction operands. bits<5> Vd; bits<13> SIMM; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{24} = SIMM{7}; let Inst{18-16} = SIMM{6-4}; let Inst{3-0} = SIMM{3-0}; let DecoderMethod = "DecodeNEONModImmInstruction"; } // NEON 2 vector register format. class N2V op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NDataI { let Inst{24-23} = op24_23; let Inst{21-20} = op21_20; let Inst{19-18} = op19_18; let Inst{17-16} = op17_16; let Inst{11-7} = op11_7; let Inst{6} = op6; let Inst{4} = op4; // Instruction operands. bits<5> Vd; bits<5> Vm; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{3-0} = Vm{3-0}; let Inst{5} = Vm{4}; } // Same as N2V but not predicated. class N2Vnp op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6, dag oops, dag iops, InstrItinClass itin, string OpcodeStr, string Dt, list pattern> : NeonInp { bits<5> Vd; bits<5> Vm; // Encode instruction operands let Inst{22} = Vd{4}; let Inst{15-12} = Vd{3-0}; let Inst{5} = Vm{4}; let Inst{3-0} = Vm{3-0}; // Encode constant bits let Inst{27-23} = 0b00111; let Inst{21-20} = 0b11; let Inst{19-18} = op19_18; let Inst{17-16} = op17_16; let Inst{11} = 0; let Inst{10-8} = op10_8; let Inst{7} = op7; let Inst{6} = op6; let Inst{4} = 0; let DecoderNamespace = "NEON"; } // Same as N2V except it doesn't have a datatype suffix. class N2VX op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : NDataXI { let Inst{24-23} = op24_23; let Inst{21-20} = op21_20; let Inst{19-18} = op19_18; let Inst{17-16} = op17_16; let Inst{11-7} = op11_7; let Inst{6} = op6; let Inst{4} = op4; // Instruction operands. bits<5> Vd; bits<5> Vm; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{3-0} = Vm{3-0}; let Inst{5} = Vm{4}; } // NEON 2 vector register with immediate. class N2VImm op11_8, bit op7, bit op6, bit op4, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NDataI { let Inst{24} = op24; let Inst{23} = op23; let Inst{11-8} = op11_8; let Inst{7} = op7; let Inst{6} = op6; let Inst{4} = op4; // Instruction operands. bits<5> Vd; bits<5> Vm; bits<6> SIMM; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{3-0} = Vm{3-0}; let Inst{5} = Vm{4}; let Inst{21-16} = SIMM{5-0}; } // NEON 3 vector register format. class N3VCommon op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NDataI { let Inst{24} = op24; let Inst{23} = op23; let Inst{21-20} = op21_20; let Inst{11-8} = op11_8; let Inst{6} = op6; let Inst{4} = op4; } class N3V op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : N3VCommon { // Instruction operands. bits<5> Vd; bits<5> Vn; bits<5> Vm; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{19-16} = Vn{3-0}; let Inst{7} = Vn{4}; let Inst{3-0} = Vm{3-0}; let Inst{5} = Vm{4}; } class N3Vnp op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops,Format f, InstrItinClass itin, string OpcodeStr, string Dt, list pattern> : NeonInp { bits<5> Vd; bits<5> Vn; bits<5> Vm; // Encode instruction operands let Inst{22} = Vd{4}; let Inst{15-12} = Vd{3-0}; let Inst{19-16} = Vn{3-0}; let Inst{7} = Vn{4}; let Inst{5} = Vm{4}; let Inst{3-0} = Vm{3-0}; // Encode constant bits let Inst{27-23} = op27_23; let Inst{21-20} = op21_20; let Inst{11-8} = op11_8; let Inst{6} = op6; let Inst{4} = op4; } class N3VLane32 op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : N3VCommon { // Instruction operands. bits<5> Vd; bits<5> Vn; bits<5> Vm; bit lane; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{19-16} = Vn{3-0}; let Inst{7} = Vn{4}; let Inst{3-0} = Vm{3-0}; let Inst{5} = lane; } class N3VLane16 op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : N3VCommon { // Instruction operands. bits<5> Vd; bits<5> Vn; bits<5> Vm; bits<2> lane; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{19-16} = Vn{3-0}; let Inst{7} = Vn{4}; let Inst{2-0} = Vm{2-0}; let Inst{5} = lane{1}; let Inst{3} = lane{0}; } // Same as N3V except it doesn't have a data type suffix. class N3VX op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : NDataXI { let Inst{24} = op24; let Inst{23} = op23; let Inst{21-20} = op21_20; let Inst{11-8} = op11_8; let Inst{6} = op6; let Inst{4} = op4; // Instruction operands. bits<5> Vd; bits<5> Vn; bits<5> Vm; let Inst{15-12} = Vd{3-0}; let Inst{22} = Vd{4}; let Inst{19-16} = Vn{3-0}; let Inst{7} = Vn{4}; let Inst{3-0} = Vm{3-0}; let Inst{5} = Vm{4}; } // NEON VMOVs between scalar and core registers. class NVLaneOp opcod1, bits<4> opcod2, bits<2> opcod3, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, list pattern> : InstARM { let Inst{27-20} = opcod1; let Inst{11-8} = opcod2; let Inst{6-5} = opcod3; let Inst{4} = 1; // A8.6.303, A8.6.328, A8.6.329 let Inst{3-0} = 0b0000; let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); let Pattern = pattern; list Predicates = [HasNEON]; let PostEncoderMethod = "NEONThumb2DupPostEncoder"; let DecoderNamespace = "NEONDup"; bits<5> V; bits<4> R; bits<4> p; bits<4> lane; let Inst{31-28} = p{3-0}; let Inst{7} = V{4}; let Inst{19-16} = V{3-0}; let Inst{15-12} = R{3-0}; } class NVGetLane opcod1, bits<4> opcod2, bits<2> opcod3, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, list pattern> : NVLaneOp; class NVSetLane opcod1, bits<4> opcod2, bits<2> opcod3, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, list pattern> : NVLaneOp; class NVDup opcod1, bits<4> opcod2, bits<2> opcod3, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, list pattern> : NVLaneOp; // Vector Duplicate Lane (from scalar to all elements) class NVDupLane op19_16, bit op6, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, list pattern> : NDataI { let Inst{24-23} = 0b11; let Inst{21-20} = 0b11; let Inst{19-16} = op19_16; let Inst{11-7} = 0b11000; let Inst{6} = op6; let Inst{4} = 0; bits<5> Vd; bits<5> Vm; let Inst{22} = Vd{4}; let Inst{15-12} = Vd{3-0}; let Inst{5} = Vm{4}; let Inst{3-0} = Vm{3-0}; } // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON // for single-precision FP. class NEONFPPat : Pat { list Predicates = [HasNEON,UseNEONForFP]; } // VFP/NEON Instruction aliases for type suffices. // Note: When EmitPriority == 1, the alias will be used for printing class VFPDataTypeInstAlias : InstAlias, Requires<[HasVFP2]>; // Note: When EmitPriority == 1, the alias will be used for printing multiclass VFPDTAnyInstAlias { def : VFPDataTypeInstAlias; def : VFPDataTypeInstAlias; def : VFPDataTypeInstAlias; def : VFPDataTypeInstAlias; } // Note: When EmitPriority == 1, the alias will be used for printing multiclass NEONDTAnyInstAlias { let Predicates = [HasNEON] in { def : VFPDataTypeInstAlias; def : VFPDataTypeInstAlias; def : VFPDataTypeInstAlias; def : VFPDataTypeInstAlias; } } // The same alias classes using AsmPseudo instead, for the more complex // stuff in NEON that InstAlias can't quite handle. // Note that we can't use anonymous defm references here like we can // above, as we care about the ultimate instruction enum names generated, unlike // for instalias defs. class NEONDataTypeAsmPseudoInst : AsmPseudoInst, Requires<[HasNEON]>; // Extension of NEON 3-vector data processing instructions in coprocessor 8 // encoding space, introduced in ARMv8.3-A. class N3VCP8 op24_23, bits<2> op21_20, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NeonInp { bits<5> Vd; bits<5> Vn; bits<5> Vm; let DecoderNamespace = "VFPV8"; // These have the same encodings in ARM and Thumb2 let PostEncoderMethod = ""; let Inst{31-25} = 0b1111110; let Inst{24-23} = op24_23; let Inst{22} = Vd{4}; let Inst{21-20} = op21_20; let Inst{19-16} = Vn{3-0}; let Inst{15-12} = Vd{3-0}; let Inst{11-8} = 0b1000; let Inst{7} = Vn{4}; let Inst{6} = op6; let Inst{5} = Vm{4}; let Inst{4} = op4; let Inst{3-0} = Vm{3-0}; } // Extension of NEON 2-vector-and-scalar data processing instructions in // coprocessor 8 encoding space, introduced in ARMv8.3-A. class N3VLaneCP8 op21_20, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NeonInp { bits<5> Vd; bits<5> Vn; bits<5> Vm; let DecoderNamespace = "VFPV8"; // These have the same encodings in ARM and Thumb2 let PostEncoderMethod = ""; let Inst{31-24} = 0b11111110; let Inst{23} = op23; let Inst{22} = Vd{4}; let Inst{21-20} = op21_20; let Inst{19-16} = Vn{3-0}; let Inst{15-12} = Vd{3-0}; let Inst{11-8} = 0b1000; let Inst{7} = Vn{4}; let Inst{6} = op6; // Bit 5 set by sub-classes let Inst{4} = op4; let Inst{3-0} = Vm{3-0}; } // Operand types for complex instructions class ComplexRotationOperand : AsmOperandClass { let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">"; let DiagnosticString = "complex rotation must be " # Diag; let Name = "ComplexRotation" # Type; } def complexrotateop : Operand { let ParserMatchClass = ComplexRotationOperand<90, 0, "Even", "0, 90, 180 or 270">; let PrintMethod = "printComplexRotationOp<90, 0>"; } def complexrotateopodd : Operand { let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">; let PrintMethod = "printComplexRotationOp<180, 90>"; } // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM. def : TokenAlias<".s8", ".i8">; def : TokenAlias<".u8", ".i8">; def : TokenAlias<".s16", ".i16">; def : TokenAlias<".u16", ".i16">; def : TokenAlias<".s32", ".i32">; def : TokenAlias<".u32", ".i32">; def : TokenAlias<".s64", ".i64">; def : TokenAlias<".u64", ".i64">; def : TokenAlias<".i8", ".8">; def : TokenAlias<".i16", ".16">; def : TokenAlias<".i32", ".32">; def : TokenAlias<".i64", ".64">; def : TokenAlias<".p8", ".8">; def : TokenAlias<".p16", ".16">; def : TokenAlias<".f32", ".32">; def : TokenAlias<".f64", ".64">; def : TokenAlias<".f", ".f32">; def : TokenAlias<".d", ".f64">; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARMInstrInfo.td000064400000000000000000007320760072674642500244140ustar 00000000000000//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file describes the ARM instructions in TableGen format. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // ARM specific DAG Nodes. // // Type profiles. def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; def SDT_ARMStructByVal : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; def SDT_ARMCMov : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; def SDT_ARMBrcond : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; def SDT_ARMBrJT : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; def SDT_ARMBr2JT : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>, SDTCisVT<4, i32>, SDTCisVT<5, OtherVT>]>; def SDT_ARMAnd : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>]>; def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>]>; def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>; def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>; def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i32>]>; // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i32>, SDTCisVT<4, i32>]>; def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>, SDTCisSameAs<0, 5>]>; def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>; def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; // Node definitions. def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>; def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , SDT_ARMStructByVal, [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, SDNPMayLoad]>; def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, [SDNPInGlue]>; def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, [SDNPHasChain]>; def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, [SDNPHasChain]>; def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, [SDNPHasChain]>; def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, [SDNPOutGlue]>; def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, [SDNPOutGlue]>; def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, [SDNPOutGlue, SDNPCommutative]>; def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, [SDNPCommutative]>; def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain, SDNPSideEffect]>; def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain, SDNPSideEffect]>; def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", SDT_ARMEH_SJLJ_SetupDispatch, [SDNPHasChain, SDNPSideEffect]>; def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, [SDNPHasChain, SDNPSideEffect]>; def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, SDNPMayLoad]>; def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate<"HasV4TOps", "armv4t">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">, AssemblerPredicate<"HasV5TOps", "armv5t">; def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate<"HasV5TEOps", "armv5te">; def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate<"HasV6Ops", "armv6">; def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; def HasV6M : Predicate<"Subtarget->hasV6MOps()">, AssemblerPredicate<"HasV6MOps", "armv6m or armv6t2">; def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, AssemblerPredicate<"HasV8MBaselineOps", "armv8m.base">; def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, AssemblerPredicate<"HasV8MMainlineOps", "armv8m.main">; def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate<"HasV6T2Ops", "armv6t2">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; def HasV6K : Predicate<"Subtarget->hasV6KOps()">, AssemblerPredicate<"HasV6KOps", "armv6k">; def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate<"HasV7Ops", "armv7">; def HasV8 : Predicate<"Subtarget->hasV8Ops()">, AssemblerPredicate<"HasV8Ops", "armv8">; def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate<"FeatureVFP2", "VFP2">; def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate<"FeatureVFP3", "VFP3">; def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, AssemblerPredicate<"FeatureVFP4", "VFP4">; def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, AssemblerPredicate<"!FeatureVFPOnlySP", "double precision VFP">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "NEON">; def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, AssemblerPredicate<"FeatureSHA2", "sha2">; def HasAES : Predicate<"Subtarget->hasAES()">, AssemblerPredicate<"FeatureAES", "aes">; def HasCrypto : Predicate<"Subtarget->hasCrypto()">, AssemblerPredicate<"FeatureCrypto", "crypto">; def HasDotProd : Predicate<"Subtarget->hasDotProd()">, AssemblerPredicate<"FeatureDotProd", "dotprod">; def HasCRC : Predicate<"Subtarget->hasCRC()">, AssemblerPredicate<"FeatureCRC", "crc">; def HasRAS : Predicate<"Subtarget->hasRAS()">, AssemblerPredicate<"FeatureRAS", "ras">; def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate<"FeatureFP16","half-float conversions">; def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, AssemblerPredicate<"FeatureFullFP16","full half-float">; def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; def HasDSP : Predicate<"Subtarget->hasDSP()">, AssemblerPredicate<"FeatureDSP", "dsp">; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, AssemblerPredicate<"FeatureDB", "data-barriers">; def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, AssemblerPredicate<"FeatureDFB", "full-data-barrier">; def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, AssemblerPredicate<"FeatureV7Clrex", "v7 clrex">; def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, AssemblerPredicate<"FeatureAcquireRelease", "acquire/release">; def HasMP : Predicate<"Subtarget->hasMPExtension()">, AssemblerPredicate<"FeatureMP", "mp-extensions">; def HasVirtualization: Predicate<"false">, AssemblerPredicate<"FeatureVirtualization", "virtualization-extensions">; def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, AssemblerPredicate<"FeatureTrustZone", "TrustZone">; def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, AssemblerPredicate<"Feature8MSecExt", "ARMv8-M Security Extensions">; def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate<"ModeThumb", "thumb">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate<"ModeThumb,FeatureThumb2", "thumb2">; def IsMClass : Predicate<"Subtarget->isMClass()">, AssemblerPredicate<"FeatureMClass", "armv*m">; def IsNotMClass : Predicate<"!Subtarget->isMClass()">, AssemblerPredicate<"!FeatureMClass", "!armv*m">; def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate<"!ModeThumb", "arm-mode">; def IsMachO : Predicate<"Subtarget->isTargetMachO()">; def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, AssemblerPredicate<"FeatureNaClTrap", "NaCl">; def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; def UseNegativeImmediates : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates", "NegativeImmediates">; // FIXME: Eventually this will be just "hasV6T2Ops". let RecomputePerFunction = 1 in { def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">; def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">; } def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; def UseMulOps : Predicate<"Subtarget->useMulOps()">; // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. // But only select them if more precision in FP computation is allowed. // Do not use them for Darwin platforms. def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" " FPOpFusion::Fast && " " Subtarget->hasVFP4()) && " "!Subtarget->isTargetDarwin()">; def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" " FPOpFusion::Fast &&" " Subtarget->hasVFP4()) || " "Subtarget->isTargetDarwin()">; def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" "!Subtarget->useNEONForSinglePrecisionFP()">; def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" "Subtarget->useNEONForSinglePrecisionFP()">; let RecomputePerFunction = 1 in { def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; } def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; //===----------------------------------------------------------------------===// // ARM Flag Definitions. class RegConstraint { string Constraints = C; } //===----------------------------------------------------------------------===// // ARM specific transformation functions and pattern fragments. // // imm_neg_XFORM - Return the negation of an i32 immediate value. def imm_neg_XFORM : SDNodeXFormgetTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); }]>; // imm_not_XFORM - Return the complement of a i32 immediate value. def imm_not_XFORM : SDNodeXFormgetTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); }]>; /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. def imm16_31 : ImmLeaf= 16 && (int32_t)Imm < 32; }]>; // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. def sext_16_node : PatLeaf<(i32 GPR:$a), [{ if (CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17) return true; if (N->getOpcode() != ISD::SRA) return false; if (N->getOperand(0).getOpcode() != ISD::SHL) return false; auto *ShiftVal = dyn_cast(N->getOperand(1)); if (!ShiftVal || ShiftVal->getZExtValue() != 16) return false; ShiftVal = dyn_cast(N->getOperand(0)->getOperand(1)); if (!ShiftVal || ShiftVal->getZExtValue() != 16) return false; return true; }]>; /// Split a 32-bit immediate into two 16 bit parts. def hi16 : SDNodeXFormgetTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), MVT::i32); }]>; def lo16AllZero : PatLeaf<(i32 imm), [{ // Returns true if all low 16-bits are 0. return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; }], hi16>; class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; class UnOpFrag : PatFrag<(ops node:$Src), res>; // An 'and' node with a single use. def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ return N->hasOneUse(); }]>; // An 'xor' node with a single use. def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ return N->hasOneUse(); }]>; // An 'fmul' node with a single use. def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ return N->hasOneUse(); }]>; // An 'fadd' node which checks for single non-hazardous use. def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ return hasNoVMLxHazardUse(N); }]>; // An 'fsub' node which checks for single non-hazardous use. def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ return hasNoVMLxHazardUse(N); }]>; //===----------------------------------------------------------------------===// // Operand Definitions. // // Immediate operands with a shared generic asm render method. class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; } class ImmAsmOperandMinusOne : AsmOperandClass { let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; let DiagnosticType = "ImmRange" # Low # "_" # High; let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; } // Operands that are part of a memory addressing mode. class MemOperand : Operand { let OperandType = "OPERAND_MEMORY"; } // Branch target. // FIXME: rename brtarget to t2_brtarget def brtarget : Operand { let EncoderMethod = "getBranchTargetOpValue"; let OperandType = "OPERAND_PCREL"; let DecoderMethod = "DecodeT2BROperand"; } // Branches targeting ARM-mode must be divisible by 4 if they're a raw // immediate. def ARMBranchTarget : AsmOperandClass { let Name = "ARMBranchTarget"; } // Branches targeting Thumb-mode must be divisible by 2 if they're a raw // immediate. def ThumbBranchTarget : AsmOperandClass { let Name = "ThumbBranchTarget"; } def arm_br_target : Operand { let ParserMatchClass = ARMBranchTarget; let EncoderMethod = "getARMBranchTargetOpValue"; let OperandType = "OPERAND_PCREL"; } // Call target for ARM. Handles conditional/unconditional // FIXME: rename bl_target to t2_bltarget? def arm_bl_target : Operand { let ParserMatchClass = ARMBranchTarget; let EncoderMethod = "getARMBLTargetOpValue"; let OperandType = "OPERAND_PCREL"; } // Target for BLX *from* ARM mode. def arm_blx_target : Operand { let ParserMatchClass = ThumbBranchTarget; let EncoderMethod = "getARMBLXTargetOpValue"; let OperandType = "OPERAND_PCREL"; } // A list of registers separated by comma. Used by load/store multiple. def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } def reglist : Operand { let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = RegListAsmOperand; let PrintMethod = "printRegisterList"; let DecoderMethod = "DecodeRegListOperand"; } def GPRPairOp : RegisterOperand; def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; let DiagnosticType = "DPR_RegList"; } def dpr_reglist : Operand { let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = DPRRegListAsmOperand; let PrintMethod = "printRegisterList"; let DecoderMethod = "DecodeDPRRegListOperand"; } def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; } def spr_reglist : Operand { let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = SPRRegListAsmOperand; let PrintMethod = "printRegisterList"; let DecoderMethod = "DecodeSPRRegListOperand"; } // An operand for the CONSTPOOL_ENTRY pseudo-instruction. def cpinst_operand : Operand { let PrintMethod = "printCPInstOperand"; } // Local PC labels. def pclabel : Operand { let PrintMethod = "printPCLabel"; } // ADR instruction labels. def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } def adrlabel : Operand { let EncoderMethod = "getAdrLabelOpValue"; let ParserMatchClass = AdrLabelAsmOperand; let PrintMethod = "printAdrLabelOperand<0>"; } def neon_vcvt_imm32 : Operand { let EncoderMethod = "getNEONVcvtImm32OpValue"; let DecoderMethod = "DecodeVCVTImmOperand"; } // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. def rot_imm_XFORM: SDNodeXFormgetZExtValue()){ default: llvm_unreachable(nullptr); case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); } }]>; def RotImmAsmOperand : AsmOperandClass { let Name = "RotImm"; let ParserMethod = "parseRotImm"; } def rot_imm : Operand, PatLeaf<(i32 imm), [{ int32_t v = N->getZExtValue(); return v == 8 || v == 16 || v == 24; }], rot_imm_XFORM> { let PrintMethod = "printRotImmOperand"; let ParserMatchClass = RotImmAsmOperand; } // shift_imm: An integer that encodes a shift amount and the type of shift // (asr or lsl). The 6-bit immediate encodes as: // {5} 0 ==> lsl // 1 asr // {4-0} imm5 shift amount. // asr #32 encoded as imm5 == 0. def ShifterImmAsmOperand : AsmOperandClass { let Name = "ShifterImm"; let ParserMethod = "parseShifterImm"; } def shift_imm : Operand { let PrintMethod = "printShiftImmOperand"; let ParserMatchClass = ShifterImmAsmOperand; } // shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } def so_reg_reg : Operand, // reg reg imm ComplexPattern { let EncoderMethod = "getSORegRegOpValue"; let PrintMethod = "printSORegRegOperand"; let DecoderMethod = "DecodeSORegRegOperand"; let ParserMatchClass = ShiftedRegAsmOperand; let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); } def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } def so_reg_imm : Operand, // reg imm ComplexPattern { let EncoderMethod = "getSORegImmOpValue"; let PrintMethod = "printSORegImmOperand"; let DecoderMethod = "DecodeSORegImmOperand"; let ParserMatchClass = ShiftedImmAsmOperand; let MIOperandInfo = (ops GPR, i32imm); } // FIXME: Does this need to be distinct from so_reg? def shift_so_reg_reg : Operand, // reg reg imm ComplexPattern { let EncoderMethod = "getSORegRegOpValue"; let PrintMethod = "printSORegRegOperand"; let DecoderMethod = "DecodeSORegRegOperand"; let ParserMatchClass = ShiftedRegAsmOperand; let MIOperandInfo = (ops GPR, GPR, i32imm); } // FIXME: Does this need to be distinct from so_reg? def shift_so_reg_imm : Operand, // reg reg imm ComplexPattern { let EncoderMethod = "getSORegImmOpValue"; let PrintMethod = "printSORegImmOperand"; let DecoderMethod = "DecodeSORegImmOperand"; let ParserMatchClass = ShiftedImmAsmOperand; let MIOperandInfo = (ops GPR, i32imm); } // mod_imm: match a 32-bit immediate operand, which can be encoded into // a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM // - "Modified Immediate Constants"). Within the MC layer we keep this // immediate in its encoded form. def ModImmAsmOperand: AsmOperandClass { let Name = "ModImm"; let ParserMethod = "parseModImm"; } def mod_imm : Operand, ImmLeaf { let EncoderMethod = "getModImmOpValue"; let PrintMethod = "printModImmOperand"; let ParserMatchClass = ModImmAsmOperand; } // Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder // method and such, as they are only used on aliases (Pat<> and InstAlias<>). // The actual parsing, encoding, decoding are handled by the destination // instructions, which use mod_imm. def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } def mod_imm_not : Operand, PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; }], imm_not_XFORM> { let ParserMatchClass = ModImmNotAsmOperand; } def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } def mod_imm_neg : Operand, PatLeaf<(imm), [{ unsigned Value = -(unsigned)N->getZExtValue(); return Value && ARM_AM::getSOImmVal(Value) != -1; }], imm_neg_XFORM> { let ParserMatchClass = ModImmNegAsmOperand; } /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() def arm_i32imm : PatLeaf<(imm), [{ if (Subtarget->useMovt(*MF)) return true; return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); }]>; /// imm0_1 predicate - Immediate in the range [0,1]. def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } def imm0_1 : Operand { let ParserMatchClass = Imm0_1AsmOperand; } /// imm0_3 predicate - Immediate in the range [0,3]. def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } def imm0_3 : Operand { let ParserMatchClass = Imm0_3AsmOperand; } /// imm0_7 predicate - Immediate in the range [0,7]. def Imm0_7AsmOperand: ImmAsmOperand<0,7> { let Name = "Imm0_7"; } def imm0_7 : Operand, ImmLeaf= 0 && Imm < 8; }]> { let ParserMatchClass = Imm0_7AsmOperand; } /// imm8_255 predicate - Immediate in the range [8,255]. def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } def imm8_255 : Operand, ImmLeaf= 8 && Imm < 256; }]> { let ParserMatchClass = Imm8_255AsmOperand; } /// imm8 predicate - Immediate is exactly 8. def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } def imm8 : Operand, ImmLeaf { let ParserMatchClass = Imm8AsmOperand; } /// imm16 predicate - Immediate is exactly 16. def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } def imm16 : Operand, ImmLeaf { let ParserMatchClass = Imm16AsmOperand; } /// imm32 predicate - Immediate is exactly 32. def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } def imm32 : Operand, ImmLeaf { let ParserMatchClass = Imm32AsmOperand; } def imm8_or_16 : ImmLeaf; /// imm1_7 predicate - Immediate in the range [1,7]. def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } def imm1_7 : Operand, ImmLeaf 0 && Imm < 8; }]> { let ParserMatchClass = Imm1_7AsmOperand; } /// imm1_15 predicate - Immediate in the range [1,15]. def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } def imm1_15 : Operand, ImmLeaf 0 && Imm < 16; }]> { let ParserMatchClass = Imm1_15AsmOperand; } /// imm1_31 predicate - Immediate in the range [1,31]. def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } def imm1_31 : Operand, ImmLeaf 0 && Imm < 32; }]> { let ParserMatchClass = Imm1_31AsmOperand; } /// imm0_15 predicate - Immediate in the range [0,15]. def Imm0_15AsmOperand: ImmAsmOperand<0,15> { let Name = "Imm0_15"; } def imm0_15 : Operand, ImmLeaf= 0 && Imm < 16; }]> { let ParserMatchClass = Imm0_15AsmOperand; } /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } def imm0_31 : Operand, ImmLeaf= 0 && Imm < 32; }]> { let ParserMatchClass = Imm0_31AsmOperand; } /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } def imm0_32 : Operand, ImmLeaf= 0 && Imm < 33; }]> { let ParserMatchClass = Imm0_32AsmOperand; } /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } def imm0_63 : Operand, ImmLeaf= 0 && Imm < 64; }]> { let ParserMatchClass = Imm0_63AsmOperand; } /// imm0_239 predicate - Immediate in the range [0,239]. def Imm0_239AsmOperand : ImmAsmOperand<0,239> { let Name = "Imm0_239"; } def imm0_239 : Operand, ImmLeaf= 0 && Imm < 240; }]> { let ParserMatchClass = Imm0_239AsmOperand; } /// imm0_255 predicate - Immediate in the range [0,255]. def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } def imm0_255 : Operand, ImmLeaf= 0 && Imm < 256; }]> { let ParserMatchClass = Imm0_255AsmOperand; } /// imm0_65535 - An immediate is in the range [0,65535]. def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } def imm0_65535 : Operand, ImmLeaf= 0 && Imm < 65536; }]> { let ParserMatchClass = Imm0_65535AsmOperand; } // imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. def imm0_65535_neg : Operand, ImmLeaf= 0 && -Imm < 65536; }]>; // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference // a relocatable expression. // // FIXME: This really needs a Thumb version separate from the ARM version. // While the range is the same, and can thus use the same match class, // the encoding is different so it should have a different encoder method. def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; let RenderMethod = "addImmOperands"; let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; } def imm0_65535_expr : Operand { let EncoderMethod = "getHiLo16ImmOpValue"; let ParserMatchClass = Imm0_65535ExprAsmOperand; } def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } def imm256_65535_expr : Operand { let ParserMatchClass = Imm256_65535ExprAsmOperand; } /// imm24b - True if the 32-bit immediate is encodable in 24 bits. def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { let Name = "Imm24bit"; let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; } def imm24b : Operand, ImmLeaf= 0 && Imm <= 0xffffff; }]> { let ParserMatchClass = Imm24bitAsmOperand; } /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield /// e.g., 0xf000ffff def BitfieldAsmOperand : AsmOperandClass { let Name = "Bitfield"; let ParserMethod = "parseBitfield"; } def bf_inv_mask_imm : Operand, PatLeaf<(imm), [{ return ARM::isBitFieldInvertedMask(N->getZExtValue()); }] > { let EncoderMethod = "getBitfieldInvertedMaskOpValue"; let PrintMethod = "printBitfieldInvMaskImmOperand"; let DecoderMethod = "DecodeBitfieldMaskOperand"; let ParserMatchClass = BitfieldAsmOperand; let GISelPredicateCode = [{ // There's better methods of implementing this check. IntImmLeaf<> would be // equivalent and have less boilerplate but we need a test for C++ // predicates and this one causes new rules to be imported into GlobalISel // without requiring additional features first. const auto &MO = MI.getOperand(1); if (!MO.isCImm()) return false; return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); }]; } def imm1_32_XFORM: SDNodeXFormgetTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), MVT::i32); }]>; def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { let Name = "Imm1_32"; } def imm1_32 : Operand, PatLeaf<(imm), [{ uint64_t Imm = N->getZExtValue(); return Imm > 0 && Imm <= 32; }], imm1_32_XFORM> { let PrintMethod = "printImmPlusOneOperand"; let ParserMatchClass = Imm1_32AsmOperand; } def imm1_16_XFORM: SDNodeXFormgetTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), MVT::i32); }]>; def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } def imm1_16 : Operand, ImmLeaf 0 && Imm <= 16; }], imm1_16_XFORM> { let PrintMethod = "printImmPlusOneOperand"; let ParserMatchClass = Imm1_16AsmOperand; } // Define ARM specific addressing modes. // addrmode_imm12 := reg +/- imm12 // def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } class AddrMode_Imm12 : MemOperand, ComplexPattern { // 12-bit immediate operand. Note that instructions using this encode // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other // immediate values are as normal. let EncoderMethod = "getAddrModeImm12OpValue"; let DecoderMethod = "DecodeAddrModeImm12Operand"; let ParserMatchClass = MemImm12OffsetAsmOperand; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } def addrmode_imm12 : AddrMode_Imm12 { let PrintMethod = "printAddrModeImm12Operand"; } def addrmode_imm12_pre : AddrMode_Imm12 { let PrintMethod = "printAddrModeImm12Operand"; } // ldst_so_reg := reg +/- reg shop imm // def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } def ldst_so_reg : MemOperand, ComplexPattern { let EncoderMethod = "getLdStSORegOpValue"; // FIXME: Simplify the printer let PrintMethod = "printAddrMode2Operand"; let DecoderMethod = "DecodeSORegMemOperand"; let ParserMatchClass = MemRegOffsetAsmOperand; let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); } // postidx_imm8 := +/- [0,255] // // 9 bit value: // {8} 1 is imm8 is non-negative. 0 otherwise. // {7-0} [0,255] imm8 value. def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } def postidx_imm8 : MemOperand { let PrintMethod = "printPostIdxImm8Operand"; let ParserMatchClass = PostIdxImm8AsmOperand; let MIOperandInfo = (ops i32imm); } // postidx_imm8s4 := +/- [0,1020] // // 9 bit value: // {8} 1 is imm8 is non-negative. 0 otherwise. // {7-0} [0,255] imm8 value, scaled by 4. def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } def postidx_imm8s4 : MemOperand { let PrintMethod = "printPostIdxImm8s4Operand"; let ParserMatchClass = PostIdxImm8s4AsmOperand; let MIOperandInfo = (ops i32imm); } // postidx_reg := +/- reg // def PostIdxRegAsmOperand : AsmOperandClass { let Name = "PostIdxReg"; let ParserMethod = "parsePostIdxReg"; } def postidx_reg : MemOperand { let EncoderMethod = "getPostIdxRegOpValue"; let DecoderMethod = "DecodePostIdxReg"; let PrintMethod = "printPostIdxRegOperand"; let ParserMatchClass = PostIdxRegAsmOperand; let MIOperandInfo = (ops GPRnopc, i32imm); } def PostIdxRegShiftedAsmOperand : AsmOperandClass { let Name = "PostIdxRegShifted"; let ParserMethod = "parsePostIdxReg"; } def am2offset_reg : MemOperand, ComplexPattern { let EncoderMethod = "getAddrMode2OffsetOpValue"; let PrintMethod = "printAddrMode2OffsetOperand"; // When using this for assembly, it's always as a post-index offset. let ParserMatchClass = PostIdxRegShiftedAsmOperand; let MIOperandInfo = (ops GPRnopc, i32imm); } // FIXME: am2offset_imm should only need the immediate, not the GPR. Having // the GPR is purely vestigal at this point. def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } def am2offset_imm : MemOperand, ComplexPattern { let EncoderMethod = "getAddrMode2OffsetOpValue"; let PrintMethod = "printAddrMode2OffsetOperand"; let ParserMatchClass = AM2OffsetImmAsmOperand; let MIOperandInfo = (ops GPRnopc, i32imm); } // addrmode3 := reg +/- reg // addrmode3 := reg +/- imm8 // // FIXME: split into imm vs. reg versions. def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } class AddrMode3 : MemOperand, ComplexPattern { let EncoderMethod = "getAddrMode3OpValue"; let ParserMatchClass = AddrMode3AsmOperand; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } def addrmode3 : AddrMode3 { let PrintMethod = "printAddrMode3Operand"; } def addrmode3_pre : AddrMode3 { let PrintMethod = "printAddrMode3Operand"; } // FIXME: split into imm vs. reg versions. // FIXME: parser method to handle +/- register. def AM3OffsetAsmOperand : AsmOperandClass { let Name = "AM3Offset"; let ParserMethod = "parseAM3Offset"; } def am3offset : MemOperand, ComplexPattern { let EncoderMethod = "getAddrMode3OffsetOpValue"; let PrintMethod = "printAddrMode3OffsetOperand"; let ParserMatchClass = AM3OffsetAsmOperand; let MIOperandInfo = (ops GPR, i32imm); } // ldstm_mode := {ia, ib, da, db} // def ldstm_mode : OptionalDefOperand { let EncoderMethod = "getLdStmModeOpValue"; let PrintMethod = "printLdStmModeOperand"; } // addrmode5 := reg +/- imm8*4 // def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } class AddrMode5 : MemOperand, ComplexPattern { let EncoderMethod = "getAddrMode5OpValue"; let DecoderMethod = "DecodeAddrMode5Operand"; let ParserMatchClass = AddrMode5AsmOperand; let MIOperandInfo = (ops GPR:$base, i32imm); } def addrmode5 : AddrMode5 { let PrintMethod = "printAddrMode5Operand"; } def addrmode5_pre : AddrMode5 { let PrintMethod = "printAddrMode5Operand"; } // addrmode5fp16 := reg +/- imm8*2 // def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } class AddrMode5FP16 : Operand, ComplexPattern { let EncoderMethod = "getAddrMode5FP16OpValue"; let DecoderMethod = "DecodeAddrMode5FP16Operand"; let ParserMatchClass = AddrMode5FP16AsmOperand; let MIOperandInfo = (ops GPR:$base, i32imm); } def addrmode5fp16 : AddrMode5FP16 { let PrintMethod = "printAddrMode5FP16Operand"; } // addrmode6 := reg with optional alignment // def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } def addrmode6 : MemOperand, ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm:$align); let EncoderMethod = "getAddrMode6AddressOpValue"; let DecoderMethod = "DecodeAddrMode6Operand"; let ParserMatchClass = AddrMode6AsmOperand; } def am6offset : MemOperand, ComplexPattern { let PrintMethod = "printAddrMode6OffsetOperand"; let MIOperandInfo = (ops GPR); let EncoderMethod = "getAddrMode6OffsetOpValue"; let DecoderMethod = "DecodeGPRRegisterClass"; } // Special version of addrmode6 to handle alignment encoding for VST1/VLD1 // (single element from one lane) for size 32. def addrmode6oneL32 : MemOperand, ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; } // Base class for addrmode6 with specific alignment restrictions. class AddrMode6Align : MemOperand, ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm:$align); let EncoderMethod = "getAddrMode6AddressOpValue"; let DecoderMethod = "DecodeAddrMode6Operand"; } // Special version of addrmode6 to handle no allowed alignment encoding for // VLD/VST instructions and checking the alignment is not specified. def AddrMode6AlignNoneAsmOperand : AsmOperandClass { let Name = "AlignedMemoryNone"; let DiagnosticString = "alignment must be omitted"; } def addrmode6alignNone : AddrMode6Align { // The alignment specifier can only be omitted. let ParserMatchClass = AddrMode6AlignNoneAsmOperand; } // Special version of addrmode6 to handle 16-bit alignment encoding for // VLD/VST instructions and checking the alignment value. def AddrMode6Align16AsmOperand : AsmOperandClass { let Name = "AlignedMemory16"; let DiagnosticString = "alignment must be 16 or omitted"; } def addrmode6align16 : AddrMode6Align { // The alignment specifier can only be 16 or omitted. let ParserMatchClass = AddrMode6Align16AsmOperand; } // Special version of addrmode6 to handle 32-bit alignment encoding for // VLD/VST instructions and checking the alignment value. def AddrMode6Align32AsmOperand : AsmOperandClass { let Name = "AlignedMemory32"; let DiagnosticString = "alignment must be 32 or omitted"; } def addrmode6align32 : AddrMode6Align { // The alignment specifier can only be 32 or omitted. let ParserMatchClass = AddrMode6Align32AsmOperand; } // Special version of addrmode6 to handle 64-bit alignment encoding for // VLD/VST instructions and checking the alignment value. def AddrMode6Align64AsmOperand : AsmOperandClass { let Name = "AlignedMemory64"; let DiagnosticString = "alignment must be 64 or omitted"; } def addrmode6align64 : AddrMode6Align { // The alignment specifier can only be 64 or omitted. let ParserMatchClass = AddrMode6Align64AsmOperand; } // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding // for VLD/VST instructions and checking the alignment value. def AddrMode6Align64or128AsmOperand : AsmOperandClass { let Name = "AlignedMemory64or128"; let DiagnosticString = "alignment must be 64, 128 or omitted"; } def addrmode6align64or128 : AddrMode6Align { // The alignment specifier can only be 64, 128 or omitted. let ParserMatchClass = AddrMode6Align64or128AsmOperand; } // Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment // encoding for VLD/VST instructions and checking the alignment value. def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { let Name = "AlignedMemory64or128or256"; let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; } def addrmode6align64or128or256 : AddrMode6Align { // The alignment specifier can only be 64, 128, 256 or omitted. let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; } // Special version of addrmode6 to handle alignment encoding for VLD-dup // instructions, specifically VLD4-dup. def addrmode6dup : MemOperand, ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); let EncoderMethod = "getAddrMode6DupAddressOpValue"; // FIXME: This is close, but not quite right. The alignment specifier is // different. let ParserMatchClass = AddrMode6AsmOperand; } // Base class for addrmode6dup with specific alignment restrictions. class AddrMode6DupAlign : MemOperand, ComplexPattern{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); let EncoderMethod = "getAddrMode6DupAddressOpValue"; } // Special version of addrmode6 to handle no allowed alignment encoding for // VLD-dup instruction and checking the alignment is not specified. def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { let Name = "DupAlignedMemoryNone"; let DiagnosticString = "alignment must be omitted"; } def addrmode6dupalignNone : AddrMode6DupAlign { // The alignment specifier can only be omitted. let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; } // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup // instruction and checking the alignment value. def AddrMode6dupAlign16AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory16"; let DiagnosticString = "alignment must be 16 or omitted"; } def addrmode6dupalign16 : AddrMode6DupAlign { // The alignment specifier can only be 16 or omitted. let ParserMatchClass = AddrMode6dupAlign16AsmOperand; } // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup // instruction and checking the alignment value. def AddrMode6dupAlign32AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory32"; let DiagnosticString = "alignment must be 32 or omitted"; } def addrmode6dupalign32 : AddrMode6DupAlign { // The alignment specifier can only be 32 or omitted. let ParserMatchClass = AddrMode6dupAlign32AsmOperand; } // Special version of addrmode6 to handle 64-bit alignment encoding for VLD // instructions and checking the alignment value. def AddrMode6dupAlign64AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory64"; let DiagnosticString = "alignment must be 64 or omitted"; } def addrmode6dupalign64 : AddrMode6DupAlign { // The alignment specifier can only be 64 or omitted. let ParserMatchClass = AddrMode6dupAlign64AsmOperand; } // Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding // for VLD instructions and checking the alignment value. def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory64or128"; let DiagnosticString = "alignment must be 64, 128 or omitted"; } def addrmode6dupalign64or128 : AddrMode6DupAlign { // The alignment specifier can only be 64, 128 or omitted. let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; } // addrmodepc := pc + reg // def addrmodepc : MemOperand, ComplexPattern { let PrintMethod = "printAddrModePCOperand"; let MIOperandInfo = (ops GPR, i32imm); } // addr_offset_none := reg // def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } def addr_offset_none : MemOperand, ComplexPattern { let PrintMethod = "printAddrMode7Operand"; let DecoderMethod = "DecodeAddrMode7Operand"; let ParserMatchClass = MemNoOffsetAsmOperand; let MIOperandInfo = (ops GPR:$base); } def nohash_imm : Operand { let PrintMethod = "printNoHashImmediate"; } def CoprocNumAsmOperand : AsmOperandClass { let Name = "CoprocNum"; let ParserMethod = "parseCoprocNumOperand"; } def p_imm : Operand { let PrintMethod = "printPImmediate"; let ParserMatchClass = CoprocNumAsmOperand; let DecoderMethod = "DecodeCoprocessor"; } def CoprocRegAsmOperand : AsmOperandClass { let Name = "CoprocReg"; let ParserMethod = "parseCoprocRegOperand"; } def c_imm : Operand { let PrintMethod = "printCImmediate"; let ParserMatchClass = CoprocRegAsmOperand; } def CoprocOptionAsmOperand : AsmOperandClass { let Name = "CoprocOption"; let ParserMethod = "parseCoprocOptionOperand"; } def coproc_option_imm : Operand { let PrintMethod = "printCoprocOptionImm"; let ParserMatchClass = CoprocOptionAsmOperand; } //===----------------------------------------------------------------------===// include "ARMInstrFormats.td" //===----------------------------------------------------------------------===// // Multiclass helpers... // /// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a /// binop that produces a value. let TwoOperandAliasConstraint = "$Rn = $Rd" in multiclass AsI1_bin_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, SDPatternOperator opnode, bit Commutable = 0> { // The register-immediate version is re-materializable. This is useful // in particular for taking the address of a local. let isReMaterializable = 1 in { def ri : AsI1, Sched<[WriteALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> imm; let Inst{25} = 1; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-0} = imm; } } def rr : AsI1, Sched<[WriteALU, ReadALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{25} = 0; let isCommutable = Commutable; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-4} = 0b00000000; let Inst{3-0} = Rm; } def rsi : AsI1, Sched<[WriteALUsi, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; } def rsr : AsI1, Sched<[WriteALUsr, ReadALUsr]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; } } /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are /// reversed. The 'rr' form is only defined for the disassembler; for codegen /// it is equivalent to the AsI1_bin_irs counterpart. let TwoOperandAliasConstraint = "$Rn = $Rd" in multiclass AsI1_rbin_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, SDNode opnode, bit Commutable = 0> { // The register-immediate version is re-materializable. This is useful // in particular for taking the address of a local. let isReMaterializable = 1 in { def ri : AsI1, Sched<[WriteALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> imm; let Inst{25} = 1; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-0} = imm; } } def rr : AsI1, Sched<[WriteALU, ReadALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let Inst{3-0} = Rm; let Inst{15-12} = Rd; let Inst{19-16} = Rn; } def rsi : AsI1, Sched<[WriteALUsi, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; } def rsr : AsI1, Sched<[WriteALUsr, ReadALUsr]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; } } /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. /// /// These opcodes will be converted to the real non-S opcodes by /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. let hasPostISelHook = 1, Defs = [CPSR] in { multiclass AsI1_bin_s_irs { def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 4, iii, [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, Sched<[WriteALU, ReadALU]>; def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 4, iir, [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, Sched<[WriteALU, ReadALU, ReadALU]> { let isCommutable = Commutable; } def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 4, iis, [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]>, Sched<[WriteALUsi, ReadALU]>; def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 4, iis, [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]>, Sched<[WriteALUSsr, ReadALUsr]>; } } /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG /// operands are reversed. let hasPostISelHook = 1, Defs = [CPSR] in { multiclass AsI1_rbin_s_is { def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 4, iii, [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, Sched<[WriteALU, ReadALU]>; def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 4, iis, [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]>, Sched<[WriteALUsi, ReadALU]>; def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 4, iis, [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]>, Sched<[WriteALUSsr, ReadALUsr]>; } } /// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test /// patterns. Similar to AsI1_bin_irs except the instruction does not produce /// a explicit result, only implicitly set CPSR. let isCompare = 1, Defs = [CPSR] in { multiclass AI1_cmp_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, SDPatternOperator opnode, bit Commutable = 0, string rrDecoderMethod = ""> { def ri : AI1, Sched<[WriteCMP, ReadALU]> { bits<4> Rn; bits<12> imm; let Inst{25} = 1; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-0} = imm; let Unpredictable{15-12} = 0b1111; } def rr : AI1, Sched<[WriteCMP, ReadALU, ReadALU]> { bits<4> Rn; bits<4> Rm; let isCommutable = Commutable; let Inst{25} = 0; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-4} = 0b00000000; let Inst{3-0} = Rm; let DecoderMethod = rrDecoderMethod; let Unpredictable{15-12} = 0b1111; } def rsi : AI1, Sched<[WriteCMPsi, ReadALU]> { bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; let Unpredictable{15-12} = 0b1111; } def rsr : AI1, Sched<[WriteCMPsr, ReadALU]> { bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; let Unpredictable{15-12} = 0b1111; } } } /// AI_ext_rrot - A unary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. /// FIXME: Remove the 'r' variant. Its rot_imm is zero. class AI_ext_rrot opcod, string opc, PatFrag opnode> : AExtI, Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { bits<4> Rd; bits<4> Rm; bits<2> rot; let Inst{19-16} = 0b1111; let Inst{15-12} = Rd; let Inst{11-10} = rot; let Inst{3-0} = Rm; } class AI_ext_rrot_np opcod, string opc> : AExtI, Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { bits<2> rot; let Inst{19-16} = 0b1111; let Inst{11-10} = rot; } /// AI_exta_rrot - A binary operation with two forms: one whose operand is a /// register and one whose operand is a register rotated by 8/16/24. class AI_exta_rrot opcod, string opc, PatFrag opnode> : AExtI, Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { bits<4> Rd; bits<4> Rm; bits<4> Rn; bits<2> rot; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-10} = rot; let Inst{9-4} = 0b000111; let Inst{3-0} = Rm; } class AI_exta_rrot_np opcod, string opc> : AExtI, Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { bits<4> Rn; bits<2> rot; let Inst{19-16} = Rn; let Inst{11-10} = rot; } /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. let TwoOperandAliasConstraint = "$Rn = $Rd" in multiclass AI1_adde_sube_irs opcod, string opc, SDNode opnode, bit Commutable = 0> { let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { def ri : AsI1, Requires<[IsARM]>, Sched<[WriteALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> imm; let Inst{25} = 1; let Inst{15-12} = Rd; let Inst{19-16} = Rn; let Inst{11-0} = imm; } def rr : AsI1, Requires<[IsARM]>, Sched<[WriteALU, ReadALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let isCommutable = Commutable; let Inst{3-0} = Rm; let Inst{15-12} = Rd; let Inst{19-16} = Rn; } def rsi : AsI1, Requires<[IsARM]>, Sched<[WriteALUsi, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; } def rsr : AsI1, Requires<[IsARM]>, Sched<[WriteALUsr, ReadALUsr]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; } } } /// AI1_rsc_irs - Define instructions and patterns for rsc let TwoOperandAliasConstraint = "$Rn = $Rd" in multiclass AI1_rsc_irs opcod, string opc, SDNode opnode> { let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { def ri : AsI1, Requires<[IsARM]>, Sched<[WriteALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> imm; let Inst{25} = 1; let Inst{15-12} = Rd; let Inst{19-16} = Rn; let Inst{11-0} = imm; } def rr : AsI1, Sched<[WriteALU, ReadALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let Inst{3-0} = Rm; let Inst{15-12} = Rd; let Inst{19-16} = Rn; } def rsi : AsI1, Requires<[IsARM]>, Sched<[WriteALUsi, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; } def rsr : AsI1, Requires<[IsARM]>, Sched<[WriteALUsr, ReadALUsr]> { bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; } } } let canFoldAsLoad = 1, isReMaterializable = 1 in { multiclass AI_ldr1 { // Note: We use the complex addrmode_imm12 rather than just an input // GPR and a constrained immediate so that we can use this to match // frame index references and avoid matching constant pool references. def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { bits<4> Rt; bits<17> addr; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { bits<4> Rt; bits<17> shift; let shift{4} = 0; // Inst{4} = 0 let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = shift{11-0}; } } } let canFoldAsLoad = 1, isReMaterializable = 1 in { multiclass AI_ldr1nopc { // Note: We use the complex addrmode_imm12 rather than just an input // GPR and a constrained immediate so that we can use this to match // frame index references and avoid matching constant pool references. def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr), AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { bits<4> Rt; bits<17> addr; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift), AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { bits<4> Rt; bits<17> shift; let shift{4} = 0; // Inst{4} = 0 let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = shift{11-0}; } } } multiclass AI_str1 { // Note: We use the complex addrmode_imm12 rather than just an input // GPR and a constrained immediate so that we can use this to match // frame index references and avoid matching constant pool references. def i12 : AI2ldst<0b010, 0, isByte, (outs), (ins GPR:$Rt, addrmode_imm12:$addr), AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { bits<4> Rt; bits<17> addr; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { bits<4> Rt; bits<17> shift; let shift{4} = 0; // Inst{4} = 0 let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = shift{11-0}; } } multiclass AI_str1nopc { // Note: We use the complex addrmode_imm12 rather than just an input // GPR and a constrained immediate so that we can use this to match // frame index references and avoid matching constant pool references. def i12 : AI2ldst<0b010, 0, isByte, (outs), (ins GPRnopc:$Rt, addrmode_imm12:$addr), AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { bits<4> Rt; bits<17> addr; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift), AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { bits<4> Rt; bits<17> shift; let shift{4} = 0; // Inst{4} = 0 let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = Rt; let Inst{11-0} = shift{11-0}; } } //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Miscellaneous Instructions. // /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in /// the function. The first operand is the ID# for this instruction, the second /// is the index into the MachineConstantPool that this is, the third is the /// size in bytes of this constant pool entry. let hasSideEffects = 0, isNotDuplicable = 1 in def CONSTPOOL_ENTRY : PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), NoItinerary, []>; /// A jumptable consisting of direct 32-bit addresses of the destination basic /// blocks (either absolute, or relative to the start of the jump-table in PIC /// mode). Used mostly in ARM and Thumb-1 modes. def JUMPTABLE_ADDRS : PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), NoItinerary, []>; /// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables /// that cannot be optimised to use TBB or TBH. def JUMPTABLE_INSTS : PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), NoItinerary, []>; /// A jumptable consisting of 8-bit unsigned integers representing offsets from /// a TBB instruction. def JUMPTABLE_TBB : PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), NoItinerary, []>; /// A jumptable consisting of 16-bit unsigned integers representing offsets from /// a TBH instruction. def JUMPTABLE_TBH : PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size), NoItinerary, []>; // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE // from removing one half of the matched pairs. That breaks PEI, which assumes // these will always be in pairs, and asserts if it finds otherwise. Better way? let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { def ADJCALLSTACKUP : PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, [(ARMcallseq_start timm:$amt, timm:$amt2)]>; } def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, Requires<[IsARM, HasV6]> { bits<8> imm; let Inst{27-8} = 0b00110010000011110000; let Inst{7-0} = imm; let DecoderMethod = "DecodeHINTInstruction"; } def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV6]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{3-0} = Rm; let Inst{15-12} = Rd; let Inst{19-16} = Rn; let Inst{27-20} = 0b01101000; let Inst{7-4} = 0b1011; let Inst{11-8} = 0b1111; let Unpredictable{11-8} = 0b1111; } // The 16-bit operand $val can be used by a debugger to store more information // about the breakpoint. def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, "bkpt", "\t$val", []>, Requires<[IsARM]> { bits<16> val; let Inst{3-0} = val{3-0}; let Inst{19-8} = val{15-4}; let Inst{27-20} = 0b00010010; let Inst{31-28} = 0xe; // AL let Inst{7-4} = 0b0111; } // default immediate for breakpoint mnemonic def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { bits<16> val; let Inst{3-0} = val{3-0}; let Inst{19-8} = val{15-4}; let Inst{27-20} = 0b00010000; let Inst{31-28} = 0xe; // AL let Inst{7-4} = 0b0111; } // Change Processor State // FIXME: We should use InstAlias to handle the optional operands. class CPS : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), []>, Requires<[IsARM]> { bits<2> imod; bits<3> iflags; bits<5> mode; bit M; let Inst{31-28} = 0b1111; let Inst{27-20} = 0b00010000; let Inst{19-18} = imod; let Inst{17} = M; // Enabled if mode is set; let Inst{16-9} = 0b00000000; let Inst{8-6} = iflags; let Inst{5} = 0; let Inst{4-0} = mode; } let DecoderMethod = "DecodeCPSInstruction" in { let M = 1 in def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), "$imod\t$iflags, $mode">; let mode = 0, M = 0 in def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; let imod = 0, iflags = 0, M = 1 in def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; } // Preload signals the memory system of possible future data/instruction access. multiclass APreLoad read, bits<1> data, string opc> { def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, IIC_Preload, !strconcat(opc, "\t$addr"), [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, Sched<[WritePreLd]> { bits<4> Rt; bits<17> addr; let Inst{31-26} = 0b111101; let Inst{25} = 0; // 0 for immediate form let Inst{24} = data; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{22} = read; let Inst{21-20} = 0b01; let Inst{19-16} = addr{16-13}; // Rn let Inst{15-12} = 0b1111; let Inst{11-0} = addr{11-0}; // imm12 } def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, !strconcat(opc, "\t$shift"), [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, Sched<[WritePreLd]> { bits<17> shift; let Inst{31-26} = 0b111101; let Inst{25} = 1; // 1 for register form let Inst{24} = data; let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{22} = read; let Inst{21-20} = 0b01; let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = 0b1111; let Inst{11-0} = shift{11-0}; let Inst{4} = 0; } } defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, "setend\t$end", []>, Requires<[IsARM]>, Deprecated { bits<1> end; let Inst{31-10} = 0b1111000100000001000000; let Inst{9} = end; let Inst{8-0} = 0; } def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { bits<4> opt; let Inst{27-4} = 0b001100100000111100001111; let Inst{3-0} = opt; } // A8.8.247 UDF - Undefined (Encoding A1) def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { bits<16> imm16; let Inst{31-28} = 0b1110; // AL let Inst{27-25} = 0b011; let Inst{24-20} = 0b11111; let Inst{19-8} = imm16{15-4}; let Inst{7-4} = 0b1111; let Inst{3-0} = imm16{3-0}; } /* * A5.4 Permanently UNDEFINED instructions. * * For most targets use UDF #65006, for which the OS will generate SIGTRAP. * Other UDF encodings generate SIGILL. * * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. * Encoding A1: * 1110 0111 1111 iiii iiii iiii 1111 iiii * Encoding T1: * 1101 1110 iiii iiii * It uses the following encoding: * 1110 0111 1111 1110 1101 1110 1111 0000 * - In ARM: UDF #60896; * - In Thumb: UDF #254 followed by a branch-to-self. */ let isBarrier = 1, isTerminator = 1 in def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, "trap", [(trap)]>, Requires<[IsARM,UseNaClTrap]> { let Inst = 0xe7fedef0; } let isBarrier = 1, isTerminator = 1 in def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, "trap", [(trap)]>, Requires<[IsARM,DontUseNaClTrap]> { let Inst = 0xe7ffdefe; } // Address computation and loads and stores in PIC mode. let isNotDuplicable = 1 in { def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 4, IIC_iALUr, [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, Sched<[WriteALU, ReadALU]>; let AddedComplexity = 10 in { def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 4, IIC_iLoad_r, [(set GPR:$dst, (load addrmodepc:$addr))]>; def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 4, IIC_iLoad_bh_r, [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; } let AddedComplexity = 10 in { def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; } } // isNotDuplicable = 1 // LEApcrel - Load a pc-relative address into a register without offending the // assembler. let hasSideEffects = 0, isReMaterializable = 1 in // The 'adr' mnemonic encodes differently if the label is before or after // the instruction. The {24-21} opcode bits are set by the fixup, as we don't // know until then which form of the instruction will be used. def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, Sched<[WriteALU, ReadALU]> { bits<4> Rd; bits<14> label; let Inst{27-25} = 0b001; let Inst{24} = 0; let Inst{23-22} = label{13-12}; let Inst{21} = 0; let Inst{20} = 0; let Inst{19-16} = 0b1111; let Inst{15-12} = Rd; let Inst{11-0} = label{11-0}; } let hasSideEffects = 1 in { def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; } //===----------------------------------------------------------------------===// // Control Flow Instructions. // let isReturn = 1, isTerminator = 1, isBarrier = 1 in { // ARMV4T and above def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, "bx", "\tlr", [(ARMretflag)]>, Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { let Inst{27-0} = 0b0001001011111111111100011110; } // ARMV4 only def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, "mov", "\tpc, lr", [(ARMretflag)]>, Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { let Inst{27-0} = 0b0001101000001111000000001110; } // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets // the user-space one). def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 4, IIC_Br, [(ARMintretflag imm:$offset)]>; } // Indirect branches let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { // ARMV4T and above def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", [(brind GPR:$dst)]>, Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { bits<4> dst; let Inst{31-4} = 0b1110000100101111111111110001; let Inst{3-0} = dst; } def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx", "\t$dst", [/* pattern left blank */]>, Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { bits<4> dst; let Inst{27-4} = 0b000100101111111111110001; let Inst{3-0} = dst; } } // SP is marked as a use to prevent stack-pointer assignments that appear // immediately before calls from potentially appearing dead. let isCall = 1, // FIXME: Do we really need a non-predicated version? If so, it should // at least be a pseudo instruction expanding to the predicated version // at MC lowering time. Defs = [LR], Uses = [SP] in { def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), IIC_Br, "bl\t$func", [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM]>, Sched<[WriteBrL]> { let Inst{31-28} = 0b1110; bits<24> func; let Inst{23-0} = func; let DecoderMethod = "DecodeBranchImmInstruction"; } def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), IIC_Br, "bl", "\t$func", [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsARM]>, Sched<[WriteBrL]> { bits<24> func; let Inst{23-0} = func; let DecoderMethod = "DecodeBranchImmInstruction"; } // ARMv5T and above def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, IIC_Br, "blx\t$func", [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { bits<4> func; let Inst{31-4} = 0b1110000100101111111111110011; let Inst{3-0} = func; } def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, IIC_Br, "blx", "\t$func", [(ARMcall_pred GPR:$func)]>, Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { bits<4> func; let Inst{27-4} = 0b000100101111111111110011; let Inst{3-0} = func; } // ARMv4T // Note: Restrict $func to the tGPR regclass to prevent it being in LR. def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; // ARMv4 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; // mov lr, pc; b if callee is marked noreturn to avoid confusing the // return stack predictor. def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, Requires<[IsARM]>, Sched<[WriteBr]>; } let isBranch = 1, isTerminator = 1 in { // FIXME: should be able to write a pattern for ARMBrcond, but can't use // a two-value operand where a dag node expects two operands. :( def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), IIC_Br, "b", "\t$target", [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, Sched<[WriteBr]> { bits<24> target; let Inst{23-0} = target; let DecoderMethod = "DecodeBranchImmInstruction"; } let isBarrier = 1 in { // B is "predicable" since it's just a Bcc with an 'always' condition. let isPredicable = 1 in // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly // should be sufficient. // FIXME: Is B really a Barrier? That doesn't seem right. def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, [(br bb:$target)], (Bcc arm_br_target:$target, (ops 14, zero_reg))>, Sched<[WriteBr]>; let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { def BR_JTr : ARMPseudoInst<(outs), (ins GPR:$target, i32imm:$jt), 0, IIC_Br, [(ARMbrjt GPR:$target, tjumptable:$jt)]>, Sched<[WriteBr]>; def BR_JTm_i12 : ARMPseudoInst<(outs), (ins addrmode_imm12:$target, i32imm:$jt), 0, IIC_Br, [(ARMbrjt (i32 (load addrmode_imm12:$target)), tjumptable:$jt)]>, Sched<[WriteBrTbl]>; def BR_JTm_rs : ARMPseudoInst<(outs), (ins ldst_so_reg:$target, i32imm:$jt), 0, IIC_Br, [(ARMbrjt (i32 (load ldst_so_reg:$target)), tjumptable:$jt)]>, Sched<[WriteBrTbl]>; def BR_JTadd : ARMPseudoInst<(outs), (ins GPR:$target, GPR:$idx, i32imm:$jt), 0, IIC_Br, [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, Sched<[WriteBrTbl]>; } // isNotDuplicable = 1, isIndirectBranch = 1 } // isBarrier = 1 } // BLX (immediate) def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, "blx\t$target", []>, Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { let Inst{31-25} = 0b1111101; bits<25> target; let Inst{23-0} = target{24-1}; let Inst{24} = target{0}; let isCall = 1; } // Branch and Exchange Jazelle def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", [/* pattern left blank */]>, Sched<[WriteBr]> { bits<4> func; let Inst{23-20} = 0b0010; let Inst{19-8} = 0xfff; let Inst{7-4} = 0b0010; let Inst{3-0} = func; let isBranch = 1; } // Tail calls. let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, Sched<[WriteBr]>; def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, Sched<[WriteBr]>; def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 4, IIC_Br, [], (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, Requires<[IsARM]>, Sched<[WriteBr]>; def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 4, IIC_Br, [], (BX GPR:$dst)>, Sched<[WriteBr]>, Requires<[IsARM, HasV4T]>; } // Secure Monitor Call is a system instruction. def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []>, Requires<[IsARM, HasTrustZone]> { bits<4> opt; let Inst{23-4} = 0b01100000000000000111; let Inst{3-0} = opt; } def : MnemonicAlias<"smi", "smc">; // Supervisor Call (Software Interrupt) let isCall = 1, Uses = [SP] in { def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, Sched<[WriteBr]> { bits<24> svc; let Inst{23-0} = svc; } } // Store Return State class SRSI : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, NoItinerary, asm, "", []> { bits<5> mode; let Inst{31-28} = 0b1111; let Inst{27-25} = 0b100; let Inst{22} = 1; let Inst{21} = wb; let Inst{20} = 0; let Inst{19-16} = 0b1101; // SP let Inst{15-5} = 0b00000101000; let Inst{4-0} = mode; } def SRSDA : SRSI<0, "srsda\tsp, $mode"> { let Inst{24-23} = 0; } def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { let Inst{24-23} = 0; } def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { let Inst{24-23} = 0b10; } def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { let Inst{24-23} = 0b10; } def SRSIA : SRSI<0, "srsia\tsp, $mode"> { let Inst{24-23} = 0b01; } def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { let Inst{24-23} = 0b01; } def SRSIB : SRSI<0, "srsib\tsp, $mode"> { let Inst{24-23} = 0b11; } def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { let Inst{24-23} = 0b11; } def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; // Return From Exception class RFEI : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, NoItinerary, asm, "", []> { bits<4> Rn; let Inst{31-28} = 0b1111; let Inst{27-25} = 0b100; let Inst{22} = 0; let Inst{21} = wb; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-0} = 0xa00; } def RFEDA : RFEI<0, "rfeda\t$Rn"> { let Inst{24-23} = 0; } def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { let Inst{24-23} = 0; } def RFEDB : RFEI<0, "rfedb\t$Rn"> { let Inst{24-23} = 0b10; } def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { let Inst{24-23} = 0b10; } def RFEIA : RFEI<0, "rfeia\t$Rn"> { let Inst{24-23} = 0b01; } def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { let Inst{24-23} = 0b01; } def RFEIB : RFEI<0, "rfeib\t$Rn"> { let Inst{24-23} = 0b11; } def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { let Inst{24-23} = 0b11; } // Hypervisor Call is a system instruction let isCall = 1 in { def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, "hvc", "\t$imm", []>, Requires<[IsARM, HasVirtualization]> { bits<16> imm; // Even though HVC isn't predicable, it's encoding includes a condition field. // The instruction is undefined if the condition field is 0xf otherwise it is // unpredictable if it isn't condition AL (0xe). let Inst{31-28} = 0b1110; let Unpredictable{31-28} = 0b1111; let Inst{27-24} = 0b0001; let Inst{23-20} = 0b0100; let Inst{19-8} = imm{15-4}; let Inst{7-4} = 0b0111; let Inst{3-0} = imm{3-0}; } } // Return from exception in Hypervisor mode. let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, Requires<[IsARM, HasVirtualization]> { let Inst{23-0} = 0b011000000000000001101110; } //===----------------------------------------------------------------------===// // Load / Store Instructions. // // Load defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, zextloadi8>; defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, truncstorei8>; // Special LDR for loads from non-pc-relative constpools. let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, isReMaterializable = 1, isCodeGenOnly = 1 in def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> { bits<4> Rt; bits<17> addr; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = 0b1111; let Inst{15-12} = Rt; let Inst{11-0} = addr{11-0}; // imm12 } // Loads with zero extension def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; // Loads with sign extension def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { // Load doubleword def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, Requires<[IsARM, HasV5TE]>; } def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "lda", "\t$Rt, $addr", []>; def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldab", "\t$Rt, $addr", []>; def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldah", "\t$Rt, $addr", []>; // Indexed loads multiclass AI2_ldridx { def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { bits<17> addr; let Inst{25} = 0; let Inst{23} = addr{12}; let Inst{19-16} = addr{16-13}; let Inst{11-0} = addr{11-0}; let DecoderMethod = "DecodeLDRPreImm"; } def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { bits<17> addr; let Inst{25} = 1; let Inst{23} = addr{12}; let Inst{19-16} = addr{16-13}; let Inst{11-0} = addr{11-0}; let Inst{4} = 0; let DecoderMethod = "DecodeLDRPreReg"; } def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, LdFrm, iir, opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let Inst{4} = 0; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_imm:$offset), IndexModePost, LdFrm, iii, opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } } let mayLoad = 1, hasSideEffects = 0 in { // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or // IIC_iLoad_siu depending on whether it the offset register is shifted. defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; } multiclass AI3_ldridx op, string opc, InstrItinClass itin> { def _PRE : AI3ldstidx { bits<14> addr; let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr{12-9}; // Rn let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } def _POST : AI3ldstidx { bits<10> offset; bits<4> addr; let Inst{23} = offset{8}; // U bit let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr; let Inst{11-8} = offset{7-4}; // imm7_4/zero let Inst{3-0} = offset{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } } let mayLoad = 1, hasSideEffects = 0 in { defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; let hasExtraDefRegAllocReq = 1 in { def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), (ins addrmode3_pre:$addr), IndexModePre, LdMiscFrm, IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $Rn_wb", []> { bits<14> addr; let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr{12-9}; // Rn let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), (ins addr_offset_none:$addr, am3offset:$offset), IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr, $offset", "$addr.base = $Rn_wb", []> { bits<10> offset; bits<4> addr; let Inst{23} = offset{8}; // U bit let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr; let Inst{11-8} = offset{7-4}; // imm7_4/zero let Inst{3-0} = offset{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } } // hasExtraDefRegAllocReq = 1 } // mayLoad = 1, hasSideEffects = 0 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. let mayLoad = 1, hasSideEffects = 0 in { def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, LdFrm, IIC_iLoad_ru, "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-5} = offset{11-5}; let Inst{4} = 0; let Inst{3-0} = offset{3-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_imm:$offset), IndexModePost, LdFrm, IIC_iLoad_ru, "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, LdFrm, IIC_iLoad_bh_ru, "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-5} = offset{11-5}; let Inst{4} = 0; let Inst{3-0} = offset{3-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am2offset_imm:$offset), IndexModePost, LdFrm, IIC_iLoad_bh_ru, "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } multiclass AI3ldrT op, string opc> { def i : AI3ldstidxT { bits<9> offset; let Inst{23} = offset{8}; let Inst{22} = 1; let Inst{11-8} = offset{7-4}; let Inst{3-0} = offset{3-0}; } def r : AI3ldstidxT { bits<5> Rm; let Inst{23} = Rm{4}; let Inst{22} = 0; let Inst{11-8} = 0; let Unpredictable{11-8} = 0b1111; let Inst{3-0} = Rm{3-0}; let DecoderMethod = "DecodeLDR"; } } defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; defm LDRHT : AI3ldrT<0b1011, "ldrht">; defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; } def LDRT_POST : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), (outs GPR:$Rt)>; def LDRBT_POST : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), (outs GPR:$Rt)>; // Pseudo instruction ldr Rt, =immediate def LDRConstPool : ARMAsmPseudo<"ldr${q} $Rt, $immediate", (ins const_pool_asm_imm:$immediate, pred:$q), (outs GPR:$Rt)>; // Store // Stores with truncate def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, IIC_iStore_bh_r, "strh", "\t$Rt, $addr", [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; // Store doubleword let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, Requires<[IsARM, HasV5TE]> { let Inst{21} = 0; } } // Indexed stores multiclass AI2_stridx { def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, StFrm, iii, opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { bits<17> addr; let Inst{25} = 0; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = addr{16-13}; // Rn let Inst{11-0} = addr{11-0}; // imm12 let DecoderMethod = "DecodeSTRPreImm"; } def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, ldst_so_reg:$addr), IndexModePre, StFrm, iir, opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { bits<17> addr; let Inst{25} = 1; let Inst{23} = addr{12}; // U (add = ('U' == 1)) let Inst{19-16} = addr{16-13}; // Rn let Inst{11-0} = addr{11-0}; let Inst{4} = 0; // Inst{4} = 0 let DecoderMethod = "DecodeSTRPreReg"; } def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, StFrm, iir, opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let Inst{4} = 0; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), IndexModePost, StFrm, iii, opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } } let mayStore = 1, hasSideEffects = 0 in { // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or // IIC_iStore_siu depending on whether it the offset register is shifted. defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; } def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset)>; def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)>; def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset)>; def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)>; // Pseudo-instructions for pattern matching the pre-indexed stores. We can't // put the patterns on the instruction definitions directly as ISel wants // the address base and offset to be separate operands, not a single // complex operand like we represent the instructions themselves. The // pseudos map between the two. let usesCustomInserter = 1, Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 4, IIC_iStore_ru, [(set GPR:$Rn_wb, (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 4, IIC_iStore_ru, [(set GPR:$Rn_wb, (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 4, IIC_iStore_ru, [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 4, IIC_iStore_ru, [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 4, IIC_iStore_ru, [(set GPR:$Rn_wb, (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; } def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, StMiscFrm, IIC_iStore_bh_ru, "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { bits<14> addr; let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr{12-9}; // Rn let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), IndexModePost, StMiscFrm, IIC_iStore_bh_ru, "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, addr_offset_none:$addr, am3offset:$offset))]> { bits<10> offset; bits<4> addr; let Inst{23} = offset{8}; // U bit let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr; let Inst{11-8} = offset{7-4}; // imm7_4/zero let Inst{3-0} = offset{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), IndexModePre, StMiscFrm, IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", "$addr.base = $Rn_wb", []> { bits<14> addr; let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr{12-9}; // Rn let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{3-0} = addr{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, am3offset:$offset), IndexModePost, StMiscFrm, IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr, $offset", "$addr.base = $Rn_wb", []> { bits<10> offset; bits<4> addr; let Inst{23} = offset{8}; // U bit let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm let Inst{19-16} = addr; let Inst{11-8} = offset{7-4}; // imm7_4/zero let Inst{3-0} = offset{3-0}; // imm3_0/Rm let DecoderMethod = "DecodeAddrMode3Instruction"; } } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 // STRT, STRBT, and STRHT def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, StFrm, IIC_iStore_bh_ru, "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-5} = offset{11-5}; let Inst{4} = 0; let Inst{3-0} = offset{3-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), IndexModePost, StFrm, IIC_iStore_bh_ru, "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def STRBT_POST : ARMAsmPseudo<"strbt${q} $Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; let mayStore = 1, hasSideEffects = 0 in { def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), IndexModePost, StFrm, IIC_iStore_ru, "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 1; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-5} = offset{11-5}; let Inst{4} = 0; let Inst{3-0} = offset{3-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), IndexModePost, StFrm, IIC_iStore_ru, "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { // {12} isAdd // {11-0} imm12/Rm bits<14> offset; bits<4> addr; let Inst{25} = 0; let Inst{23} = offset{12}; let Inst{21} = 1; // overwrite let Inst{19-16} = addr; let Inst{11-0} = offset{11-0}; let DecoderMethod = "DecodeAddrMode2IdxInstruction"; } } def STRT_POST : ARMAsmPseudo<"strt${q} $Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; multiclass AI3strT op, string opc> { def i : AI3ldstidxT { bits<9> offset; let Inst{23} = offset{8}; let Inst{22} = 1; let Inst{11-8} = offset{7-4}; let Inst{3-0} = offset{3-0}; } def r : AI3ldstidxT { bits<5> Rm; let Inst{23} = Rm{4}; let Inst{22} = 0; let Inst{11-8} = 0; let Inst{3-0} = Rm{3-0}; } } defm STRHT : AI3strT<0b1011, "strht">; def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "stl", "\t$Rt, $addr", []>; def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "stlb", "\t$Rt, $addr", []>; def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "stlh", "\t$Rt, $addr", []>; //===----------------------------------------------------------------------===// // Load / store multiple Instructions. // multiclass arm_ldst_mult { // IA is the default, so no need for an explicit suffix on the // mnemonic here. Without it is the canonical spelling. def IA : AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeNone, f, itin, !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { let Inst{24-23} = 0b01; // Increment After let Inst{22} = P_bit; let Inst{21} = 0; // No writeback let Inst{20} = L_bit; } def IA_UPD : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeUpd, f, itin_upd, !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { let Inst{24-23} = 0b01; // Increment After let Inst{22} = P_bit; let Inst{21} = 1; // Writeback let Inst{20} = L_bit; let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; } def DA : AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeNone, f, itin, !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { let Inst{24-23} = 0b00; // Decrement After let Inst{22} = P_bit; let Inst{21} = 0; // No writeback let Inst{20} = L_bit; } def DA_UPD : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeUpd, f, itin_upd, !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { let Inst{24-23} = 0b00; // Decrement After let Inst{22} = P_bit; let Inst{21} = 1; // Writeback let Inst{20} = L_bit; let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; } def DB : AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeNone, f, itin, !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { let Inst{24-23} = 0b10; // Decrement Before let Inst{22} = P_bit; let Inst{21} = 0; // No writeback let Inst{20} = L_bit; } def DB_UPD : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeUpd, f, itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { let Inst{24-23} = 0b10; // Decrement Before let Inst{22} = P_bit; let Inst{21} = 1; // Writeback let Inst{20} = L_bit; let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; } def IB : AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeNone, f, itin, !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { let Inst{24-23} = 0b11; // Increment Before let Inst{22} = P_bit; let Inst{21} = 0; // No writeback let Inst{20} = L_bit; } def IB_UPD : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), IndexModeUpd, f, itin_upd, !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { let Inst{24-23} = 0b11; // Increment Before let Inst{22} = P_bit; let Inst{21} = 1; // Writeback let Inst{20} = L_bit; let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; } } let hasSideEffects = 0 in { let mayLoad = 1, hasExtraDefRegAllocReq = 1 in defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; let mayStore = 1, hasExtraSrcRegAllocReq = 1 in defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>, ComplexDeprecationPredicate<"ARMStore">; } // hasSideEffects // FIXME: remove when we have a way to marking a MI with these properties. // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 4, IIC_iLoad_mBr, [], (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, RegConstraint<"$Rn = $wb">; let mayLoad = 1, hasExtraDefRegAllocReq = 1 in defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>; let mayStore = 1, hasExtraSrcRegAllocReq = 1 in defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>; //===----------------------------------------------------------------------===// // Move Instructions. // let hasSideEffects = 0, isMoveReg = 1 in def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<4> Rm; let Inst{19-16} = 0b0000; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let Inst{3-0} = Rm; let Inst{15-12} = Rd; } // A version for the smaller set of tail call registers. let hasSideEffects = 0 in def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<4> Rm; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let Inst{3-0} = Rm; let Inst{15-12} = Rd; } def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), DPSoRegRegFrm, IIC_iMOVsr, "mov", "\t$Rd, $src", [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<12> src; let Inst{15-12} = Rd; let Inst{19-16} = 0b0000; let Inst{11-8} = src{11-8}; let Inst{7} = 0; let Inst{6-5} = src{6-5}; let Inst{4} = 1; let Inst{3-0} = src{3-0}; let Inst{25} = 0; } def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), DPSoRegImmFrm, IIC_iMOVsr, "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<12> src; let Inst{15-12} = Rd; let Inst{19-16} = 0b0000; let Inst{11-5} = src{11-5}; let Inst{4} = 0; let Inst{3-0} = src{3-0}; let Inst{25} = 0; } let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<12> imm; let Inst{25} = 1; let Inst{15-12} = Rd; let Inst{19-16} = 0b0000; let Inst{11-0} = imm; } let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), DPFrm, IIC_iMOVi, "movw", "\t$Rd, $imm", [(set GPR:$Rd, imm0_65535:$imm)]>, Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<16> imm; let Inst{15-12} = Rd; let Inst{11-0} = imm{11-0}; let Inst{19-16} = imm{15-12}; let Inst{20} = 0; let Inst{25} = 1; let DecoderMethod = "DecodeArmMOVTWInstruction"; } def : InstAlias<"mov${p} $Rd, $imm", (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, Requires<[IsARM, HasV6T2]>; def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, Sched<[WriteALU]>; let Constraints = "$src = $Rd" in { def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), (ins GPR:$src, imm0_65535_expr:$imm), DPFrm, IIC_iMOVi, "movt", "\t$Rd, $imm", [(set GPRnopc:$Rd, (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>, UnaryDP, Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { bits<4> Rd; bits<16> imm; let Inst{15-12} = Rd; let Inst{11-0} = imm{11-0}; let Inst{19-16} = imm{15-12}; let Inst{20} = 0; let Inst{25} = 1; let DecoderMethod = "DecodeArmMOVTWInstruction"; } def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, Sched<[WriteALU]>; } // Constraints def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, Requires<[IsARM, HasV6T2]>; let Uses = [CPSR] in def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, Requires<[IsARM]>, Sched<[WriteALU]>; // These aren't really mov instructions, but we have to define them this way // due to flag operands. let Defs = [CPSR] in { def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, Sched<[WriteALU]>, Requires<[IsARM]>; def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, Sched<[WriteALU]>, Requires<[IsARM]>; } //===----------------------------------------------------------------------===// // Extend Instructions. // // Sign extenders def SXTB : AI_ext_rrot<0b01101010, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; def SXTH : AI_ext_rrot<0b01101011, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; def SXTAB : AI_exta_rrot<0b01101010, "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; def SXTAH : AI_exta_rrot<0b01101011, "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), i16)), (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), (SXTB16 GPR:$Src, 0)>; def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; // Zero extenders let AddedComplexity = 16 in { def UXTB : AI_ext_rrot<0b01101110, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; def UXTH : AI_ext_rrot<0b01101111, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; def UXTB16 : AI_ext_rrot<0b01101100, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; // FIXME: This pattern incorrectly assumes the shl operator is a rotate. // The transformation should probably be done as a combiner action // instead so we can include a check for masking back in the upper // eight bits of the source into the lower eight bits of the result. //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), // (UXTB16r_rot GPR:$Src, 3)>; def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), (UXTB16 GPR:$Src, 1)>; def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), (UXTB16 GPR:$Src, 0)>; def UXTAB : AI_exta_rrot<0b01101110, "uxtab", BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; def UXTAH : AI_exta_rrot<0b01101111, "uxtah", BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; } // This isn't safe in general, the add is two 16-bit units, not a 32-bit add. def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; def SBFX : I<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; bits<4> Rn; bits<5> lsb; bits<5> width; let Inst{27-21} = 0b0111101; let Inst{6-4} = 0b101; let Inst{20-16} = width; let Inst{15-12} = Rd; let Inst{11-7} = lsb; let Inst{3-0} = Rn; } def UBFX : I<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; bits<4> Rn; bits<5> lsb; bits<5> width; let Inst{27-21} = 0b0111111; let Inst{6-4} = 0b101; let Inst{20-16} = width; let Inst{15-12} = Rd; let Inst{11-7} = lsb; let Inst{3-0} = Rn; } //===----------------------------------------------------------------------===// // Arithmetic Instructions. // let isAdd = 1 in defm ADD : AsI1_bin_irs<0b0100, "add", IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; defm SUB : AsI1_bin_irs<0b0010, "sub", IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; // ADD and SUB with 's' bit set. // // Currently, ADDS/SUBS are pseudo opcodes that exist only in the // selection DAG. They are "lowered" to real ADD/SUB opcodes by // AdjustInstrPostInstrSelection where we determine whether or not to // set the "s" bit based on CPSR liveness. // // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen // support for an optional CPSR definition that corresponds to the DAG // node's second value. We can then eliminate the implicit def of CPSR. let isAdd = 1 in defm ADDS : AsI1_bin_s_irs; defm SUBS : AsI1_bin_s_irs; let isAdd = 1 in defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; defm RSB : AsI1_rbin_irs<0b0011, "rsb", IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; // FIXME: Eliminate them if we can write def : Pat patterns which defines // CPSR and the implicit def of CPSR is not needed. defm RSBS : AsI1_rbin_s_is; defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. // The assume-no-carry-in form uses the negation of the input since add/sub // assume opposite meanings of the carry flag (i.e., carry == !borrow). // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory // details. def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), (SUBri GPR:$src, mod_imm_neg:$imm)>; def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), (SUBSri GPR:$src, mod_imm_neg:$imm)>; def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, Requires<[IsARM, HasV6T2]>; def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, Requires<[IsARM, HasV6T2]>; // The with-carry-in form matches bitwise not instead of the negation. // Effectively, the inverse interpretation of the carry flag already accounts // for part of the negation. def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), (SBCri GPR:$src, mod_imm_not:$imm)>; def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, Requires<[IsARM, HasV6T2]>; // Note: These are implemented in C++ code, because they have to generate // ADD/SUBrs instructions, which use a complex pattern that a xform function // cannot produce. // (mul X, 2^n+1) -> (add (X << n), X) // (mul X, 2^n-1) -> (rsb X, (X << n)) // ARM Arithmetic Instruction // GPR:$dst = GPR:$a op GPR:$b class AAI op27_20, bits<8> op11_4, string opc, list pattern = [], dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), string asm = "\t$Rd, $Rn, $Rm"> : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, Sched<[WriteALU, ReadALU, ReadALU]> { bits<4> Rn; bits<4> Rd; bits<4> Rm; let Inst{27-20} = op27_20; let Inst{11-4} = op11_4; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{3-0} = Rm; let Unpredictable{11-8} = 0b1111; } // Wrappers around the AAI class class AAIRevOpr op27_20, bits<8> op11_4, string opc, list pattern = []> : AAI; class AAIIntrinsic op27_20, bits<8> op11_4, string opc, Intrinsic intrinsic> : AAI; // Saturating add/subtract let hasSideEffects = 1 in { def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rm), GPRnopc:$Rn))]>; def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; let DecoderMethod = "DecodeQADDInstruction" in def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; } def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; // Signed/Unsigned add/subtract def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; // Signed/Unsigned halving add/subtract def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; // Unsigned Sum of Absolute Differences [and Accumulate]. def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), MulFrm /* for convenience */, NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{27-20} = 0b01111000; let Inst{15-12} = 0b1111; let Inst{7-4} = 0b0001; let Inst{19-16} = Rd; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), MulFrm /* for convenience */, NoItinerary, "usada8", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ bits<4> Rd; bits<4> Rn; bits<4> Rm; bits<4> Ra; let Inst{27-20} = 0b01111000; let Inst{7-4} = 0b0001; let Inst{19-16} = Rd; let Inst{15-12} = Ra; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } // Signed/Unsigned saturate def SSAT : AI<(outs GPRnopc:$Rd), (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, Requires<[IsARM,HasV6]>{ bits<4> Rd; bits<5> sat_imm; bits<4> Rn; bits<8> sh; let Inst{27-21} = 0b0110101; let Inst{5-4} = 0b01; let Inst{20-16} = sat_imm; let Inst{15-12} = Rd; let Inst{11-7} = sh{4-0}; let Inst{6} = sh{5}; let Inst{3-0} = Rn; } def SSAT16 : AI<(outs GPRnopc:$Rd), (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, Requires<[IsARM,HasV6]>{ bits<4> Rd; bits<4> sat_imm; bits<4> Rn; let Inst{27-20} = 0b01101010; let Inst{11-4} = 0b11110011; let Inst{15-12} = Rd; let Inst{19-16} = sat_imm; let Inst{3-0} = Rn; } def USAT : AI<(outs GPRnopc:$Rd), (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, Requires<[IsARM,HasV6]> { bits<4> Rd; bits<5> sat_imm; bits<4> Rn; bits<8> sh; let Inst{27-21} = 0b0110111; let Inst{5-4} = 0b01; let Inst{15-12} = Rd; let Inst{11-7} = sh{4-0}; let Inst{6} = sh{5}; let Inst{20-16} = sat_imm; let Inst{3-0} = Rn; } def USAT16 : AI<(outs GPRnopc:$Rd), (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, Requires<[IsARM,HasV6]>{ bits<4> Rd; bits<4> sat_imm; bits<4> Rn; let Inst{27-20} = 0b01101110; let Inst{11-4} = 0b11110011; let Inst{15-12} = Rd; let Inst{19-16} = sat_imm; let Inst{3-0} = Rn; } def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), (USAT imm0_31:$pos, GPRnopc:$a, 0)>; def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), (SSAT16 imm1_16:$pos, GPRnopc:$a)>; def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), (USAT16 imm0_15:$pos, GPRnopc:$a)>; //===----------------------------------------------------------------------===// // Bitwise Instructions. // defm AND : AsI1_bin_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; defm ORR : AsI1_bin_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; defm EOR : AsI1_bin_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; defm BIC : AsI1_bin_irs<0b1110, "bic", IIC_iBITi, IIC_iBITr, IIC_iBITsr, BinOpFrag<(and node:$LHS, (not node:$RHS))>>; // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just // like in the actual instruction encoding. The complexity of mapping the mask // to the lsb/msb pair should be handled by ISel, not encapsulated in the // instruction description. def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "bfc", "\t$Rd, $imm", "$src = $Rd", [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; bits<10> imm; let Inst{27-21} = 0b0111110; let Inst{6-0} = 0b0011111; let Inst{15-12} = Rd; let Inst{11-7} = imm{4-0}; // lsb let Inst{20-16} = imm{9-5}; // msb } // A8.6.18 BFI - Bitfield insert (Encoding A1) def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm))]>, Requires<[IsARM, HasV6T2]> { bits<4> Rd; bits<4> Rn; bits<10> imm; let Inst{27-21} = 0b0111110; let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 let Inst{15-12} = Rd; let Inst{11-7} = imm{4-0}; // lsb let Inst{20-16} = imm{9-5}; // width let Inst{3-0} = Rn; } def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, "mvn", "\t$Rd, $Rm", [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<4> Rm; let Inst{25} = 0; let Inst{19-16} = 0b0000; let Inst{11-4} = 0b00000000; let Inst{15-12} = Rd; let Inst{3-0} = Rm; let Unpredictable{19-16} = 0b1111; } def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = 0b0000; let Inst{15-12} = Rd; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; let Unpredictable{19-16} = 0b1111; } def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<12> shift; let Inst{25} = 0; let Inst{19-16} = 0b0000; let Inst{15-12} = Rd; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; let Unpredictable{19-16} = 0b1111; } let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMVNi, "mvn", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { bits<4> Rd; bits<12> imm; let Inst{25} = 1; let Inst{19-16} = 0b0000; let Inst{15-12} = Rd; let Inst{11-0} = imm; } let AddedComplexity = 1 in def : ARMPat<(and GPR:$src, mod_imm_not:$imm), (BICri GPR:$src, mod_imm_not:$imm)>; //===----------------------------------------------------------------------===// // Multiply Instructions. // class AsMul1I32 opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AsMul1I { bits<4> Rd; bits<4> Rm; bits<4> Rn; let Inst{19-16} = Rd; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } class AsMul1I64 opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AsMul1I { bits<4> RdLo; bits<4> RdHi; bits<4> Rm; bits<4> Rn; let Inst{19-16} = RdHi; let Inst{15-12} = RdLo; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } class AsMla1I64 opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : AsMul1I { bits<4> RdLo; bits<4> RdHi; bits<4> Rm; bits<4> Rn; let Inst{19-16} = RdHi; let Inst{15-12} = RdLo; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } // FIXME: The v5 pseudos are only necessary for the additional Constraint // property. Remove them when it's possible to add those properties // on an individual MachineInstr, not just an instruction description. let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> { let Inst{15-12} = 0b0000; let Unpredictable{15-12} = 0b1111; } let Constraints = "@earlyclobber $Rd" in def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 4, IIC_iMUL32, [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6, UseMulOps]>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; } def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, Requires<[IsARM, HasV6, UseMulOps]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { bits<4> Ra; let Inst{15-12} = Ra; } let Constraints = "@earlyclobber $Rd" in def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s), 4, IIC_iMAC32, [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, Requires<[IsARM, HasV6T2, UseMulOps]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { bits<4> Rd; bits<4> Rm; bits<4> Rn; bits<4> Ra; let Inst{19-16} = Rd; let Inst{15-12} = Ra; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } // Extra precision multiplies with low / high results let hasSideEffects = 0 in { let isCommutable = 1 in { def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, "smull", "\t$RdLo, $RdHi, $Rn, $Rm", [(set GPR:$RdLo, GPR:$RdHi, (smullohi GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, "umull", "\t$RdLo, $RdHi, $Rn, $Rm", [(set GPR:$RdLo, GPR:$RdHi, (umullohi GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4, IIC_iMUL64, [(set GPR:$RdLo, GPR:$RdHi, (smullohi GPR:$Rn, GPR:$Rm))], (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>, Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4, IIC_iMUL64, [(set GPR:$RdLo, GPR:$RdHi, (umullohi GPR:$Rn, GPR:$Rm))], (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>, Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; } } // Multiply + accumulate def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { bits<4> RdLo; bits<4> RdHi; bits<4> Rm; bits<4> Rn; let Inst{19-16} = RdHi; let Inst{15-12} = RdLo; let Inst{11-8} = Rm; let Inst{3-0} = Rn; } let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4, IIC_iMAC64, [], (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4, IIC_iMAC64, [], (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s)>, Requires<[IsARM, NoV6]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; } } // hasSideEffects // Most significant word multiply def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> { let Inst{15-12} = 0b1111; } def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMUL32, ReadMUL, ReadMUL]> { let Inst{15-12} = 0b1111; } def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, Requires<[IsARM, HasV6, UseMulOps]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, Requires<[IsARM, HasV6, UseMulOps]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, Requires<[IsARM, HasV6]>, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; multiclass AI_smul { def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), (sext_inreg GPR:$Rm, i16)))]>, Requires<[IsARM, HasV5TE]>, Sched<[WriteMUL16, ReadMUL, ReadMUL]>; def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16), (sra GPR:$Rm, (i32 16))))]>, Requires<[IsARM, HasV5TE]>, Sched<[WriteMUL16, ReadMUL, ReadMUL]>; def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), (sext_inreg GPR:$Rm, i16)))]>, Requires<[IsARM, HasV5TE]>, Sched<[WriteMUL16, ReadMUL, ReadMUL]>; def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)), (sra GPR:$Rm, (i32 16))))]>, Requires<[IsARM, HasV5TE]>, Sched<[WriteMUL16, ReadMUL, ReadMUL]>; def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV5TE]>, Sched<[WriteMUL16, ReadMUL, ReadMUL]>; def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasV5TE]>, Sched<[WriteMUL16, ReadMUL, ReadMUL]>; } multiclass AI_smla { let DecoderMethod = "DecodeSMLAInstruction" in { def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), (sext_inreg GPRnopc:$Rm, i16))))]>, Requires<[IsARM, HasV5TE, UseMulOps]>, Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16), (sra GPRnopc:$Rm, (i32 16)))))]>, Requires<[IsARM, HasV5TE, UseMulOps]>, Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), (sext_inreg GPRnopc:$Rm, i16))))]>, Requires<[IsARM, HasV5TE, UseMulOps]>, Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)), (sra GPRnopc:$Rm, (i32 16)))))]>, Requires<[IsARM, HasV5TE, UseMulOps]>, Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, Requires<[IsARM, HasV5TE, UseMulOps]>, Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", [(set GPRnopc:$Rd, (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, Requires<[IsARM, HasV5TE, UseMulOps]>, Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; } } defm SMUL : AI_smul<"smul">; defm SMLA : AI_smla<"smla">; // Halfword multiply accumulate long: SMLAL. class SMLAL opc1, string asm> : AMulxyI64<0b0001010, opc1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV5TE]>, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; def SMLALBB : SMLAL<0b00, "smlalbb">; def SMLALBT : SMLAL<0b10, "smlalbt">; def SMLALTB : SMLAL<0b01, "smlaltb">; def SMLALTT : SMLAL<0b11, "smlaltt">; def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), (SMLALBB $Rn, $Rm, $RLo, $RHi)>; def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), (SMLALBT $Rn, $Rm, $RLo, $RHi)>; def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), (SMLALTB $Rn, $Rm, $RLo, $RHi)>; def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), (SMLALTT $Rn, $Rm, $RLo, $RHi)>; // Helper class for AI_smld. class AMulDualIbase : AI, Requires<[IsARM, HasV6]> { bits<4> Rn; bits<4> Rm; let Inst{27-23} = 0b01110; let Inst{22} = long; let Inst{21-20} = 0b00; let Inst{11-8} = Rm; let Inst{7} = 0; let Inst{6} = sub; let Inst{5} = swap; let Inst{4} = 1; let Inst{3-0} = Rn; } class AMulDualI : AMulDualIbase { bits<4> Rd; let Inst{15-12} = 0b1111; let Inst{19-16} = Rd; } class AMulDualIa : AMulDualIbase { bits<4> Ra; bits<4> Rd; let Inst{19-16} = Rd; let Inst{15-12} = Ra; } class AMulDualI64 : AMulDualIbase { bits<4> RdLo; bits<4> RdHi; let Inst{19-16} = RdHi; let Inst{15-12} = RdLo; } multiclass AI_smld { def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), NoItinerary, !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), NoItinerary, !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; } defm SMLA : AI_smld<0, "smla">; defm SMLS : AI_smld<1, "smls">; def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; multiclass AI_sdml { def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; } defm SMUA : AI_sdml<0, "smua">; defm SMUS : AI_sdml<1, "smus">; def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; //===----------------------------------------------------------------------===// // Division Instructions (ARMv7-A with virtualization extension) // def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, "sdiv", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasDivideInARM]>, Sched<[WriteDIV]>; def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, "udiv", "\t$Rd, $Rn, $Rm", [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, Requires<[IsARM, HasDivideInARM]>, Sched<[WriteDIV]>; //===----------------------------------------------------------------------===// // Misc. Arithmetic Instructions. // def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), IIC_iUNAr, "clz", "\t$Rd, $Rm", [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, Sched<[WriteALU]>; def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), IIC_iUNAr, "rbit", "\t$Rd, $Rm", [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]>; def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), IIC_iUNAr, "rev", "\t$Rd, $Rm", [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALU]>; let AddedComplexity = 5 in def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), IIC_iUNAr, "rev16", "\t$Rd, $Rm", [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALU]>; def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), (REV16 (LDRH addrmode3:$addr))>; def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; let AddedComplexity = 5 in def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), IIC_iUNAr, "revsh", "\t$Rd, $Rm", [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALU]>; def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), (and (srl GPR:$Rm, (i32 8)), 0xFF)), (REVSH GPR:$Rm)>; def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 0xFFFF0000)))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALUsi, ReadALU]>; // Alternate cases for PKHBT where identities eliminate some nodes. def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and // will match the pattern below. def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 0xFFFF)))]>, Requires<[IsARM, HasV6]>, Sched<[WriteALUsi, ReadALU]>; // Alternate cases for PKHTB where identities eliminate some nodes. Note that // a shift amount of 0 is *not legal* here, it is PKHBT instead. // We also can not replace a srl (17..31) by an arithmetic shift we would use in // pkhtb src1, src2, asr (17..31). def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), (srl GPRnopc:$src2, imm16:$sh)), (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), (sra GPRnopc:$src2, imm16_31:$sh)), (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; //===----------------------------------------------------------------------===// // CRC Instructions // // Polynomials: // + CRC32{B,H,W} 0x04C11DB7 // + CRC32C{B,H,W} 0x1EDC6F41 // class AI_crc32 sz, string suffix, SDPatternOperator builtin> : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, Requires<[IsARM, HasV8, HasCRC]> { bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{31-28} = 0b1110; let Inst{27-23} = 0b00010; let Inst{22-21} = sz; let Inst{20} = 0; let Inst{19-16} = Rn; let Inst{15-12} = Rd; let Inst{11-10} = 0b00; let Inst{9} = C; let Inst{8} = 0; let Inst{7-4} = 0b0100; let Inst{3-0} = Rm; let Unpredictable{11-8} = 0b1101; } def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; //===----------------------------------------------------------------------===// // ARMv8.1a Privilege Access Never extension // // SETPAN #imm1 def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { bits<1> imm; let Inst{31-28} = 0b1111; let Inst{27-20} = 0b00010001; let Inst{19-16} = 0b0000; let Inst{15-10} = 0b000000; let Inst{9} = imm; let Inst{8} = 0b0; let Inst{7-4} = 0b0000; let Inst{3-0} = 0b0000; let Unpredictable{19-16} = 0b1111; let Unpredictable{15-10} = 0b111111; let Unpredictable{8} = 0b1; let Unpredictable{3-0} = 0b1111; } //===----------------------------------------------------------------------===// // Comparison Instructions... // defm CMP : AI1_cmp_irs<0b1010, "cmp", IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; // ARMcmpZ can re-use the above instruction definitions. def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), (CMPri GPR:$src, mod_imm:$imm)>; def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), (CMPrr GPR:$src, GPR:$rhs)>; def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), (CMPrsi GPR:$src, so_reg_imm:$rhs)>; def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), (CMPrsr GPR:$src, so_reg_reg:$rhs)>; // CMN register-integer let isCompare = 1, Defs = [CPSR] in { def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, "cmn", "\t$Rn, $imm", [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, Sched<[WriteCMP, ReadALU]> { bits<4> Rn; bits<12> imm; let Inst{25} = 1; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-0} = imm; let Unpredictable{15-12} = 0b1111; } // CMN register-register/shift def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, "cmn", "\t$Rn, $Rm", [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { bits<4> Rn; bits<4> Rm; let isCommutable = 1; let Inst{25} = 0; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-4} = 0b00000000; let Inst{3-0} = Rm; let Unpredictable{15-12} = 0b1111; } def CMNzrsi : AI1<0b1011, (outs), (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, "cmn", "\t$Rn, $shift", [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> GPR:$Rn, so_reg_imm:$shift)]>, Sched<[WriteCMPsi, ReadALU]> { bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-5} = shift{11-5}; let Inst{4} = 0; let Inst{3-0} = shift{3-0}; let Unpredictable{15-12} = 0b1111; } def CMNzrsr : AI1<0b1011, (outs), (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, "cmn", "\t$Rn, $shift", [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> GPRnopc:$Rn, so_reg_reg:$shift)]>, Sched<[WriteCMPsr, ReadALU]> { bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{20} = 1; let Inst{19-16} = Rn; let Inst{15-12} = 0b0000; let Inst{11-8} = shift{11-8}; let Inst{7} = 0; let Inst{6-5} = shift{6-5}; let Inst{4} = 1; let Inst{3-0} = shift{3-0}; let Unpredictable{15-12} = 0b1111; } } def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), (CMNri GPR:$src, mod_imm_neg:$imm)>; def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), (CMNri GPR:$src, mod_imm_neg:$imm)>; // Note that TST/TEQ don't set all the same flags that CMP does! defm TST : AI1_cmp_irs<0b1000, "tst", IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, "DecodeTSTInstruction">; defm TEQ : AI1_cmp_irs<0b1001, "teq", IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; // Pseudo i64 compares for some floating point compares. let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, Defs = [CPSR] in { def BCCi64 : PseudoInst<(outs), (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), IIC_Br, [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, Sched<[WriteBr]>; def BCCZi64 : PseudoInst<(outs), (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, Sched<[WriteBr]>; } // usesCustomInserter // Conditional moves let hasSideEffects = 0 in { let isCommutable = 1, isSelect = 1 in def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4, IIC_iCMOVr, [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4, IIC_iCMOVsr, [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4, IIC_iCMOVsr, [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; let isMoveImm = 1 in def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4, IIC_iMOVi, [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]>; let isMoveImm = 1 in def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4, IIC_iCMOVi, [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; // Two instruction predicate mov immediate. let isMoveImm = 1 in def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, i32imm:$src, cmovpred:$p), 8, IIC_iCMOVix2, [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; let isMoveImm = 1 in def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4, IIC_iCMOVi, [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, cmovpred:$p))]>, RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; } // hasSideEffects //===----------------------------------------------------------------------===// // Atomic operations intrinsics // def MemBarrierOptOperand : AsmOperandClass { let Name = "MemBarrierOpt"; let ParserMethod = "parseMemBarrierOptOperand"; } def memb_opt : Operand { let PrintMethod = "printMemBOption"; let ParserMatchClass = MemBarrierOptOperand; let DecoderMethod = "DecodeMemBarrierOption"; } def InstSyncBarrierOptOperand : AsmOperandClass { let Name = "InstSyncBarrierOpt"; let ParserMethod = "parseInstSyncBarrierOptOperand"; } def instsyncb_opt : Operand { let PrintMethod = "printInstSyncBOption"; let ParserMatchClass = InstSyncBarrierOptOperand; let DecoderMethod = "DecodeInstSyncBarrierOption"; } def TraceSyncBarrierOptOperand : AsmOperandClass { let Name = "TraceSyncBarrierOpt"; let ParserMethod = "parseTraceSyncBarrierOptOperand"; } def tsb_opt : Operand { let PrintMethod = "printTraceSyncBOption"; let ParserMatchClass = TraceSyncBarrierOptOperand; } // Memory barriers protect the atomic sequences let hasSideEffects = 1 in { def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, Requires<[IsARM, HasDB]> { bits<4> opt; let Inst{31-4} = 0xf57ff05; let Inst{3-0} = opt; } def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, Requires<[IsARM, HasDB]> { bits<4> opt; let Inst{31-4} = 0xf57ff04; let Inst{3-0} = opt; } // ISB has only full system option def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, Requires<[IsARM, HasDB]> { bits<4> opt; let Inst{31-4} = 0xf57ff06; let Inst{3-0} = opt; } let hasNoSchedulingInfo = 1 in def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { let Inst{31-0} = 0xe320f012; } } let usesCustomInserter = 1, Defs = [CPSR] in { // Pseudo instruction that combines movs + predicated rsbmi // to implement integer ABS def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; } let usesCustomInserter = 1 in { def COPY_STRUCT_BYVAL_I32 : PseudoInst< (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), NoItinerary, [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; } let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... // Copies N registers worth of memory from address %src to address %dst // and returns the incremented addresses. N scratch register will // be attached for the copy to use. def MEMCPY : PseudoInst< (outs GPR:$newdst, GPR:$newsrc), (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), NoItinerary, [(set GPR:$newdst, GPR:$newsrc, (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; } def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def strex_1 : PatFrag<(ops node:$val, node:$ptr), (int_arm_strex node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def strex_2 : PatFrag<(ops node:$val, node:$ptr), (int_arm_strex node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def strex_4 : PatFrag<(ops node:$val, node:$ptr), (int_arm_strex node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; def stlex_1 : PatFrag<(ops node:$val, node:$ptr), (int_arm_stlex node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i8; }]>; def stlex_2 : PatFrag<(ops node:$val, node:$ptr), (int_arm_stlex node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i16; }]>; def stlex_4 : PatFrag<(ops node:$val, node:$ptr), (int_arm_stlex node:$val, node:$ptr), [{ return cast(N)->getMemoryVT() == MVT::i32; }]>; let mayLoad = 1 in { def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldrexb", "\t$Rt, $addr", [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldrexh", "\t$Rt, $addr", [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldrex", "\t$Rt, $addr", [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; let hasExtraDefRegAllocReq = 1 in def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), NoItinerary, "ldrexd", "\t$Rt, $addr", []> { let DecoderMethod = "DecodeDoubleRegLoad"; } def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldaexb", "\t$Rt, $addr", [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldaexh", "\t$Rt, $addr", [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldaex", "\t$Rt, $addr", [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; let hasExtraDefRegAllocReq = 1 in def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), NoItinerary, "ldaexd", "\t$Rt, $addr", []> { let DecoderMethod = "DecodeDoubleRegLoad"; } } let mayStore = 1, Constraints = "@earlyclobber $Rd" in { def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "strexb", "\t$Rd, $Rt, $addr", [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>; def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "strexh", "\t$Rd, $Rt, $addr", [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>; def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "strex", "\t$Rd, $Rt, $addr", [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>; let hasExtraSrcRegAllocReq = 1 in def STREXD : AIstrex<0b01, (outs GPR:$Rd), (ins GPRPairOp:$Rt, addr_offset_none:$addr), NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { let DecoderMethod = "DecodeDoubleRegStore"; } def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", [(set GPR:$Rd, (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", [(set GPR:$Rd, (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), NoItinerary, "stlex", "\t$Rd, $Rt, $addr", [(set GPR:$Rd, (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; let hasExtraSrcRegAllocReq = 1 in def STLEXD : AIstlex<0b01, (outs GPR:$Rd), (ins GPRPairOp:$Rt, addr_offset_none:$addr), NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { let DecoderMethod = "DecodeDoubleRegStore"; } } def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", [(int_arm_clrex)]>, Requires<[IsARM, HasV6K]> { let Inst{31-0} = 0b11110101011111111111000000011111; } def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), (STREXB GPR:$Rt, addr_offset_none:$addr)>; def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), (STREXH GPR:$Rt, addr_offset_none:$addr)>; def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), (STLEXB GPR:$Rt, addr_offset_none:$addr)>; def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), (STLEXH GPR:$Rt, addr_offset_none:$addr)>; class acquiring_load : PatFrag<(ops node:$ptr), (base node:$ptr), [{ AtomicOrdering Ordering = cast(N)->getOrdering(); return isAcquireOrStronger(Ordering); }]>; def atomic_load_acquire_8 : acquiring_load; def atomic_load_acquire_16 : acquiring_load; def atomic_load_acquire_32 : acquiring_load; class releasing_store : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ AtomicOrdering Ordering = cast(N)->getOrdering(); return isReleaseOrStronger(Ordering); }]>; def atomic_store_release_8 : releasing_store; def atomic_store_release_16 : releasing_store; def atomic_store_release_32 : releasing_store; let AddedComplexity = 8 in { def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; } // SWP/SWPB are deprecated in V6/V7 and optional in v7VE. // FIXME Use InstAlias to generate LDREX/STREX pairs instead. let mayLoad = 1, mayStore = 1 in { def SWP : AIswp<0, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, Requires<[IsARM,PreV8]>; def SWPB: AIswp<1, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, Requires<[IsARM,PreV8]>; } //===----------------------------------------------------------------------===// // Coprocessor Instructions. // def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm, imm:$opc2)]>, Requires<[IsARM,PreV8]> { bits<4> opc1; bits<4> CRn; bits<4> CRd; bits<4> cop; bits<3> opc2; bits<4> CRm; let Inst{3-0} = CRm; let Inst{4} = 0; let Inst{7-5} = opc2; let Inst{11-8} = cop; let Inst{15-12} = CRd; let Inst{19-16} = CRn; let Inst{23-20} = opc1; let DecoderNamespace = "CoProc"; } def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm, imm:$opc2)]>, Requires<[IsARM,PreV8]> { let Inst{31-28} = 0b1111; bits<4> opc1; bits<4> CRn; bits<4> CRd; bits<4> cop; bits<3> opc2; bits<4> CRm; let Inst{3-0} = CRm; let Inst{4} = 0; let Inst{7-5} = opc2; let Inst{11-8} = cop; let Inst{15-12} = CRd; let Inst{19-16} = CRn; let Inst{23-20} = opc1; let DecoderNamespace = "CoProc"; } class ACI pattern, IndexMode im = IndexModeNone> : I { let Inst{27-25} = 0b110; } class ACInoP pattern, IndexMode im = IndexModeNone> : InoP { let Inst{31-28} = 0b1111; let Inst{27-25} = 0b110; } let DecoderNamespace = "CoProc" in { multiclass LdStCop pattern> { def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), asm, "\t$cop, $CRd, $addr", pattern> { bits<13> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 1; // P = 1 let Inst{23} = addr{8}; let Inst{22} = Dbit; let Inst{21} = 0; // W = 0 let Inst{20} = load; let Inst{19-16} = addr{12-9}; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = addr{7-0}; let DecoderMethod = "DecodeCopMemInstruction"; } def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { bits<13> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 1; // P = 1 let Inst{23} = addr{8}; let Inst{22} = Dbit; let Inst{21} = 1; // W = 1 let Inst{20} = load; let Inst{19-16} = addr{12-9}; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = addr{7-0}; let DecoderMethod = "DecodeCopMemInstruction"; } def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset), asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { bits<9> offset; bits<4> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 0; // P = 0 let Inst{23} = offset{8}; let Inst{22} = Dbit; let Inst{21} = 1; // W = 1 let Inst{20} = load; let Inst{19-16} = addr; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = offset{7-0}; let DecoderMethod = "DecodeCopMemInstruction"; } def _OPTION : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option), asm, "\t$cop, $CRd, $addr, $option", []> { bits<8> option; bits<4> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 0; // P = 0 let Inst{23} = 1; // U = 1 let Inst{22} = Dbit; let Inst{21} = 0; // W = 0 let Inst{20} = load; let Inst{19-16} = addr; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = option; let DecoderMethod = "DecodeCopMemInstruction"; } } multiclass LdSt2Cop pattern> { def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), asm, "\t$cop, $CRd, $addr", pattern> { bits<13> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 1; // P = 1 let Inst{23} = addr{8}; let Inst{22} = Dbit; let Inst{21} = 0; // W = 0 let Inst{20} = load; let Inst{19-16} = addr{12-9}; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = addr{7-0}; let DecoderMethod = "DecodeCopMemInstruction"; } def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { bits<13> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 1; // P = 1 let Inst{23} = addr{8}; let Inst{22} = Dbit; let Inst{21} = 1; // W = 1 let Inst{20} = load; let Inst{19-16} = addr{12-9}; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = addr{7-0}; let DecoderMethod = "DecodeCopMemInstruction"; } def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, postidx_imm8s4:$offset), asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { bits<9> offset; bits<4> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 0; // P = 0 let Inst{23} = offset{8}; let Inst{22} = Dbit; let Inst{21} = 1; // W = 1 let Inst{20} = load; let Inst{19-16} = addr; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = offset{7-0}; let DecoderMethod = "DecodeCopMemInstruction"; } def _OPTION : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, coproc_option_imm:$option), asm, "\t$cop, $CRd, $addr, $option", []> { bits<8> option; bits<4> addr; bits<4> cop; bits<4> CRd; let Inst{24} = 0; // P = 0 let Inst{23} = 1; // U = 1 let Inst{22} = Dbit; let Inst{21} = 0; // W = 0 let Inst{20} = load; let Inst{19-16} = addr; let Inst{15-12} = CRd; let Inst{11-8} = cop; let Inst{7-0} = option; let DecoderMethod = "DecodeCopMemInstruction"; } } defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; } // DecoderNamespace = "CoProc" //===----------------------------------------------------------------------===// // Move between coprocessor and ARM core register. // class MovRCopro pattern> : ABI<0b1110, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { let Inst{20} = direction; let Inst{4} = 1; bits<4> Rt; bits<4> cop; bits<3> opc1; bits<3> opc2; bits<4> CRm; bits<4> CRn; let Inst{15-12} = Rt; let Inst{11-8} = cop; let Inst{23-21} = opc1; let Inst{7-5} = opc2; let Inst{3-0} = CRm; let Inst{19-16} = CRn; let DecoderNamespace = "CoProc"; } def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)]>, ComplexDeprecationPredicate<"MCR">; def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)>; def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), []>; def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)>; def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; class MovRCopro2 pattern> : ABXI<0b1110, oops, iops, NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { let Inst{31-24} = 0b11111110; let Inst{20} = direction; let Inst{4} = 1; bits<4> Rt; bits<4> cop; bits<3> opc1; bits<3> opc2; bits<4> CRm; bits<4> CRn; let Inst{15-12} = Rt; let Inst{11-8} = cop; let Inst{23-21} = opc1; let Inst{7-5} = opc2; let Inst{3-0} = CRm; let Inst{19-16} = CRn; let DecoderNamespace = "CoProc"; } def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)]>, Requires<[IsARM,PreV8]>; def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0)>; def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), []>, Requires<[IsARM,PreV8]>; def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0)>; def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; class MovRRCopro pattern = []> : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { let Inst{23-21} = 0b010; let Inst{20} = direction; bits<4> Rt; bits<4> Rt2; bits<4> cop; bits<4> opc1; bits<4> CRm; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; let Inst{11-8} = cop; let Inst{7-4} = opc1; let Inst{3-0} = CRm; } def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, imm:$CRm)]>; def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, (outs GPRnopc:$Rt, GPRnopc:$Rt2), (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; class MovRRCopro2 pattern = []> : ABXI<0b1100, oops, iops, NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, Requires<[IsARM,PreV8]> { let Inst{31-28} = 0b1111; let Inst{23-21} = 0b010; let Inst{20} = direction; bits<4> Rt; bits<4> Rt2; bits<4> cop; bits<4> opc1; bits<4> CRm; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; let Inst{11-8} = cop; let Inst{7-4} = opc1; let Inst{3-0} = CRm; let DecoderMethod = "DecoderForMRRC2AndMCRR2"; } def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2, imm:$CRm)]>; def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, (outs GPRnopc:$Rt, GPRnopc:$Rt2), (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; //===----------------------------------------------------------------------===// // Move between special register and ARM core register // // Move to ARM core register from Special Register def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> { bits<4> Rd; let Inst{23-16} = 0b00001111; let Unpredictable{19-17} = 0b111; let Inst{15-12} = Rd; let Inst{11-0} = 0b000000000000; let Unpredictable{11-0} = 0b110100001111; } def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, Requires<[IsARM]>; // The MRSsys instruction is the MRS instruction from the ARM ARM, // section B9.3.9, with the R bit set to 1. def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> { bits<4> Rd; let Inst{23-16} = 0b01001111; let Unpredictable{19-16} = 0b1111; let Inst{15-12} = Rd; let Inst{11-0} = 0b000000000000; let Unpredictable{11-0} = 0b110100001111; } // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a // separate encoding (distinguished by bit 5. def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), NoItinerary, "mrs", "\t$Rd, $banked", []>, Requires<[IsARM, HasVirtualization]> { bits<6> banked; bits<4> Rd; let Inst{23} = 0; let Inst{22} = banked{5}; // R bit let Inst{21-20} = 0b00; let Inst{19-16} = banked{3-0}; let Inst{15-12} = Rd; let Inst{11-9} = 0b001; let Inst{8} = banked{4}; let Inst{7-0} = 0b00000000; } // Move from ARM core register to Special Register // // No need to have both system and application versions of MSR (immediate) or // MSR (register), the encodings are the same and the assembly parser has no way // to distinguish between them. The mask operand contains the special register // (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be // accessed in the special register. let Defs = [CPSR] in def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, "msr", "\t$mask, $Rn", []> { bits<5> mask; bits<4> Rn; let Inst{23} = 0; let Inst{22} = mask{4}; // R bit let Inst{21-20} = 0b10; let Inst{19-16} = mask{3-0}; let Inst{15-12} = 0b1111; let Inst{11-4} = 0b00000000; let Inst{3-0} = Rn; } let Defs = [CPSR] in def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, "msr", "\t$mask, $imm", []> { bits<5> mask; bits<12> imm; let Inst{23} = 0; let Inst{22} = mask{4}; // R bit let Inst{21-20} = 0b10; let Inst{19-16} = mask{3-0}; let Inst{15-12} = 0b1111; let Inst{11-0} = imm; } // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a // separate encoding (distinguished by bit 5. def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), NoItinerary, "msr", "\t$banked, $Rn", []>, Requires<[IsARM, HasVirtualization]> { bits<6> banked; bits<4> Rn; let Inst{23} = 0; let Inst{22} = banked{5}; // R bit let Inst{21-20} = 0b10; let Inst{19-16} = banked{3-0}; let Inst{15-12} = 0b1111; let Inst{11-9} = 0b001; let Inst{8} = banked{4}; let Inst{7-4} = 0b0000; let Inst{3-0} = Rn; } // Dynamic stack allocation yields a _chkstk for Windows targets. These calls // are needed to probe the stack when allocating more than // 4k bytes in one go. Touching the stack at 4K increments is necessary to // ensure that the guard pages used by the OS virtual memory manager are // allocated in correct sequence. // The main point of having separate instruction are extra unmodelled effects // (compared to ordinary calls) like stack pointer change. def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, [SDNPHasChain, SDNPSideEffect]>; let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; let usesCustomInserter = 1, Defs = [CPSR] in def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, [(win__dbzchk tGPR:$divisor)]>; //===----------------------------------------------------------------------===// // TLS Instructions // // __aeabi_read_tp preserves the registers r1-r3. // This is a pseudo inst so that we can get the encoding right, // complete with fixup for the aeabi_read_tp function. // TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern // is defined in "ARMInstrThumb.td". let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in { def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, Requires<[IsARM, IsReadTPSoft]>; } // Reading thread pointer from coprocessor register def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, Requires<[IsARM, IsReadTPHard]>; //===----------------------------------------------------------------------===// // SJLJ Exception handling intrinsics // eh_sjlj_setjmp() is an instruction sequence to store the return // address and save #0 in R0 for the non-longjmp case. // Since by its nature we may be coming from some other function to get // here, and we're using the stack frame for the containing function to // save/restore registers, we can't keep anything live in regs across // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon // when we get here from a longjmp(). We force everything out of registers // except for our own input by listing the relevant registers in Defs. By // doing so, we also cause the prologue/epilogue code to actively preserve // all of the callee-saved resgisters, which is exactly what we want. // A constant value is passed in $val, and we use the location as a scratch. // // These are pseudo-instructions and are lowered to individual MC-insts, so // no encoding information is necessary. let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), NoItinerary, [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, Requires<[IsARM, HasVFP2]>; } let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), NoItinerary, [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, Requires<[IsARM, NoVFP]>; } // FIXME: Non-IOS version(s) let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, Defs = [ R7, LR, SP ] in { def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), NoItinerary, [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, Requires<[IsARM]>; } let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, [(ARMeh_sjlj_setup_dispatch)]>; // eh.sjlj.dispatchsetup pseudo-instruction. // This pseudo is used for both ARM and Thumb. Any differences are handled when // the pseudo is expanded (which happens before any passes that need the // instruction size). let isBarrier = 1 in def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns // // ARMv4 indirect branch using (MOVr PC, dst) let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 4, IIC_Br, [(brind GPR:$dst)], (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 4, IIC_Br, [], (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; // Large immediate handling. // 32-bit immediate using two piece mod_imms or movw + movt. // This is a single pseudo instruction, the benefit is that it can be remat'd // as a single unit instead of having to handle reg inputs. // FIXME: Remove this when we can do generalized remat. let isReMaterializable = 1, isMoveImm = 1 in def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, [(set GPR:$dst, (arm_i32imm:$src))]>, Requires<[IsARM]>; def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, Requires<[IsARM, DontUseMovt]>; // Pseudo instruction that combines movw + movt + add pc (if PIC). // It also makes it possible to rematerialize the instructions. // FIXME: Remove this when we can do generalized remat and when machine licm // can properly the instructions. let isReMaterializable = 1 in { def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), IIC_iMOVix2addpc, [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, Requires<[IsARM, UseMovtInPic]>; def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadiALU, [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, Requires<[IsARM, DontUseMovtInPic]>; let AddedComplexity = 10 in def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), NoItinerary, [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, Requires<[IsARM, DontUseMovtInPic]>; let AddedComplexity = 10 in def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), IIC_iMOVix2ld, [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, Requires<[IsARM, UseMovtInPic]>; } // isReMaterializable // The many different faces of TLS access. def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), (MOVi32imm tglobaltlsaddr :$dst)>, Requires<[IsARM, UseMovt]>; def : Pat<(ARMWrapper tglobaltlsaddr:$src), (LDRLIT_ga_abs tglobaltlsaddr:$src)>, Requires<[IsARM, DontUseMovt]>; def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, DontUseMovtInPic]>; let AddedComplexity = 10 in def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; // ConstantPool, GlobalAddress, and JumpTable def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, Requires<[IsARM, UseMovt]>; def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, Requires<[IsARM, UseMovt]>; def : ARMPat<(ARMWrapperJT tjumptable:$dst), (LEApcrelJT tjumptable:$dst)>; // TODO: add,sub,and, 3-instr forms? // Tail calls. These patterns also apply to Thumb mode. def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; // Direct calls def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; def : ARMPat<(ARMcall_nolink texternalsym:$func), (BMOVPCB_CALL texternalsym:$func)>; // zextload i1 -> zextload i8 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; // extload -> zextload def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; // smul* and smla* def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), (SMULBB GPR:$a, GPR:$b)>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), (SMULBT GPR:$a, GPR:$b)>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), (SMULTB GPR:$a, GPR:$b)>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), (SMLABB GPR:$a, GPR:$b, GPR:$acc)>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), (SMLABT GPR:$a, GPR:$b, GPR:$acc)>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def : ARMV5MOPat<(add GPR:$acc, (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), (SMLATB GPR:$a, GPR:$b, GPR:$acc)>, Sched<[WriteMUL32, ReadMUL, ReadMUL]>; def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), (SMULBB GPR:$a, GPR:$b)>; def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), (SMULBT GPR:$a, GPR:$b)>; def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), (SMULTB GPR:$a, GPR:$b)>; def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), (SMULTT GPR:$a, GPR:$b)>; def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), (SMULWB GPR:$a, GPR:$b)>; def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), (SMULWT GPR:$a, GPR:$b)>; def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; // Pre-v7 uses MCR for synchronization barriers. def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, Requires<[IsARM, HasV6]>; // SXT/UXT with no rotate let AddedComplexity = 16 in { def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), (UXTAB GPR:$Rn, GPR:$Rm, 0)>; def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), (UXTAH GPR:$Rn, GPR:$Rm, 0)>; } def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; // Atomic load/store patterns def : ARMPat<(atomic_load_8 ldst_so_reg:$src), (LDRBrs ldst_so_reg:$src)>; def : ARMPat<(atomic_load_8 addrmode_imm12:$src), (LDRBi12 addrmode_imm12:$src)>; def : ARMPat<(atomic_load_16 addrmode3:$src), (LDRH addrmode3:$src)>; def : ARMPat<(atomic_load_32 ldst_so_reg:$src), (LDRrs ldst_so_reg:$src)>; def : ARMPat<(atomic_load_32 addrmode_imm12:$src), (LDRi12 addrmode_imm12:$src)>; def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), (STRBrs GPR:$val, ldst_so_reg:$ptr)>; def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), (STRH GPR:$val, addrmode3:$ptr)>; def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), (STRrs GPR:$val, ldst_so_reg:$ptr)>; def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), (STRi12 GPR:$val, addrmode_imm12:$ptr)>; //===----------------------------------------------------------------------===// // Thumb Support // include "ARMInstrThumb.td" //===----------------------------------------------------------------------===// // Thumb2 Support // include "ARMInstrThumb2.td" //===----------------------------------------------------------------------===// // Floating Point Support // include "ARMInstrVFP.td" //===----------------------------------------------------------------------===// // Advanced SIMD (NEON) Support // include "ARMInstrNEON.td" //===----------------------------------------------------------------------===// // Assembler aliases // // Memory barriers def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; // Armv8-R 'Data Full Barrier' def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; // System instructions def : MnemonicAlias<"swi", "svc">; // Load / Store Multiple def : MnemonicAlias<"ldmfd", "ldm">; def : MnemonicAlias<"ldmia", "ldm">; def : MnemonicAlias<"ldmea", "ldmdb">; def : MnemonicAlias<"stmfd", "stmdb">; def : MnemonicAlias<"stmia", "stm">; def : MnemonicAlias<"stmea", "stm">; // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the // input operands swapped when the shift amount is zero (i.e., unspecified). def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, Requires<[IsARM, HasV6]>; def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, Requires<[IsARM, HasV6]>; // PUSH/POP aliases for STM/LDM def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; // SSAT/USAT optional shift operand. def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; // Extend instruction optional rotate operand. def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"sxtb${p} $Rd, $Rm", (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"sxth${p} $Rd, $Rm", (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"uxtb${p} $Rd, $Rm", (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; def : ARMInstAlias<"uxth${p} $Rd, $Rm", (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; // RFE aliases def : MnemonicAlias<"rfefa", "rfeda">; def : MnemonicAlias<"rfeea", "rfedb">; def : MnemonicAlias<"rfefd", "rfeia">; def : MnemonicAlias<"rfeed", "rfeib">; def : MnemonicAlias<"rfe", "rfeia">; // SRS aliases def : MnemonicAlias<"srsfa", "srsib">; def : MnemonicAlias<"srsea", "srsia">; def : MnemonicAlias<"srsfd", "srsdb">; def : MnemonicAlias<"srsed", "srsda">; def : MnemonicAlias<"srs", "srsia">; // QSAX == QSUBADDX def : MnemonicAlias<"qsubaddx", "qsax">; // SASX == SADDSUBX def : MnemonicAlias<"saddsubx", "sasx">; // SHASX == SHADDSUBX def : MnemonicAlias<"shaddsubx", "shasx">; // SHSAX == SHSUBADDX def : MnemonicAlias<"shsubaddx", "shsax">; // SSAX == SSUBADDX def : MnemonicAlias<"ssubaddx", "ssax">; // UASX == UADDSUBX def : MnemonicAlias<"uaddsubx", "uasx">; // UHASX == UHADDSUBX def : MnemonicAlias<"uhaddsubx", "uhasx">; // UHSAX == UHSUBADDX def : MnemonicAlias<"uhsubaddx", "uhsax">; // UQASX == UQADDSUBX def : MnemonicAlias<"uqaddsubx", "uqasx">; // UQSAX == UQSUBADDX def : MnemonicAlias<"uqsubaddx", "uqsax">; // USAX == USUBADDX def : MnemonicAlias<"usubaddx", "usax">; // "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like // for isel. def : ARMInstSubst<"mov${s}${p} $Rd, $imm", (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; // Same for AND <--> BIC def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"and${s}${p} $Rdn, $imm", (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; // Likewise, "add Rd, mod_imm_neg" -> sub def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"add${s}${p} $Rd, $imm", (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; // Likewise, "sub Rd, mod_imm_neg" -> add def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"sub${s}${p} $Rd, $imm", (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; // Same for CMP <--> CMN via mod_imm_neg def : ARMInstSubst<"cmp${p} $Rd, $imm", (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; def : ARMInstSubst<"cmn${p} $Rd, $imm", (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; // The shifter forms of the MOV instruction are aliased to the ASR, LSL, // LSR, ROR, and RRX instructions. // FIXME: We need C++ parser hooks to map the alias to the MOV // encoding. It seems we should be able to do that sort of thing // in tblgen, but it could get ugly. let TwoOperandAliasConstraint = "$Rm = $Rd" in { def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>; def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>; def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; } def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; let TwoOperandAliasConstraint = "$Rn = $Rd" in { def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>; def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>; def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>; def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>; } // "neg" is and alias for "rsb rd, rn, #0" def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; // Pre-v6, 'mov r0, r0' was used as a NOP encoding. def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, Requires<[IsARM, NoV6]>; // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but // the instruction definitions need difference constraints pre-v6. // Use these aliases for the assembly parsing on pre-v6. def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, Requires<[IsARM, NoV6]>; def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s), 0>, Requires<[IsARM, NoV6]>; def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, Requires<[IsARM, NoV6]>; def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, Requires<[IsARM, NoV6]>; def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, Requires<[IsARM, NoV6]>; def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, Requires<[IsARM, NoV6]>; // 'it' blocks in ARM mode just validate the predicates. The IT itself // is discarded. def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, ComplexDeprecationPredicate<"IT">; let mayLoad = 1, mayStore =1, hasSideEffects = 1 in def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), NoItinerary, [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; //===---------------------------------- // Atomic cmpxchg for -O0 //===---------------------------------- // The fast register allocator used during -O0 inserts spills to cover any VRegs // live across basic block boundaries. When this happens between an LDXR and an // STXR it can clear the exclusive monitor, causing all cmpxchg attempts to // fail. // Unfortunately, this means we have to have an alternative (expanded // post-regalloc) path for -O0 compilations. Fortunately this path can be // significantly more naive than the standard expansion: we conservatively // assume seq_cst, strong cmpxchg and omit clrex on failure. let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", mayLoad = 1, mayStore = 1 in { def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), (ins GPR:$addr, GPR:$desired, GPR:$new), NoItinerary, []>, Sched<[]>; def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), (ins GPR:$addr, GPR:$desired, GPR:$new), NoItinerary, []>, Sched<[]>; def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), (ins GPR:$addr, GPR:$desired, GPR:$new), NoItinerary, []>, Sched<[]>; def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), NoItinerary, []>, Sched<[]>; } def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, [(atomic_fence imm:$ordering, 0)]> { let hasSideEffects = 1; let Size = 0; let AsmString = "@ COMPILER BARRIER"; } capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARMInstrNEON.td000064400000000000000000014652430072674642500242600ustar 00000000000000//===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file describes the ARM NEON instruction set. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // NEON-specific Operands. //===----------------------------------------------------------------------===// def nModImm : Operand { let PrintMethod = "printNEONModImmOperand"; } def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; } def nImmSplatI8 : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmSplatI8AsmOperand; } def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; } def nImmSplatI16 : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmSplatI16AsmOperand; } def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; } def nImmSplatI32 : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmSplatI32AsmOperand; } def nImmSplatNotI16AsmOperand : AsmOperandClass { let Name = "NEONi16splatNot"; } def nImmSplatNotI16 : Operand { let ParserMatchClass = nImmSplatNotI16AsmOperand; } def nImmSplatNotI32AsmOperand : AsmOperandClass { let Name = "NEONi32splatNot"; } def nImmSplatNotI32 : Operand { let ParserMatchClass = nImmSplatNotI32AsmOperand; } def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; } def nImmVMOVI32 : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmVMOVI32AsmOperand; } class nImmVMOVIAsmOperandReplicate : AsmOperandClass { let Name = "NEONi" # To.Size # "vmovi" # From.Size # "Replicate"; let PredicateMethod = "isNEONmovReplicate<" # From.Size # ", " # To.Size # ">"; let RenderMethod = "addNEONvmovi" # From.Size # "ReplicateOperands"; } class nImmVINVIAsmOperandReplicate : AsmOperandClass { let Name = "NEONi" # To.Size # "invi" # From.Size # "Replicate"; let PredicateMethod = "isNEONinvReplicate<" # From.Size # ", " # To.Size # ">"; let RenderMethod = "addNEONinvi" # From.Size # "ReplicateOperands"; } class nImmVMOVIReplicate : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmVMOVIAsmOperandReplicate; } class nImmVINVIReplicate : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmVINVIAsmOperandReplicate; } def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; } def nImmVMOVI32Neg : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmVMOVI32NegAsmOperand; } def nImmVMOVF32 : Operand { let PrintMethod = "printFPImmOperand"; let ParserMatchClass = FPImmOperand; } def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; } def nImmSplatI64 : Operand { let PrintMethod = "printNEONModImmOperand"; let ParserMatchClass = nImmSplatI64AsmOperand; } def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; } def VectorIndex64Operand : AsmOperandClass { let Name = "VectorIndex64"; } def VectorIndex8 : Operand, ImmLeaf { let ParserMatchClass = VectorIndex8Operand; let PrintMethod = "printVectorIndex"; let MIOperandInfo = (ops i32imm); } def VectorIndex16 : Operand, ImmLeaf { let ParserMatchClass = VectorIndex16Operand; let PrintMethod = "printVectorIndex"; let MIOperandInfo = (ops i32imm); } def VectorIndex32 : Operand, ImmLeaf { let ParserMatchClass = VectorIndex32Operand; let PrintMethod = "printVectorIndex"; let MIOperandInfo = (ops i32imm); } def VectorIndex64 : Operand, ImmLeaf { let ParserMatchClass = VectorIndex64Operand; let PrintMethod = "printVectorIndex"; let MIOperandInfo = (ops i32imm); } // Register list of one D register. def VecListOneDAsmOperand : AsmOperandClass { let Name = "VecListOneD"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListOneD : RegisterOperand { let ParserMatchClass = VecListOneDAsmOperand; } // Register list of two sequential D registers. def VecListDPairAsmOperand : AsmOperandClass { let Name = "VecListDPair"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListDPair : RegisterOperand { let ParserMatchClass = VecListDPairAsmOperand; } // Register list of three sequential D registers. def VecListThreeDAsmOperand : AsmOperandClass { let Name = "VecListThreeD"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListThreeD : RegisterOperand { let ParserMatchClass = VecListThreeDAsmOperand; } // Register list of four sequential D registers. def VecListFourDAsmOperand : AsmOperandClass { let Name = "VecListFourD"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListFourD : RegisterOperand { let ParserMatchClass = VecListFourDAsmOperand; } // Register list of two D registers spaced by 2 (two sequential Q registers). def VecListDPairSpacedAsmOperand : AsmOperandClass { let Name = "VecListDPairSpaced"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListDPairSpaced : RegisterOperand { let ParserMatchClass = VecListDPairSpacedAsmOperand; } // Register list of three D registers spaced by 2 (three Q registers). def VecListThreeQAsmOperand : AsmOperandClass { let Name = "VecListThreeQ"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListThreeQ : RegisterOperand { let ParserMatchClass = VecListThreeQAsmOperand; } // Register list of three D registers spaced by 2 (three Q registers). def VecListFourQAsmOperand : AsmOperandClass { let Name = "VecListFourQ"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListFourQ : RegisterOperand { let ParserMatchClass = VecListFourQAsmOperand; } // Register list of one D register, with "all lanes" subscripting. def VecListOneDAllLanesAsmOperand : AsmOperandClass { let Name = "VecListOneDAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListOneDAllLanes : RegisterOperand { let ParserMatchClass = VecListOneDAllLanesAsmOperand; } // Register list of two D registers, with "all lanes" subscripting. def VecListDPairAllLanesAsmOperand : AsmOperandClass { let Name = "VecListDPairAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListDPairAllLanes : RegisterOperand { let ParserMatchClass = VecListDPairAllLanesAsmOperand; } // Register list of two D registers spaced by 2 (two sequential Q registers). def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass { let Name = "VecListDPairSpacedAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListDPairSpacedAllLanes : RegisterOperand { let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand; } // Register list of three D registers, with "all lanes" subscripting. def VecListThreeDAllLanesAsmOperand : AsmOperandClass { let Name = "VecListThreeDAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListThreeDAllLanes : RegisterOperand { let ParserMatchClass = VecListThreeDAllLanesAsmOperand; } // Register list of three D registers spaced by 2 (three sequential Q regs). def VecListThreeQAllLanesAsmOperand : AsmOperandClass { let Name = "VecListThreeQAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListThreeQAllLanes : RegisterOperand { let ParserMatchClass = VecListThreeQAllLanesAsmOperand; } // Register list of four D registers, with "all lanes" subscripting. def VecListFourDAllLanesAsmOperand : AsmOperandClass { let Name = "VecListFourDAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListFourDAllLanes : RegisterOperand { let ParserMatchClass = VecListFourDAllLanesAsmOperand; } // Register list of four D registers spaced by 2 (four sequential Q regs). def VecListFourQAllLanesAsmOperand : AsmOperandClass { let Name = "VecListFourQAllLanes"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListOperands"; } def VecListFourQAllLanes : RegisterOperand { let ParserMatchClass = VecListFourQAllLanesAsmOperand; } // Register list of one D register, with byte lane subscripting. def VecListOneDByteIndexAsmOperand : AsmOperandClass { let Name = "VecListOneDByteIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListOneDByteIndexed : Operand { let ParserMatchClass = VecListOneDByteIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with half-word lane subscripting. def VecListOneDHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListOneDHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListOneDHWordIndexed : Operand { let ParserMatchClass = VecListOneDHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListOneDWordIndexAsmOperand : AsmOperandClass { let Name = "VecListOneDWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListOneDWordIndexed : Operand { let ParserMatchClass = VecListOneDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // Register list of two D registers with byte lane subscripting. def VecListTwoDByteIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoDByteIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListTwoDByteIndexed : Operand { let ParserMatchClass = VecListTwoDByteIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with half-word lane subscripting. def VecListTwoDHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoDHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListTwoDHWordIndexed : Operand { let ParserMatchClass = VecListTwoDHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListTwoDWordIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoDWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListTwoDWordIndexed : Operand { let ParserMatchClass = VecListTwoDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // Register list of two Q registers with half-word lane subscripting. def VecListTwoQHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoQHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListTwoQHWordIndexed : Operand { let ParserMatchClass = VecListTwoQHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListTwoQWordIndexAsmOperand : AsmOperandClass { let Name = "VecListTwoQWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListTwoQWordIndexed : Operand { let ParserMatchClass = VecListTwoQWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // Register list of three D registers with byte lane subscripting. def VecListThreeDByteIndexAsmOperand : AsmOperandClass { let Name = "VecListThreeDByteIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListThreeDByteIndexed : Operand { let ParserMatchClass = VecListThreeDByteIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with half-word lane subscripting. def VecListThreeDHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListThreeDHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListThreeDHWordIndexed : Operand { let ParserMatchClass = VecListThreeDHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListThreeDWordIndexAsmOperand : AsmOperandClass { let Name = "VecListThreeDWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListThreeDWordIndexed : Operand { let ParserMatchClass = VecListThreeDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // Register list of three Q registers with half-word lane subscripting. def VecListThreeQHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListThreeQHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListThreeQHWordIndexed : Operand { let ParserMatchClass = VecListThreeQHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListThreeQWordIndexAsmOperand : AsmOperandClass { let Name = "VecListThreeQWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListThreeQWordIndexed : Operand { let ParserMatchClass = VecListThreeQWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // Register list of four D registers with byte lane subscripting. def VecListFourDByteIndexAsmOperand : AsmOperandClass { let Name = "VecListFourDByteIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListFourDByteIndexed : Operand { let ParserMatchClass = VecListFourDByteIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with half-word lane subscripting. def VecListFourDHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListFourDHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListFourDHWordIndexed : Operand { let ParserMatchClass = VecListFourDHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListFourDWordIndexAsmOperand : AsmOperandClass { let Name = "VecListFourDWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListFourDWordIndexed : Operand { let ParserMatchClass = VecListFourDWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // Register list of four Q registers with half-word lane subscripting. def VecListFourQHWordIndexAsmOperand : AsmOperandClass { let Name = "VecListFourQHWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListFourQHWordIndexed : Operand { let ParserMatchClass = VecListFourQHWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } // ...with word lane subscripting. def VecListFourQWordIndexAsmOperand : AsmOperandClass { let Name = "VecListFourQWordIndexed"; let ParserMethod = "parseVectorList"; let RenderMethod = "addVecListIndexedOperands"; } def VecListFourQWordIndexed : Operand { let ParserMatchClass = VecListFourQWordIndexAsmOperand; let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); } def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return cast(N)->getAlignment() >= 8; }]>; def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{ return cast(N)->getAlignment() >= 8; }]>; def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return cast(N)->getAlignment() == 4; }]>; def word_alignedstore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{ return cast(N)->getAlignment() == 4; }]>; def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return cast(N)->getAlignment() == 2; }]>; def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{ return cast(N)->getAlignment() == 2; }]>; def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return cast(N)->getAlignment() == 1; }]>; def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{ return cast(N)->getAlignment() == 1; }]>; def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ return cast(N)->getAlignment() < 4; }]>; def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr), (store node:$val, node:$ptr), [{ return cast(N)->getAlignment() < 4; }]>; //===----------------------------------------------------------------------===// // NEON-specific DAG Nodes. //===----------------------------------------------------------------------===// def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; def SDTARMVCMPZ : SDTypeProfile<1, 1, []>; def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>; def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>; def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>; def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>; def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>; def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; // Types for vector shift by immediates. The "SHX" version is for long and // narrow operations where the source and destination vectors have different // types. The "SHINS" version is for shift and insert operations. def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, i32>]>; def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, SDTCisVT<2, i32>]>; def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; def NEONvbsl : SDNode<"ARMISD::VBSL", SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>>; def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; // VDUPLANE can produce a quad-register result from a double-register source, // so the result is not constrained to match the source. def NEONvduplane : SDNode<"ARMISD::VDUPLANE", SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i32>]>>; def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>; def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>; def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>; def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>; def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; def SDTARMVTBL1 : SDTypeProfile<1, 2, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>, SDTCisVT<2, v8i8>]>; def SDTARMVTBL2 : SDTypeProfile<1, 3, [SDTCisVT<0, v8i8>, SDTCisVT<1, v8i8>, SDTCisVT<2, v8i8>, SDTCisVT<3, v8i8>]>; def NEONvtbl1 : SDNode<"ARMISD::VTBL1", SDTARMVTBL1>; def NEONvtbl2 : SDNode<"ARMISD::VTBL2", SDTARMVTBL2>; def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{ ConstantSDNode *ConstVal = cast(N->getOperand(0)); unsigned EltBits = 0; uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); return (EltBits == 32 && EltVal == 0); }]>; def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{ ConstantSDNode *ConstVal = cast(N->getOperand(0)); unsigned EltBits = 0; uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); return (EltBits == 8 && EltVal == 0xff); }]>; //===----------------------------------------------------------------------===// // NEON load / store instructions //===----------------------------------------------------------------------===// // Use VLDM to load a Q register as a D register pair. // This is a pseudo instruction that is expanded to VLDMD after reg alloc. def VLDMQIA : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn), IIC_fpLoad_m, "", [(set DPair:$dst, (v2f64 (word_alignedload GPR:$Rn)))]>; // Use VSTM to store a Q register as a D register pair. // This is a pseudo instruction that is expanded to VSTMD after reg alloc. def VSTMQIA : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn), IIC_fpStore_m, "", [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)]>; // Classes for VLD* pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VLDQPseudo : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">; class VLDQWBPseudo : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset), itin, "$addr.addr = $wb">; class VLDQWBfixedPseudo : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), (ins addrmode6:$addr), itin, "$addr.addr = $wb">; class VLDQWBregisterPseudo : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), (ins addrmode6:$addr, rGPR:$offset), itin, "$addr.addr = $wb">; class VLDQQPseudo : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">; class VLDQQWBPseudo : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset), itin, "$addr.addr = $wb">; class VLDQQWBfixedPseudo : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), (ins addrmode6:$addr), itin, "$addr.addr = $wb">; class VLDQQWBregisterPseudo : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), (ins addrmode6:$addr, rGPR:$offset), itin, "$addr.addr = $wb">; class VLDQQQQPseudo : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin, "$src = $dst">; class VLDQQQQWBPseudo : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, "$addr.addr = $wb, $src = $dst">; let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string Dt, Operand AddrMode> : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd), (ins AddrMode:$Rn), IIC_VLD1, "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } class VLD1Q op7_4, string Dt, Operand AddrMode> : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd), (ins AddrMode:$Rn), IIC_VLD1x2, "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>; def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>; def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>; def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>; def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>; def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>; def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>; def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>; // ...with address register writeback: multiclass VLD1DWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD1u, "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } multiclass VLD1QWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>; defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>; defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>; defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>; defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>; defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>; defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>; defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>; // ...with 3 registers class VLD1D3 op7_4, string Dt, Operand AddrMode> : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd), (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD3]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } multiclass VLD1D3WB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>; def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>; def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>; def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>; defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>; defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>; defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>; defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>; def VLD1d8TPseudo : VLDQQPseudo, Sched<[WriteVLD3]>; def VLD1d16TPseudo : VLDQQPseudo, Sched<[WriteVLD3]>; def VLD1d32TPseudo : VLDQQPseudo, Sched<[WriteVLD3]>; def VLD1d64TPseudo : VLDQQPseudo, Sched<[WriteVLD3]>; def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo, Sched<[WriteVLD3]>; def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo, Sched<[WriteVLD3]>; def VLD1q8HighTPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD1q8LowTPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD1q16HighTPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD1q16LowTPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD1q32HighTPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD1q32LowTPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD1q64HighTPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD1q64LowTPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; // ...with 4 registers class VLD1D4 op7_4, string Dt, Operand AddrMode> : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd), (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD4]> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } multiclass VLD1D4WB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVLD4]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD4]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>; def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>; def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>; def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>; defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>; defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>; defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>; defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>; def VLD1d8QPseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD1d16QPseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD1d32QPseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD1d64QPseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo, Sched<[WriteVLD4]>; def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo, Sched<[WriteVLD4]>; def VLD1q8LowQPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD1q8HighQPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; def VLD1q16LowQPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD1q16HighQPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; def VLD1q32LowQPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD1q32HighQPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; def VLD1q64LowQPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD1q64HighQPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; // VLD2 : Vector Load (multiple 2-element structures) class VLD2 op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd), (ins AddrMode:$Rn), itin, "vld2", Dt, "$Vd, $Rn", "", []> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2, addrmode6align64or128>, Sched<[WriteVLD2]>; def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2, addrmode6align64or128>, Sched<[WriteVLD2]>; def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2, addrmode6align64or128>, Sched<[WriteVLD2]>; def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2, addrmode6align64or128or256>, Sched<[WriteVLD4]>; def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2, addrmode6align64or128or256>, Sched<[WriteVLD4]>; def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2, addrmode6align64or128or256>, Sched<[WriteVLD4]>; def VLD2q8Pseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD2q16Pseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD2q32Pseudo : VLDQQPseudo, Sched<[WriteVLD4]>; // ...with address register writeback: multiclass VLD2WB op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> { def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), (ins AddrMode:$Rn), itin, "vld2", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), itin, "vld2", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } } defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u, addrmode6align64or128>, Sched<[WriteVLD2]>; defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u, addrmode6align64or128>, Sched<[WriteVLD2]>; defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u, addrmode6align64or128>, Sched<[WriteVLD2]>; defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u, addrmode6align64or128or256>, Sched<[WriteVLD4]>; defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u, addrmode6align64or128or256>, Sched<[WriteVLD4]>; defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u, addrmode6align64or128or256>, Sched<[WriteVLD4]>; def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo, Sched<[WriteVLD4]>; def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo, Sched<[WriteVLD4]>; def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo, Sched<[WriteVLD4]>; def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo, Sched<[WriteVLD4]>; def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo, Sched<[WriteVLD4]>; def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo, Sched<[WriteVLD4]>; // ...with double-spaced registers def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2, addrmode6align64or128>, Sched<[WriteVLD2]>; def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2, addrmode6align64or128>, Sched<[WriteVLD2]>; def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2, addrmode6align64or128>, Sched<[WriteVLD2]>; defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u, addrmode6align64or128>, Sched<[WriteVLD2]>; defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u, addrmode6align64or128>, Sched<[WriteVLD2]>; defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u, addrmode6align64or128>, Sched<[WriteVLD2]>; // VLD3 : Vector Load (multiple 3-element structures) class VLD3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), (ins addrmode6:$Rn), IIC_VLD3, "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []>, Sched<[WriteVLD3]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST3Instruction"; } def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">; def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">; def VLD3d8Pseudo : VLDQQPseudo, Sched<[WriteVLD3]>; def VLD3d16Pseudo : VLDQQPseudo, Sched<[WriteVLD3]>; def VLD3d32Pseudo : VLDQQPseudo, Sched<[WriteVLD3]>; // ...with address register writeback: class VLD3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD3]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST3Instruction"; } def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">; def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">; def VLD3d8Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD3]>; def VLD3d16Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD3]>; def VLD3d32Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD3]>; // ...with double-spaced registers: def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">; def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">; def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">; def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">; def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">; def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">; def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; // ...alternate versions to be allocated odd register numbers: def VLD3q8oddPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD3q16oddPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD3q32oddPseudo : VLDQQQQPseudo, Sched<[WriteVLD3]>; def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD3]>; // VLD4 : Vector Load (multiple 4-element structures) class VLD4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$Rn), IIC_VLD4, "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []>, Sched<[WriteVLD4]> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST4Instruction"; } def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">; def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">; def VLD4d8Pseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD4d16Pseudo : VLDQQPseudo, Sched<[WriteVLD4]>; def VLD4d32Pseudo : VLDQQPseudo, Sched<[WriteVLD4]>; // ...with address register writeback: class VLD4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u, "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD4]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST4Instruction"; } def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">; def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">; def VLD4d8Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD4]>; def VLD4d16Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD4]>; def VLD4d32Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD4]>; // ...with double-spaced registers: def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">; def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">; def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">; def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">; def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">; def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">; def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; // ...alternate versions to be allocated odd register numbers: def VLD4q8oddPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; def VLD4q16oddPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; def VLD4q32oddPseudo : VLDQQQQPseudo, Sched<[WriteVLD4]>; def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo, Sched<[WriteVLD4]>; } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 // Classes for VLD*LN pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VLDQLNPseudo : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), itin, "$src = $dst">; class VLDQLNWBPseudo : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; class VLDQQLNPseudo : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), itin, "$src = $dst">; class VLDQQLNWBPseudo : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; class VLDQQQQLNPseudo : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), itin, "$src = $dst">; class VLDQQQQLNWBPseudo : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; // VLD1LN : Vector Load (single element to one lane) class VLD1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", "$src = $Vd", [(set DPR:$Vd, (vector_insert (Ty DPR:$src), (i32 (LoadOp addrmode6:$Rn)), imm:$lane))]> { let Rm = 0b1111; let DecoderMethod = "DecodeVLD1LN"; } class VLD1LN32 op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane), IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", "$src = $Vd", [(set DPR:$Vd, (vector_insert (Ty DPR:$src), (i32 (LoadOp addrmode6oneL32:$Rn)), imm:$lane))]>, Sched<[WriteVLD1]> { let Rm = 0b1111; let DecoderMethod = "DecodeVLD1LN"; } class VLD1QLNPseudo : VLDQLNPseudo, Sched<[WriteVLD1]> { let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), (i32 (LoadOp addrmode6:$addr)), imm:$lane))]; } def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> { let Inst{7-5} = lane{2-0}; } def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> { let Inst{7-6} = lane{1-0}; let Inst{5-4} = Rn{5-4}; } def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> { let Inst{7} = lane{0}; let Inst{5-4} = Rn{5-4}; } def VLD1LNq8Pseudo : VLD1QLNPseudo; def VLD1LNq16Pseudo : VLD1QLNPseudo; def VLD1LNq32Pseudo : VLD1QLNPseudo; def : Pat<(vector_insert (v2f32 DPR:$src), (f32 (load addrmode6:$addr)), imm:$lane), (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>; def : Pat<(vector_insert (v4f32 QPR:$src), (f32 (load addrmode6:$addr)), imm:$lane), (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>; // A 64-bit subvector insert to the first 128-bit vector position // is a subregister copy that needs no instruction. def : Pat<(insert_subvector undef, (v1i64 DPR:$src), (i32 0)), (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; def : Pat<(insert_subvector undef, (v2i32 DPR:$src), (i32 0)), (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; def : Pat<(insert_subvector undef, (v2f32 DPR:$src), (i32 0)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; def : Pat<(insert_subvector undef, (v4i16 DPR:$src), (i32 0)), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; def : Pat<(insert_subvector undef, (v4f16 DPR:$src), (i32 0)), (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; def : Pat<(insert_subvector (v16i8 undef), (v8i8 DPR:$src), (i32 0)), (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { // ...with address register writeback: class VLD1LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn$Rm", "$src = $Vd, $Rn.addr = $wb", []>, Sched<[WriteVLD1]> { let DecoderMethod = "DecodeVLD1LN"; } def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; let Inst{4} = Rn{4}; } def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{4}; let Inst{4} = Rn{4}; } def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo, Sched<[WriteVLD1]>; def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo, Sched<[WriteVLD1]>; def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo, Sched<[WriteVLD1]>; // VLD2LN : Vector Load (single 2-element structure to one lane) class VLD2LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2", []>, Sched<[WriteVLD1]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2LN"; } def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> { let Inst{7} = lane{0}; } def VLD2LNd8Pseudo : VLDQLNPseudo, Sched<[WriteVLD1]>; def VLD2LNd16Pseudo : VLDQLNPseudo, Sched<[WriteVLD1]>; def VLD2LNd32Pseudo : VLDQLNPseudo, Sched<[WriteVLD1]>; // ...with double-spaced registers: def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> { let Inst{7} = lane{0}; } def VLD2LNq16Pseudo : VLDQQLNPseudo, Sched<[WriteVLD1]>; def VLD2LNq32Pseudo : VLDQQLNPseudo, Sched<[WriteVLD1]>; // ...with address register writeback: class VLD2LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2LN"; } def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> { let Inst{7} = lane{0}; } def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo, Sched<[WriteVLD1]>; def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo, Sched<[WriteVLD1]>; def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo, Sched<[WriteVLD1]>; def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> { let Inst{7} = lane{0}; } def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD1]>; def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD1]>; // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []>, Sched<[WriteVLD2]> { let Rm = 0b1111; let DecoderMethod = "DecodeVLD3LN"; } def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> { let Inst{7} = lane{0}; } def VLD3LNd8Pseudo : VLDQQLNPseudo, Sched<[WriteVLD2]>; def VLD3LNd16Pseudo : VLDQQLNPseudo, Sched<[WriteVLD2]>; def VLD3LNd32Pseudo : VLDQQLNPseudo, Sched<[WriteVLD2]>; // ...with double-spaced registers: def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> { let Inst{7} = lane{0}; } def VLD3LNq16Pseudo : VLDQQQQLNPseudo, Sched<[WriteVLD2]>; def VLD3LNq32Pseudo : VLDQQQQLNPseudo, Sched<[WriteVLD2]>; // ...with address register writeback: class VLD3LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VLD3lnu, "vld3", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", []>, Sched<[WriteVLD2]> { let DecoderMethod = "DecodeVLD3LN"; } def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> { let Inst{7} = lane{0}; } def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> { let Inst{7} = lane{0}; } def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo, Sched<[WriteVLD2]>; // VLD4LN : Vector Load (single 4-element structure to one lane) class VLD4LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>, Sched<[WriteVLD2]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD4LN"; } def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VLD4LNd8Pseudo : VLDQQLNPseudo, Sched<[WriteVLD2]>; def VLD4LNd16Pseudo : VLDQQLNPseudo, Sched<[WriteVLD2]>; def VLD4LNd32Pseudo : VLDQQLNPseudo, Sched<[WriteVLD2]>; // ...with double-spaced registers: def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VLD4LNq16Pseudo : VLDQQQQLNPseudo, Sched<[WriteVLD2]>; def VLD4LNq32Pseudo : VLDQQQQLNPseudo, Sched<[WriteVLD2]>; // ...with address register writeback: class VLD4LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VLD4lnu, "vld4", Dt, "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD4LN" ; } def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo, Sched<[WriteVLD2]>; def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo, Sched<[WriteVLD2]>; } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 // VLD1DUP : Vector Load (single element to all lanes) class VLD1DUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp, Operand AddrMode> : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd), (ins AddrMode:$Rn), IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "", [(set VecListOneDAllLanes:$Vd, (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]>, Sched<[WriteVLD2]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD1DupInstruction"; } def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8, addrmode6dupalignNone>; def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16, addrmode6dupalign16>; def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load, addrmode6dupalign32>; def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))), (VLD1DUPd32 addrmode6:$addr)>; class VLD1QDUP op7_4, string Dt, ValueType Ty, PatFrag LoadOp, Operand AddrMode> : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd), (ins AddrMode:$Rn), IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "", [(set VecListDPairAllLanes:$Vd, (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD1DupInstruction"; } def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8, addrmode6dupalignNone>; def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16, addrmode6dupalign16>; def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load, addrmode6dupalign32>; def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))), (VLD1DUPq32 addrmode6:$addr)>; let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { // ...with address register writeback: multiclass VLD1DUPWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD1dupu, "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD1DupInstruction"; } def _register : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD1DupInstruction"; } } multiclass VLD1QDUPWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD1dupu, "vld1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD1DupInstruction"; } def _register : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu, "vld1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD1DupInstruction"; } } defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>; defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>; defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>; defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>; defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>; defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>; // VLD2DUP : Vector Load (single 2-element structure to all lanes) class VLD2DUP op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode> : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd), (ins AddrMode:$Rn), IIC_VLD2dup, "vld2", Dt, "$Vd, $Rn", "", []> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2DupInstruction"; } def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes, addrmode6dupalign16>; def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes, addrmode6dupalign32>; def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes, addrmode6dupalign64>; // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]". // ...with double-spaced registers def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes, addrmode6dupalign16>; def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes, addrmode6dupalign32>; def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes, addrmode6dupalign64>; def VLD2DUPq8EvenPseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD2DUPq8OddPseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD2DUPq16EvenPseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD2DUPq16OddPseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD2DUPq32EvenPseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD2DUPq32OddPseudo : VLDQQPseudo, Sched<[WriteVLD2]>; // ...with address register writeback: multiclass VLD2DUPWB op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode> { def _fixed : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd, GPR:$wb), (ins AddrMode:$Rn), IIC_VLD2dupu, "vld2", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2DupInstruction"; } def _register : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd, GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu, "vld2", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD1]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD2DupInstruction"; } } defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes, addrmode6dupalign16>; defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes, addrmode6dupalign32>; defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes, addrmode6dupalign64>; defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes, addrmode6dupalign16>; defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes, addrmode6dupalign32>; defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes, addrmode6dupalign64>; // VLD3DUP : Vector Load (single 3-element structure to all lanes) class VLD3DUP op7_4, string Dt> : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), (ins addrmode6dup:$Rn), IIC_VLD3dup, "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []>, Sched<[WriteVLD2]> { let Rm = 0b1111; let Inst{4} = 0; let DecoderMethod = "DecodeVLD3DupInstruction"; } def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">; def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">; def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">; def VLD3DUPd8Pseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPd16Pseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPd32Pseudo : VLDQQPseudo, Sched<[WriteVLD2]>; // ...with double-spaced registers (not used for codegen): def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">; def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">; def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">; def VLD3DUPq8EvenPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPq8OddPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPq16EvenPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPq16OddPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPq32EvenPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD3DUPq32OddPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; // ...with address register writeback: class VLD3DUPWB op7_4, string Dt, Operand AddrMode> : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu, "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> { let Inst{4} = 0; let DecoderMethod = "DecodeVLD3DupInstruction"; } def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>; def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>; def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>; def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>; def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>; def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>; def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD2]>; def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD2]>; def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD2]>; // VLD4DUP : Vector Load (single 4-element structure to all lanes) class VLD4DUP op7_4, string Dt> : NLdSt<1, 0b10, 0b1111, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), (ins addrmode6dup:$Rn), IIC_VLD4dup, "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD4DupInstruction"; } def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">; def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">; def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; } def VLD4DUPd8Pseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPd16Pseudo : VLDQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPd32Pseudo : VLDQQPseudo, Sched<[WriteVLD2]>; // ...with double-spaced registers (not used for codegen): def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">; def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">; def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; } def VLD4DUPq8EvenPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPq8OddPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPq16EvenPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPq16OddPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPq32EvenPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; def VLD4DUPq32OddPseudo : VLDQQQQPseudo, Sched<[WriteVLD2]>; // ...with address register writeback: class VLD4DUPWB op7_4, string Dt> : NLdSt<1, 0b10, 0b1111, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu, "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm", "$Rn.addr = $wb", []>, Sched<[WriteVLD2]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLD4DupInstruction"; } def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">; def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">; def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; } def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">; def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">; def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; } def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD2]>; def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD2]>; def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo, Sched<[WriteVLD2]>; } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { // Classes for VST* pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VSTQPseudo : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">; class VSTQWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin, "$addr.addr = $wb">; class VSTQWBfixedPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, QPR:$src), itin, "$addr.addr = $wb">; class VSTQWBregisterPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin, "$addr.addr = $wb">; class VSTQQPseudo : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">; class VSTQQWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin, "$addr.addr = $wb">; class VSTQQWBfixedPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, QQPR:$src), itin, "$addr.addr = $wb">; class VSTQQWBregisterPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin, "$addr.addr = $wb">; class VSTQQQQPseudo : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">; class VSTQQQQWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, "$addr.addr = $wb">; // VST1 : Vector Store (multiple single elements) class VST1D op7_4, string Dt, Operand AddrMode> : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST1]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } class VST1Q op7_4, string Dt, Operand AddrMode> : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST2]> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>; def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>; def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>; def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>; def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>; def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>; def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>; def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>; // ...with address register writeback: multiclass VST1DWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u, "vst1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVST1]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd), IIC_VLD1u, "vst1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST1]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } multiclass VST1QWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u, "vst1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVST2]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd), IIC_VLD1x2u, "vst1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST2]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>; defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>; defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>; defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>; defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>; defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>; defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>; defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>; // ...with 3 registers class VST1D3 op7_4, string Dt, Operand AddrMode> : NLdSt<0, 0b00, 0b0110, op7_4, (outs), (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST3]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST1Instruction"; } multiclass VST1D3WB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u, "vst1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVST3]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd), IIC_VLD1x3u, "vst1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST3]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>; def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>; def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>; def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>; defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>; defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>; defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>; defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>; def VST1d8TPseudo : VSTQQPseudo, Sched<[WriteVST3]>; def VST1d16TPseudo : VSTQQPseudo, Sched<[WriteVST3]>; def VST1d32TPseudo : VSTQQPseudo, Sched<[WriteVST3]>; def VST1d64TPseudo : VSTQQPseudo, Sched<[WriteVST3]>; def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo, Sched<[WriteVST3]>; def VST1d64TPseudoWB_register : VSTQQWBPseudo, Sched<[WriteVST3]>; def VST1q8HighTPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST1q8LowTPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST1q16HighTPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST1q16LowTPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST1q32HighTPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST1q32LowTPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST1q64HighTPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST1q64LowTPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; // ...with 4 registers class VST1D4 op7_4, string Dt, Operand AddrMode> : NLdSt<0, 0b00, 0b0010, op7_4, (outs), (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST4]> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } multiclass VST1D4WB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u, "vst1", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVST4]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd), IIC_VLD1x4u, "vst1", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST4]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST1Instruction"; } } def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>; def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>; def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>; def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>; defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>; defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>; defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>; defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>; def VST1d8QPseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST1d16QPseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST1d32QPseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST1d64QPseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo, Sched<[WriteVST4]>; def VST1d64QPseudoWB_register : VSTQQWBPseudo, Sched<[WriteVST4]>; def VST1q8HighQPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST1q8LowQPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST1q16HighQPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST1q16LowQPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST1q32HighQPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST1q32LowQPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST1q64HighQPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST1q64LowQPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; // VST2 : Vector Store (multiple 2-element structures) class VST2 op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd), itin, "vst2", Dt, "$Vd, $Rn", "", []> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2, addrmode6align64or128>, Sched<[WriteVST2]>; def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2, addrmode6align64or128>, Sched<[WriteVST2]>; def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2, addrmode6align64or128>, Sched<[WriteVST2]>; def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2, addrmode6align64or128or256>, Sched<[WriteVST4]>; def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2, addrmode6align64or128or256>, Sched<[WriteVST4]>; def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2, addrmode6align64or128or256>, Sched<[WriteVST4]>; def VST2q8Pseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST2q16Pseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST2q32Pseudo : VSTQQPseudo, Sched<[WriteVST4]>; // ...with address register writeback: multiclass VST2DWB op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode> { def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u, "vst2", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVST2]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u, "vst2", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST2]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } } multiclass VST2QWB op7_4, string Dt, Operand AddrMode> { def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u, "vst2", Dt, "$Vd, $Rn!", "$Rn.addr = $wb", []>, Sched<[WriteVST4]> { let Rm = 0b1101; // NLdSt will assign to the right encoding bits. let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd), IIC_VLD1u, "vst2", Dt, "$Vd, $Rn, $Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST4]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST2Instruction"; } } defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair, addrmode6align64or128>; defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair, addrmode6align64or128>; defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair, addrmode6align64or128>; defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>; defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>; defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>; def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo, Sched<[WriteVST4]>; def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo, Sched<[WriteVST4]>; def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo, Sched<[WriteVST4]>; def VST2q8PseudoWB_register : VSTQQWBregisterPseudo, Sched<[WriteVST4]>; def VST2q16PseudoWB_register : VSTQQWBregisterPseudo, Sched<[WriteVST4]>; def VST2q32PseudoWB_register : VSTQQWBregisterPseudo, Sched<[WriteVST4]>; // ...with double-spaced registers def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2, addrmode6align64or128>; def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2, addrmode6align64or128>; def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2, addrmode6align64or128>; defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, addrmode6align64or128>; defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, addrmode6align64or128>; defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, addrmode6align64or128>; // VST3 : Vector Store (multiple 3-element structures) class VST3D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST3Instruction"; } def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">; def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">; def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">; def VST3d8Pseudo : VSTQQPseudo, Sched<[WriteVST3]>; def VST3d16Pseudo : VSTQQPseudo, Sched<[WriteVST3]>; def VST3d32Pseudo : VSTQQPseudo, Sched<[WriteVST3]>; // ...with address register writeback: class VST3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u, "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST3]> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVLDST3Instruction"; } def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">; def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">; def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">; def VST3d8Pseudo_UPD : VSTQQWBPseudo, Sched<[WriteVST3]>; def VST3d16Pseudo_UPD : VSTQQWBPseudo, Sched<[WriteVST3]>; def VST3d32Pseudo_UPD : VSTQQWBPseudo, Sched<[WriteVST3]>; // ...with double-spaced registers: def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">; def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">; def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">; def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">; def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">; def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">; def VST3q8Pseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST3q16Pseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST3q32Pseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; // ...alternate versions to be allocated odd register numbers: def VST3q8oddPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST3q16oddPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST3q32oddPseudo : VSTQQQQPseudo, Sched<[WriteVST3]>; def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST3]>; // VST4 : Vector Store (multiple 4-element structures) class VST4D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "", []>, Sched<[WriteVST4]> { let Rm = 0b1111; let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST4Instruction"; } def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">; def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">; def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">; def VST4d8Pseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST4d16Pseudo : VSTQQPseudo, Sched<[WriteVST4]>; def VST4d32Pseudo : VSTQQPseudo, Sched<[WriteVST4]>; // ...with address register writeback: class VST4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", "$Rn.addr = $wb", []>, Sched<[WriteVST4]> { let Inst{5-4} = Rn{5-4}; let DecoderMethod = "DecodeVLDST4Instruction"; } def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">; def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">; def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">; def VST4d8Pseudo_UPD : VSTQQWBPseudo, Sched<[WriteVST4]>; def VST4d16Pseudo_UPD : VSTQQWBPseudo, Sched<[WriteVST4]>; def VST4d32Pseudo_UPD : VSTQQWBPseudo, Sched<[WriteVST4]>; // ...with double-spaced registers: def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">; def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">; def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">; def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">; def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">; def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">; def VST4q8Pseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST4q16Pseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST4q32Pseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; // ...alternate versions to be allocated odd register numbers: def VST4q8oddPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST4q16oddPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST4q32oddPseudo : VSTQQQQPseudo, Sched<[WriteVST4]>; def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo, Sched<[WriteVST4]>; } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 // Classes for VST*LN pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VSTQLNPseudo : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), itin, "">; class VSTQLNWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QPR:$src, nohash_imm:$lane), itin, "$addr.addr = $wb">; class VSTQQLNPseudo : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), itin, "">; class VSTQQLNWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, nohash_imm:$lane), itin, "$addr.addr = $wb">; class VSTQQQQLNPseudo : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), itin, "">; class VSTQQQQLNWBPseudo : PseudoNLdSt<(outs GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, nohash_imm:$lane), itin, "$addr.addr = $wb">; // VST1LN : Vector Store (single element from one lane) class VST1LN op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane), IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]>, Sched<[WriteVST1]> { let Rm = 0b1111; let DecoderMethod = "DecodeVST1LN"; } class VST1QLNPseudo : VSTQLNPseudo, Sched<[WriteVST1]> { let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), addrmode6:$addr)]; } def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8, NEONvgetlaneu, addrmode6> { let Inst{7-5} = lane{2-0}; } def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16, NEONvgetlaneu, addrmode6> { let Inst{7-6} = lane{1-0}; let Inst{4} = Rn{4}; } def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt, addrmode6oneL32> { let Inst{7} = lane{0}; let Inst{5-4} = Rn{5-4}; } def VST1LNq8Pseudo : VST1QLNPseudo; def VST1LNq16Pseudo : VST1QLNPseudo; def VST1LNq32Pseudo : VST1QLNPseudo; def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr), (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>; def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr), (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>; // ...with address register writeback: class VST1LNWB op11_8, bits<4> op7_4, string Dt, ValueType Ty, PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins AdrMode:$Rn, am6offset:$Rm, DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn$Rm", "$Rn.addr = $wb", [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AdrMode:$Rn, am6offset:$Rm))]>, Sched<[WriteVST1]> { let DecoderMethod = "DecodeVST1LN"; } class VST1QLNWBPseudo : VSTQLNWBPseudo, Sched<[WriteVST1]> { let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), addrmode6:$addr, am6offset:$offset))]; } def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8, NEONvgetlaneu, addrmode6> { let Inst{7-5} = lane{2-0}; } def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16, NEONvgetlaneu, addrmode6> { let Inst{7-6} = lane{1-0}; let Inst{4} = Rn{4}; } def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store, extractelt, addrmode6oneL32> { let Inst{7} = lane{0}; let Inst{5-4} = Rn{5-4}; } def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo; def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo; def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo; let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { // VST2LN : Vector Store (single 2-element structure from one lane) class VST2LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn", "", []>, Sched<[WriteVST1]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVST2LN"; } def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> { let Inst{7} = lane{0}; } def VST2LNd8Pseudo : VSTQLNPseudo, Sched<[WriteVST1]>; def VST2LNd16Pseudo : VSTQLNPseudo, Sched<[WriteVST1]>; def VST2LNd32Pseudo : VSTQLNPseudo, Sched<[WriteVST1]>; // ...with double-spaced registers: def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; let Inst{4} = Rn{4}; } def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> { let Inst{7} = lane{0}; let Inst{4} = Rn{4}; } def VST2LNq16Pseudo : VSTQQLNPseudo, Sched<[WriteVST1]>; def VST2LNq32Pseudo : VSTQQLNPseudo, Sched<[WriteVST1]>; // ...with address register writeback: class VST2LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVST2LN"; } def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> { let Inst{7} = lane{0}; } def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo, Sched<[WriteVST1]>; def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo, Sched<[WriteVST1]>; def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo, Sched<[WriteVST1]>; def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> { let Inst{7} = lane{0}; } def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST1]>; def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST1]>; // VST3LN : Vector Store (single 3-element structure from one lane) class VST3LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3ln, "vst3", Dt, "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>, Sched<[WriteVST2]> { let Rm = 0b1111; let DecoderMethod = "DecodeVST3LN"; } def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> { let Inst{7} = lane{0}; } def VST3LNd8Pseudo : VSTQQLNPseudo, Sched<[WriteVST2]>; def VST3LNd16Pseudo : VSTQQLNPseudo, Sched<[WriteVST2]>; def VST3LNd32Pseudo : VSTQQLNPseudo, Sched<[WriteVST2]>; // ...with double-spaced registers: def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> { let Inst{7} = lane{0}; } def VST3LNq16Pseudo : VSTQQQQLNPseudo; def VST3LNq32Pseudo : VSTQQQQLNPseudo; // ...with address register writeback: class VST3LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), IIC_VST3lnu, "vst3", Dt, "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { let DecoderMethod = "DecodeVST3LN"; } def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> { let Inst{7-5} = lane{2-0}; } def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> { let Inst{7} = lane{0}; } def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST2]>; def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST2]>; def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST2]>; def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> { let Inst{7-6} = lane{1-0}; } def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> { let Inst{7} = lane{0}; } def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo, Sched<[WriteVST2]>; def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo, Sched<[WriteVST2]>; // VST4LN : Vector Store (single 4-element structure from one lane) class VST4LN op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4ln, "vst4", Dt, "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", "", []>, Sched<[WriteVST2]> { let Rm = 0b1111; let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVST4LN"; } def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VST4LNd8Pseudo : VSTQQLNPseudo, Sched<[WriteVST2]>; def VST4LNd16Pseudo : VSTQQLNPseudo, Sched<[WriteVST2]>; def VST4LNd32Pseudo : VSTQQLNPseudo, Sched<[WriteVST2]>; // ...with double-spaced registers: def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VST4LNq16Pseudo : VSTQQQQLNPseudo, Sched<[WriteVST2]>; def VST4LNq32Pseudo : VSTQQQQLNPseudo, Sched<[WriteVST2]>; // ...with address register writeback: class VST4LNWB op11_8, bits<4> op7_4, string Dt> : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), IIC_VST4lnu, "vst4", Dt, "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { let Inst{4} = Rn{4}; let DecoderMethod = "DecodeVST4LN"; } def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> { let Inst{7-5} = lane{2-0}; } def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST2]>; def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST2]>; def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo, Sched<[WriteVST2]>; def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> { let Inst{7-6} = lane{1-0}; } def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> { let Inst{7} = lane{0}; let Inst{5} = Rn{5}; } def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo, Sched<[WriteVST2]>; def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo, Sched<[WriteVST2]>; } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 // Use vld1/vst1 for unaligned f64 load / store def : Pat<(f64 (hword_alignedload addrmode6:$addr)), (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>; def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr), (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>; def : Pat<(f64 (byte_alignedload addrmode6:$addr)), (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>; def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr), (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>; def : Pat<(f64 (non_word_alignedload addrmode6:$addr)), (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>; def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr), (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>; // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64 // load / store if it's legal. def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)), (VLD1q64 addrmode6:$addr)>; def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr), (VST1q64 addrmode6:$addr, QPR:$value)>; def : Pat<(v2f64 (word_alignedload addrmode6:$addr)), (VLD1q32 addrmode6:$addr)>, Requires<[IsLE]>; def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr), (VST1q32 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>; def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)), (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>; def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr), (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>; def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)), (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>; def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr), (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>; //===----------------------------------------------------------------------===// // NEON pattern fragments //===----------------------------------------------------------------------===// // Extract D sub-registers of Q registers. def DSubReg_i8_reg : SDNodeXFormgetTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N), MVT::i32); }]>; def DSubReg_i16_reg : SDNodeXFormgetTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N), MVT::i32); }]>; def DSubReg_i32_reg : SDNodeXFormgetTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N), MVT::i32); }]>; def DSubReg_f64_reg : SDNodeXFormgetTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N), MVT::i32); }]>; // Extract S sub-registers of Q/D registers. def SSubReg_f32_reg : SDNodeXFormgetTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N), MVT::i32); }]>; // Translate lane numbers from Q registers to D subregs. def SubReg_i8_lane : SDNodeXFormgetTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32); }]>; def SubReg_i16_lane : SDNodeXFormgetTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32); }]>; def SubReg_i32_lane : SDNodeXFormgetTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32); }]>; //===----------------------------------------------------------------------===// // Instruction Classes //===----------------------------------------------------------------------===// // Basic 2-register operations: double- and quad-register. class N2VD op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2V; class N2VQ op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> : N2V; // Basic 2-register intrinsics, both double- and quad-register. class N2VDInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2V; class N2VQInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2V; // Same as above, but not predicated. class N2VDIntnp op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2Vnp; class N2VQIntnp op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2Vnp; // Similar to NV2VQIntnp with some more encoding bits exposed (crypto). class N2VQIntXnp op19_18, bits<2> op17_16, bits<3> op10_8, bit op6, bit op7, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2Vnp; // Same as N2VQIntXnp but with Vd as a src register. class N2VQIntX2np op19_18, bits<2> op17_16, bits<3> op10_8, bit op6, bit op7, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2Vnp { let Constraints = "$src = $Vd"; } // Narrow 2-register operations. class N2VN op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ, SDNode OpNode> : N2V; // Narrow 2-register intrinsics. class N2VNInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ, SDPatternOperator IntOp> : N2V; // Long 2-register operations (currently only used for VMOVL). class N2VL op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode OpNode> : N2V; // Long 2-register intrinsics. class N2VLInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDPatternOperator IntOp> : N2V; // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. class N2VDShuffle op19_18, bits<5> op11_7, string OpcodeStr, string Dt> : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm), (ins DPR:$src1, DPR:$src2), IIC_VPERMD, OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd, $src2 = $Vm", []>; class N2VQShuffle op19_18, bits<5> op11_7, InstrItinClass itin, string OpcodeStr, string Dt> : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm), (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd, $src2 = $Vm", []>; // Basic 3-register operations: double- and quad-register. class N3VD op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> : N3V { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } // Same as N3VD but no data type. class N3VDX op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> : N3VX{ // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } class N3VDSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> : N3VLane32<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = 0; } class N3VDSL16 op21_20, bits<4> op11_8, string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> : N3VLane16<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","", [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = 0; } class N3VQ op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> : N3V { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } class N3VQX op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> : N3VX{ // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } class N3VQSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode ShOp> : N3VLane32<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (ResTy QPR:$Vd), (ResTy (ShOp (ResTy QPR:$Vn), (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), imm:$lane)))))]> { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = 0; } class N3VQSL16 op21_20, bits<4> op11_8, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDNode ShOp> : N3VLane16<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "", [(set (ResTy QPR:$Vd), (ResTy (ShOp (ResTy QPR:$Vn), (ResTy (NEONvduplane (OpTy DPR_8:$Vm), imm:$lane)))))]> { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = 0; } // Basic 3-register intrinsics, both double- and quad-register. class N3VDInt op21_20, bits<4> op11_8, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> : N3V { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } class N3VDIntnp op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> : N3Vnp; class N3VDIntSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp> : N3VLane32<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (Ty DPR:$Vd), (Ty (IntOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), imm:$lane)))))]> { let isCommutable = 0; } class N3VDIntSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp> : N3VLane16<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (Ty DPR:$Vd), (Ty (IntOp (Ty DPR:$Vn), (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { let isCommutable = 0; } class N3VDIntSh op21_20, bits<4> op11_8, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3V { let TwoOperandAliasConstraint = "$Vm = $Vd"; let isCommutable = 0; } class N3VQInt op21_20, bits<4> op11_8, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> : N3V { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } class N3VQIntnp op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> : N3Vnp; // Same as N3VQIntnp but with Vd as a src register. class N3VQInt3np op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> : N3Vnp { let Constraints = "$src = $Vd"; } class N3VQIntSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3VLane32<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (ResTy QPR:$Vd), (ResTy (IntOp (ResTy QPR:$Vn), (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), imm:$lane)))))]> { let isCommutable = 0; } class N3VQIntSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3VLane16<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [(set (ResTy QPR:$Vd), (ResTy (IntOp (ResTy QPR:$Vn), (ResTy (NEONvduplane (OpTy DPR_8:$Vm), imm:$lane)))))]> { let isCommutable = 0; } class N3VQIntSh op21_20, bits<4> op11_8, bit op4, Format f, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3V { let TwoOperandAliasConstraint = "$Vm = $Vd"; let isCommutable = 0; } // Multiply-Add/Sub operations: double- and quad-register. class N3VDMulOp op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode> : N3V; class N3VDMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp> : N3VLane32<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$src1), (Ty (MulOp DPR:$Vn, (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), imm:$lane)))))))]>; class N3VDMulOpSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp> : N3VLane16<0, 1, op21_20, op11_8, 1, 0, (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", [(set (Ty DPR:$Vd), (Ty (ShOp (Ty DPR:$src1), (Ty (MulOp DPR:$Vn, (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))))]>; class N3VQMulOp op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode> : N3V; class N3VQMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator MulOp, SDPatternOperator ShOp> : N3VLane32<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", [(set (ResTy QPR:$Vd), (ResTy (ShOp (ResTy QPR:$src1), (ResTy (MulOp QPR:$Vn, (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), imm:$lane)))))))]>; class N3VQMulOpSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator MulOp, SDPatternOperator ShOp> : N3VLane16<1, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", [(set (ResTy QPR:$Vd), (ResTy (ShOp (ResTy QPR:$src1), (ResTy (MulOp QPR:$Vn, (ResTy (NEONvduplane (OpTy DPR_8:$Vm), imm:$lane)))))))]>; // Neon Intrinsic-Op instructions (VABA): double- and quad-register. class N3VDIntOp op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp, SDNode OpNode> : N3V; class N3VQIntOp op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp, SDNode OpNode> : N3V; // Neon 3-argument intrinsics, both double- and quad-register. // The destination register is also used as the first source operand register. class N3VDInt3 op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3V; class N3VQInt3 op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3V; // Long Multiply-Add/Sub operations. class N3VLMulOp op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> : N3V; class N3VLMulOpSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> : N3VLane32; class N3VLMulOpSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> : N3VLane16; // Long Intrinsic-Op vector operations with explicit extend (VABAL). class N3VLIntExtOp op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> : N3V; // Neon Long 3-argument intrinsic. The destination register is // a quad-register and is also used as the first source operand register. class N3VLInt3 op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDPatternOperator IntOp> : N3V; class N3VLInt3SL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3VLane32; class N3VLInt3SL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3VLane16; // Narrowing 3-register intrinsics. class N3VNInt op21_20, bits<4> op11_8, bit op4, string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ, SDPatternOperator IntOp, bit Commutable> : N3V { let isCommutable = Commutable; } // Long 3-register operations. class N3VL op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable> : N3V { let isCommutable = Commutable; } class N3VLSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode OpNode> : N3VLane32; class N3VLSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode OpNode> : N3VLane16; // Long 3-register operations with explicitly extended operands. class N3VLExt op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, bit Commutable> : N3V { let isCommutable = Commutable; } // Long 3-register intrinsics with explicit extend (VABDL). class N3VLIntExt op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp, bit Commutable> : N3V { let isCommutable = Commutable; } // Long 3-register intrinsics. class N3VLInt op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable> : N3V { let isCommutable = Commutable; } // Same as above, but not predicated. class N3VLIntnp op27_23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> : N3Vnp; class N3VLIntSL op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3VLane32; class N3VLIntSL16 op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N3VLane16; // Wide 3-register operations. class N3VW op21_20, bits<4> op11_8, bit op4, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, bit Commutable> : N3V { // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd"; let isCommutable = Commutable; } // Pairwise long 2-register intrinsics, both double- and quad-register. class N2VDPLInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2V; class N2VQPLInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2V; // Pairwise long 2-register accumulate intrinsics, // both double- and quad-register. // The destination register is also used as the first source operand register. class N2VDPLInt2 op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2V; class N2VQPLInt2 op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2V; // Shift by immediate, // both double- and quad-register. let TwoOperandAliasConstraint = "$Vm = $Vd" in { class N2VDSh op11_8, bit op7, bit op4, Format f, InstrItinClass itin, Operand ImmTy, string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode> : N2VImm; class N2VQSh op11_8, bit op7, bit op4, Format f, InstrItinClass itin, Operand ImmTy, string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode> : N2VImm; } // Long shift by immediate. class N2VLSh op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, Operand ImmTy, SDPatternOperator OpNode> : N2VImm; // Narrow shift by immediate. class N2VNSh op11_8, bit op7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, Operand ImmTy, SDPatternOperator OpNode> : N2VImm; // Shift right by immediate and accumulate, // both double- and quad-register. let TwoOperandAliasConstraint = "$Vm = $Vd" in { class N2VDShAdd op11_8, bit op7, bit op4, Operand ImmTy, string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> : N2VImm; class N2VQShAdd op11_8, bit op7, bit op4, Operand ImmTy, string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> : N2VImm; } // Shift by immediate and insert, // both double- and quad-register. let TwoOperandAliasConstraint = "$Vm = $Vd" in { class N2VDShIns op11_8, bit op7, bit op4, Operand ImmTy, Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp> : N2VImm; class N2VQShIns op11_8, bit op7, bit op4, Operand ImmTy, Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp> : N2VImm; } // Convert, with fractional bits immediate, // both double- and quad-register. class N2VCvtD op11_8, bit op7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2VImm; class N2VCvtQ op11_8, bit op7, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> : N2VImm; //===----------------------------------------------------------------------===// // Multiclasses //===----------------------------------------------------------------------===// // Abbreviations used in multiclass suffixes: // Q = quarter int (8 bit) elements // H = half int (16 bit) elements // S = single int (32 bit) elements // D = double int (64 bit) elements // Neon 2-register vector operations and intrinsics. // Neon 2-register comparisons. // source operand element sizes of 8, 16 and 32 bits: multiclass N2V_QHS_cmp op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op4, string opc, string Dt, string asm, SDNode OpNode> { // 64-bit vector types. def v8i8 : N2V; def v4i16 : N2V; def v2i32 : N2V; def v2f32 : N2V { let Inst{10} = 1; // overwrite F = 1 } def v4f16 : N2V, Requires<[HasNEON,HasFullFP16]> { let Inst{10} = 1; // overwrite F = 1 } // 128-bit vector types. def v16i8 : N2V; def v8i16 : N2V; def v4i32 : N2V; def v4f32 : N2V { let Inst{10} = 1; // overwrite F = 1 } def v8f16 : N2V, Requires<[HasNEON,HasFullFP16]> { let Inst{10} = 1; // overwrite F = 1 } } // Neon 2-register vector intrinsics, // element sizes of 8, 16 and 32 bits: multiclass N2VInt_QHS op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op4, InstrItinClass itinD, InstrItinClass itinQ, string OpcodeStr, string Dt, SDPatternOperator IntOp> { // 64-bit vector types. def v8i8 : N2VDInt; def v4i16 : N2VDInt; def v2i32 : N2VDInt; // 128-bit vector types. def v16i8 : N2VQInt; def v8i16 : N2VQInt; def v4i32 : N2VQInt; } // Neon Narrowing 2-register vector operations, // source operand element sizes of 16, 32 and 64 bits: multiclass N2VN_HSD op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, SDNode OpNode> { def v8i8 : N2VN; def v4i16 : N2VN; def v2i32 : N2VN; } // Neon Narrowing 2-register vector intrinsics, // source operand element sizes of 16, 32 and 64 bits: multiclass N2VNInt_HSD op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, SDPatternOperator IntOp> { def v8i8 : N2VNInt; def v4i16 : N2VNInt; def v2i32 : N2VNInt; } // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). // source operand element sizes of 16, 32 and 64 bits: multiclass N2VL_QHS op24_23, bits<5> op11_7, bit op6, bit op4, string OpcodeStr, string Dt, SDNode OpNode> { def v8i16 : N2VL; def v4i32 : N2VL; def v2i64 : N2VL; } // Neon 3-register vector operations. // First with only element sizes of 8, 16 and 32 bits: multiclass N3V_QHS op11_8, bit op4, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDNode OpNode, bit Commutable = 0> { // 64-bit vector types. def v8i8 : N3VD; def v4i16 : N3VD; def v2i32 : N3VD; // 128-bit vector types. def v16i8 : N3VQ; def v8i16 : N3VQ; def v4i32 : N3VQ; } multiclass N3VSL_HS op11_8, string OpcodeStr, SDNode ShOp> { def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>; def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>; def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>; def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32", v4i32, v2i32, ShOp>; } // ....then also with element size 64 bits: multiclass N3V_QHSD op11_8, bit op4, InstrItinClass itinD, InstrItinClass itinQ, string OpcodeStr, string Dt, SDNode OpNode, bit Commutable = 0> : N3V_QHS { def v1i64 : N3VD; def v2i64 : N3VQ; } // Neon 3-register vector intrinsics. // First with only element sizes of 16 and 32 bits: multiclass N3VInt_HS op11_8, bit op4, Format f, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp, bit Commutable = 0> { // 64-bit vector types. def v4i16 : N3VDInt; def v2i32 : N3VDInt; // 128-bit vector types. def v8i16 : N3VQInt; def v4i32 : N3VQInt; } multiclass N3VInt_HSSh op11_8, bit op4, Format f, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp> { // 64-bit vector types. def v4i16 : N3VDIntSh; def v2i32 : N3VDIntSh; // 128-bit vector types. def v8i16 : N3VQIntSh; def v4i32 : N3VQIntSh; } multiclass N3VIntSL_HS op11_8, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp> { def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>; def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>; def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>; def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>; } // ....then also with element size of 8 bits: multiclass N3VInt_QHS op11_8, bit op4, Format f, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp, bit Commutable = 0> : N3VInt_HS { def v8i8 : N3VDInt; def v16i8 : N3VQInt; } multiclass N3VInt_QHSSh op11_8, bit op4, Format f, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp> : N3VInt_HSSh { def v8i8 : N3VDIntSh; def v16i8 : N3VQIntSh; } // ....then also with element size of 64 bits: multiclass N3VInt_QHSD op11_8, bit op4, Format f, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp, bit Commutable = 0> : N3VInt_QHS { def v1i64 : N3VDInt; def v2i64 : N3VQInt; } multiclass N3VInt_QHSDSh op11_8, bit op4, Format f, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp> : N3VInt_QHSSh { def v1i64 : N3VDIntSh; def v2i64 : N3VQIntSh; } // Neon Narrowing 3-register vector intrinsics, // source operand element sizes of 16, 32 and 64 bits: multiclass N3VNInt_HSD op11_8, bit op4, string OpcodeStr, string Dt, SDPatternOperator IntOp, bit Commutable = 0> { def v8i8 : N3VNInt; def v4i16 : N3VNInt; def v2i32 : N3VNInt; } // Neon Long 3-register vector operations. multiclass N3VL_QHS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDNode OpNode, bit Commutable = 0> { def v8i16 : N3VL; def v4i32 : N3VL; def v2i64 : N3VL; } multiclass N3VLSL_HS op11_8, InstrItinClass itin, string OpcodeStr, string Dt, SDNode OpNode> { def v4i16 : N3VLSL16; def v2i32 : N3VLSL; } multiclass N3VLExt_QHS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { def v8i16 : N3VLExt; def v4i32 : N3VLExt; def v2i64 : N3VLExt; } // Neon Long 3-register vector intrinsics. // First with only element sizes of 16 and 32 bits: multiclass N3VLInt_HS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDPatternOperator IntOp, bit Commutable = 0> { def v4i32 : N3VLInt; def v2i64 : N3VLInt; } multiclass N3VLIntSL_HS op11_8, InstrItinClass itin, string OpcodeStr, string Dt, SDPatternOperator IntOp> { def v4i16 : N3VLIntSL16; def v2i32 : N3VLIntSL; } // ....then also with element size of 8 bits: multiclass N3VLInt_QHS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDPatternOperator IntOp, bit Commutable = 0> : N3VLInt_HS { def v8i16 : N3VLInt; } // ....with explicit extend (VABDL). multiclass N3VLIntExt_QHS op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> { def v8i16 : N3VLIntExt; def v4i32 : N3VLIntExt; def v2i64 : N3VLIntExt; } // Neon Wide 3-register vector intrinsics, // source operand element sizes of 8, 16 and 32 bits: multiclass N3VW_QHS op11_8, bit op4, string OpcodeStr, string Dt, SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { def v8i16 : N3VW; def v4i32 : N3VW; def v2i64 : N3VW; } // Neon Multiply-Op vector operations, // element sizes of 8, 16 and 32 bits: multiclass N3VMulOp_QHS op11_8, bit op4, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDNode OpNode> { // 64-bit vector types. def v8i8 : N3VDMulOp; def v4i16 : N3VDMulOp; def v2i32 : N3VDMulOp; // 128-bit vector types. def v16i8 : N3VQMulOp; def v8i16 : N3VQMulOp; def v4i32 : N3VQMulOp; } multiclass N3VMulOpSL_HS op11_8, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator ShOp> { def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16, OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>; def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32, OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>; def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16, OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, mul, ShOp>; def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32, OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, mul, ShOp>; } // Neon Intrinsic-Op vector operations, // element sizes of 8, 16 and 32 bits: multiclass N3VIntOp_QHS op11_8, bit op4, InstrItinClass itinD, InstrItinClass itinQ, string OpcodeStr, string Dt, SDPatternOperator IntOp, SDNode OpNode> { // 64-bit vector types. def v8i8 : N3VDIntOp; def v4i16 : N3VDIntOp; def v2i32 : N3VDIntOp; // 128-bit vector types. def v16i8 : N3VQIntOp; def v8i16 : N3VQIntOp; def v4i32 : N3VQIntOp; } // Neon 3-argument intrinsics, // element sizes of 16 and 32 bits: multiclass N3VInt3_HS op11_8, bit op4, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp> { // 64-bit vector types. def v4i16 : N3VDInt3; def v2i32 : N3VDInt3; // 128-bit vector types. def v8i16 : N3VQInt3; def v4i32 : N3VQInt3; } // element sizes of 8, 16 and 32 bits: multiclass N3VInt3_QHS op11_8, bit op4, InstrItinClass itinD16, InstrItinClass itinD32, InstrItinClass itinQ16, InstrItinClass itinQ32, string OpcodeStr, string Dt, SDPatternOperator IntOp> :N3VInt3_HS { // 64-bit vector types. def v8i8 : N3VDInt3; // 128-bit vector types. def v16i8 : N3VQInt3; } // Neon Long Multiply-Op vector operations, // element sizes of 8, 16 and 32 bits: multiclass N3VLMulOp_QHS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDNode MulOp, SDNode OpNode> { def v8i16 : N3VLMulOp; def v4i32 : N3VLMulOp; def v2i64 : N3VLMulOp; } multiclass N3VLMulOpSL_HS op11_8, string OpcodeStr, string Dt, SDNode MulOp, SDNode OpNode> { def v4i16 : N3VLMulOpSL16; def v2i32 : N3VLMulOpSL; } // Neon Long 3-argument intrinsics. // First with only element sizes of 16 and 32 bits: multiclass N3VLInt3_HS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDPatternOperator IntOp> { def v4i32 : N3VLInt3; def v2i64 : N3VLInt3; } multiclass N3VLInt3SL_HS op11_8, string OpcodeStr, string Dt, SDPatternOperator IntOp> { def v4i16 : N3VLInt3SL16; def v2i32 : N3VLInt3SL; } // ....then also with element size of 8 bits: multiclass N3VLInt3_QHS op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, SDPatternOperator IntOp> : N3VLInt3_HS { def v8i16 : N3VLInt3; } // ....with explicit extend (VABAL). multiclass N3VLIntExtOp_QHS op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> { def v8i16 : N3VLIntExtOp; def v4i32 : N3VLIntExtOp; def v2i64 : N3VLIntExtOp; } // Neon Pairwise long 2-register intrinsics, // element sizes of 8, 16 and 32 bits: multiclass N2VPLInt_QHS op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, SDPatternOperator IntOp> { // 64-bit vector types. def v8i8 : N2VDPLInt; def v4i16 : N2VDPLInt; def v2i32 : N2VDPLInt; // 128-bit vector types. def v16i8 : N2VQPLInt; def v8i16 : N2VQPLInt; def v4i32 : N2VQPLInt; } // Neon Pairwise long 2-register accumulate intrinsics, // element sizes of 8, 16 and 32 bits: multiclass N2VPLInt2_QHS op24_23, bits<2> op21_20, bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, string Dt, SDPatternOperator IntOp> { // 64-bit vector types. def v8i8 : N2VDPLInt2; def v4i16 : N2VDPLInt2; def v2i32 : N2VDPLInt2; // 128-bit vector types. def v16i8 : N2VQPLInt2; def v8i16 : N2VQPLInt2; def v4i32 : N2VQPLInt2; } // Neon 2-register vector shift by immediate, // with f of either N2RegVShLFrm or N2RegVShRFrm // element sizes of 8, 16, 32 and 64 bits: multiclass N2VShL_QHSD op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, SDNode OpNode> { // 64-bit vector types. def v8i8 : N2VDSh { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VDSh { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VDSh { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v1i64 : N2VDSh; // imm6 = xxxxxx // 128-bit vector types. def v16i8 : N2VQSh { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v8i16 : N2VQSh { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v4i32 : N2VQSh { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v2i64 : N2VQSh; // imm6 = xxxxxx } multiclass N2VShR_QHSD op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, string baseOpc, SDNode OpNode> { // 64-bit vector types. def v8i8 : N2VDSh { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VDSh { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VDSh { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v1i64 : N2VDSh; // imm6 = xxxxxx // 128-bit vector types. def v16i8 : N2VQSh { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v8i16 : N2VQSh { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v4i32 : N2VQSh { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v2i64 : N2VQSh; // imm6 = xxxxxx } // Neon Shift-Accumulate vector operations, // element sizes of 8, 16, 32 and 64 bits: multiclass N2VShAdd_QHSD op11_8, bit op4, string OpcodeStr, string Dt, SDNode ShOp> { // 64-bit vector types. def v8i8 : N2VDShAdd { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VDShAdd { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VDShAdd { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v1i64 : N2VDShAdd; // imm6 = xxxxxx // 128-bit vector types. def v16i8 : N2VQShAdd { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v8i16 : N2VQShAdd { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v4i32 : N2VQShAdd { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v2i64 : N2VQShAdd; // imm6 = xxxxxx } // Neon Shift-Insert vector operations, // with f of either N2RegVShLFrm or N2RegVShRFrm // element sizes of 8, 16, 32 and 64 bits: multiclass N2VShInsL_QHSD op11_8, bit op4, string OpcodeStr> { // 64-bit vector types. def v8i8 : N2VDShIns { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VDShIns { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VDShIns { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v1i64 : N2VDShIns; // imm6 = xxxxxx // 128-bit vector types. def v16i8 : N2VQShIns { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v8i16 : N2VQShIns { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v4i32 : N2VQShIns { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v2i64 : N2VQShIns; // imm6 = xxxxxx } multiclass N2VShInsR_QHSD op11_8, bit op4, string OpcodeStr> { // 64-bit vector types. def v8i8 : N2VDShIns { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VDShIns { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VDShIns { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v1i64 : N2VDShIns; // imm6 = xxxxxx // 128-bit vector types. def v16i8 : N2VQShIns { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v8i16 : N2VQShIns { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v4i32 : N2VQShIns { let Inst{21} = 0b1; // imm6 = 1xxxxx } def v2i64 : N2VQShIns; // imm6 = xxxxxx } // Neon Shift Long operations, // element sizes of 8, 16, 32 bits: multiclass N2VLSh_QHS op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, SDPatternOperator OpNode> { def v8i16 : N2VLSh { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i32 : N2VLSh { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i64 : N2VLSh { let Inst{21} = 0b1; // imm6 = 1xxxxx } } // Neon Shift Narrow operations, // element sizes of 16, 32, 64 bits: multiclass N2VNSh_HSD op11_8, bit op7, bit op6, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, SDPatternOperator OpNode> { def v8i8 : N2VNSh { let Inst{21-19} = 0b001; // imm6 = 001xxx } def v4i16 : N2VNSh { let Inst{21-20} = 0b01; // imm6 = 01xxxx } def v2i32 : N2VNSh { let Inst{21} = 0b1; // imm6 = 1xxxxx } } //===----------------------------------------------------------------------===// // Instruction Definitions. //===----------------------------------------------------------------------===// // Vector Add Operations. // VADD : Vector Add (integer and floating-point) defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i", add, 1>; def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32", v2f32, v2f32, fadd, 1>; def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32", v4f32, v4f32, fadd, 1>; def VADDhd : N3VD<0, 0, 0b01, 0b1101, 0, IIC_VBIND, "vadd", "f16", v4f16, v4f16, fadd, 1>, Requires<[HasNEON,HasFullFP16]>; def VADDhq : N3VQ<0, 0, 0b01, 0b1101, 0, IIC_VBINQ, "vadd", "f16", v8f16, v8f16, fadd, 1>, Requires<[HasNEON,HasFullFP16]>; // VADDL : Vector Add Long (Q = D + D) defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, "vaddl", "s", add, sext, 1>; defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, "vaddl", "u", add, zext, 1>; // VADDW : Vector Add Wide (Q = Q + D) defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>; defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>; // VHADD : Vector Halving Add defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vhadd", "s", int_arm_neon_vhadds, 1>; defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vhadd", "u", int_arm_neon_vhaddu, 1>; // VRHADD : Vector Rounding Halving Add defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vrhadd", "s", int_arm_neon_vrhadds, 1>; defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vrhadd", "u", int_arm_neon_vrhaddu, 1>; // VQADD : Vector Saturating Add defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vqadd", "s", int_arm_neon_vqadds, 1>; defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vqadd", "u", int_arm_neon_vqaddu, 1>; // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>; // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i", int_arm_neon_vraddhn, 1>; def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))), (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>; def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))), (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>; def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))), (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>; // Vector Multiply Operations. // VMUL : Vector Multiply (integer, polynomial and floating-point) defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>; def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul", "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>; def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul", "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>; def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32", v2f32, v2f32, fmul, 1>; def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32", v4f32, v4f32, fmul, 1>; def VMULhd : N3VD<1, 0, 0b01, 0b1101, 1, IIC_VFMULD, "vmul", "f16", v4f16, v4f16, fmul, 1>, Requires<[HasNEON,HasFullFP16]>; def VMULhq : N3VQ<1, 0, 0b01, 0b1101, 1, IIC_VFMULQ, "vmul", "f16", v8f16, v8f16, fmul, 1>, Requires<[HasNEON,HasFullFP16]>; defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>; def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>; def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, v2f32, fmul>; def VMULslhd : N3VDSL16<0b01, 0b1001, "vmul", "f16", v4f16, fmul>, Requires<[HasNEON,HasFullFP16]>; def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16, v4f16, fmul>, Requires<[HasNEON,HasFullFP16]>; def : Pat<(v8i16 (mul (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (mul (v4i32 QPR:$src1), (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), (v4i32 (VMULslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v4f32 (fmul (v4f32 QPR:$src1), (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))), (v4f32 (VMULslfq (v4f32 QPR:$src1), (v2f32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))), (VMULslfd DPR:$Rn, (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), (i32 0))>; def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))), (VMULslfq QPR:$Rn, (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0), (i32 0))>; // VQDMULH : Vector Saturating Doubling Multiply Returning High Half defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, IIC_VMULi32Q, "vqdmulh", "s", int_arm_neon_vqdmulh, 1>; defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, IIC_VMULi32Q, "vqdmulh", "s", int_arm_neon_vqdmulh>; def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q, "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>; defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D, IIC_VMULi16Q, IIC_VMULi32Q, "vqrdmulh", "s", int_arm_neon_vqrdmulh>; def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), (v4i16 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), (v2i32 (EXTRACT_SUBREG QPR:$src2, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) let PostEncoderMethod = "NEONThumb2DataIPostEncoder", DecoderNamespace = "NEONData" in { defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, "vmull", "s", NEONvmulls, 1>; defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, "vmull", "u", NEONvmullu, 1>; def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", v8i16, v8i8, int_arm_neon_vmullp, 1>; def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary, "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>, Requires<[HasV8, HasCrypto]>; } defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>; defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>; // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D, "vqdmull", "s", int_arm_neon_vqdmull, 1>; defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, "vqdmull", "s", int_arm_neon_vqdmull>; // Vector Multiply-Accumulate and Multiply-Subtract Operations. // VMLA : Vector Multiply Accumulate (integer and floating-point) defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>; def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32", v2f32, fmul_su, fadd_mlx>, Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32", v4f32, fmul_su, fadd_mlx>, Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; def VMLAhd : N3VDMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACD, "vmla", "f16", v4f16, fmul_su, fadd_mlx>, Requires<[HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC]>; def VMLAhq : N3VQMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACQ, "vmla", "f16", v8f16, fmul_su, fadd_mlx>, Requires<[HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC]>; defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>; def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32", v2f32, fmul_su, fadd_mlx>, Requires<[HasNEON, UseFPVMLx]>; def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32", v4f32, v2f32, fmul_su, fadd_mlx>, Requires<[HasNEON, UseFPVMLx]>; def VMLAslhd : N3VDMulOpSL16<0b01, 0b0001, IIC_VMACD, "vmla", "f16", v4f16, fmul, fadd>, Requires<[HasNEON, HasFullFP16, UseFPVMLx]>; def VMLAslhq : N3VQMulOpSL16<0b01, 0b0001, IIC_VMACQ, "vmla", "f16", v8f16, v4f16, fmul, fadd>, Requires<[HasNEON, HasFullFP16, UseFPVMLx]>; def : Pat<(v8i16 (add (v8i16 QPR:$src1), (mul (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (add (v4i32 QPR:$src1), (mul (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1), (fmul_su (v4f32 QPR:$src2), (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), (v4f32 (VMLAslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), (v2f32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>, Requires<[HasNEON, UseFPVMLx]>; // VMLAL : Vector Multiply Accumulate Long (Q += D * D) defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, "vmlal", "s", NEONvmulls, add>; defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, "vmlal", "u", NEONvmullu, add>; defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>; defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>; let Predicates = [HasNEON, HasV8_1a] in { // v8.1a Neon Rounding Double Multiply-Op vector operations, // VQRDMLAH : Vector Saturating Rounding Doubling Multiply Accumulate Long // (Q += D * D) defm VQRDMLAH : N3VInt3_HS<1, 0, 0b1011, 1, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlah", "s", null_frag>; def : Pat<(v4i16 (int_arm_neon_vqadds (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))), (v4i16 (VQRDMLAHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))>; def : Pat<(v2i32 (int_arm_neon_vqadds (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))), (v2i32 (VQRDMLAHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))>; def : Pat<(v8i16 (int_arm_neon_vqadds (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))), (v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>; def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))), (v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>; defm VQRDMLAHsl : N3VMulOpSL_HS<0b1110, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlah", "s", null_frag>; def : Pat<(v4i16 (int_arm_neon_vqadds (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))), (v4i16 (VQRDMLAHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>; def : Pat<(v2i32 (int_arm_neon_vqadds (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))), (v2i32 (VQRDMLAHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane))>; def : Pat<(v8i16 (int_arm_neon_vqadds (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane)))))), (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane)))))), (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; // VQRDMLSH : Vector Saturating Rounding Doubling Multiply Subtract Long // (Q -= D * D) defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlsh", "s", null_frag>; def : Pat<(v4i16 (int_arm_neon_vqsubs (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))), (v4i16 (VQRDMLSHv4i16 DPR:$src1, DPR:$Vn, DPR:$Vm))>; def : Pat<(v2i32 (int_arm_neon_vqsubs (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))), (v2i32 (VQRDMLSHv2i32 DPR:$src1, DPR:$Vn, DPR:$Vm))>; def : Pat<(v8i16 (int_arm_neon_vqsubs (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))))), (v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>; def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))))), (v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>; defm VQRDMLSHsl : N3VMulOpSL_HS<0b1111, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vqrdmlsh", "s", null_frag>; def : Pat<(v4i16 (int_arm_neon_vqsubs (v4i16 DPR:$src1), (v4i16 (int_arm_neon_vqrdmulh (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))), (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>; def : Pat<(v2i32 (int_arm_neon_vqsubs (v2i32 DPR:$src1), (v2i32 (int_arm_neon_vqrdmulh (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))), (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane))>; def : Pat<(v8i16 (int_arm_neon_vqsubs (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane)))))), (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane)))))), (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; } // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, "vqdmlal", "s", null_frag>; defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>; def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))), (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>; def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))), (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>; def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))), (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>; def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))), (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>; // VMLS : Vector Multiply Subtract (integer and floating-point) defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>; def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32", v2f32, fmul_su, fsub_mlx>, Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32", v4f32, fmul_su, fsub_mlx>, Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; def VMLShd : N3VDMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACD, "vmls", "f16", v4f16, fmul, fsub>, Requires<[HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC]>; def VMLShq : N3VQMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACQ, "vmls", "f16", v8f16, fmul, fsub>, Requires<[HasNEON, HasFullFP16, UseFPVMLx, DontUseFusedMAC]>; defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D, IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>; def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32", v2f32, fmul_su, fsub_mlx>, Requires<[HasNEON, UseFPVMLx]>; def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32", v4f32, v2f32, fmul_su, fsub_mlx>, Requires<[HasNEON, UseFPVMLx]>; def VMLSslhd : N3VDMulOpSL16<0b01, 0b0101, IIC_VMACD, "vmls", "f16", v4f16, fmul, fsub>, Requires<[HasNEON, HasFullFP16, UseFPVMLx]>; def VMLSslhq : N3VQMulOpSL16<0b01, 0b0101, IIC_VMACQ, "vmls", "f16", v8f16, v4f16, fmul, fsub>, Requires<[HasNEON, HasFullFP16, UseFPVMLx]>; def : Pat<(v8i16 (sub (v8i16 QPR:$src1), (mul (v8i16 QPR:$src2), (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (sub (v4i32 QPR:$src1), (mul (v4i32 QPR:$src2), (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1), (fmul_su (v4f32 QPR:$src2), (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), (v2f32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>, Requires<[HasNEON, UseFPVMLx]>; // VMLSL : Vector Multiply Subtract Long (Q -= D * D) defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, "vmlsl", "s", NEONvmulls, sub>; defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, "vmlsl", "u", NEONvmullu, sub>; defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>; defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>; // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D, "vqdmlsl", "s", null_frag>; defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b0111, "vqdmlsl", "s", null_frag>; def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))))), (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>; def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))))), (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>; def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1), (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn), (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm), imm:$lane)))))), (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>; def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1), (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))), (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>; // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations. def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32", v2f32, fmul_su, fadd_mlx>, Requires<[HasNEON,HasVFP4,UseFusedMAC]>; def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32", v4f32, fmul_su, fadd_mlx>, Requires<[HasNEON,HasVFP4,UseFusedMAC]>; def VFMAhd : N3VDMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACD, "vfma", "f16", v4f16, fmul, fadd>, Requires<[HasNEON,HasFullFP16,UseFusedMAC]>; def VFMAhq : N3VQMulOp<0, 0, 0b01, 0b1100, 1, IIC_VFMACQ, "vfma", "f16", v8f16, fmul, fadd>, Requires<[HasNEON,HasFullFP16,UseFusedMAC]>; // Fused Vector Multiply Subtract (floating-point) def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32", v2f32, fmul_su, fsub_mlx>, Requires<[HasNEON,HasVFP4,UseFusedMAC]>; def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32", v4f32, fmul_su, fsub_mlx>, Requires<[HasNEON,HasVFP4,UseFusedMAC]>; def VFMShd : N3VDMulOp<0, 0, 0b11, 0b1100, 1, IIC_VFMACD, "vfms", "f16", v4f16, fmul, fsub>, Requires<[HasNEON,HasFullFP16,UseFusedMAC]>; def VFMShq : N3VQMulOp<0, 0, 0b11, 0b1100, 1, IIC_VFMACQ, "vfms", "f16", v8f16, fmul, fsub>, Requires<[HasNEON,HasFullFP16,UseFusedMAC]>; // Match @llvm.fma.* intrinsics def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)), (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasVFP4]>; def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)), (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasVFP4]>; def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)), (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasVFP4]>; def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)), (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasVFP4]>; // ARMv8.2a dot product instructions. // We put them in the VFPV8 decoder namespace because the ARM and Thumb // encodings are the same and thus no further bit twiddling is necessary // in the disassembler. class VDOT : N3Vnp<0b11000, 0b10, 0b1101, op6, op4, (outs RegTy:$dst), (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD, Asm, AsmTy, [(set (AccumTy RegTy:$dst), (OpNode (AccumTy RegTy:$Vd), (InputTy RegTy:$Vn), (InputTy RegTy:$Vm)))]> { let Predicates = [HasDotProd]; let DecoderNamespace = "VFPV8"; let Constraints = "$dst = $Vd"; } def VUDOTD : VDOT<0, 1, DPR, "vudot", "u8", v2i32, v8i8, int_arm_neon_udot>; def VSDOTD : VDOT<0, 0, DPR, "vsdot", "s8", v2i32, v8i8, int_arm_neon_sdot>; def VUDOTQ : VDOT<1, 1, QPR, "vudot", "u8", v4i32, v16i8, int_arm_neon_udot>; def VSDOTQ : VDOT<1, 0, QPR, "vsdot", "s8", v4i32, v16i8, int_arm_neon_sdot>; // Indexed dot product instructions: multiclass DOTI { def "" : N3Vnp<0b11100, 0b10, 0b1101, Q, U, (outs Ty:$dst), (ins Ty:$Vd, Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm, IIC_VDOTPROD, opc, dt, []> { bit lane; let Inst{5} = lane; let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane"); let Constraints = "$dst = $Vd"; let Predicates = [HasDotProd]; let DecoderNamespace = "VFPV8"; } def : Pat< (AccumType (OpNode (AccumType Ty:$Vd), (InputType Ty:$Vn), (InputType (bitconvert (AccumType (NEONvduplane (AccumType Ty:$Vm), VectorIndex32:$lane)))))), (!cast(NAME) Ty:$Vd, Ty:$Vn, RHS, VectorIndex32:$lane)>; } defm VUDOTDI : DOTI<"vudot", "u8", 0b0, 0b1, DPR, v2i32, v8i8, int_arm_neon_udot, (v2i32 DPR_VFP2:$Vm)>; defm VSDOTDI : DOTI<"vsdot", "s8", 0b0, 0b0, DPR, v2i32, v8i8, int_arm_neon_sdot, (v2i32 DPR_VFP2:$Vm)>; defm VUDOTQI : DOTI<"vudot", "u8", 0b1, 0b1, QPR, v4i32, v16i8, int_arm_neon_udot, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>; defm VSDOTQI : DOTI<"vsdot", "s8", 0b1, 0b0, QPR, v4i32, v16i8, int_arm_neon_sdot, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>; // ARMv8.3 complex operations class BaseN3VCP8ComplexTied pattern> : N3VCP8<{?,?}, {op21,s}, q, op4, oops, iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "$src1 = $Vd", pattern>{ bits<2> rot; let Inst{24-23} = rot; } class BaseN3VCP8ComplexOdd pattern> : N3VCP8<{?,op23}, {op21,s}, q, op4, oops, iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "", pattern> { bits<1> rot; let Inst{24} = rot; } class BaseN3VCP8ComplexTiedLane32 pattern> : N3VLaneCP8 { bits<2> rot; bit lane; let Inst{21-20} = rot; let Inst{5} = lane; } class BaseN3VCP8ComplexTiedLane64 pattern> : N3VLaneCP8 { bits<2> rot; bit lane; let Inst{21-20} = rot; let Inst{5} = Vm{4}; // This is needed because the lane operand does not have any bits in the // encoding (it only has one possible value), so we need to manually set it // to it's default value. let DecoderMethod = "DecodeNEONComplexLane64Instruction"; } multiclass N3VCP8ComplexTied { let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in { def v4f16 : BaseN3VCP8ComplexTied; def v8f16 : BaseN3VCP8ComplexTied; } let Predicates = [HasNEON,HasV8_3a] in { def v2f32 : BaseN3VCP8ComplexTied; def v4f32 : BaseN3VCP8ComplexTied; } } multiclass N3VCP8ComplexOdd { let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in { def v4f16 : BaseN3VCP8ComplexOdd; def v8f16 : BaseN3VCP8ComplexOdd; } let Predicates = [HasNEON,HasV8_3a] in { def v2f32 : BaseN3VCP8ComplexOdd; def v4f32 : BaseN3VCP8ComplexOdd; } } // These instructions index by pairs of lanes, so the VectorIndexes are twice // as wide as the data types. multiclass N3VCP8ComplexTiedLane { let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in { def v4f16_indexed : BaseN3VCP8ComplexTiedLane32; def v8f16_indexed : BaseN3VCP8ComplexTiedLane32; } let Predicates = [HasNEON,HasV8_3a] in { def v2f32_indexed : BaseN3VCP8ComplexTiedLane64; def v4f32_indexed : BaseN3VCP8ComplexTiedLane64; } } defm VCMLA : N3VCP8ComplexTied<1, 0, "vcmla", null_frag>; defm VCADD : N3VCP8ComplexOdd<1, 0, 0, "vcadd", null_frag>; defm VCMLA : N3VCP8ComplexTiedLane<0, "vcmla", null_frag>; // Vector Subtract Operations. // VSUB : Vector Subtract (integer and floating-point) defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, "vsub", "i", sub, 0>; def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32", v2f32, v2f32, fsub, 0>; def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", v4f32, v4f32, fsub, 0>; def VSUBhd : N3VD<0, 0, 0b11, 0b1101, 0, IIC_VBIND, "vsub", "f16", v4f16, v4f16, fsub, 0>, Requires<[HasNEON,HasFullFP16]>; def VSUBhq : N3VQ<0, 0, 0b11, 0b1101, 0, IIC_VBINQ, "vsub", "f16", v8f16, v8f16, fsub, 0>, Requires<[HasNEON,HasFullFP16]>; // VSUBL : Vector Subtract Long (Q = D - D) defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, "vsubl", "s", sub, sext, 0>; defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, "vsubl", "u", sub, zext, 0>; // VSUBW : Vector Subtract Wide (Q = Q - D) defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>; defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>; // VHSUB : Vector Halving Subtract defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vhsub", "s", int_arm_neon_vhsubs, 0>; defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vhsub", "u", int_arm_neon_vhsubu, 0>; // VQSUB : Vector Saturing Subtract defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vqsub", "s", int_arm_neon_vqsubs, 0>; defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vqsub", "u", int_arm_neon_vqsubu, 0>; // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>; // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i", int_arm_neon_vrsubhn, 0>; def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))), (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>; def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))), (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>; def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))), (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>; // Vector Comparisons. // VCEQ : Vector Compare Equal defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>; def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32, NEONvceq, 1>; def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, NEONvceq, 1>; def VCEQhd : N3VD<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16, NEONvceq, 1>, Requires<[HasNEON, HasFullFP16]>; def VCEQhq : N3VQ<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16, NEONvceq, 1>, Requires<[HasNEON, HasFullFP16]>; let TwoOperandAliasConstraint = "$Vm = $Vd" in defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i", "$Vd, $Vm, #0", NEONvceqz>; // VCGE : Vector Compare Greater Than or Equal defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>; defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>; def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32, NEONvcge, 0>; def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32, NEONvcge, 0>; def VCGEhd : N3VD<1,0,0b01,0b1110,0, IIC_VBIND, "vcge", "f16", v4i16, v4f16, NEONvcge, 0>, Requires<[HasNEON, HasFullFP16]>; def VCGEhq : N3VQ<1,0,0b01,0b1110,0, IIC_VBINQ, "vcge", "f16", v8i16, v8f16, NEONvcge, 0>, Requires<[HasNEON, HasFullFP16]>; let TwoOperandAliasConstraint = "$Vm = $Vd" in { defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s", "$Vd, $Vm, #0", NEONvcgez>; defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s", "$Vd, $Vm, #0", NEONvclez>; } // VCGT : Vector Compare Greater Than defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>; defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>; def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32, NEONvcgt, 0>; def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32, NEONvcgt, 0>; def VCGThd : N3VD<1,0,0b11,0b1110,0, IIC_VBIND, "vcgt", "f16", v4i16, v4f16, NEONvcgt, 0>, Requires<[HasNEON, HasFullFP16]>; def VCGThq : N3VQ<1,0,0b11,0b1110,0, IIC_VBINQ, "vcgt", "f16", v8i16, v8f16, NEONvcgt, 0>, Requires<[HasNEON, HasFullFP16]>; let TwoOperandAliasConstraint = "$Vm = $Vd" in { defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s", "$Vd, $Vm, #0", NEONvcgtz>; defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s", "$Vd, $Vm, #0", NEONvcltz>; } // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) def VACGEfd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge", "f32", v2i32, v2f32, int_arm_neon_vacge, 0>; def VACGEfq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge", "f32", v4i32, v4f32, int_arm_neon_vacge, 0>; def VACGEhd : N3VDInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge", "f16", v4i16, v4f16, int_arm_neon_vacge, 0>, Requires<[HasNEON, HasFullFP16]>; def VACGEhq : N3VQInt<1, 0, 0b01, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge", "f16", v8i16, v8f16, int_arm_neon_vacge, 0>, Requires<[HasNEON, HasFullFP16]>; // VACGT : Vector Absolute Compare Greater Than (aka VCAGT) def VACGTfd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt", "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>; def VACGTfq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt", "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>; def VACGThd : N3VDInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt", "f16", v4i16, v4f16, int_arm_neon_vacgt, 0>, Requires<[HasNEON, HasFullFP16]>; def VACGThq : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt", "f16", v8f16, v8f16, int_arm_neon_vacgt, 0>, Requires<[HasNEON, HasFullFP16]>; // VTST : Vector Test Bits defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, "vtst", "", NEONvtst, 1>; def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm", (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>; def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm", (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>; def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm", (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>; def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm", (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>; let Predicates = [HasNEON, HasFullFP16] in { def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm", (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>; def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm", (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>; def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm", (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>; def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm", (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>; } def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm", (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>; def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm", (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>; def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm", (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>; def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm", (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>; let Predicates = [HasNEON, HasFullFP16] in { def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm", (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>; def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm", (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>; def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm", (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>; def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm", (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>; } // Vector Bitwise Operations. def vnotd : PatFrag<(ops node:$in), (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>; def vnotq : PatFrag<(ops node:$in), (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>; // VAND : Vector Bitwise AND def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", v2i32, v2i32, and, 1>; def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", v4i32, v4i32, and, 1>; // VEOR : Vector Bitwise Exclusive OR def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", v2i32, v2i32, xor, 1>; def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", v4i32, v4i32, xor, 1>; // VORR : Vector Bitwise OR def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", v2i32, v2i32, or, 1>; def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", v4i32, v4i32, or, 1>; def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1, (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), IIC_VMOVImm, "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), IIC_VMOVImm, "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { let Inst{10-9} = SIMM{10-9}; } def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), IIC_VMOVImm, "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), IIC_VMOVImm, "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { let Inst{10-9} = SIMM{10-9}; } // VBIC : Vector Bitwise Bit Clear (AND NOT) let TwoOperandAliasConstraint = "$Vn = $Vd" in { def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, "vbic", "$Vd, $Vn, $Vm", "", [(set DPR:$Vd, (v2i32 (and DPR:$Vn, (vnotd DPR:$Vm))))]>; def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, "vbic", "$Vd, $Vn, $Vm", "", [(set QPR:$Vd, (v4i32 (and QPR:$Vn, (vnotq QPR:$Vm))))]>; } def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), IIC_VMOVImm, "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), IIC_VMOVImm, "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", [(set DPR:$Vd, (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { let Inst{10-9} = SIMM{10-9}; } def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), IIC_VMOVImm, "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), IIC_VMOVImm, "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", [(set QPR:$Vd, (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { let Inst{10-9} = SIMM{10-9}; } // VORN : Vector Bitwise OR NOT def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, "vorn", "$Vd, $Vn, $Vm", "", [(set DPR:$Vd, (v2i32 (or DPR:$Vn, (vnotd DPR:$Vm))))]>; def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, "vorn", "$Vd, $Vn, $Vm", "", [(set QPR:$Vd, (v4i32 (or QPR:$Vn, (vnotq QPR:$Vm))))]>; // VMVN : Vector Bitwise NOT (Immediate) let isReMaterializable = 1 in { def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd), (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmvn", "i16", "$Vd, $SIMM", "", [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd), (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmvn", "i16", "$Vd, $SIMM", "", [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd), (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmvn", "i32", "$Vd, $SIMM", "", [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; } def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd), (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmvn", "i32", "$Vd, $SIMM", "", [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; } } // VMVN : Vector Bitwise NOT def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD, "vmvn", "$Vd, $Vm", "", [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>; def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD, "vmvn", "$Vd, $Vm", "", [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>; def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>; def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>; // VBSL : Vector Bitwise Select def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VCNTiD, "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", [(set DPR:$Vd, (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>; def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1), (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))), (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1), (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))), (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1), (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))), (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1), (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))), (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1), (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))), (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd), (and DPR:$Vm, (vnotd DPR:$Vd)))), (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd), (and DPR:$Vm, (vnotd DPR:$Vd)))), (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>, Requires<[HasNEON]>; def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VCNTiQ, "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", [(set QPR:$Vd, (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>; def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1), (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))), (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1), (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))), (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1), (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))), (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1), (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))), (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1), (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))), (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd), (and QPR:$Vm, (vnotq QPR:$Vd)))), (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd), (and QPR:$Vm, (vnotq QPR:$Vd)))), (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>, Requires<[HasNEON]>; // VBIF : Vector Bitwise Insert if False // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst", // FIXME: This instruction's encoding MAY NOT BE correct. def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd", []>; def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd", []>; // VBIT : Vector Bitwise Insert if True // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst", // FIXME: This instruction's encoding MAY NOT BE correct. def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd", []>; def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd", []>; // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking // for equivalent operations with different register constraints; it just // inserts copies. // Vector Absolute Differences. // VABD : Vector Absolute Difference defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vabd", "s", int_arm_neon_vabds, 1>; defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vabd", "u", int_arm_neon_vabdu, 1>; def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND, "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>; def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ, "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>; def VABDhd : N3VDInt<1, 0, 0b11, 0b1101, 0, N3RegFrm, IIC_VBIND, "vabd", "f16", v4f16, v4f16, int_arm_neon_vabds, 1>, Requires<[HasNEON, HasFullFP16]>; def VABDhq : N3VQInt<1, 0, 0b11, 0b1101, 0, N3RegFrm, IIC_VBINQ, "vabd", "f16", v8f16, v8f16, int_arm_neon_vabds, 1>, Requires<[HasNEON, HasFullFP16]>; // VABDL : Vector Absolute Difference Long (Q = | D - D |) defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, "vabdl", "s", int_arm_neon_vabds, zext, 1>; defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, "vabdl", "u", int_arm_neon_vabdu, zext, 1>; def : Pat<(v8i16 (abs (sub (zext (v8i8 DPR:$opA)), (zext (v8i8 DPR:$opB))))), (VABDLuv8i16 DPR:$opA, DPR:$opB)>; def : Pat<(v4i32 (abs (sub (zext (v4i16 DPR:$opA)), (zext (v4i16 DPR:$opB))))), (VABDLuv4i32 DPR:$opA, DPR:$opB)>; // ISD::ABS is not legal for v2i64, so VABDL needs to be matched from the // shift/xor pattern for ABS. def abd_shr : PatFrag<(ops node:$in1, node:$in2, node:$shift), (NEONvshrs (sub (zext node:$in1), (zext node:$in2)), (i32 $shift))>; def : Pat<(xor (v4i32 (bitconvert (v2i64 (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))), (v4i32 (bitconvert (v2i64 (add (sub (zext (v2i32 DPR:$opA)), (zext (v2i32 DPR:$opB))), (abd_shr (v2i32 DPR:$opA), (v2i32 DPR:$opB), 63)))))), (VABDLuv2i64 DPR:$opA, DPR:$opB)>; // VABA : Vector Absolute Difference and Accumulate defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ, "vaba", "s", int_arm_neon_vabds, add>; defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ, "vaba", "u", int_arm_neon_vabdu, add>; // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD, "vabal", "s", int_arm_neon_vabds, zext, add>; defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD, "vabal", "u", int_arm_neon_vabdu, zext, add>; // Vector Maximum and Minimum. // VMAX : Vector Maximum defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vmax", "s", smax, 1>; defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vmax", "u", umax, 1>; def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmax", "f32", v2f32, v2f32, fmaxnan, 1>; def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmax", "f32", v4f32, v4f32, fmaxnan, 1>; def VMAXhd : N3VDInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmax", "f16", v4f16, v4f16, fmaxnan, 1>, Requires<[HasNEON, HasFullFP16]>; def VMAXhq : N3VQInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmax", "f16", v8f16, v8f16, fmaxnan, 1>, Requires<[HasNEON, HasFullFP16]>; // VMAXNM let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { def VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1, N3RegFrm, NoItinerary, "vmaxnm", "f32", v2f32, v2f32, fmaxnum, 1>, Requires<[HasV8, HasNEON]>; def VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1, N3RegFrm, NoItinerary, "vmaxnm", "f32", v4f32, v4f32, fmaxnum, 1>, Requires<[HasV8, HasNEON]>; def VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1, N3RegFrm, NoItinerary, "vmaxnm", "f16", v4f16, v4f16, fmaxnum, 1>, Requires<[HasV8, HasNEON, HasFullFP16]>; def VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1, N3RegFrm, NoItinerary, "vmaxnm", "f16", v8f16, v8f16, fmaxnum, 1>, Requires<[HasV8, HasNEON, HasFullFP16]>; } // VMIN : Vector Minimum defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vmin", "s", smin, 1>; defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, "vmin", "u", umin, 1>; def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmin", "f32", v2f32, v2f32, fminnan, 1>; def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmin", "f32", v4f32, v4f32, fminnan, 1>; def VMINhd : N3VDInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmin", "f16", v4f16, v4f16, fminnan, 1>, Requires<[HasNEON, HasFullFP16]>; def VMINhq : N3VQInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmin", "f16", v8f16, v8f16, fminnan, 1>, Requires<[HasNEON, HasFullFP16]>; // VMINNM let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { def VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1, N3RegFrm, NoItinerary, "vminnm", "f32", v2f32, v2f32, fminnum, 1>, Requires<[HasV8, HasNEON]>; def VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1, N3RegFrm, NoItinerary, "vminnm", "f32", v4f32, v4f32, fminnum, 1>, Requires<[HasV8, HasNEON]>; def VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1, N3RegFrm, NoItinerary, "vminnm", "f16", v4f16, v4f16, fminnum, 1>, Requires<[HasV8, HasNEON, HasFullFP16]>; def VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1, N3RegFrm, NoItinerary, "vminnm", "f16", v8f16, v8f16, fminnum, 1>, Requires<[HasV8, HasNEON, HasFullFP16]>; } // Vector Pairwise Operations. // VPADD : Vector Pairwise Add def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD, "vpadd", "i8", v8i8, v8i8, int_arm_neon_vpadd, 0>; def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD, "vpadd", "i16", v4i16, v4i16, int_arm_neon_vpadd, 0>; def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD, "vpadd", "i32", v2i32, v2i32, int_arm_neon_vpadd, 0>; def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm, IIC_VPBIND, "vpadd", "f32", v2f32, v2f32, int_arm_neon_vpadd, 0>; def VPADDh : N3VDInt<1, 0, 0b01, 0b1101, 0, N3RegFrm, IIC_VPBIND, "vpadd", "f16", v4f16, v4f16, int_arm_neon_vpadd, 0>, Requires<[HasNEON, HasFullFP16]>; // VPADDL : Vector Pairwise Add Long defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s", int_arm_neon_vpaddls>; defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u", int_arm_neon_vpaddlu>; // VPADAL : Vector Pairwise Add and Accumulate Long defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s", int_arm_neon_vpadals>; defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u", int_arm_neon_vpadalu>; // VPMAX : Vector Pairwise Maximum def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>; def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>; def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>; def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>; def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>; def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>; def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax", "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>; def VPMAXh : N3VDInt<1, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax", "f16", v4f16, v4f16, int_arm_neon_vpmaxs, 0>, Requires<[HasNEON, HasFullFP16]>; // VPMIN : Vector Pairwise Minimum def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>; def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>; def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>; def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>; def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>; def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>; def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin", "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>; def VPMINh : N3VDInt<1, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin", "f16", v4f16, v4f16, int_arm_neon_vpmins, 0>, Requires<[HasNEON, HasFullFP16]>; // Vector Reciprocal and Reciprocal Square Root Estimate and Step. // VRECPE : Vector Reciprocal Estimate def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, IIC_VUNAD, "vrecpe", "u32", v2i32, v2i32, int_arm_neon_vrecpe>; def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, IIC_VUNAQ, "vrecpe", "u32", v4i32, v4i32, int_arm_neon_vrecpe>; def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, IIC_VUNAD, "vrecpe", "f32", v2f32, v2f32, int_arm_neon_vrecpe>; def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, IIC_VUNAQ, "vrecpe", "f32", v4f32, v4f32, int_arm_neon_vrecpe>; def VRECPEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0, IIC_VUNAD, "vrecpe", "f16", v4f16, v4f16, int_arm_neon_vrecpe>, Requires<[HasNEON, HasFullFP16]>; def VRECPEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0, IIC_VUNAQ, "vrecpe", "f16", v8f16, v8f16, int_arm_neon_vrecpe>, Requires<[HasNEON, HasFullFP16]>; // VRECPS : Vector Reciprocal Step def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm, IIC_VRECSD, "vrecps", "f32", v2f32, v2f32, int_arm_neon_vrecps, 1>; def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm, IIC_VRECSQ, "vrecps", "f32", v4f32, v4f32, int_arm_neon_vrecps, 1>; def VRECPShd : N3VDInt<0, 0, 0b01, 0b1111, 1, N3RegFrm, IIC_VRECSD, "vrecps", "f16", v4f16, v4f16, int_arm_neon_vrecps, 1>, Requires<[HasNEON, HasFullFP16]>; def VRECPShq : N3VQInt<0, 0, 0b01, 0b1111, 1, N3RegFrm, IIC_VRECSQ, "vrecps", "f16", v8f16, v8f16, int_arm_neon_vrecps, 1>, Requires<[HasNEON, HasFullFP16]>; // VRSQRTE : Vector Reciprocal Square Root Estimate def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, IIC_VUNAD, "vrsqrte", "u32", v2i32, v2i32, int_arm_neon_vrsqrte>; def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, IIC_VUNAQ, "vrsqrte", "u32", v4i32, v4i32, int_arm_neon_vrsqrte>; def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, IIC_VUNAD, "vrsqrte", "f32", v2f32, v2f32, int_arm_neon_vrsqrte>; def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, IIC_VUNAQ, "vrsqrte", "f32", v4f32, v4f32, int_arm_neon_vrsqrte>; def VRSQRTEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01011, 0, IIC_VUNAD, "vrsqrte", "f16", v4f16, v4f16, int_arm_neon_vrsqrte>, Requires<[HasNEON, HasFullFP16]>; def VRSQRTEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01011, 0, IIC_VUNAQ, "vrsqrte", "f16", v8f16, v8f16, int_arm_neon_vrsqrte>, Requires<[HasNEON, HasFullFP16]>; // VRSQRTS : Vector Reciprocal Square Root Step def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm, IIC_VRECSD, "vrsqrts", "f32", v2f32, v2f32, int_arm_neon_vrsqrts, 1>; def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm, IIC_VRECSQ, "vrsqrts", "f32", v4f32, v4f32, int_arm_neon_vrsqrts, 1>; def VRSQRTShd : N3VDInt<0, 0, 0b11, 0b1111, 1, N3RegFrm, IIC_VRECSD, "vrsqrts", "f16", v4f16, v4f16, int_arm_neon_vrsqrts, 1>, Requires<[HasNEON, HasFullFP16]>; def VRSQRTShq : N3VQInt<0, 0, 0b11, 0b1111, 1, N3RegFrm, IIC_VRECSQ, "vrsqrts", "f16", v8f16, v8f16, int_arm_neon_vrsqrts, 1>, Requires<[HasNEON, HasFullFP16]>; // Vector Shifts. // VSHL : Vector Shift defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ, "vshl", "s", int_arm_neon_vshifts>; defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm, IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ, "vshl", "u", int_arm_neon_vshiftu>; // VSHL : Vector Shift Left (Immediate) defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>; // VSHR : Vector Shift Right (Immediate) defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs", NEONvshrs>; defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu", NEONvshru>; // VSHLL : Vector Shift Left Long defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>; defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>; // VSHLL : Vector Shift Left Long (with maximum shift count) class N2VLShMax op21_16, bits<4> op11_8, bit op7, bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, Operand ImmTy> : N2VLSh { let Inst{21-16} = op21_16; let DecoderMethod = "DecodeVSHLMaxInstruction"; } def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8", v8i16, v8i8, imm8>; def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16", v4i32, v4i16, imm16>; def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32", v2i64, v2i32, imm32>; def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))), (VSHLLi8 DPR:$Rn, 8)>; def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))), (VSHLLi16 DPR:$Rn, 16)>; def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))), (VSHLLi32 DPR:$Rn, 32)>; def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))), (VSHLLi8 DPR:$Rn, 8)>; def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))), (VSHLLi16 DPR:$Rn, 16)>; def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))), (VSHLLi32 DPR:$Rn, 32)>; def : Pat<(v8i16 (NEONvshl (anyext (v8i8 DPR:$Rn)), (i32 8))), (VSHLLi8 DPR:$Rn, 8)>; def : Pat<(v4i32 (NEONvshl (anyext (v4i16 DPR:$Rn)), (i32 16))), (VSHLLi16 DPR:$Rn, 16)>; def : Pat<(v2i64 (NEONvshl (anyext (v2i32 DPR:$Rn)), (i32 32))), (VSHLLi32 DPR:$Rn, 32)>; // VSHRN : Vector Shift Right and Narrow defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", PatFrag<(ops node:$Rn, node:$amt), (trunc (NEONvshrs node:$Rn, node:$amt))>>; def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))), (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>; def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))), (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>; def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))), (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>; // VRSHL : Vector Rounding Shift defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, "vrshl", "s", int_arm_neon_vrshifts>; defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, "vrshl", "u", int_arm_neon_vrshiftu>; // VRSHR : Vector Rounding Shift Right defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs", NEONvrshrs>; defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu", NEONvrshru>; // VRSHRN : Vector Rounding Shift Right and Narrow defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i", NEONvrshrn>; // VQSHL : Vector Saturating Shift defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, "vqshl", "s", int_arm_neon_vqshifts>; defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, "vqshl", "u", int_arm_neon_vqshiftu>; // VQSHL : Vector Saturating Shift Left (Immediate) defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>; defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>; // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>; // VQSHRN : Vector Saturating Shift Right and Narrow defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s", NEONvqshrns>; defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u", NEONvqshrnu>; // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s", NEONvqshrnsu>; // VQRSHL : Vector Saturating Rounding Shift defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, "vqrshl", "s", int_arm_neon_vqrshifts>; defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm, IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, "vqrshl", "u", int_arm_neon_vqrshiftu>; // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s", NEONvqrshrns>; defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u", NEONvqrshrnu>; // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s", NEONvqrshrnsu>; // VSRA : Vector Shift Right and Accumulate defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>; defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>; // VRSRA : Vector Rounding Shift Right and Accumulate defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>; defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>; // VSLI : Vector Shift Left and Insert defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">; // VSRI : Vector Shift Right and Insert defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">; // Vector Absolute and Saturating Absolute. // VABS : Vector Absolute Value defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s", abs>; def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs", "f32", v2f32, v2f32, fabs>; def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs", "f32", v4f32, v4f32, fabs>; def VABShd : N2VD<0b11, 0b11, 0b01, 0b01, 0b01110, 0, "vabs", "f16", v4f16, v4f16, fabs>, Requires<[HasNEON, HasFullFP16]>; def VABShq : N2VQ<0b11, 0b11, 0b01, 0b01, 0b01110, 0, "vabs", "f16", v8f16, v8f16, fabs>, Requires<[HasNEON, HasFullFP16]>; // VQABS : Vector Saturating Absolute Value defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s", int_arm_neon_vqabs>; // Vector Negate. def vnegd : PatFrag<(ops node:$in), (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>; def vnegq : PatFrag<(ops node:$in), (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>; class VNEGD size, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>; class VNEGQ size, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "", [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>; // VNEG : Vector Negate (integer) def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>; def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>; def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>; def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>; def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>; def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>; // VNEG : Vector Negate (floating-point) def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD, "vneg", "f32", "$Vd, $Vm", "", [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>; def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ, "vneg", "f32", "$Vd, $Vm", "", [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>; def VNEGhd : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD, "vneg", "f16", "$Vd, $Vm", "", [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))]>, Requires<[HasNEON, HasFullFP16]>; def VNEGhq : N2V<0b11, 0b11, 0b01, 0b01, 0b01111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ, "vneg", "f16", "$Vd, $Vm", "", [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>, Requires<[HasNEON, HasFullFP16]>; def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>; def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>; def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>; def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>; def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>; def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>; // VQNEG : Vector Saturating Negate defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s", int_arm_neon_vqneg>; // Vector Bit Counting Operations. // VCLS : Vector Count Leading Sign Bits defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s", int_arm_neon_vcls>; // VCLZ : Vector Count Leading Zeros defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i", ctlz>; // VCNT : Vector Count One Bits def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, IIC_VCNTiD, "vcnt", "8", v8i8, v8i8, ctpop>; def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, IIC_VCNTiQ, "vcnt", "8", v16i8, v16i8, ctpop>; // Vector Swap def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0, (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2), NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm", []>; def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0, (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2), NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm", []>; // Vector Move Operations. // VMOV : Vector Move (Register) def : NEONInstAlias<"vmov${p} $Vd, $Vm", (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; def : NEONInstAlias<"vmov${p} $Vd, $Vm", (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; // VMOV : Vector Move (Immediate) // Although VMOVs are not strictly speaking cheap, they are as expensive // as their copies counterpart (VORR), so we should prefer rematerialization // over splitting when it applies. let isReMaterializable = 1, isAsCheapAsAMove=1 in { def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd), (ins nImmSplatI8:$SIMM), IIC_VMOVImm, "vmov", "i8", "$Vd, $SIMM", "", [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>; def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd), (ins nImmSplatI8:$SIMM), IIC_VMOVImm, "vmov", "i8", "$Vd, $SIMM", "", [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>; def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd), (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmov", "i16", "$Vd, $SIMM", "", [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd), (ins nImmSplatI16:$SIMM), IIC_VMOVImm, "vmov", "i16", "$Vd, $SIMM", "", [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> { let Inst{9} = SIMM{9}; } def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd), (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmov", "i32", "$Vd, $SIMM", "", [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; } def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd), (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, "vmov", "i32", "$Vd, $SIMM", "", [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> { let Inst{11-8} = SIMM{11-8}; } def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd), (ins nImmSplatI64:$SIMM), IIC_VMOVImm, "vmov", "i64", "$Vd, $SIMM", "", [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>; def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd), (ins nImmSplatI64:$SIMM), IIC_VMOVImm, "vmov", "i64", "$Vd, $SIMM", "", [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>; def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd), (ins nImmVMOVF32:$SIMM), IIC_VMOVImm, "vmov", "f32", "$Vd, $SIMM", "", [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>; def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd), (ins nImmVMOVF32:$SIMM), IIC_VMOVImm, "vmov", "f32", "$Vd, $SIMM", "", [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>; } // isReMaterializable, isAsCheapAsAMove // Add support for bytes replication feature, so it could be GAS compatible. multiclass NEONImmReplicateI8InstAlias { // E.g. instructions below: // "vmov.i32 d0, #0xffffffff" // "vmov.i32 d0, #0xabababab" // "vmov.i16 d0, #0xabab" // are incorrect, but we could deal with such cases. // For last two instructions, for example, it should emit: // "vmov.i8 d0, #0xab" def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm", (VMOVv8i8 DPR:$Vd, nImmVMOVIReplicate:$Vm, pred:$p)>; def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm", (VMOVv16i8 QPR:$Vd, nImmVMOVIReplicate:$Vm, pred:$p)>; // Also add same support for VMVN instructions. So instruction: // "vmvn.i32 d0, #0xabababab" // actually means: // "vmov.i8 d0, #0x54" def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm", (VMOVv8i8 DPR:$Vd, nImmVINVIReplicate:$Vm, pred:$p)>; def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm", (VMOVv16i8 QPR:$Vd, nImmVINVIReplicate:$Vm, pred:$p)>; } defm : NEONImmReplicateI8InstAlias; defm : NEONImmReplicateI8InstAlias; defm : NEONImmReplicateI8InstAlias; // Similar to above for types other than i8, e.g.: // "vmov.i32 d0, #0xab00ab00" -> "vmov.i16 d0, #0xab00" // "vmvn.i64 q0, #0xab000000ab000000" -> "vmvn.i32 q0, #0xab000000" // In this case we do not canonicalize VMVN to VMOV multiclass NEONImmReplicateInstAlias { def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm", (V8 DPR:$Vd, nImmVMOVIReplicate:$Vm, pred:$p)>; def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm", (V16 QPR:$Vd, nImmVMOVIReplicate:$Vm, pred:$p)>; def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm", (NV8 DPR:$Vd, nImmVMOVIReplicate:$Vm, pred:$p)>; def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm", (NV16 QPR:$Vd, nImmVMOVIReplicate:$Vm, pred:$p)>; } defm : NEONImmReplicateInstAlias; defm : NEONImmReplicateInstAlias; defm : NEONImmReplicateInstAlias; // TODO: add "VMOV <-> VMVN" conversion for cases like // "vmov.i32 d0, #0xffaaffaa" -> "vmvn.i16 d0, #0x55" // "vmvn.i32 d0, #0xaaffaaff" -> "vmov.i16 d0, #0xff00" // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0" // require zero cycles to execute so they should be used wherever possible for // setting a register to zero. // Even without these pseudo-insts we would probably end up with the correct // instruction, but we could not mark the general ones with "isAsCheapAsAMove" // since they are sometimes rather expensive (in general). let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in { def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm, [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))], (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>, Requires<[HasZCZ]>; def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm, [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))], (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>, Requires<[HasZCZ]>; } // VMOV : Vector Get Lane (move scalar to ARM core register) def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?}, (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), IIC_VMOVSI, "vmov", "s8", "$R, $V$lane", [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V), imm:$lane))]> { let Inst{21} = lane{2}; let Inst{6-5} = lane{1-0}; } def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1}, (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), IIC_VMOVSI, "vmov", "s16", "$R, $V$lane", [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V), imm:$lane))]> { let Inst{21} = lane{1}; let Inst{6} = lane{0}; } def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?}, (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), IIC_VMOVSI, "vmov", "u8", "$R, $V$lane", [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V), imm:$lane))]> { let Inst{21} = lane{2}; let Inst{6-5} = lane{1-0}; } def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1}, (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), IIC_VMOVSI, "vmov", "u16", "$R, $V$lane", [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V), imm:$lane))]> { let Inst{21} = lane{1}; let Inst{6} = lane{0}; } def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00, (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane), IIC_VMOVSI, "vmov", "32", "$R, $V$lane", [(set GPR:$R, (extractelt (v2i32 DPR:$V), imm:$lane))]>, Requires<[HasVFP2, HasFastVGETLNi32]> { let Inst{21} = lane{0}; } // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, (DSubReg_i8_reg imm:$lane))), (SubReg_i8_lane imm:$lane))>; def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane))>; def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, (DSubReg_i8_reg imm:$lane))), (SubReg_i8_lane imm:$lane))>; def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane))>; def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane))>, Requires<[HasNEON, HasFastVGETLNi32]>; def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane), (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>, Requires<[HasNEON, HasSlowVGETLNi32]>; def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>, Requires<[HasNEON, HasSlowVGETLNi32]>; def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2), (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)), (SSubReg_f32_reg imm:$src2))>; def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2), (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)), (SSubReg_f32_reg imm:$src2))>; //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; // VMOV : Vector Set Lane (move ARM core register to scalar) let Constraints = "$src1 = $V" in { def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V), (ins DPR:$src1, GPR:$R, VectorIndex8:$lane), IIC_VMOVISL, "vmov", "8", "$V$lane, $R", [(set DPR:$V, (vector_insert (v8i8 DPR:$src1), GPR:$R, imm:$lane))]> { let Inst{21} = lane{2}; let Inst{6-5} = lane{1-0}; } def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V), (ins DPR:$src1, GPR:$R, VectorIndex16:$lane), IIC_VMOVISL, "vmov", "16", "$V$lane, $R", [(set DPR:$V, (vector_insert (v4i16 DPR:$src1), GPR:$R, imm:$lane))]> { let Inst{21} = lane{1}; let Inst{6} = lane{0}; } def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V), (ins DPR:$src1, GPR:$R, VectorIndex32:$lane), IIC_VMOVISL, "vmov", "32", "$V$lane, $R", [(set DPR:$V, (insertelt (v2i32 DPR:$src1), GPR:$R, imm:$lane))]>, Requires<[HasVFP2]> { let Inst{21} = lane{0}; // This instruction is equivalent as // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm) let isInsertSubreg = 1; } } def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), (v16i8 (INSERT_SUBREG QPR:$src1, (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, (DSubReg_i8_reg imm:$lane))), GPR:$src2, (SubReg_i8_lane imm:$lane))), (DSubReg_i8_reg imm:$lane)))>; def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), (v8i16 (INSERT_SUBREG QPR:$src1, (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, (DSubReg_i16_reg imm:$lane))), GPR:$src2, (SubReg_i16_lane imm:$lane))), (DSubReg_i16_reg imm:$lane)))>; def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), (v4i32 (INSERT_SUBREG QPR:$src1, (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, (DSubReg_i32_reg imm:$lane))), GPR:$src2, (SubReg_i32_lane imm:$lane))), (DSubReg_i32_reg imm:$lane)))>; def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)), SPR:$src2, (SSubReg_f32_reg imm:$src3))>; def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)), SPR:$src2, (SSubReg_f32_reg imm:$src3))>; //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; def : Pat<(v2f32 (scalar_to_vector SPR:$src)), (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))), (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; def : Pat<(v4f32 (scalar_to_vector SPR:$src)), (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; def : Pat<(v8i8 (scalar_to_vector GPR:$src)), (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; def : Pat<(v4i16 (scalar_to_vector GPR:$src)), (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; def : Pat<(v2i32 (scalar_to_vector GPR:$src)), (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; def : Pat<(v16i8 (scalar_to_vector GPR:$src)), (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)), dsub_0)>; def : Pat<(v8i16 (scalar_to_vector GPR:$src)), (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)), dsub_0)>; def : Pat<(v4i32 (scalar_to_vector GPR:$src)), (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)), dsub_0)>; // VDUP : Vector Duplicate (from ARM core register to all elements) class VDUPD opcod1, bits<2> opcod3, string Dt, ValueType Ty> : NVDup; class VDUPQ opcod1, bits<2> opcod3, string Dt, ValueType Ty> : NVDup; def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>; def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>; def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>, Requires<[HasNEON, HasFastVDUP32]>; def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>; def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>; def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>; // NEONvdup patterns for uarchs with fast VDUP.32. def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>, Requires<[HasNEON,HasFastVDUP32]>; def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>; // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead. def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>, Requires<[HasNEON,HasSlowVDUP32]>; def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>, Requires<[HasNEON,HasSlowVDUP32]>; // VDUP : Vector Duplicate Lane (from scalar to all elements) class VDUPLND op19_16, string OpcodeStr, string Dt, ValueType Ty, Operand IdxTy> : NVDupLane; class VDUPLNQ op19_16, string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, Operand IdxTy> : NVDupLane; // Inst{19-16} is partially specified depending on the element size. def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> { bits<3> lane; let Inst{19-17} = lane{2-0}; } def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> { bits<2> lane; let Inst{19-18} = lane{1-0}; } def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> { bits<1> lane; let Inst{19} = lane{0}; } def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> { bits<3> lane; let Inst{19-17} = lane{2-0}; } def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> { bits<2> lane; let Inst{19-18} = lane{1-0}; } def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> { bits<1> lane; let Inst{19} = lane{0}; } def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)), (VDUPLN32d DPR:$Vm, imm:$lane)>; def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)), (VDUPLN32q DPR:$Vm, imm:$lane)>; def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)), (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src, (DSubReg_i8_reg imm:$lane))), (SubReg_i8_lane imm:$lane)))>; def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)), (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)), (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)), (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))), (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0), (i32 0)))>; def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))), (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0), (i32 0)))>; // VMOVN : Vector Narrowing Move defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN, "vmovn", "i", trunc>; // VQMOVN : Vector Saturating Narrowing Move defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn", "s", int_arm_neon_vqmovns>; defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, "vqmovn", "u", int_arm_neon_vqmovnu>; defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, "vqmovun", "s", int_arm_neon_vqmovnsu>; // VMOVL : Vector Lengthening Move defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>; defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>; def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>; def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>; def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>; // Vector Conversions. // VCVT : Vector Convert Between Floating-Point and Integers def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32", v2i32, v2f32, fp_to_sint>; def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32", v2i32, v2f32, fp_to_uint>; def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", v2f32, v2i32, sint_to_fp>; def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", v2f32, v2i32, uint_to_fp>; def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32", v4i32, v4f32, fp_to_sint>; def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32", v4i32, v4f32, fp_to_uint>; def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", v4f32, v4i32, sint_to_fp>; def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", v4f32, v4i32, uint_to_fp>; def VCVTh2sd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01110, 0, "vcvt", "s16.f16", v4i16, v4f16, fp_to_sint>, Requires<[HasNEON, HasFullFP16]>; def VCVTh2ud : N2VD<0b11, 0b11, 0b01, 0b11, 0b01111, 0, "vcvt", "u16.f16", v4i16, v4f16, fp_to_uint>, Requires<[HasNEON, HasFullFP16]>; def VCVTs2hd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01100, 0, "vcvt", "f16.s16", v4f16, v4i16, sint_to_fp>, Requires<[HasNEON, HasFullFP16]>; def VCVTu2hd : N2VD<0b11, 0b11, 0b01, 0b11, 0b01101, 0, "vcvt", "f16.u16", v4f16, v4i16, uint_to_fp>, Requires<[HasNEON, HasFullFP16]>; def VCVTh2sq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01110, 0, "vcvt", "s16.f16", v8i16, v8f16, fp_to_sint>, Requires<[HasNEON, HasFullFP16]>; def VCVTh2uq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01111, 0, "vcvt", "u16.f16", v8i16, v8f16, fp_to_uint>, Requires<[HasNEON, HasFullFP16]>; def VCVTs2hq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01100, 0, "vcvt", "f16.s16", v8f16, v8i16, sint_to_fp>, Requires<[HasNEON, HasFullFP16]>; def VCVTu2hq : N2VQ<0b11, 0b11, 0b01, 0b11, 0b01101, 0, "vcvt", "f16.u16", v8f16, v8i16, uint_to_fp>, Requires<[HasNEON, HasFullFP16]>; // VCVT{A, N, P, M} multiclass VCVT_FPI op10_8, SDPatternOperator IntS, SDPatternOperator IntU> { let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { def SDf : N2VDIntnp<0b10, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op), "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>; def SQf : N2VQIntnp<0b10, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op), "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>; def UDf : N2VDIntnp<0b10, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op), "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>; def UQf : N2VQIntnp<0b10, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op), "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>; def SDh : N2VDIntnp<0b01, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op), "s16.f16", v4i16, v4f16, IntS>, Requires<[HasV8, HasNEON, HasFullFP16]>; def SQh : N2VQIntnp<0b01, 0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op), "s16.f16", v8i16, v8f16, IntS>, Requires<[HasV8, HasNEON, HasFullFP16]>; def UDh : N2VDIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op), "u16.f16", v4i16, v4f16, IntU>, Requires<[HasV8, HasNEON, HasFullFP16]>; def UQh : N2VQIntnp<0b01, 0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op), "u16.f16", v8i16, v8f16, IntU>, Requires<[HasV8, HasNEON, HasFullFP16]>; } } defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>; defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>; defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>; defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>; // VCVT : Vector Convert Between Floating-Point and Fixed-Point. let DecoderMethod = "DecodeVCVTD" in { def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32", v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32", v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; let Predicates = [HasNEON, HasFullFP16] in { def VCVTh2xsd : N2VCvtD<0, 1, 0b1101, 0, 1, "vcvt", "s16.f16", v4i16, v4f16, int_arm_neon_vcvtfp2fxs>; def VCVTh2xud : N2VCvtD<1, 1, 0b1101, 0, 1, "vcvt", "u16.f16", v4i16, v4f16, int_arm_neon_vcvtfp2fxu>; def VCVTxs2hd : N2VCvtD<0, 1, 0b1100, 0, 1, "vcvt", "f16.s16", v4f16, v4i16, int_arm_neon_vcvtfxs2fp>; def VCVTxu2hd : N2VCvtD<1, 1, 0b1100, 0, 1, "vcvt", "f16.u16", v4f16, v4i16, int_arm_neon_vcvtfxu2fp>; } // Predicates = [HasNEON, HasFullFP16] } let DecoderMethod = "DecodeVCVTQ" in { def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32", v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32", v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; let Predicates = [HasNEON, HasFullFP16] in { def VCVTh2xsq : N2VCvtQ<0, 1, 0b1101, 0, 1, "vcvt", "s16.f16", v8i16, v8f16, int_arm_neon_vcvtfp2fxs>; def VCVTh2xuq : N2VCvtQ<1, 1, 0b1101, 0, 1, "vcvt", "u16.f16", v8i16, v8f16, int_arm_neon_vcvtfp2fxu>; def VCVTxs2hq : N2VCvtQ<0, 1, 0b1100, 0, 1, "vcvt", "f16.s16", v8f16, v8i16, int_arm_neon_vcvtfxs2fp>; def VCVTxu2hq : N2VCvtQ<1, 1, 0b1100, 0, 1, "vcvt", "f16.u16", v8f16, v8i16, int_arm_neon_vcvtfxu2fp>; } // Predicates = [HasNEON, HasFullFP16] } def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0", (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0", (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0", (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0", (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0", (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0", (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0", (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0", (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.s16.f16 $Dd, $Dm, #0", (VCVTh2sd DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.u16.f16 $Dd, $Dm, #0", (VCVTh2ud DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f16.s16 $Dd, $Dm, #0", (VCVTs2hd DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f16.u16 $Dd, $Dm, #0", (VCVTu2hd DPR:$Dd, DPR:$Dm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.s16.f16 $Qd, $Qm, #0", (VCVTh2sq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.u16.f16 $Qd, $Qm, #0", (VCVTh2uq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f16.s16 $Qd, $Qm, #0", (VCVTs2hq QPR:$Qd, QPR:$Qm, pred:$p)>; def : NEONInstAlias<"vcvt${p}.f16.u16 $Qd, $Qm, #0", (VCVTu2hq QPR:$Qd, QPR:$Qm, pred:$p)>; // VCVT : Vector Convert Between Half-Precision and Single-Precision. def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0, IIC_VUNAQ, "vcvt", "f16.f32", v4i16, v4f32, int_arm_neon_vcvtfp2hf>, Requires<[HasNEON, HasFP16]>; def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0, IIC_VUNAQ, "vcvt", "f32.f16", v4f32, v4i16, int_arm_neon_vcvthf2fp>, Requires<[HasNEON, HasFP16]>; // Vector Reverse. // VREV64 : Vector Reverse elements within 64-bit doublewords class VREV64D op19_18, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm", "", [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>; class VREV64Q op19_18, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm", "", [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>; def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>; def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>; def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>; def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>; def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>; def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>; def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>; def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>; // VREV32 : Vector Reverse elements within 32-bit words class VREV32D op19_18, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm", "", [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>; class VREV32Q op19_18, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm", "", [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>; def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>; def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>; def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>; def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>; // VREV16 : Vector Reverse elements within 16-bit halfwords class VREV16D op19_18, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm", "", [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>; class VREV16Q op19_18, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm", "", [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>; def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>; def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>; // Other Vector Shuffles. // Aligned extractions: really just dropping registers class AlignedVEXTq : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))), (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>; def : AlignedVEXTq; def : AlignedVEXTq; def : AlignedVEXTq; def : AlignedVEXTq; def : AlignedVEXTq; // VEXT : Vector Extract // All of these have a two-operand InstAlias. let TwoOperandAliasConstraint = "$Vn = $Vd" in { class VEXTd : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm, IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn), (Ty DPR:$Vm), imm:$index)))]> { bits<3> index; let Inst{11} = 0b0; let Inst{10-8} = index{2-0}; } class VEXTq : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm, IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn), (Ty QPR:$Vm), imm:$index)))]> { bits<4> index; let Inst{11-8} = index{3-0}; } } def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> { let Inst{10-8} = index{2-0}; } def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> { let Inst{10-9} = index{1-0}; let Inst{8} = 0b0; } def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> { let Inst{10} = index{0}; let Inst{9-8} = 0b00; } def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn), (v2f32 DPR:$Vm), (i32 imm:$index))), (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>; def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> { let Inst{11-8} = index{3-0}; } def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> { let Inst{11-9} = index{2-0}; let Inst{8} = 0b0; } def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> { let Inst{11-10} = index{1-0}; let Inst{9-8} = 0b00; } def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> { let Inst{11} = index{0}; let Inst{10-8} = 0b000; } def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn), (v4f32 QPR:$Vm), (i32 imm:$index))), (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>; // VTRN : Vector Transpose def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">; def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">; def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">; def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">; def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">; def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">; // VUZP : Vector Unzip (Deinterleave) def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">; def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">; // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm. def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm", (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>; def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">; def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">; def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">; // VZIP : Vector Zip (Interleave) def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">; def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">; // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm. def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm", (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>; def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">; def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">; def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">; // Vector Table Lookup and Table Extension. // VTBL : Vector Table Lookup let DecoderMethod = "DecodeTBLInstruction" in { def VTBL1 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd), (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1, "vtbl", "8", "$Vd, $Vn, $Vm", "", [(set DPR:$Vd, (v8i8 (NEONvtbl1 VecListOneD:$Vn, DPR:$Vm)))]>; let hasExtraSrcRegAllocReq = 1 in { def VTBL2 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd), (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2, "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; def VTBL3 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd), (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3, "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; def VTBL4 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd), (ins VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB4, "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; } // hasExtraSrcRegAllocReq = 1 def VTBL3Pseudo : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>; def VTBL4Pseudo : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>; // VTBX : Vector Table Extension def VTBX1 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd), (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1, "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>; let hasExtraSrcRegAllocReq = 1 in { def VTBX2 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd), (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2, "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>; def VTBX3 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd), (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX3, "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>; def VTBX4 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4, "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>; } // hasExtraSrcRegAllocReq = 1 def VTBX3Pseudo : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), IIC_VTBX3, "$orig = $dst", []>; def VTBX4Pseudo : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), IIC_VTBX4, "$orig = $dst", []>; } // DecoderMethod = "DecodeTBLInstruction" def : Pat<(v8i8 (NEONvtbl2 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vm)), (v8i8 (VTBL2 (REG_SEQUENCE DPair, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1), v8i8:$Vm))>; def : Pat<(v8i8 (int_arm_neon_vtbx2 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vm)), (v8i8 (VTBX2 v8i8:$orig, (REG_SEQUENCE DPair, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1), v8i8:$Vm))>; def : Pat<(v8i8 (int_arm_neon_vtbl3 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vm)), (v8i8 (VTBL3Pseudo (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, (v8i8 (IMPLICIT_DEF)), dsub_3), v8i8:$Vm))>; def : Pat<(v8i8 (int_arm_neon_vtbx3 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vm)), (v8i8 (VTBX3Pseudo v8i8:$orig, (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, (v8i8 (IMPLICIT_DEF)), dsub_3), v8i8:$Vm))>; def : Pat<(v8i8 (int_arm_neon_vtbl4 v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vn3, v8i8:$Vm)), (v8i8 (VTBL4Pseudo (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, v8i8:$Vn3, dsub_3), v8i8:$Vm))>; def : Pat<(v8i8 (int_arm_neon_vtbx4 v8i8:$orig, v8i8:$Vn0, v8i8:$Vn1, v8i8:$Vn2, v8i8:$Vn3, v8i8:$Vm)), (v8i8 (VTBX4Pseudo v8i8:$orig, (REG_SEQUENCE QQPR, v8i8:$Vn0, dsub_0, v8i8:$Vn1, dsub_1, v8i8:$Vn2, dsub_2, v8i8:$Vn3, dsub_3), v8i8:$Vm))>; // VRINT : Vector Rounding multiclass VRINT_FPI op9_7, SDPatternOperator Int> { let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { def Df : N2VDIntnp<0b10, 0b10, 0b100, 0, NoItinerary, !strconcat("vrint", op), "f32", v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> { let Inst{9-7} = op9_7; } def Qf : N2VQIntnp<0b10, 0b10, 0b100, 0, NoItinerary, !strconcat("vrint", op), "f32", v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> { let Inst{9-7} = op9_7; } def Dh : N2VDIntnp<0b01, 0b10, 0b100, 0, NoItinerary, !strconcat("vrint", op), "f16", v4f16, v4f16, Int>, Requires<[HasV8, HasNEON, HasFullFP16]> { let Inst{9-7} = op9_7; } def Qh : N2VQIntnp<0b01, 0b10, 0b100, 0, NoItinerary, !strconcat("vrint", op), "f16", v8f16, v8f16, Int>, Requires<[HasV8, HasNEON, HasFullFP16]> { let Inst{9-7} = op9_7; } } def : NEONInstAlias(NAME#"Df") DPR:$Dd, DPR:$Dm)>; def : NEONInstAlias(NAME#"Qf") QPR:$Qd, QPR:$Qm)>; let Predicates = [HasNEON, HasFullFP16] in { def : NEONInstAlias(NAME#"Dh") DPR:$Dd, DPR:$Dm)>; def : NEONInstAlias(NAME#"Qh") QPR:$Qd, QPR:$Qm)>; } } defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>; defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>; defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>; defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>; defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>; defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>; // Cryptography instructions let PostEncoderMethod = "NEONThumb2DataIPostEncoder", DecoderNamespace = "v8Crypto", hasSideEffects = 0 in { class AES : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary, !strconcat("aes", op), "8", v16i8, v16i8, Int>, Requires<[HasV8, HasCrypto]>; class AES2Op : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary, !strconcat("aes", op), "8", v16i8, v16i8, Int>, Requires<[HasV8, HasCrypto]>; class N2SHA op17_16, bits<3> op10_8, bit op7, bit op6, SDPatternOperator Int> : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary, !strconcat("sha", op), "32", v4i32, v4i32, Int>, Requires<[HasV8, HasCrypto]>; class N2SHA2Op op17_16, bits<3> op10_8, bit op7, bit op6, SDPatternOperator Int> : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary, !strconcat("sha", op), "32", v4i32, v4i32, Int>, Requires<[HasV8, HasCrypto]>; class N3SHA3Op op27_23, bits<2> op21_20, SDPatternOperator Int> : N3VQInt3np, Requires<[HasV8, HasCrypto]>; } def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>; def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>; def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>; def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>; def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>; def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>; def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>; def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>; def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>; def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>; def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>; def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>; def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>; def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>; def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)), (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG (SHA1H (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0)), ssub_0)), GPR)>; def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1C v4i32:$hash_abcd, (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1M v4i32:$hash_abcd, (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1P v4i32:$hash_abcd, (SUBREG_TO_REG (i64 0), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; //===----------------------------------------------------------------------===// // NEON instructions for single-precision FP math //===----------------------------------------------------------------------===// class N2VSPat : NEONFPPat<(f32 (OpNode SPR:$a)), (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (Inst (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>; class N3VSPat : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (Inst (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; class N3VSPatFP16 : NEONFPPat<(f16 (OpNode HPR:$a, HPR:$b)), (EXTRACT_SUBREG (v4f16 (COPY_TO_REGCLASS (Inst (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$a, ssub_0), (INSERT_SUBREG (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), HPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; class N3VSMulOpPat : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (Inst (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$acc, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$a, ssub_0), (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; class NVCVTIFPat : NEONFPPat<(f32 (OpNode GPR:$a)), (f32 (EXTRACT_SUBREG (v2f32 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), (i32 (COPY_TO_REGCLASS GPR:$a, SPR)), ssub_0))), ssub_0))>; class NVCVTFIPat : NEONFPPat<(i32 (OpNode SPR:$a)), (i32 (EXTRACT_SUBREG (v2f32 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, ssub_0))), ssub_0))>; def : N3VSPat; def : N3VSPat; def : N3VSPat; def : N3VSMulOpPat, Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>; def : N3VSMulOpPat, Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>; def : N3VSMulOpPat, Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>; def : N3VSMulOpPat, Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>; def : N2VSPat; def : N2VSPat; def : N3VSPatFP16, Requires<[HasFullFP16]>; def : N3VSPatFP16, Requires<[HasFullFP16]>; def : N3VSPat, Requires<[HasNEON]>; def : N3VSPat, Requires<[HasNEON]>; def : NVCVTFIPat; def : NVCVTFIPat; def : NVCVTIFPat; def : NVCVTIFPat; // NEON doesn't have any f64 conversions, so provide patterns to make // sure the VFP conversions match when extracting from a vector. def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))), (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>; def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))), (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>; def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))), (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>; def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))), (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>; // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers. def : Pat<(f32 (bitconvert GPR:$a)), (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>, Requires<[HasNEON, DontUseVMOVSR]>; def : Pat<(arm_vmovsr GPR:$a), (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>, Requires<[HasNEON, DontUseVMOVSR]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// // bit_convert let Predicates = [IsLE] in { def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; } def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; } def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; } def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; let Predicates = [IsLE] in { def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; def : Pat<(f64 (bitconvert (v4f16 DPR:$src))), (f64 DPR:$src)>; def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; def : Pat<(v4f16 (bitconvert (f64 DPR:$src))), (v4f16 DPR:$src)>; def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; } def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; } let Predicates = [IsLE] in { def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; } def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; } def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; def : Pat<(v8f16 (bitconvert (v2f64 QPR:$src))), (v8f16 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; } def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; } def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; let Predicates = [IsLE] in { def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v8f16 QPR:$src))), (v2f64 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; } let Predicates = [IsBE] in { // 64 bit conversions def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>; def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>; def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>; def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>; def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (VREV64d16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (VREV32d16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (VREV16d8 DPR:$src)>; def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (VREV64d16 DPR:$src)>; def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (VREV32d16 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (VREV64d8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (VREV32d8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (VREV16d8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (VREV64d8 DPR:$src)>; def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (VREV32d8 DPR:$src)>; def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(f64 (bitconvert (v4f16 DPR:$src))), (VREV64d16 DPR:$src)>; def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (VREV64d16 DPR:$src)>; def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (VREV64d8 DPR:$src)>; def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (VREV64d32 DPR:$src)>; def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (VREV32d16 DPR:$src)>; def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (VREV32d8 DPR:$src)>; // 128 bit conversions def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>; def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>; def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>; def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>; def : Pat<(v8f16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>; def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (VREV64q8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (VREV64q8 QPR:$src)>; def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (VREV32q8 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v8f16 QPR:$src))), (VREV32q16 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>; def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v8f16 QPR:$src))), (VREV64q16 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>; def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>; } // Use VLD1/VST1 + VREV for non-word-aligned v2f64 load/store on Big Endian def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)), (VREV64q8 (VLD1q8 addrmode6:$addr))>, Requires<[IsBE]>; def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr), (VST1q8 addrmode6:$addr, (VREV64q8 QPR:$value))>, Requires<[IsBE]>; def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)), (VREV64q16 (VLD1q16 addrmode6:$addr))>, Requires<[IsBE]>; def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr), (VST1q16 addrmode6:$addr, (VREV64q16 QPR:$value))>, Requires<[IsBE]>; // Fold extracting an element out of a v2i32 into a vfp register. def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))), (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>; // Vector lengthening move with load, matching extending loads. // extload, zextload and sextload for a standard lengthening load. Example: // Lengthen_Single<"8", "i16", "8"> = // Pat<(v8i16 (extloadvi8 addrmode6:$addr)) // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr, // (f64 (IMPLICIT_DEF)), (i32 0)))>; multiclass Lengthen_Single { let AddedComplexity = 10 in { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadvi" # SrcTy) addrmode6:$addr)), (!cast("VMOVLuv" # DestLanes # DestTy) (!cast("VLD1d" # SrcTy) addrmode6:$addr))>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadvi" # SrcTy) addrmode6:$addr)), (!cast("VMOVLuv" # DestLanes # DestTy) (!cast("VLD1d" # SrcTy) addrmode6:$addr))>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadvi" # SrcTy) addrmode6:$addr)), (!cast("VMOVLsv" # DestLanes # DestTy) (!cast("VLD1d" # SrcTy) addrmode6:$addr))>; } } // extload, zextload and sextload for a lengthening load which only uses // half the lanes available. Example: // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> = // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)), // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, // (f64 (IMPLICIT_DEF)), (i32 0))), // dsub_0)>; multiclass Lengthen_HalfSingle { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadv" # SrcTy) addrmode6oneL32:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # InsnLanes # InsnTy) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6oneL32:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # InsnLanes # InsnTy) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6oneL32:$addr)), (EXTRACT_SUBREG (!cast("VMOVLsv" # InsnLanes # InsnTy) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)>; } // The following class definition is basically a copy of the // Lengthen_HalfSingle definition above, however with an additional parameter // "RevLanes" to select the correct VREV32dXX instruction. This is to convert // data loaded by VLD1LN into proper vector format in big endian mode. multiclass Lengthen_HalfSingle_Big_Endian { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadv" # SrcTy) addrmode6oneL32:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # InsnLanes # InsnTy) (!cast("VREV32d" # RevLanes) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6oneL32:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # InsnLanes # InsnTy) (!cast("VREV32d" # RevLanes) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6oneL32:$addr)), (EXTRACT_SUBREG (!cast("VMOVLsv" # InsnLanes # InsnTy) (!cast("VREV32d" # RevLanes) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)>; } // extload, zextload and sextload for a lengthening load followed by another // lengthening load, to quadruple the initial length. // // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> = // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr)) // (EXTRACT_SUBREG (VMOVLuv4i32 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, // (f64 (IMPLICIT_DEF)), // (i32 0))), // dsub_0)), // dsub_0)>; multiclass Lengthen_Double { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadv" # SrcTy) addrmode6oneL32:$addr)), (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6oneL32:$addr)), (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6oneL32:$addr)), (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0))>; } // The following class definition is basically a copy of the // Lengthen_Double definition above, however with an additional parameter // "RevLanes" to select the correct VREV32dXX instruction. This is to convert // data loaded by VLD1LN into proper vector format in big endian mode. multiclass Lengthen_Double_Big_Endian { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadv" # SrcTy) addrmode6oneL32:$addr)), (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (!cast("VREV32d" # RevLanes) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6oneL32:$addr)), (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (!cast("VREV32d" # RevLanes) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6oneL32:$addr)), (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty) (!cast("VREV32d" # RevLanes) (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0))>; } // extload, zextload and sextload for a lengthening load followed by another // lengthening load, to quadruple the initial length, but which ends up only // requiring half the available lanes (a 64-bit outcome instead of a 128-bit). // // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> = // Pat<(v2i32 (extloadvi8 addrmode6:$addr)) // (EXTRACT_SUBREG (VMOVLuv4i32 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, // (f64 (IMPLICIT_DEF)), (i32 0))), // dsub_0)), // dsub_0)>; multiclass Lengthen_HalfDouble { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0)>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0)>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty) (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0)>; } // The following class definition is basically a copy of the // Lengthen_HalfDouble definition above, however with an additional VREV16d8 // instruction to convert data loaded by VLD1LN into proper vector format // in big endian mode. multiclass Lengthen_HalfDouble_Big_Endian { def _Any : Pat<(!cast("v" # DestLanes # DestTy) (!cast("extloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (!cast("VREV16d8") (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0)>; def _Z : Pat<(!cast("v" # DestLanes # DestTy) (!cast("zextloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLuv" # Insn1Lanes # Insn1Ty) (!cast("VREV16d8") (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0)>; def _S : Pat<(!cast("v" # DestLanes # DestTy) (!cast("sextloadv" # SrcTy) addrmode6:$addr)), (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn2Lanes # Insn2Ty) (EXTRACT_SUBREG (!cast("VMOVLsv" # Insn1Lanes # Insn1Ty) (!cast("VREV16d8") (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0)>; } defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64 let Predicates = [IsLE] in { defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32 // Double lengthening - v4i8 -> v4i16 -> v4i32 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">; // v2i8 -> v2i16 -> v2i32 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">; // v2i16 -> v2i32 -> v2i64 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">; } let Predicates = [IsBE] in { defm : Lengthen_HalfSingle_Big_Endian<"4", "i16", "i8", "8", "i16", "8">; // v4i8 -> v4i16 defm : Lengthen_HalfSingle_Big_Endian<"2", "i32", "i16", "4", "i32", "16">; // v2i16 -> v2i32 // Double lengthening - v4i8 -> v4i16 -> v4i32 defm : Lengthen_Double_Big_Endian<"4", "i32", "i8", "8", "i16", "4", "i32", "8">; // v2i8 -> v2i16 -> v2i32 defm : Lengthen_HalfDouble_Big_Endian<"2", "i32", "i8", "8", "i16", "4", "i32">; // v2i16 -> v2i32 -> v2i64 defm : Lengthen_Double_Big_Endian<"2", "i64", "i16", "4", "i32", "2", "i64", "16">; } // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64 let Predicates = [IsLE] in { def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)), (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)), (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)), (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; } // The following patterns are basically a copy of the patterns above, // however with an additional VREV16d instruction to convert data // loaded by VLD1LN into proper vector format in big endian mode. let Predicates = [IsBE] in { def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)), (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (!cast("VREV16d8") (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>; def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)), (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 (!cast("VREV16d8") (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>; def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)), (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 (!cast("VREV16d8") (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0)))), dsub_0)), dsub_0))>; } def : Pat<(v2i64 (concat_vectors DPR:$Dn, DPR:$Dm)), (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>; def : Pat<(v4i32 (concat_vectors DPR:$Dn, DPR:$Dm)), (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>; def : Pat<(v8i16 (concat_vectors DPR:$Dn, DPR:$Dm)), (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>; def : Pat<(v16i8 (concat_vectors DPR:$Dn, DPR:$Dm)), (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>; def : Pat<(v4f32 (concat_vectors DPR:$Dn, DPR:$Dm)), (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>; //===----------------------------------------------------------------------===// // Assembler aliases // def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn", (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>; def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn", (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>; // VAND/VBIC/VEOR/VORR accept but do not require a type suffix. defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm", (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm", (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm", (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm", (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; // ... two-operand aliases defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm", (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm", (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm", (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm", (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm", (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm", (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; // ... immediates def : NEONInstAlias<"vand${p}.i16 $Vd, $imm", (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>; def : NEONInstAlias<"vand${p}.i32 $Vd, $imm", (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>; def : NEONInstAlias<"vand${p}.i16 $Vd, $imm", (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>; def : NEONInstAlias<"vand${p}.i32 $Vd, $imm", (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>; // VLD1 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr", (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr", (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr", (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD1LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!", (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD1LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!", (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VLD1LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!", (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD1LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm", (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD1LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm", (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p)>; def VLD1LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm", (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; // VST1 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr", (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr", (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr", (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST1LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!", (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST1LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!", (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VST1LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!", (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST1LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm", (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VST1LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm", (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p)>; def VST1LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm", (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; // VLD2 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr", (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr", (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr", (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr", (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr", (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD2LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!", (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VLD2LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!", (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD2LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!", (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD2LNqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!", (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD2LNqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!", (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD2LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm", (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p)>; def VLD2LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm", (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; def VLD2LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm", (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD2LNqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm", (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; def VLD2LNqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm", (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; // VST2 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr", (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr", (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr", (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr", (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr", (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST2LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!", (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, pred:$p)>; def VST2LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!", (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST2LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!", (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST2LNqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!", (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST2LNqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!", (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST2LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm", (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr, rGPR:$Rm, pred:$p)>; def VST2LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm", (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; def VST2LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm", (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST2LNqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm", (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; def VST2LNqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm", (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; // VLD3 all-lanes pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPqWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, pred:$p)>; def VLD3DUPdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3DUPdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3DUPdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3DUPqWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3DUPqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3DUPqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr, rGPR:$Rm, pred:$p)>; // VLD3 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VLD3LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3LNqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VLD3LNqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; // VLD3 multiple structure pseudo-instructions. These need special handling for // the vector operands that the normal instructions don't yet model. // FIXME: Remove these when the register classes and instructions are updated. def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VLD3dWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VLD3dWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VLD3dWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VLD3qWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VLD3qWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VLD3qWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VLD3dWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD3dWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD3dWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD3qWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD3qWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD3qWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; // VST3 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, pred:$p)>; def VST3LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VST3LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VST3LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VST3LNqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; def VST3LNqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>; // VST3 multiple structure pseudo-instructions. These need special handling for // the vector operands that the normal instructions don't yet model. // FIXME: Remove these when the register classes and instructions are updated. def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VST3dWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VST3dWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VST3dWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>; def VST3qWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VST3qWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VST3qWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>; def VST3dWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST3dWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST3dWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeD:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST3qWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST3qWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST3qWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", (ins VecListThreeQ:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; // VLD4 all-lanes pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr, pred:$p)>; def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr, pred:$p)>; def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p)>; def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr, pred:$p)>; def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr, pred:$p)>; def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p)>; def VLD4DUPdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr, pred:$p)>; def VLD4DUPdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr, pred:$p)>; def VLD4DUPdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p)>; def VLD4DUPqWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr, pred:$p)>; def VLD4DUPqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr, pred:$p)>; def VLD4DUPqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr, pred:$p)>; def VLD4DUPdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr, rGPR:$Rm, pred:$p)>; def VLD4DUPdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr, rGPR:$Rm, pred:$p)>; def VLD4DUPdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>; def VLD4DUPqWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr, rGPR:$Rm, pred:$p)>; def VLD4DUPqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr, rGPR:$Rm, pred:$p)>; def VLD4DUPqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>; // VLD4 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VLD4LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VLD4LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD4LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VLD4LNqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VLD4LNqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VLD4LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; def VLD4LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD4LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>; def VLD4LNqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VLD4LNqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>; // VLD4 multiple structure pseudo-instructions. These need special handling for // the vector operands that the normal instructions don't yet model. // FIXME: Remove these when the register classes and instructions are updated. def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4dWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4dWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4dWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4qWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4qWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4qWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VLD4dWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VLD4dWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VLD4dWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VLD4qWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VLD4qWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VLD4qWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; // VST4 single-lane pseudo-instructions. These need special handling for // the lane index that an InstAlias can't handle, so we use these instead. def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VST4LNdWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, pred:$p)>; def VST4LNdWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST4LNdWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VST4LNqWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, pred:$p)>; def VST4LNqWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, pred:$p)>; def VST4LNdWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr, rGPR:$Rm, pred:$p)>; def VST4LNdWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST4LNdWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>; def VST4LNqWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr, rGPR:$Rm, pred:$p)>; def VST4LNqWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>; // VST4 multiple structure pseudo-instructions. These need special handling for // the vector operands that the normal instructions don't yet model. // FIXME: Remove these when the register classes and instructions are updated. def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4dWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4dWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4dWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4qWB_fixed_Asm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4qWB_fixed_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4qWB_fixed_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, pred:$p)>; def VST4dWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VST4dWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VST4dWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourD:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VST4qWB_register_Asm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VST4qWB_register_Asm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; def VST4qWB_register_Asm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", (ins VecListFourQ:$list, addrmode6align64or128or256:$addr, rGPR:$Rm, pred:$p)>; // VMOV/VMVN takes an optional datatype suffix defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm", (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm", (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>; // VCLT (register) is an assembler alias for VCGT w/ the operands reversed. // D-register versions. def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm", (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm", (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm", (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm", (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm", (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm", (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm", (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; let Predicates = [HasNEON, HasFullFP16] in def : NEONInstAlias<"vcle${p}.f16 $Dd, $Dn, $Dm", (VCGEhd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; // Q-register versions. def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm", (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm", (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm", (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm", (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm", (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm", (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm", (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; let Predicates = [HasNEON, HasFullFP16] in def : NEONInstAlias<"vcle${p}.f16 $Qd, $Qn, $Qm", (VCGEhq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; // VCLT (register) is an assembler alias for VCGT w/ the operands reversed. // D-register versions. def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm", (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm", (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm", (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm", (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm", (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm", (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm", (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; let Predicates = [HasNEON, HasFullFP16] in def : NEONInstAlias<"vclt${p}.f16 $Dd, $Dn, $Dm", (VCGThd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; // Q-register versions. def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm", (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm", (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm", (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm", (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm", (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm", (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm", (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; let Predicates = [HasNEON, HasFullFP16] in def : NEONInstAlias<"vclt${p}.f16 $Qd, $Qn, $Qm", (VCGThq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; // VSWP allows, but does not require, a type suffix. defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>; // VBIF, VBIT, and VBSL allow, but do not require, a type suffix. defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm", (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm", (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm", (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm", (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm", (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm", (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; // "vmov Rd, #-imm" can be handled via "vmvn". def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm", (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm", (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; // 'gas' compatibility aliases for quad-word instructions. Strictly speaking, // these should restrict to just the Q register variants, but the register // classes are enough to match correctly regardless, so we keep it simple // and just use MnemonicAlias. def : NEONMnemonicAlias<"vbicq", "vbic">; def : NEONMnemonicAlias<"vandq", "vand">; def : NEONMnemonicAlias<"veorq", "veor">; def : NEONMnemonicAlias<"vorrq", "vorr">; def : NEONMnemonicAlias<"vmovq", "vmov">; def : NEONMnemonicAlias<"vmvnq", "vmvn">; // Explicit versions for floating point so that the FPImm variants get // handled early. The parser gets confused otherwise. def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">; def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">; def : NEONMnemonicAlias<"vaddq", "vadd">; def : NEONMnemonicAlias<"vsubq", "vsub">; def : NEONMnemonicAlias<"vminq", "vmin">; def : NEONMnemonicAlias<"vmaxq", "vmax">; def : NEONMnemonicAlias<"vmulq", "vmul">; def : NEONMnemonicAlias<"vabsq", "vabs">; def : NEONMnemonicAlias<"vshlq", "vshl">; def : NEONMnemonicAlias<"vshrq", "vshr">; def : NEONMnemonicAlias<"vcvtq", "vcvt">; def : NEONMnemonicAlias<"vcleq", "vcle">; def : NEONMnemonicAlias<"vceqq", "vceq">; def : NEONMnemonicAlias<"vzipq", "vzip">; def : NEONMnemonicAlias<"vswpq", "vswp">; def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">; def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">; // Alias for loading floating point immediates that aren't representable // using the vmov.f32 encoding but the bitpattern is representable using // the .i32 encoding. def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm", (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>; def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm", (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>; capstone-sys-0.15.0/capstone/suite/synctools/tablegen/ARM/ARMInstrThumb.td000064400000000000000000001765600072674642500246000ustar 00000000000000//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file describes the Thumb instruction set. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Thumb specific DAG Nodes. // def imm_sr_XFORM: SDNodeXFormgetZExtValue(); return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); }]>; def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; } def imm_sr : Operand, PatLeaf<(imm), [{ uint64_t Imm = N->getZExtValue(); return Imm > 0 && Imm <= 32; }], imm_sr_XFORM> { let PrintMethod = "printThumbSRImm"; let ParserMatchClass = ThumbSRImmAsmOperand; } def imm0_7_neg : PatLeaf<(i32 imm), [{ return (uint32_t)-N->getZExtValue() < 8; }], imm_neg_XFORM>; def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; } def mod_imm1_7_neg : Operand, PatLeaf<(imm), [{ unsigned Value = -(unsigned)N->getZExtValue(); return 0 < Value && Value < 8; }], imm_neg_XFORM> { let ParserMatchClass = ThumbModImmNeg1_7AsmOperand; } def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; } def mod_imm8_255_neg : Operand, PatLeaf<(imm), [{ unsigned Value = -(unsigned)N->getZExtValue(); return 7 < Value && Value < 256; }], imm_neg_XFORM> { let ParserMatchClass = ThumbModImmNeg8_255AsmOperand; } def imm0_255_comp : PatLeaf<(i32 imm), [{ return ~((uint32_t)N->getZExtValue()) < 256; }]>; def imm8_255_neg : PatLeaf<(i32 imm), [{ unsigned Val = -N->getZExtValue(); return Val >= 8 && Val < 256; }], imm_neg_XFORM>; // Break imm's up into two pieces: an immediate + a left shift. This uses // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt // to get the val/shift pieces. def thumb_immshifted : PatLeaf<(imm), [{ return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); }]>; def thumb_immshifted_val : SDNodeXFormgetZExtValue()); return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); }]>; def thumb_immshifted_shamt : SDNodeXFormgetZExtValue()); return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); }]>; def imm256_510 : ImmLeaf= 256 && Imm < 511; }]>; def thumb_imm256_510_addend : SDNodeXFormgetTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32); }]>; // Scaled 4 immediate. def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } def t_imm0_1020s4 : Operand { let PrintMethod = "printThumbS4ImmOperand"; let ParserMatchClass = t_imm0_1020s4_asmoperand; let OperandType = "OPERAND_IMMEDIATE"; } def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } def t_imm0_508s4 : Operand { let PrintMethod = "printThumbS4ImmOperand"; let ParserMatchClass = t_imm0_508s4_asmoperand; let OperandType = "OPERAND_IMMEDIATE"; } // Alias use only, so no printer is necessary. def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } def t_imm0_508s4_neg : Operand { let ParserMatchClass = t_imm0_508s4_neg_asmoperand; let OperandType = "OPERAND_IMMEDIATE"; } // Define Thumb specific addressing modes. // unsigned 8-bit, 2-scaled memory offset class OperandUnsignedOffset_b8s2 : AsmOperandClass { let Name = "UnsignedOffset_b8s2"; let PredicateMethod = "isUnsignedOffset<8, 2>"; } def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; // thumb style PC relative operand. signed, 8 bits magnitude, // two bits shift. can be represented as either [pc, #imm], #imm, // or relocatable expression... def ThumbMemPC : AsmOperandClass { let Name = "ThumbMemPC"; } let OperandType = "OPERAND_PCREL" in { def t_brtarget : Operand { let EncoderMethod = "getThumbBRTargetOpValue"; let DecoderMethod = "DecodeThumbBROperand"; } // ADR instruction labels. def t_adrlabel : Operand { let EncoderMethod = "getThumbAdrLabelOpValue"; let PrintMethod = "printAdrLabelOperand<2>"; let ParserMatchClass = UnsignedOffset_b8s2; } def thumb_br_target : Operand { let ParserMatchClass = ThumbBranchTarget; let EncoderMethod = "getThumbBranchTargetOpValue"; let OperandType = "OPERAND_PCREL"; } def thumb_bl_target : Operand { let ParserMatchClass = ThumbBranchTarget; let EncoderMethod = "getThumbBLTargetOpValue"; let DecoderMethod = "DecodeThumbBLTargetOperand"; } // Target for BLX *from* thumb mode. def thumb_blx_target : Operand { let ParserMatchClass = ARMBranchTarget; let EncoderMethod = "getThumbBLXTargetOpValue"; let DecoderMethod = "DecodeThumbBLXOffset"; } def thumb_bcc_target : Operand { let ParserMatchClass = ThumbBranchTarget; let EncoderMethod = "getThumbBCCTargetOpValue"; let DecoderMethod = "DecodeThumbBCCTargetOperand"; } def thumb_cb_target : Operand { let ParserMatchClass = ThumbBranchTarget; let EncoderMethod = "getThumbCBTargetOpValue"; let DecoderMethod = "DecodeThumbCmpBROperand"; } // t_addrmode_pc :=